Patent Publication Number: US-6037887-A

Title: Programmable gain for delta sigma analog-to-digital converter

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to delta sigma converters, particularly to those useful in analog-to-digital converters, and more particularly to such delta sigma modulators which have programmable gain. 
     By way of background, delta sigma modulators are commonly used in analog-to-digital converters. A delta sigma modulator for use in analog-to-digital converters is described in U.S. Pat. No. 5,134,401 (McCartney et al.) entitled &#34;DELTA SIGMA MODULATOR HAVING PROGRAMMABLE GAIN/ATTENUATION&#34;, issued Jul. 28, 1992 and incorporated herein by reference. The McCartney et al. patent is the closest prior art presently known to the inventors. It discloses a delta sigma modulator in which the gain is programmable by selectively controlling the rate of sampling of an analog input V IN  relative to the rate of sampling a feedback reference V REF . U.S. Pat. No. 4,588,981 (Senn), which is discussed at length in the McCartney et al. patent, discloses an analog-to-digital converter using a delta sigma modulator. 
     FIG. 3 of the McCartney et al. patent is included herein as FIG. 4, labeled &#34;PRIOR ART&#34;. In the device shown in prior art FIG. 4, the digital output 111 of buffer 110 of a delta sigma modulator 81 is a digital representation of the analog input signal V IN . The &#34;gain&#34; of the delta sigma modulator 81 can be thought of as the ratio between the filtered value of an output signal on conductor 111 and the value of the analog input voltage V IN . The gain also can be thought of as the ratio of the amount of charge transferred from the input sampling capacitor C IN  to integration capacitor C13 during a comparator decision cycle to the amount of charge transferred from the feedback reference capacitor C REF  to integration capacitor C13 during the comparator decision cycle. 
     The gain is increased for the prior art delta sigma modulator 81 shown in prior art FIG. 4 by increasing the amount of charge transferred onto integrating capacitor C13 as a result of sampling V IN  onto capacitor C IN  relative to the amount of charge transferred onto integrating capacitor C 13  as a result of sampling a reference voltage V REF  onto sampling capacitor C REF . 
     Increasing the &#34;gain&#34; of the delta sigma modulator can be understood by recognizing that the output buffer can contain a &#34;maximum&#34; number, which can be thought of as a &#34;full scale&#34; value. It is desirable to be able to convert a first range of relatively small values of V IN  to corresponding digital numbers which represent the value of V IN . The largest such digital number, which is the &#34;full scale&#34; value of the output buffer 110, should represent the maximum value of V IN  in the first range. It also is desirable to be able to convert a second range (and additional ranges) of relatively larger values of V IN  to corresponding digital numbers. The largest digital number of each range is the same &#34;full scale&#34; value of the output buffer and corresponds to the maximum value of V IN  for that range. Therefore, in order to obtain the desirable correspondence between various maximum values of V IN  (for various ranges) and the same full scale digital number of output buffer 110, it is necessary to be able to adjust the &#34;gain&#34; of delta sigma modulator 81 so that the largest expected value of V IN  corresponds to the full scale digital value of output buffer 110. 
     The gain of the prior art delta sigma modulator 81 shown in prior art FIG. 4 is adjusted by sampling V IN  onto sampling capacitor C IN  and then transferring its charge onto integrating capacitor C13 at a different rate than the rate of sampling V REF  onto sampling capacitor C REF  and transferring its charge onto integrating capacitor C13. 
     The delta sigma modulator 81 shown in prior art FIG. 4 includes a programmable control unit 112 which can be controlled by the user to set the gain of the delta sigma modulator 81. This is accomplished by setting the ratio of the sampling rate of the analog input V IN  relative to the sampling rate of the reference voltage V REF . The McCartney et al. patent explains that changing the gain of the delta sigma modulator of the above mentioned Senn patent is inconvenient because it requires exchanging sampling capacitors. To avoid that shortcoming, McCartney et al. adjust the gain of the delta sigma modulator by adjusting the ratio of the rate at which the analog input V IN  is sampled onto the integrating capacitor C13 relative to the rate at which the reference voltage V REF  is sampled onto integration capacitor C13. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the invention to provide a delta sigma modulator in which the gain is programmable independently of the ratio of the rates of sampling the analog input voltage and the feedback reference voltage. 
     It is another object of the invention to provide a delta sigma modulator in which the gain is programmable independently of the ratio of the rates of sampling the analog input voltage and the feedback reference voltage and in which the dynamic range or signal-to-noise ratio is not unduly compromised. 
     It is another object of the invention to provide a delta sigma modulator or delta sigma analog-to-digital converter in which offset errors and other errors are easily corrected. 
     It is another object of the invention to provide a delta sigma modulator or delta sigma analog-to-digital converter and technique providing highly linear gain adjustment. 
     It is another object of the invention to avoid loss of dynamic range or signal-to-noise ratio of a delta sigma modulator or delta sigma analog-to-digital converter as a result of decreasing the reference feedback voltage sampling capacitance thereof. 
     It is another object of the invention to avoid loss of bandwidth of a delta sigma modulator or delta sigma analog-to-digital converter as a result of decreasing the reference feedback voltage sampling capacitor thereof. 
     Briefly described, and in accordance with one embodiment thereof, the invention provides a programmable gain delta sigma analog-to-digital converter including an analog input terminal receiving an analog input voltage, a charge summing conductor, a first capacitive switching circuit including an input sampling capacitor, first sampling switch circuitry coupled to the analog input terminal and the input sampling capacitor to charge the input sampling capacitor to the input voltage, and second capacitive switching circuitry coupled to the input sampling capacitor and the charge summing conductor to transfer charge from the input sampling capacitor to the charge summing conductor. An integrator including an amplifier and an integrating capacitor is coupled between the charge summing conductor and a comparator that includes a first input coupled to the output of the amplifier and a second input coupled to receive a fixed reference voltage. A digital filter is coupled to receive a stream of digital pulses from an output of the comparator and adapted to produce a digital number that precisely represents the analog input voltage. A second capacitive switching circuit includes a plurality of reference sampling capacitors, third switching circuitry selectively coupling a feedback reference voltage to the reference sampling capacitors, respectively, to selectively charge the reference sampling capacitors to the feedback reference voltage, and fourth switching circuitry selectively coupling the reference sampling capacitors, respectively, to the charge summing conductor. Programmable gain control circuitry is coupled to the output of the comparator for selectively controlling the number of reference sampling capacitors coupled to the feedback reference voltage generally proportionally to the inverse of a preselected gain. In the described embodiment, the programmable gain control circuitry includes sampling rate control circuitry adapted to increase the common sampling rate of the first and second capacitive switching circuits generally proportionally to the preselected gain. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a programmable gain delta sigma analog-to-digital converter of the present invention having a single ended input. 
     FIG. 2 is a schematic diagram of a differential input programmable gain delta sigma analog-to-digital converter of the present invention. 
     FIG. 3A is a timing diagram showing the waveforms of the clock signals applied to the delta sigma analog-to-digital converter of FIG. 1. 
     FIG. 3B is a timing diagram showing the waveforms of the clock signals applied to the delta sigma analog-to-digital converter of FIG. 2. 
     FIG. 4 is a schematic diagram of a prior art programmable gain delta sigma analog-to-digital converter. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, delta sigma modulator 81A includes a switched capacitor sampling circuit 83 having an input conductor to which the analog input signal V IN  is applied. (Note that where convenient the same or similar reference numerals are used to designate similar or corresponding parts in FIGS. 1 and 2 as in prior art FIG. 4.) A switch 84 controlled by φ 1  &#39; couples V IN  to one terminal of input sampling capacitor C IN  and to one terminal of a switch 88 controlled by φ 2  &#39;. Note that the timing diagram of FIG. 3A shows the waveforms of the various clock signals in FIG. 1. C IN  can be 12 picofarads. The other terminal of input sampling capacitor C IN  is connected to one terminal of a switch 96 controlled by φ 2  and one terminal of a switch 92 controlled by φ 1 . The second terminals of switches 88 and 92 are connected to ground. The second terminal of switch 96 is connected by a charge summing conductor 100 to the inverting input of operational amplifier 102, which, with integrating capacitor C 13  coupled between its output 109 and inverting input, constitutes an integrator 104. The non-inverting input of operational amplifier 102 is connected to ground. 
     To sample V IN , φ 2  and φ 2  &#39; (FIG. 3) are set to low levels to open switches 88 and 96, and φ 1  and φ 1  &#39; are set to high levels to close switches 84 and 92. C IN  then is charged to V IN  volts, i.e., V IN  is &#34;sampled&#34;. To &#34;transfer&#34; the resulting sampled charge between C IN  and integrating capacitor C 13 , switches 84 and 92 are opened, and switches 88 and 96 are closed so the sampled charge is transferred between C IN  and C 13  via charge summing conductor 100. 
     Switched capacitor circuit 85A functions to sample a feedback reference voltage and transfer the resulting sampled feedback charge between a selected feedback reference capacitance and integrating capacitor C13 according to the output decision of comparator 108. Each of switches 86-1,2 . . . n has a first terminal connected to a feedback reference voltage V REF , where, in the described embodiment, n is equal to 16 and also is equal to the maximum selectable gain of delta sigma analog-to-digital converter 81A. A second terminal of each of switches 86-1,2 . . . n is connected to a first terminal of a corresponding feedback reference voltage sampling capacitor C REF1 ,2 . . . n and also to a first terminal of a corresponding switch 90-1,2 . . . n. The second terminals of switches 90-1,2 . . . n are connected to ground. The first terminals of capacitors C REF1 , . . . n are connected to the first terminals of switches 99-1,2 . . . n, respectively. The second terminals of switches 99-1,2 . . . n are connected to charge summing conductor 100. The second terminals of feedback reference voltage sampling capacitors C REF1 ,1 . . . n are connected to the first terminals of switches 94-1,2 . . . n, respectively, and also to first terminals of switches 98-1,2 . . . n, respectively. The second terminals of switches 94-1,2 . . . n are connected to ground. The second terminals of switches 98-1,2 . . . n are connected to charge summing conductor 100. Switches 86-1,2 . . . n are controlled by φ 1  &#39;. Switches 90-1,2 . . . n are controlled by Φ 21 ,2 . . . n, respectively. Switches 94-1,2 . . . n are controlled by φ 1  or ψ&#39; 21 ,2 . . . n, respectively, depending on whether the output Q of comparator 108 is a &#34;1&#34; (high) or a &#34;0&#34; (low), as indicated in the timing diagram of FIG. 3A. Switches 98-1,2 . . . n are controlled by Φ 21 ,2 . . . n, respectively. Switches 99-1,2 . . . n are controlled by ψ 21 ,2 . . . n, respectively. (The above mentioned switches and the switches in subsequently described FIG. 2 all can be MOS transistors.) 
     Thus, the various capacitors C REF1 ,2 . . . n can be selectively connected in parallel to provide a capacitance C REF (TOTAL) that can have various values between C R  to n times C R , where C R  is the capacitance of each of capacitors C REF1 ,2 . . . n. In the described embodiment, C R  can be 1 picofarad. The number n of such capacitors can be chosen to be equal to the highest gain desired for delta sigma modulator 81A. 
     The output 109 of integrator 104 is connected to the input of an analog filter 106. The output of filter 106 is connected to the non-inverting input of a comparator 108, the inverting input of which is connected to ground. The output Q of comparator 108 supplies a sequence of digital pulses (which represent the average amplitude of V IN ) to the input of a digital buffer 110. The output of buffer 110 is applied to the input of a digital post-filter 25 which performs the function of filtering the digital stream of pulses on the output 111 of buffer 110 to thereby provide a digital number D OUT  that is a precise digital representation of V IN . 
     The output Q of comparator 108 also is applied to an input of a programmable control circuit 112A that performs the function of supplying the various clock signals applied to operate V IN  sampling circuit 83 and V REF  sampling circuit 85A. The timing diagram of FIG. 3A shows the waveforms of the various above mentioned clock signals which effectuate the sampling and charge-transferring functions so as to produce the selected gain. The desired gain of delta sigma modulator 81A is provided by the user as a gain adjustment input 17 to gain control register 147A in programmable control circuit 112A. Various implementations of programmable control circuit 112A and gain control register 147A can be easily accomplished by one skilled in the art, and therefore are not described in detail. 
     The gain of a delta sigma modulator is proportional to the expression ##EQU1## where C IN  is the capacitance of the analog input sampling capacitor and C REF (TOTAL) is the selected reference feedback capacitance, as generally explained in U.S. Pat. No. 4,851,841 (Sooch) entitled &#34;GAIN SCALING OF OVERSAMPLED ANALOG-TO-DIGITAL CONVERTERS&#34; and the article &#34;Design Methodology for ΣΔM&#34; by Agrawal and Shenoi, IEEE Transactions on Communications, vol. COM-31, pp. 360-370, March 1983. Note that the above expression assumes that V IN  and V REF  are sampled onto C IN  and C REF , respectively, at exactly the same rate or frequency. The gain of the delta sigma analog-to-digital converter is the same as the gain of the delta sigma modulator portion thereof if the gain of the following portions of the analog-to-digital converter following the delta sigma modulator portion is unity. 
     According to the present invention, V IN  and V REF  are sampled by the corresponding sampling capacitances C IN  and C REF (TOTAL) onto the integrating capacitor C13 at exactly the same rate. The gain is selected or adjusted by changing the effective feedback reference sampling capacitance C REF (TOTAL) that is charged during sampling of V REF  and then transferred to integrating capacitor C13. This is in direct contrast to changing the sampling rate of C REF  relative to the rate of sampling V IN  as in the closest prior art (the above mentioned McCartney et al. patent). The &#34;effective&#34; feedback reference sampling capacitance C REF (TOTAL) is selected by operating the above described switches in capacitive switching circuit 85A to, in effect, connect a preselected number of reference feedback capacitors C REF1 ,2 . . . n in parallel or sequentially sample them individually in order to obtain a selected &#34;effective&#34; value of C REF (TOTAL) and hence a corresponding selected value of gain between 1 and n. 
     Specifically, in FIG. 1, the gain of delta sigma analog-to-digital converter 81A is selected by causing programmable control unit 112A to operatively sample V REF  and transfer the resulting sampled charge between integrating capacitor 13 and a selected number of equal reference feedback capacitors C REF , C REF2  . . . C REFn . In the preferred embodiment, each of the individual feedback reference sampling capacitors C REF1 ,2 . . . n has the same capacitance, 1 picofarad. For the lowest selectable delta sigma modulator gain of unity, all of C REF1 ,2 . . . n are &#34;operatively&#34; connected in parallel during sampling of V REF . For the highest selectable value (n) of gain, only one of C REF1 ,2 . . . n is operatively connected to sample V REF . 
     To increase the gain of delta sigma analog-to-digital converter 81A, programmable control circuit 112A is operated (in response to gain information entered into control register 147A) to control the above switches so as to cause the ratio (C IN )/(C REF (TOTAL)) to have a particular value. In this expression, C REF (TOTAL) is equal to the total capacitance of all of the capacitors C REF1 ,2 . . . n which operatively sample V REF  and transfer the resulting sampled charge between the selected capacitors C REF1 ,2 . . . n and integrating capacitor C13. The ratio of the capacitance of input sampling capacitor C IN  to the net or total effective reference sampling capacitance C REF (TOTAL) including the selected ones of C REF1 , C REF2  . . . C REFn  is equal to the gain of delta sigma modulator of analog-to-digital converter 81A. 
     Note that programmable control circuit 112A of the present invention never adjusts the relative sampling rates of sampling circuits 83 and 85A. Only the relative capacitances of the input sampling capacitor C IN  and the value of C REF (TOTAL) are adjusted. In contrast, the ratio of the capacitances of sampling capacitors C IN  and C REF  in prior art FIG. 4 is constant, but the relative sampling rate of sampling circuits 85 to the sampling rate of circuit 83 is adjusted to change the gain of delta sigma modulator 81. 
     Those skilled in the art will understand that decreasing C REF (TOTAL) to increase the gain of delta sigma analog-to-digital converter 81A results in a loss of its dynamic range. This occurs because the reference feedback signal includes a charge error component that is equal to ##EQU2## and that charge error component increases more rapidly with decreasing C REF (TOTAL) than the other components of the reference feedback signal. Consequently, the signal-to-noise ratio, i.e., the dynamic range, of the delta sigma analog-to-digital converter is degraded when the gain thereof is increased by reducing C REF (TOTAL). 
     Also, those skilled in the art will understand that changing C REF (TOTAL) alters the frequency response characteristics of delta sigma modulator 81A, because changing the gain of delta sigma modulator 81A as described above changes the slope of its gain-bandwidth curve and the location of the unity-gain point thereof, just as an amplifier has a gain-bandwidth product that &#34;rolls off&#34; at higher frequencies. 
     In accordance with one aspect of the invention, the common sampling rate used for both sampling circuits 83 and 85A in FIG. 1 is increased proportionally to the selected gain of delta sigma modulator 81A. In FIG. 1, timing generator 18 adjusts the frequency of a sampling rate signal 18A proportionally to the gain adjustment signal on conductor 17 in accordance with subsequently described Table 1. This causes programmable control circuit 112A to increase the sampling rate of circuits 83 and 85A. (One skilled in the art can readily provide various suitable implementations of timing generator 18 to produce signal 18A, so the details are omitted.) As subsequently explained, this &#34;recovers&#34; some of the &#34;dynamic range&#34; or signal-to-noise ratio of delta sigma analog-to-digital converter 81A that otherwise is lost as a result of decreasing C REF (TOTAL) to increase the gain. 
     Note that such increasing of the common sampling frequency of V IN  and V REF  does not affect the gain of the delta sigma modulator of delta sigma analog-to-digital converter 81A (or subsequently described delta sigma analog-to-digital converter 81B), but does result in more sampled charge being transferred to integrating capacitor C 13 . This results in more effective use of the &#34;full scale&#34; sampling charge accumulated on integrating capacitor C 13  to increase the signal levels of the output of amplifier 102 relative to various noise sources, such as the above mentioned kT/C REF (TOTAL) noise, flicker noise, etc., which occur in integration amplifier 102, filter 106, and comparator 108. Consequently, the signal-to-noise ratio of delta sigma analog-to-digital converter 81A is improved. 
     Also, those skilled in the art will realize that increasing the rate of sampling by circuits 83 and 85A reduces the kT/C noise normally attributed to C IN  by √N, where N is the factor by which the sampling rate is increased. 
     A primary offset error for delta sigma modulator 81A is produced by charge injection errors in both the input sampling circuit 83 and the feedback reference voltage sampling circuit 85A. The above described technique for increasing the common sampling frequency of C IN  and C REF (TOTAL) causes such charge injection errors to be proportional to the gain selected for delta sigma modulator 81A. Such proportionality allows the above mentioned offset error to be easily predicted and corrected as a linear function of the selected gain by a subsequent calibration function. In contrast, the approach of prior art FIG. 4 adjusts the gain by changing the ratio of the input and feedback reference sampling frequencies. This causes the sum of the charge injection errors of the sampling circuits 83a and 85a in prior art FIG. 4 to vary in a non-linear fashion with respect to the selected gain. This makes a calibration correction of the delta sigma modulator offset error more difficult. 
     Finally, the technique of increasing the common sampling frequency proportionally to the selected gain not only improves the signal-to-noise ratio and improves the bandwidth characteristics of delta sigma modulator 81A, it also improves the feedback loop stability in delta sigma modulator 81A, by causing the feedback transfer function to remain constant. 
     The above described increasing of the common sampling rate of C IN  and C REF (TOTAL) also &#34;dynamically cancels&#34; mismatch errors of the individual, equal-value capacitors C REF1 ,2 . . . n if the different individual ones of C REF1 ,2 . . . n selected to contribute to C REF (TOTAL) are consecutively sampled during a particular comparator decision cycle. This technique tends to average the capacitance mismatch errors over the comparator decision cycle. For example, if the maximum value of gain (n) is selected, the corresponding minimum value of C REF (TOTAL) is equal to C R , which in the described prototype is 1 picofarad. To recover dynamic range lost by decreasing C REF (TOTAL), each of C REF1 ,2 . . . n is sampled once during each comparator decision cycle instead of sampling C REF1  n times. Consequently, the mismatches between C REF1 ,2 . . . n are averaged. 
     Digital filter 25 can be readily adapted by those skilled in the art to &#34;notch out&#34;, i.e., average, the effects of such capacitive mismatch errors. That is, instead of averaging the capacitive mismatches during one comparator decision cycle the capacitors could be selected so as to average out the mismatches at some other frequency associated with operation of the digital filter. For example, the oversampling of the various C REF1 ,2 . . . n can occur every other (or even every third, etc.) comparator decision cycle rather than every cycle; in any case, the capacitive mismatch errors can be readily averaged or &#34;notched out&#34; by digital filter 25. 
     Referring to FIG. 2, delta sigma analog-to-digital converter 81B shows the presently preferred embodiment of the invention, in which a differential analog input signal ΔV IN , equal to the difference between V IN   +   and V IN   - , is applied between the input terminals. The basic techniques described above for providing programmable gain and recovery of dynamic range are essentially the same for the circuit of FIG. 2 as for the circuit of FIG. 1. However, the switched capacitor circuit 83B for sampling ΔV IN  of FIG. 2 includes two equal sampling capacitors C IN  and C IN  &#39; (which may be 12 picofarads), two corresponding charge transfer switches 33 and 33&#39;, and two corresponding charge summing conductors 100A and 100B connected to the (-) and (+) inputs of integrator operational amplifier 102, respectively. 
     Switch 30 couples V IN   +   to one terminal of C IN  and one terminal of switch 31. The other terminal of switch 31 is connected to a bias voltage V B , which may be ground. The other terminal of C IN  is connected to one terminal of switch 32 and one terminal of transfer switch 33, the other terminal of which is connected to charge summing conductor 100A. Similarly, switch 30&#39; couples V IN   -   to one terminal of C IN  &#39; and one terminal of switch 31&#39;. The other terminal of 31&#39; is connected to V B . A second terminal of C IN  &#39; is connected to a second terminal of switch 32 and to one terminal of transfer switch 33&#39;. The other terminal of transfer switch 33&#39; is connected to charge summing conductor 100B. Switches 30 and 30&#39; are controlled by φ 2  &#39;, as shown, and switches 31 and 31&#39; are controlled by φ 2  &#39;. Switch 32 is controlled by φ 1 , and switches 33 and 33&#39; are controlled by φ 2 , as shown. (Note that all of the clock signals in FIG. 2 are shown in the timing diagram of FIG. 3B and are generated by programmable control circuit 112B. Also note that in FIG. 3B, φ 11  &#39;, φ 12  &#39; and φ 13  &#39; are shown; for convenience, φ 14 ,15 . . . 1n &#39; are omitted, but continue the &#34;unstaggered&#34; pattern of pulses shown for φ 11  &#39;, φ 12  &#39; and φ 13  &#39;. A similar comment is applicable to φ 24 ,25 . . . 2n &#39;, which, for convenience also are not shown.) 
     Programmable feedback reference capacitor circuit 10 is coupled to charge summing conductor 100A by switch 34, and to charge summing conductor 100B by switch 29. Programmable feedback reference capacitor circuit 10&#39; is coupled to charge summing conductor 100B by switch 34&#39; and to charge summing conductor 100A by switch 29&#39;. Sampling capacitor C IN  is coupled by switch 33 to charge summing conductor 100A, and sampling capacitor C IN  &#39; is coupled by switch 33&#39; to charge summing conductor 100B. Charge summing conductor 100A is connected to the (-) input of operational amplifier 102 and to one terminal of integrating capacitor C 13 , the other terminal of which is connected to the (+) output of operational amplifier 102. Charge summing conductor 100B is connected to the (+) input of operational amplifier 102 and to one terminal of integrating capacitor C 13  &#39;, the other terminal of which is connected to the (-) output of operational amplifier 102. 
     Switched reference feedback capacitor circuit 10 includes switch 20 coupling the left terminals of 1 picofarad capacitors C REF1 ,2 . . . n to V B  which may be +2.5 volts. The right terminals of C REF1 ,2 . . . n are coupled by switches 41-1,2 . . . n to V REF , and by switches 39-1,2 . . . n, respectively, to ground. Similarly, switched reference feedback capacitor circuit 10&#39; includes switch 21 coupling the left terminals of 1 picofarad capacitors C REF1 ,2 . . . n &#39; to V B . The right terminals of C REF1 ,2 . . . n &#39; are coupled by switches 42-1,2 . . . n to V REF  and by switches 40-1,2 . . . n, respectively, to ground. 
     An analog filter 106B that corresponds to filter 106 in FIG. 1 includes a second switched capacitor sampling circuit, a third switched capacitor circuit, and a second integrator. The second switched capacitor circuit includes switches 35,35&#39;,36,36&#39;,37,37&#39;,38 and 38&#39;, and sampling capacitors C INN  and C INN  &#39; coupled as shown between the outputs of operational amplifier 102 and the inputs of operational amplifier 102A. The third switched capacitor circuit includes switches 45,45&#39;,46,46&#39;,47,47&#39;,48,48&#39;,49 and 49&#39;, and capacitors C REF3  and C REF3  &#39; coupled as shown between V REF  and the inputs of operational amplifier 102A. The second integrator includes integrating capacitors C 14  and C 14  &#39; and operational amplifier 102A, the + and - outputs of which are connected to the - and + inputs, respectively, of comparator 108. The output COUT of comparator 108 is coupled to the input of digital filter 25 and to an input of program control circuit 112B. Programmable control circuit 112B, timing generator 18, and digital filter 25 are structurally similar to and are similarly connected to the corresponding elements in the embodiment of FIG. 1. FIG. 3B shows the timing diagram of the various clock signals applied to the switches as indicated in FIG. 2. 
     Table 1 below shows the sampling frequency f s  versus the analog-to-digital converter gain for the circuits of FIGS. 1 and 2. 
     
                       TABLE 1                                                     
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Analog      Input and feedback                                            
to-         Capacitor Sampling                                            
Digital     frequency relative                                            
Converter   to Comparator                                                 
Gain        Decision Frequency f.sub.s                                    
                          C.sub.REF(TOTAL)                                
______________________________________                                    
1           1xf.sub.s     16pf                                            
2           2xf.sub.s     8pf                                             
4           4xf.sub.s     4pf                                             
8           8xf.sub.s     2pf                                             
16          16xf.sub.s    1pf                                             
______________________________________                                    
 
    
     FIG. 2 describes a circuit which may be used for single power supply operation. Note that in capacitive switching circuit 10 (which always functions to &#34;take&#34; charge from integrating capacitor C 13  during a transfer cycle), all of C REF1 ,2 . . . n in capacitive switching circuit 10 are charged to the difference between V B  and V REF ) during the reference sampling phase φ 1  &#39;. During the next transfer phase, i.e., during φ 2i , the selected one of switches 39-1,2 . . . n connects the right terminal of the selected C REF1 ,2 . . . n to ground. None of the right terminals thereof can be &#34;pulled&#34; below ground by transient signals occurring on conductor 10 while turning on any of switches 39-1,2 . . . n, which are n channel MOSFETs. Consequently, none of the other switches (MOSFETs) 39-1,2 . . . n can be accidentally turned on by an &#34;electrically floating&#34; source or drain electrode that has been shifted below ground. Therefore, no loss of sampled charge through such an accidently turned on MOSFET or junction diode can occur. This, of course, would be undesirable because it would cause a loss of linearity of the analog-to-digital converter. In capacitive switching circuit 10&#39;, which always operates to &#34;give&#34; charge to integrating capacitor C 13  &#39; during a transfer cycle, always charges only the &#34;selected&#34; C REF1 ,2 . . . n to V B  volts by connecting its left terminal to V B  and its right terminal to ground during φ 1  and φ&#39; 1i . There is no possibility that any electrically floating nodes of switches 42-1,2 . . . n can go lower than ground and accidentally turn on a MOSFET switch and causing loss of charge during the subsequent transfer cycle. 
     At the present time, the best mode of practicing the invention is the assignee&#39;s recently introduced ADS1210 delta sigma analog-to-digital converter. 
     While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make the various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention. It is intended that all combinations of elements and steps which perform substantially the same function in substantially the same way to achieve the same result are within the scope of the invention, conceivably, C REF (TOTAL) can be made programmable in other ways than by the described selective parallel connection or sequential sampling of individual capacitors, for example by selective series connection or series-parallel connection of individual capacitors or by use of a voltage-variable capacitance such as a PN junction capacitor. The effect of making C REF (TOTAL) programmable is to make the &#34;effective&#34; feedback voltage and ultimately, the feedback charge, programmable. In some cases, the feedback charge might be made programmable in ways other than by making C REF (TOTAL) programmable, for example by supplying and transferring a programmable current into the integrator capacitor. 
     Various charge sampling and transferring circuits other than those described above can be used. Also note that the analog input sampling capacitors C IN  can be &#34;segmented&#34; similarly to the above described &#34;segmenting&#34; of C REF  such that to select higher gain a value of C IN (TOTAL) could be increased without changing the sampling rate; mismatches between the segmented input sampling capacitors could be averaged out between comparator decision cycles by the digital output filter, as previously described. 
     In the embodiments of both FIGS. 1 and 2, the capacitive switching circuits sample the analog input and then transfer sampled charges between the sampling capacitors and the integrating capacitors. In each case, the transfer of sampled charge can be thought of as either a &#34;give&#34; (i.e., non-inverting) transfer of charge from a sampling capacitor to an integrating capacitor or a &#34;take&#34; (i.e., inverting) transfer of charge from an integrating capacitor to a sampling capacitor. Suitable capacitive switching circuits and reference voltages can be adapted such that a particular such circuit always functions to produce a &#34;give&#34; charge transfer, always functions to produce a &#34;take&#34; charge transfer, or performs both &#34;give&#34; and &#34;take&#34; charge transfers functions, depending on the output decision of the comparator 108.