Patent Publication Number: US-2022224107-A1

Title: Circuit for and method of protecting overvoltage in universal serial bus interface

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of pending U.S. application Ser. No. 16/260,253, filed on Jan. 29, 2019, the entire contents of which is hereby incorporated by reference. 
     Korean Patent Application No. 10-2018-0098091, filed on Aug. 22, 2018, in the Korean Intellectual Property Office, and entitled: “Circuit for and Method of Protecting Overvoltage in Universal Serial Bus Interface,” is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     Embodiments relate to a universal serial bus (USB) interface, and more particularly, to a circuit for and method of protecting an overvoltage in an USB interface. 
     2. Description of the Related Art 
     A USB (or USB standard) is a standard for defining a cable, a connector, and a communication protocol to perform communication between devices, and is widely used in various applications. The USB defines not only protocols for transmitting and receiving data but also standards for power transmission. For example, USB power delivery (PD) specifies delivery of high power, e.g., 20V and 5 A. Thus, when a conductive foreign material is introduced into a USB receptacle or an electrical short occurs on a USB cable, damage may occur due to an overcurrent, and the USB receptacle and a USB plug may also be damaged. 
     SUMMARY 
     Embodiments are directed to a circuit to protect an overvoltage in a universal serial bus (USB) device, the circuit including an overvoltage protection (OVP) switch connected to a pin of a USB receptacle, and a switch controller to turn off the OVP switch when an overvoltage is detected, such that power between the pin and the USB device is interrupted, wherein the switch controller supplies a control signal to the OVP switch such that the OVP switch has a first on-resistance when the USB device is operating in a normal mode and no overvoltage is detected, and has a second on-resistance, higher than the first on-resistance, when the USB device is operating in a low-power mode and no overvoltage is detected. 
     Embodiments are directed to a circuit to protect an overvoltage in a universal serial bus (USB) device, the circuit including an overvoltage protection (OVP) switch connected to a pin of a USB receptacle, and a switch controller to turn off the OVP switch when an overvoltage is detected, such that power between the pin and the USB device is interrupted, wherein the switch controller includes a charge pump that is powered up when the USB device is operating in a normal mode and is powered down the charge pump when the USB device is operating in a low-power mode. 
     Embodiments are directed to a method for protecting an overvoltage in a universal serial bus (USB) device, the method including monitoring a voltage on a pin of a USB receptacle, turning off an overvoltage protection (OVP) switch connected to the pin of the USB receptacle when an overvoltage is detected such that power between the pin and the USB device is interrupted, turning on the OVP switch when the overvoltage is eliminated, and determining whether the USB device is operating in a normal mode or a low-power mode. When the USB device is operating in the normal mode, a first voltage is provided to the OVP switch when no overvoltage is detected. When the USB device is operating in the low-power mode, a second voltage is provided to the OVP switch, the second voltage being less than the first voltage, when no overvoltage is detected 
     Embodiments are directed to a circuit to protect an overvoltage in a universal serial bus (USB) device, the circuit including a first overprotection (OVP) switch and a second OVP switch connected in parallel, and a switch controller. The switch controller includes a first switch connected to the first OVP switch, and to be selectively connected to a ground voltage or a charge pump, the first switch to turn off the first OVP switch when an overvoltage is detected when the USB device is operating in a normal mode such that power between the pin and the USB device is interrupted, and a second switch connected to the second OVP switch, and to be selectively connected to the ground voltage or a positive supply voltage, the second switch to turn off the second OVP switch when an overvoltage is detected and the USB device is operating in a low-power mode, such that power between the pin and the USB device is interrupted, wherein the first OVP switch has a first on-resistance and the second OVP switch has a second on-resistance, higher than the first on-resistance 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIG. 1  illustrates a block diagram of a universal serial bus (USB) device according to an example embodiment; 
         FIG. 2  illustrates a block diagram of an example of a USB receptacle of  FIG. 1 , according to an example embodiment; 
         FIG. 3  illustrates a block diagram of a USB device according to an example embodiment; 
         FIG. 4  illustrates a flowchart of a method of protecting an overvoltage in a USB interface according to an example embodiment; 
         FIG. 5  illustrates a block diagram of a switch controller according to an example embodiment; 
         FIG. 6  illustrates a block diagram of a USB device according to an example embodiment; 
         FIGS. 7A and 7B  illustrate diagrams of examples of an operation of the USB device of  FIG. 6 , according to example embodiments; 
         FIG. 8  illustrates a block diagram of a USB device according to an example embodiment; 
         FIG. 9  illustrates a timing diagram of an example of an operation of the USB device of  FIG. 7 , according to an example embodiment; 
         FIG. 10  illustrates a block diagram of a USB device according to an example embodiment; 
         FIGS. 11A and 11B  illustrate diagrams of examples of an operation of the USB device of  FIG. 10 , according to example embodiments; and 
         FIG. 12  illustrates a flowchart of a method of protecting an overvoltage in a USB interface according to an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a universal serial bus (USB) device  100  according to an example embodiment.  FIG. 2  is a block diagram of an example of a USB receptacle  110  of  FIG. 1 , according to an example embodiment. 
     Referring to  FIG. 1 , the USB device  100  may be an arbitrary, i.e., any, device capable of communicating with another device through a USB interface. For example, the USB device  100  may be a stationary device, e.g., a desktop computer, a server, and the like, or a portable device, e.g., a laptop computer, a mobile phone, a tablet personal computer (PC), and the like. Also, the USB device  100  may be a component included in the stationary device or the portable device and configured to provide the USB interface. As shown in  FIG. 1 , the USB device  100  may include a USB receptacle  110 , a termination circuit  120 , a port controller  130 , a power circuit  140 , and an overvoltage protection (OVP) circuit  150 . 
     The USB receptacle  110  may be coupled to a USB cable or a USB plug to be connected to another USB device. The USB receptacle  110  may include a plurality of exposed pins that transmit and receive signals or transmit power. For example, as shown in  FIG. 2 , the USB receptacle  110  may include pins to transmit transmission signals TX+ and TX−, receive receiving signals RX+ and RX−, channel configuration (CC) signals CC 1  and CC 2 , a VBUS voltage V_BUS, and a ground voltage. In some embodiments, the USB receptacle  110  may have a USB Type-C pin arrangement as shown in  FIG. 2 . 
     When a conductive foreign material is introduced into the USB receptacle  110  while the USB plug is not coupled to the USB receptacle  110  or an electrical short occurs in the USB cable coupled to the USB receptacle  110 , at least two pins of the USB receptacle  110  may be electrically connected to each other. The pins that are inappropriately electrically connected to each other may cause leakage currents, which may not only cause a communication failure via the USB interface but also may cause damage to the USB device  100  or the other USB device. In particular, when the USB device  100  is a portable device or a component included in the portable device, a conductive material (e.g., water, metal, and the like) may be easily introduced into the USB receptacle  110 . Thus, excessive power consumption or damage may occur in the USB device  100 . For example, USB power delivery (PD) may define delivery of a high power (e.g., 20 V and 5 A) via a VBUS pin (e.g., A 4  of  FIG. 2 ). Also, when the VBUS pin has a short circuit with another pin (e.g., A 5  of  FIG. 2 ), a high voltage and current of the VBUS pin may be applied to the shorted pin. To protect an internal circuit (e.g., the termination circuit  120  and the port controller  130 ) of the USB device  100  from the high voltage and current, the USB device  100  may include the OVP circuit  150 . 
     The OVP circuit  150  may detect an overvoltage occurring at a pin included in the USB receptacle  110  and may electrically disconnect the pin from the internal circuit of the USB device  100  when an overvoltage is detected. Also, the OVP circuit  150  may output an activated detection signal DET when the overvoltage is detected. In some embodiments, the OVP circuit  150  may not attenuate signals transmitted and received via the pins of the USB receptacle  110  in a normal state in which an overvoltage does not occur. The OVP circuit  150  may include a circuit that consumes relatively high power. The USB device  100  may operate in a normal mode and a low-power mode. The OVP circuit  150  may reduce power consumption of the USB device  100  in the low-power mode. Hereinafter, as described below with reference to the drawings, the OVP circuit  150  may provide reduced power consumption in the low-power mode without causing the attenuation of the signals in the low-power mode. 
     The termination circuit  120  may be controlled by the port controller  130  and provide the USB receptacle  110  with termination in accordance with USB requirements. For example, the termination circuit  120  may transmit CC signals CC 1  and CC 2  from the port controller  130  to the USB receptacle  110  or transmit the CC signals CC 1  and CC 2  from the USB receptacle  110  to the port controller  130 , under control of the port controller  130 . Also, the termination circuit  120  may provide a VCONN voltage for providing power for an active cable from the power circuit  140  to the USB receptacle  110  under control of the port controller  130 . 
     The port controller  130  may communicate with the termination circuit  120 , control the termination circuit  120 , and control the USB interface in response to signals received through the termination circuit  120 . The port controller  130  may control port power supplied to the outside or received from the outside through the USB receptacle  110 , and process the CC signals CC 1  and CC 2  according to USB requirements. In some embodiments, the port controller  130  may be a logic block designed by logic synthesis, a software block included in a memory that stores a processor and instructions executed by the processor, or a combination thereof. In some embodiments, the port controller  130  may be referred to as a power delivery integrated circuit (PDIC). In some embodiments, the termination circuit  120  and the port controller  130  may be included in one IC, and the IC may be referred to as a PDIC. 
     The port controller  130  may output a power control signal PWR for controlling the power circuit  140 . For example, the port controller  130  may perform power negotiation with another USB device and control the power circuit  140  using the power control signal PWR based on the negotiation result. 
     In some embodiments, the port controller  130  may provide a mode signal MD indicating the normal mode or the low-power mode to the OVP circuit  150 , and may receive a detection signal DET indicating whether an overvoltage has occurred from the OVP circuit  150 . The port controller  130  may switch a mode between the normal mode and the low-power mode based on a user&#39;s input to the USB device  100  or switch a mode between the normal mode and the low-power mode when an entry condition to the normal mode or the low-power mode is satisfied, and generate the mode signal MD indicating a mode. In some embodiments, when an overvoltage occurs, i.e., when an activated detection signal DET is received from the OVP circuit  150 , the port controller  130  may control a signal generator (e.g., a speaker, a display, a light-emitting element, a vibration motor, and so forth) to notify occurrence of an overvoltage to the outside of the USB device  100 , for example, to output a signal that is recognizable, i.e., detectable, by a user of the USB device  100 . 
     The power circuit  140  may provide a VBUS voltage V_BUS to the USB receptacle  110  or receive the VBUS voltage V_BUS from the USB receptacle  110 . In some embodiments, when the USB device  100  supports an upload faced port (UFP), the power circuit  140  may receive the VBUS voltage V_BUS from a power pin (e.g., A 4  of  FIG. 2 ) of the USB receptacle  110  and distribute power supplied by the VBUS voltage V_BUS to other components of the USB device  100 . In some embodiments, when the USB device  100  supports a download faced port (DFP), the power circuit  140  may provide the VBUS voltage V_BUS to a power pin (e.g., A 4  of  FIG. 2 ) of the USB receptacle  110 . In some embodiments, the USB device  100  may support a dual role port (DRP) that is switchable between a source (or a host) and a sink (or a device). 
     In some embodiments, the power circuit  140  may generate a VCONN voltage for providing power for the active cable and provide the VCONN voltage to the termination circuit  120 . The VCONN voltage may be provided to a CC 1  pin (e.g., A 5  of  FIG. 2 ) or a CC 2  pin (e.g., B 5  of  FIG. 2 ) of the USB receptacle  110  due to an operation of the termination circuit  120  via the control of the port controller  130 . As used herein, a voltage for transmitting power, such as the VBUS voltage V_BUS and the VCONN voltage, may be referred to as a power supply voltage. 
     Referring to  FIG. 2 , a USB receptacle  110 ′ may have a structure according to USB Type-C. The USB receptacle  110 ′ may have a symmetrical pin arrangement, such that the USB receptacle  110 ′ may be properly coupled with a USB plug regardless of a direction or orientation, e.g., inserted up or down. The USB receptacle  110 ′ may include a TX 1 + pin A 2 , a TX 1 − pin A 3 , an RX 1 + pin B 11 , an RX 1 − pin B 10 , a TX 2 + pin B 2 , a TX 2 − pin B 3 , an Rx 2 + pin A 11 , and an RX 2 − pin A 10  as a data bus. The USB receptacle  110 ′ may include VBUS pins A 4 , A 9 , B 4 , and B 9 , and the CC 1  pin A 5  as a power bus and the CC 2  pin B 5  may also transmit a VCONN voltage according to a direction in which the USB receptacle  110 ′ is coupled to the USB plug. Also, the USB receptacle  110 ′ may include two sideband use (SBU) pins A 8  and B 8  and two channel configuration (CC) pins A 5  and B 5 . The CC 1  pin A 5  and the CC 2  pin B 5  may be referred to collectively as a CC pin. The USB plug coupled to the USB receptacle  110 ′ may include one CC pin CC unlike the USB receptacle  110 ′, and include a dedicated VCOON pin. Finally, the USB receptacle  110 ′ may include four ground (GND) pins A 1 , A 12 , B 1 , and B 12  in an outer portion thereof. 
     As described above, when a foreign material is introduced into the USB receptacle  110 ′, an electrical short may occur in a USB cable connected to the USB receptacle  110 ′, or pins included in the USB receptacle  110 ′ may be released, such that an electrical short may occur between at least two pins. In particular, when an electrical path is formed between power pins (e.g., the VBUS pins A 4 , A 9 , B 4 , and B 9 ) and other pins, leakage currents may markedly increase. For example, the pins A 3 , A 5 , A 8 , A 10 , B 3 , B 5 , B 8 , and B 10  located adjacent to the VBUS pins A 3 , A 9 , B 4 , and B 9  may easily have a short circuit with the VBUS pins A 3 , A 9 , B 4 , and B 9 . 
     In some embodiments, the OVP circuit  150  may protect the USB device  100  from an overvoltage occurring at an arbitrary pin other than power pins (e.g., the VBUS pins A 4 , A 9 , B 4 , and B 9 ) and ground pins (e.g., the GND pins A 1 , A 12 , B 1 , and B 12 )) in the USB receptacle  110 ′. Furthermore, in some embodiments, the OVP circuit  150  of  FIG. 1  may protect the USB device  100  from an overvoltage occurring at the pins A 3 , A 5 , A 8 , A 10 , B 3 , B 5 , B 8 , and B 10  that are located adjacent to the VBUS pins A 4 , A 9 , B 4 , and B 9 . Hereinafter, an operation of protecting the USB  100  from an overvoltage occurring at the CC 1  pin A 5  adjacent to the VBUS pin A 4  will be mainly described. 
       FIG. 3  is a block diagram of a USB device  300  according to an example embodiment. Specifically,  FIG. 3  illustrates the USB device  300  including an OVP circuit  350  configured to protect the USB device  300  from an overvoltage occurring at a CC 1  pin A 5 . Similar to the USB device  100  of  FIG. 1 , the USB device  300  may include a USB receptacle  310 , a termination circuit  320 , a port controller  330 , and an OVP circuit  350 . In  FIG. 3 , the same descriptions as with reference to  FIG. 1  will not be repeated. 
     Referring to  FIG. 3 , the OVP circuit  350  may include an OVP switch  351  and a switch controller  352 . The OVP switch  351  may be coupled to one or more CC pins described above. While the operation of the OVP circuit  350  is described below with respect to a CC 1  pin A 5 , it is understood that the operation may also be performed with respect to a CC 2  pin B 5  (and VBUS pin B 4 ). 
     For example, a CC 1  pin A 5  of the USB receptacle  310 , and may be coupled to the termination circuit  320  to interrupt VCONN. The OVP switch  351  may electrically connect the CC 1  pin A 5  to the termination circuit  320  or disconnect the CC 1  pin A 5  from the termination circuit  320  in response to a control signal CTR received from the switch controller  352 . When the CC 1  pin A 5  is electrically connected to the termination circuit  320  by the OVP switch  351 , the OVP switch  351  may have an on-resistance Ron. To minimize the distortion of a signal passing through the CC 1  pin A 5 , the OVP switch  351  may have a low on-resistance Ron. In addition, when the CC 1  pin A 5  is electrically connected to the termination circuit  320  by the OVP switch  351 , the OVP switch  351  may not limit a swing of the signal passing through the CC 1  pin A 5 . Thus, as described below with reference to  FIG. 5 , the OVP switch  351  may receive a boosted voltage. 
     The switch controller  352  may be coupled to the CC 1  pin A 5  of the USB receptacle  310  and may detect an overvoltage occurring at the CC 1  pin A 5  based on a voltage (i.e., an input voltage V_IN) of the CC 1  pin A 5 . For example, as described above with reference to  FIG. 2 , the CC 1  pin A 5  may be located adjacent, e.g., immediately next, to the VBUS pin A 4  in the USB receptacle  310 . Thus, when the CC 1  pin A 5  has a short circuit with the VBUS pin A 4 , a VBUS voltage V_BUS may be applied to the CC 1  pin A 5 . The switch controller  352  may detect the overvoltage occurring at the CC 1  pin A 5  based on a level of the input voltage V_IN, control the OVP switch  351  using the control signal CTR, and electrically disconnect the CC 1  pin A 5  from the termination circuit  320 . 
     The switch controller  352  may receive a mode signal MD from the port controller  330 , and provide a detection signal DET to the port controller  330 . As described above with reference to  FIG. 1 , the detection signal DET may indicate whether an overvoltage has occurred at the CC 1  pin A 5 , and the mode signal MD may indicate a mode (i.e., a normal mode or a low-power mode) of the USB device  300 . The switch controller  352  may generate the control signal CTR based on both the input voltage V_IN and the mode signal MD. An example of an operation of the switch controller  352  will be described below with reference to  FIG. 4 . 
       FIG. 4  is a flowchart of a method of protecting an overvoltage in a USB interface according to an example embodiment. For example, the method of  FIG. 4  may be performed by the OVP circuit  350  of  FIG. 3 . Hereinafter,  FIG. 4  will be described with reference to  FIG. 3 . 
     In operation S 10 , an operation of detecting an overvoltage may be performed. For example, the switch controller  352  may determine whether the overvoltage occurs based on an input voltage V_IN of a CC 1  pin A 5 . In some embodiments, an overvoltage may refer to a voltage that deviates from a voltage range defined by a USB standard for the CC 1  pin A 5 . For example, the USB standard may define a voltage level between −0.25 V and 1.8 V for a signal passing through the CC 1  pin A 5 , and an overvoltage is considered to have occurred when the CC 1  pin A 5  has a voltage that deviates from a range between −0.25 V and 1.8 V. In some embodiments, an overvoltage may be determined based on a maximum input voltage of internal circuits of the USB device  300 . For example, the internal circuits (e.g., the termination circuit  320  and the port controller  330 ) of the USB device  300  may receive a voltage of about 3.3 V as a positive supply voltage (e.g., VDD of  FIG. 5 ), and an overvoltage may be considered to have occurred when a detected voltage deviates from range between 0 V and 3.3 V. In some embodiments, the overvoltage may correspond to a voltage that deviates from a voltage range between 0 V and 5 V. In some embodiments, the overvoltage may be considered to have occurred when a detected voltage deviates from a range including a predetermined margin and one of the above-described voltage ranges. As shown in  FIG. 4 , when the overvoltage is not detected, operation S 10  may be repeatedly performed, whereas when the overvoltage is detected, operation S 30  may be subsequently performed. 
     In operation S 30 , an operation of turning off the OVP switch  351  may be performed. For example, the switch controller  352  may generate a control signal CTR so that the OVP switch  351  may electrically disconnect the CC 1  pin A 5  from the termination circuit  320 , i.e., the OVP switch  351  may be turned off. 
     In operation S 50 , an operation of determining whether the overvoltage has been eliminated may be performed. For example, the switch controller  352  may determine whether the overvoltage has been eliminated at the CC 1  pin A 5  based on the input voltage V_IN of the CC 1  pin A 5 . As shown in  FIG. 4 , when the overvoltage has not been eliminated, operation S 50  may be repeatedly performed, and the OVP switch  351  may remain turned off. Otherwise, when the overvoltage has been eliminated, operation S 70  may be subsequently performed. 
     In operation S 70 , an operation of determining a mode of the USB device  300  may be performed. For example, the switch controller  352  may determine the mode of the USB device  300  based on a mode signal MOD received from the port controller  330 . As shown in  FIG. 4 , when the USB device  300  is in a normal mode, operation S 91  may be subsequently performed, whereas when the USB device  300  is in a low-power mode, operation S 93  may be subsequently performed. 
     When the USB device  300  is in the normal mode, an operation of setting an on-resistance Ron of the OVP switch  351  as a first resistance R 1  may be performed in operation S 91 . As described above with reference to  FIG. 3 , the first resistance R 1  may correspond to a relatively low resistance to reduce the distortion of a signal passing through the CC 1  pin A 5 . For example, the switch controller  352  may generate a control signal CTR having a boosted voltage so that the OVP switch  351  may have the first resistance R 1  as the on-resistance Ron. As described below with reference to  FIG. 5 , the switch controller  352  may include a charge pump (e.g.,  51  of  FIG. 5 ) configured to generate a boosted voltage from positive supply voltages of internal circuits of the USB device  300 . As used herein, the first resistance R 1  may refer to a resistance lower than a second resistance R 2  to be described below. 
     When the USB device  300  is in the low-power mode, an operation of setting the on-resistance Ron of the OVP switch  351  as the second resistance R 2  may be performed in operation S 93 . The second resistance R 2  may be higher than the first resistance R 1 . For example, the switch controller  352  may generate a control signal CTR having an unboosted voltage such that the OVP switch  351  has the second resistance R 2  as the on-resistance Ron, and the charge pump included in the switch controller  352  may be powered down. Thus, the switch controller  352  may consume reduced power in the low-power mode. As a result, efficiency of the USB device  300  may be improved in the low-power mode. 
       FIG. 5  is a block diagram of a switch controller  50  according to an example embodiment. For example,  FIG. 5  illustrates an example of the switch controller  352  of  FIG. 3 . As described above with reference to  FIG. 3 , the switch controller  50  of  FIG. 5  may receive an input voltage V_IN from the CC 1  pin A 5 , receive a mode signal MD from the port controller  330 , and generate a detection signal DET and a control signal CTR. As shown in  FIG. 5 , the switch controller  50  may include a charge pump  51 , an overvoltage detector  52 , and a control circuit  53 . Hereinafter,  FIG. 5  will be described with reference to  FIGS. 3 and 4 . 
     The charge pump  51  may receive a positive supply voltage VDD and generate a boosted voltage (i.e., an output voltage V_OUT) based on the positive supply voltage VDD. The output voltage V_OUT generated by the charge pump  51  may be provided by the control circuit  53  to an OVP switch  351  under certain conditions, described below. The OVP switch  351  may provide a first resistance R 1  as an on-resistance Ron in response to the output voltage V_OUT. In some embodiments, the OVP switch  351  may include an n-channel field-effect transistor (NFET), and the charge pump  51  may generate an output voltage V_OUT that is higher than the positive supply voltage VDD. In some embodiments, the OVP switch  351  may include a p-channel FET (PFET), and the charge pump  51  may generate an output voltage V_OUT that is lower than a ground voltage. The charge pump  51  may have an arbitrary, i.e., any, configuration that generates an output voltage V_OUT. For example, the charge pump  51  may include at least one capacitor and at least one switch and receive a clock signal. 
     The charge pump  51  may operate or be powered down in response to an enable signal ENA received from the control circuit  53 . For example, the charge pump  51  may generate a boosted output voltage V_OUT from the positive supply voltage VDD in response to an activated enable signal ENA and may be powered down in response to a deactivated enable signal ENA. 
     The overvoltage detector  52  may receive an input voltage V_IN from the CC 1  pin A 5  and determine whether an overvoltage has occurred at the CC 1  pin A 5  based on the input voltage V_IN. For example, the overvoltage detector  52  may include resistors Ra and Rb that divide the input voltage V_IN and a comparator CMP. The comparator CMP may compare a voltage divided from the input voltage V_IN with a reference voltage V_REF, and output an activated detection signal DET when the divided voltage is higher than the reference voltage V_REF. Alternatively, the overvoltage detector  52  may have any structure that generates the detection signal DET according to a magnitude of the input voltage V_IN. 
     The control circuit  53  may generate an enable signal ENA and a control signal CTR based on the detection signal DET received from the overvoltage detector  52  and the mode signal MD received from the port controller  130 . For example, in response to the activated detection signal DET, the control circuit  53  may output a control signal CTR to turn off the OVP switch  351 . Also, in response to a mode signal MD indicating a low-power mode, the control circuit  53  may output a deactivated enable signal ENA to power down the charge pump  51 . As described below with reference to  FIG. 6 , in some embodiments, the control circuit  53  may include at least one logic gate to receive the detection signal DET and/or the mode signal MD as input signals, and include at least one switch that is turned on/off based on an output signal of the at least one logic gate. Examples of a configuration and an operation of the control circuit  53  will be described below with reference to  FIGS. 6, 8, and 10 . 
       FIG. 6  is a block diagram of a USB device  600  according to an example embodiment.  FIGS. 7A and 7B  are diagrams of examples of an operation of the USB device  600  of  FIG. 6 , according to example embodiments. Specifically,  FIG. 6  illustrates the USB device  600  including an OVP switch  610  including an NFET N 60  and a switch controller  620  configured to control the OVP switch  610 , and  FIGS. 7A and 7B  illustrate signals of the USB device  600  of  FIG. 6  with respect to time. In  FIGS. 6, 7A, and 7B , it is assumed that the signals are active high signals. Thus, an activated signal may have a high level, while a deactivated signal may have a low signal. In  FIGS. 7A and 7B , repeated descriptions will not be repeated. 
     Referring to  FIG. 6 , the OVP switch  610  may include an NFET N 60  to serve as a switch that is turned on and off based on a control signal CTR. Although only one NFET N 60  is illustrated in  FIG. 6 , in some embodiments, the OVP switch  610  may include a plurality of NFETs connected in series that commonly receive the control signal CTR and/or a plurality of NFETs connected in parallel to each other that commonly receive the control signal CTR. The NFET N 60  may have an on-resistance Ron, which is reduced as a gate voltage (i.e., a voltage of the control signal CTR) increases. 
     The switch controller  620  may include a charge pump  621  and a control circuit  623 . The control circuit  623  may include a control logic  623 _ 1 , a first switch  623 _ 2 , and a second switch  623 _ 3 . The control logic  623 _ 1  may receive a detection signal DET and a mode signal MD, and generate a first switch signal SW 1  and a second switch signal SW 2  based on the detection signal DET and the mode signal MD. The first switch  623 _ 2  may connect a gate of the NFET N 60  to a ground voltage or the second switch  623 _ 3  based on the first switch signal SW 1 . The second switch  623 _ 3  may connect the first switch  623 _ 2  to a positive supply voltage VDD or the charge pump  621  based on the second switch signal SW 2 . States of the first switch  623 _ 2  and the second switch  623 _ 3  shown in  FIG. 6  may correspond to states in which the first switch  623 _ 2  and the second switch  623 _ 3  receive a deactivated first switch signal SW 1  and a deactivated second switch signal SW 2 , i.e., a low-level first switch signal SW 1  and a low-level second switch signal SW 2 , respectively. 
     Referring to  FIG. 7A , the mode signal MD may have a low level in a normal mode until a time point t 72 , and have a high level in a low-power mode from the time point t 72 . Alternatively, the mode signal MD may have a high level in the normal mode and a low level in the low-power mode. 
     Until a time point t 70 , an overvoltage may not be detected at the CC 1  pin A 5  and, thus, the detection signal DET may be at a low level. The control logic  623 _ 1  may generate a high-level enable signal ENA based on a low-level mode signal MD, so that the charge pump  621  may generate an output voltage V_OUT. Also, the control logic  623 _ 1  may generate a low-level first switch signal SW 1  and a low-level second switch signal SW 2  based on the low-level detection signal DET. As a result, the first switch  623 _ 2  and the second switch  623 _ 3  may be in states shown in  FIG. 6 , and the output voltage V_OUT of the charge pump  621  may be provided as a control signal CTR to the OVP switch  610 . Thus, the on-resistance Ron of the OVP switch  610  may correspond to the first resistance R 1  lower than the second resistance R 2 . 
     At the time point t 70 , the overvoltage may occur at the CC 1  pin A 5  and, thus, the detection signal DET may transition to a high level. In response to an activated detection signal DET, the control logic  623 _ 1  may output an activated first switch signal SW 1 , so that the control signal CTR may have a ground voltage GND due to the first switch  623 _ 2 . Thus, the NFET N 60  may and the OVP switch  610  may be turned off. 
     At a time point t 71 , the overvoltage may be eliminated at the CC 1  pin A 5  and thus, the detection signal DET may transition to a low level. In response to a deactivated detection signal DET, the control logic  623 _ 1  may output a deactivated first switch signal SW 1 , so that the control signal CTR may have an output voltage V_OUT. 
     At the time point t 72 , the USB device  600  may be switched from the normal mode to the low-power mode and the mode signal MD may transition to a high level. In response to a high-level mode signal MD, the control logic  623 _ 1  may output a deactivated enable signal ENA and, thus, the charge pump  621  may be powered down. Also, in response to the high-level mode signal MD, the control logic  623 _ 1  may output an activated second switch signal SW 2 , so that a positive supply voltage VDD may be provided as a control signal CTR to the OVP switch  610 . Thus, the on-resistance Ron of the OVP switch  610  may correspond to the second resistance R 2  higher than the first resistance R 1 . 
     At a time point t 73 , an overvoltage may occur at the CC 1  pin A 5  and, thus, the detection signal DET may transition to a high level. In response to an activated detection signal DET, the control logic  623 _ 1  may output an activated first switch signal SW 1 , so that the control signal CTR may have a ground voltage GND due to the first switch  623 _ 2 . Thus, the NFET N 60  and the OVP switch  610  may be turned off. 
     At a time point t 74 , the overvoltage may be eliminated at the CC 1  pin A 5  and, thus, the detection signal DET may transition to a low level. In response to a deactivated detection signal DET, the control logic  623 _ 1  may output a deactivated first switch signal SW 1 , so that the control signal CTR may have a positive supply voltage VDD. 
     Referring to  FIG. 7B , in some embodiments, the charge pump  621  may be powered down even in the normal mode when an overvoltage is detected. For example, at a time point t 70  of  FIG. 7B , an overvoltage may occur at the CC 1  pin A 5  and, thus, the detection signal DET may transition to a high level. In response to an activated detection signal DET, the control logic  623 _ 1  may output not only an activated first switch signal SW 1  but also a deactivated enable signal ENA. As a result, the charge pump  621  may be powered down. Thus, power consumption may be reduced even in the normal mode when the overvoltage is detected. 
       FIG. 8  is a block diagram of a USB device  800  according to an example embodiment.  FIG. 9  is a timing diagram of an example of an operation of the USB device  800  of  FIG. 8 , according to an example embodiment. Specifically,  FIG. 8  illustrates the USB device  800  including an OVP switch  810  including a PFET P 80  and a switch controller  820  configured to control the OVP switch  810 .  FIG. 9  illustrates signals of the USB device  800  of  FIG. 8  with respect to time. In  FIGS. 8 and 9 , it is assumed that the signals are active high signals, and the same descriptions as with reference to  FIGS. 6, 7A, and 7B  will not be repeated. 
     Referring to  FIG. 8 , the OVP switch  810  may include a PFET P 80  that serves as a switch that is turned on and off based on a control signal CTR. Although  FIG. 8  illustrates only one PFET P 80 , in some embodiments, the OVP switch  810  may include a plurality of PFETs connected in series to each other to commonly receive a control signal CTR, and/or a plurality of PFETs connected in parallel to each other to commonly receive the control signal CTR. The PFET P 80  may have an on-resistance Ron, which is reduced as a gate voltage (i.e., a voltage of the control signal CTR) is reduced. 
     The switch controller  820  may include a charge pump  821  and a control circuit  823 . Unlike the charge pump  621  of  FIG. 6  that generates the output voltage V_OUT higher than the power supply voltage VDD, the charge pump  821  may generate an output voltage V_OUT lower than a ground voltage. The control circuit  823  may include a control logic  823 _ 1 , a first switch  823 _ 2 , and a second switch  823 _ 3 . The first switch  823 _ 2  may connect a gate of the PFET P 80  to a positive supply voltage VDD or the second switch  823 _ 3  based on a first switch signal SW 1 . The second switch  823 _ 3  may connect the first switch  823 _ 2  to the ground voltage or the charge pump  821  based on a second switch signal SW 2 . States of the first switch  823 _ 2  and the second switch  823 _ 3  shown in  FIG. 8  may correspond to a deactivated first switch signal SW 1  and a deactivated second switch signal SW 2 , i.e., a low-level first switch signal SW 1  and a low-level second switch signal SW 2 , respectively. 
     Referring to  FIG. 9 , similar to  FIGS. 7A and 7B , a mode signal MD may have a low level in a normal mode until a time point t 92 , and have a high level in a low-power mode from the time point t 92 . Also, an overvoltage may occur at a CC 1  pin A 5  at a time point t 90  and a time point t 93 , while the overvoltage may be eliminated at the CC 1  pin A 5  at a time point t 91  and a time point t 94 . 
     Until the time point t 90 , a detection signal DET may be at a low level, and the control logic  823 _ 1  may generate a low-level first switch signal SW 1  and a low-level second switch signal SW 2  based on the low-level detection signal DET. Thus, the first switch  823 _ 2  and the second switch  823 _ 3  may be in states shown in  FIG. 8 , and an output voltage V_OUT of the charge pump  821  may be provided as a control signal CTR to the OVP switch  810 . Thus, an on-resistance Ron of the OVP switch  810  may correspond to a first resistance R 1  lower than a second resistance R 2 . 
     At the time point t 90 , the detection signal DET may transition to a high level. The control logic  823 _ 1  may output an activated first switch signal SW 1  in response to an activated detection signal DET and thus, the control signal CTR may have a positive supply voltage VDD due to the first switch  823 _ 2 . Thus, the PFET P 80  and the OVP switch  810  may be turned off. Next, at the time point t 91 , the detection signal DET may transition to a low level, so that the control logic  823 _ 1  may output a deactivated first switch signal SW 1  in response to a deactivated detection signal DET. As a result, the control signal CTR may have an output voltage V_OUT. In some embodiments, as described above with reference to  FIG. 7B , the control logic  823 _ 1  may output a deactivated enable signal ENA unlike shown in  FIG. 9 , so that the charge pump  821  may be powered down from the time point t 90  to the time point t 91 . 
     At the time point t 92 , the control logic  823 _ 1  may output a deactivated enable signal ENA in response to the high-level mode signal MD and, thus, the charge pump  821  may be powered down. Also, the control logic  823 _ 1  may output an activated second switch signal SW 2  in response to the high-level mode signal MD, so that a ground voltage GND may be provided as a control signal CTR to the OVP switch  810 . As a result, the on-resistance Ron of the OVP switch  810  may correspond to the second resistance R 2  higher than the first resistance R 1 . 
     At the time point t 93 , the detection signal DET may transition to a high level and the control logic  823 _ 1  may output an activated first switch signal SW 1  in response to an activated detection signal DET, so that the control signal CTR may have a positive supply voltage VDD due to the first switch  823 _ 2 . Thus, the PFET P 80  may be turned off, and the OVP switch  810  may be turned off. Next, at a time point t 94 , the detection signal DET may transition to a low level. In response to a deactivated detection signal DET, the control logic  823 _ 1  may output a deactivated first switch signal SW 1  and thus, the control signal CTR may have a ground voltage GND. 
     In some embodiments, the OVP switch  351  of  FIG. 3  may include an NFET and a PFET connected in parallel and/or in series to each other. Thus, the switch controller  352  may include a first charge pump that generates a first output voltage higher than the positive supply voltage VDD and a second charge pump that generates a second output voltage lower than the ground voltage GND. The switch controller  352  may perform the above-described operations with reference to  FIGS. 7A, 7B, and 8 . Thus, both the first charge pump and the second charge pump may be powered down in the low-power mode. 
       FIG. 10  is a block diagram of a USB device  900  according to an example embodiment.  FIGS. 11A and 11B  are diagrams of examples of an operation of the USB device  900  of  FIG. 10 , according to example embodiments. Specifically,  FIG. 10  illustrates the USB device  900  including an OVP switch  910  including first and second OVP switches connected in parallel, and a switch controller  920  to control the OVP switch  910 .  FIGS. 11A and 11B  illustrate signals of the USB device  900  of  FIG. 10  with respect to time. In  FIGS. 10, 11A, and 11B , it is assumed that the signals are active high signals. Although the OVP switch  910  including NFETs N 91  and N 92  as the first and second OVP switches is illustrated in  FIGS. 10, 11A, and 11B , it will be understood that embodiments may be also applied to an OVP switch including PFETs as the first and second OVP switches. Hereinafter, the same descriptions as with reference to  FIGS. 7A and 7B  will not be repeated. 
     Referring to  FIG. 10 , the OVP switch  910  may include a first NFET N 91  and a second NFET N 92  connected in parallel, and that receive different signals, e.g., a first control signal CTR 1  and a second control signal CTR 2 , respectively. The first NFET N 91  may function as a first OVP switch that is turned on and off based on the first control signal CTR 1 , while the second NFET N 92  may function as a second OVP switch that is turned on and off based on the second control signal CTR 2 . 
     The switch controller  920  may include a charge pump  921  and a control circuit  923 . The control circuit  923  may include a control logic  923 _ 1 , a first switch  923 _ 2 , and a second switch  923 _ 3 . The control logic  923 _ 1  may receive a detection signal DET and a mode signal MD, and generate a first switch signal SW 1  and a second switch signal SW 2  based on the detection signal DET and the mode signal MD. The first switch  923 _ 2  may connect a gate of the first NFET N 91  to a ground voltage or the charge pump  921  based on the first switch signal SW 1 . The second switch  923 _ 3  may connect a gate of the second NFET N 92  to a positive supply voltage VDD or the ground voltage based on the second switch signal SW 2 . States of the first switch  923 _ 2  and the second switch  923 _ 3  shown in  FIG. 10  correspond to a deactivated first switch signal SW 1  and a deactivated second switch signal SW 2 , i.e., a low-level first switch signal SW 1  and a low-level second switch signal SW 2 , respectively. 
     Referring to  FIG. 11A , in some embodiments, the switch controller  920  may turn off the second OVP switch (i.e., the second NFET N 92 ) in a normal mode, and turn off the first OVP switch (i.e., the first NFET N 91 ) in a low-power mode. Thus, an on-resistance Ron of the OVP switch  910  may be dependent on the first NFET N 91  in the normal mode, and be dependent on the second NFET N 92  in the low-power mode. Since the first NFET N 91  may receive an output voltage V_OUT from the charge pump  921 , when an overvoltage does not occur at the CC 1  pin A 5 , the OVP switch  910  may have a first resistance R 1  as the on-resistance Ron in the normal mode, and have a second resistance R 2 , which is higher than the first resistance R 1 , in the low-power mode. 
     As shown in  FIG. 11A , the mode signal MD may have a low level in the normal mode until a time point t 12  and a high level in the low-power mode from the time point t 12 . Alternatively, the mode signal MD may have a high level in the normal mode and a low level in the low-power mode. 
     Until a time point t 10 , an overvoltage may not be detected at the CC 1  pin A 5  and thus, the detection signal DET may be at a low level. The control logic  923 _ 1  may generate a high-level enable signal ENA based on the low-level mode signal MD, so that the charge pump  921  may generate an output voltage V_OUT. Also, the control logic  923 _ 1  may generate a low-level first switch signal SW 1  and a low-level second switch signal SW 2  based on the low-level detection signal DET. Thus, the first switch  923 _ 2  and the second switch  923 _ 3  are in states shown in  FIG. 10 , the output voltage V_OUT of the charge pump  921  may be provided as a first control signal CTR 1  to the first NFET N 91 , and a ground voltage GND may be provided as a second control signal CTR 2  to the second NFET N 92 . Thus, the first NFET N 91  may be turned on, while the second NFET N 92  may be turned off. Due to the output voltage V_OUT higher than a positive supply voltage VDD, the first NFET N 91  may provide the first resistance R 1  lower than the second resistance R 2 . 
     At the time point t 10 , an overvoltage may occur at the CC 1  pin A 5  and, thus, the detection signal DET may transition to a high level. In response to an activated detection signal DET, the control logic  923 _ 1  may output an activated first switch signal SW 1 , so that the first control signal CTR 1  may have a ground voltage GND due to the first switch  923 _ 2 . Thus, the first NFET N 91  may be turned off, and the OVP switch  910  may be turned off. 
     At a time point t 11 , the overvoltage may be eliminated at the CC 1  pin A 5  and, thus, the detection signal DET may transition to a low level. In response to a deactivated detection signal DET, the control logic  923 _ 1  may output a deactivated first switch signal SW 1 , so that the first control signal CTR 1  may have an output voltage V_OUT. In some embodiments, as described above with reference to  FIG. 7B , the control logic  923 _ 1  may output a deactivated enable signal ENA unlike shown in  FIG. 11A  so that the charge pump  921  may be powered down from the time point t 10  to the time point t 11 . 
     At a time point t 12 , the USB device  900  may be switched from the normal mode to the low-power mode and the mode signal MD may transition to a high level. In response to the high-level mode signal MD, the control logic  923 _ 1  may output a deactivated enable signal ENA and, thus, the charge pump  921  may be powered down. Also, in response to the high-level mode signal MD, the control logic  923 _ 1  may output an activated first switch signal SW 1 , so that the ground voltage GND may be provided as the first control signal CTR 1  to the first NFET N 91 . In addition, in response to the high-level mode signal MD, the control logic  923 _ 1  may output an activated second switch signal SW 2 , so that the positive supply voltage VDD may be provided as the second control signal CTR 2  to the second NFET N 92 . As a result, the first NFET N 91  may be turned off, and the second NFET N 92  may be turned on. Thus, an on-resistance Ron of the OVP switch  910  may correspond to the second resistance R 2  higher than the first resistance R 1 . 
     At a time point t 13 , an overvoltage may occur at the CC 1  pin A 5  and, thus, the detection signal DET may transition to a high level. In response to an activated detection signal DET, the control logic  923 _ 1  may output a deactivated second switch signal SW 2 , so that the second control signal CTR 2  may have a ground voltage GND due to the second switch  923 _ 3 . Thus, the second NFET N 92  may be turned off, and the OVP switch  910  may be turned off. 
     At a time point t 14 , the overvoltage may be eliminated at the CC 1  pin A 5  and, thus, the detection signal DET may transition to a low level. In response to a deactivated detection signal DET, the control logic  923 _ 1  may output an activated second switch signal SW 2 , so that the second control signal CTR 2  may have a positive supply voltage VDD. 
     Referring to  FIG. 11B , in some embodiments, the switch controller  920  may turn off the first NFET N 91  in a low-power mode, and simultaneously turn on or off the first NFET N 91  and the second NFET N 92  in the normal mode. Thus, the on-resistance Ron of the OVP switch  910  may be dependent on the first NFET N 91  and the second NFET N 92 , which are connected in parallel, in the normal mode, and dependent only on the second NFET N 92  in the low-power mode. The first NFET N 91  may receive an output voltage V_OUT from the charge pump  921 . Since the first NFET N 91  and the second NFET N 92  are turned on together, when an overvoltage does not occur at the CC 1  pin A 5 , the OVP switch  910  may have the first resistance R 1  as the on-resistance Ron in the normal mode and the second resistance R 2 , higher than the first resistance R 1 , in the low-power mode. 
     As shown in  FIG. 11B , until the time point t 10 , the control logic  923 _ 1  may output an deactivated first switch signal SW 1  and output an activated second switch signal SW 2  in response to a deactivated detection signal DET. Thus, the first control signal CTR 1  and the second control signal CTR 2  may have an output voltage V_OUT and a positive supply voltage VDD, respectively, and both the first NFET N 91  and the second NFET N 92  may be turned on. 
       FIG. 12  is a flowchart of a method of protecting an overvoltage in a USB interface according to an example embodiment. Specifically,  FIG. 12  illustrates examples of operation S 91  and operation S 93  of  FIG. 4 . For example, the method of  FIG. 12  may be performed by the switch controller  50  of  FIG. 5 . Hereinafter, the flowchart of  FIG. 12  will be described with reference to  FIGS. 4 and 5 . 
     Subsequently to operation S 50  of  FIG. 4 , in operation S 70 ′, the switch controller  50  may determine a mode of a USB device (e.g.,  300  of  FIG. 3 ) based on a mode signal MD. When the mode signal MD corresponds to a normal mode, operation S 91 ′ may be subsequently performed. When the mode signal MD corresponds to a low-power mode, operation S 93 ′ may be subsequently performed. 
     When the mode signal MD corresponds to the normal mode, in operation S 91 ′, an operation of setting an on-resistance Ron of an OVP switch (e.g.,  351  of  FIG. 3 ) as a first resistance R 1  may be performed. As shown in  FIG. 12 , operation S 91 ′ may include operation S 91 _ 1 . In operation S 91 _ 1 , an operation of providing an output voltage V_OUT of the charge pump  51  to the OVP switch may be performed. The output voltage V_OUT may be a voltage boosted by the charge pump  51 . Thus, the OVP switch may have a relatively low on-resistance Ron, i.e., the first resistance R 1 . Subsequently to operation S 91 ′, operation S 10  of  FIG. 4  may be performed. 
     When the mode signal MD corresponds to the low-power mode, in operation S 93 ′, an operation of setting the on-resistance Ron of the OVP switch (e.g.,  351  of  FIG. 3 ) as a second resistance R 2  may be performed. As shown in  FIG. 12 , operation S 93 ′ may include operation S 93 _ 1 . In operation S 93 _ 1 , an operation of powering the charge pump  51  down may be performed. As a result, power consumption may be reduced and efficiency of the low-power mode may be improved. Subsequently to operation S 93 ′, operation S 10  of  FIG. 4  may be performed. 
     By way of summation and review, one or more embodiments may provide a circuit and method of protecting an overvoltage. One or more embodiments may provide a circuit and method of reducing power consumption. One or more embodiments may provide a circuit and method of providing different on-resistances in accordance with a mode and/or overcharge detection. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.