Patent Publication Number: US-2023155003-A1

Title: Structure of isolation feature of semiconductor device structure

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of pending U.S. patent application Ser. No. 16/858,891, filed Apr., 27, 2020 and entitled “FORMATION METHOD OF ISOLATION FEATURE OF SEMICONDUCTOR DEVICE STRUCTURE”, which is a Divisional of pending U.S. patent application Ser. No. 15/663,089, filed Jul., 28, 2017 and entitled “STRUCTURE AND FORMATION METHOD OF ISOLATION FEATURE OF SEMICONDUCTOR DEVICE STRUCTURE”, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. 
     In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. 
     Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three-dimensional transistor, such as a semiconductor device with fin field-effect transistors (FinFETs), has been introduced to replace planar transistors. These relatively new types of semiconductor IC devices face manufacturing challenges, and they have not been entirely satisfactory in all respects. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A,  2 A,  3 A,  4 A,  5 A,  6 A,  7 A,  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A, and  15 A  are perspective views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. 
         FIGS.  1 B,  2 B,  3 B,  4 B,  5 B,  6 B,  7 B,  8 B,  9 B,  10 B,  11 B,  12 B,  13 B,  14 B, and  15 B  are top views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. 
         FIGS.  5 C and  7 C  are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. 
         FIG.  16    is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. 
         FIG.  17    is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. 
         FIG.  18    is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embodiments of the disclosure form a semiconductor device structure with FinFETs. The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. 
     Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated and additional features can be added for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. 
       FIGS.  1 A,  2 A,  3 A,  4 A,  5 A,  6 A,  7 A,  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A, and  15 A  are perspective views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. For a better understanding of the semiconductor device structure, an X-Y-Z coordinate reference is provided in these figures. The X-axis is generally orientated along a substrate surface of a semiconductor device structure in the lateral direction. The Y-axis is generally oriented along the substrate surface perpendicular to the X-axis. The Z-axis is generally oriented along the substrate surface in the vertical direction perpendicular to the X-Y plane. 
       FIGS.  1 B,  2 B,  3 B,  4 B,  5 B,  6 B,  7 B,  8 B,  9 B,  10 B,  11 B,  12 B,  13 B,  14 B, and  15 B  are top views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. In some embodiments,  FIGS.  1 B,  2 B,  3 B,  4 B,  5 B,  6 B,  7 B,  8 B,  9 B,  10 B,  11 B,  12 B,  13 B,  14 B, and  15 B  respectively show a cross-sectional view in the X-Y plane of the semiconductor device structure shown in  FIGS.  1 A,  2 A,  3 A,  4 A,  5 A,  6 A,  7 A,  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A, and  15 A . 
     As shown in  FIG.  1 A , a semiconductor substrate  100  is provided. The surface of the semiconductor substrate  100  is substantially parallel to the X-Y plane. In some embodiments, the semiconductor substrate  100  is a bulk semiconductor substrate, such as a semiconductor wafer. In some embodiments, the semiconductor substrate  100  includes silicon or another elementary semiconductor material such as germanium. For example, the semiconductor substrate  100  is a silicon wafer. In some other embodiments, the semiconductor substrate  100  includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof. 
     In some embodiments, the semiconductor substrate  100  includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, another applicable method, or a combination thereof. 
     A hard mask structure is formed over the semiconductor substrate  100 . Mask layers  110 ,  120 ,  130  and  140  of the hard mask structure are shown in  FIG.  1 A  as an example, but embodiments of the disclosure are not limited thereto. The hard mask structure may include less or more layers than those shown in  FIG.  1 A . 
     In some embodiments, the mask layers  110 ,  120 ,  130  and  140  are made of or include silicon nitride, silicon oxide, silicon oxynitride, carbon-doped oxide, silicon carbide, one or more other suitable materials, or a combination thereof. For example, the mask layers  110 ,  120 ,  130  and  140  may be made of silicon nitride, silicon oxide, carbon-doped oxide and silicon nitride, respectively. The hard mask structure may include oxide-nitride-oxide (ONO) layers. In some embodiments, each of the mask layers  110 ,  120 ,  130  and  140  is deposited using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, one or more other applicable processes, or a combination thereof. 
     As shown in  FIGS.  1 A and  1 B , the mask layer  140  of the hard mask structure is patterned, in accordance with some embodiments. In some embodiments, one or more photolithography and etching processes are used to form multiple recesses or trenches in the mask layer  140 . As a result, multiple fin-shaped features  140 A are formed between the recesses. The mask layer  130  becomes partially exposed during and after the etching process. In some embodiments, the mask layer  130  serves as an etching stop layer during the etching process. 
     In some embodiments, the fin-shaped features  140 A extend along the X-axis and are arranged in a direction that is substantially parallel to the Y-axis, as shown in  FIGS.  1 A and  1 B . The pitch between the fin-shaped features  140 A (along the Y-axis) may or may not be the same. The thickness of the fin-shaped features  140 A (along the Y-axis) may or may not be the same. The length or width of the fin-shaped features  140 A (along the X-axis) may or may not be the same. 
     As shown in  FIGS.  1 A and  1 B , multiple openings  150  are formed in the patterned mask layer  140 , in accordance with some embodiments. Each of the openings  150  is positioned between two of the fin-shaped features  140 A so as to separate and isolate them from each other. Alternatively, it may be referred to as that one fin pattern is cut into two fin-shaped features  140 A by one of the openings  150 . 
     The openings  150  are arranged in a direction that is substantially parallel to the Y-axis. In some embodiments, the openings  150  are arranged in multiple lines, as shown in  FIG.  1 B . However, embodiments of the disclosure are not limited thereto. In some other embodiments, the openings  150  align to each other and are arranged in a line. The openings  150  may not be arranged in a line. 
     The openings  150  have a width W 1  along the X-axis, as shown in  FIG.  1 B . In some embodiments, the width W 1  is in a range from about 15 nm to about 20 nm, but embodiments of the disclosure are not limited thereto. In some embodiments, the openings  150  are formed during the formation of the fin-shaped features  140 A. 
     As shown in  FIGS.  2 A and  2 B , a capping layer  160  is deposited over the mask layer  140 , in accordance with some embodiments. The capping layer  160  covers the fin-shaped features  140 A and partially fills the openings  150 , as shown in  FIG.  2 A . As a result, the openings  150  become narrower and shrink due to the deposition of the capping layer  160 . 
     In some embodiments, the thickness of the capping layer  160  is in a range from about 3 nm to about 5 nm, but embodiments of the disclosure are not limited thereto. In some embodiments, the capping layer  160  is made of or includes silicon nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the capping layer  160  and the mask layer  140  are made of or include the same material. In some embodiments, the capping layer  160  is deposited using an ALD process, one or more other applicable processes, or a combination thereof. In some embodiments, the capping layer  160  is deposited conformally or uniformly. 
     The capping layer  160  will be removed during a subsequent process and therefore may be referred to as a sacrificial capping layer. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the capping layer  160  is not formed. 
     Afterwards, one or more photolithography and etching processes are performed over the mask layer  140 . The mask layers  140  and  130  are removed, as shown in  FIGS.  3 A and  3 B . The mask layers  120  and  110  are patterned so that multiple recesses or trenches are formed in the mask layers  120  and  110 . As a result, multiple fin-shaped features  120 A are formed between the recesses, as shown in  FIGS.  3 A and  3 B . The semiconductor substrate  100  becomes partially exposed during and after the etching process. In some embodiments, the capping layer  160  is removed during the etching process for patterning the mask layers  120  and  110 . 
     In some embodiments, the fin-shaped features  120 A and the fin-shaped features  140 A have similar or substantially the same pattern or arrangement (such as position, shape and dimension). In some embodiments, the fin-shaped features  120 A are slightly wider than the fin-shaped features  140 A due to the shrinkage of the openings  150 . 
     As shown in  FIGS.  3 A and  3 B , multiple openings  170  are formed in the patterned mask layers  120  and  110 , in accordance with some embodiments. Each of the openings  170  is positioned between two of the fin-shaped features  120 A so as to separate and isolate them from each other. 
     In some embodiments, the openings  170  and the openings  150  have similar or substantially the same pattern or arrangement (such as position, shape and dimension). In some embodiments, the openings  170  are slightly narrower than the openings  150  due to the deposition of the capping layer  160 . The openings  170  have a width W 2  along the X-axis, as shown in  FIG.  3 B . In some embodiments, the width W 2  is in a range from about 10 nm to about 15 nm, but embodiments of the disclosure are not limited thereto. In some embodiments, the openings  170  are formed during the formation of the fin-shaped features  120 A. 
     As shown in  FIGS.  4 A and  4 B , a capping layer  180  is deposited over the mask layer  120 , in accordance with some embodiments. The capping layer  180  covers the fin-shaped features  120 A and partially fills the openings  170 , as shown in  FIG.  4 A . As a result, the openings  170  become narrower and shrink due to the deposition of the capping layer  180 . In some embodiments, the thickness of the capping layer  180  is in a range from about 3 nm to about 5 nm, but embodiments of the disclosure are not limited thereto. The thickness of the capping layer  180  may or may not be equal to the thickness of the capping layer  160 . 
     In some embodiments, the capping layer  180  is made of or includes silicon oxide, one or more other suitable materials, or a combination thereof. In some embodiments, the capping layer  180  and the mask layer  120  are made of or include the same material. The capping layer  180  and the capping layer  160  are made of or include different materials. In some embodiments, the capping layer  180  is deposited using an ALD process, one or more other applicable processes, or a combination thereof. In some embodiments, the capping layer  180  is deposited conformally or uniformly. 
     The capping layer  180  will be removed during a subsequent process and therefore may be referred to as a sacrificial capping layer. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the capping layer  180  is not formed. 
     Afterwards, one or more photolithography and etching processes are performed over the mask layer  120 . The mask layer  120  is thinned, as shown in  FIG.  5 A . The semiconductor substrate  100  is patterned so that multiple recesses (or trenches)  105  are formed in the semiconductor substrate  100 . As a result, multiple fin structures  100 A are formed between the recesses  105 , as shown in  FIGS.  5 A and  5 B . In some embodiments, the capping layer  180  is removed during the etching process for patterning the semiconductor substrate  100 . 
     In some embodiments, the fin structures  100 A and the fin-shaped features  120 A have similar or substantially the same pattern or arrangement (such as position, shape and dimension). The fin structures  100 A have a thickness T along the Y-axis, as shown in  FIGS.  5 A and  5 B . In some embodiments, the thickness T is in a range from about 8 nm to about 12 nm, but embodiments of the disclosure are not limited thereto. 
       FIG.  5 C  is a cross-sectional view of one stage of a process for forming a semiconductor device structure, in accordance with some embodiments. In some embodiments,  FIG.  5 C  is a cross-sectional view in the X-Z plane of the structure shown in  FIG.  5 A . As shown in  FIGS.  5 A,  5 B and  5 C , multiple openings  200  are formed in the fin structures  100 A, in accordance with some embodiments. The openings  200  are formed during the formation of the fin structures  100 A, but embodiments of the disclosure are not limited thereto. 
     As shown in  FIGS.  5 A and  5 C , the openings  200  extend from the openings  170  downwards into the fin structures  100 A without penetrating the fin structures  100 A or the semiconductor substrate  100 . Each of the openings  200  is embedded in one of the fin structures  100 A. Alternatively, it may be referred to as that one of the fin structures  100 A is partially cut into two fin patterns by one of the openings  200 . 
     In some embodiments, the openings  200  and the openings  170  have similar or substantially the same pattern or arrangement (such as position, shape and dimension). The mask layer  140  shown in  FIG.  1 A  may have a pattern corresponding to the openings  200 . In some embodiments, the openings  200  are slightly narrower than the openings  170  due to the deposition of the capping layer  180 . The openings  200  have a width W 3  along the X-axis, as shown in  FIGS.  5 B and  5 C . In some embodiments, the width W 3  is in a range from about 8 nm to about 12 nm, but embodiments of the disclosure are not limited thereto. The openings  200  have a depth D 1  along the Y-axis, as shown in  FIG.  5 C . In some embodiments, the depth D 1  is in a range from about 70 nm to about 150 nm, but embodiments of the disclosure are not limited thereto. 
     In some embodiments, the openings  200  gradually shrink along a direction from the fin structures  100 A towards the semiconductor substrate  100 , as shown in  FIG.  5 C . In other words, the openings  200  shrink downwardly along the Z-axis. In some embodiments, the profile of the openings  200  in the X-Z plane is inverted triangle, as shown in  FIG.  5 C . The bottom of the openings  200  may be a tip. It should be noted that the profile shown in figures is only an example and is not a limitation to the disclosure. 
     In some cases, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. For example, forming features at smaller sizes using photolithography and etching processes faces challenges and limitations. 
     In accordance with some embodiments, one or more capping layers (such as the capping layer  160  and the capping layer  180 ) are deposited so as to reduce the dimension of the openings  200  for forming smaller features. The dimension of the narrowed openings  200  can be fine-tuned by alerting the thickness of the capping layer(s). It becomes flexible to control the dimensions of the openings  200 . Accordingly, even if photolithography and/or etching processes for forming the openings  200  face critical limitations or challenges, the described formation method can be applied to form the openings  200  with much smaller sizes. 
     However, embodiments of the disclosure are not limited thereto. In some other embodiments, the described stages shown in  FIGS.  2 A and  2 B  and/or  FIGS.  4 A and  4 B  are eliminated. 
     Afterwards, an isolation layer  210  is deposited over the mask layer  120 , as shown in  FIGS.  6 A and  6 B . The isolation layer  210  partially fills the recesses  105  between the fin structures  100 A. The fin structures  100 A are covered and surrounded by the isolation layer  210 . The isolation layer  210  further fills the openings  200  and the openings  170 . 
     The isolation layer  210  is made of a dielectric material. The dielectric material may be a low dielectric constant (low-k) material or another suitable isolation material. The low-k material may have a smaller dielectric constant than that of silicon dioxide. For example, the low-k material may have a dielectric constant in a range from about 1.5 to about 3.5. In some embodiments, the isolation layer  210  is made of or includes SiOCN, SiCN, SiOC, one or more other suitable materials, or a combination thereof. In some embodiments, the isolation layer  210  and the mask layers  120  and  110  are made of or include different materials. 
     In some embodiments, the isolation layer  210  is deposited using an ALD process, a PVD process, a CVD process, one or more other applicable processes, or a combination thereof. In some embodiments, the isolation layer  210  is deposited conformally or uniformly. In some embodiments, the isolation layer  210  is deposited until the openings  200  are fully filled with the isolation layer  210 . 
     Subsequently, one or more photolithography and etching processes are performed over the isolation layer  210  until the fin structures  100 A become exposed, as shown in  FIGS.  7 A and  7 B . The isolation layer  210  covering the fin structures  100 A may be removed using cycle of multiple etching processes. In some embodiments, the etchant for removing the isolation layer  210  is made of or includes ozone (O 3 ), dilute hydrofluoric acid (HF), one or more other suitable etchants, or a combination thereof. For example, the isolation layer  210  may be removed by O 3  and/or HF, but embodiments of the disclosure are not limited thereto. The isolation layer  210  may be oxidized first using an ashing process and then removed by O 3  and/or HF. 
     After the etching processes, some portions of the isolation layer  210  in the recesses  105  are removed while other portions of the isolation layer  210  remain in the openings  200  and the openings  170 . As a result, the remaining portions of the isolation layer  210  in the openings  200  and the openings  170  form multiple isolation features  210 A. The isolation features  210 A are used to electrically isolate active gate stacks or various devices (such as transistors) in multiple active regions from each other, which will be described in more detail later. 
     It should be noted that the isolation features  210 A may have rounded edges or corners due to the etching processes. The rounded parts of the isolation features  210 A are not shown in figures for the purpose of simplicity and clarity. 
       FIG.  7 C  is a cross-sectional view of one stage of a process for forming a semiconductor device structure, in accordance with some embodiments. In some embodiments,  FIG.  7 C  is a cross-sectional view in the X-Z plane of the structure shown in  FIG.  7 A . As shown in  FIGS.  7 A,  7 B and  7 C , the isolation features  210 A are embedded in the mask layers  120  and  110  and the fin structures  100 A, in accordance with some embodiments. Each of the isolation features  210 A is positioned between one of the fin structures  100 A so as to partially separate it into two fin patterns. One of the isolation features  210 A is sandwiched between two fin patterns. In some embodiments, the isolation features  210 A are in direct contact with the fin structures  100 A. 
     The isolation features  210 A and the fin structures  100 A may have the same thickness T. In some embodiments, the thickness of the isolation features  210 A (shown in  FIG.  7 A ) is in a range from about 8 nm to about 12 nm, such as about 10 nm. In some embodiments, the width W 3  of the isolation features  210 A (shown in  FIGS.  7 B and  7 C ) is in a range from about 8 nm to about 12 nm, such as about 10 nm. In some embodiments, the depth D 1  of the isolation features  210 A in the fin structures  100 A (shown in  FIG.  7 C ) is in a range from about 70 nm to about 150 nm. 
     In some embodiments, the isolation features  210 A gradually shrink along a direction from the fin structures  100 A towards the semiconductor substrate  100 , as shown in  FIG.  7 C . The bottom of the isolation features  210 A may be a tip in the fin structures  100 A. In some embodiments, the profile of the isolation features  210 A in the X-Z plane is inverted triangle or V-shaped. 
     As shown in  FIGS.  8 A and  8 B , an isolation layer  220  is deposited over the fin structures  100 A, in accordance with some embodiments. The isolation layer  220  fills the recesses  105  and surrounds the fin structures  100 A. In some embodiments, the isolation layer  220  is in direct contact with the isolation features  210 A. 
     The isolation layer  220  is made of or includes a dielectric material. In some embodiments, the isolation layer  220  is made of or includes silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, low-K dielectric material, one or more other suitable materials, or a combination thereof. In some embodiments, the isolation layer  220  and the isolation layer  210  are made of or include different materials. In some embodiments, the isolation layer  220  is deposited using a CVD process, a spin-on process, one or more other applicable processes, or a combination thereof. 
     In some embodiments, the isolation layer  220  is deposited over the mask layer  120 . A planarization process is then performed to thin down the isolation layer  220  until the isolation features  210 A are exposed. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, one or more other applicable processes, or a combination thereof. 
     In some embodiments, the mask layer  110  serves as a polishing stop layer during the CMP process. The planarization process is performed over the mask layer  120  until the mask layer  110  becomes exposed. As a result, the mask layer  120  is removed after the planarization process, as shown in  FIG.  8 A . The isolation features  210 A may be partially removed during the planarization process. For example, the upper portion of the isolation features  210 A (in the openings  170 ) may be removed. 
     Afterwards, in some embodiments, the exposed mask layer  110  is removed using an etching process (such as a wet etching process), one or more other applicable processes, or a combination thereof. The isolation features  210 A may or may not be partially removed during the removal of the mask layer  110 . The isolation layer  220  is then etched back to expose upper portions of the fin structures  100 A. Some portions of the isolation layer  220  remain in the recesses  105  and envelope lower portions of the fin structures  100 A. As a result, the remaining portions of the isolation layer  220  in the recesses  105  form isolation features  220 A, as shown in  FIGS.  9 A and  9 B . In some embodiments, the isolation layer  220  is etched such that the isolation layer  220  becomes lower than the fin structures  100 A but remains higher than the isolation features  220 A. 
     In accordance with some embodiments, the isolation features  210 A is substantially not removed during the partial removal of the isolation layer  220  (i.e., the formation of the isolation features  220 A). The material of the isolation features  210 A is selected such that the etchant has a sufficiently high etching selectivity of the isolation layer  220  to the isolation features  210 A. In other words, the isolation layer  220  is etched much faster than the isolation features  210 A. In some embodiments, the etching selectivity to the isolation layer  220  of the isolation features  210 A is in a range from about  50  to about  100 , but embodiments of the disclosure are not limited thereto. 
     The isolation features  220 A are used to electrically isolate various device elements, which will be formed in and/or over the fin structures  100 A. The isolation features  220 A surround lower portions of the fin structures  100 A. The upper portions of the fin structures  100 A protrude from the isolation features  220 A. In some embodiments, the bottom of the isolation features  210 A is covered by and embedded in the isolation features  220 A. The upper portions (or the top) of the isolation features  210 A protrude from the isolation features  220 A. One of the isolation features  210 A is partially sandwiched between two of the isolation features  220 A. 
     The isolation features  220 A may be referred to as shallow trench isolation (STI) features. The isolation features  220 A may or may not have a multi-layer structure. For example, the isolation features  220 A may include the isolation layer  220  and an STI liner (not shown) underlying the isolation layer  220 . The STI liner may separate the isolation layer  220  and the isolation features  210 A. The STI liner may be used to reduce defects at the interface between the semiconductor substrate  100  and the isolation layer  220 . Similarly, the STI liner may also be used to reduce defects at the interface between the fin structures  100 A and the isolation layer  220 . 
     As shown in  FIGS.  10 A and  10 B , a gate dielectric layer  230  is conformally or uniformly deposited over the fin structures  100 A, in accordance with some embodiments. The gate dielectric layer  230  extends over the upper portions of the fin structures  100 A and covers the isolation features  210 A between the fin structures  100 A. In some embodiments, the gate dielectric layer  230  is in direct contact with the isolation features  210 A. The gate dielectric layer  230  partially fills the recesses  105  and covers the isolation features  220 A. In some embodiments, the gate dielectric layer  230  is in direct contact with the isolation features  220 A. 
     In some embodiments, the gate dielectric layer  230  is a sacrificial or dummy gate dielectric layer and will be replaced with another gate dielectric layer. In some embodiments, the gate dielectric layer  230  is made of a high-K dielectric material. Examples of high-K dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, silicon oxynitride, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-K material, and a combination thereof. In some embodiments, the gate dielectric layer  230  and the isolation features  210 A are made of or include different materials. In some embodiments, the gate dielectric layer  230  is deposited using an ALD process, a CVD process, one or more other applicable processes, or a combination thereof. 
     Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, before the deposition of the gate dielectric layer  230 , an interfacial layer (not shown) is deposited over the fin structures  100 A. The interfacial layer may be used to reduce stress between the gate dielectric layer  230  and the fin structures  100 A. In some embodiments, the interfacial layer is made of silicon oxide. In some embodiments, the interfacial layer is formed using an ALD process, a thermal oxidation process, one or more other applicable processes, or a combination thereof. 
     As shown in  FIGS.  11 A and  11 B , multiple gate electrodes  240  are formed over the gate dielectric layer  230 , in accordance with some embodiments. The gate electrodes  240  extend along the Y-axis and are arranged in a direction that is substantially parallel to the X-axis. The gate electrodes  240  partially cover the fin structures  100 A. One or more of the gate electrodes  240  cover the isolation features  210 A, as shown in  FIG.  11 B . In some embodiments, the gate electrodes  240  surround the fin structures  100 A and the isolation features  210 A. 
     In some embodiments, the gate electrodes  240  include polysilicon, a metal material, another suitable conductive material, or a combination thereof. In some embodiments, the gate electrodes  240  are sacrificial or dummy gate electrodes (such as polysilicon gate electrodes) and will be replaced with other gate electrodes such as metal gate electrodes. In some embodiments, the gate electrodes  240  and the gate dielectric layer  230  covered by the gate electrodes  240  together form gate stacks. In some embodiments, the gate stacks are sacrificial or dummy gate stacks and will be replaced with metal gate stacks. 
     A hard mask structure is formed over the gate dielectric layer  230 . Patterned mask layers  250  and  260  of the hard mask structure are shown in  FIG.  11 A  as an example, but embodiments of the disclosure are not limited thereto. The hard mask structure may include less or more layers than those shown in  FIG.  11 A . 
     In some embodiments, as shown in  FIG.  11 B , the mask layer  260  covers and overlaps the isolation features  210 A. The mask layer  250 , the gate electrodes  240  and the gate dielectric layer  230  also overlaps the isolation features  210 A. In some embodiments, the isolation features  210 A are directly under the dummy gate stacks. 
     In some embodiments, the mask layers  250  and  260  are made of or include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination thereof. The mask layers  250  and  260  of the hard mask structure may be used to assist in the patterning process for forming the gate electrodes  240 . 
     For example, in some embodiments, a gate electrode layer and the mask layers  250  and  260  are sequentially deposited by using suitable deposition methods. The suitable deposition methods may include a CVD process, an ALD process, a thermal oxidation process, a PVD process, one or more other applicable processes, or a combination thereof. Afterwards, a photolithography process and an etching process are performed to pattern the deposited mask layers  250  and  260 . With the assistance of the patterned mask layers  250  and  260 , the gate electrode layer are etched and patterned. As a result, multiple gate electrodes  240  are formed. In some embodiments, the gate dielectric layer  230  serves as an etching stop layer during the formation of the gate electrodes  240 . 
     Subsequently, spacer elements  270  are formed over sidewalls of the gate electrodes  240  and the mask layers  250  and  260 , as shown in  FIGS.  12 A and  12 B  in accordance with some embodiments. Some portions of the gate dielectric layer  230 , which are not covered by the gate electrodes  240  and the spacer elements  270 , are removed after the formation of the spacer elements  270 . 
     Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, some portions of the gate dielectric layer  230 , which are not covered by the gate electrodes  240 , are removed before the formation of the spacer elements  270 . The spacer elements  270  are then formed over sidewalls of the gate dielectric layer  230 , the gate electrodes  240  and the mask layers  250  and  260 . 
     In some embodiments, the spacer elements  270  are made of or include silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, one or more other suitable materials, or a combination thereof. In some embodiments, a spacer layer is deposited using a CVD process, a PVD process, a spin-on process, one or more other applicable processes, or a combination thereof. Afterwards, an etching process, such as an anisotropic etching process, is performed to partially remove the spacer layer. As a result, the remaining portions of the spacer layer form the spacer elements  270 . 
     Although each of the spacer elements  270  shown in figures is a single layer, embodiments of the disclosure are not limited thereto. In some other embodiments, each of the spacer elements  270  has a multi-layer structure. For example, each of the spacer elements  270  may include multiple nitride layers. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the spacer elements  270  are not formed. 
     As shown in  FIGS.  12 A and  12 B , source or drain (S/D) structures  280  are formed over the fin structures  100 A, in accordance with some embodiments. The S/D structures  280  may be used to provide stress or strain to channel regions in the fin structures  100 A below the gate electrodes  240 . As a result, the carrier mobility of the device and device performance are improved. 
     As shown in  FIGS.  12 A and  12 B , two of the S/D structures  280  are on opposite sides of one of the gate electrodes  240 . One of the S/D structures  280  is between two of the gate electrodes  240 . In some embodiments, the S/D structures  280  adjoin the fin structures  100 A and the spacer elements  270 . In some embodiments, some of the S/D structures  280  adjoin each other while some of the S/D structures  280  are separated from each other. However, embodiments of the disclosure are not limited thereto. In some other embodiments, the S/D structures  280  are separated from one another. 
     In some embodiments, some portions of the fin structures  100 A, which are not covered by the gate dielectric layer  230  and the spacer elements  270 , are recessed to be lower than the gate dielectric layer  230 . Afterwards, the S/D structures  280  are grown over the fin structures  100 A that are recessed, as shown in  FIG.  12 A . In some embodiments, some portions of the fin structures  100 A are recessed to be lower than the top surface of the isolation features  220 A. As a result, the S/D structures  280 , which are grown over the recessed fin structures  100 A, extend into the isolation features  220 A, as shown in  FIG.  12 A . 
     In some embodiments, the depth of the S/D structures  280  in the fin structures  100 A is in a range from about 50 nm to about 60 nm, but embodiments of the disclosure are not limited thereto. In some embodiments, the S/D structures  280  are diamond shaped due to a crystalline structure, but embodiments of the disclosure are not limited thereto. 
     In some embodiments, one or more etching operations are performed to recess and remove the upper portions of the fin structures  100 A. It should be noted that embodiments of the disclosure have many variations. In some other embodiments, the fin structures  100 A are not partially removed before the growth of the S/D structures  280 . 
     In some embodiments, a semiconductor material (or two or more semiconductor materials) is epitaxially grown over the fin structures  100 A that are recessed. The semiconductor material is growing continually to form the S/D structures  280 . In some embodiments, the S/D structures  280  are a P-type semiconductor material. For example, the S/D structures  280  may include epitaxially grown silicon or epitaxially grown silicon germanium. The S/D structures  280  are not limited to being a P-type semiconductor material. In some embodiments, the S/D structures  280  are an N-type semiconductor material. The S/D structures  280  may include epitaxially grown silicon, silicon-germanium (SiGe), epitaxially grown phosphorous-doped silicon (SiP), boron-doped silicon germanium (SiGeB) or another suitable epitaxially grown semiconductor material. 
     In some embodiments, the S/D structures  280  are formed using a selective epitaxy growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low pressure CVD (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, deposition of doped amorphous semiconductor (e.g. Si, Ge or SiGe) followed by a solid-phase epitaxial recrystallization (SPER) step, one or more other applicable processes, or a combination thereof. The formation process of the S/D structures  280  may use gaseous and/or liquid precursors. In some embodiments, the S/D structures  280  are grown in-situ in the same process chamber. In other words, the S/D structures  280  are formed using an in-situ epitaxial growth process. In some other embodiments, some of the S/D structures  280  are grown separately. 
     In some embodiments, the S/D structures  280  are doped with one or more suitable dopants. For example, the S/D structures  280  are Si source or drain features doped with phosphorus (P), arsenic (As), or another suitable dopant. Alternatively, the S/D structures  280  are SiGe source or drain features doped with boron (B) or another suitable dopant. In some embodiments, multiple implantation processes are performed to dope the S/D structures  280 . 
     In some embodiments, the S/D structures  280  are doped in-situ during the growth of the S/D structures  280 . In some other embodiments, the S/D structures  280  are not doped during the growth of the S/D structures  280 . After the epitaxial growth, the S/D structures  280  are doped in a subsequent process. In some embodiments, the doping is achieved using an ion implantation process, a plasma immersion ion implantation process, a gas and/or solid source diffusion process, one or more other applicable processes, or a combination thereof. In some embodiments, the S/D structures  280  are further exposed to annealing processes to activate the dopants. For example, a rapid thermal annealing process is performed. 
     As shown in  FIGS.  13 A and  13 B , a capping layer  290  is deposited over the S/D structures  280 , in accordance with some embodiments. The capping layer  290  covers and surrounds the S/D structures  280 . In some embodiments, the capping layer  290  is in direct contact with the S/D structures  280 . The capping layer  290  may also cover the isolation features  220 A, the spacer elements  270 , and the mask layers  250  and  260 . The capping layer  290  may be used to protect the S/D structures  280  from oxidation during an annealing process. The capping layer  290  may also be used to assist in a subsequent etching process, which will be described in more detail later. The capping layer  290  may be referred to as a contact etch stop layer (CESL). 
     In some embodiments, the capping layer  290  is made of or includes silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, one or more other suitable materials, or a combination thereof. In some embodiments, the capping layer  290  is deposited using a CVD process, a PVD process, a spin-on process, one or more other applicable processes, or a combination thereof. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the capping layer  290  is not formed. 
     As shown in  FIGS.  13 A and  13 B , a dielectric layer  300  is deposited over the capping layer  290 , in accordance with some embodiments. The dielectric layer  300  surrounds the S/D structures  280 , the spacer elements  270 , the mask layers  250  and  260 , the gate electrodes  240  and the isolation features  210 A. The dielectric layer  300  may be referred to as an interlayer dielectric (ILD) layer. 
     In some embodiments, the dielectric layer  300  includes silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-K material, porous dielectric material, another suitable dielectric material, or a combination thereof. The material of the dielectric layer  300  is selected to minimize propagation delays and crosstalk between nearby conductive features. In some embodiments, the dielectric layer  300  is deposited using a CVD process, a spin-on process, an ALD process, a PVD process, one or more other applicable processes, or a combination thereof. 
     Afterwards, the dielectric layer  300  may be thinned down until the gate electrodes  240  are exposed. As a result, the mask layers  250  and  260  are removed. Some portions of the capping layer  290  over the gate electrodes  240  and the spacer elements  270  are removed. In some embodiments, a planarization process is performed to thin down the dielectric layer  300 . The planarization process may include a CMP process, a grinding process, an etching process, one or more other applicable processes, or a combination thereof. In some embodiments, the etching process includes a dry etching process, a wet etching process or another applicable etching process. 
     Afterwards, the sacrificial or dummy gate stacks are replaced with metal gate stacks, in accordance with some embodiments. As shown in  FIGS.  14 A and  14 B , the sacrificial gate stacks including the gate dielectric layer  230  and the gate electrodes  240  are replaced with metal gate stacks including a gate dielectric layer  310  and a gate electrode  320 . Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the gate dielectric layer  230  and the gate electrodes  240  form active gate stacks and are not replaced with other gate stacks. 
     In some embodiments, the gate dielectric layer  230  and the gate electrodes  240  are removed using a wet etching process, a dry etching process, one or more other applicable processes, or a combination thereof. As a result, trenches (not shown) are formed, and the fin structures  100 A are partially exposed through the trenches. The exposed portions of the fin structures  100 A may serve as channel regions. The isolation features  210 A may be also exposed through the trenches. 
     Afterwards, the gate dielectric layer  310  and the gate electrode  320  fill the trenches and cover the exposed portions of the fin structures  100 A and the isolation features  210 A. The gate dielectric layer  310  and the gate electrode  320  together form gate stacks. Some of the gate stacks longitudinally overlap the isolation features  210 A, as shown in  FIG.  14 B , and are therefore dummy gate stacks. Some of the gate stacks, which do not overlap the isolation features  210 A, are active gate stacks. 
     In some embodiments, the gate dielectric layer  310  is a high-K dielectric layer. The high-K dielectric layer may be made of hafnium oxide, zirconium oxide, aluminum oxide, silicon oxynitride, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-K material, or a combination thereof. In some embodiments, the gate dielectric layer  310  is deposited using an ALD process, a CVD process, a spin-on process, one or more other applicable processes, or a combination thereof. In some embodiments, a high-temperature annealing operation is performed to reduce or eliminate defects in the gate dielectric layer  310 . 
     Although the gate dielectric layer  310  shown in figures is a single layer, embodiments of the disclosure are not limited thereto. In some other embodiments, the gate dielectric layer  310  has a multi-layer structure. For example, the gate dielectric layer  310  may include an interfacial layer and a high-K dielectric layer overlying the interfacial layer. The interfacial layer may be used to reduce stress between the gate dielectric layer  310  and the fin structures  100 A. The interfacial layer may include silicon oxide or another suitable material. 
     In some embodiments, the gate electrode  320  includes one or more metal gate stacking layers overlying the gate dielectric layer  310 . It should be noted that the metal gate stacking layers are not shown in figures for the purpose of simplicity and clarity. Examples of the metal gate stacking layers include a barrier layer, one or more work function layers, a blocking layer, a glue layer, a metal filling layer, one or more other suitable metal gate layers, and combinations thereof. Some of these metal gate stacking layers can be replaced or eliminated for different embodiments. One or more additional metal gate stacking layers can be added in the gate electrode  320  for different embodiments. 
     More specifically, the barrier layer may be used to interface the gate dielectric layer  310  with the subsequently formed work function layer. The barrier layer may also be used to prevent diffusion between the gate dielectric layer  310  and the work function layer. The blocking layer may be used to prevent the metal filling layer from diffusing or penetrating into the work function layer. The glue layer may be used to increase the adhesion between the work function layer and the metal filling layer so as to prevent the metal filling layer from peeling or delamination. In some embodiments, each of the barrier layer, the blocking layer and the glue layer is made of or includes tantalum nitride, titanium nitride, another suitable material, or a combination thereof. In some embodiments, the metal filling layer is made of or includes tungsten, aluminum, copper, cobalt, another suitable material, or a combination thereof. 
     The work function layer is used to provide the desired work function for transistors to enhance device performance including improved threshold voltage (Vt). In the embodiments of forming an NMOS transistor, the work function layer can be an N-type metal layer. The N-type metal layer is capable of providing a work function value suitable for the device. The work function value may be substantially equal to or less than about 4.5 eV. The N-type metal layer may include metal, metal carbide, metal nitride, or a combination thereof. For example, the N-type metal layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. 
     On the other hand, in the embodiments of forming a PMOS transistor, the work function layer can be a P-type metal layer. The P-type metal layer is capable of providing a work function value suitable for the device. The work function value may be substantially equal to or greater than about 4.8 eV. The P-type metal layer may include metal, metal carbide, metal nitride, other suitable materials, or a combination thereof. For example, the P-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials, or a combination thereof. 
     The work function layer may also be made of hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), metal nitrides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or a combination thereof. The thickness and/or the compositions of the work function layer may be fine-tuned to adjust the work function level. For example, a titanium nitride layer may be used as a P-type metal layer or an N-type metal layer, depending on the thickness and/or the compositions of the titanium nitride layer. 
     The metal gate stacking layers are sequentially deposited by using suitable deposition methods. The suitable deposition methods may include an ALD process, a PVD process, an electroplating process, an electroless plating process, a CVD process, one or more other applicable processes, or a combination thereof. In some embodiments, the gate dielectric layer  310  and the metal gate stacking layers fill the trenches, which are formed due to the removal of the gate dielectric layer  230  and the gate electrodes  240 . In some embodiments, portions of the gate dielectric layer  310  and the metal gate stacking layers outside of the trenches are removed using a planarization process. The planarization process may include a CMP process, a grinding process, an etching process, one or more other applicable processes, or a combination thereof. The planarization process is performed until the dielectric layer  300  is exposed. As a result, multiple metal gate stacks are formed, as shown in  FIGS.  14 A and  14 B . 
     A shown in  FIGS.  15 A and  15 B , multiple conductive features  340  are formed in the dielectric layer  300 , in accordance with some embodiments. The conductive features  340  are electrically connected to one or more of the S/D structures  280 . The conductive features  340  may be referred to as conductive contacts. 
     For example, the dielectric layer  300  may be etched to form trenches or openings (not shown). A conductive material is deposited over the dielectric layer  300  to fill the trenches. In some embodiments, the conductive material is made of or includes tungsten, aluminum, copper, gold, platinum, titanium, one or more other suitable materials, or a combination thereof. In some embodiments, the conductive material is deposited using a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof. 
     A planarization process is subsequently used to remove portions of the conductive material outside of the trenches. As a result, the remaining portions of the conductive material in the trenches form the conductive features  340 . In some embodiments, the trenches in the dielectric layer  300  extend into the S/D structures  280  such that the resulting conductive features  340  extend into the S/D structures  280 , as shown in  FIG.  15 A . However, embodiments of the disclosure are not limited thereto. 
     A shown in  FIGS.  15 A and  15 B , a silicide feature  330  is formed between the conductive features  340  and the S/D structures  280 , in accordance with some embodiments. The silicide structure  330  may reduce the contact resistance and increase the conductivity of the S/D structures  280 . 
     The silicide structure  330  is made of or includes a metal material. In some embodiments, the silicide structure  330  include is made of or includes titanium silicon, nickel silicon, cobalt silicon, one or more other suitable materials, or a combination thereof. In some embodiments, the metal material is deposited using a PVD process, a CVD process, one or more other applicable processes, or a combination thereof. 
     In some embodiments, the silicide structure  330  is formed using a self-aligned silicidation (salicidation) process before the formation of the conductive features  340 . For example, the metal material is conformally deposited over the S/D structures  280 . Afterwards, an annealing process may be performed to cause the diffusion of the metal material into the S/D structures  280 . As a result, the silicide structure  330  is formed at the exposed surfaces of the S/D structures  280 . After the annealing process, a cleaning treatment may be applied to remove remaining and undiffused portions of the metal material. The resulting silicide structure  330  is self-aligned with the exposed surfaces of the S/D structures  280 . 
     Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the silicide structure  330  is not formed. 
     Subsequently, various features will be formed over the dielectric layer  300  and the conductive features  340  to continue the formation of the interconnection structure. Some of the various features are electrically connected to the conductive features  340  and the gate electrode  320 . These features may include conductive contacts, interconnection layers, conductive vias, and other suitable features. 
       FIG.  16    is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments,  FIG.  16    is a cross-sectional view taken along line I-I′ shown in  FIG.  15 A . Line I-I′ may be substantially parallel to the Y-axis. A shown in  FIG.  16   , the isolation features  220 A are over the semiconductor substrate  100 . One or more fin structures (such as lower portions  100 A′ of some of the fin structures  100 A) is in the isolation features  220 A. The gate dielectric layer  310  and the gate electrode  320  together form dummy gate stacks over the lower portions  100 A′ and the isolation features  220 A. 
     A shown in  FIG.  16   , the isolation features  210 A are between the lower portions  100 A′ and the dummy gate stacks, in accordance with some embodiments. In some embodiments, the isolation features  210 A are partially surrounded by the gate dielectric layer  310  and the gate electrode  320 . The bottom of the isolation features  210 A is embedded in the isolation features  220 A and partially surrounded by the isolation features  220 A. 
     In some embodiments, the isolation features  210 A adjoin the lower portions  100 A′, the isolation features  220 A and the gate dielectric layer  310 . In some embodiments, a portion of the isolation features  210 A is sandwiched between the lower portions  100 A′ and the gate dielectric layer  310 . In some embodiments, the interface between the isolation features  220 A and the gate dielectric layer  310  is closer to the bottom of the isolation features  210 A than the top of the isolation features  210 A. In some embodiments, the thickness of the isolation features  210 A is substantially equal to the thickness of the lower portions  100 A′ of the fin structures  100 A, as shown in  FIG.  16   . In some embodiments, the profile of the isolation features  210 A in the Y-Z plane is rectangular, as shown in  FIG.  16   , but embodiments of the disclosure are not limited thereto. 
       FIG.  17    is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments,  FIG.  17    is a cross-sectional view taken along line II-II′ shown in  FIG.  15 A . Line II-II′ may be substantially parallel to the X-axis. Line II-II′ may extend along one of the fin structures  100 A. 
     A shown in  FIG.  17   , multiple active gate stacks  350 A and a dummy gate stack  350 B are over a fin structure  100 A, in accordance with some embodiments. The active gate stacks  350 A are on two opposite sides of the dummy gate stack  350 B. Spacer elements  270  are over sidewalls of the active gate stacks  350 A and the dummy gate stack  350 B. 
     A shown in  FIG.  17   , an isolation feature  210 A is embedded in the fin structure  100 A so as to isolate the active gate stacks  350 A from each other. The isolation feature  210 A is below the active gate stacks  350 A, the dummy gate stack  350 B and the spacer elements  270 . In some embodiments, the isolation feature  210 A is directly under the dummy gate stack  350 B. The isolation feature  210 A extends into the fin structure  100 A from the bottom of the dummy gate stack  350 B. In some embodiments, the isolation feature  210 A is in direct contact with the bottom of the dummy gate stack  350 B. In some embodiments, a gate dielectric layer  310  of the dummy gate stack  350 B is sandwiched between a gate electrode  320  of the dummy gate stack  350 B and the isolation feature  210 A. 
     In some embodiments, there is only one dummy gate stack  350 B between two active gate stacks  350 A. There is only one isolation feature  210 A between two active gate stacks  350 A. The isolation feature  210 A under single dummy gate stack  350 B provides sufficient isolation between the active gate stacks  350 A so as to define various devices in multiple active regions. Accordingly, the semiconductor device structure has a decreased area. The size of the semiconductor device structure can be reduced even further to meet requirements. 
     As shown in  FIG.  17   , the isolation feature  210 A is separated from the S/D structures  280  through portions of the fin structure  100 A. Portions of the fin structure  100 A are sandwiched between the isolation feature  210 A and the S/D structures  280 . The isolation feature  210 A is spaced apart from the capping layer  290 . The isolation feature  210 A is separated from the capping layer  290  and the dielectric layer  300  by the dummy gate stack  350 B. In some embodiments, a portion of the gate dielectric layer  310  is sandwiched between the isolation feature  210 A and the gate electrode  320 . As shown in  FIG.  17   , the continuous capping layer  290  separates the dielectric layer  300  from a spacer element  270  that is over the sidewall of the dummy gate stack  350 B and from a spacer element  270  that is over the sidewall of one of the active gate stacks  350 A. 
     A shown in  FIG.  17   , the isolation feature  210 A extends deeper into the fin structure  100 A than the S/D structures  280 . As a result, the bottom of the isolation feature  210 A, which may be a tip, is lower than the bottom of the S/D structures  280 . In some embodiments, the depth D 1  of the isolation feature  210 A in the fin structure  100 A is in a range from about 70 nm to about 150 nm. In some embodiments, the depth D 2  of the S/D structures  280  is in a range from about 50 nm to about 60 nm. In some embodiments, a ratio of the depth D 1  to the depth D 2  is in a range from about 1.1 to about 2.0. The depth D 1  is greater than the depth D 2  so as to eliminate or avoid current leakage between various devices. 
     In some embodiments, the width W 3  of the isolation feature  210 A (shown in  FIGS.  7 B and  7 C ) is substantially equal to or less than the width of the dummy gate stack  350 B. The width W 3  may be less than the width of a portion of the fin structure  100 A between the S/D structures  280 , as shown in  FIG.  17   . The top surface of the isolation feature  210 A may be narrower than the distance or pitch between two of the S/D structures  280 , as shown in  FIG.  17   . 
     The isolation feature  210 A may be substantially aligned to the dummy gate stack  350 B including the gate dielectric layer  310  and the gate electrode  320 . The isolation feature  210 A may not overlap the spacer elements  270 . It can be ensured that the formation and/or the profile of the S/D structures  280  are not affected by the isolation feature  210 A. 
     For example, in some cases, the width W 3  of the isolation feature  210 A should be substantially equal to or less than about 12 nm. If the width W 3  is greater than about 12 nm, the isolation feature  210 A may affect the formation and the profile of the S/D structures  280 . 
     Although  FIG.  17    shows that the isolation feature  210 A is substantially aligned to the dummy gate stack  350 B, embodiments of the disclosure are not limited thereto. The isolation feature  210 A may shift and be misaligned to the dummy gate stack  350 B. 
       FIG.  18    is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments,  FIG.  18    is a cross-sectional view taken along line II-II′ shown in  FIG.  15 A . The structure shown in  FIG.  18    is similar to that shown in  FIG.  17   . In some embodiments, the materials and/or formation methods of the semiconductor device structure shown in  FIGS.  15 A and  15 B  can also be applied in the embodiments illustrated in  FIG.  18   , and are therefore not repeated. 
     As shown in  FIG.  18   , the isolation feature  210 A is not precisely aligned to the dummy gate stack  350 B. The isolation feature  210 A longitudinally overlaps not only the gate dielectric layer  310  and the gate electrode  320  but also one of the spacer elements  270 . 
     In some embodiments, the isolation feature  210 A is in direct contact with the dummy gate stack  350 B, one of the spacer elements  270 , and one of the S/D structures  280 . In some embodiments, one of the spacer elements  270  extends downwardly in the fin structure  100 A to adjoin the isolation feature  210 A, as indicated by a dashed circle. As a result, one of the spacer elements  270  has a bottom lower than the bottom of other spacer elements  270  and the bottom of the gate dielectric layer  310 . This spacer element  270  extends between the isolation feature  210 A and one of the S/D structures  280 , as shown in  FIG.  18   . The isolation feature  210 A may adjoin the bottom and a sidewall of the spacer elements  270 . 
     In some cases, the position of the opening  200  (shown in  FIGS.  5 A,  5 B and  5 C ) may shift in a way that is not desired. As a result, the isolation feature  210 A formed in the opening  200  may be misaligned to the dummy gate stack  350 B and have an exposed portion that is not covered by the dummy gate stack  350 B. The exposed portion of the isolation feature  210 A may adjoin the S/D structures  280 . During one or more etching processes, the exposed portion of the isolation feature  210 A may be partially etched and then removed. 
     In some embodiments, the space, which is created due to the partial removal of the exposed portion of the isolation feature  210 A, is filled with the spacer elements  270 . Accordingly, one or more of the spacer elements  270  are formed not only over the sidewalls of the dummy gate stack  350 B but also below the dummy gate stack  350 B. In some embodiments, the isolation feature  210 A and the spacer element  270  together provide electrical isolation between the active gate stacks  350 A. The possible shift of the openings  200  does not weaken the isolation between the active gate stacks  350 A. 
     According to the aforementioned embodiments, the isolation features  210 A, which are used to isolate the active gate stacks  350 A from each other, are formed before the formation of the isolation feature  220 A, the dummy gate stack  350 B and the active gate stacks  350 A. The isolation features  210 A are not formed after the formation of an ILD layer (such as the dielectric layer  300 ). The fabrication process of the isolation features  210 A does not include the removal of gate stacks, fin structures and/or other features. As a result, the fabrication process of the isolation features  210 A becomes simple. The S/D structures  280  can be prevented from being damaged during the formation of the isolation features  210 A (such as etching processes). ILD loss issues (for example, top portions of the ILD layer may be removed due to the etching processes) are also avoided. Therefore, embodiments of the disclosure provide simpler processes for forming semiconductor device structures having improved reliability. 
     Embodiments of the disclosure can be applied to not only a semiconductor device structure with N-type or P-type transistors but also a semiconductor device structure with complementary transistors or other suitable devices. Embodiments of the disclosure are not limited and may be applied to fabrication processes for any suitable technology generation. Various technology generations include a 16 nm node, a 10 nm node, a 7 nm node, a 5 nm node, a 3 nm node, or another suitable node. 
     Embodiments of the disclosure form a semiconductor device structure with a fin structure and active gate stacks over the fin structure. The semiconductor device structure includes a dummy gate stack over the fin structure. The dummy gate stack is between two of the active gate stacks. The semiconductor device structure also includes an isolation feature used to isolate the active gate stacks. The isolation feature is embedded in the fin structure and under the dummy gate stack. Since there is only one dummy gate stack between two of the active gate stacks, the area of the semiconductor device structure can be reduced even further to meet requirements. 
     Furthermore, the isolation feature embedded in the fin structure is formed before the formation of the dummy gate stack and the active gate stacks. As a result, the fabrication process of the isolation feature becomes simple. It can also be ensured that S/D structures on opposite sides of the active gate stacks are not damaged during the formation of the isolation feature and ILD loss issues are not induced. Therefore, the reliability of the semiconductor device structure is significantly enhanced. 
     In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a dummy gate stack formed over the fin structure and having a first sidewall and a second sidewall opposite to the first sidewall. The semiconductor device structure also includes a first source or drain (S/D) structure and a second S/D structure in the fin structure and respectively adjacent to the first and second sidewalls of the dummy gate stack. The semiconductor device structure further includes an isolation feature formed in the fin structure below the dummy gate stack and having a third sidewall and a fourth sidewall opposite to the third sidewall. A first end of the third sidewall overlaps the first end of the fourth sidewall. A second end of the third sidewall is in direct contact with a bottom of the dummy gate stack, and a second end of the fourth sidewall is separated from the bottom of the dummy gate stack. 
     In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first isolation feature formed over a semiconductor substrate with a fin structure. The fin structure is adjacent to and protrudes above the first isolation feature. The semiconductor device structure also includes a first source or drain (S/D) structure and a second S/D structure extending into the fin structure by a first depth from a top surface of the fin structure and separated from each other by a distance. The semiconductor device structure further includes a second isolation feature extending into the fin structure between the first S/D structure and the second S/D structure by a second depth from a top surface of the fin structure. In addition, the semiconductor device structure includes a gate stack covering the first isolation feature and the second isolation feature. The second isolation feature has a thickness substantially equal to a thickness of the fin structure and a width less than the distance, and wherein the second depth is greater than the first depth. 
     In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a dummy gate stack and first and second active gate stacks formed over a fin structure of a semiconductor substrate. The dummy gate stack is between the first and second active gate stacks. The semiconductor device structure also includes a first source or drain (S/D) structure formed in the fin structure between the first active gate stack and the dummy gate stack and a second S/D structure formed in the fin structure between the second active gate stack and the dummy gate stack. The semiconductor device structure further includes a first isolation feature formed in the fin structure between the first S/D structure and the second S/D structure. The first isolation feature has a first sidewall surface that is aligned with a first sidewall surface of the fin structure between the first S/D structure and the second S/D structure. In addition, the semiconductor device structure includes a second isolation feature formed on the semiconductor substrate to cover the first sidewall surface of the first isolation feature and the first sidewall surface of the fin structure between the first S/D structure and the second S/D structure. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.