Patent Publication Number: US-6044390-A

Title: Recursive lookahead-based 2n -bit serial multipliers over Galois Field GF (2m)

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to the multiplications of finite field elements, in applications where error correction capabilities are required, and more particularly to bit-serial multipliers used to perform multiplications of field elements over Galois Field GF (2 m ). 
     2. State of the Art 
     Finite (or Galois) fields can be applied to many areas of electrical system designs including error correcting codes, switching theory, and digital signal processing. In general, the application of Galois Fields in these areas (and particularly multiplication in Galois Fields) is one in which a derived mathematical algorithm in some Galois Field is implemented using logic elements to obtain-a desired function or result from the system. A multiplication operation performed in Galois Fields is implemented using logic elements referred to as multipliers, which perform logical operations on the input data to generate output data representing the result of the multiplication of the input data elements. 
     One example of a multiplier for finite field elements is a fully combinational parallel logic multiplier as described in &#34;Systolic Multipliers for Finite Fields GF(2 m ),&#34; by C. S. Yeh, Irving S. Reed, and T. K. Troung, IEEE Transactions on Computers, Vol. C-33, No. 4, April 1984 and incorporated herein. A fully combinational logic design does not include any sequential logic and hence must perform all intermediate steps. As a result, this type of multiplier includes a significant number of logic gates to implement it. Two examples of a bit serial multiplier are shown in &#34;Efficient Bit-Serial Multiplication and the Discrete-Time Wiener-Hopf Equation Over Finite Fields,&#34; by M. Kasahara, M. Morii, and D. L. Whiting, IEEE Transactions on Information Theory, Vol. 35, No. 6, pp. 1177-1183, November 1989, and in &#34;Encoder Using Berlekamp&#39;s Bit-Serial Multiplier Algorithm,&#34; by L. Deutsch, I. S. Reed, T. K. Troung, K. Wang, C. Yeh, IEEE Transactions on Computers, Vol. C-33, No. 10, pp. 906-911, October 1984, both incorporated herein. Bit serial multiplier designs reduce the number of required logic gates by reusing gates in a reiterative manner and pipelining to perform the multiplication operation. 
     As the bandwidth requirement of communication devices increases and hence the number of elements involved in the multiplication operations, there is a need for faster multiplication operations and multipliers which use minimum silicon area. A multiplier that is designed with fully combinational logic, uses large numbers of logic gates to perform a quick parallel multiplication. However, the speed at which the parallel multiplier described in &#34;Systolic Multipliers for Finite Fields GF(2 m )&#34; performs the multiplication is at the expense of large silicon area consumption. Bit-serial multiplier designs minimize silicon area use however, at the expense of reduced performance. The disadvantages associated with both of these schemes are that the performance vs. silicon area is not optimized to yield the best design solution. 
     The goal of the present invention is to implement a 2 n  -bit serial multiplier design that performs fast multiplications of two arbitrary field elements λ and ψ over the Galois Field, GF (2 m ) using minimal silicon area. 
     SUMMARY OF THE INVENTION 
     The present invention is a 2 n  -bit serial multiplier design for multiplying two arbitrary field elements optimized for both speed and silicon area. The multiplier design includes a precomputing stage, source registers, a Galois Field type recursive multiplication stage, and destination registers. According to the method of the present invention, the 2 n  -bit serial multiplier design is implemented by performing a precomputing (cycle-stealing) step in which source registers are pre-loaded with reconstructed and zero-padded input data prior to performing recursive multiplication and the destination registers are pre-loaded with zeros or the highest order field coefficient of the arbitrary field elements while the first cycle of the recursive multiplication phase is taking place. The result of each recursive multiplication cycle is loaded into the destination register and used in subsequent recursive multiplication cycles or in the case of the final cycle, the contents of the destination register is the product of the two field elements. By implementing a multiplier design according to the present invention, a faster 2 n  -bit serial multiplier can be realized. As a result, since multiplication is performed faster, a 2 n  -bit serial multiplier having an increased exponent value n can also be realized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention may be further understood from the following written description in conjunction with the appended drawings. In the drawings: 
     FIG. 1 shows a first implementation of a 2 n  -bit serial multiplier over Galois Field GF (2 m ) with n=1 and m=4 in accordance with the present invention; 
     FIG. 2 shows a second implementation of a 2 n  -bit serial multiplier over Galois Field GB (2 m ) with n=1 and m=4 in accordance with the present invention. 
     FIG. 3 shows a third implementation of a 2 n  -bit serial multiplier over Galois Field GF (2 m ) with n=1 and m=5 in accordance with the present invention. 
     FIG. 4 shows a fourth implementation of a 2 n  -bit serial multiplier over Galois Field GF (2 m ) with n=1 and m=5 in accordance with the present invention. 
     FIG. 5 shows a fifth implementation of a 2 n  -bit serial multiplier with n=1 over the Galois Field (2 10 ). 
     FIG. 6 shows a sixth implementation of a 2 n  -bit serial multiplier with n=2 over the Galois Field (2 10 ). 
     FIG. 7 shows a seventh implementation of a 2 n  -bit serial multiplier with n=3 over the Galois Field (2 10 ). 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In general, the system and method of the present invention is designed to perform Galois Field serial bit multiplications of two arbitrary field elements β and ψ. 
     Let GF (2 m ) be the finite field of 2 m  elements. Also, let β and ψ be two arbitrary field elements having length m over the Galois Field GF (2 m ) as defined below: ##EQU1## where k i  and e i  are two arbitrary field coefficients and α i  indicates arbitrary field position of the β and ψ field elements. The following three steps describe a novel algorithm for one embodiment of the 2 n  -bit serial multiplication of the input field elements β and ψ over the Galois Field GF (2 m ). 
     Step 1) Decomposition of β input field element 
     Let δ be a new input field element of length m that is resulted from the decomposition of the β input field element. The decomposition takes the exponent value, n, of the 2 n  -bit serial multipliers into the consideration for deriving a general formula. ##EQU2## i) in the case when the length m is even, then δ is: ##EQU3## and δ can be restructured as: ##EQU4## ii) in the case when the length m is odd, then δ is: ##EQU5## and δ can be restructured as: ##EQU6## Hence, depending on the length m of the field element, it can be represented by a restructured odd or even field element δ, as indicated in equations (5) and (7). 
     Step 2) Zero-padding 
     Let Φ be a zero-padded field element of length {2 n  -m (mod 2 n )+1} where n is the exponent value of the 2 n  -bit serial multipliers and m is the length of β input field element then: ##EQU7## Expanding equation (8) gives: ##EQU8## Next, a new input field element λ is derived by adding the restructured odd or even input field element, δ(odd) or δ(even), to the zero-padded field element Φ as shown below: 
     
         λ=δ(odd or even)+Φ                        (10) 
    
     The length of the zero-padded input field element X is also m since the following applies: 
     
         k.sub.l =0 for l&gt;m-1                                       (11) 
    
     The 2 n  -bit serial multiplication of the restructured zero-padded input field element λ with the input field element ψ is obtained by using (10): 
     
         λψ=δ(odd or even)·ψ+Φ·ψ(12) 
    
     Step 3) Recursive structuring 
     The recursive structuring is based on the following principle: 
     i) If m is even, m(mod 2 n )=2 n  -2s. 
     ii) If m is odd, m(mod 2 n )=2 n  -(2s+1). 
     where s=0, 1, 2 . . . , (2 n-1  -1) and n is a positive integer. 
     The number of multiplication cycles for a 2 n  -bit serial multiplier is determined by using the following criteria: 
     i) The number of multiplication cycles in general for m odd or even is given by (m+h)/2 n  where h={2 n  -m (mod 2 n )}. 
     ii) However, if m is odd and m(mod 2 n )=1, the number of multiplication cycles can be reduced to (m-1)/2 n . 
     For an example, Equation (12) can be recursively structured into 2 n  -bit serial multipliers with n=1. 
     a) 2 n  -bit serial multipliers with n=1 
     i) with m (even); s=0; h=0; m(mod 2 n )=2 
     Using Equations (5) and (9) in (12), λψ is: ##EQU9## λψ is recursively structured as follows: ##EQU10## 
     Using equation (11), k m  =0 and λψ is: ##EQU11## 
     Given that it takes (m+h)/2 n  multiplication cycles as stated above (for h={2 n  -m(mod 2 n )}), it takes m/2 clock cycles to do a 2 n  -bit serial multiplication when m is (even), n=1 and m(mod 2 n )=2. 
     ii) with m (odd); s=0; h=1; m(mod 2 n )=1 
     Using Equations (7) and (9) in (12), the following is resulted: ##EQU12## The above equation is put into a recursive format as: ##EQU13## Using equation (11), k m  =0 and λψ is: ##EQU14## Given that it takes (m-1)/2 n  multiplication cycles as stated above, then it takes ##EQU15## clock cycles to do a 2 n  -bit serial multiplication when m is (odd), n=1 and m(mod 2 n )=1. 
     Equation (18) can be further simplified as: ##EQU16## 
     This change speeds up the multiplication. It now takes ##EQU17## clock cycles to do a 2 n  -bit serial multiplication when m is (odd), n=1 and m(mod 2 n )=1. 
     The same justification can be made to derive recursive equations for the 2 n  -bit serial multipliers with n=2 and n=3. 
     b) 2 n  -bit serial multipliers with n=2 
     i) with m (even); s=0; h=0; m(mod 2 n )=4, and using equations (5), (9), and (12): ##EQU18## clock cycles are required to do a 2 n  -bit serial multiplication. 
     ii) m (odd); s=0; h=1; m(mod 2 n )=3, and using equations (7), (9), and (12): ##EQU19## clock cycles are required to do a 2 n  -bit serial multiplication. 
     iii) m (even); s=1; h=2; m(mod 2 n )=2 ##EQU20## clock cycles are required to do a 2 n  -bit serial multiplication. 
     iv) m (odd); s=1; h=3; m)mod 2 n )=1 ##EQU21## clock cycles are required to do a 2 n  -bit serial multiplication. 
     c) 2 n  -bit serial multipliers with n=3 
     i) with m (even); s=0; h=0; m(mod 2 n )=8, and using equations (5), (9), and (12): ##EQU22## clock cycles are required to do a 2 n  -bit serial multiplication. 
     ii) with m (odd); s=0; h=1; m(mod 2 n )=7, and using equations (7), (9), and (12): ##EQU23## clock cycles are required to do a 2 n  -bit serial multiplication. 
     iii) with m (even); s=1; h=2; m(mod 2 n )=6 ##EQU24## clock cycles are required to do a 2 n  -bit serial multiplication. 
     iv) with m (odd); s=1; h=3; m(mod 2 n )=5 ##EQU25## clock cycles are required to do a 2 n  -bit serial multiplication. 
     v) with m (even); s=2; h=4; m(mod 2 n )=4 ##EQU26## clock cycles are required to do a 2 n  -bit serial multiplication. 
     vi) with m (odd); s=2; h=5; m(mod 2 n )=3 ##EQU27## clock cycles are required to do a 2 n  -bit serial multiplication. 
     vii) with m (even); s=3; h=6; m(mod 2 n )=2 ##EQU28## clock cycles are required to do a 2 n  -bit serial multiplication. 
     viii) with m (odd); s=3; h=7; m(mod 2 n )=1 ##EQU29## clock cycles are required to do a 2 n  -bit serial multiplication. 
     Using this algorithm, any 2 n  -bit serial Galois Field GF (2 m ) multiplier(s) can be derived for a given n and m. 
     It should be understood that a recursive equation can be obtained in a variety of manners which include determining them manually given the variables n and m (odd or even) or using a software algorithm which is responsive to the input variables n and m (odd or even) and which includes within the algorithm the conditions of equations 2, 5, 9, 11, 12 (for the even case) or 2, 7, 9, 11, and 12 (for the odd case). 
     Architecture and Operation 
     In the following sections, several examples of the architectures and operations of the 2 n  -bit serial multiplier over the Galois Field GF (2 m ) are given. 
     a) 2 n  -bit serial multiplier over the Galois Field GF (2 m ) with n=1 and m=4 
     FIG. 1 shows the architecture of the 2 n  -bit serial multiplier over the Galois Field GF (2 m ) with n=1 and m=4, and FIG. 2 shows the logic diagram of the multiplier architecture shown in FIG. 1. It should be noted that FIG. 2 shows an expanded logic diagram of the elements shown in FIG. 1. Specifically, element U1 in FIG. 1 is representative of the parallel AND gates U1 shown in FIG. 2. Similarly in FIG. 1, U5 represents XOR gates as shown in FIG. 2. It should be further noted that the architectural diagrams shown in FIGS. 3-7 can be similarly expanded as shown in FIG. 2. 
     Since m=4 is an even integer and n=1, then m(mod 2 n )=2. Using (15), the following recursive equation is resulted: 
     
         λψ=(0·α.sup.2 +ψ(k.sub.3 α+k.sub.2))α.sup.2 +ψ(k.sub.1 α+k.sub.0)(32) 
    
     ψ is found using Equation (2) 
     
         ψ=e.sub.0 +e.sub.1 α+e.sub.2 α.sup.2 +e.sub.3 α.sup.3 (33) 
    
     As shown in FIGS. 1 and 2, the multiplier contains two 2-bit shift registers with parallel load capability to store and shift the input field element λ, a 4-bit register with parallel load and hold capabilities to hold the input field element ψ, and a 4-bit register γ, with synchronous reset capability. It also contains eight 2-input AND gates (U1 and U2), and four 3-input XOR (U5) gates. 
     The multiplier also includes two constant Galois Field GF (2 4 ) (U3 and U4) multipliers that perform multiplications of the field elements by α and α 2 , respectively. These are constant multipliers and are built with XOR gates. Implementing a constant multiplier with XOR gates is well-known in the field and is described in &#34;Error Control Coding: Fundamentals and Applications,&#34; by Shu Lin and Daniel J. Costello, Jr., pp. 519-521, which is incorporated herein. The output of all logic elements are connected to a 4-bit bus except the k 3  and k 2  registers which are connected to a 1-bit bus. This multiplier has CLK, LOAD, λ and ψ signals and constant values as inputs and λψ as outputs. 
     The following two steps describe the operation of the multiplier shown in FIG. 1. 
     Step 1) First multiplication cycle with precomputing 
     In the first cycle, the odd coefficients k 1  -k 3  of the λ input field element are preloaded in parallel into a 2-bit k 1  -k 3  register and the even coefficients k 0  -k 2  of the λ input field element are preloaded in parallel into a 2-bit k 0  -k 2  register when LOAD signal is high. Also, the coefficients e 0  -e 3  of the ψ input field element are preloaded in parallel into a 4-bit ψ register when LOAD signal is high. The 4-bit register γ is synchronously preloaded to zero when the LOAD signal is high. While the process is taking place, the multiplier computes the first phase of the multiplications by evaluating the following part of the recursive equation (32). 
     
         λψ-0·α.sup.2 +ψ(k.sub.3 α+k.sub.2)(34) 
    
     The result of equation (34) is shifted into the 4-bit register By at the end of the first multiplication cycle. 
     Step 2) Second multiplication cycle 
     In the second cycle, the LOAD signal goes low and this puts λ registers into a shift mode and the ψ registers into hold mode. At the next rising edge of the clock CLK, the multiplier computes the final multiplications using the value stored in the γ register in the first cycle, multiplying it by α 2  and adding it to the last term in equation (32) as shown in equation (35). 
     
         λψ=(γ.sub.cycle1)α.sup.2 +ψ(k.sub.1 α+k.sub.0)                                          (35) 
    
     The resultant stored in the γ register in the second cycle is the resultant of equation (32) which is also the resultant of the multiplication of the two arbitrary field elements β and ψ 
     The 2 n  -bit serial multiplier over the Galois Field GF (2 4 ) takes 2 ##EQU30## clock cycles to perform a multiplication. b) 2 1  -bit serial multiplier over the Galois Field GF (2 m ) with n=1 and m=5 
     i) Case 1 
     FIG. 3 shows the architecture of the 2 n  -bit serial multiplier over the Galois Field GF (2 m ) with n=1 and m=5. Since m=5 is an odd integer and n=1, then m(mod 2 n )=1. Using (18), the following recursive equation is obtained. 
     
         λψ=((0·α.sup.2 +ψ(0·α+k.sub.4))α.sup.2 +ψ(k.sub.3 α+k.sub.2))α.sup.2 +ψ(k.sub.1 α+k.sub.0)(36) 
    
     Using Equation (2), ψ is: 
     
         ψ=e.sub.0 +e.sub.1 α+e.sub.2 α.sup.2 +e.sub.3 α.sup.3 +e.sub.4 α.sup.4                                    (37) 
    
     The multiplier contains two 3-bit shift registers with parallel load capability to store and shift the input field element λ, a 5-bit register with parallel load and hold capabilities to hold the input field element ψ, and a 5-bit register By with synchronous reset capability. 
     The multiplier contains ten 2-input AND gates (U1 and U2), five 3-input XOR (U5) gates. It also includes two constant Galois Field GF (2 5 ) (U3 and U4) multipliers that perform multiplications of the field elements by constants α and α 2 , respectively. These are constant multipliers and are built with XOR gates as described previously. The output of all logic elements are connected to a 5-bit bus except the zero and k 4  registers which are connected to a 1-bit bus. This multiplier has CLK, LOAD, λ and ψ signals as inputs and λψ as outputs. 
     The following two steps describe the multiplier operation shown in FIG. 3. 
     Step 1) First multiplication cycle with precomputing 
     In the first cycle, the odd coefficients (k 1 , k 3 , 0) of the λ zero-padded input field element are preloaded in parallel into the 3-bit (k 1 , k 3 , 0) register and the even coefficients (k 0 , k 2 , k 4 ) of the λ input field element are preloaded in parallel into the 3-bit (k 0 , k 2 , k 4 ) register when LOAD signal is high. Also, the coefficients e 0  -e 4  of the ψ input field element are preloaded in parallel into a 5-bit ψ register when LOAD signal is high. The 5-bit register ψ is synchronously preloaded to zero when the LOAD signal is high. 
     While this process is taking place, the multiplier computes the first phase of multiplications by evaluating the following part of recursive equation (36). 
     
         λψ=0·α.sup.2 +ψ(0·α+k.sub.4)(38) 
    
     At the end of cycle 1, the resultant of equation (38) is stored in the γ register. 
     Step 2) Second multiplication cycle 
     In the second cycle, the LOAD signal goes low and this puts λ registers into a shift mode and the ψ registers into hold mode. At the next rising edge of the clock CLK, the multiplier computes the next second partial multiplication shown below using the value stored in the γ register in the first cycle: 
     
         λψ=(γ.sub.cycle1)α.sup.2 +ψ(k.sub.3 α+k.sub.2)                                          (39) 
    
     At the end of cycle 2, the resultant of equation (39) is stored into the γ register. 
     Step 3) Third multiplication cycle 
     In the third cycle, the LOAD signal stays low in order to keep the λ registers in a shift mode and the ψ registers in a hold mode. At the next rising edge of the clock CLK, the multiplier computes the final multiplication using the value stored in the γ register in the second cycle and adding it to the last term of equation (36). 
     
         λψ=(γ.sub.cycle2)α.sup.2 +ψ(k.sub.1 α+k.sub.0)                                          (40) 
    
     The value stored in the γ register after cycle 3 is the resultant of the equation (36) which is the resultant of the multiplication of the two arbitrary field elements β and ψ. 
     The 2 1  -bit serial multiplier over the Galois Field, GF (2 5 ) takes 3 ##EQU31## clock cycles to perform a multiplication. ii) Case 2 
     FIG. 4 shows the architecture of the 2 n  -bit serial multiplier over the Galois Field GF (2 m ) with n=1 and m=5. Since m=5 is an odd integer and n=1, then m(mod 2 n )=1. Note the variables for this multiplication operation are the same as in Case 1. However, instead of using equation (18) as in Case 1, the simplified equation (19) is used and the following recursive equation is obtained. 
     
         λψ=(ψk.sub.4 α.sup.2 +ψ(k.sub.3 α+k.sub.2))α.sup.2 +ψ(k.sub.1 α+k.sub.0)(41) 
    
     Using Equation (2), ψ is: 
     
         ψ=e.sub.0 +e.sub.1 α+e.sub.2 α.sup.2 +e.sub.3 α.sup.3 +e.sub.4 α.sup.4                                    (42) 
    
     The multiplier contains two 2-bit shift registers with parallel load capability to store and shift the input field element λ, a 5-bit register with parallel load and hold capabilities to hold the input field element ψ, and a 5-bit register γ with synchronous reset and parallel load capability. 
     The multiplier also contains fifteen 2-input AND gates (U1, U2, and U6), five 3-input XOR (U5) gates, and two constant Galois Field GF (2 5 ) (U3 and U4) multipliers that perform multiplications of the field elements by constants α and α 2 , respectively. These are constant multipliers and are built with XOR gates as described above. The output of all logic elements are connected to a 5-bit bus except the k 3  and k 2  registers which are connected to a 1-bit bus. This multiplier has CLK, LOAD, λ and ψ signals as inputs and λψ as outputs. 
     The following two steps describe the multiplier operation shown in FIG. 4. 
     Step 1) First multiplication cycle with precomputing 
     The odd coefficients k 1  -k 3  of the λ input field element are preloaded in parallel into a 2-bit k 1  -k 3  register and the even coefficients k 0  -k 2  of the λ input field element are preloaded in parallel into a 2-bit k 0  -k 2  register when LOAD signal is high. Also, the coefficients e 0  -e 4  of the ψ input field element are preloaded in parallel into a 5-bit ψ register when LOAD signal is high. The 5-bit register γ is synchronously preloaded with the highest order coefficient in equation (41), ψk 4 , when the LOAD signal is high, instead of being preloaded with &#34;0&#34; as in Case 1. 
     While this process is taking place, the multiplier computes the first phase of multiplications by evaluating the following part of recursive equation (41). 
     
         λψ=ψk.sub.4 α.sup.2 +ψ(k.sub.3 α+k.sub.2)(43) 
    
     The resultant is then stored in the γ register. 
     Step 2) Second multiplication cycle 
     In the second cycle, the LOAD signal goes low and this puts λ registers into a shift mode and the ψ registers into hold mode. At the next rising edge of the clock CLK, the multiplier computes the final multiplications. 
     
         λψ=(γ.sub.cycle1)α.sup.2 +ψ(k.sub.1 α+k.sub.0)                                          (44) 
    
     The value stored in the γ register after this cycle is the resultant of the multiplication of the two arbitrary field elements β and ψ. 
     The 2 1  -bit serial multiplier over the Galois Field, GF (2 5 ) takes 2 ##EQU32## clock cycles to perform a multiplication. c) 2 1  -bit serial multiplier with n=1 over the Galois Field, GF (2 10 ) 
     FIG. 5 shows the architecture of the 2 n  -bit serial multiplier with n=1 over the Galois Field, GF (2 10 ). Since m=10 is an even integer and n=1, then m(mod 2 n )=2. Using (15), the following recursive equation is obtained: ##EQU33## Using equation (2), ψ is ##EQU34## 
     The multiplier contains two 4-bit shift registers with parallel load capability to store and shift the input field element λ, a 10-bit register with parallel load and hold capability to hold the input field element ψ, and a 10-bit register γ with synchronous reset capability. It also contains twenty 2-input AND gates (U1 and U2), and ten 3-input XOR (U5) gates. The multiplier has two Galois Field, GF (2 10 ), U3 and U4 multipliers that perform multiplications of the field elements by α 1  and α 2 , respectively. These are constant multipliers and are built from XOR gates. The output of all logic elements are connected to a 10-bit bus except the k 9  and k 8  registers which are connected to a 1-bit bus. This multiplier has CLK, LOAD, λ, and ψ signals as inputs and λψ as outputs. 
     The multiplier takes the following steps to perform a multiplication operation shown in FIG. 5. 
     Step 1) First Multiplication Cycle with Precomputing 
     The odd coefficients k 1  -k 9  of the λ input field element are preloaded in parallel into a 5-bit k 1  -k 9  register and the even coefficients k 0  -k 8  of the λ input field element are preloaded in parallel into a 5-bit k 0  -k 8  register when LOAD signal is high. Also, the coefficients e 0  -e 9  of the ψ input field element are preloaded in parallel into a 10-bit ψ register when LOAD signal is high. The 10-bit register γ is synchronously preloaded to zero when the LOAD signal is high. While this process is taking place, the multiplier performs the first phase of multiplications by evaluating the following part of recursive equation (45) which is given as: 
     
         λψ=0·α.sup.2 +ψ(k.sub.9 α+k.sub.8)(47) 
    
     The resultant of this equation is stored in γ register after the first cycle. 
     Step 2) Second Multiplication Cycle 
     In the second cycle, the LOAD signal goes low and this puts λ registers into a shift mode and the ψ registers into hold mode. At the next rising edge of the clock CLK. the multiplier performs the following partial multiplication of equation (45): 
     
         λψ=(γcycle1)α.sup.2 +ψ(k.sub.1 α+k.sub.6)(48) 
    
     The resultant of this equation is stored in the γ register after the second cycle. 
     Step 3) Third Multiplication Cycle 
     At the next rising edge of the clock CLK, the multiplier performs the following partial multiplications: 
     
         λψ=(γ.sub.cycle2)α.sup.2 +ψ(k.sub.5 α+k.sub.4)                                          (49) 
    
     The resultant of this equation is stored in the γ register after the third cycle. 
     Step 4) Fourth Multiplication Cycle 
     At the next rising edge of the clock CLK, the multiplier performs the following partial multiplications: 
     
         λψ=(γ.sub.cycle3)α.sup.2 +ψ(k.sub.3 α+k.sub.2)                                          (50) 
    
     Step 5) Fifth Multiplication Cycle 
     In the fifth cycle, the multiplier completes the multiplications with the following result: 
     
         λψ=(γ.sub.cycle4)α.sup.2 +ψ(k.sub.1 α+k.sub.0)                                          (51) 
    
     The value stored in the γ register after the fifth cycle is the resultant of the multiplication of arbitrary field elements β and ψ. 
     The 2 n  -bit serial multiplier with n=1 over the Galois Field, GF (2 10 ) takes 5 clock cycles ##EQU35## to perform a multiplication. d) 2 n  -Bit Serial Multiplier With n=2 Over the Galois Field GF (2 10 ) 
     FIG. 6 shows the architecture of the 2 n  -bit serial multiplier with n=2 over the Galois Field GF (2 10 ). Since m=10 is an even integer and n=2, then m(mod 2 10 )=2. Using (22), the following recursive equation is obtained: ##EQU36## Using equation (2), ψ is ##EQU37## 
     The multiplier contains four 3-bit shift registers with parallel load capability to store and shift the input field element λ, a 10-bit register with parallel load and hold capability to hold the input field element ψ, and a 10-bit register By with synchronous reset capability. It also contains forty 2-input AND gates (U1, U2, U3, and U4), and ten 5-input XOR (U9) gates. The multiplier has four Galois Field, GF (2 10 ), multipliers (U5, U6, U7, and U8) that perform multiplications of the field elements by α 1 , α 2 , α 3 , and α 4 , respectively. These are constant multipliers and are built from XOR gates as described herein. The output of all logic elements are connected to a 10-bit bus except the k 9  -k 8  and zero-padded registers which are connected to a 1-bit bus. This multiplier has CLK, LOAD, λ, and ψ signals as inputs and λψ as outputs. 
     The multiplier takes the following steps to perform a multiplication operation shown in FIG. 6. 
     Step 1) First Multiplication Cycle with Precomputing 
     The coefficients (k 0 , k 4 , k 8 ) of the λ input field element are preloaded in parallel into a 3-bit register, (k 0 , k 4 , k 8 ); the coefficients (k 1 , k 5 , k 9 ) of the λ input field element are preloaded in parallel into a 3-bit register, (k 1 , k 5 , k 9 ); the coefficients (k 2 , k 6 , 0) of the λ input field element are preloaded in parallel into a 3-bit register, (k 2 , k 6 , 0); the coefficients (k 3 , k 7 , 0) of the λ input field element are preloaded in parallel into a 3-bit register, (k 3 , k 7 , 0), when LOAD signal is high. Also, the coefficients e 0  -e 9  of the ψ input field element are preloaded in parallel into a 10-bit ψ register when LOAD signal is high. The 10-bit register γ is synchronously preloaded to zero when the LOAD signal is high. 
     While this process is taking place, the multiplier performs the first phase of multiplications by evaluating the following part of recursive equation (52) which is given as: 
     
         λψ=0·α.sup.4 +ψ(0·α.sup.3 +0·α.sup.2 +k.sub.9 α+k.sub.8)       (54) 
    
     The resultant is then stored in the γ register. 
     Step 2) Second Multiplication Cycle 
     In the second cycle, the LOAD signal goes low and this puts λ registers into a shift mode and the ψ registers into hold mode. At the next rising edge of the clock CLK, the multiplier performs the following partial multiplications: 
     
         λψ=(γ.sub.cycle1)α.sup.4 +ψ(k.sub.1 α.sup.3 +k.sub.6 α.sup.2 +k.sub.5 α+k.sub.4)(55) 
    
     Step 3) Third Multiplication Cycle 
     At the next rising edge of the clock CLK, the multiplier performs the following partial multiplications: 
     
         λψ=(γ.sub.cycle2)α.sup.4 +ψ(k.sub.3 α.sup.3 +k.sub.2 α.sup.2 +k.sub.1 α+k.sub.0)(56) 
    
     The resultant stored in the γ register is the product of equation (52). 
     The 2 n  -bit serial multiplier with n=2 over the Galois Field, GF (2 10 ) takes three ##EQU38## clock cycles to perform a multiplication. e) 2 n  -Bit Serial Multiplier with n=3 over the Galois Field GF (2 10 ) 
     FIG. 7 shows the architecture of the 2 n  -bit serial multiplier with n=3 over the Galois Field GF (2 10 ). Since m=10 is an even integer and n=3, then m(mod 2 n )=2. Using (30), the following recursive equation is obtained: ##EQU39## Using equation 2, ψ is ##EQU40## 
     The multiplier contains eight 2-bit shift registers with parallel load capability to store and shift the input field element λ, a 10-bit register with parallel load and hold capability to hold the input field element ψ, and a 10-bit register By with synchronous reset capability. It also contains eighty 2-input AND gates (U1, U2, U3, U4, U5, U6, U7, and U8), and ten 9-input XOR (U5) gates. The multiplier has eight Galois Field, GE (2 10 ), (U8, U9, U10, U11, U12, U13, U14, and U15) multipliers that perform multiplications of the field elements by, α 1 , α 2 , α 3 , α 4 , α 5 , α 6 , α 7 , and α 8 , respectively. These are constant multipliers and are built from XOR gates. The output of all logic elements are connected to a 10-bit bus except the k 9  -k 8 , and zero-padded registers which are connected to a 1-bit bus. This multiplier has CLK, LOAD, λ, and ψ signals as inputs and λψ as outputs. 
     The multiplier takes the following steps to perform a multiplication operation shown in FIG. 7. 
     Step 1) First Multiplication Cycle with Precomputing 
     The coefficients (k 0 , k 8 ) of the λ input field element are preloaded in parallel into a 2-bit register, (k 0 , k 8 ); the coefficients (k 1 , k 9 ) of the λ input field element are preloaded in parallel into a 2-bit register, (k 1 , k 9 ); the coefficients (k 2 , 0) of the λ input field element are preloaded in parallel into a 2-bit register, (k 2 , 0); the coefficients (k 3 , 0) of the λ input field element are preloaded in parallel into a 2-bit register, (k 3 , 0); the coefficients (k 4 , 0) of the λ input field element are preloaded in parallel into a 2-bit register, (k 4 , 0); the coefficients (k 5 , 0) of the λ input field element are preloaded in parallel into a 2-bit register, (k 5 , 0); the coefficients (k 6 , 0) of the λ input field element are preloaded in parallel into a 2-bit register, (k 6 , 0); and the coefficients (k 7 , 0) of the λ input field element are preloaded in parallel into a 2-bit register, (k 7 , 0), when LOAD signal is high. Also, the coefficients e 0  -k 9  of the ψ input field element are preloaded in parallel into a 10-bit ψ register when LOAD signal is high. The 10-bit register γ are synchronously preloaded to zero when the LOAD signal is high. 
     While this process is taking place, the multiplier performs the first phase of multiplications by evaluating the following part of recursive equation (57) which is given as: 
     
         λψ=0·α.sup.8 +ψ(0·α.sup.7 +0·α.sup.6 +0·α.sup.5 +0·α.sup.4 +0·α.sup.3 +0·α.sup.2 +k.sub.9 α+k.sub.8)       (59) 
    
     which is stored in the γ register. 
     Step 2) Second Multiplication Cycle 
     In the second cycle, the LOAD signal goes low and this puts λ registers into a shift mode and the ψ registers into hold mode. At the next rising edge of the clock CLK, the multiplier performs the following partial multiplications: 
     
         λψ(γ.sub.cycle1)α.sup.8 +ψ(k.sub.7 α.sup.7 +k.sub.6 α.sup.6 +k.sub.5 α.sup.5 +k.sub.4 α.sup.4 +k.sub.3 α.sup.3 +k.sub.2 α.sup.2 +k.sub.1 α+k.sub.0)(60) 
    
     The resultant of equation (60) is stored in the γ register and is the resultant of the multiplication of the two arbitrary field elements β and ψ. 
     The 2 n  -bit serial multiplier with n=3 over the Galois Field, GF (2 10 ) takes two clock cycles ##EQU41## to perform a multiplication. 
     Table 1 shows the multiplication cycles of the 2 n  -bit serial multiplier over the Galois Field GF (2 m ) for 1≦m≦16 and 1≦n≦3. It is derived using the novel algorithm described before. It shows different configurations of the 2 n  -bit serial multipliers than can be used to yield an optimum performance and silicon area for a given m. 
     The 2 n  -bit serial multiplier over the Galois Field GF (2 m ) becomes a bit parallel (fully combinational logic) multiplier for n=1 and m=1-2; n=2 and m=1-4; n=3 and m=1-8. This is due to the fact that no registers are required for storing the input field element coefficients (i.e., zero cycle multiplications). 
     In general, the number of multiplication cycles is (m+h)/2 n  where h={2 n  &#39;m (mod 2 n )}. However, if m is odd and m(mod 2 n )=1, the number of multiplication cycles is reduced to (m-1)/2 n . 
     In general, the 2 n  -bit serial multiplier requires (3m) registers with parallel load feature, (m·2 n ) 2-input AND gates, m (2 n  +1)-input XOR gates, and α 2 .spsp.p constant Galois Field multipliers where p=0, 1, . . . n. 
     
                       TABLE 1                                                     
______________________________________                                    
The multiplication cycles of the 2.sup.n -bit serial multiplier           
over the Galois Field GF (2.sup.m)                                        
Cycles                                                                    
      2.sup.n -Bit Serial, n = 1                                          
                   2.sup.n -Bit Serial, n = 2                             
                                2.sup.n -Bit Serial, n = 3                
______________________________________                                    
m = 1 0            0            0                                         
m = 2 0            0            0                                         
m = 3 2            0            0                                         
m = 4 2            0            0                                         
m = 5 2            1            0                                         
m = 6 3            2            0                                         
m = 7 3            2            0                                         
m = 8 4            2            0                                         
m = 9 4            2            1                                         
m = 10                                                                    
      5            3            2                                         
m = 11                                                                    
      5            3            2                                         
m = 12                                                                    
      6            3            2                                         
m = 13                                                                    
      6            3            2                                         
m = 14                                                                    
      7            4            2                                         
m = 15                                                                    
      7            4            2                                         
m = 16                                                                    
      8            4            2                                         
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     In the preceding description, numerous specific details are set forth, such as specific input element definitions in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known logic structures and components have not been described in order to avoid unnecessarily obscuring the present invention. 
     Moreover, although the components of the present invention have been described in conjunction with certain embodiments, it is appreciated that the invention can be implemented in a variety of other ways. Consequently, it is to be understood that the particular embodiments shown and described by way of illustration is in no way intended to be considered limiting. Reference to the details of these embodiments is not intended to limit the scope of the claims which themselves recite only those features regarded as essential to the invention.