Patent Publication Number: US-6985019-B1

Title: Overvoltage clamp circuit

Description:
FIELD OF INVENTION 
   The present invention relates generally to integrated circuits, and more specifically to voltage clamp circuits. 
   DESCRIPTION OF RELATED ART 
   For many integrated circuit (IC) devices, the input/output (I/O) pins are coupled to overvoltage clamp circuits that prevent the input voltage level at the I/O pins from exceeding the IC devices&#39; internal voltage supply by a predetermined amount to prevent damage to the IC devices&#39; internal circuitry. For example, because output signals from Peripheral Component Interconnect (PCI) devices using a 3.3 volt supply may have voltage overshoots exceeding 7 volts for up to one second, it is necessary to clamp the voltage of these signals at the I/O pin(s) of a connected device to prevent damage to the connected device&#39;s internal circuitry. However, some non-PCI devices operate according to other standards (e.g., the well-known LVCMOS standards) that require the I/O pins of connected devices to be tri-statable. Unfortunately, connecting an overvoltage clamp circuit to an I/O pin of a device may prevent the I/O pin from being properly tri-stated. As a result, some IC devices include an overvoltage clamp circuit that can be selectively enabled and disabled, thereby allowing such devices to operate in either PCI systems that require input signals to be clamped or in non-PCI systems that require the I/O pins to be tri-statable. 
     FIG. 1  shows an IC device  100  having internal logic  102 , an I/O pin  103 , a buffer  104 , and a conventional overvoltage clamp circuit  110 . Buffer  104 , which includes a first terminal coupled to internal logic  102  via signal line  105   a  and includes a second terminal coupled to I/O pin  103  via a signal line  105   b , buffers signals between I/O pin  103  and internal logic  102 . Typically, buffer  104  includes one or more well-known CMOS inverters (only one shown in  FIG. 1  for simplicity), although other buffers can be used. Clamp circuit  110 , which can be selectively enabled and disabled in response to an enable signal EN, includes resistors R 1 –R 3 , a PMOS transistor  111 , and NMOS transistors  112  and  113 . PMOS transistor  111 , resistor R 3 , and NMOS transistor  112  are connected in series between signal line  105   b  and ground potential. Resistors R 1 –R 2  form a voltage divider that provides a ratioed voltage to the gate of PMOS transistor  111  via node A. The ratioed voltage at node A is a predetermined fraction of VDD that is determined by the relative resistances of R 1  and R 2 . The gate of NMOS transistor  112  receives the enable signal EN. NMOS transistor  113  is connected between signal line  105   b  and a node C between resistor R 3  and NMOS transistor  112 , and has a gate coupled to a node B between resistor R 3  and PMOS transistor  111 . Together, NMOS transistors  112 – 113  form a discharge path that sinks current from signal line  105   b  when the voltage level on signal line  105   b  exceeds a predetermined voltage, for example, during voltage overshoot of input signals applied to I/O pin  103 . 
   To enable clamp circuit  110 , EN is asserted to a logic high state (e.g., to VDD) to turn on NMOS transistor  112 . Node B is at or near ground potential, which maintains NMOS transistor  113  in a non-conductive state. The voltage divider formed by resistors R 1 –R 2  provides a ratioed voltage to the gate of PMOS transistor  111  that maintains transistor  111  in a non-conductive state as long as the voltage on signal line  105   b  remains below a predetermined level. If overshoots in an input signal applied to I/O pin  103  cause the voltage on signal line  105   b  to exceed the gate voltage of transistor  111  by more than the threshold voltage (Vtp) of transistor  111 , then transistor  111  turns on and quickly pulls node B toward the signal line voltage via resistor R 3  and transistor  112 . As the rising voltage at node B exceeds the threshold voltage (Vtn) of transistor  113 , transistor  113  turns on and sinks current from signal line  105   b  to ground potential through transistors  112  and  113 , thereby quickly discharging the voltage on I/O pin  103  to a lower (e.g., safer) level. When the signal line voltage is discharged below the predetermined level (e.g., approximately less than one Vtp above VDD), transistor  111  turns off and node B quickly discharges toward ground potential through resistor R 3  and transistor  112 , thereby turning off transistor  113  to stop discharging signal line  105   b.    
   To disable clamp circuit  110 , EN is de-asserted to a logic low state (e.g., to ground potential) to maintain NMOS transistor  112  in a non-conductive state, thereby disabling clamp circuit  110  by preventing signal line  105   b  from being discharged through transistor  112 . When clamp circuit  110  is disabled, I/O pin  103  can be tri-stated, which as described above may be desirable for device  100  to operate in some non-PCI systems that require I/O pins to be tri-stated. 
   Although allowing clamp circuit  110  to be selectively enabled and disabled in response to EN, the inclusion of NMOS transistor  112  in the discharge path with NMOS transistor  113  significantly increases the series resistance of the discharge path from signal line  105   b  to ground potential. As a result, NMOS transistors  112  and  113  are typically very large transistors that can quickly discharge signal line  105   b  during voltage overshoot conditions on signal line  105   b . For some devices that utilize clamp circuit  110 , the width of transistors  112  and  113  can be several orders of magnitude greater than that of other transistors in the device, e.g., transistor  111  and the transistors (not shown for simplicity) within internal logic  102 , which can undesirably increase circuit size. 
   Thus, there is a need for an overvoltage clamp circuit that can be selectively enabled and disabled and which occupies less silicon area than that of prior art clamp circuit  110 . 
   An area-efficient clamp circuit is disclosed that can be selectively enabled and disabled. In accordance with the present invention, a selectively enabled clamp circuit for limiting voltage overshoot on an input/output (I/O) pin of an associated integrated circuit (IC) device includes a single discharge transistor and a select circuit. The single discharge transistor is connected between the I/O pin and ground potential, and the select circuit is coupled to the I/O pin and includes an input to receive an enable signal and an output coupled to a gate of the discharge transistor. If the enable signal is in an asserted state, the select circuit turns on the discharge transistor when the voltage on the I/O pin exceeds a predetermined voltage level. If the enable signal is in a de-asserted state, the select circuit maintains the discharge transistor in a non-conductive state that allows the I/O pin to be tri-stated. 
   For some embodiments, the select circuit includes a level shifter circuit and a voltage detection circuit. For one embodiment, the level shifter circuit has a power terminal coupled to the I/O pin and includes an input to receive the enable signal, and the voltage detection circuit is coupled to the I/O pin and includes an input coupled to an output of the level shifter circuit and an output coupled to the gate of the discharge transistor. For another embodiment, the voltage detection circuit includes a detection transistor connected between the I/O pin and a first node and has a gate coupled to a voltage supply of the IC device, and the level shifter circuit has a power terminal coupled to the first node and includes an input to receive the enable signal and an output coupled to the gate of the discharge transistor. 
   For some embodiments, the enable signal is asserted if the IC device is operating in a PCI system and is de-asserted if the IC device is operating in a system that requires the I/O pin to be tri-statable (e.g., an LVCMOS system). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention are illustrated by way of example and are by no means intended to limit the scope of the present invention to the particular embodiments shown, and in which: 
       FIG. 1  is a circuit diagram of a conventional overvoltage clamp circuit; 
       FIG. 2  is a block diagram of an overvoltage clamp circuit in accordance with one embodiment of the present invention; 
       FIG. 3  is a circuit diagram of an overvoltage clamp circuit that is one embodiment of the clamp circuit of  FIG. 2 ; 
       FIG. 4  is a circuit diagram of an overvoltage clamp circuit that is another embodiment of the clamp circuit of  FIG. 2 ; and 
       FIG. 5  is a block diagram illustrating the overvoltage clamp circuit of  FIG. 2  as part of a programmable logic device. 
   

   Like reference numerals refer to corresponding parts throughout the drawing figures. 
   DETAILED DESCRIPTION 
   The present invention is applicable to a variety of integrated circuits and systems, and is particularly useful for devices that may operate both in systems that require the device I/O pins to be clamped to a predetermined voltage level (e.g., in PCI environments) and in systems that require the device I/O pins to be tri-statable (e.g., in LVCMOS environments). In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present invention. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the present invention. Further, the logic levels assigned to various signals in the description below are arbitrary, and thus can be modified (e.g., reversed polarity) as desired. Accordingly, the present invention is not to be construed as limited to specific examples described herein but rather includes within its scope all embodiments defined by the appended claims. 
     FIG. 2  shows a block diagram of an overvoltage clamp circuit  200  in accordance with one embodiment of the present invention. Clamp circuit  200  is coupled to signal line  105 , which is connected between I/O pin  103  and internal logic  102  of an associated IC device (not shown for simplicity). The associated IC device can be any well-known device, and internal logic  102  can include any suitable logic or circuitry. For some embodiments, the associated device can be a programmable logic device (PLD), and internal logic  102  can include configurable logic blocks (CLBs), I/O blocks (IOBs), memory elements, processors, and/or other well-known PLD components. Further, although not shown in the exemplary embodiment of  FIG. 2  for simplicity, actual embodiments may include a buffer (e.g., buffer  104  of  FIG. 1 ) connected between internal logic  102  and I/O pin  103 . 
   Clamp circuit  200  includes a level shifter circuit  210 , a voltage detection circuit  220 , and a discharge circuit  230 . Level shifter circuit  210  includes power terminals coupled to signal line  105  and to ground potential, an input terminal to receive an enable signal EN, and an output terminal to generate a voltage detection enable signal EN — VDET. Level shifter circuit  210  drives EN — VDET to a first logic state that enables voltage detection circuit  220  in response to an asserted EN, and drives EN — VDET to a second logic state that disables voltage detection circuit  220  in response to a de-asserted EN. For some embodiments, level shifter  210  may be any suitable, well-known voltage level shifter circuit. 
   Voltage detection circuit  220  is coupled between signal line  105  and ground potential, and includes an input terminal to receive EN — VDET and an output terminal to generate a discharge control signal CTRL. If enabled, voltage detection circuit  220  monitors the voltage level on signal line  105  and, when the signal line voltage exceeds a predetermined level, drives CTRL to an asserted state. Otherwise, if the signal line voltage does not exceed the predetermined level, or if disabled by EN — VDET, voltage detection circuit  220  maintains CTRL in a de-asserted state. For some embodiments, voltage detection circuit  220  may be any well-known circuit that asserts CTRL when the voltage on signal line  105  exceeds the predetermined voltage level. 
   Discharge circuit  230  selectively provides a discharge path between signal line  105  and ground potential in response to CTRL. When CTRL is asserted, discharge circuit  230  sinks current from signal line  105  to discharge signal line  105 , for example, during voltage overshoot of an input signal applied to I/O pin  103 . When CTRL is de-asserted, discharge circuit  230  isolates signal line  105  from ground potential and does not discharge signal line  105 . 
   For some embodiments, level shifter circuit  210  and voltage detection circuit  220  form a select circuit that selectively enables discharge circuit  230  to discharge signal line  105  in response to EN. Thus, the select circuit formed by level shifter circuit  210  and voltage detection circuit  220  may be any suitable circuit that (1) enables discharge circuit  230  to sink current from signal line  105  when EN is asserted and when the signal line voltage exceeds the predetermined level and (2) disables discharge circuit  230  to prevent the signal line voltage from being clamped when EN is de-asserted. 
   As discussed in more detail below, discharge circuit  230  may include only one transistor coupled between signal line  105  and ground potential, and therefore can be half the size of discharge transistors  112  and  113  of clamp circuit  110  of  FIG. 1  without decreasing the rate at which signal line  105  is discharged. Accordingly, embodiments of the present invention provide a clamp circuit that can be selectively enabled and disabled and which occupies less silicon area than prior art clamp circuit  110  without any loss of current-sinking performance. 
     FIG. 3  shows a clamp circuit  300  that is one embodiment of clamp circuit  200  of  FIG. 2 . Clamp circuit  300  includes a level shifter circuit  310 , a voltage detection circuit  320 , and a discharge circuit  330 . Level shifter circuit  310 , which is one embodiment of level shifter circuit  210  of  FIG. 2 , includes PMOS transistors MP 1 –MP 4 , NMOS transistors MN 1 –MN 2 , and an inverter  302 . Transistors MP 1 , MP 2 , and MN 1  are connected in series between signal line  105   b  and ground potential, with the gates of MP 1  and MN 1  receiving the enable signal EN. Transistors MP 3 , MP 4 , and MN 2  are connected in series between signal line  105   b  and ground potential, with the gates of MP 3  and MN 2  coupled to an output of inverter  302 . Inverter  302 , which may be any suitable logical inversion circuit such as a well-known CMOS inverter, includes an input to receive EN. The gate of MP 2  is coupled to a node E between MP 4  and MN 2 , and the gate of MP 4  is coupled to a node D between MP 2  and MN 1 . Node D provides the voltage detection enable signal EN — VDET to voltage detection circuit  320 . For other embodiments, other voltage level shifter circuits may be used. 
   Voltage detection circuit  320 , which is one embodiment of voltage detection circuit  220  of  FIG. 2 , includes PMOS transistors MP 5 –MP 6  and a resistor R 4  connected in series between signal line  105   b  and ground potential. The gate of MP 5  is coupled to node D of level shifter circuit  310  (i.e., the EN — VDET signal), and the gate of MP 6  is coupled to VDD. For other embodiments, other voltage detection circuits may be used. 
   Discharge circuit  330 , which is one embodiment of discharge circuit  230  of  FIG. 2 , includes an NMOS transistor MN 3  connected in series between signal line  105   b  and ground potential, with the gate of MN 3  coupled to a node F between MP 6  and R 4 . Node F provides the discharge control signal CTRL to discharge circuit  330 . 
   To enable clamp circuit  300 , EN is asserted to logic high, which turns off MP 1  and turns on MN 1 . The logic high state of EN is inverted by inverter  302  to generate a logic low signal that turns on MP 3  and turns off MN 2 . The conductive state of MN 1  pulls node D low toward ground potential (e.g., to a logic low state), which turns on MP 4  and MP 5 . The non-conductive state of MP 1  isolates node D from signal line  105   b , and the non-conductive state of MN 2  isolates node E from ground potential. 
   If the voltage on signal line  105   b  exceeds VDD by the threshold voltage (Vtp) of MP 6  (e.g., if V( 105   b )&gt;VDD+Vtp(MP 6 )), MP 6  turns on and quickly charges node F toward the signal line voltage via MP 5 . As the voltage at node F rises above the threshold voltage (Vtn) of MN 3  (e.g., as CTRL transitions to an asserted logic high state), MN 3  turns on and sinks current from signal line  105   b  to quickly discharge signal line  105   b  towards ground potential. When the voltage on signal line  105   b  drops below VDD+Vtp(MP 6 ), MP 6  turns off and node F quickly discharges toward ground potential through resistor R 4  (i.e., CTRL transitions to a de-asserted logic low state), thereby turning off transistor MN 3  to stop discharging signal line  105   b.    
   To disable clamp circuit  300 , EN is de-asserted to logic low, which turns off MN 1  and turns on MP 1 . The logic low state of EN is inverted by inverter  302  to generate a logic high signal that turns on MN 2  and turns off MP 3 . The conductive state of MN 2  discharges node E toward ground potential, which turns on MP 2 . Thus, with both MP 1  and MP 2  conductive, node D is charged toward the signal line voltage (e.g., to a logic high state), which turns off MP 4  and MP 5 . The non-conductive states of MP 3  and MP 4  isolate node E from signal line  105   b , and the non-conductive state of MP 5  isolates node F from the signal line voltage. As a result, node F is maintained at or near ground potential (e.g., in a de-asserted logic low state) via R 4 . The resulting logic low state of node F (e.g., CTRL) maintains MN 3  in a non-conductive state, thereby preventing discharge circuit  330  from sinking current from signal line  105   b.    
   Note that because level shifter circuit  310  has one of its power terminals connected to signal line  105   b , level shifter circuit  310  maintains node D at the same voltage level as signal line  105   b  when clamp circuit  300  is disabled. This is important for applications in which the logic high voltage level of input signals applied to I/O pin  103  are greater than VDD. Otherwise, if the positive power terminal of level shifter circuit  310  is connected to VDD and the logic high voltage level of input signals applied to pin  103  is greater than VDD, voltage level shifter  310  may inadvertently cause discharge circuit  330  to clamp the voltage on signal line  105   b  even if EN is de-asserted. 
   As described above, the discharge circuit  330  of clamp circuit  300  includes only one transistor MN 3  that is selectively enabled and disabled in response to EN. The inclusion of only a single transistor MN 3  in the discharge path between signal line  105   b  and ground potential allows transistor MN 3  of clamp circuit  300  to be approximately one-half the size of discharge transistors  112  and  113  of prior art clamp circuit  110 , which in turn may result in a significant reduction in circuit size without diminishing the speed with which signal line  105   b  is discharged during input signal overshoot conditions. In addition, the ability to selectively enable and disable discharge transistor MN 3  makes clamp circuit  300  ideal for use in IC devices that may be used in systems that require the device I/O pins to be clamped to a predetermined voltage level (e.g., in PCI environments) or in systems that require the device I/O pins to be tri-statable (e.g., in LVCMOS environments). 
   The resistance of R 4  and the relative sizes of MP 5  and MP 6  may be manipulated to adjust how quickly rising voltages on signal line  105   b  trigger the turning on of discharge transistor MN 3  and how quickly falling voltages on signal line  105   b  turn off discharge transistor MN 3 . Further, the Vtp of MP 6  can be manipulated during fabrication using well-known techniques (e.g., by adjusting the dopant concentrations of various active regions thereof) to adjust the predetermined voltage at which signal line  105   b  is clamped by clamp circuit  300 . 
     FIG. 4  shows a clamp circuit  400  that is another embodiment of clamp circuit  200  of  FIG. 2 . Clamp circuit  400  includes the level shifter circuit  310  and discharge circuit  330  of  FIG. 3 , as well as a voltage detection circuit  420 . For the embodiment of  FIG. 4 , voltage detection circuit  420  includes a PMOS transistor MP 7  coupled between signal line  105   b  and a node G. Level shifter circuit  310  has a first power terminal coupled to node G and a second power terminal coupled to ground potential, and includes an input to receive EN and an output to generate the discharge control signal CTRL at node E. Thus, in contrast to the embodiment of  FIG. 3 , the output of level shifter circuit  310  of clamp circuit  400  directly controls the enabling and disabling of discharge circuit  330  via CTRL at node E, and the positive power terminal of level shifter circuit  310  is coupled to voltage detection circuit  420  at node G. NMOS transistor MN 3 , which forms discharge circuit  330  of  FIG. 4 , is connected between signal line  105   b  and ground potential and has a gate to receive CTRL. 
   To enable clamp circuit  400 , EN is asserted to logic high which, as described above with respect to  FIG. 3 , turns on MP 3  and MN 1  and turns off MP 1  and MN 2 . The non-conductive states of MN 2  and MP 1  isolate node E from ground potential and isolate signal line  105   b  from node D, respectively. The conductive state of MN 1  pulls node D low toward ground potential, which turns on MP 4 , and the conductive state of MP 3  couples node E to node G. 
   If the voltage on signal line  105   b  exceeds VDD by the threshold voltage (Vtp) of MP 7  (e.g., if V( 105   b )&gt;VDD+Vtp(MP 7 )), MP 7  turns on and quickly charges node E toward the signal line voltage via MP 3  and MP 4 . As the voltage at node E rises above the threshold voltage (Vtn) of MN 3 , MN 3  turns on and sinks current from signal line  105   b  to quickly discharge signal line  105   b  towards ground potential. When the voltage on signal line  105   b  drops below VDD+Vtp(MP 7 ), MP 7  turns off and node E quickly discharges toward ground potential through resistor R 4 , thereby turning off transistor MN 3  to stop discharging signal line  105   b.    
   To disable clamp circuit  400 , EN is de-asserted to logic low, which turns off MN 1  and MP 3  and turns on MP 1  and MN 2 . The conductive state of MN 2  discharges node E toward ground potential, which maintains MN 3  in a non-conductive state and thereby prevents MN 3  from sinking current from signal line  105   b . The logic low level at node E turns on MP 2 , thereby charging node D toward the signal line voltage via MP 1  and MP 2 . The resulting logic high state of node D turns off MP 4 , which isolates node E from signal line  105   b.    
   The resistance of R 4  and the relative size of MP 7  may be manipulated to adjust how quickly rising voltages on signal line  105   b  trigger the turning on of discharge transistor MN 3  and how quickly falling voltages on signal line  105   b  turn off discharge transistor MN 3 . Further, the Vtp of MP 7  can be manipulated during fabrication using well-known techniques (e.g., by adjusting the dopant concentrations of various active regions thereof) to adjust the predetermined voltage at which signal line  105   b  is clamped by clamp circuit  400 . 
     FIG. 5  shows a PLD device  500  having clamp circuit  200  connected to a signal line  501  coupled between the PLD&#39;s internal logic  502  and the PLD&#39;s I/O pin  503 . For simplicity, only one I/O pin and clamp circuit  200  are shown in  FIG. 5 . Clamp circuit  200  can be selectively enabled or disabled in response to EN, as described above. PLD device  500  may be any suitable PLD, including field programmable gate arrays (FPGAs) and complex PLDS (CPLDs). PLD logic  502  may include any suitable logic circuits or components such as, for example, CLBs, IOBs, programmable interconnect structures, volatile and non-volatile semiconductor memory elements, microprocessors, and other well-known PLD components. 
   For the embodiments described above, the enable signal EN can be generated in any suitable manner using any suitable circuit. For some embodiments, EN may be generated within the IC device, for example, in response to a determination of whether the device is operating in a PCI environment. For other embodiments, EN can be an externally generated signal (e.g., a user-generated signal) that may be provided to the device via a suitable I/O pin. 
   While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.