Patent Publication Number: US-9904310-B2

Title: Regulator circuit and power system including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This U.S. non-provisional application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2015-0123973, filed on Sep. 2, 2015, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Example embodiments relate generally to power devices, and more particularly to regulator circuits and power systems including regulator circuits. 
     2. Description of the Related Art 
     Recently, semiconductor memory devices have adopted a regulator circuit that converts a high external power supply voltage to a low internal power supply voltage because a level of an internal operating voltage is lowered. The operation of the semiconductor memory devices may be credible after a desired (or, alternatively, a predetermined) interval elapses from a time when the external power supply voltage is applied because the internal power supply voltage is stabilized during the desired (or, alternatively, a predetermined) interval. 
     The regulator circuits have a large-sized power transistor for supplying power to the semiconductor memory devices and the large-sized power transistor has a large capacitance. 
     SUMMARY 
     At least some example embodiments are directed to provide a regulator circuit capable of rapidly compensating for a change of an internal power supply voltage. 
     At least some example embodiments are directed to a power system including a regulator circuit capable of rapidly compensating for a change of an internal power supply voltage. 
     According to at least some example embodiments, a regulator circuit includes a power transistor, a source of the power transistor configured to receive an external power supply voltage, a gate of the power transistor connected to a first node and a drain of the power transistor connected to a second node, the power supply voltage configured to generate an internal power supply voltage, a current mirror configured to provide a first current to a third node, and the current mirror further configured to provide the first node with a second current, the second current having a same magnitude as the first current, a first n-channel metal-oxide semiconductor (NMOS) transistor, a drain of the first NMOS transistor connected to the first node and a source of the first NMOS transistor connected to a fourth node, a second NMOS transistor, a drain of the second NMOS transistor connected to the third node, a gate of the second NMOS transistor connected to the second node and a source of the second NMOS transistor connected to the fourth node, and a current source configured to draw a third current from the fourth node, the current source configured to generate a mirrored current having a same magnitude as the first current based on a voltage of the third node and configured to change a magnitude of the third current based on a difference between the mirrored current and a reference current. 
     According to at least some example embodiments, the current source is configured to increase a voltage adjustment time of the gate of the power transistor to reduce a returning time of a level of the internal power supply voltage to a first level, when i) the power transistor changes the level of the internal power supply voltage from the first level to a second level and ii) the regulator circuit changes a magnitude of a load current flowing through the power transistor. 
     According to at least some example embodiments, the current source is further configured to decrease the magnitude of the third current until the magnitude of the mirrored current reaches a magnitude of the reference current when the magnitude of the mirrored current is greater than the magnitude of the reference current. 
     According to at least some example embodiments, the current source is configured to increase the magnitude of the third current until the magnitude of the mirrored current reaches a magnitude of the reference current when the magnitude of the mirrored current is smaller than the magnitude of the reference current. 
     According to at least some example embodiments, the regulator circuit is configured to decrease a level of the internal power supply voltage, the magnitude of the first current, the magnitude of the second current and a level of a first voltage of the first node when the magnitude of the load current flowing through the power transistor increases and the current source is configured to increase the magnitude of the third current to reduce a returning time of the level of the internal power supply voltage to a previous level before changing, when the magnitude of the load current flowing through the power transistor increases. 
     According to at least some example embodiments, the regulator circuit is configured to increase a level of the internal power supply voltage, the magnitude of the first current, the magnitude of the second current and a level of a first voltage of the first node when the magnitude of the load current flowing through the power transistor decreases and the current source is configured to decrease the magnitude of the third current to reduce a returning time of the level of the internal power supply voltage to a previous level before changing when the magnitude of the load current flowing through the power transistor decreases. 
     According to at least example embodiments, the current source includes a first current generator, a second current generator, a third NMOS transistor and a fourth NMOS transistor, a drain of the third NMOS transistor is connected to the fourth node, a gate of the third NMOS transistor is configured to receive a first reference voltage and a source of the third NMOS transistor is connected to a ground voltage supply, a drain of the fourth NMOS transistor is connected to the fourth node, a gate of the fourth NMOS transistor is connected to a fifth node and a source of the fourth NMOS transistor is connected to the ground voltage supply, the first current generator is connected between an external power supply voltage source and the fifth node, the first current generator is configured to generate the reference current based on a second reference voltage and the first current generator is configured to output the reference current to the fifth node, the second current generator is, connected between the fifth node and the ground voltage supply, the second current generator is configured to draw the mirrored current from the fifth node based on the voltage of the third node, and the current source is configured to generate a comparison current based on the mirrored current and the reference current, the current source is configured to apply the comparison current to the gate of the fourth NMOS transistor. 
     According to at least some example embodiments, the current source is configured to generate a first sub current that flows from the drain of the third NMOS transistor to the source of the third NMOS transistor and a second sub current that flows from the drain of the fourth NMOS transistor to the source of the fourth NMOS transistor, the current source is configured to divide the third current into the first sub current and the second sub current at the fourth node, and the current source is configured to generate the mirrored current such that the magnitude of the mirrored current is inversely proportional to the magnitude of the third current. 
     According to at least some example embodiments, the first current generator includes a first PMOS transistor, a second PMOS transistor and a fifth NMOS transistor, a source of the first PMOS transistor is configured to receive the external power supply voltage, a gate of the first PMOS transistor is connected to a sixth node and a drain of the first PMOS transistor is connected to the fifth node, the drain of the first PMOS transistor provides the reference current to the fifth node, a source of the second PMOS transistor is configured to receive the external power supply voltage, a gate of the second PMOS transistor is connected to the sixth node and a drain of the second PMOS transistor is connected to the sixth node, a drain of the fifth NMOS transistor is connected to the sixth node, a gate of the fifth NMOS transistor is configured to receive the second reference voltage and a source of the fifth NMOS transistor is connected to the ground voltage supply, and the current source is configured to generate the reference current such that the magnitude of the reference current is proportional to the level of the second reference voltage. 
     The regulator of claim  7 , wherein the second current generator includes a first PMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor, a source of the first PMOS transistor is configured to receive the external power supply voltage, a gate of the third PMOS transistor is configured to receive the voltage of the first node and a drain of the first PMOS transistor is connected to a sixth node, a drain of the fifth NMOS transistor is connected to the sixth node, a gate of the fifth NMOS transistor is connected to the sixth node and a source of the fifth NMOS transistor is connected to the ground voltage supply, a drain of the sixth NMOS transistor is connected to the fifth node, the drain of the NMOS transistor is configured to draw the mirrored current from the fifth node, a gate of the NMOS transistor is connected to the seventh node and a source of the NMOS transistor is connected to the ground voltage supply, and the current source is configured to generate the mirrored current such that the magnitude of the mirrored current is proportional to the level of the voltage of the third node. 
     The regulator of claim  1 , wherein the current mirror includes a first p-channel metal-oxide semiconductor (PMOS) transistor and a second PMOS transistor, a source of the first PMOS transistor is configured to receive the external power supply voltage, a gate of the first PMOS transistor is connected to the third node and a drain of the first PMOS transistor is connected to the first node, the drain of the first PMOS is configured to provide the second current through the first node, a source of the second PMOS transistor is configured to receive the external power supply voltage, a gate of the second PMOS transistor is connected to the third node and a drain of the second PMOS transistor is connected to the third node, the drain of the PMOS is configured to provide the first current through the third node, and the current mirror is configured to operate based on an enable signal. 
     According to at least some example embodiments, a power system includes a regulator circuit configured to generate an internal power supply voltage based on an external power supply voltage, and an operation circuit configured to perform a given operation based on the internal power supply voltage, the regulator circuit including, a power transistor, a source of the power transistor configured to receive an external power supply voltage, a gate of the power transistor connected to a first node, a first voltage being a voltage of the first node, and a drain of the power transistor connected to a second node, the drain of the power transistor configured to output the internal power supply voltage, a current mirror configured to provide a first current to a third node, a second voltage being a voltage of the third node, the current mirror further configured to provide the first node with a second current having a same magnitude as the first current, a first n-channel metal-oxide semiconductor (NMOS) transistor, a drain of the first NMOS transistor connected to the first node, a gate of the first NMOS transistor configured to receive a first reference voltage and a source of the first NMOS transistor connected to a fourth node, a second NMOS transistor, a drain of the second NMOS transistor connected to the third node, a gate of the second NMOS transistor connected to the second node and a source of the second NMOS transistor connected to the fourth node, and a current source configured to draw a third current from the fourth node, the current source configured to generate a mirrored current having a same magnitude as the first current based on the second voltage, and change a magnitude of the third current based on the mirrored current and a reference current. 
     According to a least some example embodiments, the current source is configured to increase a voltage adjustment time of the gate of the power transistor to reduce a returning time of a level of the internal power supply voltage to a first level when i) the power transistor changes the level of the internal power supply voltage from the first level to a second level and ii) the regulator circuit changes a magnitude of a load current flowing through the power transistor. 
     According to at least some example embodiments, the current source is configured to decrease the magnitude of the third current until the magnitude of the mirrored current reaches the magnitude of the reference current, when the magnitude of the mirrored current is greater than a magnitude of the reference current. 
     According to at least some example embodiments, the current source is configured to increase the magnitude of the third current until the magnitude of the mirrored current reaches the magnitude of the reference current, when the magnitude of the mirrored current is smaller than a magnitude of the reference current. 
     At least one example embodiment provides a regulator circuit including a power transistor, the power transistor configured to generate an internal power supply voltage based on an external power supply voltage, a gate of the power transistor coupled to a first node, a current mirror configured to output a first current to a second node and a second current to the first node, at least first and second n-channel metal-oxide semiconductor (NMOS) transistors coupled to the first node and the second node, respectively, each of the first and second NMOS transistors having a source connected to a third node and a current source connected between the third node and a ground voltage supply, the current source configured to change a magnitude of a third current from the third node based on the first current and the second current. 
     In an example embodiment, the current source is configured to generate a mirrored current having a same magnitude as the first current based on a voltage of the second node and change the magnitude of the third current based on a difference between the mirrored current and a reference current. 
     In an example embodiment, the current source is configured to generate the voltage of the second node. 
     In an example embodiment, a gate of one of the first and second n-channel metal-oxide semiconductor (NMOS) transistors and a drain of the power transistor are connected at a common node. 
     In an example embodiment, the current source includes a current generation circuit configured to generate a fourth current based on the external power supply voltage and a first reference voltage, a third NMOS transistor, a gate of the third NMOS transistor configured to receive the fourth current, a drain of the third NMOS transistor configured to receive a first portion of the third current and a source of the third NMOS transistor connected to the ground voltage supply and a fourth NMOS transistor, a gate of the fourth NMOS transistor configured to receive a second reference voltage, a drain of the fourth NMOS transistor configured to receive a second portion of the third current and a source of the fourth NMOS transistor connected to the ground voltage supply. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. 
         FIG. 1  illustrates a regulator circuit according to at least one example embodiment. 
         FIG. 2  illustrates a current source in the regulator circuit of  FIG. 1  according to at least one example embodiment. 
         FIG. 3  is a circuit diagram illustrating an example of a current generation unit in the current source of  FIG. 2  according to at least one example embodiment. 
         FIG. 4  is a circuit diagram illustrating another example of the current generation unit in the current source of  FIG. 2  according to at least one example embodiment. 
         FIG. 5  is a circuit diagram illustrating an example of a current mirror in the regulator circuit of  FIG. 1  according to at least one example embodiment. 
         FIG. 6  is a circuit diagram illustrating another example of the current mirror in the regulator circuit of  FIG. 1  according to at least one example embodiment. 
         FIGS. 7 through 10  respectively illustrate waveforms of the operation of the regulator circuit of  FIG. 1  according to at least one example embodiment. 
         FIG. 11  is a block diagram illustrating a power system according to at least one example embodiment. 
         FIG. 12  is a block diagram illustrating a solid state drive (SSD) system according to at least one example embodiment. 
         FIG. 13  is a block diagram illustrating a mobile system according to at least one example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like numerals refer to like elements throughout. 
     It will be understood that, although the terms first, second, third etc, may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). 
     The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  illustrates a regulator circuit according to at least one example embodiment. 
     Referring to  FIG. 1 , a regulator circuit  100  includes a power transistor PTR, a current mirror  120 , a first n-channel metal-oxide semiconductor (NMOS) transistor NT 11 , a second NMOS transistor NT 12  and a current source  110 . A load  130  may be coupled to the second NMOS transistor NT 12  and the power transistor PTR. 
     The power transistor PTR has a source connected to an external power supply voltage EVDD, a gate connected to a first node N 11  having a first voltage V 1  and a drain connected to a second node N 12  that outputs an internal power supply voltage IVDD. The load  130  is connected between the second node N 12  and a ground voltage GND. A load current ILOAD may flow from the source to the drain of the power transistor PTR. That is, the load current ILOAD may flow through the power transistor PTR. Almost all the entire load current ILOAD flows to the load  130  because a little portion of the load current ILOAD flows into a gate of the second NMOS transistor NT 12 . A magnitude of the load current ILOAD may change as a time elapses. 
     The current mirror  120  provides a first current I 1  to a third node N 13  having a second voltage V 2  and provides the first node N 11  with a second current I 2  having a same magnitude as the first current I 1 . The current mirror  120  will be described later with reference to  FIGS. 5 and 6 . 
     The first NMOS transistor NT 11  has a drain connected to the first node N 11 , a gate receiving a first reference voltage VREF 1  and a source connected to a fourth node N 14 . The second NMOS transistor NT 12  has a drain connected to the third node N 13 , a gate connected to the second node N 12  and a source connected to the fourth node N 14 . The current source  110  is connected to the third node N 13 , the fourth node N 14  and the ground voltage GND, draws a third current I 3  from the fourth node N 14 , generates a mirrored current having a same magnitude as the first current I 1  based on the second voltage V 2  and changes a magnitude of the third current I 3  based on a difference between the mirrored current and a reference current. The current source  110  will be described later with reference to  FIGS. 2 through 4 . 
     In some example embodiments, when a level of the internal power supply voltage IVDD is changed from a first level to a second level different from the first level as a magnitude of the load current ILOAD is changed, the current source  110  may increase a charging/discharging time of the gate of the power transistor PTR to reduce a returning time of the internal power supply voltage IVDD to the first level by temporarily adjusting the third current I 3 . 
     When the magnitude of the load current ILOAD decreases, a voltage drop between the source and the drain of the power transistor PTR decreases, and the level of the internal power supply voltage IVDD increases. As a voltage difference between the gate and the source of the second NMOS transistor NT 12  increases, the magnitude of the first current I 1  increases. When the mirrored current corresponding to the first current I 1  is greater than the reference current, the current source  110  may decrease the magnitude of the third current I 3  until the magnitude of the mirrored current is same as the magnitude of the reference current. Since the second current I 2  is the same as the first current I 1  and a fifth current I 5  decreases due to the decrease of the third current I 3 , the magnitude of a fourth current I 4 , flowing from the first node N 11  to the gate of the power transistor PTR increases. Since the magnitude of the second current I 2  increases, the level of the first voltage V 1  also increases. Since the gate of the power transistor PTR is charged with the increased fourth current I 4 , a gate voltage of the power transistor PTR reaches the level of the first voltage V 1  that increases rapidly and the level of the internal power supply voltage IVDD decreases to return to a level corresponding to a level that the internal power supply voltage IVDD has before the internal power supply voltage IVDD increases. 
     When the magnitude of the load current ILOAD increases, the voltage drop between the source and the drain of the power transistor PTR increases, and the level of the internal power supply voltage IVDD decreases. As the voltage difference between the gate and the source of the second NMOS transistor NT 12  decreases, the magnitude of the first current I 1  decreases. When the mirrored current corresponding to the first current I 1  is smaller than the reference current, the current source  110  may increase the magnitude of the third current I 3  until the magnitude of the mirrored current is same as the magnitude of the reference current. Since the second current I 2  is the same as the first current I 1  and the fifth current I 5  increases due to the increase of the third current I 3 , the magnitude of the fourth current I 4 , flowing from the gate of the power transistor PTR to the first node N 11  increases. Since the magnitude of the second current I 2  decreases, the level of the first voltage V 1  also decreases. Since the gate of the power transistor PTR is discharged through the increased fourth current I 4 , the gate voltage of the power transistor PTR reaches the level of the first voltage V 1  that decreases rapidly and the level of the internal power supply voltage IVDD increases to return to a level corresponding to a level that the internal power supply voltage IVDD has before the internal power supply voltage IVDD decreases. The reference current will be described later with reference to  FIGS. 2 through 4 . 
       FIG. 2  illustrates the current source in the regulator circuit of  FIG. 1  according to at least one example embodiment. 
     Referring to  FIG. 1 , the current source  110  includes a current generation unit  111 , a third NMOS transistor NT 21  and a fourth NMOS transistor NT 22 . The current generation unit  111  includes a first current generator  112  and a second current generator  113 . 
     The third NMOS transistor NT 21  has a drain connected to the fourth node N 14 , a gate receiving a second reference voltage VREF 2  and a source connected to the ground voltage GND. The fourth NMOS transistor NT 22  has a drain connected to the fourth node N 14 , a gate connected to a fifth node N 21  and a source connected to the ground voltage GND. The second reference voltage VREF 2  may have a fixed level. 
     A first sub current I 31  flows from the drain to the source of the third NMOS transistor NT 21  and a second sub current I 32  from the drain to the source of the fourth NMOS transistor NT 22 . The third current I 3  may be divided into the first sub current I 31  and the second sub current I 32  at the fourth node N 14 . 
     The first current generator  112  is connected between the external power supply voltage EVDD and the fifth node N 21 , generates a reference current IREF based on a third reference voltage VREF 3  and outputs the reference current IREF to the fifth node N 21 . The second current generator  113  is connected between the fifth node N 21  and the ground voltage GND and draws a mirrored current IMIR from the fifth node N 21  based on the second voltage V 2 . A comparison current ICOMPARED corresponding to a current obtained by subtracting the mirrored current IMIR from the reference current IREF is provided to the gate of the fourth NMOS transistor NT 22 . 
     A magnitude of the mirrored current IMIR may be inversely proportional to the magnitude of the third current I 3 . The magnitude of the mirrored current IMIR may be inversely proportional to a magnitude of the second sub current I 32 . When the level of the internal power supply voltage IVDD decreases and the magnitude of the first current I 1  decreases, the magnitude of the mirrored current IMIR decreases and a magnitude of the comparison current ICOMPARED increases. Accordingly, the gate voltage of the fourth NMOS transistor NT 22  increases and the magnitudes of the second sub current I 32  and the third current I 3  increases. On the contrary, when the level of the internal power supply voltage IVDD increases and the magnitude of the first current I 1  increases, the magnitude of the mirrored current IMIR increases and the magnitude of the comparison current ICOMPARED decreases. Accordingly, the gate voltage of the fourth NMOS transistor NT 22  decreases and the magnitudes of the second sub current I 32  and the third current I 3  decreases. 
       FIG. 3  is a circuit diagram illustrating an example of the current generation unit in the current source of  FIG. 2  according to at least one example embodiment. 
     Referring to  FIG. 3 , a current generation unit  111 A includes a first current generator  112 A and a second current generator  113 A. The second current generator  113 A includes a first p-channel metal-oxide semiconductor (PMOS) transistor PT 31 A, a first NMOS transistor NT 31 A and a second NMOS transistor NT 32 A. The first current generator  112 A includes a second PMOS transistor PT 32 A, a third PMOS transistor PT 33 A and a third NMOS transistor NT 33 A. 
     The first PMOS transistor PT 31 A has a source connected to the external power supply voltage EVDD, a gate receiving the second voltage V 2  and a drain connected to a node N 32 A. The second PMOS transistor PT 32 A has a source connected to the external power supply voltage EVDD, a gate connected to a node N 31 A and a drain, connected to the fifth node N 21 , that provides the reference current IREF to the fifth node N 21 . The third PMOS transistor PT 33 A has a source connected to the external power supply voltage EVDD, a gate connected to the node N 31 A and a drain connected to the node N 31 A. 
     The first NMOS transistor NT 31 A has a drain connected to the node N 32 A, a gate connected to the node N 32 A and a source connected to the ground voltage GND. The second NMOS transistor NT 32 A has a drain, connected to the fifth node N 21 , which draws the mirrored current IMIR from the fifth node N 21 , a gate connected to the node N 32 A and a source connected to the ground voltage GND. The third NMOS transistor NT 33 A has a drain connected to the node N 31 A, a gate receiving the third reference voltage VREF 3  and a source connected to the ground voltage GND. 
     Since the third NMOS transistor NT 33 A generates a set current ISETA based on the third reference voltage VREF 3  and the second and third PMOS transistors PT 32 A and PT 33 A operate as a current mirror, a magnitude of the reference current IREF is same as a magnitude of the set current ISETA. Therefore, the magnitude of the reference current IREF may be proportional to the level of the third reference voltage VREF 3 . 
     Since the first PMOS transistor PT 31 A generates an internal current IINTA in response to the second voltage V 2  and the first NMOS transistor NT 31 A and the second NMOS transistor NT 32 A operate as a current mirror, a magnitude of the mirrored current IMIR is same as the magnitude of the internal current IINTA. Therefore, the magnitude of the mirrored current IMIR may be proportional to the level of the second voltage V 2 . 
     When the magnitude of the mirrored current IMIR is greater than the magnitude of the reference current IREF, the current source  111 A decreases the magnitude of the comparison current ICOMPARED until the magnitude of the mirrored current IMIR reaches the magnitude of the reference current IREF, and thus decreases the magnitudes the first current I 1  and the mirrored current IMIR. 
     When the magnitude of the mirrored current IMIR is smaller than the magnitude of the reference current IREF, the current source  111 A increases the magnitude of the comparison current ICOMPARED until the magnitude of the mirrored current reaches the magnitude of the reference current IREF, and thus increases the magnitudes the first current I 1  and the mirrored current IMIR. 
       FIG. 4  is a circuit diagram illustrating another example of the current generation unit in the current source of  FIG. 2  according to at least one example embodiment. 
     Referring to  FIG. 4 , a current generation unit  111 B includes an enable transistor TREN 1 , a first current generator  112 B and a second current generator  113 B. 
     The second current generator  113 B includes a first p-channel metal-oxide semiconductor (PMOS) transistor PT 31 B, a first NMOS transistor NT 31 B and a second NMOS transistor NT 32 B. The first current generator  112 B includes a second PMOS transistor PT 32 B, a third PMOS transistor PT 33 B and a third NMOS transistor NT 33 B. 
     The enable transistor TREN 1  has a source connected to the external power supply voltage EVDD, a gate receiving an enable signal SIGEN and a drain connected to a node N 33 B. The first PMOS transistor PT 31 B has a source connected to the node N 33 B, a gate receiving the second voltage V 2  and a drain connected to a node N 32 B. The second PMOS transistor PT 32 B has a source connected to the node N 33 B, a gate connected to a node N 31 B and a drain, connected to the fifth node N 21 , that provides the reference current IREF to the fifth node N 21 . The third PMOS transistor PT 33 B has a source connected to the node N 33 B, a gate connected to the node N 31 B and a drain connected to the node N 31 B. 
     The first NMOS transistor NT 31 B has a drain connected to the node N 32 B, a gate connected to the node N 32 B and a source connected to the ground voltage GND. The second NMOS transistor NT 32 B has a drain, connected to the fifth node N 21 , which draws the mirrored current IMIR from the fifth node N 21 , a gate connected to the node N 32 B and a source connected to the ground voltage GND. The third NMOS transistor NT 33 B has a drain connected to the node N 31 B, a gate receiving the third reference voltage VREF 3  and a source connected to the ground voltage GND. 
     Since the third NMOS transistor NT 33 B generates a set current ISETB based on the third reference voltage VREF 3  and the second and third PMOS transistors PT 32 B and PT 33 B operate as a current mirror, a magnitude of the reference current IREF is same as a magnitude of the set current ISETB. Therefore, the magnitude of the reference current IREF may be proportional to the level of the third reference voltage VREF 3 . 
     Since the first PMOS transistor PT 31 B generates an internal current IINTA in response to the second voltage V 2  and the first NMOS transistor NT 31 B and the second NMOS transistor NT 32 B operate as a current mirror, a magnitude of the mirrored current IMIR is same as the magnitude of the internal current IINTA. Therefore, the magnitude of the mirrored current IMIR may be proportional to the level of the second voltage V 2 . 
     When the magnitude of the mirrored current IMIR is greater than the magnitude of the reference current IREF, the current source  111 B decreases the magnitude of the comparison current ICOMPARED until the magnitude of the mirrored current IMIR reaches the magnitude of the reference current IREF, and thus decreases the magnitudes the first current I 1  and the mirrored current IMIR. 
     When the magnitude of the mirrored current IMIR is smaller than the magnitude of the reference current IREF, the current source  111 B increases the magnitude of the comparison current ICOMPARED until the magnitude of the mirrored current IMIR reaches the magnitude of the reference current IREF, and thus increases the magnitudes the first current I 1  and the mirrored current IMIR. 
     In addition, the current generation unit  111 B is activated, when the enable signal SIGEN has a logic low level. 
       FIG. 5  is a circuit diagram illustrating an example of the current mirror in the regulator circuit according to at least one example embodiment. 
     Referring to  FIG. 5 , a current mirror  120 A includes a first PMOS transistor PT 41 A and a second PMOS transistor PT 42 A. 
     The first PMOS transistor PT 41 A has a source connected to the external power supply voltage EVDD, a gate connected to the third node N 13  and a drain, connected to the first node N 11 , which provides the second current I 2  through the first node N 11 . The second PMOS transistor PT 42 A has source connected to the external power supply voltage EVDD, a gate connected to the third node N 13  and a drain, connected to the third node N 13 , which provides the first current I 1  through the third node N 13 . 
     When a size of the first PMOS transistor PT 41 A is same as a size of the second PMOS transistor PT 42 A, the current mirror  120 A generates the second current I 2  by mirroring the first current I 1 . That is, the magnitude of the first current I 1  is same as the magnitude of the second current I 2 . 
       FIG. 6  is a circuit diagram illustrating another example of the current mirror in the regulator circuit according to at least one example embodiment. 
     Referring to  FIG. 6 , a current mirror  120 B includes an enable transistor TREN 2 , first PMOS transistor PT 41 B and a second PMOS transistor PT 42 B. 
     The enable transistor TREN 2  has a source connected to the external power supply voltage EVDD, a gate receiving the enable signal SIGEN and a drain connected to an internal node NINT. The first PMOS transistor PT 41 B has a source connected to the internal node NINT, a gate connected to the third node N 13  and a drain, connected to the first node N 11 , which provides the second current I 2  through the first node N 11 . The second PMOS transistor PT 42 A has source connected to the internal node NINT, a gate connected to the third node N 13  and a drain, connected to the third node N 13 , which provides the first current I 1  through the third node N 13 . 
     When a size of the first PMOS transistor PT 41 B is same as a size of the second PMOS transistor PT 42 B, the current mirror  120 B generates the second current I 2  by mirroring the first current I 1 . That is, the magnitude of the first current I 1  is same as the magnitude of the second current I 2 . 
       FIGS. 7 through 10  respectively illustrate waveforms of the operation of the regulator circuit of  FIG. 1  according to at least one example embodiment. 
       FIGS. 7 and 8  illustrate examples when the fourth NMOS transistor NT 22  does not operate. 
     Referring to  FIGS. 1 and 7 , when the magnitude of the load current ILOAD increases at a first time point  211 , the voltage drop between the source and the drain of the power transistor PTR increases and the level of the internal power supply voltage IVDD decreases. As the voltage difference between the gate and the source of the second NMOS transistor NT 12  decreases, the magnitudes of the first current I 1  and the second current I 2  decrease. Since a capacitance of the gate of the power transistor PTR is high, the level of the first voltage V 1  decreases until a second time point  212 . An interval from the first time point  211  to the second time point  212  may be referred to as a first delay time D 1 . After the first delay time D 1  elapses, the level of the internal power supply voltage IVDD and the magnitude of the first current I 1  return to their initial value before the first time point  211  respectively. 
     The third NMOS transistor NT 21  is activated in the current source  110 , the third current I 3  only includes the first sub current I 31  determined by the second reference voltage VREF 2  that has a fixed level, the first delay time D 1  is long and it takes a long time for the regulator circuit  100  to be stabilized. 
     Referring to  FIGS. 1 and 8 , when the magnitude of the load current ILOAD decreases at a first time point  221 , the voltage drop between the source and the drain of the power transistor PTR decreases and the level of the internal power supply voltage IVDD increases. As the voltage difference between the gate and the source of the second NMOS transistor NT 12  increases, the magnitudes of the first current I 1  and the second current I 2  increase. Since a capacitance of the gate of the power transistor PTR is high, the level of the first voltage V 1  increases until a second time point  222 . An interval from the first time point  221  to the second time point  222  may be referred to as a second delay time D 2 . After the second delay time D 2  elapses, the level of the internal power supply voltage IVDD and the magnitude of the first current I 1  return to their initial value before change respectively. 
     The third NMOS transistor NT 21  is activated in the current source  110 , the third current I 3  only includes the first sub current I 31  determined by the second reference voltage VREF 2  that has a fixed level, the second delay time D 2  is long and it takes a long time for the regulator circuit  100  to be stabilized. 
       FIGS. 9 and 10  illustrate examples when all of the components of the current source  110  of  FIG. 2  operate. 
     Referring to  FIGS. 1 and 9 , when the magnitude of the load current ILOAD increases at a first time point  231 , the voltage drop between the source and the drain of the power transistor PTR increases and the level of the internal power supply voltage IVDD decreases. As the voltage difference between the gate and the source of the second NMOS transistor NT 12  decreases, the magnitudes of the first current I 1  and the second current I 2  decrease. Since the capacitance of the gate of the power transistor PTR is high, the level of the first voltage V 1  decreases until a second time point  232 . An interval from the first time point  231  to the second time point  232  may be referred to as a third delay time D 3 . After the third delay time D 3  elapses, the level of the internal power supply voltage IVDD and the magnitude of the first current I 1  return to their initial value before change respectively. 
     When the magnitude of the first current I 1  decreases, the magnitude of the mirrored current IMIR decreases and the magnitudes of the second sub current I 32  and the third current I 3  increase. Therefore, the third delay time D 3  is shorter than the first delay time D 1  or the second delay time D 2  and it takes a shorter time for the regulator circuit  100  to be stabilized. Since the magnitude of the second sub current I 32  temporarily increases and returns to its initial value, additional power consumption of the current source  110  may be minimized. 
     Referring to  FIGS. 1 and 10 , when the magnitude of the load current ILOAD decreases at a first time point  241 , the voltage drop between the source and the drain of the power transistor PTR decreases and the level of the internal power supply voltage IVDD increases. As the voltage difference between the gate and the source of the second NMOS transistor NT 12  increases, the magnitudes of the first current I 1  and the second current I 2  increase. Since the capacitance of the gate of the power transistor PTR is high, the level of the first voltage V 1  increases until a second time point  242 . An interval from the first time point  241  the second time point  242  may be referred to as a fourth delay time D 4 . After the fourth delay time D 4  elapses, the level of the internal power supply voltage IVDD and the magnitude of the first current return to their initial value before change respectively. 
     When the magnitude of the first current I 1  increases, the magnitude of the mirrored current IMIR increases and the magnitudes of the second sub current I 32  and the third current I 3  decrease. Therefore, the third fourth time D 4  is shorter than the first delay time D 1  or the second delay time D 2  and it takes shorter time for the regulator circuit  100  to be stabilized. Since the magnitude of the second sub current I 32  temporarily increases and returns to its initial value, additional power consumption of the current source  110  may be minimized. 
       FIG. 11  is a block diagram illustrating a power system according to at least one example embodiment. 
     Referring to  FIG. 11 , a power system  200  includes a regulator circuit  210  and an operation circuit The regulator circuit  210  generates an internal power supply voltage IVDD based on an external power supply voltage EVDD. The operation circuit  220  may perform a given operation based on the internal power supply voltage IVDD. 
     The regulator circuit  210  may employ the regulator circuit  100  of  FIG. 1 . Therefore, the regulator circuit  210  may include a power transistor, a current mirror, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to the external power supply voltage EVDD, a gate connected to a first node having a first voltage and a drain connected to a second node that outputs the internal power supply voltage. The current mirror provides a first current to a third node having a second voltage and provides the first node with a second current having a same magnitude as the first current. The first NMOS transistor has a drain connected to the first node, a gate receiving a reference voltage and a source connected to a fourth node. The second NMOS transistor has a drain connected to the third node, a gate connected to the second node and a source connected to the fourth node. The current source is connected to the third node, the fourth node and the ground voltage, draws a third current from the fourth node generates a mirrored current having a same magnitude as the first current based on the second voltage and changes a magnitude of the third current based on a difference between the mirrored current and a reference current. 
     When a level of the internal power supply voltage is changed from a first level to a second level different from the first level as a magnitude of a load current ILOAD flowing from the source to the drain of the power transistor is changed, the current source may increase a charging/discharging time of the gate of the power transistor to reduce a returning time of the level of the internal power supply voltage IVDD to the first level by temporarily adjusting the third current. 
     The regulator circuit  210  may be fully understood with reference to  FIGS. 1 through 10 . 
       FIG. 12  is a block diagram illustrating a solid state drive (SSD) system according to at least one example embodiment. 
     Referring to  FIG. 12 , an SSD system  300  includes a host  310  and an SSD  320 . The SSD  320  includes first through n-th non-volatile memory devices  323 - 1 ,  323 - 2 , or  323 -n and a SSD controller  322 . Here, n represents an integer greater than or equal to 2. The first through n-th non-volatile memory devices  323 - 1   323 - 2 , or  323 -n may be used as a storage medium of the SSD  320 . 
     Each of the first through n-th non-volatile memory devices  323 - 1 ,  323 - 2 , or  323 -n may include a memory cell array formed on a substrate with a three-dimensional structure. Memory cells included in the memory cell array may be formed in a direction perpendicular to the substrate. The memory cells included in the memory cell array may be connected to a plurality of word lines, which are stacked in a direction perpendicular to the substrate, and a plurality of bit lines, which are formed in a direction parallel to the substrate. 
     The SSD controller  322  is coupled to the first through n-th non-volatile memory devices  323 - 1 ,  323 - 2 , or  323 -n through first to n-th channels CH 1 , CH 2 , to CHn, respectively. 
     The SSD controller  322  exchanges a signal SGL with the host  310  through a signal connector  324 . The signal SGL may include a command, an address and data. The SSD controller  322  may perform a program operation and a read operation on the first through n-th non-volatile memory devices  323 - 1 ,  323 - 2 , or  323 -n according to the command received from the host  310 . 
     The SSD  320  may further include an auxiliary power supply  326 . The auxiliary power supply  126  may receive a power PWR from the host  310  through a power connector  325  and provide a power to the SSD controller  322 . The auxiliary power supply  326  may be placed inside or outside the SSD  320 . For example, the auxiliary power supply  326  may be placed in a main board and provide auxiliary power to the SSD  320 . 
     The auxiliary power supply  326  may include the regulator circuit of  FIG. 1 . 
       FIG. 13  is a block diagram illustrating a mobile system according to at least one example embodiment. 
     Referring to  FIG. 13 , a mobile system  400  includes an application processor  410 , a connectivity unit  420 , a user interface  430 , a non-volatile memory device  440 , a volatile memory device  450  and a power supply  460 . 
     In at least one example embodiment, the mobile system  400  may be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc. 
     The application processor  410  may execute applications, such as a web browser, a game application, a video player, etc. In some example embodiments, the application processor  410  may include a single core or multiple cores. For example, the application processor  410  may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. The application processor  410  may include an internal or external cache memory. 
     The connectivity unit  420  may perform wired or wireless communication with an external device. For example, the connectivity unit  420  may perform Ethernet communication, near field communication (NFC), radio frequency identification (RFID) communication, mobile telecommunication, memory card communication, universal serial bus (USB) communication, etc. In at least one example embodiment, the connectivity unit  420  may include a baseband chipset that supports communications, such as global system for mobile communications (GSM), general packet radio service (GPRS), wideband code division multiple access (WCDMA), high speed downlink/uplink packet access (HSxPA), etc. 
     The non-volatile memory device  440  may store a boot image for booting the mobile system  400 . 
     The non-volatile memory device  440  may include a memory cell array formed on a substrate in a three-dimensional structure. Memory cells included in the memory cell array may be formed in a direction perpendicular to the substrate. The memory cells included in the memory cell array may be connected to a plurality of word lines, which are stacked in a direction perpendicular to the substrate, and a plurality of bit lines, which are formed in a direction parallel to the substrate. 
     The volatile memory device  450  may store data processed by the application processor  410 , or may operate as a working memory. 
     The user interface  430  may include at least one input device, such as a keypad, a touch screen, etc., and at least one output device, such as a speaker, a display device, etc. 
     The power supply  460  may supply an operating voltage to the mobile system  400 . The power supply includes a regulator circuit. The regulator circuit may employ the regulator circuit  100  of  FIG. 1 . The regulator circuit may employ the regulator circuit  210  in  FIG. 11  and the application processor  410 , the connectivity unit  420 , the user interface  430 , the non-volatile memory device  440  and the volatile memory device  450  may correspond to the operation circuit  220  in  FIG. 11 . 
     In at least one example embodiment, the mobile system  400  may further include an image processor, and/or a storage device, such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. 
     In at least one example embodiment, the mobile system  400  and/or components of the mobile system  400  may be packaged in various forms, such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), or wafer-level processed stack package (WSP). 
     The present disclosure may be applied to various electronic devices including a regulator circuit. For example, the present disclosure may be applied to systems such as a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc. 
     The foregoing is illustrative of at least one example embodiment and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.