Patent Publication Number: US-2023138324-A1

Title: Package-level esd protection

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 63/274,032, filed on Nov. 1, 2021. The content of the application is incorporated herein by reference. 
    
    
     BACKGROUND 
     In order to protect circuits of a die from being damaged by electrostatic discharge (ESD), one or more ESD protection circuits are designed within the die to pass a human body model (HBM) and charged device model (CDM) of ESD specifications. However, the die-level ESD protection circuits generally have higher parasitic effects; and if the die-level ESD protection circuits are designed with smaller size to lower the parasitic effects, the die-level ESD protection circuits will not have good ESD robustness for high-speed radio-frequency (RF) designs. 
     SUMMARY 
     It is therefore an objective of the present invention to provide a package-level ESD design, which has lower parasitic effects and better ESD robustness, to solve the above-mentioned problems. 
     According to one embodiment of the present invention, a package comprising a first pad, a die and at least one package ESD component is disclosed. The first pad is configured to receive a signal from a device external to the package or transmit a signal from an internal circuit to the device external to the package. The die comprises a second pad and the internal circuit, wherein the internal circuit is configured to receive the signal from the first pad via the second pad or transmit the signal from the internal circuit to the first pad via the second pad. The at least one ESD component is positioned outside the die. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a diagram illustrating a package according to one embodiment of the present invention 
         FIG.  2    is a diagram illustrating the package ESD components according to a first embodiment of the present invention. 
         FIG.  3    is a diagram illustrating the package ESD components according to a second embodiment of the present invention. 
         FIG.  4    is a diagram illustrating the package ESD components according to a third embodiment of the present invention. 
         FIG.  5    is a diagram illustrating the package ESD components according to a fourth embodiment of the present invention. 
         FIG.  6    is a diagram illustrating the package ESD components according to a fifth embodiment of the present invention. 
         FIG.  7    is a diagram illustrating the package ESD components according to a sixth embodiment of the present invention. 
         FIG.  8    is a diagram illustrating the package ESD components according to a seventh embodiment of the present invention. 
         FIG.  9    is a diagram showing some embodiments of the package ESD blocking component. 
         FIG.  10    is a diagram showing some embodiments of the package ESD blocking component. 
         FIG.  11    is a diagram of using the inductor to implement the package ESD conducting component when the die comprises a circuit for processing signals according to one embodiment of the present invention. 
         FIG.  12    is a diagram illustrating the designs of the inductor shown in  FIG.  11    according to one embodiment of the present invention. 
         FIG.  13    is a diagram illustrating a vertical cross-sectional view of the circuit connected to the BGA ball. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
       FIG.  1    is a diagram illustrating a package  100  according to one embodiment of the present invention, wherein the package  100  can be any integrated circuit (IC) package such as chip-on-wafer-on-substrate (CoWoS), integrated fan out (InFO) or any other two-dimensional IC package or three-dimensional IC package. As shown in  FIG.  1   , the package  100  comprises a die  110 , a package ESD conducting component  120 , a package ESD conducting component  130 , a package ESD blocking component  140  and a plurality of pads (a pad N 1  serves as an example), wherein the die  110  comprises a plurality of pads (a pad N 2  serves as an example), an internal circuit  112 , a die ESD component  114  and a die ESD component  116 . In this embodiment, the pad N 1  may be a pin or one of a ball grid array (BGA), and the pad N 1  is used to receive a signal from a device outside the package  100 , or the pad N 1  is used to transmit a signal from the internal circuit  112  to the device outside the package  100 . The package ESD conducting component  120  is coupled between a supply voltage VDD and the pad N 1 , the package ESD conducting component  130  connected between a ground voltage and the pad N 1 , and the package ESD blocking component  140  is coupled between the pad N 1  and the pad N 2 . In addition, the die ESD component is coupled between the supply voltage VDD and the pad N 2 , the die ESD component is coupled between the ground voltage and the pad N 2 , and the internal circuit  112  is configured to receive and process the signal from the pad N 1  via the package ESD blocking component  140  and the pad N 2 . 
     In the embodiment shown in  FIG.  1   , three package ESD components are designed within the package  100  to protect the internal circuit  112  against the ESD damage, however, the number and type of package ESD components are not limitations of the present invention. In another embodiment, one or two of the package ESD conducting component  120 , the package ESD conducting component  130  and the package ESD blocking component  140  can be removed from the package  100 . 
     By designing the package ESD components between the pad N 1  and the die  110 , most of the ESD current can be bypassed by the package ESD conducting component  130  or blocked by the package ESD blocking component  140 , so the remaining ESD current flowing into the die  110  will only induce small voltage drop, and package  100  can meet the requirements of the ESD specifications for high-speed RF designs. In addition, because the package ESD components with lower parasitic effects have better quality factor control and ESD robustness, the package  100  with the package ESD components will have better performance. 
       FIG.  2    is a diagram illustrating the package ESD components according to a first embodiment of the present invention. As shown in  FIG.  2   , the package  100  comprises the package ESD conducting component  130  and the package ESD blocking component  140 , wherein the package ESD conducting component  130  is implemented by using an inductor L 1 , that is one node of the inductor L 1  is coupled to the pad N 1 , and the other node of the inductor L 1  is coupled to the ground voltage. 
       FIG.  3    is a diagram illustrating the package ESD components according to a second embodiment of the present invention. As shown in  FIG.  3   , the package  100  comprises the package ESD conducting component  120 , the package ESD conducting component  130  and the package ESD blocking component  140 . The package ESD conducting component  120  is implemented by using a diode D 1 , wherein an anode of the diode D 1  is coupled to the pad N 1 , and a cathode of the diode D 1  is coupled to the supply voltage VDD. The package ESD conducting component  130  is implemented by using a diode D 2 , wherein an anode of the diode D 2  is coupled to the ground voltage, and a cathode of the diode D 2  is coupled to the pad N 1 . 
       FIG.  4    is a diagram illustrating the package ESD components according to a third embodiment of the present invention. As shown in  FIG.  4   , the package  100  comprises the package ESD conducting component  120 , the package ESD conducting component  130  and the package ESD blocking component  140 . The package ESD conducting component  120  is implemented by using a P-type transistor MP 1 , wherein a source electrode of the P-type transistor MP 1  is coupled to the supply voltage VDD, and a drain electrode of the P-type transistor MP 1  is coupled to the pad N 1 . The package ESD conducting component  130  is implemented by using an N-type transistor MN 1 , wherein a source electrode of the N-type transistor MN 1  is coupled to the ground voltage, and a drain electrode of the N-type transistor MN 1  is coupled to the pad N 1 . 
       FIG.  5    is a diagram illustrating the package ESD components according to a fourth embodiment of the present invention. As shown in  FIG.  5   , the package  100  comprises the package ESD conducting component  130  and the package ESD blocking component  140 . The package ESD conducting component  130  is implemented by using forward diode (s) D 4  and D 5  and reverse diode(s) D 3 . An anode of the diode D 3  is coupled to the ground voltage, and a cathode of the diode D 3  is coupled to the pad N 1 . The diodes D 4  and D 5  are connected in series, wherein an anode of the diode D 4  is coupled to the pad N 1 , and a cathode of the diode D 5  is coupled to the ground voltage. 
       FIG.  6    is a diagram illustrating the package ESD components according to a fifth embodiment of the present invention. As shown in  FIG.  6   , the package  100  comprises the package ESD conducting component  130  and the package ESD blocking component  140 . The package ESD conducting component  130  is implemented by using an inductor L 2  and a capacitor C 1  connected in series, wherein a first node of the inductor L 2  is coupled to the pad N 1 , a second node of the inductor L 2  is coupled to a first node of the capacitor C 1 , and a second node of the capacitor C 1  is coupled to the ground voltage. 
       FIG.  7    is a diagram illustrating the package ESD components according to a sixth embodiment of the present invention. As shown in  FIG.  7   , the package  100  comprises the package ESD conducting component  130  and the package ESD blocking component  140 . The package ESD conducting component  130  is implemented by using an inductor L 3  and a capacitor C 2  connected in parallel, wherein a first node of the inductor L 3  is coupled to the pad N 1 , a second node of the inductor L 3  is coupled to the ground voltage, a first node of the capacitor C 2  is coupled to the pad N 1 , a second node of the capacitor C 2  is coupled to the ground voltage. 
       FIG.  8    is a diagram illustrating the package ESD components according to a seventh embodiment of the present invention. As shown in  FIG.  8   , the package  100  comprises the package ESD conducting component  130  and the package ESD blocking component  140 . The package ESD conducting component  130  is implemented by using an inductor L 4 , forward diode(s) D 7  and D 8  and reverse diode(s) D 6 . A first node of the inductor L 4  is coupled to the pad N 1 , an anode of the diode D 3  is coupled to the ground voltage, and a cathode of the diode D 3  is coupled to a second node of the inductor L 4 . The diodes D 4  and D 5  are connected in series, wherein an anode of the diode D 4  is coupled to the second node of the inductor L 4 , and a cathode of the diode D 5  is coupled to the ground voltage. 
       FIG.  9    is a diagram showing some embodiments of the package ESD blocking component  140  coupled between the pad N 1  and the pad N 2 . As shown in  FIG.  9   , the package ESD blocking component  140  can be implemented by using a resistor R 1 , an inductor L 5  or a capacitor C 3 , wherein a first node of the resistor R 1 , the inductor L 5  or the capacitor C 3  is coupled to the pad N 1 , and a second node of the resistor R 1 , the inductor L 5  or the capacitor C 3  is coupled to the pad N 2 . 
       FIG.  10    is a diagram showing some embodiments of the package ESD blocking component  140  coupled between the pad N 1  and the pad N 2 . As shown in  FIG.  9   , the package ESD blocking component  140  can be implemented by using via hole, wherein the via hole is manufactured by a plurality of metal layers. The package ESD blocking component  140  can be implemented by using an inductor L 6  and a capacitor C 4  connected in series, wherein a first node of the inductor L 6  is coupled to the pad N 1 , a second node of the inductor L 6  is coupled to a first node of the capacitor C 4 , and a second node of the capacitor C 4  is coupled to the pad N 2 . The package ESD blocking component  140  can be implemented by using an inductor L 7  and a capacitor C 5  connected in parallel, wherein a first node of the inductor L 7  is coupled to the pad N 1 , a second node of the inductor L 7  is coupled to the pad N 2 , a first node of the capacitor C 5  is coupled to the pad N 1 , and a second node of the capacitor C 5  is coupled to the pad N 2 . 
     In one embodiment, when the die  110  comprises a circuit for processing a signal, the package ESD conducting component  130  can be implemented by using the inductor L 1  shown in  FIG.  2    to bypass the ESD current. As shown in  FIG.  11   , the ESD frequency is within a lower frequency range, a frequency of required signal is within a higher frequency range, the inductor L 1  serves as a high-pass filter to bypass the ESD current to the ground, and the high-frequency component can enter the pad N 2  of the die  110 . In addition, the die ESD component  116  within the die  110  can also be implemented by using an inductor L 8 , to bypass the remaining ESD current to the ground. 
     In one embodiment, the die comprises an RF circuit for processing a millimeter wave (mmW) signal, the ESD frequency may be ranging from 100 MHz to 6 GHz, and a frequency of the required millimeter wave signal is ranging from 24 GHz to 40 GHz. 
     In the embodiment shown in  FIG.  11   , the inductor L 1  can have different designs for different frequencies. Taking  FIG.  12    as an example, not a limitation of the present invention, when the pad N 1  is used to receive or transmit the millimeter wave signal with 28 GHz, the inductor L 1  can be formed by using a sixth metal layer having the ground voltage around a BGA ball; and when the pad N 1  is used to receive or transmit the millimeter wave signal with 39 GHz, the inductor L 1  can be formed by using a fifth metal layer in keep-out zone. 
       FIG.  13    is a diagram illustrating a vertical cross-sectional view of the circuit connected to the BGA ball. As shown in  FIG.  1   , the circuits comprise a first component  1302  and a second component  1304 , wherein the first component  1302  can be the package ESD conducting component formed by using the fifth metal layer L 5  and the sixth metal layer  6 , and the second component  1304  can be the package ESD blocking component formed by using a first metal layer to a fourth metal layer L 1 -L 4 . 
     Briefly summarized, in the embodiments of the present invention, by designing one or more package-level ESD component(s) between the die and the pad(s) of the package, most of the ESD current can be bypassed outside the die, and the remaining ESD current flowing into the die will only induce small voltage drop. In addition, because the package ESD components with lower parasitic effects have better quality factor control and ESD robustness, the package with the package ESD components will have better performance. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.