Patent Publication Number: US-10317861-B2

Title: Switch drive circuit capable of saving timers of fan processor

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a fan motor control circuit, and more particularly to a switch drive circuit capable of saving timers of fan processor and saving cost. 
     2. Description of the Related Art 
     Along with the advance of sciences and technologies and the development of computer industries, lightweight and miniaturized electronic products such as laptops have become the mainstream products in the market. In the lightweight, thin and miniaturized electronic products, the heat dissipation ability often affects the stability of the system, the performance of the products and even the lifetime of the products. With respect to a computer system, in order to quickly dissipate the heat generated by the computer system, the computer system is generally equipped with a cooling fan as a heat dissipation device for keeping the computer system normally operating in a proper temperature environment. 
     In general, the cooling fan used in a computer system is driven by a brushless DC motor. Please refer to  FIG. 1 . A conventional DC fan motor drive circuit includes a micro control unit (MCU)  5 , two PMOS transistors  61 ,  62  of upper arms and two NMOS transistors  63 ,  64  of lower arms. The micro control unit  5  has multiple pins and multiple timers  50 . The first and second pins  51 ,  52  of the micro control unit  5  are respectively electrically connected with the two PMOS transistors  61 ,  62  of upper arms. The first and second pins  51 ,  52  respectively transmit a first pulse width modulation (PWM) signal and a second pulse width modulation (PWM) signal. The first and second pulse width modulation (PWM) signals are identical to each other. The third and fourth pins  53 ,  54  of the micro control unit  5  are respectively electrically connected with the two NMOS transistors  63 ,  64  of lower arms corresponding to the timers  50 . The third and fourth pins  53 ,  54  respectively serve to transmit a first high-frequency pulse width modulation (PWM) signal and a second high-frequency pulse width modulation (PWM) signal modulated by the timers  50 . Therefore, the first pulse width modulation signal and the second high-frequency pulse width modulation signal and the second pulse width modulation signal and the first high-frequency pulse width modulation signal are utilized to drive four full-bridge switches, (that is, the two PMOS transistors  61 ,  62  of upper arms and the two NMOS transistors  63 ,  64  of lower arm) so as to control the rotational speed and operation of the DC fan motor. The junctions between the two PMOS transistors  61 ,  62  of upper arms and the two corresponding NMOS transistors  63 ,  64  of lower arms are respectively connected with a first end  71  and a second end  72  of the corresponding motor winding. 
     The value of the rotational speed regulated by the fan depends on the value of the duty cycle of the internal cutting pulse of the first and second high-frequency pulse width modulation signal output. The frequency of the internal cutting pulse is generally higher than 20 KHz. Therefore, the first and second high-frequency pulse width modulation signals must have a high output precision. Accordingly, the output precision of the first high-frequency pulse width modulation signal necessitates the timer  50  of the micro control unit  5  corresponding to the third pin  53  to modulate and the output precision of the second high-frequency pulse width modulation signal necessitates another timer  50  of the micro control unit  5  corresponding to the fourth pin  54  to modulate. In other words, the two NMOS transistors  63 ,  64  of lower arms of the motor drive circuit of one single conventional fan must use the two pins  53 ,  54  supported by the timers  50  to output the first and second pulse width modulation signals at high precision. 
     However, in the conventional micro control unit  5 , the number of the pins with corresponding timers  50  is limited. For example, as shown in  FIG. 1 , the number of the timers  50  in the micro control unit  5  is only sufficient to support two pins, (that is, the third and fourth pins  53 ,  54 ). The two pins  53 ,  54  have been used to connect with the two NMOS transistors  63 ,  64  of lower arms of the motor drive circuit so that the micro control unit  5  has no extra timers  51  for supporting the corresponding pins. In this case, it is necessary to selectively employ a micro control unit  5  with more timers  50  to support the corresponding pins. As a result, the cost will be greatly increased and the size of the package of the main body will be enlarged. This is unbeneficial to the optimization of the design of the fan. For example, in case a client requires a specific function of the fan, (such as virtual rotational speed), the design of the fan will often encounter the situation that the number of the timers  50  of the micro control unit  5  is not enough. 
     It is therefore tried by the applicant to provide a switch drive circuit capable of saving timers of fan processor and saving cost to solve the above problems existing in the conventional device. 
     SUMMARY OF THE INVENTION 
     It is therefore a primary object of the present invention to provide a switch drive circuit, which is capable of saving timers of fan processor and saving cost. 
     It is a further object of the present invention to provide the above switch drive circuit, which is capable of saving the use of the timers in the fan processor and is beneficial to the design of the fan. 
     To achieve the above and other objects, the switch drive circuit capable of saving timers of fan processor of the present invention is applied to a fan processor. The switch drive circuit includes multiple upper arm switch components, multiple lower arm switch components, a first drive control unit and a second drive control unit. The upper arm switch components are driven by a first pulse width modulation signal and a second pulse width modulation signal. The lower arm switch components are correspondingly electrically connected with the upper arm switch components. The first drive control unit is correspondingly electrically with one of the lower arm switch components. The first drive control unit serves to receive a third pulse width modulation signal and a high-frequency pulse width modulation signal. The second drive control unit is correspondingly electrically with another of the lower arm switch components. The second drive control unit serves to receive the third pulse width modulation signal and the high-frequency pulse width modulation signal. When the first pulse width modulation signal is in a high-level state to trigger and turn on one of the upper arm switch components, the second drive control unit receives the third pulse width modulation signal, which is in a low-level state, whereby the second drive control unit will output the high-frequency pulse width modulation signal to trigger and turn on another of the lower arm switch component. When the second pulse width modulation signal is in the high-level state to trigger and turn on another of the upper arm switch component, the first drive control unit receives the third pulse width modulation signal, which is in the high-level state, whereby the first drive control unit will output the high-frequency pulse width modulation signal to trigger and turn on one of the lower arm switch component of the lower arm switch components. By means of the design of the switch drive circuit of the present invention, the use of the timers in the fan processor is effectively saved to save cost. Moreover, the switch drive circuit of the present invention benefits the design of the fan. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The structure and the technical means adopted by the present invention to achieve the above and other objects can be best understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings, wherein: 
         FIG. 1  is a block diagram of a conventional DC fan motor drive circuit; 
         FIG. 2  is a block diagram of a first embodiment of the present invention; 
         FIG. 3  is another block diagram of the first embodiment of the present invention; 
         FIG. 4  is a circuit diagram of the first embodiment of the present invention; 
         FIG. 5  is another block diagram of the first embodiment of the present invention; 
         FIG. 6  is a block diagram of a second embodiment of the present invention; 
         FIG. 7  is another block diagram of the second embodiment of the present invention; 
         FIG. 8A  is a perspective exploded view of the second embodiment of the present invention; 
         FIG. 8B  is a perspective exploded view of the second embodiment of the present invention; and 
         FIG. 9  is another block diagram of the second embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Please refer to  FIGS. 2 and 3 .  FIG. 2  is a block diagram of a first embodiment of the present invention.  FIG. 3  is another block diagram of the first embodiment of the present invention. The switch drive circuit  1  electrically connected with a fan processor of the present invention is applied to a fan processor  2  of a fan  31 . In this embodiment, the fan processor  2  is, but not limited to, a micro control unit (MCU) for illustration purposes. The switch drive circuit  1  includes multiple upper arm switch components, multiple lower arm switch components, a first drive control unit  14  and a second drive control unit  15 . The upper arm switch components are driven by a first pulse width modulation (PWM) signal and a second pulse width modulation (PWM) signal. 
     The multiple upper arm switch components have a first upper arm switch component  111  and a second upper arm switch component  112 . Each of the first and second upper arm switch components  111 ,  112  has a first end  1111 ,  1121 , a second end  1112 ,  1122  and a third end  1113 ,  1123 . The first end  1111  of the first upper arm switch component  111  is electrically connected with the first end  1121  of the second upper arm switch component  112  and an input voltage Vin. The second end  1112  of the first upper arm switch component  111  receives the first pulse width modulation signal. The second end  1122  of the second upper arm switch component  112  receives the second pulse width modulation signal. The third ends  1113 ,  1123  of the first and second upper arm switch components  111 ,  112  are respectively electrically connected with two ends  311 ,  312  of the motor winding of the fan  31 . 
     The lower arm switch components are correspondingly electrically connected with the upper arm switch components. The lower arm switch components have a first lower arm switch component  131  and a second lower arm switch component  132 . Each of the first and second lower arm switch components  131 ,  132  has a first end  1311 ,  1321 , a second end  1312 ,  1322  and a third end  1313 ,  1323 . The first ends  1311 ,  1321  of the first and second lower arm switch components  131 ,  132  are respectively electrically connected (or coupled) with the corresponding third end  1113  of the first upper arm switch component  111  and the third end  1123  of the second upper arm switch component  112 . The second end  1312  of the first lower arm switch component  131  is electrically connected with the first drive control unit  14 . The third end  1313  of the first lower arm switch component  131  is correspondingly electrically connected with the third end  1323  of the second lower arm switch component  132 . The second end  1322  of the second lower arm switch component  132  is correspondingly electrically connected with the second drive control unit  15 . 
     The first drive control unit  14  is correspondingly electrically connected with one of the lower arm switch components, (that is, the first lower arm switch component  131 ). The first drive control unit  14  receives a third pulse width modulation (PWM) signal and a high-frequency pulse width modulation (PWM) signal. The high-frequency pulse width modulation signal is modulated and generated by one of multiple timers  20  in the fan processor  2 . In other words, the output precision of the high-frequency pulse width modulation signal is modulated by one timer  20  in the fan processor  2  to make the frequency and duty cycle of the high-frequency pulse width modulation signal precise. The value of the rotational speed regulated by the fan  31  depends on the value of the duty cycle of the internal cutting pulse of the high-frequency pulse width modulation signal output. Moreover, the first and second pulse width modulation signals are identical to the third pulse width modulation signal, that is, the first, second and third pulse width modulation signals have identical frequency. Also, the frequency of the first, second and third pulse width modulation signals is identical to the frequency of a Hall signal output from a Hall element  314  connected with the fan processor  2 . The high-frequency pulse width modulation signal is different from the first, second and third pulse width modulation signals, that is, the frequency of the high-frequency pulse width modulation signal is different from the frequency of the first, second and third pulse width modulation signals. 
     Please further refer to  FIG. 3 . The second drive control unit  15  is correspondingly electrically connected with another of the of the lower arm switch components, (that is, the second lower arm switch component  132 ). The second drive control unit  15  receives the third pulse width modulation (PWM) signal and the high-frequency pulse width modulation (PWM) signal. Therefore, when the first pulse width modulation signal is in a high-level state, one of the upper arm switch components, (that is, the first upper arm switch component  111 ) is triggered and turned on. When the second drive control unit  15  receives the third pulse width modulation signal, which is in a low-level state, the second drive control unit  15  will output the high-frequency pulse width modulation signal to trigger another of the of the lower arm switch components, (that is, the second lower arm switch component  132 ) and turn on the same. At this time, the second upper arm switch component  112  and the first lower arm switch component  131  are in a cutoff state, (that is, not turn on). In the case that the first pulse width modulation signal is switched from the high-level state to the low-level state to make the first upper arm switch component  111  in a cutoff state, the second pulse width modulation signal is in the high-level state to trigger another of the upper arm switch components, (that is, the second upper arm switch component  112 ) and turn on the same. When the first drive control unit  14  receives the third pulse width modulation signal, which is in the high-level state, the first drive control unit  14  will output the high-frequency pulse width modulation signal to trigger one of the lower arm switch components, (that is, the first lower arm switch component  131 ) and turn on the same. At this time, the second lower arm switch component  132  is in a cutoff state, (that is, not turn on). By means of the above method, the motor of the fan  31  is turned on to operate and the rotational speed of the motor of the fan  31  is controlled. 
     In this embodiment, the fan processor  2  is, but not limited to, a 16-pin processor for illustration purposes. Alternatively, any other processor such as a 10-pin processor, a 12-pin processor or a 24-pin processor is also applicable to the present invention. The fan processor  2  has multiple pins and multiple timers  20 , wherein a first pin  21  is coupled with the second end  1112  of the first upper arm switch component  111 . The first pin  21  serves to output the first pulse width modulation signal. A second pin  22  is coupled with the second end  1122  of the second upper arm switch component  112 . The second pin  22  serves to output the second pulse width modulation signal. A third pin  23  is coupled with the first and second drive control units  14 ,  15 . The third pin  22  serves to output the third pulse width modulation signal. A fourth pin  24  is coupled with the first and second drive control units  14 ,  15 . The fourth pin  24  serves to output the high-frequency pulse width modulation signal modulated by the corresponding timer  20  of the multiple timers  20 . A fifth pin  25  is coupled with the Hall element  314 . The fifth pin  25  serves to receive the Hall signal generated by the Hall element  314  when sensing the position of the rotor of the fan  31 . A sixth pin  26  corresponds to another timer  20 . The sixth pin  26  is not coupled with (or electrically connected with) any of the upper and lower arm switch components  11 ,  13  and the first and second drive control units  14 ,  15 . The sixth pin  26  serves to output another high-frequency pulse width modulation signal modulated by the other timer  20  of the multiple timers  20 . A thirteenth pin  213  of the fan processor  2  serves to receive a stable working voltage Vcc (such as 5 volts) provided by the input voltage Vin. 
     In this embodiment, the number of the timers  20  of the fan processor  2  of the fan  31  is, but not limited to, such that the two pins, (that is, the fourth and the sixth pins  24 ,  26 ) are supported, while the rest of the pins, (that is, the first to the third pins  21 ˜ 23 , the fifth pin  25  and the seventh to the sixteenth pins  27 ˜ 216 ) are not supported for illustration. Accordingly, the fan  31  of the present invention only needs to utilize the fourth pin  24  corresponding to one timer  20  in the fan processor  2  to output the high-frequency pulse width modulation signal to drive the first lower arm switch component  131  or the second lower arm switch component  132 . The sixth pin  26  of the fan processor  2  can be provided for multiple lower arm switch components of an identical switch drive circuit  1  of another fan to use. Alternatively, the sixth pin  26  can be provided for a requirement of specific function of the fan  31 , (which specific function necessitates a timer  20  to achieve), such as virtual rotational speed. Therefore, by means of the design of the switch drive circuit  1  of the present invention, the speed adjustment function of the fan  31  only needs to utilize the resource of one timer  20  in the fan processor  2  to achieve normal regulation of the rotational speed. In this case, the use of the timers  20  of the fan processor  2  can be effectively saved to save cost and optimize the design of the fan  31 . 
     Please refer to  FIG. 4  as well as  FIG. 3 . The structure of the present invention will be described in detail hereinafter. 
     The first drive control unit  14  includes a first transistor Q 1 , a first drive resistor R 1 ′ and a second drive resistor R 2 ′. In this embodiment, the first transistor Q 1  is, but not limited to, a bipolar junction transistor (BJT) for illustration purposes. The first transistor Q 1  has a base, an emitter and a collector. One end of the first drive resistor R 1 ′ is coupled with the collector of the first transistor Q 1  and the fourth pin  24  of the fan processor  2 . The collector of the first transistor Q 1  serves to receive the high-frequency pulse width modulation signal. The other end of the first drive resistor R 1 ′ is coupled with a grounding end GND. One end of the second drive resistor R 2 ′ is coupled with the base, while the other end of the second drive resistor R 2 ′ is coupled with the third pin  23  of the fan processor  2 . The other end of the second drive resistor R 2 ′ serves to receive the third pulse width modulation signal. The emitter of the first transistor Q 1  is coupled with the second end of the first lower arm switch component. 
     The second drive control unit  15  includes a second transistor Q 2 , a third transistor Q 3 , a third drive resistor R 3 ′, a fourth drive resistor R 4 ′ and a fifth drive resistor R 5 ′. In this embodiment, the second and third transistors are, but not limited to, bipolar junction transistors (BJT) for illustration purposes. Each of the second and third transistors has a base, an emitter and a collector. The base of the second transistor Q 2  is coupled with the collector of the third transistor Q 3  and one end of the third drive resistor R 3 ′. The collector of the second transistor Q 2  is coupled with one end of the fourth drive resistor R 4 ′ and the fourth pin  24  of the fan processor  2 . The collector of the second transistor Q 2  serves to receive the high-frequency pulse width modulation signal. The other end of the fourth drive resistor R 4 ′ and the emitter of the third transistor Q 3  are coupled with the grounding end GND. The emitter of the second transistor Q 2  is coupled with the second end of the second lower arm switch component. The other end of the third drive resistor R 3 ′ is coupled with an operation voltage Vc (such as five volts). The base of the third transistor Q 3  is coupled with one end of the fifth drive resistor R 5 ′. The other end of the fifth drive resistor R 5 ′ is coupled with the third pin  23  of the fan processor  2 . The other end of the fifth drive resistor R 5 ′ serves to receive the third pulse width modulation signal. 
     The first upper arm switch component  111  has a first MOS transistor M 1 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a fourth transistor Q 4  and a first capacitor C 1 . In this embodiment, the first MOS transistor M 1  is, but not limited to, a PMOS transistor for illustration purposes. The first MOS transistor M 1  has a gate, a source and a drain. The gate of the first MOS transistor M 1  is coupled with one end of the first capacitor C 1 , one end of the first resistor R 1  and one end of the second resistor R 2 . The drain of the first MOS transistor M 1 , (that is, the first end  1111  of the first upper arm switch component  111 ) is coupled with the other end of the first capacitor C 1 , the other end of the first resistor R 1  and the input voltage Vin. The source of the first MOS transistor M 1 , (that is, the third end  1113  of the first upper arm switch component  111 ) is coupled with one end  311  of the motor winding of the fan  31 . In this embodiment, the fourth transistor Q 4  is, but not limited to, a bipolar junction transistor (BJT) for illustration purposes. The fourth transistor Q 4  has a base, an emitter and a collector. The collector of the fourth transistor Q 4  is coupled with the other end of the second resistor R 2 . The emitter of the fourth transistor Q 4  is coupled with the grounding end GND. The base of the fourth transistor Q 4  is coupled with one end of the third resistor R 3 . The other end of the third resistor R 3 , (that is, the second end of the first upper arm switch component  111 ) is coupled with the first pin  21  of the fan processor  2 . The other end of the third resistor R 3  serves to receive the first pulse width modulation signal. 
     As shown in  FIG. 4 , the second upper arm switch component  112  has a second MOS transistor M 2 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a fifth transistor Q 5  and a second capacitor C 2 . In this embodiment, the second MOS transistor M 2  is, but not limited to, a PMOS transistor for illustration purposes. The second MOS transistor M 2  has a gate, a source and a drain. The gate of the second MOS transistor M 2  is coupled with one end of the second capacitor C 2 , one end of the fourth resistor R 4  and one end of the fifth resistor R 5 . The drain of the second MOS transistor M 2 , (that is, the first end  1121  of the second upper arm switch component  112 ) is coupled with the other end of the second capacitor C 2 , the other end of the fourth resistor R 4  and the input voltage Vin. The source of the second MOS transistor M 2 , (that is, the third end  1123  of the second upper arm switch component  112 ) is coupled with the other end  312  of the motor winding of the fan  31 . In this embodiment, the fifth transistor Q 5  is, but not limited to, a bipolar junction transistor (BJT) for illustration purposes. The fifth transistor Q 5  has a base, an emitter and a collector. The collector of the fifth transistor Q 5  is coupled with the other end of the fifth resistor R 5 . The emitter of the fifth transistor Q 5  is coupled with the grounding end GND. The base of the fifth transistor Q 5  is coupled with one end of the sixth resistor R 6 . The other end of the sixth resistor R 6 , (that is, the second end  1122  of the second upper arm switch component  112 ) is coupled with the second pin  22  of the fan processor  2 . The other end of the sixth resistor R 6  serves to receive the second pulse width modulation signal. 
     The first lower arm switch component  131  has a third MOS transistor M 3 , a seventh resistor R 7 , an eighth resistor R 8  and a third capacitor C 3 . In this embodiment, the third MOS transistor M 3  is, but not limited to, an NMOS transistor for illustration purposes. The third MOS transistor M 3  has a gate, a source and a drain. The drain of the third MOS transistor M 3 , (that is, the first end  1311  of the first lower arm switch component  131 ) is coupled with one end  311  of the motor winding and the source of the first MOS transistor M 1 . The gate of the third MOS transistor M 3  is coupled with one end of the third capacitor C 3 , one end of the seventh resistor R 7  and one end of the eighth resistor R 8 . The other end of the eighth resistor R 8  is coupled with the other end of the third capacitor C 3  and the grounding end GND. The other end of the seventh resistor R 7 , (that is, the second end of the first lower arm switch component  131 ) is coupled with the emitter of the first transistor Q 1  of the first drive control unit  14 . The source of the third MOS transistor M 3 , (that is, the third end of the first lower arm switch component  131 ) is coupled with one end of a ninth resistor R 9 . The other end of the ninth resistor R 9  is coupled with the grounding end GND. 
     The second lower arm switch component  132  has a fourth MOS transistor M 4 , a tenth resistor R 10 , an eleventh resistor R 11  and a fourth capacitor C 4 . In this embodiment, the fourth MOS transistor M 4  is, but not limited to, an NMOS transistor for illustration purposes. The fourth MOS transistor M 4  has a gate, a source and a drain. The drain of the fourth MOS transistor M 4 , (that is, the first end  1321  of the second lower arm switch component  132 ) is coupled with the other end  312  of the motor winding and the source of the second MOS transistor M 2 . The gate of the fourth MOS transistor M 4  is coupled with one end of the fourth capacitor C 4 , one end of the tenth resistor R 10  and one end of the eleventh resistor R 11 . The other end of the tenth resistor R 10  is coupled with the other end of the fourth capacitor C 4  and the grounding end GND. The other end of the eleventh resistor R 11 , (that is, the second end of the second lower arm switch component  132 ) is coupled with the emitter of the second transistor Q 2  of the second drive control unit  15 . The source of the fourth MOS transistor M 4 , (that is, the third end of the second lower arm switch component  132 ) is coupled with one end of the ninth resistor R 9  and the source of the third MOS transistor M 3 . 
     In addition, in practice, a first current-limiting amplifier  41  can be arranged between the third ends  1313 ,  1323  of the first and second lower arm switch components  131 ,  132  and the fan processor  2  (as shown in  FIG. 5 ). That is, one end of the first current-limiting amplifier  41  is electrically connected with the third ends  1313 ,  1323  of the first and second lower arm switch components  131 ,  132 , while the other end of the first current-limiting amplifier  41  is electrically connected with a seventh pin  27  of the fan processor  2 . 
     Therefore, by means of the design of the switch drive circuit  1  of the present invention, the use of the timers  20  in the fan processor  2  can be effectively saved to save cost and benefit the design of the fan  31 . 
     Please now refer to  FIGS. 6 and 7 .  FIG. 6  is a block diagram of a second embodiment of the present invention.  FIG. 7  is another block diagram of the second embodiment of the present invention. Also, please refer to  FIGS. 8A and 8B .  FIG. 8A  is a perspective exploded view of the second embodiment of the present invention.  FIG. 8B  is a perspective exploded view of the second embodiment of the present invention. In this embodiment, the switch drive circuit  1  of the first embodiment is applied to two fans  31 ,  32  (such as a series fan). The two fans  31 ,  32  commonly use the same processor  2 . The switch drive circuits  1 ,  1 ′ of the two fans  31 ,  32  and the fan processor  2  are together disposed on a circuit board  33 , which is disposed on the bottom sections of the two fans  31 ,  32  for illustration purposes. That is, each of the two fans  31 ,  32  has a switch drive circuit  1  of the first embodiment. The switch drive circuits  1 ,  1 ′ of the two fans  31 ,  32  are identical to the switch drive circuit  1  of the first embodiment in structure and connection relationship and effect and thus will not be repeatedly described hereinafter. The switch drive circuit  1  of the fan  31  is connected to the corresponding processor  2  and is identical to the switch drive circuit  1  of the first embodiment in structure and connection relationship and effect and thus will not be repeatedly described hereinafter. The switch drive circuit  1 ′ of the other fan  32  has a third upper arm switch component  113 , a fourth upper arm switch component  114 , a third lower arm switch component  133 , a fourth lower arm switch component  134 , a third drive control unit  16  and a fourth drive control unit  17 . Each of the third and fourth upper arm switch components  113 ,  114  has a first end  1131 ,  1141 , a second end  1132 ,  1142  and a third end  1133 ,  1143 . The first end  1131  of the third upper arm switch components  113  is electrically connected with the first end  1141  of the fourth upper arm switch component  114  and the input voltage Vin. The second end  1132  of the third upper arm switch component  113  is coupled with the ninth pin  29  of the fan processor  2 . The ninth pin  29  serves to output the fourth pulse width modulation (PWM) signal to the second end  1132  of the third upper arm switch component  113 . 
     The second end of the fourth upper arm switch component  114  is coupled with a tenth pin  210  of the fan processor  2 . The tenth pin  210  serves to output the fifth pulse width modulation (PWM) signal to the second end of the fourth upper arm switch component  114 . The third ends  113 ,  1143  of the third and fourth upper arm switch components are respectively electrically connected with one end  321  and the other end  322  of the motor winding of the other fan  32 . Each of the third and fourth lower arm switch components has a first end  1331 ,  1341 , a second end  1332 ,  1342  and a third end  1333 ,  1343 . The first ends  1331 ,  1341  of the third and fourth lower arm switch components are respectively electrically connected with (or coupled with) the third end  1131  of the third upper arm switch component  113  and third end  1143  of the fourth upper arm switch component  114 . The second end  1332  of the third lower arm switch component  133  is electrically connected with the third drive control unit  16 . The third end  1333  of the third lower arm switch component  133  is electrically connected with the third end  1343  of the fourth lower arm switch component  134 . 
     The second end  1342  of the fourth lower arm switch component  134  is electrically connected with the fourth drive control unit  17 . The third and fourth upper arm switch components  113 ,  114  of the second embodiment are identical to the first and second upper arm switch components  111 ,  112  of the first embodiment in structure, connection relationship and effect. The third and fourth lower arm switch components  133 ,  134  of the second embodiment are identical to the first and second lower arm switch components  131 ,  132  of the first embodiment in structure, connection relationship and effect and thus will not be repeatedly described hereinafter. 
     In this embodiment, the fan processor  2  and the multiple timers  20  in the fan processor  2  only support two pins, (that is, the fourth and the sixth pins  24 ,  26 ) as the fan processor  2  of the first embodiment and thus will not be repeatedly described hereinafter. The sixth pin  26  of the fan processor  2  is electrically connected with the third and fourth drive control units  16 ,  17  of the switch drive circuit  1 ′ of the other fan  32 . The sixth pin  26  serves to output another high-frequency pulse width modulation (PWM) signal modulated by another corresponding timer  20  and transmit the signal to the third and fourth drive control units. An eighth pin  28  of the fan processor  2  is coupled with the third and fourth drive control units. The eighth pin  28  serves to output the sixth pulse width modulation (PWM) signal and transmit the signal to the third and fourth drive control units. In this embodiment, the third and fourth drive control units  16 ,  17  are identical to the first and second drive control units  14 ,  15  of the first embodiment in structure, connection relationship, execution and effect and thus will not be repeatedly described hereinafter. 
     An eleventh pin  211  of the fan processor  2  is coupled with the other Hall element  324 . The eleventh pin  211  serves to receive the Hall signal generated by the other Hall element  324  when sensing the position of the rotor of the other fan  32 . In addition, in practice, as shown in  FIG. 9 , a first current-limiting amplifier  41  can be arranged between the third ends  1313 ,  1323  of the first and second lower arm switch components  131 ,  132  and the fan processor  2  and a second first current-limiting amplifier  42  can be arranged between the third ends  1333 ,  1343  of the third and fourth lower arm switch components  133 ,  134  and the fan processor  2 . That is, one end of the second current-limiting amplifier  42  is electrically connected with the third ends  1333 ,  1343  of the third and fourth lower arm switch components  133 ,  134 , while the other end of the second current-limiting amplifier  42  is electrically connected with a twelfth pin  212  of the fan processor  2 . The fourth and fifth pulse width modulation signals are identical to the sixth pulse width modulation signal. That is, the frequencies of the fourth, fifth and the sixth pulse width modulation signals are identical to each other and are identical to the frequency of the Hall signal of the other Hall element  324 . The other high-frequency pulse width modulation signal is different from the fourth, fifth and sixth pulse width modulation signals. That is, the frequency of the other high-frequency pulse width modulation signal is different from the frequencies of the fourth, fifth and sixth pulse width modulation signals. 
     Therefore, when the first pulse width modulation signal is in a high-level state to trigger and turn on the first upper arm switch component  111 , the second drive control unit  15  receives the third pulse width modulation signal, which is in a low-level state. At this time, the second drive control unit  15  will receive the high-frequency pulse width modulation signal output to trigger and turn on the second lower arm switch component  132 . At the same time, the second upper arm switch component  112  and the first lower arm switch component  131  are in a cutoff state, (that is, not turn on). Also, when the fourth pulse width modulation signal is in the high-level state to trigger and turn on the third upper arm switch component  113 , the fourth drive control unit  17  receives the sixth pulse width modulation signal, which is in the low-level state. At this time, the fourth drive control unit  17  will receive the other high-frequency pulse width modulation signal output to trigger and turn on the fourth lower arm switch component  134 . At the same time, the fourth upper arm switch component  114  and the third lower arm switch component  133  are in a cutoff state, (that is, not turn on). 
     In the case that the first pulse width modulation signal is switched from the high-level state to the low-level state to make the first upper arm switch component  111  in a cutoff state, the second pulse width modulation signal is in the high-level state to trigger and turn on the second upper arm switch component  112 . When the first drive control unit  14  receives the third pulse width modulation signal, which is in the high-level state, the first drive control unit  14  will receive the high-frequency pulse width modulation signal output to trigger and turn on the first lower arm switch component  131 . At this time, the second lower arm switch component  132  is in a cutoff state, (that is, not turn on). Also, in the case that the fourth pulse width modulation signal is switched from the high-level state to the low-level state to make the third upper arm switch component  113  in a cutoff state, the fifth pulse width modulation signal is in the high-level state to trigger and turn on the fourth upper arm switch component  114 . When the third drive control unit  16  receives the sixth pulse width modulation signal, which is in the high-level state, the third drive control unit  16  will receive the other high-frequency pulse width modulation signal output to trigger and turn on the third lower arm switch component  133 . At this time, the fourth lower arm switch component  134  is in a cutoff state, (that is, not turn on). Accordingly, the motors of the two fans  31 ,  32  can be simultaneously turned on to operate and the rotational speed of the motors of the two fans  31 ,  32  can be controlled at the same time (or synchronously). In other words, the two fans  31 ,  32  are respectively equipped with the switch drive circuits  1 ,  1 ′ of the present invention, whereby one single processor  2  can be control the operation of the motors of the two fans  31 ,  32  at the same time and the fourth and sixth pins  24 ,  26  of the fan processor  2  can control the rotational speed of the motors of the two fans  31 ,  32  at the same time. 
     Therefore, by means of the design of the switch drive circuits  1 ,  1 ′ of the present invention, which are applied to the two fans  31 ,  32 , the material of the circuit is partially saved, (for example, the fan processor and the other circuit board of the other fan  32  are saved). In addition, the use of the timers  20  in the fan processor  2  is also saved to save the cost and benefit the design of the fan. 
     The present invention has been described with the above embodiments thereof and it is understood that many changes and modifications in the above embodiments can be carried out without departing from the scope and the spirit of the invention that is intended to be limited only by the appended claims.