Patent Publication Number: US-10784216-B2

Title: Semiconductor device and semiconductor package including the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation application of U.S. patent application Ser. No. 15/295,104, filed on Oct. 17, 2016, which claims under 35 U.S.C. 119 priority to and the benefit of Korean Patent Application No. 10-2015-0157439 filed on Nov. 10, 2015 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein. 
    
    
     BACKGROUND 
     1. Technical Field 
     Inventive concepts relate to a semiconductor device and a semiconductor package including the same. More particularly, inventive concepts relate to a semiconductor device include a redistribution layer and a semiconductor package including the same. 
     2. Description of the Related Art 
     A semiconductor package may include a semiconductor device that is capable of storing a huge amount of data and processing that data in a short time. Such a device may include a circuit unit for storing and/or processing data and chip pads for inputting data to the circuit from “the outside” (that is, outside the circuit unit) or outputting data from the circuit unit to the outside. 
     Some semiconductor devices include one or more redistribution layers connected to the chip pads, in order to change the positions of pads disposed at a specified position of the semiconductor device (that is, to alter the location through which the pads connect to the outside). 
     For example, when the pads are disposed in a region of a top surface of the semiconductor device, the electrical connection points, the points where the circuit unit makes connection through pads with wires or bumps, may be changed to other regions of the top surface of the semiconductor device through a redistribution layer electrically connected to the chip pads. Such redistribution may be employed, for example, to ease crowding in one area of a circuit or, generally, for convenient placement of pads. 
     When a defect, such as short-circuit, occurs in a redistribution layer that electrically connects the outside and the semiconductor device, the defect may also occur in the semiconductor device and even in the semiconductor package including the same. 
     Therefore, for the reliability of electrical connections between the semiconductor device, or circuit unit, and the outside, the reliability of the redistribution layer is critical. 
     SUMMARY 
     Aspects of inventive concepts provide a semiconductor device with improved reliability and a semiconductor package including the same. 
     Aspects of inventive concepts provide a semiconductor device capable of stably maintaining the electrical connection to the outside, and a semiconductor package including the same. 
     Aspects of inventive concepts provide a semiconductor device capable of stably maintaining the electrical connection to the outside even when a defect occurs in the redistribution layer, and a semiconductor package including the same. 
     Aspects of the inventive concepts provide a semiconductor device, the semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane. 
     In some example embodiments, the first redistribution center pad region and the first chip center pad region are connected to each other to have a profile continuous with each other. 
     In some example embodiments, a top surface of the first redistribution center pad region and a bottom surface of the first chip center pad region are in a rectangular form that shares a first side each other. 
     In some example embodiments, the semiconductor device further comprises an insulating film disposed between the first redistribution center pad region and the semiconductor chip body, wherein the top surface of the first chip pad is exposed through the insulating film. 
     In some example embodiments, the first chip center pad region comprises a first center region, and a first peripheral region that connects the first center region with the first redistribution center pad region, and the top surface of the first center region and the top surface of the first redistribution center pad region are not disposed on the same plane. 
     In some example embodiments, the top surface of the first redistribution center pad region has an area wider than the top surface of the first center region. 
     In some example embodiments, the semiconductor chip body comprises a central region, a first edge region adjacent to an edge of the semiconductor chip body, and a first redistribution region that connects the central region and the first edge region, the first chip center pad region and the first redistribution center pad region are disposed in the central region, and the first edge pad region is disposed in the first edge region. 
     In some example embodiments, the first redistribution center pad region is disposed between the first chip center pad region and the first edge pad region. 
     In some example embodiments, the first chip center pad region is disposed between the first redistribution center pad region and the first edge pad region. 
     In some example embodiments, the first redistribution layer extends on the semiconductor chip body along a first direction, and the first redistribution center pad region further comprises first and second sub-center pad regions that are disposed along the first direction around the first chip center pad region. 
     Aspects of the inventive concepts provide a semiconductor device, the semiconductor device comprises a semiconductor chip body including a first chip pad, an insulating film that is disposed on the semiconductor chip body to expose a top surface of the first chip pad, a first redistribution layer that extends on a top surface of the first chip pad in a first direction and a passivation layer that is disposed in the first redistribution layer to expose a first chip center pad region of a first redistribution layer overlapping the first chip pad, a first redistribution center pad region of the first redistribution layer connected to the first chip center pad region and disposed on the insulating film, and a first edge pad region of the first redistribution layer adjacent to an edge of the semiconductor chip body, wherein the first chip center pad region comprises a first center region, and a first peripheral region that connects the first center region with the first redistribution center pad region, and a top surface of the first center region and a top surface of the first redistribution center pad region are not disposed on the same plane, and the top surface of the first redistribution center pad region has an area wider than the top surface of the first center region. 
     In some example embodiments, the first redistribution center pad region and the first chip center pad region are connected to each other to have a profile continuous with each other. 
     In some example embodiments, the semiconductor chip body comprises a central region, a first edge region adjacent to an edge of the semiconductor chip body, and a first redistribution region which connects the central region with the first edge region, the first chip center pad region and the first redistribution center pad region are disposed in the central region, and the first edge pad region is disposed in the first edge region. 
     Aspects of the inventive concepts provide a semiconductor package, the semiconductor package comprises a package substrate including a first top pad on a top surface and a semiconductor chip disposed on the package substrate, wherein the semiconductor chip comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body, and a first redistribution layer disposed between the passivation film and the semiconductor chip body, and the first redistribution layer exposes a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region through the passivation film, and a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane. 
     In some example embodiments, the semiconductor package further comprises a wire that electrically connects the first top pad and the first redistribution center pad region. 
     In some example embodiments, the semiconductor package further comprises a first flip pad disposed on the first redistribution center pad region, and a first bump disposed between the first flip pad and the first top pad. 
     In some example embodiments, the first redistribution center pad region and the first chip center pad region are connected to each other to have a profile continuous with each other. 
     In some example embodiments, the semiconductor package further comprises an insulating film disposed between the first redistribution center pad region and the semiconductor chip body, wherein the top surface of the first chip pad is exposed through the insulating film. 
     In some example embodiments, the first chip center pad region comprises a first center region, and a first peripheral region that connects the first center region with the first redistribution center pad region, and the top surface of the first center region and the top surface of the first redistribution center pad region are not disposed on the same plane. 
     In some example embodiments, the top surface of the first redistribution center pad region has an area wider than the top surface of the first center region. 
     In example embodiments a semiconductor device includes a semiconductor chip body including a chip pad on a top surface; an insulation film on the top surface of the semiconductor chip body patterned to leave at least a portion of the chip pad exposed; a redistribution layer on the insulation film that contacts at least a portion of the chip pad exposed through the patterned insulation film to form a chip pad region; and a passivation layer on the redistribution layer patterned to leave at least a portion of the chip pad region exposed and to leave a portion of the redistribution layer adjacent the chip pad region exposed to thereby form an auxiliary pad region. 
     In example embodiments a semiconductor device includes a semiconductor chip body including a chip pad on a top surface; an insulation film on the top surface of the semiconductor chip body patterned to leave at least a portion of the chip pad exposed; a redistribution layer on the insulation film that contacts at least a portion of the chip pad exposed through the patterned insulation film to form a chip pad region; and a passivation layer on the redistribution layer patterned to leave at least a portion of the chip pad region exposed and to leave a portion of the redistribution layer adjacent the chip pad region exposed to thereby form an auxiliary pad region and a wire electrically connected to the auxiliary pad region. 
     In example embodiments a semiconductor device includes a semiconductor chip body including a chip pad on a top surface; an insulation film on the top surface of the semiconductor chip body patterned to leave at least a portion of the chip pad exposed; a redistribution layer on the insulation film that contacts at least a portion of the chip pad exposed through the patterned insulation film to form a chip pad region; and a passivation layer on the redistribution layer patterned to leave at least a portion of the chip pad region exposed and to leave a portion of the redistribution layer adjacent the chip pad region exposed to thereby form an auxiliary pad region and a flip pad disposed on the auxiliary pad region. 
     In example embodiments a semiconductor device includes a semiconductor chip body including a chip pad on a top surface; an insulation film on the top surface of the semiconductor chip body patterned to leave at least a portion of the chip pad exposed; a redistribution layer on the insulation film that contacts at least a portion of the chip pad exposed through the patterned insulation film to form a chip pad region; and a passivation layer on the redistribution layer patterned to leave at least a portion of the chip pad region exposed and to leave a portion of the redistribution layer adjacent the chip pad region exposed to thereby form an auxiliary pad region, wherein the exposed area of the auxiliary pad region is greater than the area of the chip region. 
     In example embodiments a semiconductor device includes a semiconductor chip body including a chip pad on a top surface; an insulation film on the top surface of the semiconductor chip body patterned to leave at least a portion of the chip pad exposed; a redistribution layer on the insulation film that contacts at least a portion of the chip pad exposed through the patterned insulation film to form a chip pad region; and a passivation layer on the redistribution layer patterned to leave at least a portion of the chip pad region exposed and to leave a portion of the redistribution layer adjacent the chip pad region exposed to thereby form an auxiliary pad region, wherein, the chip pad region is within a depression formed by an opening in the insulation layer, and its top and bottom surfaces are at lower levels that the respective top and bottom surfaces of the redistribution layer located atop the insulation layer; and the auxiliary chip pad region is at the same level as the redistribution layer, with its top and bottom surfaces at the same levels as the respective top and bottom surfaces of the redistribution layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects and features of the inventive concepts will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which: 
         FIG. 1  is a perspective view for describing a semiconductor device according to some example embodiments of the inventive concepts. 
         FIG. 2  is a cross-sectional view taken along the line A 1 -A 1  of  FIG. 1 . 
         FIG. 3  is an enlarged perspective view of a region of a dotted line ‘a’ of  FIG. 1 . 
         FIG. 4  is a perspective view for illustrating a semiconductor device according to some example embodiments of the inventive concepts. 
         FIG. 5  is a cross-sectional view taken along the line A 2 -A 2  of  FIG. 4 . 
         FIG. 6  is a perspective view for illustrating a semiconductor device according to some example embodiments of the present invention. 
         FIG. 7  is a cross-sectional view taken along the line A 3 -A 3  of  FIG. 6 . 
         FIG. 8  is a perspective view for illustrating the semiconductor device according to some example embodiments of the present invention. 
         FIG. 9  is a cross-sectional view taken along the line A 4 -A 4  of  FIG. 8 . 
         FIG. 10  is an enlarged perspective view of a dotted region ‘b’ of  FIG. 8 . 
         FIG. 11  is a perspective view for illustrating a semiconductor device according to some example embodiments of the present invention. 
         FIG. 12  is a cross-sectional view taken along the line A 5 -A 5  of  FIG. 11 . 
         FIG. 13  is a perspective view for illustrating a semiconductor device according to some example embodiments of the present invention. 
         FIG. 14  is a cross-sectional view taken along the line A 6 -A 6  of  FIG. 13 . 
         FIG. 15  is a perspective view for illustrating the semiconductor package according to some example embodiments of the present invention. 
         FIG. 16  is a cross-sectional view taken along the line B-B of  FIG. 15 . 
         FIG. 17  is a cross-sectional view for illustrating the semiconductor package according to some example embodiments of the present invention. 
         FIG. 18  is a cross-sectional view for illustrating the semiconductor package according to some example embodiments of the present invention. 
         FIG. 19  is an enlarged cross-sectional view of a dotted region ‘c’ of  FIG. 18 . 
         FIG. 20  is a cross-sectional view for illustrating the semiconductor package according to some example embodiments of the present invention. 
         FIG. 21  is a block diagram of an electronic system including the semiconductor device and the semiconductor package according to some example embodiments of the present invention. 
         FIG. 22  is an exemplary semiconductor system to which the semiconductor device and the semiconductor package according to some example embodiments of the present invention are applicable. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Advantages and features of inventive concepts and methods of accomplishing the same may be understood more readily by reference to the following detailed description of example embodiments and the accompanying drawings. Inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the disclosure to those skilled in the art, and inventive concepts will only be defined by the appended claims. In the drawings, the thickness of layers and regions are exaggerated for clarity. 
     It will be understood that when an element or layer is referred to as being “connected to,” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. 
     It will be understood that, although the terms first, second, and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present inventive concept. 
     The use of the terms “a” and “an” and “the” and similar referents in the context of describing the inventive concept (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. 
     Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It is noted that the use of any and all examples, or exemplary terms provided herein is intended merely to better illuminate the inventive concept and is not a limitation on the scope of the inventive concept unless otherwise specified. Further, unless defined otherwise, all terms defined in generally used dictionaries may not be overly interpreted. 
     Hereinafter, a semiconductor device and a semiconductor package including the same in accordance with principles of inventive concepts will be described by way of several examples. 
     In example embodiments in accordance with principles of inventive concepts a semiconductor package may include an auxiliary pad that may be employed, for example, for bonding, such as wire-bonding or bump bonding, to carry electrical signals to “the outside” (that is, off-chip) or for test probing. 
     In an example embodiment a redistribution layer makes contact with a chip pad on a semiconductor device, or chip, though an opening in an insulation layer. A passivation layer is patterned over the redistribution layer, leaving the portion of the redistribution layer that overlies the chip pad exposed to form a chip pad region and an adjacent auxiliary pad region. Because the chip pad region is within the depression formed by an opening in the insulation layer, its top and bottom surfaces are at lower levels that the respective top and bottom surfaces of the redistribution layer located atop the insulation layer. The auxiliary chip pad region, though, is at the same level as the redistribution layer, with its top and bottom surfaces at the same levels as the respective top and bottom surfaces of the redistribution layer. Additionally, the auxiliary chip pad region may have a larger surface area exposed than its adjacent chip pad. A semiconductor device according to some example embodiments in accordance with principles of inventive concepts will be described referring to  FIGS. 1 to 3 . 
       FIG. 1  is a perspective view for describing an example embodiment of a semiconductor device in accordance with principles of inventive concepts.  FIG. 2  is a cross-sectional view taken along the line A 1 -A 1  of  FIG. 1 .  FIG. 3  is an enlarged perspective view of a region of a dotted line ‘a’ of  FIG. 1 . 
     Referring to  FIGS. 1 to 3 , a semiconductor device  1  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b.    
     The semiconductor chip body  60  may include an integrated circuit element. For example, the integrated circuit element may include a memory element or a logic device (e.g., a processor). The semiconductor chip body  60  may include various internal circuit patterns and internal wirings, and may electrically connect first chip pad  50   a  and the second chip pad  50   b  with the internal circuit patterns through the internal wirings. 
     The semiconductor chip body  60  may house the internal circuit pattern and the internal wirings, using an interlayer insulating film that includes at least one of oxide, nitride and oxynitride. Moreover, a low-dielectric constant material may be used as the interlayer insulating film to reduce a coupling effect between the internal wirings, and the interlayer insulating film may be made of, for example, flowable oxide (FOX), tonen silazen (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilaca glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PRTEOS), fluoride silicate glass (FSG), high density plasma (HDP), plasma enhanced oxide (PEOX), flowable CVD (FCVD) or a combination thereof. 
     In exemplary embodiments in accordance with principles of inventive concepts, the semiconductor chip body  60  may be divided into a first edge region EA 1 , a first redistribution region RA 1 , a central region CA, a second redistribution region RA 2  and a second edge region EA 2 . 
     That is, referring to  FIG. 1 , for example, the semiconductor chip body  60  includes a first edge region EA 1  adjacent to one edge side surface of the semiconductor chip body  60 , and a second edge region EA 2  adjacent to the other edge side surface facing the one edge side surface. First redistribution region RA 1  may be disposed between the central region CA and the first edge region EA 1  of the semiconductor chip body  60 , and second redistribution region RA 2  may be disposed between the central region CA and the second edge region EA 2 . 
     In this example embodiment, when the semiconductor chip body  60  is viewed from the top, as illustrated in  FIG. 1 , although it is illustrated in a rectangular shape, inventive concepts are not limited thereto. 
     Thus, even when the shape of the semiconductor chip body  60  is a circular, elliptical, shape or another type of polygonal shape, as long as the semiconductor chip body  60  includes edges, as described above, the semiconductor chip body  60  may be divided into the first edge region EA 1 , the first redistribution region RA 1 , the central region CA, the second redistribution region RA 2  and the second edge region EA 2 . 
     The first chip pad  50   a  and the second chip pad  50   b  are disposed on the top surface of the semiconductor chip body  60 . 
     The first chip pad  50   a  and the second chip pad  50   b  may be disposed in the central region CA. However, the above-mentioned arrangement is an example for explaining this embodiment and inventive concepts are not limited thereto. Thus, the first chip pad  50   a  and the second chip pad  50   b  may be disposed in any region, such as the first edge region EA 1 , the first redistribution region RA 1 , the second redistribution region RA 2  and the second edge region EA 2 , except the central region CA. 
     Although the first chip pad  50   a  and the second chip pad  50   b  are inserted into the semiconductor chip body  60  and their top surfaces are illustrated in an exposed form in  FIG. 2 , the arrangement of the first chip pad  50   a  and the second chip pad  50   b  on the semiconductor chip body  60  is not limited thereto. Thus, the first chip pad  50   a  and the second chip pad  50   b  may be in a shape that protrudes toward the top surface of the semiconductor chip body  60 , for example. 
     The first chip pad  50   a  and the second chip pad  50   b  may be formed of aluminum containing a conductive material, for example. 
     An insulating film  70  that exposes (that is, that leaves exposed) the first chip pad  50   a  and the second chip pad  50   b  may be disposed on the semiconductor chip body  60 . 
     The insulating film  70  may be disposed throughout the first edge region EA 1 , the first redistribution region RA 1 , the central region CA, the second redistribution region RA 2  and the second edge region EA 2 . 
     The insulating film  70  may expose (that is, leave exposed) the top surfaces of each of the first chip pad  50   a  and the second chip pad  50   b . That is, the exposed regions of the first chip pad  50   a  and the second chip pad  50   b  may be defined through the insulating film  70 . 
     The insulating film  70  may contain at least one of oxide, nitride and oxynitride or may be made of flowable oxide (FOX), tonen silazen (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilaca glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PRTEOS), fluoride silicate glass (FSG), high density plasma (HDP), plasma enhanced oxide (PEOX), flowable CVD (FCVD) or a combination thereof. Although the insulating film  70  is illustrated as a single layer, inventive concepts are not limited thereto. 
     The semiconductor chip body  60  may be protected using the insulating film  70 , thereby blocking electrical interference between the semiconductor chip body  60  and the first and second redistribution layers  90   a  and  90   b  disposed on the semiconductor chip body  60 . The first redistribution layer  90   a  and the second redistribution layer  90   b  are disposed on the insulating film  70 . 
     The first redistribution layer  90   a  and the second redistribution layer  90   b  may extend along a first direction X. If each of a plurality of first redistribution layers  90   a  and second redistribution layers  90   b  may be disposed, the plurality of first redistribution layers  90   a  and the second redistribution layers  90   b  may be disposed side by side with each other along a second direction Y. 
     Because the first and second redistribution layers  90   a ,  90   b  function as interconnections that form an electrical connection, they are formed of a material with high electrical conductivity. For example, the first and second redistribution layers  90   a ,  90   b  may contain titanium (Ti), copper (Cu) and nickel (Ni). In some example embodiments, the first and second redistribution layers  90   a ,  90   b  may be formed of a thin film on which several kinds of metal are deposited to ensure excellent electrical conductivity, adhesion characteristics, protection characteristics and the like. 
     The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a  and a first edge pad region  10   a , and the second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     The first and second chip center pad regions  40   a ,  40   b  are regions for meter-reading the defect of the semiconductor device  1  Therefore, even in future processes, the top surfaces of the first and second chip center pad regions  40   a ,  40   b  maintain an open state for meter-reading (that is, they are left exposed for test-probing). 
     In this example embodiment, referring to  FIG. 1 , the chip center pad region is divided into first and second chip center pad regions  40   a ,  40   b , the redistribution center pad regions is divided into first and second redistribution center pad regions  30   a ,  30   b , the connection region is divided into first and second connection regions  20   a ,  20   b  and the edge pad region is divided into first and second edge pad regions  10   a ,  10   b  in this example embodiment. This is an example to dividedly illustrate each of the constituent elements, and does not mean that the constituent elements are formed of different materials or forms. 
     In this example embodiment, although each of six first redistribution layers  90   a  and second redistribution layers  90   b  are illustrated as being disposed on the semiconductor chip body  60 , inventive concepts are not limited thereto. 
     That is, the number of the first redistribution layers  90   a  and the second redistribution layers  90   b  disposed on the semiconductor chip body  60  may be variously determined, depending on the number of chip pads included in the semiconductor chip body  60  and the needs of the user. 
     In example embodiments, the first redistribution layer  90   a  may extend through the central region CA, the first redistribution region RA 1  and the first edge region EA 1 , along the first direction X. The second redistribution layer  90   b  may extend throughout the central region CA, the second redistribution region RA 2  and the second edge region EA 2  along the first direction X. That is, the first redistribution layer  90   a  and the second redistribution layer  90   b  may extend in the opposite directions to each other from the central region CA. However, inventive concepts are not limited thereto. 
     The first redistribution layer  90   a  may be electrically connected to the first chip pad  50   a  in the central region CA. In example embodiments, the first redistribution layer  90   a  may be directly in contact with the first chip pad  50   a  with the top surface exposed through the insulating film  70  in the central region CA, and may be electrically connected thereto. However, example embodiments are not limited thereto, and an additional metal layer may be disposed between the first redistribution layer  90   a  and the first chip pad  50   a , for example. 
     A passivation film  80  is formed on the first redistribution layer  90   a  and the second redistribution layer  90   b.    
     The passivation film  80  may expose respective partial regions of the first redistribution layers  90   a  and the second the redistribution layers  90   b  to define the first and second chip center pad regions  40   a ,  40   b , the first and second redistribution center pad regions  30   a ,  30   b  and the first and second edge pad regions  10   a ,  10   b.    
     In example embodiments, an overlap region between the first redistribution layer  90   a  and the exposed top surface of the first chip pad  50   a  may be the first chip center pad region  40   a . The first chip center pad region  40   a  may include a first center region  42   a  and a first peripheral region  41   a . The peripheral region  41   a  may wrap, or surround, at least a part of the first center region  42   a.    
     In example embodiments the first center region  42   a  is parallel to the first chip pad  50   a  (that is, top and bottom surfaces of the first center region  42   a  are parallel to the top surface of the first chip pad  50   a ) and may include a flat top surface, and the peripheral region  41   a  may include a sloped side wall. 
     The region of the first redistribution layer  90   a  connected to the first chip center pad region  40   a  through the peripheral region  41   a  and disposed on the insulating film  70  may be a first redistribution center pad region  30   a . That is, the first redistribution center pad region  30   a  is disposed on the insulating film  70  and, unlike the first chip center pad region  40   a , the first redistribution center pad region  30   a  may have a step different from the first center region  42   a . The first peripheral region  41   a  may include a sloped side wall due to the step. 
     That is, the top surface of the first chip center pad region  40   a  and the top surface of the first redistribution center pad region  30   a  may not be disposed on the same plane. In example embodiments, the top surface of the first chip center pad region  40   a  refers to all of the top surface of the first peripheral region  41   a  and the top surface of the first center region  42   a . Additionally, the expression “not disposed on the same plane” refers to the fact that, in this example embodiment, the top surface of the first redistribution center pad region  30   a  and the top surface of the first center region  42   a  of the first chip center pad region  40   a  are side by side but at different levels. 
     Although the side walls of the peripheral region  41   a  are illustrated as having a certain slope, inventive concepts are not limited thereto. For example, the peripheral region  41   a  may include side walls perpendicular to the top surface of the first center region  42   a  or the top surface of the first redistribution center pad region  30   a.    
     The form viewed from the top surface of the first chip center pad region  40   a  and/or the first center region  42   a  may be the form corresponding to the first chip pad  50   a . That is, when the form of the first chip pad  50   a  is a rectangular form, the form of the first chip center pad region  40   a  and/or the first center region  42   a  may be a rectangular form corresponding to the form of the first chip pad  50   a . Thus, the first chip center pad region  40   a  may ensure the maximum contact area with the first chip pad  50   a.    
     In example embodiments, the passivation film  80  may be formed of a polymer material such as photosensitive polyimide (PSPI), benzo-cyclo-butene (BCB) and epoxy. 
     Referring to  FIG. 2  again, the first redistribution center pad region  30   a  is parallel to the first chip pads  50   a  (that is the top and bottom surfaces of the center pad region  30   a  may be parallel to the top and bottom surfaces of the first chip pads  50   a ). The first redistribution center pad region  30   a  may include a flat top surface, and the top surface may have a first length a 1  and the top surface of the first center region  42   a  may have a second length a 2 . 
     In example embodiments, the first length a 1  is greater than the second length a 2 . That is, an opening in the passivation film  80  may expose the first redistribution center pad region  30   a  so that the first length a 1  is greater than the second length a 2 . 
     In some example embodiments of the present disclosure, the first redistribution center pad region  30   a  may be a wire bonding region or a flip bonding region for packaging the semiconductor. Because the first length a 1  is greater than the second length a 2 , the first redistribution center pad region  30   a  may provide a bonding region that allows a more stable bonding, as compared to the first chip center pad region  40   a . Because, in example embodiments in accordance with principles of inventive concepts it is possible to stably maintain the electrical connection between the semiconductor device  1  and the outside using the larger surface area of first redistribution center pad region  30   a , it is possible to improve the reliability of the semiconductor device  1  and the semiconductor package including the same. 
     The first redistribution layer  90   a  may include a first connection region  20   a  that is connected to the first redistribution center pad region  30   a  and is disposed between the passivation film  80  and the insulating film  70 . The first connection region  20   a  may be disposed in the first redistribution region RA 1 . The first connection region  20   a  may electrically connect the first redistribution center pad region  30   a  and the first edge pad region  10   a.    
     The first redistribution layer  90   a  may include a first edge pad region  10   a  with a top surface exposed to (that is, exposed through) the passivation film  80 . The first edge pad region  10   a  may be disposed in the first edge region EA 1 . 
     The first edge pad region  10   a  may be a wire bonding region or a flip bonding region for packaging the semiconductor, for example. Unlike the illustrated configuration, an additional metal layer may be disposed on the first edge pad region  10   a  to form the wire bonding or the flip bonding. 
     An overlap region between the second redistribution layer  90   b  and the exposed top surface of the second chip pad  50   b  may be the second chip center pad region  40   b . The second chip center pad region  40   b  may include a second center region  42   b  and a second peripheral region  41   b . The second peripheral region  41   b  may be in the form of wrapping at least a part of the second center region  42   b.    
     The second center region  42   b  is parallel to the second chip pad  50   b  (that is, top and bottom surfaces of second center region  42   b  may be parallel to top and bottom surfaces of second chip pad  50   b ). In example embodiments the second center region may include a flat top surface that, and the second peripheral region  41   b  may include a sloped side wall. 
     The region of the second redistribution layer  90   b  connected to the second chip center pad region  40   b  through the second peripheral region  41   b  and disposed on the insulating film  70  may be a second redistribution center pad region  30   b . That is, the second redistribution center pad region  30   b  is disposed on the insulating film  70 . Unlike the second chip center pad region  40   b , the second redistribution center pad region  30   b  may have a step different from the first center region  42   b . That is, the second peripheral region  41   b  of center pad region  40   b  may include a sloped side wall due to a step between the level of second center region  42   b  and second redistribution center pad region  30   b , which is due, in turn to the second redistribution center pad region being disposed on the insulating film  70  while the second center region  42   b  is not. 
     That is, the top surface of the second chip center pad region  40   b  and the top surface of the second redistribution center pad region  30   b  may not be disposed on the same plane. In example embodiments, the top surface of the second chip center pad region  40   b  refers to all of the top surface of the second peripheral region  41   b  and the top surface of the second center region  42   b . Additionally, the expression “not disposed on the same plane” refers to the fact that, in this example embodiment, the top surface of the second redistribution center pad region  30   b  and the top surface of the second center region  42   b  of the second chip center pad region  40   b  are side by side, but at different levels. 
     Although the side walls of the second peripheral region  41   b  are illustrated as having a particular slope, inventive concepts are not limited thereto. For example, the second peripheral region  41   b  may include side walls perpendicular to the top surface of the second center region  42   b  or the top surface of the second redistribution center pad region  30   b.    
     The form viewed from the top surface of the first chip center pad region  40   b  and/or the first center region  42   b  may be a form corresponding to the first chip pad  50   b . That is, when the form of the first chip pad  50   b  is a rectangular form, the form of the first chip center pad region  40   b  and/or the first center region  42   b  may be a rectangular form corresponding to the form of the first chip pad  50   b . The first chip center pad region  40   b  may ensure the maximum contact area with the first chip pad  50   b.    
     The second redistribution center pad region  30   b  is parallel to the second chip pad  50   b  and may include a flat top surface. As described in the discussion related to the first redistribution center pad region  30   a , the top surface may have a first length a 1  and the top surface of the second center region  42   b  may have a second length a 2 . 
     In example embodiments, the first length a 1  may be greaterer than the second length a 2 . That is, an opening in the passivation film  80  may leave exposed the second redistribution center pad region  30   b  so that the first length a 1  is larger than the second length a 2 . 
     In some example embodiments of the present disclosure, the second redistribution center pad region  30   b  may be a wire bonding region or a flip bonding region for packaging the semiconductor. Because the first length a 1  is greater than the second length a 2 , the second redistribution center pad region  30   b  may secure a bonding region that allows more stable bonding, as compared to the second chip center pad region  40   b . Because, in example embodiments in accordance with principles of inventive concepts, it is possible to stably maintain the electrical connection between the semiconductor device  1  and the outside using the larger surface area, or at least, longer bonding pad region of the second redistribution center pad region  30   b , it is possible to improve the reliability of the semiconductor device  1  and the semiconductor package including the same. 
     The second redistribution layer  90   b  may include a second connection region  20   b  that is connected to the second redistribution center pad region  30   b  and is disposed between the passivation film  80  and the insulating film  70 . The second connection region  20   b  may be disposed in the second redistribution region RA 2 . The second connection region  20   b  may electrically connect the second redistribution center pad region  30   b  and the second edge pad region  10   b.    
     The second redistribution layer  90   b  may include a second edge pad region  10   b  with a top surface exposed to (that is, exposed through) the passivation film  80 . The second edge pad region  10   b  may be disposed in the second edge region EA 2 . 
     The second edge pad region  10   b  may be a wire bonding region or a flip bonding region for packaging the semiconductor, for example. Unlike the illustrated configuration, an additional metal layer may be disposed on the second edge pad region  10   b  to form the wire bonding or the flip bonding. 
     Although the first and second redistribution layers  90   a ,  90   b  are illustrated as being symmetrically disposed in this embodiment, inventive concepts are not limited thereto. For example, only the first redistribution layer  90   a  may also be disposed on the semiconductor chip body  60 . Additionally, although each of the first and second redistribution layers  90   a ,  90   b  is illustrated to include each of the first and second redistribution center pad regions  30   a ,  30   b  in this embodiment, inventive concepts are not limited thereto. Thus, the second redistribution layer  90   b  may not include the second redistribution center pad region  30   b.    
     As described above, the first redistribution center pad region  30   a  is connected to the first chip center pad region  40   a , and the second redistribution center pad region  30   b  is connected to the second chip center pad region  40   b.    
     In particular, referring to  FIG. 3  again, when the form of viewing each of the first redistribution center pad region  30   a  and the first chip center pad region  40   a  from the top surface is a rectangular form, the rectangular form may share a first side L 1  each other. That is, in a region in which the first redistribution center pad region  30   a  and the first chip center pad region  40   a  abut against each other, the first redistribution center pad region  30   a  and the first chip center pad region  40   a  may have profiles continuously connected to each other. 
     Additionally, the first redistribution center pad region  30   a  may have a first width W 1  along the second direction Y and a second width W 2  along the first direction X, and the first chip center pad region  40   a  may have a first width W 1  along the second direction Y and a third width W 3  along the first direction X. Keeping in mind that the first chip center pad region  40   a  includes a first peripheral region  41   a  and a first center region  42   a , the second width W 2  may or may not be equal to or greater than the third width W 3 . 
     In the example embodiment of  FIG. 3 , the shapes of the first redistribution center pad region  30   a  and the first chip center pad region  40   a  are illustrated as an example on the assumption that the shape of the first chip pad  50   a  is rectangular. The shape of the first redistribution center pad region  30   a  and the shape of the first chip center pad region  40   a  are not limited to the illustrated shapes, and may be other polygonal shapes. 
     Although the shape of the second redistribution center pad region  30   b  and the shape of the second chip center pad region  40   b  are not illustrated in  FIG. 3 , the description of the first redistribution center pad region  30   a  and the first chip center pad region  40   a  may be similarly applied to the second redistribution center pad region  30   b  and the second chip center pad region  40   b  corresponding to each of the first redistribution center pad region  30   a  and the first chip center pad region  40   a.    
     The semiconductor device  1  according to some example embodiments of inventive concepts has been described through  FIGS. 1 through 3 . Because the semiconductor device  1  according to this embodiment includes the first and second redistribution center pad regions  30   a ,  30   b  connected to the first and second chip center pad regions  40   a ,  40   b , even in a case where the first and second redistribution layers  90   a ,  90   b  are disconnected due to an occurrence of defect such as short-circuit or open-curcuit in the first and second connection regions  20   a ,  20   b , the first and second redistribution center pad regions  30   a ,  30   b  can be used as the bonding regions for packaging and bonding the semiconductor. 
     Furthermore, as described above, because the first and second redistribution center pad regions  30   a ,  30   b  include regions larger than first and second central regions  42   a ,  42   b , it is possible to form and/or maintain the reliable packaging and bonding of the semiconductor. Inventive concepts are not limited to this example, and may also be similarly applied to some example embodiments of the present disclosure. 
     Next, a semiconductor device according to some example embodiments of the present disclosure will be described referring to  FIGS. 4 and 5 . 
       FIG. 4  is a perspective view for illustrating a semiconductor device according to some example embodiments in accordance with principles of inventive concepts.  FIG. 5  is a cross-sectional view taken along the line A 2 -A 2  of  FIG. 4 . 
     The semiconductor device  2  according to this embodiment is substantially the same as the semiconductor device  1  as described through  FIGS. 1 through 3  except that positions of the first chip center pad region of the first redistribution layer and the first redistribution center pad region are different. 
     Therefore, the same reference numerals refer to the same constituent elements, and a detailed description of the same constituent elements will not be repeated here. 
     Referring to  FIGS. 4 and 5 , the semiconductor device  1  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b.    
     The semiconductor chip body  60  may be divided into a first edge region EA 1 , a first redistribution region RA 1 , a central region CA, a second redistribution region RA 2  and a second edge region EA 2 . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a  and a first edge pad region  10   a . The second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     In this example embodiment, the first chip center pad region  40   a  of the first redistribution layer  90   a  may be disposed between the first redistribution center pad region  30   a  and the first connection region  20   a  and, as a result, in the semiconductor device  2  according to the example embodiment, the distance between the first redistribution center pad region  30   a  and the second redistribution center pad region  30   b  may be relatively short, as compared to the semiconductor device  1  as described through  FIGS. 1 through 3 . 
     In example embodiments of a semiconductor device in accordance with principles of inventive concepts, by variously modifying the arrangement between the first redistribution center pad region  30   a  and the first chip center pad region  40   a  and/or the arrangement between the second redistribution center pad region  30   b  and the second chip center pad region  40   b , it is possible to variously modify the distance between the first redistribution center pad region  30   a  and the second redistribution center pad region  30   b.    
     Example embodiments of a semiconductor device in accordance with principles of inventive concepts will be described referring to  FIGS. 6 and 7 . 
       FIG. 6  is a perspective view for illustrating example embodiments of a semiconductor device in accordance with principles of inventive concepts.  FIG. 7  is a cross-sectional view taken along the line A 3 -A 3  of  FIG. 6 . 
     The semiconductor device according to this embodiment is substantially the same as the semiconductor device described through  FIGS. 1 through 3 , except that each of the first and second redistribution layers includes a plurality of redistribution center pad regions. 
     The same reference numerals refer to the same constituent elements, and a detailed description of the same constituent elements will not be repeated here. 
     Referring to  FIGS. 6 and 7 , the semiconductor device  3  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b.    
     The semiconductor chip body  60  may be divided into a first edge region EA 1 , a first redistribution region RA 1 , a central region CA, a second redistribution region RA 2  and a second edge region EA 2 . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a  and a first edge pad region  10   a , and the second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     The first redistribution center pad region  30   a  may include a first sub-center pad region  30   a   1  and a second sub-center pad region  30   a   2 , and the second redistribution center pad region  30   b  may include a third sub-center pad region  30   b   1  and a fourth sub-center pad region  30   ab   2 . 
     The first sub-center pad region  30   a   1  and the second sub-center pad region  30   a   2  may be disposed side by side in the first direction X around the first chip center pad region  40   a.    
     The third sub-center pad region  30   b   1  and the fourth sub-center pad region  30   b   2  may be disposed side by side in the first direction X around the second chip center pad region  40   b.    
     The first sub-center pad region  30   a   1  and the second sub-center pad region  30   a   2  may be a region that is continuous with the first chip center pad region  40   a . The third sub-center pad region  30   b   1  and the fourth sub-center pad region  30   b   2  may be regions which are continuous with the second chip center pad region  40   b.    
     In this example embodiment, each of the first sub-center pad region  30   a   1  and the second sub-center pad region  30   a   2  included in the first redistribution center pad region  30   a  may be substantially the same as the first redistribution center pad region  30   a  described through  FIGS. 1 through 3 . That is, each of the first redistribution layer  90   a  and the second redistribution layer  90   b  is substantially the same as those including a plurality of first and second redistribution center pad regions  30   a ,  30   b  of  FIGS. 1 through 3 . 
     In this example embodiment, the first redistribution center pad region  30   a  includes the first sub-center pad region  30   a   1  and the second sub-center pad region  30   a   2 , and the second redistribution center pad region  30   b  includes the third sub-center pad region  30   b   1  and the fourth sub-center pad region  30   ab   2 , and it is possible to broadly ensure an effective wire bonding region or the flip bonding region for packaging and bonding the semiconductor. 
     Therefore, the reliability of a semiconductor package including the semiconductor device  3  according to this embodiment can be improved. In particular, as will be described in greater detail below, in the case of the semiconductor package subjected to flip bonding, it is possible to further improve the reliability as compared to other types of semiconductor packages. 
     An example embodiment of a semiconductor device according to inventive concepts will be described referring to  FIGS. 8 to 10 . 
       FIG. 8  is a perspective view for illustrating the semiconductor device according to some example embodiments of the present disclosure.  FIG. 9  is a cross-sectional view taken along the line A 4 -A 4  of  FIG. 8 .  FIG. 10  is an enlarged perspective view of a dotted region ‘b’ of  FIG. 8 . 
     The semiconductor device according to this example embodiment is substantially the same as the semiconductor device described through  FIGS. 1 to 3 , except that the first and second chip center pad regions and the first and second redistribution center pad regions included in each of the first and second redistribution layers are arranged along the second direction. 
     The same reference numerals refer to the same constituent elements, and a detailed description of the same constituent elements will not be repeated here. 
     Referring to  FIGS. 8 to 10 , a semiconductor device  4  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b.    
     The semiconductor chip body  60  may be divided into a first edge region EA 1 , a first redistribution region RA 1 , a central region CA, a second redistribution region RA 2  and a second edge region EA 2 . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a  and a first edge pad region  10   a , and the second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     In this example embodiment, the first redistribution layer  90   a  may include a first connection region  20   a  and a first edge pad region  10   a  arranged along the first direction X, and a first chip center pad region  40   a  disposed along the second direction Y, around the first redistribution center pad region  30   a.    
     Second redistribution layer  90   b  may include a second connection region  20   b  and a second edge pad region  10   b  arranged along the first direction X, and a second chip center pad region  40   b  disposed along the second direction Y, around the second redistribution center pad region  30   b.    
     In this example embodiment, the first and second chip center pad regions  40   a ,  40   b , the first and second redistribution center pad regions  30   a ,  30   b , the first and second connection regions  20   a ,  20   b  and the first and second edge pad regions  10   a ,  10   b  included in each of the first and second redistribution layers  90   a ,  90   b  may be irregularly disposed in a direction different from the first direction X, rather than being disposed along the first direction X as in some example embodiments. 
     That is, in this example embodiment, the arrangement of the first and second chip center pad regions  40   a ,  40   b  and the first and second redistribution center pad regions  30   a ,  30   b  included in the first and second redistribution layers  90   a ,  90   b  described through  FIG. 8  describes an example in which various arrangements of a plurality of regions included in each of the first and second redistribution layers  90   a ,  90   b  are possible. 
     In particular, referring to  FIG. 10  again, the first chip center pad region  40   a  and the first redistribution center pad region  30   a  included in the first redistribution layer  90   a  are continuously disposed along the second direction Y and each are in the rectangular forms that share a second side L 2 . 
     Example embodiments of a semiconductor device in accordance with principles of inventive concepts will be described referring to  FIGS. 11 and 12 . 
       FIG. 11  is a perspective view for illustrating a semiconductor device according to some example embodiments and  FIG. 12  is a cross-sectional view taken along the line A 5 -A 5  of  FIG. 11 . 
     A semiconductor device according to this example embodiment is substantially the same as the semiconductor device described through  FIGS. 8 to 10 , except that the arrangement of the first chip center pad region and the first redistribution center pad region is different. 
     The same reference numerals refer to the same constituent elements, and a detailed description of the same constituent elements will not be repeated here. 
     Referring to  FIGS. 11 and 12 , a semiconductor device  5  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b.    
     The semiconductor chip body  60  may be divided into a first edge region EA 1 , a first redistribution region RA 1 , a central region CA, a second redistribution region RA 2  and a second edge region EA 2 . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a  and a first edge pad region  10   a . The second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     In this example embodiment, the first redistribution layer  90   a  may include a first connection region  20   a  and a first edge pad region  10   a  disposed along the first direction X, and a first redistribution center pad region  30   a  disposed along the second direction Y, around the first chip center pad region  40   a.    
     The second redistribution layer  90   b  may include a second connection region  20   b  and a second edge pad region  10   b  disposed along the first direction X, and a second chip center pad region  40   b  disposed along the second direction Y, around the second redistribution center pad region  30   b.    
     As illustrated in this example embodiment, the first and second chip center pad regions  40   a ,  40   b , the first and second redistribution center pad regions  30   a ,  30   b , the first and second connection regions  20   a ,  20   b  and the first and second edge pad regions  10   a ,  10   b  included in each of the first and second redistribution layers  90   a ,  90   b  can be variously disposed. 
     An example embodiment of a semiconductor device in accordance with principles of inventive concepts will be described referring to  FIGS. 13 and 14 . 
       FIG. 13  is a perspective view for illustrating example embodiments of a semiconductor device in accordance with principles of inventive concepts and  FIG. 14  is a cross-sectional view taken along the line A 6 -A 6  of  FIG. 13 . 
     A semiconductor device  6  according to this example embodiment is substantially the same as the semiconductor device  1  as described through  FIGS. 1 to 3 . 
     The same reference numerals refer to same constituent elements, and a detailed description of the same constituent elements will not be repeated here. 
     Referring to  FIGS. 13 and 14 , the semiconductor device  6  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b.    
     The semiconductor chip body  60  may be divided into a first edge region EA 1 , a first redistribution region RA 1 , a central region CA, a second redistribution region RA 2  and a second edge region EA 2 . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a , a first connection pad region  15   a  and a first edge pad region  10   a . The second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b , a second connection pad region  15   b  and a second edge pad region  10   b.    
     In this example embodiment, the semiconductor device  6  includes a first connection pad region  15   a  disposed in the first redistribution region RAI, and a second connection pad region  15   b  disposed in the second redistribution region RA 2 . 
     Through the first and second connection pad regions  15   a ,  15   b  disposed in the first and second redistribution regions RA 1 , RA 2 , it is possible to check an occurrence point of defect such as short- or open-circuit in the first and second redistribution layers  90   a ,  90   b . Thus, it is possible to determine whether to use the semiconductor device  6 , and it is possible to perform process improvement work for preventing an occurrence of the same defect in other semiconductor devices. 
     In this example embodiment, although the single first and second connection pad regions  15   a ,  15   b  are illustrated as being disposed in each of the first and second redistribution regions RA 1 , RA 2 , inventive concepts are not limited thereto. For example, the plurality of first and second connection pad regions  15   a ,  15   b  may be disposed in each of the first and second redistribution regions RA 1 , RA 2 . 
     The number of first and second connection pad regions  15   a ,  15   b  disposed in each of the first and second redistribution regions RA 1 , RA 2  may be selected in view of the area of the region exposed through the first and second connection pad regions  15   a ,  15   b.    
     Further, respective areas of the first and second connection pad regions  15   a ,  15   b  may be relatively smaller than the area of the first and second chip center pad regions  40   a ,  40   b  and/or the first and second redistribution center pad regions  30   a ,  30   b , for example, but inventive concepts are not limited thereto. 
     Example embodiments of a semiconductor package in accordance with principles of inventive concepts will be described referring to  FIGS. 15 and 16 . 
       FIG. 15  is a perspective view for illustrating example embodiments of a semiconductor package in accordance with principles of inventive concepts and  FIG. 16  is a cross-sectional view taken along the line B-B of  FIG. 15 . 
     In this example embodiment, the semiconductor chip  100  included in the semiconductor package  7  may be any one of the semiconductor devices  1  to  6  described above. The same reference numerals of the semiconductor chip  100  refer to same constituent elements, and a detailed description of the same constituent elements will not be repeated here. Referring to  FIGS. 15 and 16 , the semiconductor package  7  includes a semiconductor chip  100 , a package substrate  200 , first and second wires  220   a ,  220   b  and an adhesive layer  240 . 
     The semiconductor chip  100  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a  and a first edge pad region  10   a . The second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     The semiconductor chip  100  may be disposed on a package substrate  200  through the adhesive layer  240 . The adhesive layer  240  may include resin or the like, but inventive concepts are not limited thereto. 
     The package substrate  200  may include first and second top pads  210   a ,  201   b  and first and second bottom pads  230   a ,  230   b . The package substrate  200  may be, for example, a printed circuit board (PCB). In this example embodiment, the package substrate  200  may be a ball grid array (BGA) type package substrate. The package substrate  200  may include internal wirings. The first and second top pads  210   a ,  201   b  may be connected to the internal wirings disposed in the package substrate  200 . 
     Each of the first and second top pads  210   a ,  201   b  may be a region in which the first and second wires  220   a ,  220   b  are bonded. 
     The first and second wires  220   a ,  220   b  may electrically connect with the semiconductor chip  100  with the package substrate  200 . Specifically, the first wire  220   a  may electrically connect the first top pad  210   a  with the first edge pad region  10   a  to transmit and receive electrical signals. The second wire  210   b  may electrically connect the second top pad  210   b  with the second edge pad region  10   b  to transmit and receive the electrical signals. 
     The electrical signals transmitted and received through the respective first and second wires  220   a ,  220   b  may be signals different from each other. Solder balls may be disposed on the first and second bottom pads  230   a ,  230   b , and the semiconductor package  7  may be mounted on a substrate of an electronic device. 
     Example embodiments of a semiconductor package according to principles of inventive concepts will be described referring to  FIG. 17 . 
       FIG. 17  is a cross-sectional view for illustrating example embodiments of a semiconductor package in accordance with principles of inventive concepts. 
     A semiconductor package  8  according to this embodiment is substantially the same as the semiconductor package  7  described through  FIGS. 15 and 16 , except for the packaging type. The same reference numerals refer to same constituent elements, and a detailed description of the same constituent elements will not be repeated here. 
     In the semiconductor package  8  according to this example embodiment, a semiconductor chip  100  is a board on chip (BOC) type and may be disposed on the package substrates  200   a ,  200   b.    
     Referring to  FIG. 17 , the semiconductor package  8  includes a semiconductor chip  100 , a package substrate  200 , first and second wires  220   a ,  220   b  and an adhesive layer  240 . 
     The semiconductor chip  100  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a  and a first edge pad region  10   a . The second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     The semiconductor chip  100  may be disposed on the package substrates  200   a ,  200   b  through the adhesive layer  240 . The adhesive layer  240  may include resin or the like, but inventive concepts are not limited thereto. 
     The package substrates  200   a ,  200   b  may include first and second top pads  210   a ,  201   b . The package substrates  200   a ,  200   b , for example, may be a printed circuit board (PCB). The package substrates  200   a ,  200   b  may include internal wirings. The first and second top pads  210   a ,  201   b  may be connected to the internal wirings disposed in the package substrates  200   a ,  200   b.    
     Each of the first and second top pads  210   a ,  201   b  may be a region in which the first and second wires  220   a ,  220   b  are bonded. 
     The first and second wires  220   a ,  220   b  may electrically connect the semiconductor chip  100  with the package substrates  200   a ,  200   b . The first and second wires  220   a ,  220   b , for example, may be formed of a conductive material containing copper. 
     The first wire  220   a  may electrically connect the first top pad  210   a  with the first redistribution center pad region  30   a  to transmit and receive the electrical signals. The second wire  210   b  may electrically connect the second top pad  210   b  with the second redistribution center pad region  30   b  to transmit and receive the electrical signals. The electrical signals transmitted and received through the first and second wires  220   a ,  220   b  may be signals different from each other. 
     In this example embodiment, the first and second wires  220   a ,  220   b  may be bonded to the first and second redistribution center pad regions  30   a ,  30   b  to transmit and receive the electrical signals to and from the package substrates  200   a ,  200   b.    
     That is, the semiconductor package  8  according to this example embodiment may not use the first and second edge pad regions  10   a ,  10   b . For example, when defect such as short-circuit of the first and second redistribution layers  90   a ,  90   b  occurs in the first and second connection regions  20   a ,  20   b , the semiconductor chip  100  may be used through the first and second redistribution center pad regions  30   a ,  30   b . In accordance with principles of inventive concepts, it is possible to utilize semiconductor chip  100  that otherwise may have been discarded due to the defect of the first and second redistribution layers  90   a ,  90   b , and the semiconductor package including the same. 
     Example embodiments of a semiconductor package according to inventive concepts will be described referring to  FIGS. 18 and 19 . 
       FIG. 18  is a cross-sectional view for illustrating example embodiments of a semiconductor package in accordance with principles of inventive concepts and  FIG. 19  is an enlarged cross-sectional view of a dotted region ‘c’ of  FIG. 18 . 
     A semiconductor package  9  according to this embodiment is substantially the same as the semiconductor package  7  described through  FIGS. 15 and 16 , except for the package type. The same reference numerals refer to same constituent elements, and a detailed description of the same constituent elements will not be repeated here. 
     In the semiconductor package  9  according to this embodiment, the semiconductor chip  100  may be disposed on the package substrate  200  in a flip type. 
     Referring to  FIGS. 18 and 19 , the semiconductor package  9  includes a semiconductor chip  100 , a package substrate  200 , first and second flip pads  250   a ,  250   b  and first and second bumps  260   a ,  260   b.    
     The semiconductor chip  100  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a first redistribution center pad region  30   a , a first connection region  20   a  and a first edge pad region  10   a . The second redistribution layer  90   b  may include a second chip center pad region  40   b , a second redistribution center pad region  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     The first and second flip pads  250   a ,  250   b , for example, may contain aluminum, and the first and second bumps  260   a ,  260   b  may be formed in a multilayer structure that contains a conductive material. 
     The package substrate  200  may include first and second top pads  210   a ,  201   b . The first and second top pads  210   a ,  201   b , for example, may contain aluminum. The package substrate  200  may be, for example, a printed circuit board (PCB). The package substrate  200  may include internal wirings. The first and second top pads  210   a ,  201   b  may be connected to the internal wirings disposed in the package substrate  200 . 
     Each of the first and second top pads  210   a ,  201   b  may be a region in which the first and second bumps  260   a ,  260   b  are bonded. 
     The first and second bumps  260   a ,  260   b  may electrically connect the semiconductor chip  100  with the package substrate  200 . Specifically, the first bumps  260   a  may electrically connect the first top pad  210   a  with the first redistribution center pad region  30   a  to transmit and receive electrical signals. The second bump  260   b  may electrically connect the second top pad  210   b  with the second redistribution center pad region  30   b  to transmit and receive electrical signals. Electrical signals transmitted and received through each of the first and second bumps  260   a ,  260   b  may be signals different from each other. 
     In this example embodiment, the first and second bumps  260   a ,  260   b  may be bonded to the first and second redistribution center pad regions  30   a ,  30   b  to transmit and receive electrical signals to and from the package substrates  200   a ,  200   b.    
       FIG. 19  illustrates that the first flip pad  250   a  is disposed on the first redistribution center pad region  30   a . As described above, the length a 1  of the first redistribution center pad region  30   a  is greater than the length a 2  of the first bonding region  41   a  of the first chip center pad region  40   a . Therefore, the first flip pad  250   a  may be disposed on a wider region of the first redistribution center pad region  30   a . In accordance with principles of inventive concepts, the semiconductor package  9  according to the embodiment is capable of performing reliable flip bonding. 
     Further, the semiconductor package  9  according to this embodiment also may notuse the first and second edge pad regions  10   a ,  10   b . Thus, when a defect such as short- or open-circuit of the first and second redistribution layers  90   a ,  90   b  occurs in the first and second connection regions  20   a ,  20   b , the semiconductor chip  100  may be used through the first and second redistribution center pad regions  30   a ,  30   b . Therefore, it is possible to utilize a semiconductor chip  100  that may otherwise have been discarded due to the defect of the first and second redistribution layers  90   a ,  90   b , and the semiconductor package including the same. 
     Example embodiments of a semiconductor package in accordance with principles of inventive concepts will be described referring to  FIG. 20 . 
       FIG. 20  is a cross-sectional view for illustrating example embodiments of a semiconductor package in accordance with principles of inventive concepts. 
     The semiconductor package  10  according to this embodiment is substantially the same as the semiconductor package  9  described through  FIGS. 18 and 19 , except for a difference in the number of bumps. 
     Also, the semiconductor chip  100  included in the semiconductor package  10  according to this embodiment may be substantially the same as the semiconductor chip  100  disclosed in the semiconductor device  3  described through  FIGS. 6 and 7 . The same reference numerals refer to the same constituent elements, and a detailed description of the same constituent elements will not be repeated here. 
     Referring to  FIG. 20 , the semiconductor package  10  includes a semiconductor chip  100 , a package substrate  200 , a plurality of first and second flip pads  250   a ,  250   b  and a plurality first and second bumps  260   a ,  260   b.    
     The semiconductor chip  100  includes a semiconductor chip body  60 , an insulating film  70 , a passivation film  80 , a first redistribution layer  90   a  and a second redistribution layer  90   b . The first redistribution layer  90   a  may include a first chip center pad region  40   a , a plurality of first redistribution center pad regions  30   a , a first connection region  20   a  and a first edge pad region  10   a , and the second redistribution layer  90   b  may include a second chip center pad region  40   b , a plurality of second redistribution center pad regions  30   b , a second connection region  20   b  and a second edge pad region  10   b.    
     The plurality of first and second flip pads  250   a ,  250   b , for example, may contain aluminum, and the first and second bumps  260   a ,  260   b  may be formed of a multilayer structure that contains a conductive material. 
     The package substrate  200  may include a plurality of first and second top pads  210   a ,  201   b . The first and second top pads  210   a ,  201   b , for example, may contain aluminum. The package substrate  200 , for example, may be a printed circuit board (PCB). The package substrate  200  may include internal wirings. The first and second top pads  210   a ,  201   b  may be connected to the internal wirings disposed in the package substrate  200 . 
     Each of the plurality of first and second top pads  210   a ,  210   b  may be a region in which the plurality of first and second bumps  260   a ,  260   b  is bonded. 
     The plurality of first and second bumps  260   a ,  260   b  may electrically connect the semiconductor chip  100  with the package substrate  200 . In this embodiment, the plurality of first bumps  260   a  may be electrically connected to the first chip pad  50   a , and the plurality of second bumps  260   b  may be electrically connected to the second chip pad  50   b.    
     Therefore, even when a defect occurs in any one of the plurality of first bumps  260   a , it is possible to maintain the electrical connection with the first chip pad  50   a  using the other first bump  260   a , and similarly, when a defect occurs in any one of the plurality of second bumps  260   b , it is possible to maintain the electrical connection with the second chip pad  50   b  using the other second bump  260   b.    
     Thus, the semiconductor package  10  according to inventive concepts may improve the reliability of the semiconductor package  10  packaged in a flip type. 
       FIG. 21  is a block diagram of an electronic system including a semiconductor device and semiconductor package in accordance with principles of inventive concepts. 
     Referring to  FIG. 21 , the electronic system  11000  including the semiconductor device  1  to  6  and the semiconductor package  7  to  10  according to some example embodiments of inventive concepts may include a controller  11100 , an input/output (I/O) device  11200 , a memory device  11300 , an interface  11400  and a bus  11500 . The controller  11100 , the I/O device  11200 , the memory device  11300  and/or the interface  11400  may be connected to one another through the bus  11500 . The bus  11500  corresponds to a path through which the data are moved. 
     The controller  11100  may include at least one of a microprocessor, a digital signal processor, a microcontroller and logic devices capable of performing similar functions to the elements. The I/O device  11200  may include a keypad, a keyboard, a display device and the like. The memory device  11300  may store data and/or commands. The interface  11400  may serve to transmit data receive data to or from a communication network. The interface  11400  may be a wired or wireless interface. For example, the interface  11400  may include an antenna or a wired or wireless transceiver. Although it is not illustrated, the electronic system  11000  may further include a high-speed DRAM or SRAM, as an operating memory for improving the operation of the controller  11100 . The semiconductor device  1  to  11  manufactured according to principle of inventive concepts may be provided in the memory device  11300  or may be provided as a part of the controller  11100 , the I/O device  11200  or the like. 
     The electronic system  11000  may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a smart phone, a mobile phone, a digital music player, a memory card or all types of electronic products capable of transmitting or receiving information in a wireless environment. 
       FIG. 22  is an exemplary semiconductor system to which the semiconductor device and the semiconductor package according to some example embodiments in accordance with principles of inventive concepts are applicable. 
       FIG. 22  illustrates a tablet PC. The semiconductor device  1  to  6  and the semiconductor package  7  to  10  according to some example embodiments of inventive concepts may be used in a tablet PC, a laptop computer and the like. It will be apparent to those skilled in the art that a semiconductor device manufactured according to some example embodiments of inventive concepts may also be applied to other integrated circuit devices that are not illustrated. 
     While inventive concepts have been particularly illustrated and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the scope of inventive concepts as defined by the following claims. The exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation.