Patent Publication Number: US-7587541-B2

Title: Master-slave device communication circuit

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention relates to communication circuits, and particularly to a communication which communicates between a master device and a slave device thereof. 
   2. Description of Related Art 
   In some communication systems, a master device such as a central processing unit (CPU) communicates with some slave devices such as DRAMs via buses. Generally, when the master device needs to access a slave device, the master device will transmit a corresponding selecting signal such as a power signal to the slave device. When the slave device receives the selecting signal, the master device will communicate with the slave device immediately. However, sometimes when the master device transmits the selecting signal to the slave device, the slave device is not at a ready status, which may cause data transmitting errors between the master device and the slave device. 
   What is desired, therefore, is to provide a master-slave device communication circuit that overcomes the above problem. 
   SUMMARY 
   An embodiment of a master-slave device communication circuit includes a master device, a bus, and a slave device having a bus switch connected to the master device via the bus, and a status detecting circuit. The status detecting circuit includes a power input terminal and a detecting signal output terminal. A power terminal of the master device is connected to the power input terminal of the status detecting circuit. The detecting signal output terminal is connected to the bus switch and a trigger pin of the master device. When the master device supplies power to the slave device via the power terminal thereof, the detecting signal output terminal transmits a control signal to control the bus switch to turn on the bus and trigger the master device to communicate with the slave device after a delay time. 
   Other advantages and novel features of the present invention will become more apparent from the following detailed description of an embodiment when taken in conjunction with the accompanying drawings, in which: 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a master-slave device communication circuit in accordance with an embodiment of the present invention; and 
       FIG. 2  is a circuit diagram of a status detecting circuit of the master-slave device communication circuit of  FIG. 1 . 
   

   DETAILED DESCRIPTION 
   Referring to  FIGS. 1 and 2 , a master-slave device communication circuit in accordance with an embodiment of the present invention includes a master device  10 , a slave device  20 , a bus  30  connecting the master device  10  to the slave device  20 . The slave device includes a bus switch  22  connected to the bus  30  and a status detecting circuit  24 . 
   The status detecting circuit  24  includes a first voltage comparator OP 1 , a second voltage comparator OP 2 , a first electrical switch such as an NPN transistor Q 1 , a second electrical switch such as an NPN transistor Q 2 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a first capacitor C 1 , a second capacitor C 2 , and a third capacitor C 3 . 
   A power terminal VDD of the master device  10  is connected to the inverting input terminal of the first voltage comparator OP 1  via the first resistor R 1  and connected to the non-inverting input terminal of the second voltage comparator OP 2 . The first capacitor C 1  is connected between the inverting input terminal of the first voltage comparator OP 1  and ground. The non-inverting input terminal of the first voltage comparator OP 1  and the inverting input terminal of the second voltage comparator OP 2  are connected to a reference voltage source VREF. The power terminals of the two voltage comparators OP 1  and OP 2  are connected to the power terminal VDD of the master device  10 . The ground terminals of the two voltage comparators OP 1  and OP 2  are grounded. 
   The output terminal of the first voltage comparator OP 1  is connected to the base of the transistor Q 1  and connected to ground via the second capacitor C 2 . The power terminal VDD of the master device  10  is connected to the base of the transistor Q 1  via the second resistor R 2 . The collector of the transistor Q 1  is connected to the power terminal VDD via the third resistor R 3  and as a detecting signal output terminal T 1  connected to the bus switch  22  and a trigger pin, such as a general purpose I/O (GPIO) pin, of the master device  10 . The emitter of the transistor Q 1  is connected to the collector of the transistor Q 2 . The output terminal of the second voltage comparator OP 2  is connected to the base of the transistor Q 2  and ground via the third capacitor C 3 . The emitter of the transistor Q 2  is grounded. 
   When the master device  10  needs to access the slave device  20 , the master device  10  supplies power to the slave device  20  via the power terminal VDD of the master device  10 . Initially, because the RC circuit of the first resistor R 1  and the first capacitor C 1  has delay function, the voltage of the inverting input terminal is less than the voltage of the non-inverting input terminal of the first voltage comparator OP 1 . Thereby, the voltage of the output terminal of the first voltage comparator OP 1  is at a high voltage level, and the transistor Q 1  is turned on. At this initial state, the voltage of the inverting input terminal is less than the voltage of the non-inverting input terminal of the second voltage comparator OP 2 . Thereby, the voltage of the output terminal of the second voltage comparator OP 2  is at a high voltage level, and the transistor Q 2  is turned on. The detecting signal output terminal T 1  transmits a low voltage signal to the bus switch  22  and the trigger pin of the master device  10 . 
   After a delay time, the voltage of the inverting input terminal becomes greater than the voltage of the non-inverting input terminal of the first voltage comparator OP 1 . Thereby, the voltage of the output terminal of the first voltage comparator OP 1  is at a low voltage level, and the transistor Q 1  is turned off. The delay time allows the slave device  20  to enter a ready state. Then, the detecting signal output terminal T 1  transmits a control signal that goes from low to high to the bus switch  22  to control the bus switch  22  to turn on the bus  30 , and the control signal is also transmitted to the trigger pin of the master device  10 , and then the master device  10  is triggered to communicate with the slave device  20 . 
   The delay time can be selected by selecting the resistance of the first resistor R 1  and the capacitance of the first capacitor C 1  according to need. After the delay time, the slave device  20  is to communicate with the master device  10 , which prevents data transmitting errors between the master device  10  and the slave device  20 . 
   It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.