Patent Publication Number: US-11656988-B2

Title: Memory device and operation method thereof

Description:
This application claims the benefit of U.S. provisional application Ser. No. 63/175,554, filed Apr. 16, 2021, the subject matter of which is incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The disclosure relates in general to an In-Memory-Computing memory device and an operation method thereof. 
     BACKGROUND 
     Artificial Intelligence (“AI”) has recently emerged as a highly effective solution for many fields. The key issue in AI is that AI contains large amounts of input data (for example input feature maps) and weights to perform multiply-accumulate (MAC) operation. 
     However, the current AI structure usually encounters IO (input/output) bottleneck and inefficient MAC operation flow. 
     In order to achieve high accuracy, it would perform MAC operations having multi-bit inputs and multi-bit weights. But, the IO bottleneck becomes worse and the efficiency is lower. 
     In-Memory-Computing (“IMC”) can accelerate MAC operations because IMC may reduce complicated arithmetic logic unit (ALU) in the process centric architecture and provide large parallelism MAC operation in memory. 
     In executing IMC, if the operation speed is improved, then the IMC performance will be improved. 
     SUMMARY 
     According to one embodiment, provided is a memory device including: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result. 
     According to another embodiment, provided is an operation method for a memory device. The operation method includes: storing an input data in a plurality of page buffers; based on received addresses of a plurality of memory planes, performing, by the memory planes, bit multiplication in parallel on a plurality of weights stored in the plurality of memory planes and the input data to generate a plurality of bit multiplication results in parallel, the plurality of bit multiplication results being stored back to the page buffers; and performing bit accumulation on the plurality of bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    shows a functional block diagram of an IMC (In-Memory-Computing) memory device according to a first embodiment of the application. 
         FIG.  2    shows a functional block diagram of a memory plane and an accumulation circuit according to the first embodiment of the application. 
         FIG.  3    shows data mapping according to the first embodiment of the application. 
         FIG.  4 A  to  FIG.  4 C  show several possible example of data mapping according to the first embodiment of the application. 
         FIG.  5    shows an example of the multiplication operations of the first embodiment of the application. 
         FIG.  6 A  and  FIG.  6 B  show the grouping operation (the majority operation) and counting according to the first embodiment of the application. 
         FIG.  7 A  and  FIG.  7 B  show MAC operation flows according to the first embodiment of the application. 
         FIG.  8    shows a functional block diagram of an IMC (In-Memory-Computing) memory device according to a second embodiment of the application. 
         FIG.  9 A  and  FIG.  9 B  show MAC operation flows according to the second embodiment of the application. 
         FIG.  10    shows a flow chart of an operation method for a memory device according to a third embodiment of the application. 
     
    
    
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
     DESCRIPTION OF THE EMBODIMENTS 
     Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the disclosure. Each of the disclosed embodiments has one or more technical features. In possible implementation, one skilled person in the art would selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure. 
     First Embodiment 
       FIG.  1    shows a functional block diagram of an IMC (In-Memory-Computing) memory device  100  according to a first embodiment of the application. The memory device  100  includes a plurality of memory planes, a plurality of page buffers, a plurality of conversion units, an accumulation detection circuit  120 , an output latch  130  and an accumulation circuit  140 . The conversion unit is for example but not limited by, an analog-to-digital converter (ADC). 
     For simplicity, in  FIG.  1   , the memory device  100  includes four memory planes MP 0 -MP 3 , four page buffers PB 0 -PB 3 , four conversion units ADC 0 -ADC 3 , an accumulation detection circuit  120 , an output latch  130  and an accumulation circuit  140 . But the application is not limited thereby. 
     The page buffers PB 0 -PB 3  may store an input data IN and send the input data IN to the memory planes MP 0 -MP 3 . A plurality of bit multiplication results BM 0 -BM 3  generated by the memory planes MP 0 -MP 3  are stored back to the page buffers PB 0 -PB 3 . Further, controlled by a page buffer selection signal PB_SEL, the output latch  130  selects the bit multiplication results BM 0 -BM 3  stored in the corresponding page buffers PB 0 -PB 3  to the accumulation circuit  140 . 
     The memory planes MP 0 -MP 3  are coupled to the page buffers PB 0 -PB 3 . The memory planes MP 0 -MP 3  parallel perform bit multiplication operations (for example, bit AND operations) on weights stored in the memory planes MP 0 -MP 3  with the input data IN from the page buffers PB 0 -PB 3  to parallel generate the bit multiplication results BM 0 -BM 3 . The bit multiplication results BM 0 -BM 3  are stored back into the page buffers PB 0 -PB 3 . Further, one or more memory cell string(s) of the memory planes MP 0 -MP 3  are selected to enable the sensing operations. When the weights stored in the memory planes MP 0 -MP 3  and the input data IN from the page buffers PB 0 -PB 3  are bit-multiplied, a plurality of memory cells of the memory planes MP 0 -MP 3  generate a plurality of memory cell currents IMC 0 -IMC 3  and the memory cell currents IMC 0 -IMC 3  are commonly input into the conversion units ADC 0 -ADC 3 . 
     The conversion units ADC 0 -ADC 3  are coupled to the memory planes MP 0 -MP 3 . The memory cell currents IMC 0 -IMC 3  of the memory planes MP 0 -MP 3  are input into the conversion units ADC 0 -ADC 3 , respectively. The conversion units ADC 0 -ADC 3  convert the memory cell currents IMC 0 -IMC 3  of the memory planes MP 0 -MP 3  into a plurality of conversion results AMACO 0 -AMACO 3 . 
     The accumulation detection circuit  120  is coupled to the conversion units ADC 0 -ADC 3 . The accumulation detection circuit  120  compares the conversion results AMACO 0 -AMACO 3  of the conversion units ADC 0 -ADC 3  with a threshold value respectively to generate a page buffer selection signal PB_SEL to the output latch  130  and to generate an accumulation enable signal ACC_EN to the accumulation circuit  140 . When the conversion results AMACO 0 -AMACO 3  are higher than the threshold value, in response to the page buffer selection signal PB_SEL, the output latch  130  selects the corresponding bit multiplication results BM 0 -BM 3  stored in the corresponding page buffers PB 0 -PB 3  to the accumulation circuit  140 . 
     When at least one among the conversion results AMACO 0 -AMACO 3  is higher than the threshold value, the accumulation enable signal ACC_EN is in the enabled state; and on the contrary, the accumulation enable signal ACC_EN is in the disabled state. 
     The output latch  130  is coupled to the accumulation detection circuit  120  and the page buffers PB 0 -PB 3 . In response to the page buffer selection signal PB_SEL, the output latch  130  selects the corresponding bit multiplication results BM 0 -BM 3  stored in the corresponding page buffers PB 0 -PB 3  to the accumulation circuit  140 . For example but not limited by, when the conversion results AMACO 0  and AMACO 1  from the conversion units ADC 0  and ADC 1  are higher than the threshold value, in response to the page buffer selection signal PB_SEL, the output latch  130  selects the corresponding bit multiplication results BM 0 -BM 1  stored in the corresponding page buffers PB 0 -PB 1  to the accumulation circuit  140 . 
     The accumulation circuit  140  is coupled to the output latch  130  and the accumulation detection circuit  120 . When enabled by the accumulation enable signal ACC_EN, the accumulation circuit  140  performs bit accumulation operations on the bit multiplication results BM 0 -BM 3  from the output latch  130  to generate a MAC operation result OUT, and the details are described later. 
       FIG.  2    shows a functional block diagram of a memory plane and an accumulation circuit according to the first embodiment of the application. The memory plane MP in  FIG.  2    may be used to implement the memory planes MP 0 -MP 3  in  FIG.  1   . As shown in  FIG.  2   , the memory plane MP includes a memory block  210  and a multiplication circuit  220 . The accumulation circuit  140  includes a grouping circuit  240  and a counting unit  250 . The multiplication circuit  220  is analog while the accumulation circuit  140 , the grouping circuit  240  and the counting unit  250  are digital. 
     The memory block  210  includes a plurality of memory cells  211 . In one embodiment of the application, the memory cell  211  is for example but not limited by, a non-volatile memory cell. In MAC operations, the memory cells  211  are used for storing the weights. 
     The multiplication circuit  220  is coupled to the memory block  210 . The multiplication circuit  20  includes a plurality of single-bit multiplication units  221 . Each of the single-bit multiplication units  221  includes an input latch  221 A, a sensing amplifier (SA)  221 B, an output latch  221 C and a common data latch (CDL)  221 D. The input latch  221 A is coupled to the memory block  210 . The sensing amplifier  221 B is coupled to the input latch  221 A. The output latch  221 C is coupled to the sensing amplifier  221 B. The common data latch  221 D is coupled to the output latch  221 C. The bit multiplication result BM from the multiplication circuit  220  is stored back to the page buffer PB. 
     When the weight stored in the memory cell  211  is logic 1 and the corresponding input data IN is also logic 1, the memory cell  211  generates the cell current. The cell currents from the memory cells  211  are summed into a memory cell current IMC. 
     In the first embodiment of the application, “digital accumulation” refers to that the accumulation circuit  140  is enabled but the conversion units ADC 0 -ADC 3  are not enabled. “Hybrid accumulation” refers to that the accumulation circuit  140  and the conversion units ADC 0 -ADC 3  are enabled. That is, in the first embodiment of the application, the conversion units ADC 0 -ADC 3  are optionally triggered. 
     In one embodiment of the application, trigger of the conversion units may be used to rapidly filter the useless data to improve the MAC operation speed; the accumulating circuit  140  may accumulate the unfiltered data to improve the MAC operation accuracy. The hybrid accumulating may eliminate the variation influence of using low-resolution quantization, avoid the accumulation of useless data and maintain the resolution. 
     The grouping circuit  240  is coupled to the output latch  130 , The grouping circuit  240  includes a plurality of grouping units  241 . The grouping units  241  perform grouping operations on the bit multiplication results BM 0 -BM 3  to generate a plurality of grouping results. In one possible embodiment of the application, the grouping technique may be implemented by the majority technique, for example, the majority function technique, the grouping circuit  240  may be implemented by a majority grouping circuit based on the majority function technique, and the grouping units  241  may be implemented by a distributed majority grouping unit, which is not intended to limit the application. The grouping technique may be implemented by other similar techniques. 
     The counting unit  250  is coupled to the grouping circuit  240 . In one embodiment of the application, the counting unit  250  is for performing bitwise counting or bitwise accumulating on the grouping results (i.e. the majority results) from the grouping circuit  240  to generate the MAC operation result OUT. In one embodiment of the application, the counting unit  250  is implemented by known counting circuits, for example but not limited by, a ripple counter. In the application, the term “counting” and “accumulating” are interchangeable, and the counter and the accumulator have substantially the same meaning. 
     In the first embodiment of the application, by the circuit structure in  FIG.  1    and  FIG.  2   , the current from each memory plane may be individually quantized. Further, the accumulation circuit  140  may be shared by the memory planes, which may further reduce the circuit area. 
     Now refer to  FIG.  3    which shows data mapping according to one embodiment of the application. As shown in  FIG.  3   , each input data and each weight have N dimension(s) (N being a positive integer) with 8 bit precision, but the application is not limited by this. 
     Data mapping of the input data is described as an example but the application is not limited by. The following description is also suitable for data mapping of the weights. 
     When the input data (or the weight) is represented by a binary 8-bit format, the input data (or the weight) includes a most significant bit (MSB) vector and a least significant bit (LSB) vector. The MSB vector of the 8-bit input data (or the weight) includes bits B 7  to B 4  and the LSB vector of the 8-bit input data (or the weight) includes bits B 3  to B 0 . 
     Each bit of the MSB vector and the LSB vector of the input data is represented into unary code (value format). For example, the bit B 7  of the MSB vector of the input data may be represented as B 7   0 -B 7   7 , the bit B 6  of the MSB vector of the input data may be represented as B 6   0 -B 6   3 , the bit B 5  of the MSB vector of the input data may be represented as B 5   0 -B 5   1 , and the bit B 4  of the MSB vector of the input data may be represented as  34 . 
     Then, each bit of the MSB vector of the input data and each bit of the LSB vector of the input data represented into unary code (value format) are respectively duplicated multiple times into an unfolding dot product (unFDP) format. For example, each of the MSB vector of the input data are duplicated by (2 4 −1) times, and similarly, each of the LSB vector of the input data are duplicated by (2 4 −1) times. By so, the input data are represented in the unFDP format. Similarly, the weights are also represented in the unFDP format. 
     Multiplication operation is performed on the input data (in the unFDP format) and the weights (in the unFDP format) to generate a plurality of multiplication results. 
     For understanding, one example of data mapping is described but the application is not limited thereby. 
     Now refer to  FIG.  4 A  which shows one possible example of data mapping in one dimension according to the first embodiment of the application. As shown in  FIG.  4 A , the input data is (IN 1 , IN 2 )=(2, 1) and the weight is (We 1 , We 2 )=(1, 2). The MSB and the LSB of the input data is represented in the binary format, and thus IN 1 =10 while IN 2 =01. Similarly, the MSB and the LSB of the weight is represented in the binary format, and thus We 1 =01 while We 2 =10. 
     Then, the MSB and the LSB of the input data, and the MSB and the LSB of the weight are encoded into unary code (value format). For example, the MSB of the input data is encoded into “110”, while the LSB of the input data is encoded into “001”. Similarly, the MSB of the weight is encoded into “001”, while the LSB of the weight is encoded into “110”. 
     Then, each bit of the MSB (110, encoded into the unary code) of the input data and each bit of the LSB (001, encoded into the unary code) of the input data are duplicated a plurality of times to be represented in the unFDP format. For example, each bit of the MSB (110, represented in the value format) of the input data is duplicated three times, and thus the unFDP format of the MSB of the input data is 111111000. Similarly, each bit of the LSB (001, represented in the value format) of the input data is duplicated three times, and thus the unFDP format of the LSB of the input data is 000000111. 
     The multiplication operation is performed on the input data (represented in the unFDP format) and the weights to generate an MAC operation result. The MAC operation result is 1*0=0, 1*0=0, 1*1=1, 1*0=0, 1*0=0, 1*1=1, 0*0=0, 0*0=0, 0*1=0, 0*1=0, 0*1=0, 0*0=0, 0*1=0, 0*1=0, 0*0=0, 1*1=1, 1*1=1, 1*0=0. The values are summed into: 0+0+1+0+0+1+0+0+0+0+0+0+0+0+0+1+1+0=4. 
     From the above description, when the input data is “i” bits while the weight is “j” bits (both “i” and “j” are positive integers), the total memory cell number used in the MAC (or the multiplication) operations will be (2 i −1)*(2 j −1). 
     Now refer to  FIG.  4 B  which shows another possible example of data mapping according to the first embodiment of the application. As shown in  FIG.  4 B , the input data is (IN 1 )=(2) and the weight is (We 1 )=(1). The input data and the weight are in 4-bit. 
     The input data is represented in the binary format, and thus IN 1 =0010. Similarly, the weight is represented in the binary format, and thus We 1 =0001. 
     The input data and the weight are encoded into unary code (value format). For example, the highest bit “ 0 ” of the input data is encoded into “00000000”, while the lowest bit “ 0 ” of the input data is encoded into “0” and so on. Similarly, the highest bit “ 0 ” of the weight is encoded into “00000000”, while the lowest bit “ 1 ” of the weight is encoded into “1”. 
     Then, each bit of the input data (encoded into the unary code) is duplicated a plurality of times to be represented in the unFDP format. For example, the highest bit  401 A of the input data (encoded into the unary code) is duplicated fifteen times into the bits  403 A; and the lowest bit  401 B of the input data (encoded into the unary code) is duplicated fifteen times into the bits  403 B. 
     The weight  402  (encoded into the unary code) is duplicated fifteen times to be represented in the unFDP format. 
     The multiplication operation is performed on the input data (represented in the unFDP format) and the weights (represented in the unFDP format) to generate an MAC operation result. In details, the bits  403 A of the input data are multiplied by the weight  402 ; the bits  403 E of the input data are multiplied by the weight  402 ; and so on. The MAC operation result (“2”) is generated by adding the multiplication values. 
     Now refer to  FIG.  4 C  which shows another possible example of data mapping according to the first embodiment of the application. As shown in  FIG.  4 C , the input data is (IN 1 )=(1) and the weight is (We 1 )=(5). The input data and the weight are in 4-bit. 
     The input data is represented in the binary format, and thus IN 1 =0001. Similarly, the weight is represented in the binary format, and thus We 1 =0101. 
     Then, the input data and the weight are encoded into unary code (value format). 
     Then, each bit of the input data (encoded into the unary code) is duplicated a plurality of times to be represented in the unFDP format. In  FIG.  4 C , a bit “ 0 ” is added when each bit of the input data and each bit of the weight are duplicated. For example, the highest bit  411 A of the input data (encoded into the unary code) is duplicated fifteen times and a bit “ 0 ” is added to form the bits  413 A; and the lowest bit  411 B of the input data (encoded into the unary code) is duplicated fifteen times and a bit “ 0 ” is added to form the bits  413 B. By so, the input is represented in the unFDP format. 
     Similarly, the weight  412  (encoded into the unary code) is duplicated fifteen times and a bit “ 0 ” is additionally added into each of the weights  414 , By so, the weight is represented in the unFDF format. 
     The multiplication operation is performed on the input data (represented in the unFDP format) and the weights (represented in the unFDF format) to generate an MAC operation result. In details, the bits  413 A of the input data are multiplied by the weight  414 ; the bits  413 B of the input data are multiplied by the weight  414 ; and so on. The MAC operation result (“ 5 ”) is generated by adding the multiplication values. 
     In the prior art, in MAC operations on 8-bit input data and 8-bit weight, if direct MAC operations are used, then the total memory cell number used in the direct MAC operations will be 255*255*512=33,292,822. 
     On the contrary, in one embodiment of the application, in MAC operations on 8-bit input data and 8-bit weight, the total memory cell number used in the direct MAC operations will be 15*15*512*2=115,200*2=230,400. Thus, the memory cell number used in the MAC operation according to one embodiment of the application is about 0.7% of the memory cell number used in the prior art. 
     In one embodiment of the application, by using unFDP-based data mapping, the memory cell number used in the MAC operation is reduced and thus the operation cost is also reduced. Further, ECC (error correction code) cost is also reduced and the tolerance of the fail-bit effect is improved. 
     Referring to  FIG.  1    and  FIG.  2    again. In one embodiment of the application, in multiplication operations, the weight (the transconductance) is stored in the memory cells  211  of the memory block  210  and the input data (the voltage) is stored read out by the page buffer and transmitted to the common data latch  221 D, The common data latch  221 D outputs the input data to the input latch  221 A. 
     In order to explain the multiplication operations of one embodiment of the application, now refer to  FIG.  5    which shows one example of the multiplication operations of one embodiment of the application.  FIG.  5    is used in the case that the memory device supports the selected bit-line read function. In  FIG.  5   , the input latch  221 A includes a latch  505  and a bit line switch  510 . 
     As shown in  FIG.  5   , the weight is represented into unary code (value format), as shown in  FIG.  32   . Thus, the highest bit of the weight is stored in eight memory cells  211  the second highest bit of the weight is stored in four memory cells  211 , the third highest bit of the weight is stored in two memory cells  211  and the lowest bit of the weight is stored in one memory cell  211 . 
     Similarly, the input data is represented into unary code (value format) (as shown in  FIG.  3   ). Thus, the highest bit of the input data is stored in eight common data latches  221 D, the second highest bit of the input data is stored in four common data latches  221 D, the third highest bit of the input data is stored in two common data latches  221 D and the lowest bit of the input data is stored in one common data latch  121 D. The input data is sent from the common data latches  221 D to the latches  505 . 
     In  FIG.  5   , the plurality of bit line switches  510  are coupled between the memory cells  211  and the sensing amplifiers  221 B. The bit line switches  510  are controlled by outputs of the latches  505 . For example, when the latch  505  outputs bit “ 1 ”, the bit line switch  510  is conducted while when the latch  505  outputs bit “ 0 ”, the bit line switch  510  is disconnected. 
     Further, when the weight stored in the memory cell  211  is bit  1  and the bit line switch  510  is conducted (i.e. the input data is bit  1 ), the SA  221 B senses the memory cell current to generate the multiplication result “ 1 ”. When the weight stored in the memory cell  211  is bit  0  and the bit line switch  510  is conducted (i.e. the input data is bit  1 ), the SA  221 B senses no memory cell current. When the weight stored in the memory cell  211  is bit  1  and the bit line switch  510  is disconnected (i.e. the input data is bit  0 ), the SA  221 B senses no memory cell current (to generate the multiplication result “ 0 ”). When the weight stored in the memory cell  211  is bit  0  and the bit line switch  510  is disconnected (i.e. the input data is bit  0 ), the SA  221 B senses no memory cell current. 
     That is, via the layout shown in  FIG.  5   , when the input data is bit  1  and the weight is bit  1 , the SA  221 B senses the memory cell current (to generate the multiplication result “ 1 ”). In other situations, the SA  221 B senses no memory cell current (to generate the multiplication result “ 0 ”). The multiplication result of the SA  221 B is sent to the output latch  221 C. The outputs (which form the bit multiplication result BM) of the output latches  221 C is stored back to the page buffer PB via the common data latch  221 D. 
     The memory cell currents IMC from the memory cells  211  are summed and input into one among the conversion units ADC 0 -ADC 3 . 
     The relationship between the input data, the weight, the digital multiplication result and the analog memory cell current IMC is as the following table: 
     
       
         
           
               
               
               
               
             
               
                   
               
               
                 the input data 
                 the weight 
                 the digital multiplication result 
                 IMC 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 0 
                 0 
                 (HVT) 
                 0 
                 0 
               
               
                 0 
                 +1 
                 (LVT) 
                 0 
                 0 
               
               
                 1 
                 0 
                 (HVT) 
                 0 
                 IHVT 
               
               
                 1 
                 +1 
                 (LVT) 
                 1 
                 ILVT 
               
               
                   
               
            
           
         
       
     
     In the above table, HVT and LVT refer to high-threshold memory cell and low-threshold memory cell, respectively; and IHVT and ILVT refer to the respective analog memory cell current IMC generated by the high-threshold memory cell (the weight is 0(HTV) and the low-threshold memory cell (the weight is +1(LTV) when the input data is logic 1. 
     In one embodiment of the application, in multiplication operations, the selected bit line read (SBL-read) command may be reused to reduce the variation influence due to single-bit representation. 
     Now refer to  FIG.  6 A , which shows the grouping operation (the majority operation) and bitwise counting according to one embodiment of the application. As shown in  FIG.  6 A , “GM 1 ” refers to a first multiplication result from bitwise multiplication on the first MSB vector of the input data by the weights; “GM 2 ” refers to a second multiplication result from bitwise multiplication on the second MSB vector of the input data by the weights; “GM 3 ” refers to a third multiplication result from bitwise multiplication on the third MSB vector of the input data by the weights; and “GL” refers to a fourth multiplication result from bitwise multiplication on the LSB vector of the input data by the weights. After the grouping operation (the majority operation), the grouping result performed on the first multiplication result “GM 1 ” is a first grouping result CB 1  (whose accumulation weight is 2 2 ); the grouping result performed on the second multiplication result “GM 2 ” is a second grouping result CB 2  (whose accumulation weight is 2 2 ); the grouping result performed on the third multiplication result “GM 3 ” is a third grouping result CB 3  (whose accumulation weight is 2 2 ); and the direct counting result on the fourth multiplication result “GL” is a fourth grouping result CB 4  (whose accumulation weight is 2°). 
       FIG.  6 B  shows one accumulation example in  FIG.  4 C . Refer to  FIG.  4 C  and  FIG.  6 B . As shown in  FIG.  6 B , the bits  413 B of the input data (in  FIG.  4 C ) are multiplied by the weight  414 . The first four bits (“0000”) of the multiplication result, generated by multiplication of the bits  413 B of the input data (in  FIG.  4 C ) with the weight  414 , are grouped as the first multiplication result “GM 1 ”. Similarly, the fifth to the eighth bits (“0000”) of the multiplication result, generated by multiplication of the bits  413 B of the input data (in  FIG.  4 C ) with the weight  414 , are grouped as the second multiplication result “GM 2 ”. The ninth to the twelfth bits (“1111”) of the multiplication result, generated by multiplication of the bits  413 B of the input data (in  FIG.  4 C ) with the weight  414 , are grouped as the third multiplication result “GM 3 ”. The thirteenth to the sixteenth bits (“0010”) of the multiplication result, generated by multiplication of the bits  413 B of the input data (in  FIG.  40   ) with the weight  414 , are directly counted. 
     After the grouping operation (the majority operation), the first grouping result CB 1  is “0” (whose accumulation weight is 2 2 ); the second grouping result CB 2  is “0” (whose accumulation weight is 2 2 ); the third grouping result CB 3  is “1” (whose accumulation weight is 2 2 ). In counting, the MAC result is generated by accumulating the respective grouping results CB 1 -CB 4  multiplied by the respective accumulation weight. For example, as shown in  FIG.  6 B , the MAC operation result OUT is:
 
 CB 1*2 2   +CB 2*2 2   +CB 3*2 2   CB 4*2 0 =0*2 2 0*+2 2 +1*2 2 +1*2 0 =0000 0000 0000 0000 0000 0000 0000 0101=5.
 
     In one embodiment of the application, the grouping principle (for example, the majority principle) is as follows. 
     
       
         
           
               
               
               
             
               
                   
                   
               
               
                   
                 Group bits 
                 Grouping result (Majority result) 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 1111 
                 (case A) 
                 1 
               
               
                 1110 
                 (case B) 
                 1 
               
               
                 1100 
                 (case C) 
                 1 or 0 
               
               
                 1000 
                 (case D) 
                 0 
               
               
                 0000 
                 (case E) 
                 0 
               
               
                   
               
            
           
         
       
     
     In the above table, in case A, because the group has correct bits (“1111” which means no error bits), the majority result is 1. Similarly, in the above table, in case E, because the group has correct bits (“0000” which means no error bits), the majority result is 0. 
     In case B, because the group has one error bit (among “1110”, the bit “ 0 ” is error), by majority function, the group “1110” is determined to be “1”. In case D, because the group has one error bit (among “0001”, the bit “ 1 ” is error), by majority function, the group “0001” is determined to be “0”. 
     In case C, because the group has two error bits (among “1100”, the bits “ 00 ” or “ 11 ” are error), by majority function, the group “1100” is determined to be “1” or “0”. 
     Thus, in one embodiment of the application, by grouping (majority) function, the error bits are reduced. 
     The majority results from the grouping circuit  240  are input into the counting unit  250  for bitwise counting. 
     In counting, the counting result for the mutt cation results of the MSB vector and the counting result for the multiplication results of the LSB vector are add or accumulated. As shown in  FIG.  6 A , two accumulators are used. A first accumulator is assigned by a heavy accumulating weight (for example 2 2 ). The first accumulator is accumulating: (1) the grouping result (the majority result) (having one bit) from performing the grouping operation (the majority operation) on the multiplication result GM 1 , (2) the grouping result (the majority result) (having one bit) from performing the grouping operation (the majority operation) on the multiplication result GM 2 , and (3) the grouping result (the majority result) (having one bit) from performing the grouping operation (the majority operation) on the multiplication result GM 3 , The accumulation result by the first accumulator is assigned by heavy accumulating weight (for example 2 2 ). A second accumulator is assigned by a light accumulating weight (for example 2 0 ). The second accumulator is directly accumulating the multiplication result GL (having multiple bits). The two accumulation results by the two accumulators are added to output the MAC operation result OUT. For example but not limited by, (1) the grouping result (the majority result) (having one bit) from performing the grouping (majority) operation on the multiplication result GM 1  is “1” (one bit), (2) the grouping result (the majority result) (having one bit) from performing the grouping (majority) operation on the multiplication result GM 2  is “0” (one bit), and (3) the grouping result (the majority result) (having one bit) from performing the grouping (majority) operation on the multiplication result GM 3  is “1” (one bit). The accumulation result by the first accumulator, after weighting, is 2(=1+0+1)*2 2 =8. The multiplication result GL is 4 (having three bits). The MAC operation result OUT is 8+4=12. 
     From the above, in one embodiment of the application, in counting or accumulation, the input data is in the unFDP format, data stored in the CDL is grouped into the MSB vector and the LSB vector. By group (majority) function, the error bits in the MSB vector and the LSB vector are reduced. 
     Further, in one embodiment of the application, even the conventional accumulator (the conventional counter) is used, the time cost in counting and accumulating is also reduced. This is because digital counting command (error bit counting) is applied in one embodiment of the application and different vectors (the MSB vector and the LSB vector) are assigned by different accumulating weights. In one possible example, the time cost in accumulation operation is reduced to about 40%. 
       FIG.  7 A  and  FIG.  7 B  show MAC operation flows in one embodiment of the application.  FIG.  7 A  shows the MAC operation flow when the conversion units ADC 0 -ADC 3  are triggered and the MAC operation flow may be also referred as a hybrid MAC operation flow,  FIG.  7 B  shows the MAC operation flow when the conversion units ADC 0 -ADC 3  are not triggered and the MAC operation flow may be also referred as a digital MAC operation flow. When the conversion units ADC 0 -ADC 3  are not triggered, the output latch  130  outputs the bit multiplication results BM 0 -BM 3  to the accumulation circuit  140  for bit accumulation (that is, the output latch  130  is not controlled by the page buffer selection signal PB_SEL and the accumulation circuit  140  is not controlled by the accumulation enable signal ACC_EN). 
     In  FIG.  7 A , during the timing period T 11 , the input is broadcasted (i.e. the input data is received). During the timing period T 12 , a plurality of addresses of the memory planes are received. The memory planes perform operations based on different addresses. However, one embodiment of the application prevents the situation that several memory planes use the same address; and thus, the memory planes use different addresses. During the timing period T 13 , based on the received addresses of the memory planes, bit multiplication is performed. During the timing period T 14 , the bit multiplication results are output (for example, output from the memory planes to the accumulation circuits). During the timing period T 15 , bit accumulation is performed. Bit accumulation on different memory planes are executed in sequential. For example, as shown in  FIG.  7 A , the conversion results AMACO 0  and AMACO 2  are higher than the threshold value, bit accumulation on the memory planes MP 0  and MP 2  are executed in sequential while bit accumulation on the memory planes MP 1  and MP 3  are not executed. Of course, the sequence of the bit accumulation is not limited by  FIG.  7 A . In  FIG.  7 A , bit accumulation on the memory plane MP 2  is executed first and then bit accumulation on the memory plane MP is executed later, which is also within the spirit and scope of the application. During the timing period T 16 , the MAC operation results are output; and the next addresses of the memory planes are also output. 
     In  FIG.  7 B , the timing periods T 21 -T 24  and T 26  are the same or similar to the timing periods T 11 -T 14  and T 16 . During the timing period T 25  (bit accumulation), because the conversion units ADC 0 -ADC 3  are not triggered, in bit accumulation, bit accumulation on all memory planes are executed in sequential. For example, as shown in  FIG.  7 B , bit accumulation on the memory planes MP 0 , MP 1 , MP 2  and MP 3  are executed in sequential. Of course, the sequence of the bit accumulation is not limited by  FIG.  7 B , other execution sequence of the bit accumulation is also possible, which is also within the spirit and scope of the application. 
     As shown in  FIG.  7 A  and  FIG.  7 B , in the first embodiment of the application, the bit multiplication operations on different memory planes are performed in parallel while the bit accumulation operations on different memory planes are performed in sequential. Thus, in the first embodiment of the application, the scheduling is in centralized control which reduces circuit area and power consumption. 
     From  FIG.  7 A  and  FIG.  7 B , the MAC operation in the embodiment of the application has two types of sub-operations. The first sub-operation is multiplication to multiply the input data with the weights, which is based on the selected bit line read command. The second sub-operation is accumulation (data counting), especially, fail bit counting. In other possible embodiment of the application, more counting unit may be used to speed up the counting or accumulation operations. 
     Second Embodiment 
       FIG.  8    shows a functional block diagram of an IMC (In-Memory-Computing) memory device  800  according to a second embodiment of the application. The memory device  800  includes a plurality of memory planes, a plurality of page buffers, a plurality of conversion units, a plurality of accumulation detection circuits, an output latch  830  and a plurality of accumulation circuits. The conversion unit is for example but not limited by, an analog-to-digital converter (ADC). 
     For simplicity, in  FIG.  8   , the memory device  800  includes four memory planes MP 0 -MP 3 , four page buffers PB 0 -PB 3 , four conversion units ADC 0 -ADC 3 , four accumulation detection circuits  820 - 0 ˜ 820 - 3 , an output latch  830  and four accumulation circuits  840 - 0 ˜ 840 - 3 . But the application is not limited thereby. 
     The page buffers PB 0 -PB 3  may store an input data IN and send the input data IN to the memory planes MP 0 -MP 3 , A plurality of bit multiplication results BM 0 -BM 3  generated by the memory planes MP 0 -MP 3  are stored back to the page buffers PB 0 -PB 3  and for sending to the accumulation circuits  840 - 0 - 840 - 3 . 
     The memory planes MP 0 -MP 3  are coupled to the page buffers PB 0 -PB 3 . The memory planes MP 0 -MP 3  parallel perform bit multiplication operations (for example, bit AND operations) on weights stored in the memory planes MP 0 -MP 3  with the input data IN from the page buffers PB 0 -PB 3  to parallel generate the bit multiplication results BM 0 -BM 3 . The bit multiplication results BM 0 -BM 3  are stored back into the page buffers PB 0 -PB 3 . Further, one or more memory cell string(s) of the memory planes MP 0 -MP 3  are selected to enable the sensing operations. When the weights stored in the memory planes MP 0 -MP 3  and the input data IN from the page buffers PB 0 -PB 3  are bit-multiplied, a plurality of memory cells of the memory planes MP 0 -MP 3  generate a plurality of memory cell currents IMC 0 -IMC 3  and the memory cell currents IMC 0 -IMC 3  are commonly input into the conversion units ADC 0 -ADC 3 . 
     The conversion units ADC 0 -ADC 3  are coupled to the memory planes MP 0 -MP 3 . The memory cell currents IMC 0 -IMC 3  of the memory planes MP 0 -MP 3  are input into the conversion units ADC 0 -ADC 3 , respectively. The conversion units ADC 0 -ADC 3  convert the memory cell currents IMC 0 -IMC 3  of the memory planes MP 0 -MP 3  into a plurality of conversion results AMACO 0 -AMACO 3 . 
     The accumulation detection circuits  820 - 0 - 820 - 3  are coupled to the conversion units ADC 0 -ADC 3 . The accumulation detection circuits  820 - 0 - 820 - 3  compare the conversion results AMACO 0 -AMACO 3  of the conversion units ADC 0 -ADC 3  with a threshold value to generate a plurality of accumulation enable signals ACC_EN 0 -ACC_EN 3  to the accumulation circuits  840 - 0 - 840 - 3 . When the conversion results AMACO 0 -AMACO 3  are higher than the threshold value, the corresponding accumulation enable signals ACC_EN 0 -ACC_EN 3  are in the enabled state; and on the contrary, the accumulation enable signals ACC_EN 0 -ACC_EN 3  are in the disabled state. 
     The accumulation circuits  840 - 0 - 840 - 3  are coupled to the accumulation detection circuits  820 - 0 - 820 - 3 . When enabled by the accumulation enable signals ACC_EN 0 -ACC_EN 3 , the accumulation circuits  840 - 0 - 840 - 3  perform bit accumulation operations on the bit multiplication results BM 0 -BM 3  from the memory planes MP 0 -MP 3  to generate a plurality of digital accumulation results DMACO 0 -DMACO 3 . 
     The output latch  830  is coupled to the accumulation circuits  840 - 0 - 840 - 3 . The output latch  830  outputs the digital accumulation results DMACO 0 -DMACO 3  from the accumulation circuits  840 - 0 - 840 - 3  into the MAC operation result OUT. 
     The accumulation circuits  840 - 0 - 840 - 3  may have the same or similar circuit structure and operations as the accumulation circuit  140  in  FIG.  2    and thus the details are omitted. Similarly, the memory plane MP in  FIG.  2    may be used to implement the memory planes MP 0 -MP 3  of  FIG.  8   . 
     In the second embodiment of the application, the cell currents of each memory plane are individually quantized. 
     Data mapping in the second embodiment may be the same or similar to data mapping in the first embodiment and thus the details are omitted. 
       FIG.  9 A  and  FIG.  9 B  show MAC operation flows in the second embodiment of the application.  FIG.  9 A  shows the MAC operation flow when the conversion units ADC 0 -ADC 3  are triggered and the MAC operation flow may be also referred as the hybrid MAC operation flow.  FIG.  9 B  shows the MAC operation flow when the conversion units ADC 0 -ADC 3  are not triggered and the MAC operation flow may be also referred as the digital MAC operation flow. When the conversion units ADC 0 -ADC 3  are not triggered, the accumulation circuits  840 - 0 - 840 - 3  perform bit accumulation on the bit multiplication results BM 0 -BM 3  (that is, the accumulation circuits  840 - 0 - 840 - 3  are not controlled by the accumulation enable signals ACC_EN 0 -ACC_EN 3 ). 
     In  FIG.  9 A , the timing periods T 31 -T 34  and T 36  are the same or similar to the timing periods T 11 -T 14  and T 16 . During the timing period T 35 , the bit accumulation is performed. In bit accumulation, bit accumulation on different memory planes are executed in parallel. For example, as shown in  FIG.  9 A , the conversion results AMACO 0  and AMACO 2  are higher than the threshold value, bit accumulation on the memory planes MP 0  and MP 2  are executed in parallel while bit accumulation on the memory planes MP 1  and MP 3  are not executed. 
     In  FIG.  9 B , the timing periods T 41 -T 44  and T 46  are the same or similar to the timing periods T 11 -T 14  and T 16 . During the timing period T 45 , because the conversion units ADC 0 -ADC 3  are not triggered, in bit accumulation, bit accumulation on all memory planes are executed in parallel. 
     As shown in  FIG.  9 A  and  FIG.  9 B , in the second embodiment of the application, the bit multiplication operations on different memory planes are performed in parallel while the bit accumulation operations on different memory planes are performed in parallel. Thus, in the second embodiment of the application, the scheduling is in distributed control which fastens MAC operations. 
       FIG.  3   ,  FIG.  4 A  to  FIG.  4 C ,  FIG.  5    and  FIG.  6 A  to  FIG.  6 B  are also applicable to the second embodiment of the application. 
     Third Embodiment 
       FIG.  10    shows an operation method for a memory device according to a third embodiment of the application. The operation method for the memory device according to the third embodiment of the application includes: storing an input data in a plurality of page buffers ( 1010 ); based on the received addresses of a plurality of memory planes, performing, by the memory planes, bit multiplication in parallel on a plurality of weights stored in the plurality of memory planes and the input data to generate a plurality of bit multiplication results in parallel, the plurality of bit multiplication results being stored back to the page buffers ( 1020 ); and performing bit accumulation on the plurality of bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result, the MAC operation result is output and next addresses of the memory planes are also output ( 1030 ). Details of the steps  1010 - 1030  are as described above and thus are omitted. 
     The read voltage may affect the output value from the ADC and reading of bit  1 . In the first to the third embodiments of the application, based on the operation conditions (for example but not limited by, the programming cycle, the temperature or the read disturbance), the read voltage may be periodically calibrated to keep high accuracy and high reliability. 
     The first to the third embodiments of the application are applied to NAND type flash memory, or the memory device sensitive to the retention and thermal variation, for example but not limited by, NOR type flash memory, phase changing memory, magnetic RAM or resistive RAM. 
     The first to the third embodiments of the application is applied in 3D structure memory device and 2D structure memory device, for example but not limited by, 2D/3D NAND type flash memory, 2D/3D NOR type flash memory, 2D/3D phase changing memory, 2D/3D magnetic RAM or 2D/3D resistive RAM. 
     Although in the first to the third embodiments of the application, the input data and/or the weight are divided into the MSB vector and the LSB vector (i.e. two vectors), but the application is not limited by this. In other possible embodiment of the application, the input data and/or the weight are divided into more vectors, which is still within the spirit and the scope of the application. 
     The first to the third embodiments of the application are not only applied to majority group technique, but also other grouping techniques to speed up accumulation. 
     The first to the third embodiments of the application are A techniques, for example but not limited by, face identification. 
     In the first to the third embodiments of the application, the conversion unit may be implemented by a current mode ADC, a voltage mode ADC or a hybrid mode ADC. 
     The first to the third embodiments of the application may be applied in serial MAC operations or parallel MAC operations. 
     The first to the third embodiments of the application may be applied to non-volatile memory or volatile memory. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.