Patent Publication Number: US-7913204-B2

Title: High-level synthesis apparatus, high-level synthesis system and high-level synthesis method

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims benefit of priority from the Japanese Patent Application No. 2007-331971, filed on Dec. 25, 2007, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a high-level synthesis apparatus, a high-level synthesis system, and a high-level synthesis method. 
     2. Related Art 
     As semiconductor integrated circuits have grown smaller, the scale of the system LSI which can be mounted on a single chip has increased. An example of a known method for designing a large-scale system efficiently in a short period of time is high-level synthesis in which a behavioral description describing only the behavior of the system (logic circuit) is created using a high-level language such as the C language, and a RTL (Register Transfer Level) description including hardware information such as clock cycles, registers and operators is synthesized from the behavioral description. 
     In high-level synthesis, logic circuit design is performed based on indicators for which static analysis is simple, such as area and delay times, but power consumption which is a dynamic characteristic is not taken into account. A well-known technique for lowering the power consumption of logic circuits is to stop supplying the clock using gated clock circuits. However, if gated clock circuits are employed in all the logic circuits, the scale of the circuit increases. Moreover, for the logic circuits with only short intervals between periods of operation, the clock supply can rarely be stopped and the saving in power consumption is small. 
     Conventional high-level synthesis thus had a problem in that it was not possible to design logic circuits offering significant power saving while suppressing increases in circuit scale. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, there is provided a high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description, comprising: 
     a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description; 
     a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph and output register information indicating the point, the scheduling result inputting/outputting unit being provided with dynamic analysis data that includes at least one of the number of times that data at the point has been substituted and the number of times that a value stored at the point has changed by a predetermined simulation; 
     an allocating unit configured to consult dynamic analysis data and allocate circuit elements to the behavioral description; and 
     an RTL description generating unit configured to generate the logic circuit based on the allocation of circuit elements by the allocating unit. 
     According to one aspect of the present invention, there is provided a high-level synthesis system for automatically generating a register transfer level (RTL) logic circuit from a behavioral description, comprising: 
     a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description; 
     a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph, and output register information indicating the point; 
     a simulator provided with predetermined simulation data, the behavioral description and the register information, the simulator executing a simulation using the predetermined simulation data in the behavioral description, generating dynamic analysis data including at least one of the number of data substitutions and the number of changes to a stored value at the point indicated in the register information, and outputting the generated dynamic analysis data; 
     an allocating unit configured to consult the dynamic analysis data and allocate circuit elements to the behavioral description; and 
     an RTL description generating unit configured to generate the logic circuit based on allocation of circuit elements by the allocating unit. 
     According to one aspect of the present invention, there is provided a A high-level synthesis method for automatically generating a register transfer level (RTL) logic circuit from a behavioral description, comprising: 
     performing data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description; 
     extracting a point to be allocated to a register from data flow graph, and executing a simulation using predetermined simulation data for the behavioral description; 
     generating dynamic analysis data that includes at least one of the number of data substitutions at the point or the number of changes to a stored value at the point from results of the simulation; 
     consulting the dynamic analysis data and allocating circuit elements to the behavioral description; and 
     generating the logic circuit based on the allocation of the circuit elements. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing a schematic configuration of the high-level synthesis system according to an embodiment of the present invention; 
         FIG. 2  shows an example of a behavioral description; 
         FIG. 3  shows an example of a data flow graph; 
         FIG. 4  shows an example of internal states created from the behavioral description and register information; 
         FIG. 5  shows an example of simulation-use input data and corresponding simulation results; 
         FIG. 6  shows an example of dynamic analysis data; 
         FIG. 7  shows an example of register allocation in allocation processing; 
         FIG. 8  is a diagram showing an example of a circuit employing a clock supply stopping circuit; 
         FIG. 9  is a flowchart describing a high-level synthesis method according to the embodiment; 
         FIG. 10  shows an example of a behavioral description; 
         FIG. 11  shows an example of a data flow graph; 
         FIG. 12  shows an example of internal states created from the behavioral description and the register information; 
         FIG. 13  shows an example of simulation-use input data and simulation results; 
         FIG. 14  shows an example of dynamic analysis data; 
         FIG. 15  shows an example of register allocation in allocation processing; and 
         FIG. 16  shows a further example of register allocation in allocation processing. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     The following describes embodiments of the present invention with reference to the drawings. 
       FIG. 1  shows a schematic configuration of a high-level synthesis system according to an embodiment of the present invention. The high-level synthesis system includes a high-level synthesis apparatus  110  and a simulator  120 . 
     The high-level synthesis apparatus  110  includes a scheduling unit  111 , a scheduling result inputting/outputting unit  112 , an allocating unit  113 , and a RTL description generating unit  114 . 
     The high-level synthesis apparatus  110  is provided with a behavioral description  101 . The behavioral description  101  defines the processing content from the input of the circuit to the output of the circuit, and may be written in C or a similar programming language. An example of (part of) a behavioral description is shown in  FIG. 2 . 
     The scheduling unit  111  analyzes the data flow and determines the operation cycles (time steps) at which operations in the behavioral description  101  are executed. Data from between differing time steps are held in storage elements (such as registers, latches, or memory). 
     The scheduling result inputting/outputting unit  112  outputs information about the points (operation device output) which are to be allocated to the storage elements, as register information  103 . 
       FIG. 3  shows a data flow graph generated by analyzing and scheduling the data flow of the behavioral description shown in  FIG. 2 . From  FIG. 3 , it can be seen that a subtraction operator  301  and an addition operator  302  are allocated to step  1 , a multiplication operator  303  and an addition operator  304  are allocated to step  2 , and a division operator  305  is allocated to step  3 . 
     Further, the points p 0  to p 4  between the steps and at the outputs of the operators are allocated to storage elements, and the points are indicated in the register information  103 . 
     The simulator  120  is supplied with the behavioral description  101 , simulation-use input data  102 , and the register information  103 . The simulation-use input data is data (sample data) which is actually to be processed using the logic circuits designed using the high-level synthesis system. For instance, when designing a circuit for image processing, image data is used as the simulation-use input data  102 . 
     The simulator  120  specifies the points to be allocated to the storage elements (locations indicated by the register information  103 ) from the behavioral description  101  and the register information  103 . The simulator  120  then performs a simulation using the simulation-use input data  102 , and stores the data at the points indicated by the register information  103 . 
     For instance, from the behavioral description shown in  FIG. 2  and the register information shown in  FIG. 3 , internal states of the type shown in  FIG. 4  are created and values for the points p 0  to p 4  which actually change when the simulation is performed are stored. 
     The simulator  120  performs analysis on the stored data. For instance, the simulator  120  may detect the number of times that a value (data) is substituted at each point or the number of times that a value is changed at each point. The simulator  120  outputs the results of the analysis as dynamic analysis data  104 . 
     For the internal states shown in  FIG. 4 , an example of the simulation-use input data and values for each point are shown in  FIG. 5 .  FIG. 5  shows the results of executing the simulation with  10  sets of prepared simulation-use input data. In  FIG. 5 , the count column contains an execution count, columns in 0  to in 5  contain input data and p 0  to p 4  contain values of the points indicated by the register information. 
       FIG. 6  is an example of the dynamic analysis data obtained by analyzing the simulation results shown in  FIG. 5 . The number of substitutions column contains the number of times the value has been substituted at each point. The number of changes column contains the number of times that the value of each point differs from the preceding value after execution of the simulation. From  FIG. 6 , it can be seen that the number of changes is fewer for points p 0  and p 3 . 
     The dynamic analysis data  104  is inputted to the scheduling result inputting/outputting unit  112  of the high-level synthesis apparatus  110 . 
     The allocating unit  113  performs allocation processing using the behavioral description  101 , the data flow graph and the dynamic analysis data  104 . The allocation processing is processing to allocate circuit elements (operation devices and the like) for the behavioral description and synthesize logic circuits. 
     The allocating unit  113  consults the dynamic analysis data  104  and allocates registers (storage elements) to the points indicated by the register information  103 . For instance, points for which the number of value substitutions or value changes is small may be grouped and allocated to the same register. 
     For example, from the dynamic analysis data shown in  FIG. 6 , it is decided to allocate the points p 0  and p 3  to a single register R 0001  and the remaining points, p 1 , p 2  and p 4  to a different register R 0002  as shown in  FIG. 7 . 
     The RTL description generating unit  114  generates a RTL (Register Transfer Level) circuit description  105  using data from after the allocation processing, and outputs the generated RTL circuit description. 
     In logic circuits designed in this way, the use of the clock supply stopping circuit is restricted to registers allocated to points for which the number of value substitutions or value changes is small. In other words, gated clock registers are allocated to points for which the number of value substitutions or value changes is small. 
     In the example shown in  FIG. 2  to  FIG. 7 , for instance, a clock supply stopping circuit  801  is used in the register R 0001  alone as shown in  FIG. 8  to supply a gated clock signal. 
     Thus, the points for which the number of value substitutions or number of value changes is small are grouped and allocated to the same register. By restricting use of the clock supply stopping circuit to the register, it is possible to efficiently design logic circuits with low power consumption. Moreover, in comparison to the case in which the clock supply stopping circuit is used in all of the registers, the number of clock supply stopping circuits can be reduced, and, as a result, an increase in circuit scale can be suppressed. 
     The high-level synthesis method according to the present embodiment is described using the flowchart shown in  FIG. 9  and a different example to that shown in  FIGS. 2 to 7 . 
     (Step S 901 ) Data flow analysis using the behavioral description and scheduling processing are performed. A further example of a behavioral description is shown in  FIG. 10 , and the data flow graph obtained as a result of the scheduling is shown in  FIG. 11 . 
     (Step S 902 ) The register information indicating the points to be allocated to the registers is outputted. In the example shown in  FIG. 11 , the register information includes information for the points p 0  to p 5 . 
     (Step S 903 ) The internal states are created using the behavioral description and the register information, and the locations for storing the data (operation results) during the simulation are specified. From the behavioral description shown in  FIG. 10  and the register information shown in  FIG. 11 , internal states of the type shown in  FIG. 12  are created. 
     (Step S 904 ) A simulation is executed using the simulation-use input data, and values for each point are stored. An example of the simulation-use input data and the values of the points p 0  to p 5  obtained in the internal state shown in  FIG. 12  when the simulation using the simulation-use input data is performed are shown in  FIG. 13 . 
     (Step S 905 ) Analysis on the stored data is performed to generate dynamic analysis data, and the dynamic analysis data is outputted. The dynamic analysis data may include, for instance, the number of substitutions and number of changes of the variable for each point. 
     For instance, dynamic analysis data of the type shown in  FIG. 14  is generated from the simulation results shown in  FIG. 13 . From the dynamic analysis data, it is clear that the number of substitutions for the points p 0  and p 2  is small. 
     (Step S 906 ) Allocation processing is performed. The dynamic analysis data is consulted during register allocation. 
     For instance, upon consulting the dynamic analysis data shown in  FIG. 14 , the points p 0 , p 2 , and p 3  may be allocated to a single register R 0001  and the points p 1 , p 4 , and p 5  may be allocated to a single register R 0002 , as shown in  FIG. 15 . 
     Here, the points p 0  and p 2  for which the number of substitutions is small, and, in addition, the point p 3  have been allocated to the register R 0001 . The additional allocation is used here because, as can be seen from the  FIG. 11 , data from the points p 3  and p 4  are to be stored simultaneously and so it is necessary to allocate one of the points p 3  and p 4  to the register R 0001 . 
     As shown in  FIG. 16 , an alternative is to allocate only the points p 0  and p 2  to the register R 0001  and to allocate the point p 3  to a new register R 0003 . In this case, although the power consumption of the register R 0001  is reduced effectively, the increase in the number of registers means that it is necessary to consider the increase in power consumption resulting from the increase in circuit scale. 
     Thus, in the present embodiment, a simulation is performed using data that is actually going to be processed with the designed logic circuit, and points for which the number of data substitutions or the number of changes to the stored value is small are grouped based on the results of the simulation and allocated to a register. Then, since the use of the clock supply stopping circuit is restricted to registers for which power consumption is lowered significantly by providing a gated clock is large, it is possible to design a logic circuit with lower power consumption while suppressing increases in circuit size. 
     In the above-described embodiment, it may look as if the simulation is being performed during operations of the high-level synthesis apparatus  110 . However, if the behavioral description  101  used in the high-level synthesis and the parameters match, the register information  103  will be the same. Hence, it is possible to obtain a plurality of dynamic analysis data  104  from the register information  103  and a plurality of simulation-use input data  102 , and obtain a plurality of differing circuit descriptions  105 . 
     In the above-described embodiment, the number of data substitutions or number of changes was detected from the results of the simulation. However, the register is physically generated bit by bit, and so the probability of each bit being “1” may be calculated and included in the dynamic analysis information.