Patent Publication Number: US-2023155096-A1

Title: Deep ultraviolet light-emitting diode

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS AND PRIORITY 
     This application is a continuation of International Application No. PCT/KR2021/009184, filed on 16 Jul. 2021, which claims priority to and the benefit of Korean Application No. 10-2020-0088594, filed on 17 Jul. 2020, and Korean Application No. 10-2021-0092721, filed on 15 Jul. 2021, the disclosures of which are hereby incorporated by reference for all purposes as if fully set forth herein. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to an inorganic semiconductor light emitting diode, and more particularly to a light emitting diode emitting deep UV light of 300 nm or less. 
     BACKGROUND ART 
     In general, a light emitting diode emitting UV light within a range of 200 nm to 300 nm can be used in various applications, including a sterilization device, a water or air purification device, a high-density optical recording device, and an excitation source for a bio-aerosol fluorescence detection system. 
     Unlike a near-UV light emitting diode or a blue light emitting diode, a light emitting diode that emits relatively deep UV light includes a well layer containing Al, such as AlGaN. Due to a composition of this gallium nitride-based semiconductor layer, a deep UV light emitting diode has a structure significantly different from that of the blue light emitting diode or the near UV light emitting diode. 
     In particular, the deep UV light emitting diode according to a prior art has a structure different from that of a general blue light emitting diode or near UV light emitting diode in a shape and a position of a mesa disposed on an n-type semiconductor layer. That is, the mesa is biased toward one side from a center of the n-type semiconductor layer, a p-bump is disposed on the mesa, and an n-bump is disposed near a side opposite to the one side to be spaced apart from the mesa. 
     Such a conventional UV light emitting diode generally has a disadvantage of low light output and high forward voltage. In particular, the deep UV light emitting diode achieves favorable internal quantum efficiency by improving a crystalline quality of the semiconductor layer, but light extraction efficiency is very low. The light extraction efficiency is reduced by total internal reflection and light loss in the interior. For example, a p-type GaN layer included for an-ohmic contact absorbs UV light generated in an active layer, and an n-ohmic contact layer adhered to the n-type semiconductor layer also absorbs UV light. 
     Furthermore, since it is difficult for the conventional UV light emitting diode to utilize light emitted to a side surface of the mesa, there is a tendency to reduce a total area of the side surface of the mesa as much as possible. That is, a width of the mesa is relatively wide. However, as the mesa width increases, a distance from the n-ohmic contact layer to a central region of the mesa increases, which is not favorable for current spreading, thereby increasing a forward voltage. Moreover, poor current spreading performance limits an increase in current density, thereby limiting a luminous intensity that can be achieved with individual light emitting diodes. 
     SUMMARY 
     Technical Problem 
     Exemplary embodiments of the present disclosure provide a deep UV light emitting diode having a novel structure that is configured to improve electrical characteristics and/or light output. 
     Exemplary embodiments of the present disclosure provide a deep UV light emitting diode that is configured to improve current spreading performance. 
     Technical Solution 
     A deep UV light emitting diode according to an exemplary embodiment of the present disclosure includes: a substrate; an n-type semiconductor layer disposed on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via holes; a p-ohmic contact layer contacting the p-type semiconductor layer; an n-pad metal layer electrically connected to the n-ohmic contact layers; a p-pad metal layer electrically connected to the p-ohmic contact layer; an n-bump electrically connected to the n-pad metal layer; and a p-bump electrically connected to the p-pad metal layer, in which the p-pad metal layer is formed to surround the n-pad metal layer. 
     A light emitting diode according to another exemplary embodiment of the present disclosure includes: a substrate; an n-type semiconductor layer disposed on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via holes; a p-ohmic contact layer contacting the p-type semiconductor layer; an n-bump electrically connected to the n-ohmic contact layers; and a p-bump electrically connected to the p-ohmic contact layer, in which the p-ohmic contact layer includes Ni/Rh. 
     A deep UV light emitting diode according to another exemplary embodiment of the present disclosure includes: a substrate; an n-type semiconductor layer disposed on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and including a groove exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the groove; a p-ohmic contact layer contacting the p-type semiconductor layer; an n-pad metal layer electrically connected to the n-ohmic contact layers; a p-pad metal layer electrically connected to the p-ohmic contact layer; an n-bump electrically connected to the n-pad metal layer; and a p-bump electrically connected to the p-pad metal layer. 
     Advantageous Effects 
     According to exemplary embodiments of the present disclosure, a deep UV light emitting diode that is configured to evenly spread current within a mesa may be provided by employing a plurality of via holes. Furthermore, a deep UV light emitting diode with improved light extraction efficiency may be provided by employing Ni/Rh as a p-type ohmic contact layer. In addition, since luminous intensities of individual light emitting diodes may be increased by increasing a current density injected into the light emitting diode, the number of light emitting diodes required to sterilize bacteria or viruses may be reduced, and a sterilization time may be reduced. 
     Advantages and features of the present disclosure will be discussed in detail in the detailed description or will become apparent from the detailed description. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG.  1 A  is a schematic plan view illustrating a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
         FIG.  1 B  is a schematic cross-sectional view taken along line A-A′ in  FIG.  1 A . 
         FIGS.  2 A,  3 A,  4 A,  5 A,  6 A,  7 A, and  8 A  are schematic plan views illustrating a method of manufacturing a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
         FIGS.  2 B,  3 B,  4 B,  5 B,  6 B,  7 B, and  8 B  are schematic cross-sectional views taken along line A-A′ of their corresponding plan views shown in  FIGS.  2 A,  3 A,  4 A,  5 A,  6 A,  7 A, and  8 A , respectively. 
         FIG.  9    is a diagram showing a light output distribution of a UV light emitting diode manufactured according to an exemplary embodiment of the present disclosure. 
         FIG.  10 A  is a cross-sectional SEM image showing an interface after depositing Ni/Au on a p-type contact layer and performing heat treatment. 
         FIG.  10 B  is a cross-sectional SEM image showing an interface after depositing Ni/Au on a p-type contact layer and performing heat treatment. 
         FIGS.  11 A,  11 B, and  11 C  are schematic plan views illustrating modified examples of via hole shapes of UV light emitting diodes according to exemplary embodiments of the present disclosure. 
         FIG.  12 A  is a schematic plan view illustrating a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
         FIG.  12 B  is a schematic cross-sectional view taken along line B-B′ of its corresponding plan view shown in  FIG.  12 A . 
         FIGS.  13 A,  14 A,  15 A,  16 A,  17 A,  18 A,  19 A, and  20 A  are schematic plan views illustrating a method of manufacturing a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
         FIGS.  13 B,  14 B,  15 B,  16 B,  17 B,  18 B,  19 B, and  20 B  are schematic cross-sectional views taken along line A-A′ of their corresponding plan views shown in  FIGS.  13 A,  14 A,  15 A,  16 A,  17 A,  18 A,  19 A, and  20 A , respectively. 
         FIG.  21    is a schematic plan view illustrating a modified example of a mesa of a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
         FIG.  22    is a schematic plan view illustrating another modified example of a mesa of a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
         FIG.  23 A  is a schematic plan view illustrating a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
         FIG.  23 B  is a schematic cross-sectional view taken along line C-C′ in  FIG.  23 A . 
         FIGS.  24 A,  25 A,  26 A,  27 A,  28 A,  29 A,  30 A, and  31 A  are schematic plan views illustrating a method of manufacturing a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
         FIGS.  24 B,  25 B,  26 B,  27 B,  28 B,  29 B,  30 B, and  31 B  are schematic cross-sectional views taken along line C-C′ of their corresponding plan views shown in  FIGS.  24 A,  25 A,  26 A,  27 A,  28 A,  29 A,  30 A, and  31 A , respectively. 
         FIG.  32    is a schematic plan view illustrating a modified example of a mesa of a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so as to fully convey the spirit of the present disclosure to those skilled in the art to which the present disclosure pertains. Accordingly, the inventive concepts are not limited to the embodiments disclosed herein and can also be implemented in different forms. In the drawings, widths, lengths, thicknesses, and the like of elements can be exaggerated for clarity and descriptive purposes. When an element or layer is referred to as being “disposed above” or “disposed on” another element or layer, it can be directly “disposed above” or “disposed on” the other element or layer or intervening elements or layers can be present. Throughout the specification, like reference numerals denote like elements having the same or similar functions. 
     Nitride-based semiconductor layers described below may be grown using generally known various methods, and may be grown using technology, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydration vapor phase epitaxy (HVPE), or the like. However, in exemplary embodiments described below, it is described that semiconductor layers are grown in a growth chamber using MOCVD. In a process of growing the nitride-based semiconductor layers, sources introduced into the growth chamber may be generally known sources, for example, TMGa, TEGa, or the like may be used as a Ga source, TMAl, TEAl, or the like may be used as an Al source, TMIn, TEIn, or the like may be used as an In source, and NH3 may be used as a N source. However, the inventive concepts are not limited thereto. 
     A deep UV light emitting diode according to an exemplary embodiment of the present disclosure includes: a substrate; an n-type semiconductor layer disposed on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via holes; a p-ohmic contact layer contacting the p-type semiconductor layer; an n-pad metal layer electrically connected to the n-ohmic contact layers; a p-pad metal layer electrically connected to the p-ohmic contact layer; an n-bump electrically connected to the n-pad metal layer; and a p-bump electrically connected to the p-pad metal layer, in which the p-pad metal layer is formed to surround the n-pad metal layer. 
     By forming the plurality of via holes inside the mesa, it is possible to uniformly spread current, and further, it is possible to prevent a non-emission region from being formed inside the mesa. Conventionally, when a width of the mesa is wide, a distance from the n-ohmic contact layer to the inside of the mesa increases to form the non-emission region. On the contrary, in the present application, the current inside the mesa may be evenly spread by disposing the plurality of via holes inside the mesa, and by forming the n-ohmic contact layers in the via holes. 
     In an exemplary embodiment, the via holes may be arranged in a honeycomb shape. Accordingly, the via holes may be spaced apart from one another at equal intervals, and thus, the current may be evenly spread. 
     Meanwhile, the via-holes may be spaced apart from an edge of the mesa by a distance greater than or equal to a distance between the via-holes. 
     The n-pad metal layer may cover the via holes. 
     The p-pad metal layer may be disposed between the via holes and the edge of the mesa. 
     The n-bump and the p-bump may be disposed within an upper region of the mesa. 
     Accordingly, light may be emitted through a side surface of the mesa. 
     The deep UV light emitting diode may further include a lower insulation layer covering the p-ohmic contact layer and the n-ohmic contact layer, in which the lower insulation layer has openings exposing the p-ohmic contact layer and the n-ohmic contact layer, and the n-pad metal layer and the p-pad metal layer may be electrically connected to the n-ohmic contact layer and the p-ohmic contact layer through the openings of the lower insulation layer, respectively. 
     An upper insulation layer covering the n- and p-pad metal layers may be further included, in which the upper insulation layer has openings exposing the n-pad metal layer and the p-pad metal layer, the n-bump and the p-bump may be disposed on the upper insulation layer, and may be electrically connected to the n-pad metal layer and the p-pad metal layer through the openings of the upper insulation layer, respectively. 
     In an embodiment, the opening exposing the n-pad metal layer is disposed near one edge of the mesa, and the opening exposing the p-pad metal layer is disposed near an opposite edge of the mesa. 
     In an exemplary embodiment, the p-type semiconductor layer may include a p-type GaN layer, and the p-type GaN layer may have a thickness of 200 nm or less. Furthermore, the p-ohmic contact layer may include Ni/Rh. 
     In an exemplary embodiment, the n-pad metal layer may include an Al layer. 
     A light emitting diode according to another exemplary embodiment of the present disclosure includes: a substrate; an n-type semiconductor layer disposed on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via holes; a p-ohmic contact layer contacting the p-type semiconductor layer; an n-bump electrically connected to the n-ohmic contact layers; and a p-bump electrically connected to the p-ohmic contact layer, in which the p-ohmic contact layer includes Ni/Rh. 
     The plurality of via holes may be spaced apart from one another at equal intervals, and may be arranged in a honeycomb shape. 
     Furthermore, the deep UV light emitting diode may further include a lower insulation layer covering the n-ohmic contact layers and the p-ohmic contact layer; and an n-pad metal layer and a p-pad metal layer disposed on the lower insulation layer, in which the lower insulation layer has openings exposing the n-ohmic contact layers and the p-ohmic contact layer, respectively, the n-pad metal layer and the p-pad metal layer may be electrically connected to the n-ohmic contact layers and the p-ohmic contact layer through the openings, respectively, and the n-bump and p-bump may be electrically connected to the n-pad metal layer and the p-pad metal layer, respectively. 
     The p-pad metal layer may surround the n-pad metal layer. 
     In addition, the opening exposing the p-ohmic contact layer may have a ring shape surrounding the via holes. 
     In an embodiment, the p-pad metal layer may be disposed within an upper portion of a region between the via holes and an edge of the mesa. Accordingly, the p-pad metal layer does not cover a side surface of the mesa. 
     The deep UV light emitting diode may further include an upper insulation layer including the n-pad metal layer and the p-pad metal layer, in which the upper insulation layer has openings exposing the n-pad metal layer and the p-pad metal layer, and the n-bump and the p-bump may be electrically connected to the n-pad metal layer and the p-pad metal layer through the openings of the upper insulation layer, respectively. 
     The lower insulation layer and the upper insulation layer may cover the side surface of the mesa. 
     Meanwhile, the opening exposing the n-pad metal layer may be disposed near one edge of the mesa, and the opening exposing the p-pad metal layer may be disposed near an opposite edge of the mesa. 
     The p-type semiconductor layer may include a p-type GaN layer, the p-type GaN layer may have a thickness of 200 nm or less, and the Ni/Rh may be in ohmic contact with the p-type GaN layer. 
     A deep UV light emitting diode according to another exemplary embodiment of the present disclosure includes: a substrate; an n-type semiconductor layer disposed on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and including a groove exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the groove; a p-ohmic contact layer contacting the p-type semiconductor layer; an n-pad metal layer electrically connected to the n-ohmic contact layers; a p-pad metal layer electrically connected to the p-ohmic contact layer; an n-bump electrically connected to the n-pad metal layer; and a p-bump electrically connected to the p-pad metal layer. 
     The deep UV light emitting diode may include an n capping layer covering the n-ohmic contact layers; and a p-capping layer covering the p-ohmic contact layer. 
     The groove extends in a longitudinal direction of the mesa, and a difference between a length of the mesa in the longitudinal direction and a length of the groove may be smaller than or equal to a width of each mesa region disposed on both sides of the groove. 
     A sum of areas of the mesa regions disposed on both sides of the groove may exceed ½ of a total area of the mesa. 
     Corners of one end of the mesa region disposed on both sides of the groove may have a curved shape. 
     Depressions may be formed at outer corners among the corners of one end of the mesa region disposed on both sides of the groove, respectively. 
     The groove may include a main groove extending in the longitudinal direction of the mesa; and a plurality of sub grooves extending in a direction perpendicular to the main groove. 
     The plurality of sub grooves may include grooves having different lengths and different widths. 
     The deep UV light emitting diode may have a symmetric structure with respect to a line passing through a center and parallel to the sub groove. 
     The deep UV light emitting diode may have an asymmetric structure with respect to the line passing through the center and parallel to the main groove. 
     Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. 
       FIG.  1 A  is a schematic plan view illustrating a UV light emitting diode according to an exemplary embodiment of the present disclosure, and  FIG.  1 B  is a schematic cross-sectional view taken along line A-A′ of its corresponding plan view shown in  FIG.  1 A . 
     Referring to  FIG.  1 A  and  FIG.  1 B , the UV light emitting diode according to the illustrated exemplary embodiment may include a substrate  21 , an n-type semiconductor layer  23 , an active layer  25 , a p-type semiconductor layer  27 , n-ohmic contact layers  31 , a p-ohmic contact layer  33 , a lower insulation layer  35 , an n-pad metal layer  37   a , a p-pad metal layer  37   b , an upper insulation layer  39 , an n-bump  41   a , and a p-bump  41   b.    
     The substrate  21  is not particularly limited as long as it is a substrate capable of growing a nitride-based semiconductor, and may include, for example, a heterogeneous substrate such as a sapphire substrate, a silicon substrate, a silicon carbide substrate, a spinel substrate, or the like, or may include a homogeneous substrate such as a gallium nitride substrate, an aluminum nitride substrate, or the like. 
     The n-type semiconductor layer  23  is disposed on the substrate  21 . The n-type semiconductor layer  23  may include, for example, an AlN buffer layer (about 3.79 μm) and an n-type AlGaN layer. The n-type AlGaN layer may include a lower n-type AlGaN layer (about 2.15 μm) with an Al molar ratio of 0.8 or more, an intermediate AlGaN layer (1.7 nm) with an Al molar ratio of 0.7 to 0.8, and an upper n-type AlGaN layer with a thickness of about 66.5 nm. The n-type semiconductor layer  23  is formed of a nitride-based semiconductor having a band gap higher than that of the active layer such that light generated in the active layer passes therethrough. When the gallium nitride-based semiconductor layer is grown on the sapphire substrate  21 , the n-type semiconductor layer  23  may generally include a plurality of layers so as to improve a crystalline quality. 
     A mesa M is disposed on a partial region of the n-type semiconductor layer  23 . The mesa M includes the active layer  25  and the p-type semiconductor layer  27 . In general, after the n-type semiconductor layer  23 , the active layer  25 , and the p-type semiconductor layer  27  are sequentially grown, the mesa M is formed by patterning the p-type semiconductor layer  27  and the active layer  25  through a mesa etching process. 
     The active layer  25  may be a single quantum well structure or a multi-quantum well structure including a well layer and a barrier layer. The well layer may be formed of AlGaN or AlInGaN, and the barrier layer may be formed of AlGaN or AlInGaN having a band gap wider than the well layer. For example, each well layer may be formed of AlGaN having an Al molar ratio of about 0.5 with a thickness of about 3.1 nm, and each barrier layer may be formed of AlGaN having an Al molar ratio of 0.7 or more with a thickness of about 9 nm or more. In particular, a first barrier layer may be formed to be thicker than other barrier layers with a thickness of 12 nm or more. Meanwhile, AlGaN layers having an Al molar ratio of 0.7 to 0.8 in contact with atop and a bottom of each well layer may be disposed in a thickness of about 1 nm, respectively. However, an Al molar ratio of the AlGaN layer in contact with a last well layer may be 0.8 or more in consideration of the contact with an electron blocking layer. 
     Meanwhile, the p-type semiconductor layer  27  may include an electron blocking layer and a p-type GaN contact layer. The electron blocking layer prevents electrons from overflowing from the active layer to the p-type semiconductor layer, thereby improving a recombination rate of electrons and holes. The electron blocking layer may be formed of, for example, p-type AlGaN having an Al molar ratio of about 0.8, and may have a thickness of, for example, 55 nm. Meanwhile, the p-type GaN contact layer may be formed to have a thickness of about 300 nm. The electron blocking layer may be omitted. 
     Meanwhile, the p-type GaN contact layer is used for an ohmic contact. The p-type GaN contact layer may absorb light generated in the active layer  25 . A prior art does not solve a drawback of UV absorption by the p-type GaN contact layer. The present invention reduces light absorption of the p-type GaN contact layer by reducing the thickness of the p-type GaN contact layer. In the prior art, the p-type GaN contact layer is generally formed to have a thickness of more than 300 nm, but in the illustrated exemplary embodiment, it is formed to have a thickness of 200 nm or less, further 150 nm or less. As such, light absorption by the p-type GaN contact layer may be reduced to improve light extraction efficiency. 
     The mesa M may have a rectangular shape elongated in one direction, and includes a plurality of via holes  30   h  exposing the n-type semiconductor layer  23 . Each of the via holes  30   h  may have a concentric circle shape, and may be arranged at substantially equal intervals to one another in a region of the mesa M. As well illustrated in  FIG.  2 A , the via-holes  30   h  may be arranged in a honeycomb shape, and thus, it is possible to make intervals between the via-holes  30   h  uniform. 
     The via holes  30   h  may have a mirror symmetrical structure with respect to a plane passing in a short axis direction of the mesa M. This mirror symmetrical structure assists to spread currents in the mesa M to improve a radiation efficiency. 
     Meanwhile, the n-ohmic contact layers  31  are disposed on the n-type semiconductor layer  23  exposed to the via holes  30   h . The n-ohmic contact layers  31  may be formed by depositing a plurality of metal layers, and thereafter, by alloying the metal layers through a rapid thermal alloy (RTA) process. For example, the n-ohmic contact layers  31  may be alloyed through the RTA process after sequentially depositing Cr/Ti/Al/Ti/Au. Accordingly, the n-ohmic contact layers  31  become alloy layers containing Cr, Ti, Al, and Au. 
     The n-ohmic contact layers  31  are disposed in the via holes  30   h , respectively. The n-ohmic contact layers  31  are spaced apart from the active layer  25  and the p-type semiconductor layer  27  in the via holes  30   h . In a deep UV light emitting diode according to the prior art, an n-ohmic contact layer is generally formed to surround the mesa M along a perimeter of the mesa M, but in the illustrated exemplary embodiment, the n-ohmic contact layer is not disposed around the mesa M. Accordingly, it is possible to prevent light emitted through a side surface of the mesa M from being blocked by the n-ohmic contact layer  31  or the like. 
     The p-ohmic contact layer  33  is disposed on the p-type semiconductor layer  27  to be in ohmic contact with the p-type semiconductor layer  27 . The p-ohmic contact layer  33  may be formed through, for example, the RTA process after depositing Ni/Rh. The p-ohmic contact layer  33  is in ohmic contact with the p-type semiconductor layer  27 , and covers most of an upper region of the mesa M, for example, 80% or more. Rh has a higher reflectivity to UV rays than Au, which is advantageous for improving light extraction efficiency. In this specification, since the thickness of the p-type GaN contact layer is reduced to decrease light absorption by the p-type GaN contact layer, so as to reflect light passing through the p-type semiconductor layer  27 , favorable reflection performance of the p-ohmic contact layer  33  is required. 
     The lower insulation layer  35  covers the mesa M, and covers the p-ohmic contact layer  33  and the n-ohmic contact layers  31 . The lower insulation layer  35  also covers the exposed n-type semiconductor layer  23  around the mesa M and in the via holes  30   h . Meanwhile, the lower insulation layer  35  has openings  35   a  for allowing electrical connection to the n-ohmic contact layers  31  and openings  35   b  for allowing electrical connection to the p-ohmic contact layer  33 . The opening  35   b  may be formed so as to surround all of the via holes  30   h  in a ring shape. 
     The lower insulation layer  35  may be formed of, for example, SiO 2 , without being limited thereto, or may be formed as a distributed Bragg reflector. 
     Meanwhile, the n-pad metal layer  37   a  and the p-pad metal layer  37   b  are disposed on the lower insulation layer  35 . The n-pad metal layer  37   a  and the p-pad metal layer  37   b  may be formed together in a same process as a same metal layer and disposed on a same level, that is, on the lower insulation layer  35 . The n- and p-pad metal layers  37   a  and  37   b  may include, for example, Al layers. 
     The n-pad metal layer  37   a  is electrically connected to the n-ohmic contact layers  31  through the openings  35   a  of the lower insulation layer  35 . The n-ohmic contact layers  31  are electrically connected to one another by the n-pad metal layer  37   a . The n-pad metal layer  37   a  may be disposed within the region of the mesa M. The n-pad metal layer  37   a  may function as a reflection layer (second reflection layer) that reflects light emitted through the side surface of the mesa M in the via hole  30   h , thereby improving a light efficiency of the light emitting diode. 
     Meanwhile, the p-pad metal layer  37   b  may be electrically connected to the p-ohmic contact layer  33  through the opening  35   b  of the lower insulation layer  35 . The p-pad metal layer  37   b  may cover the opening  35   b , and may surround the n-pad metal layer  37   a  in a ring shape. The p-pad metal layer  37   b  may be defined in the upper region of the mesa M such that the p-pad metal layer does not cover side surfaces of the mesa M. 
     The upper insulation layer  39  covers the n-pad metal layer  37   a  and the p-pad metal layer  37   b . Meanwhile, the upper insulation layer  39  has openings  39   a  exposing the n-pad metal layer  37   a  and has openings  39   b  over the mesa M exposing the p-pad metal layer  37   b . The opening  39   a  may expose the n-pad metal layer  37   a  near one edge of the mesa M, and the opening  39   b  may expose the p-pad metal layer  37   b  near an opposite edge of the mesa M. 
     A plurality of openings  39   a  may be arranged, without being limited thereto, or one opening  39   a  may be arranged. In addition, although the opening  39   b  is illustrated as being continuously formed in a C shape in the drawing, the plurality of openings  39   b  may be disposed apart from one another. The upper insulation layer  39  may be formed of, for example, silicon nitride or silicon oxide. 
     The n-bump  41   a  and the p-bump  41   b  are placed on the upper insulation layer  39 . The n-bump  41   a  covers the openings  39   a  and is connected to the n-pad metal layer  37   a  exposed through the openings  39   a . The n-bump  41   a  is electrically connected to the n-type semiconductor layer  23  through the n-pad metal layer  37   a  and the n-ohmic contact layer  31 . Outer edges of the n-bump  41   a  and the p-bump  41   b  may be disposed over the mesa M so as not to cover the side surface of the mesa M. 
     The p-bump  41   b  covers the opening  39   b  and is connected to the p-pad metal layer  37   b  exposed through the opening  39   b . The p-bump  41   b  is electrically connected to the p-type semiconductor layer  27  through the p-pad metal layer  37   b  and the p-ohmic contact layer  33 . 
     The n-bump  41   a  and the p-bump  41   b  may be formed of, for example, Ti/Au/Cr/Au. As shown in  FIG.  1   , the n-bump  41   a  and the p-bump  41   b  may be disposed to face each other, and may occupy about ⅓ of an area of the mesa M, respectively. By making the areas of the n-bump  41   a  and the p-bump  41   b  relatively wide, heat generated in the light emitting diode may be easily dissipated, thereby improving a performance of the light emitting diode. 
     Furthermore, the openings  39   a  and  39   b  are covered by the n-bump  41   a  and the p-bump  41   b , and thus, moisture or solder from the outside may be prevented from infiltrating into a device through the openings  39   a  and  39   b , thereby improving a reliability thereof. 
     Meanwhile, although not shown, an anti-reflection layer may be disposed on a light exiting surface of the substrate  21 . The anti-reflection layer may be formed of a transparent insulation layer such as SiO 2  to have a thickness that is an integer multiple of ¼ of a wavelength of ultraviolet rays, for example. Alternatively, a bandpass filter in which layers having different refractive indices are repeatedly stacked may be used as the anti-reflection layer. 
       FIGS.  2 A,  3 A,  4 A,  5 A,  6 A,  7 A, and  8 A  are schematic plan views illustrating a method of manufacturing a UV light emitting diode according to an exemplary embodiment of the present disclosure, and  FIGS.  2 B,  3 B,  4 B,  5 B,  6 B,  7 B, and  8 B  are schematic cross-sectional views taken along line A-A′ of their corresponding plan views shown in  FIGS.  2 A,  3 A,  4 A,  5 A,  6 A,  7 A, and  8 A , respectively. 
     Referring to  FIGS.  2 A and  2 B , first, an n-type semiconductor layer  23 , an active layer  25 , and a p-type semiconductor layer  27  are grown on a substrate  21 . 
     Since the substrate  21 , the n-type semiconductor layer  23 , the active layer  25 , and the p-type semiconductor layer  27  are identical to those described above, detailed descriptions thereof will be omitted to avoid redundancy. However, the p-type semiconductor layer  27  may include a semiconductor layer having a band gap smaller than a well layer of the active layer  25 , for example, a GaN layer. In particular, a p-type GaN layer may be used for an ohmic contact. The semiconductor layer having the band gap smaller than the well layer is controlled to have a thickness of 200 nm or less, furthermore, 150 nm or less. 
     Meanwhile, a mesa M is formed by patterning the p-type semiconductor layer  27  and the active layer  25 . The mesa M may have a generally elongated rectangular shape, but the inventive concepts are not limited to a specific shape. As the mesa M is formed, the n-type semiconductor layer  23  may be exposed along a perimeter of the mesa M. Also, a plurality of via holes  30   h  are formed in a mesa M region. The via holes  30   h  expose the n-type semiconductor layer  23 . The via holes  30   h  may be spaced apart from one another at substantially equal intervals, and may be arranged, for example, in a honeycomb structure. Furthermore, the via-holes  30   h  may be spaced apart from an edge of the mesa M by more than the interval between the via-holes  30   h.    
     Referring to  FIG.  3 A  and  FIG.  3 B , n-ohmic contact layers  31  are formed on bottom surfaces of the via holes  30   h . The n-ohmic contact layers  31  may be alloyed through an RTA process, for example, after sequentially depositing Cr/Ti/Al/Ti/Au. For example, the n-ohmic contact layer  31  may be alloyed through the RTA process at about 965° C. for 30 seconds. 
     Referring to  FIG.  4 A  and  FIG.  4 B , after the n-ohmic contact layer  31  is formed, a p-ohmic contact layer  33  is formed on the mesa M. The p-ohmic contact layer  33  is in ohmic contact with the p-type semiconductor layer  27 . In particular, the p-ohmic contact layer  33  may be in ohmic contact with the p-type GaN layer. 
     The p-ohmic contact layer  33  may include a reflection metal layer such as Au or Rh. For example, after depositing Ni/Au or Ni/Rh, it may be alloyed through the RTA process. Ni/Au may be heat-treated, for example, at 590° C. for 80 seconds. In contrast, Ni/Rh may be heat-treated at a relatively lower temperature for a longer time, for example, may be heat-treated at 500° C. for 5 minutes. Rh has a higher reflectivity to UV rays than Au, and thus, the light extraction efficiency may be further increased. 
     Furthermore, Ni/Rh is advantageous compared to Ni/Au because an interface between the p-type contact layer  27  and the p-ohmic contact layer  33  is formed smoothly to exhibit stable ohmic resistance characteristics. In addition, since the present invention reduces light absorption of the p-type contact layer  27  by reducing a thickness of the p-type GaN contact layer, an amount of light reflected by the p-ohmic contact layer  33  is increased. Accordingly, the light extraction efficiency may be improved by using Rh having a relatively high reflectivity. 
     Referring to  FIG.  5 A  and  FIG.  5 B , a lower insulation layer  35  is formed on the mesa M. The lower insulation layer  35  covers side surfaces and an upper surface of the mesa M. The lower insulation layer  35  covers the n-ohmic contact layer  31  and the p-ohmic contact layer  33 . Meanwhile, the lower insulation layer  35  has openings  35   a  exposing the n-ohmic contact layers  31  and openings  35   b  exposing the p-ohmic contact layer  33 . 
     The opening  35   b  of the lower insulation layer  35  may be formed in a ring shape along an entire perimeter of the via holes  30   h . However, the inventive concepts are not limited thereto, and a plurality of openings may be formed so as to expose the p-ohmic contact layer  33 . For example, a portion of the ring-shaped opening  35   b  close to the via holes  30   h  may be covered with the lower insulation layer  35 , and openings may be formed in portions thereof relatively far from the via holes  30   h.    
     Referring to  FIG.  6 A  and  FIG.  6 B , an n-pad metal layer  37   a  and a p-pad metal layer  37   b  are formed on the lower insulation layer  35 . The n-pad metal layer  37   a  may be formed so as to cover the via-holes  30   h , and may be electrically connected to the n-ohmic contact layers  31  in the via-holes  30   h . The n-pad metal layer  37   a  may also cover inner walls of the via holes  30   h.    
     The p pad metal layer  37   b  may cover the opening  35   b , and may be electrically connected to the p-ohmic contact layer  33  exposed to the opening  35   b . The p-pad metal layer  37   b  may be formed in a ring shape so as to surround the n-pad metal layer  37   a . The p-pad metal layer  37   b  may be formed so as to cover the side surface of the mesa M, or may be formed to be limited in a region over the mesa M so as not to block light emitted to the side surface of the mesa M. 
     Referring to  FIG.  7 A  and  FIG.  7 B , an upper insulation layer  39  is formed on the n-pad metal layer  37   a  and the p-pad metal layer  37   b . The upper insulation layer  39  may cover the n-pad metal layer  37   a  and the p-pad metal layer  37   b  and may also cover the side surface of the mesa M. 
     Meanwhile, the upper insulation layer  39  has openings  39   a  and  39   b  exposing the n-pad metal layer  37   a  and the p-pad metal layer  37   b . The openings  39   a  expose the n-pad metal layer  37   a , and the openings  39   b  expose the p-pad metal layer  37   b . The openings  39   a  may be formed near one edge of the mesa M, and the opening  39   b  may be formed near an opposite edge of the mesa M to face the openings  39   a.    
     Referring to  FIG.  8 A  and  FIG.  8 B , an n-bump  41   a  and a p-bump  41   b  are formed on the upper insulation layer  39 . The n-bump  41   a  is electrically connected to the n-pad metal layer  37   a  through the openings  39   a , and the p-bump  41   b  is electrically connected to the p-pad metal layer  37   b  through the opening  39   b.    
     The n-bump  41   a  and p-bump  41   b  may partially cover the side surface of the mesa M, respectively, but may be formed so as to be limited a region over the mesa M. 
     According to the illustrated exemplary embodiment, current may be uniformly spread over an entire region of the mesa M by forming the via holes  30   h  in the mesa M region and forming the n-ohmic contact layers  31 . In addition, the light extraction efficiency may be improved by reducing the thickness of the p-type GaN contact layer that absorbs light generated in the active layer  25  and by using Ni/Rh as the p-ohmic contact layer  33 . 
       FIG.  9    is a diagram showing a light output distribution of the ultraviolet light emitting diode manufactured according to an exemplary embodiment of the present disclosure. Herein, the closer to red, the stronger ultraviolet light is emitted, and the closer to blue, the weaker light is emitted. Herein, an area of the light emitting diode was about 950 um×600 um, and a current of 100 mA was applied. 
     Referring to  FIG.  9   , it can be seen that light is emitted over almost an entire region of the mesa M, except for regions where the via holes  30   h  are disposed. Since current spreading is favorable, a luminous intensity of the light emitting diode may be further improved by increasing a current density. 
       FIGS.  10 A and  10 B  are cross-sectional SEM images showing an interface after depositing Ni/Au and Ni/Rh on a p-type contact layer and performing heat treatment, respectively. 
     As shown in  FIG.  10 A , when Ni/Au was used, a large number of voids were observed after an annealing process, and a thickness of the Ni/Au layer was non-uniform. On the contrary, as shown in  FIG.  10 B , when Ni/Rh was used, a thickness of an ohmic contact layer is substantially uniform even after the annealing process, and no voids are observed. 
     In addition, as a result of comparing a light emitting diode using Ni/Rh and a light emitting diode using Ni/Au as a p-ohmic contact layer in a same structured light emitting diode, the light emitting diode using the Ni/Rh showed a relatively small forward voltage (Vf), and showed an improvement in light output of about 6%. 
       FIGS.  11 A,  11 B, and  11 C  are schematic plan views illustrating modified examples of via hole shapes of UV light emitting diodes according to exemplary embodiments of the present disclosure. 
     In the above embodiments, the via hole  30   h  has been illustrated and described as having a circular shape, but the shape of the via hole is not limited to the circular shape. As shown in  FIG.  11 A , a via hole  30   h ′ may have a cross shape modified by forming depressions  30   hc  in the circular shape. The depressions  30   hc  may be formed in four parts at equal intervals, but the inventive concepts are not limited thereto. The via holes  30   h ′ may be disposed such that a convex portion of one via hole  30   h ′ faces between the depressions of two adjacent via holes  30   h ′. Furthermore, three via-holes  30   h ′ may be disposed at vertices of equilateral triangles. 
     Meanwhile, as shown in  FIG.  11 B , a via hole  30   h ″ disposed near an edge of a mesa M may have a shape modified from the cross shape. That is, the via hole  30   h ″ may include a linear portion parallel to the edge of the mesa M. The via hole  30   h ″ may be a region corresponding to ½ of the via hole  30   h ′ shown in  FIG.  11 A . Accordingly, the via hole  30   h ″ may have only two depressions. 
     Meanwhile, as shown in  FIG.  11 C , a via hole  30   h ′″ may have a polygonal shape. The via hole  30   h ′″ may include a planar sidewall, and adjacent via holes  30   h ′″ may face the planar sidewall as indicated by a dotted line. 
     Although via-holes of various shapes are shown and described in the illustrated exemplary embodiment, the inventive concepts are not limited to the shapes of these via-holes  30   h ,  30   h ′,  30   h ″, and  30   h ′″, and they may have other various shapes. The shape and the size of the via hole  30   h  affect the size of the ohmic contact region or the size of the light emitting region. Accordingly, the shape of the via hole  30   h  may be variously modified so as to adjust a magnitude of a radiation intensity. 
       FIG.  12 A  is a schematic plan view illustrating a UV light emitting diode according to an exemplary embodiment of the present disclosure, and  FIG.  12 B  is a schematic cross-sectional view taken along line B-B′ of its corresponding plan view shown in  FIG.  12 A . 
     Referring to  FIG.  12 A  and  FIG.  12 B , the UV light emitting diode according to the illustrated exemplary embodiment may include a substrate  121 , an n-type semiconductor layer  123 , an active layer  125 , a p-type semiconductor layer  127 , and n-ohmic contact layers  131   a  and  131   b , a p-ohmic contact layer  133 , an n-capping layer  134   a , a p-capping layer  134   b , a lower insulation layer  135 , an n-pad metal layer  137   a , a p-pad metal layer  137   b , an upper insulation layer  139 , an n-bump  141   a , and a p-bump  141   b.    
     Since the substrate  121  is similar to the substrate  21  described with reference to  FIGS.  1 A and  1   , a detailed description thereof will be omitted to avoid redundancy. The n-type semiconductor layer  123  is disposed on the substrate  121 . The n-type semiconductor layer  123  is substantially similar to the n-type semiconductor layer  23  described with reference to  FIGS.  1 A and  1 B . However, edges of an n-type semiconductor layer  123  may be disposed inside a region surrounded by edges of the substrate  121 , and thus, an upper surface of the substrate  121  may be exposed along the edges of the n-type semiconductor layer  123 . 
     A mesa M is disposed on a partial region of the n-type semiconductor layer  123 . The mesa M includes the active layer  125  and the p-type semiconductor layer  127 . In general, the n-type semiconductor layer  123 , the active layer  125 , and the p-type semiconductor layer  127  are sequentially grown, and thereafter, the mesa M is formed by patterning the p-type semiconductor layer  127  and the active layer  125  through a mesa etching process. 
     Since a stacked structure of the active layer  125  and the p-type semiconductor layer  127  is similar to that described with reference to  FIGS.  1 A and  1   , a detailed description thereof will be omitted to avoid redundancy. 
     The mesa M may have a rectangular external shape elongated in one direction, and includes a groove  130   g  exposing the n-type semiconductor layer  123 . The groove  130   g  may extend along a longitudinal direction of the mesa M. As shown in  FIG.  12 A , the groove  130   g  may extend from one edge of the mesa M toward an opposite edge thereof along the longitudinal direction of the mesa M. A mesa region is disposed on both sides of the groove  130   g  by the groove  130   g . A length of the groove  130   g  exceeds ½ of a length of the mesa M. In other words, the length of the groove  130   g  is greater than a distance between an inner end of the groove  130   g  and the opposite edge of the mesa M. Furthermore, the distance between the inner end of the groove  130   g  and the opposite edge of the mesa M may be smaller than a width of the mesa region disposed on both sides of the groove  130   g.    
     The groove  130   g  may have a linear shape, and the mesa M may have a symmetrical structure with respect to a straight line passing through a center of the light emitting diode and parallel to the groove  130   g.    
     Meanwhile, corners of the mesa M may have curved shapes. The edge of the mesa M may include a straight region and curved regions disposed on both sides thereof. By forming the corners of the mesa M to be curved, it is possible to prevent light from being condensed at the corner portion and thereby being lost due to light absorption. 
     Meanwhile, the n-ohmic contact layer  131   a  is disposed on the n-type semiconductor layer  123  exposed by the groove  130   g . The n-ohmic contact layer  131   b  is disposed on the n-type semiconductor layer  123  exposed along a perimeter of the mesa M. The n-ohmic contact layer  131   a  may be connected to the n-ohmic contact layer  131   b , but the inventive concepts are not limited thereto. The n-ohmic contact layers  131   a  and  131   b  may be spaced apart from the mesa M to surround the mesa M. 
     Materials and methods of forming the n-ohmic contact layers  131   a  and  131   b  are similar to those of forming the n-ohmic contact layers  31  described with reference to  FIGS.  1 A and  1 B , and thus, detailed descriptions thereof will be omitted to avoid redundancy. 
     The p-ohmic contact layer  133  is disposed on the p-type semiconductor layer  127  to be in ohmic contact with the p-type semiconductor layer  127 . The p-ohmic contact layer  133  may be formed using, for example, Ni/Rh or Ni/Au. The p-ohmic contact layer  133  is in ohmic contact with the p-type semiconductor layer  127  and covers most of a region over the mesa M, for example, 80% or more. 
     The n-capping layer  134   a  may cover upper surfaces and side surfaces of the n-ohmic contact layers  131   a  and  131   b . The p-capping layer  134   b  may cover the upper surfaces and side surfaces of the p-ohmic contact layer  133 . The n-capping layer  134   a  and the p-capping layer  134   b  prevent the n-ohmic contact layers  131   a  and  131   b  and the p-ohmic contact layer  133  from being damaged by etching, oxidation, or the like, respectively. The n-capping layer  134   a  and the p-capping layer  134   b  may be formed of a same metal in a same process. For example, the n-capping layer  134   a  and the p-capping layer  134   b  may be formed of Ti/Au/Ti. 
     The lower insulation layer  135  covers the mesa M, and covers the n-capping layer  134   a  and the p-capping layer  134   b . The lower insulation layer  135  also covers the n-type semiconductor layer  123  exposed around the mesa M and in the groove  130   g . Furthermore, the lower insulation layer  135  may cover a portion of the substrate  121  exposed around the n-type semiconductor layer  123 . Meanwhile, the lower insulation layer  135  has openings  135   a  for allowing electrical connection to the n-ohmic contact layers  131   a  and  131   b  and openings  135   b  for allowing electrical connection to the p-ohmic contact layer  133 . The opening  135   a  may have a shape similar to those of the n-ohmic contact layers  131   a  and  131   b  or the n-capping layer  134   a . That is, the opening  135   a  surrounds the mesa M and also extends into the groove  130   g . A width of the opening  135   a  may be smaller than that of the n-capping layer  134   a , and thus, the n-type semiconductor layer  123  may not be exposed through the opening  135   a . Meanwhile, the opening  135   b  is disposed in the region over the mesa M, and exposes the p-capping layer  134   b . A plurality of openings  135   b  may be disposed on the p-capping layer  134   b . In particular, the openings may be symmetrically disposed on both sides of the groove  130   g.    
     The lower insulation layer  135  may be formed of, for example, SiO2, without being limited thereto, and may be formed as a distributed Bragg reflector. In particular, the lower insulation layer  135  may be formed so as to constitute an omni-directional reflector (ODR). For example, the lower insulation layer  135  may be formed of about 10,000 Å of SiO2. 
     Meanwhile, the n-pad metal layer  137   a  and the p-pad metal layer  137   b  are disposed on the lower insulation layer  135 . The n-pad metal layer  137   a  and the p-pad metal layer  137   b  may be formed together in a same process with a same metal layer and disposed on a same level, that is, on the lower insulation layer  135 . The n and p-pad metal layers  137   a  and  137   b  may include, for example, an Al layer. 
     The n-pad metal layer  137   a  is electrically connected to the n-ohmic contact layers  131   a  and  131   b  through the opening  135   a  of the lower insulation layer  135 . The n-pad metal layer  137   a  may directly contact the n-capping layer  134   a  through the opening  135   a  of the lower insulation layer  135 . The n-pad metal layer  137   a  may cover most region of the mesa M, and may also cover a region around the mesa M. The n-pad metal layer  137   a  may form the ODR together with the lower insulation layer  135 . 
     Meanwhile, the p-pad metal layer  137   b  may be electrically connected to the p-ohmic contact layer  133  through the opening  135   b  of the lower insulation layer  135 . The p-pad metal layers  137   b  may cover each of the openings  135   b . Each of the p-pad metal layers  137   b  may be surrounded by the n-pad metal layer  137   a . The p-pad metal layers  37   b  may be limited in the region over the mesa M. In the illustrated exemplary embodiment, all side surfaces of the mesa M are covered with the n-pad metal layer  137   a . Accordingly, it is possible to prevent light loss from occurring at the side surfaces of the mesa M. 
     The upper insulation layer  139  covers the n-pad metal layer  137   a  and the p-pad metal layer  137   b . However, the upper insulation layer  139  may have openings  139   a  exposing the n-pad metal layer  137   a  and openings  139   b  exposing the p-pad metal layer  137   b . The opening  139   a  may expose the n-pad metal layer  137   a  near one edge of the mesa M, and the openings  139   b  may expose the p-pad metal layer  137   b  near the opposite edge of the mesa M. The openings  139   a  and  139   b  may be symmetrically disposed with respect to a line passing through the groove  130   g , but the inventive concepts are not limited thereto. 
     The upper insulation layer  139  may be formed of, for example, silicon nitride or silicon oxide. 
     The n-bump  141   a  and the p-bump  141   b  are disposed on the upper insulation layer  139 . The n-bump  141   a  covers the openings  139   a  and is connected to the n-pad metal layer  137   a  exposed through the openings  139   a . The n-bump  141   a  is electrically connected to the n-type semiconductor layer  123  through the n-pad metal layer  137   a  and the n-ohmic contact layers  131   a  and  131   b . The n-bump  141   a  and the p-bump  141   b  may partially cover the side surfaces of the mesa M. 
     The p-bump  141   b  covers the openings  139   b  and is connected to the p-pad metal layer  137   b  exposed through the openings  139   b . The p-bump  141   b  is electrically connected to the p-type semiconductor layer  127  through the p-pad metal layer  137   b  and the p-ohmic contact layer  133 . 
     The n-bump  141   a  and p-bump  141   b  may include Ti/Au, and may be formed of, for example, Ti/Au/Cr/Au or Ti/Ni/Ti/Ni/TiNi/Ti/Au. As shown in  FIG.  12 A , the n-bump  141   a  and the p-bump  141   b  may be disposed opposite each other, and may occupy about ⅓ of an area of the mesa M, respectively. By making the areas of the n-bump  141   a  and the p-bump  141   b  relatively wide, heat generated in the light emitting diode may be easily dissipated, thereby improving a performance of the light emitting diode. 
     Furthermore, the openings  139   a  and  139   b  are covered by the n-bump  141   a  and the p-bump  141   b , and thus, moisture or solder from the outside may be prevented from infiltrating into the openings  139   a  and  139   b , thereby improving reliability. 
     Meanwhile, although not shown, an anti-reflection layer may be disposed on a light exiting surface of the substrate  121 . The anti-reflection layer may be formed of a transparent insulation layer such as SiO2 to have a thickness that is an integer multiple of ¼ of a wavelength of ultraviolet rays, for example. Alternatively, a bandpass filter in which layers having different refractive indices are repeatedly stacked may be used as the anti-reflection layer. 
       FIGS.  13 A,  14 A,  15 A,  16 A,  17 A,  18 A,  19 A, and  20 A  are schematic plan views illustrating a method of manufacturing a UV light emitting diode according to an exemplary embodiment of the present disclosure, and  FIGS.  13 B,  14 B,  15 B,  16 B,  17 B,  18 B,  19 B, and  20 B  are schematic cross-sectional views taken along line A-A′ of their corresponding plan views shown in  FIGS.  13 A,  14 A,  15 A,  16 A,  17 A,  18 A,  19 A, and  20 A , respectively. 
     Referring to  FIG.  13 A  and  FIG.  13 B , first, an n-type semiconductor layer  123 , an active layer  125 , and an p-type semiconductor layer  127  are grown on a substrate  121 . 
     Since the substrate  121 , the n-type semiconductor layer  123 , the active layer  125 , and the p-type semiconductor layer  127  are identical to those described above, detailed descriptions thereof will be omitted to avoid redundancy. 
     Meanwhile, a mesa M is formed by patterning the p-type semiconductor layer  127  and the active layer  125 . The mesa M may have a generally elongated rectangular shape, but the inventive concepts are not limited to a specific shape. As the mesa M is formed, the n-type semiconductor layer  123  may be exposed along a perimeter of the mesa M. In addition, a groove  130   g  is formed in a mesa M region. The groove  130   g  may extend from one edge toward an opposite edge along a longitudinal direction of the mesa M. An inner end of the groove  130   g  may be disposed near the opposite edge. The mesa regions disposed on both sides of the groove  130   g  may be identical to one another, and a width of each of the mesa regions may be greater than or equal to a distance between the inner end of the groove  130   g  and the opposite edge of the mesa M. 
     Referring to  FIG.  14 A  and  FIG.  14 B , n-ohmic contact layers  131   a  and  131   b  are formed on the n-type semiconductor layer  123 . The n-ohmic contact layers  131   a  and  131   b  may be formed by, for example, sequentially depositing Cr/Ti/Al/Ti/Au, and thereafter being alloyed using an RTA process. For example, the n-ohmic contact layers  131   a  and  131   b  may be alloyed through the RTA process at about 965° C. for 30 seconds. The n-ohmic contact layer  131   a  is formed on the n-type semiconductor layer  123  exposed by the groove  130   g , and the n-ohmic contact layer  131   b  is formed on the n-type semiconductor layer  123  exposed around the mesa M. The n-ohmic contact layer  131   a  may extend from the n-ohmic contact layer  131   b . By continuously forming the n-ohmic contact layer  131   a  and the n-ohmic contact layer  131   b , current spreading may be assisted. However, the inventive concepts are not limited thereto, and the n-ohmic contact layer  131   a  may be spaced apart from the n-ohmic contact layer  131   b.    
     Referring to  FIG.  15 A  and  FIG.  15 B , after the n-ohmic contact layers  131   a  and  131   b  are formed, a p-ohmic contact layer  133  is formed on the mesa M. The p-ohmic contact layer  133  is in ohmic contact with the p-type semiconductor layer  127 . In particular, the p-ohmic contact layer  133  may be in ohmic contact with a p-type GaN layer. 
     The p-ohmic contact layer  133  may include a reflection metal layer such as Au or Rh. For example, after depositing Ni/Au or Ni/Rh, it may be alloyed through the RTA process. 
     Referring to  FIG.  16 A  and  FIG.  16 B , an isolation process for dividing the n-type semiconductor layer  123  is carried out. That is, the n-type semiconductor layer  123  between adjacent light emitting diode regions is removed to expose an upper surface of the substrate  121 . By adding the isolation process, singularization of the light emitting diodes may be aided. 
     Referring to  FIG.  17 A  and  FIG.  17 B , an n-capping layer  134   a  and a p-capping layer  134   b  are formed. The n-capping layer  134   a  covers upper surfaces and side surfaces of the n-type ohmic contact layers  131   a  and  131   b , and the p-capping layer  134   b  covers upper and side surfaces of the p-type ohmic contact layer  133 . The n-capping layer  134   a  and the p-capping layer  134   b  may be formed of, for example, Ti/Au/Ti. 
     Referring to  FIG.  18 A  and  FIG.  18 B , a lower insulation layer  135  covering the mesa M is formed. The lower insulation layer  135  covers side surfaces and an upper surface of the mesa M. The lower insulation layer  135  also covers the n-capping layer  134   a  and the p-capping layer  134   b . The lower insulation layer  135  may cover a side surface of the n-type semiconductor layer  123 , and may partially cover the substrate  121  exposed around the n-type semiconductor layer  123 . Meanwhile, the lower insulation layer  135  has openings  135   a  and  135   b  exposing the n-capping layer  134   a  and the p-capping layer  134   b.    
     The opening  135   a  of the lower insulation layer  135  exposes the n-capping layer  134   a , and the opening  135   b  exposes the p-capping layer  134   b . A plurality of openings  135   b  may be formed on the p-capping layer  134   b . As illustrated, the openings  135   b  may be symmetrically disposed on both sides of the groove  130   g.    
     Referring to  FIG.  19 A  and  FIG.  19 B , an n-pad metal layer  137   a  and a p-pad metal layer  137   b  are formed on the lower insulation layer  135 . The n-pad metal layer  137   a  may be electrically connected to the n-capping layer  134   a  through the opening  135   a , and the p-pad metal layer  137   b  may be electrically connected to the p-capping layer  134   b  through the opening  135   b . As illustrated, the n-pad metal layer  137   a  may surround the p-pad metal layers  137   b.    
     The n-pad metal layer  137   a  may cover the opening  135   a , and the p-pad metal layer  137   b  may cover the opening  135   b . In addition, the n-pad metal layer  137   a  may continuously cover the side surfaces of the mesa M, and thus, light reflectivity may be improved on the side surface of the mesa M. 
     Referring to  FIG.  20 A  and  FIG.  20 B , an upper insulation layer  139  is formed on the n-pad metal layer  137   a  and the p-pad metal layer  137   b . The upper insulation layer  139  may cover the n-pad metal layer  137   a  and the p-pad metal layer  137   b  and may also cover an edge of the n-type semiconductor layer  123 . The upper insulation layer  139  may also cover a portion of the upper surface of the substrate  121 . 
     The upper insulation layer  139  has openings  139   a  and  139   b  exposing the n-pad metal layer  137   a  and the p-pad metal layer  137   b . The openings  139   a  expose the n-pad metal layer  137   a , and the openings  139   b  expose the p-pad metal layer  137   b . The openings  139   a  may be formed near one edge of the mesa M, and the openings  139   b  may be formed near an opposite edge of the mesa M to face the openings  139   a.    
     Subsequently, as shown in  FIGS.  12 A and  12 B , an n-bump  141   a  and a p-bump  141   b  are formed on the upper insulation layer  139 . The n-bump  141   a  is electrically connected to the n-pad metal layer  137   a  through the openings  139   a , and the p-bump  141   b  is electrically connected to the p-pad metal layer  137   b  through the opening  139   b.    
     The n-bump  141   a  and p-bump  141   b  may partially cover the side surface of the mesa M, respectively, but may be formed to be limited in a region over the mesa M. 
     According to the illustrated exemplary embodiment, by forming the groove  130   g  within the mesa M region and forming the n-ohmic contact layers  131   a  and  131   b  around the mesa M and in the groove  130   g , current may be uniformly spread over an entire region of the mesa M. 
       FIG.  21    is a schematic plan view illustrating a modified example of a mesa of a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
     Referring to  FIG.  21   , a groove  130   g  extends from one edge of the mesa M toward an opposite edge in a longitudinal direction. A distance between an inner end of the groove  130   g  and the opposite edge of the mesa M, that is, a difference W 1  between a total length of the mesa M and a length of the groove  130   g  may be less than or equal to a width W 2  of each mesa region which is disposed on both sides of the groove  130   g . Moreover, the length of the groove  130   g  is greater than W 1 , and thus, exceeds ½ of the length of the mesa M. Meanwhile, an area A 1  of the mesa M between the groove  130   g  and the opposite edge of the mesa M may be smaller than an area A 2  of each mesa region disposed on the both sides of the mesa M. That is, a total area  2 A 2  of the mesa regions disposed on the both sides of the mesa M may exceed ½ of a total area of the mesa. 
       FIG.  22    is a schematic plan view illustrating another modified example of a mesa of a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
     In the previous embodiments, the corners of the mesa M were shown and described as having the curved shape, but in this modified example, depressions may be formed in some corners among corners of the mesa M, respectively. The depressions improve p-side current spreading near the corners of the mesa M. 
       FIG.  23 A  is a schematic plan view illustrating a UV light emitting diode according to an exemplary embodiment of the present disclosure, and  FIG.  23 B  is a schematic cross-sectional view taken along line C-C′ in  FIG.  23 A . 
     Referring to  FIGS.  23 A and  23 B , the UV light emitting diode according to the illustrated exemplary embodiment may include a substrate  221 , an n-type semiconductor layer  223 , an active layer  225 , a p-type semiconductor layer  227 , and n-ohmic contact layers  231   a  and  231   b , a p-ohmic contact layer  233 , an n-capping layer  234   a , a p-capping layer  234   b , a lower insulation layer  235 , an n-pad metal layer  237   a , a p-pad metal layer  237   b , an upper insulation layer  239 , an n bumps  241   a , and a p-bump  241   b.    
     Since the UV light emitting diode according to the illustrated exemplary embodiment is generally similar to the UV light emitting diode described with reference to  FIGS.  12 A and  12 B , detailed descriptions of same components will be omitted to avoid redundancy, and differences will be described in detail. 
     In the illustrated exemplary embodiment, a mesa M includes a main groove  230   g  and sub grooves  230   s . The main groove  230   g  extends from one edge to an opposite edge along a longitudinal direction of the mesa M. The mesa M may be split into two by the main groove  230   g . However, the inventive concepts are not limited thereto, and one end of the main groove  230   g  may be disposed inside the mesa M. 
     Meanwhile, the sub grooves  230   s  extend from the main groove  230   g  in a direction perpendicular to the main groove  230   g . The sub grooves  230   s  may extend from the main groove  230   g  to both sides. The sub grooves  230   s  may be symmetrically disposed with respect to the main groove  230   g.    
     Meanwhile, the n-ohmic contact layer  231   a  is disposed on the n-type semiconductor layer  223  exposed by the main groove  230   g  and the sub grooves  230   s . The n-ohmic contact layer  231   b  is disposed on the n-type semiconductor layer  223  exposed along a periphery of the mesa M. The n-ohmic contact layer  231   a  may be connected to the n-ohmic contact layer  231   b , but the inventive concepts are not limited thereto. The n-ohmic contact layers  231   a  and  231   b  may be spaced apart from the mesa M to surround the mesa M. 
     The p-ohmic contact layer  233  is disposed on the p-type semiconductor layer  227  to be in ohmic contact with the p-type semiconductor layer  227 . The p-ohmic contact layer  233  may be disposed in a same shape on regions of the mesa that is split into two by the main groove  230   g.    
     The n-capping layer  234   a  may cover upper surfaces and side surfaces of the n-ohmic contact layers  231   a  and  231   b . The p-capping layer  234   b  may cover an upper and side surfaces of the p-ohmic contact layer  233 . 
     The lower insulation layer  235  covers the mesa M, and covers the n-capping layer  234   a  and the p-capping layer  234   b . The lower insulation layer  235  also covers the n-type semiconductor layer  223  exposed around the mesa M and in the grooves  230   g  and  230   s . Furthermore, the lower insulation layer  235  may cover a portion of the substrate  221  exposed around the n-type semiconductor layer  223 . Meanwhile, the lower insulation layer  235  has openings  235   a  for allowing electrical connection to the n-ohmic contact layers  231   a  and  231   b  and openings  235   b  for allowing electrical connection to the p-ohmic contact layer  233 . The opening  235   a  may have a shape similar to that of the n-ohmic contact layers  231   a  and  231   b  or the n-capping layer  234   a . That is, the opening  235   a  surrounds the mesa M and extends into the grooves  230   g  and  230   s . A width of the opening  235   a  may be smaller than that of the n-capping layer  234   a , and thus, the n-type semiconductor layer  223  may not be exposed through the opening  235   a . Meanwhile, the opening  235   b  is disposed within an upper region of the mesa M, and exposes the p-capping layer  234   b . A plurality of openings  235   b  may be disposed on the p-capping layer  234   b . In particular, the openings  235   b  may be symmetrically disposed on both sides of the groove  230   g.    
     Meanwhile, the n-pad metal layer  237   a  and the p-pad metal layer  237   b  are disposed on the lower insulation layer  135 . The n-pad metal layer  237   a  and the p-pad metal layer  237   b  may be formed of a same metal layer in a same process and disposed on a same level, that is, on the lower insulation layer  235 . 
     The n-pad metal layer  237   a  is electrically connected to the n-ohmic contact layers  231   a  and  231   b  through the opening  235   a  of the lower insulation layer  235 . The n-pad metal layer  237   a  may directly contact the n-capping layer  234   a  through the opening  235   a  of the lower insulation layer  235 . The n-pad metal layer  237   a  may cover most of the mesa M, and may also cover a region around the mesa M. 
     Meanwhile, the p-pad metal layer  237   b  may be electrically connected to the p-ohmic contact layer  233  through the opening  235   b  of the lower insulation layer  235 . The p-pad metal layers  237   b  may cover each of the openings  235   b . Each of the p-pad metal layers  237   b  may be surrounded by the n-pad metal layer  237   a . The p-pad metal layers  237   b  may be disposed within the upper region of the mesa M. Shapes of the p-pad metal layers  237   b  may have different shapes from that of the p-pad metal layer  137   b  of  FIG.  12 A  due to the sub-grooves  230   s . That is, the p-pad metal layer  237   b  may have a rectangle shape in which a portion thereof is recessed so as to form the sub-groove  230   s . In the illustrated exemplary embodiment, all side surfaces of the mesa M are covered with the n-pad metal layer  237   a . Accordingly, it is possible to prevent light loss from occurring on the side surfaces of the mesa M. 
     The upper insulation layer  239  covers the n-pad metal layer  237   a  and the p-pad metal layer  237   b , and may have openings  139   a  exposing the n-pad metal layer  137   a  and openings  139   b  exposing the p-pad metal layer  137   b . The opening  239   a  may expose the n-pad metal layer  237   a  near the one edge of the mesa M, and the openings  239   b  may expose the p-pad metal layer  237   b  near the opposite edge of the mesa M. The openings  239   a  and  239   b  may be disposed symmetrically with respect to a line passing through the groove  230   g , but the present disclosure is not necessarily limited thereto. 
     The n-bump  241   a  and the p-bump  241   b  are disposed on the upper insulation layer  239 . The n-bumps  241   a  cover the openings  239   a  and are connected to the n-pad metal layer  237   a  exposed through the openings  239   a . The p-bump  241   b  covers the openings  239   b  and is connected to the p-pad metal layer  237   b  exposed through the openings  239   b.    
       FIGS.  24 A,  25 A,  26 A,  27 A,  28 A,  29 A,  30 A, and  31 A  are schematic plan views illustrating a method of manufacturing a UV light emitting diode according to an exemplary embodiment of the present disclosure, and  FIGS.  24 B,  25 B,  26 B,  27 B,  28 B,  29 B,  30 B, and  31 B  are schematic cross-sectional views taken along line C-C′ of their corresponding plan views shown in  FIGS.  24 A,  25 A,  26 A,  27 A,  28 A,  29 A,  30 A, and  31 A , respectively. Since the method of manufacturing the UV light emitting diode according to the illustrated exemplary embodiment is substantially similar to that described above with reference to  FIGS.  13 A through  20 B , it will be briefly described. 
     Referring to  FIGS.  24 A and  24 B , first, an n-type semiconductor layer  223 , an active layer  225 , and a p-type semiconductor layer  227  are grown on a substrate  221 . 
     Meanwhile, a mesa M is formed by patterning the p-type semiconductor layer  227  and the active layer  225 . The mesa M may have a generally elongated rectangular shape, but the inventive concepts are not limited to a specific shape. As the mesa M is formed, the n-type semiconductor layer  223  may be exposed along a perimeter of the mesa M. In addition, a main groove  230   g  and sub grooves  230   s  are formed in a mesa M region. The main groove  230   g  may extend from one edge to an opposite edge thereof along a longitudinal direction of the mesa M. Mesa regions disposed on both sides of the main groove  230   g  may be identical to one another, and may be symmetrical with respect to the main groove  230   g.    
     Referring to  FIGS.  25 A and  25 B , n-ohmic contact layers  231   a  and  231   b  are formed on the n-type semiconductor layer  223 . The n-ohmic contact layer  231   a  is formed on the n-type semiconductor layer  223  exposed by the main groove  230   g  and the sub-grooves  230   s , and the n-ohmic contact layer  231   b  is formed on the n-type semiconductor layer  223  exposed around the mesa M. The n-ohmic contact layer  231   a  may extend from the n-ohmic contact layer  231   b . By continuously forming the n-ohmic contact layer  231   a  and the n-ohmic contact layer  231   b , current spreading may be assisted. However, the inventive concepts are not limited thereto, and the n-ohmic contact layer  231   a  may be spaced apart from the n-ohmic contact layer  231   b.    
     Referring to  FIGS.  26 A and  26 B , after the n-ohmic contact layers  231   a  and  231   b  are formed, a p-ohmic contact layer  233  is formed on the mesa M. The p-ohmic contact layer  233  is in ohmic contact with the p-type semiconductor layer  227 . 
     Referring to  FIGS.  27 A and  27 B , an isolation process for dividing the n-type semiconductor layer  223  is carried out. That is, the n-type semiconductor layer  223  between adjacent light emitting diode regions is removed to expose an upper surface of the substrate  221 . By adding the isolation process, singularization of the light emitting diodes may be assisted. 
     Referring to  FIGS.  28 A and  28 B , an n-capping layer  234   a  and a p-capping layer  234   b  are formed. The n-capping layer  234   a  covers upper surfaces and side surfaces of the n-type ohmic contact layers  231   a  and  231   b , and the p-capping layer  234   b  covers an upper surface and side surfaces of the p-type ohmic contact layer  233 . 
     Referring to  FIGS.  29 A and  29 B , a lower insulation layer  235  covering the mesa M is formed. The lower insulation layer  235  covers side surfaces and an upper surface of the mesa M. The lower insulation layer  235  also covers the n-capping layer  234   a  and the p-capping layer  234   b . The lower insulation layer  235  may cover a side surface of the n-type semiconductor layer  223 , and may partially cover the substrate  221  exposed around the n-type semiconductor layer  223 . Meanwhile, the lower insulation layer  235  has openings  235   a  and  235   b  exposing the n-capping layer  234   a  and the p-capping layer  234   b , respectively. 
     The opening  235   a  of the lower insulation layer  235  exposes the n-capping layer  234   a , and the opening  235   b  exposes the p-capping layer  234   b . The opening  235   a  may be disposed in the main groove  230   g  and the sub grooves  230   s . In addition, a plurality of openings  235   b  may be formed on the p-capping layer  234   b . As shown in the drawings, the openings  235   b  may be symmetrically disposed on both sides of the groove  130   g.    
     Referring to  FIGS.  30 A and  30 B , an n-pad metal layer  237   a  and a p-pad metal layer  237   b  are formed on the lower insulation layer  235 . The n-pad metal layer  237   a  may be electrically connected to the n-capping layer  234   a  through the opening  235   a , and the p-pad metal layer  237   b  may be electrically connected to the p-capping layer  234   b  through the opening  235   b . As shown in the drawings, the n-pad metal layer  237   a  may surround the p-pad metal layers  237   b.    
     The n-pad metal layer  237   a  may cover the opening  235   a , and the p-pad metal layer  237   b  may cover the opening  235   b . In addition, the n-pad metal layer  237   a  may continuously cover the side surfaces of the mesa M, and thus, light reflectivity may be improved on the side surfaces of the mesa M. 
     Referring to  FIGS.  31 A and  31 B , an upper insulation layer  239  is formed on the n-pad metal layer  237   a  and the p-pad metal layer  237   b . The upper insulation layer  239  may cover the n-pad metal layer  237   a  and the p-pad metal layer  237   b  and also cover an edge of the n-type semiconductor layer  223 . The upper insulation layer  239  may also cover a portion of the upper surface of the substrate  221 . 
     The upper insulation layer  239  has openings  239   a  and  239   b  exposing the n-pad metal layer  237   a  and the p-pad metal layer  237   b , respectively. The openings  239   a  expose the n-pad metal layer  237   a , and the openings  239   b  expose the p-pad metal layer  237   b . The openings  239   a  may be formed near the one edge of the mesa M, and the openings  239   b  may be formed near the opposite edge of the mesa M to face the openings  239   a . The openings  239   a  and  239   b  of the upper insulation layer  239  may have a shape modified from a rectangle so as to accommodate the sub grooves  230   s . That is, as shown in  FIG.  31 A , the openings  239   a  and  239   b  may have a rectangular shape in which a portion thereof is recessed. 
     Subsequently, as shown in  FIGS.  23 A and  23 B , n-bumps  241   a  and p-bumps  241   b  are formed on the upper insulation layer  239 . The n-bump  241   a  is electrically connected to the n-pad metal layer  237   a  through the openings  239   a , and the p-bump  241   b  is electrically connected to the p-pad metal layer  237   b  through the openings  239   b.    
     Each of the n-bump  241   a  and p-bump  241   b  may partially cover the side surface of the mesa M, but may also be formed to be limited in a region over the mesa M. 
     According to the illustrated exemplary embodiment, by forming the main groove  230   g  and the sub grooves  230   s  within a mesa M region and forming the n-ohmic contact layers  231   a  and  231   b  around the mesa M and within the main groove  230   g  and the sub grooves  230   s , current may be uniformly spread over an entire region of the mesa M. 
       FIG.  32    is a schematic plan view illustrating a modified example of a mesa of a UV light emitting diode according to an exemplary embodiment of the present disclosure. 
     In the mesa M of the UV light emitting diode described above with reference to  FIGS.  23 A and  23 B , the sub grooves  230   s  are symmetrically disposed with respect to the main groove  230   g . Lengths and widths of the sub grooves  230   s  are substantially equal to one another, and thus, the n-ohmic contact layer  231   a  having a same size is formed in each of the sub grooves  230   s . However, the inventive concepts are not limited thereto, and the sub grooves may be variously modified. For example, as shown in  FIG.  32   , sub-symmetrical mesa regions M 1  and M 2  may be formed with respect to a line X-X passing through a center of the light emitting diode and parallel to a main groove  330   g . That is, sub grooves  330   s ,  330   s   2 , and  330   s   3  are asymmetrically disposed with respect to the line X-X. Meanwhile, the sub grooves  330   s   1 ,  330   s   2 , and  330   s   3  may be symmetrically disposed with respect to a line Y-Y passing through the center of the light emitting diode and perpendicular to the main groove  330   g.    
     The sub grooves  330   s   1 ,  330   s   2 , and  330   s   3  may be disposed on both sides of the main groove  330   s , but the sub grooves  330   s ,  330   s   2 , and  330   s   3  may have different widths and/or lengths. For example, the sub groove  330   s   2  having a relatively small width and length may be disposed between the sub grooves  330   s   1  having a relatively large width and length. In addition, the sub grooves  330   s   1  and  330   s   3  having different widths and/or lengths may be disposed opposite each other with the main groove  330   g  interposed therebetween. By increasing the width of the sub groove  330   s   1 , light reflection generated from a mesa sidewall may be increased. 
     The inventive concepts are not limited to the main groove  330   g  and the sub grooves  330   s   1 ,  330   s   2 , and  330   s   3  described herein, and may be variously modified. 
     Although some exemplary embodiments have been described herein, it should be understood that the above exemplary embodiments may be variously modified and changed without departing from the spirit and scope of the present disclosure, and the present disclosure includes all of the broad scope of the appended claims.