Patent Publication Number: US-11036251-B2

Title: Circuit arrangement for the generation of a bandgap reference voltage

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 16/183,101 filed Nov. 7, 2018, which is a divisional of U.S. patent application Ser. No. 16/007,403 filed Jun. 13, 2018, now U.S. Pat. No. 10,152,079, which is a divisional of U.S. patent application Ser. No. 14/996,684 filed Jan. 15, 2016, now U.S. Pat. No. 10,019,026, which claims priority from Italian Application for Patent No. 102015000014448 filed May 8, 2015, the disclosures of which are incorporated by reference. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to a circuit arrangement for the generation of a bandgap reference voltage in CMOS technology, of the type that comprises using a circuit module for the generation of a base-emitter voltage difference comprising a pair of PNP bipolar substrate transistors. 
     Various embodiments may be applied to voltage references in DRAMs, flash memories, voltage regulators, and analog-to-digital converters. 
     BACKGROUND 
     In general, modules for generation of a voltage reference represent one of the most important analog modules in the development of analog or digital circuits such as DRAMs, flash memories, voltage regulators, analog-to-digital converters, and other circuits. 
     The majority of voltage references are designed on the basis of a bandgap voltage reference that produces a reference voltage of approximately 1.25 V, said bandgap reference voltage having a low dependence upon the temperature and/or the supply voltage. 
     A bandgap voltage reference operates on the basis of the principle of balancing in a circuit the negative temperature coefficient of a pn junction, usually the voltage V BE  on the base-emitter junction of a bipolar transistor, with the positive temperature coefficient of the thermal voltage V T , where V T =kT/q. 
     The characteristics of bipolar transistors enable them, as mentioned, to supply the best defined quantities in order to obtain positive and negative temperature coefficients. The thermal voltage V T  has a positive temperature coefficient of 0.085 mV/° C. at room temperature; i.e., it is a coefficient of a PTAT (Proportional To Absolute Temperature) electrical quantity, whether voltage or current. Instead, the base-emitter voltage V BE  of a bipolar transistor has a negative temperature coefficient of approximately −2.2 mV/° C. at room temperature; i.e., it is a coefficient of a CTAT (Complementary To Absolute Temperature) electrical quantity. 
     In general, a bandgap voltage reference adds together two quantities, a PTAT one and a CTAT one, in particular two voltages, so as to obtain a voltage reference with zero temperature coefficient. This is obtained, in particular, by multiplying a multiple M of the thermal voltage V T  and adding it to the base-emitter voltage V BE , to obtain a reference voltage V REF =V BE +MV T . 
     In CMOS technologies, where independent bipolar transistors are not available, to obtain the PTAT and CTAT quantities indicated above, parasitic bipolar transistors are exploited, in a way in itself known. 
     It is also possible, to obtain PTAT voltages, to use the difference between the gate-source voltages of two weakly reverse-biased MOS transistors. 
     In what follows, reference will be made in any case to solutions for generation of a bandgap voltage reference that use the parasitic PNP bipolar substrate transistors available in CMOS technology. 
       FIG. 12  represents in this connection the structure of a pMOSFET M, obtained in CMOS technology, which shows how the regions with p+ doping of the MOS structure, the region with n doping of the n-well, and the p substrate together identify a PNP bipolar transistor. The references E, B, and C designate the emitter, base, and collector electrodes, respectively. 
       FIG. 1  shows an example of bandgap-voltage-reference generator, designated by the reference number  50 , which uses parasitic PNP bipolar substrate transistors to generate a base-emitter voltage. 
     The above generator  50  basically comprises a circuit module  101  for generation of a base-emitter voltage difference, which comprises a pair of transistors, a first bipolar transistor Q 1 , and a second bipolar transistor Q 2 . These bipolar transistors Q 1  and Q 2  are obtained from the parasitic PNP bipolar transistors available in CMOS technology, as shown in  FIG. 12 . For this reason, the parasitic bipolar transistors Q 1  and Q 2  have the collector and the base connected to ground and hence connected in common. The second bipolar transistor Q 2  has an aspect ratio that is a number N times that of the first bipolar transistor Q 1 . 
     The emitter terminals E 1  and E 2  of the bipolar transistors Q 1  and Q 2  define, respectively, two branches, B 1  and B 2 , that correspond to the paths of the currents I from the supply voltage Vdd to ground GND through the two respective transistors Q 1  and Q 2  that provide the base-emitter voltage drop on the above respective branches. 
     Connected to the emitter terminal E 1  on the first branch B 1  is a first resistance R 2 , whereas connected on the second branch B 2 , between the emitter E 2  and the supply voltage Vdd, are a second resistance R 1  for adjustment of the bandgap reference voltage and a bias resistance R 3 . Connected to the emitter E 1  of the first bipolar transistor Q 1  and to the node between the adjustment resistance R 1  and the bias resistance R 3  are the positive and negative terminals of a differential amplifier AMP, which supplies at output the reference voltage V REF . 
     In this case, we have:
 
 V   REF   =V   EB1 +( R 2/ R 1) V   T ·ln( N )
 
where V EB1  is the voltage between the emitter and the base of the first bipolar transistor Q 1 . By operating on the ratio between the two adjustment resistances R 2  and R 1  and the value of the aspect ratio N, it is possible to vary the value of the bandgap reference voltage V REF .
 
       FIG. 2  shows a circuit arrangement of a bandgap-voltage-reference generator  100 , in which, as compared to the generator  50  of  FIG. 1 , the operational amplifier has been eliminated, introducing a third branch B 3 , with a third path from the supply Vdd to ground GND, through a third bipolar transistor Q 3  set in parallel with respect to the transistors Q 1  and Q 2  that constitute the so-called bipolar core  101  of a voltage-reference generator  101 . 
     In what follows, reference will be made to CMOS current mirrors, and the diode-connected MOSFET, which provides the current-voltage conversion, will be referred to as the first MOSFET or first transistor of the current mirror, and the other MOSFET connected thereto via the gate, which provides the voltage-current conversion, will be referred to as the second MOSFET or transistor of the current mirror. 
     In this case, the circuit includes a first CMOS current mirror  102  of an n type, which comprises a first MOSFET M 1 , which, as has been said, is diode-connected, with its gate and drain electrodes shorted, and a second MOSFET M 2 , and is connected between the first branch B 1  and the second branch B 2 , and a second CMOS current mirror  103  of a p type, which comprises a first MOSFET M 4  and a second MOSFET M 3  and is connected between the first branch B 1  and the second branch B 2 . The first and second current mirrors,  102  and  103 , are complementary and connected, through nodes D 1  and D 2  corresponding to the drains in common of their MOSFETs so that each repeats current mirror the current of the other. 
     Present on the third branch B 3  is a further MOSFET M 5 , connected to the gate of the first MOSFET M 4  of the second current mirror  103 , which provides a further current mirror in parallel to the second current mirror  103 , the output of which is connected through a second adjustment resistance R 2  to the emitter E 3  of the third bipolar transistor Q 3 , thus completing the third branch B 3 . The voltage reference V REF  is taken between the further biasing transistor M 5  and the second adjustment resistance R 2 . 
     It should be noted that, together with the adjustment resistance R 1  that connects the emitter E 2  on the second branch to the source of the transistor M 2  of the first current mirror  102 , these current mirrors  102  and  103  provide substantially the structure of a ‘beta multiplier’, where, however, the MOSFETs M 1 , M 2 , M 3 , M 4  all have the same aspect ratio so that the current I 2  in the second branch B 2  is equal to the current I 1  in the first branch B 1 . Since also the MOSFET M 5  has the same aspect ratio as the MOSFET M 4 , also the current I 3  in the third branch B 3  is the same. 
     Also in this case we obtain a relation similar to the previous one:
 
 V   REF   =V   EB3 +( R 2/ R 1) V   T ·ln( N )
 
where V EB3  is the voltage between the emitter and the base of the third bipolar transistor Q 3 , while R 2  is the adjustment resistance connected to the emitter E 3  of the third bipolar transistor Q 3 , and R 1  is the adjustment resistance connected to the emitter E 2  of the transistor Q 2 .
 
     Hence, in general, known circuits use further power-consumption sources, and further operational amplifiers or bipolar transistors in addition to the pair of bipolar transistors that supplies the base-emitter voltage difference, thus preventing any reduction of consumption of the bandgap-voltage-reference generator. 
     SUMMARY 
     There is a need in the art to improve the potential of the devices according to the known art as discussed previously. 
     Various embodiments address the foregoing need thanks to a circuit arrangement having the characteristics recited in the ensuing claims. 
     In one embodiment, it is envisaged that the circuit module for generation of a base-emitter voltage difference comprises only a first bipolar substrate transistor (inserted in the first circuit branch) and a second bipolar substrate transistor (inserted in the second circuit branch). 
     Various embodiments may envisage that the circuit arrangement includes a reference-voltage generation module comprising the second current mirror and the adjustment resistance and, connected on the first branch, a reference resistance set between the first and second current mirrors and an analog buffer, the input of which is connected to the reference resistance and to the second current mirror. 
     Various embodiments may envisage that the circuit arrangement includes an analog buffer that comprises a common-drain nMOS transistor on which the reference voltage is taken. 
     Various embodiments may envisage that the common-drain nMOS transistor has its output connected on the first branch on which the reference voltage is taken. 
     Various embodiments may envisage that the nMOS transistor has its output connected on the second branch on which the reference voltage is taken. 
     Various embodiments may envisage that the transistors of the first current mirror and the nMOS transistor operating as buffer that drives the reference voltage are sized so as to have the same drain-source voltage. 
     Various embodiments may envisage that the circuit arrangement comprises a further current mirror connected between the second current mirror and the reference-voltage generation module. 
     Various embodiments may envisage that the circuit arrangement includes a further current mirror of a p type with mirroring ratio of 1:2, comprising two diode-connected transistors arranged in parallel, which are connected to the second branch and to a further branch, while the other transistor of the current mirror, which has twice the aspect ratio, is connected to the first branch, the current mirror being connected on the first and second branches to an n-type current mirror with mirroring ratio of 2:1, which is connected in turn to said circuit module for generation of a base-emitter voltage difference, whereas on the further branch the current mirror is connected through a respective adjustment resistance to the circuit module for generation of a base-emitter voltage difference on the second branch. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various embodiments will now be described, purely by way of example, with reference to the annexed figures, wherein: 
         FIG. 1  shows a circuit for a prior art bandgap voltage generator; 
         FIG. 2  shows a circuit for another example of a prior art bandgap voltage generator; 
         FIG. 3  shows a block diagram of a first embodiment of a circuit arrangement for generation of a voltage reference; 
         FIG. 4  shows in detail an embodiment of the circuit arrangement of  FIG. 3 ; 
         FIG. 5  shows a variant of the circuit arrangement of  FIG. 4 ; 
         FIG. 6  shows in detail a second embodiment of the circuit arrangement of  FIG. 3 ; 
         FIG. 7  shows a variant of the circuit arrangement of  FIG. 6 ; 
         FIG. 8  shows a second variant of the circuit arrangement of  FIG. 6 ; 
         FIG. 9  shows a block diagram of a second embodiment of a circuit arrangement for generation of a voltage reference; 
         FIG. 10  shows in detail an embodiment of the circuit arrangement of  FIG. 9 ; 
         FIG. 11  shows a variant of the circuit arrangement of  FIG. 10 ; and 
         FIG. 12  illustrates the structure of a pMOSFET in CMOS technology. 
     
    
    
     DETAILED DESCRIPTION 
     In the ensuing description, numerous specific details are provided to enable maximum understanding of the embodiments provided by way of example. The embodiments may be implemented with or without specific details, or else with other methods, components, materials, etc. In other circumstances, well-known structures, materials, or operations are not shown or described in detail so that aspects of the embodiments will not be obscured. Reference, in the course of this description, to “an embodiment” or “one embodiment” means that a particular feature, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, and the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, the particular features, structures, or characteristics may be combined in any convenient way in one or more embodiments. 
     The notation and references used herein are provided only for convenience of the reader and do not define the scope or the meaning of the embodiments. 
     With reference to  FIG. 3 , a diagram of a first embodiment of a circuit arrangement  200  for the generation of a voltage reference is described. 
     Designated by the reference  101  is the circuit module for generation of a base-emitter voltage difference, which comprises a pair of parasitic substrate transistors Q 1  and Q 2  of a PNP type, with the base in common and the collector connected to ground, as already described with reference to the generators of  FIGS. 1 and 2 , so as to define, respectively, a first branch B 1  and a second branch B 2 , corresponding to current paths between the supply Vdd and ground GND. 
     The circuit arrangement  200  comprises, connected to the above circuit module  101  for generation of a base-emitter voltage difference, in particular to the emitter terminals or nodes E 1  and E 2 , a reference-voltage generation circuit module  112 . 
     The above reference-voltage generation module  112  comprises a block  102  that carries out current mirroring, which may be considered equivalent (but for the possible insertion of bias resistances Rp 1  and Rp 2 ) to the first current mirror  102  of  FIG. 2 , and (with reference also to the embodiment described in  FIGS. 4, 6, and 9 ) is arranged in the same way, connected to the emitter terminals E 1  and E 2  via the sources of the MOSFETs M 1  (first MOSFET of the first mirror  102 ) and M 2  (second MOSFET of the first mirror  102 ).  FIG. 3  shows that these MOSFETs M 1  and M 2  identify voltage buffers  102   a  and  102   b . As described in what follows, these buffers are implemented as common-drain voltage buffers. These buffers  102   a  and  102   b , the outputs of which are connected to the branches B 1  and B 2 , have bias resistances Rp 1  and Rp 2  the value of which can be set in order to shift the working point of the circuit. Moreover, the circuit  200  also comprises the second current mirror  103  of a p type of  FIG. 2 , connected in the same way to the branches B 1  and B 2 . 
     The reference-voltage generation module  112 , however, further comprises, on a node D 1  corresponding to the first current mirror  102 , i.e., the drain of the transistor M 1 , a reference-adjustment resistance Ra 2 , connected to which is the input of an analog voltage buffer  113   a . The reference voltage V REF  is taken at the output of said analog buffer  113   a.    
     As a result of the introduction of the above reference-adjustment resistance Ra 2  and analog buffer  113   a , the node D 1  of  FIG. 2 , which was common to the drains of the transistors M 1  and M 3 , is now divided into two nodes, D 1  and D 3 , on the first branch B 1 , set between which is the reference-adjustment resistance Ra 2 . On the second branch B 2 , between the two current mirrors  102  and  103 , no elements are, instead, introduced. Consequently, the drains of the MOSFETs M 2  and M 4  are in common in a node D 2 , in the diagram of  FIG. 3  and in the implementations of  FIGS. 4 and 5 . This does not take into account the bias resistances Rp 1  and Rp 2 , which enable optimization the working point of the circuit. 
     In this circuit arrangement  200 , the reference voltage is
 
 V   REF   ≅V   EB1   +V   R2   =V   EB1   +Ra 2· I 1≅ V   EB +( Ra 2/ R 1)· V   T ·ln( N )
 
where V R2  is the voltage drop across the reference-adjustment resistance Ra 2 , and I 1  is the current that flows in the transistor Q 1 , as likewise in the transistor Q 2 , i.e., in the two branches  1 ,  2  of the circuit; namely, I 1 =I 2 =I. It should be noted that the voltage drop on the bias resistances Rp 1 , Rp 2  does not come into play for the purposes of definition of the reference voltage V REF . In fact, with reference to the circuit of  FIG. 3 , it is assumed that the drop on the voltage buffers  102   a ,  102   b  is zero (i.e., that they are ideal buffers). The voltage at the node D 3  (which is hence the reference voltage V REF ) is the sum of the drop on the adjustment resistance Ra 2 , the drop on the first buffer  102   a  (which is zero), and the potential of the emitter node E 1 , i.e., V EB1 . N is the ratio between the aspect ratios of the second transistor Q 2  and the first transistor Q 1 . R 1  is the other adjustment resistance, as it was already in  FIG. 2 . Basically, the adjustment resistance Ra 2  on the first branch B 1 , as has been seen, replaces the second adjustment resistance R 2  on the third branch B 3  of  FIG. 2 .
 
     In this way, the circuit arrangement  200  uses just the consumption of current I determined by the module  101 , which comprises just two branches, B 1  and B 2 , and hence just two bipolar transistors Q 1  and Q 2 , to generate the bandgap voltage reference V REF , without any need to add any other current consumption. 
     In other words, the circuit arrangement  200  has a circuit module  101  for generation of a base-emitter voltage difference, which comprises just the first bipolar substrate transistor Q 1  inserted in the first circuit branch B 1  and the second bipolar substrate transistor Q 2  inserted in the second circuit branch B 2 , the current that flows in the circuit arrangement  200  (from the supply voltage Vdd to ground GND) flowing only through the first bipolar substrate transistor Q 1  and the second bipolar substrate transistor Q 2 . 
     The circuit arrangement  200  is obtained in CMOS technology, and hence the bipolar transistors Q 1  and Q 2  are obtained as parasitic PNP transistors. As has been seen, the known solutions, such as the one illustrated in  FIG. 2 , normally use three or more branches, whereas the solution described herein uses just two branches, B 1  and B 2 , thus reducing current consumption. 
       FIG. 4  shows a circuit implementation  200 ′ of the embodiment of  FIG. 3 . The first buffer  102   a  is obtained via the nMOS transistor M 1 , while the second buffer  102   b  is obtained via the second nMOS transistor M 2 . The p-type current mirror  103  is obtained, as in  FIG. 2 , via two pMOS transistors, the first MOSFET M 4  and the second MOSFET M 3 , which are connected via their sources to the digital supply voltage Vdd and have their drains connected to the terminals D 3  and D 2 , respectively. 
     The third buffer  113   a  is obtained via a third MOSFET M 13  of an n type, the gate of which is connected to the resistance Ra 2  and to the node D 3 , which is the drain node of the MOS M 3  of the second current mirror  103 , i.e., on the first branch B 1 . The drain of the MOS M 13  is connected to the other end of the reference-adjustment resistance Ra 2 , i.e., to the node D 1 , and is shorted on the gates of the transistors M 1  and M 2  of the first current mirror  102 . Hence, this MOS M 13  has at input (i.e., at its gate) the voltage on the terminal at higher potential of the resistance Ra 2 , and at output (i.e., at its source) it drives the reference voltage V REF . The source of the MOSFET M 13 , on which the output V REF  is taken, is connected via a source resistance R 13  to the drain of the first MOSFET M 1  of the mirror  102  on the first branch B 1 . Consequently, the MOS M 13  operates substantially as analog buffer, in particular a common-drain voltage buffer with output on the source. 
     In this case, ensuring for example, by sizing the resistance R 13 , as described in greater detail hereinafter, that the drain-source voltage V DS1  of the first MOSFET M 1  is approximately equal to the drain-source voltage V DS13  of the MOSFET M 13  that implements the buffer  113   a , the reference voltage V REF  is
 
 V   REF   =−V   GS13   +V   R2   +V   GS1   +V   EB1   ≅V   EB1   +V   R2   =V   EB1   +Ra 2· I   D1,D3  
 
where V GS13  and V GS1  are the gate-source voltages of the transistors M 13  and M 1 , and I D1,D3  is the current that flows in their drains, i.e., the current I 1  in the first branch B 1 .
 
     The resistance R 13  between the source of the third MOSFET M 13  and the drain of the first MOSFET M 1  serves for proper operation of the circuit, in so far as it has the purpose of rendering the drain-source voltage V DS1  of the first nMOS M 1  of the mirror  102 ) equal to the drain-source voltage VDS 13  of the MOS M 13 . In fact, given two nMOS transistors traversed by the same current and with the same aspect ratio W/L, it is necessary to render also their drain-source voltages V DS  equal for them to have the very same gate-source voltage V GS  (given that by rendering the voltages V DS  equal, the effect of modulation of the channel length is made equal). It hence be noted that
 
 V   DS13 ( M 13)=− Ra 2 ·I+V   GSM13  
 
while
 
 V   DS1   =−R 13· I−V   GS13   +Ra 2· I+V   GS1  
 
i.e.,  V   DS1   =−R 13· I+Ra 2· I  
 
Then, by fixing R 13  so that
 
 R 13=2· Ra 2− V   Gs   /I  
 
we have
 
V GS13 =V GS1  
 
Rendering equal the gate-source voltages V GS  makes it possible to obtain the relation
 
 V   REF   =−V   GS13   +V   R2   +V   GS1   +V   EB1   ≅V   EB1   +V   R2  
 
appearing above.
 
     If moreover the circuit is sized in such a way that the drain-source voltage V DS1  of the first MOSFET M 1  of the current mirror  102  on the first branch B 1  is approximately equal to the drain-source voltage of the second MOSFET M 2  of the current mirror  102  on the second branch B 2 , the approximate equality
 
 V   REF   ≅V   EB1 +( Ra 2/ R 1)· V   T ·ln( N )
 
is obtained with an even higher precision, and in this way the precision with which the reference voltage V REF  is fixed increases.
 
       FIG. 5  shows a variant of the circuit arrangement of bandgap-voltage-reference generator  200 ″ where a current mirror  103 ″ in cascode configuration is used, in which it is possible to optimize the maximum output dynamics thanks to adjustment of a biasing voltage level V p . This mirroring configuration is in itself known. In the implementation described, the current mirror  103 ″ comprises the pair of MOSFETs M 3 , M 4  and further respective MOSFETs M 3   c  and M 4   c  set cascoded thereto. This arrangement increases the power-supply rejection (PSR) factor of the circuit, and moreover increases the precision with which the currents that flow on the two branches B 1  and B 2  are rendered equal to one another. It should be noted that by increasing the precision with which the currents on the two branches B 1  and B 2  are rendered equal, the precision with which the reference voltage is determined is further increased
 
 V   REF   =−V   GS13   +V   R2   +V   GS1   +V   EB1   ≅V   EB1   +V   R2   =V   EB1   +Ra 2· I   D1,D3 .
 
     In this case, the gates of the MOSFETs M 3  and M 4  are shorted on the node D 3  to provide the diode configuration on the second branch B 2 , while connected to the gates of the further pair of transistors M 3   a , M 4   a  is the biasing voltage V p  of the cascode. The voltage level V p  is a voltage level that, during the design stage, is optimized in order to maximize the output dynamic of the mirror  103 ″. An appropriate setting of the value of biasing voltage V p  renders the mirror  103 ″ equivalent to the mirror  103  of  FIG. 4  from the standpoint of the dynamics (i.e., in other words, the maximum value of voltage at the node D 3  is Vdd−V SDsat3  and the maximum value at the node D 2  is Vdd−V SG4  both for the mirror  103  and for the mirror  103 ″). Generation of the level of biasing voltage V p  would require insertion of a further current branch: this additional current branch in practice may be characterized by a current consumption that is in any case a negligible fraction of the currents that flow in the two main branches. Hence, even by generating the level of biasing voltage V p , the total consumption is approximately the one necessary in the two main branches. 
     Also in the implementations proposed in  FIGS. 4 and 5 , the voltage drop on the bias resistances R p1  and R p2  does not come into play for the purposes of definition of the reference voltage V REF , even though the drop of the voltage buffers  102   a ,  102   b ,  113   a  implemented via the MOSFETs M 1 , M 2 , M 13  is not zero, but corresponds to the gate-source voltage V GS  of the MOS. However, in all cases, by following the path that goes from the reference voltage V REF  to the emitter-base voltage V EB  of the bipolar transistors Q 1  and Q 2 , it may be noted that we obtain (with reference to the embodiments of  FIGS. 4,5,6,7, and 8 )
 
 V   REF =[− V   GS13   +V   R2   +V   GS1   +V   EB1 ]
 
where V GS13  corresponds to the gate-source voltage of the MOS M 13 , and V GS1  to the gate-source voltage of the MOS M 1 . Considering that these MOSFETs M 13  and M 1  are traversed by the same current, it follows that their gate-source voltages are equal and hence cancel out in the relation appearing above.
 
     In various embodiments, in the circuit implementations  200 ′ there may possibly be added a further bias resistance between the node D 2  and the drain of the MOS M 2 . Thanks to this further resistance, it is possible to fix to a precise value also the drain-source voltage V DS  of the MOS M 2 . In fact, operation of the circuit is improved if also the second MOSFET M 2  of the mirror  102  has (in addition to the same current) the same drain-source voltage V DS  (and obviously the same aspect ratio W/L) as the MOSFETs M 1  and M 3 : by so doing, in fact, the voltages at the source of the first MOSFET M 1  and at the source of the second MOSFET M 2  are rendered equal with a high precision, and the biasing current is set at the value
 
( V   EB1   −V   EB2 )/ R 1=( V   T ·ln( N ))/ R 1
 
with a high precision.
 
     In this way, the reference voltage V REF  is fixed with a greater precision. 
     If this further resistance between the node D 2  and the drain of the MOS M 2  is zero, i.e., is not present, we have
 
 V   DS2   =Vdd−V   SG4   −V   EB1  
 
     If the value of supply voltage Vdd is high to the point of causing the drain-source voltage V DS2  of the second MOSFET M 2  to be higher than the drain-source voltage V DS1  of the first MOSFET M 1 , which is equal to the drain-source voltage V DS3  of the third MOSFET M 13 , an improvement in performance may be obtained by inserting a value of said further bias resistance between the node D 2  and the drain of the MOS M 2  other than zero. If this resistance is denoted by R 14 , we thus have:
 
 V   DS2   =Vdd−R 14· I−V   SG4   −V   EB1  
 
and hence the resistance R 14  must be fixed to impose
 
 V   DS1   =V   DS2   =V   DS3  
 
       FIG. 6  shows a second implementation  300  of the first embodiment of  FIG. 3 . 
     This implementation corresponds to that of  FIG. 4 ; in particular, it has a similar circuit module  101  for generation of a base-emitter voltage difference and a similar second current mirror  103  connected to the supply voltage Vdd. The reference-voltage generation module  312  comprises in the same way the first current mirror  102 . In addition, the drain node D 1  of the first MOSFET M 1  of the mirror  102  and the drain node D 3  of the second MOSFET M 3  of the mirror  103  are also in this case separated by the reference-adjustment resistance Ra 2 . The difference of the reference-voltage generation module  312  from the module  112  of  FIG. 4  is that the MOSFET M 13  that implements the voltage buffer  113   a  is in this case located on the second branch B 2 , i.e., set between the drain D 4  of the diode-connected transistor M 4  of the second mirror  103 , to which it is connected via its own drain, and the drain D 2  of the second transistor of the first current mirror, to which it is connected via its own source. The gate of the transistor M 13  remains connected at the node D 3  to a terminal of the reference resistance Ra 2 , as in  FIG. 4 . In this case, the resistance R 13  is not present. 
     Considering that the current I D1  in the drain of the first diode-connected MOSFET M 1  on the first branch B 1  is approximately equal to the current I D2,D4  in the drains D 2 , D 4  of the transistors M 2  and M 13  on the second branch B 2 , by ensuring via sizing that the drain-source voltage V DS1  of the first MOSFET M 1  is approximately equal to the drain-source voltage V DS13  of the third MOSFET M 13 , then the reference voltage V REF  is
 
 V   REF   =−V   GS13   +V   R2   +V   GS1   +V   EB1   ≅V   EB1   +V   R2   =V   EB1   +Ra 2· I   D1  
 
     If moreover the circuit is sized in such a way that the drain-source voltage of the first MOSFET M 1 , V DS1 , is approximately equal to the drain-source voltage of the second MOSFET M 2  on the second branch B 2 , then also in this case the precision with which the reference voltage V REF  is determined is maximized. 
     Also in this case the module  101  has just two branches, B 1  and B 2 , i.e., just two current paths from the supply to ground, for the just two bipolar transistors Q 1  and Q 2 . 
       FIG. 7 , in a way similar to  FIG. 5 , shows a variant  300 ′ of the circuit of  FIG. 6  in which a current mirror  103 ′ in cascode configuration is used (which comprises the pair of MOSFETs M 4  (diode-connected) and M 3 , and additional respective MOSFETs M 4   a  and M 3   a  cascaded thereto. In this case, the gates of the MOSFETs M 3  and M 4  are shorted on the node D 2  to provide the diode configuration on the second branch B 2 , whereas the gates of the further pair of MOSFETs M 4   a , M 3   a  are connected to a biasing voltage V p , to which there also apply the same considerations set forth previously regarding the mirror  103 ″. 
       FIG. 8  shows a further variant  300 ″ of the circuit of  FIG. 6 , which makes it possible to obtain drain-source voltages for the MOSFETs M 1 , M 2 , M 3  that are exactly equal, in this way guaranteeing a better precision of the reference voltage V REF . 
     In this case, set between the second current mirror  103  and a reference-voltage generation module  322  is a third current mirror  104 , with an n-type MOSFET, where the MOSFET M 6  on the first branch B 1  is diode-connected with the drain connected to the node D 3 , whereas set on the second branch is the second MOSFET M 7  with the drain connected to the node D 4 . 
     The reference-voltage generation module  322  corresponds to the module  312  of  FIG. 6  or  FIG. 7 , except for the fact that a resistance R 23  is set between the source of the transistor M 13  that operates as analog buffer, on which the reference voltage V REF  is taken, and the drain of the second transistor M 2  of the first current mirror  102 . 
     The MOSFETs M 6  and M 7  of the third current mirror  104  ensure that V DS1 =V DS13 , whereas the resistance R 23  is a resistance the value of which can be sized greater than zero in order to render equal to zero also the drain-gate voltage of the MOS M 2  (in the case where this is positive). Hence, it is possible to obtain V DS2 =V DS1  via the resistance R 23 , thus rendering the drain-source voltages of M 2 , M 1  and M 13  equal, by sizing
 
 R 23=( V   Ra2   −V   GS1,2,13 )/ I   D1,D2,D3  
 
     The circuit of  FIG. 6 , instead, without the further current mirror with MOSFETs M 6  and M 7 , determines a lower value for the minimum supply voltage Vdd admissible. 
       FIG. 9  shows a block diagram of a second embodiment 400 of a circuit arrangement for the generation of a voltage reference. 
     As may be noted this embodiment comprises the circuit module  101  for generation of a base-emitter voltage difference already described with reference to  FIG. 3  and comprising a pair of parasitic substrate transistors Q 1  and Q 2  of a PNP type, with the base in common and the collector at ground and a resistive load on the emitter of the second transistor Q 2 . 
     In this case, however, from the emitter nodes E 1  and E 2  to the supply, the other modules of the circuit  400  have three branches, the second branch B 2  being split into two via the addition in parallel of a further branch B 2 ′, connected between the supply voltage Vdd and the emitter of the second bipolar transistor. In particular, connected to the supply Vdd is a p-type current mirror  403  with a mirroring ratio of 2:1:1 on the branches B 1 , B 2  and B 2 ′, respectively; namely, the current on the second branch B 2  and on the further branch B 2 ′ is half of the current I 1  (or I) on the first branch. 
     A reference-voltage generation module  412  comprises a current mirror of an n type,  402 , connected to the branches B 1  and B 2 , which has also a mirroring ratio of 2:1, comprising buffers  402   a  and  402   b . Each of the buffers  402   a  and  402  has a bias resistance Rp 1  and Rp 2 . Moreover, provided on the further branch B 2 ′ is a third bias resistance Rp 2 ′ that connects the second current mirror  403 , through an adjustment resistance R 1 ′, to the emitter E 2 . 
       FIG. 10  shows a circuit implementation  500 , where the p-type current mirror  403  comprises a second MOSFET M 23  on the first branch B 1  with aspect ratio that is twice that of the first MOSFETs M 24  and M 25  connected in parallel on the branches B 2  and B 2 ′. Likewise, the current mirror  402  implements the buffers  402   a  and  402   b  via MOSFETs M 21  and M 22 , where the first MOSFET M 21  on the first branch B 1  has an aspect ratio that is twice that of the MOSFET M 22  on the second branch B 2 . In this way, a current I 1  is determined that is twice the currents through the transistors M 24  and M 25 , so that in the second branch B 2  there once again flows a current I 2  equal to I 1 , at the same time maintaining just two branches, B 1  and B 2 , at the level of the generation module  101  and as far as ground GND. 
     The output V REF  is taken on the further branch B 2 ′ between the drain node of the transistor M 25  and the further adjustment resistance R 1 ′ connected to the emitter E 2  of the bipolar transistor Q 2  in parallel to the adjustment resistance R 1 . 
     Hence, also in this case, hence, the bandgap voltage V REF  is
 
 V   REF   ≅V   EB1,2   +V   R1′   =V   EB1,2   +R 1 ′·I/ 2≅ V   EB1,2 +( R 1 ′/R 1)· V   T ·ln( N )
 
     The adjustment ratio in this case depends upon the two adjustment resistances R 1  and R 1 ′ connected in parallel to the emitter E 2  of the second bipolar transistor Q 2 . 
       FIG. 11 , in a way similar to  FIG. 7 , shows a variant  400 ″ of the circuit of  FIG. 10  where all the MOSFETs are in cascode configuration, including the MOSFETs M 21  and M 22  that identify the buffers  402   a  and  402   b . A first biasing voltage V p1  is supplied to the further MOSFETs (M 23   c , M 24   c , M 25   cc ) of the current mirror  403 ″, and a second biasing voltage V p2  is supplied to the further MOSFETs M 21   c  and M 22   c  that implement the n-type current mirror  402 ″. 
     Hence, from the description the advantages of the solution described emerge clearly. 
     The circuit arrangement described enables a low consumption to be obtained in the generation of a bandgap reference voltage with CMOS technology, with a reduction of current consumption of approximately 33%, via a circuit that comprises only two current paths between the supply and ground in the module for generation of the base-emitter voltage, without the use, however, of operational amplifiers for supplying the reference voltage at output. 
     The reduction of current consumption is particularly important in so far as reference-voltage generation circuits are one of the most important modules for design of analog and digital circuits such as DRAMs, flash memories, voltage regulators, analog-to-digital converters, etc. 
     Of course, without prejudice to the principle of the solution described, the details and the embodiments may vary, even considerably, with respect to what has been described herein purely by way of example, without thereby departing from the sphere of protection of the present invention, which is defined by the annexed claims.