Patent Publication Number: US-8975613-B1

Title: Resistive-switching memory elements having improved switching characteristics

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation-in-Part application of U.S. application Ser. No. 12/114,667, filed on May 2, 2008 and issued as U.S. Pat. No. 8,144,498 on Mar. 27, 2012, which claims priority to U.S. Provisional Application No. 60/928,648, filed May 9, 2007. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor memories. More specifically, resistive-switching memory elements having improved switching characteristics are described. 
     BACKGROUND OF THE INVENTION 
     Non-volatile memories are semiconductor memories that retain their contents when unpowered. Non-volatile memories are used for storage in electronic devices such as digital cameras, cellular telephones, and music players, as well as in general computer systems, embedded systems and other electronic devices that require persistent storage. Non-volatile semiconductor memories can take the form of removable and portable memory cards or other memory modules, can be integrated into other types of circuits or devices, or can take any other desired form. Non-volatile semiconductor memories are becoming more prevalent because of their advantages of having small size and persistence, having no moving parts, and requiring little power to operate. 
     Flash memory is a common type of non-volatile memory used in a variety of devices. Flash memory uses an architecture that can result in long access, erase, and write times. The operational speeds of electronic devices and storage demands of users are rapidly increasing. Flash memory is proving, in many instances, to be inadequate for non-volatile memory needs. Additionally, volatile memories (such as random access memory (RAM)) can potentially be replaced by non-volatile memories if the speeds of non-volatile memories are increased to meet the requirements for RAM and other applications currently using volatile memories. 
     Resistive-switching memories are memories that include a resistive-switching material (e.g. a metal oxide) that changes from a first resistivity to a second resistivity upon the application of a set voltage, and from the second resistivity back to the first resistivity upon the application of a reset voltage. Existing resistive-switching memories have switching characteristics (e.g. set, reset, and forming voltages, retention) that are unsuitable for some applications. 
     Thus, what is needed is a resistive-switching memory element with improved switching characteristics. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings: 
         FIG. 1  illustrates a memory array of resistive switching memory elements; 
         FIG. 2  illustrates a memory element including a resistive-switching material and a select element; 
         FIGS. 3 and 4  are band diagrams and that illustrate energy levels in a memory element with ( FIG. 3 ) and without ( FIG. 4 ) an interface layer; 
         FIG. 5  is a graph illustrating the dependency of forming voltage on the presence of an interface layer; 
         FIG. 6  illustrates a memory element that shares an electrode with a diode that is used as a select element; 
         FIG. 7  illustrates a portion of a three-dimensional memory array using memory elements described herein; 
         FIGS. 8A and 8B  illustrate the memory element and the creation and manipulation of oxygen vacancies (defects) within the memory element using an interface layer; 
         FIG. 9  is a logarithm of current (I) versus voltage (V) plot for a memory element; 
         FIG. 10  is a current (I) versus voltage (V) plot for a memory element that demonstrates a resistance state change; 
         FIGS. 11 and 12  are graphs showing the relationship between thicknesses of a metal oxide layer and resulting set voltages, reset voltages, and on/off current ratios for several materials (metal oxides) used in memory elements described herein; and 
         FIGS. 13 and 14  are flowcharts describing processes and for controlling interface layers. 
     
    
    
     DETAILED DESCRIPTION 
     A detailed description of one or more embodiments is provided below along with accompanying figures. The detailed description is provided in connection with such embodiments, but is not limited to any particular example. The scope is limited only by the claims and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided for the purpose of example and the described techniques may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the embodiments has not been described in detail to avoid unnecessarily obscuring the description. 
     According to various embodiments, resistive-switching memory elements are described herein. The memory elements generally have a metal-insulator-metal (MIM) structure in which at least one insulating layer is surrounded by two conductive electrodes. Some embodiments described herein are memory elements that include electrodes of different materials (e.g. one electrode is doped silicon and one is titanium nitride) surrounding a switching layer of a higher-bandgap material (e.g. hafnium oxide (HfO 2 ), bandgap=5.7 eV, thickness ˜20-100 Å) and a coupling layer of a material having a bandgap that is greater than or approximately equal to that of the switching layer (e.g. zirconium oxide (ZrO 2 ), bandgap=5.8 eV; or aluminum oxide (Al 2 O 3 ), bandgap=8.4 eV). The coupling layer has a thickness that is less than 25 percent the thickness of the switching layer, and memory elements including the coupling layer have exhibited improved switching characteristics (e.g. lower set, reset, and forming voltages, and better retention). 
     In other embodiments, a metal-rich metal oxide switching layer and techniques for forming the metal-rich switching layer are described. The metal-rich switching layer includes increased numbers of defects (e.g. oxygen vacancies), which can be manipulated to improve switching characteristics. The metal-rich switching layer can be deposited, for example, by reducing the amount of oxidant that is introduced during an atomic layer deposition (ALD) process. In further embodiments, techniques for removing or controlling the size of an interface layer between an electrode and a switching layer deposited thereon are described. 
     I. Switching Operation 
     It is believed that the resistive switching of the memory elements described herein is caused by defects in a metal oxide switching layer of the memory element. Generally, defects are formed in or already exist in the deposited metal oxide, and existing defects can be enhanced by additional processes. For example, physical vapor deposition (PVD) processes and atomic layer deposition (ALD) processes deposit layers that can have some imperfections or flaws. Defects may take the form of variances in charge in the structure of the metal oxide: some charge carriers may be absent from the structure (i.e. vacancies), additional charge carriers may be present (i.e. interstitials), or one element can substitute for another (i.e. substitutional). 
     The defects are thought to be electrically active defects (also known as traps) in the bulk of the metal oxide and/or at the interface of the metal oxide and adjoining layers. It is believed that the traps can be filled by the application of a set voltage (to switch from a high to a low resistance state), and emptied by applying a reset voltage (to switch from the low to the high resistance state). Traps can be inherent in the as-deposited metal oxide (i.e., existing from formation of the metal oxide) or created and/or enhanced by doping and other processes. Doping can be performed using adjacent “doping” layers that interdiffuse with the switching layer, using implantation, or using other techniques. 
     It is believed that the defects in the switching layer form conductive percolation paths upon the application of the set voltage. It is further believed that the percolation paths are removed upon the application of a reset voltage. For example, a hafnium oxide layer may include oxygen or hafnium vacancies or oxygen or hafnium interstitials that may form traps which can be used to create percolation paths and alter the conductivity of the hafnium oxide layer. 
     The switching characteristics of the resistive-switching memory elements can be tailored by controlling the defects within the metal oxides. Switching characteristics include operating voltages (e.g. set, reset, and forming voltages), operating currents (e.g. on and off currents), and data retention. Defect control is achieved by type, density, energy level, and spatial distribution within the switching layer. These defects then modulate the current flow based on whether they are filled (passivated/compensated) or unfilled (uncompensated). Adding different layers, controlling the formation of the switching layer, implanting, controlling stress, certain thermal treatments are all used to control the defect characteristics. In addition, the defects need not be mobile. For example, a coupling layer  212  (see  FIG. 2 ) and an interface layer  214  (see FIGS.  2  and  8 A- 8 B) can be used to control locations, depths, densities, and/or type of defects, and techniques can be used to form a switching layer having an increased number of defects. 
     Additionally, the metal oxide switching layer can have any phase (e.g., crystalline and amorphous) or mixtures of multiple phases. Amorphous-phase metal oxides may have increased resistivity, which in some embodiments can lower the operational currents of the device to reduce potential damage to the memory element. 
     II. Memory Structure 
     A. Memory Array 
       FIG. 1  illustrates a memory array  100  of resistive switching memory elements  102 . Memory array  100  may be part of a memory device or other integrated circuit. Memory array  100  is an example of potential memory configurations; it is understood that several other configurations are possible. 
     Read and write circuitry may be connected to memory elements  102  using signal lines  104  and orthogonal signal lines  106 . Signal lines such as signal lines  104  and signal lines  106  are sometimes referred to as word lines and bit lines and are used to read and write data into the elements  102  of array  100 . Individual memory elements  102  or groups of memory elements  102  can be addressed using appropriate sets of signal lines  104  and  106 . Memory element  102  may be formed from one or more layers  108  of materials, as is described in further detail below. In addition, the memory elements  102  shown can be stacked in a vertical fashion to make multi-layer 3-D memory arrays (see  FIG. 7 ). 
     Any suitable read and write circuitry and array layout scheme may be used to construct a non-volatile memory device from resistive switching memory elements such as element  102 . For example, horizontal and vertical lines  104  and  106  may be connected directly to the terminals of resistive switching memory elements  102 . This is merely illustrative. 
     If desired, other electrical devices may be associated (i.e., be one or more of the layers  108 ) with each memory element  102  (see, e.g.,  FIG. 2 ). These devices, which are sometimes referred to as select elements, may include, for example, diodes, p-i-n diodes, silicon diodes, silicon p-i-n diodes, transistors, Schottky diodes, etc. Select elements may be connected in series in any suitable locations in memory element  102 . 
     B. Memory Element 
     1. MIM Structure 
       FIG. 2  illustrates a memory element  102  including a resistive-switching material and a select element (a diode  202 ). The memory element  102  includes a metal-insulator-metal (MIM)-style stack  204  (in some embodiments, one or more of the metal layers can be a conductive semiconductor material such as doped silicon). The stack  204  includes two electrodes  206  and  208  and a resistive-switching layer  210  (e.g. an insulator or metal oxide). The electrodes  206  and  208  can be metals, metal oxides, or metal nitrides (e.g. Pt, Ru, RuO 2 , Ir, IrO 2 , TiN, W, TaN, MoN, MoOx), or can be doped silicon, for example p- or n-type doped polysilicon. The resistive-switching layer  210  can be a metal oxide or other switching material. In some embodiments, the resistive-switching layer  210  is a high bandgap (i.e. bandgap greater than four electron volts (eVs)) material such as HfO 2 , Ta 2 O 5 , Al 2 O 3 , Y 2 O 3 , and ZrO 2  (see  FIGS. 11 and 12 ). 
     a. Switching Layer 
     The switching layer  210  can have any desired thickness, but in some embodiments can be between 10 and 100 Å, between 20 and 60 Å, or approximately 50 Å. The switching layer  210  can be deposited using any desired technique, but in some embodiments described herein is deposited using ALD, or a combination of ALD and PVD. In other embodiments, the switching layer  210  can be deposited using low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), liquid deposition processes, and epitaxy processes. 
     The switching layer  210  additionally can be metal-rich (e.g. HfO 1.7  vs. HfO 2 ) such that the elemental composition of the switching layer  210  is less than stoichiometric (e.g. less than HfO 2 ). The switching layer  210  can have a deficit of oxygen, which manifests as oxygen vacancy defects. The additional defects can lead to reduced and more predictable switching and forming voltages of the memory element  102 . Techniques for depositing a metal-rich switching layer  210  are described in  FIG. 13 . 
     b. Coupling Layer 
     The stack  204  can also include a coupling layer  212 , which may be another metal oxide such as ZrO 2  or Al 2 O 3 . In other embodiments, the coupling layer  212  can be deposited as a metal layer that will oxidize upon the deposition of the adjacent electrode  208  or upon annealing. The coupling layer  212  can, for example, facilitate switching at the electrode  208  by creating defects near the electrode  208 . The coupling layer  212  can be thinner than the resistive-switching layer  210 , for example the coupling layer  212  can have a thickness that is less than 25% of the thickness of the resistive-switching layer  210 , or a thickness that is less than 10% of the thickness of the resistive-switching layer  210 . For example, the resistive-switching layer  210  can be a 20-60 Å layer, and the interface layer  212  can be a 5-10 Å layer. 
     The coupling layer  212  in some embodiments has a bandgap that is approximately equal to or greater than a bandgap of the switching layer  210 . The higher bandgap of the coupling layer  212  can help improve retention of the memory element  102  by reducing leakage from the switching layer  210 . Additionally, the coupling layer  212  can create defects near the electrode  208  (including in near or at the interface between the coupling layer and the switching layer  210  and/or near or at the interface between the electrode  208  and the coupling layer  212 ), which can assist in switching. The coupling layer  212  is thin enough to provide access to defects in the switching layer  210 . 
     c. Interface Layer 
     The stack  204  further may include an interface layer  214  between the electrode  206  and the switching layer  210 . The interface layer  214  can be an oxide of the material of the electrode  206  that is formed as a result of and during the deposition of the switching layer  210 , for example as a result of thermal oxidation during processing. The interface layer  214  can, in some embodiments, alter defects in the switching layer  210  (see, e.g.  FIGS. 8A-8B ). In other embodiments, it may be desirable to eliminate the interface layer  214  to reduce forming voltage or to enable switching. It is believed that in some embodiments, the interface layer  214  can hinder effective electron injection into the switching layer  210  that enables traps to be filled, which thereby increases forming voltage or causes excessive potential drop across it, producing high electric fields in the switching layer  210  and preventing switching. Techniques for controlling the size of or eliminating the interface layer  214  are described in  FIGS. 13 and 14 . 
       FIGS. 3 and 4  are band diagrams  300  and  400  that illustrate energy levels in a memory element with ( FIG. 3 ) and without ( FIG. 4 ) an interface layer  214 . For each of the band diagrams  300  and  400 , there are corresponding electric field diagrams  320  and  340  that illustrate the strength of the electric field within a certain region of the memory element  102 . 
     In the band diagram  300 , a memory element has a titanium nitride electrode  302 , a zirconium oxide coupling layer  304 , a hafnium oxide switching layer  306 , a silicon oxide interface layer  308 , and an n-type polysilicon electrode  310 . In the band diagram  400 , a memory element has a titanium nitride electrode  402 , a zirconium oxide coupling layer  404 , a hafnium oxide switching layer  406 , and an n-type polysilicon electrode  408 . As is shown in the electric field diagram  320 , the electric field is reduced by a large amount  322  in the interface layer  314 . Increased switching voltages may be necessary to overcome the electric field reduction in the interface layer  214 . If the interface layer  214  is thick enough, the entire electric field may be lost to the interface layer  214 , which may prevent switching altogether. Alternatively, as is shown in the electric field diagram  420 , in the memory element without the interface layer  214  the electric field is reduced evenly  422  throughout the memory element  102 , including in the switching layer  210 , which can reduce switching voltages and lead to more predictable switching. However, as is described regarding  FIGS. 8A and 8B , it may be desirable to retain a controlled-thickness interface layer  214  to increase the number of defects in the switching layer  210 . 
       FIG. 5  is a graph  500  illustrating the dependency of forming voltage on the presence of an interface layer  214 . Three sets of memory elements were prepared:
         A first set of memory elements represented by diamonds  502  includes a titanium nitride electrode  206 , a PVD-deposited hafnium oxide switching layer  210 , and a platinum electrode  208  without a coupling layer  212 .   A second set of memory elements represented by squares  504  includes an n-type polysilicon electrode  206 , an ALD-deposited hafnium oxide switching layer  210 , and a titanium nitride electrode  208  without a coupling layer  212 .   A third set of memory elements represented by a circle  506  includes an n-type polysilicon electrode  206 , a PVD-deposited hafnium oxide switching layer  210 , and a platinum electrode  208  without a coupling layer  212 .       

     The graph  500  shows the median forming voltage of the memory elements as a function of the thickness of the switching layer in the memory elements. As can be seen, for a switching layer having the same thickness, the elements  502  including PVD hafnium oxide on titanium nitride have the lowest forming voltage, elements  506  including PVD hafnium oxide on polysilicon have the next lowest forming voltage, and elements  504  having ALD hafnium oxide on polysilicon have the highest forming voltage. It is believed that ALD processes are more likely to form a thicker interface layer  214  at least partly because of potentially higher processing temperatures (200° C. or greater versus room temperature for some instances of PVD), which leads to increased forming voltages. Additionally, the silicon oxide interface layer  214  created on polysilicon electrodes (e.g. the elements  502  and  506 ) is less conductive than an oxide created on a metal-containing electrode such as titanium nitride. Therefore, techniques for reducing and/or controlling the interface layer  214 , especially for silicon-based electrodes, can be used to improve forming voltages. 
     Although ALD process may be more likely to form thicker interface layers  214  and result in memory elements having increased forming voltages, it may be desirable to use ALD processing over PVD processing for other reasons (e.g. to form more conformal layers), and  FIG. 13  describes a process for reducing or eliminating the interface layer  214  using ALD processing. Additionally, as is described regarding  FIGS. 8A and 8B , it may be desirable to retain a controlled-thickness interface layer  214  (e.g. less than or equal to 10 Å) to increase the number of defects in the switching layer  210 , which can also be formed using the process of  FIG. 13 . 
     If it is desirable to have an interface layer  214 , the order of deposition of the layers of the MIM stack  204  may be important. Since the interface layer  214  is formed during the deposition of the switching layer  210 , the switching layer  210  can be formed on the electrode that the interface layer  214  is to be formed from (e.g. formed on the polysilicon layer if a silicon oxide interface layer  214  is desired). As an example, and as is discussed further in  FIG. 7 , when forming a three-dimensional memory array, it may be necessary to always form the memory element in the same orientation (e.g. one electrode always on the bottom), even when the orientation of other elements is to be reversed. In other embodiments however, the interface layer  214  can be created when the memory element  102  is deposited in reverse order by using a post deposition anneal of the memory element  102 . 
     d. Electrodes 
     The electrodes  206  and  208  can be different materials. In some embodiments, the electrodes have a work function that differs by between 0.1 and 1 electron volt (eV), or by between 0.4 and 0.6 eV, etc. For example, the electrode  208  can be TiN, which has a work function of 4.5-4.6 eV, while the electrode  206  can be n-type polysilicon, which has a work function of approximately 4.1-4.15 eV. Other electrode materials include p-type polysilicon (4.9-5.3 eV), tungsten (4.5-4.6 eV), tantalum nitride (4.7-4.8 eV), molybdenum oxide (approximately 5.1 eV), molybdenum nitride (4.0-5.0 eV), iridium (approximately 5.3 eV), iridium oxide (approximately 4.2 eV), ruthenium (approximately 4.7 eV), and ruthenium oxide (approximately 5.0 eV). For some embodiments described herein, the higher work function electrode receives a positive pulse (as measured compared to a common reference potential) during a reset operation, although other configurations are possible. In other embodiments, the higher work function electrode receives a negative pulse during a reset operation. In some embodiments, the memory elements  102  use bipolar switching where the set and reset voltages have opposite polarities relative to a common electrical reference, and in some embodiments the memory elements  102  use unipolar switching where the set and reset voltages have the same polarity. 
     2. Select Elements 
     The diode  202  is a select element that can be used to select a memory element for access from amongst several memory elements such as the several memory elements  102  of the memory array  100  (see  FIG. 1 ). The diode  202  controls the flow of current so that current only flows one way through the memory elements  102 . 
     The diode  202  may include two or more layers of semiconductor material. A diode is generally a p-n junction, and doped silicon layers  216  and  218  can form the p-n junction. For example, doped silicon layer  216  can be a p-type layer and doped silicon layer  218  can be an n-type layer, so that a node  220  of the diode  202  is an anode and is connected to the first electrode  206 . In this example, a node  222  of the diode  202  is a cathode and is connected to the signal line  106 , which may be, for example, a bit line or word line, or connected to a bit line or word line. The nodes  220  and  222  are not necessarily physical features in the memory element  102 , for example the electrode  206  may be in direct contact with the doped silicon layer  216 . In other embodiments, one or more additional layers such as a low resistivity film are added between the electrode  206  and the doped silicon layer  216 . 
     In some embodiments, doped silicon layer  216  is an n-type layer and doped silicon layer  218  is a p-type layer, and the node  220  is a cathode of the diode  202  and the node  222  is an anode of the diode  202 . An optional insulating layer  224  can be between the doped silicon layers  216  and  218  to create a p-i-n or n-i-p diode  202 . In some embodiments the insulating layer  224  and one of the doped silicon layers  216  and  218  are formed from the same layer. For example, a silicon layer can be deposited, and a portion of the layer can be doped to form the doped silicon layer  216  or  218 . The remaining portion of the layer is then the insulating layer  224 . 
     In other embodiments, one electrode of the memory element  102  can be doped silicon (e.g. p-type or n-type polysilicon), which can also act as a portion of the diode  202 .  FIG. 6  illustrates a memory element  102  that shares an electrode with a diode  202  that is used as a select element. Since the diode  202  is made up of two layers of doped silicon, and since a layer of doped silicon can be used as an electrode of the memory element  202 , a single layer of doped silicon (e.g. a layer of n-type polysilicon) can serve as an electrode of the memory element  102  and as a layer of the diode  202 . By sharing a doped silicon layer between the diode  202  and the memory element  102 , two layers, one doped silicon layer and a coupling layer between the diode  202  and the memory element  102 , and their associated processing steps, can be eliminated. 
     3. Switching Polarity 
     A signal line (e.g. the signal line  104 ) is connected to the “second” electrode  208 , and the signal line is configured to provide switching voltages to the second electrode  208 . In some embodiments, the second electrode  208  has a higher work function than the first electrode  206 , and the signal line  104  is configured to provide a negative set voltage relative to a common electrical reference, and a positive reset voltage relative to the common electrical reference. The embodiments may include those using a lower work function first electrode  206  (e.g. titanium nitride) and a higher work function second electrode such as platinum or ruthenium. For example, the common electrical reference may be ground (i.e. 0V), the set voltage would then be a negative voltage (e.g. −2V), and the reset voltage would be a positive voltage (e.g. 2V). The common electrical reference can be any voltage, however, such as +2V or −2V. 
     In other embodiments, the second electrode  208  also has a higher work function than the first electrode  206 , and the signal line  104  is configured to provide a positive set voltage and a negative reset voltage relative to a common electrical reference. For example, in a memory element having a doped silicon first electrode  206  (e.g. n-type polysilicon) and a higher work function second electrode  208  (e.g. titanium nitride), the reset voltage can be negative at the second electrode  208 . 
     Generally, in some embodiments, one switching voltage (e.g. the reset voltage) of the memory element can have a first polarity (e.g. a positive polarity) relative to the common electrical reference, and the other switching voltage (e.g. the set voltage) can have a negative polarity relative to the common electrical reference so that the memory element uses bipolar switching. In other embodiments, the switching voltages have the same polarity relative to a common reference and are referred to as unipolar switching. Additionally, the switching voltages can be voltage pulses (e.g. square wave pulses) having a limited duration, for example less than 1 ms, less than 50 μs, less than 1 μs, less than 50 ns, etc. 
     4. Polarity of Forming Voltage 
     Lower operating voltages are desirable for resistive switching memory elements to protect associated devices (e.g. diodes) in the memory array. Forming voltage is often the highest magnitude operating voltage, and reduction of the forming voltage is therefore an important goal to improve device operation and reliability. Forming voltage polarity has been shown to affect forming voltage magnitude in some embodiments. 
     In one example, memory elements were prepared with a higher work function electrode connected to ground and a lower work function electrode receiving the forming voltage pulse. A first example included an n-type polysilicon electrode, a hafnium oxide switching layer and a titanium nitride electrode. In this example, the titanium nitride electrode (i.e. the higher work function electrode) was grounded and positive and negative forming voltage pulses were applied to the n-type polysilicon electrode. The negative pulses had a median forming voltage of approximately −8V, while the positive pulses had a median forming voltage of approximately +13V. In a second example, a memory element was prepared having a titanium nitride electrode, a hafnium oxide switching layer, and a platinum electrode. The higher work function electrode (here, the platinum electrode) was grounded, and the lower work function electrode (the titanium nitride electrode) received forming voltage pulses. In this example, the median forming voltage of negative pulses was −4.4V, while the median forming voltage using positive pulses was 6.4V. 
     The examples above demonstrate that a negative forming voltage applied at the lower-work function electrode can reduce the magnitude of forming voltage in some embodiments. It is believed that electron injection from the lower-work function electrode can reduce the magnitude of a negative polarity forming voltage compared to a positive polarity forming voltage. 
     Additionally, it has been demonstrated for some embodiments that the greater the difference between the work function of the electrodes in a memory element, the smaller the magnitude of the forming voltage. For example, in a memory element with an n-type polysilicon electrode, a hafnium oxide switching layer and a titanium nitride electrode, the difference in work function is approximately 0.5 eV and a median forming voltage is −7V. Another memory element having an n-type polysilicon electrode, a hafnium oxide switching layer, and a platinum electrode has a work function difference of 1.6 eV and a median forming voltage of −5.5V. Therefore, in some embodiments it may be desirable to increase the work function difference between the electrodes to reduce the forming voltage, although it may not be necessary to increase the work function difference to 1.6 eV as in the example. 
     5. Other Characteristics 
     It may be desirable to have a low-leakage material as the resistive-switching layer  210  in order to aid memory retention. For example, the layer  210  may be a material that has a leakage current density less than 40 amps per square centimeter (A/cm 2 ) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide in an off state (e.g. a high resistance state) of the memory element. 
     6. 3-D Memory Structure 
       FIG. 7  illustrates a portion of a three-dimensional memory  700  array using memory elements  102  described herein. The array  700  includes two word lines  702   a  and  702   b , and a shared bit line  704 . Two MIM stacks  204   a  and  204   b  and diodes  202   a  and  204   b  are shown in the array  700 ; a memory cell  706   a  includes an MIM stack  204   a  and a diode  202   a , and a memory cell  706   b  includes an MIM stack  204   b  and a diode  202   b.    
     The memory array  700  is configured so that the two memory cells  706   a  and  706   b  can use the same shared bit line  704 . As shown here, the MIM stacks  204   a  and  204   b  both have their individual layers (i.e. electrodes  206  and  208  and switching layer  210 ) built in the same order. In other words, for both MIM stacks  204   a  and  204   b , the electrode  206  is formed first, the switching layer  210  is formed on top of the electrode  206 , and the electrode  208  is formed on top of the switching layer  210 . As mentioned above, the order of deposition of the layers of the MIM stacks  204  may need to be the same in order to create an interface layer  214 . However, in some embodiments the order of deposition can be reversed and the interface layer  214  created as a result of subsequent processes such as electrode deposition or annealing. 
     The diodes  202   a  and  202   b , on the other hand, are minors of each other. In other words the diode  202   a  has the layer  216  on the bottom, and the diode  202   b  has the layer  218  on the bottom. For example, the layer  216  may be the n-type layer and the layer  218  may be the p-type layer. Using this configuration, the diodes  202   a  and  202   b  are biased in opposite directions, which allows the memory cells  706  to both use the same shared bit line  704 . As is shown in circuit diagrams  708   a  and  708   b , the diodes can have any desired orientation, and the orientation may differ based on the configuration of the three-dimensional memory array. 
     7. Interface Layer and Oxygen Vacancies 
       FIGS. 8A and 8B  illustrate the memory element  102  and the creation and manipulation of oxygen vacancies (defects) within the memory element  102  using an interface layer  214 . The interface layer  214  is an oxide layer that can be created during the processing of other layers in the memory element  102 . For example, the deposition of the switching layer  210  may include processing at a temperature (e.g. 200° C. or greater) to create the interface layer  214 . If, for example, the electrode  206  is doped silicon (e.g. polysilicon), the deposition of the switching layer  210  (using, for example, PVD or ALD) may include temperatures that can create a silicon oxide interface layer  214 . The interface layer  214  can be eliminated in some embodiments, but in other embodiments, the interface layer  214  can be retained to improve retention of the switching layer  210  by improving leakage characteristics and to modulate defects (e.g. oxygen vacancies) in the switching layer  210 . In some embodiments where the interface layer  214  is retained, the interface layer  214  may be relatively thin (e.g. less than or equal to 10 Å) to make the defects in the switching layer  210  visible to the electrode  206  (i.e. the interface layer  214  provides access to the defects of the switching layer  210 ) and to reduce the effect of the interface layer  214  on switching voltages. 
     In one example, the bottom electrode  206  is polysilicon. Silicon, particularly, is known for attracting oxygen when heated and can draw oxygen from the metal oxide switching layer  210 , leaving oxygen vacancies  802  in the switching layer  210  nearby creating a metal-rich metal oxide switching layer. Without being bound by theory, these oxygen vacancies  802  can serve as traps which modulate the current flow with the application of programming voltages to fill and empty such traps. The oxygen vacancies  802  need not be mobile. 
     A thin or zero interlayer thickness interface layer  214  can be used to modulate the density of oxygen vacancies  802  in the switching layer  210 . For example, a thinner interface layer  214  (e.g. 5 Å vs. 10 Å) can increase the oxygen vacancy  802  density. Additionally, the thickness of the switching layer  210  can be optimized such that traps (e.g. oxygen vacancies  802 ) are more spatially equalized throughout the switching layer  210 . For example,  FIG. 8A  shows a thicker switching layer  210 , which has oxygen vacancies  802  concentrated near the interface layer  214 , while  FIG. 8B  shows a thinner switching layer  210  that has a more even distribution of oxygen vacancies  802 . For example, in two memory elements using the same materials, the switching layer  210  of  FIG. 8A  may be 50 Å while the thickness of the switching layer  210  in  FIG. 8B  is 25 Å. The distribution of oxygen vacancies  802  within the switching layer  210  can depend on several factors, including the materials used, the thickness of the interface layer  214 , the processes used (e.g. temperatures of anneals used), etc.  FIGS. 8A and 8B  are only two examples of oxygen vacancy distribution, and it is understood that various other configurations are possible. 
     III. Memory Operation 
     During a read operation, the state of a memory element  102  can be sensed by applying a sensing voltage (i.e., a “read” voltage V READ ) to an appropriate set of signal lines  104  and  106 . Depending on its history, a memory element that is addressed in this way may be in either a high resistance state or a low resistance state. The resistance of the memory element therefore determines what digital data is being stored by the memory element. If the memory element has a low resistance, for example, the memory element may be said to contain a logic one (i.e., a “1” bit). If, on the other hand, the memory element has a high resistance, the memory element may be said to contain a logic zero (i.e., a “0” bit). During a write operation, the state of a memory element can be changed by application of suitable write signals to an appropriate set of signal lines  104  and  106 . 
       FIG. 9  is a logarithm of current (I) versus voltage (V) plot  900  for a memory element  102 .  FIG. 9  illustrates the set and reset operations to change the contents of the memory element  102 . Initially, memory element  102  may be in a high resistance state (“HRS”, e.g., storing a logic zero). In this state, the current versus voltage characteristic of memory element  102  is represented by solid line HRS  902 . The high resistance state of memory element  102  can be sensed by read and write circuitry using signal lines  104  and  106 . For example, read and write circuitry may apply a read voltage V READ  to memory element  102  and can sense the resulting “off” current I OFF  that flows through memory element  102 . When it is desired to store a logic one in memory element  102 , memory element  102  can be placed into its low-resistance state. This may be accomplished by using read and write circuitry to apply a set voltage V SET  across signal lines  104  and  106 . Applying V SET  to memory element  102  causes memory element  102  to switch to its low resistance state, as indicated by dashed line  906 . In this region, the memory element  102  is changed so that, following removal of the set voltage V SET , memory element  102  is characterized by low resistance curve LRS  904 . As is described further below, the change in the resistive state of memory element  102  may be because of the filling of traps (i.e., a may be “trap-mediated”) in a metal oxide material. V SET  and V RESET  can be generally referred to as “switching voltages.” 
     The low resistance state of memory element  102  can be sensed using read and write circuitry. When a read voltage V READ  is applied to resistive switching memory element  102 , read and write circuitry will sense the relatively high “on” current value I ON , indicating that memory element  102  is in its low resistance state. When it is desired to store a logic zero in memory element  102 , the memory element can once again be placed in its high resistance state by applying a reset voltage V RESET  to memory element  102 . When read and write circuitry applies V RESET  to memory element  102 , memory element  102  enters its high resistance state HRS, as indicated by dashed line  908 . When the reset voltage V RESET  is removed from memory element  102 , memory element  102  will once again be characterized by high resistance line HRS  904 . Voltage pulses can be used in the programming of the memory element  102 . For example, a 1 ms, 10 μs, 5 μs, 500 ns, etc. square pulse can be used to switch the memory element  102 ; in some embodiments, it may be desirable to adjust the length of the pulse depending on the amount of time needed to switch the memory element  102 . 
     A forming voltage V FORM  is a voltage applied to the memory element  102  to ready the memory element  102  for use. Some memory elements described herein may need a forming event that includes the application of a voltage greater than or equal to the set voltage or reset voltage. Once the memory element  102  initially switches the set and reset voltages can be used to change the resistance state of the memory element  102 . 
     The bistable resistance of resistive switching memory element  102  makes memory element  102  suitable for storing digital data. Because no changes take place in the stored data in the absence of application of the voltages V SET  and V RESET , memory formed from elements such as element  102  is non-volatile. 
       FIG. 10  is a current (I) versus voltage (V) plot  1000  for a memory element  102  that demonstrates a resistance state change. The plot  1000  shows a voltage ramp applied to the memory element  102  along the x-axis and the resulting current along a y-axis. The line  1002  represents the response of an Ohmic material when the ramped voltage is applied. An Ohmic response is undesirable, since there is no discrete voltage at which the set or reset occurs. 
     Generally, a more abrupt response like graph  1004  is desired. The graph  1004  begins with an Ohmic response  1004   a , and then curves sharply upward  1004   b . The graph  1004  may represent a set operation, where the memory element  102  switches from the HRS  902  to the LRS  904 . 
     Without being bound by theory, non-metallic percolation paths are formed during a set operation and broken during a reset operation. For example, during a set operation, the memory element  102  switches to a low resistance state. The percolation paths that are formed by filling traps increase the conductivity of the metal oxide, thereby reducing (i.e., changing) the resistivity. The voltage represented by  404   b  is the set voltage. At the set voltage, the traps are filled and there is a large jump in current as the resistivity of the metal oxide decreases. 
     IV. Materials 
     A variety of metal oxides can be used for the switching layer  210  of the memory elements  102  described herein. In some embodiments, the memory elements  102  exhibit bulk-switching properties and are scalable. In other words, it is believed that defects are distributed throughout the bulk of the switching layer  210 , and that the switching voltages (i.e. V SET  and V RESET ) increase or decrease with increases or decreases in thickness of the metal oxide. In other embodiments, the memory elements  102  exhibit interface-mediated switching activity. Other embodiments may exhibit a combination of bulk- and interface-mediated switching properties, which may be scalable while still exhibiting defect activity at layer interfaces. 
     A. Higher-Bandgap Materials for Switching Layer 
       FIGS. 11 and 12  are graphs showing the relationship between thicknesses of a metal oxide layer and resulting set voltages, reset voltages, and on/off current ratios for several materials (metal oxides) used in memory elements described herein. These graphs illustrate the characteristics of a memory element that includes two electrodes and a single layer of metal oxide disposed in between (i.e. without a coupling layer  212 ) and indicate that certain materials exhibit bulk-switching properties. As can be seen in  FIG. 11 , for memory elements including hafnium oxide  1102 , aluminum oxide  1104 , or tantalum oxide  1106 , set voltage increases with (i.e. is dependent on) thickness, and in some embodiments and for these materials the set voltage is at least one volt (V) per one hundred angstroms (Å) of the thickness of a metal oxide layer in the memory element. In some embodiments, an increase in the thickness of the metal oxide layer of 100 Å increases the set voltage by at least 1V. Similarly, as shown in  FIG. 12 , reset voltage for hafnium oxide  1202 , aluminum oxide  1204 , or tantalum oxide  1206  also depends on thickness. These data therefore support a bulk-controlled set/reset mechanism for these materials, since a linear relationship indicates the formation of percolation paths throughout the bulk of the metal oxide. In other words, for a thicker material, more voltage is needed to fill the traps. 
     Hafnium oxide (HfO 2 , 5.7 electron volts (eV)), aluminum oxide (Al 2 O 3 , 8.4 eV) and tantalum oxide (Ta 2 O 5 , 4.6 eV) all have a bandgap greater than 4 eV, while titanium oxide (TiO 2 , 3.0 eV) and niobium oxide (Nb 2 O 5 , 3.4 eV) have bandgaps less than 4 eV. Other higher bandgap metal oxides that can be used with various embodiments described herein include yttrium oxide (Y 2 O 3 , 6.0 eV) and zirconium oxide (ZrO 2 , 5.8 eV) (also see Table 1). As shown in  FIGS. 11 and 12 , set voltages for titanium oxide  1108  and niobium oxide  1110  and reset voltages for titanium oxide  1208  and niobium oxide  1210  do not increase with thickness. Therefore, a higher bandgap (i.e., bandgap greater than 4 eV) metal oxide exhibits bulk mediated switching and scalable set and reset voltages. Table 1 summarizes the higher-bandgap materials that can be used for switching layers  210 . 
                                 TABLE 1                       Material   Bandgap                          HfO 2     5.7 eV           Al 2 O 3     8.4 eV           Ta 2 O 5     4.6 eV           Y 2 O 3     6.0 eV           ZrO 2     5.8 eV                        
B. Coupling Layer Materials
 
     The coupling layer  212  can be a metal oxide material that is chosen to complement the material of the switching layer  210 . For example, the coupling layer  212  may be chosen to complement a bandgap of the switching layer  210 . In some embodiments, the coupling layer  212  has a bandgap that is approximately equal to or greater than the bandgap of the switching layer  210 . Without being bound by theory, this can improve retention of the memory element  102  by improving leakage characteristics. As is shown in the band diagrams  300  and  400  in  FIGS. 3 and 4 , a zirconium oxide coupling layer  212  has a bandgap that is greater than the bandgap of the switching layer  210 . The higher bandgap coupling layer  212  can promote retention by reducing leakage from the switching layer  210  into the electrode  208 . 
     In other examples, the coupling layer  212  can have a lower bandgap that the switching layer  210  (for example, the coupling layer  212  can be titanium oxide (bandgap=3.5 eV)), but with some systems this may result in higher operational voltages and lower yields. 
     In some examples, a switching layer  210  is hafnium oxide (bandgap=5.7 eV) and has a first thickness (e.g. 20-100 Å). The coupling layer can then be either zirconium oxide (ZrO 2 , bandgap=5.8 eV) or aluminum oxide (Al 2 O 3 , bandgap=8.7 eV) having a second thickness that is less than 25 percent of the first thickness. For example, the coupling layer can be between 1 and 10 Å thick, or 5 Å or 8 Å. 
     It has been shown (see Table 3) for some materials systems that switching performance is better when the coupling material is in a discrete coupling layer  212  rather than dispersed throughout the switching layer  210  (e.g. using a hafnium oxide switching layer  210  and an aluminum oxide coupling layer  212  rather than a HfAlOx layer). It is believed that the defects created at the interface between the coupling layer  212  and the switching layer  210  can improve switching characteristics. 
     In some embodiments, the coupling layer  212  can be used to dope into the switching layer  210 . The doping can be either aliovalent or isovalent. In aliovalent doping, the doping species has a different valency than that of the layer being doped. For example, the switching layer  210  can be hafnium oxide and the coupling layer  212  can be aluminum oxide. A typical defect species of hafnium oxide is Hf +4 , and a typical defect species of aluminum oxide is Al +3 . Al +3  ions displace Hf +4  ions in the hafnium oxide layer, thereby creating defects and traps. In some embodiments, the doping is isovalent, and a coupling layer  212  (e.g., zirconium oxide) may have a metal having the same most common oxidation state (e.g., +4) as a metal of the switching layer  210 . In these cases, aliovalent doping may still occur when other species having different oxidation states (e.g., Zr +3 ) diffuse into the switching layer  210 . 
     C. Electrodes 
     Various electrodes can be used for the memory elements  102 . Some embodiments describe memory elements  102  that use electrodes  206  and  208  that are made of different materials. For example, the electrodes  206  and  208  can have materials that are chosen to have different work functions (e.g. between 0.4 eV and 0.6 eV different, or between 0.1 eV and 1.0 eV different), which it is believed may facilitate bipolar switching in some systems. 
     Materials that can be used for electrodes  206  and  208  include doped silicon (e.g. p-type or n-type silicon), titanium nitride, tantalum nitride, tungsten, tungsten nitride, molybdenum nitride, molybdenum oxide, platinum, ruthenium, ruthenium oxide, iridium, and iridium oxide. Electrode “pairs” may include n-type polysilicon and titanium nitride; titanium nitride, tungsten nitride, or tantalum nitride and platinum, ruthenium, ruthenium oxide, iridium, iridium oxide, molybdenum nitride, or molybdenum oxide, although other pairings are possible. Other electrodes include metal silicides (see  FIG. 14 ) and electrolessly deposited electrodes (e.g. electroless nickel). These electrodes can be used to eliminate the silicon oxide interface layer  214  and therefore reduce forming voltages. 
     In some embodiments, the electrodes  206  and  208  can be chosen to dope isovalently into the switching layer  210 . In other words, at least one of the electrodes  206  and  208  has a most common oxidation state or valency that is the same as the most common oxidation state or valency of the switching layer  210 . In some memory elements  102 , it is believed that isovalent doping can create deep traps in the switching layer  210 . For example, the electrode  206  can be doped silicon (+4 valency) and the switching layer  210  can be hafnium (+4 valency) oxide. In other embodiments, the electrodes  206  or  208  can contain titanium nitride (titanium has +4 valency), platinum (+4 valency), etc. The silicon isovalently dopes into the hafnium oxide, creating deep traps that can be used to create a greater resistance change and a higher on/off current ratio. Aliovalent doping may in some instances create donors and acceptors, which are shallow traps and may result in a resistive-changing memory that does not exhibit as great a difference in resistance states. 
     D. Material Systems 
     Table 2 includes a list of possible materials systems for memory elements  102  described herein. Although certain combinations are described in Table 2, various other configurations are possible within the bounds of the memory elements  102  described herein. For example, other electrode materials (e.g. molybdenum nitride or molybdenum nitride) or switching materials can be used. 
     
       
         
           
               
               
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                   
                 Electrode 
                 Interface 
                 Switching 
                 Coupling 
                 Electrode 
               
               
                   
                 206 
                 Layer 214 
                 Layer 210 
                 Layer 212 
                 208 
               
               
                   
               
             
            
               
                 1 
                 n-type 
                 0-10Å SiOx 
                 HfOx 30-100Å 
                 AlOx 1-10Å, 
                 TiN 
               
               
                   
                 polysilicon 
                   
                 or ~50Å 
                 or ~5Å or ~8Å 
                   
               
               
                 2 
                 n-type 
                 0-10Å SiOx 
                 HfOx 30-100Å 
                 ZrOx 1-10Å, 
                 TiN 
               
               
                   
                 polysilicon 
                   
                 or ~50Å 
                 or ~5Å or ~8Å 
                   
               
               
                 3 
                 Ni, Co, Ti,  
                 Minimal 
                 HfOx 30-100Å 
                 Optional 
                 TiN 
               
               
                   
                 Pd, Pt  
                   
                 or ~50Å 
                 (AlOx, ZrOx, 
                   
               
               
                   
                 silicide 
                   
                   
                 TiOx) 
                   
               
               
                 4 
                 n-type 
                 0-10Å SiOx 
                 AlOx, TaOx, 
                 Optional 
                 TiN 
               
               
                   
                 polysilicon 
                   
                 YOx, ZrOx 30- 
                 (AlOx, ZrOx, 
                   
               
               
                   
                   
                   
                 100Å, or ~50Å 
                 TiOx) 
                   
               
               
                 5 
                 TiN 
                 0-10Å 
                 HfOx, AlOx, 
                 Optional 
                 Pt, Ru,  
               
               
                   
                   
                   
                 TaOx, YOx, 
                 (AlOx, ZrOx, 
                 RuOx, 
               
               
                   
                   
                   
                 ZrOx 30-100Å, 
                 TiOx) 
                 Ir, IrOx 
               
               
                   
                   
                   
                 or ~50Å 
                   
                   
               
               
                 6 
                 ELD Ni 
                 Minimal 
                 HfOx, AlOx, 
                 Optional 
                 Pt, Ru,  
               
               
                   
                   
                   
                 TaOx, YOx, 
                 (AlOx, ZrOx, 
                 RuOx, 
               
               
                   
                   
                   
                 ZrOx 30-100Å, 
                 TiOx) 
                 Ir, IrOx,  
               
               
                   
                   
                   
                 or ~50Å 
                   
                 TiN 
               
               
                   
               
            
           
         
       
     
     V. Processing 
       FIGS. 13 and 14  are flowcharts describing processes  1300  and  1400  for controlled deposition of interface layers  214 . The process  1300  describes the deposition of a switching layer  210  using an ALD process that reduces the amount of oxygen introduced to create a metal-rich switching layer  210  and increase the amount of defects in the switching layer  210 . Additionally, the process  1300  can be used to tailor the size of the interface layer  214  by selecting processing parameters to obtain a desired thickness of the interface layer  214 . The process  1400  describes the deposition of a silicide electrode  206  that significantly reduces or eliminates the interface layer  214 . 
     Atomic layer deposition (ALD) is a process used to deposit conformal layers with atomic scale thickness control during various semiconductor processing operations. For depositing a metal oxide, ALD is a multi-step self-limiting process that includes the use of two reagents: a metal precursor and an oxygen source (e.g. an oxidant). Generally, a first reagent is introduced into a processing chamber containing a substrate and adsorbs on the surface of the substrate. Excess first reagent is purged and/or pumped away. A second reagent is then introduced into the chamber and reacts with the adsorbed layer to form a deposited layer via a deposition reaction. The deposition reaction is self-limiting in that the reaction terminates once the initially adsorbed layer is consumed by reaction with the second reagent. Excess second reagent is purged and/or pumped away. The aforementioned steps constitute one deposition or ALD “cycle.” The process is repeated to form the next layer, with the number of cycles determining the total deposited film thickness. 
     Returning to  FIG. 13 , the process  1300  begins with depositing a bottom electrode on a substrate in operation  1302 . The bottom electrode (e.g. the electrode  206 ) may be one of the electrode materials described above; however, in one embodiment, the bottom electrode is a polysilicon electrode that may form a silicon dioxide interface layer  214  during the deposition of the switching layer  210 . In other embodiments, the bottom electrode is a metal electrode that can also oxidize during the deposition of the switching layer  210 . 
     In operation  1304 , a thin PVD metal oxide layer is optionally deposited on the substrate. The thin PVD metal oxide layer can be used to eliminate the interface layer  214  since the PVD deposition process has been shown to not promote the growth of the interface layer  214  (see e.g.  FIG. 5 ). Once the thin (e.g. &lt;10 Å) PVD metal oxide layer is deposited, the ALD process in operation  1306  can be performed. 
     In operation  1306 , a switching layer  210  is deposited using ALD. The operation  1304  includes several component operations  1308 - 1320  that describe several cycles of the ALD process. Some of these operations are optional, or may be completed in a different order. 
     In operation  1308 , the deposition temperature of the ALD process is optionally lowered. The deposition temperature may be lowered by lowering the temperature of a heated substrate pedestal (i.e. the pedestal temperature), for example. In some examples, the deposition temperature or pedestal temperature may be 250° C. or less, 200° C. or less, 175° C. or less, etc. The reduced temperature leads to incomplete ALD reactions, leaving unreacted precursor ligands in the switching layer  210 , increasing the amount of defects in the switching layer  210 . Additionally, the reduced deposition temperature can reduce or eliminate the interface layer  214  by reducing the rate of thermal oxidation. For example, when using a silicon electrode  206 , reducing the ALD deposition temperature to below 200° C. may substantially reduce any interface layer  214 . 
     In operation  1310 , the precursor source is maintained at a desired pressure. The desired pressure can be achieved by controlling the temperature of the precursor source. The precursor source may be external to the ALD deposition chamber, and may therefore be maintained at a temperature different than the temperature of the deposition chamber. The desired temperature and pressure depends on the precursor used. For example, when using tetrakis(dimethlyamino)hafnium (TDMAH) to deposit hafnium oxide, the precursor source can be maintained at 30-100° C., or 40-50° C. In some embodiments, the temperature of the precursor source can be increased to increase the partial pressure of the precursor, which can also create a more metal-rich switching layer by increasing the amount of pressure in the chamber. In operation  1212 , the precursor is introduced to the substrate including the bottom electrode to begin the ALD process. 
     Operations  1314  and  1316  describe the treatment of the oxygen source used to form the metal oxide. Depending on the characteristics of the memory element  102 , either or both of operations  1314  and  1316  can be used to control the thickness of the interface layer  214 . The oxygen source can be ozone, oxygen, water vapor, isopropyl alcohol (IPA), ethanol or another alcohol, or other ALD oxygen sources. 
     In operation  1314 , the oxygen source is maintained at a lower vapor pressure than is typical to create a switching layer  210  having less oxygen. The vapor pressure can be reduced by reducing the temperature of the oxygen source. The temperature at which the oxygen source is maintained will differ depending on the oxygen source and the metal oxide to be deposited. For example, ozone and oxygen tend to be more oxidizing (i.e. more quickly create a layer having more oxygen), while water vapor is less oxidizing, and IPA and ethanol are less oxidizing still. The lowered temperature reduces the vapor pressure of the oxygen source, which controls the amount of the oxygen source that is introduced into the deposition chamber. Restricting the amount of the oxygen source in the chamber still allows the film to be self-limiting, while reducing the amount of oxygen in the film, as some of the precursor ligands will be unbound. The oxygen-deficient film will then have oxygen vacancies, which are defects that can be used to control the switching of the memory element  102 . 
     To deposit a metal-rich hafnium oxide switching layer  210 , for example, water vapor can be used as the oxygen source, and the water vapor source can be held at a reduced temperature such as 0 to 10° C. The reduced temperature reduces the vapor pressure of the oxygen source, effectively reducing the amount of oxygen introduced into the chamber and in the resulting film. Hafnium oxide films formed using this technique can result in elemental compositions of HfO 1.2  to HfO 1.9 , or HfO 1.7 . Generally, oxygen concentrations can be reduced to 60-95% of stoichiometric compositions (i.e. the amount of oxygen is between 60 and 95% of a stoichiometric metal oxide, e.g. HfO 1.2  to HfO 1.9 ). IPA or ethanol can be used to provide oxygen, but at the same temperature will provide less oxygen than water vapor or the other oxygen sources described above. IPA or ethanol may therefore be able to deposit metal-rich films using a room temperature source, although a similar temperature reduction can also be used with IPA and ethanol to reduce the amount of oxygen in the switching layer  210 . 
     In operation  1318 , the oxygen source is introduced to the substrate to create an ALD layer of metal oxide. A single ALD cycle may deposit a film having a thickness of 0.5 Å, for example, and multiple cycles are typically needed to build a switching layer  210  of the desired thickness. In operation  1320 , if more cycles are needed, the process  1300  returns to operation  1308 . If no more cycles are needed, the process  1300  continues to operation  1322 . 
     In operation  1322 , a coupling layer is deposited. The coupling layer  212  can be a thin layer, for example less than 25 percent the thickness of the switching layer. The coupling layer  212  can be deposited using any deposition method, such as ALD, PVD, etc. In operation  1324 , the top electrode (e.g. the electrode  208 ) is deposited. 
     In operation  1326 , the memory element is annealed. The annealing can remove unreacted precursor ligands that may exist in the film because of the low deposition temperature of the ALD process. In one example, the element is annealed using a hydrogen/argon mixture (e.g. 2-10% hydrogen, 90-98% argon), although other anneals such as vacuum anneals, oxidizing anneals, etc. can be used. 
     Returning to  FIG. 14 , the process  1400  describes the formation of a bottom electrode  206  for use in the memory elements  102 . The process  1400  describes the deposition of a silicide electrode that can be used to remove the interface layer  214  if so desired. In some embodiments, a silicide electrode does not form an interface layer  214  during the deposition of the switching layer  210 . The process  1400  can in some embodiments, be used in conjunction with the process  1300 . For example, the operations  1402 - 1412  of the process  1400  can be substituted into the operation  1302  of the process  1300 . 
     In operation  1402 , a bottom electrode (e.g. the electrode  206 ) is deposited on a substrate. The bottom electrode is a metal silicide, for example a titanium, cobalt, nickel, palladium, or platinum silicide, that is deposited according to the operations  1404 - 1412 . 
     In operation  1404 , silicon is deposited on the substrate. In operation  1406 , a metal such as titanium, cobalt, nickel, molybdenum, palladium, or platinum is deposited on the silicon. In operation  1408  a thermal treatment is performed to form the silicide layer by interdiffusing the silicon into the metal. In operation  1410 , any unreacted metal is stripped from the electrode, and in operation  1412 , the electrode can be optionally annealed to lower the resistivity of the electrode. 
     After the silicide electrode is deposited, in operation  1414 , a switching layer is deposited on the electrode (for example using techniques described in the process  1300 ), and in operation  1416  a top electrode (e.g. the electrode  208 ) is deposited over the switching layer. The silicide electrode resists the formation of oxide layers, and therefore does not form the interface layer  214 . Although in some embodiments it may be desirable to retain an interface layer  214 , in others it is more desirable to eliminate the interface layer  214 , and the process  1400  is an alternative technique for doing so. 
     VI. Representative Data 
     A. Switching Characteristics 
     Table 3 contains various switching metrics for memory elements formed using embodiments described herein, and other memory elements as a comparison:
         HfO x /TiO 2  refers to a memory element including an n-type polysilicon electrode  206 , a 50 Å thick hafnium oxide switching layer  210  deposited at 250° C., an 8 Å titanium oxide coupling layer  212  deposited at 250° C., and a titanium nitride electrode  208 .   HfO x /Al 2 O 3  refers to a memory element including an n-type polysilicon electrode  206 , a 50 Å thick hafnium oxide switching layer  210  deposited at 250° C., an 8 Å aluminum oxide coupling layer  212  deposited at 250° C., and a titanium nitride electrode  208 .       

     HfO x /ZrO 2  refers to a memory element including an n-type polysilicon electrode  206 , a 50 Å thick hafnium oxide switching layer  210  deposited at 250° C., an 8 Å zirconium oxide coupling layer  212  deposited at 250° C., and a titanium nitride electrode  208 .
         HfAl x O y  refers to a memory element including an n-type polysilicon electrode  206 , a 58 Å aluminum-doped hafnium oxide switching layer  210  deposited at 250° C., and a titanium nitride electrode  208 .       

     
       
         
           
               
               
               
               
               
             
               
                 TABLE 3 
               
               
                   
               
               
                   
                 V FORM   
                 V RESET   
                 V SET   
                 Yield 
               
               
                   
               
             
            
               
                 HfO x /TiO 2   
                 −6 V to −9 V 
                 6-7 V 
                 −3 V to −4 V  
                 40-60% 
               
               
                 HfO x /Al 2 O 3   
                 −6 V to −8 V 
                 4-6 V 
                 −3 V to −4 V  
                 50-70% 
               
               
                 HfO x /ZrO 2   
                 −5 V to −8 V 
                 6-7 V 
                 −3 V to −4 V 
                 60-80% 
               
               
                 HfAl x O y   
                 &gt;|−8| V 
                 6-7 V 
                 −4 V to −5 V  
                 20-40% 
               
               
                   
               
            
           
         
       
     
     All data are for bipolar switching, and yield refers to the percentage in a given sample of memory elements that reliably switch. As can be seen, the higher bandgap coupling layers in the HfO x /Al 2 O 3  and HfO x /ZrO 2  memory elements show improved forming or reset voltages and improved cycling yields. 
     The HfAl x O y  and the HfO x /Al 2 O 3  memory elements have the same thickness and the same material components. However, the HfAl x O y  memory element is aluminum-doped, and has the aluminum dispersed throughout the hafnium oxide layer, while the HfO x /Al 2 O 3  memory element has a bulk hafnium oxide layer and a small aluminum oxide coupling layer. The switching characteristics for the HfO x /Al 2 O 3  are better, suggesting that the improved switching may be due to defects formed at the interface between the coupling layer  212  and the switching layer  210 . 
     B. Interface Layer 
     Techniques described in the process  1300  were used to deposit a memory element  102  that substantially eliminated the interface layer  214 . Aluminum oxide was deposited using trimethylaluminum and water vapor. The amount of water vapor in the gas phase was restricted by lowering the temperature of the water vapor source to 1-5°. Using this technique, the thickness of the interface layer  214  was reduced from 1.1 nm (when the water source was held at room temperature) to approximately zero. In some embodiments, elimination of the interface layer  214  may reduce forming voltage. 
     VII. Representative Embodiments 
     In accordance with an embodiment, a resistive-switching memory element is provided that includes a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material selected from the group consisting of aluminum oxide and zirconium oxide, the coupling layer having a second thickness that is less than 25 percent of the first thickness. 
     In accordance with a further embodiment, the first electrode of the memory element is doped silicon and the memory element is configured to receive a negative reset voltage relative to a common electrical reference and a positive set voltage relative to the common electrical reference at the second electrode. 
     In accordance with a further embodiment, the first electrode of the memory element comprises a first material and the second electrode comprises a second material, and the first material is different from the second material. 
     In accordance with a further embodiment, the first material of the first electrode is doped silicon and the second material of the second electrode is titanium nitride. 
     In accordance with a further embodiment, the first thickness of the memory element is between 20 and 100 angstroms. 
     In accordance with a further embodiment, the switching layer of the memory element comprises a hafnium oxide material having an elemental composition of between HfO 1.2  and HfO 1.7 . 
     In accordance with a further embodiment, the first material of the first electrode is n-type polysilicon. 
     In accordance with a further embodiment, at least one of the first electrode and the second electrode of the memory element has a same most common oxidation state as the switching layer. 
     In accordance with a further embodiment, the memory element further includes an interface layer between the first electrode and the switching layer, the interface layer having a thickness less than 10 Å. 
     In accordance with a further embodiment, the interface layer of the memory element comprises silicon oxide. 
     In accordance with a further embodiment, a work function of the second electrode of the memory element is greater than a work function of the first electrode, and wherein the first electrode is configured to receive a forming voltage pulse having a negative voltage relative to a common electrical reference. 
     In accordance with another embodiment, a resistive-switching memory element is provided, including a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater than or equal to the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness. 
     In accordance with a further embodiment, the first metal oxide of the memory element has an oxygen concentration that is between 60 and 95% of stoichiometric. 
     In accordance with a further embodiment, the first electrode of the memory element is selected from the group consisting of doped silicon and titanium nitride, and the second electrode is selected from the group consisting of molybdenum nitride, molybdenum oxide, titanium nitride, tungsten, tantalum nitride, molybdenum nitride, molybdenum oxide, platinum, ruthenium, nickel, iridium, iridium oxide, and ruthenium oxide. 
     In accordance with a further embodiment, the first thickness of the switching layer is between 20 and 100 Å. 
     In accordance with a further embodiment, a first metal of the first metal oxide has a first most common oxidation state that is different from a second most common oxidation state of the second metal of the second metal oxide. 
     In accordance with a further embodiment, a first metal of the first metal oxide and a second metal of the second metal oxide have a same most common oxidation state. 
     In accordance with a further embodiment, a second metal of the second metal oxide has a second most common oxidation state that is than less than or equal to a first most common oxidation state of a first metal of the first metal oxide. 
     In accordance with a further embodiment, the first metal oxide is hafnium oxide and the second metal oxide is selected from the group consisting of zirconium oxide and aluminum oxide. 
     In accordance with a further embodiment, the first metal oxide is selected from the group consisting of hafnium oxide, tantalum oxide, aluminum oxide, zirconium oxide, and yttrium oxide, and the second metal oxide is selected from the group consisting of zirconium oxide and aluminum oxide. 
     In accordance with a further embodiment, the first electrode comprises doped silicon and further comprising an interface layer between the first electrode and the switching layer comprising silicon oxide and having a thickness of less than 10 Å. 
     In accordance with a further embodiment, the first electrode comprises a silicide chosen from the group consisting of titanium silicide, cobalt silicide, nickel silicide, palladium silicide, and platinum silicide. 
     In accordance with a further embodiment, the memory element is part of a three-dimensional memory array. 
     In accordance with another embodiment, a method for forming a resistive-switching memory element is provided, including depositing a first electrode on a substrate, depositing a switching layer comprising a metal oxide over the first electrode using atomic layer deposition (ALD), the depositing the switching layer further comprising maintaining a precursor at greater than 40 degrees Celsius, introducing the precursor to the substrate, maintaining an oxygen source at less than 10 degrees Celsius, introducing the oxygen source to substrate, and depositing a second electrode over the switching layer. 
     In accordance with a further embodiment, the oxygen source is at least one of water vapor, isopropyl alcohol (IPA), and ethanol. 
     In accordance with a further embodiment, the metal oxide is chosen from the group consisting of hafnium oxide, tantalum oxide, aluminum oxide, yttrium oxide, and zirconium oxide. 
     In accordance with a further embodiment, the metal oxide has an oxygen concentration that is between 60 and 95 percent of stoichiometric. 
     In accordance with a further embodiment, the metal oxide is hafnium oxide and has an elemental composition that is between HfO 1.2  and HfO 1.7 . 
     In accordance with a further embodiment, a deposition temperature for the ALD is less than 250 degrees Celsius. 
     In accordance with a further embodiment, a deposition temperature for the ALD is approximately 200 degrees Celsius. 
     In accordance with a further embodiment, the method includes annealing the memory element after depositing the second electrode. 
     In accordance with a further embodiment, the method further includes depositing a physical vapor deposition (PVD) layer over the first electrode using physical vapor deposition, wherein the switching layer is deposited over the PVD layer, and wherein the PVD layer comprises a same material as the switching layer. 
     In accordance with a further embodiment, the method further includes depositing a coupling layer over the switching layer, the coupling layer having a thickness that is less than 25 percent of a thickness of the switching layer. 
     In accordance with a further embodiment, a bandgap of the coupling layer is greater than a bandgap of the switching layer. 
     In accordance with a further embodiment, the coupling layer is selected from the group consisting of aluminum oxide and zirconium oxide. 
     In accordance with another embodiment, a method for forming a resistive-switching memory element including depositing a first electrode on a substrate, depositing a switching layer over the first electrode, the switching layer having a first thickness and a first bandgap that is greater than 4 electron volts (eV), depositing a coupling layer over the switching layer, the coupling layer having a second thickness that is less than 25 percent of the first thickness and a second bandgap that is greater than or equal to the first bandgap, and depositing a second electrode over the coupling layer. 
     In accordance with a further embodiment, the first electrode is doped silicon and depositing a switching layer comprises forming an interface layer comprising silicon oxide between the first electrode and the switching layer, the interface layer having a thickness of less than 10 Å. 
     In accordance with a further embodiment, the switching layer is chosen from the group consisting of hafnium oxide, tantalum oxide, aluminum oxide, yttrium oxide, and zirconium oxide. 
     In accordance with a further embodiment, the coupling layer is chosen from the group consisting of zirconium oxide and aluminum oxide. 
     In accordance with a further embodiment, depositing the switching layer comprises using atomic layer deposition (ALD), including maintaining a precursor at greater than 40 degrees Celsius, introducing the precursor to the substrate, maintaining an oxygen source at less than 10 degrees Celsius, and introducing the oxygen source to the substrate. 
     In accordance with a further embodiment, depositing the switching layer comprises depositing a metal oxide having an oxygen concentration that is between 60 and 95 percent of stoichiometric. 
     In accordance with a further embodiment, the method includes annealing the memory element. 
     In accordance with a further embodiment, the oxygen source is at least one of water vapor, isopropyl alcohol, and ethanol. 
     Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed examples are illustrative and not restrictive.