Patent Publication Number: US-9853611-B2

Title: Instrumentation amplifier with digitally programmable input capacitance cancellation

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 61/946,022, filed Feb. 28, 2014, entitled Instrumentation Amplifier With Built-In Digitally Programmable Input Capacitance Cancellation, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     This invention was made with government support under grant No. 1349692 awarded by NSF. The government has certain rights in the invention. 
    
    
     BACKGROUND 
     Battery-powered portable or implantable biopotential and bioimpedance measurement devices are becoming increasingly widespread in the medical diagnostics field. The signal acquisitions of the main biosignal-sensing applications such as electroencephalography (EEG) and electrocardiography (ECG) involve voltage measurements from a few microvolts to several millivolts [1]-[3]. Biopotentials are conventionally acquired using electrodes covered with electrolyte gels or solutions to decrease the contact impedance at the skin interface to values below 10 KΩ. However, wet-contact measurements cause discomfort and dry out in novel long-term monitoring applications such as in brain-computer interfaces where EEG signals are acquired and analyzed over hours or longer [4]. 
     In general, dry electrodes such as inexpensive Ag/AgCl are better suited for long-term monitoring, but their use is associated with increased contact resistances that can be above 1 MΩ [5]. This characteristic complicates the measurement of small biopotentials in the range of few μV for EEG applications by requiring very high input impedance at the analog front-end amplifier of at least 500 MΩ [6]. Nevertheless, a significant problem is that this impedance is affected by parasitic capacitances of the integrated circuit package as well as electrode cable and printed circuit board (PCB) capacitances that could be as high as 50-200 pF at the input of an instrumentation amplifier (IA) shown in  FIG. 1 . For instance, when the goal is to record EEG signals with frequencies up to 100 Hz, an interface capacitance of 200 pF would limit the input impedance at 100 Hz to approximately 8 MΩ, which is much less than 500 MΩ and would cause excessive attenuation such that the EEG signal cannot be measured reliably. 
     SUMMARY OF THE INVENTION 
     An instrumentation amplifier (IA) with a mechanism that generates negative capacitances at its input is provided to enable input capacitance cancellation for biosignal measurements, such as biopotential and bioimpedance. In one embodiment, the IA architecture includes two digitally programmable (8-bit) capacitors between the input stage and the current feedback loop of the IA to cancel the input capacitances from electrode cables and a printed circuit board. The negative capacitance generation technique can improve the input impedance from a few mega ohms to more than 100 MΩ without significant impact on performance parameters such as the common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR), total harmonic distortion (THD), and noise. 
     In another aspect, an on-chip digital calibration system is provided to adaptively improve the input impedance of the analog front-ends in biosignal measurement systems. The calibration system can be activated, for example, whenever electrode cables are changed. In one embodiment, the calibration unit controls the two 8-bit capacitor banks of the IA to generate a negative capacitance and to significantly increase the input impedance of the IA to above at least 100 MΩ. A test signal generator for operation with the calibration system is also provided to calibrate the IA. The integrated signal generator enables detection of the input impedance at the front-end IA based on current injection and amplitude detection. 
     In one embodiment, an instrumentation amplifier device is provided comprising an instrumentation amplifier comprising: 
     a differential input stage comprising an inverting input terminal and a non-inverting input terminal; 
     an output stage driven by the input stage; 
     a direct current feedback loop from the output stage to the input stage; and 
     a negative capacitance generation feedback circuit between the input stage and the direct current feedback loop, wherein a negative capacitance is generated at the input stage to cancel parasitic capacitances at the input terminal and thereby boost input impedance. 
     In one aspect of the instrumentation amplifier device, the negative capacitance generation feedback circuit is connected in parallel between the input stage and internal nodes of the instrumentation amplifier. In a further aspect, gains from the internal nodes are out of phase. 
     In a further aspect, the negative capacitance generation feedback circuit comprises a first negative impedance converter circuit connected in parallel between the inverting input terminal and a first internal node; and a second negative impedance converter connected in parallel between the non-inverting terminal and an second internal node. 
     In a further aspect, each negative impedance converter circuit comprises a plurality of programmable capacitors disposed in parallel. In a still further aspect, each programmable capacitor is disposed in series with a switch operable between an on position and an off position. In a still further aspect, each programmable capacitor comprises an 8-bit device comprising 8 capacitors, each capacitor selectable to be on or off. In a still further aspect, the instrumentation amplifier is calibratable by setting each programmable capacitor to be on or off to maximize the input impedance boosting. 
     In a further aspect, a gain from the first internal node is out of phase with a gain from the second internal node. In a still further aspect, the gain from the first internal node is 180° out of phase with the gain from the second internal node. 
     In one aspect of the instrumentation amplifier device, the negative capacitance generation feedback circuit cancels at least in part input capacitance to the input stage generated by one or more of an electrode cable, a printed circuit board, and an integrated circuit package connected to the input stage. 
     In one aspect of the instrumentation amplifier device, the negative capacitance generation feedback circuit is operable to boost the input impedance to at least 100 MΩ. 
     In one aspect of the instrumentation amplifier device, the instrumentation amplifier is operable to sense biopotential signals. 
     In one aspect, the instrumentation amplifier is operable to sense voltages representative of electroencephalography or electrocardiography biosignals. 
     In one aspect, the instrumentation amplifier device is operable to measure input biosignals having frequencies of up to at least 50 Hz. 
     In one aspect of the instrumentation amplifier device, the instrumentation amplifier includes programmable capacitors to generate the negative capacitance at the input of the instrumentation amplifier, and further comprises a calibration circuit comprising a processor operative in a calibration mode to: 
     measure voltage at an output node of the instrumentation amplifier or of a subsequent gain or filtering stage; 
     compare the measured voltage amplitude to a plurality of reference voltages; 
     generate a respective plurality of control signals responsive to the comparison; and 
     transmit the generated control signals to control the programmable capacitors of the instrumentation amplifier to optimize the negative capacitance generated at the input of the instrumentation amplifier. 
     In one aspect, the calibration circuit includes an analog-to-digital converter operative to provide the reference voltages. 
     In a further aspect, the calibration circuit further includes a calibration unit comprising input ports to receive input signals from the analog to digital converter and a plurality of output ports to transmit control signals to switches at the programmable capacitors. 
     In one aspect, the calibration unit further comprises memory to store a code representative of a control signal to optimize the negative capacitance. 
     In one aspect, the calibration circuit includes a test current generator operative to inject a test current having a selected magnitude into the input of the instrumentation amplifier to generate a voltage at the output node. 
     In one aspect, the calibration circuit includes one or more switches in a calibration path operative when closed to allow activation of the calibration device. 
     In one embodiment, a biosignal sensing device comprises the instrumentation amplifier, the biosignal sensing device operable to sense voltages representative of electroencephalography or electrocardiography biosignals. 
     In one embodiment, a method of measuring biosignals comprises: 
     receiving biosignals at an input stage of an instrumentation amplifier, the input stage including an inverting input terminal and a non-inverting input terminal; 
     generating an amplified output signal at an output stage of the instrumentation amplifier; 
     generating within the instrumentation amplifier a feedback loop from the output stage to the input stage; and 
     boosting impedance at the input stage by generating a negative capacitance in the feedback loop. 
     In one aspect, the method includes generating the negative capacitance by providing negative impedance converter circuitry connected in parallel between the input stage and internal nodes of the instrumentation amplifier. 
     In one aspect of the method, the internal nodes have out-of-phase gains. 
     In one aspect of the method, the method includes connecting electrode cables to the input stage of the instrumentation amplifier; and calibrating the negative capacitance converter circuitry after connecting the electrode cables to maximize the boosting of the impedance at the input stage. 
     In one aspect of the method, the negative capacitance converter circuitry comprises a plurality of programmable capacitors, and the calibrating step comprises setting each of the programmable capacitors to on or off. 
     In one aspect of the method, the method includes receiving voltages representative of electroencephalography or electrocardiography signals. 
     In one aspect of the method, the method includes connecting electrode cables to each of the inverting input terminal and the non-inverting input terminal, the electrode cables connected to electrodes. 
     In one aspect of the method, the electrodes comprise dry electrodes. 
     In one aspect of the method, the method includes boosting the impedance to at least 100 MΩ. 
     In one embodiment, a method of generating negative capacitances via on-chip calibration, comprises: 
     measuring, by a processor, voltage at an output node of an instrumentation amplifier or of subsequent gain/filtering stages, the instrumentation amplifier including programmable capacitors to generate a negative capacitance at an input of the instrumentation amplifier; 
     comparing, by the processor, the measured voltage amplitude to a plurality of reference voltages; 
     generating, by the processor, a respective plurality of control signals responsive to the comparison; and 
     transmitting, by the processor, the generated control signals to control the programmable capacitors of the instrumentation amplifier to optimize the negative capacitance generated at the input of the instrumentation amplifier. 
     In one aspect, the method includes storing a code in memory representative of a control signal to optimize the negative capacitance. 
     In one aspect of the method, the method includes cycling through a plurality of comparison voltages and updating the code stored in the memory with an optimized code. 
     In one aspect of the method, the method includes injecting a test current having a selected magnitude into the input of the instrumentation amplifier to generate the voltage at the output node. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
       The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a schematic illustration of an embodiment of an analog front-end system for biosignal measurements including an instrumentation amplifier with on-chip input capacitance cancellation and calibration; 
         FIG. 2  is an illustration of a basic negative impedance converter (NIC) as reference, where Z in =−Z when R 1 =R 2 ; 
         FIG. 3  is a schematic diagram of an instrumentation amplifier with direct current feedback and negative capacitance generation feedback (NCGFB); 
         FIG. 4  illustrates an implementation of negative capacitance generation feedback with programmable capacitors; 
         FIG. 5  illustrates a small-signal model of the instrumentation amplifier&#39;s input and feedback stages; 
         FIG. 6  illustrates impedances at the instrumentation amplifier inputs with and without NCGFB for different C sp  and C sn  values: (a) C sp =C sn =100 pF, (b) C sp =200 pF and C sn =50 pF; 
         FIG. 7  an illustrates input impedance comparison (at Z inp ) for the instrumentation amplifiers with and without NCGFB from simulations with foundry-supplied device models representing different process corner cases; 
         FIG. 8  is a schematic illustration of one embodiment of an instrumentation amplifier in the analog front-end with on-chip calibration circuitry; 
         FIG. 9  is a schematic illustration of one embodiment of an instrumentation amplifier with on-chip test signal generation for calibration of the instrumentation amplifier; 
         FIG. 10  illustrates an amplitude-based impedance detection method with comparators and latches; 
         FIG. 11( a )  illustrates an operational transconductance amplifier for use during the test current injection at the input of an embodiment of an instrumentation amplifier; 
         FIG. 11( b )  illustrates a bias current generation circuit for use in the operational transconductance amplifier of  FIG. 11( a ) ; 
         FIG. 12  illustrates simulated differential output voltage of a test signal generator with a load capacitance of 3 pF and enabled transient noise for all devices; 
         FIG. 13  illustrates an embodiment of a schematic of a differential voltage limiter; 
         FIG. 14  illustrates a simulated differential output voltage (v o1 −v o2 ) of the voltage limited (typical corner case, 27° C.); 
         FIG. 15  illustrates an embodiment of a relaxation oscillator block diagram; 
         FIG. 16  illustrates a frequency divider (with standard D flip-flops); 
         FIG. 17  illustrates squared output noise of a test signal generator vs. frequency; 
         FIG. 18  illustrates simulated effect of transient noise with small OTA output voltage amplitude (the dashed line is the ideal output signal without noise); 
         FIGS. 19( a ) and 19( b )  illustrate simulated output impedance and transconductance respectively of the OTA for corners (ff, tt, ss) with different temperatures (−30° C., 27° C., 85° C.) (the bolded line is the typical corner case at 27° C.); 
         FIG. 20  is a schematic flowchart illustrating an embodiment of a calibration process; 
         FIG. 21  is a schematic block diagram of an embodiment of a digital calibration unit; 
         FIG. 22  is a circuit diagram of an embodiment of an instrumentation amplifier with negative capacitance generation feedback; 
         FIG. 23  is a circuit diagram of an embodiment of a test amplifier used in the calibration circuit; 
         FIG. 24  is a schematic of an embodiment of a comparator used in the calibration circuit; 
         FIG. 25  illustrates a layout of a digital calibration unit in 130 nm CMOS technology: (a) control block, (b) memory block; and 
         FIG. 26  illustrates simulated waveforms of a test amplifier output and the digital control signals for capacitor bank switches (C inn =C inp =100 pF). 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 1 , an instrumentation amplifier device  10  is shown that incorporates an instrumentation amplifier (IA)  12  with negative capacitance generation feedback (NCGFB) and associated calibration circuit  14 . In one embodiment, the negative capacitance generation is integrated into the IA, described further below. In addition, on-chip monitoring and calibration can be provided using an analog to digital converter (ADC)  16  and a digital signal processor (DSP)  18  with a programmable capacitor bank within the IA  12  for tuning The calibration circuit also includes an on-chip test current generator (i test )  20  with high output impedance. The instrumentation amplifier is suitable, for example, in an analog front-end of, for example, a bio-signal sensing device. 
     In one embodiment, a solution for boosting input impedance is the addition of a classical negative impedance converter (NIC) at the input of the IA.  FIG. 2  shows a simplified NIC schematic that could be used to generate a negative capacitance at the input node of the IA if Z is a capacitor. However, this approach would require an additional amplifier, whose power and area consumption is undesirable. Furthermore, the additional noise from the operational amplifier at the input of the IA would have to be carefully assessed. 
     Accordingly, a negative capacitance generation scheme is provided that is integrated into the IA and thereby avoids an extra amplifier. The IA with input capacitance cancellation for impedance boosting has general usefulness in emerging biopotential and bioimpedance measurement applications regardless of how the tuning method is implemented. 
     Referring again to  FIG. 1 , an instrumentation amplifier device  10  includes an instrumentation amplifier  12  that includes a differential input stage comprising an inverting input terminal and a non-inverting input terminal, and an output stage driven by the input stage. A direct current feedback loop is provided from the output stage to the input stage ( FIG. 3 , described further below). A negative capacitance generation feedback circuit is disposed between the input stage and the direct current feedback loop, such that a negative capacitance is generated at the input stage to cancel parasitic capacitances at the input terminal and thereby boost input impedance. The negative capacitance can be implemented by, for example, a plurality of programmable capacitors (described further below). Digital tuning can be implemented via a calibration circuit including the ADC  16  to provide reference voltages to a calibration unit (DSP  18 ) that includes input ports to receive input signals from the ADC and a plurality of output ports to transmit control signals to switches at the programmable capacitors in the IA  12 . The DSP also includes memory to store codes representative of control signals to optimize the negative capacitance. The calibration circuit  14  also includes a test current generator  20  that can inject a test current having a selected magnitude into the input of the instrumentation amplifier to generate a voltage at the output node, used in the calibration process. The calibration circuit also includes one or more switches in a calibration path operative when closed to allow activation of the calibration circuit. Calibration can be performed at any appropriate time (prior to measurements), such as when the electrode cables are changed. 
     One embodiment of an IA with input capacitance cancellation for impedance boosting is described more particularly with reference to  FIG. 3 .  FIG. 3  shows a schematic of a suitable IA topology with direct current feedback, where the DC gain of the IA is decided by the ratio R 2 /R 1  and the dominant pole depends on R 2  and C 2 . The amplifier B 1  can be implemented in any suitable manner, as would be known by one of ordinary skill in the art. The IA includes a differential input stage comprising an inverting input terminal and a non-inverting input terminal, and an output stage driven by the input stage. A direct current feedback loop is provided from the output stage to the input stage. A negative capacitance generation feedback (NCGFB) circuit is provided between the input stage and the direct current feedback loop. With the NCGFB circuit, negative capacitances are generated at the input stage to cancel parasitic capacitances at the input terminal and thereby boost input impedance. 
     More particularly, the negative capacitance generation feedback circuit is connected in parallel between the input stage and internal nodes of the instrumentation amplifier. In one embodiment, the negative capacitance generation feedback circuit comprises a first negative impedance converter circuit connected in parallel between the inverting input terminal and a first internal node; and a second negative impedance converter connected in parallel between the non-inverting terminal and a second internal node. The internal nodes are preferably selected such that their gains are out of phase, preferably 180° out of phase. 
     In one embodiment, each negative impedance converter circuit comprises a plurality of programmable capacitors C p , C n , disposed in parallel, indicated in  FIG. 4 . Each programmable capacitor is disposed in series with a S p , S n , switch operable between an on position and an off position. In one embodiment, each programmable capacitor comprises an 8-bit device comprising 8 capacitors. As described further below, the instrumentation amplifier can be calibrated by setting each programmable capacitor to be on or off to maximize the input impedance boosting. The calibration can be performed whenever appropriate, such as when the input electrode cables are changed. 
     The negative capacitance generation feedback circuit can be operable to and can be calibrated to boost the input impedance to at least 100 MΩ, at least 200 MΩ, at least 300 MΩ, at least 400 MΩ, at least 500 MΩ, at least 750 MΩ, at least 1000 MΩ, at least 1500 MΩ, at least 2000 MΩ, depending on the requirements of the particular application for which the IA is used. The IA can be operable to measure input biosignals having frequencies of up to 50 Hz, up to 100 Hz, up to 200 Hz, up to 300 Hz, up to 400 Hz, up to 500 Hz, up to 600 Hz, up to 700 Hz, up to 800 Hz, up to 900 Hz, or up to 1000 Hz, again depending on the requirements of the particular application for which the IA is used and the chip fabrication process technology in which the IA is manufactured. In some applications, the IA can be incorporated into a biosignal sensing device to sense voltages representative of electroencephalography or electrocardiography signals. 
     The transfer functions from the inputs (v i+ , v i− ) to v A , v B , v C , v D , v E , and v F  are analyzed below using a small-signal model to evaluate the possibilities for negative capacitance generation feedback (NCGFB). Since nodes v C  and v D  in  FIG. 3  are the most appropriate locations to obtain suitable gains for generating negative capacitances at the inputs (v i+ , v i− ), the NCGFB realization at these two nodes is discussed further below. 
       FIG. 5  shows the small-signal model of the IA&#39;s input stage and the current feedback loop for solving the transfer functions from the inputs to internal nodes. All parasitic capacitances are omitted during this analysis because the typical applications of this IA are at low frequencies (below 1 KHz). It is also noteworthy that the small-signal inputs (v A  and v B ) of the differential pair (M 5  and M 6 ) in the feedback loop are not truly differential due to the asymmetric characteristics looking into v A  (M 3  is diode-connected) and v B  (M 4  is not diode-connected). Hence, the phase of v B  follows that of v A , and v G  is not a virtual ground. For this reason, the small-signal drain-source resistance (1/ gds,Mtail ) of M tail  should be taken into account during the analysis. Without the effect of the NCGFB, the current summation equations at nodes  1  through  4  in  FIG. 5  are: 
                             v   E     -     v   F         R   1       +       g     m   ,     M   ⁢           ⁢   1         ⁡     (       v   E     -     v     i   +         )       +       g     m   ,     M   ⁢           ⁢   9         ⁢     v   D         =   0     ,           (   1   )                         v   E     -     v   F         R   1       +       g     m   ,     M   ⁢           ⁢   2         ⁡     (       v   F     -     v     i   -         )       -       g     m   ,     M   ⁢           ⁢   10         ⁢     v   C         =   0     ,           (   2   )                       g     m   ,     M   ⁢           ⁢   2         ⁡     (       v   F     -     v     i   -         )       -       g     m   ,     M   ⁢           ⁢   4         ⁢     v   A         =   0     ,           (   3   )                       (       g     m   ,     M   ⁢           ⁢   5         +     g     mb   ,     M   ⁢           ⁢   5         +     g     m   ,     M   ⁢           ⁢   6         +     g     mb   ,     M   ⁢           ⁢   6         +     g     ds   ,   Mtail         )     ⁢     v   G       -       g     m   ,     M   ⁢           ⁢   5         ⁢     v   A       -       g     m   ,     M   ⁢           ⁢   6         ⁢     v   B         =   0     ;           (   4   )               
where g m,M1 -g m,M10  are the transconductances of M 1 -M 10 , g mb,M5  and g mb,M6  are the body effect transconductances of M 5  and M 6 , and g ds,Mtail  is the small-signal drain-source admittance of M tail . From  FIG. 5 , the voltages v A , v C , and v D  can be expressed as
 
                       v   A     =         g     m   ,     M   ⁢           ⁢   1         ⁡     (       v   E     -     v     i   +         )         g     m   ,     M   ⁢           ⁢   3             ,           (   5   )                   v   C     =           (       g     m   ,     M   ⁢           ⁢   5         +     g     mb   ,     M   ⁢           ⁢   5           )     ⁢     v   G       -       g     m   ,     M   ⁢           ⁢   5         ⁢     v   A           g     m   ,     M   ⁢           ⁢   7             ,           (   6   )                 v   D     =             (       g     m   ,     M   ⁢           ⁢   6         +     g     mb   ,     M   ⁢           ⁢   6           )     ⁢     v   G       -       g     m   ,     M   ⁢           ⁢   6         ⁢     v   A           g     m   ,     M   ⁢           ⁢   8           .             (   7   )               
Note that the conditions g m1 =g m2 , g m3 =g m4 , g m5 =g m6 , g m7 =g m8 , g m9 =g m10 , and g mb5 =g mb6  are valid for this analysis in the absence of device mismatches. Furthermore, the same definitions as in [8] are used next: v in =v i+ −v i− =v E −V F , where v i +=v in /2 and v i− =−v in /2. With these definitions, the voltage gains from v in  to v A-G  can be derived from the above equations:
 
                       A     V   ,   A       =         v   A       v   in       =         g     m   ,     M   ⁢           ⁢   7         ·     g     ds   ,   Mtail         D         ,           (   8   )                   A     V   ,   B       =         v   B       v   in       =         2   ⁢     g     m   ,     M   ⁢           ⁢   7               g     m   ,     M   ⁢           ⁢   5         ·     g     m   ,     M   ⁢           ⁢   9         ·     R   1         +         g     m   ,     M   ⁢           ⁢   7         ·     g     ds   ,   Mtail         D           ,           (   9   )                   A     V   ,   C       =         v   C       v   in       =       1       g     m   ,     M   ⁢           ⁢   9         ·     R   1         -         g     m   ,     M   ⁢           ⁢   3         ·     g     m   ,     M   ⁢           ⁢   7         ·     g     ds   ,   Mtail             g     m   ,     M   ⁢           ⁢   9         ·   D             ,           (   10   )                   A     V   ,   D       =         v   D       v   in       =       -     1       g     m   ,     M   ⁢           ⁢   9         ·     R   1           -         g     m   ,     M   ⁢           ⁢   3         ·     g     m   ,     M   ⁢           ⁢   7         ·     g     ds   ,   Mtail             g     m   ,     M   ⁢           ⁢   9         ·   D             ,           (   11   )                   A     V   ,   E       =         v   E       v   in       =       1   2     +         g     m   ,     M   ⁢           ⁢   3         ·     g     m   ,     M   ⁢           ⁢   7         ·     g     ds   ,   Mtail             g     m   ,     M   ⁢           ⁢   1         ·   D             ,           (   12   )                   A     V   ,   F       =         v   F       v   in       =       -     1   2       +         g     m   ,     M   ⁢           ⁢   3         ·     g     m   ,     M   ⁢           ⁢   7         ·     g     ds   ,   Mtail             g     m   ,     M   ⁢           ⁢   1         ·   D             ,           (   13   )                   A     V   ,   G       =         v   G       v   in       =       2   ·     g     m   ,     M   ⁢           ⁢   3         ·     g     m   ,     M   ⁢           ⁢   7       2           g     m   ,     M   ⁢           ⁢   9         ·   D           ;           (   14   )               
where:
 
     D=[(2·g m,M5 +2·g mb,M5 +g ds,Mtail )·g m,M3 ·g m,M7 −g m,M5 ·g m,M9 ·g ds,Mtail ]·R 1 . From Equations (8) and (9) it can be observed that A V,B  is always larger than A V,A , and that A V,A  and A V,B  have the same phase. Equations (10) and (11) show that A V,C  and A V,D  are in anti-phase. Although these gain magnitudes are not equal, nodes v C  and v D  are well-suited as points at which the NCGFB can be added. From Equations (12) and (13), the gains A V,E  and A V,F  have the same phase if g m,M3 ·g m,M7 ·g ds,Mtail /(g m,M1 ·D)&gt;0.5, which would complicate the use of nodes v E  and v F  for the NCGFB. 
     Returning to  FIG. 4 , a suitable NCGFB implementation is illustrated with an 8-bit digitally-controlled capacitor (C p −2 7 ·C p ) and one fixed capacitor (C p0 ) between nodes v i+  and v C . The maximum and minimum capacitance values occur with S p7,6,5,4,3,2,1,0 =[11111111] and [00000000] respectively, where ‘1’ or ‘0’ indicate that the switch is turned “on” or “off”. The same programmable capacitor configuration was connected between nodes v i−  and v D  with control switches S n7,6,5,4,3,2,1,0 . Neglecting the very high resistance at the gates of the transistors, the input impedances (Z inp  and Z inn ) in  FIG. 1  can be derived as 
                         Z   inp     ⁡     (   s   )       =     1       sC   sp     +     sC     total   ,     i   +               ,           (   15   )                     Z   inn     ⁡     (   s   )       =     1       sC   sn     +     sC     total   ,     i   -               ;           (   16   )               
where C sp  and C sn  are the cable (and PCB) capacitances at the positive and negative inputs of the IA, and C total,i+  and C total,i−  represent the IA&#39;s total equivalent capacitances at the input v i+  and v i−  respectively. The tuning range of the 8-bit capacitors can be designed to compensate for the 50-200 pF capacitances from the cables and PCB by generating negative C total,i+  and C total,i−  values through the presented NCGFB configuration. This property becomes evident after using Miller approximations to express C total,i+  and C total,i−  in terms of previously derived gains:
 
                       C     total   ,     i   +         =         C     gs   ,     M   ⁢           ⁢   1         ⁡     (     1   -     2   ⁢     A     V   ,   E           )       +       C     gd   ,     M   ⁢           ⁢   1         ⁡     (     1   -     2   ⁢     A     V   ,   A           )       +       [       C     p   ⁢           ⁢   0       +       C   p     ·       ∑     i   =   0     7     ⁢           ⁢     (       2   i     ·     S   pi       )           ]     ·     (     1   -     2   ⁢     A     V   ,   C           )           ,           (   17   )                   C     total   ,     i   -         =         C     gs   ,     M   ⁢           ⁢   2         ⁡     (     1   +     2   ⁢     A     V   ,   F           )       +       C     gd   ,     M   ⁢           ⁢   2         ⁡     (     1   +     2   ⁢     A     V   ,   B           )       +       [       C     n   ⁢           ⁢   0       +       C   n     ·       ∑     i   =   0     7     ⁢           ⁢     (       2   i     ·     S   ni       )           ]     ·     (     1   +     2   ⁢     A     V   ,   D           )           ;           (   18   )               
where C gs,X  and C gd,X  are the parasitic gate-source and gate-drain capacitances of transistor M X .
 
     Simulation Results 
     A 93.6 μW IA, using the circuitry in  FIG. 3 , was designed in IBM 0.13-μm CMOS technology for EEG signal measurement applications. A commensurate IA without NCGFB was designed as reference for comparison. Table 1 contains the design parameters of both IAs. Identical supply voltages of 1.2 V and total currents of 78 μA were used for both designs. C p0 , C p , C n0  and C n  were selected to cover cable/PCB capacitances from 50 pF to 200 pF for the IA across all device corner model cases. Notice that C p0  is not equal to C n0 , and that C p  is not equal to C n  due to the different gains and phases, as discussed above. Implementing large capacitors as off-chip capacitors is frequently done in analog front-ends for biosignal acquisitions. Therefore, it is assumed here that C 2  would not be laid out on the chip. 
     Table 2 summarizes the simulated specification parameters of both IAs. The two designs have the same gain, bandwidth, output offset voltage and noise in the typical corner case with C sp =C sn =200 pF ( FIG. 1 ). The common-mode rejection ratio (CMRR) was designed to be comparable to a commercial IA. The results show that there are only minor differences (0.1 to 0.2 dB) in the common mode rejection ratio (CMRR), power supply rejection ratio (PSRR), and total harmonic distortion (THD) of both IAs. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 PARAMETERS OF THE IA DESIGNS 
               
               
                 WITHOUT AND WITH NCGFB 
               
            
           
           
               
               
               
               
            
               
                   
                   
                 Without 
                 With 
               
               
                   
                 Component/Parameter 
                 NCGFB 
                 NCGFB 
               
               
                   
                   
               
            
           
           
               
               
               
               
            
               
                   
                 V DD  [V] 
                 1.2 
                 1.2 
               
               
                   
                 Power supply current [μA] 
                 78 
                 78 
               
               
                   
                 R 1  [KΩ] 
                 0.7 
                 0.7 
               
               
                   
                 R 2  [KΩ] 
                 40 
                 40 
               
               
                   
                 C 2  [nF] 
                 41.2 
                 41.2 
               
               
                   
                 C p0  [pF] 
                 — 
                 4.3 
               
               
                   
                 C p  [pF] 
                 — 
                 0.082 
               
               
                   
                 C n0  [pF] 
                 — 
                 2.32 
               
               
                   
                 C n  [pF] 
                 — 
                 0.028 
               
               
                   
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 COMPARISON OF SIMULATION RESULTS 
               
            
           
           
               
               
               
               
            
               
                   
                   
                 Without 
                 With 
               
               
                   
                 Performance 
                 NCGFB 
                 NCGFB 
               
               
                   
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Gain [dB] 
                 32.2 
                 32.2 
               
               
                   
                 Bandwidth [Hz] 
                 100 
                 100 
               
               
                   
                 CMRR @10 Hz [dB]* 
                 87.4 
                 87.1 
               
               
                   
                 PSRR @10 Hz [dB]* 
                 67.2 
                 66.9 
               
               
                   
                 THD @10 Hz [dB]* for 1 mV pk-pk  input 
                 −51.2 
                 −51.1 
               
               
                   
                 Output offset voltage [mV]* 
                 1.8 
                 1.8 
               
               
                   
                 Total input-referred volatage noise [μV] 
                 2.72 
                 2.72 
               
               
                   
                 (noise bandwidth: 0.1-100 Hz) 
               
               
                   
                   
               
               
                   
                 *Results are the mean from 500 Monte Carlo simulation runs including process and mismatch variations from foundry-supplied device models. 
               
            
           
         
       
     
       FIG. 6  shows the input impedances of Z inp  and Z inn  for both amplifiers in the typical corner case for different C sp  and C sn  values. The impedances at Z inp  and Z inn  for the IA with NCGFB reach 500 MΩ or more at 100 Hz. A tuning scheme, discussed further below, is used to adjust the programmable capacitors in  FIG. 4  to a value that cancels most of the capacitance at each input. For example, the case with C sp =C sn =100 pF in  FIG. 6( a )  requires that S p7,6,5,4,3,2,1,0 =[01010110] and S n7,6,5,4,3,2,1,0 =[01010001]. On the other hand, without the NCGFB method, the impedances at Z inp  and Z inn  are only below 20 MΩ at 100 Hz, which fall short of the 500 MΩ requirement for measurements with dry electrodes. The simulation results in  FIG. 6( b )  indicate that the IA with NCGFB has the capability to compensate for different cable capacitances at each input (c sp =200 pF and c sn =50 pF). 
       FIG. 7  shows the impedances at Z inp  for the IAs with and without NCGFB in the different process corner cases with C sp =200 pF. The impedances at 100 Hz for the IA with NCGFB are over 500 MΩ in all corner cases after adjusting the switch settings (S p7,6,5,4,3,2,1,0 ) of the capacitor array. In contrast, the impedances at 100 Hz for the IA without NCGFB are less than 20 MΩ in all process corner cases. 
     In summary, a 93.6 μW IA with negative capacitance generation was presented in IBM 0.13-μm CMOS technology to cancel input capacitances from the electrode cables and PCB. In comparison to an identical IA without NCGFB, the important performances such as common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR), and total harmonic distortion (THD) are not significantly affected by the proposed input capacitance cancellation technique. The IA with NCGFB does not consume any extra power to boost the impedance from below 20 MΩ to above 500 MΩ after the proper adjustment of the digitally programmable capacitors. 
     As noted above, an on-chip digital calibration circuit  14  is provided to automatically boost the input impedance of the instrumentation amplifier (IA) in analog front-ends for electroencephalography (EEG) measurements with dry electrodes.  FIG. 8  schematically illustrates one embodiment of an EEG measurement front-end developed as a single-chip implementation. 
     The input impedance is affected by parasitic capacitances from the package of the integrated circuit as well as electrode cable and printed circuit board (PCB) capacitances that can be 50-150 pF at the IA input, which are modeled as C inp  and C inn  in  FIG. 8 . The IA described above utilizes a negative capacitance generation technique to boost the input impedance from a few megaohms to above 500 MΩ. 
     Referring to  FIG. 8 , one embodiment of the calibration system includes of a digital calibration unit  30 , a test amplifier  32 , a set of four comparators  34  to detect the amplitude as described further below, and one comparator  36  to detect if an oscillation occurs. The calibration unit automatically finds the optimum code for the two capacitor banks between the input stage and the current feedback loop of the IA to cancel the unwanted input capacitances. The calibration test currents are generated by the test signal generation circuitry  38  described further below. When the four switches  42   a ,  42   b ,  44   a ,  44   b , in  FIG. 8  are closed, the system operates in calibration mode such that a test signal current, for example, a 19.5 Hz test signal current, (i t ) is injected into the circuit under test and the calibration system is connected to the signal path  46 . DC decoupling capacitors  54  are inserted at output of an operational transconductance amplifier (OTA)  52  to prevent leakage currents. The power line interference is suppressed by the notch in the low-pass filter response  56 . The calibration technique takes advantage of the knowledge that the filter output amplitude reflects the equivalent impedance at the instrumentation amplifier input because the test current magnitude is known. The minimum acceptable output amplitude can be determined based on simulations with worst-case process-voltage-temperature variations prior to selecting the number of comparators and their reference voltage levels. NOR-type SR latches are connected at the output of the comparators to hold the outputs until the reset signal. 
     One embodiment of a test signal generator for use in the calibration system is described with reference to  FIGS. 9-19 . As depicted in the embodiment of  FIG. 9 , the test signal generator includes a relaxation oscillator  62 , a frequency divider  64 , a voltage limiter  66 , and a low-transconductance OTA  68 . The on-chip oscillator generates a 20 KHz rail-to-rail square wave, which is divided down to 19.5 Hz. The voltage limiter converts the rail-to-rail signal to a level that is compatible with the OTA input requirement. 
     A first calibration step is performed with open electrodes in  FIG. 9 , where the switches S 1  and S 2  are closed to inject differential test currents (i t ) from an operational transconductance amplifier (OTA) into both input nodes to generate a voltage swing. The calibration step is repeated until the negative capacitance value is adjusted for sufficient input capacitance cancellation to meet the high input impedance requirement. In each cycle, the output of the lowpass and notch filter (LPF) is monitored as visualized in  FIG. 10 , taking advantage of the fact that the output amplitude (with combined amplifier and low pass filter (LPF)  72  gain of around 100 in this design) reflects the equivalent impedance at the instrumentation amplifier input because the test current magnitude is known. The amplitude of the signal can be determined based on simulations with worst-case process-voltage-temperature variations prior to selecting the number of comparators and their reference voltage levels. In one embodiment, a comparator bank  74  having a plurality of comparators is used to identify the amplitude around the required peak voltage swing (with minimum acceptable input impedance). Any suitable number of comparators can be used; generally one comparator can be suitable in some applications (when the manufacturing process variations are small), but 4 comparators are used in the embodiment shown for enhanced resolution and robust operation during the amplitude detection. In each cycle, the latched outputs of the comparators can be interpreted as thermometer-coded representation of the front-end input impedance. Prior to the reset in every cycle, the digital calibration control block  76  saves and compares the current code with the previous codes. The negative capacitance value is adjusted step by step by cycling through all digital settings to identify the one that results in the maximum output voltage swing that corresponds to the maximum front-end input impedance condition. This approach avoids direct measurement of the input impedance by using low-power area-efficient circuits in an amplitude detection scheme. Even though only one comparator would be needed in the typical case to check if the LPF output amplitude is large enough for a given input impedance requirement, a bank of comparators can be used to ensure detection capability in the presence of process variations, which can be evaluated with statistical simulations. If three or more sequential settings result in the same maximum amplitude code, then the negative capacitance setting in the center can be selected. 
       FIG. 11( a )  shows an embodiment of a suitable OTA and  FIG. 11( b )  shows its biasing circuit. The OTA should have significantly higher output impedance than the impedance of the node into which the current is injected. As an example, if the input impedance requirement of the instrumentation amplifier (IA) is 500 MΩ, an OTA output impedance of at least 1 GΩ up to 100 Hz is targeted to avoid excessive loading effects. Moreover, the maximum output capacitance target for the OTA design is 200 fF to ensure that it is small compared to the total capacitance (C in  in  FIG. 9 ) after partial capacitance cancellation. Due to the high impedance at the IA input, a differential test current magnitude of 1 pA was chosen to keep the input voltage swing at the injection node in the millivolts range, which maintains linear operation of the IA and LPF. This requires an OTA with very small transconductance around 25 pS (with V in =V in+ −V in− =40 mV peak ). 
     In one example, the instrumentation amplifier can have a simulated input-referred noise of 2.5 μV in the band of the interest (0.01 Hz to 100 Hz), and the OTA can generate 78 μV output-referred noise integrated from 0.01 Hz to 100 Hz. Hence, the total noise is small compared to the approximately 4 mV peak-to-peak differential swing at the instrumentation amplifier inputs (see  FIG. 12 ). To obtain the result in this figure, the test current generator was simulated with 3 pF capacitances at the OTA output nodes, which ensures that the front-end input impedance is higher than 500 MΩ in the 100 Hz band of interest (i.e., after partial input capacitance cancellation). 
     The OTA is preferably fully-differential to obtain a high power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR). Furthermore, common-mode interferences are suppressed by the instrumentation amplifier, which typically has a CMRR of more than 70 dB in biopotential measurement applications. For the ease of signal generation and amplitude detection with comparators ( FIG. 9 ), a square wave input signal can be employed in this method, which results in a slewed waveform ( FIG. 12 ) at the capacitively loaded OTA output and into an almost sinusoidal waveform at the LPF output due to the filtering ( FIG. 10 ). The linearity of the OTA is not critical in this amplitude detection-based method, and a third-order harmonic distortion (HD3) specification of −20 dB is sufficient since it ensures that the OTA&#39;s HD3 remains below the third-order component of an ideal square wave. 
     Any suitable design of a sub-nano-Siemen OTA can be used. In one embodiment of the architecture, transistors M 2 -M 6  in  FIG. 11( a )  implement a series-parallel current division with an 8:1 ratio. To generate precise picoampere range bias currents, a current splitting technique can be implemented as shown in  FIG. 11( b )  with N=10 and I REF =150 nA. There is a trade-off between the requirements for high output impedance and low output-referred noise: 
                       V     n   ,   out     2     ≈       ∑     x   =   3     10     ⁢           ⁢     [       V     n   ,   Mx     2     ·       (       g     m   ,   Mx       ·     R   o       )     2       ]         ,           (   19   )               
where R o  is the output impedance of the OTA. M x  (x=3 to 10) are the transistors in output stage that have transconductances of g m,Mx  and effective gate noises of V 2   n,Mx . To realize the required 25 pS transconductance at the OTA output stage, the bias current in the output stage would have to be in the picoampere range and the output impedance would be tens of gigaohms, which would generate integrated output noise of several millivolts. Thus, to avoid excessive output-referred noise, a common-gate structure (M 8 -M 10 ) can be introduced, as shown in  FIG. 11( a ) , which greatly reduces the output impedance with little impact on the bias current or transconductances of the transistors in the output stage (M 3 -M 7 ). The bias network (M 11 -M 20 ) utilizes scaled versions (I b1 , I b4 ) of the reference current I REF  in  FIG. 11( b ) . With the added structure, the output impedance is lowered to approximately 1/g m  of transistor M 8 . The OTA has a simulated output impedance of 2.9 GΩ and an integrated (0.01-100 Hz) output-referred noise of 78 μV. Since the output stage operates with a current of less than 20 pA and has an output resistance of 2.9 GΩ the simulated shift of the common-mode output voltage is less than 9.6 mV even with an excessive 20% mismatch between the pull-up and pull-down transistors. Hence, a common-mode feedback circuit is not necessary.
 
     Based on the simulated transconductance and noise of the OTA, the swing at its input should be limited to a differential peak-to-peak voltage of 80 mV.  FIG. 13  displays an embodiment of a voltage limiter 66 suitable for this purpose. Its output signal level is changed by alternatively steering the current I SS  into resistor R 2  (connected to V o1 ) when the 19.5 Hz (20 KHz/1024) output signal (Φ CLK ) of the frequency divider is low, or by steering I SS  into the parallel combination of R 1  and R 2  when Φ CLK  is high. For the V o2  branch, the operation is the same but with reversed clock signals at the switching transistors. The values of R 1 , R 2  and I SS  can be calculated based on the output voltage swing requirement, where the voltage drop is either I SS ·R 2  or I SS ·(R 1 ∥R 2 ). However, the use of large currents causes high power consumption, while the use of large resistors results in large layout area. In the presented design, a current of 100 μA was chosen in combination with R 1 =82 KΩ and R 2 =6.15 KΩ. The output DC level of the limiter can also be controlled with the values of R 1 , R 2 , and I SS . Since the input DC level of the OTA is 600 mV, the component values are chosen such that the limiter output signal levels at V o1  and V o2  range from 580 mV to 620 mV. Transmission gates are used as switches to minimize the resistance in series with R 1  when the switches are closed.  FIG. 14  shows the transient differential output voltage swing of the limiter, which has a peak-to-peak value close to 80 mV. 
     The amplitude of the limiter output should exhibit as little variation as possible under different process corner and temperature conditions. As depicted in  FIG. 13 , a regulation loop with a differential amplifier is added, in which a dummy transistor M ND  has the same dimensions as transistor M N , such that the voltage at node V X  reflects the variations of R 2  and M N  in the main branches because the transistors have the same gate and source voltages. Any suitable amplifier can be used for this loop. The negative feedback loop adjusts the gate voltage of M ND  such that its drain-to-source voltage is driven to a value close to v ref =580 mV. When M N , M ND , and all resistors are realized with multiple sub-devices that are matched through proper layout, then the I SS ·R 2  product only has a small error between the branches and the drain-to-source voltage of M N  is also equal to V ref  (580 mV) when R 1  is disconnected. Furthermore, the difference between the minimum and maximum output voltages depends on the ratio of the matched resistors, and has a reliable maximum value that is 40 mV higher when the switch in a branch is closed. Consequently, the peak-to-peak differential output signal swing (V o1 −V o2 ) is always close to 80 mV. 
     The test clock signal can be generated with any suitable relaxation oscillator.  FIG. 15  illustrates a block diagram for one suitable relaxation oscillator  62 . The oscillator achieves a power consumption of 4.9 μW with 1.2 V power supply and a temperature coefficient of 314 ppm/° C. The divide-by-1024 operation is implemented through 10 cascaded divide-by-2 stages consisting of D flip-flops with feedback as shown in  FIG. 16 . 
     Test Current Generation Simulation Results 
     The test current generation circuitry described above was designed and simulated using 0.13 μm CMOS technology with 1.2V supply. Since the test signal generator was designed for amplitude-based detection, the effects of process and temperature variations on key parameters were evaluated with foundry-supplied device models. Table 3 summarizes the simulation results for the OTA.  FIG. 17  shows the squared output noise of the test signal generator with a load capacitance of 3 pF.  FIG. 18  shows a noise-limited scenario, in which the simulated output noise significantly degrades the voltage amplitude at the instrumentation amplifier input. For this reason, the voltage amplitude at the OTA input was raised to an 80 mV differential peak-to-peak value, resulting in the instrumentation amplifier input voltage swing with high signal-to-noise ratio in  FIG. 12 .  FIGS. 19( a )and 19( b )  show the OTA&#39;s output impedance and transconductance vs. frequency for different process corner cases and temperatures. The output impedance remains above 1 GΩ up to 100 Hz, and the variation of the transconductance is approximately 20% in the worst case, which is acceptable if the reference voltages of the comparator bank ( FIG. 10 ) are chosen to cover the anticipated worst case. Table 4 reveals that the phase margin of the negative feedback loop in  FIG. 13  is always higher than 60° , ensuring the stability of the circuit. The worst amplitude error (3.2%) of the limiter occurs in the slow corner case at 85° C. Depending on the layout quality, an additional error of 1-3% could be introduced due to device mismatches. However, a worst-case total amplitude error of less than 6% could be acceptable, depending on the application. 
     
       
         
           
               
             
               
                 TABLE 3 
               
             
            
               
                   
               
               
                 OTA SIMULATED RESULTS 
               
            
           
           
               
               
            
               
                 Performance 
                 OTA 
               
               
                   
               
            
           
           
               
               
               
            
               
                 Output impedance at 100 Hz 
                 2.9 
                 GΩ 
               
               
                 Transconductance 
                 25.9 
                 pS 
               
               
                 Output-referred noise, 0.01 Hz-100 Hz 
                 78 
                 μV 
               
               
                 HD3 (of i out , sinusoidal V in  = 80 mV p-p  at 19.5 Hz) 
                 −30.1 
                 dB 
               
               
                 CMRR mean/standard deviation (with mismatch*) 
                 69 dB/7.2 
                 dB 
               
               
                 PSRR mean/standard deviation (with mismatch*) 
                 56 dB/6.5 
                 dB 
               
               
                 Supply current 
                 168 
                 nA 
               
               
                   
               
               
                 *100 Monte Carlo simulations with a load capacitance of 3 pF at 60 Hz. 
               
            
           
         
       
     
     
       
         
           
               
             
               
                 TABLE 4 
               
             
            
               
                   
               
               
                 SIMULATED DIFFERENTIAL OUTPUT VOLTAGE 
               
               
                 SWING OF THE LIMITER AND PHASE MARGIN 
               
               
                 IN ITS REGULATION LOOP 
               
            
           
           
               
               
               
               
               
            
               
                   
                   
                   
                 Differential 
                   
               
               
                   
                   
                   
                 Output 
               
               
                   
                 Process 
                 Temperature 
                 Swing (mV) 
                 Phase Margin 
               
               
                   
                   
               
               
                   
                 Typical 
                 −30° C.  
                 81.1 mV 
                 64.3 deg. 
               
               
                   
                   
                 27° C. 
                 80.4 mV 
                 68.9 deg. 
               
               
                   
                   
                 85° C. 
                 79.2 mV 
                 72.8 deg. 
               
               
                   
                 Fast 
                 −30° C.  
                 82.2 mV 
                 65.4 deg. 
               
               
                   
                   
                 27° C. 
                 81.0 mV 
                 70.2 deg. 
               
               
                   
                   
                 85° C. 
                 78.6 mV 
                 73.9 deg. 
               
               
                   
                 Slow 
                 −30° C.  
                 78.4 mV 
                 64.1 deg. 
               
               
                   
                   
                 27° C. 
                 78.4 mV 
                 68.7 deg. 
               
               
                   
                   
                 85° C. 
                 77.8 mV 
                 72.4 deg. 
               
               
                   
                   
               
            
           
         
       
     
     One embodiment of a calibration circuit is now described with reference to  FIGS. 8 and 20-26 . Referring to  FIG. 8 , an embodiment of the calibration circuit includes a test amplifier  32  ( FIG. 23 ) connected to the output of the instrumentation amplifier or to gain or filtering stages downstream of the instrument amplifier. The test amplifier provides amplified input voltage signals to a bank of comparators (designed as depicted in  FIG. 24 ) that in turn provides input signals to a calibration unit  30  including processor control and memory ( FIG. 21 ). An oscillation detection unit  36  is operative to detect oscillation events at the output of the instrumentation amplifier and provide a signal indicative of the oscillation event to the calibration unit. The calibration unit is operative to compare measured voltage amplitudes from the instrumentation amplifier to a plurality of reference voltages from the comparator bank  34  and to generate a plurality of control signals response to the comparison, as described further below. The control signals are transmitted to the programmable capacitors ( FIG. 4 ) of the instrumentation amplifier to optimize the negative capacitance generated at the IA&#39;s input. 
     An embodiment of a digital calibration process is depicted as a flowchart in  FIG. 20 . A start signal resets all registers at the beginning of the calibration process. The functions of setting the control signals for switches, decision-making, and saving the desired values in memory are completed during each cycle of the process. The calibration unit is implemented by control block  31  and memory block  33  shown in  FIG. 21 . At each step, the calibration unit first sends a reset signal to all the SR latches located at the outputs of the comparators. Then it sets the 8 control signals that are connected to the switches (S 7 -S 0 ) of the IA&#39;s negative capacitance generation block, where the initial output code (switch_code[7:0]) is “00000000”. After waiting for 7 periods of the test signal to allow for settling of the analog signals, the reset signal goes to “0” and the SR latches hold the output values of the four comparators from which the test signal amplitude can be inferred (inbit[3:0]). If the oscillation detection bit is “1”, then the unit will ignore inbit[3:0] and increase the current switch_code by one. If there is no oscillation, then inbit[3:0] is compared with the max_code (initially zero). If inbit[3:0] is equal or larger than max_code, then its value is replaced with max_code in the memory. Furthermore, the related switch_code is saved as best_code in another memory location. Afterwards, the switch_code is incremented by one, and the process is repeated. When the switch_code reaches “11111111” (255 in decimal), then the calibration unit reads the best_code from the memory and applies the corresponding switch_code to the programmable capacitor bank at the IA for optimum impedance at the end of the calibration. The optimum code is applied to the IA&#39;s capacitor bank until the calibration is restarted after changing electrode cables. 
       FIG. 21  shows a diagram of the calibration unit  30  with its input/output ports. The memory block receives the latched outputs of the comparators as inputs. It generates and saves the 8-bit codes to control the switches in the capacitor bank. The main clock for the calibration block is derived from the same oscillator that is part of the test signal generation circuitry (see  FIG. 8 ). The calibration unit uses a clock that is two times faster than the 19.5 Hz test signal. Such low clock speed is sufficient for this application since the test signal has a very low frequency and the calibration block has to wait proportionally to make decisions. The control block works with an internal clock signal (clock_half) generated by the memory block with half the frequency of the main clock. The internal frequency divider is implemented with a 1-bit counter inside of the memory block. The memory cells in the memory block are built by shift registers. Each of the flip-flops in the shift registers imitates the function of an SRAM cell. Therefore, the memory cells require address, read and write signals based on SRAM principles. The code comparisons and final decision-making tasks are also performed in the memory block. 
     The control block  31  contains a 4-bit counter to count the number of test signal cycles after changing the switch_code, which ensures sufficient settling time for the analog signals. The control block also has an 8-bit counter to generate all 256 states of the switch controls, which is sent to the memory block 33 as code_i[7:0] and also sent out as the switch_code for both capacitor banks of the IA (see  FIG. 22 ). The reset signal that is needed to reset the SR latches is generated by the control block during each calibration step. At the end, a finish signal is sent to the memory block  33  from the control block to stop the calibration process. Afterwards, the switch_code will be set to the optimum value and will remain unaltered. 
       FIG. 22  shows an embodiment of an IA schematic and the programmable capacitors that form a negative capacitance generation feedback (NCGFB), generally as described above, which is automatically controlled by the digital calibration unit. Because the IA circuit is not perfectly symmetric (i.e., M 3  is diode-connected while M 4  is not), it can be observed that the optimum result can be achieved by setting the capacitor sizes in the negative path (C n ) to around half of the sizes of the positive path (C p ). The tuning range of the 8-bit capacitor networks should be designed to compensate for the 50-150 pF capacitances from the cables and PCB by generating negative capacitance at the IA input. The switches of the both capacitor banks (see  FIG. 5 ) receive the same control signals from the calibration unit. 
     Depending on the value of the parasitic capacitances, the input capacitance may be overcompensated through the generation of a negative capacitance that is too large (i.e., when the value of switch_code is too high). Actually, as the values of the programmable capacitors are concurrently increased, the best code is the last code before oscillation occurs. With a test input current amplitude of i t =0.5 pA and 20 dB of gain in the IA and filter combination, the voltage swings at the filter output are below 25 mV across process corner cases. Simulations also revealed that the oscillations have amplitudes at the IA output that are at least three times higher, such that an oscillation detection threshold can be set at twice the maximum signal swing during stable operation. As indicated in  FIG. 8 , an oscillation detection comparator is connected at the output of the instrumentation amplifier to check for oscillation events during each iteration in the calibration unit. The calibration method ( FIG. 20 ) ignores the codes that lead to oscillation. All capacitor switch bank settings are tested during the calibration. Thus, only one code is skipped in case the oscillation detector threshold is exceeded due to an unexpected noise source. Choosing the number of bits for the programmable capacitors such that multiple codes meet the minimum input impedance requirement makes the calibration scheme more reliable. In addition, multiple comparators were placed instead of a single comparator to test if the output amplitude is high enough to meet the minimum impedance requirement. To account for the different corner cases and temperature conditions, the input impedance of the IA was set to 500 MΩ to obtain the range of output differential amplitudes. Afterwards, the differential reference levels were defined for the comparators as three equally-spaced values (300 mV p-p , 200 mV p-p , 100 mV p-p ) and one additional (40 mV p-p ) to cover the range with some extra margin below the minimum 
     The delay times are 8 periods of the test signal to allow settling after setting each code; and 2 more periods to compare the new input with previous one in memory, save the results in memory (if needed) and resetting the SR latches. Hence, it takes a total of 10 periods (around 510 ms with a 19.5 Hz test signal) per step, and around 130 s to finish the complete calibration. Note that cable changes are expected to be infrequent, making the wait time acceptable when the calibration is only initiated by the user from time to time. 
     An embodiment of the test amplifier in  FIG. 8  has been designed with a gain of 20 in a prototype system. As displayed in  FIG. 23 , in one embodiment, the amplifier can be implemented with an operational amplifier (low-frequency gain of 41 dB, −3 dB corner frequency of 870 KHz, power consumption of 149 μW) in fully-differential configuration using feedback resistors of 11.17 MΩ and 447 K. With high-resistance polysilicon the layout area of the larger resistor would be 77 μm×140 μm, which is acceptable. The common-mode level at the output of the test amplifier is set to 650 mV. In the main signal path, the transistor-level IA design above was employed together with an adapted version (same architecture) of the filter. 
     Each comparator in the calibration path ( FIG. 8 ) has a propagation delay of 20 μs and 300 μV input-referred offset while consuming 3 μW of power.  FIG. 24  shows an embodiment of the comparator&#39;s schematic. 
     To implement the calibration system on a chip, synthesizable Verilog HDL codes were written for the two digital blocks. All required unit cells were designed and laid out in 130 nm CMOS technology. The Verilog code was synthesized to gate-level netlists with Cadence RTL Complier. Cadence Encounter was used to automatically place and route the layouts from the generated gate-level netlists. The layout of the calibration unit is displayed in  FIG. 25 . It occupies a total chip area of approximately 0.062 mm 2  in 130 nm CMOS technology. The total power consumption of the digital calibration unit at the main clock frequency of 39 Hz is 1.2 μW with 1.2 V supply voltage. A summary of the digital calibration unit specifications is given in Table 5. 
     
       
         
           
               
             
               
                 TABLE 5 
               
             
            
               
                   
               
               
                 DIGITAL CALIBRATION UNIT SUMMARY 
               
            
           
           
               
               
               
               
               
            
               
                   
                 Block 
                 Number of Gates 
                 Area 
                 Power 
               
               
                   
                   
               
               
                   
                 Control 
                 113 
                 0.026 mm 2   
                 — 
               
               
                   
                 Memory 
                 146 
                 0.036 mm 2   
                 — 
               
               
                   
                 Total 
                 259 
                 0.062 mm 2   
                 1.2 μW 
               
               
                   
                   
               
            
           
         
       
     
     Calibration Simulation Results 
     The transistor-level analog EEG front-end blocks and the Verilog HDL codes of calibration unit were evaluated together with Cadence AMS simulations. Furthermore, Cadence Spectre simulations were performed using the transistor-level synthesized version of the calibration unit (by itself) to verify that the outcome matches the results with the functional code. Finally, a post-layout simulation of the standalone calibration unit was performed to confirm that the outputs match the schematic and functional (Verilog HDL) simulations. 
       FIG. 26  shows the Cadence output waveforms of the test amplifier and the digital signals that control the switches in the capacitor bank. The test current generator is disconnected when the “finish” signal (the topmost digital signal in the figure) transitions to high. If oscillation occurs as in  FIG. 26 , then the oscillation detection bit (second digital signal from the top) is set to “1”. In this case, the calibration block saves the best code without oscillation and sets the switches to it after cycling through all combinations. In the typical process corner case with parasitic capacitances (C inp  and C inn  in  FIG. 8 ) at the IA input both equal to 100 pF, the best code identified by the calibration system is “01010111”. With this code, the simulated input impedance is equal to 2.2 GΩ at 50 Hz. Table 6 lists simulation results of an EEG front-end with the calibration unit for other process corner cases and parasitic input capacitances in the 50-150 pF range. In all cases, the simulated input impedance of the IA remains above the 500 MΩ target for dry-contact EEG measurement methods. 
     
       
         
           
               
             
               
                 TABLE 6 
               
             
            
               
                   
               
               
                 SIMULATION RESULTS FOR DIFFERENT PARASITIC 
               
               
                 CAPACITANCE VALUES AND PROCESS CORNERS 
               
            
           
           
               
               
               
               
            
               
                 C inp , C inn   
                 Switch Control Code 
                 Process 
                 IA Input 
               
               
                 (in FIG. 1) 
                 (S x7 -S x0  in FIG. 4) 
                 Corner 
                 Impedance 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 150 pF, 150 pF 
                 10011001 
                 SS 
                 1.12 
                 GΩ 
               
               
                 150 pF, 150 pF 
                 10101101 
                 TT 
                 1.90 
                 GΩ 
               
               
                 150 pF, 150 pF 
                 10111111 
                 FF 
                 2.34 
                 GΩ 
               
               
                 150 pF, 100 pF 
                 01011111 
                 SS 
                 669 
                 MΩ 
               
               
                 150 pF, 100 pF 
                 01110101 
                 TT 
                 1.28 
                 GΩ 
               
               
                 150 pF, 100 pF 
                 01111111 
                 FF 
                 873 
                 MΩ 
               
               
                 100 pF, 100 pF 
                 01001001 
                 SS 
                 1.33 
                 GΩ 
               
               
                 100 pF, 100 pF 
                 01010111 
                 TT 
                 2.20 
                 GΩ 
               
               
                 100 pF, 100 pF 
                 01011111 
                 FF 
                 1.47 
                 GΩ 
               
               
                 100 pF, 50 pF  
                 00001101 
                 SS 
                 859 
                 MΩ 
               
               
                 100 pF, 50 pF  
                 00011011 
                 TT 
                 1.53 
                 GΩ 
               
               
                 100 pF, 50 pF  
                 00100101 
                 FF 
                 1.70 
                 GΩ 
               
               
                 50 pF, 50 pF 
                 00000000 
                 SS 
                 10.30 
                 GΩ 
               
               
                 50 pF, 50 pF 
                 00000001 
                 TT 
                 2.77 
                 GΩ 
               
               
                 50 pF, 50 pF 
                 00000111 
                 FF 
                 2.49 
                 GΩ 
               
               
                   
               
            
           
         
       
     
     It will be appreciated that the various features of the embodiments described herein can be combined in a variety of ways. For example, a feature described in conjunction with one embodiment may be included in another embodiment even if not explicitly described in conjunction with that embodiment. 
     The present invention has been described with reference to the preferred embodiments. It is to be understood that the invention is not limited to the exact details of construction, operation, exact materials or embodiments shown and described, as obvious modifications and equivalents will be apparent to one skilled in the art. It is believed that many modifications and alterations to the embodiments disclosed will readily suggest themselves to those skilled in the art upon reading and understanding the detailed description of the invention. It is intended to include all such modifications and alterations insofar as they come within the scope of the present invention. 
     The calibration system and method can be implemented on the same chip as the IA. In one embodiment, calibration can be activated by a user of the application of which the IA with calibration is a part. For example, upon changing electrode cables, the calibration can be activated. The activation can be performed in any suitable manner, such as by a button or switch, or through a graphical or other computer-implemented interface with the application. The activation can be performed automatically, for example, upon detection of an event such as connection of new cables. 
     It will be appreciated that the calibration circuit illustrated by the ADC and DSP in  FIG. 1  can be implemented in a variety of ways in addition to the particular implementations described with reference to  FIGS. 8-26 . Similarly, the instrumentation amplifier  12  of  FIG. 1  can be implemented in other ways in addition to the particular implementation described above. Also, while the instrumentation amplifier circuit has been described as particularly appropriate for biosensing measurements, it will be appropriated that the circuit and method can be used for other applications for which input impedance boosting would be desirable. 
     It will be appreciated that the various features of the embodiments described herein can be combined in a variety of ways. For example, a feature described in conjunction with one embodiment may be included in another embodiment even if not explicitly described in conjunction with that embodiment. 
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