Patent Publication Number: US-10761969-B2

Title: Nonvolatile memory device and operation method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     A claim for priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 10-2017-0136042 filed Oct. 19, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     The present inventive concepts relate to a semiconductor memory, and more particularly to a nonvolatile memory device and an operation method thereof. 
     Semiconductor memory devices are classified into volatile memory devices such as static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like which lose data stored therein when powered-off, and nonvolatile memory devices such as read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like which retain data when powered-off. 
     A storage device may be characterized as including a nonvolatile memory device, and a memory controller that controls the nonvolatile memory device. The nonvolatile memory device typically receives a control signal and a data signal from the memory controller. The input signal may be transmitted to the nonvolatile memory device through an interface that connects the nonvolatile memory device and the memory controller. In the case where a failure occurs in an operation of the storage device, debugging may be performed on the storage device. Software code, a memory controller, an interface, and the like that cause the failure may be targeted for debugging. 
     SUMMARY 
     Embodiments of the inventive concepts provide a nonvolatile memory device including debugging for an interface between a memory controller and the nonvolatile memory device, and an operation method thereof. 
     Embodiments of the inventive concepts provide an operation method of a nonvolatile memory device, the nonvolatile memory device including a signal storage circuit, a debugging information generator and a debugging information register. The operation method includes receiving, by the signal storage circuit, control signals and a data signal from external of the nonvolatile memory device; generating, by the debugging information generator, debugging information based on the control signals and the data signal; receiving a debugging information request from external of the nonvolatile memory device; and outputting, by the debugging information register, the debugging information in response to the debugging information request. 
     Embodiments of the inventive concepts further provide a nonvolatile memory device including a signal storage circuit that stores control signals and a data signal received from external of the nonvolatile memory device; a debugging information generator that generates debugging information based on the stored control signals and the stored data signal; and a debugging information register that outputs the debugging information in response to a debugging information external of the nonvolatile memory device. 
     Embodiments of the inventive concepts still further provide a nonvolatile memory package including an interface chip that receives control signals and a data signal through an external channel connected with a memory controller; a first nonvolatile memory device that receives first control signals and a first data signal through a first internal channel connected with the interface chip; and a second nonvolatile memory device that receives second control signals and a second data signal through a second internal channel connected with the interface chip. The interface chip includes a debugging support circuit that outputs first and second debugging information in response to a debugging information request from the memory controller. The debugging support circuit generates the first debugging information associated with the first nonvolatile memory device from the first control signals and the first data signal, and generates the second debugging information associated with the second nonvolatile memory device from the second control signals and the second data signal. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The above and other objects and features of the inventive concepts will become apparent in view of the following detailed description as taken with reference to the accompanying drawings. 
         FIG. 1  illustrates a block diagram of a storage device according to an embodiment of the inventive concepts. 
         FIG. 2  illustrates a flowchart of a debugging information providing operation of a nonvolatile memory device of  FIG. 1 . 
         FIG. 3  illustrates a timing diagram of a debugging information providing operation of the nonvolatile memory device of  FIG. 1 . 
         FIG. 4  illustrates a view of a debugging support circuit according to an embodiment of the inventive concepts. 
         FIG. 5  illustrates a view of debugging information that the debugging support circuit of  FIG. 4  provides. 
         FIG. 6  illustrates a flowchart of an operation method in which the debugging support circuit of  FIG. 4  provides first debugging information. 
         FIG. 7  illustrates a timing diagram of an operation of providing first debugging information. 
         FIG. 8  illustrates a flowchart of an operation method in which the debugging support circuit of  FIG. 4  provides second debugging information. 
         FIG. 9  illustrates a timing diagram of an operation of providing second debugging information. 
         FIG. 10  illustrates a flowchart of an operation method in which the debugging support circuit of  FIG. 4  provides third debugging information. 
         FIG. 11  illustrates a timing diagram of an operation of providing third debugging information. 
         FIG. 12  illustrates a flowchart of an operation method in which the debugging support circuit of  FIG. 4  provides fourth debugging information. 
         FIG. 13  illustrates a timing diagram of an operation of providing fourth debugging information. 
         FIG. 14  illustrates a flowchart of an operation method in which the debugging support circuit of  FIG. 4  provides fifth debugging information. 
         FIG. 15  illustrates a timing diagram of an operation of providing fifth debugging information. 
         FIG. 16  illustrates a flowchart of an operation method in which the debugging support circuit of  FIG. 4  provides sixth debugging information. 
         FIG. 17  illustrates a timing diagram of an operation of providing sixth debugging information. 
         FIG. 18  illustrates a view of the storage device according to another embodiment of the inventive concepts. 
         FIG. 19  illustrates a view of the storage device according to a still further embodiment of the inventive concepts. 
         FIG. 20  illustrates a block diagram of a solid state drive system to which the nonvolatile memory device according to the inventive concepts is applied. 
     
    
    
     DETAILED DESCRIPTION 
     As is traditional in the field of the inventive concepts, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the inventive concepts. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the inventive concepts. 
       FIG. 1  illustrates a block diagram of a storage device according to an embodiment of the inventive concepts. Referring to  FIG. 1 , a storage device  10  includes a nonvolatile memory device  100  and a memory controller  200 . 
     The memory controller  200  may control an operation of the nonvolatile memory device  100 . In an embodiment, the memory controller  200  may provide a control signal CTRL and a data signal DQ to the nonvolatile memory device  100  through different signal lines or different signal pins, to control the nonvolatile memory device  100 . 
     For example, the memory controller  200  may provide the nonvolatile memory device  100  with a chip enable signal CE/, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE/, a read enable signal RE/, a data strobe signal DQS, and a data signal DQ, through different signal pins. 
     The chip enable signal CE/, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WE/, the read enable signal RE/, and the data strobe signal DQS may be included in the control signal CTRL provided from the memory controller  200 . The memory controller  200  may provide the control signal CTRL and the data signal DQ to the nonvolatile memory device  100  to direct the nonvolatile memory device  100  to perform various operations. 
     The memory controller  200  may provide the nonvolatile memory device  100  with a command CMD, an address ADDR, and the data “DATA” through a data pin (DQ pin) to which the data signal DQ is provided. The memory controller  200  may receive the data “DATA” from the nonvolatile memory device  100  through a data pin. 
     The memory controller  200  may transmit data “DATA” to the nonvolatile memory device  100  to store the data “DATA” in the nonvolatile memory device  100 , or may read the data “DATA” from the nonvolatile memory device  100 . For example, the memory controller  200  may provide the command CMD, the address ADDR, and the data “DATA” to the nonvolatile memory device  100  such that the data “DATA” are stored in the nonvolatile memory device  100  at an address corresponding to the address ADDR. The memory controller  200  may provide the command CMD and the address ADDR to the nonvolatile memory device  100  to read the data “DATA” from the nonvolatile memory device  100  at an address corresponding to the address ADDR. The memory controller  200  may provide the control signal CTRL as well as the data signal DQ to the nonvolatile memory device  100  for the purpose of storing and reading the data “DATA”. 
     The nonvolatile memory device  100  performs a corresponding operation in response to the control signal CTRL and the data signal DQ provided from the memory controller  200 . For example, the nonvolatile memory device  100  may receive the data signal DQ, in which the command CMD and the address ADDR are included, from the memory controller  200  and may provide the data “DATA” to the memory controller  200 . 
     The nonvolatile memory device  100  may determine whether signals provided through the data signal DQ are the command CMD, the address ADDR, or the data “DATA”, based on the control signal CTRL. For example, the nonvolatile memory device  100  may determine a type of the data signal DQ, based on the chip enable signal CE/, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WE/, the read enable signal RE/, and the data strobe signal DQS. 
     In an embodiment, the nonvolatile memory device  100  may include NAND flash memory. However, the inventive concepts are not limited to nonvolatile memory device  100  including NAND flash memory. That is, in other embodiments the nonvolatile memory device  100  may include at least one of volatile or nonvolatile memories such as for example SRAM, DRAM, SDRAM, ROM, PROM, EPROM, EEPROM, flash memory, PRAM, MRAM, RRAM, FRAM, and the like. 
     The nonvolatile memory device  100  according to an embodiment of the inventive concepts includes a debugging support circuit  110 . In an embodiment, the debugging support circuit  110  may be implemented in the form of software, hardware, or a combination thereof. The debugging support circuit  110  may store an input signal (e.g., the control signal CTRL and the data signal DQ) provided from the memory controller  200 , and may generate debugging information DBI from the stored input signal. Upon receiving a debugging information request DIR from the memory controller  200 , the debugging support circuit  110  may provide the debugging information DBI to the memory controller  200 . 
     The memory controller  200  may receive a debugging request for signals provided to the nonvolatile memory device  100  from a host (not illustrated). The memory controller  200  may provide the debugging information request DIR to the nonvolatile memory device  100  through the data signal DQ. The debugging support circuit  110  may provide the stored debugging information DBI to the memory controller  200  through the data signal DQ in response to the debugging information request DIR. The memory controller  200  may receive the debugging information DBI and may provide the received debugging information DBI to the host (not illustrated). 
     In an embodiment, the memory controller  200  may provide a debugging mode “MODE” to the nonvolatile memory device  100  through the data signal DQ. The debugging support circuit  110  may output only the debugging information DBI of a corresponding mode from among a plurality of modes in response to the debugging mode “MODE”. As such, in response to the debugging mode “MODE”, the debugging support circuit  110  may provide the host (not illustrated) with only certain debugging information DBI from among various kinds of debugging information DBI which the host (not illustrated) requires. 
     In the case where power is supplied to the nonvolatile memory device  100  and an operation of the debugging support circuit  110  starts, the debugging support circuit  110  may generate the debugging information DBI and may store the generated debugging information DBI. 
     In an embodiment, although not illustrated in  FIG. 1 , the memory controller  200  may provide a debugging enable signal and a debugging disable signal to the nonvolatile memory device  100  through the data signal DQ. In the case where the debugging enable signal is received, the nonvolatile memory device  100  may operate the debugging support circuit  110 . The debugging support circuit  110  may generate the debugging information DBI in response to the debugging enable signal. In the case where the debugging disable signal is received, the nonvolatile memory device  100  may stop the operation of the debugging support circuit  110 . The debugging support circuit  110  may stop generating the debugging information DBI in response to the debugging disable signal. 
     In an embodiment, the debugging support circuit  110  may generate the debugging information DBI within a given time or of a given memory capacity. In the case where the debugging support circuit  110  continues to store the debugging information DBI, the capacity of a memory storing the debugging information DBI may be insufficient. Accordingly, the debugging support circuit  110  may store the debugging information DBI generated most recently or may store the debugging information DBI only of a given memory capacity. 
     As such, the storage device  10  according to an embodiment of the inventive concepts may provide various debugging information DBI to the host (not illustrated) through the debugging support circuit  110 . Accordingly, in the case where a failure arises from the storage device  10 , the host (not illustrated) may check whether an interface between the memory controller  200  and the nonvolatile memory device  100  causes the failure. 
     As described above, the debugging information request DIR and the debugging information DBI may be provided through the data signal DQ. However, the inventive concepts are not limited to providing the debugging information request DIR and the debugging information DBI through the data signal DQ. For example, the debugging information request DIR and the debugging information DBI may be provided through a separate pin. Also, the control signal CTRL and the data signal DQ illustrated in  FIG. 1  are only one exemplification of the inventive concepts, and the inventive concepts are not limited as here described. For example, the inventive concepts may provide the host (not illustrated) with the debugging information DBI associated with various kinds of control signals and data signals as well as the control signal CTRL and the data signal DQ illustrated in  FIG. 1 . 
     Below, for convenience of description, an operation of the debugging support circuit  110  will be described on the basis of the control signal CTRL and the data signal DQ illustrated in  FIG. 1 . 
       FIG. 2  illustrates a flowchart of a debugging information providing operation of a nonvolatile memory device of  FIG. 1 . Referring to  FIGS. 1 and 2 , in operation S 111 , the nonvolatile memory device  100  receives an input signal from the memory controller  200 . The input signal may include the control signal CTRL and the data signal DQ. 
     In operation S 112 , the nonvolatile memory device  100  detects the input signal. In an embodiment, the nonvolatile memory device  100  may detect a change or a level of the control signal CTRL thus provided. 
     In operation S 113 , the nonvolatile memory device  100  stores the input signal based on the detection result. In an embodiment, the nonvolatile memory device  100  may store input signals provided through different pins, respectively. The nonvolatile memory device  100  may detect a change of the control signal CTRL, and may store the control signal CTRL and the data signal DQ at a time when the change is detected. The nonvolatile memory device  100  may detect a change and a magnitude of the control signal CTRL to determine and store the data signal DQ as the command CMD, the address ADDR, or the data “DATA”. 
     In operation S 114 , the nonvolatile memory device  100  generates the debugging information DBI based on the stored input signal. In an embodiment, the nonvolatile memory device  100  may decode the input signal to check what a value of the input signal indicates. The nonvolatile memory device  100  may determine the validity of the input signal to generate the debugging information DBI. 
     In operation S 115 , the nonvolatile memory device  100  receives the debugging information request DIR from the memory controller  200 . For example, the nonvolatile memory device  100  may receive the debugging information request DIR through the data signal DQ. 
     In operation S 116 , the nonvolatile memory device  100  outputs the debugging information DBI in response to the debugging information request DIR. The debugging information DBI output in operation S 116  may include the input signal stored in operation S 113  or the debugging information DBI generated in operation S 114 . The nonvolatile memory device  100  may provide the debugging information DBI to the memory controller  200  through the data signal DQ. 
     As described above, the nonvolatile memory device  100  of the inventive concepts may perform operation S 111  to operation S 116  to output the debugging information DBI. In detail, operation S 111  to operation S 116  may be performed through the debugging support circuit  110  of the nonvolatile memory device  100 . 
       FIG. 3  illustrates a timing diagram of a debugging information providing operation of a nonvolatile memory device of  FIG. 1 . For a brief description and for brevity of illustration, a program sequence will be described with reference to signals provided to the nonvolatile memory device  100  of  FIG. 1 . However, in other embodiments the debugging information providing operation may be performed with respect to a reading operation or other operation. For brevity of illustration, the respective signals are schematically illustrated, but the inventive concepts are not limited thereto. 
     Referring to  FIGS. 1 and 3 , the memory controller  200  transmits the control signal CTRL and the data signal DQ for a page program operation to the nonvolatile memory device  100 . During a page setup period, the memory controller  200  may provide the command CMD, the address ADDR, and the data “DATA” to the nonvolatile memory device  100  through the data signal DQ. The memory controller  200  may sequentially provide a first command C 1 , first to fifth addresses A 1  to A 5 , first to n-th data D 1  to Dn, and a second command C 2 . In an embodiment, the first command C 1  may be a data input command (e.g., 80h) for a page program operation, and the second command C 2  may be a confirm command (e.g., 10h) for the page program operation. The first to fifth addresses A 1  to A 5  may be an address of a memory area of the nonvolatile memory device  100 , in which the first to n-th data D 1  to Dn will be programmed. The first to fifth addresses A 1  to A 5  may include a column address and a row address. 
     During the page setup period, the chip enable signal CE/ is at a low level. First, when the command latch enable signal CLE is at a high level, the first command C 1  is provided at a rising edge of the write enable signal WE/. Then, when the address latch enable signal ALE is at a high level, the first to fifth addresses A 1  to A 5  are respectively provided at rising edges of the write enable signal WE/. Afterwards, the first to n-th data signals D 1  to Dn are provided at rising edges and falling edges of the data strobe signal DQS. The command latch enable signal CLE may thereafter transition to a high level, and the second command C 2  is provided at a rising edge of the write enable signal WE/. 
     The debugging support circuit  110  of the nonvolatile memory device  100  may store the control signal CTRL and the data signal DQ provided during the page setup period. For example, during the page setup period, the debugging support circuit  110  may detect a rising edge of the write enable signal WE/ to store the control signal CTRL and the data signal DQ. 
     To request the debugging information DBI, the memory controller  200  may provide the debugging information request DIR to the nonvolatile memory device  100  at a first time t 1 . The memory controller  200  may provide the debugging information request DIR through the data signal DQ. In an embodiment, the debugging information request DIR may be a read command, a combination of specific commands, a vendor specific command, or a combination thereof. 
     After receiving the debugging information request DIR, the nonvolatile memory device  100  may provide the stored debugging information DBI to the memory controller  200 . For example, in an output period of the debugging information DBI, the read enable signal RE/ may transition to a high level and a low level repeatedly (toggling). The data strobe signal DQS may transition to a high level and a low level repeatedly, with a given time interval existing between the data strobe signal DQS and the read enable signal RE/. The nonvolatile memory device  100  may sequentially output the debugging information DBI based on rising edges and falling edges of the data strobe signal DQS. 
     During a debugging information output period, the debugging support circuit  110  may provide the stored control signal CTRL and the stored data signal DQ as the debugging information DBI. Also, the debugging support circuit  110  may provide various debugging information DBI generated from the stored control signal CTRL and the stored data signal DQ. The debugging information DBI that the debugging support circuit  110  provides will be more fully described later. 
     As illustrated in  FIG. 3 , an operation of providing the debugging information DBI on the basis of an exemplification in which the control signal CTRL and the data signal DQ for the page program operation are input. However, the inventive concepts are not limited thereto. For example, even though various control and data signals for performing various operations are input, the nonvolatile memory device  100  may perform an operation similar to the above-described operation to provide the debugging information DBI. 
     Hereinafter, an operation of the debugging support circuit  110  will be more fully described. For convenience of description, an operation of the debugging support circuit  110  will be described on the basis of an embodiment in which the debugging support circuit  110  operates in response to the debugging mode “MODE”. However, the inventive concepts are not limited to the following description. 
       FIG. 4  illustrates a view of a debugging support circuit according to an embodiment of the inventive concepts. Referring to  FIGS. 1 and 4 , the debugging support circuit  110  includes a signal storage circuit  111 , a debugging information generator  112 , a debugging information register  113 , and an output circuit  114 . 
     The signal storage circuit  111  detects an input signal provided to the nonvolatile memory device  100 . In an embodiment, the signal storage circuit  111  may detect a change and a magnitude of the control signal CTRL. For example, the signal storage circuit  111  may detect a rising edge, a falling edge, a high level, a low level, or the like of the control signal CTRL. 
     The signal storage circuit  111  stores the input signal based on the detection result. In an embodiment, the signal storage circuit  111  may store a level of the control signal CTRL or a level of the data signal DQ. The signal storage circuit  111  may determine and store signals input through different pins. For example, the signal storage circuit  111  may determine and store the command CMD, the address ADDR, or the data “DATA” as the data signal DQ. The signal storage circuit  111  may store the input signal based on a time or a memory capacity. 
     The signal storage circuit  111  may store the input signal by using at least one of e-fuses, flip-flops, or latches of a page buffer (not illustrated). 
     The debugging information generator  112  decodes signals stored in the signal storage circuit  111  to generate various kinds of debugging information DBI. The debugging information generator  112  may determine whether each of the stored control signal CTRL and the stored data signal DQ has a valid value and may generate various kinds of debugging information DBI based on the determination result, that is, the validity. 
     In an embodiment, the debugging information generator  112  may determine the validity of the data signal DQ on the basis of a permissible value or a range that the data signal DQ may be depending on a type of the data signal DQ. The value or range that the data signal DQ is able to have may be set in advance according to the specifications of a chip or a circuit. 
     The debugging information register  113  stores the debugging information DBI and may output the stored debugging information DBI in response to the debugging information request DIR. The debugging information register  113  may store information stored in the signal storage circuit  111  as well as the debugging information DBI generated in the debugging information generator  112 , as the debugging information DBI. The debugging information register  113  may store an input signal based on a time or a memory capacity. 
     The output circuit  114  outputs the debugging information DBI generated in the debugging support circuit  110 . The output circuit  114  may output all the debugging information DBI stored in the debugging support circuit  110  in response to the debugging information request DIR. Alternatively, as illustrated in  FIG. 4 , the output circuit  114  may output the debugging information DBI, which corresponds to the debugging mode “MODE”, from among a plurality of debugging information DBI. The output circuit  114  may include a multiplexer. 
     For example, in the case where first to sixth debugging modes MODE[ 1 ] to MODE[ 6 ] are received, the output circuit  114  may output first to sixth debugging information DBI[  1 ] to DBI[ 6 ] respectively corresponding to the first to sixth debugging modes MODE[ 1 ] to MODE[ 6 ]. 
       FIG. 5  illustrates a view of debugging information that a debugging support circuit of  FIG. 4  provides. In detail, the debugging support circuit  110  may provide the first to sixth debugging information DBI[ 1 ] to DBI[ 6 ]. Referring to  FIGS. 4 and 5 , the debugging support circuit  110  may provide an accumulated data signal DQ as the first debugging information DBI[ 1 ]. 
     In an embodiment, the signal storage circuit  111  may detect changes of the control signal CTRL and may store the data signal DQ based on the detected result. The debugging information register  113  may accumulate and store the data signal DQ stored in the signal storage circuit  111 . The accumulated data signal may include the command CMD, the address ADDR, and the data “DATA”. The debugging information register  113  may output the accumulated data signal as the first debugging information DBI[ 1 ]. A host (not illustrated) may check the data signal DQ input to the nonvolatile memory device  100  from the accumulated data signal. For example, the host may compare the data signal DQ input to the nonvolatile memory device  100  with the accumulated data signal. 
     The debugging support circuit  110  may provide information about a type of the data signal DQ as the second debugging information DBI[ 2 ]. In an embodiment, the signal storage circuit  111  may determine a type of the data signal DQ and may store the data signal DQ by using flags. The signal storage circuit  111  may determine a type of the data signal DQ as the command CMD, the address ADDR, or the data “DATA” and may store the command CMD, the address ADDR, and the data “DATA” by using different flags. For example, in the case that an input data signal DQ is the command CMD, the signal storage circuit  111  may store a flag value of “1”. In the case that the input data signal DQ is the address ADDR, the signal storage circuit  111  may store a flag value of “0”. In an embodiment, a type of the data signal DQ may be determined based on a level of the control signal CTRL at a time when the data signal DQ is received. 
     The debugging information register  113  may accumulate and store data signal flags stored in the signal storage circuit  111 . The debugging information register  113  may provide the accumulated data signal flag as the second debugging information DBI[ 2 ]. The host (not illustrated) may check a type of the data signal DQ input to the nonvolatile memory device  100  from the data signal flag. 
     The debugging support circuit  110  may provide information about the validity of the command/address as the third debugging information DBI[ 3 ]. In an embodiment, the debugging information generator  112  may decode the data signal DQ to determine whether a value indicated by the command CMD is valid. Also, the debugging information generator  112  may decode the data signal DQ to determine whether a value indicated by the address ADDR is valid. The debugging information generator  112  may generate flags based on the validity of the command/address associated with the data signal DQ indicating one operation command. 
     The debugging information register  113  may store the generated command/address validity flags and may provide the stored command/address validity flags as the third debugging information DBI[ 3 ]. The host (not illustrated) may determine whether the command CMD and the address ADDR input to the nonvolatile memory device  100  are valid, from the command/address validity flags. 
     The debugging support circuit  110  may provide the number of valid commands and addresses as the fourth debugging information DBI[ 4 ]. In an embodiment, the debugging information generator  112  may determine whether a value indicated by each of the command CMD and the address ADDR is valid and may calculate how many commands CMD and addresses ADDR are valid (i.e., a sum of the number of valid commands and the number of valid addresses). 
     The debugging information register  113  may store the number of valid commands and addresses thus calculated. The debugging information register  113  may provide the number of valid commands and addresses thus stored as the fourth debugging information DBI[ 4 ]. The host (not illustrated) may check the number of valid commands and addresses input to the nonvolatile memory device  100  from the number of valid commands and addresses. 
     The debugging support circuit  110  may provide the number of operations (meaning how many times the operation is performed) as the fifth debugging information DBI[ 5 ]. The number of operations indicates the number of operations performed in the nonvolatile memory device  100  in response to an input signal provided to the nonvolatile memory device  100 . In an embodiment, the debugging information generator  112  may decode the command CMD to determine one operation command, and may calculate the number of operations if all the commands CMD of the data signal DQ indicating one operation command are valid. The debugging information generator  112  may determine a type of an operation (e.g., a page program operation, a data read operation, and the like) performed in the nonvolatile memory device  100 , to calculate the number of operations. 
     The debugging information register  113  may store the number of operations thus calculated and may provide the number of operations thus stored as the fifth debugging information DBI[ 5 ]. The host (not illustrated) may check the number of operations performed in the nonvolatile memory device  100  from the number of operations provided as the fifth debugging information DBI[ 5 ]. 
     The debugging support circuit  110  may provide the validity of combinations of input signals as the sixth debugging information DBI[ 6 ]. In an embodiment, the debugging information generator  112  may determine whether combinations of values indicated by input signals provided through different pins at specific times are valid. For example, the debugging information generator  112  may determine whether combinations of input signals input at clock activation times (e.g., rising edges of the write enable signal WE/) are valid. The debugging information generator  112  may generate flags based on the validity. 
     The debugging information register  113  may store the validity of the combinations of the input signals thus generated and provide input signal combination flags as the sixth debugging information DBI[ 6 ]. The host (not illustrated) may check a state of input signals input to the nonvolatile memory device  100  at specific times from the input signal combination flags. For example, the host may check if a state of input signals input to the nonvolatile memory device  100  at a specific time from among a plurality of specific times is valid based on a corresponding input signal combination flag from among the input signal combination flags. 
     As described above, the host (not illustrated) may determine whether a problem arises from an interface between the nonvolatile memory device  100  and the memory controller  200 , based on the various debugging information DBI provided from the nonvolatile memory device  100 . 
     As described above, the debugging support circuit  110  according to an embodiment of the inventive concepts may generate and store various kinds of debugging information DBI. The debugging support circuit  110  may output the debugging information DBI depending on the debugging information request DIR. The debugging information DBI output from the debugging support circuit  110  is not limited to the debugging information DBI illustrated in  FIG. 5 , and all debugging information DBI that is able to be generated from an input signal may be included. 
       FIG. 6  illustrates a flowchart of an operation method in which a debugging support circuit of  FIG. 4  provides first debugging information. Referring to  FIGS. 4 and 6 , in operation S 121 , the debugging support circuit  110  receives an input signal. For example, the input signal may be the control signal CTRL and/or the data signal DQ. In operation S 122 , the debugging support circuit  110  detects the input signal. In an embodiment, the debugging support circuit  110  may detect rising edges of the write enable signal WE/, or rising edges or falling edges of the data strobe signal DQS. 
     In operation S 123 , the debugging support circuit  110  stores the data signal DQ based on the detection result. In operation S 124 , the debugging support circuit  110  receives the debugging information request DIR. In operation S 125 , the debugging support circuit  110  outputs an accumulated data signal as the first debugging information DB[ 1 ] in response to the debugging information request DIR. 
       FIG. 7  illustrates a timing diagram of an operation of providing first debugging information. Referring to  FIGS. 4 and 7 , in the case where the signal storage circuit  111  detects the rising edges of the write enable signal WE/, and the rising or falling edges of the data strobe signal DQS (e.g., at a first time t 1  to an eleventh time t 11 ), the signal storage circuit  111  may store a signal provided through the data signal DQ. The signal storage circuit  111  may store the data signals DQ corresponding to the first time t 1  to the eleventh time t 11 . For example, the data signals DQ provided at the first time t 1  to the eleventh time t 11  may be “C 1 ”, “A 1 ”, “A 2 ”, “A 3 ”, “A 4 ”, “A 5 ”, “D 1 ”, “D 2 ”, “D 3 ”, “D 4 ”, and “C 2 ”. 
     The debugging information register  113  may accumulate and store the data signal DQ stored in the signal storage circuit  111 . In the case where the debugging support circuit  110  receives the debugging information request DIR, the debugging information register  113  may output the stored data signal DQ as the debugging information DBI. The debugging information register  113  may output values of the following table  1  as the first debugging information DBI[ 1 ]. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 MODE 
                 Debugging Information (DBI) Output 
               
               
                   
                   
               
             
            
               
                   
                 MODE [1] 
                 [C1], [A1], [A2], [A3], [A4], [A5], 
               
               
                   
                   
                 [D1], [D2], [D3], [D4], [C2] 
               
               
                   
                   
               
            
           
         
       
     
       FIG. 8  illustrates a flowchart of an operation method in which a debugging support circuit of  FIG. 4  provides second debugging information. Referring to  FIGS. 4 and 8 , in operation S 131 , the debugging support circuit  110  receives an input signal. In operation S 132 , the debugging support circuit  110  detects the input signal. In an embodiment, the debugging support circuit  110  may detect rising edges of the write enable signal WE/, a high level of the command latch enable signal CLE, a high level of the address latch enable signal ALE, and rising edges or falling edges of the data strobe signal DQS. 
     In operation S 133 , the debugging support circuit  110  stores flags of the data signal DQ based on the detection result. In operation S 134 , the debugging support circuit  110  receives the debugging information request DIR. In operation S 135 , the debugging support circuit  110  outputs accumulated data signal flags as the second debugging information DB[ 2 ] in response to the debugging information request DIR. 
       FIG. 9  illustrates a timing diagram of an operation of providing second debugging information. Referring to  FIGS. 4 and 9 , in the case where the signal storage circuit  111  detects a high level of the command latch enable signal CLE and rising edges of the write enable signal WE/ (e.g., at a first time t 1  and an eleventh time t 11 ), the signal storage circuit  111  may determine and store a signal provided through the data signal DQ as the command CMD. For example, the signal storage circuit  111  may store a value indicating the command CMD by using a data signal flag (e.g., “1”). 
     In the case where the signal storage circuit  111  detects a high level of the address latch enable signal ALE and rising edges of the write enable signal WE/ (e.g., at a second time t 2  to a sixth time t 6 ), the signal storage circuit  111  may determine and store a signal provided through the data signal DQ as the address ADDR. For example, the signal storage circuit  111  may store a value indicating the address ADDR by using a data signal flag (e.g., “0”). 
     In the case where the signal storage circuit  111  detects rising edges or falling edges of the data strobe signal DQS (e.g., at a seventh time t 7  to a tenth time t 10 ), the signal storage circuit  111  may determine and store a signal provided through the data signal DQ as the data “DATA”. For example, the signal storage circuit  111  may store a value indicating the data “DATA” by using a data signal flag (e.g., “2”). 
     The debugging information register  113  may accumulate and store data signal flags stored in the signal storage circuit  111 . In the case where the debugging support circuit  110  receives the debugging information request DIR, the debugging information register  113  may output the stored data signal flags as the debugging information DBI. The debugging information register  113  may output values of the following table  2  as the second debugging information DBI[ 2 ]. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 MODE 
                 Debugging Information (DBI) Output 
               
               
                   
                   
               
             
            
               
                   
                 MODE [2] 
                 [1], [0], [0], [0], [0], [0], [2], [2], [2], [2], [1] 
               
               
                   
                   
               
            
           
         
       
     
       FIG. 10  illustrates a flowchart of an operation method in which a debugging support circuit of  FIG. 4  provides third debugging information. Referring to  FIGS. 4 and 10 , in operation S 141 , the debugging support circuit  110  receives an input signal. In operation S 142 , the debugging support circuit  110  stores the command CMD and the address ADDR. In operation S 143 , the debugging support circuit  110  decodes the command CMD and the address ADDR to determine the validity. The debugging support circuit  110  may determine the validity of the command CMD on the basis of a preset value of the command CMD. Also, the debugging support circuit  110  may determine the validity of the address ADDR on the basis of a preset range of the address ADDR. 
     In operation S 144 , the debugging support circuit  110  stores command/address validity flags based on the determination results. In an embodiment, the debugging support circuit  110  may determine whether all the data signals DQ of each operation unit are valid, and may store the command/address validity flags as the determination result. 
     In operation S 145 , the debugging support circuit  110  receives the debugging information request DIR. In operation S 146 , the debugging support circuit  110  outputs accumulated command/address validity flags as the third debugging information DB[ 3 ] in response to the debugging information request DIR. 
       FIG. 11  illustrates a timing diagram of an operation of providing third debugging information. Referring to  FIGS. 4 and 11 , during a first page setup period (an operation unit) and a second page setup period (another operation unit), the debugging support circuit  110  may receive the control signal CTRL and the data signal DQ. For convenience of description, data “DATA” provided through the data signal DQ are omitted in  FIG. 11 . 
     During the first page setup period and the second page setup period, the signal storage circuit  111  may detect rising edges of the write enable signal WE/, a high level of the command latch enable signal CLE, and a high level of the address latch enable signal ALE. The signal storage circuit  111  may store the data signal DQ input during the first page setup period and the second page setup period based on the detection result. 
     The debugging information generator  112  may decode the data signal DQ stored in the first page setup period. The debugging information generator  112  may compare the stored first and second commands C 1  and C 2  (e.g., “80h” and “10h”) with preset values. In an embodiment, the debugging information generator  112  may determine the first command C 1  as a data input command and the second command C 2  as a confirm command, and may compare values of the first and second commands C 1  and C 2  with the preset values. For example, the debugging information generator  112  may determine that a preset data input command value (e.g., “80h”) corresponding to page setup is matched with a value that the first command C 1  indicates, and may determine that a confirm command value (e.g., “10h”) is matched with a value that the second command C 2  indicates. As such, the debugging information generator  112  may determine that the commands C 1  and C 2  of the data signal DQ input during the first page setup period are valid. 
     The debugging information generator  112  may compare the first to fifth addresses A 1  to A 5  (e.g., “01” to “05”) stored during the first page setup period with a preset range. The debugging information generator  112  may determine that the first to fifth addresses “01” to “05” are within the preset range, from an address range (e.g., “01” to “99”) of a memory area in which preset data will be stored. As such, the debugging information generator  112  may determine that the address ADDR of the data signal DQ input during the first page setup period is valid. 
     Since both the command CMD and the address ADDR of the data signal DQ input during the first page setup period (operation unit) are valid, the debugging information generator  112  may store a command/address validity flag of “1” at the first time t 1 . 
     The debugging information generator  112  may decode the data signal DQ stored in the second page setup period. The debugging information generator  112  may determine that a stored third command C 3  (e.g., “80h”) is matched with a preset data input command value (e.g., “80h”) corresponding to page setup. The debugging information generator  112  may determine that a stored fourth command C 4  (e.g., “11h”) is not matched with a preset confirm command value (e.g., “10h”) corresponding to page setup. As such, the debugging information generator  112  may determine that the command CMD of the data signal DQ input during the second page setup period is invalid. 
     The debugging information generator  112  may determine that sixth to tenth addresses A 6  to A 10  stored during the second setup period are valid. Even though the sixth to tenth addresses A 6  to A 10  stored during the second setup period are valid, since the fourth command C 4  of the third and fourth commands C 3  and C 4  is invalid, the debugging information generator  112  may store a command/address validity flag of “0” at the second time t 2 . 
     The debugging information register  113  may accumulate and store the command/address validity flags. In the case where the debugging support circuit  110  receives the debugging information request DIR, the debugging information register  113  may output the accumulated command/address validity flags as the debugging information DBI. The debugging information register  113  may output values of the following table  3  as the third debugging information DBI[ 3 ]. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                 MODE 
                 Debugging Information (DBI) Output 
               
               
                   
                   
               
             
            
               
                   
                 MODE [3] 
                 [1], [0] 
               
               
                   
                   
               
            
           
         
       
     
       FIG. 12  illustrates a flowchart of an operation method in which a debugging support circuit of  FIG. 4  provides fourth debugging information. Referring to  FIGS. 4 and 12 , in operation S 151 , the debugging support circuit  110  receives an input signal. In operation S 152 , the debugging support circuit  110  stores the command CMD and the address ADDR. In operation S 153 , the debugging support circuit  110  decodes the command CMD and the address ADDR to determine validities. The debugging support circuit  110  may determine the validities of the command CMD and the address ADDR on the basis of a preset value of the command CMD and a preset range of the address ADDR. 
     In operation S 154 , the debugging support circuit  110  calculates or counts the number of valid commands and addresses based on the determination result. In an embodiment, the debugging support circuit  110  may determine the validity of each signal (e.g., a command signal or an address signal) included in the data signal DQ of one operation unit (i.e., a page setup period), and may calculate the number of valid commands and addresses (i.e., a sum of the number of valid commands and the number of valid addresses) based on the determination result. The debugging information register  110  may accumulate and store the number of valid commands and addresses thus calculated. 
     In operation S 155 , the debugging support circuit  110  receives the debugging information request DIR. In operation S 156 , the debugging support circuit  110  outputs the number of valid commands and addresses as the fourth debugging information DB[ 4 ] in response to the debugging information request DIR. 
       FIG. 13  illustrates a timing diagram of an operation of providing fourth debugging information. Referring to  FIGS. 4, 11, and 13 , the validity of the data signal DQ stored in a first page setup period and a second page setup period may be determined through the method described with reference to  FIG. 11 . 
     During the first page setup period, the debugging information generator  112  may decode the stored first and second commands C 1  and C 2  (e.g., “80h” and “10h”) and the stored first to fifth addresses A 1  to A 5  (e.g., “01”, “101”, “03”, “105”, and “05”) and may compare each of the decoded results with a preset value or range. The debugging information generator  112  may determine that each of the first and second commands C 1  and C 2  are matched with a corresponding one of preset command values (e.g., “80h” and “10h”) corresponding to the page setup operations. The debugging information generator  112  may determine that some addresses A 2  and A 4  of the first to fifth addresses A 1  to A 5  exceed a preset range (e.g., “01” to “99”). As such, the debugging information generator  112  may determine the number of valid commands and addresses during the first page setup period as “5” at a first time t 1 . 
     During the second page setup period, the debugging information generator  112  may decode the stored third and fourth commands C 3  and C 4  (e.g., “80h” and “10h”) and the stored sixth to tenth addresses A 6  to A 10  (e.g., “06”, “07”, “08”, “09”, and “10”) and may compare each of the decoded results with a corresponding preset value or range. The debugging information generator  112  may determine that each of the third and fourth commands C 3  and C 4  and the sixth to tenth addresses A 6  to A 10  are matched with the corresponding one of the preset values or ranges. As such, the debugging information generator  112  may determine the number of valid commands and addresses during the second page setup period as “7” at a second time t 2 . The debugging information register  113  may store “12” as the number of valid commands and addresses accumulated. 
     In the case where the debugging support circuit  110  receives the debugging information request DIR, the debugging information register  113  may output the number of valid commands/addresses thus stored as the debugging information DBI. The debugging information register  113  may output values of the following table  4  as the fourth debugging information DBI[ 4 ]. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 4 
               
               
                   
                   
               
               
                   
                 MODE 
                 Debugging Information (DBI) Output 
               
               
                   
                   
               
             
            
               
                   
                 MODE [4] 
                 [12] 
               
               
                   
                   
               
            
           
         
       
     
       FIG. 14  illustrates a flowchart of an operation method in which a debugging support circuit of  FIG. 4  provides fifth debugging information. Referring to  FIGS. 4 and 14 , in operation S 161 , the debugging support circuit  110  receives an input signal. In operation S 162 , the debugging support circuit  110  stores the command CMD. In operation S 163 , the debugging support circuit  110  decodes the command CMD to determine the validity. The debugging support circuit  110  may compare a value indicated by the command CMD with a preset value to determine the validity. In operation S 164 , the debugging support circuit  110  calculates the number of operations based on the determination result. In an embodiment, the debugging support circuit  110  may calculate the number of operations based on the validity of the command CMD included in the data signal DQ indicating one operation unit. The debugging support circuit  110  may calculate the number of operations for each type of an operation that the command CMD indicates. 
     In operation S 165 , the debugging support circuit  110  receives the debugging information request DIR. In operation S 166 , the debugging support circuit  110  outputs the number of operations as the fifth debugging information DB[ 5 ] in response to the debugging information request DIR. 
       FIG. 15  illustrates a timing diagram of an operation of providing fifth debugging information. Referring to  FIGS. 4, 11, and 15 , the validity of the data signal DQ stored in a first page setup period (i.e., one operation unit) and a second page setup period (i.e., another operation unit) may be determined through the method described with reference to  FIG. 11 . 
     During the first page setup period, the debugging information generator  112  may decode the first and second commands C 1  and C 2  (e.g., “80h” and “10h”) stored. The debugging information generator  112  may determine that the first and second commands C 1  and C 2  are respectively matched with preset command values (e.g., “80h” and “10h”) corresponding to the page setup operation. As such, the debugging information generator  112  may determine the number of operations as “1” at a first time t 1 . 
     During the second page setup period, the debugging information generator  112  may decode the third and fourth commands C 3  and C 4  (e.g., “80h” and “10h”) stored. The debugging information generator  112  may determine that the third and fourth commands C 3  and C 4  are respectively matched with preset command values (e.g., “80h” and “10h”) corresponding to the page setup operation. As such, the debugging information generator  112  may determine the number of operations as “2” at a second time t 2 . 
     The debugging information generator  112  may calculate or count the number of operations associated with the page setup operation so as to be distinguished from the number of other operations. 
     The debugging information register  113  may store the number of operations thus calculated. In an embodiment, the debugging information register  113  may store the number of operations for each type of operation. In the case where the debugging support circuit  110  receives the debugging information request DIR, the debugging information register  113  may output the number of operations thus stored as the debugging information DBI. The debugging information register  113  may output values of the following table  5  as the fifth debugging information DBI[ 5 ]. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 5 
               
               
                   
                   
               
               
                   
                 MODE 
                 Debugging Information (DBI) Output 
               
               
                   
                   
               
             
            
               
                   
                 MODE [5] 
                 [2] 
               
               
                   
                   
               
            
           
         
       
     
       FIG. 16  illustrates a flowchart of an operation method in which a debugging support circuit of  FIG. 4  provides sixth debugging information. Referring to  FIGS. 4 and 16 , in operation S 171 , the debugging support circuit  110  receives an input signal. In operation S 172 , the debugging support circuit  110  detects clock activation times. For example, the debugging support circuit  110  may detect rising edges of the write enable signal WE/ as clock activation times. In operation S 173 , the debugging support circuit  110  stores input signals input through different pins at the clock activation times. In operation S 174 , the debugging support circuit  110  decodes the input signals to determine the validity of combinations of the input signals at the respective clock activation times. The debugging support circuit  110  may compare a combination of values indicated by the input signals at the clock activation times with a combination of preset signal values, and may determine the validity of the combinations based on the comparison results. In operation S 175 , input signal combination flags are calculated or determined based on the determination results. The debugging support circuit  110  may accumulate and store the input signal combination flags thus calculated. 
     In operation S 176 , the debugging support circuit  110  receives the debugging information request DIR. In operation S 177 , the debugging support circuit  110  outputs the accumulated input signal combination flags as the sixth debugging information DB [ 6 ] in response to the debugging information request DIR. 
       FIG. 17  illustrates a timing diagram of an operation of providing sixth debugging information. Referring to  FIGS. 4 and 17 , the signal storage circuit  111  may detect clock activation times from an input signal. For example, the storage circuit  111  may detect rising edges of the write enable signal WE/at first through seventh times t 1  to t 7  as clock activation times. The signal storage circuit  111  may store input signals respectively input through different pins at the respective detected clock activation times. The signal storage circuit  111  may respectively store input signals at a first time t 1  to a seventh time t 7  when the rising edges of the write enable signal WE/ are detected. For example, the signal storage circuit  111  may store input signals corresponding to the command latch enable signal CLE, the address latch enable signal ALE, and others of the control signal CTRL and the data signal DQ at the first time t 1  as a first combination of input signals. For example, the signal storage circuit  111  may store input signals corresponding to the command latch enable signal CLE, the address latch enable signal ALE, and others of the control signal CTRL and the data signal DQ at the second time t 2  as a second combination of input signals. The signal storage circuit  111  may similarly store respective combinations of the input signals at each of the third time t 3  to the seventh time t 7 . 
     The debugging information generator  112  may determine the validity of the combinations of the input signals stored at each of the first time t 1  to the seventh time t 7 . The debugging information generator  112  may compare the combinations of the input signals stored at each of the first time t 1  to the seventh time t 7  with a combination of preset input signals and may determine the validity of the combinations of the input signals based on the comparison results. The debugging information generator  112  may compare a combination of the input signals stored at the first time t 1 , a combination of the input signals stored at the second time t 2 , a combination of the input signals stored at the fifth time t 5 , a combination of the input signals stored at the sixth time t 6 , and a combination of the input signals stored at the seventh time t 7  with a combination of preset input signals, and may determine the validity of the combinations of the input signals at these times based on the comparison results. The debugging information register  113  may generate input signal combination flags of “1” at the first time t 1 , the second time t 2 , the fifth time t 5 , the sixth time t 6 , and the seventh time t 7 , respectively. 
     For example, in the case that both the command latch enable signal CLE and the address latch enable signal ALE are at a high level at the third time t 3  and the fourth time t 4 , the debugging information generator  112  may determine that the combination of the input signals stored at the third time t 3  and the combination of the input signals stored at the fourth time t 4  are invalid, as a result of comparing the combinations of the input signals with a combination of preset input signals. The debugging information register  113  may generate input signal combination flags of “0” at the third time t 3  and the fourth time t 4 , respectively. 
     In the case where the debugging support circuit  110  receives the debugging information request DIR, the debugging information register  113  may output the stored input signal combination flags as the debugging information DBI. The debugging information register  113  may output values of the following table  6  as the sixth debugging information DBI[ 6 ]. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 6 
               
               
                   
                   
               
               
                   
                 MODE 
                 Debugging Information (DBI) Output 
               
               
                   
                   
               
             
            
               
                   
                 MODE [6] 
                 [1], [1], [0], [0], [1], [1], [1] 
               
               
                   
                   
               
            
           
         
       
     
       FIG. 18  illustrates a view of a storage device according to another embodiment of the inventive concepts. Referring to  FIG. 18 , storage device  20  includes a nonvolatile memory package  100   a  and a memory controller  200   a . The nonvolatile memory package  100   a  includes a first nonvolatile memory device NVM 1  and a second nonvolatile memory device NVM 2 . The first nonvolatile memory device NVM 1  and the second nonvolatile memory device NVM 2  may be connected with the memory controller  200   a  through different channels CH 1  and CH 2 . 
     The first nonvolatile memory device NVM 1  includes a first debugging support circuit  110   a _ 1 , and the second nonvolatile memory device NVM 2  includes a second debugging support circuit  110   a _ 2 . As described with reference to  FIGS. 1 to 17 , each of the first debugging support circuit  110   a _ 1  and the second debugging support circuit  110   a _ 2  may generate debugging information DBI from an input signal and may output the generated debugging information DBI in response to a debugging information request DIR. Accordingly, a detailed description associated with the first and second debugging support circuit  110   a _ 1  and  110   a _ 2  is omitted. 
     In the case that a first debugging information request DIR 1  is provided from the memory controller  200   a  through the first channel CH 1 , the first debugging support circuit  110   a _ 1  may output first debugging information DBI 1  in response to the first debugging information request DIR 1 . In the case that a second debugging information request DIR 2  is provided from the memory controller  200   a  through the second channel CH 2 , the second debugging support circuit  110   a _ 2  may output second debugging information DBI 2  in response to the second debugging information request DIR 2 . 
     That is, the storage device  20  according to an embodiment of the inventive concepts may include the plurality of nonvolatile memory devices NVM 1  and NVM 2 , and the nonvolatile memory devices NVM 1  and NVM 2  may include the debugging support circuits  110   a _ 1  and  110   a _ 2 , respectively. The debugging support circuits  110   a _ 1  and  110   a _ 2  may generate the pieces of debugging information DBI respectively associated with the nonvolatile memory devices NVM 1  and NVM 2 , and the pieces of debugging information DBI may be provided to a host (not illustrated) through the memory controller  200   a.    
       FIG. 19  illustrates a view of a storage device according to a still further embodiment of the inventive concepts. Referring to  FIG. 19 , a storage device  30  includes a nonvolatile memory package  100   b  and a memory controller  200   b . The nonvolatile memory package  100   b  includes a first nonvolatile memory device NVM 1 , a second nonvolatile memory device NVM 2 , and an interface chip (FBI)  120   b.    
     The interface chip  120   b  may be connected with the memory controller  200   b  through a channel CH 1  and may be connected with the nonvolatile memory devices NVM 1  and NVM 2  through a plurality of internal channels ICH 1  and ICH 2 . The interface chip  120   b  may transmit signals input through the channel CH 1  to one of the nonvolatile memory devices NVM 1  and NVM 2  through one of the internal channels ICH 1  and ICH 2 . The interface chip  120   b  may receive signals provided from the nonvolatile memory devices NVM 1  and NVM 2  through the internal channels ICH 1  and ICH 2  and may transmit the received signals to the memory controller  200   b  through the channel CH 1 . 
     The interface chip  120   b  may include a debugging support circuit  121   b . As described with reference to  FIGS. 1 to 17 , the debugging support circuit  121   b  may generate debugging information DBI from an input signal and may output the generated debugging information DBI in response to a debugging information request DIR. Accordingly, a detailed description associated with the debugging support circuit  121   b  is omitted. 
     The debugging support circuit  121   b  may generate the debugging information DBI associated with the first nonvolatile memory device NVM 1  from signals provided to the first nonvolatile memory device NVM 1  through the channel CH 1 . Upon receiving the debugging information request DIR for the first nonvolatile memory device NVM 1 , the debugging support circuit  121   b  may output the debugging information DBI associated with the first nonvolatile memory device NVM 1 . 
     The debugging support circuit  121   b  may generate the debugging information DBI associated with the second nonvolatile memory device NVM 2  from signals provided to the second nonvolatile memory device NVM 2  through the channel CH 1 . Upon receiving the debugging information request DIR for the second nonvolatile memory device NVM 2 , the debugging support circuit  121   b  may output the debugging information DBI associated with the second nonvolatile memory device NVM 2 . 
     Accordingly, the storage device  30  according to an embodiment of the inventive concepts may output the debugging information DBI associated with the nonvolatile memory devices NVM 1  and NVM 2  using the one debugging support circuit  121   b.    
     According to an embodiment of the inventive concepts, the debugging support circuit  121   b  included in the interface chip  120   b  may generate debugging information from signals provided through the channel CH 1 , the first internal channel ICH 1 , or the second internal channel ICH 2  and may output the generated debugging information. 
       FIG. 20  illustrates a block diagram of a solid state drive (SSD) system to which a nonvolatile memory device according to the inventive concepts is applied. Referring to  FIG. 20 , an SSD system  1000  includes a host  1100  and an SSD  1200 . 
     The SSD  1200  exchanges signals SIG with the host  1100  through a signal connector  1201  and is supplied with power PWR through a power connector  1202 . The SSD  1200  includes an SSD controller  1210 , a plurality of flash memory units  1221  to  122   n , an auxiliary power supply  1230 , and a buffer memory  1240 . 
     The SSD controller  1210  may control the flash memory units  1221  to  122   n  in response to the signal SIG from the host  1100 . The flash memory units  1221  to  122   n  may operate under control of the SSD controller  1210 . The auxiliary power supply  1230  is connected with the host  1100  through the power connector  1202 . The auxiliary power supply  1230  may be charged by the power PWR from the host  1100 . When the power PWR is not smoothly supplied from the host  1100 , the auxiliary power supply  1230  may power the SSD system  1200 . The buffer memory  1240  operates as a buffer memory of the SSD  1200 . 
     In an embodiment, each of the flash memory units  1221  to  122   n  may include a debugging support circuit described with reference to  FIGS. 1 to 20 . The debugging support circuit may be included in a nonvolatile memory device, which is included in each of the flash memories  1221  to  122   n . Alternatively, the debugging support circuit may be included in an interface chip included in each of the flash memory units  1221  to  122   n . The SSD controller  1210  may receive a debugging information request from the host  1100  and may transmit the debugging information request to each of the flash memory units  1221  to  122   n . The debugging support circuit(s) may generate debugging information associated with a nonvolatile memory devices and may output the generated debugging information to the SSD controller  1210 . The host  1100  may determine whether a problem arises from an interface between the SSD controller and the flash memory units  1221  and  122   n , based on the debugging information received from the SSD controller  1210 . 
     According to the above-described embodiments of the inventive concepts, the nonvolatile memory device may generate debugging information from an input signal and may provide the generated debugging information to the host. Accordingly, even though a memory controller and a nonvolatile memory device are combined to form one set or device, a host may easily determine whether a problem arises from an interface between the memory controller and the nonvolatile memory device. 
     According to the inventive concepts, a nonvolatile memory device may generate debugging information based on an input signal provided from a memory controller and may output the generated debugging information. Accordingly, a nonvolatile memory device and an operation method thereof, which are capable of detecting a failure cause of a storage device associated with the nonvolatile memory device, are provided. 
     While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concepts as set forth in the following claims.