Patent Publication Number: US-2023155580-A1

Title: Pre-driver circuit and driver device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority of China application No. 202111346394.2, filed on Nov. 15, 2021, which is incorporated by reference in its entirety. 
     TECHNICAL FIELD 
     The present application relates to a pre-driver circuit, particularly to a pre-driver circuit capable of providing a low swing signal for driving the main driver circuit. 
     BACKGROUND 
     Since the power driver circuit is often used to control a larger voltage or current output, in order to effectively and quickly control the power driver circuit, a pre-driver circuit is often used to generate a control signal to control the power driver circuit. In the prior art, the pre-driver circuit is often implemented with inverters. However, the output of the inverter is generally in a full swing between its power supply voltage and the ground voltage, thereby causing higher instability to the system at the moment when the signal changes. 
     For example, if the pre-driver circuit and the power driver circuit use the same power supply voltage and the same ground voltage, then during the process when the input signal of the inverter changes, and the inverter changes the pre-driving signal in a full swing manner, the pre-driver circuit and the power driver circuit may generate a leakage current, and cause noise in the power supply voltage or ground voltage, thereby affecting the stability of the system. Therefore, how to control the power driver circuit and maintain the stability of the system has become an issue to be solved. 
     SUMMARY OF THE INVENTION 
     One embodiment of the present disclosure discloses a pre-driver circuit configured to provide a pre-driving signal to drive a main driver circuit. The pre-driver circuit includes a first transistor, a second transistor, and a resistive component. The first transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor is coupled to a first voltage, the second terminal of the first transistor is configured to output the pre-driving signal, and the control terminal of the first transistor is configured to receive a first control signal. The second transistor has a first terminal, a second terminal and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor, the second terminal of the second transistor is coupled to a second voltage, and the control terminal of the second transistor is configured to receive the first control signal. The resistive component has a first terminal and a second terminal, wherein the first terminal of the resistive component is coupled to the first terminal of the second transistor is, and the second terminal of the resistive component is coupled to the second terminal of the second transistor. One of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor. 
     Another embodiment of the present disclosure discloses a driving device. The driving device includes a first pre-driver circuit and a main driver circuit. The pre-driver circuit includes a first transistor, a second transistor, and a resistive component. The first transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor is coupled to a first voltage, the second terminal of the first transistor is configured to output the first pre-driving signal, and the control terminal of the first transistor is configured to receive a first control signal. The second transistor has a first terminal, a second terminal and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor, the second terminal of the second transistor is coupled to a second voltage, and the control terminal of the second transistor is configured to receive the first control signal. The first resistive component has a first terminal and a second terminal, wherein the first terminal of the first resistive component is coupled to the first terminal of the second transistor, and the second terminal of the first resistive component is coupled to the second terminal of the second transistor. The main driver circuit includes a third transistor having a first terminal, a second terminal and a control terminal. The first terminal of the third transistor is configured to receive a power supply, the second terminal of the third transistor is configured to output a first output signal, and the control terminal of the third transistor is configured to receive the first pre-driving signal. One of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor. Since the pre-driver circuits and driving devices can generate a signal having a smaller voltage swing according to the control signal to drive the main driver circuit, thereby reducing the current ripple generated by the pre-driver circuit, which in turn reduces the situation that the system voltage swings rigorously. Furthermore, since the voltage swing of the pre-driving signal is smaller, the time required to charge or discharge the gate capacitor of the main driver circuit is also reduced, thereby increasing the on/off speed of the main driver circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic diagram illustrating a driving device according to one embodiment of the present disclosure. 
         FIG.  2    is an equivalent circuit of the first pre-driver circuit in  FIG.  1    when a first control signal is at a logic low level. 
         FIG.  3    is a schematic diagram illustrating a driving device according to another embodiment of the present disclosure. 
         FIG.  4    is a schematic diagram illustrating a driving device according to another embodiment of the present disclosure. 
         FIG.  5    is an equivalent circuit of the third pre-driver circuit in  FIG.  4    when a first control signal is at a logic high level 
         FIG.  6    is a schematic diagram illustrating a driving device according to another embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a schematic diagram illustrating a driving device  100  according to one embodiment of the present disclosure. The driving device  100  includes a first pre-driver circuit  110  and a main driver circuit  120 . In the present embodiment, the first pre-driver circuit  110  can receive a first control signal SIG C1 , and can generate a first pre-driving signal SIG PD1  having a smaller signal swing to drive the main driver circuit  120  according to the first control signal SIG C1 . Since the first pre-driving signal SIG PD1  has a smaller signal swing, ripples of currents generated by the first pre-driver circuit  110  is also smaller, thereby increasing the stability of the system voltage. 
     In  FIG.  1   , the first pre-driver circuit  110  includes a first transistor M 1 , a second transistor M 2  and a first resistive component RE 1 . The first transistor M 1  has a first terminal, a second terminal and a control terminal; the first terminal of the first transistor M 1  can be coupled to a first voltage V 1 , the second terminal of the first transistor M 1  can output the first pre-driving signal SIG PD1 , and the control terminal of the first transistor M 1  can receive the first control signal SIG C1 . The second transistor M 2  has a first terminal, a second terminal and a control terminal; the first terminal of the second transistor M 2  can be coupled to the second terminal of the first transistor M 1 , the second terminal of the second transistor M 2  can be coupled to a second voltage V 2 , and the control terminal of the second transistor M 2  can receive the first control signal SIG C1 . The first resistive component RE 1  has a first terminal and a second terminal; the first terminal of the first resistive component RE 1  can be coupled to the first terminal of the second transistor M 2 , and the second terminal of the first resistive component RE 1  can be coupled to the second terminal of the second transistor M 2 . Furthermore, the first voltage V 1  can be higher than the second voltage V 2 ; for example, the first voltage V 1  can be the operating voltage of the system, and the second voltage V 2  can be the ground voltage. 
     The main driver circuit  120  includes the third transistor M 3 ; the third transistor M 3  has a first terminal, a second terminal and a control terminal. The first terminal of the third transistor M 3  can receive the power supply P 1 . The second terminal of the third transistor M 3  can output the first output signal SIG O1 , and the control terminal of the third transistor M 3  can receive the first pre-driving signal SIG PD1 . In the present embodiment, the driving device  100  can further include a first current source CS 1 , wherein the first current source CS 1  can be coupled to the first terminal of the third transistor M 3  and can be configured to provide a power supply P 1 . In such case, the driving device  100  can correspondingly output the first output signal SIG O1  according to the voltage level of the first control signal SIG C1 , and the first output signal SIG O1  outputted by the driving device  100  is substantially the power supply P 1  provided by the first current source CS 1 . 
     In the present embodiment, the first transistor M 1  and the third transistor M 3  can be P-type transistors, and the second transistor M 3  can be an N-type transistor. In such case, when the first control signal SIG C1  is at a logic high level, the first transistor M 1  will be turned off, and the second transistor M 2  is turned on; at this time, the voltage of the first pre-driving signal SIG PD1  equals substantially to the second voltage V 2 , so that the third transistor M 3  is turned on. 
     In contrast, when the first control signal SIG C1  is at a logic low level, the first transistor M 1  is turned on, and the second transistor M 2  is turned off.  FIG.  2    illustrates an equivalent circuit of the first pre-driver circuit  110  when the first control signal SIG C1  is at a logic low level. In  FIG.  2   , the voltage of the first pre-driving signal SIG PD1  is a divisional voltage VD 1  provided by the first resistive component RE 1  and the first transistor M 1 , and the divisional voltage VD 1  can be expressed as Equation (1). 
     
       
         
           
             
               
                 
                   
                     VD 
                     ⁢ 
                     1 
                   
                   = 
                   
                     
                       
                         R 
                         ⁢ 
                         1 
                       
                       
                         
                           R 
                           ⁢ 
                           1 
                         
                         + 
                         
                           RON 
                           
                             M 
                             ⁢ 
                             1 
                           
                         
                       
                     
                     ⁢ 
                     
                       ( 
                       
                         
                           V 
                           ⁢ 
                           1 
                         
                         - 
                         
                           V 
                           ⁢ 
                           2 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                       
                   
                     ( 
                     1 
                     ) 
                   
                 
               
             
           
         
       
     
     In Equation (1), R 1  is the resistance of the first resistive component RE 1 , and RON M1  is the on-resistance of the first transistor M 1 . In the present embodiment, the resistance R 1  of the first resistive component RE 1  is higher than the on-resistance RON M1  of the first transistor M 1 . By selecting the resistance R 1  of the first resistive component RE 1  appropriately, it is feasible to make the divisional voltage VD 1  higher than the voltage at the first terminal of the third transistor M 3  minus a threshold voltage of the third transistor M 3 , thereby turning off the third transistor M 3 . For example, in  FIG.  1   , the first resistive component RE 1  may include a variable resistor, and hence, a user may adjust the resistance R 1  of the first resistive component RE 1  depending on his/her needs. However, the present disclosure is not limited thereto, in some embodiments, when a user already knows the appropriate resistance R 1 , he/she can also use an invariable resistor having a corresponding resistance to implement the first resistive component RE 1 . 
     In the present embodiment, a logic high level of the first control signal SIG C1  may, for example, equal to the first voltage V 1 , and a logic low level of the first control signal SIG C1  may, for example, equal to the second voltage V 2 . In other words, the voltage swing of the first control signal SIG C1  is the difference between the first voltage V 1  and the second voltage V 2 . In contrast, the voltage swing of the first pre-driving signal SIG PD1  is the difference between the divisional voltage VD 1  and the second voltage V 2 ; i.e., the voltage drop of the two terminals of the first resistive component RE 1 . As shown in Equation (1), the divisional voltage VD 1  is lower than the difference between the first voltage V 1  and the second voltage V 2 , and hence, the voltage swing of first pre-driving signal SIG PD1  can be lower than the voltage swing of the first control signal SIG C1 . 
     In other words, the main driver circuit  120  may use the first pre-driving signal SIG PD1  having a smaller voltage swing to control the output of the power supply P 1  so as to reduce the current ripples generated by the first pre-driver circuit  110 , thereby reducing the situation that the first voltage V 1  and the second voltage V 2  swing rigorously. Furthermore, since the voltage swing of the first pre-driving signal SIG PD1  is smaller, the time required to charge or discharge the gate capacitor of the third transistor M 3  can also be shortened when the signal voltage changes, thereby increasing the on/off speed of the main driver circuit  120 . 
       FIG.  3    is a schematic diagram illustrating a driving device  200  according to another embodiment of the present disclosure. The driving device  200  and the driving device  100  of  FIG.  1    have similar structures and may operate according to similar principles; however, in the driving device  200 , the main driver circuit  220  can output two output signals: the first output signal SIG O1  and the second output signal SIG O2 . The main driver circuit  220  can include a third transistor M 3  and a fourth transistor M 4 ; the third transistor M 3  and the fourth transistor M 4  may respectively receive a first pre-driving signal SIG PD1  generated by the first pre-driver circuit  210 A and a second pre-driving signal SIG PD2  generated by the second pre-driver circuit  210 B. As shown in  FIG.  3   , the fourth transistor M 4  has a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth transistor M 4  can receive the power supply P 1 , the second terminal of the fourth transistor M 4  can output the second output signal SIG O2 , and the control terminal of the fourth transistor M 4  can receive a second pre-driving signal SIG PD2 . 
     In the present embodiment, the first pre-driver circuit  210 A may generate the first pre-driving signal SIG PD1  according to a first control signal SIG C1 , and the second pre-driver circuit  210 B may generate second pre-driving signal SIG PD2  according to a second control signal SIG C2 . Furthermore, the second pre-driver circuit  210 B may have a similar structure as the first pre-driver circuits  110  and  210 A, and may operate according to similar principles adopted by the first pre-driver circuit  110  and  210 A. As shown in  FIG.  3   , the second pre-driver circuit  210 B includes a fifth transistor M 5 , a sixth transistor M 6  and a second resistive component RE 2 . The fifth transistor M 5  has a first terminal, a second terminal and a control terminal, the first terminal of the fifth transistor M 5  can be coupled to the first voltage V 1 , the second terminal of the fifth transistor M 5  can output second pre-driving signal SIG PD2 , and the control terminal of the fifth transistor M 5  can receive the second control signal SIG C2 . In the present embodiment, the first control signal SIG C1  and the second control signal SIG C2  are complementary. 
     The sixth transistor M 6  has a first terminal, a second terminal and a control terminal, the first terminal of the sixth transistor M 6  can be coupled to the second terminal of the fifth transistor M 5 , the second terminal of the sixth transistor M 6  can be coupled to the second voltage V 2 , and the control terminal of the sixth transistor M 6  can receive the second control signal SIG C2 . The second resistive component RE 2  has a first terminal and a second terminal, the first terminal of the second resistive component RE 2  can be coupled to the first terminal of the sixth transistor M 6 , and the second terminal of the second resistive component RE 2  can be coupled to the second terminal of the sixth transistor M 6 . 
     In the present embodiment, the fourth transistor M 4  and the fifth transistor M 5  can be P-type transistors, and the sixth transistor M 6  can be an N-type transistor. In such case, when the second control signal SIG C2  is at a logic high level, the fifth transistor M 5  will be turned off, the sixth transistor M 6  is turned on; at this time, the voltage of the second pre-driving signal SIG PD2  equals substantially to the second voltage V 2 , so that the fourth transistor M 4  is turned on, and the main driver circuit  220  outputs the second output signal SIG O2  through the second output terminal OUT 2 . Since the first control signal SIG C1  and the second control signal SIG C2  are complementary, when the second control signal SIG C2  is at the logic high level, the first control signal SIG C1  will be at the logic low level, and hence, the third transistor M 3  will be turned off, and the main driver circuit  220  will stop outputting the first output signal SIG O1  via the first output terminal OUT 1 . 
     In contrast, when the second control signal SIG C2  is at the logic low level, the sixth transistor M 6  will be turned off, and the fifth transistor M 5  is turned on; at this time, the voltage of the second pre-driving signal SIG PD2  equals substantially to the divisional voltage provided by the fifth transistor M 5  and the second resistive component RE 2 . By selecting the resistance of the second resistive component RE 2  appropriately, the voltage of the second pre-driving signal SIG PD2  can be higher than the voltage at the first terminal of the fourth transistor M 4  minus the threshold voltage of the fourth transistor M 4 ; therefore, the fourth transistor M 4  is turned off, and the main driver circuit  220  will stop outputting the second output signal SIG O2  via the second output terminal OUT 2 . Since the first control signal SIG C1  and the second control signal SIG C2  are complementary, when the second control signal SIG C2  is at a logic low level, the first control signal SIG C1  will be at a logic high level, the third transistor M 3  will be turned on, and the main driver circuit  220  can output the first output signal SIG O1  via the first output terminal OUT 1 . 
       FIG.  4    is a schematic diagram illustrating a driving device  300  according to another embodiment of the present disclosure. The driving device  300  and the driving device  200  have similar structures and may operate according to similar principles. The driving device  300  may include a first pre-driver circuit  310 A, a second pre-driver circuit  310 B, a third pre-driver circuit  310 C, a fourth pre-driver circuit  310 D, and a main driver circuit  320 . In the present embodiment, the main driver circuit  320  can include a third transistor M 3 , a fourth transistor M 4 , a seventh transistor M 7  and an eighth transistor M 8 , wherein the third transistor M 3 , the fourth transistor M 4 , the seventh transistor M 7  and the eighth transistor M 8  can respectively receive a first pre-driving signal SIG PD1  generated by the first pre-driver circuit  310 A, a second pre-driving signal SIG PD2  generated by the second pre-driver circuit  310 B, a third pre-driving signal SIG PD3  generated by the third pre-driver circuit  310 C and a fourth pre-driving signal SIG PD4  generated by the fourth pre-driver circuit  310 D. 
     As shown in  FIG.  4   , the seventh transistor M 7  has a first terminal, a second terminal and a control terminal, wherein the first terminal of the seventh transistor M 7  can be coupled to the second terminal of the third transistor M 3 , and the control terminal of the seventh transistor M 7  can receive the third pre-driving signal SIG PD3 . The eighth transistor M 8  has a first terminal, a second terminal and a control terminal, wherein the first terminal of the eighth transistor M 8  can be coupled to the second terminal of the fourth transistor M 4 , and the control terminal of the eighth transistor M 8  can receive the fourth pre-driving signal SIG PD4 . In the present embodiment, the driving device  300  can further include a second current source CS 2 . The second current source CS 2  can be coupled to the second terminal of the seventh transistor M 7  and the second terminal of the eighth transistor M 8 . In such case, the first current source CS 1  and the second current source CS 2  can generate currents having the same level, which can be used to provide the power supply P 1  together. 
     In the present embodiment, the first pre-driver circuit  310 A can generate the first pre-driving signal SIG PD1  according to the first control signal SIG C1 , the second pre-driver circuit  310 B can generate the second pre-driving signal SIG PD2  according to the second control signal SIG C2 , the third pre-driver circuit  310 C can generate the third pre-driving signal SIG PD3  according to the first control signal SIG C1 , the fourth pre-driver circuit  310 D can generate the fourth pre-driving signal SIG PD4  according to the second control signal SIG C2 . 
     As shown in  FIG.  4   , the third pre-driver circuit  310 C can include a ninth transistor M 9 , a tenth transistor M 10  and a third resistive component RE 3 . The ninth transistor M 9  has a first terminal, a second terminal and a control terminal, wherein the first terminal of the ninth transistor M 9  can be coupled to the first voltage V 1 , the second terminal of the ninth transistor M 9  can output the third pre-driving signal SIG PD3 , and the control terminal of the ninth transistor M 9  can receive the first control signal SIG C1 . The tenth transistor M 10  has a first terminal, a second terminal and a control terminal, wherein the first terminal of the tenth transistor M 10  can be coupled to the second terminal of the ninth transistor M 9 , the second terminal of the tenth transistor M 10  is coupled to the second voltage V 2 , and the control terminal of the tenth transistor M 10  can receive the first control signal SIG C1 . The third resistive component RE 3  has a first terminal and a second terminal, the first terminal of the third resistive component RE 3  can be coupled to the first terminal of the ninth transistor M 9 , and the second terminal of the third resistive component RE 3  can be coupled to the second terminal of the ninth transistor M 9 . 
     Furthermore, the fourth pre-driver circuit  310 D can include an eleventh transistor M 11 , a twelfth transistor M 12  and a fourth resistive component RE 4 . The eleventh transistor M 11  has a first terminal, a second terminal and a control terminal, wherein the first terminal of the eleventh transistor M 11  can be coupled to the first voltage V 1 , the second terminal of the eleventh transistor M 11  can output the fourth pre-driving signal SIG PD4 , and the control terminal of the eleventh transistor M 11  can receive the second control signal SIG C2 . The twelfth transistor M 12  has a first terminal, a second terminal and a control terminal, wherein the first terminal of the twelfth transistor M 12  can be coupled to the second terminal of the eleventh transistor M 11 , the second terminal of the twelfth transistor M 12  is coupled to the second voltage V 2 , and the control terminal of the twelfth transistor M 12  can receive the second control signal SIG C2 . The fourth resistive component RE 4  has a first terminal and a second terminal, wherein the first terminal of the fourth resistive component RE 4  can be coupled to the first terminal of the eleventh transistor M 11 , and the second terminal of the fourth resistive component RE 4  can be coupled to the second terminal of the eleventh transistor M 11 . 
     In the present embodiment, the ninth transistor M 9  and the eleventh transistor M 11  are both P-type transistors, and the seventh transistor M 7 , the eighth transistor M 8 , the tenth transistor M 10  and the twelfth transistor M 12  are all N-type transistors. In such case, when the first control signal SIG C1  is at the logic high level, the ninth transistor M 9  is turned off, the tenth transistor M 10  is turned on, and the voltage of the third pre-driving signal SIG PD3  equals substantially to a divisional voltage provided by the third resistive component RE 3  and the tenth transistor M 10 .  FIG.  5    illustrates the equivalent circuit of the third pre-driver circuit  310 C when the first control signal SIG C1  is at the logic high level. In  FIG.  5   , the voltage of the third pre-driving signal SIG PD3  is a divisional voltage VD 2  provided by the third resistive component RE 3  and the tenth transistor M 10 , and the divisional voltage VD 2  can be expressed by Equation (2). 
     
       
         
           
             
               
                 
                   
                     VD 
                     ⁢ 
                     2 
                   
                   = 
                   
                     
                       
                         RON 
                         
                           M 
                           ⁢ 
                           10 
                         
                       
                       
                         
                           R 
                           ⁢ 
                           3 
                         
                         + 
                         
                           RON 
                           
                             M 
                             ⁢ 
                             10 
                           
                         
                       
                     
                     ⁢ 
                     
                       ( 
                       
                         
                           V 
                           ⁢ 
                           1 
                         
                         - 
                         
                           V 
                           ⁢ 
                           2 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                       
                   
                     ( 
                     2 
                     ) 
                   
                 
               
             
           
         
       
     
     In Equation (2), R 3  is the resistance of the third resistive component RE 3 , and RON M10  is the on-resistance of the tenth transistor M 10 . In the present embodiment, the resistance R 3  of the third resistive component RE 3  is higher than the on-resistance RON M10  of the tenth transistor M 10 , and by selecting the appropriate the resistance R 3  of the third resistive component RE 3 , it is feasible to make the divisional voltage VD 2  lower than the sum of the voltage at the first terminal of the seventh transistor M 7  and the threshold voltage of the seventh transistor M 7 . In such case, when the first control signal SIG C1  is at the logic high level, the seventh transistor M 7  will be turned off. 
     Furthermore, when the first control signal SIG C1  is at the logic high level, the second control signal SIG C2  is at the logic low level; in such case, the eleventh transistor M 11  is turned on, and the twelfth transistor M 12  is turned off, and the voltage of the fourth pre-driving signal SIG PD4  equals substantially to the first voltage V 1 , so that the eighth transistor M 8  is turned on. Furthermore, according to the foregoing description regarding the embodiment of  FIG.  2   , when the first control signal SIG C1  is at the logic high level, the third transistor M 3  is turned on, and the fourth transistor M 4  is turned off. In other words, when the first control signal SIG C1  is at the logic high level, the third transistor M 3  and the eighth transistor M 8  of the driving device  300  are turned on, and the fourth transistor M 4  and the seventh transistor M 7  are turned off; hence, the current generated by the first current source CS 1  will pass through the third transistor M 3  and the first output terminal OUT 1  into a load circuit LD, and then passing through the second output terminal OUT 2  and the eighth transistor M 8  into the second current source CS 2 . At this time, the voltage of the first output terminal OUT 1  will be higher than the voltage of the second output terminal OUT 2 . 
     In contrast, when the first control signal SIG C1  is at the logic low level, the ninth transistor M 9  is turned on, the tenth transistor M 10  is turned off, and the voltage of the third pre-driving signal SIG PD3  equals substantially to the first voltage V 1 , so that the seventh transistor M 7  is turned on. In other words, the voltage swing of the third pre-driving signal SIG PD3  is the difference between the divisional voltage VD 2  and the first voltage V 1 , i.e., the voltage drop across the two terminals of the third resistive component RE 3 , and is lower than the voltage swing of the first control signal SIG C1 . 
     Furthermore, when the first control signal SIG C1  is at the logic low level, the second control signal SIG C2  is at the logic high level; at this time, the eleventh transistor M 11  is turned off, and the twelfth transistor M 12  is turned on, and the voltage of the fourth pre-driving signal SIG PD4  equals to a divisional voltage provided by the fourth resistive component RE 4  and the twelfth transistor M 12 . In the present embodiment, by selecting the resistance R 4  of the fourth resistive component RE 4  appropriately, it is feasible to make the voltage of the fourth pre-driving signal SIG PD4  lower than the sum of the voltage at the first terminal of the eighth transistor M 8  and the threshold voltage of the eighth transistor M 8 , so as to turn off the eighth transistor M 8 . 
     Furthermore, according to the foregoing description regarding the embodiment of  FIG.  3   , when the first control signal SIG C1  is at the logic low level, the third transistor M 3  is turned off, however, the fourth transistor M 4  is turned on. In other words, when the first control signal SIG C1  is at the logic low level, the fourth transistor M 4  and the seventh transistor M 7  of the driving device  300  are turned on, and the third transistor M 3  and the eighth transistor M 8  are turned off; hence, the current generated by the first current source CS 1  will pass through the fourth transistor M 4  and the second output terminal OUT 2  into the load circuit LD, and then passing through the first output terminal OUT 1  and the seventh transistor M 7  into the second current source CS 2 . In such case, the voltage of the second output terminal OUT 2  will be higher than the voltage of the first output terminal OUT 1 . In other words, the driving device  300  can be an H-type driving device, and can output currents in opposite directions between the first output terminal OUT 1  and the second output terminal OUT 2  according to the changes of the first control signal SIG C1  and the second control signal SIG C2 , and the first output signal SIG O1  and second output signal SIG O2  can be configured to be a pair of differential output signals. 
     In the present embodiment, the signal voltage swing of the first pre-driving signal SIG PD1 , the second pre-driving signal SIG PD2 , first pre-driving signal SIG PD3  and first pre-driving signal SIG PD4  can be lower than the signal voltage swing of the first control signal SIG C1  and the second control signal SIG C2 , and hence, the current ripples generated by the first pre-driver circuit  310 A, the second pre-driver circuit  310 B, the third pre-driver circuit  310 C and the fourth pre-driver circuit  310 D are smaller, thereby reducing the situation that the first voltage V 1  and the second voltage V 2  swing rigorously. Furthermore, since the voltage swing of the first pre-driving signal SIG PD1 , the second pre-driving signal SIG PD2 , first pre-driving signal SIG PD3  and first pre-driving signal SIG PD4  is smaller, when the voltage of the first control signal SIG C1  and the second control signal SIG C2  changes, the time required to charge or discharge the gate capacitor of the third transistor M 3 , the fourth transistor M 4 , the seventh transistor M 7  and the eighth transistor M 8  can also be shortened, thereby increasing the on/off speed of the main driver circuit  320 . 
     Although the power supply P 1  received from the driving device  100 ,  200  and  300  can be the current provided by the current source, the present disclosure is not limited thereto; in some embodiments, the driving device can also receive the voltage provided by a voltage source as the power supply.  FIG.  6    is a schematic diagram illustrating a driving device  400  according to another embodiment of the present disclosure. The driving device  400  and the driving device  300  have similar structures and are able to operate according to similar principles; however, in  FIG.  6   , the driving device  400  can include a first voltage source VS 1  instead of the current sources CS 1  and CS 2 . The first voltage source VS 1  can be coupled to the first terminal of the third transistor M 3  and the first terminal of the fourth transistor M 4 , and can output the voltage as the power supply P 1 . In the present embodiment, the voltage provided by the first voltage source VS 1  can be the first voltage V 1 . In such case, the first voltage source VS 1  can also be provided to the first voltage V 1  to the first pre-driver circuits  410 A,  410 B,  410 C and  410 D, and the main driver circuit  420  can output the first voltage V 1  through the first output terminal OUT 1  and output the second voltage V 2  through the second output terminal OUT 2  when the first control signal SIG C1  is at a logic high level, and output the second voltage V 2  through the first output terminal OUT 1  and output the first voltage V 1  through the second output terminal OUT 2 , when the second control signal SIG C2  is at a logic low level, according to the pre-driving signals SIG PD1 , SIG PD2 , SIG PD3  and SIG PD4  generated by the first pre-driver circuits  410 A,  410 B,  410 C and  410 D. In other words, the driving device  400  can output voltage signals of opposite phases between the first output terminal OUT 1  and the second output terminal OUT 2  according to the changes of the first control signal SIG C1  and the second control signal SIG C2 . 
     In summary, the pre-driver circuits and driving devices according to embodiments of the present disclosure can generate a signal having a smaller voltage swing according to the control signal to drive the main driver circuit, thereby reducing the current ripple generated by the pre-driver circuit, which in turn reduces the situation that the system voltage swings rigorously. Furthermore, since the voltage swing of the pre-driving signal is smaller, the time required to charge or discharge the gate capacitor of the main driver circuit is also reduced, thereby increasing the on/off speed of the main driver circuit.