Patent Publication Number: US-5892933-A

Title: Digital bus

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to an improved apparatus and method for attaching devices to a digital serial bus such as an I 2  C type of bus. 
     2. Description of the Related Art 
     Various types of digital serial busses have been known. One example of this type of bus is an I 2  C bus. These types of busses allow for low cost serial communication between electronic systems. However, as the speed of such buses are raised, various problems exist. For example, an I 2  C bus is limited in speed to the slowest device &#34;hanging&#34; on the bus. This is not a problem if the devices on the bus only need to send a very limited amount of data and/or this data is sent very infrequently. As the amount of data to be sent on the bus increases or the frequency at which devices are polled or send data increases or when a combination of these two situations occur, the limiting of the bus to the slowest device becomes problematical. 
     As an example using FIG. 1 as a reference, suppose a single I 2  C master 28 were used to connect to slave devices 40, 42, 44, and 46. If I 2  C slave device 40 could only operate at 10 kHz, the remaining I 2  C slave devices 42, 44 and 46 would be limited to that speed even if these devices might normally operate at 100 kHz. Either wait states would need to be added to the other I 2  C slave devices 42, 44 and 46 or some other method (for example, the master could drive the clock for the bus slower) would be required. This is an unacceptable slow down of the communication system. Further, the capacitive loading of the I 2  C bus becomes an issue as more devices or high capacitive devices (such as monitors) are added. Even if all the I 2  C slaves 40, 42, 44 and 46 normally have the same speed, if one of these devices has a high capacitive load, the speed on that segment would be slower. A further complication, well known to those skilled in the art, is that the termination of the I 2  C bus becomes problematical as well. 
     One approach that might be tried is shown in FIG. 2 where multiple I 2  C masters 22, 24 and 26 are employed. However, as I 2  C masters are relatively expensive devices, this type of segmentation is expensive. Further, the number of bus connections from the microcontroller (or microprocessor) 10 becomes cumbersome or is limited, which makes device coordination difficult. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the shortcoming and deficiencies noted above by providing a new way of interconnecting and controlling the connection of an I 2  C master on an I 2  C bus to I 2  C slave devices. Following the teachings of the present invention, multiple I 2  C slaves can be connected to one I 2  C master device without unduly capacitively loading the I 2  C bus. Further, according to the teachings of the present invention, a plurality of slave devices can be attached to an I 2  C bus master so that the most advantageous termination for each (or at least several) of the slave devices can be employed, and so that an I 2  C bus can be segmented to group like speed devices together, so as to maximize the total speed of the system. 
     In broad terms, the present invention provides a serial digital bus segmentation system including at least one serial digital bus master having a coupling to serial digital devices along a serial digital bus, and at least one switch, e.g., a bidirectional analog multiplexer, coupled to the serial digital bus master and having at least three connections, one for connecting to a master, and the other two for connecting to other devices. 
     Also, in broad terms, the present invention provides a method for attaching slave devices to a digital serial bus including the steps of segmenting the bus, and providing for connecting the bus segments to a bus master through a switch. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other advantages and novel features of the present invention can be understood and appreciated by reference to the following detailed description of the invention, taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is an example of a microcontrolled digital serial bus such as an I 2  C bus; 
     FIG. 2 is an example of a solution to the interconnection problem set forth in FIG. 1; and 
     FIG. 3 is a block diagram of one embodiment of this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings wherein like or similar elements are designated with identical reference numerals throughout the several views, and wherein the various elements are depicted in block form and, in particular, to FIG. 1, there is shown a microcontrolled digital serial bus. 
     As mentioned above, the circuit of FIG. 1 shows several devices on an I 2  C type of bus. It should be noted that although this invention is being described using an I 2  C bus, the use of the I 2  C bus is only an example. This unique arrangement could be used with other types of digital serial busses. However, the I 2  C bus particularly lends itself to the unique, unobvious solution set forth herein. 
     As can be seen looking at FIG. 1 and FIG. 2 the intuitive method of segmenting an I 2  C bus requires multiple I 2  C masters such as 22, 24 and 26. This approach makes sense, for example, if device 40 was a slow speed device, either by virtue of a high capacitive load or by virtue of a very slow clock speed or the like. In such a case, device 40 is advantageously placed on its own segment. As another example, if device 48 is especially &#34;talkative&#34; and needs to be polled on a rapid basis or if it sends long streams of data when polled, it makes sense to place it on its own segment also, as shown. Slave devices 42, 44 and 46 would operate on their segment of the I 2  C bus at the slowest speed of the three devices 42, 44, and 46. 
     The solution to the requirement of the multiple I 2  C masters 22, 24 and 26 in this invention can be seen in FIG. 3 where each of the I 2  C segments are coupled to a single I 2  C master 20 by way of a switch, e.g., an analog multiplexer 30. An analog multiplexer may be used even though the signals passing through the multiplexer are digital in nature as the multiplexer is a low capacitance/low impedance bidirectional analog multiplexer. A good example of this type of multiplexer is a HC4052. Alternatively, a digital multiplexer or any of a number of different &#34;switches&#34; could be used in embodiments of the present invention. 
     In operation, the controller 10, when wanting to communicate with, for example, the I 2  C slave device 40, would under software control send a signal to the analog multiplexer 30 over control line 60 to indicate that the analog multiplexer 30 should connect the I 2  C slave device 40 to the I 2  C bus master 20. It should be noted that the control line 60 may be made up of several lines so as to facilitate an easy switching of segments by the analog multiplexer 30. To communicate on the segment where slave devices 42, 44 and 46 are placed, a software controlled signal is sent from the microcontroller 10 to the analog multiplexer 30 so as to connect the desired segment to the I 2  C bus master 20, and the same would be true with respect to the segment for slave device 48. Further, as the speeds of the various segments may well be different, the same controller 10 can provide, at the same time as the switch command, a resetting of the appropriate speed to the I 2  C bus master 20. 
     Further, by having this type of segmentation, if different levels of termination or pull ups are needed on a given segment, this can be accomplished based upon the type of slave devices attached to each segment. For example, the segment connecting I 2  C slave 40 may need a stronger pullup than the segment supporting I 2  C slave devices 42, 43, and 46. 
     Obviously, numerous modifications and variations are possible in view of the teachings above. For example, the I 2  C bus may be, as noted above, a different type of serial digital bus. Further, the speeds of the devices may all be the same but a segmentation of the bus may be needed for load balancing purposes. Accordingly, the present invention is not limited by the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions, without departing from the spirit and scope of the invention as set forth and defined by the following claims.