Patent Publication Number: US-2015060899-A1

Title: Semiconductor light emitting device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-180045, filed on Aug. 30, 2013; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor light emitting device. 
     BACKGROUND 
     Conventionally, a method for manufacturing a semiconductor light emitting device has been proposed in which a semiconductor layer is grown by crystal growth on a wafer; electrodes are formed on the semiconductor layer; sealing with a resin body is performed; and subsequently, the wafer is removed. According to such a method, fine structural bodies that are formed on the wafer can be packaged as-is; and fine semiconductor light emitting devices can be efficiently manufactured. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a plan view showing a semiconductor light emitting device according to a first embodiment; and  FIG. 1B  is a cross-sectional view along line A-A′ shown in  FIG. 1A ; 
         FIG. 2A  shows a disposition of semiconductor layers of the semiconductor light emitting device according to the first embodiment; and  FIG. 2B  is a figure showing a connectional relationship between the semiconductor layers and interconnect layers; 
         FIGS. 3A and 3B  to  FIGS. 5A and 5B  show a method for manufacturing the semiconductor light emitting device according to the first embodiment; 
         FIG. 6  is a drawing in which  FIG. 5A  is superimposed onto  FIG. 2B ; 
         FIGS. 7A and 7B  to  FIGS. 10A and 10B  show the method for manufacturing the semiconductor light emitting device according to the first embodiment; 
         FIGS. 11A and 11B  are schematic cross-sectional views showing operations of the semiconductor light emitting device according to the first embodiment; 
         FIG. 12  is an xy chromaticity diagram showing colors of a light emitted by the semiconductor light emitting device according to the first embodiment; 
         FIGS. 13A and 13B  are schematic cross-sectional views showing operations of a semiconductor light emitting device according to a second embodiment; 
         FIG. 14  is an xy chromaticity diagram showing colors of a light emitted by the semiconductor light emitting device according to the second embodiment; 
         FIG. 15  is a schematic cross-sectional view showing an operation of a semiconductor light emitting device according to a third embodiment; 
         FIG. 16  is a schematic cross-sectional view showing an operation of a semiconductor light emitting device according to a forth embodiment; 
         FIG. 17  is a plan view showing a disposition of pillars of the semiconductor light emitting device according to a fifth embodiment; 
         FIG. 18  is a plan view showing a disposition of pillars of a semiconductor light emitting device according to a sixth embodiment; 
         FIG. 19  is a figure showing a connectional relationship between semiconductor layers and interconnect layers of the semiconductor light emitting device according to the sixth embodiment; 
         FIG. 20  is a plan view showing a disposition of pillars of a semiconductor light emitting device according to a seventh embodiment; 
         FIG. 21  is a plan view showing a disposition of pillars of a semiconductor light emitting device according to an eighth embodiment; and 
         FIG. 22  is a figure showing a connectional relationship between semiconductor layers and interconnect layers of the semiconductor light emitting device according to the eighth embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     A semiconductor light emitting device according to an embodiment includes a first semiconductor layer, a second semiconductor layer, a continuous insulating layer, a first fluorescer layer and a second fluorescer layer. The first semiconductor layer includes a first conductivity-type clad layer, an active layer, and a second conductivity-type clad layer stacked in the first semiconductor layer. The second semiconductor layer includes a first conductivity-type clad layer, an active layer, and a second conductivity-type clad layer stacked in the second semiconductor layer. The continuous insulating layer covers a side surface of the first semiconductor layer, a lower surface of the first semiconductor layer, a side surface of the second semiconductor layer, and a lower surface of the second semiconductor layer. The first fluorescer layer covers an upper surface of the first semiconductor layer. The second fluorescer layer covers an upper surface of the second semiconductor layer. 
     Embodiments of the invention will now be described with reference to the drawings. 
     First Embodiment 
     First, a first embodiment will be described. 
       FIG. 1A  is a plan view showing a semiconductor light emitting device according to the embodiment; and  FIG. 1B  is a cross-sectional view along line A-A′ shown in  FIG. 1A . 
       FIG. 2A  shows the disposition of semiconductor layers of the semiconductor light emitting device according to the embodiment; and  FIG. 2B  is a figure showing the connectional relationship between the semiconductor layers and the interconnect layers. 
     As shown in  FIGS. 1A and 1B , an insulating layer  11 , an insulating layer  12 , an insulating layer  13 , and a fluorescer layer  15  are stacked in this order in the semiconductor light emitting device  1  according to the embodiment. The fluorescer layer  15  is not shown for convenience of illustration in  FIG. 1A . For convenience of description hereinbelow, the insulating layer  11  side is called “down” and the fluorescer layer  15  side is called “up;” but such notation is independent of the direction of gravity. 
     The insulating layers  11  to  13  are formed of an insulating material. The insulating layer  11  is formed of, for example, an opaque resin material. The insulating layer  12  and the insulating layer  13  are formed of, for example, silicon oxide, silicon nitride, alumina, aluminum nitride, silicone polymer, polyimide, PBO, BCB or Parylene. Pillars  17   a  to  17   d  that are made of a conductive material such as, for example, copper (Cu), etc., are provided inside the insulating layer  11 . The pillars  17   a  to  17   d  have, for example, quadrilateral columnar configurations. The pillars  17   a  to  17   d  pierce the insulating layer  11  in the vertical direction such that the lower surfaces of the pillars  17   a  to  17   d  are exposed at the lower surface of the insulating layer  11 . In the specification, “covering” refers to both the state in which the covering object contacts the covered object and the state in which the covering object does not contact the covered object. 
     For example, two of each for vias  18   a  to  18   d  (referring to  FIG. 8A ) are provided inside the insulating layer  12 . The vias  18   a  to  18   d  are disposed in regions directly above the pillars  17   a  to  17   d , respectively, to pierce the insulating layer  12  in the vertical direction to be connected to the pillars  17   a  to  17   d , respectively. In the specification, “connecting” refers to being electrically connected. The insulating layer  12  covers the upper surfaces of the pillars  17   a  to  17   d . An insulating film  16  includes the insulating layer  11  and the insulating layer  12 . Accordingly, the insulating film  16  covers the side surfaces and upper surfaces of the pillars  17   a  to  17   d.    
     An interconnect layer  20  that is made of a conductive material such as, for example, copper, aluminum, nickel, gold, conductive paste, copper nano-paste, silver nano-paste or etc., is provided inside the upper portion of the insulating layer  12  and inside the lower portion of the insulating layer  13 . The lower portion of the interconnect layer  20  is positioned inside the upper portion of the insulating layer  12  and is formed in an interconnect configuration. The upper portion of the interconnect layer  20  is positioned inside the lower portion of the insulating layer  13  and is formed in a via configuration. The interconnect layer  20  is divided into multiple portions; and each portion is classified into one selected from interconnect layers  20   a  to  20   d . The interconnect layers  20   a  to  20   d  are respectively connected to the vias  18   a  to  18   d.    
     Multiple semiconductor layers  21  and multiple semiconductor layers  22  are provided to be separated from each other inside the upper portion of the insulating layer  13 . The semiconductor layers  21  and  22  have, for example, square plate configurations that are patterned into high mesas. As described below, the semiconductor layers  21  and  22  are formed by patterning one semiconductor layer to subdivide the one semiconductor layer into multiple portions; and the semiconductor layers  21  and  22  are LED (Light Emitting Diode) layers including, for example, indium gallium nitride (InGaN) that emit, for example, blue light. The lower surfaces and side surfaces of the semiconductor layers  21  and  22  are covered with the insulating layer  13 ; and the upper surfaces of the semiconductor layers  21  and  22  are exposed at the upper surface of the insulating layer  13 . The insulating layer  13  is a single continuous insulating layer covering the side surfaces and lower surfaces of all of the semiconductor layers  21  and the side surfaces and lower surfaces of all of the semiconductor layers  22  continuously. 
     As shown in  FIG. 1B , a p-type clad layer  21   p , an active layer  21   a , and an n-type clad layer  21   n  are stacked in order from below in the semiconductor layer  21 . At the four corners of the semiconductor layer  21 , the p-type clad layer  21   p  and the active layer  21   a  are removed; and the n-type clad layer  21   n  is exposed at the lower surface of the semiconductor layer  21 . In other words, the p-type clad layer  21   p  is patterned into a high mesa in a cross-shaped configuration as viewed from below. A p-side electrode  23   p  that has a cross-shaped configuration is provided on the lower surface of the p-type clad layer  21   p  to be connected to the p-type clad layer  21   p . N-side electrodes  23   n  that are rectangles are provided respectively on the exposed surfaces of the lower surface of the n-type clad layer  21   n  to be connected to the n-type clad layer  21   n.    
     Similarly, a p-type clad layer  22   p , an active layer  22   a , and an n-type clad layer  22   n  are stacked in order from below in the semiconductor layer  22 . At the four corners of the semiconductor layer  22 , the p-type clad layer  22   p  and the active layer  22   a  are removed; and the n-type clad layer  22   n  is exposed at the lower surface of the semiconductor layer  22 . A p-side electrode  24   p  that has a cross-shaped configuration is provided on the lower surface of the p-type clad layer  22   p  to be connected to the p-type clad layer  22   p ; and n-side electrodes  24   n  that are rectangles are provided respectively on the exposed surfaces of the lower surface of the n-type clad layer  22   n  to be connected to the n-type clad layer  22   n.    
     As shown in  FIG. 2A , when viewed from above, the semiconductor layers  21  are arranged in a staggered configuration; the semiconductor layers  22  are arranged in a staggered configuration; and the semiconductor layers  21  and the semiconductor layers  22  as an entirety are arranged in a matrix configuration. In the embodiment, the semiconductor layers  21  and  22  are arranged in a matrix configuration of, for example, five rows by five columns. 
     In  FIG. 2B , the interconnect layers  20   a  to  20   d  are schematically illustrated by straight lines. As shown in  FIG. 1A ,  FIG. 1B , and  FIG. 2B , the p-type clad layers  21   p  of the semiconductor layer  21  are connected to each other by the interconnect layer  20   a  and are connected to the pillar  17   a  by means of the via  18   a . The n-type clad layers  21   n  of the semiconductor layer  21  are connected to each other by the interconnect layer  20   b  and are connected to the pillar  17   b  by means of the via  18   b . The p-type clad layers  22   p  of the semiconductor layer  22  are connected to each other by the interconnect layer  20   c  and are connected to the pillar  17   c  by means of the via  18   c . The n-type clad layers  22   n  of the semiconductor layer  22  are connected to each other by the interconnect layer  20   d  and are connected to the pillar  17   d  by means of the via  18   d.    
     Thereby, a circuit block that is made of (pillar  17   a -via  18   a -interconnect layer  20   a -p-side electrode  23   p -p-type clad layer  21   p -active layer  21   a -n-type clad layer  21   n -n-side electrode  23   n -interconnect layer  20   b -via  18   b -pillar  17   b ) is formed between the pillar  17   a  and the pillar  17   b  to connect the multiple semiconductor layers  21  to each other in parallel. Also, a circuit block that is made of (pillar  17   c -via  18   c -interconnect layer  20   c -p-side electrode  24   p -p-type clad layer  22   p -active layer  22   a -n-type clad layer  22   n -n-side electrode  24   n -interconnect layer  20   d -via  18   d -pillar  17   d ) is formed between the pillar  17   c  and the pillar  17   d  to connect the multiple semiconductor layers  22  to each other in parallel. 
     As shown in  FIGS. 1A and 1B , fluorescer layers  14  are provided on the upper surfaces of the semiconductor layers  21  to cover the upper surfaces of the semiconductor layers  21 . In other words, the same number of fluorescer layers  14  as semiconductor layers  21  are provided; and the fluorescer layer  14  is disposed at each semiconductor layer  21 . When viewed from above, the configuration of each of the fluorescer layers  14  is, for example, a square having rounded corners. A prescribed fluorescer (not shown) is dispersed in the transparent resin layer of the fluorescer layer  14  to emit red light when the blue light emitted from the semiconductor layer  21  is incident. 
     The fluorescer layer  15  is provided on the entire surface of the insulating layer  13  to cover all of the fluorescer layers  14 . Thereby, one fluorescer layer  15  covers the upper surfaces of the semiconductor layers  21  and the upper surfaces of the semiconductor layers  22 . A prescribed fluorescer (not shown) is dispersed in the transparent resin layer of the fluorescer layer  15  to emit yellow light when the blue light emitted from the semiconductor layers  21  and  22  is incident. 
     The configuration of the semiconductor light emitting device  1  is, for example, a rectangular parallelepiped, e.g., a square rectangular parallelepiped, as viewed from above. The outer surface of the semiconductor light emitting device  1  includes the fluorescer layer  15 , the insulating layer  13 , the insulating film  16 , and the pillars  17   a  to  17   d . Thereby, all of the semiconductor layers  21  and semiconductor layers  22  are sealed inside a single package. 
     A method for manufacturing the semiconductor light emitting device according to the embodiment will now be described. 
       FIGS. 3A and 3B  to  FIGS. 5A and 5B  show the method for manufacturing the semiconductor light emitting device according to the embodiment. 
       FIG. 6  is a drawing in which  FIG. 5A  is superimposed onto  FIG. 2B . However, the directions of left and right are reversed from those of  FIG. 2B . 
       FIGS. 7A and 7B  to  FIGS. 10A and 10B  show the method for manufacturing the semiconductor light emitting device according to the embodiment. 
     In the description hereinbelow, the notation of “up” and “down” in the processes shown in  FIGS. 3A and 3B  to  FIGS. 8A and 8B  is reversed from the description of the configuration shown in  FIGS. 1A and 1B  and  FIGS. 2A and 2B  described above. 
     First, as shown in  FIGS. 3A and 3B , a crystal growth substrate  100  is prepared. The crystal growth substrate  100  is formed of, for example, monocrystalline sapphire (Al 2 O 3 ), silicon carbide (SiC), silicon (Si), etc. Although the description hereinbelow focuses on structures that are used to form one semiconductor light emitting device  1 , a wafer may be used as the crystal growth substrate  100  such that structures that are used to form multiple semiconductor light emitting devices  1  are made simultaneously on one wafer, and dicing and singulation are performed subsequently. 
     A semiconductor layer in which an n-type clad layer, an active layer, and a p-type clad layer are stacked in this order is formed on the crystal growth substrate  100  by performing epitaxial growth of, for example, gallium nitride (GaN). Then, the semiconductor layer is patterned to be subdivided into multiple square portions arranged in a matrix configuration; and the p-type clad layer and the active layer are removed from the corners of each of the portions to expose the n-type clad layer. 
     Thus, multiple semiconductor layers are formed on the crystal growth substrate  100 , are arranged in a matrix configuration, are separated from each other, are squares as viewed from above, include the n-type clad layer, the active layer, and the p-type clad layer stacked in this order, and have corners that are patterned into high mesas. Among the semiconductor layers, every other semiconductor layer that is disposed in a staggered configuration is called the semiconductor layer  21 ; and the remaining semiconductor layers are called the semiconductor layer  22 . The configuration of the semiconductor layer  21  and the configuration of the semiconductor layer  22  are the same. 
     Then, the p-side electrode  23   p  is formed on the p-type clad layer  21   p  of the semiconductor layer  21 ; the n-side electrodes  23   n  are formed on the exposed surfaces of the n-type clad layer  21   n ; the p-side electrode  24   p  is formed on the p-type clad layer  22   p  of the semiconductor layer  22 ; and the n-side electrodes  24   n  are formed on the exposed surfaces of the n-type clad layer  22   n.    
     Continuing as shown in  FIGS. 4A and 4B , the insulating layer  13  is formed on the crystal growth substrate  100  to cover the semiconductor layers  21  and  22 ; and via holes  13   h  are made respectively in portions of the regions directly above the p-side electrodes  23   p , portions of the regions directly above the n-side electrodes  23   n , portions of the regions directly above the p-side electrodes  24   p , and portions of the regions directly above the n-side electrodes  24   n.    
     Then, as shown in  FIGS. 5A and 5B , a seed layer (not shown) is formed on the insulating layer  13 . Continuing, a resist film is formed; and a resist pattern (not shown) is formed by patterning the resist film. Then, copper is electroplated; and subsequently, the resist pattern is removed. Thereby, the interconnect layer  20  is formed. A portion of the interconnect layer  20  is filled into the via holes  13   h  in via configurations to be connected to the p-side electrodes  23   p , the n-side electrodes  23   n , the p-side electrodes  24   p , and the n-side electrodes  24   n.    
     As shown in  FIG. 6 , the portions of the interconnect layer  20  are separated from each other and are classified into the interconnect layer  20   a  that connects the p-side electrodes  23   p  to each other, the interconnect layer  20   b  that connects the n-side electrodes  23   n  to each other, the interconnect layer  20   c  that connects the p-side electrodes  24   p  to each other, and the interconnect layer  20   d  that connects the n-side electrodes  24   n  to each other. 
     Then, as shown in  FIGS. 7A and 7B , the insulating layer  12  is formed above the insulating layer  13  and the interconnect layer  20  to cover the insulating layer  13  and the interconnect layer  20 . Then, via holes  12   a  to  12   d  are made in the insulating layer  12 , for example, two via holes apiece, for a portion of the region directly above the interconnect layer  20   a , a portion of the region directly above the interconnect layer  20   b , a portion of the region directly above the interconnect layer  20   c , and a portion of the region directly above the interconnect layer  20   d.    
     Continuing as shown in  FIGS. 8A and 8B , a seed layer (not shown) is formed on the insulating layer  12 . Then, a resist film is formed; and a resist pattern (not shown) is formed by patterning the resist film. Continuing, copper is electroplated; and subsequently, the resist pattern is removed. Thereby, the vias  18   a  to  18   d  and the pillars  17   a  to  17   d  are made. In other words, the portions of the copper film that are deposited by the electroplating to be filled into the via holes  12   a  to  12   d  are used as the vias  18   a  to  18   d , respectively. Further, the pillars  17   a  to  17   d  that are quadrilateral columns are formed on the insulating layer  12  to be connected respectively to the vias  18   a  to  18   d . Then, the insulating layer  11  is formed to fill between the pillars  17   a  to  17   d  by coating an insulating resin material. 
     Then, as shown in  FIGS. 9A and 9B , the directions of up and down for the structural bodies is reversed partway through the manufacturing. Hereinbelow, the notation of up and down is reversed from the description of  FIGS. 3A and 3B  to  FIGS. 8A and 8B  to match the description of  FIGS. 1A and 1B  and  FIGS. 2A and 2B . 
     Continuing, the crystal growth substrate  100  is removed by a method such as laser lift-off, mechanical polishing, etching, etc. Thereby, the upper surfaces of the semiconductor layers  21  and  22  are exposed at the upper surface of the insulating layer  13 , i.e., the surface that was in contact with the crystal growth substrate  100 . The crystal growth substrate  100  is not shown in  FIG. 9A . 
     Then, as shown in  FIGS. 10A and 10B , the multiple fluorescer layers  14  are formed on the insulating layer  13  in regions including the regions directly above the semiconductor layers  21  to cover the upper surfaces of the semiconductor layers  21 . The multiple fluorescer layers  14  are arranged in a staggered configuration. 
     Continuing as shown in  FIGS. 1A and 1B , one fluorescer layer  15  is formed on the entire surface of the insulating layer  13 . The fluorescer layer  15  covers the semiconductor layers  21 , the semiconductor layers  22 , and the fluorescer layers  14 . Subsequently, singulation is performed by dicing if necessary. Thereby, the semiconductor light emitting device  1  according to the embodiment is manufactured. 
     Operations and effects of the embodiment will now be described. 
       FIGS. 11A and 11B  are schematic cross-sectional views showing operations of the semiconductor light emitting device according to the embodiment. 
       FIG. 12  is an xy chromaticity diagram showing colors of the light emitted by the semiconductor light emitting device according to the embodiment. 
     As shown in  FIGS. 11A and 11B , the semiconductor layers  21  and  22  emit blue light. The fluorescer layers  14  emit red light when the blue light is incident; and the fluorescer layer  15  emits yellow light when the blue light is incident. 
     As shown in  FIG. 11A , when only the semiconductor layers  22  are caused to emit light without the semiconductor layers  21  emitting light by applying a voltage only between the pillar  17   c  and the pillar  17   d  without applying a voltage between the pillar  17   a  (referring to  FIG. 1A ) and the pillar  17   b , the light that is emitted from the semiconductor layers  22  substantially passes through only the fluorescer layer  15 . Therefore, a portion of the blue light emitted from the semiconductor layers  22  is converted into yellow light by the fluorescer layer  15 ; and the remainder of the blue light passes through as-is without being absorbed by the fluorescer layer  15 . As a result, the blue light and the yellow light are emitted from the semiconductor light emitting device  1 ; and the tint of the emitted light as an entirety is white, e.g., natural light having a color temperature of 5000 K. 
     On the other hand, as shown in  FIG. 11B , when only the semiconductor layers  21  are caused to emit light without the semiconductor layers  22  emitting light by applying a voltage only between the pillar  17   a  and the pillar  17   b  without applying a voltage between the pillar  17   c  and the pillar  17   d , the light that is emitted by the semiconductor layers  21  passes through the fluorescer layer  15  and the fluorescer layers  14 . Thereby, red light is emitted from the semiconductor light emitting device  1  in addition to the blue light and the yellow light. As a result, the tint of the light that is emitted by the semiconductor light emitting device  1  as an entirety is a cherry blossom color. 
     Then, as shown in  FIG. 12 , the tint of the light that is emitted by the semiconductor light emitting device  1  can be adjusted between natural light and cherry blossom by controlling the voltage applied between the pillar  17   a  and the pillar  17   b  and the voltage applied between the pillar  17   c  and the pillar  17   d . For example, it is also possible for the tint of the emitted light to be intermediate tints between natural light and cherry blossom. Thus, according to the semiconductor light emitting device according to the embodiment, the tint of the emitted light can be adjusted easily by merely controlling the potentials of four terminals, i.e., the pillars  17   a  to  17   d.    
     The pillar  17   b  which is the negative terminal of the semiconductor layers  21  may be connected to the pillar  17   d  which is the negative terminal of the semiconductor layers  22 . In such a case, the tint of the emitted light can be adjusted by controlling the potentials of three terminals. Also, the pillar  17   b  and the pillar  17   d  may have a common connection to the ground potential. In such a case, the tint of the emitted light can be adjusted by controlling the potentials of substantially two terminals. The pillar  17   a  which is the positive terminal of the semiconductor layers  21  may be connected to the pillar  17   c  which is the positive terminal of the semiconductor layers  22 ; the pillar  17   a  may be connected to the pillar  17   d ; or the pillar  17   b  may be connected to the pillar  17   c.    
     According to the embodiment, multiple semiconductor layers can be formed simultaneously in a micro region because the multiple semiconductor layers  21  and  22  are formed by forming a semiconductor layer collectively on the crystal growth substrate  100  and by subdividing the semiconductor layer. The interconnect layers  20   a  to  20   d , the vias  18   a  to  18   d , and the pillars  17   a  to  17   d  can be formed in the same process. As a result, according to the embodiment, a small semiconductor light emitting device for which toning is possible can be manufactured by easy processes. 
     Further, according to the embodiment, color breakup, i.e., the angle dependence of the tint of the emitted light, can be suppressed by arranging the multiple semiconductor layers  21  and the multiple semiconductor layers  22  in staggered configurations. 
     Second Embodiment 
     A second embodiment will now be described. 
       FIGS. 13A and 13B  are schematic cross-sectional views showing operations of a semiconductor light emitting device according to the embodiment. 
       FIG. 14  is an xy chromaticity diagram showing colors of the light emitted by the semiconductor light emitting device according to the embodiment. 
     As shown in  FIGS. 13A and 13B , the semiconductor light emitting device  2  according to the embodiment differs from the semiconductor light emitting device  1  (referring to  FIGS. 11A and 11B ) according to the first embodiment described above in that fluorescer layers  34  are provided instead of the fluorescer layers  14 . The fluorescer layers  34  emit light that is reddish yellow, e.g., orange, when the blue light emitted from the semiconductor layers  21  is incident. 
     Thereby, similarly to the first embodiment described above, when only the semiconductor layers  22  are caused to emit light as shown in  FIG. 13A , blue light and yellow light are emitted from the semiconductor light emitting device  2 ; and the tint of the emitted light as an entirety is, for example, natural light having a color temperature of 5000 K. On the other hand, when only the semiconductor layers  21  are caused to emit light as shown in  FIG. 13B , blue light, orange light, and yellow light are emitted from the semiconductor light emitting device  2 ; and the tint of the emitted light as an entirety is, for example, lamp having a color temperature of 2700 K. Accordingly, as shown in  FIG. 14 , the tint of the light emitted from the semiconductor light emitting device  1  can be adjusted arbitrarily between natural light and lamp. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. 
     Third Embodiment 
     A third embodiment will now be described. 
       FIG. 15  is a schematic cross-sectional view showing an operation of the semiconductor light emitting device according to the embodiment. 
     As shown in  FIG. 15 , a transparent layer  36  that is made of a transparent resin material is provided between the fluorescer layer  15  and the fluorescer layers  14  in the semiconductor light emitting device  3  according to the embodiment. In the specification, “transparent” also includes being semi-transparent. Thereby, the fluorescer layers  14  can be thermally isolated from the fluorescer layer  15 ; and more stable operations are possible. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. 
     Fourth Embodiment 
     A fourth embodiment will now be described. 
       FIG. 16  is a schematic cross-sectional view showing an operation of the semiconductor light emitting device according to the embodiment. 
     As shown in  FIG. 16 , the semiconductor light emitting device  4  according to the embodiment differs from the semiconductor light emitting device  1  (referring to  FIGS. 11A and 11B ) according to the first embodiment described above in that the fluorescer layers  15  are disposed to cover only the upper surfaces of the semiconductor layers  22  and do not cover the fluorescer layers  14 . The fluorescer layers  14  and the fluorescer layers  15  are covered with a transparent layer  37 . 
     According to the embodiment, the light that is emitted by the semiconductor layers  21  passes through only the fluorescer layers  14  and does not pass through the fluorescer layers  15 . Thereby, compared to the first embodiment described above, the tint of the emitted light can be adjusted in a wider range in the xy chromaticity diagram. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. 
     Fifth Embodiment 
     A fifth embodiment will now be described. 
       FIG. 17  is a plan view showing the disposition of the pillars of the semiconductor light emitting device according to the embodiment. 
     As shown in  FIG. 17 , the semiconductor light emitting device  5  according to the embodiment differs from the semiconductor light emitting device  1  (referring to  FIGS. 8A and 8B ) according to the first embodiment described above in that one common pillar  17   e  is provided instead of the pillar  17   b  which is the negative terminal of the semiconductor layers  21  and the pillar  17   d  which is the negative terminal of the semiconductor layers  22 . The pillar  17   e  is connected to the interconnect layer  20   b  by means of the via  18   b  and is connected to the interconnect layer  20   d  by means of the via  18   d . Thereby, the tint of the emitted light can be adjusted by controlling the potentials of three terminals. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. 
     Sixth Embodiment 
     A sixth embodiment will now be described. 
       FIG. 18  is a plan view showing the disposition of the pillars of the semiconductor light emitting device according to the embodiment. 
       FIG. 19  is a figure showing the connectional relationship between the semiconductor layers and the interconnect layers of the semiconductor light emitting device according to the embodiment. 
     As shown in  FIG. 18 , the semiconductor light emitting device  6  according to the embodiment differs from the semiconductor light emitting device  1  (referring to  FIG. 2B  and  FIG. 8A ) according to the first embodiment described above in that the pillar  17   d  and the via  18   d  are not provided. Also, as shown in  FIG. 19 , the interconnect layer  20   d  is connected to the interconnect layer  20   b  via an interconnect  25 . Accordingly, the pillar  17   b  is connected to both the interconnect layer  20   b  and the interconnect layer  20   d  and is connected to both the negative terminal of the semiconductor layers  21  and the negative terminal of the semiconductor layers  22 . Thereby, according to the embodiment as well, similarly to the fifth embodiment, the tint of the emitted light can be adjusted by controlling the potentials of three terminals. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. 
     Seventh Embodiment 
     A seventh embodiment will now be described. 
       FIG. 20  is a plan view showing the disposition of the pillars of the semiconductor light emitting device according to the embodiment. 
     As shown in  FIG. 20 , the semiconductor light emitting device  7  according to the embodiment differs from the semiconductor light emitting device  1  (referring to  FIGS. 8A and 8B ) according to the first embodiment described above in that one common pillar  17   f  is provided instead of the pillar  17   a  which is the positive terminal of the semiconductor layers  21  and the pillar  17   c  which is the positive terminal of the semiconductor layers  22 . The pillar  17   f  is connected to the interconnect layer  20   a  by means of the via  18   a  and is connected to the interconnect layer  20   c  by means of the via  18   c . Thereby, the tint of the emitted light can be adjusted by controlling the potentials of three terminals. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. 
     Eighth Embodiment 
     An eighth embodiment will now be described. 
       FIG. 21  is a plan view showing the disposition of the pillars of the semiconductor light emitting device according to the embodiment. 
       FIG. 22  is a figure showing the connectional relationship between the semiconductor layers and the interconnect layers of the semiconductor light emitting device according to the embodiment. 
     As shown in  FIG. 21 , the semiconductor light emitting device  8  according to the embodiment differs from the semiconductor light emitting device  1  (referring to  FIG. 2B  and  FIG. 8A ) according to the first embodiment described above in that the pillar  17   c  and the via  18   c  are not provided. Also, as shown in  FIG. 22 , the interconnect layer  20   c  is connected to the interconnect layer  20   a  via an interconnect  26 . Accordingly, the pillar  17   a  is connected to both the interconnect layer  20   a  and the interconnect layer  20   c  and is connected to both the positive terminal of the semiconductor layers  21  and the positive terminal of the semiconductor layers  22 . Thereby, according to the embodiment as well, the tint of the emitted light can be adjusted by controlling the potentials of three terminals. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. 
     According to the embodiments described above, a small semiconductor light emitting device for which toning is possible can be realized. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. Additionally, the embodiments described above can be combined mutually.