Patent Publication Number: US-7911750-B2

Title: Resistor triggered electrostatic discharge protection

Description:
FIELD OF THE INVENTION 
     The present invention generally relates to electrostatic discharge (ESD) protection of electronic elements and, more particularly, ESD protection of semiconductor components and integrated circuits. 
     BACKGROUND OF THE INVENTION 
     Modern electronic devices, especially semiconductor (SC) devices and integrated circuits (ICs) are at risk of damage due to electrostatic discharge (ESD) events. It is well known that electrostatic discharge from handling SC devices and ICs, by humans or machines or both, is a source of such excess voltage. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input/output (I/O) and other terminals of such SC devices and IC&#39;s.  FIG. 1  is a simplified schematic diagram of circuit  10  wherein ESD clamp  11  is placed between input/output (I/O) terminals  22  and ground or common terminal  23  of a SC device or IC to protect the other devices on the chip, that is, to protect circuit core  24  which is also coupled to I/O terminals  22  and common (e.g., “GND”) terminal  23 . Zener diode symbol  11 ′ within ESD clamp  11  indicates that the function of ESD clamp  11  is to limit the voltage than can appear across circuit core  24  irrespective of the voltage applied to external I/O and GND terminals  22 ,  23 . As used herein, the abbreviation “GND” is intended to refer to the common or reference terminal of a particular circuit or electronic element, irrespective of whether it is actually coupled to an earth return, and the abbreviation “I/O” is intended to include any external terminals other than “GND”. 
       FIG. 2  is a simplified schematic diagram illustrating internal components of prior art ESD clamp  21  which is inserted in circuit  10  in place of ESD clamp  11 . ESD clamp  21  comprises bipolar transistor  25 , having emitter  26 , collector  27  and base  28 , resistance  19  and Zener diode  130  having terminals  131 ,  132 . Zener diode  130  can also exhibit some small inherent resistance. Resistance  19  can include any inherent contact resistance and the effect of the inherent base resistance (not shown). In applications employing Zener diode  130  it is common to directly connect the base and emitter contacts, in which case resistance  19  is small. The purpose of resistance  19  in ESD clamp  21  is not to provide triggering, since this is provided by Zener diode  130  but to keep base  28  and emitter  26  at substantially the same potential unless there is an ESD event, so that in normal operation of circuit  10 , ESD clamp  21  does not interfere with the operation of circuit core  24 . When the voltage across terminals  22 ,  23  rises beyond a predetermined limit, Zener diode  130  turns on, thereby switching bipolar transistor  25  into conduction and desirably clamping the voltage across terminals  22 ,  23  at a level below a value capable of damaging circuit core  24 . 
       FIG. 3  is a simplified schematic diagram illustrating internal components of prior art ESD clamp  31  which is inserted in circuit  10  in place of ESD clamp  11 . ESD clamp  31  comprises bipolar transistor  25 , having emitter  26 , collector  27  and base  28  and resistor  29 . Resistor  29  is generally much larger than the inherent base and contact resistance. Resistor  29  is used to trigger bipolar transistor  25  into conduction when an ESD event occurs. When an ESD event arrives across terminals  22 ,  23  the collector-base voltage rises very rapidly and a small but finite leakage current begins to flow through the reverse biased collector base junction and through resistor  29 . By using a value for resistor  29  that is large compared to the inherent base resistance, sufficient voltage is developed across resistor  29  to bias the emitter-base junction into conduction, thereby turning on transistor  25  and providing ESD protection by clamping the external voltage at a level below that capable of causing damage to circuit core  24 . After the ESD transient has passed, resistor  29  discharges any charge stored on the emitter base junction, thereby returning transistor  25  to its non-conductive state so that in normal operation of circuit  10 , ESD clamp  31  does not interfere with the operation of circuit core  24 . 
     Design, construction and operation of such ESD devices is described for example in commonly owned U.S. Pat. No. 7,164,566 B2 “Electrostatic Discharge Protection Device and Method Therefore” by Hongzhong Xu et al, and further described by Danielle Coffing and Richard Ida in “Analysis of a Zener-Triggered Bipolar ESD Structure in a BiCMOS Technology”, IEEE BC™ 1998, pages 31-34, and by Joshi, Ida, Givelin and Rosenbaum in “An Analysis of Bipolar Breakdown and its Application to the Design of ESD Protection Circuits”, IEEE 01CH37167, 39 th  Annual International Reliability Physics Symposium, Orlando, Fla., 2001, pages 240-245.  FIG. 4  is an illustration of a typical current-voltage characteristic of an ESD clamp, where voltage Vt 1  is referred to as the trigger voltage and voltage Vh is referred to as the holding voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein: 
         FIG. 1  is a simplified schematic diagram of a generalized ESD protection circuit using an ESD clamp to protect a circuit core from ESD events; 
         FIG. 2  is a simplified schematic diagram illustrating internal components of a prior art ESD clamp; 
         FIG. 3  is a simplified schematic diagram illustrating internal components of a further prior art ESD clamp; 
         FIG. 4  is an illustration of a typical current-voltage characteristic of the ESD clamp of  FIGS. 2 and 3 ; 
         FIG. 5  is a simplified schematic diagram illustrating internal components of an ESD clamp according to an embodiment of the present invention; 
         FIGS. 6-7  are simplified schematic diagrams illustrating internal components of an ESD clamp according to further embodiments of the present invention in which, in  FIG. 6 , two ESD clamps of the type shown in  FIG. 5  have been electrically cascaded or stacked, and in  FIG. 7 , three ESD stages of the type shown in  FIG. 5  have been electrically cascaded or stacked, in order to achieve higher and higher trigger voltage; 
         FIG. 8  is a simplified schematic cross-sectional view through the ESD clamp of  FIG. 5  showing an arrangement of its internal regions according to an embodiment of the present invention and providing further detail; 
         FIG. 9  is a simplified schematic plan view of the ESD clamp of  FIG. 8 ; 
         FIG. 10  is a simplified plan view of two ESD clamps of the type shown in  FIG. 9  electrically cascaded or stacked according to the circuit of  FIG. 6 ; 
         FIGS. 11-12  are plots of current verses voltage for ESD clamps according to several embodiments of the invention, illustrating how the trigger voltage Vt 1  may be adjusted by changing values of R and/or by electrically cascading or stacking modular ESD stages. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description. 
     For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention. 
     The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. 
     While the circuits of  FIGS. 2 and 3  can be effective in providing ESD protection, further improvements are desirable. Accordingly, there is an ongoing need to provide improved ESD clamps, especially ESD clamps that are adapted to achieve a variety of predetermined trigger voltages, and that are bidirectional so as to conserve chip area, and that are modular in nature so as to be electrically stackable, and that are less sensitive to manufacturing variations that can adversely affect manufacturing yield. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention. 
       FIG. 5  is a simplified schematic diagram illustrating internal components of ESD clamp  41 , according to an embodiment of the present invention. ESD clamp  41  is used in generalized protection circuit  10  in place of ESD clamp  11 . ESD clamp  41  differs from prior art ESD clamps  21 ,  31  of  FIGS. 2 and 3  in that it utilizes two mirror coupled transistor stages T 1  and T 2  joined at node  52  and further does not have Zener diode  130 . Transistor stage T 1  comprises transistor  25  analogous to transistor  25  of  FIGS. 2-3  with emitter  26 , collector  27  and base  28 , plus resistor  29 , coupled in generally the same manner as in  FIGS. 2 and 3 . The same reference numbers are used for transistor stage T 1  and ESD clamp  31  of  FIG. 3 , to indicate that the individual elements are analogous but not necessarily identical. Resistor  29  is coupled between base  28  at node  34  and emitter  26  at node  32 . Node  32  is adapted to be coupled to GND terminal  23  of ESD protection circuit  10  of  FIG. 1 . Transistor stage T 2  comprises transistor  35  having emitter  36 , collector  37  and base  38 . Resistor  39  is coupled between base  38  at node  44  and emitter  36  at node  42 . Node  43  of Transistor stage T 2  is coupled to node  33  of transistor stage T 1  via node  52 . Nodes  33 ,  52  and  43  are shown as separate nodes merely for convenience of description and can be combined. Node  42  of Transistor stage T 2  is adapted to be coupled to input/output (I/O) terminals  22  of ESD circuit  10  of  FIG. 1 . It will be noted that while stages T 1  and T 2  of ESD clamp  41  individually resemble ESD clamp  31  of  FIG. 3 , they are serially coupled in opposition or in mirror arrangement, that is, node  43  of transistor stage T 2  is coupled to node  33  of transistor stage T 1 , or to say it another way, collector  27  of transistor stage T 1  is coupled to collector  37  of transistor stage T 2  via common node  52 . An advantage of ESD clamp  41  compared to ESD clamps  21  and  31  is that ESD clamp  41  is bi-directional, that is, it will respond, for example, to a positive going ESD transient at either of terminals  22  or  23  of ESD circuit  10 . This is a significant advantage since it results in a substantial area saving in providing bi-directional ESD protection to circuit core  24 , and thereby lowers the cost of manufacture of the SC device or IC containing circuit core  24  of  FIG. 1 . 
       FIGS. 6-7  are simplified schematic diagrams illustrating internal components of ESD clamps  51 ,  61  according to further embodiments of the present invention, wherein it will be understood that clamps  51 ,  61  are substituted for clamp  11  in generalized ESD protection circuit  10  of  FIG. 1 . ESD clamp  51  differs from ESD clamp  41  of  FIG. 5  in that it comprises two serially coupled ESD stages, that is, lower ESD stage or clamp  41  (e.g., clamp  41  of  FIG. 5 ) and upper ESD stage or clamp  41 ′ (also analogous to clamp  41  of  FIG. 5 ). ESD clamp  61  differs from ESD clamp  51  of  FIG. 6  in that it comprises three serially coupled ESD stages, that is, lower ESD stage or clamp  41 , intermediate ESD stage or clamp  41 ′ and upper or end ESD stage or clamp  41 ″. The terms “lower” or “first” and “upper” or “end” or “last” are used herein merely to indicate that one of the serially coupled ESD stages (e.g., “lower or “first” ESD clamp  41 ) is coupled to so-called GND terminal  23  of ESD circuit  10  and another of the serially coupled ESD stages (e.g., “upper” or “end” or “last” clamp  41 ′ or  41 ″) is coupled to so-called I/O terminals  22  of ESD circuit  10  of  FIG. 1 , wherein GND is usually (but not always) the lower potential side of circuit  10  and the I/O terminals are coupled to what is usually (but not always) the higher potential side of ESD circuit  10 . The designations of “lower” or “first” and “upper” or “end” or “last” are merely for convenience of reference and not intended to be limiting. Lower ESD stage or clamp  41  is described in connection with  FIG. 5 . Intermediate and upper ESD stages or clamps  41 ′ and  41 ″ are analogous to lower ESD stage or clamp  41  and the convention is adopted of identifying the individual components thereof analogous to those of lower ESD stage or clamp  41  by adding a prime to the individual reference numbers of intermediate stage or clamp  41 ′ and a double prime to the individual reference numbers of upper or end or last stage or clamp  41 ″, for example, emitters  26 ′,  26 ″ of intermediate and upper ESD stages or clamps  41 ′,  41 ″ are analogous to emitter  26  of lower ESD stage or clamp  41 , collectors  27 ′,  27 ″ to collector  27 , and so forth. ESD stages or clamps  41 ,  41 ′,  41 ″ are coupled so that: (i) node  42  of lower or first stage or clamp  41  is coupled to node  32 ′ of intermediate stage or clamp  41 ′ via node  65 ; (ii) node  42 ′ of intermediate stage or clamp  41 ′ is coupled to node  32 ″ of end or upper or last stage or clamp  41 ″ via node  65 ′; (iii) lower or bottom node  32  of lower or first stage of ESD clamp  41  is adapted to be coupled to GND terminal  23  of ESD circuit  10 ; and (iv) top or upper node  42 ″ of upper or end or last stage of ESD clamp  41 ″ is adapted to be coupled to I/O terminals  22  of ESD circuit  10 . When only two stages are used, then stage or clamp  41 ″ is omitted, and upper node  42 ′ of stage or clamp  41 ′ is coupled to I/O terminals  22 . ESD clamp  51  of  FIG. 6  and ESD clamp  61  of  FIG. 7  are referred to as “stacked” or “cascaded” ESD clamps, in that they comprise an electrically serially coupled arrangement of individual bi-directional ESD stages or clamps  41 ,  41 ′,  41 ″, etc.  FIG. 6  shows two-stack ESD clamp  51  and  FIG. 7 , shows three-stack ESD clamp  61 . Intermediate nodes  42 ,  65  and  32  between ESD stacks or clamps  41  and  41 ′, and intermediate nodes  42 ′,  65 ′ and  32 ″ between ESD stacks or clamps  41 ′ and  41 ″ are shown as separate nodes merely for convenience of description and can be combined. Such a multiple “stacked” arrangement makes it possible to obtain higher trigger voltage and holding voltage (e.g., voltages Vt 1  and Vh of  FIG. 4 ) than are generally possible with a single ESD protection stage, such as is illustrated in  FIG. 5 . 
     While  FIGS. 6 and 7  illustrate two-stack and three-stack configurations, respectively, any number N of ESD stages  41 , where N=1, 2, 3, 4, . . . etc., may be stacked in generally the same manner and the “N-stack” substituted for ESD clamp  11  of  FIG. 1 . In such case, then the “first” of the N serially coupled ESD stages would ordinarily have its lower node  32   1  (by analogy to stage  41 ) coupled to GND terminal  23  of circuit  10  of  FIG. 1  and the Nth stage would ordinarily have its upper node  42   N  (by analogy to stage  41 ″) coupled to the I/O terminals of the circuit core  24  of  FIG. 1 , where the subscripts  1 ,  2 , . . . N indicate the particular stage. In the same manner, the lower, intermediate and upper nodes of the i th  ESD stage would be identified as  32   i ,  52   i , and  42   i  respectively, and the intermediate nodes between electrically adjacent ESD stages “i” and the “(i+1)” would be identified as  65   i . 
       FIG. 8  shows simplified schematic cross-sectional view  70  through ESD clamp  71  analogous to ESD clamp  41  of  FIG. 5  showing an arrangement of its internal regions and providing further detail. For convenience of reference to the circuit schematic of ESD clamp  41  of  FIG. 5 , the corresponding physical regions of ESD clamp  71  are identified with the corresponding reference numbers used in  FIG. 5 . Referring now to both  FIGS. 5 and 8 , ESD clamp  71  comprises P-type substrate (P-SUBSTRATE)  72 , N-type buried layer (NBL)  73  and N doped regions  741 ,  742 ,  743  (collectively  74 ). N-type buried layer  73  and N doped regions  74  serve as the collectors  27 ,  37  coupled by node  52  corresponding to N doped region  742 . ESD clamp  71  further comprises P-type epi regions (P-EPI)  751 ,  752  (collectively  75 ) separated by N doped region  742  and P-type diffused regions (P-DIFF)  761 ,  762  (collectively  76 ) respectively in P-type epi regions  751 ,  752  that serve as base regions  28 ,  38 . P+ base contact regions  771 ,  772  (collectively  77 ) are provided in diffused regions  76  wherein base contact region  771  is coupled to base node  34  and base contact region  772  is coupled to base node  44  (see also plan view  84  of  FIG. 9 ). N+ emitter regions  781 ,  782  (collectively  78 ) are also provided in diffused regions  76 , wherein emitter region  781  is coupled to emitter node  32  and emitter region  782  is coupled to emitter node  42  (see also plan view  84  of  FIG. 9 ). Resistors  29 ,  39  couple emitter node  32  to base node  34  and emitter node  42  to base node  44 , respectively. Resistors  29 ,  39  are desirably external resistors, that is, fabricated during the same manufacturing process and by the same general techniques used for preparing the core circuit and ESD protection device, but which are not formed within semiconductor  80 . Conventional surface dielectric passivation layer  79  is also provided. 
       FIG. 9  shows simplified schematic plan view  84  of the ESD clamp  71  of  FIG. 8 . Like reference numbers are used in  FIGS. 8 and 9  to refer to like regions. N doped region  74  conveniently has a square plan view shape wherein N doped region  741  forms a central divider or partition, separating P-epi regions  751 ,  752 . N doped region  741  corresponds to node  52  of the circuit of  FIG. 5 . P-diffused regions  761 ,  762  are located in P-epi regions  751 ,  752  respectively. N+ emitter regions  781 ,  782  and P+ base contact regions  771 ,  772  are located in P-diffused regions  761 ,  762  respectively. Emitter region  781  has emitter contact region  783  to which is coupled conductor  81 , corresponding to node  32 . Emitter region  782  has emitter contact region  784 , to which is coupled conductor  82  corresponding to node  42 . Conductors  81 ,  82  are desirably a highly conductive material such as a metal or heavily doped semiconductor or semi-metal so as to minimize the series resistance of the ESD clamp to the ESD transient. P+ base contact regions  771 ,  772  have ohmic contact regions  773 ,  774  coupled respectively to conductors  341 ,  441  which extend to resistors  29 ,  39  respectively. Resistors  29 ,  39  are desirably thin film resistors, as for example, and not intended to be limiting of poly-silicon or other poly-semiconductor (poly-SC), formed on the upper surface of dielectric passivation layer  79 . In this embodiment, each of resistors  29 ,  39  is formed from the parallel combination of two resistors  291 ,  292  and  391 ,  392 , each having a resistance value of 2R, where R is the desired emitter-base coupling resistance value. For example, contact nodes  34  on 2R resistances  291 ,  292  are coupled to base contacts  773  via conductors  341  and to emitter contact  783  via contacts  321  and emitter conductor  81 , so that resistances  291 ,  292  of value 2R are electrically in parallel, thereby yielding the desired resistance value of R. Similarly, contact nodes  44  on 2R resistances  391 ,  292  are coupled to base contacts  774  via conductors  441  and to emitter contact  784  via contacts  421  and emitter conductor  82 , so that resistances  391 ,  392  of value 2R are electrically in parallel, thereby yielding the desired resistance value of R. While the embodiment of  FIG. 9  shows the resistors R of the circuit of  FIG. 5  being provided by a parallel combination of two resistances each of value 2R, persons of skill in the art will understand that this is by way of example and not intended to be limiting. Resistances  29 ,  39  of value R may be provided by a parallel combination of resistors of value 2R, 4R, 6R, etc., or a series combination of resistors of value R/2, R/3, R/4 etc., or by a series-parallel combination of individual resistances of other sizes, or by forming resistances R from one or more strips of resistive material of known resistance per square, and then locating, for example, contacts  321 ,  421  at different distances along the resistive strip to produce the desired resistances R. These modifications can be accomplished merely by altering only the metal contact mask rather than altering multiple masks of the planar process used for forming such ESD clamps. As will be subsequently shown, the trigger voltage Vt 1  can be changed by changing the values of resistance R of resistors  29 ,  39  of  FIG. 5 . Thus, the invented arrangement of incorporating resistances whose values can be altered by a minimal mask change allows a single process and basic mask set to be easily adapted to provide different desired values of Vt 1 . This is a significant advantage. 
       FIG. 10  is a simplified plan view  94  of two ESD clamps  84 ,  84 ′ of the type shown in  FIG. 9  electrically cascaded or stacked in series to provide ESD clamp  86  analogous to ESD clamp  51  of  FIG. 6  comprising stages  41 ,  41 ′. The same reference numbers are used in  FIG. 10  as in  FIG. 9  to identify similar elements, wherein the elements of lower or first ESD stage  71 ,  84  are the same as in  FIG. 9 , and those of upper or end or last ESD stage  71 ′,  84 ′ are identified by adding a (′) to the corresponding elements. Accordingly, the discussion of  FIG. 9  is incorporated herein by reference as applied to  FIG. 10 . Conductor  81  is adapted to be coupled to GND terminal  23  of circuit  10  of  FIG. 1  and conductor  82 ′ is adapted to be coupled to I/O terminal  22  of circuit  10  of  FIG. 1 . 
     It has been found that the arrangements illustrated in  FIGS. 5-10  provide very useful ESD protection when applied in circuit  10  of  FIG. 1 , and that the values of Vt 1  can be easily adjusted to suit different circumstances, e.g., different circuit operating voltages and/or desired protection thresholds. The entries in Table I show how varying the value of resistances R in the various embodiments can be used to adjust the desired trigger voltage Vt 1 . The data of Table I was taken on ESD devices corresponding to the circuit shown in  FIG. 5  and the physical implementation illustrated in  FIGS. 8-9 , where R 29  and R 39  are the values of resistors  29 ,  39  respectively. 
                     TABLE I               Single Stack, Bi-directional, Resistor Triggered ESD device                                                R 29  = R 39  = 2 kΩ   R 29  = R 39  = 4 kΩ   R 29  = R 39  = 8 kΩ   R 29  = R 39  =                   20 kΩ       Vt1 = 44.41 volts   Vt1 = 32.9 volts   Vt1 = 27.44 volts   Vt1 = 23.5                   volts                    
It will be noted that by adjusting the values of R 29  and R 39 , that the trigger voltage Vt 1  can be adjusted over a wide range. In general, resistor values in the range of about 0.5 k to 150 k Ohm are useful, with resistor values in the range of about 1 k to 100 k Ohms being more convenient and resistor values in the range of about 1 k to 60 k Ohms being preferred. While the data presented in Table 1 is for the case where all of the resistors in the resistor triggered ESD clamp stages were set to the same values, that is, all stages had the same value resistors (e g., 2 k or 4 k or 8 k or 20 k Ohms) for the different tests, this is not essential and different stages may use different resistor values in order to fine tune the desired trigger voltage and/or to obtain different trigger voltages for different polarity ESD transients. This is a further advantage of using multiple resistor triggered ESD clamp stages as described herein.
 
       FIGS. 11-12  are plots of current I in amps verses voltage V in volts for ESD clamps according to several embodiments of the invention when subjected to simulated ESD transients obtained from a charged transmission line, for example, as are routinely used for human body model (HBM) testing of ESD clamps.  FIG. 11  shows I-V plot  90  for single, double and triple stack or stage ESD clamps. Trace  91  shows the I-V plot obtained for single stage ESD clamp  41  of  FIG. 5  having the cross-section and plan view layout illustrated in  FIGS. 8 and 9 , respectively. Trace  92  shows the I-V plot obtained for double stack or stage ESD clamp  51  of  FIG. 6  having the plan view layout illustrated in  FIG. 10  and cross-sectional views corresponding to two serially coupled arrangements of the cross-section shown in  FIG. 8 . Trace  93  shows the I-V plot obtained for triple stack or stage ESD clamp  61  of  FIG. 5  having the cross-section and plan view layout corresponding to three serially coupled arrangements of ESD clamps  71  illustrated in  FIGS. 8 and 9 , respectively. In all three cases the resistor values R 29 , R 39  were set at 40 k Ohms, that is R 29 =R 39 =R 29′ =R 39′ =R 29″ =R 39″ =40 k Ohms. Vt 1  for the single stack (trace  91 ) was 23.7 volts, Vt 1  for the double stack (trace  92 ) was 48.9 volts, and Vt 1  for the triple stack (trace  93 ) was 73.9 volts, illustrating how different values of trigger voltage Vt 1  (and holding voltages) may be obtained by electrically stacking ESD stages. For experimental convenience, the individual ESD stages in the two stack and three stack arrangements were substantially identical to the single stack arrangement and had the same resistance values R 29 , R 39  but this is not essential. It may be desirable in some situations to have resistors R 29 , R 29′ , R 29″ , etc., have the same resistance values and resistors R 39 , R 39′ , R 39″ , etc., have different resistance values. 
       FIG. 12  shows I-V plot  95  for a double stack or stage ESD clamp corresponding to the circuit of ESD clamp  51  of  FIG. 6  and cross-section and plan layout shown in  FIGS. 8-9  respectively, with R 29 , R 39 =40 k Ohms but oriented in different directions on the same wafer. The device of trace  96  was oriented at 0 or 180 degrees and the device of trace  97  was oriented at 90 or 270 degrees. Stated another way, the devices of traces  96  and  97  were oriented at right angles to each other. The device corresponding to trace  96  gave Vt 1 =53.4 volts and the device of trace  97  gave Vt 1 =53.1 volts. This is an important result since it is well known in the art that ESD clamps often are orientation sensitive, that is, nominally identical ESD clamps on the same wafer or die, but with different azimuthal orientations in plan view can exhibit significantly different values of Vt 1  and I-V behavior, to the detriment of performance and manufacturing yield. The fact illustrated in  FIG. 12  that the invented arrangement does not exhibit this behavior is a significant and economically important result. 
     The two-stack results (trace  92 ) of  FIG. 11  with 40 k Ohm resistors gave Vt 1 =48.9 and the two stack results of  FIG. 12  (traces  96 ,  97 ) gave Vt 1 =53.4 and 53.1. The difference in Vt 1  results=(53.25−48.9)/48.9=8.8% occurred because the devices of  FIG. 12  where of smaller area than those of  FIG. 11 . While Vt 1  depends strongly on the value of resistors R 29  R 39 , etc., as shown by Table I, Vt 1  is also weakly dependent on the device size, thereby providing another means for fine tuning the desired value of Vt 1 . 
     According to a first embodiment, there is provided an electronic device having input/output (I/O) and common terminals, comprising, a circuit core coupled between the I/O and common terminals, and one or more serially arranged resistor triggered bi-directional ESD clamp stages coupled between the I/O and common terminals. According to a further embodiment, there is only one resistor triggered bi-directional ESD clamp stage. According to a still further embodiment, each resistor triggered bi-directional ESD clamp stage comprises first and second serially coupled bipolar transistors, each bipolar transistor having an emitter, a base and a collector, and wherein the emitter of the first transistor is coupled to the common terminal and the emitter of the second transistor is coupled to the I/O terminals and the collectors of the first and second transistors are coupled together, and a first external resistor is coupled between the emitter and base of the first transistor and a second external resistor is coupled between the emitter and base of the second transistor. According to a yet further embodiment, there are two or more resistor triggered bi-directional ESD clamp stages and each bipolar transistor has an emitter, a base and a collector, and wherein the emitter of the second transistor of the first stage is coupled to the emitter of the first transistor of the second stage. According to a still yet further embodiment, there are three or more resistor triggered bi-directional ESD clamp stages and each bipolar transistor has an emitter, a base and a collector, and wherein the emitter of the second transistor of the first stage is coupled to the emitter of the first transistor of the second stage and the emitter of the second transistor of the second stage is coupled to the emitter of the first transistor of the third stage. According to a yet still further embodiment, the first and second resistors have values in the range of about 0.5 k Ohm to 150 K Ohms. According to another embodiment, the first resistors of each of the one or more serially arranged resistor triggered bi-directional ESD clamp stages have substantially the same first values and the second resistors of each of the one or more serially arranged resistor triggered ESD clamp stages have substantially the same second values. According to a still another embodiment, the first and second resistors have different values. According to a yet another embodiment, the first and second resistors of at least some of the one or more serially arranged resistor triggered bi-directional ESD clamp stages have different values. 
     According to a second embodiment, there is provided an integrated ESD protection device, having I/O and common terminals adapted to be coupled to I/O and common terminals of a core circuit being protected by the integrated ESD protection device, comprising, first and second bipolar transistors having a common collector region and comprising, first and second base regions of a first conductivity type, one base region for each bipolar transistor, a region of a second, opposite conductivity type extending beneath the first and second base regions, and separating and laterally surrounding the first and second base regions, and serving as the common collector region of the first and second bipolar transistors, a first emitter region of the second conductivity type within the first base region and a second emitter region of the second conductivity type within the second base region, wherein the first emitter region is adapted to be coupled to the common terminal of the core circuit and the second emitter region is adapted to be coupled to the I/O terminals of the core circuit, and first and second resistors coupled respectively between the emitter region and the base region of the first transistor and the emitter region and the base region of the second transistor, wherein the first and second resistors are located so that portions of the region of second, opposite, conductivity type are located between the first resistor and the first base region and between the second resistor and the second base region. According to a further embodiment, the first and second resistors are thin film resistors. According to a still further embodiment, the thin film resistors are formed of poly-semiconductor. According to a yet further embodiment, one or both of the first and second resistors each comprise multiple segments coupled in a series arrangement or a parallel arrangement or a series-parallel arrangement to provide the desired resistance values. According to a still yet further embodiment, the first and second resistors have substantially the same resistance value. According to a yet still further embodiment, the first and second resistors have different resistance values. According to another embodiment, the combination of the first and second transistors and the first and second resistors form a modular ESD clamp stage; and the integrated ESD protection device further comprises two or more serially coupled modular ESD clamp stages. 
     According to a third embodiment, there is provided an ESD protection device adapted to be coupled between common and I/O terminals of a core circuit desired to be protected, comprising, one or more bi-directional resistor triggered ESD stages, each stage comprising, two bipolar transistors having a common collector and isolation region, a base region for each transistor separated by a portion of the common collector and isolation region, separate emitter regions, one in each base region, base contact regions, one for each base region, and ESD trigger resistors external to the transistors, coupled between the emitter region and the base contact region of each transistor. According to a still further embodiment, the ESD trigger resistors lie laterally outside the collector and isolation region. According to a still further embodiment, the ESD trigger resistors are thin film resistors. According to a yet further embodiment, the ESD trigger resistors have resistance values in the range of about 0.5 k Ohms to 150 k Ohms. 
     While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.