Patent Publication Number: US-10790204-B2

Title: Test structure leveraging the lowest metallization level of an interconnect structure

Description:
BACKGROUND 
     The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for testing a field effect-transistor or Kelvin field-effect transistor and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. 
     Test structures can be used to test for manufacturing variations in integrated circuit structures, such as manufacturing variations relating to contacts and vias that are coupled with the gates, sources, and drains of field-effect transistors. Test structures may be formed at various locations across a wafer and may be used to test the resistance response of a contact or via in a device-under-testing. In a test structure, current is supplied via a pair of connections (i.e., current leads) and a voltage drop occurs allowing the impedance (e.g., resistance) to be measured according to Ohm&#39;s law. A pair of sense connections (i.e., voltage leads) are provided in proximity to the target impedance and may be used in determining the voltage drop across the device under testing. 
     Conventional testing may rely on test structures (e.g., field-effect transistors and Kelvin field-effect transistors) connected with wiring in the lowest metallization level (i.e., the M0 metallization level) and also with wiring in the overlying metallization level (i.e., the M1 metallization level). Because conventional testing does not occur until after the formation of the M1 metallization level, production costs may be elevated because failures are only detected after M1 metallization level is formed. In addition, conventional testing must take the impedance of interconnects in the M1 metallization level into account. 
     Improved structures for testing a field effect-transistor or Kelvin field-effect transistor and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor are needed. 
     SUMMARY 
     In an embodiment of the invention, a structure includes a test pad, a device-under-testing including one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines connected with the test pad. One or more contacts are arranged between the metallization level and the device-under-testing. The one or more contacts directly connect the one or more interconnect lines with the one or more source/drain regions. 
     In an embodiment of the invention, a method includes forming a device-under-testing that includes one or more source/drain regions, forming a test pad, and forming a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines connected with the test pad. The method further includes forming one or more contacts arranged between metallization level and the device-under-testing. The one or more contacts directly connect the one or more interconnect lines with the one or more source/drain regions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals are used to indicate like features in the various views. 
         FIGS. 1-4  are schematic top views of test structures in accordance with embodiments of the invention. 
         FIG. 4A  is a schematic top view of a portion of the test structure of  FIG. 4  in accordance with alternative embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     With reference to  FIG. 1  and in accordance with embodiments of the invention, a test structure  10  includes a field-effect transistor  12  (i.e., a device-under-testing) with fins  14  that are arranged over an active device region  16  and a gate structure  18  that transversely overlaps with the fins  14 . The field-effect transistor  12  is fabricated by front-end-of-line processing, such as by complementary-metal-oxide semiconductor (CMOS) processing. The fins  14  may include source/drain regions in the form of drain regions  20 , which may include doped semiconductor material of the fins  14  and doped epitaxial semiconductor material grown from the fins  14 . The fins  14  may include additional source/drain regions in the form of source regions  22 , which may also include doped semiconductor material of the fins  14  and doped epitaxial semiconductor material grown from the fins  14 . The gate structure  18  is arranged laterally between the drain regions  20  and the source regions  22 . Specifically, the drain regions  20  are laterally arranged on one side of the gate structure  18  and the source regions  22  are laterally arranged on an opposite side of the gate structure  18 . The gate structure  18  may include a conductor, such as doped polysilicon or a metal, defining a gate electrode and a gate dielectric layer arranged between the exterior surfaces of the fins  14  and the gate electrode. 
     Drain contacts  24 , source contacts  26 , and a gate contact  28  are formed by middle-of-line (MOL) processing in a dielectric layer (not shown) of a contact level and provide vertical interconnects. The drain contacts  24  respectively extend to the drain regions  20  associated with different fins  14  of the field-effect transistor  12 . The source contacts  26  respectively extend to the source regions  22  associated with different fins  14  of the field-effect transistor  12 . The contact  28  extends to the gate electrode of the gate structure  18 . 
     A metallization level  30  is formed by back-end-of-line processing over the field-effect transistor  12  and contacts  24 ,  26 ,  28 . The metallization level  30  is part of an interconnect structure that may include interconnects in additional metallization levels arranged in a stack over the metallization level  30 . The metallization level  30  is the closest of the multiple metallization levels in the vertical stacking to the field-effect transistor  12 . The metallization level  30  includes interconnect lines that are arranged in a pattern of non-mandrel lines  32 , mandrel lines  34 , and transverse mandrel lines  36 . Each of the transverse mandrel lines  36  physically and electrically connects one or more of the mandrel lines  34  together. The metallization level  30  further includes mandrel connections  38  and test pads  40 ,  42 ,  44  that are individually connected with one of the mandrel connections  38 . 
     Different sets of the mandrel lines  34  of the metallization level  30  are connected with one of the transverse mandrel lines  36 , and each of the mandrel connections  38  may include one or more interconnect lines that extend from one of the transverse mandrel lines  36  to either the test pad  40  or the test pad  42 . The test pad  40  is connected with the source regions  22  of the fins  14 , and the test pad  42  is connected with the drain regions  20  of the fins  14 . The mandrel lines  34  that are connected with the source regions  22  of the fins  14  include cuts, diagrammatically shown by reference numeral  46 , that disconnect these mandrel lines  34  from the transverse mandrel line  36  connected with the test pad  42 . Similarly, the mandrel lines  34  that are connected with the drain regions  20  of the fins  14  also include the cuts  46  that disconnect these mandrel lines  34  from the transverse mandrel line  36  connected with the test pad  40 . The cuts  46  may be provided during multiple patterning by cutting the mandrels used to form the mandrel lines  34 . 
     The non-mandrel lines  32  of the metallization level  30  are not connected by contacts with either the drain regions  20  or source regions  22  of the underlying fins  14 . The non-mandrel lines  32  are spaced from the transverse mandrel lines  36  by a distance related to the thickness of sidewall spacers used during multiple patterning, and may further include non-mandrel cuts (not shown) adjacent to their opposite ends. The test pad  44  is connected by contact  28  and one of the mandrel interconnects  38  with the gate structure  18 . 
     The source regions  22  of the fins  14  may be connected by the source contacts  26  with the mandrel lines  34  that are connected with one of the transverse mandrel lines  36 , which is in turn connected by one of the mandrel connections  38  with the test pad  40 . The source contacts  26  provide respective vertical interconnections between the mandrel lines  34  and the source regions  22  of the fins  14 . The mandrel lines  34  associated with the test pad  40  are directly connected by the source contacts  26  with the source regions  22  of the fins  14 . In an embodiment, each of the mandrel lines  34  associated with the test pad  40  is directly connected by only one of the source contacts  26  with the source region  22  of each of the fins  14 . 
     The drain regions  20  of the fins  14  may be connected by the drain contacts  24  with the mandrel lines  34  that are connected with one of the transverse mandrel lines  36 , which is in turn connected by one of the mandrel connections  38  with the test pad  42 . The drain contacts  24  provide respective vertical interconnections between the mandrel lines  34  and the drain regions  20  of the fins  14 . The mandrel lines  34  associated with the test pad  42  are directly connected by the drain contacts  24  with the drain regions  20  of the fins  14 . In an embodiment, each of the mandrel lines  34  associated with the test pad  42  is directly connected by only one of the drain contacts  24  with the drain region  20  of each of the fins  14 . 
     The non-mandrel lines  32 , mandrel lines  34 , and transverse mandrel lines  36  of the metallization level  30  may be formed by a multiple-patterning process, such as a self-aligned double patterning (SADP) process. In that regard, mandrels may be formed by patterning a layer of a sacrificial material with lithography and etching processes. The etch mask used during patterning to form the mandrels may include cuts that are transferred to the mandrels as mandrel cuts that are arranged along the length of the mandrels. These mandrel cuts are transferred to the mandrel lines  34  to provide the cuts  46  that disconnect the mandrel lines  34  from one or the other of the transverse mandrel lines  36 . A conformal dielectric layer is formed over the mandrels and over the parallel linear spaces between the mandrels. A block mask may be formed over portions of the conformal dielectric layer within the parallel spaces and these portions of the conformal dielectric layer may subsequently define non-mandrel cuts. The non-mandrel cuts are transferred to the non-mandrel lines to provide discontinuities between the opposite ends of the non-mandrel lines  32  and the transverse mandrel lines  36 . Sidewall spacers are formed on the mandrels by an etching process, such as a reactive ion etching process, that shapes the conformal dielectric layer with the block mask present. The conformal dielectric layer is removed from the parallel spaces arranged between adjacent spacer-clad mandrels during the etching process. These parallel spaces subsequently define the non-mandrel lines  32 . After the mandrels are pulled from their positions between the sidewall spacers, the pattern is transferred to a hardmask and subsequently transferred from the hardmask to an interlayer dielectric layer (not shown) arranged over the field-effect transistor  12  as trenches. The trenches are subsequently filled with conductor to define the non-mandrel lines  32 , mandrel lines  34 , and transverse mandrel lines  36 . The mandrel connections  38  and test pads  40 ,  42 ,  44  may be formed during the multiple patterning process and/or by patterning a conductor layer with lithography and etching processes. 
     The test pad  40  may be used to perform testing of the source contacts  26  and the source regions  22  of the field-effect transistor  12 . The test pad  42  may be used to perform testing of the drain contacts  24  and the drain regions  20  of the field-effect transistor  12 . The test pad  44  may be used to perform testing of the gate contact  28  and the gate structure  18 . During testing, the currents introduced and received at the test pads  40 ,  42 ,  44  travel to and from the gate defined by the gate structure  18  through the gate contact  28 , the drain defined by the drain regions  20  through the drain contacts  24 , and the source defined by the source regions  22  through the source contacts  26  without passing through interconnects in any of the overlying metallization levels, such as interconnects in the M1 metallization level positioned immediately over the metallization level  30  and the vias connecting the metallization level  30  with the immediately-overlying metallization level. Testing via the metallization level  30 , instead of overlying metallization levels of the interconnect structure, may minimize the contribution to the impedance (e.g., electrical resistance) from interconnects in those overlying metallization levels to determinations of contact impedance. The testing process may be accelerated in comparison with conventional testing because testing is performed after forming the metallization level  30 , instead of after forming at least the nearest overlying metallization level. During technology development and manufacturing, feedback from such test structures  10  earlier in the process cycle can assist in reducing the fabrication cost of CMOS chips through earlier identification of failures. 
     With reference to  FIG. 2  and in accordance with alternative embodiments of the invention, each of the mandrel lines  34  of the metallization level  30  may be divided by the cuts  46  such that a section of each mandrel line  34  is arranged on one side of the gate structure  18  and another section of each mandrel line  34  is arranged on one side of the gate structure  18 . The cuts  46  may be centrally arranged, such as a central arrangement directly over the gate structure  18 . The sections of all mandrel lines  34  on one side of the cuts  46  are connected by the mandrel connection  38  with the test pad  40 . These sections of the mandrel lines  34  are connected by the drain contacts  24  with the drain regions  20  of the fins  14 . The sections of all mandrel lines  34  on the opposite side of the cuts  46  are connected by the mandrel connection  38  with the test pad  42 . These sections of the mandrel lines  34  are connected by the source contacts  26  with the source regions  22  of the fins  14 . The test structure  10  may be used in connection with a device-under-testing that is a long-channel field-effect transistor. 
     With reference to  FIG. 3  and in accordance with alternative embodiments of the invention, the non-mandrel lines  32  of the metallization level  30  may also be included as part of the test structure  10  instead of being passive features, and both the non-mandrel lines  32  and mandrel lines  34  may be used in constructing the test structure  10 . The non-mandrel lines  32  may be connected by a transverse non-mandrel line  50  and a non-mandrel connect  52  with the test pad  40 . The non-mandrel lines  32  are connected by the source contacts  26  with the source regions  22  of the fins  14 . The mandrel lines  34  are connected by the mandrel connection  38  with the test pad  42 . The mandrel lines  34  are connected by the drain contacts  24  with the drain regions  20  of the fins  14 . 
     With reference to  FIG. 4  and in accordance with alternative embodiments of the invention, a test structure  60  includes a Kelvin field-effect transistor (i.e., device-under-testing), general indicated by reference numeral  62 , as well as the non-mandrel lines  32 , mandrel lines  34 , transverse mandrel lines  36 , and mandrel connections  38  of the metallization level  30 . The metallization level  30  further includes the test pads  40 ,  42 ,  44  and additional test pads  64 ,  66 ,  68 . The Kelvin field-effect transistor  62  includes multiple fins  14  that are arranged over the active device region  16  and the gate structure  18  that transversely overlaps with the fins  14 , as well as drain regions  20  and source regions  22  associated with the fins  14 . An additional active region with fins (not shown) may be arranged between the active device region  16  and the test pad  44 , and an additional active region with fins (not shown) may be arranged between the active device region  16  and the test pad  68 . 
     Drain regions  20  of multiple fins  14  are connected with the test pad  40 , as described above. Source regions  22  of multiple fins  14  are connected with the test pad  42 , as described above. In an alternative embodiment, the drain region  20  of only one of the fins  14  may be connected with the test pad  40  and the source region  22  of only one of the fins  14  may be connected with the test pad  42 . 
     The drain region  20  of the fin  14  may be connected by the drain contact  24  with the overlying mandrel line  34  that is connected with one of the transverse mandrel lines  36 , which is in turn connected by one of the mandrel connections  38  with the test pad  64 . The drain contact  24  provides a vertical interconnection between the mandrel line  34  and the drain region  20  of the fin  14 . Specifically, the mandrel line  34  associated with the test pad  64  is directly connected by the drain contact  24  with the drain region  20  of one of the fins  14 . 
     The source region  22  of the fin  14  may be connected by the source contact  26  with the overlying mandrel line  34  that is connected with one of the transverse mandrel lines  36 , which is in turn connected by one of the mandrel connections  38  with the test pad  66 . The source contact  26  provides a vertical interconnection between the mandrel line  34  and the source region  22  of the fin  14 . Specifically, the mandrel line  34  associated with the test pad  66  is directly connected by the source contact  26  with the source region  22  of one of the fins  14 . 
     The test pad  40  and test pad  64  may be jointly used to perform testing of the drain regions  20  of the Kelvin field-effect transistor  62 . The test pad  42  and test pad  66  may be jointly used to perform testing of the source regions  22  of the Kelvin field-effect transistor  62 . The test pad  44  and the test pad  68  may be jointly used to perform testing of the gate structure  18  of the Kelvin field-effect transistor  62 . 
     With reference to  FIG. 4A  and in accordance with alternative embodiments of the invention, the Kelvin field-effect transistor  62  may include an additional test pad  70  and additional gate structures  72 ,  74  that are aligned parallel with the gate structure  18  and that also transversely overlap with the fins  14 . The test pads  40 ,  64 , as well as the test pad  68 , may be used to perform testing of the gate structure  72  and drain regions  20  of the Kelvin field-effect transistor  62 . The test pad  42  and test pad  66 , as well as the test pad  70 , may be used to perform Kelvin testing of the gate structure  74  and source regions  22  of the Kelvin field-effect transistor  62 . In an embodiment, the Kelvin field-effect transistor  62  may include exactly seven (7) test pads  40 ,  42 ,  44 ,  64 ,  66 ,  68 ,  70 . 
     The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones. 
     References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/−10% of the stated value(s). 
     References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane. 
     A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.