Patent Publication Number: US-2023132598-A1

Title: Semiconductor device and semiconductor device manufacturing method

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 17/047,236, filed Oct. 13, 2020, now allowed, which is incorporated by reference and is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application PCT/IB2019/053159, filed on Apr. 17, 2019, which is incorporated by reference and claims the benefit of a foreign priority application filed in Japan on Apr. 27, 2018, as Application No. 2018-087261. 
    
    
     TECHNICAL FIELD 
     One embodiment of the present invention relates to a semiconductor material and a semiconductor device. 
     Note that in this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics in general. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each one embodiment of a semiconductor device. It can be sometimes said that a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like includes a semiconductor device. 
     Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, manufacture, or a composition (composition of matter). 
     BACKGROUND ART 
     A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, and an oxide semiconductor has attracted attention as another material. As the oxide semiconductor, not only single-component metal oxides, such as indium oxide and zinc oxide, but also multi-component metal oxides are known. Among the multi-component metal oxides, in particular, an In—Ga—Zn oxide (hereinafter also referred to as IGZO) has been actively studied. 
     From the studies on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are not single crystal nor amorphous, have been found in an oxide semiconductor (see Non-Patent Document 1 to Non-Patent Document 3). Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Moreover, Non-Patent Document 4 and Non-Patent Document 5 show that a fine crystal is included even in an oxide semiconductor which has lower crystallinity than the CAAC structure or the nc structure. 
     In addition, a transistor that uses IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and an LSI and a display utilizing the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8). 
     REFERENCE 
     Non-Patent Document 
     
         
         [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186. 
         [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, pp. 04ED18-1-4ED18-10. 
         [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD&#39;13 Digest of Technical Papers”, 2013, pp. 151-154. 
         [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, pp. Q3012-Q3022. 
         [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, pp. 155-164. 
         [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, pp. 021201-1-021201-7. 
         [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217. 
         [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629. 
       
    
     SUMMARY OF THE INVENTION 
     Problems to be Solved by the Invention 
     An object of one embodiment of the present invention is to inhibit variation in electrical characteristics and shape of a plurality of elements included in a semiconductor device. Another object of one embodiment of the present invention is to inhibit variation in characteristics and element deterioration in a semiconductor device. 
     Another object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long time. Another object of one embodiment of the present invention is to provide a semiconductor device in which a transistor using an oxide semiconductor has stable electrical characteristics and reliability. 
     Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. 
     Another object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed data writing. Another object of one embodiment of the present invention is to provide a novel semiconductor device. 
     Note that the descriptions of these objects do not disturb the existence of other objects. One embodiment of the present invention does not have to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like. 
     Means for Solving the Problems 
     One embodiment of the present invention is a semiconductor device including a first region including a plurality of elements and a second region including a plurality of dummy elements. The second region is provided in an outer edge of the first region. The element and the dummy element each include an oxide semiconductor. 
     One embodiment of the present invention is a semiconductor device including a first region including a plurality of elements, a second region including a plurality of dummy elements, and a third region including a plurality of elements and a dummy element. The second region is provided in an outer edge of the first region and an outer edge of the third region. The element and the dummy element each include an oxide semiconductor. 
     In the above, the element and the dummy element have the same structure, and a structure body included in the element and a structure body included in the dummy element are formed with the same material and provided in the same layer. 
     The semiconductor device is a chip in which the second region is provided in an end portion. 
     In one embodiment of the present invention, a semiconductor device includes, over a substrate, a first region including a plurality of first elements, a second region including a plurality of second elements, and a third region including a plurality of dummy elements between the first region and the second region. The first element, the second element, and the dummy element include an oxide semiconductor. After the first element, the second element, and the dummy element are provided in the same step, the substrate is cut along the third region, thereby forming a first chip including the first region and a second chip including the second region. 
     In the above, the oxide semiconductor includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. 
     Effect of the Invention 
     One embodiment of the present invention can provide a semiconductor device in which variations in electrical characteristics and shape of a plurality of elements included in the semiconductor device is inhibited. 
     According to one embodiment of the present invention, a semiconductor device in which a transistor using an oxide semiconductor has stable electrical characteristics and reliability can be provided. According to one embodiment of the present invention, a semiconductor device that can retains data for a long time can be provided. 
     According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a semiconductor device with high design flexibility can be provided. 
     According to one embodiment of the present invention, a semiconductor device capable of high-speed data writing can be provided. According to one embodiment of the present invention, a semiconductor device capable of reducing power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. 
     Note that the descriptions of the effects do not disturb the existence of other effects. One embodiment of the present invention does not have to have all of these effects. Effects other than these will be apparent from the description of the specification, the drawings, the claims, and the like and effects other than these can be derived from the description of the specification, the drawings, the claims, and the like. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 A and  1 B  A top view and a cross-sectional view of a semiconductor device of one embodiment of the present invention. 
         FIGS.  2 A and  2 B  A top view and a cross-sectional view of a semiconductor device of one embodiment of the present invention. 
         FIGS.  3 A to  3 E  Cross-sectional views of a semiconductor device of one embodiment of the present invention. 
         FIGS.  4 A and  4 B  A top view and a cross-sectional view of a semiconductor device of one embodiment of the present invention. 
         FIGS.  5 A and  5 B  Top views of a semiconductor device of one embodiment of the present invention. 
         FIGS.  6 A to  6 C  Diagrams illustrating a structure example of a transistor of one embodiment of the present invention. 
         FIGS.  7 A to  7 C  Diagrams illustrating a structure example of a transistor of one embodiment of the present invention. 
         FIGS.  8 A to  8 C  Diagrams illustrating a structure example of a transistor of one embodiment of the present invention. 
         FIGS.  9 A to  9 C  Diagrams illustrating a structure example of a transistor of one embodiment of the present invention. 
         FIGS.  10 A to  10 C  Diagrams illustrating a structure example of a transistor of one embodiment of the present invention. 
         FIGS.  11 A and  11 B  Block diagrams illustrating a structure example of a memory device of one embodiment of the present invention. 
         FIGS.  12 A to  12 H  Circuit diagrams each illustrating a structure example of a memory device of one embodiment of the present invention. 
         FIGS.  13 A and  13 B  Schematic diagrams of a semiconductor device of one embodiment of the present invention. 
         FIGS.  14 A to  14 E  Schematic diagrams of memory devices of one embodiment of the present invention. 
         FIGS.  15 A to  15 C  Diagrams illustrating an example of a display device and circuit structure examples of a pixel. 
         FIGS.  16 A and  16 B  Diagrams illustrating circuit structure examples of a pixel. 
         FIGS.  17 A and  17 B  Diagrams each illustrating a structure example of a driver circuit. 
         FIGS.  18 A to  18 C  Diagrams each illustrating an example of a display device. 
         FIGS.  19 A and  19 B  Diagrams each illustrating an example of a display device. 
         FIG.  20    A diagram illustrating an example of a display module. 
         FIGS.  21 A to  21 F  Diagrams each illustrating an electronic device of one embodiment of the present invention. 
         FIGS.  22 A and  22 B  A top view and a cross-sectional view of a semiconductor device of one embodiment of the present invention. 
         FIG.  23    A diagram showing cross sections of semiconductor devices of Example. 
         FIG.  24    A graph showing the depression amount of channel regions of semiconductor devices of Example. 
     
    
    
     MODE FOR CARRYING OUT THE INVENTION 
     Hereinafter, embodiments will be described with reference to the drawings. Note that the embodiments can be implemented with many different modes, and it is readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments. 
     In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. The drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and explanation thereof is not repeated. Furthermore, the same hatch pattern is used for the portions having similar functions, and the portions are not especially denoted by reference numerals in some cases. 
     In this specification, terms for describing arrangement, such as “over” and “under”, are used for convenience in describing a positional relationship between components with reference to drawings. The positional relation between components is changed as appropriate in accordance with a direction in which the components are described. Thus, terms for the description are not limited to those used in this specification, and the description can be rephrased appropriately depending on the situation. 
     In this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor has a channel formation region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel formation region, and the source. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows. 
     Furthermore, functions of a source and a drain might be switched when a transistor of opposite polarity is employed or a direction of current flow is changed in circuit operation, for example. Thus, the terms of source and drain are interchangeably used in this specification and the like. 
     In this specification and the like, “electrically connected” includes the case where connection is made through an “object having any electric function”. Here, there is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between the connected components. Examples of the “object having any electric function” include a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements having a variety of functions as well as an electrode and a wiring. 
     Note that in this specification and the like, a nitride oxide refers to a compound that includes more nitrogen than oxygen. An oxynitride refers to a compound that includes more oxygen than nitrogen. The content of each element can be measured by Rutherford backscattering spectrometry (RBS), for example. 
     In this specification and the like, “parallel” indicates a state where two straight lines are placed at an angle of greater than or equal to −10° and less than or equal to 10°. Thus, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. In addition, the term “substantially parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −30° and less than or equal to 30°. Moreover, “perpendicular” indicates a state where two straight lines are placed at an angle of greater than or equal to 80° and less than or equal to 100°. Thus, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. Furthermore, “substantially perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 60° and less than or equal to 120°. 
     Note that in this specification, a barrier film means a film having a function of inhibiting the passage of oxygen and impurities such as hydrogen, and the barrier film having conductivity is referred to as a conductive barrier film in some cases. 
     In this specification and the like, a transistor having normally-on characteristics is a transistor that is on when no potential (0 V) is applied by a power supply. For example, the normally-on characteristics of a transistor mean, in some cases, electrical characteristics in which current (Id) flows between a drain and a source when a voltage applied to a gate of the transistor (Vg) is 0 V. 
     In this specification and the like, an oxide semiconductor is a type of metal oxide. A metal oxide means an oxide including a metal element. A metal oxide exhibits insulating properties, semiconductor properties, or conductivities depending on its composition or formation method. A metal oxide exhibiting semiconductor properties is referred to as a metal oxide semiconductor or an oxide semiconductor (or simply OS). A metal oxide exhibiting insulating properties is referred to as a metal oxide insulator or an oxide insulator. A metal oxide exhibiting conductivities is referred to as a metal oxide conductor or an oxide conductor. In other words, a metal oxide used in a channel formation region or the like of a transistor can be referred to as an oxide semiconductor. 
     Embodiment 1 
     In this embodiment, a semiconductor device including an element using an oxide semiconductor, which is one embodiment of the present invention, is described with reference to  FIG.  1    to  FIG.  5   . 
     Examples of the above element using an oxide semiconductor include a switching element (a transistor or the like), a capacitor, an inductance element, a memory element, and a display element (a light-emitting element or the like). 
     A metal oxide containing indium is preferably used as the oxide semiconductor. For example, a metal oxide such as an In-M-Zn oxide (the element M is one kind or a plurality of kinds selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, hafnium, tantalum, tungsten, magnesium, and the like) can be used. Furthermore, as the oxide semiconductor, an In—Ga oxide or an In—Zn oxide may be used. 
     For example, a transistor using an oxide semiconductor in a region where a channel is formed has an extremely low leakage current in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. 
     Furthermore, by using an oxide semiconductor, a variety of elements can be stacked and three-dimensionally integrated. In other words, an oxide semiconductor can be deposited by a sputtering method or the like; therefore, a three-dimensional integrated circuit (a 3D integrated circuit) in which a circuit is developed not only on a flat surface of a substrate but also in a perpendicular direction can be obtained. 
     In contrast, with an increase in integration degree of the semiconductor device, in some cases, loading effect occurs in which the etching rate and the etched shape change depending on the proportion of an opening area (an etched area) to the whole area in the mask, the partial pattern density of the openings in the mask, and the like. 
     Note that in this specification, the pattern density is the area ratio of a structure body formed in a given region. In the case where a conductive film is deposited on an entire surface in a given region, for example, the pattern density is 100%. On the other hand, in the case where part of the conductive film is removed to form a plurality of conductors, the pattern density of the conductors can be obtained by dividing the area of the remaining conductors by the area of the given region. 
     Specifically, description is made with reference to  FIG.  2    and  FIG.  3   .  FIG.  2 (A)  is a top view of a semiconductor device.  FIG.  2 (B)  is a cross-sectional view of a portion indicated by a dashed-dotted line A 1 -A 2  in  FIG.  2 (A) . For clarity of the drawing, some components are not illustrated in  FIG.  2    and  FIG.  3   . 
     As illustrated in  FIG.  2   , over a substrate  10 , there are a region  12  which has high pattern density and includes a structure body  28  functioning as an interlayer film and a plurality of elements  22  and a region  13  which has low pattern density and includes only the structure body  28  functioning as an interlayer film, not including the element. 
     Note that the element  22  in the drawing is a simplified element including an oxide semiconductor. The structure body  28  including an oxide that contains more oxygen than that in the stoichiometric composition is provided in the vicinity of the plurality of elements  22 . 
       FIG.  3 (A) ,  FIG.  3 (B) , and  FIG.  3 (C)  schematically illustrate a process in which a structure body included in the element  22  or a film  23  to be an interlayer film and a film  27  are deposited over the substrate  10 , and the film  27  was processed by a dry etching method using a mask  29  to expose the film  23 .  FIG.  3 (D)  schematically illustrates a step of depositing a film  26 A to be the structure body included in the element  22 .  FIG.  3 (E)  schematically illustrates a state in which the film  26 A is processed to form a structure body  26  in openings in the film  27  and the film  23 . 
     Just before the etching, radicals (indicated by white dots in the drawing) are uniformly diffused over the substrate  10 . Here, when etching treatment is started, the consumed amount of radicals is large in the region  12  where the etched area is large, and the consumed amount of radicals is small in the region  13  where the etched area is small, as illustrated in  FIG.  3 (A) . That is, the amount of radicals over the region  12  is smaller than that over the region  13 , and thus the etching rate of a region near the center of the region  12  becomes low. On the other hand, a region in the region  12  adjacent to the region  13 , radicals over the region  13  are consumed, and thus the etching rate becomes high. 
     As illustrated in  FIG.  3 (B) , products generated from the film  27  (indicated by black dots in the drawing) are released when the etching treatment proceeds, and thus the amount of radicals over the region  12  is further reduced. On the other hand, products from the film  27  are not generated over the region  13 , and thus a change in the amount of radicals is small. Thus, the etching rate of the region near the center of the region  12  is likely to be further reduced. On the other hand, in the region in the region  12  adjacent to the region  13 , radicals over the region  13  are consumed, and thus the etching rate is further increased. 
     Thus, as illustrated in  FIG.  3 (C) , when the film  27  is processed to expose the film  23  in the region near the center of the region  12 , the film  23  positioned below the film  27  is partly removed to an unintended extent (hereinafter also referred to as the depression amount or the amount of a reduction in a film thickness) in the region in the region  12  adjacent to the region  13 . 
     As illustrated in  FIG.  3 (D) , the film  26 A to be the structure body included in the element  22  is deposited. After that, as illustrated in  FIG.  3 (E) , when the structure body  26  is formed, abnormality in shape of the structure body  26  occurs in the case where excess depression occurs in the region in the region  12  adjacent to the region  13 . In other words, due to the abnormality in shape of the structure body  26 , the probability of occurrence of variations in characteristics of the plurality of elements  22  becomes high. 
     In the case where the film  23  is used as the structure body of the element  22 , deterioration in characteristics of the element  22  might be caused by an excess reduction in the film thickness in the region in the region  12  adjacent to the region  13 . That is, the film  23  in the region in the region  12  adjacent to the region  13  is exposed earlier than the film  23  in the region near the center of the region  12 . Accordingly, in the region in the region  12  adjacent to the region  13 , the film  23  is exposed to plasma for a longer time and damage to the film  23  is more accumulated than in the region near the center of the region  12 . That is, it is highly possible that the element  22  formed in the region  12  adjacent to the region  13  has worse characteristics than the element  22  formed in the region near the center of the region  12 . 
     A transistor using an oxide semiconductor is likely to have normally-on characteristics (characteristics in which a channel exists without voltage application to a gate electrode and current flows in a transistor) owing to an impurity (typically, hydrogen, water, and the like) and an oxygen vacancy in the oxide semiconductor that affect the electrical characteristics. In the case where the transistor is driven in the state where excess oxygen exceeding the proper amount is included in the oxide semiconductor, the valence of the excess oxygen atoms is changed and the electrical characteristics of the transistor are changed, so that reliability is decreased in some cases. 
     Therefore, it is preferable to use, as the oxide semiconductor used in the transistor, a highly purified intrinsic oxide semiconductor that does not include an impurity, an oxygen vacancy, and oxygen in excess of oxygen in the stoichiometric composition (hereinafter, also referred to as excess oxygen). 
     However, in the transistor using the oxide semiconductor, oxygen in the oxide semiconductor may be absorbed by a conductor forming the transistor or a conductor used for a plug or a wiring connected to the transistor, and thus oxygen vacancies may be generated in the oxide semiconductor in some cases. For example, in the case where heat treatment is performed in forming the transistor, oxygen in the oxide semiconductor may be absorbed by a conductor forming the transistor due to the heat treatment. 
     Oxygen vacancies may be generated in the oxide semiconductor by process damage when the transistor is formed. In a heating process when the transistor is formed, for example, oxygen in the oxide semiconductor may be absorbed by a conductor forming the transistor or a conductor used for a plug or a wiring connected to the transistor, and thus oxygen vacancies may be generated in the oxide semiconductor in some cases. 
     Therefore, it is preferable to provide, in the vicinity of the oxide semiconductor of the transistor, a component including an oxide that contains more oxygen than that in the stoichiometric composition. For example, in the oxide, a region containing oxygen in excess of that in the stoichiometric composition (hereinafter also referred to as an excess oxygen region) is preferably formed. Specifically, an excess oxygen region is preferably provided in an interlayer film or the like positioned near the transistor. 
     With the above structure, excess oxygen of the component including the excess oxygen region is diffused into oxygen vacancies generated in the oxide semiconductor, whereby the oxygen vacancies can be compensated for. On the other hand, in the case where the amount of diffused excess oxygen of the structure body including the excess oxygen region exceeds the proper value, the oversupplied oxygen might cause a change in the structure of the oxide semiconductor. 
     In view of the above, in one embodiment of the present invention, a dummy element (hereinafter also referred to as a sacrificial element) is provided between a sparse circuit region and a dense circuit region, whereby variations in characteristics of a plurality of elements formed in the dense circuit region are inhibited. 
     The above dummy element is formed in the same step as an element having a circuit function. Thus, the dummy element is provided in the same layer as the element having a circuit function. At least one of structure bodies included in the dummy element is formed using the same material as a structure body included in the element having a circuit function. Note that the dummy element preferably has the same structure as the element having a circuit function. 
     Specifically, description is made with reference to  FIG.  1   .  FIG.  1 (A)  is a top view of the semiconductor device.  FIG.  1 (B)  is a cross-sectional view of a portion indicated by a dashed-dotted line A 1 -A 2  in  FIG.  1 (A) . For clarity of the drawing, some components are not illustrated in  FIG.  1   . 
     As illustrated in  FIG.  1   , over the substrate  10 , there are the region  12  which has high pattern density and includes a structure body  28  functioning as an interlayer film and a plurality of elements  22 , a region  13  which includes the structure body  28  functioning as an interlayer film and not include the element, and a region  11  which includes the structure body  28  functioning an interlayer film and a plurality of dummy elements  21  and is provided between the region and the region  12 . 
     Although the plurality of structure bodies corresponding to the dummy elements  21  are hatched for easy understanding, the dummy element  21  preferably has the same structure as the element  22 . The structure body  28  including an oxide containing more oxygen than that in the stoichiometric composition is provided in the vicinity of the plurality of elements  22  and the dummy elements  21 . 
     By providing the region  11  including the dummy element  21  in the outer edge of the region  12 , abnormality in shape of the plurality of elements  22  formed in the region  12  and variations in characteristics thereof can be inhibited. 
     In other words, the process is designed to target the elements  22  provided in the region  12  while the elements provided in the region  11  where the processing speed is high are the dummy elements  21 , whereby variations in the shape and characteristics of the element  22  operating as a semiconductor device can be inhibited. 
     Alternatively, for example, in the case where the structure body  28 , which is illustrated in  FIG.  2    and does not include the region  11 , includes an excess oxygen region uniformly, it is highly possible that the amount of oxygen diffused to the element  22  is different between the region near the center of the region  12  and the region in the region  12  adjacent to the region  13 . 
     For example, in the case where design is made to target the characteristics of the element  22  provided in the region near the center of the region  12 , excess oxygen included in the element  13  is diffused into the region in the region  12  adjacent to the region  13  in a step of heat treatment that prompts diffusion of excess oxygen; thus, in the element  22  provided in the region in the region  12  adjacent to the region  13 , the amount of oxygen for compensation might be excess. 
     In other words, it is highly possible that oxygen diffuses into the element  22  in the region in the region  12  adjacent to the region  13  excessively beyond the proper value. 
     Here, as illustrated in  FIG.  1   , the region  11  including the plurality of dummy elements  21  is provided in the outer edge of the region  12  which has high pattern density and includes the plurality of elements  22 , whereby variations in characteristics of the plurality of elements  22  provided in the region  12  can be inhibited. 
     That is, in the case where the structure bodies  28  including an oxide containing more oxygen than that in the stoichiometric composition are provided in the region  12 , the region  11 , and the region with a small element density, by disposing the region  11  between the region  12  and the region with a small element density, excess oxygen diffused from the structure body  28  provided in the region with a small element density is absorbed by the dummy element  21  and can be prevented from being diffused into the region  12 . 
     In the case where the region  11  including the dummy elements  21  is provided in the outer edge of the region  12 , impurities (typically, hydrogen, water, and the like) diffused from the outside of the semiconductor device are absorbed by the structural body included in the dummy element  21 . In other words, the impurities are trapped by the dummy element  21 , whereby the impurities can be inhibited from being diffused into the element  22 . Thus, the element  22  can have improved reliability. 
     Thus, a variation in electrical characteristics of the transistor can be inhibited. In addition, a transistor having high reliability can be provided. Moreover, abnormality in shape of the transistor and electrostatic breakdown can be inhibited. Accordingly, the yield is improved, and thus the productivity of the semiconductor device can be increased. 
     Structure Example 2 of Semiconductor Device 
     Another example of a semiconductor device including an element using an oxide semiconductor, which is one embodiment of the present invention according to one embodiment of the present invention is described below with reference to  FIG.  4   . 
     Note that in the semiconductor device illustrated in  FIG.  4   , components having the same functions as the components included in the semiconductor device described in the above-described structure examples are denoted by the same reference numerals. 
     Specifically,  FIG.  4 (A)  is a top view of the semiconductor device formed over the substrate  15  before the dicing process.  FIG.  4 (B)  is a cross-sectional view of a portion indicated by a dashed-dotted line A 1 -A 2  in  FIG.  4 (A) . 
     As the substrate  15 , a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used, for example. A plurality of circuit regions  16  are provided over the substrate  15 . In addition, over the substrate  15 , a plurality of separation regions  18  indicated by dashed double-dotted lines are provided. The circuit region  16  includes the region  12  having high pattern density of the elements  22  and the region  11  including the dummy element  21 . 
     The regions  12  in one circuit region  16  and the regions  12  in another circuit region  16  are provided with the separation region  18  positioned therebetween. Separation lines (also referred to as “dicing lines”) are set at a position overlapping with the separation regions  18 . The substrate  15  is cut along the separation lines, whereby chips including the region  12  can be cut out from the substrate  15 . 
     Here, the separation region  18  preferably includes the region  11  including the dummy element  21 . When the region  11  serves as a separation region, the region  12  can be designed large; thus, higher integration can be achieved. 
     When the separation region  18  includes the region  11 , a conductive layer and a semiconductor layer included in the dummy element  21  can relieve ESD that might be caused in a dicing step, which can prevent a reduction in yield due to the dicing step. 
     A dicing step is generally performed while carbonated water whose specific resistance is lower than that of pure water is supplied to a cut portion, in order to cool down a substrate, remove swarf, and prevent electrification, for example. Providing a conductive layer, a semiconductor layer, or the like in the separation region  18  allows a reduction in the usage of the pure water. Therefore, the manufacturing cost of the semiconductor device can be reduced. Furthermore, productivity of the semiconductor device can be increased. 
     Impurities such as water entering from the separation region  18  are trapped by the dummy element  21 , which can inhibit a decrease in reliability. 
     Structure Example 3 of Semiconductor Device 
     Another example of a semiconductor device including an element using an oxide semiconductor of one embodiment of the present invention is described below with reference to  FIG.  5   . Note that  FIGS.  5 (A) and  5 (B)  are top views of the semiconductor device formed over the substrate  10 . 
     Note that in the semiconductor device illustrated in  FIG.  5   , structures having the same functions as the structures included in the semiconductor device described in the above structure example are denoted by the same reference numerals. 
     In a semiconductor device, a plurality of circuits having different functions may be provided over the same substrate in some cases. Here, the density of elements or wirings required for forming the circuit varies depending on a required circuit structure. Specifically, as illustrated in  FIG.  5 (B) , there arises a difference in density of arrangement of elements and wirings (hereinafter also referred to as a layout in a circuit region) between a circuit region having regular arrangement and high integration (corresponds to the region  12  in the drawing), which is typified by a memory cell or a pixel region, and a circuit region (corresponds to a region  14  in the drawing) whose layout is determined as needed by, for example, a driver circuit or a correction circuit. Since elements are not formed in the region  13  that is the outer edge of the circuit region, the difference in pattern density between the region  13  and the region  12  is large. 
     Thus, as illustrated in  FIG.  5 (A) , the sparse region  14  is provided with the dummy elements  21  to have the density of the elements equal to that of the region  12 , so that the difference in pattern density of the layout in the circuit region is decreased. Note that in this specification, the description “one value is equal to another value” does not necessarily mean that they are exactly equal to each other. In the range of common technical knowledge, they can be substantially the same, equivalent, or approximate. 
     A difference in the pattern density of the layout in the circuit region is made small such that processing abnormality or electrostatic breakdown is less likely to be caused, or the pattern densities in the circuit regions are made equal, whereby variations in characteristics of elements and abnormality in the shape can be inhibited. 
     Alternatively, the difference in the pattern density of the layout in the circuit region is made low such that a difference in the amount of excess oxygen diffused into one element arranged in each region is less likely to be generated, or the pattern densities in the circuit regions are made equal. With this structure, the amount of excess oxygen diffused into the element included in each of the plurality of regions can be controlled. 
     For example, as for one component, even in the case where the average pattern density over an entire substrate is 40%, the pattern density may be 70% in one region of the substrate, and the pattern density may be 10% in the other region of the substrate. Accordingly, the region with a pattern density of 10% is a sparse region, and thus the dummy element  21  is preferably formed such that the pattern density is approximately 70%. In other words, in the case where the dummy element  21  is not arranged, the average pattern density over the entire substrate is d ave  %, the pattern density in a region whose pattern density is higher than d ave  % is d high  %, and the pattern density in a region whose pattern density is lower than d ave  % is d low  %. It is preferable that the dummy element  21  be provided in the region whose pattern density is d low  % and thus the pattern density be higher than or equal to d ave  %, preferably d high  %. 
     With this structure, in the case where the component  28  uniformly includes an excess oxygen region, the amount of oxygen diffused into one element  22  is equivalent for the element  22  arranged in the region  12  and the plurality of elements  22  arranged in the region  14 . Accordingly, a variation in element characteristics is inhibited in the region  12  and the region  14 , and the element  22  with high reliability can be provided. 
     Furthermore, by arrangement of the dummy element  21 , impurities (typically, hydrogen, water, and the like) in an oxide semiconductor may be absorbed by a conductor included in the dummy element  21  because of heat conditions for a group of treatment of heat application (note that a budget of heat conditions for the group of treatment of heat application is also referred to as a thermal budget. In other words, the impurities are trapped by the dummy element  21 , whereby the impurities can be inhibited from being diffused into the element  22 . Thus, the element  22  can have improved reliability. 
     Thus, a variation in electrical characteristics of the transistor can be inhibited. In addition, a transistor having high reliability can be provided. Moreover, abnormality in shape of the transistor and electrostatic breakdown can be inhibited. Accordingly, the yield is improved, and thus the productivity of the semiconductor device can be increased. 
     A highly integrated semiconductor device can be used easily. A semiconductor device including a transistor with a high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, a semiconductor device that has small variations in electrical characteristics, stable electrical characteristics, and high reliability can be provided. 
     The structure, composition, method, and the like described above in this embodiment can be used in appropriate combination with the structures, compositions, methods, and the like described in the other embodiments, examples, and the like. 
     Embodiment 2 
     In this embodiment, structure examples of the transistor described in the above embodiment are described. 
     Transistor Structure Example 1 
     A structure example of a transistor  200 A is described with reference to  FIGS.  6 (A) to  6 (C) .  FIG.  6 (A)  is a top view of the transistor  200 A.  FIG.  6 (B)  is a cross-sectional view of a portion indicated by a dashed-dotted line L 1 -L 2  in  FIG.  6 (A) .  FIG.  6 (C)  is a cross-sectional view of a portion indicated by a dashed-dotted line W 1 -W 2  in  FIG.  6 (A) . Note that for clarification of the drawing, some components are not illustrated in the top view of  FIG.  6 (A) . 
       FIGS.  6 (A) to  6 (C)  illustrate the transistor  200 A and an insulator  210 , an insulator  212 , an insulator  214 , an insulator  216 , an insulator  280 , an insulator  282 , and an insulator  284  that function as interlayer films. In addition, a plug  246  (a plug  246   s  and a plug  246   d ) that is electrically connected to the transistor  200 A and functions as a contact plug, and a conductor  203  functioning as a wiring are illustrated. 
     The transistor  200 A includes the conductor  260  (a conductor  260   a  and a conductor  260   b ) functioning as a first gate (also referred to as top gate) electrode; the conductor  205  (a conductor  205   a  and a conductor  205   b ) functioning as a second gate (also referred to as bottom gate) electrode; an insulator  250  functioning as a first gate insulator; an insulator  220 , an insulator  222 , and an insulator  224  functioning as a second gate insulator; the oxide  230  (an oxide  230   a , an oxide  230   b , and an oxide  230   c ) including a region where a channel is formed; a conductor  240   s  functioning as one of a source and a drain; a conductor  240   d  functioning as the other of the source and the drain; and an insulator  274 . 
     The insulator  210  and the insulator  212  function as interlayer films. 
     As the interlayer film, a single layer or stacked layers of an insulator such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3  (BST) can be used. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators, for example. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator. 
     For example, the insulator  210  preferably functions as a barrier film that inhibits entry of impurities such as water or hydrogen into the transistor  200 A from the substrate side. Accordingly, for the insulator  210 , it is preferable to use an insulating material that has a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom (through which the above impurities do not easily pass). Alternatively, it is preferable to use an insulating material that has a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (through which the above oxygen does not easily pass). Moreover, aluminum oxide or silicon nitride, for example, may be used for the insulator  210 . This structure can inhibit diffusion of impurities such as water or hydrogen to the transistor  200 A side from the substrate side of the insulator  210 . 
     For example, the permittivity of the insulator  212  is preferably lower than that of the insulator  210 . When a material with a low permittivity is used for the interlayer film, the parasitic capacitance generated between wirings can be reduced. 
     The conductor  203  is formed to be embedded in the insulator  212 . Here, the level of the top surface of the conductor  203  and the level of the top surface of the insulator  212  can be substantially the same. Note that although a structure in which the conductor  203  is a single layer is illustrated, the present invention is not limited thereto. For example, the conductor  203  may have a multilayer structure of two or more layers. Note that for the conductor  203 , a conductive material that has high conductivity and contains tungsten, copper, or aluminum as its main component is preferably used. 
     In the transistor  200 A, the conductor  260  sometimes functions as a first gate electrode. The conductor  205  sometimes functions as a second gate electrode. In that case, the threshold voltage of the transistor  200 A can be controlled by changing a potential applied to the conductor  205  independently of a potential applied to the conductor  260 . In particular, the threshold voltage of the transistor  200 A can be higher than 0 V and the off-state current can be reduced by applying a negative potential to the conductor  205 . Thus, a drain current at the time when a potential applied to the conductor  260  is 0 V can be lower in the case where a negative potential is applied to the conductor  205  than in the case where a negative potential is not applied. 
     For example, when the conductor  205  and the conductor  260  overlap with each other, in the case where a potential is applied to the conductor  260  and the conductor  205 , an electric field generated from the conductor  260  and an electric field generated from the conductor  205  are connected and can cover a channel formation region formed in the oxide  230 . 
     That is, the channel formation region can be electrically surrounded by the electric field of the conductor  260  functioning as the first gate electrode and the electric field of the conductor  205  functioning as the second gate electrode. In this specification, a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure. 
     Like the insulator  210  or the insulator  212 , the insulator  214  and the insulator  216  function as interlayer films. For example, the insulator  214  preferably functions as a barrier film that inhibits entry of impurities such as water or hydrogen into the transistor  200 A from the substrate side. This structure can inhibit diffusion of impurities such as water or hydrogen to the transistor  200 A side from the substrate side of the insulator  214 . Moreover, for example, the insulator  216  preferably has a lower permittivity than the insulator  214 . When a material with a low permittivity is used for the interlayer film, the parasitic capacitance generated between wirings can be reduced. 
     In the conductor  205  functioning as the second gate electrode, the conductor  205   a  is formed in contact with an inner wall of an opening in the insulator  214  and the insulator  216 , and the conductor  205   b  is formed further inside. Here, the top surfaces of the conductor  205   a  and the conductor  205   b  and the top surface of the insulator  216  can be substantially level with each other. Although the transistor  200 A having a structure in which the conductor  205   a  and the conductor  205   b  are stacked is illustrated, the present invention is not limited thereto. For example, the conductor  205  may have a single-layer structure or a stacked-layer structure of three or more layers. 
     Here, for the conductor  205   a , a conductive material that has a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom (through which the above impurities are less likely to pass) is preferably used. Alternatively, it is preferable to use a conductive material that has a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (the above oxygen is less likely to pass). Note that in this specification, a function of inhibiting diffusion of impurities or oxygen means a function of inhibiting diffusion of any one or all of the impurities and the oxygen. 
     For example, when the conductor  205   a  has a function of inhibiting diffusion of oxygen, a reduction in conductivity of the conductor  205   b  due to oxidation can be inhibited. 
     In the case where the conductor  205  doubles as a wiring, the conductor  205   b  is preferably formed using a conductive material that has high conductivity and contains tungsten, copper, or aluminum as its main component. In that case, the conductor  203  is not necessarily provided. Note that the conductor  205   b  is illustrated as a single layer but may have a stacked-layer structure, for example, a stack of any of the above conductive materials and titanium or titanium nitride. 
     The insulator  220 , the insulator  222 , and the insulator  224  function as a second gate insulator. 
     Here, it is preferable that oxygen be released from the insulator  224  in contact with the oxide  230  by heating. In this specification, oxygen that is released by heating is referred to as excess oxygen in some cases. For example, silicon oxide, silicon oxynitride, or the like is used for the insulator  224  as appropriate. When an insulator containing oxygen is provided in contact with the oxide  230 , oxygen vacancies in the oxide  230  can be reduced and the reliability of the transistor  200 A can be improved. 
     As the insulator  224 , specifically, an oxide material that releases part of oxygen by heating is preferably used. An oxide that releases oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen molecules is greater than or equal to 1.0×10 18  molecules/cm 3 , preferably greater than or equal to 1.0×10 19  molecules/cm 3 , further preferably greater than or equal to 2.0×10 19  molecules/cm 3  or greater than or equal to 3.0×10 20  molecules/cm 3  in TDS (Thermal Desorption Spectroscopy) analysis. Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 400° C. 
     The insulator  222  preferably has a barrier property. The insulator  222  having a barrier property functions as a layer that inhibits entry of impurities such as hydrogen into the transistor  200 A from the surroundings of the transistor  200 A. 
     For the insulator  222 , a single layer or stacked layers of an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3  (BST) are preferably used, for example. As miniaturization and high integration of transistors progress, a problem such as leakage current may arise because of a thinner gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a gate potential during operation of the transistor can be reduced while the physical thickness is maintained. 
     For example, it is preferable that the insulator  220  be thermally stable. For example, silicon oxide and silicon oxynitride have thermal stability. Thus, when silicon oxide and silicon oxynitride are used for the insulator  220  and a high-k material is used for the insulator  222 , a combination of the insulator  220  and the insulator  222  can achieve a thermally stable stacked-layer structure having a high dielectric constant. 
     Note that the second gate insulating layer is shown to have a three-layer stacked structure in  FIG.  6   , but may have a single-layer structure or a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. 
     The oxide  230  including a region functioning as the channel formation region includes the oxide  230   a , the oxide  230   b  over the oxide  230   a , and the oxide  230   c  over the oxide  230   b . Including the oxide  230   a  under the oxide  230   b  makes it possible to inhibit diffusion of impurities into the oxide  230   b  from the components formed below the oxide  230   a . Moreover, including the oxide  230   c  over the oxide  230   b  makes it possible to inhibit diffusion of impurities into the oxide  230   b  from the components formed above the oxide  230   c . As the oxide  230 , a later-described oxide semiconductor, which is one kind of metal oxide, can be used. 
     The transistor  200 A illustrated in  FIG.  6    includes regions where the conductors  240  (the conductor  240   s  and the conductor  240   d ) overlap with the oxide  230   c , the insulator  250 , and the conductor  260 . With this structure, a transistor having a high on-state current can be provided. Moreover, a transistor having high controllability can be provided. 
     One of the conductors  240  functions as a source electrode and the other functions as a drain electrode. 
     For the conductor  240 , a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten or an alloy containing any of the metals as its main component can be used. In particular, a metal nitride film of tantalum nitride or the like is preferable because it has a barrier property against hydrogen or oxygen and its oxidation resistance is high. 
     Although  FIG.  6    illustrates the conductor  240  with a single-layer structure, a stacked-layer structure of two or more layers may be employed. For example, it is preferable to stack a tantalum nitride film and a tungsten film. Alternatively, a titanium film and an aluminum film may be stacked. Further alternatively, a two-layer structure where an aluminum film is stacked over a tungsten film, a two-layer structure where a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure where a copper film is stacked over a titanium film, or a two-layer structure where a copper film is stacked over a tungsten film may be employed. 
     A three-layer structure consisting of a titanium film or a titanium nitride film, an aluminum film or a copper film stacked over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film formed thereover; a three-layer structure consisting of a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film stacked over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film formed thereover; or the like may be employed. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. 
     A barrier layer may be provided over the conductor  240 . The barrier layer is preferably formed using a material having a barrier property against oxygen or hydrogen. This structure can inhibit oxidation of the conductor  240  at the time of deposition of the insulator  274 . 
     A metal oxide can be used for the barrier layer, for example. In particular, an insulating film of aluminum oxide, hafnium oxide, gallium oxide, or the like, which has a barrier property against oxygen and hydrogen, is preferably used. Alternatively, silicon nitride formed by a CVD method may be used. 
     With the barrier layer, the range of choices for the material of the conductor  240  can be expanded. For example, a material having a low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used for the conductor  240 . Moreover, for example, a conductor that can be easily deposited or processed can be used. 
     The insulator  250  functions as the first gate insulator. 
     As miniaturization and high integration of transistors progress, a problem such as leakage current may arise because of thinner gate insulators. In that case, the insulator  250  may have a stacked-layer structure like the second gate insulator. When the insulator functioning as the gate insulator has a stacked-layer structure of a high-k material and a thermally stable material, a gate potential during operation of the transistor can be reduced while the physical thickness is maintained. Furthermore, the stacked-layer structure can be thermally stable and have a high dielectric constant. 
     The conductor  260  functioning as a first gate electrode includes the conductor  260   a  and the conductor  260   b  over the conductor  260   a . Like the conductor  205   a , the conductor  260   a  is preferably formed using a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). 
     When the conductor  260   a  has a function of inhibiting oxygen diffusion, the range of choices for the material of the conductor  260   b  can be expanded. That is, the conductor  260   a  inhibits oxidation of the conductor  260   b , thereby preventing the decrease in conductivity. 
     As a conductive material having a function of inhibiting diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. For the conductor  260   a , the oxide semiconductor that can be used as the oxide  230  can be used. In that case, when the conductor  260   b  is deposited by a sputtering method, the conductor  260   a  can have a reduced electric resistance to be a conductor. This can be referred to as an OC (Oxide Conductor) electrode. 
     The conductor  260  functions as a wiring and thus is preferably formed using a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used for the conductor  260   b . The conductor  260   b  may have a stacked-layer structure, for example, a stack of any of the above conductive materials and titanium or titanium nitride. 
     The insulator  274  is preferably provided to cover the top surface and a side surface of the conductor  260 , a side surface of the insulator  250 , and the side surface of the oxide  230   c . For the insulator  274 , an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water or hydrogen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. Moreover, it is possible to use, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide or silicon nitride oxide, silicon nitride, or the like. 
     The insulator  274  can inhibit oxidation of the conductor  260 . Moreover, the insulator  274  can inhibit diffusion of impurities such as water or hydrogen contained in the insulator  280  into the transistor  200 A. 
     The insulator  280 , the insulator  282 , and the insulator  284  function as interlayer films. 
     Like the insulator  214 , the insulator  282  preferably functions as a barrier insulating film that inhibits entry of impurities such as water or hydrogen into the transistor  200 A from the outside. 
     Like the insulator  216 , the insulator  280  and the insulator  284  preferably have a lower permittivity than the insulator  282 . When a material with a low permittivity is used for the interlayer films, the parasitic capacitance generated between wirings can be reduced. 
     The transistor  200 A may be electrically connected to another component through a plug or a wiring such as the plug  246  embedded in the insulator  280 , the insulator  282 , and the insulator  284 . 
     As a material for the plug  246 , a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or stacked layers, as in the conductor  205 . For example, it is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance. 
     For example, when the plug  246  has a stacked-layer structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten, which has high conductivity, diffusion of impurities from the outside can be inhibited while the conductivity of a wiring is maintained. 
     An insulator  276  (an insulator  276   a  and an insulator  276   b ) having a barrier property may be provided between the plug  246  and the insulator  280 . Providing the insulator  276  can prevent oxygen in the insulator  280  from reacting with the plug  246  and oxidizing the plug  246 . 
     Furthermore, with the insulator  276  having a barrier property, the range of choices for the material of the conductor used as the plug or the wiring can be expanded. The use of a metal material having an oxygen absorbing property and high conductivity for the plug  246 , for example, can provide a semiconductor device with low power consumption. Specifically, a material having a low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used. Moreover, for example, a conductor that can be easily deposited or processed can be used. 
     With the above structure, a semiconductor device including a transistor with a high on-state current can be provided. Alternatively, a semiconductor device including a transistor with a low off-state current can be provided. Alternatively, a semiconductor device that has small variations in electrical characteristics, stable electrical characteristics, and high reliability can be provided. 
     &lt;Materials&gt; 
     [Substrate] 
     Although there is no particular limitation on a material used for a substrate, it is required to have heat resistance high enough to withstand at least heat treatment performed later. For example, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate using silicon, silicon carbide, or the like as a material or a compound semiconductor substrate using silicon germanium or the like as a material can be used as the substrate. Furthermore, an SOI substrate, a semiconductor substrate on which a semiconductor element such as a strained transistor or a FIN-type transistor is provided, or the like can be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like that can be used for a high electron mobility transistor (HEMT) may be used. That is, the substrate is not limited to a simple supporting substrate and may be a substrate where a device such as another transistor is formed. 
     Furthermore, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used as the substrate. Note that a flexible substrate may be used as the substrate. In the case where a flexible substrate is used, a transistor, a capacitor, or the like may be directly fabricated over the flexible substrate, or a transistor, a capacitor, or the like may be fabricated over another fabrication substrate and then separated therefrom and transferred onto the flexible substrate. Note that to perform separation from the fabrication substrate and transfer to the flexible substrate, a separation layer is preferably provided between the fabrication substrate and the transistor, the capacitor, or the like. 
     For the flexible substrate, for example, a metal, an alloy, a resin, glass, or fiber thereof can be used. The flexible substrate used as the substrate preferably has a lower coefficient of linear expansion because deformation due to an environment is inhibited. For the flexible substrate used as the substrate, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10 −3 /K, lower than or equal to 5×10 −5 /K, or lower than or equal to 1×10 −5 /K is used. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is suitable for the flexible substrate because of its low coefficient of linear expansion. 
     [Insulator] 
     For the insulator, a single layer or a stack of a material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, and the like is used. A material in which a plurality of materials selected from an oxide material, a nitride material, an oxynitride material, and a nitride oxide material are mixed may be used. 
     Note that in this specification and the like, a nitride oxide refers to a compound in which the nitrogen content is higher than the oxygen content. An oxynitride refers to a compound in which the oxygen content is higher than the nitrogen content. The content of each element can be measured by Rutherford backscattering spectrometry (RBS), for example. 
     When an oxide semiconductor, which is one kind of metal oxide, is used for the semiconductor layer, the hydrogen concentration in the insulator is preferably lowered in order to prevent an increase in the hydrogen concentration in the semiconductor layer. Specifically, the hydrogen concentration in the insulator is lower than or equal to 2×10 20  atoms/cm 3 , preferably lower than or equal to 5×10 19  atoms/cm 3 , further preferably lower than or equal to 1×10 19  atoms/cm 3 , still further preferably lower than or equal to 5×10 18  atoms/cm 3  in secondary ion mass spectrometry (SIMS). It is particularly preferable to lower the hydrogen concentration in the insulator in contact with the semiconductor layer. 
     Furthermore, the nitrogen concentration in the insulator is preferably lowered in order to prevent an increase in the nitrogen concentration in the semiconductor layer. Specifically, the nitrogen concentration in the insulator is lower than or equal to 5×10 19  atoms/cm 3 , preferably lower than or equal to 5×10 18  atoms/cm 3 , further preferably lower than or equal to 1×10 18  atoms/cm 3 , still further preferably lower than or equal to 5×10 17  atoms/cm 3  in SIMS. 
     It is preferred that a region of the insulator in contact with at least the semiconductor layer and a region of the insulator in contact with at least the semiconductor layer have few defects and typically have as few signals observed by electron spin resonance (ESR) spectroscopy as possible. An example of the signals is an E′ center observed at a g-factor of 2.001. Note that the E′ center is due to the dangling bond of silicon. For example, in the case where a silicon oxide layer or a silicon oxynitride layer is used as the insulator, a silicon oxide layer or a silicon oxynitride layer whose spin density due to the E′ center is lower than or equal to 3×10 17  spins/cm 3 , preferably lower than or equal to 5×10 16  spins/cm 3  is used. 
     In addition to the above-described signal, a signal due to nitrogen dioxide (NO 2 ) may be observed. The signal is divided into the following three signals according to the nitrogen nuclear spin: a signal observed at a g-factor greater than or equal to 2.037 and less than or equal to 2.039 (referred to as a first signal), a signal observed at a g-factor greater than or equal to 2.001 and less than or equal to 2.003 (referred to as a second signal), and a signal observed at a g-factor greater than or equal to 1.964 and less than or equal to 1.966 (referred to as a third signal). 
     For example, as the insulator, it is suitable to use an insulator whose spin density of a signal due to nitrogen dioxide (NO 2 ) is higher than or equal to 1×10 17  spins/cm 3  and lower than 1×10 18  spins/cm 3 . 
     Note that nitrogen oxide (NO x ) including nitrogen dioxide (NO 2 ) forms a state in the insulator. The state is positioned in the energy gap of the oxide semiconductor layer. Thus, when nitrogen oxide (NO x ) diffuses to the interface between the insulator and the oxide semiconductor layer, an electron may be trapped by the state on the insulator side. As a result, the trapped electron remains in the vicinity of the interface between the insulator and the oxide semiconductor layer; hence, the threshold voltage of the transistor is shifted in the positive direction. Accordingly, the use of a film with a low nitrogen oxide content as the insulator can reduce a shift in the threshold voltage of the transistor. 
     As an insulator that releases a small amount of nitrogen oxide (NO x ), for example, a silicon oxynitride layer can be used. The silicon oxynitride layer is a film that releases more ammonia than nitrogen oxide (NO x ) in thermal desorption spectroscopy (TDS); the typical released amount of ammonia is greater than or equal to 1×10 18 /cm 3  and less than or equal to 5×10 19 /cm 3 . Note that the released amount of ammonia is the total amount in the range of the heat treatment temperature in TDS from 50° C. to 650° C. or from 50° C. to 550° C. 
     Since nitrogen oxide (NO x ) reacts with ammonia and oxygen in heat treatment, the use of an insulator that releases a large amount of ammonia reduces nitrogen oxide (NO x ). 
     At least one of the insulators in contact with the oxide semiconductor layer is preferably formed using an insulator from which oxygen is released by heating. Specifically, it is preferable to use an insulator in which the amount of released oxygen converted into oxygen atoms is 1.0×10 18  atoms/cm 3  or more, 1.0×10 19  atoms/cm 3  or more, or 1.0×10 20  atoms/cm 3  or more in TDS performed with heat treatment where the surface temperature of the insulator is higher than or equal to 100° C. and lower than or equal to 700° C., preferably higher than or equal to 100° C. and lower than or equal to 500° C. Note that in this specification and the like, oxygen released by heating is also referred to as “excess oxygen”. 
     Furthermore, an insulator containing excess oxygen can also be formed by performing treatment for adding oxygen to an insulator. The treatment for adding oxygen can be performed by heat treatment, plasma treatment, or the like in an oxidizing atmosphere. Alternatively, oxygen may be added by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Examples of a gas used in the treatment for adding oxygen include an oxygen gas such as  16 O 2  or  18 O 2  and a gas containing oxygen, such as a nitrous oxide gas or an ozone gas. Note that in this specification, the treatment for adding oxygen is also referred to as “oxygen doping treatment”. The oxygen doping treatment may be performed while the substrate is heated. 
     For the insulator, a heat-resistant organic material such as polyimide, an acrylic resin, a benzocyclobutene-based resin, polyamide, or an epoxy-based resin can be used. Other than the above organic materials, it is also possible to use a low permittivity material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the insulator may be formed by stacking a plurality of insulators formed of these materials. 
     Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may include an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. In addition, the organic group may include a fluoro group. 
     There is no particular limitation on the method for forming the insulator. Note that a baking step is necessary in some cases depending on a material used for the insulator. In this case, when the baking step of the insulator also serves as another heat treatment step, the transistor can be manufactured efficiently. 
     [Electrode] 
     As a conductive material for forming the electrode, a material containing one or more kinds of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and the like can be used. A semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used. 
     A conductive material containing the above metal element and oxygen may be used. A conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium gallium zinc oxide, or indium tin oxide to which silicon is added may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. 
     A stack including a plurality of conductors formed of the above materials may be used. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. A stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. A stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed. A stacked-layer structure combining a conductive material containing nitrogen and a conductive material containing oxygen may be employed. 
     Note that in the case where an oxide semiconductor is used for the semiconductor layer and the gate electrode employs a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen, the conductive material containing oxygen is preferably provided on the semiconductor layer side. By providing the conductive material containing oxygen on the semiconductor layer side, oxygen released from the conductive material is easily supplied to the semiconductor layer. 
     For the electrode, a conductive material with high embeddability, such as tungsten or polysilicon, can be used, for example. A conductive material with high embeddability and a barrier layer (a diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer may be used in combination. Note that the electrode may be referred to as a “contact plug”. 
     In particular, the electrode in contact with the gate insulator is preferably formed using a conductive material through which impurities are less likely to pass. An example of the conductive material through which impurities are less likely to pass is tantalum nitride. 
     When an insulating material through which impurities are less likely to pass is used for the insulator and a conductive material through which impurities are less likely to pass is used for the electrode, diffusion of impurities to the transistor can be further inhibited. Thus, the reliability of the transistor can be further increased. That is, the reliability of the semiconductor device can be further increased. 
     [Semiconductor Layer] 
     For the semiconductor layer, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As a semiconductor material, silicon, germanium, or the like can be used, for example. Furthermore, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, an organic semiconductor, or the like can be used. 
     In the case of using an organic semiconductor for the semiconductor layer, a low molecular organic material having an aromatic ring, a π-electron conjugated conductive polymer, or the like can be used. For example, rubrene, tetracene, pentacene, perylenediimide, tetracyanoquinodimethane, polythiophene, polyacetylene, or polyparaphenylene vinylene can be used. 
     Note that semiconductor layers may be stacked. In the case of stacking semiconductor layers, semiconductors having different crystal states may be used or different semiconductor materials may be used. 
     The bandgap of an oxide semiconductor, which is one kind of metal oxide, is greater than or equal to 2 eV; thus, the use of the oxide semiconductor for the semiconductor layer can achieve a transistor with an extremely low off-state current. Specifically, the off-state current per micrometer of channel width at room temperature (typically 25° C.) at a voltage between a source and a drain of 3.5 V can be lower than 1×10 −20  A, lower than 1×10 −22  A, or lower than 1×10 −24  A. That is, the on/off ratio can be greater than or equal to 20 digits. In addition, a transistor using an oxide semiconductor for the semiconductor layer (an OS transistor) has high withstand voltage between its source and drain. Thus, a transistor with high reliability can be provided. A transistor with high output voltage and high withstand voltage can be provided. A semiconductor device or the like with high reliability can be provided. A semiconductor device with high output voltage and high withstand voltage can be provided. 
     In this specification and the like, a transistor in which silicon having crystallinity is used for a semiconductor layer where a channel is formed is also referred to as a “crystalline Si transistor”. 
     The crystalline Si transistor tends to have relatively high mobility compared with the OS transistor. On the other hand, the crystalline Si transistor has difficulty in achieving an extremely low off-state current such as one in the OS transistor. Thus, it is important that the semiconductor material used for the semiconductor layer be properly selected depending on the purpose and the usage. For example, depending on the purpose and the usage, the OS transistor and the crystalline Si transistor and the like may be used in combination. 
     In the case where an oxide semiconductor layer is used as the semiconductor layer, the oxide semiconductor layer is preferably formed by a sputtering method. The oxide semiconductor layer is preferably formed by a sputtering method, in which case the density of the oxide semiconductor layer can be increased. When the oxide semiconductor layer is formed by a sputtering method, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as a sputtering gas. In addition, increasing the purity of a sputtering gas is necessary. For example, as an oxygen gas or a rare gas used as a sputtering gas, a gas that is highly purified to have a dew point of −60° C. or lower, preferably −100° C. or lower is used. When the highly purified sputtering gas is used for the deposition, entry of moisture or the like into the oxide semiconductor layer can be prevented as much as possible. 
     Furthermore, in the case where the oxide semiconductor layer is formed by a sputtering method, moisture in a deposition chamber of a sputtering apparatus is preferably removed as much as possible. For example, with an adsorption vacuum evacuation pump such as a cryopump, the deposition chamber is preferably evacuated to be a high vacuum state (to a degree of approximately 5×10 −7  Pa to 1×10 −4  Pa). In particular, the partial pressure of gas molecules corresponding to H 2 O (gas molecules corresponding to m/z=18) in the deposition chamber in the standby mode of the sputtering apparatus is preferably lower than or equal to 1×10 −4  Pa, further preferably lower than or equal to 5×10 −5  Pa. 
     [Metal Oxide] 
     An oxide semiconductor, which is one kind of metal oxide, preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. Furthermore, aluminum, gallium, yttrium, tin, or the like is preferably contained in addition to them. Furthermore, one kind or a plurality of kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained. 
     Here, the case where an oxide semiconductor contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like. Note that it is sometimes acceptable to use a plurality of the above-described elements in combination as the element M. 
     Note that in this specification and the like, a metal oxide containing nitrogen is also collectively referred to as a metal oxide in some cases. A metal oxide containing nitrogen may be referred to as a metal oxynitride. 
     [[Structure of Metal Oxide]] 
     An oxide semiconductor, which is one kind of metal oxide, is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystalline oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. 
     The CAAC-OS has c-axis alignment, a plurality of nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that the distortion refers to a portion where the direction of a lattice arrangement changes between a region with a regular lattice arrangement and another region with a regular lattice arrangement in a region where the plurality of nanocrystals are connected. 
     The nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in some cases. Furthermore, a pentagonal or heptagonal lattice arrangement, for example, is included in the distortion in some cases. Note that it is difficult to observe a clear grain boundary even in the vicinity of distortion in the CAAC-OS. That is, formation of a grain boundary is inhibited by the distortion of a lattice arrangement. This is because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in the a-b plane direction, an interatomic bond length changed by substitution of a metal element, and the like. 
     The CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing the element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element M in the (M,Zn) layer is replaced by indium, the layer can also be referred to as an (In,M,Zn) layer. Furthermore, when indium in the In layer is replaced by the element M, the layer can also be referred to as an (In,M) layer. 
     The CAAC-OS is a metal oxide with high crystallinity. On the other hand, in the CAAC-OS, a reduction in electron mobility due to a grain boundary is less likely to occur because it is difficult to observe a clear grain boundary. Furthermore, entry of impurities, formation of defects, or the like might decrease the crystallinity of a metal oxide, which means that the CAAC-OS is a metal oxide having small amounts of impurities and defects (e.g., oxygen vacancies). Thus, a metal oxide including the CAAC-OS is physically stable. Therefore, the metal oxide including the CAAC-OS is resistant to heat and has high reliability. 
     In the nc-OS, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. Furthermore, there is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation in the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor by some analysis methods. 
     An a-like OS is a metal oxide having a structure between those of the nc-OS and an amorphous oxide semiconductor. The a-like OS contains a void or a low-density region. That is, the a-like OS has low crystallinity compared with the nc-OS and the CAAC-OS. 
     An oxide semiconductor (a metal oxide) can have various structures with different properties. The oxide semiconductor may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS. 
     [Transistor Including Metal Oxide] 
     Next, the case where the above metal oxide is used in a channel formation region of a transistor is described. 
     Note that when the above metal oxide is used in a channel formation region of a transistor, a transistor having high field-effect mobility can be achieved. In addition, a transistor having high reliability can be achieved. 
     Furthermore, a metal oxide with a low carrier density is preferably used for the transistor. In the case where the carrier density of a metal oxide film is reduced, the impurity concentration in the metal oxide film is reduced to reduce the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. For example, a metal oxide has a carrier density lower than 8×10 11 /cm 3 , preferably lower than 1×10 11 /cm 3 , further preferably lower than 1×10 10 /cm 3 , and higher than or equal to 1×10 −9 /cm 3 . 
     A highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low density of defect states and accordingly may have a low density of trap states. 
     Charges trapped by the trap states in the metal oxide take a long time to be released and may behave like fixed charges. Thus, a transistor whose channel formation region includes a metal oxide having a high density of trap states has unstable electrical characteristics in some cases. 
     Accordingly, in order to obtain stable electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In addition, in order to reduce the impurity concentration in the metal oxide, the impurity concentration in an adjacent film is also preferably reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon. 
     [Impurities] 
     Here, the influence of each impurity in the metal oxide is described. 
     When silicon or carbon, which is a Group 14 element, is contained in the metal oxide, defect states are formed in the metal oxide. Thus, the concentration of silicon or carbon in the metal oxide and the concentration of silicon or carbon in the vicinity of an interface with the metal oxide (the concentration measured by secondary ion mass spectrometry (SIMS)) are set lower than or equal to 2×10 18  atoms/cm 3 , preferably lower than or equal to 2×10 17  atoms/cm 3 . 
     When the metal oxide contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated in some cases. Thus, a transistor using a metal oxide that contains an alkali metal or an alkaline earth metal for its channel formation region is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of an alkali metal or an alkaline earth metal in the metal oxide. Specifically, the concentration of an alkali metal or an alkaline earth metal in the metal oxide obtained by SIMS is set lower than or equal to 1×10 18  atoms/cm 3 , preferably lower than or equal to 2×10 16  atoms/cm 3 . 
     When containing nitrogen, the metal oxide easily becomes n-type by generation of electrons serving as carriers and an increase in carrier density. As a result, a transistor using a metal oxide that contains nitrogen for its channel formation region is likely to have normally-on characteristics. Thus, nitrogen in the channel formation region in the metal oxide is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is set lower than 5×10 19  atoms/cm 3 , preferably lower than or equal to 5×10 18  atoms/cm 3 , further preferably lower than or equal to 1×10 18  atoms/cm 3 , still further preferably lower than or equal to 5×10 17  atoms/cm 3  in SIMS. 
     Hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to be water, and thus forms an oxygen vacancy in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor using the metal oxide that contains hydrogen for its channel formation region is likely to have normally-on characteristics. Accordingly, hydrogen in the metal oxide is preferably reduced as much as possible. Specifically, the hydrogen concentration of the metal oxide obtained by SIMS is set lower than 1×10 20  atoms/cm 3 , preferably lower than 1×10 19  atoms/cm 3 , further preferably lower than 5×10 18  atoms/cm 3 , still further preferably lower than 1×10 18  atoms/cm 3 . 
     When a metal oxide in which impurities are sufficiently reduced is used in a channel formation region of a transistor, stable electrical characteristics can be given. 
     As a metal oxide used for a semiconductor of a transistor, a thin film having high crystallinity is preferably used. With the use of the thin film, the stability or the reliability of the transistor can be improved. Examples of the thin film include a thin film of a single-crystal metal oxide and a thin film of a polycrystalline metal oxide. However, to form the thin film of a single-crystal metal oxide or the thin film of a polycrystalline metal oxide over a substrate, a high-temperature process or a laser heating process is needed. Thus, the manufacturing process cost is increased, and in addition, the throughput is decreased. 
     Non-Patent Document 1 and Non-Patent Document 2 have reported that an In—Ga—Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was found in 2009. It has been reported that CAAC-IGZO has c-axis alignment, a crystal grain boundary is not clearly observed, and CAAC-IGZO can be formed over a substrate at low temperatures. It has also been reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability. 
     In addition, in 2013, an In—Ga—Zn oxide having an nc structure (referred to as nc-IGZO) was found (see Non-Patent Document 3). It has been reported that nc-IGZO has periodic atomic arrangement in a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) and there is no regularity of crystal orientation between different regions. 
     Non-Patent Document 4 and Non-Patent Document 5 have shown a change in average crystal size due to electron beam irradiation to thin films of the above CAAC-IGZO, the above nc-IGZO, and IGZO having low crystallinity. In the thin film of IGZO having low crystallinity, crystalline IGZO of approximately 1 nm was observed even before the electron beam irradiation. Thus, it has been reported that the existence of a completely amorphous structure was not observed in IGZO. In addition, it has been shown that the thin film of CAAC-IGZO and the thin film of nc-IGZO each have higher stability to electron beam irradiation than the thin film of IGZO having low crystallinity. Thus, the thin film of CAAC-IGZO or the thin film of nc-IGZO is preferably used for a semiconductor of a transistor. 
     A transistor using a metal oxide has an extremely low leakage current in an off state. Specifically, Non-Patent Document 6 shows that the off-state current per micrometer in the channel width of the transistor is of the order of yA/μm (10 −24  A/μm). For example, a low-power-consumption CPU applying a characteristic of low leakage current of the transistor using a metal oxide is disclosed (see Non-Patent Document 7). 
     Furthermore, application of a transistor using a metal oxide to a display device that utilizes the characteristic of a low leakage current of the transistor has been reported (see Non-Patent Document 8). In the display device, a displayed image is changed several tens of times per second. The number of times an image is changed per second is referred to as a refresh rate. The refresh rate is also referred to as driving frequency. Such high-speed screen change that is hard for human eyes to recognize is considered as a cause of eyestrain. Thus, it is proposed that the refresh rate of the display device is lowered to reduce the number of times of image rewriting. Moreover, driving with a lowered refresh rate enables the power consumption of the display device to be reduced. Such a driving method is referred to as idling stop (IDS) driving. 
     The discovery of the CAAC structure and the nc structure has contributed to an improvement in electrical characteristics and reliability of a transistor using a metal oxide having the CAAC structure or the nc structure, a reduction in manufacturing cost, and an improvement in throughput. Furthermore, applications of the transistor to a display device and an LSI utilizing the characteristic of a low leakage current of the transistor have been studied. 
     &lt;Deposition Method&gt; 
     An insulating material for forming the insulator, a conductive material for forming the electrode, or a semiconductor material for forming the semiconductor layer can be formed by a sputtering method, a spin coating method, a CVD (Chemical Vapor Deposition) method (including a thermal CVD method, an MOCVD (Metal Organic Chemical Vapor Deposition) method, a PECVD (Plasma Enhanced CVD) method, a high density plasma CVD method, an LPCVD (low pressure CVD) method, an APCVD (atmospheric pressure CVD) method, and the like), an ALD (Atomic Layer Deposition) method, an MBE (Molecular Beam Epitaxy) method, a PLD (Pulsed Laser Deposition) method, a dipping method, a spray coating method, a droplet discharging method (e.g., an inkjet method), a printing method (e.g., screen printing or offset printing), or the like. 
     By a plasma CVD method, a high-quality film can be obtained at a relatively low temperature. With the use of a film formation method that does not use plasma at the time of film formation, such as an MOCVD method, an ALD method, or a thermal CVD method, damage is not easily caused on a surface where the film is formed. For example, a wiring, an electrode, an element (e.g., a transistor or a capacitor), or the like included in a semiconductor device might be charged up by receiving charges from plasma. In that case, accumulated charges might break the wiring, electrode, element, or the like included in the semiconductor device. By contrast, in the case of a film formation method not using plasma, such plasma damage is not caused; thus, the yield of semiconductor devices can be increased. Moreover, since plasma damage during film formation is not caused, a film with few defects can be obtained. 
     Unlike a film formation method in which particles ejected from a target or the like are deposited, a CVD method and an ALD method are film formation methods in which a film is formed by reaction at a surface of an object. Thus, a CVD method and an ALD method are film formation methods that enable favorable step coverage almost regardless of the shape of an object. In particular, an ALD method enables excellent step coverage and excellent thickness uniformity and can be favorably used to cover a surface of an opening with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate, and thus is preferably used in combination with another film formation method with a high deposition rate, such as a CVD method, in some cases. 
     When a CVD method or an ALD method is used, the composition of a film to be formed can be controlled with a flow rate ratio of source gases. For example, by a CVD method or an ALD method, a film with a certain composition can be formed by the flow rate ratio of the source gases. Moreover, with a CVD method or an ALD method, by changing the flow rate ratio of the source gases while forming the film, a film whose composition is continuously changed can be formed. In the case of forming a film while changing the flow rate ratio of the source gases, as compared with the case of forming a film with the use of a plurality of deposition chambers, the time taken for the film formation can be shortened because the time taken for transfer and pressure adjustment is omitted. Thus, semiconductor devices can be manufactured with improved productivity in some cases. 
     Note that in the case of forming a film by an ALD method, a gas that does not contain chlorine is preferably used as a material gas. 
     Transistor Structure Example 2 
     A structure example of a transistor  200 B is described with reference to  FIGS.  7 (A) to  7 (C) .  FIG.  7 (A)  is a top view of the transistor  200 B.  FIG.  7 (B)  is a cross-sectional view of a portion indicated by a dashed-dotted line L 1 -L 2  in  FIG.  7 (A) .  FIG.  7 (C)  is a cross-sectional view of a portion indicated by a dashed-dotted line W 1 -W 2  in  FIG.  7 (A) . Note that for clarification of the drawing, some components are not illustrated in the top view of  FIG.  7 (A) . 
     The transistor  200 B is a variation example of the transistor  200 A. Therefore, differences from the transistor  200 A are mainly described to avoid repeated description. 
     In the transistor  200 B illustrated in  FIG.  7   , the oxide  230   c , the insulator  250 , and the conductor  260  are positioned in an opening provided in the insulator  280  with the insulator  274  positioned therebetween. Moreover, the oxide  230   c , the insulator  250 , and the conductor  260  are positioned between the conductor  240   s  and the conductor  240   d.    
     Note that the oxide  230   c  is preferably provided in the opening in the insulator  280  with the insulator  274  positioned therebetween. When the insulator  274  has a barrier property, diffusion of impurities from the insulator  280  into the oxide  230  can be inhibited. 
     The insulator  250  functions as a first gate insulator. The insulator  250  is preferably provided in the opening in the insulator  280  with the oxide  230   c  and the insulator  274  positioned therebetween. 
     The insulator  274  is positioned between the insulator  280  and the transistor  200 B. For the insulator  274 , an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water or hydrogen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. Moreover, it is possible to use, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide or silicon nitride oxide, silicon nitride, or the like. 
     The insulator  274  can inhibit diffusion of impurities such as water or hydrogen contained in the insulator  280  into the oxide  230   b  through the oxide  230   c  and the insulator  250 . Furthermore, oxidation of the conductor  260  due to excess oxygen contained in the insulator  280  can be inhibited. 
     Transistor Structure Example 3 
       FIG.  8    illustrates an example of a semiconductor device including a transistor  200 C.  FIG.  8 (A)  is a top view of the semiconductor device. Note that for clarification of the drawing, some films are not illustrated in  FIG.  8 (A) .  FIG.  8 (B)  is a cross-sectional view along the dashed-dotted line L 1 -L 2  illustrated in  FIG.  8 (A) , and  FIG.  8 (C)  is a cross-sectional view along the dashed-dotted line W 1 -W 2 . 
     Note that in the semiconductor device illustrated in  FIG.  8   , components having the same functions as the components forming the semiconductor devices illustrated in  FIG.  2   ,  FIG.  3   , and  FIG.  4    are denoted by the same reference numerals. 
     In  FIGS.  8 (A) to  8 (C) , the conductor  240  is not provided, and a region  231   s  and a region  231   d  are included on part of the exposed surface of the oxide  230   b . One of the region  231   s  and the region  231   d  functions as a source region, and the other functions as a drain region. An insulator  273  is provided between the oxide  230   b  and the insulator  274 . 
     The region  231  (the region  231   s  and the region  231   d ) illustrated in  FIG.  8    is a region where an element to be described later is added to the oxide  230   b . The region  231  can be formed using a dummy gate, for example. 
     Specifically, the dummy gate is provided over the oxide  230   b , and an element that reduces the resistance of the oxide  230   b  is preferably added using the dummy gate as a mask. That is, the element is added to a region of the oxide  230  that does not overlap with the dummy gate, so that the region  231  is formed. For the addition of the element, an ion implantation method by which an ionized source gas is subjected to mass separation and then added, an ion doping method by which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used. 
     As the element that reduces the resistance of the oxide  230 , boron or phosphorus is typically used. Hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas element, or the like can also be used. Typical examples of the rare gas include helium, neon, argon, krypton, and xenon. The concentration of the element is measured by secondary ion mass spectrometry (SIMS) or the like. 
     In particular, boron and phosphorus are preferably used because an apparatus used in a manufacturing line for amorphous silicon or low-temperature polysilicon can be used. Since the existing facility can be used, capital investment can be reduced. 
     Next, an insulating film to be the insulator  273  and an insulating film to be the insulator  274  may be deposited over the oxide  230   b  and the dummy gate. The insulating film to be the insulator  273  and the insulator  274  are stacked and provided, whereby a region where the region  231  and the oxide  230   c  and the insulator  250  overlap with each other can be provided. 
     Specifically, after an insulating film to be the insulator  280  is provided over the insulating film to be the insulator  274 , the insulating film to be the insulator  280  is subjected to CMP (Chemical Mechanical Polishing) treatment, whereby part of the insulating film to be the insulator  280  is removed and the dummy gate is exposed. Then, when the dummy gate is removed, part of the insulator  273  in contact with the dummy gate is preferably also removed. Thus, the insulator  274  and the insulator  273  are exposed at the side surface of the opening provided in the insulator  280 , and the region  231  provided in the oxide  230   b  is partly exposed at the bottom surface of the opening. Next, an oxide film to be the oxide  230   c , an insulating film to be the insulator  220 , and a conductive film to be the conductor  260  are formed in this order in the opening, and then, the oxide film to be the oxide  230   c , the insulating film to be the insulator  220 , and the conductive film to be the conductor  260  are partly removed by CMP treatment or the like until the insulator  280  is exposed; thus, the transistor illustrated in  FIG.  8    can be formed. 
     Note that the insulator  273  and the insulator  274  are not necessarily provided. Design is appropriately set in consideration of required transistor characteristics. 
     For the transistor illustrated in  FIG.  8   , existing apparatuses can be used, and the conductor  240  is not provided; thus, the cost can be reduced. 
     Transistor Structure Example 4 
     A structure example of a transistor  200 D is described with reference to  FIGS.  9 (A) to  9 (C) .  FIG.  9 (A)  is a top view of the transistor  200 D.  FIG.  9 (B)  is a cross-sectional view of a portion indicated by a dashed-dotted line L 1 -L 2  in  FIG.  9 (A) .  FIG.  9 (C)  is a cross-sectional view of a portion indicated by a dashed-dotted line W 1 -W 2  in  FIG.  9 (A) . Note that for clarification of the drawing, some components are not illustrated in the top view of  FIG.  9 (A) . 
     The transistor  200 D is a variation example of the transistor  200 B. Therefore, differences from the transistor  200 B are mainly described to avoid repeated description. 
     In the transistor  200 D illustrated in  FIG.  9   , a conductor  242   s  is positioned between the conductor  240   s  and the oxide  230   b  and a conductor  242   d  is positioned between the conductor  240   d  and the oxide  230   b . Here, the conductor  240   s  (the conductor  240   d ) has a region that extends beyond the top surface and a side surface on the conductor  260  side of the conductor  242   s  (the conductor  242   d ) and is in contact with the top surface of the oxide  230   b . For the conductor  242 , a conductor that can be used for the conductor  240  is used. It is preferable that the thickness of the conductor  242  be at least larger than that of the conductor  240 . In the transistor  200 D illustrated in  FIG.  9   , the conductor  203  is not provided and the conductor  205  functioning as the second gate also functions as a wiring. 
     In the transistor  200 D illustrated in  FIG.  9   , because of the above structure, the conductor  240  can be closer to the conductor  260  than in the transistor  200 B. Alternatively, the conductor  260  and an end portion of the conductor  240   s  and an end portion of the conductor  240   d  can overlap with each other. Accordingly, the effective channel length of the transistor  200 D can be shortened, and the on-state current and the operating frequency can be improved. 
     The conductor  242   s  (the conductor  242   d ) is preferably provided to be overlapped by the conductor  240   s  (the conductor  240   d ). With such a structure, the conductor  242   s  (the conductor  242   d ) can function as a stopper to prevent over-etching of the oxide  230   b  in etching for forming the opening in which the plug  246   s  (the plug  246   d ) is to be embedded. 
     The transistor  200 D illustrated in  FIG.  9    may have a structure in which an insulator  245  is positioned on and in contact with an insulator  244 . The insulator  244  preferably functions as a barrier insulating film that inhibits entry of impurities such as water or hydrogen and excess oxygen into the transistor  200 D from the insulator  280  side. The insulator  245  can be formed using an insulator that can be used for the insulator  244 . Alternatively, the insulator  245  may be formed using a nitride insulator such as aluminum nitride, titanium nitride, silicon nitride, or silicon nitride oxide, for example. 
     Unlike in the transistor  200 B illustrated in  FIG.  7   , in the transistor  200 D illustrated in  FIG.  9   , the conductor  205  may be provided to have a single-layer structure. In this case, an insulating film to be the insulator  216  is formed over the patterned conductor  205 , and an upper portion of the insulating film is removed by a chemical mechanical polishing (CMP) method or the like until the top surface of the conductor  205  is exposed. Preferably, the planarity of the top surface of the conductor  205  is made favorable. For example, the average surface roughness (Ra) of the top surface of the conductor  205  is less than or equal to 1 nm, preferably less than or equal to 0.5 nm, further preferably less than or equal to 0.3 nm. This allows the improvement in planarity of an insulator formed over the conductor  205  and the increase in crystallinity of the oxide  230   b  and the oxide  230   c.    
     Transistor Structure Example 5 
     A structure example of a transistor  200 E is described with reference to  FIGS.  10 (A) to  10 (C) .  FIG.  10 (A)  is a top view of the transistor  200 E.  FIG.  10 (B)  is a cross-sectional view of a portion indicated by a dashed-dotted line L 1 -L 2  in  FIG.  10 (A) .  FIG.  10 (C)  is a cross-sectional view of a portion indicated by a dashed-dotted line W 1 -W 2  in  FIG.  10 (A) . Note that for clarification of the drawing, some components are not illustrated in the top view of  FIG.  10 (A) . 
     The transistor  200 E is a variation example of the above transistors. Therefore, differences from the above transistors are mainly described to avoid repeated description. 
     In  FIGS.  10 (A) to  10 (C) , the conductor  203  is not provided and the conductor  205  that functions as a second gate is made to function also as a wiring. Furthermore, the insulator  250  is provided over the oxide  230   c  and a metal oxide  252  is provided over the insulator  250 . The conductor  260  is provided over the metal oxide  252 , and an insulator  270  is provided over the conductor  260 . An insulator  271  is provided over the insulator  270 . 
     The metal oxide  252  preferably has a function of inhibiting diffusion of oxygen. When the metal oxide  252  that inhibits oxygen diffusion is provided between the insulator  250  and the conductor  260 , diffusion of oxygen into the conductor  260  is inhibited. That is, a reduction in the amount of oxygen supplied to the oxide  230  can be inhibited. Moreover, oxidization of the conductor  260  due to oxygen can be suppressed. 
     Note that the metal oxide  252  may function as part of a first gate electrode. For example, an oxide semiconductor that can be used for the oxide  230  can be used for the metal oxide  252 . In this case, when the conductor  260  is deposited by a sputtering method, the metal oxide  252  can have a reduced electric resistance to be a conductor. 
     Note that the metal oxide  252  functions as part of a first gate insulator in some cases. Thus, when silicon oxide, silicon oxynitride, or the like is used for the insulator  250 , a metal oxide that is a high-k material with a high dielectric constant is preferably used for the metal oxide  252 . Such a stacked-layer structure can be thermally stable and can have a high dielectric constant. Thus, a gate potential that is applied during operation of the transistor can be reduced while the physical thickness is maintained. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. 
     Although the metal oxide  252  in the transistor  200 E is shown as a single layer, a stacked-layer structure of two or more layers may be employed. For example, a metal oxide functioning as part of the first gate electrode and a metal oxide functioning as part of the first gate insulator may be stacked. 
     With the metal oxide  252  functioning as the first gate electrode, the on-state current of the transistor  200 E can be increased without a reduction in the influence of the electric field from the conductor  260 . With the metal oxide  252  functioning as the first gate insulator, the distance between the conductor  260  and the oxide  230  is kept by the physical thicknesses of the insulator  250  and the metal oxide  252 , so that leakage current between the conductor  260  and the oxide  230  can be reduced. Thus, with the stacked-layer structure of the insulator  250  and the metal oxide  252 , the physical distance between the conductor  260  and the oxide  230  and the intensity of electric field applied from the conductor  260  to the oxide  230  can be easily adjusted as appropriate. 
     Specifically, the oxide semiconductor that can be used for the oxide  230  can also be used for the metal oxide  252  when the resistance thereof is reduced. Alternatively, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. 
     It is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than hafnium oxide. Therefore, hafnium aluminate is preferable since it is less likely to be crystallized in a thermal budget through the following process. Note that the metal oxide  252  is not an essential structure. Design is appropriately set in consideration of required transistor characteristics. 
     For the insulator  270 , an insulating material having a function of inhibiting the passage of oxygen and impurities such as water or hydrogen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. Thus, oxidization of the conductor  260  due to oxygen from above the insulator  270  can be inhibited. Moreover, entry of impurities such as water or hydrogen from above the insulator  270  into the oxide  230  through the conductor  260  and the insulator  250  can be inhibited. 
     The insulator  271  functions as a hard mask. By providing the insulator  271 , the conductor  260  can be processed such that a side surface of the conductor  260  is substantially perpendicular; specifically, an angle formed by the side surface of the conductor  260  and a surface of the substrate can be greater than or equal to 75° and less than or equal to 100°, preferably greater than or equal to 80° and less than or equal to 95°. 
     An insulating material having a function of inhibiting the passage of oxygen and impurities such as water or hydrogen may be used for the insulator  271  so that the insulator  271  also functions as a barrier layer. In that case, the insulator  270  does not have to be provided. 
     Parts of the insulator  270 , the conductor  260 , the metal oxide  252 , the insulator  250 , and the oxide  230   c  are selected and removed using the insulator  271  as a hard mask, whereby their side surfaces can be substantially aligned with each other and a surface of the oxide  230   b  can be partly exposed. 
     The transistor  200 E includes a region  231   s  and a region  231   d  on part of the exposed surface of the oxide  230   b . One of the region  231   s  and the region  231   d  functions as a source region, and the other functions as a drain region. 
     The region  231   s  and the region  231   d  can be formed by addition of an impurity element such as phosphorus or boron to the exposed surface of the oxide  230   b  by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or plasma treatment, for example. In this embodiment and the like, an “impurity element” refers to an element other than main constituent elements. 
     Alternatively, the region  231   s  and the region  231   d  can be formed in such manner that, after part of the surface of the oxide  230   b  is exposed, a metal film is formed and then heat treatment is performed so that the element contained in the metal film is diffused into the oxide  230   b.    
     The electrical resistivity of regions of the oxide  230   b  to which the impurity element is added decreases. For that reason, the region  231   s  and the region  231   d  are sometimes referred to “impurity regions” or “low-resistance regions”. 
     The region  231   s  and the region  231   d  can be formed in a self-aligned manner by using the insulator  271  or the conductor  260  as a mask. Accordingly, the conductor  260  does not overlap with the region  231   s  or the region  231   d , so that the parasitic capacitance can be reduced. Moreover, an offset region is not formed between a channel formation region and the source region or the drain region (the region  231   s  or the region  231   d ). The formation of the region  231   s  and the region  231   d  in a self-aligned manner achieves an increase in on-state current, a reduction in threshold voltage, and an improvement in operating frequency, for example. 
     Note that an offset region may be provided between the channel formation region and the source region or the drain region in order to further reduce the off-state current. The offset region is a region where the electrical resistivity is high and a region where the above-described addition of the impurity element is not performed. The offset region can be formed by the above-described addition of the impurity element after the formation of an insulator  275 . In this case, the insulator  275  serves as a mask like the insulator  271  or the like. Thus, the impurity element is not added to a region of the oxide  230   b  overlapped by the insulator  275 , so that the electrical resistivity of the region can be kept high. 
     The transistor  200 E includes the insulator  275  on the side surfaces of the insulator  270 , the conductor  260 , the metal oxide  252 , the insulator  250 , and the oxide  230   c . The insulator  275  is preferably an insulator having a low dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like is preferably used. In particular, silicon oxide, silicon oxynitride, silicon nitride oxide, or porous silicon oxide is preferably used for the insulator  275 , in which case an excess-oxygen region can be easily formed in the insulator  275  in a later step. Silicon oxide and silicon oxynitride are preferable because of their thermal stability. The insulator  275  preferably has a function of diffusing oxygen. 
     The transistor  200 E also includes the insulator  274  over the insulator  275  and the oxide  230 . The insulator  274  is preferably deposited by a sputtering method. When a sputtering method is used, an insulator containing few impurities such as water or hydrogen can be deposited. For example, aluminum oxide is preferably used for the insulator  274 . 
     Note that an oxide film obtained by a sputtering method may extract hydrogen from the structure body over which the oxide film is deposited. Thus, the hydrogen concentration in the oxide  230  and the insulator  275  can be reduced when the insulator  274  absorbs hydrogen and water from the oxide  230  and the insulator  275 . 
     This embodiment can be implemented in an appropriate combination with the structures described in the other embodiments, Example, and the like. 
     Embodiment 3 
     In this embodiment, a memory device of one embodiment of the present invention including a transistor in which an oxide is used for a semiconductor (hereinafter referred to as an OS transistor in some cases) and a capacitor (hereinafter, such a memory device is also referred to as an OS memory device in some cases), is described with reference to  FIG.  11    and  FIG.  12   . The OS memory device includes at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Since the OS transistor has an extremely low off-state current, the OS memory device has excellent retention characteristics and thus can function as a nonvolatile memory. 
     &lt;Structure Example of Memory Device&gt; 
       FIG.  11 (A)  illustrates a structure example of the OS memory device. A memory device  1400  includes a peripheral circuit  1411  and a memory cell array  1470 . The peripheral circuit  1411  includes a row circuit  1420 , a column circuit  1430 , an output circuit  1440 , and a control logic circuit  1460 . 
     The column circuit  1430  includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging wirings. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the wirings are connected to the memory cell included in the memory cell array  1470 , and will be described later in detail. The amplified data signal is output as a data signal RDATA to the outside of the memory device  1400  through the output circuit  1440 . The row circuit  1420  includes, for example, a row decoder and a word line driver circuit, and can select a row to be accessed. 
     As power supply voltages from the outside, a low power supply voltage (VS S), a high power supply voltage (VDD) for the peripheral circuit  1411 , and a high power supply voltage (VIL) for the memory cell array  1470  are supplied to the memory device  1400 . Control signals (CE, WE, and RE), an address signal ADDR, and a data signal WDATA are also input to the memory device  1400  from the outside. The address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit. 
     The control logic circuit  1460  processes the input signals (CE, WE, and RE) input from the outside, and generates control signals for the row decoder and the column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. Signals processed by the control logic circuit  1460  are not limited thereto, and other control signals may be input as necessary. 
     The memory cell array  1470  includes a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of the wirings that connect the memory cell array  1470  to the row circuit  1420  depends on the structure of the memory cell MC, the number of the memory cells MC in a column, and the like. The number of the wirings that connect the memory cell array  1470  to the column circuit  1430  depends on the structure of the memory cell MC, the number of the memory cells MC in a row, and the like. 
     Note that  FIG.  11 (A)  illustrates an example in which the peripheral circuit  1411  and the memory cell array  1470  are formed on the same plane; however, this embodiment is not limited thereto. For example, as illustrated in  FIG.  11 (B) , the memory cell array  1470  may be provided to overlap part of the peripheral circuit  1411 . For example, the sense amplifier may be provided below the memory cell array  1470  so that they overlap with each other. 
       FIG.  12    illustrates structure examples of a memory cell applicable to the memory cell MC. 
     [DOSRAM] 
       FIGS.  12 (A) to  12 (C)  illustrate circuit structure examples of a memory cell of a DRAM. In this specification and the like, a DRAM using a memory cell including one OS transistor and one capacitor is referred to as DOSRAM in some cases. A memory cell  1471  illustrated in  FIG.  12 (A)  includes a transistor M 1  and a capacitor CA. Note that the transistor M 1  includes a gate (also referred to as a top gate in some cases) and a back gate. 
     A first terminal of the transistor M 1  is connected to a first terminal of the capacitor CA. A second terminal of the transistor M 1  is connected to a wiring BIL. The gate of the transistor M 1  is connected to a wiring WOL. The back gate of the transistor M 1  is connected to a wiring BGL. A second terminal of the capacitor CA is connected to a wiring CAL. 
     The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. In the time of data writing and data reading, a low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M 1 . Applying a given potential to the wiring BGL can increase or decrease the threshold voltage of the transistor M 1 . 
     The memory cell MC is not limited to the memory cell  1471 , and the circuit structure can be changed. For example, as in a memory cell  1472  illustrated in  FIG.  12 (B) , the back gate of the transistor M 1  may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the memory cell MC may be a memory cell including a single-gate transistor, that is, the transistor M 1  not including a back gate, as in a memory cell  1473  illustrated in  FIG.  12 (C) . 
     In the case where the semiconductor device described in the above embodiment is used for the memory cell  1471  and the like, the transistor described in the above embodiment can be used as the transistor M 1 . When an OS transistor is used as the transistor M 1 , the leakage current of the transistor M 1  can be extremely low. That is, with the use of the transistor M 1 , written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. In addition, refresh operation of the memory cell can be unnecessary. In addition, owing to an extremely low leakage current, multi-level data or analog data can be retained in the memory cell  1471 , the memory cell  1472 , and the memory cell  1473 . 
     In the DOSRAM, when the sense amplifier is provided below the memory cell array  1470  so that they overlap with each other as described above, the bit line can be shortened. Thus, the bit line capacitance can be small, and the storage capacitance of the memory cell can be reduced. 
     [NOSRAM] 
       FIGS.  12 (D) to  12 (H)  illustrate circuit structure examples of a gain-cell memory cell including two transistors and one capacitor. A memory cell  1474  illustrated in  FIG.  12 (D)  includes a transistor M 2 , a transistor M 3 , and a capacitor CB. Note that the transistor M 2  includes a top gate (simply referred to as a gate in some cases) and a back gate. In this specification and the like, a memory device including a gain-cell memory cell using an OS transistor as the transistor M 2  is referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM) in some cases. 
     A first terminal of the transistor M 2  is connected to a first terminal of the capacitor CB. A second terminal of the transistor M 2  is connected to a wiring WBL. A gate of the transistor M 2  is connected to the wiring WOL. A back gate of the transistor M 2  is connected to the wiring BGL. A second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M 3  is connected to a wiring RBL. A second terminal of the transistor M 3  is connected to a wiring SL. A gate of the transistor M 3  is connected to the first terminal of the capacitor CB. 
     The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. In the time of data writing, data retaining, and data reading, a low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M 2 . By application of a given potential to the wiring BGL, the threshold voltage of the transistor M 2  can be increased or decreased. 
     The memory cell MC is not limited to the memory cell  1474 , and the circuit structure can be changed as appropriate. For example, as in a memory cell  1475  illustrated in  FIG.  12 (E) , the back gate of the transistor M 2  may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the memory cell MC may be a memory cell including as single-gate transistor, that is, the transistor M 2  not including a back gate, as in a memory cell  1476  illustrated in  FIG.  12 (F) . Alternatively, for example, in the memory cell MC, the wiring WBL and the wiring RBL may be combined into one wiring BIL, as in a memory cell  1477  illustrated in  FIG.  12 (G) . 
     In the case where the semiconductor device described in the above embodiment is used for the memory cell  1474  and the like, the transistor described in the above embodiment can be used as the transistor M 2 . When an OS transistor is used as the transistor M 2 , the leakage current of the transistor M 2  can be extremely low. Accordingly, with the use of the transistor M 2 , written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. In addition, refresh operation of the memory cell can be unnecessary. In addition, owing to an extremely low leakage current, multi-level data or analog data can be retained in the memory cell  1474 . The same applies to the memory cells  1475  to  1477 . 
     Note that the transistor M 3  may be a transistor containing silicon in a channel formation region (hereinafter, also referred to as a Si transistor in some cases). The conductivity type of the Si transistor may be of either an n-channel type or a p-channel type. The Si transistor has higher field-effect mobility than the OS transistor in some cases. Therefore, a Si transistor may be used as the transistor M 3  functioning as a reading transistor. Furthermore, the transistor M 2  can be provided to be stacked over the transistor M 3  when a Si transistor is used as the transistor M 3 ; therefore, the area occupied by the memory cell can be reduced, leading to high integration of the memory device. 
     Alternatively, the transistor M 3  may be an OS transistor. When an OS transistor is used as each of the transistor M 2  and the transistor M 3 , the circuit of the memory cell array  1470  can be formed using only n-channel transistors. 
       FIG.  12 (H)  illustrates an example of a gain-cell memory cell of one capacitor for three transistors. A memory cell  1478  illustrated in  FIG.  12 (H)  includes a transistor M 4  to a transistor M 6  and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell  1478  is electrically connected to the wiring BIL, a wiring RWL, a wiring WWL, the wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring for supplying a low-level potential. Note that the memory cell  1478  may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL. 
     The transistor M 4  is an OS transistor including a back gate that is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M 4  may be electrically connected to each other. Alternatively, the transistor M 4  may include no back gate. 
     Note that each of the transistor M 5  and the transistor M 6  may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistor M 4  to the transistor M 6  may be OS transistors, in which case the circuit of the memory cell array  1470  can be formed using only n-channel transistors. 
     In the case where the semiconductor device described in the above embodiment is used for the memory cell  1478 , the transistor described in the above embodiment can be used as the transistor M 4 . When an OS transistor is used as the transistor M 4 , the leakage current of the transistor M 4  can be extremely low. 
     Note that the structures of the peripheral circuit  1411 , the memory cell array  1470 , and the like described in this embodiment are not limited to the above. Positions and functions of these circuits, wirings connected to the circuits, circuit elements, and the like can be changed, deleted, or added as needed. 
     The structure described in this embodiment can be used in an appropriate combination with the structures described in the other embodiments, Example, and the like. 
     Embodiment 4 
     In this embodiment, an example of a chip  1200  on which the semiconductor device of the present invention is mounted will be described with reference to  FIG.  13   . A plurality of circuits (systems) are mounted on the chip  1200 . A technique for integrating a plurality of circuits (systems) into one chip is referred to as system on chip (SoC) in some cases. 
     As illustrated in  FIG.  13 (A) , the chip  1200  includes a CPU (Central Processing Unit)  1211 , a GPU (Graphics Processing Unit)  1212 , one or more of analog arithmetic units  1213 , one or more of memory controllers  1214 , one or more of interfaces  1215 , one or more of network circuits  1216 , and the like. 
     A bump (not illustrated) is provided on the chip  1200 , and as illustrated in  FIG.  13 (B) , the chip  1200  is connected to a first surface of a printed circuit board (PCB)  1201 . In addition, a plurality of bumps  1202  are provided on a rear side of the first surface of the PCB  1201 , and the PCB  1201  is connected to a motherboard  1203 . 
     Memory devices such as DRAMs  1221  and a flash memory  1222  may be provided over the motherboard  1203 . For example, the DOSRAM described in the above embodiment can be used as the DRAM  1221 . In addition, for example, the NOSRAM described in the above embodiment can be used as the flash memory  1222 . 
     The CPU  1211  preferably includes a plurality of CPU cores. In addition, the GPU  1212  preferably includes a plurality of GPU cores. Furthermore, the CPU  1211  and the GPU  1212  may each include a memory for temporarily storing data. Alternatively, a common memory for the CPU  1211  and the GPU  1212  may be provided in the chip  1200 . The NOSRAM or the DOSRAM described above can be used as the memory. Moreover, the GPU  1212  is suitable for parallel computation of a number of data and thus can be used for image processing or product-sum operation. When an image processing circuit or a product-sum operation circuit using an oxide semiconductor of the present invention is provided in the GPU  1212 , image processing and product-sum operation can be performed with low power consumption. 
     In addition, since the CPU  1211  and the GPU  1212  are provided on the same chip, a wiring between the CPU  1211  and the GPU  1212  can be shortened, and the data transfer from the CPU  1211  to the GPU  1212 , the data transfer between the memories included in the CPU  1211  and the GPU  1212 , and the transfer of arithmetic operation results from the GPU  1212  to the CPU  1211  after the arithmetic operation in the GPU  1212  can be performed at high speed. 
     The analog arithmetic unit  1213  includes one or both of an A/D (analog/digital) converter circuit and a D/A (digital/analog) converter circuit. Furthermore, the product-sum operation circuit may be provided in the analog arithmetic unit  1213 . 
     The memory controller  1214  includes a circuit functioning as a controller of the DRAM  1221  and a circuit functioning as an interface of the flash memory  1222 . 
     The interface  1215  includes an interface circuit for an external connection device such as a display device, a speaker, a microphone, a camera, or a controller. Examples of the controller include a mouse, a keyboard, and a game controller. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used. 
     The network circuit  1216  includes a network circuit such as a LAN (Local Area Network). The network circuit  1216  may further include a circuit for network security. 
     The circuits (systems) can be formed in the chip  1200  through the same manufacturing process. Therefore, even when the number of circuits needed for the chip  1200  increases, there is no need to increase the number of manufacturing processes; thus, the chip  1200  can be manufactured at low cost. 
     The motherboard  1203  provided with the PCB  1201  on which the chip  1200  including the GPU  1212  is mounted, the DRAMs  1221 , and the flash memory  1222  can be referred to as a GPU module  1204 . 
     The GPU module  1204  includes the chip  1200  using SoC technology, and thus can have a small size. In addition, the GPU module  1204  is excellent in image processing, and thus is suitably used in a portable electronic device such as a smartphone, a tablet terminal, a laptop PC, or a portable (mobile) game machine. Furthermore, the product-sum operation circuit using the GPU  1212  can execute a method in a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencorder, a deep Boltzmann machine (DBM), a deep belief network (DBN), or the like; thus, the chip  1200  can be used as an AI chip or the GPU module  1204  can be used as an AI system module. 
     The structure described in this embodiment can be used in an appropriate combination with the structures described in the other embodiments, examples, and the like. 
     Embodiment 5 
     In this embodiment, application examples of the memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment can be applied to, for example, memory devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, the computers refer not only to tablet computers, notebook computers, and desktop computers, but also to large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment is applied to a variety of removable memory devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives).  FIG.  14    schematically illustrates some structure examples of removable memory devices. The semiconductor device described in the above embodiment is processed into a packaged memory chip and used in a variety of storage devices and removable memories, for example. 
       FIG.  14 (A)  is a schematic diagram of a USB memory. A USB memory  1100  includes a housing  1101 , a cap  1102 , a USB connector  1103 , and a substrate  1104 . The substrate  1104  is held in the housing  1101 . The substrate  1104  is provided with a memory chip  1105  and a controller chip  1106 , for example. The semiconductor device described in the above embodiment can be incorporated in the memory chip  1105  or the like on the substrate  1104 . 
       FIG.  14 (B)  is a schematic external diagram of an SD card, and  FIG.  14 (C)  is a schematic diagram of the internal structure of the SD card. An SD card  1110  includes a housing  1111 , a connector  1112 , and a substrate  1113 . The substrate  1113  is held in the housing  1111 . The substrate  1113  is held in the housing  1111 . The substrate  1113  is provided with a memory chip  1114  and a controller chip  1115 , for example. When the memory chip  1114  is also provided on the back side of the substrate  1113 , the capacity of the SD card  1110  can be increased. In addition, a wireless chip with a radio communication function may be provided on the substrate  1113 , in which case data can be read from and written in the memory chip  1114  by radio communication between a host device and the SD card  1110 . The semiconductor device described in the above embodiment can be incorporated in the memory chip  1114  or the like on the substrate  1113 . 
       FIG.  14 (D)  is a schematic external diagram of an SSD, and  FIG.  14 (E)  is a schematic diagram of the internal structure of the SSD. An SSD  1150  includes a housing  1151 , a connector  1152 , and a substrate  1153 . The substrate  1153  is held in the housing  1151 . The substrate  1153  is provided with a memory chip  1154 , a memory chip  1155 , and a controller chip  1156 , for example. The memory chip  1155  is a work memory of the controller chip  1156 , and a DOSRAM chip can be used, for example. When the memory chip  1154  is also provided on the back side of the substrate  1153 , the capacity of the SSD  1150  can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip  1154  or the like on the substrate  1153 . 
     This embodiment can be implemented in an appropriate combination with the structures described in the other embodiments, Examples, and the like. 
     Embodiment 6 
     In this embodiment, a display device and a display module are described as examples of a semiconductor device including the transistor disclosed in this specification and the like. 
     The transistor using an oxide semiconductor, which is described using the transistor  200  or the like, is also referred to as an OS transistor below in some cases. 
     &lt;Display Device&gt; 
     An example of a display device in which the above transistor can be used is described.  FIG.  15 (A)  is a block diagram illustrating a structure example of a display device  500 . 
     The display device  500  illustrated in  FIG.  15 (A)  includes a driver circuit  511 , a driver circuit  521   a , a driver circuit  521   b , and a display region  531 . Note that the driver circuit  511 , the driver circuit  521   a , and the driver circuit  521   b  are collectively referred to as a “driver circuit” or a “peripheral driver circuit” in some cases. 
     The driver circuit  521   a  and the driver circuit  521   b  can function as scan line driver circuits, for example. The driver circuit  511  can function as a signal line driver circuit, for example. Note that one of the driver circuit  521   a  and the driver circuit  521   b  may be omitted. Some sort of circuit may be provided to face the driver circuit  511  with the display region  531  placed therebetween. 
     The display device  500  illustrated in  FIG.  15 (A)  as an example includes p wirings  535  that are arranged substantially parallel to each other and whose potentials are controlled by the driver circuit  521   a  and/or the driver circuit  521   b , and q wirings  536  that are arranged substantially parallel to each other and whose potentials are controlled by the driver circuit  511  (p and q are each a natural number of 1 or more). The display region  531  includes a plurality of pixels  532  arranged in a matrix. The pixel  532  includes a pixel circuit  534  and a display element. 
     When three pixels  532  function as one pixel, full-color display can be achieved. The three pixels  532  each control the transmittance, reflectance, amount of emitted light, or the like of red light, green light, or blue light. The light colors controlled by the three pixels  532  are not limited to the combination of red, green, and blue and may be yellow, cyan, and magenta. 
     A pixel  532  that controls white light may be added to the pixels controlling red light, green light, and blue light so that the four pixels  532  may collectively function as one pixel. The addition of the pixel  532  controlling white light can increase the luminance of the display region. When the number of pixels  532  functioning as one pixel is increased and red, green, blue, yellow, cyan, and magenta are used in appropriate combination, the range of color reproduction can be widened. 
     Using the pixels arranged in a matrix of 1920×1080, the display device  500  that can achieve display with a resolution of what is called full high definition (also referred to as “2K resolution”, “2K1K”, “2K”, or the like) can be obtained. For example, using the pixels arranged in a matrix of 3840×2160, the display device  500  that can achieve display with a resolution of what is called ultra high definition (also referred to as “4K resolution”, “4K2K”, “4K”, or the like) can be obtained. For example, using the pixels arranged in a matrix of 7680×4320, the display device  500  that can achieve display with a resolution of what is called super high definition (also referred to as “8K resolution”, “8K4K”, “8K”, or the like) can be obtained. By increasing the number of pixels, the display device  500  that can achieve display with 16K or 32K resolution can be obtained. 
     A wiring  535 _ g  in the g-th row (g is a natural number of 1 to p) is electrically connected to q pixels  532  arranged in the g-th row among the plurality of pixels  532  arranged in p rows and q columns in the display region  531 . A wiring  536 _ h  in the h-th column (h is a natural number of 1 to q) is electrically connected top pixels  532  arranged in the h-th column among the plurality of pixels  532  arranged in p rows and q columns. 
     [Display Element] 
     The display device  500  can employ various modes or include various display elements. Examples of display elements include an EL (electroluminescence) element (an organic EL element, an inorganic EL element, or an EL element containing organic and inorganic materials), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a display element using MEMS (micro electro mechanical systems), a digital micromirror device (DMD), a DMS (digital micro shutter), MIRASOL (registered trademark), an IMOD (interferometric modulation) element, a MEMS shutter display element, an optical-interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, a display element using a carbon nanotube, and the like, which are elements including a display medium whose contrast, luminance, reflectivity, transmittance, or the like is changed by an electrical or magnetic effect. Alternatively, quantum dots may be used as the display element. 
     Examples of display devices using EL elements include an EL display. Examples of display devices using electron emitters include a field emission display (FED), an SED-type flat panel display (SED: Surface-conduction Electron-emitter Display), and the like. Examples of display devices using quantum dots include a quantum dot display and the like. Examples of display devices using liquid crystal elements include a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display) and the like. Examples of display devices using electronic ink, Electronic Liquid Powder (registered trademark), or an electrophoretic element include electronic paper and the like. The display device may be a plasma display panel (PDP). Alternatively, the display device may be a retina scanning-type projection device. 
     Note that in the case of achieving a transflective liquid crystal display or a reflective liquid crystal display, some or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes contain aluminum, silver, or the like. Moreover, in such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes. Thus, the power consumption can be further reduced. 
     Note that in the case where an LED is used, graphene or graphite may be provided under an electrode or a nitride semiconductor of the LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Providing graphene or graphite as described above facilitates deposition of a nitride semiconductor, such as an n-type GaN semiconductor layer containing crystals, thereover. Furthermore, a p-type GaN semiconductor layer containing crystals or the like can be provided thereover to form the LED. Note that an AlN layer may be provided between graphene or graphite and the n-type GaN semiconductor layer containing crystals. The GaN semiconductor layer included in the LED chip may be formed by MOCVD. Note that when graphene is provided, the GaN semiconductor layer included in the LED can be deposited by a sputtering method. 
       FIG.  15 (B) ,  FIG.  15 (C) ,  FIG.  16 (A) , and  FIG.  16 (B)  illustrate circuit structure examples that can be used for the pixel  532 . 
     [Example of Pixel Circuit for Light-Emitting Display Device] 
     The pixel circuit  534  illustrated in  FIG.  15 (B)  includes a transistor  461 , a capacitor  463 , a transistor  468 , and a transistor  464 . The pixel circuit  534  illustrated in  FIG.  15 (B)  is electrically connected to a light-emitting element  469  that can function as a display element. 
     OS transistors can be used as the transistor  461 , the transistor  468 , and the transistor  464 . It is particularly preferable to use an OS transistor as the transistor  461 . 
     One of a source and a drain of the transistor  461  is electrically connected to the wiring  536 _ h . Furthermore, a gate of the transistor  461  is electrically connected to the wiring  535 _ g . A video signal is supplied from the wiring  536 _ h.    
     The transistor  461  has a function of controlling writing of a video signal to a node  465 . 
     One of a pair of electrodes of the capacitor  463  is electrically connected to the node  465 , and the other is electrically connected to a node  467 . The other of the source and the drain of the transistor  461  is electrically connected to the node  465 . 
     The capacitor  463  has a function of a storage capacitor for retaining data written to the node  465 . 
     One of a source and a drain of the transistor  468  is electrically connected to a potential supply line VL_a, and the other is electrically connected to the node  467 . Furthermore, a gate of the transistor  468  is electrically connected to the node  465 . 
     One of a source and a drain of the transistor  464  is electrically connected to a potential supply line V 0 , and the other is electrically connected to the node  467 . Furthermore, a gate of the transistor  464  is electrically connected to the wiring  535 _ g.    
     One of an anode and a cathode of the light-emitting element  469  is electrically connected to a potential supply line VL_b, and the other is electrically connected to the node  467 . 
     As the light-emitting element  469 , an organic electroluminescent element (also referred to as an organic EL element) can be used, for example. Note that the light-emitting element  469  is not limited thereto; an inorganic EL element formed of an inorganic material may be used, for example. 
     A high power supply potential VDD is supplied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is supplied to the other, for example. 
     In the display device  500  including the pixel circuits  534  in  FIG.  15 (B) , the pixels  532  are sequentially selected row by row by the driver circuit  521   a  and/or the driver circuit  521   b , and then the transistor  461  and the transistor  464  are brought into an on state and a video signal is written to the node  465 . 
     The pixel  532  in which data has been written to the node  465  is brought into a holding state when the transistor  461  and the transistor  464  are brought into an off state. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor  468  is adjusted in accordance with the potential of the data written to the node  465 , and the light-emitting element  469  emits light with a luminance corresponding to the amount of flowing current. This operation is sequentially performed row by row; thus, an image can be displayed. 
     As illustrated in  FIG.  16 (A) , a transistor having a backgate may be used as the transistor  461 , the transistor  464 , and the transistor  468 . In each of the transistor  461  and the transistor  464  illustrated in  FIG.  16 (A) , the gate is electrically connected to the backgate. Thus, the gate and the backgate always have the same potential. The backgate of the transistor  468  is electrically connected to the node  467 . Thus, the backgate always has the same potential as the node  467 . 
     The OS transistor described above can be used as at least one of the transistor  461 , the transistor  468 , and the transistor  464 . 
     [Example of Pixel Circuit for Liquid Crystal Display Device] 
     The pixel circuit  534  illustrated in  FIG.  15 (C)  includes the transistor  461  and the capacitor  463 . The pixel circuit  534  illustrated in  FIG.  15 (C)  is electrically connected to a liquid crystal element  462  that can function as a display element. It is preferable to use an OS transistor as the transistor  461 . 
     The potential of one of a pair of electrodes of the liquid crystal element  462  is set as appropriate according to the specifications of the pixel circuit  534 . For example, the one of the pair of electrodes of the liquid crystal element  462  may be supplied with a common potential, or may have the same potential as a capacitor line CL which is described later. Alternatively, a potential supplied to the one of the pair of electrodes of the liquid crystal element  462  may vary among the pixels  532 . The other of the pair of electrodes of the liquid crystal element  462  is electrically connected to a node  466 . The alignment state of the liquid crystal element  462  depends on data written to the node  466 . 
     As a driving method of the display device including the liquid crystal element  462 , for example, a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, a VA mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an MVA mode, a PVA (Patterned Vertical Alignment) mode, an IPS mode, an FFS mode, a TBA (Transverse Bend Alignment) mode, and the like may be used. Examples of a driving method of the display device include, in addition to the above driving methods, an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, and a guest-host mode. However, not limited to the above, a variety of liquid crystal elements and driving methods thereof can be used. 
     When the liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions. 
     A liquid crystal exhibiting a blue phase for which an alignment film is not needed may be used. The blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while the temperature of a cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral material is mixed to account for 5 weight % or more is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition that contains a liquid crystal exhibiting the blue phase and a chiral material has a short response time of 1 msec or less, and has optical isotropy, which makes the alignment process unneeded and has the viewing angle dependence small. An alignment film does not need to be provided and rubbing treatment is thus not necessary; accordingly, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. Thus, the productivity of the liquid crystal display device can be increased. 
     Moreover, it is possible to use a method called domain multiplication or multi-domain design, in which a pixel (pixel) is divided into some regions (subpixels) and molecules are aligned in different directions in their respective regions. 
     The specific resistivity of a liquid crystal material is greater than or equal to 1×10 9  Ω·cm, preferably greater than or equal to 1×10 11  Ω·cm, further preferably greater than or equal to 1×10 12  Ω·cm. Note that a value of the specific resistivity in this specification is a value measured at 20° C. 
     In the pixel circuit  534  in the g-th row and the h-th column, one of the source and the drain of the transistor  461  is electrically connected to the wiring  536 _ h , and the other is electrically connected to the node  466 . The gate of the transistor  461  is electrically connected to the wiring  535 _ g . A video signal is supplied from the wiring  536 _ h . The transistor  461  has a function of controlling writing of a video signal to the node  466 . 
     One of the pair of electrodes of the capacitor  463  is electrically connected to a wiring to which a particular potential is supplied (hereinafter, the capacitor line CL), and the other is electrically connected to the node  466 . Note that the potential value of the capacitor line CL is set as appropriate according to the specifications of the pixel circuit  534 . The capacitor  463  has the function of a storage capacitor for retaining data written to the node  466 . 
     In the display device  500  including the pixel circuits  534  in  FIG.  15 (C) , for example, the pixel circuits  534  are sequentially selected row by row by the driver circuit  521   a  and/or the driver circuit  521   b , and then the transistor  461  is brought into an on state and a video signal is written to the node  466 . 
     The pixel circuit  534  in which the video signal has been written to the node  466  is brought into a holding state when the transistor  461  is brought into an off state. This operation is sequentially performed row by row; thus, an image can be displayed on the display region  531 . 
     As illustrated in  FIG.  16 (B) , a transistor having a backgate may be used as the transistor  461 . In the transistor  461  illustrated in  FIG.  16 (B) , the gate is electrically connected to the backgate. Thus, the gate and the backgate always have the same potential. 
     [Structure Example of Peripheral Circuit] 
       FIG.  17 (A)  illustrates a structure example of the driver circuit  511 . The driver circuit  511  includes a shift register  512 , a latch circuit  513 , and a buffer  514 .  FIG.  17 (B)  illustrates a structure example of the driver circuit  521   a . The driver circuit  521   a  includes a shift register  522  and a buffer  523 . The driver circuit  521   b  can have a structure similar to that of the driver circuit  521   a.    
     A start pulse SP, a clock signal CLK, and the like are input to the shift register  512  and the shift register  522 . 
     [Structure Example of Display Device] 
     With the use the OS transistor described in the above embodiment, some or all of driver circuits that include shift registers can be integrally formed over the same substrate as a pixel portion, whereby a system-on-panel can be formed. 
     In this embodiment, a structure example of a display device using a liquid crystal element and a structure example of a display device using an EL element are described. In  FIG.  18 (A) , a sealant  4005  is provided so as to surround a pixel portion  4002  provided over a first substrate  4001 , and a pixel portion  4002  is sealed by the sealant  4005  and a second substrate  4006 . In  FIG.  18 (A) , a signal line driver circuit  4003  and a scan line driver circuit  4004  that are formed using a single crystal semiconductor or a polycrystalline semiconductor over a substrate separately prepared are mounted in a region different from the region surrounded by the sealant  4005  over the first substrate  4001 . Various signals and potentials given to the signal line driver circuit  4003 , the scan line driver circuit  4004 , or the pixel portion  4002  are supplied from an FPC  4018   a  (Flexible Printed Circuit) and an FPC  4018   b.    
     In  FIG.  18 (B)  and  FIG.  18 (C) , the sealant  4005  is provided so as to surround the pixel portion  4002  and the scan line driver circuit  4004  that are provided over the first substrate  4001 . The second substrate  4006  is provided over the pixel portion  4002  and the scan line driver circuit  4004 . Thus, the pixel portion  4002  and the scan line driver circuit  4004  are sealed together with a display element by the first substrate  4001 , the sealant  4005 , and the second substrate  4006 . In  FIG.  18 (B)  and  FIG.  18 (C) , the signal line driver circuit  4003  that is formed using a single crystal semiconductor or a polycrystalline semiconductor over a substrate separately prepared is mounted in a region different from the region surrounded by the sealant  4005  over the first substrate  4001 . In  FIG.  18 (B)  and  FIG.  18 (C) , various signals and potentials given to the signal line driver circuit  4003 , the scan line driver circuit  4004 , or the pixel portion  4002  are supplied from the FPC  4018 . 
     Although  FIG.  18 (B)  and  FIG.  18 (C)  illustrate the examples in which the signal line driver circuit  4003  is formed separately and mounted on the first substrate  4001 , the structure is not limited thereto. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted. 
     Note that there is no particular limitation on the connection method of the separately formed driver circuit; wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), COF (Chip On Film), or the like can be used.  FIG.  18 (A)  illustrates an example in which the signal line driver circuit  4003  and the scan line driver circuit  4004  are mounted by COG,  FIG.  18 (B)  illustrates an example in which the signal line driver circuit  4003  is mounted by COG, and  FIG.  18 (C)  illustrates an example in which the signal line driver circuit  4003  is mounted by TCP. 
     In some cases, the display device encompasses a panel in which the display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel. 
     The pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors, and the OS transistor described in the above embodiment can be used. 
       FIG.  19 (A)  and  FIG.  19 (B)  are cross-sectional views illustrating cross-sectional structures of portions indicated by the chain line N 1 -N 2  in  FIG.  18 (B) .  FIG.  19 (A)  is an example of a liquid crystal display device using a liquid crystal element as the display element.  FIG.  19 (B)  is an example of a light-emitting display device (also referred to as an “EL display device”) using a light-emitting element as the display element. 
     The display devices illustrated in  FIG.  19 (A)  and  FIG.  19 (B)  each include the electrode  4015 , and the electrode  4015  is electrically connected to a terminal included in the FPC  4018  through an anisotropic conductor  4019 . The electrode  4015  is electrically connected to a wiring  4014  in an opening formed in an insulator  4112 , an insulator  4111 , and an insulator  4110 . 
     The electrode  4015  is formed of the same conductor as a first electrode layer  4030 , and the wiring  4014  is formed of the same conductor as source electrodes and drain electrodes of a transistor  4010  and a transistor  4011 . 
     The pixel portion  4002  and the scan line driver circuit  4004  provided over the first substrate  4001  include a plurality of transistors, and in  FIG.  19 (A)  and  FIG.  19 (B) , the transistor  4010  included in the pixel portion  4002  and the transistor  4011  included in the scan line driver circuit  4004  are illustrated as examples. The insulator  4112  is provided over the transistor  4010  and the transistor  4011  in  FIG.  19 (A) , and a partition wall  4510  is formed over the insulator  4112  in  FIG.  19 (B) . 
     The transistor  4010  and the transistor  4011  are provided over an insulator  4102 . The transistor  4010  and the transistor  4011  each include an electrode  4017  formed over an insulator  4103 , and the insulator  4112  is formed over the electrode  4017 . Note that the electrode  4017  can function as a back gate electrode. 
     The transistor described in the above embodiment can be used as the transistor  4010  and the transistor  4011 . It is preferable to use OS transistors as the transistor  4010  and the transistor  4011 . A change in the electrical characteristics of OS transistors is inhibited and thus the OS transistors are electrically stable. Accordingly, the display devices of this embodiment illustrated in  FIG.  19 (A)  and  FIG.  19 (B)  can be highly reliable display devices. 
     In the OS transistor, a current value in an off state (off-state current value) can be made small. Accordingly, the retention time of an electrical signal such as an image signal can be made longer, and a writing interval can also be set longer in a power-on state. Accordingly, the frequency of refresh operation can be reduced, which leads to an effect of reducing power consumption. 
     The OS transistor can have relatively high field-effect mobility and is thus capable of high-speed operation. Consequently, when the above OS transistor is used in a driver circuit portion or the pixel portion of the display device, high-quality images can be obtained. Moreover, the driver circuit portion or the pixel portion can be separately formed over the same substrate, so that the number of components of the display device can be reduced. 
     The display devices illustrated in  FIG.  19 (A)  and  FIG.  19 (B)  each include a capacitor  4020 . The capacitor  4020  includes an electrode  4021  formed in the same step as a gate electrode of the transistor  4010 , and an electrode formed in the same step as a source electrode and a drain electrode thereof. The electrodes overlap with each other with the insulator  4103  therebetween. 
     In general, the capacitance of a capacitor provided in a pixel portion of the display device is set in consideration of leakage current or the like of a transistor provided in the pixel portion so that charge can be held for a predetermined period. The capacitance of the capacitor may be set in consideration of off-state current of the transistor or the like. 
     For example, when an OS transistor is used for the pixel portion of the liquid crystal display device, the capacitance of the capacitor can be ⅓ or smaller or ⅕ or smaller of the liquid crystal capacitance. Moreover, using an OS transistor can omit the formation of a capacitor. 
     The transistor  4010  provided in the pixel portion  4002  is electrically connected to the display element. In  FIG.  19 (A) , a liquid crystal element  4013  that is a display element includes the first electrode layer  4030 , a second electrode layer  4031 , and a liquid crystal layer  4008 . An insulator  4032  and an insulator  4033  having a function of alignment films are provided to sandwich the liquid crystal layer  4008 . The second electrode layer  4031  is provided on the second substrate  4006  side, and the first electrode layer  4030  and the second electrode layer  4031  overlap with each other with the liquid crystal layer  4008  positioned therebetween. 
     A spacer  4035  is a columnar spacer obtained by selective etching of an insulator and is provided to adjust a distance (cell gap) between the first electrode layer  4030  and the second electrode layer  4031 . Note that a spherical spacer may be used. 
     In the display device, a black matrix (light-blocking layer), an optical member (optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, and the like may be provided. For example, circular polarization may be employed by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, or the like may be used as a light source. 
     The display devices illustrated in  FIG.  19 (A)  and  FIG.  19 (B)  include the insulator  4111  and an insulator  4104 . As the insulator  4111  and the insulator  4104 , insulators through which an impurity element does not easily pass are used. A semiconductor layer of the transistor is sandwiched between the insulator  4111  and the insulator  4104 , whereby entry of impurities from the outside can be prevented. Moreover, when the insulator  4111  and the insulator  4104  are in contact with each other outside the pixel portion  4002 , the effect of preventing entry of impurities from the outside can be enhanced. 
     The insulator  4104  can be formed using a material and a method similar to those for the insulator  222 , for example. The insulator  4111  can be formed using a material and a method similar to those for the insulator  274 , for example. 
     As the display element included in the display device, a light-emitting element utilizing electroluminescence (also referred to as an “EL element”) can be used. An EL element includes a layer containing a light-emitting compound (also referred to as an “EL layer”) between a pair of electrodes. By generating a potential difference between the pair of electrodes that is greater than the threshold voltage of the EL element, holes are injected from the anode side and electrons are injected from the cathode side to the EL layer. The injected electrons and holes are recombined in the EL layer and a light-emitting substance contained in the EL layer emits light. 
     EL elements are classified according to whether a light-emitting material is an organic compound or an inorganic compound; in general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element. 
     In an organic EL element, by voltage application, electrons from one electrode and holes from the other electrode are injected into the EL layer. The carriers (electrons and holes) are recombined, and thus, a light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to a ground state. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element. 
     Besides the light-emitting compound, the EL layer may also include a substance with a high hole-injection property, a substance with a high hole-transport property, a hole-blocking material, a substance with a high electron-transport property, a substance with a high electron-injection property, a substance with a bipolar property (a substance with a high electron-transport property and a high hole-transport property), and the like. 
     The EL layer can be formed by a method such as an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, or a coating method. 
     The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element includes a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure in which a light-emitting layer is interposed between dielectric layers, which are further interposed between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that the description is made here using an organic EL element as a light-emitting element. 
     In order that light emitted from the light-emitting element can be extracted, at least one of the pair of electrodes is transparent. A transistor and a light-emitting element are formed over a substrate; the light-emitting element can have a top emission structure in which light emission is extracted from the surface on the side opposite to the substrate, a bottom emission structure in which light emission is extracted from the surface on the substrate side, or a dual emission structure in which light emission is extracted from both surfaces. The light-emitting element having any of the emission structures can be used. 
     A light-emitting element  4513  that is a display element is electrically connected to the transistor  4010  provided in the pixel portion  4002 . The structure of the light-emitting element  4513  is a stacked-layer structure of the first electrode layer  4030 , a light-emitting layer  4511 , and the second electrode layer  4031 ; however, the structure is not limited thereto. The structure of the light-emitting element  4513  can be changed as appropriate depending on, for example, the direction in which light is extracted from the light-emitting element  4513 . 
     The partition wall  4510  is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable that a photosensitive resin material be used, and an opening portion be formed over the first electrode layer  4030  such that a side surface of the opening portion is formed to be an inclined surface having continuous curvature. 
     The light-emitting layer  4511  may be formed using a single layer or a plurality of layers stacked. 
     A protective layer may be formed over the second electrode layer  4031  and the partition wall  4510  in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, and the like into the light-emitting element  4513 . For the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed. In a space that is sealed by the first substrate  4001 , the second substrate  4006 , and the sealant  4005 , a filler  4514  is provided for sealing. In this manner, it is preferable that packaging (sealing) be performed with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification to prevent exposure to the outside air. 
     As the filler  4514 , an ultraviolet curable resin or a thermosetting resin as well as an inert gas such as nitrogen or argon can be used; and PVC (polyvinyl chloride), an acrylic resin, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), or the like can be used. In addition, a drying agent may be contained in the filler  4514 . 
     For the sealant  4005 , a glass material such as a glass frit or a resin material such as a light curable resin, a thermosetting resin, or a curable resin that is cured at room temperature, such as a two-component-mixture-type resin, can be used. In addition, a drying agent may be contained in the sealant  4005 . 
     In addition, if necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter may be provided as appropriate on a light-emitting surface of the light-emitting element. Furthermore, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment that can reduce glare by diffusing reflected light with projections and depressions on a surface can be performed. 
     When the light-emitting element has a microcavity structure, light with high color purity can be extracted. Furthermore, when a microcavity structure and a color filter are used in combination, glare can be reduced and visibility of a displayed image can be increased. 
     The first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, or the like) for applying voltage to the display element have light-transmitting properties or light-reflecting properties, which depends on the direction in which light is extracted, the position where the electrode layer is provided, and the pattern structure of the electrode layer. 
     For the first electrode layer  4030  and the second electrode layer  4031 , a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used. 
     The first electrode layer  4030  and the second electrode layer  4031  can be formed using one or more kinds of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag); alloys thereof and metal nitrides thereof. 
     The first electrode layer  4030  and the second electrode layer  4031  can be formed using a conductive composition including a conductive macromolecule (also referred to as a conductive polymer). As the conductive macromolecule, what is called a π-electron conjugated conductive macromolecule can be used. Examples include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more kinds of aniline, pyrrole, and thiophene or a derivative thereof. 
     Since the transistor is easily broken owing to static electricity or the like, a protective circuit for protecting the driver circuit is preferably provided. The protective circuit is preferably formed using a nonlinear element. 
     With the use of the shift register described in the above embodiment, it is possible to provide a highly reliable display device. With the use of the transistor described in the above embodiment, it is possible to further increase the reliability of the display device. With the use of the transistor described in the above embodiment, it is possible to provide a display device that has a high resolution, a large size, and high display quality. Furthermore, a display device with reduced power consumption can be provided. 
     &lt;Display Module&gt; 
     A display module is described as an example of a semiconductor device using the above-described OS transistor. In a display module  6000  illustrated in  FIG.  20   , a touch sensor  6004  connected to an FPC  6003 , a display panel  6006  connected to an FPC  6005 , a backlight unit  6007 , a frame  6009 , a printed circuit board  6010 , and a battery  6011  are provided between an upper cover  6001  and a lower cover  6002 . Note that the backlight unit  6007 , the battery  6011 , the touch sensor  6004 , and the like are not provided in some cases. 
     The semiconductor device of one embodiment of the present invention can be used for, for example, the touch sensor  6004 , the display panel  6006 , and an integrated circuit mounted on the printed circuit board  6010 . For example, the above-described display device can be used for the display panel  6006 . 
     The shapes and sizes of the upper cover  6001  and the lower cover  6002  can be changed as appropriate in accordance with the sizes of the touch sensor  6004 , the display panel  6006 , and the like. 
     The touch sensor  6004  can be a resistive or capacitive touch sensor and can be formed to overlap with the display panel  6006 . A touch sensor function can be added to the display panel  6006 . For example, an electrode for a touch sensor can be provided in each pixel of the display panel  6006  so that a capacitive touch panel function is added. Alternatively, a photosensor can be provided in each pixel of the display panel  6006  so that an optical touch sensor function is added, for example. In the case where the touch sensor  6004  do not need to be provided, the touch sensor  6004  can be omitted. 
     The backlight unit  6007  includes a light source  6008 . A structure may be employed in which the light source  6008  is provided at an end portion of the backlight unit  6007  and a light diffusing plate is used. When a light-emitting display device or the like is used for the display panel  6006 , the backlight unit  6007  can be omitted. 
     The frame  6009  has a function of protecting the display panel  6006  and a function of an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board  6010  side. The frame  6009  may also have a function of a radiator plate. 
     The printed circuit board  6010  includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, and the like. As a power supply for supplying power to the power supply circuit, the battery  6011  or a commercial power supply may be used. Note that the battery  6011  can be omitted when a commercial power supply is used as the power supply. 
     The display module  6000  can be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet. 
     This embodiment can be implemented in an appropriate combination with the structures described in the other embodiments and the like. 
     Embodiment 7 
     &lt;Electronic Device&gt; 
     The semiconductor device of one embodiment of the present invention can be used for processors such as CPUs and GPUs or chips.  FIG.  21    illustrates specific examples of electronic devices including a processor such as a CPU or a GPU or a chip of one embodiment of the present invention. 
     &lt;Electronic Device and System&gt; 
     The GPU or the chip of one embodiment of the present invention can be incorporated into a variety of electronic devices. Examples of electronic devices include a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, and an audio reproducing device in addition to electronic devices provided with a relatively large screen, such as a television device, a desktop or laptop personal computer, a monitor for a computer and the like, digital signage, and a large game machine like a pachinko machine. When the integrated circuit or the chip of one embodiment of the present invention is provided in an electronic device, the electronic device can include artificial intelligence. 
     The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display a video, data, or the like on a display portion. When the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission. 
     The electronic device of one embodiment of the present invention may include a sensor (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radioactive rays, flow rate, humidity, gradient, oscillation, a smell, or infrared rays). 
     The electronic device of one embodiment of the present invention can have a variety of functions. For example, the electronic device can have a function of displaying a variety of data (a still image, a moving image, a text image, and the like) on a display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of executing a variety of software (programs), a wireless communication function, and a function of reading out a program or data stored in a recording medium.  FIG.  21    illustrates examples of electronic devices. 
     [Mobile Phone] 
       FIG.  21 (A)  illustrates a mobile phone (smartphone), which is a type of information terminal. An information terminal  5500  includes a housing  5510  and a display portion  5511 . As input interfaces, a touch panel is provided in the display portion  5511  and a button is provided in the housing  5510 . 
     The information terminal  5500  can execute an application utilizing artificial intelligence, with the use of the chip of one embodiment of the present invention. Examples of the application utilizing artificial intelligence include an application for interpreting a conversation and displaying its content on the display portion  5511 ; an application for recognizing letters, figures, and the like input to the touch panel of the display portion  5511  by a user and displaying them on the display portion  5511 ; and an application for biometric authentication using fingerprints, voice prints, or the like. 
     [Information Terminal 1] 
       FIG.  21 (B)  illustrates a desktop information terminal  5300 . The desktop information terminal  5300  includes a main body  5301  of the information terminal, a display  5302 , and a keyboard  5303 . 
     Like the information terminal  5500  described above, the desktop information terminal  5300  can execute an application utilizing artificial intelligence, with the use of the chip of one embodiment of the present invention. Examples of the application utilizing artificial intelligence include design-support software, text correction software, and software for automatic menu generation. Furthermore, with the use of the desktop information terminal  5300 , novel artificial intelligence can be developed. 
     Note that in the above description, a smartphone and a desktop information terminal are shown as examples of the electronic devices in  FIGS.  21 (A) and  21 (B) ; alternatively, the electronic device can be an information terminal other than a smartphone and a desktop information terminal. Examples of information terminals other than a smartphone and a desktop information terminal include a PDA (Personal Digital Assistant), a laptop information terminal, and a workstation. 
     [Household Appliance] 
       FIG.  21 (C)  illustrates an electric refrigerator-freezer  5800  as an example of a household appliance. The electric refrigerator-freezer  5800  includes a housing  5801 , a refrigerator door  5802 , a freezer door  5803 , and the like. 
     When the chip of one embodiment of the present invention is used in the electric refrigerator-freezer  5800 , the electric refrigerator-freezer  5800  including artificial intelligence can be obtained. Utilizing the artificial intelligence enables the electric refrigerator-freezer  5800  to have a function of automatically making a menu based on foods stored in the electric refrigerator-freezer  5800  and food expiration dates, for example, a function of automatically adjusting the temperature to be appropriate for the foods stored in the electric refrigerator-freezer  5800 , and the like. 
     Although the electric refrigerator-freezer is described here as an example of a household appliance, other examples of a household appliance include a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating-cooling combination appliance such as an air conditioner, a washing machine, a drying machine, and an audio visual appliance. 
     [Game Machine] 
       FIG.  21 (D)  illustrates a portable game machine  5200  as an example of a game machine. The portable game machine includes a housing  5201 , a display portion  5202 , a button  5203 , and the like. 
     When the GPU or the chip of one embodiment of the present invention is used in the portable game machine  5200 , the portable game machine  5200  with low power consumption can be obtained. Moreover, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit, the peripheral circuit, and the module can be reduced. 
     Furthermore, when the GPU or the chip of one embodiment of the present invention is used in the portable game machine  5200 , the portable game machine  5200  including artificial intelligence can be obtained. 
     In general, the progress of a game, the actions and words of game characters, and expressions of a phenomenon and the like in the game are programed in the game; however, the use of artificial intelligence in the portable game machine  5200  enables expressions not limited by the game program. For example, expression is possible in which a question posed by a player, the progress of the game, time, and the actions and words of game characters are changed. 
     When a game requiring a plurality of players is played on the portable game machine  5200 , the artificial intelligence can create a virtual game player; thus, the game can be played alone with the game player created by the artificial intelligence as an opponent. 
     Although the portable game machine is illustrated as an example of a game machine in  FIG.  21 (D) , the game machine using the GPU or the chip of one embodiment of the present invention is not limited thereto. Examples of the game machine using the GPU or the chip of one embodiment of the present invention include a home stationary game machine, an arcade game machine installed in entertainment facilities (a game center, an amusement park, and the like), and a throwing machine for batting practice installed in sports facilities. 
     [Moving Vehicle] 
     The GPU or the chip of one embodiment of the present invention can be used in an automobile, which is a moving vehicle, and around a driver&#39;s seat in the automobile. 
       FIG.  21   (E 1 ) illustrates an automobile  5700  as an example of a moving vehicle, and  FIG.  21   (E 2 ) is a diagram illustrating the periphery of a windshield inside the automobile.  FIG.  21   (E 2 ) illustrates a display panel  5701 , a display panel  5702 , and a display panel  5703  that are attached to a dashboard and a display panel  5704  that is attached to a pillar. 
     The display panel  5701  to the display panel  5703  can provide a variety of kinds of information by displaying a speedometer, a tachometer, a mileage, a fuel meter, a gearshift indicator, air-condition setting, and the like. The content, layout, or the like of the display on the display panels can be changed as appropriate to suit the user&#39;s preference, so that the design can be improved. The display panel  5701  to the display panel  5703  can also be used as lighting devices. 
     The display panel  5704  can compensate for the view obstructed by the pillar (a blind spot) by showing an image taken by an imaging device (not illustrated) provided for the automobile  5700 . That is, displaying an image taken by the imaging device provided on the outside of the automobile  5700  leads to compensation for the blind spot and enhancement of safety. In addition, showing an image for compensating for the area which a driver cannot see makes it possible for the driver to confirm safety more easily and comfortably. The display panel  5704  can also be used as a lighting device. 
     Since the GPU or the chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used in an automatic driving system of the automobile  5700 , for example. The chip can also be used for a system for navigation, risk prediction, or the like. The display panel  5701  to the display panel  5704  may display information regarding navigation information, risk prediction, and the like. 
     Although an automobile is described above as an example of a moving vehicle, moving vehicles are not limited to an automobile. Examples of moving vehicles include a train, a monorail train, a ship, and a flying object (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket), and these moving vehicles can include a system utilizing artificial intelligence when equipped with the chip of one embodiment of the present invention. 
     [Broadcasting System] 
     The GPU or the chip of one embodiment of the present invention can be used in a broadcasting system. 
       FIG.  21 (F)  schematically shows data transmission in a broadcasting system. Specifically,  FIG.  21 (F)  shows a path in which a radio wave (a broadcasting signal) transmitted from a broadcast station  5680  is delivered to a television receiver (TV)  5600  of each household. The TV  5600  includes a receiving device (not illustrated), and the broadcast signal received by an antenna  5650  is transmitted to the TV  5600  through the receiving device. 
     Although a UHF (Ultra High Frequency) antenna is illustrated as the antenna  5650  in  FIG.  21 (F) , a BS/110° CS antenna, a CS antenna, or the like can also be used as the antenna  5650 . 
     A radio wave  5675 A and a radio wave  5675 B are broadcast signals for terrestrial broadcasting; a radio wave tower  5670  amplifies the received radio wave  5675 A and transmits the radio wave  5675 B. Each household can view terrestrial TV broadcasting on the TV  5600  by receiving the radio wave  5675 B with the antenna  5650 . Note that the broadcasting system is not limited to the terrestrial broadcasting shown in  FIG.  21 (F)  and may be satellite broadcasting using an artificial satellite, data broadcasting using an optical line, or the like. 
     The above-described broadcasting system may utilize artificial intelligence by using the chip of one embodiment of the present invention. When the broadcast data is transmitted from the broadcast station  5680  to the TV  5600  at home, the broadcast data is compressed by an encoder. When the antenna  5650  receives the compressed broadcast data, the compressed broadcast data is decompressed by a decoder of the receiving device in the TV  5600 . With the use of artificial intelligence, for example, a display pattern included in an image to be displayed can be recognized in motion compensation prediction, which is one of the compressing methods for the encoder. In-frame prediction utilizing artificial intelligence, for instance, can also be performed. For another example, when the broadcast data with low resolution is received and displayed on the TV  5600  with high resolution, image interpolation such as upconversion can be performed in the broadcast data decompression by the decoder. 
     The above-described broadcasting system utilizing artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting, which needs a large amount of broadcast data. 
     As an application of artificial intelligence in the TV  5600 , a recording device including artificial intelligence may be provided in the TV  5600 , for example. With such a structure, the artificial intelligence in the recording device can learn the user&#39;s preference, so that TV programs that suit the user&#39;s preference can be recorded automatically. 
     The electronic devices, the functions of the electronic devices, application examples of artificial intelligence, its effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device. 
     This embodiment can be implemented in an appropriate combination with the structures described in the other embodiments, Examples, and the like. 
     Example 1 
     In this example, a semiconductor device  990  including a plurality of transistors  200  was fabricated and the cross section of the transistor  200  positioned in a certain region was observed. 
     As illustrated in  FIG.  22 (A) , the semiconductor device  990  includes the transistors  200  arranged in 132 rows and 132 columns formed through the same process. In the semiconductor device  990 , the density of the transistors  200  was set to 0.88/μm 2 . 
     Here,  FIG.  22 (B)  illustrates a cross-sectional view in the L length direction of a transistor  200 Ex which was formed as the transistor  200 . Note that the channel length and channel width of the transistor  200 Ex were each designed to be 60 nm. 
     The table below shows materials used for structure bodies of the transistor  200 Ex. Note that in the transistor  200 Ex, components having the same function as the components in the transistor  200  described in the above embodiments are denoted by the same reference numerals. Thus, the above embodiments can be referred to for the components not shown in the table below. 
     
       
         
           
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Component 
                 Material 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 280 
                 Silicon oxide 
               
               
                 273 
                 Aluminum oxide 
               
               
                 240 
                 Tantalum nitride 
               
               
                 230 
                 Oxide semiconductor 
               
               
                 224 
                 Silicon oxide 
               
               
                 280 
                 Silicon oxide 
               
               
                 273 
                 Aluminum oxide 
               
               
                 242 
                 Tantalum nitride 
               
               
                 230 
                 Oxide semiconductor 
               
               
                 224 
                 Silicon oxide 
               
               
                   
               
            
           
         
       
     
     &lt;Method of Fabricating Samples&gt; 
     A method of fabricating the semiconductor device  990  including the transistor  200  is described below. 
     As the insulator  224 , silicon oxide was formed by a CVD method. 
     Next, as a film to be the oxide  230   a , an In—Ga—Zn oxide was formed over the insulator  224  by a sputtering method using a target with In:Ga:Zn=1:3:4 [atomic ratio]. Subsequently, as a film to be the oxide  230   b , an In—Ga—Zn oxide was formed over the film to be the oxide  230   a  by a sputtering method using a target with In:Ga:Zn=4:2:4.1 [atomic ratio]. Note that the film to be the oxide  230   a  and the film to be the oxide  230   b  were successively formed. 
     Next, a tantalum nitride film was formed as a film to be the conductor  240  over the film to be the oxide  230  by a sputtering method. 
     Next, the film to be the oxide  230   a , the film to be the oxide  230   b , and the film to be the conductor  240  were processed to form the oxide  230   a , the oxide  230   b , and the conductor  240 . 
     Next, the insulator  273  was formed over the oxide  230   a , the oxide  230   b , and the conductor  240 . Note that the insulator  273  had a stacked-layer structure of an aluminum oxide film formed by a sputtering method and an aluminum oxide film formed by an ALD method. 
     Next, as a film to be the insulator  280 , a silicon oxide film was formed over the insulator  273  by a CVD method. After that, the film to be the insulator  280  was planarized by a CMP method to form the insulator  280 . 
     Then, the insulator  280 , the insulator  273 , and the conductor  240  were partly removed to form an opening from which the oxide  230   a  and the oxide  230   b  were exposed. 
     Here, the insulator  280  was processed by a dry etching method using a gas containing carbon, hydrogen, and fluorine. The insulator  273  was processed by a wet etching method using TMAH (Tetra Methyl Ammonium Hydroxide). The conductor  240  was processed by a dry etching method using a gas containing fluorine and chlorine. 
     Next, a film to be the oxide  230   c  was formed over the exposed insulator  224 , the exposed oxide  230   a , and the exposed oxide  230   b . Note that the oxide  230   c  had a stacked-layer structure. Next, as a first oxide of the oxide  230   c , an In—Ga—Zn oxide was formed by a sputtering method using a target with In:Ga:Zn=4:2:4.1 [atomic ratio]. Next, as a second oxide of the oxide  230   c , an In—Ga—Zn oxide was formed over the first oxide of the oxide  230   c  by a sputtering method using a target with In:Ga:Zn=1:3:4 [atomic ratio]. Note that the first oxide and the second oxide were successively formed. 
     Next, as a film to be the insulator  250 , silicon oxide was formed by a CVD method. Next, as a film to be the conductor  260 , a titanium nitride film and a tungsten film were successively formed by a CVD method. 
     Next, the film to be the conductor  260 , the film to be the insulator  250 , and the film to be the oxide  230   c  were partly removed by a CMP method to form the conductor  260 , the insulator  250 , and the oxide  230   c.    
     Through the above process, the semiconductor device  990  including the plurality of transistors  200  was fabricated. 
     &lt;Cross-Sectional Observation of Transistor  200 &gt; 
     Next, cross-sectional observation was performed on a transistor  200 ( 1 , 1 ) in the first row and the first column, a transistor  200 ( 3 , 3 ) in the third row and the third column, a transistor  200 ( 6 , 6 ) in the sixth row and the sixth column, a transistor  200 ( 45 , 35 ) in the 45th row and the 35th column, and a transistor  200 ( 65 , 65 ) in the 65th row and the 65th column, among the transistors  200  arranged in the 132 rows and 132 columns included in the semiconductor device  990 . 
     As a comparative example, cross-sectional observation was performed on a semiconductor device in which one transistor  200 Ex is formed in a center portion of a region that has the same area as the semiconductor device  990 . 
     Note that the cross-sectional observation was performed with a scanning transmission electron microscope (STEM). As an apparatus for the observation, HD-2700 manufactured by Hitachi High-Technologies Corporation was used.  FIG.  23    shows the cross-sectional STEM observation results of the semiconductor device  990  and the comparative example. 
     Cross-sectional views in the lower side of  FIG.  23    show regions of the semiconductor device  990 , which correspond to a region  991  indicated by dashed-dotted lines in the cross-sectional view in the upper left. In addition, a cross-sectional view in the upper right shows a region of the comparative transistor corresponding to the region  991 . 
     Here, in the region  991  of each transistor, an interface between the conductor  240  and the oxide  230   b  and an extended surface thereof are indicated by dashed lines. The interface between the oxide  230   c  and the oxide  230   b  is also indicated by dashed lines. It was found that, in each of the comparative example and the semiconductor device  990 , the interface between the oxide  230   c  and the oxide  230   b  is positioned lower than the extended surface of the interface between the conductor  240  and the oxide  230   b . In other words, it was found that part of the oxide  230  was removed in the step of removing part of the conductor  240 . 
     Accordingly, the distance between the upper dashed lines and the lower dashed lines, which is denoted by arrows, is the amount of the oxide  230  partly removed in the step of removing part of the conductor  240  (hereinafter also referred to as depression amount).  FIG.  24    shows the depression amount in the channel portion of (etching amount of channel part) each of the transistors  200 . 
     According to the results in  FIG.  24   , the depression amount of each of the comparative transistor and the transistor  200 ( 1 , 1 ) was greater than or equal to 3.0 nm. In contrast, the depression amount of the transistor  200 ( 3 , 3 ) was approximately 2.0 nm, and the depression amount of each of the transistor  200 ( 6 , 6 ), the transistor  200 ( 45 , 35 ), and the transistor  200 ( 65 , 65 ) was less than 2 nm. 
     This indicates that in the step of removing part of the conductor  240 , variations in processing occur depending on a layout. In particular, it was found that the etching amount of the transistor  200 ( 1 , 1 ) disposed in the endmost portion of the circuit region was the largest. On the other hand, it was found that the depression amounts of the transistors  200  from the transistor  200 ( 3 , 3 ) which is positioned close to the center side than the endmost portion to the transistor  200 ( 65 , 65 ) which is positioned in the center portion or inner than the transistor  200 ( 3 , 3 ), were substantially uniform. 
     Furthermore, the depression amount of the comparative transistor around which other transistors are not provided was substantially the same as that of the transistor  200 ( 1 , 1 ). From these results, loading effect probably occurs in the semiconductor device  990  in the step of removing the conductor  240 . 
     Here, in a region where the degree of variations in processing is large, variations in transistors can be probably inhibited by providing a sacrificial element. Specifically, in the case where a region with low pattern density and a region with high pattern density are adjacent to each other, variations in processing depending on the layout occur in the periphery of the region with high pattern density. That is, by providing a sacrificial element between regions with different pattern densities, variations in transistors included in the region with high pattern density can be inhibited. 
     At least part of this example can be implemented in combination with the other embodiments described in this specification as appropriate. 
     REFERENCE NUMERALS 
       10 : substrate,  11 : region,  12 : region,  13 : region,  14 : region,  15 : substrate,  16 : circuit region,  18 : separation region,  21 : dummy element,  22 : element,  23 : film,  26 : structure body,  26 A: film,  27 : film,  28 : structure body,  29 : mask