Patent Publication Number: US-2023145588-A1

Title: Semiconductor packages and methods of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. Pat. Application No. 16/264,599 filed Jan. 31, 2019, now issued as U.S. Pat. 11,552,026, the contents of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to semiconductor packages and method of manufacturing the same, and, more particularly, to semiconductor packages including at least two semiconductor components and method of manufacturing the same. 
     2. Description of the Related Art 
     There is a continuing desire to incorporate more than one semiconductor component into a single semiconductor package to reduce dimensions of the package. A semiconductor package incorporating multiple semiconductor components may be referred to as a system in package (SiP). Because semiconductor components in a semiconductor package specify electrical connections to an external environment, such electrical connections and the process for making the same are important in determining whether the semiconductor components can function properly or can achieve specified performances. 
     SUMMARY 
     In an embodiment, a semiconductor package includes a substrate; a preformed feeding element; a preformed shielding element; and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element. 
     In an embodiment, a semiconductor package includes a substrate and a RF structure. The RF structure is disposed on the substrate and includes a feeding element and a shielding element adjacent to the feeding element, wherein a pitch from the feeding element to the shielding element is about 1000 µm to about 1500 µm with the insertion loss≥-0.5 dB under about 0.5 GHz to about 70 GHz. 
     In an embodiment, a semiconductor package includes a substrate and a RF structure. The RF structure is disposed on the substrate and includes a feeding element and a shielding element adjacent to the feeding element, wherein a pitch from the feeding element to the shielding element is about 1000 µm to about 1500 µm with the return loss≤-10 dB under about 0.5 MHz to about 80 MHz. 
     In an embodiment, a semiconductor package includes a substrate and a RF structure. The RF structure is disposed on the substrate and includes a feeding element and a shielding element adjacent to the feeding element, wherein a pitch from the feeding element to the shielding element is about 0 µm &lt;Pitch≤ about 800 µm with the insertion loss≥-0.5 dB under about 60 GHz to about 75 GHz. 
     In an embodiment, a semiconductor package includes a substrate and a RF structure. The RF structure is disposed on the substrate and includes a feeding element and a shielding element adjacent to the feeding element, wherein a pitch from the feeding element to the shielding element is about 0 µm &lt;Pitch≤ about 800 µm with the return loss≦-10 dB under about 0.5 MHz to about 80 MHz. 
     In an embodiment, a method of manufacturing includes (a) forming a RF structure on a substrate, the RF structure including a feeding element and a shielding element adjacent to the feeding element; and (b) molding the substrate, the feeding element and the shielding element. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 ( a )  illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  1 ( b )  illustrates a top view of the second semiconductor component of  FIG.  1 ( a )  along with A-A line in accordance with an embodiment of the present disclosure. 
         FIG.  1 ( c )  illustrates an enlarged view of an area B of the embodiment of a second semiconductor component illustrated in  FIG.  1 ( a ) . 
         FIG.  2    illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  3 ( a )  illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  3 ( b )  illustrates an enlarged view of an area C of the conductive via of the embodiment of a third semiconductor component illustrated in  FIG.  3 ( a ) . 
         FIG.  3 ( c )  illustrates an enlarged view of an area D of the embodiment of a second semiconductor component illustrated in  FIG.  3 ( a ) . 
         FIG.  4    illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  5    illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  6    illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  7    illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  8    illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  9    illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  10 ( a )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. 
         FIG.  10 ( b )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. 
         FIG.  11 ( a )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. 
         FIG.  11 ( b )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. 
         FIG.  11 ( c )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. 
         FIG.  11 ( d )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. 
         FIG.  11 ( e )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. 
         FIG.  12 ( a )  and  FIG.  12 ( b )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package of  FIG.  1 ( a ).   
         FIG.  12 ( a ) ,  FIG.  12 ( b ) , and  FIG.  12 ( c )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package of  FIG.  3 ( a ) . 
         FIG.  12 ( a ) ,  FIG.  12 ( b ) ,  FIG.  12 ( c ) , and  FIG.  12 ( d )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package of  FIG.  4   . 
         FIG.  12 ( a ) ,  FIG.  12 ( b ) ,  FIG.  12 ( c ) ,  FIG.  12 ( d ) , and  FIG.  12 ( e )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package of  FIG.  5   . 
         FIG.  12 ( a ) ,  FIG.  12 ( b ) ,  FIG.  12 ( c ) ,  FIG.  12 ( d ) ,  FIG.  12 ( e ) , and  FIG.  12 ( f )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package of  FIG.  7   . 
     
    
    
     DETAILED DESCRIPTION 
     Spatial descriptions, such as “top,” “side,” “over,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated by such arrangement. 
       FIG.  1 ( a )  illustrates a cross-sectional view of a semiconductor package  100  according to an embodiment of the present disclosure. The semiconductor package  100  includes a substrate  101 , a first semiconductor component  102 , a second semiconductor component  104 , and an encapsulant  106 . 
     The substrate  101  has a first surface  101   a , a second surface  101   b , and a side surface  101   c . The first surface  101   a  is opposite to the second surface  101   b . The side surface  101   c  extends between the first surface  101   a  and the second surface  101   b . In the embodiment illustrated in  FIG.  1 ( a ) , the substrate  101  includes at least one bonding pad  114  disposed adjacent to the first surface  101   a  of the substrate  101 . The bonding pad  114  may be, for example, a contact pad of a trace. In the embodiment of  FIG.  1 ( a ) , the first surface  101   a  is an active surface, the bonding pad  114  is a contact pad, and the bonding pad  114  is disposed directly (e.g., in physical contact) on the first surface  101   a  of the substrate  101 . The bonding pad  114  may include, for example, copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc, other metals, metal alloys, or a combination of two or more thereof. 
     The first semiconductor component  102  is disposed on the first surface  101   a  of the substrate  101 . The first semiconductor component  102  may be any semiconductor component including, for example, a chip, a package, an interposer, or a combination thereof. In the embodiment illustrated in  FIG.  1 ( a ) , the first semiconductor component  102  is a chip including at least one conductive connector  112 . The first conductive connector  112  contacts the bonding pad  114 . The conductive connector  112  may be, for example, a pillar structure, which may include an under bump metallization (UBM) layer, a pillar, a barrier layer, a solder layer, or a combination of two or more thereof, or solder/stud bumps. 
     The second semiconductor component  104  is disposed on the first surface  101   a  of the substrate  101 . The second semiconductor component  104  may be any semiconductor component including, for example, a RF structure. A RF structure may include at least one feeding element and at least one shielding element. According to the present disclosures, the feeding element and the shielding element were pre-formed so that their properties can be pre-determined and formed in any desired shape, for example, including square-like, triangular-like, round-like, rectangular-like, pentagonal-like, hexagonal-like, heptagonal-like, octagonal-like, trapezoidal-like, oval-like, rhombic-like, or parallelogram-like column shape. Unlike a feeding via or shielding via or ground via formed by photolithography in combination with etching (or drilling) and electroplating on a substrate, where the shape of the via fully depends on the drilling or etching technology and the properties of the via fully depends on the electroplating technology, the feeding element and the shielding element according to the embodiments of the present disclosures are pre-formed, for example, by molding, where their shape and properties can be controlled. Therefore, the voids in the feeding via or shielding via or ground via caused by electroplating can be avoided, which can reduce the signal loss. 
     In the embodiment illustrated in  FIG.  1 ( a ) , the second semiconductor component  104  includes at least one preformed feeding element  104   b  disposed on the first surface  101   a  of the substrate  101  and at least one preformed shielding element  104   a ,  104   c  disposed on the first surface  101   a  of the substrate  101  and adjacent to the preformed feeding element  104   b . The preformed feeding element  104   b  and the preformed shielding element  104   a ,  104   c  are spaced from each other by a distance. The shielding element  104   a ,  104   c  may include a plurality of pieces  104   a ,  104   c  spacing apart from each other. The feeding element  104   b  and the shielding element  104   a ,  104   c  may be disposed on the substrate  101  by a surface mount technology (SMT). In the embodiment illustrated in  FIG.  1   , the feeding element  104   b  and the shielding element  104   a ,  104   c  are disposed on the substrate  101  by a surface mount technology (SMT) with a solder paste  110 . 
     The encapsulant  106  is disposed between the first semiconductor component  102  and the second semiconductor component  104 . The encapsulant  106  encapsulates the preformed feeding element  104   b  and the preformed shielding element  104   a ,  104   c . In the embodiment illustrated in  FIG.  1 ( a ) , the preformed feeding element  104   b  defines a first space in the encapsulant  106  and the preformed shielding element  104   a ,  104   c  defines a second space in the encapsulant  106 , where the encapsulant  106  surrounds them and accommodates the first space and the second space. The encapsulant  106  may extend from the preformed shielding element  104   a  to the first semiconductor component  102 . The encapsulant  106  may cover the first semiconductor component  102 , the preformed feeding element  104   b , the preformed shielding element  104   a ,  104   c , and the first surface  101   a  of the substrate  101 , but not the side surface  101   c  of the substrate  101 . The encapsulant  106  may be, for example, a solder mask (the material of which is, for example, polyimide (PI)), a passivation layer (the material of which is, for example, a metal oxide), or an underfill. The encapsulant  106  may include fillers, the material of which is, for example, silica and/or carbon for reducing stress on the die and warpage of a resulting semiconductor package. 
       FIG.  1 ( b )  illustrates a top view of the second semiconductor component  104  of  FIG.  1 ( a )  along with A-A line in accordance with an embodiment of the present disclosure. The second semiconductor component  104  comprises one feeding element  104   b  and one shielding element  104   a ,  104   c . The shielding element  104   a ,  104   c  surrounds the feeding element  104   b . The shielding element  104   a ,  104   c  comprises two pieces  104   a ,  104   c  spacing apart from each other and includes at least one opening between them. The shielding element  104   a ,  104   c  are disposed adjacent to the feeding element  104   b  and are at the opposite sides of each other. The distance X from the center of the shielding element  104   a ,  104   b  to the center of the feeding element  104   b  (a pitch) is determined according to the desired properties of the second semiconductor component  104 . 
     In an embodiment of the present disclosures, the pitch X can be about 1000 µm to about 1500 µm for a RF structure with an insertion loss≧-0.5 dB under about 0.5 GHz to about 70 GHz. 
     In an embodiment of the present disclosures, the pitch X can be about 1000 µm to about 1200 µm for a RF structure with an insertion loss≧-0.5 dB under about 0.5 GHz to about 70 GHz. 
     In an embodiment of the present disclosures, the pitch X can be about 1300 µm to about 1500 µm for a RF structure with an insertion loss≧-0.5 dB under about 0.5 GHz to about 70 GHz. 
     In an embodiment of the present disclosures, the pitch X can be about 1000 µm to about 1500 µm for a RF structure with a return loss≤-10 dB under about 0.5 MHz to about 80 MHz. 
     In an embodiment of the present disclosures, the pitch X can be about 1300 µm to 1500 µm with the return loss≤-10 dB under about 0.5 MHz to about 60 MHz. 
     In an embodiment of the present disclosres, the pitch X can be about 0 µm &lt;Pitch≤800 µm with the insertion loss≥-0.5 dB under about 60 GHz to about 75 GHz. 
     In an embodiment of the present disclosures, the pitch X can be about 0 µm &lt;Pitch≤800 µm with the return loss≤-10 dB under about 60 MHz to about 80 MHz. 
     The feeding element  104   b  and the shielding element  104   a ,  104   c  are all surrounded by the encapsulant  106 . The feeding element  104   b  and the shielding element  104   a ,  104   c  can be in different shape depending on the molding technology or the technology to be used to form them. In the embodiment illustrated in  FIG.  1 ( b ) , an outer boundary of the feeding element  104   b  is similar to an outer boundary of the shielding element  104   a  and an outer boundary of the shielding element  104   a  can be similar to an outer boundary of the opposite shielding element  104   c . In the embodiment illustrated in  FIG.  1 ( b ) , the feeding element  104   b  and the shielding elements  104   a ,  104   c  have a round-like column shape 
       FIG.  1 ( c )  illustrates an enlarged view of an area B of the embodiment of a second semiconductor component  104  illustrated in  FIG.  1 ( a ) . In the embodiment illustrated in  FIG.  1 ( c ) , the encapsulant  106  includes fillers  122 . The fillers  122  are adjacent to the feeding element  104   b  and the shielding elements  104   a ,  104   c . The fillers  122  may be in regular or irregular shape. In the embodiment illustrated in  FIG.  1 ( c ) , the shape of the fillers  122  remain intact because the feeding element  104   b  and the shielding elements  104   a ,  104   c  are preformed in accordance with the embodiments of the present disclosures rather than formed by photolithography in combination with etching (or drilling) and electroplating. Therefore, the fillers  122  in the encapsulant  106  are not damaged by the etching or drilling and the shape thereof can remain intact. Accordingly, the effect of the fillers  122 , such as reducing stress on the die and warpage of a resulting semiconductor package, will not be compromised and can be maintained. 
       FIG.  2    illustrates a cross-sectional view of a semiconductor package  200  according to an embodiment of the present disclosure. The semiconductor package  200  in  FIG.  2    is similar to the semiconductor package  100  in  FIG.  1   , with differences including that the semiconductor package  200  includes a first encapsulant  216  and a second encapsulant  206 . The first encapsulant  216  is adjacent to the second encapsulant  206 . The first encapsulant  216  encapsulates the second semiconductor component  204 . In particular, the first encapsulant  216  covers the preformed feeding element  204   b , the preformed shielding element  204   a ,  204   c , and the first surface  201   a  of the substrate  201 , but not the side surface  201   c  of the substrate  201 . The second encapsulant  206  covers the first semiconductor component  202  and the first surface  201   a  of the substrate  201 , but not the side surface  201   c  of the substrate  201 . The first encapsulant  216  and the second encapsulant  206  are composed of different materials. The first encapsulant  216  and the second encapsulant  206  may include fillers, the material of which is, for example, silica and/or carbon for reducing stress on the die and warpage of a resulting semiconductor package. 
       FIG.  3 ( a )  illustrates a cross-sectional view of a semiconductor package  300  according to an embodiment of the present disclosure. The semiconductor package  300  in  FIG.  3    is similar to the semiconductor package  100  in  FIG.  1   , with differences including that the semiconductor package  300  further includes a third semiconductor component  318  disposed in the encapsulant  306 . The third semiconductor component  318  is disposed between the first semiconductor component  302  and the second semiconductor component  304 . The third semiconductor component  318  may be, for example, a compartment separating the first semiconductor component  302  from the second semiconductor component  304 , or a conductive via. In the embodiment illustrated in  FIG.  3 ( a ) , the third semiconductor component  318  is a conductive via extending through the encapsulant  306  from the substrate  308  to the surface of the encapsulant  306  and formed by drilling (or etching) and electroplating. 
       FIG.  3 ( b )  illustrates an enlarged view of an area C of the conductive via  318  of the embodiment of a third semiconductor component  318  illustrated in  FIG.  3 ( a ) .  FIG.  3 ( c )  illustrates an enlarged view of an area D of the embodiment of a second semiconductor component  304  illustrated in  FIG.  3 ( a ) . The encapsulant  306  includes fillers  320  adjacent to the conductive via  318  and fillers  322  adjacent to the feeding element  304   b  and the shielding elements  304   a ,  304   c . As described above for  FIG.  1 ( c ) , the fillers  322  adjacent to the feeding element  304   b  and the shielding elements  304   a ,  304   c  remain intact in shape and so are their effects. Contrary to those fillers  322  adjacent to the feeding element  304   b  and the shielding elements  304   a ,  304   c , fillers  320  adjacent to the conductive via  318  cannot remain intact in shape as they are damaged by a drilling or etching process for forming the conductive via. Accordingly, the effect of the fillers  320  adjacent to a via formed by a drilling or etching process, for example, in reducing stress or warpage of a resulting semiconductor package will be reduced. Therefore, comparing a semiconductor component which is preformed to that is formed by drilling (or etching) and electroplating, the efficacy of an encapsulant adjacent to them will be different and deteriorated. 
       FIG.  4    illustrates a cross-sectional view of a semiconductor package  400  according to an embodiment of the present disclosure. The semiconductor package  400  in  FIG.  4    is similar to the semiconductor package  300  in  FIG.  3 ( a ) , with differences including that the semiconductor package  400  includes a conductive layer  424  disposed on the encapsulant  406 . The conductive layer  424  covers the top surface  406   a  of the encapsulant  406 , the side surfaces  406   b ,  406   c  of the encapsulant  406 , the exposed surface of the second semiconductor component  404  (including the feeding element  404   b  and the shielding elements  404   a ,  404   c ), and the exposed surface of the third semiconductor component  418 . The conductive layer  424  may be, for example, a shielding layer or a conformal shielding layer. 
       FIG.  5    illustrates a cross-sectional view of a semiconductor package  500  according to an embodiment of the present disclosure. The semiconductor package  500  in  FIG.  5    is similar to the semiconductor package  400  in  FIG.  4   , with differences including that the conductive layer  524  disposed on the encapsulant  506  covers the top surface  506   a  of the encapsulant  506 , a single one of the side surfaces  506   b ,  506   c  of the encapsulant  506 , the exposed surface of the third semiconductor component  518 , but not the exposed surface of the second semiconductor component  504  (including the feeding element  504   b  and the shielding elements  504   a ,  504   c ). 
       FIG.  6    illustrates a cross-sectional view of a semiconductor package  600  according to an embodiment of the present disclosure. The semiconductor package  600  in  FIG.  6    is similar to the semiconductor package  300  in  FIG.  3 ( a ) , with differences including that the semiconductor package  600  includes a connector  628  disposed on the encapsulant  606 . The connector  628  is disposed adjacent to the second semiconductor component  604 . In the embodiment illustrated in  FIG.  6   , the connector  628  is disposed on the feeding element  604   b  and the shielding element  604   a ,  604   c . The connector  628  may be, for example, a connector for connecting to an antenna layer. 
       FIG.  7    illustrates a cross-sectional view of a semiconductor package  700  according to an embodiment of the present disclosure. The semiconductor package  700  in  FIG.  7    is similar to the semiconductor package  500  in  FIG.  5   , with differences including that the semiconductor package  700  includes a connector  728  disposed on the encapsulant  706 . The connector  728  is disposed adjacent to the second semiconductor component  704 . In the embodiment illustrated in  FIG.  7   , the connector  728  is disposed on the feeding element  704   b  and the shielding element  704   a ,  704   c . The connector  728  may be, for example, a connector for connecting to an antenna layer. 
       FIG.  8    illustrates a cross-sectional view of a semiconductor package  800  according to an embodiment of the present disclosure. The semiconductor package  800  in  FIG.  8    is similar to the semiconductor package  700  in  FIG.  7   , with differences including that the semiconductor package  800  includes an antenna layer  830  disposed adjacent to the feeding element  804   b  and the shielding elements  804   a ,  804   c  and electrically connected to the feeding element  804   b  and the shielding element  804   a ,  804   c . In the embodiment illustrated in  FIG.  8   , the antenna layer  830  includes a second connector  832  connecting to the first connector  828  disposed on the feeding element  804   b  and the shielding elements  804   a ,  804   c . 
       FIG.  9    illustrates a cross-sectional view of a semiconductor package  900  according to an embodiment of the present disclosure. The semiconductor package  900  in  FIG.  9    is similar to the semiconductor package  100  in  FIG.  1 ( a ) , with differences including that the semiconductor package  900  includes a third semiconductor component  934  disposed on the substrate  908  and the encapsulant  906  exposes the second semiconductor component  904  and the third semiconductor component  934 . The third semiconductor component  934  is disposed on the first surface  901   a  of the substrate  901  and may be at the same side or opposite side of the second semiconductor component  904 . The third semiconductor component  934  may be any semiconductor component including, for example, a RF structure, a chip, a package, an interposer, or a combination thereof. The third semiconductor component  934  may be the same or different from the second semiconductor component  904 . In the embodiment illustrated in  FIG.  9   , the third semiconductor component  934  is a RF structure including includes at least one preformed feeding element  934   b  and at least one preformed shielding element  934   a ,  934   c  and disposed at the opposite side of the second semiconductor component  904 . 
       FIG.  10 ( a )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. The second semiconductor component  1004  comprises one feeding element  1004   b  and four pieces of shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e . The four pieces of shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e  are disposed adjacent to the feeding element  1004   b . The four pieces of shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e  surround the feeding element  1004   b . The shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e  includes an opening between each pieces  1004   a ,  1004   c ,  1004   d ,  1004   e . The four pieces of shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e  are spaced apart from each other by the encapsulant  1006 . The four pieces of shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e  may surround the feeding element  1004   b  in any arrangement, for example, in a square-like, round-like, rectangular-like, trapezoidal-like, oval-like, rhombic-like, or parallelogram-like arrangement. In the embodiment illustrated in  FIG.  10 ( a ) , the four pieces of shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e  surround the feeding element  1004   b  in a round-like arrangement. 
       FIG.  10 ( b )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. The second semiconductor component  1005  in  FIG.  10 ( b )  is similar to the second semiconductor component  1004  in  FIG.  10 ( a ) , with differences including that the second semiconductor component  1005  includes eight pieces of shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e ,  1004   f ,  1004   g ,  1004   h ,  1004   i  disposed adjacent to the feeding element  1004   b . The eight pieces of shielding element  1004   a ,  1004   c ,  1004   d ,  1004   e ,  1004   f ,  1004   g ,  1004   h ,  1004   i  surround the feeding element  1004   b  in a round-like arrangement. 
       FIG.  11 ( a )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. The second semiconductor component  1104  in  FIG.  11 ( a )  is similar to the second semiconductor component  104  in  FIG.  1 ( b ) , with differences including that the shielding element  1104   a ,  1104   c  are preformed in a rectangular-like column shape. 
       FIG.  11 ( b )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. The second semiconductor component  1105  in  FIG.  11 ( b )  is similar to the second semiconductor component  1104  in  FIG.  11 ( a ) , with differences including that the second semiconductor component  1105  includes three pieces of shielding element  1105   a ,  1105   c ,  1105   d  disposed adjacent to the feeding element  1105   b . The three pieces of shielding element  1105   a ,  1105   c ,  1105   d  surround the feeding element  1105   b . The three pieces of shielding element  1105   a ,  1105   c ,  1105   d  may surround about ¾ of the surroundings of the feeding element  1105   b . 
       FIG.  11 ( c )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. The second semiconductor component  1107  in  FIG.  11 ( c )  is similar to the second semiconductor component  1105  in  FIG.  11 ( b ) , with differences including that the three pieces of shielding element  1107   a ,  1107   c ,  1107   d  contact each other and there is no opening between each of them. 
       FIG.  11 ( d )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. The second semiconductor component  1109  in  FIG.  11 ( c )  is similar to the second semiconductor component  1105  in  FIG.  11 ( b ) , with differences including that there are four pieces of shielding element  1109   a ,  1109   c ,  1109   d ,  1109   e  surround the feeding element  1109   b . The four pieces of shielding element four pieces of shielding element  1109   a ,  1109   c ,  1109   d ,  1109   e  surround the feeding element  1109   b  in a square-like arrangement. 
       FIG.  11 ( e )  illustrates a top view of a second semiconductor component in accordance with embodiments of the present disclosure. The second semiconductor component  1111  in  FIG.  11 ( e )  is similar to the second semiconductor component  1109  in  FIG.  11 ( d ) , with differences including that the four pieces of shielding element  1111   a ,  1111   c ,  1111   d ,  1111   e  contact each other and there is no opening between each of them. 
       FIG.  12 ( a )- 12 ( b )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package  100  of  FIG.  1 ( a ) .  FIG.  12 ( a )- 12 ( c )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package  300  of  FIG.  3 ( a ) .  FIG.  12 ( a )- 12 ( d )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package  400  of  FIG.  4   .  FIG.  12 ( a )- 12 ( e )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package  500  of  FIG.  5   .  FIG.  12 ( a )- 12 ( f )  illustrate a method for manufacturing a semiconductor package such as the semiconductor package  700  of  FIG.  7   . 
     Referring to  FIG.  12 ( a ) , a first semiconductor component  702  and a second semiconductor component  704  are provided on a substrate  701 . The first semiconductor component  702  is a chip including at least one conductive connector  712 . The second semiconductor component  704  is a RF structure including at least one feeding element  704   b  and at least one shielding element  704   a ,  704   c . The substrate  701  includes at least one bonding pad  714 . The shielding element comprises two pieces  704   a ,  704   c . The feeding element  704   b  and the shielding element  704   a ,  704   c  were preformed in a round-like column shape by a molding technology before being provided on the substrate  701 . The preformed feeding element  704   b  and the preformed shielding element  704   c  are disposed on the substrate  701  by a surface mounted technology (SMT). The temperature of the SMT process is preferably controlled below about 200° C. The working temperature of the solder paste  710  is preferably below about 200° C. in the SMT process. 
     Referring to  FIG.  12 ( b ) , an encapsulant  706  is disposed between the first semiconductor component  702  and the second semiconductor component  704  by, for example, molding. The encapsulant  706  encapsulates the first semiconductor component  702 , the preformed feeding element  704   b  and the preformed shielding element  704   a ,  704   c . The encapsulant  706  covers the first semiconductor component  702 , the preformed feeding element  704   b  and the preformed shielding element  704   a ,  704   c , surrounds the preformed feeding element  704   b  and the preformed shielding element  704   a ,  704   c , and extends from the preformed shielding element  704   a  to the first semiconductor component  702 . The encapsulant  706  may be, for example, a solder mask (the material of which is, for example, polyimide (PI)) or a passivation layer (the material of which is, for example, a metal oxide) or an underfill. The encapsulant  706  may include a filler, the material of which is, for example, silica and/or carbon. 
     Referring to  FIG.  12 ( c ) , a third semiconductor component  718  is disposed in the encapsulant  706 . The third semiconductor component  718  is disposed between the first semiconductor component  702  and the second semiconductor component  704 . The third semiconductor component  718  may be, for example, a compartment separating the first semiconductor component  702  from the second semiconductor component  704 , or a conductive via. The encapsulant  706  defines the location for forming the compartment or the conductive via. The compartment or conductive via may be formed by drilling (or etching) and electroplating. Accordingly, as described above for the encapsulant  706  including fillers adjacent to the compartment or conductive via  718 , they cannot remain intact in shape as they are damaged by the drilling or etching process and therefore their effects in the encapsulant  706  as fillers will be deteriorated. 
     Referring to  FIG.  12 ( d ) , the encapsulant  706  is ground to expose the second semiconductor component  704 . Subsequently, a separation technique (e.g., sawing) is performed to obtain individual semiconductor packages such as the semiconductor package  300  of  FIG.  3 ( a ) . A conductive layer  724  is disposed on the encapsulant  706  by, for example, a electroplating technology where it covers the top surface  706   a  of the encapsulant  706 , the side surfaces  706   b ,  706   c  of the encapsulant  706 , the exposed surface of the second semiconductor component  704  (including the feeding element  704   b  and the shielding elements  704   a ,  704   c ), and the exposed surface of the third semiconductor component  718 . The conductive layer  724  may be, for example, a shielding layer or a conformal shielding layer. 
     Referring to  FIG.  12 ( e ) , the conductive layer  724  is disposed on the encapsulant  706  where it selectively covers the top surface  706   a  of the encapsulant  706 , one of the side surfaces  706   b ,  706   c  of the encapsulant  706 , the exposed surface of the third semiconductor component  718  except for the exposed surface of the second semiconductor component  704 . The conductive layer  724  may be, for example, a shielding layer or a conformal shielding layer, and be formed by photolithography in combination with etching and electroplating or physical vapor deposition. 
     Referring to  FIG.  12 ( f ) , a connector  728  is disposed on the encapsulant  706 . The connector  728  is disposed adjacent to the second semiconductor component  704 . In the embodiment illustrated in  FIG.  7   , the connector  728  is disposed on the feeding element  704   b  and the shielding elements  704   a ,  704   c . The connector  728  may be, for example, a connector for connecting to an antenna layer. The connector  728  may be formed by photolithography in combination with etching and electroplating or physical vapor deposition. 
     As used herein and not otherwise defined, the term “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the term can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the term can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. 
     While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.