Patent Publication Number: US-11657765-B2

Title: Display device and method of driving the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority from and the benefit of Korean Patent Application No. 10-2020-0120255, filed on Sep. 18, 2020, which is hereby incorporated by reference for all purposes as if fully set forth herein. 
     BACKGROUND 
     Field 
     Embodiments of the invention relate generally to a display device and, more specifically to a display device capable of preventing image sticking and a method of driving the display device. 
     Discussion of the Background 
     As display devices, an organic light emitting display device, a liquid crystal display device, a plasma display device, and the like are being used. 
     Among them, the organic light emitting display device has advantages, such as high brightness, ultra-thin thickness, etc., since the organic light emitting display device employs a self-emissive element that allows an organic light emitting layer to emit a light using a recombination of electrons and holes. 
     The above information disclosed in this Background section is only for understanding of the background of the inventive concepts, and, therefore, it may contain information that does not constitute prior art. 
     SUMMARY 
     Applicant recognized that when an organic light emitting display device is driven for a long time in the same pattern, one or more light emitting elements may be burned in due to the increase of current stress, and as a result, image sticking occurs in areas where fixed patterns or logos are displayed for a long time. 
     Display devices constructed according to the principles and embodiments of the invention and illustrative methods of driving the same are capable of effectively preventing image sticking and improving image burn-in. For example, image shifting may be employed in which the display image is periodically shifted in a display device supporting a variable frequency mode. 
     Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts. 
     According to one aspect of the invention, a display device includes: a display panel to display an image, a panel driver to drive the display panel, and a controller to control a driving of the panel driver. The controller includes a first circuit to receive frame data during an active period in synchronization with a vertical synchronization signal determining a start time point of a frame having the active period and a variable blank period, to shift a position of the frame data in response to a shift start signal to generate shift data, and to provides the shift data to the panel driver. A number of active periods of the vertical synchronization signal included in one period of the shift start signal differs from the number of active periods of the vertical synchronization signal included in another period of the shift start signal. 
     The controller may further include a second circuit to count the variable blank period based on a reference clock to generate a count value of the frame, to compare a cumulative value obtained by cumulating the count value with a predetermined reference value, and to determine an activation time point of the shift start signal according to the compared result. 
     The second circuit may include a shift determiner including a counter to count a number of occurrences of the reference clock during the variable blank period to output a first count value and a calculator to add a pre-stored second count value of the active period and the first count value to calculate the count value. 
     The active period may have a substantially constant duration every frame, and the variable blank period may have a variable duration. 
     The controller may be configured to receive the frame data in response to a data enable signal, and the counter may be configured to count a non-active period of the data enable signal to generate the first count value. 
     The controller may further include a first memory in which the second count value is stored. 
     The shift determiner may further include an adder to add the count value and a previous cumulative value to output the cumulative value and a comparator to compare the cumulative value with the reference value and to output a shift control signal according to the compared result. 
     The controller may further include a second memory configured to receive the cumulative value output from the adder and to update the previous cumulative value to the cumulative value. 
     The shift determiner may further include a signal generator to receive the shift control signal to control the activation time point of the shift start signal and to provide the shift start signal to the image processor. 
     The shift determiner may further include a preliminary comparator to compare the count value with the reference value. 
     The preliminary comparator may be configured to provide the count value to the adder when the count value is smaller than the reference value and to output a pre-shift control signal when the count value is greater than the reference value. 
     The shift determiner may further include a signal generator to receive the pre-shift control signal to control the activation time point of the shift start signal and to provide the shift start signal to the image processor. 
     The display panel may include a plurality of pixels each comprising a light emitting element. 
     The first circuit may include an image processor including a shift processor to determine a pixel shift amount based on shift setting information and to generate initial shift data obtained by shifting the frame data according to the pixel shift amount and a shift direction and a data compensator to compensate for the initial shift data to generate the shift data. 
     The data compensator may include an area setter to set first and second compensation areas according to the pixel shift amount and the shift direction, a first sub-compensator to scale up first sub-shift data corresponding to the first compensation area among the initial shift data to generate first compensation data, and a second sub-compensator to scale down second sub-shift data corresponding to the second compensation area among the initial shift data to generate second compensation data. 
     According to one aspect of the invention, a method of driving a display device, the method includes the steps of: receiving frame data during an active period in synchronization with a vertical synchronization signal determining a start time point of a frame having the active period and a variable blank period, setting a period of a shift start signal based upon the variable blank period, shifting the frame data in response to the shift start signal to generate shift data, converting the shift data to a data signal, and displaying an image using the data signal. A number of active periods of the vertical synchronization signal included in one period of the shift start signal differs from the number of active periods of the vertical synchronization signal included in another period of the shift start signal. 
     The step of setting the period of the shift start signal may include the steps of counting the variable blank period based on a reference clock to generate a count value of the frame, comparing a cumulative value obtained by cumulating the count value with a predetermined reference value, and determining an activation time point of the shift start signal according to the compared result. 
     The step of determining the activation time point of the shift start signal may include the steps of generating the count value of the frame, adding the count value and a pre-stored previous cumulative value to generate the cumulative value, comparing the cumulative value with the reference value to output a shift control signal according to the compares result, and activating the shift start signal in response to the shift control signal. 
     The step of calculating the count value may further include the steps of counting a number of occurrences of the reference clock during the variable blank period to output a first count value and adding a pre-stored second count value of the active period and the first count value to calculate the count value. 
     The active period may have a substantially constant duration every frame, and the variable blank period may have a variable duration. 
     The variable blank period may be generated after the active period in the frame is generated. 
     The step of receiving the frame data may include receiving the frame data in response to a data enable signal, and the step of outputting the first count value may include counting a non-active period of the data enable signal to generate the first count value. 
     The method may further include the step of receiving the count value and updating the previous cumulative value to the cumulative value. 
     The method may further include the step of comparing the count value with the reference value prior to the outputting of the cumulative value. 
     The step of comparing of the count value with the reference value may include the steps of adding the count value and the previous cumulative value when the count value is smaller than the reference value and outputting a pre-shift control signal when the count value is greater than the reference value. 
     The method may further include the step of activating the shift start signal in response to the pre-shift control signal. 
     The step of generating of the shift data may include the steps of determining a pixel shift amount based on shift setting information to generate initial shift data obtained by shifting the frame data according to the pixel shift amount and a shift direction and compensating for the initial shift data to generate the shift data. 
     The step of compensating for the initial shift data may include the steps of setting first and second compensation areas according to the pixel shift amount and the shift direction, scaling up first sub-shift data corresponding to the first compensation area among the initial shift data to generate first compensation data, and scaling down second sub-shift data corresponding to the second compensation area among the initial shift data to generate second compensation data. 
     It is to be understood that both the foregoing general description and the following detailed description are illustrative and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate illustrative embodiments of the invention, and together with the description serve to explain the inventive concepts. 
         FIG.  1    is a block diagram of an embodiment of an electronic apparatus constructed according to the principles of the invention. 
         FIG.  2    is a block diagram of an embodiment of the display device of  FIG.  1   . 
         FIG.  3    is a waveform diagram showing illustrative frame data input to the display device of  FIG.  2    in a variable frequency mode. 
         FIG.  4    is a plan view of an embodiment of the display panel of  FIG.  1   . 
         FIG.  5    is a block diagram of an embodiment of the controller of  FIG.  2   . 
         FIG.  6    is a block diagram of an embodiment of the shift determiner of  FIG.  5   . 
         FIG.  7 A  is an illustrative waveform diagram showing a relation between a vertical synchronization signal and a shift start signal as input and output signals of the signal generator of  FIG.  6   . 
         FIG.  7 B  is an illustrative waveform diagram showing an activation time point of the shift start signal and a shift control signal as output and input signals of the signal generator of  FIG.  6   . 
         FIG.  8    is a block diagram of an embodiment of the image processor of  FIG.  5   . 
         FIGS.  9 A and  9 B  are views of embodiments of shift directions of an image according to the principles of the invention. 
         FIG.  10    is a view of an embodiment showing a pixel shift according to an image shift operation by the image processor of  FIG.  5   . 
         FIG.  11    is an illustrative waveform diagram showing a refresh operation of the display device operated in an ultra-low frequency mode. 
         FIG.  12    is a block diagram of another embodiment of the shift determiner of  FIG.  5   . 
         FIG.  13    is an illustrative waveform diagram showing an activation time point of a shift start signal and a pre-shift control signal as output and input signals of the signal generator of  FIG.  12   . 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments. Further, various embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concepts. 
     Unless otherwise specified, the illustrated embodiments are to be understood as providing illustrative features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts. 
     The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements. 
     When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z-axes, and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure. 
     Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly. 
     The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. 
       FIG.  1    is a block diagram of an embodiment of an electronic apparatus constructed according to the principles of the invention.  FIG.  2    is a block diagram of an embodiment of the display device DD of  FIG.  1   .  FIG.  3    is a waveform diagram showing illustrative frame data input to the display device DD of  FIG.  2    in a variable frequency mode.  FIG.  4    is a plan view of an embodiment of the display panel DP of  FIG.  1   . 
     Referring to  FIG.  1   , the electronic apparatus ED may include a host processor  10  and the display device DD. The display device DD may be a device that is configured to display an image, and the host processor  10  may control a driving of the display device DD. As an example, the host processor  10  may be a graphic processing unit (GPU). The host processor  10  may apply an input image signal I_DAT and an input control signal I_CS to the display device DD to control a display operation of the display device DD. 
     The display device DD may include the display panel DP, a controller  100 , and a panel driver  200 . The display device DD may be a device that is activated in response to electrical signals. The display device DD may be applied to various electronic items, e.g., a tablet computer, a notebook computer, a computer, a television set, a smartphone, or the like. 
     The controller  100  may receive the input image signal I_DAT and the input control signal I_CS from the host processor  10 . The input image signal I_DAT may include a red image signal, a green image signal, and a blue image signal. The controller  100  may convert the data format of the input image signal I_DAT to generate image data RGB. The generated image data RGB may be provided to the panel driver  200 . The input control signal I_CS may include a vertical synchronization signal Vsync (refer to  FIG.  3   ), a data enable signal DE (refer to  FIG.  3   ), a master clock signal, and the like, however, the embodiments should not be limited thereto or thereby. The controller  100  may generate a panel control signal based on the input control signal I_CS. 
     The controller  100  may be operated in a variable frequency mode.  FIG.  3    is a waveform diagram showing frame data input to the display device DD of  FIG.  2    in a variable frequency mode. Referring to  FIGS.  1  and  3   , the host processor  10  may change the duration of a blank period BP 1  to BP 6  in every frame and may apply the input image signal I_DAT to the controller  100  at a variable frame rate. The controller  100  that operates in the variable frequency mode may provide the image data RGB to the panel driver  200  in synchronization with the variable frame rate, and thus, may control the panel driver  200  so that the image is be displayed at the variable frame rate. 
     As shown in  FIG.  3   , the speed at which the host processor  10  renders frame data FD 1  to FD 7 , that is, an internal processing speed, may not be substantially constant. The rendering speed may be changed depending on the frame data FD 1  to FD 7 . For example, the host processor  10  may render first, second, fourth, sixth, and seventh frame data FD 1 , FD 2 , FD 4 , FD 6 , and FD 7  at a frequency of about 144 Hz and may render third and fifth frame data FD 3  and FD 5  at a frequency of about 72 Hz. The time point at which the host processor  10  transmits the rendered frame data FD 1  to FD 7  to the controller  100  may be coincide with or may the a time point at which the rendering of corresponding frame data FD 1  to FD 7  is completed. 
     In a case where the second frame data FD 2  are rendered at a frequency of about 144 Hz, the host processor  10  may provide the first frame data FD 1  to the controller  100  at a frequency of about 144 Hz. The host processor  10  may provide the first frame data FD 1  to the controller  100  during a first active period AP 1  of a first frame FP 1 . The host processor  10  may provide the first frame data FD 1  at a first frame rate in the first frame FP 1 . 
     In a case where the third frame data FD 3  are rendered at a frequency of about 72 Hz, the host processor  10  may provide the second frame data FD 2  to the controller  100  at a frequency of about 72 Hz. The host processor  10  may provide the second frame data FD 2  to the controller  100  during a second active period AP 2  of a second frame FP 2 , and a second blank period BP 2  of the second frame FP 2  may be maintained until the rendering of the third frame data FD 3  is completed. That is, the host processor  10  may provide the second frame data FD 2  at a second frame rate in the second frame FP 2 . As an example, the first frame rate may be about 144 Hz, and the second frame rate may be about 72 Hz. 
     In the illustrated embodiment, the duration of the first active period AP 1  of the first frame FP 1  and the duration of the second active period AP 2  of the second frame FP 2  may be substantially the same as each other. That is, active periods AP 1  to AP 7  may have a substantially constant duration in every frame regardless of the frame rate. However, the duration of a first blank period BP 1  of the first frame FP 1  and the duration of the second blank period BP 2  of the second frame FP 2  may be different from each other. As an example, the duration of the second blank period BP 2  may be greater than the duration of the first blank period BP 1 . That is, the blank periods BP 1  to BP 6  in every frame FP 1  to FP 6  may have different durations depending on the frame rate. When the frame rate decreases, the duration of the corresponding blank period may increase. As described above, a mode in which the durations of the blank periods BP 1  to BP 6  are varied depending on the frame rate is referred to as the variable frequency mode, and the blank periods BP 1  to BP 6  having different durations from each other are referred to as variable blank periods. In every frame FP 1  to FP 6 , each of the variable blank periods BP 1  to BP 6  may occur after a corresponding active period among the active periods AP 1  to AP 6 . In the variable frequency mode, the host processor  10  may provide the input image signal I_DAT to the display device DD at irregular periods or irregular frequencies. 
     The active periods AP 1  to AP 6  of the frames FP 1  to FP 6  are defined as active periods of the data enable signal DE, and the blank periods BP 1  to BP 6  of the frames FP 1  to FP 6  are defined as non-active periods of the data enable signal DE. In the variable frequency mode, durations of the active periods of the data enable signal DE may be substantially constant regardless of the frame rate. Durations of the non-active periods of the data enable signal DE may be variable depending on the frame rate. The vertical synchronization signal Vsync may be activated at a start time point of every frame FP 1  to FP 6 . Depending on the frame rate, an active period of the vertical synchronization signal Vsync may also be variable. 
     Referring to  FIG.  2   , the panel driver  200  may include a scan driver  210  and a data driver  220 . The panel control signal may include a scan control signal SCS to control a driving of the scan driver  210  and a data control signal DCS to control a driving of the data driver  220 . 
     The scan driver  210  may receive the scan control signal SCS from the controller  100 . The scan control signal SCS may include a vertical start signal, which starts an operation of the scan driver  210 , and a vertical clock signal. The scan driver  210  may generate a plurality of scan signals SS and may sequentially output the scan signals SS to scan lines described below. In addition, the scan driver  210  may generate a plurality of emission control signals in response to the scan control signal SCS and may output the emission control signals to a plurality of emission control lines EML 1  to EMLn described below. 
     According to the illustrated embodiment, the scan driver  210  may include an initialization scan driver, a compensation scan driver, a write scan driver, and a black scan driver. The initialization scan driver outputs initialization scan signals to initialization scan lines GIL 1  to GILn of the display panel DP, and the compensation scan driver outputs compensation scan signals to compensation scan lines GWL 1  to GWLn of the display panel DP. The initialization scan driver and the compensation scan driver may be configured as independent circuits, respectively, or may be integrated into one circuit. When the initialization scan driver and the compensation scan driver are integrated into one circuit, the initialization scan signals may be defined as previous scan signals, and the compensation scan signals may be defined as current scan signals. 
     The write scan driver outputs write scan signals to write scan lines GDL 1  to GDLn of the display panel DP, and the black scan driver outputs black scan signals to black scan lines GBL 1  to GBLn of the display panel DP. The write scan driver and the black scan driver may be configured as independent circuits, respectively, or may be integrated into one circuit. When the write scan driver and the black scan driver are integrated into one circuit, the write scan signals may be defined as current scan signals, and the black scan signals may be defined as next scan signals. 
     In addition,  FIG.  2    shows a structure in which the scan lines and the emission control lines are connected to one scan driver  210 , however, the embodiments should not be limited thereto or thereby. According to another embodiment of the invention, a scan driver  210  that is connected to the scan lines and an emission driver that is connected to the emission control lines may be provided as separate components. 
     The scan driver  210  may be built in the display panel DP. That is, the scan driver  210  may be formed in the display panel DP through a thin film process that forms pixels PX 11  to PXnm of the display panel DP. 
     The data driver  220  receives the data control signal DCS and the image data RGB from the controller  100 . The data driver  220  converts the image data RGB to data signals DS and outputs the data signals DS to a plurality of data lines DL 1  to DLm described below. The data signals DS may be analog voltages corresponding to grayscale values of the image data RGB. 
     The display device DD further includes a voltage generator to generate voltages that are required for the operation of the display device DD. In the illustrated embodiment, the voltage generator may generate a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage Vint. 
     The display panel DP may include components that substantially generate the image IM. As an example, the display panel DP may be an organic light emitting display panel. The display panel DP includes the scan lines, the data lines DL 1  to DLm, and the pixels PX 11  to PXnm. The scan lines extend in a first direction DR 1  and are spaced apart from each other in a second direction DR 2 . The data lines DL 1  to DLm extend in the second direction DR 2  and are spaced apart from each other in the first direction DR 1 . As an example, the scan lines include the initialization scan lines GIL 1  to GILn, the compensation scan lines GWL 1  to GWLn, the write scan lines GDL 1  to GDLn, and the black scan lines GBL 1  to GBLn. 
     Each of the pixels PX 11  to PXnm is connected to a corresponding data line and a corresponding scan line. For example, a first pixel PX 11  among the pixels PX 11  to PXnm is connected to a first data line DL 1 , a first initialization scan line GILL a first compensation scan line GWL 1 , a first write scan line GDL 1 , and a first black scan line GBL 1 . A last pixel PXnm among the pixels PX 11  to PXnm is connected an m-th data line DLm, an n-th initialization scan line GILn, an n-th compensation scan line GWLn, an n-th write scan line GDLn, and an n-th black scan line GBLn. That is, according to an example, each of the pixels PX 11  to PXnm may be connected to four types of scan lines. However, the type of scan lines connected to each of the pixels PX 11  to PXnm should not be limited thereby or thereto. That is, two or three types of scan lines may be connected to each of the pixels PX 11  to PXnm. 
     The first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage Vint may be supplied to the display panel DP. Each of the pixels PX 11  to PXnm may receive the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage Vint. 
     Each of the pixels PX 11  to PXnm includes a light emitting element and a pixel circuit unit that controls an emission of the light emitting element. As an example, the light emitting element may be an organic light emitting diode. 
     Referring to  FIG.  4   , the display panel DP includes a display area DA through which the image IM is displayed and a non-display area NDA adjacent to the display area DA. The display area DA is an area through which the image IM is displayed, and the non-display area NDA is a bezel area through which the image IM is not displayed.  FIG.  4    shows a structure in which the non-display area NDA is disposed to surround the display area DA, however, the embodiments should not be limited thereto or thereby. The non-display area NDA may be adjacent to at least one side of the display area DA. 
     The image IM may be displayed through the display area DA. The image IM may include a first image IM 1  and a second image IM 2 . The first image IM 1  may be an image that is displayed at a fixed position for a predetermined time or longer in a specific gray level. The first image IM 1  may be a still image, and the second image may be a video or a still image. For example, the first image IM 1  may include a broadcaster logo, subtitles, date, time, and the like. The first image IM 1  may include a title of a program. Hereinafter, for the convenience of explanation, all various images that are displayed at a fixed position for a predetermined time or longer in a specific gray level will be referred to as the first image IM 1 . The second image IM 2  may be an image that is displayed through the other area of the display area DA except an area through which the first image IM 1  is displayed. 
     The organic light emitting diode includes a plurality of electrodes and a light emitting layer disposed between the electrodes and including an organic material. When an area of the display area DA through which the first image IM 1  is displayed is referred to as a first area, pixels in the first area may be burnt out due to the first image IM 1  being displayed through the same pixels for a long time. Accordingly, when an image different from the first image IM 1  is displayed through the first area after the first image IM 1  is displayed through the first area, the first image IM 1  may remain in the first area, which is not intended, and this persistent first image IM 1  phenomena is called “image sticking.” The controller  100  may periodically perform an image shift operation to compensate for the image sticking. 
       FIG.  5    is a block diagram of an embodiment of the controller  100  of  FIG.  2   , and  FIG.  6    is a block diagram of an embodiment of the shift determiner  120  of  FIG.  5   .  FIG.  7 A  is an illustrative waveform diagram showing a relation between a vertical synchronization signal and a shift start signal as input and output signals of the signal generator of  FIG.  6   , and  FIG.  7 B  is an illustrative waveform diagram showing an activation time point of the shift start signal and a shift control signal as input and output signals of the signal generator of  FIG.  6   . 
     Referring to  FIGS.  3  and  5   , the controller  100  may include a first circuit in the form of an image processor  110  and a second circuit in the form of a shift determiner  120 . The image processor  110  may receive the input image signal I_DAT from the host processor  10  of  FIG.  1   . For example, referring to  FIG.  3   , the input image signal I_DAT may include the frame data FD 1  to FD 6  received in each of the frames FP 1  to FP 6 . Each of the frames FP 1  to FP 6  may include a corresponding active period among the active periods AP 1  to AP 6  and a corresponding variable blank period among the variable blank periods BP 1  to BP 6 . 
     The image processor  110  may convert the input image signal I_DAT to the image data RGB and may provide the image data RGB to the panel driver  200  of  FIG.  1   . As an example, the image processor  110  may perform the image shift operation in response to the shift start signal S_STV. The image processor  110  may shift the frame data FD 1  to FD 6  during several frames from the time point at which the shift start signal S_STV is activated and may output the shifted frame data as the image data RGB. The image processor  110  may shift a position of the frame data FD 1  to FD 6  in the first and second directions DR 1  and DR 2  of the display panel DP (refer to  FIG.  2   ) or in a third direction different from the first and second directions DR 1  and DR 2  by at least one pixel during several frames. 
     The shift determiner  120  may count the duration of the variable blank period BP 1  to BP 6  in each frame FP 1  to FP 6  and may determine the activation time point of the shift start signal S_STV. That is, the shift start signal S_STV may be activated in association with the duration of the variable blank periods BP 1  to BP 6 . The shift determiner  120  may receive the data enable signal DE and the vertical synchronization signal Vsync to generate the shift start signal S_STV. 
     Referring to  FIGS.  6 ,  7 A, and  7 B , the shift determiner  120  may include a counter  121 , a calculator  122 , an adder  123 , a comparator  124 , and a signal generator  125 . 
     The counter  121  may count the variable blank periods BP 1  to BP 6  (refer to  FIG.  3   ) based on a reference clock R_clk and may output a first count value CNT 1 . The counter  121  may receive the reference clock R_clk and the data enable signal DE to count the variable blank periods BP 1  to BP 6 . The counter  121  may count the number of occurrences of the reference clock R_clk during a time period from a start time point of the non-active period BP 1  of the data enable signal DE of the first frame FP 1 , e.g., a current frame, to a start time point of the active period AP 2  of the data enable signal DE of the second frame FP 2 , e.g., a next frame. 
     The first count value CNT 1  output from the counter  121  may be provided to the calculator  122 . The calculator  122  may add the first count value CNT 1  and a pre-stored second count value CNT 2  of the active period and may calculate a count value CNT 3  in every frame. Since the active periods AP 1  to AP 7  of the frames have substantially constant duration, the second count value CNT 2  may have a fixed value. The shift determiner  120  may further include a first memory  126  in which the second count value CNT 2  is stored. However, the embodiments should not be limited thereto or thereby. That is, the first memory  126  may be provided as a separate component outside of the shift determiner  120 . 
     The adder  123  may receive the count value CNT 3  from the calculator  122 . The adder  123  may add the count value CNT 3  and a previous cumulative value P_CNT and may output a cumulative value F_CNT. The shift determiner  120  may further include a second memory  127  in which the cumulative value P_CNT is stored. The adder  123  may read out a cumulative value, i.e., the previous cumulative value P_CNT, up to a previous frame, e.g. the first frame FP 1 , from the second memory  127  and may add the count value CNT 3  and the previous cumulative value P_CNT to calculate the cumulative value F_CNT of the present frame, e.g., the second frame FP 2 . 
     The second memory  127  may receive the cumulative value F_CNT of the current frame FP 2 , which is output from the adder  123 , and may update the previous cumulative value P_CNT to the cumulative value F_CNT.  FIG.  6    shows a structure in which the second memory  127  is disposed in the shift determiner  120 , however, the embodiments should not be limited thereto or thereby. That is, the second memory  127  may be provided as a separate component outside the shift determiner  120 . 
     The comparator  124  may compare the cumulative value F_CNT with a predetermined reference value R_CNT and may output the shift control signal S_CS according to the compared result. Specifically, when the cumulative value F_CNT is smaller than the reference value R_CNT, the comparator  124  may deactivate the shift control signal S_CS, and when the cumulative value F_CNT is equal to or greater than the reference value R_CNT, the comparator  124  may activate the shift control signal S_CS. For example, as shown in  FIG.  7 B , the shift control signal S_CS may be activated at a time point t 1  at which the reference value R_CNT and the cumulative value F_CNT become the same. 
     The signal generator  125  may receive the vertical synchronization signal Vsync and may receive the shift control signal S_CS from the comparator  124 . The signal generator  125  may generate the shift start signal S_STV based on the vertical synchronization signal Vsync in response to the shift control signal S_CS. The vertical synchronization signal Vsync may be generated in each frame according to the frame rate. Referring to  FIG.  7 B , the shift start signal S_STV may be generated in synchronization with the vertical synchronization signal Vsync during an active period S_AP of the shift control signal S_CS. The activated shift control signal S_CS may be deactivated in synchronization with a falling time point of the vertical synchronization signal Vsync. That is, the shift start signal S_STV may be activated in a period in which both the vertical synchronization signal Vsync and the shift control signal S_CS are activated and may be deactivated in a period in which at least one of the vertical synchronization signal Vsync and the shift control signal S_CS are deactivated. 
     The shift determiner  120  may control the activation time point of the shift start signal S_STV in association with the variable blank periods BP 1  to BP 6 . Accordingly, the number of the active periods of the vertical synchronization signal Vsync included in each one of the periods of the shift start signal S_STV may be variable. For example, referring to  FIG.  7 A , the number of the active periods of the vertical synchronization signal Vsync included in an i-th period T 1  of the shift start signal S_STV may be “n”, and the number of the active periods of the vertical synchronization signal Vsync included in a j-th period T 2  of the shift start signal S_STV may be “k”. In this case, “n” and “k” may have an integer number equal to or greater than 1, and “n” and “k” may have different values from each other. The signal generator  125  may apply the shift start signal S_STV to the image processor  110 , and the image processor  110  may start the image shift operation in response to the shift start signal S_STV. As an example, the active period of the shift start signal S_STV may be maintained during predetermined several frames in one period. In this case, the image processor  110  may not perform the image shift operation during the non-active period of the shift start signal S_STV and may perform the image shift operation during the active period of the shift start signal S_STV. 
       FIG.  8    is a block diagram of an embodiment of the image processor  110  of FIG.  5 , and  FIGS.  9 A and  9 B  are views of embodiments of shift directions of an image according to the principles of the invention.  FIG.  10    is a view of an embodiment showing a pixel shift according to a shift direction of the image by the image processor of  FIG.  5   . 
     In the embodiment of  FIG.  8   , the image processor  110  includes a shift processor  111  and a data compensator  112 . 
     The shift processor  111  performs the image shift operation on the input image signal I_DAT in response to the shift start signal S_STV. The shift processor  111  determines the pixel shift amount based on shift setting information and generates initial shift data I_RGB obtained by shifting the input image signal I_DAT according to the pixel shift amount and a shift direction. 
     The data compensator  112  compensates for the initial shift data I_RGB to generate final shift data F_RGB and outputs the final shift data F_RGB as the image data RGB (refer to  FIG.  5   ). As an example, the data compensator  112  includes an area setter  112   a , a compensator  112   b , and a synthesizer  112   c.    
     The area setter  112   a  may set a compensation area and a non-compensation area according to the pixel shift amount and the shift direction. As an example, the compensation area may include a first compensation area and a second compensation area. Among the initial shift data I_RGB, a first shift data I_RGB 1  corresponding to the non-compensation area may be directly provided to the synthesizer  112   c  without passing through the compensator  112   b.    
     A second shift data I_RGB 2  corresponding to the compensation area may be provided to the compensator  112   b . The compensator  112   b  may compensate for the second shift data I_RGB 2  and may generate compensation data C_RGB. As an example, the second shift data I_RGB 2  may include first sub-shift data I_RGB 21  corresponding to the first compensation area and second sub-shift data I_RGB 22  corresponding to the second compensation area. The first sub-shift data I_RGB 21  may be provided to a first sub-compensator  112   b _ 1 , and the second sub-shift data I_RGB 22  may be provided to a second sub-compensator  112   b _ 2 . The first sub-compensator  112   b _ 1  may scale-up the first sub-shift data I_RGB 21  to generate first compensation data C_RGB 1 , and the second sub-compensator  112   b _ 2  may scale-down the second sub-shift data I_RGB 22  to generate second compensation data C_RGB 2 . 
     The synthesizer  112   c  may receive the first shift data I_RGB 1  from the area setter  112   a  and may receive the first and second compensation data C_RGB 1  and C_RGB 2  from the first and second sub-compensators  112   b _ 1  and  112   b _ 2 . The synthesizer  112   c  may synthesize the first shift data I_RGB 1  and the first and second compensation data C_RGB 1  and C_RGB 2  to generate the final shift data F_RGB. In the period where the image shift operation is performed, the final shift data F_RGB may be provided to the data driver  220  as the image data RGB. 
     Referring to  FIGS.  9 A and  9 B , the image shift may be set in various ways. As shown in  FIG.  9 A , the image shift may be set to sequentially move to first to ninth positions P 1  to P 9  in a spiral type pattern from an original position P 0  at which an original image corresponding to the input image signal I_DAT is displayed. The shift amount from each of the first to ninth positions P 1  to P 9  to the original position P 0  may be defined as the pixel shift amount. The pixel shift amount may vary in the unit of at least one frame. The pixel shift amount may include at least one of a horizontal shift component and a vertical shift component. In a case where the original image is shifted from the original position P 0  to the first position P 1 , the pixel shift amount may include only the horizontal shift component, and in a case where the original image is shifted from the original position P 0  to a second position P 2 , the pixel shift amount may include the horizontal shift component and the vertical shift component. In this case, the horizontal shift component indicates the shift amount of the original image that moves in first direction DR 1 , and the vertical shift component indicates the shift amount of the original image that moves in the second direction DR 2 . 
     As shown in  FIG.  9 B , the image shift may be set to move one of first to sixth positions P 1  to P 6  in a  FIG.  8    type pattern from the original position P 0  at which the original image corresponding to the input image signal I_DAT is displayed. 
     For example, referring to  FIGS.  8 ,  9 B, and  10   , after a first image shift operation is performed, an original image O_IM corresponding to the input image signal I_DAT may be shifted from an original position P 0  to a first position P 1 . A first shift image S_IM 1  corresponding to first shift data may be shifted to the third direction DR 3  with respect to the original image O_IM. When the first image shift operation is performed, the pixel shift amount may include a first horizontal shift component Sh 1  and a first vertical shift component Sv 1 . 
     In the first shift image S_IM 1 , an area (hereinafter, referred to as a “first area A 1 ”) that does not overlap the original image O_IM is a portion in which an actual image may not be displayed. In the original image O_IM, an area (hereinafter, referred to as a “second area A 2 ”) that does not overlap the first shift image S_IM 1  is a portion in which there is no data to be displayed. Accordingly, the compensation operation, e.g., the scale-up or the scale-down, is performed based on data corresponding to overlap areas. Thus, data corresponding to the first area A 1  are removed from the initial shift data I_RGB, data corresponding to the second area A 2  are generated, and as a result, the final shift data F_RGB are completed. 
     After a second image shift operation is performed, the original image O_IM corresponding to the input image signal I_DAT may be shifted from the original position P 0  to the second position P 2 . A second shift image S_IM 2  corresponding to second shift data may be shifted to the first direction DR 1  with respect to the original image O_IM. When the second image shift operation is performed, the pixel shift amount may include a second horizontal shift component Sh 2 . In the second shift image S_IM 2 , an area (hereinafter, referred to as a “third area A 3 ”) that does not overlap the original image O_IM is a portion in which an actual image may not be displayed. In the original image O_IM, an area (hereinafter, referred to as a “fourth area A 4 ”) that does not overlap the second shift image S_IM 2  is a portion in which there is no data to be displayed. Accordingly, the compensation operation, e.g., the scale-up or the scale-down, is performed based on data corresponding to overlap areas. Thus, data corresponding to the third area A 3  are removed from the initial shift data I_RGB, data corresponding to the fourth area A 4  are generated, and as a result, the final shift data F_RGB are completed. 
     After a third image shift operation is performed, the original image O_IM corresponding to the input image signal I_DAT may be shifted to the third position P 3  from the original position P 0 . A third shift image S_IM 3  corresponding to third shift data may be shifted to a fourth direction DR 4  with respect to the original image O_IM. When the third image shift operation is performed, the pixel shift amount may include a third horizontal shift component Sh 3  and a second vertical shift component Sv 2 . In the third shift image S_IM 3 , an area (hereinafter, referred to as a “fifth area A 5 ”) that does not overlap the original image O_IM is a portion in which an actual image may not be displayed. In the original image an area (hereinafter, referred to as a “sixth area A 6 ”) that does not overlap the third shift image S_IM 3  is a portion in which there is no data to be displayed. Accordingly, the compensation operation, e.g., the scale-up or the scale-down, is performed based on data corresponding to overlap areas. Thus, data corresponding to the fifth area A 5  are removed from the initial shift data I_RGB, data corresponding to the sixth area A 6  are generated, and as a result, the final shift data F_RGB are completed. 
     The image shift operation performed using the image processor  110  (refer to  FIG.  8   ) may be performed in various ways in addition to the embodiments shown in  FIGS.  9 A and  9 B . 
       FIG.  11    is an illustrative waveform diagram showing a refresh operation of the display device operated in an ultra-low frequency mode.  FIG.  12    is a block diagram of another embodiment of the shift determiner of  FIG.  5   .  FIG.  13    is an illustrative waveform diagram showing an activation time point of a shift start signal and a pre-shift control signal as output and input signals of the signal generator of  FIG.  12   . In  FIGS.  12  and  13   , the same reference numerals denote the same elements used in  FIGS.  6  and  7 B , and thus, detailed descriptions of the same elements will be omitted to avoid redundancy. 
     The display device DD (refer to  FIG.  1   ) operated in the ultra-low frequency mode may display a still image IM_A at a predetermined period T_R. For example, the display device DD may be operated at a frequency lower than about 1 Hz in the ultra-low frequency mode. In the ultra-low frequency mode, the period T_R at which the still image IM_A is refreshed to another image IM_B may be greater than a predetermined shift period. 
     Hereinafter, a method of performing the image shift operation at the predetermined period in the ultra-low frequency mode will be described. 
     In the embodiment of  FIGS.  12  and  13   , the shift determiner  120  further includes a preliminary comparator  128 . The preliminary comparator  128  receives a count value CNT 3  from a calculator  122  and compares the received count value CNT 3  with a predetermined reference value R_CNT. 
     When the count value CNT 3  is smaller than the reference value R_CNT, the preliminary comparator  128  provides the count value CNT 3  to an adder  123 . When the count value CNT 3  is provided to the adder  123 , the adder  123  and a comparator  124  may be operated similar to the adder  123  and the comparator  124  shown in  FIGS.  6  and  7 B . When the count value CNT 3  is equal to or greater than the reference value R_CNT, the preliminary comparator  128  may activate a pre-shift control signal PS_CS. For example, as shown in  FIG.  13   , after a time point t 2  at which the reference value R_CNT becomes the same as the count value CNT 3 , the pre-shift control signal PS_CS may be activated. 
     A signal generator  125  receives a vertical synchronization signal Vsync and receives the pre-shift control signal PS_CS from the preliminary comparator  128 . The signal generator  125  generates a shift start signal S_STV based on the vertical synchronization signal Vsync in response to the pre-shift control signal PS_CS. The shift start signal S_STV may be generated in synchronization with the vertical synchronization signal Vsync in an active period PS_AP of the pre-shift control signal PS_CS. The activated pre-shift control signal PS_CS may be deactivated in synchronization with a falling time point of the vertical synchronization signal Vsync. That is, the shift start signal S_STV is activated in a period in which both the vertical synchronization signal Vsync and the pre-shift control signal PS_CS are activated. According to  FIG.  13   , the number of the active periods of the vertical synchronization signal Vsync included in one period of the shift start signal S_STV may be one. As an example, the active period of the shift start signal S_STV may be maintained in predetermined several frames. 
     The signal generator  125  may provide the shift start signal S_STV to the image processor  110  (refer to  FIG.  5   ), and the image processor  110  may normally perform the image shift operation at a predetermined period in response to the shift start signal S_STV in the ultra-low frequency mode. 
     Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art.