Patent Publication Number: US-6034730-A

Title: Module switching type picture compressing and reproducing apparatus

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a picture processing apparatus, in particular, to an apparatus for compressing and encoding picture data with a CPU (Central Processing Unit) or a DSP (Digital Signal Processor) and an apparatus for reproducing picture data from compressed picture code with a CPU or a DSP. 
     2. Description of the Related Art 
     If digitized picture data are directly recorded in a record medium such as a CD-ROM and a hard disk, required capacity of record media becomes huge. Thus, the digitized picture data are normally compressed before recorded. DCT (Discrete Cosine Transform) coding has been more widely used in compression systems than other method such as DPCM and other orthogonal transform codings. For example, DCT coding is used in international encoding standards such as JPEG (Joint Photographic coding Experts Group) and MPEG (Moving Picture coding Experts Group). DCT coding utilizes its characteristics that power spectrum concentrates in lower frequency components of DCT coefficients. 
     FIG. 24 is a schematic diagram showing hierarchical levels of a coding format corresponding to MPEG. Referring to FIG. 24, MPEG codes are hierarchically structured. The top hierarchical level is a video sequence. The video sequence is composed of a plurality of GOPs (Group Of Pictures). Each GOP is composed of a plurality of pictures. One picture represents one frame. Pictures can be categorized into I pictures, P pictures, and B pictures. I pictures are intra-frame encoded. P pictures are forward inter-frame encoded. B pictures are forward/backward inter-frame encoded. Each picture is composed of a plurality of slices. Each slice is composed of a plurality of macro blocks that are arranged from left to right and from top to bottom. Each macro block is composed of a total of six blocks. Four blocks of them are luminance components (Y1, Y2, Y3, and Y4) and two blocks of them are color difference components (Cb and Cr). Each of blocks is composed of 8×8 pixels. Each block is the minimum coding unit. 
     Next, with reference to the accompanying drawings, a picture compressing system corresponding to a conventional DCT system such as MPEG will be described. 
     FIG. 25 is a block diagram showing a structure of a picture compressing apparatus that compresses picture data corresponding to MPEG. Referring to FIG. 25, the picture compressing apparatus reads RGB pixel data of the picture. YUV converting means 205 converts the RGB pixel data into YUV pixel data. Motion estimating means 206 searches the motion of macro blocks of the present frame relative to preceding/following frames. As mentioned above, pictures are categorized into three types of pictures: I pictures which are intra-frame encoded, P pictures which are interframe encoded, and pictures which are forward/backward inter-frame encoded. Thus, three types of compressing processes are performed. 
     In the case of I pictures, DCT means 208 transforms block data in the present frame to DCT coefficients. A quantizing means 209 quantizes the DCT coefficients. A variable length encoding means 210 compresses with high-efficiency the quantized DCT coefficients to Huffman codes. 
     Reproduced picture data used as reference in encoding P pictures and B pictures are obtained from quantized DCT coefficients as follows. Dequantizing means 214 dequantizes the quantized DCT coefficients. IDCT (Inverse Discrete Cosine Transform) means 213 performs the inverse discrete cosine transform for the dequantized DCT coefficients. The obtained picture data are stored in reference frame portion 211. 
     In the case of P pictures, motion-compensated predicting means 207 calculates the differences between the level of the pixels of each blocks in the present frame and the level of the pixels in the preceding frame read out from the reference frame portion 211 with the displacement pointed out by a motion vector searched by the motion estimating means 206. The DCT means 208 performs the discrete cosine transform for the differential data to produce DCT coefficients. The quantizing means 209 quantizes the DCT coefficients. The variable length encoding means 210 compresses with high-efficiency the quantized DCT coefficients to Huffman codes. 
     Reproduced picture data used as reference in encoding other P pictures and B pictures are obtained from quantized DCT coefficients as follows. Dequantizing means 214 dequantizes the quantized DCT coefficients. IDCT (Inverse Discrete Cosine Transform) means 213 performs the inverse discrete cosine transform for the dequantized DCT coefficients to generate differential data. The picture data in reference frame portion 211 are read out with the displacement pointed out by motion vector and added to the differential data. The sums are stored in reference frame portion 211. 
     In the case of B pictures, the motion-compensated predicting means 207 calculates the differential data between the level of the pixels of the block in the present frame and the level of the pixels in the preceding or following frame read out from the reference frame portion 211 with the displacement pointed out by a motion vector searched by the motion estimating means 206. The DCT means 208 performs the discrete cosine transform for the differential data to generate DCT coefficients. The quantizing means 209 quantizes the DCT coefficients. The variable length encoding means 210 compresses with high-efficiency the quantized DCT coefficients to Huffman codes. Since B pictures are not used as a reference frame, reproduced picture data are not regenerated from the quantized DCT coefficients in B pictures. 
     Next, with the reference to the accompanying drawings, a picture data reproducing system will be described. FIG. 26 is a block diagram showing the structure of a picture reproducing apparatus that reproduces picture data from the codes which are generated by picture compressing system or conform to MPEG syntax. 
     The picture data reproducing apparatus shown in FIG. 26 decodes I pictures that have been intra-frame encoded, P pictures that have been forward inter-frame encoded, and B pictures that have been forward or backward inter-frame encoded. 
     In the case of I pictures, picture data are reproduced as follows. The variable length decoding means 225 decodes variable length codes to regenerate quantized DCT coefficients. The dequantizing means 226 dequantizes the quantized DCT coefficients to regenerate dequantized DCT coefficients. The IDCT means 227 performs the inverse discrete cosine transform for the dequantized DCT coefficients to regenerate the YUV pixel data. RGB converting means 228 converts YUV pixel data into RGB pixel data and outputs the RGB pixel data. 
     In the case of P pictures, picture data are reproduced as follows. The variable length decoding means 225 decodes variable length codes to regenerate quantized DCT coefficients. The dequantizing means 226 dequantizes the quantized DCT coefficients. The IDCT means 227 performs the inverse discrete cosine transform to regenerate the differential data. The data of preceding frame read out from the reference frame portion 229 are compensated in motion by the motion compensating means 230 and added to the differential data to regenerate data in the present frame. The RGB converting means 228 converts the resultant data into RGB pixel data and outputs the RGB pixel data. 
     In the case of B pictures, picture data are reproduced as follows. The variable length decoding means 225 decodes variable length codes to regenerate quantized DCT coefficients. The dequantizing means 226 dequantizes the quantized DCT coefficients. The IDCT means 227 performs the inverse discrete cosine transform to regenerate the differential data. The data of preceding frame or following frame read out from the reference frame portion 229 are compensated in motion by the motion compensating means 230 and added to the differential data to regenerate data in the present frame. The RGB converting means 228 converts the resultant data into RGB pixel data and outputs the RGB pixel data. 
     Thus, corresponding to the international standard MPEG system, a picture data can be compressed with high-efficiency and reproduced. However, since the motion estimating, motion-compensated predicting process and the DCT/IDCT process require a large number of calculations, when a picture data are compressed and reproduced by software on CPU or DSP, it should be processed with an optimum program corresponding to the characteristic of each of CPUs, DSPs. 
     Thus, a variety of programs corresponding to a variety of CPUs, DSPs should be provided and they should be switched to cope with each of CPUs and DSPs. 
     As a related art reference for switching a plurality of programs, a system which switches a plurality of encoding/decoding processes on a time sharing basis with a priority has been proposed in Japanese Patent Laid-Open Publication 63-234,461. In addition, for example, in Japanese Patent Laid-Open Publication No. 2-108119, a structure of which a plurality of data compressing means are provided and data are compressed by the optimum means with the most compression efficiency is disclosed. In Japanese Patent Laid-Open Publication No. 5-233267, a structure of a program ROM built-in apparatus of which both a compressed program stored in a ROM and a differential program stored in a backup RAM are both developed in a RAM to compose a executable program has been proposed. 
     However, in the conventional picture compressing and reproducing apparatuses, a large number of programs corresponding to a large number of CPUs, DSPs, and so forth are required. Thus, the storage capacity of programs becomes large. 
     In addition, whenever apparatuses are switched, programs must also be switched. Thus, the process becomes complicated. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a picture compressing apparatus and reproducing apparatus which execute an optimum program for the CPU or DSP in use among a large number of types of CPUs and DSPs and are provided with a small program capacity. 
     A first aspect of the present invention is to provide a picture compressing apparatus which compresses picture data by causing a facultative CPU (Central Processing Unit) or a facultative DSP (Digital Signal Processor) to execute a program for performing an intra-frame encoding process, a forward inter-frame encoding process and a bidirectional inter-frame encoding process, wherein said intra-frame encoding process comprises dividing the present frame into small blocks, performing DCT (Discrete Cosine Transform) process for each of the small blocks, quantizing the transformed result, and encoding with high-efficiency the quantized result, said forward inter-frame encoding process comprises dividing the present frame into small blocks, searching through the preceding frame for a small block which minimizes the difference between each of the small blocks in the present frame and the searched small block, obtaining the differential data between each of the small blocks in the present frame and the relevant searched small block, performing the DCT process for the differential data, quantizing the transformed result, and encoding with high-efficiency the quantized result, said bidirectional inter-frame encoding process comprises dividing the present frame into small blocks, searching through the preceding frame and the following frame for a small block which minimizes the difference between each of the small blocks in the present frame and the searched small block, obtaining the differential data between each of the small blocks in the present frame and the relevant searched small block, performing the DCT process for the differential data, quantizing the transformed result, and encoding with high-efficiency the quantized result, said program is composed of a basic module and differential modules of which each corresponds to each CPU and each DSP, the apparatus comprises a means for storing the modules, a means for detecting the CPU or DSP which is being currently used, and a means for creating the program for the detected CPU or DSP with the basic module and the differential module corresponding to the CPU or DSP. 
     A second aspect of the present invention is to provide a picture reproducing apparatus which reproduces picture data by causing a facultative CPU (Central Processing Unit) or a facultative DSP (Digital Signal Processor) to execute a program for performing a reproducing process, wherein said reproducing process comprises decoding picture codes to regenerate quantized DCT coefficients, dequantizing the quantized DCT coefficients to regenerate dequantized DCT coefficients, performing IDCT (Inverse Discrete Cosine Transform) for the dequantized DCT coefficients to regenerate pixel data or differential data, storing the regenerated pixel data in a reference frame portion, reading out pixel data from the reference frame portion, compensating the motion of the read pixel data, adding the differential data to the motion compensated pixel data, said program is composed of a basic module and differential modules of which each corresponds to each CPU and each DSP, the apparatus comprises a means for storing the modules, a means for detecting the CPU or DSP which is being currently used, and a means for creating the program for the detected CPU or DSP with the basic module and the differential module corresponding to the CPU or DSP. 
     These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of the best mode embodiment thereof, as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram showing an example of the structure of a picture compressing apparatus according to an embodiment of the present invention; 
     FIG. 2 is a block diagram showing an example of the structure of a picture reproducing apparatus according to an embodiment of the present invention; 
     FIG. 3 is a schematic diagram for explaining a creating process of an optimum program according to an embodiment of the present invention; 
     FIG. 4 is a flow chart for explaining a process of an apparatus controlling means of a picture compressing apparatus according to an embodiment of the present invention; 
     FIG. 5 is a first part of a flow chart for explaining a picture compressing process according to an embodiment of the present invention; 
     FIG. 6 is a second part of a flow chart for explaining a picture compressing process according to an embodiment of the present invention; 
     FIG. 7 is a flow chart for explaining a compression program creating process according to an embodiment of the present invention; 
     FIG. 8 is a flow chart for explaining an apparatus controlling means of a picture reproducing apparatus according to an embodiment of the present invention; 
     FIG. 9 is a flow chart for explaining a picture reproducing process according to an embodiment of the present invention; 
     FIG. 10 is a flow chart for explaining a reproducing program creating process according to an embodiment of the present invention; 
     FIG. 11 is a flow chart for explaining a module creating process according to an embodiment of the present invention; 
     FIG. 12(a) is an example of instruction; 
     FIG. 12(b) is a list showing difference codes according to an embodiment of the present invention; 
     FIG. 13(c) is an example of a string of difference codes; 
     FIG. 14(A) is a list of program codes of a basic quantizing module; 
     FIG. 14(B) is a list of program codes of an optimum quantizing module for CPU B; 
     FIG. 14(c) is a top portion of a list of difference codes of a quantizing differential module for CPU B; 
     FIG. 15 is a list of difference codes of a quantizing differential module for CPU B; 
     FIG. 16(A) is a list of program codes of a basic DCT module; 
     FIG. 16(B) is a list of program codes of an optimum DCT module for CPU B; 
     FIG. 16(c) is a top portion of a list of difference codes of a DCT differential module for CPU B; 
     FIG. 17 is a list of difference codes of a DCT differential module for CPU B; 
     FIG. 18(A) is a list of program codes of a basic motion compensating module; 
     FIG. 18(B) is a list of program codes of an optimum motion compensating module for CPU B; 
     FIG. 18(c) is a top portion of a list of difference codes of a motion compensating differential module for CPU B; 
     FIG. 19 is a list of difference codes of a motion compensating differential module for CPU B; 
     FIG. 20(A) is a list of program codes of a basic YUV converting module; 
     FIG. 20(B) is a list of program codes of an optimum YUV converting module for CPU B; 
     FIG. 20(c) is a top portion of a list of difference codes of a YUV converting differential module for CPU B; 
     FIG. 21 is a list of difference codes of a YUV converting differential module for CPU B; 
     FIG. 22(A) is a list of program codes of a basic variable length encoding module; 
     FIG. 22(B) is a list of program codes of an optimum variable length encoding module for CPU B; 
     FIG. 22(c) is a top portion of a list of difference codes of a variable length encoding differential module for CPU B; 
     FIG. 23 is a list of difference codes of a variable length encoding differential module for CPU B; 
     FIG. 24 is a schematic diagram showing hierarchical levels of a code format conforming to MPEG; 
     FIG. 25 is a block diagram showing the structure of a conventional picture compressing apparatus; and 
     FIG. 26 is a block diagram showing the structure of a conventional picture reproducing apparatus. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram showing the structure of a picture compressing apparatus according to an embodiment of the present invention. With reference to FIG. 1, the picture compressing apparatus comprises apparatus controlling means 1, CPU 2, keyboard 3, picture compressing means 4, program data 15, decoding means 16, and code table 17. The apparatus controlling means 1 controls the entire apparatus. The CPU 2 executes a program which is equivalent to picture compressing means 4. The keyboard 3 allows the user to input data to the apparatus. The picture compressing means 4 compresses a picture. The program data 15 contains the basic modules and plural sets of differential modules. Each of differential modules is generated by taking difference between the basic module and an optimum module for each of CPU. All of the modules are compressed by entropy coding. The decoding means 16 decodes the program data 15 with reference to code table 17 in which entropy codes are stored. 
     The picture compressing means 4 comprises YUV converting means 5, motion estimating means 6, motion-compensated predicting means 7, DCT means 8, quantizing means 9, variable length encoding means 10, dequantizing means 14, IDCT means 13, motion compensating means 12, and reference frame portion 11. 
     The YUV converting means 5 converts RGB pixel data of a picture into YUV pixel data. The motion estimating means 6 searchers the motion of the picture for each of macro blocks. The motion-compensated predicting means 7 calculates the differential data between the existing block and the blocks of the preceding/following frames that have been motion compensated. The DCT means 48 performs the discrete cosine transform process for the absolute data or differential data of the block to generate DCT coefficients. The quantizing means 9 quantizes the DCT coefficients. The variable length encoding means 10 encodes the quantized DCT coefficients to Huffman codes. The dequantizing means 9 dequantizes the quantized DCT coefficients. The IDCT means 13 performs the IDCT process for the dequantized DCT coefficients to generate absolute pixel data or difference pixel data. The motion compensating means 12 adds the differential data to the absolute pixel data of the reference frame that has been motion compensated and write the sum to the reference frame portion 11. The reference frame portion 11 stores the preceding/following reference frames. 
     The picture compressing apparatus shown in FIG. 1 reads RGB pixel data of a picture. The YUV converting means 5 converts the RGB pixel data into YUV pixel data. The motion estimating means 6 searches the motion vector of each of the macro blocks in the present frame. The motion vector is derived so that difference between picture block in the present frame and a picture block in the preceding frame or following frame which is displaced according to the motion vector is minimized. 
     In MPFG, pictures (frames) are categorized into I pictures that are intra-frame encoded, P pictures that are forward inter-frame encoded, and B pictures that are forward/backward or bidirectionally inter-frame encoded. Thus, corresponding to the type of a picture, three types of compression are performed. 
     In the case of I pictures, a DCT means 8 performs the discrete cosine transform process for the data of the block of the existing frame to generate DCT coefficients. A quantizing means 9 quantizes the DCT coefficients. A variable length encoding means 10 compresses with high-efficiency the quantized DCT coefficients to Huffman codes. 
     Reproduced picture data used as reference in encoding P pictures and B pictures are obtained from quantized DCT coefficients as follows. Dequantizing means 14 dequantizes the quantized DCT coefficients. IDCT (Inverse Discrete Cosine Transform) means 13 performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate pixel data. The obtained pixel data are stored in a reference frame portion 11. 
     In the case of P pictures, a motion-compensated predicting means 7 calculates the differential data between the data of the pixels of the block (8×8 pixels) of the existing frame and the data of the pixels of the preceding frame read out from the reference frame portion 11 with the displacement assigned by a motion vector searched by the motion estimating means 8. The DCT means 8 performs the discrete cosine transform process for the differential data to generate DCT coefficients. The quantizing means 9 quantizes the DCT coefficients. The variable length encoding means 10 compresses with high-efficiency the quantized DCT coefficients to Huffman codes. 
     Reproduced picture data used as reference in encoding P pictures and B pictures is obtained from quantized DCT coefficients as follows. The dequantizing means 14 dequantizes the quantized DCT coefficients. The IDCT means 13 performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate differential data. The picture data in reference frame portion 11 are read out with the displacement pointed out by motion vector and added to the differential data. The sums are stored in reference frame portion 11. 
     In the case of B pictures, the motion-compensated predicting means 7 calculates the differential data between the data of the pixels of the block (8×8 pixels) of the existing frame and the data of the pixels of the preceding frame or following frame read out from the reference frame portion 11 with the displacement assigned by the motion vector searched by the motion estimating means 6. The DCT means 8 performs the discrete cosine transform process for the differential data to generate DCT coefficients. The quantizing means 9 quantizes the DCT coefficients. The variable length encoding means 10 compresses with high-efficiency the quantized DCT coefficients to Huffman codes. Since B pictures are not used as a reference frame, pixel data are riot regenerated from the quantized DCT coefficients in B pictures. 
     The apparatus controlling means 1 examines the ID of existing CPU 2 and CPU ID of the program data 15 to determine whether or not the program of the picture compressing means 4 is an optimum program for an existing CPU 2. When the determined result is No, the apparatus controlling means 1 extracts compressed codes of basic modules and differential modules corresponding to the existing CPU from the program data 15, causes the decoding means 16 to decode the compressed codes with reference to code table 17, combines decoded modules for each function to generate optimum modules for the existing CPU 2, and combines and assembles the optimum modules into the optimum program for the existing CPU 2. 
     FIG. 2 is a block diagram showing the structure of a picture reproducing apparatus according to an embodiment of the present invention. 
     With reference to FIG. 2, the picture reproducing apparatus comprises apparatus controlling means 21, CPU 22, keyboard 23, picture reproducing means 24, program data 31, decoding means 32, and code table 33. The apparatus controlling means 21 controls the entire apparatus. The CPU 22 executes the program which is equivalent to the picture reproducing means 24. The keyboard 23 allows the user to input data to the apparatus. The picture reproducing means 24 reproduces pictures. The program data 31 contains the basic modules and plural sets of differential modules. Each of differential modules is generated by taking difference between the basic module and an optimum module for each of CPU. All of the modules are compressed by entropy coding. The decoding means 32 decodes the program data 31. The decoding means 32 decodes the program data 31 with reference to code table 33 in which entropy codes are stored. 
     The picture reproducing means 24 comprises variable length decoding means 25, dequantizing means 26, IDCT means 27, RGB converting means 28, reference frame portion 29, and motion compensating means 30. The variable length decoding means 25 decodes compressed codes to regenerate quantized DCT coefficients. The dequantizing means 26 dequantizes the quantized DCT coefficients that have been decoded to regenerate dequantized DCT coefficients. The IDCT means 27 performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate YUV pixel data or differential data. The RGB converting means 28 converts YUV pixel data into RGB pixel data. The reference frame portion 69 stores the preceding frame and following frame which are used as reference frames. The motion compensating means 30 compensates the motion of the block data that are read out from the reference frame portion 69 corresponding to motion vectors. 
     The picture reproducing apparatus shown in FIG. 2 receives encoded with high-efficiency codes of the picture and reproduces pictures that are consist of I pictures that have been intra-frame encoded, P pictures that have been forward inter-frame encoded, and B pictures that have been forward or backward inter-frame encoded. 
     In the case of I pictures, picture data are reproduced as follows. The variable length decoding means 25 decodes the received codes to regenerate quantized DCT coefficients. The dequantizing means 26 dequantizes the quantized DCT coefficients to regenerate dequantized DCT coefficients. The IDCT means 27 performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate the YUV pixel data of the block. The RGB converting means 28 converts YUV pixel data into RGB pixel data. 
     In the case of P pictures, picture data are reproduced as follows. The variable length decoding means 25 decodes the received codes to regenerate quantized DCT coefficients. The dequantizing means 26 dequantizes the quantized DCT coefficients. The IDCT means 27 performs the inverse discrete cosine transform process for the dequantized DCT coefficients to generate the differential data of the pixels of the block. The data of preceding frame read out from the reference frame portion 29 are compensated in motion by the motion compensating means 30 and added to the differential data to regenerate YUV pixel data in the present frame. The RGB converting means 28 converts the resultant data into RGB pixel data and outputs the RGB pixel data. 
     In the case of B pictures, the variable length decoding means 25 decodes the received codes to regenerate quantized DCT coefficients. The dequantizing means 26 dequantizes the quantized DCT coefficients. The IDCT means 27 performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate the differential data of the block. The data of preceding or following frame read out from the reference frame portion 29 is motion compensated by the motion compensating means 30 and added to the differential data to regenerate YUV pixel data in the present frame. The RGB converting means 28 converts the resultant data into RGB pixel data and outputs the RGB pixel data. 
     In addition, the apparatus controlling means 21 examines the ID of existing CPU 22 and the CPU ID of the program data 31 to determines whether or not the program of the picture reproducing means 24 is an optimum program for the existing CPU 22. When the determined result is No, the apparatus controlling means 21 extracts compressed codes of basic modules and differential modules corresponding to the existing CPU from the program data 31, causes the decoding means 32 to decode the compressed codes with reference to code table 33, combines decoded modules for each function to generate optimum modules for the existing CPU 22, and combines and assembles the optimum modules into the optimum program for the existing CPU 22. 
     Next, the method of creating an optimum program for a particular CPU according to an embodiment of the present invention will be described. 
     FIG. 3 is a schematic diagram showing a data flow of an optimum program creating process according to an embodiment of the present invention. FIG. 3 shows how the dequantizing optimum module for CPU B 82 is generated from a compressed basic and differential module in program data 31 in the case that a CPU A (CPU ID=A) is switched to a CPU B (CPU ID=B). 
     At first, compressed codes of basic module of dequantizing and compressed codes of differential data of dequantizing corresponding to CPU B are extracted from the program data 31. 
     Next the decoding means 32 decodes the compressed codes of basic module to generate basic module of dequantizing 83 with reference to the code table 33, decodes the compressed codes of differential data to generate (differential module of dequantizing corresponding to CPU B 85 with reference to the code table 33, and creates dequantizing module 82 optimum for CPU B from the basic module 83 and the differential data 85. 
     Next, the dequantizing optimum module for the CPU A in the picture reproducing program 81 is substituted with the dequantizing module 82 optimum for the CPU B. 
     Next, likewise, the variable length decoding optimum module for CPU A, the IDCT optimum module for CPU A, the motion compensating optimum module for CPU A, and the RGB converting optimum module for CPU A are substituted with those optimum for CPU B. Thus, a picture reproducing program 81 optimum for CPU B is created. 
     The program data 31 is composed of modules that specially causes the CPU to be highly loaded. That is, on the picture reproducing side, the program data 31 is composed of a variable length decoding module, an dequantizing module, an IDCT module, a motion compensating module, and an RGB converting module. In addition, since the modules have many repetitive instructions, similar instructions are contained and arranged in modules. Thus, the difference between optimum modules for different CPUs is small and the amount of differential data is small. 
     According to an embodiment of the present invention, program data is so structured that the aforementioned feature of differential data is utilized. By making the program data 31 consist of the basic modules and the differential modules that are created by taking difference between each basic module and plurality of the optimum module for each CPU, the entire size of the program data 31 can be reduced. 
     On the picture compressing side, likewise, the program data 15 consist of basic modules and differential modules for each function such as YUV converting, motion estimating, motion-compensated predicting, DCT, quantization, variable length encoding, dequantization, IDCT, and motion compensation. 
     Next, the operation according to an embodiment of the present invention will be described. 
     FIG. 4 is a flow chart showing a process of the apparatus controlling means 1 of the picture compressing apparatus shown in FIG. 1. 
     The system compares the ID of the existing CPU 2 and the CPU ID of the existing program data 15 (at step 41) and determines; whether or not they match (at step 42). Only if the determined result at step 42 is No, the system creates a compression program (at step 43). Next, the system compresses; pictures (at step 44). The system determines whether or not all frames have been compressed (at step 45). When the determined result at step 45 is No, the flow returns to step 44. 
     FIGS. 5 and 6 show a first part and a second part of a flow chart of a picture compressing process, respectively. 
     As seen from FIGS. 1, 5, and 6, in the picture compressing process, the YUV converting means 5 converts RGB pixel data into YUV pixel data (at step 101). The motion estimating means 6 searches for a motion vector of each macro block of the picture (at step 102), determines the type of the picture (at step 103), and performs a predetermined process corresponding to the type of the picture. 
     In the case of I pictures, they are compressed as follows. The DCT means 8 performs the discrete cosine transform process for the YUV pixel data to generate DCT coefficients (at step 104). The quantizing means 9 quantizes the DCT coefficients (at step 105). The variable length encoding means 10 compresses with high-efficiency the quantized DCT coefficients to Huffman codes (at step 106). The dequantizing means 14 dequantizes the quantized DCT coefficients (at step 107). The IDCT means 13 performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate YUV pixel data and they are stored in reference frame portion 11 (at step 108). 
     In the case of P pictures, they are compressed as follows. The motion-compensated predicting means 7 calculates the differential data between the block of the existing block and the block of preceding frame read out from reference frame portion 11 with displacement assigned by motion vector (at step 109). The DCT means 8 performs the discrete cosine transform process for the differential data to generate DCT coefficients (at step 110). The quantizing means 9 quantizes the DCT coefficients (at step 111). The variable length encoding means 10 compresses with high-efficiency the quantized DCT coefficients to Huffman codes (at step 112). The dequantizing means 14 dequantizes the quantized DCT coefficients (at step 113). The IDCT means 13 performs the inverse discrete transform process for the dequantized DCT coefficients to regenerate differential data (at step 114). The motion compensating means 12 displaces the data in preceding frame read out from the reference frame portion 11 in accordance with motion vector and adds the differential data to the displaced data. The sum are stored in reference frame portion 11 (at step 115). 
     In the case of B pictures, they are compressed as follows. The motion-compensated predicting means 7 calculates the differential data between the block of the existing block and the block of preceding or following frame read out from reference frame portion 11 with displacement assigned by motion vector (at step 116). The DCT means 8 performs the discrete cosine transform process for the differential data to generate DCT coefficients (at step 117). The quantizing means 9 quantizes the DCT coefficients (at step 118). The variable length encoding means 10 compresses with high-efficiency the quantized DCT coefficients to Huffman codes (at step 119). The dequantizing means 14 dequantizes the quantized DCT coefficients (at step 120). The IDCT means 13 performs the inverse discrete transform process for the dequantized DCT coefficients to regenerate differential data (at step 121). The motion compensating means 12 displaces the data in preceding or following frame read out from the reference frame portion 11 in accordance with motion vector and adds the differential data to the displaced data. The sum are stored in reference frame portion 11 (at step 122). 
     FIG. 7 is a flow chart for explaining the process of creating compression program according to an embodiment of the present invention. 
     The system creates a YUV converting module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;YUV --  Conversion&#34; (at step 131). Next, the system creates a motion estimating module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Motion --  Estimating&#34; (at step 132). 
     Thereafter, the system creates a motion-compensated predicting module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Motion --  Compensated --  Predicting&#34; (at step 133). The system creates a DCT module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;DCT&#34; (at step 134). 
     The system creates a quantizing module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Quantizing&#34; (at step 135). The system creates a variable length encoding module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Variable --  Length --  Code --  Encoding&#34; (at step 136). The system creates a dequantizing module with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Dequantizing&#34; (at step 137). 
     The system creates an IDCT module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;IDCT&#34; (at step 138). The system creates a motion compensating module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Motion --  Compensating&#34; (at step 139). 
     FIG. 8 is a flow chart for explaining a process of the apparatus controlling means 21 of the picture reproducing apparatus shown in FIG. 2. 
     The system compares the ID of the existing CPU 22 with the CPU ID of the existing program data 31 (at step 141) and determines whether or not they match (at step 142). Only if the determined result is No, the system creates a reproducing program (at step 143). Next, the system reproduces pictures (at step 144) and determines whether or not all frames have been reproduced (at step 145). When the determined result is No, the flow returns to step 144. 
     FIG. 9 is a flow chart for explaining a picture reproducing process according to an embodiment of the present invention. 
     The variable length decoding means 25 (see FIG. 2) decodes compressed codes to regenerate quantized DCT coefficients (at step 161), determines the type of the picture (at step 162), and processes the picture corresponding to the type. 
     In the case of I pictures, picture data are reproduced as follow,. The dequantizing means 26 (see FIG. 2) dequantizes the quantized DCT coefficients (at step 163). The IDCT means 27 (see FIG. 2) performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate YUV pixel data. The YUV pixel data is stored in the reference frame portion 29 (at step 164). The RGB converting means 28 (see FIG. 2) converts the YUV pixel data into RGB pixel data (at step 165). 
     In the case of P pictures, picture data are reproduced as follows. The dequantizing means 28 (see FIG. 2) dequantizes the quantized DCT coefficients (at step 166). The IDCT means 27 (see FIG. 2) performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate differential data (at step 167). The data of preceding frame read out from the reference frame portion 29 (see FIG. 2) is motion compensated by the motion compensating means 30 (see FIG. 2) and added to the differential data to regenerate YUV pixel data in the present frame and the YUV pixel data is stored in the reference frame portion 29 (at step 168). The RGB converting means 28 (see FIG. 2) converts the YUV pixel data into RGB pixel data (at step 169). 
     In the case of B pictures, picture data are reproduced as follows. The dequantizing means 28 (see FIG. 2) dequantizes the quaitized DCT coefficients (at step 170). The IDCT means 27 (see FIG. 2) performs the inverse discrete cosine transform process for the dequantized DCT coefficients to regenerate differential data (at step 171). The data of preceding or following frame read out from the reference frame portion 29 (see FIG. 2) is motion compensated by the motion compensating means 30 (see FIG. 2) and added to the differential data to regenerate YUV pixel data in the present frame and the YUV pixel data is stored in the reference frame portion 29 (at step 172). The RGB converting means 28 (see FIG. 2) converts the YUV pixel data into RGB pixel data (at step 173). 
     FIG. 10 is a flow chart for explaining the process of creating reproduction program according to an embodiment of the present invention. 
     The system creates a variable length decoding module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Variable --  Length --  Code --  Decoding&#34; (at step 151). The system creates a dequantizing module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Dequantizing&#34; (at step 152). The system creates an IDCT module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;IDCT&#34; (at step 153). 
     The system creates an RGB converting module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;RGB --  Converting&#34; (at step 154). The system creates a motion compensating module of the existing CPU with arguments &#34;X&#34; (X is the ID of existing CPU) and &#34;Motion --  Compensating&#34; (at step 155). 
     FIG. 11 is a flow chart showing a process of creating each module shown in FIG. 7 or 10 with arguments of &#34;designated CPU&#34; and &#34;designated function&#34;. 
     The apparatus controlling means 1 (21) extracts the compressed codes of the basic module of designated function and the compressed codes of the differential module corresponding to designated function and designated CPU from the program data 15 (31) (at step 181). 
     Next, with reference to the code table 17 (33), the decoding means 16 (32) decodes codes in both modules (at step 182). The system combines the decoded differential module and the decoded basic module to create an optimum module for the designated CPU (at step 183). 
     The system substitutes the module in the picture compressing means 4 (or the picture reproducing means 24) with the created optimum module (at step 184). 
     Next, with reference to the accompanying drawings, an embodiment of the present invention will be described in detail. In the following description, it is assumed that an Intel 80×86 processor is used. 
     FIGS. 12 and 13 are a first part and a second part of a list showing the structure of difference codes of program data, respectively. FIG. 12(A) shows an example of a program code. An instruction shown in FIG. 12(A) is used to move the content of a register bx to a register ax. As shown in FIG. 12(A), a program instruction (mov ax, bx) is divided into an operation code and operands. For an operand, a register is often used as shown in this example. Thus, some differential codes represent the change in the unit of instruction and the other differential codes represent changes in the unit of operation code, operand, and register. 
     FIG. 12(B) shows the list of the difference codes. As shown in FIG. 12(B), each difference code is composed of one byte. 
     &#34;00&#34; represents that no change arises. 
     &#34;01&#34; represents that the types of all the registers is changed from 32 bits to 16 bits. 
     &#34;02&#34; represents that the types of all the registers are changed from 16 bits to 32 bits. 
     &#34;03&#34; represents that the type of the first register is changed from 32 bits to 16 bits. 
     &#34;04&#34; represents that the type of the first register is changed from 16 bits to 32 bits. 
     &#34;05&#34; represents that the type of the second register is changed from 32 bits to 16 bits. 
     &#34;06&#34; represents that the type of the second register is changed from 16 bits to 32 bits. 
     &#34;07&#34; represents that the operand is substituted with the operand preceded by the difference code. 
     &#34;08&#34; represents that the first register is substituted with the register preceded by the difference code. 
     &#34;09&#34; represents that the second register is substituted with the register preceded by the difference code. 
     &#34;0A&#34; represents that the operation code is substituted with the operation code preceded by the difference code. 
     &#34;0B&#34; represents that the instruction of the existing line is substituted with the instruction preceded by the difference code. 
     &#34;0C&#34; represents that the instruction preceded by the difference code is inserted between the preceding line and the existing line. 
     &#34;0D&#34; represents that lines from the existing line to the line of the numeric value preceded by the difference code are substituted with the program code preceded by the numeric value. 
     &#34;0E&#34; represents that the program codes preceded by the numeric value is inserted between the preceding line and the existing line for the number of lines designated by the numeric value preceded by the difference code. 
     &#34;0F&#34; represents that the existing line is deleted. 
     &#34;10&#34; represents that the lines from existing line by the number designated by numeric value preceded by difference code are deleted. 
     &#34;11&#34; represents that the existing line and the next line are exchanged. 
     &#34;12&#34; represents that the existing line and the line designated by numeric value preceded by difference code are exchanged. 
     FIG. 13(C) is a list showing an example of the string of difference codes of program data. The first two codes represent the start line and the last line of the range in which difference exist. 
     &#34;0010&#34; is a two-byte BCD (Binary Coded Decimal) code that represents the start line number from which difference exists. 
     &#34;0014&#34; is a two-byte BCD code that represents the last line number to which difference exists. 
     &#34;01&#34;, &#34;04&#34;, &#34;00&#34;, &#34;0B, `inc ax`&#34;, &#34;00&#34; represents difference codes arranged in the ascending order of line numbers. 
     When there is another range of lines in which difference exist, the start line number and the last line number are described as, for example, &#34;0040&#34; and &#34;0045&#34;, respectively. After the last line number, difference codes are described in the ascending order of the line numbers. When there is no more line in which difference exist, &#34;0000&#34; is described. 
     In this embodiment, difference codes are described only for the range of lines in which difference exists in an aforementioned manner, the data size of the difference file becomes small. The data size of the difference file becomes smaller because, on the contrary to that an instruction is normally composed of three bytes of more, difference code is composed of only one byte. 
     In addition, since similar difference codes are arranged, when they are compressed by the entropy encoding method, the data size of the difference file becomes further decreased. 
     FIGS. 14 and 15 show an example in which a basic quantizing module is substituted with a quantizing optimum module for a CPU B. FIG. 14(A) shows program codes of a basic quantizing module. FIG. 14(B) shows program codes of the quantizing optimum module for the CPU B. FIG. 14(C) shows a top portion of difference codes of a quantizing differential module for the CPU B. FIG. 15 shows difference codes portion of the quantizing differential module for the CPU B. 
     Referring to FIG. 15, to create the optimum quantizing module for the CPU B, the following changes are performed. 
     Since the line &#34;0020&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0021&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0022&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the lines &#34;0023&#34; and &#34;0024&#34; describe the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. 
     Since the line &#34;0025&#34; describes the difference code &#34;0C&#34;, the program code &#34;push ax&#34;0 preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0026&#34; describes the difference code &#34;0C&#34;, the program code &#34;mov ax, cx&#34;0 preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0027&#34; describes the difference code &#34;07&#34;, the operand of the basic module of the line &#34;0025&#34; is substituted with the operand &#34;dx&#34;0 preceded by the difference code. Since the line &#34;0028&#34; describes the difference code &#34;0C&#34;, the program code &#34;mov cx, ax&#34;0 preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0028&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. 
     Since the line &#34;0030&#34; describes the difference code &#34;0C&#34;, the program code &#34;pop ax&#34;0 preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0031&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0032&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. 
     FIGS. 16 and 17 show an example of a process in which a basic DCT module is substituted with a DCT optimum module for the CPU B. FIG. 16(A) shows program codes of a basic DCT module. FIG. 16(B) shows program codes of the DCT optimum module for the CPU B. FIG. 16(C) shows a top portion of difference codes of a DCT differential module for the CPU B. FIG. 17 shows difference codes portion of the DCT differential module for the CPU B. 
     Referring to FIG. 17, to create an optimum DCT module for the CPU B, the following changes are performed. 
     Since the line &#34;0020&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0021&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0022&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0023&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0024&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0025&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0026&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0027&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0028&#34; describes the difference code &#34;00&#34;, no change is performed. Since the line &#34;0029&#34; describes the difference code &#34;0B&#34;, the existing line is substituted with the program code &#34;shr ax, cl&#34; preceded by the difference code. Since the line &#34;0030&#34; describes the difference code &#34;0D&#34;, the program codes &#34;neg cl&#34; and &#34;add cl, 16&#34; preceded by the difference code are inserted between the preceding line and the existing line. Since the line &#34;0032&#34; describes the difference code &#34;0C&#34;, the program code &#34;shr dx, cl&#34; preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0033&#34; describes the difference code &#34;0C&#34;, the program code &#34;or ax, dx&#34;0 proceeded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0034&#34; describes the difference code &#34;03&#34;, the type of the first register of the basic module of line &#34;0030&#34; is changed from 32 bits to 16 bits. 
     FIGS. 18 and 19 show an example of a process in which a basic motion compensating module is substituted with a motion compensating optimum module for the CPU B. FIG. 18(A) shows program codes showing the basic motion compensating module. FIG. 18(B) shows program codes of the motion compensating optimum module for the CPU B. FIG. 18(C) shows a top portion of a motion compensating differential module for the CPU B. FIG. 19 shows a difference codes portion of the motion compensating differential module for the CPU B. 
     Referring to FIG. 19, to create the optimum motion compensating module for the CPU B, the following changes are performed. 
     Since the line &#34;0020&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0021&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0022&#34; describes the difference code &#34;00&#34;, no change is performed. Since the line &#34;0023&#34; describes the difference code &#34;00&#34;, no change is performed. 
     Since the lines &#34;0024&#34; to &#34;0029&#34; describe the difference code &#34;00&#34;, no change is performed. Since the line &#34;0030&#34; describes the difference code &#34;0C&#34;, the program code &#34;mov [si], dx&#34;0 preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0031&#34; describes the difference code &#34;0B&#34;, the line &#34;0030&#34; of the basic module is substituted with the program code &#34;mov dx, [si+2]&#34; preceded by the difference code. Since the line &#34;0032&#34; describes the difference code &#34;0B&#34;, the existing line is substituted with the program code &#34;mov cx, [di+2]&#34; preceded by the difference code. Since the line &#34;0033&#34; describes the difference code &#34;00&#34;, no change is performed. 
     FIGS. 20 and 21 show an example of a process in which a basic YUV converting module is substituted with an YUV converting optimum module for the CPU B. FIG. 20(A) shows program codes of the basic YUV converting module. FIG. 20(B) shows program codes of the YUV converting optimum module for the CPU B. FIG. 20(C) shows a top portion of difference codes of a YUV converting differential module for the CFU B. FIG. 21 shows a difference codes portion of the YUV converting differential module for the CPU B. 
     Referring to FIG. 21, to create the optimum YUV converting module for the CPU B, the following changes are preformed. 
     Since the line &#34;0020&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0021&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0022&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0023&#34; describes the difference code &#34;00&#34;, no change is performed. 
     Since the line &#34;0024&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0025&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0026&#34; describes the difference code &#34;00&#34;, no changed is performed. Since the line &#34;0027&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. Since the line &#34;0028&#34; describes the difference code &#34;0C&#34;, the program code &#34;adc dx, 0&#34; preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0029&#34; describes the difference code &#34;03&#34;, the type of the register of the basic module of the line &#34;0028&#34; is changed from 32 bits to 16 bits. Since the line &#34;0030&#34; describes the difference code &#34;0C&#34;, the program code &#34;adc dx, 0&#34; preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0031&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. 
     Since the line &#34;0032&#34; describes the difference code &#34;0C&#34;, the program code &#34;mov bh, dl&#34; preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0033&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0034&#34; describes the difference code &#34;00&#34;, no changed is performed. Since the line &#34;00 35  &#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. Since the line &#34;0036&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. 
     FIGS. 22 and 23 show an example of a process in which a basic variable length encoding module is substituted with a variable length encoding optimum module for the CPU B. FIG. 22(A) shows program codes of the basic variable length encoding module. FIG. 22(B) shows program codes of the variable length encoding optimum module for the CPU B. FIG. 22(C) shows a top portion of difference codes of the optimum variable length encoding module for the CPU B. FIG. 23 shows a difference code portion of the variable length encoding differential module for the CPU B. 
     Referring to FIG. 23, to create the optimum variable length encoding module of the CPU B, the following changes are performed. 
     Since the line &#34;0020&#34; describes the difference code &#34;0C&#34;, the program code &#34;xchg bh, b1&#34; preceded by the difference code is inserted between the preceding line and the existing line. Since the line &#34;0021&#34; describes the difference code &#34;0A&#34;, the existing line is substituted with the program code &#34;xchg dh, d1&#34; preceded by the difference code. Since the line &#34;0022&#34; describes the difference code &#34;01&#34;, the types of all the registers are changed from 32 bits to 16 bits. 
     Since the line &#34;0023&#34; describes the difference code &#34;0C&#34;, the program code &#34;mov [di+2], dx&#34;0 is inserted between the preceding line and the existing line. Since the line &#34;0024&#34; describes the difference code &#34;03&#34;, the type of the first register is changed from 32 bits to 16 bits. 
     As described above, since the program for picture compression and reproduction executable on plural kind of CPU and DSP is consist of the basic modules and plural sets of differential modules corresponding to each CPU and DSP and they are compressed by entropy coding, the capacity of the program is reduced while maintaining the adaptability to plural kind of CPUs and DSPs. 
     In addition, according to the present invention, once an optimum compressing/reproducing program of each CPU, DSP, and so forth is created, unless they are changed, it is not necessary to create an additional compressing/reproducing program. 
     Although the present invention has been shown and described with respect to a best mode embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions, and additions in the form and detail thereof may be made therein without departing from the spirit and scope of the present invention.