Patent Publication Number: US-7589573-B2

Title: Startup circuit and method

Description:
RELATED APPLICATION 
   This application is a Continuation of U.S. application Ser. No. 10/930,976 titled “STARTUP CIRCUIT AND METHOD”, filed Aug. 31, 2004, now U.S. Pat. No. 7,145,372, issued Dec. 5, 2006, which is commonly assigned and incorporated herein by reference. 

   FIELD 
   The present invention relates generally to startup circuits and in particular the present invention relates to low power startup circuits. 
   BACKGROUND 
   Reference voltages are needed in equipment such as power supplies, current supplies, panel meters, calibration standards, data conversion systems, and the like. Bandgap reference circuits are typically chosen to produce reference voltages due to their ability to maintain stable output voltages that vary little with temperature and supply voltage. 
   A typical bandgap reference circuit  10  is shown in  FIG. 1 . Circuit  10  includes an amplifier  11  and a bandgap voltage generator  12 . The output of the bandgap reference circuit (at node Vbgr) stabilizes according to the following equation: 
                       Vbgr   =       Vbe   ⁢           ⁢   2     +       (       Vbe   ⁢           ⁢   1     -     Vbe   ⁢           ⁢   2       )     *     (     1   +     2   *   R   ⁢           ⁢     1   /   R     ⁢           ⁢   2       )                     =       Vbe   ⁢           ⁢   2     +       (     Vt   *     ln   ⁡     (   n   )         )     *     (     1   +     2   *   R   ⁢           ⁢     1   /   R     ⁢           ⁢   2       )                       (   1   )               
where Vbe 1  and Vbe 2  are the base to emitter voltages of bipolar junction transistors (BJTs)  15  and  16 , respectively, and R 1  and R 2  are the resistances of the resistors  13  and  14  respectively. Vt is the thermal voltage, which is approximately 25.853 milliVolts (mV) at a temperature of 300 degrees Kelvin (˜26.84 degrees Celsius), and n is the ratio of the current density of BJTs  15  and  16 .
 
   In equation (1), the first term on the right hand side has a negative temperature coefficient, while the second term on the right had side has a positive temperature coefficient. An almost zero temperature coefficient can be obtained by setting a proper ratio between the first and the second terms on the right had side of the equation. 
   An intrinsic problem with a bandgap reference circuit such as circuit  10  is that it has two stable states. A first stable state is the normal operational state, where Vbgr is equal to about 1.25 Volts (V). The second stable state is the zero-current state, where Vbgr is equal to 0 and Vbias is equal to 0. 
   To prevent the reference circuit  10  from staying in the zero-current state, a startup circuit, such as startup circuit  23  shown in  FIG. 2 , is normally added to the bandgap reference circuit. The startup circuit may include a resistor and several diode-connected n-channel metal oxide semiconductor field effect transistors (NMOSFETs). In circuit  23 , the voltage at terminal  24  is higher than Vt 1 +Vt 2 , where Vt 1  and Vt 2  are the threshold voltages of transistors  18  and  19 , respectively. This ensures that Vbias, Vbgr, and the voltage at node  25  will be pulled to at least Vt 1 +Vt 2 −Vt 3 , where Vt 3  is the threshold voltage of the transistors  20 ,  21 , and  22 . Therefore, using the startup circuit  23 , the bandgap circuit will be powered up to the normal operational state. 
   The startup circuit  23  has two major drawbacks. First, if the power supply voltage Vcc is less than Vt 1 +Vt 2 , then Vbias, Vbgr, and the voltage at node  25  can only be pulled up to a level of Vcc−Vt 3 . For example, if Vcc=1.6 V, and Vt 3 =1.0 V, Vbias, Vbgr, and the node  25  voltage can be pulled to 0.6 V, which is not enough to turn on the NMOSFETs  26 ,  27 ,  28 , and  29 , and BJTs  15  and  16  provided the threshold voltages of those devices are larger than 0.6 V, since typical threshold voltages for such devices are approximately 0.7 V. Therefore, the bandgap reference circuit  10  will stay in the zero-current state. Second, the startup circuit  23  consumes power during the normal operation of the circuit  10 . This is unacceptable, especially if the circuit  10  is used for portable devices, which have stringent power consumption requirements of a few microwatts. 
   For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a startup circuit for low power circuits. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a circuit diagram of a prior art bandgap reference circuit; 
       FIG. 2  is a circuit diagram of a prior art startup circuit connected to a bandgap reference circuit; 
       FIG. 3  is a circuit diagram of a startup circuit according to one embodiment of the present invention; 
       FIG. 4  is a circuit diagram of a startup circuit according to one embodiment of the present invention connected to a reference circuit; 
       FIG. 5  is a plot of Vbgr current injection over time for one embodiment of the present invention; 
       FIG. 6  is a plot of Vbgr node voltage over time for one embodiment of the present invention; and 
       FIG. 7  is a block diagram of a memory and processing system on which embodiments of the present invention are practiced. 
   

   DETAILED DESCRIPTION 
   In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. 
   The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
   An improved startup circuit  300  is shown in  FIGS. 3 and 4 .  FIG. 3  is a circuit diagram of a startup circuit  300  according to one embodiment of the present invention. Circuit  300  comprises two circuit branches  310  and  320 , each connected between a supply voltage  302  and ground. Branch  310  includes a PMOS transistor  336 , and NMOS transistors  337  and  338 , all source to drain connected in series between the supply voltage  302  and ground. Transistors  336  and  338  are each gate connected to an enable signal enb. Branch  320  includes four PMOS transistors  331 ,  332 ,  333 , and  334 , and two NMOS transistors  339  and  335 , all source to drain connected in series between the supply voltage and ground. The PMOS transistors  331 ,  332 ,  333 ,  334 , and  335  are each gate connectable to a node (indicated in  FIG. 3  as Vbgr) of a circuit that is to be started using the circuit  300 . The gate of transistor  337  is connected to a node  340  between transistor  334  and transistor  339 , and the gate of transistor  339  is connected to a node  342  (also node Vbgr, see also  FIG. 4 ) between transistor  337  and transistor  338 . 
   Circuit  300  is shown connected to a bandgap reference circuit  400  in  FIG. 4 . Node  342 /Vbgr of circuit  300  is connected to the node of the circuit to be started, in this embodiment node Vbgr of bandgap reference circuit  400 , to start node Vbgr. Circuit  400  is similar to circuit  10  of  FIG. 1  in one embodiment. Two PMOS transistors  440  and  441  are connected to the enable signal enb in the circuit  400 . 
   Before the reference circuit  400  is started, the enable signal providing a potential to node enb and to transistors  336  and  338  of circuit  300  is at Vcc. With this voltage at node enb, transistors  336 ,  440 , and  441  are off. NMOSFET  338  is on, pinning node Vbgr to ground. NMOSFETs  335  and  339  are off, and PMOSFETs  331 ,  332 ,  333 , and  334  are fully on. Node  340  is therefore pulled to Vcc. NMOSFET  337  is on, but no current flows into node Vbgr because PMOSFET  336  is off. BJT  416  is also off. This greatly reduces if not eliminates leakage current through branch  310  of the circuit  300 . 
   When the reference circuit  400  is enabled, node enb goes to ground. Initially, node Vbgr remains close to ground. PMOSFETs  331 ,  332 ,  333 ,  334 ,  440 , and  441  turn on, NMOSFET  337  is on, and NMOSFETs  335  and  338  are off. At the beginning of the cycle, PMOSFET  336  and NMOSFET  337  are fully on (their absolute gate to source voltages are approximately Vcc). Therefore at the beginning of the cycle, a large current injects into node Vbgr through FETs  336  and  337 . The ideal current value can be represented as:
 
μ* Cox*W/L *(| Vgs|−|Vt |) 2 /2
 
of PET  336  if it is weaker than FET  337 , or
 
μ* Cox*W/L *(| Vgs|−|Vt |) 2 /2
 
of FET  337  if it is weaker than PET  336 .
 
   The current injection into node Vbgr after the circuit has been enabled at the time of approximately 300 nanoseconds is shown in  FIG. 5 . The current injection brings node Vbgr to a higher voltage. When the voltage at node Vbgr becomes greater than about 0.7 V at room temperature, BJT  416  turns on. 
   After the bandgap reference circuit stabilizes to the operational state, node Vbgr rises to approximately 1.25 V. At this potential, NMOSFETs  335  and  339  are on. PMOSFET  331  switches from fully on at the beginning of the startup sequence to weakly on (its absolute gate to source voltage equals Vcc−Vbgr). The drain to source voltage drop across the weakly on FET  331  causes the source voltage of FET  332  to drop below Vcc. The body effect, caused by the source voltage of FET  332  being lower than the Nwell voltage (Vcc) gives transistor  332  a higher threshold voltage Vt than transistor  331 . Therefore, PMOS  332  is on, but is on even more weakly than PMOS  331 , presuming they have the same size, because |Vgs−Vt| of PMOS  332  is smaller than PMOS  331 . Similar analysis applies to PMOSs  333  and  334 . The result is that the voltage at node  340  is pushed very close to ground. The node voltage at node  340  after the circuit has been enabled for approximately 300 ns is shown in  FIG. 6 . PMOS  334  and NMOS  337  are actually off at this time. The current consumption of the two branches  310  and  320  of the startup circuit  300  after startup is zero if leakage current is not taken into account. After startup, the voltage at node Vbgr can remain at any voltage between Vtn and Vcc (approximately 1.8 V) and not be disturbed by the startup circuit, where Vtn is the threshold voltage of devices  335  and  339 . 
   In another embodiment, two more startup circuits like startup circuit  300  are used to start up nodes  425  and Vbias of circuit  400 . Such circuits are connected similarly to the way circuit  300  is connected to node Vbgr of circuit  400 , and operate in the same fashion. Nodes  425  and Vbias in that embodiment each have their own startup circuit, with the respective nodes fed back in the same way as circuit  300  has node Vbgr fed back to it to start up node Vbgr. Each can use a separate startup circuit with its own enable signal, and feeds nodes back the same way node Vbgr is fed back to the circuit  300 . In this way, multiple nodes of a circuit can be started, with the same benefits of the startup circuit. Further, the nodes can be started in an order that is most logical for power consumption and the like for the circuit being started. 
   Other types of circuits for which the embodiments of the present invention are useful include by way of example but not by way of limitation, any circuit using a large amount of current injection which then shuts off itself after stabilization of the Vbgr node. The startup circuit embodiments of the present invention may be used with many different startup circuits, not just bandgap circuits, but anything that is to be started. Further, many low power analog circuits also need and use startup circuits. The embodiments of the present invention are also amenable to use with such analog circuits as well. 
     FIG. 7  is a functional block diagram of a memory device  700 , such as a flash memory device, of one embodiment of the present invention, which is coupled to a processor  710 . The memory device  700  and the processor  710  may form part of an electronic system  720 . The memory device  700  has been simplified to focus on features of the memory that are helpful in understanding the present invention. The memory device includes an array of memory cells  730 . The memory array  730  is arranged in banks of rows and columns. 
   An address buffer circuit  740  is provided to latch address signals provided on address input connections A 0 -Ax  742 . Address signals are received and decoded by row decoder  744  and a column decoder  746  to access the memory array  730 . It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends upon the density and architecture of the memory array. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts. 
   The memory device reads data in the array  730  by sensing voltage or current changes in the memory array columns using sense/latch circuitry  750 . The sense/latch circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array. Data input and output buffer circuitry  760  is included for bi-directional data communication over a plurality of data (DQ) connections  762  with the processor  710 , and is connected to write circuitry  755  and read/latch circuitry  750  for performing read and write operations on the memory  700 . 
   Command control circuit  770  decodes signals provided on control connections  772  from the processor  710 . These signals are used to control the operations on the memory array  730 , including data read, data write, and erase operations. An analog voltage and current supply  780  is connected to control circuitry  770 , row decoder  744 , write circuitry  755 , and read/latch circuitry  750 . In a flash memory device, analog voltage and current supply  780  is important due to the high internal voltages necessary to operate a flash memory. The flash memory device has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. 
   A startup circuit, such as startup circuit  300 , is shown in  FIG. 7  connected to control circuitry  770 , address circuitry  740 , and analog voltage and current supply  780 . The startup circuit  300  is used in various embodiments in a memory device and in a processing system including processor  710 , to startup various nodes of the circuitry within the memory device or the system. It should be understood that any circuit or node in such a memory device or processing system that needs to be started may be started with the embodiments of the present invention, and that while not all connections are shown, such connections and use of the startup circuit embodiments of the present invention are within its scope. It should also be understood that while a generic memory device is shown, the startup circuit embodiments of the present invention are amenable to use with multiple different types of memory devices, including but not limited to dynamic random access memory (DRAM), synchronous DRAM, flash memory, and the like. 
   The embodiments of the present invention offer good startup behavior to a reference circuit while keeping almost zero current consumption after startup. The concept is in part based on the MOSFET body effect, so it is reliable and easy to implement, and has a small size. 
   CONCLUSION 
   A startup circuit has been described that is able to inject high current into npn bipolar junction transistors, pnp BJTs, or the gates of MOSFET current sources in order to start a reference circuit with a Vcc of 1.4-2.2 V. The invention utilizes the body effect of MOSFETs to eliminate the leakage through the startup circuit after the bandgap circuit successfully starts, while still offering strong current injection during startup of the bandgap circuit. 
   Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.