Patent Publication Number: US-6661289-B2

Title: Voltage-to-current conversion circuit and OTA using the same

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a Rail-to-Rail voltage-to-current conversion circuit, comprising MOSFETs, and in which the linear operating range has been extended to the power source range, and an OTA (Operational Transconductance Amplifier) using the same. More particularly, the present invention relates to a voltage-to-current conversion circuit, in which the transconductance is kept constant by using two MOSFETs of the same polarity, and an OTA using the same. 
     Recently, it has become important to reduce the voltage of the power source of an analog integrated circuit composed of MOSFETs, from the general requirements of the reduction in power consumption of semiconductor integrated circuits and in withstand voltage of devices. 
     An analog-to-digital hybrid circuit is an integrated circuit that is expected to be widely used in the future. In a digital circuit, the power consumption is in proportion to the second power of the power source voltage to be supplied to the circuit and, therefore, reduction in power source voltage is an effective approach to reduce the power consumption. As a result, there is a trend that the power source voltage of a digital circuit is lowered year after year. As the power source voltage of a digital circuit is lowered, that of the part of an analog circuit composed of MOSFETs, which is realized on the same chip, is required to be lower. On the other hand, as the signal processing becomes more complicated, the operating speed of an integrated circuit increases, the semiconductor process becomes finer in order to enable a higher speed operation, and as a result, the withstand voltage of a device is lowered. Therefore, the reduction in power source voltage becomes an unavoidable issue in an integrated circuit using a high-speed processor. 
     Generally, the reduction in power source voltage in an analog integrated circuit causes a problem that the linear range of an input signal is reduced. Various Rail-to-Rail circuits, in which the linear range of input signal has been extended to that of the positive and negative power source voltage, have been proposed as circuit configurations to solve this problem. 
     Among the fundamental circuit elements in an analog circuit composed of MOSFETs, there are the voltage-to-current conversion circuit that generates an output current in accordance with an input voltage and the OTA (Operational Transconductance Amplifier) using same. FIG. 1 is a diagram that shows circuit symbols of an OTA. An OTA circuit  1  puts out an output current Iout in accordance with the difference between two input voltages Vin 1  and Vin 2 . For the above-mentioned voltage-to-current conversion circuit and OTA, the Rail-to-Rail circuit has been proposed. 
     FIG. 2 is a diagram that shows the configuration of the Rail-to-Rail OTA circuit, which has been disclosed in M. F. Li, U. Dasgupta, X. W. Zhang, Y. C. Lim, “A low-Voltage CMOS OTA with Rail-to-Rail Differential Input Range”, IEEE Trans. Circuit and Systems 1, vol. 47, pp. 1-8, January 2000. As shown schematically, the OTA circuit has extended the linear input range by using in parallel a pOTA circuit  1   p  composed of a p channel MOSFET and an nOTA circuit  1   n  composed of an n channel MOSFET. In this circuit, however, which uses a p channel MOSFET and an n channel MOSFET, the matching of the transconductances of transistors of different polarity is required in order to achieve a linear characteristic. 
     Takai, Watanabe, Takagi, Fujii, “Rail-to-Rail OTA using Transconductance-Parameter-independent OTA”, ECT-00-94, pp. 73-78, October 2000 has disclosed the configuration in which the transconductance of two input circuits is kept constant by the control voltage generated by using circuits similar to those of the two input circuits, and furthermore, the influence of the operation at the point where the operations of the two input circuits switch is suppressed by using a current selection circuit. 
     Moreover, Sato, Takagi, Fujii, “Rail-to-Rail OTA using One kind MOSFET&#39;s as VCCS”, ECT-00-95, pp. 79-84, October 2000 has disclosed the OTA that has combined a pair of MOSFETs and a MOSFET of the same polarity. Since the OTA is composed of MOSFETs of the same polarity, there is no problem about the matching of transconductances. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to realize a voltage-to-current conversion circuit composed of MOSFETs of the same polarity, which can realize an OTA with Rail-to-Rail with a simpler configuration. 
     FIG. 3 is a diagram that shows the basic configuration of the voltage-to-current conversion circuit of the present invention. As shown schematically, the voltage-to-current conversion circuit of the present invention is characterized by comprising a first MOSFET  11 , to which a fixed drain-source voltage is applied all the time and which generates a first current signal ID 1  for the input voltage, a second MOSFET  12 , which has the same polarity as that of the first MOSFET  11 , to which the fixed drain-source voltage is applied all the time, and which generates a second current signal ID 2  for the input voltage, which is complementary to the first current signal ID 1 , and a difference current operation circuit  13  that performs the operation to calculate the difference between the first current signal ID 1  and the second current signal ID 2 . 
     The first MOSFET  11  and the second MOSFET  12  can each be an n channel type or a p channel type as long as they have the same polarity. 
     There are various modifications for the method to make the first MOSFET  11  and the second MOSFET  12  operate so as to generate current signals complementary to each other. FIG. 4A is a diagram that shows the basic configuration in which the sources of the first MOSFET  11  of n channel type and the second MOSFET  12  of n channel type are grounded and a fixed voltage is applied to each drain, and FIG. 4B is a diagram that shows the voltage-to-current characteristics of the two MOSFETs. 
     In this basic configuration, the sources of the first MOSFET  11  and the second MOSFET  12  are grounded, respectively, as shown in FIG. 4A, and a voltage VDS is applied to each drain. An input voltage Vin is applied to the gate of the first MOSFET  11 . A gate voltage generation circuit  14  generates and applies a voltage 2VT+VDS−Vin to the gate of the second MOSFET  12 . Here, VT is the threshold voltage of the MOSFET. 
     First, the variation characteristic of the current ID 1  versus the input voltage Vin of the first MOSFET  11  is described. The operation of the MOSFET can be divided into three regions according to the relationship between a drain-source voltage VDS and a gate-source voltage VGS, as shown in FIG. 4B, and a drain current ID in each region is as follows. 
     Cutoff region: VGS≦VT 
     ID=0 
     Saturation region: VT&lt;VGS, VGS−VT&lt;VDS 
     ID=K (VGS−VT) 2    
     Non-saturation region: VT&lt;VGS, VDS&lt;VGS−VT 
     ID=2K (VGS−VT−VDS/2) VDS 
     Therefore, if the gate-source voltage is assumed to be the input voltage Vin, the linear relationship between the input voltage and the drain current holds only in the non-saturation region. 
     Since the voltage 2VT+VDS−Vin is applied to the gate of the second MOSFET  12  in FIG. 4A, the drain current ID 2  changes as shown in FIG. 4B for the input voltage Vin. In other words, the current characteristic is so established that the drain current ID 2  and the drain current ID 1  are symmetrical with respect to the symmetry axis at which the input voltage is VT+VDS/2. Such a relationship between the first MOSFET  11  and the second MOSFET  12  is referred to as the complementary action to each other here, and ID 1  and ID 2  are referred to as the currents complementary to each other. 
     Therefore, the difference current IO, which is obtained by subtracting the drain current ID 2  of the second MOSFET  12  from the drain current ID 1  of the first MOSFET  11 , is as follows in each region. 
     Region A: Vin≦VT 
     First MOSFET  11 : Cutoff region, ID 1 =0 
     Second MOSFET  12 : Non-saturation region 
     ID 2 =−2K·VDS·Vin+K (VDS+2VT) VDS 
     IO=2K·VDS·Vin−K (VDS+2VT) VDS 
     Region B: VT&lt;Vin&lt;VT+VDS 
     First MOSFET  11 : Saturation region, ID 1 =K (Vin−VT) 2    
     Second MOSFET  12 : Saturation region 
     ID 2 =K (2VT+VDS−Vin−VT) 2    
     IO=2K·VDS·Vin−K (VDS+2VT) VDS 
     Region C: VT+VDS≦Vin 
     First MOSFET  11 : Non-saturation region 
     ID 1 =2K·VDS·Vin−K (VDS+2VT) VDS 
     Second MOSFET  12 : Cutoff region, ID 2 =0 
     IO=2K·VDS·Vin−K (VDS+2VT) VDS 
     As described above, a voltage-to-current conversion circuit, having a linear input signal range from the grounding potential to the power source voltage, can be realized with a circuit that uses the two n channel MOSFETs shown in FIG.  4 A. 
     In the configuration shown FIG. 4A, the sources of the first MOSFET  11  and the second MOSFET  12  are grounded, respectively, and the voltage VDS is applied to each drain so that the first MOSFET  11  and the second MOSFET  12  are made to operate so as to produce current signals complementary to each other. There are, however, various modifications for the method to make both the first MOSFET  11  and the second MOSFET  12  produce complementary current signals. FIG.  5 A and FIG. 5B show examples of those modifications. 
     In the configuration shown in FIG. 5A, the source of the first MOSFET  11  is grounded and the voltage VDS is applied to the drain, which are the same as the case of the configuration shown in FIG. 4, but the input voltage Vin is applied to the source of the second MOSFET  12 , the constant voltage VG, which is equal to VDS+2VT, is applied to the gate, and the voltage VDS+Vin generated in a drain voltage generation circuit  15  is applied to the drain. Therefore, the drain-source voltage becomes VDS. In this case, the operations of the first MOSFET  11  and the second MOSFET  12  can be divided into the following three regions according to the input voltage Vin. 
     Region A: Vin≦VT 
     First MOSFET  11 : Cutoff region, ID 1 =0 
     Second MOSFET  12 : Non-saturation region 
     ID 2 =−2K (Vin−VG/2) (VG−2VT) 
     IO=2K·Vin (VG−2VT)−K·VG (VG−2VT) 
     Region B: VT&lt;Vin&lt;VG−VT 
     First MOSFET  11 : Saturation region, ID 1 =K (Vin−VT) 2    
     Second MOSFET  12 : Saturation region 
     ID 2 =K (VG−Vin−VT) 2    
     IO=2K·Vin (VG−2VT)−K·VG (VG−2VT) 
     Region C: VG−VT≦Vin 
     First MOSFET  11 : Non-saturation region 
     ID 1 =2K (Vin−VG) (VG−2VT) 
     Second MOSFET  12 : Cutoff region, ID 2 =0 
     IO=2K·Vin (VG−2VT)−K·VG (VG−2VT) 
     As described above, a voltage-to-current conversion circuit, having a linear input signal range from the grounding potential to the power source voltage, can be realized with a circuit that uses the two n channel MOSFETs shown in FIG.  5 A. 
     In the configuration shown in FIG. 5A, the constant voltage VG to be applied to the gate of the second MOSFET  12  is generated in the constant voltage source, but another configuration is possible in which VDS+2 VT is generated from the voltage VDS in a gate bias generation circuit  16  and applied to the gate of the second MOSFET  12  as shown in FIG.  5 B. 
     Although the cases where n channel MOSFETs are used have been described above as examples, it is also possible to use p channel MOSFETs in the configuration. 
     According to the present invention, as described above, attention has been focused on the fact that the difference in the currents that flow in two MOSFETs is linear with the input voltage within the power source voltage range, if the two MOSFETs of the same polarity are so set that the currents that flow in each MOSFET vary symmetrically with respect to a fixed input voltage value, that is, that they operate complementarily. Therefore, operation conditions can be set variously as long as two MOSFETs operate complementarily. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a diagram that shows the general symbols used in a circuit diagram of an OTA; 
     FIG. 2 is a diagram that shows a conventional example of an OTA with Rail-to-Rail, which is the combination of an OTA circuit of a p channel MOSFET and that of an n channel MOSFET; 
     FIG. 3 is a diagram that shows the basic configuration of the voltage-to-current conversion circuit of the present invention; 
     FIG.  4 A and FIG. 4B are diagrams that show the basic circuit configuration and the operation principles, respectively, of the first aspect that realizes the voltage-to-current conversion circuit of the present invention; 
     FIG.  5 A and FIG. 5B are diagrams that show the basic circuit configuration and an example of the modification, respectively, of the second aspect that realizes the voltage-to-current conversion circuit of the present invention; 
     FIG. 6 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit in the first embodiment, which is the voltage-to-current conversion circuit of the first aspect of the present invention realized using n channel MOSFETs; 
     FIG. 7 is a diagram that shows an example of the circuit configuration of a 2 VT generation circuit to be used in the embodiments of the present invention; 
     FIG. 8 is a diagram that shows the rough configuration of an OTA that uses the two voltage-to-current conversion circuits in the first embodiment; 
     FIG. 9 is a diagram that shows the circuit configuration of the OTA shown in FIG. 8; 
     FIG. 10 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit in the second embodiment, which is the voltage-to-current conversion circuit of the first aspect of the present invention realized using p channel MOSFETs; 
     FIG. 11 is a diagram that shows the rough configuration of the voltage-to-current conversion circuit in the third embodiment, which is the voltage-to-current conversion circuit of the second aspect of the present invention realized using n channel MOSFETs; 
     FIG. 12 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit in the third embodiment; 
     FIG. 13 is a diagram that shows the input voltage-to-output current characteristic of the voltage-to-current conversion circuit in the third embodiment; 
     FIG. 14 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit of a modification example of the third embodiment; 
     FIG. 15 is a diagram that shows the rough configuration of an OTA that uses the two voltage-to-current conversion circuits in the third embodiment; 
     FIG. 16 is a diagram that shows a part of the circuit configuration of the OTA shown in FIG. 15; 
     FIG.  17 A and FIG. 17B are diagrams that show a part of the circuit configuration of the OTA shown in FIG. 15; 
     FIG. 18 is a diagram that shows a part of the circuit configuration of the OTA shown in FIG. 15; 
     FIG. 19 is a diagram that shows a part of the circuit configuration of the OTA shown in FIG. 15; 
     FIG. 20 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit in the fourth embodiment, which is the voltage-to-current conversion circuit of the second aspect of the present invention realized using p channel MOSFETs. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 6 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit in the first embodiment of the present invention and this embodiment is an example in which the basic configuration shown in FIG. 4A is realized using n channel MOSFETs. As shown in FIG. 6, the voltage-to-current conversion circuit in the first embodiment comprises an n channel MOSFET (field effect transistor) M 1  that corresponds to the first MOSFET and an n channel MOSFET (field effect transistor) M 2  that corresponds to the second MOSFET shown in FIG. 4, respectively, a circuit  21  that generates the voltage 2 VT+VDS from the voltage VDS and the voltage 2 VT, a circuit  22  that generates the voltage 2 VT+VDS−Vin from the voltage 2 VT+VDS and the input voltage Vin, a circuit  23  that generates the voltage VDS from the voltage VDS, which is applied to the transistor, a circuit  24  that fixes the drain potential of M 1  to VDS and takes out its current ID 1 , a circuit  25  that fixes the drain potential of M 2  to VDS and takes out its current ID 2 , and a difference operation circuit  26  that performs the operation of the difference current IO between ID 1  and ID. Therefore, the part composed of the circuit  21  and the circuit  22  corresponds to the gate voltage generation circuit  14  in FIG.  4 A. 
     The voltage 2 VT to be supplied to the circuit  21  is twice as great as that of the threshold voltage that the n channel MOSFET possesses, and for example, the circuit disclosed in Wada, Takagi, Fujii, “Realization of MOSFET Characteristics without Cutoff Region”, ECT-99-113, pp. 19-24, October 1999 can be used. One example of the circuit is shown in FIG.  7 . 
     The circuit  21  and the circuit  22  generate the voltage 2 VT+VDS−Vin to be applied to the gate of M 2 . As shown in FIG. 4B, the range of the input voltage Vin in which the drain current flows into M 2  is as follows. 
     
       
         0 ≦Vin&lt;VDS+VT   (1) 
       
     
     Since the gate potential VG 2  of M 2  is 2 VT+VDS−Vin, VG 2  varies in the following range. 
     
       
           VT&lt;VG   2 &lt; VDS+ 2 VT   (2) 
       
     
     Therefore, it is required that the input signal range of the circuit  21  and the circuit  22  should be larger than that shown in the expression (1). The circuit  21  is a level shift circuit composed of two p channel MOSFETs and generates 2 VT+VDS by shifting 2 VT by VDS in the positive direction. The circuit  22  is also a level shift circuit composed of two n channel MOSFETs and generates 2 VT+VDS−Vin by shifting 2 VT+VDS by Vin in the negative direction. It is assumed that all the constituent MOSFETs of the circuit  21  and the circuit  22  operate in the saturation region and a region called a weak reversal region. Moreover, the fact is utilized that since the drain current of the MOSFET depends only on the voltage between the gate and the source in the saturation region and the weakly reversal region, the voltages between the gate and the source of the two MOSFETs in which the same drain current flows are equal to each other. 
     In order for the p channel MOSFET in the circuit  21 , to the gate of which VDS is applied, always to be able to operate in the saturation region and the weak reversal region, the power source voltage VDD is required to satisfy the following expression, 
     
       
         2 VT−|VTP|+ 2 VDS&lt;VDD   (3) 
       
     
     where VTP is the threshold voltage of the p channel MOSFET. In addition, in order for the n channel MOSFET, to the gate of which Vin is applied, to be able to operate in the saturation region and the weak reversal region, the following condition has to be satisfied. 
     
       
         VDS≦VT  (4) 
       
     
     The circuit  26  is a current mirror circuit and generates the difference current IO between the current ID 1  that flows through M 1  and the current ID 2  that flows through M 2 . The difference current IO is shown by the following expression.                    IO   =     ID1   -   ID2                 =       2        K   ·   VDS   ·   Vin       -       K        (     VDS   +     2      VT       )          VDS                     (   5   )                         
     Next, the OTA that uses the voltage-to-current conversion circuit in the first embodiment is described. The OTA is a circuit that puts out the current Iout corresponding to the difference between the two input voltages Vin 1  and Vin 2 , as shown in FIG. 1, and the relationship is shown as follows, where the conversion coefficient is assumed to be gm,                      I                 out     =     gm        (     Vin1   -   Vin2     )                   =       gm   ·   Vin1     -     gm   ·   Vin2                     (   6   )                         
     Therefore, the OTA can be realized by using the two voltage-to-current conversion circuits in the first embodiment. 
     FIG. 8 is a diagram that shows a configuration of an OTA that uses the two voltage-to-current conversion circuits in the first embodiment. The input signal range of the voltage-to-current conversion circuit in the first embodiment is that of the power source voltage, therefore, this OTA also has the input signal range of the Rail-to-Rail. As shown schematically, this OTA comprises a first voltage-to-current conversion circuit  31 , a second voltage-to-current conversion circuit  32 , a 2 VT generation circuit  20  that generates 2 VT as shown in FIG. 7, a 2 VT+VDS generation circuit  21  shown in FIG. 6, a 2 VT+VDS−Vin 1  generation circuit  22 A that generates 2 VT+VDS−Vin 1  to be supplied to the first voltage-to-current conversion circuit  31 , a 2 VT+VDS−Vin 1  generation circuit  22 B that generates 2 VT+VDS−Vin 1  to be supplied to the second voltage-to-current conversion circuit  32 , and a difference output operation circuit  33  that performs the operation to calculate the difference current Iout between the output currents  101  and  102  of the first and the second voltage-to-current conversion circuits  31  and  32 . 
     If the currents that flow through the first MOSFET and the second MOSFET in the first voltage-to-current conversion circuit  31  are denoted as ID 11  and ID 12 , respectively, and the currents that flow through the first MOSFET and the second MOSFET in the second voltage-to-current conversion circuit  32  are denoted as ID 21  and ID 22 , respectively, the above-mentioned expression ( 6 ) is rewritten as follows.                I                 out     =     IO1   -   IO2                 =       (     ID11   -   ID12     )     -     (     ID21   -   ID22     )                   =       (     ID11   +   ID22     )     -     (     ID12   +   ID21     )                             
     Then, in the difference output operation circuit  33 , the difference is calculated after the operations of addition of ID 11  and ID 22  and that of ID 12  and ID 21  are performed. 
     FIG. 9 is a diagram that shows the circuit configuration of the OTA. In the figure, however, the 2 VT generation circuit  20  and the 2 VT+VDS generation circuit are omitted. 
     In the first embodiment, the n channel MOSFETs are used as M 1  and M 2 , but it is also possible to use p channel MOSFETs. The second embodiment is an example of this case. 
     FIG. 10 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit in the second embodiment. AS shown in FIG. 10, the voltage-to-current conversion circuit in the second embodiment comprises a circuit  41  that generates VDD−2|VTP|−VDS, a circuit  42  that generates 2 VDD−2|VTP|−VDS−Vin, a circuit  43  that generates VDS to be applied to the gate, a circuit  44  that fixes the drain current of the first MOSFET (MP 1 ) of p channel type to VDD−VDS and takes out its drain current, and a circuit  45  that fixes the drain current of the second MOSFET (MP 2 ) of p channel type to VDD−VDS and takes out its drain current. 
     Next, the basic configuration shown in FIG. 5A is described with the third embodiment that is realized using n channel MOSFETs. 
     FIG. 11 is a diagram that shows the rough configuration of the voltage-to-current conversion circuit in the third embodiment. As shown schematically, the voltage-to-current conversion circuit in the third embodiment comprises M 1  that corresponds to the first MOSFET and M 2  that corresponds to the second MOSFET in FIG. 5A, respectively, a power source VG that supplies the gate voltage VG to be applied to the gate of M 2 , a 2 VT generation circuit  51 , a circuit  52  that generates the voltage VG−2 VT from the fixed voltage VG and 2 VT, a circuit  53  that generates the voltage VG−2 VT+Vin from the VG−2 VT and the input voltage Vin, an M 1  drain bias circuit  54  that fixes the drain potential of M 1  to VDS and takes out its current ID 1 , an M 2  drain bias circuit  55  that fixes the drain potential of M 2  to VDS and takes out its current ID 2 , an M 2  source bias circuit  56  that applies the input voltage Vin to the source of M 2 , and a difference operation circuit  57  that performs the operation to calculate the difference current IO between ID 1  and ID 2 . Therefore, the part composed of the circuits  51  to  53  corresponds to the drain voltage generation circuit  15  in FIG.  5 A. 
     FIG. 12 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit in the third embodiment. The power source VG and the 2 VT generation circuit  51  are omitted. As shown schematically, the configuration of each part of the circuit is similar to that of the first embodiment, and the operations are also similar. As the operation principles of the entire voltage-to-current conversion circuit are the same as those described with reference to FIG. 5A, a more detailed description is not given here. 
     FIG. 13 shows the simulation results of the relationship between the input voltage Vin and the output current IO of the voltage-to-current conversion circuit in the third embodiment. As shown schematically, it is known that an almost linear output current IO can be obtained for the input voltage Vin within the power source voltage range. 
     In the voltage-to-current conversion circuit in the third embodiment, the input voltage Vin is applied to the source of M 2  via the M 2  source bias circuit  56 , but it is possible to apply the input voltage Vin directly to the source. FIG. 14 is a diagram that shows the circuit configuration of one example of the modifications. In this modification example, the input voltage Vin is applied directly to the source terminal of M 2 , and simultaneously the current ID 2  is generated after the ID 2 ′ taken out from the drain side is turned back by the current mirror circuit and taken out to the grounding side, in order to prevent the current from flowing to the input terminal of the input voltage Vin. Other parts are the same as those of the third embodiment. 
     Since the voltage-to-current conversion circuit in the third embodiment also shows the linear output characteristic for the input signal within the power source voltage range, the OTA circuit with Rail-to-Rail can be realized by using two of the circuits. FIG. 15 is a diagram that shows a configuration of an OTA circuit that uses two of the voltage-to-current conversion circuits in the third embodiment. As shown schematically, the OTA circuit comprises a circuit  61  that generates VG−2 VT and VDD−VG+2 VT, an M 11  circuit  62 , an M 12  circuit  63 , an M 21  circuit  64 , an M 22  circuit  65 , and a difference output operation circuit  66 . The circuit  61  corresponds to the circuit  52  in FIG. 12, the M 11  circuit  62  and the M 21  circuit  64  correspond to M 1  and the circuit  54  in FIG. 12, respectively, and the M 12  circuit  63  and the M 22  circuit  65  correspond to the part composed of M 2 , the circuit  55 , and the circuit  56  in FIG. 12 or to that composed of M 2 , the circuit  55 ′, and the current mirror circuit in FIG.  14 . The circuit  53  in FIG. 12 is included in the M 12  circuit  63  and the M 22  circuit  65 . In this OTA also, the difference output operation circuit  66  performs the operation to calculate the difference after the operations to calculate the addition of ID 11  and ID 22  and that of ID 12  and ID 21 . 
     The concrete circuit configuration of this OTA is shown in FIG. 16 to FIG.  19 . FIG. 16 shows the circuit  61  that generates VG−2 VT and VDD−VG+2 VT, FIG.  17 A and FIG. 17B show the M 11  circuit  62  and the M 21  circuit  64 , respectively, FIG. 18 shows the M 12  circuit  63 , and FIG. 19 shows the M 22  circuit  65 . 
     FIG. 20 is a diagram that shows the circuit configuration of the voltage-to-current conversion circuit in the fourth embodiment. The fourth embodiment is realized by using p channel MOSFETs in the basic configuration shown in FIG.  5 A. As shown schematically, the voltage-to-current conversion circuit in the fourth embodiment comprises MP 1  that corresponds to the first MOSFET, MP 2  that corresponds to the second MOSFET, a circuit  72  that generates a voltage VG+|2 VTP| from the fixed voltage VG and |2 VTP|, a circuit  73  that generates a voltage Vin−VDD+2|VTP|+VG, an M 1  drain bias circuit  74  that fixes the drain potential of M 1  to VG+2|VTP| and takes out its current IDP 1 , an M 2  drain bias circuit  75  that fixes the drain potential of M 2  to Vin−VDD+2|VTP|+VG and takes out its current ID 2 , and an M 2  source bias circuit  76  that applies the input voltage Vin to the source of M 2 . Circuits such as the difference current operation circuit are omitted. 
     As described above, according to the present invention, a voltage-to-current conversion circuit with Rail-to-Rail and an OTA can be realized with a simple configuration, in which variations in the transconductance parameters are small because the MOSFETs of the same polarity are used, and in which the transconductance can be set to an almost constant value.