Patent Publication Number: US-9847137-B2

Title: Method to reduce program disturbs in non-volatile memory cells

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 14/664,131 , filed Mar. 20, 2015 , now U.S. Pat. No. 9,431,124 , Issued Aug. 30, 2016 , which is a continuation of U.S. patent application Ser. No. 14/216,589 , filed Mar. 17, 2014 , Now U.S. Pat. No. 8,988,938 , Issued on Mar. 24, 2015 , which is a continuation of U.S. patent application Ser. No. 13/920,352 , filed Jun. 18, 2013 , now U.S. Pat. No. 8,675,405 , issued Mar. 18, 2014 , which claims the benefit of priority to U.S. Provisional Patent Application No. 61/778,136 , filed Mar. 12, 2013 , all of which are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates generally to memory devices, and more particularly to methods for reducing program disturbs in non-volatile memory cells. 
     BACKGROUND 
     Non-volatile memories are widely used for storing data in computer systems, and typically include a memory array with a large number of memory cells arranged in rows and columns. Each of the memory cells includes a non-volatile charge trapping gate field-effect transistor that is programmed or erased by applying a voltage of the proper polarity, magnitude and duration between a control gate and the substrate. A positive gate-to-substrate voltage causes electrons to tunnel from the channel to a charge-trapping dielectric layer raising a threshold voltage (V T ) of the transistor, and a negative gate-to-channel voltage causes holes to tunnel from the channel to the charge-trapping dielectric layer lowering the threshold voltage. 
     Non-volatile memories suffer from program or bitline disturbs, which is an unintended and detrimental change in memory cell V T  when another memory cell connected to the same bitline is inhibited from being programmed. Bitline disturb refers to disturb of the memory cells located in a row different from the row containing the cell undergoing programming. Bitline disturb occurring in the deselected row increases as the number of erase/program cycles in rows selected in the common well increases. The magnitude of bitline disturb also increases at higher temperatures, and, since memory cell dimensions scale down faster than applied voltages at advanced technology nodes, bitline disturb also becomes worse as the density of non-volatile memories increase. 
     It is, therefore, an object of the present invention to provide improved non-volatile memories and methods of programming the same. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be understood more fully from the detailed description that follows and from the accompanying drawings and the appended claims provided below, where: 
         FIG. 1  is a block diagram illustrating a cross-sectional side view of a non-volatile memory transistor or device; 
         FIG. 2  is a schematic diagram illustrating a two transistor (2T) memory cell for which an embodiment of the present disclosure is particularly useful; 
         FIG. 3  is a schematic diagram is a segment of a memory array illustrating an embodiment of a program operation according to the present disclosure; 
         FIG. 4  is a graph illustrating a positive high voltage (V POS ), a negative high voltage (V NEG ), and an intermediate, margin voltage (V MARG ) according to an embodiment of the present disclosure; 
         FIG. 5  is a graph illustrating voltages applied to a selected global wordline (V SELECTED WL ) and a deselected global wordline (V DESELECTED GWL ) during a program operation according to an embodiment of the present disclosure; 
         FIG. 6  is a block diagram illustrating a processing system including a memory device according to an embodiment of the present disclosure; 
         FIGS. 7A-7C  are block diagrams illustrating details of command and control circuitry of a non-volatile memory according to various embodiments of the present disclosure; and 
         FIG. 8  is a flowchart illustrating a method for reducing bitline disturbs in unselected memory cells according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Methods for reducing program disturbs in non-volatile memories are described herein. The method is particularly useful for operating memories made of memory arrays of bit cells or memory cells including non-volatile trapped-charge semiconductor devices that may be programmed or erased by applying a voltage of the proper polarity, magnitude and duration. 
     In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description. 
     Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term to couple as used herein may include both to directly electrically connect two or more components or elements and to indirectly connect through one or more intervening components. 
     The non-volatile memory may include memory cells with a non-volatile memory transistor or device implemented using Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or floating gate technology. 
     In one embodiment, illustrated in  FIG. 1 , the non-volatile memory transistor or device is a SONOS-type non-volatile memory device. Referring to  FIG. 1 , a SONOS device  100  includes a gate stack  102  formed over a substrate  104 . The SONOS device  100  further includes source/drain regions  106  formed in a well  108  in the substrate  104  on either side of gate stack  102 , which define a channel region  110  underneath gate stack. Gate stack  102  includes an oxide tunnel dielectric layer  112 , a nitride or oxynitride charge-trapping layer  114 , a top, blocking oxide layer  116  and a poly-silicon (poly) or metal layer which serves as a control gate  118 . 
     When the control gate  118  is appropriately biased, electrons from the source/drain regions  106  are injected or tunnel through tunnel dielectric layer  112  and are trapped in the charge-trapping layer  114 . The mechanisms by which charge is injected can include both Fowler-Nordheim (FN) tunneling and hot-carrier injection. The charge trapped in the charge-trapping layer  114  results in an energy barrier between the drain and the source, raising the threshold voltage V T  necessary to turn on the SONOS device  100  putting the device in a “programmed” state. The SONOS device  100  can be “erased” or the trapped charge removed and replaced with holes by applying an opposite bias on the control gate  118 . 
     In another embodiment, the non-volatile trapped-charge semiconductor device can be a floating-gate MOS field-effect transistor (FGMOS) or device. Generally, is similar in structure to the SONOS device  100  described above, differing primarily in that a FGMOS includes a poly-silicon (poly) floating gate, which is capacitively coupled to inputs of the device, rather than a nitride or oxynitride charge-trapping. Thus, the FGMOS device can be described with reference to  FIG. 1 . Referring to  FIG. 1 , a FGMOS device  100  includes a gate stack  102  formed over a substrate  104 . The FGMOS device  100  further includes source/drain regions  106  formed in a well  108  in the substrate  104  on either side of gate stack  102 , which define a channel region  110  underneath gate stack. Gate stack  102  includes a tunnel dielectric layer  112 , a floating gate layer  114 , a blocking oxide or top dielectric layer  116  and a poly-silicon or metal layer which serves as a control gate  118 . 
     Similarly to the SONOS device described above the FGMOS device  100  can be programmed by applying an appropriate bias between the control gate and the source and drain regions to inject charge in to the charge-trapping layer, raising the threshold voltage V T  necessary to turn on the FGMOS device. The FGMOS device can be erased or the trapped charge removed by applying an opposite bias on the control gate. 
     A memory array is constructed by fabricating a grid of memory cells arranged in rows and columns and connected by a number of horizontal and vertical control lines to peripheral circuitry such as address decoders and sense amplifiers. Each memory cell includes at least one non-volatile trapped-charge semiconductor device, such as those described above, and may have a one transistor (1T) or two transistor (2T) architecture. 
     In one embodiment, illustrated in  FIG. 2 , the memory cell  200  has a 2T-architecture and includes, in addition to a non-volatile memory transistor  202 , a pass or select transistor  204 , for example, a conventional IGFET sharing a common substrate connection  206  with the memory transistor  202 . Referring to  FIG. 2 , the memory transistor  202  has a charge trapping layer  208  and a drain  210  connected to a source  222  of the select transistor  204  and through the select transistor to a bitline  212 , a control gate  214  connected to a wordline  216  and a source  218  connected to a source line  224 . Select transistor  204  also includes a drain  220  connected to a bitline  212  and a gate  226  connected to a select or read line  228 . 
     During an erase operation to erase the memory cell  200  a negative high voltage (V NEG ) is applied to the wordline  216  and a positive high voltage (V POS ) applied to the bitline and the substrate connection  206 . Generally, the memory cell  200  is erased as part of a bulk erase operation in which all memory cells in a selected row of a memory array are erased at once prior to a program operation to program the memory cell  200  by applying the appropriate voltages to a global wordline (GWL) shared by all memory cells in the row, the substrate connection and to all bitlines in the memory array. 
     During the program operation the voltages applied to the wordline  216  and the bitline  212  are reversed, with V POS  applied to the wordline and V NEG  applied to the bitline, to apply a bias to program the memory transistor  202 . The substrate connection  206  or connection to the well in which the memory transistor  202  is formed is coupled to electrical ground, V NEG  or to a voltage between ground and V NEG . The read or select line  228  is likewise coupled to electrical ground (0V), and the source line  224  may be at equipotential with the bitline  212 , i.e., coupled to V NEG , or allowed to float. 
     After an erase operation or program operation is completed, the state of the memory cell  200  can be read by setting a gate-to-source voltage (V GS ) of the memory transistor  202  to zero, applying a small voltage between the drain terminal  210  and source terminal  218 , and sensing a current that flows through the memory transistor. In the programmed state, an N-type SONOS memory transistor, for example, will be OFF because V GS  will be below the programmed threshold voltage V TP . In the erased state, the N-type memory transistor will be ON because the V GS  will be above an erased threshold voltage V. Conventionally, the ON state is associated with a logical “0” and the OFF state is associated with a logical “1.” 
     A memory array of memory cells and methods of operating the same to reduce disturbs will now be described with reference to  FIG. 3  and Table I below. In the following description, for clarity and ease of explanation, it is assumed that all of the transistors in memory array are N-type SONOS transistors. It should be appreciated, without loss of generality that a P-type configuration can be described by reversing the polarity of the applied voltages, and that such a configuration is within the contemplated embodiments of the invention. In addition, the voltages used in the following description are selected for ease of explanation and represent only one exemplary embodiment of the invention. Other voltages may be employed in different embodiments of the invention. 
       FIG. 3  illustrates an exemplary embodiment of a segment of a memory array  300 , which may be part of a large memory array of memory cells. In  FIG. 3 , memory array  300  includes four memory cells  301 ,  302 ,  303  and  304  arranged in two rows (ROW  1 , ROW  2 ) and two columns (COLUMN  1 , COLUMN  2 ). Each of the memory cells  301 - 304  may be structurally equivalent to memory cell  200  described above. 
     Referring to  FIG. 3 , memory cell  301  is the targeted cell to be programmed to a logic “1” state (i.e., programmed to an ON state) while memory cell  302 , already erased to a logic “0” state by a preceding erase operation, is maintained in a logic “0” or OFF state. These two objectives (programming cell  301  and inhibiting cell  302 ) are accomplished by applying a first or positive high voltage (V POS ) to a first global wordline (GWL 1 ) in the first row of the memory array  300 , a second or negative high voltage (V NEG ), is applied to a first bitline (BL 1 ) to bias transistor T 1  on programming the selected memory cell  301 , while an inhibit voltage (V Inhib ) is applied to a second bitline (BL 2 ) to bias transistor T 2  off on inhibiting programming of the deselected memory cell  302 , and a common or shared voltage is applied to the substrate nodes (SUB) of all memory cells  301 ,  302 ,  303  and  304 , and the read lines (RL 1  and RL 2 ) coupled to electrical ground (0V). The source lines (SL 1  and SL 2 ) may be at equipotential with the bitlines in their respective columns, i.e., SL 1  is coupled to V NEG  and SL 2  coupled to the V Inhib , or allowed to float. 
     In addition, and as described in greater detail below, a selected margin voltage (V MARG ) having a voltage level or magnitude less than V NEG  is applied to a second global wordline (GWL 2 ) in the second row of the memory array  300  to reduce or substantially eliminate program-state bitline disturb in the deselected memory cell  304  due to programming of the selected memory cell  301 . 
     Table I depicts exemplary bias voltages that may be used for programming a non-volatile memory having a 2T-architecture and including memory cells with N-type SONOS transistors. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                 TABLE I 
               
               
                   
               
               
                   
                   
                   
                   
                 Substrate 
                   
                   
                   
                   
               
               
                 GWL1 
                 BL1 
                 SL1 
                 RL1 
                 Node 
                 GWL2 
                 BL2 
                 SL2 
                 RL2 
               
               
                   
               
             
            
               
                 V POS  +4.7 V 
                 V NEG  −3.6 V 
                 Float/−3.6 V 
                 V GND  0.0 V 
                 V NEG  −3.6 V 
                 V Marg  −2.6 V 
                 V Inhib  +1.2 V 
                 Float/+1.2 V 
                 V GND  0.0 V 
               
               
                   
               
            
           
         
       
     
     Because the voltage applied to the second global wordline (GWL2) has a lower voltage level or magnitude that V NEG , which is conventionally applied to wordlines in deselected row or cells, the gate to drain voltage (V GD ) across transistor T 4  is 3.8V, as compared to a V GD  in conventionally operated memories of 4.8V, the amount of bitline disturb of the threshold V T  of T 4  is reduced significantly. In one embodiment of this invention it was observed to be reduced from about 60 mV to less than about 7 mV. 
     The margin voltage (V MARG ) can be generated using dedicated circuitry in the memory (not shown in this figure) used solely for generating V MARG , or can be generated using circuitry already included in the memory device. Generally, the margin voltage (V MARG ) has the same polarity as the second or V NEG  high voltage, but is higher or more positive than V NEG  by a voltage equal to at least the threshold voltage (V T ) of the transistor T 4  in the memory cell  304  for which program state bitline disturb is reduced. Optionally, the circuitry used to generate the margin voltage (V MARG ) is programmable to set a desired margin voltage (V MARG ) with steps, in one embodiment, of 14 mV or less. 
     In one embodiment, the circuitry used to generate the margin voltage (V MARG ) includes a digital-to-analog-converter (DAC) enabled by command and control circuitry in the memory programmed to generate a margin voltage (V MARG ) of a desired magnitude or voltage level to be coupled to the GWLs of deselected row(s) during the program operation. In one particular advantageous embodiment the DAC is a margin mode DAC in the memory, which is used during initialization of the memory to adjust voltages therein, and which is not normally enabled during the program operation. Significant advantages of this embodiment include that V MARG  can be trimmed using the (MDAC) bits, it does not represent a large load on a negative pump for V NEG  and an output buffer of the margin mode DAC offers a low impedance driver for the V MARG  signal. Adapting such a margin mode DAC for generating V MARG  during the program operation requires forming an electrical connection to the GWLs of deselected rows of the memory array  300  during the program operation, and enabling the margin mode DAC through a DAC enable signal. 
     In certain embodiments, further adaption of the V MARG  circuit is desirable to overcome the fact that V MARG  was not originally designed to drive large capacitive loads active during program. One method of overcoming this limitation will now be described with reference to the graphs of  FIGS. 4 and 5 . 
       FIG. 4  is a graph illustrating a positive first high voltage (V POS    402 ), a negative second high voltage (V NEG    404 ), and an intermediate, margin voltage (V MARG    406 ) according to an embodiment of the present disclosure. Referring to  FIG. 4  it is noted that the start-up time for the circuit generating the margin voltage (V MARG    406 ) can be relatively slow, up to 80-110 μs, as compared to the second high voltage (V NEG    404 ). During this time the voltage difference between a deselected global wordline (GWL 2 ) to which the margin voltage (V MARG    406 ) is applied and the p-well (SPW) or substrate node to which second high voltage (V NEG    404 ), can reach 1.6-1.7 volts for 20-40 μs. Thus, to reduce erase-state bitline disturb in an unselected memory cell in the first column and second row of the memory array (e.g., cell T 3 ), V NEG  is coupled to the second global wordline (GWL 2 ) in the deselected row for up to about 40 μs until a capacitance associated with the deselected wordline(s) is sufficiently pre-charged, and V NEG  has reached a value close to −2.0 volts. The margin voltage is then coupled to the global wordline (GWL 2 ) in the deselected row for the remainder of the program operation to reduce program-state bitline disturb in a second unselected memory cell in the second column and second row of the memory array due to programming of the selected memory cell. 
     A graph illustrating voltages applied to a selected global wordline (V SELECTED WL    502 ) and a deselected global wordline (V DESELECTED GWL    504 ) during a program operation according to an embodiment of the present disclosure is shown in  FIG. 5 . Referring to  FIG. 5  it is noted from the graph of the deselected global wordline voltage (V DESELECTED GWL    504 ) that at about 15 μs, indicated by reference numeral  506  on the graph of the deselected global wordline voltage, the global wordline (GWL 2 ) in the deselected row is switched from being coupled to second high voltage (V NEG    404 ), to being coupled to the margin voltage (V MARG    406 ) for the remainder of the program operation. 
     A processing system  600  to reduce bitline program disturbs according to an embodiment of the present disclosure will now be described with reference to  FIG. 6 . 
     Referring to  FIG. 6  the processing system  600  generally includes a non-volatile memory  602  coupled to a processor  604  in a conventional manner via an address bus  606 , a data bus  608  and a control bus  610 . It will be appreciated by those skilled in the art that the processing system of  FIG. 6  has been simplified for the purpose of illustrating the present invention and is not intended to be a complete description. In particular, details of the processor, row and column decoders, sense amplifiers and command and control circuitry, which are known in the art have are not described in detail herein. 
     The processor  604  may be a type of general purpose or special purpose processing device. For example, in one embodiment the processor can be a processor in a programmable system or controller that further includes a non-volatile memory, such as a Programmable System On a Chip or PSoC™ controller, commercially available from Cypress Semiconductor of San Jose, Calif. 
     The non-volatile memory  602  includes a memory array  612  organized as rows and columns of non-volatile memory cells (not shown in this figure) as described above. The memory array  612  is coupled to a row decoder  614  via multiple wordlines and read lines  616  (at least one wordline and one read line for each row of the memory array) as described above. The memory array  612  is further coupled to a column decoder  618  via a multiple bitlines and source lines  620  (one each for each column of the memory array) as described above. The memory array  612  is coupled to a plurality of sense amplifiers  622  to read multi-bit words therefrom. The non-volatile memory  602  further includes command and control circuitry  624  to control the row decoder  614 , the column decoder  618  and sense amplifiers  622 , and to receive read data from sense amplifiers. The command and control circuitry  624  includes voltage control circuitry  626  to generate the voltages needed for operation of the non-volatile memory  602 , including V POS , V NEG  and V INHIB , and a margin mode DAC  628  to generate V MARG  described above, which is routed through the voltage control circuitry to the row decoder  614 . The voltage control circuitry  626  operates to apply appropriate voltages to the memory cells during read, erase and program operations. 
     The command and control circuitry  624  is configured to control the row decoder  614  to select a first row of the memory array  612  for a program operation by applying a V POS  to a first global wordline (GWL 1 ) in the first row and to deselect a second row of the memory array by applying a margin voltage to a second global wordline (GWL 2 ) in the second row. In some embodiments, the command and control circuitry  624  is configured to sequentially couple first V NEG  to the second global wordline for a brief period of time and then the margin voltage. As described above, in some embodiments, the start-up time for a margin voltage circuit can be relatively slow as compared to that of V NEG  coupled to a substrate node or p-well (SPW) in which the memory transistor is formed, and during this time the voltage bias difference between the deselected wordline (GWL 2 ) and a p-well (SPW) or substrate node can cause erase-state bitline disturb in an unselected memory cell in the first column and second row of the memory array (e.g., cell T 3 ). Thus, to reduce erase-state bitline disturb in the unselected memory cell in the first column and second row of the memory array (e.g., cell T 3 ), V NEG  is coupled to the second global wordline (GWL 2 ) in the deselected row for a brief time until a capacitance associated with the deselected wordline(s) is sufficiently pre-charged, and V NEG  has reached a value close to −2.0 volts. The margin voltage is then coupled to the global wordline (GWL 2 ) in the deselected row for the remainder of the program operation to reduce program-state bitline disturb in a second unselected memory cell in the second column and second row of the memory array due to programming of the selected memory cell. 
     The command and control circuitry  624  is further configured to control the column decoder  618  to select a memory cell in the first row (e.g., cell T 1 ) for programming by applying a V NEG  to a first shared bitline (BL 1 ) in a first column, and to inhibit a unselected memory cell in the first row (e.g., cell T 2 ) from programming by applying an inhibit voltage to a second shared bitline (BL 2 ) in a second column. The column decoder  618  may be further configured to apply V NEG  to a first shared source line (SL 1 ) in the first column, and to apply the inhibit voltage on a second shared source line (SL 2 ) in the second column. 
     Details of the command and control circuitry of a memory device according to various embodiments of the present disclosure will now be described with reference to  FIGS. 7A-7C . 
     Referring to  FIG. 7A , in one embodiment the command and control circuitry  700  includes a negative HV supply or pump  702  to generate a V NEG  coupled to the bitline and source line of the selected cell, and to the substrate nodes during the program operation, a digital-to-analog-converter (DAC  704 ) enabled by the command and control circuitry to generate a margin voltage to be coupled to the GWLs of deselected rows during the program operation, and a switching circuit  706  to switch between V NEG  and the margin voltage coupled to the deselected GWLs during the program operation. The DAC  704  can be a dedicated DAC used solely for generating V MARG , or a DAC already included in the command and control circuitry  700  or voltage control circuitry  626  for other purposes, and which is normally not utilized during a program operation. As noted above, in one particular advantageous embodiment the DAC is a margin mode DAC  628  in the command and control circuitry  624  of the non-volatile memory  602 , which is used during test to measure the threshold voltages of the non-volatile devices therein, and which is not normally enabled during the program operation. It will be appreciated that adapting such a margin mode DAC for generating V MARG  during the program operation requires forming an electrical connection to the switching circuit  706 , and through the switching circuit and the row decoder (not shown in this figure) to the GWLs of deselected rows of the memory array during the program operation. The command and control circuitry  624  of the non-volatile memory  602  enables the DAC  704  through a DAC enable signal, and, optionally, operates the DAC to provide a programmed margin voltage level or magnitude. Generally, the DAC  704  is operated to provide a margin voltage having a magnitude less than the voltage magnitude of V NEG , i.e., higher or more positive than V NEG  in the N-type SONOS embodiment described above, by a voltage equal to at least the threshold voltage (V T ) of the of the memory transistor in the memory cell. In other embodiments, the DAC  704  may be programmed or operated to provide a margin voltage magnitude less than V NEG  by an amount close to the V T  of the memory transistor. For example, in one embodiment described above the DAC  704  may be programmed or operated to provide a margin voltage adjustable to within one or more small steps of about 14 mV each. 
     In another embodiment, shown in  FIG. 7B , the command and control circuitry  700  includes a second charge pump  708  to generate the margin voltage to be coupled to the GWLs of deselected rows during the program operation. By selecting the second charge pump  708  to have a start-up time and power to charge the capacitance associated with the deselected wordline(s) that are substantially the same as the negative pump  702 , the GWLs of the deselected rows can be coupled to the margin voltage throughout the program operation, and thus the need for a separate switching circuit  706  is eliminated. 
     In yet another embodiment, shown in  FIG. 7C , the command and control circuitry  700  includes a voltage divider  710  coupled to an output of negative pump  702  to generate the margin voltage to be coupled to the GWLs of deselected rows during the program operation. Because V NEG  and V MARG  are both supplied by the negative pump  702  there is substantially no difference in start-up time between V NEG  and V MARG , and the voltage bias difference between V MARG  applied the deselected wordline (GWL 2 ) and V NEG  applied to the p-well (SPW) or substrate node cannot reach a voltage level sufficient to cause erase-state bitline disturb in the unselected memory cell in the first column and second row of the memory array (e.g., 1.6-1.7 volts for 20-40 μs), the GWLs of the deselected rows can be coupled to the margin voltage throughout the program operation, and thus the need for a separate switching circuit  706  is eliminated. 
       FIG. 8  is a flowchart illustrating a method for reducing program disturb in one embodiment. Note, it will be understood that although all steps of the method are described individually below implying a sequential order that is not necessarily the case, and that as shown in  FIG. 8 , a first five individual steps of the method are performed at substantially the same time, while a last two steps are performed in order after only a slight delay. 
     Referring to  FIG. 8 , a first positive high voltage (V POS ) is coupled to a first global wordline in a first row of a memory array of memory cells ( 802 ). In the next operation, a V NEG  is coupled to a first shared bitline in a first column of the memory array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell ( 804 ). In embodiments in which the memory transistors are formed in wells in a substrate, the wells may be coupled to electrical ground, a voltage between ground and V NEG , or, as in the embodiment shown to V NEG  ( 806 ). Optionally, V NEG  may be coupled to a second global wordline in a second row of the memory array for a brief period of time to apply a bias to a non-volatile memory transistor in a first unselected memory cell in the first column and the second row of the memory array sharing the first shared bitline with the selected memory cell to reduce erase-state bitline disturb in the first unselected memory cell ( 808 ). Simultaneously, a margin voltage less than V NEG  is generated ( 810 ). In the next operation, after only a slight delay the margin voltage is coupled to the second global wordline in the second row of the memory array ( 812 ). In the next operation, an inhibit voltage is coupled to a second shared bitline in a second column of the memory array to apply a bias to a non-volatile memory transistor in a second unselected memory cell in the second row and second column to reduce program-state bitline disturb in the second unselected memory cell ( 814 ). 
     Thus, embodiments of a non-volatile memory and methods of operating the same to reduce disturbs have been described. Although the present disclosure has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. 
     The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. 
     Reference in the description to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the circuit or method. The appearances of the phrase one embodiment in various places in the specification do not necessarily all refer to the same embodiment.