Patent Publication Number: US-7915726-B2

Title: Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 11/217,152, filed Aug. 31, 2005, now U.S. Pat. No. 7,326,591 which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The following disclosure relates generally to interconnecting substrates for microelectronic dies and, more particularly, to methods for coupling microelectronic dies to interconnecting substrates having conductive traces on two sides. 
     BACKGROUND 
     Conventional die-level packaged microelectronic devices typically include a microelectronic die, an interposer substrate or lead frame attached to the die, and a moulded casing around the die. The die generally includes an integrated circuit coupled to a plurality of bond-pads. The bond-pads are typically coupled to contacts on the interposer substrate or lead frame, and serve as external electrical contacts through which supply voltage, signals, etc., are transmitted to and from the integrated circuit. In addition to contacts, interposer substrates can also include ball-pads coupled to the contacts by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages that have lower profiles and higher pin counts than conventional packages using lead frames. 
     One process for making a packaged microelectronic device with a ball-grid array includes (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to separate or singulate the dies, (c) attaching individual dies to an interposer substrate, (d) wire-bonding bond-pads on the dies to contacts on the interposer substrate, and (e) encapsulating the dies with a suitable moulding compound. Packaged microelectronic devices made in the foregoing manner are often used in cellphones, pagers, personal digital assistants, computers, and other electronic products. As the demand for these products grows, there is a continuing drive to increase the performance of packaged microelectronic devices while at the same time reducing the height and surface area or “footprint” of such devices on printed circuit boards. Reducing the size of microelectronic devices, however, becomes more difficult as the performance increases because higher performance typically requires more integrated circuitry and bond-pads. In addition, increasing circuit density can lead to noise during high-speed signal transmission. 
       FIG. 1  is a schematic cross-sectional view of a packaged microelectronic device  100  configured in accordance with the prior art. The packaged microelectronic device  100  includes a die  130  bonded to an interposer substrate  120  in a conventional “board on chip” arrangement. The interposer substrate  120  includes a sheet of non-conductive material  123  (e.g., BT resin, FR4, etc.) having a first side  121 , an opposing second side  122 , and a slot  125  extending therethrough. Conductive traces  126  (identified individually as a first conductive trace  126   a  and a second conductive trace  126   b ) are formed on the first side  121  of the non-conductive material  123  on opposite sides of the slot  125 . Each of the conductive traces  126  extends between a contact  127  and a corresponding ball-pad  128 . Solder balls  129  can be deposited on the ball-pads  128  to form part of a ball-grid array. 
     The die  130  includes an integrated circuit  132  electrically coupled to a series of bond-pads  134  (only one of the bond-pads  134  is shown in  FIG. 1 ). The integrated circuit  132  is electrically coupled to the ball-grid array by individual wire-bonds  136  that extend from the bond-pads  134  to the contacts  127 . After the wire-bonds  136  have been attached, the die  130  and the adjacent portion of the substrate  120  can be encased in a suitable mold compound  140 . 
     As the speed of the packaged microelectronic device  100  increases and the size becomes smaller, the first side  121  of the non-conductive material  123  becomes very congested with conductive traces. The congestion limits the ability to match input and output trace lengths to reduce signal transmission problems. In addition, the close proximity of signal traces to ground and power planes or ground and power traces can cause signal noise due to a phenomenon known as ground/power bounce. 
       FIG. 2  is a schematic cross-sectional view of a packaged microelectronic device  200  having conductive traces  226  on both sides of a substrate  220 . Specifically, the substrate  220  includes a first conductive trace  226   a  on a first side  221  of a non-conductive material  223 , and a second conductive trace  226   b  on a second side  222  of the non-conductive material  223 . A portion of a plated via  250  extends through the non-conductive material  223  to electrically couple the second conductive trace  226   b  to a contact  227  on the first side  221 . 
     Although moving the second conductive trace  226   b  to the second side  222  of the substrate  220  does reduce the trace count on the first side  221 , the plated via  250  still adds to the congestion on the first side  221  and can cause trace routing constraints. A further shortcoming of this configuration is that the plated via  250  increases the length of the inductance loop when the second conductive trace  226   b  is used for power or ground purposes. Increasing the length of the inductance loop can cause additional noise during signal transmission. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic cross-sectional view of a packaged microelectronic device configured in accordance with the prior art. 
         FIG. 2  is a schematic cross-sectional view of another packaged microelectronic device configured in accordance with the prior art. 
         FIGS. 3A-3F  are a series of schematic views illustrating various stages in a method of manufacturing an interconnecting substrate for use with a microelectronic die in accordance with an embodiment of the invention. 
         FIG. 4  is a schematic cross-sectional view of a packaged microelectronic device configured in accordance with an embodiment of the invention. 
         FIG. 5  is a schematic top view of an interconnecting substrate configured in accordance with another embodiment of the invention. 
         FIG. 6  is a schematic cross-sectional view of a packaged microelectronic device configured in accordance with a further embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     A. Overview 
     The following disclosure describes several embodiments of packaged microelectronic devices, interconnecting substrates for packaged microelectronic devices, and methods for forming vias in interconnecting substrates. One aspect of the invention is directed toward a method of manufacturing a substrate for attachment to a microelectronic device. The method includes forming a conductive trace on a first side of a non-conductive material, and forming a hole through a second side of the non-conductive material to the conductive trace. The hole is formed so that at least a portion of the conductive trace covers the hole on the first side of the non-conductive material. The method can further include forming an edge of the non-conductive material that crosses through at least a portion of the hole. In one embodiment, forming an edge of the non-conductive material can include removing a section of the non-conductive material to form a slot through the non-conductive material. 
     Another aspect of the invention is directed to a method of manufacturing a microelectronic device having a die with a plurality of terminals electrically coupled to an integrated circuit. The method includes attaching the die to a substrate that has a first conductive trace on a first side of a non-conductive material and a second conductive trace on a second side of the non-conductive material. The method further includes electrically coupling a first terminal on the die to the first conductive trace on the first side of the non-conductive material, and electrically coupling a second terminal on the die to the second conductive trace on the second side of the non-conductive material. In one embodiment, electrically coupling the first terminal to the first conductive trace can include attaching a first wire-bond from the first terminal to the first conductive trace. Similarly, electrically coupling the second terminal to the second conductive trace can include attaching a second wire-bond from the second terminal to the second conductive trace. 
     A further aspect of the invention is directed toward a substrate for attachment to a microelectronic device. The substrate includes a sheet of non-conductive material having a first conductive trace on a first side and a second conductive trace on a second side opposite to the first side. The first conductive trace has a first surface facing away from the non-conductive material and a second surface facing toward the non-conductive material. Similarly, the second conductive trace has a third surface facing away from the non-conductive material and a fourth surface facing toward the non-conductive material. The substrate further includes a first electrical contact area on the first surface of the first conductive trace and a second electrical contact area on the fourth surface of the second conductive trace. In one embodiment, the first contact area can include a first area of exposed metal plating suitable for attachment to a first wire-bond, and the second contact area can include a second area of exposed metal plating suitable for attachment to a second wire-bond. 
     Specific details of several embodiments of the invention are described below with reference to  FIGS. 3A-6  to provide a thorough understanding of such embodiments. Other details describing well-known structures often associated with microelectronic devices and microelectronic device mounting substrates are not set forth in the following description to avoid unnecessarily obscuring the description of the various embodiments. Persons of ordinary skill in the art will understand, however, that the invention may have other embodiments with additional elements or without several of the elements shown or described below with reference to  FIGS. 3A-6 . 
     B. Embodiments of Methods for Manufacturing Interconnecting Substrates for Microelectronic Dies 
       FIGS. 3A-3F  are a series of schematic views illustrating various stages in a method of manufacturing an interconnecting substrate  320  (“substrate  320 ”) in accordance with an embodiment of the invention. More specifically,  FIGS. 3A ,  3 B,  3 D and  3 F are schematic top views, while  FIGS. 3C and 3E  are schematic cross-sectional views. Referring first to  FIG. 3A , the substrate  320  includes a sheet of non-conductive material  323  (e.g., BT resin, FR4, etc.) having a first side  321  and an opposite second side  322 . In the illustrated embodiment, a first plurality of conductive lines or traces  326  (e.g., copper traces; identified individually as a first conductive trace  326   a , a second conductive trace  326   b , and a third conductive trace  326   c ) are formed on the first side  321  using suitable plating, patterning, and etching processes known in the art. A second plurality of conductive traces  326  (identified individually as a fourth conductive trace  326   d , a fifth conductive trace  326   e , and a sixth conductive trace  326   f ) are formed on the second side  322  in a similar manner. In the illustrated embodiment, portions of the second plurality of conductive traces  326   d - f  are positioned in vertical alignment with corresponding portions of the first plurality of conductive traces  326   a - c . Aligning the conductive traces  326  in this manner can facilitate alignment of the drill, laser, or other boring device used to form the vias described in detail below with reference to  FIGS. 3B and 3C . In other embodiments, however, the conductive traces  326   d - f  on the second side  322  can be positioned independently of the conductive traces  326   a - c  on the first side  321 . 
     As described in greater detail below, in one embodiment, the first plurality of conductive traces  326   a - c  can be used for signal transmission and the second plurality of conductive traces  326   d - f  can be used for grounding and/or power transmission. Separating the ground/power traces from the signal traces in this manner can favorably reduce signal noise caused by ground/power bounce and inductance loop effects. After forming, both sides of the non-conductive material  323  can be covered with a dielectric layer  342  (e.g., a solder mask) to protect the conductive traces  326 . The dielectric layer  342  can be removed in a region  344 , however, to facilitate the process steps that follow. 
     Referring next to  FIG. 3B , a plurality of holes or vias  360  (identified individually as a first via  360   a , a second via  360   b , and a third via  360   c ) are formed in the substrate  320  so that they extend from the first side  321  of the non-conductive material  323  to the conductive traces  326   d - f  on the second side  322  of the non-conductive material  323 . A cross-sectional view of this via configuration is shown in  FIG. 3C , which is taken along line  3 C- 3 C in  FIG. 3B . As shown in  FIG. 3C , the first via  360   a  extends through the non-conductive material  323 , but stops at the fourth conductive trace  326   d  on the second side  322 . The vias  360  illustrated in  FIGS. 3B and 3C  can be formed by any suitable method known in the art including, for example, drilling, etching, laser boring, etc. 
     Referring next to  FIG. 3D , each of the vias  360  can be at least partially filled With plug material  362  after forming. In this embodiment, a wide variety of materials known in the art can be used as the plug material  362  including, for example, epoxy resins, solder mask material, and/or other suitable materials that can be used to temporarily fill and/or stabilize the vias  360  during subsequent processing steps. After the vias  360  have been plugged, a slot  370  is formed through the non-conductive material  323  using any suitable method known in the art including routing, punching, cutting, etc. The slot  370  extends from a first edge portion  371  to a second edge portion  372 . The first edge portion  371  is positioned so that it crosses at least a portion of the first via  360   a  and the third via  360   c . Similarly, the second edge portion  372  is positioned so that it crosses at least a portion of the second via  360   b.    
       FIG. 3E  is an enlarged cross-sectional view taken along line  3 E- 3 E in  FIG. 3D , and shows how the plug material  362  is carried by the remaining portion of the via  360   a  after the slot  370  has been formed in the substrate  320 . After the slot  370  has been formed, the plug materials  362  can be removed from each of the vias  360  by etching, laser ablation, drilling, or other suitable method known in the art. Removing the plug material  362  from each via  360  forms a corresponding alcove along the respective edge of the slot  370  in which a portion of each of the conductive traces  326   d - f  is exposed, as shown in  FIG. 3F . Next, contact areas  327   a - c  (e.g., wire-bond attach areas) on the conductive traces  326   a - c , and contact areas  327   d - f  on conductive traces  326   d - f , can be prepared for wire-bond attachment in a subsequent packaging step. In those embodiments in which the conductive traces  326  include copper, preparing the contact areas  327  can include plating the specified areas with nickel (Ni) and then gold (Au) using suitable methods known in the art. In other embodiments, other methods and/or materials can be used to facilitate wire-bond attachment to the conductive traces  326 . 
     C. Embodiments of Packaged Microelectronic Devices 
       FIG. 4  is a schematic cross-sectional view of a packaged microelectronic device  400  configured in accordance with an embodiment of the invention. In the illustrated embodiment, the packaged microelectronic device  400  (e.g., a memory module, processing device, etc.) includes a die  430  attached to a substrate  320  manufactured as described above with reference to  FIGS. 3A-3F . For ease of reference, the section view of the substrate  320  shown in  FIG. 4  is taken along line  4 - 4  in  FIG. 3F . As shown in  FIG. 4 , the third conductive trace  326   c  has a first surface  461   a  facing away from the non-conductive material  323  and a second surface  462   a  facing toward the non-conductive material  323 . The third contact area  327   c  is formed on the first surface  461   a  of the third conductive trace  326   c . The sixth conductive trace  326   f  has a first surface  461   b  facing away from the non-conductive material  323  and a second surface  462   b  facing toward the non-conductive material  323 . The sixth contact area  327   f  is formed on the second surface  462   b  of the sixth conductive trace  326   f.    
     In another aspect of this embodiment, the microelectronic die  430  is a memory device, a processor, or other type of component that includes an integrated circuit  432  electrically coupled to a series of terminals  434  (e.g., bond-pads). (Only one of the terminals  434  is shown in  FIG. 4  because of the perspective of the view.) Each of the terminals  434  can be electrically coupled to one of the conductive traces  326  by a corresponding wire-bond  436 . For example, a first one of the terminals  434  can be electrically coupled to the sixth conductive trace  326   f  by a first wire-bond  436   a  that extends from the terminal to the sixth contact area  327   f . Similarly, a second one of the terminals  434  can be electrically coupled to the third conductive trace  326   c  by a second wire-bond  436   b  that extends from the terminal to the third contact area  327   c . The other conductive traces (e.g., the conductive traces  326   a, b, d  and  e ) can be attached to individual terminals  434  with additional wire-bonds in a similar manner. After all of the terminals  434  have been electrically coupled to corresponding traces  326 , the microelectronic die  430  and the portion of the substrate  320  around the wire-bonds  436  can be encased in a suitable mold compound  440 . 
     One feature of the embodiment illustrated in  FIG. 4  is that the conductive traces  326   a - c  on the first side  321  of the non-conductive material  323  can be used for signal transmission, while the conductive traces  326   d - f  on the second side  322  can be used for power and/or ground connections. Separating the trace planes in the foregoing manner can reduce noise and/or other problems that arise during signal transmission. In addition, placing the power and/or ground circuits on the second side  322  of the non-conductive material  323  can reduce the inductance loop, thereby reducing the potential for noise caused by ground/power bounce. 
     D. Other Embodiments of Interconnecting Substrates and Packaged Microelectronic Devices 
       FIG. 5  is a schematic top view of an interconnecting substrate  520  configured in accordance with another embodiment of the invention. Many features of the substrate  520  are at least generally similar in structure and function to corresponding features of the interconnecting substrate  320  described above with reference to  FIGS. 3A-3F . For example, the substrate  520  includes a first conductive trace  526   a  and a second conductive trace  526   b  formed on a first side  521  of a sheet of non-conductive material  523 , and a third conductive trace  526   c  and a fourth conductive trace  526   d  formed on a second side  522  of the sheet of non-conductive material  523 . In this particular embodiment, however, the first and second conductive traces  526   a,b  are at least approximately aligned with the third and fourth conductive traces  526   c,d , respectively. Each of the conductive traces  526  includes a corresponding contact area  527  (e.g., wire-bond attach areas). As explained above, in those embodiments in which the conductive traces  526  include copper, the contact areas  527  can include nickel (Ni) plating followed by gold (Au) plating. In other embodiments, other methods and/or materials can be used to facilitate wire-bond attachment to the conductive traces  526 . 
       FIG. 6  is a schematic cross-sectional view of a packaged microelectronic device  600  configured in accordance with a further embodiment of the invention. In the illustrated embodiment, the packaged microelectronic device  600  includes a die  630  attached to the interconnecting substrate  520  of  FIG. 5 . The section view of the substrate  520  shown in  FIG. 6  is taken along line  6 - 6  in  FIG. 5 . In one aspect of this embodiment, the microelectronic die  630  is a memory device, processor, imager, or other type of component that includes an integrated circuit  632  electrically coupled to a series of terminals  634  (e.g., bond-pads). (Only one of the terminals  634  is shown in  FIG. 6  because of the perspective of the view.) Each of the terminals  634  can be electrically coupled to one of the conductive traces  526  by a corresponding wire-bond  636 . For example, a first one of the terminals  634  can be electrically coupled to the first conductive trace  526   a  by a first wire-bond  636   a  that extends from the terminal to the first contact area  527   a . Similarly, a second one of the terminals  634  can be electrically coupled to the second conductive trace  526   b  by a second wire-bond  636   b  that extends from the terminal to the second contact area  527   b . The other conductive traces (e.g., the conductive traces  526   c,d ) can be attached to individual terminals  634  with additional wire-bonds in a similar manner. In other embodiments, one or both of the conductive traces  526   a  and/or  526   b  on the first surface  521  can be electrically coupled to one or both of the conductive traces  526   c  and/or  526   d  on the second surface  522 , respectively, by corresponding vias (not shown). After each of the terminals  634  has been electrically coupled to a corresponding trace  526 , the microelectronic die  630  and the portion of the substrate  520  around the wire-bonds  636  can be encased in a suitable mold compound  640 . 
     From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.