Patent Publication Number: US-2023141244-A1

Title: Semiconductor structure

Description:
TECHNICAL FIELD 
     The present disclosure relates to the field of semiconductor technologies, and in particular to a semiconductor structure. 
     BACKGROUND 
     A Group III nitride semiconductor is the third generation of new semiconductor material after the first and second generation of semiconductor materials such as Si, GaAs, etc. The Group III nitride semiconductor have high saturation electron mobility, high breakdown voltage and wide forbidden band width. Because of these characteristics, a high electron mobility transistor (HEMT) device based on GaN have broad application prospects. 
     The existing group III nitride semiconductor HEMT devices have the phenomenon of “current collapse” when used as high-frequency devices or high-voltage high-power switching devices. That is, when the device is operated in direct current pulse mode or high frequency mode, the drain output current cannot keep up with the change of the gate control signal, and there will be a transient decrease in drain current and an increase in dynamic on-resistance, which seriously affects the application of the device. This phenomenon is ultimately caused by a polarization effect that not only brings a two-dimensional electron gas (2DEG) in the heterojunction interface channel, but also causes the formation of positively charged ionized donor with charge density substantially equal to the concentration of 2DEG on the upper surface of the potential barrier layer in the heterojunction. The principle is that when the HEMT device works in the cutoff state, the electric field strength of a side of the gate electrode biased toward the drain electrode reaches the maximum, and the electrons on the gate leap to the surface of the potential barrier layer under the action of the electric field force and migrate laterally between its surface donor energy levels toward the drain electrode, which neutralizes the ionized donors on the surface and depletes the electrons in the channel, to form a “virtual gate”. When the operating state of the HEMT device changes from cutoff to on, the electrons on the surface of the potential barrier layer migrating from the gate electrode will migrate back to the gate electrode at a slow rate. However, when the HEMT device is switched at a certain frequency, the electrons on the surface of the potential barrier layer cannot migrate back to the gate electrode in time, causing an increase in the on-state resistance, which may be several times higher than the static on-state resistance, i.e., current collapse. 
     In view of this, it is necessary to provide a new semiconductor structure to solve the above problem. 
     SUMMARY 
     An object of the present disclosure is to provide a semiconductor structure to solve the problem of current collapse. 
     To this end, the present disclosure provides a semiconductor structure including: a substrate and a heterojunction structure disposed on the substrate, where the heterojunction structure comprises a source region, a drain region, and a gate region disposed between the source region and the drain region, and the drain region is provided with a quantum well structure. 
     Optionally, the quantum well structure includes an N-type semiconductor layer, a first P-type semiconductor layer, and a quantum well layer disposed between the N-type semiconductor layer and the first P-type semiconductor layer. 
     Optionally, the first P-type semiconductor layer includes a hole passivation layer away from the quantum well layer. 
     Optionally, the heterojunction structure includes, from bottom to top, a channel layer and a potential barrier layer. 
     Optionally, the potential barrier layer acts as an N-type semiconductor layer in the quantum well structure. 
     Optionally, a material combination of the channel layer and the potential barrier layer includes: GaN and AlN, GaN and InN, GaN and InAlGaN, GaAs and AlGaAs, GaN and InAlN, or InN and InAlN. 
     Optionally, the gate region is provided with at least one of a dielectric layer or a second P-type semiconductor layer. 
     Optionally, the quantum well layer is a single quantum well layer or a multiple quantum well layer. 
     Optionally, a material of the first P-type semiconductor layer includes at least one of GaN, AlGaN, InGaN, or AlInGaN. 
     Optionally, the source region is provided with a source electrode, the quantum well structure is provided with a first drain electrode, and the gate region is provided with a gate electrode; the source electrode is in ohmic contact with the heterojunction structure, and the first drain electrode is in ohmic contact with the quantum well structure, and the gate electrode is in Schottky contact with the heterojunction structure. 
     Optionally, the drain region is further provided with a second drain electrode, and the second drain electrode is in ohmic contact with the heterojunction structure. 
     Optionally, the first drain electrode and the quantum well structure are electrically insulated from the second drain electrode by an insulating layer. 
     Optionally, the first drain electrode is disposed between the gate electrode and the second drain electrode. 
     Optionally, the second drain electrode is disposed between the gate electrode and the first drain electrode. 
     Compared to the related art, the present disclosure has the beneficial effect of the following aspects. 
     1) The quantum well structure is provided in the drain region of the heterojunction structure, and the quantum well structure is used to generate photons by recombination luminescence, the photons can be radiated not only on the surface region of the potential barrier layer but also into the interior of the heterojunction structure, thereby the release process of electrons captured by the defects can be accelerated to reduce the current collapse effect as well as the dynamic on-resistance. 
     2) In optional embodiments, a) the quantum well structure includes an N-type semiconductor layer, a first P-type semiconductor layer, and a quantum well layer between the N-type semiconductor layer and the first P-type semiconductor layer; or b) the potential barrier layer in the heterojunction structure acts as the N-type semiconductor layer in the quantum well structure. Relative to the embodiments a) and b), the semiconductor structure can be simplified. 
     3) In optional embodiments, the first P-type semiconductor layer includes a hole passivation layer away from the quantum well layer. The hole passivation layer prevents electrons in the gate electrode from migrating to the first P-type semiconductor layer and from recombining with holes in the first P-type semiconductor layer. In other words, the hole passivation layer can create a high resistance blocking state between the gate electrode and the drain electrode. The hole passivation layer can be achieved by injecting H ions into the first P-type semiconductor layer. The H ions can passivate the P-type doping ion Mg of the first P-type semiconductor layer so that Mg does not generate holes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a cross-sectional view illustrating a semiconductor structure according to a first embodiment of the present disclosure. 
         FIG.  2    is a cross-sectional view illustrating a semiconductor structure according to a second embodiment of the present disclosure. 
         FIG.  3    is a cross-sectional view illustrating a semiconductor structure according to a third embodiment of the present disclosure. 
         FIG.  4    is a cross-sectional view illustrating a semiconductor structure according to a fourth embodiment of the present disclosure. 
         FIG.  5    is a cross-sectional view illustrating a semiconductor structure according to a fifth embodiment of the present disclosure. 
         FIG.  6    is a cross-sectional view illustrating a semiconductor structure according to a sixth embodiment of the present disclosure. 
         FIG.  7    is a cross-sectional view illustrating a semiconductor structure according to a seventh embodiment of the present disclosure. 
     
    
    
     List of reference numerals: semiconductor structure  1 ,  2 ,  3 ,  4 ,  5 ,  6  and  7 ; substrate  10 ; heterojunction structure  11 ; source region  12   a ; drain region  12   b ; gate region  12   c ; channel layer  11   a ; potential barrier layer  11   b ; quantum well structure  13 ; N-type semiconductor layer  13   a ; first P-type semiconductor layer  13   b ; quantum well layer  13   c ; hole passivation layer  130 ; dielectric layer  14 ; second P-type semiconductor layer  15 ; source electrode  16   a ; first drain electrode  16   b ; gate electrode  16   c ; second drain electrode  16   d ; insulating layer  17 . 
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     In order to make the above-mentioned objects, features and advantages of the present disclosure more obvious and understandable, the specific embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings. 
       FIG.  1    is a cross-sectional view illustrating a semiconductor structure according to a first embodiment of the present disclosure. 
     Referring to  FIG.  1   , the semiconductor structure  1  includes: a substrate  10  and a heterojunction structure  11  disposed on the substrate  10 ; the heterojunction structure  11  includes a source region  12   a , a drain region  12   b , and a gate region  12   c  disposed between the source region  12   a  and the drain region  12   b , and the drain region  12   b  is provided with a quantum well structure  13 . 
     The substrate  10  may include a GaN-based material. the GaN-based material may include at least one of GaN, AlGaN, InGaN, or AlInGaN, and the present embodiment is not limited thereto. 
     The substrate  10  may also include: at least one of Al 2 O 3 , sapphire, silicon carbide, or silicon, and the GaN-based material thereon. 
     The heterojunction structure  11  may include, from the bottom to top, a channel layer  11   a  and a potential barrier layer  11   b . Specifically, a) one channel layer  11   a  and one potential barrier layer  11   b  may be provided; or b) multiple channel layers  11   a  and multiple potential barrier layers  11   b  may be provided, and the multiple channel layers  11   a  and the multiple potential barrier layers  11   b  are arranged alternately; or c) one channel layer  11   a  and two or more potential barrier layers  11   b  are provided, to meet different functional requirements. 
     A material combination of the channel layer  11   a  and the potential barrier layer  11   b  may includes: GaN and AlN, GaN and InN, GaN and InAlGaN, GaAs and AlGaAs, GaN and InAlN, or InN and InAlN. 
     A nucleation layer and a buffer layer (not shown in the figures) may also be provided between the heterojunction structure  11  and the substrate  10 . The material of the nucleation layer may include, for example, AlN, AlGaN, etc., and the material of the buffer layer may include at least one of AlN, GaN, AlGaN or AlInGaN. The nucleation layer can alleviate the problem of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layers, such as the channel layer  11   a  in the heterojunction structure  11  and the substrate  10 , and the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layers and improve the crystal quality. 
     Referring to  FIG.  1   , in this embodiment, the quantum well structure  13  includes an N-type semiconductor layer  13   a , a first P-type semiconductor layer  13   b , and a quantum well layer  13   c  disposed between the N-type semiconductor layer  13   a  and the first P-type semiconductor layer  13   b . 
     The N-type semiconductor layer  13   a  is used to provide electrons and the first P-type semiconductor layer  13   b  is used to provide holes to achieve recombination luminescence of the electrons and the holes in the quantum well layer  13   c . The N-type semiconductor layer  13   a  and/or the first P-type semiconductor layer  13   b  may include a GaN-based material. The GaN-based material may include at least one of GaN, AlGaN, InGaN or AlInGaN. An N-type doping element in the N-type semiconductor layer  13   a  may be Mg, and a P-type doping element in the first P-type semiconductor layer  13   b  may be Si. 
     In the embodiment shown in  FIG.  1   , the N-type semiconductor layer  13   a  is close to the heterojunction structure  11  and the first P-type semiconductor layer  13   b  is away from the heterojunction structure  11 , or in other embodiments, the first P-type semiconductor layer  13   b  may be close to the heterojunction structure  11  and the N-type semiconductor layer  13   a  is away from the heterojunction structure  11 . 
     The quantum well layer  13   c  may be a single quantum well layer or a multiple quantum well layer. 
     In the semiconductor structure  1 , the drain region  12   b  of the heterojunction structure  11  is provided with the quantum well structure  13 , and the quantum well structure  13  is used to generate photons by recombination luminescence, and the photons can accelerate the release process of electrons captured by defects, to reduce the current collapse effect as well as the dynamic on-resistance. In addition, the photons can be radiated not only on the surface region of the potential barrier layer  11   b  but also into the interior of the heterojunction structure  11 . In other words, not only the release process of electrons in the surface region of the potential barrier layer can be accelerated, but also the release process of electrons inside the heterojunction structure can be accelerated, such that the current collapse effect and the dynamic on-resistance are reduced. 
     The semiconductor structure  1  can be produced and sold as a semi-finished product of a semiconductor device. 
       FIG.  2    is a cross-sectional view illustrating a semiconductor structure according to a second embodiment of the present disclosure. 
     Referring to  FIG.  2   , the semiconductor structure  2  of the second embodiment is substantially the same as the semiconductor structure  1  of the first embodiment, the difference is only in that the potential barrier layer  11   b  is an N-type semiconductor layer to serve as an N-type semiconductor layer  13   a  in the quantum well structure  13 . In other words, there is no need to additionally configure the N-type semiconductor layer  13   a  in the quantum well structure  13 . 
     In the second embodiment, the channel layer  11   a  may be an intrinsic semiconductor layer. 
       FIG.  3    is a cross-sectional view illustrating a semiconductor structure according to a third embodiment of the present disclosure. 
     Referring to  FIG.  3   , the semiconductor structure  3  of the third embodiment is substantially the same as the semiconductor structures  1  and  2  of the first and second embodiments, the difference is only in that the first P-type semiconductor layer  13   b  includes a hole passivation layer  130  away from the quantum well layer  13   c . 
     The hole passivation layer  130  prevents the electrons in the gate electrode  16   c  (shown with reference to  FIG.  6   ) from recombining with the holes in the first P-type semiconductor layer  13   b . In other words, the hole passivation layer  130  can create a high resistance blocking state between the gate electrode  16   c  and the first drain electrode  16   b  (shown with reference to  FIG.  6   ). 
     The hole passivation layer  130  can be achieved by injecting H ions into the first P-type semiconductor layer  13   b . The H ions can passivate the P-type doping ion Mg of the first P-type semiconductor layer  13   b  so that Mg does not generate holes. 
       FIG.  4    is a cross-sectional view illustrating a semiconductor structure according to a fourth embodiment of the present disclosure. 
     Referring to  FIG.  4   , the semiconductor structure  4  of the fourth embodiment is substantially the same as the semiconductor structures  1 ,  2 , and  3  of the first, second and third embodiments, the difference is only in that the gate region  12   c  is provided with a dielectric layer  14 . 
     The material of the dielectric layer  14  may include silicon dioxide or silicon nitride, etc. The dielectric layer  14  can change the degree of polarization of the gate region  12   c  in the heterojunction structure  11 , so that the semiconductor structure  4  is in a normally closed state. 
       FIG.  5    is a cross-sectional view illustrating a semiconductor structure according to a fifth embodiment of the present disclosure. 
     Referring to  FIG.  5   , the semiconductor structure  5  of the fifth embodiment is substantially the same as the semiconductor structure  4  of the fourth embodiment, the difference is only in that the dielectric layer  14  of the gate region  12   c  is provided with a second P-type semiconductor layer  15 . 
     The material of the second P-type semiconductor layer  15  may include at least one of GaN, AlGaN, InGaN or AlInGaN, and the P-type doping element may be Mg. 
     The second P-type semiconductor layer  15  may consume two-dimensional electron gas in the gate region  12   c  in the heterojunction structure  11 , such that the semiconductor structure  5  is in a normally closed state. 
     The second P-type semiconductor layer  15  in the fifth embodiment can be combined with the semiconductor structures  1 ,  2 , and  3  of the first, second and third embodiments, i.e., the gate region  12   c  is provided with the second P-type semiconductor layer  15 . 
       FIG.  6    is a cross-sectional view illustrating a semiconductor structure according to a sixth embodiment of the present disclosure. 
     Referring to  FIG.  6   , the semiconductor structure  6  of the sixth embodiment is substantially the same as the semiconductor structures  1 ,  2 ,  3 ,  4 , and  5  of the first to fifth embodiments. The difference is only in that: the source region  12   a  is provided with a source electrode  16   a , the quantum well structure  13  is a first drain electrode  16   b , and the gate region  12   c  is provided with a gate electrode  16   c ; the source electrode  16   a  is in ohmic contact with the heterojunction structure  11 , and the first drain electrode  16   b  is in ohmic contact with the quantum well structure  13 , and the gate electrode  16   c  is in Schottky contact with the heterojunction structure  11 . 
     The material of at least one of the source electrode  16   a , the first drain electrode  16   b  or the gate electrode  16   c  may include a metal, such as Ti/Al/Ni/Au, Ni/Au, and other existing conductive materials. 
       FIG.  7    is a cross-sectional view illustrating a semiconductor structure according to a seventh embodiment of the present disclosure. 
     Referring to  FIG.  7   , the semiconductor structure  7  of the seventh embodiment is substantially the same as the semiconductor structures  1 ,  2 ,  3 ,  4 ,  5 ,  6  of the first to sixth embodiments, the difference is only in that the drain region  12   b  is provided with a second drain electrode  16   d , and the second drain electrode  16   d  is in ohmic contact with the heterojunction structure  11 . 
     The first drain electrode  16   b  and the second drain electrode  16   d  may be connected in parallel. The first drain electrode  16   b  and the second drain electrode  16   d  can perform different functions when the same potential or different potentials are applied, depending on the specific design of the semiconductor structure  7 . 
     In the semiconductor structure  7  shown in  FIG.  7   , the second drain electrode  16   d  is disposed between the gate electrode  16   c  and the first drain electrode  16   b . In some embodiments, the first drain electrode  16   b  may also be disposed between the gate electrode  16   c  and the second drain electrode  16   d . 
     In the semiconductor structure  7  shown in  FIG.  7   , the first drain electrode  16   b  and the quantum well structure  13  are electrically insulated from the second drain electrode  16   d  by an insulating layer  17 . The insulating layer  17  may include a material such as silicon dioxide, silicon nitride, etc. In some embodiments, the insulating layer  17  may also be omitted. 
     Although the present disclosure is disclosed as above, the present disclosure is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the scope of the present disclosure shall be as defined by the claims.