Patent Publication Number: US-7592854-B2

Title: Temperature sensing circuit

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of application Ser. No. 10/390,699, filed on Mar. 19, 2003, now U.S. Pat. No. 7,078,954 which is hereby incorporated by reference in its entirety. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention generally relates to a temperature-sensing circuit using CMOS (complementary metal oxide semiconductor) transistors, and particularly relates to a temperature-sensing circuit capable of performing a stable operation at a high temperature, notably at a temperature above 100° C. 
   2. Description of the Related Art 
   There are various types of temperature sensors known in the art. 
   A first type is a temperature sensor system making use of thermocouples or resistors. In the case of thermocouples, a thermocurrent produced at a contact point between two types of metal wires is amplified by an amplifier and measured by a voltmeter. In the case of resistors, a three-wire bridge arrangement is used such that a voltage change due to the change of resistance is amplified by an amplifier and a change of resistance value due to a change of temperature is measured by a voltmeter. 
   A second type is a semiconductor temperature sensors using bipolar transistors (see “Transistor technology”, CQ publishing, October 1990, p. 469). Such sensors rely on the characteristic that the base-emitter voltage changes linearly in response to the change of temperature. Therefore, the semiconductor temperature sensors are widely used since they reduce production variation and give good accuracy and reproducibility. 
   A third type is a semiconductor temperature sensor using MOS transistors. For example, it is described in JP-A 9-243466 that a voltage gain β of the MOS transistor is converted into a voltage value and the converted voltage is output as a value representing temperature. JP-A 7-321288 discloses a temperature sensor based on a bipolar transistor similar to a technique described above, but using NPN transistors to achieve a CMOS transistor. 
   The above-mentioned first type temperature sensor system either using thermocouples or resistors generates a small output. Therefore, in order to amplify the output, it is necessary to connect a high-performance amplifier to the temperature sensor system. Such a complicated electronic circuit results in increased cost and size of the temperature sensor system. 
   The above-mentioned second type temperature sensor is constructed using a bipolar transistor and thus cannot be integrated into an IC chip fabricated by a standard CMOS process. Also, since a bipolar transistor is a current element controlled by an electric current, it is difficult to construct a circuit with a low current consumption. 
   Among the temperature sensors of the above-mentioned third type, the temperature sensor disclosed in JP-A 9-243466 is susceptible to process fluctuation since it uses the voltage gain value β. The temperature sensor disclosed in JP-A 7-321288 has a drawback in that it is difficult to form a circuit of low current consumption since the bipolar transistor similar to that used in the second type temperature sensor is a current element controlled by an electric current. 
   For all of the first, second and third types of temperature sensors, the upper limit of a range within which an accurate sensing can be guaranteed is about 100° C., at which point a reverse leakage current increases at a pn junction. Accuracy of temperature measurement rapidly drops at a temperature higher than the upper limit. 
   SUMMARY OF THE INVENTION 
   Accordingly, it is a general object of the present invention to provide a temperature-sensing circuit that can obviate the problems described above. 
   It is another and more specific object of the present invention to provide a temperature-sensing circuit using a MOS transistor that is operable with a high accuracy at a high temperature, notably at a temperature above 100° C. 
   In order to achieve the above objects according to the present invention, a temperature-sensing circuit includes: 
   a first circuit block outputting an output voltage having negative or positive temperature coefficients; 
   a second circuit block amplifying the output voltage of the first circuit block to a predetermined amplitude and outputting the amplified voltage as an output voltage of the second circuit block; and 
   a third circuit block producing a voltage having temperature coefficients of a polarity opposite to the output voltage of the first circuit block and adding the produced voltage to the output voltage of the second circuit block to cancel out components of second order temperature coefficients contained in the output voltages of both the first and second circuit blocks. 
   According to the present invention, the above objects can also be achieved by a temperature-sensing circuit including: 
   a first circuit block outputting an output voltage having negative temperature coefficients; 
   a second circuit block amplifying the output voltage of the first circuit block to a predetermined amplitude and outputting the amplified voltage as an output voltage of the second circuit block; and 
   a third circuit block producing a voltage having positive temperature coefficients and adding the produced voltage to the output voltage of the second circuit block to cancel out components of second order temperature coefficients contained in the output voltages of both the first and second circuit blocks. 
   According to the present invention, the above objects can also be achieved by a temperature-sensing circuit including: 
   a first circuit block outputting an output voltage having negative temperature coefficients; 
   a third circuit block outputting an output voltage having positive temperature coefficients; and 
   a second circuit block adding the output voltages at a predetermined ratio such that components of second order temperature coefficients contained in the output voltages of both the first and second circuit blocks are cancelled out. 
   In the temperature-sensing circuits described above, outputs of two of the circuit blocks are added in such a manner that the components of second order temperature coefficients contained in both outputs cancel out. Thus, the output voltages obtained from the temperature-sensing circuits contain first order temperature coefficients only. Accordingly, high-accuracy temperature-sensing circuits can be obtained. 
   In a preferred embodiment of the present invention, the temperature-sensing circuit includes a pair of MOS transistors. Accordingly, the temperature-sensing circuit can be fabricated at a reduced cost and can be integrated into an IC chip and thus the current consumption can be reduced. 
   In a preferred embodiment of the present invention provided with an adjusting part capable of adjusting values of the first resistor and the second resistor of the second circuit block after diffusion and film-forming step of a fabrication process, components of the second order temperature coefficients can be completely cancelled out. Thus, a high-accuracy temperature-sensing circuit can be provided. 
   Thus, according to the present invention, various drawbacks of the circuits using bipolar transistors can be eliminated by since a temperature detection circuit is fabricated using CMOS transistors. Thus, since MOS transistors are used, the temperature-sensing circuit of the present invention is operable with low current consumption and can be integrated into an IC chip. Further, since the circuit is arranged to obtain work function differences between a plurality of MOS transistors, a problem of junction leakage can be prevented. Thus, a temperature-sensing circuit operable at a high temperature notably above 100° C. can be provided. 
   Further, according to the temperature-sensing circuit of the present invention, the effect of process fluctuation is obviated by using MOS transistors having substrates and channels of the same doping density but having gates of opposite conductivity types or the same conductivity type with different impurity concentrations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram showing a principle of the present invention; 
       FIG. 2  is a block diagram showing another principle of the present invention; 
       FIG. 3A  is a graph showing a temperature characteristic curve of a first circuit block of the present invention; 
       FIG. 3B  is a graph showing a temperature characteristic curve of a third circuit block of the present invention; 
       FIG. 4  is a graph showing a temperature characteristic curve of an output of a temperature-sensing circuit of the present invention; 
       FIG. 5  is a diagram showing a circuit arrangement of a first embodiment of the temperature-sensing circuit of the present invention; 
       FIG. 6  is a diagram showing a circuit arrangement of a second embodiment of the temperature-sensing circuit of the present invention; 
       FIG. 7  is a diagram showing a circuit arrangement of a third embodiment of the temperature-sensing circuit of the present invention; 
       FIG. 8  is a diagram showing a circuit arrangement of a fourth embodiment of the temperature-sensing circuit of the present invention; and 
       FIG. 9  is a diagram showing trimmable resistors. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   In the following, the principle and embodiments of the present invention will be described with reference to the accompanying drawings. 
   According to the present invention, MOS transistors each having a gate with a work function different from a gate of the other MOS transistor are used for achieving a temperature-sensing circuit operable at a high temperature in a CMOS process. Before explaining embodiments of the present invention, the principle of the present invention will be described. 
   A threshold voltage Vt for switching ON a channel of a MOS transistor (hereinafter referred to as a transistor) is given by:
 
 V t=φms−Qf/Cox+ 2 φf−Qb/Cox   (1),
 
where, φms is the difference between work function φm of the gate and work function φs of a substrate, Qf represents fixed electric charges in an oxide film, φf represents the Fermi level of the substrate, Qb represents electric charges in a depletion layer between an inversion layer and the substrate and Cox represents capacitance per unit area of the oxide film. The work function φm of the gate can be expressed as:
 
φ m=χ+Eg/ 2 +φf   (2),
 
where, χ represents electron affinity and Eg represents band-gap energy.
 
   A first transistor and a second transistor of a pair of transistors used in each first and third circuit blocks of the present invention are identical except that conditions for the gate are different. For example, the polarity of electric conductivity at the gate may be opposite or the polarity may the same but of different concentration. This implies that for these pairs of transistors, equation (1) takes identical values except for φms and equation (2) takes identical values except for φf. 
   The difference between the threshold voltages Vt 1  and Vt 2  of the pair of transistors, respectively, can be expressed as:
 
Δ V t=Vt 1− Vt 2=φ m 1−φ m 2=φ f 1−φ f 2  (3),
 
where, Vt 1 , φm 1 , φf 1  are threshold voltage, work function at the gate and Fermi level of the substrate, respectively, for the first transistor, and, Vt 2 , φm 2 , φf 2  are threshold voltage, work function at the gate and Fermi level of the substrate, respectively, for the second transistor.
 
   In the first circuit block, the difference between threshold voltages ΔVt of a pair of transistors having gate conductivity types of opposite polarities is obtained. In a particular embodiment, the pair of transistors consists of a first MOS transistor having a heavily doped n-type gate and a second MOS transistor having a heavily doped p-type gate. 
   Since both n-type and p-type are heavily doped, φf 1  of n-type is near Conduction band and φf 2  of p-type is near Valence band and thus (φf 1 −φf 2 ) takes a value near the band gap of Si, which may be about 1.12 V. 
   In IEEE J. Solid-State Circuits, vol. SC-15, pp. 264, June 1980, there is an article on the consideration of the difference of Vt for a similar structure. Therein, the difference of Vt is expressed by an equation:
 
Δ Vt ( T )=Δφ f 0−(α T   2 )/ T+β,  
 
where Δφf 0  is Δφf (=φf 1 −φf 2 ) at absolute zero degrees, T represents absolute temperature, α and β are constants which take values of 7.02E-4 V/K and 1109 K, respectively.
 
     FIG. 3A  is a graph of ΔVt against temperature. As can be seen in the graph, ΔVt has a negative temperature characteristic. A detailed analysis of the characteristic curve indicates that it has a negative first order temperature coefficient and also a negative second order temperature coefficient. It is to be noted that the second order temperature coefficient has an adverse effect on the linearity between temperature and voltage and thus it is desirable to minimize the second order temperature coefficient. 
   In the third circuit block, the difference of Vt between a pair of transistors of “same conductivity type and different impurity concentration” is derived. In a particular embodiment, the pair of transistors includes a first MOS transistor having a heavily doped p-type gate and a second MOS transistor having a lightly doped P-type gate. 
   Accordingly, it can be derived from Equation (3) that: 
                           Δ   ⁢           ⁢   Vt     =       Vt   ⁢           ⁢   1     -     Vt   ⁢           ⁢   2                   =       ϕ   ⁢           ⁢   m   ⁢           ⁢   1     -     ϕ   ⁢           ⁢   m   ⁢           ⁢   2                   =       ϕ   ⁢           ⁢   f   ⁢           ⁢   1     -     ϕ   ⁢           ⁢   f   ⁢           ⁢   2                   =         -   kT     /     qln   ⁡     (     Ng   ⁢           ⁢     1   /   Ni       )         +     kT   /     qln   ⁡     (     Ng   ⁢           ⁢     2   /   Ni       )                       =     kT   /     qln   ⁡     (     Ng   ⁢           ⁢     2   /   Ng     ⁢           ⁢   1     )                 ,           (   4   )               
where Ng 1  and Ng 2 , respectively, represent lightly and heavily doped gates of the same conductivity type. In Equation (3), k is the Boltzmann constant, q is an amount of charge of electrons, T is absolute temperature, Eg is the band gap of silicon and Ni is carrier concentration of an intrinsic semiconductor.
 
   Referring to Equation (4), it appears that ΔVt has a linear relationship against absolute temperature T, or in other words, it appears that ΔVt can be expressed by a first order positive temperature coefficient only. However, since Ng 1  is lightly doped, the effective carrier concentration is not in fact equal to Ng 1  and the carrier concentration Ng 1  itself has a positive temperature coefficient. Therefore, temperature characteristics of ΔVt appear in a superposed manner as shown in  FIG. 3B  which is a plot of a result of actual measurement. As can be seen in the graph, ΔVt has a positive temperature characteristic. A detailed analysis of the characteristic curve indicates that it has a positive first order temperature coefficient and also a positive second order temperature coefficient. Because of the second order temperature coefficient, this characteristic alone is not suitable for being used as a high-precision temperature-sensing circuit for the same reason as for the first circuit block. 
   Therefore, according to the present invention, in order to cancel out the negative second order temperature coefficient contained in the output of the first circuit block and the positive second order temperature coefficient contained in the output of the third circuit block, these outputs are added (or mixed) in the second circuit block at a predetermined ratio. 
     FIG. 4  is a graph showing a result of an operation of multiplying the negative second order output of the first circuit block by a factor of 0.86 in the second circuit block and then adding it with the positive second order temperature coefficient of the third circuit block. As a result of the operation, the second order temperature coefficient is cancelled out and an output voltage having a substantially perfectly first order temperature coefficient (correlation coefficient R 2  representing the degree of correlation against a straight line is 0.9999999997). Accordingly, a high-precision temperature-sensing circuit can be achieved. 
   As has been described above, the output voltages having positive temperature coefficients or negative temperature coefficients are all obtained by taking the difference of Vt as the difference between work functions of the gates. As can be understood from Equation (3), this value is the difference between inherent physical number φf of poly silicon (Poly Si) used as a gate material of the MOS transistors. Therefore, essentially, this value is not affected by the structure or mode of use of the device. Accordingly, unlike the temperature-sensing method using the temperature characteristic of the current value at the pn-junction, the temperature detecting circuit of the present invention is capable of performing a high-precision sensing at a temperature higher than 100° C., since there is no increase of reverse leakage current at the pn-junction and there is less effect due to process fluctuation. 
   In the following, embodiments of circuit configurations for realizing the principle of the present invention will be described in detail. 
     FIG. 5  shows a circuit configuration of the first embodiment of the present invention in which MOS transistors M 1  and M 2  form the first circuit block, a MOS transistor M 5  and resistors R 1  and R 2  form the second block and MOS transistors M 3  and M 4  form the third circuit block. 
   First, a detailed circuit configuration for obtaining the difference between threshold voltages Vt of a pair of MOS transistors in the first circuit block will be described. In the figure, the MOS transistor M 2  indicated by a circle has a heavily doped p-type polysilicon gate and the MOS transistor M 1  has a heavily doped n-type polysilicon gate. 
   Drain current Id of the MOS transistor in a saturation region (Vds&gt;Vgs−Vt) is represented by:
 
 Id =(β12)( Vgs−Vt ) 2   (5),
 
where Vgs represents gate-source voltage of the MOS transistor.
 
   In the Equation, β represents the conductivity coefficient of the MOS transistor and is expressed by an equation:
 
β=μ(ε ox/Tox )( Weff/Leff )  (6),
 
where, μ represents mobility of carrier, εox represents permittivity of oxide film, Tox represents thickness of oxide film, Weff represents effective channel width and Leff represents effective channel length.
 
   The MOS transistors M 1  and M 2  forming a pair have similar structures except for the polarity of impurities of the gate electrodes. Accordingly, since the mobility of carrier μ, the permittivity of oxide film εox, the thickness of oxide film Tox, the effective channel width Weff, and the effective channel length Leff are the same for both transistors, the value β is the same for both transistors. Therefore, drain currents Id 1  and Id 2  of the MOS transistors M 1  and M 2 , respectively, can be represented by:
 
 Id 1=(β/2)( Vgs 1− Vt 1) 2   (7),
 
 Id 2=(β/2)( Vgs 2− Vt 2) 2   (8),
 
where Vgs 1  and Vgs 2  are gate-source voltages of the MOS transistors M 1  and M 2 , respectively.
 
   As can be seen in  FIG. 5 , since the transistors M 1  and M 2  are in series connection between the power supply Vcc and the ground GND, the drain currents are equal, i.e., Id 1 =Id 2 . Therefore, from Equations (7) and (8), it can be derived that:
 
 Vgs 1− Vgs 2= Vt 1− Vt 2=Δ Vt   (9).
 
Since it is known that for the MOS transistor M 1 , Vgs 1 =0V, it can be expressed that:
 
 Vgs 2= Vt 2− Vt 1  (10).
 
Accordingly, it can be seen that Vgs 2 =ΔVt=V 1  and this voltage V 1  has the second order temperature coefficient that has been described in the description of the principle of the present invention. This voltage V 1  is supplied to the second circuit block of the next stage.
 
   The second circuit block includes the MOS transistor M 5  and a series connection of the first resistor R 1  and the second resistor R 2 . The output of the first block is applied to a connecting point between the MOS transistor M 5  and the resistor R 1  and the gate voltage of the MOS transistor M 5  is supplied as a feed back voltage to the first circuit block, so as to form a source-follower circuit. In the present embodiment, the ratio between the resistor R 1  and the resistor R 2  is determined such that the voltage V 2  at an output of the second circuit block of  FIG. 5  is expressed by:
 
 V 2=0.86 ×V 1  (11).
 
The voltage V 2  is supplied to the third circuit block of the next stage.
 
   As has been explained with reference to  FIG. 4 , the value 0.86 is selected for cancelling out the second order temperature coefficient components by adding the output containing the negative second order temperature coefficient from the first circuit block and the output containing the positive second order temperature coefficient from the third circuit block, in order to obtain a high-precision output voltage that contains the first order temperature coefficient only. 
   It is to be noted that resistance values of the resistors R 1  and R 2  may vary slightly due to the difference between processes. In order to obtain a predetermined resistance ratio, one or both of the resistors R 1  and R 2  are formed as a resistive body arranged in a manner, for example, shown in  FIG. 9 , and then, after diffusion and film-forming processes, a laser beam is selectively irradiated on adjustment parts indicated by a “X” mark to trim the resistive body. By obtaining a predetermined resistance ratio by correcting the resistance values of the resistors R 1  and R 2  using such trimming means (resistance value adjusting means), the second order temperature coefficient components can be completely eliminated. 
   In the third circuit block, the MOS transistor M 4  indicated by a triangle has a lightly doped (Ng 1 ) n-type polysilicon gate. In a manner similar to the transistor M 1 , the MOS transistor M 3  has a heavily doped (Ng 2 ) n-type polysilicon gate. In a manner similar to the first circuit block, the difference ΔVt between the threshold voltages Vt 4  and Vt 3  of the transistors M 4  and M 3 , respectively, is considered. Then, the gate-source voltage Vgs 3  of the MOS transistor M 3  can be expressed as:
 
 Vgs 3=−Δ Vt =−( Vt 4− Vt 3)  (12),
 
where ΔVt is the voltage containing the second order temperature coefficient that has been explained in the principle of the present invention. Since the voltage V 2  containing the negative temperature coefficient is supplied from the upstream stage, the output V 3  of the third circuit block can be expressed by:
 
 V 3= V 2− Vgs 3= V 2−(−Δ Vt )= V 2+Δ Vt   (13),
 
where V 3  corresponds to Vtemp indicated in  FIG. 4 .
 
   Thus, according to the arrangement described above, the outputs of the first and third circuit blocks are added such that the negative second order temperature coefficient component contained in output of the first circuit block and the positive second order temperature coefficient component contained in the output of the third circuit block cancel each other. Therefore, since the second order temperature coefficient is cancelled out, the output V 3  (Vtemp) has a high-precision temperature characteristic containing the first order temperature coefficient only. 
   In the above-mentioned first embodiment of the present invention, the MOS transistors are all N-channel transistors. An essential requirement for a pair of MOS transistors is that all elements except for the gate be the same. That is to say, the MOS transistors show a degree of being a paired structure. In order to achieve this, it is necessary that the substrate potential of the MOS transistor be independent from the other MOS transistor and that the substrate potential and the source potential are made equal to eliminate a back-bias effect. According to the first embodiment of the present invention, this is achieved by providing an N-channel transistor formed in an independent P-well. 
   However, in some technologies, there may be a case where there are independent N-wells but no P-well. In such a case, the MOS transistor is formed on a P-channel. This is the second embodiment of the present invention.  FIG. 6  shows a circuit configuration of the second embodiment of the present invention. Circuit arrangements of the first, second and third circuit blocks, calculation of the difference of Vt and a manner in which V 1 , V 2  and V 3  are generated are the same as in the first embodiment. It is to be noted that in the first circuit block, the voltage containing a negative second order temperature coefficient is output from the power supply Vcc, and in the second circuit block, the output V 2  is also output as a voltage from the power supply Vcc. Therefore, the output V 3  of the third circuit block that is a final output voltage obtained by adding the negative second order temperature coefficients is output as a voltage from the ground GND. 
   According to the above-mentioned second embodiment of the present invention, the final output V 3  is converted into an output from the ground GND in the third circuit block. Also, the third circuit block is formed by the first MOS transistor having a heavily doped n-type gate and the second MOS transistor having a lightly doped n-type gate. According to the third embodiment of the present invention, the voltage from the power supply Vcc is converted into an output from the ground GND in the second circuit block. Also, the second circuit block is formed by the first MOS transistor having a heavily doped p-type gate and the second MOS transistor having a lightly doped p-type gate. 
   The MOS transistor M 4  indicated by a square has a lightly doped (Ng 1 ) p-type polysilicon gate. The MOS transistor M 3  indicated by a circle has a heavily doped (Ng 2 ) p-type polysilicon gate. Calculation of the difference of Vt and a manner in which V 1 , V 2  and V 3  are generated are the same as in the first embodiment. 
     FIG. 8  shows a circuit configuration of the fourth embodiment of the present invention. In the fourth embodiment, the first circuit block “a” and the second circuit block “b” are the same as those of the first embodiment (see  FIG. 5 ). The fourth embodiment of the present invention is characterized in that the third circuit block “c” is formed as a negative-feedback operation amplifier. 
   That is to say, in the third circuit block “c”, the MOS transistor M 3  having a heavily doped n-type gate and the MOS transistor M 4  having a lightly doped n-type gate serve as input MOS transistors of the first stage differential amplifier. The output V 3  of the upstream second circuit block is input into the MOS transistor M 3 . Since the Vt of the MOS transistors of the differential inputs are different, V 4  of the third circuit block V 4  is a voltage obtained by adding the difference of Vt between the MOS transistor M 3  and the MOS transistor M 4  (ΔVt) and the gate voltage V 3  of the MOS transistor M 3 . 
   That is to say, the voltage V 3  containing the negative second order temperature coefficient and the voltage containing the positive second order temperature coefficient (the difference between Vt of the MOS transistor M 3  and Vt of the MOS transistor M 4 ) are added and the voltage V 4  having the first order temperature coefficient in which only the second order temperature coefficient is cancelled out is obtained. Also, since the third block is configured as an operation amplifier, the output voltage can be output as a voltage V 5  that is obtained by multiplying V 4  by a certain factor. 
   Finally, a process of fabricating a MOS transistor will be described. Gates of different impurity concentrations may be formed by performing the steps of depositing a non-doped gate, masking portions to be formed into lightly doped gates by an oxide film, heavily doping portions that are not masked by deposition of phosphor, etching the masking oxide film and lightly doping phosphor or boron into the lightly doped portions by ion-implantation. 
   It is also possible to form the heavily doped portion by ion-implantation in a similar manner to the lightly doped portion. Thus, a pair of MOS transistors having gates of same conductivity type and different Fermi level φf can be formed. Since the same process is used except for the doping step of the gate, the gate is formed with the same thickness of insulation film, channel dope, channel length and channel width. Therefore, the only difference is the concentration of impurity, and the difference in the threshold voltages Vt is equivalent to the difference in the Fermi levels φf. 
   Each of the above-mentioned embodiments makes use of an n-type channel MOS transistor and a p-type channel MOS transistor as MOS transistors M 1  and M 2  with the gate being a combination of a heavily or lightly doped n-type region or a heavily or lightly doped p-type region. However, when the circuit is configured using the first, second and third circuit blocks of the present invention, a similar circuit can be easily obtained using the gate of other combinations. 
   Also, each of the above-mentioned embodiments is characterized in that the first circuit block outputs a voltage containing a “negative” second order temperature coefficient and the third circuit block outputs a voltage containing a “positive” temperature coefficient. However, it is possible to obtain the same configuration with the first circuit block outputting a voltage containing a “positive” second order temperature coefficient and the third circuit block outputs a voltage containing a “negative” temperature coefficient. 
   Also, each of the above-mentioned embodiments has been explained with reference to the block configuration shown in  FIG. 1 , but it is also possible to implement each of the embodiments in accordance with the block configuration shown in  FIG. 2 . 
   Further, the present invention is not limited to these embodiments, and variations and modifications may be made without departing from the scope of the present invention. 
   The present application is based on Japanese priority application No. 2002-077915 filed on Mar. 20, 2002, the entire contents of which are hereby incorporated by reference.