Patent Publication Number: US-8530315-B2

Title: finFET with fully silicided gate

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is continuation of and claims priority from U.S. patent application Ser. No. 13/345,233 filed on Jan. 6, 2012, the disclosure of which is hereby incorporated by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention generally relates to the field of semiconductors, and more particularly relates to fin field effect transistors (finFETs) with a fully silicided gate. 
     BACKGROUND OF THE INVENTION 
     Fin field effect transistors (finFETs) are leading candidates to enable the scaling of gate lengths to 25 nm and below. When using finFETs, it is desirable to lower the gate resistance to improve performance characteristics such as the effective AC resistance (AC R eff ) and the maximum operating frequency (RF f max ). One approach to lowering the gate resistance is polysilicon pre-doping. Pre-doping the polysilicon with boron or arsenic and then performing a rapid thermal anneal (RTA) is commonly used in fabricating planar CMOS devices. However, with the 3D structure of a fin FET, it is difficult to achieve a uniform high doping concentration down to the line in-between the fins through such a conventional implant and thermal diffusion. Additionally, this requires an extra mask step to form both nFET and pFET devices formed. 
     Another approach to lowering the gate resistance is increasing the thickness of the gate silicide. The thickness of the gate silicide can be increased by increasing the initial nickel platinum (NiPt) deposition thickness or by performing RTA at a higher temperature. However, both of these methods for increasing the thickness of the gate silicide also increase the thickness of the silicide in the source/drain regions. This leads to silicide encroachment and increased junction leakage. 
     SUMMARY OF THE INVENTION 
     One embodiment of the present invention provides a method for fabricating a finFET device. According to the method, multiple fin structures are formed over a buried insulator (BOX) layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes a dielectric layer and a polysilicon layer. Gate spacers are formed on vertical sidewalls of the gate stack, and an epitaxial silicon (epi) layer is deposited over the fin structures to merge the fin structures together. Ions are implanted to form source and drain regions in the fin structures, and the gate spacers are etched so that an upper surface of the gate spacers is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions. 
     Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a finFET device according to one embodiment of the present invention; 
         FIG. 2  illustrates a polysilicon structure formed above an SOI substrate during a process for fabricating a finFET device in accordance with a first embodiment of the present invention; 
         FIG. 3  illustrates silicon nitride structures formed on the sides of the polysilicon structure during the fabrication process of the first embodiment; 
         FIG. 4  illustrates the formation of fin structures during the fabrication process of the first embodiment; 
         FIG. 5  illustrates formation of a gate stack perpendicular to the fin structures during the fabrication process of the first embodiment; 
         FIG. 6  illustrates gate spacers formed along the sides of the gate stack during the fabrication process of the first embodiment; 
         FIG. 7  illustrates an epitaxial silicon layer deposited over the fin structures during the fabrication process of the first embodiment; 
         FIG. 8  illustrates the spacers pulled down prior to silicidation during the fabrication process of the first embodiment; 
         FIG. 9  is a cross-sectional view illustrating the spacers pulled down prior to silicidation during the fabrication process of the first embodiment; 
         FIG. 10  is a cross-sectional view illustrating silicidation during the fabrication process of the first embodiment; and 
         FIG. 11  is a cross-sectional view illustrating a fully silicided gate during the process of the first embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Preferred embodiments of the present invention will be described in detail hereinbelow with reference to the attached drawings. 
     Embodiments of the present invention provide fin field effect transistors (finFETs) with a fully silicided gate. The gate spacers are pulled down prior to silicidation. By partially removing the gate spacers from the gate sidewall prior to silicidation, the polysilicon layer of the gate of the finFET can be fully silicided during the silicidation process without increasing the thickness of the silicide in the source/drain regions. Thus, the gate resistance is lowered without increasing junction leakage. Additionally, there is a concurrent stress benefit from liner proximity. 
       FIG. 1  shows a finFET device according to one embodiment of the present invention. The finFET device  100  is formed on a silicon-on-insulator (SOI) substrate. The SOI substrate includes a semiconductor layer disposed on a buried insulator (BOX) layer  112 , which is disposed on a semiconductor substrate. In another embodiment, the finFET device is formed on a bulk silicon substrate. 
     The finFET device  100  includes a gate stack disposed on a hardmask  104  (i.e., dielectric). The gate stack of this embodiment is a fully silicided gate  902  that includes a fully silicided polysilicon layer, a metal gate, and a high-K layer. Source/drain regions  214  are provided, with the gate stack  902  being located between the source/drain regions  214 . Gate spacers  905  with an inverted-L shape are located on the vertical sidewalls of the gate stack  102 . 
     In this embodiment, the gate spacers  905  are formed of one or more layers of silicon nitride (SiN) and/or silicon oxide (SiO 2 ). Silicide regions  904  are formed in an upper portion of the source/drain regions  214 . An upper surface of the gate spacers  905  reaches less than half the height of the gate  902  above the top surface of the source/drain regions. In one embodiment, the upper surface of the gate spacers is near the top surface of the source/drain regions (e.g., ⅛ or less the height of the gate above the top surface of the source/drain regions). 
       FIGS. 2-11  illustrate a process for fabricating the finFET device of  FIG. 1  according to one embodiment of the present invention. The process begins with an SOI substrate that includes a semiconductor layer  111  (e.g., a silicon layer) disposed on a buried insulator (BOX) layer  112  (e.g., an oxide layer). As shown in  FIG. 2 , a hardmask (dielectric) layer  104  is formed on the semiconductor layer  111 . The hard mask layer  104  of this embodiment is silicon dioxide (SiO 2 ) or silicon nitride (SiN). A polysilicon structure  204  is deposited on the hardmask layer  104  and then etched. As shown in  FIG. 3 , silicon nitride removable structures  206  are formed on the vertical sidewalls of the polysilicon structure  204  through a standard deposition and etching process. 
     As shown in  FIG. 4 , the polysilicon structure  204  is removed, and the hardmask and semiconductor layers  104  and  111  are etched to form fin structures  208 . The removable structures  206  are then removed, as shown in  FIG. 5 . This produces fin structures  208  that are formed by the portions of the hardmask layer  104  and semiconductor layer  111  that were located under the removable structures  206 . In another embodiment, the dielectric  208  is removed to form the trigate structure. 
     A gate stack  102  is formed on the BOX layer  112  perpendicular to the fin structures  208 , and an SiN layer  210  is formed on the gate stack  102 . The gate stack  102  of this embodiment includes a polysilicon layer, a metal gate, and a high-K layer (e.g., HfO 2 ). In this illustrative embodiment, the gate length (L gate ) is about 25 nm or less. Next, as shown in  FIG. 6 , upper portions of the hardmask layer  104  and the SiN layer  210  are removed. Gate spacers  106  are formed along the vertical sidewalls of the gate stack  102 . Optionally, ions are then implanted to form source and drain extension regions that extend under the spacer. 
     An epitaxial silicon (epi) layer  214  is then deposited over the fin structures  208 , as shown in  FIG. 7 . In the illustrated embodiment, the epi layer is an undoped or in-situ doped epitaxial film with a thickness of about 30 nm, and the polysilicon layer of the gate extends about 40 nm above the top surface of the epi layer  214 . The epi layer  214  creates uniform extensions on the fins so as to merge the individual fin structures  208  together. The use of in-situ doped films enables uniform junction formation, which results in a reduction in resistance. An in-situ doped epi layer provides conformal doping of the devices, reduces the resistance, and significantly improves performance. In an alternative embodiment, a silicon germanium (SiGe) cladding is deposited over the fins instead of the epi layer. 
     Ions are then implanted into the semiconductor layer  111  to form source and drain regions. The result of epi formation and ion implantation is a finFET device with merged source/drain regions S and D. A channel region is located between the source/drain regions S and D. Next, second spacers  109  are formed on the vertical sidewalk of the gate spacers  106 . The second spacers  109  extend to the top surface of the epi layer  214  of the merged source/drain regions. In this embodiment, the second spacers  109  are formed of one or more layers of silicon nitride (SiN) and/or silicon oxide (SiO 2 ). The gate spacers  106  and the second spacers  109  can be formed of the same or different materials. 
     As shown in  FIG. 8 , an etch is then performed to pull down the gate spacers  106  and the second spacers  109 . In this illustrative embodiment, the spacers  106  and  109  are pulled down to near the top surface of the epi layer (e.g., about 5 nm or less from the top surface of the epi layer). The remaining portions of the spacers combine to form spacers  905  with an inverted-L shape profile, as shown in  FIGS. 8 and 9 . In another embodiment, the spacers are pulled down by at least half of the height of the gate  102  above the top surface of the epi layer  214  (e.g., pulled down by at least about 20 nm). The spacers can be etched by adjusting the overetch time before silicidation. 
     Next, silicidation is performed. As shown in  FIG. 10 , metal  901  (e.g., NiPt) is deposited over the structure. RTA is then performed to diffuse the deposited metal and form silicide regions. During RTA, there is vertical diffusion of the metal into the top surfaces of the gate  102  and source/drain regions  214 . And because the spacers were pulled down prior to silicidation, there is also horizontal diffusion of the metal into the vertical sidewalls of the polysilicon layer of the gate  102 . The result is silicide regions  904  in the upper portions of the source/drain regions  214 , and a polysilicon layer of the gate that is fully silicided  902 , as shown in  FIGS. 1 and 11 . The silicide on the source/drain regions is much shallower than on the gate. In the illustrated embodiment, a nickel platinum silicide is formed. In further embodiments, the silicide is formed using nickel, platinum, titanium, cobalt, or a combination or alloy thereof. 
     By pulling down the spacers  902  by at least half of the height of the gate above the top surface of the epi layer  214  prior to silicidation, the additional horizontal diffusion into the vertical sidewalls of the gate can operate to convert the entire polysilicon layer of the gate to form the fully silicided gate (i.e., silicide down to the metal gate layer). The full silicidation of the gate is better assisted by pulling down the gate to nearer to (e.g., 5 nm or less) the top surface of the epi layer. Full silicidation is also assisted by reducing the height of the polysilicon layer, depositing a thicker metal layer, or performing RTA at a higher temperature. While there are performance-based reasons to limit the use of such alterations as explained above, more conservative use of one or more of these in addition to pulling down the gate spacers prior to silicidation can enhance full silicidation without producing the same drawbacks because the silicide on the source/drain regions is much shallower than on the gate. 
     Conventional fabrication steps are then performed to form the remainder of the integrated circuit that includes this finFET. For example, a stress liner is formed, contacts are formed on the silicide regions, and then metal lines are formed. 
     Accordingly, embodiments of the present invention provide a finFET device with a fully silicided gate. The gate spacers are pulled down prior to silicidation. By at least partially removing the gate spacers from the gate sidewall prior to silicidation, there is both vertical and horizontal diffusion into the polysilicon layer of the gate during silicidation. This allows the polysilicon layer of the gate of the finFET to be fully silicided during the silicidation process without increasing the thickness of the silicide in the source/drain regions. Thus, the gate resistance is lowered without increasing junction leakage. From an intrinsic device point of view, the fully silicided gate provides significantly better f max , f CROSS , f min , and R N  at a lower finger width. The device is particularly well suited for ultralow-power/low-noise RF applications. 
     It should be noted that some features of the present invention may be used in an embodiment thereof without use of other features of the present invention. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples, and exemplary embodiments of the present invention, and not a limitation thereof. 
     It should be understood that these embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. 
     The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed. 
     The methods as discussed above are used in the fabrication of integrated circuit chips. 
     The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products (such as, but not limited to, an information processing system) having a display, a keyboard, or other input device, and a central processor. 
     As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention. 
     The terms “a” or “an”, as used herein, are defined as one as or more than one. The term plurality, as used herein, is defined as two as or more than two. Plural and singular terms are the same unless expressly stated otherwise. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The terms program, software application, and the like as used herein, are defined as a sequence of instructions designed for execution on a computer system. A program, computer program, or software application may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system. 
     Although specific embodiments of the invention have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the invention. The scope of the invention is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.