Patent Publication Number: US-2021167125-A1

Title: Display device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a National Phase patent application of International Patent Application No. PCT/KR2019/009108, filed on Jul. 23, 2019, which claims priority to and the benefit of Korean Patent Application No. 10-2018-0095664 filed in the Korean Intellectual Property Office on Aug. 16, 2018, the entire contents of which are incorporated herein by reference. 
    
    
     BACKGROUND 
     (a) Field 
     The present disclosure relates to a display device. 
     (b) Description of the Related Art 
     Generally, as a display device, a liquid crystal display (LCD), a light emitting diode (LED) display, and the like are used. 
     A light emitting diode display includes two electrodes and a light emitting layer disposed therebetween, and an electron injected from a cathode, which is one electrode, and a hole injected from an anode, which is the other electrode, are coupled with each other in the light emitting layer to generate an exciton, and the exciton emits energy to emit light. 
     The light emitting diode display includes a plurality of pixels including a light emitting diode including a cathode, an anode, and a light emitting layer, and each pixel includes a plurality of transistors and capacitors for driving the light emitting diode. 
     The transistor includes a gate electrode, a source electrode, a drain electrode, and a semiconductor layer. The semiconductor layer is an important element determining characteristics of the transistor. The semiconductor layer is mainly made of silicon (Si). Silicon is classified into amorphous silicon and polycrystalline silicon according to a crystal form. Amorphous silicon has a simple manufacturing process, but has low charge mobility, so it has limitations in manufacturing high-performance transistors, while polycrystalline silicon has high charge mobility, but requires a step of crystallizing silicon, increasing manufacturing cost and making the process complicated. Recently, research has been conducted on transistors using oxide semiconductors having higher electron mobility and a higher ON/OFF ratio than amorphous silicon and having lower cost and higher uniformity than polycrystalline silicon. 
     SUMMARY OF THE INVENTION 
     Technical Problem 
     Embodiments provide a display device that may reduce a time and cost required for a manufacturing process through a simple manufacturing process. 
     Technical Solution 
     A display device according to some embodiments includes: a substrate; a first transistor and a second transistor disposed on the substrate and spaced apart from each other; a first electrode connected to one of the first transistor and the second transistor; a second electrode overlapping the first electrode; and a light emitting layer between the first electrode and the second electrode, wherein the first transistor may include: a first semiconductor layer on the substrate; a first gate electrode on the first semiconductor layer; and a first source electrode and a first drain electrode connected to the first semiconductor layer, and the second transistor may include: a second semiconductor layer on the substrate; a second gate electrode on the second semiconductor layer; and a second source electrode and a second drain electrode connected to the second semiconductor layer, and the first gate electrode and the second semiconductor layer may be on the same layer. 
     The first gate electrode may include polycrystalline silicon doped with impurities. 
     The second semiconductor layer may include polycrystalline silicon. 
     The first semiconductor layer may include an oxide semiconductor. 
     The first transistor may be connected to the first electrode. 
     The display device may include: a buffer layer on the substrate; and a first gate insulating layer on the first semiconductor layer, and the first semiconductor layer may be between the buffer layer and the first gate insulating layer, while the second semiconductor layer and the first gate electrode may be on the first gate insulating layer. 
     The display device may further include a second gate insulating layer on the second semiconductor layer and the first gate electrode, and the second gate electrode may be on the second gate insulating layer. 
     A display device according to another embodiment includes: a substrate; a first transistor and a second transistor disposed on the substrate and spaced apart from each other; a first electrode connected to one of the first transistor and the second transistor; a second electrode overlapping the first electrode; and a light emitting layer between the first electrode and the second electrode, wherein the first transistor may include: a first semiconductor layer on the substrate; a first gate electrode on the first semiconductor layer; and a first source electrode and a first drain electrode connected to the first semiconductor layer, and the second transistor may include: a second semiconductor layer on the substrate; a second gate electrode on the second semiconductor layer; and a second source electrode and a second drain electrode connected to the second semiconductor layer, and the first semiconductor layer and the second gate electrode may be on the same layer. 
     The first semiconductor layer may include polycrystalline silicon, and the second semiconductor layer may include an oxide semiconductor. 
     The second gate electrode may include polycrystalline silicon doped with impurities. 
     The display device may further include: a buffer layer on the substrate; an insulating layer on the second semiconductor layer; and a first gate insulating layer on the first semiconductor layer, and the second semiconductor layer may be between the buffer layer and the insulating layer, while the first semiconductor layer may be between the insulating layer and the first gate insulating layer. 
     The first gate electrode may be on the first gate insulating layer, and the second gate electrode may be between the insulating layer and the first gate insulating layer. 
     A display device according to another embodiment includes: a substrate; a first transistor and a second transistor disposed on the substrate and spaced apart from each other; a first electrode connected to one of the first transistor and the second transistor; a second electrode overlapping the first electrode; and a light emitting layer between the first electrode and the second electrode, wherein the first transistor may include: a first gate electrode on the substrate; a first semiconductor layer on the first gate electrode; and a first source electrode and a first drain electrode connected to the first semiconductor layer, and the second transistor may include: a second semiconductor layer on the substrate; a second gate electrode on the second semiconductor layer; and a second source electrode and a second drain electrode connected to the second semiconductor layer, and the first gate electrode and the second semiconductor layer may be on the same layer. 
     The first gate electrode may include polycrystalline silicon doped with impurities. 
     The first semiconductor layer may include an oxide semiconductor. 
     The second semiconductor layer may include polycrystalline silicon. 
     The display device may further include an auxiliary metal layer on the first semiconductor layer, wherein the auxiliary metal layer and the second gate electrode may be on the same layer. 
     The auxiliary metal layer may be between the first semiconductor layer and the first source electrode and between the first semiconductor layer and the first drain electrode. 
     The auxiliary metal layer may directly contact the first semiconductor layer. 
     The display device may further include: a buffer layer on the substrate; and a gate insulating layer on the buffer layer, and the first gate electrode and the second semiconductor layer may be between the buffer layer and the gate insulating layer. 
     Advantageous Effects 
     According to the embodiments, it is possible to provide a display device that may reduce a time and cost required for a manufacturing process through a simple manufacturing process. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a cross-sectional view a partial area of a display device according to some embodiments. 
         FIG. 2  illustrates a cross-sectional view a partial area of a display device according to some embodiments. 
         FIG. 3  illustrates a cross-sectional view a partial area of a display device according to some embodiments. 
         FIG. 4  illustrates a cross-sectional view a partial area of a display device according to some embodiments. 
         FIG. 5 ,  FIG. 6 ,  FIG. 7 , and  FIG. 8  respectively illustrate a cross-sectional view of a partial area of a display device according to a manufacturing process. 
         FIG. 9  illustrates an equivalent circuit diagram of one pixel of a display device according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. 
     Parts that are irrelevant to the description will be omitted to clearly describe the present disclosure, and like reference numerals designate like elements throughout the specification. 
     Further, in the drawings, the size and thickness of each element are arbitrarily illustrated for ease of description, and the present disclosure is not necessarily limited to those illustrated in the drawings. In the drawings, the thicknesses of layers, films, panels, regions, areas, etc. are exaggerated for clarity. In the drawings, for ease of description, the thicknesses of some layers and areas are exaggerated. 
     It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, in the specification, the word “on” or “above” means positioned (or disposed) on or below the object portion, and does not necessarily mean positioned (or disposed) on the upper side of the object portion based on a gravitational direction. 
     In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. 
     Further, throughout the specification, the phrase “in a plan view” or “on a plane” means viewing a target portion from the top, and the phrase “in a cross-section” or “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side. 
     Hereinafter, a display device according to some embodiments will be described in detail with reference to the accompanying drawings. Hereinafter, a display device according to some embodiments will be described with reference to  FIG. 1 .  FIG. 1  illustrates a cross-sectional view a partial area of a display device according to some embodiments. 
     Referring to  FIG. 1 , a substrate  110  includes a first area PA 1  in which a first transistor Ta is disposed and a second area PA 2  in which a second transistor Tb is disposed. First, the first area PA 1  will be described, and then the second area PA 2  will be described. 
     The substrate  110  may include a glass substrate or a substrate in which a polymer layer and a barrier layer are alternately stacked. 
     A buffer layer  111  is disposed on the substrate  110  corresponding to the first area PA 1 . The buffer layer  111  may include an inorganic insulating material such as a silicon oxide, a silicon nitride, or the like, or an organic insulating material. The buffer layer  111  may be a single layer or a multilayer. For example, when the buffer layer  111  is a double layer, a lower layer thereof may include a silicon nitride, and an upper layer thereof may include a silicon oxide. 
     A first semiconductor layer  130   a  is disposed on the buffer layer  111 . The first semiconductor layer  130   a  according to some embodiments includes an oxide semiconductor. 
     The oxide semiconductor may include a combination of a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), and an oxide thereof. More specifically, the oxide semiconductor may include at least one of a zinc oxide (ZnO), a zinc-tin oxide (ZTO), a zinc-indium oxide (ZIO), an indium oxide (InO), a titanium oxide (TiO), an indium-gallium-zinc oxide (IGZO), and an indium-zinc-tin oxide (IZTO). 
     A first gate insulating layer  141  is disposed on the first semiconductor layer  130   a . The first gate insulating layer  141  may include an inorganic insulating material such as a silicon nitride, a silicon oxide, or the like, or an organic insulating material. 
     A first gate electrode  154   a  is disposed on the first gate insulating layer  141 . The first gate electrode  154   a  overlaps the first semiconductor layer  130   a.    
     The first gate electrode  154   a  according to some embodiments includes polycrystalline silicon doped with impurities. The first gate electrode  154   a  is in a conductive state as impurities are doped into polycrystalline silicon. An impurity doped into the first gate electrode  154   a  may be a group  5  element, and the first gate electrode  154   a  may be n+ doped. 
     A second gate insulating layer  142  is disposed on the first gate electrode  154   a  and the first gate insulating layer  141 . The second gate insulating layer  142  may include an inorganic insulating material such as a silicon nitride, a silicon oxide, or the like, or an organic insulating material. 
     A storage electrode  125   a  is disposed on the second gate insulating layer  142 . The storage electrode  125   a  may include at least one of copper, a copper alloy, aluminum, an aluminum alloy, molybdenum, and a molybdenum alloy. 
     A storage capacitor may be configured by overlapping the first gate electrode  154   a  and the storage electrode  125   a  in a plan view with the second gate insulating layer  142  therebetween. 
     A first insulating layer  160  is disposed on the storage electrode  125   a  and the second gate insulating layer  142 . The first insulating layer  160  may include an inorganic insulating material such as a silicon nitride, a silicon oxide, and an aluminum oxide, or may include an organic insulating material. 
     A first source electrode  173   a  connected to the first semiconductor layer  130   a  including the oxide semiconductor and a first drain electrode  175   a  connected to the first semiconductor layer  130   a  are disposed on the first insulating layer  160 . 
     The first source electrode  173   a  is connected to the first semiconductor layer  130   a  through a first contact hole  61  formed in the first insulating layer  160 , the second gate insulating layer  142 , and the first gate insulating layer  141 . The first drain electrode  175   a  is connected to the first semiconductor layer  130   a  through a second contact hole  62  formed in the first insulating layer  160 , the second gate insulating layer  142 , and the first gate insulating layer  141 . 
     The first source electrode  173   a  and the first drain electrode  175   a  may include a metal film including at least one of copper, a copper alloy, aluminum, an aluminum alloy, molybdenum, and a molybdenum alloy. The first source electrode  173   a  and the first drain electrode  175   a  may include a single layer or a multilayer according to embodiments. 
     A second insulating layer  180  is disposed on the first source electrode  173   a  and the first drain electrode  175   a . The second insulating layer  180  covers and flattens the first source electrode  173   a  and the first drain electrode  175   a . The second insulating layer  180  may include an organic insulating material or an inorganic insulating material. 
     A pixel electrode  191 , which is a first electrode, is disposed on the second insulating layer  180 . The pixel electrode  191  may be connected to the first drain electrode  175   a  through a contact hole formed in the second insulating layer  180 . 
     A partition wall  360  overlapping the second insulating layer  180  and a portion of the pixel electrode  191  is disposed on the pixel electrode  191 . The partition wall  360  has an opening  365  exposing the pixel electrode  191 . 
     The partition wall  360  may include an organic material such as a polyacrylate resin and a polyimide resin, or a siloxane-based inorganic material. 
     A light emitting layer  370 , which is a light emitting member, is disposed on the pixel electrode  191  exposed by the opening  365 . A common electrode  270  is disposed on the light emitting layer  370  and the partition wall  360 . The pixel electrode  191 , the light emitting layer  370 , and the common electrode  270  may form a light emitting diode. 
     Here, the pixel electrode  191  is an anode that is a hole injection electrode, and the common electrode  270  is a cathode that is an electron injection electrode. However, the present embodiment is not limited thereto, and the pixel electrode  191  may be a cathode and the common electrode  270  may be an anode according to a driving method of the display device. Holes and electrons are injected into the light emitting layer  370  from the pixel electrode  191  and the common electrode  270 , respectively, and excitons generated by coupling the injected holes and electrons fall from an excited state to a ground state to emit light. 
     The light emitting layer  370  may include a low molecular organic material or a polymer organic material such as poly(3,4-ethylenedioxythiophene) (PEDOT). The light emitting layer  370  may be formed as a multilayer including a light emitting layer and at least one of a hole injecting layer, a hole transporting layer, an electron transporting layer, and an electron injecting layer. When all of these are included, the hole injection layer is disposed on the pixel electrode  191 , which is an anode, and the hole transport layer, the light emitting layer, the electron transport layer, and an electron injection layer may be sequentially stacked thereon. 
     An encapsulation layer  400  for protecting the light emitting diode may be disposed on the common electrode  270 . The encapsulation layer  400  may be sealed to the substrate  110  by a sealant. The encapsulation layer  400  may be formed of various materials such as glass, quartz, ceramic, a polymer, and metal. Meanwhile, the encapsulation layer  400  may be formed by depositing an inorganic film and an organic film on the common electrode  270  without using a sealant. 
     Hereinafter, the second area PA 2  will be described. Detailed description of the constituent elements described in the first area PA 1  will be omitted. 
     The buffer layer  111  is disposed on the substrate  110  corresponding to the second area PA 2 . In addition, the first gate insulating layer  141  is disposed on the buffer layer  111 . 
     A second semiconductor layer  157   b  is disposed on the first gate insulating layer  141 . The second semiconductor layer  157   b  includes polycrystalline silicon. 
     The second semiconductor layer  157   b  includes a source region  152   b  connected to a second source electrode  173   b  to be described later, a drain region  153   b  connected to a second drain electrode  175   b  to be described later, and a channel region  151   b  disposed between the source region  152   b  and the drain region  153   b . The source region  152   b  and the drain region  153   b  are in a conductive state in which impurities are doped into polycrystalline silicon. The impurities doped into the source region  152   b  and the drain region  153   b  may be a group  5  element, and may be n+ doped. 
     The second gate insulating layer  142  is disposed on the second semiconductor layer  157   b  and the first gate insulating layer  141 . 
     A second gate electrode  124   b  is disposed on the second gate insulating layer  142 . The second gate electrode  124   b  overlaps the channel region  151   b  of the second semiconductor layer  157   b.    
     The second gate electrode  124   b  may include at least one of copper, a copper alloy, aluminum, an aluminum alloy, molybdenum, and a molybdenum alloy. 
     The first insulating layer  160  is disposed on the second gate electrode  124   b  and the second gate insulating layer  142 . 
     The second source electrode  173   b  connected to the source region  152   b  of the second semiconductor layer  157   b  and the second drain electrode  175   b  connected to the drain region  153   b  of the second semiconductor layer  157   b  are disposed on the first insulating layer  160 . 
     The second source electrode  173   b  and the source region  152   b  are connected through a third contact hole  63  formed in first insulating layer  160  and the second gate insulating layer  142 . In addition, the second drain electrode  175   b  and the drain region  153   b  are connected through a fourth contact hole  64  formed in the first insulating layer  160  and the second gate insulating layer  142 . 
     In the second area PA 2 , the second insulating layer  180 , the partition wall  360 , the common electrode  270 , and the encapsulation layer  400  may be sequentially stacked on the second source electrode  173   b  and the second drain electrode  175   b.    
     Hereinafter, a stacking relationship between the first transistor Ta disposed in the first area PA 1  and the second transistor Tb disposed in the second area PA 2  will be described. 
     The first semiconductor layer  130   a  according to some embodiments is disposed between the buffer layer  111  and the first gate insulating layer  141 . 
     The first gate electrode  154   a  and the second semiconductor layer  157   b  are disposed between the first gate insulating layer  141  and the second gate insulating layer  142 . The first gate electrode  154   a  and the second semiconductor layer  157   b  are disposed on the same layer. The first gate electrode  154   a  and the second semiconductor layer  157   b  may include the same material, and may be formed through the same manufacturing process. 
     Since the first gate electrode  154   a  may be simultaneously formed in the process of forming the second semiconductor layer  157   b , a separate gate electrode forming process is not required, and thus the manufacturing process of the display device may be simplified. 
     The first gate electrode  154   a  and the second semiconductor layer  157   b  include polycrystalline silicon. In addition, the source region  152   b  and the drain region  153   b  of the second semiconductor layer  157   b  and the first gate electrode  154   a  may include polycrystalline silicon doped with impurities. 
     The storage electrode  125   a  and the second gate electrode  124   b  are disposed between the second gate insulating layer  142  and the first insulating layer  160 . The storage electrode  125   a  and the second gate electrode  124   b  may be formed in the same process, and may include the same material. 
     The display device according to some embodiments may include the first transistor Ta including an oxide semiconductor and the second transistor Tb including polycrystalline silicon. In this case, since the first gate electrode  154   a  included in the first transistor Ta and the second semiconductor layer  157   b  included in the second transistor Tb may be formed through the same process, the manufacturing process and the stacked structure may be simplified. 
     Hereinafter, a display device according to some embodiments will be described with reference to  FIG. 2  to  FIG. 4 .  FIG. 2 ,  FIG. 3 , and  FIG. 4  illustrate a cross-sectional view of a display device according to some embodiments, respectively. A description of the same or similar constituent elements as those of the embodiments described above will be omitted. 
     First, referring to  FIG. 2 , the substrate  110  includes the first area PA 1  in which the first transistor Ta is disposed and the second area PA 2  in which the second transistor Tb is disposed. First, the first area PA 1  will be described, and then the second area PA 2  will be described. 
     The buffer layer  111  is disposed on the substrate  110  corresponding to the first area PA 1 . An insulating layer  131  is disposed on the buffer layer  111 . The insulating layer  131  may include an inorganic insulating material or an organic insulating material. 
     Next, a first semiconductor layer  157   a  is disposed on the insulating layer  131 . The first semiconductor layer  157   a  includes polycrystalline silicon. 
     The first semiconductor layer  157   a  includes a source region  152   a  connected to a first source electrode  173   a  to be described later, a drain region  153   a  connected to a first drain electrode  175   a , and a channel region  151   a  disposed between the source region  152   a  and the drain region  153   a . The source region  152   a  and the drain region  153   a  are in a conductive state in which impurities are doped. 
     The first gate insulating layer  141  is disposed on the insulating layer  131  and the first semiconductor layer  157   a.    
     A first gate electrode  124   a  is disposed on the first gate insulating layer  141 . The first gate electrode  124   a  overlaps the channel region  151   a  of the first semiconductor layer  157   a . The first gate electrode  124   a  may include at least one of copper, a copper alloy, aluminum, an aluminum alloy, molybdenum, and a molybdenum alloy. 
     A second gate insulating layer  142  is disposed on the first gate electrode  124   a  and the first gate insulating layer  141 . 
     A storage electrode  125   a  is disposed on the second gate insulating layer  142 . Although not shown in the present specification, the storage electrode  125   a  may be connected to a separate driving voltage line and the like. 
     The storage electrode  125   a  and the first gate electrode  124   a  may form a storage capacitor by overlapping each other with the second gate insulating layer  142  therebetween. 
     A first insulating layer  160  is disposed on the storage electrode  125   a  and the second gate insulating layer  142 . 
     The first source electrode  173   a  and the source region  152   a  of the first semiconductor layer  157   a  are connected through the first contact hole  61  formed in the first insulating layer  160 , the second gate insulating layer  142 , and the first gate insulating layer  141 . The first drain electrode  175   a  and the drain region  153   a  of the first semiconductor layer  157   a  are connected through the second contact hole  62  of the first insulating layer  160 , the second gate insulating layer  142 , and the first gate insulating layer  141 . 
     A second insulating layer  180  is disposed on the first source electrode  173   a  and the first drain electrode  175   a.    
     A pixel electrode  191 , which is a first electrode, is disposed on the second insulating layer  180 . The pixel electrode  191  may be connected to the first drain electrode  175   a  through a contact hole formed in the second insulating layer  180 . 
     A partition wall  360  overlapping the second insulating layer  180  and a portion of the pixel electrode  191  is disposed on the pixel electrode  191 . A light emitting layer  370 , which is a light emitting member, is disposed on the pixel electrode  191  exposed by the opening  365  included in the partition wall  360 . A common electrode  270  is disposed on the light emitting layer  370  and the partition wall  360 . The pixel electrode  191 , the light emitting layer  370 , and the common electrode  270  may form a light emitting diode. An encapsulation layer  400  for protecting the light emitting diode may be disposed on the common electrode  270 . 
     Hereinafter, the second transistor Tb disposed in the second area PA 2  will be described. 
     The buffer layer  111  is disposed on the substrate  110 , and a second semiconductor layer  130   b  is disposed on the buffer layer  111 . 
     The second semiconductor layer  130   b  according to some embodiments includes an oxide semiconductor. The oxide semiconductor may include a combination of a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), and an oxide thereof. More specifically, the oxide semiconductor may include at least one of a zinc oxide (ZnO), a zinc-tin oxide (ZTO), a zinc-indium oxide (ZIO), an indium oxide (InO), a titanium oxide (TiO), an indium-gallium-zinc oxide (IGZO), and an indium-zinc-tin oxide (IZTO). 
     The insulating layer  131  is disposed on the second semiconductor layer  130   b  and the buffer layer  111 . The insulating layer  131  may include an inorganic insulating material or an organic insulating material. A second gate electrode  154   b  is disposed on the insulating layer  131 . 
     The second gate electrode  154   b  may include polycrystalline silicon doped with impurities. The second gate electrode  154   b  is in a conductive state as impurities are doped into polycrystalline silicon. 
     The first gate insulating layer  141 , the second gate insulating layer  142 , and the first insulating layer  160  are sequentially disposed on the insulating layers  131  and the second gate electrodes  154   b.    
     A second source electrode  173   b  connected to the second semiconductor layer  130   b  and a second drain electrode  175   b  connected to the second semiconductor layer  130   b  are disposed on the first insulating layer  160 . 
     The second source electrode  173   b  may be connected to the second semiconductor layer  130   b  through the third contact hole  63 , and the second drain electrode  175   b  may be connected to the second semiconductor layer  130   b  through the fourth contact hole  64 . 
     The second insulating layer  180 , the partition wall  360 , the common electrode  270 , and the encapsulation layer  400  are sequentially disposed on the second source electrode  173   b  and the second drain electrode  175   b.    
     Hereinafter, a stacking relationship between the first transistor Ta disposed in the first area PA 1  and the second transistor Tb disposed in the second area PA 2  will be described. 
     The second semiconductor layer  130   b  is disposed between the buffer layer  111  and the insulating layer  131 . 
     The first semiconductor layer  157   a  and the second gate electrode  154   b  are disposed between the insulating layer  131  and the first gate insulating layer  141 . The first semiconductor layer  157   a  and the second gate electrode  154   b  are disposed on the same layer. The first semiconductor layer  157   a  and the second gate electrode  154   b  may include the same material, and may be formed through the same manufacturing process. 
     The first semiconductor layer  157   a  and the second gate electrode  154   b  include polycrystalline silicon. The source region  152   a  and the drain region  153   a  of the first semiconductor layer  157   a  and the second gate electrode  154   b  may include polycrystalline silicon doped with impurities. 
     Since the second gate electrode  154   b  may be simultaneously formed in the process of forming the first semiconductor layer  157   a , a separate gate electrode forming process is not required, and thus the manufacturing process may be simplified. 
     The display device according to some embodiments may include the first transistor Ta including polycrystalline silicon and the second transistor Tb including an oxide semiconductor. In this case, since the first semiconductor layer  157   a  included in the first transistor Ta and the second gate electrode  154   b  included in the second transistor Tb may be formed through the same process, the manufacturing process and the stacked structure may be simplified. 
     Hereinafter, it will be described with reference to  FIG. 3 . In  FIG. 3 , the first area PA 1  in which the first transistor Ta is disposed will be first described. 
     Referring to  FIG. 3 , the first gate electrode  154   a  is disposed on the buffer layer  111 . The first gate electrode  154   a  may include polycrystalline silicon doped with impurities. 
     A gate insulating layer  140  is disposed on the first gate electrode  154   a  and the buffer layer  111 . 
     The first semiconductor layer  157   a  is disposed on the gate insulating layer  140 . The first semiconductor layer  157   a  according to some embodiments may include an oxide semiconductor. 
     The first insulating layer  160  is disposed on the first semiconductor layer  157   a . A first source electrode  173   a  connected to a first semiconductor layer  157   a  including an oxide semiconductor through a first contact hole  61  and a first drain electrode  175   a  connected to the first semiconductor layer  157   a  through a second contact hole  62  are disposed on the first insulating layer  160 . 
     Next, the second area PA 2  in which the second transistor Tb is disposed will be described. 
     The second semiconductor layer  157   b  is disposed on the buffer layer  111  disposed on the substrate  110 . The second semiconductor layer  157   b  includes polycrystalline silicon. 
     The second semiconductor layer  157   b  includes a source region  152   b  connected to a second source electrode  173   b , a drain region  153   b  connected to a second drain electrode  175   b , and a channel region  151   b  disposed between the source region  152   b  and the drain region  153   b . The source region  152   b  and the drain region  153   b  are in a conductive state in which impurities are doped. 
     The gate insulating layer  140  is disposed on the second semiconductor layer  157   b  and the buffer layer  111 . A second gate electrode  124   b  is disposed on the gate insulating layer  140 . The second gate electrode  124   b  may overlap the channel region  151   b  of the second semiconductor layer  157   b.    
     The second gate electrode  124   b  may include a metal film including at least one of copper, a copper alloy, aluminum, an aluminum alloy, molybdenum, and a molybdenum alloy. The second gate electrode  124   b  may include a single film or multi-film according to some embodiments. 
     The first insulating layer  160  is disposed on the second gate electrode  124   b  and the gate insulating layer  140 . 
     The second source electrode  173   b  is connected to the source region  152   b  through the third contact hole  63  formed in the first insulating layer  160  and the gate insulating layer  140 . The second drain electrode  175   b  is connected to the drain region  153   b  through the fourth contact hole  64  formed in the first insulating layer  160  and the gate insulating layer  140 . 
     The first gate electrode  154   a  and the second semiconductor layer  157   b  according to some embodiments may be disposed between the buffer layer  111  and the gate insulating layer  140 . The first gate electrode  154   a  and the second semiconductor layer  157   b  are disposed on the same layer. The first gate electrode  154   a  and the second semiconductor layer  157   b  may include the same material, and may be formed through the same manufacturing process. 
     The first gate electrode  154   a  and the second semiconductor layer  157   b  include polycrystalline silicon. In addition, the source region  152   b  and the drain region  153   b  of the second semiconductor layer  157   b  and the first gate electrode  154   a  may be doped with impurities in polycrystalline silicon. 
     Since the first gate electrode  154   a  may be simultaneously formed in the process of forming the second semiconductor layer  157   b , a separate gate electrode forming process is not required, and thus a process therefor may be simplified. 
     Although the present specification shows the configuration in which the light emitting diode is connected to the first transistor Ta in  FIG. 3 , the present invention is not limited thereto, and the light emitting diode may be connected to the second transistor Tb. 
     Hereinafter, it will be described with reference to  FIG. 4 . Referring to  FIG. 4 , auxiliary metal layers  126   a  and  127   a  are disposed on the first semiconductor layer  157   a  disposed in the first area PA. The first insulating layer  160  is disposed on the auxiliary metal layers  126   a  and  127   a.    
     The first source electrode  173   a  and the first drain electrode  175   a  are disposed on the first insulating layer  160 . The first source electrode  173   a  is connected to the auxiliary metal layer  126   a  through the first contact hole  61  formed in the first insulating layer  160 . The first drain electrode  175   a  may be connected to the auxiliary metal layer  127   a  through the second contact hole  62  formed in the first insulating layer  160 . 
     The auxiliary metal layers  126   a  and  127   a  may be disposed on the same layer as the second gate electrode  124   b . The auxiliary metal layers  126   a  and  127   a  and the second gate electrode  124   b  may be disposed between the gate insulating layer  140  and the first insulating layer  160 . 
     Hereinafter, a manufacturing method of the display device according to some embodiments will be described with reference to  FIG. 5  to  FIG. 8 .  FIG. 5 ,  FIG. 6 ,  FIG. 7 , and  FIG. 8  respectively illustrate a cross-sectional view of a partial area of a display device according to a manufacturing process. 
     First, as shown in  FIG. 5 , the substrate  110  includes the first area PA 1  and the second area PA 2 . The buffer layer  111  is disposed on the entire surface of the substrate  110  so as to overlap the first area PA 1  and the second area PA 2 . In addition, the first semiconductor layer  130   a  including an oxide semiconductor is formed in the first area PA 1 . 
     Next, as shown in  FIG. 6 , the first gate insulating layer  141  overlapping the entire surface of the substrate  110  is formed on the buffer layer  111  and the first semiconductor layer  130   a.    
     The second semiconductor layer  157   b  is formed on the first gate insulating layer  141  disposed in the second area PA 2 , and the first gate electrode  154   a  is formed on the first gate insulating layer  141  disposed in the first area PA 1 . The first gate electrode  154   a  and the second semiconductor layer  157   b  are formed on the same layer. 
     The first gate electrode  154   a  and the second semiconductor layer  157   b  include polycrystalline silicon. In addition, the source region  152   b  and the drain region  153   b  of the second semiconductor layer  157   b  and the first gate electrode  154   a  may be doped with impurities in polycrystalline silicon. 
     Since the first gate electrode  154   a  may be simultaneously formed in the process of forming the second semiconductor layer  157   b , a separate gate electrode forming process is not required, and thus a process therefor may be simplified. 
     As shown in  FIG. 7 , the second gate insulating layer  142  overlapping the entire surface of the substrate  110  is formed on the first gate electrode  154   a , the second semiconductor layer  157   b , and the first gate insulating layer  141 . Then, the storage electrode  125   a  and the second gate electrode  124   b  are formed on the second gate insulating layer  142 . 
     Next, as shown in  FIG. 8 , the first insulating layer  160  overlapping the entire surface of the substrate  110  is formed. The first insulating layer  160 , the second gate insulating layer  142 , and the first gate insulating layer  141  have the first contact hole  61  and the second contact hole  62  exposing a portion of the first semiconductor layer  130   a . In addition, the first insulating layer  160  and the second gate insulating layer  142  have the third contact hole  63  exposing a portion of the source region  152   b  and the fourth contact hole  64  exposing a portion of the drain region  153   b.    
     Next, the first source electrode  173   a , the first drain electrode  175   a , the second source electrode  173   b , and the second drain electrode  175   b  are formed on the first insulating layer  160 , and then the light emitting diode connected to the first drain electrode  175   a  is formed, thereby providing the display device as shown in  FIG. 1 . 
     Hereinafter, a display device according to some embodiments will be described with reference to  FIG. 9 .  FIG. 9  illustrates an equivalent circuit diagram of one pixel of a display device according to some embodiments. 
     As shown in  FIG. 9 , one pixel PX of the display device according to some embodiments may include a plurality of transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  connected to a plurality of signal lines  151 ,  152 ,  153 ,  154 ,  155 ,  156 ,  171 , and  172 , a storage capacitor Cst, and a light emitting diode LED. Although a structure including seven transistors and one capacitor is shown in the present embodiment, the present embodiment is not necessarily limited thereto, and the number of transistors and the number of capacitors may be variously changed. 
     The transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  may include the first transistor Ta including an oxide semiconductor and the second transistor Tb including polycrystalline silicon. The first transistor Ta may include a driving transistor T 1 , a switching transistor T 2 , an operation control transistor T 5 , and a light emission control transistor T 6 . The second transistor Tb may include a compensation transistor T 3 , an initialization transistor T 4 , and a bypass transistor T 7 , but is not limited thereto. 
     The signal lines  151 ,  152 ,  153 ,  154 ,  155 ,  156 ,  171 , and  172  may include a first scan line  151 , a second scan line  152 , a third scan line  153 , an emission control line  154 , a bypass control line  155 , an initialization voltage line  156 , a data line  171 , and a driving voltage line  172 . The first scan line  151 , the second scan line  152 , the third scan line  153 , the emission control line  154 , the bypass control line  155 , the initialization voltage line  156 , the data line  171 , and the driving voltage line  172  may be connected to one pixel PX. 
     The first scan line  151  may transmit a first scan signal GW 1  to the switching transistor T 2 , the second scan line  152  may transmit a second scan signal GW 2  to the compensation transistor T 3 , and the third scan line  153  may transmit a third scan signal GI to the initialization transistor T 4 . In addition, the emission control line  154  may transmit an emission control signal EM to the operation control transistor T 5  and the emission control transistor T 6 , and the bypass control line  155  may transmit a bypass signal GB to the bypass transistor T 7 . Further, the initialization voltage line  156  may transmit an initialization voltage Vint that initializes the driving transistor T 1 . 
     The data line  171  may transmit a data signal Dm, and the driving voltage line  172  may transmit a driving voltage ELVDD. 
     A gate electrode G 1  of the driving transistor T 1  is connected to one end Cst 1  of the storage capacitor Cst, and a source electrode S 1  of the driving transistor T 1  is connected to the driving voltage line  172  via the operation control transistor T 5 . A drain electrode D 1  of the driving transistor T 1  may be electrically connected to an anode of the light emitting diode LED via the light emission control transistor T 6 . The driving transistor T 1  may receive the data signal Dm in accordance with a switching operation of the switching transistor T 2  to supply a driving current Id to the light emitting diode LED. 
     A gate electrode G 2  of the switching transistor T 2  may be connected to the first scan line  151 , a source electrode S 2  of the switching transistor T 2  may be connected to the data line  171 , and a drain electrode D 2  of the switching transistor T 2  may be connected to the source electrode S 1  of the driving transistor T 1  and may be connected to the driving voltage line  172  via the operation control transistor T 5 . The switching transistor T 2  may be turned on in response to the first scan signal GW 1  transmitted through the first scan line  151  to perform a switching operation to transmit the data signal Dm transmitted to the data line  171  to the source electrode S 1  of the driving transistor T 1 . 
     A gate electrode G 3  of the compensation transistor T 3  may be connected to the second scan line  152 , a source electrode S 3  of the compensation transistor T 3  may be connected to the drain electrode D 1  of the driving transistor T 1  and may be connected to the anode of the light emitting diode LED via the emission control transistor T 6 , and a drain electrode D 3  of the compensation transistor T 3  may be connected to the drain electrode D 4  of the initialization transistor T 4 , one end Cst 1  of the storage capacitor Cst, and the gate electrode G 1  of the driving transistor T 1 . The compensation transistor T 3  may be turned on depending on the second scan signal GW 2  transmitted through the second scan line  152  to connect the gate electrode G 1  and the drain electrode D 1  of the driving transistor T 1  to each other to diode-connect the driving transistor T 1 . According to an example, the second scan signal GW 2  is a signal in which a level of the first scan signal GW 1  is inverted, and thus, when the first scan signal GW 1  is at a high level, the second scan signal GW 2  may be at a low level, while when the first scan signal GW 1  is at a low level, the second scan signal GW 2  may be at a high level. 
     A gate electrode G 4  of the initialization transistor T 4  may be connected to the third scan line  153 , a source electrode S 4  of the initialization transistor T 4  may be connected to the initialization voltage line  156 , and a drain electrode D 4  of the initialization transistor T 4  may be connected to the one end Cst 1  of the storage capacitor Cst, the gate electrode G 1  of the driving transistor T 1 , and the drain electrode D 3  of the compensation transistor T 3 . The initialization transistor T 4  may be turned on according to the third scan signal GI transmitted through the third scan line  153  to transmit the initialization voltage Vint to the gate electrode G 1  of the driving transistor T 1  to perform an initializing operation to initialize a gate voltage Vg of the gate electrode G 1  of the driving transistor T 1 . 
     A gate electrode G 5  of the operation control transistor T 5  may be connected to the emission control line  154 , a source electrode S 5  of the operation control transistor T 5  may be connected to the driving voltage line  172 , and a drain electrode D 5  of the operation control transistor T 5  may be connected to the source electrode S 1  of the driving transistor T 1  and the drain electrode S 2  of the switching transistor T 2 . 
     A gate electrode G 6  of the emission control transistor T 6  may be connected to the emission control line  154 , a source electrode S 6  of the emission control transistor T 6  may be connected to the drain electrode D 1  of the driving transistor T 1  and the source electrode S 3  of the compensation transistor T 3 , and a drain electrode D 6  of the emission control transistor T 6  may be electrically connected to the anode of the light emitting diode LED. The operation control transistor T 5  and the emission control transistor T 6  may be simultaneously turned on according to an emission control signal EM transmitted through the emission control line  154 , thus the driving voltage ELVDD may be compensated through the diode-connected driving transistor T 1  and then may be transmitted to the light emitting diode LED. 
     A gate electrode G 7  of the bypass transistor T 7  may be connected to the bypass control line  155 , a source electrode S 7  of the bypass transistor T 7  may be connected together to the drain electrode D 6  of the emission control transistor T 6  and the anode of the light emitting diode LED, and a drain electrode D 7  of the bypass transistor T 7  may be connected together to the initialization voltage line  156  and the source electrode S 4  of the initialization transistor T 4 . 
     The other end Cst 2  of the storage capacitor Cst may be connected to the driving voltage line  172 , and the cathode of the light emitting diode LED may be connected to a driving voltage line  741  for transmitting the common voltage ELVSS. 
     While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.