Patent Publication Number: US-2007099344-A1

Title: Ultrathin leadframe BGA circuit package

Description:
This application is a Continuation of U.S. application Ser. No. 10/931,363, filed Aug. 31, 2004, which is a Divisional of U.S. application Ser. No. 10/233,159, filed Aug. 29, 2002, which claims priority under 35 U.S.C. 119 from Singapore application No. 200202330-7, filed Apr. 19, 2002, all of which are incorporated herein by reference. 
    
    
     BACKGROUND  
      Leadframes have been used to support terminals for connection to integrated circuit dies as a package is formed.  
      In some embodiments of the present invention a leadframe provides a die pad and surrounding bondpads. A die is mounted on the die pad and connections are made between the die and some of the bondpads. The support members for the bondpads and the remainder of the leadframe are positioned to lie below a reference plane defined relative to the lower surface of the die and the lower surface of the bondpads. The leadframe, die and bondpads are encapsulated in insulating material and the package is processed to remove all of the interstitial and leadframe material that lie below the reference plane. The lower surface of the resulting package has an array of bondpads adjacent the die pad. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIG. 1  is a sectional elevation view of an integrated circuit package formed according to an embodiment of the invention;  
       FIG. 2  is a view of an embodiment of a leadframe in accordance with the invention and which is constructed and arranged for assembly into a circuit package in accordance with an embodiment of the invention;  
       FIG. 3  is a detailed side elevation cross-section view showing an etching operation which may be a part of the process for preparing the leadframe for assembly of a package in accordance with an embodiment of the invention;  
       FIG. 4  is a detailed side elevation cross-section views showing a mechanical forming operation which may be a part of the process for preparing the leadframe for assembly of a package in accordance with an embodiment of the invention;  
       FIG. 5  is a side elevation cross-section view showing a an embodiment of a subassembly of a leadframe and die for use in forming an integrated circuit package in accordance with an embodiment of the invention;  
       FIG. 6  is a side elevation cross sectional view of an oversized molded integrated circuit package prior to singulation and backgrinding;  
       FIG. 7  is a cross-section elevation view of the oversized package of  FIG. 6  after removal of interstitial material and the distal support members; and  
       FIG. 8  is a flow chart of integrated circuit package forming operations in accordance with an embodiment of the present invention. 
    
    
     DESCRIPTION OF EMBODIMENTS  
      In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural changes may be made without departing from the spirit and scope of the present invention.  
      For convenience, reference has been made in the specification and claims to various surfaces as “upper” or “lower”. It is not intended that such descriptions be absolute, since repositioning of a described object to an orientation other than that shown in the attached drawings may change their classification, but not their orientation relative to each other. Thus such terms are used in a relative rather than an absolute sense.  
      The following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.  
      In  FIG. 1 , an integrated circuit package  10  carrying a semiconductor die  12  illustrates a package manufactured in accordance with an embodiment of the invention. Die  12  has its inactive, or lower, face attached to a die pad  14  by conventional die attachment or lead-on-chip (LOC) process technology for attaching a die to a die pad using adhesive or double backed tape, as known in the art. The active, or upper, surface of die  12  has on it a number of terminals or vias which connect to various points in electronic circuits within die  12 .  
      A plurality of bond pads  16  are each connected by jumper wires or conductors  18  to the terminals or vias exposed on the upper surface of die  12 . One end of a jumper wire or conductor  18  is wirebonded or otherwise conductively attached to a terminal or via on the upper surface of die  12 . The other end of conductor  18  is connected to a corresponding bond pad  16 . The die  12 , die pad  14 , jumper wires  18  and bond pads  16  together form a subassembly which may then be encapsulated in a suitable thermoplastic or thermoset material  22  to form an oversized electronic circuit package. After the lower surface of bond pads  16  is exposed as described below, solder balls  20  are applied to the lower surface of each bond pad. The solder balls  20  facilitate the connection of bond pads  16  of package  10  to circuit conductors on a motherboard or other printed circuit board providing electrical connections between die  12  and other circuits to form an electronic system.  
       FIG. 2  is a top view of a leadframe structure used in an embodiment of the invention for arranging bondpads  16  surrounding die pad  14 . In one embodiment of the invention the leadframe  24  may be etched or stamped from a single sheet of a suitable conductive material such as copper or a copper alloy. In another embodiment of the invention a further layer of material may be added to at least the die pad region  14  to facilitate its functioning as a heat spreader to conduct heat away from individual concentrations of heat on the lower surface of die  12 .  
      Etching the sheet material to manufacture the leadframe  24  may permit the creation of more complex arrangements of bond pads  16  in the open portion  23  of the leadframe  24  adjacent die pad  14 . Multiple leadframes  24  may be produced on a large sheet in the stamping or etching process and later singulated into separate leadframes  24  for use in individual packages  10  at various stages of the manufacturing process. Though the drawings in the present application illustrate the manufacture of a single integrated circuit package  10  from a single leadframe  24 , it will be appreciated by one skilled in the art that the various embodiments of the manufacturing process described herein may also be practiced on multiple packages with the singulation into individual packages occurring at several suitable places in the process after the encapsulating step described below.  
      Frame portion  26  has a plurality of support fingers  28  extending inwardly from it and supporting bond pads  16  with their proximal portion. Both frame portion  26  and support fingers  28  comprise support members for bond pads  16  prior to their encapsulation in interstitial material  22 . As shown in  FIG. 2 , according to one embodiment of the invention, bond pads  16  are arranged in multiple staggered courses or rows such as the two staggered separate courses or rows  29   a  or  29   b  surrounding die pad  14  to provide an array of staggered bond pads. It will be appreciated by those skilled in the art that a number of other staggered and aligned bond pad configuration geometries are possible and indeed, are facilitated by the flexibility of application of embodiments of the present invention.  
      Each of the support fingers  28  between the frame portion  26  and bond pad  16  has a width which may be substantially narrower than the width or length dimensions of generally rectilinearly shaped bond pads  16  or a diameter or chord of either oval, octagonal or curvilinearly shaped bond pads. When two or more staggered multiple courses  29  of bond pads  16  are arrayed adjacent a die pad  14 , the width dimension of the supporting fingers  28 , viewed in the plane of the leadframe  24 , are substantially less that the surface dimensions of bond pad  16 .  
      In preparing the leadframe  24  for carrying out the package forming methods according to an embodiment of the invention, adhesive strips  30  are applied to secure fingers  28  to a supporting substrate  32  during the assembly process. The use of adhesive strips  30  is optional and can be directly beneath bond pad  16  or nearby to provide support during the assembly process. Securing fingers  28  to substrate  32  using tape strips  30  strengthens them during the wire bonding operation used for connecting jumper wires  18  between terminals on die  12  and bond pads  16 .  
      In  FIG. 3  there is shown a detail elevation view of a bond pad  16  which is supported at the end of a finger  28  extending inwardly from leadframe frame portion  26 . In one embodiment an etching process is carried out to selectively reduce the thickness of a portion of the leadframe finger or support member  28 . In  FIG. 3 , the portion of the finger or support member  28  distal of the bond pad  16  is etched away to lower the top surface  33  of finger  28  so that the entirety of that portion of the length of finger  28  is lowered below a reference plane  37  which passes through bond pad  16  at a distance below the upper surface of bond pad  16  which is suitable for the finished height h of bond pad  16 .  
      Once the subassembly is completed and encapsulated as discussed below, the portions of leadframe  24  which are located below reference plane  37  are removed by grinding, or some other material removing operation, to leave the upper portion of bond pads  16  exposed on the lower surface of package  10 . Because the grinding removes of the material below the reference plane  37 , the portions of fingers  28  distal of the bond pads is removed, leaving the remaining portion of the bond pad supported by the interstitial material  22  with the lower face of the bond pad  16  exposed for receiving solder balls  20  or solder for connection the terminals of the package  1 —to conductors on a some printed circuit board to allow the package to become part of an electronic system.  
      In  FIG. 4  there is shown a detail elevation view of a bond pad  16  which is at the end of a support finger  28  extending inwardly from the perimeter portion  26  of the leadframe. The fingers  28  are mechanically formed so as to separate the reference plane  37  defined by the lower surface  38  of bond pads  16  away from the surface of substrate  32  before fingers  28  are secured to substrate  32  with tape  30 .  
       FIG. 5  shows an elevation view of the package with die  12  attached to die pad  14  and elevated above the taped portions of fingers  28  which are secured to substrate  32 . In  FIG. 5 , bond pad  16   a  is shown extending from and therefore, electrically connected to die pad  14  to provide a connection to exterior circuits for the ground plane provided by die pad  14 . Other bond pads  16  are generally not connected to die pad  14  by fingers  28  of leadframe  24 .  
       FIG. 6  also shows the jumper wires or conductors  18  which have their ends wirebonded respectively to bond pads  16  and to terminals on the active surface of die  12 . In one embodiment, the wirebonding process is preferably carried out while portions of the length of fingers  28  remain taped to substrate  32  to increase the resistance to bending and damage of the thin leadframe during the wirebonding process.  
       FIG. 6  illustrates package  10  following molding of the subassembly into an oversized molded structure by encapsulating the subassembly in a suitable interstitial material  22  which may be a thermosetting plastic or other readily moldable material as is commonly used in the art. The oversized molded structure contains the taped portions of fingers  28 . Once the intyerstitial material  22  has cured ior otherwise solidified, the package may then be singulated to reduce it to an oversized single die package that is then ground and further singulated to the final sized package  10  shown in cross section in  FIG. 7 . The grinding may be performed by backgrinding or surface grinding machines as are presently used for the surface grinding of semiconductor wafers.  
      In the package of  FIG. 7 , the lower surfaces  72  of bond pads  16  are exposed as a part of the backgrinding process and the portions of fingers  28  distal of the bond pads  16  were removed along with tape  30  and the remainder of the surrounding support frame portion  26  of leadframe  24 . Addition of solder balls  20  to the freshly exposed, recently ground, lower faces of bond pads  16  completes the manufacture of the package  10  to the configuration shown in  FIG. 1 .  
       FIG. 9  is a flow chart of the manufacturing operations that may be followed in manufacturing a die package according to an embodiment of the present invention. In the portion of the process of block  91  the leadframe is formed with a lower surface thereof defining a reference plane. The leadframe support members are positioned below the reference plane in a further operation  92 . In a further operation  93  the die is mounted on the die pad with the body of the die positioned above the die pad. In a further operation  94  some of the bond pads are connected to terminals on the die. The die and leadframe are then encapsulated with interstitial material in operation  95 . In the final block  96  the distal support members and interstitial material lying below the reference plane are removed by grinding, etching or some other material removal process.  
      It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art after reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.