Patent Publication Number: US-9853450-B2

Title: Power factor corrector power sharing

Description:
BACKGROUND 
     Power factor correction is utilized in power transmission systems to reduce transmission losses and improve voltage regulation at a load. Some loads receive power from redundant power supplies having redundant power factor correctors and corresponding redundant output converters. The redundant output converters consume valuable space, reducing power density. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic illustration of an example power factor correction power-sharing system. 
         FIG. 2  is a schematic illustration of an implementation of the power factor correction power-sharing system of  FIG. 1 . 
         FIG. 3  is a flow diagram of an example method that may be carried out by the system of  FIG. 1 . 
         FIG. 4  is a schematic illustration of an example implementation of the power factor correction power-sharing system of  FIG. 1 . 
         FIG. 5  is a diagram of an example implementation of the power factor correction power-sharing system of  FIG. 4 . 
         FIG. 6  is a flow diagram of an example method that may be carried out by the system of  FIG. 5 . 
         FIG. 7  is a diagram of an example alternating current (AC) cycle for AC power sources of the system of  FIG. 5 . 
         FIG. 8  is a truth table for example control of transistors of a power-sharing manager of the system of  FIG. 5 . 
         FIG. 9  is an expanded truth table for example control of transistors of a power-sharing manager of the system of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS 
       FIG. 1  schematically illustrates an example power factor correction power-sharing system  20 . As will be described hereafter, system  20  facilitates sharing of power from non-isolated power factor corrector converters (power factor correctors). With such power factor correction, voltages are also stepped down. System  20  facilitates use of smaller power conversion components or the elimination of power conversion components to conserve valuable space and increase power density. System  20  comprises power factor corrector  22 , power factor corrector  24  and power-sharing manager  26 . 
     Power factor corrector  22  comprises an active power factor corrector for use with alternating current (AC) power source  27 . Power factor corrector  24  comprises an active power factor corrector for use with AC power source  28 , wherein power sources  27 ,  28  have at least one line or neutral in common. Power factor correctors  22  and  24  each rectify the alternating current being received and provide power factor correction. Power factor correctors  22  and  24  shape current and maintain an output voltage. In one implementation, each of power factor correctors  22 ,  24  comprises a boost converter. In other implementations, each of power factor correctors  22 ,  24  may comprise other power factor correctors such as a buck-boost power factor correction converter and a buck power factor correction converter. Each of power factor correctors  22  and  24  are electrically connected in parallel to power-sharing manager  26 . 
     Power-sharing manager  26  transmits power from power factor correctors  22  and  24 , in an alternating manner, to load  30 . As shown by  FIG. 2 , in one implementation, load  30  may comprise a power/energy consuming device  32 , such as an enterprise-level server, that receives the power through an output converter  34  sometimes referred to as a switch mode converter) that is electrically connected to power-sharing manager  26 . In such an implementation, the output converter  34  provides electrical isolation and produces a desired output voltage (tightening the output voltage range) to satisfy the voltage range of the power/energy consuming device  32 . In other implementations, load  30  may omit the output converter  34 . 
     In addition to alternately transmitting power from power factor corrector  22  and  24  to load  30 , power-sharing manager  26  steps down voltage from power factor correctors  22  and  24  and inhibits electrical current circulation between power factor correctors  22  and  24 . Power-sharing manager  26  inhibits electrical current circulation from power factor corrector  22  to power factor corrector  24  and inhibits electrical current circulation from power factor corrector  24  to power factor corrector  22  to facilitate the alternating supply of power from power factor correctors  22  and  24  to a single load  30  without cross circulating currents. Because power-sharing manager  26  steps down voltage and shares power from two different power factor correctors  22 ,  24  to a single load  30  with a single output converter  34  or no output converter between power-sharing manager  26  and the load  30  (rather than utilizing two output converters—an output converter between the load and each power factor corrector), power-sharing manager  26  facilitates the elimination of at least one output converter. As a result, power-sharing system  20  conserves valuable printed circuit board real estate or space and facilitates the use of lower voltage, less costly power transmission components. Power-sharing system  20  facilitates intelligent management to provide sharing and fault protection while maintaining high efficiency. 
       FIG. 3  is a flow diagram of an example method  100  that may be carried out by power factor correction power-sharing system  20 . As indicated by step  102 , power-sharing manager  26  alternately transmits power to load  30  from power factor corrector  22  and power factor corrector  24 . As indicated by step  104 , power-sharing manager  26  inhibits current circulation between power factor corrector  22  and power factor corrector  24 . 
       FIG. 4  schematically illustrates power factor correction power-sharing system  120 , an example implementation of system  20 . System  120  is similar to system  20  except that system  120  is specifically illustrated as comprising power factor correctors  122 ,  124  and power-sharing manager  126  in place of power factor correctors  22 ,  24  and power-sharing manager  26 , respectively. Power factor correctors  122  and  124  each comprise boost power converters. Power factor corrector  122  comprises a boost power converter for use with AC power source  27  to receive power/energy from AC power source  27 . Power factor corrector  124  comprises a boost power converter for use with AC power source  28  to receive power/energy from AC power source  28 . As noted above, AC power sources  27 ,  28  have at least one line or neutral in common with one another. 
     Power-sharing manager  126  comprises dual input buck converter  134  and controller  136 . Dual input buck converter  134  steps down the voltage being transmitted to load  30 . Dual input buck converter  134  comprises a pair of transistors  138 ,  140  (or other switching devices) by which electrical current from boost converters  122 ,  124  is selectively supplied to load  30 . Controller  136  actuates the pair of transistors  138 ,  140  of the dual input buck  134  to inhibit electrical current circulation between power factor correctors  122  and  124 . 
     In one implementation, controller  136  comprises one or more processing units. For purposes of this application, the term “processing unit” shall mean a presently developed or future developed processing unit that executes sequences of instructions contained in a memory. Execution of the sequences of instructions causes the processing unit to perform steps such as generating control signals. The instructions may be loaded in a random access memory (RAM) for execution by the processing unit from a read only memory (ROM), a mass storage device, or some other persistent storage. In other implementations, controller  136  may comprise hard wired circuitry that may be used in place of or in combination with software instructions to implement the functions described. For example, controller  36  may be embodied as part of one or more application-specific integrated circuits (ASICs). Unless otherwise specifically noted, a “controller” is not limited to any specific combination of hardware circuitry and software, nor to any particular source for the instructions executed by the processing unit. 
     As with power-sharing manager  26 , power-sharing manager  126  inhibits electrical current circulation from power factor corrector  122  to power factor corrector  124  and inhibits electrical current circulation from power factor corrector  124  to power factor corrector  122  to facilitate the alternating supply of power from power factor correctors  122  and  124  to a single load  30  without cross circulating currents. Because power-sharing manager  126  steps down voltage and shares power from two different power factor correctors  122 ,  124  to a single load  30  with a single output converter or no output converter (rather than utilizing two output converters—an output converter between the load and each of the two power factor correctors), power-sharing manager  126  facilitates the elimination of at least one output converter. As a result, power-sharing system  120  conserves valuable printed circuit board real estate or other space (allowing additional components such as hard drives, memory and the like) and facilitates the use of lower voltage, less costly power transmission components. Power-sharing system  120  facilitates intelligent management to provide sharing and fault protection while maintaining high efficiency. 
       FIG. 5  is a diagram illustrating power factor correction power-sharing system  220 , an example implementation of system  20  or system  120 . System  220  comprises power factor corrector  222 , power factor corrector  224  and power-sharing manager  226 . Power factor corrector  222  comprises an active power factor corrector for use with alternating current (AC) power source  27 . Power factor corrector  224  comprises an active power factor corrector for use with AC power source  28 , wherein power sources  27 ,  28  have at least one line or neutral in common. Power factor correctors  222  and  224  are each electrically connected in parallel to power-sharing manager  226 . Power factor correctors  222  and  224  rectify AC input and provide power factor correction. Power factor correctors  222  and  224  comprise rectifiers  250 ,  254  and boost converters  256 ,  258 , respectively. 
     Rectifiers  250 ,  254  rectify AC current received from AC power sources  27  and  28 , respectively. Rectifiers  250 ,  254  each comprise full bridge rectifiers, each bridge rectifier including four diodes  264 . Although each of power factor correctors  222 ,  224  is illustrated comprising a full bridge rectifier, in other implementations, power factor correctors  222 ,  224  may comprise bridgeless power factor boost converters or may use other rectifier technology such as active rectifiers. 
     Boost converters  256 ,  258  comprise DC-to-DC power converters having an output voltage greater than an input voltage. Boost converters  256 ,  258  provide power factor correction, providing a higher power factor. In particular, boost converters  256 ,  258  comprise active power factor correctors that change the wave shape of current being drawn from AC sources  26  and  28  such that the input currents more closely match to a purely resistive load. 
     Boost converters  256 ,  258  are located between bridge rectifiers  250 ,  254  and power-sharing manager  226 . In the example illustrated, boost converter  256 ,  258  comprise inductors  268  (L 1 ),  270  (L 2 ), boost transistors  272  (Q 1 ),  274  (Q 2 ), diodes  276  (D 1 ),  278  (D 2 ) and capacitances  280  (C 1 ) and  282  (C 2 ), respectively. In the example illustrated, each of transistors  272 ,  274  comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) transistor additionally provided with an anti-parallel diode  282 . In other implementations, transistors  272 ,  274  may comprise other forms of transistors such as insulated-gate bipolar transistor (IGBT) or bipolar junction transistor (BJT) transistors. In other implementations, anti-parallel diodes  282  may be omitted. 
     Power-sharing manager  226  transmits power from power factor correctors  222  and  224 , in an alternating manner, to load  30 . Power-sharing manager  226  comprises dual input buck converter  334  and controller  336 . Dual input buck converter  334  steps down voltage being transmitted to load  30  and controls the transmission of power to load  30  from either power factor corrector  222  or power factor corrector  224 . Dual input buck converter  334  comprises capacitance  340 , inductor  342 , diode  344 , diode  346  (D 3 ), diode  348  (D 4 ), transistor  350  (Q 3 ) and transistor  352  (Q 4 ). Inductor  342  is electrically connected to capacitor  340  on a first side of capacitor  340 . Diode  344  is electrically connected between the second side of capacitor  340  and inductor  342 , wherein inductor  342  is electrically connected between diode  344  and capacitance  340 . Diode  346  is electrically connected between a positive output of active power factor corrector  222  and a node  356  between diode  344  and inductor  342  with its anode connected to the positive output of power factor corrector  222  and its cathode connected to node  356 . Diode  348  is electrically connected between a positive output of active power factor corrector  224  and node  356  with its anode connected to the positive output of power factor corrector  224  and its cathode connected to node  356 . Transistor  350  is located between a return of active power factor corrector  222  and the second side of capacitance  340 . Transistor  352  is located between a return of active power factor corrector  224  and the second side of capacitance  340 . In the example illustrated, each of transistors  350 ,  352  comprise MOSFET transistors having associated anti-parallel diodes  360 . In other implementations, transistors  350  (Q 3 ),  352  (Q 4 ) may comprise other forms of transistors and/or may omit such anti-parallel diodes  360 . 
     Controller  336  generates control signals to selectively open and close transistors  350  (Q 3 ),  352  (Q 4 ) so as to inhibit electrical current circulation between power factor correctors  222  and  224 , wherein when a transistor is “closed” the transistor (switch) is on and conducting electrical current. Controller  336  opens and closes each of transistors  350 ,  352  based upon (A) the status of the other of transistors  350 ,  352 , (B) the status of the boost converter transistors  272  (Q 1 ),  274  (Q 2 ) (“Type  1  circulation”); (C) a determined phase relationship of AC power sources  27 ,  28  to an output potential or bulk regulation for each of the active power factor correctors  222 ,  224  (“Type  2 ” circulation). In the example illustrated, controller  336  receives data signals  364 ,  366  indicating the status (closed or open) of transistors  272 ,  274 , respectively. In the example illustrated, controller  336  receives zero crossings signals from zero crossing sensors  368 ,  370  indicating zero crossings of the AC cycle for each of AC power sources  27 ,  28 . Based upon such a zero crossing signals controller  336  determines the phase relationship of the AC power sources  27 ,  28  to the output potential or bulk regulation for each of the active power factor correctors  222 ,  224 . In other implementations, controller  336  may determine the phase relationship of the AC power sources to the output potential or bulk regulation for each of the active power factor correctors  222 ,  224  in other fashions. In implementations where a potential between the AC power sources  27 ,  28  cannot exceed the output potential of each active power factor correctors  222 ,  224 , consideration of or control based upon the Type  2  circulation may be omitted. 
       FIG. 6  is a flow diagram of an example method  400  for controlling transistors  350  (Q 3 ),  352  (Q 4 ) of the dual input buck converter  334  to supply power to a load  30  alternately from power factor correctors  222 ,  224  while inhibiting current circulation between power factor correctors  222 ,  224 . As indicated by step  402 , controller  336  receives or utilizes signals  364 ,  366  indicating the status of transistors  272  (Q 1 ) and  274  (Q 2 ). As indicated by step  404 , controller  336  determines the region or momentary phase relationship between AC power sources  27 ,  28 . In implementations where a potential between the AC power sources  27 ,  28  cannot exceed the output potential of each active power factor correctors  222 ,  224 , consideration of or control based upon the Type  2  circulation pertaining to Regions B and C may be omitted in steps  406  and  408 . 
       FIG. 7  illustrates an example AC cycle for AC power sources  27 ,  28  and their phase relationship. Line  500  illustrates an example sinusoidal waveform of power from AC power source  27  (for example, line  1  to neutral (N) in a three-phase power source). Similarly, line  502  illustrates an example sinusoidal waveform of power from AC power source  28  (for example, line  2  to neutral (N) in a three-phase power source). Line  508  illustrates the aggregate phase relationship (for example, line  1 -line  2  in the three-phase power source). Lines  510  and  512  are reference lines illustrating the times of the AC cycle when the input potential of the AC power sources  27 ,  28  exceeds the output potential of the power factor correctors  222 ,  224 . Region  514  (Region B) represents the period of time during which the difference or potential between AC power sources  26  and  28  (AC 1 -AC 2 ) exceeds the output potential of power factor corrector  224 . Region  516  (Region C) represents a period of time during which the difference or potential between AC power sources  26  and  28  (AC 2 -AC 1 ) exceeds the output potential of power factor corrector  222 . Using the zero cross signals received from sensors  368 ,  370  and the predetermined or established sinusoidal waveform characteristics for power provided by AC power source  27  and AC power source  28 , controller  336  determines whether or not system  220  is currently and momentarily subject to “Type  2 ” circulation in region  514  or region  516 . 
     As indicated by step  406  and further represented by the truth tables of  FIGS. 8 and 9  (where “X” indicates that the state is irrelevant), controller  336  closes transistor  350  (Q 3 ) to transmit power to load  30  from power factor corrector  222  if transistor  274  (Q 2 ) is closed, if transistor  352  (Q 4 ) is open and if system  220  is not in region B. As indicated by step  408  and further represented by the truth tables of  FIGS. 8 and 9 , controller  336  closes transistor  352  (Q 4 ) to transmit power to load  30  from power factor corrector  224  if transistor  272  (Q 1 ) is closed, if transistor  350  (Q 3 ) is open and if system  220  is not in region C. 
     In operation, power-sharing manager  226  allows sharing of power from non-isolated power factor correctors  222  and  224  under all conditions including separate phase, line-to neutral inputs. Diodes  276  and  278 , which double as boost diodes, block sneak electrical current paths or electrical circulation through boost transistors  272  and  274  when such transistors are closed. Transistors  350  (Q 3 ) and  352  (Q 4 ) block sneak electrical current paths from a power factor corrector PFCn through capacitance Cn. Diode  348  (D 4 ) blocks the sneak electrical current path from power factor corrector  222  through capacitance  282  (C 2 ). Diode  346  (D 3 ) blocks the sneak electrical path from power factor corrector  224  through capacitance  280  (C 1 ). Diodes  346  and  348  further provide fault isolation for power factor corrector faults. Because the switching of transistors  350 ,  352  is managed during Type  2  circulation conditions, system  220  blocks sneak electrical paths through capacitance  280 , capacitance  340 , transistor  350 , transistor  352  and diode  278  by opening transistor  352  (Q 4 ) when line to line voltage (AC 1 -AC 2 ) is greater than the output potential of power factor corrector  222  (capacitance  280 ) and further blocks sneak electrical paths through capacitance  282 , capacitance  340 , transistor  352 , transistor  350  and diode  276  by opening transistor  350  (Q 3 ) when line to line voltage (AC 2 -AC 1 ) is greater than the output potential of power factor corrector  224  (capacitance  282 ). 
     Although the present disclosure has been described with reference to example embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the claimed subject matter. For example, although different example embodiments may have been described as including one or more features providing one or more benefits, it is contemplated that the described features may be interchanged with one another or alternatively be combined with one another in the described example embodiments or in other alternative embodiments. Because the technology of the present disclosure is relatively complex, not all changes in the technology are foreseeable. The present disclosure described with reference to the example embodiments and set forth in the following claims is manifestly intended to be as broad as possible. For example, unless specifically otherwise noted, the claims reciting a single particular element also encompass a plurality of such particular elements.