Patent Publication Number: US-2017365395-A1

Title: 3d spiral inductor

Description:
BACKGROUND 
     Technical Field 
     The present invention relates to a 3D spiral inductor, especially relates to a miniaturized 3D spiral inductor embedded in a dielectric layer. 
     Description of Related Art 
       FIG. 1  shows a prior art 
       FIG. 1  is US 2015/0303888 A1, which shows a schematic view of a semiconductor device with an LC resonant circuit, which includes an insulation layer  110 , an inductor component  130 , and a capacitor component  150 . The inductor component  130  and the capacitor component  150  are formed by patterning two metal layers located on two opposite surfaces of the first insulation layer  110 . The inductor component  130  and the capacitor component  150  are electrically coupled with each other through vias  194 . 
     The disadvantage for the prior art is that it disclosed a flat inductor. A size of the planar inductor is limited due to its winding on a flat surface. Further, the diameter of each winding is smaller and smaller due to its snail winding on a flat surface. A size-flexible spiral inductor needs to be developed for matching various design choice. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a prior art. 
         FIGS. 2A ˜ 2 E show different views for a first embodiment according to the present invention. 
         FIG. 3  shows an inductor equivalent to the first embodiment. 
         FIGS. 4A ˜ 4 E show a second embodiment according to the present invention. 
         FIG. 5  shows an inductor equivalent to the second embodiment. 
         FIGS. 6A ˜ 6 D show a fabrication process for making a 3D spiral inductor of the first embodiment. 
         FIGS. 7A ˜ 7 F show a fabrication process for making a 3D spiral inductor of the second embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIGS. 2A ˜ 2 E show different views for a first embodiment according to the present invention. 
       FIG. 2A  shows a top view of the first embodiment. 
       FIG. 2A  shows a top view of an inductor which comprises a plurality of top metal pads in a matrix of 2×N.  FIG. 2A  shows the top metal pads being in a matrix of 2×3, as an example, formed on a top surface of a dielectric layer  20 . The matrix comprises a plurality of left metal pads L 11 , L 21 , L 31  and a plurality of right metal pads R 11 , R 21 , R 31 . 
     A plurality of top metal wires T 1 , T 2  . . . , configured in parallel and diagonally. The top first metal wire T 1  connects left first metal pads L 11  and right second metal pad R 21 . A top second metal wire T 2  connects the left second metal pad L 21  and right third metal pad R 31 . 
     The right first metal pad R 11  functions as a first terminal of the inductor, and the left third metal pad L 31  functions as a second terminal of the inductor. 
       FIG. 2B  shows a section view of  FIG. 2A  according to line AA′. 
       FIG. 2B  shows a plurality of left metal vias L 1 , L 2 , L 3 , and a plurality of right metal vias R 1 , R 2 , R 3 . 
     Both the left metal vias and the right metal visa are all coelevationally embedded in the same dielectric layer  20 . Each metal via L 1 , L 2 , L 3 , R 1 , R 2 , R 3  has the corresponding top metal pad L 11 , L 21 , L 31 , R 11 , R 21 , R 31  respectively configured on its top. 
       FIG. 2B  shows a bottom second metal wire B 2  electrically coupled to bottom ends of the left second metal via L 2  and the right second metal via R 2 . 
       FIG. 2C  shows a bottom view of the first embodiment. 
       FIG. 2C  shows a plurality of bottom metal wires B 1 , B 2 , B 3  configured in parallel and latitudinally. The plurality of bottom metal wires B 1 , B 2 , B 3  are embedded in the dielectric layer  20 . 
     The bottom first metal wire B 1  is electrically coupled to bottom ends of the left first metal via L 1  and the right first metal via R 1 . 
     The bottom second metal wire B 2  is electrically coupled to bottom ends of the left second metal via L 2  and the right second metal via R 2 . 
     The bottom third metal wire B 3  is electrically coupled to bottom ends of the left third metal via L 3  and right third metal via R 3 . 
       FIG. 2D  shows a 3D spiral inductor for the first embodiment according to the present invention. 
       FIG. 2D  shows a 3D spiral inductor for the first embodiment, referring to  FIGS. 2A-2C , the 3D spiral inductor is further drawn as shown in  FIG. 2D  in a 3D view without showing dielectric layer  20 . In other words,  FIG. 2D  is a perspective view of the first embodiment according to the present invention. 
       FIG. 2D  shows a 3D spiral inductor formed by a connection of metal elements R 1 -B 1 -L 1 -T 1 -R 2 -B 2 -L 2 -T 2 -R 3 -B 3 -L 3  in a 3D view. 
       FIG. 2E  shows virtual planes VP 1 ˜VP 5 . 
       FIG. 2E  shows virtual planes VP 1 ˜VP 5  to assist describing the structure of the first embodiment. The right first metal via R 1 , bottom first metal B 1 , and left first metal via L 1  are configured coplanarly in a first virtual plane VP 1 . 
     The left first metal via L 1 , top first metal wire T 1 , and right second metal via R 2  are configured coplanarly in a second virtual plane VP 2 . 
     The right second metal via R 2 , bottom second metal wire B 2 , and left second metal via L 2  are configured coplanarly in a third virtual plane VP 3 . 
     The left second metal via L 2 , top second metal wire T 2 , and right third metal via R 3  are configured coplanarly in a fourth virtual plane VP 4 . 
     The right third metal via R 3 , bottom third metal wire B 3 , and left third metal via L 3  are configured coplanarly in a fifth virtual plane VP 5 . 
       FIG. 3  shows an inductor equivalent to the first embodiment. 
       FIG. 3  shows a traditional discrete 3D spiral inductor  300  which is theoretically equivalent to the first embodiment, the top end of the 3D spiral inductor  300  is a first terminal equivalent to left third metal pad L 31  of the first embodiment ( FIG. 2A ). The bottom end of the 3D spiral inductor  300  is a second terminal equivalent to right first metal pad R 11  of the first embodiment ( FIG. 2A ). The 3D spiral inductor is now miniaturized and realized by metal elements R 1 -B 1 -L 1 -T 1 -R 2 -B 2 -L 2 -T 2 -R 3 -B 3 -L 3  embedded in the dielectric layer  20  according to the first embodiment according to the present invention. 
       FIGS. 4A ˜ 4 E show a second embodiment according to the present invention. 
       FIG. 4A  shows a top view of the second embodiment. 
       FIG. 4A  is the same as  FIG. 2A , and is therefore omitted to describe for simplification of the specification. 
       FIG. 4B  shows a section view of  FIG. 4A  according to line BB′. 
       FIG. 4B  shows a magnetic core  25  extended along a center axis of the 3D spiral inductor. The dielectric layer comprising a top section dielectric layer  202  and a bottom section dielectric layer  201 . The magnetic core  25  is configured on a top surface of the bottom section  201  of the dielectric layer. 
       FIG. 4C  shows a bottom view of the second embodiment. 
       FIG. 4C  is the same as  FIG. 2C  and is therefore omitted to describe for simplification of the specification. 
       FIG. 4D  shows a 3D spiral inductor for the second embodiment according to the present invention. 
       FIG. 4D  shows a magnetic core  25  extended along a center axis of the 3D spiral inductor.  FIG. 4D  shows a 3D spiral inductor of the second embodiment formed in a 3D view without showing dielectric layer  20 . In other words,  FIG. 4D  is a perspective view of the second embodiment according to the present invention. 
       FIG. 4D  shows a 3D spiral inductor formed by a connection of metal elements R 1 -B 1 -L 1 -T 1 -R 2 -B 2 -L 2 -T 2 -R 3 -B 3 -L 3  in a 3D view. 
       FIG. 4E  shows virtual planes VP 1 ˜VP 5 . 
       FIG. 4E  is the same as  FIG. 2E , and is therefore omitted to describe for simplification of the specification. 
       FIG. 5  shows an inductor equivalent to the second embodiment. 
       FIG. 5  shows a traditional discrete magnetic cored 3D spiral inductor  500  which is theoretically equivalent to the second embodiment, the top end of the 3D spiral inductor  500  is a first terminal equivalent to left third metal pad L 31  of the second embodiment ( FIG. 4A ). The bottom end of the 3D spiral inductor  500  is a second terminal equivalent to right first metal pad R 11  of the second embodiment ( FIG. 4A ). The centered black magnetic core is equivalent to the magnetic core  25  of the second embodiment ( FIG. 4A ). The 3D spiral inductor is now miniaturized and realized by metal elements R 1 -B 1 -L 1 -T 1 -R 2 -B 2 -L 2 -T 2 -R 3 -B 3 -L 3  embedded in the dielectric layers  201 ,  202  according to the second embodiment ( FIG. 4B ). 
       FIGS. 6A ˜ 6 D show a fabrication process for making a 3D spiral inductor of the first embodiment. 
       FIG. 6A  shows: 
     preparing a temporary carrier  29  with a release layer (not shown) on top surface of the temporary carrier  29 ; 
     forming a plurality of bottom metal wires B 1 , B 2 , B 3  on top of the release layer (not shown); 
       FIG. 6B  shows: 
     forming a dielectric layer  20  on a top side of the plurality of bottom metal wires B 1 ˜B 3 ; 
       FIG. 6C  shows: 
     etching the dielectric layer  20  to form a plurality of vias  22  in a matrix of 2×N; 
       FIG. 6D  shows: 
     filling metal in each via  22  to form a plurality of metal vias L 1 ˜L 3 , R 1 ˜R 3 , forming a plurality of metal pads L 11 , L 21 , L 31 , R 11 , R 21 , R 31  and forming a plurality of top metal wires T 1 , T 2  on a top surface of the dielectric layer  20 ; each metal pad is configured on a top end of each corresponding metal via L 1 -L 3 , R 1 -R 3 ; and detaching the temporary carrier  29 . 
       FIGS. 7A ˜ 7 F show a fabrication process for making a 3D spiral inductor of the second embodiment. 
       FIG. 7A  shows: 
     preparing a temporary carrier  29  with a release layer (not shown) on top surface of the temporary carrier  29 ; 
     forming a plurality of bottom metal wires B 1 , B 2 , B 3  on top of the release layer (not shown); 
       FIG. 7B  shows: 
     forming a first dielectric layer  201  on a top side of the plurality of bottom metal wires B 1 ˜B 3 ; 
       FIG. 7C  shows: 
     forming a magnetic core  25  on a top side of the first dielectric layer  201 ; 
       FIG. 7D  shows: 
     forming a second dielectric layer  202  on a top side of the magnetic core  25 ; 
       FIG. 7E  shows: 
     etching the first dielectric layer  201  and second dielectric layer  202  to form a plurality of vias  22  in a matrix of 2×N; 
       FIG. 7F  shows: 
     filling metal in each via  22  to form a plurality of metal vias L 1 ˜L 3 , R 1 ˜R 3 ; forming a plurality of metal pads L 11 , L 21 , L 31 , R 11 , R 21 , R 31  and forming a plurality of top metal wires T 1 , T 2  on a top surface of the dielectric layer  20 ; each metal pad is configured on a top end of each corresponding metal via L 1 ˜L 3 , R 1 ˜R 3 ; and detaching the temporary carrier  29 . 
     While several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be configured without departs from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims. 
     NUMERICAL SYSTEM 
       
     
       
         
           
               
               
             
               
                   
                   
               
             
            
               
                   
                 dielectric layer 20, 201, 202 
               
               
                   
                 magnetic core 25 
               
               
                   
                 spiral inductor 300, 500 
               
               
                   
                 bottom metal wires B1, B2, B3 
               
               
                   
                 left metal via L1, L2, L3 
               
               
                   
                 left metal pads L11, L21, L31 
               
               
                   
                 right metal via R1, R2, R3 
               
               
                   
                 right metal pads R11, R21, R31 
               
               
                   
                 top metal wires T1, T2 
               
               
                   
                 virtual plane VP1~VP5