Patent Publication Number: US-2023140914-A1

Title: Method for manufacturing semiconductor element, semiconductor element body, and semiconductor element substrate

Description:
TECHNICAL FIELD 
     The present disclosure relates to a method for manufacturing a semiconductor element, a semiconductor element body, and a semiconductor element substrate. 
     BACKGROUND OF INVENTION 
     In a known technique, after a growth mask including a plurality of openings is formed on a GaN substrate, a plurality of island-shaped GaN-based semiconductor layers grown from the GaN substrate and extending on the growth mask are formed, and then the GaN-based semiconductor layers are peeled from the GaN substrate (e.g., see Patent Document 1 below). 
     Patent Document 1 discloses a technique of providing a spacer at the outer periphery of a bonding surface when GaN semiconductor layers, which are formed by epitaxial lateral overgrowth (ELO) of an underlying substrate, and a support substrate are bonded together. 
     CITATION LIST 
     Patent Literature 
     Patent Document 1: JP 2013-251304 A 
     SUMMARY 
     In the present disclosure, a method for manufacturing a semiconductor device includes: forming a mask layer on an underlying substrate, the mask layer including a first mask portion in which two opening portions adjacent to each other are located spaced apart by a predetermined first interval and a second mask portion in which two opening portions adjacent to each other are located spaced apart by a predetermined second interval larger than the first interval; forming a semiconductor element by growing a semiconductor layer on the mask layer; preparing a support substrate including a bonding surface, the bonding surface facing the underlying substrate; bonding together an upper surface of the semiconductor element and the bonding surface of the support substrate; and peeling the semiconductor element formed on the mask layer from the underlying substrate. 
     In the present disclosure, a semiconductor element body includes: a first semiconductor element layer formed on a growth surface of an underlying substrate and having a predetermined first height dimension in a direction perpendicular to the growth surface; a second semiconductor element layer formed on the growth surface of the underlying substrate and having a predetermined second height dimension higher than the first height dimension; and a support substrate including a bonding surface bonded to an upper surface of the second semiconductor element layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a cross-sectional view illustrating a configuration of a semiconductor element body according to a first embodiment of the present disclosure. 
         FIG.  2    is a cross-sectional view illustrating a portion of the semiconductor element body as viewed from a cross-sectional plane line II-II in  FIG.  1   . 
         FIG.  3    is a process diagram for describing basic manufacturing procedures of a method for manufacturing a semiconductor element. 
         FIGS.  4 A to  4 C  are each a cross-sectional view illustrating an element forming step according to the first embodiment. 
         FIG.  5    is a photograph of a semiconductor element layer formed on an underlying substrate. 
         FIG.  6    is a graph showing an inclination of an upper surface of the semiconductor element layer. 
         FIG.  7    is a cross-sectional view illustrating a preparing step according to the first embodiment. 
         FIGS.  8 A and  8 B  are each a cross-sectional view illustrating a bonding step according to the first embodiment. 
         FIG.  9    is a cross-sectional view illustrating a peeling step according to the first embodiment. 
         FIGS.  10 A to  10 C  are each a cross-sectional view illustrating an element forming step for a semiconductor element body according to a second embodiment of the present disclosure. 
         FIG.  11    is a cross-sectional view illustrating a configuration of a semiconductor element body according to a third embodiment of the present disclosure. 
         FIG.  12    is a cross-sectional view of the semiconductor element body as viewed from a cross-sectional plane line XII-XII in  FIG.  11   . 
         FIG.  13    is a cross-sectional view illustrating a method for manufacturing a semiconductor element according to a fourth embodiment. 
         FIG.  14    is a plan view illustrating a configuration example of a mask layer according to the fourth embodiment. 
         FIG.  15    is a plan view illustrating another configuration of the mask layer according to the fourth embodiment. 
         FIG.  16    is a cross-sectional view illustrating a configuration example of an underlying substrate according to the fourth embodiment. 
         FIG.  17    is a plan view illustrating a configuration example of a semiconductor element substrate according to the fourth embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Embodiments of the present disclosure will be described below with reference to each drawing schematically illustrated. 
     As illustrated in  FIG.  3   , a semiconductor element of the present embodiment can be manufactured through steps including, for example, a mask layer forming step S 1 , an element forming step S 2 , a preparing step S 3 , a bonding step S 4 , and a peeling step S 5 . However, the element forming step S 2  and the preparing step S 3  need not be performed in this order. For example, the element forming step S 2  and the preparing step S 3  may be performed in parallel. 
     Hereinafter, description will be given with reference to  FIGS.  1  to  3   . 
     In the mask layer forming step S 1 , a mask  12  is formed. The mask  12  includes first mask portions  121  and second mask portions  122 . For the first mask portions  121 , two opening portions  12   b  adjacent to each other are located spaced apart by a predetermined first interval ΔL 1  on an underlying substrate  11 . For the second mask portions  122 , two opening portions adjacent to each other are located spaced apart by a predetermined second interval ΔL 2  larger than the first interval ΔL 1 . 
     In the element forming step S 2 , a semiconductor element layer  13 , which is a crystal growth layer of a semiconductor crystal, is vapor phase grown on growth surfaces  11   a  exposed from the opening portions  12   b . The semiconductor element layer  13  of the present disclosure is a nitride semiconductor layer. The semiconductor element layer  13  includes connecting portions  13   b , each of which is connected to a corresponding one of the growth surfaces  11   a  exposed from the opening portions  12   b  of the mask layer  12 . A semiconductor layer is grown on the mask layer  12  to form semiconductor elements  15 . 
     In the preparing step S 3 , a support substrate  16  including a bonding surface  16   c  to be placed on the underlying substrate  11  side is prepared. In the bonding step S 4 , the upper surfaces  15   a  of the semiconductor elements  15  and the bonding surface  16   c  of the support substrate  16  are bonded together. In the peeling step S 5 , the semiconductor elements  15  formed on the mask layer  12  are peeled from the underlying substrate  11 . 
     First Embodiment 
       FIG.  4    is a cross-sectional view illustrating an element forming step according to a first embodiment. As illustrated in  FIG.  4 A , the underlying substrate  11  is prepared. As the underlying substrate  11 , for example, a GaN template substrate can be used. The underlying substrate  11  is an off-angle substrate. The normal lines of the growth surfaces  11   a  of the underlying substrate  11  are inclined by 0.3° from the a-axis &lt;11-20&gt; direction. While the off angle relative to the a-axis is 0.3° in the present embodiment, a substrate having an off angle of from 0.1° to 1° can be used. However, the upper limit value for the off angle is a value selected as appropriate depending on the device as long as flat growth is achieved. Thus, the upper limit value of the off angle is not necessarily 1°, and may be set exceeding 1°. An off angle of less than 0.1° may make it impossible to peel the ELO semiconductor layer, and thus an off angle of 0.1° or greater is advantageous. The upper limit value for the off angle of 1° is a standard off angle for LED substrates. 
     As such an underlying substrate  11 , for example, a GaN substrate cut out from a GaN single crystal ingot can be used such that the growth surfaces  11   a  of the underlying substrate  11  are in a predetermined plane direction. As the underlying substrate  11 , any nitride semiconductor substrate may be used. Alternatively, an n-type substrate or a p-type substrate in which the nitride semiconductor is doped with impurities may be used. 
     Here, the “nitride semiconductor” may be constituted by, for example, Al x Ga y In z N (0≤x≤1; 0≤y≤1; 0≤z≤1; x+y+z=1). As the GaN template substrate, for example, sapphire, Si, or SiC can be used as a foundation. 
     The mask layer  12  is formed on the underlying substrate  11 . The material of the mask layer  12  may be, for example, a silicon oxide (e.g., such as SiO 2 ), a silicon nitride (SiN x ), or a high-melting-point metal (such as Ti or W). The mask layer  12  may be formed by, for example, a plasma chemical vapor deposition (PCVD) method or the like. In the present disclosure, for example, an SiO 2  layer of approximately 100 nm is layered on the growth surfaces  11   a . For example, the SiO 2  layer is patterned by a photolithography method, wet etching with buffered hydrogen fluoride (BHF), and the like. As a result, the mask layer  12  illustrated in  FIG.  4 A  is formed. 
     The mask layer  12  has a stripe shape in which a plurality of strip shape portions  12   a  that are long in the direction perpendicular to the paper surface are aligned in parallel at predetermined intervals. In the present disclosure, the width of the opening portion  12   b  between adjacent strip shape portions  12   a  is, for example, approximately 5 μm. The width of each strip shape portion  12   a  is, for example, approximately 50 μm to 200 μm. The width of the opening portion  12   b  is, for example, approximately 2 μm to 20 μm. 
     As the material for forming the mask layer  12 , apart from SiO 2 , a material may be used that makes it difficult for a semiconductor layer to grow from the mask material by vapor phase growth. As the mask material, for example, an oxide, such as ZrO x , TiO x , or AlO x , which can be patterned, or a transition metal, such as W or Cr can also be used. As the method for layering the mask  12 , any method that is suitable for the mask material, such as vapor deposition, sputtering, or coating and curing, can be used as appropriate. 
     As illustrated in  FIG.  4 B , a semiconductor element layer  13 , which is a crystal growth layer of a semiconductor crystal, is vapor phase grown on the growth surfaces  11   a  exposed from the opening portions  12   b . The semiconductor element layer  13  of the present disclosure is a nitride semiconductor layer. 
     As a method of crystal growth, vapor phase epitaxy (VPE) by a chloride transport method using a chloride as a group III raw material, or metal organic chemical vapor deposition (MOCVD) using an organic metal as a group III raw material can be used. The ratio of a raw material gas of a group III element, the ratio of a raw material gas of an impurity, and the like can be varied during the growing step to form the semiconductor element layer  13  as a multi-layer film that functions as a light-emitting diode (LED) or a laser diode (LD). 
     When the grown crystal exceeds the opening portions  12   b  of the mask layer  12 , the crystal is also laterally grown along the mask layer upper surface  12   c . The crystal growth is completed before adjacent portions of the semiconductor element layer  13  grown from the growth surfaces  11   a  overlap with each other. In this manner, the semiconductor element layer  13 , which is a nitride semiconductor grown by an epitaxial lateral overgrowth (ELO) method, is obtained. The width of the semiconductor element layer  13  is, for example, from approximately 50 μm to approximately 200 μm, and the height is from approximately 10 μm to approximately 50 μm. 
       FIG.  5    is a photograph showing a specific example of the semiconductor element layer  13  formed on the underlying substrate  11 , and is a top view of the semiconductor element layer  13  formed on the mask layer  12  by the above-described method.  FIG.  6    is a graph showing an inclination of the upper surface of the semiconductor element layer  13 , and shows a measurement result of measuring a distance between the upper surface of the semiconductor element layer  13  illustrated in  FIG.  1    and a reference surface. 
     The width W of the semiconductor element layer  13  formed in a strip shape is 35 μm. In the width direction, the right end side is higher than the left end side, and the height difference between both ends is 150 nm. The inclination angle of a first surface  13   a  (upper surface) of the semiconductor element layer  13  is 0.25°. The off angle of the underlying substrate  11  used in the growth of the semiconductor element layer  13  is 0.22°, and the inclination angle of the first surface  13   a  corresponds to the off angle of the underlying substrate  11 . 
     Growing the semiconductor element layer  13  with an off angle added to the underlying substrate  11  in this manner is preferable for realizing a semiconductor element layer  13  having crystallinity of excellent quality. The semiconductor element layer  13  has the first surface  13   a  and a second surface  13   c  located on the opposite side to the first surface  13   a.    
     After the semiconductor element layer  13  is grown, as illustrated in  FIG.  4 B , a metal layer  14  is formed on a first surface  13   a  of the semiconductor element layer  13 . First, the entire upper surfaces of the underlying substrate  11 , the mask layer  12 , and the semiconductor element layer  13  are covered with a photoresist film. Thereafter, opening portions  12   b  are provided using a photolithography method such that the first surface  13   a  of the semiconductor element layer  13  is exposed. Thereafter, a Cr layer and a AuSn layer, which is an alloy of gold and tin, are vapor deposited in order at the opening portions  12   b . Thereafter, any unnecessary metal layer is removed together with the photoresist film by a lift-off method to form the metal layer  14 . The thickness of the metal layer  14  is approximately from 1 μm to 5 μm. 
     After the metal layer  14  is formed, the underlying substrate  11 , the mask layer  12  formed on the underlying substrate  11 , the semiconductor element layer  13 , and the metal layer  14  are immersed in BHF for approximately 10 minutes to remove the mask layer  12 . As a result, as illustrated in  FIG.  4 C , semiconductor elements  15  are formed on the underlying substrate  11 . The semiconductor elements  15  and the underlying substrate  11  are connected to the underlying substrate  11  via connecting portions  13   b , which are portions of the semiconductor element layer  13  grown at the opening portions  12   b  of the mask layer  12 . The connecting portions  13   b  are, for example, of a columnar shape. The metal layer  14  can be used as an electrode of the semiconductor element  15 . 
     However, depending on the configuration of the semiconductor elements  15 , the metal layer  14  need not necessarily be used as an electrode. An upper surface  15   a  of the semiconductor element  15  is inclined similarly to the first surface  13   a  of the semiconductor element layer  13 . The semiconductor element layer  13  has the first surface  13   a  and the second surface  13   c  located on the opposite side to the first surface  13   a.    
       FIG.  7    is a cross-sectional view illustrating a preparing step according to the first embodiment. Subsequently, a support substrate  16  for connecting to the semiconductor element  15  is prepared. In the support substrate  16 , a silicon substrate is used as a base  16   a . A metal layer  16   b  that is less likely to be oxidized, such as Au, is located on one surface of the base  16   a . The surface facing the underlying substrate  11  of the metal layer  16   b  is the bonding surface  16   c . The metal layer  16   b  facilitates bonding of the semiconductor element  15  to the support substrate  16 . For the metal layer  16   b , apart from Au, a precious metal material less likely to be oxidized such as Pt or Pd, or a material containing such a precious metal material as a main component can be used. However, the present disclosure is not limited thereto. 
     Subsequently, the semiconductor element  15  is connected to the support substrate  16  by using a substrate bonding apparatus (not illustrated). First, the underlying substrate  11  and the support substrate  16  are attached to the substrate bonding apparatus so that the growth surfaces  11   a  of the underlying substrate  11  and the bonding surface  16   c  of the support substrate  16  are parallel to each other. 
       FIG.  8    is a cross-sectional view illustrating a bonding step according to the first embodiment. As illustrated in  FIG.  8 A , with the bonding surface  16   c  facing the metal layer  14 , the support substrate  16  is arranged on the metal layer  14  formed in the step of forming the metal layer  14  described above to bring the bonding surface  16   c  of the support substrate  16  and the upper surface  15   a  of the semiconductor elements  15  into contact with each other. Since the first surface  13   a  of the semiconductor element layer  13  is inclined as described above, the upper surface  15   a  of the semiconductor element  15 , which is the upper surface of the metal layer  14  formed on the first surface  13   a , is also inclined. 
     As illustrated in  FIG.  8 B , the support substrate  16  is pressed so that the metal layer  14  is pressed into close contact with the support substrate  16 , and then the metal layer  14  is heated to 300° C. to perform AuSn bonding. However, bonding with the metal layer  14  is not limited to AuSn bonding. Various bonding methods that use other low-melting-point materials (e.g., such as AuIn, AuGe, InPd, or InSn) similar to AuSn can be used. Bonding may also be performed with a metal layer  14  that contains AuSn and/or AuCu having excellent thermal conductivity and that functions as a heat sink. At this time, the semiconductor elements  15  are displaced so that the entire surface of the upper surfaces  15   a  of the semiconductor elements  15  abuts against the bonding surface  16   c . As a result, a large stress may be generated in the connecting portions  13   b  of the semiconductor element layer  13  and the connecting portions  13   b  may be broken. 
       FIG.  9    is a cross-sectional view illustrating a peeling step according to the first embodiment. After the underlying substrate  11 , the support substrate  16 , and the like are cooled by the substrate bonding apparatus or the like, the underlying substrate  11  and the support substrate  16  are taken out from the substrate bonding apparatus. At this time, the semiconductor element  15  is bonded onto the support substrate  16 , and the connecting portions  13   b  are broken, so that the underlying substrate  11  can be easily peeled off. In the drawing, the connecting portions  13   b  having a columnar shape are attached to the semiconductor element layer  13 . It is conceivable that the connecting portions  13   b  remain on the underlying substrate  11  side, on the semiconductor element  15  side, or on both sides, depending on the condition of breakage. Thus, after peeling, any connecting portions  13   b  remaining on the semiconductor elements  15  may be removed by polishing or the like. 
     In a semiconductor element body  17  bonded and peeled by the method described above, the first surface  13   a  of the semiconductor element layer  13  is parallel to the bonding surface  16   c , which is a surface of the support substrate  16 . On the other hand, the second surface  13   c  of the semiconductor element layer  13  is inclined with respect to the surface of the support substrate  16  in accordance with the inclination of the first surface  13   a  of the semiconductor element layer  13 . Here, the first surface  13   a  of the semiconductor element layer  13  is considered to be parallel to the surface of the support substrate  16 , when the inclination is, for example, less than 0.5°. 
     As described above, the semiconductor element body  17  of the first embodiment includes the support substrate  16 , the first surface  13   a , and the second surface  13   c  located on the opposite side to the first surface  13   a , and the first surface  13   a  side is fixed to the support substrate  16 . The semiconductor element body  17  includes the semiconductor element layer  13  in which the second surface  13   c  is inclined with respect to the surface of the support substrate  16 . As a result, the semiconductor element layer  13  having excellent quality can be realized by the simple support structure. 
     As described above, since the semiconductor element  15  is formed with the upper surface  15   a  inclined with respect to the growth surfaces  11   a  of the underlying substrate  11 , when being pressed in the bonding step S 3 , shearing stress is concentrated on the end portion of the connecting portions  13   b  having a columnar shape, and the connecting portions  13   b  are sheared. Accordingly, the semiconductor elements  15  can be separated from the underlying substrate  11  by simply being pressed, without separately applying a large force in a direction perpendicular to the surface of the underlying substrate  11  by ultrasonic waves or the like. As described above, the semiconductor elements  15  can be reliably transferred to the support substrate  16  without applying excessive force to the semiconductor elements  15 , thereby improving the yield of the semiconductor elements  15 . 
     Second Embodiment 
       FIG.  10    is a cross-sectional view illustrating an element forming step for a semiconductor element body according to a second embodiment of the present disclosure. As illustrated in  FIG.  10 A , first, an underlying substrate  21  is prepared. As the underlying substrate  21 , as in the first embodiment, a GaN template substrate is used. However, a crystal plane of a growth surface  21   a  of the underlying substrate  21  has no off angle. A mask layer  22  is formed in a step similar to or the same as that in the first embodiment. The growth surfaces  21   a  are exposed through opening portions  22   b  of strip shape bodies  22   a  of the mask layer  22 . 
     As illustrated in  FIG.  10 B , as in the first embodiment, a semiconductor element layer  23 , which is a crystal growth layer of a nitride semiconductor, is vapor phase grown on the growth surfaces  20   a  exposed from the opening portions  22   b  of the strip shape bodies  22   a . Thereafter, a metal layer  24  of a AuSn alloy or the like is formed on a first surface  23   a  of the semiconductor element layer  23 . 
     As illustrated in  FIG.  10 C , the mask layer  22  on the underlying substrate  21  is etched to form semiconductor elements  25  on the underlying substrate  21 . The first surface  23   a  of the semiconductor element layer  23  and an upper surface  25   a  of the semiconductor element  25  are substantially parallel to the growth surface  21   a  of the underlying substrate  21 . Also, in the second embodiment, similar to the first embodiment, the semiconductor element layer  23  has the first surface  23   a  and a second surface  23   c  located on the opposite side to the first surface  23   a.    
     Third Embodiment 
       FIG.  11    is a cross-sectional view schematically illustrating a configuration of a semiconductor element body according to a third embodiment of the present disclosure.  FIG.  12    is a cross-sectional view of the semiconductor element body as viewed from a cross-sectional plane line XII-XII in  FIG.  11   . The same reference signs are assigned to portions corresponding to those in the above-described embodiments, and description thereof will not be repeated. In the above-described embodiments, configurations in which the opening portions  12   b  extend in parallel in a stripe shape has been described. In other embodiments of the present disclosure, at a portion where the semiconductor element layer  13  to be used as a spacer of the support substrate  16  relative to the underlying substrate  11  is formed, opening portions  12   b   1  may be formed spaced apart at constant intervals in the &lt;1-100&gt; direction (e.g., the vertical direction in  FIG.  12   ). According to the opening portions  12   b   1  such as those described above, the semiconductor element layer  13  described above that serves as a sacrificial layer need not be fabricated, and unwanted semiconductor crystals are not grown. Thus, improved productivity can be had. 
     As described above, in the present disclosure, a method for manufacturing a semiconductor device includes: a mask layer forming step of forming a mask layer on an underlying substrate, the mask layer including a first mask portion in which two opening portions adjacent to each other are located spaced apart by a predetermined first interval and a second mask portion in which two opening portions adjacent to each other are located spaced apart by a predetermined second interval larger than the first interval; an element forming step of forming a semiconductor element by growing a semiconductor layer on the mask layer; a preparing step of preparing a support substrate including a bonding surface, the bonding surface facing the underlying substrate; a bonding step of bonding together an upper surface of the semiconductor element and the bonding surface of the support substrate; and a peeling step of peeling the semiconductor element formed on the mask layer from the underlying substrate. 
     When spacers are used in forming a GaN semiconductor layer by epitaxial vapor phase growth, the variation in height of the GaN semiconductor layer has an in-plane distribution. Thus, when spacers having the same height are used in the entire plane, the amount of protrusion of the bonding layer from the GaN semiconductor layer varies depending on the location. In a case where the amount of protrusion of the bonding layer is large, for example, when the semiconductor elements constructed of the GaN semiconductor layer are semiconductor lasers, an emission end surface of the semiconductor elements may be covered by the protruding portion of the bonding layer, and thus the manufacturing yield may decrease. Thus, a method for manufacturing a semiconductor element and a semiconductor element body with which the manufacturing yield can be improved are desired. 
     According to the method for manufacturing a semiconductor element according to the present disclosure, for the mask layer on the underlying substrate, the growth rate of the semiconductor element layer is faster and thus the thickness of the semiconductor element layer can be made larger in the second mask portion of which the interval is larger than that of the first mask portion. As a result, the amount of protrusion of the metal layer between the upper surface of the semiconductor element layer and the bonding surface of the support substrate can be kept constant, thereby improving manufacturing yield. 
     Fourth Embodiment 
       FIG.  13    is a cross-sectional view illustrating a method for manufacturing a semiconductor element according to a fourth embodiment.  FIG.  14    is a plan view illustrating a configuration example of a mask layer according to the fourth embodiment. As illustrated in  FIGS.  13  and  14   , the method for manufacturing a semiconductor element according to the fourth embodiment includes: a step of preparing an underlying substrate UK on a surface of which a mask layer ML is disposed, the mask layer ML including a first opening portion K 1  and a second opening portion K 2  adjacent to each other in a first direction (X direction); a step of forming, on the underlying substrate UK, a first semiconductor layer SL 1  overlapping the first opening portion K 1  in plan view using, for example, an ELO method; and a step of forming, on the underlying substrate UK, a second semiconductor layer SL 2  overlapping the second opening portion K 2  in plan view and being larger in thickness than the first semiconductor layer SL 1  using, for example, an ELO method. The first and second semiconductor layers SL 1  and SL 2  may be formed by the same film forming process (for example, an ELO process). 
     The mask layer ML includes: a first mask portion M 1 ; a second mask portion M 2  that is adjacent to the first mask portion M 1  via the first opening portion K 1  and that is wider than the first mask portion M 1  (W 1 &lt;W 2 ); and a third mask portion M 3  adjacent to the second mask portion M 2  via the second opening portion K 2 . The first and second opening portions K 1  and K 2  are slit-shaped, in which the Y direction (second direction) orthogonal to the X direction is the longitudinal direction. A substrate including the underlying substrate UK and the mask layer ML is sometimes referred to as a template substrate TS. The underlying substrate UK and the first and second semiconductor layers SL 1  and SL 2  each contain, for example, a nitride semiconductor. The first and second opening portions K 1  and K 2  expose the upper surface (seed portion) of the underlying substrate UK, and function as growth start holes that cause the growth of the first and second semiconductor layers SL 1  and SL 2  to start. The mask portions M 1  to M 3  function as selective growth masks that cause the first and second semiconductor layers SL 1  and SL 2  to laterally grow. A mask portion and an opening portion refer to a portion with a mask body and a portion without a mask body, respectively, regardless of whether the mask portion is layered. Each of the opening portions need not be entirely surrounded by the mask portion. 
     The width direction in  FIGS.  13  and  14    is the X direction. For example, the width W 3  of the third mask portion M 3  is equal to the width W 2  of the second mask portion M 2 , and the width of the first opening portion K 1  and the width of the second opening portion K 2  are equal to each other. In this step, the thickness of the second semiconductor layer SL 2  supplied with more raw material becomes larger than the thickness of the first semiconductor layer SL 1 . Periodically arranging the combined configuration of the first and second semiconductor layers SL 1  and SL 2  in the plane causes the second semiconductor layer SL 2  to have a large thickness in the region where the first semiconductor layer SL 1  has a large thickness, and causes the second semiconductor layer SL 2  to have a small thickness in the region where the first semiconductor layer SL 1  has a small thickness. Thus, the difference in thickness (height difference) between the first and second semiconductor layers SL 1  and SL 2  is made uniform in a plane. Note that the width (the length in the X direction) of the second semiconductor layer SL 2  may be larger than the width of the first semiconductor layer SL 1 . 
     After the first and second semiconductor layers SL 1  and SL 2  are formed, the step of forming a first device layer DL 1  on the first semiconductor layer SL 1  and the step of forming a second device layer DL 2  on the second semiconductor layer SL 2  are performed. As a result, a semiconductor element substrate HK 1  is formed. The first and second device layers DL 1  and DL 2  may be formed in the same film forming process. Each of the first and second device layers DL 1  and DL 2  can include an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. 
     After the first and second device layers DL 1  and DL 2  are formed, the step of forming a first metal layer CL 1  on the first device DL 1  and the step of forming a second metal layer CL 2  on the second device layer DL 2  are performed. The first and second metal layers CL 1  and CL 2  may be formed in the same film forming process. For example, since the thickness of the first device layer DL 1  and the thickness of the second device layer DL 2  are approximately the same, the position of the upper surface of the second metal layer CL 2  is located higher than the upper surface of the first metal layer CL 1 . 
     After the first and second metal layers CL 1  and CL 2  are formed, the step of bonding the first and second device layers DL 1  and DL 2  to a support substrate SK via the first and second metal layers CL 1  and CL 2  is performed, with the first and second metal layers CL 1  and CL 2  in a melted state, by bringing the first and second metal layers CL 1  and CL 2  into contact with the support substrate SK and then curing the first and second metal layers CL 1  and CL 2 . When bonding, the second semiconductor layer SL 2  and the second device layer DL 2  function as a spacer, and the second metal layer CL 2  becomes thinner than the first metal layer CL 1 . 
     The second metal layer CL 2  may come into contact with an end surface of the second device layer DL 2  (a surface having a normal line parallel to the X direction or the Y direction). The second metal layer CL 2  enhances the strength of bonding with the support substrate SK. Note that an emission surface of a laser beam may be included in an end surface of the first device layer DL 1  (e.g., a surface having a normal line parallel to the Y direction). As described above, the difference in thickness (height difference) between the first and second semiconductor layers SL 1  and SL 2  is made uniform in a plane, and thus the risk of the first metal layer CL 1  coming into contact with an end surface of the first device layer DL 1  is reduced. The second semiconductor layer SL 2  and the second device layer DL 2  can be sacrificial layers (not used as a semiconductor layer element). However, the present disclosure is not limited thereto. In some cases, the second semiconductor layer SL 2  and the second device layer DL 2  can be used as a semiconductor element depending on the configuration of the second device layer DL 2 . 
     When the first and second device layers DL 1  and DL 2  are bonded to the support substrate SK, stress is applied to the first and second semiconductor layers SL 1  and SL 2 , and thus the bonding force between the underlying substrate UK and the first and second semiconductor layers SL 1  and SL 2  that are fixed together is weakened (e.g., the bonding portion is broken). 
     The first and second metal layers CL 1  and CL 2  may be bonded to a third metal layer KL located on the support substrate SK. The first metal layer CL 1  may be an electrode (anode or cathode) on the first device layer DL 1 . 
     For example, when the first and second device layers DL 1  and DL 2  and the support substrate SK are bonded together, the respective upper surfaces of the first and second metal layers CL 1  and CL 2  may be inclined relative to the support substrate SK by approximately from 0.05° to 5°. This inclination is due to the off angle of the underlying substrate UK, for example. Thus, when the first and second device layers DL 1  and DL 2  are bonded to the support substrate SK, the first and second semiconductor layers SL 1  and SL 2  are effectively subjected to upward stress. 
     After the support substrate SK is bonded, the step of separating the first and second semiconductor layers SL 1  and SL 2  from the underlying substrate UK is performed. As a result, a semiconductor element substrate HK 2  is formed. Before the first and second semiconductor layers SL 1  and SL 2  are separated, the mask layer ML (first to third mask portions M 1  to M 3 ) may be removed by etching or the like. The mask layer ML and the first and second semiconductor layers SL 1  and SL 2  may adhere to each other by Van der Waals&#39; forces or mutual diffusion of constituent elements. Thus, removing the mask layer ML can easily separate the first and second semiconductor layers SL 1  and SL 2 . Note that in the present disclosure, the support substrate SK is bonded before the mask layer ML is removed. 
     Note that the mask layer ML (first to third mask portions M 1  to M 3 ) may be removed by etching or the like before the support substrate SK is bonded. Since the mask layer ML is exposed on the surface prior to bonding, the mask layer ML on the entire surface of the semiconductor element substrate can be easily removed by wet etching. Before the first and second semiconductor layers SL 1  and SL 2  are separated, the first semiconductor layer SL 1  and the first device layer DL 1  may be divided into a plurality of semiconductor element portions aligned in the Y direction. 
       FIG.  15    is a plan view illustrating another configuration of the mask layer according to the fourth embodiment. The mask layer ML is not limited to that in  FIG.  14   . For example, as in  FIG.  15   , a configuration may be employed in which the length in the Y direction orthogonal to the first direction (X direction) of the second opening portion K 2  is smaller than the length of the first opening portion K 1 . The second opening portion K 2  is formed in, for example, a mask portion M 4  adjacent to a slit-shaped first opening portion K 1 . For example, the respective widths of the first and second opening portions K 1  and K 2  are equal to each other. 
     In this case, the thickness of the second semiconductor layer SL 2  grown on the second opening portion K 2  (which grows faster in the Z direction than in the X direction) is larger than the thickness of the first semiconductor layer SL 1 . In a region where the thickness of the first semiconductor layer SL 1  is large, the thickness of the second semiconductor layer SL 2  is also large. In a region where the thickness of the first semiconductor layer SL 1  is small, the thickness of the second semiconductor layer SL 2  is also small. Thus, the difference in thickness (height difference) between the first and second semiconductor layers SL 1  and SL 2  is made uniform in a plane. In  FIG.  15   , the width (the length in the X direction) of the second semiconductor layer SL 2  is smaller than the width of the first semiconductor layer SL 1 . 
     In the fourth embodiment, a configuration may be employed in which the underlying substrate UK contains a nitride semiconductor (such as a GaN-based semiconductor, AlN, InN, AlInN, or BN), and the first and second semiconductor layers SL 1  and SL 2  each contain a nitride semiconductor, for example, a GaN-based semiconductor (such as GaN, AlGaN, InGaN, or AlInGaN). In this case, the thickness direction (Z direction) of the first and second semiconductor layers SL 1  and SL 2  can be the &lt;0001&gt; direction (c-axis direction) of the nitride semiconductor, the first direction (X direction) in which the first and second opening portions K 1  and K 2  are aligned can be the &lt;11-20&gt; direction (a-axis direction) of the nitride semiconductor, and the Y direction can be the &lt;1-100&gt; direction (m-axis direction) of the nitride semiconductor. 
       FIG.  16    is a cross-sectional view illustrating a configuration example of an underlying substrate according to the fourth embodiment. The underlying substrate UK may be a GaN wafer cut out from a bulk crystal of GaN, or may be a SiC wafer (hexagonal 6H—SiC or 4H—SiC) cut out from a bulk crystal of SiC. An off angle may be added when the underlying substrate UK is cut out from the bulk crystal. 
     A configuration may be employed in which the underlying substrate UK includes a dissimilar substrate  1  having a lattice constant different from that of the GaN-based semiconductor, and an underlying layer  4  (seed layer) formed on the dissimilar substrate  1 . In this case, the dissimilar substrate  1  may be a silicon substrate, and the underlying layer  4  may be AlN or a silicon carbide (6H—SiC or 4H—SiC). Alternatively, the dissimilar substrate  1  may be a silicon carbide substrate, and the underlying layer  4  may be a GaN-based semiconductor or AlN. 
     A configuration may be employed in which the underlying substrate UK includes the dissimilar substrate  1  and the underlying layer  4  formed on the dissimilar substrate  1 , and the underlying layer  4  includes a buffer layer  2  on the lower layer side and a seed layer  3  formed on the buffer layer  2 . In this case, a configuration may be employed in which the dissimilar substrate  1  is a silicon substrate, the buffer layer  2  contains AlN and/or a silicon carbide, and the seed layer  3  is a GaN-based semiconductor. A boron nitride (BN) may be used for the buffer layer  2 , and AlN may be used for the seed layer  3 . The upper surface of the dissimilar substrate  1  in  FIG.  16    may have an off angle. 
     The semiconductor element substrate HK 1  in  FIG.  13    includes a first semiconductor layer SL 1  containing a nitride semiconductor, a first device layer DL 1  overlapping the first semiconductor layer SL 1  in plan view, a first metal layer CL 1  disposed on the first device layer DL 1 , a second semiconductor layer SL 2  containing a nitride semiconductor, a second device layer DL 2  overlapping the second semiconductor layer SL 2  in plan view, and a second metal layer CL 2  disposed on the second device layer DL 2 . The thickness of the second semiconductor layer SL 2  is larger than the thickness of the first semiconductor layer SL 1 . 
     The semiconductor element substrate HK 1  includes an underlying substrate UK connected to the first and second semiconductor layers SL 1  and SL 2 . The first and second device layers DL 1  and DL 2  each contain a nitride semiconductor (e.g., a GaN-based semiconductor). The first and second semiconductor layers SL 1  and SL 2  may contain the same nitride semiconductor (e.g., GaN). Since the first and second device layers DL 1  and DL 2  have approximately the same thickness, the upper surface of the second metal layer CL 2  is located higher than the upper surface of the first metal layer CL 1 . The semiconductor element substrate HK 1  is provided with a mask layer ML that is in contact with the underlying substrate UK and the first and second semiconductor layers SL 1  and SL 2 . 
     The semiconductor element substrate HK 2  in  FIG.  13    includes a first semiconductor layer SL 1  containing a nitride semiconductor, a first device layer DL 1  overlapping the first semiconductor layer SL 1  in plan view, a first metal layer CL 1  disposed on the first device layer DL 1 , a second semiconductor layer SL 2  containing a nitride semiconductor, a second device layer DL 2  overlapping the second semiconductor layer SL 2  in plan view, and a second metal layer CL 2  disposed on the second device layer DL 2 . The thickness of the second semiconductor layer SL 2  is larger than the thickness of the first semiconductor layer SL 1 . 
     The semiconductor element substrate HK 2  includes a support substrate SK bonded to the first and second device layers DL 1  and DL 2  via the first and second metal layers CL 1  and CL 2 . The first and second device layers DL 1  and DL 2  each contain a nitride semiconductor (e.g., a GaN-based semiconductor). The first and second semiconductor layers SL 1  and SL 2  may contain the same nitride semiconductor (e.g., GaN). 
     In the semiconductor element substrate HK 2 , the thickness of the second metal layer CL 2  can be smaller than the thickness of the first metal layer CL 1 . The second metal layer CL 2  may come into contact with an end surface T 2  of the second device layer DL 2 . A configuration may be employed in which the first device layer DL 1  has a light-emitting function, and the second device layer DL 2  is a sacrificial layer (has no light-emitting function). A configuration may be employed in which the third metal layer KL is located on the support substrate SK, and the first and second metal layers CL 1  and CL 2  are bonded to the third metal layer KL. The support substrate SK may be a mounting substrate (a drive substrate for a thin-film transistor (TFT) substrate or the like). 
     In the semiconductor element substrates HK 1  and HK 2 , the first and second semiconductor layers SL 1  and SL 2  may be aligned in the &lt;11-20&gt; direction (X direction) of the nitride semiconductor. The first semiconductor layer SL 1  and the first device layer DL 1  may constitute a semiconductor element portion (e.g., a light-emitting element portion). An emission surface of a laser beam may be included in an end surface T 1  of the first device layer DU. The first metal layer CL 1  may function as an electrode, for example an anode. 
       FIG.  17    is a plan view illustrating a configuration example of a semiconductor element substrate according to the fourth embodiment. As illustrated in  FIG.  17   , a configuration may be employed in which the semiconductor element substrates HK 1  and HK 2  include a plurality of regions AR, and each of the regions AR is provided with the first semiconductor layer SL 1  and the first device layer DL 1  as well as the second semiconductor layer SL 2  and the second device layer DL 2 . The semiconductor element substrates HK 1  and HK 2  may include a plurality of semiconductor element portions HB (each including the first semiconductor layer SL 1  and the first device layer DL 1 ). The plurality of semiconductor element portions HB may be aligned in the X direction and/or the Y direction. 
     The present disclosure has been described in detail above. However, the present disclosure is not limited to the embodiments described above, and various modifications or improvements can be made without departing from the essential spirit of the present disclosure 
     REFERENCE SIGNS 
       11  Underlying substrate 
       13  Semiconductor element layer 
       13   a  First surface 
       13   b  Connecting portion 
       13   c  Second surface 
       14  Metal layer 
       15  Semiconductor element 
       15   a  Upper surface 
       16  Support substrate 
       16   c  Bonding surface 
       17  Semiconductor element body 
     S 1  Mask layer forming step 
     S 2  Element forming step 
     S 3  Preparing step 
     S 4  Bonding step 
     S 5  Peeling step