Patent Publication Number: US-2019180710-A1

Title: Display apparatus and method of driving display panel using the same

Description:
This application claims priority to Korean Patent Application No. 10-2017-0169716, filed on Dec. 11, 2017, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference. 
     BACKGROUND 
     1. Field 
     Exemplary embodiments of the inventive concept relate to a display apparatus and a method of driving a display panel using the display apparatus. More particularly, exemplary embodiments of the inventive concept relate to a display apparatus including a data driver including driving blocks which generate common voltages and output the common voltages to display blocks of the display panel to enhance a uniformity of the common voltages and a method of driving a display panel using the display apparatus. 
     2. Description of the Related Art 
     A display apparatus includes a display panel and a display panel driver. The display panel driver generally includes a timing controller, a gate driver and a data driver. The timing controller adjusts driving timings of the gate driver and the data driver. The gate driver outputs gate signals to gate lines. The data driver outputs data voltages to data lines. 
     The display panel driver may further include a common voltage generator. The common voltage generator generates a common voltage and outputs the common voltage generator to the display panel. 
     Pixels of the display panel display desired grayscales using a difference of the data voltage and the common voltage. 
     SUMMARY 
     As a size of the display panel increases, the common voltage may vary according to a position in the display panel such that the display quality of the display panel may be deteriorated. 
     In addition, when the display panel displays a specific pattern in a specific polarity inversion driving method, the pixels of the display panel may not display the desired grayscales due to an oscillation of the common voltage such that the display quality of the display panel may be deteriorated. 
     Exemplary embodiments of the inventive concept provide a display apparatus including a data driver including driving blocks which generate common voltages and output the common voltages to display blocks of the display panel. 
     Exemplary embodiments of the inventive concept also provide a method of driving a display panel using the above-mentioned display apparatus. 
     In an exemplary embodiment according to the inventive concept, a display apparatus includes a display panel, a gate driver and a data driver. The display panel includes a plurality of display blocks. The gate driver generates a plurality of gate signals and outputs the plurality of the gate signals to a plurality of gate lines. The data driver generates a plurality of data voltages, outputs the plurality of the data voltages to a plurality of data lines, generates common voltages and outputs the common voltages to the display panel. The data driver includes a plurality of driving blocks. The driving blocks generate the common voltages and output the common voltages to the display blocks. 
     In an exemplary embodiment, the display blocks may extend along an extending direction of the data lines. The display blocks may be arranged along an extending direction of the gate lines. 
     In an exemplary embodiment, the driving blocks may be respectively integrated circuits connected to an end portion of the display panel. 
     In an exemplary embodiment, the driving block may include a plurality of data voltage amplifiers which output the data voltages to the data lines and at least one common voltage amplifier which outputs the common voltage to the display panel. 
     In an exemplary embodiment, the driving block may further include a decoder which receives a common voltage base signal from a timing controller and generates the common voltage based on the common voltage base signal. 
     In an exemplary embodiment, the driving block may further include a feedback part which compares a fed-back common voltage from the display panel with a reference voltage and generates a comparing signal and a polarity converting part which converts a polarity inversion driving method of the display panel based on the comparing signal. 
     In an exemplary embodiment, the feedback part may include a first comparator comprising a first input terminal receiving the fed-back common voltage, a second input terminal receiving a first reference voltage which is greater than a target common voltage and an output terminal outputting a first comparing signal when the fed-back common voltage is greater than the first reference voltage and a second comparator comprising a first input terminal receiving the fed-back common voltage, a second input terminal receiving a second reference voltage which is less than the target common voltage and an output terminal outputting a second comparing signal when the fed-back common voltage is less than the second reference voltage. 
     In an exemplary embodiment, the feedback part may include a first comparator comprising a first input terminal receiving the fed-back common voltage, a second input terminal receiving a first reference voltage which is greater than a target common voltage and an output terminal outputting a first comparing signal when the fed-back common voltage is greater than the first reference voltage, a second comparator comprising a first input terminal receiving the fed-back common voltage, a second input terminal receiving a second reference voltage which is less than the target common voltage and an output terminal outputting a second comparing signal when the fed-back common voltage is less than the second reference voltage, a third comparator comprising a first input terminal receiving the fed-back common voltage, a second input terminal receiving a third reference voltage which is greater than the first reference voltage and an output terminal outputting a third comparing signal when the fed-back common voltage is greater than the third reference voltage and a fourth comparator comprising a first input terminal receiving the fed-back common voltage, a second input terminal receiving a fourth reference voltage which is less than the second reference voltage and an output terminal outputting a fourth comparing signal when the fed-back common voltage is less than the fourth reference voltage. 
     In an exemplary embodiment, the driving blocks may further include a multiplexer disposed between the data voltage amplifiers and the data lines and which determines connections between the data voltage amplifiers and the data lines. 
     In an exemplary embodiment, the polarity inversion driving method may include a first mode and a second mode. The polarity converting part may convert the polarity inversion driving method between the first mode and the second mode according to the comparing signal. Polarities of the data voltages may be inverted every data line in the first mode. The polarities of the data voltages may be inverted every two data lines in the second mode. 
     In an exemplary embodiment, the polarity inversion driving method may include a first mode and a second mode. The polarity converting part may convert the polarity inversion driving method between the first mode and the second mode according to the comparing signal. Polarities of the data voltages may be inverted every data line in the first mode. The polarities of the data voltages may be inverted every six data lines in the second mode. 
     In an exemplary embodiment, the polarity inversion driving method may include a first mode and a second mode. The polarity converting part may convert the polarity inversion driving method between the first mode and the second mode according to the comparing signal. Polarities of the data voltages may be inverted every two data lines in the first mode. The polarities of the data voltages may be inverted every six data lines in the second mode. 
     In an exemplary embodiment, the polarity inversion driving method may include a first mode, a second mode and a third mode. The polarity converting part may convert the polarity inversion driving method among the first mode, the second mode and the third mode according to the comparing signal. Polarities of the data voltages may be inverted every data line in the first mode. The polarities of the data voltages may be inverted every two data lines in the second mode. The polarities of the data voltages may be inverted every six data lines in the third mode. 
     In an exemplary embodiment, the timing controller may include a feedback part which compares a fed-back common voltage from the display panel with a reference voltage and generates a comparing signal and a polarity converting part which converts a polarity inversion driving method of the display panel based on the comparing signal. 
     In an exemplary embodiment of a method of driving a display panel according to the inventive concept, the method includes generating a plurality of gate signals, outputting the plurality of the gate signals to a plurality of gate lines, generating a plurality of data voltages, outputting the plurality of the data voltages to a plurality of data lines, generating a plurality of common voltages and outputting the plurality of the common voltages to a plurality of driving blocks of the display panel. 
     In an exemplary embodiment, the method may further include comparing a fed-back common voltage from the display panel with a reference voltage, generating a comparing signal based on a result of the comparing the fed-back common voltage with the reference voltage and converting a polarity inversion driving method of the display panel based on the comparing signal. 
     In an exemplary embodiment, generating the comparing signal may include comparing the fed-back common voltage with a first reference voltage greater than a target common voltage, outputting a first comparing signal when the fed-back common voltage is greater than the first reference voltage, comparing the fed-back common voltage with a second reference voltage less than the target common voltage and outputting a second comparing signal when the fed-back common voltage is less than the second reference voltage. 
     In an exemplary embodiment, generating the comparing signal may further include comparing the fed-back common voltage with a third reference voltage greater than the first reference voltage, outputting a third comparing signal when the fed-back common voltage is greater than the third reference voltage, comparing the fed-back common voltage with a fourth reference voltage less than the second reference voltage and outputting a fourth comparing signal when the fed-back common voltage is less than the fourth reference voltage. 
     In an exemplary embodiment, converting the polarity inversion driving method of the display panel may include determining connections between a plurality of data voltage amplifiers and the plurality of the data lines using a multiplexer disposed between the plurality of the data voltage amplifiers and the plurality of the data lines. 
     According to the display apparatus and the method of driving the display panel of the display apparatus, the driving blocks of the data driver generate the common voltages and output the common voltages to the display blocks of the display panel such that the uniformity of the common voltage may be enhanced. 
     In addition, the polarity inversion driving method of the display panel may be converted using a waveform of the fed-back common voltage when the distortion of the common voltage occurs. Therefore, the distortion of the common voltage may be reduced. 
     As a result, the level of the common voltage may be stabilized such that the display quality of the display panel may be enhanced. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages of the inventive concept will become more apparent by describing in detailed exemplary embodiments thereof with reference to the accompanying drawings, in which: 
         FIG. 1  is a block diagram illustrating an exemplary embodiment of a display apparatus according to the inventive concept; 
         FIG. 2  is a conceptual diagram illustrating an exemplary embodiment of a pixel structure of a display panel of  FIG. 1 ; 
         FIG. 3A  is a conceptual diagram illustrating an exemplary embodiment of the display panel of  FIG. 2  displaying a checker board pattern; 
         FIG. 3B  is a timing diagram illustrating an exemplary embodiment of data voltages and a common voltage when the display panel of  FIG. 2  displays the checker board pattern of  FIG. 3A ; 
         FIG. 4A  is a conceptual diagram illustrating an exemplary embodiment of the display panel of  FIG. 2  displaying a sub checker board pattern; 
         FIG. 4B  is a timing diagram illustrating an exemplary embodiment of data voltages and a common voltage when the display panel of  FIG. 2  displays the sub checker board pattern of  FIG. 4A ; 
         FIG. 5  is a plan view illustrating the display panel and a data driver of  FIG. 1 ; 
         FIG. 6A  is a conceptual diagram illustrating a first driving block of  FIG. 5 ; 
         FIG. 6B  is a conceptual diagram illustrating a second driving block of  FIG. 5 ; 
         FIG. 7  is a circuit diagram illustrating a common voltage generator of the first driving block of  FIG. 6A ; 
         FIG. 8  is a block diagram illustrating a feedback part and a polarity converting part of the data driver of  FIG. 5 ; 
         FIG. 9  is a circuit diagram illustrating the feedback part of  FIG. 8 ; 
         FIG. 10  is a timing diagram illustrating a waveform of a fed-back common voltage of  FIG. 9 ; 
         FIGS. 11A and 11B  are conceptual diagrams illustrating a polarity inversion driving method of a first mode; 
         FIGS. 12A and 12B  are conceptual diagrams illustrating a polarity inversion driving method of a second mode; 
         FIGS. 13A and 13B  are conceptual diagrams illustrating a polarity inversion driving method of a third mode; 
         FIG. 14  is a circuit diagram illustrating an exemplary embodiment of a feedback part of a data driver of a display apparatus according to the inventive concept; 
         FIG. 15  is a timing diagram illustrating an exemplary embodiment of a waveform of a fed-back common voltage of  FIG. 14 ; and 
         FIG. 16  is a block diagram illustrating an exemplary embodiment of a feedback part and a polarity converting part of a timing controller of a display apparatus according to the inventive concept. 
     
    
    
     DETAILED DESCRIPTION 
     It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. 
     Hereinafter, the inventive concept will be explained in detail with reference to the accompanying drawings. 
       FIG. 1  is a block diagram illustrating an exemplary embodiment of a display apparatus according to the inventive concept. 
     Referring to  FIG. 1 , the display apparatus includes a display panel  100  and a display panel driver. The display panel driver includes a timing controller  200 , a gate driver  300 , a gamma reference voltage generator  400  and a data driver  500 . 
     The display panel  100  includes an active region displaying an image and a peripheral region adjacent to the active region. In an exemplary embodiment, for example, the display panel  100  may be a display panel of a liquid crystal display apparatus which includes a liquid crystal layer. 
     The display panel  100  includes a plurality of gate lines GL, a plurality of data lines DL and a plurality of subpixels SP electrically connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D 1  and the data lines DL extend in a second direction D 2  crossing the first direction D 1 . 
     The timing controller  200  receives input image data IMG and an input control signal CONT from an external apparatus (not shown). The input image data IMG may include red image data, green image data and blue image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronizing signal and a horizontal synchronizing signal. 
     The timing controller  200  generates a first control signal CONT 1 , a second control signal CONT 2 , a third control signal CONT 3  and data signals DATA based on the input image data IMG and the input control signal CONT. 
     The timing controller  200  generates the first control signal CONT 1  for controlling an operation of the gate driver  300  based on the input control signal CONT, and outputs the first control signal CONT 1  to the gate driver  300 . The first control signal CONT 1  may include a vertical start signal and a gate clock signal. 
     The timing controller  200  generates the second control signal CONT 2  for controlling an operation of the data driver  500  based on the input control signal CONT, and outputs the second control signal CONT 2  to the data driver  500 . The second control signal CONT 2  may include a horizontal start signal and a load signal. 
     The timing controller  200  generates the data signals DATA based on the input image data IMG The timing controller  200  outputs the data signals DATA to the data driver  500 . 
     The timing controller  200  may output a common voltage base signal COM to the data driver  500 . In an exemplary embodiment, for example, the timing controller  200  may receive the common voltage base signal COM from outside and output the common voltage base signal COM to the data driver  500 . 
     The timing controller  200  generates the third control signal CONT 3  for controlling an operation of the gamma reference voltage generator  400  based on the input control signal CONT, and outputs the third control signal CONT 3  to the gamma reference voltage generator  400 . 
     The gate driver  300  generates gate signals driving the gate lines GL in response to the first control signal CONT 1  received from the timing controller  200 . For example, the gate driver  300  may sequentially output the gate signals to the gate lines GL. 
     The gate driver  300  may be directly mounted on the display panel  100  or connected to the display panel  100  in a type of a tape carrier package (“TCP”). In another exemplary embodiment, the gate driver  300  may be integrated on the peripheral region of the display panel. 
     The gamma reference voltage generator  400  generates a gamma reference voltage VGREF in response to the third control signal CONT 3  received from the timing controller  200 . The gamma reference voltage generator  400  provides the gamma reference voltage VGREF to the data driver  500 . The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA. 
     In an exemplary embodiment, the gamma reference voltage generator  400  may be disposed in the timing controller  200 , or in the data driver  500 . 
     The data driver  500  receives the second control signal CONT 2  and the data signals DATA from the timing controller  200 , and receives the gamma reference voltages VGREF from the gamma reference voltage generator  400 . The data driver  500  converts the data signals DATA into data voltages VD having an analog type using the gamma reference voltages VGREF. The data driver  500  outputs the data voltages VD to the data lines DL. 
     The data driver  500  may receive the common voltage base signal COM from the timing controller  200 . The data driver  500  generates a common voltage VCOM based on the common voltage base signal COM and outputs the common voltage VCOM to the display panel  100 . 
       FIG. 2  is a conceptual diagram illustrating an exemplary embodiment of a pixel structure of a display panel of  FIG. 1 . 
     Referring to  FIGS. 1 and 2 , the display panel  100  includes a plurality of subpixels SP disposed in a matrix form. 
     Subpixels R 11 , G 11 , B 11 , R 12 , G 12 , B 12 , R 13 , G 13 , B 13 , R 14 , G 14  and B 14  in a first row of the subpixels SP in the display panel  100  are connected to a first gate line GL 1 . Subpixels R 21 , G 21 , B 21 , R 22 , G 22 , B 22 , R 23 , G 23 , B 23 , R 24 , G 24  and B 24  in a second row of the subpixels SP in the display panel  100  are connected to a second gate line GL 2 . Subpixels R 31 , G 31 , B 31 , R 32 , G 32 , B 32 , R 33 , G 33 , B 33 , R 34 , G 34  and B 34  in a third row of the subpixels SP in the display panel  100  are connected to a third gate line GL 3 . 
     Subpixels R 11 , R 21  and R 31  in a first column of the subpixels SP in the display panel  100  are connected to a first data line DL 1 . Subpixels G 11 , G 21  and G 31  in a second column of the subpixels SP in the display panel  100  are connected to a second data line DL 2 . Subpixels B 11 , B 21  and B 31  in a third column of the subpixels SP in the display panel  100  are connected to a third data line DL 3 . Subpixels R 12 , R 22  and R 32  in a fourth column of the subpixels SP in the display panel  100  are connected to a fourth data line DL 4 . Subpixels G 12 , G 22  and G 32  in a fifth column of the subpixels SP in the display panel  100  are connected to a fifth data line DL 5 . Subpixels B 12 , B 22  and B 32  in a sixth column of the subpixels SP in the display panel  100  are connected to a sixth data line DL 6 . 
     The subpixels having different colors are alternately disposed along a row direction (i.e., first direction D 1 ). In an exemplary embodiment, for example, red, green and blue subpixels are alternately disposed along the row direction. 
     The subpixels having the same color are disposed along a column direction (i.e., second direction D 2 ). In an exemplary embodiment, for example, the red subpixels are disposed in the first column, the green subpixels are disposed in the second column and the blue subpixels are disposed in the third column. 
     Although a single data line is connected to the subpixels in the single column (i.e., a non-staggered structure) in this exemplary embodiment, in an alternative exemplary embodiment, a single data line may be connected to the subpixels in two adjacent columns (i.e., a staggered structure). 
       FIG. 3A  is a conceptual diagram illustrating an exemplary embodiment of the display panel  100  of  FIG. 2  displaying a checker board pattern.  FIG. 3B  is a timing diagram illustrating an exemplary embodiment of a data voltages VD and a common voltage VCOM when the display panel  100  of  FIG. 2  displays the checker board pattern of  FIG. 3A . 
     Referring to  FIGS. 1 to 3B , the display panel  100  may display the checker board pattern. In the checker board pattern, three turned-on subpixels and three turned-off subpixels are alternately and repetitively disposed along the row direction and one turned-on subpixel and one turned-off subpixel are alternately and repetitively disposed along the column direction. 
     In this exemplary embodiment, the display panel  100  is driven in one column inversion method. In the one column inversion method, polarities of the data voltages are inverted every data line (i.e., every column of pixels). In an exemplary embodiment, for example, during a first frame, data voltages applied to first, third, fifth, seventh, ninth and eleventh data lines DL 1 , DL 3 , DL 5 , DL 7 , DL 9  and DL 11  may have a first polarity. In contrast, during the first frame, data voltages applied to second, fourth, sixth, eighth, tenth and twelfth data lines DL 2 , DL 4 , DL 6 , DL 8 , DL 10  and DL 12  may have a second polarity. During a second frame, data voltages applied to first, third, fifth, seventh, ninth and eleventh data lines DL 1 , DL 3 , DL 5 , DL 7 , DL 9  and DL 11  may have the second polarity. In contrast, during the second frame, data voltages applied to second, fourth, sixth, eighth, tenth and twelfth data lines DL 2 , DL 4 , DL 6 , DL 8 , DL 10  and DL 12  may have the first polarity. 
     In a case that the display panel  100  displays the checker board pattern, during a first horizontal period when the gate signal is applied to the subpixels in the first row, the red and blue subpixels R 12 , R 14 , B 12  and B 14 , which are turned on, may have data voltages of a negative polarity and the green subpixels G 12  and G 14 , which are turned on, may have data voltages of a positive polarity. During the first horizontal period, the number of the turned-on subpixels R 12 , R 14 , B 12  and B 14  having the data voltages of the negative polarity is greater than the number of the turned-on subpixels G 12  and G 14  having the data voltages of the positive polarity. Thus, a waveform of the common voltage VCOM may be oriented toward the negative polarity due to a coupling effect. 
     In the case that the display panel  100  displays the checker board pattern, during a second horizontal period when the gate signal is applied to the subpixels in the second row, the red and blue subpixels R 21 , R 23 , B 21  and B 23 , which are turned on, may have data voltages of a positive polarity and the green subpixels G 21  and G 23 , which are turned on, may have data voltages of a negative polarity. During the second horizontal period, the number of the subpixels R 21 , R 23 , B 21  and B 23  having the data voltages of the positive polarity is greater than the number of the subpixels G 21  and G 23  having the data voltages of the negative polarity. Thus, a waveform of the common voltage VCOM may be oriented toward the positive polarity due to the coupling effect. 
     As explained above, when the display panel  100  displays the checker board pattern, the common voltage VCOM may have a waveform oscillating between a negative value and a positive value due to the coupling effect as shown in  FIG. 3B . Due to the oscillation of the common voltage VCOM, the subpixels may not display the desired grayscales. 
       FIG. 4A  is a conceptual diagram illustrating an exemplary embodiment of the display panel  100  of  FIG. 2  displaying a sub checker board pattern.  FIG. 4B  is a timing diagram illustrating an exemplary embodiment of data voltages VD and a common voltage VCOM when the display panel  100  of  FIG. 2  displays the sub checker board pattern of  FIG. 4A . 
     Referring to  FIGS. 1, 2, 4A and 4B , the display panel  100  may display the sub checker board pattern. In the sub checker board pattern, one turned-on subpixel and one turned-off subpixel are alternately and repetitively disposed along the row direction and one turned-on subpixel and one turned-off subpixel are alternately and repetitively disposed along the column direction. 
     In this exemplary embodiment, the display panel  100  is driven in the one column inversion method. 
     In a case that the display panel  100  displays the sub checker board pattern, during a first horizontal period when the gate signal is applied to the subpixels in the first row, all of the turned-on subpixels G 11 , R 12 , B 12 , G 13 , R 14  and B 14  may have data voltages of a negative polarity. Thus, a waveform of the common voltage VCOM may be oriented toward the negative polarity due to a coupling effect. 
     In the case that the display panel  100  displays the sub checker board pattern, during a second horizontal period when the gate signal is applied to the subpixels in the second row, all of the turned-on subpixels R 21 , B 21 , G 22 , R 23 , B 23  and G 24  may have data voltages of a positive polarity. Thus, a waveform of the common voltage VCOM may be oriented toward the positive polarity due to a coupling effect. 
     As explained above, when the display panel  100  displays the sub checker board pattern, the common voltage VCOM may have a waveform oscillating between a negative value and a positive value due to the coupling effect as shown in  FIG. 4B . Due to the oscillation of the common voltage VCOM, the subpixels may not display the desired grayscales. 
       FIG. 5  is a plan view illustrating an exemplary embodiment of the display panel and a data driver of  FIG. 1 .  FIG. 6A  is a conceptual diagram illustrating an exemplary embodiment of a first driving block of  FIG. 5 .  FIG. 6B  is a conceptual diagram illustrating an exemplary embodiment of a second driving block of  FIG. 5 . 
     Referring to  FIGS. 1 to 6B , the display panel  100  may include a plurality of display blocks A 1  to A 12 . The display blocks A 1  to A 12  may extend along an extending direction of the data line DL (i.e., second direction D 2 ). The display blocks A 1  to A 12  may be arranged along an extending direction of the gate line GL (i.e., first direction D 1 ). 
     The display panel driver may include a printed circuit board PB, a first data circuit board  510 , a second data circuit board  520 , a first flexible circuit board FP 1  and a second flexible circuit board FP 2 . 
     The timing controller  200  may be disposed on the printed circuit board PB. The first data circuit board  510  may be connected to the printed circuit board PB through the first flexible circuit board FP 1 . The second data circuit board  520  may be connected to the printed circuit board PB through the second flexible circuit board FP 2 . 
     The data driver  500  may generate the data voltages VD and output the data voltages VD to the data lines DL of the display panel  100 . In addition, the data driver  500  may generate the common voltage VCOM and output the common voltage VCOM to the display panel  100 . 
     The data driver  500  may include a plurality of driving blocks DB 1  to DB 12 . Each of the driving blocks DB 1  to DB 12  may generate the common voltage VCOM and output the common voltage VCOM to the corresponding display block among the display blocks A 1  to A 12 . The levels of the common voltages VCOM outputted to the driving blocks A 1  to A 12  may be same as one another. Alternatively, the levels of the common voltages VCOM outputted to the driving blocks A 1  to A 12  may be different from one another. The levels of the common voltages VCOM outputted from the driving blocks DB 1  to DB 12  may be adjusted according to lengths of paths transmitting the common voltage VCOM from the driving blocks DB 1  to DB 12  to the display panel  100 . When the path transmitting the common voltage VCOM to a common electrode of the display panel  100  is long, the level of the common voltage VCOM may decrease as transmitting the path. Thus, when the path transmitting the common voltage VCOM to a common electrode of the display panel  100  is relatively long, the corresponding driving block may output the common voltage VCOM having a relatively high level such that the common voltages VCOM arrived to the common electrodes of the display panel  100  by the driving blocks DB 1  to DB 12  are the same as one another. 
     The driving blocks DB 1  to DB 12  may be integrated circuits connected to an end portion of the display panel. The driving blocks DB 1  to DB 12  may include data flexible circuit boards and the integrated circuits disposed on the data flexible circuit boards. 
     The driving block may include data voltage amplifiers outputting the data voltages to the data lines DL and at least one common voltage amplifier outputting the common voltage to the display panel  100 . 
     In an exemplary embodiment, for example, a first driving block DB 1  may include a plurality of data voltage amplifiers AM 11  to AM 16  outputting the data voltages VD 11  to VD 16  to the data lines DL 11  to DL 16  and a first common voltage amplifier AMC 1  outputting the common voltage VCOM 1  to a first common electrode CT 1  of the display panel  100 . 
     In an exemplary embodiment, for example, a second driving block DB 2  may include a plurality of data voltage amplifiers AM 21  to AM 26  outputting the data voltages VD 21  to VD 26  to the data lines DL 21  to DL 26  and a second common voltage amplifier AMC 2  outputting the common voltage VCOM 2  to a second common electrode CT 2  of the display panel  100 . 
       FIG. 7  is a circuit diagram illustrating an exemplary embodiment of a common voltage generator of the first driving block DB 1  of  FIG. 6A . 
     Referring to  FIGS. 1 to 7 , the driving block DB 1  to DB 12  may further include a decoder receiving the common voltage base signal COM from the timing controller  200  and generating the common voltage VCOM based on the common voltage base signal COM. 
     Each of the driving blocks DB 1  to DB 12  may include the decoder. In an exemplary embodiment, for example, the first driving block DB 1  may include a first decoder DEC 1  receiving a first common voltage base signal COM 1  for the first driving block DB 1  from the timing controller  200  and generating the first common voltage VCOM 1  based on the first common voltage base signal COM 1 . The first decoder DEC 1  may generate the first common voltage VCOM 1  between a high-level power voltage VDD and a ground voltage GND based on the first common voltage base signal COM 1 . 
     Although not shown in figures, the second driving block DB 2  may include a second decoder receiving a second common voltage base signal for the second driving block DB 2  from the timing controller  200  and generating the second common voltage VCOM 2  based on the second common voltage base signal. 
       FIG. 8  is a block diagram illustrating an exemplary embodiment of a feedback part  530  and a polarity converting part  540  of the data driver  500  of  FIG. 5 .  FIG. 9  is a circuit diagram illustrating an exemplary embodiment of the feedback part  530  of  FIG. 8 .  FIG. 10  is a timing diagram illustrating an exemplary embodiment of a waveform of a fed-back common voltage VCOMF of  FIG. 9 . 
     Referring to  FIGS. 1 to 10 , the data driver  500  may include the feedback part  530  and the polarity converting part  540 . The feedback part  530  may compare the fed-back common voltage VCOMF from the display panel  100  with reference voltages VCOMH and VCOML to generate comparing signals HS and LS. The polarity converting part  540  may convert the polarity inversion driving method of the display panel  100  based on the comparing signals HS and LS. 
     For example, each of the driving blocks DB 1  to DB 12  may include the feedback part  530  and the polarity converting part  540 . In an exemplary embodiment, for example, the first driving block DB 1  compares a fed-back common voltage from the first display block A 1  with the reference voltages VCOMH and VCOML, generates the comparing signals HS and LS and converts the polarity inversion driving method of the first display block Al based on the comparing signals HS and LS. For example, the second driving block DB 2  compares a fed-back common voltage from the second display block A 2  with the reference voltages VCOMH and VCOML, generates the comparing signals HS and LS and converts the polarity inversion driving method of the second display block A 2  based on the comparing signal HS and LS. As a result, the display blocks A 1  to A 12  may be driven in different polarity inversion driving methods. 
     In an exemplary embodiment, for example, the feedback part  530  may include a first comparator CMP 1  and a second comparator CMP 2 . The first comparator CMP 1  may include a first input terminal receiving the fed-back common voltage VCOMF, a second input terminal receiving a first reference voltage VCOMH which is greater than a target common voltage and an output terminal outputting a first comparing signal HS when the fed-back common voltage VCOMF is greater than the first reference voltage VCOMH. The second comparator CMP 2  may include a first input terminal receiving the fed-back common voltage VCOMF, a second input terminal receiving a second reference voltage VCOML which is less than the target common voltage and an output terminal outputting a second comparing signal LS when the fed-back common voltage VCOMF is less than the second reference voltage VCOML. 
     In an exemplary embodiment, for example, the first reference voltage VCOMH and the second reference voltage VCOML may represent a tolerance range of the common voltage VCOM. For example, the first reference voltage VCOMH may mean an upper limit of the tolerance range of the common voltage VCOM and the second reference voltage VCOML may mean a lower limit of the tolerance range of the common voltage VCOM. When the fed-back common voltage VCOMF is greater than the first reference voltage VCOMH, the first comparing signal HS representing that the fed-back common voltage VCOMF exceeds the upper limit of the tolerance range of the common voltage VCOM may be outputted. When the fed-back common voltage VCOMF is less than the second reference voltage VCOML, the second comparing signal LS representing that the fed-back common voltage VCOMF exceeds the lower limit of the tolerance range of the common voltage VCOM may be outputted. 
     When the first comparing signal HS or the second comparing signal LS is received, the polarity converting part  540  may convert the polarity inversion driving method of the display panel  100 . In an alternative embodiment, when both the first comparing signal HS and the second comparing signal LS are received, the polarity converting part  540  may convert the polarity inversion driving method of the display panel  100 . For example, the polarity converting part  540  may output a mode determining signal CS to convert the polarity of the display panel  100  based on the first comparing signal HS and the second comparing signal LS. 
     In an exemplary embodiment, for example, the polarity inversion driving methods may include a first mode and a second mode. The polarity converting part  540  may convert the polarity inversion driving methods between the first mode and the second mode according to the comparing signals HS and LS. 
     In another exemplary embodiment, for example, the polarity inversion driving methods may include the first mode, the second mode and a third mode. The polarity converting part  540  may convert the polarity inversion driving methods among the first mode, the second mode and the third mode according to the comparing signals HS and LS. 
       FIGS. 11A and 11B  are conceptual diagrams illustrating an exemplary embodiment of a polarity inversion driving method of a first mode.  FIGS. 12A and 12B  are conceptual diagrams illustrating an exemplary embodiment of a polarity inversion driving method of a second mode.  FIGS. 13A and 13B  are conceptual diagrams illustrating an exemplary embodiment of a polarity inversion driving method of a third mode. 
     Referring to  FIGS. 1 to 13B , the first mode may be an inversion method in which polarities of the data voltages are inverted every data line such as one column inversion method and one dot inversion method. Particularly, in the one dot inversion method, polarities of the data voltages are inverted every subpixel. The second mode may be an inversion method in which polarities of the data voltages are inverted every two data lines such as a two-columns inversion method and a two-by-one inversion method. Particularly, in the two-by-one dot inversion method, polarities of the data voltages are inverted every two data lines in the first direction D 1  and every subpixel in the second direction D 2 . The third mode may be an inversion method in which polarities of the data voltages are inverted every six data lines such as a six-columns inversion method and a six-by-one inversion method. Particularly, in the six-by-one dot inversion method, polarities of the data voltages are inverted every six data lines in the first direction D 1  and every subpixel in the second direction D 2 . When the display panel  100  has the non-staggered structure, the first to third modes may be the one column inversion method, the two columns inversion method and the six columns inversion method, respectively. When the display panel  100  has the staggered structure, the first to third modes may be the one dot inversion method, the two-by-one inversion method and the six by one inversion method, respectively. 
     The data driver  500  may include an amplifying part AP including a plurality of data voltage amplifiers PA 1  to PA 6  and NA 1  to NA 6 , a data channel part CHP including a plurality of data channels CH 1  to CH 12  and a multiplexer MUX disposed between the amplifying part AP and the data channel part CHP and determining connections between the data voltage amplifiers PA 1  to PA 6  and NA 1  to NA 6  and the data channels CH 1  to CH 12 . 
     The polarity converting part  540  may output the mode determining signal CS to the multiplexer MUX to convert the polarity inversion driving mode of the display panel  100 . 
     The amplifying part AP may include positive data voltage amplifiers PA 1  to PA 6  and negative data voltage amplifiers NA 1  to NA 6 . The positive data voltage amplifiers PA 1  to PA 6  and the negative data voltage amplifiers NA 1  to NA 6  may be alternately disposed each other as shown in  FIG. 11A . 
       FIG. 11A  may represent a polarity structure of the data driver  500  in a first frame in the first mode.  FIG. 11B  may represent a polarity structure of the data driver  500  in a second frame in the first mode. 
     As shown in  FIG. 11A , positive data voltages are outputted to first, third, fifth, seventh, ninth and eleventh data channels CH 1 , CH 3 , CH 5 , CH 7 , CH 9  and CH 11  and negative data voltages are outputted to second, fourth, sixth, eighth, tenth and twelfth data channels CH 2 , CH 4 , CH 6 , CH 8 , CH 10  and CH 12  in the first frame in the first mode by the operation of the multiplexer MUX. 
     As shown in  FIG. 11B , negative data voltages are outputted to first, third, fifth, seventh, ninth and eleventh data channels CH 1 , CH 3 , CH 5 , CH 7 , CH 9  and CH 11  and positive data voltages are outputted to second, fourth, sixth, eighth, tenth and twelfth data channels CH 2 , CH 4 , CH 6 , CH 8 , CH 10  and CH 12  in the second frame in the first mode by the operation of the multiplexer MUX. 
       FIG. 12A  may represent a polarity structure of the data driver  500  in a first frame in the second mode.  FIG. 12B  may represent a polarity structure of the data driver  500  in a second frame in the second mode. 
     As shown in  FIG. 12A , positive data voltages are outputted to first, second, fifth, sixth, ninth and tenth data channels CH 1 , CH 2 , CH 5 , CH 6 , CH 9  and CH 10  and negative data voltages are outputted to third, fourth, seventh, eighth, eleventh and twelfth data channels CH 3 , CH 4 , CH 7 , CH 8 , CH 11  and CH 12  in the first frame in the second mode by the operation of the multiplexer MUX. 
     As shown in  FIG. 12B , negative data voltages are outputted to first, second, fifth, sixth, ninth and tenth data channels CH 1 , CH 2 , CH 5 , CH 6 , CH 9  and CH 10  and positive data voltages are outputted to third, fourth, seventh, eighth, eleventh and twelfth data channels CH 3 , CH 4 , CH 7 , CH 8 , CH 11  and CH 12  in the second frame in the second mode by the operation of the multiplexer MUX. 
       FIG. 13A  may represent a polarity structure of the data driver  500  in a first frame in the third mode.  FIG. 13B  may represent a polarity structure of the data driver  500  in a second frame in the third mode. 
     As shown in  FIG. 13A , positive data voltages are outputted to first, second, third, fourth, fifth and sixth data channels CH 1 , CH 2 , CH 3 , CH 4 , CH 5  and CH 6  and negative data voltages are outputted to seventh, eighth, ninth, tenth, eleventh and twelfth data channels CH 7 , CH 8 , CH 9 , CH 10 , CH 11  and CH 12  in the first frame in the third mode by the operation of the multiplexer MUX. 
     As shown in  FIG. 13B , negative data voltages are outputted to first, second, third, fourth, fifth and sixth data channels CH 1 , CH 2 , CH 3 , CH 4 , CH 5  and CH 6  and positive data voltages are outputted to seventh, eighth, ninth, tenth, eleventh and twelfth data channels CH 7 , CH 8 , CH 9 , CH 10 , CH 11  and CH 12  in the second frame in the third mode by the operation of the multiplexer MUX. In addition to the operation of the multiplexer MUX changing connections between the data voltage amplifiers and the data channels, the arrangement of the data voltages VD 1  to VD 12  may change such that only the polarity of the data voltage supplied to each data channel is changed without changing of the amplitude of the data voltage thereof even if the modes (inversion methods) are changed as shown in  FIGS. 11A to 13B . 
     Referring again to  FIGS. 3A and 3B , during the first horizontal period when the gate signal is applied to the subpixels in the first row, if in the first mode (i.e., one-column inversion method), the turned-on subpixels R 12 , G 12 , B 12 , R 14 , G 14  and B 14  may have data voltages of (−), (+), (−), (−), (+) and (−) such that the common voltage VCOM may be oriented toward the negative polarity in the first row. Here, (−) means that the corresponding voltage has a negative value, and (+) means that the corresponding voltage has a positive value. 
     However, during the first horizontal period when the gate signal is applied to the subpixels in the first row, if in the second mode (i.e., two-columns inversion method), the turned-on subpixels R 12 , G 12 , B 12 , R 14 , G 14  and B 14  may have data voltages of (−), (+), (+), (+), (−) and (−) such that the polarity of the common voltage VCOM may be in equilibrium in the first row. In the similar way, during the second horizontal period when the gate signal is applied to the subpixels in the second row, the polarity of the common voltage VCOM may be in equilibrium in the second row in the second mode (i.e., two-columns inversion method). 
     In addition, during the first horizontal period when the gate signal is applied to the subpixels in the first row, if in the third mode (i.e., six columns inversion method), the turned-on subpixels R 12 , G 12 , B 12 , R 14 , G 14  and B 14  may have data voltages of (+), (+), (+), (−), (−) and (−) such that the polarity of the common voltage VCOM may be in equilibrium in the first row. In the similar way, during the second horizontal period when the gate signal is applied to the subpixels in the second row, the polarity of the common voltage VCOM may be in equilibrium in the second row in the third mode. 
     Referring again to  FIGS. 4A and 4B , during the first horizontal period when the gate signal is applied to the subpixels in the first row, the turned-on subpixels G 11 , R 12 , B 12 , G 13 , R 14  and B 14  may have data voltages of (−), (−), (−), (−), (−) and (−) such that the common voltage VCOM may be oriented toward the negative polarity in the first row in the first mode. 
     However, during the first horizontal period when the gate signal is applied to the subpixels in the first row, if in the second mode, the turned-on subpixels G 11 , R 12 , B 12 , G 13 , R 14  and B 14  may have data voltages of (+), (−), (+), (−), (+) and (−) such that the polarity of the common voltage VCOM may be in equilibrium in the first row. In the similar way, during the second horizontal period when the gate signal is applied to the subpixels in the second row, the polarity of the common voltage VCOM may be in equilibrium in the second row in the second mode. 
     In addition, during the first horizontal period when the gate signal is applied to the subpixels in the first row, if in the third mode, the turned-on subpixels G 11 , R 12 , B 12 , G 13 , R 14  and B 14  may have data voltages of (+), (+), (+), (−), (−) and (−) such that the polarity of the common voltage VCOM may be in equilibrium in the first row. In the similar way, during the second horizontal period when the gate signal is applied to the subpixels in the second row, the polarity of the common voltage VCOM may be in equilibrium in the second row in the third mode. 
     For example, the polarity converting part  540  may convert the polarity inversion driving method between the first mode and the second mode according to the comparing signals HS and LS or the mode determining signal CS which is generated based on the comparing signals HS and LS. In an exemplary embodiment, polarities of the data voltages are inverted every data line in the first mode and polarities of the data voltages are inverted every two data lines in the second mode. In another exemplary embodiment, polarities of the data voltages are inverted every data line in the first mode and polarities of the data voltages are inverted every six data lines in the second mode. In still another exemplary embodiment, polarities of the data voltages are inverted every two data lines in the first mode and polarities of the data voltages are inverted every six data lines in the second mode. 
     For example, the polarity converting part  540  may convert the polarity inversion driving method among the first mode, the second mode and the third mode according to the comparing signals HS and LS or the mode determining signal CS which is generated based on the comparing signals HS and LS. In an exemplary embodiment, polarities of the data voltages are inverted every data line in the first mode, polarities of the data voltages are inverted every two data lines in the second mode and polarities of the data voltages are inverted every six data lines in the second mode. 
     However, the polarity inversion driving method of the display panel  100  may not be limited to the one column inversion method, the two columns inversion method and the six columns inversion method. 
     According to the above exemplary embodiments, the driving blocks DB 1  to DB 12  of the data driver  500  generates the common voltages and outputs the common voltages to the display blocks A 1  to A 12  of display panel  100  such that the uniformity of the common voltage VCOM may be enhanced. 
     In addition, by converting the polarity inversion driving method of the display panel  100  using a waveform of the fed-back common voltage VCOMF when the distortion of the common voltage VCOM occurs, the distortion of the common voltage VCOM may be reduced. 
     As a result, the level of the common voltage VCOM may be stabilized such that the display quality of the display panel  100  may be enhanced. 
       FIG. 14  is a circuit diagram illustrating an exemplary embodiment of a feedback part  530 A of a data driver  500  of a display apparatus according to the inventive concept.  FIG. 15  is a timing diagram illustrating an exemplary embodiment of a waveform of a fed-back common voltage VCOMF of  FIG. 14 . 
     The display apparatus according to the exemplary embodiment is substantially the same as the display apparatus of the exemplary embodiments explained referring to  FIGS. 1 to 13B  except for the structure of the feedback part. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the exemplary embodiments of  FIGS. 1 to 13B  and any repetitive explanation concerning the above elements will be omitted. 
     Referring to  FIGS. 1 to 8 and 11A to 15 , the display apparatus includes a display panel  100  and a display panel driver. The display panel driver includes a timing controller  200 , a gate driver  300 , a gamma reference voltage generator  400  and a data driver  500 . 
     The data driver  500  receives the second control signal CONT 2  and the data signals DATA from the timing controller  200 , and receives the gamma reference voltages VGREF from the gamma reference voltage generator  400 . The data driver  500  converts the data signals DATA into data voltages VD having an analog type using the gamma reference voltages VGREF. The data driver  500  outputs the data voltages VD to the data lines DL. 
     The data driver  500  may receive the common voltage base signal COM from the timing controller  200 . The data driver  500  generates a common voltage VCOM based on the common voltage base signal COM and outputs the common voltage VCOM to the display panel  100 . 
     The data driver  500  may include the feedback part  530 A and the polarity converting part  540 . The feedback part  530 A may compare the fed-back common voltage VCOMF from the display panel  100  with a reference voltage VCOMH 1 , VCOMH 2 , VCOML 1  and VCOML 2  to generate comparing signals HS 1 , HS 2 , LS 1  and LS 2 . The polarity converting part  540  may convert the polarity inversion driving method of the display panel  100  based on the comparing signals HS 1 , HS 2 , LS 1  and LS 2 . 
     For example, each of the driving blocks DB 1  to DB 12  may include the feedback part  530 A and the polarity converting part  540 . 
     In an exemplary embodiment, for example, the feedback part  530 A may include a first comparator CMP 1 , a second comparator CMP 2 , a third comparator CMP 3  and a fourth comparator CMP 4 . 
     The first comparator CMP 1  may include a first input terminal receiving the fed-back common voltage VCOMF, a second input terminal receiving a first reference voltage VCOMH 1  which is greater than a target common voltage and an output terminal outputting a first comparing signal HS 1  when the fed-back common voltage VCOMF is greater than the first reference voltage VCOMH 1 . 
     The second comparator CMP 2  may include a first input terminal receiving the fed-back common voltage VCOMF, a second input terminal receiving a second reference voltage VCOML 1  which is less than the target common voltage and an output terminal outputting a second comparing signal LS 1  when the fed-back common voltage VCOMF is less than the second reference voltage VCOML 1 . 
     The third comparator CMP 3  may include a first input terminal receiving the fed-back common voltage VCOMF, a second input terminal receiving a third reference voltage VCOMH 2  which is greater than the first reference voltage VCOMH 1  and an output terminal outputting a third comparing signal HS 2  when the fed-back common voltage VCOMF is greater than the third reference voltage VCOMH 2 . 
     The fourth comparator CMP 4  may include a first input terminal receiving the fed-back common voltage VCOMF, a second input terminal receiving a fourth reference voltage VCOML 2  which is less than the second reference voltage VCOML 1  and an output terminal outputting a fourth comparing signal LS 2  when the fed-back common voltage VCOMF is less than the fourth reference voltage VCOML 2 . 
     In an exemplary embodiment, for example, the first reference voltage VCOMH 1  and the second reference voltage VCOML 1  may represent a first tolerance range of the common voltage VCOM. For example, the first reference voltage VCOMH 1  may mean an upper limit of the first tolerance range of the common voltage VCOM and the second reference voltage VCOML 1  may mean a lower limit of the first tolerance range of the common voltage VCOM. 
     In an exemplary embodiment, for example, the third reference voltage VCOMH 2  and the fourth reference voltage VCOML 2  may represent a second tolerance range of the common voltage VCOM. For example, the third reference voltage VCOMH 2  may mean an upper limit of the second tolerance range of the common voltage VCOM and the fourth reference voltage VCOML 2  may mean a lower limit of the second tolerance range of the common voltage VCOM. 
     When the first comparing signal HS 1  or the second comparing signal LS 1  is received, the polarity converting part  540  may convert the polarity inversion driving method of the display panel  100 . When the third comparing signal HS 2  or the fourth comparing signal LS 2  is received, the polarity converting part  540  may convert the polarity inversion driving method of the display panel  100  in a different way from when the first comparing signal HS 1  or the second comparing signal LS 1  is received. 
     In an exemplary embodiment, for example, the polarity inversion driving methods may include a first mode and a second mode. The polarity converting part  540  may convert the polarity inversion driving methods between the first mode and the second mode according to the comparing signal HS 1 , LS 1 , HS 2  and LS 2 . 
     In another exemplary embodiment, for example, the polarity inversion driving methods may include the first mode, the second mode and a third mode. The polarity converting part  540  may convert the polarity inversion driving methods among the first mode, the second mode and the third mode according to the comparing signal HS 1 , LS 1 , HS 2  and LS 2 . 
     In this way, the data driver  500  may manage the distortion of the common voltage VCOM in various levels. The data driver  500  may differently convert the polarity inversion driving methods of the display panel  100  according to the degree of the distortion of the common voltage VCOM to compensate the distortion of the common voltage VCOM. 
     According to an exemplary embodiment, the driving blocks DB 1  to DB 12  of the data driver  500  generates the common voltages and outputs the common voltages to the display blocks A 1  to A 12  of display panel  100  such that the uniformity of the common voltage VCOM may be enhanced. 
     In addition, by converting the polarity inversion driving method of the display panel  100  using a waveform of the fed-back common voltage VCOMF when the distortion of the common voltage VCOM occurs, the distortion of the common voltage VCOM may be reduced. 
     As a result, the level of the common voltage VCOM may be stabilized such that the display quality of the display panel  100  may be enhanced. 
       FIG. 16  is a block diagram illustrating an exemplary embodiment of a feedback part  210  and a polarity converting part  220  of a timing controller  200  of a display apparatus according to the inventive concept. 
     The display apparatus according to the exemplary embodiment is substantially the same as the display apparatus of the exemplary embodiments explained referring to  FIGS. 1 to 13B  except that the timing controller  200  includes the feedback part  210  and the polarity converting part  220 . Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment of  FIGS. 1 to 13B  and any repetitive explanation concerning the above elements will be omitted. 
     Referring to  FIGS. 1 to 7, 9 to 13B and 16 , the display apparatus includes a display panel  100  and a display panel driver. The display panel driver includes a timing controller  200 , a gate driver  300 , a gamma reference voltage generator  400  and a data driver  500 . 
     The data driver  500  receives the second control signal CONT 2  and the data signals DATA from the timing controller  200 , and receives the gamma reference voltages VGREF from the gamma reference voltage generator  400 . The data driver  500  converts the data signals DATA into data voltages VD having an analog type using the gamma reference voltages VGREF. The data driver  500  outputs the data voltages VD to the data lines DL. 
     The data driver  500  may receive the common voltage base signal COM from the timing controller  200 . The data driver  500  generates a common voltage VCOM based on the common voltage base signal COM and outputs the common voltage VCOM to the display panel  100 . 
     The timing controller  200  may include the feedback part  210  and the polarity converting part  220 . The feedback part  210  may compare the fed-back common voltage VCOMF from the display panel  100  with a reference voltage VCOMH and VCOML to generate comparing signals HS and LS. The polarity converting part  220  may convert the polarity inversion driving method of the display panel  100  based on the comparing signals HS and LS. 
     For example, the timing controller  200  may include a plurality of the feedback parts  210  and a plurality of the polarity converting parts  220  corresponding to the plurality of the display blocks A 1  to A 12 . 
     Alternatively, the timing controller  200  may include the single feedback part  210  and the single polarity converting part  220 . 
     In an exemplary embodiment, for example, the feedback part  210  may include a first comparator CMP 1  and a second comparator CMP 2 . The first comparator CMP 1  may include a first input terminal receiving the fed-back common voltage VCOMF, a second input terminal receiving a first reference voltage VCOMH which is greater than a target common voltage and an output terminal outputting a first comparing signal HS when the fed-back common voltage VCOMF is greater than the first reference voltage VCOMH. The second comparator CMP 2  may include a first input terminal receiving the fed-back common voltage VCOMF, a second input terminal receiving a second reference voltage VCOML which is less than the target common voltage and an output terminal outputting a second comparing signal LS when the fed-back common voltage VCOMF is less than the second reference voltage VCOML. 
     When the first comparing signal HS or the second comparing signal LS is received, the polarity converting part  220  may convert the polarity inversion driving method of the display panel  100 . Alternatively, when both the first comparing signal HS and the second comparing signal LS are received, the polarity converting part  220  may convert the polarity inversion driving method of the display panel  100 . For example, the polarity converting part  220  may output a mode determining signal CS to convert the polarity of the display panel  100  based on the first comparing signal HS and the second comparing signal LS. 
     In an exemplary embodiment, for example, the polarity inversion driving methods may include a first mode and a second mode. The polarity converting part  220  may convert the polarity inversion driving methods between the first mode and the second mode according to the comparing signals HS and LS. 
     In another exemplary embodiment, for example, the polarity inversion driving methods may include the first mode, the second mode and a third mode. The polarity converting part  220  may convert the polarity inversion driving methods among the first mode, the second mode and the third mode according to the comparing signals HS and LS. 
     The polarity converting part  220  may output the mode determining signal CS to the multiplexer MUX to convert the polarity inversion driving mode of the display panel  100 . 
     According to an exemplary embodiment, the driving blocks DB 1  to DB 12  of the data driver  500  generates the common voltages and outputs the common voltages to the display blocks A 1  to A 12  of display panel  100  such that the uniformity of the common voltage VCOM may be enhanced. 
     In addition, by converting the polarity inversion driving method of the display panel  100  using a waveform of the fed-back common voltage VCOMF when the distortion of the common voltage VCOM is generated, the distortion of the common voltage VCOM may be reduced. 
     As a result, the level of the common voltage VCOM may be stabilized such that the display quality of the display panel  100  may be enhanced. 
     According to exemplary embodiments of the display apparatus and the method of driving the display panel, the level of the common voltage is stabilized such that the display quality of the display panel may be enhanced. 
     The foregoing is illustrative of the inventive concept and is not to be construed as limiting thereof. Although a few exemplary embodiments of the inventive concept have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims. The inventive concept is defined by the following claims, with equivalents of the claims to be included therein.