Patent Publication Number: US-11664061-B2

Title: Memory devices including processing elements, and memory systems including memory devices

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of, and claims priority under 35 U.S.C. § 120 to, U.S. patent application Ser. No. 16/903,055, filed Jun. 16, 2020, which in turn, claims the benefit of priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2019-0138775, filed on Nov. 1, 2019, in the Korean Intellectual Property Office, and the disclosure of each above-identified application is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The present disclosure relates to memory devices, and more particularly, to memory devices including a Processing Elements (PE) and to memory systems including such memory devices. 
     In a general computer system, a host accesses a memory device to perform a computational operation on data stored in the memory device. Recently, in accordance with increasing performance requirements for computer systems, memory devices such as Processing In Memory or Processor In Memory (PIM) have been developed to perform some of the computational operations of a host through internal processing. Such a memory device may include a memory cell array and a PE. For example, the memory cell array may include Dynamic Random Access Memory (DRAM) cells. Since a DRAM cell is a memory that determines data by charge stored in a capacitor, a refresh operation is periodically performed to maintain data stored in the DRAM cell. 
     SUMMARY 
     According to some aspects of the inventive concepts, there is provided a memory device including a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which at least one wordline included in each of the plurality of banks is activated and configured to control a refresh operation in which at least one bank of the plurality of banks is refreshed, based on a PE enable signal configured to enable selectively the at least one PE. 
     According to some aspects of the inventive concepts, there is provided a memory device including a memory cell array including a plurality of banks, a plurality of Processing Elements (PEs) respectively connected to the plurality of banks, a refresh control unit generating refresh signals for controlling refresh operations respectively on the plurality of banks, and an active control unit activating a wordline included in at least one selected bank from the plurality of banks according to an active command and according to the refresh signals during a PE enable mode in which the plurality of PEs are enabled. 
     According to another aspect of the inventive concept, there is provided a memory system including a memory device including a plurality of banks and a plurality of Processing Elements (PEs), and a memory controller providing the memory device with an active command and a refresh command, wherein the memory device activates wordlines included in each of the plurality of banks in response to receiving the active command during a PE enable mode in which the plurality of PEs are enabled. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG.  1    is a block diagram illustrating a memory system according to some embodiments of the inventive concept; 
         FIG.  2    is a block diagram illustrating a memory device according to some embodiments of the inventive concept; 
         FIG.  3    is a block diagram illustrating a bank and a Processing Element (PE) according to some embodiments of the inventive concept; 
         FIG.  4    is a timing diagram illustrating an operation of a memory device in a PE enable mode, according to some embodiments of the inventive concept; 
         FIG.  5    is a block diagram illustrating in detail a control logic according to some embodiments of the inventive concept; 
         FIG.  6    illustrates a bank selection table according to some embodiments of the inventive concepts; 
         FIG.  7    is a block diagram illustrating in detail a control logic according to some embodiments of the inventive concepts; 
         FIG.  8    is a block diagram illustrating a memory system according to some embodiments of the inventive concepts; 
         FIG.  9    is a block diagram illustrating a memory device according to some embodiments of the inventive concepts; 
         FIG.  10    illustrates a bank selection table according to some embodiments of the inventive concepts; 
         FIG.  11    illustrates a bank selection table according to some embodiments of the inventive concepts; 
         FIG.  12    is a block diagram illustrating a memory system according to some embodiments of the inventive concepts; 
         FIG.  13    is a block diagram illustrating a bank and a PE according to some embodiments of the inventive concepts; 
         FIG.  14    is a block diagram illustrating a memory device according to some embodiments of the inventive concepts; 
         FIG.  15    is a flowchart illustrating operations between a memory device and a memory controller, according to some embodiments of the inventive concepts; 
         FIG.  16    is a flowchart illustrating operations between a memory device and a memory controller, according to some embodiments of the inventive concepts; and 
         FIG.  17    is a block diagram illustrating a mobile system to which a memory device is applied, according to some embodiments of the inventive concepts. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, aspects of the inventive concepts and some examples of embodiments thereof will be described in detail with reference to the accompanying drawings. 
       FIG.  1    is a block diagram illustrating a memory system  10  according to some embodiments of the inventive concepts. 
     Referring to  FIG.  1   , the memory system  10  may include a memory device  100  and a memory controller  200 . The memory device  100  may include a memory cell array  110 , a Processing Element (PE)  120 , and a control logic  130 . The memory controller  200  may include a PE enable mode controller  210 . In some embodiments, the memory device  100  may be implemented as a memory chip or a memory module, and the memory controller  200  may be implemented as part of a host. In some embodiments, the memory device  100  and the memory controller  200  may be implemented together in one memory module. 
     The memory controller  200  may control normal memory operations, such as a write operation, a read operation, and the like, on the memory cell array  110  by providing the memory device  100  with various types of signals. In detail, the memory controller  200  may write data DATA to the memory device  100  or may read data DATA from the memory device  100  by providing the memory device  100  with a command CMD and an address ADDR. The memory controller  200  may further provide the memory device  100  with a clock signal CLK. 
     The command CMD may include an active command (e.g., ACT 1  of  FIG.  4   ) for changing the memory cell array  110  to an active state to write or read data. The memory device  100  may activate a row included in the memory cell array  110 , i.e., a wordline, in response to the active command. Also, the command CMD may include a precharge command (e.g., PRECHARGE1 of  FIG.  4   ) for changing the memory cell array  110  from the active state to a standby state after writing or reading of data is completed. In addition, the command CMD may include a refresh command (e.g., BANK_A REF of  FIG.  4   ) for controlling a refresh operation on the memory cell array  110 . 
     The memory controller  200  may control an internal processing operation through the PE  120  by providing the memory device  100  with various types of signals. In some embodiments, the memory controller  200  may determine a PE enable mode to control the internal processing operation of the PE  120 , and the memory controller  200  may generate a PE enable command indicating the PE enable mode according to the determined PE enable mode. In some embodiments, the memory controller  200  may provide the memory device  100  with a signal indicating the PE enable mode through a combination of the command CMD, the address ADDR, and/or the clock signal CLK. 
     In some embodiments, the memory controller  200  may include the PE enable mode controller  210 . The PE enable mode controller  210  may determine the PE enable mode for enabling an operation of the PE  120 . The PE enable mode controller  210  may be implemented as hardware and/or software. For example, in some embodiments the memory controller  200  may include a memory (not shown in  FIG.  1   ), with the memory loaded with instructions for embodying the PE enable mode controller  210 . The memory controller  200  may also include a processor (not shown in  FIG.  1   ), with the processor configured to perform a PE enable mode control operation by accessing the memory to execute the instructions. 
     The memory device  100  may include various types of memories, for example, may include Dynamic Random Access Memory (DRAM) such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate (LPDDR) SDRAM, Graphic Double Data Rate (GDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), and the like. However, embodiments of the inventive concepts are not limited thereto, and, for example, the memory device  100  may include a nonvolatile memory such as flash memory, Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), Phase change RAM (PRAM), Resistive RAM (ReRAM), and the like. 
     The memory cell array  110  may include a plurality of banks BKs, and each of the plurality of banks BKs may include a plurality of memory cells. In detail, the plurality of memory cells may be respectively located at points where a plurality of wordlines and a plurality of bitlines intersect with each other. The memory cell array  110  may store internal processing data. Here, the internal processing data may include data on which a computational operation is to be performed by the PE  120  and/or data that is generated as a result of performing the computational operation by the PE  120 . 
     The PE  120  may perform a data operation on data stored in the memory cell array  110  and/or data received from the memory controller  200 . The PE  120  may store a result of the data operation in the memory cell array  110  or may provide the memory controller  200  with the result of the data operation. Therefore, the PE  120  may also be referred to as an operational unit or Processor In Memory (PIM). For example, the PE  120  may be an Arithmetic Logic Unit (ALU) or Multiply-Accumulator (MAC). In some embodiments, PE  120  may be configured to perform data operations such as data invert, data shift, data swap, data compare, and the like; logical operations such as AND, XOR, and the like; and/or mathematical operations, such as addition, subtraction, and the like. 
     The PE  120  may include a plurality of PEs. In some embodiments, the number of the plurality of PEs may equal or be the same as the number of the plurality of banks BKs included in the memory cell array  110 . Here, each of the plurality of PEs may access a corresponding or respective bank to perform a data operation. In some embodiments, the number of the plurality of PEs may be less than the number of the plurality of banks BKs included in the memory cell array  110 . Here, each of the plurality of PEs may access at least two corresponding banks to perform a data operation. For example, two adjacent banks may share one PE. For example, a bank group including a plurality of banks may share one PE. However, the inventive concepts are not limited thereto, and in some embodiments the memory device  100  may include one PE  120 , and the one PE  120  may access a plurality of banks BKs to perform a data operation. 
     The control logic  130  may control an active operation activating at least one wordline selected from wordlines included in each of the plurality of banks BKs, based on a PE enable signal. In detail, the control logic  130  may activate wordlines included in each of the plurality of banks BKs in response to the active command in the PE enable mode in which the PE enable signal is activated. Therefore, since PEs connected to the plurality of banks BKs may perform data operations, a data operation speed may be improved. The control logic  130  may activate a wordline included in one of the plurality of banks BKs in response to the active command in a PE disable mode in which the PE enable signal is inactivated. 
     Also, the control logic  130  may control the active operation activating at least one wordline selected from wordlines included in each of the plurality of banks BKs and a refresh operation on the plurality of banks BKs, on based on the PE enable signal and a refresh signal. In detail, the control logic  130  may determine banks on which the refresh operation is not performed, among the plurality of banks BKs, based on the refresh signal. The control logic  130  may activate wordlines included in each of the banks on which the refresh operation is not performed, among the plurality of banks BKs, in response to the active command in the PE enable mode in which the PE enable signal is activated. Therefore, even when the refresh operation is performed on a few banks among the plurality of banks BKs, as many wordlines as possible may be activated, thereby preventing performance degradation of the memory device  100  and the memory system  10  including the same in the PE enable mode. 
     Also, the control logic  130  may transmit, to the PE  120 , information about a bank on which the refresh operation is performed, in the PE enable mode. Therefore, the PE  120  may perform a data operation on the remaining banks except for the bank on which the refresh operation is performed, in the PE enable mode. In detail, the PE  120  may perform the data operation on memory cells connected to a wordline included in each of the banks on which the refresh operation is not performed, in the PE enable mode. 
       FIG.  2    is a block diagram illustrating a memory device  100  according to some embodiments of the inventive concepts. 
     Referring to  FIG.  2   , the memory device  100  may include first through fourth banks BANK_A through BANK_D, first through fourth PEs PEa through PEd, and a control logic  130 . The memory device  100  may correspond to the memory device  100  of  FIG.  1   . In some embodiments, the first through fourth PEs PEa through PEd may be respectively connected to the first through fourth banks BANK_A through BANK_D, and each of the first through fourth PEs PEa through PEd may perform operations on pieces of data respectively stored in the first through fourth banks BANK_A through BANK_D. 
       FIG.  3    is a block diagram illustrating a bank BK and a PE, according to some embodiments of the inventive concepts. 
     Referring to  FIG.  3   , the bank BK may be connected to a row decoder XDEC and a column decoder YDEC. The bank BK may correspond to one of the first through fourth banks BANK_A through BANK_D of  FIG.  2   . In detail, the bank BK may include a plurality of wordlines WL connected to the row decoder XDEC, a plurality of bitlines BL connected to the column decoder YDEC, and a plurality of memory cells MC respectively arranged at intersections between the plurality of wordlines WL and the plurality of bitlines BL. An input/output sense amplifier IOSA may sense and amplify data read from the bank BK. According to some embodiments, positions of the column decoder YDEC and the input/output sense amplifier IOSA may be changed from that shown in  FIG.  3   . The PE may be connected to the input/output sense amplifier IOSA and may perform an operation on data received from the input/output sense amplifier IOSA. In some embodiments, the PE may be connected to the column decoder YDEC and may perform an operation on data received from the column decoder YDEC. 
     Referring to  FIG.  2    again, the control logic  130  may generate wordline enable signals WL_EN for activating wordlines included in each of the first through fourth banks BANK_A through BANK_D based on a PE enable signal PE_EN. The wordline enable signals WL_EN may include first through fourth wordline enable signals WL_EN1 through WL_EN4 respectively corresponding to the first through fourth banks BANK_A through BANK_D. In detail, the control logic  130  may include an active control unit  131  and a refresh control unit  132 . Hereinafter, detailed operations of the active control unit  131  and the refresh control unit  132  will be described. 
     The active control unit  131  may control an active operation in which wordlines included in each of the first through fourth banks BANK_A through BANK_D are activated, based on the PE enable signal PE_EN, an active command ACT, a bank address BA, and a refresh signal REF_CON. Hereinafter, operations of the active control unit  131  in a PE enable mode in which the PE enable signal PE_EN is activated and a PE disable mode in which the PE enable signal PE_EN is inactivated will be respectively described. 
     In the PE enable mode, the active control unit  131  may generate the wordline enable signals WL_EN to activate the wordlines included in each of the first through fourth banks BANK_A through BANK_D in response to the active command ACT. For example, the active control unit  131  may activate all of the first through fourth wordline enable signals WL_EN1 through WL_EN4 respectively applied to the first through fourth banks BANK_A and BANK_D. 
     Also, in the PE enable mode, the active control unit  131  may determine a bank from among the first through fourth banks BANK_A through BANK_D on which a refresh operation is performed, based on the refresh signal REF_CON. Here, the active control unit  131  may generate the wordline enable signals WL_EN so as not to activate a wordline included in the bank on which the refresh operation is performed, but to activate a wordline included in a bank on which the refresh operation is not performed, in response to the active command ACT. For example, if the refresh operation is to be performed on the second bank BANK_B, then the active control unit  131  may generate wordline enable signals WL_EN1, WL_EN2, and WL_EN4, so as to activate wordlines included in respective first, third, and fourth banks BANK_A, BANK_C, and BANK_D. Further, the active control  131  may refrain from generating a wordline enable signal WL_EN2, thereby preventing activation of wordlines included in the second bank BANK_B. 
     In the PE disable mode, the active control unit  131  may generate the wordline enable signals WL_EN to activate a wordline included in one of the first through fourth banks BANK_A through BANK_D in response to the active command ACT. For example, the active control unit  131  may select the first bank BANK_A from the first through fourth banks BANK_A through BANK_D based on the bank address BA, activate the first wordline enable signal WL_EN1 applied to the first bank BANK_A, and inactivate the second through fourth wordline enable signals WL_EN2 through WL_EN4 respectively applied to the second through fourth banks BANK_B through BANK_D. 
     The refresh control unit  132  may generate the refresh signal REF_CON to control the refresh operation on the first through fourth banks BANK_A through BANK_D, based on the bank address BA and a refresh command REF. For example, the refresh signal REF_CON may include first through fourth refresh signals respectively corresponding to the first through fourth banks BANK_A through BANK_D. 
     In some embodiments, the refresh operation may include a normal refresh operation that is performed in response to a refresh command and a refresh address received from the memory controller  200 . For example, the refresh control unit  132  may generate the refresh signal REF_CON to sequentially perform the refresh operation on the first through fourth banks BANK_A through BANK_D according to the bank address BA, in response to the refresh command REF. In an embodiment, the refresh operation may include an auto refresh or self-refresh operation that internally generates a refresh address. For example, the refresh control unit  132  may generate the refresh signal REF_CON to sequentially perform the refresh operation on the first through fourth banks BANK_A through BANK_D according to the refresh address that is internally generated. 
       FIG.  4    is a timing diagram illustrating an operation of the memory device  100  in a PE enable mode, according to an embodiment of the inventive concept. 
     Referring to  FIGS.  1  through  4   , the memory device  100  may receive a command CMD from the memory controller  200 . For example, the memory device  100  may sequentially receive, from the memory controller  200 , a PE enable command PE_EN CMD, a first active command ACT 1 , a first precharge command PRECHARGE1, a first bank refresh command BANK_A REF, a second active command ACT 2 , and a second precharge command PRECHARGE2. 
     In response to the PE enable command PE_EN CMD indicating PE enable, a PE enable entry signal PE_EN_ENTRY may be activated. When the PE enable entry signal PE_EN_ENTRY is activated, a PE enable signal PE_EN may transition from logic low to logic high. However, the present disclosure is not limited thereto, and the PE enable signal PE_EN may immediately transition from the logic low to the logic high in response to the PE enable command PE_EN CMD. In other words, in some embodiments, the PE enable entry signal PE_EN_ENTRY may be optional or omitted. Herein, a section in which the PE enable signal PE_EN is logic high may be defined as a “PE enable mode,” and a section in which the PE enable signal PE_EN is logic low may be defined as a “PE disable mode” or a “normal mode.” 
     In the PE enable mode, in response to the first active command ACT 1 , all of first through fourth wordline enable signals WL_EN1 through WL_EN4 may transition to logic high at a first time point t1. Therefore, wordlines included in each of the first through fourth banks BANK_A through BANK_D may be activated. Although not shown, the memory device  100  may receive a read command and/or a write command after receiving the first active command ACT 1 . The memory device  100  may perform a read operation on memory cells connected to an activated wordline in response to the read command, and the PE  120  may perform a data operation on read data. Also, the memory device  100  may write a result of the data operation or data received from the memory controller  200  to the activated wordline in response to the write command. 
     In response to the first precharge command PRECHARGE1, all of the first through fourth wordline enable signals WL_EN1 through WL_EN4 may transition to logic low at a second time point t2. Therefore, the wordlines included in each of the first through fourth banks BANK_A through BANK_D may be inactivated. Here, a section between the first time point t1 and the second time point t2 may be regarded as a section in which the first active command ACT 1  is executed, and thus, may be defined as an “active section” or an “active operation section.” 
     In response to the first bank refresh command BANK_A REF, a first refresh signal REF_A corresponding to the first bank BANK_A may transition to logic high. Therefore, the first wordline enable signal WL_EN1 corresponding to the first bank BANK_A may transition to logic high. The first refresh signal REF_A may maintain being logic high for a refresh period, and a section in which the first refresh signal REF_A is logic high may be defined as a “refresh section.” When the first refresh signal REF_A transitions to logic low, the first wordline enable signal WL_EN1 corresponding to the first bank BANK_A may also transition to logic low. 
     In response to the second active command ACT 2 , the second through fourth wordline enable signals WL_EN2 through WL_EN4 may transition to logic high at a third time point t3. Therefore, wordlines included in each of the second through fourth banks BANK_B through BANK_D may be activated. Although not shown, the memory device  100  may receive a read command or a write command after receiving the second active command ACT 2 . Therefore, the memory device  100  may perform a read operation or a write operation on memory cells connected to an activated wordline and perform a data operation on the memory cells through the PE  120 . 
     According to some embodiments, in the refresh section in which the first refresh signal REF_A is logic high, the active control unit  131  may interrupt an active operation on the first bank BANK_A on which the refresh operation is performed and may perform the active operation only on the second through fourth banks BANK_B through BANK_D on which the refresh operation is not performed. As described above, the active control unit  131  may selectively activate the wordlines included in each of the first through fourth banks BANK_A through BANK_D based on the refresh signal REF_CON. 
     In response to the second precharge command PRECHARGE2, all of the second through fourth wordline enable signals WL_EN2 through WL_EN4 may transition to logic low at a fourth time point t4. Therefore, wordlines included in each of the second through fourth banks BANK_B through BANK_D may be inactivated. 
       FIG.  5    is a block diagram illustrating in detail a control logic  130   a  according to some embodiments of the inventive concepts. 
     Referring to  FIG.  5   , the control logic  130   a  may include an active control unit  131 , a refresh control unit  132 , and wordline enable controllers  133 . The active control unit  131  may include a bank selector  1311  and bank active controllers  1312 . The refresh control unit  132  may include a bank selector  1321  and refresh controllers  1322 . The control logic  130   a  may correspond to the example embodiment of the control logic  130  shown in  FIG.  2   . Hereinafter, the control logic  130   a  will be described with reference to  FIGS.  2 ,  5  and  6   . 
     The bank selector  1311  may generate a bank selection signal BKsel1 selecting at least one bank from a plurality of banks based on a PE enable signal PE_EN and a bank address BA. For example, when the PE enable signal PE_EN is activated, the bank selector  1311  may generate the bank selection signal BKsel1 to select all of the plurality of banks. When the PE enable signal PE_EN is inactivated or not activated, the bank selector  1311  may generate the bank selection signal BKsel1 to select one of the plurality of banks according to the bank address BA. Hereinafter, a bank selection operation will be described with reference to  FIG.  6     
       FIG.  6    illustrates a bank selection table TA1 according to some embodiments of the inventive concepts. 
     Referring to  FIG.  6   , a bank address BA may be a 2-bit signal including BA0 and BA1. For example, the bank address BA may be generated by decoding the address ADDR received from the memory controller  200 . For example, in a PE disable mode, the bank selector  1311  may select a first bank BANK_A when the bank address BA is “00,” select a second bank BANK_B when the bank address BA is “01,” select a third bank BANK_C when the bank address BA is “10,” and select a fourth bank BANK_D when the bank address BA is “11.” In a PE enable mode, the bank selector  1311  may select all of the first through fourth banks BANK_A through BANK_D. 
     Referring to  FIG.  5    again, the bank active controllers  1312  may respectively correspond to a plurality of banks. For example, when the plurality of banks includes first through fourth banks (e.g., BANK_A through BANK_D of  FIG.  2   ), the bank active controllers  1312  may include four bank active controllers respectively corresponding to the first through fourth banks. The bank active controllers  1312  may generate an active control signal ACT_CON based on an active command ACT and the bank selection signal BKsel1. In detail, the bank active controllers  1312  may generate the active control signal ACT_CON to activate a wordline included in at least one bank selected according to the bank selection signal BKsel1, in response to the active command ACT. 
     The bank selector  1321  may generate a bank selection signal BKsel2 selecting at least one from a plurality of banks based on the bank address BA. The refresh controllers  1322  may respectively correspond to a plurality of banks. For example, when the plurality of banks includes first through fourth banks (e.g., BANK_A through BANK_D of  FIG.  2   ), the refresh controllers  1322  may include four refresh controllers respectively corresponding to the first through fourth banks. The refresh controllers  1322  may generate a refresh signal REF_CON based on a refresh command REF and the bank selection signal BKsel2. In detail, the refresh controllers  1322  may generate the refresh signal REF_CON to perform a refresh operation on at least one bank selected according to the bank selection signal BKsel2, in response to the refresh command REF. 
     The wordline enable controllers  133  may respectively correspond to a plurality of banks. For example, when the plurality of banks include first through fourth banks (e.g., BANK_A through BANK_D of  FIG.  2   ), the wordline enable controllers  133  may include four wordline enable controllers respectively corresponding to the first through fourth banks. The wordline enable controllers  133  may generate wordline enable signals WL_EN based on an active control signal ACT_CON and the refresh signal REF_CON. 
       FIG.  7    is a block diagram illustrating in detail a control logic  130   b  according to some embodiments of the inventive concepts. 
     Referring to  FIG.  7   , as compared to the control logic  130   a  of  FIG.  5   , the control logic  130   b  may further include a PE enable signal generator  134 , a row address (RA)/bank address (BA) generator  135 , and a command decoder  136 . The PE enable signal generator  134  may generate a PE enable signal PE_EN based on a command CMD and an address ADDR. In some embodiments, the PE enable signal generator  134  may receive a row address RA from the RA/BA generator  135  and may also generate the PE enable signal PE_EN based on the command CMD and the row address RA. 
     The RA/BA generator  135  may receive the address ADDR from the memory controller  200  and may generate the row address RA and a bank address BA from the received address ADDR. The generated bank address BA may be provided to a bank selector  1311  included in an active control unit  131  and a bank selector  1321  included in a refresh control unit  132 . The generated row address RA may be provided to a row decoder (e.g., the row decoder XDEC of  FIG.  3   ) connected to each bank. 
     The command decoder  136  may receive the command CMD from the memory controller  200  and may generate an active command ACT and a refresh command REF by decoding the received command CMD. The generated active command ACT may be provided to bank active controllers  1312  included in the active control unit  131 , and the generated refresh command REF may be provided to refresh controllers  1322  included in the refresh control unit  132 . 
       FIG.  8    is a block diagram illustrating a memory system  10 A according to some embodiments of the inventive concepts. 
     Referring to  FIG.  8   , the memory system  10 A may include a memory device  100 A and a memory controller  200 , and the memory device  100 A may include a memory cell array  110 A, a PE  120 , and a control logic  130 A. The memory cell array  110 A may include a plurality of bank groups BGs. The memory system  10 A may correspond generally to the memory system  10  of  FIG.  1   , except that in some embodiments, the memory cell array  110 A may include the plurality of bank groups BGs unlike the memory cell array  110  of  FIG.  1   , and each of the plurality of bank groups BGs may include a plurality of banks. 
       FIG.  9    is a block diagram illustrating the memory device  100 A, according to some embodiments of the inventive concepts. 
     Referring to  FIG.  9   , the memory cell array  110 A may include first through fourth bank groups BG0 through BG3, and each of the first through fourth bank groups BG0 through BG3 may include first through fourth banks BANK_A through BANK_D. The first through fourth banks BANK_A through BANK_D of each bank group may be respectively connected to first through fourth PEs PEa through PEd, and thus, the first through fourth PEs PEa through PEd are illustrated as being included in the memory cell array  110 A. However, the inventive concepts are not limited thereto, and the number of bank groups included in the memory cell array  110 A and the number of banks included in each bank group may be variously selected in different embodiments. 
     In some embodiments, the memory device  100 A may include a clock pin P1 receiving a clock signal CLK and a plurality of command/address (CA) pins P2 receiving a command CMD and an address ADDR. Here, a PE enable signal generator  134  may generate a PE enable signal PE_EN from the clock signal CLK received through the clock pin P1, and the command CMD and the address ADDR received through the plurality of CA pins P2. In some embodiments, the memory device  100 A may further include a PE pin P3 receiving a PE enable command PE_EN CMD. Here, the PE enable signal generator  134  may generate the PE enable signal PE_EN from the PE enable command PE_EN CMD received through the PE pin P3. 
     A control logic  130 A may include an active control unit  131   a , a refresh control unit  132   a , wordline enable controllers  133   a  through  133   n , the PE enable signal generator  134 , an RA/BA generator  135 , and a command decoder  136 . The command decoder  136  may generate an active command ACT and a refresh command REF from the clock signal CLK received through the clock pin P1, and the command CMD and the address ADDR received through the plurality of CA pins P2. The RA/BA generator  135  may generate a row address RA and a bank address BA from the clock signal CLK received through the clock pin P1, and the command CMD and the address ADDR received through the plurality of CA pins P2. 
     The active control unit  131   a  may include a bank selector  1311  and bank active controllers  1312   a  through  1312   n , and the number of bank active controllers  1312   a  through  1312   n  may be equal to or correspond to the number of banks included in the memory cell array  110 A. For example, the number of banks included in the memory cell array  110 A may be 16, and the number of bank active controllers  1312   a  through  1312   n  may be 16. The bank active controllers  1312   a  through  1312   n  may respectively correspond to banks included in the memory cell array  110 A. 
     For example, when a bank selection signal BKsel1 and the active command ACT are activated and a first refresh signal REF_A is inactivated, the bank active controller  1312   a  may generate a first bank active signal ACTa that is activated. When all of the bank selection signal BKsel1, the active command ACT, and the first refresh signal REF_A are activated, the bank active controller  1312   a  may generate the first bank active signal ACTa that is inactivated. For example, the bank active controller  1312   a  may generate an inverted first refresh signal by performing an inverting operation on the first refresh signal REF_A and may generate the first bank active signal ACTa by performing an AND operation on the bank selection signal BKsel1, the active command ACT, and the inverted first refresh signal. The first bank active signal ACTa may be provided for the wordline enable controller  133   a.    
     The refresh control unit  132   a  may include a bank selector  1321  and refresh controllers  1322   a  through  1322   d , and the number of refresh controllers  1322   a  through  1322   d  may correspond to the number of banks BANK_A through BANK_D included in each bank group of the memory cell array  110 A. For example, the number of banks included in each bank group may be 4, and the number of refresh controllers  1322   a  through  1322   d  may be 4. 
     For example, when a bank selection signal BKsel2 and the refresh command REF are activated, the refresh controller  1322   a  may generate the first refresh signal REF_A that is activated. When at least one selected from the bank selection signal BKsel2 and the refresh command REF is inactivated, the refresh controller  1322   a  may generate the first refresh signal REF_A that is inactivated. For example, the refresh controller  1322   a  may generate the first refresh signal REF_A by performing an AND operation on the bank selection signal BKsel2 and the refresh command REF. The first refresh signal REF_A may be provided for the bank active controller  1312   a  and the wordline enable controller  133   a.    
     The number of wordline enable controllers  133   a  through  133   n  may correspond to the number of banks included in the memory cell array  110 A. For example, the number of banks included in the memory cell array  110 A may be 16, and the number of wordline enable controllers  133   a  through  133   n  may be 16. 
     For example, when at least one selected from the first bank active signal ACTa and the first refresh signal REF_A is activated, the wordline enable controller  133   a  may generate a first wordline enable signal WL_EN1 that is activated. When both the first bank active signal ACTa and the first refresh signal REF_A are inactivated, the wordline enable controller  133   a  may generate the first wordline enable signal WL_EN1 that is inactivated. For example, the wordline enable controller  133   a  may generate the first wordline enable signal WL_EN1 by performing an OR operation on the first bank active signal ACTa and the first refresh signal REF_A. 
       FIG.  10    illustrates a bank selection table TA2 according to some embodiments of the inventive concepts. 
     Referring to  FIG.  10   , the RA/BA generator  135  may generate a bank address BA that is a 4-bit signal including BA0 through BA3, by decoding the address ADDR. In a PE disable mode, the bank selector  1311  may select a first bank BANK_A of a first bank group BG0 when the bank address BA is “0000,” select a second bank BANK_B of the first bank group BG0 when the bank address BA is “0001,” select a third bank BANK_C of the first bank group BG0 when the bank address BA is “0010,” and select a fourth bank BANK_D of the first bank group BG0 when the bank address BA is “0011.” The banks of other bank groups may be selected when the bank address BA is as shown in  FIG.  10   . As described above, in the PE disable mode, the bank selector  1311  may sequentially select one bank according to the bank address BA. In a PE enable mode, the bank selector  1311  may select all of the first through fourth banks BANK_A through BANK_D of first through fourth bank groups BG0 through BG3. 
       FIG.  11    illustrates a bank selection table TA3 according to some embodiments of the inventive concepts. 
     Referring to  FIG.  11   , the RA/BA generator  135  may generate a bank address BA that is a 4-bit signal including BA0 through BA3 by decoding the address ADDR. In a PE disable mode, the bank selector  1311  may sequentially select one bank according to the bank address BA in the same manner as illustrated in  FIG.  10   . 
     In a PE enable mode, the bank selector  1311  may mask upper three bits, i.e., BA3, BA2, and BA1, and select two banks of each bank group according to the least significant bit, i.e., BA0. For example, in the PE enable mode, the bank selector  1311  may select first and third banks BANK_A and BANK_C when the bank address BA is “0000” and select second and fourth banks BANK_B and BANK_D when the bank address BA is “0001.” However, the inventive concepts are not limited thereto, and a plurality of banks may be selectively activated by masking one or more bits of the bank address BA according to the number of bank groups and/or banks included in a memory cell array. 
       FIG.  12    is a block diagram illustrating a memory system  10 B according to some embodiments of the inventive concepts. 
     Referring to  FIG.  12   , the memory system  10 B may include a memory device  100 B and a memory controller  200 , and the memory device  100 B may include a memory cell array  110 B, a PE  120 , and a control logic  130 B. The memory cell array  110 B may include a plurality of banks BKs, and each of the plurality of banks BKs may include a plurality of blocks BLK. The memory system  10 B may correspond generally to the memory system  10  of  FIG.  1   , except with each of the plurality of banks BK including a plurality of blocks BLK. Hereinafter, dispositions of each bank BK and a PE will be described with reference to  FIG.  13   . 
       FIG.  13    is a block diagram illustrating a bank BK and a PE according to some embodiments of the inventive concepts. 
     Referring to  FIG.  13   , the bank BK may be connected to a row decoder XDEC and a column decoder YDEC. The bank BK may correspond to one of the plurality of banks BKs of  FIG.  12   . In detail, the bank BK may include a plurality of blocks BLK0 through BLKm (wherein m is a natural number). The plurality of blocks BLK0 through BLKm may be respectively connected to a plurality of bitline sense amplifiers BLSA. An input/output sense amplifier IOSA may sense and amplify data read from the bank BK. According to some embodiments, positions of the column decoder YDEC and the input/output sense amplifier IOSA may be changed. The PE may be connected to the input/output sense amplifier IOSA and may perform an operation on data received from the input/output sense amplifier IOSA. 
       FIG.  14    is a block diagram illustrating a memory device  100 B according to some embodiments of the inventive concepts. 
     Referring to  FIG.  14   , the memory device  100 B may include first through fourth banks BANK_A through BANK_D, first through fourth PEs PEa through PEd, and a control logic  130   c . The memory device  100 B may correspond to the memory device  100 B of  FIG.  12   . In some embodiments, the first through fourth PEs PEa through PEd may be respectively connected to the first through fourth banks BANK_A through BANK_D and may respectively perform operations on pieces of data respectively stored in the first through fourth banks BANK_A through BANK_D. 
     The control logic  130   c  may include an active control unit  131   c  and a refresh control unit  132   c . The active control unit  131   c  may determine a block in an active state in each bank based on a row address RA and may provide the refresh control unit  132   c  with active block information ACT_BLK so that a refresh operation is not performed on the block in the active state. The refresh control unit  132   c  may generate a refresh signal REF_CON based on the active block information ACT_BLK so that the refresh operation is not performed on the block in the active state. 
     Also, the active control unit  131   c  may determine a block on which the refresh operation is being performed based on the row address RA and the refresh signal REF_CON in response to an active command ACT in a PE enable mode, and generate wordline enable signals WL_EN not to activate a wordline included in the block on which the refresh operation is being performed, and to activate a wordline included in a block on which the refresh operation is not performed. 
       FIG.  15    is a flowchart illustrating operations between a memory device  100  and a memory controller  200 , according to some embodiments of the inventive concepts. 
     Referring to  FIG.  15   , an operating method according to some embodiments relates to a method of controlling an active operation and a refresh operation in the memory device  100  that includes a PE, for example, and may include operations that are performed in a time series in the memory device  100  and the memory controller  200  of  FIG.  1   . The above descriptions with reference to  FIGS.  1  through  14    may also be applied to the operations shown in  FIG.  15   . The operating method will now be described with reference to  FIGS.  1  and  15   . 
     In operation S 100 , the memory controller  200  determines a PE enable mode. For example, the PE enable mode controller  210  may determine the PE enable mode to enable an operation of the PE  120 . In operation S 110 , the memory controller  200  transmits a PE enable command to the memory device  100 . For example, the PE enable command may be generated by a combination of the command CMD, the address ADDR, and the clock signal CLK. In operation S 120 , the memory device  100  generates a PE enable signal in response to the PE enable command. 
     In operation S 130 , the memory controller  200  controls an active operation of the memory device  100 . In operation S 140 , the memory controller  200  transmits an active command to the memory device  100 . In operation S 150 , the memory device  100  activates wordlines included in each of a plurality of banks BKs in response to the active command. As described above, in the PE enable mode in which the PE enable signal is activated, since the memory device  100  activates as many wordlines as possible, as many PEs  120  as possible may simultaneously perform computational operations, thereby improving performances of the memory device  100  and the memory system  10 . 
     In operation S 160 , the memory controller  200  controls a refresh operation of the memory device  100 . In operation S 170 , the memory controller  200  transmits a refresh command to the memory device  100 . In operation S 180 , the memory device  100  performs the refresh operation on a first bank. In detail, the control logic  130  may enable a wordline included in the first bank and may perform the refresh operation on memory cells connected to the enabled wordline. 
       FIG.  16    is a flowchart illustrating operations between a memory device  100  and a memory controller  200 , according to some embodiments of the inventive concepts. 
     Referring to  FIG.  16   , an operating method according to some embodiments relates to a method of controlling an active operation and a refresh operation in the memory device  100  including a PE, for example, and may include operations that are performed in a time series in the memory device  100  and the memory controller  200  of  FIG.  1   . The operations S 100 , S 110 , S 120 , S 160 , S 170 , and S 180  described above with reference to  FIG.  15    may be respectively applied to operations S 100 , S 110 , S 120 , S 160 , S 170 , and S 180  of  FIG.  16   , and duplicate descriptions thereof are omitted herein. 
     In operation S 210 , the memory controller  200  controls an active operation of the memory device  100 . In operation S 220 , the memory controller  200  transmits an active command to the memory device  100 . In operation S 230 , the memory device  100  activates wordlines included in banks other than a first bank among a plurality of banks BKs in response to the active command. As described above, in the PE enable mode in which the PE enable signal is activated, since the memory device  100  activates as many wordlines as possible included in banks except for a bank on which the refresh operation is being performed, as many PEs  120  as possible may simultaneously perform computational operations, thereby improving performances of the memory device  100  and the memory system  10 . 
       FIG.  17    is a block diagram illustrating a mobile system  1000  to which a memory device is applied, according to an embodiment of the inventive concept. 
     Referring to  FIG.  17   , the mobile system  1000  may include a camera  1100 , a display  1200 , an audio processor  1300 , a modem  1400 , dynamic random access memories (DRAMs)  1500   a  and  1500   b , flash memory devices  1600   a  and  1600   b , input/output (I/O) devices  1700   a  and  1700   b , and an application processor (AP)  1800 . The mobile system  1000  may be implemented as a laptop computer, a mobile phone, a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. Also, the mobile system  1000  may be embodied as a server or a personal computer (PC). 
     The camera  1100  may capture a still image or a moving image under control of a user. The camera  1100  may be embodied as a plurality of cameras including a front camera, a rear camera, and the like. The display  1200  may be embodied in various forms such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an Active-Matrix Organic Light Emitting Diode (AM-OLED) display, a Plasma Display Panel (PDP), and the like. The audio processor  1300  may process audio data included in contents stored in the flash memory devices  1600   a  and  1600   b . For example, the audio processor  1300  may perform various types of processing, such as decoding, amplifying, noise filtering, and the like, on audio data. 
     The modem  1400  is a device that modulates and transmits a signal to transmit and/or receive wired and/or wireless data and demodulates the signal to recover an original signal at a receiving side. The I/O devices  1700   a  and  1700   b  may include devices that provide digital input and output functions, such as a Universal Serial Bus (USB) or storage, a digital camera, a Secure Digital (SD) card, a touch screen, a Digital Video Disk (DVD), a Network adapter, and the like. 
     The AP  1800  controls an overall operation of the mobile system  1000 . In detail, the AP  1800  may control the display  1200  so that parts of contents stored in the flash memory devices  1600   a  and  1600   b  are displayed on the display  1200 . Also, when a user input is received through the I/O devices  1700   a  and  1700   b , the AP  1800  may perform a control operation corresponding to the user input. 
     The AP  1800  may be provided as a System-on-Chip (SoC) that drives an application program, an Operating System (OS), and the like. Alternatively, the AP  1800  and other semiconductor components, for example, the DRAM  1500   a , a flash memory  1620 , and/or a memory controller  1610 , may be mounted using various types of packages. In other words, the AP  1800  and other semiconductor components may be mounted using packages such as Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), CERamic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-level Processed Stack Package (WSP), and the like. 
     A kernel of an operating system driven on the AP  1800  may include an input/output (I/O) scheduler and a device driver for controlling the flash memory devices  1600   a  and  1600   b . The device driver may control access performances of the flash memory devices  1600   a  and  1600   b  or may control a CPU mode, a Dynamic voltage and Frequency Scaling (DVFS) level, and the like in an SoC with reference to the number of synchronous queues managed by the I/O scheduler. 
     In some embodiments, the AP  1800  may include an accelerator block or an accelerator chip  1820  that is a circuit only for an AI data operation. Therefore, the DRAM  1500   b  may be further mounted on the accelerator block or the accelerator chip  1820 . The accelerator block or the accelerator chip  1820  is used to increase a performance index of the mobile system  1000  by accelerating a multitasking operation simultaneously loading a plurality of applications frequently occurring in the mobile system  1000 , and switch and execution between the applications. 
     According to some embodiments, the mobile system  1000  may include a plurality of DRAMs  1500   a  and  1500   b . In an embodiment, the AP  1800  may include a controller  1810 , and thus, the DRAM  1500   a  may be directly connected to the AP  1800 . The AP  1800  may control the DRAMs  1500   a  and  1500   b  through commands and MRS setting conforming to JEDEC standards or may communicate with the DRAMs  1500   a  and  1500   b  by setting DRAM interface protocols to use company-particular characteristics such as a low voltage, a high speed, reliability, and the like and Error Correction Code (ECC). 
     The DRAMs  1500   a  and  1500   b  have relatively smaller latency and bandwidth than the I/O devices  1700   a  and  1700   b  or the flash memory devices  1600   a  and  1600   b . The DRAMs  1500   a  and  1500   b  may be initialized when the mobile system  1000  is powered on and may be loaded with operating system and application data to be used as temporary storage locations for the operating system and application data or may be used as execution spaces for various types of software code. 
     Four fundamental arithmetic operations of addition, subtraction, multiplication, and division and a vector operation, an address operation, or an FFT operation may be performed in the DRAMs  1500   a  and  1500   b . Also, a function for performing an inference may be performed in the DRAMs  1500   a  and  1500   b . Here, the inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training stage of learning a model through various types of data and an inference stage of recognizing data with the learned model. For example, the function used for the inference may include a hyperbolic tangent function, a sigmoid function, a Rectified Linear Unit (ReLU) function, or the like. For example, the function used for the inference may be performed in the DRAM  1500   b , and the accelerator block or the accelerator chip  1820  may perform an AI data operation based on data stored in the DRAM  1500   b.    
     According to some embodiments, the mobile system  1000  may include a plurality of storages or a plurality of flash memory devices  1600   a  and  1600   b  having larger capacities than the DRAMs  1500   a  and  1500   b . According to some embodiments, the accelerator block or the accelerator chip  1820  may perform the training stage and the AI data operation by using the flash memory devices  1600   a  and  1600   b . According to embodiments, the AP  1800  may include an interface  1830 , and thus the flash memory devices  1600   a  and  1600   b  may be directly connected to the AP  1800 . For example, the AP  1800  may be embodied as an SoC, the flash memory device  1600   a  may be embodied as a separate chip, and the AP  1800  and the flash memory device  1600   a  may be assembled into one package. However, the inventive concept is not limited thereto, and the plurality of flash memory devices  1600   a  and  1600   b  may be electrically connected to the mobile system  1000  through a connection. 
     The flash memory devices  1600   a  and  1600   b  may store pictures captured through the camera  1100  or may store data transmitted through a data network, for example, Augmented Reality (AR)/Virtual Reality (VR), High Definition (HD), or Ultra High Definition (UHD) contents. 
     The DRAM  1500   a  may correspond to the memory device  100 ,  100 A, or  100 B described above with reference to  FIGS.  1  through  16    and may include the PE  120 . Also, the controller  1810  may correspond to the memory controller  200  described above with reference to  FIGS.  1  through  16   . For example, the user may capture an object through the camera  1100 , and thus, the mobile system  1000  may perform image signal processing on an object image input through the camera  1100 . An operation of the mobile system  1000  associated with image signal processing will now be described. 
     The controller  1810  in the AP  1800  may determine a PE enable mode and may provide the DRAM  1500   a  with a PE enable command indicating the determined PE enable mode. The DRAM  1500   a  may activate a PE enable signal in response to the PE enable command and thus may enter the PE enable mode, i.e., a PIM mode. Next, the controller  1810  may provide the DRAM  1500   a  with an active command, and the DRAM  1500   a  may activate wordlines included in each of the largest number of banks in response to the active command. 
     For example, PEs included in the DRAM  1500   a  may perform a data operation associated with an object image input through the camera  1100  and may provide the controller  1810  with a result of the data operation. The AP  1800  may generate an object recognition result associated with the object image based on the result of the data operation received from the controller  1810  and may provide the I/O device  1700   a  with the generated object recognition result. As another example, the PEs included in the DRAM  1500   a  may generate an object recognition result by performing a data operation associated with an object image input through the camera  1100  and may provide the controller  1810  with the generated object recognition result. The AP  1800  may provide the I/O device  1700   a  with the object recognition result received from the controller  1810 . 
     While the inventive concepts have been particularly shown and described with reference to examples of embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.