Patent Publication Number: US-2012032703-A1

Title: Pulse-shrinking delay line based on feed forward

Description:
FIELD OF THE INVENTION 
     The invention relates to an electronic circuit comprising a digital delay line with a cascade of a plurality of stages configured for modifying a width of a pulse propagating down the cascade. 
     BACKGROUND ART 
     Delay lines are well-known components and are used in, e.g., delay-locked loops (DLLs) and in time-to-digital converters (TDCs). DLLs are typically used for generating time-shifted clocks. The TDC is a key block for measuring timing differences between two clock signals. The TDC, in particular, is a key block of a digital PLL, such as the one needed in multi-gigahertz radio applications. 
     Digital delay lines are often made as a cascade of CMOS inverter stages. The binary signal propagates from the cascade&#39;s input to the cascade&#39;s output, and each stage delays the occurrence of the signal&#39;s edges by a specific amount of time. In a TDC, the digital delay line used is typically of the type that changes the signal&#39;s pulse-width while the pulse is propagating along the cascade. This delay line has a cascade of stages, each of which implements a longer delay for the propagation of one of the pulses edges, e.g., the rising edge, than for the other edge of the pulse, e.g., the falling edge. This configuration shrinks or widens the width of the signal&#39;s pulse to a further extent at each stage. A stage is implemented as, e.g., a pair of CMOS inverters arranged in series. For an example of a known pulse-shrinking delay line see, e.g., Tisa S, Lotito A, Giudice A &amp; Zappa F (2003) “Monolithic time-to-digital converter with 20 ps resolution”; Proc. European Solid-State Circuits Conference, ESSCIRC&#39;03, Estoril, Portugal, pp. 465-468. 
     There is a variety of approaches to obtaining a shrinking or widening of the pulse width. One approach is to select the ratios of the sizes of the transistors for the different stages so as to determine how fast a falling edge and how fast a rising edge propagates. For example, if the width of the p-type field effect transistor (FET) of the i-th inverter in the cascade is denoted by W pi  and the width of the n-type FET in the i-th inverter as W ni , then shrinking occurs between the input of inverter (i)  and the output of inverter (i+1)  if the ratio W p(i+1) /W n(i+1)  is smaller than the ratio W p(i) . Another approach is to bias the gates of one or more transistor per stage. For more information see, e.g., U.S. Pat. No. 6,288,587. 
     SUMMARY OF THE INVENTION 
     The inventors propose an a pulse shrinking delay line, i.e., a delay line that modifies the signal&#39;s pulse width, with a configuration that enables to obtain a higher time resolution than the conventional pulse shrinking delay lines. That is, the delay line of the invention can be configured to operate with shorter delays. 
     To this end, the inventors propose an electronic circuit comprising a digital delay line with a cascade of a plurality of stages. Each specific one of the stages has an input and an output and a main path between the input and the output. The main path has a first inverter and a second inverter connected in series via an intermediate node. Each specific stage has a third inverter between the input and the intermediate node of a downstream one of the stages in the cascade. Each specific stage has a fourth inverter between the intermediate node and the output of the downstream stage. 
     In effect the cascaded main paths in the circuit of the invention represent a pulse-width changing configuration known in the art, e.g., using proper ratios of the transistor widths as mentioned above. The third and fourth inverters implement a feed-forward mechanism that serves to pre-charge the inputs of the relevant inverters downstream of the specific stage, thus accelerating the propagation of the pulse down the cascade. Note that the feed-forward path connects nodes in the delay line that functionally lie an odd number of inverting operations apart. 
     In a further embodiment of a circuit according to the invention the first inverter is formed by a first transistor having its main channel connected between a first supply voltage and the intermediate node, and having a control electrode connected to the input. The second inverter is formed by a second transistor having its main channel connected between the output and a second supply voltage, and having its control electrode connected to the intermediate node. The third inverter is formed by a third transistor having its main channel connected between the second supply voltage and the intermediate node of the downstream stage, and having its control electrode connected to the input. The fourth inverter is formed by a fourth transistor having its main channel connected between the first supply voltage and the output of the downstream stage, and having its control electrode connected to the intermediate node. In this embodiment, the pulse&#39;s edge of a first polarity is given a reduced propagation time as a result of only keeping the feed-forward transistors assisting in faster propagating this edge. The edge of the other polarity is propagated only via the main path and is not subjected to a feed-forward operation. 
     The inventors have found that, even when the transistors of the inverters in above embodiment have equal size or width throughout the cascade, pulse-width modification occurs during propagation along the cascade. This embodiment has the advantage that the design and lay-out is simplified, and that moreover, for a pulse-shrinking configuration, this embodiment offers the best ratio of the shrinking delay to propagation delay. It is preferred that the propagation delay is low as this reduces the conversion time in, e.g., a TDC embodiment of the invention, so that the digital information is available at the output earlier; the noise level is lower since the time uncertainty associated with the delay action is more or less proportional to the propagation delay. Accordingly, for a given shrinking delay, it is preferred to have the lowest propagation delay. Furthermore, this embodiment has advantages in that the lay-out is smaller than when using full-fledged inverters, and in that the loads per inverter are minimized, thus leading to a further reduction of the propagation delays. As a result, a better resolution is obtained for still shorter time periods. 
     Above embodiments relate to a single-ended pulse-shrinking delay lines. The same principle can be applied to differential pulse-shrinking delay lines. The feed-forward paths should then similarly be connected between nodes that functionally lie an odd number of inverting operations apart. 
     More specifically, the invention relates also to an electronic circuit comprising a digital delay line with a cascade of a plurality of stages configured for modifying a width of a pulse propagating down the cascade. Each specific one of the stages has a first input, a second input, a first output and a second output, a first inverter between the first input and the first output; and a second inverter between the second input and the second output. Each specific one of the stages has the first output connected to the second input of an adjacent one of the stages downstream in the cascade, and has the second output connected to the first input of the adjacent one of the stages. Each specific stage has a fifth inverter connected between the first input and the first input of a downstream one of the stages in the cascade, and a sixth inverter connected between the second input and the second input if the downstream one of the stages. The downstream stage is such that the downstream stage and the specific stage are connected via an odd number of other ones of the stages. A reason for this is explained as follows. The feed-forward path implements a single inversion between the nodes of the main path that are bridged by a feed-forward path&#39;s inverter. The main path of the cascade is formed by pairs of inverters that are cross-connected between succeeding stages. A snap shot of the logical states of the relevant nodes in the main path, taken at an arbitrary moment, reveals that the nodes bridged by the feed-forward path have assumed complementary logical states (e.g., one is high and the other is low) between the pulse&#39;s transitions. The feed-forward path, driven by a transition at a particular node upstream accelerates the complementary transition in the downstream node. 
     For completeness, a feed-forward mechanism in a delay line is mentioned in the description of  FIGS. 10 and 11  of US 2007/0047689. However, the delay line is not of the type that modifies the signal&#39;s pulse-width as the pulse is propagating down the delay line, and the specific connections are not detailed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       The invention is explained in further detail, by way of example and with reference to the accompanying drawing, wherein: 
         FIG. 1  is a block diagram of an embodiment of a pulse-shrinking delay line in the invention; 
         FIG. 2  is a diagram illustrating the shrinking of a positive pulse propagating down the delay line of  FIG. 1 ; 
         FIG. 3  is a diagram of another embodiment of a pulse-shrinking delay line in the invention; 
         FIGS. 4 and 5  are transistor diagrams of implementations of the delay line in  FIG. 1 ; and 
         FIGS. 6 and 7  are diagrams of a differential type of pulse shrinking delay lines in the invention. 
     
    
    
     Throughout the Figures, similar or corresponding features are indicated by same reference numerals. 
     DETAILED EMBODIMENTS 
       FIG. 1  is a diagram showing an electronic circuit  100  with a digital pulse-shrinking delay line with a cascade of a plurality of stages. For clarity, only stages  102  and  104  have been indicated. Stage  102  has a first input  106  and a first output  108  and a main path between first input  106  and first output  108 . The main path has a first inverter  110  and a second inverter  112  connected in series via an intermediate node  114 . Stage  104  has a first input  116  and a first output  118  and a main path between first input  116  and first output  118 . The main path has a first inverter  120  and a second inverter  122  connected in series via an intermediate node  124 . Each of stages  102  and propagates the rising edge and the falling edge of a pulse at the relevant first input to the relevant output. 
     Stage  102  has a second output  126  and a third inverter  128  between first input  106  and second output  126 ; a third output  130  and a fourth inverter  132  between intermediate node  114  and third output  130 ; a second input  134  connected to intermediate node  114 ; and a third input  136  connected to first output  108 . Likewise, stage  104  has a second output  138  and a third inverter  140  between first input  116  and second output  138 ; a third output  142  and a fourth inverter  144  between intermediate node  124  and third output  142 ; a second input  146  connected to intermediate node  124 ; and a third input  148  connected to first output  118 . 
     Stage  104  has first input  116  connected to first output  108  of preceding stage  102 , second input  146  connected to second output  126  of preceding stage  102  and third input  148  connected to third output  130  of preceding stage  102 . 
     The cascaded main paths formed by inverters  110 ,  112 ,  120  and  122  represent a pulse-width changing configuration known in the art, if the inverters propagate the rising edge of a pulse and the falling edge of the pulse with different delays. This is brought about in conventional shrinking delay lines by, e.g., different biasing of the inverters or different dimension ratios of adjacent inverters per stage, as mentioned above. Additional inverters  128  and  132 , used in the invention, implement a feed-forward mechanism. Inverter  128  serves to pre-charge intermediate node  124  that is the input to inverter  122 , and inverter  132  serves to pre-charge the first input of the stage (not shown) that succeeds stage  104 . The pre-charging causes the transitions of the signal pulse, i.e., the rising edges and falling edges, to be speeded up, and as a result brings about the shrinking of the width of the pulse while it propagates down the cascade. 
       FIG. 2  is a diagram  200  illustrating the operation of circuit  100 . It is assumed that stages  102  and  104  form part of a longer delay line of which the other stages have not been shown. A pulse  202  at input  106  is modified by stage  102  into a pulse  204  at output  108 . Pulse  204  appears at input  116  and is modified by stage  104  into a pulse  206  at output  118 . As the edges of pulse  202  are fed-forward to stage  104 , stage  104  causes the edges of pulse  204  to be subjected to a shorter time-shift than without the use of the feed-forward path. As a consequence the width of pulse  206  becomes smaller than the width of pulse  204 . Note that in the invention, inverters  110 ,  112 ,  120  and  122  can be uniform in the sense of using the same bias or same dimension ratio throughout, in contrast with the conventional pulse shrinking delay line. In the invention, the shrinking operation is carried out by inverters  128 ,  132 ,  140  and  144  that implement the feed-forward path. 
       FIG. 3  is a diagram of a circuit  300  illustrating a variation on the theme of the invention. In circuit  100 , additional inverters  128 ,  132 ,  140  and  144  are located in the feed-forward paths to the stage immediately succeeding the stage accommodating the additional inverters. In circuit  300 , the feed-forward paths connect a specific stage to a downstream one of the stages further downstream than the stage immediately succeeding the specific stage. 
     More specifically, circuit  300  comprises a pulse-shrinking delay line with a plurality of cascaded stages, of which only stages  302 ,  304 ,  306 ,  308  and  310  have been indicated. The main path of the delay line is formed by a cascade of modules  312 ,  314 ,  316 ,  318  and  320 , each comprising a series arrangement of inverting gates, not shown in order to not obscure the drawing. Circuit  300  comprises additional inverters  332 ,  324 ,  326 ,  328 ,  330 ,  332 ,  334 ,  336  and  338  to form feed-forward paths between stages  302 - 310 . Note that the feed-forward path connecting one stage to a next one, located downstream the cascade, skips a stage in between. For example, additional inverters  322  and  324  of stage  302  connect to stage  306 , skipping stage  304 . Instead of skipping a single stage, one could design pulse-shrinking delay lines wherein the feed-forward paths skip more than one stage. 
       FIG. 4  is a transistor implementation  400  of stages  102  and  104  in circuit  100  discussed above, created with field effect transistors (FETs) in, e.g., CMOS. Conventionally, a CMOS inverter is formed by connecting the main current channels of a PFET and an NFET in series between a first supply voltage (here: V DD ) and a second supply voltage (here signal-ground). The control electrodes of the PFET and NFET are connected and form the inverter&#39;s input. The inverter&#39;s output is formed by a node between the main channels. Implementation  400  causes the shrinking of a negative pulse: the rising edge of the input pulse propagates faster than the falling edge of the input pulse. In implementation  400 , each of inverters  110 ,  112 ,  128  and  132  of circuit  100  is reduced to a single transistor, either a PFET or an NFET, and only those transistors have been kept that help to reduce the propagation delay of the signal&#39;s rising edge. The transistors in  FIG. 3  have been given the same reference numerals as the corresponding inverters of circuit  100 . Transistors  110  and  132  are PFETs, and transistors  128  and  112  are NFETs in this example. Because the load on each node is minimized, the propagation delay is further reduced as compared to an implementation with full-fledged two-FET inverters. 
       FIG. 5  is another transistor implementation  500  of stages  102  and  104  in circuit  100  discussed above, created with FETs. In a sense, implementation  500  is a mirror image of implementation  400 . Implementation  500  is operative to cause the shrinking of a positive pulse: the falling edge of the input pulse propagates faster than the rising edge of the input pulse. 
     The inventors have carried out simulations for a shrinking-pulse delay line of cascaded stages with each a series connection of two conventional CMOS inverters, and for a shrinking-pulse delay line of cascaded stages each of which configured as implementation  300  made in a 65 nm CMOS process for a supply voltage of 1.2 Volts at a temperature of 47° Celsius. The targeted shrinking delay Δt was set to 10 ps (10 −11  seconds). The delay TP H  per stage for a rising edge was found to be 33 ps for the conventional stage and 19 ps for the stage in the invention. The delay TP L  per stage for a falling edge was found to be 43 ps for the conventional stage and 29 ps for a stage in the invention. 
     Accordingly, in comparison to the conventional approach, the invention provides a shorter delay per stage, lower power consumption, and lower susceptibility of the operation to the transistor sizes used. 
     In above embodiments, the cascade of stages uses inverters. It is clear that other logic gates can be used that implement an inverting operation, e.g., a NOR gate or a NAND gate. These latter gates can be biased at one of their inputs so as to functionally implement an inverter, or the additional input terminals can be used to control the pulse propagating down the cascade by applying control signals thereto. 
       FIG. 6  gives a further embodiment of the invention in the form of a pseudo-differential delay line  600  with a plurality of stages in a cascade, of which only stages  602 ,  604  and  606  are shown. The main path through stages  602 ,  604  and  606  is formed by first inverter  606  and second inverter  608  in stage  602 , first inverter  610  and second inverter  612  in stage  604 , and first inverter  614  and second inverter  616  in stage  606 . The main path of delay line  600  is similar to a pseudo differential delay line known in the art. That is, the sizes of the transistors in the relevant inverters are properly tuned to subject the pulse to a shrinking operation while propagating down the cascade. 
     Delay line  600  includes feed-forward paths according to the invention in order to pre-charge nodes further downstream in the cascade. The configuration is as follows. Each specific one of stages  602 ,  604  and  606  has a first input  601 ,  605  and  609 , respectively; a second input  603 ,  607  and  611 , respectively; a first output  613 ,  617  and  621 , respectively; and a second output  615 ,  619  and  623 , respectively. First inverters  606 ,  610  and  614  are connected between the first input and the first output of their respective stages. Second inverter  608 ,  612  and  616  are connected between the second input and the second output of their respective stages. Each of the stages, e.g., stage  604 , has the first output, here output  617 , connected to the second input of an adjacent one of the stages downstream in the cascade, here input  611  of stage  606 . Each of the stages, e.g., stage  604 , has its second output, here output  619 , connected to the first input of the adjacent stage, here input  609  of stage  606 . Each particular one of stages  602 ,  604  and  606  has a third inverter  618 ,  622  and  626 , respectively, connected between the first input of the particular stage and the first input of a downstream one of the stages in the cascade. Each particular one of stages  602 ,  604  and  606  has a fourth inverter  620 ,  624  and  626 , respectively, connected between the second input of the particular stage and the second input of the downstream one of the stages. Generally, there is an odd number of stages connected between the particular stage and the downstream stage. In the example shown, there is a single stage, e.g., stage  604 , connected between the stages being connected through the feed-forward paths, here stages  602  and  606 . 
     The inverters in delay line  600  can be implemented by full CMOS inverters, each having a P-FET and an N-FET with their main channels connected in series between the supply voltages. 
       FIG. 7  is a diagram of an implementation  700  of delay line  600 , wherein the full inverters have been replaced by single transistors, similarly to the embodiments discussed above with reference to  FIGS. 4 and 5 . The best shrinking capability is obtained with lowest propagation time by omitting half the transistors: in the example shown, only the N-FETs are maintained in the main path, and the P-FETs are maintained in the feed-forward path. In  FIG. 7 , each transistor is indicated by the same reference numeral of the inverter in the diagram of  FIG. 6  whose operation this transistor fulfills. The advantages are similar to the ones discussed with reference to the embodiment of  FIGS. 4 and 5 . Similarly, an operational variation of delay line  700  can be obtained by replacing the N-FETs by P-FETs and vice versa, together with changing the polarities of the supply voltages, in the diagram of  FIG. 7 .