Patent Publication Number: US-6215335-B1

Title: Nonoverlapping phased, resettable, peak detector

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates in general to a peak detector, and more particularly to a resettable peak detector that generates a nonoverlapping phased output signals. 
     2. Description of Related Art 
     Today&#39;s wireless communications markets are being driven by a multitude of user benefits. Products such as cellular phones, cordless phones, pagers, and the like have freed corporate and individual users from their desks and homes and are driving the demand for additional equipment and systems to increase their utility. As a result digital radio personal communications devices will play an increasingly important role in the overall communications infrastructure in the next decade. 
     Mixed-signal integration and power management have taken on added importance now that analog and mixed analog-digital ICs have become the fastest-growing segment of the semiconductor industry. Integration strategies for multimedia consoles, cellular telephones and battery-powered portables are being developed, as well as applications for less integrated but highly specialized building blocks that serve multiple markets. These building blocks include data converters, comparators, demodulators, filters, amplifiers and voltage regulators. 
     One important aspect of digital radio personal communications devices is the integration of the RF sections of transceivers. Compared to other types of integrated circuits, the level of integration in the RF sections of transceivers is still relatively low. Considerations of power dissipation, low offset budgets, form factor, and cost dictate that the RF/IF portions of these devices evolve to higher levels of integration than is true at present. Nevertheless, there are some key barriers to realizing these higher levels of integration. 
     For example, there are many applications where it&#39;s necessary to provide an RF peak detector circuit in an RF receiver system to determine level and offset signal values. These values are used as the inputs in subsequent circuits. For peak detectors, nonoverlapping phased output signals and resettability are required to provide the proper signaling to subsequent circuitry. In some components, such as a demodulator, the bit error rates (BER) start to degrade for signal levels above and below predetermined levels. This is due to offsets within such components. As a result, resettable circuitry and reliable level and offset information is necessary to provide signals within a predetermined range and to eliminate transient voltages. 
     It can be seen then that there is a need for an peak detector to provide level and offset signaling. Specifically, a peak detector that is resettable and provides a nonoverlapping phased output to eliminate transient voltages. 
     SUMMARY OF THE INVENTION 
     To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a peak detector, and more particularly to a resettable peak detector that generates a nonoverlapping phase output signals. 
     The present invention solves the above-described problems by providing a peak detector that is resettable and generates a nonoverlapping phased output signal that provides a level and an offset signal value used in subsequent circuitry. 
     A method in accordance with the principles of the present invention includes comparing an input signal to a first reference signal to produce a maximum sample signal when the input signal is greater than the first reference signal. Comparing the input signal to a second reference signal to produce a minimum sample signal when the input signal is less than the first reference signal. Further, sampling the input signal to activate a maximum sample signal when the input signal is greater than the first reference signal and to activate a minimum sample signal when the input signal is less than the second reference signal, thereto to produce a maximum output signal and a minimum output signal, respectively. 
     Other embodiments of a system in accordance with the principles of the invention may include alternative or optional additional aspects. One such aspect of the present invention includes retaining the input signal in a storage medium. 
     Another aspect of the present invention is that the storage medium further includes a sample and hold amplifier. 
     Another aspect of the present invention is that the input signal includes an in-phase and a quadrature input signal. 
     Another aspect of the present invention is that the input signal is stored as the first reference signal in a maximum sample and hold amplifier, when the input signal is greater than the first reference signal. 
     Another aspect of the present invention is that the input signal is stored as the second reference signal in a minimum sample and hold amplifier, when the input signal is less than the first reference signal. 
     Another aspect of the present invention is that the detector includes a reset signal. 
     Another aspect of the present invention is that the implementation of the reset signal further includes a maximum reference signal and a minimum reference signal. 
     Another aspect of the present invention is that the maximum reference signal and the minimum reference signal further includes a positive signal level for a maximum reference signal and a negative signal level for a minimum reference signal. 
     Another aspect of the present invention is that the implementation of the reset signal reduces transient signals in the maximum and the minimum output signals. 
     Another aspect of the present invention is that the maximum output signal and the minimum output signal provides a level and an offset signal. 
     Another aspect of the present invention is that the minimum and maximum sample signals are generated as a function of a comparator and a clock signal output. 
     Another aspect of the present invention is that the minimum and maximum sample signals provide a maximum nonoverlapping phased output signal and a minimum nonoverlapping phased output signal. 
     Another aspect of the present invention is that the clock signal further includes a voltage doubler that controls a sample and hold amplifier. 
     These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Referring now to the drawings in which like reference numbers represent corresponding parts throughout: 
     FIG. 1 is an exemplary diagram showing a peak detector in a typical radio receiver system; 
     FIG. 2 is a block diagram of a peak detector circuit; 
     FIG. 3 is a block diagram of a peak detection network; 
     FIG. 4 is a flow diagram illustrating a general signal transition through the peak detector; 
     FIG. 5 is a flow diagram illustrating a reset signal transition through the peak detector; and 
     FIG. 6 is an exemplary hardware environment for the peak detector. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following description of the exemplary embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration the specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized as structural changes may be made without departing from the scope of the present invention. 
     The primary design issues of a comparator circuit such as the peak detector is to generate a resettable nonoverlapping phased signal and to provide a level and offset signal value as input to subsequent circuitry. The peak detector is part of the automatic gain control (AGC) circuit in the in-phase/quadrature path of a wireless receiver. The maximum and minimum input signals, V max  and V min  respectively, are a positive and a negative peak value of an in-phase or a quadrature signal, also referred to as a differential signal. The input signals are generated by an RF receiver signal. Thus, the output of the peak detector is used to calculate the in-phase and the quadrature signal level by V p-p =V max −V min . Also, the output of the peak detector is used to calculate the in-phase and the quadrature offset voltage level by V offset =(V max +V min )/2. The peak detector compares an input signal to a first reference voltage to produce a maximum sample signal, and compares the input signal to a second reference voltage to produce a minimum sample signal, wherein the maximum and minimum sample signals produce a sampling of the current input signal thereto to produce a maximum output signal and a minimum output signal respectively. 
     In a time-divisional duplex transceiver system, the transmitter and receiver are never on simultaneously. In operation, data is bursted by the RF transmitter at more than twice the rate of the continuous input data to be transmitted for less than half the time. The far end receiver stores up the bursted data to be read out of a memory at a slower continuous pace. The receiver circuits, however, typically introduce DC offset voltages. The peak detector senses the in-phase and quadrature input signals to determine these offset voltages and signal levels. The peak detector output provides the level and offset information to drive the digital logic circuits that ultimately serve to acquire the desired gain and attenuate offsets in a system. 
     FIG. 1 is an exemplary diagram showing the peak detector in a typical radio receiver system. An RF signal is received by an antenna  100  and is routed into receiver system  110 . The outputs from the receiver system, the in-phase  120  and the quadrature  130  signals, are the input signals to the in-phase  140  and the quadrature  145  peak detectors. The peak detector output signals are comprised of a maximum (V max )  150  and a minimum (V min )  155  in-phase output signal and a maximum (V max )  160  and a minimum (V min )  165  quadrature output signal. The generated outputs are capable of providing level and offset information. 
     FIG. 2 is block diagram of a peak detector circuit. The peak detector circuit monitors a stream of input voltages  220  and generates outputs equal to the maximum signal  280  and minimum signal  290  values. In its normal operation mode, the maximum comparator  260  compares the input signal with the maximum signal stored in maximum sample and hold amplifier (SHA 2 )  240 . The minimum comparator  270  compares the input signal with the minimum value stored in minimum sample and hold amplifier (SHA 3 )  245 . The sample and hold amplifier (SHA 1 )  230  samples and holds the current input value  220 . If the input signal  220  is greater than the maximum signal stored in SHA 2   240 , the sample max signal  250  is active and the output of SHA 1   230  is transferred to SHA 2  to update the maximum sample and hold amplifier  240 . If the input signal  220  is less than the minimum signal stored in SHA 3   245 , the sample min signal  255  is active and the output of SHA 1   230  is transferred to SHA 3   245  to update the minimum sample and hold amplifier  245 . 
     When a reset  210  is activated, multiplexers  236 ,  238  are used to switch from the input signal to a positive (Vdd)  232  and a negative (Vss)  234  supply rail signal. The supply rail signals  232 ,  234  are used in the comparison  260 ,  270  with the maximum signal stored in SHA 2   240  and the minimum signal stored in SHA 3   245 , respectively. The reset signal thus forces the outputs  280 ,  290  to be updated with the input signal  220 . The comparators  260 ,  270  output is gated with the clock signal to generate the nonoverlapping phased signals required by the SHA 2   240  and SHA 3   245  sample and hold amplifiers. Thus, it is obvious to those skilled in the art that the implementation of the sample max  250  and sample min  255  control signals may be more elaborate than what is suggested in the figure. 
     Each of these control functions is, in fact, implemented by three signals that are generated as a function of the comparator outputs  260 ,  270  and the clock signals. Finally, the control signals are then driven by voltage doublers to control the sample and hold amplifiers. 
     The peak detectors are used to find the peaks of the in phase and quadrature channels. The two outputs  280 ,  290  of the peak detector are added and subtracted by subsequent blocks to generate and estimate of the offset and peak to peak signal levels, respectively. 
     FIG. 3 is a block diagram of a peak detection network. The minimum and maximum sample and hold amplifiers  330 ,  335  determine if the input is greater than the previous maximum or less than the previous minimum, the appropriate sample signal  312 ,  314  becomes active and the output is updated. The amplified and offset corrected in-phase and quadrature signal  320  is then transmitted to the peak detector to be used in the determination of the offset voltage and signal level. 
     The minimum and maximum comparator circuits  340 ,  345  compare the input signal with the signal in the maximum sample and hold amplifiers  330  and the minimum sample and hold amplifiers  335 . When the reset  310  signal is active, the multiplexor (MUX)  390  switches to allowing the supply rails signals  380 ,  385 , instead of the input signal, to be compared with the previously held maximum and minimum signals in the sample and hold amplifiers  330 ,  335 . This forces the outputs to be updated with the current input voltages. 
     The peak detector output, is combined with the minimum and maximum clock circuit signals  350 ,  355  and generates the nonoverlapping phased signal required by the sample and hold amplifiers  330 ,  335 . Two peak detectors are used to find the peaks of the in-phase and the quadrature channels. The two outputs of the peak detectors  360 ,  370  are added and subtracted by subsequent blocks to generate an estimate of the offset and the peak to peak signal levels, respectively. 
     FIG. 4 is a flow diagram illustrating a general signal transition through the peak detector. The current input value is stored in the sample and hold amplifier (SHA 1 )  400 . The current input value is compared with the value held in the maximum sample and hold amplifier (SHA 2 )  410 . If the value held in the maximum sample and hold amplifier  410  is greater than the current input  430  the maximum sample signal  450  is activated to allow the maximum sample and hold amplifier to be update with the current input value. If the value in the maximum sample and hold amplifier  430  is less than the current input the output is unchanged  470 . In either case the output is combined with a clock signal to generate a nonoverlapping maximum signal  490 . Again, the current input value is stored in the sample and hold amplifier (SHA 1 )  400 . The current input value is compared with the value held in the minimum sample and hold amplifier (SHA 3 )  420 . If the value held in the minimum sample and hold amplifier  420  is less than the current input  440  the minimum sample signal  460  is activated to allow the minimum sample and hold amplifier to be updated with the current input value. If the value in the minimum sample and hold amplifier  440  is less than the current input, the output is unchanged  480 . In either case an output is combined with the clock signal to generate a nonoverlapping minimum signal  495 . 
     FIG. 5 is a flow diagram illustrating the reset signal transition through the peak detector. When a reset signal is active  500 , the current input value is stored in the input sample and hold amplifier (SHA 1 )  505 . The activation of the reset allows the previously held maximum value in the maximum sample and hold amplifier (SHA 2 ) to be compared  510  with the supply rail voltage thus triggering a maximum sample pulse regardless of the input voltage  530 . The maximum output therefore is equal to the current input  550 . The comparator output  570  is gated with a clock signal to generate a nonoverlapping phased signal required by the maximum sample and hold amplifier (SHA 2 ). Again, when a reset signal is active  500 , the current input value is stored in the input sample and hold amplifier (SHA 1 )  505 . The activation of the reset allows the previously held minimum value in the minimum sample and hold amplifier (SHA 3 ) to be compared  520  with the supply rail voltage thus triggering a minimum sample pulse regardless of the input voltage  540 . The minimum signal output therefore is equal to the current input  560 . The comparator output  580  is gated with the clock signal to generate the nonoverlapping phased signal required by the minimum sample and hold amplifier (SHA 3 ). 
     Referring to FIG. 6, another exemplary hardware environment for comparing multiple signals from a sources shown according to the present invention. The present invention may be implemented using an peak detector  630 , comprised of a processor  640  and memory (RAM)  650 . It is envisioned that attached to the detector  630  may be a memory device  650 . Also included in this embodiment may be input devices  660 , for downloading data and commands. 
     The detector  630  may operate under the control of an operating system. The detector  630  executes one or more computer programs under the control of the operating system. 
     Generally, the operating system and the detector programs may be tangibly embodied in a computer-readable medium or carrier, e.g. one or more of the fixed or removable data storage devices  670 , or other data storage or data communications devices. Both operating system and the computer programs may be loaded from the data storage devices into the memory  650  of the detector  630  for execution by the processor  640 . Those skilled in the art will recognize that the memory  650  is optional, or may be a memory device embedded or otherwise couple to the peak detector  630 . Both the operating system and the detector programs comprise instructions which, when read and executed by the processor  640 , cause the detector to perform the steps necessary to execute the steps or elements of the present invention. 
     Although one detector system configuration is illustrated in FIG. 6, those skilled in the art will recognize that any number of different configurations performing similar functions may be used in accordance with the present invention. 
     The foregoing description of the exemplary embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not with this detailed description, but rather by the claims appended hereto.