Patent Publication Number: US-9853114-B1

Title: Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority to and the benefit of U.S. Provisional Patent Application No. 62/412,179, entitled “Partial GAA Nanowire-like FET with Stacked Nanowire-Like Channels with Simple Manufacturing Flow,” filed Oct. 24, 2016 in the U.S. Patent and Trademark Office, the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     The present disclosure relates generally to field effect transistors and methods of manufacturing field effect transistors. 
     BACKGROUND 
     Conventional circuits are commonly formed from non-planar “fin” field effect transistors (finFETs). Conventional finFETs generally include multiple vertical fins serving as conducting channel regions. Narrowing the width of the fin channel regions improves gate control of the potential in the fin channel regions. Accordingly, conventional finFETs may be provided with narrow fin widths to reduce short-channel effects and thus enable scaling to shorter gate lengths. However, as gate lengths are scaled, conventional finFETs may fail to provide the desired performance (e.g., I eff −I off ). Additionally, conventional finFETs are not a gate-all-around (GAA) structure, and therefore gate control is only on sides of the fins, which limits further gate length scaling. 
     Future technologies have contemplated forming circuits from either gate-all-around (GAA) nanowire (NW) FETs or GAA nanosheet (NS) FETs in order to reduce short-channel effects and thereby enable scaling to shorter gate lengths. However, both GAA NW FETs and GAA NS FETs present integration problems. For instance, GAA FETs require an internal spacer to separate the GAA gate metal from the source/drain regions to reduce parasitic capacitance. Additionally, GAA FETs generally require that the GAA gate metal is formed in a narrow vertical region between the bottom of an overlying channel region and the top of an underlying channel region to reduce parasitic capacitance. However, forming the GAA gate metal in a narrow vertical region between the channel regions makes it difficult to achieve the desired threshold voltage (V t ). 
     SUMMARY 
     The present disclosure is directed to various embodiments of a field effect transistor (FET) for an nFET and/or a pFET device. In one embodiment, the FET includes a fin including a stack of nanowire-like channel regions. The stack includes at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region. The FET also includes a source electrode and a drain electrode on opposite sides of the fin. The FET further includes a dielectric separation region including SiGe between the first and second nanowire-like channel regions. The dielectric separation region extends completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region. The FET also includes a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer of the gate stack does not extend between the first and second nanowire-like channel regions. 
     The FET may also include an external spacer on the fin. The dielectric separation region may extend to a lateral extent under the external spacer. The lateral extent to which the dielectric separation region extends may be the same as the external spacer. 
     The material of the dielectric separation region may be different than a dielectric material of the gate dielectric layer. 
     The dielectric separation region may be a portion of the gate dielectric layer of the gate stack. 
     Each nanowire-like channel region of the stack of nanowire-like channel regions may have a width from approximately 3 nm to approximately 8 nm, such as from approximately 4 nm to approximately 6 nm. Each nanowire-like channel region of the stack of nanowire-like channel regions may have a height from approximately 4 nm to approximately 12 nm, such as from approximately 4 nm to approximately 8 nm. The dielectric separation region may have a thickness from approximately 2 nm to approximately 6 nm, such as from approximately 2 nm to approximately 4 nm. 
     The FET may include a first fin and a second fin having a second stack of nanowire-like channel regions adjacent to the first fin. A separation distance between the first fin and the second fin may be greater than a thickness of the dielectric separation region. 
     The dielectric separation region of the stack of nanowire-like channel regions may have a thickness up to approximately twice a thickness of the gate dielectric layer of the gate stack. 
     Each nanowire-like channel region of the stack of nanowire-like channel regions may include silicon, the surface of the second nanowire-like channel region facing the first nanowire-like channel region and the surface of the first nanowire-like channel region facing the second nanowire-like channel region may each have a (100) orientation, and the pair of sidewalls of the stack of nanowire-like channel regions may each have a (110) orientation. 
     Each nanowire-like channel region of the stack of nanowire-like channel regions may include silicon, and the surface of the second nanowire-like channel region facing the first nanowire-like channel region, the surface of the first nanowire-like channel region facing the second nanowire-like channel region, and the pair of sidewalls of the stack of nanowire-like channel regions may each have a (110) orientation. 
     The first and second nanowire-like channel regions may be strained. 
     The present disclosure is also directed to various method of forming a field effect transistor (FET) for an nFET and/or a pFET device. The method includes forming a stack of alternating sacrificial layers and conducting channel layers on a substrate and etching the stack to form at least one fin. The at least one fin includes a stack of nanowire-like channel regions and the stack includes at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region. The method also includes forming a source electrode on a first side of the at least one fin and forming a drain electrode on a second side of the at least one fin opposite to the first side. The method further includes forming a dielectric separation region between the first and second nanowire-like channel regions of the stack of nanowire-like channel regions. The dielectric separation region extends completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region. The method also includes forming a gate stack including a gate dielectric layer and a metal layer on the gate dielectric layer. The gate stack extends along a pair of sidewalls of the stack of nanowire-like channel regions, and the metal layer of the gate stack does not extend between the first and second nanowire-like channel regions of the stack of nanowire-like channel regions. 
     The method may also include forming an external spacer on the at least one fin. The dielectric separation region may extend to a lateral extent under the external spacer. The lateral extent to which the dielectric separation region extends may be the same as the external spacer. 
     The etching of the stack may include forming a first fin and a second fin adjacent to the first fin. A horizontal separation distance between the first fin and the second fin may be at least as great as a vertical separation distance between adjacent nanowire-like channel regions in the first fin or the second fin. 
     The dielectric separation region may be formed during the forming of the gate stack, and the dielectric separation region may be a portion of the gate dielectric layer of the gate stack. 
     The method may include removing the sacrificial layers before the forming of the dielectric separation region. 
     The forming of the source electrode and the drain electrode may include forming pFET source and drain electrodes by depositing an Si buffer layer followed by depositing a layer of SiGe or SiGeB, such as by an epitaxial deposition process, and the removing of the sacrificial layers may not remove the pFET source and drain electrodes due to the Si buffer layer. 
     The sacrificial layers may include SiGe, the layer of the pFET source and drain regions may include SiGe, and a portion of the layer of the pFET source and drain regions adjacent to the sacrificial layers may have a concentration of Ge that is the same or different than a concentration of Ge in the sacrificial layers. 
     The forming of the source electrode and the drain electrode may include forming nFET source and drain regions including Si by epitaxial deposition, and the removing of the sacrificial layers may not remove the nFET source and drain electrodes due to the Si. 
     The conducting channel layers may include Si, the sacrificial layers may include SiGe, and the Ge content of the SiGe may be from approximately 10% to approximately 50%. 
     The method may also include forming a conventional finFET for the nFET and/or the pFET device, and the forming of the conventional finFET may not utilize sacrificial layers. 
     The conducting channel layers may include Si and the sacrificial layers may include SiGe, and the method may not include removing the sacrificial layers before the forming of the gate stack. 
     This summary is provided to introduce a selection of features and concepts of embodiments of the present disclosure that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in limiting the scope of the claimed subject matter. One or more of the described features may be combined with one or more other described features to provide a workable device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features and advantages of embodiments of the present disclosure will become more apparent by reference to the following detailed description when considered in conjunction with the following drawings. In the drawings, like reference numerals are used throughout the figures to reference like features and components. The figures are not necessarily drawn to scale. 
         FIGS. 1A-1B  are a schematic perspective view and a schematic cross-sectional view, respectively, of a field effect transistor (FET) according to one embodiment of the present disclosure; and 
         FIGS. 2A-2B  depict a schematic cross-sectional view and a schematic top view, respectively, of a task of a method of forming a FET according to one embodiment of the present disclosure; 
         FIGS. 2C-2D  depict a schematic cross-sectional view and a schematic top view, respectively, of another task of the method of forming the FET according to one embodiment of the present disclosure; 
         FIG. 2E  depicts a schematic top view of a further task of the method of forming the FET according to one embodiment of the present disclosure; 
         FIGS. 2F-2G  depict a schematic cross-sectional view and a schematic top view, respectively, of another task of the method of forming the FET according to one embodiment of the present disclosure; 
         FIGS. 2H-2I  depict a schematic cross-sectional view and a schematic top view, respectively, of another task of the method of forming the FET according to one embodiment of the present disclosure; and 
         FIGS. 2J-2K  depict a schematic cross-sectional view and a schematic top view, respectively, of a further task of the method of forming the FET according to one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure is directed to various embodiments of a field effect transistor (FET) and methods of manufacturing the same. The FETs of the present disclosure include a stack of nanowire-like channels and a gate stack including a dielectric layer and a metal layer. According to one or more embodiments of the present disclosure, the dielectric layer of the gate stack extends completely around each of the nanowire-like channels, whereas the metal layer of the gate stack extends along sides of the nanowire-like channels, but does not extend between adjacent nanowire-like channels in the stack of nanowire-like channels. Accordingly, the FETs of the present disclosure are partial-GAA nanowire-like FETs (i.e., partial GAA NW-like FETs). Providing the full gate stack (i.e., the dielectric layer and the metal layer) along the sides of the nanowire-like channels affords improved control of the channel potential compared to conventional finFETs due to gate coupling to each nanowire-like channel through the dielectric layer at the top and bottom of each nanowire-like channel in addition to the gate coupling to each nanowire-like channel through the dielectric layer along the sides of each nanowire-like channel. The FETs of the present disclosure are configured to enable scaling to shorter gate lengths compared to conventional FETs by improving gate control of the potential in the conducting fin channel regions. The FETs of the present disclosure are also configured to enable these shorter gate lengths without creating the integration problems associated with conventional full gate-all-around (GAA) nanosheet FETs and full GAA nanowire FETs. 
     Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numbers refer to like elements throughout. The present invention, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present invention to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present invention may not be described. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof may not be repeated. 
     In the drawings, the relative sizes of elements, layers, and regions may be exaggerated and/or simplified for clarity. Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. 
     It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present invention. 
     It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present. 
     The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the present invention. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. 
     As used herein, the term “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by those of ordinary skill in the art. Further, the use of “may” when describing embodiments of the present invention refers to “one or more embodiments of the present invention.” As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Also, the term “exemplary” is intended to refer to an example or illustration. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. 
     With reference now to  FIGS. 1A-1B , a field effect transistor (FET)  100  according to one embodiment of the present disclosure includes a source electrode  101 , a drain electrode  102 , at least one fin  103  extending between the source and drain electrodes  101 ,  102 , and a gate stack  104  including a gate dielectric layer  105  and a metal layer  106  on the dielectric layer  105 . The source and drain electrodes  101 ,  102 , the fin  103 , and the gate stack  104  are formed on a substrate  107  (e.g., a bulk-silicon substrate or a silicon-on-insulator (SOI) substrate). As illustrated in  FIG. 1B , each of the fins  103  is divided or separated into a stack of discrete nanowire-like channel regions  108 . Although in the illustrated embodiment the stack includes three nanowire-like channel regions  108 , in one or more embodiments, the stack may include any other suitable number of nanowire-like channel regions  108 , such as two channel regions or more than three channel regions. In one or more embodiments, the nanowire-like channel regions  108  may be strained. 
     As illustrated in  FIG. 1B , the gate dielectric layer  105 , or a portion of the gate dielectric layer  105 , of the gate stack  104  extends completely around each of the nanowire-like channel regions  108  (i.e., the gate dielectric layer  105 , or a portion of the gate dielectric layer  105 , of the gate stack  104  extends along an upper surface  109 , a lower surface  110 , and a pair of opposing sidewalls or side surfaces  111 ,  112  of each of the nanowire-like channel regions  108 ). Accordingly, in the illustrated embodiment, for each pair of adjacent nanowire-like channel regions  108 , the gate dielectric layer  105  or a portion of the gate dielectric layer  105  of the gate stack  104  separates the upper surface  109  of the underlying nanowire-like channel region  108  from the lower surface  110  of the overlying nanowire-like channel region  108 . Additionally, in the illustrated embodiment, the metal layer  106  of the gate stack  104  extends along the side surfaces  111 ,  112  of the nanowire-like channel regions  108  and along the upper surface  109  of the uppermost nanowire-like channel region  108  (i.e., the metal layer  106  extends around or covers the nanowire-like channel regions  108  of the fin  103 ) but the metal layer  106  does not extend between adjacent nanowire-like channel regions  108  or between the lowermost nanowire-like channel region  108  and the substrate  107 . Accordingly, in the illustrated embodiment, the full gate stack  104  (i.e., the gate dielectric layer  105  and the metal layer  106 ) does not extend fully or completely around each of the nanowire-like channel regions  108  such that the FET  100  of the present disclosure is a partial gate-all-around (GAA) FET rather than a full GAA FET. Providing the full gate stack  104  along the side surfaces  111 ,  112  of the nanowire-like channels  108  affords improved control of the channel potential compared to a conventional finFET structure due to gate coupling to each nanowire-like channel region  108  through the gate dielectric layer  105  along the upper and lower surfaces  109 ,  110  of each nanowire-like channel  108  in addition to the gate coupling to each nanowire-like channel region  108  through the gate dielectric layer  105  along the side surfaces  111 ,  112  of each of the nanowire-like channel regions  108 . 
     In one or more embodiments, the gate dielectric layer  105  of the gate stack  104  may not extend, or may not substantially extend, between adjacent nanowire-like channel regions  108  and the FET  100  may include a separate dielectric layer vertically separating adjacent nanowire-like channel regions  108 . The separate dielectric layer may be formed from a dielectric material different than a dielectric material of the gate dielectric layer  105  of the gate stack  104 . That is, the dielectric layer may extend along the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  and the gate dielectric layer  105  may extend along the side surfaces  111 ,  112  of the nanowire-like channel regions  108  such that the dielectric constant of the dielectric layer extending between adjacent nanowire-like channel regions  108  (e.g., along upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108 ) is different than the dielectric constant of the gate dielectric layer  105  extending along the side surfaces  111 ,  112  of the nanowire-like channel regions  108 . Accordingly, the FET  100  includes one or more separation regions  113  vertically separating adjacent nanowire-like channel regions  108  that are formed of a dielectric material that may be the same as or different than the dielectric material of the gate dielectric layer  105  of the gate stack  104 . Providing one or more dielectric layers extending along the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  105  that have a different dielectric constant than the gate dielectric layer  105  extending along the side surfaces  111 ,  112  of the nanowire-like channel regions  108  may provide improved electron transport along the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  and/or more desired gate coupling to the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108 . 
     In one or more embodiments, the nanowire-like channel regions  108  may have a channel width W from approximately 3 nm to approximately 8 nm and a channel height H from approximately 4 nm to approximately 12 nm and the portions of the gate dielectric layer  105  of the gate stack  104  extending between the nanowire-like channel regions  108  may have a thickness T from approximately 2 nm to approximately 6 nm such that adjacent nanowire-like channel regions  108  of the fin  103  are separated by approximately 2 nm to approximately 6 nm. In one or more embodiments, the nanowire-like channel regions  108  may have a channel width W from approximately 4 nm to approximately 6 nm and a channel height H from approximately 4 nm to approximately 8 nm and the portions of the gate dielectric layer  105  of the gate stack  104  extending between the nanowire-like channel regions  108  may have a thickness T from approximately 2 nm to approximately 4 nm such that adjacent nanowire-like channel regions  108  of the fin  103  are separated by approximately 2 nm to approximately 4 nm. Providing the nanowire-like channel regions  108  with a channel height H from approximately 4 nm to approximately 8 nm (e.g., from approximately 3 nm to approximately 7 nm) and providing portions of the gate dielectric layer  105  of the gate stack  104  extending between the nanowire-like channel regions  108 , which may have with a thickness T from approximately 2 nm to approximately 4 nm, may achieve improved electron transport in the nanowire-like channel regions  108  of the fin  103  due to increased injection velocity from quantum confinement. Additionally, this increased injection velocity is not substantially offset by increased phonon or surface-roughness scattering rates. Providing the nanowire-like channel regions  108  with a channel height H from approximately 4 nm to approximately 8 nm (e.g., from approximately 3 nm to approximately 7 nm) and providing portions of the gate dielectric layer  105  of the gate stack  104  extending between the nanowire-like channel regions  108 , which may have with a thickness T from approximately 2 nm to approximately 4 nm, may further achieve improved electrostatic control of the nanowire-like channel regions  108  of the fin  103  due to coupling of fringing fields from the gate stack  104  to the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108 , thereby reducing short-channel effects and enabling scaling to shorter gate lengths if desired. 
     In the illustrated embodiment, the FET  100  also includes a second fin  103  including a second stack of nanowire-like channel regions  108  adjacent to the first fin  103  including the first stack of nanowire-like channel regions  108 . In the illustrated embodiment, the gate stack  104  (i.e., the gate dielectric layer  105  and the metal layer  106 ) extend around the second fin  103  in the same manner that the gate stack  104  extends around the first fin  103 . In one or more embodiments, the FET  100  may include any other suitable number of fins each including a stack of nanowire-like channel regions  108 , such as, for instance, three or more fins. In one or more embodiments, the first fin  103  (i.e., the first stack of nanowire-like channel regions  108 ) is spaced apart from the second fin  103  (i.e., the second stack of nanowire-like channel regions  108 ) by a distance D at least as great as the separation distance between adjacent nanowire-like channel regions  108  in the first and second stacks (e.g., the horizontal separation distance D between the first and second stacks of nanowire-like channel regions  108  is at least as great as the thickness T of the portions of the gate dielectric layer  105  vertically separating adjacent nanowire-like channel regions  108 ). In one or more embodiments, the distance D that the first stack of nanowire-like channel regions  108  is spaced apart from the second stack of nanowire-like channel regions  108  is greater than the separation distance between adjacent nanowire-like channel regions  108  in the first and second fins  103 . 
     Additionally, in one or more embodiments, the thickness T of the portions of the gate dielectric layer  105  vertically separating adjacent nanowire-like channel regions  108  is different than a thickness t D  of the portions of the gate dielectric layer  105  extending along the side surfaces  111 ,  112  of the nanowire-like channel regions  108  (e.g., the thickness T of the portions of the gate dielectric layer  105  extending along the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  is different than the thickness t D  of the portions of the gate dielectric layer  105  extending along the side surfaces  111 ,  112  of the nanowire-like channel regions  108 ). That is, the gate dielectric layer  105  may have a non-uniform (e.g., varying) thickness. In one or more embodiments, the thickness T of the portions of the gate dielectric layer  105  vertically separating adjacent nanowire-like channel regions  108  is equal to or less than approximately twice the thickness t D  of the portions of the gate dielectric layer  105  extending along the side surfaces  111 ,  112  of the nanowire-like channel regions  108 . 
     In one or more embodiments, the thickness t D  of the gate dielectric layer  105  of the gate stack  104  may be from approximately 1 nm to approximately 3 nm and the thickness t M  of the metal layer  106  of the gate stack  104  may be greater than a thickness of a work-function tuning metal layer having a thickness from approximately 1 nm to approximately 5 nm. 
     In one or more embodiments, the FET  100  may include one or more n-type FETs and/or one or more p-type FETs. In one or more embodiments, the nanowire-like channel regions  108  may be formed of silicon (Si), the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  have a (100) orientation, and the side surfaces  111 ,  112  of the nanowire-like channel regions  108  have a (110) orientation. In one or more embodiments, the nanowire-like channel regions  108  may be formed of Si, the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  have a (110) orientation, and the side surfaces  111 ,  112  of the nanowire-like channel regions  108  have a (110) orientation. In one or more embodiments, the FET  100  includes an n-type FET having nanowire-like channel regions  108  formed of Si, a p-type FET having nanowire-like channel regions  108  formed of silicon germanium (SiGe), the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions have a (110) orientation or a (100) orientation, and the side surfaces  111 ,  112  of the nanowire-like channel regions  108  have a (110) orientation. In one or more embodiments in which the FET  100  includes both n-type FETs and p-type FETs, the orientation of the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  of the n-type FETs may be the same as the orientation of the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  of the p-type FETs. In one or more embodiments in which the FET  100  includes both n-type FETs and p-type FETs, the nanowire-like channel regions  108  of both the n-type FETs and the p-type FETs may be formed of Si, the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  of the n-type FET may have a (100) orientation, and the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  of the p-type FET may have a (110) orientation. In one or more embodiments in which the FET  100  includes both n-type FETs and p-type FETs, the nanowire-like channel regions  108  of both the n-type FETs and the p-type FETs may be formed of Ge, the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  of the n-type FET may have a (111) orientation, and the upper and lower surfaces  109 ,  110  of the nanowire-like channel regions  108  of the p-type FET may have a (110) orientation. In one or more embodiments in which the FET  100  includes both n-type FETs and p-type FETs, the nanowire-like channel regions  108  of the n-type FETs may be made from Si, Ge, SiGe, or a group III-V material, the nanowire-type channel regions  108  of the p-type FETs may be made of Si, Ge, or SiGe, and the surface orientation of upper and lower surfaces  109 ,  110  of the nanowire-like channels  108  of the n-type or p-type FETs may be Si (110), Ge (110) n-type Si FET (100), p-type Si FET (110), n-type Ge FET (111), or p-type Ge FET (110). 
     In one or more embodiments, the gate dielectric layer  105  of the gate stack  104  may be formed of a high-K dielectric material, such as, for example, a material having a K greater than 10 (e.g., HFO 2 ). In one or more embodiments, the nanowire-like channel regions  108  may be formed of Si, SiGe, Ge, or a group III-V material, such as indium gallium arsenide (InGaAs), indium arsenide (InAs), or indium antimonide (InSb). 
     In one or more embodiments, the metal layer  106  of the gate stack  104  may include a work-function tuning metal layer. In one or more embodiments, the metal layer  106  of the gate stack  104  may include a low-resistance metal cladding layer adjacent to the work-function tuning metal layer. 
       FIGS. 2A-2K  depict tasks of a method of forming a field effect transistor (FET) according to one embodiment of the present disclosure. As illustrated in  FIGS. 2A-2B , the method includes a task of layer-by-layer deposition of an stack of alternating sacrificial layers  201  and conducting channel layers  202  on a silicon substrate  203  such that the lowermost sacrificial layer  201  is directly on the silicon substrate  203  and each conducting channel layer  202  is between a pair of sacrificial layers  201 . The silicon substrate  203  may include a (100) or (110) silicon (Si) substrate. Although in the illustrated embodiment the task includes depositing three conducting channel layers  202  and four sacrificial layers  201 , in one or more embodiments, the task may include depositing any other suitable number of conducting channel layers  202  and sacrificial layers  201  depending on the desired size of the FET (e.g., the task may include depositing one or more conducting channel layers  202 ). In one or more embodiments, the sacrificial layers  201  are formed of SiGe and the conducting channel layers  202  are formed of Si. In one or more embodiments, the SiGe material of the sacrificial layers  201  may include Ge in the range from approximately 10% to approximately 50% (e.g., from approximately 15% to approximately 35% or from approximately 20% to approximately 30%). In one or more embodiments, the sacrificial layers  201  have a thickness from approximately 2 nm to approximately 6 nm (e.g., approximately 2 nm to approximately 4 nm) and the conducting channel layers  202  have a thickness from approximately 4 nm to approximately 12 nm (e.g., a thickness from approximately 4 nm to approximately 8 nm). In one or more embodiments, the conducting channel layers  202  and the sacrificial layers  201  may not be formed of Si and SiGe, respectively. In one or more embodiments, the conducting channel layers  202  and the sacrificial layers  201  may be any other suitable materials whereby the sacrificial layers  201  can be selectively etched relative to conducting channel layers  202  for n-type FETs, p-type FETs, or both n-type and p-type FETs. In one or more embodiments in which the FET is an n-type FET, the materials of the conducting channel layers  202  and the sacrificial layers  201  may be Group III-V materials, such as InGaAs and InP, respectively. In one or more embodiments, the materials of the conducting channel layers  202  and the sacrificial layers  201  may be Group IV materials, such as Ge and SiGe, respectively, for either n-type FETs or p-type FETs. In one or more embodiments in which the FET is a p-type FET, the materials of the conducting channel layers  202  and the sacrificial layers  201  may be Group IV materials, such as SiGe and Si, respectively. 
     In one or more embodiments, the conducting channel layers  202  may be formed of Si, upper and lower surfaces of the conducting channel layers  202  have a (100) orientation, and sidewalls of the conducting channel layers  202  have a (110) orientation. In one or more embodiments, the conducting channel layers  202  may be formed of Si, the upper and lower surfaces of the conducting channel layers  202  have a (110) orientation, and the sidewalls of the conducting channel layers  202  have a (110) orientation. In one or more embodiments in which the FET includes both n-type and p-type FETs, the n-type FET has conducting channel layers  202  formed of Si, the p-type FET has conducting channel layers  202  formed of SiGe, the upper and lower surfaces of the conducting channel layers  202  have a (110) orientation or a (100) orientation, and the sidewalls of the conducting channel layers  202  have a (110) orientation. In one or more embodiments in which the FET includes both n-type FETs and p-type FETs, the orientation of the upper and lower surfaces of the conducting channel layers  202  of the n-type FETs may be the same as the orientation of the upper and lower surfaces of the conducting channel layers  202  of the p-type FETs. In one or more embodiments in which the FET includes both n-type FETs and p-type FETs, the conducting channel layers  202  of both the n-type FETs and the p-type FETs may be formed of Si, the upper and lower surfaces of the conducting channel layers  202  of the n-type FET may have a (100) orientation, and the upper and lower surfaces of the conducting channel layers  202  of the p-type FET may have a (110) orientation. In one or more embodiments in which the FET includes both n-type FETs and p-type FETs, the conducting channel layers  202  of both the n-type FETs and the p-type FETs may be formed of Ge, the upper and lower surfaces of the conducting channel layers  202  of the n-type FET may have a (111) orientation, and the upper and lower surfaces of the conducting channel layers  202  of the p-type FET may have a (110) orientation. In one or more embodiments in which the FET includes both n-type FETs and p-type FETs, the conducting channel layers  202  of the n-type FETs may be made from Si, Ge, SiGe, or a group III-V material, the conducting channel layers  202  of the p-type FETs may be made of Si, Ge, or SiGe, and the surface orientation of upper and lower surfaces of the conducting channel layers  202  of the n-type or p-type FETs may be Si (110), Ge (110) n-type Si FET (100), p-type Si FET (110), n-type Ge FET (111), or p-type Ge FET (110). 
     In one or more embodiments in which the conducting channel layers  202  are formed of materials from different groups (e.g., Group IV, Group III-V) and/or in which the conducting channel layers  202  do not have the same surface orientation, the conducting channel layers  202  may be formed by epitaxial growth from a starting material on an insulator and/or a separate epitaxial growth from a bulk substrate. 
     With reference now to  FIGS. 2C-2D , the method according to one embodiment of the present disclosure includes a task of patterning and etching the stack of conducting channel layers  202  and sacrificial layers  201  to form at least one fin  204 . The task of patterning and etching the stack of alternating conducting channel layers  202  and the sacrificial layers  201  may be performed by any suitable process or technique, such as, for instance, lithography, sidewall-image transfer, or dry etching. In the illustrated embodiment, the task includes forming two adjacent fins  204 , although in one or more embodiments, the task may include forming any other desired number of fins  204 , such as one fin or three or more fins. As illustrated in  FIG. 2C , each of the fins  204  includes a stack of nanowire-like channel regions  205  formed from the material of the conducting channel layers  202 . The task of patterning and etching the stack includes forming the one or more fins with the desired channel height H, the desired channel width W and, in the case of two or more fins, forming the fins  204  with the desired horizontal separation distance D between adjacent fins  204 . In one or more embodiments, the method includes forming two or more fins  204  in which the horizontal separation distance D between two adjacent fins  204  is at least as great as the thickness T of the sacrificial layers  201 . In one or more embodiments, the task may include forming the one or more fins  204  with a channel width W from approximately 3 nm to approximately 8 nm, such as, for example, a channel width W from approximately 4 nm to approximately 6 nm. The channel width W of the one or more fins  204  may vary depending on the type of device into which the FET is designed to be incorporated. In one or more embodiments, the task of forming the one or more fins  204  may include a single mask task and a single etch task or two or more mask and etch tasks. Additionally, in one or more embodiments, the task may include an etch (e.g., a dry etch) that is not selective to either the channel layer material or the sacrificial layer material. Furthermore, the task may be utilized to form one or more fins  204  for nFETs and pFETs. 
     With continued reference to  FIG. 2D , the method also includes a task of forming a dummy gate  206  (e.g., a dummy gate formed of oxide/poly-Si/nitride) and forming an external sidewall spacer  207  by any process known in the art, such as nitride deposition. 
     The method also includes a task of masking source and drain regions and etching the one or more fins  204  in regions not protected by the dummy gate  206  and the external sidewall spacer  207  formed during the task described above with reference to  FIGS. 2C-2D . In one or more embodiments, the etching of the one or more fins  204  proceeds all the way down to, or into, the silicon substrate  203 . 
     With reference now to  FIG. 2E , the method also includes a task of forming source and drain regions  208 ,  209  (e.g., nFET source and drain regions or pFET source and drains) by, for example, epitaxial deposition. In one or more embodiments, the source and drain regions  208 ,  209  may be nFET source and drain regions formed from any suitable material, such as Si, SiP, or SiCP. In one or more embodiments, the nFET source and drain regions  208 ,  209  may be formed of Si having impurities, such as phosphorous (P) or carbon (C). During the task of epitaxial deposition, the source and drain regions  208 ,  209  will form from a bottom and along sidewalls of the etched region, thereby connecting the source and drain regions  208 ,  209  to the nanowire-like channel regions  205  and the sacrificial layers  201 . Additionally, in one or more embodiments, during the task of epitaxial deposition, the nFET source and drain regions  208 ,  209  grow from the silicon substrate  203  to enable strain in the channel regions. 
     The method also includes a task of removing the masking of the source and drain regions  208 ,  209  (i.e., unmasking the source and drain regions  208 ,  209 ). 
     In one or more embodiments, the task of forming the source and drain regions  208 ,  209  may include a task of forming pFET source and drain regions by, for example, epitaxial deposition. In one or more embodiments, the task of forming the pFET source and drain regions  208 ,  209  includes depositing a buffer layer of Si having a thickness, for example, from approximately 1 nm to approximately 5 nm (e.g., approximately 1.5 nm), followed by depositing a layer of SiGe, SiGeB, or a similar material. In one or more embodiments, the task may include depositing a SiGe layer having impurities, such as boron (B) or tin (Sn). In one or more embodiments, a portion of the buffer layer adjacent to the sacrificial layers  201  may be formed from SiGe. In one or more embodiments, a portion of the SiGe of the pFET source and drain regions  208 ,  209  adjacent to the SiGe sacrificial layers  201  may have the same or different concentration of Ge as the SiGe sacrificial layers  201 . In one or more embodiments in which the sacrificial layers  201  are formed of Si, the task of forming the pFET source and drain regions  208 ,  209  may not include depositing the buffer layer of Si, although in one or more embodiments, the task of forming the pFET source and drain regions  208 ,  209  may include depositing the buffer layer of Si even when the sacrificial layers  201  are formed of Si. During the task of epitaxial deposition, the pFET source and drain regions  208 ,  209  will form from a bottom and along sidewalls of the etched region, thereby connecting the source and drain regions  208 ,  209  to the nanowire-like channel regions  205  and the sacrificial layers  201 . Additionally, in one or more embodiments, during the task of epitaxial deposition, the pFET source and drain regions  208 ,  209  grow from the silicon substrate  203  to enable strain in the channel regions. 
     With reference now to  FIGS. 2F-2G , the method also includes tasks of depositing an interlayer dielectric (ILD)  210 , performing chemical mechanical planarization (CMP) to a top of the dummy gate  206 , and then removing the dummy gate  206  to expose the one or more fins  204 . With continued reference to  FIGS. 2F-2G , the method also includes a task of removing the SiGe sacrificial layers  201  by wet or dry etch that is selective with respect to Si, including selective with respect to the Si nanowire-like channel regions  205 . The selective etching of the sacrificial layers  201  will not etch into the pFET or nFET source and drain regions  208 ,  209  because these regions include an Si material adjacent to the sacrificial layers  201 . In one or more embodiments in which the sacrificial layers  201  have sufficient dielectric properties (e.g., for nFET, the sacrificial layers  201  are formed of SiGe or InP), the method may not include the task of removing the sacrificial layers  201  before a subsequent task, described below, of forming a gate stack  211 . In one or more embodiments, the method may include partially removing the sacrificial layers  201  prior to the task of forming the gate stack  211 . 
     With reference now to  FIGS. 2H-2K , the method also includes forming the gate stack  211  by forming a gate dielectric layer  212  (see  FIGS. 2H-2I ) and then forming a metal layer  213  ( FIGS. 2J-2K ) on the gate dielectric layer  212  by any process or processes known in the art, such as atomic-layer deposition (ALD). During the task of forming the gate stack  211 , the gate dielectric layer  212 , or a portion of the gate dielectric layer  212 , fills the regions of the removed sacrificial layers  201  (i.e., the gate dielectric layer  212 , or a portion of the gate dielectric layer  212 , fills the regions previously occupied by the sacrificial layers  201 ). The gate dielectric layer  212  also forms over each of the one or more fins  204  (i.e., the gate dielectric layer  212  forms along the sides of the nanowire-like channel regions  205  and along an upper surface of the uppermost nanowire-like channel region  205  in each fin  204 ). Accordingly, following the task of forming the gate stack  211 , each of the fins  204  includes a stack of two or more nanowire-like channel regions  205  separated by portions of the gate dielectric layer  212 . Additionally, during the task of forming the gate stack  211 , the metal layer  213  forms on the gate dielectric layer  212  and around each of the one or more fins  204  such that the metal layer  213  extends along the sidewalls of the nanowire-like channel regions  205  and along the upper surface of the uppermost nanowire-like channel region  205  of each fin  204 . Since the gate dielectric layer  212 , or a portion of the gate dielectric layer  212 , fills the regions of the removed sacrificial layers  201 , the metal layer  213  of the gate stack  211  does not deposit into the regions of the removed sacrificial layers  201 . Accordingly, following the task of forming the gate stack  211 , the metal layer  213  of the gate stack  211  does not extend between the nanowire-like channel regions  205  (i.e., unlike the gate dielectric layer  212 , the metal layer  213  does not extend along the upper and lower surfaces of each of the nanowire-like channel regions  205 ). 
     In one or more embodiments, the method may include a task of forming (e.g., depositing) a dielectric layer in the regions of the removed sacrificial layers  201  and removing (e.g., etching) portions of the dielectric layer along the sidewalls of the nanowire-like channel regions  205  before the task of forming the gate stack  211  (e.g., the method may include forming a dielectric layer along the upper and lower surfaces of the nanowire-like channel regions  205  before forming the gate stack  211 ). The dielectric material of the dielectric layer is different than the dielectric material of the gate dielectric layer  212  of the gate stack  211  (e.g., the dielectric layer has a dielectric constant different than the dielectric constant of the gate dielectric layer  212 ). Accordingly, following the task of forming the gate stack  211 , the dielectric constant of the dielectric layer extending between adjacent nanowire-like channel regions  205  (e.g., along upper and lower surfaces of the nanowire-like regions  205 ) is different than the dielectric constant of the gate dielectric layer extending along the sidewalls of the nanowire-like channel regions  205 . Providing dielectric layers with different dielectric constants along the upper and lower surfaces of the nanowire-like channel regions  205  compared to along the sidewalls of the nanowire-like channel regions  205  may provide improved electron transport along the upper and lower surfaces of the nanowire-like channel regions  205  and/or more desired gate coupling to the upper and lower surfaces of the nanowire-like channel regions  205 . 
     The method also includes completing formation of the FET and a circuit including one or more of the FETs by tasks known in the art, including CMP tasks to enable gate metal only in the removed dummy gate regions, followed by a task of contact formation, and a task of back-end-of-line (BEOL) formation. Additionally, in one or more embodiments, the method may include forming partial gate-all-around (GAA) FETS, conventional full GAA FETs, and/or conventional finFETs on the same chip/circuit as the FET formed according to the tasks of the present disclosure described above.