Patent Publication Number: US-8536639-B2

Title: I-shape floating gate for flash memory device and fabricating the same

Description:
CROSS-REFERENCE OF RELATED APPLICATIONS 
     This application is a U.S. National Stage Application of International Application No. PCT/CN2012/074965 filed May 5, 2012, which claims priority from Chinese Patent Application No. 201110320029.4 filed on Oct. 20, 2011. The entirety of all the above-listed applications are which is incorporated herein by reference in it&#39;s entirety. 
     FIELD OF THE INVENTION 
     The present invention relates to a nonvolatile memory of a manufacturing technology of an ultra-large-scaled integrated circuit, and in particular, to a floating gate structure of a flash memory, which is capable of increasing a coupling ratio of the flash memory, reducing a crosstalk between adjacent cells, lowering an operating voltage and improving reliability, and a method for fabricating the same. 
     BACKGROUND OF THE INVENTION 
     Nowadays a flash memory is a mainstream technology of a nonvolatile memory. The flash memory has advantages of being able to keep data in a case of power-off, having a good compatibility with a CMOS process and capable of erasing and writing data for multiple times, etc., and thus it is widely used in various products, for example, a storage and communication device such as a mobile phone, a laptop, a palmtop and a solid state driver. The flash memory usually employs a polysilicon floating gate to store data (charges). The flash memory cell and its floating gate structure are usually as shown in  FIG. 1 , where a voltage on a control gate controls a channel of the flash memory cell via the floating gate by a certain coupling ratio. The larger the coupling ratio is, the stronger the control capability of the control gate to the channel will be. Therefore, by improving the coupling ratio of the flash memory device, an operating voltage of the flash memory for programming and erasing may be reduced, and an influence on the reliability caused by a fluctuation of the number of charges stored on the floating gate may also be reduced. The coupling ratio Cr may be calculated via a formula 
               Cr   =     Cono   Ctotal       ,         
where Ctotal is a summation of capacitances between the floating gate and all of the other electrodes, and Cono is a capacitance between the floating gate and the control gate, thus the coupling ratio may be effectively increased by increasing Cono. However, with a rapid diminishing of a size of the flash memory device, a space between adjacent cells is reduced drastically. In order to reduce a crosstalk between adjacent cells, a thickness of the floating gate should also be correspondingly reduced greatly, which causes an area of a dielectric layer between the floating gate and the control gate to be reduced drastically, thereby the capacitance value Cono is also reduced greatly. Thus, the coupling ratio is diminished with the diminishing of the size of the flash memory device, which may cause problems that it is difficult to lower an operating voltage and an anti-interference ability is poor. It is an effective method to improve the coupling ratio of the flash memory cell by employing a dielectric material having a high dielectric constant and increasing the contact area between the floating gate and the control gate in structure design.
 
     SUMMARY OF THE INVENTION 
     An object of an embodiment of present invention is to provide a   floating gate structure of a flash memory device, and a method for fabricating the same. 
     A technical solution according to an embodiment of the invention is as followings. 
     According to the embodiment of the invention, a cross section of the floating gate structure of the flash memory device in the direction of a width of a channel are formed in a  , that is, the floating gate structure is divided into three parts having an upper part, a middle part and a lower part, wherein the upper part and the lower part are wider, and the middle part is narrower. Thus, under the same device size, an area between the floating gate and a control gate of the flash memory device may be effectively increased, thereby attaining objects of improving a coupling ratio of the flash memory device, lowering an operating voltage and improving a reliability thereof. 
     A method for fabricating a floating gate structure of the flash memory device according to one embodiment of the invention will now be described briefly, which comprises the steps of: 
     1-1) Growing a sacrificial silicon oxide layer and depositing a silicon nitride layer on a silicon substrate sequentially; 
     1-2) Performing a photolithography process and an etching process on an active region to form a shallow trench isolation region; 
     1-3) Depositing an isolation dielectric layer, removing the sacrificial silicon oxide layer and the silicon nitride layer, so as to open a window for a region of the floating gate structure; 
     1-4) Growing or depositing a tunneling oxide layer, and then depositing a polysilicon layer for a floating gate and a germanium-silicon layer sequentially; 
     1-5) Depositing a top polysilicon layer for the floating gate and performing an etching back process to form a polysilicon hard mask; 
     1-6) Etching the germanium-silicon layer by taking the polysilicon hard mask as a hard mask, and stopping the etching at the bottom polysilicon layer of the floating gate structure; 
     1-7) Depositing a polysilicon layer such that the top polysilicon layer of the floating gate structure and the bottom polysilicon layer of the floating gate structure are connected with each other; 
     1-8) Performing a chemical mechanical polishing (CMP) to the top polysilicon layer, and stopping the polishing at the oxide layer of the isolation region; 
     1-9) Etching back the oxide layer of the shallow trench isolation region to laterally expose the germanium-silicon layer deposited in the step 4; 
     1-10) Removing the germanium-silicon layer via a wet etching process, and depositing a blocking oxide layer; 
     1-11) Depositing a control gate polysilicon, so as to forming an   floating gate structure surrounded by the control gate polysilicon; 
     1-12) After forming the floating gate structure of the invention, subsequent processes for fabricating the flash memory cell are the same as traditional flash memory processes. 
     In comparison with the prior art, the embodiment of the invention has the following beneficial effects. By ways of designing the floating gate structure, a contact area between the floating gate and the control gate in the cell is increased and a coupling ratio between adjacent cell is decreased at the same time. Therefor, a gate coupling ratio of the flash memory device can be improved under the same device size, so that an operating voltage of the flash memory device can be lowered, a crosstalk can be reduced and a reliability can be improved. Moreover, when a size of the flash memory device is reduced drastically, the coupling ratio can be maintained and a performance of the flash memory device is guaranteed. Meanwhile, the   floating gate structure provided in the embodiment of the invention may also employ a dielectric material having a high dielectric constant, thereby further increasing the coupling ratio of the flash memory device. 
     Therefore, in comparison with the prior art, by a technical solution provided according to the embodiment of the invention, the coupling ratio of the flash memory device can be effectively increased under the same size, thereby lowering the operating voltage and improving the reliability thereof. Moreover, the technology may also be compatible with a technology in which a dielectric material having a high dielectric constant is employed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a general floating gate flash memory cell and a floating gate structure thereof, in which: reference sign “ 01 ” represents a floating gate, reference sign “ 02 ” represents a tunneling oxide layer, reference sign “ 03 ” represents a substrate, reference sign “ 04 ” represents a shallow trench isolation region. 
         FIG. 2  is a schematic diagram of a floating gate structure according to the invention, in which: 
       reference sign “ 01 ” represents a floating gate, reference sign “ 02 ” represents a tunneling oxide layer, reference sign “ 03 ” represents a substrate, reference sign “ 04 ” represents a shallow trench isolation region. 
         FIG. 3  shows main process steps for fabricating a floating gate structure of the invention, in which: 
         FIG. 3   a  shows a window of a region of the floating gate structure and the tunneling oxide layer on a surface of an active region, in which: 
       reference sign “ 001 ” represents an oxide layer in the isolation region, reference sign “ 002 ” represents the tunneling oxide layer, reference sign “ 003 ” represents the substrate; 
         FIG. 3   b  represents a step of depositing a bottom polysilicon layer of a floating gate and a germanium-silicon layer sequentially, in which: 
       reference sign “ 001 ” represents the oxide layer in the isolation region, reference sign “ 004 ” represents the germanium-silicon layer, reference sign “ 005 ” represents the bottom polysilicon layer, reference sign “ 002 ” represents the tunneling oxide layer, reference sign  20 . “ 003 ” represents the substrate; 
         FIG. 3   c  shows a step of depositing a top polysilicon layer and performing an etching back process to form a polysilicon hard mask, in which: 
       reference sign “ 006 ” represents the polysilicon hard mask, reference sign “ 004 ” represents the germanium-silicon layer, reference sign “ 005 ” represents the bottom polysilicon layer, reference sign “ 001 ” represents the oxide layer in the isolation region, reference sign “ 002 ” represents the tunneling oxide layer, reference sign “ 003 ” represents the substrate; 
         FIG. 3   d  shows a step of etching the germanium-silicon material by taking the polysilicon hard mask as a hard mask, and stopping the etching at the bottom polysilicon layer of the floating gate, in which: 
       reference sign “ 006 ” represents the polysilicon hard mask, reference sign “ 004 ” represents the germanium-silicon layer, reference sign “ 005 ” represents the bottom polysilicon layer, reference sign “ 001 ” represents the oxide layer of the isolation region, reference sign “ 002 ” represents the tunneling oxide layer, reference sign “ 003 ” represents the substrate; 
         FIG. 3   e  shows a step of depositing a polysilicon such that the top polysilicon layer of the floating gate and the bottom polysilicon layer of the floating gate are connected with each other, in which: 
       reference sign “ 007 ” represents the top polysilicon layer, reference sign “ 004 ” represents the germanium-silicon material, reference sign “ 001 ” represents the oxide layer of the isolation region, reference sign “ 003 ” represents the substrate, reference sign “ 002 ” represents the tunneling oxide layer; 
         FIG. 3   f  shows a step of performing a chemical mechanical polishing (CMP) process on the top polysilicon layer and stopping the polishing at the oxide layer of the isolation region, in which: 
       reference sign “ 008 ” represents a   polysilicon floating gate, reference sign “ 004 ” represents the germanium-silicon layer, reference sign “ 001 ” represents the oxide layer of the isolation region, reference sign “ 003 ” represents the substrate, reference sign “ 002 ” represents the tunneling oxide layer. 
         FIG. 3   g  shows a step of etching back the oxide layer of the shallow trench isolation region and exposing the germanium-silicon layer deposited in the step 4 laterally, in which: 
       reference sign “ 008 ” represents the   polysilicon floating gate, reference sign “ 004 ” represents the germanium-silicon layer, reference sign “ 001 ” represents the oxide layer of the isolation region, reference sign “ 003 ” represents the substrate, reference sign “ 002 ” represents the tunneling oxide layer; 
         FIG. 3   h  shows a step of removing the germanium-silicon layer via a wet etching process to form the   floating gate structure, in which: 
       reference sign “ 008 ” represents the   polysilicon floating gate, reference sign “ 001 ” represents the oxide layer of the isolation region, reference sign “ 003 ” represents the substrate, reference sign “ 002 ” represents the tunneling oxide layer; and 
         FIG. 3   i  shows a step of depositing a blocking oxide layer and a polysilicon control gate to form a device having the floating gate, wherein: 
       reference sign “ 009 ” represents the polysilicon control gate, reference sign “ 010 ” represents the blocking oxide layer, reference sign “ 001 ” represents the oxide layer of the isolation region, reference sign “ 008 ” represents the   floating gate, reference sign “ 002 ” represents the tunneling oxide layer. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The invention will now be described in detail in conjunction with the drawings. In the detailed description of the embodiments of the invention, for a convenience of illustration, cross-sectional views representing a device structure will be exaggerated partially and not to scale. Moreover, schematic diagrams are examples only, without limiting a protection scope of the invention. Furthermore, practical manufacturing should relate to three-dimensional sizes including length, width and depth. 
     In one embodiment of the invention, a cross section of a floating gate of a traditional flash memory device along a lateral direction of a channel is modified from a square shape to a  , which may effectively improve a coupling ratio of the flash memory, thereby lowering an operating voltage and improving a reliability. In the floating gate according to the invention, a height of a middle part of the   occupies 40%-80% of a height of the entire floating gate, and a width of the middle part occupies 5%-30% of a width of the entire floating gate. 
     Based on the above, one embodiment of the invention puts forward a novel process method of a floating gate structure, which may be realized by adding several process steps during a manufacturing of a floating gate according to a standard process flow. The process method for suppressing a programming interference of a flash memory provided in the embodiment of the invention is as shown in  FIG. 3 . 
     The process method of the novel floating gate structure according to one embodiment of the invention will now be illustrated in detail in conjunction with  FIG. 3 . 
     1) First of all, a window (with a width of 65 nm) for a region of the floating gate structure and a tunneling oxide layer (with a thickness of 10 nm) on a surface of an active region are manufactured via the standard process flow of the flash memory, as shown in  FIG. 3   a.    
     2) After a gate oxide of the active region is formed in the standard process flow, the floating gate is manufactured according to the process method provided in the embodiment of the invention. 
     I) A bottom polysilicon layer for a floating gate (with a thickness of 20 nm) and a germanium-silicon material (with a thickness of 160 nm) are deposited sequentially, as shown in  FIG. 3   b.    
     II) A top polysilicon layer (with a thickness of 25 nm) is deposited and etched back to form a polysilicon hard mask, as shown in  FIG. 3   c.    
     III) The germanium-silicon material is etched by taking the polysilicon hard mask as a hard mask, and the etching is stopped at the bottom polysilicon layer for the floating gate, as shown in  FIG. 3   d.    
     IV) A polysilicon layer is deposited such that the top polysilicon layer of the floating gate and the bottom polysilicon of the floating gate are connected with each other, as shown in  FIG. 3   e.    
     V) A chemical mechanical polishing (CMP) is performed on the top polysilicon layer, and the polishing is stopped at the oxide layer of the isolation region, as shown in  FIG. 3   f.    
     VI) The oxide layer of the shallow trench isolation region is etched back so as to laterally expose the germanium-silicon layer deposited in the step 4, as shown in  FIG. 3   g.    
     VII) The germanium-silicon layer is removed via a wet etching process to form the     floating gate structure, as shown in  FIG. 3   h.    
     VIII) A blocking oxide layer (with a thickness of an equivalent oxide layer of 14 nm) and a polysilicon control gate (with a thickness of 200 nm) are deposited to form a device of the floating gate, as shown in  FIG. 3   i.    
     3) Thereafter, following standard processes of the flash memory are performed. 
     The above-described embodiment is not intended to limit the invention. Additional variations and modifications may be made by those skilled in the art without departing from the spirit or scope of the invention. Therefore, a protection scope of the invention is as defined by the appended claims.