Patent Publication Number: US-11031069-B2

Title: Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of U.S. patent application Ser. No. 14/518,670, filed Oct. 20, 2014, now U.S. Pat. No. 10,418,091, which is a continuation application of U.S. patent application Ser. No. 12/573,203, filed Oct. 5, 2009, now U.S. Pat. No. 8,873,283, which is a divisional application of U.S. patent application Ser. No. 11/509,188, filed Aug. 24, 2006, now U.S. Pat. No. 7,606,066, which claims priority to: (1) U.S. Provisional Patent Application No. 60/714,917, filed Sep. 7, 2005; (2) U.S. Provisional Patent Application No. 60/722,139, filed Sep. 30, 2005; (3) U.S. Provisional Patent Application No. 60/728,061, filed Oct. 19, 2005; (4) U.S. Provisional Patent Application No. 60/749,385, filed Dec. 12, 2005; and (5) U.S. Provisional Patent Application No. 60/774,275, filed Feb. 16, 2006, each of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The inventions relate to a semiconductor memory cell, array, architecture and device, and techniques for controlling and/or operating such cell, array and device; and more particularly, in one aspect, to a dynamic random access memory (“DRAM”) cell, array, architecture and device, wherein the memory cell includes an electrically floating body wherein an electrical charge is stored therein. 
     There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Semiconductor-on-Insulator (SOI) is a material in which such devices may be fabricated or disposed on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET. 
     One type of dynamic random access memory cell is based on, among other things, the electrically floating body effect of SOI transistors. (See, for example, U.S. Pat. No. 6,969,662). In this regard, the dynamic random access memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation layer (or non-conductive region, for example, in a bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor. 
     With reference to  FIGS. 1A, 1B and 1C , in one embodiment, semiconductor DRAM array  10  includes a plurality of memory cells  12  each consisting of transistor  14  having gate  16 , body region  18 , which is electrically floating, source region  20  and drain region  22 . The body region  18  is disposed between source region  20  and drain region  22 . Moreover, body region  18  is disposed on or above region  24 , which may be an insulation region (for example, in an SOI material/substrate) or non-conductive region (for example, in a bulk-type material/substrate). The insulation or non-conductive region  24  may be disposed on substrate  26 . 
     Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s)  28 , a selected source line(s)  30  and/or a selected bit line(s)  32 . In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region  18  wherein the data states are defined by the amount of carriers within electrically floating body region  18 . Notably, the entire contents of the &#39;662 patent, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein. 
     The memory cell  12  of DRAM array  10  operates by accumulating in or emitting/ejecting majority carriers (electrons or holes)  34  from body region  18 . (See, for example, the N-channel transistor in  FIGS. 2A and 2B ). In this regard, conventional write techniques may accumulate majority carriers (in this example, “holes”)  34  in body region  18  of memory cells  12  by, for example, impact ionization near source region  20  and/or drain region  22 . (See,  FIG. 2A ). The majority carriers  30  may be emitted or ejected from body region  18  by, for example, forward biasing the source/body junction and/or the drain/body junction. (See,  FIG. 2B ). 
     Notably, for at least the purposes of this discussion, logic high or logic “1” corresponds to, for example, an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic low or logic “0”. In contrast, logic low or logic “0” corresponds to, for example, a reduced concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or logic “1”. 
     In one conventional technique, the memory cell is read by applying a small bias to the drain of the transistor as well as a gate bias which is above the threshold voltage of the transistor. In this regard, in the context of memory cells employing N-type transistors, a positive voltage is applied to one or more word lines  28  to enable the reading of the memory cells associated with such word lines. The amount of drain current is determined/affected by the charge stored in the electrically floating body region of the transistor. As such, conventional reading techniques sense the amount of the channel current provided/generated in response to the application of a predetermined voltage on the gate of the transistor of the memory cell to determine the state of the memory cell; a floating body memory cell may have two or more different current states corresponding to two or more different logical states (for example, two different current conditions/states corresponding to the two different logical states: “1” and “0”). 
     In sum, conventional writing programming techniques for memory cells having an N-channel type transistor often provide an excess of majority carriers by channel impact ionization (see,  FIG. 3A ) or by band-to-band tunneling (gate-induced drain leakage “GIDL”) (see,  FIG. 3B ). The majority carrier may be removed via drain side hole removal (see,  FIG. 4A ), source side hole removal (see,  FIG. 4B ), or drain and source hole removal, for example, using the back gate pulsing (see,  FIG. 4C ). 
     Notably, conventional programming/reading techniques often lead to relatively large power consumption (due to, for example, high writing “0” current) and relatively small memory programming window. The present inventions, in one aspect, are directed to a combination of the programming/reading methods which allows relatively low power memory programming and provides a relatively larger memory programming window (e.g., both relative to at least the conventional programming techniques). This new approach may also provide a floating body memory cell that may be less sensitive to the technology variations and may include improved retention characteristics. 
     SUMMARY OF THE INVENTIONS 
     There are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein. 
     In one aspect, the present inventions are directed to an integrated circuit device (for example, a logic or discrete memory device) including a memory cell including an electrically floating body transistor (for example, an N-channel type transistor or a P-channel type transistor). The electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. The integrated circuit device further includes data write circuitry, coupled to the memory cell, to apply (i) first write control signals to the memory cell to write the first data state therein and (ii) second write control signals to the memory cell to write the second data state therein, wherein, in response to first write control signals applied to the memory cell, the electrically floating body transistor generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor. In this regard, the first write control signals cause, provide, produce and/or induce the first bipolar transistor current. 
     In one embodiment, the first write control signals include a signal applied to the gate and a signal applied to the source region wherein the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude. In another embodiment, the first write control signals include a signal applied to the gate and a signal applied to the drain region wherein the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude. 
     In yet another embodiment, the first write control signals include a signal applied to the gate and a signal applied to the source region to cause, provide, produce and/or induce the first bipolar transistor current. In this embodiment, the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude and the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude. 
     The first write control signals, in another embodiment, include a signal applied to the gate and a signal applied to the drain region, wherein (i) the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude and (ii) the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude. 
     In other embodiments, the first write control signals include a signal applied to the gate and a signal applied to the drain region wherein, in response to the first bipolar transistor current, majority carriers are generated in the electrically floating body region. In this embodiment, signal applied to the gate may temporally change relative to the signal applied to the drain region to cause, provide, produce and/or induce the majority carriers to accumulate in a portion of the electrically floating body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the electrically floating body region. Indeed, the signal applied to the gate may change or terminate before the signal applied to the drain region. 
     In certain embodiments, the second write control signals include a signal applied to the gate, a signal applied to the source region, and a signal applied to the drain region. The signal applied to the drain region may include a blocking voltage to prevent the first data state from being written into the electrically floating body transistor. 
     The integrated circuit device may further include data sense circuitry, coupled to the memory cell, to sense the data state of the memory cell. In response to read control signals applied to the memory cell, the electrically floating body transistor may generate a second bipolar transistor current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second bipolar transistor current. In one embodiment, the second bipolar transistor current is representative of the first data state. 
     The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. The signal applied to the drain region may include a positive voltage pulse or a negative voltage pulse. Indeed, one or more of the read control signals may include a constant or unchanging voltage amplitude (for example, ground). 
     In another aspect, the present inventions are directed to an integrated circuit device (for example, a logic or discrete memory device) comprising a memory cell array including a plurality of word lines, plurality of source lines, plurality of bit lines, and plurality of memory cells arranged in a matrix of rows and columns. Each memory cell includes an electrically floating body transistor (for example, an N-channel type transistor or a P-channel type transistor), wherein the electrically floating body transistor includes a source region coupled to an associated source line, a drain region, a body region disposed between the source region and the drain region coupled to an associated bit line, wherein the body region is electrically floating, and a gate disposed over the body region and coupled to an associated word line. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. 
     In this aspect of the inventions, the source region of the electrically floating body transistor of each memory cell of a first row of memory cells is connected to a first source line. 
     The integrated circuit device of this aspect of the inventions further includes data write circuitry, coupled to the first row of memory cells, to apply (i) first write control signals to the memory cells to write the first data state therein and (ii) second write control signals to the memory cells to write the second data state therein. In response to first write control signals applied to at least a portion of the memory cells of the first row of memory cells, the electrically floating body transistor of each such memory cell of the first row generates a first bipolar transistor current which at least substantially provides the first charge in the body region of the electrically floating body transistor of the each such memory cells. 
     In one embodiment, the source region of the electrically floating body transistor of each memory cell of a second row of memory cells is connected to the first source line. In another embodiment, the source region of the electrically floating body transistor of each memory cell of a second row of memory cells is connected to a second source line, and the source region of the electrically floating body transistor of each memory cell of a third row of memory cells is connected to a second source line. In this embodiment, the second and third rows of memory cells are adjacent to the first row of memory cells. 
     In another embodiment, the first write control signals cause, provide, produce and/or induce the first bipolar transistor current. The first write control signals may include a signal applied to the gate which includes a first voltage having a first amplitude and a second voltage having a second amplitude. The write control signals may include a signal applied to the source region which includes a first voltage having a first amplitude and a second voltage having a second amplitude. Moreover, the first write control signal includes a signal applied to the drain region which includes a first voltage having a first amplitude and a second voltage having a second amplitude. 
     In certain embodiments, the data write circuitry, prior to applying the first write control signals, applies the second write control signals to all of all of the memory cells of the first row of memory cells to write the second data state therein. In certain other embodiments, the data write circuitry at least substantially simultaneously applies (i) the first write control signals to the portion of the memory cells of the first row of memory cells to write the first data state therein, and (ii) the second write control signals to the other portion of the memory cells of the first row of memory cells to write the second data state therein. 
     In one embodiment, the first write control signals may include a signal applied to the gate and a signal applied to the source region of the electrically floating body transistors of a one or more memory cells of the first row of memory cells to cause, provide, produce and/or induce the first bipolar transistor current, wherein (i) the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude, and (ii) the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude. In another embodiment, the first write control signals include a signal applied to the gate and a signal applied to the drain region of the electrically floating body transistors of a one or more memory cells of the first row of memory cells to cause, provide, produce and/or induce the first bipolar transistor current, wherein (i) the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude, and (ii) the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude. In a preferred embodiment, the signal having the fourth voltage is applied to the gate before the signal having the second voltage is applied to the drain. 
     The integrated circuit device of this aspect of the present inventions may further include data sense circuitry, coupled to each memory cell of the plurality of memory cells, to sense the data state of the memory cell. In response to read control signals applied to the memory cells, the electrically floating body transistor of each memory cell generates a second bipolar transistor current which is representative of the data state of the memory cell. The data sense circuitry determines the data state of the memory cell substantially based on the second bipolar transistor current. In one embodiment, the second bipolar transistor current is representative of the first data state. 
     The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. The signal applied to the drain region may include a positive voltage pulse or a negative voltage pulse. Indeed, one or more of the read control signals may include a constant or unchanging voltage amplitude (for example, ground). 
     In yet another aspect, the present inventions are directed to an integrated circuit device (for example, a logic or discrete memory device) including a memory cell consisting essentially of an electrically floating body transistor (for example, an N-channel type transistor or a P-channel type transistor). The electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. The integrated circuit device further includes data write circuitry, coupled to the memory cell, to apply (i) first write control signals to the memory cell to write the first data state therein and (ii) second write control signals to the memory cell to write the second data state therein, wherein, in response to first write control signals applied to the memory cell, the electrically floating body transistor generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor. In this regard, the first write control signals cause, provide, produce and/or induce the first bipolar transistor current. 
     The first write control signals may include a signal applied to the gate and a signal applied to the source region wherein the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude. Alternatively, the first write control signals include a signal applied to the gate and a signal applied to the drain region wherein the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude. 
     The first write control signals may include a signal applied to the gate and a signal applied to the source region to cause, provide, produce and/or induce the first bipolar transistor current. In this embodiment, the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude. In addition, the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude. 
     The first write control signals, in one embodiment, include a signal applied to the gate and a signal applied to the drain region, wherein (i) the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude and (ii) the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude. 
     In other embodiments, the first write control signals include a signal applied to the gate and a signal applied to the drain region wherein, in response to the first bipolar transistor current, majority carriers are generated in the electrically floating body region. In this embodiment, signal applied to the gate may temporally change relative to the signal applied to the drain region to cause, provide, produce and/or induce the majority carriers to accumulate in a portion of the electrically floating body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the electrically floating body region. Indeed, the signal applied to the gate may change or terminate before the signal applied to the drain region. 
     In certain embodiments, the second write control signals include a signal applied to the gate, a signal applied to the source region, and a signal applied to the drain region. The signal applied to the drain region may include a blocking voltage to prevent the first data state from being written into the electrically floating body transistor. 
     The integrated circuit device may further include data sense circuitry, coupled to the memory cell, to sense the data state of the memory cell. In response to read control signals applied to the memory cell, the electrically floating body transistor may generate a second bipolar transistor current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second bipolar transistor current. In one embodiment, the second bipolar transistor current is representative of the first data state. 
     The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. The signal applied to the drain region may include a positive voltage pulse or a negative voltage pulse. Indeed, one or more of the read control signals may include a constant or unchanging voltage amplitude (for example, ground). 
     Again, there are many inventions, and aspects of the inventions, described and illustrated herein. This Summary of the Inventions is not exhaustive of the scope of the present inventions. Moreover, this Summary of the Inventions is not intended to be limiting of the inventions and should not be interpreted in that manner. While certain embodiments have been described and/or outlined in this Summary of the Inventions, it should be understood that the present inventions are not limited to such embodiments, description and/or outline, nor are the claims limited in such a manner. Indeed, many other embodiments, which may be different from and/or similar to, the embodiments presented in this Summary, will be apparent from the description, illustrations and claims, which follow. In addition, although various features, attributes and advantages have been described in this Summary of the Inventions and/or are apparent in light thereof, it should be understood that such features, attributes and advantages are not required whether in one, some or all of the embodiments of the present inventions and, indeed, need not be present in any of the embodiments of the present inventions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present inventions and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those shown, are contemplated and are within the scope of the present inventions. 
       Moreover, there are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein. 
         FIG. 1A  is a schematic representation of a prior art DRAM array including a plurality of memory cells comprised of one electrically floating body transistor; 
         FIG. 1B  is a three-dimensional view of an exemplary prior art memory cell comprised of one electrically floating body partially depleted transistor (PD-SOI NMOS); 
         FIG. 1C  is a cross-sectional view of the prior art memory cell of  FIG. 1B , cross-sectioned along line C-C′; 
         FIGS. 2A and 2B  are exemplary schematic illustrations of the charge relationship, for a given data state, of the floating body, source and drain regions of a prior art memory cell comprised of one electrically floating body transistor (PD-SOI NMOS); 
         FIGS. 3A and 3B  are exemplary schematic and general illustrations of conventional methods to program a memory cell to logic state “1” (i.e., generate or provide an excess of majority carrier in the electrically floating body of the transistor (an N-type channel transistor in this exemplary embodiment) of the memory cell of  FIG. 1B ; majority carriers in these exemplary embodiments are generated or provided by the channel electron impact ionization ( FIG. 3A ) and by GIDL or band to band tunneling ( FIG. 3B ); 
         FIGS. 4A-4C  are exemplary schematics and general illustrations of conventional methods to program a memory cell to logic state “0” (i.e., provide relatively fewer majority carrier by removing majority carriers from the electrically floating body of the transistor of the memory cell of  FIG. 1B ; majority carriers may be removed through the drain region/terminal of the transistor ( FIG. 4A ), the source region/terminal of the transistor ( FIG. 4B ), and through both drain and source regions/terminals of the transistor via using the back gate pulses applied to the substrate/backside terminal of the transistor of the memory cell ( FIG. 4C ); 
         FIG. 5  illustrates an exemplary schematic (and control signal) of a conventional reading technique, the state of the memory cell may be determined by sensing the amount of the channel current provided/generated by the transistor of the memory cell in response to the application of a predetermined voltage on the gate of the transistor; 
         FIG. 6A  is a schematic representation of an equivalent electrically floating body memory cell (N-channel type) including an intrinsic bipolar transistor in addition to the MOS transistor; 
         FIG. 6B  is a schematic representation (and control signal voltage relationship) of an exemplary embodiment of an aspect of the present inventions of programming a memory cell to logic state “1” by generating, storing and/or providing an excess of majority carriers in the electrically floating body of the transistor of the memory cell in accordance with certain aspects and/or embodiments of the present inventions; 
         FIG. 6C  illustrates three exemplary relationships of selected control signals to program or write logic state “1” into a memory cell in accordance with certain aspects and/or embodiments of the present inventions; notably, in this illustration the gate and drain control signal sequences are illustrated whereby the control signal applied to the drain region may be applied before the signal is applied to the gate of the transistor (Case A), simultaneously (Case B), or after the control signal is applied to the gate (Case C); 
         FIG. 7  illustrates an exemplary schematic (and control signal) of an exemplary embodiment of an aspect of the present inventions of programming a memory cell to logic state “0” by generating, storing and/or providing relatively fewer majority carriers (as compared to the number of majority carriers in the electrically floating body of the memory cell that is programmed to logic state “1”) in the electrically floating body region of the transistor of the memory cell, wherein the majority carrier are removed (write “0”) through both drain and source regions/terminals by applying a control signal (for example, a programming pulse) to the gate of the transistor of the memory cell; 
         FIG. 8  illustrates an exemplary schematic (and control signal) of an exemplary embodiment of an aspect of the present inventions of holding or maintaining the data state of a memory cell when programming, for example, a neighboring memory cell to a predetermined data state (for example, logic state “1” and/or logic state “0”); 
         FIG. 9  is a graphical representation of the exemplary retention time distribution of a memory cell implementing one or more aspect of the present inventions; 
         FIG. 10  illustrates an exemplary schematic (and control signal) of an exemplary embodiment of an aspect of the present inventions of reading the data state of a memory cell by sensing the amount of the current provided/generated in response to the application of a predetermined voltage on the gate of the transistor of the memory cell; 
         FIG. 11  illustrates an exemplary distribution of logic state “1” and state “0” of a memory cell implementing one or more aspect of the present inventions; 
         FIGS. 12A and 12B  are schematic block diagrams of embodiments of an integrated circuit device including, among other things, a memory cell array, data sense and write circuitry, memory cell selection and control circuitry, according certain aspects of the present inventions; 
         FIGS. 13, 14A, 14B, and 15  illustrate an embodiment of an exemplary memory array having a plurality of memory cells and employing a separate source line configuration for each row of memory cells, according to certain aspects of the present inventions; 
         FIG. 16  illustrates exemplary relationships of selected write control signals to implement a program or write operation for logic high or logic “1” into a memory cell according to one embodiment of the present inventions; 
         FIG. 17  illustrates exemplary relationships of selected write control signals to implement a program or write operation for logic low or logic “0” into a memory cell according to one embodiment of the present inventions; 
         FIG. 18  illustrates exemplary relationships of selected control signals to implement a read operation of a memory cell according to one embodiment of the present inventions; 
         FIGS. 19, 21, 22, 23, 24, 25 and 26  illustrate exemplary relationships of selected control signals to control or implement certain operations of the memory cells of associated memory array configurations or layouts illustrated herein, according to certain aspects of the present inventions; 
         FIGS. 20 and 27  illustrate exemplary embodiments of memory arrays having a plurality of memory cells and employing separate or common source line configurations for each row of memory cells, according to certain aspects of the present inventions; and 
         FIG. 28  illustrates a quasi non-destructive reading technique according to one embodiment of the present inventions; 
         FIG. 29  illustrates exemplary timing relationships of selected write control signals to (i) program or write logic “0” into one or more N-channel type memory cells, (ii) program or write logic “1” into one or more N-channel type memory cells, and (iii) read one or more N-channel type memory cells according to one embodiment of the present inventions; 
         FIG. 30  illustrates an exemplary embodiment of a memory array having a plurality of memory cells (including N-channel type transistors) and employing a common source line configuration for each row of memory cells, according to certain aspects of the present inventions; 
         FIG. 31  illustrates an exemplary embodiment of a memory array having a plurality of memory cells (including P-channel type transistors) and employing a common source line configuration for each row of memory cells, according to certain aspects of the present inventions; 
         FIG. 32  illustrates exemplary timing relationships of selected write control signals to (i) program or write logic “0” into one or more P-channel type memory cells, (ii) program or write logic “1” into one or more P-channel type memory cells, and (iii) read one or more P-channel type memory cells according to one embodiment of the present inventions; 
         FIG. 33  illustrates an exemplary schematic (and control signals) of an FD transistor employed as a floating body memory cell, according to an aspect of the present inventions; notably, back gate bias is not required (although it may be employed); 
         FIGS. 34 and 35  illustrate exemplary schematic (and control signals) of a double-gate and triple-gate transistor, respectively, employed as a floating body memory cell, according to aspects of the present inventions; and 
         FIG. 36  illustrates an exemplary semiconductor cell (and control signals) that may be used as a floating memory cell according to the present inventions; as before, a back gate bias is not required (although it may be employed) and additional technology/fabrication processes are also not required (although such processing may be implemented); and 
         FIG. 37  illustrates exemplary relationships of selected control signals to control or implement certain operations of the memory cells of associated memory array configurations or layouts illustrated herein, according to certain aspects of the present inventions. 
     
    
    
     DETAILED DESCRIPTION 
     At the outset, it should be noted that there are many inventions described herein as well as many aspects and embodiments of those inventions. In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ intrinsic bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ the intrinsic bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell. 
     The present inventions, in addition thereto or in lieu thereof, may employ band-to-band tunneling to write a data state in the electrically floating body memory cell and an intrinsic bipolar transistor current generated by the electrically floating body transistor to read and/or determine the data state of the memory cell. In this embodiment, however, during the read operation, the data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     The present inventions are also directed to semiconductor memory cell, array, circuitry and device to implement such control and operation techniques. Notably, the memory cell and/or memory cell array may comprise a portion of an integrated circuit device, for example, logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory). 
     With reference to  FIG. 6A , in one embodiment, electrically floating body transistor  14  may be schematically illustrated as including a MOS transistor “component” and an intrinsic bipolar transistor “component”. In one aspect, the present inventions employ the intrinsic bipolar transistor “component” to program/write as well as read memory cell  12 . In this regard, the intrinsic bipolar transistor generates and/or produces a bipolar transistor current which is employed to program/write the data state in memory cell  12  and read the data state of memory cell  12 . Notably, in this exemplary embodiment, electrically floating body transistor  14  is an N-channel device. As such, majority carriers  34  are “holes”. 
     With reference to  FIGS. 6A-6C , in operation, when writing or programming logic “1”, in one embodiment, control signals having predetermined voltages (for example, Vg=0v, Vs=0v, and Vd=3v) are applied to gate  16 , source region  20  and drain region  22  (respectively) of transistor  14  of memory cell  12 . Such control signals generate or provide a bipolar current in electrically floating body region  18  of transistor  14 . The bipolar current causes or produces impact ionization and/or the avalanche multiplication phenomenon in electrically floating body region  18 . In this way, an excess of majority carriers is produced, provided and/or generated in electrically floating body region  18  of transistor  14  of memory cell  12 . Thus, in this embodiment, the predetermined voltages of the control signals program or write logic “1” in memory cell  12  via impact ionization and/or avalanche multiplication in electrically floating body region  18 , caused or produced by a bipolar current in body region  18  of transistor  14  of memory cell  12 . 
     Notably, it is preferred that the bipolar transistor current responsible for impact ionization and/or avalanche multiplication in electrically floating body region  18  is initiated or induced by the control signal applied to gate  16  of transistor  14 . Such a control signal may induce channel impact ionization which raises or increases the potential of body region  18  and “turns on”, produces, causes and/or induces a bipolar current in transistor  14 . One advantage of the proposed writing/programming technique is that a large amount of the excess majority carriers may be generated and stored in electrically floating body region  18  of transistor  14 . 
     With reference to  FIG. 6C , the control signal applied to drain region  22  of transistor  14  may be applied before the control signal is applied to the gate, simultaneously thereto, or after the control signal is applied to the gate (Cases A, B, C, respectively). From a relative timing perspective, it is preferred that the control signal applied to drain region  22  temporally extends beyond or continues after the control signal which is applied to gate  16  ceases. (See, for example, Case C of  FIG. 6C ). In this way, majority carriers  34  are generated in electrically floating body region  18  via the bipolar current, and majority carriers  34  may accumulate (and be stored) in a portion of electrically floating body region  18  of the transistor of memory cell(s)  12  that is juxtaposed or near gate dielectric  32  (which is disposed between gate  16  and electrically floating body region  18 ). 
     In another embodiment for programming or writing logic “1” into memory cell  12 , the control signals having predetermined voltages (for example, Vg=−3v, Vs=−0.5v and Vd=1v) are applied to gate  16  and source region  20  and drain region  22  (respectively) to initiate or induce band-to-band tunneling. In this way, an excess of majority carriers are generated and stored in electrically floating body region  18  of transistor  14 . 
     With reference to  FIG. 7 , in one exemplary embodiment, memory cell  12  may be programmed to logic “0” by applying control signals having predetermined voltages to gate  16 , source region  20  and drain region  22  (for example, Vg=1.5v, Vs=0v and Vd=0v, respectively). In response, majority carriers may be removed from electrically floating body region  18  of transistor  14 . In one embodiment, the majority carriers are removed, eliminated or ejected from body region  18  through source region  20  and drain region  22 . (See,  FIG. 7 ). In another embodiment, the majority carriers may be removed, eliminated or ejected from body region  18  substantially through source region  20  or drain region  22 . 
     The transistor  14  of memory cell  12  may be programmed to logic “0” by applying control signals, having predetermined voltages, to gate  16 , source region  20  and drain region  22  of transistor  14  (for example, Vg=0v, Vs=−0.4v and Vd=−1.5v, respectively). In this embodiment, it is preferred that the gate-to-source voltage is below the threshold voltage of transistor  14 . In this way, the power consumption during “0” writing may be even further reduced. 
     Notably, the control signal applied to gate  16  to write or program logic “0” is different from and, in at least one embodiment, higher than a holding voltage (discussed below) that may be applied to the gates of transistors  14  of other memory cells  12  (for example, other memory cells in a memory cell array). In this way, the impact of the write operation on the other memory cells is minimized and/or reduced. 
     The illustrated/exemplary voltage levels to implement the write operations are merely exemplary. The control signals increase the potential of electrically floating body region  18  which “turns on”, produces, causes and/or induces a bipolar current in the transistor of the memory cell. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a read operation, the data state may be determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     Accordingly, the voltage levels to implement the write operations are merely exemplary. Indeed, the indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative. 
     Notably, the inventive programming technique may consume less power relative to conventional techniques of  FIGS. 4A and 4B . In this regard, the current for writing or programming to logic “0” is smaller when compared to such conventional techniques. Moreover, the programming techniques of the present inventions may be implemented without employing a back gate terminal (Compare,  FIG. 4C ). 
     In one embodiment, the memory cell  12  may be implemented in a memory cell array. When a memory cell is implemented in a memory cell array configuration, it may be advantageous to implement a “holding” operation or condition to certain memory cells when programming one or more other memory cells of the array in order to improve or enhance the retention characteristics of such certain memory cells. In this regard, the transistor of the memory cell may be placed in a “holding” state via application of control signals (having predetermined voltages) which are applied to the gate and the source and drain regions of the transistor of the memory cells which are not involved in the write or read operations. 
     For example, with reference to  FIG. 8 , such control signals provide, cause and/or induce majority carrier accumulation in an area that is close to the interface between gate dielectric  32  and electrically floating body  18 . In this embodiment, it may be preferable to apply a negative voltage to gate  16  where transistor  14  is an N-channel type transistor  14 . The proposed holding condition may provide enhanced retention characteristics (See, for example,  FIG. 9 ). 
     With reference to  FIG. 10 , in one embodiment, the data state of memory cell  12  may be read and/or determined by applying control signals having predetermined voltages to gate  16  and source region  20  and drain region  22  of transistor  14  (for example, Vg=−0.5v, Vs=3v and Vd=0v, respectively). Such control signals, in combination, induce and/or cause a bipolar transistor current in memory cells  12  that are programmed to logic “1”. The bipolar transistor current may be considerably larger than a channel current. As such, sensing circuitry (for example, a cross-coupled sense amplifier), which is coupled to transistor  14  (for example, drain region  22 ) of memory cell  12 , senses the data state using primarily and/or based substantially on the bipolar transistor current. Notably, for those memory cells  12  that are programmed to logic “0”, such control signals induce, cause and/or produce little to no bipolar transistor current (for example, a considerable, substantial or sufficiently measurable bipolar transistor current). 
     The proposed reading technique may provide a larger signal (see,  FIG. 11 ) compared to the conventional method (see,  FIG. 5 ). Moreover, the reading technique may simplify the sensing of the signal read from transistor  14  of memory cell  12 . 
     In another embodiment, a read operation may be performed by applying 0 volts to source region  20  and gate  16  and a positive voltage (for example, +3.5 volts) to drain region  22 . Under these circumstances, a bipolar transistor current is produced between source region  20  and drain region  22 . The bipolar transistor current may be larger than a channel current. As such, sensing circuitry (for example, a cross-coupled sense amplifier), which is coupled to transistor  14  (for example, drain region  22 ) of memory cell  12 , senses the data state using primarily and/or based substantially on the bipolar transistor current. 
     Thus, in response to read control signals, electrically floating body transistor  14  generates a bipolar transistor current which is representative of the data state of memory cell  12 . Where the data state is logic high or logic “1”, electrically floating body transistor  14  provides a substantially greater bipolar transistor current than where the data state is logic low or logic “0”. Indeed, electrically floating body transistor  14  may provide little to no bipolar transistor current when the data state is logic low or logic “0”. As discussed in more detail below, data sensing circuitry determines the data state of the memory cell based substantially on the bipolar transistor current induced, caused and/or produced in response to the read control signals. 
     Notably, where electrically floating body transistor  14  is an P-channel type transistor, in operation, during the read operation, in one embodiment, 0 volts may be applied to source region  20  and gate  16  and a negative voltage (for example, −4 volts) may be applied to drain region  22 . Such control signals, in combination, induce and/or cause a bipolar transistor current which may be considerably larger than a channel current. Moreover, electrically floating body transistor  14  generates a bipolar transistor current which is representative of the data state of the memory cell. In this embodiment, where the data state is logic high or logic “1”, electrically floating body transistor  14  provides a substantially greater bipolar transistor current than where the data state is logic low or logic “0”. Indeed, electrically floating body transistor  14  may provide little to no bipolar transistor current when the data state is logic low or logic “0”. The sensing circuitry (for example, a cross-coupled sense amplifier), which is coupled to transistor  14  (for example, drain region  22 ) of memory cell  12 , senses the data state using primarily and/or based substantially on the bipolar transistor current. 
     As with other operations, the illustrated/exemplary voltage levels to implement the read operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative. 
     As mentioned above, the present inventions may be implemented in an integrated circuit device (for example, a discrete memory device or a device having embedded memory) including a memory array having a plurality of memory cells arranged in a plurality of rows and columns wherein each memory cell includes an electrically floating body transistor. The memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, data sense circuitry (for example, sense amplifiers or comparators), memory cell selection and control circuitry (for example, word line and/or source line drivers), as well as row and column address decoders) may include P-channel and/or N-channel type transistors. 
     For example, with reference to  FIGS. 12A and 12B , the integrated circuit device may include array  10 , having a plurality of memory cells  12 , data write and sense circuitry  36 , and memory cell selection and control circuitry  38 . The data write and sense circuitry  36  reads data from and writes data to selected memory cells  12 . In one embodiment, data write and sense circuitry  36  includes a plurality of data sense amplifiers. Each data sense amplifier receives at least one bit line  32  and an output of reference generator circuitry (for example, a current or voltage reference signal). In one embodiment, the data sense amplifier may be a cross-coupled type sense amplifier as described and illustrated in the Non-Provisional U.S. patent application Ser. No. 11/299,590 (U.S. Patent Application Publication US 2006/0126374), filed by Waller and Carman, on Dec. 12, 2005, and entitled “Sense Amplifier Circuitry and Architecture to Write Data into and/or Read Data from Memory Cells”, the application being incorporated herein by reference in its entirety) to sense the data state stored in memory cell  12  and/or write-back data into memory cell  12 . 
     The data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In the context of current sensing, a current sense amplifier may compare the current from the selected memory cell to a reference current, for example, the current of one or more reference cells. From that comparison, it may be determined whether memory cell  12  contained logic high (relatively more majority carries  34  contained within body region  18 ) or logic low data state (relatively less majority carries  28  contained within body region  18 ). Notably, the present inventions may employ any type or form of data write and sense circuitry  36  (including one or more sense amplifiers, using voltage or current sensing techniques, to sense the data state stored in memory cell  12 ) to read the data stored in memory cells  12  and/or write data in memory cells  12 . 
     Briefly, memory cell selection and control circuitry  38  selects and/or enables one or more predetermined memory cells  12  to facilitate reading data therefrom and/or writing data thereto by applying a control signal on one or more word lines  28 . The memory cell selection and control circuitry  38  may generate such control signals using address data, for example, row address data. Indeed, memory cell selection and control circuitry  38  may include a conventional word line decoder and/or driver. There are many different control/selection techniques (and circuitry therefor) to implement the memory cell selection technique. Such techniques, and circuitry therefor, are well known to those skilled in the art. Notably, all such control/selection techniques, and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present inventions. 
     The present inventions may be implemented in any architecture, layout, and/or configuration comprising memory cells having electrically floating body transistors. For example, in one embodiment, memory array  10  including a plurality of memory cells  12  having a separate source line for each row of memory cells (a row of memory cells includes a common word line connected to the gates of each memory cell of the row). (See, for example,  FIGS. 13-15 ). The memory array  10  may employ one or more of the exemplary programming, reading and/or holding techniques described above. 
     In one embodiment, the present inventions are implemented in conjunction with a two step write operation whereby all the memory cells of a given row are written to a predetermined data state by first executing a “clear” operation, whereby all of the memory cells of the given row are written or programmed to logic “0”, and thereafter selective memory cells of the row are selectively write operation to the predetermined data state (here logic “1”). The present inventions may also be implemented in conjunction with a one step write operation whereby selective memory cells of the selected row are selectively written or programmed to either logic “1” or logic “0” without first implementing a “clear” operation. 
     With reference to  FIGS. 13, 14A and 14B , memory cells  12  may be programmed using the two step operation wherein a given row of memory cells are written to a first predetermined data state by first executing a “clear” operation (which, in this exemplary embodiment, all of the memory cells of the given row are written or programmed to logic “0”) and thereafter selected memory cells are written to a second predetermined data state (i.e., a selective write operation to the second predetermined data state). The “clear” operation may be performed by writing or programming each memory cell of the given row to a first predetermined data state (in this exemplary embodiment the first predetermined data state is logic “0”) using the inventive technique described above. (See,  FIG. 7 ). 
     In particular, transistor of each memory cell  12  of a given row (for example, memory cells  12   a - 12   d ) is controlled to store a majority carrier concentration in the electrically floating body region of the transistor which corresponds to logic “0”. In this regard, control signals to implement a clear operation are applied to the gate, the source region and the drain region of the transistor of memory cells  12   a - 12   d . In one embodiment, a clear operation includes applying (i) 1.5v to the gate, (ii) 0v to the source region, and (iii) 0v to the drain region of the transistor. In response, the same logic state (for example, logic low or logic “0”) is stored in memory cells  12   a - 12   d  and the state of memory cells  12   a - 12   d  are “cleared”. Notably, it may be preferable to maintain the gate-to-source voltage below the threshold voltage of the transistor of memory cell  12  to further minimize or reduce power consumption. 
     Thereafter, selected memory cells of the given row may be programmed to the second predetermined logic state. In this regard, the transistors of certain memory cells of a given row are written to the second predetermined logic state in order to store the second predetermined logic state in memory cells. For example, with reference to  FIG. 14A , memory cells  12   b  and  12   c  are programmed to logic high or logic “1”, via impact ionization and/or avalanche multiplication, by applying (i) −2v to the gate (via word line  28   i ), (ii) −2v to the source region (via source line  30   i ), and (iii) 1.5v to the drain region (via bit line  32   j+1  and  32   j+2 ). In particular, such control signals generate or provide a bipolar current in the electrically floating body region of the transistor of memory cell  12 . The bipolar current causes or produces impact ionization and/or the avalanche multiplication phenomenon in the electrically floating body region of the transistors of memory cells  12   b  and  12   c . In this way, an excess of majority carriers are provided and stored in the electrically floating body region of the transistor of memory cells  12   b  and  12   c  which corresponds to logic high or logic “1”. 
     As mentioned above, it is preferred that the bipolar transistor current responsible for impact ionization and/or avalanche multiplication in the floating body is initiated or induced by the control signal (control pulse) applied to the gate of the transistor. Such a signal/pulse may induce the channel impact ionization which raises or increases the potential of the electrically floating body region of the transistor of memory cells  12   b  and  12   c  and “turns-on” and/or produces a bipolar current in transistor  14 . One advantage of the proposed method is that a large amount of the excess majority carriers may be generated and stored in the electrically floating body region of the transistor of memory cells  12   b  and  12   c.    
     Notably, in this exemplary embodiment, memory cells  12   a  and  12   d  are maintained at logic low (or logic “0”) by applying an inhibit control signal to the drain region of each memory cell  12   a  and  12   d . For example, applying 0v to the drain regions of memory cells  12   a  and  12   d  (via bit lines  32   j  and  32   j+4 ) inhibits writing logic high or logic “1” into memory cells  12   a  and  12   d  during the selective write operation for memory cells  12   b  and  12   c.    
     It may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array  10  to minimize and/or reduce the impact of the write operation for memory cells  12   a - 12   d  connected to word line  28   i . With reference to  FIGS. 13 and 14A , in one embodiment, a holding voltage is applied to the gates of the transistors of other memory cells of memory cell array  10  (for example, each memory cell connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 ). In one exemplary embodiment, a holding voltage of −1.2v is applied to the gate of each transistor of the memory cells connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 . In this way, the impact of the write operation of memory cells  12   a - 12   d  (which are connected to word line  28   i ) on the other memory cells of memory cell array  10  is minimized and/or reduced. 
     With reference to  FIG. 14B , in another embodiment, memory cells are selectively written to logic high (logic “1”) using the band-to-band tunneling (GIDL) method. As mentioned above, the band-to-band tunneling provides, produces and/or generates an excess of majority carriers in the electrically floating body of the transistors of each selected memory cell (in this exemplary embodiment, memory cells  12   b  and  12   c ). For example, after implementing the clear operation, memory cells  12   b  and  12   c  are programmed to logic high or logic “1”, via band-to-band tunneling, by applying (i) −3v to the gate (via word line  28   i ), (ii) −0.5v to the source region (via source line  30   i ), and (iii) 1v to the drain region (via bit line  32   j+1  and  32   j+2 ). 
     As mentioned above, the other memory cells connected to word line  28   i  (in this exemplary embodiment, memory cells  12   a  and  12   d ) may be maintained at logic low via application of a write “inhibit” control signal to the bits lines associated with such other memory cells (bit lines  32   j  and  32   j+4 , respectively). Moreover, the other memory cells of memory cell array  10  which are not connected to word line  28   i  may be maintained at a given data state via application of “holding” operation or condition. In this regard, with reference to  FIG. 14B , in one embodiment, a holding voltage is applied to the gate of the transistor of each memory cell connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 . In one exemplary embodiment, −1.2v is applied to the gate of each transistor of the memory cells connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 . In this way, the impact of the write operation for memory cells  12   a - 12   d  (which are connected to word line  28   i ) on the other memory cells of memory cell array  10  is minimized and/or reduced. 
     A selected row of memory cells may be read by applying a read control signals to the associated word line  28  and associated source lines  30  and sensing a signal (voltage and/or current) on associated bit lines  32 . In one exemplary embodiment, with reference to  FIG. 15 , memory cells  12   a - 12   d  are read by applying (i) −0.5v to the gate (via word line  28   i ) and (ii) 3v to the source region (via source line  30   i ). The data write and sense circuitry  36  reads the data state of the memory cells  12   a - 12   d  by sensing the response to the read control signals applied to word line  28   i  and source line  30   i . In response to the read control signals, memory cells  12   a - 12   d  generate a bipolar transistor current which is representative of the data state of memory cells  12   a - 12   d . In this example, memory cells  12   b  and  12   c  (which were earlier programmed to logic “1”), in response to the read control signals, generate a bipolar transistor current which is considerably larger than any channel current. In contrast, memory cells  12   a  and  12   d  (which were earlier programmed to logic “0”), in response to such control signals, induce, cause and/or produce little to no bipolar transistor current (for example, a considerable, substantial or sufficiently measurable bipolar transistor current). The circuitry in data write and sense circuitry  36  which senses the data state of the memory cell (for example, a cross-coupled sense amplifier) senses the data state using and/or based substantially on the bipolar transistor current. 
     Thus, in response to read control signals, the electrically floating body transistor of each memory cell  12   a - 12   d  generates a bipolar transistor current which is representative of the data state stored therein. The data sensing circuitry in data write and sense circuitry  36  determines the data state of memory cells  12   a - 12   d  based substantially on the bipolar transistor current induced, caused and/or produced in response to the read control signals. Notably, as mentioned above, a read operation may be performed by applying other control signaling techniques. 
     Again, it may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array  10  to minimize and/or reduce the impact of the read operation of memory cells  12   a - 12   d . With continued reference to  FIG. 15 , in one embodiment, a holding voltage is applied to the gates of the transistors of other memory cells of memory cell array  10  (for example, each memory cell connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 ). In one exemplary embodiment, a holding voltage of −1.2v is applied to the gate of each transistor of the memory cells connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 . In this way, the impact of the read operation of memory cells  12   a - 12   d  (which are connected to word line  28   i ) on the other memory cells of memory cell array  10  is minimized and/or reduced. 
     In another embodiment, with reference to  FIG. 16 , the control signals to implement a write operation may be configured to provide a lower power consumption as well as a one step write whereby selective memory cells of a selected row of memory cells are selectively written or programmed to either logic “1” or logic “0” without first implementing a “clear” operation. In this embodiment, the temporally varying control signals to implement the write logic “1” operation include the voltage applied to the gate (V gw“1” ) and the voltage applied to the drain region (V dw“1” ). The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, during phase 1, the drain pulse (V dw“1”1 ) may be applied to the drain region (via, for example, the associated bit line) of the electrically floating body transistor of the memory cell before the gate pulse (V gw“1”1 ) is applied to the gate (via, for example, the associated word line), simultaneously thereto, or after the gate pulse (V gw“1”1 ) is applied to gate. It is preferred that the drain pulse (V dw“1”1 ) include an amplitude which is sufficient to maintain a bipolar current that is suitable for programming the memory cell to logic “1”. From a relative timing perspective, it is preferred that the drain pulse (V dw“1”1 ) extend beyond/after or continue beyond the conclusion of the gate pulse (V gw“1”1 ), or extend beyond/after or continue beyond the time the gate pulse (V gw“1”1 ) is reduced, as illustrated in  FIG. 16  (see, Δt&gt;0). In this way, majority carriers are generated in the electrically floating body region via a bipolar current and majority carriers may accumulate (and be stored) in a portion of the electrically floating body region of the transistor of the memory cell  12  that is juxtaposed or near the gate dielectric (which is disposed between the gate and the electrically floating body region). 
     Notably, with continued reference to  FIG. 16 , during phase 2 of the programming, the gate voltage (V gw“1”2 ) may be equal to (or substantially equal to) the voltage applied to the gate to implement a hold operation (V gh ) and the drain bias (V dw“1”2 ) may be equal to (or substantially equal to) the voltage applied to the drain region to implement a hold operation (V dh ). 
     With reference to  FIG. 17 , the temporally varying control signals to implement the write logic “0” operation including the voltage applied to the gate (V gw“0” ) and the voltage applied to the drain region (V dw“0” ). In this embodiment, during phase 1, the control signal applied to the drain region (V dw“0”1 ) may be applied before the control signal is applied to the gate (V gw“0”1 ), or simultaneously thereto, or after the control signal is applied to the gate. It is preferred that the drain pulse (V dw“0”1 ) include an amplitude which is insufficient to maintain a bipolar current that is suitable for programming the memory cell to logic “1”. From a relative timing perspective, it is preferred that the drain pulse (V dw“0”1 ) extend beyond/after or continue beyond the conclusion of the gate pulse (V gw“0”1 ), or extend beyond/after or continue beyond the time the gate pulse (V gw“0”1 ) is reduced, as illustrated in  FIG. 17  (see, Δt&gt;0). In this way, majority carriers are generated in the electrically floating body region via a bipolar current and majority carriers may accumulate (and be stored) in a portion of the electrically floating body region of the transistor of the memory cell  12  that is juxtaposed or near the gate dielectric (which is disposed between the gate and the electrically floating body region). 
     Like phase 2 of the write logic “1” described above, during phase 2 of the write operation for logic “0”, the gate voltage (V gw“0”2 ) may be equal to (or substantially equal to) the voltage applied to the gate to implement a hold operation (V gh ) and the drain bias (V dw“0”2 ) may be equal to (or substantially equal to) the voltage applied to the drain region to implement a hold operation (V dh ). 
     Notably, in the preceding discussion pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. 
     The memory cell may be read using read control signals illustrated in  FIG. 18 . In this embodiment, a read control signal is applied to the drain region and the gate. The voltage applied to the drain region (V dr ) may be applied to drain region before application of the voltage applied to the gate (V gr ), simultaneously thereto, or after the voltage is applied to the gate. Further, the drain pulse (V dr ) may cease or terminate before the gate pulse (V gr ), simultaneously thereto (as illustrated in  FIG. 18 ), or after the gate pulse (V gr ) concludes or ceases. 
     Notably, in this embodiment, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     The programming and reading techniques described herein may be employed in conjunction with a plurality of memory cells arranged in an array of memory cells. A memory array implementing the structure and techniques of the present inventions may be controlled and configured including a plurality of memory cells having a separate source line for each row of memory cells (a row of memory cells includes a common word line). The exemplary layouts or configurations (including exemplary control signal voltage values), according to certain aspects of the present inventions are shown, each consisting of the control signal waveforms and exemplary array voltages during one-step writing phase 1, phase 2, and reading. 
       FIG. 19  provides exemplary control signal information (temporal and amplitude) in connection with the exemplary layout or configuration illustrated in  FIG. 20 . In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (V gw ) via the associated word line, (ii) a voltage applied to the source (V sw ) via the source line, and (iii) a voltage applied to the drain region (V dw ) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having an amplitude of 0.5V, and logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of 0V. In addition, during phase 1 of the write operation, the source pulse (V sw1 ) includes an amplitude of −2.5V and the gate pulse (V gw1 ) includes an amplitude of −2.5V. During phase 2 of the write operation, the source pulse (V sw2 ) includes an amplitude of −2.2V and the gate pulse (V gw2 ) includes an amplitude of −3.3V. 
     Notably, under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, under these conditions, little to no bipolar current is generated for programming the memory cell to logic “0”. 
     As noted above, in the preceding discussion pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. Although the “one-step” programming technique may consume more power than the “two-step” programming technique, the “one-step” programming technique may present a less complex control signaling regime and circuitry therefor. 
     A row of memory cells (for example,  12   a - 12   d ) may be read in parallel. In this embodiment, memory cells  12  are read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line and (ii) a voltage applied to the source (V sr ) via the source line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of −0.5V and the source pulse (V sr ) includes an amplitude of 3V. 
     Notably, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
       FIG. 21  provides exemplary control signal information (temporal and amplitude) in connection with the exemplary layout illustrated in  FIG. 20 . In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (V gw ) via the associated word line, (ii) a voltage applied to the source (V sw ) via the source line, and (iii) a voltage applied to the drain region (V dw ) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having (i) an amplitude of 0.5V during phase 1 and (ii) an amplitude of 0V during phase 2, and logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of 0V. In addition, during phase 1 of the write operation, the source pulse (V sw1 ) includes an amplitude of −2.5V and the gate pulse (V gw1 ) includes an amplitude of −2.5V. During phase 2 of the write operation, the source pulse (V sw2 ) includes an amplitude of −2.5V and the gate pulse (V gw2 ) includes an amplitude of −3.3V. 
     Notably, under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, under these conditions, little to no bipolar current is generated for programming the memory cell to logic “0”. 
     As noted above, in the preceding discussion pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. 
     A row of memory cells (for example,  12   a - 12   d ) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line and (ii) a voltage applied to the source (V sr ) via the source line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of −0.5V and the source pulse (V sr ) includes an amplitude of 3V. 
     Notably, as mentioned above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
       FIG. 22  provides exemplary control signal information (temporal and amplitude) in connection with the exemplary layout illustrated in  FIG. 20 . In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (V gw ) via the associated word line, (ii) a voltage applied to the source (V sw ) via the source line, and (iii) a voltage applied to the drain region (V dw ) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having an amplitude of 0.5V, and logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of 0V. In addition, during phase 1 of the write operation, the source pulse (V sw“1”1 ) includes an amplitude of −2.5V and the gate pulse (V gw“1”1 ) includes an amplitude of −2.5V. During phase 2 of the write operation, the source pulse (V sw“1”2 ) includes an amplitude of −2.2V, and the gate pulse (V gw“1”2 ) includes an amplitude of −3.3V. Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”. 
     As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. 
     A row of memory cells (for example,  12   a - 12   d ) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line and (ii) a voltage applied to the source (V sr ) via the source line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of −3V and the source pulse (V sr ) includes an amplitude of −3.5V. 
     As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
       FIG. 23  provides exemplary control signal information (temporal and amplitude) in connection with the exemplary layout illustrated in  FIG. 20 . In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (V gw ) via the associated word line, (ii) a voltage applied to the source (V sw ) via the source line, and (iii) a voltage applied to the drain region (V dw ) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having (i) an amplitude of 0.5V during phase 1 and (ii) an amplitude of 0V during phase 2, and logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of 0V. In addition, during phase 1 of the write operation, the source pulse (V sw1 ) includes an amplitude of −2.5V and the gate pulse (V gw1 ) includes an amplitude of −2.5V. During phase 2 of the write operation, the source pulse (V sw2 ) includes an amplitude of −2.5V, and the gate pulse (V gw2 ) includes an amplitude of −3.3V. Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”. 
     As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. 
     A row of memory cells (for example,  12   a - 12   d ) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line and (ii) a voltage applied to the source (V sr ) via the source line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of −3V and the source pulse (V sr ) includes an amplitude of −3.5V. 
     As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
       FIG. 24  provides exemplary control signal information (temporal and amplitude) in connection with the exemplary layout illustrated in  FIG. 20 . 
     In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (V gw ) via the associated word line, (ii) a voltage applied to the source (V sw ) via the source line, and (iii) a voltage applied to the drain region (V dw ) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having an amplitude of 0.5V, and logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of 0V. In addition, during phase 1 of the write operation, the source pulse (V sw1 ) includes an amplitude of −2.5V and the gate pulse (V gw1 ) includes an amplitude of −2.5V. During phase 2 of the write operation, the source pulse (V sw2 ) includes an amplitude of −2.2V, and the gate pulse (V gw2 ) includes an amplitude of −3.3V. Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”. 
     As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. 
     A row of memory cells (for example,  12   a - 12   d ) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line and (ii) a voltage applied to the source (V sr ) via the source line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of −2.5V and the source pulse (V sr ) includes an amplitude of −3V. 
     As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
       FIG. 25  provides exemplary control signal information (temporal and amplitude) in connection with the exemplary layout illustrated in  FIG. 20 . In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (V gw ) via the associated word line, (ii) a voltage applied to the source (V sw ) via the source line, and (iii) a voltage applied to the drain region (V dw ) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having (i) an amplitude of 0.5V during phase 1 and (ii) an amplitude of 0V during phase 2, and logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of 0V. In addition, during phase 1 of the write operation, the source pulse (V sw1 ) includes an amplitude of −2.5V and the gate pulse (V gw1 ) includes an amplitude of −2.5V. During phase 2 of the write operation, the source pulse (V sw2 ) includes an amplitude of −2.5V, the drain pulse (V dw2 ) includes an amplitude of 0V, and the gate pulse (V gw2 ) includes an amplitude of −3.3V. Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”. 
     As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. 
     A row of memory cells (for example,  12   a - 12   d ) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line, (ii) a voltage applied to the source (V sr ) via the source line, and (iii) a voltage applied to the drain (V dr ) via the associated bit line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of −3V, the source pulse (V sr ) includes an amplitude of −2.5V and the drain pulse (V dr ) includes an amplitude of 0.5V. 
     As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     Although not discussed above with respect to the embodiments illustrated in  FIGS. 19-25 , it may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array  10  to minimize and/or reduce the impact of the write and/or read operations for memory cells  12   a - 12   d  connected to word line  28   i . For example, with reference to  FIGS. 19 and 20 , in one embodiment, a holding voltage is applied to the gates of the transistors of other memory cells of memory cell array  10  (for example, each memory cell connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 ). In one exemplary embodiment, a holding voltage of −1.2v is applied to the gate of each transistor of the memory cells connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 . In this way, the impact of the write operation of memory cells  12   a - 12   d  (which are connected to word line  28   i ) on the other memory cells of memory cell array  10  is minimized and/or reduced. 
     Notably, the illustrated/exemplary voltage levels discussed above to implement the write and read operations of the embodiments of  FIGS. 19-25  are merely exemplary. In the context of certain write and read operations, the control signals increase the potential of electrically floating body region which “turns on” or produces a bipolar current in the transistor of the memory cell. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a read operation, the data state may be determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     Accordingly, the illustrated/exemplary voltage levels to implement the write and read operations are merely exemplary. the indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative. 
     As mentioned above, the present inventions may be implemented in any memory array architecture having a plurality of memory cells that employ electrically floating body transistors. For example, in one embodiment, with reference to  FIGS. 26 and 27 , a memory array implementing the structure and techniques of the present inventions may be controlled and configured having a common source line for every two rows of memory cells (a row of memory cells includes a common word line). An example (including exemplary control signal voltage values), according to certain aspects of the present inventions is also shown that consists of the control signal waveforms and exemplary array voltages during one-step writing phase 1, phase 2, and reading. 
     In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (V gw ) via the associated word line and (ii) a voltage applied to the drain region (V dw ) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having (i) an amplitude of 3V during phase 1 and (ii) an amplitude of 2.7V during phase 2. Conversely, logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having (i) an amplitude of 2.5V during phase 1 and (ii) an amplitude of 2.2V during phase 2. In addition, during phase 1 of the write operation, the gate pulse (V gw1 ) includes an amplitude of 0V. During phase 2 of the write operation, the gate pulse (V gw2 ) includes an amplitude of −1.5V. The voltage applied to the source lines (and, as such, the source regions of the transistors of the row of memory cells) is 0V. Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”. 
     As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. 
     A row of memory cells (for example,  12   a - 12   d ) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line and (ii) a voltage applied to the drain (V dr ) via the associated bit line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of −0.5V and the drain pulse (V dr ) includes an amplitude of 3V. The voltage applied to the source lines (and, as such, the source regions of the transistors of the row of memory cells) is 0V. 
     As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     Again, it may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array  10  to minimize and/or reduce the impact of the write operation for memory cells  12   a - 12   d  connected to word line  28   i . In this embodiment, a holding voltage is applied to the gates of the transistors of other memory cells of memory cell array  10  (for example, each memory cell connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 ). In one exemplary embodiment, a holding voltage of −1.2v is applied to the gate of each transistor of the memory cells connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 . In this way, the impact of the write operation of memory cells  12   a - 12   d  (which are connected to word line  28   i ) on the other memory cells of memory cell array  10  is minimized and/or reduced. 
     Notably, the reading technique described herein may reduce the degradation of the floating body charge caused by charge-pumping (charge-pumping disturb) thus allowing the quasi non-disturbing reading (see, for example,  FIG. 28 ). As a result, when memory cell  12  is read multiple times without or before a refresh operation, the read window remains relatively stable for each successive read operation. 
     The memory array may employ any of the exemplary programming, holding and/or reading techniques described herein. Moreover, exemplary voltage values for each of the control signals for a given operation (for example, programming, holding or reading), according to exemplary embodiments of the present inventions, is also provided. 
     As noted above, these embodiments of the present inventions may be implemented in any electrically floating body memory cell and memory cell array. For example, in one aspect, the present inventions are a memory array, having a plurality of memory cells each including an electrically floating body transistor, and/or technique of writing or programming data into one or more memory cells of such a memory array. In this aspect of the inventions, the data states of adjacent memory cells and/or memory cells that share a word line may be individually programmed. 
     The memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells  12  in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, these discussions will not be repeated. 
     In another exemplary embodiment, with reference to  FIGS. 29 and 30 , control signals having a predetermined amplitude may be selectively applied to a row of memory cells (for example, memory cells  12   a - d ) to write logic “1” into selected memory cells  12   a  and  12   d , and logic “0” into selected memory cells  12   b  and  12   c . In particular, the logic “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having an amplitude of 0V, and logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of 0.5V. For example, logic “1” may be programmed or written in memory cells  12   a  and  12   d  by applying a voltage pulse of 0V to bit lines  32   j  and  32   j+3 , respectively. Logic “0” is programmed in memory cells  12   b  and  12   c  by applying a voltage pulse of 0.5V to bit lines  32   j+1  and  32   j+2 , respectively. 
     In addition, a voltage of 3V is applied to source region of the transistors of memory cells  12   a - 12   d  (via source line  30   i - 30   i+4 ) and a voltage pulse of 0.5V to gate of the transistors of memory cells  12   a - 12   d  (via word line  28   i ). The source pulse may be applied before the gate pulse, simultaneously thereto, or after the gate pulse is applied to gate  16  of memory cells  12   a  and  12   d . It is preferred that the source pulse be applied to source region of the transistors of memory cells  12   a  and  12   d  with a sufficient amplitude to maintain a sufficient bipolar current to program logic “1” into memory cells  12   a  and  12   d . From a relative timing perspective, it is preferred that the source pulse extend beyond when the gate pulse reduces or ceases, as illustrated in  FIG. 29 . In this way, majority carriers are generated in the electrically floating body region and majority carriers may accumulate (and be stored) in a portion of the electrically floating body region of the transistor of the memory cell  12  that is juxtaposed or near the gate dielectric (which is disposed between the gate and the electrically floating body region). 
     Notably, in this exemplary embodiment, when programming logic “0”, a drain pulse (0.5V amplitude in this example) is applied to drain regions of the transistors of memory cells  12   b  and  12   c  to prevent, prohibit, limit and/or retard a bipolar current (if any) from causing or generating a sufficient charge in the floating body region of transistors to program or write logic state “1” into the transistors of memory cells  12   b  and  12   c . As such, the drain pulse may be characterized as a “blocking” pulse. From a relative timing perspective, it is preferred that the drain pulse be applied to drain regions of the transistors of memory cells  12   b  and  12   c  for a temporal period that extends beyond or is applied before, during and after the source and gate pulses (for example, initiates, starts, ramps, declines and/or terminates) as illustrated in  FIG. 29 . 
     With continued reference to  FIGS. 29 and 30 , for those unselected memory cells (i.e., the memory cells coupled to word lines  28   i+1 ,  28   i+2  and  28   i+3 ), a holding condition may be applied or established to prevent, minimize or avoid disturbance of the data state of, or charge stored in the unselected memory cells. In this regard, a voltage (for example, −1.2V) may be applied to gates  16  of the unselected memory cells and a voltage (for example, 0V) may be applied to source regions and drain regions of the transistors of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the programming or writing operation. Under these conditions, the data state of the unselected memory cells is unaffected (or substantially unaffected) by the programming of or writing to selected memory cells  12   a - d.    
     The memory cells may be read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line and (ii) a voltage applied to the source (V sr ) via the source line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of −0.5V and the source pulse (V sr ) includes an amplitude of 3V. In this embodiment, the source pulse (V sr ) may be applied to source line  30  (and, for example, the source regions of the transistors of memory cells  12   a - 12   d ) before application of the gate pulse to word line  28  (and, for example, the gates of the transistors of memory cells  12   a - 12   d ), simultaneously thereto, or after the gate pulse is applied to word line  28 . Further, the source pulse may cease or terminate before the gate pulse, simultaneously thereto (as illustrated in  FIG. 29 ), or after the gate pulse concludes or ceases. 
     Notably, for those memory cells that are not read (i.e., those memory cells coupled to word lines  28   i+1 ,  28   i+2  and  28   i+3 ), a holding condition may be applied or established to prevent, minimize or avoid disturbance of the data state in the unselected memory cells. In this regard, a voltage (for example, −1.2V) may be applied to gates  16  of the unselected memory cells and a voltage (for example, 0V) may be applied to source regions of the transistors of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the read operation. Under these conditions, the state of the unselected memory cells is unaffected (or it is substantially unaffected) during the reading of, for example, selected memory cells  12   a - d.    
     As noted above, the illustrated/exemplary voltage levels to implement the write and read operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.25, 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative. 
     During the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     Further, the reading technique described herein may reduce the degradation of the floating body charge caused by charge-pumping (charge-pumping disturb) thus allowing the quasi non-disturbing reading. As a result, when memory cell  12  is read multiple times without or before a refresh operation, the read window remains relatively stable for each successive read operation. 
     As noted above, memory array  10  may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells  12  in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. For example, with reference to  FIG. 31 , where P-channel type transistors are employed as memory cells  12 , the exemplary control voltages and timing relationships of  FIG. 32  may be employed to (i) program or write logic state “1” into one or more P-channel type memory cells, (ii) program or write logic state “0” into one or more P-channel type memory cells, and (iii) read one or more P-channel type memory cells. 
     Briefly, the logic “1” and “0” are written to one or more selected memory cells, having P-channel type transistors, by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having an amplitude of 0V, and logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of −0.5V. For example, logic “1” may be programmed or written in memory cells  12   a  and  12   d  by applying a voltage pulse of 0V to bit lines  32   j  and  32   j+3 , respectively. Logic “0” is programmed in memory cells  12   b  and  12   c  by applying a voltage pulse of −0.5V to bit lines  32   j+1  and  32   j+2 , respectively. 
     In addition, a voltage of −3V is applied to source region of the transistors of memory cells  12   a - 12   d  (via source line  30   i - 30   i+4 ) and a voltage pulse of −0.5V to gate of the transistors of memory cells  12   a - 12   d  (via word line  28   i ). As with the N-channel type memory cells, the source pulse may be applied before the gate pulse, simultaneously thereto, or after the gate pulse is applied to the gate of the memory cells. It is preferred that the source pulse be applied to source region of the memory cells with a sufficient amplitude to maintain a sufficient bipolar current to program logic state “1” into the memory cells. From a relative timing perspective, it is preferred that the source pulse extends beyond when the gate pulse reduces or ceases (See,  FIG. 32 ). In this way, majority carriers are generated in the electrically floating body region and majority carriers may accumulate (and be stored) in a portion of the electrically floating body region of the transistor of the memory cell  12  that is juxtaposed or near the gate dielectric (which is disposed between the gate and the electrically floating body region). 
     Notably, in this exemplary embodiment, when programming logic “0”, a drain pulse (−0.5V amplitude in this example) is applied to drain regions of the transistors of memory cells  12   b  and  12   c  to prevent, prohibit, limit and/or retard a bipolar current (if any) from causing or generating a sufficient charge in the floating body region of transistors to program or write logic state “1” into the transistors of memory cells  12   b  and  12   c . As such, the drain pulse may be characterized as a “blocking” pulse. From a relative timing perspective, it is preferred that the drain pulse be applied to drain regions of the transistors of memory cells  12   b  and  12   c  for a temporal period that extends beyond or is applied before, during and after the source and gate pulses (for example, initiates, starts, ramps, declines and/or terminates) as illustrated in  FIG. 32 . 
     From a relative timing perspective, it is preferred that the drain pulse be applied to the drain region of the memory cells programmed to logic state “0” for a temporal period that extends or is applied before, during and after the source and gate pulses (for example, initiates, starts, ramps, declines and/or terminates). (See,  FIG. 32 ). 
     Notably, for those unselected memory cells (i.e., the memory cells coupled to word lines not enabled), a holding condition may be applied or established to prevent, minimize or avoid disturbance of the data state of, or charge stored in the unselected memory cells. In this regard, a voltage (for example, 1.2V) may be applied to the gates of the unselected memory cells and a voltage (for example, 0V) may be applied to the source and drain regions of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the programming or writing operation. Under these conditions, the data state of the unselected memory cells is unaffected (or substantially unaffected) by the programming of or writing to selected memory cells. 
     The data may be read from P-channel type memory cells applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line and (ii) a voltage applied to the source (V sr ) via the source line. The logic state of each memory cell (for example,  12   a - 12   d ) is sensed, determined and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate pulse (V gr ) includes an amplitude of 0.5V and the source pulse (V sr ) includes an amplitude of −3V. In this embodiment, the source pulse (V sr ) may be applied to source line  30  (and, for example, the source regions of the transistors of memory cells  12   a - 12   d ) before application of the gate pulse to word line  28  (and, for example, the gates of the transistors of memory cells  12   a - 12   d ), simultaneously thereto, or after the gate pulse is applied to word line  28 . Further, the source pulse may cease or terminate before the gate pulse, simultaneously thereto (as illustrated in  FIG. 32 ), or after the gate pulse concludes or ceases. 
     During the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     Notably, for those memory cells that are not read (i.e., those memory cells coupled to non-enabled or unselected word lines), a holding condition may be applied or established to prevent, minimize or avoid disturbance of the data state in the unselected memory cells. In this regard, a voltage (for example, 1.2V) may be applied to the gates of the unselected memory cells and a voltage (for example, 0V) may be applied to the source regions of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the read operation. Under these conditions, the states of the unselected memory cells are unaffected (or it is substantially unaffected) during the reading of selected memory cells. 
     The voltage amplitudes illustrated in  FIG. 32  to perform certain operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, as mentioned above, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by −0.1, −0.25, −0.5, −1.0 and −2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative. 
     As mentioned above, the present inventions may be implemented in any electrically floating body memory cell and memory cell array. For example, in certain aspects, the present inventions are directed to a memory array, having a plurality of memory cells each including an electrically floating body transistor, and/or technique of programming data into one or more memory cells of such a memory cell array. In this aspect of the inventions, the data states of adjacent memory cells and/or memory cells that share a word line may or may not be individually programmed. 
     With reference to  FIGS. 12A and 12B , memory array  10  may be comprised of a plurality of memory cells  12  of N-channel type, P-channel type and/or both types of electrically floating body transistors. The memory array  10  includes a plurality of rows and columns (for example, in a matrix form) of memory cells  12 . 
     The circuitry which is peripheral to memory array  10  (for example, data write and sense circuitry  36  (such as, for example, sense amplifiers or comparators), memory cell selection and control circuitry  38  (such as, for example, address decoders and word line drivers)) may include P-channel type and/or N-channel type transistors. Where N-channel type transistors or P-channel type transistors are employed as memory cells  12  in memory array(s)  10 , suitable write voltages are known to those skilled in the art. Accordingly, for sake of brevity, these discussions will not be repeated here. 
     As mentioned above, memory cells  12  (having electrically floating body transistor  14 ) and memory cell array  10  of the present inventions may be implemented in an integrated circuit device having a memory portion and a logic portion (see, for example,  FIG. 12A ), or an integrated circuit device that is primarily a memory device (see, for example,  FIG. 12B ). Indeed, the present inventions may be implemented in any device having one or more memory cells  12  (having electrically floating body transistors) and/or memory cell arrays  10 . For example, with reference to  FIG. 12A , an integrated circuit device may include array  10 , having a plurality of memory cells  12  (having electrically floating body transistors), data write and sense circuitry, and memory cell selection and control circuitry (not illustrated in detail). The data write and sense circuitry writes data into and senses the data state of one or more memory cells. The memory cell selection and control circuitry selects and/or enables one or more predetermined memory cells  12  to be read by data sense circuitry during a read operation. 
     For example, the electrically floating body transistor, which programmed (written to), controlled and/or read using the techniques of the present inventions, may be employed in any electrically floating body memory cell, and/or memory cell array architecture, layout, structure and/or configuration employing such electrically floating body memory cells. In this regard, an electrically floating body transistor, which state is read by using the techniques of the present inventions, may be implemented in the memory cell, architecture, layout, structure and/or configuration described and illustrated in the following non-provisional U.S. patent applications: 
     (1) application Ser. No. 10/450,238, which was filed by Fazan et al. on Jun. 10, 2003 and entitled “Semiconductor Device” (now U.S. Pat. No. 6,969,662); 
     (2) application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (U.S. Patent Application Publication No. 2004/0238890); 
     (3) application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (U.S. Patent Application Publication No. 2005/0013163); 
     (4) application Ser. No. 10/840,009, which was filed by Ferrant et al. on May 6, 2004 and entitled “Semiconductor Memory Device and Method of Operating Same” (U.S. Patent Application Publication No. 2004/0228168); and 
     (5) application Ser. No. 10/941,692, which was filed by Fazan et al. on Sep. 15, 2004 and entitled “Low Power Programming Technique for a One Transistor SOI Memory Device &amp; Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same” (U.S. Patent Application Publication No. 2005/0063224). 
     The entire contents of these five (5) U.S. patent applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. For the sake of brevity, those discussions will not be repeated; rather those discussions (text and illustrations), including the discussions relating to the memory cell, architecture, layout, structure, are incorporated by reference herein in its entirety. 
     Notably, the memory cells may be controlled (for example, programmed or read) using any of the control circuitry described and illustrated in the above-referenced five (5) U.S. patent applications. For the sake of brevity, those discussions will not be repeated; such control circuitry is incorporated herein by reference. Indeed, all memory cell selection and control circuitry for programming, reading, controlling and/or operating memory cells including electrically floating body transistors, whether now known or later developed, are intended to fall within the scope of the present inventions. 
     Moreover, the data write and data sense circuitry may include a sense amplifier (not illustrated in detail herein) to read the data stored in memory cells  12 . The sense amplifier may sense the data state stored in memory cell  12  using voltage or current sensing circuitry and/or techniques. In the context of a current sense amplifier, the current sense amplifier may compare the cell current to a reference current, for example, the current of a reference cell (not illustrated). From that comparison, it may be determined whether memory cell  12  contained logic high (relatively more majority carriers  34  contained within body region  18 ) or logic low data state (relatively less majority carriers  34  contained within body region  18 ). Such circuitry and configurations thereof are well known in the art. 
     In addition, the present inventions may employ the reference generation techniques (used in conjunction with the data sense circuitry for the read operation) described and illustrated in U.S. Provisional Patent Application Ser. No. 60/718,417, which was filed by Bauser on Sep. 19, 2005, and entitled “Method and Circuitry to Generate a Reference Current for Reading a Memory Cell Having an Electrically Floating Body Transistor, and Device Implementing Same”. The entire contents of the U.S. Provisional Patent Application Ser. No. 60/718,417 are incorporated herein by reference. Further, the present inventions may also employ the read circuitry and techniques described and illustrated in U.S. patent application Ser. No. 10/840,902, which was filed by Portmann et al. on May 7, 2004, and entitled “Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same” (now U.S. Pat. No. 6,912,150). The contents of U.S. Provisional Patent Application Ser. No. 60/718,417 and U.S. Pat. No. 6,912,150 are hereby incorporated by reference herein. 
     It should be further noted that while each memory cell  12  in the exemplary embodiments (described above) includes one transistor  14 , memory cell  12  may include two transistors, as described and illustrated in application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (U.S. Patent Application Publication No. 2005/0013163). The contents of U.S. Patent Application Publication No. 2005/0013163 are hereby incorporated by reference herein 
     The electrically floating memory cells, transistors and/or memory array(s) may be fabricated using well known techniques and/or materials. Indeed, any fabrication technique and/or material, whether now known or later developed, may be employed to fabricate the electrically floating memory cells, transistors and/or memory array(s). For example, the present inventions may employ silicon, germanium, silicon/germanium, gallium arsenide or any other semiconductor material (whether bulk-type or SOI) in which transistors may be formed. As such, the electrically floating memory cells may be disposed on or in (collectively “on”) SOI-type substrate or a bulk-type substrate. 
     Indeed, the electrically floating transistors, memory cells, and/or memory array(s) may employ the techniques described and illustrated in non-provisional patent application entitled “Integrated Circuit Device, and Method of Fabricating Same”, which was filed on Jul. 2, 2004, by Fazan, Ser. No. 10/884,481 (U.S. Patent Application Publication No. 2005/0017240), provisional patent application entitled “One Transistor Memory Cell having Mechanically Strained Electrically Floating Body Region, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,060, by Bassin, and/or provisional patent application entitled “Memory Cell, Array and Device, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,061, by Okhonin et al. (hereinafter collectively “Integrated Circuit Device Patent Applications”). The contents of the Integrated Circuit Device Patent Applications are hereby incorporated by reference herein. 
     In another aspect, the present inventions are directed to techniques for programming, reading, controlling and/or operating a semiconductor memory cell, array, architecture and device including electrically floating body transistors, having, for example, fully depleted (FD), surrounding-gate, double-gate, triple-gate and/or FinFET characteristics, in which electrical charge is stored in the body of the transistor. The present inventions are also directed to semiconductor memory cell, array, architecture and device that implement circuitry to implement such reading, controlling and/or operating techniques. The programming/reading technique may employ any of the techniques described and/or illustrated herein. 
       FIG. 33  illustrates the FD transistor (N-channel type) in a holding condition in accordance with the present inventions. The accumulation layer is induced by application of a negative bias or voltage to the front gate (i.e., gate  16 ). In this case FD transistor  14  behaves as a PD transistor thus it may be used as a floating body memory cell. When used in this manner, an advantage of this embodiment is that a back gate bias need not be applied. 
       FIGS. 34 and 35  illustrate the inventive technique applied to the double-gate and triple-gate transistors, respectively, wherein the electrically floating body transistor is used as a memory cell. With reference to  FIG. 34 , double gate transistor (N-channel type)  14  is in a holding condition. By inducing an accumulation layer via application of a negative bias or voltage to the front gate (i.e., gate  16 —illustrated as g 1  and g 2  in the cross-sectional view) double gate transistor  14  behaves as or similar to a PD transistor. In this way, transistor  14  may be employed as a floating body memory cell. Again, a back gate bias need not be applied but may be incorporated. 
     Similarly, with reference to  FIG. 35 , triple gate transistor (N-channel type)  14  is in a holding condition. By inducing an accumulation layer via application of a negative bias or voltage to the front gate (i.e., gate  16 ) transistor  14  behaves as or similar to a PD transistor and, as such, may be employed as a floating body memory cell. 
       FIG. 36  illustrates that the use of the present inventions may simplify the memory array by eliminating additional fabrication steps in relation to certain other techniques/embodiments (See, for example, conventional FD-SOI or PD-SOI transistors integration of Fazan, U.S. patent application Ser. No. 10/487,157). In this embodiment, a voltage may be applied to the entire substrate or predetermined portion or regions thereof (for example, regions in which the memory array(s) are/is located) to provide or create a PD-like region wherein the memory cells comprised of transistors having electrically floating body are disposed. 
     Moreover, memory array  10  (including SOI memory transistors) may be integrated with SOI logic transistors, as described and illustrated in the Integrated Circuit Device Patent Applications. For example, in one embodiment, an integrated circuit device includes memory section (having, for example, PD or FD SOI memory transistors  14 ) and logic section (having, for example, high performance transistors, such as FinFET, multiple gate transistors, and/or non-high performance transistors (for example, single gate transistors that do not possess the performance characteristics of high performance transistors—not illustrated)). 
     Further, memory array(s)  10  may be comprised of N-channel, P-channel and/or both types of transistors, as well as partially depleted and/or fully depleted type transistors. For example, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include fully depleted type transistors (whether P-channel and/or N-channel type). Alternatively, such circuitry may include partially depleted type transistors (whether P-channel and/or N-channel type). There are many techniques to integrate both partially depleted and/or fully depleted type transistors on the same substrate (see, for example, application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (U.S. Patent Application Publication No. 2004/0238890)). All such techniques, whether now known or later developed, are intended to fall within the scope of the present inventions. 
     Notably, electrically floating body transistor  14  may be a symmetrical or non-symmetrical device. Where transistor  14  is symmetrical, the source and drain regions are essentially interchangeable. However, where transistor  14  is a non-symmetrical device, the source or drain regions of transistor  14  have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable. This notwithstanding, the drain region of the electrically floating N-channel transistor of the memory cell (whether the source and drain regions are interchangeable or not) is that region of the transistor that is connected to the bit line/sense amplifier. 
     As mentioned above, the memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells  12  in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, these discussions will not be repeated. 
     There are many inventions described and illustrated herein. While certain embodiments, features, attributes and advantages of the inventions have been described and illustrated, it should be understood that many others, as well as different and/or similar embodiments, features, attributes and advantages of the present inventions, are apparent from the description and illustrations. As such, the embodiments, features, attributes and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, attributes and advantages of the present inventions are within the scope of the present inventions. 
     As mentioned above, the illustrated/exemplary voltage levels to implement the read and write operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.1, 0.15, 0.25, 0.5, 1 volt) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative. 
     The illustrated/exemplary voltage levels and timing to implement the write and read operations are merely exemplary. In this regard, in certain embodiments, the control signals increase the potential of electrically floating body region of the transistor of the memory cell which “turns on” or produces a bipolar current in the transistor. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a read operation, the data state may be determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     For example, with reference to  FIGS. 27 and 37 , temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (V gw ) via the associated word line and (ii) a voltage applied to the drain region (V dw ) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (V dw“1” ) having an amplitude of 0V. Conversely, logic “0” is written into a memory cell by applying the drain pulse (V dw“0” ) having an amplitude of 0.5V. In addition, during phase 1 of the write operation, the gate pulse (V gw1 ) includes an amplitude of 0.5V. During phase 2 of the write operation, the gate pulse (V gw2 ) includes an amplitude of −1V. The voltage applied to the source lines (and, as such, the source regions of the transistors of the row of memory cells) is 3V. 
     Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”. Here, the drain pulse may be characterized as a “blocking” pulse. From a relative timing perspective, it is preferred that the drain pulse be applied to drain regions of the transistors of memory cells  12  for a temporal period that extends beyond or is applied before, during and after the source and gate pulses (for example, initiates, starts, ramps, declines and/or terminates) as illustrated in  FIG. 37 . 
     As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. 
     In this embodiment, the control techniques facilitate a one step write operation whereby selective memory cells of the selected row are selectively written or programmed to either logic “1” or logic “0” without first implementing a “clear” operation. 
     Notably, memory cells of the embodiment of  FIG. 37  (for example,  12   a - 12   d ) may be read in the same manner as described above with respect to  FIGS. 26 and 27 . 
     After a read and/or write operation of a row of memory cells, it may be advantageous to employ a refresh operation to the neighboring row of memory cells. In this regard, the neighboring rows of memory cells are those rows of memory cells which “share” a source line  30 . Thus, with reference to  FIG. 27 , where the read and/or write operation is conducted on the row of memory cells associated with word line  28   i , the neighboring row of memory cells is associated with word line  28   i+1 . The word lines  28   i  and  28   i+1  “share” source line  30   i . 
     Further, it may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array  10  to minimize and/or reduce the impact of the read and write operations for memory cells  12   a - 12   d  connected to word line  28   i . For example, with reference to  FIGS. 27 and 37 , in one embodiment, a holding voltage is applied to the gates of the transistors of other memory cells of memory cell array  10  (for example, each memory cell connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 ). In one exemplary embodiment, a holding voltage of −1.2v is applied to the gate of each transistor of the memory cells connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 . In this way, the impact of the write operation of memory cells  12   a - 12   d  (which are connected to word line  28   i ) on the other memory cells of memory cell array  10  is minimized and/or reduced. 
     As mentioned above, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of such aspects and/or embodiments. For the sake of brevity, those permutations and combinations will not be discussed separately herein. As such, the present inventions are neither limited to any single aspect (nor embodiment thereof), nor to any combinations and/or permutations of such aspects and/or embodiments. 
     Moreover, the above embodiments of the present inventions are merely exemplary embodiments. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. Many modifications and variations are possible in light of the above teaching. It is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. As such, the foregoing description of the exemplary embodiments of the inventions has been presented for the purposes of illustration and description. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the inventions not be limited solely to the description above.