Patent Publication Number: US-7916064-B2

Title: Voltage-to-time converter, and voltage-to-digital converting device having the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority of Taiwanese Application No. 098102512, filed on Jan. 22, 2009. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a signal converting device, more particularly a voltage-to-digital converting device having a voltage-to-time converter. 
     2. Description of the Related Art 
     A conventional voltage-to-time converter proposed in an article by J.-B. Begueret, M. R. Benbrahim, Z. Li, F. Rodes and J.-P. Dom, entitled “Converters dedicated to long-term monitoring of strain gauge transducers”, IEEE JSSC, vol. 32, pp. 349-356, March 1997, is capable of converting a voltage signal into a timing signal that is associated with resistance and capacitance of an RC-integrator. However, a drift of integrated circuit fabrication easily incurs an error in the capacitance of the RC-integrator. Furthermore, increased operating temperature may cause the resistance of the RC-integrator to vary. Therefore, due to non-ideal variance of the resistance, resolution of the timing signal generated by the conventional voltage-to-time converter is reduced. 
     Another conventional voltage-to-time converter proposed in an article by S.-J. Bae, H.-J. Chi, Y.-S. Sohn and H.-J. Park, entitled “A VCDL-based 60-760 MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme”, IEEE JSSC, vol. 40, pp. 1119-1129, May 2005, is capable of outputting a timing signal in response to an input voltage, where the timing signal has a time delay corresponding to the input voltage. However, the conventional voltage-to-time converter is based upon non-linear operation, i.e., the time delay is not proportional to the input voltage. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a voltage-to-digital converting device having a voltage-to-time converter that can overcome the aforesaid drawbacks of the prior art. 
     According to one aspect of the present invention, there is provided a voltage-to-digital converting device adapted for converting an input voltage into a digital signal. The voltage-to-digital converting device comprises: 
     a first voltage-to-time converter adapted for receiving a reference clock and the input voltage, and outputting a first delay clock in response to the input voltage, the first delay clock having a first time delay relative to the reference clock, the first time delay corresponding to the input voltage; 
     a second voltage-to-time converter adapted for receiving the reference clock and a feedback voltage, and outputting a second delay clock in response to the feedback voltage, the second delay clock having a second time delay relative to the reference clock, the second time delay corresponding to the feedback voltage; and 
     a time-to-digital converting circuit coupled to the first and second voltage-to-time converters for receiving the first and second delay clocks therefrom, comparing phases of the first and second delay clocks, generating the feedback voltage based on result of phase comparison made thereby, and outputting the digital signal upon detecting that the phases of the first and second delay clocks are in-phase. 
     According to another aspect of the present invention, there is provided a voltage-to-digital converting device adapted for converting a difference between first and second voltages into a digital signal. The voltage-to-digital converting device comprises: 
     a first voltage-to-time converter adapted for receiving a reference clock and the first voltage, and outputting a first delay clock in response to the first voltage, the first delay clock having a first time delay relative to the reference clock, the first time delay corresponding to the first voltage; 
     a second voltage-to-time converter adapted for receiving the reference clock and the second voltage, and outputting a second delay clock in response to the second voltage, the second delay clock having a second time delay relative to the reference clock, the second time delay corresponding to the second voltage; and 
     a time-to-digital converting circuit coupled to the first and second voltage-to-time converters for receiving the first and second delay clocks therefrom, and outputting the digital signal in accordance with a difference between phases of the first and second delay clocks. 
     According to a further aspect of the present invention, a voltage-to-time converter comprises: 
     a series connection of a current source, a first switch and a capacitor, the first switch having a control end for receiving a first control signal such that the first switch is operable between an ON-state and an OFF-state in response to the first control signal; 
     a comparator having a first input end coupled to a common node of the first switch and the capacitor, a second input end adapted for receiving an input voltage, and an output end; 
     a second switch adapted to be coupled between the first input end of the comparator and a reference voltage source, and having a control end for receiving a second control signal such that the second switch is operable between an ON-state and an OFF-state in response to the second control signal; 
     a first flip-flop having a high-level data input, a clock input adapted for receiving a reference clock, a clear input coupled to the output end of the comparator, a data output coupled to the control end of the first switch and outputting the first control signal to the control end of the first switch, and an inverted data output coupled to the control end of the second switch and outputting the second control signal to the control end of the second switch; and 
     a second flip-flop having a low-level data input, a clock input adapted for receiving the reference clock, a set input coupled to the output end of the comparator, and a data output for outputting an output clock. 
     The output clock outputted by the second flip-flop has a time delay relative to the reference clock. The time delay corresponds to the input voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which: 
         FIG. 1  is a schematic circuit block diagram illustrating the first preferred embodiment of a voltage-to-digital converting device according to the present invention; 
         FIG. 2  is a schematic electrical circuit diagram illustrating a first voltage-to-time converter of the first preferred embodiment; 
         FIGS. 3   a  to  3   f  are timing diagrams illustrating a reference clock (CK 0 ), a first control signal (Q 1 ), a second control signal (Q bar1 ), a voltage (V C ) across a capacitor of the first voltage-to-time converter, an output signal (V G ) outputted by a comparator of the first voltage-to-time converter, and a first delay clock (CK 1 ) respectively; 
         FIG. 4  is a plot of experimental measurement results for illustrating relationships between an input voltage and a first time delay of the first delay clock at different operating temperatures under various fabrication conditions; 
         FIG. 5  is a schematic electrical circuit diagram illustrating a second voltage-to-time converter of the first preferred embodiment; 
         FIG. 6  is a schematic electrical circuit block diagram illustrating the second preferred embodiment of a voltage-to-digital converting device according to the present invention; 
         FIGS. 7   a  to  7   e  are timing diagrams illustrating the reference clock (CK 0 ), the first delay clock (CK 1 ), a second delay clock (CK 2 ), a third delay clock (CK 3 ), and a fourth delay clock (CK 4 ), respectively, in an example performed by the second preferred embodiment; 
         FIGS. 8 to 10  are schematic electrical circuit block diagrams illustrating operation of a time-to-digital converting circuit of the second preferred embodiment in the example; and 
         FIG. 11  is a schematic circuit block diagram illustrating another application of the second preferred embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure. 
     Referring to  FIG. 1 , the first preferred embodiment of a voltage-to-digital converting device according to the present invention is shown to be adapted for converting an input voltage (V in ) into a digital signal. The voltage-to-digital converting device includes a first voltage-to-time converter (VTC 1 ), a second voltage-to-time converter (VTC 2 ), and a time-to-digital converting circuit  3 . 
     The first voltage-to-time converter (VTC 1 ) is adapted for receiving a reference clock (CK 0 ) and the input voltage (V in ), and outputs a first delay clock (CK 1 ) in response to the input voltage (V in ). The first delay clock (CK 1 ) has a first time delay (T delay ) relative to the reference clock (V in ) (see  FIG. 3   f ). The first time delay (T delay ) corresponds to the input voltage (V in ). Preferably, the first time delay (T delay)  of the first delay clock (CK 1 ) outputted by the first voltage-to-time converter (VTC 1 ) is proportional to the input voltage (V in ). 
     In this embodiment, referring further to  FIG. 2 , the first voltage-to-time converter (VCT 1 ) includes a series connection of a current source (I 0 ), a first switch (S 1 ) and a capacitor (C), a comparator (Com), a second switch (S 2 ), a first flip-flop (F 1 ), and a second flip-flop (F 2 ). The first switch (S 1 ) has a control end for receiving a first control signal (Q 1 ) such that the first switch (S 1 ) is operable between an ON-state and an OFF-state in response to the first control signal (Q 1 ). The comparator (Com) has a non-inverting input end serving as a first input end and coupled to a common node (n) of the first switch (S 1 ) and the capacitor (C), an inverting input end serving as a second input end and adapted for receiving the input voltage (V in ), and an output end for outputting an output signal (V G ). The second switch (S 2 ) is adapted to be coupled between the non-inverting input end of the comparator (Com) and a reference voltage source (not shown) supplying a reference voltage (V ref ) that is less than the input voltage (V in ), and has a control end for receiving a second control signal (Q bar1 ) such that the second switch (S 2 ) is operable between an ON-state and an OFF-state in response to the second control signal (Q bar1 ). The first flip-flop (F 1 ) has a high-level data input (D), a clock input adapted for receiving the reference clock (CK 0 ), a clear input (CLR) coupled to the output end of the comparator (Com), a data output (Q) coupled to the control end of the first switch (S 1 ) and outputting the first control signal (Q 1 ) to the control end of the first switch (S 1 ), and an inverted data output (  Q ) coupled to the control end of the second switch (S 2 ) and outputting the second control signal (Q bar1 ) to the control end of the second switch (S 2 ). The second flip-flop (F 2 ) has a low-level data input (D), a clock input adapted for receiving the reference clock (CK 0 ), a set input (SET) coupled to the output end of the comparator (Com), and a data output (Q) for outputting the first delay clock (CK 1 ). 
     Referring further to  FIGS. 3   a  to  3   f , operation of the first voltage-to-time converter (VCT 1 ) is described hereinbelow.  FIG. 3   a  illustrates the reference clock (CK 0 ).  FIG. 3   b  illustrates the first control signal (Q 1 ) outputted at the data output (Q) of the first flip-flop (F 1 ).  FIG. 3   c  illustrates the second control signal (Q bar1 ) outputted at the inverted data output (  Q ) of the first flip-flop (F 1 ).  FIG. 3   d  illustrates a voltage (V C ) across the capacitor (C).  FIG. 3   e  illustrates the output signal (V G ) outputted at the output end of the comparator (Com).  FIG. 3   f  illustrates the first delay clock (CK 1 ) outputted at the data output (Q) of the second flip-flop (F 2 ). 
     When the reference clock (CK 0 ) is switched from a low level to a high level, the first control signal (Q 1 ) outputted at the data output (Q) of the first flip-flop (F 1 ) has a high level such that the first switch (S 1 ) is in the ON-state, and the second control signal (Q bar1 ) outputted at the inverted data output (  Q ) of the first flip-flop (F 1 ) has a low level such that the second switch (S 2 ) is in the OFF-state. In this case, the capacitor (C) is charged through the first switch (S 1 ) with a current supplied by the current source (I 0 ), as shown in  FIG. 3   d . Thereafter, when the voltage (V C ) across the capacitor (C) is greater than the input voltage (V in ), the output signal (V G ) outputted at the output end of the comparator (Com) is switched to a high level, as shown in  FIG. 3   e . In this case, the first control signal (Q 1 ) is switched from the high level to a low level such that the first switch (S 1 ) is in the OFF-state, and the second control signal (Q bar1 ) outputted at the inverted data output (  Q ) of the first flip-flop (F 1 ) is switched from the low level to the high level such that the second switch (S 2 ) is in the ON-state. On the other hand, the first delay clock (CK 1 ) is switched from a low level to a high level. Due to conduction of the second switch (S 2 ), the voltage (V C ) across the capacitor (C) is pulled down to the reference voltage (V ref ) such that the output signal (V G ) outputted at the output end of the comparator (Com) is pulled down to a low level. The first delay clock (CK 1 ) remains at the high level prior to a next rising edge of the reference clock (CK 0 ). Therefore, as shown in  FIG. 3   f , the first delay clock (CK 1 ) has the first time delay (T delay ) relative to the reference clock (CK 0 ). 
     In this embodiment, the current supplied by the current source (I 0 ) is a constant current (I const ), and the capacitor (C) has a constant capacitance (C const ). Thus, a quantity (Q C ) of electric charges accumulated in the capacitor (C) is represented as follows:
 
 Q   C   =I   const   ·T   delay   =C   const   ·V   in  
 
 V   in =( I   const   /C   const )· T   delay     V   in   ∝T   delay  
 
Therefore, the first voltage-to-time converter (VCT 1 ) has linear conversion characteristics.
 
       FIG. 4  illustrates relationships between the input voltage (V in ) and the first time delay (T delay ) of the first delay clock (CK 1 ) at different operating temperatures under various fabrication conditions, wherein “ss0” indicates a linear relationship at an operating temperature of 0° C. under a worst fabrication condition, “ss80” indicates a linear relationship at an operating temperature of 80° C. under the worst fabrication condition, “tt0” indicates a linear relationship at the operating temperature of 0° C. under a normal fabrication condition, “tt80” indicates a linear relationship at the operating temperature of 80° C. under the normal fabrication condition, “ff0” indicates a linear relationship at the operating temperature of 0° C. under a best fabrication condition, and “ff80” indicates a linear relationship at the operating temperature of 80° C. under the best fabrication condition. 
     The second voltage-to-time converter (VTC 2 ) is adapted for receiving the reference clock (CK 0 ) and a feedback voltage (V fb ), and outputs a second delay clock (CK 2 ) in response to the feedback voltage (V fb ). The second delay clock (CK 2 ) has a second time delay relative to the reference clock (CK 0 ). The second time delay corresponds to the feedback voltage (V fb ). Preferably, the second time delay of the second delay clock (CK 2 ) outputted by the second voltage-to-time converter (VTC 2 ) is proportional to the feedback voltage (V fb ). 
     In this embodiment, referring further to  FIG. 5 , the second voltage-to-time converter (VTC 2 ) has the same configuration as that of the first voltage-to-time converter (VCT 1 ). The second voltage-to-time converter (VTC 2 ) differs from the first voltage-to-time converter (VCT 1 ) in that the inverting input end of the comparator (Com) receives the feedback voltage (V fb ). Since the first and second voltage-to-time converters (VCT 1 , VTC 2 ) have the same configuration, an error of device parameters for each of the first and second voltage-to-time converters (VCT 1 , VTC 2 ) caused by fluctuation of an external voltage source or temperature variation can be canceled or compensated. 
     It is noted that, in other embodiments, the input voltage (V in ) is not required to be constant, and can be a biomedical signal that has slow and small fluctuations. 
     The time-to-digital converting circuit  3  is coupled to the first and second voltage-to-time converters (VTC 1 , VTC 2 ) for receiving the first and second delay clocks (CK 1 , CK 2 ) therefrom, compares phases of the first and second delay clocks (CK 1 , CK 2 ), generates the feedback voltage (V fb ) based on result of phase comparison made thereby, and outputs the digital signal upon detecting that the phases of the first and second delay clocks (CK 1 , CK 2 ) are in-phase. 
     In this embodiment, as shown in  FIG. 1 , the time-to-digital converting circuit  3  includes a time-to-digital converter  31  and a digital-to-analog converter  32 . 
     The time-to-digital converter  31  includes a phase detector  311  and a controller  312 . The phase detector  311  is coupled to the first and second voltage-to-time converters (VTC 1 , VTC 2 ) for receiving the first and second delay clocks (CK 1 , CK 2 ) therefrom, detects and compares the phases of the first and second delay clocks (CK 1 , CK 2 ), and outputs a comparison result. The controller  312  is coupled to the phase detector  311 , and outputs a digital output based on the comparison result from the phase detector  311 . 
     The digital-to-analog converter  32  is coupled to the controller  312  of the time-to-digital converter  31  for receiving the digital output therefrom, converts the digital output from the controller  312  into the feedback voltage (V fb ), and outputs the feedback voltage (V fb ) to the second voltage-to-time converter (VTC 2 ). 
     The controller  312  of the time-to-digital converter  31  outputs the digital output that serves as the digital signal when the phase detector  311  detects that the phases of the first and second delay clocks (CK 1 , CK 2 ) are in-phase. It is noted that, in this embodiment, the controller  312  is configured to increase a value of the digital output when the phase detector  311  detects that the phase of the second delay clock (CK 2 ) leads that of the first delay clock (CK 1 ), and to decrease the value of the digital output when the phase detector  311  detects that the phase of the second delay clock (CK 2 ) lags that of the first delay clock (CK 1 ). 
       FIG. 6  illustrates the second preferred embodiment of a voltage-to-digital converting device according to this invention, which is a modification of the first preferred embodiment. In this embodiment, the voltage-to-digital converting device is adapted for converting a difference between first and second voltages (V 1 , V 2 ) into a digital signal. 
     Unlike the first preferred embodiment, the first voltage-to-time converter (VCT 1 ) outputs the first delay clock (CK 1 ) in response to the first voltage (V 1 ), and the second voltage-to-time converter (VTC 2 ) outputs the second delay clock (CK 2 ) in response to the second voltage (V 2 ). The first time delay of the first delay clock (CK 1 ) outputted by the first voltage-to-time converter (VCT 1 ) is proportional to the first voltage (V 1 ). The second time delay of the second delay clock (CK 2 ) outputted by the second voltage-to-time converter (VTC 2 ) is proportional to the second voltage (V 2 ). 
     Furthermore, the time-to-digital converting circuit  4  outputs the digital signal in accordance with a difference between the phases of the first and second delay clocks (CK 1 , CK 2 ). The time-to-digital converting circuit  4  is configured to adjust continuously the phase of at least one of the first and second delay clocks (CK 1 , CK 2 ) until the phases of the first and second delay clocks (CK 1 , CK 2 ) are in-phase. The digital signal has a value associated with the number of times the phase of said at least one of the first and second delay clocks (CK 1 , CK 2 ) was adjusted. 
     In this embodiment, the time-to-digital converting circuit  4  includes a first delayer  43 , a second delayer  44 , a phase detector  41 , and a controller  42 . 
     The first delayer  43  is coupled to the first voltage-to-time converter (VCT 1 ) for receiving the first delay clock (CK 1 ) therefrom, is operable so as to delay the phase of the first delay clock (CK 1 ) in response to a first control signal, and outputs a third delay clock (CK 3 ) having a time delay relative to the first delay clock (CK 1 ). 
     The second delayer  44  is coupled to the second voltage-to-time converter (VTC 2 ) for receiving the second delay clock (CK 2 ) therefrom, is operable so as to delay the phase of the second delay clock (CK 2 ) in response to a second control signal, and outputs a fourth delay clock (CK 4 ) having a time delay relative to the second delay clock (CK 2 ). 
     Each of the first and second delayers  43 ,  44  includes a series connection of delay components (d 1 -dn), and a multiplexer (M). For each of the first and second delayers  43 ,  44 , the series connection of the delay components (d 1 -dn) is coupled to a corresponding one of the first and second voltage-to-time converters (VTC 1 , VTC 2 ) for receiving a corresponding one of the first and second delay clocks (CK 1 , CK 2 ) therefrom. Each of the delay components (d 1 -dn) has an output. The multiplexer (M) of each of the first and second delayers  43 ,  44  has a plurality of input ends coupled respectively to the outputs of the delay components (d 1 -dn) of the corresponding one of the first and second delayers  43 ,  44 , a control end for receiving a corresponding one of the first and second control signals, and an output end for outputting a corresponding one of the third and fourth delay clocks (CK 3 , CK 4 ), and is operable to establish electrical connection between the output of one of the delay components (d 1 -dn) of the corresponding one of the first and delayers  43 ,  44  and the output end in response to the corresponding one of the first and second control signals. 
     The phase detector  41  is coupled to the output ends of the multiplexers (M) of the first and second delayers  43 ,  44  for receiving the third and fourth delay clocks (Ck 3 , CK 4 ) therefrom, detects and compares phases of the third and fourth delay clocks (Ck 3 , CK 4 ), and outputs a comparison result. 
     The controller  42  is coupled to the phase detector  41  and to the control ends of the multiplexers (M) of the first and second delayers  43 ,  44 , receives the comparison result from the phase detector  41 , outputs respectively the first and second control signal to the control ends of the multiplexers (M) of the first and second delayers  43 ,  44  in response to the comparison result so as to bring the phases of the third and fourth delay clocks (Ck 3 , CK 4 ) closer to each other, and outputs the digital signal when the comparison result indicates that the phases of the third and fourth delay clocks (Ck 3 , CK 4 ) are in-phase. 
     Referring further to  FIGS. 7   a  to  7   e , and  8  to  10 , an example performed by the voltage-to-digital converting device of the second preferred embodiment is described hereinbelow, wherein a difference between the phases of the first and second delay clocks (CK 1 , CK 2 ) outputted by the first and second voltage-to-time converters (VTC 1 , VTC 2 ) is four time delay units (see  FIGS. 7   b  and  7   c ), and each of the delay components (d 1 -dn) delays a signal inputted thereto by one time delay unit. 
     Initially, during a first clock of the reference clock (CK 0 ), the controller  42  outputs respectively predetermined first and second control signals to the multiplexers (M) of the first and second delayers  43 ,  44  such that each of the multiplexers (M) of the first and second delayers  43 ,  44  is operable to establish electrical connection between the delay component (d 3 ) and the phase detector  41  in response to a corresponding one of the predetermined first and second control signals, as shown in  FIG. 8 . Thus, the phase detector  41  detects that a difference between phases of the third and fourth delay clocks (CK 3 , CK 4 ) outputted by the first and second delayers  43 ,  44  is still four time delay units (see  FIGS. 7   d  and  7   e ). 
     Then, during a second clock of the reference clock (CK 0 ), the controller  42  updates the first and second control signals in response to the comparison result from the phase detector  41 , and outputs the first and second control signals updated thereby to the multiplexers (M) of the first and second delayers  43 ,  44  such that the multiplexer (M) of the first delayer  43  is operable to establish electrical connection between the delay component (d 4 ) and the phase detector  41  in response to the updated first control signal and that the multiplexer (M) of the second delayer  44  is operable to establish electrical connection between the delay component (d 2 ) and the phase detector  41  in response to the updated second control signal, as shown in  FIG. 9 . In this case, the phase detector  41  detects that the difference between the phases of the third and fourth delay clocks (CK 3 , CK 4 ) outputted by the first and second delayers  43 ,  44  becomes two time delay units (see  FIGS. 7   d  and  7   e ). At the same time, the value of the digital signal is added by 2. 
     Thereafter, during a third clock of the reference clock (CK 0 ), the controller  42  updates the first and second control signals once again in response to the comparison result from the phase detector  41 , and outputs the first and second control signals updated thereby to the multiplexers (M) of the first and second delayers  43 ,  44  such that the multiplexer (M) of the first delayer  43  is operable to establish electrical connection between the delay component (d 5 ) and the phase detector  41  in response to the updated first control signal and that the multiplexer (M) of the second delayer  44  is operable to establish electrical connection between the delay component (d 1 ) and the phase detector  41  in response to the updated second control signal, as shown in  FIG. 10 . In this case, the phase detector  41  detects that the phases of the third and fourth delay clocks (CK 3 , CK 4 ) outputted by the first and second delayers  43 ,  44  are in-phase (see  FIGS. 7   d  and  7   e ). At the same time, the value of the digital signal is added by 2. Finally, the controller  42  outputs the digital signal. 
       FIG. 11  illustrates another application of the second preferred embodiment, wherein a differential voltage pair (V in+ , V in− ) serves as the first and second voltages. 
     In sum, due to the inclusion of the first and second voltage-to-time converters (VCT 1 , VTC 2 ) having the same configuration and linear operation characteristics, an adverse effect caused by a drift of fabrication process, voltage variation or temperature variation can be compensated. 
     While the present invention has been described in connection with what are considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.