Patent Publication Number: US-8969845-B2

Title: Memory cells having storage elements that share material layers with steering elements and methods of forming the same

Description:
REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 13/783,585, filed Mar. 4, 2013, which is a continuation of U.S. patent application Ser. No. 12/905,047, filed Oct. 14, 2010, now U.S. Pat. No. 8,389,971, each of which is incorporated by reference herein in its entirety for all purposes. 
     This application is related to the following U.S. patent applications, each of which is hereby incorporated by reference herein in its entirety: 
     U.S. patent application Ser. No. 12/904,770, filed Oct. 14, 2010, and titled “Bipolar Storage Elements For Use In Memory Cells And Methods Of Forming The Same;” and 
     U.S. patent application Ser. No. 12/904,802, filed Oct. 14, 2010, and titled “Multi-Level Memory Arrays With Memory Cells That Employ Bipolar Storage Elements And Methods Of Forming The Same.” 
    
    
     BACKGROUND 
     The present invention relates to memory arrays, and more particularly to memory cells having storage elements that share material layers with steering elements and methods of forming the same. 
     Non-volatile memories formed from reversible resistivity-switching materials are known. For example, U.S. patent application Ser. No. 11/125,939, filed May 9, 2005 and titled “Rewriteable Memory Cell Comprising A Diode And A Resistance-Switching Material” (hereinafter “the &#39;939 application”), which is hereby incorporated by reference herein in its entirety, describes a rewriteable non-volatile memory cell that includes a diode coupled in series with a reversible resistivity-switching material such as a metal oxide or metal nitride. 
     However, fabricating memory devices from rewriteable resistivity-switching materials is difficult; and improved methods of forming memory devices that employ resistivity-switching materials are desirable. 
     SUMMARY 
     In a first aspect of the invention, a memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. 
     In a second aspect of the invention, a monolithic three-dimensional memory array is provided that includes a first memory level monolithically formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a plurality of memory cells, wherein each memory cell includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. 
     In a third aspect of the invention, a non-volatile memory is provided that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. Each of the memory cells includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. 
     Other features and aspects of this invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIGS. 1A-1N  are cross-sectional views of exemplary bipolar storage elements provided in accordance with the present invention. 
         FIG. 2A  is a schematic illustration of an exemplary memory cell in accordance with this invention. 
         FIG. 2B  is a simplified perspective view of another exemplary embodiment of a memory cell in accordance with this invention. 
         FIG. 2C  is a simplified perspective view of yet another exemplary embodiment of a memory cell in accordance with this invention. 
         FIG. 2D  is a simplified perspective view of a portion of a first memory level formed from a plurality of memory cells in accordance with this invention. 
         FIG. 2E  is a simplified perspective view of a portion of a first monolithic three dimensional memory array that includes a first memory level positioned below a second memory level in accordance with the present invention. 
         FIG. 2F  is a simplified perspective view of a portion of a second monolithic three dimensional memory array that includes a first memory level positioned below a second memory level in accordance with the present invention. 
         FIGS. 3A-3F  are cross sectional views of exemplary memory cell stacks provided in accordance with the present invention. 
         FIG. 4A  is a schematic diagram of another exemplary three dimensional memory array provided in accordance with the present invention. 
         FIG. 4B  illustrates exemplary timing diagrams for resetting memory cells simultaneously in accordance with the present invention. 
         FIG. 4C  illustrates exemplary timing diagrams for setting memory cells simultaneously in accordance with the present invention. 
         FIGS. 5A-5C  are cross sectional views of first exemplary memory cell stacks in which storage elements and steering elements may share a material layer in accordance with the present invention. 
         FIGS. 6A-6C  are cross sectional views of second exemplary memory cell stacks in which storage elements and steering elements may share a material layer in accordance with the present invention. 
         FIGS. 7A-7D  are cross sectional views of third exemplary memory cell stacks in which storage elements and steering elements may share a material layer in accordance with the present invention. 
         FIGS. 8A-8D  are cross sectional views of fourth exemplary memory cell stacks in which storage elements and steering elements may share a material layer in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     A metal-insulator-metal (“MIM”) stack formed from a reversible resistivity-switching (“RRS”) material sandwiched between two metal or otherwise conducting layers may serve as a resistance-switching element for a memory cell. The two conducting layers may serve as the top and bottom electrodes of the resistance-switching element, and may be used to apply an electric field across the RRS material that changes the resistivity of the RRS material from a high value to a low value and vice versa. 
     Unipolar MIM stacks employ similar materials on each side of the RRS material, such as the same or similar electrode materials, and generally operate the same independent of which electrode is biased positively or negatively. For some RRS materials, such as metal oxides, unipolar MIM stacks may not switch reliably and may suffer from low yield (e.g., due to set and reset operations being performed using the same voltage polarity with little separation between the set and reset voltages). As such, some unipolar MIM stacks may be unsuitable for use in memory cells and memory arrays. 
     Bipolar MIM stacks may be more reliable than unipolar MIM stacks because bipolar MIM stacks employ set and reset voltages that have opposite polarities. However, bipolar MIM stacks may require large forming voltages to initiate reliable switching. 
     In accordance with embodiments of the present invention, bipolar MIM stacks are provided that exhibit improved switching properties and that may be fabricated using conventional fabrication techniques. Methods of forming such bipolar MIM stacks, as well as methods of employing such bipolar MIM stacks in three-dimensional (“3D”) memory arrays, are also provided. 
     These and other embodiments of the invention are described below with reference to  FIGS. 1A-4C . 
     Exemplary MIM Stacks 
       FIGS. 1A-1N  are cross-sectional views of exemplary bipolar storage elements  100   a - k  provided in accordance with the present invention. Exemplary process details for forming such bipolar storage elements are described below with reference to  FIGS. 3A-3F . 
     Each bipolar storage element  100   a - k  takes the form of an MIM stack  102   a - k  that includes an RRS material  104  sandwiched between a top electrode  106  and a bottom electrode  108 . One or more additional layers  110  such as a metal layer, a metal oxide layer, a metal/metal oxide layer stack, or the like, may be employed within MIM stack  102   a - k  as described further below. 
     Each MIM stack  102   a - k  exhibits bipolar switching due to differences between top electrode  106 /RRS material  104  interface and bottom electrode  108 /RRS material  104  interface (e.g., differences in work function, electron affinity, oxygen affinity, interfacial layers, etc.). Such bipolar MIM stacks preferentially set with one voltage polarity applied between top and bottom electrodes  106  and  108 , and preferentially reset with the opposite voltage polarity applied between top and bottom electrodes  106  and  108 . 
     In some embodiments, MIM stacks  102   a - k  also may be asymmetrical, with different numbers, types and/or thicknesses of materials on either side of RRS material  104 . 
     RRS material  104  may include, for example, HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X , Al X O Y , another metal oxide (“MO X ”) layer, or another suitable switching material. In some embodiments, top electrode  106  may include titanium nitride, tantalum nitride, tungsten nitride, combinations of the same, a metal/metal nitride stack such as Ti/TiN, Ta/TaN, W/WN or another similar layer; and bottom electrode  108  may include heavily doped semiconductor such as n+ silicon or p+ silicon, heavily doped germanium, heavily doped silicon-germanium, etc. 
     In other embodiments, top electrode  106  may include heavily doped semiconductor such as n+ silicon or p+ silicon, heavily doped germanium, heavily doped silicon-germanium, etc.; and bottom electrode  108  may include titanium nitride, tantalum nitride, tungsten nitride, combinations of the same, a metal/metal nitride stack such as Ti/TiN, Ta/TaN, W/WN or another similar layer. Other materials and/or configurations may be used for top and/or bottom electrodes  106  and  108 . 
     In some embodiments, additional layer(s)  110  may include, for example, titanium, titanium oxide, tantalum, tantalum oxide, tungsten, tungsten oxide, etc. In yet other embodiments, additional layer(s)  110  may include a metal/metal oxide layer stack such as Ti/TiO X , Zr/ZrO X , Ni/NiO X , Al/Al X O Y , Ta/TaO X , Nb/NbO X , Hf/HfO X , or any suitable layer stack. 
     Operation of the bipolar MIM stacks of the present invention is now described. Referring to  FIGS. 1A-1B , bipolar MIM stack  100   a  may reside in either a low resistance or “set” state ( FIG. 1A ) or a high resistance or “reset” state ( FIG. 1B ). While not wishing to be bound by any particular theory, it is believed that RRS material  104  may have its resistivity modulated by the creation and/or elimination of oxygen vacancies  112  within RRS material  104 . In some embodiments, when a sufficient number of oxygen vacancies  112  are present within RRS material  104 , conductive paths or filaments may extend across the entire width of RRS material  104  (as shown in  FIG. 1A ) and may create a low resistance path through RRS material  104 . 
     Likewise, oxygen vacancies may be eliminated from RRS material  104  to eliminate conductive paths or filaments that extend across RRS material  104  (as shown in  FIG. 1B ) and increase the resistance of any path through RRS material  104 . In other embodiments, conductive paths or filaments may not actually be formed, and merely an increase in oxygen vacancy density may decrease RRS material resistivity while a decrease in oxygen vacancy density may increase RRS material resistivity. 
     When first formed, RRS material  104  is typically in a high resistivity state and a forming voltage is applied to place RRS material  104  in a condition that can be modulated by application of set and reset voltages of the appropriate polarity (as described further below). The forming voltage is typically significantly larger than the set or reset voltages (e.g., about 14-16 volts versus about 7-10 volts). While not wishing to be bound by any particular theory, application of the forming voltage may create a baseline number of oxygen vacancies within RRS material  104 , and the number of oxygen vacancies within RRS material  104  may be modulated about this baseline number via application of set and reset voltages to modulate the resistivity of RRS material  104 . 
     In embodiments of the present invention, additional layer(s)  110  is believed to “getter” oxygen ions from RRS material  104  during a set operation ( FIG. 1A ), creating oxygen vacancies  112  within RRS material  104  as the oxygen ions leave RRS material  104  and travel to additional layer(s)  110 . This causes RRS material  104  to switch to a low resistivity state. Likewise, additional layer(s)  110  is believed to seed oxygen ions to RRS material  104  during a reset operation ( FIG. 1B ), passivating oxygen vacancies within RRS material  104  as oxygen ions travel from additional layer(s)  110  to RRS material  104 . This causes RRS material  104  to switch to a high resistivity state. 
     As used herein, a bipolar MIM stack that employs a positive voltage applied to its top electrode relative to its bottom electrode during a set operation is referred to as having a “positive polarity” or a “positive polarity orientation.” Likewise, a bipolar MIM stack that employs a negative voltage applied to its top electrode relative to its bottom electrode during a set operation is referred to as having a “negative polarity” or a “negative polarity orientation.” 
     MIM stack  102   a  is an example of a “positive polarity” MIM stack. For example, to set MIM stack  102   a  to a low resistance state, a positive voltage is applied to top electrode  106  relative to bottom electrode  108 . This may cause negative oxygen ions (O—) within RRS material  104  to travel toward additional layer(s)  110 . As the oxygen ions leave RRS material  104 , oxygen vacancies  112  are formed within RRS material  104 , lowering the resistivity of RRS material  104  and in some cases creating one or more conductive paths or filaments within RRS material  104  as shown in  FIG. 1A . 
     To reset MIM stack  102   a  to a high resistance state, the opposite voltage polarity is applied to top electrode  106  relative to bottom electrode  108 , which may cause oxygen ions to travel from additional layer(s)  110  to RRS material  104 . This may passivate oxygen vacancies in RRS material  104 , in some cases break conduction paths or filaments that extend across RRS material  104 , and increase the resistivity of RRS material  104 . 
       FIGS. 1C-1D  illustrate a “negative polarity” MIM stack  102   b  in which the positions of RRS material  104  and additional layer(s)  110  are reversed. As will be described below, the top and bottom electrode materials also may be reversed. MIM stack  102   b  is set by applying a negative voltage polarity to top electrode  106  relative to bottom electrode  108  ( FIG. 1C ); and reset by applying a positive voltage polarity to top electrode  106  relative to bottom electrode  108  ( FIG. 1D ). Additional MIM stacks provided in accordance with the present invention are now described with reference to  FIGS. 1E-1N . 
       FIG. 1E  illustrates a cross-sectional view of a third exemplary bipolar storage element  100   c  (MIM stack  102   c ) having a bottom metal nitride electrode  108 , a metal or metal oxide layer  110  formed above bottom electrode  108 , RRS material  104  formed above the metal or metal oxide layer  110 , and a top heavily doped semiconductor electrode  106  formed above RRS material  104 . 
     To “set” MIM stack  102   c  to a low resistance state, a negative voltage is applied to top electrode  106  relative to bottom electrode  108 . Likewise, to “reset” MIM stack  102   c  to a high resistance state, a positive voltage is applied to top electrode  106  relative to bottom electrode  108 . 
     In general, bottom electrode  108  may include, for example, titanium nitride, tantalum nitride, tungsten nitride, combinations of the same, a metal/metal nitride stack such as Ti/TiN, Ta/TaN, W/WN or another similar barrier layer. Metal or metal oxide layer  110  may include, for example, titanium, titanium oxide, tantalum, tantalum oxide, tungsten, tungsten oxide, or another similar layer. RRS material  104  may include, for example, HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X  or Al X O Y  or another suitable switching material. Top electrode  106  may include heavily doped silicon such as n+ silicon or p+ silicon, heavily doped germanium, heavily doped silicon-germanium, etc. 
       FIG. 1F  illustrates a particular exemplary embodiment of MIM stack  102   c , referred to as MIM stack  102   d  in  FIG. 1F , in which bottom electrode  108  is titanium nitride, metal or metal oxide layer  110  is titanium or titanium oxide, RRS material  104  is hafnium oxide and top electrode  106  is n+ silicon. 
     For example, bottom electrode  108  (TiN) may have a thickness of about 10-60 nanometers, and in some embodiments about 20 nanometers. Ti or TiO X  layer  110  may have a thickness of about 0.5-10 nanometers, and in some embodiments about 4 nanometers. When TiO X  is employed, x may be about 1.2-2, and in some embodiments about 1.5. Hafnium oxide layer  104  may have a thickness of about 3-12 nanometers, and in some embodiments about 5 nanometers, with x being about 1.2-2.0 and in some embodiments about 1.7. 
     N+ silicon layer  106  may have a thickness of about 10-100 nanometers, and in some embodiments about 20 nanometers. The doping concentration of n+ silicon layer  106  may be about 5×10 19 -5×10 21  atoms/cm 3  and in some embodiments about 2×10 20  atoms/cm 3 . Other film thicknesses, x values and/or doping concentrations may be used. MIM stack  102   d  is set and reset using the same voltage polarities described above for MIM stack  102   c.    
       FIGS. 1G-1H  illustrate additional MIM stacks  102   e  and  102   f  which represent “inverted” versions of MIM stacks  102   c  and  102   d , respectively. Specifically, the order of the material layers in MIM stack  102   e  is reversed relative to MIM stack  102   c , and the order of the material layers in MIM stack  102   f  is reversed relative to MIM stack  102   d . MIM stacks  102   e  and  102   f  are “set” to a low resistance state by applying a positive voltage to top electrode  106  relative to bottom electrode  108 . Likewise, to “reset” MIM stack  102   e  or  102   f  to a high resistance state, a negative voltage is applied to top electrode  106  relative to bottom electrode  108 . 
       FIG. 1I  illustrates a cross-sectional view of another exemplary bipolar storage element  100   g  (MIM stack  102   g ) having a bottom metal nitride electrode  108 , a metal/metal oxide layer stack  110  including metal oxide layer  110   a  and metal layer  110   b  formed above bottom electrode  108 , RRS material  104  formed above metal/metal oxide layer stack  110 , and a top heavily doped semiconductor electrode  106  formed above RRS material  104 . 
     While not wishing to be bound by any particular theory, in such an arrangement, metal layer  110   b  is believed to “getter” oxygen ions from RRS material  104  during a set operation, creating oxygen vacancies within RRS material  104  as the oxygen ions leave RRS material  104  and travel to metal layer  110   b  and allowing RRS material  104  to switch to a low resistivity state. 
     Likewise, metal oxide layer  110   a  is believed to seed oxygen ions to RRS material  104  during a reset operation, passivating oxygen vacancies within RRS material  104  as oxygen ions travel from metal oxide layer  110   a  to RRS material  104  and allowing RRS material  104  to switch to a high resistivity state. In some embodiments, metal oxide layer  110   a  may serve as a buffer layer and reduce damage to interface(s) of RRS material  104  due to the strong gettering properties of metal layer  110   b  during multiple switching operations. 
     To “set” MIM stack  100   g  to a low resistance state, a negative voltage is applied to top electrode  106  relative to bottom electrode  108 . Likewise, to “reset” MIM stack  100   g  to a high resistance state, a positive voltage is applied to top electrode  106  relative to bottom electrode  108 . 
     In general, bottom electrode  108  may include, for example, titanium nitride, tantalum nitride, tungsten nitride, combinations of the same, a metal/metal nitride stack such as Ti/TiN, Ta/TaN, W/WN or another similar barrier layer. Metal/metal oxide layer stack  110  may include, for example, Ti/TiO X , Zr/ZrO X , Ni/NiO X , Al/Al X O Y , Ta/TaO X , Nb/NbO X , Hf/HfO X  or another similar layer stack. RRS material  104  may include, for example, HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X  or Al X O Y  or another suitable switching material. Top electrode  106  may include n+ silicon, p+ silicon, heavily doped germanium, heavily doped silicon-germanium, etc. 
     In some embodiments, metal/metal-oxide layer stack  110  may be formed from a different material than is employed for RRS material  104 . For example, a Ti/TiO X  layer stack may be employed with a HfO X , ZrO X , NiO X , TaO X , NbO X  or Al X O Y  switching material. A Zr/ZrO X  layer stack may be used with a HfO X , NiO X , TiO X , TaO X , NbO X  or Al X O Y  switching material. 
     A Ni/NiO X  layer stack may be used with a HfO X , ZrO X , TiO X , TaO X , NbO X  or Al X O Y  switching material. An Al/Al X O Y  layer stack may be employed with a HfO X , ZrO X , NiO X , TiO X , TaO X , or NbO X  switching material. A Ta/TaO X  layer stack may be employed with a HfO X , TiO X , ZrO X , NiO X , NbO X  or Al X O Y  switching material. A Nb/NbO X  layer stack may be employed with a HfO X , TiO X , ZrO X , NiO X , TaO X  or Al X O Y  switching material. A Hf/HfO X  layer stack may be employed with a NbO X , TiO X , ZrO X , NiO X , TaO X  or Al X O Y  switching material. 
     In other embodiments, metal/metal oxide layer stack  110  may be formed from a similar material to that employed for RRS material  104 . For example, a Ti/TiO X  layer stack may be employed with a TiO X  switching layer. However, in such embodiments, the metal oxide of the layer stack may have a different crystalline structure or other property compared to that of the switching material (e.g., amorphous versus crystalline structure). 
     It is believed that the metal oxide layer of metal/metal-oxide layer stack  110  may serve as a “buffer” layer that allows formation/elimination of oxygen vacancies within the switching material to be more controllable and/or repeatable, which may improve the endurance/longevity of the switching material. 
       FIG. 1J  illustrates a particular exemplary embodiment of MIM stack  102   g , referred to as MIM stack  102   h  in  FIG. 1J , in which bottom electrode  108  is titanium nitride, metal/metal oxide layer stack  110  is titanium oxide over titanium, RRS material  104  is hafnium oxide and top electrode  106  is n+ silicon. 
     For example, bottom electrode  108  (TiN) may have a thickness of about 10-60 nanometers, and in some embodiments about 20 nanometers. Ti layer  110   b  may have a thickness of about 0.5-10 nanometers, and in some embodiments about 4 nanometers. TiO X  layer  110   a  may have a thickness of about 0.5-6 nanometers, and in some embodiments about 1 nanometer; and x may be about 1.2-2.0 and in some embodiments about 1.5. Hafnium oxide layer  104  may have a thickness of about 3-12 nanometers, and in some embodiments about 5 nanometers; and x may be about 1.2-2 and in some embodiments about 1.7. 
     N+ silicon layer  106  may have a thickness of about 10-100 nanometers, and in some embodiments about 20 nanometers. The doping concentration of n+ silicon layer  106  may be about 5×10 19 -5×10 21  atoms/cm 3  and in some embodiments about 2×10 20  atoms/cm 3 . Other film thicknesses, x values and/or doping concentrations may be used. MIM stack  102   h  is set and reset using the same polarities described above for MIM stack  102   g.    
       FIGS. 1K-1L  illustrate additional MIM stacks  102   i  and  102   j  which represent “inverted” versions of MIM stacks  102   g  and  102   h , respectively. Specifically, the order of the material layers in MIM stack  102   i  is reversed relative to MIM stack  102   g , and the order of the material layers in MIM stack  102   j  is reversed relative to MIM stack  102   h . MIM stacks  102   i  and  102   j  are “set” to a low resistance state by applying a positive voltage to top electrode  106  relative to bottom electrode  108 . Likewise, to “reset” MIM stack  102   i  or  102   j  to a high resistance state, a negative voltage is applied to top electrode  106  relative to bottom electrode  108 . 
       FIGS. 1M-1N  illustrate a particular embodiment of an MIM stack  102   k  similar to MIM stack  102   j  of  FIG. 1L . On test wafers having MIM stack  102   k , TEM images reveal a sharp interface between HfO X  and TiO X  layers  104  and  110   a . The interface between TiO X  and Ti layers  110   a  and  110   b  appears less sharp, with a mixture of amorphous and crystalline structures being observed in TiO X /Ti layer stack  110 . 
     For example, in some test samples, no pure Ti layer  110   b  appears to exist as oxygen may diffuse into Ti Layer  110   b , such as from TiO X  and/or HfO X  layers  110   a  and/or  104 , forming Ti rich islands  114  (e.g., metal rich regions surrounded by metal oxide). Nitrogen may also diffuse into TiO X  layer  110   a  and/or Ti layer  110   b  from TiN layer  106 . 
     Indeed, in some embodiments, a structure similar to MIM stack  102   k  of  FIG. 1M  and/or  FIG. 1N  has been observed when a thick (e.g., about 8 or more nanometers) Ti layer is deposited over HfO X  layer  104  without TiO X  layer, presumably due to oxygen diffusion into the Ti layer from HfO X  layer  104 . 
     While not wishing to be bound by any particular theory, in such an arrangement, Ti+ islands  114  of Ti layer  110   b  are believed to “getter” oxygen ions from RRS material  104  during a set operation, creating oxygen vacancies within RRS material  104  as the oxygen ions leave RRS material  104  and travel to Ti layer  110   b  and allowing RRS material  104  to switch to a low resistivity state ( FIG. 1M ). 
     Likewise, TiO X  layer  110   a  is believed to seed oxygen ions to RRS material  104  during a reset operation, passivating oxygen vacancies within RRS material  104  as oxygen ions travel from TiO X  layer  110   a  to RRS material  104  and allowing RRS material  104  to switch to a high resistivity state. Suitable values for forming, set and reset voltages for MIM stacks  102   a - k  depend on a number of factors such as the types and/or thicknesses of materials used. 
     In some embodiments, for MIM stacks that are positively oriented, a forming voltage of about +14 to +16 volts or more, a set voltage of about +9 to +11 volts, and/or a reset voltage of about −7 to −8 volts may be used. Likewise, for MIM stacks that are negatively oriented, a forming voltage of about −14 to −16 volts or more, a set voltage of about −9 to −11 volts, and/or a reset voltage of about +7 to +8 volts may be used. Any other suitable forming, set and/or reset voltages may be employed. 
     The above MIM stacks  102   a - k  were described as having low-resistance set states and high-resistance reset states. In other embodiments, MIM stacks  102   a - k  may have high resistance set states and low-resistance reset states. 
     Exemplary Inventive Memory Cell 
       FIG. 2A  is a schematic illustration of an exemplary memory cell  200  in accordance with this invention. Memory cell  200  includes MIM stack  102  coupled to a steering element  204 . MIM stack  102  includes RRS material  104  (not separately shown) which has a resistivity that may be reversibly switched between two or more states, as described previously with reference to  FIGS. 1A-1N . 
     Steering element  204  may include a thin film transistor, a diode, a metal-insulator-metal tunneling current device, a punch-through diode, a Schottky-diode or another similar steering element that exhibits non-ohmic conduction by selectively limiting the voltage across and/or the current flow through MIM stack  102 . In this manner, memory cell  200  may be used as part of a two or three dimensional memory array and data may be written to and/or read from memory cell  200  without affecting the state of other memory cells in the array. In some embodiments, steering element  204  may be omitted, and memory cell  200  may be used with a remotely located steering element. 
     Exemplary Embodiments of Memory Cells and Memory Arrays 
       FIG. 2B  is a simplified perspective view of an exemplary embodiment of memory cell  200  in accordance with this invention in which steering element  204  is a diode. Memory cell  200  includes MIM stack  102  (having RRS material  104 ) coupled in series with diode  204  between a first conductor  202   a  and a second conductor  202   b.    
     As described above with reference to  FIGS. 1A-1N , MIM stack  102  may serve as a reversible resistance-switching element for memory cell  200 . MIM stack  102  may be similar to any of MIM stacks  102   a - k  of  FIGS. 1A-1N , or any other suitable MIM stack, and may include a top conducting layer  106  and a bottom conducting layer  108  that surround RRS material  104  and serve as top and bottom electrodes for MIM stack  102 . One or more additional layers  110  such as a metal layer, a metal oxide layer, a metal/metal oxide layer stack, or the like, may be employed within MIM stack  102  as described previously. 
     In some embodiments, a barrier layer  206  may be formed between MIM stack  102  and diode  204 , and a barrier layer  208  may be formed between MIM stack  102  and second conductor  202   b . An additional barrier layer  210  may be formed between diode  204  and first conductor  202   a . Barrier layers  206 ,  208  and  210  may include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, molybdenum, combinations of the same, or another similar barrier layer. Barrier layer  208  may be separate from or part of second conductor  202   b  and barrier layer  210  may be separate from or part of first conductor  202   a.    
     Diode  204  may include any suitable diode such as a vertical polycrystalline p-n or p-i-n diode, whether upward pointing with an n-region above a p-region of the diode or downward pointing with a p-region above an n-region of the diode, a p-n-p or n-p-n punch through diode, a Schottky diode or the like. Exemplary embodiments of diode  204  are described below with reference to  FIGS. 3A-3D . 
     In the embodiment of  FIG. 2B , MIM stack  102  is positioned above diode  204 . However, as shown in  FIG. 2C , MIM stack  102  alternatively may be positioned below diode  204 . 
     First conductor  202   a  and/or second conductor  202   b  may include any suitable conductive material such as tungsten, any appropriate metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, a highly conductive carbon or the like. In the embodiment of  FIG. 2A , first and second conductors  202   a  and  202   b , respectively, are line or rail-shaped and extend in different directions (e.g., substantially perpendicular to one another). Other conductor shapes and/or configurations may be used. In some embodiments, barrier layers, adhesion layers, antireflection coatings and/or the like (not shown) may be used with first conductor  202   a  and/or second conductor  202   b  to improve device performance and/or aid in device fabrication. 
       FIG. 2D  is a simplified perspective view of a portion of a first memory level  212  formed from a plurality of memory cells  200 , such as memory cells  200  of  FIG. 2A  or  2 B. For simplicity, RRS material  104 , conductive layers  106  and  108 , additional layer(s)  110 , diode  204 , and barrier layers  206 ,  208  and  210  are not separately shown. Memory array  212  is a “cross-point” array including a plurality of bit lines (second conductors  202   b ) and word lines (first conductors  202   a ) to which multiple memory cells are coupled (as shown). Other memory array configurations may be used, as may multiple levels of memory. 
       FIG. 2E  is a simplified perspective view of a portion of a monolithic three dimensional memory array  214   a  that includes a first memory level  216  positioned below a second memory level  218 . Memory levels  216  and  218  each include a plurality of memory cells  200  in a cross-point array. Persons of ordinary skill in the art will understand that additional layers (e.g., an interlevel dielectric) may be present between first and second memory levels  216  and  218 , but are not shown in  FIG. 2E  for simplicity. Other memory array configurations may be used, as may additional levels of memory. 
     In the embodiment of  FIG. 2E , when a bipolar steering element such as a p-i-n diode is employed within each memory cell  200 , all diodes may “point” in the same direction (have the same “steering element” polarity orientation), such as upward or downward depending on whether p-i-n diodes having a p-doped region on the bottom or top of the diodes are employed, simplifying diode fabrication. 
     In accordance with this invention, all bipolar MIM stacks  102  also may have the same polarity orientation across all memory levels in memory array  214   a  of  FIG. 2E . That is, each MIM stack  102  in memory array  214   a  may be either positively oriented, such that a positive voltage is applied to each MIM stack  102 &#39;s top electrode relative to its bottom electrode during a set operation, or negatively oriented, such that a negative voltage is applied to each MIM stack  102 &#39;s top electrode relative to its bottom electrode during a set operation. This simplifies MIM stack fabrication. 
     In some embodiments, the memory levels may be formed as described in U.S. Pat. No. 6,952,030, titled “High-Density Three-Dimensional Memory Cell,” which is hereby incorporated by reference herein in its entirety for all purposes. For instance, the second (top) conductors of a first memory level may be used as the first (bottom) conductors of a second memory level that is positioned above the first memory level as shown in  FIG. 2F . 
     In such embodiments, the diodes on adjacent memory levels preferably point in opposite directions as described in U.S. patent application Ser. No. 11/692,151, filed Mar. 27, 2007 and titled “Large Array Of Upward Pointing P-I-N Diodes Having Large And Uniform Current” (the “&#39;151 application”), which is hereby incorporated by reference herein in its entirety for all purposes. 
     For example, as shown in memory array  214   b  in  FIG. 2F , the diodes of first memory level  216  may be upward pointing diodes as indicated by arrow D 1  (e.g., with p regions at the bottom of the diodes), whereas the diodes of second memory level  218  may be downward pointing diodes as indicated by arrow D 2  (e.g., with n regions at the bottom of the diodes), or vice versa. 
     In accordance with the present invention, in embodiments in which conductors are shared between memory levels as in  FIG. 2F , MIM stacks  102  are arranged to have the same voltage polarity orientation within a memory level, but opposite voltage polarity orientations between adjacent memory levels. 
     For example, MIM stacks  102  of first memory level  216  may be positively oriented whereas MIM stacks  102  of second memory level  218  may be negatively oriented, or vice versa. In some embodiments, diodes  204  may be oriented to be reverse biased during the set operations of MIM stacks  102 . Alternatively, diodes  204  may be oriented to be forward biased during the set operations of MIM stacks  102 . 
     A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates. The layers forming one memory level are deposited or grown directly over the layers of an existing level or levels. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, titled “Three Dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays. 
     Exemplary Stacked Memory Cells 
       FIG. 3A  is a cross sectional view of a first memory cell stack  300   a  provided in accordance with the present invention. Memory cell stack  300   a  includes a first memory cell  200 - 1  and a second memory cell  200 - 2  formed above first memory cell  200 - 1 . As shown in  FIG. 3A , first and second memory cells  200 - 1  and  200 - 2  share a common word line  302  that serves as both the top conducting rail of first memory cell  200 - 1  and the bottom conducting rail of second memory cell  200 - 2 . 
     In other embodiments, first and second memory cells  200 - 1  and  200 - 2  may share a bit line rather than a word line. Additional memory cells (not shown) may be provided at each memory level (e.g., to the left and/or right of memory cells  200 - 1  and/or  200 - 2 ) as described in  FIGS. 2D-F . 
     With reference to  FIG. 3A , first memory cell  200 - 1  includes a first MIM stack  102 - 1  coupled in series with a first diode  204 - 1  between bit line  202   a  and word line  302 . First MIM stack  102 - 1  has a positive polarity orientation such that a positive voltage applied to word line  302  relative to bit line  202   a  may be employed to set first MIM stack  102 - 1 . First diode  204 - 1  is oriented to be reverse biased during such a set operation. In other embodiments, first diode  204 - 1  may be oriented to be forward biased while a set operation is performed on first MIM stack  102 - 1 . 
     Second memory cell  200 - 2  includes a second MIM stack  102 - 2  coupled in series with a second diode  204 - 2  between word line  302  and bit line  202   b . Second MIM stack  102 - 2  has a negative polarity orientation such that a positive voltage applied to word line  302  relative to bit line  202   b  may be employed to set second MIM stack  102 - 2 . Second diode  204 - 2  is oriented to be reverse biased during such a set operation. In other embodiments, second diode  204 - 2  may be oriented to be forward biased while a set operation is performed on second MIM stack  102 - 2 . 
     As can be seen from  FIG. 3A , first MIM stack  102 - 1  has a first polarity orientation and second MIM stack  102 - 2  has a second, opposite polarity orientation relative to first MIM stack  102 - 1 . Likewise, first diode  204 - 1  has a first polarity orientation and second diode  204 - 2  has a second, opposite polarity orientation relative to first diode  204 - 1 . 
     First and second MIM stacks  102 - 1  and  102 - 2  may include any of MIM stacks  102   a - k  previously described, or any other suitable MIM stack and/or bipolar storage element. In  FIG. 3A , first and second MIM stacks  102 - 2  and  102 - 1  are shown as being similar to MIM stack  102   h  ( FIG. 1J ) and MIM stack  102   j  ( FIG. 1L ), respectively. 
     First and second diodes  204 - 1  and  204 - 2  may include any two terminal, non-linear steering element such as a p-n or p-i-n junction diode, a punch through diode, a tunneling oxide device, a Schottky diode, or the like. In  FIG. 3A , first and second diodes  204 - 1  and  204 - 2  are shown as being p-i-n junction diodes. When bipolar steering elements are employed in a shared conductor embodiment such as that of  FIG. 3A , the polarity of the diodes is alternated between memory levels as shown. However, when unipolar steering elements such as punch through diodes are employed, the diodes may be oriented the same between memory level as shown in the memory cell stack  300   b  of  FIG. 3B . 
     With reference to  FIG. 3A , first memory cell  200 - 1  includes bit line  202   a . Bit line  202   a  may be about 200 to about 2500 angstroms of any suitable conductive material such as tungsten or another appropriate metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the like. 
     In some embodiments, a plurality of bit lines  202   a  (see for example,  FIGS. 2D-F ) may be formed as substantially parallel, substantially co-planar bit lines  202   a . Exemplary widths for bit lines  202   a  and/or spacings between bit lines  202   a  range from about 200 to about 2500 angstroms, although other conductor widths and/or spacings may be used. Bit lines  202   a  may be separated from one another by dielectric material (not shown) such as silicon dioxide, silicon nitride, silicon oxynitride, low K dielectric, etc., and/or other dielectric materials. 
     Barrier layer  210  is formed over bit line  202   a . Barrier layer  210  may be about 20 to about 500 angstroms, and preferably about 100 angstroms, of titanium nitride or another suitable barrier layer such as tantalum nitride, tungsten nitride, tungsten, molybdenum, combinations of one or more barrier layers, barrier layers in combination with other layers such as titanium/titanium nitride, tantalum/tantalum nitride or tungsten/tungsten nitride stacks, or the like. Other barrier layer materials and/or thicknesses may be employed. 
     Semiconductor material used to form diode  204 - 1  is formed over barrier layer  210 . In the embodiment of  FIG. 3A , diode  204 - 1  is formed from a polycrystalline semiconductor material such as polysilicon, a polycrystalline silicon-germanium alloy, polygermanium or any other suitable material. 
     For example, a heavily doped amorphous or polycrystalline p+ silicon layer  204 - 1   a  may be deposited on barrier layer  210 . CVD or another suitable process may be employed to deposit p+ silicon layer  204 - 1   a . In at least one embodiment, p+ silicon layer  204 - 1   a  may be formed, for example, from about 100 to about 1000 angstroms, preferably about 100 angstroms, of p+ silicon with a doping concentration of about 10 21  cm −3 . Other layer thicknesses and/or doping concentrations may be used. P+ silicon layer  204 - 1   a  may be doped in situ, for example, by flowing an acceptor gas during deposition, or ex situ, for example, via implantation. 
     After deposition of p+ silicon layer  204 - 1   a , a lightly doped, intrinsic and/or unintentionally doped amorphous or polycrystalline silicon layer  204 - 1   b  may be formed over p+ silicon layer  204 - 1   a . CVD or another suitable deposition method may be employed to deposit intrinsic silicon layer  204 - 1   b . In at least one embodiment, intrinsic silicon layer  204 - 1   b  may be about 500 to about 4800 angstroms, preferably about 2500 angstroms, in thickness. Other intrinsic layer thicknesses may be used. 
     Additional silicon may be deposited and doped by ion implantation or doped in situ during deposition to form a n+ silicon layer  204 - 1   c . Further, in some embodiments, a diffusion process may be employed. In at least one embodiment, the resultant n+ silicon layer  204 - 1   c  may have a thickness of about 100 to about 1000 angstroms, preferably about 100 angstroms, with a doping concentration of about 10 21  cm −3 . Other layer thicknesses and/or doping concentrations may be used. 
     Following formation of n+ silicon layer  204 - 1   c , a silicide-forming metal layer stack  206  may be deposited over n+ silicon layer  204 - 1   c . Exemplary silicide-forming metals include sputter or otherwise deposited titanium or cobalt. In some embodiments, a silicide-forming metal layer stack  206  is formed from about 1-4 nanometers of titanium and about 15-25 nanometers of titanium nitride. Other silicide-forming metal layer materials and/or thicknesses may be used. 
     A rapid thermal anneal (“RTA”) step may be performed to form a silicide region by reaction of silicide-forming metal such as Ti with n+ region  204 - 1   c . In some embodiments, the RTA may be performed at about 540° C. for about 1 minute, to cause silicide-forming metal and the deposited silicon of diode  204  to interact to form a silicide layer, consuming all or a portion of the silicide-forming metal. 
     As described in U.S. Pat. No. 7,176,064, titled “Memory Cell Comprising A Semiconductor Junction Diode Crystallized Adjacent To A Silicide,” which is hereby incorporated by reference herein in its entirety for all purposes, silicide-forming materials such as titanium and/or cobalt react with deposited silicon during annealing to form a silicide layer. 
     The lattice spacing of titanium silicide and cobalt silicide are close to that of silicon, and it appears that such silicide layers may serve as “crystallization templates” or “seeds” for adjacent deposited silicon as the deposited silicon crystallizes (e.g., a silicide layer may enhance the crystalline structure of silicon diode  204 - 1  during annealing). Lower resistivity silicon thereby is provided. Similar results may be achieved for silicon-germanium alloy and/or germanium diodes. 
     Following formation of metal layer stack  206 , bottom electrode  108 - 1  of MIM stack  102 - 1  may be formed. For example, bottom electrode  108 - 1  may include heavily doped silicon such as n+ silicon or p+ silicon, heavily doped germanium, heavily doped silicon-germanium, etc. In the embodiment of  FIG. 3A , bottom electrode  108 - 1  may include n+ silicon having a thickness of about 10-100 nanometers, and in some embodiments about 20 nanometers. The doping concentration of the n+ silicon may be about 5×10 19 -5×10 21  atoms/cm 3  and in some embodiments about 2×10 20  atoms/cm 3 . Other film thicknesses and/or doping concentrations may be used. 
     Following formation of bottom electrode  108 - 1 , RRS material  104 - 1  may be formed by atomic layer deposition (“ALD”) or another suitable method. For example, RRS material  104 - 1  may include HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X , Al X O Y  or another suitable switching material. In the embodiment of  FIG. 3A , RRS material  104 - 1  may include HfO X  having a thickness of about 3-12 nanometers, and in some embodiments about 5 nanometers, with x being about 1.2-2.0 and in some embodiments about 1.7. Other thickness ranges and/or x values may be used. 
     Following formation of RRS material  104 - 1 , a metal/metal oxide layer stack  110 - 1  may be formed. Metal/metal oxide layer stack  110 - 1  may include, for example, Ti/TiO X , Zr/ZrO X , Ni/NiO X , Al/Al X O Y , Ta/TaO X , Nb/NbO X , Hf/HfO X  or another similar layer stack. 
     In the embodiment shown, metal/metal oxide layer stack  110 - 1  may include Ti layer  110   b - 1  having a thickness of about 0.5-10 nanometers, and in some embodiments about 4 nanometers and TiO X  layer  110   a - 1  having a thickness of about 0.5-6 nanometers, and in some embodiments about 1 nanometer; and x may be about 1.2-2.0 and in some embodiments about 1.5. Other thicknesses and/or x values may be used. 
     TiO X  layer  110   a - 1  may be formed, for example, by depositing a layer of Ti over HfO X  layer  104 - 1  and then oxidizing the Ti to form TiO X  layer  110   a - 1 . For example, a layer of Ti may be deposited via PVD and then oxidized in the same ALD chamber used to form HfO X  layer  104 - 1  (e.g., by not flowing the Hf precursor). Ti layer  110   b - 1  may then be formed over TiO X  layer  110   a - 1 . 
     Top electrode  106 - 1  is formed over Ti layer  110   b - 1 . For example, top electrode  106 - 1  may include titanium nitride, tantalum nitride, tungsten nitride, combinations of the same, a metal/metal nitride stack such as Ti/TiN, Ta/TaN, W/WN or another similar barrier layer. In the embodiment shown, top electrode  106 - 1  may include about 10-60 nanometers, and in some embodiments about 20 nanometers of TiN. Other layer thicknesses may be used. In some embodiments, n+ silicon layer  108 - 1 , HfO X  layer  104 - 1 , TiO X  layer  110   a - 1 , Ti Layer  110   b - 1  and/or TiN layer  106 - 1  may be formed in a single cluster tool (e.g., without breaking vacuum) to improve the interfaces between the various layers. 
     To etch the above described MIM stack and diode layers into a pillar structure  304  (as shown in  FIG. 3A , but see also  FIGS. 2A-2F ), any suitable etch process may be used. In some embodiments, a hard mask process may be employed as follows:
         (1) deposit a metal hard mask over top TiN electrode  106 - 1 , such as about 500-1000 angstroms of W;   (2) deposit an oxide hard mask over the metal hard mask, such as about 1000-2000 angstroms of Si X O y ;   (3) deposit a polysilicon hard mask over the oxide hard mask, such as about 500-2000 angstroms of polysilicon; and   (4) deposit photoresist over the polysilicon hard mask, such as about 1000-3000 angstroms of photoresist.       

     The photoresist layer then may be exposed and developed, and the polysilicon hard mask layer may be etched using, for example, HBr, Cl 2 , O 2 , and/or He in a suitable high-density plasma etch chamber. 
     Following stripping (asking) of the photoresist, the oxide hard mask may be etched through the patterned and etched polysilicon hard mask using, for example, C 4 F 6 , O 2 , and Ar in a suitable medium-density plasma etch chamber. The metal hard mask may then be etched through the patterned and etched oxide hard mask using, for example, NF 3 , Ar, N 2 , Cl 2 , He, and/or O 2  in a suitable high-density plasma etch chamber. 
     Thereafter, TiN top electrode  106 - 1  may be etched using, for example, HBr, Cl 2 , and/or He; Ti/TiO X  metal layer stack  110 - 1  may be etched using, for example, CF 4 , Cl 2 , He, and/or N 2 ; HfO X  RRS material  104 - 1  may be etched using, for example, HBr, Cl 2 , He, and/or N 2 ; n+ silicon bottom electrode  108 - 1  may be etched using, for example, HBr, Cl 2 , He, O 2  and/or N 2 ; Ti/TiN layer stack  206  may be etched using, for example, HBr, Cl 2 , and/or He; polysilicon diode  204 - 1  may be etched using, for example, HBr, Cl 2 , He, O 2  and/or N 2 ; and TiN layer  210  may be etched using, for example, HBr, Cl 2 , and/or He. All of these etch processes may be performed, for example, in a suitable high-density plasma etch chamber. Other etch chemistries and/or processes may be employed. 
     The resulting pillar structure  304  may be surrounded by a suitable dielectric to isolate it from other similar pillar structures (not shown) on the same memory level. For example, approximately 200-7000 angstroms of silicon dioxide may be deposited and planarized using chemical mechanical polishing or an etchback process to remove excess dielectric material and form a planar surface for receiving word line  302 . 
     Word line  302  may be formed from any suitable conductive material such as tungsten, another suitable metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the like deposited by any suitable method (e.g., CVD, PVD, etc.). Other conductive layer materials may be used. 
     For example, conductive material may be deposited and etched to form word line  302  (and other word lines not separately shown). In at least one embodiment, such word lines are substantially parallel, substantially coplanar conductors that extend in a different direction than bit line(s)  202   a  (as shown in  FIG. 2F , for example). 
     Word line  302  may be isolated from other word lines via a suitable dielectric fill and etchback process. Thereafter, second memory cell  200 - 2  may be formed over word line  302  in a manner similar to that used to form first memory cell  200 - 1 . 
     Note that when forming second memory cell  200 - 2 , metal/metal-oxide layer stack  110 - 2  is positioned below RRS material  104 - 2 . In such an embodiment, metal/metal-oxide layer stack  110 - 2  may be formed, for example, by depositing a layer of metal, such as titanium, and then oxidizing a portion of the metal layer to form the metal oxide layer portion of the metal/metal-oxide layer stack next to the remaining (unoxidized) portion of the metal layer. 
     That is, a portion of the metal layer may be oxidized, and the oxidized portion of the metal layer may serve as metal-oxide layer  110   a - 2  of metal/metal-oxide layer stack  110 - 2 , and the unoxidized portion of the metal layer may serve as metal layer  110   b - 2  of metal/metal-oxide layer stack  110 - 2 . The remainder of second memory cell  200 - 2  then may be formed. 
     A shared conductor embodiment such as is shown in  FIG. 3A , has a compact structure compared to a non-shared conductor architecture, and also employs a reduced number of masking steps. 
     Following formation of memory cell stack  300   a  (and/or any additional memory cell layers/levels to be formed above memory cell stack  300   a ), the resultant structure may be annealed to crystallize the deposited semiconductor material of diodes  204 - 1  and  204 - 2  (and/or to form silicide regions by reaction of silicide-forming metal from layer  206  with silicon region(s) of diodes  204 - 1  and  204 - 2 ). 
     As stated, the lattice spacing of titanium silicide and cobalt silicide are close to that of silicon, and it appears that silicide layers may serve as “crystallization templates” or “seeds” for adjacent deposited silicon as the deposited silicon crystallizes (e.g., a silicide layer may enhance the crystalline structure of silicon diodes during annealing at temperatures of about 600-800° C.). Lower resistivity diode material thereby is provided. Similar results may be achieved for silicon-germanium alloy and/or germanium diodes. 
     Thus in at least one embodiment, a crystallization anneal may be performed for about 10 seconds to about 2 minutes in nitrogen at a temperature of about 600 to 800° C., and more preferably between about 650 and 750° C. Other annealing times, temperatures and/or environments may be used. 
       FIG. 3B  is a cross sectional view of a second memory cell stack  300   b  provided in accordance with the present invention. Second memory cell stack  300   b  of  FIG. 3B  is similar to first memory cell stack  300   a  of  FIG. 3A , but employs unipolar steering elements in place of the bipolar steering elements employed by first memory cell stack  300   a.    
     For example, diodes  204 - 1  and  204 - 2  in  FIG. 3B  are punch through diodes rather than p-i-n junction diodes as are used in memory cell stack  300   a  of  FIG. 3A . Because diodes  204 - 1  and  204 - 2  of memory cell stack  300   b  are unipolar, diodes  204 - 1  and  204 - 2  need not be inverted relative to one another when a shared conductor arrangement is employed. As stated, other steering elements may be used such as tunneling devices, Schottky diodes or the like. 
       FIG. 3C  is a cross sectional view of a third memory cell stack  300   c  provided in accordance with the present invention. Third memory cell stack  300   c  of  FIG. 3C  is similar to first memory cell stack  300   a  of  FIG. 3A , but does not employ a shared word line. Rather, memory cell  200 - 2  does not employ the word line of memory cell  200 - 1 . Instead, memory cell  200 - 2  employs a separate bit line  202   a  and a separate word line  202   b  as shown. Memory cell  200 - 2  is isolated from memory cell  200 - 1  by one or more interlevel dielectrics  306 , which may include silicon oxide, silicon nitride or a similar dielectric. 
     In an embodiment such as that of  FIG. 3C , the polarity orientation of MIM stacks  102 - 1  and  102 - 2 , as well as of diodes  204 - 1  and  204 - 2 , may be the same throughout the entire memory cell stack  300   c.    
       FIG. 3D  is a cross sectional view of a fourth memory cell stack  300   d  provided in accordance with the present invention. The fourth memory cell stack  300   d  of  FIG. 3D  is similar to third memory cell stack  300   c  of  FIG. 3C , but employs unipolar steering elements in place of the bipolar steering elements employed by third memory cell stack  300   c  of  FIG. 3C . For example, diodes  204 - 1  and  204 - 2  in  FIG. 3D  are punch through diodes rather than p-i-n junction diodes as are used in memory cell stack  300   c  of  FIG. 3C . 
       FIG. 3E  is a cross sectional view of a fifth memory cell stack  300   e  provided in accordance with the present invention. The fifth memory cell stack  300   e  of  FIG. 3E  is similar to first memory cell stack  300   a  of  FIG. 3A , but employs no steering element within each memory cell  200 - 1  and  200 - 2 . In such an embodiment, steering elements remote from the memory cells  200 - 1  and/or  200 - 2  may be employed to limit current flow through MIM stacks  102 - 1  and/or  102 - 2 . Such a steering element may include, for example, a transistor, a diode, a tunneling device or any other suitable device. 
       FIG. 3F  is a cross sectional view of a sixth memory cell stack  300   f  provided in accordance with the present invention. The sixth memory cell stack  300   f  of  FIG. 3F  is similar to fifth memory cell stack  300   e  of  FIG. 3E , but does not employ a shared word line. Rather, memory cell  200 - 2  of memory cell stack  300   f  does not employ the word line of memory cell  200 - 1 . 
     Instead, memory cell  200 - 2  of memory cell stack  300   f  employs a separate bit line  202   a  and a separate word line  202   b  as shown. Memory cell  200 - 2  of memory cell stack  300   f  is isolated from memory cell  200 - 1  by one or more interlevel dielectrics  306 , which may include silicon oxide, silicon nitride or a similar dielectric. 
     Array lines may be shared between adjacent memory levels as described previously with reference to  FIG. 2F  and  FIGS. 3A ,  3 B and  3 E. Shared array lines may be either bit lines or word lines. In some embodiments and as described previously with reference to  FIGS. 2F ,  3 A,  3 B and  3 E, the bottom most array line may be a bit line with a layer of memory cells above it, followed by a shared word line with a layer of memory cells above it, followed by a shared bit line with a layer of memory cells above it, etc., with the top most array line being a bit line. In other embodiments, the bottom and top most array lines may be word lines. 
     In some embodiments, lower IR drops may be achieved by spreading simultaneously selected bits to multiple memory levels. In this manner, bias may be memory level independent, simplifying memory control circuitry design, and reset and set operations may be performed on bits from multiple memory levels as described below with reference to  FIGS. 4A-4C . 
       FIG. 4A  is a schematic diagram of an exemplary three dimensional memory array  400  provided in accordance with the present invention. Memory array  400  is fully mirrored with array lines shared and MIM stacks and diodes alternating polarity orientation between adjacent memory levels. 
     Memory array  400  includes a plurality of memory levels  402   a - n  having shared word lines WL 1  and WL 2 . Top memory level  402   n  includes bit lines BL 1  and BL 2 , and bottom memory level  402   a  includes bit lines BL 3  and BL 4 . Memory cells  406 ,  408 ,  410  and  412  are located in top memory level  402   n  between WL 1  and BL 1 , WL 1  and BL 2 , WL 2  and BL 1 , and WL 2  and BL 2 , respectively. Each memory cell  406 - 412  includes a resistance-switchable MIM stack oriented to be set and a diode oriented to be reverse biased when a positive voltage polarity is applied between the memory cell&#39;s word line relative to its respective bit line (as shown). 
     Memory cells  414 ,  416 ,  418  and  420  are located in bottom memory level  402   a  between WL 1  and BL 3 , WL 1  and BL 4 , WL 2  and BL 3 , and WL 2  and BL 4 , respectively. Each memory cell  414 - 420  includes a resistance-switchable MIM stack oriented to be set and a diode oriented to be reverse biased when a positive polarity voltage is applied between the memory cell&#39;s word line relative to its respective bit line (as shown). 
     Memory cells above and below a word line may be simultaneously reset or set. For example,  FIG. 4B  illustrates exemplary timing diagrams for resetting memory cells  410  and  418  simultaneously. With reference to  FIG. 4B , at time t0, WL 2  is pulled to ground (0 volts) from a reset voltage (Vr) (e.g., about 4 volts in some embodiments, although other reset voltages maybe used). WL 1  is held at Vr and BL 2  and BL 4  are grounded. 
     At time t1, both BL 1  and BL 3  switch from ground to reset voltage Vr. BL 1  and BL 3  remain at Vr until a time t2 when both return to ground. With WL 2  at 0 and BL 1  at Vr between times t1 and t2, memory cell  410  is reset. Likewise, with WL 2  at 0 and BL 3  at Vr between times t1 and t2, memory cell  418  is reset. Accordingly, both memory cells  410  and  418  may be reset simultaneously. At time t3, WL 2  returns to Vr. 
     In some embodiments, the pulse width from t1 to t2 may be about 1 to 500 nanoseconds, and in some embodiments about 50 nanoseconds. Other pulse widths may be used. 
       FIG. 4C  illustrates exemplary timing diagrams for setting memory cells  410  and  418  simultaneously. With reference to  FIG. 4C , at time t0, WL 2  switches to a set voltage (Vs) from ground. In some embodiments, Vs may be about 4 volts, although other set voltages may be used. WL 1 , BL 2  and BL 4  are grounded. 
     At time t1, both BL 1  and BL 3  switch from ground to −Vs. BL 1  and BL 3  remain at −Vs until a time t2 when both return to ground. With WL 2  at Vs and BL 1  at −Vs between times t1 and t2, memory cell  410  is set. Likewise, with WL 2  at Vs and BL 3  at −Vs between times t1 and t2, memory cell  418  is set. Accordingly, both memory cells  410  and  418  may be set simultaneously. At time t3, WL 2  returns to ground. 
     In some embodiments, the pulse width from t1 to t2 may be about 1 to 500 nanoseconds, and in some embodiments about 50 nanoseconds. Other pulse widths may be used. 
     Simultaneous setting and/or resetting of memory cells on multiple memory levels provides higher bandwidth for memory array  400 . 
     Memory Cell Stacks Having Storage Elements and Steering Elements that Share Material Layers 
       FIGS. 5A-5C  illustrate cross sectional views of first exemplary memory cell stacks  200 - 1   a ,  200 - 1   b  and  200 - 1   c  in which storage elements and steering elements may share a material layer (as shown in  FIGS. 5B-5C ) in accordance with the present invention. For example,  FIG. 5A  illustrates lower memory cell  200 - 1  of  FIG. 3A  (referred to as memory cell  200 - 1   a  in  FIG. 5A ) having steering element  204 - 1  (e.g., an n-i-p diode) coupled in series with storage element  102 - 1  (e.g., an MIM stack). 
     In general any suitable steering element such as an n-p, p-n, n-i-p, p-i-n, punch through, Schottky, other diode configuration or other similar device may be used for steering element  204 - 1 . Any of the MIM stacks described herein may be employed for storage element  102 - 1  such as MIM stacks that employ TiN/Ti/TiO X /HfO X /n+ Si, TiN/Ti/HfO X /n+ Si, TiN/TiO X /HfO X /n+ Si, other metal, metal nitride, semiconductor and/or RRS materials, as well as any other suitable storage elements. 
     In some embodiments, diode  204 - 1  may be referred to as the lower or “L0” diode. MIM stack  102 - 1  may be referred to as the lower or “L0” MIM stack. 
     As seen in  FIG. 5A , memory cell  200 - 1   a  employs a first n+ Si layer  108 - 1  within MIM stack  102 - 1  and a second n+ Si layer  204 - 1   c  within diode  204 - 1 , separated by intervening Ti/TiN layer  206  as previously described. In some embodiments of the invention, as shown in  FIG. 5B , a memory cell  200 - 1   b  may be formed in which Ti/TiN layer  206  is eliminated and a single n+ Si layer  108 - 1 ,  204 - 1   c  is used for both MIM stack  102 - 1  and diode  204 - 1 . Such a device structure may simplify process flow, eliminating at least two deposition steps (for the Ti/TiN layer and/or second n+ Si layer) and one clean step (between n+ Si layer and Ti/TiN layer deposition), and reduce device cost. 
     In some embodiments, n+ silicon layer  108 - 1 ,  204 - 1   c  may have a thickness of about 5-100 nanometers, and in some embodiments about 20 nanometers. The doping concentration of n+ silicon layer  108 - 1 ,  204 - 1   c  may be about 5×10 19 -5×10 21  atoms/cm 3  and in some embodiments about 2×10 20  atoms/cm 3 . Other film thicknesses and/or doping concentrations may be used. 
     As stated previously, a silicide such as titanium silicide or cobalt silicide, may be added to the top of a diode stack to enhance the crystalline structure of the diode (e.g., through use of an anneal at temperatures of about 600-800° C.). Lower resistivity diode material thereby may be provided. In accordance with some embodiments of the present invention, memory cell  200 - 1   b  of  FIG. 5B  may be modified to include a TiSi X  layer or TiO X /TiSi X  layer stack  502  formed above diode  204 - 1  to improve the crystalline structure of diode  204 - 1 , as shown by memory cell  200 - 1   c  in  FIG. 5C . 
     As shown in  FIG. 5C , the silicide layer or layer stack  502  is positioned between n+ Si layer  108 - 1 ,  204 - 1   c  and RRS layer  104 - 1  (e.g., HfO X  layer  104 - 1 ). Such a layer may be formed, for example, by depositing a titanium layer over n+ Si layer  108 - 1 ,  204 - 1   c  and converting the Ti to TiSi X  during a silicidation anneal performed at about 540° C. to 650° C. for about 60 seconds. Other process times and/or temperatures may be used. 
     If the silicidation anneal is performed before HfO X  layer  104 - 1  is deposited, then a single TiSi X  layer may be formed between n+ Si layer  108 - 1 ,  204 - 1   c  and HfO X  layer  104 - 1 . However, if the silicidation anneal is performed after HfO X  layer  104 - 1  is deposited, then a dual layer of TiO X /TiSi X  may be formed between n+ Si layer  108 - 1 ,  204 - 1   c  and HfO X  layer  104 - 1 . 
     In some embodiments, the TiO X  layer may have a thickness of about 0.5 to 10 nanometers, in some embodiments about 1 nanometer, and an x value of about 1 to 2; and the TiSi X  layer may have a thickness of about 1 to 10 nanometers, in some embodiments about 2 nanometers, and an x value of about 0.5 to 1.5. Other thicknesses and/or x values may be used. 
     The use of a TiSi X  layer between n+ Si layer  108 - 1 ,  204 - 1   c  and HfO X  layer  104 - 1  may prevent the formation of a SiO X  sub-layer on the n+ Si layer during formation of the HfO X  layer. Such a SiO X  layer may increase the forming voltage of MIM stack  102 - 1 . Additionally or alternatively, Ti from TiSi X  layer  502  may migrate into and dope HfO X  layer  104 - 1 , advantageously reducing the set/reset voltage of HfO X  layer  104 - 1 . Such advantages may be seen with other metal oxide RRS layers employed within MIM stack  102 - 1  such as ZrO X , NiO X , TiO X , TaO X , NbO X , Al X O Y , or another metal oxide (MO X ) layer. A cobalt silicide or other silicide layer may be similarly formed and/or employed. 
       FIGS. 6A-6C  illustrate cross sectional views of second exemplary memory cell stacks  200 - 1   d ,  200 - 1   e  and  200 - 1   f  in which storage elements and steering elements may share a material layer (as shown in  FIGS. 6B-6C ) in accordance with the present invention. Memory cell stacks  200 - 1   d ,  200 - 1   e  and  200 - 1   f  of  FIGS. 6A-6C  are similar to memory cell stacks  200 - 1   a ,  200 - 1   b  and  200 - 1   c  of  FIGS. 5A-5C , but employ punch through diodes in place of the n-i-p diodes of memory cell stacks  200 - 1   a ,  200 - 1   b  and  200 - 1   c  of  FIGS. 5A-5C . 
     For example,  FIG. 6A  illustrates lower memory cell  200 - 1  of  FIG. 3B  (referred to as memory cell  200 - 1   d  in  FIG. 6A ) having steering element  204 - 1  (e.g., an n-p-n punch through diode) coupled in series with storage element  102 - 1  (e.g., an MIM stack). Any of the MIM stacks described herein may be employed for MIM stack  102 - 1  such as MIM stacks that employ TiN/Ti/TiO X /HfO X /n+ Si, TiN/Ti/HfO X /n+ Si, TiN/TiO X /HfO X /n+ Si, other metal, metal nitride, semiconductor and/or RRS materials, as well as any other suitable storage elements. 
     In some embodiments of the invention, as shown in  FIG. 6B , a memory cell  200 - 1   e  may be formed in which Ti/TiN layer  206  is eliminated and a single n+ Si layer  108 - 1  is used for both MIM stack  102 - 1  and diode  204 - 1 . As stated, such a device structure may simplify process flow, eliminating at least two deposition steps (for the Ti/TiN layer and/or second n+ Si layer) and one clean step (between n+ Si layer and Ti/TiN layer deposition), and reduce device cost. 
     In some embodiments, n+ silicon layer  108 - 1  may have a thickness of about 5-100 nanometers, and in some embodiments about 20 nanometers. The doping concentration of n+ silicon layer  108 - 1  may be about 5×10 19 -5×10 21  atoms/cm 3  and in some embodiments about 2×10 20  atoms/cm 3 . Other film thicknesses and/or doping concentrations may be used. 
     As with memory cell  200 - 1   c  of  FIG. 5C ,  FIG. 6C  illustrates a memory cell  200 - 1   f  which includes a TiSi X  layer or TiO X /TiSi X  layer stack  502  formed above diode  204 - 1  to improve the crystalline structure of diode  204 - 1 . For example, the silicide layer or layer stack  502  may be positioned between n+ Si layer  108 - 1  and HfO X  layer  104 - 1 . 
     Such a layer may be formed, for example, by depositing a titanium layer over n+ Si layer  108 - 1  and converting the Ti to TiSi X  during a silicidation anneal performed at about 540° C. to 650° C. for about 60 seconds. If the silicidation anneal is performed after HfO X  layer  104 - 1  is deposited, then a dual layer of TiO X /TiSi X  may be formed between n+ Si layer  108 - 1  and HfO X  layer  104 - 1  (as previously described). 
       FIGS. 7A-7D  illustrate cross sectional views of third exemplary memory cell stacks  200 - 2   a ,  200 - 2   b ,  200 - 2   c  and  200 - 2   d  in which storage elements and steering elements may share a material layer (as shown in  FIGS. 7B-7D ) in accordance with the present invention. For example, memory cell stack  200 - 2   a  of  FIG. 7A  is similar to upper memory cell  200 - 2  of  FIG. 3A  having steering element  204 - 2  (e.g., a p-i-n diode) coupled in series with storage element  102 - 2  (e.g., an MIM stack). 
     However, in memory cell stack  200 - 2   a  of  FIG. 7A , the positions of diode  204 - 2  and MIM stack  102 - 2  are reversed so that first n+ layer  106 - 2  and second n+ layer  204 - 2   c  of memory cell stack  200 - 2   a  are near one another. Ti/TiN layer stack  206  also is split into a Ti layer  206   a  (positioned above diode  204 - 2 ) and a TiN layer  206   b  (positioned between MIM stack  102 - 2  and diode  204 - 2 ) as shown. 
     In general any suitable steering element such as an n-p, p-n, n-i-p, p-i-n, punch through, Schottky, other diode configuration or other similar device may be used for steering element  204 - 2 . Any of the MIM stacks described herein may be employed for storage element  102 - 2  such as MIM stacks that employ TiN/Ti/TiO X /HfO X /n+ Si, TiN/Ti/HfO X /n+ Si, TiN/TiO X /HfO X /n+ Si, other metal, metal nitride, semiconductor and/or RRS materials, as well as any other suitable storage elements. In some embodiments, diode  204 - 2  may be referred to as the upper or “L1” diode. MIM stack  102   2  may be referred to as the upper or “L1” MIM stack. 
     As seen in  FIG. 7A , memory cell  200 - 2   a  employs a first n+ Si layer  106 - 2  within MIM stack  102 - 2  and a second n+ Si layer  204 - 2   c  within diode  204 - 2 , separated by intervening TiN layer  206   b . In some embodiments of the invention, as shown in  FIG. 7B , a memory cell  200 - 2   b  may be formed in which TiN layer  206   b  is eliminated and a single n+ Si layer  106 - 2 ,  204 - 2   c  is used for both MIM stack  102 - 2  and diode  204 - 2 . Such a device structure may simplify process flow, eliminating at least two deposition steps (for the TiN layer and/or second n+ Si layer) and one clean step (between n+ Si layer and TiN layer deposition), and reduce device cost. 
     In some embodiments, n+ silicon layer  106 - 2 ,  204 - 2   c  may have a thickness of about 5-100 nanometers, and in some embodiments about 20 nanometers. The doping concentration of n+ silicon layer  106 - 2 ,  204 - 2   c  may be about 5×10 19 -5×10 21  atoms/cm 3  and in some embodiments about 2×10 20  atoms/cm 3 . Other film thicknesses and/or doping concentrations may be used. 
     Note that the presence of Ti layer  206   a  above p+ Si layer  204 - 2   a  of diode  204 - 2  allows a silicide layer (titanium silicide) to be formed at the top of the diode stack to enhance the crystalline structure of diode  204 - 2  (e.g., through use of an anneal at temperatures of about 600-800° C.). Lower resistivity diode material thereby may be provided. 
     In accordance with some embodiments of the present invention, it may be desirable to leave diode  204 - 2  below MIM stack  102 - 2 , as was shown in  FIG. 3A . For example,  FIG. 7C  illustrates an example of a memory cell  200 - 2   c  that is similar to memory cell  200 - 2  of  FIG. 3A , with diode  204 - 2  below MIM stack  102 - 2 , but with TiO X  layer  110   a - 2 , Ti layer  110   b - 2 , TiN layer  108 - 2  and Ti/TiN layer stack  206  removed (see  FIG. 3A  versus  FIG. 7C ). In such an embodiment, p+ Si layer  204 - 2   a  serves as both the bottom electrode of MIM stack  102 - 2  and the p+ region of diode  204 - 2 , greatly reducing the overall memory cell stack height and simplifying process flow. 
     In some embodiments, memory cell  200 - 2   c  of  FIG. 7C  may be modified to include a TiSi X  layer or TiO X /TiSi X  layer stack  502  formed above diode  204 - 2  to improve the crystalline structure of diode  204 - 2 , as shown by memory cell  200 - 2   d  in  FIG. 7D . 
     As shown in  FIG. 7D , the silicide layer or layer stack  502  is positioned between p+ Si layer  204 - 2   a  and RRS layer  104 - 2  (e.g., HfO X  layer  104 - 2 ). Such a layer may be formed, for example, by depositing a titanium layer over p+ Si layer  204 - 2   a  and converting the Ti to TiSi X  during a silicidation anneal performed at about 540° C. to 650° C. for about 60 seconds. Other process times and/or temperatures may be used. 
     If the silicidation anneal is performed before HfO X  layer  104 - 2  is deposited, then a single TiSi X  layer may be formed between p+ Si layer  204 - 2   a  and HfO X  layer  104 - 2 . However, if the silicidation anneal is performed after HfO X  layer  104 - 2  is deposited, then a dual layer of TiO X /TiSi X  may be formed between p+ Si layer  204 - 2   a  and HfO X  layer  104 - 2 . 
     In some embodiments, the TiO X  layer may have a thickness of about 0.5 to 10 nanometers, in some embodiments about 1 nanometer, and an x value of about 1 to 2; and the TiSi X  layer may have a thickness of about 1 to 10 nanometers, in some embodiments about 2 nanometers, and an x value of about 0.5 to 1.5. Other thicknesses and/or x values may be used. 
     The use of a TiSi X  layer between p+ Si layer  204 - 2   a  and HfO X  layer  104 - 2  may prevent the formation of a SiO X  sub-layer on the p+ Si layer during formation of the HfO X  layer. As stated, such a SiO X  layer may increase the forming voltage of MIM stack  102 - 2 . Additionally or alternatively, Ti from TiSi X  layer  502  may migrate into and dope HfO X  layer  104 - 2 , advantageously reducing the set/reset voltage of HfO X  layer  104 - 2 . 
     Such advantages may be seen with other metal oxide RRS layers employed within MIM stack  102 - 2  such as ZrO X , NiO X , TiO X , TaO X , NbO X , Al X O Y , or another MO X  layer. A cobalt silicide or other silicide layer may be similarly formed and/or employed. 
       FIGS. 8A-8D  illustrate cross sectional views of fourth exemplary memory cell stacks  200 - 2   e ,  200 - 2   f ,  200 - 2   g  and  200 - 2   h  in which storage elements and steering elements may share a material layer (as shown in  FIGS. 8B-8D ) in accordance with the present invention. Memory cell stacks  200 - 2   e ,  200 - 2   f ,  200 - 2   g  and  200 - 2   h  of  FIGS. 8A-8D  are similar to memory cell stacks  200 - 2   a ,  200 - 2   b ,  200 - 2   c  and  200 - 1 D of  FIGS. 7A-7D , but employ punch through diodes in place of the p-i-n diodes of memory cell stacks  200 - 2   a ,  200 - 2   b ,  200 - 2   c  and  200 - 2   d  of  FIGS. 7A-7D . 
     Memory cell stack  200 - 2   e  of  FIG. 8A  is similar to upper memory cell  200 - 2  of  FIG. 3B  having steering element  204 - 2  (e.g., an n-p-n punch through diode) coupled in series with storage element  102 - 2  (e.g., an MIM stack). However, in memory cell stack  200 - 2   e  of  FIG. 8A , the positions of diode  204 - 2  and MIM stack  102 - 2  are reversed so that first n+ layer  106 - 2  and second n+ layer from diode  204 - 2  of memory cell  200 - 2   e  are near one another. 
     Ti/TiN layer stack  206  also is split into a Ti layer  206   a  (positioned above diode  204 - 2 ) and a TiN layer  206   b  (positioned between MIM stack  102 - 2  and diode  204 - 2 ) as shown. Any of the MIM stacks described herein may be employed for MIM stack  102 - 2  such as MIM stacks that employ TiN/Ti/TiO X /HfO X /n+ Si, TiN/Ti/HfO X /n+ Si, TiN/TiO X /HfO X /n+ Si, other metal, metal nitride, semiconductor and/or RRS materials, as well as any other suitable storage elements. 
     In some embodiments of the invention, as shown in  FIG. 8B , a memory cell  200 - 2   f  may be formed in which TiN layer  206   b  is removed and a single n+ Si layer  106 - 2  is used for both MIM stack  102 - 2  and diode  204 - 2 . As stated, such a device structure may simplify process flow, eliminating at least two deposition steps (for the TiN layer and/or second n+ Si layer) and one clean step (between n+ Si layer and TiN layer deposition), and reduce device cost. 
     In some embodiments, n+ silicon layer  106 - 2  may have a thickness of about 5-100 nanometers, and in some embodiments about 20 nanometers. The doping concentration of n+ silicon layer  106 - 2  may be about 5×10 19 -5×10 21  atoms/cm 3  and in some embodiments about 2×10 20  atoms/cm 3 . Other film thicknesses and/or doping concentrations may be used. 
     As in the embodiment of  FIG. 7B , the presence of Ti layer  206   a  above top n+ Si layer of diode  204 - 2  in  FIG. 8B  allows a silicide layer (titanium silicide) to be formed at the top of the diode stack to enhance the crystalline structure of diode  204 - 2  (e.g., through use of an anneal at temperatures of about 600-800° C.). Lower resistivity diode material thereby may be provided. 
     In accordance with some embodiments of the present invention, it may be desirable to leave diode  204 - 2  below MIM stack  102 - 2 , as was shown in  FIG. 3B . For example,  FIG. 8C  illustrates an example of a memory cell  200 - 2   g  that is similar to memory cell  200 - 2  of  FIG. 3B , with diode  204 - 2  below MIM stack  102 - 2 , but with TiO X  layer  110   a - 2 , Ti layer  110   b - 2 , TiN layer  108 - 2  and Ti/TiN layer stack  206  removed. In such an embodiment, the top n+ Si layer of diode  204 - 2  also serves as the bottom electrode of MIM stack  102 - 2 , greatly reducing the overall memory cell stack height and simplifying process flow. 
     In some embodiments, memory cell  200 - 2   g  of  FIG. 8C  may be modified to include a TiSi X  layer or TiO X /TiSi X  layer stack  502  formed above diode  204 - 2  to improve the crystalline structure of diode  204 - 2 , as shown by memory cell  200 - 2   h  in  FIG. 8D . 
     As shown in  FIG. 8D , the silicide layer or layer stack  502  is positioned between the top n+ Si layer of diode  204 - 2  and RRS layer  104 - 2  (e.g., HfO X  layer  104 - 2 ). Such a layer may be formed, for example, by depositing a titanium layer over the top n+ Si layer of diode  204 - 2  and converting the Ti to TiSi X  during a silicidation anneal performed at about 540° C. to 650° C. for about 60 seconds. If the silicidation anneal is performed after HfO X  layer  104 - 2  is deposited, then a dual layer of TiO X /TiSi X  may be formed between the top n+ Si layer of diode  204 - 2  and HfO X  layer  104 - 2 . 
     Through use of the present invention, at least one material layer of a steering element may be shared with a storage element, memory cell stack height may be reduced and process flow may be simplified. Further, in some embodiments, use of such shared material layers within memory cells may provide a reduction in forming, set and/or reset voltages of the memory cells. 
     In one particular embodiment of a memory cell similar to memory cell  200 - 1   e  of  FIG. 6B  (without TiO X  layer  110   a - 1 ), forming voltage of the memory cell dropped from about 14-15 volts to about 6-7 volts, set voltage dropped from about 10-11 volts to about 6-7 volts, and reset voltage dropped from about −12 volts to about −8 volts when compared to a similar memory cell without shared material layers. Such voltage drops are merely exemplary and will depend significantly on material type, layer thicknesses, and the like. In general, however, reducing stack height of a memory cell appears to reduce the set and reset voltages of the memory cell. 
     The foregoing description discloses only exemplary embodiments of the invention. Modifications of the above disclosed apparatus and methods which fall within the scope of the invention will be readily apparent to those of ordinary skill in the art. For instance, while the present invention has been described primarily with reference to bipolar, metal oxide based storage elements, other bipolar storage elements, whether employing metal oxide switching materials or not, may be similarly employed within memory arrays with shared or separate conductors including, for example, chalcogenide-based storage elements (e.g., in MIM stacks), Pt/NiO X /TiN MIM stacks, or the like. 
     Some carbon-based materials exhibit similar reversible resistivity-switching properties such amorphous carbon containing nanocrystalline graphene (referred to herein as “graphitic carbon”), graphene, graphite, carbon nano-tubes, amorphous diamond-like carbon (“DLC”), silicon carbide, boron carbide and other crystalline forms of carbon, which may include secondary materials. Accordingly, the present invention may be used with bipolar MIM stacks using any of these resistivity-switching materials. 
     Further, MIM stacks may be placed above or below steering elements within any memory cells. 
     In some embodiments of the invention, MIM stacks may be formed from an RRS material sandwiched between two conductive layers. The two conductive layers may be metal, metal nitride, heavily doped semiconductor, whether n+ or p+, combinations of metal, metal nitride and/or semiconductor, or the like. Exemplary metal conductive layers include titanium, tungsten and tantalum; and exemplary metal nitride conductive layers include titanium nitride, tungsten nitride and tantalum nitride. Other metal and/or metal nitrides may be used. 
     Accordingly, although the present invention has been disclosed in connection with exemplary embodiments thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention, as defined by the following claims.