Patent Publication Number: US-2023157017-A1

Title: Erasable programmable single-ploy non-volatile memory cell and associated array structure

Description:
This application claims the benefit of U.S. Provisional Application Serial No. 63/279,184, filed Nov. 15, 2021, the subject matter of which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a non-volatile memory, and more particularly to an erasable programmable single-poly non-volatile memory cell and an associated array structure. 
     BACKGROUND OF THE INVENTION 
     As is well known, a memory cell of a non-volatile memory comprises a storage unit. For example, the storage unit is a floating gate transistor. The storage state of the memory cell is determined according to the number of charges stored in the floating gate of the floating gate transistor. 
     In order to be compatible with the standard CMOS manufacturing process, the memory cell of the conventional non-volatile memory is equipped with a single-poly floating gate transistor. The floating gate transistor and associated electronic devices are collaboratively formed as a single-poly non-volatile memory cell. 
     For example, an erasable programmable single-poly non-volatile memory is disclosed in U.S. Pat. No. 8,941,167.  FIG.  1 A  is a schematic top view illustrating a conventional single-poly non-volatile memory cell.  FIG.  1 B  is a schematic equivalent circuit diagram of the single-poly non-volatile memory cell as shown in  FIG.  1 A . For succinctness, the single-poly non-volatile memory cell is referred hereinafter as a memory cell. 
     As shown in  FIG.  1 A , three p-type doped regions  31 ,  32  and  33  are formed in an N-well region NW1. In addition, a select gate  34  and a floating gate  36  formed of a polysilicon layer are spanned over the areas between the p-type doped regions  31 ,  32  and  33 . The floating gate  36  is externally extended to a region beside a p-type doped region  48  and an n-type doped region  49 . The p-type doped region  48  and the n-type doped region  49  are formed in an N-well region NW2. In addition, the floating gate  36  is also located beside an n-type doped region  53 . 
     The conventional single-poly non-volatile memory cell comprises a select transistor M S , a floating gate transistor M F , a p-type transistor and an n-type transistor. The select transistor M S  and the floating gate transistor M F  are constructed in the N-well region NW1. The p-type transistor is constructed in the N-well region NW2. The n-type transistor is constructed in a P-well region PW (not shown), which is located under the n-type doped region  53 . 
     The p-type doped region  31 , the p-type doped region  32 , the select gate  34  and the N-well region NW1 are collaboratively formed as the select transistor M S . The p-type doped region  32 , the p-type doped region  33 , the floating gate  36  and the N-well region NW1 are collaboratively formed as the floating gate transistor M F . The floating gate  36  and an erase gate region  45  are collaboratively formed as the p-type transistor. The floating gate  36  and an assist gate region  55  are collaboratively formed as the n-type transistor. In addition, the erase gate region  45  comprises the N-well region NW2, the p-type doped region  48  and the n-type doped region  49 . The assist gate region  55  comprises the P-well region PW and the n-type doped region  53 . 
     Please refer to  FIG.  1 B . The select gate  34  of the select transistor M S  receives a select gate voltage V SG . The first drain/source terminal of the select transistor M S  receives a source line voltage V SL . The body terminal of the select transistor M s  receives an N-well voltage V NW1 . The first drain/source terminal of the floating gate transistor M F  is connected to the second drain/source terminal of the select transistor M S . The second drain/source terminal of the floating gate transistor M F  receives a bit line voltage V BL . The body terminal of the floating gate transistor M F  receives the N-well voltage V NW1 . 
     Moreover, it is regarded that the two drain/source terminals of the p-type transistor are connected to the p-type doped region  48 . The body terminal of the p-type transistor receives an N-well voltage V NW2 . That is, the p-type transistor is formed as a metal-oxide-semiconductor capacitor C MOS1 . Hereinafter, the metal-oxide-semiconductor capacitor is also referred as a MOS capacitor. The first terminal of the MOS capacitor C MOS1  is connected to the floating gate  36 . The second terminal of the MOS capacitor C MOS1  receives an erase line voltage V EL . 
     Similarly, it is regarded that the two drain/source terminals of the n-type transistor are connected to the n-type doped region  53 . The body terminal of the n-type transistor receives a P-well voltage V PW . That is, the p-type transistor is formed as a MOS capacitor C MOS2 . The first terminal of the MOS capacitor C MOS2  is connected to the floating gate  36 . The second terminal of the MOS capacitor C MOS2  receives an assist gate voltage V AG . 
     By providing proper bias voltages as the select gate voltage V SG , the source line voltage V SL , the bit line voltage V SL , the erase line voltage V EL , the assist gate voltage V AG , the N-well voltage V NW1 , the N-well voltage V NW2  and the P-well voltage V PW , a program action, an erase action or a read action can be selectively performed on the non-volatile memory cell. 
     In the assist gate region  55 , the second terminal of the MOS capacitor C MOS2  receives the assist gate voltage V AG . While the program action, the erase action or the read action is performed, the assist gate voltage V AG  is coupled to the floating gate  36  in order to enhance the programming efficiency, the erasing efficiency or the reading speed of non-volatile memory cell. 
     As mentioned above, the conventional single-poly non-volatile memory cell comprises the assist gate region  55 . Consequently, the conventional non-volatile memory cell can be regarded as a five-terminal memory cell. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides an array structure of erasable programmable non-volatile memory cells. The array structure is constructed in a semiconductor substrate. The array structure comprises: an isolation structure formed on the semiconductor substrate, wherein a surface of the semiconductor substrate is divided into a first region and a second region by the isolation structure; a well region formed in the surface of the semiconductor substrate corresponding to the first region; a first gate structure and a second gate structure formed on the surface of the semiconductor substrate corresponding to the first region, wherein the first region is divided into a first sub-region, a second sub-region and a third sub-region by the first gate structure and the second gate structure, wherein the first sub-region is located beside a first side of the first gate structure, the second sub-region is arranged between a second side of the first gate structure and a first side of the second gate structure, and the third sub-region is located beside a second side of the second gate structure, wherein the first gate structure is connected to a first select gate line, an extension segment of the second gate structure is externally extended from the second gate structure through a surface of the isolation structure, a portion of the second region is covered by a first portion of the second gate structure, and a portion of the third sub-region is covered by a second portion of the second gate structure; a first doped region, a second doped region and a third doped region formed in the surface of the semiconductor substrate corresponding to the first sub-region, the second sub-region and the third sub-region, respectively, wherein the first doped region is connected to a first source line, and the third doped region is connected to a first bit line; and, a fourth doped region formed in the surface of the semiconductor substrate corresponding to the second region, wherein the fourth doped region is connected to an erase line; wherein the first doped region, the first gate structure and the second doped region are collaboratively formed as a first select transistor, the second doped region, the second gate structure and the third doped region are collaboratively formed as a first floating gate transistor, the first portion of the second gate structure and the fourth doped region are collaboratively formed as a first capacitor, and the second portion of the second gate structure and the third doped region are collaboratively formed as a second capacitor, wherein a first memory cell of the array structure comprises the first select transistor, the first floating gate transistor, the first capacitor and the second capacitor. 
     Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG.  1 A  (prior art) is a schematic top view illustrating a conventional single-poly non-volatile memory cell; 
         FIG.  1 B  (prior art) is a schematic equivalent circuit diagram of the single-poly non-volatile memory cell as shown in  FIG.  1 A ; 
         FIGS.  2 A to  2 F  schematically illustrate the steps of a method of manufacturing a single-poly non-volatile memory cell according to a first embodiment of the present invention; 
         FIG.  2 G  is a schematic equivalent circuit diagram of the single-poly non-volatile memory cell according to the first embodiment of the present invention; 
         FIG.  3 A  is a bias voltage table illustrating the bias voltages for performing a program action, an erase action and two read actions on the memory cell according to the first embodiment of the present invention; 
         FIG.  3 B  is a schematic circuit diagram the operations of performing the program action on the memory cell according to the first embodiment of the present invention; 
         FIG.  3 C  is a schematic circuit diagram the operations of performing the erase action on the memory cell according to the first embodiment of the present invention; 
         FIG.  3 D  is a schematic circuit diagram the operations of performing a first read action on the memory cell according to the first embodiment of the present invention; 
         FIG.  3 E  is a schematic circuit diagram the operations of performing a second read action on the memory cell according to the first embodiment of the present invention; 
         FIG.  4 A  is a schematic top view illustrating an array structure of with plural memory cells of the first embodiment; 
         FIG.  4 B  is a schematic circuit diagram illustrating the equivalent circuit of the array structure as shown in  FIG.  4 A ; 
         FIGS.  5 A to  5 E  schematically illustrate the steps of a method of manufacturing a single-poly non-volatile memory cell according to a second embodiment of the present invention; 
         FIG.  6 A  is a schematic top view illustrating an array structure of with plural memory cells of the second embodiment; 
         FIG.  6 B  is a schematic circuit diagram illustrating the equivalent circuit of the array structure as shown in  FIG.  6 A ; 
         FIG.  7    is a schematic top view illustrating a single-poly non-volatile memory cell of the third embodiment and an associated array structure of with plural memory cells; 
         FIG.  8 A  is a single-poly non-volatile memory cell according to a fourth embodiment of the present invention; 
         FIG.  8 B  is a schematic equivalent circuit diagram of the single-poly non-volatile memory cell according to the fourth embodiment of the present invention; 
         FIG.  8 C  is a bias voltage table illustrating the bias voltages for performing a program action, an erase action and two read actions on the memory cell according to the fourth embodiment of the present invention; and 
         FIG.  9    is a single-poly non-volatile memory cell according to a fifth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       FIGS.  2 A to  2 F  schematically illustrate the steps of a method of manufacturing a single-poly non-volatile memory cell according to a first embodiment of the present invention.  FIG.  2 G  is a schematic equivalent circuit diagram of the single-poly non-volatile memory cell according to the first embodiment of the present invention. For brevity, the single-poly non-volatile memory cell is referred hereinafter as a memory cell. 
     As shown in  FIG.  2 A , an isolation structure forming step is performed. Firstly, an isolation structure such as a shallow trench isolation (STI) structure  102  is formed on a p-type substrate (p-sub). Due to the STI structure  102 , a region A and a region B are defined. The p-type substrate is covered by the STI structure  102 . The surface of the p-type substrate corresponding to the region A and the region B is exposed. The region B is a rectangular region. The region A is composed of two rectangular sub-regions A 1  and A 2 . In the subsequent steps, two serially-connected n-type transistors and an assist gate region are formed in the region A, and an erase gate region is formed in the region B. 
     Then, a well region forming step is performed. As shown in  FIG.  2 B , the region A is exposed, and a P-well region PW is formed in the surface of the p-type substrate corresponding to the region A. In an embodiment, no well region is formed in the region B. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, another P-well region (not shown) is formed in the surface of the p-type substrate corresponding to the region B. Alternatively, an N-well region (not shown) is formed in the surface of the p-type substrate corresponding to the region B. 
     Then, a gate structure forming step is performed. As shown in  FIG.   2 C , two gate oxide layers  103  and  105  are formed. Then, two polysilicon gate layers  113  and  115  are formed on the two gate oxide layers  103  and  105 , respectively. Consequently, two gate structures  123  and  125  are formed. 
     Please refer to  FIG.  2 C  again. The two gate structures  123  and  125  are formed on the surface of the region A. In addition, the region A is divided into three sub-regions by the two gate structures  123  and  125 . The gate structures  123  and  125  are formed on the surface corresponding to the sub-region A 1 . The first sub-region is located beside a left side of the gate structure  123 . The second sub-region is arranged between the right side of the gate structure  123  and the left side of the gate structure  125 . The third sub-region is located beside the right side of the gate structure  125  (including the sub-region A 2 ). In other words, the third sub-region is an L-shaped sub-region. 
     Moreover, two extension segments are externally extended from the gate structure  125  through the surface of the STI structure  102 . The first extension segment of the gate structure  125  is externally extended to the region B. In addition, a portion of the region B is covered by the first extension segment of the gate structure  125 . The second extension segment of the gate structure  125  is externally extended to the sub-region A 2  of the region A. In addition, a portion of the sub-region A 2  is covered by the second extension segment of the gate structure  125 . In this embodiment, the polysilicon gate layer  115  of the gate structure  125  is served as a floating gate. The polysilicon gate layer  113  of the gate structure  123  is served as a select gate. 
     Please refer to  FIG.  2 D . Then, a doped region forming step is performed. In an embodiment, a doping process is performed to form four n-type doped regions  141 ,  142 ,  143  and  145  by using the two gate structures  123  and  125  as the mask. That is, the n-type doped region  145  is formed in the portion of the region B that is not covered by the gate structure  125 . In addition, the three n-type doped regions  141 ,  142  and  143  are respectively formed in the three sub-regions of the region A that are not covered by the two gate structures  123  and  125 . 
     In the region A, the gate structure  123  and the two n-doped regions  141  and  142  on its two sides are collaboratively formed as a select transistor. In addition, the gate structure  125  and the two n-doped regions  142  and  143  on its two sides are collaboratively formed as a floating gate transistor. In this embodiment, the floating gate transistor and the select transistor are n-type transistors and constructed in the P-well region PW. That is, the body terminal of the floating gate transistor and the body terminal of the select transistor are connected to the P-well region PW. 
     The n-doped region  143  is a drain/source terminal of the floating transistor. In addition, the n-doped region  143  can be served as the assist gate region. That is, the second extension segment of the gate structure  125  is externally extended to a region beside the assist gate region. Consequently, the assist gate region and the gate structure  125  are collaboratively formed as an n-type transistor. In addition, the n-type transistor is connected as a MOS capacitor. 
     In the region B, the n-type doped region  145  is the erase gate region. The first extension segment of the gate structure  125  is externally extended to a region beside the erase gate region. Consequently, the erase gate region and the gate structure  125  are collaboratively formed as an n-type transistor. In addition, the n-type transistor is connected as another MOS capacitor. 
     Please refer to  FIG.  2 E . After a step of forming metal conductor lines is completed, the memory cell of this embodiment is fabricated. That is, the n-type doped region  141  is connected to a source line SL, the n-type doped region  143  is connected to a bit line BL, the n-type doped region  145  is connected to an erase line EL, and the polysilicon gate layer  113  is connected to a select gate line SG. 
     Due to a special structural design of the memory cell, the programming efficiency and the erasing efficiency are both enhanced. It is noted that the special structure design is not restricted. For example, as shown in  FIG.  2 F , there are two overlap regions A MF  and A AG  between the polysilicon gate layer  115  and the region A. The overlap region A MF  is located under the polysilicon gate layer  115  and arranged between the n-type doped regions  142  and  143 . In addition, the overlap region A MF  is a channel region of the floating gate transistor (i.e., an active region of the floating gate transistor). The overlap region A AG  is located in the third sub-region of region A under the polysilicon gate layer  115 . Three sides of the overlap region A AG  are next to the n-type doped region  143 . In addition, the overlap region A AG  is an active region of the assist gate region. Moreover, there is an overlap region A EG  between the polysilicon gate layer  115  and the region B. The overlap region A EG  is located in the region B under the polysilicon gate layer  115 . In addition, three sides of the overlapping region A EG  are next to the n-type doped region  145 . The overlap region A EG  is an active region of the erase gate region. The area A AG  of the active region of the assist gate region is larger than the area A EG  of the active region of the erase gate region (i.e., A AG  &gt; A EG ). Moreover, the sum of the area A AG  of the active region of the assist gate region and the area A EG  of the active region of the erase gate region is larger than the area A MF  of the active region of the floating gate transistor. That is, (A AG +A EG ) &gt; A MF . 
     Moreover, due to the special structural design of the memory cell, the size of the memory cell is reduced. For example, as shown in  FIG.  2 F , the channel region of the floating gate transistor is extended in a w-x direction (e.g., in a horizontal direction). The second extension segment of the polysilicon gate layer  115  (or the gate structure  125 ) is extended in a y-z direction (e.g., in the horizontal direction). In other words, the second extension segment of the polysilicon gate layer  115  is extended in the same direction as the channel region of the floating gate transistor. 
     As shown in  FIG.  2 G , the equivalent circuit of the memory cell of the first embodiment comprises a select transistor M S , a floating gate transistor M F , a capacitor C EG  and a capacitor C AG . Moreover, the capacitor C EG  and the capacitor C AG  are MOS capacitors. 
     The gate terminal of the select transistor M S  is connected to a select gate line SG. The first drain/source terminal of the select transistor M S  is connected to the source line SL. The first drain/source terminal of the floating gate transistor M F  is connected to the second drain/source terminal of the select transistor M S . The second drain/source terminal of the floating gate transistor M F  is connected to the bit line BL. The first terminal of the capacitor C EG  is connected to the floating gate  115  of the floating gate transistor M F . The second terminal of the capacitor C EG  is connected to the erase line EL. The first terminal of the capacitor C AG  is connected to the floating gate  115  of the floating gate transistor M F . The second terminal of the capacitor C AG  is connected to the bit line BL. 
     As mentioned above, the memory cell of the present invention comprises the assist gate region and the erase gate region. In comparison with the memory cell as shown in  FIG.  1 A , the memory cell of the present invention is a four-terminal memory cell. In addition, the size of the memory cell of the present invention is smaller. 
       FIG.  3 A  is a bias voltage table illustrating the bias voltages for performing a program action, an erase action and two read actions on the memory cell according to the first embodiment of the present invention.  FIG.   3 B  is a schematic circuit diagram the operations of performing the program action on the memory cell according to the first embodiment of the present invention.  FIG.  3 C  is a schematic circuit diagram the operations of performing the erase action on the memory cell according to the first embodiment of the present invention.  FIG.  3 D  is a schematic circuit diagram the operations of performing a first read action on the memory cell according to the first embodiment of the present invention.  FIG.  3 E  is a schematic circuit diagram the operations of performing a second read action on the memory cell according to the first embodiment of the present invention. 
     While the program action (PGM), the erase action (ERS) and the two read actions (Read_1 and Read_2) are performed, the P-well region PW receives a ground voltage (0V). Moreover, the erase voltage V EE  is higher than the program voltage V PP , the program voltage V PP  is higher than the read voltage V R , and the read voltage V R  is higher than the ground voltage (0V). For example, the erase voltage V EE  is 12V, the program voltage V PP  is 9V, and the read voltage V R  is 5V. 
     Please refer to  FIG.  3 B . While the program action is performed, the bit line BL receives a program voltage V PP , the source line SL receives the ground voltage (0V), the select gate line SG receives the program voltage V PP , and the erase line EL receives a voltage between the ground voltage (0V) and the erase voltage V EE . 
     While the program action is performed, the select transistor M S  is turned on, and a program current I P  is generated between the bit line BL and the source line SL. Therefore, when the hot carriers (e.g. electrons) in the program current I P  pass through the channel region of the floating gate transistor M F , a channel hot electron injection effect (CHE effect) is generated and the hot carriers are injected into the floating gate  115 . Furthermore, the capacitor C AG  may couple the program voltage V PP  received by the bit line BL to the floating gate  115 , so that the number of hot carriers injected into the floating gate  115  can be increased to improve the program efficiency. 
     Please refer to  FIG.  3 C . While the erase action is performed, the bit line BL receives the ground voltage (0V), the source line SL receives the ground voltage (0V), the select gate line SG receives the ground voltage (0V), and the erase line EL receives the erase voltage V EE . 
     While the erase action is performed, the select transistor M S  is turned off. Under this circumstance, a Fowler-Nordheim Tunneling (FN) effect is generated between the two terminals of the transistor C EG . Consequently, hot carriers are ejected from the floating gate  115  to the erase line EL. 
     Please refer to  FIG.  3 D . While the first read action is performed, the bit line BL receives the read voltage V R , the source line SL receives the ground voltage (0V), the select gate line SG receives the read voltage V R , and the erase line EL receives a voltage between the ground voltage (0V) and the erase voltage V EE . 
     While the first read action is performed, the select transistor M S  is turned on, and the read current I R  is generated between the bit line BL and the source line SL. The read current I R  flows from the bit line BL to the source line SL. The storage state of the memory cell can be determined according to the magnitude of the read current I R . For example, in case that the electrons are stored in the floating gate  115 , the magnitude of the read current I R  is very low (e.g., nearly zero). Consequently, it is determined that the memory cell is in a first storage state. Whereas, in case that no electrons are stored in the floating gate  115 , the magnitude of the read current I R  is high. Under this circumstance, it is determined that the memory cell is in a second storage state. 
     Please refer to  FIG.  3 E . While the second read action is performed, the source line SL receives the read voltage V R , the bit line BL receives the ground voltage (0V), the select gate line SG receives the read voltage V R , and the erase line EL receives a voltage between the ground voltage (0V) and the erase voltage V EE . 
     While the second read action is performed, the select transistor M S  is turned on, and the read current I R  is generated between the bit line BL and the source line SL. The read current I R  flows from the source line SL to the source line BL. The storage state of the memory cell can be determined according to the magnitude of the read current I R . For example, in case that the electrons are stored in the floating gate  115 , the magnitude of the read current I R  is very low (e.g., nearly zero). Consequently, it is determined that the memory cell is in the first storage state. Whereas, in case that no electrons are stored in the floating gate  115 , the magnitude of the read current I R  is very high. Under this circumstance, it is determined that the memory cell is in the second storage state. 
     Moreover, plural memory cells can be collaboratively formed as an array structure.  FIG.  4 A  is a schematic top view illustrating an array structure of with plural memory cells of the first embodiment.  FIG.  4 B  is a schematic circuit diagram illustrating the equivalent circuit of the array structure as shown in  FIG.  4 A . The array structure comprises eight memory cells in a 2x4 array. The array structure is connected to the source lines SL 1 , SL 2 , the select gate lines SG 1 , SG 2 , SG 3 , SG 4 , the bit lines BL 1 , BL 2 , and the erase line EL. The array structure comprises plural n-type doped regions  411 - 419 ,  431 - 439 ,  461 ~ 462  and plural polysilicon gate layers  421 - 428 ,  451 ~ 458 . 
     In some embodiments, in order to perform the first read action described in  FIG.  3 D , the source lines SL 1  and SL 2  in  FIG.  4 B  can be connected to each other. In some other embodiments, in order to perform the second read action described in  FIG.  3 E , the bit lines BL 1  and BL 2  in  FIG.  4 B  can be connected to each other. 
     The structure of each memory cell is similar to that of  FIG.  2 E . For succinctness, only the structure of the memory cell  c   22  will be described as follows, and the structures of the other memory cells are not redundantly described herein. In the memory cell  c   22  shown in  FIG.  4 A , the polysilicon gate layer  453  and the two n-doped regions  433  and  434  are collaboratively formed as a select transistor, and the polysilicon gate layer  454  and the two n-doped regions  434  and  435  are collaboratively formed as a floating gate transistor. The polysilicon gate layer  454  and the n-doped region  461  are collaboratively formed as an n-type transistor, and the n-type transistor is connected as a MOS transistor. In addition, the polysilicon gate layer  454  and the n-doped region  435  are collaboratively formed as an n-type transistor, and the n-type transistor is connected as another MOS transistor. 
     The n-type doped region  433  is connected to the source line SL 2 . The n-type doped region  435  is connected to the bit line BL 2 . The polysilicon gate layer  453  is connected to the select gate line SG 2 . The n-type doped region  461  is connected to the erase line EL. 
     The equivalent circuit of the array structure is shown in  FIG.  4 B . The array structure comprises four memory cells  c   11 ~ c   24  in a 2x4 array. The structures of these memory cells  c   11 ~ c   24  are identical. For succinctness, only the structure of the memory cell  c   11  will be described as follows, and the structures of the other memory cells are not redundantly described herein. 
     The connecting relationships between associated components of the memory cells  c   11  will be described as follows. The first drain/source terminal of the select transistor M S  is connected to the source line SL 1 . The gate terminal of the select transistor M S  is connected to the select gate line SG 1 . The first drain/source terminal of the floating gate transistor M F  is connected to the second drain/source terminal of the select transistor M S . The second drain/source terminal of the floating gate transistor M F  is connected to the bit line BL 1 . The first terminal of the capacitor C EG  is connected to the floating gate of the floating gate transistor M F . The second terminal of the capacitor C EG  is connected to the erase line EL. The first terminal of the capacitor C AG  is connected to the floating gate of the floating gate transistor M F . The second terminal of the capacitor C AG  is connected to the bit line BL 1 . 
     Similarly, by providing proper bias voltages to the source lines SL 1 , SL 2 , the select gate lines SG 1 , SG 2 , SG 3 , SG 4 , the bit lines BL 1 , BL 2 , and the erase line EL, a program action, an erase action or a read action can be selectively performed on the memory cells  c   11 ~ c   24  of the array structure. The magnitudes of the bias voltages are similar to those described in  FIG.  3 A . 
     In the embodiment, the transistors of the memory cell are n-type transistors. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, the n-type transistors are replaced by p-type transistors. In addition, the memory cell and the array structure with the p-type transistors can be implemented according to the teachings of the embodiment. 
       FIGS.  5 A to  5 E  schematically illustrate the steps of a method of manufacturing a single-poly non-volatile memory cell according to a second embodiment of the present invention. 
     As shown in  FIG.  5 A , an isolation structure forming step is performed. Firstly, an isolation structure such as a shallow trench isolation (STI) structure  502  is formed on a p-type substrate (p-sub). Due to the STI structure  502 , a region A and a region B are defined. The p-type substrate is covered by the STI structure  502 . The surface of the p-type substrate corresponding to the region A and the region B is exposed. In the subsequent steps, two serially-connected n-type transistors and an assist gate region are formed in the region A, and an erase gate region is formed in the region B. 
     Then, a well region forming step is performed. As shown in  FIG.  5 A , the region A is exposed, and a P-well region PW is formed in the surface of the p-type substrate corresponding to the region A. In an embodiment, no well region is formed in the region B. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, another P-well region (not shown) is formed in the surface of the p-type substrate corresponding to the region B. Alternatively, an N-well region (not shown) is formed in the surface of the p-type substrate corresponding to the region B. 
     Then, a gate structure forming step is performed. As shown in  FIG.  5 B , two gate oxide layers  503  and  505  are formed. Then, two polysilicon gate layers  513  and  515  are formed on the two gate oxide layers  503  and  505 , respectively. Consequently, two gate structures  523  and  525  are formed. 
     Please refer to  FIG.  5 B  again. The two gate structures  523  and  525  are formed on the surface of the region A. In addition, the region A is divided into four sub-regions by the two gate structures  523  and  525 . The first sub-region is located beside a right side of the gate structure  523 . The second sub-region is arranged between the left side of the gate structure  523  and the right side of the gate structure  525 . The third sub-region and the fourth sub-region are located beside two sides of the extension segment of the gate structure  525 . 
     In this embodiment, the polysilicon gate layer  515  of the gate structure  525  is served as a floating gate. The polysilicon gate layer  513  of the gate structure  523  is served as a select gate. 
     Please refer to  FIG.  5 C . Then, a doped region forming step is performed. In an embodiment, a doping process is performed to form five n-type doped regions  541 ,  542 ,  543 ,  544  and  545  by using the two gate structures  523  and  525  as the mask. That is, the n-type doped region  545  is formed in the portion of the region B that is not covered by the gate structure  525 . In addition, the four n-type doped regions  541 ,  542 ,  543  and  544  are respectively formed in the four sub-regions of the region A that are not covered by the two gate structures  523  and  525 . 
     In the region A, the gate structure  523  and the two n-doped regions  541  and  542  on its two sides are collaboratively formed as a select transistor. In addition, the gate structure  525  and the two n-doped regions  542  and  543  on its two sides are collaboratively formed as a floating gate transistor. In this embodiment, the floating gate transistor and the select transistor are n-type transistors and constructed in the P-well region PW. That is, the body terminal of the floating gate transistor and the body terminal of the select transistor are connected to the P-well region PW. 
     The n-doped region  543  is a drain/source terminal of the floating transistor. In addition, the n-doped region  543  can be served as the assist gate region. That is, the extension segment of the gate structure  525  is extended to a region beside the assist gate region. Consequently, the assist gate region and the gate structure  525  are collaboratively formed as an n-type transistor. In addition, the n-type transistor is connected as a MOS capacitor. 
     In the region B, the n-type doped region  545  is the erase gate region. The extension segment of the gate structure  525  is externally extended to a region beside the erase gate region. Consequently, the erase gate region and the gate structure  525  are collaboratively formed as an n-type transistor. In addition, the n-type transistor is connected as another MOS capacitor. 
     It is noted that the extension segment of the gate structure  525  can also be designed to cover the A region and is extended to the B region along the edge of the A region in another embodiment. Therefore, the area A is divided into three sub-regions. In addition, after the doped region forming step, only three n-type doped regions  541 ,  542 ,  543  are formed, and there is no n-doped region  544  in  FIG.  5 C . 
     Please refer to  FIG.  5 D . After a step of forming metal conductor lines is completed, the memory cell of this embodiment is fabricated. That is, the n-type doped region  541  is connected to a source line SL, the n-type doped region  543  is connected to a bit line BL, the n-type doped region  545  is connected to an erase line EL, and the polysilicon gate layer  513  is connected to a select gate line SG. 
     The equivalent circuit of the memory cell of the second embodiment is a four-terminal memory cell. Furthermore, the equivalent circuit is similar to that of  FIG.  2 G  and is not redundantly described herein. 
     Due to a special structural design of the memory cell, the programming efficiency and the erasing efficiency are both enhanced. It is noted that the special structure design is not restricted. For example, as shown in  FIG.  5 E , there are two overlap regions A MF  and A AG  between the polysilicon gate layer  515  and the region A. The overlap region A MF  is located under the polysilicon gate layer  515  and arranged between the n-type doped regions  542  and  543 . In addition, the overlap region A MF  is a channel region of the floating gate transistor (i.e., an active region of the floating gate transistor). The overlap region A AG  is located under the extension segment of the polysilicon gate layer  515  and arranged between the n-type doped regions  543  and  544 . In addition, the overlap region A AG  is an active region of the assist gate region. Moreover, there is an overlap region A EG  in the region B under the polysilicon gate layer  515 . In addition, three sides of the overlapping region A EG  are next to the n-type doped region  545 . The overlap region A EG  is an active region of the erase gate region. The area A AG  of the active region of the assist gate region is larger than the area A EG  of the active region of the erase gate region (i.e., A AG  &gt; A EG ). Moreover, the sum of the area A AG  of the active region of the assist gate region and the area A EG  of the active region of the erase gate region is larger than the area A MF  of the active region of the floating gate transistor. That is, (A AG +A EG ) &gt; A MF . 
     Moreover, due to the special structural design of the memory cell, the size of the memory cell is reduced. For example, as shown in  FIG.  5 E , the channel region of the floating gate transistor is extended in a w-x direction (e.g., in a horizontal direction). The extension segment of the polysilicon gate layer  115  (or the gate structure  125 ) is extended in a y-z direction (e.g., in the horizontal direction). In other words, the extension segment of the polysilicon gate layer  515  is extended in the same direction as the channel region of the floating gate transistor. 
     Moreover, plural memory cells can be collaboratively formed as an array structure.  FIG.  6 A  is a schematic top view illustrating an array structure of with plural memory cells of the second embodiment.  FIG.  6 B  is a schematic circuit diagram illustrating the equivalent circuit of the array structure as shown in  FIG.  6 A . The array structure comprises four memory cells in a 2x2 array. The array structure is connected to the source lines SL 1 , SL 2 , the select gate lines SG 1 , SG 2 , the bit lines BL 1 , BL 2 , and the erase line EL. The array structure comprises plural n-type doped regions  611 ~ 627  and plural polysilicon gate layers  631 ~ 636 . 
     The structure of each memory cell is similar to that of  FIG.  5 E . For succinctness, only the structure of the memory cell  c   12  will be described as follows, and the structures of the other memory cells are not redundantly described herein. In the memory cell  c   12 , the polysilicon gate layer  631  and the two n-doped regions  611  and  612  are collaboratively formed as a select transistor, and the polysilicon gate layer  632  and the two n-doped regions  612  and  613  are collaboratively formed as a floating gate transistor. The polysilicon gate layer  632  and the n-doped region  627  are collaboratively formed as an n-type transistor, and the n-type transistor is connected as a MOS transistor. In addition, the polysilicon gate layer  632  and the n-doped region  613  are collaboratively formed as an n-type transistor, and the n-type transistor is connected as another MOS transistor. 
     The n-type doped region  611  is connected to the source line SL 1 . The n-type doped region  613  is connected to the bit line BL 1 . The polysilicon gate layer  631  is connected to the select gate line SG 2 . The n-type doped region  627  is connected to the erase line EL. 
     The equivalent circuit of the array structure is shown in  FIG.  6 B . The array structure comprises four memory cells  c   11 ~ c   22  in a 2×2 array. The structures of these memory cells  c   11 ~ c   22  are identical. For succinctness, only the structure of the memory cell  c   11  will be described as follows, and the structures of the other memory cells are not redundantly described herein. 
     The connecting relationships between associated components of the memory cells  c   11  will be described as follows. The first drain/source terminal of the select transistor M S  is connected to the source line SL 1 . The gate terminal of the select transistor M S  is connected to the select gate line SG 1 . The first drain/source terminal of the floating gate transistor M F  is connected to the second drain/source terminal of the select transistor M S . The second drain/source terminal of the floating gate transistor M F  is connected to the bit line BL 1 . The first terminal of the capacitor C EG  is connected to the floating gate of the floating gate transistor M F . The second terminal of the capacitor C EG  is connected to the erase line EL. The first terminal of the capacitor C AG  is connected to the floating gate of the floating gate transistor M F . The second terminal of the capacitor C AG  is connected to the bit line BL 1 . 
     Similarly, by providing proper bias voltages to the source lines SL 1 , SL 2 , the select gate lines SG 1 , SG 2 , the bit lines BL 1 , BL 2 , and the erase line EL, a program action, an erase action or a read action can be selectively performed on the memory cells  c   11 ~ c   22  of the array structure. The magnitudes of the bias voltages are similar to those described in  FIG.  3 A  and  FIG.  4 B . 
     In some embodiments, in order to perform the first read action described in  FIG.  3 D , the source lines SL 1  and SL 2  in  FIG.  6 B  can be connected to each other. In some other embodiments, in order to perform the second read action described in  FIG.  3 E , the bit lines BL 1  and BL 2  in  FIG.  6 B  can be connected to each other. 
       FIG.  7    is a schematic top view illustrating a single-poly non-volatile memory cell of the third embodiment and an associated array structure of with plural memory cells. The array structure comprises plural n-type doped regions  711 - 719  and plural polysilicon gate layers  731 ~ 733 . The memory cell of the third embodiment is similar to the memory cell of the second embodiment. 
     In  FIG.  6 A , the n-doped region  613  of the memory cell  c   12  of the second embodiment is connected with the n-doped region  617  of the adjacent memory cell by a metal conductor line BL 1 . In comparison with the second embodiment in  FIG.  6 A , the memory cell  c   12  of the third embodiment shares the n-doped region  713  with the memory cell  c   22  in  FIG.  7   , the memory cell  c   11  of the third embodiment shares the n-doped region  719  with the memory cell  c   21  in  FIG.  7   , and both the n-doped region  713 ,  719  are connected with the metal conductor line BL. 
     The equivalent circuit of the memory cell of the third embodiment is similar to the equivalent circuit of the memory cell of the second embodiment and is not redundantly described herein. Moreover, the equivalent circuit of the array structure of  FIG.  7    is similar to the array structure shown in  FIG.  6 B  and is not redundantly described herein. 
     Similarly, by providing proper bias voltages to the source lines SL 1 , SL 2 , the select gate lines SG 1 , SG 2 , the bit line BL, and the erase line EL, a program action, an erase action or a read action can be selectively performed on the memory cells  c   11 ~ c   22  of the array structure in  FIG.  7   . The magnitudes of the bias voltages are similar to those described in  FIG.  3 A . Since the memory cells  c   11 ~ c   22  of the array structure are connected to the bit line BL, the total size of the array structure in  FIG.  7    can be reduced and only the second read action described in  FIG.  3 E  can be performed on the array structure. 
       FIG.  8 A  illustrates a single-poly non-volatile memory cell according to a fourth embodiment of the present invention.  FIG.  8 B  is a schematic equivalent circuit diagram of the single-poly non-volatile memory cell according to the fourth embodiment of the present invention.  FIG.  8 C  is a bias voltage table illustrating the bias voltages for performing a program action, an erase action and two read actions on the memory cell according to the fourth embodiment of the present invention. 
     In comparison with memory cell of the first embodiment in  FIG.  2 E , the memory cell of the fourth embodiment shown in  FIG.  8 A  further comprises a gate structure  821  formed on the STI structure  102  and the gate structure  821  is located beside one side of the gate structure  125 . The gate structure  821  includes a gate oxide layer  801  formed on the surface of the STI structure  102  and a polysilicon gate layer  811  formed on the gate oxide layer  801 . Furthermore, the polysilicon gate layer  811  is connected with an assist gate line AG. Also, the polysilicon gate layer  811  and the polysilicon gate layer  115  are collaboratively formed as a poly/poly plate capacitor. 
     As shown in  FIG.  8 B , the first terminal of the poly/poly plate capacitor C AGP  is connected to the floating gate  115  of the floating gate transistor M F  and the second terminal of the poly/poly plate capacitor C AGP  is connected to the assist gate line AG. 
     In comparison with the bias voltage table in  FIG.  3 A , the bias table in  FIG.  8 C  further comprises a bias voltage for the assist gate line AG. For succinctness, only the bias voltage on the assist gate line AG will be described as follows, and the other bias voltages are not redundantly described herein. 
     While the program action (PGM) is performed, the assist gate line AG receives a voltage between the ground voltage (0V) and a positive assist gate voltage V AG . While the erase action (ERS) is performed, the assist gate line AG receives a voltage between a negative assist gate voltage -V AG  and the ground voltage (0V). While the first read action or the second read action is performed, the assist gate line AG receives a voltage between the negative assist gate voltage -V AG  and the positive assist gate voltage V AG . For example, the positive assist gate voltage V AG  is 10V. 
       FIG.  9    illustrates a single-poly non-volatile memory cell according to a fifth embodiment of the present invention. 
     In comparison with memory cell of the second embodiment in  FIG.  5 D , the memory cell of the fifth embodiment shown in  FIG.  9    further comprises a gate structure  921  formed on the STI structure  502  and the gate structure  921  is located beside one side of the gate structure  525 . The gate structure  921  includes a gate oxide layer  901  formed on the surface of the STI structure  502  and a polysilicon gate layer  911  formed on the gate oxide layer  901 . Furthermore, the polysilicon gate layer  911  is connected with the assist gate line AG. Also, the polysilicon gate layer  911  and the polysilicon gate layer  515  are collaboratively formed as a poly/poly plate capacitor. In some embodiment, the gate structure  921  can be shared with the adjacent cell in a memory array. 
     The equivalent circuit of the memory cell of the fifth embodiment is identical to the equivalent circuit of the memory cell of the fourth embodiment shown in  FIG.  8 B . Moreover, the bias voltages for the program action, erase action and read action are similar to those described in  FIG.  8 C . and is not redundantly described herein. 
     From the above descriptions, the present invention provides an erasable programmable single-poly non-volatile memory cell and an associated array structure. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.