Patent Publication Number: US-2005129043-A1

Title: Nonblocking and deterministic multicast packet scheduling

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
      This application is related to and claims priority of U.S. Provisional Patent Application Ser.No. 60/516,265, filed on 30, Oct. 2003. This application is U.S. patent application to and incorporates by reference in its entirety the related PCT Application Docket No. S-0006 entitled “NONBLOCKING AND DETERMINISTIC MULTICAST PACKET SCHEDULING” by Venkat Konda assigned to the same assignee as the current application, and filed concurrently. This application is related to and incorporates by reference in its entirety the related U.S. patent application Ser. No. 09/967,815 entitled “REARRANGEABLY NON-BLOCKING MULTICAST MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed on 27, Sep. 2001 and its Continuation In Part PCT Application Serial No. PCT/US 03/27971 filed on 6, Sep. 2003. This application is related to and incorporates by reference in its entirety the related U.S. patent application Ser. No. 09/967,106 entitled “STRICTLY NON-BLOCKING MULTICAST MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed on 27, Sep. 2001 and its Continuation In Part PCT application Serial No. PCT/US 03/27972 filed on 6, Sep. 2003.  
      This application is related to and incorporates by reference in its entirety the related U.S. Provisional Patent Application Ser. No. 60/500,790 filed on 6, Sep. 2003 and its U.S. patent application Ser. No. 10/933,899 as well as its PCT application Serial No. 04/29043 filed on 5, Sep. 2004. This application is related to and incorporates by reference in its entirety the related U.S. Provisional Patent Application Ser. No. 60/500,789 filed on 6, Sep. 2003 and its U.S. patent application Ser. No. 10/933,900 as well as its PCT application Serial No. 04/29027 filed on 5, Sep. 2004.  
      This application is related to and incorporates by reference in its entirety the related U.S. Provisional Patent Application Ser. No. 60/516,057, filed 30, Oct. 2003 and its U.S. Patent Application Docket No. V-0005 as well as its PCT Application Docket No. S-0005 filed concurrently. This application is related to and incorporates by reference in its entirety the related U.S. Provisional Patent Application Ser. No. 60/516,163, filed 30, Oct. 2003 and its U.S. Patent Application Docket No. V-0009 as well as its PCT Application Docket No. S-0009 filed concurrently. This application is related to and incorporates by reference in its entirety the related U.S. Provisional Patent Application Ser. No. 60/515,985, filed 30, Oct. 2003 and its U.S. patent application Docket No. V-0010 as well as its PCT Application Docket No. S-0010 filed concurrently. 
    
    
     BACKGROUND OF INVENTION  
      Today&#39;s ATM switches and IP routers typically employ many types of interconnection networks to switch packets from input ports (also called “ingress ports”) to the desired output ports (also called “egress ports”). To switch the packets through the interconnection network, they are queued either at input ports, or output ports, or at both input and output ports. A packet may be destined to one or more output ports. A packet that is destined to only one output port is called unicast packet, a packet that is destined to more than one output port is called multicast packet, and a packet that is destined to all the output ports is called broadcast packet.  
      Output-queued (OQ) switches employ queues only at the output ports. In output-queued switches when a packet is received on an input port it is immediately switched to the destined output port queues. Since the packets are immediately transferred to the output port queues, in an r*r output-queued switch it requires a speedup of r in the interconnection network. Input-queued (IQ) switches employ queues only at the input ports. Input-queued switches require a speedup of only one in the interconnection network; Alternatively in IQ switches no speedup is needed. However input-queued switches do not eliminate Head of line (HOL) blocking, meaning if the destined output port of a packet at the head of line of an input queue is busy at a switching time, it also blocks the next packet in the queue even if its destined output port is free.  
      Combined-input-and-output queued (CIOQ) switches employ queues at both its input and output ports. These switches achieve the best of the both OQ and IQ switches by employing a speedup between 1 and r in the interconnection network. Another type of switches called Virtual-output-queued (VOQ) switches is designed with r queues at each input port, each corresponding to packets destined to one of each output port. VOQ switches eliminate HOL blocking.  
      VOQ switches have received a great attention in the recent years. An article by Nick Mckeown entitled, “The iSLIP Scheduling Algorithm for Input-Queued Switches”, IEEE/ACM Transactions on Networking, Vol. 7, No. 2, April 1999 is incorporated by reference herein as background of the invention. This article describes a number of scheduling algorithms for crossbar based interconnection networks in the introduction section on page 188 to page 190.  
      U.S. Pat. No. 6,212,182 entitled “Combined Unicast and Multicast Scheduling” granted to Nick Mckeown that is incorporated by reference as background describes a VOQ switching technique with r unicast queues and one multicast queue at each input port. At each switching time, an iterative arbitration is performed to switch one packet to each output port.  
      U.S. Pat. No. 6,351,466 entitled “Switching Systems and Methods of Operation of Switching Systems” granted to Prabhakar et al. that is incorporated by reference as background describes a VOQ switching technique in a crossbar interconnection network with r unicast queues at each input port and one queue at each output port requires a speedup of at least four performs as if it were output-queued switch including the accurate control of packet latency.  
      However there are many problems with the prior art of switch fabrics. First, HOL blocking for multicast packets is not eliminated. Second, mathematical minimum speedup in the interconnection is not known. Third, speedup in the interconnection network is used to flood the output ports, which creates unnecessary packet congestion in the output ports, and rate reduction to transmit packets out of the egress ports. Fourth, arbitrary fan-out multicast packets are not scheduled in nonblocking manner to the output ports. Fifth, at each switching time packet arbitration is performed iteratively that is expensive in switching time, cost and power. Sixth and lastly, the current art performs scheduling in greedy and non-deterministic manner and thereby requiring segmentation and reassembly at the input and output ports.  
     SUMMARY OF INVENTION  
      A system for scheduling multicast packets through an interconnection network having a plurality of input ports, a plurality of output ports, and a plurality of input queues, comprising multicast packets, at each input port is operated in nonblocking manner in accordance with the invention by scheduling at most as many packets equal to the number of input queues from each input port to each output port. The scheduling is performed so that each multicast packet is fan-out split through not more than two interconnection networks and not more than two switching times. The system is operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs arbitration in only one iteration, with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In another embodiment each output port also comprises a plurality of output queues and each packet is transferred to an output queue in the destined output port in nonblocking and deterministic manner and without the requirement of segmentation and reassembly of packets even when the packets are of variable size. In one embodiment the scheduling is performed in strictly nonblocking manner with a speedup of at least three in the interconnection network. In another embodiment the scheduling is performed in rearrangeably nonblocking manner with a speedup of at least two in the interconnection network. The system also offers end to end guaranteed bandwidth and latency for multicast packets from input ports to output ports. In all the embodiments, the interconnection network may be a crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.  
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       FIG. 1A  is a diagram of an exemplary four by four port switch fabric with input and output multicast queues containing short packets and a speedup of three in the crossbar based interconnection network, in accordance with the invention;  FIG. 1B  is a high-level flowchart of an arbitration and scheduling method  40 , according to the invention, used to switch packets from input ports to output ports;  FIG. 1C  is a diagram of a three-stage network similar in scheduling switch fabric  10  of  FIG. 1A ;  FIG. 1D ,  FIG. 1E ,  FIG. 1F ,  FIG. 1G , and  FIG. 1H  show the state of switch fabric  10  of  FIG. 1A , after nonblocking and deterministic packet switching, in accordance with the invention, in five consecutive switching times.  
       FIG. 1I  shows a diagram of an exemplary four by four port switch fabric with input and output multicast queues containing long packets and a speedup of three in the crossbar based interconnection network, in accordance with the invention;  FIG. 1J ,  FIG. 1K ,  FIG. 1L , and  FIG. 1M  show the state of switch fabric  16  of  FIG. 1I , after nonblocking and deterministic packet switching without segmentation and reassembly of packets, in accordance with the invention, after four consecutive fabric switching cycles;  FIG. 1N  is a diagram of an exemplary four by four port switch fabric with input and output multicast queues and a speedup of two in the crossbar based interconnection network, in accordance with the invention.  
       FIG. 2A  is a diagram of an exemplary four by four port switch fabric with input multicast queues and a speedup of three in the crossbar based interconnection network, in accordance with the invention;  FIG. 2B ,  FIG. 2C ,  FIG. 2D ,  FIG. 2E , and  FIG. 2F  show the state of switch fabric  20  of  FIG. 2A , after nonblocking and deterministic packet switching, in accordance with the invention, in five consecutive switching times.  
       FIG. 3A  is a diagram of an exemplary four by four port switch fabric with input and output multicast queues, and a speedup of three in link speed and clock speed in the crossbar based interconnection network, in accordance with the invention;  FIG. 3B  is a diagram of an exemplary four by four port switch fabric with input and output multicast queues and a speedup of three in the shared memory based interconnection network, in accordance with the invention;  FIG. 3C  is a diagram of an exemplary four by four port switch fabric with input and output multicast queues, and a speedup of three in link speed and clock speed in the shared memory based interconnection network, in accordance with the invention;  FIG. 3D  is a diagram of an exemplary four by four port switch fabric with input and output multicast queues and a speedup of three in the hypercube based interconnection network, in accordance with the invention;  FIG. 3E  is a diagram of an exemplary four by four port switch fabric with input and output multicast queues, and a speedup of three in link speed and clock speed in the hypercube based interconnection network, in accordance with the invention.  
       FIG. 4A  is a diagram of a general r*r port switch fabric with input and output multicast queues and a speedup of three in the crossbar based interconnection network, in accordance with the invention;  FIG. 4B  is a diagram of a general r*r port switch fabric with input and output multicast queues, and a speedup of three in link speed and clock speed in the crossbar based interconnection network, in accordance with the invention;  FIG. 4C  is a diagram of a general r*r port switch fabric with input and output multicast queues and a speedup of three in the shared memory based interconnection network, in accordance with the invention;  FIG. 4D  is a diagram of a general r*r port switch fabric with input and output multicast queues, and a speedup of three in link speed and clock speed in the shared memory based interconnection network, in accordance with the invention;  FIG. 4E  is a diagram of a general r*r port switch fabric with input and output multicast queues and a speedup of three in the three-stage clos network based interconnection network, in accordance with the invention;  FIG. 4F  is a diagram of a general r*r port switch fabric with input and output multicast queues, and a speedup of three in link speed and clock speed in the three-stage clos network based interconnection network, in accordance with the invention;  FIG. 4G  shows a detailed diagram of a four by four port (2-rank) hypercube based interconnection network in one embodiment of the middle stage interconnection network  131 - 133  in switch fabric  70  of  FIG. 3D  and switch fabric  80  of  FIG. 3E .  
       FIG. 5A  is an intermediate level implementation of the act  44  of the arbitration and scheduling method  40  of  FIG. 1B ;  FIG. 5B  is a low-level flow chart of one variant of scheduling acts of the act  44  of  FIG. 5A .  
       FIG. 6A  is an intermediate level implementation of the act  44  of the arbitration and scheduling method  40  of  FIG. 1B , with linear time complexity scheduling method;  FIG. 6B  is a low-level flow chart of one variant of act  44  of  FIG. 6A . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
      The present invention is concerned about the design and operation of nonblocking and deterministic scheduling in switch fabrics regardless of the nature of the traffic, including unicast and arbitrary fan-out multicast packets, arriving at the input ports. Specifically the present invention is concerned about the following issues in packet scheduling systems: 1) Strictly and rearrangeably nonblocking of packet scheduling; 2) Deterministically switching the packets from input ports to output ports (if necessary to specific output queues at output ports) i.e., without congesting output ports; 3) Without requiring the implementation of segmentation and reassembly (SAR) of the packets; 4) Arbitration in only one iteration; 5) Using mathematical minimum speedup in the interconnection network; and 6) yet operating at 100% throughput and in fair manner even when the packets are of variable size.  
      When a packet at an input port is destined to more than one output ports, it requires one-to-many transfer of the packet and the packet is called a multicast packet. When a packet at an input port is destined to only one output port it requires one-to-one transfer of the packet and the packet is called a unicast packet. When a packet at an input port is destined to all output ports, it requires one-to-all transfer of the packet and the packet is called a broadcast packet. In general, a multicast packet is meant to be destined to more than one output ports, which includes unicast and broadcast packets. A set of multicast packets to be transferred through an interconnection network is referred to as a multicast assignment. A multicast packet assignment in a switch fabric is nonblocking if any of the available packets at input ports can always be transferred to any of the available output ports.  
      The switch fabrics of the type described herein employ virtual output queues (VOQ) at input ports. In one embodiment, the packets received at each input port are arranged into as many queues as there are output ports. Each queue holds packets that are destined to only one of the output ports. Accordingly unicast packets are placed in the corresponding input queues corresponding to its destination output port, and multicast packets are placed in any one of the input queues corresponding to one of its destination output ports. The switch fabric may or may not have output queues at the output ports. When there are output queues, in one embodiment, there will be as many queues at each output port as there are input ports. The packets are switched to output queues so that each output queue holds packets switched from only one input port.  
      In certain switch fabrics of the type described herein, each input queue in all the input ports, comprising arbitrary fan-out multicast packets with constant rates, allocate equal bandwidth in the output ports. The nonblocking and deterministic switch fabrics with each input queue in all the input ports, having unicast packets with constant rates, allocate equal bandwidth in the output ports are described in detail in U.S. Patent Application, Attorney Docket No. V-0005 and its PCT Application, Attorney Docket No. S-0005 that is incorporated by reference above. The nonblocking and deterministic switch fabrics with the each input queue, having multirate unicast packets, allocate different bandwidth in the output ports are described in detail in U.S. Patent Application, Attorney Docket No. V-0009 and its PCT Application, Attorney Docket No. S-0009 that is incorporated by reference above. The nonblocking and deterministic switch fabrics with the each input queue, having multirate multicast packets, allocate different bandwidth in the output ports are described in detail in U.S. Patent Application, Attorney Docket No. V-0010 and its PCT Application, Attorney Docket No. S-0010 that is incorporated by reference above.  
      Referring to  FIG. 1A , an exemplary switch fabric  10  with an input stage  110  consists of four input ports  151 - 154  and an output stage  120  consists of four output ports  191 - 194  via a middle stage  130  of an interconnection network consists of three four by four crossbar networks  131 - 133 . Each input port  151 - 154  receives multicast packets through the inlet links  141 - 144  respectively. Each out port  191 - 194  transmits multicast packets through the outlet links  201 - 204  respectively. Each crossbar network  131 - 133  is connected to each of the four input ports  151 - 154  through eight links (hereinafter “first internal links”) FL 1 -FL 8 , and is also connected to each of the four output ports  191 - 194  through eight links (hereinafter “second internal links”) SL 1 -SL 8 . In switch fabric  10  of  FIG. 1A  each of the inlet links  141 - 144 , first internal links FL 1 -FL 8 , second internal links SL 1 -SL 8 , and outlet links  201 - 204  operate at the same rate.  
      At each input port  151 - 154  multicast packets received through the inlet links  141 - 144  are sorted according to their destined output port into as many input queues  171 - 174  (four) as there are output ports so that packets destined to output ports  191 - 194  are placed in input queues  171 - 174  respectively in each input port  151 - 154 . In one embodiment, as shown in switch fabric  10  of  FIG. 1A , before the multicast packets are placed in input queues they may also be placed in prioritization queues  161 - 164 . Each prioritization queue  161 - 164  contains f queues holding multicast packets corresponding to the priority of [ 1 -f]. For example the packets destined to output port  191  are placed in the prioritization queue  161  based on the priority of the packets [ 1 -f], and the highest priority packets are placed in input queue  171  first before the next highest priority packet is placed. The usage of priority queues  161 - 164  is not relevant to the operation of switch fabric  10 , and so switch fabric  10  in  FIG. 1A  could also be implemented without the prioritization queues  161 - 164  in another embodiment. (The usage of priority queues is not relevant to all the embodiments described in the current invention and so all the embodiments can also be implemented without the prioritization queues in nonblocking and deterministic manner.)  
      The network also includes a scheduler coupled with each of the input stage  110 , output stage  120  and middle stage  130  to switch packets from input ports  151 - 154  to output ports  191 - 194 . The scheduler maintains in memory a list of available destinations for the path through the interconnection network in the middle stage  130 .  
      In one embodiment, as shown in  FIG. 1A , each output port  191 - 194  consists of as many output queues  181 - 184  as there are input ports (four), so that packets switched from input ports  151 - 154  are placed in output queues  181 - 184  respectively in each output port  191 - 194 . Each input queue  171 - 174  in the four input ports  151 - 154  in switch fabric  10  of  FIG. 1A  shows an exemplary four packets with A 1 -A 4  in the input queue  171  of input port  151  and with P 1 -P 4  in the fourth input queue  174  of the input port  164  ready to be switched to the output ports. The head of line packets in all the 16 input queues in the four input ports  151 - 154  are designated by A 1 -P 1  respectively.  
      Table 1 shows an exemplary packet assignment between input queues and output queues in switch fabric  10  of  FIG. 1A . Unicast packets in input queue  171  in input port  151  denoted by I{1,1} are assigned to be switched to output queue  181  in output port  191  denoted by O{1,1}. Unicast packets in input queue  172  in input port  151  denoted by I{1,2} are assigned to be switched to output queue  181  in output port  192  denoted by O{2,1}. Similarly packets in the rest of 16 input queues are assigned to the rest of 16 output queues as shown in Table 1. In another embodiment, input queue to output queue assignment may be different from Table 1, but in accordance with the current invention, there will be only one input queue in each input port assigned to switch packets to an output queue in each output port and vice versa.  
               TABLE 1                          Input Queue to Output Queue Unicast Packet       Assignment in  FIG. 1A                               Packets from   Packets from   Packets from   Packets from       input port 151   input port 152   input port 153   input port 154               I{1,1}      I{2,1}   O{1,2}   I{3,1}   O{1,3}   I{4,1}   O{1,4}       O{1,1}       I{1,2}      I{2,2}   O{2,2}   I{3,2}   O{2,3}   I{4,2}   O{2,4}       O{2,1}       I{1,3}      I{2,3}   O{3,2}   I{3,3}   O{3,3}   I{4,3}   O{3,4}       O{3,1}       I{1,4}      I{2,4}   O{4,2}   I{3,4}   O{4,3}   I{4,4}   O{4,4}       O{4,1}                  
 
      To characterize a multicast assignment, for each input queue I{x,y} where x,y ε[1-4], let I{x,y}=OP, where OP  ⊂ {1,2,3,4} denote the subset of output ports to which a multicast packet in input queue I{x,y} is destined. In one embodiment, multicast packets from input queue I{x,a}=OP{a,b,c,d} are switched to the output queues O{a,x}, O{b,x}, O{c,x}, and O{d,x} in the four output ports a, b, c, and d. For example, a multicast packet in input queue I{1,1}=OP{1,2} is switched to output queues O{1,1} and O{2,1}. Similarly a multicast packet in input queue I{1,1}=OP{1,2,3,4} is switched to output queues O{1,1}, O{2,1}, O{3,1}, and O{4,1}.  
      A multicast packet received on inlet link  141  with OP ε{1,2,3,4} may be placed in any one of the input queues I{1,1}, I{1,2}, I{1,3}, and I{1,4}, since the packet&#39;s destination output ports are all the output ports  191 - 194 . However applicant notes that once the multicast packet is placed, say in input queue I{1,1}, the rest of the following packets with the same source and destination addresses will be placed in the same input queue, so that packet order is maintained as they are received by inlet link  141 . For example, the multicast packet may also be placed in input queue I{1,2}=OP{1,2,3,4}; then it is switched to output queues O{1,1}, O{2,1}, O{3,1}, and O{4,1}. So irrespective of in which input queue it is placed, it will be switched to the same output queues in the destined output ports. Also it must be observed that the multicast packet with OP ε{1,2,3,4} in switch fabric  10  of  FIG. 1A  (once granted by the output ports) does not let any other packet to be switched to the output ports in a fabric switching cycle, because it is switched to all the four output ports  191 - 194 .  
      Table 2 shows an exemplary set of multicast packet requests received through inlet links  141 - 144  by input queues of the input ports in switch fabric  10  of  FIG. 1A . Multicast packets in input queue I{1,1} are destined to be switched to output queues O{1,1}, O{2,1}, and O{3,1}. Multicast packets in input queue I{1,2} are destined to be switched to output queues O{1,1} and O{2,1}. Similarly the rest of 16 input queues have multicast packets assigned to the destined output queue as shown in Table 2.  
      Applicant observes that when the input queues contain multicast packets as shown in Table 2, there arises input port contention. Each inlet link receives at most one packet in each switching time and four packets in four switching times (hereinafter “a fabric switching cycle). Since each output port can receive at most four packets in a fabric switching cycle, all the received multicast packets in the input queues of each input port cannot be switched to output ports thus arising input port contention. And so only a few of them will be selected to be switched to output ports.  
               TABLE 2                       An Exemplary Set of Multicast Packet Requests       received by the input ports in  FIG. 1A                                                  Packet requests at   Packet requests at           Input port 151   Input port 152                       I{1,1}   OP{1,2,3}   I{2,1}   OP{1,2,4}           I{1,2}   OP{1,2}   I{2,2}   OP{1,2,3}           I{1,3}   OP{3,4}   I{2,3}   OP{3}           I{1,4}   OP{4}   I{2,4}   OP{4}                       Packet requests at   Packet requests at           Input port 153   Input port 154                       I{3,1}   OP{1}   I{4,1}   OP{1,2,3,4}           I{3,2}   OP{2,4}   I{4,2}   OP{1,2}           I{3,3}   OP{3}   I{4,3}   OP{3,4}           I{3,4}   OP{1,3}   I{4,4}   OP{4}                      
 
       FIG. 1B  shows an arbitration and scheduling method, in accordance with the current invention, in one embodiment with three four by four crossbar networks  131 - 133  in the middle stage  130 , i.e., with a speedup of three, to operate switch fabric  10  of  FIG. 1A  in strictly nonblocking and deterministic manner. The specific method used in implementing the strictly non-blocking and deterministic switching can be any of a number of different methods that will be apparent to a skilled person in view of the disclosure. One such arbitration and scheduling method is described below in reference to  FIG. 1B .  
      The arbitration part of the method  40  of  FIG. 1B  (described in detail later) comprises three steps: namely the generation of requests by the input ports, the issuance of grants by the output ports and the acceptance of the grants by the input ports. Since only four packets can be received by the output ports in each fabric switching cycle without congesting the output ports, only four packets can be switched from input ports, counting a multicast packet as many times as its fan-out Accordingly arbitration is performed to select at most four packets to be switched from each input port in a fabric switching cycle. Table 3 shows the four packets that will be switched to the output ports after the input contention is resolved for the packets shown in Table 2. The particular arbitration selection criteria used to resolve the input port contention is not relevant to the current invention as long as the multicast packets are selected so that only four packets are switched from each input port in each fabric switching cycle.  
      As shown in Table 3, from input port  151  two packets will be switched in each fabric switching cycle: one packet from I{1,1} to output ports  191 ,  192 , and  193 ; and the second from I{1,4} to output port  194 . Clearly the total number of packets switched from input port  151  in each fabric switching cycle is four by counting a multicast packet as many times as its fan-out. Packets from I{1,2} and I{1,3} shown in Table 2 are not going to be switched to output ports, since they are not selected in the arbitration during input port contention resolution. Similarly in the rest of the input ports only four packets are selected as shown in Table 3, and they will be switched to the output ports in each fabric switching cycle.  
               TABLE 3                       Multicast Packet (Arbitration) Requests generated by       the input ports in  FIG. 1A  corresponding to the       requests of TABLE 2                                                Packet requests from   Packet requests from           input port 151   input port 152                       I{1,1}   OP{1,2,3}   I{2,1}   OP{1,2,4}           I{1,4}   OP{4}   I{2,3}   OP{3}                       Packet requests from   Packet requests from           input port 153   input port 154                       I{3,1}   OP{1}   I{4,1}   OP{1,2,3,4}           I{3,2}   OP{2,4}           I{3,3}   OP{3}                      
 
      Table 4 shows the packet requests received by the output ports corresponding to the packet requests generated in the input ports in Table 3. Since as discussed above each packet from an input queue in an input port is assigned to a corresponding output queue as shown in Table 1, it is clear that only four packet requests will be received by each output port and hence all the packets will be issued grants. And hence there does not arise output port contention. Similarly all the packet grants will be accepted by input ports since each input port generated requests for at most four packets only.  
               TABLE 4                       Multicast Packet Arbitration Requests received by the       Output Ports in  FIG. 1A  corresponding to the       requests of TABLE 3                                                Packet requests to   Packet requests to           output port 191   output port 192                       I{1,1}   O{1,1}   I{1,1}   O{2,1}           I{2,1}   O{1,2}   I{2,1}   O{2,2}           I{3,1}   O{1,3}   I{3,2}   O{2,3}           I{4,1}   O{1,4}   I{4,1}   O{2,4}                       Packet requests to   Packet requests to           output port 193   output port 194                       I{1,1}   O{3,1}   I{1,4}   O{4,1}           I{2,3}   O{3,2}   I{2,1}   O{4,2}           I{3,3}   O{3,3}   I{3,2}   O{4,3}           I{4,1}   O{3,4}   I{4,1}   O{4,4}                      
 
      In accordance with the current invention, all the 16 packets A 1 -P 1 , whether they are unicast or multicast packets, will be switched in a fabric switching cycle in nonblocking manner, from the input ports to the output ports via the interconnection network in the middle stage  130 . In each switching time at most one packet is switched from each input queue in each input port and at most one packet is switched into each output port. However when it is a multicast packet, there is a possibility that it is switched out into more than one output ports from an input queue in the same switching time depending on the schedule generated as discussed later. Applicant makes an important observation that the problem of deterministic and nonblocking scheduling of the  16  arbitrarily fan-out multicast packets A 1 -P 1  to switch to the 16 output queues at output ports  191 - 194  in switch fabric  10  of  FIG. 1A  is related to the nonblocking scheduling of the three-stage clos network  14  shown in  FIG. 1C .  
      Referring to  FIG. 1C , an exemplary symmetrical three-stage Clos network  14  operated in time-space-time (TST) configuration of eleven switches for satisfying communication requests between an input stage  110  and output stage  120  via a middle stage  130  is shown where input stage  110  consists of four, four by three switches IS 1 -IS 4  and output stage  120  consists of four, three by four switches OS 1 -OS 4 , and middle stage  130  consists of three, four by four switches MS 1 -MS 3 . The number of inlet links to each of the switches in the input stage  110  and outlet links to each of the switches in the output stage  120  is denoted by n, and the number of switches in the input stage  110  and output stage  120  is denoted by r. Each of the three middle switches MS 1 -MS 3  are connected to each of the r input switches through r links (for example the links FL 1 -FL 4  connected to the middle switch MS 1  from each of the input switch IS 1 -IS 4 ), and connected to each of the output switches through r second internal links (for example the links SL 1 -SL 4  connected from the middle switch MS 1  to each of the output switch OS 1 -OS 4 ). The network has  16  inlet links namely I{1,1}-I{4,4} and 16 outlet links O{1,1}-O{4,4}. Just like in switch fabric  10  of  FIG. 1A  in the three-stage clos network  14  of  FIG. 1C , all the 16 input links are also assigned to the 16 output links as shown in Table 1. The network  14  of  FIG. 1C  is operable in strictly non-blocking manner for multicast connection requests, by fanning out each connection request in the first stage at most two times and as many times as needed in the middle stage, when the number of switches in the middle stage  130  is equal to  
             3   ×   n     -   1     n     ≅   3       
 
 switches (See the related U.S. patent application Ser. No. 09/967,106 entitled “STRICTLY NON-BLOCKING MULTICAST MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed on 27, Sep. 2001 and its Continuation In Part PCT Application Serial No. PCT/US 03/27972 filed on 6, Sep. 2003.that is incorporated by reference, as background to the invention). 
 
      In accordance with the current invention, in one embodiment with three four by four crossbar networks  131 - 133  in the middle stage  130 , i.e., with a speedup of three, switch fabric  10  of  FIG. 1A  is operated in strictly nonblocking manner, by fanning out each packet request in the input port at most two times and as many times as needed in the middle stage interconnection networks. The specific method used in implementing the strictly non-blocking and deterministic switching can be any of a number of different methods that will be apparent to a skilled person in view of the disclosure. One such arbitration and scheduling method is described below in reference to  FIG. 1B .  
               TABLE 5                       Multicast Packet Assignment in  FIG. 1A  using       the Method of  FIG. 1B         for the Packet Acceptances of TABLE 4                                                Packets Scheduled   Packets Scheduled           in Switching time   in Switching           1 (Shown in  FIG. 1D  &amp;  FIG. 1H )   time 2 (Shown in  FIG. 1E )                       I{2,1}   O{1,2} &amp;  O{2,2}   I{1,4}   O{4,1}           I{4,1}   O{3,4} &amp;  O(4,4)   I{3,3}   O{3,3}               I{4,1}   O{1,4} &amp;  O{2,4}                       Packets scheduled   Packets scheduled           in Switching   in Switching           time 3 (Shown in  FIG. 1F )   time 4 (Shown in  FIG. 1G )                       I{1,1}   O{2,1} &amp;  O{3,1}   I{1,1}   O{1,1}           I{3,1}   O{1,3}   I{2,3}   O{3,2}           I{2,1}   O{4,2}   I{3,2}   O{2,3} &amp;  O{4,3}                      
 
      Table 5 shows the schedule of the packets in each of the four switching times for the acceptances of Table 4 using the scheduling part of the arbitration and scheduling method  40  of  FIG. 1B , in one embodiment.  FIG. 1D  to  FIG. 1H  show the state of switch fabric  10  of  FIG. 1A  after each switching time.  FIG. 1D  shows the state of switch fabric  10  of  FIG. 1A  after the first switching time during which the packets E 1  and M 1  are switched to the output queues. Packet E 1  from input port  152  is destined to output ports  191 ,  192 , and  194 . According to the current invention a multicast packet is fanned out through at most two interconnection networks  131 - 133  in any of the four switching times. For example, as shown in  FIG. 1D , packet El from input port  152  is switched via crossbar network  131 , in the first switching time, into the output queues  182  of output port  191  and  182  of output port  192 . (Packet E 1  will be switched to output queue  182  of output port  194  in the third switching time shown in  FIG. 1F  through the crossbar switch  133 , as described later). So multicast packet E 1  is fanned out through only two crossbar networks, namely crossbar network  131  in first switching time and crossbar network  133  in third switching time. However in the first switching time packet E 1  is fanned out to output ports  191  and  192 , and in the third switching time it is fanned out to output port  194 .  
      In accordance with the current invention, a multicast packet from an input port is fanned out through at most two crossbar networks in the middle stage, possibly in two switching times, and the multicast packet from the middle stage (crossbar) networks is fanned out to as many number of the output ports as required. Also when a multicast packet is switched to the destined output ports in two different scheduled switching times, after the first switching time the multicast packet is still kept at the head of line of its input queue until it is switched to the remaining output ports in the second scheduled switching time. And hence in  FIG. 1D , packet E 1  is still at the head of line of input queue  171  of input port  152 .  
      In  FIG. 1D , similarly multicast packet MI from input port  154  (destined to output ports  191 - 194 ) is fanned out through crossbar network  132 , and from crossbar network  132  it is fanned out into output queue  184  of output port  193  and output queue  184  of output port  194 . Packet M 1  will be switched to output ports  191 - 192  in the second switching time, as described later. Multicast packet M 1  is also still left at the head of line of input queue  171  of input port  154 . Applicant observes that all the output ports in each switching time receives at most one packet, however when multicast packets are switched all the input ports may not be switching at most one packet in each switching time.  
       FIG. 1E  shows the state of switch fabric  10  of  FIG. 1A  after the second switching time during which the packets D 1 , K 1 , and M 1  are switched to the output queues. Unicast packet D 1  from input port  151  is switched via crossbar network  131  into output queue  181  of output port  194 . Unicast packet K 1  from input port  153  is switched via crossbar network  133  into output queue  183  of output port  193 . Multicast packet M 1  from input port  153  is fanned out through crossbar network  132  and from there it is fanned out into output queue  184  of output port  191  and output queue  184  of output port  192 . Since multicast packet M 1  is switched out to all the destined output ports it is removed at the head of line and hence packet M 2  is at the head of line of input queue  171  of input port  154 . Again only one packet from each input port is switched and each output port receives only one packet in the second switching time. Once again all the output ports in the second switching time receive at most one packet.  
       FIG. 1F  shows the state of switch fabric  10  of  FIG. 1A  after the third switching time during which the packets A 1 , E 1 , and I 1  are switched to the output queues. Multicast packet A 1  from input port  151  is fanned out through crossbar network  131 , and in crossbar network  131  it is fanned out twice into output queue  181  of output port  192  and output queue  181  of output port  193 . (Multicast packet A 1  is scheduled to fan out to the output port  191  in the fourth switching time). And so head of line of input queue  171  of input port  151  still contains packet A 1 . Multicast packet E 1  from input port  152  is fanned out via crossbar network  133  into the output queue  182  of output port  194 . Since multicast packet E 1  is switched out to all the destinations it is removed from the head of line of input queue  171  of input port  152 . Unicast packet  11  from input port  153  is switched via crossbar network  132  into the output queue  183  of output port  191 . Again all the output ports in the third switching time receive at most one packet.  
       FIG. 1G  shows the state of switch fabric  10  of  FIG. 1A  after the fourth switching time during which the packets A 1 , G 1 , and J 1  are switched to the output queues. Multicast packet A 1  from input port  151  is switched via crossbar network  133  into the output queue  181  of output port  192 . Since multicast packet A 1  is switched out to all the destinations it is removed from the head of line of input queue  171  of input port  151 . Unicast packet G 1  from input port  152  is switched via crossbar network  132  into the output queue  182  of output port  193 . Multicast packet J 1  from input port  153  is switched via crossbar network  131 , and from crossbar network  131  it is fanned out twice into output queue  183  of output port  192  and output queue  183  of output port  194 . In this case multicast packet J 1  is fanned out through only one middle stage (crossbar) network in only one switching time to all its destined output ports. And since multicast packet J 1  is switched out to all the destinations it is removed from the head of line of input queue  172  of input port  153 . Again all the output ports in the fourth switching time receive at most one packet.  
       FIG. 1H  shows the state of switch fabric  10  of  FIG. 1A  after the fifth switching time during which the packets E 2  and M 2  are switched to the output queues. Packet E 2  from input port  152  is switched via crossbar network  131  into the output queues  182  of output port  191  and output queue  182  of output port  192 . (Packet E 2  will be switched to output queue  182  of output port  194  in a later switching time just like packet E 1 ). Multicast packet M 2  from input port  154  (destined to output ports  191 - 194 ) is fanned out through crossbar network  132 , and from crossbar network  132  it is fanned out into output queue  184  of output port  193  and output queue  184  of output port  194 . Packet M 2  will be switched to output ports  191 - 192  in a later switching time, just like packet M 1 . Multicast packets E 2  and M 2  are still at the head of line of input queue  171  of input port  152  and input queue  171  of input port  154  respectively, since they are not switched to all their destined output ports. And so the arbitration and scheduling method  40  of  FIG. 1B  need not do the rescheduling after the schedule for the first fabric switching cycle is performed. And so the packets from any particular input queue to the destined output queue are switched along the same path and travel in the same order as they are received by the input port and hence never arises the issue of packet reordering.  
      Since in the fabric switching cycle the maximum of 16 multicast packets are switched to the output ports, the switch is nonblocking and operated at 100% throughput, in accordance with the current invention. Since switch fabric  10  of  FIG. 1A  is operated so that each output port, at a switching time, receives at least one packet as long as there is at least a packet from any one of input queues destined to it, hereinafter the switch fabric is called “work-conserving system”. It is easy to observe that a switch fabric is directly work-conserving if it is nonblocking. In accordance with the current invention, switch fabric  10  of  FIG. 1A  is operated so that no packet at the head of line of each input queues is held for more than as many switching times equal to the number of input queues (four) at each input port, hereinafter the switch fabric is called “fair system”. Since virtual output queues are used, head of line blocking is also eliminated for both unicast and multicast packets.  
      In accordance with the current invention, using the arbitration and scheduling method  40  of  FIG. 1B , switch fabric  10  of  FIG. 1A  is operated so that each output port, at a switching time, receives at most one packet even if it is possible to switch three packets in a switching time using the speedup of three in the interconnection network. And the speedup is strictly used only to operate interconnection network in nonblocking manner, and absolutely never to congest the output ports. Hence the arbitration and scheduling method  40  of  FIG. 1C , to switch packets in switch fabric  10  of  FIG. 1A  is deterministic. Each inlet link  141 - 144  receives packets at the same rate as each outlet link  201 - 204  transmits, i.e., one packet in each switching time. Since only one packet is deterministically switched from each input port  151 - 154  in each switching time, and only one packet is switched into each output port  191 - 194 , the packet fabric  10  of  FIG. 1A  never congests the output ports.  
      An important advantage of deterministic switching in accordance with the current invention is packets are switched out of the input ports at most at the peak rate, even when the switch fabric is oversubscribed. That also means packets are received at the output ports at most the peak rate. It means no traffic management is needed in the output ports and the packets are transmitted out of the output ports deterministically. And hence the traffic management is required only at the input ports in switch fabric  10  of  FIG. 1A .  
      Another important characteristic of switch fabric  10  of  FIG. 1A  is all the packets belonging to a particular input queue are switched to the same output queue in the destined output port. Applicant notes three key benefits due to the output queues. 1) In a switching time, a byte or a certain number of bytes are switched from the input ports to the output ports. Alternatively switching time of the switch fabric is variable and hence is a flexible parameter during the design phase of switch fabric. 2) So even if the packets A 1 -P 1  are of arbitrarily long and variable size, since each packet in an input queue is switched into the same output queue in the destined output port, the complete packet need not be switched in a switching time. Alternatively the second benefit of output queues is, longer packets need not be physically segmented in the input port and rearranged in the output port. The packets are logically switched to output queues segment by segment, (the size of the packet segment is determined by the switching time.) with out physically segmenting the packets; the packet segments in each packet are also switched through the same path from the input queue to the destined output queue. 3) The third benefit of the output queues is packets and packet segments are switched in the same order as they are received by the input ports and never arising the issue of packet reordering.  
       FIG. 1I  shows a switch fabric  16  switching long packets. There is one packet in each input queue making it 16 packets in all the  16  input queues namely: packet {A 1 -A 4 } in the input queue  171  of input port  151 , packet {B 1 -B 4 } in the input queue  172  of input port  151 , packet {C 1 -C 4 } in the input queue  173  of input port  151 , and so on with packet {P 1 -P 4 } in the input queue  174  in input port  154 . Each of these 16 packets consists of 4 equal size packet segments. For example packet {A 1 -A 4 } consists of four packet segments namely A 1 , A 2 , A 3 , and A 4 . If packet size is not a perfect multiple of four of the size of the packet segment, the fourth packet may be shorter in size. However none of the four packet segments are longer than the maximum packet segment size. Packet segment size is determined by the switching time; i.e., in each switching time only one packet segment is switched from any input port to any output port. Excepting for longer packet sizes the diagram of switch fabric  16  of  FIG. 1I  is the same as the diagram of switch fabric  10  of  FIG. 1A . Just the same way it is performed in the case of switch fabric  10  of  FIG. 1A , the arbitration and scheduling method  40  of  FIG. 1B  for the packet requests in Table 2 is performed to generate the schedule given in Table 5.  
      In one embodiment,  FIG. 1J  to  FIG. 1M  show the state of switch fabric  16  of  FIG. 1I  after each fabric switching cycle.  FIG. 1J  shows the state of switch fabric  16  of  FIG. 11  after the first fabric switching cycle during which all the scheduled head of line packet segments A 1 -P 1  are switched to the output queues. These multicast packet segments are switched to the output queues in exactly the same manner, using the arbitration and scheduling method  40  of  FIG. 1B , as the packets A 1 -P 1  are switched to the output queues in switch fabric  10  of  FIG. 1A  as shown in  FIGS. 1D-1G .  FIG. 1K  shows the state of switch fabric  16  of  FIG. 1I  after the second fabric switching cycle during which all the scheduled head of line packet segments A 2 -P 2  are switched to the output queues.  FIG. 1L  shows the state of switch fabric  16  of  FIG. 11  after the third fabric switching cycle during which all the scheduled head of line packet segments A 3 -P 3  are switched to the output queues.  FIG. 1M  shows the state of switch fabric  16  of  FIG. 1I  after the fourth fabric switching cycle during which all the scheduled head of line packet segments A 1 -P 1  are switched to the output queues. In each of the first, second, third, and fourth fabric switching cycle the packet segments are switched to the output queues in exactly the same manner as the packets A 1 -P 1  are switched to the output queues in switch fabric  10  of  FIG. 1A  as shown in the  FIGS. 1D-1G . Clearly all the packet segments are switched in the same order, as received by the respective input ports. Hence there is no issue of packet reordering. Packets are also switched at 100% throughput, work conserving, and fair manner.  
      In  FIGS. 1J-1M  packets are logically segmented and switched to the output ports. In one embodiment, a tag bit ‘1’ is also padded in a particular designated bit position of each packet segment to denote that the packet segments are the first packet segments with in the respective packets. By reading the tag bit of ‘1’, the output ports recognize that the packet segments A 1 -P 1  are the first packet segments in a new packet. Similarly each packet segment is padded with the tag bit of ‘1’ in the designated bit position except the last packet segment which will be padded with ‘0’. (For example, in packets segments in switch fabric  16  of  FIG. 1I , packet segments A 1 -P 1 , A 2 -P 2  and A 3 -P 3  are padded with tag bit of ‘1’ where as the packet segments A 4 -P 4  are padded with the tag bit of ‘0’). When the tag bit is detected as ‘0’ the output port next expects a packet segment of a new packet or a new packet. If there is only one packet segment in a packet it will be denoted by a tag bit of ‘0’ by the input port. The output port if it receives two consecutive packet segments with the designated tag bit of ‘0’, it determines that the second packet segment is the only packet segment of a new packet.  
      In switch fabric  16  of  FIG. 1I  the packets are four segments long. However in general packets can be arbitrarily long. In addition different packets in the same queue can be of different size. In both the cases the arbitration and scheduling method  40  of  FIG. 1B  operates switch fabric in nonblocking manner, and the packets are switched at 100% throughput, work conserving, and fair manner. A 1 so there is no need to physically segment the packets in the input ports and reassemble in the output ports. The switching time of the switch fabric is also a flexible design parameter so that it is set to switch packets byte by byte or a few bytes by few bytes in each switching time.  
       FIG. 1B  shows a high-level flowchart of an arbitration and scheduling method  40 , in one embodiment, executed by the scheduler of  FIG. 1A . According to this embodiment, at most r requests will be generated from each input port in act  41 . When each input port has r unicast packet requests with one request from each input queue there will be at most r requests from each input port. However when there are multicast packets, r requests from each input port cannot be satisfied since each output port can receive at most r packets in a fabric switching cycle. Thus multicast packets in input ports arise input port contention. However each input port can only switch at most r packets in a fabric switching cycle. Hence a multicast packet request from an input port is at the expense of another packet request from another input queue of the same input port. And it must be observed that the r requests from each input port are made to r different output ports. Therefore in act  41  a set of multicast requests are generated, by using an arbitration policy, in each input port so that the sum of the packets of all the requests is not more than r, i.e., by counting a multicast packet as many times as its fan-out. In one embodiment the arbitration policy may be based on a priority scheme. However the type of selection policy used in act  41  to resolve the input port contention is irrelevant to the current invention.  
      In act  42 , each output port will issue at most r grants, each request corresponding to an associated output queue. Since each input port generates only one request it can be easily seen that each output port receives at most r requests, i.e., one from each input port. And each output port can issue grants to all the r received requests. Therefore applicant observes that multicast packets do not arise output port contention. In act  43 , each input port accepts at most r grants. Since each output port issues at most r grants one to each input port, each input port receives at most r grants. And each input port will accept all the r grants.  
      In act  44 , all the r 2  requests will be scheduled without rearranging the paths of previously scheduled packets. In accordance with the current invention, all the r 2  requests will be scheduled in strictly nonblocking manner with the speedup of three in the middle stage  130 . It should be noted that the arbitration of generation of requests, issuance of grants, and generating acceptances is performed in only one iteration. After act  44  the control returns to act  45 . In act  45  it will be checked if there are new and different requests at the input ports. If the answer is “NO”, the control returns to act  45 . If there are new requests but they are not different such that request have same input queue to output queue requests, the same schedule is used to switch the next r 2  requests. When there are new and different requests from the input ports the control transfers from act  45  to act  41 . And acts  41 - 45  are executed in a loop.  
      The network  14  of  FIG. 1C  can also be operated in rearrangeably non-blocking manner for multicast connection requests, when the number of switches in the middle stage  130  is equal to 2×n/n=2 switches. (See the related U.S. patent application Ser. No. 09/967,815 entitled “REARRANGEABLY NON-BLOCKING MULTICAST MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed on 27, Sep. 2001 and its Continuation In Part PCT Application Serial No. PCT/US 03/27971 filed on 6, Sep. 2003.that is incorporated by reference, as background to the invention). Similarly according to the current invention, in another embodiment having multicast packets in input queues and using only two four by four crossbar network  131  in the middle stage  130 , i.e., with a speedup of two, switch fabric  18  of  FIG. 1N  is operated in rearrangeably nonblocking manner.  
      In strictly nonblocking network, as the packets at the head of line of all the input queues are scheduled at a time, it is always possible to schedule a path for a packet from an input queue to the destined output queue through the network without disturbing the paths of prior scheduled packets, and if more than one such path is available, any path can be selected without being concerned about the scheduling of the rest of packets. In a rearrangeably nonblocking network, as the packets at the head of line of all the input queues are scheduled at a time, the scheduling of a path for a packet from an input queue to the destined output queue is guaranteed to be satisfied as a result of the scheduler&#39;s ability to rearrange, if necessary by rearranging, the paths of prior scheduled packets. Switch fabric  18  of  FIG. 1N  is operated in rearrangeably nonblocking manner where as switch fabric  10  of  FIG. 1A  is operated in strictly nonblocking manner, in accordance with the current invention.  
      Referring to  FIG. 2A  a switch fabric  20  does not have output queues otherwise the diagram of switch fabric  20  of  FIG. 2A  is exactly same as the diagram of switch fabric  10  of  FIG. 1A . In accordance with the current invention, switch fabric  20  is operated in strictly nonblocking and deterministic manner in the same way in every aspect that is disclosed about switch fabric  10  of  FIG. 1A , excepting that it requires SAR in the input and output ports. Packets need to be segmented in the input ports as determined by the switching time and switched to the output ports need to be reassembled separately. However the arbitration and scheduling method  40  of  FIG. 1B  is also used to switch packets in switch fabric  20  of  FIG. 2A . Here also the scheduling is performed on all 16 head of line packets at the same time and assuming that virtually there are 16 output queues at the output ports, and the packets will be switched in four switching times. During the switching times, however the packets are switched into the destined output ports instead of the output queues.  FIGS. 2B-2F  show the state of switch fabric  20  of  FIG. 2A  after each switching time in a fabric switching cycle, by scheduling the packet requests shown in Table 2. Using the arbitration and scheduling method of  FIG. 1B  and following the same steps described as in switch fabric  10  of  FIG. 1A , the packets scheduled in each switching time are shown in Table 5.  
       FIG. 2B  shows the state of switch fabric  20  of  FIG. 2A  after the first switching time during which the packets E 1  and M 1  are switched to the output queues. Packet E 1  from input port  152  is switched via crossbar network  131 , in the first switching time, into output port  191  and output port  192 . (Packet E 1  will be switched to output port  194  in the third switching time shown in  FIG. 2C  through the crossbar switch  133 , as described later). So multicast packet E 1  is fanned out through only two crossbar networks, namely crossbar network  131  in first switching time and crossbar network  133  in third switching time. However in the first switching time packet E 1  is fanned out to output ports  191  and  192 , and in the third switching time it is fanned out to output port  194 .  
      In accordance with the current invention, a multicast packet from an input port is fanned out through at most two crossbar networks in the middle stage, possibly in two switching times, and the multicast packet from the middle stage (crossbar) networks is fanned out to as many number of the output ports as required. Also when a multicast packet is switched to the destined output ports in two different scheduled switching times, after the first switching time the multicast packet is still kept at the head of line of its input queue until it is switched to the remaining output ports in the second scheduled switching time. And hence in  FIG. 2B , packet E 1  is still at the head of line of input queue  171  of input port  152 .  
      In  FIG. 2B , similarly multicast packet M 1  from input port  154  (destined to output ports  191 - 194 ) is fanned out through crossbar network  132 , and from crossbar network  132  it is fanned out into output port  193  and output port  194 . Packet M 1  will be switched to output ports  191 - 192  in the second switching time, as described later. Multicast packet M 1  is also still left at the head of line of input queue  171  of input port  154 . Applicant observes that all the output ports in each switching time receives at most one packet, however when multicast packets are switched all the input ports may not be switching at most one packet in each switching time.  
       FIG. 2C  shows the state of switch fabric  20  of  FIG. 2A  after the second switching time during which the packets D 1 , K 1 , and M 1  are switched to the output queues. Unicast packet D 1  from input port  151  is switched via crossbar network  131  into output port  194 . Unicast packet K 1  from input port  153  is switched via crossbar network  133  into output port  193 . Multicast packet M 1  from input port  153  is fanned out through crossbar network  132  and from there it is fanned out into output port  191  and output port  192 . Since multicast packet M 1  is switched out to all the destined output ports it is removed at the head of line and hence packet M 2  is at the head of line of input queue of input port  154 . Again only one packet from each input port is switched and each output port receives only one packet in the second switching time. Once again all the output ports in the second switching time receive at most one packet.  
       FIG. 2D  shows the state of switch fabric  20  of  FIG. 2A  after the third switching time during which the packets A 1 , E 1 , and I 1  are switched to the output queues. Multicast packet A 1  from input port  151  is fanned out through crossbar network  131 , and in crossbar network  131  it is fanned out twice into output port  192  and output port  193 . (Multicast packet A 1  is scheduled to fan out to the output port  191  in the fourth switching time). And so head of line of input queue  171  of input port  151  still contains packet A 1 . Multicast packet E 1  from input port  152  is fanned out via crossbar network  133  into output port  194 . Since multicast packet E 1  is switched out to all the destinations it is removed from the head of line of input queue  171  of input port  152 . Unicast packet I 1  from input port  153  is switched via crossbar network  132  into output port  191 . Again all the output ports in the third switching time receive at most one packet.  
       FIG. 2E  shows the state of switch fabric  20  of  FIG. 2A  after the fourth switching time during which the packets A 1 , G 1 , and J 1  are switched to the output queues. Multicast packet A 1  from input port  151  is switched via crossbar network  133  into output port  192 . Since multicast packet A 1  is switched out to all the destinations it is removed from the head of line of input queue  171  of input port  151 . Unicast packet G 1  from input port  152  is switched via crossbar network  132  into output port  193 . Multicast packet J 1  from input port  153  is switched via crossbar network  131 , and from crossbar network  131  it is fanned out twice into output port  192  and output port  194 . In this case multicast packet J 1  is fanned out through only one middle stage (crossbar) network in only one switching time to all its destined output ports. And since multicast packet J 1  is switched out to all the destinations it is removed from the head of line of input queue  172  of input port  153 . Again all the output ports in the fourth switching time receive at most one packet.  
       FIG. 2F  shows the state of switch fabric  20  of  FIG. 2A  after the fifth switching time during which the packets E 2  and M 2  are switched to the output queues. Packet E 2  from input port  152  is switched via crossbar network  131  into output port  191  and output port  192 . (Packet E 2  will be switched to output port  194  in a later switching time just like packet E 1 ). Multicast packet M 2  from input port  154  (destined to output ports  191 - 194 ) is fanned out through crossbar network  132 , and from crossbar network  132  it is fanned out into output port  193  and output port  194 . Packet M 2  will be switched to output ports  191 - 192  in a later switching time, just like packet M 1 . Multicast packets E 2  and M 2  are still at the head of line of input queue  171  of input port  152  and input queue  171  of input port  154  respectively, since they are not switched to all their destined output ports. And so the arbitration and scheduling method  40  of  FIG. 1B  need not do the rescheduling after the schedule for the first fabric switching cycle is performed. And so the packets from any particular input queue to the destined output port are switched along the same path and travel in the same order as they are received by the input port and hence never arises the issue of packet reordering.  
      The arbitration and scheduling method  40  of  FIG. 1B  operates switch fabric  20  of  FIG. 2A  also in strictly nonblocking manner, and the packets are switched at 100% throughput, work conserving, and fair manner. The switching time of the switch fabric is also a flexible design parameter so that it can be set to switch packets byte by byte or a few bytes by few bytes in each switching time. However switch fabric  20  requires SAR, meaning that the packets need to be physically segmented in the input ports and reassembled in the output ports. Nevertheless in switch fabric  20  the packets and packet segments are switched through to the output ports in the same order as received by the input ports. In fact, excepting for the SAR, the arbitration and scheduling method  40  of  FIG. 1B  operates switch fabric  20  in every aspect the same way as described about switch fabric  10  of  FIG. 1A .  
      Speedup of three in the middle stage for nonblocking operation of the switch fabric is realized in two ways: 1) parallelism and 2) tripling the switching rate. Parallelism is realized by using three interconnection networks in parallel in the middle stage, for example as shown in switch fabric  10  of  FIG. 1A . The tripling of switching rate is realized by operating the interconnection network, the first and second internal links at triple clock rate, for each clock in the input and output ports. In the first clock the single interconnection network is operated for switching as the first interconnection network of an equivalent switch fabric implemented with three parallel interconnection networks, for example as the interconnection network  131  in switch fabric  10  of  FIG. 1A . Similarly in the second clock the single interconnection network is operated as the second interconnection network, for example as the interconnection network  132  in switch fabric  10  of  FIG. 1A . In the third clock the single interconnection network is operated as the third interconnection network, for example as the interconnection network  133  in switch fabric  10  of  FIG. 1A . And so triple rate in the clock speed of the interconnection network, and in the first and second internal links is required in this implementation. The arbitration and scheduling method  40  of  FIG. 1B  operates both the switch fabrics, implementing the speedup by either parallelism or by triple rate, in nonblocking and deterministic manner in every aspect as described in the current invention.  
      Referring to  FIG. 3A  shows the diagram of a switch fabric  30  which is the same as the diagram of switch fabric  10  of  FIG. 1A  excepting that speedup of three is provided with a speedup of three in the clock speed in only one crossbar interconnection network in the middle stage  130  and a speedup of three in the first and second internal links. In another embodiment of the network in  FIG. 1A  each of the interconnection networks in the middle stage are shared memory networks.  FIG. 3B  shows a switch fabric  50 , which is the same as switch fabric  10  of  FIG. 1A , excepting that speedup of three is provided with three shared memory interconnection networks in the middle stage  130 .  FIG. 3C  shows a switch fabric  60  which is the same as switch fabric  30  of  FIG. 3A  excepting that speedup of three is provided with a speedup of three in the clock speed in only one shared memory interconnection network in the middle stage  130  and a speedup of three in the first and second internal links.  
      Similarly  FIG. 3D  shows a switch fabric  70 , which is the same as switch fabric  10  of  FIG. 1A , excepting that speedup of three is provided with three hypercube interconnection networks in the middle stage  130 .  FIG. 3E  shows a switch fabric  60  which is exactly the same as switch fabric  30  of  FIG. 3A  excepting that speedup of three is provided with a speedup of three in the clock speed in only one hypercube based interconnection network in the middle stage  130  and a speedup of three in the first and second internal links.  
      In switch fabrics  10  of  FIG. 1A, 16  of  FIG. 1I, 18  of  FIG. 1N, 20  of  FIG. 2A, 30  of  FIG. 3A, 50  of  FIG. 3B, 60  of  FIG. 3C, 70  of  FIG. 3D , and  80  of  FIG. 3E  the number of input ports  110  and output ports  120  is denoted in general with the variable r for each stage. The speedup in the middle stage is denoted by s. The speedup in the middle stage is realized by either parallelism, i.e., with three interconnection networks (as shown in  FIG. 4A ,  FIG. 4C  and  FIG. 4E ), or with triple switching rate in one interconnection network (as shown in  FIG. 4B ,  FIG. 4D  and  FIG. 4F ). The size of each input port  151 -{ 150 +r} is denoted in general with the notation r*s (means each input port has r input queues and is connected to s number of interconnection networks with s first internal links) and of each output switch  191 -{ 190 +r} is denoted in general with the notation s*r (means each output port has r output queues and is connected to s number of interconnection networks with s second internal links). Likewise, the size of each interconnection network in the middle stage  130  is denoted as r*r. An interconnection network as described herein may be either a crossbar network, shared memory network, or a network of subnetworks each of which in turn may be a crossbar or shared memory network, or a three-stage clos network, or a hypercube, or any internally nonblocking interconnection network or network of networks. A three-stage switch fabric is represented with the notation of V(s,r).  
      Although it is not necessary that there be the same number of input queues  171 -{ 170 +r} as there are output queues  181 -{ 180 +r}, in a symmetrical network they are the same. Each of the s middle stage interconnection networks  131 - 132  are connected to each of the r input ports through r first internal links, and connected to each of the output ports through r second internal links. Each of the first internal links FL 1 -FLr and second internal links SL 1 -SLr are either available for use by a new packet or not available if already taken by another packet.  
      Switch fabric  10  of  FIG. 1A  is an example of general symmetrical switch fabric of  FIG. 4A , which provides the speedup of three by using three crossbar interconnection networks in the middle stage  13 Q. Referring to  FIG. 4B  shows the general symmetrical switch fabric which is the same as the switch fabric of  FIG. 4A  excepting that speedup of three is provided with a speedup of three in the clock speed in only one crossbar interconnection network in the middle stage  130  and a speedup of three in the first and second internal links.  
       FIG. 4C  shows the general symmetrical switch fabric, which provides the speedup of three by using three shared memory interconnection networks in the middle stage  130 .  FIG. 4D  shows the general symmetrical switch fabric, which provides the speedup of three by using a speedup of three in the clock speed in only one shared memory interconnection network in the middle stage  130  and a speedup of three in the first and second internal links.  
       FIG. 4E  shows the general symmetrical switch fabric, which provides the speedup of three by using three, three-stage clos interconnection networks in the middle stage  130 .  FIG. 4F  shows the general symmetrical switch fabric, which provides the speedup of three by using a speedup of three in the clock speed in only one three-stage clos interconnection network in the middle stage  130  and a speedup of three in the first and second internal links.  
      In general the interconnection network in the middle stage  130  may be any interconnection network: a hypercube, or a batcher-banyan interconnection network, or any internally nonblocking interconnection network or network of networks. In one embodiment interconnection networks  131 - 133  may be three of different network types. For example, the interconnection network  131  may be a crossbar network, interconnection network  132  may be a shared memory network, and interconnection network  133  may be a hypercube network. In accordance with the current invention, irrespective of the type of the interconnection network used in the middle stage, a speedup of three in the middle stage operates switch fabric in strictly nonblocking manner using the arbitration and scheduling method  40  of  FIG. 1B . And a speedup of two in the middle stage operates the switch fabric in rearrangeably nonblocking manner.  
      It must be noted that speedup in the switch fabric is not related to internal speedup of an interconnection network. For example, crossbar network and shared memory networks are fully connected topologies, and they are internally nonblocking without any additional internal speedup. For example the interconnection network  131 - 133  in either switch fabric  10  of  FIG. 1A  or switch fabric  50  of  FIG. 3B  which are crossbar network or shared memory networks, there is no speedup required in either the interconnection network  131 - 133  to be operable in nonblocking manner. However if the interconnection network  131 - 133  is a three-stage clos network, each three-stage clos network requires an internal speedup of three to be operable in strictly nonblocking manner. In a switch fabric where the middle stage interconnection networks  131 - 133  are three-stage clos networks, switch fabric speedup of three is provided in the form of three different three-stage clos networks  131 - 133 . In addition each three-stage clos network  131 - 133  in turn require additional speedup of three for them to be internally strictly nonblocking. Clearly, switch fabric speedup is different from internal speedup of the interconnection networks.  
      Similarly if the interconnection network in the middle stage  131 - 133  is a hypercube network, in one embodiment, an internal speedup of d is needed in a d-rank hypercube (comprising 2 d  nodes) for it to be nonblocking network. In accordance with the current invention, the middle stage interconnection networks  131 - 133  may be any interconnection network that is internally nonblocking for the switch fabric to be operable in strictly nonblocking manner with a speedup of three in the middle stage using the arbitration and scheduling method  40  of  FIG. 1B , and to be operable in rearrangeably nonblocking manner with a speedup at least two in the middle stage.  
      Referring to  FIG. 4G  shows a detailed diagram of a four by four port (2-rank) hypercube based interconnection network in one embodiment of the middle stage interconnection network  131 - 133  in switch fabric  70  of  FIG. 3D  and switch fabric  80  of  FIG. 3E . There are four nodes in the 4-node hypercube namely:  00 ,  01 ,  10 , and  11 . Node  00  is connected to node  01  by the bi-directional link A. Node  01  is connected to node  11  by the bi-directional link B. Node  11  is connected to node  10  by the bi-directional link C. Node  10  is connected to node  00  by the bi-directional link D. And each of the four nodes is connected to the input and output ports of the switch fabric. Node  00  is connected to the first internal link FL 1  and the second internal link SL 1 . Node  01  is connected to the first internal link FL 2  and the second internal link SL 2 . Node  10  is connected to the first internal link FL 3  and the second internal link SL 3 . Node  11  is connected to the first internal link FL 4  and the second internal link SL 4 . For the hypercube network  131 - 133  shown in  FIG. 4G  to be internally nonblocking, in one embodiment, it is needed to operate the links A, B, C, and D in both the directions at the same rate as the inlet links (or outlet links) of the switch fabric, or with a speedup of some factor depending on the scheduling scheme of the hypercube network. According to the current invention, it is required for the hypercube to operated in internally nonblocking manner, and for the switch fabric to be operable in strictly nonblocking manner with a speedup of three using the arbitration and scheduling method  40  of  FIG. 1B , and to be operable in rearrangeably nonblocking manner with a speedup of at least two in the middle stage.  
      Although  FIGS. 4A-4F  show an equal number of first internal links and second internal links, as in the case of a symmetrical switch fabric, the current invention is now extended to non-symmetrical switch fabrics. In general, an (r 1 *r 2 ) asymmetric switch fabric, for switching multicast packets, comprising r 1  input ports with each input port having r 2  input queues, r 2  output ports with each output port having r 1  output queues, and an interconnection network having a speedup of  
       s   =           2   ×     r   1       +     r   2     -   1       MAX   ⁡     (       r   1     ,     r   2       )         ≅   3         
 
 with s subnetworks, and each subnetwork comprising at least one first internal link connected to each input port for a total of at least r 1  first internal links, each subnetwork further comprising at least one second internal link connected to each output port for a total of at least r 2  second internal links is operated in strictly nonblocking manner in accordance with the invention by scheduling at most r 1  packets in each switching time to be switched in at most r 2  switching times when r 1 ≦r 2 , in deterministic manner, and without the requirement of segmentation and reassembly of packets. In another embodiment, the switch fabric is operated in strictly nonblocking manner by scheduling at most r 2  packets in each switching time to be switched in at most r 1  switching times when r 2 ≦r 1 , in deterministic manner, and without the requirement of segmentation and reassembly of packets. The scheduling is performed so that each multicast packet is fan-out split through not more than two subnetworks, and not more than two switching times. 
 
      Such a general asymmetric switch fabric is denoted by V(s,r 1 ,r 2 ). In one embodiment, the system performs only one iteration for arbitration, and with mathematical minimum speedup in the interconnection network. The system is also operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The arbitration and scheduling method  40  of  FIG. 1B  is also used to schedule packets in V(s,r 1 ,r 2 ) switch fabrics.  
      The arbitration and scheduling method  40  of  FIG. 1B  also operates the general V(s,r 1 ,r 2 ) switch fabric in nonblocking manner, and the packets are switched at 100% throughput, work conserving, and fair manner. The switching time of the switch fabric is also a flexible design parameter so that it can be set to switch packets byte by byte or a few bytes by few bytes in each switching time. Also there is no need of SAR just as it is described in the current invention. In the embodiments without output queues the packets need to be physically segmented in the input ports and reassembled in the output ports.  
      Similarly in one embodiment, the non-symmetrical switch fabric V(s,r 1 ,r 2 ), for switching multicast packets, is operated in rearrangeably nonblocking manner with a speedup of  
       s   =         2   ×     MAX   ⁡     (       r   1     ,     r   2       )           MAX   ⁡     (       r   1     ,     r   2       )         =   2         
 
 in the interconnection network, by scheduling at most r 1  packets in each switching time to be switched in at most r 2  switching times when r 1 ≦r 2 , in deterministic manner, and without the requirement of segmentation and reassembly of packets. In another embodiment, the non-symmetrical switch fabric V(s,r 1 ,r 2 ) is operated in rearrangeably nonblocking manner with a speedup of  
       s   =         2   ×     MAX   ⁡     (       r   1     ,     r   2       )           MAX   ⁡     (       r   1     ,     r   2       )         =   2         
 
 in the interconnection network, by scheduling at most r 2  packets in each switching time to be switched in at most r 1  switching times when r 2 ≦r 1 , in deterministic manner and without the requirement of segmentation and reassembly of packets. The scheduling is performed so that each multicast packet is fan-out split through not more than two subnetworks, and not more than two switching times. 
 
      In an asymmetric switch fabric V(s,r 1 ,r 2 ), for switching multicast packets, comprising r 1  input ports with each input port having r 2  input queues, r 2  output ports, and an interconnection network having a speedup of  
       s   =           2   ×     r   1       +     r   2     -   1       MAX   ⁡     (       r   1     ,     r   2       )         ≅   3         
 
 with s subnetworks, and each subnetwork comprising at least one first internal link connected to each input port for a total of at least r 1  first internal links, each subnetwork further comprising at least one second internal link connected to each output port for a total of at least r 2  second internal links is operated in strictly nonblocking manner, in accordance with the invention, by scheduling at most r 1  packets in each switching time to be switched in at most r 2  switching times, in deterministic manner, and requiring the segmentation and reassembly of packets. The scheduling is performed so that each multicast packet is fan-out split through not more than two subnetworks, and not more than two switching times. The arbitration and scheduling method  40  of  FIG. 1B  is also used to switch packets in V(s,r 1 ,r 2 ) switch fabrics without using output queues. 
 
      Similarly in an asymmetric switch fabric V(s,r 1 ,r 2 ), for switching multicast packets, comprising r 1  input ports with each input port having r 2  input queues, r 2  output ports, and an interconnection network having a speedup of  
       s   =         2   ×     MAX   ⁡     (       r   1     ,     r   2       )           MAX   ⁡     (       r   1     ,     r   2       )         =   2         
 
 with s subnetworks, and each subnetwork comprising at least one first internal link connected to each input port for a total of at least r 1  first internal links, each subnetwork further comprising at least one second internal link connected to each output port for a total of at least r 2  second internal links is operated in rearrangeably nonblocking manner in accordance with the invention by scheduling at most r 1  packets in each switching time to be switched in at most r 2  switching times, in deterministic manner, and requiring the segmentation and reassembly of packets. The scheduling is performed so that each multicast packet is fan-out split through not more than two subnetworks, and not more than two switching times. 
 
      Applicant now notes that all the switch fabrics described in the current invention offer input port to output port rate and latency guarantees. End-to-end guaranteed bandwidth i.e., from any input port to any output port is provided based on the input queue to output queue assignment of unicast and multicast packets. Guaranteed and constant latency is provided for packets from multiple input ports to any output port. Since each input port switches packets into its assigned output queue in the destined output port, a packet from one input port will not prevent another packet from a second input port switching into the same output port, and thus enforcing the latency guarantees of packets from all the input ports. The switching time of switch fabric determines the latency of the packets in each flow and also the latency of packet segments in each packet.  
       FIG. 5A  shows an implementation of act  44  of the arbitration and scheduling method  40  of  FIG. 1B . The scheduling of r 2  packets is performed in act  44 . In act  44 A, it is checked if there are more packets to schedule. If there are more packets to schedule, i.e., if all r 2  packets are not scheduled, the control transfers to act  44 B 1 . In act  44 B 1  it is checked if there is an open path through one of the three interconnection networks in the middle stage through any of the r scheduling times, if the answer is “yes” the control transfers to act  44 C. If the answer is “no” in act  44 B 1 , the control transfers to act  44 B 2 . In act  44 B 2 , it is searched for two and only two interconnection networks in either one switching time or any two of the r scheduling times, such that there are available paths to all the destination output ports of the packet request. According to the current invention, it is always possible to find two middle stage interconnection networks so that there are open paths to all the destination output ports of the packet request. Then the control transfer to  44 C. The packet is scheduled through the selected one path or two paths in act  44 C. In  44 D the selected first internal links and second internal links are marked as selected so that no other packet selects these links in the same scheduling time. Then control returns to act  44 A and thus acts  44 A,  44 B,  44 C, and  44 D are executed in a loop to schedule each packet.  
       FIG. 5B  is a low-level flowchart of one variant of acts  44 B,  44 C and  44 D of the method of  44  of  FIG. 5A . The control to act  44 BA 1  transfers from act  44 A when there is a new packet request to be scheduled. Act  44 BA 1  assigns the new packet request to c and index variable i is assigned to ( 1 , 1 ) denoting scheduling time  1  and interconnection network  1  respectively. Then act  44 BA 2  checks if i is greater than (r,3) which means if all the three interconnection network in all r scheduling times are checked or not. If the answer is “no” the control transfers to act  44 BA 4 . Act  44 BA 4  checks if packet request c has no available first internal link to interconnection network i. 2  in the scheduling time i. 1  (where i. 1  represents the first element and i. 2  represents the second element of the tuple i). If the answer is “no”, in act  44 BA 5 , two sets namely O i  and O k  are generated to determine the set of destination switches of c having and not having available links from i, respectively. In act  44 BA 6 , it is checked if O i  has all the required destination ports of packet request c. If the answer is “yes”, the control transfers to act  44 C 1 , where packet request is scheduled through interconnection network i. 2  of scheduling time i. 1 . Act  44 D 1  marks the used first and second internal links to and from i as unavailable. From act  44 D 1  control transfers to act  44 A.  
      If the answer is “yes” in act  44 BA 4 , the control transfers to act  44 BA 13 . In act  44 BA 13 , if i. 2  is less than 3, tuple i is adjusted so that i. 2  is incremented by 1 to check the next interconnection network in the same scheduling time i. 1 . If i. 2  is equal to 3, tuple i is adjusted so that i. 1  is incremented by 1 to check the next scheduling time and the interconnection network  1 . Then control transfers to act  44 BA 2 . According to the current invention act  44 BA 2  never results in yes and hence act  44 BA 3  is never reached. Thus acts  44 BA 2 ,  44 BA 4 ,  44 BA 5 ,  44 BA 6 ,  44 BA 7 ,  44 BA 8 , and  44 BA 13  form the outer loop of a doubly nested loop to schedule packet request c.  
      If act  44 BA 6  results in “no”, the control transfers to act  44 BA 7 . In act  44 BA 7 , another index variable j is assigned to ( 1 , 1 ) denoting scheduling time  1  and interconnection network  1  respectively. Then act  44 BA 8  checks if j is greater than (r,3) which means if all the three interconnection network in all r scheduling times are checked or not. If the answer is “no” the control transfers to act  44 BA 9 . Act  44 BA 9  checks if i is equal to j, i.e., i. 1  is equal to j. 1  and also i. 2  is equal to j. 2 . If act  44 BA 9  results in “no”, the control transfers to act  44 BA 10 . In act  44 BA 10 , a set O j  is generated to determine the set of destination switches of c having available links from j. In act  44 BA 11 , it is checked if O k  is a subset of O j . If the answer is “yes”, it means packet request c has open paths to all its destination output ports through two interconnection networks denoted by tuples i and j. In that case, in act  44 C 2  packet request is scheduled through interconnection network i. 2  of scheduling time i. 1  and interconnection network j. 2  of scheduling time j. 1  by fanning out twice in the input port of packet request c. Act  44 D 2  marks the used first and second internal links to and from both i and j as unavailable. From act  44 D 2  control transfers to act  44 A.  
      If act  44 BA 11  results in “no” the control transfers to act  44 BA 12 . Also if act  44 BA 9  results in “no” the control transfers to act  44 BA 12 . In act  44 BA 12 , if j. 2  is less than 3, tuple j is adjusted so that j. 2  is incremented by  1  to check the next interconnection network in the same scheduling time j. 1 . If j. 2  is equal to 3, tuple j is adjusted so that j. 1  is incremented by  1  to check the next scheduling time and the interconnection network  1 . Then control transfers to act  44 BA 8 . And if act  44 BA 2  results in “yes” the control transfers to act  44 BA 13 . Thus acts  44 BA 8 ,  44 BA 9 ,  44 BA 10 ,  44 BA 11 , and  44 BA 12  form the inner loop of the doubly nested loop to schedule packet request c.  
      The following method illustrates the psuedo code for one implementation of the acts  44 B,  44 C, and  44 D of the scheduling method  44  of  FIG. 5A  to schedule r 2  packets in a strictly nonblocking manner by using the speedup of three in the middle stage  130  (with either three interconnection networks, or a speedup of three in clock speed and link speeds) in the switch fabrics in  FIG. 4A-4F .  
      Pseudo Code of the Scheduling Method:  
                                      Step 1:   c = current packet request;       Step 2:   for i = each interconnection network in each scheduling time do {       Step 3:    if (c has no available link to i) continue;       Step 4:     O i  = Set of all destination output ports of c having available links from i;       Step 5:     O k  = Set of all destination output ports of c having no available links from i;       Step 6:    if (O i  = All the required destination output ports of c) {             Schedule c through i;             Mark all the used paths to and from i as unavailable;            }       Step 7:    for j = each interconnection network in each scheduling time do {       Step 8:     if (i = j) {              continue;       Step 9:     } else {               O j  = Set of all destination output ports of c having available links from j;       Step 10:        if (O k     O j ) {                 Schedule c through i and j;                 Mark all the used paths to and from i and j as unavailable;                }             }            }           }                  
 
      Step 1 above labels the current packet request as “c”. Step 2 starts an outer loop of a doubly nested loop and steps through all interconnection networks in each of r scheduling times. If the input switch of c has no available link to interconnection network of scheduling time denoted by i, the next interconnection network in the same scheduling time or the first interconnection network in the next scheduling time is selected to be i in the Step 3. Steps 4 and 5 determine the set of destination output ports of c having and not having available links from i, respectively. In Step 6 if interconnection network of scheduling time denoted by i have available links to all the destination output ports of packet request c, packet request c is set up through interconnection network of scheduling time denoted by i. And all the used links of interconnection network of scheduling time denoted by i to output ports and from input port are marked as unavailable for future requests. Step 7 starts the inner loop to step through all the interconnection network of scheduling times to search for the second interconnection network of scheduling time, and if i is same as j, Step 8 continues to select the next interconnection network in the same scheduling time or the first interconnection network in the next scheduling time to be j. Step 9 determines the set of all destination output ports having available links from j. And in Step 10, if all the links that are unavailable from i are available from j, packet request c is scheduled through i and j. All the used links from i and j to output ports are marked as unavailable. These steps are repeated for all the pairs of all interconnection networks in each of r scheduling times. One or two interconnection networks in one or two of r scheduling times can always be found through which c can be scheduled. It is easy to observe that the number of steps performed by the scheduling method is proportional to s 2 *r 2 , where m is the number of middle switches in the network and hence the scheduling method is of time complexity O(s 2 *r 2 ).  
      In strictly nonblocking scheduling of the switch fabric, to schedule a packet request from an input queue to an output queue, it is always possible to find a path through the interconnection network to satisfy the request without disturbing the paths of already scheduled packets, and if more than one such path is available, any of them can be selected without being concerned about the scheduling of the rest of the packet requests. In strictly nonblocking networks, the switch hardware cost is increased but the time required to schedule packets is reduced compared to rearrangeably nonblocking switch fabrics. Embodiments of strictly nonblocking switch fabrics with a speedup of three in the middle stage, using the scheduling method  44  of  FIG. 5A  of time complexity O(s 2 *r 2 ), are shown in switch fabric  10  of  FIG. 1A  and switch fabric  16  of  FIG. 1I .  
      In rearrangeably nonblocking switch fabrics, the switch hardware cost is reduced at the expense of increasing the time required to schedule packets. The scheduling time is increased in a rearrangeably nonblocking network because the paths of already scheduled packets that are disrupted to implement rearrangement need to be scheduled again, in addition to the schedule of the new packet. For this reason, it is desirable to minimize or even eliminate the need for rearrangements of already scheduled packets when scheduling a new packet. When the need for rearrangement is eliminated, that network is strictly nonblocking depending on the number of middle stage interconnection networks and the scheduling method. One embodiment of rearrangeably nonblocking switch fabrics using a speedup of two in the middle stage is shown in switch fabric  18  of  FIG. 1N . It must be noted that the arbitration of generation of requests, issuance of grants, and generating acceptances is performed in only one iteration irrespective of whether the switch fabric is operated in strictly nonblocking manner or in rearrangeably nonblocking manner.  
      Strictly nonblocking multicast switch fabrics described in the current invention require scheduling method of O(s 2 *r 2 ) time complexity. If the speedup in the middle stage interconnection networks is increased further the scheduling method time complexity is reduced to O(s*r). The strictly nonblocking networks with linear scheduling time complexity are described in the related U.S. patent application Ser. No. 10/933,899 as well as its PCT Application Serial No. 04/29043 entitled “STRICTLY NON-BLOCKING MULTICAST LINEAR-TIME MULTI-STAGE NETWORKS” and U.S. patent application Ser. No. 10/933,900 as well as its PCT Application Serial No. 04/29027 entitled “STRICTLY NON-BLOCKING MULTICAST MULTI-SPLIT LINEAR-TIME MULTI-STAGE NETWORKS” that is incorporated be reference above. Applicant notes that switch fabrics are also operable in strictly nonblocking manner, by directly extending the speedup in the middle stage as described in these two related U.S. Patent Applications, and thereby using scheduling methods of linear time complexity.  
      Accordingly with additional speedup and thereby using scheduling method of linear time complexity,  FIG. 6A  shows one implementation of act  44  of the arbitration and scheduling method  40  of  FIG. 1B . The scheduling of r 2  packets is performed in act  44 . In act  44 A, it is checked if there are more packets to schedule. If there are more packets to schedule, i.e., if all r 2  packets are not scheduled, the control transfers to act  44 B. In act  44 B an open path through one of the three interconnection networks in the middle stage is selected by searching through r scheduling times. The packet is scheduled through the selected path and selected scheduling time in act  44 C. In  44 D the selected first internal link and second internal link are marked as selected so that no other packet selects these links in the same scheduling time. Then control returns to act  44 A and thus acts  44 A,  44 B,  44 C, and  44 D are executed in a loop to schedule each packet.  
       FIG. 6B  shows a low-level flow chart of one variant of act  44  of  FIG. 6A . Act  44 A transfers the control act  44 B if there is a new packet request to schedule. Act  44 B 1  assigns the new packet request to c. In act  44 B 2  sched_time_ 1  is assigned to index variable i. Then act  44 B 3  checks if i is less than or equal to schedule time r. If the answer is “YES” the control transfers to act  44 B 4 . Another index variable j is set to interconnection network  1  in Act  44 B 4 . Act  44 B 5  checks if j is either interconnection network  1 -x, the value of x being as described in the related U.S. Provisional Patent Applications. If the answer is “YES” the control transfers to act  44 B 6 . Act  44 B 6  checks if packet request c has no available first internal link to interconnection network j in the scheduling time i. If the answer is “NO”, act  44 B 7  checks of interconnection network j in scheduling time i has no available second internal link to the destined output port of the packet request c. If the answer is “NO”, the control transfers to act  44 C. In act  44 C the packet request c is scheduled through the interconnection network j in the scheduling time i, and then in act  44 D the first and second internal links, corresponding to the interconnection network j in the scheduling time i, are marked as used. Then the control goes to act  44 A. If the answer results in “YES” in either act  44 B 6  or act  44 B 7  then the control transfers to act  44 B 9  where j is incremented by 1 and the control goes to act  44 B 5 . If the answer results in “NO” in act  44 B 5 , the control transfers to act  44 B 10 . Act  44 B 10  increments i by 1, and the control transfers to act  44 B 3 . Act  44 B 3  never results in “NO”, meaning that in the r scheduling times, the packet request c is guaranteed to be scheduled. Act  44 B comprises two loops. The inner loop is comprised of acts  44 B 5 ,  44 B 6 ,  44 B 7 , and  44 B 9 . The outer loop is comprised of acts  44 B 3 ,  44 B 4 ,  44 B 5 ,  44 B 6 ,  44 B 7 ,  44 B 9 , and  44 B 10 . The act  44  is repeated for all the packet requests until all r 2  packet requests are scheduled.  
      The following method illustrates the psuedo code for one implementation of the scheduling method  44  of  FIG. 6A  to schedule r 2  packet requests in a strictly nonblocking manner by using the speedup of three in the middle stage  130  (with either three interconnection networks, or a speedup of three in clock speed and link speeds) in the switch fabrics in  FIG. 4A-4F .  
                                      Step 1:   for each packet request to schedule do {       Step 2:   c = packet schedule request;       Step 3:    for i = sched_time_1 to sched_time_r do {       Step 4:     for j = inter_conn_net_1 to inter_conn_net_x do {       Step 5:      if (c has no available first internal link to j) continue;       Step 6:      elseif (j has no available second internal link to the destined output port of c) continue;       Step 7:      else {               Schedule c through interconnection network j in the schedule time i;               Mark the used links to and from interconnection network j as unavailable;              }             }            }           }                  
 
      Step 1 starts a loop to schedule each packet Step 2 labels the current packet request as “c”. Step 3 starts a second loop and steps through all the r scheduling times. Step 4 starts a third loop and steps through x interconnection networks. If the input port of packet request c has no available first internal link to the interconnection network j in the scheduling time i in Step 5, the control transfers to Step 4 to select the next interconnection network to be i. Step 6 checks if the destined output port of packet request c has no available second internal link from the interconnection network j in the scheduling time i, and if so the control transfers to Step 4 to select the next interconnection network to be i. In Step 7 packet request c is set up through interconnection network j in the scheduling time i. And the first and second internal links to the interconnection network j in the scheduling time i are marked as unavailable for future packet requests. These steps are repeated for all x interconnection networks in all the r scheduling times until the available first and second internal links are found. In accordance with the current invention, one interconnection network in one of r scheduling times can always be found through which packet request c can be scheduled. It is easy to observe that the number of steps performed by the scheduling method is proportional to s*r, where s is the speedup equal to x and r is the number of scheduling times and hence the scheduling method is of time complexity O(s*r).  
      Table 6 shows how the steps 1-8 of the above pseudo code implement the flowchart of the method illustrated in  FIG. 6B , in one particular implementation.  
                   TABLE 6                       Steps of the pseudo           code of the   Acts of       scheduling method   Flowchart of  FIG. 6B                    1   44A       2   44B1       3   44B2, 44B3, 44B10       4   44B4, 44B5, 44B9       5   44B6       6   44B7       7   44C, 44D                  
 
      Also according to the current invention, a direct extension of the speedup required in the middle stage  130  for the switch fabric to be operated in nonblocking manner is proportionately adjusted depending on the number of control bits that are appended to the packets before they are switched to the output ports. For example if additional control bits of 1% are added for every packet or packet segment (where these control bits are introduced only to switch the packets from input to output ports) to be switched from input ports to output ports, the speedup required in the middle stage  130  for the switch fabric is 3.01 to be operated in strictly nonblocking manner and 2.01 to be operated in rearrangeably nonblocking manner.  
      Similarly according to the current invention, when the packets are segmented and switched to the output ports, the last packet segment may or may not be the same as the packet segment. Alternatively if the packet size is not a perfect multiple of the packet segment size, thoughput of the switch fabric would be less than 100%. In embodiments where the last packet segment is frequently smaller than the packet segment size, the speedup in the middle stage needs to be proportionately increased to operate the system at 100% thoughput.  
      The current invention of nonblocking and deterministic switch fabrics can be directly extended to arbitrarily large number of input queues, i.e., with more than one input queue in each input port switching to more than one output queue in the destination output port, and each of the input queues holding a different multicast flow or a group of multicast microflows in all the input ports offer flow by flow QoS with rate and latency guarantees. End-to-end guaranteed bandwidth i.e., for multiple flows in different input queues of an input port to any destination output port can be provided. Moreover guaranteed and constant latency is provided for packet flows from multiple input queues in an input port to any destination output port. Since each input queue in an input port holding different flow but switches packets into the same destined output port, a longer packet from one input queue will not prevent another smaller packet from a second input queue of the same input port switching into the same destination output port, and thus enforcing the latency guarantees of packet flows from the input ports. Here also the switching time of switch fabric determines the latency of the packets in each flow and also the latency of packet segments in each packet.  
      By increasing the number of multicast flows that are separately switched from input queues into output ports, end to end guaranteed bandwidth and latency can be provided for fine granular flows. And also each flow can be individually shaped and if necessary by predictably tail dropping the packets from desired flows under oversubscription and providing the service providers to offer rate and latency guarantees to individual flows and hence enable additional revenue opportunities.  
      Numerous modifications and adaptations of the embodiments, implementations, and examples described herein will be apparent to the skilled artisan in view of the disclosure.  
      The embodiments described in the current invention are also useful directly in the applications of parallel computers, video servers, load balancers, and grid-computing applications. The embodiments described in the current invention are also useful directly in hybrid switches and routers to switch both circuit switched time-slots and packet switched packets or cells.  
      Numerous such modifications and adaptations are encompassed by the attached claims.