Patent Publication Number: US-2022222160-A1

Title: Data accessing method using dynamic speed adjustment with aid of thermal control unit, and associated apparatus

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to memory control, and more particularly, to a data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as a memory device, a memory controller of the memory device, and an electronic system equipped with the memory device. 
     2. Description of the Prior Art 
     Developments in memory technology have enabled the wide application of various portable and non-portable memory devices (e.g. memory cards conforming to the SD/MMC, CF, MS, XD or UFS specifications, solid state drives (SSDs), embedded storage devices conforming to the UFS or EMMC specifications, etc.). Improving access control of memories in these memory devices remains an issue to be solved in the art. 
     NAND flash memories may comprise single level cell (SLC) and multiple level cell (MLC) flash memories. In an SLC flash memory, each transistor used as a memory cell may have either of two electrical charge values respectively corresponding to logic values 0 and 1. In comparison, the storage ability of each transistor used as a memory cell in an MLC flash memory may be fully utilized. The transistor in the MLC flash memory can be driven by a voltage higher than that in the SLC flash memory, and different voltage levels can be utilized to record information of at least two bits (e.g. 00, 01, 11, or 10). In theory, the recording density of the MLC flash memory may reach at least twice the recording density of the SLC flash memory, and is therefore preferred by manufacturers of NAND flash memories. 
     The lower cost and larger capacity of the MLC flash memory means it is more likely to be applied in memory devices than an SLC flash memory. The MLC flash memory does have instability issues, however. To ensure that access control of the flash memory in the memory device meets required specifications, a controller of the flash memory may be equipped with some management mechanisms for properly managing data access. 
     Even memory devices with the above management mechanisms may have certain deficiencies, however. For example, during a data accessing of a memory device, high speed data transmission may lead to heat accumulation, which may cause degraded performance of the memory device, and more particularly, cause malfunction of the memory device. Hence, there is a need for a novel method and associated architecture to improve the performance of the memory device without introducing a side effect or in a way that is less likely to introduce a side effect. 
     SUMMARY OF THE INVENTION 
     It is an objective of the present invention to provide a data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as a memory device, a memory controller of the memory device, and an electronic system equipped with the memory device, in order to solve the above-mentioned problems. 
     It is another objective of the present invention to provide a data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as a memory device, a memory controller of the memory device, and an electronic system equipped with the memory device, in order to achieve optimal performance of the memory device. 
     At least one embodiment of the present invention provides data accessing method using dynamic speed adjustment with aid of a thermal control unit, where the data accessing method is applicable to a memory controller of a memory device. The memory device may comprise the memory controller and a non-volatile (NV) memory, and the NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements). The data accessing method may comprise: utilizing a thermal control unit within the memory controller to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from a host device, controlling a transmission interface circuit of the memory controller to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, detecting an increment of the temperature between a first start time point and a first end time point, wherein a first time period from the first start time point to the first end time point corresponds to a first predetermined time difference; based on at least one first predetermined rule, determining a first communications speed according to the increment; and controlling the transmission interface circuit to switch from the original communications speed to the first communications speed, for performing data transmission between the host device and the memory controller at the first communications speed. 
     In addition to the above method, the present invention also provides a memory controller of a memory device, where the memory device comprises the memory controller and an NV memory. The NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements). In addition, the memory controller comprises a processing circuit, and the processing circuit is arranged to control the memory controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the memory controller. The memory controller further comprises a transmission interface circuit and a memory device protection circuit that are coupled to the processing circuit. The transmission interface circuit is arranged to perform communications with the host device, and the memory device protection circuit is arranged to perform memory device protection on the memory device. Additionally, the memory device protection circuit may comprise a thermal control unit, where the thermal control unit is arranged to perform thermal control, for triggering dynamic speed adjustment during data accessing. For example, the memory controller utilizes the thermal control unit to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from the host device, the memory controller controls the transmission interface circuit to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, the memory controller detects an increment of the temperature between a first start time point and a first end time point, wherein a first time period from the first start time point to the first end time point corresponds to a first predetermined time difference; based on at least one first predetermined rule, the memory controller determines a first communications speed according to the increment; and the memory controller controls the transmission interface circuit to switch from the original communications speed to the first communications speed, for performing data transmission between the host device and the memory controller at the first communications speed. 
     In addition to the above method, the present invention also provides the memory device comprising the above memory controller, wherein the NV memory is arranged to store information, and the memory controller is coupled to the NV memory, and is arranged to control operations of the memory device. 
     The present invention method and associated apparatus can guarantee that the memory device can operate properly in various situations without encountering the related art problems. For example, the data accessing method provides multiple control schemes for access control. With aid of the present invention method and associated apparatus, the memory device will not suffer from the existing problems of the related art, such as the degraded performance problem, the malfunction problem, etc. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of an electronic system according to an embodiment of the present invention, where the electronic system comprises a host device and a memory device. 
         FIG. 2  illustrates a temperature-aware speed control scheme of a data accessing method using dynamic speed adjustment with aid of a thermal control unit according to an embodiment of the present invention. 
         FIG. 3  illustrates some implementation details of the timer regarding the temperature-aware speed control scheme shown in  FIG. 2  according to an embodiment of the present invention. 
         FIG. 4  illustrates some implementation details of the thermal control unit regarding the temperature-aware speed control scheme shown in  FIG. 2  according to an embodiment of the present invention. 
         FIG. 5  illustrates a speed-down control scheme of the data accessing method according to an embodiment of the present invention. 
         FIG. 6  illustrates a working flow of the speed-down control scheme shown in  FIG. 5  according to an embodiment of the present invention. 
         FIG. 7  illustrates a speed-up control scheme of the data accessing method according to an embodiment of the present invention. 
         FIG. 8  illustrates a working flow of the speed-up control scheme shown in  FIG. 7  according to an embodiment of the present invention. 
         FIG. 9  is a flowchart of the data accessing method using dynamic speed adjustment with aid of the thermal control unit according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a diagram of an electronic system  10  according to an embodiment of the present invention, where the electronic system  10  comprises a host device  50  and a memory device  100 . The host device  50  may comprise at least one processor (e.g. one or more processors) which may be collectively referred to as the processor  52 , and may further comprise a power supply circuit  54  that is coupled to the processor  52 . The processor  52  is arranged for controlling operations of the host device  50 , and the power supply circuit  54  is arranged for providing power to the processor  52  and the memory device  100 , and outputting one or more driving voltages to the memory device  100 . The memory device  100  may be arranged for providing the host device  50  with storage space, and obtaining the one or more driving voltages from the host device  50  as power source of the memory device  100 . Examples of the host device  50  may include, but are not limited to: a multifunctional mobile phone, a wearable device, a tablet computer, and a personal computer such as a desktop computer and a laptop computer. Examples of the memory device  100  may include, but are not limited to: a solid state drive (SSD), and an embedded storage device such as that conforming to Universal Flash Storage (UFS) or embedded MMC (eMMC) specifications. According to this embodiment, the memory device  100  may comprise a memory controller  110  and a non-volatile (NV) memory  120 , where the memory controller  110  is arranged to control operations of the memory device  100  and access the NV memory  120 , and the NV memory  120  is arranged to store information. The NV memory  120  may comprise at least one NV memory element (e.g. one or more NV memory elements), such as a plurality of NV memory elements  122 - 1 ,  122 - 2 , . . . , and  122 -N, where “N” may represent a positive integer that is greater than one. For example, the NV memory  120  may be a flash memory, and the plurality of NV memory elements  122 - 1 ,  122 - 2 , . . . , and  122 -N may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto. 
     As shown in  FIG. 1 , the memory controller  110  may comprise a processing circuit such as a microprocessor  112 , a storage unit such as a read-only memory (ROM)  112 M, a control logic circuit  114 , an error correction code (ECC) circuit  115 , a random access memory (RAM)  116 , a transmission interface circuit  118  and a memory device protection circuit  119  (labeled “MDP circuit” in  FIG. 1 , for brevity), where the above components can be coupled to one another via a bus. The RAM  116  is implemented by a Static RAM (SRAM), but the present invention is not limited thereto. The RAM  116  can be arranged to provide the memory controller  110  with internal storage space. For example, the RAM  116  can be utilized as a buffer memory for buffering data. In addition, the ROM  112 M of this embodiment is arranged to store a program code  112 C, and the microprocessor  112  is arranged to execute the program code  112 C to control the access of the NV memory  120 . Note that, in some examples, the program code  112 C can be stored in the RAM  116  or any type of memory. Further, the data protection circuit  115  can be configured to protect data and/or perform error correction, where the ECC circuit  115 E can protect data and/or perform error correction. The transmission interface circuit  118  can conform to a specific communications specification (e.g. UFS specification), and can perform communications according to the specific communications specification, for example, perform communications with the host device  50  for the memory device  100 . The memory device protection circuit  119  can be configured to perform memory device protection on the memory device  100 . For example, the memory device protection circuit  119  may comprise a timer  119 TR and a thermal control unit  119 TC, where the timer  119 TR can perform timing control, and the thermal control unit  119 TC can perform thermal control, for triggering dynamic speed adjustment during data accessing. With aid of the timing control of the timer  119 TR and the thermal control of the thermal control unit  119 TC, the memory controller  110  can perform dynamic speed adjustment during data accessing. 
     In this embodiment, the host device  50  may transmit host commands and corresponding logical addresses to the memory controller  110  to access the memory device  100 . The memory controller  110  receives the host commands and the logical addresses, and translates the host commands into memory operating commands (which may be simply referred to as operating commands), and further controls the NV memory  120  with the operating commands to perform reading, writing/programing, etc. on memory units (e.g. data pages) having physical addresses within the NV memory  120 , where the physical addresses may be associated with the logical addresses. When the memory controller  110  perform an erase operation on any NV memory element  122 - n   0  of the plurality of NV memory elements  122 - 1 ,  122 - 2 , . . . , and  122 -N (in which “n 0 ” may represent any integer in the interval [1, N]), at least one physical block of multiple physical blocks of the NV memory element  122 - n   0  may be erased, where each physical block of the multiple physical blocks may comprise multiple physical pages (e.g. data pages), and an access operation (e.g. reading or writing) may be performed on one or more physical pages. 
     When the host device  50  accesses the memory device  100  (e.g. the NV memory  120  therein, with aid of the memory controller  110 ), an accessing request (e.g. a read request, a write request, etc.) from the host device  50  may carry a logical address, and the logical address may comprise a logical block address (LBA) indicating a logical block, and more particularly, may further comprise a logical page address indicating a logical page in the logical block. The memory device  100  (e.g. the memory controller  110 ) can store and update at least one logical-to-physical (L2P) address mapping table (e.g. one or more L2P address mapping tables) in the NV memory  120 , to manage mapping relationships between logical blocks and physical blocks according to a block-based mapping control scheme, and more particularly, to manage mapping relationships between logical blocks and pages and physical blocks and pages according to a page-based mapping control scheme. 
     According to some embodiments, the memory device  100  may be implemented to be a memory card conforming to the SD/MMC, CF, MS, XD or UFS specifications, where the memory device  100  may be coupled to the host device  50  through an intermediate device such as a memory card reader, but the present invention is not limited thereto. 
       FIG. 2  illustrates a temperature-aware speed control scheme of a data accessing method using dynamic speed adjustment with aid of a thermal control unit (e.g. the thermal control unit  119 TC shown in  FIG. 1 ) according to an embodiment of the present invention. The data accessing method is applicable to the electronic system  10  shown in  FIG. 1 , and more particularly, the memory device  100  and the memory controller  110  therein. The plurality of NV memory elements  122 - 1 ,  122 - 2 , . . . , and  122 -N of this embodiment can be implemented as a set of flash memory dies  122  (labeled “Flash die” for brevity). As shown in  FIG. 2 , the control logic circuit  114  may comprise a Flash controller  114 F and a Non-Volatile Memory Express (NVMe) controller  114 N, where the Flash controller  114 F can control the NV memory  120  (e.g. the set of flash memory dies  122 ) with the memory operating commands, and the NVMe controller  114 N can operate according to NVMe specification, to make the control logic circuit  114  be capable of controlling the NV memory  120  (e.g. the set of flash memory dies  122 ) in response to NVMe commands. In addition, the transmission interface circuit  118  can be configured to conform to PCIe specification, and therefore at least one portion (e.g. a portion or all) of the transmission interface circuit  118  can be regarded as the PCIe interface circuit of the memory controller  110 , and a corresponding transmission interface circuit in the host device  50  can be configured to conform to PCIe specification, and therefore at least one portion (e.g. a portion or all) of the corresponding transmission interface circuit can be regarded as the PCIe interface circuit of the host device  50 , such as the Root Complex in the host device  50  shown in  FIG. 2 . Additionally, the PCIe interface circuit within the transmission interface circuit  118  may comprise a PCIe Media Access Control (MAC) circuit  118 M and a PCIe physical layer (PHY) circuit  118 P, for performing associated operations regarding MAC and PHY, respectively. For example, the PCIe MAC circuit  118 M may comprise a register circuit  118 R, to allow the microprocessor  112  to perform associated control on the PCIe MAC circuit  118 M, for controlling data speed adjustment during data accessing, where the register circuit  118 R may comprise multiple registers such as the registers REG 1 , REG 2 , etc., and the microprocessor  112  can set the respective register values of the registers REG 1 , REG 2 , etc. 
     The host device  50  and the memory controller  110  can be configured to establish a PCIe link via the respective PCIe interface circuits of the host device  50  and the memory controller  110  (labeled “PCIe link via PCIe Interface” for brevity). Regarding data transmission between the host device  50  and the memory controller  110 , the register REG 1  can be utilized for triggering speed change, and therefore can be regarded as a Trigger-Speed-Change Register (TSCR), and the register REG 2  can be utilized for setting a target communications speed (e.g. a transfer rate, typically measured in unit of gigatransfers/gigatransactions per second (GT/s) for PCIe interfaces), and therefore can be regarded as a Target-Speed Register (TSR). As shown in  FIG. 2 , the microprocessor  112  can control the timer  119 TR with a predetermined counter value COUNT and a start counting signal START, and the timer  119 TR can start counting in response to trigger of the start counting signal START and count until the predetermined counter value COUNT is reached, for performing the timing control for the microprocessor  112 . When 1 the predetermined counter value COUNT is reached, the timer  119 TR can send a timeout signal TIMEOUT (e.g. an interrupt such as a timeout interrupt) to notify the microprocessor  112  of timeout (e.g. the predetermined counter value COUNT is reached). In addition, the microprocessor  112  can control the thermal control unit  119 TC with at least one threshold THRESHOLD such as a first temperature threshold δ H  and a second temperature threshold δ L , and the thermal control unit  119 TC can monitor temperature T at a predetermined intra-controller location of the memory controller  110 , send a temperature signal TEMPERATURE carrying the latest value of the temperature T to the microprocessor  112 , and perform temperature-related detection on the temperature T according to one or more of the first temperature threshold δ H  and the second temperature threshold δ L . For example, when the temperature T is greater than the first temperature threshold δ H , the thermal control unit  119 TC can send an interrupt signal INTERRUPT (e.g. another interrupt) to the microprocessor  112  to notify the microprocessor  112  of a first temperature-related detection result (e.g. the temperature T reaching the threshold THRESHOLD such as the first temperature threshold δ H , in an increasing direction of the temperature T). For another example, when the temperature T is less than the second temperature threshold δ L , the thermal control unit  119 TC can send the interrupt signal INTERRUPT to the microprocessor  112  to notify the microprocessor  112  of a second temperature-related detection result (e.g. the temperature T reaching the threshold THRESHOLD such as the second temperature threshold δ L , in a decreasing direction of the temperature T). 
     Based on the temperature-aware speed control scheme shown in  FIG. 2 , the memory device  100  (e.g. the memory controller  110 ) can dynamically adjust a PCIe link speed such as the speed of a PCIe link between the host device  50  and the memory controller  110 , to control the temperature and the power consumption of the memory device  100 . 
       FIG. 3  illustrates some implementation details of the timer  119 TR regarding the temperature-aware speed control scheme shown in  FIG. 2  according to an embodiment of the present invention. The timer  119 TR may comprise at least one register (e.g. one or more registers) such as the register  310 , and comprise a control unit  320  and a counter  330 , where the control unit  320  can be implemented with logic circuits  322 . The timer  119 TR can utilize the register  310  to store the predetermined counter value COUNT as the register value  312  (labeled “Value” for brevity) thereof. The control unit  320  can control operations of the timer  119 TR. For example, the control unit  320  can clear the register  310  by default. The microprocessor  112  can write the predetermined counter value COUNT into the register  310  and then send the start counting signal START. In response to the trigger of the start counting signal START, the control unit  320  can obtain the predetermined counter value COUNT from the register  310  and control the counter  330  to start counting until the counter value of the counter  330  reaches the predetermined counter value COUNT. For example, the predetermined counter value COUNT may correspond to a predetermined time difference. When the counter value of the counter  330  reaches the predetermined counter value COUNT, which may indicate that the predetermined time difference is expired, the control unit  320  can send the timeout signal TIMEOUT to notify the microprocessor  112  of timeout (e.g. the counter value of the counter  330  reaches the predetermined counter value COUNT). 
       FIG. 4  illustrates some implementation details of the thermal control unit  119 TC regarding the temperature-aware speed control scheme shown in  FIG. 2  according to an embodiment of the present invention. The thermal control unit  119 TC may comprise at least one register (e.g. one or more registers) collectively referred to as the register  410 , and further comprise a control unit  420  and a thermal sensor  430 , where the control unit  420  can be implemented with logic circuits  422 . The thermal control unit  119 TC can utilize the register  410  to store the threshold THRESHOLD such as the first temperature threshold δ H  and the second temperature threshold δ L  as the register values  412  (labeled “Value” for brevity) thereof. The control unit  420  can control operations of the thermal control unit  119 TC. For example, the control unit  420  can clear the register  410  by default. The microprocessor  112  can write the threshold THRESHOLD such as the first temperature threshold δ H  and the second temperature threshold δ L  into the register  410 . In addition, the control unit  420  can obtain the threshold THRESHOLD such as the first temperature threshold δ H  and the second temperature threshold δ L  from the register  410 , obtain the temperature T sensed by the thermal sensor  430 , and determine whether the temperature T reaches the threshold THRESHOLD, and more particularly, determine whether the temperature T reaches any of the first temperature threshold δ H  and the second temperature threshold δ L . For example, when T&gt;δ H , the control unit  420  can send the interrupt signal INTERRUPT to the microprocessor  112  to notify the microprocessor  112  of the first temperature-related detection result (e.g. the temperature T reaching the threshold THRESHOLD such as the first temperature threshold δ H ). For another example, when T&lt;δ L , the control unit  420  can send the interrupt signal INTERRUPT to the microprocessor  112  to notify the microprocessor  112  of the second temperature-related detection result (e.g. the temperature T reaching the threshold THRESHOLD such as the second temperature threshold δ L ). Additionally, the control unit  420  can send the temperature signal TEMPERATURE carrying the latest value of the temperature T to the microprocessor  112 , for being read by the microprocessor  112 . As the thermal control unit  119 TC can be positioned at the predetermined intra-controller location of the memory controller  110 , the microprocessor  112  can utilize the thermal control unit  119 TC to accurately monitor the temperature T at the predetermined intra-controller location. 
     For example, the predetermined intra-controller location may represent a predetermined sub-area of a chip area of an integrated circuit (IC) for implementing the memory controller  110 , where the predetermined sub-area may correspond to the transmission interface circuit  118 , and the temperature T may represent the temperature of the transmission interface circuit  118 . For better comprehension, the predetermined intra-controller location may represent a location next to the transmission interface circuit  118  or an intra-interface location within the transmission interface circuit  118 , but the present invention is not limited thereto. In addition, the second temperature threshold δ L  is typically less than the first temperature threshold δ H . For better comprehension, the first temperature threshold δ H  can be equal to any first predetermined value among multiple first predetermined values in a predetermined abnormal temperature range above a predetermined normal temperature range, and the second temperature threshold δ L  can be equal to any second predetermined value among multiple second predetermined values in the predetermined normal temperature range. For example, δ H =80 (° C.) and δ L =50 (° C.), but the present invention is not limited thereto. In some examples, the first temperature threshold δ H  and/or the second temperature threshold δ L  may vary. 
       FIG. 5  illustrates a speed-down control scheme of the data accessing method according to an embodiment of the present invention, where the power consumption POWER of the memory controller  110  (e.g. the transmission interface circuit  118 ) may vary with respect to time, and may be measured in unit of Watt (W). For better comprehension, the memory controller  110  (e.g. under control of the microprocessor  112 ) can reduce the power consumption POWER with various control schemes such as a Dynamic Voltage and Frequency Scaling (DVFS) control scheme regarding the microprocessor  112 , the speed-down control scheme regarding the transmission interface circuit  118 , etc., and more particularly, can decrease an operational frequency of the microprocessor  112  and decrease the communications speed (e.g. transfer rate) of the transmission interface circuit  118 , but the present invention is not limited thereto. For example, the memory controller  110  can merely decrease the communications speed (e.g. transfer rate) of the transmission interface circuit  118 , without adjusting the operational frequency of the microprocessor  112 , to guarantee the stability of the whole system of the memory device  100 . 
     As shown in  FIG. 5 , the memory controller  110  can trigger speed-down of the data transmission between the host device  50  and the memory controller  110  according to the speed-down control scheme, to switch from a higher speed to a lower speed, and the associated operations may comprise: 
     (1) with aid of the thermal control unit  119 TC, the microprocessor  112  detects that the temperature T reaches the threshold THRESHOLD, for example, T&gt;δ H ;
 
(2) the microprocessor  112  gets a first temperature value T 11  from the temperature signal TEMPERATURE at a first start time point t 11 ;
 
(3) the microprocessor  112  gets a second temperature value T 12  from the temperature signal TEMPERATURE at a first end time point t 12 ;
 
(4) the microprocessor  112  sets the Target-Speed Register such as the register REG 2 , to notify the transmission interface circuit  118  of the target communications speed, where the microprocessor  112  can determine the target communications speed according to an increment ΔT 1  (e.g. a positive value such as the difference (T 12 -T 11 ) between the second temperature value T 12  and the first temperature value T 11 ), for example, based on at least one first predetermined rule (e.g. one or more first predetermined rules); and
 
(5) the microprocessor  112  sets the Trigger-Speed-Change Register such as the register REG 1 , to make the transmission interface circuit  118  send a request of speed change to the Root Complex, where this request indicates the target communications speed;
 
but the present invention is not limited thereto. In some examples, the associated operations of the speed-down control scheme may vary.
 
       FIG. 6  illustrates a working flow of the speed-down control scheme shown in  FIG. 5  according to an embodiment of the present invention. 
     In Step S 10 , the thermal control unit  119 TC can check whether the temperature T reaches the threshold THRESHOLD such as the first temperature threshold δ H  in the increasing direction of the temperature T (e.g. T≥δ H ), and more particularly, check whether the temperature T is greater than the first temperature threshold δ H . If Yes (e.g. T&gt;δ H ), Step S 11  is entered; if No, Step S 10  is entered. 
     In Step S 11 , when T&gt;δ H , the microprocessor  112  can receive the interrupt signal INTERRUPT from the thermal control unit  119 TC. For example, the thermal control unit  119 TC can send the interrupt signal INTERRUPT to the microprocessor  112  when detecting that T&gt;δ H . 
     In Step S 12 , after receiving the interrupt signal INTERRUPT, the microprocessor  112  can read the temperature signal TEMPERATURE to obtain the latest value of the temperature T at the first start time point t 11 , and record the latest value of the temperature T to be the first temperature value T 11  corresponding to the first start time point t 11 . 
     In Step S 13 , the microprocessor  112  can set the predetermined counter value COUNT (e.g. a first predetermined counter value corresponding to a first predetermined time difference) into the timer  119 TR, and set the start counting signal START to make the timer  119 TR (e.g. the counter  330  therein) start counting. 
     In Step S 14 , when the counter value of the counter  330  reaches the predetermined counter value COUNT, the timer  119 TR can send the timeout signal TIMEOUT to notify the microprocessor  112  of timeout. 
     In Step S 15 , after receiving the timeout signal TIMEOUT, the microprocessor  112  can read the temperature signal TEMPERATURE to obtain the latest value of the temperature T at the first end time point t 12 , and record the latest value of the temperature T to be the second temperature value T 12  corresponding to the first end time point t 12 . 
     In Step S 16 , the microprocessor  112  can calculate the increment ΔT 1  such as the difference (T 12 −T 11 ) between the second temperature value T 12  and the first temperature value T 11 . 
     In Step S 17 , based on the at least one first predetermined rule, the microprocessor  112  can determine the target communications speed according to the increment ΔT 1 . For example, in a situation where an original communications speed such as the higher speed represents the PCIe Generation (Gen) 4 Speed Gen_4_Speed (e.g. 16 GT/s), the microprocessor  112  can determine the target communications speed TARGET_SPEED such as the lower speed to be a first communications speed among a first set of predetermined communications speeds, such as one of the PCIe Gen 1 Speed Gen_1_Speed (e.g. 2.5 GT/s), the PCIe Gen 2 Speed Gen_2_Speed (e.g. 5 GT/s) and the PCIe Gen 3 Speed Gen_3_Speed (e.g. 8 GT/s) that are less than the PCIe Gen 4 Speed Gen_4_Speed, and the at least one first predetermined rule may comprise: 
     (1) if ΔT 1 &gt;α 1 , TARGET_SPEED=Gen_1_Speed;
 
(2) if α 1 &gt;ΔT 1 &gt;β 1 , TARGET_SPEED=Gen_2_Speed; and
 
(3) if β 1 &gt;ΔT 1 &gt;γ 1 , TARGET_SPEED=Gen_3_Speed;
 
where α 1 &gt;β 1 &gt;γ 1 , but the present invention is not limited thereto. In another example, the above rules can be re-written as follows:
 
(1) if ΔT 1 ≥α 1 , TARGET_SPEED=Gen_1_Speed;
 
(2) if α 1 &gt;ΔT 1 ≥β 1 , TARGET_SPEED=Gen_2_Speed; and
 
(3) if β 1 &gt;ΔT 1 ≥γ 1 , TARGET_SPEED=Gen_3_Speed;
 
where α 1 &gt;β 1 &gt;γ 1 &gt;0. In some examples, the original communications speed such as the higher speed may represent any communications speed among the PCIe Gen 2 Speed Gen_2_Speed, the PCIe Gen 3 Speed Gen_3_Speed, the PCIe Gen 4 Speed Gen_4_Speed, the PCIe Gen 5 Speed Gen_5_Speed (e.g. 32 GT/s), etc., and the target communications speed TARGET_SPEED such as the lower speed may represent one of another set of predetermined communications speeds less than the any communications speed.
 
     In Step S 18 , the microprocessor  112  can set a register value corresponding to the target communications speed TARGET_SPEED determined in Step S 17  into the register REG 2 , to notify the transmission interface circuit  118  of the target communications speed TARGET_SPEED through the register REG 2 , where this register value of the register REG 2  indicates the target communications speed TARGET_SPEED determined in Step S 17 . 
     In Step S 19 , the microprocessor  112  can set a register value corresponding to a trigger state into the register REG 1 , to make the transmission interface circuit  118  send a request of speed change to the host device  50  (e.g. the Root Complex), where this request indicates the target communications speed TARGET_SPEED determined in Step S 17 . 
     For better comprehension, the method may be illustrated with the working flow shown in  FIG. 6 , but the present invention is not limited thereto. According to some embodiments, one or more steps may be added, deleted, or changed in the working flow shown in  FIG. 6 . 
       FIG. 7  illustrates a speed-up control scheme of the data accessing method according to an embodiment of the present invention. For better comprehension, the memory controller  110  (e.g. under control of the microprocessor  112 ) can enhance the overall processing performance with various control schemes such as the DVFS control scheme regarding the microprocessor  112 , the speed-up control scheme regarding the transmission interface circuit  118 , etc., and more particularly, can increase the operational frequency of the microprocessor  112  and increase the communications speed (e.g. transfer rate) of the transmission interface circuit  118 , where the power consumption POWER will be increased correspondingly, but the present invention is not limited thereto. For example, the memory controller  110  can merely increase the communications speed (e.g. transfer rate) of the transmission interface circuit  118 , without adjusting the operational frequency of the microprocessor  112 , to guarantee the stability of the whole system of the memory device  100 . 
     As shown in  FIG. 7 , the memory controller  110  can trigger speed-up of the data transmission between the host device  50  and the memory controller  110  according to the speed-up control scheme, to switch from a lower speed to a higher speed, and the associated operations may comprise: 
     (1) with aid of the thermal control unit  119 TC, the microprocessor  112  detects that the temperature T reaches the threshold THRESHOLD, for example, T&lt;δ L ;
 
(2) the microprocessor  112  gets a first temperature value T 21  from the temperature signal TEMPERATURE at a second start time point t 21 ;
 
(3) the microprocessor  112  gets a second temperature value T 22  from the temperature signal TEMPERATURE at a second end time point t 22 ;
 
(4) the microprocessor  112  sets the Target-Speed Register such as the register REG 2 , to notify the transmission interface circuit  118  of the target communications speed, where the microprocessor  112  can determine the target communications speed according to a decrement ΔT 2  (e.g. a positive value such as the difference (T 21 −T 22 ) between the first temperature value T 21  and the second temperature value T 22 , or an absolute value |(T 22 −T 21 )| of another difference (T 22 −T 21 ) if it is calculated by subtracting T 21  from T 22 ), for example, based on at least one second predetermined rule (e.g. one or more second predetermined rules); and
 
(5) the microprocessor  112  sets the Trigger-Speed-Change Register such as the register REG 1 , to make the transmission interface circuit  118  send a request of speed change to the Root Complex, where this request indicates the target communications speed;
 
but the present invention is not limited thereto. In some examples, the associated operations of the speed-up control scheme may vary.
 
       FIG. 8  illustrates a working flow of the speed-up control scheme shown in  FIG. 7  according to an embodiment of the present invention. 
     In Step S 20 , the thermal control unit  119 TC can check whether the temperature T reaches the threshold THRESHOLD such as the second temperature threshold δ L  in the decreasing direction of the temperature T (e.g. T≤δ L ), and more particularly, check whether the temperature T is less than the second temperature threshold δ L . If Yes (e.g. T&lt;δ L ), Step S 21  is entered; if No, Step S 20  is entered. 
     In Step S 21 , when T&lt;δ L , the microprocessor  112  can receive the interrupt signal INTERRUPT from the thermal control unit  119 TC. For example, the thermal control unit  119 TC can send the interrupt signal INTERRUPT to the microprocessor  112  when detecting that T&lt;δ L . 
     In Step S 22 , after receiving the interrupt signal INTERRUPT, the microprocessor  112  can read the temperature signal TEMPERATURE to obtain the latest value of the temperature T at the second start time point t 21 , and record the latest value of the temperature T to be the first temperature value T 21  corresponding to the second start time point t 21 . 
     In Step S 23 , the microprocessor  112  can set the predetermined counter value COUNT (e.g. a second predetermined counter value corresponding to a second predetermined time difference) into the timer  119 TR, and set the start counting signal START to make the timer  119 TR (e.g. the counter  330  therein) start counting. For example, the second predetermined counter value can be the same as the first predetermined counter value, and the second predetermined time difference can be the same as the first predetermined time difference. For another example, the second predetermined counter value can be different from the first predetermined counter value, and the second predetermined time difference can be different from the first predetermined time difference. 
     In Step S 24 , when the counter value of the counter  330  reaches the predetermined counter value COUNT, the timer  119 TR can send the timeout signal TIMEOUT to notify the microprocessor  112  of timeout. 
     In Step S 25 , after receiving the timeout signal TIMEOUT, the microprocessor  112  can read the temperature signal TEMPERATURE to obtain the latest value of the temperature T at the second end time point t 22 , and record the latest value of the temperature T to be the second temperature value T 22  corresponding to the second end time point t 22 . 
     In Step S 26 , the microprocessor  112  can calculate the decrement ΔT 2  such as the difference (T 21 −T 22 ) between the first temperature value T 21  and the second temperature value T 22 . 
     In Step S 27 , based on the at least one second predetermined rule, the microprocessor  112  can determine the target communications speed according to the decrement ΔT 2 . For example, in a situation where the first communications speed such as the lower speed represents the PCIe Gen 1 Speed Gen_1_Speed, the microprocessor  112  can determine the target communications speed TARGET_SPEED such as the higher speed to be a second communications speed among a second set of predetermined communications speeds, such as one of the PCIe Gen 4 Speed Gen_4_Speed, the PCIe Gen 3 Speed Gen_3_Speed and the PCIe Gen 2 Speed Gen_2_Speed that are greater than the PCIe Gen 1 Speed Gen_1_Speed, and the at least one second predetermined rule may comprise: 
     (1) if ΔT 2 &gt;α 2 , TARGET_SPEED=Gen_4_Speed;
 
(2) if α 2 &gt;ΔT 2 &gt;β 2 , TARGET_SPEED=Gen_3_Speed; and
 
(3) if β 2 &gt;ΔT 2 &gt;γ 2 , TARGET_SPEED=Gen_2_Speed;
 
where α 2 &gt;β 2 &gt;γ 2 , but the present invention is not limited thereto. In another example, the above rules can be re-written as follows:
 
(1) if ΔT 2 ≥α 2 , TARGET_SPEED=Gen_4_Speed;
 
(2) if α 2 &gt;ΔT 2 &gt;β 2 , TARGET_SPEED=Gen_3_Speed; and
 
(3) if β 2 &gt;ΔT 2 &gt;γ 2 , TARGET_SPEED=Gen_2_Speed;
 
where α 2 &gt;β 2 &gt;γ 2 &gt;0. In some examples, the first communications speed such as the lower speed may represent any communications speed among the PCIe Gen 1 Speed Gen_1_Speed, the PCIe Gen 2 Speed Gen_2_Speed, the PCIe Gen 3 Speed Gen_3_Speed, the PCIe Gen 4 Speed Gen_4_Speed, the PCIe Gen 5 Speed Gen_5_Speed, etc. except the highest communications speed available (e.g. the PCIe Gen 6 Speed Gen_6_Speed such as 64 GT/s), and the target communications speed TARGET_SPEED such as the higher speed may represent one of another set of predetermined communications speeds greater than the any communications speed.
 
     In Step S 28 , the microprocessor  112  can set a register value corresponding to the target communications speed TARGET_SPEED determined in Step S 27  into the register REG 2 , to notify the transmission interface circuit  118  of the target communications speed TARGET_SPEED through the register REG 2 , where this register value of the register REG 2  indicates the target communications speed TARGET_SPEED determined in Step S 27 . 
     In Step S 29 , the microprocessor  112  can set the register value corresponding to the trigger state into the register REG 1 , to make the transmission interface circuit  118  send a request of speed change to the host device  50  (e.g. the Root Complex), where this request indicates the target communications speed TARGET_SPEED determined in Step S 27 . 
     For better comprehension, the method may be illustrated with the working flow shown in  FIG. 8 , but the present invention is not limited thereto. According to some embodiments, one or more steps may be added, deleted, or changed in the working flow shown in  FIG. 8 . 
       FIG. 9  is a flowchart of the data accessing method using dynamic speed adjustment with aid of the thermal control unit according to an embodiment of the present invention. For example, Steps S 30  and S 31  can be performed in a default speed phase PHASE( 0 ), Steps S 40 -S 42  can be performed in a speed-down phase PHASE( 1 ), and Steps S 50 -S 52  can be performed in a speed-up phase PHASE( 2 ). 
     In Step S 30 , the memory controller  110  can utilize the thermal control unit  119 TC to start monitoring the temperature T at the predetermined intra-controller location of the memory controller  110 . 
     In Step S 31 , in response to at least one accessing request (e.g. one or more accessing requests, such as one or more read requests and/or one or more write requests) from the host device  50 , the memory controller  110  can control the transmission interface circuit  118  to perform data transmission between the host device  50  and the memory controller  110  at a default communications speed (e.g. the highest communications speed available among all PCIe multi-Gen Speeds such as the PCIe Gen 1 Speed Gen_1_Speed, the PCIe Gen 2 Speed Gen_2_Speed, the PCIe Gen 3 Speed Gen_3_Speed, the PCIe Gen 4 Speed Gen_4_Speed, etc.), for accessing (e.g. reading or writing) data in the NV memory  120 , but the present invention is not limited thereto. For example, in response to the aforementioned at least one accessing request, the memory controller  110  can continue accessing the NV memory  120  in one or more subsequent phases, and more particularly, control the transmission interface circuit  118  to perform data transmission between the host device  50  and the memory controller  110  at one or more other communications speeds (e.g. one or more of the remaining communications speeds among all PCIe multi-Gen Speeds such as the PCIe Gen 1 Speed Gen_1_Speed, the PCIe Gen 2 Speed Gen_2_Speed, the PCIe Gen 3 Speed Gen_3_Speed, the PCIe Gen 4 Speed Gen_4_Speed, etc.) in one or more phases among the speed-down phase PHASE( 1 ) and the speed-up phase PHASE( 2 ), for accessing data in the NV memory  120 . 
     In Step S 40 , in response to the temperature T being greater than the first temperature threshold δ H , the memory controller  110  can detect an increment ΔT 1  of the temperature T between a first start time point t 11  and a first end time point t 12 , where a first time period Δt 1  from the first start time point t 11  to the first end time point t 12  can be configured to correspond to the first predetermined time difference. For example, the memory controller  110  can correctly control the first time period Δt 1  with aid of the timer  119 TR, to make the first time period Δt 1  be equal to the first predetermined time difference. 
     In Step S 41 , based on the aforementioned at least one first predetermined rule, the memory controller  110  can determine a first communications speed (e.g. the lower speed of the speed-down control scheme) according to the increment ΔT 1 . 
     In Step S 42 , the memory controller  110  can control the transmission interface circuit  118  to switch from an original communications speed (e.g. the higher speed of the speed-down control scheme, such as the default communications speed or a previously increased communications speed of the speed-up phase PHASE( 2 ) in a previous iteration of the loop shown in  FIG. 9 ) to the first communications speed, for performing data transmission between the host device  50  and the memory controller  110  at the first communications speed. 
     In Step S 50 , in response to the temperature T being less than the second temperature threshold δ L , the memory controller  110  can detect a decrement ΔT 2  of the temperature T between a second start time point t 21  and a second end time point t 22 , where a second time period Δt 2  from the second start time point t 21  to the second end time point t 22  can be configured to correspond to the second predetermined time difference. For example, the memory controller  110  can correctly control the second time period Δt 2  with aid of the timer  119 TR, to make the second time period Δt 2  be equal to the second predetermined time difference. 
     In Step S 51 , based on the aforementioned at least one second predetermined rule, the memory controller  110  can determine a second communications speed (e.g. the higher speed of the speed-up control scheme) according to the decrement ΔT 2 . 
     In Step S 52 , the memory controller  110  can control the transmission interface circuit  118  to switch from the first communications speed (e.g. the lower speed of the speed-up control scheme) to the second communications speed, for performing data transmission between the host device  50  and the memory controller  110  at the second communications speed, where the first communications speed may represent a decreased communications speed that is just used in the speed-down phase PHASE( 1 ). 
     Regarding the speed-down phase PHASE( 1 ), the aforementioned at least one first predetermined rule can be arranged to map a first set of possible ranges of the increment ΔT 1  to a first set of predetermined communications speeds (e.g. a set of candidate communications speeds for being selected as the target communications speed TARGET_SPEED such as the lower speed of the speed-down control scheme), respectively. The first set of possible ranges may correspond to the respective ranges of the intervals (γ 1 , β 1 ), (β 1 , α 1 ) and (α 1 , ∞), and more particularly, comprise the respective ranges of varied (e.g. half-open and/or closed) and/or non-varied versions of these intervals, where each of the values α 1 , β 1  and γ 1  may be added into an associated interval of these intervals as an endpoint of the associated interval. For example, the first set of possible ranges may comprise the respective ranges of the intervals [γ 1 , β 1 ), [β 1 , α 1 ) and [α 1 , ∞). For another example, the first set of possible ranges may comprise the respective ranges of the intervals [γ 1 , β 1 ], (β 1 , α 1 ) and [α 1 , ∞). In Step S 41 , in response to the increment ΔT 1  falling within a possible range among the first set of possible ranges of the increment ΔT 1 , the memory controller  110  can select a predetermined communications speed corresponding to the possible range from the first set of predetermined communications speeds. For example, the aforementioned at least one first predetermined rule may comprise mapping relationships between the first set of possible ranges and the first set of predetermined communications speeds. 
     Regarding the speed-up phase PHASE( 2 ), the aforementioned at least one second predetermined rule can be arranged to map a second set of possible ranges of the decrement ΔT 2  to a second set of predetermined communications speeds (e.g. a set of candidate communications speeds for being selected as the target communications speed TARGET_SPEED such as the higher speed of the speed-up control scheme), respectively. The second set of possible ranges may correspond to the respective ranges of the intervals (γ 2 , β 2 ), (β 2 , α 2 ) and (α 2 , ∞), and more particularly, comprise the respective ranges of varied (e.g. half-open and/or closed) and/or non-varied versions of these intervals, where each of the values α 2 , β 2  and γ 2  may be added into an associated interval of these intervals as an endpoint of the associated interval. For example, the second set of possible ranges may comprise the respective ranges of the intervals [γ 2 , β 2 ), [β 2 , α 2 ) and [α 2 , ∞). For another example, the second set of possible ranges may comprise the respective ranges of the intervals [γ 2 , β 2 ], (β 2 , α 2 ) and [α 2 , ∞). In Step S 51 , in response to the decrement ΔT 2  falling within a possible range among the second set of possible ranges of the decrement ΔT 2 , the memory controller  110  can select a predetermined communications speed corresponding to the possible range from the second set of predetermined communications speeds. For example, the aforementioned at least one second predetermined rule may comprise mapping relationships between the second set of possible ranges and the second set of predetermined communications speeds. For brevity, similar descriptions for this embodiment are not repeated in detail here. 
     For better comprehension, the method may be illustrated with the working flow shown in  FIG. 9 , but the present invention is not limited thereto. According to some embodiments, one or more steps may be added, deleted, or changed in the working flow shown in  FIG. 9 . For example, a first partial working flow comprising Steps S 40 -S 42  may be repeated (e.g. by executing Steps S 40 -S 42  multiple times) to speed down multiple times in the speed-down phase PHASE( 1 ), and a second partial working flow comprising Steps S 50 -S 52  may be repeated (e.g. by executing Steps S 50 -S 52  multiple times) to speed up multiple times in the speed-up phase PHASE( 2 ). 
     According to some embodiments, in response to at least one additional accessing request (e.g. one or more additional accessing requests, such as one or more additional read requests and/or one or more additional write requests), the memory controller  110  can control the transmission interface circuit  118  to perform data transmission between the host device  50  and the memory controller  110  at any of all communications speeds available (e.g. any communications speed among all PCIe multi-Gen Speeds such as the PCIe Gen 1 Speed Gen_1_Speed, the PCIe Gen 2 Speed Gen_2_Speed, the PCIe Gen 3 Speed Gen_3_Speed, the PCIe Gen 4 Speed Gen_4_Speed, etc.) in any phase among the speed-down phase PHASE( 1 ) and the speed-up phase PHASE( 2 ), for accessing data in the NV memory  120 . For brevity, similar descriptions for these embodiments are not repeated in detail here. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.