Patent Publication Number: US-11650792-B2

Title: Multiple mode arithmetic circuit

Description:
PRIORITY APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/535,878, filed Aug. 8, 2019, the content of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     A field programmable gate array (FPGA) is composed of an array of programmable logic blocks that are interconnected with a reconfigurable routing network. Logic blocks vary in type and typically include reconfigurable logic, memories, and arithmetic logic. Reconfigurable logic is commonly implemented with lookup tables. 
     Different logic blocks are used to provide arithmetic functions in different modes (e.g., an integer mode and a floating-point mode). Accordingly, an FPGA that provides arithmetic functions in multiple modes dedicates some tiles to each mode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Some embodiments of the disclosed technology are illustrated by way of example and not limitation in the figures of the accompanying drawings. 
         FIG.  1    is a high-level diagrammatic view of a tile of an FPGA that uses a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  2    is a high-level diagrammatic view of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  3    is a high-level diagrammatic view of a memory circuit portion of an FPGA tile that fuses memory and arithmetic circuits, according to some example embodiments. 
         FIG.  4    is a diagrammatic view of a portion of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  5    is a diagrammatic view of a portion of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  6    is a diagrammatic view of a portion of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  7    is a diagrammatic view of a portion of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  8    is a diagrammatic view of a portion of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  9    is a table showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  10    is a table showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  11    is a table showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  12    is a table showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  13    is a table showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  14    is a table showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  15    is a table showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  16    is a table showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  17    is a flowchart illustrating operations of a method performed by a multiple mode arithmetic circuit, according to various embodiments of the invention. 
         FIG.  18    is a high-level diagrammatic view of a multiple mode arithmetic circuit, according to some example embodiments. 
         FIG.  19    is a diagrammatic view of a reduced-delay circuit for converting a fixed point value to a block floating point value, according to some example embodiments. 
         FIG.  20    is a block diagram illustrating components of a system for controlling fabrication of circuits described herein, according to some example embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Example methods, systems and circuits for a multiple mode arithmetic circuit will now be described. In the following description, numerous examples having example-specific details are set forth to provide an understanding of example embodiments. It will be evident, however, to one of ordinary skill in the art that these examples may be practiced without these example-specific details, and/or with different combinations of the details than are given here. Thus, specific embodiments are given for the purpose of simplified explanation, and not limitation. 
     A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two&#39;s complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. 
     The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. 
     By providing a multiple mode arithmetic circuit on a tile of an FPGA, the versatility of the tile and the resulting FPGA is increased. As a result, more tiles of the FPGA can be used under a wider variety of circumstances, improving the bandwidth of the arithmetic processing and reducing computation time in comparison to prior art implementations in which single mode arithmetic circuits are used. Though described herein as being provided on a tile of an FPGA, the multiple mode arithmetic circuit may also be used in an ASIC or hardened FPGA. 
       FIG.  1    is a high-level diagrammatic view of a tile  100  of an FPGA along with connected routing  105  and  110 . The tile  100  fuses memory and arithmetic circuits and comprises a machine-learning processor (MLP)  115 , a block random access memory (BRAM)  120 , and a logic random access memory (LRAM)  125 . The MLP  115  comprises a floating-point multiply and accumulate (MAC)  130  and an integer MAC  135 . The BRAM  120  comprises a memory  140 . 
     In a first operation mode, the MACs  130  and  135  receive inputs from one or more of the routing  105 , the LRAM  125 , the memory  140 , and an operand cascade input  145 . Outputs are provided by the MACs  130  and  135  to the routing  105 , an operand cascade output  160 , the LRAM  125 , or any suitable combination thereof. The memory  140  receives input from the routing  110 , a memory cascade input  155 , or both. Outputs are provided by the memory  140  to the routing  110 , a memory cascade output  165 , or both. In the first operation mode, the MACs  130  and  135  do not receive input from the routing  110  and the memory  140  does not receive input from the routing  105 . Thus, the inputs from the routing fabric of the FPGA are divided between the MLP  115  and the BRAM  120 , and the MLP  115  accesses data from the BRAM  120  within the tile  100 , without going through the switch fabric. 
     A typical MAC multiplies two or more products and adds the results to an accumulator. The MACs  130  and  135 , in some example embodiments, provide additional functionality by allowing partial products to be summed and provided as an output before being added to the accumulator. Thus, the individual partial products, sums of partial products for a current multiplication, and an accumulation result across multiple multiplication cycles may all be accessed by use of the MACs  130  and  135 . Though a single box is shown in  FIG.  1    for MACs  130  and  135 , in some example embodiments, multiple MACs of each type are used (e.g., two integer MACs and two floating-point MACs). 
     In a second operation mode, the MACs  130  and  135  receive inputs from one or more of the routing  105 , the routing  110 , the LRAM  125 , and the operand cascade input  145 . Outputs are provided by the MACs  130  and  135  to the routing  105 , the routing  110 , the operand cascade output  160 , the LRAM  125 , or any suitable combination thereof. In the second operation mode, the memory  140  does not receive inputs from the routing  105  or the routing  110 . Thus, in the second operation mode, the tile  100  operates as a dedicated MLP, with MLP  115  having full access to the routing fabric of the FPGA and the memory  140  effectively disabled. Nonetheless, the LRAM  125  may make use of some routing connections in the second operation mode. 
     In a third operation mode, the memory  140  receives input from the routing  105 , the routing  110 , the memory cascade input  155 , or any suitable combination thereof. Outputs are provided by the memory  140  to the routing  105 , the routing  110 , the memory cascade output  165 , or any suitable combination thereof. In the third operation mode, the MLP  115  does not receive inputs from the routing  105  or the routing  110 . Thus, in the third operation mode, the tile  100  operates as a dedicated BRAM, with BRAM  120  having full access to the routing fabric of the FPGA and the MLP  115  effectively disabled. 
     As shown in  FIG.  1   , the LRAM  125  is connected to the routing  105  and the routing  110 . In some example embodiments, the routing connections for the LRAM  125  are maintained in all operation modes. To use data stored in the LRAM  125  for calculations by the MLP  115 , control signals identify the address to read and the data from the LRAM  125  that is to be used. The data is provided from the LRAM  125  to the MLP  115  via intra-tile connections, without using the routing  105  or the routing  110 . 
     The intra-tile connections shown between the LRAM  125  and the memory  140  to the floating-point MAC  130  and the integer MAC  135  operate at a higher bandwidth than the routing  105  and  110 . In various example embodiments, the intra-tile data access speed is a factor of at least 10, 50, 100, or 500 times faster than the routing connection access speed. 
     The differences between the LRAM  125  and the BRAM  120  are typically implementation details such that the BRAM  120  is similar to a cache style memory (typically using SRAM cells) and the LRAM  125  is similar to a register file (typically using flops). However, these are not concrete rules, and other types of memory may be used for the LRAM  125  and the BRAM  120 . In some example embodiments, the BRAM  120  has a greater storage capacity than the LRAM  125  and is optimized for area and the LRAM  125  is optimized for latency. In further example embodiments, the LRAM  125  stores a working set of sums of partial products for matrix multiplications. 
     The FPGA tile  100  receives a clock input to control the rate at which operations are performed. A frequency multiplier (e.g., a 2× multiplier) may be applied to the input clock frequency to change the operation rate. In some example embodiments, running the FPGA tile  100  at twice the clock rate allows twice as many calculations to be performed by using the MAC  130  or the MAC  135  twice in a single (external) clock cycle. For example, in a 128-bit input mode, sufficient inputs may be provided to perform four calculations per clock cycle but the MAC hardware is sufficient to perform only two. Accordingly, by performing two calculations on each of two internal clock cycles, four calculations are performed on the single external clock cycle, allowing the FPGA tile  100  to perform as effectively as an alternative design comprising twice as many MACs. 
     As another example of an advantage of using a frequency multiplier, operations that reuse at least some of the input operands may be performed more efficiently. For example, when weights or coefficients from the routing  105  are the same for multiple operations, other coefficients may be updated using the higher-frequency internal clock (e.g., read from the BRAM  120 ) and the multiple operations performed within a single external clock cycle. One practical use of this advantage is in machine learning, with a batch size equal to the clock multiplier (e.g., 2). The results of the multiple operations may be accumulated together to generate a single output to the routing  105  per external clock cycle, output in parallel to the routing  105  if there are sufficient output pins, or stored in the BRAM  120 . 
       FIG.  2    is a high-level diagrammatic view of an arithmetic circuit portion  200  of a multiple mode arithmetic circuit, according to some example embodiments. In some example embodiments, the arithmetic circuit  200  is the MLP  115 . The arithmetic circuit  200  receives intra-tile inputs from the memory portion of the FPGA tile, routing fabric inputs from a routing fabric of the FPGA, control signals from the routing fabric of the FPGA, and operand cascade inputs from another FPGA tile without making use of the routing fabric. In various example embodiments, more or fewer inputs are present. 
     The arithmetic circuit  200  provides intra-tile outputs to the memory portion of the FPGA tile, routing fabric outputs to the routing fabric of the FPGA, and operand cascade outputs to another FPGA tile without making use of the routing fabric. In various example embodiments, more or fewer outputs are present. Typically, the operand cascade inputs are received from a first FPGA tile, the arithmetic circuit  200  is part of a second FPGA tile, and the operand cascade outputs are provided to a third FPGA tile. 
       FIG.  3    is a high-level diagrammatic view of a memory circuit portion  300  of an FPGA tile that fuses memory and arithmetic circuits, according to some example embodiments. In some example embodiments, the memory circuit  300  is the BRAM  120 . The memory circuit  300  receives intra-tile inputs from the arithmetic portion of the FPGA tile, routing fabric inputs from a routing fabric of the FPGA, control signals from the routing fabric of the FPGA, memory cascade inputs from a first FPGA tile, and reverse memory cascade inputs from a second FPGA tile. The cascade inputs do not make use of the routing fabric. The memory cascade inputs may comprise control signals as well as data signals. In various example embodiments, more or fewer inputs are present. 
     The memory circuit  300  provides intra-tile outputs to the arithmetic portion of the FPGA tile, routing fabric outputs to the routing fabric of the FPGA, memory cascade outputs to the second FPGA tile, and reverse memory cascade outputs to the first FPGA tile. In various example embodiments, more or fewer outputs are present. 
       FIG.  4    is a diagrammatic view of a portion  400  of a multiple mode arithmetic circuit, according to some example embodiments. The portion  400  comprises multiplexers  410 A,  410 B,  410 C, and  410 D; registers  420 A,  420 B,  420 C, and  420 D, referred to collectively as stage 0 delay registers  420 ; bit remap logic  430 A,  430 B,  430 C, and  430 D; and stage 1 delay registers  440  (shown in more detail as individual registers  510 A,  510 B,  510 C,  510 D,  510 E,  510 F,  510 G,  510 H,  510 I,  510 J,  510 K,  510 L,  510 M,  510 N,  510 O, and  510 P in  FIG.  5   ). The portion  400  accepts inputs for two multiply operands, A and B, remaps the operands to a format used by the next portion of the arithmetic circuit, and provides the remapped operands to delay registers used by the next portion. 
     The multiplexer  410 A selects the low bits for the B operand from four options: MLP_DIN[ 71 : 0 ], 72 bits of data received via the routing fabric  105 ; REGFILE_DOUT[ 71 : 0 ], 72 bits of data received from the LRAM  125  within the tile  100 ; BRAM_DOUT[ 71 : 0 ], 72 bits of data received from the BRAM  120  within the tile  100 ; and FWDI_MULTB_L[ 71 : 0 ], 72 bits of data received from the operand cascade input  145 . The multiplexer  410 B selects the high bits for the B operand from eight options: BRAM_DIN[ 71 : 0 ], 72 bits of data received via the routing fabric  110 ; REGFILE_DOUT[ 143 : 72 ], 72 bits of data received from the LRAM  125  within the tile  100 ; BRAM_DOUT[ 143 : 72 ], 72 bits of data received from the BRAM  120  within the tile  100 ; MLP_DIN[ 71 : 0 ]; REGFILE_DOUT[ 71 : 0 ]; BRAM_DOUT[ 71 : 0 ]; and FWDI_MULTB_L[ 71 : 0 ]. Thus, the B operand is generated from a combination of inputs from one or more of the routing fabric  105 , the routing fabric  110 , the LRAM  125 , the BRAM  120 , and the operand cascade input  145 . 
     The low bits for the A operand are selected by the multiplexer  410 C from four options: MLP_DIN[ 71 : 0 ]; REGFILE_DOUT[ 71 : 0 ]; BRAM_DOUT[ 71 : 0 ]; and FWDI_MULTA_L[ 71 : 0 ], 72 bits of data received from the operand cascade input  145 . The high bits for the A operand are selected by the multiplexer  410 D from eight options: BRAM_DIN[ 71 : 0 ]; MLP_DIN[ 71 : 0 ]; REGFILE_DOUT[ 143 : 72 ]; REGFILE_DOUT[ 71 : 0 ]; FWDI_MULTA_L[ 71 : 0 ]; BRAM_DOUT[ 143 : 72 ]; BRAM_DOUT[ 71 : 0 ]; and FWDI_MULTA_H[ 71 : 0 ], 72 bits of data received from the operand cascade input  145 . Thus, the A operand is also generated from a combination of inputs from one or more of the routing fabric  105 , the routing fabric  110 , the LRAM  125 , the BRAM  120 , and the operand cascade input  145 . 
     The inputs selected by the multiplexers  410 A- 410 D are optionally stored in the corresponding one of the registers  420 A- 420 D, which provide data to the operand cascade output  160  in the form of FWDO_MULTB_L[ 71 : 0 ], the low bits of the B operand; FWDO_MULTIB_H[ 71 : 0 ], the high bits of the B operand; FWDO_MULTA_L[ 71 : 0 ], the low bits of the A operand; and FWDO_MULTA_H[ 71 : 0 ], the high bits of the A operand. Additionally, each of the registers  420 A- 420 D is accessed by the corresponding one of the bit remap logics  430 A- 430 D. Each of the bit remap logics  430 A- 430 D remaps the inputs based on a multiplication mode and byte selection mode input. Exponent and sign bits are output from the bit remap logics  430 A- 430 D as signals &lt;EXPA&gt;, &lt;SGNA&gt;, &lt;EXPB&gt;, &lt;SGNB&gt;, &lt;EXPC&gt;, &lt;SGNC&gt;, &lt;EXPD&gt;, and &lt;SGND&gt;. The remapped inputs are provided to the stage 1 delay registers  440 , for access by the next portion of the arithmetic circuit. 
     In a floating-point mode that differs from the floating-point format used by the portion  500 , the bit remap logics  430 A- 430 D convert the inputs to a format expected by the portion  500 . In an example, the portion  500  expects floating-point values with a 15-bit mantissa, a one-bit sign, and an 8-bit exponent. In this example, the multiple mode arithmetic circuit supports inputs and outputs using various combinations of 16-bit mantissas, 10-bit mantissas, 12-bit mantissas, 8-bit exponents, 6-bit exponents, and 5-bit exponents. Based on the input format and the format expected by the portion  500 , the bit remap logics  430 A- 430 D convert the input values. In this example, selection of the input floating-point format is in response to a mode selection input. 
     The bit remap logics  430 A- 430 D, in some example embodiments, perform sign extension. As a result, operands that are smaller than the size of the input values accepted by the arithmetic blocks (e.g., the multipliers  520 A- 520 H) are routed using only the routing resources necessary for the operands and sign-extended by the bit remap logics  430 A- 430 D prior to use by the arithmetic blocks. By comparison with designs that perform sign extension prior to routing, this design saves routing resources. 
     The integer arithmetic logic blocks may be used to perform floating-point operations on the mantissas of floating-point operands by identifying the highest exponent among the exponents of the floating-point operands and right-shifting the mantissas of the other operands by the difference in exponents. For example, consider the table below, showing four operands. 
     
       
         
           
               
               
               
               
               
             
               
                   
                   
               
               
                   
                 Original 
                 Original 
                 Adjusted 
                 Adjusted 
               
               
                   
                 Mantissa 
                 Exponent 
                 Mantissa 
                 Exponent 
               
               
                   
                   
               
             
            
               
                   
                 10101010 
                 0001 
                 11110101 
                 0100 
               
               
                   
                 11110000 
                 0010 
                 11111100 
                 0100 
               
               
                   
                 00110011 
                 0011 
                 00011001 
                 0100 
               
               
                   
                 00001111 
                 0100 
                 00001111 
                 0100 
               
               
                   
                   
               
            
           
         
       
     
     After the adjustment, the mantissas of the operands can be manipulated as integers, since all exponents are equal. This floating-point mode is referred to as block floating-point since in all of the numbers being operated on are grouped together (in a “block”) with a common exponent value. 
     In the example above, note that the first two operands have their mantissas padded with 1s and the last two operands have their mantissas padded with 0s. This is consistent with 2&#39;s complement representation of negative numbers. In an unsigned mode or a signed/magnitude mode, the manipulation of the mantissa changes accordingly either by padding with 0s (for unsigned) or inserting 0s without modifying the sign bit (sign/magnitude). 
       FIG.  5    is a diagrammatic view of a portion  500  of a multiple mode arithmetic circuit, according to some example embodiments. The portion  500  comprises registers  510 A,  510 B,  510 C,  510 D,  510 E,  510 F,  510 G,  510 H,  510 I,  510 J,  510 K,  510 L,  510 M,  510 N,  510 O, and  510 P; multipliers  520 A,  520 B,  520 C,  520 D,  520 E,  520 F,  520 G, and  520 H; adders  530 A,  530 B,  530 C,  530 D,  550 A,  550 B, and  560 ; multiplexers  540 A,  540 B,  540 C,  540 D, and  570 ; and stage 2 delay registers  580 . 
     Each of the registers  510 A- 510 P stores eight bits of data for an operand for one of the multipliers  520 A- 520 H. Each of the multipliers  520 A- 520 H accepts eight bits of the A operand and eight bits of the B operand. Thus, the portion  500 , in total, handles 64 bits of the A operand and 64 bits of the B operand. To handle the complete input received by the portion  400 , the portion  500  is duplicated, with each instance of the portion  500  handling half of the inputs. 
     In a first operation mode, the portion  500  is configured to determine a sum of eight 8-bit multiply operations. By sign-extending or padding with leading zeros, as appropriate, the sum of fewer multiply operations or the sum of eight smaller (e.g., 6-bit or 4-bit) operations may be determined in the first operation mode. In a first variation of the first operation mode, each of the multipliers  520 A- 520 H is an eight-bit multiplier that is configured to output the sum of two four-bit multiplies. In a second variation of the first operation mode, each of the multipliers  520 A- 520 H is an eight-bit multiplier that is configured to output the result of two four-bit multiplies. In a second operation mode, the portion  500  is configured to output a sum of two 16-bit multiply operations. By sign-extending or padding with leading zeros, as appropriate, a single multiply operation or the sum of two smaller (e.g., 12-bit or 10-bit) operations may be determined in the second operation mode. In a third operation mode, the portion  500  in combination with the second instance of the portion  500  is configured, using an additional shifter and a wider adder, to determine a single 32-bit multiply operation. By sign-extending or padding with leading zeros, as appropriate, a smaller multiply operation (e.g., 18-bit or 24-bit) may be determined in the third operation mode. In additional operation modes, one or more individual multiply results may be provided at the output, in addition to or instead of the sum of the multiply operations. 
     With respect to the first operation mode, each of the eight multipliers  520 A- 520 H performs an eight-bit multiplication using a different portion of the operands A and B as inputs. The results of the eight multiplications are pairwise summed by the adders  530 A- 530 D. The four addition results are pairwise summed by the adders  550 A- 550 B, using the multiplexers  540 A- 540 D (controlled by a MODESEL signal) to determine whether to take the additional result directly or shifted as shown. The shifted results are used to support 16-bit multiplication. The two results of the adders  550 A- 550 B are summed by the adder  560 . The result of the adder  560  is the sum of the eight eight-bit multiplications, and is provided, via the mux  570 , to the stage 2 delay registers  580 . 
     With respect to the second operation mode, the multipliers  520 A- 520 D together, in combination with the adders  530 A,  530 B, and  550 A, determine a first 16-bit multiplication result. The multipliers  520 E- 520 H, in combination with the adders  530 C,  530 D, and  550 B, determine a second 16-bit multiplication result. Four multipliers of a first operand size can be used to generate multiplication results of a second operand size that is twice the first operand size. The larger operands are divided into two portions, high and low, and organized as follows, wherein AH represents the high portion of the A operand, AL represents the low portion of the A operand, BH represents the high portion of the B operand, and BL represents the low portion of the B operand. AH AL×BH BL=AL×BL+AH×BL&lt;&lt;SIZE+BH×AL&lt;&lt;SIZE+AH×BH&lt;&lt;2×SIZE. Since doubling the size of the operand uses four multipliers of the original size to perform one multiplication at the larger size, the number of operations performed by the arithmetic circuit is reduced (in this case by a factor of four) when the size of the operands is increased (in this case by a factor of two). Each of the four component multiplication results is a partial product. The partial product results are summed to generate the final multiplication result. The particular value of “SIZE” is implementation-dependent. 8 bits is used by way of example herein. Additionally, the process of combining four multipliers to operate as a larger multiplier may be repeated, so that four larger multipliers (16 original multipliers) are used to form an even larger multiplier. Thus, in an example embodiment, the MLP  115  provides 64 4-bit multipliers, 16 8-bit multipliers, 4 16-bit multipliers, or one 32-bit multiplier. 
     Thus, in the second operation mode, the multiplier  520 D multiplies BL with AH and the multiplier  520 C multiplies BH with AL. The results are added by the adder  530 B and the result from the adder  530 B is shifted left eight bits. The multiplier  520 B multiplies BH with AH and the result is shifted left sixteen bits. The multiplier  520 A multiples BL with AL. Following the results through the adders  530 A and  550 A, the output of the adder  550 A is the result of the 16-bit multiply operation. The multipliers  520 E- 520 H and adders  530 C,  530 D, and  550 B are similarly configured to process a second 16-bit multiply operation. The results of the two operations are summed by the adder  560  and provided to the stage 2 delay registers  580  via the multiplexer  570 . The size of the output of the adder  560  is one bit larger than size of the outputs of the adders  550 A and  550 B. Thus, in an eight-bit mode of operation, the adder  560  provides a 19-bit output and in a sixteen-bit mode of operation, the adder  560  provides a 34-bit output. 
     In some example embodiments, the portion  500  performs only a single 16-bit multiply in the second operation mode. In these embodiments, the results generated by the multipliers  520 E- 520 H and the adders  530 C,  530 D,  550 B, and  560  are ignored. Instead, the multiplexer  570  is configured to provide the output from the adder  550 A, containing the single 16-bit multiply result, to the stage 2 delay registers  580 . 
     In the third operation mode, the four 16-bit multiply operations provided by two instances of the portion  500  are combined in a manner analogous to that described with respect to the second operation mode, using an additional shifter and a wider adder, resulting in a circuit that determines a single 32-bit multiplication, making use of the adder  630  discussed below with respect to  FIG.  6   . 
     Though the portion  500  is described as performing multiplication operations on the selected inputs and then summing the result of the multiplication operations, other configurations of the arithmetic circuit are contemplated. For example, the inputs from the registers  510 A- 510 P may be provided to the multipliers  520 A- 520 H as shown and also be provided to a set of adders. Using a multiplexer for each multiplier/adder pair, the input to the adders  530 A- 530 D is selected either as the multiplication result or the addition result. Thus, based on a configuration signal controlling the multiplexers, the arithmetic circuit either determines a sum of the input operands or the sum of products of the input operands (as shown in  FIG.  5   ). 
     As mentioned previously, to handle the complete input received by the portion  400 , the portion  500  is duplicated, with each instance of the portion  500  handling half of the inputs. The portion  500  and its duplicate may be configured independently. Thus, different portions of the multiple mode arithmetic logic circuit may be configured to simultaneously perform integer and floating-point operations. 
       FIG.  6    is a diagrammatic view of a portion  600  of a multiple mode arithmetic circuit, according to some example embodiments. The portion  600  comprises the multiplexer  570  of  FIG.  5    and the corresponding multiplexer  610  from a duplicate of the portion  500  that handles the high half of the inputs A and B. The outputs of the multiplexers  570  and  610  are provided to the stage 2 delay registers  620 A and  620 B, each 34 bits wide. Inputs to the portion  600  are also received from the stage 1 delay registers  630 A,  630 B,  630 C,  630 D,  630 E,  630 F,  630 G, and  630 H, storing the &lt;SGNA&gt;, &lt;SGNB&gt;, &lt;SGNC&gt;, &lt;SGND&gt;, &lt;EXPA&gt;, &lt;EXPB&gt;, &lt;EXPC&gt;, and &lt;EXPD&gt; values generated by the bit remap logics  430 A- 430 D of  FIG.  4   . The portion  600  further includes an adder  650 ; multiplexers  640 A,  640 B,  640 C,  640 D,  640 E,  640 F,  640 G,  640 H,  660 ,  680 A, and  680 B; multipliers  670 A and  670 B; and stage 3 delay registers  690 . 
     The results from the portion  500  and its duplicate are added by the adder  650 . The multiplexer  660  selects either the results from the portion  500  or the summed results from both portions, based on a value of an ADD0_15_BYPASS signal, and provides the selected result to the multiplier  670 A and the multiplexer  680 A. Based on the &lt;EXPA&gt;, &lt;EXPB&gt;, &lt;SGNA&gt;, and &lt;SGNB&gt; values received via the multiplexers  640 A- 640 D and the value received from the multiplexer  660 , the multiplier  670 A generates a 24-bit floating-point multiplication result. Similarly, based on the &lt;EXPC&gt;, &lt;EXPD&gt;, &lt;SGNC&gt;, and &lt;SGND&gt; values received via the multiplexers  640 E- 640 H and the result received from the register  620 B, the multiplier  670 B generates a second 24-bit floating-point multiplication result. Based on an FPMULT_AB signal, the multiplexers  680 A- 680 B output either the 24-bit floating-point results generated by the multipliers  670 A- 670 B or pass through the results provided by the register  620 B and the multiplexer  660 . The outputs of the multiplexers  680 A- 680 B are provided to the stage 3 delay registers  690 . 
     Thus, in one operation mode, the outputs of the multiplexers  680 A- 680 B of the portion  600  are the outputs of the portion  500  and its duplicate portion, bypassing the adder  650  and the multipliers  670 A- 670 B. In a second operation mode, the output of the multiplexer  680 A is the sum of all multiplies performed by the portion  500  and its duplicate and the output of the multiplexer  680 B is the sum of the multiplies performed by the duplicate of the portion  500 . In a third operation mode, the output of the multiplexers  680 A- 680 B are 24-bit floating-point versions of the outputs of the portion  500  and its duplicate portion. In a fourth operation mode, the output of the multiplexer  680 A is a 24-bit floating-point representation of the sum of all multiplies performed by the portion  500  and its duplicate and the output of the multiplexer  680 B is a 24-bit floating-point representation of the sum of the multiplies performed by the duplicate of the portion  500 . 
       FIG.  7    is a diagrammatic view of a portion  700  of a multiple mode arithmetic circuit, according to some example embodiments. The portion  700  includes the multiplexer  680 A of  FIG.  6   ; stage 1 delay registers  710 A,  710 B,  710 C, and  710 D; multiplexers  720 A,  720 B,  720 C,  720 D,  740 A,  740 B,  750 A,  750 B,  770 , and  780 ; stage 3 delay registers  730 A and  730 B; adders  760 A and  760 B; stage 4 delay register  790 . Connections between the portion  700  and upper block  795  are also shown in  FIG.  7   . The upper block  795  refers to the portion of the arithmetic circuit shown in  FIG.  8   . 
     The output of the multiplexer  680 A is stored in the stage 3 delay register  730 A. The stage 3 delay register  730 B stores either the output of the multiplexer  660 B of  FIG.  6    or an addition result generated by adding the output of the multiplexer  660 B to FWDI_DOUT[ 47 : 0 ], as described below with respect to  FIG.  8   . 
     The multiplexer  750 A selects a value from FWDI_DOUT[ 47 : 0 ], REGFILE_DOUT[ 47 : 0 ], 48 bits from the LRAM  125 ; REGFILE_DOUT[ 95 : 48 ], a different 48 bits from the LRAM  125 ; delay register  730 B; and {24′H0, FWDI_DOUT[ 47 : 24 ]}, 24 0 bits prepended to 24 bits of the operand cascade input. The multiplexer  750 B selects a value from the stage 3 delay registers  730 A and  730 B. The outputs of the multiplexers  750 A and  750 B are provided to the adder  760 A and the adder  760 B. Based on the SUB_AB_DEL and LOAD_AB_DEL signals received from the multiplexers  740 A and  740 B and the selected values received from the multiplexers  750 A and  750 B, the adder  760 A generates an addition result. Based on the SUB_AB_DEL and LOAD_AB_DEL signals received from the multiplexers  740 A and  740 B and the selected values received from the multiplexers  750 A and  750 B, the adder  760 B generates an addition result or a subtraction result. The SUB signals control whether the adders  760 A and  760 B generate addition or subtraction results. The LOAD signals control whether the adders  760 A- 760 B add the input value to the accumulated value or ignore the accumulated value and merely load the input value, providing the input value as the output and setting the accumulator value to the input value. The DEL signals have a delay of 0-4 cycles. 
     The bypass multiplexer selects either the result generated by the adder  760 B or the result of the multiplexer  750 B. Thus, bypass multiplexer  770  provides either an addition result from the portion  700  or either result from  FIG.  6   . The multiplexer  780  selects either the output of the multiplexer  770  or the output of the adder  760 A and provides the result to the stage 4 delay register  790 . 
       FIG.  8    is a diagrammatic view of a portion  800  of a multiple mode arithmetic circuit, according to some example embodiments. The portion  800  corresponds to the upper block  795  shown in  FIG.  7   . The portion  800  includes the multiplexer  660 B of  FIG.  6   ; the multiplexers  720 C and  720 D of  FIG.  7   ; adders  840 A and  840 B; the stage 4 delay register  790 ; multiplexers  830 A,  830 B,  860 A,  860 B,  860 C,  860 D, and  880 ; logic blocks  850 A and  850 B; and output register  870 . The portion  700  of  FIG.  7    is represented in  FIG.  8    as lower block  890 . 
     The multiplexer  830 A selects a value from FWDI_DOUT[ 47 : 0 ]; REGFILE_DOUT[ 71 : 0 ]; REGFILE_DOUT[ 47 : 24 ], 24 bits from the LRAM  125 ; and value from the output register  870 , received via a feedback path. The multiplexer  830 B selects either the value from the multiplexer  660 B or the value from the stage 4 delay register  790 . 
     The adder  840 A sums the outputs from the multiplexers  830 A and  830 B, as modified by the SUB_REG and LOAD_REG signals. The SUB signals control whether the adder  840 A generates addition or subtraction results. The LOAD signals control whether the adder  840 A adds the input value to the accumulated value or ignores the accumulated value and merely loads the input value, providing the input value as the output and setting the accumulator value to the input value. As SUB_REG and LOAD_REG are not DEL signals, there is no delay in handling the inputs. The adder  840 B adds the outputs from the multiplexers  830 A- 830 B or takes the difference, depending on the SUB_REG signal. The multiplexers  860 B and  860 C select either the outputs of the adders  840 A- 840 B or, based on an FPADD_CD_BYPASS signal, provide the output from the multiplexer  830 B. The multiplexer  860 D selects an output from the multiplexer  860 B, the multiplexer  860 C, a MULT8BYP input, and a MULT16BYP input. If a bypass signal is used, the MULT8BYP signal is selected when the circuit is configured to perform 8-bit operations, and the MULT16BYP signal is selected when the circuit is configured to perform 16-bit operations. 
     The output of the multiplexer  860 D is stored in the output register  870 . If the circuit is configured to perform a floating-point format conversion (e.g., from an internal 24-bit floating-point format to a 16-bit output floating-point format), the value in the output register  870  is processed by the logic block  850 B before being provided as an input to the multiplexer  860 A. Likewise, if the circuit is configured to perform the floating-point format conversion, the value in the stage 4 delay register  790  is processed by the logic block  850 A. The multiplexer  860 A selects an input from the processed and unprocessed values of the registers  790  and  870 . The output of the multiplexer  860 A is provided as FWDO_DOUT[ 47 : 0 ], a 48-bit operand cascade output. 
     In a floating-point mode that differs from the floating-point format used by the portions  500 - 700 , the logics  850 A- 850 B convert the intermediate outputs to a format expected by the FPGA. In an example, the portions  500 - 700  operates on floating-point values with 16-bit mantissas and 8-bit exponents. In this example, the multiple mode arithmetic circuit supports inputs and outputs using various combinations of 16-bit mantissas, 10-bit mantissas, 12-bit mantissas, 8-bit exponents, 6-bit exponents, and 5-bit exponents. Based on the output format and the format operated on the portions  500 - 700 , the logics  850 A- 850 B convert the output values. In some example embodiments, the internal floating-point format used by the portions  500 - 700  has a mantissa size at least as large as the mantissa size of the input/output floating-point format. 
     Integer accumulators can be used for floating-point operations in special cases. In embodiments with both integer and floating-point accumulators, the integer accumulator may be wider than the floating-point accumulator, allowing block floating-point operations to use the integer accumulator without loss of data when the floating-point exponents are close in value. 
     The multiplexer  880  selects, based on an OUTPUT_SEL signal, the output value for the circuit from the output of the multiplexer  860 A; LRAM_DOUT[ 71 : 0 ], a 72-bit value read from the LRAM  125 ; and BRAM_DOUT[ 143 : 72 . The selected output value is provided as DOUT[ 71 : 0 ], a 72-bit output provided to the routing fabric  105 . 
     By way of example and not limitation, the multiple mode arithmetic circuit of  FIGS.  5 - 8    provide a row multiplication result via the multiplexer  880 . In matrix multiplication, each number in a row of the first operand is multiplied by each number in a column of the second operand and the sum of the results is stored as an element in the result matrix. This process is repeated for each row of the first operand and each column of the second operand, but the individual multiplication results are discarded. By using a multiple mode arithmetic circuit, row multiplication operands can be performed on matrices using different number formats without relying on a general-purpose processor. 
       FIG.  9    is a table  900  showing operand types and inputs for four operands of a multiple mode arithmetic circuit, according to some example embodiments. The MODEA column indicates the five-bit mode input value for selection of the A operands for a multiple mode arithmetic circuit that performs operations on A operands and B operands. The OPERAND TYPES column indicates the type of operands used in the selected mode. The remaining four columns indicate the source of each eight-bit portion of the A operands. 
     Regarding the OPERAND TYPES of  FIGS.  9 - 16   , INT8 indicates that the operands are 8-bit integers; INT7 indicates that the operands are 7-bit integers; INT6 indicates that the operands are 6-bit integers; INT16 indicates that the operands are 16-bit integers; BFP8 indicates that the operands are 8-bit block floating-point numbers; BFP7 indicates that the operands are 7-bit block floating-point numbers; BFP6 indicates that the operands are 6-bit block floating-point numbers; BFP6_EXPB indicates that the operands are 6-bit block floating-point numbers with an exponent stored in a register; BFLOAT16 indicates that the operands are 16-bit floating-point numbers in the bfloat format, with one sign bit, eight exponent bits, and seven fraction bits; FLOAT16 indicates that the operands are 16-bit floating-point numbers in the half-precision floating-point format, with one sign bit, five exponent bits, and ten fraction bits; and FLOAT24 indicates that the operands are 24-bit floating-point numbers with one sign bit, eight exponent bits, and fifteen fraction bits. 
     Regarding the REG columns of  FIGS.  9 - 16   , DIN indicates that the data is received via the stage 1 delay registers  440  of  FIG.  4   . Accordingly, DIN may reflect data received via the switch fabric of the FPGA, data received from intra-tile communications within the tile of the FPGA, data received from the operand cascade input, or any suitable combination thereof. The range within brackets after the name of a source or register indicates the range of bits. For example, DIN[ 7 : 0 ] refers to bits  0 - 7  from DIN. As another example, DIN[ 15 : 8 ] refers to bits  8 - 15  from DIN. In addition to inputs from DIN,  FIG.  9    (and  FIGS.  10 - 16   ) include explicit binary values, indicated as a number, a bit symbol, and a value for the number of bits. For example, 8′B0 refers to eight zero bits and 1′B1 refers to a single one bit. 8′B10000000 refers to the specific sequence of eight bits. An empty entry indicates that the eight bits of operand A for the column are not used in the mode of the row. 
       FIG.  10    is a table  1000  showing operand types and inputs for four operands of the multiple mode arithmetic circuit, according to some example embodiments. The MODEA and OPERAND TYPES columns correspond to the columns of the same names in  FIG.  9   . The remaining four columns indicate the source of four more eight-bit portion of the A operands, using the same notation described above with respect to  FIG.  9   . 
       FIG.  11    is a table  1100  showing operand types and inputs for four operands of the multiple mode arithmetic circuit, according to some example embodiments. The MODEA and OPERAND TYPES columns correspond to the columns of the same names in  FIGS.  9 - 10   . The remaining four columns indicate the source of four more eight-bit portion of the A operands, using the same notation described above with respect to  FIG.  9   . 
       FIG.  12    is a table  1200  showing operand types and inputs for four operands of the multiple mode arithmetic circuit, according to some example embodiments. The MODEA and OPERAND TYPES columns correspond to the columns of the same names in  FIGS.  9 - 11   . The remaining four columns indicate the source of four more eight-bit portion of the A operands, using the same notation described above with respect to  FIG.  9   . 
       FIG.  13    is a table  1300  showing operand types and inputs for four operands of the multiple mode arithmetic circuit, according to some example embodiments. The MODEB column indicates the five-bit mode input value for selection of the B operands for the multiple mode arithmetic circuit. The OPERAND TYPES column contains values with the same meaning as described above with respect to  FIG.  9   . Each column indicates the source of data used for four B operands. 
       FIG.  14    is a table  1400  showing operand types and inputs for four operands of the multiple mode arithmetic circuit, according to some example embodiments. The MODEB and OPERAND TYPES columns correspond to the columns of the same names in  FIG.  13   . The remaining four columns indicate the source of four more eight-bit portion of the B operands, using the same notation described above with respect to  FIG.  9   . 
       FIG.  15    is a table  1500  showing operand types and inputs for four operands of the multiple mode arithmetic circuit, according to some example embodiments. The MODEB and OPERAND TYPES columns correspond to the columns of the same names in  FIGS.  13 - 14   . The remaining four columns indicate the source of four more eight-bit portion of the B operands, using the same notation described above with respect to  FIG.  9   . 
       FIG.  16    is a table  1600  showing operand types and inputs for four operands of the multiple mode arithmetic circuit, according to some example embodiments. The MODEB and OPERAND TYPES columns correspond to the columns of the same names in  FIGS.  13 - 15   . The remaining four columns indicate the source of four more eight-bit portion of the B operands, using the same notation described above with respect to  FIG.  9   . 
       FIG.  17    is a flowchart illustrating operations of a method  1700  performed by a multiple mode arithmetic circuit, according to various embodiments of the invention. The method  1700  includes operations  1710 ,  1720 , and  1730 . By way of example and not limitation, the method  1700  is described as being performed by the circuits of  FIGS.  1 - 8   . 
     In operation  1710 , the multiple mode arithmetic circuit receives a mode selection inputs that selects a mode from a set of modes comprising a first mode and a second mode. As an example, the MODESEL signal shown in  FIG.  5    is received. Depending on the value of the mode selection signal, either operation  1720  or operation  1730  is performed. 
     In response to the mode selection input selecting the first mode, the multiple mode arithmetic circuit, in operation  1720 , configures a plurality of integer arithmetic logic blocks to perform operations on integer operands. For example, a MODEA signal and a MODEB signal may be received, causing configuration of the arithmetic circuit in accordance with the tables of  FIGS.  9 - 16    in operation  1720 . Thus, in this example embodiment, the first mode is an integer mode. 
     In response to the mode selection input selecting the second mode, the multiple mode arithmetic circuit configures the plurality of integer arithmetic logic blocks to perform operations on floating-point operands, in operation  1730 . For example, a second MODEA signal and a second MODEB signal may be received, causing configuration of the arithmetic circuit in accordance with the tables of  FIGS.  9 - 16    in operation  1720 . 
     Thus, by virtue of the method  1700 , the same set of integer arithmetic logic blocks are used to perform either integer or floating-point operations. As a result, the multiple mode arithmetic circuit can be used in systems performing integer operations, floating-point operations, or both, resulting in increased versatility by comparison to existing FPGA tiles that perform arithmetic operations in a single mode while retaining the advantages of arithmetic FPGA tiles over general-purpose processors. 
     In some example embodiments, other components of the circuit are used in both modes. In the example embodiment of  FIG.  4   , the bit remap logics  430 A- 430 D remap the inputs for use in both the first mode and the second mode. In the example embodiment of  FIG.  5   , the registers  510 A- 510 P are used to store input values to the multipliers  520 A- 520 H and the multiplexers  540 A- 540 D select input values to the adders  550 A- 550 B in both the first mode and the second mode. 
     Additional modes may also be supported. For example, the second mode may be a floating-point mode that operates on floating-point numbers with arbitrary exponent values and a third mode may be a block floating-point mode that operates on floating-point numbers with exponents that differ by no more than a predetermined threshold (e.g., 4). 
       FIG.  18    is a high-level diagrammatic view of a multiple mode arithmetic circuit  1800 , according to some example embodiments. In some example embodiments, the arithmetic circuit  1800  is the MLP  115 . The arithmetic circuit  1800  receives intra-tile inputs from the memory portion of the FPGA tile, routing fabric inputs from a routing fabric of the FPGA, control signals from the routing fabric of the FPGA, and operand cascade inputs from another FPGA tile without making use of the routing fabric. In various example embodiments, more or fewer inputs are present. 
     The inputs comprise two complex numbers, A+jB and C+jD. The output is a complex number, wherein the real component is AC−BD and the imaginary component is AD+BC. This functionality is implemented using the circuits of  FIGS.  4 - 8   , with the inputs being selected from any combination of routing fabric inputs, intra-tile inputs, and operand cascade inputs and the outputs being provided to any combination of routing fabric outputs, intra-tile outputs, and operand cascade outputs. 
     As discussed with respect to  FIG.  5   , four multipliers may be used to provide a single multiplier handling operands of twice the width. Thus, four 8-bit multipliers may be used to provide a single 16-bit multiplier, four 4-bit multipliers may be used to provide a single 8-bit multiplier, and four 16-bit multipliers may be used to provide a single 32-bit multiplier. Since the disclosed circuits provide this quadruple multiplier functionality, the structure of  FIG.  18    makes use of the four multipliers to provide complex multiplication functionality at the original width without requiring additional hardware. Thus, the same circuit may implement either 32-bit multiplication or 16-bit complex multiplication; 16-bit multiplication or 8-bit complex multiplication; 8-bit multiplication or 4-bit complex multiplication; and so on. 
       FIG.  19    is a diagrammatic view of a reduced-delay circuit  1900  for converting a fixed point value to a block floating point value, according to some example embodiments. The reduced-delay circuit  1900  includes multiplexers  1905  and  1945 ; OR gates  1910  and  1950 ; adders  1915  and  1925 ; a leading zero detector (LZD)  1920 ; subtractors  1930  and  1935 ; a shifter  1940 ; and a rounder  1955 . Data flows from the top of the circuit  1900  to the bottom. Thus, multiple operations are performed in parallel, reducing delay when compared with prior art circuits that generate the result using sequential operations. 
     The inputs to the circuit  1900  are the exponents of the two floating-point numbers being multiplied, EXP_A and EXP_B, and the N-bit result of the multiplication of the mantissas of the two floating point numbers, [N- 1 : 0 ]. The adder  1925  determines the sum of EXP_A, EXP_B, and CONST, wherein CONST is defined by:
 
CONST= N− 2 −d− 2×bias in +bias out +1.
 
     In this equation, N is the number of bits of the multiplication result, d is the number of fraction bits in the output floating-point value, bias in  is the input bias on the exponent, and bias out  is the output bias on the exponent. In some example embodiments, bias in  is 15 or 127 and bias out  is 127. The first five terms define the ordinary value of CONST. The final +1 is used in conjunction with the subtractors  1930  and  1935  to provide two parallel calculations of the exponent. 
     The multiplexer  1905  inverts the low N-1 bits of the multiplication result if the highest bit (represented as BFP_SIGN) is 1, indicating that the result is a negative number. Otherwise, the sign bit is removed and the low N-1 bits are output from the multiplexer  1905 . This effectively converts the input two&#39;s complement value to a signed-magnitude format. 
     The least significant bit (N[ 0 : 0 ]) and BFP_SIGN are input to the OR gate  1910 . The output replaces the least significant bit from the multiplexer  1905  and the resulting value is input to the LZD  1920 . The LZD  1920  determines the number of leading zeros in the input, and outputs that value as Z′. 
     The output from the multiplexer  1905  is added, by the adder  1915 , to BFP_SIGN. The addition result from the adder  1915  is shifted left Z′ bits by the shifter  1940 . The most significant bit (MSB) of the result will be 1 if Z′ was an accurate count of the number of leading zeros. If Z′ was an accurate count of the leading zeros, the shifted result will be normalized by having the MSB equal to 1. The shifted result is provided to the rounder  1955 , which rounds the result from N-1 bits to P-1 bits, where P is the size of the output mantissa+sign. If the rounding operation had an overflow because the number of significant bits exceeded P-1, RND_OVERFLOW is set. 
     The subtractors  1930  and  1935  each subtract Z′ from the result of the adder  1925 . The subtractor  1935  also applies a carry input (CIN) value, set to −1. Thus, two possible exponents are calculated in parallel by the subtractors  1930  and  1935 . 
     The OR gate  1950  controls the multiplexer  1945  and determines whether the exponent should be the output of the subtractor  1930  or the output of the subtractor  1935 . If Z′ was incorrect, as indicated by the MSB value output from the shifter  1940  being a zero, the exponent should be the output of the subtractor  1935 , adjusted by an additional −1, instead of the output of the subtractor  1930 , determined by using Z′ as the count of leading zeros. Furthermore, if RND_OVERFLOW was set, the exponent should be reduced by one to compensate. 
     The output from the circuit  1900  is a sign, exponent, and mantissa of the result of the multiplication of the two input floating-point numbers. The output sign is BFP_SIGN; the output exponent is the output of the multiplexer  1945 ; and the output mantissa is the output of the rounder  1955 . By using the circuit  1900  to determine both possible exponents in parallel instead of performing other operations first to ensure that the leading zero count is accurate, the delay is reduced. Though the circuit  1900  is shown as operating on block floating-point values, the LZD  1920 , shifter  1940 , and paired subtractors  1930  and  1935  would also form the core of a similar circuit to operate on standard floating-point values. 
     The circuit  1900  may be implemented as a circuit portion of the multiple mode arithmetic circuit  115 , to convert an output from the plurality of integer logic blocks to a floating-point number. The conversion comprises determining, by the parallel subtractors  1930  and  1935 , two possible exponent values of the floating-point number; determining, by the LZD  1920 , an estimated count of leading zeroes in the output; and selecting, by the multiplexer  1945  between the two possible exponent values based on a determination of whether the estimated count of leading zeroes was correct (by the shifter  1940  and multiplexer  1950 ). 
       FIG.  20    is a block diagram illustrating components of a computer  2000  that programs an FPGA, according to some example embodiments. All components need not be used in various embodiments. For example, clients, servers, autonomous systems, and cloud-based network resources may each use a different set of components, or, in the case of servers, for example, larger storage devices. 
     One example computing device in the form of a computer  2000  (also referred to as computing device  2000  and computer system  2000 ) may include a processor  2005 , memory storage  2010 , removable storage  2015 , and non-removable storage  2020 , all connected by a bus  2040 . Although the example computing device is illustrated and described as the computer  2000 , the computing device may be in different forms in different embodiments. For example, the computing device may instead be a smartphone, a tablet, a smartwatch, or another computing device including elements the same as or similar to those illustrated and described with regard to  FIG.  20   . Devices such as smartphones, tablets, and smartwatches are collectively referred to as “mobile devices.” Further, although the various data. storage elements are illustrated as part of the computer  2000 , the storage may also or alternatively include cloud-based storage accessible via a network, such as the Internet, or server-based storage. 
     The memory storage  2010  may include volatile memory  2045  and non-volatile memory  2050  and may store a program  2055 . The computer  2000  may include, or have access to, a computing environment that includes a variety of computer-readable media, such as the volatile memory  2045 ; the non-volatile memory  2050 ; the removable storage  2015 ; and the non-removable storage  2020 . Computer storage includes random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EPROM), flash memory or other memory technologies, compact disc read-only memory (CD ROM), digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium capable of storing computer-readable instructions. 
     The computer  2000  may include or have access to a computing environment that includes an input interface  2025 , an output interface  2030 , and a communication interface  2035 . The output interface  2030  may interface to or include a display device, such as a touchscreen, that also may serve as an input device. The input interface  2025  may interface to or include one or more of a touchscreen, a touchpad, a mouse, a keyboard, a camera, one or more device-specific buttons, one or more sensors integrated within or coupled via wired or wireless data connections to the computer  2000 , and other input devices. The computer  2000  may operate in a networked environment using the communication interface  2035  to connect to one or more remote computers, such as database servers. The remote computer may include a personal computer (PC), server, router, network PC, peer device or other common network node, or the like. The communication interface  2035  may connect to a local-area network (LAN), a wide-area network (WAN), a cellular network, a WiFi network, a Bluetooth network, or other networks. 
     Computer instructions stored on a computer-readable medium (e.g., the program  2055  stored in the memory storage  2010 ) are executable by the processor  2005  of the computer  2000 . A hard drive, CD-ROM, and RAM are some examples of articles including a non-transitory computer-readable medium such as a storage device. The terms “computer-readable medium” and “storage device” do not include carrier waves to the extent that carrier waves are deemed too transitory. “Computer-readable non-transitory media” includes all types of computer-readable media, including magnetic storage media, optical storage media, flash media, and solid-state storage media. It should be understood that software can be installed in and sold with a computer. Alternatively, the software can be obtained and loaded into the computer, including obtaining the software through a physical medium or distribution system, including, for example, from a server owned by the software creator or from a server not owned but used by the software creator. The software can be stored on a server for distribution over the Internet, for example. 
     The program  2055  is shown as including a design module  2060  and a place and route module  2065 . Any one or more of the modules described herein may be implemented using hardware (e.g., a processor of a machine, an ASIC, an FPGA, or any suitable combination thereof). Moreover, any two or more of these modules may be combined into a single module, and the functions described herein for a single module may be subdivided among multiple modules. Furthermore, according to various example embodiments, modules described herein as being implemented within a single machine, database, or device may be distributed across multiple machines, databases, or devices. 
     The design module  2060  defines a design of a circuit (e.g., a processor, signal processor, compute engine, state machine, or controller circuit). For example, the design module  2060  may provide a user interface to allow a user to design a circuit. 
     The place and route module  2065  determines the physical layout of the resulting integrated circuit based on the circuit design defined by the design module  2060 . For example, a design comprising one or more tiles with fused memory and arithmetic circuits may be laid out by the place and route module  2065  in order to be programmed into the FPGA configuration. 
     The Abstract of the Disclosure is provided to comply with 37 C.F.R. § 1.72(b), requiring an abstract that allows the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the claims. In addition, in the foregoing Detailed Description, it may be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as limiting the claims. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.