Patent Publication Number: US-10768601-B2

Title: Programmable controller

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is based upon and claims the benefit of priority to Japanese Patent Application No. PCT/JP2012/080099, filed Nov. 20, 2012, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a programmable controller. 
     Description of Background Art 
     A programmable controller of a multi-CPU configuration may include multiple CPU modules (for example, see Japanese Patent Laid-Open Publication No. 2011-123688). In Japanese Patent Laid-Open Publication No. 2011-123688, a system processor has a code switch for identifying each of the CPU modules. The entire contents of this publication are incorporated herein by reference. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, a programmable controller includes multiple interface circuitry modules, and multiple CPU modules. An interface circuitry module of the interface circuitry modules transmits a potential signal having an electric potential state of different electric potential states to a CPU module of the CPU modules, the CPU module is connectable to a second CPU module of the CPU modules and includes a CPU which performs arithmetic processing and a memory that stores discrimination information and definition information, the discrimination information including binarized information indicating whether the CPU in the CPU module is a main CPU or a sub CPU, the first discrimination information being set based on the electric potential state of the potential signal that is input into the CPU module from the interface circuitry module to which the CPU module is connected, and the definition information including setting information indicating whether the CPU in the CPU module is set in advance as the main CPU or the sub CPU. 
     According to another aspect of the present invention, a method for controlling a servo motor includes executing arithmetic processing via multiple CPU modules connected to multiple interface circuitry modules, generating a control command based on the arithmetic processing, and transmitting the control command to a servo control device that executes operation and control of a servo motor. An interface circuitry module of the interface circuitry modules transmits a potential signal having an electric potential state of different electric potential states to a CPU module of the CPU modules, the CPU module is connectable to a second CPU module of the CPU modules and includes a CPU which performs arithmetic processing and a memory that stores discrimination information and definition information, the discrimination information includes binarized information indicating whether the CPU in the CPU module is a main CPU or a sub CPU, the first discrimination information is set based on the electric potential state of the potential signal that is input into the CPU module from the interface circuitry module to which the CPU module is connected, and the definition information includes setting information indicating whether the CPU in the CPU module is set in advance as the main CPU or the sub CPU. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIG. 1  illustrates a state in which a programmable controller (PLC) according to a first embodiment of the present invention is used; 
         FIG. 2  is a block diagram illustrating a schematic configuration of the PLC illustrated in  FIG. 1 ; 
         FIG. 3  is a block diagram illustrating a schematic configuration of a CPU module that is connected to an IF unit in a CPU rack; 
         FIG. 4  is a block diagram illustrating a schematic configuration of a CPU module that is connected to an IF unit in another CPU rack; 
         FIG. 5  is a flowchart that describes operation of the PLC when power is turned on; 
         FIG. 6  is a flowchart that describes operation of the PLC when program scan is performed; 
         FIG. 7  is a flowchart that describes data backup procedures of the PLC; 
         FIG. 8  is a flowchart that describes editing procedures of a control program using an engineering tool (program editing application); 
         FIG. 9  is a block diagram illustrating a schematic configuration of a PLC  2  according to a second embodiment; 
         FIG. 10  is a block diagram illustrating a schematic configuration of a CPU module that is connected to an IF unit in a CPU rack in the second embodiment; 
         FIG. 11  is a block diagram illustrating a schematic configuration of a PLC  2  according to a third embodiment; and 
         FIG. 12  is a block diagram illustrating a schematic configuration of a CPU module that is connected to an IF unit in a CPU rack in the third embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings. 
     First Embodiment 
     In the following, a first embodiment of the present invention is described using the drawings.  FIG. 1  illustrates a state in which a programmable controller (PLC)  2  according to the first embodiment of the present invention is used. The programmable controller  2  is used by being connected via a servo control device  3  to a servo motor  4  as a control object. Of course, the control object is not limited to the servo motor  4 . Various other types of motors and various actuators other than motors can be control objects. 
     The PLC  2  is structured to have multiple modules such as power source modules  10 , CPU (central processing unit) modules  5  and option modules  6 . Each of the CPU modules  5  has a memory. The memories each store a control program. When the control program is executed, based on arithmetic processing of the CPU module  5 , a control command is transmitted from the PLC  2  to the servo control device  3 . Based on the received control command, the servo control device  3  executes operation control and driving of the servo motor (control object)  4 . 
     The PLC  2  has a data communication port ( 2   a ) such as a USB port. By connecting an external storage device such as a USB memory to the data communication port ( 2   a ), data, setting information and the like in the PLC  2  can be backed up. Further, the PLC  2  has a data communication port ( 2   b ) such as an Ethernet port. By connecting the PLC  2  via the data communication port ( 2   b ) to a PC that has a program editing application such as an engineering tool, reading, editing and writing of a control program in the PLC  2  can be performed via the PC. The PLC  2  has an error display (error display means) (ER) that performs error display when content based on a discrimination bit (to be described later) and content based on definition information do not match. 
       FIG. 2  is a block diagram illustrating a schematic configuration of the PLC  2 . The PLC  2  has multiple CPU racks (R). The CPU racks (R) each have a power source module  10  and a CPU module  5 . Several types of modules are prepared as option modules  6 . Some of the CPU racks (R) may each have an option module  6 . For example, according to a control device, a module suitable for an application may be selected from a lineup of modules and used as an option module in the PLC  2 . The lineup of the modules includes communication modules (for RS-232C communication, Devicenet communication and the like), servo control modules, I/O modules, and the like. 
     In  FIG. 2 , a CPU rack (R 1 ) has a power source module  10 , two CPU modules ( 5   a ,  5   b ), and an option module  6 . A CPU rack (R 2 ) has a power source module  10 , one CPU module ( 5   c ), and an option module  6 . A CPU rack (R 3 ) has a power source module  10 , and one CPU module ( 5   d ). The CPU modules ( 5   a - 5   d ) have the same configuration. 
     The CPU racks (R 1 -R 3 ) respectively have inter-rack interface units (interface units; hereinafter, referred to as IF units) (F 1 -F 3 ). The IF units have functions to connect the CPU racks with each other via the IF units. In  FIG. 2 , the CPU rack (R 1 ) and the CPU rack (R 2 ) are connected via the IF unit (F 1 ) and the IF unit (F 2 ). The CPU rack (R 1 ) and the CPU rack (R 3 ) are connected via the IF unit (F 1 ) and the IF unit (F 3 ). 
     The IF unit (F 1 ) is connected via the power source module  10  to the CPU module ( 5   a ). The CPU module ( 5   b ) is connected to the CPU module ( 5   a ). The IF unit (F 2 ) is connected via the power source module  10  to the CPU module ( 5   c ). The IF unit (F 3 ) is connected via the power source module  10  to the CPU module ( 5   d ). The IF units (F 1 -F 3 ) each have a function to set a CPU module that is connected to the IF unit as a main CPU or a sub CPU depending on whether or not the IF unit has therein a slave rack extension module  11 . 
       FIG. 3  is a block diagram illustrating a schematic configuration of the CPU module ( 5   a ) that is connected to the IF unit (F 1 ) in the CPU rack (R 1 ).  FIG. 4  is a block diagram illustrating a schematic configuration of the CPU module ( 5   c ) that is connected to the IF unit (F 2 ) in the CPU rack (R 2 ). The CPU module  5  has a CPU (central processing unit)  13 , an FPGA  7  and a memory  8 . The CPU  13  is a processor that executes various applications. The FPGA  7  is an integrated circuit that incorporates a circuit that is specialized for a system, and has a function of executing processing such as generating a scan period based on execution of a control program (P). The control program (P) is stored in the memory  8 . The CPU  13  performs arithmetic processing by executing the control program (P), and operation of the servo motor  4  is controlled based on an arithmetic result of the arithmetic processing. 
     The IF unit (F 1 ) does not have a slave rack extension module  11 . Therefore, a potential state of the connection port ( 11   a ) that is connected to the CPU ( 5   a ) is OPEN. A potential level of the connection port ( 11   b ) that is connected to the connection port ( 11   a ) is the same as a potential level of the connection port ( 11   a ). Further, the potential level of the connection port ( 11   b ) and a potential level of the discrimination bit ( 12   a ) are the same level. Therefore, the potential level of the connection port ( 11   b ) and the potential level of the discrimination bit ( 12   a ) both are the same as the potential level of the connection port ( 11   a ) (hereinafter, this state is referred to as an OPEN state). The connection port ( 11   a ) of the IF unit (F 1 ) is connected via the power source module  10  to the connection port ( 11   b ) that is provided to a FPGA ( 7   a ) in the CPU module ( 5   a ). Consequently, a first potential signal (S 1 ) is input from the IF unit (F 1 ) to the CPU module ( 5   a ). When the potential state of the connection port ( 11   a ) is the OPEN state, a potential state of the first potential signal (S 1 ) that is input to the connection port ( 11   b ) is determined by the potential level of the discrimination bit ( 12   a ) and thus is Low Level. 
     The CPU module ( 5   a ) has the discrimination bit ( 12   a ) in the memory ( 8   a ). The discrimination bit ( 12   a ) has binarized information indicating whether a CPU ( 13   a ) in the CPU module ( 5   a ) of itself is a main CPU or a sub CPU. The information is based on the potential state of the first potential signal (S 1 ) that is input to the connection port ( 11   b ). For example, in the present first embodiment, when the potential state of the first potential signal (S 1 ) that is input to the connection port of the FPGA is Low, the discrimination bit is “0” and the CPU module is set as a main CPU. When the potential state of the first potential signal (S 1 ) that is input to the connection port of the FPGA is High, the discrimination bit is “1” and the CPU module is set as a sub CPU. 
     In the CPU module ( 5   a ), a potential state of an input potential to the connection port ( 11   b ) of the FPGA ( 7   a ) is Low Level. Therefore, the discrimination bit ( 12   a ) is “0” and the CPU ( 13   a ) in the CPU module ( 5   a ) is set as a main CPU. When the CPU ( 13   a ) is set as a main CPU, the setting information (the information that the CPU ( 13   a ) is a main CPU) is stored as definition information (Qa) in the memory ( 8   a ). When the control program (P) is executed, an operation clock signal of the CPU module ( 5   a ) as a main CPU becomes a reference clock signal of the program execution. Therefore, the clock signal of the CPU module ( 5   a ) is transmitted to other sub CPUs. The CPU modules ( 5   b - 5   d ) also each generate a clock signal. 
     The CPU module ( 5   a ) has an output port ( 11   c ). A potential state (predetermined potential state) of a second potential signal (S 2 ) that is output from the output port ( 11   c ) is Vcc. The CPU module ( 5   b ) has therein an FPGA ( 7   b ). The output port ( 11   c ) is connected to a connection port ( 11   d ) of the FPGA ( 7   b ). A potential state of the output port ( 11   c ) is Vcc Level. Therefore, the potential state of the second potential signal (S 2 ) that is input to the connection port ( 11   d ) is High Level. 
     The CPU module ( 5   b ) has a discrimination bit ( 12   b ) in a memory ( 8   b ). The discrimination bit ( 12   b ) has configuration and function that are the same as those of the discrimination bit ( 12   a ). In the CPU module ( 5   b ), the potential state of the second potential signal (S 2 ) that is input to the connection port ( 11   d ) of the FPGA ( 7   b ) is High Level. Therefore, the discrimination bit ( 12   a ) is “1” and a CPU ( 13   b ) in the CPU module ( 5   b ) is set as a sub CPU. When the CPU ( 13   b ) is set as a sub CPU, the setting information (the information that the CPU ( 13   b ) is a sub CPU) is stored as definition information (Qb) in the memory ( 8   b ). When the control program (P) is executed, an operation clock signal of the CPU module ( 5   a ) as a main CPU becomes a reference clock signal of the program execution. An operation clock signal of the CPU module ( 5   b ) as a sub CPU is synchronized with a clock signal received from the CPU module ( 5   a ) as a main CPU. 
     As described above, the IF unit (F 1 ) does not have the slave rack extension module  11 . Therefore, the CPU module ( 5   a ) that is connected to the IF unit (F 1 ) is set as a main CPU. The CPU module ( 5   b ) that is connected to the CPU module ( 5   a ) (in other words, a CPU module that is not directly connected to an IF unit but is connected to another CPU module) is set as a sub CPU. 
     When the input potential to the connection port of the FPGA is one of High Level and Low Level, to set the CPU of the CPU module as a main CPU or a sub CPU is a matter of freedom in design. Further, when the input potential to the connection port of the FPGA is one of High Level and Low Level, to set an information value of the discrimination bit to “0” or “1” is also a matter of freedom in design. 
     The IF unit (F 2 ) has therein the slave rack extension module  11 . Therefore, the potential state of the first potential signal (S 1 ) that is input to a connection port ( 11   e ) connected to the CPU ( 5   c ) is Vcc Level. The connection port ( 11   e ) of the slave rack extension module  11  is connected via the power source module  10  to a connection port ( 11   f ) that is provided to a FPGA ( 7   c ) in the CPU module ( 5   c ). When a potential of the connection port ( 11   e ) is Vcc Level, the potential state of the first potential signal (S 1 ) that is input to the connection port ( 11   f ) is High Level. 
     The CPU module ( 5   c ) has a discrimination bit ( 12   c ) in a memory ( 8   c ). The discrimination bit ( 12   c ) has configuration and function that are the same as those of the discrimination bit ( 12   a ). In the CPU module ( 5   c ), an input potential to the connection port ( 11   f ) of the FPGA ( 7   c ) is High Level. Therefore, the discrimination bit ( 12   c ) is “1” and a CPU ( 13   c ) in the CPU module ( 5   c ) is set as a sub CPU. When the CPU ( 13   c ) is set as a sub CPU, the setting information (the information that the CPU ( 13   c ) is a sub CPU) is stored as definition information (Qc) in the memory ( 8   c ). When the control program (P) is executed, an operation clock signal of the CPU module ( 5   a ) as a main CPU becomes a reference clock signal of the program execution. An operation clock signal of the CPU module ( 5   c ) as a sub CPU is synchronized with a clock signal received from the CPU module ( 5   a ) as a main CPU. 
     As described above, when the IF unit (F 2 ) has the slave rack extension module  11 , the CPU module ( 5   c ) that is connected to the IF unit (F 2 ) is set as a sub CPU. A CPU module connected to the CPU module ( 5   c ) is also set as a sub CPU. A connection state between the IF unit (F 3 ) and the CPU module ( 5   d ) and settings of the CPU module ( 5   d ) are the same as a connection state between the IF unit (F 2 ) and the CPU module ( 5   c ) and settings of the CPU module ( 5   c ), and thus a description thereof is omitted. That is, the IF unit (F 3 ) has the slave rack extension module  11 . Therefore, a discrimination bit ( 12   d ) is “1” and the CPU module ( 5   d ) is set as a sub CPU. The information that the CPU module ( 5   d ) is a sub CPU is stored as definition information (Qd) in a memory ( 8   d ) (illustration of the discrimination bit ( 12   d ), the definition information (Qd) and the memory ( 8   d ) in the drawings is omitted in the present first embodiment). 
     As described above, despite of being CPU modules of the same configuration, the CPU modules ( 5   a - 5   d ) can each be automatically set as a main CPU or a sub CPU depending on a connection state with an IF unit. Depending on which IF unit a CPU module is connected to, that is, depending on whether a CPU module is connected to an IF unit that has a slave rack extension module or an IF unit that does not have a slave rack extension module, the CPU module is automatically set as a main CPU or a sub CPU, and the setting content is stored as definition information in the CPU module. 
     The PLC  2  performs a hardware connection state detection operation and a definition information confirmation operation after power is turned on. In the hardware connection state detection operation, detection of connection states between the CPU racks (R 1 -R 3 ), detection of presence or absence of a slave rack extension module in each of the IF units, detection of connection states of the CPU modules, and the like, are performed. In the detection of the connection states of the CPU modules, detection is performed regarding which IF unit or which CPU module each of the CPU modules is connected to. By the hardware connection state detection operation, connection states between the IF units and the CPU modules are detected. Based on the connection situation in the PLC  2 , a CPU module to be set as a main CPU (this is referred to as a CPU module of which a connection state is “main”) and a CPU module to be set as a sub CPU (this is referred to as a CPU module of which a connection state is “sub”) are identified. 
     In the definition information confirmation operation, confirmation of the setting content of the definition information in each of the CPU modules is performed. That is, setting information is obtained regarding which CPU module is set in advance as a main CPU (this is referred to as a CPU module of which definition information is “main”) and which CPU module is set in advance as a sub CPU (this is referred to as CPU module of which definition information is “sub”). 
     When there is no contradiction between a CPU module of which the connection state is “main” and a CPU module of which the definition information is “main” and there is no contradiction between a CPU module of which the connection state is “sub” and a CPU module of which the definition information is “sub,” the PLC  2  is in a normally operable state. When the PLC  2  is in the normally operable state, a scan operation based on the execution of the control program (P), data backup processing via the data communication port ( 2   a ) that the PLC  2  has, reading, editing and writing of the control program using a program editing application, and the like, can be performed. 
     On the other hand, when there is a contradiction between the connection state and the definition information of a CPU module, the PLC  2  is not in the normally operable state. In this case, some functions such as the data backup processing via the data communication port ( 2   a ), the reading of the control program and a monitor of a register in the control program are effective, but some other functions such as the scan operation based on the execution of the control program (P) and the writing of the control program via the data communication port ( 2   a ) are ineffective. 
     Operation of the PLC  2  is described using flowcharts of  FIG. 5-8 .  FIG. 5  is a flowchart that describes the operation of the PLC  2  when power is turned on. When the power of the PLC  2  is turned on (S 1 ), the PLC  2  starts the hardware connection state detection operation (S 2 ). Next, the PLC  2  starts the definition information confirmation operation (S 3 ). By these operations, the connection states of the IF units (F 1 -F 3 ) and the CPU modules ( 5   a - 5   d ), presence or absences of the lave rack extension module  11 , and contents of the definition information (Qa-Qd) are confirmed. 
     When the definition information (Qa-Qd) is not stored in any of the memories ( 8   a - 8   d ) (S 4 ), that is, when none of the definition information (Qa-Qd) has any content, it is determined that all the CPU modules ( 5   a - 5   d ) are “unused.” In this case, new definition information (Qa-Qd) is created in the memories ( 8   a - 8   d ) of the CPU modules ( 5   a - 5   d ) (S 5 ). Specifically, in a CPU module of which the connection state is “main,” that the CPU module is “main” is stored as the definition information. In a CPU module of which the connection state is “sub,” that the CPU module is “sub” is stored as the definition information. Then, the PLC  2  is in the normally operable state. 
     When the definition information (Qa-Qd) is stored in any one of the memories ( 8   a - 8   d ) (S 4 ), whether or not the connection state is “main” is confirmed (S 6 ). When the connection state is not “main,” whether or not the definition information stored in the CPU module is “main” is confirmed (S 7 ). When the definition information is also not “main,” it is determined that the connection state and the definition state match (that is, both are “sub”) (S 8 ). When the definition information is “main,” it is determined that the connection state and the definition state do not match (S 9 ), and error display is performed, for example, in the error display (error notification means) (ER) that the PLC  2  has (S 10 ). In this case, the PLC  2  is not in the normally operable state. 
     When the connection state is “main” (S 6 ), whether or not the definition information stored in the CPU module is “main” is confirmed (S 11 ). When the definition information is also “main,” it is determined that the connection state and the definition state match (that is, both are “main”) (S 12 ). When the definition information is “sub,” it is determined that the connection state and the definition state do not match (S 9 ), and error display is performed, for example, in the error display (ER) that the PLC  2  has (S 10 ). In this case, the PLC  2  is not in the normally operable state. 
     The above matching operation between the connection state and the definition information is performed for all the CPU modules. When it is determined that the connection state and the definition information match for all the CPU modules, the PLC  2  is in the normally operable state. 
     Next, the operation of the PLC  2  when program scan is performed is described using  FIG. 6 . When a scan operation is started (S 21 ), batch output (S 22 ) and batch input (S 23 ) are performed. Here, the batch output means that content of an output register that has been set by a ladder program (control program written in a ladder language) is output to an external device; and the batch input means that input from an external device is incorporated into an input register. Next, the CPU modules ( 5   a - 5   d ) each start to operate (S 24 ). First, match or mismatch between the connection state and the definition information of each of the CPU modules is confirmed (S 25 ). The confirmation process of match or mismatch between the connection state and the definition information of each of the CPU modules is as described in  FIG. 5 . 
     When it is determined that the connection state and the definition information of each of the CPU modules match, analysis of the control program (P) (for example, written in the ladder language) is executed (S 26 ), and operation control of the servo motor  4  based on the control program (P) is performed. Here, a clock signal of a CPU module that has been set as a main CPU is transmitted to a CPU module that has been set as a sub CPU. The sub CPU operates while synchronized with the clock signal of the main CPU. 
     Next, data backup procedures of the PLC  2  are described using  FIG. 7 . A USB memory (external storage device) is connected to the data communication port ( 2   a ) (S 31 ). When a data communication request signal for communicating with the USB memory is received (S 32 ), the PLC  2  first confirms match or mismatch between the connection state and the definition information of each of the CPU modules (S 33 ). The confirmation process of match or mismatch between the connection state and the definition information of each of the CPU modules is as described in  FIG. 5 . 
     When it is determined that the connection state and the definition information of each of the CPU modules match, data backup from the PLC  2  to the USB memory (data reading from the PLC  2 ) and data loading from the USB memory to the PLC  2  (data writing to the PLC  2 ) are allowed (S 34 ). On the other hand, when it is determined that the connection state and the definition information of each of the CPU modules do not match, only data reading from the PLC  2  is allowed, but data writing to the PLC  2  is not allowed (S 35 ). 
     Next, editing procedures of the control program (P) using an engineering tool (program editing application) are described using  FIG. 8 . A PC having an engineering tool is connected to the data communication port ( 2   a ) (S 41 ). When an editing command is received from the PC side (S 42 ), the PLC  2  first confirms match or mismatch between the connection state and the definition information of each of the CPU modules (S 43 ). The confirmation process of match or mismatch between the connection state and the definition information of each of the CPU modules is as described in  FIG. 5 . 
     When it is determined that the connection state and the definition information of each of the CPU modules match, both data reading from the PLC  2  to the PC and data writing from the PC to the PLC  2  by the engineering tool are allowed (S 44 ). On the other hand, when it is determined that the connection state and the definition information of each of the CPU modules do not match, only data reading from the PLC  2  to the PC is allowed, but data writing to the PLC  2  is not allowed (S 45 ). 
     Second Embodiment 
       FIG. 9  is a block diagram illustrating a schematic configuration of a PLC  2  according to a second embodiment. The PLC  2  has multiple CPU racks (R 1 -R 3 ). The CPU racks (R 1 -R 3 ) respectively have IF units (F 1 -F 3 ), power source modules  10 , CPU modules  5  and option modules  6 . In  FIG. 9 , the CPU rack (R 1 ) has one CPU module ( 5   a ), the CPU rack (R 2 ) has one CPU module ( 5   c ), and the CPU rack (R 3 ) has one CPU module ( 5   d ). The CPU modules ( 5   a ,  5   c ,  5   d ) have the same configuration. 
       FIG. 10  is a block diagram illustrating a schematic configuration of the CPU module ( 5   a ) that is connected to the IF unit (F 1 ) in the CPU rack (R 1 ). The CPU module ( 5   a ) has a discrimination bit ( 12   a ) in a memory ( 8   a ). The discrimination bit ( 12   a ) has configuration and function that are the same as described in the first embodiment. In the CPU module ( 5   a ), the IF unit (F 1 ) does not have a slave rack extension module  11 . Therefore, a potential state of the connection port ( 11   a ) is an OPEN state. Therefore, an input potential to a connection port ( 11   b ) of an FPGA ( 7   a ) due to a first potential signal (S 1 ) is Low Level, the discrimination bit ( 12   a ) is “0” and a CPU ( 13   a ) in the CPU module ( 5   a ) is set as a main CPU. When the CPU ( 13   a ) is set as a main CPU, the setting information (the information that the CPU ( 13   a ) is a main CPU) is stored as definition information (Qa) in the memory ( 8   a ). When the control program (P) is executed, an operation clock signal of the CPU module ( 5   a ) as a main CPU becomes a reference clock signal of the program execution. 
     In the CPU rack (R 2 ), the IF unit (F 2 ) has a slave rack extension module  11 . Therefore, the CPU module ( 5   c ) is set as a sub CPU. In the CPU rack (R 3 ), the IF unit (F 3 ) has a slave rack extension module  11 . Therefore, a CPU ( 13   d ) in the CPU module ( 5   d ) is set as a sub CPU. In the CPU racks (R 2 , R 3 ), a process in which the CPU modules ( 5   c ,  5   d ) are each set as a sub CPU is the same as that described regarding the CPU rack (R 2 ) and the CPU module ( 5   c ) in the first embodiment and that described in  FIG. 4 , and thus a detailed description thereof is omitted. When the control program (P) is executed, an operation clock signal of the CPU module ( 5   c ) as a sub CPU is synchronized with a clock signal received from the CPU module ( 5   a ) as a main CPU. 
     Third Embodiment 
       FIG. 11  is a block diagram illustrating a schematic configuration of a PLC  2  according to a third embodiment. The PLC  2  has multiple CPU racks (R 1 -R 3 ). The CPU racks (R 1 -R 3 ) respectively have IF units (F 1 -F 3 ), power source modules  10 , CPU modules  5  and option modules  6 . In  FIG. 11 , the CPU rack (R 1 ) has two CPU modules ( 5   a ,  5   b ), the CPU rack (R 2 ) has two CPU modules ( 5   c ,  5   d ), and the CPU rack (R 3 ) has two CPU modules ( 5   e ,  5   f ). The CPU modules ( 5   a - 5   f ) have the same configuration. 
     In the CPU rack (R 1 ), the IF unit (F 1 ) does not have a slave rack extension module  11 . Therefore, a CPU ( 13   a ) in the CPU module ( 5   a ) is set as a main CPU. Further, a CPU ( 13   b ) in the CPU module ( 5   b ) that is connected to the CPU module ( 5   a ) that is a main CPU is set as a sub CPU. A process in which each of these is set is the same as that described regarding the CPU rack (R 1 ) and the CPU modules ( 5   a ,  5   b ) in the first embodiment and that described in  FIG. 3 , and thus a detailed description thereof is omitted. When the control program (P) is executed, an operation clock signal of the CPU module ( 5   a ) as a main CPU becomes a reference clock signal of the program execution. An operation clock signal of the CPU module ( 5   b ) as a sub CPU is synchronized with a clock signal from the CPU module ( 5   a ) as a main CPU. 
       FIG. 12  is a block diagram illustrating a schematic configuration of the CPU module ( 5   c ) that is connected to the IF unit (F 2 ) in the CPU rack (R 2 ). The CPU module ( 5   c ) has a discrimination bit ( 12   c ) in a memory ( 8   c ). The discrimination bit ( 12   c ) has configuration and function that are the same as described in the first embodiment. In the CPU module ( 5   c ), the IF unit (F 2 ) does not have a slave rack extension module  11 . Therefore, a potential state of the connection port ( 11   e ) is Vcc Level. Therefore, an input potential to a connection port ( 11   f ) of an FPGA ( 7   c ) due to a first potential signal (S 1 ) is High Level, the discrimination bit ( 12   c ) is “1” and the CPU ( 13   c ) in the CPU module ( 5   c ) is set as a sub CPU. When the CPU ( 13   c ) is set as a sub CPU, the setting information (the information that the CPU ( 13   c ) is a sub CPU) is stored as definition information (Qc) in the memory ( 8   c ). When the control program (P) is executed, an operation clock signal of the CPU module ( 5   c ) as a sub CPU is synchronized with a clock signal from the CPU module ( 5   a ) as a main CPU. 
     The CPU module ( 5   c ) has an output port ( 11   g ). A potential state (predetermined potential state) of a second potential signal (S 2 ) that is output from the output port ( 11   g ) is Vcc. The CPU module ( 5   d ) has therein an FPGA ( 7   d ). The output port ( 11   g ) is connected to a connection port ( 11   h ) of the FPGA ( 7   d ). A potential state of the output port ( 11   g ) is a Vcc Level. Therefore, the potential state of the second potential signal (S 2 ) that is input to the connection port ( 11   h ) is High Level. 
     The CPU module ( 5   d ) has a discrimination bit ( 12   d ) in a memory ( 8   d ). The discrimination bit ( 12   d ) has configuration and function that are the same as those of the discrimination bit ( 12   a ). In the CPU module ( 5   d ), the potential state of the second potential signal (S 2 ) that is input to the connection port ( 11   h ) of the FPGA ( 7   d ) is High Level. Therefore, the discrimination bit ( 12   d ) is “1” and the CPU ( 13   d ) in the CPU module ( 5   d ) is set as a sub CPU (the CPU ( 13   d ) is a sub CPU that is dependently connected to the CPU module ( 5   c ) as a sub CPU, and thus may be referred to as a sub-sub CPU in order to be distinguished from the CPU module ( 5   c ) as a sub CPU). When the CPU ( 13   d ) is set as a sub CPU, the setting information (the information that the CPU ( 13   d ) is a sub CPU) is stored as definition information (Qd) in the memory ( 8   d ). When the control program (P) is executed, an operation clock signal of the CPU module ( 5   d ) as a sub CPU is synchronized with a clock signal from the CPU module ( 5   a ) as a main CPU. 
     A CPU in the CPU module ( 5   e ) in the CPU rack (R 3 ) is also set as a sub CPU, similar to the CPU ( 13   c ) in the CPU module ( 5   c ) in the CPU rack (R 2 ). Further, a CPU in the CPU module ( 5   f ) in the CPU rack (R 3 ) is also set as a sub CPU (sub-sub CPU), similar to the CPU ( 13   d ) in the CPU module ( 5   d ) in the CPU rack (R 2 ). Configurations and setting processes of these are the same as those described regarding the CPU rack (R 3 ) in the third embodiment and those described in  FIG. 12 , and thus a detailed description thereof is omitted. 
     According to a programmable controller of the multi-CPU configuration, multi-tasking becomes possible, and load balancing and high speed processing are realized. Further, multiple applications are divided according to functionality and are processed by multiple CPUs. Thereby, complicated processing is avoided and simplified high-speed processing is achieved. 
     When a system processor has a code switch for identifying each of the CPU modules, by setting the code switches, one CPU module can be distinguished from other CPU modules. 
     However, in order to identify each of the CPUs, a switch is provided for each of the CPUs, and switch settings are purposely performed. Further, on a program side, it is declared which CPU is a main CPU and which CPU is a sub CPU. When there is a contradiction between the declaration on the program side and the settings (that is, the switch settings) of the main CPU and the sub CPU that are detected on a hardware side, there is a concern that the program may operate abnormally. The abnormal operation of the program can cause abnormal operation of a control object (such as a motor) of which operation is controlled by the programmable controller. 
     A programmable controller according to an embodiment of the present invention can automatically complete settings for main and sub CPUs by connecting multiple CPUs having the same configuration to a circuit, without the need of declaring which CPU is a main CPU and which CPU is a sub CPU in a program and without the need of performing switch settings. Further, a programmable controller according to an embodiment of the present invention can prevent abnormal operation of a program even when settings of a main CPU and a sub CPU have changed due to a change or the like in circuit connection. 
     A programmable controller according to an embodiment of the present invention includes multiple interface units and multiple CPU modules. Each of the interface units can connect to one of the CPU modules and can transmit a first potential signal having multiple different potential states toward the connected CPU module. Each of the CPU modules can connect to one of the interface units and can connect to another CPU module, and has therein a CPU for performing arithmetic processing and a memory for storing a discrimination bit and definition information. The discrimination bit has binarized information indicating whether the CPU in the CPU module that has the discrimination bit is a main CPU or a sub CPU based on the potential state of the first potential signal that is input to the CPU module from the interface unit to which the CPU module is connected. The definition information has setting information indicating whether the CPU in the CPU module that has the definition information is set in advance as a main CPU or as a sub CPU. 
     When one of the CPU modules is connected to another CPU module, the CPU module can transmit a second potential signal having a predetermined potential state toward the another CPU module. A discrimination bit in the another CPU module has binarized information indicating that the CPU of the CPU module is a sub CPU based on the potential state of the second potential signal. 
     The programmable controller may further include an error notification means that performs error notification when content of the binarized information that the discrimination bit in the CPU module has indicating whether the CPU of the CPU module is a main CPU or a sub CPU and content of the setting information that the definition information in the CPU module has indicating whether the CPU of the CPU module is a main CPU or a sub CPU do not match. 
     The programmable controller may limit execution of arithmetic processing by the CPU when content of the binarized information that the discrimination bit in the CPU module has indicating whether the CPU of the CPU module is a main CPU or a sub CPU and content of the setting information that the definition information in the CPU module has indicating whether the CPU of the CPU module is a main CPU or a sub CPU do not match. 
     When the definition information is not stored in the memory that the CPU module has, the programmable controller may create new definition information in the memory based on the content of the binarized information that the discrimination bit in the CPU module has indicating whether the CPU of the CPU module is a main CPU or a sub CPU. 
     The multiple CPU modules may generate clock signals that become timing references for execution of the arithmetic processing, and may cause a clock signal of a CPU module of which the CPU is indicated as a sub CPU by the binarized information that the discrimination bit has to be synchronized with a clock signal of a CPU module of which the CPU is indicated as a main CPU by the binarized information that the discrimination bit has. 
     According to an embodiment of the present invention, settings for main and sub CPUs can be automatically completed by connecting multiple CPUs having the same configuration to a circuit, without the need of declaring which CPU is a main CPU and which CPU is a sub CPU and without the need of performing switch settings. Further, abnormal operation of a program can be prevented even when settings of a main CPU and a sub CPU have changed due to a change or the like in circuit connection. 
     Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.