Patent Publication Number: US-2021172907-A1

Title: Semiconductor-Based Chemical Detection Device

Description:
RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 15/943,668, filed Apr. 2, 2018. U.S. application Ser. No. 15/943,668 is a continuation application of U.S. application Ser. No. 15/292,795 filed Oct. 13, 2016. U.S. application Ser. No. 15/292,795 is a divisional of U.S. application Ser. No. 14/597,507 filed Jan. 15, 2015. U.S. application Ser. No. 14/597,507 is a continuation of U.S. application Ser. No. 13/861,237 filed Apr. 11, 2013; now U.S. Pat. No. 8,983,783. U.S. Pat. No. 8,983,783 is a continuation of U.S. patent application Ser. No. 13/174,514 filed Jun. 30, 2011; now U.S. Pat. No. 8,731,847. U.S. Pat. No. 8,731,847 claims benefit of U.S. Provisional Application No. 61/360,493 filed Jun. 30, 2010, U.S. Provisional Application No. 61/360,495 filed Jul. 1, 2010, U.S. Provisional Application No. 61/361,403 filed Jul. 3, 2010, and U.S. Provisional Application No. 61/365,327 filed Jul. 17, 2010. All of the aforementioned applications are incorporated herein by reference, each in their entirety. 
    
    
     BACKGROUND 
     Electronic devices and components have found numerous applications in chemistry and biology (more generally, “life sciences”), especially for detection and measurement of various chemical and biological reactions and identification, detection and measurement of various compounds. One such electronic device is referred to as an ion-sensitive field effect transistor, often denoted in the relevant literature as an “ISFET” (or pHFET). ISFETs conventionally have been explored, primarily in the academic and research community, to facilitate measurement of the hydrogen ion concentration of a solution (commonly denoted as “pH”). 
     More specifically, an ISFET is an impedance transformation device that operates in a manner similar to that of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and is particularly configured to selectively measure ion activity in a solution (e.g., hydrogen ions in the solution are “analytes”). A detailed theory of operation of an ISFET is given in “Thirty years of ISFETOLOGY: what happened in the past 30 years and what may happen in the next 30 years,” P. Bergveld, Sens. Actuators, 88 (2003), pp. 1-20 (“Bergveld”), which publication is hereby incorporated herein by reference in its entirety. 
     Details of fabricating an ISFET using a conventional Complementary Metal Oxide Semiconductor (CMOS) process may be found in Rothberg, et al., U.S. Patent Publication No. 2010/0301398, Rothberg, et al., U.S. Patent Publication No. 2010/0282617, and Rothberg et al., U.S. Patent Publication 2009/0026082; these patent publications are collectively referred to as “Rothberg,” and are all incorporated herein by reference in their entireties. In addition to CMOS, bipolar and CMOS (biCMOS) processing may be used, such as a process that would include a p-channel MOS FET array with bipolar structures on the periphery. Alternatively, other technologies may be employed where a sensing element can be made with a three-terminal devices in which a sensed ion leads to the development of a signal that controls one of the three terminals; such technologies may also include, for example, Gallium Arenides (GaAs) and carbon nanotube technologies. 
     Taking a CMOS example, a P-type ISFET fabrication is based on a p-type silicon substrate, in which an n-type well forms a “body” of the transistor. Highly-doped p-type (p+) source (S) and drain (D) regions, are formed within the n-type well. A highly-doped n-type (n+) region B may also be formed within the n-type well to provide a conductive body (or “bulk”) connection to the n-type well. An oxide layer may be disposed above the source, drain and body connection regions, through which openings are made to provide electrical connections (via electrical conductors) to these regions. A polysilicon gate may be formed above the oxide layer at a location above a region of the n-type well, between the source and the drain. Because it is disposed between the polysilicon gate and the transistor body (i.e., the n-type well), the oxide layer often is referred to as the “gate oxide.” 
     Like a MOSFET, the operation of an ISFET is based on the modulation of charge concentration (and thus channel conductance) caused by a Metal-Oxide-Semiconductor (MOS) capacitance. This capacitance is constituted by a polysilicon gate, a gate oxide and a region of the well (e.g., n-type well) between the source and the drain. When a negative voltage is applied across the gate and source regions, a channel is created at the interface of the region and the gate oxide by depleting this area of electrons. For an n-well, the channel would be a p-channel. In the case of an n-well, the p-channel would extend between the source and the drain, and electric current is conducted through the p-channel when the gate-source potential is negative enough to attract holes from the source into the channel. The gate-source potential at which the channel begins to conduct current is referred to as the transistor&#39;s threshold voltage VTH (the transistor conducts when VGS has an absolute value greater than the threshold voltage VTH). The source is so named because it is the source of the charge carriers (holes for a p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel. 
     As described in Rothberg, an ISFET may be fabricated with a floating gate structure, formed by coupling a polysilicon gate to multiple metal layers disposed within one or more additional oxide layers disposed above the gate oxide. The floating gate structure is so named because it is electrically isolated from other conductors associated with the ISFET; namely, it is sandwiched between the gate oxide and a passivation layer that is disposed over a metal layer (e.g., top metal layer) of the floating gage. 
     As further described in Rothberg, the ISFET passivation layer constitutes an ion-sensitive membrane that gives rise to the ion-sensitivity of the device. The presence of analytes such as ions in an analyte solution (i.e., a solution containing analytes (including ions) of interest or being tested for the presence of analytes of interest), in contact with the passivation layer, particularly in a sensitive area that may lie above the floating gate structure, alters the electrical characteristics of the ISFET so as to modulate a current flowing through the channel between the source and the drain of the ISFET. The passivation layer may comprise any one of a variety of different materials to facilitate sensitivity to particular ions; for example, passivation layers comprising silicon nitride or silicon oxynitride, as well as metal oxides such as silicon, aluminum or tantalum oxides, generally provide sensitivity to hydrogen ion concentration (pH) in an analyte solution, whereas passivation layers comprising polyvinyl chloride containing valinomycin provide sensitivity to potassium ion concentration in an analyte solution. Materials suitable for passivation layers and sensitive to other ions such as sodium, silver, iron, bromine, iodine, calcium, and nitrate, for example, are known, and passivation layers may comprise various materials (e.g., metal oxides, metal nitrides, and metal oxynitrides). Regarding the chemical reactions at the analyte solution/passivation layer interface, the surface of a given material employed for the passivation layer of the ISFET may include chemical groups that may donate protons to or accept protons from the analyte solution, leaving at any given time negatively charged, positively charged, and neutral sites on the surface of the passivation layer at the interface with the analyte solution. 
     With respect to ion sensitivity, an electric potential difference, commonly referred to as a “surface potential,” arises at the solid/liquid interface of the passivation layer and the analyte solution as a function of the ion concentration in the sensitive area due to a chemical reaction (e.g., usually involving the dissociation of oxide surface groups by the ions in the analyte solution in proximity to the sensitive area). This surface potential in turn affects the threshold voltage of the ISFET; thus, it is the threshold voltage of the ISFET that varies with changes in ion concentration in the analyte solution in proximity to the sensitive area. As described in Rothberg, since the threshold voltage VTH of the ISFET is sensitive to ion concentration, the source voltage VS provides a signal that is directly related to the ion concentration in the analyte solution in proximity to the sensitive area of the ISFET. 
     Arrays of chemically-sensitive FETs (“chemFETs”), or more specifically ISFETs, may be used for monitoring reactions—including, for example, nucleic acid (e.g., DNA) sequencing reactions, based on monitoring analytes present, generated or used during a reaction. More generally, arrays including large arrays of chemFETs may be employed to detect and measure static and/or dynamic amounts or concentrations of a variety of analytes (e.g., hydrogen ions, other ions, non-ionic molecules or compounds, etc.) in a variety of chemical and/or biological processes (e.g., biological or chemical reactions, cell or tissue cultures or monitoring, neural activity, nucleic acid sequencing, etc.) in which valuable information may be obtained based on such analyte measurements. Such chemFET arrays may be employed in methods that detect analytes and/or methods that monitor biological or chemical processes via changes in charge at the chemFET surface. Such use of chemFET (or ISFET) arrays involves detection of analytes in solution and/or detection of change in charge bound to the chemFET surface (e.g. ISFET passivation layer). 
     Research concerning ISFET array fabrication is reported in the publications “A large transistor-based sensor array chip for direct extracellular imaging,” M. J. Milgrew, M. O. Riehle, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 111-112, (2005), pp. 347-353, and “The development of scalable sensor arrays using standard CMOS technology,” M. J. Milgrew, P. A. Hammond, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 103, (2004), pp. 37-42, which publications are incorporated herein by reference and collectively referred to hereafter as “Milgrew et al.” Descriptions of fabricating and using ChemFET or ISFET arrays for chemical detection, including detection of ions in connection with DNA sequencing, are contained in Rothberg. More specifically, Rothberg describes using a chemFET array (in particular ISFETs) for sequencing a nucleic acid involving incorporation of known nucleotides into a plurality of identical nucleic acids in a reaction chamber in contact with or capacitively coupled to the chemFET, wherein the nucleic acids are bound to a single bead in the reaction chamber, and detecting a signal at the chemFET, wherein detection of the signal indicates release of one or more hydrogen ions resulting from incorporation of the known nucleotide triphosphate into the synthesized nucleic acid. 
     However, with the scaling of ISFET sensor array designs, more and more ISFET sensors are packed on a chip. Thus, there is a need in the art to provide a readout scheme to output measured data from a chip at a high speed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         FIG. 1  illustrates a 1T ion sensitive pixel according to an embodiment of the present invention. 
         FIG. 2  illustrates the cross section of a 1T pixel according to an embodiment of the present invention. 
         FIG. 3  shows the schematic of an array of pixels with column readout switches according to an embodiment of the present invention. 
         FIG. 4  shows the source follower configuration of the 1T pixel according to an embodiment of the present invention. 
         FIG. 5A  shows a 1T common source ion sensitive pixel according to an embodiment of the present invention. 
         FIG. 5B  shows the pixel in a common source readout configuration according to an embodiment of the present invention. 
         FIG. 5C  shows a common source equivalent circuit according to an embodiment of the present invention. 
         FIG. 6  shows a schematic of an array of pixels with column readout switches according to an embodiment of the present invention. 
         FIG. 7A  shows a cross section of a 1T common source pixel according to an embodiment of the present invention. 
         FIG. 7B  shows a cross section of a 1T common source pixel according to an embodiment of the present invention. 
         FIG. 8  shows a common source pixel with a cascoded row selection device according to an embodiment of the present invention. 
         FIG. 9  shows a one-transistor pixel array with cascoded column circuit according to an embodiment of the present invention. 
         FIGS. 10A and 10B  show a one-transistor pixel array according to an embodiment of the present invention. 
         FIG. 11  shows a two-transistor (2T) pixel according to an embodiment of the present invention. 
         FIG. 12A to 12H  illustrate 2T pixel configurations according to embodiments of the present invention. 
         FIG. 13A to 13D  illustrate common source 2T cell configurations according to embodiments of the present invention. 
         FIG. 14A  shows a 2T pixel array according to an embodiment of the present invention. 
         FIGS. 14B and 14C  show a layout for a 2×2 2T pixel array according to an embodiment of the present invention. 
         FIG. 15  shows a capacitive charge pump according to an embodiment of the present invention. 
         FIG. 16  shows a charge pump according to an embodiment of the present invention. 
         FIG. 17  shows a charge pump according to an embodiment of the present invention. 
         FIG. 18  shows a charge pump according to an embodiment of the present invention. 
         FIG. 19  shows a basic IS accumulation pixel according to an embodiment of the present invention. 
         FIG. 20A to 20P  show surface potential diagrams for basic charge accumulation according to an embodiment of the present invention. 
         FIGS. 21 and 22  show an IS accumulation pixel with 2 transistors according to an embodiment of the present invention. 
         FIG. 23  shows surface potential diagrams for the pixel of  FIG. 22  according to an embodiment of the present invention. 
         FIG. 24  shows an IS accumulation pixel with 2 transistors and 4 electrodes according to an embodiment of the present invention. 
         FIG. 25  shows the surface potential diagrams for the pixel of  FIG. 24  according to an embodiment of the present invention. 
         FIG. 26  shows an IS accumulation pixel with 1 transistor and 3 electrodes according to an embodiment of the present invention. 
         FIG. 27  shows a three transistor (3T) active pixel sensor according to an embodiment of the present invention. 
         FIG. 28  shows an alternate embodiment of a 3T active pixel sensor. 
         FIG. 29  shows a 3T active pixel sensor with a sample and hold circuit according to an embodiment of the present invention. 
         FIG. 30  shows a 3T active pixel sensor with a correlated double sampling circuit according to an embodiment of the present invention. 
         FIG. 31  shows a 2.5T active pixel sensor array according to an embodiment of the present invention. 
         FIG. 32  shows a 1.75T active pixel sensor array according to an embodiment of the present invention. 
         FIG. 33  illustrates a block diagram of a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 34  illustrates a block diagram of another chemical detection circuit according to another embodiment of the present invention. 
         FIG. 35  illustrates a block diagram of yet another chemical detection circuit according to yet another embodiment of the present invention. 
         FIG. 36  illustrates a process for generating an output of a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 37  illustrates a block diagram of a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 38A  illustrates a block diagram of components of a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 38B  illustrates shift directions in different quadrants of a tile according to an embodiment of the present invention. 
         FIG. 39  illustrates a block diagram of a channel of a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 40  illustrates a swizzle configuration of signal lines of a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 41  illustrates a process for output data from a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 42  illustrates a system architecture for chemical detection according to an embodiment of the present invention. 
         FIG. 43  illustrates an analog reader board for a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 44  illustrates a digital reader board for a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 45  illustrates a block diagram of analog front end and noise calculations for a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 46  illustrates a block diagram of bandwidth utilization for a chemical detection circuit according to an embodiment of the present invention. 
         FIG. 47  illustrates a block diagram for clock distribution according to an embodiment of the present invention. 
         FIG. 48  illustrates a block diagram for power distribution according to an embodiment of the present invention. 
         FIG. 49  illustrates a block diagram for digital-to-analog converts (DACs) of an analog reader board according to an embodiment of the present invention. 
         FIG. 50  illustrates a block diagram of field-programmable gate array (FPGA) configuration according to an embodiment of the present invention. 
         FIG. 51  illustrates a block diagram of FPGA power monitoring according to an embodiment of the present invention. 
         FIG. 52  illustrates a digital chemical detection circuit according to an embodiment of the present invention. 
         FIG. 53  illustrates a more detailed block diagram of the digital chemical detection circuit of  FIG. 52  according to an embodiment of the present invention. 
         FIG. 54  illustrates a serializer circuit according to an embodiment of the present invention. 
         FIG. 55  illustrates a more detailed block diagram of the serializer of  FIG. 54  according to an embodiment of the present invention. 
         FIG. 56  illustrates a block diagram of a digital chemical detection circuit according to an embodiment of the present invention. 
         FIG. 57  illustrates a block diagram of another digital chemical detection circuit according to an embodiment of the present invention. 
         FIG. 58  illustrates a block diagram of another digital chemical detection circuit according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     One-Transistor Pixel Array 
     A floating gate (FG) transistor may be used to detect ions in close proximity to the gate electrode. The transistor may be configured with other transistors to form a pixel that can be placed into an array for addressable readout. In the simplest form, the ancillary transistors are used solely to isolate and select the floating gate transistor for readout in an array. The floating gate transistor may be a chemically-sensitive transistor, and more specifically, a chemically-sensitive field effect transistor (ChemFET). The ChemFET may be designed with a metal-oxide-semiconductor field-effect transistor (MOSFET) containing self-aligned source and drain implants fabricated using standard complementary metal-oxide-semiconductor (CMOS) processing. The ChemFET may be an ion sensitive FET (ISFET), and may be a PMOS or an NMOS device. 
     A floating gate (FG) transistor may be used to detect ions in close proximity to the gate electrode. The transistor may be configured with other transistors to form a pixel that can be placed into an array for addressable readout. In the simplest form, the ancillary transistors are used solely to isolate and select the floating gate transistor for readout in an array. The floating gate transistor may be a chemically-sensitive transistor, and more specifically, a chemically-sensitive field effect transistor (ChemFET). The ChemFET may be designed with a metal-oxide-semiconductor field-effect transistor (MOSFET) containing self-aligned source and drain implants fabricated using standard complementary metal-oxide-semiconductor (CMOS) processing. The ChemFET may be an ion sensitive FET (ISFET), and may be a PMOS or an NMOS device. 
     To reduce the pixel size to the smallest dimensions and simplest form of operation, the ancillary transistors may be eliminated to form an ion sensitive field-effect transistor (ISFET) using one transistor. This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Parasitic overlap capacitance between terminals of the transistor limits the gain. The capacitance ratios also allow consistent pixel-to-pixel gain matching and relatively constant current operation which justifies the use of a row selection line which can sink the necessary current without causing unacceptable variation. Derivatives of this allow for increased programmable gain through a cascoded transistor enabled during readout. Configurable pixels can be created to allow both common source read out as well as source follower read out. 
       FIG. 1  illustrates a 1T ion sensitive pixel according to one embodiment of the present invention. As shown, the pixel  100  may have one and only one transistor  101 , one and only one row line R and one and only one column line C. The transistor  101  is shown as an n-channel MOSFET (NMOS) transistor in a p-type epitaxial substrate available using standard CMOS processes in this embodiment. It should be understood that NMOS is only used as an example in the present invention, and the transistor  101  may be a PMOS as well. The selection of NMOS or PMOS as a preferred device depends on which device does not require a top-side bulk contact for a given process. Typically NMOS is preferred when using a P+ wafer with P− epitaxy layer (called an epi-wafer) because the underlying P+ substrate biases the bulk on an array of pixels without the need to wire in a bulk contact at each pixel location. Therefore, a global bulk contact is an attractive combination for use with a 1T pixel where a small pixel pitch is required. The floating gate G of the transistor  101  may contain trapped charge, which may be properly discharged such that the electrode is at approximately the same potential as the substrate when all other terminals are also biased to the substrate potential. The row line R may be capacitively coupled to the drain D of the transistor  101 , and the column line may be coupled to the source S of the transistor  101 . A gate to drain overlap capacitance Cgd may form between the gate G and the drain D. The pixel  100  may be addressable from the row line R, which supplies the column current (i.e., drain-to-source current of the transistor  101 ) and boosts the potential at the floating gate. 
     In a one-transistor pixel array, such as the one shown in  FIG. 3 , row selection may be facilitated by boosting the FG nodes for a particular row. In one embodiment, the readout of the pixel is a winner-take-all circuit, which will be described below. 
       FIG. 2  illustrates the cross section of a 1T pixel according to one embodiment of the present invention. The transistor in the 1T pixel may be formed using an n-channel FET device by having a drain D and a source S formed using n-type implants within a p-type semiconductor. As shown, the transistor may have a floating gate G, the drain D and the source S. The source S may be coupled to the column line C and the drain D may be coupled to the row line R. Lightly doped drain (LDD) regions may create a gate to drain overlap capacitance Cgd and/or a gate to source overlap capacitance Cgs. 
     In one embodiment, the 1T ion pixel  100  may work by boot-strapping the row selection line R to the floating gate G while at the same time providing a source of current for the column line bias. In the simplest form, this bootstrapping occurs without adding any extra capacitors. The gate to drain overlap capacitance Cgd, as shown in  FIGS. 1 and 2 , may naturally form the necessary capacitive coupling. To increase capacitive coupling, if desired, the row selection metal line can form an extra metal capacitor to the floating metal electrode or more significant source and drain extensions can be made with ion implantation. 
       FIG. 3  shows the schematic of an array of pixels with column readout switches according to one embodiment of the present invention. For illustrative purposes, four 1T pixels  301 ,  302 ,  303  and  304  of an array  300  are shown arranged into two rows and two columns, though the array  300  could extend to an array of any size of 1T pixels. The 1T pixel may be similar to the one shown in  FIG. 1 . The drains of pixels  301  and  302  are coupled to a row line RO, and the sources of pixels  301  and  302  are coupled to column lines C 0  and C 1  respectively. The drains of pixels  303  and  304  are coupled to a row line R 1 , and the sources of pixels  303  and  304  are coupled to column lines C 0  and C 1  respectively. The pixel array can be loaded with a current source but the simplest implementation makes use of just a single switch that precharges the column line to a low potential such as the substrate potential. A column readout switch  305  is coupled to the column line C 0  and a column readout switch  306  is coupled to the column line Cl. The column readout switch  305  comprises a switch Sa, a switch Sb, a current source Isource and a capacitor Cw. The switch Sa is used for precharging the column line and to initialize the column line quickly between samples. The switch Sb is used to sample and hold the analog value that is read on the column line. In some cases, neither a sampling capacitor nor a switch Sb are required if the pixel is converted to digital through and analog to digital converter while the pixel is held under bias. The switch Sa is used to ground the column line C 0 . After the column line switch Sb is open the sample is held in the capacitor, the final value on the column line, as sampled by the capacitor, will be determined almost entirely by the active row because the circuit operates according to “a winner take-all” mode (i.e., the resulting voltage represents the largest voltage of the ISFETs coupled to the readout circuit). The column readout circuit  306  functions similarly. 
     The operation of this pixel depends on the fact that the signal range of any given pixel is small compared to the supply voltage or read range of the source follower. For example, the useful signal range may be only 100 mV and the supply voltage may be 3.3V. When a row is selected, the R line is driven to an active high voltage VH, while all other row lines are held at an active low voltage VL. The voltage VL is selected to be approximately equal to the nominal voltage on the column line C during the readout of any given pixel. Because the signal range is small, this voltage is known to within 100 mV in this example. Therefore, the drain to source voltage of all inactive pixels is always held to small values. This point is only critical if the gate to source voltage of inactive pixels is near the threshold of the device. For the row driven to VH, the FG voltages for that row are significantly higher than the other rows because of the bootstrapping that occurs when the row line transitions to VH. After the column line switch Sb is open, the final value on the column line will be determined almost entirely by the active row because the circuit operates according to the winner take-all mode. 
     There are two sources of current from other rows that can distort the signal value (one that adds current and one that takes away current) and there must be enough bootstrapping available to successfully read pixels without significant interaction from the other rows that produce these sources. The analysis to determine how much bootstrapping is needed is as follows. By the time the pixel is sampled, the device has entered the subthreshold region of operation which has a transconductance slope, for example, of approximately 100 mV/decade. This means that for every 100 mV of change in gate voltage, the current changes by 10 times. In order to effectively read a single pixel, a criteria is set so that 99% of the current on the column line is attributable to the active row and only 1% is attributable to the inactive rows (distortion current). From here it can be determined how much bootstrapping is necessary. With only 2 rows in the pixel array, a 200 mV difference in the floating gate voltages is needed according to the subthreshold slope. Since a signal range of about 100 mV is also needed to be accounted for, the total requirement is about 300 mV. If there are 10 rows, there may be 10 times more contribution from inactive rows. Therefore an extra 100 mV is needed. If the array is increased to 100 rows, another 100 mV is needed. If the array is increased to 10{circumflex over ( )}n rows, 300+100*n mV is needed. As an example, a 10000 (10{circumflex over ( )}4) row pixel array only requires a total of 700 mV (300+100*4) of bootstrapping. This amount of bootstrapping can be achieved from the overlap capacitance of the gate and drain. If more capacitance is needed, extra coupling can be facilitated in the mask layout. The above analysis only applies to pixels contributing to the readout current. 
     Pixels can also take current away from the column line and sink it through the deactivated row lines. Since the deactivated row line is set to approximately the level of the column line, this current draw will be minimal but it must still be quantified and controlled. To accomplish this, the final current on the column line should not be allowed to diminish beyond a certain level. This is ensured by loading the column with a small current sink such as 1 uA. For a W/L (width to length) ratio of 1, a transistor biased at its threshold will have a saturation current of about 0.1 uA. This current decreases by a factor of 10 for every 100 mV of reduction in gate to source voltage. If less than 1% contribution of current is required, the VGS of inactive pixels needs to be kept to 100+100*n mV below the threshold voltage where 10{circumflex over ( )}n is the number of pixels in the row. Thus, for a 10000 row pixel array, VGS needs to be kept to 500 mV below threshold. A typical 3.3V NMOS transistor has a VT of 600 mV. Therefore, VGS should be less than 100 mV for inactive pixels. Assuming that the FG has a nominal voltage of 0V when the row (R) and column (C) lines are at 0V, this condition is met even as R and C couple to the FG. If the FG has a larger nominal voltage than 0V (for example, due to the trapped charge), more bootstrapping is necessary to cause the column line to reach a level within 100 mV of the FG. As long as the nominal FG voltage is sufficiently low, the second criteria for minimizing distortion current is not a limiting factor. Finally, enough bootstrapping is needed to produce a current on the column line that matches the bleeding current so that the pixel can produce a measurable voltage on the column line. If VG is nominally 0v, then 700 mV is needed for bootstrapping. Therefore, for an NMOS with VT as large as 600 mV, the amount of bootstrapping required is simply limited by the VT. In order to readout the pixel with margin, a good target for bootstrapping is 1V. This leaves 300 mV of range for variation. Achieving 1V of bootstrapping is practical within a 3.3V supply. 
     All the current from the column readout is distributed through the row line. This causes significant droop in the voltage of the row line if the column current is also significant. The voltage droop affects the bootstrapping level but is not detrimental to the readout of the source follower because variation in drain voltage has only a second order effect. Since pixels are read out with multiple samples, offsets are canceled such that the droop does not affect the sensitivity of the pixels. 
     It should be noted that the same layout can be used for both source follower readout and common source readout as long as optimizations are not made for either. Only accommodations that need to be made are in the column circuits. This makes for a flexible readout architecture and either readout method may be used depending on the necessary signal range. If the signal needs a high gain, the common source mode should be used. Otherwise, the source follower mode may be used. 
       FIG. 4  shows the source follower configuration of the 1T pixel according to one embodiment of the present invention. The source follower mode has a buffered readout and operates in a voltage mode, and has a gain less than 1. As shown, the sole transistor  401  may be coupled to an input voltage Vi at its gate G and to a fixed voltage at its drain D. The source S of the transistor  401  may be grounded via a current source Isource. The output voltage Vo may be taken from the source of the transistor  401 . A coupling capacitance Cc may exist between the input and the gate of the transistor  401 , a parasitic capacitor Cgd may exist between the gate G and the drain D of the transistor  401 , and a parasitic capacitor Cgs may exist between the gate and the source S of the transistor  401 . 
     The following analysis is given for the gain of the source follower readout. Referring to  FIG. 4 , the gain of the circuit (G) may be defined as Vo/Vi. Using reference pixels the electrode of the system may be swept to measure the gain such that Vo/Vi=G. Using the measured value of a parameter G, which is 0.65 in this example, the ratio of Cc to Cgd may be determined. As will be discussed later, it is this ratio that will determine the gain in the common source mode. The input capacitance of the source follower is Ci=Cgd+Cgs(I−Asf), wherein Asf is the gain of source follower. Due to the body effect, Asf is approximately 0.85. The capacitive divider relating to the input voltage on the FET is Cc/(Ci+Cc) and therefore, Cc/(Ci+Cc)=G/Asf. Since Cgs is about 3-5 times larger than Cgd and Asf is about 0.85, Ci is approximately 2Cgd. Therefore, Cc=2Cgd(G/(Asf−G)). In this example, the ratio of Cc to Cgd is about 6.5. 
     In one embodiment, the present invention obtains voltage gain by reading out with the common source configuration. It is desirable to achieve both a reduction in pixel size as well as an increase in signal level. The present invention eliminates the ancillary transistors in other pixel designs (e.g., 2T and 3T discussed below) and uses the source of the ISFET as the selection line to achieve both of these goals. The common source mode is a gain mode and a current mode. 
       FIG. 5A  shows a 1T common source ion sensitive pixel according to one embodiment of the present invention. As shown, the pixel  500  may have one and only one transistor  501 , one and only one row line R and one and only one column line C. The transistor  501  is shown as an n-channel MOSFET (NMOS) transistor in a p-type epitaxial substrate available using standard CMOS processes in this embodiment, although it may be a p-channel MOSFET as well. An NMOS device is typically preferred in use with a P+ epi wafer that requires no front side bulk contacts. Technically a PMOS could be use with a N+ epi wafer, but this configuration is not as commonly produced in standard CMOS processes. The row line R may be coupled to the source S of the transistor  501 , and the column line may be coupled to the drain D of the transistor  501 . The row selection is facilitated by switching on a path for the source voltage, and the readout of the pixel is through the drain. 
     The schematic of an array of pixels with column readout switches according to one embodiment of the present invention is shown in  FIG. 6 . The array  600  has four 1T common source pixels  601 ,  602 ,  603  and  604 . The 1T pixel may be similar to the one shown in  FIG. 5A . In this example, pixels are arranged into two rows and two columns. The drains of pixels  601  and  602  are coupled to a column line CO, and the sources of pixels  601  and  602  are coupled to row lines RO and R 1  respectively. The drains of pixels  603  and  604  are coupled to a column line C 1 , and the sources of pixels  603  and  604  are coupled to row lines RO and R 1  respectively. A column readout switch  605  is coupled to the column line C 0  and a column readout switch  606  is coupled to the column line C 1 . The column readout switch  605  comprises a switch Sa, a switch Sb, a resistor R and a capacitor C w0 . The column readout switch  606  comprises a switch Sa, a switch Sb, a resistor R and a capacitor C w1 . The switch Sa may pull the voltage on the column line to a fixed voltage, for example, to a 3.3V supply. When the column line switch Sb is open, the final value on the column line will be determined by the active row since the switch Sb, along with the capacitor C w0 , acts as a sample and hold circuit. 
     The pixel array can be loaded with a current source with finite output resistance or another load device such as a resistor. Normally the row selection lines will be held at an active high voltage VH. When a row is selected for readout, its row selection line is pulled low to VL. The value of VL is set such that the nominal current level is about 1 uA. If the FG has a value of 100 mV higher than the norm, 10 times this current will result on the column line. If the value of FG is 100 mV lower than the norm, the current will be 10 times lower. The settling time of the signal on the column line will be signal dependent. The voltage gain is achieved with the selection of the value of R and it can be configurable to achieve programmable gain. For example, if R is 100 k ohms, then the 100 mV, translates to 1V at the output. 
     The actual circuit is more complicated than just a simple common source amplifier because of the parasitic capacitance involved. Since the FG node is not driven, but rather capacitively coupled to the output, there is a feedback mechanism that limits the gain. This limit is roughly equal to the total capacitance at the FG node to the gate to drain capacitance. This ratio may be about 3. It could be designed to achieve higher gain such as 10 times with careful mask operations to reduce source and drain extensions. 
       FIG. 7A  shows the cross section of a 1T common source pixel according to one embodiment of the present invention. The transistor in the 1T pixel may be formed using an n-channel FET device by having a drain D and source S be formed using n-type implants within a p-type semiconductor. As shown, the transistor may have a floating gate G, the drain D and the source S. The source S may be coupled to the row line R and the drain D may be coupled to the column line C. Lightly doped drain (LDD) regions may create a gate to source overlap capacitance Cgs and a gate to drain overlap capacitance Cgd. 
     The overlap capacitance created by the LDD regions can be reduced by skipping the LDD implants at the drain for the device.  FIG. 7B  shows the cross section of a 1T common source pixel according to one embodiment of the present invention.  FIG. 7B  shows a drain node with a missing LDD region. This missing region reduces the capacitance and increases gain. This can be achieved through masking out the LDD implants and can be implemented in standard CMOS processing. 
     In the 1T pixel shown in  FIG. 5A , since the source current must be supplied from the row selection line, variations in current due to variations in signal will create variations in voltage. These variations can distort the measurements. Therefore the row selection line should be low resistance and the driver for that line should also supply a steady source voltage independent of the current load. Where this is not possible, the current can be supplied from the column line and a second selection transistor can be added to form a 2T pixel for common source read out, as shown in  FIG. 10A  described below. Since the gain is limited by the parasitic overlap capacitance, it is expected that the best load to use is a current source implemented with transistors of high output resistance. In this case, relatively constant current will be maintained in all devices since the gain is achieved through capacitor ratios. This makes the 1T configuration feasible since voltage variation at the source is minimal, even with a single row selection line that carries all the current. 
     The pixel in common source readout configuration is shown in  FIG. 5B . The transistor forms an amplifier with negative voltage gain. This negative voltage gain forms a natural feedback loop with the parasitic capacitors in order to control the gain. The open loop gain of the amplifier is A=gm(ro), wherein gm is a transconductance. The value A is typically larger than 100 for a given bias condition and process technology. As shown in  FIG. 5C , the common source equivalent circuit has a feedback capacitance Cgd, a coupling capacitance Cc, and Cgs. 
     Since A is large compared to the loop gain, the negative input terminal may be considered as a virtual ground node and the gain of the circuit may be determined as Vo/Vi=−Cc/Cgd. Since this ratio is known from the analysis or measured values of the source follower configuration, the gain may be determined to be about 6.5. However compared to the source follower, the gain is Vo/Vi=2/(Asf−G). In this example, a gain of 10 is realized over the source follower configuration. A lower bound on this gain is given by assuming that the input capacitance of the source follower is solely due to Cgd and that the Asf is equal to 1. In this case the gain is about 3. Since neither of these conditions is realistic, the gain is expected to always exceed this number. Thus, if the gain of the source follower configuration of a pixel is known, the gain of the common source configuration of this pixel is also known. In addition, the higher the gain, the more sensitive the pixel is. This makes the common source configuration preferable. 
     Flicker noise can be reduced by using a channel doping of the same type as the minority carrier. For example, an NMOS with a n-type implant produces a buried channel transistor. To shift the workfunction of the device, a P+ gate electrode can be used. 
     One-Transistor Pixel Array with Cascoded Column Circuit 
     One derivative of the one-transistor pixel allows for increased programmable gain through a cascoded transistor enabled during readout. 
     Since the gain of the common source readout is limited by the Cgd capacitance, as shown in  FIG. 5B , lowering this capacitance can increase the gain.  FIG. 8  shows a common source pixel with a cascoded row selection device. As shown, a transistor  801  may be added to a common source pixel, e.g., the circuit shown in  FIG. 5B . The gate of the transistor  801  may be coupled to a voltage Vb, and the source of the transistor  801  may be coupled to the drain of the transistor  501 . The output voltage Vo may be taken from the drain of the transistor  801 . The cascode effectively removes the Cgd capacitance from the feedback loop and replaces it with Cds which is much smaller. Gain on the order of the loop gain is then achievable, which may exceed 100. 
     Higher gain and variable gain may be produced in the 1T configuration by bringing the cascode device outside the pixel to the column line.  FIG. 9  shows a one-transistor pixel array with cascoded column circuit. This allows high gain and yet still allows the pixel pitch to be minimized with only 1 transistor per pixel. The shown pixel array is a column having a number of one-transistor pixels (e.g., 500) connected in series, and has a cascode device at the base of the array. The cascode device may comprise a transistor  901 . The gate of the transistor  901  may be coupled to a bias voltage Vb, the source of the transistor  901  may be coupled to the drain of the transistor  501 , and the drain of the transistor  901  may be coupled to a fixed voltage via a current source. The output voltage Vo may be taken from the drain of the transistor  901 . It should be understood that the array may have a number of columns. 
     In this case, the cascode forces the drain of the pixel to remain at a fairly steady voltage over the range of inputs. This causes the pixel to push nearly all of the change in current through the cascode device at the base of the array and into the current load. This reduces the negative feedback from Cds, which would otherwise limit the gain. Given that the current load has infinite output resistance and there is effectively no coupling capacitor to the FG node, the gain of the pixel is now −(gm1rO1+1)gm2rO2, wherein gm1 is the transconductance of the cascode device at the base of the column line and gm2 is the transconductance of the pixel and rO1 and rO2 are the small signal output resistances as seen at the drain. The value of the output resistance is determined by channel length modulation. Longer gate lengths produce higher output resistance because the effect of channel length modulation is minimized. Since this gain is so large, it can be limited and configured by variation of the current source output resistance, which is shown as Radj in  FIG. 9 . This allows for programmable gain at the column level while maintaining a simple 1 transistor pixel. The gain of the pixel is then set by −gm2RL, assuming that the load resistance RL is much smaller than the output resistance of the cascode configuration, where R L  is the adjusted value of Radj. The gain is now configurable and programmable within the range of 1 to 100 or larger. For example, if the bias current is about 5 uA, the transconductance of the pixel is about 50 uA/V, and a load resistance of 20K ohms is needed for gain of 1. A gain of 10 is achieved with a 200K ohm load and gain of 100 with a 2M ohm load. There are many was to implement the effect of the cascode device at the column line. The main purpose of the cascode, as shown in  FIG. 901  as an NMOS transistor, is that the column line is held to a potential that is largely independent of the current level in the pixel. A differential amplifier with high gain can be applied to maintain this condition more precisely. This approach would be called gain-enhanced cascoding. 
     Various layout choices can be made to implement a 1 T and 2T transistor. In order to reduce the size of the pixel the source and drains of adjacent pixels can be shared. In this way a single row selection line enables 2 rows at a time. This reduces the row wiring: two columns are then read out at once for a given column pitch. Such a scheme is shown in  FIGS. 10A and 10B . As shown, a pixel array  1000  comprises transistors  1001 ,  1002 ,  1003  and  1004  in a column. The source of  1001  is coupled to a row line R 2 , and the source of  1004  is coupled to a row line RO. Transistors  1001  and  1002  may form a mirror M 1 , and transistors  1003  and  1004  may form a mirror M 2 . The drain of  1001  and  1002  are coupled to a column line CA, and the drain of  1003  and  1004  are coupled to a column line CB. 
     In one embodiment, the cascoded device is gain-enhanced with a differential amplifier in feedback to control a transistor that maintains a constant voltage on the column line. 
     Two-Transistor Pixel Array 
     In a pixel array, a row selection device may be used for selection and isolation. When a row selection line is activated, the row selection device (a MOSFET) forms a channel due to the gate voltage exceeding a threshold voltage and acts like a switch. When the row selection is deactivated, the channel is diminished. It is important to note that a row selection device never really completely turns “on” or “off”. It only approximates a switch. When the gate is substantially lower than the source of the row selection transistor, good isolation is achieved and the pixel with the active row selection can be read effectively without input from deactivated pixels. With many rows in an array of pixels, it is necessary to achieve a given level of isolation for each row selection device. That is, the requirements for the row selection device depend on the number of rows. 
       FIG. 11  shows a two-transistor (2T) pixel according to one embodiment of the present invention. As shown, the 2T pixel  1100  comprises an ISFET  1101  and a row selection device  1102 . In the pixel  1100 , the source of the ISFET  1101  is coupled to a column line Cb, the drain of the row selection device  1102  is coupled to a column line Ct, and the drain of the ISFET  1101  is coupled to the source of the row selection device  1102 . The gate of the row selection device  1102  is coupled to a row line R. 
     Both ISFET  1101  and the row selection device  1102  are shown as NMOS, but other types of transistors may be used as well. The 2T pixel  1100  is configured as the source follower readout mode, although 2T pixels may be configured as the common source readout mode. 
       FIG. 12A to 12H  illustrate more 2T pixel configurations according to embodiments of the present invention. In these Figures, “BE” stands for “with body effect”, i.e. the ISFET is body-effected because the body terminal is connected to the analog supply voltage or analog ground voltage (depending on whether the ISFET transistor type is p-channel or n-channel MOS). The body effect is eliminated if the body terminal is connected to the source terminal of the transistor. “PR” stands for “PMOS devices in reversed positions”, i.e. the positions of the p-channel ISFET and row selection device in the pixel circuit topology have been reversed (or switched around). “PNR” stands for “PMOS/NMOS devices in reversed positions”, i.e. the positions of the p-channel ISFET and n-channel row selection device in the pixel circuit topology have been reversed (or switched around). 
       FIG. 12A  illustrates a 2T pixel, according to one embodiment of the present invention. As shown, both the ISFET and the row selection device SEL are p-channel MOS transistors, with the source terminal of the ISFET coupled to the drain terminal of the row selection device. The drain terminal of the ISFET is connected to the analog ground voltage and the source terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the row selection device. 
       FIG. 12B  illustrates a 2T pixel, according to one embodiment of the present invention. As shown, both the ISFET and the row selection device SEL are p-channel MOS transistors, with the source terminal of the ISFET connected to the body terminal to eliminate the body effect, and also connected to the drain terminal of the row selection device. The drain terminal of the ISFET is connected to the analog ground voltage and the source terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the row selection device. 
       FIG. 12C  illustrates a 2T pixel, according to one embodiment of the present invention. As shown, both the ISFET and the row selection device SEL are p-channel MOS transistors, with the drain terminal of the ISFET connected to the source terminal of the row selection device. The drain terminal of the row selection device is connected to the analog ground voltage and the source terminal of the ISFET is connected to a current source. The output voltage Vout is read out from the source terminal of the ISFET. 
       FIG. 12D  illustrates a 2T pixel, according to one embodiment of the present invention. As shown, both the ISFET and the row selection device SEL are p-channel MOS transistors, with the drain terminal of the ISFET connected to the source terminal of the row selection device. The drain of the row selection terminal is connected to the analog ground voltage and the source terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the ISFET. The source terminal of the ISFET is connected to the body terminal to eliminate the body effect. 
       FIG. 12E  illustrates a 2T pixel, according to one embodiment of the present invention. As shown, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors respectively, with their source terminals connected together. The drain terminal of the ISFET is connected to the analog ground voltage and the drain of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the drain terminal of the row selection device. 
       FIG. 12F  illustrates a 2T pixel, according to one embodiment of the present invention. As shown, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors respectively, with their source terminals connected together. The drain terminal of the ISFET is connected to the analog ground voltage and the drain of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the drain terminal of the row selection device. The source terminal of the ISFET is connected to the body terminal to eliminate the body effect. 
       FIG. 12G  illustrates a 2T pixel, according to one embodiment of the present invention. As shown, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors respectively, with their drain terminals coupled together. The source terminal of the row selection device is connected to the analog ground voltage and the source terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the ISFET. 
       FIG. 12H  illustrates a 2T pixel, according to one embodiment of the present invention. As shown, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors respectively, with their drain terminals coupled together. The source terminal of the row selection device is connected to the analog ground voltage and the source terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the ISFET. The source terminal of the ISFET is connected to the body terminal to eliminate the body effect. 
       FIGS. 13A to 13D  illustrate common source 2T cell configurations according to embodiments of the present invention. In  FIGS. 13A and 13B , both the ISFET and the row selection device are n-channel MOS transistors, and in  FIGS. 13C and 13D , both the ISFET and the row selection device are p-channel MOS transistors. 
     In  FIG. 13A , the source terminal of the ISFET is connected to the analog ground supply and the drain terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The source terminal of the row selection device and the drain terminal of the ISFET are connected together. The output voltage Vout is read out from the drain terminal of the row selection device. 
     In  FIG. 13B , the source terminal of the row selection device is connected to the analog ground supply and the drain terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The drain terminal of the row selection device and the source terminal of the ISFET are connected together. The output voltage Vout is read out from the drain terminal of the ISFET. 
     In  FIG. 13C , the source terminal of the ISFET is connected to the analog supply voltage, and the drain terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The source terminal of the row selection device and the drain terminal of the ISFET are connected together. The output voltage Vout is read out from the drain terminal of the row selection device. 
     In  FIG. 13D , the source terminal of the row selection device is connected to the analog supply voltage, and the drain terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The source terminal of the ISFET and the drain terminal of the row selection terminal are connected together. The output voltage Vout is read out from the drain terminal of the ISFET. 
       FIG. 14A  shows a 2T pixel array according to one embodiment of the present invention. For illustrative purposes, eight 2T pixels are shown arranged into two columns, though the 2T pixel array  1400  could extend to an array of any size of 2T pixels. Each column pitch contains three column lines cb[ 0 ], ct[ 0 ] and cb[ 1 ], The row lines rs[ 0 ], rs[ 1 ], rs[ 2 ] and rs[ 3 ], connect to all columns in parallel. A row selection device  1401 RS and an ISFET  1401 IS may form one 2T pixel, with the source of  1401 IS connected to the drain of  1401 RS. The source of  1401 RS is connected to the column line cb[ 0 ], and the drain of  1401 IS is connected to the column line ct[ 0 ]. The gate of  1401 RS is connected to the row line rs[ 0 ). This pixel is mirrored in a pixel comprising  1402 IS and  1402 RS, with drains of  1401 IS and  1402 IS connected to the column line ct[ 0 ], and the gate of  1402 RS connected to the row line rs[ 1 ]. The pixel comprising  1402 IS and  1402 RS is mirrored in a pixel comprising  140315  and  1403 RS, with the source of  1402 RS and  1403 RS connected to the row line cb[ 1 ], and the gate of  1403 RS coupled to the row line rs[ 2 ]. The pixel comprising  140315  and  1403 RS is mirrored in a pixel comprising  140415  and  1404 RS, with the drains of  140315  and  140415  connected to the row line ct[ 0 ], the gate of  1404 RS coupled to the row line rs[ 3 ], and the source of  1404 RS coupled to the column line cb[ 0 ]. In the embodiment shown in  FIG. 14 , each of the IS devices is an ISFET and each of the RS devices is a row select device. 
     The right column, including a pixel consisting of  1405 RS and  1405 IS, a pixel consisting of  1406 RS and  1406 IS, a pixel consisting of  1407 RS and  1407 IS, and a pixel consisting of  1408 RS and  140815 , is coupled to column traces cb[ 2 ], ct[ 1 ], and cb[ 3 ] in substantially the same manner as described above. 
       FIGS. 14B and 14C  show a layout for a 2×2 2T pixel array according to an embodiment of the present invention. The 2×2 2T pixel array may be part of the pixel array  1400 .  FIG. 14B  shows that polysilicon gates for  1401 RS,  1401 IS,  1402 RS and  1402 IS may be placed on top of a continuous diffusion layer  1410  and polysilicon gates for  1405 RS,  140515 ,  1406 RS and  140615  may be placed on top of a continuous diffusion layer  1412 . In one embodiment, the continuous diffusion layers  1410  and  1412  may run from the top of the pixel array to the bottom of the pixel array. That is, the diffusion layer may have no discontinuities in the pixel array. 
       FIG. 14C  shows where microwells for ISFETs  1401 IS,  1402 IS,  140515  and  140615  may be placed. The microwells may be used to hold analyte solutions that may be analyzed by the ISFETs. As shown in  FIG. 14C , in one embodiment, the microwells may each have a hexagonal shape and stacked like a honeycomb. Further, in one embodiment, the contact may be placed directly on top of the gate structure. That is, the ISFETs may have a contact landed on polysilicon gate over thin oxide. 
     The pixel array  1400  has high density because of continuous diffusion, shared contacts, mirrored pixels, and one ct (column top) line and 2 cb (column bottom) line per physical column. A global bulk contact may be implemented by using a P+ wafer with P− epitaxy region. 
     The arrangement of pixel array  1400  provides for high speed operation. Row lines rs[ 0 ] and rs[ 1 ] are selected together and readout through cb[ 0 ] and cb[ 1 ]. This leads to a 4 times faster readout due to twice the number of pixels enabled for a single readout and half the parasitic load of a continuous array, allowing each column to settle twice as fast. In an embodiment, the full array is separated into a top half and a bottom half. This leads to another 4 times faster readout time due to twice the number of pixels readout at a time (both out the top and the bottom) and half the parasitic load of a continuous array. Thus, the total increase in speed over a single row selected continuous array is 16 times. 
     In an embodiment, both top and bottom halves of the pixel array may be enabled at the same time during readout. This can allow a multiplexing of readout between the top half and the bottom half. For example, one half can be doing a “wash” (e.g., flushing out reactants from the wells over the pixel devices) and the other half can be performing the readout. Once the other half is read, the readout for the two halves is switched. 
     In an embodiment, a 2T pixel design can incorporate two chemically-sensitive transistors (e.g., ISFETs) rather than one chemically-sensitive transistor and one row select device as described with respect to  FIGS. 11-14 . Both chemically-sensitive transistors, or ISFETs, can be NMOS or PMOS device and configured in a source follower or common source readout mode. Possible uses of such a 2T pixel may be where the first chemically-sensitive transistor has a different sensitivity to a particular analyte to that of the second chemically-sensitive transistor, allowing a local and in-pixel differential measurement to be made. Alternatively, both chemically-sensitive transistors may have the same sensitivity to a particular analyte, allowing a local and in-pixel average measurement to be made. These are among two examples of potential uses for this embodiment, and based on the description herein, a person of ordinary skill in the art will recognize other uses for the 2T pixel design that incorporate two chemically-sensitive transistors (e.g., ISFETs). 
     In one embodiment, a column circuit allows column lines to be swapped to a sampling circuit such that either source-side or drain-side row selection can be made in either source follower mode or common source mode. 
     Capacitive Charge Pump 
     One or more charge pumps may be used to amplify the output voltage from a chemically-sensitive pixel that comprises one or more transistors, such as those described above. 
     One or more charge pumps may be used to amplify the output voltage from a chemically-sensitive pixel that comprises one or more transistors, such as those described above. 
       FIG. 15  shows a capacitive charge pump with a two times voltage gain according to one embodiment of the present invention. A charge pump  1500  may comprise φ1 switches  1501 ,  1502 ,  1503  and  1504 , φ2 switches  1505  and  1506 , and capacitors  1507  and  1508 . Vref1 and Vref2 are set to obtain the desired DC offset of the output signal, and both are chosen to avoid saturation of the output during the boost phase. The operation of the charge pump may be controlled by timing signals, which may be provided by a timing circuit. 
     At time t 0 , all switches are off. 
     At time t 1 , φ1 switches  1501 ,  1502 ,  1503  and  1504  are turned on. The track phase may start. An input voltage Vin, which may be from an ion sensitive pixel, may start to charge capacitors  1507  and  1508 . 
     At time t 2 , φ1 switches  1501 ,  1502 ,  1503  and  1504  are turned off, and capacitors  1507  and  1508  are charged to Vin−Vref1. 
     At time t 3 , φ2 switches  1505  and  1506  are turned on, while φ1 switches  1501 ,  1502 ,  1503  and  1504  remain off. The boost phase may start. The capacitor  1507  may start to discharge through the capacitor  1508 . Since the capacitors are in parallel during the track phase and in series during the boost phase, and the total capacitance is halved during the boost phase while the total charge remains fixed, the voltage over the total capacitance must double, making Vout approximately two times Vin. 
     A source follower SF may be used to decouple the gain circuit from the following stage. 
     The charge pump  1500  may provide a two times gain without a noisy amplifier to provide a virtual ground. 
       FIG. 16  shows a charge pump according to an embodiment of the present invention. 
     At time t 0 , all switches are off. 
     At time t 1 , φ1 switches  1501 ,  1502 ,  1503 ,  1504 ,  1601  and  1602  are turned on. The track phase may start. An input voltage Vin, which may be from an ion sensitive pixel, may start to charge capacitors  1507 ,  1508  and  1604 . 
     At time t 2 , φ1 switches  1501 ,  1502 ,  1503 ,  1504 ,  1601  and  1602  are turned off, and capacitors  1507 ,  1508  and  1604  are charged to Vin−Vref1. 
     At time t 3 , φ2 switches  1505  and  1603  are turned on, while φ1 switches  1501 ,  1502 ,  1503 ,  1504 ,  1601  and  1602  remain off. The boost phase may start. The capacitor  1507  may start to discharge through the capacitors  1508  and  1604 , and the capacitor  1508  may start to discharge through the capacitor  1604 . Since the capacitors are in parallel during the track phase and in series during the boost phase, and the total capacitance is divided by three during the boost phase while the total charge remains fixed, the voltage over the total capacitance must triple, making Vout approximately three times Vin. 
       FIG. 17  shows an embodiment of a charge pump according to an embodiment of the present invention. Two charge pumps  1500  shown in  FIG. 15  are connected in series, enabling gain pipelining and amplifying input voltage Vin by a factor of four. 
     Additional series charge pumps can be added to increase the gain further. In a multi-stage charge pump, the capacitor values do not have to be the same size from stage to stage. It can be observed that the total area consumed by capacitors increases with the square of the gain. Although this feature may, in some cases, be undesirable with respect to area usage, power consumption, and throughput, the charge pump can be used without these penalties when the total noise produced by the ion sensitive pixel and associated fluidic noise is larger than the charge pump KT/C noise when a reasonable capacitor size is used. 
       FIG. 18  shows an embodiment of a charge pump according to an embodiment of the present invention. A feedback path including a source follower SFP and a switch φfb is added to the charge pump  1500 , feeding the output Vout back to the input of the charge pump. 
     At time t 1 , all switches are off. 
     At time t 1 , a switch φsp is on, providing an input voltage Vin to the input of the charge pump  1500 . 
     From time t 2  to time t 5 , the charge pump  1500  operates to push the output voltage Vout to 2(Vin−Vref1), as described before with reference to  FIG. 15 . 
     From time t 6  to t 7 , the switch φfb is on, feeding the output voltage 2(Vin−Vref1). back to the input of the charge pump  1500 , and the first cycle ends. 
     During the second cycle, the charge pump  1500  amplifies the output voltage by 2(2(Vin−Vref1)). The process repeats, with the output being amplified during each cycle. 
     CCD-Based Multi-Transistor Active Pixel Sensor Array 
     An ion sensitive MOS electrode is charge coupled to adjacent electrodes to facilitate both confinement and isolation of carriers. Measurements of ion concentration are made by discrete charge packets produced at each pixel and confined by potential barriers and wells. The ion sensitive electrode can act as either a barrier level or as a potential well. Working in the charge domain provides several benefits, including but not limited to: 1) increased signal level and improved signal to noise through the accumulation of multiple charge packets within each pixel, 2) better threshold matching of the MOS sensing and reference structures, 3) reduction in flicker noise, and 4) global-snap shot operation. 
     A floating electrode is used to detect ions in close proximity to the electrode. The electrode is charge coupled to other electrodes and to other transistors to form a pixel that can be placed into an array for addressable readout. It is possible to obtain gain by accumulating charge into another electrode or onto a floating diffusion (FD) node or directly onto the column line. It is desirable to achieve both a reduction in pixel size as well as increase in signal level. To reduce pixel size, ancillary transistors may be eliminated and a charge storage node with certain activation and deactivation sequences may be used. 
     The ion sensitive (IS) accumulation pixel contains some of the following concepts: 
     1. Electrodes are charge coupled to the IS electrode; 
     2. A source of carriers (electrons or holes) for charge packets; 
     3. A reference electrode to act as a barrier or a well for the charge packets; 
     4. A floating diffusion node for charge to voltage conversion; 
     5. Ancillary transistors to provide buffering and isolation for addressable readout; and 
     6. Sequences to eliminate some or all ancillary transistors depending on the application. 
     The basic IS accumulation pixel is shown in  FIG. 19 . Charge accumulation can occur either locally at the time of readout or globally during a separate integration time. The embodiment shown in  FIG. 19  is a three transistor three electrode (3T3E) pixel. The three transistors include a reset transistor RT, a source follower  1901  and a row selection transistor RS, and the three electrodes include an electrode VS, an electrode VR, and an ion sensitive electrode  1902 . The pixel also includes a transfer gate TX. It is also possible to configure the IS accumulation pixel with additional elements to allow simultaneous accumulation and readout. This can be done, for example, by adding 2 more electrodes to pipeline the process. In the basic configuration, charge is accumulated onto the floating diffusion node that is connected to the source of the reset (RT) control gate. In a rolling shutter operation, the floating diffusion (FD) is reset to CD=VDD. The row is then selected and readout through the source follower enabled by row selection (RS). Next, charge is accumulated onto the FD node which discharged the parasitic capacitor. A second sample is then taken. The difference between the samples represents the ion concentration. The samples are correlated and taken relatively quickly in time. Therefore, the thermal noise of the readout circuit is eliminated and the 1/f noise is reduced. To operate in a global shutter mode, all FD nodes are simultaneously reset to VDD. Then charge is accumulated on each isolated FD node. After accumulation, each row is selected by enabling the RS gate. The signal value is readout on the column line with a load on the source follower. Next the pixel is reset and sampled again. The difference between the samples represents the ion concentration. The 1/f noise is reduced through the double sampling. However, the thermal reset noise is not eliminated because the reset value is uncorrelated in time. The thermal noise can be reduced by half the power by following the reset operation with a subthreshold reset before sampling. In general, the thermal noise is low compared to the signal due to the charge accumulation. A correlated reset scheme with global shutter is available in other configurations. 
     The basic charge accumulation scheme is shown in  FIG. 20  using the surface potential diagrams. Only the electrodes are shown since the transistors are only used for readout. In each of these sequences, increasing potential is pointing down as is conventional to show potential wells containing electrons. Four cycles of charge accumulation are shown in  FIG. 20A-P . First, all charge is removed from the channel under the IS electrode and the channels are fully depleted using a high potential on FD (A). Next, the TX gate transitions to a low potential which creates the confinement barrier (B). A fill and spill operation is used to produce a charge packet proportional to the ion concentration at the IS electrode (C-D). In the next cycle, this charge packet is transferred to the FD node which discharges due to the electrons. The diagram shows electrons accumulating on the FD node, but the voltage is actually decreasing. After many cycles, as shown in  FIG. 20E-P , the signal to noise ratio is improved and the signal can be read out with gain. Hundreds to millions of cycles can be used to amplify the signal. 
     In alternative embodiments, the order of electrodes may be switched, and/or the IS electrode may be used as the barrier rather than the well. Transistors may be added to this accumulation line to enable a large array of pixels. The ancillary transistors are used to increase speed. However, it should be noted that no transistors are necessary to enable a full pixel array of the accumulation line. Instead, an array can be partitioned such that no transistors are needed. In an embodiment, the FD nodes are connected to the column line. Before a pixel is read out, the column line is reset to VDD. Then a row is selected by accumulating charge for that row directly onto the column line. After many cycles, the column discharges to a value directly proportional to the ion concentration. Since the capacitance of the column line depends on the total number of rows, the amount of accumulation required, depends on the number of rows. The array can be partitioned into sub arrays to make timing scalable. For example, every 100 rows can contain a local source follower buffer that is then connected to a global array. This hierarchical approach can be used in general with all readout schemes to make massive arrays of pixels with fast readout. 
     Due to the thermal activity of carriers, charge packets cannot be generated without noise. Each fill and spill operation produces charge error proportional to KTC (thermal noise in the floating diffusion capacitor), where C is equal to Cox times the area of the ion sensitive electrode. During the fill operation charge can flow freely between the source of electrons and the confinement well. However, during the spill operation, the device enters the subthreshold mode and carriers move by diffusion, mainly in only one direction, which results in half of the thermal noise of a resistive channel. The total noise in electrons for each charge packet is therefore sqrt(KTC/2)/q where q represents the charge of one electron in coulombs (1.6×10e-19). The signal in electrons is equal to VC/q. The signal to noise ratio after n cycles is equal to V*sqrt(2nC/KT). Note that the signal to noise ratio improves by the square root of the number of cycles of accumulation. For small signal levels, the amount of accumulation will be limited to the threshold mismatch between the VR reference electrode and the ion sensitive electrode. Since there is a reference electrode in every pixel and the electrodes are charge coupled, the relative threshold mismatch between each pair of electrodes is small. Assuming, this difference is about 1 mV, over 1000 accumulation cycles should be feasible, thereby improving the signal to noise by more than 30 times. By way of example, if the signal is 1 mV and the electrode area is 1 square micron with Cox=5 fF/um{circumflex over ( )}2, the signal to noise ratio after 1000 cycles is 50 to 1. Since the signal level then reaches 1 V, it is expected that no other noise source is relevant. For clarity, the dominant noise is simply the charge packet thermal noise which is well known. 
       FIGS. 21 and 22  show the IS accumulation pixel with only 2 transistors. The selection transistor is eliminated by using a deactivation sequence after a row is read out. To deactivate, the FD node is discharged, which reduces the potential of the FD node and disables the source follower for that row. The surface potential diagrams for the pixel of  FIG. 22  are shown in  FIG. 23 . 
       FIG. 24  shows the IS accumulation pixel with 2 transistors and 4 electrodes. This pixel produces the fill and spill charge packets and readout all at the same FD node. The 4th electrode allows global shutter operation and correlated double sampling. For faster readout, single sampling can be used if charge accumulation sufficiently reduces the 1/f noise contribution.  FIG. 25  shows the surface potential diagrams for the basic operation of the pixel of  FIG. 24 . 
       FIG. 26  shows an IS accumulation pixel with 1 transistor and 3 electrodes. The channel can be depleted and supplied from the same node. This pixel depends on charge coupling, and signal range is lower than signal range for the other pixels. 
     Several design permutations are available depending on the desired mode of operation. The CCD channels are surface mode and are built in standard CMOS technology preferably below 0.13 um. Extra implants can be added to avoid surface trapping and other defects. A channel stop and channel can be formed from donor and acceptor impurity implants. The channel can be made of multiple implants to produce a potential profile optimal for the mode of operation. 
       FIG. 27  shows an embodiment of a three transistor (3T) active pixel sensor. The three transistors are a reset transistor  2701 , a source follower  2702  and a row selection switch  2703 . The reset transistor  2701  has a gate controlled by a reset signal RST, a source coupled to the floating diffusion (FD) of a pixel, and a drain connected to a fixed voltage. The source follower  2702  has its gate connected to the source of the reset transistor  2701 , and its drain connected to a fixed voltage. A row selection transistor  2703  has its gate connected to a row line, its drain connected to a fixed voltage and its source connected to a column. Other electrodes interacting with the pixel includes a transfer gate TG, an ion selective electrode ISE, an input control gate ICG, and an input diffusion ID. These three elements form charge coupled electrodes that are operated in an identical way to VS, VR, and TX in  FIG. 19 . 
       FIG. 28  shows an alternate embodiment of a 3T active pixel sensor. The difference between the sensor in  FIG. 28  and the sensor shown in  FIG. 27  is that the sensor  2800  has a second input control gate ICG 2 , which allows more control over the potential barrier near the ion-sensitive electrode. 
       FIG. 29  shows an embodiment of a 3T active pixel sensor with a sample and hold circuit, which may be used to eliminate signal variations. As shown, the gate of the row selection transistor  2703  is controlled by a RowSelm signal provided by a row selection shift register. The source of the row selection transistor  2703  is coupled to a current sink ISink  2902  and a column buffer  2903 . The current sink ISink  2902  may be biased by a voltage VB 1  and the column buffer, which may be an amplifier, may be biased by a voltage VB 2 . 
     The sample and hold circuit  2901  may include a switch SH, a switch CAL, a capacitor Csh, and an amplifier Amp. The switch SH&#39;s input is coupled to the output of the column buffer  2903 , and its output is coupled to a voltage VREF through the switch CAL, the upper part of the capacitor Csh, and the input of the amplifier Amp. The amplifier is biased by a voltage VB 2 . The output of the amplifier is coupled to a switch  2904  controlled by a signal ColSeln from a column selection shift register. The output of the switch  2904  is buffered by an output buffer  2905  before reaching the output terminal Vout. The output buffer is biased by a voltage VB 3 . 
       FIG. 30  shows an embodiment of a 3T active pixel sensor with a correlated double sampling circuit. The most significant difference between the sensor in  FIG. 30  and that in  FIG. 29  is that the former uses a correlated double sampling circuit  3001  to measure the signal from the column buffer  2903 . An amplifier in the correlated double sampling circuit  3001  receives at its first input the output of the column buffer  2903  via a switch SH, and a capacitor Cin. The amplifier receives a reference voltage VREF at its second input, and is biased by the voltage VB 2 . A reset switch RST and a capacitor Cf are coupled in parallel with the amplifier. 
       FIG. 31  shows an embodiment of a 2.5T active pixel sensor used for a four pixel array. Each of the pixels has its own transfer transistor TX 1 , TX 2 , TX 3  and TX 4  and its own reset transistor. The drain of each transfer transistor is coupled to the source of the reset transistor in the same pixel, and the source of each transfer transistor is coupled to the gate of the source follower. 
       FIG. 32  shows an embodiment of a 1.75T active pixel sensor for a four pixel array. Each of the pixels has its own transfer transistor. The source of each transfer transistor is coupled to the floating diffusion of the same pixel, and the drain of each transfer transistor is coupled to the drain of the reset transistor RST of the sensor. 
     Array Column Integrator 
     The described embodiments may provide a chemical detection circuit with an improved signal-to-noise ratio. The chemical detection circuit may include a current source, a chemical detection pixel, an amplifier and a capacitor. The chemical detection pixel may comprise a chemically-sensitive transistor that may have first and second terminals and a row-select switch connected between the current source and chemically-sensitive transistor. The amplifier may have a first input and a second input, with the first input connected to an output of the chemically-sensitive transistor via a switch and the second input connected to an offset voltage. The capacitor may be connected between an output of the amplifier and the first input of the amplifier. The capacitor and amplifier may form an integrator and may be shared by a column of chemical detection pixels. 
     Some embodiments may also provide a chemical detection circuit with an improved signal-to-noise ratio. The chemical detection circuit may include a plurality of columns of chemical detection pixels. Each column of chemical detection pixels may comprise a current source, a plurality of chemical detection pixels, an amplifier and a capacitor. Each chemical detection pixel may comprise a chemical-sensitive transistor that may have first and second terminals and a row-select switch connected between the current source and chemically-sensitive transistor. The amplifier may have a first input and a second input, with the first input connected to an output of each chemically-sensitive transistor via a switch and the second input connected to an offset voltage. The capacitor may be connected between an output of the amplifier and the first input of the amplifier. The capacitor and amplifier may form an integrator that is shared by a column of chemical detection pixels. 
     Other embodiments may provide a method to generate an output signal from a chemical detection circuit. The method may comprise selecting a chemical detection pixel from a column of chemical detection pixels for readout, integrating a readout current from the chemical detection pixel to an integrator, and reading out an output voltage of the integrator. 
       FIG. 33  illustrates a block diagram of a chemical detection circuit  3300  according to an embodiment of the present invention. The chemical detection circuit  3300  may comprise a plurality of chemical detection pixels  3302 . 1 - 3302 .N, a current source  3308 , an amplifier  3310 , an offset voltage V sd    3314 , a capacitor C int    3312 , and three switches  3316 ,  3318  and  3320 . Each chemical detection pixel (e.g.,  3302 . 1 , . . . , or  3302 .N) may comprise a chemically-sensitive transistor (e.g.,  3304 . 1 , . . . , or  3304 .N, respectively) and a row-select switch (e.g.,  3306 . 1 , . . . , or  3306 .N, respectively). The amplifier  3310  may have a first input terminal coupled to an output of the current source  3308  and a second input terminal coupled to the offset voltage V sd    3314 . The capacitor C int    3312  may have a first side coupled to the first input terminal of the amplifier  3310  and a second side coupled to an output terminal of the amplifier  3310  via the switch  3318 . The switch  3316  may be coupled between the first side of the capacitor C int    3312  and the output terminal of the amplifier  3310 . The switch  3320  may be coupled between the second side of the capacitor C int    3312  and ground. In one embodiment, the plurality of chemical detection pixels  3302 . 1  to  3302 .N may form a column of chemical detection pixels. The capacitor C int    3312  may be configured as a negative feed back loop for the amplifier  3310  and thus, the capacitor C int    3312  and amplifier  3310  may form an integrator for the column of chemical detection pixels. In one embodiment, the integrator may be shared by all chemical detection pixels of the column and may be referred to as a column integrator. 
     Each chemically-sensitive transistor may have a gate terminal that may be covered by a passivation layer. The gate terminal may have a floating gate structure sandwiched between a gate oxide and a passivation layer (e.g., floating gate G in  FIG. 2 ). During operation, the passivation layer may be exposed to an analyte solution to be analyzed. Each chemically-sensitive transistor  3304 . 1 ˜ 3304 .N may further have a first terminal connected to a first side of a respective row-select switch  3306 . 1 ˜ 3306 .N and a second terminal connected to ground. For example, as shown in  FIG. 33 , the transistor  3304 . 1  may be a PMOS with a first terminal (e.g., the source) connected to a first side of the row-select switch  3306 . 1  and a second side (e.g., the drain) connected to ground. Each row-select switch (e.g.,  3306 . 1 , . . . , or  3306 .N) of each chemical detection pixel may have a second side connected to the current source  3308 . The second side of each row-select switch may also be coupled to the first input of the amplifier  3310 . 
     In one embodiment, the chemical detection circuit  3300  may be configured so that each of the chemically-sensitive transistors (e.g.,  3304 . 1 , . . . , or  3304 .N) may work in a current-mode. That is, each of the chemically-sensitive transistors may work as a transconductance amplifier. The ion-concentration of analyte being measured by the chemically-sensitive transistor may be detected by a current output. In one embodiment, each chemically-sensitive transistor  3304 . 1  to  3304 .N may be an ion-sensitive field effect transistor (ISFET) and each row-select switch  3306 . 1  to  3306 .N may also be a transistor. 
     During operation, when one chemical detection pixel is selected, the corresponding row-select switch may be closed. For example, as shown in  FIG. 33 , the chemical detection pixel  3302 . 1  may be selected, and thus the row-select switch  3306 . 1  may be closed. The current source  3308  may provide a DC bias current I dc  to the selected chemically-sensitive transistor  3304 . 1 . The signal current I sig  resulting from gate voltage change of the chemically-sensitive transistor  3304 . 1  may be integrated onto the capacitor C int    3312  and an output signal of the amplifier  3310  may be read out as V out . The offset voltage V sd    3314  to the second input of the amplifier  3310  may provide the source-to-drain voltage V sd  for the chemically-sensitive transistor to operate. 
     Each measurement operation may comprise two phases. The first phase of operation may be an integration phase and the second phase of operation may be a clear phase to clear charges. During the first phase of operation, the switch  3318  may be closed and switches  3316  and  3320  may be left open. After the output signal Vout is read out, the operation may enter the second phase, during which the switches  3316  and  3320  may be closed and the switch  3318  may be left open to clear out the charges accumulated on the capacitor C int    3312 . In one embodiment, a correlated-double-sampling (CDS) scheme may be implemented by closing switch  3320  during the second phase. This may allow the inherent offset voltage of the amplifier  3310  to be stored on the capacitor C int    3312 . 
     In one embodiment, the current source  3308  may be a programmable current source attached to each column to provide a DC bias current I dc , which may be relatively large. In this configuration, the bias current I dc  will not integrate onto the capacitor C int    3312  and thus the integrator may avoid premature saturation. Amplification level may be derived from the C int  value and duration of integration. 
     Further, in one embodiment, the output signal Vout may be converted into a digital signal by an ADC. For example, the charging signal current I sig  may be digitized using a single-slope integration ADC such that a counter may increment (counting a number) until the integrator output voltage crosses some threshold as defined by a comparator. When the single-slope integration ADC is used, calibration may be performed to determine an absolute value of the capacitor C int    3312 . Alternatively, a “dual-slope integrating ADC” may be used that uses a fixed integration period followed by a variable discharge period. In other embodiments, the output signal Vout may be converted into a digital signal by other known analog-to-digital conversion techniques. 
     In one embodiment, integration of current response of the chemically-sensitive transistor may provide a better signal-to-noise ratio (SNR) than measurement of instantaneous voltage output of a chemically-sensitive transistor. 
     In one or more embodiments, it may be hard to completely cancel the DC current of the chemical sensitive transistor using the current source  3308 . Therefore, in one embodiment, the size of the capacitor may be limited to a certain size. In another embodiment, the duration of integration time may be limited to, for example, 1 μs. If the integration time is limited, a dual-slope ADC with a much slower discharge phase may be used to convert the output voltage Vout to a digital output. 
       FIG. 34  illustrates a block diagram of another chemical detection circuit  3400  according to an embodiment of the present invention. The chemical detection circuit  3400  may comprise a plurality of chemical detection pixels  3402 . 1 - 3402 .N, a current source  3408 , an amplifier  3410 , a resistor  3424 , an offset voltage V set    3414 , a capacitor C int    3412 , and three switches  3416 ,  3418  and  3420 . Each chemical detection pixel (e.g.,  3402 . 1 , . . . , or  3402 .N) may comprise a chemically-sensitive transistor (e.g.,  3404 . 1 , . . . , or  3404 .N, respectively), a row-select switch (e.g.,  3406 . 1 , . . . , or  3406 .N, respectively) and an output switch (e.g.,  3422 . 1 , . . . ,  3422 .N). The amplifier  3410  may have a first input terminal coupled to the output switches of the chemical detection pixels so that when a chemical detection pixel is selected, its output switch may be closed to generate an output signal for the first input terminal of the amplifier  3410 . The amplifier  3410  may also have a second input terminal coupled to the offset voltage V set    3414 . The capacitor Cant  3412  may have a first side coupled to the first input terminal of the amplifier  3410  and a second side coupled to an output terminal of the amplifier  3410  via the switch  3418 . The switch  3416  may be coupled between the first side of the capacitor C int    3412  and the output terminal of the amplifier  3410 . The switch  3420  may be coupled between the second side of the capacitor Cant  3412  and ground. In one embodiment, the plurality of chemical detection pixels  3402 . 1  to  3402 .N may form a column of chemical detection pixels. The capacitor C int    3412  may be configured as a negative feedback loop for the amplifier  3410  and thus, the capacitor C int    3412  and amplifier  3410  may form an integrator for the column of chemical detection pixels. The integrator may be shared by all chemical detection pixels of the column and may be referred to as a column integrator. 
     Each chemically-sensitive transistor  3404 . 1 ˜ 3404 .N may have a gate structure similar to that of the chemically-sensitive transistor  3302 . 1 ˜ 3302 .N. Each chemically-sensitive transistor  3404 . 1 ˜ 3404 .N may further have a first terminal connected to a first side of a respective row-select switch  3406 . 1 ˜ 3406 .N and a first side of a respective output switch  3422 . 1 ˜ 3422 .N. Each chemically-sensitive transistor  3404 . 1 ˜ 3404 .N may also have a second terminal connected to ground. For example, as shown in  FIG. 34 , the transistor  3404 . 1  may be a PMOS with a first terminal (e.g., the source) connected to a first side of the row-select switch  3406 . 1  and a first side of the output switch  3422 . 1 . Further, the transistor  3404 . 1  may also have a second side (e.g., the drain) connected to ground. Each row-select switch (e.g.,  3406 . 1 , . . . , or  3406 .N) of each chemical detection pixel  3402 . 1 ˜ 3402 .N may have a second side connected to the current source  3408 . The second side of each output switch  3422 . 1 ˜ 3422 .N may also be coupled to the first input of the amplifier  3410  via the resistor  3424 . 
     In one embodiment, the chemical detection circuit  3400  may be configured that each of the chemically-sensitive transistors (e.g.,  3404 . 1 , . . . , or  3404 .N) may work in a voltage-mode. That is, during operation, each of the chemically-sensitive transistors may work as a voltage amplifier. The ion concentration of analyte being measured by the chemically-sensitive transistor may be detected by a voltage level at the output. When one chemical detection pixel is selected, the corresponding row-select and output switches may be closed. The offset voltage V set  may set an appropriate voltage between the virtual ground (e.g., the first terminal or negative terminal) of the amplifier  3410  and the output of the selected chemically-sensitive transistor. For example, as shown in  FIG. 34 , the chemical detection pixel  3402 . 1  may be selected, and thus the row-select switch  3406 . 1  and output switch  3422 . 1  may be closed. The current source  3408  may provide a current I ss  to the selected chemically-sensitive transistor  3404 . 1 . The resistor  3424  may be used to convert an output voltage at the selected chemically-sensitive transistor to a charging current I is  to be integrated onto the capacitor C int    3412 . An output signal of the amplifier  3410  may be read out as V out . 
     Similar to operation of the chemical detection circuit  3300 , the operation of the chemical detection circuit  3400  may have an integration phase and a clear phase to clear charges. During the integration phase, the switch  3420  may be closed and switches  3416  and  3420  may be left open. After the output signal Vout is read out, the operation may enter the second phase, during which the switches  3416  and  3420  may be closed and the switch  3418  may be left open to clear out the charges accumulated on the capacitor C int    3412 . 
     In one embodiment, each chemically-sensitive transistor  3404 . 1  to  3404 .N may be an ion-sensitive field effect transistor (ISFET) and each row-select switch  3406 . 1  to  3406 .N may be a transistor. Each output switch  3422 . 1  to  3422 .N may also be a transistor. 
     Further, similar to the chemical detection circuit  3300 , the output signal Vout of the chemical detection circuit  3400  may be converted into a digital signal by an ADC. For example, the charging current I is  may be digitized using a single-slope integration ADC or a dual-slope integrating ADC. In other embodiments, the output signal Vout of the chemical detection circuit  3400  may be converted into a digital signal by other known analog-to-digital (ND) conversion techniques. 
     Moreover, in one embodiment, the resistance of the resistor  3424  may dominate over the resistance of the series row-select switch (e.g.,  3406 . 1  to  3406 .N) to limit the current to be integrated onto the capacitor C int    3412 . 
       FIG. 35  illustrates a block diagram of yet another chemical detection circuit  3500  according to yet another embodiment of the present invention. The chemical detection circuit  3500  may have a pass transistor  3524  that replaces the resistor  3424  of the chemical detection circuit  3400 . Other than the transistor  3524 , other parts of the chemical detection circuit  3500  may be identical to the chemical detection circuit  3400 . The pass transistor  3524  may have a gate voltage V bias  tied to some process-, voltage-, and temperature (PVT) independent bias circuit. The on-resistance of this pass transistor  3524  may be designed to dominate over the resistance of the series row-select switch in the pixel. 
       FIG. 36  illustrates a process  3600  for generating an output of a chemical detection circuit according to an embodiment of the present invention. The process  3600  may be performed by the chemical detection circuits  3300 ,  3400  and  3500  as described above with respect to  FIGS. 33-35 . The process  3600  may start at step  3602 , at which a chemical detection pixel may be selected for readout. As shown in  FIG. 33 , for example, when the chemical detection pixel  3302 . 1  is selected, the row-select switch  3306 . 1  may be closed. Alternatively, as shown in  FIGS. 34 and 35 , for example, when the chemical detection pixel  3402 . 1  is selected, the row-select switch  3406 . 1  and the output switch  3422 . 1  may be closed. 
     Then the process  3600  may proceed to step  3604 . At step  3604 , the process  3600  may integrate a readout current from the chemical detection pixel to an integrator. As described above, the readout current may be caused by a voltage change at a gate terminal of the selected chemical detection pixel. In one embodiment, as shown in  FIG. 33 , the chemical detection pixel may work in a current mode, the selected chemical detection pixel may supply a readout current to charge a capacitor of the integrator. In another embodiment, as shown in  FIGS. 34 and 35 , the chemical detection pixel may work in a voltage mode and an output voltage from the chemical detection pixel may be converted by a resistor or a pass transistor to a current to charge the capacitor of the integrator. 
     Then, at step  3506 , the process  3600  may read out an output voltage of the integrator. As described above, output voltage of the integrator (Vout at the output of the amplifier  3310  or output of the amplifier  3410 ) may have a better signal-to-noise ratio (SNR) for detection of ion concentration of the analyte being analyzed by the chemical detection pixel than instantaneous voltage measurement. 
     Although in the above description, the chemically-sensitive transistors may be described as PMOS devices, they may also be implemented as NMOS devices in one embodiment. Further, the switches (e.g., row-selected switches, output switches, charge clear switches) may be implemented in either PMOS or NMOS transistors in an embodiment. 
     Array Configuration and Readout Scheme 
     The described embodiments may provide a chemical detection circuit that may comprise a plurality of first output circuits at a first side and a plurality of second output circuits at a second and opposite side of the chemical detection circuit. The chemical detection circuit may further comprise a plurality of tiles of pixels each placed between respective pairs of first and second output circuits. Each tile array may include four quadrants of pixels. Each quadrant may have columns with designated first columns interleaved with second columns. Each first column may be connected to a respective first output circuit in first and second quadrants, and to a respective second output circuit in third and fourth quadrants. Each second column may be connected to a respective second output circuit in first and second quadrants, and to a respective first output circuit in third and fourth quadrants. 
     Some embodiments may also provide a chemical detection system that may comprise a motherboard having at least one central processing unit, an output device coupled to the mother board, and a chemical detection reader board connected to the mother board. The chemical detection reader board may have a chemical detection circuit that may comprise a plurality of first output circuits at a first side and a plurality of second output circuits at a second and opposite side of the chemical detection circuit. The chemical detection circuit may further comprise a plurality of tiles of pixels each placed between respective pairs of first and second output circuits. Each tile array may include four quadrants of pixels. Each quadrant may have columns with designated first columns interleaved with second columns. Each first column may be connected to a respective first output circuit in first and second quadrants, and to a respective second output circuit in third and fourth quadrants. Each second column may be connected to a respective second output circuit in first and second quadrants, and to a respective first output circuit in third and fourth quadrants. 
     Other embodiments may provide a method to read out data from a chemical detection circuit. The method may comprise selecting a first quadrant of a tile to read out data, selecting one group of first columns and one group of second columns, reading out data of the group of first columns from a first set of output pins located at a first side of the chemical detection circuit, reading out data of the group of second columns from a second set of output pins located at a second side of the chemical detection circuit, and repeating selection and data readouts for next groups of first columns and second columns till all remaining columns of the first quadrant are read out. 
       FIG. 37  illustrates a block diagram of a chemical detection circuit  3700  according to an embodiment of the present invention. The chemical detection circuit  3700  may comprise a plurality of tiles of pixels  3702 . 1 - 3702 .N and  3704 . 1 - 3704 .N, output circuits  3706  and  3708 , control logic and digital interface  3710 , and bias circuit and diagnostic output logic  3712 . Each tile  3702 . 1 - 3702 .N and  3704 . 1 - 3704 .N may include pixels formed in columns with each column containing many rows. For example, each tile may contain 6848 columns×11136 rows of pixels. The tiles  3702 . 1 - 3702 .N may form a slice (e.g., a top slice) and the tiles  3704 . 1 - 3704 .N may form another slice (e.g., a bottom slice). The plurality of tiles  3702 . 1 - 3702 .N and  3704 . 1 - 3704 .N may form a conglomerate pixel array. The output circuits  3706  and  3708  may be placed at two opposite sides of the tiles (e.g., top and bottom). The output circuits  3706  and  3708 , control logic and digital interface  3710 , and bias circuit and diagnostic output logic  3712  may each contain a plurality of pins for input and output data for the chemical detection circuit  3700 . In one embodiment, the chemical detection circuit  3700  may be formed on an integrated circuit chip. Further, in one embodiment, the output circuits  3706  and  3708  may include analog-to-digital converters (ADCs) to generate digital outputs. Moreover, in one embodiment, two slices may be operated independently and exposed to a different analyte. For example, while data is being read out for the top tile, the bottom tile may be flushed out of fluid for another round of test. This may be used in conjunction with a dual-channel flow cell (e.g., mounted on top of the chemical detection circuit  3700 ) that two different flow channels may carry out different tasks at the same time. 
     Pixels of each tile  3702 . 1 - 3702 .N and  3704 . 1 - 3704 .N may be divided into four quadrants and data generated at each pixel may be read out from either the top or the bottom. An exemplary configuration of the pixels within a pair of tiles is shown in  FIG. 38A . 
       FIG. 38A  illustrates a block diagram  3800  of components of the chemical detection circuit  3700  (of  FIG. 37 ) according to an embodiment of the present invention. As shown in  FIG. 38A , the tile  3702 . 1  may comprise four quadrants: top left (TL) quadrant  3802 , top right (TR) quadrant  3804 , bottom left (BL) quadrant  3806 , bottom right (BR) quadrant  3808 ; and four row select registers: top left row select register  3828 , top right row select register  3836 , bottom left row select register  3830 , bottom right row select register  3838 . The tile  3704 . 1  may comprise four quadrants: top left quadrant  3816 , top right quadrant  3818 , bottom left quadrant  3812 , bottom right quadrant  3814 ; and four row select registers each for a respective quadrant: top left row select register  3832 , top right row select register  3844 , bottom left row select register  3834 , bottom right row select register  3846 . The tiles  3702 . 1  and  3704 . 1  may share a current sources and swizzles block  3810 . The current sources and swizzles block  3810  may be sandwiched between the pair of tiles. Further, the tiles  3702 . 1  and  3704 . 1  may share top and bottom output circuits including channel circuits  3820  and  3822 , column multiplexers  3848  and  3850 , output multiplexers  3824  and  3826 , and output buffers  3840  and  3842 . The channel circuits  3820  and  3822  may include sample and hold (S/H) circuits. In one embodiment, each quadrant of the tile may comprise a plurality of columns that each may include a plurality of rows. For example, a quadrant may have 1712 columns that each may contain 2784 rows of pixels. In one embodiment, each tile may include reference pixels. For example, a predetermined number (e.g., 4) of columns and or rows of pixels at outer peripheral of each tile may be designated as reference pixels. The reference pixels may be used to generate signals representing the background and are not exposed to the analyte. 
     Each column may generate an output signal when one row of pixels is selected according to the respective row select register for the quadrant. In one embodiment, each column of a quadrant may be designated as a first or second column (e.g., an odd column or even column), and the output signal may be read from either the top or the bottom output circuits. The columns may be grouped for parallel read out operation. That is, a group of first columns or a group of second columns (n columns, n being an integer larger than one) may be read out together simultaneously in parallel. For example, if n is equal to 8, odd column groups may be columns [1:8], [17:24], [33:40], etc., and even column groups may be [9:16], [25:32], [41:48], etc. The column groups may be connected according to quadrant they are in. For a top left quadrant (e.g.,  3802 ,  3812 ) odd column groups may be connected to the output circuit at a first side (e.g., top output circuits including the channel circuit  3820 , column multiplexer  3848 , output multiplexer  3824  and output buffer  3840 ) and even column groups may be connected to the output circuit at a second side (e.g., bottom output circuits including the channel circuit  3822 , column multiplexer  3850 , output multiplexer  3826  and output buffer  3842 ). For a top right quadrant (e.g.,  3804 ,  3814 ) odd column groups may be connected to the output circuit at the first side and even column groups may be connected to the output circuit at the second side. For a bottom left quadrant (e.g.,  3806 ,  3816 ) odd column groups may be connected to the output circuit at the second side and even column groups may be connected to output circuit at the first side. For a bottom right quadrant (e.g.,  3808 ,  3818 ) odd column groups may be connected to the output circuit at the second side and even column groups may be connected to the output circuit at the first side. 
     In one embodiment, a group of first columns and a group of second columns may form a data channel to be read out together simultaneously from either the first or the second side of the output circuits. Each data channel may comprise one group of first columns and one group of second columns located in each quadrant between a first side of output circuits and a second side of output circuits (e.g., n first columns and n second columns from each of TL  3802 , BL  3806 , BL  3816 , TL  3812 ). 
     The readout operation may use the row select shift registers (e.g., a vertical shift register) to select rows and column shift registers to select columns (e.g., a horizontal shift register). When the operation starts, switches inside the current sources and swizzles block  3810  may be enabled to provide driving currents to the signal lines, any pixel select lines of an unused flow cell may be disabled, all row and column shift registers may be reset. Then, the vertical shift register may start counting by increments of 1 and the horizontal shift register may start counting by 16. Data for the frame may start with the vertical shift registers selecting row  1  of TL, TR, BL, and BR since reset. In one embodiment, the word “swizzle” may refer to the configuration that a metal line which passes through one column in the top circuitry may be routed in the space between the top and bottom circuitry in such a way that it passes through a different column in the bottom circuitry, as shown below in  FIG. 40 . 
     The readout operation may start with a TL quadrant (e.g., the TL quadrant  3802 ). The first group of odd columns (e.g., n first columns [ 1 : 8 ]) in TL  3802  and first group of even columns (e.g., n second columns [ 9 : 16 ]) in TL  3802  may be selected by the horizontal shift registers. Selected odd column pixels in row  1  of TL  3802  may be routed to top outputs through the channel circuit  3820 , column multiplexer  3848 , output multiplexer  3824  and then they may be read out through the top output buffer  3840 . At the same time, the selected even column pixels in row  1  of TL may be routed to bottom outputs through the channel circuit  3822 , column multiplexer  3850 , output multiplexer  3826  and then they may read out through the bottom output buffer  3842 . 
     During the above readout time, the next group of odd pixels (e.g., columns [ 17 : 24 ]) in row  1  of TL  3802  may be connected to the top column multiplexer  3848  and output multiplexer  3824  via the channel circuit  3820 . Similarly, the next group of even pixels (e.g., columns [ 25 : 32 ]) in row  1  of TL  3802  may be connected to the bottom column multiplexer  3850  and output multiplexer  3826  via the channel circuit  3822 . Then, the top and bottom output multiplexers  3824  and  3826  may switch their respective multiplexers, and subsequently, the next group of odd pixels in row  1  of TL  3802  may be read out through the top outputs, and the next group of even pixels in row  1  of TL  3802  may be read out through the bottom outputs. This may continue until all pixels from row  1  of TL  3802  have been read out. At the end of the read out of row  1 , the TL  3802 &#39;s vertical shift register may shift to the next row, and the outputs may begin to settle. 
     After row  1  of the TL quadrant  3802  is finished, the readout operation may continue to TR quadrant  3804 . A first group of odd columns (e.g., columns [ 1 : 8 ]) in TR quadrant  3804  and a first group of even columns (e.g., columns [ 9 : 16 ]) in TR quadrant  3804  may be selected by the horizontal shift registers. Then the selected first group of odd column pixels in row  1  of TR quadrant  3804  may be routed to top outputs through the channel circuit  3820 , column multiplexer  3848 , output multiplexer  3824  and then they may be read out through the top output buffer  3840 . At the same time, the selected first group of even column pixels [ 9 : 16 ] in row  1  of TR  3804  may be routed to bottom outputs through the channel circuit  3822 , column multiplexer  3850 , output multiplexer  3826  and then they may read out through the bottom output buffer  3842 . 
     During the above readout time, the next group of odd pixels (e.g., columns [ 17 : 24 ]) in row  1  of TR  3804  may be connected to the top column multiplexer  3848  and output multiplexer  3824  via the channel circuit  3820 . Similarly, the next group of even pixels (e.g., columns [ 25 : 32 ]) in row  1  of TR  3804  may be connected to the bottom column multiplexer  3850  and output multiplexer  3826  via the channel circuit  3822 . Then, the top and bottom output multiplexers  3824  and  3826  may switch their respective multiplexers, and subsequently, the next group of odd pixels in row  1  of TR  3804  may be read out through the top outputs, and the next group of even pixels in row  1  of TR  3804  may be read out through the bottom outputs. This may continue until all pixels from row  1  of TR  3804  have been read out. At the end of the read out of row  1 , the TR  3804 &#39;s vertical shift register may shift to the next row, and the outputs may begin to settle. 
     After row  1  of the TR quadrant  3804  is finished, the readout operation may continue to BL quadrant  3806 . A first group of odd columns (e.g., columns [ 1 : 8 ]) in BL quadrant  3806  and a first group of even columns (e.g., columns [ 9 : 16 ]) in BL quadrant  3806  may be selected by the horizontal shift registers. Then the selected first group of odd column pixels in row  1  of BL quadrant  3806  may be routed to bottom outputs through the channel circuit  3822 , column multiplexer  3850 , output multiplexer  3826  and then they may read out through the bottom output buffer  3842 . At the same time, the selected first group of even column pixels [ 9 : 16 ] in row  1  of BL  3806  may be routed to top outputs through the channel circuit  3820 , column multiplexer  3848 , output multiplexer  3824  and then they may be read out through the top output buffer  3840 . 
     During the above readout time, the next group of odd pixels (e.g., columns [ 17 : 24 ]) in row  1  of BL  3806  may be connected to the bottom column multiplexer  3850  and output multiplexer  3826  via the channel circuit  3822 . Similarly, the next group of even pixels (e.g., columns [ 25 : 32 ]) in row  1  of BL  3806  may be connected to the top column multiplexer  3848  and output multiplexer  3824  via the channel circuit  3820 . Then, the top and bottom output multiplexers  3824  and  3826  may switch their respective multiplexers, and subsequently, the next group of odd pixels in row  1  of BL  3806  may be read out through the bottom outputs, and the next group of even pixels in row  1  of BL  3806  may be read out through the top outputs. This may continue until all pixels from row  1  of BL  3806  have been read out. At the end of the read out of row  1 , the BL  3806 &#39;s vertical shift register may shift to the next row, and the outputs may begin to settle. 
     After row  1  of the BL quadrant  3806  is finished, the readout operation may continue to BR quadrant  3808 . A first group of odd columns (e.g., columns [ 1 : 8 ]) in BR quadrant  3808  and a first group of even columns (e.g., columns [ 9 : 16 ]) in BR quadrant  3808  may be selected by the horizontal shift registers. Then the selected first group of odd column pixels in row  1  of BR quadrant  3808  may be routed to bottom outputs through the channel circuit  3822 , column multiplexer  3850 , output multiplexer  3826  and then they may read out through the bottom output buffer  3842 . At the same time, the selected first group of even column pixels [ 9 : 16 ] in row  1  of BR quadrant  3808  may be routed to top outputs through the channel circuit  3820 , column multiplexer  3848 , output multiplexer  3824  and then they may be read out through the top output buffer  3840 . 
     During the above readout time, the next group of odd pixels (e.g., columns [ 17 : 24 ]) in row  1  of BR quadrant  3808  may be connected to the bottom column multiplexer  3850  and output multiplexer  3826  via the channel circuit  3822 . Similarly, the next group of even pixels (e.g., columns [ 25 : 32 ]) in row  1  of BR quadrant  3808  may be connected to the top column multiplexer  3848  and output multiplexer  3824  via the channel circuit  3820 . Then, the top and bottom output multiplexers  3824  and  3826  may switch their respective multiplexers, and subsequently, the next group of odd pixels in row  1  of BR quadrant  3808  may be read out through the bottom outputs, and the next group of even pixels in row  1  of BR quadrant  3808  may be read out through the top outputs. This may continue until all pixels from row  1  of BR quadrant  3808  have been read out. At the end of the read out of row  1 , the BR quadrant  3808 &#39;s vertical shift register may shift to the next row, and the outputs may begin to settle. 
     After row  1  of all four quadrants are read out, the operation may return to TL, and the pattern may be repeated until all rows in TL, TR, BL, and BR are read out to complete one frame for a tile (e.g.,  3702 . 1 ). And then, the operation may be carried on in a next tile (e.g.,  3702 . 2 ). This scheme may allow row n in a quadrant to settle for ¾ of the time that it takes to read out row n from all four quadrants. 
     In one embodiment, the readout operation may be performed to complete one quadrant at a time. That is, after one row for a quadrant has finished, move on to the next row of the same quadrant; and continue to a next quadrant only after all rows of same the quadrant are finished. 
     In one embodiment, the tiles at the top slice (e.g.,  3702 . 1 ˜ 3702 .N) may operate concurrently, and the tiles at the bottom slice may operate alternately with corresponding tiles of the top slice (e.g.,  3702 . 1  and  3704 . 1  would operate alternately). 
       FIG. 38B  illustrates shift directions in different quadrants of a tile according to an embodiment of the present invention. As shown in  FIG. 38B , in one embodiment, the readout operation may start from the center of a tile and move outward (e.g., increment the row and column select registers). 
       FIG. 39  illustrates a block diagram of part of a data channel  3900  of the chemical detection circuit  3700  according to an embodiment of the present invention. The data channel  3900  may comprise n first columns  3902  and n second columns  3904  of TL quadrant  3802 , and n first columns  3908  and n second columns  3906  of BL quadrant  3806 .  FIG. 39  only shows the data channel  3900  in the top slice (e.g., TL quadrant  3802  and BL quadrant  3806  of the tile  3702 . 1 ). Although not shown, the data channel  3900  may further comprise n first columns and n second columns in each of TL quadrant  3812  and BL quadrant  3816  of the tile  3704 . 1 . As shown in  FIG. 39 , the data channel  3900  may have two 2n signal lines with top 2n signal lines connected to the output channel circuit  3820  at the right side. Although not shown, the bottom 2n signal lines may be connected to the output channel circuit  3822  to the left side. The pixels of the n first columns  3902  and the n second columns  3906  may each be connected to a respective top 2n signal lines. The pixels of the n second columns  3904  and the n first columns  3908  may each be connected to a respective bottom 2n signal lines. The current sources and swizzles block  3810  at the left side of the 2n signal lines may provide 2n current sources that each may drive a respective signal line. Further, the 2n signal lines may be swizzled in the current sources and swizzles block  3810  (details of one exemplary embodiment of the swizzle will be described later with respect to  FIG. 40 ). 
     During operation, data from the top 2n signal lines may be read out from the channel circuit  3820 , column multiplexer  3848 , output multiplexer  3824  and output buffer  3840  and the bottom 2n signal lines may be readout from corresponding circuits at the left. 
       FIG. 40  illustrates a swizzle configuration of signal lines of the chemical detection circuit  3700  (of  FIG. 37 ) according to an embodiment of the present invention. In one embodiment of the chemical detection circuit  3700 , there may be two output lines running through each column so that a column of pixels may be connected to the column circuitry at the top of the chemical detection circuit  3700  (e.g., the IC chip) or to the column circuitry at the bottom of the chemical detection circuit  3700 . The column output lines may run the full height of the die and may be very long, and therefore may be susceptible to crosstalk. To reduce crosstalk, the column output lines may be swizzled in the middle of the chemical detection circuit  3700  (e.g., in the current sources and swizzles block  3810  of  FIG. 38A ). As shown in  FIG. 40 , the four columns may have 8 wires (e.g., each column may contain two wires). Each wire may be connected to either the top column circuitry  4002  or the bottom column circuitry  4004 . For example, the wires A, D, E and H may be connected to the top column circuitry  4002  and wires B, C, F and G may be connected to the bottom column circuitry  4004 . The sequence of the 8 wires may be swizzled in the middle. For example, top half of wire A may run through pixels of column  1  and bottom half of wire A may run through pixels of column  2 , top half of wire B may run through pixels of column  1  and bottom half of wire B may run through pixels of column  3 , top half of wire C may run through pixels of column  2  and bottom half of wire C may run through pixels of column  1 , top half of wire D may run through pixels of column  2  and bottom half of wire D may run through pixels of column  4 , top half of wire E may run through pixels of column  3  and bottom half of wire E may run through pixels of column  1 , top half of wire F may run through pixels of column  3  and bottom half of wire F may run through pixels of column  4 , top half of wire G may run through pixels of column  4  and bottom half of wire G may run through pixels of column  2 , top half of wire H may run through pixels of column  4  and bottom half of wire H may run through pixels of column  3 . In one embodiment, the swizzle according to pattern shown in  FIG. 40  may be repeated for every four columns. As a result, the crosstalk may be reduced by as much as 50%. 
       FIG. 41  illustrates a process  4100  for outputting data from a chemical detection circuit according to an embodiment of the present invention. The process  4100  may be performed by the chemical detection circuit  3700 . The process  4100  may start at step  4102 , at which a first quadrant of a tile may be selected to read out data. As described above with respect to  FIG. 38A , for example, a readout operation may be performed for a tile (e.g.,  3702 . 1 ) by starting at the top left quadrant  3802 . Then the process  4100  may proceed to step  4104 . At step  4104 , the process  4100  may select one group of first columns and one group of second columns. As described above, the readout operation may be performed in groups of first columns and second columns (e.g., odd columns [ 1 : 8 ] and even columns [ 9 : 16 ]). Then, at step  4106 , the process  4100  may read out data for the group of first columns from a first set of output pins (e.g., top output buffers  3840 ) and for the group of second columns from a second set of output pins (e.g., bottom output buffers  3842 ). 
     Then the process  4100  may proceed to step  4108 . At step  4108 , the process  4100  may repeat selection and data readouts for a next group of first columns and a next group of second columns until all remaining columns of the first quadrant are read out. For example, the chemical detection circuit  3700  may repeat the readout operation for odd column groups [ 17 : 24 ], [ 33 : 40 ], etc. and even column groups [ 25 : 32 ], [ 41 : 48 ], etc. for all remaining columns of the first quadrant (e.g., TL quadrant  3802 ). 
       FIG. 42  illustrates a system architecture  4200  for chemical detection according to an embodiment of the present invention. The system architecture  4200  may comprise a motherboard  4202 , an output device  4208 , a reader board  4210  and a valve board  4212 . The motherboard  4202  may include CPUs  4204  and storage  4206  (e.g., a Double Date Rate (DDR) memory device). The CPUs  4204  may scale from 2 cores to 6 cores. The memory DDRs  4206  may be 1 GB to 96 GB DDR3 (double data rate type 3). The motherboard  4202  may also support on board RAID (6 SATA ports) and graphics processor board (GPU). The output device  4208  may be a color display with high brightness (e.g., an XGA multi-touch input independent and display independent 8 wire analog resistive). The reader board  4210  may include a sensor  4218  (e.g., the chemical detection circuit  3700 ) and other peripheral circuits (details shown in  FIGS. 43 and 44  for analog and digital chemical sensors respectively). The valve board  4212  may include a FPGA  4214  and valve controls  4216 . During operation, the FPGA  4214  may be loaded with control logic to control the operation of the valve board. The valve controls  4216  may include a plurality of valves (e.g.,  30  valves) that controls flow of fluid containing analyte to be analyzed by the sensor  4218 . The valve board  4212  may further include thermistor inputs, pressure sensor inputs and may further include heater/cooler controls (not shown) that may control heaters/coolers for the sensor  4218  and analytes (e.g., to assist in controlling reactions during the testing of samples). In one embodiment, the motherboard  4202  and the reader board  4210  may be connected according to the PCI express (PCIe) standard, the reader board  4210  and the valve board  4212  may be connected by serial link over LVDS (low-voltage differential signaling). 
       FIG. 43  illustrates an analog reader board  4300  for a chemical detection circuit according to an embodiment of the present invention. The analog reader board  4300  may include an analog chemical sensor  4302 , a clock  4304 , a power supply  4306 , a serial link for LVDS  4308 , a reader FPGA  4310 , a memory  4312 , ADCs  4314 , a PCIe switch  4316 , a PCIe connector  4318 , two satellite FPGA blocks  4320  and  4322 , and a voltage reference and DACs block  4324 . The analog chemical sensor  4302  may be an IC chip embodiment of chemical detection circuit  3700 . The analog data read out from the analog chemical sensor  4302  may be digitized by the ADCs  4314 , which may use voltage references and DACs  4324 . The digitized data may be sent to the satellite FPGAs  4320  or  4322 , which may perform settling correction, and then sent to the reader FPGA  4310 . The reader FPGA  4310  may buffer data in the memory  4312 , which may include a plurality of DDR memory blocks. The reader FPGA  4310  may also perform frame averaging (e.g., average a pixel&#39;s data value among multiple frames; this is possible because the analog chemical sensor may read out data at a frame rate higher than required (e.g., 30 FPS) or variable rate frame averaging (e.g., average different portions of a pixels time history at a different rate) and then send data out to a server motherboard (e.g., motherboard  4202  of  FIG. 42 ) via PCIe switch  4316  and PCIe connector  4318 . The PCIe switch  4316  may include multiplexers that multiplex links to a PCIex 16 link of the PCIe connector  4318 . The LVDS  4308  may provide serial links to a valve board (e.g., the valve board  4212  of  FIG. 42 ). The power of the reader board  4300  may be provided by the power supply  4306  and the timing signals may be provided by the clock  4304 . In one embodiment, the ADCs  4314  may be placed close to the analog chemical sensor  4302 . 
       FIG. 44  illustrates a digital reader board  4400  for a chemical detection circuit according to an embodiment of the present invention. The digital reader board  4400  may include a digital chemical sensor  4402 , a clock  4404 , a power supply  4406 , a serial link for LVDS  4408 , a reader FPGA  4410 , a memory  4412 , a PCIe switch  4416 , and a PCIe connector  4418 . The digital chemical sensor  4402  may be an IC chip embodiment of chemical detection circuit  3700  (of  FIG. 37 ) with ADCs incorporated on the chip that digitize the output data signals on-chip. The clock  4404 , power supply  4406 , serial link for LVDS  4408 , reader FPGA  4410 , memory  4412 , PCIe switch  4416 , and PCIe connector  4418  may perform functions similar to their counterparts on the analog digital reader board  4300 . In one embodiment, the digital chemical sensor  4402  may be placed on a replaceable board separate from the digital reader board  4400 . 
       FIG. 45  illustrates a block diagram  4500  of an output configuration for a chemical detection circuit according to an embodiment of the present invention. The block diagram  4500  may show an analog front end and noise calculations for analog data output from an analog chemical detector  4502 . The DAC  4504  may generate analog signals according to digital reference values, and analog signals from the DAC  4504  may be buffered by the buffers  4506 . 1 ˜ 4506 . 4 . The output from analog chemical detector  4502  may be amplified by the amplifiers  4508 . 1 ˜ 4508 . 4  and the amplified signals may be filtered by the low pass filters  4510 . 1 ˜ 4510 . 4 . The filtered signals may be input to the ADC module  4512 , which may contain a plurality of differential amplifiers  4514 . 1 ˜ 4514 . 4 . The amplified signals may pass another round of low pass filters  4516 . 1 ˜ 4516 . 4  and then finally the signals may be converted by the Quad ADC  4518  into digital data and sent to FPGAs. The Quad ADC  4518  may receive clock signals from a clock fanout  4524 . The clock signals may be generated by a PLL  4522  based on signals from an oscillator  4520 . In one embodiment, the analog chemical detector  4502  may be an IC chip embodiment of the chemical detection circuit  3700 . 
       FIG. 46  illustrates a block diagram  4600  of bandwidth utilization for a chemical detection circuit according to an embodiment of the present invention. An analog chemical detector  4602  may send its data to a plurality of ADCs  4604 . The ADCs  4604  may send digital data to the FPGA(s)  4606 , which may in turn send data to CPU(s)  4608  and storage units  4616  and  4618  (e.g., DDR3 memory). The CPU(s)  4608  may cache data in a memory cache  4610  (e.g., DDR3 memory) and hard drives  4612  and  4614 . In one embodiment, the analog chemical detector  4602  may be an IC chip embodiment of the chemical detection circuit  3700 . The numbers given in  FIG. 46  may be theoretical maximums. The FPGA(s)  4606  may perform a 3:1 compression of samples (e.g., settling correction) and a 2:1 or greater compression of frames (e.g. frame averaging). 
       FIG. 47  illustrates a block diagram  4700  for clock distribution for an analog reader board (e.g., the analog reader board  4300  of  FIG. 43 ) according to an embodiment of the present invention. The clock signals for various components of an analog reader board may be generated based on a 100 MHz oscillator  4702 . The clock generator  4704  may receive the signals from the 100 MHz oscillator  4702  and generate various clock signals. For example, the clock generator  4704  may generate 120 MHz clock signals to be sent to two zero delay buffers  4706 . 1  and  4706 . 2 , a flip flop  4716  and a first PLL of the FPGA  4714  (e.g., the reader FPGA  4310  of the analog reader board  4300 ). The zero delay buffers  4706 . 1  and  4706 . 2  may provide the 120 MHz clock signals to ADC sets  4718 . 1  and  4718 . 2  for the ADCs to send digitized data to FPGAs  4720 . 1  and  4720 . 2  (e.g., the satellite FPGAs  4320  and  4322  of the analog reader board  4300 ) at a frequency of, for example, 840 MHz. The first PLL of the FPGA  4714  may send clock signals to first PLLs in respective FPGAs  4720 . 1  and  4720 . 2 , and may also send a clock signal internally to a flip flop port of the FPGA  4714 . The flip flop  4716  may generate channel increment/decrement signals for data read out based on an output of the flip flop port of the FPGA  4714  and the 120 MHz clock signal from the clock generator  4704 . The oscillator  4702  may also generate a 33 MHz clock signal for a clock driver  4708 , which may provide clock signals for second PLLs in the FPGAs  4720 . 1  and  4720 . 2  respectively and for a second PLL in the FPGA  4714 . The second PLL in the FPGA  4714  may generate an internal clock (e.g., 267 MHz). In one embodiment, basing all of these clocks may allow for the synchronization of the channel outputs of the sensor and the sampling by the ADCs. 
     Communication external to the analog board reader may be based on a 100 MHz clock signals from a PCIe connector. The 100 MHz clock signals from PCIe connector may be buffered by a PCIe clock buffer  4710 . The buffered 100 MHz clock signals may be sent to first and second SerDes PLL (serialization/deserialization phase locked loop) of the FPGA  4714  and may also be sent to a PCIe switch  4712  (e.g., PCIe switch  4316 ). 
     In one embodiment, the zero delay buffers  4706 . 1  and  4706 . 2  may allow for skew adjustment between ADC sample clocks and data channels of a chemical detector (not shown). The clocks may be differential LVDS where possible, but the clocks for channels of the chemical detector may be differential low-voltage positive emitter-coupled logic (LVPECL). Further, in one embodiment, the combination of ADC and data channel 120 MHz clocks need to be low jitter (e.g., &lt;15 μs—as drawn ˜4.5 rms). In one embodiment, in the case of the analog chemical sensor, the “clock” provided to the sensor may be the “channel increment/decrement signal”—allowing for synchronization of channel switch and sampling by the ADCs. 
       FIG. 48  illustrates a block diagram  4800  for power distribution of system components according to an embodiment of the present invention. A PC power supply  4802  may be coupled to an AC input. The valve board  4804  (e.g., the valve board  4212  of the system architecture  4200 ) may receive power from the PC power supply  4802  by two 4-pin connectors. The motherboard  4806  (e.g., the motherboard  4202  of the system architecture  4200 ) may receive power from the PC power supply  4802  by two 8-pin connectors and a 24-pin connector. The 24-pin cable to provide power to the motherboard  4806  may be “Y-cabled” to also provide power to the reader board  4808  (e.g., the reader board  4210  of system architecture  4200 , which may be an analog reader board (e.g.,  4300 ) or digital reader board (e.g.,  4400 )). The reader board  4808  may include an onboard power supply  4810  that may include a plurality of power regulators (e.g., low dropout linear regulator, programmable output low dropout regular) and/or DC/DC power supplies (e.g., high voltage high current DC/DC power supply). In one embodiment, all of the DC/DC switching power supplies may be synchronized with the main reader board clock. This may keep any switching noise from the power supplies from “beating” against the clocks used elsewhere. Further, the clocks for the switching power supplies may be arranged in time such that the instantaneous current load on the PC power supply is minimized. 
       FIG. 49  illustrates a block diagram  4900  for DACs of an analog reader board according to an embodiment of the present invention. The DAC configuration  4900  may include a voltage reference  4902 , a DAC  4904 , a low pass filter including a resistor  4906  and a capacitor  4908 . The filtered signal may be amplified by an operational amplifier  4910 . The output from the operational amplifier  4910  may be filtered by a bead  4912  and a plurality of capacitors  4914  (e.g., a bulk LPF/LF charge). The filtered signal then may be sent to first inputs of the operational amplifiers  4916 . 1 ˜ 4916 . 4  via local decoupling circuits (e.g., the capacitors  4918  and corresponding resistors  4920 ). The second inputs to the operational amplifiers  4916 . 1 ˜ 4916 . 4  may be respective channel inputs  4924 . 1 ˜ 4924 . 4 . The output of the operational amplifiers  4916 . 1 ˜ 4916 . 4  may be coupled back to the first inputs via respective feedback resistors  4922 . 1 ˜ 4922 . 4 . In one embodiment, a plurality of DACs may be provided for channel offset, references voltages, electrode drive, built-in self-test (BIST) drive and ISFET Bias. 
       FIG. 50  illustrates a block diagram of FPGA configuration for an analog reader board  5000  according to an embodiment of the present invention. The analog reader board  5000  may be an embodiment of the analog reader board  4300 . The analog reader board  5000  may comprise a plurality of ADC modules  5002 . 1  and  5002 . 2 , two satellite FPGAs  5004 . 1  and  5004 . 2  (e.g., satellite FPGAs  4320  and  4322 ), a reader FPGA  5006  (e.g., reader FPGA  4310 ) and its memory modules  5008 . 1  and  5008 . 2 , a PCIe switch  5010  (e.g., PCIe switch  4316 ), an analog chemical sensor  5012  (e.g., analog chemical sensor  4302 ), LVDS drivers and receivers  5014  (e.g., LVDS  4308 ) and a plurality of DAC modules  5016  and  5018 . In one embodiment, each ADC of the ADC modules  5002 . 1  and  5002 . 2  may include a PLL. The satellite FPGAs  5004 . 1  and  5004 . 2  may perform sample averaging, which may be controlled by Dstrobe signal from the reader FPGA  5006  and software setup in the satellite FPGAs  5004 . 1  and  5004 . 2 . Moreover, in one embodiment, the control logic for the reader FPGA  5006  may be loaded from the memory modules  5008 . 1  and/or  5008 . 2 , which may be SPI flash devices (e.g., EEPROM) that hold two images: (1) a default “loader” image, and (2) a current run-time image. The control logic (e.g., images) for the satellite FPGAs  5004 . 1  and  5004 . 2  may be loaded by the reader FPGA  5006  from a motherboard (e.g., motherboard  4202 ) over PCIe. Further, in one embodiment, the FPGAs (including the valve FPGA  4214 ) may be de-configured and reloaded by a PCIe reset. Also, PCI enumerations may be trigged once PCIe FPGA may be programmed. 
       FIG. 51  illustrates a block diagram of FPGA power monitoring for a reader board  5100  according to an embodiment of the present invention. The reader board  5100  may be an embodiment of the reader board  4808 . The reader board  5100  may comprise a power supply module  5102  (e.g., power supply  4810 ) that receives 5V and 12 V inputs from a 24 pin connector  5106 . The power supply module  5102  may provide power to the rest of reader  5104 . The output voltages from the power supply module  5102  may be monitored by a plurality of voltage monitors  5108  and  5112 . The first voltage monitor  5108  may receive its power supply VCC from the 24 pin connector  5106  and generate a reset RST signal if one of the monitored voltage (including VCC) deviates more than a threshold from a predetermined voltage level (e.g., 1.5% deviation). The RST signal from the voltage monitor  5108  may be “OR”-ed with a reset signal from a PCIe connector  5110  by an OR gate  5116 . The output of the OR gate  5116  may be input as a monitored voltage for the second voltage monitor  5112 , which may also receive its power supply VCC from the 24 pin connector  5106  and generate a reset RST signal if one of the monitored voltage (including VCC) deviates more than a threshold from a predetermined voltage level (e.g., 1.5% deviation). The RST signal from the voltage monitor  5112  may be sent to a clock driver  5114 , which may generate a reset signal and nCONFIG signal to the rest of reader  5104 . The reset signal from the clock driver  5114  may be sent to a PCIe switch of the reader board. The nCONFIG signal from the clock driver  5114  may be sent to a FPGA of the reader board to cause the FPGA to reload. In one embodiment, “OR”-ing the RST signal from the voltage monitor  5108  with the reset signal from the PCIe connector  5110  may guarantee the nCONFIG pulse width requirements being met. 
     Column ADC and Serializer Circuit 
     The described embodiments may provide a chemical detection circuit that may comprise a column of chemically-sensitive pixels. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor and a row selection device. The chemical detection circuit may further comprise a column interface circuit coupled to the column of chemically-sensitive pixels and an analog-to-digital converter (ADC) coupled to the column interface circuit. 
     Some embodiments may also provide a chemical sensor that may comprise a plurality of columns of chemically-sensitive pixels. Each column may comprise a plurality of chemically-sensitive pixels formed in rows. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor and a row selection device. The chemical sensor may further comprise a column interface circuit coupled to the column of chemically-sensitive pixels and an analog-to-digital converter (ADC) coupled to the column interface circuit. 
     Other embodiments may provide a method of generating an output signal for a chemical detection circuit. The method may comprise generating a row selection signal by a row decoder of the chemical detection circuit. The chemical detection circuit may have a pixel array that includes a column of chemical detection pixels. Each chemical detection pixel may include a chemically-sensitive transistor and a row selection device. The method may further comprise applying the row selection signal to a respective row selection device of a selected chemical detection pixel, converting an analog signal at a readout signal line of the column of chemical detection pixels to a digital signal by an Analog-to-Digital converter (ADC) and outputting the converted digital signal as the output signal for the chemical detection circuit. 
     The described embodiments may further provide a chemical detection circuit that may comprise a pixel array comprising a plurality of chemically-sensitive pixels formed in columns and rows. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor and a row selection device. The chemical detection circuit may further comprise a pair of analog-to-digital converter (ADC) circuit blocks, a pair of input/output (I/O) circuit blocks coupled to the pair of ADC circuit blocks respectively and a plurality of serial link terminals coupled to the pair of IO circuit blocks. 
     The described embodiments may further provide a method to read out data from a chemical detection device. The method may comprise reading data from a plurality of columns of chemically-sensitive pixels on the chemical detection device in parallel. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor and a row selection device. The method may further comprise digitizing data read from the plurality of columns of chemically-sensitive pixels in parallel, serializing the digitized data in parallel for each column of chemically-sensitive pixels respectively, and transmitting the buffered digitized data on a plurality of serial links in parallel. 
       FIG. 52  illustrates a digital chemical detection circuit  5200  according to an embodiment of the present invention. The digital chemical detection circuit  5200  may be an IC chip comprising a pixel array  5202 , row decoders  5204 . 1  and  5204 . 2 , column ADCs  5206 . 1  and  5206 . 2 , I/O circuits  5208 . 1 , a plurality of bias circuits  5210 . 1 ˜ 5210 . 3 , a timing sequencer  5212  and  5208 . 2  and a plurality of output terminals D[ 0 ]˜D[N−1]. The pixel array  5202  may comprise chemical detection pixels formed in columns with each column including a plurality of rows of pixels. In one embodiment, the pixel array  5202  may include many tiles of pixels and the tiles may be placed in slices as described above with respect to  FIG. 37 . The row decoders  5204 . 1  and  5204 . 2  may generate row selection signals for rows of pixels based on control logic. 
     In one embodiment, the column ADCs  5206 . 1  and  5206 . 2  may include a plurality of ADCs each corresponding to one column. In another embodiment, the column ADCs  5206 . 1  and  5206 . 2  may include a plurality of ADCs and each ADC may be shared between several columns (e.g., using one or more multiplexers). Moreover, in one embodiment, the column ADCs  5206 . 1  and  5206 . 2  may perform offset cancellation. 
     The bias circuits  5210 . 1 ˜ 5210 . 3  may generate all bias and reference voltages needed for the chemical detection circuit  5200  on chip. That is, the chemical detection circuit  5200  does not have any external analog references. The bias circuits  5210 . 1 ˜ 5210 . 3  may need an external power supply, such as VDDA to function. The timing sequencer  5212  may provide the internal timing signals for the chemical detection circuit  5200 . 
     The plurality of output terminals D[ 0 ]˜D[N−1] may provide serial links to one or more devices external of the IC chip. The serial links may use printed circuit board transmission lines. The signaling over the transmission lines may use differential signaling or CMOS signaling. The differential signaling may be any differential signaling scheme, for example, Low-voltage differential signaling (LVDS) or current mode logic (CML). In one embodiment, half of the output pins may be placed on one side of the chip  5200  and another half on an opposite side. The number N may be an even number (e.g., 24, 32). Further, in one embodiment, the serial interface may be programmable. For example, the strength of the drivers may be programmed and tuned for a given system. The driver type (LVDS, CML, CMOS) may also be programmed. Moreover, on-chip termination may be enabled or disabled. Various aspects of the protocol may be configured such as run-length control and format. 
       FIG. 53  illustrates a more detailed block diagram  5300  of the output circuits of the digital chemical detection circuit of  FIG. 52  according to an embodiment of the present invention. As shown in  FIG. 53 , column interface  5302  may be connected to the pixel array (e.g., pixel array  5202 ) to read data out of the pixel array. The column comparators  5304  may include a plurality of comparators (e.g., ADCs). In one embodiment, the column comparators  5304  may perform offset cancellation. 
     The DACs  5312 . 1  and  5312 . 2  may provide reference voltages for the column comparators  5304  to perform analog-to-digital conversion. A pair of latches blocks  5306  and  5308  may provide buffer for the output data. The digitized data may be sent from the column comparators first to the A latches  5306  and then sent from the A latches  5306  to the B latches  5308  according to the control provided by the gray code blocks  5314 . 1  and  5314 . 2 . A plurality of output serializer  5310 . 1 ˜ 5310 . n  may be coupled between the buffer and the output terminals D[ 0 ]˜D[n−1] (e.g., n=N/2). The gray code circuits  5314 . 1 ˜ 5314 . 2  may distribute a digital count to all of the latches that are controlled by the comparators  5304  such that when a given comparator transitions, the gray code may be latched into memory. This gray code may be set to count synchronously with a DAC ramp circuit which establishes a global reference for all comparators of the comparators  5304 . When the global reference falls below the pixel value held at given column, a corresponding comparator may fire. Since the comparator can transition asynchronous to the clock, the count may be distributed with a gray code where only one bit transition is made at any time is used to avoid invalid codes. 
     In one embodiment, each output terminal may comprise two pins for differential signaling (e.g., low-voltage differential signaling). In one embodiment, the A latches  5306  may be the master latches while the B latches  5308  may be the slave latches. The latches may allow the analog-to-digital conversion to run in parallel to the readout of a previously converted row. 
     The on-chip bias and reference voltages may be provided by the bias and reference circuit block  5316 . As shown in  FIG. 53 , the bias and reference circuit block  5316  may provide bias and reference voltages to the column interface circuit  5302 , the DACs  5312 . 1  and  5312 . 2 , and gray code circuits  5314 . 1 ˜ 5314 . 2 . Further, as shown in  FIG. 53 , the timing sequencer circuit  5320  may provide timing signals to the gray code circuits  5314 . 1 ˜ 5314 . 2 , DACs  5312 . 1 ˜ 5312 . 2 , row decoders  5318 . 1 ˜ 5318 . 2 , pixel controls and column controls. The timing sequencer  5320  may be connected to pins TMODE, TEN, RST for reset and test modes. The timing sequencer  5320  may also be connected to pins for SDA, SCL, CLK for programming registers with a serial protocol such as SPI. The timing sequencer  5320  may control all the timing on the chip by advancing each row during a frame time and providing stimulus to the circuits during each row time. Because the pixel can operate in many different ways, the timing sequencer  5320  may be reprogrammed to change the operation of the control signals. 
       FIG. 54  illustrates a serializer circuit  5400  according to an embodiment of the present invention. The serializer circuit  5400  may comprise a plurality of shift registers  5402 , bit alignment logic  5406 , a pair of ping-pong registers  5406 , a multiplexer  5408  to select one of the ping-pong registers, a multiplexer  5410  to multiplex the output from the multiplexer  5408  and built-in self test (BIST), an encoder  5412 , a serializer  5416  and driver  5418 . 
     The shift registers  5402  may be part of the I/O buffer. In one embodiment, as shown in  FIG. 54 , 14-bit shift registers may be used. The data shifted out of the shift registers may be sent to the bit alignment logic  5406 , where the data may be aligned. For example, the 14-bits data may be aligned to 8-bits data according to align control. The aligned data from the alignment logic  5406  may be sent to the pair of ping-pong registers  5406  that latch each parallel word with timing overlap to prevent glitches in the data. 
     Then, the multiplexer  5408  may select one of the pair of ping-pong registers  5406  to output its data to the multiplexer  5410 . The multiplexer  5410  may select either the output data from the multiplexer  5408  or the BIST data to be sent to the encoder  5412 . To achieve DC balance, an encoding scheme such as 8b/10b may be used. Thus, in one embodiment, the encoder  5412  may be an 8B10B encoder. It should be noted that other encoding schemes may also be applied. The encoded data from the encoder  5412  may be serialized in the serializer  5413  and sent out by the driver  5418 . In one embodiment, the serializer  5413  may be driven by a PLL clock signal. In one embodiment, the driver  5418  may be configured to transmit data signals by low-voltage differential signaling. In one embodiment, the driver  5418  may work in a differential mode, in which one bit may be transmitted at each transmit clock signal and the pair of output pins may carry the differential data pair. In another embodiment, the driver  5418  may work in a dual-channel mode, in which two bits may be transmitted per transmit clock cycle in parallel by the pair of output pins of an output terminal. 
       FIG. 55  illustrates a more detailed block diagram  5500  As shown in  FIG. 55 , the serializer  5413  may comprise a plurality of registers  5502 , a pair of multiplexers  5504 , a pair of registers  5506 , a multiplexer  5508  and a buffer register  5510 . The registers  5502  may each hold one bit of the encoded data. The registers  5502  may work at a clock speed at one tenth of the PLL clock signal. The output from the registers  5502  may be sent to the pair of multiplexers  5504 . Each of the multiplexers  5504  may generate an output to be sent to one of the pair of registers  5506 . The pair of registers  5506  may operate at one half of the clock speed of the PLL clock signal. The output from the pair of registers  5506  may be input to the multiplexer  5508 , which may select one of the outputs from the pair of registers  5506  to be the output. The output from the multiplexer  5508  may be sent to the buffer register  5510 . The buffer register  5510  may operate at the clock speed of the PLL clock signal to send out its content to the driver  5418 . 
       FIG. 56  illustrates a block diagram of a digital chemical detection circuit according to an embodiment of the present invention.  FIG. 56  shows a layout of a digital chemical detection circuit according to an embodiment of the present invention. 
       FIG. 57  illustrates a block diagram of another digital chemical detection circuit according to an embodiment of the present invention.  FIG. 56  shows another layout of a digital chemical detection circuit according to an embodiment of the present invention. 
       FIG. 58  illustrates a block diagram of another digital chemical detection circuit  5800  according to an embodiment of the present invention. The digital chemical detection circuit  5800  may comprise a pixel array  5802 , a plurality of output circuits  5804 . 1 ˜ 5804 . 2 , a plurality of serial output circuits  5806 . 1 ˜ 5806 . 2 , a plurality of row select circuits  5808 . 1 ˜ 5808 . 2 , a clock tree  5810  and a plurality of thermometers  5812 . The pixel array  5802  may be a 2T pixel array  1400  shown in  FIG. 14A  and comprise a plurality of 2T pixels configured according to  FIG. 14A . The row select  5808 . 1 ˜ 5808 . 2  may be the row decoders as described above with respect to  FIGS. 52-53 . Also, the output circuits  5804 . 1 ˜ 5804 . 2  may include column interface, offset cancellation and column ADC as described above with respect to  FIGS. 52-53 . The serial output circuits  5806 . 1 ˜ 85806 . 2  may include the serializer circuits described above with respect to  FIGS. 52-55 . The clock tree  5810  may be an embodiment of the timing sequencer described above with respect to  FIGS. 52-53 . In one embodiment, the digital chemical detection circuit  5800  may include four thermometers placed on chip. Further, in one embodiment, the four thermometers may be placed at or near the four corners of the pixel array  5802 . 
     Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings. In other instances, well-known operations, components and circuits have not been described in detail so as not to obscure the embodiments. It can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments. For example, some embodiments are described with an NMOS. A skilled artisan would appreciate that a PMOS may be used as well. 
     Those skilled in the art may appreciate from the foregoing description that the present invention may be implemented in a variety of forms, and that the various embodiments may be implemented alone or in combination. Therefore, while the embodiments of the present invention have been described in connection with particular examples thereof, the true scope of the embodiments and/or methods of the present invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims. 
     Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints. 
     Some embodiments may be implemented, for example, using a computer-readable medium or article which may store an instruction or a set of instructions that, if executed by a machine, may cause the machine to perform a method and/or operations in accordance with the embodiments. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and/or software. The computer-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disc Read Only Memory (CD-ROM), Compact Disc Recordable (CD-R), Compact Disc Rewriteable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of Digital Versatile Disc (DVD), a tape, a cassette, or the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.