Patent Publication Number: US-8984748-B2

Title: Singulated semiconductor device separable electrical interconnect

Description:
TECHNICAL FIELD 
     The present disclosure relates to a socket assembly produced using additive printing processes that is capable of interconnecting one or more singulated die devices in a separable or solderless fashion to another circuit member, such as for example a test station. The present socket assembly allows the singulated die devices to be tested prior to final packaging. 
     BACKGROUND OF THE INVENTION 
     Traditional semiconductors and IC devices are typically formed on a substrate using photolithography. The substrate may be a silicon wafer. Multiple IC devices are typically formed on a single wafer and then the wafer is cut into die. The IC devices are typically packaged in a variety of ways to provide redistribution from the terminals on the die to a spacing that is conducive to cost effective printed circuit board (PCB) fabrication techniques. The package also serves to protect the fragile silicon or provide additional functions such as thermal management or near device decoupling. In many cases, the size and distance between die terminals is so small that the IC device cannot be connected to the final PCB without some sort of re-routing interface. In such cases, the package can provide the re-routing interface. 
     Most IC devices are produced with terminals in either a peripheral pattern that runs along the edges of the IC device or an area array pattern that spans across the surface of the IC device. A main method for attachment when the terminals are in an area array pattern is to connect the terminals with solder. Basically, the package has an array of terminals that correspond to the IC device terminals. Solder is applied to the terminals on the IC device and/or the package and reflowed to create the mechanical and electrical connection in a process commonly called flip chip attachment. In a flip chip attachment the IC device is flipped over to mate the terminals on the die to the terminals on the IC package substrate. 
     After IC device is positioned in this type of package and attached to the package terminals, the package is often under filled with an epoxy of some type to provide support and strength to the solder joints. The epoxy protects the solder joints from thermal expansion, miss-match and/or shock during use. Regardless of whether a package is under filled with epoxy, the connection of the IC device to the package is generally not reworkable after packaging, and if there is a missing or broken connection it is difficult to repair. 
     Once the IC devices are packaged, the IC devices are usually tested in a variety of ways to determine the reliability and performance of the IC devices in the package. The IC devices may be tested as they would be used in a final application. In many cases, the functional performance of the IC device is not known prior to placing it into the package. If the packaged IC device fails testing then the cost of the package and manufacturing process is lost. 
     Area array packaging has been utilized for many years, and provides a method for interconnecting IC devices with larger terminal counts than peripheral lead packaging. In general, the area array packaging is more expensive due to the larger pin counts and more sophisticated substrates required. The limitations for area array packaging include the terminal pitch, thermal management, cost, ability to rework faulty IC devices and reliability of the solder joints. 
     There also have been advancements in recent years in both area array packaging and peripheral lead packaging where multiple IC devices are placed in the same package, creating what has been nicknamed SiP for “system in package.” Placing multiple IC devices in a single package further complicates the problems discussed above. 
     BRIEF SUMMARY OF THE INVENTION 
     The present disclosure relates to a socket assembly that forms a solderless electrical interconnection between a singulated bare-die integrated circuit device (referred to herein as an “IC device”) and another circuit member. The present socket assembly provides a very high frequency interface for an IC device with fine pitch terminals. The present socket assembly allows the IC device to be tested prior to final packaging. The other circuit member can be a printed circuit board, a test assembly, or any other electrical device. 
     One embodiment is directed to a socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer. A conductive material is deposited in at least a portion of the recesses comprising conductive traces electrically coupling the contact members to the other circuit member. 
     The conductive traces preferably have substantially rectangular cross-sectional shapes. In one embodiment, a conductive material, a non-conductive material, and a semi-conductive material are printed on a single layer of the compliant printed circuit. Additional circuitry planes can be printed on the compliant printed circuit, such as for example, a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, and a flexible circuit. 
     The contact members can be formed from one of a curable conductive material, sintered conductive particles, conductive inks, and the like. In one embodiment, a flexible circuit member electrically coupled to the conductive traces extends beyond a perimeter edge of the socket assembly and is connected to a test station. 
     One or more electrical devices can be printed on the compliant printed circuit and electrically coupled to one or more of the conductive traces. The electrical devices can be selected from the group consisting of a power plane, ground plane, capacitor, resistor, filters, signal or power altering and enhancing device, capacitive coupling feature, memory device, embedded integrated circuit, and RF antennae. Optical quality material can also be deposited in at least a portion of the recesses to create one or more optical circuit geometries. In another embodiment, one or more optical fibers are located in at least a portion of the recesses. 
     There are few or no commercial products available today to allow a semiconductor manufacturer to validate the IC device directly off of the singulated die, with process or performance information provided in a manner much faster than if the die is tested after packaging. In most cases today, in order to provide any high performance test capability, the user must probe the die in an expensive wafer probe system with expensive probes. In many cases, full functionally testing of the IC device on the wafer is not possible. The present socket assembly allows the user to power and manage the IC device to be tested. This test capability allows the IC device manufacturer to segregate the performance of the IC devices before packaging vs. after packaging. 
     The ability to build multi-layer structures compliant printed circuit with a relatively large surface area is a major advantage, and the ability to add electrical enhancements provides performance advantages over existing probe products. For example, the ability to add programmable logic, transistors, and memory device to the present socket assembly provides an opportunity to incorporate test intelligence into the assembly, extending the use of legacy test equipment or improving the test performance of the system. 
     Transistors and memory printed into the socket assembly provide adaptive testing or the ability to alter the circuit being tested. The present socket assembly also permits interconnecting a group of IC devices to simulate a multi-chip or system-in-package configuration, so that the IC devices can be tested in relation to the other chips they will eventually be expected to interact with. 
     The present socket assembly provides a low cost alternative to other socket products, by utilizing an additive printing process and unique contact member fabrication process. The nature of the process can allow for very high frequency performance, as well as the addition of on-board electrical devices and circuitry planes that are not available with other socket products. The present socket assembly can be superior to membrane socket products in terms of mechanical performance, manufacturing complexity, electrical performance, and cost. 
     The present disclosure is also directed to a method of making a socket assembly that forms a solderless electrical connection between terminals on a singulated integrated circuit device and another circuit member. A base layer of a dielectric material is printed onto a surface of a fixture, while leaving cavities in the fixture exposed. A conductive material is printed into a plurality of the cavities in the fixture. At least one dielectric layer is printed with recesses corresponding to a target circuit geometry on the dielectric base layer. A conductive material is deposited in at least a portion of the recesses comprising conductive traces electrically coupled to the contact members of a compliant printed circuit. The compliant printed circuit is removed from the fixture to expose distal ends of the contact members. The compliant printed circuit is positioned relative to an opening in a socket housing so the contact members electrically couple with the terminals on a singulated integrated circuit device located in the opening. Compliant layers can optionally be printed on the compliant printed circuit to increase performance of the present socket assemblies. 
     The present disclosure is also directed to a method of adaptive testing of singulated semiconductor devices using the socket assembly of the present disclosure. Electrical devices on the socket assembly can monitor performance of the circuit member being tested and signal the test station to modify the test protocol accordingly. The test station can also be signaled to modify the circuit member. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         FIG. 1  is a cross-sectional view of a fixture for making a compliant printed circuit for a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 2  illustrates contact members formed in the fixture of  FIG. 1 . 
         FIG. 3  illustrates conductive traces coupled to the contact members of  FIG. 2 . 
         FIG. 4  illustrates a compliant layer added to the assembly of  FIG. 3 . 
         FIG. 5  illustrates a protective layer added to the assembly of  FIG. 4 . 
         FIG. 6  is a cross-sectional view of a compliant printed circuit in a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 7  is a cross-sectional view of an alternate compliant printed circuit in a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 8  is a cross-sectional view of a compliant printed circuit with circuitry layers in a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 9  is a cross-sectional view of a compliant printed circuit with electrical devices in a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 10  is a cross-sectional view of a multi-layered compliant printed circuit in a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 11  is a cross-sectional view of a compliant printed circuit with coupling features in a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 12  illustrates a compliant printed circuit with optical features for a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 13  illustrates an alternate compliant printed circuit with optical features for a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 14  illustrates a method of reworking contact members on a compliant printed circuit for a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 15  illustrates a socket assembly in accordance with an embodiment of the present disclosure. 
         FIG. 16  illustrates a pick and place system used with a socket assembly in accordance with an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present disclosure relates to a high performance socket assembly capable of interconnecting one or more IC devices in a solderless interface, permitting the IC device to be tested prior to final packaging. The present socket assembly can be used with IC devices having contact-to-contact spacing (pitch) on the order of less than about 1.0 millimeter (1×10 −3  meters), and more preferably a pitch of less than about 0.7 millimeter, and most preferably a pitch of less than about 0.4 millimeter. 
       FIG. 1  is a cross-sectional view of a fixture  50  useful in making a compliant printed circuit for a socket assembly in accordance with an embodiment of the present disclosure. The fixture  50  can include a plurality of cavities  52  in a first surface  54 . The locations of the cavities  52  are arranged in an array that corresponds to terminals on a wafer-level IC device (see e.g.,  FIG. 6 ). The cavities  52  can be formed using a variety of techniques, such as molding, machining, printing, imprinting, embossing, etching, coining, and the like. Inner surfaces  53  of the cavities  52  can be pretreated preparatory to formation of the compliant printed circuit. 
     A base layer  56  is preferably located on the first surface  54  of the fixture  50 . In one embodiment, the base layer  56  is printed onto the first surface  54 , while leaving the cavities  52  exposed. In another embodiment, the base layer  56  is applied to the first surface  54  before the cavities  52  are formed. The base layer  56  can facilitate removal of compliant printed circuit  70  from the fixture  50  (see  FIG. 6 ). The base layer  56  is preferably a dielectric material that also acts as an electrical insulator and a carrier layer for the compliant printed circuit  70 . 
     The fixture  50  can be constructed from a variety of materials, such as for example metal, plastic, ceramics, and composites thereof. In one embodiment, the fixture  50  is made from a resist material that can be dissolved to release the compliant printed circuit  70 . Making the fixture  50  from a dissolvable material can permit the contact members (such as the contact members  60  shown in  FIG. 6 ) to have a variety of internal features, undercuts, or cavities that are difficult or typically not possible to make using conventional molding or machining techniques, referred to herein as a “non-moldable features.” The cavities  52  can be optionally coated with a material to facilitate release of the contact members  60  from the fixture  50 . 
     As illustrated in  FIG. 2 , conductive material  58  is deposited in the cavities  52 . The conductive material  58  may be deposited up to a top surface  66  of the base layer  56 . In one embodiment, the conductive material  58  may be a metallic powder that can be sintered to create contact members  60  (see  FIG. 6 ). In another embodiment, the conductive material  58  is a flowable, curable conductive material. Various methods for maskless deposition of electronic materials, such as inkjet printing technology as will be described below, may also be used to deposit the conductive material  58  in the cavities  52 . 
     As mentioned above, in one embodiment, the inner surfaces  53  of the cavities  52  can be optionally pretreated before deposition of the conductive material  58 . For example, the inner surfaces  53  can be coated with particles of rhodium and then sintered. The sintered rhodium is then coated with nickel or copper. In another embodiment, the inner surfaces  53  can be coated with a low friction material that facilitates removal of the contact members  60  (see  FIG. 6 ) from the fixture  50 . 
     The conductive material  58  is preferably deposited in a first state and then processed to create a second more permanent state. For example, a metallic powder can be deposited in the cavities and subsequently sintered, or a curable conductive material may flow into the cavities  52  and can be subsequently cured. As used herein “cure” and inflections thereof refers to a chemical-physical transformation that allows a material to progress from a first form (e.g., flowable form) to a more permanent second form. The term “curable” refers to a characteristic of a material having the potential to be cured, such as for example by the application of a suitable energy source. 
       FIG. 3  illustrates dielectric layers  62  and conductive traces  64  deposited, such as by printing, on an exposed top surface  66  of base layer  56 . In one embodiment, the conductive traces  64  can be created by sintering or printing a platable target that is subsequently plated with a conductive material. In one embodiment, the plating is optionally applied using printing technology, such as for example inkjet printing technology, aerosol printing technology, or other maskless deposition process. The printing process is additive in nature. Digital images of the dielectric layers  62  and conductive traces  64  are printed directly on the surface  66 , eliminating or reducing many of the lithography, plating, and etching steps used to manufacture conventional sockets. The resulting compliant printed circuit  70  (see  FIG. 6 ) provides high frequency capability, and can reduce manufacturing production time and cost by orders of magnitude. 
     The use of additive printing processes can permit a wide variety of materials to be applied on a layer with a registration relative to the features of the previous layer. Selective addition of conductive, non-conductive, or semi-conductive materials at precise locations to create a desired effect can offer advantages in tuning impedance or adding electrical function on a given layer. Tuning performance on a layer by layer basis relative to the previous layer can greatly enhance electrical performance. 
     In one embodiment, recesses  67  (or trenches) formed in the base layer  56  can permit control of the location, cross section, material content, and aspect ratio of the contact members  60  (shown in  FIG. 6 ) and the conductive traces  64 . Maintaining the conductive traces  64  with a cross-section of 1:1 or greater can provide greater signal integrity than traditional subtractive trace forming technologies. For example, traditional methods take a sheet of a given thickness and etch the material between the traces away to have a resultant trace that is usually wider than it is thick. The etching process also removes more material at the top surface of the trace than at the bottom, leaving a trace with a trapezoidal cross-sectional shape, degrading signal integrity in some applications. 
     Using recesses to control the aspect ratio of the conductive traces  64  can result in a more rectangular or square cross-section of the conductive traces, with a corresponding improvement in signal integrity. The use of additive printing processes also permits conductive material, non-conductive material, and semi-conductive material to be simultaneously located on a single layer. 
     In another embodiment, pre-patterned or pre-etched thin conductive foil circuit traces can be transferred to the recesses  67 . For example, a pressure sensitive adhesive can be used to retain the copper foil circuit traces in the recesses  67 . The trapezoidal cross-sections of the pre-formed conductive foil traces are then post-plated. The plating material fills the open spaces in the recesses  67 , resulting in a substantially rectangular or square cross-sectional shape corresponding to the shape of the recesses  67 . 
     In another embodiment, a thin conductive foil is pressed into the recesses  67 , and the edges of the recesses  67  act to cut or shear the conductive foil. The process positions a portion of the conductive foil in the recesses  67 , but leaves the negative pattern of the conductive foil not wanted outside and above the recesses  67  for easy removal. Again, the foil in the recesses  67  is preferably post plated to add material to increase the thickness of the conductive traces  64  and to fill any voids left between the conductive foil and the recesses  67 . 
       FIG. 4  illustrates a compliant layer  72  deposited on a surface  74  of the dielectric layers  62  and the conductive traces  64 . The compliant layer  72  is preferably printed onto the surface  74 . The compliant layer  72  can be printed using inkjet printing technology, aerosol printing technology, or other maskless deposition techniques as previously described. The compliant layer  72  provides normal force and actuation compliance. In another embodiment, the compliant layer  72  can be bonded to the surface  74 . As used herein, “bond” or “bonding” refers to, for example, adhesive bonding, solvent bonding, ultrasonic welding, thermal bonding, or any other techniques suitable for attaching adjacent layers to a substrate. 
     Finally,  FIG. 5  illustrates a protective layer  78  added to a top surface  76  of the compliant layer  72 . The protective layer  78  can be applied using printing technology or can be a patterned film bonded to the top surface  76 . The added protective layer  78  may complete the compliant printed circuit  70 . 
     Various methods for maskless deposition of electronic materials and forming electrical devices and features may also be used, such as disclosed in U.S. Pat. No. 7,485,345 (Renn et al.); U.S. Pat. No. 6,825,829 (Albert at al.); and U.S. Pat. Publication No. 2008/0008822 (Kowalski et al.), which are hereby incorporated by reference. Inkjet printing technology, aerosol printing technology, and other printing technology are examples of maskless deposition which can be used to deposit features. 
     The availability of printable silicon inks provides the ability to print the conductive material  58  and other electrically active materials to form electrical devices and features. Exemplary embodiments of printable silicone inks are disclosed, for example, in U.S. Pat. No. 7,485,345 (Renn et al.); U.S. Pat. No. 7,382,363 (Albert et al.); U.S. Pat. No. 7,148,128 (Jacobson); U.S. Pat. No. 6,967,640 (Albert et al.); U.S. Pat. No. 6,825,829 (Albert et al.); U.S. Pat. No. 6,750,473 (Amundson et al.); U.S. Pat. No. 6,652,075 (Jacobson); U.S. Pat. No. 6,639,578 (Comiskey et al.); U.S. Pat. No. 6,545,291 (Amundson et al.); U.S. Pat. No. 6,521,489 (Duthaler et al.); U.S. Pat. No. 6,459,418 (Comiskey et al.); U.S. Pat. No. 6,422,687 (Jacobson); U.S. Pat. No. 6,413,790 (Duthaler et al.); U.S. Pat. No. 6,312,971 (Amundson et al.); U.S. Pat. No. 6,252,564 (Albert et al.); U.S. Pat. No. 6,177,921 (Comiskey et al.); U.S. Pat. No. 6,120,588 (Jacobson); U.S. Pat. No. 6,118,426 (Albert et al.); and U.S. Pat. Publication No. 2008/0008822 (Kowalski et al.), which are hereby incorporated by reference. For example, conductive material can be deposited in the cavities using printing technology. 
     Printing processes can preferably be used to fabricate various functional structures, such as conductive paths and electrical devices without the use of masks or resists. Features down to about 10 microns can be directly written in a wide variety of functional inks, including metals, ceramics, polymers and adhesives, on virtually any substrate—silicon, glass, polymers, metals and ceramics. The substrates can be planar and non-planar surfaces. The printing process can be followed by a thermal treatment, such as in a furnace or with a laser, to achieve dense functionalized structures. 
     U.S. Pat. No. 6,506,438 (Duthaler et al.) and U.S. Pat. No. 6,750,473 (Amundson et al.), which are incorporated herein by reference, teach using inkjet printing to make various electrical devices, such as resistors, capacitors, diodes, inductors (or elements which can be used in radio applications or magnetic or electric field transmission of power or data), semiconductor logic elements, electro-optical elements, transistors (including, light emitting, light sensing or solar cell elements, field effect transistors, top gate structures), and the like. 
     U.S. Pat. No. 7,674,671 (Renn et al.); U.S. Pat. No. 7,658,163 (Renn et al.); U.S. Pat. No. 7,485,345 (Renn et al.); U.S. Pat. No. 7,045,015 (Renn et al.); and U.S. Pat. No. 6,823,124 (Renn et al.), which are hereby incorporated by reference, teach using aerosol printing to create various electrical devices and features. 
     Printing of electronically active inks can be done on a large class of substrates, without the requirements of standard vacuum processing or etching. The inks may incorporate mechanical, electrical or other properties, such as, conducting, insulating, resistive, magnetic, semiconductive, light modulating, piezoelectric, spin, optoelectronic, thermoelectric or radio frequency. 
     A plurality of ink drops are dispensed from the print head directly to a substrate or on an intermediate transfer member. The transfer member can be a planar or non-planar structure, such as a drum. The surface of the transfer member can be coated with a non-sticking layer, such as silicone, silicone rubber, or Teflon. 
     The ink (also referred to as function inks) can include conductive materials, semi-conductive materials (e.g., p-type and n-type semiconducting materials), metallic material, insulating materials, and/or release materials. The ink pattern can be deposited in precise locations on a substrate to create fine lines having a width smaller than 10 microns, with precisely controlled spaces between the lines. For example, the ink drops form an ink pattern corresponding to portions of a transistor, such as a source electrode, a drain electrode, a dielectric layer, a semiconductor layer, or a gate electrode. 
     The substrate can be an insulating polymer, such as polyethylene terephthalate (PET), polyester, polyethersulphone (PES), polyimide film (e.g. Kapton, available from DuPont located in Wilmington, Del.; Upilex available from Ube Corporation located in Japan), or polycarbonate. Alternatively, the substrate can be made of an insulator such as undoped silicon, glass, or a plastic material. The substrate can also be patterned to serve as an electrode. The substrate can further be a metal foil insulated from the gate electrode by a non-conducting material. The substrate can also be a woven material or paper, planarized or otherwise modified on at least one surface by a polymeric or other coating to accept the other structures. 
     Electrodes can be printed with metals, such as aluminum or gold, or conductive polymers, such as polythiophene or polyaniline. The electrodes may also include a printed conductor, such as a polymer film comprising metal particles, such as silver or nickel, a printed conductor comprising a polymer film containing graphite or some other conductive carbon material, or a conductive oxide such as tin oxide or indium tin oxide. 
     Dielectric layers can be printed with a silicon dioxide layer, an insulating polymer, such as polyimide and its derivatives, poly-vinyl phenol, polymethylmethacrylate, polyvinylidenedifluoride, an inorganic oxide, such as metal oxide, an inorganic nitride such as silicon nitride, or an inorganic/organic composite material such as an organic-substituted silicon oxide, or a sol-gel organosilicon glass. Dielectric layers can also include a bicylcobutene derivative (BCB) available from Dow Chemical (Midland, Mich.), spin-on glass, or dispersions of dielectric colloid materials in a binder or solvent. 
     Semiconductor layers can be printed with polymeric semiconductors, such as, polythiophene, poly(3-alkyl)thiophenes, alkyl-substituted oligothiophene, polythienylenevinylene, poly(para-phenylenevinylene) and doped versions of these polymers. An example of suitable oligomeric semiconductor is alpha-hexathienylene. Horowitz, Organic Field-Effect Transistors, Adv. Mater., 10, No. 5, p. 365 (1998) describes the use of unsubstituted and alkyl-substituted oligothiophenes in transistors. A field effect transistor made with regioregular poly(3-hexylthiophene) as the semiconductor layer is described in Bao et al., Soluble and Processable Regioregular Poly(3-hexylthiophene) for Thin Film Field-Effect Transistor Applications with High Mobility, Appl. Phys. Lett. 69 (26), p. 4108 (Dec. 1996). A field effect transistor made with a-hexathienylene is described in U.S. Pat. No. 5,659,181 (Bridenbaugh et al.), which is incorporated herein by reference. 
     A protective layer can optionally be printed onto the electrical devices and features. The protective layer can be an aluminum film, a metal oxide coating, a polymeric film, or a combination thereof. 
     Organic semiconductors can be printed using suitable carbon-based compounds, such as, pentacene, phthalocyanine, benzodithiophene, buckminsterfullerene or other fullerene derivatives, tetracyanonaphthoquinone, and tetrakisimethylanimoethylene. The materials provided above for forming the substrate, the dielectric layer, the electrodes, or the semiconductor layer are exemplary only. Other suitable materials known to those skilled in the art having properties similar to those described above can be used in accordance with the present disclosure. 
     An inkjet print head, or other print head, preferably includes a plurality of orifices for dispensing one or more fluids onto a desired media, such as for example, a conducting fluid solution, a semiconducting fluid solution, an insulating fluid solution, and a precursor material to facilitate subsequent deposition. The precursor material can be surface active agents, such as octadecyltrichlorosilane (OTS). 
     Alternatively, a separate print head is used for each fluid solution. The print head nozzles can be held at different potentials to aid in atomization and imparting a charge to the droplets, such as disclosed in U.S. Pat. No. 7,148,128 (Jacobson), which is hereby incorporated by reference. Alternate print heads are disclosed in U.S. Pat. No. 6,626,526 (Ueki et al.), and U.S. Pat. Publication Nos. 2006/0044357 (Andersen et al.) and 2009/0061089 (King et al.), which are hereby incorporated by reference. 
     The print head preferably uses a pulse-on-demand method, and can employ one of the following methods to dispense the ink drops: piezoelectric, magnetostrictive, electromechanical, electropneumatic, electrostatic, rapid ink heating, magnetohydrodynamic, or any other technique well known to those skilled in the art. The deposited ink patterns typically undergo a curing step or another processing step before subsequent layers are applied. 
     While inkjet printing is preferred, the term “printing” is intended to include all forms of printing and coating, including: pre-metered coating such as patch die coating, slot or extrusion coating, slide or cascade coating, and curtain coating; roll coating such as knife over roll coating, forward and reverse roll coating; gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; screen printing processes; electrostatic printing processes; thermal printing processes; aerosol printing processes; and other similar techniques. 
       FIG. 6  illustrates the compliant printed circuit  70  removed from the fixture  50  (shown in  FIGS. 1-5 ) and integrated into socket assembly  94 . Conductive traces  64  are electrically coupled to another circuit member  96 , such as for example, a printed circuit board, a test assembly, a packaged integrated circuits, unpackaged integrated circuits, flexible circuits, bare-die devices, organic or inorganic substrates, or any other device capable of carrying electrical current. 
     Exposed portions  80  of the contact members  60  are optionally plated. In another embodiment, the contact members  60  are further processed, such as for example by coining or etching, to facilitate engagement with terminals  82  on singulated die  88 . In operation, force  86  is applied to rear surface  84  of the singulated die  88  so the distal ends  90  of the contact members  60  electrically couple with the terminals  82 . The compliant layer  72  can compensate for non-planarity at the interface  92 . 
       FIG. 7  is a schematic illustration of an alternate socket assembly  100  with gaps  102 ,  104  in dielectric layers  106 ,  108  of the printed compliant circuit  118  in accordance with an embodiment of the present disclosure. In the illustrated embodiment, the gaps  102 ,  104  are located substantially adjacent to contact members  110  to provide a degree of compliance. The gaps  102 ,  104  decouple compliance of contact members  110  from the dielectric layers  106 ,  108 . 
     A height  112  of the contact members  110  can be increased to reduce the chance of a top surface  114  of the dielectric layer  106  contacting IC device  116 . For example, the depth of the cavities  52  in the fixture  50  of  FIG. 1  can be increased to create the longer contact members  110  of  FIG. 7 . 
       FIG. 8  is a schematic illustration of an alternate socket assembly  130  with additional functional layers  132 A,  132 B,  132 C (collectively “ 132 ”) in the compliant printed circuit  142 , in accordance with an embodiment of the present disclosure. The functional layers can be, for example, specialty dielectrics, ground planes, power planes, shielding layers, stiffening layers, capacitive coupling features, circuitry layers, and the like. The layers  132  can be printed or preformed and selectively bonded or non-bonded to provide contiguous material or releasable layers. 
     In the illustrated embodiment, layers  132 A and  132 B are ground planes. Layer  132 C is a compliant layer that operates in either alone or in conjunction with gaps  134  adjacent to the contact members  136  to compensate for non-planarity at the interface  138  with the wafer  140 . 
       FIG. 9  is a schematic illustration of a socket assembly  150  with additional electrical devices  152  located on the printed compliant circuit  164  in accordance with embodiments of the present disclosure. The electrical devices  152  can be capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, an embedded IC, an RF antennae, and the like. The electrical devices  152  can be located on surface  154  or embedded in one of the layers. The socket assembly  150  can include an extension  158 , such as for example a flexible circuit member, electrically coupling conductive traces  160  to another circuit member  156 . As used herein, the term “circuit members” refers to, for example, a packaged integrated circuit device, an unpackaged integrated circuit device, a printed circuit board, a test station, a flexible circuit, a bare-die device, an organic or inorganic substrate, a rigid circuit, or any other device capable of carrying electrical current. 
     The electrical devices  152  can be added as discrete components or printed onto one of the layers. The electrical devices  152  can be printed using inkjet printing technology, aerosol printing technology, or other maskless deposition techniques, as previously described. Electrical devices that are typically located on the test station  156  can be incorporated into the socket assembly  150 , improving electrical performance. 
     In one embodiment, the electrical devices  152  monitor the testing of the circuit member  162  and communicate feedback to the test station  156 . In one embodiment, a feedback signal from the electronic devices  152  can cause the test station  156  to alter the testing protocol depending on the performance of the circuit member  162 , referred to as adaptive testing. In one embodiment, the feedback signal from the electronic devices  152  can cause the test station  156  to alter the circuit member  162 , such as for example, by altering software resident on the circuit member  162 . 
       FIG. 10  is a cross-sectional view of a socket assembly  180  with a multiple layer  182  printed complaint circuit  192  in accordance with an embodiment of the present disclosure. The socket assembly  180  permits IC manufactures to reduce the pitch  184  of the terminals  186  on the IC devices  188  since the required signal routing to a test station  190  is performed by the socket assembly  180 . 
       FIG. 11  is a cross-sectional view of a socket assembly  200  with coupling features  202  printed into the printed compliant circuit  208  in accordance with an embodiment of the present disclosure. In one embodiment, the coupling features  202  can be capacitive couplings located between dielectric layers  204 ,  206 . In another embodiment, the coupling features  202  can be optical fibers supported by the dielectric layers  204 ,  206 . Optical quality materials can optionally be printed directly onto the dielectric layers  204 ,  206 . The printing process can also allow for deposition of coatings in-situ that will enhance the optical transmission or reduce loss. The precision of the printing process can resolve misalignment issues when the optical fibers  202  are placed into a connector. In another embodiment, the coupling features  202  can be embedded coaxial or printed micro strip RF circuits with dielectric layers  204 ,  206 . The dielectric layers  204 ,  206  can be formed of metal. Any of the structures noted above, as well as the contact members  220 , can be created by printing dielectrics and metallization geometry. 
       FIG. 12  illustrates an alternate printed compliant circuit  230  for a socket assembly in accordance with an embodiment of the present disclosure. Optical fibers  232  are located between layers  234 ,  236  of dielectric material. In one embodiment, optical fibers  232  are positioned over printed compliant layer  238 , and dielectric layer  240  is printed over and around the optical fibers  232 . A compliant layer  242  is preferably printed above the optical fiber  232  as well. The compliant layers  238 ,  242  support the optical fibers  232  during flexure. In another embodiment, the dielectric layer  240  is formed or printed with recesses into which the optical fibers  232  are deposited. 
     In another embodiment, optical quality materials  244  are printed during printing of the compliant printed circuit  230 . The optical quality material  244  and/or the optical fibers  232  comprise optical circuit geometries. The printing process allows for deposition of coatings in-situ that enhances the optical transmission or reduces loss. The precision of the printing process reduces misalignment issues when the optical materials  244  are optically coupled with another optical structure. 
       FIG. 13  illustrates another embodiment of a printed compliant circuit  250  for a socket assembly in accordance with an embodiment of the present disclosure. Embedded coaxial RF circuits  252  or printed micro strip RF circuits  254  are located with dielectric/metal layers  256 . These RF circuits  252 ,  254  are preferably created by printing dielectrics and metallization geometry. 
       FIG. 14  illustrates a printed compliant circuit  260  on which damaged contact members are removed and new contact members  262  are re-printed. Although the illustrated embodiment discloses triangular shaped contact members  262 , a variety of other non-triangular shapes can be created using printing technology. 
       FIG. 15  is an alternate socket assembly  300  with additional functionality built into the compliant printed circuit  302  in accordance with an embodiment of the present disclosure. One or more of the layers  304 A,  304 B,  304 C,  304 D, and  304 E (collectively “ 304 ”) can include additional functionality, such as for example, specialty dielectrics, ground planes, power planes, shielding layers, stiffening layers, capacitive coupling features, circuitry layers, and the like. The layers  304  can be printed or preformed and selectively bonded or non-bonded to provide contiguous material or releasable layers. 
     The additional functionality can also be provided by additional electrical devices  306 , preferably positioned adjacent to opening  308  in socket housing  310  that receives the IC device  312 . The electrical devices  306  can be shielding, near device decoupling, capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, embedded IC, RF antennae, and the like. The electrical devices  306  can be added as discrete components or printed onto one of the layers. The electrical devices  306  can include passive or active functional elements. Passive structure refers to a structure having a desired electrical, magnetic, or other property, including but not limited to a conductor, resistor, capacitor, inductor, insulator, dielectric, suppressor, filter, varistor, ferromagnet, and the like. 
     In one embodiment, the compliant printed circuit  302  extends beyond a perimeter edge  314  of the socket housing  310 . In one embodiment, extension  316  including a flexible circuit member can be electrically coupled to the compliant printed circuit  302 . In the illustrated embodiment, the compliant printed circuit  302  is electrically coupled to test station  320  via the extension  316 . The testing protocol can reside in the electrical device  306  or the test station  320 , or a combination thereof. The test station  320  can be, for example, a logic analyzer, a PC-based test platform, and the like. 
     In one embodiment, the electrical device  306  monitors the testing of the IC device  312  and communicates feedback to test station  320 . In one embodiment, the feedback signal from the electrical devices  306  can cause the test station  320  to alter the testing protocol based on the performance of the IC device  312 . This methodology is also referred to as adaptive testing. In one embodiment, the feedback signal from the electrical devices  306  can cause the test station  320  to alter the IC device  312 , such as for example, by altering software resident on the IC device  311 . 
       FIG. 16  illustrates the use of pick and place system  350  to position singulated die  352  relative to socket assembly  354  in accordance with an embodiment of the present disclosure. Due to the fine pitch of terminals  356 , edge alignment of the singulated die  352  is not likely reliable in many cases. Pick and place system  350  with split vision or optical alignment is used to align die terminals  356  to the contact tips  358 . Pick up chuck  360  is optionally used to apply load or provide thermal management. 
     In the illustrated embodiment, contact tips  358  are shaped to facilitate electrical coupling with protruding terminals  356  on the singulated die  352 . In one embodiment, shape of the contact tips  358  is established by altering the shape of cavities  52  in fixture  50  (see e.g.,  FIG. 1 ). In another embodiment, the shape of the contact tips  358  can be created using the additive printing processes discussed herein. 
     Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range is encompassed within the embodiments of the present disclosure. The upper and lower limits of these smaller ranges which may independently be included in the smaller ranges is also encompassed within the embodiments of the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either both of those included limits are also included in the embodiments of the invention. 
     Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the invention belong. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the embodiments of the present disclosure, the preferred methods and materials are now describe. All patents and publications mentioned herein, including those cited in the Background of the application, are hereby incorporated by reference to disclose and described the methods and/or materials in connection with which the publications are cited. 
     The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the embodiments of the present disclosure are not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed. 
     Other embodiments of the invention are possible. Although the description above contains much specificity, these should not be construed as limiting the scope of the invention, but as merely providing illustrations of some of the presently preferred embodiments of this invention. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments of the present disclosure. Thus, it is intended that the scope of at least some of the present disclosure herein disclosed should not be limited by the particular disclosed embodiments described above. 
     Thus, the scope of this invention should be determined by the appended claims and their legal equivalents. Therefore, it will be appreciated that the scope of the present disclosure fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present disclosure is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural, chemical, and functional equivalents to the elements of the above-described preferred embodiment that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present disclosure, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims.