Patent Publication Number: US-7916804-B2

Title: Method and system for a fast-switching phase-locked loop using a direct digital frequency synthesizer

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE 
     This application is a continuation of U.S. application Ser. No. 11/680,253 filed on Feb. 28, 2007, which is hereby incorporated by reference. 
     Each of the above referenced applications is hereby incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     Certain embodiments of the invention relate to signal processing for communication systems. More specifically, certain embodiments of the invention relate to a method and system for a fast-switching Phase-locked Loop using a Direct Digital Frequency Synthesizer. 
     BACKGROUND OF THE INVENTION 
     A Direct Digital Frequency Synthesizer (DDFS) is a digitally-controlled signal generator that may vary the output signal frequency over a large range of frequencies, based on a single fixed-frequency precision reference clock. In addition, a DDFS is also phase-tunable. In essence, within the DDFS, discrete amplitude levels are fed to a Digital-to-Analog Converter (DAC) at a sampling rate determined by the fixed-frequency reference clock. The output of the DDFS provides a signal whose shape depends on the sequence of discrete amplitude levels that are fed to the DAC at the constant sampling rate. The DDFS is particularly well suited as a frequency generator that outputs a sine or other periodic waveforms over a large range of frequencies, from almost DC to approximately half the fixed-frequency reference clock frequency. 
     A DDFS offers a larger range of operating frequencies and requires no feedback loop, thereby providing near instantaneous phase- and frequency changes, avoiding over- and undershooting and settling time issues associated with another analog systems. A DDFS may provide precise digitally-controlled frequency and/or phase changes without signal discontinuities. 
     In some communication systems, inphase and quadratrue channels are modulated onto a carrier frequency that may be generated and controlled in an analog Phase-Locked Loop comprising a phase detector, a loop filter, an amplifier and a voltage controlled oscillator in a feedback-loop configuration. These analog PLLs are limited to operations within a narrow range of frequencies, sometimes referred to as the lock range. Furthermore, because of the feedback-loop configuration, any change in frequency may require the analog PLL to transition to a new steady-state. Hence, the rate of frequency changes may be limited to how fast the analog PLL may settle. For these reasons, some analog PLLs may not be suited to wideband operations with fast-switching of frequencies. 
     Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings. 
     BRIEF SUMMARY OF THE INVENTION 
     A method and/or system for a fast-switching Phase-locked Loop using a Direct Digital Frequency Synthesizer, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
     These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1A  is a diagram illustrating an exemplary WLAN and Bluetooth® wireless communication system, in connection with an embodiment of the invention. 
         FIG. 1B  is a block diagram illustrating an exemplary Direct Digital Frequency Synthesizer (DDFS), in connection with an embodiment of the invention. 
         FIG. 2  is block diagram illustrating an exemplary embodiment of a variable carrier frequency modulator for an inphase and quadrature channel, in accordance with an embodiment of the invention. 
         FIG. 3  is a block diagram illustrating an exemplary embodiment of a fast-switching wideband PLL oscillator using a DDFS, in accordance with an embodiment of the invention. 
         FIG. 4  is a flow chart illustrating overall functionality, in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Certain embodiments of the invention may be found in a method and system for a fast-switching Phase-locked Loop using a Direct Digital Frequency Synthesizer. Aspects of a method and system for a fast-switching Phase-locked Loop using a Direct Digital Frequency Synthesizer may include generating a second signal from a first signal by: frequency translating an inphase component of the first signal utilizing a filtered fast-switching oscillating signal generated using at least a direct digital frequency synthesizer (DDFS), and frequency translating a corresponding quadrature component of the first signal utilizing a phase-shifted version of the generated and filtered fast-switching oscillating signal. The filtered fast-switching oscillating signal may be generated by filtering a fast-switching oscillating signal. 
     The inphase and quadrature components of the first signal may be multiplied with the filtered fast-switching oscillating signal and a phase-shifted version of the filtered fast-switching oscillating signal, respectively. The filtered fast-switching oscillating signal may be obtained by removing at least one frequency-sum term of the fast-switching oscillating signal, where the fast-switching signal oscillating signal may be generated from a signal generated by the DDFS that may be multiplied with an oscillating reference signal. The oscillating reference signal may comprise a fixed-frequency. By frequency-dividing a high-frequency oscillating signal, the fixed-frequency oscillating reference signal may be generated. The DDFS may be clocked by the high-frequency oscillating signal. The second signal may be generated during demodulation or during modulation of the first signal. Filtering of the fast-switching oscillating signal may utilize a high-pass filter, a low-pass filter or a switchable filter that switches between high-pass and low-pass filtering characteristics. 
       FIG. 1A  is a diagram illustrating an exemplary WLAN and Bluetooth® wireless communication system, in connection with an embodiment of the invention. Referring to  FIG. 1 , there is shown a WLAN access point  112   b , a computer  110   a , a Bluetooth® headset  114   a , a router  130 , the Internet  132  and a web server  134 . The computer or host device  110   a  may comprise a wireless LAN (WLAN) radio  111   a , a Bluetooth® radio  111   b , a host processor  111   c , and a host memory  111   d . There is also shown a Wireless LAN (WLAN) connection between the wireless LAN radio  111   a  and the wireless LAN access point  112   b , and a Bluetooth® wireless connection between the Bluetooth® radio  111   b  and the Bluetooth® headset  114   a.    
     Frequently, computing and communication devices may comprise hardware and software to communicate using multiple wireless communication standards. The WLAN radio  111   a  may be compliant with IEEE 802.11 standard. There may be instances when the WLAN radio  111   a  and the Bluetooth® radio  111   b  may be active concurrently. For example, it may be desirable for a user of the computer or host device  110   a  to access the Internet  132  in order to consume streaming content from the Web server  134 . Accordingly, the user may establish a WLAN connection between the computer  110   a  and the access point  112   b . Once this connection is established, the streaming content from the Web server  134  may be received via the router  130 , the access point  112   b , and the WLAN connection, and consumed by the computer or host device  110   a.    
     It may be further desirable for the user of the computer  110   a  to listen to an audio portion of the streaming content on the Bluetooth® headset  114   a . Accordingly, the user of the computer  110   a  may establish a Bluetooth® wireless connection with the Bluetooth® headset  114   a . Once the Bluetooth® wireless connection is established, and with suitable configurations on the computer enabled, the audio portion of the streaming content may be consumed by the Bluetooth® headset  114   a . In instances where such advanced communication systems are integrated or located within the host device  110   a , the RF frequency generation may support fast-switching to enable support of multiple communication standards and/or advanced wideband systems like, for example, Ultrawideband (UWB) radio. 
       FIG. 1B  is a block diagram illustrating an exemplary Direct Digital Frequency Synthesizer (DDFS), in connection with an embodiment of the invention. Referring to  FIG. 1B , there is shown a DDFS  100 , a clock  102  and a DDFS controller  104 . There is also shown a digital input signal d(t) and an analog output signal g(t). 
     The DDFS  100  may be a digitally-controlled signal generator that may vary the analog output signal g(t) over a large range of frequencies, based on a single fixed-frequency precision reference clock, which may be clock  102 . In addition, the DDFS  100  is also phase-tunable. The digital input signal d(t) may comprise control information about the frequency and/or phase of the analog output signal g(t) that may be generated as a function of the digital input signal d(t). The clock  102  may provide a reference clock that may be N times higher than the frequency fc that may be generated at the output signal g(t). Using the clock  102  and the information that may be contained in the digital input signal d(t), the DDFS controller  104  may generate a variable frequency analog output signal g(t). 
       FIG. 2  is block diagram illustrating an exemplary embodiment of a variable carrier frequency modulator for an inphase and quadrature channel, in accordance with an embodiment of the invention. Referring to  FIG. 2 , there is shown a variable carrier frequency modulator  200  that may be coupled to an antenna  216 . The variable carrier frequency modulator  200  may comprise a carrier frequency control  202 , a Phase-Locked Loop (PLL) oscillator  210 , multipliers  204  and  208 , a phase shift block  206 , a summation block  212 , and a filter  214 . There is also shown an inphase (I) channel signal, a quadrature (Q) channel signal, a PLL control signal d(t), a carrier frequency signal f C (t), a modulated I-channel signal RFI, and a modulated Q-channel signal RFQ. 
     In some communication systems, the I-channel and the Q-channel may be modulated onto the carrier frequency separately and may be added after modulation and before transmission. The I-channel signal may be modulated onto the carrier frequency signal s C (t) by multiplying the I-channel signal with the carrier frequency signal s C (t) in the multiplier  204 . The output signal of multiplier  204  may be the modulated I-channel signal RFI. The Q-channel signal may be modulated onto a phase-shifted carrier frequency signal by multiplying the Q-channel signal with the phase-shifted carrier frequency signal in the multiplier  208 . The phase-shifted carrier frequency may be obtained by shifting the phase of the carrier frequency signal s C (t) in phase shift block  206 . The phase shift block  206  may, for example, shift the phase of the carrier frequency signal by 90 degrees. The output signal of the multiplier  208  may be the modulated Q-channel signal RFQ. The PLL oscillator  210  may be controlled by the carrier frequency control  202  via the PLL control signal d(t). In some transmission systems, the carrier frequency signal s C (t) may change quickly; for example in Orthogonal Frequency Division Multiplexing (OFDM) systems. In other systems, the carrier frequency control  202  may select one of a few, rarely changing transmission channels. 
       FIG. 3  is a block diagram illustrating an exemplary embodiment of a fast-switching wideband PLL oscillator using a DDFS, in accordance with an embodiment of the invention. Referring to  FIG. 3 , there is shown a carrier frequency control  302  and a fast-switching PLL  310 . The fast-switching PLL  310  may comprise a reference oscillator  304 , a Direct Digital Frequency Synthesizer (DDFS)  306 , a frequency divider  308 , a multiplier  310  and a filter  312 . There is also shown a DDFS control signal d(t), a reference frequency signal s REF , a DDFS output signal s D (t), a divided reference frequency signal s′ REF , an unfiltered carrier frequency signal s C1 (t), and a carrier frequency signal s C (t). 
     The carrier frequency control  302  and the fast-switching PLL  310  may be an exemplary embodiment of the carrier frequency control  202  and the PLL oscillator  210  of the variable carrier frequency modulator  200  illustrated in  FIG. 2 . An embodiment of the invention illustrated in  FIG. 3  may also be used in a receiver structure instead of a transmitter structure as shown in  FIG. 2 . 
     The carrier frequency control  302  may comprise suitable logic, circuitry and/or code that may be enabled to generate a DDFS control signal d(t). In an embodiment of the invention, the DDFS control signal d(t) may be equal to the PLL control signal d(t) in  FIG. 2 . Because the DDFS  306  may be controlled by a digital control signal, the DDFS control signal d(t) that may be generated by the carrier frequency control  302  may be digital. The DDFS control signal d(t) may comprise information that may allow controlling the output frequency f D (t) and phase of the DDFS output signal s D (t). The frequency f D (t) may be time-varying, for example, because the carrier frequency may change quickly. The DDFS output signal s D (t) may be approximately sinusoidal. 
     In accordance with an embodiment of the invention, the DDFS  306  may be driven by a fixed-frequency reference frequency signal s REF , which may be a higher frequency f REF  than the frequency f D (t) of the DDFS output signal s D (t). The reference frequency signal s REF  may be generated by the reference oscillator  304 . The reference frequency signal s REF  generated in the reference oscillator  304  may also be divided by a factor N in the frequency divider  308  to generate the divided reference frequency signal S′ REF . The divided reference frequency signal S′ REF  may be used to translate the DDFS output signal s D (t) in frequency. This may be achieved by multiplying in multiplier  310  the divided reference frequency signal S′ REF  with s D (t) to generate the unfiltered carrier frequency signal s C1 (t). The carrier frequency signal s C (t) may be obtained by filtering the unfiltered carrier frequency signal s C1 (t) in filter  312 . 
     An embodiment of the invention may offer a higher signal quality and higher carrier frequencies than generation of the carrier frequency signal f C (t) directly in the DDFS  306 . The DDFS  306  may comprise a Digital-to-Analog converter that may output a new signal level every 1/f REF  seconds. Hence, as the frequency f D (t) of the DDFS output signal s D (t) may vary while the rate of signal level changes of s D (t) may remain constant, the number of samples per period of the DDFS output signal s D (t) may vary and may be given by f REF /f D (t) samples per period of the frequency signal s D (t). Due to the digital-to-analog conversion, the frequency signal s D (t) may resemble, for example, an ideal sinusoid more closely with an increasing number of samples per period, that is, with increasing f REF /f D (t). A high carrier frequency f C (t) of good signal quality may be achieved through frequency translation in the multiplier  310 , as shown in the following relationship: 
                                   s     C   ⁢           ⁢   1       ⁡     (   t   )       =       ⁢         s   REF   ′     ⁡     (   t   )       ·       s   D     ⁡     (   t   )                     =       ⁢       cos   ⁡     (     2   ⁢   π   ⁢       f   REF     N     ⁢   t     )       ·     cos   ⁡     (     2   ⁢   π   ⁢           ⁢       f   D     ⁡     (   t   )       ⁢   t     )                     =       ⁢       1   2     ⁡     [       cos   ⁡     (     2   ⁢     π   ⁡     (         f   REF     N     -         f   D     ⁡     (   t   )       ⁢   t       )         )       +     cos   ⁡     (     2   ⁢     π   ⁡     (         f   REF     N     +         f   D     ⁡     (   t   )       ⁢   t       )         )         ]                       (   1   )               
Hence, after multiplication, the unfiltered carrier frequency signal s C1 (t) may contain frequency components corresponding to the sum and difference of the frequencies f D (t) and f REF /N. By low-pass filtering the unfiltered carrier frequency signal s C1 (t) in filter  312 , the difference component may be removed and the carrier frequency s C (t) may be obtained:
 
     
       
         
           
             
               
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     For example, with a reference frequency f REF =24 GHz, as may be achieved with modern semiconductor manufacturing processes of, for example, 45 nm, f D (t) may, for example, vary from 0-4 GHz and may have at least f REF /max{f D (t)}=6 samples per period. The frequency divider  308  may generate, for example, a signal s′ REF (t) with N=4 that may be of frequency f REF /N=6 GHz. As illustrated in this example, the carrier frequency f C (t) may be varied from 6-10 GHz. 
     In another embodiment of the invention, the filter  312  may be replaced by a filter that may comprise switchable high-pass and low-pass filter characteristics. In this regard, the filter  312  may be enabled to switch so that it possesses low-pass characteristics or switch so that it possesses high-pass characteristics. In these instances, the switchable filter  312  may filter out either the sum or difference component in equation (1) above and therefore may extend the achievable frequency range f C (t). For example, if f D (t) may vary from 0-4 GHz, f REF /N=6, as illustrated in the example above, the frequency may range from 6-10 GHz when the switchable filter  312  may be a low-pass filter and from 2-6 GHz when the switchable filter  312  may be a high-pass filter. In these instances, the fast-switching PLL  310  may vary its carrier frequency from 2 GHz to 10 GHz. 
       FIG. 4  is a flow chart illustrating overall functionality, in accordance with an embodiment of the invention. Referring to  FIG. 4 , there is shown a start step  402 , process steps  404 ,  406 ,  408 ,  410 ,  412 ,  414  and  416 , and an end step  418 . 
     In accordance with an embodiment of the invention, a signal s D (t) that may be fast-varying may be generated in process step  404 . This process may correspond to the output of the DDFS  306  shown in  FIG. 3 . sD(t) may be modulated onto s′ REF  in process step  506  to generate the unfiltered carrier signal s C1 (t). In step  508 , a high or low frequency-sum component may be removed from the unfiltered carrier frequency signal s C1 (t) to generate s C (t), the carrier frequency signal illustrated in  FIG. 3 . In step  514 , the I-channel data may be modulated onto the carrier frequency signal s C (t). In step  510 , the carrier frequency signal s C (t) may be phase-shifted to generate a carrier signal appropriate for modulation of the Q-channel in step  512 . In step  516 , the modulated I-channel and the modulated Q-channel signals may be added to form an RF signal that may be suitable for transmission. 
     In accordance with an embodiment of the invention, a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency Synthesizer may include generating a second signal from a first signal by: frequency translating in  204  an inphase component of the first signal utilizing a filtered fast-switching oscillating signal generated using a direct digital frequency synthesizer (DDFS)  210  and frequency translating in  208  a corresponding quadrature component of the first signal utilizing a phase-shifted version of the generated filtered fast-switching oscillating signal, as illustrated in  FIG. 2 . The filtered fast-switching oscillating signal s C (t) may be generated by filtering a fast-switching oscillating signal in filter  312 , shown in  FIG. 3 . The inphase and quadrature components of the first signal may be multiplied with the filtered fast-switching oscillating signal and a phase-shifted version of the filtered fast-switching oscillating signal, respectively as illustrated in  FIG. 2  and  FIG. 4 . The filtered fast-switching oscillating signal s C (t) may be obtained by removing at least one frequency-sum term of the fast-switching oscillating signal s C1 (t) by filter  312 , where the fast-switching signal oscillating signal s C1 (t) may be generated from a signal s D (t) generated by the DDFS  306  that may be multiplied with an oscillating reference signal s′ REF . The oscillating reference signal S′ REF  may comprise a fixed-frequency. By frequency-dividing, as shown in block  308  in  FIG. 3 , a high-frequency oscillating signal s REF , the fixed-frequency oscillating reference signal s′ REF  may be generated. The DDFS  308  may be clocked by the high-frequency oscillating signal s REF . The second signal may be generated during demodulation or during modulation of the first signal, as shown in  FIG. 2 . Filtering of the fast-switching oscillating signal may utilize a high-pass filter  302 , a low-pass filter  302  or a switchable filter  302  that switches between high-pass and low-pass filtering characteristics, as illustrated in  FIG. 3 . 
     Another embodiment of the invention may provide a machine-readable storage, having stored thereon, a computer program having at least one code section executable by a machine, thereby causing the machine to perform the steps as described above for a Method and System for a fast-switching Phase-locked Loop using a Direct Digital Frequency Synthesizer. 
     Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. 
     The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form. 
     While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.