Patent Publication Number: US-2023163082-A1

Title: Electronic package and manufacturing method thereof

Description:
BACKGROUND 
     1. Technical Field 
     The present invention relates to a semiconductor device, and more particularly, to a warpage-proof electronic package and a manufacturing method thereof. 
     2. Description of Related Art 
     With the vigorous development of portable electronic products in recent years, various related products have been gradually developing toward high-density, high-performance, and being light, thin, short, and small. Various types of semiconductor packaging structures that are applied to the portable electronic products are thus rolled out, in order to meet the demands for lightweight, thinness, small size and high-density. 
       FIG.  1    is a schematic cross-sectional view of a conventional semiconductor package  1 . As shown in  FIG.  1   , the semiconductor package  1  is provided with at least one semiconductor chip  11  disposed on a packaging substrate  10  in a flip chip manner, at least one dummy block  12  provided around the semiconductor chip  11  on the packaging substrate  10 , a packaging layer  14  formed on the packaging substrate  10  to cover the semiconductor chip  11 , and then a plurality of solder balls  17  formed under the packaging substrate  10  to connect to a circuit board (not shown in the figure). 
     In the aforementioned semiconductor package  1 , a mismatch between the coefficients of thermal expansion (CTE) of the semiconductor chip  11  and the packaging layer would easily result in non-uniform thermal stress, causing the packaging layer  14  to warp during thermal cycles. Therefore, the dummy block  12  is arranged around the semiconductor chip  11  to reduce the degree of warpage. 
     In the conventional semiconductor package  1 , however, the dummy block  12  occupies a very large surface area of the packaging substrate  10 , leaving no space to arrange other electronic components on the surface of this area. Therefore, if there are demands for other electronic components, the size of the packaging substrate  10  needs to be increased to arrange the required wiring layers. This could hardly meet the demand for miniaturization, but increases manufacturing costs. 
     Therefore, how to overcome the above-mentioned problems of the prior art has become an urgent issue to be solved at present. 
     SUMMARY 
     In view of the various deficiencies of the prior art, the present invention provides an electronic package comprising: a wiring structure; at least one electronic component provided on and electrically connected to the wiring structure; a packaging layer formed on the wiring structure to cover the electronic component, wherein the packaging layer has a first surface and a second surface opposite to each other and side surfaces adjacent to the first and second surfaces, and the packaging layer is bonded to the wiring structure via its second surface; and a frame body embedded in the packaging layer, wherein the frame body neither contacts the wiring structure nor covers the electronic component. 
     The present invention also provides a manufacturing method of an electronic package, comprising: providing a frame body and at least one electronic component on a wiring structure, wherein the frame body neither contacts the wiring structure nor covers the electronic component; and forming a packaging layer on the wiring structure such that the packaging layer covers the electronic component and the frame body, wherein the packaging layer has a first surface and a second surface opposite to each other and side surfaces adjacent to the first and second surfaces, so that the packaging layer is bonded to the wiring structure via its second surface. 
     In the aforementioned electronic package and manufacturing method thereof, the electronic component is exposed from the first surface of the packaging layer. 
     In the aforementioned electronic package and manufacturing method thereof, the frame body is exposed from the side surface and/or the first surface of the packaging layer. 
     In the aforementioned electronic package and manufacturing method thereof, the frame body is flush with the side surface and/or the first surface of the packaging layer. 
     In the aforementioned electronic package and manufacturing method thereof, the frame body is made of a metal or semiconductor material. 
     In the aforementioned electronic package and manufacturing method thereof, the frame body has a ring shape to surround the electronic component. 
     In the aforementioned electronic package and manufacturing method thereof, the frame body is suspended on the wiring structure. 
     In the aforementioned electronic package and manufacturing method thereof, the frame body is provided on the wiring structure by supporting legs. 
     The aforementioned electronic package and manufacturing method thereof further comprise another electronic component provided on the wiring structure, and the another electronic component is covered by the frame body. 
     The aforementioned electronic package and manufacturing method thereof further comprise a shielding layer formed on the packaging layer. 
     In the aforementioned electronic package and manufacturing method thereof, the frame body has a plurality of opening areas, and a plurality of the electronic components are provided on the wiring structure, so that the plurality of the electronic components are respectively exposed from the plurality of opening areas. 
     It can be seen from the above that the electronic package and manufacturing method thereof of the present invention mainly use the frame body to disperse thermal stress, so that warpage of the packaging layer can be avoided during thermal cycles. Additionally, other electronic components can be arranged around the electronic component. Therefore, compared with the prior art, the electronic package of the present invention allows for the arrangement of required wirings on the surface of the wiring structure without increasing the size of the wiring structure. Such advantages not only meet the demand for miniaturization, but also reduce manufacturing costs. 
    
    
     
       BRIEF DESCRIOPTION OF THE DRAWINGS 
         FIG.  1    is a schematic cross-sectional view of a conventional semiconductor package. 
         FIGS.  2 A to  2 D  are schematic cross-sectional views of a first embodiment of a manufacturing method of an electronic package of the present invention. 
         FIG.  3 A  is a schematic cross-sectional view of a top view of  FIG.  2 D . 
         FIG.  3 B  is a schematic view of another aspect of  FIG.  3 A . 
         FIG.  3 C  is a schematic view of another aspect of  FIG.  3 B . 
         FIG.  3 C- 1    is a schematic cross-sectional view of  FIG.  3 C  taken along X-X. 
         FIG.  3 C- 2    is a schematic cross-sectional view of  FIG.  3 C  taken along Z-Z. 
         FIGS.  4 A- 1  and  4 A- 2    are schematic views of another aspect of  FIGS.  3 C- 1  and  3 C- 2   . 
         FIG.  4 B  is a schematic view of another aspect of  FIG.  4 A- 1   . 
         FIG.  4 C  is a schematic view of another aspect of  FIG.  4 B . 
         FIG.  5 A  is a schematic cross-sectional view of a second embodiment of a manufacturing method of an electronic package of the present invention. 
         FIGS.  5 B and  5 C  are schematic views of other different aspects of  FIG.  5 A . 
         FIG.  6 A  is a schematic cross-sectional view of a third embodiment of a manufacturing method of an electronic package of the present invention. 
         FIGS.  6 B and  6 C  are schematic views of other different aspects of  FIG.  6 A . 
         FIG.  7 A  is a schematic cross-sectional view of a fourth embodiment of a manufacturing method of an electronic package of the present invention. 
         FIG.  7 B  is a schematic view of a different aspect of  FIG.  7 A . 
         FIG.  8 A- 1    is a schematic cross-sectional view of a fifth embodiment of a manufacturing method of an electronic package of the present invention. 
         FIG.  8 A- 2    is a schematic cross-sectional view of a top view of  FIG.  8 A- 1   . 
         FIG.  8 B- 1    is a schematic cross-sectional view of another aspect of  FIG.  8 A- 1   . 
         FIG.  8 B- 2    is a schematic cross-sectional view of a top view of  FIG.  8 B- 1   . 
     
    
    
     DETAILED DESCRIPTIONS 
     The following describes the implementation of the present invention with specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. 
     It should be understood that, the structures, ratios, sizes, and the like depicted in the accompanying figures are all used only to illustrate the contents disclosed in the present specification for one skilled in the art to read and comprehend rather than to limit the conditions for practicing the present disclosure. Therefore, these structures, ratios, sizes and the like carry no substantial technical meanings. Any modification of the structure, alteration of the ratio relationship, or adjustment of the size without affecting the possible effects and achievable proposes of the present invention should still be deemed as falling within the scope of the technical disclosure of the present invention. Meanwhile, terms such as “upper,” “first,” “second,” “a” and the like used herein are used merely for clear explanation rather than limiting the practicable scope of the present disclosure, and thus, any alterations or adjustments of the relative relationships thereof without essentially altering the technical contents should be considered in the practicable scope of the present disclosure. 
       FIGS.  2 A to  2 D  are schematic cross-sectional views of a first embodiment of a manufacturing method of an electronic package  2  of the present invention. 
     As shown in  FIG.  2 A , a wiring structure  20  which has a first side  20   a  (such as an upper side) and a second side  20   b  (such as a lower side) opposite to each other is provided, and at least one supporting structure  2   a  is provided on the first side  20   a  of the wiring structure  20 . 
     In this embodiment, the wiring structure  20  is, for example, a packaging substrate with a core layer and a wiring layer, a coreless packaging substrate, a through-silicon interposer (TSI) with through-silicon vias (TSV), or other types of plate having at least one insulating layer and at least one wiring layer, e.g., a fan out type redistribution layer (RDL), bonded to the insulating layer. For example, the material forming the wiring layer is copper, and the material forming the insulating layer is, for example, a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP). It should be understood that the wiring structure  20  can also be other sheets carrying chips, such as a lead frame, a wafer, or other boards having metal routing, and is not limited to the above. 
     Furthermore, the supporting structure  2   a  is a metal frame of, for example, copper or a semiconductor frame of, for example, silicon or glass, which has at least one supporting leg  22  combined with the wiring structure  20  and at least one frame body  23  provided on the supporting legs  22 . For example, the supporting leg  22  is adhered to the first side  20   a  of the wiring structure  20  by a bonding material  220  such as glue, and the frame body  23  has an opening area  230  to have the first side  20   a  of the wiring structure  20  exposed therefrom. 
     As shown in  FIG.  2 B , at least one electronic component  21  is provided on the first side  20   a  of the wiring structure  20 , and the electronic component  21  is exposed in the opening area  230 . 
     In this embodiment, the electronic component  21  is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the electronic component  21  is a semiconductor chip, which has an active surface  21   a  and an inactive surface  21   b  opposite to each other, wherein electrode pads (not shown in the figure) of the active surface  21   a  are arranged on the wiring structure  20  in a flip chip manner by a plurality of conductive bumps  210  such as solder materials, metal pillars or the like, and are electrically connected to the wiring layer of the wiring structure  20 , and then the conductive bumps  210  are covered with a underfill  211 ; alternatively, the electronic component  21  can be electrically connected to the wiring layer of the wiring structure  20  through a plurality of bonding wires (not shown in the figure) by means of wire bonding; and alternatively, the electronic component  21  can directly contact the wiring layer of the wiring structure  20 . Therefore, desired types and quantity of electronic components can be connected to the wiring structure  20  to improve its electrical performance. There are various ways, not limited to the above, to electrically connect the electronic component  21  to the wiring structure  20 . 
     Furthermore, the electronic component  21  is aligned with the opening area  230 , such that the frame body  23  surrounds the electronic component  21 , and the inactive surface  21   b  is completely exposed from the opening area  230 . For example, a height H 1  of the electronic component  21  relative to the first side  20   a  of the wiring structure  20  is greater than a height H 2  of the supporting structure  2   a  relative to the first side  20   a  of the wiring structure  20 . 
     As shown in  FIG.  2 C , a packaging layer  24  is formed on the first side  20   a  of the wiring structure  20 , such that the packaging layer  24  covers the support structure  2   a  and the electronic component  21 , wherein the packaging layer  24  has a first surface  24   a  and a second surface  24   b  opposite to each other, the electronic component  21  is exposed on the first surface  24   a  of the packaging layer  24 , and the packaging layer  24  is bonded to the first side  20   a  of the wiring structure  20  via its second surface  24   b.    
     In this embodiment, the packaging layer  24  is an insulating material, such as polyimide (PI), dry film, encapsulant such as epoxy, or a packaging material (molding compound). For example, the packaging layer  24  can be formed on the first side  20   a  of the wiring structure  20  by a process selected from liquid compound, injection, lamination or compression molding, and the like. 
     Furthermore, partial materials of the packaging layer  24  (even partial materials of the inactive surface  21   b  of the electronic component  21 ) can be removed by a planarization process, such as polishing, to make the first surface  24   a  of the packaging layer  24  flush with the inactive surface  21   b  of the electronic component  21 , so that the inactive surface  21   b  of the electronic component  21  is exposed from the first surface  24   a  of the packaging layer  24 . 
     As shown in  FIG.  2 D , the supporting leg  22  is used as a cutting path S (as shown in  FIG.  2 C ) to perform a singulation process therealong, so that the packaging layer  24  defines side surfaces  24   c  adjacent to the first and second surfaces  24   a,    24   b,  so as to produce the electronic package  2  of the present invention. 
     In this embodiment, a plurality of conductive components  27  can be formed on the second side  20   b  of the wiring structure  20 , so that the conductive components  27  are electrically connected to the wiring layer of the wiring structure  20 . 
     Furthermore, the frame body  23  is exposed on the side surfaces  24   c  of the packaging layer  24 , and the shape of a top surface of the frame body  23  can be a general ring shape (as shown in  FIG.  3 A ) or a ring shape with missing corners A (as shown in  FIG.  3 B ) or a ring with toothed edges (as shown in  FIG.  3 C ). For example, the frame body  33  with a tooth-edged ring has tooth portions  330  and a ring portion  33   a.  The tooth portions  330  are exposed from the side surfaces  24   c  of the packaging layer  24  (as shown in  FIG.  3 C- 1   ), and the ring portion  33   a  is embedded in the packaging layer  24  without being exposed from the side surfaces  24   c  of the packaging layer  24  (as shown in  FIG.  3 C- 2   ). 
     Alternatively, as shown in  FIGS.  4 A- 1  and  4 A- 2   , the frame body  43  (for example, a frame body with a tooth-edged ring) may also be exposed from the first surface  24   a  of the packaging layer  24 . A planarization process can be employed to remove, by polishing, partial materials of the packaging layer  24  and partial materials of the inactive surface  21   b  of the electronic component  21  (even partial surfaces of the frame body  43 ), to make the first surface  24   a  of the packaging layer  24  flush with the inactive surface  21   b  of the electronic component  21  and a surface  43   a  of the frame body  43 , so that the inactive surface  21   b  of the electronic component  21  and the frame body  43  are exposed from the first surface  24   a  of the packaging layer  24 . It should be understood that, as in an electronic package  4   b  shown in  FIG.  4 B , an inactive surface  41   b  of the electronic component  21  can also be embedded in the first surface  24   a  of the packaging layer  24 , and only the surface  43   a  of the frame body  43  is exposed therefrom. Therefore, the inactive surface  41   b  of the electronic component  21  and the frame body  23  may be unexposed from the first surface  24   a  of the packaging layer  24  at the same time, as shown in  FIG.  4 C . 
     In addition, at least one passive component  35  can also be arranged on the first side  20   a  of the wiring structure  20 , as shown in  FIG.  3 C- 1   , such that the frame body  33  covers the passive component  35 . It should be understood that at least one passive component  25  can also be arranged on the second side  20   b  of the wiring structure  20  as required, as shown in  FIG.  2 D . 
     Therefore, the manufacturing method of the present invention employs mainly a design of the frame body  23 ,  33 , and  43  to disperse thermal stress and avoid warpage during thermal cycles. 
     Furthermore, the frame body  23 ,  33 ,  43  is suspended on the first side  20   a  of the wiring structure  20 , and thus does not occupy a surface area of the first side  20   a  of the wiring structure  20 , so as to facilitate the arrangement of other electronic components (such as the passive component  35 ) around the electronic component  21 , wherein the frame body  33 ,  43  covers the passive component  35 . Therefore, compared with the prior art, the electronic package  2 ,  3 ,  4 ,  4   b  of the present invention can have required wirings arranged on the surface of the first side  20   a  of its wiring structure  20  without increasing the size of the first side  20   a  of the wiring structure  20 . Consequently, the electronic package of the present application can not only meet the demand for miniaturization, but also reduce manufacturing costs. 
       FIGS.  5 A to  5 C  are schematic cross-sectional views of a second embodiment of a manufacturing method of an electronic package  5  of the present invention. The difference between this embodiment and the first embodiment lies in the singulation process, so the similarities will not be repeated in the following. 
     As shown in  FIG.  5 A , the singulation process is performed along the periphery of the supporting structure  2   a  (the cutting path L shown in  FIG.  2 C ) to produce the electronic package  5  of the present invention, and the supporting leg  22  of the supporting structure  2   a  is retained. 
     In this embodiment, the supporting structure  2   a  is embedded completely in the packaging layer  24  without being exposed from the packaging layer  24 . In another embodiment, as in an electronic package  5   b  shown in  FIG.  5 B , the frame body  23  of the supporting structure  2   a  can be exposed from the first surface  24   a  of the packaging layer  24 . 
     It should be understood that the cutting path of the singulation process can be set according to requirements, such as an electronic package  5   c  shown in  FIG.  5 C  (with the supporting leg  22  partially retained), and there is no particular limitation. 
     Therefore, the manufacturing method of the present invention employs mainly a design of the frame body  23  to disperse thermal stress and avoid warpage during thermal cycles. 
     Furthermore, the frame body  23  is provided on the first side  20   a  of the wiring structure  20  by the supporting leg  22 , and a width R of the supporting leg  22  is much smaller than a width D of the conventional dummy block  12  (as shown in  FIG.  1   ). As a result, the supporting leg  22  occupies very little surface area of the wiring structure  20 , facilitating the arrangement of other electronic components (such as the passive component  35 ) around the electronic component  21 , wherein the passive component  35  is covered by the frame body  23 . Therefore, compared with the prior art, the electronic package  5  of the present invention can have required wirings arranged on the surface of the first side  20   a  of its wiring structure  20  without increasing the size of the first side  20   a  of the wiring structure  20 . Consequently, the electronic package of the present application can not only meet the demand for miniaturization, but also reduce manufacturing costs. 
       FIGS.  6 A to  6 C  are schematic cross-sectional views of a third embodiment of a manufacturing method of an electronic package  6  of the present invention. The difference between this embodiment and the above-mentioned embodiments lies in the addition of a shielding process, so the similarities will not be repeated in the following. 
     As shown in  FIG.  6 A , based on the electronic package  3  of  FIG.  3 C- 1   , after the singulation process, a shielding layer  66  is formed on the side surface  24   c  and the first surface  24   a  of the packaging layer  24 , and the shielding layer  66  contacts the frame body  33  on the side surface  24   c  of the packaging layer  24 . 
     As shown in  FIG.  6 B , based on the aspect of  FIG.  4 A- 2   , the shielding layer  66  can also contact the frame body  43  on the first surface  24   a  of the packaging layer  24 . Alternatively, as shown in  FIG.  6 C , based on the aspect of  FIG.  5 A , the shielding layer  66  may not contact the frame body  23 . 
     It should be understood that the shielding layer  66  can be in contact with or not in contact with the electronic component  21  as required, and there is no particular limitation. 
     Therefore, the manufacturing method of the present invention adopts mainly a design of the shielding layer  66  to prevent the electronic component  21  from electromagnetic interference (EMI). 
       FIG.  7 A  is a schematic cross-sectional view of a fourth embodiment of a manufacturing method of an electronic package  7  of the present invention. The difference between this embodiment and the above-mentioned embodiments lies in the addition of a packaging process, so the similarities will not be repeated in the following. 
     As shown in  FIG.  7 A , based on the electronic package  3  of  FIG.  3 C- 1   , another electronic component  71  is arranged on the second side  20   b  of the wiring structure  20 . The electronic component  71  is a semiconductor chip, which can be arranged on the wiring structure  20  in a flip chip manner by a plurality of conductive bumps  710  such as solder materials, metal pillars or others, and is electrically connected to the wiring layer of the wiring structure  20 . However, there are various ways to electrically connect the electronic component  71  to the wiring structure  20 , and there are no particular limitations. 
     In this embodiment, another packaging layer  74  can be formed on the second side  20   b  of the wiring structure  20  in a way to cover the electronic component  71 , the conductive bumps  710 , the passive component  25  and the conductive components  27 , wherein the conductive components  27  protrude from the packaging layer  74 . For example, the packaging layer  74  is an insulating material, such as polyimide (PI), dry film, encapsulant such as epoxy or a molding compound such as epoxy, and can be formed on the second side  20   b  of the wiring structure  20  by a process selected from liquid compound, injection, lamination, compression molding or the like. It should be understood that the packaging layer  74  on the second side  20   b  and the packaging layer  24  on the first side  20   a  can be made of the same or different materials, and there are no particular limitations. 
     Therefore, the wiring structure  20  can optionally be provided with the packaging layer  24 ,  74  and the frame body  33 ,  73  on at least one side thereof, as shown in an electronic package  7   b  of  FIG.  7 B , and there are no particular limitations. 
       FIG.  8 A- 1    is a schematic cross-sectional view of a fifth embodiment of a manufacturing method of an electronic package  8  of the present invention. The difference between this embodiment and the above-mentioned embodiments lies in the number of electronic components, so the similarities will not be repeated in the following. 
     As shown in  FIGS.  8 A- 1  and  8 A- 2   , based on the electronic package  3  of  FIGS.  3 A and  3 C- 1   , a frame body  83  has a plurality of opening areas  830 , and a plurality of electronic components  21 ,  81  are provided on the first side  20   a  of the wiring structure  20 , so that each of the electronic components  21 ,  81  is exposed from each of the opening areas  830 . 
     In this embodiment, the electronic component  81  is a semiconductor chip, which can be provided on the wiring structure  20  in a flip chip manner by a plurality of conductive bumps  810  such as solder materials, metal pillars or others, and is electrically connected to the wiring layer of the wiring structure  20 . However, there are various ways to electrically connect the electronic component  81  to the wiring structure  20 , such as the wire bonding shown in  FIG.  8 B- 1    and  FIG.  8 B- 2    (that is, an electronic component  82  is electrically connected to the wiring layer of the wiring structure  20  by a bonding wire  820 ), and there are no particular limitations. 
     The present invention also provides an electronic package  2 ,  3 ,  4 ,  4   b,    4   c,    5 ,  5   b,    5   c,    6 ,  7 ,  7   b,    8 , comprising: a wiring structure  20 , at least one electronic component  21 ,  71 ,  81 ,  82 , a packaging layer  24 , 74  and a frame body  23 ,  33 ,  43 ,  73 ,  83 . 
     Said electronic component  21 ,  71 ,  81 ,  82  is arranged on the wiring structure  20  and electrically connected thereto. 
     Said packaging layer  24 ,  74  is formed on the wiring structure  20  to cover the electronic component  21 ,  71 ,  81 ,  82 , wherein the packaging layer  24  has a first surface  24   a  and a second surface  24   a  opposite to each other and side surfaces  24   b  adjacent to the first and second surfaces  24   a,    24   b,  and the packaging layer  24  is bonded to the wiring structure  20  via its second surface  24   b.    
     Said frame body  23 ,  33 ,  43 ,  73 ,  83  is embedded in the packaging layer  24 ,  74 , and the frame body  23 ,  33 ,  43 ,  73 ,  83  neither contacts the wiring structure  20  nor covers the electronic component  21 ,  71 ,  81 ,  82 . 
     In one embodiment, the electronic component  21 ,  81  is exposed from the first surface  24   a  of the packaging layer  24 . 
     In one embodiment, the frame body  23 ,  33 ,  43 ,  83  is exposed from the side surface  24   c  and/or the first surface  24   a  of the packaging layer  24 . 
     In one embodiment, the frame body  23 ,  33 ,  43 ,  83  is flush with the side surface  24   c  and/or the first surface  24   a  of the packaging layer  24 . 
     In one embodiment, the frame body  23 ,  33 ,  43 ,  73 ,  83  is made of a metal or semiconductor material. 
     In one embodiment, the frame body  23 ,  33 ,  43 ,  73 ,  83  takes the shape of a ring to surround the electronic component  21 ,  71 . 
     In one embodiment, the frame body  23 ,  33 ,  43 ,  73 ,  83  is suspended on the wiring structure  20 . 
     In one embodiment, the frame body  23  is erected on the wiring structure  20  by supporting legs  22 . 
     In one embodiment, said electronic package  3 ,  4 ,  4   b,    5 ,  5   b,    5   c,    6 ,  7 ,  8  further comprises another electronic component (such as a passive component  35 ) provided on the wiring structure  20 , and the frame body  23 ,  83  covers the another electronic component. 
     In one embodiment, said electronic package  6  further comprises a shielding layer  66  formed on the packaging layer  24 . 
     In summary, the manufacturing method of the present invention adopts mainly a design of the frame body to disperse thermal stress and avoid warpage, so as to facilitate the arrangement of other electronic components around the electronic component. Therefore, the electronic package of the present invention allows for the arrangement of required wirings on a surface of its wiring structure without increasing the size of the wiring structure. As a result, it not only meets the demand for miniaturization, but also reduces manufacturing costs. 
     The foregoing embodiments are provided for the purpose of illustrating the principles and effects of the present invention, rather than limiting the present disclosure. Anyone skilled in the art can modify and alter the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection claimed by the present disclosure should be as described in the accompanying Claims listed below.