Patent Publication Number: US-11646756-B1

Title: Determining sampling thresholds of SERDES receivers

Description:
BACKGROUND 
     Data signals may be communicated between two devices (e.g., transmitter and receiver) over one or more communications links. Transmission of data signals via the communication links commonly suffer from undesirable signal impairments (e.g., attenuation, noise, etc.) that deteriorate the quality of the data signals. To protect the integrity of a data signal, a receiver (e.g., a serializer/deserializer (SERDES) receiver) recovers the data signal by appropriate sampling and quantization. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various examples will be described below with references to the following figures. 
         FIG.  1    is a block diagram of a SERDES receiver for determining a sampling threshold of the SERDES receiver, in accordance with an example. 
         FIGS.  2 A- 2 H  schematically depict histogram plots at various stages of determination of an updated sampling threshold, in accordance with an example. 
         FIG.  3    is a flowchart of a method for determining a sampling threshold of a SERDES receiver, in accordance with an example. 
         FIG.  4    is a flowchart of a method for determining a sampling threshold of a SERDES receiver, in accordance with another example. 
     
    
    
     It is emphasized that, in the drawings, various features are not drawn to scale. In fact, in the drawings, the dimensions of the various features have been arbitrarily increased or reduced for clarity of discussion. 
     DETAILED DESCRIPTION 
     The following detailed description refers to the accompanying drawings. Wherever possible, the same reference numbers or symbols are used in the drawings and the following description refers to the same or similar parts. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only. While several examples are described in this document, modifications, adaptations, and other implementations are possible. Accordingly, the following detailed description does not limit the disclosed examples. Instead, the proper scope of the disclosed examples may be defined by the appended claims. 
     Data signals received at a receiver often differ from the data signal transmitted from a transmitter due to signal impairments such as attenuation, distortion, and noise. Such signal impairments may cause various changes that degrade the quality of the data signals and the overall performance of a communication system. The performance of the communication system is usually measured in terms of Bit Error Rate (BER) that represents the ability of the communication systems to pass bits without errors. For high-speed data communication systems such as systems that use multi-level pulse-amplitude modulation (PAM) or multi-PAM format (e.g., PAM4), these signal impairments may be more prominent due to high data rates and cause high BER. 
     To capture a data signal correctly, a receiver (e.g., a SERDES receiver) may utilize a sampling circuit to compare the data signal with one or more threshold voltages (hereinafter referred to as “sampling thresholds”) to interpret each symbol (which may represent one or more bits) of the data signal as one or more digital states (e.g., digital states ‘0’ and ‘1’. In communication systems using Non-Return to Zero (NRZ) format, the sampling circuit may use a single sampling threshold to interpret each symbol of the received data signal in a digital state ‘1’ when a voltage signal representing the symbol of the received data signal is greater than the sampling threshold and a digital state ‘0’ when the voltage signal is less than the sampling threshold. In communication systems using PAM4 format, a receiver may interpret a voltage signal representing each symbol of the received data signal into four digital states 00, 01, 10, and 11 defined by three sampling thresholds. 
     The receiver may generally use eye scan information generated by an eye scan circuit or a controller to analyze the quality of the received data signal. For illustration purposes, the eye scan information may be represented with help of an eye diagram which is an imaginary time-folded representation of a data signal that is derived from a waveform by repeating the parts of the waveform corresponding to each symbol into a single graph with a voltage representing the data signal on a vertical axis and time on a horizontal axis. By repeating this construction over many samples of the waveform, the resulting graph represents the average statistics indicative of the quality of the data signal received at a receiver. Similarly, the controller may obtain eye scan information by averaging data derived from the signal. For example, in a system implementing Non-Return to Zero (NRZ) encoding, the eye scan information may be represented as an eye diagram including a single eye corresponding to a single sampling threshold. The single eye represents a range of voltages between two voltage values representing the digital states ‘0’ and ‘1’. In such a case, the single sampling threshold is configured as a decision threshold for decoding a given voltage level as one of the digital states ‘0’ and ‘1’. 
     In communication systems using PAM4 format, eye scan information may include three eyes corresponding to three sampling thresholds. Each of the three eyes represents a range of voltages, between two contiguous voltages, representing two contiguous digital states of the digital states 00, 01, 10, and 11. The contiguous voltages corresponding to the four digital states defining the three eyes may be referred to as levels 0, 1, 2, and 3. In the PAM4 based receivers, the three sampling thresholds are configured for decoding a given voltage level as one of the digital states 00, 01, 10, and 11. 
     Typically, the sampling thresholds are defined during a training phase (which typically occurs during the startup of the system). The receiver may determine the sampling thresholds using eye scan information generated by measuring a data signal of a training sequence. For example, the receiver determines a sampling threshold at a voltage corresponding to a center of an eye in the eye diagram. The term “center of an eye” is a voltage value that is in the middle of a voltage range of the eye. The receiver may locate the center of the eye based on a vertical eye-opening of the eye. However, it may be challenging to accurately locate the center of the eye due to distortions in the received data signal. Inaccuracy in locating the center of the eye may provide an inaccurate sampling threshold. If the sampling threshold is inaccurate, a probability of incorrectly interpreting the digital state for the received data signal may increase, which may result in increased BER. 
     Examples described herein provide techniques for determining a sampling threshold of a receiver (e.g., SERDES receiver). In the described examples, a controller determines a sampling threshold of the receiver that is more accurate and reliable as compared to the one determined using traditional techniques. The controller uses eye scan information corresponding to a data signal of a training sequence to determine the sampling threshold. The controller determines a value of a sampling threshold (referred to herein as a reference sampling threshold) by locating a center of an eye in the eye diagram. The controller then determines a voltage range that contains an updated value of the sampling threshold (referred to herein as an updated sampling threshold) of the receiver. The controller then narrows the voltage range to find the updated sampling threshold. The controller narrows the voltage range based on accumulated hit rates of the data signal corresponding to the respective voltage levels defining the voltage range containing the updated sampling threshold. 
     In some examples, a controller may determine a reference sampling threshold of a receiver based on a training sequence received by the receiver. The controller may then determine an upper voltage level and a lower voltage level of a voltage range based on the reference sampling threshold. The controller may compare an upper voltage accumulated hit rate with a lower voltage accumulated hit rate and update at least one of the upper voltage level or the lower voltage level based on the comparison. Updating the upper voltage level may include decrementing the upper voltage level by a predetermined value and updating the lower voltage level may include incrementing the lower voltage level by the predetermined value. After updating at least one of the upper voltage level or the lower voltage level, the controller may determine whether a voltage difference (e.g., a first voltage difference) between the instantaneous values of the upper voltage level and the lower voltage level is smaller than or equal to the predetermined value. In response to determining that the first voltage difference is smaller than or equal to the predetermined value, the controller may selectively set the updated sampling threshold of the receiver at the instantaneous value of the upper voltage level or the instantaneous value of the lower voltage level based on accumulated hit rates corresponding to the instantaneous values of the upper voltage level and the lower voltage level. In some examples, setting the updated sampling threshold of the receiver may mean that the controller sets the receiver to compare a received data signal with the updated sampling threshold to interpret its digital state. 
     Throughout the disclosure and in the appended claims, the term “voltage level” (e.g., upper voltage level and lower voltage level) may correspond to a voltage within a range of voltages. Further, a voltage difference between an upper voltage level and a lower voltage level may be referred to as a first voltage difference for the first iteration, and a voltage difference between an upper voltage level and a lower voltage level may be referred to as a second voltage difference for the next iteration. 
     In the examples described herein, the disclosed technique provides the updated sampling threshold of the receiver that is different from the reference sampling threshold. When the controller utilizes the described technique for setting the updated sampling threshold of the receiver, it is observed that a value of BER reduces as compared to a value of BER when the controller utilizes the reference sampling threshold. In addition, it is also observed that when the controller utilizes the described technique for setting the updated sampling threshold of the receiver, the values of BER over several training sequences have fewer variations as compared to variations in the values of BER when the controller utilizes the reference sampling threshold. These observations indicate that the determined updated sampling threshold is more accurate and reliable as compared to that of the reference sampling threshold. 
     Examples are further described herein with reference to  FIGS.  1 ,  2 A- 2 H , and  3 - 4 . Any functionality described herein may be performed by an electronic hardware logic including electronic circuitry, logic gates, etc., of a receiver. In some examples, the functionality described herein may be performed by a controller of a SERDES receiver by way of at least one processor executing instructions stored in a memory (e.g., a machine-readable storage medium). 
       FIG.  1    is a block diagram depicting a portion of an example receiver  100  (e.g., SERDES receiver). The term “receiver” as used herein may refer to a stand-alone receiver or a transceiver module operating in a receiving mode. The receiver  100  may be an electrical receiver or an optoelectronic receiver. The receiver  100  includes one or more front-end circuitry  102 , a sampling circuit  104 , and a controller  106 . The front-end circuitry  102  may be configured to receive a data signal from an external source (e.g., a transmitter) and output a voltage signal V corresponding to the received data signal. The front-end circuitry  102  may include one or more electronic circuitry (e.g., gain stages and equalizer circuits) to enhance the quality of the received data signal of a training sequence by adding gain and/or minimizing distortions in the received data signal. 
     The sampling circuit  104  is coupled to the front-end circuitry  102  to receive the voltage signal V from the front-end circuitry  102 . The sampling circuit  104  applies a decision logic to the received voltage signal V to determine a symbol (i.e., a sample) for a time period (i.e., a sampling period). A sample represents the data received by the receiver  100  over a communication link in a sampling period. The sampling circuit  104  may include one or more slicers that are configured to slice the received voltage signal V into two or more digital states (e.g., digital states 00, 01, 10, and 11 for communication systems using PAM4 format) based on one or more sampling thresholds. 
     In some examples, the receiver  100  may include an eye scan circuit (not shown) to generate an eye scan information indicative of the quality of the received data signal as represented by the voltage signal V. The eye scan circuit may be communicatively coupled to the controller  106  to provide the eye scan information to the controller  106 . For example, the eye scan circuit may include a suitably configured Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), another microcontroller having a processor and memory, or other electronic circuitry that analyzes the incoming signal and generate the scan information. As previously noted, the eye scan information may be represented in the form of a graphical representation called an eye diagram for ease of illustration. 
     The controller  106  is coupled to the sampling circuit  104  to receive the samples from the sampling circuit  104 . In some examples, the controller  106  may also receive the eye scan information from the eye scan circuit. The controller  106  may be a microcontroller comprising at least a processor and a memory. In some examples, the controller  106  may be implemented as an ASIC, system-on-chip (SOC), an FPGA, logic gates, comparators, logical adder circuits, or the like. The controller  106  may include logic to perform one or more of the functionalities described herein. The logic may be implemented in hardware or firmware. The controller  106  may perform a number of operations to analyze the received data signal represented by the samples from the sampling circuit  104 . 
     To properly decode information symbols from an incoming signal, the sampling circuit  104  may be configured with sampling thresholds, for example, three sampling thresholds in the case of PAM4 applications. With varying operating conditions, it is useful to update the sampling thresholds for accurate detection of the symbols. To that end, in some examples, during a training phase, the controller  106  is configured to determine an updated sampling threshold of the receiver  100  and tune the sampling circuit  104  based on the updated sampling threshold. In the description hereinafter, operations to determine one of the three sampling thresholds are described. It is to be noted that the remaining of the three sampling thresholds may be updated in the similar manner without limiting the scope of the disclosure. 
     The functionalities performed by the controller  106  for determining an updated sampling threshold of the receiver  100  are described with reference to  FIGS.  2 A- 2 H .  FIGS.  2 A- 2 H  are described in conjunction with  FIG.  1   .  FIGS.  2 A- 2 H  schematically depict example histogram plots  200 A- 200 H at various stages of determination of an updated sampling threshold. For example, in the present context, histogram plots depicted in  FIGS.  2 A- 2 H  may represent a portion of the eye scan information corresponding to the training sequence for a range of voltages at a data sampling phase. The term “data sampling phase” refers to a phase angle or a sampling point within each sample period at which the sampling circuit  104  samples the voltage signal received from the front-end circuitry  102 . In particular, the histogram plot represents the distribution of voltage signals for a given sample (e.g., any of 00, 01, 10, or 11) over multiple samples. 
     The horizontal axis (i.e., X-axis) of each of the histogram plots  200 A- 200 H represents voltages and the vertical axis (i.e., Y-axis) of each of the histogram plots  200 A- 200 H represents a hit rate of the given symbol. In particular, in the examples of  FIGS.  2 A- 2 H , the horizontal axis of the histogram shows a series of voltages (e.g., V 1 , V 2 , . . . V 13 ) with a voltage interval (ΔV) (e.g., 5 mv) between any two adjacent voltages (e.g., between V 1  and V 2 ) in the series of voltages (e.g., V 1 , V 2 , . . . V 13 ). In some examples, the voltage interval (ΔV) represents a voltage resolution of the receiver  100  depending on the implementation of the receiver  100 . Further, as used herein, the term “hit rate” at a given voltage may refer to a probability that a voltage signal representing a data signal is within plus or minus one voltage margin. The voltage margin may be a value that is half of the voltage resolution of the receiver  100 . For example, if the voltage resolution of the receiver  100  is 6 mV, the voltage margin is 3 mV and a hit rate at a voltage of 100 mV is a probability that the voltage signal is between 97 mV and 103 mV. 
     While analyzing the data signal of the training sequence, the controller  106  may determine a reference sampling threshold (V ref ) of the receiver  100  using the eye scan information. In some examples, the controller  106  may locate a center of a given eye (e.g., defined between level 0 and level 1) of an eye diagram and establish V ref  at a voltage level corresponding to the center of the given eye. The controller  106  may determine a voltage level for which a minimum hit rate is observed and establish V ref  at the determined voltage level. In the example histogram plot  200 A of  FIG.  2 A , the controller  106  observes a minimum hit rate at voltage V 7 . The controller  106  then establishes V ref  of the receiver  100  at voltage V 7 . 
     Further, the controller  106  may determine an upper voltage level L U  and a lower voltage level L L  of a voltage range containing an updated sampling threshold of the receiver  100 . The controller  106  may determine L U  and L L  based on V ref . In some examples, the controller  106  may determine L U  and L L  using example relationships represented by equations (1) and (2).
 
 L   L   =V   ref −½ O   (1)
 
 L   U   =V   ref +½ O   (2)
 
where ‘O’ represents a preconfigured value for setting an initial width of the voltage range that contains the updated sampling threshold. In an example, the preconfigured value ‘O’ is equal to the largest expected value of a vertical eye-opening. The controller  106  may receive the preconfigured value of ‘O’ before the training phase. In the example of  FIG.  2 A , the preconfigured value ‘O’ is a value equal to ten times the voltage interval (i.e., 10 ΔV). For example, if the preconfigured value ‘O’ is 50 mV and the voltage interval (ΔV) is 5 mV, the value of ‘O’ is 10 ΔV. According to equations (1) and (2), the controller  106  computes L L  and L U  as represented by equations 3 and 4, respectively.
 
 L   L   =V   7 −5 Δ V   (3)
 
 L   U   =V   7 +5 Δ V   (4)
 
In this example, L L  and L U  respectively correspond to voltages V 2  and V 12 .
 
     Furthermore, the controller  106  may determine accumulated hit rates of the sample corresponding to L U  and L L . As used herein, the term “accumulated hit rate” for a given voltage level is a sum of the hit rates for a range of voltage encompassing the given voltage. The range of voltages for which the hit rates are accumulated may include one or more contiguous voltages. In some examples, the range of voltages includes a single voltage corresponding to the instantaneous value of the given voltage level. In some other examples, the range of voltages includes multiple contiguous voltages corresponding to an instantaneous value of the given voltage level and one or more previous values of the given voltage level. The accumulated hit rate corresponding to the L U  is indicated herein by ‘A U ’ and is also referred to as upper voltage accumulated hit rate. The accumulated hit rate corresponding to L L  is indicated herein by ‘A L ’ and is also referred to as lower voltage accumulated hit rate. 
     At the first occurrence of determining A U , the range of voltages for which the hit rates are accumulated may include the instantaneous value of L U . Similarly, at the first occurrence of determining A L , the range of voltage for which the hit rates are accumulated may include the instantaneous value of L L . Accordingly, the accumulated hit rates A U  and A L  corresponding to the respective L U  and L L  are the hit rates at the respective L U  and L L . 
     Accordingly, in the example of  FIG.  2 A , A U  corresponding to L U  is equal to a hit rate (E U ) at V 12  (see equation 5) and A L  corresponding to L L  is equal to a hit rate (E L ) at V 2  (see equation 6). In  FIG.  2 A ,
 
 A   U ( V   12 )= E   U ( V   12 )=60  (5)
 
 A   L ( V   2 )= E   L ( V   2 )=80  (6)
 
     The controller  106  may then compare A U  with A L . In some examples, the controller  106  may compare A U  with A L  according to a comparison margin (M). In some examples, the controller  106  may determine the comparison margin (M) using an example relationship represented by equation (7).
 
 M= 2 └log     10     (min(x,y))┘+1   *C   (7)
 
where ‘x’ and ‘y’ are the values (e.g., A U  and A L ) being compared, min(x, y) represents a lower of the values x and y, and ‘C’ is a scaling factor. The scaling factor C may be a fixed predetermined value. for illustration purposes, in the description hereinafter value of the scaling factor C is considered to be 4 (four).
 
     To compare A U  with A L , the controller  106  may determine whether an absolute difference between A U  and A L  is smaller than or equal to the comparison margin (M) (i.e., ≤M), or greater than the comparison margin (M) (i.e., &gt;M). In some examples, the controller  106  may use comparison conditions represented in equations (8a)-(8d) to compare A U  and A L .
 
 A   L   −A   U   &gt;M   (8a)
 
 A   U   −A   L   &gt;M   (8b)
 
 A   L   −   A   U   ≤M   (8c)
 
 A   U   −A   L   ≤M   (8d)
 
     In the example of  FIG.  2 A , where for A U =60, A L =80, and C=4, the controller  106  may determine the comparison margin (M) as being 16 according to equation (7). The controller  106  may then determine that an absolute difference between A U  and A L  (i.e., 80−60=20) is greater than the comparison margin (M) (i.e., 20&gt;16) and A U  and A L  satisfy the comparison condition of equation (8a) (i.e., A L −A U &gt;M). In some examples, such comparison operations may be performed by hardware electronic comparators (not shown). 
     In some examples, the controller  106  may be connected to hardware such as a subtractor  107 . The subtractor  107  may be a device implemented using digital logic gates or equivalent circuitry that compare quantities and output a digital signal indicating a difference between the two quantities. For example, the controller  106  may provide values of A L  and A U  to the subtractor  107 . In return, the subtractor  107  may provide an absolute value of the difference between A L  and A U  to the controller  106 . Further, in some examples, the controller  106  may be connected to hardware such as a comparator  109 . The comparator  109  may be a device implemented using digital logic gates or equivalent circuitry that compare quantities and output a comparison result between the two quantities. For example, the controller may provide values of the comparison margin (M) and the difference between A L  and A U  to the comparator  109 . In return, the comparator  109  may provide a comparison result. The comparison result may indicate any of the four conditions represented via the equations (8a)-(8d). In particular, the comparison result may indicate that whether the absolute difference between A L  and A U  is greater than the comparison margin (M) or not. It is to be noted that in some examples, functionalities of the subtractor  107  and the comparator  109  may be combined into a single device or circuit. In some examples, the operations performed by the subtractor  107  and the comparator  109  may be performed by the controller  106  itself. 
     Based on the comparison of A U  and A L , the controller  106  may update at least one of L U  or L L . In some examples, when the absolute difference between A U  and A L  corresponding to the respective L U  and L L  is less than or equal to the comparison margin (M) (i.e., A L  and A U  satisfy the comparison conditions of equations (8c) and (8d)), the controller  106  may update both L U  and L L . In some other examples, when the absolute difference between A U  and A L  corresponding to the respective L U  and L L  is greater than the comparison margin (M) (i.e., A L  and A U  do not satisfy the comparison conditions of equations (8c) and (8d)), the controller  106  may update one of L U  or L L . In some examples, when A L  is greater than A U  (i.e., A L  and A U  satisfy the comparison condition of equation (8a)), the controller  106  may update L L  to an updated value and retain L U  at a previous value. In other examples, when A U  is greater than A L  (i.e., A U  and A L  satisfy the comparison condition of equation (8b)), the controller  106  may update L U  to an updated value and retain L L  at the previous value. 
     Updating L U  may include decrementing L U  by a predetermined value. In some examples, the predetermined value is the voltage interval (ΔV). Updating L L  may include incrementing L L  by the predetermined value. Table 1 shows update conditions for updating one or both of L U  or L L  based on the comparison conditions represented in equations (8a)-(8d). Table 1 also includes update conditions for A U  and A L  corresponding to the instantaneous values of the respective L U  and L L . As shown in Table 1, when the controller  106  updates one of L U  or L L , the controller  106  may determine A U  or A L  corresponding to the updated voltage level (L U  or L L ) by determining E U  or E L  at the updated voltage level (L U  or L L ). Further, when the controller  106  updates both L U  and L L , the controller  106  may compute A U  by summing up E U  at the instantaneous value (i.e., updated value) of L U  and A U  corresponding to the previous value of L U  and similarly, compute the accumulated hit rate A L  by summing up E L  at the instantaneous value (i.e., updated value) of L L  and A L  corresponding to the previous value of L L . In some examples, to perform such sum the controller  106  may send the quantities to be added (e.g., the values of E L  at the instantaneous value of L L  and A L  corresponding to the previous value of L L ), labeled as addends in  FIG.  1   , to hardware such as adder  111 . The adder  111  may be a device implemented using digital logic gates or equivalent circuitry that sum the quantities and output the sum of the quantities to the controller  106 . It is to be noted that in some examples, functionalities of the subtractor  107 , the comparator  109 , and the adder  111  may be combined into a single device or circuit. In some examples, the operations that are performed by the adder  111  may be performed by the controller  106  itself. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Update conditions for upper voltage level  
               
               
                 and lower voltage level based on comparison conditions 
               
            
           
           
               
               
            
               
                 Comparison 
                 Update Conditions for Upper and Lower voltage Levels 
               
            
           
           
               
               
               
               
               
            
               
                 condition 
                 L L   
                 A L   
                 L U   
                 A U   
               
               
                   
               
               
                 A L  − A U  &gt; M 
                 Update to 
                 E L  at the 
                 Retain at 
                 E U  at the 
               
               
                 (Equation (8a)) 
                 an updated 
                 updated value 
                 the previous 
                 previous  
               
               
                   
                 value of L L   
                 of L L   
                 value of L U   
                 value of L U   
               
               
                 A U  − A L  &gt; M 
                 Retain at 
                 E L  at the 
                 Update to 
                 E L  at the 
               
               
                 (Equation (8b)) 
                 the previous 
                 previous value 
                 an updated 
                 updated  
               
               
                   
                 value of L L   
                 of L L   
                 value of L U   
                 value of L U   
               
               
                 A L  − A U  ≤ M 
                 Update to 
                 A L   
                 Update to 
                 A U  corre- 
               
               
                 (Equation (8c)) 
                 an updated 
                 corresponding 
                 an updated 
                 sponding  
               
               
                 and 
                 value of Ll 
                 to the previous 
                 value of L U   
                 to the  
               
               
                 A U  − A L  ≤ M 
                   
                 value of  
                   
                 previous 
               
               
                 (Equation (8d)) 
                   
                 L L  + E L   
                   
                 value of  
               
               
                   
                   
                 at the updated 
                   
                 L U  + E U   
               
               
                   
                   
                 value of L L   
                   
                 at the  
               
               
                   
                   
                   
                   
                 updated  
               
               
                   
                   
                   
                   
                 value of L U   
               
               
                   
               
            
           
         
       
     
     In the example of  FIG.  2 A , the controller  106  determines that A U  and A L  satisfy the comparison condition of equation (8a) (i.e., A L −A U &gt;M) as discussed above. Accordingly, based on the update conditions of Table 1, the controller  106  increments L L  from V 2  to V 3  (shown by a dotted line in  FIG.  2 B ) and retains L U  at V 12  (shown by a solid line in  FIG.  2 B ). 
     After updating at least one of L U  or L L , the controller  106  may determine a first voltage difference (Vd 1 ) between the instantaneous values of L U  (the previous value or the updated value) and L L  (the previous value or the updated value) and then determine whether Vd 1  is smaller than or equal to the predetermined value (e.g., the voltage interval ΔV). In some instances, if Vd 1  is smaller than or equal to the predetermined value, the controller  106  may selectively set the updated sampling threshold of the receiver  100  at one of the instantaneous values of L U  or L L  based on A U  and A L  corresponding to the instantaneous values of the respective L U  and L L . In particular, the controller  106  may selectively set the updated sampling threshold by setting it to the instantaneous value of the voltage level (L U  or L L ). In some examples, if A U  at the instantaneous value of L U  is lower than or equal to A L  corresponding to the instantaneous value of L L  (i.e., A U  A L ), the controller  106  sets the updated sampling threshold of the receiver  100  at the instantaneous value of L U . In some instances, when Vd 1  is zero (i.e., when L U =L L ), the controller  106  may set the updated sampling threshold of the receiver  100  to any of the instantaneous values of L U  or L L . In some examples, setting the updated sampling threshold may include setting the sampling circuit  104  of the receiver  100  to sample a voltage signal (V) based on the updated sampling threshold. 
     In some other instances, if Vd 1  is greater than the predetermined value, the controller  106  may set a new upper voltage level and a new lower voltage level of the voltage range containing the updated sampling threshold. The controller  106  may set the new upper voltage level and the new lower voltage level, respectively, at the instantaneous value of L U  (i.e., at the previous value or the updated value) and the instantaneous value of L L  (i.e., at the previous value or the updated value). 
     The controller  106  may then again determine A U  and A L  corresponding to the set L U  (i.e., new upper voltage level) and the set L L  (i.e., new lower voltage level) and compare them according to conditions as given in Table 1. The controller  106  may then compute the comparison margin (M) based on the A U  and A L  according to the relationship of equation (7). The controller  106  may then compare A U  with A L  with each other using the computed comparison margin (M) and the comparison conditions of equations (8a)-(8d). 
     The controller  106  may again update at least one of the set L U  or the set L L  based on the comparison of the A U  and A L . After updating at least one of the set L U  or the set L L , the controller  106  may again determine whether a voltage difference (i.e., a second voltage difference Vd 2 ) between the instantaneous values of L U  and L L  is smaller than or equal to the predetermined value (e.g., voltage interval ΔV). In some examples, when Vd 2  is smaller than or equal to the predetermined value, the controller  106  may selectively set the updated sampling threshold of the receiver  100  at one of the instantaneous values of L U  or L L . In some examples, when Vd 2  is greater than the predetermined value (e.g., the voltage interval ΔV), the controller  106  may again set a new L U  and a new L L  of the voltage range containing the updated sampling threshold, respectively, at the instantaneous value of L U  and the instantaneous value of L L . The controller  106  may then repeat the process of updating at least one of L U  or L L  until a voltage difference between the instantaneous values of L U  and L L  is smaller than or equal to the predetermined value (e.g., voltage interval ΔV). 
     The example histogram plot  200 B of  FIG.  2 B  shows L U  (i.e., retained L U ) at V 12  and L L  (i.e., updated L L ) at V 3  after the controller  106  updates L L . The controller  106  determines that a voltage difference between the instantaneous values of L L  and L U  (i.e., V 12 −V 3 ) is greater than the predetermined value (i.e., V 12 −V 3 &gt;ΔV). Accordingly, the controller  106  sets a new L L  at V 3  and a new L U  at V 12  of the voltage range containing the updated sampling threshold. The controller  106  again determines A U  and A L  corresponding to the instantaneous values of L U  (i.e., V 12 ) and L L  (i.e., V 3 ) using the conditions for computing A U  and A L  as given in Table. 1. In this example, A U  is equal to E U  at V 12  and A L  is equal to E L  at V 3 . Accordingly, in  FIG.  2 B ,
 
 A   U ( V   12 )= E   U ( V   12 )=60  (9)
 
 A   L ( V   3 )= E   L ( V   3 )=50  (10)
 
The controller  106  then computes the comparison margin M (i.e., 16) for A U =60, A L =50, and C=4 according to equation (7). The controller  106  determines that a difference between A U  and A L  (i.e., A U −A L =60−50=10) is smaller than or equal to the comparison margin M (i.e., 10&lt;16), and A U  and A L  satisfy the comparison conditions of equations (8c) and (8d). The controller  106  then updates both L U  and L L  as per update conditions of Table 1. The controller  106  decrements L U  from V 12  to V 11  and increments L L  from V 3  to V 4 .
 
     The example histogram plot  200 C of  FIG.  2 C  shows L U  at V 11  and L L  at V 4  after the controller  106  updates L U  and L L . As the voltage difference V 11 −V 4  is greater than the predetermined value (i.e., V 11 −V 4 &gt;ΔV), the controller  106  sets a new L L  at V 4  and a new L U  at V 11 . The controller  106  again determines A U  and A L  based on the update conditions for A U  and A L  as given in Table 1. In the example of  FIG.  2 C , A U  and A L  may be determined according to relationships presented in equations 11 and 12, respectively.
 
 A   U ( V   11 )= A   U ( V   12 )+ E   U ( V   11 )=60+50=110  (11)
 
 A   L ( V   4 )= A   L ( V   3 )+ E   L ( V   4 )=50+30=80  (12)
 
     The controller  106  then determines the value of the comparison margin M as 16 for A U =110, A L =80, and C=4 according to equation (7). Accordingly, the controller  106  determines that the difference between A U  and A L  (i.e., 30) is greater than the comparison margin M (i.e., 30&gt;16), and A U  and A L  satisfy the comparison condition of equation (8a), and the controller  106 . Accordingly, the controller  106  decrements L U  from V 11  to V 10  and retains L L  at V 4 . 
     Moving to  FIG.  2 D , in the example histogram plot  200 D, with L U  being at V 10  and L L  being at V 4  and the voltage difference V 10 −V 4  is greater than ΔV, the controller  106  sets a new L L  at V 4  and a new L U  at V 10 . The controller  106  again determines A U  and A L  based on the update conditions shown in Table-1. In the example of  FIG.  2 D , A U  and A L  may be determined according to relationships presented in equations 13 and 14, respectively.
 
 A   U ( V   10 )= E   U ( V   10 )=40  (13)
 
 A   L ( V   4 )= E   L ( V   4 )=30  (14)
 
     The controller  106  then determines the value of the comparison margin M as 16 for A U =40, A L =30, and C=4 according to equation (7). Accordingly, the controller  106  determines that the difference between A U  and A L  (i.e., 10) is smaller than the comparison margin M (i.e., 10&lt;16), and A U  and A L  satisfy the comparison condition of equations (8c) and (8d). Accordingly, the controller  106  decrements L U  from V 10  to V 9  and increments L L  to V 5 . 
     Referring now to  FIG.  2 E , in the example histogram plot  200 E, with L U  being at V 9  and L L  being at V 5  and the voltage difference V 9 −V 5  is greater than ΔV, the controller  106  sets a new L L  at V 5  and a new L U  at V 9 . The controller  106  again determines A U  based on the update conditions shown in Table-1. In the example of  FIG.  2 E , A U  and A L  may be determined according to relationships presented in equations 15 and 16, respectively.
 
 A   U ( V   9 )= A   U ( V   10 )+ E   U ( V   9 )=40+35=75  (15)
 
 A   L ( V   5 )= A   L ( V   4 )+ E   L ( V   5 )=30+8=38  (16)
 
     The controller  106  then determines the value of the comparison margin M as 16 for A U =75, A L =38, and C=4 according to equation (7). Accordingly, the controller  106  determines that the difference between A U  and A L  (i.e.,  37 ) is greater than the comparison margin M (i.e., 37&gt;16), and A U  and A L  satisfy the comparison condition of equation (8a). Accordingly, the controller  106  decrements L U  from V 9  to V 8  and retains L L  to V 5 . 
     In the example histogram plot  200 F of  FIG.  2 F , with L U  being at V 8  and L L  being at V 5  and the voltage difference V 8 −V 5  is greater than ΔV, the controller  106  sets a new L L  at V 5  and a new L U  at V 8 . The controller  106  again determines A U  and A L  based on the update conditions shown in Table-1. In the example of  FIG.  2 F , A U  and A L  may be determined according to relationships presented in equations 17 and 18, respectively.
 
 A   U ( V   8 )= E   U ( V   8 )=20  (17)
 
 A   L ( V   5 )= E   L ( V   5 )=8  (18)
 
     The controller  106  then determines the value of the comparison margin M as 8 for A U =20, A L =8, and C=4 according to equation (7). Accordingly, the controller  106  determines that the difference between A U  and A L  (i.e., 12) is greater than the comparison margin M (i.e., 12&gt;8), and A U  and A L  satisfy the comparison condition of equation (8a). Accordingly, the controller  106  decrements L U  from V 8  to V 7  and retains L L  to V 5 . 
     Moving to the example of  FIG.  2 G , with L U  being at V 7  and L L  being at V 5  and the voltage difference V 8 −V 5  is greater than ΔV, the controller  106  sets a new L L  at V 5  and a new L U  at V 8 . The controller  106  again determines A U  and A L  based on the update conditions shown in Table-1. In the example of  FIG.  2 F , A U  and A L  may be determined according to relationships presented in equations 19 and 20, respectively.
 
 A   U ( V   7 )= E   U ( V   7 )=6  (19)
 
 A   L ( V   5 )= E   L ( V   5 )=8  (20)
 
     The controller  106  then determines the value of the comparison margin M as 8 for A U =6, A L =8, and C=4 according to equation (7). Accordingly, the controller  106  determines that the difference between A U  and A L  (i.e., 2) is less than the comparison margin M (i.e., 2&lt;8), and A U  and A L  satisfy the comparison condition of equations (8c) and 8d. Accordingly, the controller  106  decrements L U  from V 7  to V 6  and increments L L  to V 6 . 
     Accordingly, the example histogram plot  200 H of  FIG.  2 H  shows both L U  and L L  at V 6  after the controller  106  updates L U  and L L . The controller  106  determines that both the instantaneous values of L L  and L U  are the same (i.e., V 6 ). In this instance, the controller  106  determines that a voltage difference between the instantaneous values of L L  and L U  is zero (i.e., voltage difference&lt;ΔV), which is smaller than or equal to the predetermined value. Accordingly, the controller  106  sets the updated sampling threshold of the receiver  100  at V 6 . 
       FIGS.  3  and  4    are flow diagrams respectively depicting example methods  300  and  400  for determining a sampling threshold (i.e., an updated sampling threshold) of a receiver (e.g., the SERDES receiver  100  of  FIG.  1   ). The methods  300  and  400  may, for example, be executed by a controller (e.g., the controller  106  of  FIG.  1   ). For illustration purposes, the execution of example methods  300  and  400  is described in conjunction with the controller  106  of  FIG.  1   . Although the methods  300  and  400  are described with reference to the controller  106  of  FIG.  1   , other applications or devices suitable for the execution of the example methods  300  and  400  may be utilized. 
     In  FIG.  3   , at block  302 , the method  300  may include determining a reference sampling threshold (V ref ) of the receiver  100  by analyzing a data signal of a training sequence received by the receiver  100 . In some examples, the controller  106  may locate a center of an eye (e.g., defined between level 0 and level 1) of the eye diagram and establish V ref  at a voltage level corresponding to the center of the eye as described earlier with reference to  FIGS.  1  and  2 A . 
     As block  304 , the method  300  may include determining an upper voltage level L U  and a lower voltage level L L  of a voltage range containing the updated sampling threshold of the receiver  100  based on V ref . In some examples, the controller  106  may determine L U  and a L L  based on the relationships presented in the equations (1) and (2). Further, at block  306 , the method  300  may include comparing an upper voltage accumulated hit rate A U  with a lower voltage accumulated hit rate A L . In some examples, the controller  106  may determine A U  and A L  as described previously and compare them with each other according to the comparison margin (M) (equation (7)) and the comparison conditions of equations (8a)-(8d). 
     At block  308 , the method  300  may include updating at least one of L U  or L L  based on the comparison of A U  and A L . In some examples, the controller  106  may update at least one of L U  or L L  using the update conditions of Table 1, as described previously. In some instances, when the absolute difference between A U  and A L  is greater than the comparison margin (M) (i.e., A L  and A U  satisfy the comparison condition of equation (8a) or (8b)), the controller  106  may update one of L U  or L L . When the absolute difference between A U  and A L  is smaller than or equal to the comparison margin (M) (i.e., A L  and A U  satisfy the comparison conditions of equations (8c) and (8d)), the controller  106  may update both L U  or L L . 
     At block  310 , the method  300  may include determining whether a voltage difference (i.e., Vd 1 ) between the instantaneous values of L U  (previous or updated value) and L L  (previous or updated value) is smaller than or equal to the predetermined value (i.e., the voltage interval (ΔV)). In some examples, the controller  106  may perform a check, at block  310 , to determine whether Vd 1  is smaller than or equal to the predetermined value. At block  310 , if it is determined that Vd 1  is smaller than or equal to the predetermined value, the controller  106 , at block  312 , may selectively set the updated sampling threshold of the receiver  100  at one of the instantaneous values of L U  or L L  depending on A U  and A L ) corresponding to the instantaneous values of L U  and L L . The controller  106  may set the updated sampling threshold of the receiver  100  at the instantaneous value of L U  or the instantaneous value of L L  for which the accumulated hit rate (e.g., A U  or A L ) is a lower value. 
     Referring to block  310  again, at block  310 , if it is determined that the Vd 1  is greater than the predetermined value, the method  300  may return to block  304 . In some examples, the method  300  may repeat block  304  to determine an upper voltage level (i.e., a new upper voltage level) and a lower voltage level (i.e., a new lower voltage level) of the voltage range containing the updated sampling threshold for the next iteration. In some examples, the controller  106  may set the new upper voltage level at the instantaneous value of L U  and the new lower voltage level at the instantaneous value of L L . The method  300  may then repeat block  306  to compare A U  corresponding to the set L U  (i.e., new upper voltage level) with A L  corresponding to the set L L  (i.e., new lower voltage level) and block  308  to update at least one of the set L U  or the set L L . The method  300  may then repeat block  310  to determine whether a voltage difference (i.e., Vd 2 ) between the instantaneous values of the set L U  and the set L L  is smaller than or equal to the predetermined value (e.g., the voltage interval ΔV). In some examples, when Vd 2  is smaller than or equal to the predetermined value, the method  300  may include selectively setting the updated sampling threshold of the receiver  100  at one of the instantaneous values of the set L U  or the set L L . In some examples, when Vd 2  is greater than the predetermined value, the method  300  may again return to block  304 . In some examples, the method  300  may include iteratively performing the method blocks  304 ,  306 ,  308 , and  310  until the method  300  determines that a voltage difference between the instantaneous values of L U  and L L  is smaller than or equal to the predetermined value. 
       FIG.  4    includes certain method blocks that are similar to one or more method blocks described in  FIG.  3   , details of which are not repeated herein for the sake of brevity. By way of example, blocks  402 ,  404 ,  406 ,  418 , and  420  of  FIG.  4    are respectively similar to blocks  302 ,  304 ,  306 ,  310 , and  312  of  FIG.  3   . 
     At block  402 , the controller  106  may determine a reference sampling threshold (V ref ) of the receiver  100  by analyzing a data signal of a training sequence received by the receiver  100 . At block  404 , the controller  106  may determine an L U  and a L L  of a voltage range containing the updated sampling threshold of the receiver  100  based on V ref . At block  406 , the controller  106  may compare an upper voltage accumulated hit rate A U  with a lower voltage accumulated hit rate A L . In some examples, the controller  106  may compute A U  and A L , as described previously, and compare A U  with A L  according to a comparison margin (M) (equation (7)) and the comparison conditions represented in equations (8a)-(8d). 
     At block  408 , the controller  106  may perform a check to determine whether an absolute difference between A U  and A L  is smaller than or equal to the comparison margin (M). At block  408 , if it is determined that the absolute difference between A U  and A L  is smaller than or equal to the comparison margin (M) (i.e., A U  and A L  satisfy the comparison conditions of equations (8c) and (8d)), the controller  106 , at block  410 , may update both L U  and L L . The method  400  then proceeds to block  418 . 
     At block  408 , if it is determined that the absolute difference between A U  and A L  is greater than the comparison margin (M) (i.e., A U  and A L  satisfy the comparison condition of equation (8a) or (8b)), the method  400  may proceed to block  412 . At block  412 , the controller  106  may again perform a check to determine whether A U  is more than A L . At block  412 , if it is determined that A U  is more than A L  (i.e., A U &gt;A L , and A U  and A L  satisfy the comparison condition of equation (8b)), the controller  106 , at block  414 , may update L U . In such instances, the controller  106  may retain L L  at the previous value. The method  400  then proceeds to block  418 . 
     Referring to block  412  again, if it is determined that A U  is less than A L  (i.e., A U &lt;A L , and A U  and A L  satisfy the comparison conditions of equation (8a)), the controller  106 , at block  416 , may update L L . In such instances, the controller  106  may retain L U  at the previous value. The method  400  then proceeds to block  418 . 
     At block  418 , the controller  106  may again perform a check to determine whether Vd 1  is smaller than or equal to the predetermined value (e.g., voltage interval ΔV). At block  418 , if it is determined that Vd 1  is smaller than or equal to the predetermined value, the controller  106  may selectively set the updated sampling threshold at one of the instantaneous values of L U  or L L  for which an accumulated hit rate (e.g., any of the A U  or A L ) is observed to be lower. For example, when A L  corresponding to the instantaneous value of L L  is lower than A U  corresponding to the instantaneous value of L U , the controller  106  may set the updated sampling threshold at the instantaneous value of L L . 
     Referring to block  418  again, if it is determined that Vd 1  is greater than the predetermined value, the method  400  may return to block  404  and iteratively perform the method blocks  404 ,  406 ,  408 ,  410 ,  412 ,  414 ,  416 , and  418  until the method  400  determines that a voltage difference between the instantaneous values of L U  and L L  is smaller than or equal to the predetermined value (e.g., voltage interval ΔV). 
     In the examples described herein, functionalities described as being performed by “instructions” may be understood as functionalities that may be performed by those instructions when executed by a processing resource. In other examples, functionalities described in relation to instructions may be implemented by one or more modules, which may be any combination of hardware and programming to implement the functionalities of the modules. 
     As used herein, “machine-readable storage medium” may be any electronic, magnetic, optical, or other physical storage apparatus to contain or store information such as executable instructions, data, and the like. For example, the machine-readable storage medium may be a random-access memory (RAM) or another type of dynamic storage device that may store information and machine-readable instructions that may be executed by the processor. In an example, the machine-readable storage medium may be a non-transitory machine-readable medium. 
     The terminology used herein is for the purpose of describing example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. The term “plurality,” as used herein, is defined as two or more than two. The term “coupled,” as used herein, is defined as connected, whether directly without any intervening elements or indirectly with at least one intervening element, unless otherwise indicated. The term “and/or” as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items. The presence of broadening words and phrases such as “one or more,” “at least,” “but not limited to” or other like phrases in some instances shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent. 
     The foregoing description of various examples has been presented for purposes of illustration and description. The foregoing description is not intended to be exhaustive or limited to the examples disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from the practice of various examples. The examples discussed herein were chosen and described in order to explain the principles and the nature of various examples of the present disclosure and its practical application to enable one skilled in the art to utilize the present disclosure in various examples and with various modifications as are suited to the particular use contemplated. The features of the examples described herein may be combined in all possible combinations of methods, apparatus, modules, systems, and computer program products.