Patent Publication Number: US-11032910-B2

Title: System-in-Package device ball map and layout optimization

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Patent Application No. 62/492,795 filed on May 1, 2017, the disclosure of which is incorporated herein in its entirety by reference. 
    
    
     TECHNICAL FIELD 
     Disclosed are embodiments relating generally to a System-in-Package (“SiP”) substrate and connection layout, and optimization of the same. 
     BACKGROUND 
     General purpose integrated circuits (ICs) are often designed without emphasis on optimizing the physical layout of the pins or balls on the package that will ultimately connect to other devices in a system design. There may be exceptions, for instance, when considering such combinations of circuits such as a processor and its memory, the power management for a system design, and in the analog domain of ICs, the relationship between digital, analog, and power pins with respect to potential noise issues. With the advent of System-in-Package (SiP) designs, there may be new complexities to the design for a SiP. In particular, a new complexity may arise in how to optimize a pin arrangement or ball map, for instance, of the SIP itself in order to optimize the layout of the PCB to which it is attached. 
     Accordingly, there is a need for systems and methods that optimize the substrate and connection layout in SiP designs. 
     SUMMARY 
     According to some embodiments, a system is provided. The system comprises, for example, a System-in-Package (SiP), wherein the SiP comprises an array of connectors on a bottom surface of the SiP, and a printed circuit board (PCB). In certain aspects, the PCB comprises a top layer, a ground layer, and a power layer, wherein the top layer comprises a plurality of escape traces on a top surface of the PCB. The PCB may include, for example, only 4 layers in some embodiments. The system may also comprise a plurality of electronic components mounted on the top surface of the PCB, wherein at least one of the plurality of electronic components is electrically connected to at least one of the plurality of escape traces. In certain aspects, the SiP is mounted on the top surface of the PCB and is arranged such that all external signals of the SiP are connected to the plurality of escape traces using the array of connectors. The connectors may be, for instance, one or more of an array of pins, an array of balls, and an array of contact surfaces, adapted for surface mount on the PCB. In some embodiments, the PCB has a bottom surface and no components are mounted on that bottom surface. Additionally, at least one of the connectors in the array of connectors may be a test point of the SiP and contact at least one of the ground layer and the power layer using a via of the PCB. In some embodiments, the electronic component electrically connected to the at least one escape trace is a digital processor, memory, graphics device, analog device, power management circuit, communications device, or sensor. 
     According to some embodiments, a SiP is provided. The SiP may be, for example, the SiP used in the system described above, and comprise: a SiP substrate, with an array of connectors on a bottom surface of the SiP substrate; a processor mounted on and electrically connected to the SiP substrate; a memory mounted on and electrically connected to the SiP substrate; and a plurality of SiP electronic components mounted on the SiP substrate and at least partially interconnected with one or more of the processor and the memory. In certain aspects, a first plurality of the connectors is configured for providing the external signals from at least one of the plurality of SiP electronic components to the plurality of electronic components mounted on the top surface of the PCB, a second plurality of the connectors is configured for providing power and ground connections for the SiP to the power layer and the ground layer of said PCB, respectively, and the first plurality of connectors is arranged along one or more outer edges of the array and the second plurality of connectors is arranged in a center of the array. 
     According to some embodiments, a System-in-Package (SiP) is provided. The SiP comprises, for example, a SiP substrate; a processor mounted on and electrically connected to the SiP substrate; a memory mounted on and electrically connected to the SiP substrate; a plurality of electronic components mounted on the SiP substrate and at least partially interconnected with one or more of the processor and the memory; and an array of connectors arranged on a bottom surface of the SIP package. In certain aspects, a first plurality of the connectors is configured for providing signals from at least one of said plurality of electronic components to an external device, and a second plurality of the connectors is configured for providing power and ground connections for the SiP. In some embodiments, the first plurality of connectors is arranged along one or more outer edges of the array and the second plurality of connectors is arranged in a center of the array. In some embodiments, the outer edge of the array is the outermost three rows and columns of connectors. 
     In some embodiments, the array of connectors is one or more of an array of pins, an array of balls, and an array of contact surfaces, adapted for surface mount on the PCB. Additionally, the electronic components may comprise one or more of a digital processor, memory, graphics device, analog device, power management circuit, communications device, and sensor. 
     According to some embodiments, a method for optimizing a system comprising a printed circuit board (PCB) and a System-in-Package (SiP) mounted on the PCB is provided. The method may include identifying signals generated by or used by components of the SiP, grouping signals of the identified SiP components that are internal signals of the SiP, and grouping signals of the identified SiP components that are external signals for the SiP. The method may also include identifying and grouping power input, power output, and ground lines for the SiP components. In some embodiments, the method also includes arranging the components and their connection to an array of package connectors of the SiP such that all of the external signals are connected to one or more escape traces on a top layer of said PCB and such that at least one of the power input, power output, and ground lines is connected to a via of the PCB through at least one of the package connectors, wherein the via is electrically connected to a power or ground layer of the PCB. The arranging may comprise, for example, determining the number and location of the package connectors, routing the external signals to one or more package connectors along one or more outer edges of the array, and routing one or more of the power input, power output, and ground lines to one or more package connectors in a center of the array. 
     One advantage of a SiP device is the potential opportunity to optimize the pin arrangement (or other connection set, such as a ball grid array) with respect to the system of which it may become a part. According to some embodiments, this is possible in either general purpose SiPs, which may be used in a variety of different system implementations, or in a specific system implementation where the pin arrangement of the SiP may be designed specifically for an optimal layout for a larger system. 
     These and other features of the present disclosure will become apparent to those skilled in the art from the following detailed description of the disclosure, taken together with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various embodiments. 
         FIG. 1  is a diagram of a power management and a processor/memory device. 
         FIG. 2  is a diagram of a System-in-Package (SiP) device according to some embodiments. 
         FIGS. 3A and 3B  depict the traces of a PCB layout for a SiP device. 
         FIGS. 4A-4C  depict the traces of PCB layout with optimized traces according to some embodiments. 
         FIG. 5  is a flow chart of a process for the optimal placement of connectors in a SiP according to some embodiments. 
         FIG. 6  is a flow chart of a process for the optimal placement of connectors in a SiP according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  depicts a simplified block diagram  100  of a power management device  101  and a processor/memory device  102  that may be a portion of system components mounted on a PCB. These two components, or their equivalents, may be used in  FIG. 2  to illustrate the interconnections of these components in a SiP as opposed to a PCB. Continuing to refer to the example of  FIG. 1 , the power management device  101  uses three types of inputs/outputs: power inputs  103 , power outputs  104  and external signals  105  that go to and from the system. In this example, processor/memory device  102  uses two types of inputs/outputs: power inputs  106  and external signals  107 . The physical locations of inputs/outputs of each device  101 ,  102  in its package may be optimized specifically for that device and may be used in a typical PCB for a system. 
       FIG. 2  depicts a block diagram  200  of a System-in-Package (SiP) device  201  according to some embodiments. In certain aspects, the diagram  200  uses the components of  FIG. 1 . For instance, in this example, the SiP device  201  has three components: a power management device  202 , a memory device  203 , and a microprocessor  204 . To connect these components within the SiP, there are a number of internal connections. These may include, for instance, internal power buses  211  and internal signal busses  212 , which may be in the SiP substrate on which the three components are mounted. The SiP  201  also uses a number of inputs and outputs. In this example SiP  210 , five types of inputs/outputs are used. These include power inputs and grounds  205 , as well as power outputs  206 . This SiP  201  also has external signals  208 , which go, for instance, to and from the system to connect internal components/processing with external devices, such as a PCB and/or secondary system. Other inputs/outs may include test pins  209  and  210 , which can be used to observe internal power buses or internal signals and signals that are brought off the SiP and then back on to it  207  so that those signals may be observed and/or used externally to the SiP. These selective internal signals may be connected externally  207  in order to allow individual control and testing of the components within the SiP by external components in a system. 
       FIG. 3A  depicts the external connector or ball locations of a SiP substrate as black dots where the pinout for each of the four SiP components of this example (chips 1-4) are maintained instead of ball locations being optimized for use in a system PCB on which the SiP is to be mounted. The black lines attached to the black dots represent how signal traces on the surface layer of the PCB on which the SiP is to be mounted are connected to the balls of the SiP, and illustrate how those traces are used to get signals from the SiP balls out from under the SiP package to other components on the system&#39;s PCB. These lines or escape traces are only illustrated in a length to get the trace out from under the SiP package, as indicated by the outermost dashed line portions, but would be longer than depicted to connect to other components on the system&#39;s PCB. The larger black circles with a white dot in the center represent vias to other layers in the PCB. 
     Continuing to refer to  FIG. 3A , it may be seen that the SiP  300  has four components  321 ,  322 ,  323 , and  324  in this example. In this example, each component uses the same pinout (or ball map) it has as a standalone device for the SiP substrate, when it is integrated into the SiP. As may be seen in  FIG. 3A , this results in multiple power inputs  325 ,  326 ,  327 , and  328 , and uses many more pins than is necessary to power the components integrated within the SiP. Internal signals that need to be connected externally  331  and  332  can result in traces that reduce the ability to route other signals on the same PCB layer. Unconnected pins  329  and  330  may be placed in areas that are more easily useable for PCB routing purposes. This can lead to numerous signals  333  that must use a via  343  to be routed to a different layer in the PCB. Once routed to this different layer in the PCB, that signal  333  may then be required to use another via to get back to the surface layer where all the components are located and attached both physically and electrically to the PCB to make the proper interconnections. For a component on the surface (or the bottom of the PCB), an interconnection may require the use of a via to get to the same layer in the PCB as signal  333  for proper interconnection. 
     The result of various signal balls of a SiP being connected to other components on the PCB using vias to other PCB layers can be an increase in the number of PCB layers. For example, six PCB layers may be required. Typically a PCB uses two or more layers for signal interconnections, two or three layers for power and ground distribution, and the top and bottom surface must be reserved for component attachment. With shared PCB surfaces, the number of required layers is typically six. However, and according to some embodiments, if all of the signal balls can escape from under the package on the top surface, layers can be removed from the PCB stack up (i.e., the layers that make up the PCB). For instance, in some embodiments, a PCB with no more than 4 layers is possible. 
     According to aspects of embodiments disclosed herein, and because of the often large size of a system PCB, it is more economical to have fewer PCB layers, even at the expense of more layers in the SiP substrate, if needed. The use of more layers on the SIP substrate allows for all of the complex signal connections to be made in the smaller size of the substrate and further allows for the external connections (e.g., a ball map) to be optimized for the external signals to escape from under the SiP package on the surface of a PCB on which the SiP and other components are mounted. 
       FIG. 3B  depicts a cross-sectional view of  FIG. 3A  along B-B, where the packaged SiP device  341  is attached to the printed circuit board (PCB)  350  by soldering it down using all of the balls (pins). Specifically identified are vias  343 ,  344 ,  345 , which are also shown in  FIG. 3A , and which are connected to balls  333 ,  334 ,  335  for use on a signal or other plane in the PCB other than the top, first signal layer. Also illustrated is the electrical trace  346 , which may also be seen in  FIG. 3A . The PCB in this example has six layers  351 - 356 . The external connections in the circle  340 , which are in the middle of the layout cannot escape from under the package on the top surface, and therefore must be connected to a different layer in the PCB in order to be able to interconnect with other components on the PCB. In this illustration, balls  333 ,  334 , and  335  are examples. 
       FIGS. 4A and 4B  represent the same four components as in  FIG. 3 , but optimized for a system&#39;s PCB in accordance with some embodiments. For instance,  FIG. 4  illustrate how the signals from components in a SiP may be connected and deployed on a single signal layer of the system PCB to which the SiP is attached.  FIG. 4A  depicts as black dots the external connector or ball locations of a SiP substrate from a top view looking through the package of the SiP  441 , where the overall pinout for all components in the SiP have been optimized for use in a system on a system PCB using a minimum number of PCB layers. While balls are used in this illustration, according to embodiments, external connectors maybe be one or more of an array of pins, an array of balls, and an array of contact surfaces, adapted for surface mount on a PCB. In this example, the SiP substrate ball locations are the same locations as the balls on the system PCB.  FIG. 4B  depicts a side view of  FIG. 4A  at B-B, with 4 PCB layers depicted. In this embodiment, all of the external signals are contained in the three outer columns and rows. Examples of these three outer columns and rows are signal balls  431 ,  432  and  433 . In certain aspects, the three rows and columns are a result of how many traces on the PCB surface can be routed between the connection balls located in the outermost rows and columns of SiP connection balls. In this example, the ball to ball spacing is 1.27 mm, which allow for two traces to be routed between connection balls. 
     Referring to  FIG. 4A , the black lines attached to the black dots represent how signal traces on the top surface layer of the PCB on which the SiP is mounted are connected to the balls of the SiP, and illustrate how those traces are used to get signals from the SiP balls out from under the SiP package to other components on the system&#39;s PCB. These lines are escape traces and are only illustrated in a length sufficient to get the trace out from under the SiP package, where the package  441  (depicted as a shaded light gray area). These traces would be longer than depicted in order to connect to other components on the system&#39;s PCB. The larger black circles with a dot in the center represent vias to other layers in the PCB. 
     Continuing to refer to  FIG. 4A , according to some embodiments, the outer three rows/columns of the ball grid array (BGA)  401  are routable on a single layer of the PCB  442 . The connections inside dashed line box  402 , however, are not routable on the same layer of the PCB where components are mounted. In this example the top layer of the PCB. To reduce the number of PCB layers, signals from the SiP device are brought out using escape traces on the surface of the PCB for the external signal balls such as  431 ,  432 , and  433  which are placed in the outer three rows/columns of the SiP package. 
     Continuing to refer to the example of  FIG. 4A , PCB traces  422  and  423  can be routed between SiP package pins  431  and  434  and their corresponding traces  421  and  424 , thus bringing all four of the traces out on the top surface of the PCB. In this example, power inputs/outputs  403 ,  404 ,  405  and  406  are placed such that it is easy to group these pins together and connect to the underlying power planes of the PCB using vias, such as for example, but not limited to, via  416  as well as unlabeled vias inside blocks  405  and  406 . Associated internal signals, connected externally  407  may be placed next to each other to allow for easy connection; internal signals that are needed for a common purpose, like for example, but not limited to, a communication port, may be grouped together. For a communication port, these types of signals may be, for example, but not limited to, address lines, control lines, data lines, and clock signals. 
     Continuing to refer to the example of  FIG. 4A , in some embodiments, if an internal signal of one component must be connected to the signal of another component externally, like  407 , it may be placed on connection balls that would not normally be routed on the PCB surface for mounting components, thus saving those connectors for external signals. Although, in some embodiments it is possible for two internal signals  409  and  410  that need to be connected together externally, to be brought out on the PCB surface on which components are mounted. In this case, one pin should be placed on a ball that would not be routable on a single layer and the other ball should be placed on a pad that would be routable on a single layer. Signals such as test points  414  and  415 , may be connected using vias to another PCB layer such that they can easily connect to a test pad, if necessary. In some embodiments, the test points are placed in the balls that are not routable in a single layer unless there are unused signal ball connections available that are routable in the PCB layer for mounting components. Similarly, and according to some embodiments, unconnected pins  408  should be placed on pads that may not be routable in a single layer. This can reduce the overall number of PCB layers required to route the SiP signals. 
     According to some embodiments, and as illustrated in  FIG. 4A , the three outermost rows/columns of pins/pads may be routed out from under the SiP package as the escape traces used to connect to other components on the system PCB. Additionally, dashed lead  435  depicts how an unconnected pin may still be brought out from under the SiP package for use with other components; in this manner, this disclosure illustrates how more escape traces or more leads than depicted for the three rows/columns of  FIG. 4A  may be utilized, if needed. For instance, the layout of  FIG. 3  has only 2 such rows/columns that are usable. Escape trace  435  illustrates how balls or pins inside the outer rows/columns used for external signals may also be used to get other signals to the top layer of the PCB. 
       FIG. 4B  depicts a side view of  FIG. 4A  at B-B, where the packaged SiP device  441  is attached to the printed circuit board (PCB)  442  by soldering it down using all of the balls (pins) such as  443 ,  451  and  454 . PCB  442  is depicted with four layers. Specifically identified are balls  451  and  454  which are also shown in  FIG. 4A  as  431  and  434 , respectively. Also illustrated are the electrical traces  452  and  453  (and also seen in  FIG. 4A  as  422  and  423 , respectively) on the PCB  442 , which are attached to balls  432  and  433 , respectively. In these figures, for ease of depiction purposes, only a portion of the electrical traces or escape traces are shown in order to explain how the signals can be brought out from under the package to form the rest of the system&#39;s circuit on the system&#39;s PCB. 
     Referring now to  FIG. 4C , and according to some embodiments, grouping of the PCB layout traces  450  is used to allow the signals from the SiP to escape from under the SiP package  471  on one layer of the PCB. In this illustration, the connection balls in the middle of the SiP have been blacked out  472  as they are the power and ground external connections for the SiP. In this depiction there are several groups of signals identified which are typical, but not limited to, a microprocessor system. These escape traces allow the signals to escape out from under the SiP package to other components on the PCB board or substrate. In this example, the signal groups shown are the oscillator  452 , USB  453 , MMI  454 , MMC  455 , UART/SPI/I2C  456 , Analog to Digital Converter  457 , LCD Control  458  and LCD Data  459 , JTAG  460 , GPMC address and data  463 ,  461  and  462  respectively. 
       FIG. 5  depicts a process  500  according to some embodiments. This process may be used to determine the optimal placement of connectors in a SiP substrate for minimizing the number of layers in a system PCB using that SiP. According to some embodiments, first, all pins or signals of all the components in the SiP are classified into different categories in step  501 . These may include, for example, power and ground inputs, power outputs, internal power connections (e.g. those used only internally), internal signals used only internally, internal signals connected externally, external signals, and test points (required for monitoring internal signals and/or internal power connections). The data sheets for the components used in the SiP may be consulted to determine what signals are needed for each component in the SiP and their respective classification or category. Additionally, the data sheet for the SiP may be consulted to determine which, if any, components in the SiP are only used for internal interconnections with the other components in the SiP and have no requirement for external connections. 
     In step  502 , power inputs, grounds and power outputs are consolidated in one category by voltage and power domains to determine the number of package pins needed for each power input, ground or power output. In certain aspects, the initial number of external connectors needed for power and ground may be reduced by consolidating some of the same voltages and grounds to a single external connector by voltage value and by ground, depending upon maximum current demands for that external connection and the maximum internal currents for the interconnections between that external connector and the internal or external devices/components being supplied by that external connector. 
     In some embodiments, the category for internal signals that are used only internally and internal power connections that do not require monitoring test points, as well as any other signals that do not need to be connected to external pins (or balls) may be eliminated from consideration, because they have no need for any external connection. 
     According to some embodiments, the process may move to step  503  for consolidating the set of signals that require external connectors, or package pins (or balls) for use in the system and accordingly connections to the system PCB. Next, and according to some embodiments, how many pins are available for use in the SiP package must be determined  504 , and accordingly the corresponding connecting locations on the system PCB. That is, determining the number of package pins that can be routed on a given PCB layer for a given PCB technology node  504  can be based on the package used for the SiP. 
     For example, but not limited to, using 1.27 mm pitch BGA pins and a 6 mil PCB trace with 6 mil tolerance between traces, this results in the outer three rows/columns of the BGA being able to be routed on a single layer of the PCB substrate. According to some embodiments, any pins inside the outer three rows/columns of the BGA cannot be routed on a single PCB layer, if needed externally. In certain aspects, once the numbers, spacing and size of pins for a package have been determined for a given PCB in step  504 , then placement of the minimal set of signals determined through step  503  can begin. 
     According to some embodiments, first, the external signals can be placed on package connection balls such that they can be routed in the fewest number of PCB layers  505 . Second, the power inputs, grounds and power outputs should be centrally placed  506  such that it is easy to connect to power and ground planes. Then, associated internal signals connected externally should be placed next to each other 507. Next, test points should be placed  508  such that it is easy to connect to a test pad. Finally, any remaining pins are left unconnected  509 .  FIG. 4A  depicts one such connector placement that may result from the steps of  FIG. 5 . Using the methods of the present disclosure can allow for a reduced number of layers in a system PCB using a SiP device, thereby reducing the system PCB costs, as well as eliminating the need to place components on the bottom or underside of the system PCB because of these optimum interconnections. 
     Referring now to  FIG. 6 , a process  600  for optimizing a system comprising a printed circuit board (PCB) and a System-in-Package (SiP) mounted on the PCB according to some embodiments is provided. 
     In step  610 , signals generated by or used by components of the SiP are identified. 
     In step  620 , signals of the identified SiP components that are internal signals of the SiP are grouped, and signals of the identified SiP components that are external signals for the SiP are grouped. 
     In step  630 , power input, power output, and ground lines for the SiP components are identified and grouped. 
     In step  640 , the components and their connections to an array of package connectors of the SiP, such as pins or balls, are arranged such that all of the external signals are connected to one or more escape traces on a top layer of a PCB. In some embodiments, one or more escape traces on a top layer of a PCB are arranged to properly interface with an array of package connectors of the SiP, such that all of the escape traces are connected to external signals and such that at least one of the power input, power output, and ground lines is connected to a via of the PCB through at least one of the package connectors. In some embodiments, that via is electrically connected to a power or ground layer of said PCB. 
     While the processes described above and illustrated in the drawings are shown as a sequence of steps, this was done solely for the sake of illustration. Accordingly, it is contemplated that some steps may be added, some steps may be omitted, the order of the steps may be re-arranged, and some steps may be performed in parallel. 
     While various embodiments of the present disclosure are described herein, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the disclosure unless otherwise indicated herein or otherwise clearly contradicted by context.