Patent Publication Number: US-8994351-B2

Title: Smooth mode transition plateau for a power supply controller

Description:
BACKGROUND INFORMATION 
     1. Field of the Disclosure 
     The present invention relates generally to power supplies, and in particular but not exclusively, relates to controllers for switch mode power supplies. 
     2. Background 
     A wide variety of household or industrial appliances require a regulated direct current (dc) source for their operation. Different types of switch mode power supplies are often utilized to convert low frequency (e.g., 50 Hz or 60 Hz) alternating current (ac) or high voltage dc input mains to a regulated dc output voltage at the output of the power supply. Switch mode power supplies are popular because of their small size due to high frequency operation, well regulated outputs, high efficiency, and the safety and protection features that are provided. 
     In general, a switch mode power supply includes a switching element accompanied with an energy transfer element, such as for example a high frequency transformer, which provides safety isolation. In many examples, the energy transfer element transforms the input voltage level to a lower output voltage level. The output of the transformer is then rectified and filtered to provide a regulated dc output to be provided to an electronic device. The controller for the switch mode power supply typically senses the output of the switch mode power supply in a closed loop to regulate the output. 
     Some common control methods used in the controllers for switch mode power supplies to regulate the output versus load and line variations are the pulse width modulation (PWM), pulse frequency modulation (PFM), ON-OFF control or pulse skipping. 
     One popular topology utilized for a switch mode power supply is a flyback converter. When the switch is closed in a flyback converter, energy is stored in the primary inductance of the energy transfer element because of the blocking direction of the secondary diode cannot transfer to the secondary winding and load. However, when switch opens, the stored energy is transferred to the load by the reversed direction of current. The output regulation of the power converter is through processing the feedback from output to generate an internal signal, which may be referred to as a control signal to regulate the output. 
     The feedback signal from the output can come through an opto-coupler from a sense circuit coupled to the dc output. This feedback is referenced to the secondary ground it is referred as the secondary control. In some switch mode power supplies, the output sense that generates the feedback or control signal may be extracted indirectly from a third winding that is magnetically coupled to the secondary winding on the same transformer core. In this example, the feedback signal may be referenced to the primary ground may therefore be referred to as the primary control. The third winding in some cases also provides the operating power for the power supply controller and is sometimes referred to as a bias or feedback winding. The feedback or control signal may then be used by the controller of the switch mode power supply to, for example, modulate the pulse width (i.e., PWM), change switching frequency (i.e., PFM) or disabling some switching cycles (pulse skipping) of a drive signal used to switch the power switch of the switch mode power supply to regulate the output. 
     Voltage mode control with fixed frequency and ON-time control, usually referred as pulse width modulation (PWM), is typically better suited for high load regulation while the pulse skipping control, also referred as burst mode, is typically utilized for regulation at low loads. Control methods such as fixed on-time, variable off-time or fixed off-time, variable on-time even though they result in switching period time change, would still fit in definition of PWM control. 
     Current mode control may utilize a fixed switching frequency. In current mode control schemes, the on-time of each pulse of the drive signal is terminated when the current flowing in the power switch reaches the current limit threshold of the pulse peak value. In this control method, power switch current ramps up linearly when the power switch is on until the power switch current reaches the current limit threshold. The power switch is then turned off and the current limit threshold is varied to regulate the output. The peak current control mode is also considered as PWM control. In some examples of switch mode power supply controller, in order to improve light load efficiency and no-load power consumption, the switching frequency and current limit level may be reduced in response to a load drop. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
         FIG. 1  is an example block diagram illustrating generally one example of a power supply including a power supply controller featuring a smooth transition plateau in accordance with the teachings of the present invention. 
         FIG. 2  is an example illustrating an example relationship of current limit with respect to changing load conditions in a power supply controller in accordance with the teachings of the present invention. 
         FIG. 3  is an example illustrating an example relationship of switching frequency with respect changing load conditions and a duty cycle of a drive signal in a power supply controller in accordance with the teachings of the present invention. 
         FIG. 4  is a schematic illustrating one example of current limit adjustment circuit in accordance with the teachings of the present invention. 
         FIG. 5A  illustrates a simplified circuit block example of an oscillator that generates a variable frequency oscillating signal in accordance with the teachings of the present invention. 
         FIG. 5B  is an example timing diagram that illustrates waveforms according to the circuit block example of  FIG. 5A  in accordance with the teachings of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Methods and apparatuses for controlling a switched mode power converter are disclosed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention. 
     Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale. 
     It is appreciated that in description below and in all examples that a switch mode power supply may include an integrated circuit (IC) holding different circuitry of a controller that may also include some switching and power devices in a monolithic or in a hybrid structure. 
     It is noted that for the power supply control schemes in which the skipped cycles do not result in a considerable change in overall switching frequency, that these power supply control schemes are still considered to be of duty cycle modulation or PWM control since the overall switching frequency is not changed considerably. However, if it is required to skip a large number (e.g., a large percentage) of cycles that result in switching frequency change, then this power supply control scheme is considered to be pulse frequency modulation (PFM) control. These various power supply control schemes regulate the power delivered through varying the power switch on-time as a proportion of the switching cycle time period, which may be referred to as duty cycle control. In some applications, in order to achieve a desired result of regulation at different loads and different input voltage levels, a multi-mode combination of the PWM control methods could be used in accordance with the teachings of the present invention. 
     One key challenge in implementing multiple modes of duty cycle control in a power converter is ensuring a smooth transition between operating modes. The transition between modes normally introduces some change or discontinuity in the control loop gain of the power converter since each mode of duty cycle control has distinct characteristic in term of control loop gain depending on the operating conditions of the power converter. 
     Some known solutions exist such as inserting a hysteresis at the border of transition between operating modes to ensure that any change in the control loop gain during transition from one control mode to another control mode does not result in control loop instability that may potentially cause oscillation between modes and rising the output voltage ripple of the converter, audible noise and even damage to certain components within the power converter. 
     Another key challenge in implementing multiple modes of duty cycle control is to maintain a low cost solution by minimizing number of terminals for implementation of multi-mode control. In some cases, multi-mode control for transitions from one PWM control mode to another requires extra terminals to sense the load condition for transition. Such extra terminals are usually coupled to an additional winding on the energy transfer element of the power supply to detect the period of energy delivery during each switching cycle, which changes with load conditions. It is detected by sensing a voltage on the additional winding on the energy transfer element ringing to low level, which indicates that energy delivery to the output is complete for that switching cycle. 
     In general, a goal of multi-mode control is maintaining a high efficiency across a wide load range while employing the low cost packaging by a minimum addition of terminals and devices. 
     In traditional controllers that implement multi-mode solutions, the peak current control pulse width modulation, the switching frequency, and the peak operating current limit are controlled in multiple regions. The switching frequency and current limit level are reduced with load reductions to reduce switching losses and to improve/increase efficiency at the light loads. At very low load/no load conditions, the operation is at burst mode with skipped switching pulses to fulfill the no-load input power consumption, which are required by the regulatory standards for efficiency and no-load/standby power consumption. 
     When operating in a peak current control pulse width modulation mode, increases in the current limit level result in an increase in power switch on-time, which result in an increase of the transfer of energy to the output. As the output load of the power supply increases, the current limit and switching frequency are increased by the controller up to a maximum switching frequency. A problem with a classic peak current control pulse width modulation mode is the sub-harmonic oscillations that can occur in a fixed frequency or increased frequency by any disturbance in oscillator or in switch timing. As the on-time of the power switch increases to increase power delivery, and as the duty cycle exceeds 50%, the power supply controller is more susceptible to the sub-harmonic oscillations. 
     As will be discussed in greater detail below, in order to address the sub-harmonic oscillations, examples of a power supply controller in accordance with the teachings of the present invention utilize an advanced mode of operation that may be referred to as extended on-time modulated off-time. In one example of peak current control with controlled variable current limit and frequency, the maximum switching frequency of the converter is estimated to happen at around 50% of the rated current limit where duty cycle is less than 50%. An example controller with extended on-time modulated off-time utilizes the frequency and current limit control in response to load variations and could extend the on-time and duty cycle beyond the critical value of 50% at maximum frequency without risk of sub harmonic oscillations in accordance with the teachings of the present invention. 
     In one example, a power supply controller utilizes a classic peak current control pulse width modulation mode and variable switching frequency for lighter loads, which results in peak current limits of, for example 25% to 50% of the maximum current limit. For heavier loads that result in a drive signal duty cycle of greater than 50%, an extended on-time modulated off-time mode is utilized to reduce the risks of sub harmonic oscillations. In addition, an intermediate mode is also introduced in an example for the intermediate loads to provide a smooth transition between the modes, which results in peak current limits of, for example, greater than 50% for drive signal duty cycles of less than 50%. In this intermediate mode, the switching cycle frequency is maintained or fixed at a plateau of the maximum switching frequency of the power supply controller and the peak current is increased from 50% with respect to the load until the duty cycle reaches 50% in accordance with the teachings of the present invention. 
     Thus, a power supply controller with a smooth mode transition plateau is introduced in accordance with the teachings of the present invention. In one example, a power supply controller includes a drive signal generator that is coupled to generate a drive signal, which drives a switching of a power switch to control a transfer of energy from an input of a power supply to an output of the power supply. The controller includes feedback circuit that is coupled to receive a feedback signal representative of the output of the power supply. The feedback circuit is coupled to generate a control signal in response to the feedback signal and an oscillator circuit is coupled to generate a variable frequency oscillating signal in response to the control signal. The drive signal generator is coupled to generate the drive signal in response to the oscillating signal. A frequency of the oscillating signal increases from a first frequency to a second frequency with respect to the control signal for a first range of control signal values. The frequency of the oscillating signal remains substantially equal to the second frequency for a second range of control signal values and the frequency of the oscillating signal decreases from the second frequency to a third frequency with respect to the control signal for a third range of control signal values. The first range of control signal values is less than the second range of control signal values and the second range of control signal values is less than the third range of control signal values. 
     To illustrate,  FIG. 1  shows generally a block diagram illustrating one example of a power supply  100  including an energy transfer element  120  and a controller  160  featuring a smooth transition plateau in accordance with the teachings of the present invention. In the illustrated example, energy transfer element  120  is a transformer including a primary winding  122 , secondary winding  124  and a third winding  126 . In the illustrated example, power supply  100  is a flyback power converter  100  with controller  160  in a primary control configuration in which a feedback signal V FB    156  referenced to the primary ground is generated through the third winding  126 . The input of power supply  100  is coupled to receive V AC    102  from an ac line. V AC    102  is rectified through bridge rectifier  104 , the rectified voltage V RECT    106  is a full-wave  108  that is filtered by the filter capacitance C F    110 . In one example, it is appreciated that value of the filter capacitance C F    110  is not very big and the input dc voltage may moderately drop at higher loads. In one example, the dc voltage applied to the primary winding  122  of the energy transfer element  120  may increase gradually with reductions in the load. As shown in the depicted example, the dc voltage is chopped by the power switch  150  in response to drive signal  155 . 
     In particular, when power switch  150  is switched on in response to drive signal  155 , current  151  flowing in primary winding  122  of the energy transfer element  120  stores energy in the magnetic core and because of blocking direction of diode D 1   130  coupled to secondary winding  124 , energy transfer element  120  cannot transfer energy to the load. However, when power switch  150  is switched off in response to drive signal  155 , the reverse direction of current at secondary winding  124  is conducted through diode D 1   130  to charge bulk capacitor C o    135  and provide a filtered output voltage V o    132  across the load  134 . In this configuration of the primary control, the feedback for output regulation is retrieved from a third winding  126  coupled to the secondary winding  124  on the same core of energy transfer element  120 . 
     In the example configuration of  FIG. 1 , the voltage induced in the third winding  126  is directly sampled through the resistive divider that includes R 1   146  and R 2   148 . The scaled down induced feedback signal V FB    156  is applied to the FB pin of controller  160 . In the example, the feedback signal VFB  156  is representative of the output voltage V O    132  of the power supply  100  during an OFF time of power switch  150  when secondary diode D 1   130  is conducting current. In one example, the third winding  126  may also provide the supply voltage V CC    144  for the controller  160  through rectifier  140  and filter capacitance C 1   145  as shown. In one example, controller  160  receives also a current sense  152 , which is representative of current  151 . In one example, based on the application, there may also be extra control signals  154  received by controller  160  to generate drive signal  155  to control switching of the switch  150  to control the transfer of energy from the input of the power supply  100  to the output of the power supply in accordance with the teachings of the present invention. 
     As shown in the depicted example, controller  160  includes a feedback circuit  162 , which is also labeled “FB” in  FIG. 1 , which is coupled to receive the feedback signal V FB    156  and a feedback reference signal  176 . In one example, feedback circuit  162  includes a comparator that generates control signal V C    170  in response to a comparison of feedback signal V FB    156  and feedback reference signal  176 . In one example, the control signal V C    170  is representative of load  134  coupled to the output of the power supply  100 . Thus, in one example, control signal V C    170  increases in magnitude in response to the load  134  increasing from lighter loads to heavier loads. 
     In one example, controller  160  also includes a current limit adjustment circuit  166 , which is also labeled “I LIMIT ” in  FIG. 1 , which is coupled to receive the control signal V C    170 . In the example, current limit adjustment circuit  166  generates a variable current limit signal  174  in response to control signal V C    170 . In one example, variable current limit signal  174  increases from a minimum current limit to a maximum current limit with respect to the control signal V C    170 . Thus for a no load or light load condition, the variable current limit signal  174  is at a minimum current limit, and at full load conditions, the variable current limit signal  174  is at a maximum current limit, which is referred to as 100% I Limit-Max . 
     To illustrate,  FIG. 2  shows an example relationship of the current limit  274 , which corresponds to variable current limit signal  174  in  FIG. 1 , with respect to control signal  270  or changing load conditions, which corresponds to control signal V C    170  in  FIG. 1 . As shown, when the control signal V C    270  is at a minimum control signal value of V C-min    218 , the current limit  274  is at a minimum of I LIMIT-min    228 . As the control signal V C    270  increases to a full load condition of V C-FL    217 , the current limit  274  increases to a maximum of I Limit-Max    227 . 
     As shown along the x-axis of  FIG. 2 , it is noted that three ranges of control signal values are defined. The first range of control signal values is defined from V C-Min    218  to V C-A    213 . In one example design, V C-A    213  corresponds to a current limit I Limit3    223 , which is substantially equal to 50% of I Limit-max    227 . The second range of control signal values is defined from V C-A    213  to V C-B    214 . In one example, as will be discussed, V C-B    214  corresponds to a current limit I Limit4    224 , which is greater than I Limit3    223 , less than I Limit-Max    227 , and corresponds to the current limit at which the duty cycle of drive signal  155  of  FIG. 1  is substantially equal to 50%. In other words, in one example, when the control signal V C    270  is equal to V C-B    214 , the on-time interval of the drive signal  155  is equal to one-half of the time period of a single pulse of the drive signal  155 . The third range of control signal values is defined from V C-B    214  to V C-FL    217 . As can be observed, the second range of control signal values is greater than the first range of control signal values and the third range of control signal values is greater than the second range of control signal values. It is also noted that in one example, an offset V C-Offset    219  is applied to the control signal V C    270  for a no load condition, as shown. 
     Referring back to  FIG. 1 , in one example, controller  160  also includes a drive signal generator  168  that is labeled “ON-OFF Control” in  FIG. 1 , which is coupled to receive the variable current limit signal  174  from the current limit adjustment circuit, a current sense signal  152 , which is representative of current  151  through power switch  150 , and an oscillating signal  172  from an oscillator  164 . In one example, drive signal generator  168  generates drive signal  155  in response to the oscillating signal  172 . For instance, in one example, each on-time interval of drive signal  155  is initiated with each pulse of the oscillating signal  172 . Thus, as the frequency of oscillating signal  172  generated by oscillator  164  increases or decreases, the frequency of drive signal  155  increases or decreases accordingly to vary the switching frequency of power switch  150 . In one example, the on-time interval of each pulse of drive signal  155  is terminated by drive signal generator  168  in response to the current sense signal  152  and the variable current limit signal  174 . For instance, in one example, when the current  151  through power switch  150  reaches the current limit as indicated by variable current limit signal  174 , the on-time interval of the pulse of drive signal  155  is terminated and power switch  150  is turned off for the remainder of the switching cycle until the next switching cycle begins, as initiated by oscillating signal  172 . 
     As mentioned, oscillating signal  172  is generated by oscillator  164 . In one example, the frequency of oscillating signal  172  varies across different ranges of control signal values. For instance, as will be discussed, the frequency of the oscillating signal  172  increases from a first frequency to a second frequency with respect to the control signal V C    170  for a first range of control signal values. The frequency of the oscillating signal  172  then remains substantially equal to the second frequency for a second range of control signal V C    170  values. The frequency of the oscillating signal  172  then decreases from the second frequency to a third frequency with respect to the control signal V C    170  for a third range of control signal values. The first range of control signal values is less than the second range of control signal values, and the second range of control signal values is less than the third range of control signal values. 
     To illustrate,  FIG. 3  shows an example relationship of the switching frequency  372  of drive signal  155  of  FIG. 1  with respect to control signal  370  or changing load conditions, which corresponds to control signal V C    170  in  FIG. 1  in accordance with the teachings of the present invention. In addition, the duty cycle  311  of drive signal  155  is also illustrated along the x-axis of  FIG. 3  to show the relationship of the switching frequency  372  of drive signal  155  with respect to the duty cycle  311  of drive signal  155  in accordance with the teachings of the present invention. 
     As shown along the x-axis of  FIG. 3 , it is noted that the three example ranges of control signal values defined with respect to  FIG. 2  are also illustrated in  FIG. 3 . In particular, the first range of control signal values is defined from V C-Min    318  to V C-A    313 . In the example, V C-Min    318  corresponds to a minimum switching frequency F Min    348  in this region and V C-A    313  corresponds to a maximum switching frequency of F Max    343 . As shown, when the control voltage  370  is at V C-A    313 , the duty cycle  311  is less than 50%, which is labeled as “D&lt;0.5”  363  along the x-axis of  FIG. 3 . 
     In the illustrated example, the second range of control signal values is defined from V C-A    313  to V C-B    314 . As shown, when the control voltage  370  is at V C-B    314 , the switching frequency  372  is maximum switching frequency of F Max    343  and the duty cycle  311  is substantially equal to 50%, which is labeled as “D=0.5”  364  along the x-axis of  FIG. 3 . Thus, it is appreciated that in the second range of control signal values defined from V C-A    313  to V C-B    314 , the switching frequency substantially remains constant at the maximum switching frequency F MAX    343 . In other words, while the load increases in the second range of control signal values, the switching frequency remains substantially fixed at F MAX    343  until the duty cycle  311  of drive signal  155  rises to approximately 50%. As can be observed from  FIG. 3 , it is noted that a plateau  350  is formed with the switching frequency  372  remaining substantially constant at F MAX    343  for the second range of control signal values from V C-A    313  to V C-B    314 . 
     Continuing with the example depicted in  FIG. 3 , the third range of control signal values is defined from V C-B    314  to V C-FL    317 . Thus, as the control signal V C    370  increases in the third range from V C-B    314  to a full load condition of V C-FL    317 ,  FIG. 3  show that the switching frequency  373  decreases from the maximum switching frequency F MAX    343  to a full load switching frequency F FL    347 . 
     As can be observed, the second range of control signal values is greater than the first range of control signal values and the third range of control signal values is greater than the second range of control signal values. It is also noted that in one example, an offset V C-Offset    319  is applied to the control V C    270  for a no load condition, at which the switching frequency  373  is at a frequency of F noLoad    349 . 
     With reference to  FIGS. 2 and 3 , it is noted that, even though not directly related to the present disclosure, at very low loads, the region below the minimum control voltage V C-Min    318  towards V C-offset    319  at no load, when current limit I Limit    274  has been reduced to a minimum value I Limit-min    228  and remains at this level, the switching frequency  372  at V C-Min    318  has been reduced to F Min    348  drops further at an increased rate by a large number of skipped pulses in the drive  155  due to a light load  134  in order to reduce switching loss and increase efficiency. 
       FIG. 4  is a schematic illustrating one example of current limit adjustment circuit  400  in accordance with the teachings of the present invention. In one example, current limit adjustment circuit  400  corresponds with current limit adjustment circuit I Limit    166  of  FIG. 1 . As shown in the depicted example, current limit adjustment circuit  400  is coupled to receive the control signal  470 , which in the illustrated example is representative of the load, and corresponds to control signals V C    170 ,  270 , and  370  of  FIGS. 1-3 , respectively. In the example, a diode connected FET  412  receives a reference current Iref  410  and mirrors it to FETs  414  and  416 . The FET  414  passes the current from the diode connected FET  418  coupled to VDD  405  supply bus. Current through resistor R Slope    426  is defined by voltage at point A  428  and voltage at point B  424 . The buffer  430  receives the control signal V C    470  at its non-inverting input and is coupled as a voltage follower to adjust V A =V C  as shown. The buffer  420  receives V BG    422  at its non-inverting input and is coupled as a voltage follower to keep V B =V BG  as shown. 
     As a result, the current I slope    425  through resistor R slope    426  can be determined as follows:
 
 I   slope =( V   C   −V   BG )/ R   slope   (Eq. 1)
 
     Thus, the current I slope    425  through diode connected FET  418  is responsive to the control signal V C    470 . In the illustrated example, a coefficient K of the reference current Iref  410  through FET  416  clamps the upper border of I slope    425 . 
     As shown in the depicted example, current through the diode connected FET  418  is mirrored through a programmed plurality of current sources  435 , which includes a plurality of mirrored current sources  438  (M 1 , M 2 , . . . Mn) that are selectively coupled in parallel through plurality of switches  436  (S 1 , S 2 , . . . Sn), and controlled by a signal from a current limit programming circuit  437  as shown. As a result, the total programmed variable current limit I Limit    474  across the resistor R Limit    441  generates voltage  443  to the non-inverting input of comparator  440 . In one example, variable current limit I Limit    474  of  FIG. 4  corresponds to variable current limit  174  of  FIG. 1 . Referring back to  FIG. 4 , a current sense signal  452  is coupled to be received by resistor R sense    444 . In one example, current sense signal  452  of  FIG. 4  corresponds to current sense signal  152  of  FIG. 1 , and is therefore representative of the current  151  through the power switch  150 . Referring back to the example of  FIG. 4 , resistor R sense    644  generates voltage  446 , which is applied to the inverting input of comparator  440 . Thus, as soon as current  151  in the main power switch  150  of the power converter reaches the current limit, as indicated with variable current limit I Limit    474  in response to the control voltage V C    430 , the gate turn-off signal  449  at output of comparator  440  is coupled to terminate the on-time interval of drive signal  155  to turn off power switch  150  for this switching cycle. 
       FIG. 5A  illustrates a simplified circuit block example of an oscillator  500  that generates a variable frequency oscillating signal  572 . In one example, oscillator  500  and oscillating signal  572  correspond to oscillator  164  and oscillating signal  172  of  FIG. 1 , respectively. Accordingly, in one example, drive signal  155  is generated in response to oscillating signal  572 . Referring back to the example of  FIG. 5A , oscillator  500  varies the frequency of oscillating signal  572  according to the example described with respect to  FIG. 3 , by symmetrically charging and discharging the oscillator main capacitance C OSC    540  with charging/discharging slopes in response to the control signal V C    570 , which is representative of the output load change. In the example, control voltage V C    570  corresponds to control signals V C    170 ,  270 ,  370  and  470  of  FIGS. 1-4 , respectively. In addition, oscillator  500  varies the frequency of oscillating signal  572  further in response to the duty cycle of the drive signal  155 , as indicated by an on-time extension signal, which is labeled as OTE signal  510  in  FIG. 5A . In one example, OTE signal  510  is inactive at the beginning of each on-time interval of the drive signal  155 , and becomes active when the on-time interval of drive signal  155  exceeds 50% of period at maximum frequency F Max    343 , as shown in  FIG. 3 , or in other words, when the duty cycle  311  of the drive signal  155  is greater than or equal to 0.5 at the maximum frequency F Max    343 . Thus, in one example, OTE signal  510  becomes active as soon as the duty cycle is greater than or equal to “D=0.5”  364  along the x-axis of  FIG. 3 . 
     For instance, as shown in the example of  FIG. 5A , when the latch  545  is in a reset condition, which is when input R  537  is high, the inverted/complementary output Q′  544  of the latch  545  goes high and closes switch S 1 A  524  and switch S 1 B  534 . By closing switch S 1 A  524 , the main capacitance C osc ,  540  of the oscillator  540  starts to linearly charge from the supply bus V DD    505 , with a constant current  526 , through the variable current source I Charge    527  that is controlled by the control voltage V C    570  in response to the load change at the output of the power supply. The voltage V Ramp    520  across the capacitance C osc    540  rises linearly and switch S 1 B  534  applies the higher threshold V H    511  to the inverting input  533  of the comparator  535 . 
     When V Ramp    520  at the non-inverting input  531  of comparator  535  has ramped up to the threshold V H    511 , the output of comparator  535  goes high at terminal S  538 . In addition, the inverter  536  lowers the signal  537  at input R of the latch  545 . As a result, output Q  542  goes high and output Q′  544  is pulled low, which results in switches S 1 A  524  and S 1 B  534  to open and switches S 2 A  522  and S 2 B  532  to close, thus ending the charging period and starting the discharging period of capacitance C OSC    540 . When switch S 2 B  532  is closed, the lower threshold V L    530  is applied to the inverting input  533  of the comparator  535 . As a result, the voltage V Ramp    520  across the capacitance C osc    540  discharges down to V L    530 , with a constant current  728  through the variable current source I Disch    529 , which is controlled by the control signal V c    570  in response to the load coupled to the power supply output. The total charging and discharging periods of the capacitance C osc    540  defines one cycle of the oscillator and the switching frequency of oscillating signal  572  in response to the control signal Vc  570  and the load change. 
     In one example, it is appreciated that the current sources I Charge    527  and I Disch    529  vary in response to changes in the control signal V C    570  from lower control signal values up to a control signal value corresponding to V C-A    213  of  FIG. 2  or V C-A    313  of  FIG. 3 . As shown in  FIGS. 2 and 3 , a control signal V C    270  value of V C-A    213  corresponds to a current limit of 50% of the maximum current limit I Limit-Max    227 . Furthermore, when the control signal V C    370  has reached V C-A    313 , the switching frequency  372  has increased to a maximum switching frequency of F MAX    343 , while the duty cycle of the drive signal  155  is still less than 50%. For control signal V C    570  values that are greater than V C-A    313 , the currents through variable current sources I Charge    527  and I Disch    529  remain the same in order to maintain the maximum switching frequency F MAX    343 , as illustrated at the plateau  350  in  FIG. 3 . 
     As mentioned previously, when the control signal V C    570  rises to a value greater than V C-B    314 , as shown in  FIG. 3  and which corresponds to a duty cycle of greater than 50%, the OTE signal  510  becomes active, which is coupled to be received by one input of AND gate  514 . The other input of AND gate  514  is coupled to receive the drive signal  555 , which corresponds to drive signal  155  of  FIG. 1 . Thus, when the drive signal  555  is active and when OTE signal  510  is active, which indicates that the on-time interval of the drive signal  555  has exceeded a 50% duty cycle, the output of AND gate  513  turns on switch S 3   518 , which activates current source I OTE    517  to draw a current  516  from capacitance C OSC    540  to ground  501  through switch S 3   518 . In one example, current  516  is a constant current that is a fraction of charging current  526  and therefore reduces the charging current rate of the capacitance C osc    540  in a portion of the charging interval when drive signal  555  and OTE signal  510  are both active. As a result, when current source I OTE    517  is activated in response to OTE signal  510  and duty cycles of greater than 50%, the charging slope of V RAMP    520  is reduced for the portion of on-time interval that both the drive signal  555  that OTE signal  510  are active. As a result, on-time and duty cycle can be extended beyond the 50% and the switching frequency  373  is reduced, as illustrated in  FIG. 3 . It is appreciated that as the load increases, the control signal V C    370  increases and the duty cycle increases, which increases the amount of time that the OTE signal  510  is active, which further decreases the switching frequency  373 , as shown in  FIG. 3  for the third range of control signal values from V C-B    314  to V C-FL    317 . 
       FIG. 5B  is an example timing diagram that illustrates waveforms according to the circuit block example of  FIG. 5A  in accordance with the teachings of the present invention. In particular,  FIG. 5B  presents some example waveforms according the circuit block of  FIG. 5A  versus time  590  when operation is in the third region of control signal V C &gt;V C-B , which is when drive signal  555  and OTE signal  510  are both active, the on-time and duty cycle has been extended beyond 50%, the switching period increases and the switching frequency decreases in response to a gradual increase in load. In the example, signal Q′  544  controls switches S 1 A and S 1 B. When signal Q′  544  is high  548 , both switches S 1 A and S 1 B are closed, charging the oscillator capacitance C osc    540 , which corresponds to V Ramp    560  ramping up to V H    567  as shown. When signal Q′  544  is low  549 , both switches S 1 A and S 1 B are open. The signal Q  542  is complementary of signal Q′  544 , and controls S 2 A and S 2 B for discharging the oscillator capacitance C osc    540 . When signal Q′  544  is low  549 , signal Q  542  goes high  547  and discharges oscillator capacitance C osc    540 , which corresponds to V Ramp    560  ramping down  568  to V L    561 . For the example of  FIG. 5B , in an extended on-time modulated off-time mode of operation, the charging slope  562  is defined by current source I Charge    527  but when the drive signal  555  on-time has exceeded 0.5(1/F Max ) and OTE signal  510  is activated  502  to close switch S 3 ,  518  the current source I OTE    517  reduces the charging rate  564  for the duration of OTE signal  510  activation t OTE    594 . The OTE signal  510  remains active until the drain current  151  reaches current limit I Limit    166 , as illustrated for example in  FIG. 1 , and the on-time interval t ON    592  is terminated, which begins the off-time t OFF    596  with the drive signal  555  in an inactive state  554 . Then, the charging slope  566  continues with the original slope  562  up to the higher charging threshold V H    567 , after which S 1 A and S 1 B are opened, S 2 A and S 2 B are closed and the voltage V Ramp    560  across the oscillator capacitance C osc    540  decreases with slope  568  defined by the current source I Disch    529 . As shown, V Ramp    560  ramps down to V L    561 , at which point the switching period T sw    598  is complete and a new switching cycle begins. 
     As mentioned, it is appreciated that the timing diagram of  FIG. 5B  illustrates operation in the third region of control signal V C &gt;V C-B  when duty cycle has been extended beyond 0.5 (50%) and the OTE signal is active. However, in the first and second regions of operation (lower loads, V C &lt;V C-B ), when OTE signal  510  is not activated and the duty cycle is still below 0.5 (50%), the charging (rising) portion of voltage V Ramp    560  across the oscillator capacitance C osc    540  monotonically increases from lower threshold V L    561  to the higher threshold V H    567 . 
     The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention. 
     These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.