Patent Publication Number: US-10325651-B2

Title: 3D semiconductor device with stacked memory

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part of U.S. patent application Ser. No. 15/351,389, filed on Nov. 14, 2016, now U.S. Pat. No. 9,799,761; which is a continuation of U.S. patent application Ser. No. 14/506,160, filed on Oct. 3, 2014, now U.S. Pat. No. 9,496,271, issued on Nov. 15, 2016; which is a continuation of U.S. patent application Ser. No. 13/792,202, which was filed on Mar. 11, 2013, now U.S. Pat. No. 8,902,663, issued on Dec. 2, 2014; the entire contents of all of the foregoing are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the field of monolithic 3D integration to semiconductor chips performing logic and/or memory functions. 
     2. Discussion of Background Art 
     Over the past 40 years, the microelectronic industry has seen a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling” i.e. component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate performance, functionality and power consumption of ICs. 
     3D stacking of semiconductor chips is one avenue to tackle issues with wires. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), one can place transistors in ICs closer to each other. This reduces wire lengths and keeps wiring delay low. However, there are many barriers to practical implementation of 3D stacked chips. These include:
         Constructing transistors in ICs typically require high temperatures (higher than ˜700° C.) while wiring levels are constructed at low temperatures (lower than ˜400° C.). Copper or Aluminum wiring levels, in fact, can get damaged when exposed to temperatures higher than ˜400° C. If one would like to arrange transistors in 3 dimensions along with wires, it has the challenge described below. For example, let us consider a 2 layer stack of transistors and wires i.e. Bottom Transistor Layer, above it Bottom Wiring Layer, above it Top Transistor Layer and above it Top Wiring Layer. When the Top Transistor Layer is constructed using Temperatures higher than 700° C., it can damage the Bottom Wiring Layer.   Due to the above mentioned problem with forming transistor layers above wiring layers at temperatures lower than 400° C., the semiconductor industry has largely explored alternative architectures for 3D stacking. In these alternative architectures, Bottom Transistor Layers, Bottom Wiring Layers and Contacts to the Top Layer are constructed on one silicon wafer. Top Transistor Layers, Top Wiring Layers and Contacts to the Bottom Layer are constructed on another silicon wafer. These two wafers are bonded to each other and contacts are aligned, bonded and connected to each other as well. Unfortunately, the size of Contacts to the other Layer is large and the number of these Contacts is small. In fact, prototypes of 3D stacked chips today utilize as few as 10,000 connections between two layers, compared to billions of connections within a layer. This low connectivity between layers is because of two reasons: (i) Landing pad size needs to be relatively large due to alignment issues during wafer bonding. These could be due to many reasons, including bowing of wafers to be bonded to each other, thermal expansion differences between the two wafers, and lithographic or placement misalignment. This misalignment between two wafers limits the minimum contact landing pad area for electrical connection between two layers; (ii) The contact size needs to be relatively large. Forming contacts to another stacked wafer typically involves having a Through-Silicon Via (TSV) on a chip. Etching deep holes in silicon with small lateral dimensions and filling them with metal to form TSVs is not easy. This places a restriction on lateral dimensions of TSVs, which in turn impacts TSV density and contact density to another stacked layer. Therefore, connectivity between two wafers is limited.       

     It is highly desirable to circumvent these issues and build 3D stacked semiconductor chips with a high-density of connections between layers. To achieve this goal, it is sufficient that one of three requirements must be met: (1) A technology to construct high-performance transistors with processing temperatures below ˜400° C.; (2) A technology where standard transistors are fabricated in a pattern, which allows for high density connectivity despite the misalignment between the two bonded wafers; and (3) A chip architecture where process temperature increase beyond 400° C. for the transistors in the top layer does not degrade the characteristics or reliability of the bottom transistors and wiring appreciably. This patent application describes approaches to address options (1), (2) and (3) in the detailed description section. In the rest of this section, some background art that has previously tried to address options (1), (2) and (3) will be described. 
     U.S. Pat. No. 7,052,941 from Sang-Yun Lee (“S-Y Lee”) describes methods to construct vertical transistors above wiring layers at less than 400° C. In these single crystal Si transistors, current flow in the transistor&#39;s channel region is in the vertical direction. Unfortunately, however, almost all semiconductor devices in the market today (logic, DRAM, flash memory) utilize horizontal (or planar) transistors due to their many advantages, and it is difficult to convince the industry to move to vertical transistor technology. 
     A paper from IBM at the Intl. Electron Devices Meeting in 2005 describes a method to construct transistors for the top stacked layer of a 2 chip 3D stack on a separate wafer. This paper is “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),”  IEDM Tech. Digest , p. 363 (2005) by A. W. Topol, D. C. La Tulipe, L. Shi, et al. (“Topol”). A process flow is utilized to transfer this top transistor layer atop the bottom wiring and transistor layers at temperatures less than 400° C. Unfortunately, since transistors are fully formed prior to bonding, this scheme suffers from misalignment issues. While Topol describes techniques to reduce misalignment errors in the above paper, the techniques of Topol still suffer from misalignment errors that limit vertical contact dimensions between two chips in the stack to &gt;130 nm, and; hence, limits device density. 
     The textbook “Integrated Interconnect Technologies for 3D Nanoelectronic Systems” by Bakir and Meindl (“Bakir”) describes a 3D stacked DRAM concept with horizontal (i.e. planar) transistors. Silicon for stacked transistors is produced using selective epitaxy technology or laser recrystallization. Unfortunately, however, these technologies have higher defect density compared to standard single crystal silicon and do not provide a mono-crystalline stacked layer or layers. This higher defect density degrades transistor performance and device yield. 
     In the NAND flash memory industry, several organizations have attempted to construct 3D stacked memory. These attempts predominantly use transistors constructed with poly-Si or selective epi technology as well as charge-trap concepts. References that describe these attempts to 3D stacked memory include “Integrated Interconnect Technologies for 3D Nanoelectronic Systems”, Artech House, 2009 by Bakir and Meindl (“Bakir”), “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, Symp. VLSI Technology Tech. Dig. pp. 14-15, 2007 by H. Tanaka, M. Kido, K. Yahashi, et al. (“Tanaka”), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by W. Kim, S. Choi, et al. (“W. Kim”), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. (“Lue”) and “Sub-50 nm Dual-Gate Thin-Film Transistors for Monolithic 3-D Flash”, IEEE Trans. Elect. Dev., vol. 56, pp. 2703-2710, November 2009 by A. J. Walker (“Walker”). An architecture and technology that utilizes single crystal Silicon using epi growth is described in “A Stacked SONOS Technology, Up to 4 Levels and 6 nm Crystalline Nanowires, with Gate-All-Around or Independent Gates (ΦFlash), Suitable for Full 3D Integration”, International Electron Devices Meeting, 2009 by A. Hubert, et al (“Hubert”). However, the approach described by Hubert has some challenges including the use of difficult-to-manufacture nanowire transistors, higher defect densities due to formation of Si and SiGe layers atop each other, high temperature processing for long times, difficult manufacturing, etc. 
     There are many techniques to construct 3D stacked integrated circuits or chips including: 
     Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs). 
     Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs). 
     Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,557,632, 8,298,875, 8,642,416, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,476,145, 8,536,023, 8,574,929, 8,581,349, 8,642,416, 8,687,399, 8,742,476, 8,674,470, 8,803,206, 8,836,073, 8,836,080, 8,902,663, 8,994,404, 9,021,414, 9,023,688, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,088, 9,406,670, 9,460,978, 9,509,313; U.S. patent application publications 2011/0092030, 2016/0218046; and pending U.S. patent application Ser. Nos. 14/607,077, 14/642,724, 14/814,865, 62/307,568, 62/297,857, 15/095,187, 15/150,395, 15/173,686, 62/383,463, 62/440,720, 62/443,751, 15/243,941, PCT/US16/52726, 62/406,376, 62/432,575, 62/440,720, 62/297,857, 15/333,138, 15/344,562, and 15/351,389. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference. 
     Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. Nos. 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031; and U.S. patent application publication 2016/0064439. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference. 
     It is clear based on the background art mentioned above that invention of novel technologies for 3D stacked chips will be useful. 
     SUMMARY 
     In one aspect, a semiconductor device comprising: a first memory cell comprising a first transistor; and a second memory cell comprising a second transistor, wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor, wherein access to said first memory cell is controlled by at least one junction-less transistor, and wherein said junction-less transistor is not part of said first memory cell and said second memory cell. 
     In another aspect, a semiconductor device comprising: a first memory cell comprising a first transistor; and a second memory cell comprising a second transistor, wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor; a first gate and a second gate, wherein both said first gate and said second gate each control said first transistor&#39;s channel. 
     In another aspect, a semiconductor device comprising: a first memory cell comprising a first transistor; a second memory cell comprising a second transistor, wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor; a horizontally oriented Resistive RAM (R-RAM) cell connected to a source or a drain of said first transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various embodiments of the invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which: 
         FIGS. 1A-1J  are drawing illustrations of a zero-mask per layer 3D resistive memory with a junction-less transistor; 
         FIGS. 2A-2K  are drawing illustrations of an alternative zero-mask per layer 3D resistive memory; 
         FIGS. 3A-3L  are drawing illustrations of a one-mask per layer 3D resistive memory; 
         FIGS. 4A-4B  are drawing illustrations of periphery on top of memory layers; 
         FIGS. 5A-5B  are exemplary drawing illustrations of potential challenges associated with high field effects in floating-body RAM; 
         FIG. 6  is an exemplary drawing illustration of how a floating-body RAM chip may be managed when some memory cells may have been damaged; 
         FIG. 7  is an exemplary drawing illustration of a methodology for implementing the bad block management scheme described with respect to  FIG. 6 ; and 
         FIGS. 8A-8E  are exemplary drawing illustrations of a process flow which may be utilized to form a 3D NAND R-RAM architecture utilizing junction-less transistors. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the invention are now described with reference to the indicated figures, it being appreciated that the figures illustrate the subject matter not to scale or to measure. Many figures describe process flows for building devices. These process flows, which may be a sequence of steps for building a device, may have many structures, numerals and labels that may be common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step&#39;s figure may have been described in previous steps&#39; figures. 
     The entirety of U.S. Pat. Nos. 8,379,458 and 8,273,610 are incorporated herein by reference. 
     While many of today&#39;s memory technologies rely on charge storage, several companies are developing non-volatile memory technologies based on resistance of a material changing. Examples of these resistance-based memories include phase change memory, Metal Oxide memory, resistive RAM (RRAM), memristors, solid-electrolyte memory, ferroelectric RAM, MRAM, etc. Background information on these resistive-memory types is given in “Overview of candidate device technologies for storage-class memory,”  IBM Journal of Research and Development , vol. 52, no. 4.5, pp. 449-464, July 2008 by Burr, G. W.; Kurdi, B. N.; Scott, J. C.; Lam, C. H.; Gopalakrishnan, K.; Shenoy, R. S. Typical RRAM materials may include transition metal oxides such as TiOx, NiOx, HFOx, WoX, TaOx, VoX, CuOx, SrToOx, CuSiOx, SiOx, TiON, and electrodes may include Pt, TiN/Ti, TiN, Ru, Ni, W, TaN, Ir, Au. STT-MRAM materials may include Ir, PtMn, CoFe, Ru, CoFeB, MgO, CoFeB, Ta. 
       FIGS. 1A-J  describe a novel memory architecture for resistance-based memories, and a procedure for its construction. The memory architecture utilizes junction-less transistors and has a resistance-based memory element in series with a transistor selector. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in  FIG. 1A-J , and all other masks may be shared between different layers. The process flow may include several steps that occur in the following sequence. 
     Step (A): Peripheral circuits  102  may be first constructed and above this an insulator layer, such as a layer of silicon dioxide, oxide layer  104  may be deposited.  FIG. 1A  shows a drawing illustration after Step (A). 
     Step (B):  FIG. 1B  illustrates the structure after Step (B). A wafer of n+ Silicon  108  may have an oxide layer  106  grown or deposited above it. Following this, hydrogen may be implanted into the n+ Silicon wafer at a certain depth indicated by  114 . Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted n+ Silicon wafer  108  may form the top layer  110 . The bottom layer  112  may include the peripheral circuits  102  with oxide layer  104 . The top layer  110  may be flipped and bonded to the bottom layer  112  using oxide-to-oxide bonding.
 
Step (C):  FIG. 1C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) may be cleaved at the hydrogen plane  114  using either a anneal or a sideways mechanical force or other means. A CMP process may then conducted. A layer of silicon oxide  118  may then be deposited atop the n+ Silicon layer  116 . At the end of this step, a single-crystal n+Si layer  116  exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 1D  illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple n+ silicon layers  120  may be formed with silicon oxide layers in between. The composition of the silicon oxide regions within the stacked Si/SiO 2  layers may be insulators or dielectrics other than silicon dioxide such as, for example, a low-k dielectric, carbon containing silicon oxides, amorphous carbon. The thickness of the silicon oxide regions within the stacked Si/SiO 2  layers may be adjusted to minimize layer to layer, strata to strata disturb mechanisms, and may include thicknesses of 50 nm, 75 nm, 10 nm, 150 nm, 200 nm, 500 nm, and less than 1000 nm. A thin conductive layer, such as a metal, may also be formed between the two bonding oxides to form a field shield to mitigate layer to layer, strata to strata disturb mechanisms, and may be electrically floating or tied to a bias, such as ground or Vdd. The stacked Si/SiO 2  layers may alternatively be formed by successive ion implants of oxygen atoms/ions to various depths from the top surface of a mono-crystalline silicon wafer/substrate and then heat treated to form oxide layers thus forming silicon layers in-between the oxide layers, a layered ‘SIMOX’ process approach.
 
Step (E):  FIG. 1E  illustrates the structure after Step (E). Lithography and etch processes may then be utilized to make a structure as shown in the figure.
 
Step (F):  FIG. 1F  illustrates the structure after Step (F). Gate dielectric  126  and gate electrode  124  may then be deposited following which a CMP may be performed to planarize the gate electrode  124  regions. Lithography and etch may be utilized to define gate regions. Gate dielectric  126  and gate electrode  124  may be, for example, a HKMG structure or a TEL SPA radical oxidation oxide and an appropriate work function electrode, for example, tungsten, degenerately doped polysilicon or amorphous silicon. Although the width of the n+ regions  121  near and under the gates are illustrated as being larger than the thickness, one skilled in the art would recognize that the reverse (i.e., thickness larger than width) could be formed to provide increased gate control of the transistor channel.
 
Step (G):  FIG. 1G  illustrates the structure after Step (G). A silicon oxide layer  130  may then be deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity, along with word-line (WL)  132  and source-line (SL)  134  regions.
 
Step (H):  FIG. 1H  illustrates the structure after Step (H). Vias may be etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material  136  may then be deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, well known to change resistance by applying voltage. An electrode for the resistance change memory element may then be deposited (preferably using ALD) and is shown as electrode/BL contact  140 . A CMP process may then be conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with junctionless transistors are created after this step.
 
Step (I):  FIG. 1I  illustrates the structure after Step (I). BLs  138  may then be constructed. Contacts may be made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be achieved in steps prior to Step (I) as well.
 
 FIG. 1J  shows cross-sectional views of the array for clarity.
 
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates that are simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
       FIG. 2A-K  describe an alternative process flow to construct a horizontally-oriented monolithic 3D resistive memory array. This embodiment has a resistance-based memory element in series with a transistor selector. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in  FIG. 2A-K , and all other masks may be shared between different layers. The process flow may include several steps as described in the following sequence. 
     Step (A): Peripheral circuits with tungsten wiring  202  may be first constructed and above this a layer of silicon dioxide  204  is deposited.  FIG. 2A  shows a drawing illustration after Step (A). 
     Step (B):  FIG. 2B  illustrates the structure after Step (B). A wafer of p− Silicon  208  may have an oxide layer  206  grown or deposited above it. Following this, hydrogen may be implanted into the p− Silicon wafer at a certain depth indicated by  214 . Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer  208  may form the top layer  210 . The bottom layer  212  may include the peripheral circuits  202  with oxide layer  204 . The top layer  210  may be flipped and bonded to the bottom layer  212  using oxide-to-oxide bonding.
 
Step (C):  FIG. 2C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) may be cleaved at the hydrogen plane  214  using either a anneal or a sideways mechanical force or other means. A CMP process may then be conducted. A layer of silicon oxide  218  may then be deposited atop the p− Silicon layer  216 . At the end of this step, a single-crystal p− Silicon layer  216  exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 2D  illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple p− silicon layers  220  may be formed with silicon oxide layers in between. The composition of the silicon oxide regions within the stacked Si/SiO 2  layers may be insulators or dielectrics other than silicon dioxide such as, for example, a low-k dielectric, carbon containing silicon oxides, amorphous carbon. The thickness of silicon oxide regions within the stacked Si/SiO 2  layers may be adjusted to minimize layer to layer, strata to strata disturb mechanisms, and may include thicknesses of 50 nm, 75 nm, 100 nm, 150 nm, 200 nm, 500 nm, and less than 1000 nm. A thin conductive layer, such as a metal, may also be formed between the two bonding oxides to form a field shield to mitigate layer to layer, strata to strata disturb mechanisms, and may be electrically floating or tied to a bias, such as ground or Vdd. The stacked Si/SiO 2  layers may alternatively be formed by successive ion implants of oxygen atoms/ions to various depths from the top surface of a mono-crystalline silicon wafer/substrate and then heat treated to form oxide layers thus forming silicon layers in-between the oxide layers, a layered ‘SIMOX’ process approach.
 
Step (E):  FIG. 2E  illustrates the structure after Step (E), including insulator regions such as silicon oxide  222 . Lithography and etch processes may then be utilized to construct a structure as shown in the figure.
 
Step (F):  FIG. 2F  illustrates the structure on after Step (F). Gate dielectric  226  and gate electrode  224  may then be deposited following which a CMP may be done to planarize the gate electrode  224  regions. Lithography and etch may be utilized to define gate regions. Gate dielectric  226  and gate electrode  224  may be, for example, a HKMG structure or a TEL SPA radical oxidation oxide and an appropriate work function electrode, for example, tungsten, degenerately doped polysilicon or amorphous silicon. Although the width of the p− regions  221  near and under the gates are illustrated as being larger than the thickness, one skilled in the art would recognize that the reverse (i.e., thickness larger than width) could be formed to provide increased gate control of the transistor channel.
 
Step (G):  FIG. 2G  illustrates the structure after Step (G). Using the hard mask defined in Step (F), p− regions not covered by the gate may be implanted to form n+ regions  228 . Spacers may be utilized during this multi-step implantation process and layers of silicon present in different layers of the stack may have different spacer widths to account for lateral straggle of buried layer implants. Bottom layers could have larger spacer widths than top layers. A thermal annealing step, such as a RTA or spike anneal or laser anneal or flash anneal, may then be conducted to activate n+ doped regions.
 
Step (H):  FIG. 2H  illustrates the structure after Step (H). A silicon oxide layer  230  may then be deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity, along with word-line (WL)  232  and source-line (SL)  234  regions.
 
Step (I):  FIG. 2I  illustrates the structure after Step (I). Vias may be etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material  236  may then be deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, which is well known to change resistance by applying voltage. An electrode for the resistance change memory element may then be deposited (preferably using ALD) and is shown as electrode/BL contact  240 . A CMP process may then be conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with transistors are created after this step.
 
Step (J):  FIG. 2J  illustrates the structure after Step (J). BLs  238  may be constructed. Contacts may be made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (I) as well.
 
 FIG. 2K  shows cross-sectional views of the array for clarity.
 
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
       FIG. 3A-L  describes an alternative process flow to construct a horizontally-oriented monolithic 3D resistive memory array. This embodiment has a resistance-based memory element in series with a transistor selector. One mask is utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in  FIG. 3A-L , and all other masks may be shared between different layers. The process flow may include several steps as described in the following sequence. 
     Step (A): Peripheral circuits  302  with tungsten wiring may be first constructed and above this a layer of silicon dioxide  304  may be deposited.  FIG. 3A  illustrates the structure after Step (A). 
     Step (B):  FIG. 3B  illustrates the structure after Step (B). A wafer of p− Silicon  306  may have an oxide layer  308  grown or deposited above it. Following this, hydrogen may be implanted into the p− Silicon wafer at a certain depth indicated by  310 . Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer  306  may form the top layer  312 . The bottom layer  314  may include the peripheral circuits  302  with oxide layer  304 . The top layer  312  may be flipped and bonded to the bottom layer  314  using oxide-to-oxide bonding.
 
Step (C):  FIG. 3C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) may be cleaved at the hydrogen plane  310  using either a anneal or a sideways mechanical force or other means. A CMP process may be conducted. At the end of this step, a single-crystal p− Si layer exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 3D  illustrates the structure after Step (D). Using lithography and then implantation, n+ regions  316  and p− regions  318  may be formed on the transferred layer of p− Si after Step (C).
 
Step (E):  FIG. 3E  illustrates the structure after Step (E). An oxide layer  320  may be deposited atop the structure obtained after Step (D). A first layer of Si/SiO 2    322  may be formed atop the peripheral circuit layer  302 . The composition of the ‘ SiO 2 ’ layer within the stacked Si/SiO 2  layers such as Si/SiO 2    322 , may be insulators or dielectrics other than silicon dioxide such as, for example, a low-k dielectric, carbon containing silicon oxides, amorphous carbon. The thickness of the ‘SiO 2 ’ insulator layer within the stacked Si/SiO 2  layers such as Si/SiO 2    322  may be adjusted to minimize layer to layer, strata to strata disturb mechanisms, and may include thicknesses of 50 nm, 75 nm, 100 nm, 150 nm, 200 nm, 500 nm, and less than 1000 nm. A thin conductive layer, such as a metal, may also be formed between the two bonding oxides to form a field shield to mitigate layer to layer, strata to strata disturb mechanisms, and may be electrically floating or tied to a bias, such as ground or Vdd. The stacked Si/SiO 2  layers, such as Si/SiO 2    322 , may alternatively be formed by successive ion implants of oxygen atoms/ions to various depths from the top surface of a mono-crystalline silicon wafer/substrate and then heat treated to form oxide layers thus forming silicon layers in-between the oxide layers, a layered ‘SIMOX’ process approach.
 
Step (F):  FIG. 3F  illustrates the structure after Step (F). Using procedures similar to Steps (B)-(E), additional Si/SiO 2  layers  324  and  326  may be formed atop Si/SiO 2  layer  322 . A rapid thermal anneal (RTA) or spike anneal or flash anneal or laser anneal may be done to activate implanted layers  322 ,  324  and  326  (and possibly also the peripheral circuit layer  302 ). Alternatively, the layers  322 ,  324  and  326  may be annealed layer-by-layer as soon as their implantations are done using a laser anneal system.
 
Step (G):  FIG. 3G  illustrates the structure after Step (G). Lithography and etch processes may be utilized to make a structure as shown in the figure.
 
Step (H):  FIG. 3H  illustrates the structure after Step (H). Gate dielectric  328  and gate electrode  330  may be deposited following which a CMP may be done to planarize the gate electrode  330  regions. Lithography and etch may be utilized to define gate regions over the p− silicon regions (eg. p− Si region  318  after Step (D)). Note that gate width could be slightly larger than p− region width to compensate for overlay errors in lithography. Gate dielectric  328  and gate electrode  330  may be, for example, a HKMG structure or a TEL SPA radical oxidation oxide and an appropriate work function electrode, for example, tungsten, degenerately doped polysilicon or amorphous silicon. Although the width of the p− regions  317  and n+ regions  315  near and under the gates are illustrated as being larger than the thickness, one skilled in the art would recognize that the reverse (i.e., thickness larger than width) could be formed to provide increased gate control of the transistor channel.
 
Step (I):  FIG. 3I  illustrates the structure after Step (I). A silicon oxide layer  332  may be deposited and planarized. It is shown transparent in the figure for clarity. Word-line (WL) and Source-line (SL) regions are shown in the figure.
 
Step (J):  FIG. 3J  illustrates the structure after Step (J). Vias may be etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material  336  may be deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, which is well known to change resistance by applying voltage. An electrode for the resistance change memory element may be deposited (preferably using ALD) and is shown as electrode/BL contact  340 . A CMP process may be conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with transistors are created after this step.
 
Step (K):  FIG. 3K  illustrates the structure after Step (K). BLs  336  may be constructed. Contacts may be made to BLs  338 , WLs  332  and SLs  334  of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 3-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be achieved in steps prior to Step (J) as well.
 
 FIG. 3L  shows cross-sectional views of the array for clarity.
 
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
     While the 3D DRAM and 3D resistive memory implementations in have been described with single crystal silicon constructed with ion-cut technology, other options exist. One could construct them with selective epi technology. Procedures for doing these will be clear to those skilled in the art. 
     Various layer transfer schemes described herein and in patent references incorporated can be utilized for constructing single-crystal silicon layers for memory architectures described herein and in incorporated references. 
       FIGS. 4A-B  show it is not the only option for the architecture, as depicted in  FIG. 1 - FIG. 3 , to have the peripheral transistors, such as within bottom side periphery  402 , below the memory layers, such as memory layer  1   404 , memory layer  2   406 , and memory layer  3   408 . Peripheral transistors, such as within topside periphery  410 , could also be constructed above the memory layers, as shown in  FIG. 4B , and may include substrate or memory layer  4   412 . This periphery layer would utilize technologies described herein, and could utilize junction-less transistors or recessed channel transistors, and may utilize optical annealing, shielding layers, and absorbers/reflectors as described in incorporated patent references. 
     The double gate devices shown in  FIG. 1 - FIG. 3  may have both gates connected to each other. Each gate terminal may be designed to be controlled independently, which may lead to design advantages for memory chips. 
     One of the concerns with using n+ Silicon as a control line for 3D memory arrays is its high resistance. Using lithography and (single-step of multi-step) ion-implantation, one could dope heavily the n+ silicon control lines while not doping transistor gates, sources and drains in the 3D memory array. This preferential doping may mitigate the concern of high resistance. 
     Over the past few years, the semiconductor industry has been actively pursuing floating-body RAM technologies as a replacement for conventional capacitor-based DRAM or as a replacement for embedded DRAM/SRAM. In these technologies, charge may be stored in the body region of a transistor instead of having a separate capacitor. This could have several potential advantages, including lower cost due to the lack of a capacitor, easier manufacturing and potentially scalability. There are many device structures, process technologies and operation modes possible for capacitor-less floating-body RAM. Some of these are included in “Floating-body SOI Memory: The Scaling Tournament”, Book Chapter of Semiconductor-On-Insulator Materials for Nanoelectronics Applications, pp. 393-421, Springer Publishers, 2011 by M. Bawedin, S. Cristoloveanu, A. Hubert, K. H. Park and F. Martinez (“Bawedin”). 
       FIG. 5A-5B  illustrates some of the potential challenges associated with possible high field effects in floating-body RAM. The Y axis of the graph shown in  FIG. 5A  may indicate current flowing through the cell during the write operation, which may, for example, consist substantially of impact ionization current. While impact ionization may be illustrated as the high field effect in  FIG. 5A , some other high field effect may alternatively be present. The X axis of the graph shown in  FIG. 5B  may indicate some voltage applied to the memory cell. While using high field effects to write to the cell, some challenges may arise. At low voltages  520 , not enough impact ionization current may be generated while at high voltages  522 , the current generated may be exponentially higher and may damage the cell. The device may therefore work only at a narrow range of voltages  524 . 
     A challenge of having a device work across a narrow range of voltages is illustrated with  FIG. 5B . In a memory array, for example, there may be millions or billions of memory cells, and each memory individual cell may have its own range of voltages between which it operates safely. Due to variations across a die or across a wafer, it may not be possible to find a single voltage that works well for substantially all members of a memory array. In the plot shown in  FIG. 5B , four different memory cells may have their own range of “safe” operating voltages  502 ,  504 ,  506  and  508 . Thus, it may not be possible to define a single voltage that can be used for writing substantially all cells in a memory array. While this example described the scenario with write operation, high field effects may make it potentially difficult to define and utilize a single voltage for reading substantially all cells in a memory array. This situation may be unique to floating-body RAM and may not be generally present in capacitor-based DRAM. Solutions to this potential problem may be required. 
       FIG. 6  illustrates an embodiment of the invention that describes how floating-body RAM chip  610  may be managed wherein some memory cells within floating-body RAM chip  610  may have been damaged due to mechanisms, such as, for example, high-field effects after multiple write or read cycles. For example, a cell rewritten a billion times may have been damaged more by high field effects than a cell rewritten a million times. As an illustrative example, floating-body RAM chip  610  may include nine floating-body RAM blocks,  601 ,  602 ,  603 ,  604 ,  605 ,  606 ,  607 ,  608  and  609 . If it is detected, for example, that memory cells in floating-body RAM block  605  may have degraded due to high-field effects and that redundancy and error control coding schemes may be unable to correct the error, the data within floating-body RAM block  605  may be remapped in part or substantially in its entirety to floating-body RAM block  608 . Floating-body RAM block  605  may not be used after this remapping event. 
       FIG. 7  illustrates an embodiment of the invention of an exemplary methodology for implementing the bad block management scheme described with respect to  FIG. 6 . For example, during a read operation, if the number of errors increases beyond a certain threshold, an algorithm may be activated. The first step of this algorithm may be to check or analyze the causation or some characteristic of the errors, for example, if the errors may be due to soft-errors or due to reliability issues because of high-field effects. Soft-errors may be transient errors and may not occur again and again in the field, while reliability issues due to high-field effects may occur again and again (in multiple conditions), and may occur in the same field or cell. Testing circuits may be present on the die, or on another die, which may be able to differentiate between soft errors and reliability issues in the field by utilizing the phenomenon or characteristic of the error in the previous sentence or by some other method. If the error may result from floating-body RAM reliability, the contents of the block may be mapped and transferred to another block as described with respect to  FIG. 6  and this block may not be reused again. Alternatively, the bad block management scheme may use error control coding to correct the bad data and may provide the user data about the error and correction. The read operation may end. 
     The following description is taken from Wikipedia: Resistive random-access memory (RRAM or ReRAM) is a non-volatile memory type under development by a number of different companies, some of which have patented versions of ReRAM. The technology bears some similarities to CBRAM and phase change memory. Different forms of ReRAM have been disclosed, based on different dielectric materials, spanning from perovskites to transition metal oxides to chalcogenides. Even silicon dioxide has been shown to exhibit resistive switching as early as 1967, and has recently been revisited. Leon Chua, who is considered to be the father of non-linear circuit theory, has argued that all 2-terminal non-volatile memory devices including ReRAM should be considered memristors. 
     The basic idea is that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage. The conduction path formation can arise from different mechanisms, including defects, metal migration, etc. Once the filament is formed, it may be reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance) by an appropriately applied voltage. Recent data suggests that many current paths, rather than a single filament, are probably involved. 
     A memory cell can be deduced from the basic memory cell in three different ways. In the simplest approach, the pure memory element can be used as a basic memory cell, resulting in a configuration where parallel bitlines are crossed by perpendicular wordlines with the switching material placed between wordline and bitline at every cross-point. This configuration is called a cross-point cell. Since this architecture will lead to a large “sneak” parasitic current flowing through non selected memory cells via neighboring cells, the cross-point array has a very slow read access. A selection element can be added to improve the situation, but this selection element consumes extra voltage and power. A series connection of a diode in every cross-point allows one to reverse bias, zero bias, or at least partially bias non-selected cells, leading to negligible sneak currents. This can be arranged in a similar compact manner as the basic cross-point cell. Finally a transistor device (ideally an MOS Transistor) can be added which makes the selection of a cell very easy and therefore gives the best random access time, but comes at the price of increased area consumption. 
     For random access type memories, a transistor type architecture is preferred while the cross-point architecture and the diode architecture open the path toward stacking memory layers on top of each other and therefore may be ideally suited for mass storage devices. The switching mechanism itself can be classified in different aspects. First there are effects where the polarity between switching from the low to the high resistance level (reset operation) is reversed compared to the switching between the high and the low resistance level (set operation). These effects are called bipolar switching effects. On the contrary, there are also unipolar switching effects where both set and reset operations require the same polarity, but different voltage magnitude. 
     In U.S. Pat. No. 8,026,521, which is incorporated by reference herein its entirety, a 3D architecture is presented for R-RAM. In U.S. Pat. No. 7,843,718, which is incorporated by reference herein its entirety, another 3D architecture has been presented utilizing a vertical structure of what one skilled in the art would call a NAND architecture for RRAM. In a NAND architecture only two diffusion contacts are required to access an R-RAM structure that is serially connected, sometimes called a NAND string or chain. 
     The RRAM or memeristors may include transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure. Typical RRAM materials may include transition metal oxides such as TiOx, NiOx, HFOx, WoX, TaOx, VoX, CuOx, SrToOx, CuSiOx, SiOx, TiON, and electrodes may include Pt, TiN/Ti, TiN, Ru, Ni, W, TaN, Ir, Au. STT-MRAM materials may include Ir, PtMn, CoFe, Ru, CoFeB, MgO, CoFeB, Ta. 
     As illustrated in  FIGS. 8A-8E , a process flow which may be utilized to form a 3D NAND R-RAM architecture utilizing junction-less transistors is shown and described. As illustrated in  FIG. 8A , multiple mono-crystalline heavily doped n+ silicon layers may be formed with insulator layers in-between and then lithography and etch processes may be utilized to make a structure, such as, for example, as shown in  FIG. 8A . Thus n+ silicon regions  829  and insulator regions  826  may be stacked and formed above peripheral circuits  802 , which may include the isolation and bonding insulator layer  811 . Processes to form the structure in  FIG. 8A  may include the steps described with respect to FIGS. 6A to 6E of U.S. Pat. No. 9,117,749 and in at least a portion of FIG. 101 in U.S. Pat. No. 8,273,610, incorporated herein by reference. The multi-layer/region stack structure may be formed within one lithographic and etch step, thus, the transistor elements or portions may have been defined by a common lithography step, which also may be described as a single lithography step, same lithography step, or one lithography step, or single masking step, same masking step, or one masking step. Peripheral circuits  802  may be constructed with tungsten, or conventional aluminum/copper, wiring and may have isolation and/or bonding oxide above it (in-between the top metallization/wiring of peripheral circuits  802  and the bottom n+ silicon region in the stack, such as isolation and bonding insulator layer  811 . Isolation and bonding insulator layer  811  may include an etch stop layer. The composition of the insulator regions  826  within the stacked Si/SiO 2  layers may be insulators or dielectrics such as, for example, silicon dioxide, a low-k dielectric, carbon containing silicon oxides, amorphous carbon. The thickness of insulator regions  826  within the stacked Si/SiO 2  layers may be adjusted to minimize layer to layer, strata to strata disturb and interference mechanisms, and may include thicknesses of 50 nm, 65 nm, 100 nm, 150 nm, 200 nm, 500 nm, and less than 1000 nm. Insulator regions  826  within the stacked Si/SiO 2  layers may include a thin conductive layer, such as a metal, which may be formed between the two bonding oxides/insulator layers to form a field shield to mitigate layer to layer, strata to strata disturb and interference mechanisms, and may be electrically floating, or may be tied to a bias, such as ground or Vdd. The stacked Si/SiO 2  layers may alternatively be formed by successive ion implants of oxygen atoms/ions to various depths from the top surface of a mono-crystalline silicon wafer/substrate and then heat treated to form oxide layers thus forming silicon layers in-between the oxide layers, a layered ‘SIMOX’ process approach, and then layer transferred on top of peripheral circuits  802 , or peripheral circuits may be formed on top of the memory stack. The peripheral circuits  802  may include memory control circuits as well as circuitry for other purposes and of various types, such as, for example, analog, digital, RF, or memory, as well as circuits/devices as described herein and in the referenced patents, publications, applications. The lithography steps in the formation processing may be done with precise alignment to the underlying peripheral circuits  802  as the stack layers are thin and the alignment marks on the peripheral circuits  802  substrate/layer may be visible at the short wavelengths utilized for precision alignment. If necessary, a step of a window etch could be added for better visibility of the underneath alignment marks. In general, precise alignment is the good alignment of a state of the art stepper which results in a less than 40 nm alignment error. All the lithography steps may be aligned accordingly. 
     As illustrated in  FIG. 8B , an intermediate structure may be formed wherein the select gates and memory transistor gates may be formed. A gate dielectric may be grown on the exposed surfaces of n+ silicon regions  829  (for example, with the TEL SPA tool radical oxidation oxide) or deposited substantially over the structure&#39;s surface, such as, for example, in the well-known HKMG formation processing using ALD or other conformal deposition technique. This step could use high temperature or other type of process to form the gate dielectric. A gate electrode material, such as, for example, doped amorphous or polysilicon, or the well-known metal stack of HKMG processing, may be deposited. The gate electrode material may be in-situ doped during deposition, or doped at a later step. Additional material, such as insulator material, for example silicon oxide, may be deposited to complete filling the gate fill regions between the ridges of Si/SiO 2  stacks and enable the following CMP step. CMP may be performed to planarize the gate electrode material and insulator fill material, and may be planarized substantially to the top of the Si/SiO2 region stacks, or partially into the etch stop/CMP stop material (not shown). The top face of the topmost insulator region of insulator regions  826  may include an insulating (unless removed later) etch stop/CMP stop material, such as, for example, SiN or a-carbon, placed on it at an earlier stage, so to provide a CMP stop, thus enabling the formation of separate gate and select gate regions. Although the width of the n+ regions  829  near and under the gates are illustrated as being larger than the thickness, one skilled in the art would recognize that the reverse (i.e., thickness larger than width) could be formed to provide increased gate control of the transistor channel. A lithographic pattern of photoresist  841  may be formed wherein the memory gate regions  830 , eventual resistor regions  831 , select gate regions  832 , and the top layer of the stack that is in-between memory gate regions  830  and eventual resistor regions  831 , and the top layer of the stack that is in-between the two legs of the select gate regions  832 , may be covered so to protect from the etch of the gate material. The remaining gate fill may then be etched to define gate structure regions shown in  FIG. 8B , thus forming the memory gate regions  830 , eventual resistor regions  831 , select gate regions  832 , and gate dielectric regions  858 . The photoresist  841  may be stripped at this point (not shown), and the structure filled with additional isolative material, such as an insulator material, for example silicon oxide, which may be deposited to complete filling the gap regions between the ridges of Si/SiO 2  stacks and the gate structure regions and enable the following CMP step. CMP may be performed to planarize the structure isolative fill material, and may be planarized to above to the top of the Si/SiO2 region stacks, thereby covering the entire structure. 
     As illustrated in  FIG. 8C , a lithographic pattern of etch opening photoresist  842  may be formed to be open over the eventual resistor regions  831  and may have a misalignment tolerance driven overlap of the top of the stack isolation layer. The lithographic pattern of photoresist  842  may protect the memory gate regions  830 , select gate regions  832 , and most of the stack regions from the etch, and the stack regions may be protected from the etch by the CMP/etch stop material on the topmost layer of the stack. An etch may be performed which may remove the eventual resistor regions  831 , associated isolative fill material, and associated gate dielectric regions  858  that is exposed/open by a lithographic pattern of etch opening photoresist  842 . Remaining after etch may include remaining isolative fill material region  835 , Si/SiO2 region stacks (partially shown) and (not shown) memory gate regions  830 , select gate regions  832 , and associated gate dielectric regions  858 . 
     As illustrated in  FIG. 8D , the RRAM/Memristor elements may be formed. Normally resistive RRAM/memristor resistive change material may be deposited, for example by ALD or other conformal deposition techniques, and then a second isolative fill, for example, silicon oxide may be performed and a CMP may be done to remove the resistive change material from the top surface of the structure, thus forming remaining resistive change material regions  833 , and second isolative fill regions  857 . The first isolative fill regions, other than the single illustrated remaining isolative fill material region  835 , are not shown for clarity. This flow is useful for RRAM/memristor resistive change material that is initially non-conducting and which could became conductive if the proper voltage is applied on it. An advantage of this suggested flow is that lithography could be applied for all groups of layers together. 
     As illustrated in  FIG. 8E , the entire structure may be covered with an interlayer dielectric (ILD), for example, SACVD silicon oxide, which may be planarized with chemical mechanical polishing. The ILD is shown transparent in the figure for clarity in illustration. Select metal lines  846  may be formed and connected to the associated select gate contacts, the contacts may be formed to overlap both related regions of select gate regions  832 . The select metal lines  846  signal may be routed to another metallization layer and parallel the WL direction (not shown). Word-line (WL) metallization  859  may be formed and connected to the associated gate contacts, the contacts may be formed to overlap the specific memory gate regions  830 . Cell source regions  844  may be formed by a trench contact etch and filled to couple to the N+ silicon regions on the source end of the NAND strings. BL contacts (not shown) can be made into stair-like structures of BL  852  (portions of N+ regions  829 ) using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on VLSI Technology , pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., and in U.S. Pat. No. 7,915,667, or using the staircase methods of “A stacked memory device on logic 3D technology for ultra-high-density data storage,”  Nanotechnology,  22 (2011) 254006 by J. Kim, et al. Through layer vias (not shown) may be formed to electrically couple the BL, SL, and WL metallization to the peripheral circuits  802 . 
     Persons of ordinary skill in the art will appreciate that the illustrations in  FIGS. 8A through 8E  are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, BL or SL contacts may be constructed in a staircase manner as described previously. Moreover, the stacked memory layer may be connected to a periphery circuit that may be above the memory stack. Additionally, each tier of memory could be configured with a slightly different donor wafer n+ layer doping profile. Further, the memory could be organized in a different manner, such as BL and SL interchanged, or where buried wiring for the memory array may be below the memory layers but above the periphery. Furthermore, cell source regions  844  could be tied to Vpp and the other side through select transistors and then the BL line which could be the N+ silicon to a staircase-like structure to control each layer using the BL lines. Moreover, if diagonal sneak paths (a sidewall programmable resistor than spans two layers in the stack rather than being only parallel to one layer) cannot be overcome with neighboring BL biasing schemes, than the commoned side of each string (where cell source regions  844  are) could be staircased to permit both sides of the selected gate column of the device selected to program/read, etc. to be biased appropriately to suppress the sneak. Moreover, the peripheral circuits could be formed to the side of the stack memory array on any of the stack layers or the substrate on which they sit. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. 
     It will also be appreciated by persons of ordinary skill in the art that the invention is not limited to what has been particularly shown and described hereinabove. For example, drawings or illustrations may not show n or p wells for clarity in illustration. Moreover, transistor channels illustrated or discussed herein may include doped semiconductors, but may instead include undoped semiconductor material. Further, any transferred layer or donor substrate or wafer preparation illustrated or discussed herein may include one or more undoped regions or layers of semiconductor material. Moreover, although the insulator between the stacked crystalline layers is identified as silicon oxide, other dielectrics may be utilized such as, for example, a low-k dielectric, carbon containing silicon oxides. Further, contacts may be formed, for example, as sidewall structures or end-wall structures, with various overlaps as required by the process and layout. Furthermore, the wiring of the peripheral circuits may be done using a lower melting point metal than tungsten, for example copper, and care taken not to exceed a damaging temperature during processing and may employ optical annealing. Rather, the scope of the invention includes both combinations and sub-combinations of the various features described herein above as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by the appended claims.