Patent Publication Number: US-9899248-B2

Title: Method of forming semiconductor packages having through package vias

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation-in-part of commonly owned U.S. patent application having Ser. No. 14/696,198 filed on Apr. 24, 2015 and entitled “Semiconductor Packages and Methods of Forming the Same” and claims priority to and the benefit of U.S. Provisional Application Ser. No. 62/087,167, filed on Dec. 3, 2014 and entitled “Semiconductor Packages and Methods of Forming the Same,” which applications are hereby incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along scribe lines. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging. 
     The semiconductor industry has experienced rapid growth due to continuous improvement in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20 nm node), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed, and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques for semiconductor dies. 
     As semiconductor technologies further advance, stacked semiconductor devices, e.g., three dimensional integrated circuits (3DICs), have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be installed or stacked on top of one another to further reduce the form factor of the semiconductor device. Package-on-package (POP) devices are one type of 3DIC wherein dies are packaged and are then packaged together with another packaged die or dies. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS. 1-16  are cross-sectional views of various intermediate steps of forming semiconductor device in accordance with some embodiments. 
         FIGS. 17A-17C  illustrate various cross-sectional views of opening profiles for a through via in accordance with some embodiments. 
         FIGS. 18-31  are cross-sectional views of various intermediate steps of forming semiconductor device in accordance with some embodiments. 
         FIGS. 32-34  are cross-sectional views of various intermediate steps of forming semiconductor device in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embodiments will be described with respect to embodiments in a specific context, namely a three dimensional (3D) integrated fan-out (InFO) package-on-package (PoP) device. Other embodiments may also be applied, however, to other electrically connected components, including, but not limited to, package-on-package assemblies, die-to-die assemblies, wafer-to-wafer assemblies, die-to-substrate assemblies, in assembling packaging, in processing substrates, interposers, substrates, or the like, or mounting input components, boards, dies or other components, or for connection packaging or mounting combinations of any type of integrated circuit or electrical component. 
       FIGS. 1 through 16  illustrate cross-sectional views of intermediate steps in forming a semiconductor package in accordance with some embodiments.  FIG. 1  is a cross-sectional view of a carrier substrate  40 . The carrier substrate  40  comprises, for example, silicon based materials, such as a silicon wafer, glass or silicon oxide, or other materials, such as aluminum oxide, a ceramic material, combinations of any of these materials, or the like. In some embodiments, the carrier substrate  40  is planar in order to accommodate further processing. In some embodiments, the carrier substrate  40  may be a wafer on which multiple package structures are formed. The carrier substrate  40  may be any suitable substrate that provides (during intermediary operations of the fabrication process) mechanical support for the layers over the carrier substrate  40 . 
       FIG. 2  is a cross-sectional view of a release layer  42  on the carrier substrate  40  in accordance with some embodiments. The release layer  42  may be formed of a polymer-based material, which may be removed along with the carrier substrate  40  from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer  42  is an epoxy-based thermal release material, which loses its adhesive property when heated, such as a Light-to-Heat-Conversion (LTHC) release coating. In other embodiments, the release layer  42  may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV light. The release layer  42  may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate  40 , or the like. 
       FIG. 3  is a cross-sectional view of a first patterned layer  44  on the release layer  42  in accordance with some embodiments. As will be discussed in greater detail below, the first patterned layer  44  is patterned with openings, in which through vias formed in subsequent processes will extend. The first patterned layer  44  may be a polymer (such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like), a nitride (such as silicon nitride or the like), an oxide (such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or a combination thereof, or the like), or the like, and may be formed, for example, by spin coating, lamination, Chemical Vapor Deposition (CVD), or the like. In some embodiments, the first patterned layer  44  is a photoresist material and is patterned by exposing to light through the patterned mask, creating first openings  47  in photoresist material. 
       FIG. 4  is a cross-sectional view of a seed layer  46  of a subsequently formed through via over the first patterned layer  44  and a portion of the release layer  42  in accordance with some embodiments. The seed layer  46  may be formed over the first patterned layer  44  and in the first openings  47  formed in the first patterned layer  44 . In some embodiments, the seed layer  46  is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. The seed layer  46  may be made of copper, titanium, nickel, gold, or a combination thereof, or the like. In some embodiments, the seed layer  46  comprises a titanium layer and a copper layer over the titanium layer. The seed layer  46  may be formed using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), a combination thereof, or the like. The seed layer  46  may comprise one or more layers. 
     As will be discussed in greater detail below, the seed layer  46  will be utilized to form through vias, after which, a portion of the seed layer  46  may be removed to form a recess. The thickness of the seed layer  46 , or if a composite seed layer is utilized, one or more layers of the composite seed layer, may be used to control a recess depth from a bottom surface of the first patterned layer  44  to the through vias  50  (see  FIG. 6 ). Accordingly, the thicknesses and the materials of the seed layer  46  may be selected to aid in the control of the recess. For example, in some embodiments, the seed layer  44  may comprise a layer of titanium and an overlying copper layer. In this embodiment, the titanium layer may be selectively removed, creating a recess and exposing the copper layer. In some embodiments, a first seed layer (e.g., a layer of titanium) has a thickness of about 0.01 μm to about 5 μm, and a second seed layer (e.g., a layer of copper) has a thickness of about 0.01 μm to about 5 μm. In other embodiments, other materials may be utilized. 
       FIG. 5  is a cross-sectional view of a second patterned layer  48  over the seed layer  46  with second openings  49  to expose at least a portion of the first openings  47  in accordance with some embodiments. The second patterned layer  48  may be formed by a wet process, such as a spin-on process, or by a dry process, or applying a dry film, and may be exposed to light for patterning. The patterning forms second openings  49  through the second patterned layer  48  to expose a portion of the seed layer  46  and the first openings  47 , and the width of the second openings  49  may be wider than the width of the first openings  47 . In some embodiments, the second patterned layer  48  comprises a photoresist layer and is patterned using photolithography techniques. In another embodiment, other materials such as silicon oxide or silicon nitride may be used as the second patterned layer  48 . 
       FIG. 6  is a cross-sectional view of a conductive material filling the first openings  47  (see  FIG. 3 ) and the second openings  49  (see  FIG. 5 ) of the second patterned layer  48  on the exposed portions of the seed layer  46  to form through vias  50  in accordance with some embodiments. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or a combination thereof, or the like, and may have a composite structure including a plurality of layers. As illustrated in  FIG. 6 , the through vias  50  comprise a body portion having a first width w 1  and a narrow projection having a second width w 2  as the through vias  50  extend through the first patterned layer  44 . The through vias  50  include a ledge or a recess having a width w 3  between the first width w 1  and the second width w 2 . The first width w 1  of the through vias  50  may be in a range from about 20 μm to about 500 μm, the second width of w 2  may be in a range from about 20 μm to about 500 μm, and the third width of w 3  may be in a range from about 0 μm to about 100 μm. A first height h 1  of the body portion of the through vias  50  may be in a range from about 20 μm to about 1000 μm, and a second height h 2  of the narrow projection of the through vias  50  may be in a range from about 0.01 μm to about 50 μm. 
       FIG. 7  is a cross-sectional view of the through vias  50  after removing the second patterned layer  48  (see  FIG. 6 ) in accordance with some embodiments. In some embodiments, in which the second patterned layer  48  comprises a photoresist material, the second patterned layer  48  may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like, and it may also be removed by rinsing in Acetone, Isopropanol, and deionized water, or the like. Once the second patterned layer  48  is removed, portions of the seed layer  46  that are not covered by the through vias  50  are exposed. 
       FIG. 8  illustrates removal of exposed seed layer  46  in accordance with some embodiments. The exposed seed layer  46  may be removed by, for example, using an acceptable etching process, such as by wet or dry etching, to expose at least a portion of the first patterned layer  44 . 
       FIG. 9  illustrates attaching an integrated circuit die  52  to the first patterned layer  44  in accordance with some embodiments. In some embodiments, the integrated circuit die  52  may be adhered to the first patterned layer  44  by an adhesive  54 , such as a die-attach film (DAF). A thickness of the adhesive  54  may be in a range from about 0.01 μm to about 100 μm. The integrated circuit die  52  may be a single die as illustrated in  FIG. 9 , or in some embodiments, two or more than two dies may be attached, and may include any die suitable for a particular approach. For example, the integrated circuit die  52  may include a static random access memory (SRAM) chip or a dynamic random access memory (DRAM) chip, a processor, a memory chip, logic chip, analog chip, digital chip, a central processing unit (CPU), a graphics processing unit (GPU), or a combination thereof, or the like. The integrated circuit die  52  may be attached to a suitable location for a particular design or application. For example,  FIG. 9  illustrates an embodiment in which the integrated circuit die  52  is mounted in a center region wherein the through vias  50  are positioned around a perimeter. In other embodiments, the integrated circuit die  52  may be offset from a center. Before being attached to the first patterned layer  44 , the integrated circuit die  52  may be processed according to applicable manufacturing processes to form integrated circuits in the integrated circuit die  52 . 
     In some embodiments, the integrated circuit die  52  is mounted to the first patterned layer  44  such that die connectors  56  are facing away from or distal to the first patterned layer  44 . The die connectors  56  provide an electrical connection to the electrical circuitry formed on the integrated circuit die  52 . The die connectors  56  may be formed on an active side of the integrated circuit die  52 , or may be formed on a backside and comprise through vias. The die connectors  56  may further comprise through vias providing an electrical connection between a first side and a second side of the integrated circuit die  52 . In an embodiment, the conductive material of the die connectors  56  is copper, tungsten, aluminum, silver, gold, tin, a combination thereof, or the like. 
       FIG. 10  illustrates encapsulating the integrated circuit die  52  and the through vias  50  by an encapsulant  58  in accordance with some embodiments. The encapsulant  58  is placed in gaps between the integrated circuit die  52  and around the through vias  50 . The encapsulant  58  may be molded on the integrated circuit die  52  and the through vias  50  using, for example, compression molding. In some embodiments, the encapsulant  58  is made of a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure and solidify the encapsulant  58 , wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof. Other encapsulating processes may be used, such as lamination, compression molding, or the like. 
     In some embodiments, the molding material completely covers the upper surfaces of the integrated circuit die  52 . In these embodiments, a planarization step, such as a grinding, may be performed on the molding material  58  to expose the integrated circuit die  52  and the die connectors  56 . In some embodiments, surfaces of the die connectors  56  and surfaces of the through vias  50  are planar with a surface of the molding material  58 . The through vias  50  may be referred to as through molding vias (TMVs), through package vias (TPVs), and/or through InFO (Integrated Fan-Out) vias (TIVs). 
       FIG. 11  illustrates formation of a redistribution structure  60  in accordance with some embodiments. The redistribution structure  60  may comprise any number of dielectric layers, metallization patterns, and vias. For example,  FIG. 11  illustrates an embodiment in which the redistribution structure  60  includes three dielectric layers  62 ,  64 ,  66  with respective metallization patterns and vias, as will be discussed below, although other embodiments may have fewer or more. 
     The first dielectric layer  62  is formed on the encapsulant  58  and die connectors  56 . In some embodiments, the first dielectric layer  62  is formed of a polymer, which may be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, that may be patterned using lithography. In other embodiments, the first dielectric layer  62  is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or the like. The first dielectric layer  62  may be formed by spin coating, lamination, Chemical Vapor Deposition (CVD), the like, or a combination thereof. The first dielectric layer  62  is then patterned to form openings to expose portions of the die connectors  56  and the through vias  50 . The patterning may be by an acceptable process, such as by exposing the first dielectric layer  62  to light when the dielectric layer is a photo-sensitive material or by etching using, for example, a patterned mask and an anisotropic etch. 
     First metallization pattern  70  with vias  72  is formed on the first dielectric layer  62 . As an example to form first metallization pattern  70  and vias  72 , a seed layer (not shown) is formed over the first dielectric layer  62  and in the openings formed in the first dielectric layer  62 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A mask is then formed and patterned on the seed layer in accordance with a desired redistribution pattern. In some embodiments, the mask is a photoresist formed by spin coating or the like and exposed to light for patterning. The pattern of the mask corresponds to the first metallization pattern  70  with vias  72 . The patterning forms openings through the mask to expose the seed layer. A conductive material is formed in the openings of the mask and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed, are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the first metallization pattern  70  and vias  72 . The second dielectric layer  64  is formed over the first dielectric layer  62  to provide a more planar surface for subsequent layers. In some embodiments, the second dielectric layer  64  is formed of polymer, a nitride, an oxide, or the like. In some embodiments, the second dielectric layer  64  is PBO formed by a spin-on process. 
     A third dielectric layer  66 , second metallization pattern  68 , and vias  74  are formed on the second dielectric layer  64  and first metallization pattern  70 . The third dielectric layer  66 , second metallization pattern  68 , and vias  74  can be formed using similar processes with similar materials as used for forming the first dielectric layer  62 , first metallization pattern  70 , and vias  72  as discussed above. The vias  74  interconnect metallization patterns  68  and  70 . A fourth dielectric layer  67  is formed on the third dielectric layer  66  and surrounding the second metallization pattern  68 . In some embodiments, the fourth dielectric layer  67  is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the fourth dielectric layer  67  is formed of a nitride or an oxide such as silicon nitride, silicon oxide, PSG, BSG, BPSG, or the like. The fourth dielectric layer  67  may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The fourth dielectric layer  67  is then patterned to create third openings  71 . The patterning may be by an acceptable process, such as by exposing the fourth dielectric layer  67  to light when the dielectric layer is a photo-sensitive material or by etching using, for example, an anisotropic etch. 
     The redistribution layer  60  may be referred to as a front side redistribution layer on the integrated circuit die  52 . This front side redistribution layer  60  may be utilized to provide an external electrical connection to the integrated circuit die  52  and/or to electrically couple the integrated circuit die  52  to the through vias  50 , which by be electrically coupled to one or more other packages, package substrates, components, the like, or a combination thereof. The numbers of illustrated metallization layers in the redistribution layer  60  are only for illustrative purposes and are not limiting. There may be any number of dielectric layers and metallization patterns different from those illustrated in  FIG. 11 . 
       FIG. 12  illustrates a formation of under bump metallizations (UBMs)  75  in the third openings  71  (see  FIG. 11 ) in accordance with some embodiments. The UBMs  75  may comprise multiple layers, such as a layer of titanium, followed by a layer of copper, and a third layer of Ni. In some embodiments, the UBMs  75  may comprises a layer of titanium (Ti) layer, a tantalum (Ta) layer, and a tantalum nitride (TaN) layer. The UBM pad may be patterned by electro-plating or electroless-plating method. 
       FIG. 13  illustrates the formation of a set of conductive connectors  76  over the UBMs  75  and electrically coupled to the redistribution layer  60 . The conductive connectors  76  may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, combination thereof (e.g., a metal pillar having a solder ball attached thereof), or the like. The conductive connectors  76  may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In an embodiment in which the conductive connectors  76  are solder bumps, the conductive connectors  76  are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors  76  are metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. 
       FIG. 14  illustrates removing the carrier substrate  40  and the release layer  42  to expose the first patterned layer  44 , and a removal of one or more layers of seed layer  46  on the through vias  50  in accordance with some embodiments. In some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer  42  (see  FIG. 13 ) so that the release layer decomposes under the heat of the light and the carrier substrate  40  can be removed. A cleaning and/or grinding process may be performed to remove residual portions of the release layer. In another embodiment, a thermal process, a chemical strip process, laser removal, a UV treatment, the like, or a combination thereof may be used. After the de-bonding of the carrier substrate  40  and the release layer  42 , one or more layers of seed layer  46  are exposed. One or more layers of the seed layer  46  is removed by acceptable etching process, such as by wet or dry etching. The through vias  50  are then exposed after the removal of the exposed seed layer. In some embodiments, one or more of layers of the seed layer  46  may remain over the through vias  50 . The thickness of removed layers of the seed layer  46  will control a recess depth between a surface distal to the encapsulant  58  of the first patterned layer  44  and an exposed surface of the seed layer  46  and/or the through vias  50 . The recess is discussed in greater detail below with reference to  FIGS. 17A-17C . 
       FIG. 15  illustrates the formation of a set of conductive connectors  78  over and electrically coupled to the through vias  50 . The conductive connectors  78  may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors  78  may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, a combination thereof, or the like. In an embodiment in which the conductive connectors  78  are solder bumps, the conductive connectors  78  are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors  78  are metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. A diameter of the conductive connectors  78  may be in a range from about 20 μm to about 500 μm. 
       FIG. 16  illustrates the conductive connectors  78  electrically coupled to a substrate  80  with an additional adhesive support of an adhesive material  82  in accordance with some embodiments. The substrate  80  may be any substrate, such as an integrated circuit die, a package, a printed circuit board, an interposer, or the like. In some embodiments, the adhesive material  82  may be epoxy or glue, and it may be applied to the conductive connectors  78 . In some embodiments, the conductive connectors  78  may attach directly to the through vias  50 . Light or UV light may be used for solidifying the adhesive material  82  between the wafer  80  and the conductive connectors  78 . 
     In some embodiments, UBM structures may also be utilized between the conductive connectors  78  and the through vias  50 . The UBM structures may be similar to the UBMs  75 . 
       FIGS. 17A-17C  illustrate various configurations of recesses  79  as illustrated in  FIG. 14 , in accordance with various embodiments. The use of a multi-layer seed layer allows the seed layers to be utilized to control a depth of the recess  79 . For example, in embodiments such as those illustrated in  FIGS. 17A-17C , a multi-layer seed layer  46  is utilized having a first seed layer  83  (such as a titanium layer) and a second seed layer  84  (such as a copper layer). In embodiments such as these, the thickness of the first seed layer  83  defines the depth of the recesses  79  by relying on the etch selectivity between the materials of the first seed layer  83  and the second seed layer  84  such that the second seed layer  84  acts as an etch stop layer for removing the first seed layer  83 . In some embodiments, the first seed layer  83  has a thickness and the recesses  79  have a depth R of about 0.01 μm to about 5 μm. In other embodiments, the first seed layer  83  and the second seed layer  84  may be removed from the ends of the through vias  50 , such that the seed layer  46  is completely removed and the through vias  50  are exposed. 
       FIGS. 17A-17C  further illustrate various sidewall profiles for the openings  47  (see  FIG. 3 ). For example,  FIG. 17A  illustrates an embodiment in which the projection of the through vias  50  has substantially vertical sidewalls extending through the first patterned layer  44 .  FIG. 17B  illustrates an embodiment in which the projection of the through vias  50  has a positive taper extending through the first patterned layer  44 , such that a width of the projection increases as the projection extends outward away from a central body of the through vias  50 . In an embodiment, the sidewalls of the projection have a positive taper angle (cc) of about 5 degrees to about 85 degrees. The angle (cc) of the positive taper may be adjusted by a dose from about 500 mJ/cm 2  to about 1000 mJ/cm 2 , and a focus depth from about 5 μm to about 10 μm during the lithography process. 
       FIG. 17C  illustrates an embodiment in which the projection of the through vias  50  has a negative taper extending through the first patterned layer  44 , such that a width of the projection decreases as the projection extends outward away from a central body of the through vias  50 . In an embodiment, the sidewalls of the projection have a negative taper angle ( 13 ) of about 5 degrees to about 85 degrees. The angle ( 13 ) of the positive taper may be adjusted by a dose from about 100 mJ/cm 2  to about 500 mJ/cm 2 , and a focus depth from about 15 μm to about 20 μm during the lithography process. The taper of the projection of the through vias  50  may be adjusted to reduce stress in a particular design. 
     Embodiments such as those disclosed herein allow contact to be made to the through vias  50  without the use of processes that may cause more damage or provide less control. For example, embodiments such as those herein utilize openings in the first patterned layer  44  and the seed layer structure to form recesses to the through vias  50 , relying on well-controlled selective etching processes, as opposed to laser drilling openings through a dielectric layer to provide electrical contact to the through vias. Techniques such as laser drilling may cause damage and provide less control over the profile and critical dimensions. 
       FIGS. 18 through 31  illustrate cross-sectional views of the various intermediate stages of manufacturing a package structure in accordance with some embodiments. The embodiment illustrated in  FIGS. 18-31  may utilize many similar structures and processes as discussed above with reference to  FIGS. 1-16  and  FIGS. 17A-17C , wherein like reference numbers refer to like elements that may be formed of similar materials using similar processes. Other materials and processes, however, may be utilized. Referring now to  FIG. 18 , there is shown a sacrificial layer  94  formed on the release layer  42  and carrier substrate  40 , wherein some embodiments may utilize the carrier substrate  40  and the release layer  42  as described above with reference to  FIGS. 1 and 2 . As will be discussed below, a structure will be formed on the carrier substrate  40  and then the carrier substrate  40  will be subsequently removed. The sacrificial layer  94  provides a protective layer to protect the subsequently formed polymer layer  44  (see  FIG. 19 ) during the subsequent removal of the carrier substrate  40  and release layer  42  (see, e.g.,  FIG. 29 ). After the removal process, the polymer layer  44  remains flat. 
     In some embodiments, the sacrificial layer  94  may be a polymer layer or a metal layer. The polymer layer may be, for example, a hexamethyldisilazane (HMDS) layer, or the like, and the metal layer may be, for example, a titanium (Ti) layer, or the like. The polymer layer may be deposited by spin coating, and the metal layer may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), sputtering, or the like. In some embodiments, the thickness of the HMDS layer is in a range from about 0.01 μm to about 5 μm. In another embodiment, the sacrificial layer  94  is a Ti layer formed by, for example, sputtering, CVD, PVD, or the like. The thickness of the Ti layer is in a range from about 0.01 μm to about 5 μm. 
       FIGS. 19 through 30  illustrate subsequent cross-sectional views of various intermediate steps, similar to those illustrated in  FIGS. 3-14 , respectively. Similar processes and materials may be used and will not be repeated herein, wherein like reference numbers refer to like elements. 
     Referring now to  FIG. 31 , removal of the sacrificial layer  94  (see  FIG. 30 ) and one or more layers of seed layer  46  are illustrated in accordance with some embodiments. The sacrificial layer  94  and the one or more layers of seed layer  46  may be removed by, for example, using an acceptable etching process, such as by wet or dry etching, to expose at least a portion of the first patterned layer  44  and the through vias  50 . The removal of the sacrificial layer  94  and the removal of one or more layers of seed layer  46  expose the through vias  50  and create recesses  79  as discussed above with reference to  FIGS. 17A-17C . The through vias  50  may be further electrically coupled to another semiconductor structures. The HMDS layer may be removed by, for example, plasma ashing, rinsing in Acetone, Isopropanol, or the like. The Ti layer may be removed by wet etching or dry etching. Thereafter, subsequent processing may be performed. For example, processing such as that discussed above with reference to  FIGS. 15 and 16  to form conductive connectors  78  (see  FIG. 15 ) and to couple a substrate  80  using the conductive connectors  78  and an adhesive material  82  (see  FIG. 16 ). Similar processes and materials may be used as in  FIGS. 15 and 16 , and will not be repeated herein. 
       FIGS. 32 through 34  illustrate cross-sectional views of the various intermediate stages of manufacturing a package structure in accordance with some embodiments. Referring first to  FIG. 32 , there is shown another structure in accordance with some embodiments. The embodiment illustrated in  FIG. 32  assumes processes similar to those used to form the structure illustrated in  FIG. 31  have been performed, wherein like reference numerals refer to like elements. Those processes will not be duplicated herein for brevity. Other materials and processes, however, may be utilized. 
     As shown in  FIG. 32 , the first patterned layer  44  is recessed such that a portion of the through vias  50  protrudes from the first patterned layer  44 . In some embodiments, the first patterned layer  44  may be recessed by etching using for example, dry etching, wet etching, a combination thereof, or the like. The dry etching process may include an ashing process, such as using argon, oxygen, a combination thereof, or the like, and an etching time may be used from about 30 seconds to about 50 seconds, such as 40 seconds, in order to accurately control the thickness of the first patterned layer  44 . As illustrated in  FIG. 32 , the first patterned layer  44  is thinned, thereby exposing sidewalls of the through vias  50 . In some embodiments, the protruding portion of the through vias  50  may have a third height h 3  of about 1 μm to about 5 μm, along sidewalls of the through vias  50 , which is inversely dependent on the thickness of the first patterned layer  44 . The protruding portion of the through vias  50  may provide a larger process window for package on wafer (POW) process, and it can reduce the solder wettability issues at the interface between through vias  50  and solder balls  75 . In another embodiment, the protruding portion may comprise a positive, negative, and vertical shape depending on the sidewall profiles of the openings  47 , as discussed above in  FIGS. 17  A-C. By adjusting a dose and a focus depth during the lithography process, the angle of sidewalls of the openings may be controlled. 
       FIGS. 33-34  illustrate cross-sectional views of steps of attaching a second package to the through vias  50 , similar to those illustrated in  FIGS. 15-16 , respectively. Similar processes and materials may be used and will not be repeated herein, wherein like reference numbers refer to like elements. 
     In some embodiments, a method of manufacturing a semiconductor device is provided. The method includes forming a first layer over a carrier substrate and forming first openings in the first layer. Through vias are formed over the first layer, such that the through vias extend into the first openings. An integrated circuit is placed over the first layer, and a molding compound is formed over the first layer, the molding compound extending along sidewalls of the integrated circuit and the through vias. A redistribution layer may be formed on the integrated circuit and the through vias. The carrier substrate is removed. 
     In another embodiment, a method of manufacturing a semiconductor device is provided. The method includes forming a first layer on a carrier substrate and forming openings in the first layer. One or more seed layers are formed along sidewalls and a bottom of the openings, over which through vias are formed such that the through vias extend into the openings. An integrated circuit is placed on the first layer, and a molding compound is formed on the first layer, the molding compound being interposed between the integrated circuit and the through vias. The carrier substrate may be removed. 
     In yet another embodiment, a semiconductor device is provided. The semiconductor device includes a first layer having an opening, and an integrated circuit on the first layer. An encapsulant is positioned on the first layer adjacent the integrated circuit, the encapsulant having a through via extending therethrough, the through via extending into the opening. The portion of the through via extending through the encapsulant has a width greater than the portion of the through via extending into the opening. 
     In some embodiments, a method of manufacturing a semiconductor device is provided. The method includes forming a first layer over a carrier substrate and forming first openings in the first layer. One or more seed layers are formed along a top surface of the first layer, sidewalls of the first openings, and a bottom of the first openings. Through vias are formed on the one or more seed layers, such that the through vias extend into the first openings. A semiconductor die is placed over the first layer, and a molding compound is formed adjacent to sidewalls of the through vias and the semiconductor die. The carrier substrate is removed. At least a portion one or more seed layers are removed to expose a top portion of the through vias and a portion of the first layer is remove to expose a portion of sidewalls of the through vias. 
     In another embodiment, a method of manufacturing a semiconductor device is provided. The method includes forming a first dielectric layer on a carrier substrate. One or more seed layers are formed over the first dielectric layer. Through vias are formed over the one or more seed layers, the one or more seed layers and the through vias extending through the first dielectric layer. An integrated circuit die is placed over the first dielectric layer, and an encapsulant is formed between the integrated circuit die and the through vias. The carrier substrate is removed, and then a portion of one or more seed layers and a portion of the first dielectric layer are removed to expose a portion of sidewalls of the through vias. 
     In yet another embodiment, a semiconductor device is provided. The semiconductor device includes a first dielectric layer, and an integrated circuit on the first dielectric layer. An integrated circuit is placed on the first dielectric layer. Through vias are placed to be surrounding the integrated circuit die and to be above the first dielectric layer. An encapsulant being on the first dielectric layer is interposed between the integrated circuit and the through vias. The portion of the through via protrudes from the first dielectric layer and have exposed sidewalls. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.