Patent Publication Number: US-2023155867-A1

Title: Adaptive receiver with pre-cursor cancelation

Description:
PRIORITY CLAIM 
     The present application is a continuation of U.S. application Ser. No. 17/648,899, entitled “ADAPTIVE RECEIVER WITH PRE-CURSOR CANCELATION,” filed Jan. 25, 2022 (now U.S. Pat. No. 11,558,223), which is a continuation of U.S. application Ser. No. 16/671,146, entitled “ADAPTIVE RECEIVER WITH PRE-CURSOR CANCELATION,” filed Oct. 31, 2019 (now U.S. Pat. No. 11,240,073), which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     Technical Field 
     Embodiments described herein are related to the field of high-speed interface design, and more particularly to canceling inter-symbol interference. 
     Description of the Related Art 
     Computing systems typically include a number of interconnected integrated circuits. In some cases, the integrated circuits may communicate using communication channels or links to transmit and receive data bits. The communication channels may support parallel communication, in which multiple data bits are transmitted in parallel, or serial communication, in which data bits are transmitted one bit at a time in a serial fashion. 
     The data transmitted between integrated circuits may be encoded to aid in transmission. For example, in the case of serial communication, data may be encoded to provide sufficient transitions between logic states to allow for clock and data recovery circuits to operate. Alternatively, in the case of parallel communication, the data may be encoded to reduce switching noise or to improve signal integrity. 
     During transmission of the data, the physical characteristics of the communication channel may attenuate a transmitted signal associated with a particular data symbol. For example, the impedance of wiring included in the communication channel or link may attenuate certain frequency ranges of the transmitted signal. Additionally, impedance mismatches between wiring included in the communication channel and devices coupled to the communication channel may induce reflections of the transmitted signal, which may also degrade subsequently transmitted signals corresponding to other data symbols. 
     SUMMARY OF THE EMBODIMENTS 
     Various embodiments of an apparatus and method for canceling inter-symbol interference in serial data transmission are disclosed. Broadly speaking, a method and apparatus are contemplated, in which, a summer circuit may be configured to receive an input signal that encodes a plurality of data symbols, and combine the input signal with a feedback signal to generate an equalized signal. A clock generator circuit may be configured to generate a clock signal using the equalized signal. A data slicer circuit may be configured to sample, using a plurality of voltage offsets and the clock signal, the equalized signal to generate a plurality of samples of a particular data symbol of the plurality of data symbols. A precursor compensation circuit may be configured to generate an output value for the particular data symbol using the plurality of samples, and a post cursor compensation circuit may be configured to generate the feedback signal using at least one of the plurality of samples and a value of a previously received data symbol. In another non-limiting embodiment, the data slicer circuits may be further configured to sample, using the plurality of voltage offsets, the equalized input signal to generate a plurality of error samples. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description makes reference to the accompanying drawings, which are now briefly described. 
         FIG.  1    is a block diagram that illustrates an embodiment of a receiver circuit with precursor cancelation. 
         FIG.  2    illustrates an input signal waveform. 
         FIG.  3    is a block diagram that illustrates an embodiment of a post-cursor compensation circuit. 
         FIG.  4    is a block diagram that illustrates an embodiment of a data slicer circuit. 
         FIG.  5    is a block diagram that illustrates a different embodiment of a data slicer circuit. 
         FIG.  6    is a block diagram that illustrates another embodiment of a data slicer circuit. 
         FIG.  7    is block diagram that illustrates an embodiment of a precursor compensation circuit. 
         FIG.  8    is a flow diagram depicting an embodiment of a method for operating a data receiver circuit that includes precursor cancelation. 
         FIG.  9 A  is a flow diagram depicting an embodiment of a method for adapting clock recovery. 
         FIG.  9 B  is a flow diagram depicting another embodiment of a method for adapting clock recovery. 
         FIG.  10    is a flow diagram depicting an embodiment of a method for performing clock recovery. 
         FIG.  11    is a block diagram depicting two devices coupled via a communication channel. 
         FIG.  12    illustrates an embodiment of a computer system. 
     
    
    
     While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the disclosure to the particular form illustrated, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include,” “including,” and “includes” mean including, but not limited to. 
     Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, paragraph (f) interpretation for that unit/circuit/component. More generally, the recitation of any element is expressly intended not to invoke 35 U.S.C. § 112, paragraph (f) interpretation for that element unless the language “means for” or “step for” is specifically recited. 
     As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. The phrase “based on” is thus synonymous with the phrase “based at least in part on.” 
     DETAILED DESCRIPTION OF EMBODIMENTS 
     A computing system may include one or more devices or integrated circuits, such as, e.g., a central processing unit (CPU) and memories. Each one of the integrated circuits of the computing system may communicate through either a serial or parallel interface. In a parallel interface, multiple data bits are communicated simultaneously, while in a serial interface, data is communicated as a series of sequential single data bits (commonly referred to as “symbols”). When employing a serial interface to communicate data between two devices or integrated circuits included in a computing system, the data may be transmitted according to different protocols. For example, the data may be transmitted using return to zero (RZ), non-return to zero (NRZ), pulse amplitude modulation (PAM), or any suitable combination thereof. 
     As symbols are transmitted, a signal in which the symbols are encoded may experience distortion. In some cases, the distortion accumulates from the medium through which the signal is propagating in a linear predictable form referred to as Inter-Symbol-Interference or “ISI.” As used herein, ISI is an impairment on a currently transmitted symbol that results from prior and future symbols. Previous symbols result in post-cursor ISI and future symbols result in pre-cursor ISI. 
     In order to reduce the effects of ISI in a computer system, various techniques may be employed, such as the use of a decision feedback equalizer (DFE). A DFE operates by sampling an incoming signal to generate a series of data symbols. The series of data symbols, some of which may be scaled, may be used to generate a signal that is combined with the incoming signal to cancel post-cursor ISI. This type of DFE is causal, which prevents the cancelation of precursor ISI. By only canceling post-cursor ISI, precursor ISI still has a significant impact on the performance of a channel between a transmitter circuit and a receiver circuit. 
     Various techniques, e.g., pre-cursor pre-emphasis, may be employed to reduce the impact of precursor ISI, but such techniques make adaptation within the receiver circuit difficult as the transmitter circuit does not have information regarding the channel response without communication from the receiver circuit. The embodiments illustrated in the drawings and described herein may provide techniques for mitigating the effects of precursor ISI, while providing for adaptation within the receiver circuit. 
     An embodiment of a data receiver circuit is illustrated in  FIG.  1   . As illustrated, data receiver circuit  100  includes summer circuit  101 , data sample circuit  102 , clock generator circuit  103 , precursor compensation circuit  104 , and post-cursor compensation circuit  105 . 
     Summer circuit  101  is configured to receive input signal  106  that encodes a plurality of data symbols  107 , and combine input signal  106  with feedback signal  113  to generate an equalized input signal (denoted as “equalized signal  109 ”). In various embodiments, summer circuit  101  may be a particular embodiment of a summing amplifier configured to combine voltage levels of two or more input signals into a single voltage level on an output signal. Summer circuit  101  may include, in various embodiments, a differential amplifier circuit or any other suitable amplifier circuit that may be used as a gain stage in a summing amplifier. 
     Clock generator circuit  103  is configured to generate clock signal  110  using equalized signal  109 . In some embodiments, clock generator circuit  103  may be configured to perform a process commonly referred to as “clock recovery” using equalized signal  109  in order to generate clock signal  110 . Clock generator circuit  103  may, in various embodiments, employ a phase detector circuit, along with phase-locked or delay-locked loop circuits, latch circuits, flip-flop circuits, or any other suitable combination of analog and/or digital circuits. 
     Phase detector circuits employed by clock generator circuits, such as clock generator circuit  103 , may be either linear or non-linear. For example, clock generator circuit  103  may use a non-linear bang-bang phase detector that is configured to compare a negative edge of clock signal  110  to a particular transition on equalized signal  109  for a current data symbol, and a different transition on equalized signal  109  for a previous data symbol. Using results of the comparison, timing of clock signal  110  may be adjusted using a delay-locked or phase-locked loop circuit. Alternatively, clock generator circuit  103  may employ a Mueller-Muller phase detector circuit configured to equalize respective amplitudes of samples taken before and after a pulse of clock signal  110  by adjusting the timing of clock signal  110 . It is noted that although only two types of phase detector circuits are described, in other embodiments, any suitable phase detector circuit may be employed. 
     Data sample circuit  102  is configured to sample, using voltage offsets  108  and clock signal  110 , equalized signal  109  to generate samples  111  of a particular data symbol of data symbols  107 . It is noted that some of samples  111  may be used to determine output data bits  112  (data samples), while others of samples  111  (error samples) may be used to perform adaptation within data receiver circuit  100 . As described below in more detail, data sample circuit  102  may include multiple data slicer circuits each coupled to a respective one of voltage offsets  108 . A particular data slicer circuit, which may be a particular embodiment of a differential amplifier circuit or any other suitable circuit, may be configured to compare a voltage level of equalized signal  109  to a voltage level of the data slicer circuit&#39;s corresponding voltage offset signal when clock signal  110  is asserted. 
     Precursor compensation circuit  104  is configured to generate output data bits  112  for the particular data symbol of data symbols  107  using samples  111 . As described below in more detail, precursor compensation circuit  104  may be a particular embodiment of an unrolled-loop decision feedback equalizer circuit that selects between different ones of samples  111 . In some cases, the selection is made using samples from one or more of data symbols  107  that were received prior to the particular data symbol. 
     Post-cursor compensation circuit  105  is configured to generate feedback signal  113  using at least one sample of samples  111  associated with the particular data symbol and a different sample associated with a different data symbol of data symbols  107  received prior to the particular data symbol. In various embodiments, post-cursor compensation circuit  105  may be a particular embodiment of a decision feedback equalizer (DFE) circuit or other suitable circuit configured to adjust a voltage level of feedback signal  113  using values of previously received data symbols. 
     It is noted that the embodiment depicted in  FIG.  1    is merely an example. In other embodiments, different circuit blocks or different arrangements of circuits blocks may be employed. 
     As noted above, when a particular data symbol is transmitted from a transmitter circuit to a receiver circuit, the signal encoding the particular data symbol may be affected by previously transmitted data symbols as well as data symbols transmitted after the particular data symbol. The resultant effect of the precursor and post-cursor symbols is illustrated in the example waveform depicted in  FIG.  2   . 
     As illustrated, variation in the voltage level of input signal  200  as a function of time is depicted. In various embodiments, input signal  200  may correspond to input signal  106  as depicted in  FIG.  1   . Contributions from a precursor symbol are indicated by hm1 offset  202 , and a contribution from a post-cursor symbol is indicated by h1 offset  203 . 
     In some cases, prior to transmission, input signal  200  may be modified using a finite impulse response (FIR) filter to cancel the precursor contribution to input signal  200 . The usefulness of such filtering is limited as it may reduce the dynamic range of input signal  200  at the transmitter circuit, as well as introduce other precursor contributions to input signal  200 . 
     Residual precursor contributions may adversely affect the performance of a communication channel or link. The amount of input signal  200  may be modified by the FIR filter to cancel precursor effects is limited as the more emphasis that is used for a first precursor symbol generates a larger residue for other precursor symbols. Residual precursor contributions may result in clock data recovery circuits to lock early, or result in edge/data offsets less than half of unit interval (UI)  204 . 
     Post-cursor compensation circuit  105  may be a particular embodiment of a FIR filter. A block diagram illustrating an embodiment of post-cursor compensation circuit  105  is depicted in  FIG.  3   . As illustrated, post-cursor compensation circuit  105  includes delay circuit  301 , weight circuit  302 , and summer circuit  303 . 
     Delay circuit  301  receives samples  111  and generates tap signals  304 . Each of tap signals  304  is a replica of samples  111 , delayed by a particular period of time. For example, an initial one of tap signals  304  is delayed from samples  111  by the particular period of time. A next one of tap signals, subsequent to the initial one of tap signals  304 , is delayed from the initial one of tap signals  304  by the particular period of time. Delay circuit  301  may include multiple latch circuits, flip-flop circuits, or any other circuits suitable for generating the desired delay between tap signals. 
     Weight circuit  302  is configured to generate weighted signals  305  using tap signals  304  and voltage offsets  108 . In various embodiments, weight circuit  302  may generate a particular voltage on a given one of weighted signals  305  using a value of a corresponding one of tap signals  304  and a corresponding one of voltage offsets  108 . Weight circuit  302  may include multiple amplifier circuits, which may be configured to buffer, based on, at least in part, tap signals  304 , respective voltage levels of voltage offsets  108 . 
     Summer circuit  303  may be a particular embodiment of a summing amplifier circuit configured to add respective voltage levels of weighted signals  305  to generate feedback signal  113 . In various embodiments, summer circuit  303  may be implemented as an operational amplifier or any other suitable amplifier circuit configured to generate an output signal whose voltage level is a sum of respective voltage levels of two or more input signals. 
     Data sample circuit  102  may be implemented according to a variety of circuit topologies employing different numbers of data slicer circuits (or simply “slicer circuits”) and offset voltages.  FIGS.  4 - 6    illustrate different circuit topologies that may be employed for data sample circuit  102 . 
     Turning to  FIG.  4   , a block diagram of an embodiment of data sample circuit  102  is depicted. As illustrated, data sample circuit  102  includes slicer circuits  401 - 410 . Each of slicer circuits  401 - 410  is coupled to equalized signal  109  and a respective one of offsets  413 - 422 . Slicer circuits  401 - 406  are configured to generate samples  423 - 428 , respectively, using offsets  413 - 418 , respectively. Slicer circuits  407 - 410  are configured to generate error samples  429 - 432 , respectively, using offsets  419 - 422 , respectively. It is noted that offsets  413 - 422  may be included in voltage offsets  108  and samples  423 - 432  may be included in samples  111 . 
     A variety of offset values may be used in conjunction with the embodiment illustrated in  FIG.  4   . A particular set of voltage offset values are illustrated in Table 1. As used herein, H0 is a voltage level that corresponds to a target amplitude of equalized signal  109 , H1 is a voltage level that corresponds to an effective magnitude of a first post-cursor value, and Hm1 is a voltage level that corresponds to an effective magnitude of a first precursor value. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Offset Values for FIG. 4 
               
            
           
           
               
               
               
            
               
                   
                 Offset 
                 Value 
               
               
                   
                   
               
               
                   
                 413 
                 H1 
               
               
                   
                 414 
                 −H1 
               
               
                   
                 415 
                 H1 + Hm1 
               
               
                   
                 416 
                 −H1 − Hm1 
               
               
                   
                 417 
                 H1 − Hm1 
               
               
                   
                 418 
                 −H1 + Hm1 
               
               
                   
                 419 
                 −H0 + H1 + Hm1 
               
               
                   
                 420 
                 −H0 + H1 − Hm1 
               
               
                   
                 421 
                 H0 + H1 + Hm1 
               
               
                   
                 422 
                 H0 + H1 − Hm1 
               
               
                   
                   
               
            
           
         
       
     
     Using the offset values listed in Table 1, samples  423  and  424  may be used to generate raw bit decisions within precursor compensation circuit  104 . Additionally, slicer circuits  407 - 410  provide coverage of 50% of the voting pattern possible for a value of a particular symbol, which allows for good tracking of changes in the channel response for the purpose of clock/data recovery. 
     Each of slicer circuits  401 - 406  may be a particular embodiment of a clocked differential amplifier circuit configured to generate a digital value using results of a comparison of input signals when a clock signal is asserted. For example, slicer circuit  401  may be configured to generate sample  423  by comparing equalized signal  109  to offset  413  when clock signal  110  is asserted. If, at the time clock signal  110  is asserted, a voltage level of equalized signal  109  is greater than a voltage level of offset  413 , sample  423  may be set to a particular logic value. Alternatively, if, at the time clock signal  110  is asserted, the voltage level of equalized signal  109  is less than the voltage level of offset  413 , sample  423  may be set to a different logic value. In some embodiments, slicer circuits  401 - 406  may include a latch or other suitable storage circuit configured to store a particular value of a sample until another assertion of clock signal  110 . 
     Slicer circuits  407 - 410  may be particular embodiments of a differential amplifier circuit configured to generate a digital value using results of a comparison of respective input signals and equalized signal  109 . Unlike slicer circuits  401 - 406 , slicer circuits  407 - 410  do not employ clock signal  110 , thereby providing samples that change as the voltage level of equalized signal  109  changes relative to offsets  419 - 422 . 
     Another embodiment of data sample circuit  102  is depicted in  FIG.  5   . In this embodiment, data sample circuit  102  includes slicer circuits  501 - 507 . It is noted that slicer circuits  501 - 505  may be configured to operate in a similar fashion to slicer circuits  401 - 406  as illustrated in  FIG.  4   , and that slicer circuits  506  and  507  may be configured to operate in a similar fashion to slicer circuits  407 - 410 . 
     In the case of the embodiment of  FIG.  5   , clock generator circuit  103  is configured to lock when H1 is equal to Hm1, which results in a locking point close to a peak in the pulse response received from the communication link. Since H1 and Hm1 are equal, fewer slicer circuits are needed. For example, one less data slicer circuit is employed, along with two fewer error slicer circuits. Additionally, a reference digital-to-analog converter (DAC) may be eliminated. By employing fewer slicer circuits and reference DACs, circuit complexity, area, and power consumption may be reduced. 
     The voltage offsets for the embodiment of data sample circuit  102  depicted in  FIG.  5    are illustrated in Table 2. As above, offsets  510 - 516  may be included in voltage offsets  108 . 
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 Offset Values for FIG. 5 
               
            
           
           
               
               
               
            
               
                   
                 Offset 
                 Value 
               
               
                   
                   
               
               
                   
                 510 
                 H1 
               
               
                   
                 511 
                 −H1 
               
               
                   
                 512 
                 H1 + Hm1 
               
               
                   
                 513 
                 −H1 − Hm1 
               
               
                   
                 514 
                 0 
               
               
                   
                 515 
                 −H0 
               
               
                   
                 516 
                 −H0 + H1 + Hm1 
               
               
                   
                   
               
            
           
         
       
     
     In some cases, further simplifications to data sample circuit  102  may be made at the expense of performance. An example of such modifications is illustrated in the embodiment of data sample circuit  102  depicted in  FIG.  6   . As illustrated, the embodiment of data sample circuit  102  of  FIG.  6    includes slicer circuits  601 - 605 . It is noted that slicer circuits  601 - 603  may be configured to operate in a similar fashion to slicer circuits  401 - 406  as illustrated in  FIG.  4   , and that slicer circuits  604  and  605  may be configured to operate in a similar fashion to slicer circuits  407 - 410 . 
     As noted in Table 3 below, the offsets used in the raw bit slicer circuits, i.e., slicer circuits  601  and  602 , are a function of both H1 and Hm1. While reducing the need for three additional data slicer circuits from the embodiment of  FIG.  4   , an H1 tap error of 2Hm1 is introduced for certain patterns processed by precursor compensation circuit  104 . 
     The voltage offsets for the embodiment of data sample circuit  102  depicted in  FIG.  6    are illustrated in Table 3. As above, offsets  606 - 610  may be included in voltage offsets  108 . 
     
       
         
           
               
               
               
             
               
                   
                   
               
               
                   
                 Offset 
                 Value 
               
               
                   
                   
               
             
            
               
                   
                 606 
                 H1 + Hm1 
               
               
                   
                 607 
                 −H1 − Hm1 
               
               
                   
                 608 
                 0 
               
               
                   
                 609 
                 −H0 
               
               
                   
                 610 
                 −H0 + H1 − Hm1 
               
               
                   
                   
               
            
           
         
       
     
     Turning to  FIG.  7   , a block diagram of an embodiment of precursor compensation circuit  104  is depicted. As illustrated, precursor compensation circuit  104  includes latch circuits  701 - 703 , and N-bit lookahead processing circuit  704 . 
     Each of latch circuits  701 - 703  represents multiple instances of latch circuits, each coupled to different clock signals to capture respective ones of Hm1 samples&lt;7:0&gt;705, −Hm1 samples&lt;7:0&gt;706, and 0 samples&lt;7:0&gt;707, all of which may be included in samples  111 . Each of Hm1 samples&lt;7:0&gt;705 is sampled during a respective unit interval using a voltage level corresponding to Hm1. In a similar fashion—Hm1 samples&lt;7:0&gt;706 and 0 samples&lt;7:0&gt;707 are sampled in a similar fashion using a negative version of the voltage corresponding to Hm1, and a voltage level at or near ground potential, respectively. It is noted that although  FIG.  7    depicts eight samples for each input, in various embodiments, any suitable number of samples may be employed. 
     N-bit lookahead processing circuit  704  may be configured to select a value for a particular data symbol based on values of future data symbols. In various embodiments, N-bit lookahead processing circuit  704  may employ different number of future bits in its determination of the value for the particular data symbol. 
     In one case, N-bit lookahead processing circuit  704  may employ 1-bit lookahead, where an immediate future data symbol is used to select one of the precursor bits, i.e., one of Hm1 samples&lt;7:0&gt;705 or one of −Hm1 samples&lt;7:0&gt;706. Alternatively, N-bit lookahead processing circuit  704  may employ 2-bit future data symbols to select an appropriate one of Hm1 samples&lt;7:0&gt;705 or −Hm1 samples&lt;7:0&gt;706 as output. It is noted that any suitable number of future data symbols may be employed. 
     In various embodiments, N-bit lookahead processing circuit  704  may include multiple selection circuits coupled to Hm1 samples&lt;7:0&gt;705, −Hm1 samples&lt;7:0&gt;706, and 0 samples&lt;7:0&gt;707, as well as signals  708 - 710 . The selection circuits may be arranged in parallel, series, or any suitable combination thereof. 
     In various embodiments, the selection circuits may be particular embodiments of multiplex or other suitable circuits configured to generate output signals by selecting a particular one of multiple inputs using respective control signals. A given selection circuit may, in some embodiments, include one or more pass gates, multiple logic gates, or any suitable combination thereof. 
     Structures, such as those shown in  FIGS.  1 - 7   , for canceling inter-symbol interference may be referred to using functional language. In some embodiments, these structures may be described as including “a means for receiving an input signal that encodes a plurality of data symbols,” “a means for combining the input signal with a feedback signal to generate an equalized signal,” “a means for generating a clock signal using the equalized signal,” “a means for sampling, using a plurality of voltage offsets and the clock signal, the equalized signal to generate a plurality of samples of a particular data symbol of the plurality of data symbols,” “a means for generating an output value for the particular data symbol using the plurality of samples,” and “a means for generating the feedback signal using at least one of the plurality of samples and a value of a previously received data symbol.” 
     The corresponding structure for “means for receiving an input signal that encodes a plurality of data symbols” is summer circuit  101  and its equivalents. The corresponding structure for “means for combining the input signal with a feedback signal to generate an equalized signal” is summer circuit  101  and other equivalent circuits. The corresponding structure for “means for generating a clock signal using the equalized signal” is clock generator circuit  103  and its equivalents. Data sample circuit  102  and its equivalents are the corresponding structure for “means for sampling, using a plurality of voltage offsets and the clock signal, the equalized signal to generate a plurality of samples of a particular data symbol of the plurality of data symbols.” The corresponding structure for “means for generating an output value for the particular data symbol using the plurality of samples” is latch circuits  701 - 703  and N-bit lookahead processing circuit  704 , and their equivalents. Delay circuit  301 , weight circuit  302 , and summer circuit  303  and their equivalents are the corresponding structure for “means for generating the feedback signal using at least one of the plurality of samples and a value of a previously received data symbol.” 
     Turning to  FIG.  8   , a flow diagram depicting an embodiment of a method for operating a data receiver circuit that includes a precursor compensation circuit is illustrated. The method, which may be applied to receiver circuit  100  as depicted in  FIG.  1   , begins in block  801 . 
     The method includes receiving an input signal that encodes a plurality of data symbol (block  802 ). In various embodiments, the method may include receiving the input signal from a transmitter circuit via a channel. A value of a particular one of the plurality of data symbols may, in some embodiments, correspond to a plurality of bits. 
     The method also includes combining the input signal with a feedback signal to generate an equalized input signal (block  803 ). In various embodiments, the method may also include adding respective voltage levels of the input signal and the feedback signal to generate the equalized input signal. 
     The method further includes generating a clock signal using the equalized input signal (block  804 ). In various embodiments, the method may also include receiving a reference clock signal, and generating the clock signal using the reference clock signal. In some cases, the method may include phase-locking the clock signal to one or more transitions included in the equalized input signal. 
     The method also includes sampling, using a plurality of voltage offsets and the clock signal, the equalized input signal to generate a plurality of samples of a particular data symbol of the plurality of data symbols (block  805 ). In various embodiments, the method may also include sampling, using the plurality of voltage offsets, the equalized input signal to generate a plurality of error samples. In some cases, the method may include generating the clock signal using the equalized input signal and the plurality of error samples. 
     The method further includes generating an output value for the particular data symbol using the plurality of samples (block  806 ). In some embodiments, the method may include predicting one or more future data symbols using the plurality of samples. The method may include, in various embodiments, adapting the plurality of voltage offsets using at least one of the one or more future data symbols. 
     In various embodiments, the plurality of voltage offsets may include a voltage offset corresponding to a contribution to the voltage level of the input signal resulting from a particular future data symbol of the one or more future data symbols. In some cases, the voltage offset corresponding to the contribution to the voltage level of the input signal results from the particular future data symbol is equal to a contribution to the voltage level of the input signal resulting from a particular past data symbol. 
     The method also includes generating the feedback signal using at least one of the plurality of samples and a value of a previously received data symbol (block  807 ). In some embodiments, the method may include comparing the equalized input signal to a sum of the voltage offset corresponding to the contribution to the voltage level of the input signal resulting from the particular future data symbol and the voltage offset corresponding to a contribution to the voltage level of the input signal resulting from the particular past data symbol. In such cases, the method may also include comparing the equalized input signal to a difference between a negative version of the voltage offset corresponding to the contribution to the voltage level of the input signal resulting from the particular future data symbol and the voltage offset corresponding to a contribution to the voltage level of the input signal resulting from the particular past data symbol. The method concludes in block  808 . 
     As described above, while receiving data, operational parameters of clock generator circuit  103  may be adjusted or adapted to when equalized signal  109  is sampled during a unit interval. Such an adaptation process may allow for adjustment of the sampling point to maintain the sampling point at or near a peak of the pulse response received via a communication channel or link. An embodiment of a method of for adapting a clock generator circuit is illustrated in  FIG.  9 A . The method, which may be applied to data receiver circuit  100  and used in conjunction with the method depicted in  FIG.  8   , begins in block  901 . 
     The method includes adapting clock data recovery using samples generated with a voltage level associated with a first post-cursor symbol (block  902 ). As described above, different slicer circuits use different comparison voltage levels to generate respective samples. The various samples may be used not only to determine a value for a received symbol, but also to adjust clock data recovery operation. In the present embodiment, only samples generated using the voltage level associated with the first post-cursor symbol may be used. Samples generated using other voltage levels, which may correspond to other precursor or post-cursor symbols, may be ignored. 
     In some embodiments, the method may include adjusting one or more operational parameters of clock generator circuit  103 . Adjusting such parameters may include writing one or more values into respective control registers included in clock generator circuit  103 . The method concludes in block  903 . 
     Multiple methods may be used to adapt clock data recovery in a data receiver circuit. An embodiment of another method for adapting clock data recovery is depicted in the flow diagram of  FIG.  9 B . The method, which may be applied to data receiver circuit  100  and used in conjunction with the method depicted in  FIG.  8   , begins in block  904 . 
     The method includes gathering post DFE error samples (block  905 ). As described above, data sample circuit  102  generates not only data samples, but error samples as well. In some cases, the data and error samples are further processed by post-cursor compensation circuit  105  in order to generate feedback signal  113 . Error samples that have been processed by post-cursor compensation circuit  105  may be stored in a latch, register, or other suitable storage circuit for later use. 
     The method also includes adapting clock data recovery using the post DFE error samples (block  906 ). In this case, adjustments to the operational parameters of clock generator circuit  103  may be made using the error samples, which have been operated upon by post-cursor compensation circuit  105 . Other processed samples, or other samples that have not been processed by post-cursor compensation circuit  105  may be ignored. 
     As with the method depicted in  FIG.  9 A , the method may include adjusting one or more operational parameters of clock generator circuit  103 . In some cases, the adjusting may include writing one or more values into respective control registers included in clock generator circuit  103 . The method concludes in block  907 . 
     Turning to  FIG.  10   , a flow diagram illustrating an embodiment of a method for performing clock data recovery is depicted. The method, which may be applied to data receiver circuit  100 , begins in block  1001 . 
     The method includes setting an edge/data offset to half of a unit interval (block  1002 ). In various embodiments, the edge/data offset is used to sample equalized signal  109 , and is selected to half of the unit interval based on an assumption that equalized signal  109  will be at its maximum value for a particular symbol half way through the unit interval for the particular symbol. 
     The method further includes adapting clock/data recovery circuit parameters (block  1003 ). As characteristics of the communication link or channel changes, the location of a peak of equalized signal  109  may move away from the middle of the unit interval for the particular symbol. When this occurs, the edge/data offset may be adjusted to move it towards the peak of equalized signal  109 . In various embodiments, the method may include writing one or more values to registers used by or included in clock generator circuit  103 . It is noted that block  1003  may correspond to either of the methods depicted in  FIG.  9 A  or  FIG.  9 B . The method concludes in block  1004 . 
     An example of two computer systems coupled via a communication channel in a computer network is depicted in  FIG.  11   . As illustrated, computer network  1100  includes computer systems  1101  and  1102 , each coupled to communication channel  1105 . It is noted that although only two computer systems are depicted in the embodiment depicted in  FIG.  11   , in other embodiments, any suitable number of computer systems may be included in computer network  1100 . 
     Computer system  1101  includes transmitter circuit  1103 . In various embodiments, transmitter circuit  1103  may transmit data to computer system  1102  using communication channel  1105 . Transmitter circuit  1103  may reformat data prior to transmitting. Such reformatting may include converting parallel data into a serial stream of data symbols, as well as the addition of error detection and correction data bits. 
     Communication channel  1105  may include one or more wires, circuit board traces, fiber optic cables, or any other suitable medium capable of propagating a signal that encodes multiple data symbols. In some cases, the medium may be selected to provide a particular impedance between the two computer systems. In such cases, transmitter circuit  1103  and data receiver circuit  100  may include circuit elements to match an impedance of the medium used in communication channel  1105 . Although only a single communication channel is depicted in the embodiment of  FIG.  11   , in other embodiments, any suitable number of communication channels between computer systems  1101  and  1102  may be employed. 
     As described above, data receiver circuit  100  may be configured to receive the signal transmitted by transmitter circuit  1103  via communication channel  1105 . Data receiver circuit  100  may be further configured to compensate for both precursor and post-cursor interference resulting from the transmission of the signal via communication channel  1105 , in order to recover data bits encoded in the signal. 
     A block diagram of a computer system is illustrated in  FIG.  12   . In the illustrated embodiment, computer system  1200  includes processor circuit  1202 , memory circuit  1203 , input/output circuits  1204 , and analog/mixed-signal circuits  1205 , each of which may be configured to send and receive data using communication bus  1206 . In various embodiments, computer system  1200  may be configured for use in a desktop computer, server, or in a mobile computing application such as, e.g., a tablet, or laptop computer, and may correspond to either of computer system  1101  or computer system  1102  as illustrated in  FIG.  11   . 
     Processor circuit  1202  may, in various embodiments, be representative of a general-purpose processor circuit that performs computational operations. For example, processor circuit  1202  may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA), or other suitable processing circuit. 
     Memory circuit  1203  may, in various embodiments, include any suitable type of memory such as a Dynamic Random-Access Memory (DRAM), a Static Random-Access Memory (SRAM), a Read-only Memory (ROM), an Electrically Erasable Programmable Read-only Memory (EEPROM), or a non-volatile memory, for example. It is noted that in the embodiment illustrated in  FIG.  12   , a single memory circuit is depicted. In other embodiments, any suitable number of memory circuits may be employed. 
     Input/output circuits  1204  includes data receiver circuit  100 , and may be configured to coordinate data transfer between computer system  1200  and one or more devices using communication channel  1207 . In various embodiments, communication channel  1207  may employ a serial data transfer protocol and data receiver circuit  100  may determine values for received data symbols as described above. Such devices may include, without limitation, storage devices (e.g., magnetic or optical media-based storage devices including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral devices. In some embodiments, input/output circuits  1204  may be configured to implement a version of Universal Serial Bus (USB) protocol or IEEE 1394 (Firewire®) protocol. In various embodiments, communication channel  1207  may correspond to communication channel  1105  as illustrated in  FIG.  11   . 
     Input/output circuits  1204  may also be configured to coordinate data transfer between computer system  1200  and other computer systems or integrated circuits coupled to computer system  1200  via a network. In one embodiment, input/output circuits  1204  may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as Gigabit Ethernet or 10-Gigabit Ethernet, for example, although it is contemplated that any suitable networking standard may be implemented. In some embodiments, input/output circuits  1204  may be configured to implement multiple discrete network interface ports. 
     Analog/mixed-signal circuits  1205  may include a variety of circuits including, for example, a crystal oscillator, a phase-locked loop (PLL), an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC) (all not shown). In other embodiments, analog/mixed-signal circuits  1205  may be configured to perform power management tasks with the inclusion of on-chip power supplies and voltage regulators. 
     It is noted that the embodiment of a computer system depicted in  FIG.  12    is merely an example. In other embodiments, different numbers of circuit blocks along with different arrangements of circuit blocks may be employed. 
     Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure. 
     The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.