Patent Publication Number: US-9430159-B2

Title: Non-volatile memory devices and controllers

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This Application claims priority of Taiwan Patent Application No. 103135326, filed on Oct. 13, 2014, the entirety of which is incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a non-volatile memory devices and a controller, and more particularly to a non-volatile memory devices and a controller which have a recovery function performed after an abnormal status occurs. 
     2. Description of the Related Art 
     In recent years, non-volatile memories, such as flashes, are developed rapidly and applied for various electronic devices. At present, non-volatile memories will be developed continuously in capacity and operation technique. When a large amount of data is stored in non-volatile memories, it becomes more important to provide an effective and reliable recovery machine for abnormal statuses, such as power being off suddenly, in order to ensure the accuracy and security for the stored data. 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment of a non-volatile memory device is provided. The non-volatile memory device comprises a non-volatile memory, a connection interface, and a controller. The non-volatile memory is divided into a plurality of physical blocks. Each physical block is divided into a plurality of physical pages. The connection interface is connected to a host. The controller receives a series of write commands from the host through the connection interface, and address of the write commands correspond to logic pages in a corresponding logic block. The controller selects one physical block from the plurality of physical block to serve as an operation physical block and writes the different logic pages of the different logic blocks into the operation physical block. When the controller performs a recovery operation after an abnormal status occurs, even though there is remaining space in the operation physical block, the controller re-selects another physical block to serve as the operation physical block for following data write operation. 
     An exemplary embodiment of a controller for a non-volatile memory device is provided. The non-volatile memory device comprises a non-volatile memory and a connection interface. The non-volatile memory is divided into a plurality of physical blocks. Each physical block is divided into a plurality of physical pages, and the connection interface is connected to a host. The controller receives a series of write commands from the host through the connection interface, and address of the write commands correspond to logic pages in a corresponding logic block. The controller selects one physical block from the plurality of physical block to serve as an operation physical block and writes the different logic pages of the different logic blocks into the operation physical block. When the controller performs a recovery operation after an abnormal status occurs, even though there is remaining space in the operation physical block, the controller re-selects another physical block to serve as the operation physical block for following data write operation. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows an exemplary embodiment of a system; 
         FIG. 2  shows an exemplary embodiment of a detailed structure of devices of  FIG. 1 ; 
         FIG. 3  shows an exemplary embodiment of relationship between the physical blocks and pages; 
         FIG. 4  shows a schematic view showing grouping of physical blocks according to an exemplary embodiment; 
         FIG. 5  shows a schematic view showing corresponding relationship between logic blocks and physical blocks by recording in a table according to an exemplary embodiment; 
         FIG. 6  shows a schematic view showing correlation between logic blocks and physical blocks according to another exemplary embodiment; 
         FIG. 7  shows an exemplary embodiment of a block of a memory element of an NAND flash memory; 
         FIG. 8  shows a schematic view showing stored charge and operation voltages of a triple-level cell (PLC) flash memory according of to an exemplary embodiment; 
         FIG. 9  shows a schematic view showing the case occurs when an operation voltage VT_ 1  is applied according to an exemplary embodiment; 
         FIG. 10  shows a schematic view showing the case in which one read operation is performed by using seven operation voltages successively according to an exemplary embodiment; 
         FIG. 11  shows an exemplary embodiment of a method for finding the CSB. 
         FIG. 12  shows an exemplary embodiment of a method for finding the MSB. 
         FIG. 13  shows a schematic view showing corresponding relationship of the operation physical block before and after an abnormal status occurs; and 
         FIG. 14  shows a flow chart of a method for finding which pages are valid pages by a controller. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     An embodiment of the invention provides a non-volatile memory device and a controller therein. The non-volatile memory device is implemented, for example, by an external flash device or a flash external hard disk. The non-volatile memory device can be connected to a host through a connection interface, such as USB or STATA to serve as a storage device of the host. The non-volatile memory device comprises one or more non-volatile memory cells and also comprises one or more random-access memories or conventional magnetic hard disk. The host transmits access instructions, such as read or write instructions, to the non-volatile memory device via the connection interface. The controller performs operations to the memory cells according to these read or write instructions. 
     In order to speed up entire access speed or reduce wastage of flash memories, some random-access memories are configured as caches or buffers. In other words, some data is not written directly into the flash memories, but temporarily into the random-access memories. In another manner, single-level cell (SLC) flash memories with higher speed are configured as the first stage cache, and cheaper multi-level cell (MLC) flash memories are configured to practically store a large amount of data. 
     These manners may induce some efficiency. However, when abnormal statuses occurs, such when the user takes off the non-volatile memory device from the host without appropriate measure while the power is off suddenly, a recovery operation, such as re-writing, may be performed for some data. 
     In an embodiment of the recovery operation performed after the abnormal statue occurs, for unstable data pages, such as data pages which belong to the same hardware circuit element or region with other data pages and are influenced by each other, in order to avoid extension of errors, the valid data pages are copied into another physical block, and the original physical block is not used any more. The embodiment also includes a process in which, when it is determined which one is valid data, only a portion of the data is read and it is determined whether the read portion of the data is valid data according to a statistics value for speeding up the determination. 
     In the following, a structure applied to the above embodiments is provided. Then, the embodiment will be illustrated by referring to figures. 
     Referring to  FIG. 1 , a first embodiment of the invention is shown. 
     A computer  10  comprises an USB transmission interface  102  and performs a data access operation to an USB disk  12  through the USB transmission interface  102 . The above description is given as an example without limitation for the invention. For example, the computer  10  can be replaced with any other electronic device, such as a mobile phone, a table computer, a television, a camera, or any electronic apparatus requiring data storage. The USB disk  12  can be replaced with any other type of external storage device connected to the computer  10  or an internal storage device within the computer  10 . The USB transmission interface  102  can be replaced with another data transmission interface, such as IEEE 1394, DATA, MS, MMC, SD, CF, IDE, or PCI interface. 
     An USB disk, an external hard disk, an internal magnetic disk, or a flash disk is given as an example. When the data storage device is connected to an electronic device, such as a computer, through a transmission interface, the electronic device can perform a read operation to the data storage device to determine whether the data storage device is formatted. If the data storage device has not be formatted yet, the electronic device usually asks the user to format the data storage device or not. When the user decides to format the data storage device, the electronic device sends a command to the data storage device, such that the data storage device performs a format operation by itself in response to the command. In another manner, the electronic device provides a detailed control instruction required for the format, to, for example, to build a file table in the data storage device and fill predetermined values. 
     Referring to  FIG. 2 , an exemplary embodiment of a detailed structure of the devices of  FIG. 1 . 
     A host  20  comprises a management module  201  and a first transmission interface  203 . The host  203  accesses a data storage device  22  by hardware, software, or a combination of hardware and software via the first transmission interface  203 . The host  20  described herein corresponds to the computer  10  of  FIG. 1 . In an embodiment, the management module  201  comprises a combination of an operation system, performed on the host, for file and data storage, a corresponding drive program, and related control circuits. 
     The data storage device  22  comprises a second transmission interface, a microcontroller  221 , a buffering memory  229 , a memory management module  223 , a code reorganizing module  225 , and a first module interface  231 . The data storage device  22  further comprises a memory module  24 . The memory module  224  comprises a second module interface, a control circuit  243 , and a memory block array  245 . 
     In the embodiment, the second transmission interface  227  corresponds to the first transmission interface  203  of the host  20 , for example, to provide related process of signal transmission in machine and electronic aspect.. The buffering memory  229  is used for buffering or cache architecture building during the signal transmission. The entire operation of the data storage device  22  is performed through generating an appropriate control signal by a predetermined instruction code, which is performed by the microcontroller  221 , to control the operation of each element at the appropriate time. The memory management module  223  and the reorganizing module  225  may be implemented by circuit hardware or operate according to the instruction code which is assigned to the microcontroller  221  through circuits and performed by the microcontroller  221 . In an alternative embodiment, the memory management module  223  and the reorganizing module  225  may be implemented in response to the corresponding instruction code which is performed by the microcontroller  221 . 
     The first module interface  231  is used to communication with the memory module  24 . The second module interface in the memory module  24  corresponds to the first module interface  231 . The control circuit  243  accesses the memory block array  245  in response to the instruction of the microcontroller  221 . The memory block array  245  comprises a plurality of flash memory physical blocks. 
     The memory management module  223  comprises process logic and a table for intercomparison and recoding of the physical blocks and logic blocks. Moreover, the data storage device  22  may further comprise an error correcting module (not shown). 
     The reorganizing module  225  is responsible for reorganizing the original data which was written into the memory module  24  to generate corresponding reorganized coding data and further reversely reorganize the reorganized coding data which is read from the memory module  24  to revert the value of the original data. The above operation comprises position exchanging of a bit at a specific position, inverting of the bits at a part of the positions, and reverse code reorganizing for the data at the odd address and the even address in different manners. 
     The objective of the code reorganizing is to achieve data stability. For example, in the flash memory, if the values of the adjacent units are the same, such as both being “0”or “1”, the storage stability of the stored data may be influenced due to electronic characteristics. In other words, through the code reorganizing, the values stored in the adjacent units are “0”and “1”in the interlaced pattern, which enhances the storage stability of the data. Thus, if there is a code reorganizing function, the storage quality can be maintained even though flash memories with lower cost are used. 
     The code reorganizing may be performed for other objectives, for example, for avoiding the data stored in the data storage device from reading by unauthorized users. The code reorganizing can be implemented by any coding manners which have been currently known or will be developed in the future. The manners in which the original data is coded, decode, and then recovered to the original data are within the scope of the code reorganizing. 
       FIG. 3  shows an exemplary embodiment of the relationship between the physical blocks and pages in the flash memory. 
     In  FIG. 3 , there are four physical blocks PB 1 , PB 2 , PB 3 , and PB 4 . Each physical block is further divided into a plurality of pages P 1 , P 2 , P 3  . . . P 12 . In the embodiment, one physical block corresponds to twelve pages. In practical design, the number of pages in one physical block is determined and adjusted according to different requirements. In different applications, the physical blocks and the pages may have different names, or even the physical blocks and the pages are grouped, which have known by one skilled in the art, thus omitting the related description. 
     For flash memories, such as NAND flash memories or NOR flash memories, before the flash memories which have not used yet operate a write operation, the physical blocks have t be erased. The erasing operation is performed by one unit of one physical block, while the write operation is performed by one unit of one page. The physical blocks which have been erased can perform the data write operation to the expected pages. However, in the case that one certain page has experienced the write operation, if it wants to perform the write operation to the certain page again, the physical block including the certain page has to experience the erasing operation first. 
     Since the range of the physical block is larger than the range of the page, if the page which has been experienced the write operation will be written again, the data movement has to be performed in advance. In other words, the data at the same address in logic may be moved from one physical block to another physical block during the data write and re-write processes. 
       FIG. 4  shows a schematic view showing the grouping of physical blocks according to an exemplary embodiment. 
     Referring to  FIG. 1 , all of the physical blocks are grouped into three types: a system block group  41 , a data block group  43 , and a backup block group  45 . The system block group  41  is used to store system data, such as the table of the logic blocks and the physical blocks, the instruction codes of the microcontroller, and various indexes. Expect the system block group  41 , the data block group  43  comprises the physical blocks which practically store data. The backup block group  45  comprises the physical blocks for data movement and backup. 
     As described above, when one page which has experienced the write operation will be written again, the erasing operation has to be performed for the one page in advance. In other words, the data of the other page in the physical block where the one page is disposed are also copied to another physical block, which is selected from the backup block group  45 , with the data of the one page. After the data is copied to the selected physical block from the backup block group  45 , the selected backup block is grouped into the data block group  43 , while the original physical block experiences the erasing operation and is grouped into the backup block group  45 . 
     In other words, not only the physical block corresponding the logic address varies all the time, but also the relationship between the physical block and the area varies. Thus, the system has to record the corresponding relationship between the logic blocks and the physical blocks. 
       FIG. 5  shows a schematic view showing the corresponding relationship between the logic blocks and the physical blocks according to an exemplary embodiment. In the embodiment, the logic block LB 0  corresponds to the physical bock PB 5 , the logic block LB 1  corresponds to the physical bock PB 0 , the logic block LB 2  corresponds to the physical bock PB 6 , and the logic block LB 3  corresponds to the physical bock PB 9 . 
     The data storage device may store the above corresponding relationship by tables or other manners. 
       FIG. 5  shows a schematic view showing the corresponding relationship between the logic blocks and the physical blocks by recording in a table. In the embodiment of  FIG. 6 , the logic block  435  corresponds to the physical bock  221 , the logic block  212  corresponds to the physical bock  779 , the logic block  112  corresponds to the physical bock  832 , and the logic block  554  corresponds to the physical bock  21 . 
       FIG. 7  shows an exemplary embodiment of a block of a memory element of an NAND flash memory. There are pages with a predetermined number on the block, such as pages P_ 0 , P_ 1 , P_ 2 , . . . , P_N. Each page comprises a plurality of memory cells M_ 0 , M_ 1 , M_ 2 , . . . , M_K. Through setting appropriate voltages VG_ 0 , VG_ 1 , VG_ 2 , . . . , VG_N respectively to the pages, the potential stored at the floating gate of each memory cell can be readout, thereby obtaining the data stored in each memory cell. 
     For a single-level cell (SLC) flash memory, each memory cell store data with only one bit, that is “0”or “1”. For this case, in theory, how much the charge is stored in each memory cell can be detected by applying appropriate setting voltages VG_ 0 , VG_ 1 , VG_ 2 , . . . , VG_N respectively to the pages, and then the value of the corresponding data can be obtained. 
     In opposition, a multi-level cell (MLC) flash memory, several various setting voltages have to be applied for one read operation to determine how much the charge is stored in each memory cell and then calculate the practical contents stored in the memory cells. 
       FIG. 8  shows a schematic view showing stored charge and operation voltages of a triple-level cell (PLC) flash memory according of to an exemplary embodiment. As shown in  FIG. 8 , for one memory cell, the stored data is  111 ,  011 ,  001 , . . . , or  110  respectively when the amount of the stored charge is in the range L 0 , L 1 , L 2 , . . . , or L 7 . 
     For this memory cell, in theory, when the operation voltage VT_ 1  is applied, the detection circuit may detect whether the charge stored in the memory cell belongs to the portion including the range L 0  (that is the data “ 111 ”) or the portion including the ranges L 1 , L 2 , L 3 , L 4 , L 5 , L 6 , and L 7  (that is the data “ 011 ”, “ 001 ”, “ 101 ”, “ 100 ”, “ 000 ”, “ 010 ”, or “ 110 ”). 
     Through applying combination of several voltages in a specific order, in theory, the data with three bits can be determined, that is the contents of the most signification bit (MSB), the central signification bit (CSB), and the least significant bit (LSB). 
     However, as described, with the development of the semiconductor manufacturing process toward higher density and with the achievement in lowering the cost and lengthening the usage time of the flash memories, the issue of the stability of the related circuits and memory cells becomes more important. 
       FIG. 9  shows a schematic view showing the case in which the readout data is not correct when the operation voltage VT_ 1  is applied to the memory cell due to overlapping or even shift in the states of bits. In this case, for solving the issue of the incorrect data, various error correction manners are required or the operation voltage has to be dynamically adjusted. 
       FIG. 10  shows a schematic view showing the case in which the read operation is performed to the memory cell by using seven different voltages and the amount of charge at the floating gate of the memory cell is detected to determine whether the value of the LSB of the data stored in the memory cell is “0”or “1”. 
     As shown in  FIG. 10 , if the amount of charge stored in the memory cell is on the left side of the voltage VLSB (that is L 0 , L 1 , L 2 , or L 3 ), it represents that the content of LSB is “0”. In contrary, if the amount of charge stored in the memory cell is on the right side of the voltage VLSB (that is L 4 , L 5 , L 6 , or L 7 ), it represents that the content of LSB is “1”. 
     Since there is overlapping between the states, the various voltages VLSB, VLSB+D, VLSB−D, VLSB+ 2 D, VLSB− 2 D, VLSB+ 3 D, and VLSB− 3 D may be applied successively. Accordingly, if the amount of charge stored in the memory cell is between LSB+D and LSB, certainly significant information can obtained according to the detection result. 
     The result for one bit can be obtained every time when one voltage applied. Thus, result for seven bits can be obtained by applying voltages by seven times. There are eight possible combinations for the seven buts. The correction code may be calculated and the correct bit data can be fined by the LDPC decoding circuit and manner based on the bit sequence corresponding to the seven bits. That is, the error correction is performed by using the obtained soft information with LDPC and BCH. 
       FIG. 11  shows an exemplary embodiment of a method for finding the CSB. CSB represents the second bit. As shown in  FIG. 11 , if the amount of charge stored in the memory cell is in the range L 2 , L 3 , L 4 , or L 5 , it represents that the content of CSB stored in the memory cell is “0”. In contrary, if the amount of charge stored in the memory cell is in the range L 0 , L 1 , L 6 , or L 7 , it represents that the content of CSB stored in the memory cell is “1”. In this configuration, it can be understood easily that two operation voltages VCSB 1  and VCSB 2  are required to find which range the amount of charge stored in the memory cell is in. 
     Similarly, several step adjustment degrees can be applied to the operation voltages VCSB 1  and VCSB 2 , such that the read operation is performed by using different voltages successively. The bit sequence is generated according to the readout result obtained each time. The bit sequence is used to perform the error correction in coordination with LDPC and BCH. 
       FIG. 12  shows an exemplary embodiment of a method for finding the MSB. MSB represents the highest bit. As shown in  FIG. 12 , if the amount of charge stored in the memory cell is in the range L 0 , L 3 , L 4 , or L 5 , it represents that the content of MSB stored in the memory cell is “1”. In contrary, if the amount of charge stored in the memory cell is in the range L 1 , L 2 , L 5 , or L 6 , it represents that the content of MSB stored in the memory cell is “0”. 
     Similarly, several step adjustment degrees can be applied to the operation voltages VCSB 1 , VCSB 2 , VCSB 3 , and VCSB 4 , such that the read operation is performed by using different voltages successively. The bit sequence is generated according to the readout result obtained each time. The bit sequence is used to perform the error correction in coordination with LDPC and BCH. 
     After the various structure and configuration is described, an exemplary embodiment of a recovery method performed after an abnormal status occurs. 
     First,  FIG. 13  shows two physical blocks  1301  and  1302 . The physical block was selected from the several physical block before the abnormal status to serve as operation physical block. When the controller performs a write operation to a non-volatile memory device (such as a flash memory), different physical blocks are accessed always for the write operation performed each time. The operation physical block is used as a block into which a controller writes all data, even though a series of write operation is performed for different logic blocks. 
     For example, in the physical block  1301 , when P 0001 ˜P 0005  correspond to five logic pages (not shown) of the first logic block, P 0006 ˜P 0007  correspond to two logic pages (not shown) of the second logic block. The corresponding relationship can be accomplished by maintaining a table by the controller. 
     After the abnormal status is relieved, the controller checks the data and the related tables and attempts to recover the repairable data. In the recovery operation, one step is to select one new operation physical block  1302 . The previous physical block  1301  is not used any more. 
     Moreover, in a multi-level flash memory, several memory cells may belong to the same hardware element, or there may be a hardware element between the several memory cells. In order to prevent the hardware element from operating unstably due to an abnormal status (such as power being off suddenly) and further prevent the following operations from experiencing the errors, the controller copies the contents of one or more physical pages P 101 , P 011 , and P 012  which are lastly written into the previous operation physical block  1301  to the new operation physical block  1302 . Moreover, since the physical pages have been moved to the new operation physical block, the controller also adjusts the table to correct the corresponding relationship between the physical pages and the logic pages. 
       FIG. 14  shows a flow chart of a method for finding which pages are valid pages in the operation physical block when the controller performs the recovery operation. First, the controller cancels code reorganizing, error correcting, and retry machine (step  1401 ). Then, the controller reads a predetermined amount of data one page by one page, such as the data of 1 K bits (step  1403 ). The controller calculates how many bits with the value “1”among the read data (step  1405 ). If the number of bits with the value “1”is less than or equal to five (step  1407 ), the controllers determines that the page is a blank page (step  1409 ), otherwise, the controllers determines that the page is a valid page (step  1411 ). After the determination operation, the controller updates the table (step  1413 ). Thus, if there is new data required to be written, the controller can know whether there is sufficient space in the operation physical block and know which page serves as the first page for the write operation if there is sufficient space. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.