Patent Publication Number: US-11640974-B2

Title: Memory array isolation structures

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application claims the benefit of U.S. Provisional Application No. 63/045,992, filed on Jun. 30, 2020, which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. Semiconductor memories include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. 
     On the other hand, non-volatile memories can keep data stored on them. One type of non-volatile semiconductor memory is Ferroelectric random access memory (FeRAM, or FRAM). Advantages of FeRAM include its fast write/read speed and small size. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A,  1 B, and  1 C  illustrate a perspective view, a circuit diagram, and a top down view of a memory array in accordance with some embodiments. 
         FIGS.  2 ,  3 A,  3 B,  4 ,  5 ,  6 ,  7 ,  8 ,  9 ,  10 ,  11 ,  12 A,  12 B,  13 ,  14 ,  15 ,  16 ,  17 A,  17 B,  18 A,  18 B ,  19 A,  19 B,  20 ,  21 ,  22 A,  22 B,  23 A,  23 B,  23 C,  24 A,  24 B,  24 C,  25 A,  25 B,  25 C,  26 A,  26 B,  26 C,  27 A,  27 B,  27 C,  28 A,  28 B,  28 C, and  28 D illustrate varying views of manufacturing a memory array in accordance with some embodiments. 
         FIGS.  29 ,  30 , and  31    illustrate varying views of a memory array in accordance with some embodiments. 
         FIGS.  32 A and  32 B  illustrate characteristics of a device in accordance with some embodiments. 
         FIGS.  33 A,  33 B,  33 C, and  33 D  illustrates illustrate a memory array in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Various embodiments provide a 3D memory array with a plurality of vertically stacked memory cells. Each memory cell includes thin film transistor (TFT) having a word line region acting as a gate electrode, a bit line region acting as a first source/drain electrode, and a source line region acting as a second source/drain electrode. Each TFT further includes an insulating memory film (e.g., as a gate dielectric) and an oxide semiconductor (OS) channel region. 
       FIGS.  1 A,  1 B, and  1 C  illustrate examples of a memory array according to some embodiments.  FIG.  1 A  illustrates an example of a portion of the memory array  200  in a three-dimensional view;  FIG.  1 B  illustrates a circuit diagram of the memory array  200 ; and  FIG.  1 C  illustrates a top down view of the memory array  200  in accordance with some embodiments. The memory array  200  includes a plurality of memory cells  202 , which may be arranged in a grid of rows and columns. The memory cells  202  may further stacked vertically to provide a three dimensional memory array, thereby increasing device density. The memory array  200  may be disposed in the back end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in the interconnect layers of the semiconductor die, such as, above one or more active devices (e.g., transistors) formed on a semiconductor substrate. 
     In some embodiments, the memory array  200  is a flash memory array, such as a NOR flash memory array, or the like. Each memory cell  202  may include a thin film transistor (TFT)  204  with an insulating, memory film  90  as a gate dielectric. In some embodiments, a gate of each TFT  204  is electrically coupled to a respective word line (e.g., conductive line  72 ), a first source/drain region of each TFT  204  is electrically coupled to a respective bit line (e.g., conductive line  106 ), and a second source/drain region of each TFT  204  is electrically coupled to a respective source line (e.g., conductive line  108 ), which electrically couples the second source/drain region to ground. The memory cells  202  in a same horizontal row of the memory array  200  may share a common word line while the memory cells  202  in a same vertical column of the memory array  200  may share a common source line and a common bit line. 
     The memory array  200  includes a plurality of vertically stacked conductive lines  72  (e.g., word lines) with dielectric layers  52  disposed between adjacent ones of the conductive lines  72 . The conductive lines  72  extend in a direction parallel to a major surface of an underlying substrate (not explicitly illustrated in  FIGS.  1 A and  1 B ). The conductive lines  72  may have a staircase configuration such that lower conductive lines  72  are longer than and extend laterally past endpoints of upper conductive lines  72 . For example, in  FIG.  1 A , multiple, stacked layers of conductive lines  72  are illustrated with topmost conductive lines  72  being the shortest and bottommost conductive lines  72  being the longest. Respective lengths of the conductive lines  72  may increase in a direction towards the underlying substrate. In this manner, a portion of each of the conductive lines  72  may be accessible from above the memory array  200 , and conductive contacts may be made to an exposed portion of each of the conductive lines  72 . 
     The memory array  200  further includes a plurality of conductive lines  106  (e.g., bit lines) and conductive lines  108  (e.g., source lines). The conductive lines  106  and  108  may each extend in a direction perpendicular to the conductive lines  72 . A dielectric material  98  is disposed between and isolates adjacent ones of the conductive lines  106  and the conductive lines  108 . In some embodiments, at least a portion of the dielectric material  98  is a low-hydrogen material formed using a hydrogen-comprising precursor that is introduced at a reduced flowrate. For example, at least portions of the dielectric material  98  (e.g., dielectric material  98 A) in physical contact with an oxide semiconductor (OS) layer  92  (described below) may have a relatively low hydrogen concentration, such as, a less than 3 atomic percent (at %). The low hydrogen concentration (e.g., in the above range) may reduce hydrogen diffusion into the OS layer  92 , thereby reducing defects and improving device stability. For example, by reducing hydrogen diffusion with an embodiment dielectric material  98 , the threshold voltage (V th ) curve of the TFTs  204  may shift in a positive bias direction, enhancing stability of the TFTs  204 . A relatively low hydrogen concentration can be achieved in the dielectric material  98  by, for example, reducing a flowrate of hydrogen-comprising precursor(s) used to deposit the dielectric material  98 . For example, in embodiments where the dielectric material  98  comprises silicon oxide, silicon nitride, or the like, the dielectric material  98  may be deposited by a process with a relatively low SiH 4  precursor flowrate to suppress H° or H +  diffusion into the dielectric material  98  and the OS layer  92 . 
     Pairs of the conductive lines  106  and  108  along with an intersecting conductive line  72  define boundaries of each memory cell  202 , and a dielectric material  102  is disposed between and isolates adjacent pairs of the conductive lines  106  and  108 . In some embodiments, the conductive lines  108  are electrically coupled to ground. Although  FIG.  1 A  illustrates a particular placement of the conductive lines  106  relative the conductive lines  108 , it should be appreciated that the placement of the conductive lines  106  and  108  may be flipped in other embodiments. 
     As discussed above, the memory array  200  may also include an oxide semiconductor (OS) layer  92 . The OS layer  92  may provide channel regions for the TFTs  204  of the memory cells  202 . For example, when an appropriate voltage (e.g., higher than a respective threshold voltage (V th ) of a corresponding TFT  204 ) is applied through a corresponding conductive line  72 , a region of the OS layer  92  that intersects the conductive line  72  may allow current to flow from the conductive lines  106  to the conductive lines  108  (e.g., in the direction indicated by arrow  206 ). The OS layer  92  may have a relatively low hydrogen concentration, such as in a range of about 10 20  to about 10 22  atoms per cubic centimeter as measured by Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) analysis. As a result, stability of the TFTs  204  may be improved compared to TFTs with OS layers having a higher concentration of hydrogen. 
     A memory film  90  is disposed between the conductive lines  72  and the OS layer  92 , and the memory film  90  may provide gate dielectrics for the TFTs  204 . In some embodiments, the memory film  90  comprises a ferroelectric material, such as a hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. Accordingly, the memory array  200  may also be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film  90  may be a multilayer structure comprising a layer of SiN x  between two SiO x  layers (e.g., an ONO structure), a different ferroelectric material, a different type of memory layer (e.g., capable of storing a bit), or the like. 
     In embodiments where the memory film  90  comprises a ferroelectric material, the memory film  90  may be polarized in one of two different directions, and the polarization direction may be changed by applying an appropriate voltage differential across the memory film  90  and generating an appropriate electric field. The polarization may be relatively localized (e.g., generally contained within each boundaries of the memory cells  202 ), and a continuous region of the memory film  90  may extend across a plurality of memory cells  202 . Depending on a polarization direction of a particular region of the memory film  90 , a threshold voltage of a corresponding TFT  204  varies, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory film  90  has a first electrical polarization direction, the corresponding TFT  204  may have a relatively low threshold voltage, and when the region of the memory film  90  has a second electrical polarization direction, the corresponding TFT  204  may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as the threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error prone) to read the digital value stored in the corresponding memory cell  202 . 
     To perform a write operation on a memory cell  202  in such embodiments, a write voltage is applied across a portion of the memory film  90  corresponding to the memory cell  202 . The write voltage can be applied, for example, by applying appropriate voltages to a corresponding conductive line  72  (e.g., the word line) and the corresponding conductive lines  106 / 108  (e.g., the bit line/source line). By applying the write voltage across the portion of the memory film  90 , a polarization direction of the region of the memory film  90  can be changed. As a result, the corresponding threshold voltage of the corresponding TFT  204  can also be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value can be stored in the memory cell  202 . Because the conductive lines  72  intersect the conductive lines  106  and  108 , individual memory cells  202  may be selected for the write operation. 
     To perform a read operation on the memory cell  202  in such embodiments, a read voltage (a voltage between the low and high threshold voltages) is applied to the corresponding conductive line  72  (e.g., the world line). Depending on the polarization direction of the corresponding region of the memory film  90 , the TFT  204  of the memory cell  202  may or may not be turned on. As a result, the conductive line  106  may or may not be discharged through the conductive line  108  (e.g., a source line that is coupled to ground), and the digital value stored in the memory cell  202  can be determined. Because the conductive lines  72  intersect the conductive lines  106  and  108 , individual memory cells  202  may be selected for the read operation. 
       FIG.  1 A  further illustrates reference cross-sections of the memory array  200  that are used in later figures. Cross-section B-B′ is along a longitudinal axis of conductive lines  72  and in a direction, for example, parallel to the direction of current flow of the TFTs  204 . Cross-section C-C′ is perpendicular to cross-section B-B′ and is parallel to a longitudinal axis of the conductive lines  72 . Cross-section C-C′ extends through the conductive lines  106 . Cross-section D-D′ is parallel to cross-section C-C′ and extends through the dielectric material  102 . Subsequent figures refer to these reference cross-sections for clarity. 
     In  FIG.  2   , a substrate  50  is provided. The substrate  50  may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate  50  may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  50  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. 
       FIG.  2    further illustrates circuits that may be formed over the substrate  50 . The circuits include active devices (e.g., transistors) at a top surface of the substrate  50 . The transistors may include gate dielectric layers  202  over top surfaces of the substrate  50  and gate electrodes  204  over the gate dielectric layers  202 . Source/drain regions  206  are disposed in the substrate  50  on opposite sides of the gate dielectric layers  202  and the gate electrodes  204 . Gate spacers  208  are formed along sidewalls of the gate dielectric layers  202  and separate the source/drain regions  206  from the gate electrodes  204  by appropriate lateral distances. In some embodiments, the transistors may be planar field effect transistors (FETs), fin field effect transistors (finFETs), nano-field effect transistors (nanoFETs), or the like. 
     A first ILD  210  surrounds and isolates the source/drain regions  206 , the gate dielectric layers  202 , and the gate electrodes  204  and a second ILD  212  is over the first ILD  210 . Source/drain contacts  214  extend through the second ILD  212  and the first ILD  210  and are electrically coupled to the source/drain regions  206  and gate contacts  216  extend through the second ILD  212  and are electrically coupled to the gate electrodes  204 . An interconnect structure  220 , including one or more stacked dielectric layers  224  and conductive features  222  formed in the one or more dielectric layers  224 , is over the second ILD  212 , the source/drain contacts  214 , and the gate contacts  216 . Although  FIG.  2    illustrates two stacked dielectric layers  224 , it should be appreciated that the interconnect structure  200  may include any number of dielectric layers  224  having conductive features  222  disposed therein. The interconnect structure  220  may be electrically connected to the gate contacts  216  and the source/drain contacts  214  to form functional circuits. In some embodiments, the functional circuits formed by the interconnect structure  220  may comprise logic circuits, memory circuits, sense amplifiers, controllers, input/output circuits, image sensor circuits, the like, or combinations thereof. Although  FIG.  2    discusses transistors formed over the substrate  50 , other active devices (e.g., diodes or the like) and/or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuits. 
     In  FIGS.  3 A and  3 B , a multi-layer stack  58  is formed over the structure of  FIG.  2   . The substrate  50 , the transistors, the ILDs, and the interconnect structure  120  may be omitted from subsequent drawings for the purposes of simplicity and clarity. Although the multi-layer stack  58  is illustrated as contacting the dielectric layers  224  of the interconnect structure  220 , any number of intermediate layers may be disposed between the substrate  50  and the multi-layer stack  58 . For example, one or more additional interconnect layers comprising conductive features in insulting layers (e.g., low-k dielectric layers) may be disposed between the substrate  50  and the multi-layer stack  58 . In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines for the active devices on the substrate  50  and/or the memory array  200  (see  FIGS.  1 A and  1 B ). 
     The multi-layer stack  58  includes alternating layers of conductive lines  72 A-D (collectively referred to as conductive layers  54 ) and dielectric layers  52 A-C (collectively referred to as dielectric layers  52 ). The conductive layers  54  may be patterned in subsequent steps to define the conductive lines  72  (e.g., word lines). The conductive layers  54  may comprise a conductive material, such as, copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and the dielectric layers  52  may comprise an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The conductive layers  54  and dielectric layers  52  may be each formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), or the like. Although  FIGS.  3 A and  3 B  illustrate a particular number of conductive layers  54  and dielectric layers  52 , other embodiments may include a different number of conductive layers  54  and dielectric layers  52 . 
       FIGS.  4  through  12 B  are views of intermediate stages in the manufacturing a staircase structure of the memory array  200 , in accordance with some embodiments.  FIGS.  4  through  11  and  12 B  are illustrated along reference cross-section B-B′ illustrated in  FIG.  1   .  FIG.  12 A  is illustrated in a three-dimensional view. 
     In  FIG.  4    a photoresist  56  is formed over the multi-layer stack  58 . As discussed above, the multi-layer stack  58  may comprise alternating layers of the conductive layers  54  (labeled  54 A,  54 B,  54 C, and  54 D) and the dielectric layers  52  (labeled  52 A,  52 B, and  52 C). The photoresist  56  can be formed by using a spin-on technique. 
     In  FIG.  5   , the photoresist  56  is patterned to expose the multi-layer stack  58  in regions  60  while masking remaining portions of the multi-layer stack  58 . For example, a topmost layer of the multi-layer stack  58  (e.g., conductive layer  54 D) may be exposed in the regions  60 . The photoresist  56  may be patterned using acceptable photolithography techniques 
     In  FIG.  6   , the exposed portions of the multi-layer stack  58  in the regions  60  are etched using the photoresist  56  as a mask. The etching may be any acceptable etch process, such as by wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may remove portions of the conductive layer  54 D and dielectric layer  52 C in the regions  60  and define openings  61 . Because the conductive layer  54 D and the dielectric layer  52 C have different material compositions, etchants used to remove exposed portions of these layers may be different. In some embodiments, the dielectric layer  52 C acts as an etch stop layer while etching the conductive layer  54 D, and the conductive layer  54 C acts as an etch stop layer while etching dielectric layer  52 C. As a result, the portions of the conductive layer  54 E and the conductive layer  54 D may be selectively removed without removing remaining layers of the multi-layer stack  58 , and the openings  61  may be extended to a desired depth. Alternatively, a timed etch processes may be used to stop the etching of the openings  61  after the openings  61  reach a desired depth. In the resulting structure, the conductive layer  54 C is exposed in the regions  60 . 
     In  FIG.  7   , the photoresist  56  is trimmed to expose additional portions of the multi-layer stack  58 . The photoresist can be trimmed using acceptable photolithography techniques. As a result of the trimming, a width of the photoresist  56  is reduced, and portions the multi-layer stack  58  in regions  60  and  62  may be exposed. For example, a top surface of the conductive layer  54 C may be exposed in the regions  60 , and a top surface of the conductive layer  54 D may be exposed in the regions  62 . 
     In  FIG.  8   , portions of the conductive layer  54 D, the dielectric layer  52 C, the conductive layer  54 C, and the dielectric layer  52 B in the regions  60  and  62  are removed by acceptable etching processes using the photoresist  56  as a mask. The etching may be any acceptable etch process, such as by wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings  61  further into the multi-layer stack  58 . Because the conductive layers  54 D/ 54 C and the dielectric layers  52 C/ 52 B have different material compositions, etchants used to remove exposed portions of these layers may be different. In some embodiments, the dielectric layer  52 C acts as an etch stop layer while etching the conductive layer  54 D; the conductive layer  54 C acts as an etch stop layer while etching dielectric layer  52 C; the dielectric layer  52 B acts as an etch stop layer while etching the conductive layer  54 C; and the conductive layer  54 B acts as an etch stop layer while etching the dielectric layer  52 B. As a result, portions of the conductive layers  54 D/ 54 C and the dielectric layer  52 C/ 52 B may be selectively removed without removing remaining layers of the multi-layer stack  58 , and the openings  61  may be extended to a desired depth. Further, during the etching processes, unetched portions of the conductive layers  54  and dielectric layers  52  act as a mask for underlying layers, and as a result a previous pattern of the conductive layer  54 D and dielectric layer  52 C (see  FIG.  7   ) may be transferred to the underlying conductive layer  54 C and dielectric layer  52 B. In the resulting structure, the conductive layer  54 B is exposed in the regions  60 , and the conductive layer  54 C is exposed in the regions  62 . 
     In  FIG.  9   , the photoresist  56  is trimmed to expose additional portions of the multi-layer stack  58 . The photoresist can be trimmed using acceptable photolithography techniques. As a result of the trimming, a width of the photoresist  56  is reduced, and portions the multi-layer stack  58  in regions  60 ,  62 , and  64  may be exposed. For example, a top surface of the conductive layer  54 B may be exposed in the regions  60 ; a top surface of the conductive layer  54 C may be exposed in the regions  62 ; and a top surface of the conductive layer  542 D may be exposed in the regions  64 . 
     In  FIG.  10   , portions of the conductive layers  54 D,  54 C, and  54 B in the regions  60 ,  62 , and  64  are removed by acceptable etching processes using the photoresist  56  as a mask. The etching may be any acceptable etch process, such as by wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings  61  further into the multi-layer stack  58 . In some embodiments, the dielectric layer  52 C acts as an etch stop layer while etching the conductive layer  54 D; the dielectric layer  52 B acts as an etch stop layer while etching the conductive layer  54 C; and the dielectric layer  52 A acts as an etch stop layer etching the conductive layer  54 B. As a result, portions of the conductive layers  54 D,  54 C, and  54 B may be selectively removed without removing remaining layers of the multi-layer stack  58 , and the openings  61  may be extended to a desired depth. Further, during the etching processes, each of the dielectric layers  52  act as a mask for underlying layers, and as a result a previous pattern of the dielectric layers  52 C/ 52 B (see  FIG.  9   ) may be transferred to the underlying conductive layers  54 C/ 54 B. In the resulting structure, the dielectric layer  52 A is exposed in the regions  60 ; the dielectric layer  52 B is exposed in the regions  62 ; and the dielectric layer  52 C is exposed in the regions  64 . 
     In  FIG.  11   , the photoresist  56  may be removed, such as by an acceptable ashing or wet strip process. Thus, a staircase structure  68  is formed. The staircase structure comprises a stack of alternating ones of the conductive layers  54  and the dielectric layers  52 . Lower conductive layers  54  are wider and extend laterally past upper conductive layers  54 , and a width of each of the conductive layers  54  increases in a direction towards the substrate  50 . For example, the conductive layer  54 A may longer than the conductive layer  54 B; the conductive layer  54 B may be longer than the conductive layer  54 C; and the conductive layer  54 C may be longer than the conductive layer  54 D. As a result, conductive contacts can be made from above the staircase structure  68  to each of the conductive layers  54  in subsequent processing steps. 
     In  FIG.  12   , an inter-metal dielectric (IMD)  70  is deposited over the multi-layer stack  58 . The IMD  70  may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. The IMD  70  extends along sidewalls of the conductive layers  54  as well as sidewalls of the dielectric layers  52 . Further, the IMD  70  may contact top surfaces of each of the dielectric layers  52 . 
     As further illustrated in  FIG.  12   , a removal process is then applied to the IMD  70  to remove excess dielectric material over the multi-layer stack  58 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the multi-layer stack  58  such that top surfaces of the multi-layer stack  58  and IMD  70  are level after the planarization process is complete. 
       FIGS.  13  through  17 B  are views of intermediate stages in the manufacturing of the memory array  200 , in accordance with some embodiments. In  FIGS.  13  through  17 B  the multi-layer stack  58  is formed and trenches are formed in the multi-layer stack  58 , thereby defining the conductive lines  72 . The conductive lines  72  may correspond to word lines in the memory array  200 , and the conductive lines  72  may further provide gate electrodes for the resulting TFTs of the memory array  200 .  FIG.  17 A  is illustrated in a three-dimensional view.  FIGS.  13  through  16  and  17 B  are illustrated along reference cross-section C-C′ illustrated in  FIG.  1 A . 
     In  FIG.  13   , a hard mask  80  and a photoresist  82  are deposited over the multi-layer stack  58 . The hard mask layer  80  may include, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The photoresist  82  can be formed by using a spin-on technique, for example. 
     In  FIG.  14   , the photoresist  82  is patterned to form trenches  86 . The photoresists can be patterned using acceptable photolithography techniques. For example, the photoresist  82  be exposed to light for patterning. After the exposure process, the photoresist  82  may be developed to remove exposed or unexposed portions of the photo resist depending on whether a negative or positive resist is used, thereby defining a patterning of the form trenches  86 . 
     In  FIG.  15   , a pattern of the photoresist  82  is transferred to the hard mask  84  using an acceptable etching process, such as by wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Thus, trenches  86  are formed extending through the hard mask  84 . The photoresist  82  may be removed by an ashing process, for example. 
     In  FIG.  16   , a pattern of the hard mask  84  is transferred to the multi-layer stack  58  using one or more acceptable etching processes, such as by wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching processes may be anisotropic. Thus, trenches  86  extended through the multi-layer stack  58 , and the conductive lines  72  (e.g., word lines) are formed from the conductive layers  54 . By etching trenches  86  through the conductive layers  54 , adjacent conductive lines  72  can be separated from each other. Subsequently, in  FIGS.  17 A and  17 B , the hard mask  84  may then be removed by an acceptable process, such as a wet etching process, a dry etching process, a planarization process, combinations thereof, or the like. Due to the staircase shape of the multi-layered stack  58  (see e.g.,  FIG.  12   ), the conductive lines  72  may have varying lengths that increase in a direction towards the substrate  50 . For example, the conductive lines  72 A may be longer than the conductive lines  72 B; the conductive lines  72 B may be longer than the conductive lines  72 C; and the conductive lines  72 C may be longer than the conductive lines  72 D. 
       FIGS.  18 A through  23 C  illustrate forming and patterning channel regions for the TFTs  204  (see  FIG.  1 A ) in the trenches  86 .  FIGS.  18 A,  18 A, and  23 A  are illustrated in a three-dimensional view. In  FIGS.  18 B,  19 B,  20 ,  21 ,  22 A,  22 B, and  23 B  cross-sectional views are provided along line C-C′ of  FIG.  1 A .  FIG.  23 C  illustrates a corresponding top-down view of the TFT structure. 
     In  FIGS.  18 A and  18 B , a memory film  90  is conformally deposited in the trenches  86 . The memory film  90  may have a material that is capable of storing a bit, such as material capable of switching between two different polarization directions by applying an appropriate voltage differential across the memory film  90 . For example, the polarization of the memory film  90  may change due to an electric field resulting from applying the voltage differential. 
     For example, the memory film  90  may be a high-k dielectric material, such as a hafnium (Hf) based dielectric material, or the like. In some embodiments, the memory film  90  comprises a ferroelectric material, such as, hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. In other embodiments, the memory  90  may be a multilayer structure comprising a layer of SiN x  between two SiO x  layers (e.g., an ONO structure). In still other embodiments, the memory film  90  may comprise a different ferroelectric material or a different type of memory material. The memory film  90  may be deposited by CVD, PVD, ALD, PECVD, or the like to extend along sidewalls and a bottom surface of the trenches  86 . After the memory film  90  is deposited, an annealing step (e.g., at a temperature range of about 300° C. to about 600° C.) in may be performed to achieve a desired crystalline phase, improve film quality, and reduce film-related defects/impurities for the memory film  90 . In some embodiments, the annealing step may further be below 400° C. to meet a BEOL thermal budget and reduce defects that may result in other features from high-temperature annealing processes. 
     In  FIGS.  19 A and  19 B , the OS layer  92  is conformally deposited in the trenches  86  over the memory film  90 . The OS layer  92  comprises a material suitable for providing a channel region for a TFT (e.g., TFTs  204 , see  FIG.  1 A ). In some embodiments, the OS layer  92  comprises an indium-comprising material, such as In x Ga y Zn z MO, where M may be Ti, Al, Ag, Si, Sn, or the like. X, Y, and Z may each be any value between 0 and 1. In other embodiments, a different semiconductor material may be used for the OS layer  92 . The OS layer  92  may be deposited by CVD, PVD, ALD, PECVD, or the like. The OS layer  92  may extend along sidewalls and a bottom surface of the trenches  86  over the FE layer  90 . After the OS layer  92  is deposited, an annealing step (e.g., at a temperature range of about 300° C. to about 450° C. or in a range of about 300° C. to about 400° C.) in oxygen-related ambient may be performed to activate the charge carriers of the OS layer  92 . 
     In  FIG.  20   , a dielectric material  98 A is deposited on sidewalls and a bottom surface of the trenches  86  and over the OS layer  92 . The dielectric material  98 A may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. In some embodiments, depositing the dielectric material  98 A may comprise reducing a flow of a hydrogen-comprising precursor so that the dielectric material  98 A is formed with a relatively low hydrogen concentration. For example, in embodiments where the dielectric material  98 A is a silicon-comprising insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or the like), a first hydrogen-comprising precursor (e.g., silane (SiH 4 ), Tetraethyl Silicate (TEOS), or the like) and a second hydrogen-free precursor may be simultaneously supplied during the deposition process. Because the first hydrogen-comprising precursor is used. The second hydrogen-free precursor may be, for example, N 2 O when the dielectric material  98 A comprises silicon oxide, and the second hydrogen-free precursor may be, for example, NH 3  when the dielectric material  98 A comprises silicon nitride. A flowrate of the first hydrogen-comping precursor is used, hydrogen ions (e.g., H + ) and/or hydrogen species (H°) may diffuse into OS layer  92  through the dielectric material  98 A, causing instability in the resulting transistor. Accordingly, various embodiments improve transistor stability by reducing a flowrate of the first hydrogen-comprising precursor. For example, a ratio of a flowrate of the second hydrogen-free precursor to a flowrate of the first hydrogen-comprising precursor may be at least 60. It has been observed that maintaining a precursor flowrate in the above ratio, hydrogen diffusion into the OS layer  92  may be reduced to a desired level and device stability may be improved. 
     In some embodiments, a hydrogen concentration of the OS layer  92  after the dielectric material  98 A is deposited may be in a range of about 10 20  atoms per cubic centimeter to about 10 22  atoms per cubic centimeter as measured by Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS).  FIG.  32 A  illustrates a graph  300  of hydrogen concentrations (e.g., curve  302 ) in the OS layer  92  and the dielectric material  98 A according to some embodiments. In graph  300 , the x-axis indicates sputtering time, which corresponds to a detection time (e.g., distance) during the ToF-SIMs analysis. By maintaining a hydrogen concentration of the OS layer  92  in this range, a threshold voltage characteristic curve of the resulting transistor  204  may shift in a positive bias direction, enhancing stability of the transistor. For example,  FIG.  32 B  illustrates a graph  304  depicting a threshold voltage characteristic curve  306  of a first transistor and a threshold voltage characteristic curve  308  of a second transistor. The first transistor (e.g., corresponding to curve  306 ) has a channel region (e.g., OS layer) with a hydrogen concentration over the above range, and the second transistor (e.g., corresponding to curve  308 ) has a channel region with a hydrogen concentration in the above range. Arrow  310  indicates the positive bias direction shift of the threshold voltage characteristic curve  308  compared to the threshold voltage characteristic curve  306 . 
     As a result of embodiment deposition processes, a hydrogen concentration in the dielectric material  98 A may be relatively low. For example, a hydrogen concentration of the dielectric material  98 A may be greater than 0 and less than 5 at % when the dielectric material  98 A comprises silicon oxide (e.g., SiO x ). As another example, an overall hydrogen concentration of the dielectric material  98 A may be greater than 0 and less than 10 at % when the dielectric material  98 A comprises silicon nitride (e.g., SiN x ). An overall hydrogen concentration at an interface  96  between the OS layer  92  and the dielectric material  98 A may be less than about 3 at %. Maintaining hydrogen concentrations of the dielectric material  98 A within these ranges may achieve advantages, such as reduced diffusion into the OS layer  92  and improved transistor stability. 
     In  FIG.  21   , bottom portions of the dielectric material  98 A in the trenches  86  are removed using a combination of photolithography and etching, for example. The etching may be any acceptable etch process, such as by wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. 
     Subsequently, as also illustrated by  FIG.  21   , the dielectric material  98 A may be used as an etch mask to etch through a bottom portion of the OS layer  92  in the trenches  86 . The etching may be any acceptable etch process, such as by wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Etching the OS layer  92  may expose portions of the memory film  90  on a bottom surface of the trenches  86 . Thus, portions of the OS layer  92  on opposing sidewalls of the trenches  86  may be separated from each other, which improves isolation between the memory cells  202  of the memory array  200  (see  FIG.  1 A ). 
     In  FIGS.  22 A and  22 B , an additional dielectric material  98 B or dielectric material  98 C may be deposited to fill remaining portions of the trenches  86 . In the embodiment of  FIG.  22 A , the dielectric material  98 B may have a same material composition and be formed using a like process as the dielectric material  98 A. For example, the dielectric material  98 B may be formed using a deposition process with a relatively low flowrate for a hydrogen comprising precursor. In some embodiments the dielectric material  98 B may be formed with a deposition process where a ratio of a flowrate of a hydrogen-free precursor (e.g., N 2 O) to a flowrate of a hydrogen-comprising precursor (e.g., SiH 4 ) is at least 60. In some embodiments, a respective ratio of the flowrate of the hydrogen-free precursor to the flowrate of the hydrogen-comprising precursor may be the same for depositing the dielectric material  98 B as depositing the dielectric material  98 A. As a result, a hydrogen concentration of the dielectric material  98 B is relatively low. For example, an overall hydrogen concentration of the dielectric material  98 B may be greater than 0 and less than 5 at % when the dielectric material  98 B comprises silicon oxide (e.g., SiO x ). As another example, an overall hydrogen concentration of the dielectric material  98 B may be greater than 0 and less than 10 at % when the dielectric material  98 B comprises silicon nitride (e.g., SiN x ). 
       FIG.  22 B  illustrates an alternate embodiment memory array  200 ′ where a dielectric material  98 C is deposited to fill remaining portions of the trenches  86  instead of the dielectric material  98 B. The dielectric material  98 C may have a different material composition and be formed using a different process than the dielectric material  98 A. The dielectric material  98 C may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. However, depositing the dielectric material  98 C may comprise increasing a flow of a hydrogen-comprising precursor compared to the dielectric material  98 A. As a result, the dielectric material  98 C is formed with a relatively high hydrogen concentration. For example, in embodiments where the dielectric material  98 C is a silicon-comprising insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or the like), a third hydrogen-comprising precursor (e.g., SiH 4 , TEOS, or the like) and a fourth hydrogen-free precursor may be simultaneously flowed during the deposition process. The fourth hydrogen-free precursor may be, for example, N 2 O when the dielectric material  98 C comprises silicon oxide, and the fourth hydrogen-free precursor may be, for example, NH 3  when the dielectric material  98 C comprises silicon nitride. For example, a ratio of a flowrate of the second hydrogen-free precursor to a flowrate of the first hydrogen-comprising precursor may greater  60 , such as up to 70. It has been observed that maintaining a precursor flowrate in the above ratio, a hydrogen concentration of the dielectric material  98 C may be greater than a hydrogen concentration of the dielectric material  98 A. For example, an overall hydrogen concentration of the dielectric material  98 C may be in a range of about 1×10 21  atoms/cm 3  to 1×10 22  atoms/cm 3  when the dielectric material  98 C comprises silicon oxide (e.g., SiO x ). As another example, an overall hydrogen concentration of the dielectric material  98 C may be greater than 1×10 22  atoms/cm 3  when the dielectric material  98 C comprises silicon nitride (e.g., SiN x ). Because the relatively low-hydrogen concentration dielectric material  98 A separates the relatively high-hydrogen concentration dielectric material  98 C and the OS layer  92 , a high hydrogen concentration in the dielectric material  98 C may not significantly degrade device performance in the resulting transistor, and the benefits described above may still be achieved. 
     Subsequent figures illustrate further processing based on the embodiment of  FIG.  22 A  (e.g., where the dielectric material  98 B and the dielectric material  98 A have a same material composition) for ease of illustration. The dielectric material  98 B and the dielectric material  98 A may be referred to collectively as the dielectric material  98  herein after. It should be understood that similar processing may be applied to the embodiment of  FIG.  22 B  (e.g., wherein the dielectric material  98 C and the dielectric material  98 A have different material compositions).  FIGS.  33 A through  33 C  illustrate the memory array  200 ′ according to the embodiment of  FIG.  22 B . 
     In  FIGS.  23 A through  23 C , a removal process is then applied to the dielectric material  98 , the OS layer  92 , and the memory film  90  to remove excess material over the multi-layer stack  58 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the multi-layer stack  58  such that top surface of the multi-layer stack  58  is level after the planarization process is complete.  FIG.  23 C  illustrates a corresponding top-down view of the structure illustrated in  FIG.  23 A . 
       FIGS.  24 A through  27 C  illustrate intermediate steps of manufacturing conductive lines  106  and  108  (e.g., source lines and bit lines) in the memory array  200 . The conductive lines  106  and  108  may extend along a direction perpendicular to the conductive lines  72  such that individual cells of the memory array  200  may be selected for read and write operations. In  FIGS.  24 A through  27 C , figures ending in “A” illustrate a 3D view; figures ending in “B” illustrate a top down view, and figures ending in “C” illustrate a corresponding cross-sectional view parallel to line C-C′ of  FIG.  1 A . 
     In  FIGS.  24 A,  24 B, and  24 C , trenches  100  are patterned through the OS layer  92  and the dielectric material  98  (including the dielectric material  98 A and the dielectric material  98 B).  FIG.  24 C  illustrates a cross-section view of line C-C′ in  FIG.  24 B . Patterning the trenches  100  may be performed through a combination of photolithography and etching, for example. The trenches  100  may be disposed between opposing sidewalls of the memory film  90 , and the trenches  100  may physically separate adjacent stacks of memory cells in the memory array  200  (see  FIG.  1 A ). 
     In  FIGS.  25 A,  25 B, and  25 C , a dielectric material  102  is deposited in and fills the trenches  100 .  FIG.  25 C  illustrates a cross-sectional view of line C-C′ in  FIG.  25 B . The dielectric layer  102  may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric layer  102  may extend along sidewalls and a bottom surface of the trenches  86  over the OS layer  92 . After deposition, a planarization process (e.g., a CMP, etch back, or the like) may be performed to remove excess portions of the dielectric material  102 . In the resulting structure, top surfaces of the multi-layer stack  58 , the memory film  90 , the OS layer  92 , and the dielectric material  102  may be substantially level (e.g., within process variations). In some embodiments, materials of the dielectric materials  98  and  102  may be selected so that they may be etched selectively relative each other. For example, in some embodiments, the dielectric material  98  is an oxide and the dielectric material  102  is a nitride. In some embodiments, the dielectric material  98  is a nitride and the dielectric material  102  is an oxide. Other materials are also possible. 
     In  FIGS.  26 A,  26 B, and  26 C , trenches  104  are patterned for the conductive lines  106  and  108 .  FIG.  26 C  illustrates a cross-sectional view of line C-C′ in  FIG.  26 B . The trenches  104  are patterned by patterning the dielectric material  98  (including the dielectric material  98 A and the dielectric material  98 C) using a combination of photolithography and etching, for example. 
     For example, a photoresist  120  may be deposited over the multi-layer stack  58 , the dielectric material  98 , the dielectric material  102 , the OS layer  92 , and the memory film  90 . The photoresist  118  can be formed by using a spin-on technique, for example. The photoresist  120  is patterned to define openings  122 . Each of the openings  122  may overlap a corresponding region of the dielectric material  102 , and each of the openings  122  may further partially expose two separate regions of the dielectric material  98 . For example, each opening  120  may expose a region of the dielectric material  102 ; partially expose a first region of the dielectric material  98 ; and partially expose a second region of the dielectric material  98  that is separated from the first region of the dielectric material  98  by the region of the dielectric material  102 . In this way, each of the openings  122  may define a pattern of a conductive line  106  and an adjacent conductive line  108  that are separated by the dielectric material  102 . The photoresists can be patterned using acceptable photolithography techniques. For example, the photoresist  120  be exposed to light for patterning. After the exposure process, the photoresist  120  may be developed to remove exposed or unexposed portions of the photoresist depending on whether a negative or positive resist is used, thereby defining a patterning of the form openings  122 . 
     Subsequently, portions of the dielectric material  98  exposed by the openings  122  may be removed by etching, for example. The etching may be any acceptable etch process, such as by wet or dry etching, a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching process may use an etchant that etches the dielectric material  98  without significantly etching the dielectric material  102 . As a result, even though the openings  122  expose the dielectric material  102 , the dielectric material  102  may not be significantly removed. A pattern of the trenches  104  may correspond to the conductive lines  106  and  108  (see  FIGS.  27 A,  27 B, and  27 C ). For example, a portion of the dielectric material  98  may remain between each pair of the trenches  104 , and the dielectric material  102  may be disposed between adjacent pairs of the trenches  104 . After the trenches  104  are patterned, the photoresist  120  may be removed by ashing, for example. 
     In  FIGS.  27 A,  27 B, and  27 C  the trenches  104  are filled with a conductive material to form the conductive lines  106  and  108 .  FIG.  27 C  illustrates a cross-sectional view of line C-C′ in  FIG.  27 B . The conductive lines  106  and  108  may each comprise a conductive material, such as, copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, which may be each formed using, for example, CVD, ALD, PVD, PECVD, or the like. After the conductive lines  106  and  108  are deposited, a planarization (e.g., a CMP, etch back, or the like) may be performed to remove excess portions of the conductive material, thereby forming the conductive lines  106  and  108 . In the resulting structure, top surfaces of the multi-layer stack  58 , the memory film  90 , the OS layer  92 , the conductive lines  106 , and the conductive lines  108  may be substantially level (e.g., within process variations). The conductive lines  106  may correspond to bit lines in the memory array, and the conductive lines  108  may correspond to source lines in the memory array  200 . Although  FIG.  27 C  illustrates a cross-sectional view that only shows the conductive lines  106 , a cross-sectional view of the conductive lines  108  may be similar. 
     Thus stacked TFTs  204  may be formed in the memory array  200 . Each TFT  204  comprises a gate electrode (e.g., a portion of a corresponding conductive line  72 ), a gate dielectric (e.g., a portion of a corresponding memory film  90 ), a channel region (e.g., a portion of a corresponding OS layer  92 ), and source and drain electrodes (e.g., portions of corresponding conductive lines  106  and  108 ). The dielectric material  102  isolates adjacent TFTs  204  in a same column and at a same vertical level. The TFTs  204  may be disposed in an array of vertically stacked rows and columns. 
     In  FIGS.  28 A,  28 B,  28 C, and  28 D , contacts  110  are made to the conductive lines  72 , the conductive lines  106 , and the conductive lines  108 .  FIG.  28 A  illustrates a perspective view of the memory array  200 ;  FIG.  28 B  illustrates a top-down view of the memory array  200 ; and  FIG.  28 C  illustrates a cross-sectional view of the device and underlying substrate alone the line  30 C′- 30 C′ of  FIG.  28 A ; and  FIG.  28 D  illustrates a cross-sectional view of the device along line B-B′ of  FIG.  1 A . In some embodiments, the staircase shape of the conductive lines  72  may provide a surface on each of the conductive lines  72  for the conductive contacts  110  to land on. Forming the contacts  110  may include patterning openings in the IMD  70  and the dielectric layers  52  to expose portions of the conductive layers  54  using a combination of photolithography and etching, for example. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the IMD  70 . The remaining liner and conductive material form the contacts  110  in the openings. 
     As also illustrated by the perspective view of  FIG.  28 A , conductive contacts  112  and  114  may also be made to the conductive lines  106  and the conductive lines  108 , respectively. The conductive contacts  110 ,  112 , and  114  may be electrically connected to conductive lines  116 A,  116 B, and  116 C, respectively, which connect the memory array to an underlying/overlying circuitry (e.g., control circuitry) and/or signal, power, and ground lines in the semiconductor die. For example, conductive vias  118  may extend through the IMD  70  to electrically connect conductive lines  116 C to the underlying circuitry of the interconnect structure  220  and the active devices on the substrate  50  as illustrated by  FIG.  28 C . Other conductive vias may be formed through the IMD  70  to electrically connect the conductive lines  116 A and  116 B to the underlying circuitry of the interconnect structure  220 . In alternate embodiments, routing and/or power lines to and from the memory array may be provided by an interconnect structure formed over the memory array  200  in addition to or in lieu of the interconnect structure  220 . Accordingly, the memory array  200  may be completed. 
     Although the embodiments of  FIGS.  2  through  28 B  illustrate a particular pattern for the conductive lines  106  and  108 , other configurations are also possible. For example, in these embodiments, the conductive lines  106  and  108  have a staggered pattern. In some embodiments, the conductive lines  106  and  108  in a same row of the array are all aligned with each other.  FIG.  29    illustrates a top-down view, and  FIG.  30    illustrates a cross-sectional view alone line C-C′ of  FIG.  28   .  FIG.  31    illustrates a cross-sectional view alone line D-D′ of  FIG.  29   . In  FIGS.  29 ,  30 , and  31   , like reference numerals indicate like elements formed by like processes as the elements of  FIGS.  2  through  28 B . 
       FIGS.  33 A,  33 B,  33 C, and  33 D  illustrate memory array  200 ′ according to an alternate embodiment illustrated and described above with respect to  FIG.  22 B .  FIG.  33 A  illustrates a perspective view of the memory array  200 ;  FIG.  33 B  illustrates a top-down view of the memory array  200 ; and  FIG.  33 C  illustrates a cross-sectional view of the device and underlying substrate alone the line  30 C′- 30 C′ of  FIG.  33 A ; and  FIG.  33 D  illustrates a cross-sectional view of the device along line B-B′ of  FIG.  1 A . The memory array  200 ′ may be similar to the memory array  200  where like reference numerals indicate like elements formed using like processes. However, the dielectric material  98 B is replaced with a dielectric material  98 C, and the dielectric material  98 C has a different material composition than the dielectric material  98 A. For example, as described above, a hydrogen concentration of the dielectric material  98 C may be higher than the dielectric material  98 A. This can be achieved, for example, by increasing a flowrate of a hydrogen-comprising precursor while depositing the dielectric material  98 C compared to depositing the dielectric material  98 A. 
     Various embodiments provide a 3D memory array with vertically stacked memory cells. The memory cells each comprise a TFT with a memory film, gate dielectric material and an oxide semiconductor channel region. The TFT comprises source/drain electrodes, which are also source lines and bits lines in the memory array. A dielectric material is disposed between and isolates adjacent ones of the source/drain electrodes. In some embodiments, at least a portion of the dielectric material is a low-hydrogen material formed using a hydrogen-comprising precursor that is introduced at a reduced flowrate. For example, at least portions of the dielectric material (e.g., layer) in physical contact with channel region of the TFT may have a relatively low hydrogen concentration, such as, a less than 3 at %. The low hydrogen concentration (e.g., in the above range) may reduce hydrogen diffusion into the channel region, thereby reducing defects and improving stability. A relatively low hydrogen concentration can be achieved in the dielectric material by, for example, reducing a flowrate of a hydrogen-comprising precursor used to deposit the dielectric material. 
     In some embodiments, a memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %). Optionally, in some embodiments, the dielectric material comprises: a first dielectric material contacting the OS layer, the first dielectric material extending continuously from the source line to the bit line; and a second dielectric material on an opposing side of the first dielectric material as the OS layer, the second dielectric material extending continuously from the source line to the bit line, a hydrogen concentration of the second dielectric material being greater than a hydrogen concentration of the first dielectric material. Optionally, in some embodiments, the dielectric material comprises silicon oxide, and an overall hydrogen concentration of the dielectric material is greater than 0 at % and less than 5 at %. Optionally, in some embodiments, the dielectric material comprises silicon nitride, and an overall hydrogen concentration of the dielectric material is greater than 0 at % and less than 10 at %. Optionally, in some embodiments, the OS layer comprises hydrogen. Optionally, in some embodiments, a hydrogen concentration of the OS layer is in a range of 10 20  atoms per cubic centimeter to 10 22  atoms per cubic centimeter. Optionally, in some embodiments, a longitudinal axis of the word line extends parallel to a major surface of a semiconductor substrate, a longitudinal axis of the source line extends perpendicular to the major surface of the semiconductor substrate, and a longitudinal axis of the bit line extends perpendicular to the major surface of the semiconductor substrate. 
     In some embodiments, a device includes: a semiconductor substrate; a first memory cell over the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises: a gate electrode comprising a portion of a first word line; a first portion of a ferroelectric material, the first portion of the ferroelectric material being on a sidewall of the first word line; and a first channel region on a sidewall of the ferroelectric material, the first channel region comprising hydrogen, and a hydrogen concentration of the first channel region being in a range of 10 20  atoms per cubic centimeter to 10 22  atoms per cubic centimeter; a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor; a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor; a first dielectric material separating the source line and the bit line, wherein the first dielectric material physically contacts the first channel region; and a second memory cell over the first memory cell. Optionally, in some embodiments, the second memory cell comprising a second thin film transistor, wherein a second portion of the source line provides a first source/drain electrode for the second thin film transistor, and wherein a second portion of the bit line provides a second source/drain electrode for the second thin film transistor. Optionally, in some embodiments, the device further includes a second word line under the first word line, wherein a gate electrode of the second thin film transistor comprises a portion of the second word line, and wherein the first word line is longer than the second word line. Optionally, in some embodiments, a hydrogen concentration at an interface between the first dielectric material and the first channel region is less than 3 atomic percent. Optionally, in some embodiments, the device further includes a second dielectric material separating the source line and the bit line, the second dielectric material being separated from the first channel region by the first dielectric material, and the first dielectric material has a different material composition than the second dielectric material. Optionally, in some embodiments, a hydrogen concentration of the second dielectric material is greater than a hydrogen concentration of the first dielectric material. 
     In some embodiments, a method includes patterning a first trench extending through a first conductive line; depositing a memory film along sidewalls and a bottom surface of the first trench; depositing an oxide semiconductor (OS) layer over the memory film, the OS layer extending along the sidewalls and the bottom surface of the first trench; depositing a first dielectric material over and contacting the OS layer, wherein depositing the first dielectric material comprises simultaneously supplying a first hydrogen-comprising precursor at a first flowrate and a second hydrogen-free precursor at a second flowrate, and wherein a ratio of the second flowrate of the second hydrogen-free precursor to the first flowrate of the first hydrogen-comprising precursor is at least 60; and depositing a second dielectric material over the first dielectric material to fill a remaining portion of the first trench. Optionally, in some embodiments, depositing the second dielectric material comprises simultaneously supplying a third hydrogen-comprising precursor at a third flowrate and a fourth hydrogen-free precursor at a fourth flowrate, and wherein a ratio of the fourth flowrate of the fourth hydrogen-free precursor to the third flowrate of the third hydrogen-comprising precursor is the same as a ratio of the second flowrate of the second hydrogen-free precursor to the first flowrate of the first hydrogen-comprising precursor. Optionally, in some embodiments depositing the second dielectric material comprises simultaneously supplying a third hydrogen-comprising precursor at a third flowrate and a fourth hydrogen-free precursor at a fourth flowrate, and wherein the third flowrate of the third hydrogen-comprising precursor is greater than the first flowrate of the first hydrogen-comprising precursor. Optionally, in some embodiments, the method further includes patterning a third trench in the first dielectric material and the second dielectric material; patterning a fourth trench in the first dielectric material and the second dielectric material; and filling the third trench and the fourth trench with a conductive material to define a source line and a bit line. Optionally, in some embodiments, the first hydrogen-comprising precursor is silane (SiH 4 ), and the second hydrogen-free precursor is N 2 O. Optionally, in some embodiments, after depositing the first dielectric material, a hydrogen concentration at an interface between the first dielectric material and the OS layer is 3 at % or less. Optionally, in some embodiments, depositing the first dielectric material comprises diffusing hydrogen into the OS layer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.