Patent Publication Number: US-2021193826-A1

Title: Power Device with Low Gate Charge and Low Figure of Merit

Description:
This application is a divisional of U.S. patent application Ser. No. 16/296,760, filed Mar. 8, 2019, application is hereby incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to a power device comprising a low Figure of Merit (“FOM”). 
     BACKGROUND 
     For VDMOS (Vertical, double-Diffused, Metal-Oxide, Semiconductor) devices used as power switches, gate charge Qg plays an important role for generating switching loss. In general, it is desirable to achieve the lowest gate charge Qg possible for maximum switching performance. The RQg FOM thus determines switching performance in terms of conduction and gate drive power loss, and is represented by the equation RQg FOM=(Rds(on)×Qg). As previously noted, FOM should be minimized. Current VDMOS has relatively high Qg and thus a high FOM, which results in power loss, especially for applications in which switching loss is dominant. 
     One method for evaluating MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) devices is by comparing the FOM or Figure of Merit. One simple FOM is the RQg FOM. In its simplest form, the RQg figure of merit includes gate charge (Qg) multiplied by the “on” resistance between the drain and source of the device (Rds(on)). The result of this multiplication generates the RQg FOM, which can then be used to compare devices or certain device technologies. In general, a lower RQg FOM corresponds to a lower switching loss. 
     Methods have been tried to reduce the Qg without significantly increasing Rds(on). One typical approach is to have planar “split gate” structure by removing the gate polysilicon on the top of a JFET (Junction Field-Effect Transistor) neck. In this case, gate to drain overlap is significantly reduced. While both Qg (gate charge) and Qgd (gate to drain charge) will both decrease but Rds(on) is increased. In addition, the “split gate” approach has a minimal impact on Qgs (gate to source charge), which is also important in determining device switching performance. 
     SUMMARY 
     A device comprises a cell, wherein each cell comprises a body comprising a main top surface and a main bottom surface; a gate on the main surface on the device having a first length; a gate isolation layer over the gate having a second length at least twice as long as the first length; a source contact in the device body proximate to the gate; a source metal layer over the gate isolation layer; and a drain on the main bottom surface of the cell. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1A  is a cross-sectional view of a Super Junction (“SJ”) VDMOS device according to the prior art; 
         FIG. 1B  is a cross-sectional view of the SJ VDMOS device of  FIG. 1A , including an indication of the vertical current flow within the device in an active mode of operation; 
         FIG. 2A  is a cross-sectional view of a SJ VDMOS device including an improved FOM according to an embodiment; 
         FIG. 2B  is a cross-sectional view of the SJ VDMOS device of  FIG. 2A , including an indication of the vertical current flow within the device in an active mode of operation; 
         FIG. 3  is a plan view of the device of  FIG. 1A  and  FIG. 1B ; 
         FIG. 4  is a plan view of the device of  FIG. 2A  and  FIG. 2B  arranged in a first configuration according to an embodiment; 
         FIG. 5  is a plan view of the device of  FIG. 2A  and  FIG. 2B  arranged in a second configuration according to an embodiment; 
         FIG. 6  is a table of simulation results for a plurality of boy SJ VDMOS devices comprising different polysilicon gate lengths according to embodiments; and 
         FIG. 7  is a table of simulation and measurement results for a plurality of 250V SJ VDMOS devices comprising different polysilicon gate lengths according to embodiments. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     According to embodiments, methods, transistor cells, and transistor devices comprising a plurality of transistor cells are described that are configured to reduce the Qg without significantly increasing Rds(on), thus improving FOM. By removing one of the two source contacts in a conventional SJ VDMOS device cell while maintaining the other device structures, the polysilicon gate length is significantly reduced and FOM is improved. Embodiment concepts can be adapted to other device types as well. For example, any vertical device having two symmetrical source contacts can modified as described herein. The device cells can be replicated in two or more configurations while maintaining the improvement in FOM according to embodiments. 
       FIG. 1A  is a cross-sectional view of an exemplary SJ VDMOS device cell  100  including a source metal region  102 , a gate insulation layer  104 , an insulated gate  106 , source contacts  108 A and  108 B, a body region including zones  110  and  114 , an interface  112  between zones  110  and  114 , and a drain contact  116 . Source metal region  102  can be formed of aluminum or other conductive materials. A dielectric layer such as silicon dioxide or other dielectric materials can be used for gate insulation layer  104 . Insulated gate  106  can comprise a polysilicon or an aluminum gate surrounded by a dielectric layer such as silicon dioxide or other dielectric materials. Source contacts  108 A and  108 B can include a diffused region in the body of the device cell  100 , for example an N+ type diffused region. Source contacts  108 A and  108 B can be diffused into another diffused region, for example, a P− base region for forming a channel region. Zones  110  can comprise P-type columns and zone  114  can comprise an N-type epitaxial region. Zones  110  and  114  will support reverse bias voltages when the device is in OFF state. Interface  112  comprises a PN junction between zones  110  and  114  where a depletion region is formed on each side of junction  112  when the device is in the OFF state. Drain contact  116  can be a metallized bottom surface of device cell  100 , such as aluminum or aluminum alloys. The body of device cell  100  can include an N− drift region in the epitaxial region over an N+ substrate. Zones  110  also include a P+ contact  103  that is shorted to the source metal region  102  as shown. 
       FIG. 1B  is a cross-sectional view of the SJ VDMOS device cell  100  of  FIG. 1A , including an indication of the vertical current flow  118 ,  120 , and  122  within the device in an active mode of operation. Not all of the reference numerals are replicated in  FIG. 1B  for simplicity in understanding the drawing figures. The main path  122  of the current flow through the body of device cell  100  splits into two equal branches, including current branch  118  that flows up to the main top surface of the device and across a first channel to the first source contact  108 A and current branch  120  that flows up to the main top surface of the device and across a second channel to the second source contact  108 B. Current branch  122  represents the total vertical current flow through the device, and current branches  118  and  120  each represent about half of the total vertical current flow through the device. 
     Thus, device cell  100  includes N+ source contacts  108 A and  108 B on both sides of the polysilicon gate  106 . Drain current flows to each N+ source contact through left channel and right channels during conduction. 
     It is known in the art that a plurality of device cells are replicated in a pattern of, for example, rows and columns and interconnected to complete an entire power device. 
       FIG. 2A  is a cross-sectional view of a SJ VDMOS device cell  200  including an improved FOM according to an embodiment including a source metal region  202 , a gate insulation layer  204 , a single insulated gate  206 , a single source contact  208 , a body region including zones  210  and  214 , an interface  212  between zones  210  and  214 , and a drain contact  216 . Source metal region  202  can comprise aluminum or other conductive materials. Gate insulation layer  204  can comprise a dielectric layer such as silicon dioxide or other dielectric materials. Insulated gate  206  can comprise a polysilicon or an aluminum gate surrounded by a dielectric layer such as silicon dioxide or other dielectric materials. Source contact  208  can comprise a diffused region in the body of the device cell  200 , for example an N+ diffused region. Source contact  208  can be diffused into another diffused region, for example, a P-base region for forming a channel region. Zones  210  can comprise P-type columns and zone  214  can comprise an N-type epitaxial region. Zones  210  and  214  will support reverse bias voltages when the device is in OFF state. Interface  212  comprises a PN junction between zones  210  and  214  where a depletion region is formed on each side of junction  212  when the device is in the OFF state. Drain contact  216  can be a metallized bottom surface of device cell  200 , such as aluminum or aluminum alloys. The body of device cell  200  can include an N− drift region in an epitaxial region over an N+ substrate. Zones  210  also include a P+ contact  203  that is shorted to the source metal region  202  as shown. 
     Note that the single insulated gate  206  and the single source contact  208  are asymmetrically arranged with respect to gate insulation layer  204 . In various embodiments, insulated gate  206  and source contact  208  each have lengths less than one-half that of the length of the gate insulation layer  204 . In some embodiments, insulated gate  206  and source contact  208  each have lengths less than one-third that of the length of the gate insulation layer  204 . In an embodiment, the length of the polysilicon gate  206  can be a minimum length, thus reducing the corresponding gate to drain overlap. 
       FIG. 2B  is a cross-sectional view of the SJ VDMOS device cell  200  of  FIG. 2A , including an indication of the vertical current flow  222 ,  218  within the device in an active mode of operation. Not all of the reference numerals are replicated in  FIG. 2B  for simplicity in understanding the drawing figures. The main path  222  of the current flow through the body of device cell  200  includes a single current branch  218  that flows up to the main top surface of the device and across a channel to the single source contact  208 . Current branches  222  and  218  thus represent the same total vertical current flow through the device. 
     In comparing device cell  200  with exemplary device cell  100 , gate charges Qg and Qgd are significantly reduced and a much lower FOM (Rds(on)×Qg) is realized. A slightly higher specific Rds(on) (Rds(on)×AA) is realized, where AA is the Active Area of the SJ VDMOS device. Comparing device cell  200  with prior art device cell boo, only half of the source contact length is used ( 208  vs  108 A and  108 B) and the single source contact  208  is asymmetrically located with respect to the gate insulation layer  204 . In addition, the length of polysilicon gate  206  is significantly reduced with respect to polysilicon gate  106 . For example, in an embodiment the length of polysilicon gate  206  can be less than one-half that of polysilicon gate  106 . In another embodiment the length of polysilicon gate  206  can be less than one-third that of polysilicon gate  106 . In another embodiment the length of polysilicon gate can be a minimum gate length based on critical dimensions of a given semiconductor manufacturing process. 
     Both device cells  100  and  200  have the same P+ contacts  103  and  203  that are shorted to the corresponding source metal regions  102  and  202  as previously described. Removing one of the N+ contacts and/or shrinking the gate polysilicon length in device cell  200  does not alter the source to drain overlap, which is corroborated below with respect to the simulation and measurement results shown in  FIGS. 6 and 7 . With respect to device cell  200 , the source metal coupling to the P+ contact  203  on the right hand side of the device cell is important even though no current flows in that side of the device cell. The voltage on the P+ contact  203  sets the voltage of top of zone  110  to ground when the device is in a reverse bias condition. If the P+ contact  203  is removed on that side, zone  110  would be electrically floating and the breakdown voltage of the device cell would be lower. 
       FIG. 3  is a plan view of the device cell  100  of  FIG. 1A  and  FIG. 1B . For simplicity only the outline of a cell including two device cells  100 A and  100 B is shown, where the first device cell  100 A includes a first source contact stripe  108 A, a second source contact stripe  108 B, and a polysilicon gate stripe  106  corresponding to the same features shown in  FIG. 1A  and  FIG. 1B . Gate stripe  106  has a first edge  109 A that overlaps an edge of source stripe  108 A and a second edge  109 B that overlaps an edge of source stripe  108 B. 
     The second device cell  100 B also includes a first source contact stripe  108 A, a second source contact stripe  108 B, and a polysilicon gate stripe  106  corresponding to the same features shown in  FIG. 1A  and  FIG. 1B . Gate stripe  106  of second device  100 B also has a first edge  109 A that overlaps an edge of source stripe  108 A and a second edge  109 B that overlaps an edge of source stripe  108 B. 
     The total cell pitch of both of the device cells  100 A and  100 B (“2×cell pitch”) is shown in  FIG. 3  and “L” is also shown, which is the length for the polysilicon gate for each device. 
       FIG. 4  is a plan view of the device of  FIG. 2A  and  FIG. 2B . For simplicity only the outline of a cell including two device cells  200 A and  200 B is shown, wherein the first device cell  200 A includes a single source contact stripe  208  and a polysilicon gate stripe  206  corresponding to the same features shown in  FIG. 2A  and  FIG. 2B . Gate stripe  206  has a first edge  209  that overlaps an edge of source stripe  208 . 
     The second device cell  200 B also includes a single source contact stripe  208  and a polysilicon gate stripe  206  corresponding to the same features shown in  FIG. 2A  and  FIG. 2B . Gate stripe  206  of second device cell  200 B also has a first edge  209  that overlaps an edge of source stripe  208 . 
     The total cell pitch of both device cells  200 A and  200 B (“2×cell pitch”) is shown in  FIG. 4  and “L′” is also shown, which is the length of the polysilicon gate for each device. The gate polysilicon length in the prior art device cells  100 A and  100 B of  FIG. 3  is “L”, wherein the gate polysilicon length of device  200  shown in  FIG. 4  is “L′”, wherein L′&lt;L in an embodiment. 
     Note that device cells  200 A and  200 B include “charge reduction stripes”  210  that are not associated with directing the vertical current flow of the device, and do not include either a source stripe  208  or a gate stripe  206 . A source implant is performed on both sides of the polysilicon gate in the prior art device, while only a single-sided source implant is performed in the devices shown in  FIGS. 2A, 2B, and 4  according to an embodiment. The “charge reduction stripe”  210  thus does not include the source implant. 
       FIG. 4  shows a cell layout for a power device wherein each cell comprises a source  208  and an overlapping polysilicon gate  206 . A charge reduction stripe  210  separates cell  200 A from the next cell  200 B, which also comprises a source  208  and an overlapping polysilicon gate  206  in the same order. 
       FIG. 5  shows a cell layout for a power device wherein each cell is “flipped” horizontally with respect to the adjacent cell. For example, cell  300 A comprises a polysilicon gate  306  including portion  309  overlapping a source  308 , and a charge reduction stripe  310 . Cell  300 A is separated from the next cell  300 B, which comprises a flipped configuration comprising, in order, a source  308  and an overlapping polysilicon gate  306  including overlap portion  309 , and a charge reduction stripe  310 . 
       FIG. 5  is a plan view of the device of  FIG. 2A  and  FIG. 2B  shown in an alternative layout configuration according to another embodiment. For simplicity only the outline of a cell including two devices  300 A and  300 B is shown, wherein the first device  300 A includes a single source contact stripe  308  and a polysilicon gate stripe  306  corresponding to the same features shown in  FIG. 2A  and  FIG. 2B . Gate stripe  306  has a first edge that overlaps an edge of source stripe  308 . Cell  300 A includes, in order from left to right, a gate stripe  306  followed by a source stripe  308 . 
     The second cell  300 B also includes a single source contact stripe  308  and a polysilicon gate stripe  306  corresponding to the same features shown in  FIG. 2A  and  FIG. 2B . Gate stripe  306  of second cell  200 B also has a first edge that overlaps an edge of source stripe  308 . Cell  300 B includes, in order from left to right, a source stripe  308  followed by a gate stripe  306  in a flipped configuration with respect to cell  300 A. 
     While layout configurations can use the cell layouts shown in  FIGS. 4 and 5  repeated in the same orientation throughout an array of such cells, other layout configurations are possible. For example, other configurations wherein a number of cells having the same source/gate or gate/source configuration, for example three, four, or more having the same source/gate configuration or gate/source configuration can be repeated in order. A macrocell can then be designated having the three, four, or more repeated cells. The macrocell can itself be repeated or flipped as desire when constructing the finished power device. Those skilled in the art will realize that many such repeated configurations can be achieved for a power device using the cells shown in  FIG. 4 ,  FIG. 5 , or a mixture of those shown in  FIGS. 4 and 5 . The flipping of the cells or macrocells can be done in both the X-axis and Y-axis directions as desired. 
       FIG. 6  is a table  600  of simulation results for a plurality of SJ VDMOS devices comprising different polysilicon gate lengths according to embodiments. Four simulations were run for single source contact embodiments having gate lengths of 1 μm, 1.4 μm, 1.8 μm, and 2.2 μm. For comparison, a simulation was run for an exemplary device having two source contacts with a total gate length of 3.6 μm. 
     Table  600  is based on a boy BV (Breakdown Voltage datasheet rating) SJ VDMOS platform, which summarizes FOM related device parameters. A significant reduction of Qg (gate charge Qg is defined as the charge from zero to the point at which the driving voltage Vgs equals the actual gate voltage of the device), Ciss (effective input capacitance seen by the gate drive circuit, Ciss=Cgs+Cgd with Cds shorted), Crss (reverse transfer capacitance, Crss=Cgd, which is also called Miller Capacitance), and FOM (Figure of Merit: Rds(on)×Qg) achieved when comparing the single source stripe device to the exemplary dual source stripe device. Also shown in  FIG. 6  is the output capacitance Coss. The simulated value of the output capacitance Coss is not significantly affected by the gate length and number of source contacts since a P+ source contact remains where the N+ source contact has been removed. Furthermore, Coss is not significantly changed since the drain side of the device cell is not changed, such that the source to drain overlap not changed. 
     The FOM percentage reduction is a function of polysilicon gate length. In a specific range, the shorter the length, the more the improvement in FOM. While the polysilicon gate length can be reduced to the minimum amount, this may cause a corresponding increase in Rds(on). Thus, in some embodiments the polysilicon gate length is chosen to be above the minimum length geometry offered by the manufacturing technology used, since Rds(on) will be on the border of starting to increase dramatically which will be more dominant than the Qg reduction so FOM will be the same or even higher so it is not possible to push this parameter to a point that even small variation will affect device parameters dramatically. 
       FIG. 7  is a table  700  of simulation and measurement results for a plurality of VDMOS devices comprising different polysilicon gate lengths according to embodiments. Table boo uses a 250V BV (Breakdown Voltage datasheet rating) platform, showing a significant reduction of Qg (gate charge), Qgs (gate to source charge), Qgd (gate to drain charge), and FOM (Figure of Merit) achieved when comparing the single source stripe device to the conventional dual source stripe device. Also shown in  FIG. 7  is the Rds(on) resistance, which shows only a slight increase in resistance. Based on measured data, a 40% FOM improvement has been achieved when the polysilicon length is reduced by half. Similar to the 100V case shown in  FIG. 5 , further FOM reduction can be achieved by further shrinking the polysilicon gate length in a range that is allowed by the corresponding process window. 
     Compared to the exemplary devices shown in  FIGS. 1A, 1B, and 3 , the device embodiments shown in  FIGS. 2A, 2B, 4, and 5  include a source contact only on one side of the polysilicon gate. There is no source contact on the other side of the polysilicon gate, according to the embodiments shown and described herein. The polysilicon gate length is thus significantly reduced, whose length is used to make sure that the channel is turned on/off during switching but having minimum overlap with drain. (The N-epitaxial layer described above is also part of the drain side since it is connected to the drain through the N-type doping.) Thus Qgd (gate to drain charge) is much improved. Further, there is no polysilicon on top of the P-body region on the side where the N+ source contact is removed. Thus, there is no inversion layer when the device is turned on. As a result, gate to source overlap is reduced to half, which results in half of Qgs (gate to source charge). Total Qg (gate charge) is thus significantly reduced, with a small corresponding increase is Rds(on). Since the percentage of Rds(on) increase is less than the decrease of Qg, the FOM is significantly reduced. 
     Thus, embodiments have been described wherein, with respect to the two source contact exemplary devices, half of the source contact and corresponding channel have been removed, and the length of the polysilicon gate has been reduced. Devices according to embodiments described herein exhibit improved performance and lower FOMs due to the reduction of Qg being more than the increase of Rds(on). 
     Device embodiments can be used in small power converters because the circuits used in the small power converters are normally are single ended and subject to hard switching. Device embodiments can also be used in low voltage applications, especially when switching loss is dominant (e.g., the top switch of buck converter). Device embodiments can also be used in combination with conventional devices, for example as a top switch and the conventional device as bottom switch (where conduction loss is dominant) for optimal efficiency. 
     When constructing a power device, a plurality of cells as shown in  FIGS. 2A, 2B, 4 , and  5  may be used, in any orientation. However, a plurality of cells as shown in  FIGS. 1A, 1B, and 3  may also be used, in any orientation, to create a power device having a mixture of cell types. Such a mixture of cells types may be used to achieve a specific FOM in an embodiment. 
     In an example, a device comprises a cell, wherein each cell comprises: a body comprising a main top surface and a main bottom surface; a gate on the main surface on the device having a first length; a gate isolation layer over the gate having a second length at least twice as long as the first length; a source contact in the device body proximate to the gate; a source metal layer over the gate isolation layer; and a drain on the main bottom surface of the cell. The device can comprise a plurality of substantially identical cells, wherein the gate is asymmetrical with respect to the gate isolation layer, and wherein the source contact is asymmetrical with respect to the gate isolation layer. The second length can be at least three times as long as the first length. The gate can comprise a minimum length gate, and can comprise a polysilicon gate. 
     In another example, a device comprises a cell, wherein each cell comprises: a gate stripe having a first edge and a second edge; a source stripe extending along and being overlapped by the first edge of the gate stripe; and a charge reduction stripe extending along the second edge of the gate stripe. The device can comprise a plurality of substantially identical cells, and further comprises forming a channel underneath the gate stripe in an active mode of operation, and not forming a channel underneath the charge reduction stripe in the active mode of operation. A length of the charge reduction stripe is greater than a length of the source stripe or the gate stripe. The gate stripe can comprise a minimum length gate stripe, and can comprise a polysilicon gate stripe. 
     An example method of fabricating a device cell comprises forming a gate on a main surface of the device cell having a first length; forming a gate isolation layer over the gate having a second length at least twice as long as the first length; forming a source contact proximate to the gate; forming a source metal layer over the gate isolation layer; and forming a drain on a main bottom surface of the device cell. The example method comprises forming a plurality of substantially identical cells, wherein the gate is formed asymmetrically with respect to the gate isolation layer, and wherein the source contact is formed asymmetrically with respect to the gate isolation layer. Forming the gate can comprise forming a minimum length gate and can comprise forming a polysilicon gate. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.