Patent Publication Number: US-7719918-B2

Title: Semiconductor memory device having input/output sense amplification circuit with reduced junction loading and circuit layout area

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   The present application claims priority to Korean patent application number 10-2007-0016245 filed on Feb. 15, 2007, which is incorporated herein by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device including an input/output sense amplifier that amplifies a read data and provide it to the external, when making a read operation. 
   In general, data stored in a memory cell of a semiconductor memory device is transferred to an input/output sense amplifier via any one of a pair of local input/output lines when a read command is inputted in a read operation. 
   And, the transferred data is amplified by the input/output sense amplifier and then outputted via a global input/output line. 
   A semiconductor memory device may have a structure of two banks that are arranged symmetrically to each other with respect to the input/output sense amplifier arranged therebetween the two banks. When the data stored in one of the above two banks is transferred to the global input/output line in a read operation, the input/output sense amplifier for the remaining bank should remain floating with the global input/output line. 
     FIG. 1  shows one example of a graphic memory structure divided into four quarters. In one quarter (e.g., upper left quarter of  FIG. 1 ), eight banks BA 0  to BA 7  are arranged such that one set of four banks BA 0 , BA 2 , BA 4 , BA 6  and the other set of four banks BA 1 , BA 3 , BA 5 , BA 7  are laid out symmetrically to each other with one-to-one relation between each symmetrically arranged banks. An input/output sense amplifying circuit IOSA is arranged therebetween the two sets of banks. Another set of eight banks DQ 0  to DQ 7  is also arranged in the same upper left corner of  FIG. 1 . The input/output sense amplifier disposed between the two banks BA 0  and BA 1  can be represented as shown in  FIG. 2 . 
   Referring to  FIG. 2 , two input/output sense amplifiers  10 ,  20  are shown therein. The input/output sense amplifier  10  corresponds to the bank BA 0 , and the input/output sense amplifier  20  corresponds to the bank BA 1 . Both input/output sense amplifiers  10 ,  20  are connected to a global input/output line RGIO. Each input/output sense amplifiers  10 ,  20  comprises sense amplifiers  11 ,  21 , inverters IV 1 , IV 2 , and drivers  12 ,  22 , respectively. 
   With such structure, to read data stored in the bank BA 0 , the data stored in the bank BA 0  is transferred to the sense amplifier  11  via any one of a pair of local input/output lines LIO 0  and LIO 0 B, the sense amplifier  11  is turned-on by a strobe signal IOSA_STROBE 0  to amplify the inputted data and outputs an amplified signal D 0  and an inverted amplified signal D 0 B. 
   And, the inverted amplified signal DOB is inverted by the inverter IV 1 , and as the amplified signal D 0  and the signal inverted by the inverter IV 1  are inputted to the driver  12 , the driver is turned-on to transfer a high or low level of data to the global input/output line RGIO. After this, the data transferred to the global input/output line RGIO is latched through a latch LAT. 
   While the bank BA 0  is accessed to read data, the sense amplifier  21  is turned-off by the strobe signal IOSA_STROBE 0 , and the driver  22  is turned-off by the amplified signal D 1  and the output signal of the inverter IV 2  to allow the output stages of the global input/output line RGIO and the driver  22  to be floated. 
   It is noted that all banks BA 0  to BA 7  commonly use the global input/output line RGIO. When reading the bank BA 0 , for example, the output stage of the global input/output line RGIO and the driver  22  are floated, in order to prevent the influence from the input/output sense amplifiers of the remaining banks (such as BA 1  to BA 7 ) on the data that is read from a specific bank (such as BA 0 ). 
   In other word, as shown in  FIG. 3 , when reading the bank BA 0 , only the driver  12  of the BA 0  is turned-on and the drivers corresponding to the remaining banks BA 1  to BA 7  are floated together with the global input/output line RGIO so that all the drivers corresponding to the remaining banks BA 1  to BA 7  have no effect on the operation of reading the bank BA 0 . 
   However, when all drivers for the banks BA 0  to BA 7  are commonly connected to the global input/output line as shown in  FIG. 3 , a junction loading can occur due to the remaining seven drivers of BA 1  to BA 7  (besides the driver  12  corresponding to the bank BA 0 ) causing deterioration of the slop of the data carried by the global input/output line RGIO. 
   When the slop of the data carried on the global input/output line RGIO is deteriorated, the time ‘tAA’ required for inputting the command and then outputting the data increases, thereby causing problems of decreased operating speed of the memory device. 
   Also, as the drivers included in the respective sense amplifier generally drive the long global input/output line RGIO, the size of each driver is rather large. When the large-sized drivers are disposed in every bank of BA 0  to BA 7  as shown in  FIG. 3 , the layout area required for the drivers in the semiconductor memory device becomes a serious problem. 
   SUMMARY OF THE INVENTION 
   Accordingly, the present invention reduces the time required for inputting a command and then outputting a data by reducing a junction loading of input/output sense amplifiers connected to global input/output lines, when making a read operation. 
   Also, the present invention reduces a layout area occupied by a driver in a semiconductor memory device by reducing the number of large-sized drivers included in an input/output sense amplifier. 
   According to one aspect of the present invention, there is provided a semiconductor memory device including a plurality of sense amplifiers that amplify data transferred from each bank and output them as amplified signals, the semiconductor memory device including: a controller that judges the output states of the amplified signals in each sense amplifier to output driving signals corresponding to the output amplified signals; and a driver that drives an global input/output line with the driving signal. 
   Preferably, the driver is floated together with the global input/output line by the driving signal when the sense amplifiers are turn-off and is driven by the driving signal when the amplified signal is transferred from any one of the sense amplifiers. 
   Preferably, the respective sense amplifiers amplify a pair of data transferred from the respective banks, and the controller combines first and second amplified signals output from a first sense amplifier corresponding to a first bank of the banks and third and fourth amplified signals output from a second sense amplifier corresponding to a second bank to output them as first and second driving signals. 
   Preferably, at this time, the second amplified signal is a signal opposite to the first amplified signal in view of a phase and the fourth amplified signal is a signal opposite to the third amplified signal in view of a phase. 
   Preferably, the controller outputting the first and second driving signals includes a first combination unit that enables the first driving signal by way of a logic combination of the second and fourth amplified signals when the second and fourth amplified signals are in a first logic level; and a second combination unit that enables the second driving signal by way of a logic combination of the first and third amplified signals when the first and third amplified signals are in the first logic level. 
   Preferably, in the constitution of the controller, the first combination unit includes a first NAND gate that NAND-combines the second and fourth amplified signals to output it as the first driving signal. 
   Preferably, the second combination unit includes a second NAND gate that NAND-combines the first and third amplified signals; and an inverter that outputs the second driving signal by inverting the output of the second NAND gate. 
   Preferably, the driver includes a pull-up unit that pulls-up the global input/output line to a power source voltage level in response to the first driving signal; and a pull-down unit that pulls-down the global input/output line to a ground voltage level in response to the second driving signal. 
   Preferably, in the constitution of the driver, the pull-up unit includes a PMOS transistor that rises the global input/output line to the power source voltage level in response to the first driving signal and the pull-down unit includes an NMOS transistor that falls the global input/output line to the ground voltage level in response to the second driving signal. 
   Preferably, the first and second banks are arranged to be symmetrical to each other based on the arrangement region of the input/output sense amplifying circuit in which the first and second sense amplifiers are disposed. 
   Preferably, the plurality of drivers share the one global input/output line, the global input/output line being provided with a latch. 
   According to another aspect of the present invention, there is provided a semiconductor memory device including: an input/output sense amplifying circuit having a plurality of drivers; and a plurality of banks arranged to be symmetrical to each other, putting the input/output sense amplifying circuit therebetween, wherein the respective drivers are preferably shared in a pair of banks arranged to be symmetrical to each other among the plurality of banks. 
   Preferably, the plurality of drivers shares one global input/output line, and the respective drivers are floated together with the global input/output lines when data are not transferred from the pair of banks shared and drive the global input/output lines when the data are transferred from any one of the pair of banks shared. 
   Preferably, the global input/output line is further provided with a latch. 
   Preferably, the input/output sense amplifier further includes a plurality of first sense amplifiers that amplify a first data transferred from any one of the pair of banks to provide it as a first amplified signal; a plurality of second sense amplifiers that amplify a second data transferred from the other of the pair of banks to provide it as a second amplified signal; and a plurality of controllers that judge the output states of the first and second amplified signals to generate first and second driving signals corresponding to the output amplified signals; wherein the respective drivers drive the global input/output lines with the first and the second driving signals. 
   Preferably, at this time, the respective controller generates the first and second driving signals corresponding to the first data when the first amplified signal is enabled and the first and second driving signals corresponding to the second data when the second amplified signal is enabled, by way of a combination of the first and second amplified signals. 
   Preferably, in the constitution of the input/output sense amplifying circuit, the respective drivers include a pull-up unit that pulls-up the global input/output line to a power source voltage level in response to the first driving signal; and a pull-down unit that pulls-down the global input/output line to a ground voltage level in response to the second driving signal. 
   Preferably, in the constitution of the respective drivers, the pull-up unit includes a PMOS transistor that rises the global input/output line to the power source voltage level in response to the first driving signal and the pull-down unit includes an NMOS transistor that falls the global input/output line to the ground voltage level in response to the second driving signal. 
   Preferably, each of the plurality of banks is arranged in a bank region divided into a quarter centering on the regions where input/output pads of a center are arranged. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows arrangement of memory banks and input/output sense amplification circuits in a semiconductor memory device. 
       FIG. 2  is a circuit diagram showing two input/output sense amplifiers  10 ,  20  disposed in between two symmetrically arranged banks BA 0  and BA 1  shown in  FIG. 1  according to prior art. 
       FIG. 3  is a circuit diagram showing drivers disposed between one group of four banks BA 0 , BA 2 , BA 4 , BA 6  and the other group of four banks BA 1 , BA 3 , BA 5 , BA 7  showed in  FIG. 1  according to prior art. 
       FIG. 4  is a circuit diagram of an input/output sense amplifier disposed between two banks arranged to be symmetrical to each other according to an embodiment of the present invention. 
       FIG. 5  is a waveform diagram in connection with operation of the circuit shown in  FIG. 4 . 
       FIG. 6  is a circuit diagram showing drivers  140 ,  240 ,  340 ,  440  disposed between a group of four banks BA 0 , BA 2 , BA 4 , BA 6  and the another group of four banks BA 1 , BA 3 , BA 5 , BA 7  according to an embodiment of the present invention. 
   

   DESCRIPTION OF SPECIFIC EMBODIMENTS 
   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
   Embodiments of the present invention allow input/output sense amplifiers, each corresponding to a plurality of banks, to share one driver, making it possible to reduce ‘tAA’ and get an advantage of optimized circuit layout area. 
   The memory bank and input/output sense amplifier structure shown in  FIG. 1  will be referenced with respect to an embodiment of the present invention. In  FIG. 1 , the bank region is divided into four quarters centering on the regions DQ 0  to DQ 23  where input/output pads are arranged. A plurality of banks BA 0  to BA 7  are arranged in each quarter region to have one-to-one correspondence in a symmetrical manner with respect to the input/output sense amplifying circuit IOSA in each quarter. 
   Shown in  FIG. 4  according to an embodiment of the present invention include two sense amplifiers  110 ,  120  that amplify the read data transferred from two corresponding banks arranged to be symmetrical to each other (for example, BA 0  and BA 1  of  FIG. 1 ); a controller  130  that determines data output states of the two sense amplifiers  110 ,  120  and outputs driving signals DRV 1 , DRV 2  to correspond to the outputted data; a driver  140  that drives a global input/output line RGIO based on the driving signals DRV 1 , DRV 2 ; and a latch unit  150  that latches the data transferred to the global input/output line RGIO. Herein, the input/output sense amplifying circuit according to an embodiment of the present invention can be defined to include the sense amplifiers  110  and  120 , the controller  130 , and the driver  140 . 
   The sense amplifier  110  senses and amplifies the potential difference between a pair of local input/output lines LIO 0 , LIO 0 B in response to a strobe signal IOSA_STROBE 0  and outputs the amplified signals D 0 , D 0 B when the data are transferred from the corresponding bank to any one of the pair of local input/output lines LIO 0  and LIO 0 B. 
   Likewise, the sense amplifier  120  senses and amplifies the potential difference between the pair of local input/output lines LIO 0  and LI 1 B in response to the strobe signal IOSA_STROBE 1  and outputs the amplified signals D 1 , D 1 B when the data are transferred from the corresponding bank to any one of the pair of local input/output lines LIO 1 , LIO 1 B. 
   Herein, the two sense amplifiers  110 ,  120  are disposed between the two banks arranged to be symmetrical to each other to amplify the data transferred from the respectively connected banks. 
   The controller  130  includes two combination units  131 ,  132  that combines the amplified signals D 0 , D 1  and the inverted amplified signals D 0 B, D 1 B, respectively, to output them as the driving signals DRV 1 , DRV 2 , wherein the combination unit  131  enables the driving signal DRV 1  when the inverted amplified signals D 0 B, D 1 B are in a first logic level, and the combination unit  132  enables the driving signal DRV 2  when the amplified signals D 0 , D 1  are in the first logic level. 
   For example, the combination unit  131  may comprise an NAND gate NA 0  that NAND-combines the amplified signals DOB, D 1 B and outputs the driving signal DRV 1 , and the combination unit  132  may comprise an NAND gate NA 1  that NAND-combines the amplified signals D 0 , D 1  and an inverter IV 1  that inverts the signal outputted from the NAND gate NA 1 , thereby outputting the driving signal DRV 2 . 
   The driver  140  is floated together with the global input/output line RGIO in accordance with the driving signals DRV 1 , DRV 2  or transfers high or low level data to the global input/output line RGIO. The driver  140  may comprise a pull-down unit  141  and a pull-up unit  142 . 
   For example, the pull-down unit  141  may comprise an NMOS transistor NM that pulls-down the global input/output line RGIO to a ground voltage level in response to the driving signal DRV 1 , and the pull-up unit  142  may comprise a PMOS transistor PM that pulls-up the global input/output line RGIO to a power source voltage level in response to the driving signal DRV 2 . 
   The latch unit  150  latches the state of the global input/output line RGIO and may comprise an inverter IV 4  that inverts the signal of the global input/output line RGIO and an inverter IV 5  that inverts the signal output from the inverter IV 4  to output it to the global input/output line RGIO. 
   The operations of the device according to an embodiment of the present invention will be described in detail with reference to  FIG. 5 . 
   First, when no bank is inputted with a read command, all the amplified signals D 0 , D 0 B, D 1 , D 1 B outputted from the two sense amplifiers  110 ,  120  are maintained in a high state. 
   Accordingly, the driving signal DRV 1  outputted from the controller  130  is in a low level, and the driving signal DRV 2  is in a high level, so that the driver  140  is floated together with the global input/output line RGIO. 
   Next, when a read command is inputted to any one of the two banks symmetrically arranged to each other to transfer the data to the pair of local input/output lines LIO 0 , LIO 0 B, the strobe signal IOSA_STROBE 0  is enabled to turn-on the sense amplifier  110 . 
   Accordingly, the amplified signal D 0  and the inverted amplified signal DOB outputted from the sense amplifier  110  are amplified at different levels. As shown in  FIG. 5  for example, the amplified signal D 0  is in a low level, while the inverted amplified signal DOB is in a high level. 
   And, the amplified signals D 1 , D 1 B outputted from the sense amplifier  120  are still maintained in a high level. 
   The controller  130  NAND-combines a high level of the amplified signal DOB and a high level of the inverted amplified signal D 1 B and outputs a low level of the driving signal DRV 1 , and the controller  130  also NAND-combines a low level of the amplified signal D 0  and a high level of the amplified signal D 1  and then inverts the outputted signal as a low level of the driving signal DRV 2 . 
   The PMOS transistor PM in the driver  140  pulls-up the global input/output line RGIO to a high level based on the driving signals DRV 1 , DRV 2 . Therefore, a high level of data is transferred to the global input/output line RGIO. 
   Subsequently, when the read command is inputted to any one of the two banks symmetrically arranged to each other to transfer the data to the pair of local input/output lines LIO 1 , LIO 1 B, the strobe signal IOSA_STROBE 1  is enabled to turn-on the sense amplifier  120 . 
   Accordingly, the amplified signal D 1  and the inverted amplified signal D 1 B outputted from the sense amplifier  120  are amplified at different levels. As shown in  FIG. 5  for example, the amplified signal D 1  is in a high level while the inverted amplified signal D 1 B is in a low level. 
   And, the amplified signals D 0 , D 0 B outputted from the sense amplifier  110  are maintained in a high level. 
   The controller  130  NAND-combines a high level of the amplified signal DOB and a low level of the inverted amplified signal D 1 B and outputs a high level of the driving signal DRV 1 , and also the controller  130  NAND-combines a high level of the amplified signal D 0  and a high level of the amplified signal D 1  and then inverts the outputted signal as a high level of the driving signal DRV 2 . 
   The NMOS transistor NM in the driver  140  pulls-down the global input/output line RGIO to a low level based on the driving signals DRV 1 , DRV 2 . Therefore, a low level of data is transferred to the global input/output line RGIO. 
     FIG. 6  shows the layouts of the drivers  140 ,  240 ,  340 ,  440  according to an embodiment of the present invention where four banks BA 0 , BA 2 , BA 4 , BA 6  are symmetrically arranged to four banks BA 1 , BA 3 , BA 5 , BA 7 , respectively. 
   As shown in  FIG. 6 , in an embodiment of the present invention, the two symmetrically arranged banks (for example, BA 0 , BA 1 ) are connected to share one driver  140  such that, even in the structure having the eight banks, the read operation can be performed normally using only the four drivers  140 ,  240 ,  340 ,  440 . 
   Accordingly, when reading the bank BA 0  in an embodiment of the present invention, only the driver  140  is operated and all the remaining drivers  240 ,  340 ,  440  are floated together with the global input/output line so that only the junction loadings due to the three drivers  240 ,  330 ,  440  occur, thereby making it possible to improve a signal slop of the global input/output line RGIO. 
   In other words, the conventional devices having the structure of eight banks require that drivers should be disposed in every bank of BA 0  to BA 7 , by which junction loadings due to all of the seven drivers will occur. However, in an embodiment of the present invention, the two symmetrically arranged banks (for example, BA 0 , BA 1 ) share one driver  140  so that only the junction loadings due to the three drivers  240 ,  340 ,  440  occur. 
   With the reduction of the junction loading, the present invention improves the signal slop of the global input/output line RGIO and thus reduces the time ‘tAA’ required for inputting the command and outputting the data to improve an operation speed of a memory. 
   Also, in the prior art, the drivers should be disposed in every bank BA 0  to BA 7  requiring that all of the eight drivers should be disposed. However, in the present invention, the two symmetrically arranged banks (for example, BA 0 , BA 1 ) share the one driver  140  so that the read operation can normally be performed using only all the four drivers  140 ,  240 ,  340 ,  440 . 
   Therefore, an embodiment of the present invention reduces the layout area occupied by the input/output sense amplifier in the semiconductor memory device, thereby making it possible to improve a net die. 
   As above, the present invention has an effect that input/output sense amplifiers each corresponding to a plurality of banks, respectively, is connected to share one driver to reduce a junction loading due to drivers, thereby making it possible to improve a signal slop of a global input/output line. 
   Also, the present invention has an effect that it allows input/output sense amplifiers corresponding to a plurality of banks to share one driver to dispose only one driver per a plurality of banks, thereby making it possible to reduce a layout area occupied by the driver. 
   Those skilled in the art will appreciate that the specific embodiments disclosed in the foregoing description may be readily utilized as a basis for modifying or designing other embodiments for carrying out the same purposes of the present invention. Those skilled in the art will also appreciate that such equivalent embodiments do not depart from the spirit and scope of the invention as set forth in the appended claims.