Patent Publication Number: US-11043451-B2

Title: Electrical fuse and/or resistor structures

Description:
FIELD OF THE INVENTION 
     The invention relates to semiconductor structures and, more particularly, to electrical fuse (eFuse) and resistor structures and methods of manufacture. 
     BACKGROUND 
     Electrical fuses (eFuses)/metal resistors are essential for semiconductor applications such as system-on-chips (SoCs). However, conventional poly fuses/resistors are not feasible due to incompatibility with gate-last high-k/metal gate technology with self-aligned contacts. For example, in the process flow of forming the eFuses/metal resistors, nitride material formed on the top of metal gate material becomes damaged during the etching processes with selective chemistries. 
     SUMMARY 
     In an aspect of the invention, a method comprises: forming metal gates having a capping material on a top surface thereof; protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material; forming an insulator material and metal material within the recess; and forming a contact in direct electrical contact with the metal material. 
     In an aspect of the invention, a method comprises: forming metal gate structures in a dielectric material; forming a capping material over the metal gate structures; forming a mask over the capping material of the metal gate structures; recessing the dielectric material between the metal gate structures by an etching process while the mask over the capping material protects the capping material and the metal gate structures; depositing insulator material and metal material within the recess in the dielectric material; and forming a contact in direct electrical contact with the metal material. 
     In an aspect of the invention, a structure comprises: an efuse formed between replacement gate metals in a dielectric material, the replacement gate metals including a nitride capping material, the efuse is provided within a recess of the dielectric material, and the efuse comprises a nitride insulator material and a metal material which is in contact with a contact structure formed in an insulator material above the efuse. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention. 
         FIG. 1  shows a starting structure and respective fabrication processes according to aspects of the present invention. 
         FIG. 2  shows a recessed portion in a dielectric material and respective fabrication processes according to aspects of the present invention. 
         FIG. 3  shows materials in the recessed portion and respective fabrication processes according to aspects of the present invention. 
         FIG. 4  shows a planar surface formed from the materials in the recessed portion and respective fabrication processes according to aspects of the present invention. 
         FIG. 5  shows a contact structure contacting a metal material and respective fabrication processes according to aspects of the present invention. 
         FIG. 6  shows a recessed portion in a dielectric material and respective fabrication processes according to another aspect of the present invention. 
         FIG. 7  shows materials in the recessed portion and respective fabrication processes according to the other aspect of the present invention. 
         FIG. 8  shows a planar surface of the materials in the recessed portion and respective fabrication processes according to the other aspect of the present invention. 
         FIG. 9  shows a contact structure in contact with a metal material and respective fabrication processes according to the other aspect of the present invention. 
         FIG. 10  shows a beginning structure and respective fabrication processes according to yet another aspect of the present invention. 
         FIG. 11  shows contact trenches in a dielectric material between gate structures and respective fabrication processes according to yet another aspect of the present invention. 
         FIG. 12  shows metal contacts formed in the contact trenches and respective fabrication processes according to yet another aspect of the present invention. 
         FIG. 13  shows an opening formed in insulator material to expose the metal contacts and respective fabrication processes according to yet another aspect of the present invention. 
         FIG. 14  shows materials in the opening of the insulator material and respective fabrication processes according to yet another aspect of the present invention. 
         FIG. 15  shows contact structures in contact with the metal contacts and respective fabrication processes according to yet another aspect of the present invention. 
         FIG. 16  shows an alternative structure and respective fabrication processes according to still yet another aspect of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The invention relates to semiconductor structures and, more particularly, to electrical fuse (eFuse) and resistor structures and methods of manufacture. More specifically, the present invention provides a method and structure for forming electrical fuses/resistors which are embedded in middle of the line (MOL) interlevel dielectric (ILD) layers. For example, in embodiments described herein, a thin metal layer between contacts can be used as fuse links/resistors. 
     In embodiments, electrical contacts to the fuses/resistors are physically isolated from the fuses, with the electrical connection achieved through contacts, e.g., tungsten contacts, formed on top of the gate metal. The structures of the present invention also prevent diffusion of copper into the fuses/resistors thus improving reliability. Moreover, the fabrication processes described herein can be used post SAC (semi-aqueous chemistry) cap formation to form replacement metal gate (RMG) and eFuses. In additional embodiments, the methods for fabricating the eFuse and resistor structures are fully compatible with current CMOS integration processes. 
     The eFuse and resistor structures of the present invention can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the eFuse and resistor structures of the present invention have been adopted from integrated circuit (IC) technology. For example, the structures of the present invention are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the eFuse and resistor structures of the present invention uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. 
       FIG. 1  shows a structure and respective fabrication processes according to aspects of the present invention. In embodiments, the structure  10  includes a metal  16  (e.g., gate metal) with spacers and cap material  14  formed on sidewalls and a top of the gate metal  16 . As should be understood by those of skill in the art, the gate metal  16  is formed in the active region of the structure  10 . The gate metal  16  and spacers and cap material  14  are formed in an interlevel dielectric material  12  using conventional lithography, etching and deposition methods as should be understood by those of skill in the art such that further explanation is not required. In embodiments, the gate metal  16  can be TiN, tungsten or other gate metals known to those of skill in the art. The gate metal  16  can also be representative of a dummy or replacement gate metal. The spacers and cap  14  are preferably nitride material. 
     As shown in  FIG. 2 , a recess  20  is formed in the interlevel dielectric material  12 , e.g., between adjacent gate metals  16 . In embodiments, the recess  20  is formed using lithography and etching processes. More specifically, a mask (photoresist)  18  is exposed to energy (light) to form a pattern masking the active region, e.g., gate metal  16 . The interlevel dielectric material  12  is then subjected to an etching process, e.g., reactive ion etching (using SAC), to remove portions of the interlevel dielectric material  12 . During this etching process, the gate metal  16  and cap material  14 , e.g., nitride, remain protected by the mask  18  such that the cap material  14  will not be removed or eroded from a top of the gate metal  16  during the etching process. In this way, for example, a resistor module will not be affected by erosion caused by the SAC. In embodiments, the recess  20  can be about 15 nm to 80 nm deep, and more preferably about 35 nm to 40 nm deep. 
     As shown in  FIG. 3 , a nitride material  22  is deposited within the recess  20 , followed by a metal material  24 . In embodiments, an oxide material can be deposited on the metal material, as also shown by reference numeral  24 . In embodiments, the metal material  24  can be, e.g., WSix; although other metals or metal alloys are also contemplated by the present invention. In embodiments, the nitride material  22  and metal material  24  can be deposited using conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. The metal material  24  can be used to form an eFuse or resistor in accordance with any of the aspects of the present invention, depending on its thickness. For example, the metal material  24  can be deposited to a thickness of about 5 nm to 10 nm, and more preferably about 10 nm; although other dimensions are also contemplated by the present invention. 
     In  FIG. 4 , the nitride material  22  and metal material  24  undergo a polishing process to planarize these materials thus forming a planar surface. In embodiments, the polishing process can be, for example, a chemical mechanical polishing process. In this way, the nitride material  22  and metal material  24  remain within the recess  20 , and any additional material is removed from the cap material  14 . Also, the cap material  14  will remain intact above the gate metal  16 . 
     In  FIG. 5 , a contact structure  28  is formed in direct electrical contact with the metal material  24 . In embodiments, the contact structure  28  is formed through an insulator material  26 , e.g., oxide, using conventional lithography, etching and deposition processes. For example, after deposition of the insulator material  26 , a mask (photoresist) can be deposited on the insulator material  26  and exposed to energy to form a pattern. An etching process, e.g., RIE, can then be performed through the pattern to form an opening in the insulator material  26  to expose the underlying metal material  24 . A metal material or alloy thereof, e.g., tungsten, TiN, etc., can then be deposited within the opening to form the contact structure  28 . Any residual material formed on the insulator material  26  can then removed by a CMP process. 
       FIGS. 6-9  show an alternative structure and respective fabrication processes according to additional aspects of the present invention. Referring to  FIG. 6 , the structure  10 ′ includes gate modules  14 ′ and  14 ″ (e.g., dummy gate material) formed in an interlevel dielectric material  12  using conventional lithography, etching and deposition methods as should be understood by those of skill in the art such that further explanation is not required. In embodiments, the gate modules  14 ′ and  14 ″ can be nitride material, e.g., TiN. 
     As further shown in  FIG. 6 , a recess  20  is formed in the interlevel dielectric material  12 . In embodiments, the recess  20  is formed using lithography and etching processes. More specifically, a mask (photoresist) is exposed to energy (light) to form a pattern masking the active region, e.g., gate metal  16 . The interlevel dielectric material  12  and the gate module  14 ″ is then subjected to an etching process, e.g., RIE, to remove portions of the interlevel dielectric material  12  and the gate module  14 ″. During this etching process, the gate modules  14 ′, e.g., nitride, remain protected by the mask. In embodiments, the recess  20  can be about 15 nm to 80 nm deep, and more preferably about 35 nm to 40 nm deep. 
     As shown in  FIG. 7 , a nitride material  22  is deposited within the recess  20 , followed by a metal material  24  and an insulator material  30 , e.g., nitride material. In embodiments, the metal material  24  can be, e.g., WSix; although other metals or metal alloys are also contemplated by the present invention. In embodiments, the nitride material  22 , metal material  24  and insulator material  30  can be deposited using conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. The metal material  24  can be used to form an eFuse or resistor in accordance with aspects of the present invention, depending on its thickness. For example, the metal material  24  can deposited to a thickness of about 5 nm to 10 nm, and more preferably about 10 nm; although other dimensions are also contemplated by the present invention. 
     In  FIG. 8 , the nitride material  22 , metal material  24  and insulator material  30  undergo a polishing process to planarize these materials thus forming a planar surface. In embodiments, the polishing process can be, for example, a CMP process. In this way, the nitride material  22 , metal material  24  and insulator material  30  remain within the recess  20 , and any additional material is removed from the gate modules  14 ′. 
     In  FIG. 9 , a contact structure  34  is formed in direct electrical contact with the metal material  24 . In embodiments, the contact structure  34  is formed through insulator material  26 , e.g., oxide, using conventional lithography, etching and deposition processes. For example, after deposition of the insulator material  26 , a mask (photoresist) can be deposited on the insulator material  26  and exposed to energy to form a pattern. An etching process, e.g., RIE, can then be performed through the pattern to form an opening in the insulator material  26  to expose the underlying metal material  24 . A metal material or metal alloy, e.g., tungsten, TiN, etc., can be deposited within the opening to form the contact structure  28 . Any residual material formed on the insulator material  26  can then removed by a CMP process. 
       FIGS. 10-15  show an alternative structure and respective fabrication processes according to additional aspects of the present invention. Referring to  FIG. 10 , the structure  10 ″ includes a post CMP structure having a gate structure  100  formed in an interlevel dielectric material  120  (formed on an insulator material, e.g., STI or BOX) using conventional lithography, etching and deposition methods as should be understood by those of skill in the art such that further explanation is not required. In embodiments, the gate structure  100  includes spacers  105  formed on a gate metal  110  and a capping material  115 , e.g., nitride material. 
     As shown in  FIG. 11 , contact trenches  125  are formed in the interlevel dielectric material  120 , between the gate structures  100 . In embodiments, the contact trenches  125  are formed using lithography and etching processes. More specifically, a mask (photoresist)  18  is exposed to energy (light) to form a pattern masking the active region, e.g., gate structures  100 . The interlevel dielectric material  120  is then subjected to an etching process, e.g., RIE, to remove portions of the interlevel dielectric material  120 . During this etching process, the gate structures  100 , e.g., nitride, remain protected by the mask. 
     As shown in  FIG. 12 , a liner material  130  is deposited within the contact trenches  125 , followed by a metal material  135 . The combination of the liner material  130  and the metal material  135  will form contacts  140 . In embodiments, the metal material  135  can be, e.g., WSix; although other metal or metal alloys are contemplated by the present invention. In embodiments, the liner material  130  can be Ti or TiN or combinations thereof. The metal material  135  and liner material  130  can be deposited using conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. 
     In  FIG. 13 , any residual metal material  135  and liner material  130  on the interlevel dielectric material  120  can be removed using a conventional CMP process. Another insulator material  145 , e.g., oxide, can be formed on the planarized surface, e.g., metal material  135 , liner material  130 , gate structure  100  and exposed portions of the interlevel dielectric material  120 . An opening  150  is formed in the insulator material  145 , partly exposing the contacts  140 . The opening  150  is formed using conventional lithography and etching processes. 
     In  FIG. 14 , a metal material  155 , e.g., WSix, is deposited in the opening  150  and in contact with the contacts  140 . The metal material  155  will also be deposited on the insulator material  145 . An insulator material  160  is deposited within the opening  150  and on the metal material  155 . In embodiments, the insulator material  160  can be nitride or oxide; although other insulator materials are also contemplated by the present invention. Any residual insulator material  160  formed on the metal material  155 , outside the opening  150 , can be removed by a CMP process, with the metal material  155  acting as an etch stop. 
     As shown in  FIG. 15 , contacts  165  are formed in direct electrical contact with the contacts  140 , through insulator material  170 . In embodiments, the contacts  165  are formed through the insulator material  170 , e.g., oxide, using conventional lithography, etching and deposition processes. For example, after deposition of the insulator material  170 , a mask (photoresist) can be deposited on the insulator material  170  and exposed to energy to form a pattern. An etching process, e.g., RIE, can be performed through the pattern to form an opening in the insulator material  170  to expose the metal material of the contacts  140 . A metal material, e.g., tungsten, TiN, etc., can be deposited within the opening to form the contacts  165 . Any residual material formed on the insulator material  170  can then removed by a CMP process. In this way, contacts  165  are formed off of the same plane of the fuse or resistor. 
       FIG. 16  shows an alternative structure and respective fabrication processes according to additional aspects of the present invention. Referring to  FIG. 16 , the structure  10 ″′ includes a post CMP structure having a gate structure  100  formed in an interlevel dielectric material  120  (formed on an insulator material, e.g., STI or BOX) using conventional lithography, etching and deposition methods as should be understood by those of skill in the art such that further explanation is not required. In embodiments, the gate structure  100  includes spacers  105  formed on a gate metal  110  and a capping material  115 , e.g., nitride material. 
     As previously described, contacts  140  are formed in contact trenches formed in the interlevel dielectric material  120 , between the gate structures  100 . In embodiments, the contact trenches are formed using lithography and etching processes as previously described. The contacts  140  can include, e.g., a liner material and metal material deposited using conventional deposition processes, e.g., CVD processes. In embodiments, the metal material can be, e.g., WSix, and the liner material  130  can be Ti or TiN or combinations thereof. Any residual metal material and liner material on the interlevel dielectric material  120  can be removed using a conventional CMP process. 
     In comparison to  FIG. 13 , for example, a recess  200  is formed directly in the interlevel dielectric material  120  between the contacts  140 . The recess  200  is formed using conventional lithography and etching processes. A metal material  155 , e.g., WSix, is deposited in the recess  200  and in contact with the contacts  140 . The metal material  155  will also be deposited on the insulator material  145 . An insulator material  160  is deposited within the recess  200  and on the metal material  155 . In embodiments, the insulator material  160  can be nitride or oxide; although other insulator materials are also contemplated by the present invention. Any residual insulator material  160  and metal material  155  formed outside the recess  200  can be removed by a CMP process stopping on the insulator material  120  thus forming a dielectric cap with the insulator material  160 . 
     Still referring to  FIG. 16 , contacts  165  are formed in direct electrical contact with the contacts  140 , through insulator material  170 . In embodiments, the contacts  165  are formed through the insulator material  170 , e.g., oxide, using conventional lithography, etching and deposition processes. For example, after deposition of the insulator material  170 , a mask (photoresist) can be deposited on the insulator material  170  and exposed to energy to form a pattern. An etching process, e.g., RIE, can then be performed through the pattern to form an opening in the insulator material  170  to expose the metal material of the contacts  140 . A metal material, e.g., tungsten, TiN, etc., can then be deposited within the opening to form the contacts  165 . Any residual material formed on the insulator material  170  can then removed by a CMP process. In this way, contacts  170  are formed off of the same plane of the fuse or resistor. 
     In alternative aspects of the invention, a structure comprises: an efuse formed above the contacts and the replacement gate structures in a dielectric material, the replacement gate metals including a nitride capping material, the efuse is provided within a recess of the dielectric material, and the efuse comprises a nitride insulator material and a metal material which is in contact with a contact structure formed in an insulator material above the efuse. In an additional aspects of the invention, a structure comprises: an efuse formed between contacts and the replacement gate structures in a dielectric material, the replacement gate metals including a nitride capping material, the efuse is provided within a recess of the dielectric material, and the efuse comprises a nitride insulator material and a metal material which is in contact with a contact structure formed in an insulator material above the efuse. 
     The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.