Patent Publication Number: US-2004056708-A1

Title: Fast dynamic low-voltage current mirror with compensated error

Description:
PRIORITY CLAIM  
       [0001] This application claims priority to Italian Application Serial Number 2002A000816, filed Sep. 19, 2002.  
       BACKGROUND OF THE INVENTION  
       [0002] 1. Field of the Invention  
       [0003] The present invention relates to current mirror circuits. More particularly, the present invention relates to a low-voltage current mirror having reduced mirroring error.  
       [0004] 2. The State of the Art  
       [0005] The basic prior-art current mirror, shown in FIG. 1, is well known. Current source  10  is coupled to the drain and gate of n-channel MOS transistor  12  and to the gate of n-channel MOS transistor  14 .  
       [0006] The basic principle of operation of the current mirror of FIG. 1 is that if the VGS voltages of two identical MOS transistors  12  and  14  operating in the saturation region are equal, then their channel currents should be equal and in first approximation expressed as follows:  
         I   i   =I   0 =(β/2)( W/L )( V   GS   −V   th ) 2    
       [0007] There are three effects that cause the current mirror to operate differently from the ideal case: channel length modulation; threshold offset between two different transistors; and imperfect geometrical matching. The second and third effects result from process and layout imperfections.  
       [0008] The first effect, known as the Early effect, depends on the shortening of the effective channel length in the saturation region caused by V ds  being greater than V dsat  limit (V dsat =V gs −V th ). Under these conditions, the depletion region around the drain junction becomes increasingly wider, causing the standard drift transport equations to be substituted by more complex equations which take into account the diffusion effect of charge through the depleted region due to the negative concentration gradient.  
       [0009] This effect becomes more evident as the channel length L decreases. The Early effect coefficient ζ is inversely proportional to L (λ∝1/L). The following expression of an NMOS drain current in the saturated region translates the preceding considerations, giving an idea of how the real mirrored current will differ from the reference current.  
         I   i   =I   0 =(β/2)( W/L )( V   GS   −V   th ) 2 (1 +λV   ds )  
       [0010] Considering the small-signal equivalent circuit, it is possible to derive the output resistance, which is a good measure of the perfection of a current mirror as a current source. Higher performance current mirrors will attempt to increase the value of r out  with respect to the standard case.  
       [0011] The standard current mirror of FIG. 1 has no limitation on V in min  and V out min , that is V imin =V th1 ; V omin =V dsat2    
       [0012] The current mirror of FIG. 1 suffers from the Early effect if V ds ≠V gs . It has a low output impedance r o =1/g o : r o =1/λI o in the saturation region.  
       [0013] Referring now to FIG. 2, a prior-art Wilson current mirror is shown. This current mirror introduces a negative feedback loop with the addition of n-channel MOS transistor  16 . If I o  increases, the current I i  mirrored by n-channel MOS transistor  14  tries to increase in contrast to the hypothesis that I i  is constant. V i  decreases in order to counter this effect, thus reducing the current flowing through n-channel MOS transistor  14 . This effect can also be explained in terms of output impedance increase induced by negative current feedback. As the n-channel MOS cascode transistor  14  enters the linear region, the output impedance of this current mirror decreases, countering the advantageous effects of the feedback structure.  
       [0014] In order to make the Wilson current mirror more symmetrical, a NMOS diode formed from n-channel MOS transistor  18  may be added to its first branch as shown in FIG. 3, thus equalizing the V ds  voltage drop across n-channel MOS transistor  12  and n-channel MOS transistor  14 . This results in an output impedance equal to that of the current mirror of FIG. 2, but the mirroring factor (ε=I o /I i ) has been improved.  
       [0015] Referring now to FIG. 4, a prior-art cascode current mirror is shown. This cascode current mirror is similar to the Wilson mirror, but the gates of n-channel MOS transistor  12  and n-channel MOS transistor  14  are coupled to the drain of n-channel MOS transistor  12  instead of to the drain of n-channel MOS transistor  14 .  
       [0016] Like the Wilson current mirror, the cascode current mirror of FIG. 4 has a high output impedance and mirroring precision, since these improvements are dependant on the saturation of the n-channel MOS transistor  18 . However, like the Wilson current mirror, the cascode current mirror is penalized by the minimum V i  and/or V o  operating value, which is about 2V th .  
       [0017] Referring now to FIG. 5, a prior-art high-swing cascode current mirror is shown. This circuit introduces a n-channel MOS source-follower transistor  20  between the gates of n-channel MOS transistor  18  and n-channel MOS transistor  16  and n-channel MOS bias transistor  22  in series with n-channel MOS source-follower transistor  20 . N-channel MOS source-follower transistor  20  acts as a level shifter, thus biasing n-channel MOS transistor  14  at the high limit of its saturation region. Like the cascode current mirror of FIG. 4, the high-swing cascode current mirror of FIG. 5 has a high output impedance but has the advantage of reducing the minimum V o  operating value. The V i  is subject to the same limitation as the cascode current mirror of FIG. 4.  
       [0018] All of the current mirrors of FIGS. 1 through 5 are limited in their minimum power supply voltage value V DD . This limiting factor makes these circuits unsuitable for low-voltage applications.  
       [0019] Referring now to FIG. 6, a current mirror is shown in which a biasing circuit including n-channel MOS transistor  24  driven from current source  26  has been added to drive the gates of n-channel MOS transistors  16  and  18 . N-channel MOS transistor  12  is not in diode configuration, having its gate coupled to the drain of n-channel MOS transistor  18 .  
       [0020] If the transistors in the circuit are properly sized ((W/L) 18 =(W/L) 16 =(m/n) 2 (W/L) and (W/L) 0 =(1/(1+n/m) 2 (W/L)) it is possible to reduce the minimum V i  and V o  operating value to about only one V th  (if m&gt;&gt;n) without affecting the large output impedance and to improve the current matching capability (being V ds1 =V ds2 +(V dsat ) W/L ), thus improving the mirroring factor ε=I o /I i .  
       BRIEF DESCRIPTION OF THE INVENTION  
       [0021] The present invention provides current mirrors suitable for low-voltage power supply applications.  
       [0022] According to one illustrative embodiment of the present invention, a current mirror comprises a current source; a first n-channel MOS transistor having a drain and a gate coupled to the current source and a source coupled to a source potential; a second n-channel MOS transistor having a drain, a gate coupled, to the drain and gate of the first n-channel MOS transistor, and a source coupled to the source potential; and a zero-threshold-voltage MOS transistor having a source coupled to the drain of the second n-channel MOS transistor, a gate coupled to the drain and the gate of the first n-channel MOS transistor, and a drain comprising an output-current node.  
       [0023] According to another illustrative embodiment of the present invention, a current mirror comprises a first current source; a first n-channel MOS transistor having a drain and a gate coupled to the current source and a source coupled to a source potential; a second n-channel MOS transistor having a drain, a gate coupled to the drain and the gate of the first n-channel MOS transistor, and a source coupled to the source potential; a third n-channel MOS transistor having a source coupled to the drain of the second n-channel MOS transistor, a gate, and a drain comprising an output-current node; a second current source; a p-channel MOS transistor having a drain coupled to the source potential, a source coupled to the second current source and the gate of the third n-channel MOS transistor, and a gate coupled to the drain and the gate of the first n-channel MOS transistor.  
       [0024] According to another illustrative embodiment of the present invention, a current mirror comprises a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel MOS transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel MOS transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel MOS transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel MOS transistor and a drain coupled to the source of the zero-threshold n-channel MOS transistor.  
       [0025] According to another illustrative embodiment of the present invention, a current mirror comprises a current source; a first n-channel MOS transistor having a drain coupled to ground, and a gate and a source coupled to the current source; a second n-channel MOS transistor having a source coupled to ground, a gate coupled to the gate of the first n-channel MOS transistor, and a drain; a first p-channel MOS transistor having a source coupled to an operating potential, and a drain and gate coupled to the drain of the second n-channel MOS transistor; a zero-threshold p-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first p-channel MOS transistor, and a source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel MOS transistor and a drain coupled to the source of the zero-threshold p-channel MOS transistor.  
       [0026] According to another illustrative embodiment of the present invention, a current mirror comprises a first current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the first current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel MOS transistor, and a drain; a third p-channel MOS transistor having a drain coupled to a current-output node, a source coupled to the drain of the second p-channel MOS transistor, and a gate; a second current source; an n-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel MOS transistor, and a drain coupled to the second current source and the gate of the third p-channel MOS transistor.  
       [0027] According to another illustrative embodiment of the present invention, a current mirror comprises a current source, a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel MOS transistor, and a drain; a zero-threshold p-channel MOS transistor having a source coupled to the drain of the second p-channel MOS transistor, a gate coupled to the gate of the first p-channel MOS transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and drain coupled to the drain of the zero-threshold p-channel MOS transistor; a second n-channel MOS transistor having a source coupled to ground, a gate coupled to the gate of the first n-channel MOS transistor, and a drain; and a zero-threshold n-channel MOS transistor having a source coupled to the drain of the second n-channel MOS transistor, a gate coupled to the gate of the first n-channel MOS transistor, and a drain coupled to a current-output node. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES  
     [0028]FIG. 1 is a schematic diagram of a classic prior-art current mirror.  
     [0029]FIG. 2 is a schematic diagram of a prior-art Wilson current mirror.  
     [0030]FIG. 3 is a schematic diagram of another variation of a prior-art Wilson current mirror.  
     [0031]FIG. 4 is a schematic diagram of a prior-art cascode current mirror.  
     [0032]FIG. 5 is a schematic diagram of a prior-art high-swing cascode current mirror.  
     [0033]FIG. 6 is a schematic diagram of another prior-art high-swing cascode current mirror.  
     [0034]FIG. 7 is a schematic diagram of a first error-compensated current mirror suitable for low-voltage operation according to the present invention.  
     [0035]FIG. 8 is a schematic diagram of a second error-compensated current mirror suitable for low-voltage operation according to the present invention.  
     [0036]FIGS. 9A through 9D are schematic diagrams of other alternate error-compensated current mirrors employing p-channel MOS transistors and suitable for low-voltage operation according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0037] Persons of ordinary skill in the art will realize that the following description of the present invention is only illustrative and not in any way limiting. Other embodiments of this invention will be readily apparent to those skilled in the art having benefit of this disclosure.  
     [0038] According to the present invention, it is possible to reduce the Early effect by properly cascoding the mirrored side of a current mirror. Two illustrative methods are shown in FIGS. 7 and 8.  
     [0039] Referring first to FIG. 7, a zero-threshold cascode current mirror is shown. Current source  10  is coupled to the drain and gate of n-channel MOS transistor  12  and to the gate of n-channel MOS transistor  14 . Zero-threshold-voltage MOS transistor  28  is coupled in series with n-channel MOS transistor  14  and its gate is coupled to the gates of n-channel MOS transistors  12  and  14 .  
     [0040] In the current mirror of FIG. 7 both n-channel MOS transistors  14  and  28  have their gates coupled to the reference voltage generated by the diode-connected n-channel MOS transistor  12 . The resulting scheme is very simple, requiring only a single extra transistor. This current mirror does not suffer from the V DDmin =2V th  limitation since the threshold voltage of MOS transistor  28  is close to (ideally) zero. The ideal minimum value of the V in  and V out  voltages:  
     
       V 
       imin 
       =V 
       th12 
       ; V 
       omin 
       =V 
       dsat14  
     
     [0041] Considering the mirroring factor ε=I o /I i =(1+λV gs12 )/(1+λV ds14 ), the error is very close to zero (V ds14 =V gs12 −V th28 ≈Vgs 12 ). Persons of ordinary skill in the art will appreciate that even if the threshold voltage of MOS transistor  28  is not exactly zero but slightly positive, depending on the process technology employed, this mirror circuit plays a significant role in compensating the error of a mirror structure comprising a standard p=mirror followed by an n-mirror (FIG. 3A).  
     [0042] The current mirror of FIG. 7 may be employed in all technologies which include a very-low-threshold-voltage transistor. This may be accomplished either with or without triple well structures to reduce the impact of body effect on the threshold voltage.  
     [0043] Referring now to FIG. 8, a schematic diagram of another illustrative embodiment of the invention shows another possible scheme that reduces the Early effect of the MOS transistor  14  by employing a compensated-threshold cascode standard low-voltage MOS transistor.  
     [0044] In the embodiment of FIG. 8, current source  10  is coupled to the drain and gate of n-channel MOS transistor  12  and to the gate of n-channel MOS transistor  14 . A p-channel MOS transistor  30  has its source coupled to a second current source  32 , its drain coupled to the source potential at ground, and a gate coupled to the gates of n-channel MOS transistors  12  and  14 . N-channel MOS transistor  16  has its gate is coupled to the source of p-channel MOS transistor  30 .  
     [0045] In order to compensate for the V ds  voltage drop of n-channel MOS transistor  14  caused by the non-zero threshold voltage of n-channel MOS transistor  16 , the gate of n-channel MOS transistor  16  is biased by a low-voltage p-channel MOS transistor  30  having its gate line connected to the same gate voltage as n-channel MOS transistors  12  and  14  (the reference voltage generated by n-channel MOS transistor  12 ). The source of p-channel MOS transistor  32  is coupled to the gate of n-channel MOS transistor  16  so as to bias it to one PMOS threshold plus one NMOS threshold. The p-channel MOS transistor  32  and the cascode n-channel MOS transistor  16  act as opposite level shifters (which compensate each other if there is matching between the n-channel and the p-channel transistors) so that the resulting V ds  voltage is the same as the V gs  voltage: V th32 ≈V th16   V th14 +V th32 −V th16 ≈V th14 =V gs14 =V ds14    
     [0046] Persons of ordinary skill in the art will observe that because of the configuration of the p-channel MOS transistor, the feedback it induces allows the cascode n-channel transistor to be correctly biased at all possible values of I ref  current, which is the same current flow across p-channel MOS transistor  32 .  
     [0047] All of the preceding current mirrors have been n-channel current mirrors. The same approach, however, may be used to reduce the Early effect of a p-channel current mirror or to compensate for the error of a current mirror circuit formed by cascading a p-channel transistor with an n-channel transistor.  
     [0048]FIGS. 9A through 9D are examples of p-channel current mirrors according to the present invention. Referring first to FIG. 9A, a schematic diagram of a zero-threshold cascode n-channel current mirror is shown. P-channel MOS transistor  40  is coupled between V DD  and a current source  42  referenced to ground. Its gate and drain are coupled to the gate of p-channel MOS transistor  44 , whose source is also coupled to V DD . The drain of p-channel MOS transistor  44  is coupled to the drain and gate of n-channel MOS transistor  46 . The output structure of this current mirror includes n-channel MOS transistor  48  coupled in series with zero-threshold n-channel MOS transistor  50  between ground and the current output node. The gates of MOS transistors  48  and  50  are coupled to the gate and drain of n-channel MOS transistor  46 .  
     [0049] The current mirror circuit illustrated in FIG. 9B is a zero-threshold p-channel cascode p-channel current mirror. N-channel MOS transistor  52  is coupled between ground and a current source  54  referenced to V DD . Its gate and drain are coupled to the gate of n-channel MOS transistor  56 , whose source is also coupled to ground. The drain of n-channel MOS transistor  56  is coupled to the drain and gate of p-channel MOS transistor  58 , whose source is coupled to V DD . The output structure of this current mirror includes p-channel MOS transistor  60  coupled in series with zero-threshold p-channel MOS transistor  62  between V DD  and the current output node. The gates of MOS transistors  60  and  62  are coupled to the gate and drain of p-channel MOS transistor  58 .  
     [0050] The zero-threshold transistors  50  and  62  in FIGS. 9A and 9B perform the same function in their respective circuits. They both serve to reduce the Early effect in the output structures of the current mirrors containing them.  
     [0051] Referring now to FIG. 9C, a compensated-threshold cascode p-channel MOS current mirror is shown. P-channel MOS transistor  70  is coupled between V DD  and a current source  72  referenced to ground. Its gate and drain are coupled to the gate of p-channel MOS transistor  74 , whose source is also coupled to V DD . The drain of p-channel MOS transistor  74  is coupled to the drain of p-channel MOS transistor  76 , whose source is the current-output node of the circuit. N-channel MOS transistor  78  is coupled in series with current source  80  between V DD  and ground. The gate of n-channel MOS transistor  78  is coupled to the gates of p-channel MOS transistors  70  and  74 . The gate of p-channel MOS transistor  76  is coupled to the drain of p-channel MOS transistor  78 .  
     [0052] Persons of ordinary skill in the art will observe that the circuit of FIG. 9C is the complement of the circuit of FIG. 8, the p-channel and n-channel devices being reversed. Thus, such skilled persons will understand the operation of the circuit of FIG. 9C from the description of the operation of the circuit of FIG. 8.  
     [0053] Referring now to FIG. 9D, a multiple zero-threshold current mirror structure is shown. P-channel MOS transistor  90  is coupled between V DD  and a current source  92  referenced to ground. Its gate and drain are coupled to the gate of p-channel MOS transistor  94 , whose source is also coupled to V DD . The drain of p-channel MOS transistor  94  is coupled to the source of zero-threshold p-channel MOS transistor  96 , and its gate is coupled to the gates of p-channel MOS transistors  90  and  94 . The drain of zero-threshold p-channel MOS transistor  96  is coupled to the drain and gate of n-channel MOS transistor  98 . N-channel MOS transistor  100  is coupled in series with zero-threshold n-channel MOS transistor  102  between ground and the current-output node of the circuit.  
     [0054] While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.