Patent Publication Number: US-6661395-B2

Title: Method and device to drive a plasma display

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to a system and method to drive a plasma display. In particular, the present invention relates to a plasma display driving system and a method of driving a plasma display, by changing scanning frequency, to reduce the scanning time during address period. 
     2. Description of the Related Art 
     An AC memory type plasma display panel (referred to as PDP hereafter) has many advantages such as small size, high display ability, and high reliability. Thus, the PDP can be found in various wide screen electronic devices for displaying output data. The current method of driving a plasma display panel is achieved through a plurality of subframe-display operations, which altogether constitute a full frame-display operation. For example, a picture frame in a plasma display panel with 256 gray levels may comprise eight subframes SF 0 ˜SF 7  as shown in FIG.  1 A. Each subframe-display operation comprises steps of resetting, scanning, and sustaining the display signal. Specifically, a plasma display panel is driven by a driving signal that comprises an erasing period, a addressing period, and a sustaining period. During the erasing period, residual ions of each illuminant cell of a PDP are erased using a voltage pulse having a pulse width shorter than a sustaining pulse. During the addressing period, external data are input using a voltage pulse having a voltage higher than a sustaining pulse of the erasing period. During the sustaining period, an AC voltage of a constant frequency is applied to avoid an ignition miss or incorrect display and to obtain a correct power margin. 
     FIG. 1B shows a cross section of a conventional PDP structure, and FIG. 1C shows a schematic top view of the data and scanning electrodes of the same PDP. As shown in FIG. 1B, a PDP is constructed by joining a front glass substrate  1  with a rear glass substrate  2 , wherein data electrodes  3  for inputting external data are formed on the surface of the front glass substrate  1  that opposes the rear glass substrate  1 . Furthermore, a plurality of ribs  4  is defined on the data electrodes  3  to form illuminant cells. A plurality of sustaining electrodes  7  and scanning electrodes  8  in parallel direction, on the other hand, are formed on the surface of the rear glass substrate  2  that opposes the front glass substrate  1 , wherein the above-mentioned data electrodes  3  are formed perpendicular to both the sustaining electrodes  7  and the scanning electrodes  8 . In addition, the surfaces of both the sustaining electrodes  7  and scanning electrodes  8  are coated with a dielectric layer  6  (such as a MgO layer) for protecting the surfaces of the electrodes. Furthermore, a fluorescence material  5  (such as phosphorous) is deposited between ribs (where the illuminant cells reside) for illumination to occur as soon as a voltage is applied. As shown in FIGS. 1C and 1D, a typical conventional plasma display panel comprises a plurality of row plasma display units (represented by L 1 ˜LN). Each row display unit has one of the plurality sustaining electrodes  7  (represented by a corresponding X 1 ˜X N ), one of the plurality of parallel scanning electrodes  8  (Y 1 ˜Y N ); for example, the first row display unit L 1  comprises the first sustaining electrode X 1 , and the first scanning electrode Y 1 . The plurality of illuminant cells of the first row display unit L 1  is driven by the X 1 , Y 1  simultaneously during the sustaining period. The plurality of data electrodes  3  (D 1 ˜D M ) are disposed perpendicular to both the sustaining electrodes  7  (X 1 ˜X N ) and the scanning electrodes  8  (Y 1 ˜Y N ). Each of the sustaining electrodes  7  (X 1 ˜X N ) is connected to the others and thereby the electrodes can be driven synchronously. In contrast, each of the scanning electrodes  8  (Y 1 ˜Y N ) is connected separately from the other electrodes so as to actuate each of the electrodes independently. Thus, external data are input to each illuminant cell of the plasma display panel via the data electrodes  3  (D 1 ˜D M ) by controlling both the sustaining electrodes  7  (X 1 ˜X N ) and the scanning electrodes  8  (Y 1 ˜Y N ). 
     FIG. 2 is a driving signal diagram of various electrodes of the plasma display panel shown in FIGS. 1B,  1 C, and  1 D, which are driven according to the method of a prior art. Accordingly, a plasma display panel is driven by a driving signal that comprises an erasing period, an addressing period, and a sustaining period. During the erasing period, a very short pulse V W  of a high voltage is applied to all of the sustaining electrodes  7  (including X 1 ˜X N ), and all of the scanning electrodes  8  (including Y 1 ˜Y N ) are connected to the ground V g , so as to remove the remaining residual ions. At this point, no data electrodes  3  (including D 1 ˜D M ) are driven yet. During the addressing period, a bias V K  is applied to all of the sustaining electrodes  7  (including X 1 ˜X N ), so the scanning electrodes  8  (Y 1 ˜Y N ) can input external data sequentially via the data electrodes  3  (D 1 ˜D M ) based on an addressing signal V Y . At this point, the scanning electrodes  8  (Y 1 ˜Y N ) are connected to a row address decoder (not shown in the figure) to receive an addressing signal, and the data electrodes  3  (D 1 ˜D M ) are connected to external data to proceed writing operations. During the sustaining period, a periodic voltage pulse V S  is alternately applied to the sustaining electrodes  7  (X 1 ˜X N ) and the scanning electrodes  8  (including Y 1 ˜Y N ) to maintain the luminance of the illuminant cells. FIG. 3 shows the timing chart of the output pulse of the scanning electrodes Y 1 ˜Y N . In FIG. 3, the scanning frequency of each scanning electrode is f p . 
     As shown in FIG. 2, addressing cost most of the frame time. For a 600×400 256 color PDP as a example, if erasing period takes 150 us and each address line takes 3 us, then the erasing period and addressing period take 15.6 ms [(150+3×600)×8/1000=15.6], it is about 90% of one frame time(16.7 ms). Thus, the time for sustaining is too short to generate sufficient brightness. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a plasma display driving system and a method to drive a plasma display. When misfiring does not occur, the frequency, pulse width, and interval of the signals output by the scanning electrodes are modified to decrease the addressing period. Thus, the sustaining period is increased to raise the brightness of the PDP. 
     To achieve the above-mentioned object, the present invention provides a plasma display driving system including a controlling circuit, a scan driver, and a data driver. The controlling circuit outputs a first scan driving pulse and a second scan driving pulse, and a third scan driving pulse during the addressing period. The frequency of the first scan driving pulse is higher than the second scan driving pulse, and the frequency of the second scan driving pulse is higher than the third scan driving pulse. The scan driver drives the first scanning electrodes, the second scanning electrodes, and the third scanning electrodes according to the first scan driving pulse, the second scan driving pulse, and the third scan driving pulse respectively. The data driver drives the first data electrodes, the second data electrodes, and the third data electrodes responding to the first scanning electrodes, the second scanning electrodes and the third scanning electrodes when the scanning electrodes are driven. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention. 
     FIG. 1A shows the subframes included in a picture frame in a plasma display panel with 256 gray levels. 
     FIG. 1B shows a cross section of a conventional PDP structure. 
     FIGS. 1C and 1D show schematic top views of the data and scanning electrodes of the same PDP. 
     FIG. 2 is a driving signal diagram of various electrodes of the plasma display panel. 
     FIG. 3 is a timing chart of the conventional plasma display driving system. 
     FIGS.  4 ( a ) and ( 4   b ) are block diagrams of the PDP and the drive circuit according to the present invention. 
     FIG. 5 is a timing chart of the plasma display driving system according to the first embodiment of the present invention. 
     FIG. 6 is a timing chart of the plasma display driving system according to the second embodiment of the present invention. 
     FIG. 7 is a timing chart of the plasma display driving system according to the third embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 4A and 4B are block diagrams of the PDP and the drive circuit according to the present invention. The scan driver  32  provides scan pulse and sustain discharge pulse to scanning electrodes Y 1 ˜Y N . The sustain driver  31  provides sustain discharge pulse to sustain electrode  7 . The data driver  33  provides data pulse to data electrodes D 1 ˜D M . The controlling circuit  34  controls the operation of the sustain driver  31 , the scan driver  32 , and the data driver  33 . 
     According to the embodiments of the present invention, the controlling circuit  34  controls the output signal timing of the scan driver  32  and the data driver  33  to decrease the addressing time of the conventional address display separation driving method. 
     First Embodiment 
     In FIG. 4A, during addressing period and in the prerequisite of avoiding misfiring, the first scan driving pulse, the second scan driving pulse, and the third scan driving pulse are output in turn by controlling circuit  34 . Here, pulse width is getting wider from the first scan driving pulse to the third scan driving pulse, and the periods between the falling edge of the first scan driving pulse and the rising edge of the second scan driving pulse are equal to the periods between the falling edge of the second scan driving pulse and the rising edge of the third scan driving pulse. 
     In addition, the controlling circuit  34  controls the pulse width of the scan driving pulses received by the first data electrode, the second data electrode, and the third data electrode in turn by the scan pulse width controller  346 , and makes the interval between each pulse equal by the scan pulse trigger  347 . 
     FIG. 5 is a timing chart of the plasma display driving system according to the first embodiment of the present invention. The scan driver  32  drives the first scanning electrode, the second scanning electrode, and the third scanning electrode according to the responding first scan driving pulse, the second scan driving pulse, and the third scan driving pulse, respectively. The pulse width (Δtr 1 ˜Δtr n ) of the pulses output from the scanning electrodes is getting wider. In addition, Δtr n  is the same as the tr p  in FIG. 3, and the periods between each pulse are all ΔT 1 . Because the pulse width (Δtr 1 ˜Δtr n−1 ) are narrower than the conventional pulse width tr p , the addressing period is decreased. Thus, the first embodiment of the present invention decreases the addressing time by decreasing scan pulse width and scanning time to increase sustaining time, and the brightness of the PDP panel is improved. 
     Next, data driver  33  drives the data electrodes D 1 ˜D M  responding to the scanning electrodes to write data when the scanning electrodes Y 1 ˜Y N are driven respectively. 
     In addition, the present invention can use scan pulses having only two types, but the effect is less conspicuous than with three types. 
     Second Embodiment 
     In FIG. 4B, during addressing period and in the prerequisite of avoiding misfiring, the first scan driving pulse, the second scan driving pulse, and the third scan driving pulse are output in turn by controlling circuit  34 . Here, pulse width is getting wider from the first scan driving pulse to the third scan driving pulse. Moreover, the frequency of the first scan driving pulse is higher than the second scan driving pulse, and the frequency of the second scan driving pulse is higher than the third scan driving pulse. 
     In the second embodiment, the controlling circuit  34  controls the first scanning electrodes, the second scanning electrodes, and the third scanning electrodes to output scan pulses with different frequency in turn by the scan frequency controller  3442 , the data frequency controller  3482 , and data output controller  3413 . 
     The scan driver  32  drives the first scanning electrodes (Y 1 ˜Y n1 ), the second scanning electrodes (Y n1+1 ˜Y n1+n ), and the third scanning electrodes (Y n2+1 ˜Y n2+n ) according to the responding first scan driving pulses, the second scan driving pulses, and the third scan driving pulses, respectively. 
     FIG. 6 is a timing chart of the plasma display driving system according to the second embodiment of the present invention. The output frequency of the first scanning electrodes (Y 1 ˜Y n1 ) is f 1 , the output frequency of the second scanning electrodes (Y n1+1 ˜Y n1+n ) is f 2 , and the output frequency of the third scanning electrodes (Y n2+1 ˜Y n2+n ) is f 3 . Here, the output frequency f 3  is higher than the conventional output frequency f p  of the scanning electrodes, and the frequency f 3  is higher than f 2 , and the frequency f 2  is higher than f 1 . 
     Thus, the second embodiment of the present invention decreases the addressing time by increasing the scan frequency, and the brightness of the PDP panel is improved. 
     Next, data driver  33  drives the data electrodes responding to the scanning electrodes to write data when the scanning electrodes are driven respectively. 
     In addition, the present invention can use scan pulses with two frequency types, but the effect is less conspicuous than with three. 
     Third Embodiment 
     The controlling circuit  34  outputs the first scan driving pulses, the second scan driving pulses, and the third scan driving pulses in turn during addressing period. Here, the pulse width of the first scan driving pulses is narrower than the second scan driving pulses, and the pulse width of the second scan driving pulses is narrower than the third scan driving pulses. 
     The scan driver  32  drives the first scanning electrodes (Y 1 ˜Y n ), the second scanning electrodes (Y n1+1 ˜Y n1+n ), and the third scanning electrodes (Y n2+1 ˜Y n2+n ) according to the responding first scan driving pulses, the second scan driving pulses, and the third scan driving pulses, respectively. 
     FIG. 7 is a timing chart of the plasma display driving system according to the third embodiment of the present invention. The pulse width output from the first scanning electrodes (Y 1 ˜Y n ) is Δtr 1 , the pulse width output from the second scanning electrodes (Y n1+1 ˜Y n1+n ) is Δtr 2 , and the pulse width output from the third scanning electrodes (y n2+1 ˜Y n2+n ) is Δtr 3 . In the prerequisite of avoiding misfiring, the pulse width Δtr 3  is less than or equal to the pulse width tr p  output by the conventional scanning electrode. In addition, the pulse width Δtr 3  is wider than the pulse width Δtr 2 , and the pulse width Δtr 2  is wider than the pulse width Δtr 1 . Thus, the decreased pulse width will decrease the addressing time, then the sustaining time is increased, so the brightness of the PDP panel is improved. 
     Next, data driver  33  drives the data electrodes responding to the scanning electrodes to write data when the scanning electrodes Y 1 ˜Y N , Y n1+1 ˜Y n1+n , and Y n2+1 ˜Y n2+n  are driven respectively. 
     In addition, the present invention can use scan pulses having only two types, but the effect is less conspicuous than with three types. 
     Accordingly, when misfiring does not occur, the frequency, pulse width, and interval of the signals output by the scanning electrodes are modified to decrease addressing period. Thus, the sustaining period is increased to raise the brightness of the PDP. 
     The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.