Patent Publication Number: US-11387753-B2

Title: Semiconductor integrated circuit, semiconductor integrated circuit device, and motor-drive control system

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-170534, filed on Sep. 19, 2019; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor integrated circuit, a semiconductor integrated circuit device, and a motor-drive control system. 
     BACKGROUND 
     Conventionally, there has been disclosed a semiconductor integrated circuit including an H-switch that performs charge, discharge, and low-speed discharge on current for an exciting coil of a motor. The charge, discharge, and low-speed discharge are controlled by turning ON/OFF of a switching element constituting the H-switch. The switching element in an ON-state generates heat due to current flowing through its on-resistance. Functions of the switching element may be deteriorated due to the generated heat. Furthermore, a life of the switching element is shorter as a time interval during which the switching element is exposed to heat is longer. Thus, there are desired a semiconductor integrated circuit, a semiconductor integrated circuit device, and a motor-drive control system capable of effectively dispersing generated heat. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a semiconductor integrated circuit according to a first embodiment; 
         FIG. 2  is a diagram schematically illustrating a configuration of a semiconductor integrated circuit device with which the semiconductor integrated circuit according to the first embodiment is integrated; 
         FIGS. 3A to 3F  are diagrams illustrating drive modes of the semiconductor integrated circuit according to the first embodiment; 
         FIGS. 4A and 4B  are diagrams illustrating effects of the semiconductor integrated circuit according to the first embodiment; 
         FIG. 5  is a side view schematically illustrating a configuration of a semiconductor integrated circuit device according to a second embodiment; 
         FIG. 6  is a diagram schematically illustrating a configuration of a first semiconductor chip of the semiconductor integrated circuit device according to the second embodiment; 
         FIG. 7  is a diagram schematically illustrating a configuration of a second semiconductor chip of the semiconductor integrated circuit device according to the second embodiment; 
         FIGS. 8A and 8B  are diagrams schematically illustrating a configuration of a function change circuit; 
         FIG. 9  is a plan view schematically illustrating a configuration of the semiconductor integrated circuit device according to the second embodiment; and 
         FIGS. 10A to 10C  are diagrams illustrating effects of the semiconductor integrated circuit device according to the second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a semiconductor integrated circuit includes: a first switching element whose main current path is connected to a first output end and a power end therebetween, wherein the first output end supplies excitation current to a first exciting coil of a motor; a second switching element whose main current path is connected to the first output end and a first grounding end therebetween; a third switching element whose main current path is connected to a second output end and the power end therebetween, wherein the second output end supplies excitation current to the first exciting coil of the motor; a fourth switching element whose main current path is connected to the second output end and the first grounding end therebetween; a mode set circuit that sets a drive mode of the first to fourth switching elements; and a control circuit that generates, in accordance with the drive mode, drive signals for controlling turning ON/OFF of the first to fourth switching elements, and supplies the generated drive signals to the first to fourth switching elements, wherein the drive mode includes: a first discharge mode that turns ON the first switching element and the third switching element; and a second discharge mode that turns ON the second switching element and the fourth switching element. 
     Exemplary embodiments of a semiconductor integrated circuit, a semiconductor integrated circuit device, and a motor-drive control system will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. 
     First Embodiment 
       FIG. 1  is a diagram illustrating a semiconductor integrated circuit according to a first embodiment. The semiconductor integrated circuit according to the present embodiment includes an H-switch on A-phase (first-phase) side and an H-switch on B-phase (second-phase) side, so as to control drive of a motor. The motor includes an exciting coil  10 , an exciting coil  20 , and a rotor  100 . The rotor  100  is controlled by magnetic field generated by the exciting coil  10  and the exciting coil  20 . 
     The H-switch on A-phase side includes four NMOS transistors  11  to  14 . Drains of the transistor  11  and the transistor  13  are connected to a pad P 3 . A voltage source  600  is connected to the pad P 3 , which supplies a voltage VM. Source-drain paths of the NMOS transistor  11  to  14  form a main current path. A source of the transistor  11  and a drain of the transistor  12  are connected to an output end  10 - 1 . Sources of the transistor  12  and the transistor  14  are connected to a pad P 21 . The pad P 21  is grounded. In other words, a source of the transistor  13  and a drain of the transistor  14  are connected to an output end  10 - 2 . The output end  10 - 1  is connected to a pad P 10 , and the output end  10 - 2  is connected to a pad P 11 . The exciting coil  10  is connected to the pad P 10  and the pad P 11  therebetween. The output ends  10 - 1  and  10 - 2  output excitation current to be supplied to the exciting coil  10 . 
     The H-switch on B-phase side includes four NMOS transistors  21  to  24 . Drains of the transistor  21  and the transistor  23  are connected to the pad P 3 . Sources of the transistor  22  and the transistor  24  are connected to a pad P 22 . The pad P 22  is grounded. A source of the transistor  21  and a drain of the transistor  22  are connected to an output end  20 - 1 . A source of the transistor  23  and a drain of the transistor  24  are connected to an output end  20 - 2 . The output end  20 - 1  is connected to a pad P 12 , and the output end  20 - 2  is connected to a pad P 13 . The exciting coil  20  is connected to the pad P 12  and the pad P 13  therebetween. The output ends  20 - 1  and  20 - 2  output excitation current to be supplied to the exciting coil  20 . 
     PWM signals are supplied, from a Pulse-Width-Modulation (PWM) control circuit  40 , to gates of the transistors  11  to  14  and gates of the transistors  21  to  24  constituting the respective H-switches. Turning ON/OFF of each of the transistors  11  to  14  and  21  to  24  is controlled by a corresponding PWM signal supplied from the PWM control circuit  40 . Excitation currents flowing into the exciting coil  10  and the exciting coil  20  are controlled by turning ON/OFF of each of the transistors. For example, a PWM signal whose Duty is controlled in accordance with an excitation-waveform pattern of a pseudo-sine waveform is supplied to each of the transistors  11  to  14  and  21  to  24  so as to constitute a stepping motor. 
     A mode set circuit  50  sets a drive mode of the transistors  11  to  14  and  21  to  24 . The drive mode includes a charge mode for charging the exciting coils  10  and  20 , a high-speed discharge mode for discharging the exciting coils  10  and  20  at a high speed, and a low-speed discharge mode for discharging the exciting coils  10  and  20  at a low speed. 
     The mode set circuit  50  according to the present embodiment sets a mode (hereinafter, may be referred to as “U-mode”) in which the transistors  11 ,  13 ,  21 , and  23  on the voltage source  600  side are turned ON to discharge charges of the exciting coils  10  and  20  at a low speed, and a mode (hereinafter, may be referred to as “D-mode”) in which the transistor  12 ,  14 ,  22 , and  24  on a ground side are turned ON to discharge charges of the exciting coils  10  and  20 . In the low-speed discharge, the U-mode and the D-mode are alternately executed so as to equalize counts of turning-ON of the transistors  11  to  14 , and  21  to  24 . Therefore, generation of heat due to turning ON of the transistors  11  to  14  and  21  to  24  is equalized and dispersed, and thus functional decline of the transistors  11  to  14  and  21  to  24  due to the heat generation is prevented to be able to extend a life of the semiconductor integrated circuit. 
       FIG. 2  is a diagram schematically illustrating a configuration of a semiconductor chip  1  with which the semiconductor integrated circuit according to the first embodiment is integrated. Note that in the following, a configuration corresponding to the above-mentioned configuration is represented with same reference symbols and the description is omitted appropriately. The same applies hereafter. The semiconductor chip  1  includes a power-unit region  3  and a control-unit region  2 . 
     The power-unit region  3  includes regions A 11  to A 14  in which the transistors  11  to  14  are respectively formed, and regions B 21  to B 24  in which the transistors  21  to  24  are respectively formed. In other words, the transistor  11  is formed in the region A 11 , and the transistor  21  is formed in the region B 21 . The regions A 11 , A 13 , B 21 , and B 23 , in which the transistors  11 ,  13 ,  21 , and  23  whose drains are connected to the voltage source  600  are formed, are arranged in line on an upper-portion side of the power-unit region  3 , in other words, a region side in which the pad P 3  connected to the voltage source  600  is formed. The regions A 12 , A 14 , B 22 , and B 24 , in which the transistors  12 ,  14 ,  22 , and  24  whose sources are grounded are formed, are arranged in line on a lower-portion side of the power-unit region  3 . 
     The output end  10 - 1  is formed in a bonding part of the region A 11  and the region A 12 . Similarly, the output ends  10 - 2 ,  20 - 1 , and  20 - 2  are formed in respective bonding parts of the regions A 13  and A 14 , the regions B 21  and B 22 , and the regions B 23  and B 24 . 
     The pads P 10  to P 13  and the pad P 3  are arranged in line on an upper-portion side of the semiconductor chip  1 . The output ends  10 - 1 ,  10 - 2 ,  20 - 1 , and  20 - 2  are respectively connected to the pads P 10 , P 11 , P 12 , and P 13  by using predetermined wires (not illustrated). 
     The control-unit region  2  includes the PWM control circuit  40  and the mode set circuit  50 . The control-unit region  2  includes an input end CT to which a control signal CTL, supplied from the outside via a pad P 1 , is applied, and an input end CL to which a clock signal CLK, supplied from the outside via a pad P 2 , is applied. The input ends CT and CL are respectively connected to the pads P 1  and P 2  by using predetermined wires (not illustrated). For example, the control signal CTL is supplied to the mode set circuit  50  and the PWM control circuit  40  to be used as a control signal for controlling a value of the excitation current. For example, the clock signal CLK is used as a synchronous signal for controlling a timing when the PWM controlling circuit  40  generates a PWM signal. 
     According to the present embodiment, the transistors  11  to  14  and  21  to  24  constituting the H-switches are integrated with the power-unit region  3 . In other words, at least one of four sides surrounding a region in which the transistor is formed is in contact with a region in which another transistor is formed. Thus, timings are controlled at which the transistors  11  to  14  and  21  to  24  are turned ON, and thus heat generated in a region whose transistor is in an ON-state is able to be dissipated via a region whose transistor is in an OFF-state. 
       FIGS. 3A to 3F  are diagrams illustrating examples of drive modes set by the mode set circuit  50 . The semiconductor integrated circuit according to the first embodiment includes the A-phase side and the B-phase side, the A-phase side and the B-phase side are controlled by drive modes that are similar to each other, and thus the A-phase side will be explained as an example. ON/OFF states of the transistors  11  to  14  and flows of current are illustrated in  FIGS. 3A to 3F . 
     In  FIG. 3A , there is illustrated a state in which the transistors  11  and  14  are in an ON-state. The state indicates a charge mode in which current flows into the exciting coil  10  from a side of the voltage source  600  that supplies the voltage VM. In  FIG. 3B , there is illustrated a state in which the transistors  12  and  14  are in an ON-state. The state indicates a D-mode in which a charge of the exciting coil  10  is discharged at a low speed with reference to a ground potential. In  FIG. 3C , there is illustrated a state in which the transistors  12  and  13  are in an ON-state. The state indicates a high-speed discharge mode in which current flows from the exciting coil  10  in a direction from a ground side to the voltage source  600  so as to discharge a charge of the exciting coil  10  at a high speed. In  FIG. 3D , there is illustrated a charge mode which is similar to that illustrated in  FIG. 3A . In  FIG. 3E , there is illustrated a state in which the transistors  11  and  13  are in an ON-state. The state indicates a U-mode in which a charge of the exciting coil  10  is discharged at a low speed with reference to a power-source voltage VM. In  FIG. 3F , there is illustrated a high-speed discharge mode similar to that illustrated in  FIG. 3C . 
     The exciting coil  10  is excited by repetition of the series of drive modes illustrated in  FIGS. 3A to 3F  so as to drive the rotor  100 . 
       FIGS. 4A and 4B  are diagrams illustrating effects of the semiconductor integrated circuit according to the first embodiment.  FIG. 4A  illustrates transistors turned into an ON-state in the series of drive modes A to F illustrated in  FIGS. 3A to 3F . A transistor in at least one region, which is in contact with a region whose transistor is in an ON-state, is in an OFF-state. Therefore, heat generated from the transistor in an ON-state is able to be dissipated via a region whose transistor is in an OFF-state. Thus, it is possible to effectively dissipate the generated heat. 
     In  FIG. 4B , there is illustrated totalization results of the number of times that each of the transistors  11  to  14  and  21  to  24  is turned ON by the series of controls in the drive modes A to F. The number of times that each of the transistors  11  to  14  and  21  to  24  is turned ON is averaged to be three. Therefore, heat generation due to an ON-state is averaged. In other words, the series of controls includes the U-mode and the D-mode, and thus the number of times that each of the transistors  11  to  14  and  21  to  24  is turned ON is able to be averaged. The heat generation by the transistors  11  to  14  and  21  to  24  is averaged, and thus concentration of heat is avoided to reduce functional decline in the transistors  11  to  14  and  21  to  24  due to the generated heat, so that it is possible to extend a life of the semiconductor integrated circuit device. Note that the U-mode and the D-mode are alternately executed in the series of controls, for example. 
     Second Embodiment 
       FIG. 5  is a side view schematically illustrating a configuration of a semiconductor integrated circuit device according to a second embodiment. The semiconductor integrated circuit device according to the present embodiment includes a semiconductor chip  1 A arranged on an upper surface  70 A side of a die pad  70  made of metal, and a semiconductor chip  1 B arranged on a lower surface  70 B side opposite to the upper surface  70 A. The semiconductor chip  1 B is arranged on the lower surface  70 B side of the die pad  70  and is operated in parallel with the semiconductor chip  1 A, so that it is possible to provide a semiconductor integrated circuit device having a high driving capability. Heat generated from the semiconductor chips  1 A and  1 B are effectively dissipated by the die pad  70 . There is provided a resin that seals therein the semiconductor chips  1 A and  1 B, bonding wires  73  and  74 , and inner portions of leads  71  and  72  of the semiconductor integrated circuit device; however, illustration thereof is omitted. 
     The semiconductor chip  1 A is mounted on a mounting part  70 - 1 A of the upper surface  70 A of the die pad  70  by an adhesive agent  80 A. The pads (not illustrated) formed in the semiconductor chip  1 A are connected to connection parts  71 A and  72 A on the upper side of the leads  71  and  72  by the bonding wires  73  and  74 . 
     The semiconductor chip  1 B is mounted on a mounting part  70 - 1 B of the lower surface  70 B of the die pad  70  by an adhesive agent  80 B. The pads (not illustrated) formed in the semiconductor chip  1 B are connected to connection parts  71 B and  72 B on the lower side of the leads  71  and  72  by the bonding wires  75  and  76 . 
       FIG. 6  is a diagram schematically illustrating a configuration of the semiconductor chip  1 A. The semiconductor chip  1 A has a configuration similar to that of the semiconductor chip  1  according to the first embodiment. Corresponding configuration elements are indicated by adding “A” to their reference symbols. The semiconductor chip  1 A further includes a function change circuit  60 A. The function change circuit  60 A has functions for switching connections between “input ends CL-A and CT-A” and “pads P 1 A and P 2 A”, and connections between output ends “ 10 - 1 A,  10 - 2 A,  20 - 1 A, and  20 - 2 A” and “pads P 10 A, P 11 A, P 12 A, and P 13 A”. 
       FIG. 7  is a diagram schematically illustrating a configuration of the semiconductor chip  1 B. Similarly to the semiconductor chip  1 A, the semiconductor chip  1 B has a configuration similar to that of the semiconductor chip  1  according to the first embodiment. Corresponding configuration elements are indicated by adding “B” to their reference symbols. The semiconductor chip  1 B further includes a function change circuit  60 B. The function change circuit  60 B has functions for switching connections between “input ends CL-B and CT-B” and “pads P 1 B and P 2 B”, and connections between output ends “ 10 - 1 B,  10 - 2 B,  20 - 1 B, and  20 - 2 B” and “pads P 10 B, P 11 B, Pl 2 B, and P 13 B”. 
       FIGS. 8A and 8B  are diagrams schematically illustrating connection relations of wires by the function change circuits  60 A and  60 B. A solid line indicates a connected state, and a dashed line indicates a shut-off state. Connection relations of each of the wires in the function change circuits  60 A and  60 B are corresponding to each other. An example of connection relation by the function change circuit  60 A is illustrated in  FIG. 8A . The function change circuit  60 A has connection routes PL- 1 A to PL- 6 A and PC- 1 A to PC- 6 A. The function change circuit  60 A changes a function of the semiconductor chip  1 A by setting the connection routes PL- 1 A to PL- 6 A and PC- 1 A to PC- 6 A to a connection state or to a shut-off state. 
     The pad P 1 A is connected to the input end CT-A, and the pad P 2 A is connected to the input end CL-A. The output end  10 - 1 A, the output end  10 - 2 A, the output end  20 - 1 A, and the output end  20 - 2 A are respectively connected to the pad P 10 A, the pad P 11 A, the pad P 12 A, and the pad P 13 A. The connection routes PC- 1 A to PC- 6 A are shut off. Note that illustration of a pad P 3 A and pads P 21 A and P 22 A is omitted. 
     An example of connection relation by the function change circuit  60 B is illustrated in  FIG. 8B . The function change circuit  60 B has connection routes PL- 1 B to PL- 6 B and PC- 1 B to PC- 6 B. The function change circuit  60 B changes a function of the semiconductor chip  1 B by setting the connection routes PL- 1 B to PL- 6 B and PC- 1 B to PC- 6 B to a connection state or to a shut-off state. 
     The pad P 1 B is connected to the input end CL-B, and the pad P 2 B is connected to the input end CT-B. The output end  10 - 1 B, the output end  10 - 2 B, the output end  20 - 1 B, and the output end  20 - 2 B are respectively connected to the pad P 13 B, the pad P 12 B, the pad P 11 B, and the pad P 10 B. The connection routes PL- 1 B to PL- 6 B are shut off. In other words, connection relation in the function change circuit  60 A and connection relation in the function changing circuit  60 B are changed in such a manner that connection ends are exchanged between the left portion and the right portion while interposing the pad P 3 A and the pad P 3 B as a center. Note that illustration of the pad P 3 B to which the power-source voltage VM is supplied and grounded pads P 21 B and P 22 B is omitted. 
       FIG. 9  is a plan view schematically illustrating a configuration in which the semiconductor chips  1 A and  1 B are respectively arranged on both surfaces of the die pad  70 . For convenience of explanation, the semiconductor chip  1 A arranged on the upper side of a mounting part  70 - 1  of the die pad  70  and the semiconductor chip  1 B arranged on the lower side of the die pad  70  are two-dimensionally illustrated, and thus the semiconductor chips  1 A and  1 B are illustrated in such a manner that they are separated from the die pad  70 . The semiconductor chip  1 B is arranged under the lower-side surface of the die pad  70 , and thus the semiconductor chip  1 B is illustrated by using dashed lines for convenience of explanation. 
     The clock signal CLK is supplied from a lead  72 - 1  that is common to the semiconductor chips  1 A and  1 B, and the control signal CTL is supplied from a lead  72 - 2  that is common to the semiconductor chips  1 A and  1 B, so that it is possible to execute, in common, synchronization and control of operations of PWM control circuits  40 A and  40 B, and those of mode set circuits  50 A and  50 B, which are integrated with the semiconductor chips  1 A and  1 B. Thus, parallel operation of the semiconductor chips  1 A and  1 B is realized, so that it is possible to increase driving capability of the semiconductor integrated circuit device. 
     The function change circuit  60 A is constituted of the connection relation illustrated in  FIG. 8A , and the function change circuit  60 B is constituted of the connection relation illustrated in  FIG. 8B . The semiconductor chip  1 B is upset and arranged such that its reverse face is in contact with the die pad  70 . Thus, the semiconductor chip  1 B is arranged in a state where left and right of positions of the pads formed in the semiconductor chip  1 B are reversed with respect to positions of the pads formed in the semiconductor chip  1 A. In other words, when viewed from the upper side in perspective, the pad P 10 A of the semiconductor chip  1 A is located on the left side, on the other hand, the pad P 10 B of the semiconductor chip  1 B is located on the right side. In other words, the pad P 13 B of the semiconductor chip  1 B is located in a position corresponding to the pad P 10 A of the semiconductor chip  1 A while interposing the die pad  70  therebetween. 
     The pad P 10 A is connected to a lead  71 - 1  by a wire  73 - 1 , and the pad P 13 B is connected to the lead  71 - 1  by a wire  75 - 1 . The pad P 13 B is changed into a function originally corresponding to the pad P 10 B by the function change circuit  60 B, and thus supplies an output from the output end  10 - 1 B. In other words, the pad P 13 B supplies an output corresponding to that of the output end  10 - 1 A of the semiconductor chip  1 A. Thus, the pad P 10 A and the pad P 13 B are connected to the lead  71 - 1 , and thus outputs from the semiconductor chip  1 A and the semiconductor chip  1 B are summed up, so that it is possible to obtain a configuration that improves driving capability. The same applies to the other pads P 10 B to P 12 B. 
     The pad P 13 B is arranged in a position corresponding to the pad P 10 A. Thus, the lead  71 - 1  is close to the pads P 10 A and P 13 B, so that it is possible to reduce lengths of the wires  73 - 1  and  75 - 1 . The same applies to other wires  73 - 2  to  73 - 5 ,  75 - 2  to  75 - 5 ,  74 - 1 ,  74 - 2 ,  76 - 1 , and  76 - 2 . 
     By employing a configuration in which the function change circuits  60 A and  60 B change connection relation between “the pads P 1 A, P 2 A, P 10 A to P 13 A, P 21 A, P 22 A, P 1 B, P 2 B, P 10 B to P 13 B, P 21 B, and P 22 B” and “ends CT-B, CL-B,  10 - 1 B,  10 - 2 B,  20 - 1 B,  20 - 2 B” so as to change the function, it is possible to arrange the semiconductor chips  1 A and  1 B, having the same configuration, on both respective surfaces of the common die pad  70  and further to execute parallel driving. In other words, it is possible to provide a semiconductor integrated circuit device whose driving capability is improved. When semiconductor chips having the same configuration are prepared as the semiconductor chips  1 A and  1 B, there can be provided semiconductor integrated circuit device in which the semiconductor chips  1 A and  1 B are arranged on respective upper and lower surfaces of the die pad  70  so as to be operated in parallel as long as connection relations in the function change circuits  60 A and  60 B are changed, so that it is possible to reduce the cost of design and manufacturing. 
     Each of the function change circuits  60 A and  60 B may have a configuration in which a corresponding connection relation is changed by whether the connection route is connected or shut off as needed. For example, each of the function change circuits  60 A and  60 B may be constituted of a programmable device such as an eFuse to be electrically programed. In accordance with whether a semiconductor chip having such a configuration is arranged on the upper side or the lower side of the die pad  70 , configurations of the function change circuits  60 A and  60 B are able to be easily changed by programming. Or, each of the function change circuits  60 A and  60 B may have a configuration that changes its connection relation by trimming of whether or not a wire (not illustrated) formed on the semiconductor chips  1 A and  1 B is cut. 
       FIGS. 10A to 10C  are diagrams illustrating effects of the semiconductor integrated circuit device according to the second embodiment. In  FIG. 10A , there are illustrated drive modes of the semiconductor chip  1 A and transistors that are turned ON in accordance with each of the drive modes. In  FIG. 10B , there are illustrated drive modes of the semiconductor chip  1 B and transistors that are turned ON in accordance with each of the drive modes. 
     In  FIG. 10C , there is illustrated a totalization results of the number of times that each of the transistors  11  to  14  and  21  to  24  is turned ON by the series of controls in the drive modes A to F. As illustrated in  FIG. 10C , in the series of controls of the drive mode A to F, the number of times that each of the transistors  11  to  14  and  21  to  24  of the semiconductor chips  1 A and  1 B is turned ON is averaged to be three. Therefore, heat generation due to an ON-state is averaged and dispersed. In other words, the series of controls includes the U-mode and the D-mode, and thus the number of times that each of the transistors  11  to  14  and  21  to  24  is turned ON is able to be averaged. Thus, generated heat is dispersed to prevent functional decline in the transistors  11  to  14  and  21  to  24 , so that it is possible to extend a life of the semiconductor integrated circuit device. Note that the U-mode and the D-mode are alternately executed in the series of controls, for example. 
     The semiconductor chip  1 A has the series of drive modes of the drive modes A to F, on the other hand, the semiconductor chip  1 B has the drive mode E instead of the drive mode B. In other words, the U-mode and the D-mode are exchanged between the semiconductor chip  1 A and the semiconductor chip  1 B. Thus, when the semiconductor chip  1 A on the upper side of the die pad  70  is in the U-mode, the semiconductor chip  1 B operates in the D-mode, and thus regions in which heat is generated are different. According to the above-mentioned control, it is possible to more effectively disperse heat. 
     The semiconductor chips  1 A and  1 B are respectively arranged on the upper side and the lower side of the die pad  70  in an upset manner. Thus, regions A 11 A to A 14 A and B 21 A to B 24 A of the semiconductor chip  1 A and regions A 11 B to A 14 B and B 21 B to B 24 B of the semiconductor chip  1 B that are arranged on the lower surface  70 B side have a line-symmetric relation with respect to center axes of the semiconductor chips  1 A and  1 B. Therefore, for example, when the semiconductor chips  1 A and  1 B operate in the same drive mode A, positions of regions of transistors that are turned ON are different between the semiconductor chips  1 A and  1 B. In other words, at the lower surface  70 B side of the die pad  70  corresponding to the region A 11 A of the transistor  11  that is turned ON in the semiconductor chip  1 A, the region B 23 B of the transistor  23  in an OFF-state is located. Thus, regions generating heat are dispersed, so that it is possible to avoid concentration of heat. 
     The drive transistor is exemplified as an NMOS transistor; however, not limited thereto. For example, the transistors  11 ,  13 ,  21 , and  23  arranged on the power end side may be constituted of PMOS transistors. Furthermore, the switching element may be constituted of a power element such as a GaN transistor and an Insulated Gate Bipolar Transistor (IGBT) having a function of a high withstanding voltage. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.