Patent Publication Number: US-10784372-B2

Title: Semiconductor device with high voltage field effect transistor and junction field effect transistor

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part of U.S. application Ser. No. 15/915,105 filed on Mar. 8, 2018, which is a continuation of U.S. application Ser. No. 14/942,527 filed on Nov. 16, 2015, which claims the benefit under 35 U.S.C. 119(a) of Korean Patent Application No. 10-2015-0047731 filed on Apr. 3, 2015 in the Korean Intellectual Property Office, and further claims the benefit under 35 U.S.C. 119(a) of Korean Patent Application No. 10-2018-0041261 filed on Apr. 9, 2018, the entire disclosures of each of which are incorporated herein by reference for all purposes. 
    
    
     BACKGROUND 
     1. Field 
     The following description relates to a semiconductor device including a high voltage field effect transistor (HVFET) having a common drain structure and a junction field effect transistor (JFET). In addition, the following description also relates to a semiconductor device including a JFET configured to control a pinch-off voltage and current in a HVFET. 
     2. Description of Related Art 
     A high voltage field effect transistor (HVFET) is a device controlling passage of power having tens to hundreds of voltages associated with the power and performs switching of such a high voltage power. The HVFET has to have a high voltage endurance so that a breakdown does not occur even at a high voltage in order to block a current in a turned-off status and also have a small on-resistance value to reduce power loss in a turned-on status. 
     A junction field effect transistor (JFET) is a device included in such a controller of a high voltage power with the HVFET, and a circuit that controls a gate of the HVFET includes low voltage transistors; thereby, the JFET restricts a voltage and a current that are applied to the circuit so that they are not able to exceed a threshold through a pinch-off. 
     HVFETs and JFETs in related arts use a substantial area to perform the aforementioned features. Accordingly, the HVFETs and JFETs have difficulties in minimization of size. 
     To solve the above-described problem, the related arts disclose a fabricating method of a high voltage transistor and a high voltage transistor combined with a junction transistor. However, the junction transistor according to the technique above uses a well region used in a drift drain region of a high voltage transistor as a channel region of the junction field effect transistor. A doping concentration of the well region is determined depending on an on-resistance property of the high voltage transistor, and a structure of a buried impurity layer is determined. Therefore, there is an issue that respective control of current-voltage of the junction transistor is difficult. 
     SUMMARY 
     This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. 
     The following description relates to a semiconductor device and manufacture method thereof with a junction transistor and a high voltage transistor feature that improves a degree of integration by minimizing an area. 
     Further, the following description relates to a semiconductor device and manufacture method with a junction transistor that may control a pinch-off feature of a junction transistor while maintaining an on-resistance (Rsp) feature of a high voltage transistor. 
     In one general aspect, a semiconductor device includes a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region; a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region; and a first gate electrode and a second gate electrode disposed spaced apart from the drain region, wherein a maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view. 
     The source region and the drain region may be disposed between the first gate electrode and the second gate electrode. 
     The first N-type well region and the source region may comprise a junction field effect transistor (JFET), and the JFET has a rectangular shape in a plan view. 
     The rectangular shape may have a vertical length in a vertical direction greater than a horizontal length in a horizontal direction in the plan view. 
     The first N-type well region may have a cross-sectional area smaller than a cross-sectional area of the second N-type well region. 
     The first N-type well region may have a maximum depth smaller than or equal to a maximum depth of the second N-type well region with respect to a top surface of the substrate respectively. 
     The semiconductor device may further comprise a P-type gate region disposed in the first N-type well region. 
     The drain region, the first gate electrode and the second gate electrode of the semiconductor device may comprise a High Voltage Field Effect Transistor (HVFET). 
     In another general aspect, a semiconductor device includes a first gate electrode disposed on a substrate; a second gate electrode disposed on the substrate; and a first source region and a first drain region disposed between the first gate electrode and the second gate electrode, wherein the first source region has a maximum vertical length in a direction vertical to the first or second gate electrode and a maximum width in the direction, and wherein the maximum vertical length of the first source region is greater than the maximum width. 
     The semiconductor device may further comprise a well region, and the source region and the drain region are disposed in the well region. 
     The semiconductor device may further comprise a third gate electrode disposed on the substrate, and a second source region and a second drain region disposed between the second gate electrode and the third gate electrode. 
     The first and second source regions may comprise a junction field effect transistor (JFET), and wherein the first, second and third gate electrodes and the first and second drain regions comprise a High Voltage Field Effect Transistor (HVFET). 
     Other features and aspects will be apparent from the following detailed description, the drawings, and the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a semiconductor device according to embodiments. 
         FIG. 2  is a top-view of a semiconductor device according to a comparative example. 
         FIG. 3  is a top-view of an embodiment of a semiconductor device. 
         FIG. 4  is a diagram in which a portion of the semiconductor device of  FIG. 3  is enlarged. 
         FIG. 5  is a cross-sectional view taken along the line A-A′ of the semiconductor device  1  of  FIG. 3 . 
         FIG. 6  are cross-sectional views of embodiments of the semiconductor device  1  of  FIG. 3  along line B-B′. 
         FIG. 7  is a top-view of another embodiment of a semiconductor device. 
         FIG. 8  are cross-sectional views of embodiments of the semiconductor device  1  of  FIG. 7  along line C-C′. 
         FIG. 9  are cross-sectional views of embodiments of the semiconductor device  1  of  FIG. 7  along line D-D′. 
         FIG. 10  is a top-view of another embodiment of a semiconductor device. 
         FIG. 11  is a top-view of an embodiment of a semiconductor device. 
         FIG. 12  is a V-I graph according to an operation of a semiconductor device according to an embodiment and a comparative example. 
         FIG. 13  are contour map of equipotential electric field line of a semiconductor device of a comparative example and an embodiment. 
     
    
    
     Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. 
     DETAILED DESCRIPTION 
     The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness. 
     The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application. 
     Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween. 
     Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element&#39;s relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly. 
     The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof. 
     For convenience of explanation, in a top-view of a semiconductor device, a part in which an external electrode D is disposed is referred to as a head, and a part in which a common drain region connected to an external electrode D is divided into two parts and is arranged long is referred to as a tail. However, it will be clearly understood that embodiments of the following disclosure are not limited to the above-mentioned names, but may be variously named, which will be apparent to those skilled in the art. 
     In addition, in the following description, if a substrate of a semiconductor device is P-type, a well region may be N-type in an embodiment. If a substrate of a semiconductor is N-type, a well region may be P-type in another embodiment. 
     The following description is provided to suggest a semiconductor device having the structure of a Junction Field Effect Transistor (JFET) and a High Voltage Field Effect Transistor (HVFET) that minimize an area, thereby improving integration degree. 
     The following description is also provided to suggest a semiconductor device having a JFET that may control pinch-off feature of a JFET while maintaining on-resistance feature of a HVFET. 
     The following description is also provided to suggest a semiconductor device having a JFET that may control a current amount while maintaining on-resistance feature of the JFET. 
     The following description is also provided to suggest a semiconductor device that allows electric field of a HVFET to be distributed uniformly without being affected by addition of a JFET. 
     The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application. 
       FIG. 1  is a block diagram illustrating a semiconductor device according to embodiments. 
     According to  FIG. 1 , in order to implement a Junction Field Effect Transistor (JFET)  10  and a High Voltage Field Effect Transistor (HVFET)  20 . Here, the JFET  10  is also referred to as Tap-JFET. The semiconductor device  1  converts an alternating current (AC) input  3  into a direct current (DC) voltage signal in a high voltage at a rectifier  2  and receives it. In the HVFET  20 , an application device  6  is connected to an end of a source S, and a control IC  5  is connected to an end of a gate G. The application device  6  to which the semiconductor device  1  is connected may be a USB type C in an embodiment and may be a LED lighting driver in another embodiment, but embodiments of the present description are not limited thereto and include various devices using a HVFET and a JFET together. JFET  10  and HV NMOS  20  are integrated as one chip  1 . The one chip (semiconductor device)  1  may use one common drain to integrate the JFET  10  and HV NMOS  20 . The entire chip area is reducing by embedding the JFET  10  in a certain region of the HVFET  20 . 
       FIG. 2  is a plan view of a semiconductor device according to a comparative example. 
     Referring to  FIG. 2 , a semiconductor device  1 ′ includes a HVFET  20  and a JFET  10 . 
     The JFET  10  includes an N-type source region (first N+ doped region)  110 -S, an N-type drain region  140 -D (second N+ doped region), and a P-type gate region  170 , and the JFET  10  includes the first N-type well region  310 . 
     The HVFET  20  includes an N-type drain region (second N+ doped region)  140 -D formed in a substrate  201 , an N-type HVFET source regions  210 -S,  211 -S (third N+ doped regions), a second N-type well region  320  and a P-type well region  112 - 1 ,  112 - 2 . The HVFET  20  shares a drain region  140 -D with the JFET  10 . Thus, the drain region  140 -D becomes a common drain region for JFET  10  and HVFET  20 . 
     In the semiconductor device  1 ′ of the comparative example, the source region  110 -S and the first N-type well region  310  of the JFET  10  are extended outwardly to the boundary of the area of the HVFET  20 , such that T-shaped JFET  10  is formed in the semiconductor device  1 ′ in a plan view. T-shaped JFET  10  has an extra area of the first N-type well region  310 . Due to the extra area of the first N-type well region  310 . The amount of the N-type impurities (dopants) in the semiconductor device  1 ′ may increase. N-type impurities (dopants) and P-type impurities (dopants) in the semiconductor device  1 ′ are unbalanced. That is, an electrical field in the semiconductor device  1 ′ of the comparative example is not uniformly distributed. The electric field may be locally concentrated on a certain portion of the semiconductor device  1 ′, due to the increased amount of the N-type impurities. As a result, a breakdown voltage may be decreased in the semiconductor device  1 ′ (see “Old” in  FIG. 12 ). 
       FIG. 3  is a plan view of an embodiment of a semiconductor device. An N-type well region  300  includes the N-type well region  310  and the N-type well region  320 . For convenience of the description, hereinafter the N-type well region  310  of the JFET  10  is referred to as a first N-type well region  310 , and the N-type well region  320  of the HVFET  20  is referred to as a second N-type well region  320 . The area of the first N-type well region  310  is remarkably smaller than an area of the second N-type well region  320 . The small area of the first N-type well region  310  is intended to minimize the increase of total N-type dopants. 
     Referring to  FIG. 3 , in a plan view (top view), the first N-type well region  310  of the JFET  10  of the semiconductor device  1  has a rectangular shape. Thus, an area of the first N-type well region  310  of the JFET  10  in  FIG. 3  is smaller than an area of the first N-type well region  310  of the JFET  10  in  FIG. 2 . The JFET  10  is embedded in the HVFET  20 . That is, the JFET  10  is not formed to be protrusive outwardly from a border of the HVFET  20 . Thus, an overall shape of the HVFET  20  combined with the JFET  10  is a rectangle. 
     Due to the small area of the first N-type well region  310 , the amount of the N-type impurities is not increased much, compared to the comparative example illustrated in  FIG. 2 . N-type impurities and P-type impurities in the semiconductor device  1  are balanced. Therefore, the semiconductor device  1  according to the embodiment may allow a breakdown voltage in a predetermined range (see “New” in  FIG. 12 ) and also minimize the chip size. 
     The semiconductor device  1  includes a JFET  10  in the first area  400  and a HVFET  20  in the second area  500 . All of the N-type well regions  310  and  320  are formed in a substrate  201 . The source region  110 -S of the JFET  10  is an N+ doped region formed in the first N-type well region  310 . A vertical length of the source region  110 -S of the JFET  10  is greater than a vertical length of the drain region  140 -D of HVFET  20  in a Y-direction in a plan view. A P-type gate region  170  of the JFET  10  is formed between the first N-type well region  310  and the second N-type well region  320 . The P-type gate region  170  is formed in the substrate  201 . 
     The HVFET  20  includes a common drain region  140 -D (a second N+ doped region), a HVFET source region  210 -S,  211 -S, and a gate electrode  221 -G, as illustrated in the second area  500 . A maximum vertical length of the source region  110 -S of the JFET  10  is greater than a maximum vertical length of the drain region  140 -D of HVFET  20  in a Y-direction in a plan view. 
     In addition, the HVFET  20  includes a P-type well region  112 . The channel region and HVFET source region  210 -S of the HVFET  20  are formed in the P-type well region  112 . 
     The HVFET  20  may further include a field plate  160 . The field plate  160  may comprise metal or polycrystalline silicon to reduce the electric field on the semiconductor device  1 , thereby increasing a breakdown voltage of the semiconductor device  1 . 
       FIG. 4  is a diagram in which the region  400  of  FIG. 3  illustrating an embodiment of the present description is enlarged. Referring to  FIG. 4 , the N-type well region  300  includes, in a direction parallel to a surface of a substrate  201 , the first N-type well region  310  having a first width w 1  and a second N-type well region  320  having a second width w 2 . The first N-type well region  310  includes a source region  110 -S (a first N+ doped region) of a JFET  10  so that the source region of JFET  10  and the first N-type well region  310  can be formed to shape a rectangular. The source region  110 -S of the JFET  10  has a vertical length SL 1  greater than a horizontal length (width) SW 1  in a plan view. The current of the JFET depends on the vertical length SL 1  of the source region  110 -S as well as the width SW 1  of the source region  110 -S. If the vertical length SL 1  of the source region  110 -S increases, the current of the JFET  10  increases. The first N-type well region  310  of the JFET  10  also has a vertical length L 1  greater than a horizontal length (width, W 1 ) in a plan view. 
       FIG. 5  is a cross-sectional view of an embodiment of a semiconductor, which is the cross-sectional view taken along line A-A′ of the semiconductor device  1  of  FIG. 3 . 
     Referring to  FIG. 5 , in the semiconductor device  1 , a well region  300  is formed in a substrate  201 . In an embodiment, if the substrate has a P-type conductivity, the well region may have an N-type conductivity. In another embodiment, if the substrate has an N-type conductivity, the well region may have a P-type conductivity. The first N-type well region  310  of a JFET  10  is disposed in the substrate  201  and has a first depth d 1 . A first N+ doped region  110 -S is disposed in the first N-type well region  310 . 
     The semiconductor device  1  further includes a second N+ doped region  140 -D in an N-type well region  300 . The first N+ doped region  110 -S and the second N+ doped region  140 -D are disposed spaced apart from each other on a top surface of the substrate. The first N+ doped region is a source region of the JFET, and the second N+ doped region is a drain region of the JFET. 
     The N-type well region  300  includes the first N-type well region  310  having a first depth d 1  from a top surface of the substrate  201  and a second N-type well region  320  having a second depth d 2  from the top surface of the substrate  201 . According to various embodiments, the first depth d 1  and the second depth d 2  may be equal (that is, d 1 =d 2 ), or the first depth d 1  may be smaller than the second depth d 2  as illustrated in  FIG. 5  (that is, d 1 &lt;d 2 ). 
     The semiconductor device  1  includes a P-type gate region  170  that is disposed in the N-type well region  300  and has a third depth smaller than the respective first and second depths. The P-type gate region  170  is disposed closer to the source region  110 -S than the drain region  140 -D. The P-type gate region  170  may be maintained at a ground voltage in an embodiment, but may be maintained at a different voltage in another embodiment. 
     The semiconductor device  1  may further include a P+ doped region (not illustrated) in the P-type gate region  170  in an embodiment. To the P+ doped region, a ground voltage may be applied via a terminal (not illustrated) according to an embodiment, and a different voltage may be applied according to another embodiment. 
     A drain region of a HVFET  20  and a JFET  10 , that is, the second N+ doped region  140 -D is formed in the second N-type well region  320 , and the drain region  140 -D is formed as N-type and is connected to the common drain terminal  150 -D. The common drain terminal  150 -D is made of a metal wire. 
     The semiconductor device  1  may further include a field plate  160  on a surface of a field oxide film  120  disposed closer to the drain region  140 -D than the source region  110 -S. The field plate  160  is connected to a common drain region. 
     The source region  110 -S of the JFET  10  is formed in the first N-type well region  310 , and the source region  110 -S is formed as N-type and is connected to the source terminal  250 -S of the JFET  10 . The source terminal  250 -S is made of a metal wire. 
     The JFET source region and the first N-type well region  310  are formed in a boundary of the HVFET  20 , but is not extended into outside the HVFET  20 , as illustrated in  FIG. 3 . The first N-type well region  310  and the second N-type well region  320  each are initially formed spaced apart by a certain distance, and subsequently, they meet at a certain point H after going through a heat treatment at a high temperature. The second N-type well region  320  and the first N-type well region  310  are formed by ion implantation at an equal impurity concentration, and a diffusion region  330  is formed by diffusion of ion-implanted N-type dopants. 
     The diffusion region  330  includes a concave groove H. An N-type impurity concentration of the diffusion region  330  may be lower than that of the first N-type well region  310  or the second N-type well region  320 . A depth of a bottom surface of the diffusion region  330  may be lower than or equal to that of the first N-type well region  310  or the second N-type well region  320 . 
     According to embodiments, a maximum depth d 1  of the first N-type well region  310  may be equal to or different from a maximum depth d 2  of the second N-type well region  320 . 
     In an embodiment, depending on an area of the source region  110 -S of the JFET, the maximum depth d 1  of the first N-type well region  310  may be smaller than the maximum depth d 2  of the second N-type well region  320  (d 1 &lt;d 2 ), but in another embodiment, the respective depths may be equal to each other (d 1 =d 2 ) by adjusting the implanted N-type impurity ions. However, a cross-section area of the first N-type well region  310  is quite less than a cross-section area of the second N-type well region  320 , which is the same when viewed in a plan view as well. 
     Since the entire N-type dopant concentration  300  increases as the cross-section area of the first N-type well region  310  becomes larger, the entire N-type dopant concentration may be adjusted by the cross-section area of the first N-type well region  310 . However, an issue occurs in a breakdown voltage if the dopant concentration of the first N-type well region  310  exceeds a certain level; thus, a degree of dopant implantation of the first N-type well region  310  is properly adjusted to such a concentration that the reduced surface electric field (RESURF) will not collapse. 
     A field oxide film  120  may be formed on a surface of the substrate between a drain region  140 -D and the source region  110 -S. The field oxide film  120  is formed by Local Oxidation of Silicon (LOCOS) process or Shallow Trench Isolation (STI) process. 
     The semiconductor device  1  may further include a buried impurity layer  130 , and the buried impurity layer  130  may be electrically connected to the substrate  201  (see  FIG. 6 ). For example, the buried impurity layer  130  may be formed in the N-type well region  300  in parallel with a top surface of the substrate  201 . The buried impurity layer  130  may be doped with P-type impurity ions and may be formed to cross the second N-type well region  320 , the first N-type well region  310 , and the diffusion region  330 . The buried impurity layer  130  is spaced apart by a certain distance from and under the field oxide film  120 . The buried impurity layer  130  may be formed in a horizontal direction of a bottom surface of the field oxide film  120 . In another example, the buried impurity layer  130  may be formed directly below the field oxide layer without spaces. In the present description, one buried impurity layer is suggested, but in another embodiment, at least two buried impurity layers may be formed spaced apart from each other in a vertical direction with respect to a top surface of the substrate  201 . Also, the breakdown voltage and the on-resistance feature of the JFET  10  may vary depending on the number of the buried impurity layers  130 . 
     The substrate  201  is connected to a ground reference voltage. An output voltage of a source terminal  250 -S of the JFET  10  is determined according to the voltage difference between the substrate  201  and the drain region  140 -D. 
     A P-type gate region  170  of the JFET  10  is formed by implanting P-type impurity ions into the N-type well region  300 . The P-type gate region  170  is formed through the P-type buried impurity layer  130  in contact with the bottom surface of the field oxide film  120 . The P-type gate region  170  of the JFET  10  is electrically connected to the substrate  201  and is grounded. 
     A pinch-off may occur due to a potential difference between the substrate  201  and the source region  110 -S. Thus, a pinch-off voltage V pinch-off  can be adjusted by applying a certain voltage to the source region  110 -S of the JFET and setting the P-type gate region  170  to a ground voltage. Because the common drain region  140 -D is remote from the P-type gate region  170 , the electric potential of the drain at the P-type gate region  170  becomes small. The depletion is generally caused by the source region  110 -S near the P-type gate region  170 , not by the potential different between the drain and the P-type gate region, thereby causing a pinch-off. 
     When the pinch-off occurs in the diffusion region  330 , the resistance of the N-type well region  300  between the common drain terminal  150 -D and the source terminal  250 -S of the JFET rapidly increases. Even if the input voltage of the common drain terminal  150 -D is kept increased, the output voltage of the source terminal  250 -S is maintained at a certain pinch-off voltage. However, if the input voltage is below or equal to the pinch-off voltage, the output voltage of the source terminal  250 -S of the JFET increases in proportion to the input voltage of the common drain terminal  150 -D. That is, even when a high input voltage is input to the drain region, the JFET  10  controls the amount of voltage so that it does not exceed a specific voltage, thereby protecting an internal circuit (e.g., the control Integrated Circuit of  FIG. 1 ) connected to the source terminal  250 -S. 
       FIGS. 6( a ) and 6( b )  are cross-sectional views of an embodiment of the semiconductor device, which is a cross-sectional view taken along the line B-B′ of the semiconductor device  1  of  FIG. 3 . 
     Referring to  FIG. 6( a ) , in a semiconductor device  1  according to an embodiment, a second N-type well region  320  is disposed in a substrate  201 , and a common drain region  140 -D is disposed in one upper side of the well region  300 . The common drain region  140 -D is electrically connected to a common drain terminal  150 -D, and a field oxide film  120  is formed on remaining top surface of the substrate  201  or the second N-type well region  320  except for the common drain region  140 -D. 
     The buried impurity layer  130  may be formed in the second N-type well region  320  and P-type substrate  210 , being spaced apart from a bottom surface of the field oxide film  120  by a certain distance under the field oxide film  120 . In another embodiment, a buried impurity layer  130  may be formed in the second N-type well region  320 , being in contact with the bottom surface of the field oxide film  120  rather than being spaced apart therefrom. In another embodiment, the buried impurity layer  130  may be a plurality of layers. 
     Referring to  FIG. 6( b ) , the semiconductor device  1  according to another embodiment may further include a bulk contact region  161 . 
     The bulk contact region  161  may be formed on a top surface of the substrate  201  in which the second N-type well region  320  is not formed. The bulk contact region  161  is electrically connected to a pick-up terminal  165 . The bias to be applied to the substrate  201  varies depending on the bias applied to the pick-up terminal  165 , so that the pinch-off voltage of the JFET varies depending on the voltage difference between the common drain terminal  150 -D and the pick-up terminal  165 . 
     The field oxide film  120  is formed between the drain region  140 -D and the bulk contact region  161  and formed on the upper surface of the substrate  201  or the second N-type well region  320 . 
     In addition, according to various embodiments, the semiconductor device of the present description  1  may include a P-type gate region  170  and may apply a certain voltage to an electrode (not illustrated) connected to the P-type gate region  170 . 
     In addition, according to various embodiments, the semiconductor device  1  may include a bulk contact region  161  on the upper surface of the substrate  201  and may apply a bias to a pick-up electrode  165 . 
       FIG. 7  is a top-view of an embodiment of a semiconductor device. 
     Referring to  FIG. 7 , it is similar to  FIG. 3  but further includes gate electrodes  221 -G 1 ,  221 -G 2 . The gate electrodes  221 -G 1 ,  221 -G 2  are used as a gate electrode of a HVFET  20 . Each of the gate electrodes  221 -G 1 ,  221 -G 2  is disposed in a region in which a source region  110 -S of a JFET is not disposed. Each of the gate electrodes  221 -G 1 ,  221 -G 2  is symmetrically disposed on both side surfaces of the substrate  201 . In one example, an end of the gate electrode  221 -G 1 , or  221 -G 2  may be formed extending horizontally from the first N-type well region  310 . The HVFET source region  210 -S,  211 -S of the HVFET  20  is formed at a side surface of each gate electrode. The common drain region  140 -D is disposed between the first gate electrode  221 -G 1  and the second gate electrode  221 -G 2 . The source region  110 -S and the first N-type well region  310  are disposed between the first gate electrode  221 -G 1  and the second gate electrode  221 -G 2 . The source region  110 -S of the JFET and the HVFET source region  210 -S,  211 -S of the HVFET  20  are formed spaced apart from each other. Each of the P-type well regions  112 - 1 ,  112 - 2  is formed adjacent to each of the gate electrodes  221 -G 1 ,  221 -G 2  of the HVFET. 
       FIG. 8  is a cross-sectional view of the semiconductor device illustrated in  FIG. 7 , which is a cross-sectional view of the semiconductor device  1  taken along the line C-C′ of  FIG. 7 . 
     In the semiconductor device  1  according to an embodiment, a field oxide film  120  is disposed on a substrate  201 . 
     Each of the gate electrodes  221 -G 1 ,  221 -G 2  of HVFET  20  is disposed on a top surface of the field oxide film  120 . The semiconductor device  1  further includes a P-type buried impurity layer  130  disposed spaced apart from a bottom surface of the field film and having a third depth d 3 . 
     The semiconductor device  1  further includes first and second P-type well regions  112 - 1 ,  112 - 2 . As an embodiment, referring to  FIG. 8( a ) , each of the first and second P-type well regions  112 - 1 ,  112 - 2  is disposed apart from the P-type buried impurity layer  130  and has a fourth depth d 4 , which is a greater than the third depth d 3  (d 3 &lt;d 4 ). The semiconductor device  1  further includes first and second P+ doped regions  301 - 1 ,  301 - 2  respectively disposed in the first and second P-type well regions. 
     The semiconductor  1  further includes a plurality of field plates  222  formed on the field oxide film  120 . The pluralities of field plates  222  are formed spaced apart from each other, so that at least each portion of them are overlapped. 
     Referring to  FIG. 8( b )  as another embodiment, first and second P-type well regions  112 - 1 ,  112 - 2  may be merged as one well region, different from the embodiment of  FIG. 8( a ) . That is, the first and second P-type well regions  112 - 1 ,  112 - 2  and a third P-type well region  112 - 3  may be formed as one P-type well region  112 . 
       FIG. 9  is another cross-sectional view of the semiconductor device  1  illustrated in  FIG. 7 , taken along the line D-D′. 
     Referring to  FIG. 9 , the semiconductor device  1  includes at least a P-type well region  112 - 1 ,  112 - 2 , the first N-type well region  310 , and a field oxide film  120 . 
     The first and second field oxide films  120  are disposed on a top surface of the substrate  201 , and the first N-type well region  310  having a fifth depth d 5  is disposed on the top surface of the substrate  201 . 
     The semiconductor device  1  further includes at least one first N+ doped region  110 -S (a source region of the JFET) disposed in the first N-type well region  310 . 
     The first and second P-type well regions  112 - 1 ,  112 - 2  are disposed symmetrically on both sides of the first N-type well region  310  and spaced apart from the first N-type well region  310 , and they have a sixth depth d 6  less than the fifth depth d 5 . 
     The semiconductor device  1  further includes first and second P+ doped regions  301 - 1 ,  301 - 2  respectively disposed in the first and second P-type well regions  112 - 1 ,  112 - 2 . 
     The semiconductor device  1  further includes first and second gate electrodes  221 -G 1  and  221 -G 2 . The first and second gate electrodes  221 -G 1  and  221 -G 2  are spaced apart in a vertical direction of a plane of the substrate  201  and overlapped with the first and second P-type well regions  112 - 1 ,  112 - 2 . The first and second gate electrodes  221 -G 1  and  221 -G 2  are disposed on the field oxide film  120 . 
     In addition, the semiconductor device  1  further includes first and second field plates  222  formed on the first and second field oxide film  120 . The first and second field plates  222  are respectively spaced apart in a vertical direction from and overlapped with the first and second gate electrodes  221 -G 1  and  221 -G 2  and the plane of the substrate. 
     The semiconductor device of the present description may vary the width of the first and second P-type well regions according to various embodiments. As illustrated in  FIG. 9( b ) , the width of the first and second P-type well regions may be set as wider compared to  FIG. 9( a ) , and thus, a breakdown voltage may be adjusted to be larger. That is, if the first and second P-type well regions  112 - 1 ,  112 - 2  are disposed near the first N-type well region  310 , the area of a depletion region is increased much, and thus, a breakdown voltage may be increased. 
       FIG. 10  is a top-view of another embodiment of a semiconductor device. For convenience of description, differences from  FIG. 3  will be mainly described. 
     Referring to  FIG. 10 , a source region  110 -S of the JFET may be formed in the N-type well region  310  and it is extended vertically longer on a side surface of the HVFET  20  different from  FIG. 3 . The first source region  110 ′-S 1  extends from the second gate electrode  221 -G 2  toward the first gate electrode  221 -G 2  in a Y-direction, such that the first source region  110 -S has a length greater than a width. The vertical length of source region  110 -S as well as N-type well region  310  is increased together. If the vertical length SL 1  of the source region  110 -S increases, the current of the JFET increases. The source region  110 -S is formed longer than that of the embodiment of  FIG. 3 , so the current of the JFET in  FIG. 10  is higher than a JFET current in  FIG. 3 . The vertical length of the source region  110 -S of JFET  10  is greater than a vertical length of the common drain region  140 -D. The vertical length of the N-type well region  310  of JFET  10  is also greater than a vertical length of the common drain region  140 -D. The length of the source region is controllable or adjustable than the drain region. The JFET current can be increased by increasing length of the source region. If the length of the source region  110 -S of JFET  10  becomes longer without change in the HVFET  20 , only the amount of current may be increased while a pinch-off voltage remains the same. 
     As shown in  FIG. 10 , an area of the first N-type well region  310  is increased, thus the total N-type dopants are increased. It is required to balance between the N-type dopants and P-type dopants to increase breakdown voltage of HVFET  20 . Thus, the P-type well extension region  112 E is extended toward to the source region of JFET  10 . 
       FIG. 11  is a top-view of another embodiment of a semiconductor device. 
     Referring to  FIG. 11  as an embodiment, a first source region  110 -S 1 , a first drain region  140 -D 1 , a first gate electrode  221 -G 1 , a second gate electrode  221 -G 2 , a first buried impurity layer  130 - 1 , a first N-type well region  310  and a second N-type well region  320  are formed in the semiconductor device  1 . The first source region  110 -S 1  is disposed at a corner of the semiconductor device  1 . The first source region  110 -S 1  is adjacent to the first gate electrode  221 -G 1  rather than the second gate electrode  221 -G 2 . 
     The semiconductor device  1  further comprises a second source region  110 -S 2 , a second drain region  140 -D 2 , a third gate electrode  221 -G 3 , a second buried impurity layer  130 - 2 , a third N-type well region  350  and a fourth N-type well region  360 . The second source region  110 -S 2  is disposed between the second gate electrode  221 -G 2  and the third gate electrode  221 -G 3 . Second source region  110 -S 2  of JFETs  10   b  is formed near the second gate electrode  221 -G 2 . Two JFETs  10   a ,  10   b  are formed in the semiconductor device  1 . It helps that more JFET current flows in the semiconductor device  1 . 
       FIG. 12  is a V-I curve according to the operation of a semiconductor device. 
     When measuring voltages and currents in the semiconductor device  1 ′ of the comparative example (that is, “Old”) illustrated in  FIG. 2 , a well region  310  for inserting a JFET is further implanted into an outer of a HVFET. The well region  310  is extended to outside the HVFET  20 , resulting in decreasing a breakdown voltage at or below 200 V. 
     However, in the case of the semiconductor device (that is, “New”) of the present description, a breakdown voltage is near 1000 V, which is because a charge or dopant amount between an N-type impurity and a P-type impurity is balanced. In contrast, in the case of the semiconductor device (“Old”), a breakdown voltage is at or below 200 V. This indicates that it is important to design the JFET to be placed inside the HVFET  20 . 
       FIG. 13( a )  is a graph of an electric field distribution according to the operation of the semiconductor device of the comparative example, and  FIG. 13( b )  is a graph of an electric field distribution according to the operation of the semiconductor device of the present description. 
       FIG. 13( a )  depicts a contour map of the equipotential electric field line in the case of the comparative example. The electric field lines of the comparative example are locally concentrated at a specific point. This result is caused by the imbalance of the total N-type charge amount and the total P-type charge amount in the HVFET  20 . When the N-type well region  310  including the source region of the JFET is formed outside the HVFET  20 , the RESURF of the HVFET collapses. Thus, the breakdown voltage is lowered to 200 V or less as illustrated in  FIG. 12 . 
     However, in the case of the semiconductor device of the present description (that is, New), the electric field is uniformly distributed as illustrated in  FIG. 13( b ) ; as a result, the breakdown voltage is near 1000 V. This shows that it is important to design the source region  110 -S and the first N-type well region  310  of JFET  10  to be arranged within an area or boundary of the HVFET  20 . 
     A semiconductor device according to the present description allows the JFET and the HVFET to share a drain, thereby improving the integration degree. 
     In addition, a semiconductor device according to the present description allows the JFET to be fully inserted into the HVFET, thereby having advantages in design. 
     In addition, a semiconductor device according to the present description forms a P-type well region of the JFET in an N-type well region in a channel region of the HVFET in a direction toward the channel width, thereby individually controlling the pinch-off feature of the JFET while maintaining an electric feature of the HVFET. 
     In addition, a semiconductor device according to the present description reduces the area of a well region for a source region of the JFET, thereby having an effect that RESURF does not collapse. 
     In addition, a semiconductor device according to the present description reduces the area of a well region of the JFET, and thus, the electric field is uniformly distributed, thereby having a higher breakdown voltage. 
     In addition, a semiconductor device according to the present description operates at a relatively high voltage, thereby having an effect that the JFET may be used at the same voltage region together with the HVFET. 
     In addition, a semiconductor device according to the present description individually controls the area of a source region of the JFET, thereby individually controlling the current amount without any change in pinch-off. 
     While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.