Patent Publication Number: US-7596775-B2

Title: Method for determining a standard cell for IC design

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method for an integrated circuit, and more particularly, to a method for determining a standard cell for an integrated circuit in the IC design flow. 
   2. Description of the Prior Art 
   Integrated circuits (IC) are often implemented by connecting together different types of functional blocks to achieve the desired IC specification. Please refer to  FIG. 1 .  FIG. 1  is a block diagram of IC  10 . The IC  10  includes logic blocks  12 , memory  14 , Input/Output (I/O)  16 , analog/mixed signal blocks  18 , and custom blocks  20 . Some examples of analog/mixed signal blocks include functions of Phase Locked Loops (PLL) and Digital-Analog Converters (DAC). Of these, I/O  16 , memory  14  and analog/mixed signal blocks  18  are typically used as a single pre-formed unit, or hard macro, by the IC designer, whereas some of the other blocks, primarily the logic, are constructed from a set of lower level sub-blocks, or standard cells, to enable a higher degree of customization and optimization. 
   An IC designer typically has numerous options to implement each of the functional blocks to create the best possible design for the IC. With respect to the I/O, memory and/or analog functions, hard macros that implement the required function but which are optimized for higher speed or lower power or smaller area are available, and the IC designer chooses the hard macro best suited to the particular design. 
   Implementing logic functions is much more complex due to the typically large number of standard cells, ranging from tens of thousands to tens of millions, needed to implement the logic functions. Each standard cell is comprised of a predetermined number of transistors coupled together to perform a particular logic function. For example, there are standard cells that perform the functions of NAND, AND, NOR and OR gates, as well as more complicated logic functions such as single bit adders. The IC designer typically has access to different implementations of these low level functions, the different implementations targeted respectively for lower power, higher speed or smaller area. Electronics design automation (EDA) tools are necessary to analyze various implementations and obtain an optimum result when designing complex logic functions. 
   Please refer to  FIG. 2 .  FIG. 2  is a flowchart of IC design according to the prior art. Steps of the IC design are as follows. 
   Step  110 : design RTL (register transfer level), the IC designer programs register transfer level code to describe a logic function requirement of the circuit so as to generate a RTL file; 
   Step  120 : synthesis, using synthesis software to verify the RTL file generated in the step  110 ; the synthesis software is coupled to a library of standard cells; a typical known standard cell library includes a plurality of different cell types, such as AND, NOR, flip-flop and inverter cells, and each cell will be available in several different sizes; the synthesis software analyzes the logic function of the RTL file with an implementation of that function using various types of standard cells that meet the specification; 
   Step  130 : APR (auto place and route), the EDA tool can place and route standard cells for the RTL file that has passed the verification of the synthesis software in the step  120 ; after APR, a netlist is generated including a list of cells required and the necessary connections between them; in addition, the IC designer can choose a suitable standard cell for the IC according to the area constraint and timing constraint; 
   Step  140 : layout, the placement tool uses the information from the library to place the cells so as to minimize the interconnections required by the netlist; a router then draws the wiring between the placed cells to implement the connectivity specified in the netlist so as to complete the layout. 
   In general, each cell will be available in several different sizes, the size referring to the size of the output driver transistors. Although the selection of the correctly sized cell is driven by the design, it is unavoidable that a larger cell (larger output driver transistors) will have a greater delay than a smaller cell. 
   One optimization target for IC design is cost. A smaller area logic circuit will allow a larger number of usable ICs per silicon wafer, reducing the cost of each IC. The IC designer&#39;s goal is to design the IC so that the specifications are met using the smallest possible silicon area. The IC designer is typically provided with multiple variants of each hard macro, the variants showing different trade-offs among the variables of area, speed and power. This extends to standard cells where each logic function, for example an AND gate, has multiple different implementations, the different implementations required for different output drive strength. Standard cells with increased drive strength are typically larger than those with relatively less output drive strength. IC design according to the prior art focus on the cost, so the IC design flow mainly assists IC designers to create the smallest implementation of an IC incorporating the various logic function blocks. However, when the IC designer requires designing a circuit of a higher performance and stability, they do not have any reference information. 
   SUMMARY OF THE INVENTION 
   The present invention provides a method for determining a standard cell for an integrated circuit comprising providing a plurality of standard cells with a same function; generating critical dimensions of each standard cell in a plurality of surroundings; generating a plurality of circuit parameters corresponding to the plurality of surroundings according to the critical dimensions of each standard cell in the plurality of surroundings; subtracting an ideal circuit parameter of each standard cell from each circuit parameter of the standard cell and so as to generate a plurality of differences of circuit parameters; calculating a distribution of the plurality of differences of circuit parameters of each standard cell so as to generate a best cell index of each standard cell; and choosing one standard cell from the plurality of standard cells with the same function for the integrated circuit according to best cell indices of the plurality of standard cells. 
   The present invention further provides a method for determining a standard cell for an integrated circuit comprising providing a plurality of standard cells with a same function; generating a first index according to a layout size of each standard cell; generating a second index according to timing data of each standard cell; generating a third index according to critical dimensions of each standard cell in a plurality of surroundings; determining weight and priority of the first, second and third indexes respectively; and choosing one standard cell from the plurality of standard cells with the same function for the integrated circuit according to the weight or priority of the first, second and third indexes of each standard cell. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of IC. 
       FIG. 2  is a flowchart of IC design according to the prior art. 
       FIG. 3  is a diagram of a standard cell in three different surroundings. 
       FIG. 4  is a flowchart of generating a best cell index according to the present invention. 
       FIG. 5  is a flowchart of the IC design flow according to the present invention. 
       FIG. 6  is a diagram of the standard cells with the same function generating the BCI according to the present invention. 
       FIG. 7  is a diagram of selection of a standard cell for a layout according the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 3 .  FIG. 3  is a diagram of a standard cell in three different surroundings. Integrated circuits (IC) are often implemented by connecting together different types of functional blocks to achieve the desired IC specification. One optimization target for IC design is cost. A smaller area logic circuit will allow a larger number of usable ICs per silicon wafer, reducing the cost of each IC. An IC designer&#39;s goal is to design the IC so that the specifications are met using the smallest possible silicon area. The IC designer typically has numerous options to implement each of the functional blocks to create the best possible design for the IC. In addition, the IC designer can utilize some fundamental standard cells to implement the different functions for the IC with low power consumption, high speed, and small area. Electronics design automation (EDA) tools are necessary to analyze various implementations and obtain an optimum result when designing complex logic functions. The IC designer can choose a suitable standard cell for the IC according to the area constraint and timing constraint. As shown in  FIG. 3 , the standard cell AN4M6N (blank block) is surrounded in three different conditions. The blocks A to H in condition 1 are LDFQRM2N, BUFM10N, DFQRM0N, CKINVM8N, ADHM0N, LAGCEM3N, FIL4N, and OA122M4N respectively. The blocks A to I in condition 2 are SDFEZRM 0 N, HDFM4N, BEMXM2N, ND2M4N, HDFQRM2N, HADFM0N, OR4M0N, BUFM14N, and HSDFCRSM1N respectively. The blocks A to H in condition 3 are AOI32M2N, HSDFQM2N, XOR3M1N, CKAN2M6N, ADHM4N, INVM14N, HADFM2N, and LALM16N respectively. When the standard cell AN4M6N is surrounded in the different conditions, the performance of the standard cell AN4M6N may change. For example, when the intervals in the layout of the standard cell are identical, the delay timing of the stand standard cell is not easy influenced by the surroundings and the standard cell can have a stable performance. However, the layout is large for the identical intervals. The small layout sacrifices a part of intervals so that the delay timing of the stand standard cell will be influenced by the surroundings easily and results in a bad performance. Thus, the present invention utilizes simulators to generate an index according to the critical dimensions of the standard cell for the IC designer reference. 
   Please refer to  FIG. 4 .  FIG. 4  is a flowchart of generating a best cell index according to the present invention. According to the embodiment of the present invention, the flows of generating the best cell index (BCI) for each standard cell are as follows. 
   Step  210 : generating netlists; selecting a plurality of surroundings and utilizing a environment simulator to generate the plurality of netlists corresponding to the plurality of surroundings for a standard cell, each netlist recording the critical dimensions of the standard cell; basically, the more different surroundings there are, the more precisely the index approached to the real condition can be obtained, but the time cost is also increased; thus, the embodiment gives 60 surroundings for an example so as to generate 60 netlists of the condition 1 to the condition 60; 
   Step  220 : generating circuit parameters; the circuit parameters including timing data and power data, taking timing data as an example, utilizing a SPICE (simulation program with integrated circuit emphasis) simulator to generate a plurality of timing data of the standard cell according to the plurality of netlists in the step  210 ; the plurality of timing data are delay timing of the standard cell in the plurality of surroundings; 60 timing data are generated according to the netlists of the condition 1 to the condition 60; 
   Step  230 : calculating data; calculating the differences of the plurality of circuit parameters in the step  220  and an ideal circuit parameter of the standard cell in an ideal condition, so from the 60 timing data the ideal timing data are subtracted respectively so as to obtain 60 timing differences; 
   Step  240 : generating BCI; according to the property of the DELTA function, 60 timing difference in the step  230  are drawn as a chart, where the x-coordinate is a range of the plurality of timing differences and the y-coordinate is number of timing differences in a range; the formula of the best cell index of the standard cell is (Y/N)/X, where Y, N, and X are number of timing differences in a range with greatest number of timing differences, total number of the plurality of timing differences, and a range of the plurality of timing differences respectively. 
   The different circuit parameters are generated according to the critical dimensions of the standard cell, so the BCI corresponding to different circuit parameters can be generated according to the step  210  to step  240 . The BCI for power parameters and timing parameters are BCI 1 , and BCI 2  respectively as following: 
   BCI 1 =(Y 1 /N 1 )/X 1 , where Y 1 , N 1 , and X 1  are number of differences of power data in a range with greatest number of differences of power data, total number of the plurality of differences of power data, and a range of the plurality of differences of power data respectively. 
   BCI 2 =(Y 2 /N 2 )/X 2 , Y 2 , N 2 , and X 2  are number of differences of timing data in a range with greatest number of differences of timing data, total number of the plurality of differences of timing data, and a range of the plurality of differences of timing data respectively. 
   Please refer to  FIG. 5 .  FIG. 5  is a flowchart of the IC design flow according to the present invention. The IC design flow comprises design RTL (register transfer level)  110 , synthesis  120 , APR (auto place and route)  130 , and layout  140 . In the step  110 , the IC designer programs RTL code to describe a logic function requirement of a circuit. In the step  120 , the RTL code generated in the step  110  is verified by synthesis software. In the step  130 , an EDA (electronics design automation) tool places standard cells and routes wires for the RTL code that passed the verification, and the IC designer can choose the standard cells according to the specification of the circuit by himself. In the step  140 , a layout of the circuit is generated. According to the embodiment of the present invention, each standard cell has information of the timing, area, and BCI. The BCI of the present invention is generated according to the critical dimensions of each standard cell, and the BCI can indicate the resistance to the environment. The larger the BCI is of the standard cell, the less the environment can influence the standard cell, which means the standard cell has a stable performance. According to the timing, area, and BCI of each standard cell, if the circuit requires a stable performance, the IC designer can choose a standard cell with a larger BCI, and if the layout size is limited, the IC designer can choose a standard cell with a small area. In addition, the IC designer sets weight and priority of the timing, area, and index according to the requirement of the cost or performance so that the EDA tool can choose a suitable standard cell. For example, if a layout requires a stable performance, the IC designer can set the priority as 2, 3, 1, and the weight as 30%, 20%, 50% for the timing, area, and index respectively; if a layout requires a low cost, the IC designer can set the priority as 3, 1, 2, and the weight as 20%, 50%, 30% for the timing, area, and index respectively. 
   Please refer to  FIG. 6 .  FIG. 6  is a diagram of the standard cells with the same function generating the BCI according to the present invention. In this embodiment, the standard cell AN4M6N has two different layout types, type  1  and type  2 . The area of the type  1  is 5.4, and the area of the type  2  is 5.04. According to the step  210  to the step  240  in the  FIG. 4 , the environment simulator generates  60  conditions for the type  1  and type. Then the SPICE generates 60 timing differences for the type  1  and type  2  respectively. Finally, the 60 timing differences of the type  1  are drawn as the chart  1 , and the 60 timing differences of the type  2  are drawn as the chart  2 . The x-coordinate of the chart is a range of the plurality of timing differences with an interval of 0.07. The y-coordinate is number of timing differences in a range. The BCI of the type  1  and type  2  are as follows according to the BCI formula (Y/N)/X.
 
BCI of type 1=(24/60)/0.21=1.905
 
BCI of type 2=(21/60)/0.35=1.000
 
   As the result of the BCI of the type  1  and type  2 , the BCI of the type  1  is larger than the type  2 , which means the layout of the type  1  has a more stable performance. In addition, comparing the chart  1  and chart  2 , the distribution of the timing difference in the chart  1  is more centralized approached to the DELTA function. Thus, for the two types of the standard cell AN4M6N, the type  1  has a larger area, a high resistance to the environment, and a stable performance, and the type  2  has a small area and a low resistance to the environment. 
   Please refer to  FIG. 7 .  FIG. 7  is a diagram of selection of a standard cell for a layout according the present invention. For the IC designer, the BCI provides a reference index of the performance of the standard cell. When the circuit requires a stable performance, the IC designer can choose a standard cell with a larger BCI. On the other hand, when the layout size is limited but the performance is not requested strictly, the BCI is not an important reference and the area is considered first. As the example of the standard cell AN4M6N in the  FIG. 6 , when using the standard cell AN4M6N in the layout in the  FIG. 7 , the IC designer can choose the type  1  or type  2  for the standard cell AN4M6N. The type  1  has a larger area but a higher resistance to the environment, so the type  1  is a possible choice for an IC with a high performance and a high price. The type  2  has a smaller area but a lower resistance to the environment, so the type  2  is a possible choice for an IC with a limited layout size and a low cost. With the information of the timing, area, and BCI of the standard cell, the IC designer can more easily to choose a standard cell for the layout when designing the circuit. 
   In conclusion, the IC design flow comprises design RTL, synthesis, APR, and layout. In the embodiment of the present invention, the IC designer can choose a suitable standard cell for the layout according to the timing, area, and best cell index (BCI) of each standard cell. The BCI of each standard cell generated by utilizing the environment simulator to generate critical dimensions of the standard cell in a plurality of surroundings, utilizing a SPICE simulator to generate a plurality of circuit parameters corresponding to the plurality of surroundings, calculating the differences of the plurality of circuit parameters and the ideal circuit parameters of the standard cell, and analyzing the distribution of the differences. The BCI of the present invention is generated according to the critical dimensions of the standard cell in the different surroundings, and the BCI can indicate the resistance to the environment of each standard cell. The larger the BCI of the standard cell is, the less the environment can influence the standard cell, which means the standard cell has a stable performance. For the IC designer, the BCI provides a reference index of the performance of the standard cell. When the circuit requires a stable performance, the IC designer can choose a standard cell with a larger BCI. On the other hand, when the layout size is limited but the performance is not requested strictly, the BCI is not an important reference and the area is considered first. In addition, the IC designer sets the weight and priority of the timing, area, and index according to the requirement of the cost or performance so that the EDA tool can choose a suitable standard cell. Thus, the BCI is important information for the IC designer when designing the circuit. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.