Patent Publication Number: US-9419602-B2

Title: Passive drive control circuit for AC current

Description:
BACKGROUND 
     The present disclosure pertains to electrical circuits and particularly to electricity control circuits. 
     SUMMARY 
     The disclosure reveals a circuit that may control current to a load without generating a large amount of electromagnetic interference on main lines of an AC power supply for the load and circuit. Control may be effected with silicon controlled rectifiers (SCRs). For instance, the circuit may implement passive triggering using a capacitor between the anode and the gate of an SCR. By using a sufficiently large capacitor, gate current may be applied during a zero crossing of a waveform of the AC power supply in a passive manner without a need to store energy prior to the zero crossing. The circuit may synchronize SCR triggering with a voltage variation in a clean manner, that is, without generating electromagnetic interference. The circuit may be used with an in-line thermostat. However, the circuit may be used in other ways. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         FIG. 1  is a block diagram of an SRC passive drive circuit; 
         FIG. 2  is a diagram of the passive drive circuit but with more detail than the diagram of  FIG. 1 ; 
         FIG. 3  is a diagram of the circuit like that of  FIG. 2  but with examples of component devices; 
         FIG. 4  is a diagram of an SCR gate triggering signal generator; 
         FIG. 5  is a diagram of waveforms indicating a basis of gate signals for SRCs of the circuit; and 
         FIG. 6  is a diagram of a graph that may show electromagnetic interference caused by an example of the present circuit. 
     
    
    
     DESCRIPTION 
     The present system and approach may incorporate one or more processors, computers, controllers, user interfaces, wireless and/or wire connections, and/or the like, in an implementation described and/or shown herein. 
     This description may provide one or more illustrative and specific examples or ways of implementing the present system and approach. There may be numerous other examples or ways of implementing the system and approach. 
     In an in-line application like a controller in series with a load, electromagnetic conducted emissions (EMI) limits need to be respected (for example, in the U.S.A., see FCC regulations). In order to comply with FCC regulations relative to using SCRs as a switching device in the controller, the triggering approach may have to be controlled in such a way that low EMI noise is emitted on the AC main lines. Usual related art recommended triggering approaches do not necessarily comply with the regulations. Active triggering may be used; however, with each SCR having a different reference for its gate, the circuit can become very complex. 
     The present approach may solve a reference issue of active triggering by doing passive triggering using a capacitor between the anode and the gate of the SCR. Passive triggering may use power from a commercial power supply line. Other approaches may use resistive techniques between the anode and gate to trigger the SCR. These approaches cannot necessarily apply current through the gate at the zero crossing because a voltage drop may be needed in order to generate the current. Such triggering approaches generate non-compliant electromagnetic conducted emission. 
     The current through a capacitor may depend on its size and its variation of voltage which is a maximum at zero crossing of the power supply waveform. So, by using a sufficiently large capacitor, the gate current may be applied at the zero crossing in a passive manner without a need to store the energy prior to a zero crossing. 
     The present driving approach or circuit may be used in any application with voltage variation like an AC supply. It may synchronize the SCR triggering with the voltage variation in a clean manner, i.e., without generating electromagnetic interference. 
     Specifically, the circuit may be used with an in-line thermostat when the controller&#39;s switch is made with SCRs. However, the circuit is not necessarily limited to this application; it can be used in virtually any kind of controller using SCRs on an AC supply. An addition of a power steal module can be useful compliment to the present circuit but it is not necessarily needed for the present SCR circuit. 
       FIG. 1  is a block diagram of an SRC passive drive circuit  10 . A line ( 1 )  11  may connect one side circuit  10  to an AC power source  13 . A line ( 2 )  12  may connect power source  13  to a load  14  which may be an electric heater. Load  14  may be connected to a power steal module  15  which in turn can be connected to circuit  10 . Module  15  may be absent in view of a description of circuit  10 . Line  12  may be connected to the other side of circuit  10 . 
     A first portion  21  of circuit  10  may be noted. Portion  21  may cover a half-wave operation. A second portion  22  may cover the other half-wave operation of circuit  10  as desired. An SCR  16  may have a first terminal at line  17  connected to line  11 , and a second terminal at line  18  connected to line  12 . A control terminal of SCR  16  may be connected by a line  19  to a first terminal of a first switch  23  and a first terminal of a diode  24 . A second terminal of diode  24  may be connected by a line  25  to line  11 . 
     Switch  23  may have a second terminal connected by a line  26  to a first end of a capacitor  27 . A second switch  28  may have a first terminal connected by a line  29  to line  12 . A second end of capacitor  27  may be connected by a line  31  to a second terminal of switch  28 . 
     A control terminal of switch  23  may be connected by a line  32  to a first output of a trigger signal generator  30 . A control terminal of switch  28  may be connected by a line  33  to a second output of trigger signal generator  30 . Signals from generator  30  may turn switches  23  and  28  on and off according to signals provided to control terminals from lines  32  and  33 , respectively. 
     Second portion  22  of circuit  10  may be noted. A second SCR  36  may have a first terminal at a line  37  connected to line  12 , and a second terminal at a line  38  connected to line  11 . A control terminal of SCR  36  may be connected by a line  39  to a first terminal of a third switch  43  and a first terminal of a diode  44 . A second terminal of diode  44  may be connected by a line  45  to line  12 . 
     Switch  43  may have a second terminal connected by a line  46  to a first end of a capacitor  47 . A fourth switch  48  may have a first terminal connected by a line  49  to line  11 . A second end of capacitor  47  may be connected by a line  51  to a second terminal of switch  48 . 
     A control terminal of switch  43  may be connected by line  33  to the second output of trigger signal generator  30 . A control terminal of switch  48  may be connected by a line  32  to a first output of trigger signal generator  30 . Signals from generator  30  may turn switches  43  and  48  on and off according to signals provided to control terminals from lines  33  and  32 , respectively. 
     First portion  21  of circuit  10  may incorporate a transient-voltage suppression device  55  having a first end connected to line  19  and a second end connected by line  57  to line  12 . Second portion  22  of circuit  10  may incorporate a transient-voltage suppression device  56  having a first end connected to line  39  and a second end connected by line  58  to line  11 . 
       FIG. 2  is a diagram of the passive drive circuit  10  but with more detail than the diagram of  FIG. 1 . The switches  23 ,  28 ,  43  and  48  may be N-channel FETs. The capacitors  27  and  47  may be 2.2 microfarads. Diodes  24  and  44  may be Schottky diodes. 
     The MOSFETs  23 ,  28 ,  43  and  48  may be just switches able to use low voltage capacitors  27  and  47 . MOSFETs  23  and  43  could be sufficient to keep the circuit deactivated but capacitors  27  and  47  may need to be high voltage capacitors because of the parasite diode of MOSFETs  23 ,  28 ,  43  and  48 . So, the Vgm signals on lines  32  and  33  may be either high or low with respect to their source pin, to activate or not activate these switches. 
       FIG. 3  is a diagram of circuit  10  like that of  FIG. 2  but with examples of component devices. Examples of components for switches  23 ,  28 ,  43  and  48  may be of model FQS4903. Examples of SCRs  16  and  36  may be of model S6025L. Examples of the 2.2 microfarad capacitors  27  and  47  may be rated at 25 volts and have a 20 percent tolerance. Examples of Schottky diodes  24  and  44  may be of model BAT54 (30 v). Examples of transient-voltage suppression devices (TVSs)  55  and  56  may be of model SMAJ350CA. The examples of the noted components may be substituted with those of other model designations. 
       FIG. 4  is a diagram of an SCR gate triggering signal generator  30  designed to provide Vgm+ and Vgm− signals on lines  32  and  33 , respectively. Vrect on line  71  may be a rectified signal of power source  13 . A signal on line  72  may be that from a CPU drive. The circuit for generator  30  may be regarded as an illustrative example since other circuit designs may suffice for generating signals Vgm+ and Vgm− on lines  32  and  33 . 
       FIG. 5  is a diagram of a graph showing magnitude versus time for waveforms indicating a basis of gate signals for SRCs  16  and  36 . Since nothing appears to happen in the OFF state, just the waveforms of the ON state are shown in the diagram. A V 1  waveform shown by curve  61  may represent the AC power source  13 . A V Line 1 -V int waveform  62  may appear at the node between circuit  10  and the power steal module  15 . So, at each V 1  zero crossing  65 , a V Line 1 -V int waveform  62  may change polarity thus, since I=C dV/dt, the variation of voltage across the capacitors  27  and  47  may generate the necessary current to trigger the SCRs  16  and  36 . Since SCRs conduct only in one direction, the positive variation of current Ig on line  39  as shown by waveform  63  may trigger SCR  36  and the negative variation of current Ig on line  19  as shown by waveform  64  may trigger SCR  16 . 
       FIG. 6  is a diagram of a graph  75  that may show test results for an example circuit  10 , to determine an amount of EMI noise that could be emitted on the AC main lines so as to determine whether the circuit is compliant with pertinent regulations. 
     To recap, a silicon controlled rectifier drive circuit for an in-line thermostat may incorporate a first silicon controlled rectifier (SCR) having a cathode connected to a first line, an anode connected to a second line, and a gate connected to a source of a first field effect transistor (FET); a first capacitor having a first end connected to a drain of the first FET and a second end connected to a drain of a second FET; a second SCR having a cathode connected to the second line, an anode connected to the first line, and a gate connected to a source of a third FET; a second capacitor having a first end connected to a drain of the third FET and a second end connected to a drain of a fourth FET; a first diode having an anode connected to the first line and a cathode connected to the source of the first FET; and a second diode having an anode connected to the second line and a cathode connected to the source of the second FET. 
     The first diode may be a Schottky diode, and the second diode may be a Schottky diode. 
     The circuit may further incorporate a first transient-voltage suppression diode (TVS) having a first end connected to the source of the first FET and a second end connected to the second line, and a second TVS having a first end connected to the source of the third FET and a second end connected to the first line. 
     The first, second, third and fourth FETs may be N-channel FETs. 
     The first, second, third and fourth FETs may be MOSFETs. 
     The first line may be connectable to an AC power source. An electric load may be connectable between the second line and the AC power source. 
     A power steal module may be connectable between the second line and the electric load. 
     The circuit may further incorporate a triggering signal source having a first output connected to a gate of the first FET and a gate of the fourth FET, and having a second output connected to a gate of the second FET and a gate of the third FET. 
     The first and second outputs of the triggering signal source may provide signals that activate and deactivate all FETs simultaneously for a given period. The signals from the first and second outputs may be with respect to a polarity of the FETs. 
     A silicon controlled rectifier (SCR) passive drive system may incorporate a first SCR having a cathode connected to an anode of a first diode, an anode connected to a first terminal of a first switch, and having a gate connected to a first terminal of a second switch and a cathode of the first diode; a second SCR having a cathode connected to an anode of a second diode, the first terminal of the first switch, an anode connected to a first terminal of a third switch and the cathode of the first SCR, and having a gate connected to a first terminal of a fourth switch and a cathode of the second diode; a first capacitor having a first end connected to a second terminal of the first switch and a second end connected to a second terminal of the second switch; and a second capacitor having a first end connected to a second terminal of the third switch and a second end connected to a second terminal of the fourth switch. Each switch may have a control terminal. 
     The system may further incorporate a trigger circuit having a first output connected to the control terminals of the second and third switches and a second output connected to the control terminals of the first and fourth switches. The first output may provide a first trigger signal. The second output may provide a second trigger signal. The first trigger signal and the second trigger signal may be synchronized with respect to polarity. The first, second, third and fourth switches may be field effect transistors (FETs). The first terminals of the FETs may be drains. The second terminals of the FETs may be sources. The control terminals of the FETs may be gates. 
     The first diode may be a Schottky diode. The second diode may be a Schottky diode. 
     The system may further incorporate a first transient-voltage suppression diode having a first end connected to the gate of the first SCR and a second end connected to the anode of the first SCR, and a second transient-voltage suppression diode having a first end connected to the gate of the second SCR and a second end connected to the anode of the second SCR. 
     The cathode of the first SCR may be connected to a first line. The cathode of the second SCR may be connected to one end of a load. A second end of the load may be connected to a second line. The first and second lines may be connectable to an AC power source. 
     A heating control system may incorporate a passive drive mechanism, and a trigger signal generator connected to the passive drive mechanism. The passive drive mechanism may incorporate a first switch having a first terminal, a second terminal connectable to a load, and a control terminal connected to a first output of the trigger signal generator; a capacitor having a first end connected to the first terminal of the first switch and having a second end; a second switch having a first terminal, a second terminal connected to the second end of the capacitor, and a control terminal connected to the trigger signal generator; an SCR having a first terminal connected to the second terminal of the first switch, a second terminal, and a control terminal connected to the first terminal of the second switch; and a diode having a first terminal connected to the second terminal of the SCR, and a second terminal connected to the first terminal of the second switch. 
     The second terminal of the SCR may be connectable to a power source. The load may be connectable to the power source. 
     The system may further incorporate a power steal module connected between the load and the second terminal of the first switch. 
     The first and second switches may be field effect transistors. The first and second terminals of the first switch may be a drain and a source, respectively. The first and second terminals of the second switch may be a source and a drain, respectively. The first and second terminals of the SCR may an anode and a cathode, respectively. The control terminal of the SCR may be a gate. The first terminal of the diode may be an anode and the second terminal may be a cathode. 
     In the present specification, some of the matter may be of a hypothetical or prophetic nature although stated in another manner or tense. 
     Although the present system and/or approach has been described with respect to at least one illustrative example, many variations and modifications will become apparent to those skilled in the art upon reading the specification. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the related art to include all such variations and modifications.