Patent Publication Number: US-9837282-B1

Title: Semiconductor structure

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of application Ser. No. 15/365,967 filed on Dec. 1, 2016, entitled “METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE”, and the entire content of which is hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly, to a semiconductor structure and a method of fabricating the semiconductor structure for improving the critical dimension uniformity. 
     2. Description of the Prior Art 
     In semiconductor manufacturing processes, in order to transfer an integrated circuit onto a semiconductor wafer, the integrated circuits from a database are first designed as a layout pattern and a photomask is then manufactured according to the layout pattern. Patterns on the photomask may then be able to be transferred to the semiconductor wafer. The steps mentioned above may be regarded as a photolithographic process. The photolithographic processes includes many steps, such as a thin film deposition process, a photoresist coating process, an exposure and develop process, and an etching process. The critical dimension (CD) control of the pattern formed by the photolithographic process mentioned above is very important because the layout pattern has to be extremely accurate for forming delicate integrated circuits so as to align with the patterns of the previous and following steps. There are many causes of CD deviations, and etching uniformity of the etching process should be an important one. The etching uniformity may be influenced by many factors, such as etchant condition, layout pattern, and loading effect. Accordingly, the etching process and/or the layout design have to be modified for improving the etching uniformity and the CD control of the semiconductor structure. 
     SUMMARY OF THE INVENTION 
     It is one of the objectives of the present invention to provide a semiconductor structure and a method of fabricating the same. In the method of fabricating the semiconductor structure, a fin cut mask used in a fin cut process includes a compensation pattern corresponding to a region where fin structures are removed by a fin remove process, and a fin bump is formed corresponding to the compensation pattern after the fin cut process and the fin remove process. The compensation pattern may be used to improve etching uniformity of the fin cut process, and the critical dimension control of the semiconductor structure may be enhanced accordingly. 
     A method of forming a semiconductor structure is provided in an embodiment of the present invention. The method includes the following steps. A semiconductor substrate including a plurality of fin structures is provided. Each of the fin structures is elongated in a first direction, and each of the fin structures is partly located in a first region and partly located in a second region adjoining the first region. A fin remove process is performed for removing the fin structures in the second region. A fin cut process is performed with a fin cut mask for cutting at least a part of the fin structures in the first region. The fin cut mask includes a plurality of cut patterns corresponding to a part of the fin structures in the first region and a compensation pattern corresponding to the second region of the semiconductor substrate. A fin bump is formed in the second region and corresponding to the compensation pattern after the fin cut process and the fin remove process. 
     A semiconductor structure is provided in an embodiment of the present invention. The semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region, and each of the fin structures is elongated in the first direction. The first recessed fins are disposed in the second region. Each of the first recessed fins is elongated in the first direction, and a topmost surface of each of the first recessed fins is lower than a topmost surface of each of the fin structures. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each of the first recessed fins and lower than the topmost surface of each of the fin structures. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-15  are schematic drawings illustrating a method of fabricating a semiconductor structure according to a first embodiment of the present invention, wherein 
         FIG. 1  is a flow chart of the method of fabricating the semiconductor structure in this embodiment, 
         FIG. 3  is a schematic drawing in a step subsequent to  FIG. 2 , 
         FIG. 4  is a cross-sectional diagram taken along a line A-A′ in  FIG. 3 , 
         FIG. 5  is a schematic drawing in a step subsequent to  FIG. 3 , 
         FIG. 6  is a cross-sectional diagram taken along a line B-B′ in  FIG. 5 , 
         FIG. 7  is a schematic drawing illustrating a fin cut mask in this embodiment, 
         FIG. 8  is a schematic drawing in a step subsequent to  FIG. 5 , 
         FIG. 9  is a cross-sectional diagram taken along a line C-C′ in  FIG. 8 , 
         FIG. 10  is a flow chart of a process of forming a fin cut mask in this embodiment, 
         FIG. 11  is a schematic drawing illustrating a fin cut layout pattern in this embodiment, 
         FIG. 12  is a schematic drawing illustrating a corrected layout pattern in this embodiment, 
         FIG. 13  is a schematic drawing in a step subsequent to  FIG. 8 , 
         FIG. 14  is a cross-sectional diagram taken along a line D-D′ in  FIG. 13 , and 
         FIG. 15  is a schematic drawing in a step subsequent to  FIG. 14 . 
         FIG. 16  and  FIG. 17  are schematic drawings illustrating a method of fabricating a semiconductor structure according to a second embodiment of the present invention, wherein  FIG. 16  is a flow chart of the method of fabricating the semiconductor structure in this embodiment. 
         FIG. 18  is a schematic drawing illustrating a fin cut mask according to a third embodiment of the present invention. 
         FIG. 19  is a schematic drawing illustrating a fin cut mask according to a fourth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIGS. 1-15 .  FIGS. 1-15  are schematic drawings illustrating a method of fabricating a semiconductor structure according to a first embodiment of the present invention. The method of fabricating the semiconductor structure in this embodiment includes the following steps. As shown in  FIG. 1  and  FIG. 2 , in step S 1 , a semiconductor substrate  10  is provided. The semiconductor substrate  10  in this embodiment may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The semiconductor substrate  10  includes a plurality of fin structures  10 F, and each of the fin structures  10 F includes a fin-shaped structure made of semiconductor material. Each of the fin structures  10 F is elongated in a first direction D 1 , and the fin structures  10 F are repeatedly disposed in a second direction D 2 . The first direction D 1  may be substantially orthogonal to the second direction D 2 , but not limited thereto. The fin structures  10 F may be formed by performing a patterning process, such as a multiple patterning process, to the semiconductor substrate  10 . A first region R 1  and a second region R 2  are defined on the semiconductor substrate  10 . The second region R 2  is located adjoining the first region R 1 . In other words, the first region R 1  and the second region R 2  may be directly connected with each other. Each of the fin structure s  10 F is partly located in the first region R 1  of the semiconductor substrate  10  and partly located in the second region R 2  of the semiconductor substrate  10 . For example, the first region R 1  may be disposed adjoining the second region R 2  in the first direction D 1 , each of the fin structures  10 F may extend from the first region R 1  to the second region R 2  along the first direction D 1 , and one end of each fin structure  10  may be disposed within the second region R 2 , but not limited thereto. 
     As shown in  FIG. 1  and  FIGS. 3-6 , in step S 2 , a fin remove process is performed for removing the fin structures  10 F in the second region R 2 . In some embodiments, the fin remove process may include but is not limited to the following steps. As shown in  FIG. 3  and  FIG. 4 , a first patterned mask layer  20  is formed on the semiconductor substrate  10 . The first pattern mask layer  20  includes a first opening  21  exposing the fin structures  10 F in the second region R 2 . A first etching process  91  with the first pattern mask layer  20  as a mask is performed for removing the fin structures  10 F in the second region R 2 . Specifically, the fin structures  10 F which are not covered by the first pattern mask layer  20  in the first etching process  91  are at least partially removed by the first etching process  91 . In some embodiments, the first patterned mask layer  20  may further include a second opening  22  exposing a part of the fin structures  10 F in the first region R 1 , and the second opening  22  may be elongated in the first direction D 1 , but not limited thereto. As shown in  FIGS. 3-6 , a plurality of recessed fins may be formed by the fin remove process described above. For example, a plurality of first recessed fins  11  may be formed in the second region R 2 , and a second recess fin  12  may be formed in the first region R 1 . Each of the first recessed fins  11  is a residual part of each fin structure  10 F in the second region R 1  after the first etching process  91 , and the second recessed fin  12  is a residual part of one of the fin structures  10 F in the first region R 1  after the first etching process  91 . Therefore, the topmost surface of the first recessed fin  11  and the topmost surface of the second recessed fin  12  are lower than the topmost surface of the fin structure  10 F. 
     As shown in  FIG. 1  and  FIGS. 7-14 , in step S 3 , a fin cut process with a fin cut mask  30 M is performed for cutting at least a part of the fin structures  10 F in the first region R 1 . Specifically, the fin cut process may include but is not limited to the following steps. As shown in  FIGS. 7-9 , a second patterned mask layer  30  is formed on the semiconductor substrate  10 . The second patterned mask layer  30  is defined by the fin cut mask  30 M by such as a photolithographic process. The second mask layer  30  includes a plurality of third openings  31  exposing a part of the fin structures  10 F in the first region R 1  and at least one dummy pattern  32  in the second region R 2 . The third openings  31  in the second patterned mask layer  30  is defined by a plurality of cut patterns  311  in the fin cut mask  30 M, and the dummy pattern  32  of the second mask layer  30  is defined by a compensation pattern  312  in the fin cut mask  30 M. A third region R 3  corresponding to the first region R 1  of the semiconductor substrate  10  and a fourth region R 4  corresponding to the second region R 2  of the semiconductor substrate  10  may be defined on the fin cut mask  30 M. The fin cut mask  30 M includes the cut patterns  311  in the third region R 3  and the compensation pattern  312  in the fourth region R 4 . In other words, the fin cut mask  30 M includes the cut patterns  311  corresponding to a part of the fin structures  10 F in the first region R 1  and the compensation pattern  312  corresponding to the second region R 2  of the semiconductor substrate  10 . In this embodiment, the fin remove process is performed before the fin cut process, and the dummy pattern  32  may overlap a part of the first recessed fins  11 . Additionally, each of the third openings  31  may be elongated in the second direction D 2 , and the dummy pattern  32  may be elongated in the second direction D 2  also, but not limited thereto. The shape of the dummy pattern  32  may be similar to that of the third openings  31  adjacent to the juncture of the first region R 1  and the second region R 2  preferably for improving the etching loading effect near the juncture of the first region R 1  and the second region R 2  in a subsequent etching process. 
     In some embodiments, the process of forming the fin cut mask  30 M may include but is not limited to the following steps. As shown in  FIGS. 7-8  and  FIG. 10-12 , in step S 31 , a fin cut layout pattern  30 L is input into a computer system. The fin cut layout pattern  30 L includes a plurality of slot patterns  301  in the third region R 3  corresponding to the first region R 1 . In step S 32 , an optical proximity correction (OPC) to the fin cut layout pattern  30 L is performed for generating a corrected layout pattern  30 L′. The corrected layout pattern  30 L′ includes a correcting pattern  302  in the fourth region R 4  corresponding to the second region R 2 . The correcting pattern  302  is generated in accordance with at least one of the slot patterns  301  adjacent to the fourth region R 4 . In step S 33 , the corrected layout pattern  30 L′ is output to the fin cut mask  30 M, and the compensation pattern  312  is defined by the correcting pattern  302 . In other words, the compensation pattern  312  on the fin cut mask  30 M is generated by the optical proximity correction, and the compensation pattern  312  is located in the fourth region R 4  corresponding to the second region R 2  of the semiconductor substrate  10  where the fin structures  10 F are going to be removed. 
     As shown in  FIGS. 7-9  and  FIGS. 13-14 , a second etching process  92  with the second pattern mask layer  30  as a mask is per formed for cutting a part of the fin structures  10 F in the first region R 1 . The dummy pattern  32  of the second patterned mask layer  30  covers a part of the first recessed fin  11  during the second etching process  92 , and a fin bump  19  is formed by the second etching process  92  accordingly. The fin bump  19  is formed by removing a part of the first recessed fins  11  which are not covered by the second patterned mask layer  30  in the second etching process  92 . In other words, the fin bump  19  is a part of the first recessed fin  11  covered by the dummy pattern  32  in the second etching process  92  and remains after the second etching process  92 . Therefore, the fin bump  11  is formed in the second region R 2  and corresponding to the compensation pattern  312  after the fin cut process and the fin remove process. Accordingly, the correcting pattern generated in accordance with the slot pattern by the optical proximity correction is printable on the semiconductor substrate  10 . It is worth noting that other correcting patterns may also be generated in accordance with the slot patterns which are not adjacent to the fourth region R 4  by the optical proximity correction, and these correcting patterns may be formed in the third region R 3  and will not be printable on the semiconductor substrate  10 . 
     In some embodiments, an area of the first recessed fins  11  covered by the dummy pattern  32  is smaller than an area of the first recessed fins  11  which are not covered by the dummy pattern  32  for etching most parts of the first recessed fins  11  in the second etching process, but not limited thereto. Additionally, a plurality of recessed fins may also be formed by the second etching process  92 . For example, a plurality of third recessed fins  13  may be formed in the second region R 2 , and a plurality of fourth recess fins  14  may be formed in the first region R 1 . Each of the third recessed fins  13  may be a part of the first recessed fin  11  etched by the second etching process  92 . Each of the fourth recessed fins  14  may be a part of the fin structure  10 F exposed by the third openings  31  and etched by the second etching process  92 . Therefore, the topmost surface of the third recessed fin  13  is lower than the topmost surface of the fourth recessed fin  14 . In this embodiment, the dummy pattern  32  may be used to improve the etching loading effect near the juncture of the first region R 1  and the second region R 2  in the second etching process  92 , and the critical dimension control of the fin structures  10 F near the juncture of the first region R 1  and the second region R 2  may be improved accordingly. 
     As shown in  FIG. 15 , a shallow trench isolation (STI)  40  is formed on the semiconductor substrate  10  after the fin remove process and the fin cut process described above. The shallow trench isolation  40  covers the fin bump  19  and the recessed fins, such as the first recess fin  11  in the second region R 2  and the second recessed fin  12  in the first region R 1 . The fin structures  10 F with the topmost surface higher than the topmost surfaces of the first recess fin  11 , the second recessed fin  12 , and the fin bump  19  may protrude above the level of the topmost surface of the shallow trench isolation  40 . In other words, other subsequently formed parts, such as gate structures, may be formed directly on the fin structures  10 F and may be isolated from the first recess fin  11 , the second recessed fin  12 , and the fin bump  19  by the shallow trench isolation  40 . 
     Please refer to  FIG. 16  and  FIG. 17 .  FIG. 16  and  FIG. 17  are schematic drawings illustrating a method of fabricating a semiconductor structure according to a second embodiment of the present invention. As shown in  FIG. 16  and  FIG. 17 , the difference between the method in this embodiment and the method in the first embodiment is that the fin cut process is performed before the fin remove process in this embodiment. In this embodiment, the dummy pattern  32  of the second patterned mask layer  30  covers a part of the fin structures  10 F in the second region R 2  during the second etching process. An area of the fin structures  10 F covered by the dummy pattern  32  is smaller than an area of the fin structures  10 F in the second region R 2  without being covered by the dummy pattern  32 . 
     Please refer to  FIG. 18  and  FIG. 19 .  FIG. 18  is a schematic drawing illustrating a fin cut mask  31 M according to a third embodiment of the present invention.  FIG. 19  is a schematic drawing illustrating a fin cut mask  32 M according to a fourth embodiment of the present invention. As shown in  FIG. 18 , the difference between the fin cut mask  31 M in the third embodiment and the fin cut mask in the first embodiment is that the fin cut mask  31 M further include a peripheral pattern  313  disposed in the third region R 3  and adjacent to the junction of the third region R 3  and the fourth region R 4 , and there is no pattern disposed in the fourth region R 4  of the fin cut mask  31 M. A shown in  FIG. 18  and  FIG. 19 , the fin cut mask  32 M in the fourth embodiment may further include a plurality of compensation patterns  322  disposed in the fourth region R 4 , and the shape of each of the compensation patterns  322  may be similar to that of the peripheral pattern  313  for improving the etching loading effect near the junction of the first region and the second region in the fin cut process described above. 
     To summarize the above descriptions, in the method of fabricating a semiconductor structure in the present invention, the compensation pattern in the fin cut mask is located corresponding to the second region where the fin structures are removed by the fin remove process. The compensation pattern may be used to improve the etching loading effect near the juncture of the first region and the second region in the second etching process of the fin cut process. The critical dimension control of the fin structures near the juncture of the first region and the second region may be improved accordingly. Additionally, the fin bump is formed corresponding to the compensation pattern after the fin cut process and the fin remove process. Therefore, the correcting pattern of the corrected layout pattern is generated in accordance with the slot pattern by the optical proximity correction, and the correcting pattern is printable on the semiconductor substrate. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.