Patent Publication Number: US-7917316-B2

Title: Test system and computer program for determining threshold voltage variation using a device array

Description:
The Present Application is a Division of U.S. patent application Ser. No. 11/462,186, filed on Aug. 3, 2006 now U.S. Pat. No. 7,423,446. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to device characterization methods and circuits, and more particularly to a circuit for determining threshold voltage variation of devices within an array. 
     2. Description of Related Art 
     Threshold voltage variation has become significant as processes have shrunk. As process technologies have evolved, random doping fluctuation (RDF) has emerged as a dominant and less controllable factor in device parameter variation. RDF has the statistical effect of generating threshold voltage variations, as the number and location of dopant atoms in the channel region can vary significantly from device to device, even though the overall doping density of a process layer for the entire wafer is well-controlled. Threshold voltage “scatter” is a term used to refer to the spread of threshold voltage. 
     Software models can be employed to determine the effects of RDF on circuit performance; however, in order to accurately determine the actual RDF, it is typically necessary to characterize RDF using a test circuit. Threshold voltage variation due to RDF can be characterized by measuring a large number of devices typically arranged in an addressable manner in an array-type test structure. However, full characterization of an array is a time-intensive procedure, since the channel current vs. gate voltage curve must be sampled for each individual device to gather threshold voltage statistics that describe the array. There is no direct measure of threshold voltage in a device; therefore, it is generally necessary to either measure the slope of the gate voltage vs. drain current curve to extrapolate V T  or estimate V T  using a fixed reference current. Either of the above-mentioned methods for measuring threshold voltage require many measurements for each device in the array. 
     For a square array of order N, the required measurement time is N-squared proportional, and for large arrays at present, the measurements typically require cycles of more than a day to complete. As array sizes increase, the result is unacceptable delays in design turn time, especially when determining factors for a process scaling over a large range of options. 
     Therefore, it would be desirable to provide a characterization method and circuit for determining threshold voltage variation within arrays of devices that can reduce the characterization time while accurately providing the threshold voltage statistics for an entire array. 
     SUMMARY OF THE INVENTION 
     The above objectives of reducing characterization time for determining threshold voltage variation within an array is achieved in characterization array and method. 
     The method may be embodied in a computer system executing program instructions for carrying out the steps of the method and may further be embodied in a computer program product containing program instructions in computer-readable form for carrying out the steps of the method. 
     The method fully characterizes at least one device in an array to determine a relationship between the source voltage and threshold voltage for the device. Then, a circuit within the characterization array is enabled to fix the drain-source voltage, gate voltage and drain current for each individual device within the array and the source voltage of each device is sensed and measured. 
     The measured source voltage values are adjusted according to the determined source-threshold voltage relationship for the fully-characterized device, and the statistics of the threshold voltage are computed from the resulting adjusted values. The result is a statistical description of the distribution of threshold voltages for the array. 
     The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1C  are pictorial diagrams depicting various models for threshold voltage that may be used in methods according to embodiments of the present invention. 
         FIG. 2A  is a schematic diagram of a characterization circuit, and  FIG. 2B  is a schematic of a characterization array, in accordance with embodiments of the present invention. 
         FIG. 3  is a pictorial diagram of a wafer test system in which methods in accordance with an embodiment of the present invention are performed. 
         FIG. 4  is a flow chart of a method in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENT 
     The present invention relates to a threshold voltage characterization method performed using a characterization array in accordance with an embodiment of the present invention. The method may be a computer-performed method embodied in a computer program having program instructions for carrying out the method. A characterization array is used in the method and may be controlled by computer to provide a measure of threshold voltage for each device in the array. The variation in threshold voltage over the entire array may then be observed from the measurement data. The method of the present invention dramatically reduces the amount of time to characterize the threshold voltage variation within an array, permitting greater flexibility in design decisions associated with process scaling and other process adjustments and in verification of designs. 
     Referring now to  FIGS. 1A-1C , various definitions of threshold voltage as known in the art are shown in graphs of drain-source current I DS  versus gate-source voltage V GS .  FIG. 1A  shows a threshold voltage (V T ) model in which the threshold voltage is specified as a particular V GS  that produces a predetermined reference current (I REF ) through the channel of the device.  FIG. 1B  shows a threshold voltage model in which the linear (active) region slope of I DS  versus V GS  is projected to a V GS  value that would produce I DS =0 if the active region slope continued to I DS =0. Finally,  FIG. 1C  shows a model of threshold voltage in which the threshold voltage is specified as the point of maximum slope of I DS  versus V GS , which is the point of maximum transconductance g m =dI DS /dV GS . 
     The present invention does not limit the definition of threshold voltage to any particular threshold voltage model, but provides a methodology in which threshold voltage according to any of the above-described models, or any other suitable threshold voltage model, may be measured over an entire array without requiring full characterization of I DS  versus V GS  device behavior for each device in the array. 
     The following equations express the behavior of a Metal-Oxide field effect transistor (MOSFET) over three regions of operation: 
               I   DS     =     {             I   0     ⁢     W   L     ⁢       e   ⁢                   V   GS     -           ⁢     V   T         S   S         ⁢     (     1   -     e       -           ⁢     V     DS   ⁢                   (     kT   /   q     )           )               V   GS     &lt;           ⁢       V   T     ⁢           ⁢     (     Cut   ⁢     -     ⁢   off     )                   k   ⁢     W   L     ⁢     (         (       V   GS     -     V   T       )     ⁢     V   DS       -       V   DS   2     2       )               V   D     &lt;       V   DSAT     ⁢           ⁢     (   Linear   )                     k   ′     ⁢     W   L     ⁢       (       V   GS     -     V   T       )     α     ⁢     (     1   +     λ   ⁢           ⁢     V   DS         )               V   D     &gt;       V   DSAT     ⁢           ⁢     (   Saturation   )                       
In each of the regions described by the equations above, dependency of the channel current I DS  on threshold voltage V T , appears as a dependency on V GS −V T . Therefore, if a measurement is made for each device that enforces a predetermined I DS  and V DS , then any variation in V T  will cause a corresponding and equal change in V GS . If V G  is also fixed, then any variation in V T  will cause a corresponding and opposite change in V S .
 
     Referring now to  FIG. 2A , a characterization circuit in accordance with an embodiment of the present invention is depicted. Transistor N 1  is a device under test for which the threshold voltage V T  is to be determined. Transistor P 1  and current source I 2  form a source-follower that imposes a constant V DS  value across the channel of transistor N 1 , since the amount of current diverted through transistor P 1  will increase as V S  decreases, causing an equal change in V D . Transistor P 1  is generally a thick oxide device having a long channel and operated in the saturation region. Current source I 1  fixes the channel current I DS  through transistor N 1 . A constant voltage V G  is imposed on the gate of transistor N 1 . Therefore, any variation in the threshold voltage (ΔV T ) of device N 1  will appear directly as an opposite change in source voltage (ΔV S ) in the depicted measurement circuit, since ΔV G =0, ΔI DS =0 and according to the above equations, Δ(V GS −ΔV T )=0. 
     Referring now to  FIG. 2B , a characterization array  20  in accordance with an embodiment of the present invention is shown. Characterization array  20  is a test integrated circuit integrated on a die, a wafer kerf or other integrated circuit location that may be experimental only, or occupy one or more die or kerf locations in a production wafer. An array of transistors including device under test DUT is operated in a controlled manner via signals provided by scan latches  22 . Although the exemplary embodiment uses scan latches  22  to apply the control signals, it is understood that registers controlled via a control interface or other suitable circuit may be provided to control the operation of characterization array  20 . Further, it is understood that although the exemplary embodiment supplies signals to external equipment via pads VGP, IDP and VSP, one or more of the external devices used to operate and evaluate device under test DUT may be integrated within characterization array  20 . For example, any or all of voltage source V G , current source I 21  and a voltage measurement circuit for measuring the voltage at pad VSP can be integrated on a wafer including characterization array  20 . 
     Signals provided from scan latches  22  select a unique row and column associated with one of the transistors, e.g., device under test DUT. The selection of a row is made by a logical “1” applied to the gate of one of current steering transistors NI 1 -NI 4  and simultaneously to a gate of a corresponding one of source voltage sense transistors NS 1 -NS 4 . Scan latches  22  are programmed such that only one row is selected at a time, i.e., all gates of transistors NI 1 -NI 4  and NS 1 -NS 4  are set to logical “0” other than the gates corresponding to the selected row. The selection of a column is made by enabling a buffer, e.g., buffer  24  that applies a reference gate voltage provided at pad VGP to the gates of all of the transistors in a column of the transistor array. A corresponding buffer  23  is also enabled and applies the output of amplifier A 1  to the drain of each transistor in the selected column. The gate of a corresponding drain voltage sense transistor ND 1 -ND 4  for the selected column is also set to a logic “1”, and provides a sense path for sensing the drain voltage of a column at the inverting input of amplifier A 1 . Scan latches  22  are programmed such that only one column is selected at a time, i.e., all buffer enable inputs and drain voltage sense transistor ND 1 -ND 4  gates are set to logical “0” other the enable inputs of the buffers corresponding to the selected column and the gate of the corresponding drain voltage sense transistor ND 1 -ND 4 . 
     The source follower circuit described with reference to  FIG. 2A  is included within characterization array  20 , but includes amplifier A 1 , which forces the drain-source voltage (V DS ) to be a constant value for each selected transistor in the array. For example, when transistor DUT is selected by enabling buffers  23  and  24  and transistors ND 4 , NI 2  and NS 2 , transistor ND 4  applies the drain voltage of transistor DUT to the inverting input of amplifier A 1 . Simultaneously, transistor NS 2  applies the source voltage of transistor DUT to the gate of source-follower transistor P 10 , which controls the voltage at the non-inverting input of amplifier A 1 . The feedback loop acts to hold the drain-source voltage of transistor DUT constant by tracking any changes in the source voltage sensed from the selected row and adjusting the drain voltage supplied to the transistors in the column by an equal amount. Only one of the transistors in the array is conducting current at any time. Current provided from the output of A 1  is directed through buffer  23  through the channel of transistor DUT and through transistor NI 2  to an external stable current source I 21 . Since the current output of amplifier A 1  is supplied to the drains of each transistor in a selected column, but only one selected row has a return path enabled via one of transistors NI 1 -NI 4 , only one device is selected for characterization for each valid combination of row and column selection signals provided from scan latches  22 . 
     The above-described characterization array  20  thus provides a mechanism for uniquely selecting each device in the array and sensing changes in the source voltage V S  at pad VSP for a fixed operating point set by the channel current I DS  permitted through pad IDP and the gate voltage V G  applied at pad VGP. By setting different valid selection combinations in scan latches  22 , each transistor in the array is selected and a value of V S  is measured and collected, for example by an external computer-controlled digital voltmeter (DVM). Since the changes in V S  can thereby be characterized for the entire array, the difference between V S  and V T  need only be measured for one device, by fully characterizing the I DS  versus V GS  behavior of one of the transistors in the array, e.g. transistor DUT. 
     The full characterization of transistor DUT can be performed by selecting transistor DUT as described above and varying the value of the voltage applied to pad VGP, with current source I 21  replaced by a current measuring circuit, such as a digital current meter DCM. The behavior of I DS  versus V GS  is then obtained by recording the current produced from pad IDP versus the gate voltage applied to pad VGP minus the source voltage observed at pad VSP. The threshold voltage can be then determined in conformity with one of the models depicted in  FIGS. 1A-1C , or any other suitable threshold voltage model. The source voltage data obtained over the entire array is then be normalized by computing the difference between the source voltage measured for the fully-characterized transistor during the array tests and the threshold voltage determined from the model and subtracting that value from each of the source voltage data points collected during the array measurements. Effectively, the above-described operation is the same as normalizing all source voltages to a particular device by subtracting the source voltage measurement for the particular device to find a deviation value for each device. Then, the threshold voltage for the particular device is determined from full characterization and the threshold voltage for the other devices is determined by subtracting the source voltage deviation for the other device. 
     Referring now to  FIG. 3 , a wafer test system in which a method according to an embodiment of the invention is performed, is shown. A wafer tester  30  includes a boundary scan unit  31  for providing stimulus to a die or kerf circuit  32 A on a wafer under test  32 , via a probe head  33  having electrical test connections  33 A to die  32 A. Wafer tester  30  also includes a digital voltmeter DVM, which may be part of a parametric measurement unit that also includes a programmable voltage source PVS, a programmable current source PCS, and a digital current meter DCM, that are all coupled to die  32 A via probe head  33  electrical test connections  33 A. The output of programmable voltage source is connected to pad VGP, the output of programmable current source PCS is connected to pad IDP and the input of digital voltmeter DVM is connected to pad VSP. 
     A workstation computer  38 , having a processor  36  coupled to a memory  37 , for executing program instructions from memory  37 , wherein the program instructions include program instructions for executing one or more methods in accordance with an embodiment of the present invention, is coupled to wafer tester  30 , whereby the measurements described above are performed and measurements collected and stored in memory  37  and/or other media storage such as a hard disk. A CD-ROM drive  35  provides for import of program instructions in accordance with embodiments of the present invention that are stored on media such as compact disc CD. Workstation computer  38  is also coupled to a graphical display  39  for displaying program output such as distributions of the threshold voltage for devices in the characterization array provided by embodiments of the present invention. Workstation computer  38  is further coupled to input devices such as a mouse  34 B and a keyboard  34 A for receiving user input. Workstation computer may be coupled to a public network such as the Internet, or may be a private network such as the various “intra-nets” and software containing program instructions embodying methods in accordance with embodiments of the present invention may be located on remote computers or locally within workstation computer  38 . Further, workstation computer  38  may be coupled to wafer tester  30  by such a network connection. 
     While the system of  FIG. 3  depicts a configuration suitable for sequential test of a plurality of dies on a wafer, the depicted system is illustrative and not a limitation of the present invention. Probe head  33  may be a multi-die full wafer probe system, or may comprise multiple probe heads for simultaneously testing multiple wafers on a single or multiple die basis. Additionally, while boundary scan control of the characterization array is illustrated, the techniques of the present invention may also be applied to execution of test code from a processor incorporated on wafer  32  with appropriate current and voltage sources and voltage measurement circuitry provided on wafer  32 , as well. The resultant generated display or data exported from workstation computer  38  may take the form of graphical depictions of the threshold voltage variation across the characterization array, or may graphical or numerical statistical distribution information that describes the threshold voltage variation. 
     Referring now to  FIG. 4 , a method in accordance with an embodiment of the invention is depicted in a flowchart. First, one transistor is selected and fully characterized to determine the threshold voltage for that transistor (step  40 ). Next one of the devices (which may be the fully-characterized device) is selected (step  42 ), the gate voltage and drain-source current are forced to predetermined values and the drain voltage is controlled to maintain the drain-source voltage at another predetermined value (step  44 ). The source voltage of the selected device is then sensed and measured (step  46 ) and the measured source voltage is stored in a collection of V S  data points (step  48 ). Until the source voltage has been measured for all devices (decision  50 ), steps  42 - 48  are repeated, selecting a different device each repetition of step  42 . 
     After the source voltage for all of the devices has been measured, the offset between the source voltage measured in step  48  for the fully-characterized device and the threshold voltage determined in step  40  for the fully-characterized device is computed (step  52 ). Next the set of threshold voltages for the entire array is determined by subtracting the offset determined in step  52  from each V S  data point collected in step  48 , yielding the threshold voltage set for the entire array (step  54 ). Finally, statistics of the threshold voltage variation are computed and displayed (step  56 ). 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention.