Patent Publication Number: US-2016224087-A1

Title: Over-current detection circuit and over-current detection system with over-current detection circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Chinese Patent Application No. 201510049401.0 Jan. 31, 2015, the contents of which are incorporated by reference herein. 
     FIELD 
     The subject matter herein generally relates to detection systems. 
     BACKGROUND 
     An over-current detection system may be used to detect whether an over-current is present at an interface. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
         FIG. 1  is a block diagram of one embodiment of an over-current detection system and an interface. 
         FIG. 2  is a circuit diagram of a detection circuit of the over-current detection system and the interface of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure. 
     Several definitions that apply throughout this disclosure will now be presented. 
     The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like. 
     The present disclosure is described in relation to an over-current detection system may be used to detect whether an over-current is at a USB interface. 
       FIG. 1  illustrates an embodiment of an over-current detection system. The over-current detection system is used in a computer. The over-current detection system comprises an over-current detection circuit  100  and a processing module  200 . The over-current detection circuit  100  comprises a power supply module  10 , a control circuit  20 , and a control chip  30 . The control chip  30  is coupled to the processing module  200 . 
     The power supply module  10  comprises a first power supply  11  and a second power supply  13 . The first power supply  11  is configured to supply power to an interface  40  via a fuse F 1 . In one embodiment, the first power supply  11  is configured to provide a 5V voltage, the second power supply  13  is configured to provide a 3V voltage, the fuse F 1  is a recoverable fuse, and the interface  40  is a USB interface. 
     The control circuit  20  comprises a first switch Q 1  and a second switch Q 2 . Each of the first switch Q 1  and the second switch Q 2  comprises a control terminal G, a first connecting terminal S, and a second connecting terminal D. In one embodiment, each of the first switch Q 1  and the second switch Q 2  is an n-channel field effect transistor (FET). 
     The control chip  30  comprises a control pin GPIO and a detection pin OC. The control pin GPIO of the control chip  30  is configured to output a control signal. The detection pin OC of the control chip  30  is configured to output a detection signal. 
     In one embodiment, the control chip  30  is a north bridge chip (PCH). 
     The control chip  30  is configured to output a low level detection signal after detecting an over-current is present at the interface  40 . The processing module  200  is configured to record error information after receiving the low level detection signal. The processing module  200  outputs error information when the computer is in Windows mode. If the computer is in DOS mode or a sleep mode, the processing module  200  will output error information after the computer is in Windows mode next time. 
       FIG. 2  illustrates that the first power supply  11  is coupled to a first node  15  via the fuse F 1 . The first node  15  is grounded via a capacitor C 1 . The first node  15  is coupled to the interface  40 . The first node  15  is coupled to a second node  17  via a first resistor R 1 . The second node  17  is grounded via a second resistor R 2 . The second node  17  is coupled to the first connecting terminal S of the second switch Q 2 . The second node  17  is coupled to the detection pin OC of the control chip  30 . The second connecting terminal D of the second switch Q 2  is grounded. The control terminal G of the second switch Q 2  is coupled to the first connecting terminal S of the first switch Q 1 . The control terminal G of the second switch Q 2  is coupled to the second power supply  13  via a third resistor R 3 . The second connecting terminal D of the first switch Q 1  is grounded. The control terminal G of the first switch Q 1  is coupled to the control pin GPIO of the control chip  30 . The control pin GPIO of the control chip  30  is coupled to the second power supply  13  via a fourth resistor R 4 . 
     A working principle of the over-current detection system is as follows. When an over-current is present at the interface  40 , the fuse F 1  is switched off. The interface  40  is disconnected from the control chip  30 . The first power supply  11  does not supply power to the interface  40 . The control chip  30  outputs a low level detection signal. If the computer is in the Windows mode, the processing module  200  outputs error information after receiving the low level detection signal. If the computer is in the DOS mode or sleep mode, the processing module  200  records error information after receiving the low level detection signal. The control chip  30  outputs a low level control signal after the computer is in the Windows mode next time. The first switch Q 1  is switched off after receiving the low level control signal. The second switch Q 2  is switched on after the first switch Q 1  is switched off. The control chip  30  outputs a low level detection signal after the second switch Q 2  is switched on. The processing module  200  outputs the error information after receiving the low level detection signal. 
     When the interface  40  is in a normal state, the control chip  30  outputs a high level control signal. The first switch Q 1  is switched on after receiving the high level control signal. The second switch Q 2  is switched off after the first switch Q 1  is switched on. The control chip  30  outputs a high level detection signal after the second switch Q 2  is switched off. The processing module  200  does not output the error information. 
     In one embodiment, each control terminal G is a gate terminal, each first connecting terminal S is a source terminal, and each second connecting terminal D is a drain terminal. 
     It is to be understood that even though numerous characteristics and advantages have been set forth in the foregoing description of embodiments, together with details of the structures and functions of the embodiments, the disclosure is illustrative only and changes may be made in detail, including in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.