Patent Publication Number: US-3874915-A

Title: Silicon nitride on silicon oxide coatings for semiconductor devices

Description:
United States Patent 91 Ono et al.  
 [ Apr. 1, 1975 1 SILICON NITRIDE ON SILICON OXIDE COATINGS FOR SEMICONDUCTOR DEVICES [75] Inventors: Minoru Ono, Kodaira; Toshimitu Momoi, Tokyo, both of Japan [73] Assignee: Hitachi, Ltd., Tokyo, Japan [22] Filed: July 10, 1973 [21] Appl. No.: 377,901  
 Related US. Application Data [62] Division of Ser. No. 65,383, Aug. 20, 1970, Pat. No. 3,788,913. which is a division of Ser. No. 701.988, Jan. 31. 1968, abandoned.  
 [30] I Foreign Application Priority Data Feb. 3, 1967 Japan 42-6608 Feb. 3, 1967 Japan 42-6609 [52] US. Cl 117/212, 117/219, 148/187 [51] Int. Cl. Bold 1/18, H011 7/44 [58] Field of Search 117/212; 29/571, 590;  
 [56] References Cited UNITED STATES PATENTS 3,672,983 6/1972 Dewitt et al. 117/212 Primary Examiner-John D. Welsh Attorney, Agent, or F irm---Craig &amp; Antonelli [57] ABSTRACT 9 Claims, 12 Drawing Figures P MEUAPR 11975 3.874.915  
 SHEETlDfZ FIG. /0 PRIOR ART F /6. lb PRIOR ART 3 4 3 SILICON NITRIDE ON SILICON OXIDE COATINGS FOR SEMICONDUCTOR DEVICES The present application is a division of application Ser. No. 65,383, filed Aug. 20, 1970, now US. Pat. No. 3,788,913, which, in turn, is a division of application Ser. No. 701,988, filed Jan. 31, 1968, now abandoned.  
 BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a technique of passivating a semiconductor device with silicon compounds.  
 2. Description of the Prior Art Generally, in a unit circuit element like a transistor, a diode, a semiconductor resistor, a capacitor, etc. or in a so-called integrated semiconductor device like an integrated circuit device composed by assembling many such circuit elements as described above, interconnecting the same and providing outgoing lead terminals thereto, the surfaces thereof and the parts which particularly affect the characteristics thereof, e.g. the PN junction parts, the part nearby which becomes a space charge layer, the region operating due to the diffusion of minority carriers, etc. are covered with a passivation film such as an SiO- film because the characteristics of the elements or devices are altered by the influence of external moisture, conducting materials, ionic materials or the like.  
  Most passivation films which have been formed directly on a semiconductor substrate have been made of silicon dioxide. Silicon dioxide has the advantage of having a small increment of surface electron density. However, if metallic ions, such as sodium ions are present in the film the characteristics of the film are not stable. This instability is caused by the fact thationic materials, such as sodium ions, migrate in the SiO films at a relatively low temperature, for example, above 100C. This migration is remarkably forced or enhanced by the application of an electric field. Thus, the characteristics of the film change during operation at high temperatures. Therefore, it is desirable to form SiO passivation films free of harmful ions such as sodium ions.  
  Recently nitrides, such as Si N,, have been developed as a substitute for SiO It has been found that the increment of the surface electron density of silicon nitride is higher than that for SiO- film. The former films have an increment of surface electron density of 3 X electrons/cm? whereas the latter have an increment of 3 X 10 electrons/cm? However, the migration ofionic materials, such as sodium ions, in the Si N passivation films is quite small.  
  In an attempt to overcome the above-described defects, a semiconductor device comprising a double layer passivation film consisting of a lower layer of silicon oxide and an upper layer of silicon nitride has been proposed. In the production of such a semiconductor device, however, ifa hole is provided in the double film by an etching step, excessive etching or side etching of the lower silicon oxide layer occurs due to a difference in etching rate between the silicon oxide and the silicon nitride, thereby rendering the fabrication of the device difficult. I  
 SUMMARY OF THE INVENTION An object of this invention is to provide a method for producing a novel stabilized semiconductor device covered with silicon compound films.  
  A further object of this invention is to provide a method of preventing the undesired influence caused by the side etching an thereby forming multiple layers of passivation films comprising a silicon oxide film and a silicon nitride film on a semiconductor surface.  
  A yet further object of the invention is to provide a method of producing a semiconductor device having excellent characteristics whose variation is small, wherein an SiO layer, whose tendency to become N type is relatively small, is used as a first passivation layer for the semiconductor, and wherein an Si N layer, in which the tendency of ion movement is relatively small, is formed thereupon as a second passivation layer, the combined passivation layers precluding the entrance of ions, such as Na&#34;, from outside and enabling the surface of the substrate to .have a low tendency to become of N conductivity type.  
  According to an embodiment of this invention, the semiconductor device of the invention is provided in the following way.  
  I. An SiO layer is formed partially on a semiconductor surface. Such an SiO layer is formed by a method wherein the silicon semiconductor surface is oxidized at a high temperature, a method utilizing SiO formed at the time of impurity diffusion, or a method wherein SiO is deposited on a semiconductor by thermally decomposing organo-oxysilane or the like. And then the SiO layer is selectively etched by ordinary methods.  
  2. Then, an Si N, layer is deposited both on the SiO layer and on a substrate surface not covered with the SiO layer by reacting SiH gas and NH gas at about 700C. 1000C., using N gas as a carrier gas.  
  3. A hole for electrode formation is then provided through a portion of the Si N layer which does not cover the SiO; layer. The hole is provided by known photo-etching techniques.  
  4. The semiconductor wafer treated in this way is cut into respective elements to provide a completed semiconductor element.  
 BRIEF DESCRIPTION OF THE DRAWINGS FIGS. la and 1b are sectional diagrams showing a semiconductor wafer according to the prior art.  
  FIGS. 2a to 2c are sectional diagrams showing a semiconductor wafer comprising an MOS type field effect transistor (MOS FET) according to an embodiment of this invention.  
  FIG. 3 is a sectional diagram showing a semiconductor substrate comprising a transistor structure according to another embodiment of the invention.  
  FIGS. 4a to 4d and FIG. 5 are sectionaldiagrams and a plan diagram of a semiconductor device according to a further embodiment of the invention.  
  FIG. 6 is a fragmentary sectional diagram of a modified embodiment of the invention.  
 DESCRIPTION OF THE PREFERRED EMBODIMENTS For a better understanding of this invention, a conventional example will be briefly depicted with reference to the accompanying drawings. As shown in FIG. 1a, according to a conventional example, an SiO layer 2 is formed on a silicon semiconductor substrate 1 and an Si N layer 3 is formed on the SiO layer 2. Thus, a double passivation film structure is composed so as to provide both of the advantages of the two surface stabilization passivation films. Then, the Si N and SiO films are partially etched away with a hydrofluoric acid etchant to form an opening 4 through which an electrode is connected to the silicon semiconductor substrate. However, since the chemical properties of the two films differ from each other, the etching speed is different and the opening 4 is etched excessively in a transverse direction and shaped inside in the region of the SiO layer as shown in the enlarged drawing of FIG. 1b. Accordingly, moisture, etc. is likely to adhere to the gap in the SiO layer and to seriously influence the electrical properties of the device involved. Further, when an electrode is to be established from the semiconductor surface through the passivation film, the electrode may not be connected at the gap part and, even if connected, the connection may become very weak. In a double passivation film of SiO Si N according to this invention, the Si N exhibits a slower etching speed than SiO and the relation of the etching speed in this system is the reverse of the relation of etching speed in a conventionally known SiO glass double passivation film. Thus, etching techniques to be applied to known double passivation films cannot be utilized. Therefore, this invention provides an etching method which is effective when applied in a case where a first film (SiO is etched with an etchant which etches a second film (Si N,) as described hereinabove and the etching speed of the first film is larger than that of the second film. According to this method, a stabilized semiconductor device is provided.&#34;  
  Now, a method of making an MOS FET will be described hereinbelow in conjunction with FIGS. 2a to &#39;26 as an embodiment of this invention.  
  On a P type silicon semiconductor substrate 11, an N type source region 12 and an N type drain region 13 are formed and an SiO film 15 of 1000 2000A is provided on the substrate between these two regions. The film 15 induces an N type Channel 14 on the substrate surface between the regions. After such a body is prepared, silane and ammonia are reacted at about 700 l000C., using N gas as a carrier gas, to form an Si N film 16 of 500 1000A in a thickness on the surface of the film 15 and the substrate surface. This state is shown in FIG. 20. Then, as shown in FIG. 2b, the Si N film provided on a part of the surfaces of the source region l2 and the drain region 13 is exposed to etchant, for example, hydrofluoric acid by using a corrosion resistive mask provided by known photo-resisting techniques, e.g. a sensitized KPR film (KPR is a trade mark of Kodak Co. Ltd.). thus, exposing a portion of the source and drain regions. After the mask material 20 is eliminated, a source electrode 17, a gate electrode 18 and a drain electrode 19 are set. This state is shown in FIG. 20. In the semiconductor passivation film provided in the above method, the SiO film 15 which induces a channel layer and which is the most important part for the electrical characteristics of an MOS field effect transistor has all of its exposed surfaces covered with the Si N film 16. That is, the entire Si0 film is enclosed and shielded from the surrounding atmosphere by the silicon nitride film 16 and the semiconductor substrate 11. Thus, at the part where the passivation film for surface stabilization (Si N film) is partially etched away and at thepart where the semiconductor surface is exposed, moisture or contamination materials are never captured and the electrical characteristics of the element can be made quite stable.  
  In the MOS FET shown in FIG. 20, the leakage current between the source and drain regions may flow through the induced channel layer 10 below the single layer of Si N However, the leakage current can be reduced substantially to zero by forming the gate electrode 18 and the channel layer 14 in a ring form surrounding the drain region 13, as known in a ring-gate type MOS FET. It is further to be noted that it is possible in this embodiment to make parts for setting electrodes on the source and drain regions into a single layer only and to form all the other parts into a double layer structure consisting of an SiO film and an Si N film.  
 Now, another embodiment of the invention will be described below with reference to FIG. 3. This embodiment is provided by applying this invention to the man ufacture of a surface stabilized bipolar transistor. A surface passivation film 22 of 3000 5000 A consisting of SiO is formed to cover and passivate PN junction terminations exposed on the surface of a semiconductor substrate 21 wherein PN junctions 27 and 28 of an emitter and a collector are formed, and on the other surface parts of the semiconductor, a surface passivation film 23 of 3000 4000A consisting of Si N is provided. Then, parts of the Si N film 23 necessary for electrode connections are eliminated and electrodes 24, 25 and 26 are connected thereto. In such a transistor, if an Si N film is adhered directly to the termination of the PN junction, a strong N type channel layer is induced in the semiconductive surface at the vicinity of the PN junction termination by the Si N film, and  
 thereby the withstand voltage of the PN junction or the current amplification factor is lowered remarkably.  
 However, when this invention is applied as in this embodiment, the damage of inducing a strong N-type channel is reduced and a semiconductor device whose electrical characteristics are quite stable can be obtained. It is needless to mention that this technique is not restricted to transistors, but can be applied to the surface stabilization of diodes, etc. to provide the same effect. Though the stability of the characteristics of the semiconductor element as shown in FIG. 3 is remarkably improved compared with that of the element covered only with a SiO layer, an small variation of the characteristics is still observed during a long, hightemperature operation. An investigation of the cause therefor indicates that since the SiO film is exposed on the side surfaces of the element when the semiconductor wafer is cut or separated by etching into elements, ionic materials, such as Na enter through these parts especially in a high temperature state, move to the adjacent operating parts, such as the PN junction, and change the characteristics of the element. Therefore, in the preferred embodiments to be described below, a second film (Si N in this embodiment) is formed on the first film in a way that the first film (SiO in the embodiment) of the double film which contacts the semiconductor substrate may not be exposed at all. Now,  
 such an embodiment will be described in conjunction with the accompanying drawings.  
 FIG. 4a shows a semiconductor wafer 31 prepared for the application of this invention and N type base layers 32 and 42, P type emitter layers 33 and 43 and a I type annular layer 34 are formed by applying a diffusion technique to a P type semiconductor wafer 31 which becomes a collector. Reference numeral 35 designates an SiO layer having a thickness of about 5000 A, which can be formed by various methods as described hereinabove, but in this embodiment, it indicates an SiO layer provided by oxidizing the semiconductor surface at a high temperature. Such an SiO layer includes a phospho-silicate glass layer thermally produced at the time of the diffusion treatment.  
  FIG. 4b shows the wafer shown in FIG. 4a in an enlarged way. The same figure shows the state after parts 36 and 36&#39; for placing an electrode in an SiO layer 35 and a part 37 for separating the wafer into respective elements are etched away. The overall treatment was done with a single etching treatment according to a known photo etching method called the photoresist mask etching method.  
  Then, as shown in FIG. 4c, an Si N, layer 38, a second layer, having a thickness of about 4000 A is formed on the remaining SiO layer and on the exposed semiconductor surface by such method and openings 39 and 39 for electrode formation, i.e. exposed semiconductor parts, are formed in that part of the Si N layer which does not cover the SiO layer by a similar photoetching method. Since the Si N is difficult to etch, a fairly rigid material must be prepared as a mask material. Thus, a suitable mask may include a chromium layer (not shown) formed on the Si N layer 38 in advance, the chromium layer being treated by a photoetching technique. The Si N, layer may then be etched by using the chromium layer as a mask. In this case, it is also possible to etch the other wafer part not covered with the SiO layer, i.e. the Si N layer 38 on the part to be cut as shown by a ditch 40 in FIG. 4c. Then, electrodes 41a and 41b, made e.g. of A1, are formed on the exposed semiconductor surfaces of the wafer.  
  The upper part of the wafer is shown in FIG. 5. Ditches 40 are formed between the respective element parts on the wafer and thus, the apparent representation of the positions for separation is provided.  
  Then, the wafer is cut at the ditch parts by a mechanical or chemical method, etc. to provide respective completed elements as shown in FIG. 4a. In this case, by forming electrode materials in the ditch parts 40 at the time of forming the electrodes 41a and 41b, the possibility of Si powder generated in the process of wafer cutting adhering to the wafer surface (generally, it adheres electrostatically) and damaging the passivation film can be prevented. Further, if such electrode materials have the property of preventing a channel layer from being induced on the semiconductor surface part (the Al prevents an N type channel), the formation of the annular ring diffused layer can be dispensed with.  
  As is evident from the foregoing description of the invention, when the surface is to be protected with a multiple passivation film according to this invention, the inner passivation film, Si0 film, is not exposed outside, and a complete surface passivation film is provided.  
  Therefore, it is evident that this invention can be applied to the formation of a double or a multiple passivation film composed of known materials, etc. in addition to the SiO -Si N double passivation film described hereinabove. It is further possible to derive electrodes, as shown in FIG. 6, by providing an opening in an SiO film 53, deriving a first electrode 55 from the surface of a semiconductive substrate 51 over the SiO film 53 through said opening, forming an Si N, film 54 in a way to expose the first electrode 55 on the SiO film 53 and connecting a second electrode 56 to the first electrode 55 through this opening. In addition, since the SiO film 53 is perfectly covered with the Si N, film 54 there is no danger that Na ions will enter into the SiO film from external sources.  
 We claim:  
  1. A method of making a semiconductor device comprising the steps of:  
 a. preparing a semiconductor substrate comprising a principal surface having a predetermined portion thereof covered with a first insulating film consisting mainly of silicon oxide,  
 b. covering at least a portion of the exposed surface of said first film and at least a portion of said principal surface not covered with the first film with a second insulating film consisting mainly of silicon nitride,  
 c. completely covering said first and second films, except for a portion of said second film directly contacting the surface of said semiconductor substrate at a location spaced from the portion of said surface covered with said first insulating film, with a corrosion resistive mask,  
 d. exposing the combination thus composed to an etchant to partially etch away the portion of said second insulating film not covered with said corrosion resistive mask, and  
 e. introducing a conductivity type impurity into said substrate using said first insulating film as a selective mask.  
 2. A method for manufacturing a semiconductor device, comprising the steps of:  
 covering a major surface of a semiconductor substrate with a first oxide film having a hole extending to the major surface;  
 introducing a conductivity type determining impurity into said substrate through said hole to form a diffused region defining with the adjacent semiconductor material a PN junction terminating at the portion of said major surface covered with said first oxide film;  
 forming a second oxide film to cover said diffused region in said hole;  
 removing a portion of said first oxide film and at least a portion of said second oxide film so that the exposed major surface of said semiconductor substrate completely surrounds the remaining portion of the first oxide film which covers the entire edge portion of said PN junction and so that a portion of said diffused region is exposed;  
 depositing an insulating film consisting substantially of silicon nitride on said semiconductor substrate to completely cover the exposed surfaces of said oxide films, the exposed surface of said diffused region and the exposed portion of said major surface surrounding said first oxide film, thereby entirely shielding the remaining oxide films from the surrounding atmosphere;  
 forming in said insulating film an opening extending to said diffused region; and  
 connecting an electrode to said diffused region through said opening.  
  3. A method for manufacturing semiconductor devices, comprising the steps of:  
 preparing a semiconductor substrate including a plurality of semiconductor regions formed in a major surface of said substrate, each of said plurality of semiconductor regions defining with the adjacent semiconductor material a PN junction terminating at the major surface of said substrate;  
 forming an oxide film on said major surface of said semiconductor substrate to completely cover the exposed edge portions of said PN junctions;  
 removing selected portions of said oxide film to expose each of said plurality of semiconductor regions and a circumferential portion of the major surface completely surrounding a portion of said major surface in which said plurality of semiconductor regions are formed, the edge portions of said PN junctions completely covered with the remaining oxide film;  
 covering with an insulating film consisting substantially of silicon nitride the exposed surfaces of said plurality of semiconductor regions, the exposed circumferential portion of said major surface and the entire exposed surface of the oxide film covering the portion of said major surface surrounded by said exposed circumferential portion of the major surface;  
 forming a plurality of holes respectively extending to said semiconductor regions in the portions of said insulating film directly contacting the respective 3 semiconductor regions; and  
 connecting a contact to each respective semiconductor region through said plurality of holes. 4. A method for manufacturing semiconductor devices, comprising the steps of:  
 forming a semiconductor wafer having a plurality of semiconductor portions spaced from each other and an oxide film covering a principal surface of said semiconductor wafer, each of said semiconductor portions including at least one PN junction terminating at the principal surface of the wafer;  
 forming holes respectively extending to said semiconductor portions and ditches exposing said principal surface so as to divide the oxide film into a plurality of islands, the islands of the oxide film being spaced from each other and covering said semiconductor portions, respectively; covering, with an insulating film consisting essentially of silicon nitride, the entire exposed surfaces of said semiconductor portions in said holes, the entire exposed portions of said principal surface in said ditches and the entire exposed surfaces of said oxide film; forming a plurality of further holes respectively extending to said semiconductor portions in the portions of said insulating film directly contacting with the respective semiconductor portions;  
 connecting contacts to said semiconductor portions through said further holes, respectively; and  
 dividing the semiconductor wafer at said ditches, in  
 which said insulating film directly contacts the surface of the wafer, thereby forming separate semiconductor devices.  
  5. A method according to claim 2, wherein the step of forming the plurality of holes in the portions of said insulating film&#39; directly contacting the respective semiconductor regions includes completely covering said insulating film, except for the portions thereof where said holes are to be located, with a corrosion resistive mask, and exposing the thus covered insulating film to an etchant to partially etch away the portion of said insulating film not covered with said corrosion resistive mask.  
 6. A method according to claim 3, wherein the step an etchant to partially etch away the portion of said insulating film not covered with said corrosion resistive mask.  
  7. A method according to claim 4, wherein the step of forming the plurality of further holes in the portions of said insulating film directly contacting the respective semiconductor regions includes completely covering said insulating film except for the portions thereof where said holes are to be located, with a corrosion resistive mask, and exposing the thus covered insulating film to an etchant to partially etch away the portion of said insulating film not covered with said corrosion resistive mask.  
 8. A method of manufacturing a semiconductor device comprising the steps of:  
 a. forming in a semiconductor substrate a semiconductor region of a conductivity type opposite to the substrate so as to define a PN junction terminating at a principal surface of the substrate, the termination of said PN junction and the vicinity thereof being covered with a first insulating film consisting essentially of silicon dioxide;  
 b. forming a hole in the first insulating film so as to expose a surface portion of said semiconductor region;  
 c. covering the entire upper surface of said first insulating film, the entire side walls of said hole and the exposed surface portion of said semiconductor region with a second insulating film consisting essentially of silicon nitride; d. completely covering said second insulating film with a corrosion resistive mask;  
 e. selectively removing a portion of said second insulating film covering said semiconductor region so as to again expose a surface portion of said semiductor region of a conductivity type opposite to the I substrate, so as to define a PN junction terminating at a principal surface of the substrate, the termination of said PN junction and the vicinity thereof being coveredwith a first insulating film consisting essentially of silicon dioxide;  
 b. forming a hole in the first insulating film so as to I expose a surface portion of said semiconductor region;  
 c. covering the entire upper surface of said first insulating film, the entire side walls of said hole and the exposed surface portion of said semiconductor ree. selectively removing a portion of said second insu- S seconfi lnsulatmg film Conslstmg essenlating film which is not covered with said corrosion of slhco mmde; resistive mask, so as to expose the semiconductor d. completely covering said insulating films, except t for a portion of said second film directly contacting m said hole and the surface of the semiconductor substrate at a Provldmg an electrode to the exposed semiconduccation in said hole spaced from said first film, with Surface in Said 0 6 l a corrosion resistive mask;