Patent Publication Number: US-6983551-B2

Title: Interconnecting substrates for electrical coupling of microelectronic components

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 09/644,801, filed on Aug. 23, 2000 now U.S. Pat. No. 6,483,044. 
    
    
     TECHNICAL FIELD 
     The present invention relates to microelectronic devices and methods for manufacturing and using microelectronic devices. More specifically, several aspects of the invention are directed toward interconnecting substrates that electrically couple microelectronic components, such as packaged microelectronic devices, to other components. 
     BACKGROUND 
     Printed circuit boards (PCBs) and interposing substrates are types of interconnecting substrates for electrically connecting microelectronic components together. In a typical application used in semiconductor manufacturing, a packaged microelectronic device includes an interconnecting substrate, a microelectronic die attached to the interconnecting substrate, and a protective casing covering the die. Such packaged microelectronic devices are generally known as Flip-Chip, Chip-On-Board, or Board-On-Chip devices. The interconnecting, substrates used in packaged microelectronic devices typically include a plurality of contact elements coupled to bond-pads on the die, a plurality of ball-pads on at least one side of the interconnecting substrate, and conductive traces coupling each contact element to a corresponding ball-pad. Packaged microelectronic devices using an interconnecting substrate are generally surface mounted to another interconnecting substrate, such as a PCB, in the fabrication of Printed Circuit Assemblies (PCAs). 
     The competitive semiconductor manufacturing and printed circuit assembly industries are continually striving to miniaturize the microelectronic devices and the PCAs for use in laptop computers, hand-held computers, and communication products. Additionally, there is a strong drive to increase the operating frequencies of the microelectronic devices. The trends of miniaturization and high operating frequencies further drive the need to increase the density of traces and contacts on PCBs and other types of interconnecting substrates. Therefore, several high frequency packaged microelectronic devices require shielding to protect the integrity of the signals on the interconnecting substrate from capacitive coupling and/or inductive coupling. 
     In conventional PCB technologies, the signal integrity is protected by providing ground and power planes in the interconnecting substrates. Such use of ground and power planes in conventional interconnecting substrates has been limited to robust PCBs that are fairly thick. The miniaturization of components, however, often requires very thin interconnecting substrates for packaging microelectronic devices. One manufacturing concern of using ground and power planes in such thin interconnecting substrates is that high-temperature processing can cause voids to form in the substrates or delamination of the substrates. The substrates may also warp during high temperature processing. 
     To resolve the problems of voids, delamination and warping, the interconnecting substrates are typically preheated to remove moisture from the dielectric materials. One drawback of preheating the interconnecting substrates is that it is time-consuming and increases the cost of packaging microelectronic devices and fabricating PCAs. Additionally, although such preheating techniques are generally satisfactory for removing a sufficient amount of moisture from low-density, thick PCBs, preheating may still cause unacceptable voids or delamination in thin, high-density interconnecting substrates used in packaged microelectronic devices. The thicker conventional PCBs can have some voids and/or delamination without affecting the performance of the PCAs because they have sufficient structural integrity to prevent warpage and lower densities that are not likely affected by voids or slight delamination. In contrast to thick, low-density PCBs, the thin interconnecting substrates that are used in highly miniaturized applications may not have the structural integrity or sufficient open real estate to withstand preheating or subsequent high-temperature processing even after being preheated. Therefore, there is a need to develop a thin, high-density interconnecting substrate that can withstand high-temperature processes and is suitable for high density, high frequency applications. 
     SUMMARY 
     The present invention is directed toward interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer. The interconnecting substrate also has at least one vent through at least one of the first conductive stratum, the second conductive stratum, and/or the dielectric layer. The vent is configured to direct moisture away from the dielectric layer, and thus the vent can be a moisture release element that allows moisture to escape from the dielectric layer during high temperature processing. 
     The first conductive stratum can be a ground plane, and the second conductive stratum can be a power plane. Additionally, the vents can comprise holes and/or channels in the first and second conductive stratums. The holes and/or channels can be superimposed with one another, or they can be offset from one another. The vents are located in areas of the first and second conductive stratums that will not affect the electrical integrity of the conductive stratums or the internal wiring of the interconnecting substrate. For example, locations and configurations of the holes, channels or other types of vents can be designed so that they do not adversely affect the signal integrity. 
     In another aspect of the invention, a method of manufacturing an interconnecting substrate comprises constructing an internal conductive core by disposing a first conductive stratum on a first surface of a dielectric layer; forming at least one vent in at least one of the first conductive stratum and/or the dielectric layer so that the vent is configured to direct moisture away from the dielectric layer; and laminating the internal conductive core between a first external layer and a second external layer. The process of constructing the internal conductive core can also include disposing a second conductive stratum on a second surface of the dielectric layer that is opposite the first surface. The vents can be formed in the first conductive stratum and/or the second conductive stratum by etching holes, channels, and/or other openings through the first and/or second conductive stratums. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional isometric view of a portion of an interconnecting substrate in accordance with an embodiment of the invention. 
         FIG. 2  is a cross-sectional isometric view of a portion of an interconnecting substrate in accordance with another embodiment of the invention. 
         FIG. 3  is a cross-sectional isometric view of an interconnecting substrate in accordance with yet another embodiment of the invention. 
         FIG. 4  is a cross-sectional isometric view of an interconnecting substrate in accordance with still another embodiment of the invention. 
         FIG. 5  is a top isometric view having a cut-away portion of a packaged microelectronic device and an interconnecting substrate in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure describes interconnecting substrates used in the manufacturing of microelectronic devices and PCAs, packaged microelectronic devices having interconnecting substrates, and methods for making and using such interconnecting substrates. Many specific details of certain embodiments of the invention are set forth in the following description and in  FIGS. 1–5  to provide a thorough understanding of these embodiments. One skilled in the art, however, will understand that the present invention may have additional embodiments, or that the invention may be practiced without several of the details described below. 
       FIG. 1  is a cross-sectional top isometric view illustrating a portion of an interconnecting substrate  100  in accordance with one embodiment of the invention. In this embodiment, the interconnecting substrate  100  has a first external layer  110 , a second external layer  112 , and a conductive core  120  laminated between the first and second external layers  110 / 112 . The first and second external,layers  110 / 112  can be composed of a thermoplastic resin (e.g., a polyether sulfone), a polyimide film, or other suitable dielectric materials. The first external layer  110  has a first external surface  113 , and the second external layer  112  has a second external surface  115 . 
     The conductive core  120  includes a dielectric separator layer  122  having a first surface  123  and a second surface  124 . The dielectric separator layer  122  is typically composed of a material having a high resistivity, such as BT epoxy, FR-4, polyimide, cyanate ester, fluoropolymer composites (e.g., Roger&#39;s RO-2800), or epoxy/nonwoven aramids (e.g, DuPont Thermount). These materials provide good dielectric properties, but they absorb enough moisture to affect the structural and electrical integrity of the substrate  100  during manufacturing processes or field operations. The conductive core  120  also includes at least a first conductive stratum  126 , and the conductive core  120  preferably also includes a second conductive stratum  128 . The first conductive stratum  126  can be disposed on the first surface  123  of the separator layer  122 , and the second conductive stratum  128  can be disposed on the second surface  124  of the separator layer  122 . The first and second conductive stratums  126 / 128  are preferably composed of highly conductive materials. For example, the first and second conductive stratums  126 / 128  are generally composed of copper, but silver, gold, aluminum, tungsten, alloys of these metals, or other conductive materials can also be used. 
     The interconnecting substrate  100  can be a very thin, high-density unit for coupling a memory device, processor, or other high-frequency microelectronic device to a larger printed circuit board or another component. The interconnecting substrate  100 , for example, can have a thickness from the first external surface  113  of the first external layer  110  to the second external surface  115  of the second external layer  112  of approximately 0.01 to 0.25 millimeters, but it can also have a larger thickness. The first and second conductive stratums  126 / 128  can be ground and power planes, respectively. The first conductive stratum  126  can accordingly be connected to a ground potential, and the second conductive stratum  128  can accordingly be connected to a power potential. Unlike internal wiring within the interconnecting substrate  100  or on the first and second external surfaces  113 / 115 , the first conductive stratum  126  and the second conductive stratum  128  are generally substantially contiguous layers having a surface area approximately equal to the total surface area of the first and second external surfaces  113 / 115 . 
     The interconnecting substrate  100  can also include a plurality of conductive lines. In one embodiment, the interconnecting substrate  100  has a plurality of signal lines  140  extending through the dielectric separator layer  122 . The interconnecting substrate  100  can also include contacts  142  and surface lines  144 . The contacts  142  can extend through the first and second external layers  110 / 112 , and the surface lines  144  can extend across the first external surface  113  and/or the second external surface  115 . For purposes of simplicity, only a single contact line  142  is shown extending between the first conductive stratum  126  and a surface line  144  on the first external surface  113  of the first external layer  110 . It will be appreciated that the configuration of the signal lines  140 , contact lines  142 , and surface lines  144  are designed according to the specific uses of the interconnecting substrate  100 , and thus the invention can include virtually any configuration of such conductive lines. The contacts  142  or vias can couple the ground plane defined by the first conductive stratum  126  and/or the power plane defined by the second conductive stratum  128  to surface lines  144  on one or both of the first and/or second external surfaces  113 / 115 , as is known in the art of PCB manufacturing and design. 
     The interconnecting substrate  100  also includes at least one vent  160  through at least one of the first conductive stratum  126  and/or the second conductive stratum  128 . In the embodiment shown in  FIG. 1 , the interconnecting substrate  100  includes a first vent  160  in the first conductive stratum  126  and a second vent  160  in the second conductive stratum  128 . The first and second vents  160  shown in  FIG. 1  are holes that extend through each of the first and second conductive stratums  126 / 128 . Additionally, the vents  160  shown in  FIG. 1  are superimposed with one another such that the first vent  160  in the first conductive stratum  126  is aligned with the second vent  160  in the second conductive stratum  128 . The vents  160  are configured to direct moisture away from the dielectric layer and into the first and second external layers  110  and  112 . As such, the conductive stratums  126 / 128  do not act as moisture barriers that entrap moisture absorbed by the dielectric layer  122 . 
     The interconnecting substrate  100  can be fabricated by constructing the internal conductive core  120  and then laminating the first and second external layers  110  and  112  to the conductive core  120 . In one embodiment, the conductive core  120  is constructed by disposing the first conductive stratum  126  on the first surface  123  of the dielectric layer  122 . In applications that also include the second conductive stratum  128 , constructing the internal conductive core  120  can further include disposing the second conductive stratum  128  on the second surface  124  of the dielectric layer  122 . The vents  160  can be formed in the first conductive stratum  126  and the second conductive stratum  128  by etching the holes through the first and second conductive stratums  126 / 128  using photolithographic processes known in the semiconductor manufacturing arts. After forming the vents  160 , the first and second external layers  110  and  112  can be laminated to the conductive core  120  by aligning the first external layer  110  with the first conductive stratum  126  and aligning the second external layer  112  with the second conductive stratum  128 . The first external layer  110 , the second external layer  112 , and the conductive core  120  are then pressed together using techniques known in the PCB fabricating arts to laminate the first and second external layers  110  and  112  to the conductive core  120 . After laminating the first and second external layers  110  and  112  to the conductive core  120 , the vents  160  are at least partially filled with material from the first layer  110 , the second layer  112 , and/or the dielectric layer  112  (shown in broken lines in  FIG. 1 ). 
     Several embodiments of the interconnecting substrate  100  shown in  FIG. 1  are particularly well suited for high temperature processing of very thin, multi-layer substrates used in packaging high frequency microelectronic dies. In a typical application, the interconnecting substrate  100  is subject to elevated temperatures in solder reflow and/or burn-in processes. During such high temperature processing, moisture absorbed by the dielectric layer  122  expands and creates an internal pressure gradient within the interconnecting substrate  100 . As the moisture expands, it can pass through the vents  160  in the first and second conductive stratums  126 / 128  and into the first and second external layers  110 / 112  (shown by arrows M). The moisture then passes through the first and second external layers  110 / 112  to dissipate in the external environment. The vents  160  accordingly direct the moisture away from the dielectric layer  122  to the relieve the pressure gradient in the interconnecting substrate  100  caused by expanding moisture. 
     Several embodiments of the interconnecting substrate  100  are expected to reduce the occurrences of voids and/or delamination in very thin, multi-layer substrates that have a metal ground plane and/or a metal power plane. In conventional multi-layer interconnecting substrates, the ground planes and power planes are contiguous layers that do not have openings designed or otherwise configured to direct moisture away from the dielectric layer. The contiguous ground and power planes in conventional interconnecting substrates are thus moisture barriers that force expanding moisture in conventional multi-layer substrates to travel to the edge of the interconnecting substrate (arrow T) to relieve pressure within the interconnecting substrate. It will be appreciated that the distance along the path of arrow T is much greater than the distance along the path of arrows M. As a result, several embodiments of the interconnecting substrate  100  dissipate the expanding moisture in a manner that limits the pressure gradient within the interconnecting substrate  100  to inhibit the formation of voids or the delamination of the interconnecting substrate  100 . The interconnecting substrate  100 , therefore, is expected to be particularly useful for Chip-On-Board, Board-On-Chip, Flip-Chip, and other types of microelectronic device packaging that use very thin interconnecting substrates for high frequency devices. 
     Several embodiments of the interconnecting substrate  100  are also expected to be well suited for packaging microelectronic dies that operate at high frequencies. One manufacturing concern of producing high frequency microelectronic devices is that the high density of the conductive lines and pads on the interconnecting substrate can impair the integrity of the signals because of capacitive coupling and/or inductive coupling. Several embodiments of the interconnecting substrate  100  are expected to shield the conductive components on such high-density interconnecting substrates by providing a ground plane (e.g., the first conductive stratum  126 ) and/or or a power plane (e.g., the second conductive stratum  128 ). As such, several embodiments of the interconnecting substrate  100  are particularly useful for packaging memory devices and processors that operate at frequencies over 200 MHz. 
       FIG. 2  is a cross-sectional isometric view of an interconnecting substrate  200  in accordance with another embodiment of the invention. Several components of the interconnecting substrate  200  are similar to the components of the interconnecting substrate  100  illustrated above in  FIG. 1 , and thus like reference numbers refer to like components in  FIGS. 1 and 2 . The interconnecting substrate  200  accordingly includes the first and second external layers  110  and  112 . The interconnecting substrate  200  can also include a conductive core  220  having the dielectric layer  122 , the signal lines  140  through the dielectric layer  122 , a first conductive stratum  226  on one surface of the dielectric layer  122 , and a second conductive stratum  228  on an opposing surface of the dielectric layer  122 . In an alternative embodiment, the conductive core  220  can have only one of the first conductive stratum  226  or the second conductive stratum  228  on one side of the dielectric layer  122 . The interconnecting substrate  200  can also include a plurality of vents  260  in one or both of the first and second conductive stratums  226 / 228 . In this embodiment, the vents  260  are elongated channels extending through at least a portion of the first conductive stratum  226  and/or the second conductive stratum  228 . The channels  260  generally have short lengths to protect the signal integrity and provide an adequate return path for the first and second conductive stratums  226 / 228 . The channels  260 , however, can also have long lengths if such vents do not affect the operation of the stratums  226 / 228 . The vents  260  can be superimposed with one another for at least a portion of their lengths, and they are generally filled with material from the first layer  110 , the second layer  112 , and/or the dielectric layer  112  (shown in broken lines). In operation, the vents  260  are expected to direct moisture away from the dielectric layer  122  in a manner similar to the vents  160  of the interconnecting substrate  100 . As a result, the interconnecting substrate  200  is also expected to reduce the formation of voids or delamination of the various layers in the interconnecting substrate  200  during high temperature processing. 
       FIG. 3  is a cross-sectional top isometric view showing a portion of an interconnecting substrate  300  in accordance with another embodiment of the invention. The interconnecting substrate  300  can have the first external layer  110 , the second external layer  112 , and the conductive core  120  between the first and second external layers  110  and  112 . The conductive core  120  can also include the dielectric layer  122 , the first conductive stratum  126  on one side of the dielectric layer  122 , and the second conductive stratum  128  on the other side of the dielectric layer  122 . The difference between the interconnecting substrate  300  in  FIG. 3  and the interconnecting substrate  100  in  FIG. 1  is that the interconnecting substrate  300  has a plurality of vents  160  that are offset from each other. The interconnecting substrate  300 , for example, can have a first vent  160  between two signal lines  140  and a second vent  160  in the second conductive substrate  128  offset from the first vent  160 . The vents  160  shown in  FIG. 3  can also be channels similar to the vents  260  shown in  FIG. 2 . Additionally, in alternative embodiments, the vents  160  and  260  illustrated in  FIGS. 1–3  can be combined into a single device such that an interconnecting substrate has vents that are holes and/or channels that are superimposed with one another and/or offset from one another. Additionally, the vents can have other shapes that are neither cylindrical nor rectilinear according to the particular structure of the signal lines and other features of the interconnecting substrates. 
       FIG. 4  is a cross-sectional top isometric view illustrating a portion of an interconnecting substrate  400  in accordance with another embodiment of the invention. The interconnecting substrate  400  has the first external layer  110  and the second external layer  112 . The interconnecting substrate  400  also includes a conductive core  420  having a dielectric separator layer  422 , a first conductive stratum  426  on one side of the dielectric layer  422 , and a second conductive stratum  428  on another side of the dielectric layer  422 . The first and second conductive stratums  426 / 428  can be solid layers of a metal material without any vents. The interconnecting substrate  400  can also include a plurality of vents  460  defined by channels extending through the dielectric layer  422 . The vents  460  generally extend to the edge of the interconnecting substrate  400  so that moisture within the dielectric layer  422  can escape from the conductive core  420  at the edge of the interconnecting substrate  400 . The vents  460  are generally at least partially filled with material from the dielectric layer  422 . In an alternative embodiment, the first and second conductive stratums  426 / 428  can have vents similar to the first and second conductive stratums  126 ,  226 ,  128  or  228  shown above with reference to  FIGS. 1–3 . The configuration of the vents  460  in the dielectric layer  422  can accordingly be combined with any of the vents  160  and  260  in the conductive stratums shown above with reference to  FIGS. 1–3 . In operation, therefore, the expanding moisture in the dielectric layer  422  can be directed away from the dielectric layer  422  through the vents  460  to the edge of the interconnecting substrate  400  in addition to, or in lieu of, any vents  160  or  260  in the first and second conductive stratums  426 / 428 . 
       FIG. 5  is a cut-away top isometric view of a packaged microelectronic device  500  having an interconnecting substrate  502  in accordance with an embodiment of the invention. The microelectronic device  500  can also include a microelectronic die  570  attached to one side of the interconnecting substrate  502 , a first protective casing  598  covering at least a portion of the die  570 , and a second protective casing  599  covering a top side of the die  570  and a portion of the interconnecting substrate  502 . The microelectronic die  570  can be memory device, a processor, or another type of component that has an integrated circuit  572  and a plurality of bond-pads  574  coupled to the integrated circuit  572 . 
     The interconnecting substrate  502  can be similar to any of the interconnecting substrates  100 ,  200 ,  300 , or  400  illustrated and described above with reference to  FIGS. 1-4 . For example, the interconnecting substrate  502  can have a first external layer  510 , a second external layer  512 , and a conductive core between the first and second external layers  510  and  512 . The conductive core can include a dielectric separator layer  522  and at least a first conductive stratum  526  on one side of the dielectric layer  522 . The conductive core can also include a second conductive stratum  528  on another side of the dielectric layer  522 . The interconnecting substrate  502  also includes a plurality of vents  560  in either the first conductive stratum  526 , the second conductive stratum  528 , and/or the dielectric layer  522 . The vents  560  can be holes, channels or other features that are configured to direct moisture away from the dielectric layer  522  to the edge of the interconnecting substrate  502  and/or the first and second external layers  510  and  512 . The structure of the first external layer  510 , second external layer  512 , the dielectric layer  522 , and the first and second conductive stratums  526 / 528  can be similar to those described above with reference to  FIGS. 1–4 . 
     The interconnecting substrate  502  can also include a plurality of contact elements  582 , a plurality of ball-pads  584 , and a plurality of trace lines  586  coupling selected contact elements  582  to corresponding ball-pads  584 . The contact elements  582  are further coupled to selected bond-pads  574  on the die  570  by wire-bond lines  587 . In certain applications, certain contact elements  582  may be coupled directly to either the first conductive stratum  526  or the second conductive stratum  528  by vertical contacts that go through the various layers of the interconnecting substrate  502 . For example, a conductive element  582   a  can be coupled to a ground plane (e.g, the first conductive stratum  526 ) or a power plane (e.g., the second conductive stratum  528 ) by a contact (not shown) extending through the interconnecting substrate  502  to the ground plane or the power plane. The first conductive stratum  526  or the second conductive stratum  528  can also be coupled to either a ground potential or a power potential by a ball-pad  584   b  coupled to the selected potential and a contact element  582   b  coupled to the ball-pad  584   b  and the first conductive stratum  526  or the second conductive stratum  528 . 
     From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except by the appended claims.