Patent Publication Number: US-7215594-B2

Title: Address latch circuit of memory device

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an address latch circuit of a memory device, and more particularly to such an address latch circuit wherein a latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition, thereby making it possible to reduce power consumption caused during the level transition of the address signal. 
   2. Description of the Related Art 
   In general, memory devices employing synchronous dynamic random access memories (DRAMs) require a very small amount of current consumption, and the amount of current consumption is one of the main factors to be extremely sensitively handled in battery-equipped devices such as notebook computers. 
   DRAMs must also have a latch circuit that latches an external address signal for a read/write operation of a specific memory cell or an internal address signal for a refresh operation of the memory cell for a predetermined period of time and then transfers the latched external or internal address signal to an associated bank. 
     FIG. 1  is a circuit diagram showing the configuration of an address latch circuit of a conventional memory device. 
   As shown in  FIG. 1 , the address latch circuit comprises a first transfer circuit  10  for transferring an external address signal eat&lt;k&gt; in response to an external address control signal extaxp, a second transfer circuit  15  for transferring an internal address signal iat&lt;k&gt; in response to an internal address control signal intaxp, a latch  20  for latching the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; transferred from the first or second transfer circuit  10  or  15 , and an output driver  30  for amplifying and outputting the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; latched by the latch  20 . 
   The external address control signal extaxp is able to drive large fan-out and load and is generated by generating an external address before control signal extaxp_before before the external address control signal extaxp is generated, namely, earlier by a delay time of a first delay  11  than the external address control signal extaxp, and passing the generated external address before control signal extaxp_before through a drive device, such as the first delay  11 . Similarly, the internal address control signal intaxp is able to drive large fan-out and load and is generated by generating an internal address before control signal intaxp_before before the internal address control signal intaxp is generated, namely, earlier by a delay time of a second delay  16  than the internal address control signal intaxp, and passing the generated internal address before control signal intaxp_before through a drive device, such as the second delay  16 . 
   The latch  20  includes a first inverter INV 1  for inverting the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; transferred from the first or second transfer circuit  10  or  15 , and a second inverter INV 2  for inverting an output signal from the first inverter INV 1  and applying the inverted signal as an input signal to the first inverter INV 1  to latch the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt;. 
   Accordingly, if the external address signal eat&lt;k&gt; is externally inputted, the external address control signal extaxp is generated to turn on a first transfer transistor  12  of the first transfer circuit  10 , so as to transfer the external address signal eat&lt;k&gt;. Similarly, if the internal address signal iat&lt;k&gt; is internally inputted from an address generator (not shown) for a refresh operation, the internal address control signal intaxp is generated to turn on a second transfer transistor  14  of the second transfer circuit  15 , so as to transfer the internal address signal iat&lt;k&gt;. 
   The transferred external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; is changed from low to high in level or vice versa and constantly maintained by the first inverter INV 1  and second inverter INV 2  of the latch  20 , and then amplified and outputted as an address signal at_row&lt;k&gt; by the output driver  30 . 
   However, since this latch operation is performed with respect to all address signals, the number of address signal level transitions increases in the latch  20  as the number of address signals and the speed of a DRAM increase. The increased number of address signal level transitions leads to an increase in the number of events of power consumption resulting from the formation of a direct current path between a supply voltage terminal and a ground voltage terminal of the latch inverter, or the second inverter INV 2 , during the level transition and, in turn, an increase in power consumption. 
   SUMMARY OF THE INVENTION 
   Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide an address latch circuit of a memory device wherein a latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition, thereby making it possible to reduce power consumption caused during the level transition of the address signal. 
   In accordance with the present invention, the above and other objects can be accomplished by the provision of an address latch circuit of a memory device comprising: first transfer means for transferring a first address signal in response to a first address control signal; second transfer means for transferring a second address signal in response to a second address control signal; comparison means for outputting a latch control signal in response to first and second address before control signals, the first and second address before control signals being generated earlier than the first and second address control signals, respectively; latch means for latching the first or second address signal transferred from the first or second transfer means in response to the latch control signal from the comparison means; transfer time adjustment means for adjusting a transfer time of the latch control signal from the comparison means so as to control the operation of the latch means; and an output driver for amplifying and outputting the first address signal or second address signal latched by the latch means. 
   Preferably, the comparison means outputs the latch control signal when at least one of the first and second address before control signals is made active. 
   To this end, the comparison means may include a NOR gate for NORing the first and second address before control signals. 
   Preferably, the first address before control signal is generated earlier by a delay time of a first delay than the first address control signal, and the second address before control signal is generated earlier by a delay time of a second delay than the second address control signal. 
   Preferably, the transfer time adjustment means includes a third delay for delaying the latch control signal from the comparison means by a delay time thereof and transferring the delayed signal to the latch means. 
   The delay time of the third delay may be set to an OFF time of the latch means before the first address signal or second address signal from the first or second transfer means is applied to the latch means. 
   Preferably, the latch means includes: a first inverter for inverting the first address signal or second address signal transferred from the first or second transfer means; a second inverter for inverting an output signal from the first inverter and applying the inverted signal as an input signal to the first inverter; and a switch for switching an operation of the second inverter in response to the latch control signal from the comparison means. 
   Preferably, the second inverter and switch each include a plurality of MOS (Metal-Oxide Semiconductor) transistors, each of the MOS transistors having a channel length shorter than those of other MOS transistors constituting the latch means. 
   The first address control signal may be an external address control signal and the second address control signal may be an internal address control signal. 
   The first address before control signal may be an external address before control signal and the second address before control signal may be an internal address before control signal. 
   The first address signal may be an external address signal and the second address signal may be an internal address signal. 
   In a feature of the present invention, if an address signal is inputted after an address control signal is generated in the form of a pulse signal, a latch is turned off in response to an address before control signal generated earlier than the address control signal. As a result, a latch operation is not performed while the address signal makes a level transition. Thereafter, when the address signal is stabilized after the level transition and the address before control signal is made inactive, the latch is turned on to perform the latch operation. Therefore, it is possible to reduce power consumption caused during the level transition of the address signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a circuit diagram showing the configuration of an address latch circuit of a conventional memory device; and 
       FIG. 2  is a circuit diagram showing the configuration of an address latch circuit of a memory device according to the present invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Now, a preferred embodiment of the present invention will be described in detail with reference to the annexed drawing. Those skilled in the art will appreciate that the present embodiment is proposed for illustrative purposes and various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention. The same elements as those in the conventional configuration are denoted by the same reference numerals and referred to using the same terms. 
     FIG. 2  is a circuit diagram showing the configuration of an address latch circuit of a memory device according to the present invention. 
   As shown in  FIG. 2 , the address latch circuit of the memory device according to the present invention comprises a first transfer circuit  10  for transferring an external address signal eat&lt;k&gt; in response to an external address control signal extaxp, a second transfer circuit  15  for transferring an internal address signal iat&lt;k&gt; in response to an internal address control signal intaxp, and a comparator  40  for outputting a latch control signal in response to an external address before control signal extaxp_before which is earlier by a delay time of a first delay  11  than the external address control signal extaxp and an internal address before control signal intaxp_before which is earlier by a delay time of a second delay  16  than the internal address control signal intaxp. The address latch circuit further comprises a latch  20  for latching the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; transferred from the first or second transfer circuit  10  or  15  in response to the latch control signal from the comparator  40 , a transfer time adjuster  50  for adjusting a transfer time of the latch control signal from the comparator  40  so as to control the operation of the latch  20 , and an output driver  30  for amplifying and outputting the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; latched by the latch  20 . 
   The comparator  40  is provided with a NOR gate  42  for NORing the external address before control signal extaxp_before and the internal address before control signal intaxp_before. 
   The transfer time adjuster  50  is provided with a third delay  51  for delaying the latch control signal from the comparator  40  by a delay time thereof and transferring the delayed signal to the latch  20 . 
   The delay time of the third delay  51  is set to an OFF time of the latch  20  before the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; from the first or second transfer circuit  10  or  15  is applied to the latch  20 . 
   In other words, before the latch  20  is applied with the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; from the first or second transfer circuit  10  or  15 , it is turned off so as not to perform the latch operation while the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; makes a level transition. 
   The latch  20  includes a first inverter INV 1  for inverting the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; transferred from the first or second transfer circuit  10  or  15 , a second inverter  22  for inverting an output signal from the first inverter INV 1  and applying the inverted signal as an input signal to the first inverter INV 1 , and a switch  24  for switching the operation of the second inverter  22  in response to the latch control signal from the comparator  40 . 
   In detail, the switch  24  includes a first PMOS (P-channel Metal-Oxide Semiconductor) transistor P 1  and a first NMOS (N-channel Metal-Oxide Semiconductor) transistor N 1  connected in series between a supply voltage terminal Vdd and a ground voltage terminal Vss and having their gates for receiving an inverted version of the latch control signal and the latch control signal, respectively. The second inverter  22  includes a second PMOS transistor P 2  and a second NMOS transistor N 2  for cooperating to invert the output signal from the first inverter INV 1  and apply the inverted signal as the input signal to the first inverter INV 1 . The second PMOS transistor P 2  and the second NMOS transistor N 2  are connected in series between the first PMOS transistor P 1  and the first NMOS transistor N 1  and have their gates for receiving the output signal from the first inverter INV 1  in common. 
   Preferably, the latch operation can be rapidly carried out by making the channel length of each of the first and second PMOS transistors P 1  and P 2  and the first and second NMOS transistors N 1  and N 2  in the second inverter  22  and switch  24  shorter than those of other MOS transistors constituting the latch  20 . 
   A detailed description will hereinafter be given of the operation of the address latch circuit of the memory device with the above-stated configuration according to the present invention. 
   It should be noted herein that only the kth address signal, among a plurality of row address signals, is described for illustrative purposes although the latch circuit is provided and functions in the same manner with respect to all of the row address signals. 
   First, if the external address signal eat&lt;k&gt; is inputted, the external address control signal extaxp and the external address before control signal extaxp_before which is earlier by the delay time of the first delay  11  than the external address control signal extaxp are generated. 
   That is, the external address before control signal extaxp_before and the external address control signal extaxp are sequentially generated with a time difference therebetween as pulse signals with low to high level transitions. Then, the external address control signal extaxp is applied to the first transfer circuit  10  to turn on a first transfer transistor  12  thereof. As a result, the external address signal eat&lt;k&gt; is transferred to the latch  20  through the first transfer transistor  12 . 
   The external address before control signal extaxp_before is applied to the comparator  40 . Since the external address before control signal extaxp_before is high in level, the NOR gate  42  outputs a low-level latch control signal. This low-level latch control signal is delayed by the third delay  51  and then inverted by a tenth inverter INV 10  of the switch  24 . Thereafter, the inverted latch control signal is applied to the gate of the first PMOS transistor P 1  to turn off the first PMOS transistor P 1 , and the latch control signal is applied to the gate of the first NMOS transistor N 1  to turn off the first NMOS transistor N 1 . 
   At this time, the delay time of the third delay  51  of the transfer time adjuster  50  is adjusted such that the external address signal eat&lt;k&gt; with level transition is transferred through the first transfer circuit  10  and arrives at the latch  20  after the first PMOS transistor P 1  and the first NMOS transistor N 1  are turned off. 
   Accordingly, the second PMOS transistor P 2  and second NMOS transistor N 2  of the second inverter  22  float, so the external address signal eat&lt;k&gt; applied to the latch  20  is inverted by the first inverter INV 1 , but not fed back, while it makes a level transition. Namely, the latch operation is not performed while the external address signal eat&lt;k&gt; makes a level transition. 
   On the other hand, in the case where the internal address signal iat&lt;k&gt; is inputted, the present address latch circuit is operated in the same manner as in the case where the external address signal eat&lt;k&gt; is inputted. 
   As described above, if at least one of the external address before control signal extaxp_before and internal address before control signal intaxp_before is generated, the first PMOS transistor P 1  and first NMOS transistor N 1  of the switch  24  in the latch  20  are turned off to cause the second PMOS transistor P 2  and second NMOS transistor N 2  of the second inverter  22  to float. As a result, no direct current path is formed between the supply voltage terminal Vdd and the ground voltage terminal Vss, thus reducing power consumption. 
   However, in the case where the external address before control signal extaxp_before or internal address before control signal intaxp_before returns to low in level after being generated, the external address control signal extaxp or internal address control signal intaxp returns to low in level, too, thereby causing the first transfer transistor  12  of the first transfer circuit  10  and the second transfer transistor  14  of the second transfer circuit  15  to be turned off so as to block an input to the latch  20 . 
   Also, the NOR gate  42  of the comparator  40  outputs a high-level latch control signal so as to turn on the first PMOS transistor P 1  and first NMOS transistor N 1  of the switch  24 , thereby causing the output signal from the first inverter INV 1  to be inverted by the second PMOS transistor P 2  and second NMOS transistor N 2  of the second inverter  22  and applied as the input signal to the first inverter INV 1 . As a result, the latch operation is normally performed by constantly maintaining the input external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt;. 
   In other words, whereas the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; makes a low to high level transition or vice versa and then keeps up the current level, the external address before control signal extaxp_before or internal address before control signal intaxp_before and the external address control signal extaxp or internal address control signal intaxp are pulse signals that temporarily go from low to high in level when the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; is generated. 
   Thus, the time when the external address control signal extaxp or internal address control signal intaxp is generated can be determined to be the time when the level transition of the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; occurs. In this regard, if at least one of the external address control signal extaxp and internal address control signal intaxp is generated, the latch operation is disabled by the external address before control signal extaxp_before or internal address before control signal intaxp_before. Therefore, it is possible to reduce power consumption caused during the level transition of the external address signal eat&lt;k&gt; or internal address signal iat&lt;k&gt; inputted to the latch  20 . 
   As apparent from the above description, the present invention provides an address latch circuit of a memory device wherein a latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition. Therefore, it is possible to reduce power consumption caused during the level transition of the address signal. 
   Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.