Patent Publication Number: US-2021193632-A1

Title: Micro-led array device based on iii-nitride semiconductors and method for fabricating same

Description:
CROSS REFERENCE TO THE RELATED APPLICATIONS 
     This application is based upon and claims priority to Chinese Patent Application No. 201911334325.2, filed on Dec. 23, 2019, the entire contents of which are incorporated herein by reference. 
     TECHNICAL FIELD 
     The present disclosure relates to a Micro-LED array device based on III-nitride semiconductors and a method for fabricating the same. The present disclosure also belongs to the technical field of semiconductor lighting and display. 
     BACKGROUND 
     III-Nitride materials are direct band gap semiconductors and have band gaps spanning a wide spectrum, ranging from deep ultraviolet to near infrared. They are widely used in high-efficiency solid-state lighting and ultrahigh resolution display. Unlike the traditional lighting, semiconductor lighting is a revolutionary technique, which uses a semiconductor chip as a luminous source to directly convert electric energy into optical energy with relatively high conversion efficiency. A light emitting diode (LED), as a core component of a semiconductor light source for solid-state lighting, has the advantages of high brightness, long service life, small size, low energy consumption, environmental friendliness, safety in use, etc., and is highly stable and capable of operating in severe environments. Thus, LED is a new generation lighting source after incandescent lamps and fluorescent lamps. With the continuous development of LED, the solid-state lighting technique has gradually replaced the existing lighting techniques, leading us into a new era of lighting. 
     Micro-LEDs usually refer to an LED having a size of 1-100 μm. This allows for miniaturization of an LED device by integrating high-density micro-sized LED arrays on a chip based on pixelation and matricization techniques. Due to unique small size characteristics, Micro-LEDs have higher quantum efficiency and better heat dissipation capability, and even much higher current saturation density and higher modulation bandwidth than large-sized LEDs. Therefore, Micro-LEDs have been extensively used in various fields, including micro-displays, visible light communications, and emitter arrays and optical tweezer systems of optogenetics. 
     A common size of a gallium nitride-based Micro-LED is several tens of microns, so that a large number of Micro-LED arrays can be integrated within a relatively small area. However, due to the small area, the space between light emitting units is small, resulting in easy mutual interference therebetween. When one Micro-LED is lit up, the light emitting units around it may be influenced. Especially in a Micro-LED array on a sapphire substrate, when one Micro-LED is lit up, a bright area around it may be observed on a macroscopic level due to excellent light transmittance of the sapphire, which hinders the pixelation application in display field. The present disclosure solves the problem of mutual interference between light emitting units by using special blocking walls during the fabrication of Micro-LEDs. 
     Chinese patent document No. CN109935614A discloses a micron full-color quantum dot light emitting diode (QLED) array device based on a quantum dot transfer process with a deep silicon etching mask and a method for fabricating the same. Arrays are separated by isolation trenches filled with a light-absorbing material, such as silver. The isolation trenches are formed by an inductively coupled plasma (ICP) etching method for isolation, which are mainly aimed at electrical isolation to prevent mutual effects of electrical properties of adjacent devices. Such isolation trenches, however, cannot block propagating light, and therefore, there still exists the problem of optical mutual interference between adjacent pixel cells. The filling of silver is to enhance the quantum efficiency of the LED device, which, however, cannot solve the problem of optical mutual interference and cannot serve as an electrode. 
     SUMMARY 
     The present disclosure aims to provide a Micro-LED array device to address the problem of mutual interference between light emitting units of Micro-LEDs. 
     The present disclosure adopts the following technical solutions: a Micro-LED array device based on III-nitride semiconductors structurally includes, from top to bottom, in sequence: 
     a Si substrate; 
     a GaN buffer layer grown on the Si substrate; 
     an n-type GaN layer grown on the buffer layer; 
     an InGaN/GaN quantum-well active layer grown on the n-type GaN layer; and 
     a p-type GaN layer grown on the quantum-well active layer. 
     The Micro-LED array device has n arrayed sector mesa units. In each unit, a sector mesa structure is formed by etching to penetrate through the p-type GaN layer and the quantum-well active layer and deep into the n-type GaN layer. The Micro-LED array device further includes a p-type electrode array deposited by evaporation on the p-type GaN layer of sector arrays, and an n-type electrode array deposited by evaporation on the n-type GaN layer. The n-type electrodes in each unit surround the sector mesa in the form of an annular structure, and the n-type electrode array forms blocking walls to isolate the sector mesas from one another. The blocking walls, and the blocking wall and the annular structure surrounding the sector mesa are connected to each other. 
     Preferably, the Si substrate has a thickness of 800 μm. The GaN buffer layer has a thickness of 1750 nm. The n-type GaN layer has a thickness of 1650-1850 nm. The InGaN/GaN quantum-well active layer has a thickness of 200-300 nm, a period number of 10, an In content of 0.26, a Ga content of 0.74, a well width of 2.2 nm, and a barrier thickness of 5.8 nm. The p-type GaN layer has a thickness of 100-200 nm. 
     Preferably, the arrayed sector mesa may come in three sizes: from the inside out, a mesa defined by one quarter of a circular ring with a radius of 32 μm; a mesa defined by one eighth of a circular ring and one quarter of a circular ring inside with a difference of 50 μm between inside and outside radii; and a mesa defined by one eighth of a circular ring and one eighth of a circular ring inside with a difference of 100 μm between inside and outside radii. The sector mesas in three sizes may be concentric, and a period between the outermost circular ring sector and a next circular ring sector in the same size may be 900 μm. With the sector mesas in three different sizes within one concentric circle, the effects of the size factor on luminous intensity and mutual interference can be compared within a small range without changing the parameters of the blocking wall. 
     The present disclosure further discloses a method for fabricating the Micro-LED array device, including the following steps: 
     (1) depositing an insulating layer as a first dielectric layer on an InGaN/GaN quantum-well LED epitaxial wafer using plasma enhanced chemical vapor deposition (PECVD) technique; 
     (2) coating the first dielectric layer with photoresist by spinning, prebaking the photoresist, using ultra-violet lithography with a mask to form ordered sector mesa array patterns on the photoresist, and carrying out developing and postbaking; 
     (3) using reactive ion etching (ME) technique, introducing O 2  to remove a small amount of residual photoresist in regions where most of the photoresist is removed by developing; 
     (4) depositing by evaporation a metal mask layer using physical vapor deposition (PVD) technique, and removing the photoresist layer and a metal film layer on the photoresist layer using a lift-off technique, to obtain ordered sector mesa array patterns with a large area; 
     (5) using the ME technique, longitudinally etching the first dielectric layer with metal as a mask to transfer the sector mesa array structures to the p-type GaN layer; 
     (6) using inductively coupled plasma (ICP) technique, anisotropically etching the p-type GaN layer and the quantum-well layer to the n-type GaN layer with metal as a mask; 
     (7) using wet etching, removing the metal mask layer and the first dielectric layer from the sector mesa array structures, thereby forming GaN sector mesa array structures isolated from one another, and repairing etching damage in sidewalls of the GaN layer and the quantum-well layer; 
     (8) fabricating the n-type electrode array structure that isolates the sector mesa arrays from one another: firstly depositing by evaporation an insulating layer as a second dielectric layer on the GaN sector mesa array structures using the PECVD technique and coating the second dielectric layer with the photoresist by spinning; forming n-type electrode array structure patterns by overlaying on the photoresist of the sector mesa array structures using the ultra-violet lithography with a mask having the n-type electrode array structure, and etching the second dielectric layer using the ME technique with the photoresist as a mask to transfer the n-type electrode array structure patterns to the n-type GaN layer; 
     (9) fabricating the n-type electrodes: depositing by evaporation a metal in the regions of the n-type electrode array structure patterns as the n-type electrodes using the PVD technique, then carrying out a lift-off process to remove the photoresist layer and the metal film covering the photoresist layer, washing and drying samples, and finally realizing ohmic contact between the metal and the n-type GaN layer using a thermal annealing technique; and 
     (10) fabricating the p-type electrodes: carrying out a spin coating to obtain a new layer of photoresist, forming p-type electrode array patterns by overlaying on the photoresist using the ultra-violet lithography with a mask, and etching the second dielectric layer using the RIE technique with the photoresist as a mask to transfer the p-type electrode array patterns to the p-type GaN layer; depositing by evaporation a layer of metal as the p-type electrode array using the PVD technique, then carrying out the lift-off process to remove the photoresist layer and the metal film covering the photoresist layer, washing and drying samples, and finally realizing ohmic contact between the metal and the p-type GaN layer using the thermal annealing technique. 
     Preferably, the blocking wall formed by the n-type electrodes is 6-10 μm wide and 450-550 nm thick. 
     Preferably, the first dielectric layer and the second dielectric layer each has a thickness of 150-250 nm, and is made of SiO 2 , and the metal mask layer is 50 nm thick, and made of nickel (Ni). 
     Preferably, the n-type electrode array is composed of a plurality of layers of metals titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) having a thickness of 450-500 nm, and the p-type electrode array is composed of a plurality of layers of metals Ni/Au having a thickness of 150-200 nm. 
     The present disclosure, aiming at the problem of optical mutual interference, particularly adds blocking walls formed by n-type electrodes between light emitting units of Micro-LED sector mesa arrays, which can serve not only for electrical isolation to physically isolate optical propagating paths, but also for optical isolation to effectively solve the problem of mutual interference between the light emitting units of Micro-LEDs and facilitate individual control without obviously increasing the size of Micro-LED arrays. With the n-type electrode metal as the blocking walls and the p-type electrodes of grid structures, the current expanding range can be increased, so that the luminous efficiency is effectively improved. Thus, applications in many fields such as ultrahigh resolution lighting and display, communication, and biosensing are allowed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a structural schematic diagram of an InGaN/GaN quantum-well LED substrate grown by metal organic chemical vapor deposition (MOCVD) method. 
         FIG. 2  is a structural schematic diagram of a resulting Micro-LED array device from step (1) according to the present disclosure. 
         FIG. 3  is a structural schematic diagram of a resulting Micro-LED array device from step (2) according to the present disclosure. 
         FIG. 4  is a structural schematic diagram of a resulting Micro-LED array device from step (4) according to the present disclosure. 
         FIG. 5  is a structural schematic diagram of a resulting Micro-LED array device from step (5) according to the present disclosure. 
         FIG. 6  is a structural schematic diagram of a resulting Micro-LED array device from step (6) according to the present disclosure. 
         FIG. 7  is a structural schematic diagram of a resulting Micro-LED array device from step (7) according to the present disclosure. 
         FIG. 8  is a structural schematic diagram of a resulting Micro-LED array device from step (8) according to the present disclosure. 
         FIG. 9  is a structural schematic diagram of a resulting Micro-LED array device from step (9) according to the present disclosure. 
         FIG. 10  is a structural schematic diagram of a resulting Micro-LED array device from step (10) according to the present disclosure. 
         FIG. 11  is a schematic diagram of a mask used in step (2) according to the present disclosure. 
         FIG. 12  is a schematic diagram of a mask used in step (8) according to the present disclosure. 
         FIG. 13  is a schematic diagram of a mask used in step (10) according to the present disclosure. 
         FIG. 14  is an optical micrograph of a Micro-LED array device fabricated according to the present disclosure, in which the outermost white circular ring is an annular n-type electrode, line-like structures in white linked with the circular ring are blocking walls formed by n-type electrodes, and white grid structures in sectors are p-type electrodes. 
         FIG. 15  shows part of blocking walls formed by n-type electrodes in a Micro-LED array device fabricated according to the present disclosure. 
         FIG. 16  is an I-V curve graph of a Micro-LED array device fabricated according to the present disclosure. 
         FIG. 17  is a planar structural schematic diagram of a Micro-LED array device fabricated according to the present disclosure. 
         FIG. 18  is a three-dimensional structural schematic diagram of a Micro-LED array device fabricated according to the present disclosure. 
         FIG. 19  is a three-dimensional structural schematic diagram showing arrays of a Micro-LED array device fabricated according to the present disclosure. 
     
    
    
     The specific embodiments of the present disclosure will be further described with reference to the accompanying drawings. 
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The technical solutions in embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in examples of the present disclosure. Apparently, the described embodiments are merely a part rather than all of the embodiments of the present disclosure. All other embodiments derived by a person of ordinary skill in the art from the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure. 
     Embodiment 1 
     A method for fabricating a Micro-LED array device based on III-nitride semiconductors with addition of blocking walls included the following steps. 
     The method was carried out on a Si blue LED epitaxial wafer that was structurally composed of: 
     the Si substrate  1  having a thickness of 800 μm; 
     the GaN buffer layer  2  grown on the Si substrate and having a thickness of 1750 nm; 
     the n-type GaN layer  3  grown on the buffer layer and having a thickness of 1650 nm; 
     the InGaN/GaN quantum-well active layer  4  grown on the n-type GaN layer; 
     wherein the InGaN/GaN quantum-well active layer has a thickness of 200 nm, a period number of 10, an In content of 0.26, a Ga content of 0.74, a well width of 2.2 nm, and a barrier thickness of 5.8 nm; and 
     the p-type GaN layer  5  grown on the quantum-well active layer and having a thickness of 100 nm. 
     (1) The first dielectric layer  6  was deposited by evaporation a SiO 2  layer having a thickness of 150 nm on the Si blue LED epitaxial wafer using plasma enhanced chemical vapor deposition (PECVD) technique, as shown in  FIG. 2 , and a gas mixture of 5% SiH 4 /N 2  and N 2 O was introduced for 7 minutes and 10 seconds, with respective flow rate of 100 sccm and 450 sccm, a pressure of 300 mTorr, a power of 10 W, and a temperature of 350° C. 
     (2) The insulating SiO 2  dielectric layer  6  was coated with the photoresist (S1805) layer  7  by spinning and then subjected to prebaking at 100° C. for 1 minute. Then, ordered sector mesa array patterns were formed on the photoresist using ultra-violet lithography with the mask as shown in  FIG. 11 , and exposed for 1 second, developed for 11 seconds and postbaked at 100° C. for 1 minute, as shown in  FIG. 3 . 
     (3) Using reactive ion etching (ME) technique, O 2  was introduced for 20 seconds with a flow rate of 10 sccm, a pressure of 3 Pa and a power of 50 W to remove residual photoresist, and a 50 nm thick layer of metal nickel (Ni) was deposited by evaporation as the metal mask layer  8  using physical vapor deposition (PVD) technique at a rate of 1 A/s. Next, a lift-off process was carried out using an acetone solution under ultrasound for 5 minutes to remove the photoresist layer  7  and the metal Ni film layer  8  on the photoresist layer, to obtain ordered metal sector mesa array patterns with a large area, as shown in  FIG. 4 . 
     (4) Using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the first SiO 2  dielectric layer  6  was longitudinally etched with the metal Ni as a mask layer to transfer the metal sector mesa structures to the p-type GaN layer, as shown in  FIG. 5 . 
     (5) Using inductively coupled plasma (ICP) technique, a gas mixture of Cl 2  and BCl 3  was introduced for 3 minutes and 30 seconds, with respective flow rate of 48 sccm and 6 sccm, an ICP power of 300 W, an RF power of 100 W, and a pressure of 10 mTorr, and the p-type GaN layer  5  and the quantum-well layer  4  were anisotropically etched with the metal Ni as a mask to form sector mesa array structures deep into the n-type GaN layer  3 , as shown in  FIG. 6 , with an etching depth of about 800 nm. 
     (6) Using wet etching, samples were firstly put in a KOH solution at a concentration of 0.5 mol/L, and heated in a water bath at 40° C. for 15 minutes to repair etching damage in sidewalls of GaN and quantum wells. Next, the samples were soaked in a nitric acid solution at a concentration of nitric acid:water=1:5 at room temperature for 10 minutes to remove the metal mask layer  8 , and soaked in a buffered oxide etch (BOE) for 1 minute to remove the first SiO 2  dielectric layer  6 , thereby forming GaN sector mesa array structures isolated from one another, as shown in  FIG. 7 . 
     (7) The second SiO 2  dielectric layer  9  having a thickness of 150 nm was deposited by evaporation using the PECVD technique, and a gas mixture of 5% SiH 4 /N 2  and N 2 O was introduced for 7 minutes and 10 seconds, with respective flow rate of 100 sccm and 450 sccm, a pressure of 300 mTorr, a power of 10 W, and a temperature of 350° C. Next, spin coating was performed to obtain two layers of photoresist  10 , the first layer of photoresist (LOR10B) was prebaked at 150° C. for 5 minutes, and the second layer of photoresist (AZ1500) was prebaked at 90° C. for 2 minutes. Then, blocking wall patterns and n-type electrode patterns were formed by overlaying on the photoresist using the ultra-violet lithography with the mask as shown in  FIG. 12 , with an exposure time of 4.3 seconds, a developing time of 9 seconds and postbaking at 100° C. for 1 minute. Using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the second SiO 2  dielectric layer  9  was etched with the photoresist as a mask to transfer the blocking wall patterns and the n-type electrode patterns to the n-type GaN layer, as shown in  FIG. 8 . 
     (8) Fabrication of n-type electrodes: metals titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) were deposited by evaporation in the regions of the blocking walls and the regions of the n-type electrode patterns using the PVD technique with respective thicknesses of 20 nm/200 nm/50 nm/180 nm, a total thickness of 450 nm, as the n-type electrode  11 , where the blocking wall was 6 μm wide and 450 nm thick. Then, a lift-off process was carried out using an acetone solution under ultrasound for 5 minutes to remove the photoresist layer  10  and the n-type electrode metal layer on the photoresist layer. Samples were washed and dried. Finally, ohmic contact between the metals Ti/Al/Ni/Au and the n-type GaN layer was realized using a thermal annealing technique under conditions of N 2 , a temperature of 750° C. and time of 30 seconds, as shown in  FIG. 9 . 
     (9) Fabrication of p-type electrodes: spin coating was performed to obtain two new layers of photoresist, the first layer of photoresist (LOR10B) was prebaked at 150° C. for 5 minutes, and the second layer of photoresist (AZ1500) was prebaked at 90° C. for 2 minutes. Then, p-type electrode patterns were formed by overlaying on the photoresist using the ultra-violet lithography with the mask as shown in  FIG. 13 , with an exposure time of 4.3 seconds and a developing time of 9 seconds. Then, using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the second SiO 2  dielectric layer  9  was etched with the photoresist as a mask to transfer the p-type electrode patterns to the p-type GaN layer  5 . Metals Ni/Au were deposited by evaporation using the PVD technique with respective thickness of 30 nm/120 nm, a total thickness of 150 nm, as the p-type electrode  12 . Then, the photoresist layer and the metal Ni/Au film layer on the photoresist layer were removed using an acetone solution under ultrasound for 5 minutes. Samples were washed and dried. Finally, ohmic contact between the metals Ni/Au and the p-type GaN layer was realized using the thermal annealing technique under conditions of O 2  and N 2  in a ratio of 1:4, a temperature of 500° C. and time of 10 minutes, as shown in  FIG. 10 . 
     (10) A top view of the resulting Micro-LED array device under an optical microscope was as shown in  FIG. 14 , an electrical test I-V characteristic curve was shown in  FIG. 16 , a planar structural schematic diagram was shown in  FIG. 17 , and a three-dimensional structural schematic diagram was shown in  FIG. 18 . 
     Embodiment 2 
     A method for fabricating a Micro-LED array device based on III-Nitride semiconductors with addition of blocking walls included the following steps. 
     The method was carried out on a Si blue LED epitaxial wafer that was structurally composed of: 
     the Si substrate  1  having a thickness of 800 μm; 
     the GaN buffer layer  2  grown on the Si substrate and having a thickness of 1750 nm; 
     the n-type GaN layer  3  grown on the buffer layer and having a thickness of 1750 nm; 
     the InGaN/GaN quantum-well active layer  4  grown on the n-type GaN layer; wherein the InGaN/GaN quantum-well active layer has a thickness of 250 nm, a period number of 10, an In content of 0.26, a Ga content of 0.74, a well width of 2.2 nm, and a barrier thickness of 5.8 nm; and the p-type GaN layer  5  grown on the quantum-well active layer and having a thickness of 150 nm. 
     (1) The first dielectric layer  6  was deposited by evaporation a SiO 2  layer having a layer of 200 nm on the Si blue LED epitaxial wafer using plasma enhanced chemical vapor deposition (PECVD) technique, as shown in  FIG. 2 , and a gas mixture of 5% SiH 4 /N 2  and N 2 O was introduced for 9 minutes and 40 seconds, with respective flow rate of 100 sccm and 450 sccm, a pressure of 300 mTorr, a power of 10 W, and a temperature of 350° C. 
     (2) The insulating SiO 2  dielectric layer  6  was coated with the photoresist (S1805) layer  7  by spinning and then subjected to prebaking at 100° C. for 1 minute. Then, ordered sector mesa array patterns were formed on the photoresist using ultra-violet lithography with the mask as shown in  FIG. 11 , and exposed for 1 second, developed for 10 seconds and postbaked at 100° C. for 1 minute, as shown in  FIG. 3 . 
     (3) Using reactive ion etching (ME) technique, O 2  was introduced for 20 seconds with a flow rate of 10 sccm, a pressure of 3 Pa and a power of 50 W to remove residual photoresist, and a 50 nm thick layer of metal nickel (Ni) was deposited by evaporation as the metal mask layer  8  using physical vapor deposition (PVD) technique at a rate of 1 A/s. Next, a lift-off process was carried out using an acetone solution under ultrasound for 5 minutes to remove the photoresist layer  7  and the metal Ni film layer  8  on the photoresist layer, to obtain ordered metal sector mesa array patterns with a large area, as shown in  FIG. 4 . 
     (4) Using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the first SiO 2  dielectric layer  6  was longitudinally etched with the metal Ni as a mask layer to transfer the metal sector mesa structures to the p-type GaN layer, as shown in  FIG. 5 . 
     (5) Using inductively coupled plasma (ICP) technique, a gas mixture of Cl 2  and BCl 3  was introduced for 3 minutes and 30 seconds, with respective flow rate of 48 sccm and 6 sccm, an ICP power of 300 W, an RF power of 100 W, and a pressure of 10 mTorr, and the p-type GaN layer  5  and the quantum-well layer  4  were anisotropically etched with the metal Ni as a mask to form sector mesa array structures deep into the n-type GaN layer  3 , as shown in  FIG. 6 , with an etching depth of about 800 nm. 
     (6) Using wet etching, samples were firstly put in a KOH solution at a concentration of 0.5 mol/L, and heated in a water bath at 40° C. for 15 minutes to repair etching damage in sidewalls of GaN and quantum wells. Next, the samples were soaked in a nitric acid solution at a concentration of nitric acid:water=1:5 at room temperature for 10 minutes to remove the metal mask layer  8 , and soaked in a buffered oxide etch (BOE) for 1 minute to remove the first SiO 2  dielectric layer  6 , thereby forming GaN sector mesa array structures isolated from one another, as shown in  FIG. 7 . 
     (7) The second SiO 2  dielectric layer  9  having a thickness of 200 nm was deposited by evaporation using the PECVD technique, and a gas mixture of 5% SiH 4 /N 2  and N 2 O was introduced for 9 minutes and 40 seconds, with respective flow rate of 100 sccm and 450 sccm, a pressure of 300 mTorr, a power of 10 W, and a temperature of 350° C. Next, spin coating was performed to obtain two layers of photoresist  10 , the first layer of photoresist (LOR10B) was prebaked at 150° C. for 5 minutes, and the second layer of photoresist (AZ1500) was prebaked at 90° C. for 2 minutes. Then, blocking wall patterns and n-type electrode patterns were formed by overlaying on the photoresist using the ultra-violet lithography with the mask as shown in  FIG. 12 , with an exposure time of 4.3 seconds, developing time of 9 seconds and postbaking at 100° C. for 1 minute. Using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the second SiO 2  dielectric layer  9  was etched with the photoresist as a mask to transfer the blocking wall patterns and the n-type electrode patterns to the n-type GaN layer, as shown in  FIG. 8 . 
     (8) Fabrication of n-type electrodes: metals titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) were deposited by evaporation in the regions of the blocking walls and the regions of the n-type electrode patterns using the PVD technique with respective thickness of 30 nm/210 nm/50 nm/210 nm, a total thickness of 500 nm, as the n-type electrode  11 , where the blocking wall was 8 μm wide and 500 nm thick. Then, a lift-off process was carried out using an acetone solution under ultrasound for 5 minutes to remove the photoresist layer  10  and the n-type electrode metal layer on the photoresist layer. Samples were washed and dried. Finally, ohmic contact between the metals Ti/Al/Ni/Au and the n-type GaN layer was realized using a thermal annealing technique under conditions of N 2 , a temperature of 750° C. and time of 30 seconds, as shown in  FIG. 9 . 
     (9) Fabrication of p-type electrodes: spin coating was performed to obtain two new layers of photoresist, the first layer of photoresist (LOR10B) was prebaked at 150° C. for 5 minutes, and the second layer of photoresist (AZ1500) was prebaked at 90° C. for 2 minutes. Then, p-type electrode patterns were formed by overlaying on the photoresist using the ultra-violet lithography with the mask as shown in  FIG. 13 , with an exposure time of 4.3 seconds and developing time of 9 seconds. Then, using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the second SiO 2  dielectric layer  9  was etched with the photoresist as a mask to transfer the p-type electrode patterns to the p-type GaN layer  5 . Metals Ni/Au were deposited by evaporation using the PVD technique with respective thickness of 30 nm/150 nm, a total thickness of 180 nm, as the p-type electrode  12 . Then, the photoresist layer and the metal Ni/Au film layer on the photoresist layer were removed using an acetone solution under ultrasound for 5 minutes. Samples were washed and dried. Finally, ohmic contact between the metals Ni/Au and the p-type GaN layer was realized using the thermal annealing technique under conditions of O 2  and N 2  in a ratio of 1:4, a temperature of 500° C. and time of 10 minutes, as shown in  FIG. 10 . 
     (10) A top view of the resulting Micro-LED array device under an optical microscope was as shown in  FIG. 14 , an electrical test I-V characteristic curve was shown in  FIG. 16 , a planar structural schematic diagram was shown in  FIG. 17 , and a three-dimensional structural schematic diagram was shown in  FIG. 18 . 
     Embodiment 3 
     A method for fabricating a Micro-LED array device based on III-Nitride semiconductors with addition of blocking walls included the following steps. 
     The method was carried out on a Si blue LED epitaxial wafer that was structurally composed of: 
     the Si substrate  1  having a thickness of 800 μm; 
     the GaN buffer layer  2  grown on the Si substrate and having a thickness of 1750 nm; 
     the n-type GaN layer  3  grown on the buffer layer and having a thickness of 1850 nm; 
     the InGaN/GaN quantum-well active layer  4  grown on the n-type GaN layer; wherein the InGaN/GaN quantum-well active layer has a thickness of 300 nm, a period number of 10, an In content of 0.26, a Ga content of 0.74, a well width of 2.2 nm, and a barrier thickness of 5.8 nm; and the p-type GaN layer  5  grown on the quantum-well active layer and having a thickness of 200 nm. 
     (1) The first SiO 2  dielectric layer  6  having a thickness of 250 nm was deposited by evaporation on the Si blue LED epitaxial wafer using plasma enhanced chemical vapor deposition (PECVD) technique, as shown in  FIG. 2 , and a gas mixture of 5% SiH 4 /N 2  and N 2 O was introduced for 11 minutes and 50 seconds, with respective flow rate of 100 sccm and 450 sccm, a pressure of 300 mTorr, a power of 10 W, and a temperature of 350° C. 
     (2) The insulating SiO 2  dielectric layer  6  was coated with the photoresist (S1805) layer  7  by spinning and then subjected to prebaking at 100° C. for 1 minute. Then, ordered sector mesa array patterns were formed on the photoresist using ultra-violet lithography with the mask as shown in  FIG. 11 , and exposed for 1 second, developed for 11 seconds and postbaked at 100° C. for 1 minute, as shown in  FIG. 3 . 
     (3) Using reactive ion etching (ME) technique, O 2  was introduced for 20 seconds with a flow rate of 10 sccm, a pressure of 3 Pa and a power of 50 W to remove residual photoresist, and a 50 nm thick layer of metal nickel (Ni) was deposited by evaporation as the metal mask layer  8  using physical vapor deposition (PVD) process at a rate of 1 A/s. Next, a lift-off process was carried out using an acetone solution under ultrasound for 5 minutes to remove the photoresist layer  7  and the metal Ni film layer  8  on the photoresist layer, to obtain ordered metal sector mesa array patterns with a large area, as shown in  FIG. 4 . 
     (4) Using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the first SiO 2  dielectric layer  6  was longitudinally etched with the metal Ni as a mask layer to transfer the metal sector mesa structures to the p-type GaN layer, as shown in  FIG. 5 . 
     (5) Using inductively coupled plasma (ICP) technique, a gas mixture of Cl 2  and BCl 3  was introduced for 3 minutes and 30 seconds, with respective flow rate of 48 sccm and 6 sccm, an ICP power of 300 W, an RF power of 100 W, and a pressure of 10 mTorr, and the p-type GaN layer  5  and the quantum-well layer  4  were anisotropically etched with the metal Ni as a mask to form sector mesa array structures deep into the n-type GaN layer  3 , as shown in  FIG. 6 , with an etching depth of about 800 nm. 
     (6) Using wet etching, samples were firstly put in a KOH solution at a concentration of 0.5 mol/L, and heated in a water bath at 40° C. for 15 minutes to repair etching damage in sidewalls of GaN and quantum wells. Next, the samples were soaked in a nitric acid solution at a concentration of nitric acid:water=1:5 at room temperature for 10 minutes to remove the metal mask layer  8 , and soaked in a buffered oxide etch (BOE) for 1 minute to remove the first SiO 2  dielectric layer  6 , thereby forming GaN sector mesa array structures isolated from one another, as shown in  FIG. 7 . 
     (7) The second SiO 2  dielectric layer  9  having a thickness of 250 nm was deposited by evaporation using the PECVD technique, and a gas mixture of 5% SiH 4 /N 2  and N 2 O was introduced for 11 minutes and 50 seconds, with respective flow rate of 100 sccm and 450 sccm, a pressure of 300 mTorr, a power of 10 W, and a temperature of 350° C. Next, spin coating was performed to obtain two layers of photoresist  10 , the first layer of photoresist (LOR10B) was prebaked at 150° C. for 5 minutes, and the second layer of photoresist (AZ1500) was prebaked at 90° C. for 2 minutes. Then, blocking wall patterns and n-type electrode patterns were formed by overlaying on the photoresist using the ultra-violet lithography with the mask as shown in  FIG. 12 , with an exposure time of 4.3 seconds, developing time of 9 seconds and postbaking at 100° C. for 1 minute. Using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the second SiO 2  dielectric layer  9  was etched with the photoresist as a mask to transfer the blocking wall patterns and the n-type electrode patterns to the n-type GaN layer, as shown in  FIG. 8 . 
     (8) Fabrication of n-type electrodes: metals titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) were deposited by evaporation in the regions of the blocking walls and the regions of the n-type electrode patterns using the PVD technique with respective thickness of 40 nm/230 nm/60 nm/220 nm, a total thickness of 550 nm, as the n-type electrode  11 , where the blocking wall was 10 μm wide and 550 nm thick. Then, a lift-off process was carried out using an acetone solution under ultrasound for 5 minutes to remove the photoresist layer  10  and the n-type electrode metal layer on the photoresist layer. Samples were washed and dried. Finally, ohmic contact between the metals Ti/Al/Ni/Au and the n-type GaN layer was realized using a thermal annealing technique under conditions of N 2 , a temperature of 750° C. and time of 30 seconds, as shown in  FIG. 9 . 
     (9) Fabrication of p-type electrodes: spin coating was performed to obtain two new layers of photoresist, the first layer of photoresist (LOR10B) was prebaked at 150° C. for 5 minutes, and the second layer of photoresist (AZ1500) was prebaked at 90° C. for 2 minutes. Then, p-type electrode patterns were formed by overlaying on the photoresist using the ultra-violet lithography with the mask as shown in  FIG. 13 , with an exposure time of 4.3 seconds and a developing time of 9 seconds. Then, using the RIE technique, a gas mixture of O 2  and CF 4  was introduced for 3 minutes and 40 seconds, with respective flow rate of 10 sccm and 30 sccm, a power of 150 W, and a pressure of 4 Pa, and the second SiO 2  dielectric layer  9  was etched with the photoresist as a mask to transfer the p-type electrode patterns to the p-type GaN layer  5 . Metals Ni/Au were deposited by evaporation using the PVD technique with respective thickness of 50 nm/150 nm, a total thickness of 200 nm, as the p-type electrode  12 . Then, the photoresist layer and the metal Ni/Au film layer on the photoresist layer were removed using an acetone solution under ultrasound for 5 minutes. Samples were washed and dried. Finally, ohmic contact between the metals Ni/Au and the p-type GaN layer was realized using the thermal annealing technique under conditions of O 2  and N 2  in a ratio of 1:4, a temperature of 500° C. and time of 10 minutes, as shown in  FIG. 10 . 
     (10) A top view of the resulting Micro-LED array device under an optical microscope was as shown in  FIG. 14 , an electrical test I-V characteristic curve was shown in  FIG. 16 , a planar structural schematic diagram was shown in  FIG. 17 , and a three-dimensional structural schematic diagram was shown in  FIG. 18 . 
     The above embodiments are preferred embodiments of the present disclosure. However, the implementation modes of the present disclosure are not limited by the above embodiments. Any other change, modification, substitution, combination, and simplification made without departing from the spiritual essence and principles of the present disclosure shall be construed as equivalent replacements and fall within the protection scope of the present disclosure.