Patent Publication Number: US-9891650-B2

Title: Current generation circuit, and bandgap reference circuit and semiconductor device including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese patent application No. 2014-082566, filed on Apr. 14, 2014, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     The present invention relates to a current generation circuit, and a bandgap reference circuit and a semiconductor device including the same. For example, the present invention relates to a current generation circuit suitable for generating an accurate current, and a bandgap reference circuit and a semiconductor device including the aforementioned current generation circuit and suitable for continuously outputting a constant reference voltage irrespective of their temperature. 
     A bandgap reference circuit is required to continuously output a constant reference voltage irrespective of its temperature. A technique relating to a bandgap reference circuit is disclosed in H. Neuteboom, B. M. J. Kup, and M. Janssens, “A DSP-based hearing instrument IC”, IEEE J. Solid-State Circuits, vol. 32, pp. 1790-1806, November 1997. 
     The bandgap reference circuit disclosed in H. Neuteboom, B. M. J. Kup, and M. Janssens, “A DSP-based hearing instrument IC”, IEEE J. Solid-State Circuits, vol. 32, pp. 1790-1806, November 1997 generates a constant reference voltage irrespective of its temperature by giving positive temperature dependence to a current flowing through a current path formed by two bipolar transistors, an operational amplifier, and a resistive element, and feeding a current in proportion to the aforementioned current through a bipolar transistor in which the voltage between its base and emitter has negative temperature dependence. 
     Further, Japanese Unexamined Patent Application Publications No. 2011-198093 and No. 2011-81517 disclose a technique for reducing errors in a reference voltage caused by the offset voltage of an operational amplifier. 
     SUMMARY 
     The present inventors have found the following problem. The bandgap reference circuit disclosed in H. Neuteboom, B. M. J. Kup, and M. Janssens, “A DSP-based hearing instrument IC”, IEEE J. Solid-State Circuits, vol. 32, pp. 1790-1806, November 1997 needs to accurately generate a current having positive temperature dependence in order to output a constant reference voltage irrespective of its temperature. However, since an operational amplifier is disposed on the current path through which the current having positive temperature dependence flows, errors occur in the current flowing through that current path due to the influence of the offset voltage of the operational amplifier. 
     Therefore, there is a problem that the current generation unit provided in the bandgap reference circuit disclosed in H. Neuteboom, B. M. J. Kup, and M. Janssens, “A DSP-based hearing instrument IC”, IEEE J. Solid-State Circuits, vol. 32, pp. 1790-1806, November 1997 is affected by the offset voltage of the operational amplifier and hence cannot accurately generate the current having positive temperature dependence. As a result, there is a problem that this bandgap reference circuit cannot continuously output a constant reference voltage irrespective of its temperature. Other problems to be solved and novel features will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings. 
     A first aspect of the present invention is a current generation circuit including: first and second bipolar transistors; a first current distribution circuit that makes first and second currents flow between collectors and emitters of the first and second bipolar transistors, respectively, according to a first control voltage; a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a gate of the first NMOS transistor being supplied with a second control voltage; a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a gate of the second NMOS transistor being supplied with the second control voltage; a first resistive element disposed between the second NMOS transistor and the second bipolar transistor; a first operational amplifier that generates the second control voltage according to a drain voltage of the first NMOS transistor and a reference bias voltage; and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage. 
     Another aspect of the present invention is a current generation circuit including: first and second bipolar transistors; a current distribution circuit that makes first and second currents flow between collectors and emitters of the first and second bipolar transistors, respectively, based on a control voltage; a first NMOS transistor disposed between the first bipolar transistor and the current distribution circuit, a gate and a drain of the first NMOS transistor being connected to each other; a second NMOS transistor disposed between the second bipolar transistor and the current distribution circuit, a gate of the second NMOS transistor being connected to the gate and the drain of the first NMOS transistor; a first resistive element disposed between the second NMOS transistor and the second bipolar transistor; and an operational amplifier that generates the control voltage according to a drain voltage of each of the first and second NMOS transistors. 
     According to the above-described aspects, it is possible to provide a current generation circuit capable of generating an accurate current, and a bandgap reference circuit and a semiconductor device including the aforementioned current generation circuit and capable of continuously outputting a constant reference voltage irrespective of their temperature. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, advantages and features will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a circuit diagram showing a current generation circuit according to a first embodiment; 
         FIG. 2  is a circuit diagram showing details of a current distribution circuit provided in the current generation circuit shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram showing a modified example of the current distribution circuit provided in the current generation circuit shown in  FIG. 1 ; 
         FIG. 4  is a circuit diagram showing an operational amplifier provided in the current generation circuit shown in  FIG. 1 ; 
         FIG. 5  is a cross section showing transistors formed in a triple well process; 
         FIG. 6  is a cross section showing transistors formed in a single well process; 
         FIG. 7  is a circuit diagram showing a modified example of the current generation circuit shown in  FIG. 1 ; 
         FIG. 8  is a circuit diagram showing a bandgap reference circuit according to a second embodiment; 
         FIG. 9  shows details of MOS transistors provided on a PTAT current generation loop of the bandgap reference circuit shown in  FIG. 8 ; 
         FIG. 10  is a circuit diagram showing a bandgap reference circuit according to a comparative example; 
         FIG. 11  is a graph showing variation characteristics of reference voltages Vbgr; 
         FIG. 12  is a circuit diagram showing a modified example of the bandgap reference circuit shown in  FIG. 8 ; 
         FIG. 13  is a circuit diagram showing a bandgap reference circuit according to a third embodiment; 
         FIG. 14  is a circuit diagram showing a bandgap reference circuit according to a fourth embodiment; 
         FIG. 15  is a circuit diagram showing a first specific example of the bandgap reference circuit shown in  FIG. 14 ; 
         FIG. 16  is a circuit diagram showing a second specific example of the bandgap reference circuit shown in  FIG. 14 ; 
         FIG. 17  is a circuit diagram showing a bandgap reference circuit according to a fifth embodiment; 
         FIG. 18  is a graph showing characteristics of a reference voltage Vbgr before and after secondary characteristic compensation; 
         FIG. 19  is a circuit diagram showing a current generation circuit according to a sixth embodiment; 
         FIG. 20  is a circuit diagram showing a bandgap reference circuit in which the current generation circuit shown in  FIG. 19  is applied; 
         FIG. 21  is a circuit diagram showing a current generation circuit according to a seventh embodiment; 
         FIG. 22  is a circuit diagram showing a bandgap reference circuit in which the current generation circuit shown in  FIG. 21  is applied; 
         FIG. 23  is a circuit diagram showing a current generation circuit according to an eighth embodiment; 
         FIG. 24  is a circuit diagram showing a bandgap reference circuit in which the current generation circuit shown in  FIG. 23  is applied; 
         FIG. 25  is a circuit diagram showing a reference voltage and reference current generation circuit according to a ninth embodiment; 
         FIG. 26  shows an internal reference current generation circuit provided in the reference voltage and reference current generation circuit shown in  FIG. 25 ; 
         FIG. 27  shows a reference voltage and reference current generation section provided in the reference voltage and reference current generation circuit shown in  FIG. 25 ; and 
         FIG. 28  is a block diagram showing an electronic system including a semiconductor device in which the reference voltage and reference current generation circuit shown in  FIG. 25  is provided. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments are explained hereinafter with reference to the drawings. It should be noted that the drawings are made in a simplified manner, and therefore the technical scope of the embodiments should not be narrowly interpreted based on those drawings. Further, the same components are assigned the same symbols and their duplicated explanations are omitted. 
     In the following embodiments, when necessary, the present invention is explained by using separate sections or separate embodiments. However, those embodiments are not unrelated with each other, unless otherwise specified. That is, they are related in such a manner that one embodiment is a modified example, an application example, a detailed example, or a supplementary example of a part or the whole of another embodiment. Further, in the following embodiments, when the number of elements or the like (including numbers, values, quantities, ranges, and the like) is mentioned, the number is not limited to that specific number except for cases where the number is explicitly specified or the number is obviously limited to a specific number based on its principle. That is, a larger number or a smaller number than the specific number may be also used. 
     Further, in the following embodiments, their components (including operation steps and the like) are not necessarily indispensable except for cases where the component is explicitly specified or the component is obviously indispensable based on its principle. Similarly, in the following embodiments, when a shape, a position relation, or the like of a component(s) or the like is mentioned, shapes or the likes that are substantially similar to or resemble that shape are also included in that shape except for cases where it is explicitly specified or they are eliminated based on its principle. This is also true for the above-described number or the like (including numbers, values, quantities, ranges, and the like). 
     First Embodiment 
       FIG. 1  is a circuit diagram showing a current generation circuit  10  according to a first embodiment. The current generation circuit  10  includes a gate grounding circuit in place of an operational amplifier on a current path whose current value increases as its temperature rises (i.e., a PTAT (Proportional To Absolute Temperature) current generation loop). As a result, the current generation circuit  10  eliminates the need for providing an operational amplifier on the PTAT current generation loop, thus making it possible to accurately generate an output current having positive temperature dependence. Detailed explanations are given hereinafter. 
     As shown in  FIG. 1 , the current generation circuit  10  includes a current distribution circuit  11 , an N-channel type MOS transistor (first NMOS transistor) M 1 , an N-channel type MOS transistor (second NMOS transistor) M 2 , a PNP type bipolar transistor (first bipolar transistor) Q 1 , a PNP type bipolar transistor (second bipolar transistor) Q 2 , a resistive element (first resistive element) R 1 , an operational amplifier (second operational amplifier) A 1 , an operational amplifier (first operational amplifier) A 2 , and a reference bias source  12 . 
     The base and collector of the bipolar transistor Q 1  are connected to each other. The base and collector of the bipolar transistor Q 2  are connected to each other. More specifically, the base and collector of the bipolar transistor Q 1  are both connected to a ground voltage terminal (hereinafter referred to as “ground voltage terminal GND”) to which a ground voltage GND is supplied. The base and collector of the bipolar transistor Q 2  are both connected to the ground voltage terminal GND. In this embodiment, an example where the size (emitter size) of the bipolar transistor Q 2  is n times (n is a positive number no less than 1) as large as the size (emitter size) of the bipolar transistor Q 1  is explained. 
     The source of the MOS transistor M 1  is connected to the emitter of the bipolar transistor Q 1  and the drain of the MOS transistor M 1  is connected to the current distribution circuit  11  through a node N 1 . Further, a control voltage V 1  output from the operational amplifier A 1  is supplied to the gate of the MOS transistor M 1 . The MOS transistor M 1  serves as a cascode (gate grounding circuit). 
     The source of the MOS transistor M 2  is connected to one end of the resistive element R 1  and the drain of the MOS transistor M 2  is connected to the current distribution circuit  11  through a node N 2 . Further, the control voltage V 1  output from the operational amplifier A 1  is supplied to the gate of the MOS transistor M 2 . The other end of the resistive element R 1  is connected to the emitter of the bipolar transistor Q 1 . The MOS transistor M 2  serves as a cascode (gate grounding circuit). 
     The current distribution circuit  11 , which is, for example, a current mirror circuit, outputs a current I 1  corresponding to a control voltage V 2  output from the operational amplifier A 2  and a current I 2  in proportion to the current I 1  to the nodes N 1  and N 2 , respectively. These currents I 1  and I 2  flow between the collectors and emitters of the bipolar transistors Q 1  and Q 2 , respectively. 
     (Details of Current Distribution Circuit  11 ) 
       FIG. 2  is a circuit diagram showing details of the current distribution circuit  11 . As shown in  FIG. 2 , the current distribution circuit  11  includes P-channel type MOS transistors MP 21 , MP 22 , MP 23  and MP 24 , and a bias source  14 . 
     The source of the MOS transistor MP 21  is connected to a power supply voltage terminal (hereinafter referred to as “power supply voltage terminal VDD”) to which a power supply voltage VDD is supplied, and the control voltage V 2  output from the operational amplifier A 2  is supplied to the gate of the MOS transistor MP 21 . The source of the MOS transistor MP 23  is connected to the drain of the MOS transistor MP 21 , and the drain of the MOS transistor MP 23  is connected to the node N 1 . Further, a bias voltage output from the bias source  14  is supplied to the gate of the MOS transistor MP 23 . 
     The source of the MOS transistor MP 22  is connected to the power supply voltage terminal VDD, and the control voltage V 2  output from the operational amplifier A 2  is supplied to the gate of the MOS transistor MP 22 . The source of the MOS transistor MP 24  is connected to the drain of the MOS transistor MP 22 , and the drain of the MOS transistor MP 24  is connected to the node N 2 . Further, the bias voltage output from the bias source  14  is supplied to the gate of the MOS transistor MP 24 . 
     With the above-described configuration, a current I 1  flows to the node N 1  (i.e., between the collector and emitter of the bipolar transistor Q 1 ), and a current I 2 , which is in proportion to the current I 1 , flows to the node N 2  (i.e., between the collector and emitter of the bipolar transistor Q 2 ). 
     For example, when the control voltage V 2  is large, the on-resistance of each of the MOS transistors MP 21  and MP 22  increases. Therefore, the currents I 1  and I 2 , which flow to the nodes N 1  and N 2 , respectively, decrease. On the other hand, when the control voltage V 2  is small, the on-resistance of each of the MOS transistors MP 21  and MP 22  decreases. Therefore, the currents I 1  and I 2 , which flow to the nodes N 1  and N 2 , respectively, increase. 
     (Details of Current Distribution Circuit  11   a ) 
       FIG. 3  is a circuit diagram showing a modified example of the current distribution circuit  11  as a current distribution circuit  11   a . As shown in  FIG. 3 , the current distribution circuit  11   a  includes P-channel type MOS transistors MP 21  and MP 22 , and resistive elements R 21  and R 22 . 
     The source of the MOS transistor MP 21  is connected to the power supply voltage terminal VDD, and the control voltage V 2  output from the operational amplifier A 2  is supplied to the gate of the MOS transistor MP 21 . One end of the resistive element R 21  is connected to the drain of the MOS transistor MP 21  and the other end of the resistive element R 21  is connected to the node N 1 . 
     The source of the MOS transistor MP 22  is connected to the power supply voltage terminal VDD, and the control voltage V 2  output from the operational amplifier A 2  is supplied to the gate of the MOS transistor MP 22 . One end of the resistive element R 22  is connected to the drain of the MOS transistor MP 22  and the other end of the resistive element R 22  is connected to the node N 2 . Further, the drains of the MOS transistors MP 21  and MP 22  are connected to each other. 
     With the above-described configuration, a current I 1  flows to the node N 1  (i.e., between the collector and emitter of the bipolar transistor Q 1 ), and a current I 2 , which is in proportion to the current I 1 , flows to the node N 2  (i.e., between the collector and emitter of the bipolar transistor Q 2 ). 
     For example, when the control voltage V 2  is large, the on-resistance of each of the MOS transistors MP 21  and MP 22  increases. Therefore, the currents I 1  and I 2 , which flow to the nodes N 1  and N 2 , respectively, decrease. On the other hand, when the control voltage V 2  is small, the on-resistance of each of the MOS transistors MP 21  and MP 22  decreases. Therefore, the currents I 1  and I 2 , which flow to the nodes N 1  and N 2 , respectively, increase. 
     The current distribution circuit  11  can be changed or modified as desired to other configurations having functions equivalent to those of the configurations shown in  FIGS. 2 and 3 . 
     Here,  FIG. 1  is referred to again. The operational amplifier A 1  outputs, from its output terminal OUTA, the control voltage V 1  according to a potential difference between a reference bias voltage Vb, which is supplied from the reference bias source  12  to its inverting input terminal INN, and the drain voltage of the MOS transistor M 1  (a voltage at the node N 1 ), which is supplied to its non-inverting input terminal INP. 
     The operational amplifier A 2  outputs, from its output terminal OUTA, the control voltage V 2  according to a potential difference between the reference bias voltage Vb, which is supplied from the reference bias source  12  to its inverting input terminal INN, and the drain voltage of the MOS transistor M 2  (a voltage at the node N 2 ), which is supplied to its non-inverting input terminal INP. 
     Since the two input terminals of the operational amplifier A 1  are connected to an artificial ground and the two input terminals of the operational amplifier A 2  are also connected to the artificial ground, the potential at the nodes N 1  and N 2  are substantially equal to each other. 
     (Details of Operational Amplifiers A 1  and A 2 ) 
       FIG. 4  is a circuit diagram showing details of the operational amplifier A 1 . The configuration of the operational amplifier A 2  is identical to that of the operational amplifier A 1 , and therefore only the operational amplifier A 1  is explained hereinafter. 
     As shown in  FIG. 4 , the operational amplifier A 1  includes P-channel type MOS transistors MP 11  to MP 13 , N-channel type MOS transistors MN 11  to MN 15 , and a constant current source  13 . In this embodiment, an example where an input differential pair is formed by N-channel type MOS transistors is explained. However, the present invention is not limited to such examples. The input differential pair may be formed by P-channel type MOS transistors, provided that it works properly. 
     The constant current source  13  and the MOS transistor MN 14  are connected in series between the power supply voltage terminal VDD and the ground voltage terminal GND. More specifically, the input terminal of the constant current source  13  is connected to the power supply voltage terminal VDD and the output terminal thereof is connected to the drain and gate of the MOS transistor MN 14 . The source of the MOS transistor MN 14  is connected to the ground voltage terminal GND. 
     The source of the MOS transistor MP 11  is connected to the power supply voltage terminal VDD, and the drain and gate of the MOS transistor MP 11  are connected to the drain of the MOS transistor MN 11 . The source of the MOS transistor MN 11  is connected to the drain of the MOS transistor MN 13 , and the gate of the MOS transistor MN 11  is connected to the inverting input terminal INN. 
     The source of the MOS transistor MP 12  is connected to the power supply voltage terminal VDD, and the drain and gate of the MOS transistor MP 12  are connected to the drain of the MOS transistor MN 12 . The source of the MOS transistor MN 12  is connected to the drain of the MOS transistor MN 13 , and the gate of the MOS transistor MN 12  is connected to the non-inverting input terminal INP. 
     The source of the MOS transistor MN 13  is connected to the ground voltage terminal GND, and the gate of the MOS transistor MN 13  is connected to the drain and gate of the MOS transistor MN 14 . 
     The source of the MOS transistor MP 13  is connected to the power supply voltage terminal VDD, and the drain of the MOS transistor MP 13  is connected to the output terminal OUTA. Further, the gate of the MOS transistor MP 13  is connected to the drain and gate of the MOS transistor MP 12 . 
     The source of the MOS transistor MN 15  is connected to the ground voltage terminal GND, and the drain of the MOS transistor MN 15  is connected to the output terminal OUTA. Further, the gate of the MOS transistor MN 15  is connected to the drain and gate of the MOS transistor MN 14 . 
     Note that the configuration of each of the operational amplifiers A 1  and A 2  can be changed or modified as desired to other configurations having functions equivalent to those of the configurations shown in  FIG. 4 . 
     Further, the voltages Vbe 1  and Vbe 2  between the bases and emitters (hereinafter called “base-emitter voltages Vbe 1  and Vbe 2 ”) of the bipolar transistors Q 1  and Q 2 , respectively, have negative temperature dependence. That is, the base-emitter voltages Vbe 1  and Vbe 2  of the bipolar transistors Q 1  and Q 2 , respectively, decrease as their temperature rises. Therefore, when the emitter size of the bipolar transistor Q 2  is larger than that of the bipolar transistor Q 1 , a differential voltage ΔVbe between the voltages Vbe 1  and Vbe 2  (i.e., ΔVbe=Vbe 1 -Vbe 2 ) has positive temperature dependence. That is, the differential voltage ΔVbe increases as the temperature rises. 
     Therefore, even for the current path formed by the bipolar transistor Q 1 , the MOS transistor M 1 , the MOS transistor M 2 , the resistive element R 1 , and the bipolar transistor Q 2 , it is possible to make a current having positive temperature dependence flows therethrough by adjusting the resistance value of the resistive element R 1 , the emitter size of the bipolar transistor Q 2 , and so on. This current path, thorough which a current having positive temperature dependence flows, is hereinafter referred to as “PTAT current generation loop”. 
     No operational amplifier is disposed on this PTAT current generation loop. Therefore, no error is caused in the current flowing through this PTAT current generation loop due to the influence of the offset voltage of an operational amplifier. That is, the current generation circuit  10  can accurately generate a current having positive temperature dependence (e.g., the current I 2 ). 
     Further, in the current generation circuit  10 , the PTAT current generation loop including no operational amplifier is formed by using the PNP type bipolar transistors Q 1  and Q 2 . Therefore, the current generation circuit  10  can be formed even in an environment where no NPN type bipolar transistor can be used. 
       FIG. 5  is a cross section showing transistors formed in a triple well process.  FIG. 6  is a cross section showing transistors formed in a single well process (an N-well process in this example). 
     In the triple well process, the P-sub is isolated from the P-well by forming a Deep-N well in the P-sub. As a result, it is possible to form NPN type bipolar transistors as well as PNP type bipolar transistors. 
     In contrast to this, in the single well process, no Deep-N well is formed in the P-sub. Therefore, although PNP type bipolar transistors can be formed, no NPN type bipolar transistor can be formed in the single well process. 
     The current generation circuit  10  can be formed not only in the triple well process but also in the single well process in which no NPN type bipolar transistor can be used. 
     Note that although an example where the PNP type bipolar transistors Q 1  and Q 2  are provided is explained in this embodiment, the present invention is not limited to such examples. That is, NPN type bipolar transistors Q 1   a  and Q 2   a  may be provided. 
       FIG. 7  is a circuit diagram showing a modified example of the current generation circuit  10  as a current generation circuit  10   a.    
     As shown in  FIG. 7 , in comparison to the current generation circuit  10 , the current generation circuit  10   a  includes NPN type bipolar transistors Q 1   a  and Q 2   a  in place of the PNP type bipolar transistors Q 1  and Q 2 . Note that since the current generation circuit  10   a  includes the NPN type bipolar transistors Q 1   a  and Q 2   a , the current generation circuit  10   a  needs to be formed in a triple well process. The other configuration of the current generation circuit  10   a  is similar to that of the current generation circuit  10 , and therefore its explanation is omitted. 
     The current generation circuit  10   a  provides advantageous effects similar to those of the current generation circuit  10 . 
     Second Embodiment 
       FIG. 8  is a circuit diagram showing a bandgap reference circuit  1  according to a second embodiment. Note that the current generation circuit  10  is applied in the bandgap reference circuit  1 . 
     As shown in  FIG. 8 , the bandgap reference circuit  1  includes, in addition to the current distribution circuit  11 , the MOS transistors M 1  and M 2 , the bipolar transistors Q 1  and Q 2 , the operational amplifiers A 1  and A 2 , the resistive element R 1 , and the reference bias source  12 , which constitute the current generation circuit  10 , a resistive element (second resistive element) R 2  having a fixed resistance, and a bipolar transistor (third bipolar transistor) Q 3 . Since the current generation circuit  10  is already explained above, the configuration other than the current generation circuit  10  is explained hereinafter. 
     The bipolar transistor Q 3  is a PNP type bipolar transistor, i.e., a bipolar transistor having the same conductivity type as that of the bipolar transistors Q 1  and Q 2 . Further, in this example, the size (emitter size) of the bipolar transistor Q 3  is equal to the size (emitter size) of the bipolar transistor Q 1 . 
     The base and collector of the bipolar transistor Q 3  are connected to each other. More specifically, the base and collector of the bipolar transistor Q 3  are both connected to the ground voltage terminal GND. 
     The resistive element R 2  is disposed between the emitter of the bipolar transistor Q 3  and the current distribution circuit  11 . 
     The current distribution circuit  11  outputs, in addition to the currents I 1  and I 2 , a current I 3  in proportion to these currents I 1  and I 2 . This current I 3  flows through the resistive element R 2  and between the collector and emitter of the bipolar transistor Q 3 . 
     Further, the bandgap reference circuit  1  externally outputs a voltage at a node on the current path extending from the current distribution circuit  11  to the resistive element R 2  as a reference voltage Vbgr from its output terminal OUT. 
     Note that the bandgap reference circuit  1  can generate a constant reference voltage Vbgr irrespective of its temperature by making the current I 3  having positive temperature dependence output from the current distribution circuit  11  flow through the bipolar transistor Q 3  whose base-emitter voltage Vbe 3  has negative temperature dependence. 
     Further, in the bandgap reference circuit  1 , the PTAT current generation loop including no operational amplifier is formed by using the PNP type bipolar transistors. Therefore, the bandgap reference circuit  1  can also be formed in a single well process and the like in which no NPN type bipolar transistor can be used. 
     Next, it is explained how much the influence of the offset voltage of an operational amplifier can be reduced by eliminating the operational amplifier from the PTAT current generation loop. Note that the ratio among the emitter sizes of the bipolar transistors Q 1  to Q 2  is expressed as “1:n:1” 
     Firstly, the base-emitter voltages Vbe 1  and Vbe 2  of the bipolar transistors Q 1  and Q 2 , respectively, are expressed by the below-shown Expressions (1) and (2). 
     
       
         
           
             
               
                 
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                     Vbe 
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     In the expressions, Js represents the saturation current density of the bipolar transistor and A represents the unit size. Further, the relation “Vt=kT/q” holds, where: k is Boltzmann constant; T is an absolute temperature; and q is an elementary charge. 
     Note that based on the current path from the ground voltage terminal GND to the gate of the MOS transistor M 1  through the bipolar transistor Q 1  and the current path from the ground voltage terminal GND to the gate of the MOS transistor M 2  through the bipolar transistor Q 2 , a potential difference between the ground voltage terminal GND and the control voltage V 1  of the operational amplifier A 1  is expressed by the below-shown Expression (3).
 
[Expression 3]
 
 Vbe 1+ Vgs 1= Vbe 2+ R 1· I 2+ Vgs 2  (3)
 
     In the expression, Vgs 1  and Vgs 2  represent the voltages between the gates and sources (hereinafter called “gate-source voltages”) of the MOS transistors M 1  and M 2 , respectively; R 1  represents the resistance value of the resistive element R 1 ; and I 2  represents the current value of the current I 2 . 
       FIG. 9  shows details of the MOS transistors M 1  and M 2 . In  FIG. 9 , the resistive component of a current path that is formed between the source and drain of the MOS transistor M 1  by the short channel effect is represented as “ro 1 ”, and similarly, the resistive component of a current path that is formed between the source and drain of the MOS transistor M 2  by the short channel effect is represented as “ro 2 ”. 
     Note that, of the current I 1  supplied to the MOS transistor M 1 , a current I that flows when the square-root law is assumed flows between the source and drain of the MOS transistor M 1 , and a current I 1   ro  flows through the resistive component rot. Further, of the current I 2  supplied to the MOS transistor M 2 , a current I that flows when the square-root law is assumed flows between the source and drain of the MOS transistor M 2 , and a current I 2   ro  flows through the resistive component ro 2 . That is, the current values I 1  and I 2  of the currents I 1  and I 2  are expressed by the below-shown Expressions (4) and (5).
 
[Expression 4]
 
 I 1= I+I 1 ro   (4)
 
[Expression 5]
 
 I 2= I+I 2 ro   (5)
 
     When the offset voltages Vos 1  and Vos 2  of the operational amplifiers A 1  and A 2 , respectively, are not taken into consideration, the voltages Vds 1  and Vds 2  between the sources and drains (hereinafter called “source-drain voltages Vds 1  and Vds 2 ”) of the MOS transistors M 1  and M 2 , respectively, are expressed by the below-shown Expressions (6) and (7).
 
[Expression 6]
 
 Vds 1= Vb −( V 1− Vgs 1)  (6)
 
[Expression 7]
 
 Vds 2= Vb −( V 1− Vgs 2)  (7)
 
     On the other hand, when the offset voltages Vos 1  and Vos 2  of the operational amplifiers A 1  and A 2 , respectively, are taken into consideration, the source-drain voltages Vds 1 _ os  and Vds 2 _ os  of the MOS transistors M 1  and M 2 , respectively, are expressed by the below-shown Expressions (8) and (9).
 
[Expression 8]
 
 Vds 1_ os=Vds 1− Vos 1  (8)
 
[Expression 9]
 
 Vds 2_ os=Vds 2 −Vos 2  (9)
 
     Further, in this case, the current values I 1   ro  and I 2   ro  are expressed by the below-shown Expressions (10) and (11). Note that ro represents the resistance value of each of the resistive components ro 1  and ro 2 . 
     
       
         
           
             
               
                 
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                     ⁢ 
                     10 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                     ⁢ 
                     ro 
                   
                   = 
                   
                     
                       
                         Vds 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       - 
                       
                         Vos 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     ro 
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
             
               
                 
                   [ 
                   
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     11 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                     ⁢ 
                     ro 
                   
                   = 
                   
                     
                       
                         Vds 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                       - 
                       
                         Vos 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     ro 
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
     Note that since the sizes of the MOS transistors M 1  and M 2  are equal to each other, the relations “Vgs 1 =Vgs 2 =Vgs” and “Vds 1 =Vds 2 =Vds” hold. Further, based on Expressions (1), (2), (3), (4), (10) and (11), the below-shown Expression (12) holds. 
     
       
         
           
             
               
                 
                   [ 
                   
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     12 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                         = 
                           
                         ⁢ 
                         
                           
                             
                               Vbe 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             - 
                             
                               Vbe 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                           
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             Vt 
                             · 
                             
                               ln 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     
                                       n 
                                       · 
                                       I 
                                     
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                   
                                   
                                     I 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             Vt 
                             · 
                             
                               ln 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     n 
                                     ⁢ 
                                     
                                       { 
                                       
                                         I 
                                         + 
                                         
                                           
                                             
                                               Vds 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               1 
                                             
                                             - 
                                             
                                               Vos 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               1 
                                             
                                           
                                           ro 
                                         
                                       
                                       } 
                                     
                                   
                                   
                                     I 
                                     + 
                                     
                                       
                                         
                                           Vds 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           2 
                                         
                                         - 
                                         
                                           Vos 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           2 
                                         
                                       
                                       ro 
                                     
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
     Note that since the relation “I 2 =I 3 ” holds, the reference voltage Vbgr is expressed by the below-shown Expression (13). 
     
       
         
           
             
               
                 
                   [ 
                   
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     13 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         Vbgr 
                         = 
                           
                         ⁢ 
                         
                           
                             Vbe 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                           + 
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               2 
                               · 
                               I 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             Vbe 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                           + 
                           
                             
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                             ⁢ 
                             
                               ( 
                               
                                 Vt 
                                 · 
                                 
                                   ln 
                                   ⁡ 
                                   
                                     ( 
                                     
                                       
                                         n 
                                         ⁢ 
                                         
                                           { 
                                           
                                             I 
                                             + 
                                             
                                               
                                                 
                                                   Vds 
                                                   ⁢ 
                                                   
                                                       
                                                   
                                                   ⁢ 
                                                   1 
                                                 
                                                 - 
                                                 
                                                   Vos 
                                                   ⁢ 
                                                   
                                                       
                                                   
                                                   ⁢ 
                                                   1 
                                                 
                                               
                                               ro 
                                             
                                           
                                           } 
                                         
                                       
                                       
                                         I 
                                         + 
                                         
                                           
                                             
                                               Vds 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               2 
                                             
                                             - 
                                             
                                               Vos 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               2 
                                             
                                           
                                           ro 
                                         
                                       
                                     
                                     ) 
                                   
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
     Note that in general, the MOS transistors M 1  and M 2  are designed so that the resistance value ro of each of the resistive components ro 1  and ro 2  of the current paths formed between the sources and drains of the MOS transistors M 1  and M 2 , respectively, by the short channel effect is very high. By referring to Expression (13), it can be understood that when the resistance value ro is very high, the offset voltages Vos 1  and Vos 2  hardly have any effect on the reference voltage Vbgr. That is, the bandgap reference circuit  1  is not substantially affected by the offset voltages Vos 1  and Vos 2  and hence is able to generate an accurate reference voltage Vbgr. 
       FIG. 10  is a circuit diagram showing a bandgap reference circuit  50  according to a comparative example. As shown in  FIG. 10 , the bandgap reference circuit  50  includes a current distribution circuit  51 , an operational amplifier A 52 , bipolar transistors Q 51  to Q 53 , and resistive elements R 51  and R 52 . The current distribution circuit  51 , the operational amplifier A 52 , the bipolar transistors Q 51  to Q 53 , the resistive elements R 51  and R 52 , and nodes N 51  and N 52  correspond to the current distribution circuit  11 , the operational amplifier A 2 , the bipolar transistors Q 1  to Q 3 , the resistive elements R 1  and R 2 , and the nodes N 1  and N 2 , respectively. Note that the operational amplifier A 52  generates a control voltage V 5  according to the potential difference between the nodes N 51  and N 52 . The other configuration of the bandgap reference circuit  50  is similar to that of the bandgap reference circuit  1 , and therefore its explanation is omitted. 
     In the bandgap reference circuit  50 , a PTAT current generation loop is formed by the bipolar transistor Q 51 , the operational amplifier A 52 , the resistive element R 51 , and the bipolar transistor Q 52 . This PTAT current generation loop includes the operational amplifier A 52  disposed thereon. 
     Firstly, the base-emitter voltages Vbe 51  and Vbe 52  of the bipolar transistors Q 51  and Q 52 , respectively, are expressed by the below-shown Expressions (14) and (15). 
     
       
         
           
             
               
                 
                   [ 
                   
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     14 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     Vbe 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     51 
                   
                   = 
                   
                     Vt 
                     · 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             51 
                           
                           
                             Js 
                             · 
                             A 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
             
               
                 
                   [ 
                   
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     15 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     Vbe 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     52 
                   
                   = 
                   
                     Vt 
                     · 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             52 
                           
                           
                             n 
                             · 
                             Js 
                             · 
                             A 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
     Further, assuming that the operational amplifier A 52  is performing a normal feedback operation, the below-shown Expression (16) holds.
 
[Expression 16]
 
 Vbe 51= Vbe 52+ R 51· I 52+ Vos 50  (16)
 
     In the expression, R 51  represents the resistance value of the resistive element R 51 ; I 52  represents the current value of the current I 52 ; and Vos 50  represents the offset voltage of the operational amplifier A 52 . 
     Based on Expressions (14) to (16), the current I 52  is expressed by the below-shown Expression (17). 
     
       
         
           
             
               
                 
                   [ 
                   
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     17 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     52 
                   
                   = 
                   
                     
                       
                         Vt 
                         · 
                         
                           ln 
                           ⁡ 
                           
                             ( 
                             n 
                             ) 
                           
                         
                       
                       - 
                       
                         Vos 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         50 
                       
                     
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       51 
                     
                   
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
           
         
       
     
     Note that since the relation “I 52 =I 53 ” holds, the reference voltage Vbgr 50  is expressed by the below-shown Expression (18). 
     
       
         
           
             
               
                 
                   [ 
                   
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     18 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         
                           Vbgr 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           50 
                         
                         = 
                           
                         ⁢ 
                         
                           
                             Vbe 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             53 
                           
                           + 
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               52 
                               · 
                               I 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             52 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             Vbe 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             53 
                           
                           + 
                           
                             
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 52 
                               
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 51 
                               
                             
                             ⁢ 
                             
                               ( 
                               
                                 
                                   Vt 
                                   · 
                                   
                                     ln 
                                     ⁡ 
                                     
                                       ( 
                                       n 
                                       ) 
                                     
                                   
                                 
                                 - 
                                 
                                   Vos 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   50 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   18 
                   ) 
                 
               
             
           
         
       
     
     From Expression (18), it can be understood that the reference voltage Vbgr 50  could change due to the influence of the offset voltage Vos 50 . That is, the bandgap reference circuit  50  is affected by the offset voltage Vos 50  and hence is not able to generate an accurate reference voltage Vbgr 50 . 
       FIG. 11  is a graph showing variation characteristics of the reference voltages Vbgr and Vbgr 50  of the bandgap reference circuits  1  and  50 , respectively. Note that the configuration of the MOS transistors used for the input differential pair of the operational amplifier A 2  of the bandgap reference circuit  50  is identical to that of the MOS transistors M 1  and M 2  provided in the bandgap reference circuit  1 . 
     As shown in  FIG. 11 , the bandgap reference circuit  1  in which no operational amplifier is present on the PTAT current generation loop has smaller variations than those of the bandgap reference circuit  50  in which an operational amplifier is present on the PTAT current generation loop. 
     Although an example where the PNP type bipolar transistors Q 1 , Q 2  and Q 3  are provided is explained in this embodiment, the present invention is not limited to such examples. That is, NPN type bipolar transistors Q 1   a , Q 2   a  and Q 3   a  may be provided. 
       FIG. 12  is a circuit diagram showing a modified example of the bandgap reference circuit  1  as a bandgap reference circuit  1   a . As shown in  FIG. 12 , in comparison to the bandgap reference circuit  1 , the bandgap reference circuit  1   a  includes NPN type bipolar transistors Q 1   a  to Q 3   a  in place of the PNP type bipolar transistors Q 1  to Q 3 . Note that since the bandgap reference circuit  1   a  includes the NPN type bipolar transistors Q 1   a  to Q 3   a , the bandgap reference circuit  1   a  needs to be formed in a triple well process. The other configuration of the bandgap reference circuit  1   a  is similar to that of the bandgap reference circuit  1 , and therefore its explanation is omitted. 
     The bandgap reference circuit  1   a  provides advantageous effects similar to those of the bandgap reference circuit  1 . 
     Third Embodiment 
       FIG. 13  is a circuit diagram showing a bandgap reference circuit  1   b  according to a third embodiment. Note that the current generation circuit  10  is applied in the bandgap reference circuit  1   b.    
     As shown in  FIG. 13 , in comparison to the bandgap reference circuit  1 , the bandgap reference circuit  1   b  additionally includes a resistive element (third resistive element) R 3  connected in parallel with the resistive element R 2  and the bipolar transistor Q 1 . The other configuration of the bandgap reference circuit  1   b  is similar to that of the bandgap reference circuit  1 , and therefore its explanation is omitted. 
     The bandgap reference circuit  1   b  can divide (i.e., lower) the reference voltage Vbgr from 1.2V to 0.8V, for example, by using the resistive element R 3 , and output the divided (i.e., lowered) reference voltage. 
     Fourth Embodiment 
       FIG. 14  is a circuit diagram showing a bandgap reference circuit  1   c  according to a fourth embodiment. Note that the current generation circuit  10  is applied in the bandgap reference circuit  1   c.    
     As shown in  FIG. 13 , in comparison to the bandgap reference circuit  1 , the bandgap reference circuit  1   c  includes a variable resistance VR 1  in place of the resistive element R 2 . The other configuration of the bandgap reference circuit  1   c  is similar to that of the bandgap reference circuit  1 , and therefore its explanation is omitted. 
     First Specific Example of Bandgap Reference Circuit  1   c    
       FIG. 15  is a circuit diagram showing a first specific example of the bandgap reference circuit  1   c . In the bandgap reference circuit  1   c  shown in  FIG. 15 , a variable resistance VR 1   a  is provided as the variable resistance VR 1 . 
     The variable resistance VR 1   a  includes a resistive element R 2 , a plurality of switches SW 1 s each disposed between a respective one of a plurality of nodes on the resistive element R 2  and the current distribution circuit  11 , and a plurality of switches SW 2 s each disposed between a respective one of the plurality of nodes on the resistive element R 2  and the output terminal OUT. One of the plurality of switches SW 1 s and one of the plurality of switches SW 2 s are turned on by an externally supplied control signal. 
     With this configuration, the variable resistance VR 1   a  can change the resistance value between the output terminal OUT and the bipolar transistor Q 3  by controlling the switches SW 2 s based on the control signal. By doing so, the bandgap reference circuit  1   c  shown in  FIG. 15  can make a fine adjustment to the temperature dependence of the reference voltage Vbgr. Further, the variable resistance VR 1   a  can change the resistance value between the current distribution circuit  11  and the bipolar transistor Q 3  by controlling the switches SW 1 s based on the control signal. By doing so, the variable resistance VR 1   a  can prevent the rise of the upper end voltage (the voltage on the side connected to the current distribution circuit  11 ) of the resistive element R 2  and thereby maintain the normal operation of the current distribution circuit  11 . 
     Second Specific Example of Bandgap Reference Circuit  1   c    
       FIG. 16  is a circuit diagram showing a second specific example of the bandgap reference circuit  1   c.    
     In the bandgap reference circuit  1   c  shown in  FIG. 16 , a variable resistance VR 1   b  is provided as the variable resistance VR 1 . 
     The variable resistance VR 1   b  includes a resistive element R 2  and a plurality of switches SW 2 s each disposed between a respective one a plurality of nodes on the resistive element R 2  and the output terminal OUT. One of the plurality of switches SW 2 s is turned on by an externally supplied control signal. 
     With this configuration, the variable resistance VR 1   b  can change the resistance value between the output terminal OUT and the bipolar transistor Q 3  by controlling the switches SW 2 s based on the control signal. By doing so, the bandgap reference circuit  1   c  shown in  FIG. 16  can make a fine adjustment to the temperature dependence of the reference voltage Vbgr. 
     Fifth Embodiment 
       FIG. 17  is a circuit diagram showing a bandgap reference circuit  1   d  according to a fifth embodiment. Note that the current generation circuit  10  is applied in the bandgap reference circuit  1   d.    
     As shown in  FIG. 17 , in comparison to the bandgap reference circuit  1 , the bandgap reference circuit  1   d  additionally includes a current distribution circuit (second current distribution circuit)  15 , an N-channel type MOS transistor (third NMOS transistor) M 4 , and a resistive element (fourth resistive element) R 4 . 
     The source of the MOS transistor M 4  is connected to one end of the resistive element R 4  and the drain of the MOS transistor M 4  is connected to the current distribution circuit  15 . Further, the control voltage V 1  output from the operational amplifier A 1  is supplied to the gate of the MOS transistor M 4 . The other end of the resistive element R 4  is connected to the ground voltage terminal GND. 
     The current distribution circuit  15 , which is, for example, a current mirror circuit, outputs a current I 4  and a current I 5  in proportion to the current I 4 . The current I 4  flows between the source and drain of the MOS transistor M 4  and through the resistive element R 4 . Further, the current I 5  flows through the resistive element R 2 . That is, both the current I 3  output from the current distribution circuit  11  and the current I 5  output from the current distribution circuit  15  flow through the resistive element R 2 . 
     Further, the bandgap reference circuit  1   d  externally outputs a voltage at a node on the current path extending from the current distribution circuits  11  and  15  to the resistive element R 2  as a reference voltage Vbgr from its output terminal OUT. 
     Note that based on the current path that starts from the ground voltage terminal GND, passes through the bipolar transistor Q 1 , the MOS transistor M 1 , the MOS transistor M 4 , and the resistive element R 4 , and reaches the ground voltage terminal GND again, the below-shown Expression (19) holds.
 
[Expression 19]
 
 Vbe 1+ Vgs 1= Vgs 4+ Vr 4  (19)
 
     In the expression, Vgs 4  represents the gate-source voltage of the MOS transistor M 4 , and Vr 4  represents the voltage generated across the resistive element R 4 . 
     From Expression (19), it appears that the relation “Vbe 1 =Vr 4 ” holds if the sizes of the MOS transistors M 1  and M 4  are equal to each other. However, in reality, since the currents I 1  and I 4 , which flow between the sources and drains of the MOS transistors M 1  and M 4 , respectively, are different from each other, the values Vbe 1  and Vr 4  are different from each other. 
     Note that when the difference between the voltages Vgs 1  and Vgs 4  is expressed as “ΔVgs=Vgs 1 -Vgs 4 ”, the below-shown Expression (20) holds.
 
[Expression 20]
 
 Vr 4=Δ Vgs+Vbe 1  (20)
 
     In the primary approximation (or first-order approximation), the voltage Vr 4  has negative temperature dependence. Therefore, the current I 4 , which is determined by the resistance value R 4  of the resistive element R 4  and the voltage value Vr 4 , (and the current I 5  in proportion to the current I 4 ) has negative temperature dependence. Meanwhile, as described above, the current I 2  (and the current I 3  in proportion to the current I 2 ) has positive temperature dependence. 
     The bandgap reference circuit  1   d  can generate a constant reference voltage Vbgr irrespective of its temperature by making both the current I 3  having positive temperature dependence output from the current distribution circuit  11  and the current I 5  having negative temperature dependence output from the current distribution circuit  15  flow through the resistive element R 2 . 
     Note that it has been known that in general, the base-emitter voltage of a bipolar transistor includes a second-order term. Therefore, for example, when only the configuration in which the negative temperature dependence and the position temperature dependence are cancelled out each other by using the differential voltage ΔVbe having positive temperature dependence and the base-emitter voltage Vbe 3  having negative temperature dependence is employed as in the case of the bandgap reference circuit  1 , the second-order term of the base-emitter voltage Vbe 3  remains. As a result, there is a possibility that the reference voltage Vbgr is unstable for temperature changes. It has been known that it is desirable to include a signal having a third-order characteristic in the reference voltage Vbgr in order to solve this instability. 
     In contrast to this, in the bandgap reference circuit  1   d , the currents I 4  and I 5  are not a function of the voltage Vbe 1  alone but are a function of the voltage Vbe 1  and the differential voltage ΔVbe (see Expression (20)). It has been confirmed that these currents I 4  and I 5  include a third-order term based on simulations and the like. Therefore, since the reference voltage Vbgr includes a signal having a third-order characteristic, the reference voltage Vbgr is stable even when the temperature changes. 
       FIG. 18  is a graph showing characteristics of the reference voltage Vbgr before and after secondary characteristic compensation. In the figure, the broken line represents the reference voltage Vbgr before the secondary characteristic compensation and the solid line represents the reference voltage Vbgr after the secondary characteristic compensation. 
     As shown in  FIG. 18 , while the reference voltage Vbgr before the secondary characteristic compensation is relatively unstable for temperature changes, the reference voltage Vbgr after the secondary characteristic compensation is relatively stable even when the temperature changes. 
     Sixth Embodiment 
       FIG. 19  is a circuit diagram showing a current generation circuit  10   b  according to a sixth embodiment. In comparison to the current generation circuit  10 , the current generation circuit  10   b  includes depletion type MOS transistors M 1   a  and M 2   a  in place of the enhancement type MOS transistors M 1  and M 2 . The other configuration of the current generation circuit  10   b  is similar to that of the current generation circuit  10 , and therefore its explanation is omitted. 
     The current generation circuit  10   b  can lower the gate voltage of the MOS transistors M 1   a  and M 2   a . By doing so, the requirement on the output voltage range for the operational amplifier A 1  is relaxed, thus making it possible to drive the current generation circuit  10   b  at a lower voltage. 
     As described above, the current generation circuit  10   b  can be operated at a lower voltage, while providing advantageous effects similar to those of the current generation circuit  10 . 
     Although an example where the depletion type MOS transistors M 1   a  and M 2   a  are provided in place of the enhancement type MOS transistors M 1  and M 2  is explained in this embodiment, the present invention is not limited to such examples. That is, native type MOS transistors M 1   a  and M 2   a  may be provided. 
     Further, in the current generation circuit  10   b , the PNP type bipolar transistors Q 1  and Q 2  may be replaced by NPN type bipolar transistors Q 1   a  and Q 2   a  as in the case of the example shown in  FIG. 7 . 
     (Bandgap Reference Circuit  1   e  in which Current Generation Circuit  10   b  is Applied) 
       FIG. 20  is a circuit diagram showing a bandgap reference circuit  1   e  in which the current generation circuit  10   b  is applied. 
     As shown in  FIG. 20 , the bandgap reference circuit  1   e  further includes a resistive element R 2  and a bipolar transistor Q 3  in addition to the configuration of the current generation circuit  10   b . That is, the bandgap reference circuit  1   e  is obtained by replacing the current generation circuit  10  by the current generation circuit  10   b  in the bandgap reference circuit  1 . 
     The bandgap reference circuit  1   e  provides advantageous effects similar to those of the bandgap reference circuit  1 . Further, the bandgap reference circuit  1   e  can be operated at a low voltage by using the depletion type or native type MOS transistors M 1   a  and M 2   a.    
     Note that the bandgap reference circuit  1   e  may include a resistive element R 3  connected in parallel with the resistive element R 2  and the bipolar transistor Q 3  as in the case of the example shown in  FIG. 13 , and include a variable resistance VR 1  in place of the resistive element R 2  as in the case of the example shown in  FIG. 14 . Further, the bandgap reference circuit  1   e  may further include a current distribution circuit  15 , a MOS transistor M 4 , and a resistive element R 4  as in the case of the example shown in  FIG. 17 . 
     Further, the bandgap reference circuit  1   e  may include NPN type bipolar transistors Q 1   a , Q 2   a  and Q 3   a  in place of the PNP type bipolar transistors Q 1 , Q 2  and Q 3  as in the case of the example shown in  FIG. 12 . 
     Seventh Embodiment 
       FIG. 21  is a circuit diagram showing a current generation circuit  10   c  according to a seventh embodiment. In comparison to the current generation circuit  10 , the current generation circuit  10   c  additionally includes resistive elements (supplemental resistive elements) R 11  and R 12  between the collectors and emitters of the bipolar transistors Q 1  and Q 2 , respectively. The other configuration of the current generation circuit  10   c  is similar to that of the current generation circuit  10 , and therefore its explanation is omitted. 
     By additionally including the resistive elements R 11  and R 12  between the collectors and emitters of the bipolar transistors Q 1  and Q 2 , respectively, the current generation circuit  10   c  can lower the level of the reference voltage Vbgr, for example, from 1.2V to 0.8V. Further, since currents having negative temperature dependence flow through the resistive elements R 11  and R 12  and currents having positive temperature dependence flow through the bipolar transistors Q 1  and Q 2 , the current generation circuit  10  can consequently generate a constant current I 2  irrespective of its temperature. 
     As described above, the current generation circuit  10   c  can accurately generate the constant current I 2  irrespective of its temperature. 
     In the current generation circuit  10   b , the PNP type bipolar transistors Q 1  and Q 2  may be replaced by NPN type bipolar transistors Q 1   a  and Q 2   a  as in the case of the example shown in  FIG. 7 . 
     (Bandgap Reference Circuit if in which Current Generation Circuit  10   c  is Applied) 
       FIG. 22  is a circuit diagram showing a bandgap reference circuit if in which the current generation circuit  10   c  is applied. 
     As shown in  FIG. 22 , the bandgap reference circuit if further includes a resistive element R 2  in addition to the configuration of the current generation circuit  10   c . That is, the bandgap reference circuit if is obtained by replacing the current generation circuit  10  by the current generation circuit  10   c  and removing the bipolar transistor Q 3  in the bandgap reference circuit  1 . Note that the bipolar transistor Q 3  is removed because since the current generation circuit  10   c  generates the constant current I 2  irrespective its temperature, there is no need to adjust the temperature dependence of the reference voltage Vbgr by using the bipolar transistor Q 3 . 
     The bandgap reference circuit if provides advantageous effects similar to those of the bandgap reference circuit  1 . 
     Note that the bandgap reference circuit if may include a resistive element R 3  connected in parallel with the resistive element R 2 , and include a variable resistance VR 1  in place of the resistive element R 2 . Further, the bandgap reference circuit if may further include a current distribution circuit  15 , a MOS transistor M 4 , and a resistive element R 4 . 
     Further, the bandgap reference circuit if may include NPN type bipolar transistors Q 1   a  and Q 2   a  in place of the PNP type bipolar transistors Q 1  and Q 2 . 
     Eighth Embodiment 
       FIG. 23  is a circuit diagram showing a current generation circuit  10   d  according to an eighth embodiment. As shown in  FIG. 23 , the current generation circuit  10   d  includes a current distribution circuit  11 , N-channel type MOS transistors M 1  and M 2 , PNP type bipolar transistors Q 1  and Q 2 , a resistive element R 1 , and an operational amplifier A 3 . 
     The base and collector of the bipolar transistor Q 1  are both connected to the ground voltage terminal GND. The base and collector of the bipolar transistor Q 2  are both connected to the ground voltage terminal GND. 
     The source of the MOS transistor M 1  is connected to the emitter of the bipolar transistor Q 1  and the drain and gate of the MOS transistor M 1  are connected to a node N 1 . That is, the MOS transistor M 1  is a diode-connected transistor. The source of the MOS transistor M 2  is connected to one end of the resistive element R 1  and the drain of the MOS transistor M 2  is connected to a node N 2 . Further, the gate of the MOS transistor M 2  is connected to the drain and gate of the MOS transistor M 1 . Further, the other end of the resistive element R 1  is connected to the emitter of the bipolar transistor Q 2 . 
     The operational amplifier A 3  has, for example, a function equivalent to that of the operational amplifier A 1  or A 2 , and outputs a control voltage V 3  according to the potential difference between the nodes N 1  and N 2 . The current distribution circuit  11  outputs a current I 1  corresponding to the control voltage V 3  output from the operational amplifier A 3  and a current I 2  in proportion to the current I 1  to the nodes N 1  and N 2 , respectively. 
     The gate potential of the MOS transistors M 1  and M 2  (i.e., the potential at the node N 1 ) has a value expressed as “Vbe 1 +Vgs 1 ”. Note that since a depletion type MOS transistor and a native type MOS transistor cannot be diode-connected, the MOS transistors M 1  and M 2  have to be enhancement type MOS transistors. 
     With this configuration, the current generation circuit  10   d  provides advantageous effects similar to those of the current generation circuit  10 . Further, in comparison to the current generation circuit  10 , the current generation circuit  10   d  can reduce the number of operational amplifiers by one and thereby reduce the circuit size. 
     In the current generation circuit  10   d , the PNP type bipolar transistors Q 1  and Q 2  may be replaced by NPN type bipolar transistors Q 1   a  and Q 2   a  as in the case of the example shown in  FIG. 7 . 
     (Bandgap Reference Circuit  1   g  in which Current Generation Circuit  10   d  is Applied) 
       FIG. 24  is a circuit diagram showing a bandgap reference circuit  1   g  in which the current generation circuit  10   d  is applied. 
     As shown in  FIG. 24 , the bandgap reference circuit  1   g  further includes a resistive element R 2  and a bipolar transistor Q 3  in addition to the configuration of the current generation circuit  10   d . That is, the bandgap reference circuit  1   g  is obtained by replacing the current generation circuit  10  by the current generation circuit  10   d  in the bandgap reference circuit  1 . 
     The bandgap reference circuit  1   g  provides advantageous effects similar to those of the bandgap reference circuit  1 . Further, since the bandgap reference circuit  1   g  can reduce the number of operational amplifiers by one, it can reduce the circuit size. 
     Note that the bandgap reference circuit  1   g  may include a resistive element R 3  connected in parallel with the resistive element R 2  and the bipolar transistor Q 3  as in the case of the example shown in  FIG. 13 , and include a variable resistance VR 1  in place of the resistive element R 2  as in the case of the example shown in  FIG. 14 . Further, the bandgap reference circuit  1   g  may further include a current distribution circuit  15 , a MOS transistor M 4 , and a resistive element R 4  as in the case of the example shown in  FIG. 17 . 
     Further, the bandgap reference circuit  1   g  may include NPN type bipolar transistors Q 1   a , Q 2   a  and Q 3   a  in place of the PNP type bipolar transistors Q 1 , Q 2  and Q 3  as in the case of the example shown in  FIG. 12 . 
     Note that the characteristic features of the current generation circuits  10   b ,  10   c  and  10   d  may be combined with one another. However, the MOS transistors M 1  and M 2  used in the current generation circuit  10   d  have to be enhancement type MOS transistors. 
     Ninth Embodiment 
       FIG. 25  shows a reference voltage and reference current generation circuit  2  according to a ninth embodiment. In the following explanation, an example where the bandgap reference circuit  1   c  is applied in the reference voltage and reference current generation circuit  2  is explained. However, needless to say, any of the above-described other bandgap reference circuits may be applied. 
     As shown in  FIG. 25 , the reference voltage and reference current generation circuit  2  includes a bandgap reference circuit  1   c , an internal reference current generation circuit  16 , a bias voltage generation circuit  17 , a startup circuit  18 , a reference voltage and reference current generation section (reference voltage current generation section)  19 , and a startup detection circuit  20 . The internal reference current generation circuit  16  and the bias voltage generation circuit  17  forms a reference bias source  12 . 
     The internal reference current generation circuit  16  generates a reference current I 0  and outputs the generated reference current I 0  to a node N 3 . The bias voltage generation circuit  17  generates a reference bias voltage Vb based on the reference current I 0  supplied through the node N 3  and the resistive component of the bias voltage generation circuit  17  itself. 
     (Details of Internal Reference Current Generation Circuit  16 ) 
       FIG. 26  is a circuit diagram showing details of the internal reference current generation circuit  16 . 
     As shown in  FIG. 26 , the internal reference current generation circuit  16  includes a startup circuit  21 , P-channel type MOS transistors MP 31  to MP 33 , N-channel type MOS transistors MN 31  and MN 32 , and a resistive element R 31 . 
     The source of the MOS transistor MP 31  is connected to the power supply voltage terminal VDD, and the drain and gate of the MOS transistor MP 31  are connected to nodes N 31  and N 32 , respectively. The source of the MOS transistor MP 32  is connected to the power supply voltage terminal VDD, and the drain and gate of the MOS transistor MP 32  are connected to the node N 32 . The source of the MOS transistor MN 31  is connected to the ground voltage terminal GND, and the drain and gate of the MOS transistor MN 31  are connected to the node N 31 . The source of the MOS transistor MN 32  is connected to one end of the resistive element R 31 , and the drain and gate of the MOS transistor MN 32  are connected to the nodes N 32  and N 31 , respectively. The other end of the resistive element R 31  is connected to the ground voltage terminal GND. The source of the MOS transistor MP 33  is connected to the power supply voltage terminal VDD, and the drain of the MOS transistor MP 33  is connected to the output terminal of the internal reference current generation circuit  16 . Further, the gate of the MOS transistor MP 33  is connected to the node N 32 . Further, the output of the startup circuit  21  is connected to the node N 31 . Note that the startup circuit  21  supplies a startup current to the node N 31  and thereby stabilizes the reference current I 0  when the supply of the power supply voltage is started. 
     With this configuration, the internal reference current generation circuit  16  can generate a stable reference current I 0 . Note that it is possible to generate a plurality of reference currents I 0  having different current values by providing the internal reference current generation circuit  16  with a plurality of MOS transistors MP 33 . 
     Here,  FIG. 25  is referred to again. The bias voltage generation circuit  17  includes, for example, an N-channel type MOS transistor M 3  that is diode-connected between the node N 3  and the ground voltage terminal GND. A reference bias voltage Vb is generated based on the reference current I 0  flowing through the MOS transistor M 3  and the resistive component of the MOS transistor M 3 . 
     The startup circuit  18  starts the operation of the bandgap reference circuit  1   c  by supplying a startup current to the non-inverting input terminal of the operational amplifier A 2  (i.e., the node N 2 ) when the supply of the power supply voltage is started. For example, when the startup circuit  18  detects that the bandgap reference circuit  1   c  is not operating when the supply of the power supply voltage is started, the startup circuit  18  forcefully makes the bandgap reference circuit  1   c  start to operate by controlling the voltage of the non-inverting input terminal of the operational amplifier A 2 . 
     When the reference voltage Vbgr reaches a predetermined level, the startup detection circuit  20  externally transmits information about that state. As a result, for example, an external circuit changes its mode from a suspended mode to an operating mode. 
     The reference voltage and reference current generation section  19  generates a plurality of reference voltages Vref 1  to Vrefp (p is an arbitrary natural number) and a plurality of reference currents Iref 1  to Irefq (q is an arbitrary natural number), which are required for an external circuit, based on the reference voltage Vbgr. 
     (Details of Reference Voltage and Reference Current Generation Section  19 ) 
       FIG. 27  is a circuit diagram showing details of the reference voltage and reference current generation section  19 . 
     As shown in  FIG. 27 , the reference voltage and reference current generation section  19  includes a P-channel type MOS transistor MP 40 , P-channel type MOS transistors MP 41  to MP 4   q , an operational amplifier A 40 , a resistive element R 40 , and a plurality of switches SWs. 
     The source of the MOS transistor MP 40  is connected to the power supply voltage terminal VDD, and the drain of the MOS transistor MP 40  is connected to a node N 41 . Further, the output voltage of the operational amplifier A 40  is supplied to the gate of the MOS transistor MP 40 . One end of the resistive element R 40  is connected to the node N 41  and the other end thereof is connected to the ground voltage terminal GND. Each of the plurality of switched SWs is disposed between a respective one of a plurality of nodes on the resistive element R 40  and a node N 42 . Further, one of the plurality of switched SWs is turned on based on an externally supplied control signal. The operational amplifier A 40  outputs a voltage according to a potential difference between the reference voltage Vbgr and the potential at the node N 42 . 
     The source of each of the MOS transistors MP 41  to MP 4   q  (i.e., q MOS transistors) is connected to the power supply voltage terminal VDD, and the output voltage of the operational amplifier A 40  is supplied to the gate of each of the MOS transistors MP 41  to MP 4   q . Further, reference currents Iref 1  to Irefq are output from the drains of the MOS transistors MP 41  to MP 4   q , respectively. Further, voltages at the plurality of nodes on the resistive element R 40  are output as reference voltages Vref 1  to Vrefp, respectively. 
     As described above, the reference voltage and reference current generation circuit  2  can generate accurate reference voltages Vref 1  to Vrefp and accurate reference currents Iref 1  to Irefq irrespective its temperature by using the bandgap reference circuit  1   c.    
     (Electronic System Including Semiconductor Device  3  in which Reference Voltage and Reference Current Generation Circuit  2  is Provided) 
       FIG. 28  is a block diagram showing an electronic system  4  including a semiconductor device  3  in which the reference voltage and reference current generation circuit  2  is provided. 
     As shown in  FIG. 28 , the electronic system  4  includes a semiconductor device  3 , an external component  5 , an external LDO (Low Drop Out) regulator  6 , and a capacitor C 1 . The semiconductor device  3  includes a reference voltage and reference current generation circuit  2 , a sensor unit  7 , an LDO regulator  8 , and a digital unit  9 . 
     The reference voltage and reference current generation circuit  2  is driven by a power supply voltage supplied form an external LDO regulator  6 , and outputs a reference voltage Vref and a reference current Iref. The LDO regulator  8  is driven by the power supply voltage supplied form the external LDO regulator  6 , and generates an internal power supply voltage according to the reference voltage Vref and the reference current Iref. After its noises are removed by the capacitor C 1 , the generated internal power supply voltage is supplied to internal circuits such as the sensor unit  7  and the digital unit  9 . 
     The sensor unit  7  is driven by the power supply voltage supplied form the external LDO regulator  6  and the internal power supply voltage supplied from the LDO regulator  8 , and covers an externally input analog signal into a digital signal, for example, by using the reference voltage Vref and the reference current Iref and transmits the generated digital signal to the digital unit  9 . The sensor unit  7  also transmits/receives signals to/from the external component  5 . The digital unit  9  preforms certain processing on the digital signal received from the sensor unit  7  and outputs a processing result, for example, to an external circuit. 
     The electronic system  4  is merely an example of a system in which the reference voltage and reference current generation circuit  2  is provided, and can be changed or modified as desired to other circuit configurations in which the reference voltage and reference current generation circuit  2  is provided. 
     As described above, each of the current generation circuits according to the above-described first and sixth to eighth embodiments includes a gate grounding circuit (MOS transistors M 1  and M 2 ) in place of the operational amplifier on the PTAT current generation loop. As a result, each of the current generation circuits according to the above-described first and sixth to eighth embodiments does not require any operational amplifier disposed on the PTAT current generation loop and hence is able to accurately output a current having positive temperature dependence. 
     Further, in each of the current generation circuits according to the above-described first and sixth to eighth embodiments, the PTAT current generation loop including no operational amplifier is formed by using PNP type bipolar transistors. Therefore, they can be formed even in an environment where no NPN type bipolar transistor can be used. 
     Further, in each of the current generation circuits according to the above-described first and sixth to eighth embodiments, the drain voltage of the MOS transistors M 1  and M 2  is fixed by using the operational amplifiers A 1  and A 2 . By doing so, the drain voltage of the MOS transistors M 1  and M 2  is biased at a low voltage, thus making it possible to operate them at a low voltage. 
     Further, each of the bandgap reference circuits according to the above-described second to eighth embodiments can generate a constant reference voltage Vbgr irrespective of its temperature by using the above-described current generation circuit. Further, the reference voltage and reference current generation circuit according to the above-described ninth embodiment and the semiconductor device using it can carry out desired operations by using the above-described bandgap reference circuit. 
     (Differences from Related Art) 
     Each of the configurations disclosed in Japanese Unexamined Patent Application Publications No. 2011-198093 and No. 2011-81517 requires an additional circuit for reducing the influence of the offset voltage of the operational amplifier. Therefore, the circuit size and the cost increase. 
     Further, the configuration disclosed in Japanese Unexamined Patent Application Publication No. 2011-198093 requires the measurement of an offset amount and the compensation control of a reference voltage. Therefore, the cost for tests that are carried out at the time of shipment increases. Further, in the configuration disclosed in Japanese Unexamined Patent Application Publication No. 2011-81517, the connection destinations of the input and output terminals of an operational amplifier are switched. This switching needs to be repeated at a frequency equal to or higher than the cut-off frequency of the subsequent low-pass filter. Therefore, when an external circuit to which the reference voltage is supplied is not in synchronization with the switching timing or when the external circuit is a continuous time circuit, there is a possibility that the characteristic deteriorates due to the residual errors that cannot be removed by the low-pass filter. 
     In contrast to this, the current generation circuits according to the above-described embodiments and the bandgap reference circuits including them do not include any operational amplifier on the current paths through which currents having positive temperature dependence flow in the first place. Therefore, the above-described problems do not occur in the current generation circuits and the bandgap reference circuits according to the above-described embodiments. 
     The present invention made by the inventors has been explained above in a specific manner based on embodiments. However, the present invention is not limited to the above-described embodiments, and needless to say, various modifications can be made without departing from the spirit and scope of the present invention. 
     For example, the semiconductor device according to the above-described embodiment may have a configuration in which the conductivity type (p-type or n-type) of the semiconductor substrate, the semiconductor layer, the diffusion layer (diffusion region), and so on may be reversed. Therefore, when one of the n-type and p-type is defined as a first conductivity type and the other is defined as a second conductivity type, the first and second conductivity types may be the p-type and n-type, respectively. Alternatively, the first and second conductivity types may be the n-type and p-type, respectively. 
     The first to ninth embodiments can be combined as desirable by one of ordinary skill in the art. 
     While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above. 
     Further, the scope of the claims is not limited by the embodiments described above. 
     Furthermore, it is noted that, Applicant&#39;s intent is to encompass equivalents of all claim elements, even if amended later during prosecution.