Patent Publication Number: US-7589512-B2

Title: Load control device

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates to a load control device for controlling a load such as a lamp of a vehicle. 
   Some of the related art load control devices include a triangular wave generation portion, a set voltage generation portion, a comparison portion and a driving control portion. In case a driving instruction signal to instruct driving of a load at a certain level corresponding to a fixed input is supplied, the triangular wave generation portion generates a triangular wave. The set voltage generation portion holds and generates a second set voltage set between the maximum voltage and the minimum voltage of the triangular wave. The comparison portion compares the triangular wave with the second set voltage. The driving control portion thus generates a driving control signal that changes its level with a constant frequency and duty based on the comparison result of the comparison portion. 
   In case a driving instruction signal to instruct stoppage of driving of a load at a certain level corresponding to a fixed input is supplied, the triangular wave generation portion generates a triangular wave. The set voltage generation portion holds and generates a third set voltage lower than the second set voltage. The comparison portion compares the triangular wave with the third set voltage. The driving control portion thus generates a driving control signal that changes its level with a constant frequency and duty based on the comparison result of the comparison portion. 
   In case a driving instruction signal that changes its level with a predetermined frequency and duty corresponding to a pulse input, the triangular wave generation portion generates a first set voltage set between the second set voltage and the third set voltage. The set voltage generation portion selectively generates the second set voltage or third set voltage in correspondence to the frequency and duty of the driving instruction signal. The comparison portion compares the first set voltage with the second set voltage or the third set voltage. The driving control portion thus generates a driving control signal that changes its level with the same frequency and duty as those of the driving control signal (for example, refer to JP-A-2001-148294 (claim 1, [A0019] to [A0053], FIGS. 1 to 3)). 
   In the above related load control device, the driving control portion generates and outputs a driving control signal that changes its level with certain frequency and duty even when the temperature changes. The ON resistance of a power MOSFET as a load driving element is substantially proportional to temperature and heat increases with temperature. Thus, it is necessary to perform heat dissipation design so that heat dissipation will be permitted at the expected maximum operating temperature. As a result, the device scale increases. 
   Also, the above load control device according to the related art uses a headlamp mounted on a vehicle such as a two-wheeled vehicle or a four-wheeled vehicle as a load. The headlamp mounted on a vehicle may be one including a low-beam lamp and a high-beam lamp attached to a single reflector or a single headlamp including a filament for low beams and a filament for high beams. Low beams are preferably turned ON so as not to cause glare on the eyes of the driver of a vehicle in front or an oncoming vehicle, if any, in night driving. High beams are preferably turned ON in the absence of a vehicle in front or an oncoming vehicle in night driving. 
   Some of the above vehicles have a feature called DRL (Daytime Running Light) that forcibly turns ON a headlamp in the daytime also in order to let pedestrians or oncoming cars recognize the presence of the vehicle and prevent possible traffic accidents. Some vehicles equipped with the DRL feature use low beams for DRL while others use high beams for DRL. 
   The related art load control device is composed of ICs and has a capacitor interposed therein as an external component between a connection terminal and a ground so as to set the frequency of a triangular wave generated by the triangular wave generation portion. In case the capacitor has shorted by some cause, the FET as a load driving element is maintained ON. As a result, in case the load is the headlamp, the headlamp is maintained ON with a 100% duty ratio. 
   With a vehicle using low beams for DRL, there are no particular problems even when the headlamp keeps lighting. The headlight lighting state ensures safety of the people on the vehicle, pedestrians and oncoming vehicles so that the lighting state is rather favorable from the viewpoint of a fail-safe design. With a vehicle using high beams for DRL, the headlight lighting state is maintained with a 100% duty ratio. This could cause glare with respect to the driver of a vehicle in front or an oncoming vehicle which leads to a traffic accident. 
   This advantage could be common to any device in general that controls a load based on a generated triangular wave signal. 
   SUMMARY OF THE INVENTION 
   The invention has been accomplished in view of the foregoing circumstances. An object of the invention is to provide a load control device that solves the above problems. 
   In order to solve the above problems, the invention provides a load control device, comprising: 
   a triangular wave generation portion which generates a triangular wave signal by charging/discharging a capacitor based on a constant current supplied from a constant current source; 
   a load control portion which controls a load based on the triangular wave signal; and 
   a temperature compensation element whose characteristic changes with a rise in temperature, which is provided to the constant current source. 
   Preferably, the load control portion includes a pulse width modulation wave generation portion which generates a pulse width modulation wave signal based on the triangular wave signal, and a load driving portion which supplies a load current to the load based on the pulse width modulation wave signal. 
   Preferably, the temperature compensation element is a diode having a characteristic that the reverse-direction leakage current increases with the rise in temperature. 
   Preferably, the temperature compensation element is a thermistor having a characteristic that the resistance value drops with the rise in temperature. 
   In the above configurations, the load control device operates normally at normal temperatures. When the temperature has approached an operating limit, the frequency of a pulse width modulation signal is corrected to decrease the heat value. It is thus unnecessary to make a heat dissipation design to allow heating at an expected maximum operating temperature unlike in the related art practices. As a result, a heat dissipation portion is simplified thus downsizing the load control device. 
   According to the present invention, there is also provided a load control device for controlling a load based on a generated triangular wave signal, comprising: 
   a triangular wave generation portion which generates the triangular wave signal having the same frequency in a first interposing state where a capacitor for setting the frequency of the triangular wave signal is interposed between a power source and an input end of a comparison portion and a second interposing state where the capacitor is interposed between a ground and the input end of the comparison portion, 
   wherein the capacitor is configured to be interposed in either the first interposing state or the second interposing state. 
   Preferably, the load control device further comprises a pulse width modulation wave generation portion which generates a pulse width modulation wave signal based on the triangular wave signal, and a load control portion which controls the load based on the pulse width modulation wave signal. 
   According to the above configurations, it is possible to enhance the safety of a load control device subjected to a short of a capacitor. In case the load control device is mounted on a vehicle and the headlamp of a vehicle is used as a load and low beams are used for DRL, it is possible to assure a fail-safe design. In case high beams are used for DRL, it is possible to enhance the safety. It is unnecessary to manufacture two types of printed circuit boards depending on the type of vehicle using the load control device. This contributes to reduced costs. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects and advantages of the present invention will become more apparent by describing in detail preferred exemplary embodiments thereof with reference to the accompanying drawings, wherein: 
       FIG. 1  is a block diagram showing the configuration of a load control device according to a first embodiment of the invention; 
       FIG. 2  is a circuit diagram as a particular implementation of the configuration of the load control device shown in  FIG. 1 ; 
       FIG. 3  is a timing chart used to illustrate an exemplary operation of the load control device shown in  FIG. 1 ; 
       FIG. 4  shows an exemplary result of comparison between a case where a lamp of a certain rating is actually driven by a load control device according to first embodiment and a case where the same lamp is actually driven in accordance with the related art; 
       FIG. 5  is a circuit diagram showing the configuration of a load control device according to a second embodiment of the invention; 
       FIG. 6  is a circuit diagram showing the configuration of a load control device according to a third embodiment of the invention; 
       FIG. 7  shows an exemplary result of comparison between a case where a lamp of a certain rating is actually driven by a load control device according to the third embodiment and a case where the same lamp is actually driven in accordance with the related art; 
       FIG. 8  is a circuit diagram as an another particular implementation of the configuration of the load control device shown in  FIG. 1 ; 
       FIG. 9  shows an exemplary configuration of the patterns P 1  to P 3  and lands L 1  to L 3  formed on a printed circuit board where the load control device shown in  FIG. 1  is mounted and an exemplary mounting state of the capacitor C 1 ; 
       FIG. 10  is a timing chart used to illustrate an exemplary operation of the load control device shown in  FIG. 1 ; 
       FIG. 11  shows an exemplary configuration of a comparator CP 2  and its peripheral circuitry according to a fifth embodiment of the invention; and 
       FIG. 12  is a timing chart used to illustrate an exemplary operation of the comparator CP 2  and its peripheral circuitry shown in  FIG. 11 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   First Embodiment 
     FIG. 1  is a block diagram showing the configuration of a load control device according to a first embodiment of the invention. The load control device according to the first embodiment includes a triangular wave generation circuit  1 , a pulse width modulation (PWM) wave generation portion  2 , an OR gate  3 , a driving circuit  4 , and a load driving element  5 . The triangular wave generation circuit  1  generates a triangular wave signal of a predetermined frequency and shape by switching between charging and discharging of an external capacitor C 1  for frequency setting. 
   The PWM generation circuit  2  generates a PWM signal (at “H” (High) level or “L” (Low) level) based on a triangular wave signal supplied from a triangular wave generation circuit  1 . The OR gate  3  supplies to the driving circuit  4  a logical value (at “H” (High) level or “L” (Low) level) obtained through logical OR operation of a control signal (at “H” (High) level or “L” (Low) level) supplied externally and a PWM signal (at “H” (High) level or “L” (Low) level) supplied from the PWM generation circuit  2 . The driving circuit  4  amplifies and inverts the logical value supplied from the OR gate  3  and applies a driving voltage to the load driving element  5 . When the driving voltage is applied from the driving circuit  4 , the load driving element  5  supplies a load current to a load  6 . 
     FIG. 2  is a circuit diagram as a particular implementation of the block diagram of a load control device shown in  FIG. 1 . In  FIG. 2 , a portion enclosed by alternate long and short dashed lines constitutes a load control device. Components of the load control device including transistors Q 1  to Q 10 , resistors R 1  to R 12 , comparators CP 1 , CP 2 , an OR gate  3 , a driving circuit  4  and a constant voltage power source  21  are composed of ICs. That is, a capacitor C 1  and an N-channel MOSFET  22  as a load driving element  5  are external components of the ICs. 
   The load control device of this embodiment is a device (low-side switching device) that includes an N-channel MOSFET  22  as a load driving element  5  downstream a lamp  11  as a load  6 . The load control device is mounted for example on a vehicle.  FIG. 2  shows a lamp  11  used as a headlamp which serves as the load  6  shown in  FIG. 1 . The lamp  11  is connected between the power terminal Tb and the output terminal To of the load control device. In  FIG. 2 , a battery  12  mounted on a vehicle is used as a power source. A battery voltage V bat  is connected between the power terminal Tb and the ground terminal Tg of the load control device. 
   In  FIG. 2 , a control signal (at “H” (High) level or “L” (Low) level) (fixed input) outputted from an ECU (Electronic Control Unit)  13  mounted on a vehicle is supplied to the load control device. The ECU controls the fuel injection amount or ignition timing of the engine of a vehicle to control the engine or controls an automatic transmission or traction control. 
   In  FIG. 2 , PNP transistors Q 1  to Q 4 , PNP transistors Q 5  to Q 10 , resistors R 1  to R 9 , a comparator CP 1  and a capacitor C 1  constitute a triangular wave generation circuit  1  shown in  FIG. 1 . The transistors Q 2  to Q 4  constitute a current mirror circuit (constant current source). The emitter area of each of the transistors Q 2  to Q 4  is the same. Thus, collector currents I 2  to I 4  flowing through the collectors of the transistors Q 2  to Q 4  are the same. That is, Expression (1) is satisfied.
 
I2=I3=I4  (1)
 
   where a current I 0  flowing through a resistor R 2  is represented by Expression (2) using a constant voltage Vc, the base-emitter voltage V BE2  of the transistor Q 2  and the resistor R 2 .
 
 I 0=( Vc−V   BE2 )/ R 2  (2)
 
   The transistor Q 1  is used for amplification. A diode D 1  has a p-n junction and a characteristic that a reverse-direction leakage current increases with a rise in temperature. A current I 1  flowing through the resistor R 1  is a current that bypasses part of the current I 0  from the transistor Q 2 . Given the reverse-direction leakage current of the diode D 1  as Ird 1  and the dc current amplification ratio of the transistor Q 1  as hfeq 1 , the current I 1  is represented by the expression (3) in the state that the transistor Q 1  is not saturated.
 
 I 1 =Ird 1 ×hfeq 1  (3)
 
   From Expression (2) and Expression (3), the current I 2  is represented by Expression (4).
 
 I 2 =I 0 −I 1={( Vc−V   BE2 )/ R 2 }−Ird 1 ×hfeq 1  (4)
 
   The collector currents I 2  to I 4  are constant currents as a reference for charging or discharging the capacitor C 1 . The collector current I 4  is a current used to charge the capacitor C 1  with electric charges. 
   The transistors Q 5  to Q 7  constitute a current mirror circuit (constant current source). The resistor R 3  is provided to compensate for the base current of the transistor Q 5 . The ratio of the emitter area of the transistor Q 5  to the total emitter area of the transistors Q 6  and Q 7  is 1:2. The collector current flowing in the collector of the transistor Q 5  is equal to the collector current I 3  of the transistor Q 3 . Further, from Expression (1), the collector current I 3  of the transistor Q 3  is equal to the collector current I 2  of the transistor Q 2 . 
   Thus, the collector current I 6  flowing in the transistor Q 6  is twice each of the collector currents I 2  to I 4  of the transistors Q 2  to Q 4 . That is, Expression (5) is satisfied.
 
 I 6=2 ×I 2=2 ×I 3=2 ×I 4  (5)
 
   The collector current I 6  is a current used to discharge the electric charges accumulated on the capacitor C 1 . 
   The transistor Q 8  is provided to shut down the supply of the collector current I 6  when turned ON. The transistor Q 8  and the resistors R 4  to R 6  generate a reference voltage Vt 1  for generating the triangular wave signal. The resistor R 7  is a base resistor connected between the base of the transistor Q 9  and the output terminal of the comparator CP 1 . 
   The transistor Q 10  and resistors R 8  and R 9  constitute a circuit for turning ON/OFF the transistor Q 8  by way of the output signal of the comparator CP 1 . In the triangular wave generation circuit  1 , the comparator CP 1  compares the voltage VC 1  of the capacitor C 1  with a reference voltage Vt 1  based on a constant current obtained by a current mirror circuit (constant current source) composed of transistors Q 2  to Q 4 , a current mirror circuit (constant current source) composed of transistors Q 5  to Q 7  and a resistor R 2  respectively connected to a constant voltage Vc. The triangular wave generation circuit  1  thus switches between charging and discharging of the capacitor C 1  to generate a triangular wave signal. 
   The comparator CP 2  and resistors R 10  and R 11  constitute a PWM generation circuit  2  shown in  FIG. 1 . The resistors R 10  and R 11  generate a reference voltage Vk for generating the PWM signal. The reference voltage Vk is represented by Expression (6).
 
 Vk=Vc×R 11/( R 10 +R 11)  (6)
 
   In the PWM generation circuit  2 , the comparator CP 2  compares a triangular wave signal supplied from the triangular wave generation circuit  1  with the reference voltage Vk. The PWM generation circuit  2  thus generates a PWM signal. 
   The resistor R 12  is interposed between a power source Vc and an input terminal Ti and functions as a pull-up resistor to stably hold the potential of a control signal supplied from the ECU  13 . The constant voltage power source  21  generates a constant voltage Vc from a battery voltage V bat  supplied from a battery  12  and supplies the constant voltage Vc to each part of the load control device. The MOSFET  22  has its gate connected to the output terminal of the driving circuit  4  and its drain connected to the output terminal To of the load control device and its source grounded. 
   Operation of the load control device of this configuration will be described referring to the timing chart shown in  FIG. 3 . As shown in  FIG. 3 , in case the control signal supplied from the ECU  13  is High, the output signal of the OR gate  3  is always High. The driving circuit  4  amplifies and inverts the logical value of High level supplied from the OR gate  3  and applies a Low driving voltage to the MOSFET  22 . While the Low driving voltage is applied from the driving circuit  4 , the MOSFET  22  has its gate voltage driven Low so that it is turned OFF. In this case, the source voltage of the MOSFET  22  is almost equal to the battery voltage V bat  so that a load current does not flow into a load  6 , or a lamp  11  in this example as shown in  FIG. 3 . 
   As shown in  FIG. 3 , in case the control signal supplied from the ECU  13  is Low, the output signal of the comparator CP 2  of the PWM generation circuit  2  serves as an output signal of the OR gate  3 . 
   In case the voltage VC 1  of the capacitor C 1  is lower than the reference voltage Vt 1  at a certain time, the output signal of the comparator CP 1  is driven Low and the transistors Q 9  and Q 10  are turned OFF. While the transistor Q 9  is turned OFF, the reference voltage Vt 1  is the upper limit voltage Vb of the triangular wave signal as shown in  FIG. 3 . The upper limit voltage Vb is represented by Expression (7).
 
 Vb=Vc×R 5/( R 4 +R 5)  (7)
 
   When the transistor Q 10  is turned OFF, a current flows into the base of the transistor Q 8  from the resistor R 9  so that the transistor Q 8  is turned ON. When the transistor Q 8  is turned ON, supply of a collector current I 6  is stopped. As a result, a collector current I 4  flows, which charges the capacitor C 1  with electric charges and the voltage across the terminals of the capacitor C 1  increases. The voltage VC 1  of the capacitor C 1  rises. 
   When the voltage VC 1  of the capacitor C 1  exceeds the upper limit voltage Vb even by a small amount, the output signal of the comparator CP 1  is driven High, which turns ON the transistors Q 9  and Q 10 . While the transistor Q 9  is turned ON, without considering the saturation voltage of the transistor Q 9 , the reference voltage Vt 1  becomes a resistance dividing voltage of the composite resistance value of the resistors R 5  and R 6  and the resistance value of the resistor R 4 , and as shown in  FIG. 3 , becomes the lower limit voltage Va of the triangular wave signal. The lower limit voltage Va is represented by Expression (8).
 
 Va=Vc ×( R 5 ×R 6)/( R 4 ×R 5 +R 4 ×R 6 +R 5 ×R 6)  (8)
 
   When the transistor Q 10  is turned ON, a current does not flow from the resistor R 9  to the base of the transistor Q 8 . This turns OFF the transistor Q 8 . When the transistor Q 8  is turned OFF, supply of the collector current I 6  starts. As mentioned above, the collector current I 6  is double the collector current I 4 . Thus, the electric charges accumulated on the capacitor C 1  are discharged with a current value obtained by subtracting the collector current I 4  from the collector current I 6 . When the electric charges accumulated on the capacitor C 1  are discharged, the voltage across the terminals of the capacitor C 1  drops. Thus, the voltage VC 1  of the capacitor C 1  drops. When the voltage VC 1  of the capacitor C 1  drops below the lower limit voltage Va even by a small amount, the output signal of the comparator CP 1  is inverted to Low. These operations are repeated to generate the triangular wave signal shown in  FIG. 3 . 
   When the triangular wave signal supplied from the triangular wave generation circuit  1 , that is, the voltage VC 1  of the capacitor C 1  exceeds the reference voltage Vk, the output signal of the comparator CP 2  of the PWM generation circuit  2  is driven Low. When the voltage VC 1  of the capacitor C 1  drops below the reference voltage Vk, the output signal of the comparator CP 2  is driven High. These operations are repeated to generate the PWM signal shown in  FIG. 3 . 
   The output signal of the comparator CP 2 , that is, the PWM signal is supplied to the driving circuit  4  via the OR gate  3 . The driving circuit  4  amplifies and inverts the logical value of the PWM signal supplied from the OR gate  3  and applies a driving voltage to the MOSFET  22 . While the driving voltage applied from the driving circuit  4  is High, the MOSFET  22  has its gate voltage driven High so that it is turned ON. The source voltage of the MOSFET  22  is almost equal to the ground voltage. As shown in  FIG. 3 , a load current flows into a load  6 , or a lamp  11  in this example. 
   In case the driving voltage from the driving circuit  4  is Low, the MOSFET  22  is turned OFF. Thus, the source voltage of the MOSFET  22  rises until it is almost equal to the battery voltage V bat . As shown in  FIG. 3 , a load current does not flow into a load  6 , or a lamp  11  in this example. 
   These operations are repeated to drive the lamp  11  to blink based on the supplied driving voltage. 
   The period T of the triangular wave signal will be described. While the transistor Q 1  is not saturated, the current I 1  is represented by Expression (3) above. The period T of the triangular wave signal is represented by Expression (9). 
   
     
       
         
           
             
               
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   The voltage V BE2  across the base and emitter of the transistor Q 2  has a temperature characteristic of around 2 mV/° C. so that it may be regarded as almost constant. Thus, the period T of the triangular wave signal is influenced by the leakage current Ird 1  of the diode D 1  and the dc current amplification ratio hfeq 1  of the transistor Q 1 . The reverse-direction leakage current Ird 1  of the diode D 1 , similar to the dc current amplification ratio hfeq 1  of the transistor Q 1 , has a characteristic that it increases with a rise in temperature. As the temperature rises, the period T of the triangular wave signal becomes longer than Expression (9). In other words, the frequency of the triangular wave signal drops. 
   When the current I 1  increases and the transistor Q 1  is saturated, the saturation voltage is almost 0 volts so that the current I 1  is represented by 
   Expression (10).
 
 I 1 =V   BE2   /R 1  (10)
 
   In case the reverse-direction current Ird 1  of the diode D 1  increases and the transistor Q 1  is saturated, it is necessary to apply Expression (10) in place of Expression (3) for the current I 1 . The period T of the triangular wave signal thus becomes constant as represented by Expression (11). As a result, even when the reverse-direction Ird 1  of the diode D 1  has increased, the period T of the triangular wave signal does not become longer than necessary. 
   
     
       
         
           
             
               
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                 ) 
               
             
           
         
       
     
   
     FIG. 4  shows an exemplary result of comparison between a case where a lamp of a certain rating is actually driven by a load control device of the above configuration and a case where the same lamp is actually driven in accordance with the related art. In this comparison experiment, setting is made so that the frequency of a PWM signal is 100 Hz at a temperature of 25° C. both in First embodiment and related art example. The duty ratio of the PWM signal is 50%, the ON resistance of the MOSFET as a load driving element  5  at 25° C. is set to 30 mΩ, and the ON resistance temperature coefficient of the MOSFET is 0.8%/° C. 
   In  FIG. 4 , the switching heat refers to a total of heat generated when the MOSFET is turned ON and turned OFF. The ON heat refers to the heat in a period where the MOSFET is on past the turn-on period until it shifts to the turn-off period. The total heat is a total of switching heat and ON heat, that is, heat of the actual MOSFET. From  FIG. 4 , it is understood that the total heat increases with a rise in temperature in the related art example while the total heat drops at 125° C., an operation limit temperature in First embodiment. 
   In this way, according to First embodiment of the invention, A diode D 1  having a characteristic that the reverse-direction leakage current increases with a rise in temperature, a fixed resistor R 1  and a transistor Q 1  for amplification are added to a transistor Q 2  of the current mirror circuit (constant current source). Thus, the load control device operates normally at normal temperatures. When the temperature has exceeded 75° C. and approached an operation limit, the frequency of the PWM signal is corrected to decrease heat. It is thus unnecessary to make a heat dissipation design to allow heating at an expected maximum operating temperature unlike in the related art practices. As a result, a heat dissipation portion is simplified thus downsizing the load control device. 
   Second Embodiment 
   While the diode D 1  having a p-n junction is used in the first embodiment, the invention is not limited thereto. For example, a Schottky barrier diode may be used instead of the diode D 1 . In case a high temperature leakage current that flows with a rise in the temperature of a Schottky barrier diode is large enough, a PNP transistor Q 1  may be omitted as shown in  FIG. 5 . 
     FIG. 5  is a circuit diagram showing the configuration of a load control device according to Second embodiment of the invention. In  FIG. 5 , a same component as that in  FIG. 2  is given a same sign and the corresponding description is omitted. The load control device shown in  FIG. 5  differs from that shown in  FIG. 2  in that a Schottky barrier diode D 2  is provided anew instead of a diode D 1  having a p-n junction and a PNP transistor Q 1  is removed. Operation of the load control device in this example is almost the same as that in First embodiment so that its description is omitted. 
   In this way, according to Second embodiment of the invention, a Schottky barrier diode D 2  having a characteristic that a high temperature leakage current increases substantially with a rise in temperature and a fixed resistor R 1  are added to a transistor Q 2  of the current mirror circuit (constant current source). This provides almost the same effect as that of First embodiment. 
   Third Embodiment 
     FIG. 6  is a circuit diagram showing the configuration of a load control device according to the third embodiment of the invention. 
   In  FIG. 6 , a same component as that in  FIG. 2  is given a same sign and the corresponding description is omitted. The load control device shown in  FIG. 6  differs from that shown in  FIG. 2  in that a thermistor TH 1  is provided anew instead of PNP transistor Q 1  and a diode D 1  is removed. 
   The thermistor TH 1  has a characteristic that the resistance value drops with a rise in temperature. The thermistor TH 1  is called an NTC (negative temperature coefficient) thermistor where a change in temperature is proportional to a change in resistance value. The thermistor TH 1  is produced for example by mixing oxides such as nickel (Ni), manganese (Mn), cobalt (Co) and iron (Fe) and sintering the resulting mixture. 
   Referring to  FIG. 6 , a thermistor TH 1 , transistors Q 2  to Q 10 , resistors R 1  to R 9 , a comparator CP 1  and a capacitor C 1  constitute a triangular wave generation circuit  1  shown in  FIG. 1 . The transistors Q 2  to Q 4  constitute a current mirror circuit (constant current source). The emitter area of each of the transistors Q 2  to Q 4  is the same. Thus, a collector current I 2  to I 4  flowing through each of the collectors of the transistors Q 2  to Q 4  is the same. That is, Expression (1) is satisfied.
 
I2=I3=I4  (1)
 
where a current I 0  flowing through a resistor R 2  is represented by Expression (2) using a constant voltage Vc, the base-emitter voltage V BE2  of the transistor Q 2  and the resistor R 2 .
 
 I 0=( Vc−V   BE2 )/ R 2  (2)
 
   A current I 1  flowing through the resistor R 1  is a current that bypasses part of the current I 0  from the transistor Q 2 . Given the resistance value of the thermistor TH 1  as Rth 1 , the current I 1  is represented by the expression (12).
 
 I 1 =V   BE2 /( Rth 1 +R 1)  (12)
 
   From Expression (2) and Expression (12), the current I 2  is represented by Expression (13).
 
 I 2 =I 0 −I 1={( Vc−V   BE2 )/ R 2 }−{V   BE2 /( Rth 1 +R 1)}  (13)
 
   The collector currents I 2  to I 4  are constant currents as a reference for charging or discharging the capacitor C 1 . The collector current I 4  is a current used to charge the capacitor C 1  with electric charges. 
   The configuration of a load control device according to Third embodiment of the invention after a transistor Q 5  is the same as that of the load control device according to First embodiment (refer to  FIG. 2 ) described earlier so that the corresponding description is omitted. The operation of the load control device of the above configuration is substantially the same as the operation of the load control device explained above with reference to the timing chart shown in  FIG. 3 . 
   The period T of the triangular wave signal generated by the triangular wave generation circuit  1  is represented by Expression (14). 
   
     
       
         
           
             
               
                 T 
                 = 
                 
                   
                     2 
                     × 
                     
                       ( 
                       
                         Vb 
                         - 
                         Va 
                       
                       ) 
                     
                     × 
                     C 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       1 
                       / 
                       I 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   = 
                   
                     [ 
                     
                       2 
                       × 
                       Vc 
                       × 
                       
                         
                           { 
                           
                             
                               ( 
                               
                                 
                                   R 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     5 
                                     / 
                                     
                                       ( 
                                       
                                         
                                           R 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           4 
                                         
                                         + 
                                         
                                           R 
                                           ⁢ 
                                           
                                               
                                           
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                                           5 
                                         
                                       
                                       ) 
                                     
                                   
                                 
                                 - 
                                 
                                   
                                     ( 
                                     
                                       R 
                                       ⁢ 
                                       
                                           
                                       
                                       ⁢ 
                                       5 
                                       × 
                                       R 
                                       ⁢ 
                                       
                                           
                                       
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                                       6 
                                     
                                     ) 
                                   
                                   / 
                                   
                                     ( 
                                     
                                       
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                                         ⁢ 
                                         
                                             
                                         
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                                         4 
                                         × 
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                                         ⁢ 
                                         
                                             
                                         
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                                         5 
                                       
                                       + 
                                       
                                         R 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         4 
                                         × 
                                         R 
                                         ⁢ 
                                         
                                             
                                         
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                                         6 
                                       
                                       + 
                                       
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                                         ⁢ 
                                         
                                             
                                         
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                                         5 
                                         × 
                                         R 
                                         ⁢ 
                                         
                                             
                                         
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                                         6 
                                       
                                     
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                               } 
                             
                             × 
                             C 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           ] 
                         
                         / 
                         
                           [ 
                           
                             
                               { 
                               
                                 
                                   
                                     ( 
                                     
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                                       - 
                                       
                                         V 
                                         
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                                           ⁢ 
                                           
                                               
                                           
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                                           2 
                                         
                                       
                                     
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                                   R 
                                 
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                                 1 
                               
                               } 
                             
                             - 
                             
                               
                                 V 
                                 
                                   BE 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                               / 
                               
                                 ( 
                                 
                                   
                                     Rth 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                   
                                   + 
                                   
                                     R 
                                     ⁢ 
                                     
                                         
                                     
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                 ( 
                 14 
                 ) 
               
             
           
         
       
     
   
   The voltage V BE2  across the base and emitter of the transistor Q 2  has a temperature characteristic of around 2 mV/° C. so that it may be regarded as almost constant. Thus, the period T of the triangular wave signal is influenced only by the resistance value Rh 1  of the thermistor TH 1 . The thermistor TH 1  has a characteristic that the resistance value drops with a rise in temperature. As the temperature rises, the period T of the triangular wave signal becomes longer than Expression (14). In other words, the frequency of the triangular wave signal drops. 
     FIG. 7  shows an exemplary result of comparison between a case where a lamp of a certain rating is actually driven by a load control device of the above configuration and a case where the same lamp is actually driven in accordance with the related art. In this comparison experiment, an NTC thermistor is used as a thermistor TH 1  with the resistance value Rth 1  at a temperature of 25° C. being 100 kΩ and the B constant being 4500. The other conditions and meanings of words shown in  FIG. 7  are the same as those of First embodiment described referring to  FIG. 4 . From  FIG. 7 , it is understood that, while the total heat increases with a rise in temperature in the related art example, increase in the total heat is suppressed despite a rise in temperature in the third embodiment. 
   In this way, according to The third embodiment of the invention, a thermistor TH 1  having a characteristic that the resistance value drops with a rise in temperature and a fixed resistor R 1  are added to a transistor Q 2  of the current mirror circuit (constant current source). This provides almost the same effect as that of the first embodiment. 
   Fourth Embodiment 
     FIG. 8  is a circuit diagram as an another particular implementation of the block diagram of a load control device shown in  FIG. 1 . In  FIG. 8 , a portion enclosed by alternate long and short dashed lines constitutes a load control device. Components of the load control device including transistors Q 101  to Q 109 , resistors R 101  to R 11 , comparators CP 101 , CP 102 , an OR gate  3 , a driving circuit  4  and a constant voltage power source  121  are composed of ICs. That is, a capacitor C 101  and an N-channel MOSFET  122  as a load driving element  5  are external components of the ICs. 
   The load control device in this embodiment is a device (low-side switching device) that includes an N-channel MOSFET  122  as a load driving element  5  downstream a lamp  111  as a load  6 . The load control device is mounted for example on a vehicle. As the load  6  shown in  FIG. 1 , a lamp  111  used as a headlamp is used in  FIG. 8 . The lamp  111  is connected between the power terminal Tb and the output terminal To of the load control device. In  FIG. 8 , a battery  112  mounted on a vehicle is used as a power source. A battery voltage V bat  is connected between the power terminal Tb and the ground terminal Tg of the load control device. 
   In  FIG. 8 , a control signal (at “H” (High) level or “L” (Low) level) (fixed input) outputted from an ECU (Electronic Control Unit)  113  mounted on a vehicle is supplied to the load control device. The ECU is designed to control the fuel injection amount or ignition timing of the engine of a vehicle to control the engine or control an automatic transmission or traction control. 
   In  FIG. 8 , PNP transistors Q 101  to Q 103 , PNP transistors Q 104  to Q 109 , resistors R 101  to R 108 , a comparator CP 101  and a capacitor C 101  constitute a triangular wave generation circuit  1  shown in  FIG. 1 . The transistors Q 101  to Q 103  constitute a current mirror circuit. The emitter area of each of the transistors Q 101  to Q 103  is the same. Thus, collector currents I 1  to I 3  flowing through the collectors of the transistors Q 101  to Q 103  are the same. That is, Expression (1) is satisfied.
 
I1=I2=I3  (1)
 
where a collector current I 1  is represented by Expression (2) using a constant voltage Vc, the base-emitter voltage V BE1  of the transistor Q 1  and the resistor R 1 .
 
 I 1=( Vc−V   BE1 )/ R 1  (2)
 
   The collector currents I 1  to I 3  are constant currents as a reference for charging or discharging the capacitor C 101 . The collector current I 3  is a current used to discharge the electric charges accumulated on the capacitor C 101  or charge the capacitor C 101  with electric charges. 
   The transistors Q 104  to Q 106  constitute a current mirror circuit (constant current source). The resistor R 102  is provided to compensate for the base current of the transistor Q 104 . The ratio of the emitter area of the transistor Q 104  to the total emitter area of the transistors Q 105  and Q 106  is 1:2. The collector current flowing in the collector of the transistor Q 104  is equal to the collector current I 2  of the transistor Q 102 . Further, from Expression (1), the collector current I 2  of the transistor Q 102  is equal to the collector current I 1  of the transistor Q 101 . 
   Thus, the collector current I 5  flowing in the transistor Q 105  is twice each of the collector currents I 1  to  13  of the transistors Q 101  to Q 103 . That is, Expression (3) is satisfied.
 
 I 5=2 ×I 1=2 ×I 2=2 ×I 3  (3)
 
   The collector current I 5  is a current used to charge the capacitor C 101  with electric charges or discharge the electric charges accumulated on the capacitor C 101 . 
   The transistor Q 107  is provided to shut down the supply of the collector current I 5  when turned ON. The transistor Q 108  and the resistors R 103  to R 105  generate a reference voltage Vt 1  for generating the triangular wave signal. The resistor R 106  is a base resistor connected between the base of the transistor Q 108  and the output terminal of the comparator CP 101 . 
   The transistor Q 109  and resistors R 107  and R 108  constitute a circuit for turning ON/OFF the transistor Q 107  by way of the output signal of the comparator CP 1 . In the triangular wave generation circuit  1 , the comparator CP 101  compares the voltage VC 1  of the capacitor C 101  with a reference voltage Vt 1  based on a constant current obtained by a current mirror circuit composed of transistors Q 101  to Q 103 , a current mirror circuit composed of transistors Q 104  to Q 106  and a resistor R 101  respectively connected to a constant voltage Vc. The triangular wave generation circuit  1  thus switches between charging and discharging of the capacitor C 101  to generate a triangular wave signal. 
   The comparator CP 102  and resistors R 109  and R 110  constitute a PWM generation circuit  2  shown in  FIG. 1 . The resistors R 109  and R 110  generate a reference voltage Vk for generating the PWM signal. The reference voltage Vk is represented by Expression (15).
 
 Vk=Vc×R 110/( R 109 +R 110)  (15)
 
   In the PWM generation circuit  2 , the comparator CP 102  includes a triangular wave signal supplied from the triangular wave generation circuit  1  with the reference voltage Vk. The PWM generation circuit  2  thus generates a PWM signal. 
   The resistor R 111  is interposed between a power source Vc and an input terminal Ti and functions as a pull-up resistor to stably hold the potential of a control signal supplied from the ECU  113 . The constant voltage power source  121  generates a constant voltage Vc from a battery voltage V bat  supplied from a battery  112  and supplies the constant voltage Vc to each part of the load control device. The MOSFET  122  has its gate connected to the output terminal of the driving circuit  4  and its drain connected to the output terminal To of the load control device and its source grounded. 
   Operation of the load control device of this configuration will be described. It is assumed that the load control device of the above configuration includes an IC where transistors Q 101  to Q 109 , resistors R 101  to R 111 , comparator CP 101 , CP 102 , an OR gate  3 , a driving circuit  4  and a constant voltage power source  121  are arranged on its internal chip, a capacitor C 101  and a MOSFET  122  mounted on a single printed circuit board. 
   For example as shown in  FIG. 9 , on this printed circuit board is formed patterns P 1  to P 3  for mounting a capacitor C 101  as an external component of the IC. At the ends of the patterns P 1  to P 3  are respectively formed lands L 1  to L 3 . The pattern P 1  is connected to a power line that connects to the output terminal of the constant voltage power source  121  shown in  FIG. 8 . The pattern P 2  is connected to the non-inverted input terminal of the comparator CP 101  shown in  FIG. 8 . The pattern P 3  is connected to the ground line shown in  FIG. 8 . 
   (1) In case a vehicle where this load control device is mounted uses low beams for DRL: 
   In this case, as shown in  FIG. 9 , one terminal of the capacitor C 101  is inserted into a through hole made almost in the center of the land L 1  formed at an end of the pattern P 1  and the other terminal of the capacitor C 101  is inserted into a through hole made almost in the center of the land L 2  formed at an end of the pattern P 2 . Next, for example by melting cream solder previously applied on the lands L 1  and L 2 , one terminal of the capacitor C 101  and the land L 1  are electrically connected to each other and the other terminal of the capacitor C 101  and the land L 2  are electrically connected to each other. 
   Next, operation of the load control device of the above configuration will be described referring to the timing chart shown in  FIG. 10 . As shown in  FIG. 10 , in case the control signal supplied from the ECU  113  is High, the output signal of the OR gate  3  is always High. The driving circuit  4  amplifies and inverts the logical value of High level supplied from the OR gate  3  and applies a Low driving voltage to the MOSFET  122 . While the Low driving voltage is applied from the driving circuit  4 , the MOSFET  122  has its gate voltage driven Low so that it is turned OFF. In this case, the source voltage of the MOSFET  122  is almost equal to the battery voltage V bat  so that a load current does not flow into a load  6 , or a lamp  111  in this example as shown in  FIG. 10 . 
   As shown in  FIG. 10 , in case the control signal supplied from the ECU  113  is Low, the output signal of the comparator CP 102  of the PWM generation circuit  2  serves as an output signal of the OR gate  3 . 
   In case the voltage VC 1  of the capacitor C 101  is lower than the reference voltage Vt 1  at a certain time, the output signal of the comparator CP 101  is driven Low and the transistors Q 108  and Q 109  are turned OFF. While the transistor Q 108  is turned OFF, the reference voltage Vt 1  is the upper limit voltage Vb of the triangular wave signal as shown in  FIG. 10 . The upper limit voltage Vb is represented by Expression (16).
 
 Vb=Vc×R 104/( R 103 +R 104)  (16)
 
   When the transistor Q 109  is turned OFF, a current flows into the base of the transistor Q 107  from the resistor R 108  so that the transistor Q 107  is turned ON. When the transistor Q 7  is turned ON, supply of a collector current I 5  is stopped. As a result, a collector current I 3  flows, which discharges the electric charges accumulated on the capacitor C 101  and the voltage across the terminals of the capacitor C 101  decreases. The voltage VC 1  of the capacitor C 101  rises. 
   When the voltage VC 1  of the capacitor C 101  exceeds the upper limit voltage Vb even by a small amount, the output signal of the comparator CP 101  is driven High, which turns ON the transistors Q 108  and Q 109 . While the transistor Q 108  is turned ON, without considering the saturation voltage of the transistor Q 108 , the reference voltage Vt 1  becomes a resistance dividing voltage of the composite resistance value of the resistors R 104  and R 105  and the resistance value of the resistor R 103 , and as shown in  FIG. 10 , becomes the lower limit voltage Va of the triangular wave signal. The lower limit voltage Va is represented by Expression (17).
 
 Va=Vc ×( R 104 ×R 105)/( R 103 ×R 104 +R 103 ×R 105 +R 104 ×R 105)  (17)
 
   When the transistor Q 109  is turned ON, a current does not flow from the resistor R 8  to the base of the transistor Q 107 . This turns OFF the transistor Q 107 . When the transistor Q 107  is turned OFF, supply of the collector current I 5  starts. The collector current I 5  is double the collector current I 3 . Thus, subtracting the collector current I 3  from the collector current I 5 , the collector current I 3  flows so that the capacitor C 101  is charged with electric charges. When the capacitor C 101  is charged, the voltage across the terminals of the capacitor C 101  increases. Thus, the voltage VC 1  of the capacitor C 101  drops. When the voltage VC 1  of the capacitor C 101  drops below the lower limit voltage Va even by a small amount, the output signal of the comparator CP 101  is inverted to Low. These operations are repeated to generate the triangular wave signal shown in  FIG. 10 . 
   The period T of the triangular wave signal is represented by Expression (18). 
   
     
       
         
           
             
               
                 
                   
                     
                       T 
                       = 
                       
                         
                           2 
                           × 
                           
                             ( 
                             
                               Vb 
                               - 
                               Va 
                             
                             ) 
                           
                           × 
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             101 
                             / 
                             I 
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         = 
                       
                     
                       
                   
                     
                 
                 ⁢ 
                 
                     
                   
                     [ 
                     
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                       × 
                       Vc 
                       × 
                       
                         
                           { 
                           
                             
                               ( 
                               
                                 
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                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     104 
                                     / 
                                     
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                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
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                                         + 
                                         
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                                       ) 
                                     
                                   
                                 
                                 - 
                                 
                                   
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                                       ⁢ 
                                       
                                           
                                       
                                       ⁢ 
                                       104 
                                       × 
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                                       ⁢ 
                                       
                                           
                                       
                                       ⁢ 
                                       105 
                                     
                                     ) 
                                   
                                   / 
                                   
                                     ( 
                                     
                                       
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                               } 
                             
                             × 
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                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             101 
                           
                           ] 
                         
                         / 
                         
                           [ 
                           
                             { 
                             
                               
                                 
                                   ( 
                                   
                                     Vc 
                                     - 
                                     
                                       V 
                                       
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                                         1 
                                       
                                     
                                   
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                                 / 
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                               101 
                             
                             } 
                           
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 18 
                 ) 
               
             
           
         
       
     
   
   When the triangular wave signal supplied from the triangular wave generation circuit  1 , that is, the voltage VC 1  of the capacitor C 101  exceeds the reference voltage Vk, the output signal of the comparator CP 102  of the PWM generation circuit  2  is driven Low. When the voltage VC 1  of the capacitor C 101  drops below the reference voltage Vk, the output signal of the comparator CP 102  is driven High. These operations are repeated to generate the PWM signal shown in  FIG. 10 . 
   The output signal of the comparator CP 2 , that is, the PWM signal is supplied to the driving circuit  4  via the OR gate  3 . The driving circuit  4  amplifies and inverts the logical value of the PWM signal supplied from the OR gate  3  and applies a driving voltage to the MOSFET  122 . While the driving voltage applied from the driving circuit  4  is High, the MOSFET  122  has its gate voltage driven High so that it is turned ON. The source voltage of the MOSFET  122  is almost equal to the ground voltage. As shown in  FIG. 10 , a load current flows into a load  6 , or a lamp  11  in this example. 
   In case the driving voltage from the driving circuit  4  is Low, the MOSFET  122  is turned OFF. Thus, the source voltage of the MOSFET  122  rises until it is almost equal to the battery voltage V bat . As shown in  FIG. 10 , a load current does not flow into a load  6 , or a lamp  111  in this example. 
   These operations are repeated to drive the lamp  111  to blink based on the supplied driving voltage. 
   For example, in case the capacitor C 101  has shorted by some cause in this normal operation, the voltage VC 1  of the capacitor C 101  becomes a constant voltage Vc. The constant voltage Vc is higher than the reference voltage Vk as understood from Expression (15). Thus, the voltage VC 1  of the capacitor C 101  is higher than the reference voltage Vk. Thus, the output signal of the comparator CP 102 , that is, the PWM signal is fixed to Low level. 
   The PWM signal fixed to Low level is supplied to the driving circuit  4  via the OR gate  3 . The driving circuit  4  amplifies and inverts the logical value of the PWM signal supplied from the OR gate  3  and keeps applying a High driving voltage to the MOSFET  122 . While the driving voltage that is fixed to High level is applied from the driving circuit  4 , the MOSFET  122  is maintained ON and keeps feeding a load current to the lamp  111 . In other words, the lamp  111  keeps lighting with a 100% duty ratio. 
   In this case, low beams are used for DRL so that the lamp  111  in constant lighting does not present no particular problems. The lighting state of the lamp  111  ensures safety of the people on the vehicle, pedestrians and oncoming vehicles so that the lighting state is rather favorable from the viewpoint of a fail-safe design. 
   (2) In case a vehicle where this load control device is mounted high beams for DRL: 
   In this case, one terminal of the capacitor C 101  is inserted into a through hole made almost in the center of the land L 2  formed at an end of the pattern P 2  and the other terminal of the capacitor C 101  is inserted into a through hole made almost in the center of the land L 3  formed at an end of the pattern P 3 . Next, for example by melting cream solder previously applied on the lands L 2  and L 3 , one terminal of the capacitor C 101  and the land L 2  are electrically connected to each other and the other terminal of the capacitor C 101  and the land L 3  are electrically connected to each other. 
   Next, operation of the load control device of the above configuration will be described. In case the control signal supplied from the ECU  113  is High, the output signal of the OR gate  3  is always High. The driving circuit  4  amplifies and inverts the logical value of High level supplied from the OR gate  3  and applies a Low driving voltage to the MOSFET  122 . While the Low driving voltage is applied from the driving circuit  4 , the MOSFET  122  is turned OFF. In this case, the source voltage of the MOSFET  122  is almost equal to the battery voltage V bat  so that a load current does not flow into a load  6 , or a lamp  11  in this example. 
   In case the control signal supplied from the ECU  113  is Low, the output signal of the comparator CP 102  of the PWM generation circuit  2  serves as an output signal of the OR gate  3 . 
   In case the voltage VC 1  of the capacitor C 101  is lower than the reference voltage Vt 1  at a certain time, the output signal of the comparator CP 1  is driven Low and the transistors Q 108  and Q 109  are turned OFF. While the transistor Q 108  is turned OFF, the reference voltage Vt 1  is the upper limit voltage Vb of the triangular wave signal. 
   When the transistor Q 109  is turned OFF, a current flows into the base of the transistor Q 107  from the resistor R 108  so that the transistor Q 107  is turned ON. When the transistor Q 107  is turned ON, supply of a collector current I 5  is stopped. As a result, a collector current I 3  flows, which charges the capacitor C 101  with electric charges and the voltage across the terminals of the capacitor C 101  increases. The voltage VC 1  of the capacitor C 101  rises. 
   When the voltage VC 1  of the capacitor C 101  exceeds the upper limit voltage Vb even by a small amount, the output signal of the comparator CP 101  becomes “H” level and the transistors Q 108  and Q 109  are turned ON. While the transistor Q 108  is turned ON, the reference voltage Vt 1  becomes the lower limit voltage Va of the triangular wave signal. 
   When the transistor Q 109  is turned ON, a current does not flow from the resistor R 108  to the base of the transistor Q 107 . This turns OFF the transistor Q 107 . When the transistor Q 107  is turned OFF, supply of the collector current I 5  starts. The collector current I 5  is double the collector current I 3  as mentioned above. Thus, subtracting the collector current I 3  from the collector current I 5 , the collector current I 3  flows so that the electric charges accumulated on the capacitor C 101  are discharged. 
   When the electric charges accumulated on the capacitor C 101  are discharged, the voltage across the terminals of the capacitor C 101  decreases. Thus, the voltage VC 1  of the capacitor C 101  drops. When the voltage VC 1  of the capacitor C 101  drops below the lower limit voltage Va even by a small amount, the output signal of the comparator CP 101  is inverted to Low. These operations are repeated to generate the triangular wave signal. The period T of the triangular wave signal is represented by Expression (18) mentioned above. 
   When the triangular wave signal supplied from the triangular wave generation circuit  1 , that is, the voltage VC 1  of the capacitor C 101  exceeds the reference voltage Vk, the output signal of the comparator CP 102  of the PWM generation circuit  2  is driven Low. When the voltage VC 1  of the capacitor C 101  drops below the reference voltage Vk, the output signal of the comparator CP 102  is driven High. These operations are repeated to generate the PWM signal. 
   The output signal of the comparator CP 102 , that is, the PWM signal is supplied to the driving circuit  4  via the OR gate  3 . The driving circuit  4  amplifies and inverts the logical value of the PWM signal supplied from the OR gate  3  and applies a driving voltage to the MOSFET  122 . While the driving voltage applied from the driving circuit  4  is High, the MOSFET  122  is turned ON. The source voltage of the MOSFET  122  is almost equal to the ground voltage, and thus a load current flows into a lamp  111  in this example. 
   In case the driving voltage from the driving circuit  4  is Low, the MOSFET  122  is turned OFF. Thus, the source voltage of the MOSFET  122  rises until it is almost equal to the battery voltage V bat . As a result, a load current does not flow into a lamp  111 . 
   These operations are repeated to drive the lamp  111  to blink based on the supplied driving voltage. 
   For example, in case the capacitor C 101  has shorted by some cause in this normal operation, the voltage VC 1  of the capacitor C 101  becomes 0V. The voltage VC 1  of the capacitor C 101  is 0V and thus is lower than the reference voltage Vk in Expression (15). The output signal of the comparator CP 102 , i.e., the PWM signal, is fixed to High level. 
   The PWM signal fixed to High level is supplied to the driving circuit  4  via the OR gate  3 . The driving circuit  4  amplifies and inverts the logical value of the PWM signal supplied from the OR gate  3  and keeps applying a Low driving voltage to the MOSFET  122 . While the driving voltage that is fixed to Low level is applied from the driving circuit  4 , the MOSFET  122  is maintained OFF and maintains a state where a load current does not flow into the lamp  111 . In other words, the lamp  111  stays OFF. 
   In this case, the high beams are used for DRL so that the lamp  111  stays OFF. There is no possibility of glare occurring on the eyes of the driver of a vehicle in front or an oncoming vehicle, thus previously preventing a traffic accident. 
   In this way, according to Fourth embodiment of the invention, the triangular wave generating circuit  1  is configured such that a triangular wave signal of the same frequency and same shape is generated in a first interposing state where a capacitor C 101  for setting the frequency is interposed between the constant voltage Vc and the non-inverted input terminal of the comparator CP 101  and a second interposing state where the capacitor C 101  is interposed between a ground and the non-inverted input terminal of the comparator CP 101 . 
   According to the fourth embodiment of the invention, for example, as shown in  FIG. 9 , patterns P 1  to P 3  for mounting the capacitor C 101  for frequency setting are formed on a printed circuit board where a load control device is mounted, in accordance with the capacitor C 101  and the first or second interposing form. In case a vehicle where the load control device is mounted uses the low beams for DRL, both terminals of the capacitor C 101  are electrically connected to the land L 1  of the pattern P 1  and the land L 2  of the pattern P 2 . In case a vehicle where the load control device is mounted uses the high beams for DRL, both terminals of the capacitor C 1  are electrically connected to the land L 2  of the pattern P 2  and the land L 3  of the pattern P 3 . 
   It is thus possible to enhance the safety of the load control device assumed when the capacitor C 101  has shorted. With a vehicle using low beams for DRL, a fail-safe design is ensured. With a vehicle using high beams for DRL, safety is enhanced. It is unnecessary to manufacture two types of printed circuit boards depending on the type of vehicle using the load control device. This contributes to reduced costs. 
   Fifth Embodiment 
   While the comparator CP 2  (CP 102 ) does not exhibit hysteresis in each of the foregoing embodiments, the invention is not limited thereto but the comparator CP 2  (CP 102 ) may exhibit hysteresis.  FIG. 11  is a circuit diagram showing an exemplary configuration of a comparator CP 2  (CP 102 ) and its peripheral circuitry where a hysteresis circuit  31  is added to the comparator CP 2  (CP 102 ). 
   The hysteresis circuit  31  is composed of an inverter INV, a PNP transistor Q 21 , and resistors R 21  and R 22 . The inverter INV inverts the output signal of the comparator CP 2  (CP 102 ), that is, the PWM signal. The resistor R 22  is a base resistor connected between the base of the transistor Q 21  and the output end of the inverter INV. The PNP transistor Q 21  changes the reference voltage Vk when it is turned ON by a High output signal of the inverter INV supplied via the resistor R 22 . Configuration of the other parts of the load control device than the comparator CP 2  (CP 102 ) and its peripheral circuitry may be the same as that in  FIG. 2  in the first embodiment, the same as that in  FIG. 5  in the second embodiment, the same as that in  FIG. 6  in the third embodiment, and the same as that in  FIG. 8  in the fourth embodiment. 
   Next, operation of the comparator CP 2  (CP 102 ) and its peripheral circuitry of the load control device will be described referring to the timing chart shown in  FIG. 12 . 
   In case a triangular wave signal supplied from the triangular wave generation circuit  1  is above a reference voltage Vk, the output signal of the comparator CP 2  (CP 102 ) of the PWM generation circuit  2  is driven Low. The output signal of the inverter INV is driven High and the transistor Q 21  is turned ON. 
   While the transistor Q 21  is turned ON, without considering the saturation voltage of the transistor Q 21 , the reference voltage Vk becomes a resistance dividing voltage of the composite resistance value of the resistors R 11  and R 21  and the resistance value of the resistor R 10 , and as shown in  FIG. 12 , becomes a second reference voltage Vk 2 . The second reference voltage Vk 2  is represented by Expression (19).
 
 Vk 2 =Vc ×{( R 11 ×R 21)/( R 11 +R 21)}/[ R 10+( R 11 ×R 21)/( R 11 +R 21)]  (19)
 
   Next, when the triangular wave signal drops below the second reference voltage Vk 2 , the output signal of the comparator CP 2  (CP 102 ) is driven High. Thus, the output signal of the inverter INV is driven Low and the transistor Q 21  is turned OFF. While the transistor Q 21  is turned OFF, the reference voltage Vk 2  changes to a value represented by Expression (6) as shown in  FIG. 12 . In other words, the comparator CP 2  has hysteresis. These operations are repeated to generate a PWM signal with a larger pulse width than in the foregoing embodiments as shown in  FIG. 12 . In this way, according to Fifth embodiment, the comparator CP 2  (CP 102 ) has hysteresis so that a noise resistance can be enhanced further than the above embodiments. 
   Sixth Embodiment 
   While the invention is applied to a device (low-side switching device) that includes an N-channel MOSFET  22  as a load driving element  5  arranged downstream a lamp  11  as a load  6  in the foregoing embodiments, the invention is not limited thereto. For example, the invention may be applied to a device (high-side switching device) that includes an N-channel MOSFET  22  as a load driving element  5  arranged upstream a lamp  11  as a load  6 . In this case, a P-channel MOSFET may be used in place of an N-channel MOSFET  22  as a load driving element  5 . 
   Seventh Embodiment 
   While an N-channel MOSFET  22  or a P-channel MOSFET is used as a load driving element  5  in the foregoing embodiments, the invention is not limited thereto. The load driving element  5  may be a bipolar transistor, a thyristor, an IGBT (Insulated Gate Bipolar Transistor), an SIT (Static Induction Transistor) or any other type of switching element. 
   While embodiments of the invention have been detailed referring to drawings, specific configurations of the invention are not limited thereto but modifications to the design within the scope of the invention are also included in the invention. 
   For example, while the constant voltage power source  21  is provided in the above embodiments, the invention is not limited thereto but the constant voltage power source  21  may be done without. In this case, in the first embodiment, the emitter of each of the transistors Q 1  to Q 4  and one end of each of the resistors R 4 , R 9 , R 10  and R 12  are directly connected to the power terminal Tb. In the second embodiment, the emitter of each of the transistors Q 2  to Q 4 , the cathode of the Schottky barrier diode D 2 , and one end of each of the resistors R 4 , R 9 , R 10  and R 12  are directly connected to the power terminal Tb. In the third embodiment, the emitter of each of the transistors Q 2  to Q 4 , the thermistor TH 1 , and one end of each of the resistors R 4 , R 9 , R 10  and R 12  are directly connected to the power terminal Tb. Note that, in Third embodiment, the connecting position of the thermistor TH 1  may be changed with that of the resistor R 1 . 
   Also, while the constant voltage power source  21  is provided in the above embodiments, the invention is not limited thereto. The constant voltage power source  21  may be not provided to the load control device. In this case, the emitter of each of the transistors Q 1  to Q 3  (Q 101  to Q 103 ) and one end of each of the resistors R 3 , R 8 , R 9  and R 11  (R 103 , R 108 , R 109  and R 111 ) are directly connected to the power terminal Tb. The pattern P 1  to which one terminal of the capacitor C 1  (C 101 ) is to be connected is also directly connected to the power terminal Tb. 
   While the patterns P 1  to P 3  shown in  FIG. 9  are formed on a printed circuit board in the foregoing embodiments, the invention is not limited thereto. For example, the following configuration may be used. One terminal of the capacitor C 101  is electrically connected to the land of a pattern that is connected to the non-inverted input terminal of the comparator CP 101 . The pattern P 2  shown in  FIG. 9  is formed in a very short length and the other terminal of the capacitor C 101  is electrically connected to one land (not shown in  FIG. 9 ). In case an automobile where this load controller is mounted uses low beams for DRL, a jumper pin is electrically connected across the lands L 1  and L 2  shown in  FIG. 9 . In case an automobile where this load controller is mounted uses high beams for DRL, a jumper pin is electrically connected across the lands L 2  and L 3  shown in  FIG. 9 . 
   While the load control device according to the invention is mounted on a vehicle, and the load  6  is a lamp  11  used as a headlamp in the above embodiments, the invention is not limited thereto. The invention may be generally applied to a device for controlling a load based on the generated PWM signal or the like. 
   The foregoing embodiments may use techniques of each other unless its purpose and configuration are not contradictory or problematic. 
   Although the invention has been illustrated and described for the particular preferred embodiments, it is apparent to a person skilled in the art that various changes and modifications can be made on the basis of the teachings of the invention. It is apparent that such changes and modifications are within the spirit, scope, and intention of the invention as defined by the appended claims. 
   The present application is based on Japan Patent Application No. 2006-161862 filed on Jun. 12, 2006 and Japan Patent Application No. 2006-161873 filed on Jun. 12, 2006, the contents of which are incorporated herein for reference.