Patent Publication Number: US-11664724-B1

Title: Power bus voltage drop compensation using sampled bus resistance determination

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/886,460, filed May 28, 2020, which is a continuation of U.S. patent application Ser. No. 15/179,521, filed Jun. 10, 2016, the entireties of both of which are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     This invention relates to apparatus and methods for compensating for voltage errors introduced by a non-ideal power distribution connections between a power converter and a load. 
     BACKGROUND 
     Non-ideal connections between the output of a power converter and its load may introduce a voltage drop which may vary as a function of changes in load current owing to the resistance in the non-ideal connection. Traditional attempts to compensate for such errors include using negative feedback to compare the voltage at the load to a desired reference voltage requiring relatively high bandwidth connections between the load and the power converter due to the need to constantly monitor and control the voltage at the load. Other attempts have accounted for resistances in the system by providing a correction circuitry based on an expected resistance in the line. Thus, it would be advantageous to have systems and methods that provide for maintaining a voltage at a load, and accounting for variations in bus resistance over time, while reducing the bandwidth required to maintain a desired load voltage. 
     SUMMARY 
     One exemplary method of the present disclosure is a method of converting power. The method includes providing a first power conversion stage. The first power conversion stage including an input for receiving power from a power source and a first output for supplying power via a first power bus to a first load. The first load is electrically separated from the first output by a first bus resistance. The method further includes providing a control circuit adapted to provide a control signal to the first power conversion stage. The method further includes measuring a first load voltage at or near the first load, measuring a first output voltage at or near the first output, and measuring a first current flowing between the first output and the first load through the first power bus. The method additionally includes determining a representation of the first bus resistance as a function of the measuring using the control circuit. The method also includes sending a control signal to the first power conversion stage from the control circuit as a function of the representation of the first bus resistance. Furthermore, the method includes adjusting, in response to the control signal, the first power conversion stage to include a negative output resistance component configured to compensate for the first bus resistance. 
     Another exemplary embodiment of the present disclosure is a method of converting power. The method includes providing a plurality of power conversion stages each having a respective input for receiving power from a power source and a respective output for supplying power via a respective power bus to a respective load, each load being electrically separated from the respective output by a respective bus resistance. The method further includes providing a control circuit adapted to provide a respective control signal to the each of the plurality of power conversion stages. The method further includes measuring a respective load voltage of the power being supplied to each load at or near the load, and measuring a respective output voltage being supplied to each load at or near the respective output. The method further includes determining a representation of the respective bus resistance as a function of the respective measuring. The method also includes sensing a respective control signal to each power conversion stage as a function of the representation of the respective bus resistance. The method also includes adjusting, in response to a respective control signal, a response characteristic of each power conversion stage to include a negative output resistance component configured to compensate for the respective bus resistance. 
     Another exemplary embodiment of the present disclosure is a system of converting power. The system includes a first power conversion stage. The first power conversion stage includes an input for receiving power from a power source, and a first output for supplying power via a first power bus to a first load, the first load being electrically separated from the first output by a first bus resistance. The system further includes a control circuit. The control circuit is adapted to measure a first output voltage at or near the first output and a first current flowing between the first output and the first load through the first power bus. The system also includes an output monitor, the output monitor configured to measure a first load voltage at or near the first load. In the system, the control circuit is configured to determine a representation of the first bus resistance as a function of the measuring using the control circuit, and additionally configured to send a control signal to the first power conversion stage from the control circuit as a function of the representation of the first bus resistance. The first power conversion stage is configured to adjust a voltage at the first output to include a negative output resistance component to compensate for the first bus resistance in response to the first control signal. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  shows a power delivery system according to one embodiment. 
         FIG.  1 B  shows the power delivery system of  FIG.  1 A , including a DC transformer, according to one embodiment. 
         FIG.  2    shows a relationship between current and voltage in the systems of  FIG.  1 A . 
         FIG.  3 A  illustrates sample timing in one embodiment of a power delivery system according to one embodiment.  FIG.  3 B  illustrates an expanded view of the sample timing of  FIG.  3 A . 
         FIG.  4    shows another power delivery system according to one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Electronic systems may comprise one or more power sources (e.g. voltage regulators) that deliver power to one or more loads by means of one or more power distribution buses. A power distribution bus may comprise, e.g., cables, bus bars, printed circuit board traces and other conductive devices. Because the power distribution bus has finite resistance there will be a voltage drop in the bus that will vary as a function of load current. In some systems the effects of bus resistance may be minimized by providing distribution bus conductors of sufficiently large gauge to keep the maximum voltage drop in the bus below some desired maximum value. This, however, may result in a distribution bus that is bulky, heavy and costly. Another way to reduce the effects of distribution bus voltage drop is to control the voltage output of the power source as a function of the voltage measured at the load, thereby reducing or eliminating errors in voltage, e.g. due to voltage drop in bus as a function of load current. This approach has required using wideband feedback from the load, with associated additional interconnection, processing bandwidth, stability, and control issues. 
     A first embodiment of a power distribution system  10 A is shown in  FIG.  1 A  having a power delivery stage  15 A (comprising a power conversion stage  30  and a power distribution bus  40 ) connected to supply power to a load  50 . The power conversion stage  30  receives power from an input source  20  and delivers power, at an output voltage V O  and an output current I O , to load  50  via a distribution bus  40 . The total resistance, R B , in the distribution bus is indicated in  FIG.  1 A  by lumped bus resistances  42 ,  44 . A power conversion controller  32  in the power conversion stage  30  may control the magnitude of the output voltage, V O  by supplying a control signal to a voltage regulator  34  within the power conversion stage  30 . The control bandwidth, BW, of the power conversion controller  32  may be sufficiently large to enable the voltage V O  to be maintained within pre-defined limits (e.g. 0.1%, 1%) under normal operating conditions, e.g. at the maximum slew rate and variation in magnitude of the output current, I O , demanded by the load  50 . 
     A control circuit  70  may be provided to measure the output voltage, V O , and optionally the output current, I O , and to deliver a control signal  90  to the power conversion stage  30 . The control circuit  70  may be configured as a function in a larger supervisory system for managing operation, e.g. power up, fault detection, and power down, of the power conversion stage  30 , or as a dedicated auxiliary circuit. An output monitor  60  may be provided to measure the load voltage V L  and optionally the output current, I O , and communicate with the control circuit  70 . The output monitor  60  may be similarly deployed as a function of a larger monitoring circuit, such as a supervisory load monitoring circuit, or as a dedicated auxiliary circuit. Data and control signals may pass between the control circuit  70  and the output monitor  60  via data bus  80 , which may be of any form (e.g. analog, digital, physical conductors, wireless), and use any form of communication protocol (e.g. PMBus, I2C, etc.). 
     Bus resistance, R B , causes a reduction in the load voltage, V L , relative to the output voltage as a function of output current, V O :V L =V O −I O *R B . A method for counteracting the effect of the bus voltage drop, I O *R B , comprises using the control circuit  70  to make measurements of the output voltage V O , and using the output monitor  60  to make a measurement of the load voltage V L , and using one or both of the control circuit  70  or output monitor  60  to measure the output current I O . The measurements made by the output monitor  60 , e.g. of V L  and optionally I O , may be provided to the control circuit via data bus  80 . The control circuit  70  may use the measured values of V O , I O  and V L  to determine a magnitude of bus resistance:R BD =(V OM −V LM )/I OM , where R BD  is the determined magnitude of the bus resistance, and V OM , V LM  and I OM  are the respective measured values of V O , V L  and I O . R BD  may be delivered to the power conversion circuit  30 , by means of control signal  90 , where it may be used to alter the magnitude of V O (t) as a function of the magnitude of the load current I O . If, for example, it is desired to maintain the load voltage at an essentially constant voltage V L =V LD , the power conversion circuit would set V O =V LD  R BD *I O , where V LD  is the desired load voltage. In this way, V O  will be controlled to offset and compensate for the voltage drop in the power bus, I O *R B , thereby reducing or eliminating variations in V L . 
     The relationship between V O  and I O  is shown in  FIG.  2   . Because V O  increases with increasing I O , the power conversion stage  30  exhibits a negative output resistance characteristic that counteracts and compensates for the effects of the finite, positive, bus resistance. 
     The accuracy of the determined value of resistance, R BD , will be affected by the relative timing (synchronization error) of the measurements of V O , V L  and I O . Accuracy is improved if all of the measurements are made within a sampling time period during which the values of V O , V L  and I O  do not vary significantly. The method may therefore comprise synchronizing the measurements of V O , V L  and I O  to occur within a sampling period, T S , that is short with respect to anticipated changes in V O , V L  and I O . By this we mean that T S  is short enough so that anticipated variations in average values of V O , V L  and I O  do not exceed a small percentage (e.g., 0.1%, 1%) of their values at the beginning of the sampling period. For example, the sampling period may be a very small fraction of a second, e.g. 1 mS, 100 uS, 10 uS, 1 uS, 100 nS, 10 nS, etc. The control circuit  70  may synchronize the taking of the measurements by sending a synchronization signal to the output monitor  60 , via data bus  80 . Within a very short time after receiving the synchronization signal the output monitor  60  takes a sample of the load voltage, V LM . Also within a very short time period of sending the synchronization signal, the control circuit  70  takes samples of output voltage, V OM , and preferably the output current, I OM . In this way, sampled measurements of V OM , V LM  and I OM  may be synchronized to all be taken at some time, and preferably at the same time, within the short sampling period T S . 
     Effects associated with timing of samples and transient load changes may introduce errors into individual determined values of R BD . The method may therefore incorporate an averaging process to improve accuracy in the determination of R BD . For example, as illustrated in  FIG.  3 A , an averaging interval, TD, may comprise a finite number, N, of sequential sample intervals of length T S . The averaging interval may preferably be made long relative to any synchronization errors in the samples. For example, a system may use 100 uS sampling intervals, T S , and obtain 100 contiguous samples per 10 mS averaging interval, TD. As shown in  FIG.  3 B , which shows an expanded view of a portion of  FIG.  3 A , samples of V O , V L  and I O  are taken within each sampling interval. The durations of both the sampling period, T S , and the averaging interval, TD, are made short with respect to anticipated changes in the average values of V O , V L  and I O . The N values of R BD  that are determined during the averaging interval, TD, are averaged by control circuit  70  to provide an averaged determined value, R BDA . R BDA  is delivered to the power conversion circuit  30  where it is used, in the manner discussed earlier, to change the magnitude of V O  as a function of the magnitude of the load current I O :V O =V LD +R BDA *I O . Although sampling periods are shown to be contiguous in  FIG.  3 A , it is understood that sampling intervals may be separated in time within an averaging interval. Any suitable method of averaging the values may be used. For example, a simple mathematical average of all of the data points may be used to calculate the averaged determined value; alternatively the data points may be screened to eliminate any that differ by more than a predetermined percentage, such as 10% or 5% or less, from the other data points. 
     Although the bus resistance may change over time, e.g. due to temperature changes or other environmental effects, the changes should occur very slowly compared to V O , V L , and I O  for typical electronic loads. The frequency with which the bus resistance or average bus resistance is determined and delivered to power conversion circuit  30  may therefore be low compared to the control bandwidth, BW, of the power conversion controller  32 . Accordingly a single supervisory circuit or controller may be used to service a plurality of conversion circuits and loads. 
     A second embodiment of a power distribution system  10 B is shown in  FIG.  1 B , having a power delivery stage  15 B. The power delivery system  15 B may be the same as power delivery system  15 A, but further includes a DC transformer  43 , such as a fixed-ratio bus converter, or voltage transformation module (“VTM”), in the power path between the regulator  34  and the load  50  to implement various power distribution architectures, as described below. Accordingly, operation of the system  10 B in  FIG.  1 B  is substantially the same as that of system  10 A of  FIG.  1 A , except as described below. For example, power distribution architectures such as those described in Vinciarelli,  Factorized Power Architecture with Point of Load Sine Amplitude Converters , U.S. Pat. No. 6,984,965, issued Jan. 10, 2006 (the “FPA Patent”), and in Vinciarelli et al.,  Power Distribution Architecture with Series - Connected Bus Converter , U.S. application Ser. No. 13/933,252 filed Jul. 2, 2013 (the “NIBA Application”), both of which are assigned to VLT, Inc., and are herein incorporated by reference, in their entirety may be implemented. 
     As defined herein, the DC transformer  43  delivers a DC output voltage, V OUT , which is a fixed fraction of the input voltage, VIN, delivered to its input. The DC transformer  43  may also provide isolation between an input of the DC transformer  43  and an output of the DC transformer  43 . The voltage transformation ratio and/or voltage gain of the DC-transformer  43  is defined herein as the ratio of the output voltage to the input voltage at a load current. Expressed mathematically, the voltage transformation ratio and/or voltage gain may be expressed as K=V OUT /V IN . The voltage transformation ratio of a DC transformer, such as DC transformer  43 , may be fixed by design, e.g. by a converter topology, timing architecture, and/or the turns ratio of the transformer. 
     In one embodiment, the DC transformer  43  may be implemented using Sine-Amplitude Converter (“SAC”) topologies and/or timing architectures, such as those described in Vinciarelli,  Factorized Power Architecture and Point of Load Sine Amplitude Converters, U.S. Pat. No.  6,930,893 , and in Vinciarelli, Point of Load Sine Amplitude Converters and Methods , U.S. Pat. No. 7,145,786, both assigned to VLT, Inc., and incorporated herein by reference in their entirety (hereinafter the “SAC Patents”), as well as those described in the NIBA Application, discussed above. The DC transformer  43 , using a SAC topology, may be capable of achieving very high power densities and conversions efficiencies for voltage transformation at an essentially resistive output resistance. The SAC topology may also provide galvanic isolation between an input of the DC transformer  43  and an output of the DC transformer  43 , with an equivalent output resistance. To the extent the DC transformer  43  is essentially resistive and experiences voltage droop with increases in current, the sampled bus compensation system may be used to correct for the equivalent series resistance  45  of the DC transformer  43  in addition to the lumped bus resistances  42 - 1 ,  42 - 2 ,  44 - 1 ,  44 - 2 , of the bus segments  40 - 1 ,  40 - 2 . As described in the &#39;965 Patent and the &#39;252 Application, the DC transformer  43  may provide voltage reduction and current multiplication. In one embodiment, the voltage gain may be less than one (K&lt;1), or more preferably, (K≤¼). Further, the DC transformer may be located relatively closer to the load  50 , than to the regulator  34 , thereby allowing the output voltage, V O , of the regulator  34  to be greater than the load voltage, V L . In one embodiment, the output voltage, V O , is greater than the load voltage, V L , by a factor of four or more. 
       FIG.  4    shows an embodiment of a power distribution system  100  having a plurality of power delivery stages,  15   1 ,  15   2 , each of the kind shown in  FIG.  1 A  and each comprising an input source  20   1 ,  20   2 , a power conversion stage  30   1 ,  30   2 , a distribution bus  40   1 ,  40   2  and a load  50   1 ,  50   2 . The input voltages, Vin1 and Vin2, may come from different sources  20   1 ,  20   2 , or the input voltages Vin1 and Vin2 may come from the same source. The total resistance in each distribution bus  40   1 ,  40   2  is indicated in  FIG.  4    by lumped bus resistances  42   1 ,  44   1  and  42   2 ,  44   2 . Operation of the system of  FIG.  4    is substantially the same as that of the system  10 A of  FIG.  1 A , except that the system of  FIG.  4    uses a single control circuit  701 , a single output monitor  601  and a single data bus  801  to determine bus resistances, and optionally averaged bus resistances, for the multiplicity of power delivery stages  15   1 ,  15   2 , and communicate those resistances to the respective power conversion stages  30   1 ,  30   2  as control signals  901 ,  902 . Although the system of  FIG.  4    shows two power delivery stages  15   1 ,  15   2 , it will be evident that any number of power delivery stages can be operated in accordance with the methods described herein. Furthermore, a single control circuit  701  can be used to provide a control signal to several (e.g. 3, 5, 12, etc.) power conversion stages and a single output monitor  601  can be used to sample and communicate data from several loads (e.g. 4, 7, 11). The numbers of control circuits and output monitors may be different, depending on performance capabilities and requirements, and the number of data buses required will depend on the nature of the selected communication technique. The sampled bus compensation system described above may provide superior performance compared to other techniques because it may be used to compensate for the initial value tolerance, variability in time and temperature dependency of all resistive elements in the power path. 
     A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, essentially complete cancellation of bus resistance may not be required in all systems; in such systems the magnitude of R BD  may be scaled appropriately.