Patent Publication Number: US-4096360-A

Title: Multichannel record disc reproducing system

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to multichannel record disc reproducing systems. More particularly, it relates to a system for demodulating and reproducing without distortion and with a high signal-to-noise ratio. The reproduced signal comprises an angle-modulated signal picked up from a multichannel record disc through the use of a plurality of phase-locked loops having, respectively, different lock ranges. 
     Systems for demodulating angle-modulated signals by means of phase-locked loops (hereinafter referred to as PLL) have been known in the prior art. A PLL of this type generally comprises a phase comparator which is supplied with an angle-modulated signal as one input. A loop filter is used for attenuating the high-frequency component of an output error signal from the phase comparator. A direct-current amplifier amplifies the output signals from the loop filter. A voltage-controlled oscillator generates a frequency which is controlled by the output of the direct-current amplifier. The resulting output of the oscillator is supplied, as a phase comparison signal, to the phase comparator. A demodulated output signal is derived from the direct-current amplifier. The direct-current amplifier may be omitted. The frequency characteristic of the demodulated signal is determined by the width of the lock range or capture range of the PLL. 
     There may be a carrier drop in the signal reproduced from a multichannel record disc, on which a direct-wave signal and an angle-modulated signal have been multiplexed and recorded. That is, an absence of the carrier component may occur in the reproduced angle-modulated signal or there may be an over-modulation due to a disturbance caused by a frequency close to the carrier frequency. This close frequency may be a higher harmonic of the direct wave. As a result, an abnormal noise is generated. 
     Accordingly, in order to reduce or eliminate this noise, it has been a conventional practice to constrict the lock range of the PLL when an abnormal noise occurs. By this expedient, an abnormal locking of the PLL is prevented. Furthermore, the high-frequency component (for example, in the vicinity of 8 KHz) of the demodulated signal is attenuated, whereby the apparent noise level is lowered. As is known, the lock range or capture range of a PLL is determined by the loop gain of the PLL. This loop gain is determined principally by quantities such such factors as the gain of the direct-current amplifier, the passing quantity of the loop filter, and the conversion gain of the phase comparator and the voltage-controlled oscillator. The prior art has varied the lock range by increasing and decreasing this loop gain of the PLL, so that the characteristic of the loop filter is varied. 
     Usually, this loop filter includes a lag-lead filter comprising a fixed resistor connected between the input and output terminals and a series connection of a capacitor and a variable resistor connected between ground and the junction between the fixed resistor and the output terminal. This combination constitutes a kind of low-pass filter. By varying the resistance of the variable resistor in this loop filter, the characteristic of this loop filter is changed, and the loop gain of the PLL varies. Hence, the lock range of the loop is appropriately varied and set. Here, increasing the resistance value of the variable resistor of the loop filter causes the lock range width to increase, while decreasing the same resistance value causes the lock range width to decrease. 
     An angle-modulated signal is obtained by modulating a carrier with a modulation signal in which much energy is distributed particularly in a high-frequency range (in the vicinity of 8 KHz). For example, this is the frequency range which may include the sound of cymbals. When such a signal is reproduced and is introduced into the PLL, its lock range is made narrower than the deflection frequency width of the angle-modulated signal. This narrowing is accomplished by varying the above mentioned variable resistor. As a result, even when there are higher harmonics of the direct-wave signal, admixed in the angle-modulated wave band, the PLL does not erroneously lock with these higher harmonics. Furthermore, as a result of the smaller lock range of the PLL, there is an attenuation of the high-frequency band of the demodulation by the PLL. Therefore, even if the PLL should unlock, the noise in the high-frequency band will be attenuated, and a great noise will not be sensed. 
     An angle-modulated signal may be obtained by modulating a carrier with a modulation signal, in which much energy is distributed particularly in a low-frequency range (in the vicinity of 2 KHz). For example, a signal such as this may include the sound of a trumpet. If the deviation frequency of this angle-modulated signal exceeds the lock range, this angle-modulated signal is relatively overmodulated with respect to the lock range of the PLL. In this case, an abnormal noise is generated in the output signal of the PLL despite the angle-modulated wave. This abnormal noise is very unpleasant to the ear. 
     Accordingly, the lock range of the PLL is made uniformly narrow in a conventional demodulation system in which a PLL is used. Therefore, the abnormal noise can be neglected from the standpoint of the sense hearing an angle-modulated signal produced by modulation a high frequency. However, if an angle-modulated signal is produced by modulation of a medium low frequency, the PLL unlocks, despite the normal angle-modulated signal. Beat sounds are generated by the input signal of the voltage-controlled oscillator and the input of the PLL. These beat sounds are very unpleasant to the ear. 
     Conversely, if the lock range of the PLL is broadened, the PLL responds rapidly. Although unlocking will not occur, the PLL responds to even a slight abnormality. Furthermore, the demodulation characteristic of the PLL extends up to the high-frequency range, at which it does not attenuate very much. For this reason, an unpleasant abnormal noise is heard. 
     Thus, there are mutually different advantages and disadvantages in the case of a narrow lock range and a wide lock range of the PLL. Consequently, it has not been possible to demodulate completely, without distortion or generation of noise, in a system wherein a single PLL is used for an input angle-modulated signal, and its lock range is controlled, as in the prior art. 
     SUMMARY OF THE INVENTION 
     Accordingly, a general object of the present invention is to provide a novel and useful multichannel record disc reproducing system. 
     Another and more specific object of the invention is to provide a multichannel record disc reproducing system having a demodulation system in which a plurality of PLLs, having respectively different widths of lock range, are used. In this system, it is possible to demodulate an angle-modulated signal with little distortion or noise. 
     A further object of the invention is to provide a multichannel record disc reproducing system in which a plurality of PLLs respectively having mutually different lock range widths are used. By detecting abnormality of an angle-modulated signal, the demodulated outputs of the PLLs are selectively added, to obtain a demodulated signal. 
     Other objects and further features of the invention will be apparent from the following detailed description with respect to preferred embodiments of the invention when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a block diagram showing one example of a multichannel record disc reproducing system, of a general type, to which the present invention can be applied; 
     FIG. 2 is a block diagram showing one embodiment of an essential part of the system illustrated in FIG. 1; 
     FIG. 3 is a circuit diagram showing one embodiment of a specific circuit for use in the block system shown in FIG. 2; 
     FIG. 4 is a graph indicating the PLLs lock range characteristics in the circuit shown in FIGS. 2 and 3; 
     FIG. 5 is a block diagram of another embodiment of an essential part of the system of the invention; 
     FIGS. 6(A) through 6(D) are output signal waveform diagrams respectively of the synchronous detectors in the FIG. 5; 
     FIG. 7 is a circuit diagram of one embodiment of a circuit for use in FIG. 5; 
     FIGS. 8(A) through 8(F) are graphs showing waveforms of the demodulated signal of the PLLs and of the output signals of the synchronous detectors; and 
     FIG. 9 is a block diagram of a modification of one of the system part illustrated in FIG. 5. 
    
    
     DETAILED DESCRIPTION 
     A multiplexed signal comprising a direct wave sum signal and an angle-modulated difference signal for each pair of two channels, is recorded (FIG. 1) on each side wall of the sound groove of a four-channel record disc 10. A total of four channels are thus recorded. A pickup cartridge 11 picks up one pair of multiplexed signals, comprising the direct wave sum signal and the angle-modulated wave difference signal, from the left wall of the grooves of the disc 10. The picked up signal is fed to an equalizer 12, having an RIAA (Recording Industry Association of America) turnover characteristic. 
     The resulting signal is fed from equalizer 12 to a low-pass filter 13 for eliminating the angle-modulated wave component and for deriving only the direct wave sum signal component. The direct wave sum signal is fed to a matrix circuit 15, via an equalizer 14 having the RIAA roll-off characteristic. 
     The output of the equalizer 12 is partly fed to a band-pass filter 16 (or high-pass filter), having a passband in the approximate range of 20 KHz to 45 KHz. An angle-modulated wave difference signal is derived from this filter. For demodulation, the angle-modulated wave difference signal is fed to a demodulation circuit 17. 
     The demodulated output from the demodulation circuit 17 is supplied to a low-pass filter 18, where the unwanted components contained in the demodulated output are eliminated thereat. The output is fed from the low-pass filter 18 to the matrix circuit 15 via (in succession) an FM/PM equalizer 19 and an automatic noise reduction system (ANRS) circuit 20 comprising an expandor. The a characteristic of the expandor compensates for the characteristic of a compressor in the recording system. 
     The matrix circuit 15 combines the direct wave sum signal from the equalizer 14 and the demodulated difference signal from the ANRS circuit 20. From output terminals 21a and 21b are derived, for instance, the left front (the first channel) and the left rear (the second channel) signals, respectively. 
     FIG. 1 shows only the system for the first and second channel signals (the signals recorded on the left wall of the grooves of the disc 10). Exactly the same system is duplicated for the right front (the third) and the right rear (the fourth) channel. A detailed illustration and description of this right system are omitted herein. 
     Here, the demodulation circuit 17 constitutes an essential part of the system of the present invention. The demodulation circuit 17 will now be described with respect to several embodiments. 
     FIG. 2 illustrates one embodiment of a demodulation circuit 17. An angle-modulated signal is introduced through an input terminal 30 to two PLLs 31a and 31b. The PLL 31a is of an ordinary design, comprising a phase comparator 32a, a loop filter 33a, and a voltage-controlled oscillator (VCO) 34a. The PLL 31b is similar, comprising similar components respectively designated by like reference numerals but with the suffix b. 
     The loop gain of the PLL 31a produces a lock range which is equal to or wider than the maximum deviation frequency range of the input angle-modulated signal. Accordingly, since its lock range is wide, the PLL 31a is capable of demodulating an angle-modulated signal, with little distortion, when it is recorded responsive to a modulation signal having great energy distributed in the medium and low frequencies as, for example, in a trumpet sound. It should be mentioned that, if the higher harmonics of the direct-wave signal band becomes admixed as a disturbance wave in the angle-modulated signal band, the PLL 31a also becomes locked to this disturbance wave. For this reason, the distortion due to this disturbance wave cannot be effectively prevented. 
     The demodulated output of the PLL 31a is delayed by a specific time in a delay circuit 35. Then it is fed to an addition circuit 37. The delay circuit 35 compensates for the time difference between the demodulated output signals of the PLLs 31a and 31b due to the difference between the lock ranges of these PLLs 31a and 31b. 
     The lock range of PLL 31b is narrower than the lock range of the PLL 31a. This narrow lock range causes the PLL 31b to demodulate by attenuating the high-frequency range, with respect to an angle-modulated signal which is produced responsive to a high energy modulation signal, particularly in the high frequencies as, for example, in the sound of cymbals. As a result, the noise level in the demodulated signal is apparently lowered. Furthermore, there is a reduction in the distortion due to interference with the angle-modulated signal particularly in response to the higher harmonics of the direct wave signal. 
     In this connection, the angle-modulated signal, which is produced responsive to a modulation signal in which much energy is distributed in the medium and low frequencies, has a frequency deviation which is greater than the lock range of the PLL 31b. Consequently, this angle-modulated signal is overmodulated relative to the lock range of the PLL 31b. If the angle-modulated signal of this character is demodulated, distortion will be generated in the PLL 31b. 
     The demodulated output of the PLL 31b passes through a high-frequency characteristic correction circuit 36 and there is supplied to the addition circuit 37. The high-frequency characteristic correction circuit 36 corrects the demodulated signal of the PLL 31b since its lock range is narrow and the high-frequency range of its demodulated signal is attenuated. 
     The addition circuit 37 adds the demodulated output of the PLL 31a, which has passed through the delay circuit 35, and the demodulated output of the PLL 31b which has passed through the high-frequency characteristic correction circuit 36. The resulting demodulated signal is led out through an output terminal 38. 
     If the higher harmonic component of the direct-wave signal band becomes admixed in the angle-modulated wave band, distortion does not occur in the demodulated output of the PLL 31b. Distortion (noise) is produced in the demodulated output of the PLL 31b. If the demodulation signal of the PLLs 31a and 31b is denoted by Vs, and the noise component within the demodulated output of the PLL 31a is denoted by √Vn 1   2 , the demodulated output of the PLL 31a is (Vs + √Vn 1   2 ), and the demodulated output of the PLL 31b is Vs. Accordingly, the demodulated output appearing at terminal 38 is (2Vs + √Vn 1   2 ). Therefore, when the two PLLs 31a and 31b are used, the signal-to-noise ratio is improved by approximately 6 dB as compared to the use of a single PLL 31a. 
     If the deviation frequency of an angle-modulated signal produced responsive to a modulation signal in which much energy is distributed in the medium low frequencies becomes greater than the lock range of the PLL 31b, distortion does not occur in the demodulated output of the PLL 31a. However, distortion (noise) is produced in the demodulated output of the PLL 31b. When this noise component is denoted by √Vn 2   2 , the resulting demodulated output appearing at output terminal 38 becomes (2Vs + √Vn 2   2 ). Therefore, the signal-to-noise ratio is improved by approximately 6 dB as compared to the use of only one PLL 31b. 
     Furthermore, if the two above mentioned noises are generated simultaneously, the resulting demodulated output led out of the output terminal 38 becomes (2Vs + √Vn1 2  + √Vn 2   2 ). Since these two noise components are generated responsive to different causes, their generation sources may be considered to be independent of each other. However, when their magnitudes are substantially the same, that is, when √Vn 1   2  + √Vn 2   2  + √Vo 2 , the above mentioned demodulated output becomes 
     
         2Vs + √Vn.sub.1.sup.2 + √Vn.sub.2.sup.2 = 2Vs + √2 √Vo.sup.2. 
    
     Therefore, the signal-to-noise ratio is improved by approximately 3 dB as compared to the use of either PLL 31a or 31b, alone. 
     If the delay time difference and the high-frequency characteristic difference of the PLLs 31a and 31b in the above described embodiment of the invention are negligibly small, the delay circuit 35 and the high-frequency characteristic correction circuit 36 may be omitted. Furthermore, three or more PLLs may be used. 
     FIG. 3 shows one embodiment of a specific circuit for use in the system of FIG. 2. Those parts which are the same as corresponding parts in FIG. 2 are designated by like reference numerals. 
     An angle-modulated signal is introduced through the input terminal 30 and supplied to the PLLs 31a and 31b. The PLL 31a comprises an integrated circuit 40a containing built-in components such as the above mentioned phase comparator 31a, loop filter 33a, and voltage-controlled oscillator 34a. An output signal is demodulated in the PLL 31a and passed through a low-pass filter 41a, where its carrier component is removed. The resulting signal is passed through an amplifier 42 and the delay circuit 35, which comprises a plurality of inductors and capacitors. The demodulated signal which has passed through the delay circuit 35 is passed through an amplifier 43 and then fed to the addition circuit 37. 
     The angle-modulated signal is supplied through the input terminal 30 and demodulated in the PLL 31b, having an integrated circuit 40b. The resulting demodulated output is passed through a low-pass filter 41b, where its carrier component is removed. The resulting demodulated output is supplied to the high-frequency characteristic correction circuit 36. This correction circuit 36 comprises an operational amplifier 45 and a correction network 46, comprising a resistor and capacitors and connected in the negative feedback loop of the operational amplifier 45. The output signal of the correction circuit 36 is supplied to the addition circuit 37 and, at a junction 44, is added to the demodulated signal from amplifier 43. The resulting signal is led out through the output terminal 38. 
     The lock range widths of the PLLs 31a and 31b are determined by the resistance values of resistors 47 and 48. In the instant embodiment of the invention, the resistance value of the resistor 47 is 15 KΩ, while the resistor 48 is 3.3 KΩ. As a result, the lock ranges of the PLLs 31a and 31b are as indicated in FIG. 4. The curve I indicates the lock range of the PLL 31a, and the curve II indicates the lock range of the PLL 31b. 
     Furthermore, U.S. Pat. NO. 3,936,618, describes an input angle-modulated signal transmission system. A PLL and synchronous detector are provided. An unlocking of the PLL is detected by the synchronous detector to produce a detection signal for varying the lock range of the PLL. In this previous system, there is a problem since the output signal of the synchronous detector is also varied by the variation of the lock range of the PLL. Thus, an unlocking of the PLL cannot be detected with accuracy. Furthermore, there are various causes for abnormal noises. Hence, a single synchronous detector cannot distinguish and detect all abnormal noises, due to different causes. 
     FIG. 5 shows a second embodiment of the invention in which the concept of the above described embodiment is incorporated. In FIG. 5, those parts which are the same as corresponding parts in FIG. 2 are designated by like reference numerals and will not be described in detail again. 
     An angle-modulated signal is introduced through the input terminal 30 and supplied to the PLL 31a and to a synchronous detector 50a. From the voltage-controlled oscillator 34a, there is an output which is 90° out of phase relative to the oscillation output supplied to the phase comparator 32a, which is fed to the synchronous detector 50a. As a consequence, the input angle-modulated signal is subjected to the synchronous detector 50a, with the signal from the voltage-controlled oscillator 34a. The resulting synchronous detected output difference signal is formed into a control signal in a control signal forming circuit 51a. 
     When the PLL 31a locks to the input signal during normal demodulation, the input signal into the PLL 31a and the signal supplied from the voltage-controlled oscillator 34a to the phase comparator 32a have a phase difference of 90°. The input signal supplied into the synchronous detector 50a and the input signal from the voltage-controlled oscillator 34a to the synchronous detector 50a have a mutual relationship wherein the phase difference therebetween is zero degrees (same phase) or 180° (opposite phase) output voltage of the synchronous detector 50a is substantially zero. The synchronous detector 50a produces an output voltage in accordance with the phase difference between the input signal and the signal from the voltage-controlled oscillator 34a. 
     Since the lock range of the PLL 31a fixed, the synchronous detector 50a can accurately and positively detect abnormalities. 
     The control signal from the control signal forming circuit 51a is supplied to a control circuit 52a, where it controls the demodulated output from the PLL 31a. An attenuation or muting circuit shown in FIG. 6 or 13 of U.S. Pat. No. 3,936,618, for example, can be used for the control circuit 52a. 
     The system containing the PLL 31b is similar to that described above. The corresponding parts are designated by like reference numerals, but with the subscript b. A detailed description of these parts will be omitted. 
     In the instant embodiment of the invention, as in the preceding embodiments, a delay circuit 35 may be provided in the demodulated output transmission system of the PLL 31a. A high-frequency characteristic correction circuit 36 may be provided in the demodulated output transmission system of the PLL 31b. 
     If an abnormal sound is generated in the demodulated signal as a result of admixing of the higher harmonics of the direct-wave signal into the angle-modulated signal band, the output signal waveform of the synchronous detector 50a of the wide lock range PLL 31a is as indicated in FIG. 6(A). The output signal waveform of a synchronous detector 50b of the narrow lock range PLL 31b is as indicated in FIG. 6(C). 
     Furthermore, if an angle-modulated signal, produced by a modulation signal in which much energy is distributed in the medium low frequencies, is introduced as input, and its frequency deviation is greater than the lock range of the PLL 31b (although it is less than the lock range of the PLL 31a), the output waveform of the synchronous detector 50a is as indicated in FIG. 6(B). The output waveform of the synchronous detector 50b is as indicated in FIG. 6(D) since the angle-modulated signal is in an overmodulated state relative to the lock range of the PLL 31b. 
     Accordingly, the control signal forming circuit 51a will form a control signal, not in response to the signal waveform of FIG. 6(B), but in response to the signal waveform of FIG. 6(A). Furthermore, the control signal forming circuit 51b will form a control signal, not in response to the signal waveform of FIG. 6(C), but in response to the signal waveform of FIG. 6(D). 
     Switching circuits may be used for the control circuits 52a and 52b and a demodulated output containing noise is cut off so that it will not be led out through the output terminal. Simple switching circuits are used for the control circuits 52a and 52b. A difference of 6 dB arises between the output levels when both demodulated outputs of the PLLs 31a and 31b are led out and when the demodulated output of one of the PLLs is led out. This is not desirable since, in this case a great variation occurs in the separation of the reproduced sound generated by the loudspeakers. 
     Accordingly, in the specific circuit described below, the output level is continually maintained constant, irrespective of switching operation. 
     FIG. 7 shows a specific circuit for use in the system illustrated in FIG. 5. In this circuit, switching circuits are used for the control circuits 52a and 52b in FIG. 5. In FIG. 7, those parts which are the same as corresponding parts in FIG. 5 are designated by like reference numerals. 
     An angle-modulated signal is introduced into this circuit through the input terminal 30. Then, it is supplied to a circuit including an integrated circuit 60a containing a built-in PLL 31a and the synchronous detector 50a. The input signal is also supplied to a circuit including an integrated circuit 60b containing a built-in PLL 31b and the synchronous detector 50b. Signals thus demodulated by the PLLs within the integrated circuits 60a and 60b are sent to respective low-pass filters 61a and 61b. There their unwanted carrier components are removed. Thereafter, they are supplied respectively to the emitters of switching transistors 62a and 62b. 
     Furthermore, detection signals from the synchronous detectors within the integrated circuits 60a and 60b are respectively supplied to the control signal forming circuits 51a and 51b. The control signal forming circuit 51a comprises transistors Q1 through Q4, resistors R1 through R9, and capacitors C1 through C5. The capacitor C2 and the resistor R1 constitute a differentiation circuit. The transistors Q1 and Q2, the resistors R1 through R5, and the capacitor C2 constitute a Schmitt trigger circuit. The resistor R6 and the capacitor C4 constitute an integration circuit for pulse density detection. 
     When a detection output is produced by the integrated circuit 60a, the transistors Q1, Q2, and Q3 successively switch &#34;ON&#34;. The charge in the capacitor C5 is rapidly discharged through the transistor Q3. As a consequence, the transistor Q4 also switches &#34;ON&#34;. The transistor 62a, whose base is connected to the collector of the transistor Q4, switches &#34;OFF&#34;. When the synchronous detector stops producing its detection output, the transistors Q1, Q2, and Q3 successively switch &#34;OFF&#34;. The capacitor C5 is charged through the resistor R7, with a relatively long time constant. When the capacitor C5 has been thus charged to a specific value, the transistor Q4 switches &#34;OFF&#34;, and the transistor 62a switches &#34;ON&#34;. 
     The control signal forming circuit 51b comprises transistors Q5 and Q6, capacitors C6 and C7, and resistors R10 through R13. The capacitor C6 and the resistor R10 constitute a differentiation circuit. When the synchronous detector of the integrated circuit 60b produces an output, the transistors Q5 and Q6 successively switch &#34;ON&#34;, while the transistor 62b switches &#34;OFF&#34;. When the output of the synchronous detector disappears, the transistors Q5 and Q6 switch &#34;OFF&#34;, while the transistor 62b switches &#34;ON&#34;. 
     The demodulated signals which have passed through the transistors 62a and 62b in an &#34;ON&#34; state are added at a junction point 63. The resulting signal is led out by way of a field-effect transistor (FET) 65 and through the output terminal 38. A resistor 64 of high impedance is connected between the point 63 and ground. 
     When the input voltages of the emitters of the transmitters are denoted respectively by ei 1  and ei 2 , the signal source impedances thereof by Rg 1  and Rg 2 , the resistances between the emitters and collectors of the transistors 62a and 62b by Ra and Rb, the resistance value of the resistor 64 by Rc, and the voltage applied to the gate of the FET 65 by e o , the voltage e o  can be expressed as follows: ##EQU1## Then, if the signals passing through the transistors 62a and 62b are considered to be substantially equal, the following relationships may be used: ##EQU2## From Eqs. (1) and (2), the following equation is obtained: ##EQU3## If the transistors 62a and 62b have the same characteristics and both are &#34;ON&#34;, the following relationship is valid: 
     
         R = Ra = Rb                                                (4) 
    
     From Eqs. (3) and (4), the following equation can be obtained: ##EQU4## If, in this expression, R → 0, and Rc&gt;&gt; Rg, the following relationship is obtained: 
     
         e.sub.o ≈ ei . . . (6) 
    
     If transistor 62a is &#34;ON&#34;, and the transistor 62b is &#34;OFF&#34;, the expression for e o , from Eq. (3), becomes: ##EQU5## Since Ra → 0, and Rb → ∞, the following relationships are obtained: ##EQU6## From Eqs. (7) and (8), ##EQU7## Here, if Rc &gt;&gt; Rg, e o  becomes: 
     
         e.sub.o ≈ ei . . . (10) 
    
     The above analysis and results are also the same when the transistor 62a is &#34;OFF&#34;, while the transistor 62b is &#34;ON&#34;. 
     Accordingly, if the impedance Rc of the resistor 64 is switably greater than the impedance Rg, that is, if the preceding stages of the transistors 62a and 62b have low output impedances, and the succeeding stages thereof have high input impedances, the output level of both transistors 62a and 62b are &#34;ON&#34;. The output levels are equal when either one of the transistors 62a and 62b is &#34;OFF&#34;. Therefore, the output can be derived continually with a constant level irrespective of the &#34;ON&#34; and &#34;OFF&#34; states of the transistors 62a and 62b. 
     One example of constants of the circuit elements or components of the circuit organization described above is as follows: 
     
         ______________________________________                                    
Resistors --                                                              
R1    10 KΩ,                                                        
                 R2     12 KΩ,                                      
                                 R3   100 Ω,                        
R4    15 KΩ,                                                        
                 R5     33 KΩ,                                      
                                 R6   33 KΩ,                        
R7    100 KΩ,                                                       
                 R8     680 Ω,                                      
                                 R9   220 KΩ,                       
64    470 KΩ                                                        
Capacitors --                                                             
C1    1,800 PF,  C2     2,200 PF,                                         
                                 C3   0.033 μF,                        
C4    0.1 μF, C5     10 μF,                                         
                                 C6   560 PF,                             
C7    10 μF                                                            
______________________________________                                    
 
    
     Next to be considered is a system wherein there is a PLL 31b with a narrow lock range. When an angle-modulated input signal has a frequency deviation which is wider than the lock range of the PLL 31b, the demodulated signal of the PLL 31b assumes a waveform, as indicated in FIG. 8(A). At this time, the output signal waveform of the synchronous detector 50b becomes as indicated in FIG. 8(B). When there is an input signal in which the higher harmonics of the direct-wave signal is admixed in the angle-modulated wave band, a disturbance wave is dissipated before the VCO 34b locks to the disturbance wave. The VCO 34b has a slow follow-up characteristic with respect to the high frequencies of the PLL 31b. The resulting demodulated output waveform is almost completely free of abnormal sounds as indicated in FIG. 8(C). 
     The output waveform of the synchronous detector 50b is as indicated in FIG. 8(D). The waveforms indicated in FIGS. 8(B) and 8(D) are theoretically determined waveforms. The actual output waveforms of the synchronous detector 50b respectively corresponding thereto are as indicated in FIGS. 8(E) and 8(F). 
     It is necessary to adapt the control signal forming circuit 51b to produce a control signal output, with respect to the output signal of the synchronous detector 50b, having the waveform indicated in FIG. 8(E). Circuit 51b should not produce a control signal output, with respect to the output signal, having the waveform indicated in FIG. 8(F). An example of a modification for positively and accurately carrying out this operation is shown in FIG. 9. FIG. 9 shows only the part of the system containing the PLL 51b, and the part containing the PLL 51a has been omitted. 
     As compared to FIG. 5, the embodiment in FIG. 9, has an integration circuit 70 inserted between the synchronous detector 50b and the control signal forming circuit 51b. The output signal of the synchronous detector 50b is supplied to this integration circuit 70 and is there integrated. The peak value of the signal obtained by the integration of the signal in FIG. 8(E) by the integration circuit 70 is greater than the peak value of the signal obtained by the integration of the signal in FIG. 8(F). 
     Accordingly, the threshold value of the control signal forming circuit 51b is set so that it detects the integrated peak value of the signal indicated in FIG. 8(E). However, it will not detect the integrated peak value of the signal indicated in FIG. 8(F). By this measure, detection of abnormalities can be positively and accurately accomplished. 
     In accordance with the present invention, at least two PLLs of mutually different lock ranges are used. Three or more PLLs could, of course, be used within the purview of the invention. 
     Further, this invention is not limited to these embodiments but various modifications may be made without departing from the scope and spirit of the invention.