Patent Publication Number: US-7710183-B2

Title: CMOS level shifter circuit design

Description:
BACKGROUND 
     1. Field of Disclosure 
     This disclosure relates generally to level shifting circuits, and in particular to level shifting circuits with increased voltage ranges and reduced insertion delays. 
     2. Background 
     In various electronic devices, integrated circuits operating at low supply voltages are interfaced with electronic circuits operating at higher supply voltages. For example, a chip set operating at a first core voltage level (VddL), for example at 0.7 V, can interface with a memory device operating at a higher voltage level (VddH), for example at 1.4 V. In such cases, a level shifting circuit (“level shifter”) can be employed to maintain communication between circuits of different supply voltage levels. 
     Conventional level shifting circuits operate satisfactorily at low voltage ranges, but can fail at low VddL values and wider voltage ranges. In addition, the insertion delay of a level shifting circuit may become unacceptably large. Thus, the development of level shifters operating over relatively wider voltage ranges with reduced insertion delays is desirable. 
     SUMMARY 
     In one aspect, a level shifting circuit includes assist circuits. In one configuration, the level shifting circuit includes an input point, an output point, and a cross-coupled pair of field effect transistors of a first type coupled to the output point. The level shifting circuit also includes a pair of assist circuits that are responsive to changes in input and output voltage levels, and that transiently change the gate-to-source and source-to-drain voltages of the pair of field effect transistors of the first type. The level shifting circuit also includes a pair of field effect transistors of a second type coupled between the input and output points. The field effect transistor pair of the second type are responsive to input voltage levels. In certain configurations, the field effect transistors of the first type are PMOS devices, and the field effect transistors of the second type are NMOS devices. 
     In another aspect, a method of shifting a voltage level is provided. The method includes providing an input signal to a circuit, and, in response to the input signal, transiently weakening one member of a pair of cross-coupled field effect transistors of the circuit until an output node coupled to the pair of cross-coupled field effect transistors is pulled to a final voltage. 
     The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims. It should be appreciated by those skilled in the art that the conception and specific configurations disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. 
         FIG. 1  shows an exemplary wireless communication system in which embodiments of the invention may be advantageously employed; 
         FIG. 2  is a circuit diagram of a conventional level shifting circuit; 
         FIG. 3  is a circuit diagram of a second conventional level shifting circuit based on PMOS transistors in series; and 
         FIG. 4  is a circuit diagram of a level shifting circuit that includes assist circuits. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows an exemplary wireless communication system  100  in which an embodiment of the invention may be advantageously employed. For purposes of illustration,  FIG. 1  shows three remote units  120 ,  130 , and  150  and two base stations  140 . It will be recognized that typical wireless communication systems may have many more remote units and base stations. Remote units  120 ,  130 , and  150  include level shifting circuits  125 A,  125 B and  125 C, which is an embodiment of the invention as discussed further below.  FIG. 1  shows forward link signals  180  from the base stations  140  and the remote units  120 ,  130 , and  150  and reverse link signals  190  from the remote units  120 ,  130 , and  150  to base stations  140 . 
     In  FIG. 1 , remote unit  120  is shown as a mobile telephone, remote unit  130  is shown as a portable computer, and remote unit  150  is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be cell phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, or fixed location data units such as meter reading equipment. Although  FIG. 1  illustrates remote units according to the teachings of the invention, the invention is not limited to these exemplary illustrated units. The invention may be suitably employed in any device which includes level shifting circuits. 
     A conventional level shifting circuit  202  is shown in  FIG. 2 . The circuit  202  includes two NMOS transistors MN 1 ,MN 2  with their sources coupled to ground voltage VSS, and two PMOS transistors MP 1 ,MP 2  with their sources coupled to a source voltage VddH. The drain of the NMOS transistor MN 1  is coupled to the drain of the PMOS transistor MP 1 , and the drain of the NMOS transistor MN 2  is coupled to the drain of the PMOS transistor MP 2 . The gate of the PMOS transistor MP 1  is coupled at a node N 2  to the drains of the NMOS and PMOS transistors MN 2 , MP 2 , while the gate of the PMOS transistor MP 2  is coupled at a node N 1  to the drains of the NMOS and PMOS transistors MN 1 , MP 1 . As a result, the gate of the PMOS transistor MP 1  is coupled to the drain of the PMOS transistor MP 2 , and the gate of the PMOS transistor MP 2  is coupled to the drain of the PMOS transistor MP 1 , forming a cross-coupled pair of PMOS transistors. A node N 3  is coupled to an output point OUT. 
     In the conventional level shifting circuit  202  shown in  FIG. 2 , an input point IN is coupled to the gate of the NMOS transistor MN 1 . The input point IN is also coupled to an inverter INV, which in turn is coupled to the gate of the NMOS transistor MN 2 . 
     When an input signal Vin is in a low level (VSS), the NMOS transistor MN 1  is turned off. At the same time, a signal at the level of VddL is applied via the inverter circuit INV to the gate of the NMOS transistor MN 2 , turning this transistor on so that the node N 2  and the output node N 3  are at the voltage level of VSS. Due to the cross-coupling from the node N 2  to the gate of the PMOS transistor MP 1 , the PMOS transistor MP 1  is turned on so that the node N 1  has a voltage level of VddH. Thus, when the input signal Vin is in a low level, the output point OUT is at a voltage level of VSS and the node N 1  is at a voltage level of VddH. 
     When the input signal Vin is in a high level (VddL), the NMOS transistor MN 1  is turned on. As a result, the node N 1  has a voltage level of VSS. At the same time, a low input signal is applied via the inverter circuit INV to the gate of the NMOS transistor MN 2 , turning this transistor off. Due to the cross coupling from the node N 1  to the gate of the PMOS transistor MP 2 , this transistor is turned on, and the output node N 3  is at the voltage level of VddH. Consequently, when the input signal Vin is in a high level, the output point OUT is at voltage level of VddH and the node N 1  is at a voltage level of VSS. 
     When the input signal Vin changes from low to high, the NMOS transistor MN 1  turns on and attempts to pull the node N 1  from the voltage level of VddH to the voltage level of VSS. However, the PMOS transistor MP 1  is still on and resists (or “fights”) the drop in voltage at the node N 1 . A similar conflict between the PMOS and NMOS transistors MP 2 ,MN 2  occurs when the input signal Vin changes from high to low: the NMOS transistor MN 2  turns on and attempts to pull the output node N 2  from the high voltage level of VddH to the low value of VSS. Although the conventional level shifting circuit can operate satisfactorily when the voltage range between VddH and VddL is relatively small, as VddL becomes lower and the voltage range increases, the PMOS devices become stronger than the NMOS devices, and the NMOS devices are unable to pull down their nodes. Under these conditions, the conventional level shifting circuit  202  will fail. To minimize such failures, the NMOS devices can be made stronger, although this increases the area of the devices. 
     One way of modifying the level shifting circuit  202  to handle wider voltage ranges is to add circuit components in series with the existing PMOS devices. A circuit of this type is shown in  FIG. 3 . In this level shifting circuit  302 , NMOS transistors MN 1 ,MN 2  and PMOS transistors MP 1 ,MP 2  are arranged as in the conventional level shifting circuit  202  shown in  FIG. 2 . However, in the level shifting circuit  302 , a third PMOS transistor MP 3  is added in series with the PMOS transistor MP 1 , and a fourth PMOS transistor MP 4  is added in series with the PMOS transistor MP 2 . The gate of the PMOS transistor MP 3  is coupled to an input point IN. The input point IN is also coupled to an inverter circuit INV, which is coupled to the gate of the NMOS transistor MN 2  and the added PMOS transistor MP 4 . The drains of the NMOS and PMOS transistors MN 1 ,MP 1  are coupled at a node N 1 , and the drains of the NMOS and PMOS transistors MN 2 ,MP 2  are coupled at a node N 2 . An output node N 3  is coupled to an output point OUT. 
     When an input signal Vin in a low level is applied, the NMOS transistor MN 1  is turned off while the PMOS transistor MP 3  is turned on. At the same time, a high input signal is applied via the inverter circuit INV to the gate of the NMOS transistor MN 2 , turning this transistor on, and to the gate of the PMOS transistor MP 4 , turning this transistor partially off. As a result, the nodes N 2 ,N 3  are at a voltage value of VSS. Due to the cross-coupling from the node N 2  to the gate of the PMOS transistor MP 1 , this transistor is on. Thus, both PMOS transistors MP 1 ,MP 3  are on, and the node N 1  is at a voltage value of VddH. Therefore, when the input signal is in a low level, the output point OUT is at a voltage level of VSS and the node N 1  is at a voltage level of VddH. 
     As the input signal changes from a low to a high level (from VSS to VddL), the NMOS transistor MN 1  turns on and begins to pull down the node N 1  from a voltage level of VddH to VSS. This drop in voltage at the node N 1  is opposed by the PMOS transistor MP 1 , which is still on. As the input signal changes from low to high, however, the gate of the PMOS transistor MP 3  also goes higher to a voltage value of VddL. This means that the gate voltage of the PMOS transistor MP 3  is now closer to the transistor&#39;s source value of VddH. Because the gate-to-source voltage of the PMOS transistor MP 3  is less, the transistor is partially turned off. In essence, applying VddL to the gate of the PMOS transistor MP 3  “weakens” the transistor and allows the NMOS transistor MN 1  to more easily pull down the node N 1 . Similarly, when the output node N 3  goes from VddH to VSS, a voltage value of VddL is applied to the gate of the PMOS transistor MP 4 , turning this transistor partially off and making it easier for the NMOS transistor MN 2  to pull the output node N 3  to a lower value. 
     Although the level shifting circuit  302  can work successfully at lower VddL values and at wider voltage ranges than the conventional circuit  202 , the time interval required for an input to produce an output (or the “insertion delay”) is large since two PMOS devices are used for each NMOS device. 
     A configuration of a level shifting circuit having a pair of assist circuits is shown in  FIG. 4 . In the configuration, a level shifting circuit  402  includes a pair of assist circuits  404 , 406 , each of which comprises two field effect transistors of a first type, in this case two PMOS transistors (or devices), coupled to an output node. One portion of the level shifting circuit  402  comprises two field effect transistors of a second type, in this case two NMOS transistors (or devices)  408 , 410 , with their sources coupled to ground voltage VSS, and two field effect transistors of the first type, in this case two PMOS transistors (or devices)  412 , 414 , with their sources coupled to a source voltage VddH. The drain of the NMOS transistor  408  is coupled to the drain of the PMOS transistor  412 , and the drain of the NMOS transistor  410  is coupled to the drain of the PMOS transistor  414 . At a node  416 , the gate of the PMOS transistor  414  is coupled to the drains of the NMOS and PMOS transistors  408 , 412 , while the gate of the PMOS transistor  412  is coupled at an output node  418  to the drains of the NMOS and PMOS transistors  410 , 414 . As a result, the gate of the PMOS transistor  412  is coupled to the drain of the PMOS transistor  414 , and the gate of the PMOS transistor  414  is coupled to the drain of the PMOS transistor  412 , forming a cross-coupled pair of PMOS transistors. 
     In the level shifting circuit  402 , an input point  420  is coupled to the gate of the NMOS transistor  408 . The input point  420  is also coupled to an inverter circuit  422 , which operates at voltage VddL, and which is coupled to the gate of the NMOS transistor  410 . 
     In the assist circuit  404 , two PMOS transistors  424 , 426  are coupled in series, drain-to-source, to the node  416 . The source of the PMOS transistor  426  is coupled to a source voltage VddL. The gate of the PMOS transistor  424  is coupled to the input point  420 , and the gate of the PMOS transistor  426  is coupled to a node  428  via an inverter circuit  430  which operates at voltage VddH. 
     Similarly, in the assist circuit  406 , two PMOS transistors  432 , 434  are serially coupled, drain-to-source, to the output node  418 . The source of the PMOS transistor  434  is coupled to a source voltage VddL. The gate of the PMOS transistor  432  is coupled indirectly to the input point  420  via the inverter circuit  422 , and the gate of the PMOS transistor  434  is coupled to a node  436  via an inverter circuit  438  which operates at voltage VddH. 
     At steady state, at least one of the PMOS transistors  424 , 426  in the assist circuit  404 , and at least one of the PMOS transistors  432 , 434  in the assist circuit  406 , is off. 
     The NMOS transistors  408 , 410  and the PMOS transistors  412 , 414  are arranged similarly to those in the level shifting circuit  202  of  FIG. 2 . At steady state, when an input signal Vin having a low voltage level is applied, the NMOS transistor  408  is turned off while the NMOS transistor  410  is turned on. The output node  418  and the gate of the PMOS transistor  412  are at a voltage level of VSS. Because the PMOS transistor  412  is turned on, the node  416  is at a voltage level of VddH. 
     Although the node  428  is at a value of VSS, the gate of the PMOS transistor  426  is at a value of VddH due to the inverter circuit  430 . Because the gate voltage is higher than the assist circuit source voltage of VddL, the PMOS transistor  426  is turned off. Thus, the assist circuit  404  is turned off. 
     Similarly, the assist circuit  406  is turned off because the voltage applied to the gate of the PMOS transistor  432  is at the level of VddL, which is the same as the transistor&#39;s source voltage. 
     At steady state when the input signal Vin is at a high level, the NMOS transistor  408  is turned on and the NMOS transistor  410  is turned off. The node  416  is at a voltage value of VSS, as is the gate of the PMOS transistor  414 . The output node  418  is at the voltage value of VddH and the PMOS transistor  412  is off. In the assist circuit  404 , the PMOS transistor  424  is off since its gate voltage of VddL is the same as its source voltage. Also, in the assist circuit  406 , the PMOS transistor  434  is turned off since its gate voltage of VddH is higher than its source voltage of VddL. 
     When the input signal changes from a low value of VSS to a high value of VddL, the NMOS transistor  408  turns on. In addition, the input signal to the NMOS transistor  410  goes from a high value of VddL to a low value of VSS due to the inverter circuit  422 . Momentarily, the gate of the PMOS transistor  432  in the assist circuit  406  is at a low value of VSS while the gate of the PMOS transistor  434  in the same assist circuit is already at a low value of VSS. When this occurs, the source voltage VddL of the assist circuit  406  is greater than the gate voltages of both PMOS transistors  432 , 434  and both transistors  432 , 434  are turned on. As a 
     Thus, the assist circuit  406  has at least two properties. First, by momentarily raising the gate voltage of the PMOS transistor  412 , the assist circuit  406  weakens the PMOS transistor  412  by reducing the gate-to-source voltage, making it easier for the NMOS  408  to pull down the voltage at the node  416 . Second, by momentarily charging the output node  418  to a voltage value of VddL, the assist circuit  406  does part of the work in bringing the output node  418  to its final value of VddH. 
     The assist circuit  404  works in a similar manner. When the input signal changes from a high value of VddL to a low value of VSS, the PMOS transistor  424  is turned on while the PMOS transistor  426  is already on. Thus, the node  416  is momentarily charged to a voltage value of VddL. Also, due to the cross coupling, the gate of the PMOS transistor  414  is brought to a value of VddL, which momentarily weakens the transistor so that the NMOS transistor  410  can more easily pull down the output voltage to a voltage value of VSS. 
     The assist circuits  404 , 406  only operate while the NMOS transistors  408 , 410  are pulling their respective nodes  416 , 418  to a final voltage value of VSS. Once the NMOS transistors have pulled their drain voltages and the nodes  416 , 418  to the final voltage value, the assist circuits turn off since at a final voltage, at least one PMOS transistor in each assist circuit is turned off. Thus, the assist circuits operate transiently to weaken the PMOS transistors  412 , 414  and to charge the nodes  416 , 418  to VddL. 
     Although for clarity, only the node  418  is labeled as “output node,” it should be understood that the node  416  can also be considered an output node. 
     Compared to the conventional level shifting circuits  202 , 302 , the level shifting circuit  402  improves (reduces) the insertion delay by charging the output node  418  to VddL as soon as the input signal goes high. The insertion delay is also improved since each NMOS transistor competes against only one PMOS transistor rather than two PMOS transistors as in the level shifting circuit  302 . The level shifting circuit  402  also has better low VddL behavior since the gate voltages of the PMOS devices are transiently raised to VddL, making it easier for the NMOS devices to oppose the PMOS devices. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding configurations described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.