Patent Publication Number: US-9846475-B2

Title: Controlling power consumption in multi-core environments

Description:
BACKGROUND 
     High performance computing (HPC) and supercomputing environments may require integration of multiple cores. However, power consumption in these environments may be significant. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The various advantages of the embodiments of the present invention will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which: 
         FIG. 1  is a block diagram that illustrates an example computer system, in accordance with some embodiments; 
         FIG. 2  is a block diagram that illustrates an example of a multi-core processor, in accordance with some embodiments; 
         FIG. 3  is a block diagram that illustrates example of a socket power control unit (PCU), in accordance with some embodiments; 
         FIG. 4  is a block diagram that illustrates an example of a core local power unit (CLPU) that may be used to control a frequency of a core, in accordance with some embodiments; and 
         FIG. 5  is a flowchart of an example method of modulating the frequency of a core in a tile, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments may involve an apparatus that enables modulation of a frequency of a first core in a multi-core environment, wherein the apparatus may include logic to determine power limit assigned to a first core, logic to determine a stall count of the first core, and logic to modulate the frequency of the first core based at least on the power limit assigned to the first core and the stall count of the first core. The first core may be included in a first tile of a socket in the multi-core computer environment. 
     Embodiments may involve a system in which a phase locked loop (PLL) is configured to be associated with a clock signal in a multi-core environment. The system may include a socket coupled with the PLL and be configured to include multiple tiles. At least one of the tiles may include a first core and a second core. The first core may be configured to include logic to determine a power limit assigned to a first core, determine a stall count of the first core, and modulate the frequency of the first core based at least on the power limit assigned to the first core and the stall count of the first core. The modulation of the frequency of the first core may be performed independently of a frequency of the tiles not associated with the first core. 
     Embodiments may involve a computer implemented method that provides for modulating a frequency of a core in a first tile of a multi-core environment at least independently of cores in other tiles based at least on an estimated power requirement of the core, a power limit assigned to the core and stall count of the core. The first and the other tiles may be associated with a phase locked loop (PLL) of a socket. 
     Turning to  FIG. 1 , a block diagram that illustrates an example computer system  100  is shown, in accordance with some embodiments. The computer system  100  may include a central processing unit (CPU)  105 , a graphics and memory controller hub (GMCH)  110 , and an input/output controller hub (ICH)  125 . The GMCH  110  may be coupled to the CPU  105  via a bus  107 . The ICH  125  may be coupled to the GMCH  110  via a bus  122 . The GMCH  110  may also be coupled to memory devices  115  and display devices  120 . The ICH  125  may be coupled to I/O devices  130 . The GMCH  110  may include a graphics system  200  (not shown). Although the CPU  105 , the GMCH  110  and the ICH  125  may be illustrated as separate components, the functions of two or more of these components may be combined. A power supply  150  may be used to provide power to the computer system  100 . The power supply  150  may be a battery or an external power source. 
     For some embodiments, the CPU  105  may be a multi-core processor. For example, the multi-core processor may be based on the Many Integrated Core (MIC) architecture of Intel Corporation of Santa Clara, Calif. and may be implemented as a PCI Express (Peripheral Component Interconnect Express) card. The computer system  100  may also include many other components; however, for simplicity, they are not shown. For some embodiments, the computer system  100  may be a server computer system. 
     Turning to  FIG. 2 , a block diagram that illustrates an example multi-core processor is shown, in accordance with some embodiments. The multi-core processor  200  may include multiple cores  240 ,  242 ,  250 ,  252 ,  260 ,  262 ,  270  and  272  and multiple tiles  205 ,  215 ,  225  and  235 . Each tile may include two cores. For example, the tile  205  may include the cores  240  and  242 . It should be noted that the number of tiles and cores in the multi-core processor  200  may be many more. For example, there may be fifty (50) cores included in twenty five (25) tiles. The cores  240 - 272  and the tiles  205 - 235  may be associated with a socket. 
     Generally, the multi-core processor  200  may be implemented with a single phase locked loop (PLL)  280  providing a common reference signal and therefore the same frequency for all of the tiles  205 - 235  and cores  240 - 272 . This may limit all of the cores  240 - 272  to a single frequency and therefore a single performance (P) state. One possible solution to overcome this limitation is to implement one PLL per core or tile. This may enable placing the core  240  of the tile  205  into one P state (e.g., P 0 ) and the core  250  of the tile  215  into a different P state (e.g., P 1 ). This solution, however, may not be practical when there are design or power constraints. 
     Turning to  FIG. 3 , a block diagram that illustrates an example socket power control unit (PCU) is shown, in accordance with some embodiments. The PCU  305  may be configured to assign a power limit  310  to which each of the tiles in the socket may be assigned. The PCU  305  may also assign a thermal limit  315  to the tile. The PCU  305  may include a socket meter  325 , which may be configured to receive a power estimate  320  from each of the tiles. For some embodiments, the power limit  310  assigned to a tile may be proportional to a power estimate  320  of the tile. The PCU  305  may be associated with a socket power limit (also referred to as a running average power limit (RAPL))  330 . 
     The PCU  305  may periodically (e.g., every few milliseconds) re-evaluate the tile power limit  310  based on the RAPL  330 . The PCU  305  may be configured to compare the power estimate  320  received from the tile with the assigned power limit  310 . For some embodiments, when the power estimate  320  is less than the power limit  310 , the PCU  305  may reduce the power limit  310 . For some embodiments, when the power estimate  320  is close to the power limit  310  within a predetermined range, the PCU  305  may increase the power limit  310 . 
     Turning to  FIG. 4 , a diagram of a core local power unit that may be used to control the frequency of a core is shown, in accordance with some embodiments. Since the workloads running on the individual cores may be different, it may be advantageous to be able to control the P state for each core or tile independently of the other cores or tiles in the same socket while using the same PLL for the socket. In this example, core local power unit (CLPU)  400  may be associated with the core  240  ( FIG. 3 ), and the CLPU  401  may be associated with the core  242  ( FIG. 3 ). 
     The CLPU  400  may include a core energy monitor  405 . For some embodiments, the power estimate  320  (shown in  FIG. 3 ) may be determined by the core energy monitor  405  of the CLPU  400  and the core energy monitor (not shown) of the CLPU  401 . The CLPU  400  may include Performance/Throttle (P/T) selection logic  410 . The PIT selection logic  410  may be configured to control the power consumption of the core  240 . This may include the placing the core  240  into different performance (P) states or throttling (T) states. 
     The P/T selection logic  410  may be configured to modify the clock rate or frequency at which the core  240  may be operating. The P/T selection logic  410  may also control a voltage operating point for the core  241 . For example, when placed in a P 0  state, the core  240  may operate at a relatively high frequency high performance level and may have more power consumption; when placed in a P 1  state, the frequency and performance of the core  240  may be lower and the power consumption may be less; when placed in the T or throttled state, the core  240  may he throttled by modulating the frequency and the power consumption may be at its lowest. Having the core  240  operating at a low frequency level may also reduce the thermal load and cooling requirement associated with the core  240 . 
     The core energy monitor  405  may be configured to receive an activity counter  407  from the core  240  to determine the core energy  420 . The activity counter  407  may include information related to a number of times the core  240  is placed in the C 0  state, the number of instructions retired, the number of core stalls, etc. 
     The P/T selection logic  410  may be configured to receive information regarding the core energy  420  from the core energy monitor  405 , core stall count  409  from the core  240 , thermal limit  315  from the PCU  305 , and power limit  310  from the PCU  305 . For some embodiments, when the power estimate  320  is determined to be greater than the assigned power limit  310 , the CLPU  400  may cause the frequency of the core with the higher core stalls to be modulated. A threshold may be used to determine whether the core stall count  409  is at a level that may affect the modulation of the frequency of the core  240 . For example, when the core stalls, it may not perform any instruction. As such, modulating the frequency of the core to a lower frequency may not affect its performance but may reduce its power consumption. The modulation of the frequency may be proportional to the core stall ratio (e.g., stall vs. not stall) and may be bounded by the power limit. The modulation of the frequency of the core may be performed by the core clock modulation module  420 . The core clock modulation module  410  may be coupled with the core clock gating control  415 . The core clock gating control  415  may be coupled with the PLL  280  (shown in  FIG. 2 ). By modulating the frequency of the cores in the socket based on the estimated power  320  and the power limit  310 , the performance and power consumption of the individual cores may be optimized. For some embodiments, the modulation of the frequency of the core may further be based on the assigned thermal limit  315 . For example, when it is determined that a temperature of the core is near the assigned thermal limit  315 , the P/T selection logic  410  may reduce the frequency of the core. The P/T selection logic  410  may also receive user requirement  490  and Operating System (OS) requirement  495  and use these requirements to determine how to modulate the frequency. 
     Turning to  FIG. 5 , an example flow diagram illustrating a process performed by a core local power unit (CLPU), in accordance with some embodiments. The process may correspond to the CLPU  400  managing the power consumption of the core  240 . At block  505 , the CLPU may determine a power limit assigned to a core. The power limit may be assigned by a PCU  305  (shown in  FIG. 4 ). At block  510 , the estimated power required by the core may be determined. The estimated power requirement may be determined by the core energy monitor  405  (shown in  FIGS. 4 and 5 ). At illustrated block  515 , the power limit is compared with the estimated power requirement to determine whether the power assigned to the core by the PCU  305  is appropriate. For example, when the estimated power requirement is much less than the power limit assigned by the PCU  305 , the power limit may be reduced. At block  520 , a number of core stalls may be determined. At block  525 , the frequency of the core may be modulated based on a result of the comparison between the estimated power requirement and the power limit and based on the number of core stalls. For example, the frequency may be decreased when the number of core stalls is higher than a predetermined threshold and the estimated power requirement is less than the power limit. Although not shown in  FIG. 5 , the frequency of the core may also be modulated based on the thermal limit assigned to the core by the PCU  305 . 
     Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints. 
     One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor. 
     Example sizes/models/valuues/ranges may have been given, although embodiments of the present invention are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments of the invention. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments of the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that embodiments of the invention can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting. 
     The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms “first”, “second”, etc. might be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated. 
     Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments of the present invention can be implemented in a variety of forms. Therefore while the embodiments of this invention have been described in connection with particular examples thereof, the true scope of the embodiments of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.