Patent Publication Number: US-10320335-B1

Title: Compact doherty power amplifier using non-uniform phase match devices

Description:
TECHNICAL FIELD 
     The present invention relates generally to a compact Doherty power amplifier using non-uniform phase match devices. 
     BACKGROUND 
     RF power amplifiers are important elements in wireless communication infrastructure. One of the key cost factors of wireless service providers is the real estate rental cost of the base-station installation including the RF power amplifiers. A small form factor of the power amplifiers is therefore of high interest to wireless service providers. The Doherty power amplifier topology and its derivatives are one of the most preferred topologies due to its simple architecture and high efficiency operation for modulated signals. However, with the highly increasing demand of data traffic, the foot-print of the Doherty power amplifier is getting larger in order to meet the large power back-off operation for high efficiency with the modulated signals. One of the most typical way of improving average efficiency is using multiple way or multiple stage Doherty amplifiers, which take up a large space. 
     SUMMARY 
     An RF amplifier comprises an amplifier chip on a flange having an input and an output comprising a parasitic capacitance and a parasitic inductance; a first chip capacitor coupled to the output of the output of the amplifier by a first plurality of bond wires; and a second chip capacitor coupled to the first chip capacitor by a second plurality of bond wires; and an output impedance matching network having an input coupled to the output of the second chip capacitor by a third plurality of bond wires, and an output, and a phase shift between the input and the output of less than 90 degrees, wherein the phase shift from the output of the amplifier chip to the output of the output impedance matching network is 180 degrees. 
     According to embodiments, a device design method achieves a small form factor without compromising amplifier performance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1 ( a )  shows an ideal two-way Doherty amplifier architecture; 
         FIG. 1 ( b )  shows a conventional two-way Doherty amplifier implementation structure; 
         FIG. 2 ( a )  shows an ideal three-way Doherty amplifier architecture; 
         FIG. 2 ( b )  shows a conventional three-way Doherty amplifier implementation structure; 
         FIG. 3 ( a )  is a practical device schematic with parasitic components and an output matching network; 
         FIG. 3 ( b )  is a practical device schematic with parasitic components, an output matching network, and additional internal matching elements according to an embodiment; 
         FIG. 3 ( c )  is an implementation of the device schematic of  FIG. 3 ( a ) ; 
         FIG. 3 ( d )  is an implementation of the device schematic of  FIG. 3 ( b )  according to an embodiment, using chip capacitors and bonding wires; 
         FIG. 4 ( a )  is a conventional Doherty amplifier schematic with the quarter wave length transmission line; 
         FIG. 4 ( b )  is a Doherty amplifier schematic with a 180° phase shift match device, according to an embodiment; 
         FIG. 4 ( c )  is a layout example of the conventional Doherty amplifier of  FIG. 4 ( a ) ; 
         FIG. 4 ( d )  is a layout example of the Doherty amplifier of  FIG. 4 ( b ) , according to an embodiment; 
         FIG. 5 ( a )  is a layout embodiment of the three-way Doherty amplifier of  FIG. 2 ( b ) ; 
         FIG. 5 ( b )  is a more compact layout embodiment of the three-way Doherty amplifier, according to an embodiment; and 
         FIG. 5 ( c )  is an even more compact layout embodiment of the three-way Doherty amplifier, according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     Doherty power amplifier architectures are known in the art and include at least one main amplifier and one peaking amplifier. The outputs of the main amplifier and peaking amplifier are typically added together to provide an output signal with maximum linearity. The input and output paths of the main amplifier and peaking amplifier typically include phase shifting. For example, a phase shift of λ/4 (ninety degrees) in the output of the peaking amplifier provided by a transmission line segment is typically used in a two-way Doherty power amplifier. 
       FIG. 1 ( a )  shows an ideal two-way Doherty amplifier architecture  102  including a main amplifier current source I m  in series with a phase shift impedance Z TL  (delay line) having a phase shift of λ/4 (ninety degrees) coupled to node  110 . A peaking amplifier current source I a  is also coupled to node  110 . The ideal two-way Doherty amplifier architecture  102  is completed with a summing resistance R sum  coupled from node  110  to ground. 
       FIG. 1 ( b )  shows a typical implementation structure  104  of a two-way Doherty amplifier in the presence of the non-negligible parasitic components. Implementation  104  includes a main amplifier represented by transistor M 1  having a gate coupled to input node  106 , and a source coupled to ground. Other more complicated amplifiers can be used as is known by those skilled in the art. In  FIG. 1 ( b )  the drain of transistor M 1  is shown to be coupled to parasitic components including a parasitic capacitance C DS1  coupled to ground, and a series-coupled parasitic inductance L 1 . Parasitic inductance L 1  is coupled to a first output impedance matching network OMN 1 , which in turn is coupled to summing node  110 . Similarly, the drain of transistor M 2  (representing an implementation of the peaking amplifier) is shown to be coupled to parasitic components including a parasitic capacitance C DS2  coupled to ground, and a series-coupled parasitic inductance L 2 . Parasitic inductance L 2  is coupled to a second output impedance matching network OMN 2 , which in turn is coupled to summing node  110  through phase shifting impedance Z TL  having a phase shift of ninety degrees. The main amplifier current (I m ) and the peaking amplifier current (I a ) are combined at the summing node  110  where the load at the summing node is represented by R sum . However, the RF power devices such as laterally diffused metal oxide semiconductors (LDMOS) or gallium nitride (GaN) devices have non-negligible parasitic components such as the drain to source capacitance (CDS) or the drain wire inductance (L 1 ), previously described. Those parasitic components introduce phase shifts in the RF signals. The conventional design practices use the output impedance matching networks (OMN) such that the matched devices have a ninety degree phase shift. Therefore, as shown in  FIG. 1 ( b ) , the output matching network behaves as the Doherty impedance inverter. However, it inverts the peaking amplifier signal as well requiring the additional quarter wave length delay line (Z TL ) as depicted in  FIG. 1 ( b )  in order to compensate the ninety degree phase shift. 
       FIG. 2 ( a )  shows an ideal three-way Doherty amplifier architecture  202  including a main amplifier current source I m  in series with a first phase shift impedance Z TL  (delay line) having a phase shift of λ/4 (ninety degrees) coupled to node  204 . A first peaking amplifier current source I a1  is also coupled to node  204 . A second peaking amplifier current source I a2  is coupled to node  206 , and a second phase shift impedance Z TL2  (delay line) having a phase shift of λ/4 (ninety degrees) is coupled between nodes  204  and  206 . The ideal three-way Doherty amplifier architecture  202  is completed with a summing resistance R sum  coupled from node  206  to ground. 
       FIG. 2 ( b )  shows a typical implementation structure  203  of a two-way Doherty amplifier in the presence of the non-negligible parasitic components. Implementation  203  includes a main amplifier represented by transistor M 1  having a gate coupled to input node  208 , and a source coupled to ground. Other more complicated amplifiers can be used as is known by those skilled in the art. In  FIG. 2 ( b )  the drain of transistor M 1  is shown to be coupled to parasitic components including a parasitic capacitance C DS1  coupled to ground, and a series-coupled parasitic inductance L 1 . Parasitic inductance L 1  is coupled to a first output impedance matching network OMN 1 , which in turn is coupled to node  204 . Similarly, the drain of transistor M 2  representing the first peaking amplifier is shown to be coupled to parasitic components including a parasitic capacitance C DS2  coupled to ground, and a series-coupled parasitic inductance L 2 . Parasitic inductance L 2  is coupled to a second output impedance matching network OMN 2 , which in turn is coupled to node  204  through phase shifting impedance Z TL2  having a phase shift of ninety degrees. Similarly, the drain of transistor M 3  representing the second peaking amplifier is shown to be coupled to parasitic components including a parasitic capacitance C DS3  coupled to ground, and a series-coupled parasitic inductance L 3 . Parasitic inductance L 3  is coupled to a third output impedance matching network OMN 3 , which in turn is coupled to node  206  through phase shifting impedance Z TL3  having a phase shift of ninety degrees. A phase shifting impedance ZTL 1  also having a phase shift of ninety degrees is coupled between nodes  204  and  206 . The main amplifier current (I m ) and the peaking amplifier currents (I a1  and I a2 ) are combined at the summing node  206  where the load at the summing node is represented by R sum . 
     The amplifier circuit  203  of  FIG. 2 ( b )  shows one of the conventional 3-way Doherty power amplifier implementation examples using the power devices with the parasitic components. As can be seen from both  FIG. 1 ( b )  and  FIG. 2 ( b ) , the phase matching quarter wave length transmission lines (Z TL1 , Z TL2 , and Z TL3 ) are required on a printed circuit board (PCB) resulting in a large power amplifier form factor. The impedance inverter (Z TL1 ) of  FIG. 2( a )  is replaced by the output matching network (OMN 1 ) of the main device (M 1 ) of  FIG. 2 ( b ) . However, using the same device topology, the peaking devices (M 2  and M 3 ) require additional phase delay lines (Z TL2  and Z TL3 ) to compensate for the phase shift introduced by the output matching networks (OMN 2  and OMN 3 ) for proper Doherty power combining at the nodes  204  and  206 . 
     According to embodiments, a customized RF power device design method for a smaller power amplifier foot-print is used that reduces the wireless service providers&#39; real estate rental costs. According to embodiments, power devices have an internal matching network using bonding wires and chip capacitors. Then, the device is matched to a wanted impedance and phase on the board collectively resulting in a ninety degree phase shift from the device intrinsic node to the design reference plane on the board. Embodiments introduce non-uniform phase match devices. In other words, at least one of the devices is internally matched to collectively provide a ninety degree phase shift between the device intrinsic node to the design reference plane whereas at least one of the other devices are internally matched to collectively provide 180° phase shift such that the external quarter wave length delay lines are absorbed inside the package using the chip and wire components, and large separate quarter wave length delay lines need not be used. Therefore, using the two or multiple devices with different phase matches for a Doherty amplifier design, the lateral dimensions of the power amplifier are reduced. 
     The non-uniform phase match device implementations are described in further detail.  FIG. 3 ( a )  shows a schematic diagram  302  of the typical device which is matched to collectively provide 90° phase shift. Typical power devices such as transistor M 1  have non-negligible parasitic components. The gate of transistor M 1  is coupled to the input node  304 . The dominant parasitic components are the drain-to-source parasitic capacitance (C DS ) and the drain-to-package inductance (L 1 ). These parasitic components are effectively absorbed into the output matching network (OMN) resulting in a ninety degree phase shift to the design reference plane on the PCB from the drain of transistor M 1  to the output node  310 . The OMN could include the package parasitic components or additional internal chip and bonding wires together with the transmission lines on a PCB depending on the matching topology. The electrical length of the devices between the intrinsic nodes to the package reference plane is typically less than ninety degrees and could become ninety degrees with an additional piece of transmission line for layout convenience. One embodiment  320  of this type of device is shown in  FIG. 3 ( c ) . 
     The devices shown in embodiment  320  of  FIG. 3 ( c )  comprise a die ( 1 ), that may comprise one or more transistors or one or more amplifiers, bonding wires ( 2 ), that may include one or more bonding wires, a package output lead ( 3 ), coupled to the output of the transistor or amplifier, and a transmission line on a PCB ( 4 ), or other matching stubs, which are omitted in this example. Also shown in  FIG. 3 ( c )  a flange ( 6 ) that is coupled to ground, and an package input lead ( 7 ). The input bonding wires between the input lead ( 7 ) and the die ( 1 ) are not shown in the example of embodiment  320  of  FIG. 3 ( c ) . The phase shift between the die ( 1 ) intrinsic node (drain of transistor M 1 ) and the output node  310  (end of transmission line on PCB ( 4 )) is made to be ninety degrees in the example embodiment  320 . 
     The schematic of an embodiment device  306  is shown in  FIG. 3 ( b ) . The quarter wave length transmission lines that would otherwise be implemented as large quarter wavelength transmission lines can instead be implemented using lumped elements inside the package or the output matching network OMN is implemented inside the package using additional chip and wires to collectively provide 180° phase shift between the intrinsic node (drain of transistor M 1 ) to the design reference plane (output node  312 ). In other words, the external transmission line that would otherwise be used is replaced by using the internal quasi-lumped components such as chip capacitors and bonding wires (L 1 , C 1 , L 2 , C 2 , and L 3 ). The transmission lines can be represented by using lumped elements either maintaining the characteristic impedance of the transmission line or not. 
     One embodiment  322  of device  306  is shown  FIG. 3 ( d )  where chip capacitors ( 5 A) and ( 5 B) are shown. Note that there are three sets of bonding wires also shown. Bonding wires ( 2 A) connect the die ( 1 ) to the first chip capacitor ( 5 A). Bonding wires ( 2 B) connect the first chip capacitor ( 5 A) to the second chip capacitor ( 5 B). Bonding wires ( 2 C) connect the second chip capacitor to the package output lead ( 3 ). Therefore, the electrical length of this type of device between the intrinsic node (drain of transistor M 1 ) to the package could be above 90° and below 180°. In  FIG. 3 ( d )  a phase shift of 180° between the intrinsic device drain node to node  312  is shown. The gate of transistor M 1  is coupled to input node  308 . The embodiment  322  thus provides a full phase shift of 180° without the use of large quarter wavelength transmission lines that increase the footprint of the amplifier implementation. 
     A typical Doherty amplifier configuration  402  is shown in  FIG. 4 ( a )  where only ninety degree phase shift devices are used and its corresponding layout  420  is shown in  FIG. 4  ( c ). Referring to  FIG. 4 ( a ) , as previously described, a main amplifier includes an input node  404 , transistor M 1 , parasitic elements C DS1  and L 1 , and an output matching network OMN 1  coupled to summing node  410 . A peaking amplifier includes an input node  406 , transistor M 2 , parasitic elements C DS2  and L 2 , and an output matching network OMN 2  coupled to summing node  410  through quarter wavelength transmission line Z TL . Summing node  410  is coupled to impedance transformer MN 3  to output node  412  to present a 50Ω output impedance. 
     Layout  420  of  FIG. 4 ( c )  includes a first amplifier (main amplifier) implementation  422  associated with a first input as previously described, a second amplifier (peaking amplifier) implementation  424  as previously described, a quarter wavelength transmission line  426 , and an impedance transformer  428  to provide the 50Ω output impedance. 
     Another Doherty amplifier schematic  408  using non-uniform phase matched devices according to embodiments is shown in  FIG. 4 ( b )  and its corresponding layout  440  is shown in  FIG. 4 ( d ) . Referring to  FIG. 4 ( b ) , as previously described, a main amplifier includes an input node  404 , transistor M 1 , parasitic elements C DS1  and L 1 , and an output matching network OMN 1  coupled to summing node  410 . A peaking amplifier includes an input node  406 , transistor M 2 , parasitic elements C DS2  and L 21 , chip capacitors C 21  and C 22 , bond wires L 22  and L 23 , and an output matching network OMN 2  coupled to summing node  410 . Summing node  410  is coupled to impedance transformer MN 3  to output node  412  to present a 50Ω output impedance. 
     As can be seen in the layout  440  shown in  FIG. 4 ( d ) , the form factor of layout  440  takes less space than the layout  420  shown in  FIG. 4 ( c )  by using the non-uniform phase matched devices (chip capacitors and bond wires). The summing node impedance is transformed to the system impedance, 50Ω, using an impedance transformer (MN 3 ) and is marked as  428  in the layouts of  FIGS. 4 ( c )  and  4  ( d ). Layout  440  of  FIG. 4 ( d )  includes the first amplifier implementation  424 , which has a phase shift of ninety degrees between the drain of transistor M 1  and the summing node  410 , which is part of element  430 . Element  430  is a small transmission line portion that has a phase shift of less than ninety degrees and can be calculated as part of the phase shift associated with output matching network OMN 1 . Layout  440  of  FIG. 4  ( d ) also includes the second amplifier implementation  422 , which has a phase shift of 180° between the drain of transistor M 2  and the summing node  410 , which is part of element  430 . Element  430  as previously described is a small transmission line portion that has a phase shift of less than ninety degrees and can be calculated as part of the phase shift associated with output matching network OMN 2 . As previously described impedance transformer  428  is also shown. Note that the form factor of layout  440  of  FIG. 4 ( d )  is smaller than that of the form factor of layout  420  of  FIG. 4 ( c )  due to the use of non-uniform phase shift devices and the elimination of the quarter wavelength transmission line  426 . 
     The embodiment method can be applied to three-way Doherty amplifiers as well to decrease the amplifier form factor. One exemplary three-way Doherty amplifier which has the device size ratio M 1 :M 2 :M 3 =1:2:2 (wherein M 1  is a transistor representing the main amplifier, M 2  is a transistor representing a first auxiliary amplifier, and M 3  is a transistor representing a second auxiliary amplifier) can be implemented as can be seen in  FIG. 5 ( a )  using only the ninety degree phase shift devices or using the proposed non-uniform phase matched devices as shown in  FIG. 5 ( b ) . 
       FIG. 5 ( a )  shows a three-way Doherty amplifier  502 A in which Input  1  is associated with the main amplifier  504  having an output phase shift of ninety degrees. Input  2  and Input  3  are associated with the first auxiliary amplifier split into two amplifier halves  506  and  508 , each having an output phase shift of ninety degrees, with the additional ninety degrees of phase shift being provided by quarter wave transmission lines  514  and  516 . Similarly, Input  4  and Input  5  are associated with the second auxiliary amplifier split into two amplifier halves  510  and  512 , each having an output phase shift of ninety degrees, with the additional ninety degrees of phase shift being provided by quarter wave transmission lines  518  and  520 . The outputs of all of the amplifiers are coupled together with another quarter wave transmission line  522 , and then to the output impedance transformer  524 . 
       FIG. 5 ( b )  shows a three-way Doherty amplifier  502 B, wherein quarter wave transmission lines  514 ,  516 ,  518 , and  520  are eliminated according to an embodiment, leading to a smaller form factor than three-way Doherty amplifier  502 A shown in  FIG. 5 ( a ) . Input  1  is again associated with the main amplifier  504  having an output phase shift of ninety degrees. Input  2  and Input  3  are associated with the first auxiliary amplifier split into two amplifier halves  506  and  508 , each having an output phase shift of 180 degrees, using non-uniform phase matched devices (such as discrete chip capacitors and bond wires) as previously discussed. Similarly, Input  4  and Input  5  are associated with the second auxiliary amplifier split into two amplifier halves  510  and  512 , each having an output phase shift of 180 degrees, using non-uniform phase matches devices (such as discrete chip capacitors and bond wires) as previously discussed. The outputs of all of the amplifiers are still coupled together with another quarter wave transmission line  522 , and then to the output impedance transformer  524 . 
     The embodiment method can achieve smaller power amplifier layout areas by replacing the quarter wave length transmission lines with the internal lumped element matching. Furthermore, the center quarter wave length transmission line  522  of  FIG. 5 ( b )  can be implemented in a single package as well using the lumped chip capacitors and wires of which the output impedance  530  is the summing node impedance as can be seen in  FIG. 5 . ( c ). The device in  FIG. 5 ( c )  could have fully chip and wire internally matched components or partial chip and wire matching network with internal PCB using system in a chip technology. The embodiment method can be also applied to other types of 3-way Doherty amplifiers or N-way Doherty amplifiers without limitation. 
       FIG. 5 ( c )  shows a three-way Doherty amplifier  502 C, wherein quarter wave transmission lines  514 ,  516 ,  518 ,  520 , and  522  are eliminated according to an embodiment, leading to a smaller form factor than three-way Doherty amplifier  502 A shown in  FIG. 5 ( a )  or three-way Doherty amplifier  502 B shown in  FIG. 5 ( b ) . Input  1  is again associated with the main amplifier  504  having an output phase shift of ninety degrees provided in a single amplifier package  530 . Input  2  and Input  3  are associated with the first auxiliary amplifier split into two amplifier halves  506  and  508 , each having an output phase shift of 180 degrees, using non-uniform phase matched devices (such as discrete chip capacitors and bond wires) as previously discussed provided in the single amplifier package  530 . Similarly, Input  4  and Input  5  are associated with the second auxiliary amplifier split into two amplifier halves  510  and  512 , each having an output phase shift of 180 degrees, using non-uniform phase matches devices (such as discrete chip capacitors and bond wires) as previously discussed provided in the single amplifier package  530 . The outputs of all of the amplifiers are still coupled together and then to the output impedance transformer  524 . 
     Embodiment methods can be used for a compact Doherty RF power amplifier of customer systems. Therefore, suppliers and customers can utilize this embodiment method to reduce system power amplifier foot-print. The embodiment method can be used to develop and provide customized devices for compact customer power amplifiers without compromising performance. 
     According to embodiments the quarter wave length transmission line on a PCB is replaced by using the internal chip and wire quasi-lumped elements to minimize the RF power amplifier size resulting in non-uniform phase matched customized devices for an amplifier. 
     Embodiment methods can be used in two-way, three-way or multiple-way Doherty or outphasing amplifier topologies where the multiple-phase-matched devices can benefit without limitation. The electrical phases of 90° or 180° do not have to be completed inside an integrated circuit amplifier package. A substantial amount of output phase shift can be implemented inside the package and the rest of the required phase shift can be completed on a PCB using minor pieces of transmission line on the PCB for the layout convenience if needed. 
     Embodiment methods also include cases including the same or different harmonic or baseband frequency responses of the circuits without exclusion. Amplifier  502 C shown in  FIG. 5 ( c ) , for example, could be fully implemented using capacitor and amplifier chips and bond wires (the length and number of the bond wires can be used to adjust the output phase shift as required) inside the package or partially using the chip and wire with internal boards, for example, using system in a chip techniques previously discussed. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.