Patent Publication Number: US-7218687-B2

Title: Receiver with baseline wander correction and correction method thereof

Description:
This application claims priority from Taiwanese application no. 90106688, filed in Taiwan, R.O.C., on Mar. 21, 2001, pursuant to 35 U.S.C. 119(a)–(d). 
   FIELD OF THE INVENTION 
   The present invention relates generally to the field of data transmission and, in particular, to an apparatus and method for minimizing baseline wander in received signals. 
   BACKGROUND OF THE INVENTION 
   In 100 Megabit per second (Mbps) Fast Ethernet applications, a 100 Mbps transmitter transmits a multi-level transmission- 3  (MLT- 3 ) signal through a coupling transformer to a transmission medium, and then a 100 Mbps receiver receives the MLT- 3  signal over the transmission medium. The transformer is equivalent to a high-pass filter which blocks a DC component of the MLT- 3  signal. Unlike the Manchester data encoding scheme used in 10 Mbps Ethernet systems, the MLT- 3  signal is not DC balanced and its DC component varies with the signal pattern. When the DC component is filtered, it cannot be compensated sufficiently by simply adding a common mode voltage with a fixed DC level in the receiver end. Thus, an undesirable phenomenon known as baseline wander occurs. If baseline wander is not cancelled out or compensated for, the phenomenon can cause signal distortion in the front end of the receiver. In the worst case, baseline wander can cause the back end of the receiver to produce incorrect results. 
     FIG. 1  shows a data transmitter baseline wander correction circuit according to the prior art. It uses a feedback circuit taking a feedback signal E feedback  from one of the windings of a coupling transformer to generate an estimated DC value. Then, the estimated DC value is added to a digital signal to be transmitted. Thereby, the baseline wander problem in the output transmit signal is corrected. However, a drawback of the data transmitter of  FIG. 1  is that it is possible for the feedback network to become unstable. Moreover, if the coupling transformer is not matched well, the output transmit signal and the feedback signal will not be the same. Even though there is no baseline wander in the output transmit signal, it cannot ensure that the receive transformer coupled to the transmission medium does not introduce the undesirable phenomenon at receiver end. 
   Another technique for correcting baseline wander is illustrated in  FIG. 2 . By utilizing a peak detector to detect possible directions of baseline wander, the DC value of the received signal is thus adjusted to compensate for baseline wander. A disadvantage of the technique of  FIG. 2  is that the output of the peak detector can be affected by data patterns. This may cause ripples in the detected output so that the system of  FIG.2  cannot achieve perfect baseline wander correction. Also, the received signal passes through an equalizer prior to correcting baseline wander. Hence, the linearity required for input terminals of the equalizer should be very strict. 
   Accordingly, what is needed is a novel technique for correcting baseline wander that utilizes characteristics of baseline wander to compensate for the undesirable phenomenon of a received signal before the signal passes through an equalizer. It would be highly preferable for such a technique to be immune to the effects of the received signal peaks. Further, it would be desirable to have a receiver with baseline wander correction that decreases its production costs. 
   SUMMARY OF THE INVENTION 
   It is an object of the present invention to provide an apparatus and method that corrects the baseline wander inherent in communication systems having transformer coupled transmission medium. 
   The present invention discloses a receiver with baseline wander correction for correcting a received input signal taken from a coupling transformer. In accordance with one aspect of the invention, the receiver with baseline wander correction includes a first and a second biasing resistor networks configured to receive a first and a second signal of the received input signal, and to produce a first correction signal and a second correction signal. A comparator is provided to receive the first and the second correction signals. The comparator compares the first correction signal with the second correction signal in order to produce a control signal. The receiver also includes comparison logic and compensation control circuitry. The comparison logic receives the first and the second correction signals and then generates a logic signal in accordance with the first and the second correction signals. The compensation control circuitry receives the control signal and the logic signal and produces a compensation signal in accordance with the control and the logic signals. Thereafter, the compensation signal is provided to respective output terminals of the first and the second biasing resistor networks to correct respective DC values of the first and the second correction signals. Further, the receiver has an equalizer coupled to the output terminals of the first and the second biasing resistor networks. The equalizer is configured to receive and compensate the first and the second correction signals. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which: 
       FIG. 1  is a block diagram of a baseline wander correction circuit according to the prior art; 
       FIG. 2  is a block diagram of a DC restoration circuit according to another prior art; 
       FIG. 3  is a block diagram of a receiver with baseline wander correction according to the present invention; 
       FIG. 4  shows equivalent small-signal models of biasing resistor networks; 
       FIGS. 5A˜5C  are diagrams illustrating baseline wander for an MLT- 3  signal; 
       FIG. 6  is a flowchart illustrating the operation of the invention; and 
       FIGS. 7A˜7B  are plots showing the simulation result of the invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIGS. 5A˜5C  illustrate a pair of MLT- 3  signals R X+ , R X−  received from two input terminals of a receiver. The MLT- 3  encoding scheme for use in Fast Ethernet is a three-level (H, M, L) differential pulse code that makes a transition whenever a “1” exists in the unencoded input data. As shown in  FIG. 5A , there is no baseline wander in the received signals R x+  and R X− . In  FIG. 5B , the signal R X+  wanders down and the signal R X−  wanders up. In contrast, the signal R X+  wanders up and the signal R X−  wanders down in  FIG. 5C . In the illustrations in  FIGS. 5B and 5C , an important characteristic of baseline wander is that the pair of received signals R X+  and R X−  have opposite wander directions. That is, the signal R X+  wanders up if the signal R X−  wanders down, and vice versa. In general, since a 350 μH coupling transformer has a time constant of approximately 7 μsec, the above-described baseline wander varies slowly. Therefore, the present invention provides a Non-Return-to-Zero Inverted (NRZI) signal RD in accordance with the characteristic of baseline wander to determine when respective DC values of the received signals R X+  and R X−  are adjusted to compensate for baseline wander. 
   Still referring to  FIG. 5A , the average value of (R X+ −R X− ) is about equal to zero when both received signals R X+  and R X−  are at the M level. In  FIG. 5B , the value of (R X+ −R X− ) is less than zero when the received signals R X+  and R X−  are at the M level. This is called the type I baseline wander.  FIG. 5C  shows the type II baseline wander in which the value of (R X+ −R X− ) is greater than zero when the received signals R X+  and R X−  are at the M level. The received signals R X+  and R −  are dynamically corrected by adding an opposite direction of DC current, depending on the value of (R X+ −R X− ) which is positive or negative. Further, when the NRZI signal RD is “0”, it represents that both received signals R X+  and R X−  are at the M level (hereinafter referred to as M-level period for brevity). 
   Referring to  FIG. 3 , a receiver  10  of the invention receives input signals R X+  and R X−  from a coupling transformer (not shown). The received signals R X+  and R X−  are provided to an equalizer  15  which corrects Inter-Symbol Interference (ISI) induced by the transmission medium. The outputs of the equalizer  15 , indicated by R XP  and R XN , pass through comparison logic  12  to produce the NRZI signal RD. The receiver  10  also includes a first biasing resistor network  17 , a second biasing resistor network  18 , a comparator  14 , an integrator  16  and a voltage-to-current (V-I) converter  11 . As described above, the NRZI signal RD is used to identify the M-level period in order to determine when the received signals R X+  and R X−  are adjusted to compensate for baseline wander. Each element of the invention will be described in detail below. 
   The comparison logic  12  compares the signals R XP  and R XN  against a threshold level V th , respectively. As an example, given a 1 volt peak-to-peak MLT- 3  input signal, the threshold level V th  is set at 500 mV. The comparison results are logically ORed together to produce the NRZI signal RD. On the other hand, the comparator  14  receives the signals R XP  and R XN  from the equalizer  15  and compares them to produce a control signal CS. For example, the control signal CS is “1” if the signal R XP  is greater than or equal to the signal R XN ; the control signal CS is “0” if the signal R XP  is less than the signal R XN . When the NRZI signal RD is logic “0”, the integrator  16  charges or discharges a capacitor according to the control signal CS, thereby altering an output voltage VC of the integrator  16 . Thereafter, the V-I converter  11  converts the output voltage VC of the integrator  16  into a compensation current I. The compensation current I is applied to the first and the second biasing resistor networks  17 ,  18  so as to compensate for respective DC values of a first and a second correction signals V X+  and V X− . 
   As shown in  FIG. 3 , the integrator  16  includes a first current source  161 , a second current source  162 , a first switch  163 , a second switch  164 , a third switch  165  and a capacitor C. The first current source  161  provides the capacitor C with a charge current through the first and the third switches  163 ,  165 . On the other hand, the second current source  162  provides the capacitor C with a discharge current through the second and the third switches  164 ,  165 . In one embodiment, the first current source&#39;s current value is equal to the second current source&#39;s current value. Whether the first switch  163  and the second switch  164  are turned on or not, depending on the control signal CS from the comparator  14 . The relationships between the control signal CS and the conduction of the switches  163 ,  164  are listed in Table 1 below. 
   
     
       
         
             
             
             
           
             
                 
               TABLE 1 
             
             
                 
                 
             
             
                 
               Control signal 
               Control signal 
             
             
                 
               CS = 1 
               CS = 0 
             
             
                 
                 
             
           
          
             
                 
             
          
         
         
             
             
             
             
          
             
                 
               First switch (163) 
               OFF 
               ON 
             
             
                 
               Second switch (164) 
               ON 
               OFF 
             
             
                 
                 
             
          
         
       
     
   
   The difference between the signals R XP  and R XN , i.e., the output of the comparator  14 , reflects the status of baseline just during the M-level period. Therefore, the third switch  165  is made conductive when the signals R XP  and R XN  are at the M level. In addition, the NRZI signal is logic “0” if both signals R XP  and R XN  are at the M level as described above. The third switch  165  is controlled by the NRZI signal RD and made conductive as the NRZI signal RD=0. 
     FIG. 4  shows equivalent small-signal models of the first and the second biasing resistor networks  17 ,  18 . As depicted, the first biasing resistor network  17  is constructed of resistors R 1 , R 2 , R 3 , and R 7 / 2  and the second biasing resistor network  18  is constructed of resistors R 4 , R 5 , R 6 , and R 7 / 2 . Resistor R 7  with resistance equal to 100 ohms is a matching resistor. Note that R 7 / 2  stands for an equivalent resistor having half the resistance of R 7 . 
   The concept of the invention will now be described herein. The voltage difference ΔV1 for the first biasing resistor network  17  is given by:
 
Δ V 1 =I× ( R 1 +RA )
 
while the voltage difference ΔV2 for the second biasing resistor network  18  is
 
Δ V 2 =−I ×( R 4 +RB )
 
where I is the compensation current, RA is an equivalent resistance of the parallel combination of R 2 , R 3  and R 7 / 2 , and RB is an equivalent resistance of the parallel combination of R 5 , R 6  and R 7 / 2 . If R 1 =R 4 , R 2 =R 5  and R 3 =R 6 , then
 
|Δ V 1 |=|ΔV 2|
 
After some algebra, the respective DC values of signals V X+  and V X−  in  FIG. 4  are
 
   
     
       
         
           
             V 
             
               X 
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               DC 
             
             ⁢ 
             
               = 
               
                 
                   
                     Vdd 
                     × 
                     
                       R3 
                       
                         R2 
                         + 
                         R3 
                       
                     
                   
                   + 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V1 
                   
                 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 
                   
                     V 
                     
                       X 
                       - 
                     
                   
                   ⁢ 
                   
                     
                        
                       DC 
                     
                     ⁢ 
                     
                       = 
                       
                         
                           Vdd 
                           × 
                           
                             R6 
                             
                               R5 
                               + 
                               R6 
                             
                           
                         
                         + 
                         
                           Δ 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           V2 
                         
                       
                     
                   
                 
               
             
           
         
       
     
   
   Accordingly, ΔV1 and ΔV2 provided by the biasing resistor networks  17 ,  18  can be used to correct the DC values of signals V X+  and V X− . For a type I baseline wander, the signal R XP  is less than the signal R XN  during the M-level period so that the voltage of the capacitor C should be increased. The control signal CS becomes “0” in order to turn on the first switch  163  and turn off the second switch  164 . This enables the capacitor C to be charged when the third switch  165  is turned on. As a result, ΔV1 is increased and ΔV2 is decreased. Conversely, for a type II baseline wander, the signal R XP  is greater than the signal R XN  during the M-level period so that the voltage of the capacitor C should be decreased. The control signal CS becomes “1” in order to turn off the first switch  163  and turn on the second switch  164 . This enables the capacitor C to be discharged when the third switch  165  is turned on. Consequently, ΔV1 is decreased and ΔV2 is increased. 
   Turning now to  FIG. 6 , an operational flowchart of the invention is illustrated. The comparison logic  12  provides the NRZI signal RD and the integrator  16  checks to determine whether the NRZI signal RD is “0” (step S 51 ). The integrator  16  maintains its output voltage VC if the NRZI signal RD is not “0” (step S 52 ), and then it proceeds to step S 56 . Otherwise, the comparator  14  compares the signal R XP  to the signal R XN  (step S 53 ). If the signal R XP  is greater than the signal R XN , it proceeds to step S 54  where the integrator  16  discharges its output voltage VC. If the signal R XP  is less than the signal R XN , it proceeds to step S 55  where the integrator  16  charges its output voltage VC. Finally (step S 56 ), the V-I converter  11  converts the voltage VC into the compensation current I so as to adjust ΔV1 and ΔV2, and thus the signals R XP  and R XN  are corrected. 
   According to the present invention, the compensation current I is controlled by the integrator  16 , and the integrator  16  changes its output to the V-I converter  11  only when the NRZI signal is “0”. Hence, the received signal peaks should not affect baseline wander correction. Furthermore, the receiver  11  of the invention compensates for the DC values of the signals V X+  and V X−  before they pass through the equalizer  15 . It is not necessary that the equalizer  15  have good linearity.  FIG. 7A  shows waveforms of MLT- 3  input signals with baseline wander.  FIG. 7B  shows waveforms that are corrected according to the invention. 
   It is appreciated that the receiver  10  of the invention can use an up/down counter and a digital-to-analog converter (DAC) instead of the integrator  16  and the V-I converter  11 . The output of the comparator  14  causes the up/down counter to increment or decrement its count value. Then, the DAC converts the count value into the corresponding current value. 
   While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.