Patent Publication Number: US-9425801-B2

Title: Programmable logic circuit and nonvolatile FPGA

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2014-091490 filed on Apr. 25, 2014 in Japan, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to programmable logic circuits and nonvolatile field programmable gate arrays (FPGAs). 
     Field programmable integrated circuits, notably field programmable gate arrays (FPGAs), have received attention in recent years. FPGAs realize basic logic data by means of logic blocks. Users can achieve desired logic functions by switching connections among logic blocks by switches. Configuration memories store logic data of the logic blocks and data of the switches for changing connections. Desired logic functions can be realized based on the stored data. 
     Nonvolatile FPGAs can be constituted by storing nonvolatile data in the configuration memories. Antifuse FPGAs including antifuse elements that are typical one-time elements are known as nonvolatile FPGAs. In an antifuse FPGA, an antifuse element serves as the switch connecting the logic blocks. Conventional antifuse FPGAs, however, needed a high voltage transistor in a circuit for selecting an antifuse element since a high voltage is required to program the antifuse element. High voltage transistors have a drawback of increasing the entire area of FPGAs since gate oxide films thereof are thick, and lengths of channels thereof are long. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating an example of an FPGA configuration. 
         FIG. 2  is a circuit diagram illustrating a cell of a programmable logic circuit according to a first embodiment. 
         FIG. 3A  is a cross-sectional view showing a first specific example of a programmable device in each cell. 
         FIG. 3B  is a cross-sectional view showing a second specific example of a programmable device in each cell. 
         FIG. 3C  is a cross-sectional view showing a third specific example of a programmable device in each cell. 
         FIGS. 4A to 4C  are explanatory circuit diagrams illustrating operations of cells. 
         FIGS. 5A and 5B  are diagrams illustrating a first specific example and a second specific example of fuse elements. 
         FIGS. 6A and 6B  are diagrams illustrating a third specific example and a fourth specific examples of fuse elements. 
         FIG. 7  is a circuit diagram illustrating a programmable logic circuit according to a first modification of the first embodiment. 
         FIG. 8  is a circuit diagram illustrating a programmable logic circuit according to a second modification of the first embodiment. 
         FIG. 9  is a circuit diagram illustrating a programmable logic circuit according to a second embodiment. 
         FIG. 10  is a circuit diagram illustrating a programmable logic circuit according to a third embodiment. 
         FIG. 11  is a circuit diagram illustrating a programmable logic circuit according to a fourth embodiment. 
         FIG. 12  is a circuit diagram illustrating a programmable, logic circuit according to a fifth embodiment. 
         FIG. 13  is a circuit diagram illustrating a programmable logic circuit according to a modification of the fifth embodiment. 
         FIG. 14  is a circuit diagram illustrating a programmable logic circuit according to a sixth embodiment. 
         FIG. 15  is a circuit diagram showing a programmable logic circuit according to a modification of a sixth embodiment. 
         FIG. 16  is a circuit diagram illustrating a programmable logic circuit according to a seventh embodiment. 
         FIG. 17  is a circuit diagram illustrating a programmable logic circuit according to an eighth embodiment. 
         FIG. 18  is a cross-sectional view illustrating a programmable device in a programmable logic circuit according to a ninth embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     A programmable logic circuit according to an embodiment includes: a first programmable device with a first terminal and a second terminal, a resistance of the first programmable device being changeable from a high resistance to a low resistance; a second programmable device with a third terminal and a fourth terminal, a resistance of the second programmable device being changeable from a high resistance to a low resistance; a first wiring line to which the first terminal of the first programmable device is connected; a second wiring line to which the third terminal of the second programmable device is connected; a third wiring line to which the second terminal of the first programmable device and the fourth terminal of the second programmable device are connected; and a fuse element of which one terminal is connected to the third wiring line. 
     Embodiments will now be explained with reference to the accompanying drawings. 
     First Embodiment 
     Before a programmable logic circuit according to a first embodiment is described, a configuration of common FPGAs will be described. As shown in  FIG. 1 , an FPGA  100  generally includes a plurality of basic blocks  110  arranged in an array form. Each basic block  110  is connected to adjacent basic blocks  110  with wiring lines, and includes a logic block  120  and a switch block  130 . The logic block  120  performs logical operations basically using a look-up table containing a truth table. 
     Each switch block  130  controls the connection and the disconnection of the wiring lines connecting to adjacent basic blocks  110  so that signals are transmitted to given directions. Each switch block  130  also connects to the logic block  120  included in the relevant basic block  110  including the switch block  130 . The logic block  120  and the switch block  130  are capable of controlling the connection based on data stored in a configuration memory of the programmable logic circuit. 
       FIG. 2  shows a programmable logic circuit according to a first embodiment. The programmable logic circuit according to the first embodiment includes at least one source line SL, at least one program line PL crossing the source line SL, and a cell  10  disposed in an intersection region of the source line SL and the program line PL. The cell  10  includes a programmable device  12  with a first terminal connecting to the source line SL and a second terminal connecting to the program line PL, and a fuse element  16  with a first terminal connecting to the program line PL and a second terminal connecting to a power supply or write circuit (not shown). 
       FIG. 3A  shows a first specific example of the programmable device  12 , which is a metal-oxide-semiconductor (MOS) transistor. This MOS transistor includes a source  12   b   1  and a drain  12   b   2  that are separated from each other in a semiconductor layer  12   a , a gate insulating film  12   c  disposed on a portion of the semiconductor layer  12   a  between the source  12   b , and the drain  12   b   2 , which will serve as a channel  12   b   3 , and a gate electrode  12   d  disposed on the gate insulating film  12   c . The gate insulating film  12   c  and the gate electrode  12   d  overlap portions of the source  12   b   1  and the drain  12   b   2  if viewed from above the gate electrode  12   d . In other words, the portions of the source  12   b   1  and the drain  12   b   2  extend to a portion of the semiconductor layer  12   a  that will serve as the channel  12   b   3  located immediately below the gate insulating film  12   c . The gate electrode  12   d  connects to one of the program line PL and the source line SL, and the source  12   b   1  and the drain  12   b   2  connect to the other. 
     A conductive path is formed between the source  12   b   1  and the drain  12   b   2  via the gate insulating film  12   c  and the gate electrode  12   d  in the programmable device  12  if breakdown of the gate insulating film  12   c  is caused by a program voltage Vprg applied between the gate electrode  12   d  and the source  12   b   1 , and between the gate electrode  12   d  and the drain  12   b   2 . This forms conductive paths between the gate electrode  12   d  and the source  12   b   1 , and between the gate electrode  12   d  and the drain  12   b   2 . If the breakdown of the gate insulating film does not occur, no conductive path is formed among the gate electrode  12   d , the source  12   b   1 , and the drain  12   b   2 . This means that the programmable device  12  disposed in the intersection region between the program line PL and the source line SL is not conductive in the initial state due to the presence of the gate insulating film, and becomes conductive after the programming since the breakdown of the gate insulating film occurs. 
     If the programmable device  12  is a MOS transistor, the breakdown is preferably caused at the overlapping regions between the gate electrode  12   d  and the source  12   b   1  and between the gate electrode  12   d  and the drain  12   b   2  rather than between the gate electrode  12   d  and the semiconductor layer  12   a . Breakdown of the gate insulating film between the gate electrode  12   d  and the semiconductor layer  12   a  may lead to connection with other programmable device, which is also subjected to breakdown of the gate insulating film, via the semiconductor layer (substrate). Avoiding this may require a well region provided to each programmable device in order to separate the programmable device from the other programmable devices, and therefore may require an increase in area. This problem may be overcome if the breakdown occurs in the overlapping regions between the gate electrode  12   d  and the source  12   b   1  and between the gate electrode  12   d  and the drain  12   b   2 . The area of the programmable device  12 , i.e., the area of the programmable logic circuit, and the entire area of the FPGA including such programmable logic circuits may be reduced in this manner. 
       FIG. 3B  shows a second specific example of the programmable device  12 , which is a MOS transistor. This MOS transistor Includes a source  12   b   1  and a drain  12   b   2  that are separated from each other in a semiconductor layer  12   a , a gate insulating film  12   c  disposed on a portion of the semiconductor layer  12   a  between the source  12   b   1  and the drain  12   b   2 , which will serve as a channel  12   b   3 , and a gate electrode  12   d  disposed on the gate insulating film  12   c . The gate insulating film  12   c  and the gate electrode  12   d  overlap at least portion of the source  12   b   1  if viewed from above the gate electrode  12   d . In other words, at least the portion of the source  12   b   1  extend to a portion of the semiconductor layer  12   a  that will serve as the channel  12   b   3  located immediately below the gate insulating film  12   c . The gate electrode  12   d  connects to one of the program line PL and the source line SL, and the source  12   b   1  connects to the other. 
     A conductive path is formed between the source  12   b   1  and the gate electrode  12   d  via the gate insulating film  12   c  in the programmable device  12  if breakdown of the gate insulating film  12   c  is caused by a program voltage Vprg applied between the gate electrode  12   d  and the source  12   b   1 . 
       FIG. 3C  shows a third specific example of the programmable device  12 , which is a MOS transistor. This MOS transistor includes a source  12   b   1  and a drain  12   b   2  that are separated from each other in a semiconductor layer  12   a , a gate insulating film  12   c  disposed on a portion of the semiconductor layer  12   a  between the source  12   b   1  and the drain  12   b   2 , which will serve as a channel  12   b   3 , and a gate electrode  12   d  disposed on the gate insulating film  12   c . The gate insulating film  12   c  and the gate electrode  12   d  overlap at least portion of the drain  12   b   2  if viewed from above the gate electrode  12   d . In other words, at least the portion of the drain  12   b   2  extend to a portion of the semiconductor layer  12   a  that will serve as the channel  12   b   3  located immediately below the gate insulating film  12   c . The gate electrode  12   d  connects to one of the program line PL and the source line SL, and the drain  12   b   2  connects to the other. 
     A conductive path is formed between the drain  12   b   2  and the gate electrode  12   d  via the gate insulating film  12   c  in the programmable device  12  if breakdown of the gate insulating film  12   c  is caused by a program voltage Vprg applied between the gate electrode  12   d  and the drain  12   b   2 . 
     The operations of the cells in the programmable logic circuit according to the first embodiment will be described with reference to  FIGS. 4A to 4C .  FIG. 4A  shows that a program voltage Vprg is applied to the second terminal that is different from the first terminal connecting to the program line PL of the fuse element  16  and a voltage Vss that is lower than the program voltage Vprg is applied to the source line SL in the initial state of the cell  10 . The program voltage Vprg may be applied to the source line SL, and the voltage Vss may be applied to the second terminal of the fuse element  16 . 
     Since the fuse element  16  is conductive in  FIG. 4A , a voltage obtained by subtracting the voltage Vss from the program voltage Vprg (Vprg−Vss) is applied across the programmable device  12 . This voltage (Vprg−Vss) programs the programmable device  12  to make it conductive. 
       FIG. 4B  shows that the programmable device  12 , which is now conductive, serves as a resistor. A current flows in this state since both the fuse element  16  and the programmable device  12  are conductive. The current programs the fuse element  16  to make it nonconductive. 
       FIG. 4C  shows the final state, in which the fuse element  16  is nonconductive, and the programmable device  12  is conductive. The programing operation ends in this state. 
     The fuse element  16  will further be described with reference to  FIGS. 5A to 6B .  FIG. 5A  is a plan view of a first specific example of the fuse element  16 . The first specific example of the fuse element  16  is obtained by narrowing a portion of the wiring line  15 . The narrowed portion  16  increases the current density, causes electromigration to blow out (break) the wiring line  15 , and make the fuse element  16  nonconductive. The wiring line may be formed by metal or poly silicon. 
       FIG. 5B  is a cross-sectional view showing a second specific example of the fuse element  16 . The fuse element  16  according to the second specific example is a via connecting a wiring line  15   a  and a wiring line  15   b . Decreasing the size (diameter) of the via  16  increases the current density in the via  16  to cause electromigration as in the case of the first specific example. This makes the wiring lines  15   a  and  15   b  nonconductive. 
       FIG. 6A  is a plan view showing a third specific example the fuse element  16 . The fuse element  16  according to the third specific example includes a hole  17  that penetrates the wiring line  15  in the thickness direction. The hole  17  decreases the cross-sectional area of the wiring line  15  in a plane perpendicular to the direction along which the wiring line  15  extends. The first specific example of the fuse element  16  shown in  FIG. 5A  also decreases the cross-sectional area of the wiring line  15  in a plane perpendicular to the direction along which the wiring line  15  extends. Instead of decreasing the width of the wiring line as in the first specific example, the thickness of the wiring line  15  may be decreased to form the fuse element  16 . This also decreases the cross-sectional area of the wiring line  15  in a plane perpendicular to the direction along which the wiring line  15  extends to form the fuse element  16 . Advantages similar to those of the third specific example may be obtained by decreasing the cross-sectional area in a plane perpendicular to the direction along which the wiring line  15  extends to form the fuse element  16 . 
       FIG. 6B  is a plan view of a fourth specific example of the fuse element  16 . The fourth specific example of the fuse element  16  may be disposed between a wiring line  15   a  and a wiring line  15   b  and is formed of a material with a lower melting point than a material of the wiring lines  15   a ,  15   b . The width and the thickness of the fuse element  16  may be identical with those of the wiring lines  15   a ,  15   b , or the width or the thickness may be less than that of the wiring lines  15   a ,  15   b . Examples of the low melting point material used to form the fuse element  16  include SnSb, BiSn, SnAg, ZnAl, and InSn. 
     The mean time to failure MTF for the electromigration of the wiring lines can be expressed as follows: 
             MTF   =       AJ     -   n       ⁢     exp   ⁡     (     E   kT     )               
where A and n are constants, J is the current density, E is the activation energy of the fuse element  16 , T is the absolute temperature, and k is the Boltzmann constant. According to this expression, the wiring line width of the first specific example shown in  FIG. 5A , for example, may be changed by (10) 1/n  in order to change the time by one order of magnitude required for electromigration in the wide portion of the wiring line and in the narrow portion. This allows electromigration to be caused more easily in the narrow portion in the wiring line. Although the value of n may vary depending on the respective processes, if the value of n is in a range from 1.5 to 2, for example, electromigration may be caused more easily in a narrow wiring line if the ratio between the width of the fuse element  16  and the width of the wiring line shown in  FIGS. 5A and 5B  is made about 1/4.6 to 1/3.2. Further, narrower width of the fuse element  16  compared with the width of the wiring line  15  may cause the electromigration more easily in the fuse element  16 .
 
     As described above, the fuse element may be formed by narrowing the wiring line or forming a via with a small diameter in the wiring line, and need not be formed in the area of the silicon substrate. This allows a reduction in the area of the programmable logic circuit, and further a reduction of the entire area of the FPGA, unlike the conventional cases where a high voltage transistor is used instead of the fuse element. 
     (Modification) 
       FIG. 7  shows a programmable logic circuit according to a first modification of the first embodiment. The programmable logic circuit according to the first modification includes cells  10   11 - 10   22  arranged in a 2×2 matrix form, program lines PL 1 , PL 2 , source lines SL 1 , SL 2  crossing the program lines PL 1 , PL 2 , fuse elements  16   1 ,  16   2  corresponding to the program lines PL 1 , PL 2 , write circuits  20 ,  22 , and read circuits  30 ,  32 . Each cell  10   ij  (i, j=1, 2) is disposed at an intersection region between a program line PL i  and a source line SL j . The cell  10   ij  (i, j=1, 2) includes a programmable device  12   ij  with a first terminal connecting to the source line SL j  and a second terminal connecting to the program line PL i , and a fuse element  16   i  with a first terminal connecting to one terminal of the program line PL i , and a second terminal connecting to the write circuit  20 . The other terminal of the program line PL i  connects to the read circuit  32 . One terminal of the source line SL i  (i=1, 2) connects to the write circuit  22 , and the other connects to the read circuit  30 . 
       FIG. 8  shows a programmable logic circuit according to a second modification of the first embodiment. The programmable logic circuit according to the second modification includes cells  10   11 - 10   33  arranged in a 3×3 matrix form, program lines PL 1 , PL 2 , PL 3 , source lines SL 1 , SL 2 , SL 3  crossing the program lines PL 1 , PL 2 , PL 3 , fuse elements  16   1 ,  16   2 ,  16   3  corresponding to the program lines PL 1 , PL 2 , PL 3 , write circuits  20 ,  22 , and read circuits  30 ,  32 . Each cell  10   ij  (i, j=1, 2, 3) is disposed at an intersection region between a program line PL i  and a source line SL j . The cell  10   ij  (i, j=1, 2, 3) includes a programmable device  12   ij  with a first terminal connecting to the source line SL j  and a second terminal connecting to the program line PL i , and a fuse element  16   i  with a first terminal connecting to one terminal of the program line PL i , and a second terminal connecting to the write circuit  20 . The other terminal of the program line PL i  connects to the read circuit  32 . One terminal of the source line SL i  (i=1, 2, 3) connects to the write circuit  22 , and the other terminal connects to the read circuit  30 . 
     The programming operations of the first modification and the second modification will be described below. 
     In a programming operation, a voltage Vprg−Vss is applied across the programmable device to be programmed, and a voltage less than Vprg−Vss is applied to the other programmable devices. For example, the programmable device  12   11  of the cell  10   11  in the first modification shown in  FIG. 7  is programmed if the write circuit  20  and the write circuit  22  apply the program voltage Vprg to the program line PL 1 , the voltage Vss to the source line SL 1 , and a write inhibiting voltage Vinh meeting the condition Vprg&gt;Vinh&gt;Vss to the source line SL 2 . The write circuit  20  also applies the write inhibiting voltage Vinh or voltage Vss to the program line PL 2 , or let it to be in a floating state. 
     Since the fuse elements  16   1 ,  16   2  are one-time programmable elements, programming one of the programmable devices connecting to the same program line PL means inhibits the other programmable devices from being programmed. For example, programming the programmable device  12   11  of the cell  10   11  shown in  FIG. 7  inhibits the programmable device  12   12  connecting to the same program line PL 1  from being programmed. This characteristic allows stable programming of only one programmable device connecting to the same program line PL. In FPGAs including source lines SL as input lines and program lines PL as output lines, no signals in different source lines SL are outputted to the same program line PL. Therefore, the programmable logic circuits according to the first modification and the second modification of the first embodiment can be effectively employed in FPGAs. 
     In a read operation, the read circuits  30 ,  32  select one of the cells. The read circuit  30  applies a read voltage Vread to the source line SL connecting to the selected cell, and the read circuit  32  detects whether a current flows through the program line connecting to the selected cell. If this operation is applied to switch blocks and logic blocks of FPGAs, the read voltage Vread acts as a voltage Vdd corresponding to a High level of logic signals, the read circuit  30  serves as an input circuit, and the read circuit  32  serves as an output circuit. This configuration forms a signal switching circuit in which logic signals may pass through only the programmed cell  10   ij . 
     As described above, according to the first embodiment and its modifications, programmable logic circuits and nonvolatile FPGAs can be provided, for which an increase in area can be prevented. 
     Second Embodiment 
       FIG. 9  shows a programmable logic circuit according to a second embodiment. The programmable logic circuit according to the second embodiment is obtained by disposing n-channel MOS transistors  40   1 ,  40   2  between the write circuit  22  and the source line SL 1 , and between the write circuit  22  and the source line SL 2 , respectively, in the programmable logic circuit according to the first modification of the first embodiment shown in  FIG. 7 . Instead of the n-channel MOS transistors  40   1 ,  40   2 , p-channel MOS transistors may be disposed. 
     The programming operations in the programmable logic circuit according to the second embodiment will be described below. 
     In a programming operation, both the transistors  40   1 ,  40   2  are turned ON to apply the same voltages as those applied in the first modification shown in  FIG. 7 . Non-selected source lines SL may be left in a floating state. For example, if the programmable device  12   11  in the cell  10   11  is to be programmed, the transistor  40   1  connecting to the source line SL 1  is turned ON to apply a program voltage Vprg to the program line PL 1 , and a voltage Vss to the source line SL 1 . The transistor  40   2  connected to the non-selected source line SL 2  is turned OFF. As a result, the program voltage Vprg is applied to one terminal of the programmable device  12   12 , but the other terminal is left in a floating state. Therefore, no voltage is applied to the programmable device  12   12  to prevent the programmable device  12   12  from being programmed erroneously. 
     The voltage applied to the gate of the transistor  40   1  to turn it ON is higher than the threshold voltage. This gate voltage has an effect on the resistance value of the programmable device  12   11  after being programmed. For example, if the gate voltage is less than Vprg, the transistor  40   1  after being programmed operates in a saturation state and the current flows therethrough is curbed. As a result, a current with a value similar to that of the current flowing through the transistor  40   1  flows through the programmable device  12   11 , and the programming of the programmable device  12   11  is complete. If the gate voltage is Vprg, the transistor  40   1  after being programmed does not curb the current, and the resistance value of the programmable device  12   11  is lowered. This allows controlling of the resistance value of the programmable device. 
     A write inhibiting voltage Vinh or voltage Vss is applied to the non-selected program line PL 2 , or it is let to be in a floating state. 
     The read operation is performed in a similar manner to that for the first modification according to the first embodiment. 
     The programming operation for the second embodiment does not require application of a plurality of voltage values to the source lines SL. This allows simplification of the circuit configuration. In a FPGA, this circuit may be used to switch signals from the other terminals of the source lines SL to the program lines PL by turning OFF both of the transistors  40   1 ,  40   2 . 
     As described above, the programmable logic circuit and the nonvolatile FPGA according to the second embodiment are capable of suppressing an increase in area, as in the case of the first modification of the first embodiment. 
     Third Embodiment 
       FIG. 10  shows a programmable logic circuit according to a third embodiment. The programmable logic circuit according to the third embodiment is obtained by replacing the write circuit  22  with a write circuit  24  in the programmable logic circuit according to the first modification of the first embodiment shown in  FIG. 7 . 
     The write circuit  24  includes n-channel MOS transistors  24   a   j  and p-channel MOS transistors  24   b   j  each corresponding to one of the source lines SL j  (j=1, 2). The drain of each transistor  24   a   j  (j=1, 2) connects to the corresponding source line SL j , and the source connects to a power supply supplying a voltage Vss. The drain of each transistor  24   b   j  (j=1, 2) connects to the corresponding source line SL j , and the source connects to a power supply supplying a write inhibiting voltage Vinh. 
     The programming operation for the programmable logic circuit according to the third embodiment will be described below. For example, if the programmable device  12   11  is to be programmed, a signal PD 1  with a voltage value to turn ON the transistor  24   a   1  is applied to the gate of the transistor  24   a   1 , a signal PU 1  with a voltage value Vinh to turn OFF the transistor  24   b   1  is applied to the gate of the transistor  24   b   1 , and a program voltage Vprg is applied to the program line PL 1 . As a result, a voltage Vprg-Vss is applied to the programmable device  12   11 . 
     The voltage value of the signal PD 1  is higher than the threshold voltage. This gate voltage has an effect on the resistance value of the programmable device  12   11  after being programmed. For example, if a voltage value of the signal PD 1  is less than Vprg, the transistor  24   a   1  after being programmed operates in a saturation state to curb the current flowing therethrough. As a result, a current with a value similar to that of the current flowing through the transistor  24   a   1  flows through the programmable device  12   11 , and the programming of the transistor  24   a   1  is complete. If the voltage value of the signal PD 1  is the same as the voltage Vprg, the programmable device  12   11  after being programmed does not curb the current, and has a low resistance value. The resistance value of the programmable device can be controlled in this manner. 
     The non-selected source line SL 2  may be left in a floating state if the voltage value of a signal PD 2  to be applied to the gate of the transistor  24   a   2  is the same as the voltage Vss, and the voltage value of a signal PU 2  to be applied to the gate of the transistor  24   b   2  is the same as the voltage Vinh to turn OFF both the transistors. Or, the voltage to be applied to the non-selected source line SL 2  may be write inhibiting voltage Vinh if the voltage value of a signal PD 2  to be applied to the gate of the transistor  24   a   2  is the same as the voltage Vss, and the voltage value of a signal PU 2  to be applied to the gate of the transistor  24   b   2  is the same as the voltage Vss. A write inhibiting voltage Vinh or voltage Vss may be applied to the non-selected program line PL 2 , or the non-selected program line PL 2  may be left in a floating state. 
     The read operation is performed in a similar manner to that for the first modification according to the first embodiment. 
     In a FPGA, this circuit may be used to switch signals from the other terminals of the source lines SL to the program lines PL by setting the voltage values of the signals PD 1 , PU 1 , PD 2 , and PU 2  to turn OFF the transistors. The write inhibiting voltage Vinh is in a range Vprg&gt;Vinh&gt;Vss as described above. If the power supply voltage Vdd for operating the FPGA is used as the voltage Vinh, the number of voltage values is not increased. This may help downsizing the power supply circuit. 
     As described above, the programmable logic circuit and the nonvolatile FPGA according to the third embodiment are capable of suppressing an increase in area, as in the case of the first modification of the first embodiment. 
     Fourth Embodiment 
       FIG. 11  shows a programmable logic circuit according to a fourth embodiment. The programmable logic circuit according to the fourth embodiment is obtained by replacing the write circuit  24  with a write circuit  24 A in the programmable logic circuit according to the third embodiment shown in  FIG. 10 . 
     The write circuit  24 A includes a p-channel transistor  24   c   j  disposed between the source line SL j  (j=1, 2) and the p-channel transistor  24   b   j  (j=1, 2) of the write circuit  24 . The drain of the transistor  24   c   j  (j=1, 2) connects to the source line SL j , and the source thereof connects to the drain of the transistor  24   b   j . The gates of the transistors  24   a   1 ,  24   b   1  are connected to a common terminal SEL 1 , and the gates of the transistors  24   a   2 ,  24   b   2  are connected to a common terminal SEL 2  in the write circuit  24 A. The gates of the transistors  24   c   1 ,  24   c   2  are connected to a common terminal EN. Instead p-channel transistors  24   c   j  (j=1, 2), n-channel transistors may be disposed between the source line SL j  (j=1, 2) and the n-channel transistor  24   a   j  (j=1, 2) of the write circuit  24 . In that case, the voltage Vss for terminal EN should be changed to Vinh or Vprg, and the voltage Vinh or Vprg for the terminal EN should be changed to Vss, in the following description. 
     The programming operation of the fourth embodiment will be described below. For example, if the programmable device  12   11  is to be programmed, a voltage Vss is applied to the terminal EN to turn ON the transistor  24   c   1 , a write inhibiting voltage Vinh or program voltage Vprg is applied to the terminal SEL 1  to turn ON the transistor  24   a   1 , and a voltage Vss is applied to the selected source line SL 1 . A write voltage Vprg is applied to the selected program line PL 1 . This allows a voltage Vprg-Vss to be applied across the selected programmable device  12   11 . 
     A voltage Vss is applied to the terminal SEL 2  to turn ON the transistor  24   b   2 , thereby applying a write inhibiting voltage Vinh to the non-selected source line SL 2 . This allows a voltage Vprg-Vinh to be applied to the non-selected programmable device  12   12 , and thus preventing the programmable device  12   12  from being programmed erroneously. A write inhibiting voltage Vinh or voltage Vss is applied to the non-selected program line PL 2 , or the non-selected program line PL 2  is left to be in a floating state. 
     In a FPGA, this circuit may be used to switch signals from the read circuit  30  to the program lines PL by turning OFF the transistors  24   a   1 ,  24   c   1 ,  24   a   2 ,  24   c   2  to obtain a high impedance by applying the voltage Vss to the terminals SEL 1 , SEL 2 , and a write inhibiting voltage Vinh to the terminal EN. The write inhibiting voltage Vinh is in a range meeting the condition Vprg&gt;Vinh&gt;Vss. If the power supply voltage Vdd for operating the FPGA is used as the write inhibiting voltage Vinh, the number of voltage values need not be increased, and thus the power supply circuit can be downsized. This configuration may increase the number of transistors to be used, but decrease the number of signals to be inputted. Therefore, the area for a considerable number of programmable devices arranged in an array may be reduced. 
     As described above, the programmable logic circuit and the nonvolatile FPGA according to the fourth embodiment are capable of suppressing an increase in area, as in the case of the first modification of the first embodiment. 
     Fifth Embodiment 
       FIG. 12  shows a programmable logic circuit according to a fifth embodiment. The programmable logic circuit according to the fifth embodiment includes inverter circuits  42   1 ,  42   2  disposed between the read circuit  30  and the source line SL 1 , and the read circuit  30  and the source line SL 2 , respectively, in the programmable logic circuit according to the fourth embodiment shown in  FIG. 11 . The inverter circuits  42   1 ,  42   2  may be CMOS inverters or any other inverters. 
     An increase in the size of the array of programmable devices or the number of signal switching circuits connecting to the array may increase the resistance and the capacitance of the programmable device after being programmed. This may lead to degradation of the rising waveform and the falling waveform of logic signals, and increase power consumption. 
     The inverter circuits  42   1 ,  42   2  disposed between the read circuit  30  and the source line SL 1 , and the read circuit  30  and the source line SL 2 , respectively in the fifth embodiment may amplify output signals IN 1 , IN 2  from the read circuit  30  to the source lines SL 1 , SL 2 , and prevent the degradation of the rising waveform and the falling waveform of logic signals to suppress the increase in power consumption. 
     If the program voltage Vprg used to program the programmable device may cause damage to the transistors included in the inverter circuits  42   1 ,  42   2 , protection transistors  43   1 ,  43   2  may be disposed between the outputs of the inverter circuits  42   1 ,  42   2  and the source lines SL 1 , SL 2  as shown in  FIG. 13  to protect the inverter circuits  42   1 ,  42   2 . Further, write circuit  24 A may be considered as CMOS inverter composed of transistor  24   a   j  and  24   b   j  when voltage Vss is applied to the terminal EN. Therefore, the write circuit  24 A is also used as the inverter circuits  42   j  (j=1, 2). The terminals SEL 1  and SEL 2  are also used as the terminals IN 1  and IN 2 . The read circuit  30  includes the function to pull-up and pull-down the terminals IN 1  and IN 2  for programming. In that case, the circuit can be reduced in area since the inverter circuits  42   j  are included in the write circuit  24 A. 
     As described above, the programmable logic circuit and the nonvolatile FPGA according to the fifth embodiment are capable of suppressing an increase in area, as in the case of the first modification of the first embodiment. 
     Sixth Embodiment 
       FIG. 14  shows a programmable logic circuit according to a sixth embodiment. The programmable logic circuit according to the sixth embodiment includes inverter circuits  44   1 ,  44   2  disposed between the read circuit  32  and the program line PL 1 , and the read circuit  32  and the program line PL 2 , respectively, in the programmable logic circuit according to the fourth embodiment shown in  FIG. 11 . The inverter circuits  44   1 ,  44   2  may be CMOS inverters or any other inverters. 
     With such a configuration, the degradation of the rising waveform and the falling waveform of logic signals may be prevented as in the case of the fifth embodiment. 
     If the program voltage Vprg used to program the programmable device may cause damage to the transistors included in the inverter circuits  44   1 ,  44   2 , protection transistors  45   1 ,  45   2  may be disposed between the inputs of the inverter circuits  44   1 ,  44   2  and the program lines PL 1 , PL 2  as shown in  FIG. 15  to protect the inverter circuits  44   1 ,  44   2 . 
     As described above, the programmable logic circuit and the nonvolatile FPGA according to the sixth embodiment are capable of suppressing an increase in area, as in the case of the first modification of the first embodiment. 
     Seventh Embodiment 
       FIG. 16  shows a programmable logic circuit according to a seventh embodiment. The programmable logic circuit according to the seventh embodiment includes inverter circuits  44   1 ,  44   2  disposed between the read circuit  32  and the program line PL 1 , and the read circuit  32  and the program line PL 2 , respectively, in the programmable logic circuit according to the fifth embodiment shown in  FIG. 12 . The inverter circuits  44   1 ,  44   2  may be CMOS inverters or any other inverters. 
     With such a configuration, the degradation of the rising waveform and the falling waveform of logic signals may be prevented as in the case of the fifth embodiment. Since the inverter circuits  42   1 ,  42   2 ,  44   1 ,  44   2  are connected to both the sources lines SL 1 , SL 2  to which signals are inputted and the program lines PL 1 , PL 2  from which signals are outputted, the degrees of the amplification of signals are increased, which causes the programmable logic circuit to operate faster. There is a possibility that the logic may be inverted through the signal switching circuit in the fifth or sixth embodiment shown in  FIG. 12 or 14 , since only one inverter circuit is present in each signal path. The two inverter circuits disposed on each signal path in the six embodiment may prevent the Inversion of logic through the signal switching circuit. 
     If the program voltage Vprg used to program the programmable device may cause damage to the transistors included in the inverter circuits, protection transistors may be disposed between the source lines SL 1 , SL 2  and the inverter circuits  42   1 ,  42   2 , or between the program lines PL 1 , PL 2  and the inverters circuit  44   1 ,  44   2  as shown in  FIG. 13 or 15  to protect the inverter circuits. 
     As described above, the programmable logic circuit and the nonvolatile FPGA according to the seventh embodiment are capable of suppressing an increase in area, as in the case of the first modification of the first embodiment. 
     Eighth Embodiment 
       FIG. 17  shows a programmable logic circuit according to an eighth embodiment. The programmable logic circuit according to the eighth embodiment is obtained by replacing the write circuit  24 A with a write circuit  24 B and adding a dummy wiring line DSL and programmable devices  12   13 ,  12   23  to the programmable logic circuit according to the seventh embodiment shown in  FIG. 16 . Each programmable device  12   i3  (i=1, 2) includes a first terminal connecting to the dummy wiring line DSL, and a second terminal connecting to a corresponding program line PL i . 
     The write circuit  24 B is obtained by adding to the write circuit  24 A shown in  FIG. 16  an n-channel transistor  24   a   3 , a p-channel transistor  24   c   3 , and a p-channel transistor  24   b   3  that are connected in series. The source of the transistor  24   a   3  is connected to a power supply generating a voltage Vss, the drain is connected to one terminal of the dummy wiring line DSL, and the gate is connected to a terminal SEL 3 . The drain of the transistor  24   c   3  is connected to the dummy wiring line DSL, the source is connected to the drain of the transistor  24   b   3 , and the gate is connected to a terminal EN. The source of the transistor  24   b   3  is connected to a power supply generating a write inhibiting voltage Vinh, and the gate is connected to the terminal SEL 3 . The other terminal of the dummy wiring line DSL may or may not be connected to the read circuit  30 . 
     If none of the programmable devices connected to one fuse element is programmed in the seventh embodiment shown in  FIG. 16 , the fuse element is kept electrically conductive. As a result, the write circuit  20  and the read circuit  32  are kept connected to each other while the FPGA is operating. This may cause a malfunction or an increase in power consumption. This may not be a problem if all the fuse elements are to be programmed. If not, this problem may be avoided by the dummy wiring line DSL serving as a source line as in the eighth embodiment shown in  FIG. 17 . 
     If neither the programmable device  12   11  nor the programmable device  12   12  is to be programmed in the eighth embodiment, the programming of the programmable device  12   13  can make the fuse element  16   1  nonconductive. The dummy wiring line DSL is not used as a signal path in an FPGA, and thus does not need to be connected to any element. However, a dummy wiring line DSL being left to be in a floating state may have an intermediate voltage, which may increase the leakage current of the inverter circuits  44   1 ,  44   2 . In order to prevent this, the dummy wiring line DSL may be connected to a constant voltage such as the voltage Vss or the power supply voltage Vdd. For example, while the FPGA is operating, the write inhibiting voltage Vinh may be applied to the terminal SEL 3 , and the voltage VSS may be applied to the dummy wiring line DSL. 
     The programmable logic circuit and the nonvolatile FPGA according to the eighth embodiment are capable of suppressing an increase in area, as in the case of the seventh embodiment. 
     Ninth Embodiment 
     A programmable logic circuit according to a ninth embodiment will be described with reference to  FIG. 18 . The programmable logic circuit according to the ninth embodiment is obtained by employing a programmable device  12 A shown in  FIG. 18  in any of the programmable logic circuits according to the first embodiment to the eighth embodiment. 
     The programmable device  12 A shown in  FIG. 18  is a variable resistance nonvolatile memory including a first electrode  18   a  and a second electrode  18   b , each including one or more layers, and a variable resistance film  19  disposed between the first electrode  18   a  and the second electrode  18   b . The resistance value of the variable resistance film  19  changes to a high resistance, a low resistance, or an intermediate resistance depending on the magnitude, the direction, and the application time of a voltage applied between the second electrode  18   b  and the first electrode  18   a . Generally, a high voltage is applied to a variable resistance film of a resistive change memory to introduce defects (filament) to make it become a variable resistance insulating film. In the voltage Vprg is employed as the initial voltage (forming voltage) of the above operation to introduce defects, the above operation corresponds to the programming operation for the programmable device according to the first embodiment to the eighth embodiment. Therefore, a resistive change memory can be used as the programmable device of the programmable logic circuit according to any of the first to the eighth embodiments. Similarly, if a resistive change memory, the resistance of which may be switched between a high resistance and a low resistance by a current, is used as a fuse element of the programmable device, the fuse element can be programmed to be in a low resistance state if it is used in a programming operation, and a high resistance state if it is used in an FPGA. The resistive change programmable device to be programmed and the resistive change fuse element are arranged so that the high-resistance state and the low-resistance state thereof are opposite to each other. Since the resistive change memory used as the programmable device or fuse element becomes a nonvolatile memory after defects are introduced thereto, the FPGA can be rewritten repeatedly. 
     The programmable logic circuit and the nonvolatile FPGA according to the ninth embodiment are capable of suppressing an increase in area, as in the case of the first to the eighth embodiments. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the Inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.