Patent Publication Number: US-7589703-B2

Title: Liquid crystal display with sub-pixel structure

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to a liquid crystal display and, more particularly, to driving the sub-pixels in the liquid crystal display. 
     BACKGROUND OF THE INVENTION 
     As known in the art, a color liquid crystal display (LCD) panel  1  has a two-dimensional array of pixels  10 , as shown in  FIG. 1 . Each of the pixels comprises a plurality of sub-pixels, usually in three primary colors of red (R), green (G) and blue (B). These RGB color components can be achieved by using respective color filters.  FIG. 2  illustrates a plan view of the pixel structure in a conventional transmissive LCD panel. As shown in  FIG. 2 , a pixel can be divided into three sub-pixels  12 R,  12 G and  12 B. The structure of a typical transmissive LCD sub-pixel is shown in  FIG. 3 . As shown, the LCD sub-pixel comprises a color filter  42  and an ITO electrode  44  disposed on an upper substrate  40 . In the lower section of the LCD sub-pixel, a lower transmissive electrode  64 , a passivation layer  65  and a device layer  62  are disposed on a lower substrate  60 . The sub-pixel  12  further comprises a liquid crystal layer  50  disposed between the upper and lower electrodes. The upper electrode is typically connected to a common line where the voltage is denoted by Vcom (see  FIG. 5 ). As shown in  FIG. 4 , the lower electrode is electrically connected to a data line m through a switching element or thin-film transistor (TFT), which is turned on by a signal on the gate line n−1. The equivalent circuit of the sub-pixel  12  is shown in  FIG. 5 . Typically, the sub-pixel  12  is associated with a number of capacitors. C LC  is the charge capacitance of the liquid crystal layer in the sub-pixel; C ST  is a charge storage capacitor fabricated in the sub-pixel in order to maintain the voltage potential between the upper and lower electrodes after the gate line signal has passed; and C gs  is the gate-source capacitance, which is related to one of the capacitors associated with the TFT and the passivation layer (not shown) in the sub-pixel. When the gate line signal is “on”, it drives the TFT to charge up these capacitors so that the voltage level (or V PIXEL ) on the transmissive electrode  64  (see  FIGS. 3 and 4 ) is substantially equal to the signal on data line m, at least before the gate line signal has passed. Depending on the design of the LCD sub-pixel, V PIXEL  is typically reduced by an amount known as the feed-through voltage drop. In a conventional LCD panel such as a Multi-domain Vertical Alignment (MVA) panel, the color of the display varies significantly with the view angles due to the changes in the gamma curve. 
     It is thus desirable and advantageous to provide a method and pixel structure for reducing the effect of viewing angles on the color of a LCD panel. 
     SUMMARY OF THE INVENTION 
     A transmissive liquid-crystal display has a pixel structure wherein each pixel is divided into at least a first region and a second region, each region having a pair of electrodes. The electrode pair in the first region comprises a first electrode connected to a gate line via a TFT and a second electrode connected to a first voltage via a first common line. The electrode pair in the second region comprises a first electrode connected to the same gate line via another TFT, and a second electrode connected to a second voltage via a second common line. Each of the first and second voltages has a common signal and a different signal. The different signals are periodical and in a “swing’ fashion. These signals are in-sync with each other but with a different polarity. Each region also has a storage capacitor connected to a third common line connected to a third voltage, which is substantially equal to the average of the first and second voltages. 
     Alternatively, each pixel has a first capacitor operatively connected between the first electrode in the first region and the first common line, and a second capacitor operatively connected between the first electrode in the second region and the second common line. 
     In another embodiment, a pixel also has a third region. The third region has a third electrode pair. The third electrode pair comprises a first electrode connected to the same gate line via a different TFT, and a second electrode connected to a third voltage via a third common line, wherein the third voltage is substantially equal to the average of the first and second voltages. Each of the regions has a storage capacitor connected in parallel to the respective electrode pair. 
     The present invention will become apparent upon reading the description taken in conjunction with  FIGS. 6 to 19   c.    
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic representation showing a typical LCD panel. 
         FIG. 2  is a schematic representation showing a plan view of the pixel structure in a typical LCD panel. 
         FIG. 3  is a schematic representation showing a cross sectional view of the sub-pixel. 
         FIG. 4  is a schematic representation showing the electrical connections on the lower electrode in a prior art sub-pixel. 
         FIG. 5  is an equivalent circuit of the prior art sub-pixel as shown in  FIG. 4 . 
         FIG. 6  is a schematic representation showing the electrical connections on the lower electrode in a sub-pixel, according to the present invention. 
         FIG. 7   a  shows a masking layer disposed on a color sub-pixel, according to the present invention. 
         FIG. 7   b  shows a color filter disposed on a color sub-pixel, according to the present invention. 
         FIG. 7   c  shows a pair of upper electrodes disposed on a color sub-pixel, according to the present invention. 
         FIG. 8  is a schematic representation showing a cross sectional view of a color sub-pixel, according to the present invention. 
         FIG. 9  is an equivalent circuit of a sub-pixel, according to the present invention. 
         FIGS. 10   a - 10   h  show a timing chart with various signals associated with a sub-pixel, according to the present invention, wherein: 
         FIG. 10   a  shows the signal on gate line n−1; 
         FIG. 10   b  shows the signal on gate line n; 
         FIG. 10   c  shows the signal on gate line n+1; 
         FIG. 10   d  shows the signal on common line  1 ; 
         FIG. 10   e  shows the signal on common line  2 ; 
         FIG. 10   f  shows the signal on data line m; 
         FIG. 10   g  shows the signal V PIXEL1 , and 
         FIG. 10   h  shows the signal V PIXEL2 . 
         FIG. 11  is an equivalent circuit of a sub-pixel, according to another embodiment of the present invention. 
         FIG. 12  is a schematic representation showing a cross sectional view of a color sub-pixel, according to a different embodiment of the present invention. 
         FIG. 13  is an equivalent circuit of the sub-pixel as shown in  FIG. 11 . 
         FIGS. 14   a - 14   j  show a timing chart with various signals associated with a sub-pixel as shown in  FIG. 13 , wherein: 
         FIG. 14   a  shows the signal on gate line n−1; 
         FIG. 14   b  shows the signal on gate line n; 
         FIG. 14   c  shows the signal on gate line n+1; 
         FIG. 14   d  shows the signal on common line  1 ; 
         FIG. 14   e  shows the signal on common line  2 ; 
         FIG. 14   f  shows the signal on common line  3 ; 
         FIG. 14   g  shows the signal on data line in; 
         FIG. 14   h  shows the signal V PIXEL1 ; 
         FIG. 14   i  shows the signal V PIXEL2 ; and 
         FIG. 14   j  shows the signal V PIXEL3 . 
         FIG. 15  is a schematic representation showing a cross sectional view of a color sub-pixel, according to another embodiment of the present invention. 
         FIGS. 16   a - 16   h  show a timing chart with various signals associated with a sub-pixel, according to another embodiment of the present invention, wherein: 
         FIG. 16   a  shows the signal on gate line n−1; 
         FIG. 16   b  shows the signal on gate line n; 
         FIG. 16   c  shows the signal on gate line n+1; 
         FIG. 16   d  shows the signal on common line  1 ; 
         FIG. 16   e  shows the signal on common line  2 ; 
         FIG. 16   f  shows the signal on data line in; 
         FIG. 16   g  shows the signal V PIXEL1 , and 
         FIG. 16   h  shows the signal V PIXEL2 . 
         FIGS. 17   a - 17   e  show the relationship between the signals V PIXEL1  and V PIXEL2  and the Vcom swing; wherein 
         FIG. 17   a  shows an example of a constant Vcom signal; 
         FIG. 17   b  shows an example of Vcom signal of common line  1 ; 
         FIG. 17   c  shows an example of Vcom signal of common line  2 ; 
         FIG. 17   d  shows an example of V PIXEL1  in two-frame time; and 
         FIG. 17   e  shows an example of V PIXEL2  in two-frame time. 
         FIG. 18   a  shows a representation of pixel in a positive frame, according to the present invention. 
         FIG. 18   b  shows a representation of pixel in a negative frame. 
         FIG. 19   a  is a schematic representation of dot inversion. 
         FIG. 19   b  is a schematic representation of two-line inversion. 
         FIG. 19   c  is a schematic representation of column inversion. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In an LCD panel of the present invention, a color sub-pixel is further divided into two or more regions. As shown in  FIG. 6 , a color sub-pixel  120  is divided into two sub-regions  121 ,  122 , for example. Each of the sub-regions has a lower electrode. As shown in  FIG. 6 , region  121  has a lower electrode  161  electrically connected to Data line m through a switching element TFT 1 . Region  122  has a lower electrode  162  electrically connected to Data line m through another switching element TFT 2 . Both TFT 1  and TFT 2  are activated or turned on by the signal on Gate line n−1. Furthermore, the sub-pixel  120  is associated with two common lines: common  1  and common  2  for separately providing a voltage level to the upper electrodes  141 ,  142  (see  FIG. 8 ). Optionally, the sub-pixel is also associated to another common line  3 . In order to improve the viewing quality of the LCD panel, each color sub-pixel has a mask  170  made of an opaque material, as shown in  FIG. 7   a . Furthermore, the sub-pixel has a color filter  172  as shown in  FIG. 7   b . In contrast to the prior art LCD panel, the sub-pixel has two upper electrodes  141 ,  142  as shown in  FIG. 7   c . These electrodes are separately connected to common line  1  and common line  2 . As shown in  FIG. 8 , the mask  170  can be disposed on the upper substrate  140 . The color filter  172  and the electrodes  141 ,  142  can be disposed on the mask  170 . In the lower part of the color sub-pixel  120 , the lower electrodes  161 ,  162 , a passivation layer  165  and a device layer  164  can be disposed on a lower substrate  160 . 
     Furthermore, sub-region  121  is associated with a charge storage capacitor C ST1  and other capacitors (C gs1  for example). Likewise, sub-region  122  is associated with a charge storage capacitor C ST2  and other capacitors (C gs2  for example). Both the charge storage capacitors C ST1 , C ST2  are connected to a common voltage Vcom (common  3  in  FIG. 6 ) which has a constant voltage level. As shown in  FIG. 9 , the upper electrode  141  is electrically connected to Common  1  and the upper electrode  142  is electrically connected to Common  2 . 
     The signals at various gate, data and common lines are shown in  FIGS. 10   a - 10   h .  FIG. 10   a  shows the signal on gate line n−1;  FIG. 10   b  shows the signal on gate line n; and  FIG. 10   c  shows the signal on gate line n+1. The sub-pixel  120  depicted in  FIG. 9  is driven by gate line n−1.  FIGS. 10   d  and  10   e  show the signal on common line  1  and common line  2 . As shown, the signals on the common lines are periodical in a “swing” fashion. The signals are in-sync with each other but with different polarity.  FIG. 10   f  shows the signal on Data line m. As shown, the signal level on the data line may have different values, but only the signal level V_signal during Gate line n−1 determines the voltage potential on the electrodes in sub-region  121  and the electrodes in sub-region  122 . The applied voltage V PIXEL1  on electrode  161  in sub-region  121  is shown in  FIG. 10   g . The applied voltage V PIXEL2  on electrode  162  in sub-region  122  is shown in  FIG. 10   h.    
     The one frame time root-mean squared voltage potential V PIXEL1  between electrodes  161  and  141  in sub region  121  and the one frame time root-mean squared voltage potential V PIXEL2  between electrodes  161  and  141  in sub region  121  are given by:
 
 V   PIXEL1     —     RMS   =V _signal+(Δ Vcom/ 2)×( C   LC1 /( C   LC1   +C   ST1   +C   others ))  (1)
 
 V   PIXEL2     —     RMS   =V _signal−(Δ Vcom/ 2)×( C   LC2 /( C   LC2   +C   ST2   +C   others ))  (2)
 
     where C others  include C gs  and capacitance associated with the switching element and the passivation layers in the sub-region. 
     In another embodiment of the present invention, both C LC  and C ST  in the same sub-region are connected to the same common line. As shown in  FIG. 11 , C LC1  and C ST1  in sub-region  121  are connected to common line  1  and C LC2  and C ST2  in sub-region  122  are connected to common line  2 . The voltage potential V PIXEL1  and the voltage potential V PIXEL2  are given by:
 
 V   PIXEL1   −V _signal+Δ Vcom ×( C   LC1   +C   ST1 )/( C   LC1   +C   ST1   +C   others )  (4)
 
 V   PIXEL2   =V _signal−Δ Vcom ×( C   LC2   +C   ST2 )/( C   LC2   +C   ST2   +C   other )  (5)
 
and the rms (root-mean squared) value of the second term in the above equations is
 
(ΔVcom/2)×(C LC +C ST )/(C LC +C ST +C others )  (6)
 
Because of the inclusion of the charge storage capacitance term in the equations, the coupling voltage on common line  1  and common line  2  is less sensitive to the C LC  value. This allows a higher fabrication margin in the making of the LCD panel. At the same time, the magnitude of ΔVcom can be reduced.
 
     A color sub-pixel can also be divided into three sub-regions. As shown in  FIG. 12 , the sub-pixel  120 ′ has three sub-regions  121 ,  122  and  123  defined by the upper electrodes  141 ,  142 ,  143  and the lower electrodes  161 ,  162 ,  163 . For example, the upper electrodes  141 ,  142  and  143  can be electrically connected to common line  1 , common line  3  and common line  2 , respectively. Likewise, the charge storage capacitors C ST1 , C ST2  and C ST3  are separately connected to common line  1 , common line  3  and common line  2 , respectively, as shown in  FIG. 13 . Accordingly, the voltage potentials V PIXEL1  V PIXEL2  and V PIXEL3  are given by:
 
 V   PIXEL1   =V _signal+Δ Vcom ×( C   LC1   +C   ST1 )/( C   LC1   +C   ST1   +C   others )  (7)
 
V PIXEL2 =V_signal  (8)
 
 V   PIXEL3   =V _signal−Δ Vcom ×( C   LC3   +C   ST3 )/( C   LC3   +C   ST3   +C   others )  (9)
 
and the rms value of the second term in the Equations 7 and 9 is
 
(ΔVcom/2)×(C LC +C ST )/(C LC +C ST +C others )  (10)
 
     The signals at various gate, data and common lines are shown in  FIGS. 14   a - 14   j .  FIG. 14   a  shows the signal on gate line n−1;  FIG. 14   b  shows the signal on gate line n; and  FIG. 14   c  shows the signal on gate line n+1.  FIG. 14   d  shows the signal on common line  1  applied to upper electrode  141  and the charge storage capacitor C ST1 .  FIG. 14   e  shows the signal on common line  2  applied to upper electrode  143  and the charge storage capacitor C ST3 .  FIG. 14   f  shows the signal on common line  3  applied to upper electrode  142  and the charge storage capacitor C ST2 . As shown, the signals on the common lines  1  and  2  have two voltage levels in an alternate form. The signal on common line  3  is a constant voltage.  FIG. 14   g  shows the signal on Data line m. The applied voltage V PIXEL1  on electrode  161  in sub-region  121  is shown in  FIG. 14   h . The applied voltage V PIXEL2  on electrode  162  in sub-region  122  is shown in  FIG. 14   i . The applied voltage V PIXEL3  on electrodes  163  in sub-region  123  is shown in  FIG. 14   j.    
     In another embodiment of the present invention, the color sub-pixel is also divided into three sub-regions  121 ,  122  and  123  as shown in  FIG. 15 . The sub-regions  121 ,  122  and  123  are defined by the lower electrodes  161 ,  162  and  163 . However, there are only two upper electrodes  141  and  142 . There are four charge storage capacitors associated with the sub-pixel  120 ″. C ST1  is associated with the lower electrode  161 . C ST1-2  is associated with the lower electrode  162 . C ST2-3  is associated with the lower electrode  162 . C ST3  is associated with the lower electrode  163 . If both C ST1  and C ST1-2  are connected to common line  1  and both C ST2-3  and C ST3  are connected to common line  2 , the voltage potentials V PIXEL1  V PIXEL2  and V PIXEL3  associated with sub-regions  121 ,  122  and  123  are given by:
 
 V   PIXEL1   =V _signal+Δ Vcom ×( C   LC1   +C   ST1 )/( C   LC1   +C   ST1   +C   others )  (11)
 
 V   PIXEL2   V _signal+Δ Vcom [( C   LC12   +C   ST1-2 )−( C   LC23   +C   ST2-3 )]/( C   LC12   +C   ST1-2   +C   LC23   +C   ST2-3   +C   others )]  (12)
 
 V   PIXEL3   =V _signal−Δ Vcom ×( C   LC3   +C   ST3 )/( C   LC3   +C   ST3   +C   others )  (13)
 
In Equation 12, C LC12  and C LC23  are the capacitance associated with the liquid crystal layer in the sub-region  122 . If the design of the sub-regions is such that C LC12 =C LC23 , and C ST1-2 =C ST2-3 , Equation 12 is reduced to
 
V PIXEL2 =V_signal  (12′)
 
The rms value of the second term in the Equations 11 and 13 is
 
(ΔVcom/2)×(C LC +C ST )/(C LC +C ST +C others )  (14)
 
     It should be noted that, in the embodiment as shown in  FIG. 15 , the driving waveforms on the three sub-regions are substantially the same as the driving waveforms associated with the embodiment of  FIG. 12 . The added advantage of the embodiment of  FIG. 15  is that that only two common lines, common  1  and common  2 , are used. As with the lower electrode  162  in  FIG. 12 , the lower electrode  162  in  FIG. 15  is also connected to the data line via a switching device TFT 2  driven by a gate line signal (see  FIG. 13 ). 
     In  FIGS. 10 and 14 , the signal levels on common lines  1  and  2  change in a swing cycle or period equal to every two gate line signals. It is also possible to double or triple the swing period. As shown in  FIG. 16 , the period is doubled such that the swing cycle is equal to four gate line signals.  FIG. 16   a  shows the signal on gate line n−1;  FIG. 16   b  shows the signal on gate line n; and  FIG. 16   c  shows the signal on gate line n+1.  FIGS. 16   d  and  16   e  show the signal on common line  1  and common line  2 .  FIG. 16   f  shows the signal on Data line m. The applied voltage V PIXEL1  on electrode  161  in sub-region  121  (see  FIG. 8 ) is shown in  FIG. 16   g . The applied voltage V PIXEL2  on electrode  162  in sub-region  122  is shown in  FIG. 16   h.    
     In sum, in an LCD panel of the present invention, a sub-pixel is divided into at least two sub-regions. Each of the sub-regions has a separate electrode pair so that the voltage potential across the liquid crystal layer in one sub-region is different from the voltage potential in the other sub-region. In particular, when each sub-region has a separate upper electrode and a separate lower electrode, the lower electrodes in both sub-regions are connected to the same data line while the upper electrodes in the sub-regions are connected to different common lines. Furthermore, each of the sub-regions has a separate charge storage capacitor. The charge storage capacitors in the sub-regions can be connected to the respective common lines or a different common line. The signals on common line  1  and common line  2  have the same swing waveform alternating between two signal levels, but the polarities are different. As such, when the brightness in one sub-region is reduced, the brightness in the other sub-region is increased. 
     When suitable swing voltage waveforms in positive frames and negative frames are separately provided to the sub-regions in the pixels in LCD panel, different pixel inversion effects can be achieved.  FIGS. 17   d  and  17   e  show exemplary waveforms separately provided to sub-region  121  and sub-region  122  of a color sub-pixel  120 . The waveform as shown in  FIG. 17   d  is similar to the waveform of  FIG. 16   h  but it is extended to two-frame time. Likewise, the waveform as shown in  FIG. 17   e  is similar to the waveform of  FIG. 16   g  but it is extended to two-frame time. If the constant Vcom signal is 5.5V as shown in  FIG. 17   a , then Vcom 1 , or the swing voltage for sub-region  121  and Vcom 2 , or the swing voltage for sub-regions  122 , are 5.5V plus or minus ΔVcom, as shown in  FIGS. 17   b  and  17   c . Vcom 1  and Vcom 2  signals are only different in polarity. If V_signal is 6V in a positive frame and −6V in a negative frame, then V PIXEL1  alternates between (11.5V+2 ΔVcom×coupling ratio) and 11.5V, V PIXEL2  alternates between 11.5V and (11.5V−2 ΔVcom×coupling ratio) in a positive frame, V PIXEL1  alternates between 0.5V and (0.5V−2 ΔVcom×coupling ratio), and V PIXEL2  alternates between (0.5V+2 ΔVcom×coupling ratio) and 0.5V in a negative frame. Here the coupling ratio (CR) is C LC1 /(C LC1 +C ST +C others ) for sub-region  121  and C LC2 /(C LC2 +C ST +C others ) for sub-region  122 . 
       FIGS. 18   a  and  18   b  are schematic representations of a pixel in a positive frame and a pixel in a negative frame. The upward pointing arrow indicates a pulled-up V_signal in a sub-region  121  and the downward pointing arrow indicates a pulled-down V_signal in the sub-region  122  of each of the color pixels R, G and B. The letter H indicates the sub-region being brighter because the applied voltage is higher. Likewise, the letter L indicates the sub-region being darker because the applied voltage is lower. 
     It is possible to apply the waveforms V PIXEL1  and V PIXEL2  on the pixels on an LCD panel to achieve a dot inversion scheme, as shown in  FIG. 19   a . It is also possible to use similar waveforms to achieve a two-line inversion scheme and a row inversion scheme, as shown in  FIGS. 19   b  and  19   c.    
     Thus, by dividing a color sub-pixel into two sub-regions, with each sub-region having a separate switching element TFT and storage capacitor, it is possible to achieve different pixel inversion schemes using swing voltages in complementary polarities. 
     It should be noted that the present invention has been disclosed in conjunction with a transmissive LCD panel. However, the present invention is also applicable to a transflective LCD panel as well as a reflective LCD panel. 
     Thus, although the invention has been described with respect to one or more embodiments thereof, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.