Patent Publication Number: US-10770133-B1

Title: Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits

Description:
PRIORITY CLAIM/RELATED APPLICATIONS 
     This application is a continuation in part of and claims priority under 35 USC 120 to U.S. patent application Ser. No. 15/709,399, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations”, U.S. patent application Ser. No. 15/709,401, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations”, U.S. patent application Ser. No. 15/709,379, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, U.S. patent application Ser. No. 15/709,382, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, and U.S. patent application Ser. No. 15/709,385, filed Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells” that in turn claim priority under 35 USC 119(e) and 120 and claim the benefit of U.S. Provisional Patent Application No. 62/430,767, filed Dec. 6, 2016 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations” and U.S. Provisional Patent Application No. 62/430,762, filed Dec. 6, 2016 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells”, the entirety of all of which are incorporated herein by reference. 
    
    
     FIELD 
     The disclosure relates generally to a computational memory element and in particular to a computational memory element array having a write inhibit ability that can save power. 
     BACKGROUND 
     Memory cells have traditionally been used to store bits of data. It is also possible to architect a memory cell so that the memory cell is able to perform some simple logical functions when multiple memory cells are connected to the same read bit line. For example, when memory cells A, B, and C are connected to a particular read bit line and are read simultaneously, and the memory cells and read bit line circuitry are designed to produce a logical AND result, then the result that appears on the read bit line is AND (a, b, c) (i.e. “a AND b AND c”), where a, b, and c represent the binary data values stored in memory cells A, B, and C respectively. More particularly, in these computational memory cells, the read bit line is pre-charged to a logic “1” before each read operation, and the activation of one or more read enable signals to one or more memory cells discharges the read bit line to a logic “0” if the data stored in any one or more of those memory cells=“0”; otherwise, the read bit line remains a logic “1” (i.e. in its pre-charge state). In this way, the read bit line result is the logical AND of the data stored in those memory cells. 
     Some computational algorithms (e.g. searches) are performed such that, as the algorithm proceeds, various portions of the computational memory cell array are identified as containing data that is irrelevant to the final result. Since pre-charging the read bit line in a portion of the computational memory cell array consumes power, it is desirable to be able to temporarily inhibit the pre-charge in these “irrelevant” portions of the computational memory cell array, from the time they are identified as such until the algorithm completes, to save power during that time. It is also desirable to be able to inhibit writes to the memory cells in such “irrelevant” portions of the computational memory cell array, for the same reason. 
     Furthermore, it is also desirable to be able to inhibit writes to the memory cells in selective portions of the computational memory cell array on a per-write-operation basis, not to save power, but rather to enhance the computational capability of the computational memory cell array. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an example of a semiconductor memory that may include a plurality of computation memory cells and write inhibit circuitry; 
         FIG. 2  illustrates an example of a computer system that may include a plurality of computation memory cells and write inhibit circuitry; 
         FIG. 3A  illustrates an example of a processing array with computational memory cells that may be incorporated into a semiconductor memory or computer system; 
         FIG. 3B  illustrates the processing array with computational memory cells having one section and multiple bit line sections; 
         FIG. 3C  illustrates the processing array with computational memory cells having multiple sections and multiple bit line sections; 
         FIGS. 4A and 4B  illustrate examples of two different types of computational memory cells that may be used in the semiconductor memory of  FIG. 1 , the computer system of  FIG. 2  or the processing array of  FIGS. 3A-3C ; 
         FIG. 5  illustrates read/write logic including read logic, read data storage, and write logic associated with each bit line section in the processing array device depicted in  FIG. 3C ; 
         FIG. 6  illustrates the read and write control circuitry in a single bit line section from  FIGS. 3B and 3C  that can be used when the act of reading multiple memory cells on a read bit line produces a logical AND of the data stored in those memory cells; 
         FIG. 7  illustrates a first embodiment of the read and write control circuitry in a single bit line section from  FIGS. 3B and 3C  that includes a write inhibit capability for memory cells in selective bit line sections on a per-write-operation basis; 
         FIG. 8  illustrates a second embodiment of the read and write control circuitry in a single bit line section from  FIGS. 3B and 3C  that has additional circuitry, including write logic circuitry, that can be used to inhibit the read bit line pre-charge in selective bit line sections and to inhibit writes to the memory cells in selective bit line sections for an extended period of time; and 
         FIG. 9  illustrates a third embodiment of read and write control circuitry in a single bit line section from  FIGS. 3B and 3C  that combines the circuitry in  FIGS. 7-8 . 
     
    
    
     DETAILED DESCRIPTION OF ONE OR MORE EMBODIMENTS 
     The disclosure is particularly applicable to a processing array, semiconductor memory or computer that utilizes a plurality of computational memory cells (with each cell being formed with a static random access memory (SRAM) cell) and additional circuitry to provide a write inhibit capability that can: 1) temporarily inhibit the read bit line pre-charge in “irrelevant” portions of the computational memory cell array to save power when the processing array is performing a process such as a search process; 2) temporarily inhibit writes to “irrelevant” portions of the computational memory cells array to save power when the processing array is performing a process such as a search process; or 3) inhibit writes to the computational memory cells in selective portions of the computational memory cell array on a per-write-operation basis to enhance the computational capability of the computational memory cell array. It will be appreciated, however, that each computational memory cell may be other types of volatile and non-volatile memory cell that are within the scope of the disclosure, that other additional circuitry (including more, less or different logic) may be used and are within the scope of the disclosure or that different computational memory cell architectures that those disclosed below are within the scope of the disclosure. 
     The disclosure is directed to a memory/processing array that has a plurality of computing memory cells in an array with additional circuitry for write inhibits in selective bit line sections on per-write operation basis to enhance the computational capability of the bit line sections. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bit line sections for an extended period of time, to save power. Each computing memory cell in a column in the array may have a read bit line and the read bit line for each of the computing memory cells in the column may be tied together as a single read bit line. The memory/processing array may be subdivided into one or more sections (an example of which is shown in  FIGS. 3B and 3C ) wherein each section has a unique set of “n” bit lines (each bit line being part of a bit line section) where each bit line section (bl-sect) comprises a single read bit line and a pair of positive and negative write bit lines, with each bit line connected to “m” computational memory cells. Each bit line section also may have a read data storage that is used to capture and store the read result from the read bit line during read operations (so a read data storage is implemented per read bit line) and read circuitry for routing the read data or the selected write data for performing logical operations. In the disclosure, BL-Sect[x,y] is a shorthand notation indicating a bit line section with bit line “y” in section “x” and “bl-sect” means bit line section. 
       FIG. 1  illustrates an example of a semiconductor memory  10  that may include a plurality of computation memory cells and circuitry that provides a write inhibit capability that are described below in more detail. The below disclosed plurality of computation memory cells and write inhibit circuitry allow the semiconductor memory  10  to save power and operate more efficiently than are possible with just the plurality of computation memory cells.  FIG. 2  illustrates an example of a computer system  20  that may include a plurality of computation memory cells and the write inhibit circuitry that are described below in more detail. The below disclosed plurality of computation memory cells and write inhibit circuitry allow the semiconductor memory  10  or computer system  20  and memory  24  to save power and operate more efficiently than are possible with just the plurality of computation memory cells. The computer system  20  in  FIG. 2  may have at least one processor  22  and a memory  24  that may include the plurality of computation memory cells and read circuitry for selecting read or write data. 
       FIG. 3A  illustrates an example of a processing array  30  with computational memory cells in an array that may be incorporated into a semiconductor memory or computer system and may include the write inhibit circuitry. The processing array  30  may include an array of computational memory cells (cell  00 , . . . , cell  0   n  and cell m 0 , . . . , cell mn). In one embodiment, the array of computational memory cells may be rectangular as shown in  FIG. 3A  and may have a plurality of columns and a plurality of rows wherein the computational memory cells in a particular column may also be connected to the same read bit line (RBL 0 , . . . , RBLn). The processing array  30  may further include a wordline (WL) generator and read/write logic control circuit  32  that may be connected to and generate signals for the read word line (RE) and write word line (WE) for each memory cell (such as RE 0 , . . . , REn and WE 0 , . . . , WEn) to control the read and write operations is well known and one or more read/write circuitry  34  that are connected to the read and write bit lines of the computational memory cells. In the embodiment shown in  FIG. 3A , the processing array may have read/write circuitry  34  for each set of bit line signals of the computational memory cells (e.g., for each column of the computational memory cells whose read bit lines are connected to each other). For example, BL 0  read/write logic  340  may be coupled to the read and write bit lines (WBLb 0 , WBL 0  and RBL 0 ) for the computational memory cells in column  0  of the array and BLn read/write logic  34   n  may be coupled to the read and write bit lines (WBLbn, WBLn and RBLn) for the computational memory cells in column n of the array as shown in  FIG. 3A . 
     The wordline (WL) generator and read/write logic control circuit  32  may also generate one or more control signals that control each read/write circuitry  34 . For example, for the different embodiments of the read/write logic described in the co-pending U.S. patent application Ser. No. 16/111,178, filed on Aug. 23, 2018 and incorporated herein by reference, the one or more control signals may include a Read_Done control signal, an XORacc_En control signal, an ANDacc_En control signal and an ORacc_En control signal whose operation and details are described in the above incorporated by reference application. Note that for each different embodiment, a different one or more of the control signals is used so that the wordline (WL) generator and read/write logic control circuit  32  may generate different control signals for each embodiment or the wordline (WL) generator and read/write logic control circuit  32  may generate each of the control signals, but then only certain of the control signals or all of the control signals may be utilized as described in the above incorporated by reference co-pending patent application. 
     During a read operation, the wordline (WL) generator and read/write logic control circuit  32  may activate one or more word lines that activate one or more computational memory cells so that the read bit lines of those one or more computational memory cells may be read out. Further details of the read operation are not provided here since the read operation is well known. 
       FIGS. 3B and 3C  illustrate the processing array  30  with computational memory cells having sections having the same elements as shown in  FIG. 3A . The array  30  in  FIG. 3B  has one section (Section 0) with “n” bit lines (bit line  0  (BL 0 ), . . . , bit line n (BLn)) in different bit line sections (bl-sect), where each bit line connects to “m” computational memory cells (cell  00 , . . . , cell m 0  for bit line  0 , for example). In the example in  FIG. 3B , the m cells may be the plurality of computational memory cells that are part of each column of the array  30 .  FIG. 3C  illustrates the processing array  30  with computational memory cells having multiple sections. In the example in  FIG. 3C , the processing array device  30  comprises “k” sections with “n” bit lines each, where each bit line within each section connects to “m” computational memory cells. Note that the other elements of the processing array  30  are present in  FIG. 3C , but not shown for clarity. In  FIG. 3C , the BL-Sect(0,0) block shown corresponds to the BL-Sect(0,0) shown in  FIG. 3B  with the plurality of computational memory cells and the read/write logic  340  and each other block shown in  FIG. 3C  corresponds to a separate portion of the processing array. As shown in  FIG. 3C , the set of control signals, generated by the wordline generator and read/write logic controller  32 , for each section may include one or more read enable control signals (for example S[0]_RE[m:0] for section 0), one or more write enable control signals (for example S[0]_WE[m:0] for section 0) and one or more read/write control signals (for example S[0]_RW_Ctrl[p:0] for section 0). As shown in  FIG. 3C , the array  30  may have a plurality of sections (0, . . . , k in the example in  FIG. 3C ) and each section may have multiple bit line sections (0, . . . , n per section, in the example in  FIG. 3C ). 
       FIGS. 4A and 4B  illustrate examples of two different types of computational memory cells that may be used in the semiconductor memory of  FIG. 1 , the computer system of  FIG. 2  or the processing array of  FIGS. 3A-C . In the examples, the computational memory cell are based on an SRAM memory cell. 
       FIG. 4A  illustrates an example of a dual port SRAM cell  20  that may be used for computation. The dual port SRAM cell may include two cross coupled inverters  121 ,  122  and two access transistors M 23  and M 24  that interconnected together to form a 6 T SRAM cell. The SRAM may be operated as storage latch and may have a write port. The two inverters are cross coupled since the input of the first inverter is connected to the output of the second inverter and the output of the first inverter is coupled to the input of the second inverter as shown in  FIG. 4A . A Write Word line carries a signal and is called WE and a write bit line and its complement are called WBL and WBLb, respectively. The Write word line WE is coupled to the gates of the two access transistors M 23 , M 24  that are part of the SRAM cell. The write bit line and its complement (WBL and WBLb) are each coupled to one side of the respective access transistors M 23 , M 24  as shown in  FIG. 4A  while the other side of each of those access transistors M 23 , M 24  are coupled to each side of the cross coupled inverters (labeled D and Db in  FIG. 4A .) 
     The circuit in  FIG. 4A  may also have a read word line RE, a read bit line RBL and a read port formed by transistors M 21 , M 22  coupled together to form as isolation circuit as shown. The read word line RE may be coupled to the gate of transistor M 21  that forms part of the read port while the read bit line is coupled to the source terminal of transistor M 21 . The gate of transistor M 22  may be coupled to the Db output from the cross coupled inverters  121 ,  122 . 
     During reading, multiple cells (with only a single cell being shown in  FIG. 4A ) can turn on to perform an AND function. Specifically, at the beginning of the read cycle, RBL is pre-charged high and if the Db signal of all cells that are turned on by RE is “0”, then RBL stays high since, although the gate of transistor M 21  is turned on by the RE signal, the gate of M 22  is not turned on and the RBL line is not connected to the ground to which the drain of transistor M 22  is connected. If the Db signal of any or all of the cells is “1” then RBL is discharged to 0 since the gate of M 22  is turned on and the RBL line is connected to ground. As a result, RBL=NOR (Db 0 , Db 1 , etc.) where Db 0 , Db 1 , etc. are the complementary data of the SRAM cells that have been turned on by the RE signal. Alternatively, RBL=NOR (Db 0 , Db 1 , etc.)=AND (D 0 , D 1 , etc.), where D 0 , D 1 , etc. are the true data of the cells that have been turned on by the RE signal. 
     As shown in  FIG. 4A , the Db signal of the cell  20  may be coupled to a gate of transistor M 22  to drive the RBL. However, unlike the typical 6 T cell, the Db signal is isolated from the RBL line and its signal/voltage level by the transistors M 21 , M 22 . Because the Db signal/value is isolated from the RBL line and signal/voltage level, the Db signal is not susceptive to the lower bit line level caused by multiple “0” data stored in multiple cells in contrast to the typical SRAM cell. Therefore, for the cell in  FIG. 4A , there is no limitation of how many cells can be turned on to drive RBL. As a result, the cell (and the device made up for multiple cells) offers more operands for the AND function since there is no limit of how many cells can be turned on to drive RBL. Furthermore, in the cell in  FIG. 4A , the RBL line is pre-charged (not a static pull up transistor as with the typical 6 T cell) so this cell can provide much faster sensing because the current generated by the cell is all be used to discharge the bit line capacitance with no current being consumed by a static pull up transistor so that the bit line discharging rate can be faster by more than 2 times. The sensing for the disclosed cell is also lower power without the extra current consumed by a static pull up transistor and the discharging current is reduced by more than half. 
     The write port of the cell in  FIG. 4A  is operated in the same manner as the 6 T typical SRAM cell. As a result, the write cycle and Selective Write cycle for the cell have the same limitation as the typical 6 T cell. In addition to the AND function described above, the SRAM cell  20  in  FIG. 4A  also may perform a NOR function by storing inverted data. Specifically, if D is stored at the gate of M 22 , instead of Db, then RBL=NOR (D 0 , D 1 , etc.). One skilled in the art understand that the cell configuration shown in  FIG. 4A  would be slightly altered to achieve this, but that modification is within the scope of the disclosure. Further details of this exemplary computational memory cell is found in co-pending U.S. patent application Ser. Nos. 15/709,379, 15/709,382 and Ser. No. 15/709,385 all filed on Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells” which are incorporated herein by reference. 
       FIG. 4B  illustrates an implementation of a dual port SRAM cell  100  with an XOR function. The dual port SRAM cell  100  may include two cross coupled inverters I 31 , I 32  and two access transistors M 33  and M 34  that are interconnected together as shown in  FIG. 4B  to form the basic SRAM cell. The SRAM may be operated as storage latch and may have a write port. The two inverters I 31 , I 32  are cross coupled since the input of the first inverter is connected to the output of the second inverter (labeled D) and the output of the first inverter (labeled Db) is coupled to the input of the second inverter as shown in  FIG. 4B . The cross coupled inverters I 31 , I 32  form the latch of the SRAM cell. The access transistor M 33  and M 34  may have their respective gates connected to write bit line and its complement (WBL, WBLb) respectively. A Write Word line carries a signal WE. The Write word line WE is coupled to the gate of a transistor M 35  that is part of the access circuitry for the SRAM cell. 
     The circuit in  FIG. 4B  may also have a read word line RE, a read bit line RBL and a read port formed by transistors M 31 , M 32  coupled together to form as isolation circuit as shown. The read word line RE may be coupled to the gate of transistor M 31  that forms part of the read port while the read bit line RBL is coupled to the drain terminal of transistor M 31 . The gate of transistor M 32  may be coupled to the Db output from the cross coupled inverters I 31 , I 32 . The isolation circuit isolates the latch output Db (in the example in  FIG. 4B ) from the read bit line and signal/voltage level so that the Db signal is not susceptive to the lower bit line level caused by multiple “0” data stored in multiple cells in contrast to the typical SRAM cell. 
     The cell  100  may further include two more read word line transistors M 36 , M 37  and one extra complementary read word line, REb. When the read port is active, either RE or REb is high and the REb signal/voltage level is the complement of RE signal/voltage level. RBL is pre-charged high, and if one of (M 31 , M 32 ) or (M 36 , M 37 ) series transistors is on, RBL is discharged to 0. If none of (M 31 , M 32 ) or (M 36 , M 37 ) series transistors is on, then RBL stay high as 1 since it was precharged high. The following equation below, where D is the data stored in the cell and Db is the complement data stored in the cell, describes the functioning/operation of the cell:
 
 RBL =AND(NAND( RE,Db ),NAND( REb,D ))=XNOR( RE,D )  (EQ1)
 
If the word size is 8, then it needs to be stored in 8 cells (with one cell being shown in  FIG. 4B ) on the same bit line. On a search operation, an 8 bit search key can be entered using the RE, REb lines of eight cells to compare the search key with cell data. If the search key bit is 1, then the corresponding RE=1 and REb=0 for that cell. If the search key bit is 0, then the corresponding RE=0 and REb=1. If all 8 bits match the search key, then RBL will be equal to 1. IF any 1 of the 8 bits is not matched, then RBL will be discharged and be 0. Therefore, this cell  100  (when used with 7 other cells for an 8 bit search key) can perform the same XNOR function but uses half the number of cell as the typical SRAM cell. The following equation for the multiple bits on the bit line may describe the operation of the cells as:
 
 RBL =AND(XNOR( RE 1, D 1),XNOR( RE 2, D 2), . . . ,XNOR( REi,Di )), where  i  is the number of active cell.  (EQ2)
 
     By controlling either RE or REb to be a high signal/on, the circuit  100  may also be used to do logic operations mixing true and complement data as shown below:
 
 RBL =AND( D 1, D 2, . . . , Dn,Dbn+ 1, Dbn+ 2, . . .  Dbm )  (EQ3)
 
     where D 1 , D 2 , . . . Dn are “n” number of data with RE on and Dbn+1, Dbn+2, . . . Dbm are m-n number of data with REb on. 
     Furthermore, if the cell  100  stores inverse data, meaning WBL and WBLb shown in  FIG. 4B  is swapped, then the logic equation EQ1 becomes XOR function and logic equation EQ3 becomes NOR a function and can be expressed as EQ 4 and EQ5
 
 RBL =XOR( RE,D )  (EQ4)
 
 RBL =NOR( D 1, D 2, . . . , Dn,Dbn+ 1, Dbn+ 2, . . .  Dbm )  (EQ5)
 
where D 1 , D 2 , . . . Dn are n number of data with RE on and Dbn+1, Dbn+2, . . . Dbm are m-n number of data with REb on.
 
     In another embodiment, the read port of the circuit  100  is  FIG. 4B  may be reconfigured differently to achieve different Boolean equation. Specifically, transistors M 31 , M 32 , M 36  and M 37  may be changed to PMOS and the source of M 32  and M 37  is VDD instead of VSS, the bit line is pre-charged to 0 instead of 1 and the word line RE active state is 0. In this embodiment, the logic equations EQ1 is inverted so that RBL is an XOR function of RE and D (EQ6). EQ3 is rewritten as an OR function (EQ7) as follows:
 
 RBL =XOR( RE,D )  (EQ6)
 
 RBL =OR( D 1, D 2, . . . , Dn,Dbn+ 1, Dbn+ 2, . . .  Dbm )  (EQ7)
 
     where D 1 , D 2 , . . . Dn are n number of data with RE on and Dbn+1, Dbn+2, . . . Dbm are m-n number of data with REb on. 
     If the cell stores the inverse data of the above discussed PMOS read port, meaning WBL and WBLb is swapped, then
 
 RBL =XNOR( RE,D )  (EQ8)
 
 RBL =NAND( D 1, D 2, . . . , Dn,Dbn+ 1, Dbn+ 2, . . .  Dbm )  (EQ9)
 
     where D 1 , D 2 , . . . Dn are n number of data with RE on and Dbn+1, Dbn+2, . . . Dbm are m-n number of data with REb on. 
     For example, consider a search operation where a digital word needs to be found in a memory array in which the memory array can be configured as each bit of the word stored on the same bit line. To compare 1 bit of the word, then the data is stored in a cell and its RE is the search key Key, then EQ1 can be written as below:
 
 RBL =XNOR(Key, D )  EQ10
 
     If Key=D, then RBL=1. If the word size is 8 bits as D[0:7], then the search key Key[0:7] is its RE, then EQ2 can be expressed as search result and be written as below:
 
 RBL =AND(XNOR(Key[0], D [0]),XNOR(Key[1], D [1], . . . ,Key[7], D [7])  EQ11
 
If all Key[i] is equal to D[i] where i=0-7, then the search result RBL is match. Any one of Key[i] is not equal to D[i], then the search result is not match. Parallel search can be performed in  1  operation by arranging multiple data words along the same word line and on parallel bit lines with each word on 1 bit line. Further details of this computation memory cell may be found in U.S. patent application Ser. No. 15/709,399 and Ser. No. 15/709,401 both filed on Sep. 19, 2017 and entitled “Computational Dual Port Sram Cell And Processing Array Device Using The Dual Port Sram Cells For Xor And Xnor Computations”, which are incorporated herein by reference.
 
       FIG. 5  illustrates more details of the read/write circuitry  34  including read logic, read data storage, and write logic for each bl-sect in the processing array device depicted in  FIG. 3C . The read/write circuitry  34  for each bit line section may include read circuitry  50 , a read storage  52 , implemented as a register, and write circuitry  54 . The read/write circuitry  34  may also implement one embodiment of the write inhibit circuitry as described below. The read circuitry  50  and read storage  52  allows the data on the read bit lines connected to the particular read circuitry and read storage to accumulate so that more complex Boolean logic operations may be performed. Various implementations of the read circuitry  50  and read storage  52  may be found in Ser. No. 16/111,178, filed Aug. 23, 2018 that is co-pending and co-owned and is incorporated herein by reference. The write circuitry  54  manages the writing of data from each section. Each of the read circuitry  50 , read storage  52  and write circuitry  54  may be connected to one or more control signals (S[x]_RW_Ctrl[p:0] in the example implementation shown in  FIG. 5 ) that control the operation of each of the circuits. The control signals may include the read control signals that are described above in the incorporated by reference patent application. 
     The read circuitry  50  may receive inputs from the read bit line of the computing memory cells of the section (S[x]_RBL[y]) and the write circuitry  54  may receive an input from the read data storage  52  and output data to the write bit lines of the computing memory cells of the section (S[x]_WBL[y] and S[x]_WBLb[y] in the example in  FIG. 5 ). 
       FIG. 6  illustrates the read and write control circuitry  34  in a single bit line section (Section[x], BL[y] in this example) from  FIGS. 3B and 3C  that can be used when the act of reading multiple memory cells on a read bit line produces a logical AND of the data stored in those computational memory cells. The read/write circuitry  34  may have a pullup element  600  (RBL Pullup in  FIG. 6 ), such as a pullup transistor, that is used to pre-charge the read bit line (S[x]_RBL[y] in  FIG. 6 ). The one or more read/write control signals may include a GRE control signal (S[x]_GRE) that is used to enable and disable the pullup element  600 . The GRE signal may be generated and is the logical OR of the RE[m:0] signals (see  FIGS. 3A-3C ) used to read the memory cells connected to the read bit line, and when asserted to “1” indicates that an active read operation to one or more of those memory cells is in progress. When GRE=0, the pullup transistor is enabled, thereby pre-charging the read bit line to “1”. When GRE=1, the pullup transistor is disabled, thereby allowing the read bit line to be discharged to “0” if the data stored in one or more of the memory cells being read is =“0”. 
     The circuitry in  FIG. 6  may further comprise additional write logic  602  in the write logic  54 , such as two AND gates  604 ,  606  in one implementation, used to generate the positive write bit line (WBL) and negative write bit line (WBLb) states that determine the logic value stored in the memory cell during write operations. A GWE control signal, along with the “WrData” output (write data signal) of the previously-disclosed write logic, is used to control the states of WBL and WBLb by controlling the state of each AND gate. The GWE signal is generated by the read/write logic control  32  and is the logical OR of the WE[m:0] signals (see  FIGS. 3A-3C ) used to write the memory cells connected to the write bit lines, and when asserted to “1” indicates that an active write operation to one or more of those memory cells is in progress. When GWE=0, WBL and WBLb (i.e. the outputs of the two AND gates) are both “0”, and memory cell content remains unchanged. When GWE=1, WBL=WrData and WBLb=not WrData. If WrData=1 then WBL=1 and WBLb=0, and a logic “1” is stored in the memory cell(s) that is/are actively being written. If WrData=0 then WBL=0 and WBLb=1, and a logic “0” is stored in the memory cell(s) that is/are actively being written. 
     As shown in  FIG. 7 , using the circuitry shown in  FIG. 6  as a starting point, a mechanism to inhibit writes to the memory cells in selective bl-sects on a per-write operation basis may be achieved by forcing WBL and WBLb to “0” when a “Write If Valid” (wifval) control signal is asserted to “1” (simultaneously with one or more WE[m:0]=1), to indicate that the state of the write mux output (Wmux_Out) should be used to determine whether or not to inhibit writes to the memory cells in the bl-sect for that particular write operation, and Wmux_Out=0. In this way, writes to write-enabled memory cell(s) only occur if Wmux_Out=1; otherwise, the data stored in write-enabled memory cells remains unchanged (as disclosed in the previously-referenced patent). 
       FIG. 7  illustrates a first embodiment of the read and write control circuitry  34  in a single bit line section from  FIGS. 3B and 3C  that includes a write inhibit capability for memory cells in selective bit line sections on a per-write-operation basis. In addition to the pullup element  600  and additional write circuitry  602 - 606  shown in  FIG. 6 , this circuitry may further include a third logic gate  700  (a 2 input AND gate for example) and a fourth logic gate  702  (a two input NOR gate for example) in the write logic  54 . The third logic gate  700  may have a first input connected to the wifval control signal and its other input connected to the inverted Wmux_Out output from the write multiplexer WMUX signal whose output is the selected read register output signal to be written into the memory cells. The third logic gate  700  outputs a “WrInh” signal that is the second input to the fourth logic gate  702 . The fourth logic gate  702  has a first input that is the inverted GWE control signal and a second input that is the WrInh output. The fourth logic gate  702  has an output “WrEnable” (write enable) that is the first input to the two AND gates  604 ,  606  that control and generate WBL and WBLb as described above. The “WrEnable” signal generated by the third and fourth logic gates  700 ,  702  thus controls the generation of the write signals and provides the write inhibit capability. 
       FIG. 8  illustrates a second embodiment of the read and write control circuitry  34  in a single bit line section from  FIGS. 3B and 3C  that has additional circuitry, including write logic circuitry, that can be used to inhibit the read bit line pre-charge in selective bit line sections and to inhibit writes to the memory cells in selective bit line sections for an extended period of time. One implementation of a mechanism to inhibit the read bit line pre-charge in irrelevant bl-sects, and to inhibit writes to the memory cells in irrelevant bl-sects, is to implement a Set-Reset (S-R) latch  800  in the read circuitry whose output, when set to “1”, indicates that the bl-sect has been “decommissioned” (i.e. identified as containing data that is irrelevant to the final algorithm result, and marked as such). The S-R latch is set to “1” when an “inhibit set” (inhset) control signal (from the control signals generated by the read/write logic control  32  in  FIG. 3A ) is asserted to “1”, to indicate that the state of the read bit line should be used to determine whether or not to decommission the bl-sect, and RBL=0. The S-R latch is reset to “0” when an “inhibit reset” (inhreset) control signal is asserted to “1”. 
     The general idea here is that at various stages in an algorithm, such as a search algorithm, the circuitry can arrange for RBL=1 in bl-sects that the algorithm has identified as containing data relevant to the final result, and it can arrange for RBL=0 in bl-sets that the algorithm has identified as containing data irrelevant to the final result and the logic control  32  may assert the inhset control signal to decommission the latter bl-sects. Later, at the end of the algorithm, the control logic  32  may assert the inhreset control signal to recommission any decommissioned bl-sects. Note that asserting inhreset=1 has no effect in bl-sects that were never decommissioned. 
     The circuitry in  FIG. 8  may include a pulldown element  802 , such as a pulldown transistor, that is connected to the read bit line (RBL[y]). When the output of the S-R latch is “0” (i.e. the bl-sect is in commission), the state of GRE controls the state of the RBL pullup, as in  FIG. 6 , and the RBL pulldown is disabled. When the output of the S-R latch is “1” (i.e. the bl-sect is decommissioned), the RBL pullup is disabled and the RBL pulldown is enabled, thereby forcing RBL=0 until the bl-sect is recommissioned (i.e. until the S-R latch is reset to “0”) thus inhibiting the read line bit precharge and saving power. Additionally, when the output of the S-R latch is “0”, the state of GWE controls the states of WBL and WBLb, as in  FIG. 6  and described above. When the output of the S-R latch is “1”, WBL and WBLb are forced to “0”, causing the memory cells connected to WBL and WBLb to retain their current states even when their respective WE control signals are asserted to “1” (as disclosed in the previously-referenced patent), thereby inhibiting writes to the memory cells in the bl-sect until it is recommissioned (i.e. until the S-R latch is reset to “0”). 
     In summary,  FIG. 8  depicts the pulldown element  802  implemented on the read bit line and a third 2-input AND gate  804  (the first two AND gates being those that generate WBL and WBLb), whose first input is the inhset control signal, whose second input is the inverted state of the read bit line (RBL), and whose output is the “Set” input to the S-R latch  800 . The S-R latch has a “Reset” input connected to the inhreset control signal, and whose output “Inh”: 1) controls the enable/disable state of the RBL pulldown transistor (0=disable, 1=enable), and 2) is the first input to a first 2-input NOR gate  806 , and 3) is the first input to a second 2-input NOR gate  808 . The first 2-input NOR gate  806  has a first input that is the Inh output of the S-R latch, a second input is the GRE control signal, and an output “puen” that controls the enable/disable state of the RBL pullup transistor (0=disable, 1=enable). The second 2-input NOR gate  808  has a first input that is the Inh output of the S-R latch, a second input is the inverted GWE control signal, and an output “WrEnable” is the first input to the two AND gates  604 ,  606  that generate WBL and WBLb or inhibit the writing of data as described above. 
       FIG. 9  illustrates a third embodiment of read and write control circuitry  34  in a single bit line section from  FIGS. 3B and 3C  that combines the circuitry in  FIGS. 7-8 . The circuitry shown in  FIG. 9  thus supports both sets of capabilities described above with reference to  FIGS. 7-8 . The same circuitry in  FIGS. 7 and 8  is numbered similarly in  FIG. 9  and operates in the same manner so that circuitry (elements  600 - 808 ) and its operation will not be described here. 
     The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. 
     The system and method disclosed herein may be implemented via one or more components, systems, servers, appliances, other subcomponents, or distributed between such elements. When implemented as a system, such systems may include an/or involve, inter alia, components such as software modules, general-purpose CPU, RAM, etc. found in general-purpose computers. In implementations where the innovations reside on a server, such a server may include or involve components such as CPU, RAM, etc., such as those found in general-purpose computers. 
     Additionally, the system and method herein may be achieved via implementations with disparate or entirely different software, hardware and/or firmware components, beyond that set forth above. With regard to such other components (e.g., software, processing components, etc.) and/or computer-readable media associated with or embodying the present inventions, for example, aspects of the innovations herein may be implemented consistent with numerous general purpose or special purpose computing systems or configurations. Various exemplary computing systems, environments, and/or configurations that may be suitable for use with the innovations herein may include, but are not limited to: software or other components within or embodied on personal computers, servers or server computing devices such as routing/connectivity components, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, consumer electronic devices, network PCs, other existing computer platforms, distributed computing environments that include one or more of the above systems or devices, etc. 
     In some instances, aspects of the system and method may be achieved via or performed by logic and/or logic instructions including program modules, executed in association with such components or circuitry, for example. In general, program modules may include routines, programs, objects, components, data structures, etc. that performs particular tasks or implement particular instructions herein. The inventions may also be practiced in the context of distributed software, computer, or circuit settings where circuitry is connected via communication buses, circuitry or links. In distributed settings, control/instructions may occur from both local and remote computer storage media including memory storage devices. 
     The software, circuitry and components herein may also include and/or utilize one or more type of computer readable media. Computer readable media can be any available media that is resident on, associable with, or can be accessed by such circuits and/or computing components. By way of example, and not limitation, computer readable media may comprise computer storage media and communication media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and can accessed by computing component. Communication media may comprise computer readable instructions, data structures, program modules and/or other components. Further, communication media may include wired media such as a wired network or direct-wired connection, however no media of any such type herein includes transitory media. Combinations of the any of the above are also included within the scope of computer readable media. 
     In the present description, the terms component, module, device, etc. may refer to any type of logical or functional software elements, circuits, blocks and/or processes that may be implemented in a variety of ways. For example, the functions of various circuits and/or blocks can be combined with one another into any other number of modules. Each module may even be implemented as a software program stored on a tangible memory (e.g., random access memory, read only memory, CD-ROM memory, hard disk drive, etc.) to be read by a central processing unit to implement the functions of the innovations herein. Or, the modules can comprise programming instructions transmitted to a general purpose computer or to processing/graphics hardware via a transmission carrier wave. Also, the modules can be implemented as hardware logic circuitry implementing the functions encompassed by the innovations herein. Finally, the modules can be implemented using special purpose instructions (SIMD instructions), field programmable logic arrays or any mix thereof which provides the desired level performance and cost. 
     As disclosed herein, features consistent with the disclosure may be implemented via computer-hardware, software and/or firmware. For example, the systems and methods disclosed herein may be embodied in various forms including, for example, a data processor, such as a computer that also includes a database, digital electronic circuitry, firmware, software, or in combinations of them. Further, while some of the disclosed implementations describe specific hardware components, systems and methods consistent with the innovations herein may be implemented with any combination of hardware, software and/or firmware. Moreover, the above-noted features and other aspects and principles of the innovations herein may be implemented in various environments. Such environments and related applications may be specially constructed for performing the various routines, processes and/or operations according to the invention or they may include a general-purpose computer or computing platform selectively activated or reconfigured by code to provide the necessary functionality. The processes disclosed herein are not inherently related to any particular computer, network, architecture, environment, or other apparatus, and may be implemented by a suitable combination of hardware, software, and/or firmware. For example, various general-purpose machines may be used with programs written in accordance with teachings of the invention, or it may be more convenient to construct a specialized apparatus or system to perform the required methods and techniques. 
     Aspects of the method and system described herein, such as the logic, may also be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices (“PLDs”), such as field programmable gate arrays (“FPGAs”), programmable array logic (“PAL”) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits. Some other possibilities for implementing aspects include: memory devices, microcontrollers with memory (such as EEPROM), embedded microprocessors, firmware, software, etc. Furthermore, aspects may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. The underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (“MOSFET”) technologies like complementary metal-oxide semiconductor (“CMOS”), bipolar technologies like emitter-coupled logic (“ECL”), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, and so on. 
     It should also be noted that the various logic and/or functions disclosed herein may be enabled using any number of combinations of hardware, firmware, and/or as data and/or instructions embodied in various machine-readable or computer-readable media, in terms of their behavioral, register transfer, logic component, and/or other characteristics. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) though again does not include transitory media. Unless the context clearly requires otherwise, throughout the description, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list. 
     Although certain presently preferred implementations of the invention have been specifically described herein, it will be apparent to those skilled in the art to which the invention pertains that variations and modifications of the various implementations shown and described herein may be made without departing from the spirit and scope of the invention. Accordingly, it is intended that the invention be limited only to the extent required by the applicable rules of law. 
     While the foregoing has been with reference to a particular embodiment of the disclosure, it will be appreciated by those skilled in the art that changes in this embodiment may be made without departing from the principles and spirit of the disclosure, the scope of which is defined by the appended claims.