Patent Publication Number: US-2023139314-A1

Title: Semiconductor devices

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims the benefit below 35 USC 119(a) of Korean Patent Application No. 10-2021-0149072 filed on Nov. 2, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. 
     BACKGROUND 
     The present disclosure relates to a semiconductor device. 
     As demand for high performance, high speed, and/or multifunctionality of semiconductor devices increase, the degree of integration of semiconductor devices is increasing. In manufacturing a semiconductor device having a fine pattern corresponding to the trend for high integration of semiconductor devices, it may be beneficial to implement patterns having a fine width or a fine separation distance. In addition, in order to reduce limitations in operating characteristics due to size reductions of planar metal oxide semiconductor FETs (MOSFETs), efforts are being made to develop a semiconductor device having a channel including a three-dimensional structure. 
     SUMMARY 
     Example embodiments provide a semiconductor device having improved electrical characteristics and reliability. 
     According to example embodiments, a semiconductor device comprises: a substrate including an active region extending in a first direction; a gate electrode extending in a second direction and intersecting the active region on the substrate, the gate electrode comprising at least one first electrode layer and a second electrode layer; a plurality of channel layers on the active region and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate the plurality of channel layers at least partially surrounded by the gate electrode; a plurality of source/drain regions, with at least one source/drain region on each side of the gate electrode, the plurality of channel layers electrically connected to the plurality of channel layers; and one or more air gap regions located in the second electrode layer between the plurality of channel layers and between a lowermost channel layer of the plurality of channel layers and the active region in the third direction. The at least one first electrode layer or the second electrode layer has a first thickness between adjacent ones of the plurality of channel layers in the third direction, and has a second thickness on side surfaces of the plurality of channel layers, wherein the second thickness is greater than the first thickness. 
     According to example embodiments, a semiconductor device comprises: a substrate having first and second regions, the substrate comprising an active region on each of the first and second regions, respectively; a first gate electrode on the first region intersecting the active region and comprising at least one first electrode layer and a second electrode layer; a second gate electrode on the second region intersecting the active region and comprising at least one third electrode layer and a fourth electrode layer; a plurality of channel layers on each of the active regions, respectively, the plurality of channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and at least partially surrounded by the first and second gate electrodes, respectively; and one or more air gap regions located in the fourth electrode layer between at least portions of the plurality of channel layers on the second region in the vertical direction. The at least one third electrode layer comprises a same material as a material of the at least one first electrode layer, and the fourth electrode layer comprises a same material as a material of the second electrode layer, and wherein the at least one first electrode layer has a first thickness on the first region, and the at least one third electrode layer on the second region has a second thickness that is less than the first thickness. 
     According to example embodiments, a semiconductor device comprises: a substrate comprising an active region; a gate electrode extending on the substrate and intersecting the active region, the gate electrode comprising a first electrode layer; a plurality of channel layers on the active region and spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate the plurality of channel layers at least partially surrounded by the gate electrode a plurality of source/drain regions, with at least one source/drain region on each side of the gate electrode, the plurality of source/drain regions electrically connected to the plurality of channel layers; and one or more air gap regions located in the gate electrode between the plurality of channel layers in the vertical direction. The first electrode layer surrounds an entirety of each of the one or more air gap regions and has a reduced thickness in a region overlapping the one or more air gap regions in the vertical direction. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: 
         FIG.  1    is a layout diagram illustrating a semiconductor device according to example embodiments; 
         FIG.  2    includes schematic cross-sectional views illustrating a semiconductor device according to example embodiments; 
         FIG.  3    is a partially enlarged view illustrating a portion of the semiconductor device of  FIG.  2    according to example embodiments; 
         FIGS.  4 A and  4 B  are schematic cross-sectional views and partially enlarged views illustrating a semiconductor device according to example embodiments; 
         FIG.  5    includes schematic cross-sectional views illustrating a semiconductor device according to example embodiments; 
         FIGS.  6 A and  6 B  are a layout view and a schematic cross-sectional view illustrating a semiconductor device according to example embodiments, respectively; 
         FIG.  7    includes schematic cross-sectional views illustrating a semiconductor device according to example embodiments; 
         FIG.  8    includes schematic cross-sectional views illustrating a semiconductor device according to example embodiments; 
         FIG.  9    is a flowchart illustrating a method of manufacturing a semiconductor device according to example embodiments; 
         FIGS.  10 A to  10 H  are views illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments; and 
         FIGS.  11 A to  11 G  are diagrams illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, example embodiments will be described with reference to the accompanying drawings. 
       FIG.  1    is a layout diagram illustrating a semiconductor device according to example embodiments. For convenience of description, only some components of the semiconductor device are illustrated in  FIG.  1   . 
       FIG.  2    includes schematic cross-sectional views illustrating a semiconductor device according to example embodiments.  FIG.  2    illustrates cross-sections taken along lines I-I′ and II-II′ of  FIG.  1   . 
       FIG.  3    is a partially enlarged view illustrating a portion of the semiconductor device of  FIG.  2    according to example embodiments.  FIG.  3    illustrates an enlarged area ‘A’ of  FIG.  2   . 
     Referring to  FIGS.  1  to  3   , a semiconductor device  100  may include a substrate  101  including an active region  105 , a channel structure  140  including first to third channel layers  141 ,  142  and  143  vertically spaced apart from each other on the active region  105 , a gate structure GS extending through and intersecting the active region  105  and including a gate electrode  170 , source/drain regions  150  in contact with the channel structure  140 , air gap regions AG located in the gate electrode  170 , and contact plugs  180  connected to the source/drain regions  150 . The semiconductor device  100  may further include an isolation layer  110 , inner spacer layers  130 , and an interlayer insulating layer  190 . The gate structure GS includes gate dielectric layers  162 , gate spacer layers  164 , and the gate electrode  170  including the first to third electrode layers  172 ,  174 , and  176 . 
     In the semiconductor device  100 , the active region  105  may have a fin shape, and the gate electrode  170  may be between the active region  105  and the channel structure  140 , between the first to third channel layers  141 ,  142 , and  143  of the channel structure  140 , and on the channel structure  140 . Accordingly, the semiconductor device  100  may include a transistor having a multi-bridge channel FET (MBCFET™) structure, which is a gate-all-around field effect transistor. 
     The substrate  101  may have an upper surface extending in the X-direction and the Y-direction. The substrate  101  may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate  101  may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like. 
     The substrate  101  may include an active region  105  in an upper portion thereof. The active region  105  may be defined by a device isolation layer  110  in the substrate  101  and may extend in a first direction, for example, the X-direction. However, it may be possible to describe the active region  105  as an element separate from the substrate  101  according to one embodiment. The active region  105  may have a structure extending upwardly. The active region  105  may be formed as a portion of the substrate  101 , or may include an epitaxial layer grown from the substrate  101 . However, on both sides of the gate structure GS, the active region  105  may be partially recessed to form recess regions, and source/drain regions  150  may be disposed in the recess regions. 
     In example embodiments, the active region  105  may or may not include a well region including impurities. For example, in the case of a P-type transistor (pFET), the well region may include N-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), and in the case of an N-type transistor, the well region may include P-type impurities such as boron (B), gallium (Ga), or aluminum (Al). In the case of including the well region, the well region may be located at a predetermined depth from the upper surface of the active region  105 . 
     The device isolation layer  110  may define the active region  105  in the substrate  101 . The device isolation layer  110  may be formed by, for example, a shallow trench isolation (STI) process. In some embodiments, the device isolation layer  110  may further include a region extending relatively further deeply while having a step into a lower portion of the substrate  101 . The device isolation layer  110  may expose an upper surface of the active region  105 , or partially expose an upper portion of the active region  105 . In example embodiments, the device isolation layer  110  may have a curved upper surface to have a higher level as it approaches the active region  105 . In some embodiments, “level” may mean a height level when viewed with respect to a reference plane, such as an upper surface of the substrate  101 . When an Element A is said to be at a “higher level” than Element B, this may mean that Element A is a height level that is further away from an upper surface of the substrate  101  than the height level of Element B. When an Element A is said to be at a “lower level” than Element B, this may mean that Element A is a height level that is closer to an upper surface of the substrate  101  than the height level of Element B. The device isolation layer  110  may be formed of an insulating material. The device isolation layer  110  may be formed of, for example, an oxide, a nitride, or a combination thereof. 
     The channel structure  140  may be on the active region  105  in regions in which the active region  105  intersects the gate structure GS. The channel structure  140  may include first to third channel layers  141 ,  142 , and  143 , which are two or more channel layers spaced apart from each other in the Z-direction. The channel structure  140  may be connected to the source/drain regions  150 , such as by being electrically connected. The channel structure  140  may have a width equal to or smaller than that of the active region  105  in the Y-direction, and may have a width equal to or similar to that of the gate structure GS in the X-direction. In some embodiments, the channel structure  140  may have a reduced width such that side surfaces are below the gate structure GS in the X-direction. As used herein, when the term Element A is “below” Element B is used, it may refer to the situation where Element A is closer to a reference plane, such as substrate  101 , in a particular direction than Element B. Likewise, when the term Element A is “above” Element B is used, it may refer to the situation where Element A is further away from a reference plane, such as substrate  101 , in a particular direction than Element B. 
     The channel structure  140  may be formed of a semiconductor material, and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel structure  140  may be formed of, for example, the same material as a material of the substrate  101 . In some embodiments, the channel structure  140  may include an impurity region in a region adjacent to the source/drain regions  150 . The number and shape of the channel layers constituting one channel structure  140  may be variously changed in the example embodiments. For example, in some embodiments, the channel structure  140  may further include a channel layer below a lowermost portion of the gate electrode  170 . 
     The source/drain regions  150  may be on both sides of the gate structure GS in recess regions partially recessed from the upper portions of the active regions  105 , such that at least one source/drain region  150  is on each side of the gate structure GS. The source/drain regions  150  may be on, and at least partially cover, side surfaces of each of the first to third channel layers  141 ,  142 , and  143  of the channel structure  140 . The upper surfaces of the source/drain regions  150  may be at the same or similar height as the lower surface of an uppermost portion of the gate electrode  170 , and the height may be variously changed in example embodiments. According to example embodiments, the source/drain regions  150  may be connected to or merged with each other on two or more active regions  105  adjacent to each other in the Y-direction to form one source/drain region  150 . The source/drain regions  150  may include impurities. 
     The gate structure GS may intersect the active region  105  and the channel structure  140  to extend in the second direction, for example, the Y-direction. Channel regions of transistors may be formed in the channel structure  140  intersecting the gate electrode  170  of the gate structure GS. The gate structure GS may include the gate electrode  170 , the gate dielectric layers  162  between the gate electrode  170  and the channel structure  140 , and the gate spacer layers  164  on sides of the gate electrode  170 . In some embodiments, the gate structure GS may further include a capping layer on the upper surface of the gate electrode  170 . Alternatively, a portion of the interlayer insulating layer  190  on the gate structure GS may be referred to as a gate capping layer. 
     The gate dielectric layers  162  may be between the active region  105  and the gate electrode  170  and between the channel structure  140  and the gate electrode  170 , and may be on, and cover at least a portion of, the surfaces of the gate electrode  170 . For example, the gate dielectric layers  162  may surround all surfaces except an uppermost surface of the gate electrode  170 . The gate dielectric layers  162  may extend between the gate electrode  170  and the gate spacer layers  164 , but the configuration is not limited thereto. The gate dielectric layers  162  may include oxide, nitride, or a high-k material. The high-k material may refer to a dielectric material having a higher dielectric constant than that of a silicon oxide layer (SiO 2 ). The high-k material may be any one of, for example, aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr 2 O 3 ). In some embodiments, the gate dielectric layers  162  may be formed of a multilayer film. 
     The gate spacer layers  164  may be on both sides of the gate electrode  170 . The gate spacer layers  164  may insulate the source/drain regions  150  from the gate electrode  170 . In some embodiments, the gate spacer layers  164  may have a multi-layer structure. The gate spacer layers  164  may be formed of oxide, nitride, and oxynitride, and in detail, a low-k film, wherein a low-k film may refer to a dielectric material having the same dielectric constant as that of a silicon oxide layer (SiO 2 ) or having a lower dielectric constant than that of a silicon oxide layer (SiO 2 ). 
     The gate electrode  170  may be on the active region  105  to at least partially fill a gap between the channel structures  140  and extend upwardly from the channel structures  140 . The gate electrode  170  may be spaced apart from the channel structure  140  by the gate dielectric layers  162 . The gate electrode  170  may include first to third electrode layers  172 ,  174 , and  176  sequentially stacked from the gate dielectric layers  162 . The first electrode layer  172  may comprises a plurality of layers in some embodiments and may be a single layer in other embodiments. The term “first electrode layer  172 ” as used herein may refer to a single layer or a plurality of layers but will include at least one layer. 
     As illustrated in  FIGS.  2 B and  3   , in a cross-section of the gate electrode  170 , the first electrode layer  172  may surround the first to third channel layers  141 ,  142 , and  143  respectively, and may be spaced apart from each other in the Z-direction. It will be understood that “an element A surrounds an element B” (or similar language) as used herein means that the element A is at least partially around the element B but does not necessarily mean that the element A completely encloses the element B, unless it is so indicated. The first electrode layer  172  may further be on upper surfaces of the active region  105  and the device isolation layer  110 . A gate dielectric layer  162  may be between the first electrode layer  172  and the first to third channel layers  141 ,  142 , and  143  and between the first electrode layer  172  and the active region  105 . In this embodiment, the first electrode layer  172  may have a uniform or constant thickness. The first electrode layer  172  may be spaced apart from the air gap regions AG and may not contact the air gap regions AG. 
     The second electrode layer  174  may be on the first electrode layer  172 . The second electrode layer  174  may be between the first to third channel layers  141 ,  142 , and  143  together with the first electrode layer  172 . As illustrated in  FIGS.  2 B and  3   , the second electrode layer  174  may surround the respective first to third channel layers  141 ,  142 , and  143  in a cross-section of the gate electrode  170 , and may be in a connected form in the Z-direction as a single layer. The second electrode layer  174  may extend downwardly along side surfaces of the first to third channel layers  141 ,  142  and  143 , and may have a curve corresponding to side surfaces of the first to third channel layers  141 ,  142  and  143 . Air gap regions AG are in the second electrode layer  174 , and the second electrode layer  174  may completely or entirely surround the respective air gap regions AG in some embodiments. 
     The second electrode layer  174  may have a non-uniform or non-constant thickness and may be non-conformally disposed around the first to third channel layers  141 ,  142 , and  143 . The second electrode layer  174  may be on the upper surface of the active region  105 , on portions of the upper surfaces of the first to third channel layers  141 ,  142 , and  143 , and on lower surfaces of the first to third channel layers  141 ,  142  and  143 , and may have a relatively thin thickness or reduced thickness. The second electrode layer  174  may have a relatively thin thickness between the first to third channel layers  141 ,  142 , and  143  and between the first channel layer  141  and the active region  105 . The second electrode layer  174  may have a relatively thin thickness above and below the air gap regions AG. As illustrated in  FIG.  3   , the second electrode layer  174  may have a first thickness T 1  in a region extending horizontally toward the air gap regions AG, and may have a second thickness T 2  greater than the first thickness T 1  on the side surfaces of the first to third channel layers  141 ,  142  and  143  and the upper surface of the device isolation layer  110 . The second electrode layer  174  may have the first thickness T 1  in a region overlapping the air gap regions AG in the Z-direction. As used herein, when element A is said to “overlap” or is “overlapping” element B, it may refer to the situation where element A is said to extend over or past, and cover a part of, element B in a given direction. Note that element A may overlap element B in a first direction, but may or may not overlap element B in a second direction. The second electrode layer  174  may be formed by a method different from that of the first electrode layer  172 , to have the profile as described above. This will be described in more detail below with reference to  FIGS.  9  and  10 G . 
     The third electrode layer  176  may be on the second electrode layer  174  and may extend in the Y-direction while filling between the adjacent active regions  105 . Unlike the first and second electrode layers  172  and  174 , the third electrode layer  176  may not be between the first to third channel layers  141 ,  142 , and  143  in the Z-direction. The third electrode layer  176  may have a thickness greater than that of the first and second electrode layers  172  and  174 . In some embodiments, the third electrode layer  176  may be omitted. 
     The gate electrode  170  may include a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and/or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. The first to third electrode layers  172 ,  174 , and  176  may include different materials. The first electrode layer  172  and the second electrode layer  174  may include materials having different work functions. For example, the second electrode layer  174  may include a material having a lower work function than a work function of the first electrode layer  172 . For example, the first electrode layer  172  may include Titanium Nitride (TiN), the second electrode layer  174  may include aluminum (Al), for example, Titanium Aluminum Carbide (TiAlC) or Titanium Aluminum Nitride (TiAlN), and the third electrode layer  176  may include tungsten (W) or molybdenum (Mo). 
     The air gap regions AG may be between the first to third channel layers  141 ,  142 , and  143  and between the first channel layer  141 , which is the lowermost channel layer of the first to third channel layers  141 ,  142 ,  143 , and the active region  105 . The air gap regions AG may be located in the second electrode layer  174 , and thus may be defined by the second electrode layer  174 . The air gap regions AG are regions formed of air or gas, but in the present specification, for ease of understanding, may be regarded as one region or layer. A plurality of air gap regions AG may be spaced apart from each other in the Z-direction. The number of air gap regions AG may be changed according to the number of channel layers constituting the channel structure  140 . 
     Lengths of the air gap regions AG in a horizontal direction, for example, an X-direction and a Y-direction, may be relatively longer than lengths in a vertical direction, for example, a Z-direction. The length of the air gap regions AG in the vertical direction may be determined by the distance between the first to third channel layers  141 ,  142 , and  143  (a separation distance) and the thickness of the first and second electrode layers  172  and  174 . By adjusting at least one of a uniform thickness of the first electrode layer  172  and a non-uniform thickness of the second electrode layer  174 , the size of the air gap regions AG may be adjusted, and accordingly, the threshold voltage of the semiconductor device  100  may be adjusted. For example, the length of the air gap regions AG in the vertical direction may be in the range of about 20% to about 50% of the distance between the adjacent channel layers  141 ,  142 , and  143 . For example, the length may range from about one nanometer (1 nm) to about five (5) nm, but is not limited thereto. 
     The inner spacer layers  130  may be between the channel structures  140  in parallel with the gate electrode  170 . The gate electrode  170  may be stably spaced apart from the source/drain regions  150  by the inner spacer layers  130  to be electrically isolated from each other. The inner spacer layers  130  may have a shape in which the side surface facing the gate electrode  170  is inwardly, convexly rounded toward the gate electrode  170 , but the configuration is not limited thereto. The inner spacer layers  130  may be formed of oxide, nitride, or oxynitride, and in detail, may be formed of a low-k film. However, in some embodiments, the inner spacer layers  130  may be omitted. 
     The contact plugs  180  may pass through the interlayer insulating layer  190  to be connected to the source/drain regions  150 , and may apply an electrical signal to the source/drain regions  150 . The contact plugs  180  may have inclined side surfaces in which a lower width is narrower than an upper width according to an aspect ratio, but the configuration is not limited thereto. For example, the contact plugs  180  may extend downwardly from an upper portion, for example, to further below the lower surface of the third channel layer  143 , but the configuration is not limited thereto. In some example embodiments, the contact plugs  180  may contact upper surfaces of the source/drain regions  150  without recessing the source/drain regions  150 . 
     The contact plugs  180  may include a metal silicide layer on a lower end including a lower surface, and may further include a barrier layer on an upper surface and sidewalls of the metal silicide layer. The barrier layer may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The contact plugs  180  may include, for example, a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In example embodiments, the number and arrangement of the conductive layers constituting the contact plugs  180  may be variously changed. 
     The interlayer insulating layer  190  may be on, and at least partially cover, the source/drain regions  150  and the gate structure GS, and be on, and at least partially cover, the device isolation layer  110 . The interlayer insulating layer  190  may include at least one of an oxide, a nitride, and an oxynitride, and may include, for example, a low-k material. In some embodiments, the interlayer insulating layer  190  may include a plurality of insulating layers. 
       FIGS.  4 A and  4 B  are schematic cross-sectional views and partially enlarged views illustrating a semiconductor device according to an example embodiment.  FIG.  4 B  illustrates an enlarged area ‘B’ of  FIG.  4 A .  FIGS.  4 A and  4 B  may include elements similar to those previously discussed. Thus, the same or similar reference numerals may be used to refer to the same or similar elements, and a description of those elements will not be repeated here. 
     Referring to  FIGS.  4 A and  4 B , in a semiconductor device  100   a,  the shapes of first and second electrode layers  172   a  and  174   a  of a gate electrode layer  170   a  may be different from those of the example embodiments of  FIGS.  2  and  3   . 
     The first electrode layer  172   a  may have a non-uniform or non-constant thickness around the first to third channel layers  141 ,  142 , and  143  and may be non-conformally disposed thereon. The first electrode layer  172   a  have a relatively thin first thickness T 1 ′ between the first to third channel layers  141 ,  142  and  143  and on the upper surface of the active region  105 , and may have a second thickness T 2 ′ greater than the first thickness T 1 ′ on side surfaces of the first to third channel layers  141 ,  142 , and  143 . The first electrode layer  172   a  may have a relatively thin thickness in a region overlapping the air gap regions AGa in the Z-direction. In contrast, the second electrode layer  174   a  may have a uniform or constant thickness on the first electrode layer  172   a.    
     In some embodiments, according to the profiles of the first electrode layer  172   a  and the second electrode layer  174   a,  air gap regions AGa may have a relatively thinned shape on the ends as compared to on the central portions in a cross-section in the Y-direction. However, the detailed shape of the air gap regions AGa is not limited thereto. 
     In some embodiments, a fourth electrode layer (not shown) may be between the gate dielectric layers  162  and the first electrode layer  172   a.  In this case, the fourth electrode layer may be a layer having a constant thickness similar to that of the second electrode layer  174   a,  and may be formed in a process different from that of the first electrode layer  172   a,  and may be formed in the same process as the second electrode layer  174   a.    
       FIG.  5    includes schematic cross-sectional views illustrating a semiconductor device according to example embodiments.  FIG.  5    may include elements similar to those previously discussed. Thus, the same or similar reference numerals may be used to refer to the same or similar elements, and a description of those elements will not be repeated here. 
     Referring to  FIG.  5   , in a semiconductor device  100   b,  a gate electrode layer  170   b  may not include a layer corresponding to the first electrode layer  172  in the example embodiment of  FIGS.  2  and  3   . The gate electrode layer  170   b  may include a second electrode layer  174  and a third electrode layer  176 . The second electrode layer  174  may be on gate dielectric layers  162 , and as described above with reference to  FIGS.  1  to  3   , may have a reduced thickness between the first to third channel layers  141 ,  142 , and  143  and on the upper surface of the active region  105 . 
       FIGS.  6 A and  6 B  are a layout view and a schematic cross-sectional view illustrating a semiconductor device according to example embodiments, respectively.  FIG.  6 B  illustrates cross-sections taken along lines III-III′, IV-IV′, and V-V′ of  FIG.  6 A . 
     Referring to  FIGS.  6 A and  6 B , in a semiconductor device  100   c,  a substrate  101  may have first to third regions R 1 , R 2 , and R 3 . The first to third regions R 1 , R 2  and R 3  may be areas adjacent to or spaced apart from each other, and may be areas in which first to third gate electrodes  170 A,  170 B, and  170 C, each including respective first electrode layers  172  with different thicknesses, are disposed respectively. 
     First to third transistors including the first to third gate electrodes  170 A,  170 B, and  170 C, respectively, may be transistors driven under different threshold voltages, and may constitute the same circuit or different circuits in the semiconductor device  100   c.  For example, when the first to third transistors are pFETs, a first transistor of the first region R 1  may have a lowest threshold voltage and operating voltage, based on the absolute value, and a third region of the third transistor R 3  may have a highest threshold voltage and operating voltage. 
     In each of the first to third regions R 1 , R 2 , and R 3 , each of the first electrode layers  172  may have a substantially uniform thickness. On the first region R 1 , the first electrode layer  172  has a third thickness T 3 , and on the second region R 2 , the first electrode layer  172  have a fourth thickness T 4  less than a third thickness T 3 , and on the third region R 3 , the first electrode layer  172  may have a fifth thickness T 5  less than the fourth thickness T 4 . The thicknesses may be, for example, an average thickness or thicknesses on corresponding locations. For example, the first electrode layer  172  of the first region R 1  may be formed by depositing a preliminary first electrode layer three times, the first electrode layer  172  of the second region R 2  may be formed by depositing the preliminary first electrode layer twice, and the first electrode layer  172  of the third region R 3  may be formed by depositing the preliminary first electrode layer once. This structure of the first electrode layer  172  may be formed by the patterning that uses a protective layer deposited to a relatively thin thickness, between the first to third channel layers  141 ,  142  and  143 , to have a form similar to that of the second electrode layers  174 . This will be described in more detail below with reference to  FIGS.  11 A to  11 G . 
     In the first region R 1 , air gap regions AG may not be located in the first gate electrode  170 A. Accordingly, the first electrode layer  172  may be vertically connected to form one layer, and a space between the first to third channel layers  141 ,  142 , and  143  may be at least partially filled with the first electrode layer  172 . In the second and third regions R 2  and R 3 , the air gap regions AG may be located in the second and third gate electrodes  170 B and  170 C, as described with reference to  FIGS.  1  to  3   . 
     The second electrode layer  174  may have the same average thickness in the first to third regions R 1 , R 2 , and R 3 , but the configuration is not limited thereto. In the first region R 1 , the second electrode layer  174  may extend toward the substrate  101  along the first electrode layer  172 . As for the description of the second electrode layer  174  in the second and third regions R 2  and R 3 , the description with reference to  FIGS.  1  to  3    may be equally applied. In the example embodiments, since the thicknesses of the first electrode layer  172  are different from each other, when the thicknesses of the second electrode layers  174  are equal to each other, a height L 1  in the Z-direction of the air gap regions AG in the second region R 2  may be less than a height L 2  in the Z-direction of the air gap regions AG in the third region R 3 . In some embodiments, the semiconductor device  100   c  may include only two of the first to third regions R 1 , R 2 , and R 3 . 
       FIG.  7    includes schematic cross-sectional views illustrating a semiconductor device according to example embodiments.  FIG.  7    may include elements similar to those previously discussed. Thus, the same or similar reference numerals may be used to refer to the same or similar elements, and a description of those elements will not be repeated here. 
     Referring to  FIG.  7   , in a semiconductor device  100   d,  unlike the example embodiment of  FIG.  6 B , air gap regions AG may be located in a first gate electrode  170 A in the first region R 1 . Also in this embodiment, the first electrode layer  172  on the first region R 1  may have a third thickness T 3   d,  the first electrode layer  172  on the second region R 2  may have a fourth thickness T 4   d  less than the third thickness T 3   d , and the first electrode layer  172  on the third region R 3  may have a fifth thickness T 5   d  that is less than the fourth thickness T 4   d.  In some embodiments, the semiconductor device  100   d  may include only two of the first to third regions R 1 , R 2 , and R 3 . 
     As such, in example embodiments, the presence or absence of the air gap regions AG according to the region may be changed depending on a separation distance between the first to third channel layers  141 ,  142 , and  143  and a relative thickness of the first electrode layer  172 . 
       FIG.  8    includes schematic cross-sectional views illustrating a semiconductor device according to example embodiments.  FIG.  8    may include elements similar to those previously discussed. Thus, the same or similar reference numerals may be used to refer to the same or similar elements, and a description of those elements will not be repeated here. 
     Referring to  FIG.  8   , a semiconductor device  100   e  may not include the inner spacer layer  130 , unlike the example embodiment of  FIGS.  2  and  3   . In this case, the source/drain regions  150  may expand to regions in which the inner spacer layers  130  are omitted, to have an expanded shape. The gate electrode  170  may be spaced apart from the source/drain regions  150  by the gate dielectric layers  162 . In another embodiment, the source/drain regions  150  may not expand to the region in which the inner spacer layers  130  are omitted, but the gate electrode  170  may expand in the X-direction. 
     According to this structure, when the inner spacer layer  130  is omitted and the source/drain regions  150  are grown, the source/drain regions  150  may have improved crystallinity. In some embodiments, the inner spacer layer  130  may be omitted only in some devices of the semiconductor device  100   e.  For example, when SiGe is used for the source/drain regions  150  in a pFET, the inner spacer layer  130  may be selectively omitted only in the pFET to improve the crystallinity of SiGe. 
       FIG.  9    is a flowchart illustrating a method of manufacturing a semiconductor device according to example embodiments. 
       FIGS.  10 A to  10 H  are views illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments. An example embodiment of a method of manufacturing the semiconductor device of  FIGS.  1  to  3    is described with reference to  FIGS.  10 A to  10 H . 
     Referring to  FIGS.  9  and  10 A , sacrificial layers  120  and first to third channel layers  141 ,  142 , and  143  may be alternately stacked on a substrate  101  (S 110 ). 
     The sacrificial layers  120  may be the layers replaced by the gate dielectric layers  162  and the gate electrode  170  as illustrated in  FIG.  2    through a subsequent process. The sacrificial layers  120  may be formed of a material respectively having etch selectivity with respect to the first to third channel layers  141 ,  142 , and  143 . The first to third channel layers  141 ,  142 , and  143  may include a material different from that of the sacrificial layers  120 . The sacrificial layers  120  and the first to third channel layers  141 ,  142 , and  143  may include a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials, and may or may not contain impurities. For example, the sacrificial layers  120  may include silicon germanium (SiGe), and the first to third channel layers  141 ,  142 , and  143  may include silicon (Si). 
     The sacrificial layers  120  and the first to third channel layers  141 ,  142 , and  143  may be formed by performing an epitaxial growth process from the substrate  101 . Each of the sacrificial layers  120  and the first to third channel layers  141 ,  142 , and  143  may have a thickness in a range of about one Angstrom (1 Å) to about one hundred (100) nm. The number of layers of the channel layers  141 ,  142 , and  143  alternately stacked with the sacrificial layers  120  may be variously changed in example embodiments. 
     Referring to  FIGS.  9  and  10 B , an active structure may be formed by removing portions of the sacrificial layers  120 , the first to third channel layers  141 ,  142  and  143 , and the substrate  101 , and the device isolation layer  110  may be formed (S 120 ). 
     The active structure may include the sacrificial layers  120  and the first to third channel layers  141 ,  142 , and  143  stacked alternately with each other, and may further include the active region  105  that is formed to extend from the substrate  101  by removing a portion of the substrate  101 . The active structure may be formed in the form of a line extending in one direction, for example, the X-direction, and the active structures may be formed to be spaced apart from each other in the Y-direction. 
     In the region from which a portion of the substrate  101  has been removed, the insulating material is partially or completely filled, and then, the insulating material is partially removed such that the active region  105  protrudes, thereby forming the device isolation layer  110 . The upper surface of the device isolation layer  110  may be formed to be lower than the upper surface of the active region  105 . 
     Referring to  FIGS.  9  and  10 C , a sacrificial gate structure SS and gate spacer layers  164  may be formed on the active structure (S 130 ). 
     The sacrificial gate structure SS may be a sacrificial structure formed in a region in which the gate dielectric layers  162  and the gate electrode  170  are disposed, on the channel structure  140  through a subsequent process, as illustrated in  FIG.  2   . The sacrificial gate structure SS may include first and second sacrificial gate layers  202  and  204  and a mask pattern layer  206  that are sequentially stacked. The first and second sacrificial gate layers  202  and  204  may be patterned using a mask pattern layer  206 . The first and second sacrificial gate layers  202  and  204  may be an insulating layer and a conductive layer, respectively, but are not limited thereto, and the first and second sacrificial gate layers  202  and  204  may also be formed as a single layer. For example, the first sacrificial gate layer  202  may include silicon oxide, and the second sacrificial gate layer  205  may include polysilicon. The mask pattern layer  206  may include silicon oxide and/or silicon nitride. The sacrificial gate structure SS may have a line shape that intersects the active structures and extends in one direction. The sacrificial gate structure SS may extend in, for example, a Y-direction, and may be spaced apart from a sacrificial gate structure SS adjacent thereto in the X-direction. 
     The gate spacer layers  164  may be formed on both sidewalls of the sacrificial gate structure SS. The gate spacer layers  164  may be formed of a low-k material, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. 
     Referring to  FIGS.  9  and  10 D , on the outside of the sacrificial gate structure SS, the exposed sacrificial layers  120  and first to third channel layers  141 ,  142 , and  143  may be partially removed to form recess regions, inner spacer layers  130  may be formed, and source/drain regions  150  partially or completely filling the recess regions may be formed (S 140 ). 
     First, the exposed sacrificial layers  120  and first to third channel layers  141 ,  142 , and  143  are removed using the sacrificial gate structure SS and the gate spacer layers  164  as masks, thereby forming recess regions. Accordingly, the first to third channel layers  141 ,  142 , and  143  may form the channel structure  140  having a limited length in the X-direction. 
     Next, portions of the sacrificial layers  120  may be removed. The sacrificial layers  120  may be selectively etched with respect to the channel structure  140  by, for example, a wet etching process, and may be removed to a predetermined depth from the side surface in the X-direction. The sacrificial layers  120  may have inwardly concave side surfaces by side etching as described above. However, the shape of the side surfaces of the sacrificial layers  120  is not limited to the illustration. 
     Next, the inner spacer layers  130  may be formed in the regions from which the sacrificial layers  120  have been partially removed. The inner spacer layers  130  may be formed of the same material as the gate spacer layers  164 , but the material is not limited thereto. For example, the inner spacer layers  130  may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN. 
     Next, the source/drain regions  150  may be formed by growing from the upper surface of the active region  105  and side surfaces of the channel structure  140 , for example, by a selective epitaxial process. The source/drain regions  150  may include impurities by in-situ doping, and may also include a plurality of layers having different doping elements and/or doping concentrations. 
     Referring to  FIGS.  9  and  10 E , after the interlayer insulating layer  190  is formed, the sacrificial layers  120  and the sacrificial gate structure SS may be removed (S 150 ). 
     The interlayer insulating layer  190  may be formed by forming an insulating layer at least partially covering the sacrificial gate structure SS and the source/drain regions  150  and performing a planarization process. 
     The sacrificial layers  120  and the sacrificial gate structure SS may be selectively removed with respect to the gate spacer layers  164 , the interlayer insulating layer  190 , and the channel structure  140 . First, the sacrificial gate structure SS is removed to form an upper gap region UR, and lower gap regions LR may be formed by removing the sacrificial layers  120  exposed through the upper gap region UR. For example, when the sacrificial layers  120  include silicon germanium (SiGe) and the channel structures  140  include silicon (Si), the sacrificial layers  120  may be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the removal process, the source/drain regions  150  may be protected by the interlayer insulating layer  190  and the inner spacer layers  130 . 
     Hereinafter, operation (S 160 ) of forming the gate structure  160  will be described with reference to  FIGS.  9  and  10 F to  10 H . 
     First, referring to  FIGS.  9  and  10 F , the gate dielectric layers  162  may be formed (S 162 ), and the first electrode layer  172  may be formed to have a uniform thickness (S 164 ). 
     The gate dielectric layers  162  may be formed to conform to, and at least partially cover, inner surfaces of the upper gap region UR and the lower gap regions LR. 
     The first electrode layer  172  may be formed to conform to, and at least partially cover, the gate dielectric layers  162  in the upper gap region UR and the lower gap regions LR. For example, the first electrode layer  172  may be formed to have a uniform thickness using thermal atomic layer deposition. The first electrode layer  172  may be formed to have a substantially uniform thickness on a circumference of the channel structure  140 . The size of air gap regions AG (refer to  FIG.  10 G ) to be formed subsequently may be adjusted by the thickness of the first electrode layer  172 . 
     Referring to  FIGS.  9  and  10 G , the second electrode layer  174  may be formed to have a non-uniform thickness (S 166 ). 
     The second electrode layer  174  may surround the first electrode layer  172  in the upper gap region UR and the lower gap regions LR and extend onto the active region  105  and the device isolation layer  110 . The second electrode layer  174  may be formed to completely fill the lower gap regions LR in some embodiments. 
     The second electrode layer  174  may be formed by using a different deposition process from that of the first electrode layer  172 . For example, the second electrode layer  174  may be formed to have a non-uniform thickness using a plasma-enhanced atomic layer deposition (PEALD) method. This may be because, in the PEALD process, the deposition material is directionally supplied and deposited by plasma. The second electrode layer  174  is formed to be relatively thin in a region extending horizontally between the channel structures  140  and between the first channel layer  141  and the active region  105 , and to be relatively thick in other regions. 
     Between the first to third channel layers  141 ,  142  and  143  and between the first channel layer  141  and the active region  105 , the second electrode layer  174  may be deposited to a thickness that does not fill the spaces between the first to third channel layers  141 ,  142 , and  143 . Accordingly, the air gap regions AG may be formed between the first to third channel layers  141 ,  142 , and  143  and between the first channel layer  141  and the active region  105 . The size of the air gap regions AG may also be adjusted by the thickness of the second electrode layer  174 . In example embodiments, the relative thicknesses of the first electrode layer  172  and the second electrode layer  174  may be variously changed. 
     In the case of the example embodiment of  FIGS.  4 A and  4 B , in contrast to the present embodiment, the first electrode layer  172   a  may be formed by PEALD, and then the second electrode layer  174   a  may be formed by thermal ALD. 
     Referring to  FIGS.  9  and  10 H , a third electrode layer  176  may be formed (S 168 ). 
     The third electrode layer  176  may be formed on the second electrode layer  174  in the upper gap region UR, and may be formed to completely fill the upper gap region UR in some embodiments. Accordingly, the gate structure GS may be formed. The third electrode layer  176  may be formed to have a substantially flat upper surface by a planarization process or the like. In some embodiments, the third electrode layer  176  may include a plurality of conductive layers. 
     Next, an interlayer insulating layer  190  may be further formed on the gate structure GS. 
     Next, referring to  FIG.  2   , contact plugs  180  may be formed (S 170 ). 
     First, the interlayer insulating layer  190  may be patterned to form contact holes exposing the source/drain regions  150 . Contact plugs  180  may be formed by partially or completely filling the contact holes with a conductive material. In detail, after depositing a material forming a barrier layer in the contact holes, a silicide process may be performed to form a metal-semiconductor compound layer such as a silicide layer on a lower end. Next, a conductive material may be deposited to partially or completely fill the contact holes to form the contact plugs  180 . Accordingly, the semiconductor device  100  of  FIGS.  1  to  3    may be manufactured. 
       FIGS.  11 A to  11 G  are diagrams illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments. An example embodiment of a method of manufacturing the semiconductor device of  FIGS.  6 A and  6 B  will be described with reference to  FIGS.  11 A to  11 G .  FIGS.  11 A- 11 G  may include elements similar to those previously discussed. Thus, the same or similar reference numerals may be used to refer to the same or similar elements, and a description of those elements will not be repeated here. 
     Referring to  FIG.  11 A , in the first to third regions R 1 , R 2  and R 3 , the operations described above with reference to  FIGS.  10 A to  10 E  are performed in the same manner, and after forming the upper gap region UR and the lower gap regions LR, preliminary first electrode layer  172 P may be formed. 
     The preliminary first electrode layer  172 P may be formed to conform to, and at least partially cover, the gate dielectric layers  162  in the upper gap region UR and the lower gap regions LR in the first to third regions R 1 , R 2 , and R 3 . In this operation, the preliminary first electrode layer  172 P may be formed to have a fifth thickness T 5 . In the following embodiments of the manufacturing method, a case in which a ratio (T 3 :T 4 :T 5 ) of the third thickness (T 3 ), the fourth thickness (T 4 ), and the fifth thickness (T 5 ) of  FIG.  6 B  is 3:2:1 will be described. However, the ratio (T 3 :T 4 :T 5 ) is not limited thereto. 
     Referring to  FIG.  11 B , a first protective layer PL 1  may be formed in the first to third regions R 1 , R 2 , and R 3 , and a first mask layer ML 1  may be formed in the first region R 1 . 
     The first protective layer PL 1  may be nonconformally formed, while surrounding the preliminary first electrode layer  172 P. The first protective layer PL 1  may include, for example, at least one of aluminum oxide (AlOx), titanium oxide (TiOx), and titanium nitride (TiN). The first protective layer PL 1  may be formed in the same manner as the second electrode layer  174  described above with reference to  FIG.  10 G . For example, the first protective layer PL 1  may be formed to have a non-uniform thickness using PEALD. The first protective layer PL 1  is formed to be relatively thin in a region extending horizontally between the channel structures  140  and between the first channel layer  141  and the active region  105 , and may be formed to be relatively thick in other regions. Accordingly, between the first to third channel layers  141 ,  142  and  143  and between the first channel layer  141  and the active region  105 , air gap regions AG′ may be formed in the first protective layer PL 1 . 
     The first mask layer ML 1  may be formed to at least partially cover the first region R 1 . The first mask layer ML 1  may be, for example, a photoresist layer, but is not limited thereto. 
     Referring to  FIG.  11 C , the first protective layer PL 1  and the preliminary first electrode layer  172 P may be removed from the second and third regions R 2  and R 3 . 
     The first protective layer PL 1  may be removed from the second and third regions R 2  and R 3  exposed from the first mask layer ML 1 , thereby removing the exposed preliminary first electrode layer  172 P. Accordingly, the preliminary first electrode layer  172 P may remain only in the first region R 1 . 
     In this operation, since the air gap regions AG′ are formed in the first protective layer PL 1 , the path of the etchant is secured, and a defect in which the first protective layer PL 1  remains between the first to third channel layers  141 ,  142 , and  143  and between the first channel layer  141  and the active region  105  may be prevented. 
     Referring to  FIG.  11 D , the first mask layer ML 1  and the first protective layer PL 1  may be removed from the first region R 1 , and preliminary first electrode layer  172 P may be additionally formed in the first to third regions R 1 , R 2 , and R 3 . 
     First, the first mask layer ML 1  and the first protective layer PL 1  may be sequentially removed from the first region R 1  to expose the preliminary first electrode layer  172 P. In this operation, since the air gap regions AG′ are formed in the first protective layer PL 1 , the path of the etchant is secured, and thus, defects in which the first protective layer PL 1  remains between the first to third channel layers  141 ,  142 , and  143  and between the first channel layer  141  and the active region  105 , or in which lower preliminary first electrode layers  172 P are damaged, may be prevented. 
     Next, preliminary first electrode layer  172 P may be additionally formed in the entire first to third regions R 1 , R 2 , and R 3 . In this operation, the preliminary first electrode layer  172 P may be further formed with a fifth thickness T 5 . Accordingly, in the first region R 1 , the preliminary first electrode layer  172 P have a fourth thickness T 4  that is twice the fifth thickness T 5 , and in the second and third regions R 2  and R 3 , the preliminary first electrode layer  172 P may have the fifth thickness T 5 . 
     Referring to  FIG.  11 E , a second protective layer PL 2  may be formed in the first to third regions R 1 , R 2  and R 3 , and a second mask layer ML 2  may be formed in the first and second regions R 1  and R 2 . 
     The second mask layer ML 2  may be formed to expose the third region R 3 . The second protective layer PL 2  and the second mask layer ML 2  may be formed in the same manner as the first protective layer PL 1  and the first mask layer ML 1  described above with reference to  FIG.  11 B , respectively. 
     Referring to  FIG.  11 F , the second protective layer PL 2  and the preliminary first electrode layer  172 P may be removed from the third region R 3 . 
     The second protective layer PL 2  may be removed from the third region R 3  exposed from the second mask layer ML 2 , thereby removing the exposed preliminary first electrode layer  172 P. Accordingly, in the first region R 1 , the preliminary first electrode layer  172 P have a fourth thickness T 4 , and in the second region R 2 , the preliminary first electrode layer  172 P have a fifth thickness T 5 , and the preliminary first electrode layer  172 P may not remain in the third region R 3 . 
     Referring to  FIG.  11 G , the second mask layer ML 2  and the second protective layer PL 2  are removed from the first and second regions R 1  and R 2 , and the preliminary first electrode layer  172 P may be additionally formed in the first to third regions R 1 , R 2  and R 3 , thereby forming the first electrode layer  172 . 
     First, the second mask layer ML 2  and the second protective layer PL 2  are sequentially removed from the first and second regions R 1  and R 2 , thereby exposing the preliminary first electrode layer  172 P. Next, preliminary first electrode layer  172 P may be additionally formed in the entire first to third regions R 1 , R 2 , and R 3 . In this operation, the preliminary first electrode layer  172 P may be further formed with a fifth thickness T 5 . Accordingly, the preliminary first electrode layer  172 P are stacked three times in the first region R 1  to have a third thickness T 3  that is three times the fifth thickness T 5 , and in the second region R 2 , the preliminary first electrode layer  172 P are stacked twice to have a fourth thickness T 4  that is twice the fifth thickness T 5 , and in the third region R 3 , the preliminary first electrode layer  172 P may be formed once to have the fifth thickness T 5 . 
     Next, the semiconductor device of  FIGS.  6 A and  6 B  may be manufactured by further performing the process described above with reference to  FIGS.  10 G and  10 H . According to this manufacturing method, by forming the first electrode layer  172  to have different thicknesses in different areas, the formation of the MBCFET™ devices having various threshold voltages may be facilitated without defects. 
     As set forth above, by including an air gap having a controlled size in the gate electrode, a semiconductor device having improved electrical characteristics and reliability may be provided. 
     While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.