Patent Publication Number: US-6340920-B1

Title: Low voltage low power crystal oscillator

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a crystal oscillator. More particularly, the present invention relates to a low voltage crystal oscillator configured with low power dissipation. 
     2. Description of the Related Art 
     There is shown in FIG. 1, a conventional Pierce-type oscillator having an input terminal XTAL-in, an output terminal XTAL-out, and an inverter  10  disposed therebetween. The inverter  10  is connected in parallel to a quartz crystal XTAL and a resistor R. The conventional oscillator pads on an integrated circuit (not shown in the drawing) by the input terminal XTAL-in and the output terminal XTAL-out. The inverter  10  includes a P-channel MOS transistor P 0  and an N-channel MOS transistor N 0 , both gates of which are connected to the input terminal XTAL-in. The P-channel transistor P 0  is configured with a source connected to a voltage source Vdd, and a drain tied to the drain of the N-channel transistor N 0  as the output terminal XTAL-out. The N-channel transistor N 0  has its source connected to ground. For parallel resonance, an input capacitor Cin and an output capacitor Cout are provided at the input terminal XTAL-in and the output terminal XTAL-out, respectively. 
     Power dissipated by the oscillator is proportional to three factors: operating frequency, capacitances of the capacitor Cin and Cout, and V 2  where V denotes the voltage across the quartz crystal XTAL. For minimizing the power dissipation, major design concern focuses on the voltage across the quartz crystal XTAL because the operating frequency and the capacitances are established. However, voltage swing at the output terminal XTAL-out of the conventional oscillator is Vdd so that the a great amount of power is dissipated thereby. 
     U.S. Pat. No. 5,486,795 discloses a low power crystal oscillator, an improvement of the conventional Pierce-type oscillator as shown in FIG.  2 . Such a low power crystal oscillator further includes a load device and a switch. The load device is constituted by a diode-connected N-channel MOS transistor N 1 , which is configured with a gate and a drain tied together to the voltage source Vdd, and a source connected to the source of the P-channel transistor P 0 . The switch can be a P-channel MOS transistor P 1  configured with a source connected to voltage source Vdd, a drain connected to the source of the P-channel transistor P 0 . The voltage at the gate of the transistor P 1  is set to “0” on powering up, and set from “0” to “1” by a delay device D 1  after a period of time is elapsed. 
     The improved crystal oscillator further includes a clamping device and another switch. The clamping device is constituted by a diode-connected P-channel MOS transistor P 2 , which is configured with a gate and a drain tied together to the ground, and a source connected to the source of the N-channel transistor N 0 . The other switch can be an N-channel MOS transistor N 2  configured with a source connected to the ground, a drain connected to the source of the N-channel transistor N 0 . The voltage at the gate of the transistor N 2  is set to “1” on powering on, and set from “1” to “0” by a delay device D 2  after a predetermined time is elapsed. 
     As above, the N-channel transistor N 1  and the P-channel transistor P 2  are diode-connected transistors for providing predetermined voltage drop, Vtn and |Vtp|, respectively. Thus, the voltage swing at the output terminal of the quartz crystal XTAL can be decreased to about Vdd-|Vtp|-Vtn and thus power dissipation can be reduced. However, because the load device and the clamping device is implemented by means of diode-connected transistor each having a constant voltage drop of about 0.6V˜0.7V. the voltage difference between nodes D and E remains at about 0.4V so that AC voltage gain is decreased when Vdd is about 1.8V. Therefore, such oscillators are not suitable for low voltage operation. 
     The same approach by diminishing the voltage swing at the output terminal of the quartz crystal to decrease power dissipation is also disclosed in U.S. Pat. No. 5,545,941, and thus encounters the same issues. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the present invention to provide a low voltage crystal oscillator which is configured with low power dissipation. 
     For attaining the above-identified object, the present invention provides an oscillator having an inverter, a quartz crystal, a voltage source, an upper clamper, a ground node, a lower clamper, and a feedback-controlled switch. The inverter are connected in parallel to the quartz crystal having a crystal input and a crystal output. The upper clamper is connected between the inverter and the voltage source. The lower clamper is connected between the inverter and the ground node. The feedback-controlled switch has a pair of switch control nodes connected to the crystal input, a switch input connected to the crystal output, and a switch output connected to the upper clamper and the lower clamper. The potential at the switch output is determined by voltage levels at the switch control nodes and the switch input in order to control the upper clamper and the lower damper while oscillating. 
    
    
     BRIEF DESCRIPTION OF DRAWING 
     The following detailed description, given by way of examples and not intended to limit the invention to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which: 
     FIG. 1 schematically depicts a circuit diagram of a conventional Pierce-type oscillator; 
     FIG. 2 schematically depicts a circuit diagram of the other conventional oscillator; 
     FIG. 3 schematically depicts a circuit diagram of a low voltage oscillator in accordance with one preferred embodiment of the present invention; and 
     FIG. 4 schematically depicts the circuit diagram of a low voltage oscillator in accordance with the other preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     According to the present invention, a low power oscillator, which is suitable for low voltage operation, is provided. The oscillator employs a feedback-controlled switch for controlling voltage swing at the output terminal of quartz crystal for the purposes of low voltage operation and low power dissipation. 
     With reference to FIG. 3, a circuit diagram of the low power oscillator in accordance with one preferred embodiment of the present invention is schematically illustrated. In the drawing, the same reference numerals are given for the same or similar elements as those depicted in FIG.  1  and FIG. 2, where threshold voltages of N-channel transistor and P-channel transistor are designated as Vtn and −Vtp, respectively. 
     The oscillator of the present embodiment includes an inverter  10 , a quartz crystal XTAL connected in parallel to the inverter  10 , a voltage source Vdd, a ground node, an upper clamper, a lower clamper, and a feedback-controlled switch. The feedback-controlled switch can be a CMOS transmission gate  20  having a P-channel transistor P 4  and an N-channel transistor N 4 . The feedback-controlled switch is provided with a pair of switch control terminals connected to an input terminal X 1  of the quartz crystal XTAL, a switch input terminal connected to an output terminal X 2  of the quartz crystal XTAL, and a switch output terminal connected to the upper clamper and the lower clamper. The upper clamper can be a P-channel transistor P 3 , which is configured with a source connected to the voltage source Vdd, a gate connected to the switch output terminal of the CMOS transmission gate  20 , and a drain connected to the source of the P-channel transistor P 0  in the inverter  10 . The lower clamper can be an N-channel transistor N 3  having a source connected to the ground node, a gate connected to the switch output terminal of the CMOS transmission gate  20 , and a drain connected to the source of the N-channel transistor N 3  in the inverter  10 . 
     Prior to oscillation, both of the input terminal X 1  and the output terminal X 2  are biased at about Vdd/2 so that the transistors P 3 , N 3 , P 0  and N 0  are turned on. During the oscillation period, the potential at the input terminal X 1  gradually decreases from Vdd/2, and the potential at the output terminal X 2  gradually increases from Vdd/2 such that source-to-gate potential Vsg 1  of the transistor P 4  increases. when Vsg 1  is greater than |Vtp|, the transistor P 4  is turned on so that the transistors P 3  and N 3  can be controlled by the drain voltage of the transistor P 4 . When the potential at the output terminal X 2  gradually increases to Vdd−|Vtp|, due to the conduction of the transistor P 4  the transmission gate  20  provides a voltage of Vdd−|Vtp| to the gates of the transistors P 3  and N 3  so that the transistor P 3  is turned off and transistor N 3  is turned on. When the potential at the input terminal X 1  gradually increases from logic low level , the gate-to-source potential of the transistor N 0  gradually increases. When the gate-to-source potential of the transistor N 0  is greater than threshold voltage Vtn, the transistor N 0  is turned on and the potential at the output terminal X 2  gradually decreases from logic high level. When the gate-to-source potential Vgs 2  of the transistor N 4  is greater than Vtn, the transistor N 4  is turned on and the gate potential of the transistor N 3  decreases in conjunction with that of the output terminal X 2 . When the potential at the output terminal X 2  gradually decreases to Vtn, due to the conduction of the transistor N 4  the transmission gate  20  provides a voltage of Vtn to the gate of the transistor N 3  so as to turn off the transistor N 3  and turn on the transistor P 3 . 
     With respect to the embodiment of FIG. 3, the voltage swing at the output terminal X 2  is about Vdd−|Vtp|-Vtn and thus power dissipation can be reduced efficiently. Furthermore, because this embodiment makes use of the upper clamper and the lower clamper, both being non-diode-connected, the oscillator is operable at an operating voltage less than 1.8V. Moreover, the upper clamper, the lower clamper and the inverter can be adjusted in dimension to increase the potential difference between the nodes D and E and thus increases AC voltage gain. 
     This circuit has been experimentally evaluated and it can operate properly as the supply voltage is scaled below 1.8V. 
     Referring to FIG. 4, a circuit diagram of a lower voltage oscillator in accordance with the other preferred embodiment of the present invention is schematically illustrated. 
     The oscillator of this embodiment includes an inverter  10 , a quartz crystal XTAL connected in parallel to the inverter  10 , a voltage source Vdd, a ground node, an upper clamper, a lower clamper, and a delay device. For example, the delay device can be a resistor or a CMOS transmission gate  30  as shown in FIG.  4 . The CMOS transmission gate  30  is provided with a pair of switch control terminals connected to voltage source Vdd and ground node, respectively. The CMOS transmission gate  30  has a delay input terminal connected to an output terminal X 2  of the quartz crystal XTAL, and a delay output terminal connected to the upper clamper and the lower clamper. The upper damper can be a P-channel transistor P 3 , which is configured with a source connected to the voltage source Vdd, a gate connected to the delay output terminal of the CMOS transmission gate  30 , and a drain connected to the source of the P-channel P 0  in the inverter  10 . The lower damper can be an N-channel transistor N 3  having a source connected to the ground node, a gate connected to the delay output terminal of the CMOS transmission gate  30 , and a drain connected to the source of the N-channel transistor N 0  in the inverter  10 . Thus, the potential at the delay output terminal is determined by that that of the delay input terminal for controlling the transistors P 3  and N 3 . 
     With respect to the embodiment of FIG. 4, the voltage swing at the output terminal X 2  can be reduced to about Vdd−|Vtp|−-Vtn and thus power dissipation thereof can be efficiently reduced. Moreover, the upper clamper, the lower damper and the inverter can be adjusted in dimension to increase the potential difference between the nodes D and E and thus increases AC voltage gain. 
     Moreover, though both the upper damper and the lower damper are provided in the embodiments as shown in FIGS. 3 and 4, the oscillator only configured with either the upper damper or the lower damper can be applicable and operable. 
     While the invention has been described with reference to various illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those person skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as may fall within the scope of the invention defined by the following claims and their equivalents.