Patent Publication Number: US-5257270-A

Title: Shift-correction code rate-enhancing parity encoding/decoding

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application contains subject matter related to U.S. application Ser. No. 07/433,877 filed Nov. 9, 1989 by Dennis G. Howe et al. and entitled: SHIFT CORRECTING CODE FOR CHANNEL ENCODED DATA, which is a continuation of U.S. application Ser. No. 07/200,166 now abandoned filed May 31, 1988 by the same inventors with the same assignee as the present application. 
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The invention is related to error correction systems and in particular to shift-error correction systems for channel-encoded data. 
     2. Background Art 
     Shift-correction codes (described in the above-referenced commonly assigned U.S. patent application) based on ternary block codes may be used to protect run-length-limited (RLL) binary data (channel data) against certain types of errors. During the encoding operation, the shift-error correction encoder will (i) represent a block of input (information) d,k-constrained channel data as a sequence of ternary symbols (or &#34;trits&#34;), (ii) calculate a (usually much shorter) sequence of parity trits which uniquely correspond to the information trit sequence, (iii) map (code) the parity trit sequence to a d,k-constrained binary sequence (i.e., transform the parity checks to channel data) that is appended to the original block of information channel data to form a channel data representation of a shift-correction codeword, and (iv) transmit such encoded data. One useful aspect of shift-correction coding of channel data (relative to coding on user data prior to modulating it to channel data) is that the rate of the channel data representation of a shift-correction code is somewhat higher than the rate of the ternary code on which the shift-correction code is based. This is due to the fact that, on average, the number of information channel bits represented by each information trit is larger than the number of channel bits needed to represent a parity trit. This illustrated by the following example: 
     In a maxentropic 2,7-constrained binary code there are, on average, 4.53 channel bits in each &#34;run&#34; (a run is comprised of a channel data &#34;one&#34; together with the number of contiguous channel data &#34;zeros&#34; that immediately follow it), while in a widely used (practical) 2,7 code there are an average of 4.42 channel bits per run. Since each shift-correction code information trit represents one information channel run, a codeword of a shift-correction code that is based on a (N,K) ternary block error correcting code will have an average of 4.42K channel bits in its information part (when the practical 2,7 modulation code is used). On the other hand, since each parity trit has only one of the three possible values, it is represented by one of the three shortest possible channel runs (which have lengths 3, 4, or 5 channel bits in the 2,7 modulation code of this example). Since each of the three possible parity trit values occur with equal probability, the average length of a parity channel run is four channel bits. Therefore, the rate of the channel data representation of the shift-correction codeword (based on the (N,K) ternary code) is 
     
         R.sub.scc =4.42K/(4.42K+4(N-K))                            (1) 
    
     while the rate of the base code is 
     
         R.sub.B =K/N.                                              (2) 
    
     The shift-correction code thus enjoys a rate advantage of 
     
         ΔR=R.sub.scc /RB=4.42/(4+0.42R.sub.B)&gt;1              (3) 
    
     so that, in our example, rate increases exceeding 5% are possible, depending on R B . 
     The rate increase ΔR can be enhanced (made larger) if the overall number of channel bits needed to represent the shift-correction code&#39;s parity trits can be reduced further. One method of accomplishing this is to reduce the number of parity channel data runs that are required, i.e., to map (code) more than one parity trit per channel run. Doing this, however, is complicated by the fact that error multiplication must be avoided when received channel data is decoded back to parity trits, i.e., our mapping must be such that if any received channel data sequence suffers t shift-errors (a shift-error changes the decimal value of a run by ±1) the sequence of trits obtained via decoding of the erroneous channel data will contain at most t incorrect trits. A trit to d,k-constrained binary code that obeys this last condition is said to obey the &#34;shift-error condition&#34;. We note that the trit to d,k-constrained binary mapping used in the parent application obeys the shift-error condition, but it maps each parity trit to a single channel run. If the shift-error condition is not obeyed, a channel data shift-error will cause more than one shift-correction code symbol (i.e., trit) to be erroneous and the shift-correction code&#39;s performance (i.e., its shift-error correcting capability) will be seriously degraded. 
     DISCLOSURE OF THE INVENTION 
     We shall first describe a shift-error condition compliant method of coding/decoding two trits (i.e., a &#34;trit pair&#34;) per run of d,k-constrained binary data. The encoding scheme is based on (i) grey coding pairs of trits and (ii) assigning each grey-coded trit pair to a single unique channel run. This is illustrated in Table I, which has the grey-coded trit pairs listed in its first column and numerals R 0 , R 1 , R 2 , . . . , R 8  to which those trit pairs are mapped in its third column. Each of the numbers R j  is associated via a technique taught in the above-referenced commonly assigned application with a unique run of channel data that is transmitted. (This technique of transforming the R j  to channel data runs will be reviewed in the detailed description of the invention which follows.) This latter transformation (i.e., the transformation of R j  to a unique channel data run) provides that a shift-error which occurs in the channel data associated with some sequence of the R j  will alter the value by ±1 of only one of the R.sub. j recovered via the inverse of the transformation. 
     More specifically, if the sequence of channel data that represents a sequence (R j ) suffers shift-errors, each shift-error can change only one of the recovered R j  values to either of the nearest values R j-1  or R j  +1 (we note that the R j  are cyclic with respect to this, i.e., a shift-error that effects R 0  may change it to either R 8  or R 1  and similarly R 8  may become R 7  or R 0 ) Thus, from Table I we can see that when a sequence of numerals R j  which is corrupted by one shift-error is decoded back to the sequence of parity trit pairs, the resulting trit sequence will have only one erroneous trit, i.e., the shift-error condition is obeyed. 
     In order to practice this method of coding/decoding two trits per run, the d,k-constrained channel code must provide at least nine unique runs, i.e., it must have (k -d)≧8. Thus for example this method could be used with 2,10 or 3,11 RLL channel codes, but not with 1,7 or 2,7 RLL channel codes. 
     The rate of a shift-correction code that is based on an (N,K) block ternary code, when using the referenced application&#39;s method of coding parity trits to channel data (one trit per run of average length d+2) is given by ##EQU1## where L 1  =average number of channel bits per run for the d,k-constrained channel code used, 
     N=total number of symbols (trits) per (N,K) base code codeword, 
     K=number of information symbols (trits) per (N,K) base code codeword. 
     Using the trit pair to RLL binary code described in Table I to map parity trits to channel data, this same shift-correction code would have rate (here a pair of parity trits is mapped to one of nine runs having average length d+5 channel bits) ##EQU2## 
     Thus, practicing the invention results in a shift-correction code rate enhancement (increase) of ##EQU3## which, for example, when d=2 and L 1  =4.64 (as would occur for an efficient 2,10 RLL code) has value ΔR&#39;&gt;1.06 as (N-K)/K approaches 1. Thus, if 2,10 RLL modulation code (or any d=2 RLL code having (k-d)≧8) is used, shift-correction code rate increases of 6 percent or more are possible via the invention. Even larger rate increases are achievable when RLL modulation codes with d&gt;2 are used. 
     We shall now consider a shift-error condition compliant method of coding/decoding three trits per two runs of d,k-constrained binary data. This method will be useful with d,k-constrained channel data that has only six unique run lengths, i.e., when (k-d)≧5 (thus, this method can be used with both 1,7 and 2,7 RLL modulation codes). The method consists of (i) grey coding triples of trits and (ii) assigning each such grey coded trit triple to a unique pair of d,k-constrained channel data runs. This process is illustrated in Table IV, where the twenty-seven possible trit triples are laid out as a two dimensional matrix (ignore, for the moment, the nine triples contained in the boxes at the intersections of rows 2, 4, 6 and columns 2, 4, 6 of Table IV). The first and second of the pair of run numerals P j , S k  (j=0,1, . . . 5 and k=0,1, . . . , 5) to which the triples are assigned are listed at the left of each matrix row and at the head of each matrix column respectively. Coding is done by locating the input trit triple in the matrix and assigning to it the P j , S k  values that identify the row/column location of the input triple in the Table IV matrix. The sequence of numeral pairs {P j , S k  } which is obtained from the input sequence of trits is then transformed to a sequence of run pairs via the technique taught in the above-referenced application. This process provides that a shift-error that occurs in the channel data associated with the numeral pair sequence {P j , S k ) will alter by ±1 only one of the P j  or S k  that are recovered via the inverse of the process (both the P j  and S k  are cyclic with respect to such alterations). 
     Inspection of Table IV shows that if the value of one of the received pair of run numerals is cyclically shifted (i.e., its value is changed to that of either of its cyclic neighbors), the decoded trit triple will be erroneous in only one of its three elements. This is true even if one of the run numeral pairs not used by the encoder (e.g., P 1 , S 1 ) is received, provided that we decode such illegal received run numeral pairs into the trit triples shown at the corresponding locations (the trit triples contained in the small boxes) in Table IV. Thus, this trit triple to RLL run pair coding/decoding process obeys the shift-error condition. 
     Since all twenty-seven possible parity trit triples occur with equal probability, the rate of this trit triple to run pair code can be shown to be 3 trits per 2(d+3.333) channel bits; the average rate of an (N,K) block code based shift-correction coder that uses this method of mapping parity trits to d,k-constrained channel data is ##EQU4## 
     Finally, if the (N,K) base code on which the shift-correction code is based has a number of parity checks that is not divisible by two (in the case when (k-d)≧8), or three (in the case when 8&gt;(k-d)≧5), we must input one (or two) additional &#34;dummy&#34; or &#34;padding&#34; trits into the trit pair to single run encoder (or into the trit triple to run pair encoder) to cause a complete decodable codeword to be produced. Highest code rate can be achieved by computing the padding trit values to be such that the shortest possible last run (or run pair) is produced by the encoder. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is described below in detail by reference to the accompanying drawings, of which: 
     FIG. 1 is a block diagram of a system which employs shift-correction coding/decoding; 
     FIG. 2 is a block diagram illustrating the operation of the shift-correction code encoder of the system of FIG. 1; 
     FIG. 3 is a block diagram illustrating the operation of the shift-correction code decoder of the system of FIG. 1; 
     FIG. 4 is a logic circuit diagram illustrating a trit pair to runlength encoder of the present invention; 
     FIG. 5 is a logic circuit diagram illustrating a trit pair to runlength decoder of the present invention; 
     FIG. 6 is a logic circuit diagram illustrating a trit-triple to runlength pair encoder of the present invention; and 
     FIG. 7 is a logic diagram illustrating a trit-triple to runlength pair decoder of the present invention. 
    
    
     MODES FOR CARRYING OUT THE INVENTION 
     We shall illustrate the use of trit pair to single run encoding/decoding to encode/decode the parity checks of a shift-correcting modulation code that is based on a shortened m=3 ternary BCH error correcting code (we assume use of a d=2 RLL modulation code that obeys (k-d) ≧8). First, however, to augment the clarity of the illustration we shall review the shift-correction coding/decoding method taught in the above-referenced commonly assigned patent application. The various tables referred to hereinafter are given at the conclusion of the specification. 
     Review of Shift Correction Coding/Decoding 
     Referring to FIG. 1, data from an information source 1 is encoded by a modulation or channel encoder 2 in accordance with an RLL (d,k) code for transmission as &#34;message&#34; data through a channel 4 (such as an optical disk data storage system, for example). However, as described in the above-referenced parent application, shift-correction encoder 6 (also referred to herein as an error correcting modulation (ECM) encoder) sections the message data into blocks and computes a &#34;check&#34; block of redundant data from each &#34;message&#34; block and appends the check block to its corresponding message block prior to transmission through the channel 4. The data is retrieved from the channel 4 (for example, by playing back recorded data from an optical disk data storage system) by first decoding it in a shift-correction decoder 8 (also referred to herein as an (ECM) decoder). The ECM decoder 8 detects and may correct (in the case of error correction) errors in the message block of RLL encoded data and then transmits the corrected message block to a modulation or channel decoder 10. The channel decoder 10 transforms the RLL channel data into binary data and transmits the binary data to a data sink 12. 
     Since the ECM code&#39;s basecode is a ternary BCH code with m=3, its natural length is N=3 m  -1=26 trits. The ternary polynomial 
     
         p(X)=X.sup.3 -X+1                                          (8) 
    
     is irreducible and primitive, hence the polynomial 
     
         g(X)=(X-1)p(X)=X.sup.4 X.sup.3 -X.sup.2 X-1                (9) 
    
     generates a (26,22) single-error-correcting (T=1) ternary BCH code. A tutorial example will now be given using g(X) of equation (9). To simplify our exposition we shorten this code to a (8,4) ternary BCH having T=1. 
     Review of Shift-Correction Encoding 
     Shift-correction encoding will now be briefly reviewed in connection with the present example by reference to FIG. 2 which illustrates the operation of the encoder 6 of FIG. 1. To perform shift-correction encoding, we start by taking in K information channel runs (Block 30 of FIG. 2). In our example K=4, and we will suppose that the input information runs are given by the 4-tuple 
     
         {X.sub.i }={X.sub.0, X.sub.1, X.sub.2, X.sub.3 }=(4,5,6,7).(10) 
    
     Using the relation S i  ={X 0  +X 1  +. . . +X i ) we obtain the corresponding S-vector (Block 32 of FIG. 2) 
     
         {S.sub.i }={S.sub.0, S.sub.1, S.sub.2, S.sub.3 }={4,9,15,22}(11) 
    
     and reducing the S i  modulo 3 (Block 34 of FIG. 2), the corresponding t-vector 
     
         {t.sub.i }={1,0,0,1}.                                      (12) 
    
     Thus, the shift-correction codeword&#39;s information-part polynomial is (Block 36 of FIG. 2) 
     
         d(X)=X.sup.4 +1≡C.sub.m (X),                         (13) 
    
     and the four parity check trits are (Block 38 of FIG. 2) the ternary coefficients of 
     
         r(X)=-rem [X.sup.4 d(X)/g(X)]=-X.sup.3 -X.sup.2 -X+1. 
    
     That is, the parity vector is 
     
         {p.sub.i }={-1, -1, -1, +1}                                (14) 
    
     and the complete logical shift-correction codeword is 
     
         {C.sub.i }={t.sub.i }+{p.sub.i }={1,0,0,1,-1,-1,-1,+1).    (15) 
    
     The entire logical codeword of equation (15) must be converted to d,k-constrained binary data before it can be transmitted through the channel. The information part {t i  } of equation (15) already has such a representation, viz., the input channel data that corresponds to the runs {X i  } of equation (10). The parity symbols {p i  } given by equation (14), however, exist at this point only as logical quantities. It is the coding (and subsequent decoding) of the sequence {p i  } to a d,k-constrained binary sequence that is the subject of the present invention. 
     In the method of accomplishing this latter coding described in the referenced commonly assigned application the elements p i  are effectively treated as modulo 3 reductions of S-vector elements which correspond to the parity part of the shift-correction codeword. Thus, the logical S-vector that corresponds to the entire codeword is obtained by extending equation (11) to produce 
     
         {S&#39;.sub.i }={4,9,15,22,-1,-1,-1,1}.                        (16) 
    
     This vector is then transformed into a corresponding channel run vector {X&#39; i  } (Block 40 of FIG. 2) using the inverse of the transformation used to obtain equation (11) from equation (10), i.e., using ##EQU5## Carrying out this process we obtain {from equation (16)} 
     
         {X&#39;.sub.i }={4,5,6,7,-23,0,0,2}.                           (18) 
    
     This vector is then converted to a (d,k) constrained binary channel run vector (Block 42 of FIG. 2) by adjusting the elements of {X&#39; i  } by adding appropriate multiples of d+1 (where d is the d-constraint of the modulation code being used) to the last four elements of {X&#39; i  } (i.e., the elements corresponding to the parity checks) so that all the elements of the vector of equation (18) will be positive and as small as possible without violating the RLL code&#39;s d-constraint. The result of doing this is (since d=2) 
     
         {X&#34;.sub.i }={4,5,6,7,4,3,3,5},                             (19) 
    
     The final values of each of the last four elements of equation (19) will thus be either d+1, d+2, or d+3. These elements are then converted to a RLL binary sequence (Block 43 of FIG. 2) and combined with the message channel bits (under control of a switch 44 of FIG. 2) to form the channel data representation 45 of FIG. 2 of the entire shift-correction codeword that is transmitted through the channel. 
     Review of Shift-Correction Decoding 
     Shift-correction decoding will now be reviewed in connection with the present example by reference to FIG. 3, which illustrates the operation of the decoder 8 of FIG. 1. Suppose now, that during transmission (recording and playback) a left-wise shift-error occurs at the fifth channel &#34;one&#34; of the codeword of equation (19). The received codeword will then be represented by the channel run sequence 
     
         {X.sub.i }={4,5,6,e,uns/6/ ,e,uns/5/ ,3,3,5},              (20) 
    
     (received at Block 58) where the underlined runs are the ones effected by the shift-error. Following the decoding method of the above-referenced application, we next obtain the logical ternary symbol form of the received shift-correction codeword by first calculating the received S-vector {S i  } from equation (20) using S i  =X 0  +X 1  . . . +X i  (Block 60 of FIG. 3) to obtain 
     
         {S.sub.i }={4,9,15,21,26,29,32,37}                         (21) 
    
     and then reducing each element modulo 3 to obtain the received logical codeword (also Block 60 of FIG. 3) 
     
         {C.sub.i }={1,0,0,0,-1,-1,-1,1}                            (22) 
    
     Comparing vector (22) with the transmitted codeword vector (15) we see that these differ (under modulo 3 addition) by the error vector 
     
         {e.sub.i }={C.sub.i }-{C.sub.i }={0,0,0,-1,0,0,0,0}        (23) 
    
     which corresponds to the single error event which one unit decrement of the fourth run, or equivalently, a left-shift of the fifth channel &#34;one&#34;. That is, once the error vector (23) is obtained (Block 66 of FIG. 3), modulo 3 subtraction of it from the received logical codeword vector (22) produces the correct codeword vector (15) (Block 68 of FIG. 3). We note that this {e i  }, which we deduced here via inspection, would in practice be computed via the algorithm used to decode the ternary (8,4) BCH codeword of equation (22) (or by table look up base on the syndrome computed in Block 64 of FIG. 3). 
     Once the error vector of equation (23) is obtained, error correction is accomplished by incrementing the fourth received run by one, and decrementing the fifth received run by one, i.e., by right shifting the fifth received channel &#34;one&#34;. Finally, the message runs of the corrected codeword are transformed to binary RLL channel data and sent to the RLL decoder (Block 80 of FIG. 3). 
     Trit Pair to Single Runlength Coding/Decoding 
     We now describe the use of the trit pair to runlength coding/decoding of the present invention to code/decode the parity trits of the above example. This corresponds to the encoding operation of Blocks 40 and 42 of FIG. 2 and the treatment of parity runs by the decoding operation of Block 60 of FIG. 3. The parity check sequence {p i  } of equation (14) is first calculated in the normal way. Next, adjacent p i  elements are formed into a sequence of pairs and runlength numerals R j  are assigned to them according to Table I. Thus the {p i  } given as by equation (14) would become 
     
         {p.sub.i }={(-1,-1), (-1,1)}={7,6}                         (24) 
    
     where {7,6}={R 7 ,R 6  } as shown in Table I. 
     The complete logical shift-correction codeword, which is analogous to equation (15), is then 
     
         {C.sub.i }={t.sub.i }+{p.sub.i }={1,0,0,1,7,6}             (25) 
    
     In order to convert the codeword of equation (25) to d,k-constrained binary data, we take its last two elements (i.e., the parity symbols) to be modulo 9 reductions of the S-vector elements which correspond to the parity part of the shift-correction codeword. The S-vector that corresponds to the entire codeword of equation (25) is therefore obtained by extending equation (11) to produce 
     
         {S&#39;.sub.i }={4,9,15,22,7,6}                                (26) 
    
     and the corresponding unadjusted run vector is (using equations (17)): 
     
         {X&#39;.sub.i }={4,5,6,7,-15,-1}                               (27) 
    
     We now adjust equation (27) by adding multiples of nine to the last two elements until we obtain the smallest positive values that obey the d,k-constraints of the RLL code (recall that we have assumed d=2 and (k-d) ≧8). Carrying out this process yields 
     
         {X.sub.i }={4,5,6,7,3,8},                                  (28) 
    
     which is the channel data run representation of the entire shift-correction codeword that is transmitted through the channel. 
     Suppose now, that during transmission (recording and playback) a left-wise shift-error occurs (as before) at the fifth channel &#34;one&#34; of the codeword of equation (28). The received codeword will then have the channel run representation 
     
         {X.sub.i }={4,5,6,6,4,8}                                   (29) 
    
     where the underlined runs are those effected by the shift-error. We start to decode as taught in the above-referenced application, i.e., we construct a received S-vector in the normal way, obtaining 
     
         {S.sub.i }={4,9,15,21,25,33}                               (30) 
    
     and then reduce the information runs (the first four elements of equation (30)) modulo 3 and reduce the parity runs (the last two elements of equation (30)) modulo 9 to produce the received logical codeword 
     
         {C.sub.i }={1,0,0,0,7,6,}.                                 (31) 
    
     The received codeword of equation (31) differs (under modulo 3 and modulo 9 addition for the information and parity parts of the sequence respectively) from the transmitted word of equation (25) by 
     
         {e.sub.i }={C.sub.i }-{C.sub.i }={0,0,0,-1,0,0}            (32) 
    
     which completely (as before) specifies the shift-error that occurred. 
     Although the preceding discussion illustrated the application of the trit pair to runlength coding/decoding method to a shift-error correction coding system, it did not demonstrate how the trit pair to runlength code prevents error multiplication (because the shift-error event used in our example did not alter either of the two parity checks of equation (24)). We will therefore illustrate the new system&#39;s maintenance of the shift-error condition in the following extension of our example. 
     Suppose the codeword of equation (25) having the channel run representation of equation (28) is transmitted and a right-shift error occurs at the sixth channel &#34;one&#34;, so that the received channel run representation of the codeword is 
     
         {X.sub.i }={4,5,6,7,4,7}                                   (33) 
    
     where the underlined runs are those affected by the shift-error. The corresponding {S i  } and {C i  } vectors are thus 
     
         {S.sub.i }={4,9,15,22,26,33,}                              (34) 
    
     
         and 
    
     
         {C.sub.i }={1,0,0,1,8,6},                                  (35) 
    
     where the last two elements of equation (35) are the run numerals assigned to the two pairs of parity trits. Comparison of equations (35) and (31) shows that only one of the run numerals has been altered by the shift-error, and that it has been changed by only +1. Reference to Table I shows that the received run numerals decode as 
     
         {8,6}={(-1,0), (-1,1)}={-1,0,-1,1}                         (36) 
    
     and comparison of equation (36) with equation (24) shows that only one parity trit was changed by the shift error. 
     Once the shift-correction codeword&#39;s parity trits are obtained from the received runlength numerals via a trit pair to runlength decoder that implements the decoding specified in Table I, the shift-correction decoder can decode the shift-correction codeword in the normal way. This completes our example illustration. 
     Trit Pair to Runlength Encoder/Decoder Operation 
     The trit pair to runlength encoder is a combinatorial logic circuit that has as its input a pair of trits (ternary digits) and has as its output the runlength number, an integer from zero to eight, defined modulo 9. Encoding of an input trit pair is done by finding that trit pair in the trit pair column of Table I; the output is the corresponding runlength numeral in the third column. Decoding is done in an analogous fashion. 
     Trit Pair to Runlength Encoder Circuitry 
     The operations depicted by Blocks 40 and 42 of FIG. 2 are performed in a first embodiment of the present invention by the trit pair encoder 104 of FIG. 4. The inputs 100, 102 to the trit pair encoder 104 of FIG. 4 comprise the trit pair AB where A=a 1  a 2  and B=b 1  b 2 , i.e., the trit values 0,1, and 2 are represented by the bit pairs 00, 01, and 10 respectively. The first stage 106 of the encoder 104 has AND gates 108-116 receiving respective pairs of inputs a 1 , a 2 , b 1 , b 2 . The AND gates 108-116 of the first stage 106 implement the Boolean equations in the first column of Table II to generate outputs R j  for j=1, . . . ,8. All R j  produced by the first stage 106 are zero except the one in the same row of Table I as the corresponding values of a 1  a 2  b 1  b 2  (i.e., the R j  output by 106 have binary values; one of the R j  will have value one and all others have value zero). 
     The second stage 118 of the encoder 104 receives as its four inputs 120-123 respective combinations of the binary values of R j  from the first stage 106 for 0≦j≦8. The inputs are transformed by respective OR gates 124-126 to a four bit output R. The second stage 118 implements the Boolean equations of the right-hand column of Table II. Only one R j  can be equal to one. For the one R j  =1, the output r 1  r 2  r 3  r 4  occurs is the one that appears in the same row of Table I as does the non-zero R j . In fact, the output r 1  r 2  r 3  r 4  that occurs in the binary representation of the index j of the non-zero R j . 
     Runlength To Trit Pair Decoder Circuitry 
     The operation depicted by Block 60 of FIG. 3 is performed in the first embodiment of the present invention by the trit pair decoder 130 of FIG. 5. The input 128 to the decoder 130 of FIG. 5 is R, the binary representation of the runlength, namely the four bits r 1  r 2  r 3  r 4 . The first stage 132 of the decoder 130 has AND gates 134-142 generating from the four-bit input R the outputs R j , where j=0, . . . ,8 and only one of the R j  equals one (all the other being zero), as discussed above with regard to the encoder 104. The AND gates 134-142 of the second stage 132 implement the Boolean equations in the left column of Table III. The second stage 144 of the decoder 130 has OR gates 146-149 receiving respective combinations of the R j  from the first stage 132. The second stage generates therefrom the trit pair A=a 1  a 2  and B=b 1  b 2  by implementing the Boolean equations in the right column of Table III. As before, only one of the R j  equals one. Again, the rule is that R j  equals 1 if and only if the current values of a 1  a 2  b 1  b 2  and j appear on the same row of Table I. 
     Trit Triple To Runlength Pair Coding/Decoding 
     The trit triple to runlength pair encoder is a combinatorial logic circuit that has as its input a triple of trits (ternary digits) having values either 0,1  or 2 and has as its output a pair of numbers, the runlength numerals. The runlength numerals are integers from zero to five, defined modulo six. 
     Encoding is done according to the trit triple to run pair encoding/decoding table (Table IV). Each of the 27 possible trit triples appears exactly once in Table IV, as a triple not contained in a smaller box. (The nine triples in the smaller boxes of Table IV are used for decoding). 
     Encoding is done by locating the input trit triples (ignoring those lying in the smaller boxes) in Table IV; the first output run numeral is the one associated with the row in which the input trit triple is located, and the second output run numeral is associated with the corresponding column. 
     Decoding is done in a similar fashion. A pair of received runs determines uniquely a row and column in Table IV and this row and column determines a trit triple. 
     The encoding/decoding table (Table IV) has the following important property, which we call &#34;the shift-error property&#34;: Triples of trits in adjacent locations of Table IV differ in exactly one element. 
     Trit Triple To Run Length Pair Encoder Circuitry 
     In a second embodiment of the present invention, the encoding operations of Blocks 40 and 42 of FIG. 2 are performed by the trit triple encoder of FIG. 6. The input 150 to the encoder 152 of FIG. 6 is the trit triple ABC where A=a 1  a 2 , B=b 1  b 2  and C=c 1  c 2 , i.e., the individual trits of value 0, 1, or 2 are represented by the bit pairs 00, 01, and 10 respectively. 
     The first stage 154 of the encoder 152 has three logic elements 154a, 154b, 154c which convert the input bit pairs of the three trits A, B, C to nine outputs X i  where i=0, 1, or 2 and X is one of A, B, or C. The logic element 154a implements the Boolean equations in the left column of the first three rows of Table V. The logic element 154b implements the Boolean equations in the middle column of the first three rows of Table V. The logic element 154c implements the Boolean equations in the right column of the first three rows of Table V. Exactly three of the X i  have value one (all the others being zero) and these three X i  correspond to the input triple ABC. For example, if the triple trit 012 is the received input, the three non-zero X i  are A 0 , B 1  and C 2 . 
     The second stage 156 of the encoder 152 has inputs X i , where X is one of A, B, or C and i=0, 1, or 2, and outputs Y j  where Y is one of R or S and j=0, . . . ,5. In accordance with Table IV, the output R j  equals one if and only if the input trit triple ABC lies in an unboxed location of the j th  row of Table IV and the output S j  equals one if and only if the input trit triple ABC lies in an unboxed location in the j th  column of Table IV. 
     Logic elements 156a-156f implement the Boolean equations in the fourth through ninth rows of Table V to generate the outputs Y j . The logic element 156a is typical and has three AND gates 158-160 each receiving a certain pair of the inputs X i  as indicated in the drawing of FIG. 6. An OR gate 162 receives the outputs of the three AND gates 158-160. Two AND gates 164, 166 each receives the output of the OR gate 162 and certain one of the inputs X i , as indicated in the drawing of FIG. 6. The outputs of the two AND gates 164, 166 are two of the outputs Y j . 
     The third stage 168 of the encoder 152 has as inputs R 0 , . . . R 5 , S 0 , . . . ,S 5  and outputs the pair of binary triples R=r 1  r 2  r 3  and S=s 1  s 2  s 3 . Only one R 0 , . . . R 5  can equal one, all the others being zero. And, r 1  r 2  r 3  is the binary representation of the index j of the non-zero R j . Similarly, exactly one of S 0 , . . . S 5  equals one and s 1  s 2  s 3  is the binary representation of the index j of the non-zero S j . 
     The third stage 168 has a first set of three OR gates 170-172 each receiving a certain combination of the inputs R 0 , . . . R 5  and whose outputs are the three bits of the output R defined in Table V. The OR gates 170-172 implement the Boolean equations in the left column of the bottom three rows of Table V. The third stage also has a second set of three OR gates 174-176 each receiving a certain combination of the inputs S 0 , . . . S 5  and whose outputs are the three bits of the output S defined in Table V. The OR gates 174-176 implement the Boolean equations in the right column of the bottom three rows of Table V. 
     We note that this encoder will never output run numeral pairs that correspond to the rows and columns of the trit triples contained in the small boxes in Table IV (such trit triples are always encoded as the pair of run numerals corresponding to the next smaller row and column, i.e., they will be represented by a shorter length channel bit sequence.) 
     Runlength Pair To Trit Triple Decoder Circuitry 
     In the second embodiment of the invention, the decoding operation of Block 60 of FIG. 3 is performed by the trit triple decoder 178 of FIG. 7. The input to the decoder 178 of FIG. 7 is the run numeral pair RS, where R =r 1  r 2  r 3  and S=s 1  s 2  s 3  each have one of the values 0, 1, . . . , 5 represented by the bit triples 000, 001, 010, 011, 100, and 101 respectively. 
     The first stage 180 of the decoder 178 has twelve outputs X i  where i=0,1,2,3,4 or 5 and X is one of R or S. Exactly two of these X i  will have value one and the rest zero. X i  equals one if only if one of the decoder&#39;s input binary triples r 1  r 2  r 3  or s 1  s 2  s 3  is the binary representation of i, for i=0, . . . , 5. 
     The first stage has a first set of six AND gates 182-187 whose inputs are the r 1  r 2  r 3 , different ones of which are inverted at the inputs of different ones of the AND gates 182-187 as indicated in the drawing of FIG. 7. The AND gates 182-187 implement the equations in the left column of the first six rows of Table VI to generate the R 0 , . . . , R 5 . The first stage also has a second set of six AND gates 188-193 whose inputs are the s 1  s 2  s 3 , different ones of which are inverted at the inputs of different ones of the AND gates 188-193 as indicated in the drawing of FIG. 7. The AND gates 188-193 implement the equations in the right column of the first six rows of Table VI to generate the S 0 , . . . , S 5 . 
     The second stage 194 of the decoder 178 has inputs X i  where X equals R or S and i=0, . . . , 5 and outputs Y j  where Y is one of A,B, or C and j=1 or 2. The second stage 194 has OR gates 196-199 each receiving a different pair of the inputs X i  as indicated in the drawings and implement the Boolean equations in the seventh and eighth rows of Table VI. The remaining pairs of the inputs X i  are received by different ones of OR gates 200-205 in the second stage 194. A set of three AND gates 206-208 receiving different combinations of the outputs of the OR gates 200-205 together with an OR gate 210 implement the Boolean equation of the ninth row of Table VI. A set of three AND gates 212-214 receiving different combinations of the outputs of the OR gates 200-205 together With an OR gate 216 implement the Boolean equation of the tenth row of Table VI. 
     The third stage 218 is simply a set of wired OR gates 220, 222, 224 which implement the simple Boolean equations of the bottom two rows of Table VI. The third stage 218 has as inputs A 1 , A 2 , B 1 , B 2 , C 1 , C 2 , and outputs the triple of binary pairs (a 1 , a 2 ), (b 1 , b 2 ), (c 1 , c 2 ) which are the binary representations of the (decoded) trit triple ABC. 
     Finally, we note that if one of the two received run numerals that are input to the FIG. 4 decoder is incorrect by one decimal unit, the decoder will output a trit triple that has only one of its three elements incorrect, even if one of the illegal run pairs (i.e., one of the run pairs not used by the encoder) is received (since such illegal run pairs correspond to the Table IV rows and columns containing the small boxes, and the decoder decodes such illegal run pairs to the trit triple values contained in the respective box). 
     
                       TABLE I
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TRIT PAIR TO RUNLENGTH
CODING/DECODING TABLE
      BINARY                    BINARY
      REPRESENTA-               REPRESENTA-
TRIT  TION OF      RUNLENGTH    TION
PAIR  A B          NUMERAL      of R.sub.j
A   B          a.sub.1 a.sub.2
                    b.sub.1 b.sub.2
                           R.sub.j    r.sub.1 r.sub.2 r.sub.3 r.sub.4
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0   0          00   00     R.sub.0 = 0
                                      0 0 0 0
0   1          00   01     R.sub.1 = 1
                                      0 0 0 1
0   2          00   10     R.sub.2 = 2
                                      0 0 1 0
1   2          01   10     R.sub.3 = 3
                                      0 0 1 1
1   0          01   00     R.sub.4 = 4
                                      0 1 0 0
1   1          01   01     R.sub.5 = 5
                                      0 1 0 1
2   1          10   01     R.sub.6 = 6
                                      0 1 1 0
2   2          10   10     R.sub.7 = 7
                                      0 1 1 1
2   0          10   00     R.sub. 8 = 8
                                      1 0 0 0
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                       TABLE II
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BOOLEAN ALGEBRA EQUATIONS FOR
TRIT PAIR TO RUNLENGTH ENCODER
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R.sub.0 = a.sub.1 a.sub.2 b.sub.1 b.sub.2
                 r.sub.1 = R.sub.8
R.sub.1 = a.sub.1 a.sub.2 b.sub.2
                 r.sub.2 = R.sub.4 + R.sub.5 + R.sub.6 + R.sub.7
R.sub.2 = a.sub.1 a.sub.2 b.sub.1
                 r.sub.3 = R.sub.2 + R.sub.3 + R.sub.6 + R.sub.7
R.sub.3 = a.sub.2 b.sub.1
                 r.sub.4 = R.sub.1 + R.sub.3 + R.sub.5 + R.sub.7
R.sub.4 = a.sub.2 b.sub.1 b.sub.2
R.sub.5 = a.sub.2 b.sub.2
R.sub.6 = a.sub.1 b.sub.2
R.sub.7 = a.sub.1 b.sub.1
R.sub.8 = a.sub.1 b.sub.1 b.sub.2
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                       TABLE III
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BOOLEAN ALGEBRA EQUATIONS
RUNLENGTH TO TRIT PAIR DECODER
______________________________________
R.sub.0 = r.sub.1 r.sub.2 r.sub.3 r.sub.4
                  A.sub.1 = R.sub.3 + R.sub.4 + R.sub.5
R.sub.1 = r.sub.2 r.sub.3 r.sub.4
                  A.sub.2 = R.sub.6 + R.sub.7 + R.sub.8
R.sub.2 = r.sub.2 r.sub.3 r.sub.4
                  B.sub.1 = R.sub.1 + R.sub.5 + R.sub.6
R.sub.3 = r.sub.2 r.sub.3 r.sub.4
                  B.sub.2 = R.sub.2 + R.sub.3 + R.sub.7
R.sub.4 = r.sub.2 r.sub.3 r.sub.4
R.sub.5 = r.sub.2 r.sub.3 r.sub.4
                  a.sub.1 = A.sub.2  b.sub.1 = B.sub.2
R.sub.6 = r.sub.2 r.sub.3 r.sub.4
                  a.sub.2 = A.sub.1  b.sub.2 = B.sub.1
R.sub.7 = r.sub. 2 r.sub.3 r.sub.4
R.sub.8 = r.sub.1
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                                           TABLE IV
__________________________________________________________________________
TRIT TRIPLE - RUN LENGTH PAIR ENCODING/DECODING
TABLE
__________________________________________________________________________
        SECOND RUN NUMERAL, S.sub.k
FIRST RUN NUMERAL R.sub.j
         ##STR1##
 R.sub.0 = 0 R.sub.1 = 1 R.sub.2 = 2
         ##STR2##
 R.sub.3 = 3 R.sub.4 = 4 R.sub.5 = 5
         ##STR3##
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                       TABLE V
______________________________________
BOOLEAN ALGEBRA
TRIT TRIPLE TO RUNLENGTH PAIR ENCODER
______________________________________
A.sub.0 = a.sub.1 a.sub.2
              B.sub.0 = b.sub.1 b.sub.2
                           C.sub.0 = c.sub.1 c.sub.2
A.sub.1 = a.sub.2
              B.sub.1 = b.sub.2
                           C.sub.1 = c.sub.2
A.sub.2 = a.sub.1
              B.sub.2 = b.sub.1
                           C.sub.2 = c.sub.1
R.sub.0 =         S.sub.0 =
A.sub.0 · (B.sub.0 C.sub.2 + B.sub.1 C.sub.0 + B.sub.2 C.sub.1)
                  B.sub.0 · (A.sub.0 C.sub.1 + A.sub.1 C.sub.0 +
                  A.sub.2 C.sub.2)
R.sub.1 =         S.sub.1 =
A.sub.0 · (B.sub.0 C.sub.2 + B.sub.1 C.sub.0 + B.sub.2 C.sub.1)
                  B.sub.0 · (A.sub.0 C.sub.1 + A.sub.1 C.sub.0 +
                  A.sub.2 C.sub.2)
R.sub.2 =         S.sub.2 =
A.sub.1 · (B.sub.0 C.sub.1 + B.sub.1 C.sub.2 + B.sub.2 C.sub.0)
                  B.sub.1 · (A.sub.0 C.sub.2 + A.sub.1 C.sub.1 +
                  A.sub.2 C.sub.0)
R.sub.3 =         S.sub.3 =
A.sub.1 · (B.sub.0 C.sub.1 + B.sub.1 C.sub.2 + B.sub.2 C.sub.0)
                  B.sub.1 · (A.sub.0 C.sub.2 + A.sub.1 C.sub.1 +
                  A.sub.2 C.sub.0)
R.sub.4 =         S.sub.4 =
A.sub.2 · (B.sub.0 C.sub.0 + B.sub.1 C.sub.1 + B.sub.2 C.sub.2)
                  B.sub.2 · (A.sub.0 C.sub.0 + A.sub.1 C.sub.2 +
                  A.sub.2 C.sub.1)
R.sub.5 =         S.sub.5 =
A.sub.2 · (B.sub.0 C.sub.0  + B.sub.1 C.sub.1 + B.sub.2 C.sub.2)
                  B.sub.2 · (A.sub.0 C.sub.0 + A.sub.1 C.sub.2 +
                  A.sub.2 C.sub.1)
r.sub.1 = R.sub.4 + R.sub.5
                   s.sub.1 = S.sub.4 + S.sub.5
r.sub.2 = R.sub.2 + R.sub.3
                   s.sub.2 = S.sub.2 + S.sub.3
r.sub.3 = R.sub.1 + R.sub.3 + R.sub.5
                   s.sub.3 = S.sub.1 + S.sub.3 + S.sub.5
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                       TABLE VI
______________________________________
BOOLEAN ALGEBRA
RUNLENGTH PAIR TO TRIT TRIPLE DECODER
______________________________________
R.sub.0 = r.sub.1 r.sub.2 r.sub.3
                    S.sub.0 = s.sub.1 s.sub.2 s.sub.3
R.sub.1 = r.sub.1 r.sub.2 r.sub.3
                    S.sub.1 = s.sub.1 s.sub.2 s.sub.3
R.sub.2 = r.sub.1 r.sub.2 r.sub.3
                    S.sub.2 = s.sub.1 s.sub.2 s.sub.3
R.sub.3 = r.sub.1 r.sub.2 r.sub.3
                    S.sub.3 = s.sub.1 s.sub.2 s.sub.3
R.sub.4 = r.sub.1 r.sub.2 r.sub.3
                    S.sub.4 = s.sub.1 s.sub.2 s.sub.3
R.sub.5 = r.sub.1 r.sub.2 r.sub.3
                    S.sub.5 = s.sub.1 s.sub.2 s.sub.3
A.sub.1 = R.sub.2 + R.sub.3
                     B.sub.1 = S.sub.2 + S.sub.3
A.sub.2  = R.sub.4 + R.sub.5
                     B.sub.2 = S.sub.4 + S.sub.5
C.sub.1 =
      (R.sub.0 + R.sub.5) (S.sub.1 + S.sub.2) + (R.sub.1 + R.sub.2)
      (S.sub.3 + S.sub.4) +
      (R.sub.3 + R.sub.4) (S.sub.0 + S.sub.5)
C.sub.2 =
      (R.sub.1 + R.sub.2) (S.sub.0 + S.sub.5) + (R.sub.3 + R.sub.4)
      (S.sub.1 + S.sub.2) +
      (R.sub.0 + R.sub.5) (S.sub.3 + S.sub.4)
a.sub.1 = A.sub.2
               b.sub.1 = B.sub.2
                            c.sub.1 = C.sub.2
a.sub.2 = A.sub.1
               b.sub.2 = B.sub.1
                            c.sub.2 = C.sub.1
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     While the invention has been described in detail by specific reference to preferred embodiments thereof, it is understood that variations and modifications thereof may be made without departing from the true spirit and scope of the invention.