Patent Publication Number: US-9847706-B2

Title: Systems and methods for reducing voltage ringing in a power converter

Description:
FIELD OF DISCLOSURE 
     The present disclosure generally relates to integrated circuits, and, more particularly, to systems and methods for reducing voltage ringing in a power converter of an electronic circuit. 
     BACKGROUND 
     Many electronic devices on the market today often use power converters to convert electric energy from one form to another (e.g., converting between alternating current and direct current), converting a voltage or current of an electrical signal, modifying a frequency of an electrical signal, or some combination of the above. Examples of power converters may include boost converters and buck converters. Such power converters are often used to convert an input voltage for other circuitry, wherein such converted voltage is greater than (e.g., if a boost converter is used) or less than (e.g., if a buck converter is used) than the input voltage.  FIG. 1  illustrates an example circuit  100  comprising a boost converter  102  for converting an input source voltage V BAT  to produce a supply voltage V SUPPLY  for a switched output stage  104  of an amplifier (e.g., an audio amplifier), as is known in the art. In  FIG. 1 , boost converter  102  comprises an inductor  106  coupled at a first terminal to an input source voltage V BAT  and coupled at a second terminal to non-gate terminals of each of switches  108  and  110 . Boost converter  102  shown in  FIG. 1  also comprises a switch  108  (e.g., an n-type metal-oxide-semiconductor field effect transistor) coupled at one non-gate terminal to a ground voltage and coupled at its other non-gate terminal to inductor  106  and a non-gate terminal of switch  110 , and a switch  110  (e.g., a p-type metal-oxide-semiconductor field effect transistor) coupled at one non-gate terminal to inductor  106  and a non-gate terminal of switch  108  and coupled at its other non-gate terminal to a terminal of capacitor  107 . Boost converter  102  shown in  FIG. 1  also includes a capacitor  107  coupled between a non-gate terminal of switch  110  and a ground voltage. Predriver circuit  116  may receive an input control voltage v CTRL  (typically a pulse-width-modulated input voltage signal) and apply control logic and/or buffering to such input voltage to drive a positive-polarity control voltage v CTRLP  to the gate terminal of switch  110  and to drive a negative-polarity control voltage v CTRLN  to the gate terminal of switch  108 , wherein v CTRLP  and v CTRLN  are each a function of v CTRL . In steady-state operation, switch  108  will generally be open when switch  110  is closed, and vice versa. When switch  108  is closed, current may flow from the voltage source generating the input source voltage V BAT  through inductor  106 , and inductor  106  may store energy. During this time, inductor  106  may have a voltage drop across it, with a positive-polarity at the terminal coupled to the input source voltage V BAT . When switch  108  is open and switch  110  is closed, the current flowing through inductor  106  may be reduced. Such change or reduction in current may be opposed by inductor  106  and the voltage polarity of inductor  106  may reverse (e.g., with a positive-polarity at the terminal coupled to generating the input source voltage V BAT ). As a result, effectively two voltage sources are in series (input source voltage V BAT  and the voltage across inductor  106 ) thus causing a voltage higher than V BAT  to charge capacitor  107 . If switches  108  and  110  are cycled fast enough, inductor  106  will not discharge fully in between charging stages, and the supply voltage V SUPPLY  on capacitor  107  will have voltage greater than that of the input source voltage V BAT  when switch  108  is opened. Thus, the supply voltage V SUPPLY  generated by boost converter  102  will be a function of input control voltage V CTRL  (e.g., the switching rate and/or duty cycle of a pulse-modulated signal) and the input source voltage V BAT . 
     Switched output stage  104  comprises two complementary legs, each leg comprising a pull-up device  112  (e.g., a switch, a p-type metal-oxide-semiconductor field effect transistor, etc.) coupled at its non-gate terminals between a supply voltage and an output node and a pull-down device  114  (e.g., a switch, an n-type metal-oxide-semiconductor field effect transistor, etc.) coupled at its non-gate terminals between a ground voltage and the output node. An amplifier predriver circuit  118  may receive an input voltage v IN  (typically a pulse-width-modulated input voltage signal) and apply control logic and/or buffering to such input voltage to generate a positive-polarity input voltage V IN+  to be applied to the gate terminals of the pull-up device  112   a  and pull-down device  114   a  of a first leg and a negative-polarity input voltage V IN−  to be applied to the gate terminals of the pull-up device  112   b  and pull-down device  114   b  of the other leg. Accordingly, switched output stage  104  generates a differential output voltage signal v OUT  to its output node which is a function of v IN  and V SUPPLY . 
     One disadvantage of boost converters is that the output voltage V SUPPLY  of the boost converter may be susceptible to overshoot and ringing, which may ultimately affect the output voltage signal (e.g., v OUT ) of a switched output stage to which the supply voltage is supplied. Such overshoot and subsequent ringing often occurs as a result of parasitic capacitances and inductances in the circuit resonating at their characteristic frequency, which decays over time due to resistances present in the circuit. For example, referring to  FIG. 1 , as switching node voltage v SW  transitions between its maximum and minimum voltages, v SW  may first overshoot such maximum or minimum voltages by an overshoot amplitude, and then oscillate about such maximum or minimum voltage as the ringing decays. Such overshoot and ringing may couple through switch  110 , and thus may cause ringing on the supply voltage V SUPPLY  which may in turn cause noise or distortion on the output voltage signal v OUT . 
     Traditional approaches to reduction of overshoot and ringing of the output voltage V SUPPLY  of a boost converter include increasing the rise and fall times of the negative-polarity control voltage v CTRLN  However, such approaches are not without disadvantages, as increasing rise and fall times places constraints on timing parameters (e.g., minimum duty cycle) associated with boost converter  102 .  FIG. 2  illustrates example voltage and timing graphs associated with boost converter  102  illustrated in  FIG. 1 , as is known in the art. As shown in  FIG. 2 , during a rising-edge transition of switching node voltage v SW , negative-polarity control voltage v CTRLN  may decrease from its maximum voltage (e.g., a supply voltage) to a plateau voltage during a time period t 1 , and then remain at such plateau voltage during a period of time t 2 , before falling to zero. Also as shown in  FIG. 2 , v SW  may transition from zero to its maximum voltage during time t 2 . Those of ordinary skill in the art may recognize that a long time period t 1  places constraints on timing parameters (e.g., minimum duty cycle) associated with boost converter  102  and thus can negatively affect timing efficiency and power efficiency while not significantly improving electromagnetic interference. Conversely, long time period t 2  will likely show reduced electromagnetic interference, overshoot, and ringing than a shorter time period t 2 . However, assuming a constant weak pull down strength from the gate terminal of switch  108  during each time period t 1  and t 2 , any beneficial increase in time period t 2  results in an undesired increase in time period t 1 . 
     Similarly, as also shown in  FIG. 2 , negative-polarity control voltage v CTRLN  may increase from a ground voltage to a plateau voltage, and then remain at such plateau voltage during a period of time t 2 ′, before rising to its maximum voltage during a period of time t 1 ′. Also as shown in  FIG. 2 , v SW  may transition from a maximum voltage to a ground voltage during time t 2 ′. Those of ordinary skill in the art may recognize that a long time period t 1 ′ places constraints on timing parameters (e.g., minimum duty cycle) associated with boost converter and thus can negatively affect timing efficiency and power efficiency while not significantly improving electromagnetic interference. Conversely, long time period t 2 ′ will likely show reduced electromagnetic interference, overshoot, and ringing than a shorter time period t 2 ′. 
     SUMMARY 
     In accordance with the teachings of the present disclosure, certain disadvantages and problems associated with output signal integrity of a power converter have been reduced or eliminated. 
     In accordance with embodiments of the present disclosure, an apparatus may include an input configured to indicate a switching node voltage of a switching node of a power converter comprising a first switch device coupled at its non-gate terminals between a ground voltage and the switching node and a second switch device coupled at its non-gate terminals between an output supply node and the switching node. The apparatus may also include a predriver circuit coupled to the input and a gate terminal of the first switch device, the predriver circuit configured to drive an input voltage signal to the gate terminal of the first switch device and configured to select an effective impedance of the gate terminal of the first switch device based on the input. 
     In accordance with these and other embodiments of the present disclosure, a method may include receiving an input configured to indicate a switching node voltage of a switching node of a power converter comprising a first switch device coupled at its non-gate terminals between a ground voltage and the switching node and a second switch device coupled at its non-gate terminals between an output supply node and the switching node. The method may also include selecting an effective impedance of a gate terminal of the first switch device based on the input. 
     Technical advantages of the present disclosure may be readily apparent to one having ordinary skill in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein: 
         FIG. 1  illustrates an example circuit comprising a boost converter for converting an input source voltage to produce a supply voltage for a switched output stage of an amplifier, as is known in the art; 
         FIG. 2  illustrates example voltage and timing graphs associated with the boost converter illustrated in  FIG. 1 , as is known in the art; and 
         FIG. 3  illustrates an example circuit comprising a boost converter and a predriver for converting an input source voltage to produce a supply voltage in accordance with embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  illustrates an example circuit  300  comprising a boost converter  302  for converting an input source voltage v BAT  to produce a supply voltage V SUPPLY , in accordance with embodiments of the present disclosure. As shown in  FIG. 3 , circuit  300  may comprise a boost converter  302  and a predriver circuit  301 . 
     Boost converter  302  may comprise any system, device, or apparatus configured to convert a direct current input source voltage V BAT  to generate a supply voltage V SUPPLY  wherein the conversion is based on a control voltage v CTRL  or a derivative thereof. As shown in  FIG. 3 , boost converter  302  may include an inductor  306 , a switch  308  (implemented as an n-type metal-oxide-semiconductor field effect transistor in the embodiments represented by  FIG. 3 ), a switch  310  (implemented as a p-type metal-oxide-semiconductor field effect transistor in the embodiments represented by  FIG. 3 ), and a capacitor  307 . Inductor  306  may be coupled at a first terminal to the input source voltage V BAT  and coupled at a second terminal to non-gate terminals of each of switches  308  and  310 . Switch  308  may be coupled at one non-gate terminal to a ground voltage and coupled at its other non-gate terminal to inductor  306  and a non-gate terminal of switch  310 . Switch  310  may be coupled at one non-gate terminal to inductor  306  and a non-gate terminal of switch  308  and coupled to a terminal of capacitor  307 . Capacitor  307  may be coupled between a ground voltage and a non-gate terminal of switch  310 . The various components of boost converter  302  may be configured such that switch  308  is generally open when switch  310  is closed, and vice versa. When switch  308  is closed, current may flow from the voltage source generating the input source voltage V BAT  through inductor  306 , and inductor  306  may store energy. During this time, inductor  306  may have a voltage drop across it, with a positive-polarity at the terminal coupled to generating the input source voltage V BAT . When switch  308  is open and switch  310  is closed, the current flowing through inductor  306  may be reduced. Such change or reduction in current may be opposed by inductor  306  and the voltage polarity of inductor  306  may reverse (e.g., with a positive-polarity at the terminal coupled to generating the input source voltage V BAT ). As a result, effectively two voltage sources are in series (input source voltage V BAT  and the voltage across inductor  306 ) thus causing a voltage higher than V BAT  to charge capacitor  307 , thus generating supply voltage V SUPPLY  on capacitor  307 . The supply voltage V SUPPLY  generated by boost converter  302  may be a function of input control voltages v CTRLP  and v CTRLN  controlling switches  308  and  310  (e.g., the switching rate and/or duty cycle of a pulse-modulated signal) and the input source voltage V BAT . 
     Predriver circuit  301  may comprise any system, device, or apparatus configured to receive an input control voltage v CTRL  (e.g., a pulse-width-modulated voltage signal) and apply control logic and/or buffering to such input voltage to drive positive-polarity control voltage v CTRLP  to the gate terminal of switch  310  and to drive a negative-polarity control voltage v CTRLN  to the gate terminal of switch  308 , wherein v CTRLP  and v CTRLN  are each a function of v CTRL . Based on respective input voltage signals v CTRLP  and v CTRLN , boost converter  302  may generate a supply voltage V SUPPLY  which is a function of the respective input control signals v CTRLP  and v CTRLN . 
     As shown in  FIG. 3 , predriver circuit  301  may include a rising-edge negative-polarity portion  303 , a falling-edge negative-polarity portion  304 , and a positive-polarity portion  320 . Rising-edge negative-polarity portion  303  may comprise pull-down device  312   a  (implemented as an n-type metal-oxide-semiconductor field effect transistor in the embodiments represented by  FIG. 3 ), pull-down device  312   b  (implemented as an n-type metal-oxide-semiconductor field effect transistor in the embodiments represented by  FIG. 3 ), logic AND gate  315 , and logic inverter  316 . Pull-down device  312   a  may be coupled at its non-gate terminals between a ground voltage and the node for negative-polarity control voltage v CTRLN  and may be driven at its gate terminal by input control voltage v CTRL . Pull-down device  312   b  may be coupled at its non-gate terminals between a ground voltage and the node for negative-polarity control voltage v CTRLN  and may be driven at its gate terminal by the output terminal of logic AND gate  315 . Logic AND gate  315  may in turn be driven at one of its input terminals by input control voltage v CTRL  and driven at its other input terminal by the output terminal of logic inverter  316 . Logic inverter  316  may be driven at its input terminal by the switching node voltage v SW  present at the node in which inductor  306 , switch  308 , and switch  310  are coupled to each other. Pull-down device  312   b  may be configured such that when enabled, it has a greater drive strength (e.g., a greater size) than pull-down device  312   a . Thus, when the switching node voltage v SW  transitions from the ground voltage to its maximum voltage, negative-polarity control voltage v CTRLN  may be driven by both pull-down device  312   a  and pull-down device  312   b , which may quickly pull down negative-polarity control voltage v CTRLN  from its maximum voltage to a plateau voltage (e.g., corresponding to time period t 1  depicted in  FIG. 2 ), at which point pull-down device  312   b  may turn off in response to v SW  transitioning to a higher voltage, and pull-down device  312   a  may then slowly pull down negative-polarity control voltage v CTRLN  from the plateau voltage to the ground voltage ( FIG. 2  depicts the time period t 2  in which v CTRLN  is at the plateau voltage, during which V sw  transitions to its maximum voltage). 
     Accordingly, rising-edge negative-polarity portion  303  may ensure a switching transition of negative-polarity control voltage v CTRLN  in order to maintain a desired level of timing and/or power efficiency (e.g., by quickly pulling down negative-polarity control voltage v CTRLN  from its maximum voltage to the plateau voltage) while also controlling the falling edge of negative-polarity control voltage v CTRLN  to reduce or eliminate its tendency to cause overshoot or ringing on the switching node voltage v SW  (e.g., by slowly pulling down negative-polarity control voltage v CTRLN  from the plateau voltage to the ground voltage relative to the rate at which rising-edge negative-polarity portion  303  pulls down negative-polarity control voltage v CTRLN  from its maximum voltage to the plateau voltage). Thus, based on an input indicating the switching node voltage v SW , rising-edge negative-polarity portion  303  may select a drive strength of a pull-down circuit, thus selecting an effective impedance for the gate terminal of switch  308  which is based on the drive strength, such that rising-edge negative-polarity portion  303  is configured to decrease the drive strength as the switching node voltage v SW  increases from the ground voltage to an output voltage (e.g., maximum voltage). 
     Falling-edge negative-polarity portion  304  may comprise pull-up device  314   a  (implemented as a p-type metal-oxide-semiconductor field effect transistor in the embodiments represented by  FIG. 3 ), pull-up device  314   b  (implemented as a p-type metal-oxide-semiconductor field effect transistor in the embodiments represented by  FIG. 3 ), logic OR gate  317 , logic inverter  318 , and logic OR gate  319 . Pull-up device  314   a  may be coupled at its non-gate terminals between a supply voltage and the node for negative-polarity control voltage v CTRLN  and may be driven at its gate terminal by logic OR gate  317 . Logic OR gate  317  may be driven at one of its input terminals by input control voltage v CTRL  and driven at its other input terminal by the output terminal of logic inverter  318 . Logic inverter  318  may be driven at its input terminal by the positive-polarity control voltage v CTRLP . Pull-up device  314   b  may be coupled at its non-gate terminals between a supply voltage and the node for negative-polarity control voltage v CTRLN  and may be driven at its gate terminal by the output terminal of logic OR gate  319 . Logic OR gate  319  may in turn be driven at one of its input terminals by input control voltage v CTRL  and driven at its other input terminal by the switching node voltage v SW . Pull-up device  314   b  may be configured such that when enabled, it has a greater drive strength (e.g., a greater size) than pull-up device  314   a . Thus, when the switching node voltage v SW  transitions from its maximum voltage to the ground voltage, the negative-polarity control voltage v CTRLN  may first be driven by pull-up device  314   a  to be at or near a plateau voltage (e.g., corresponding to time period t 2 ′ depicted in  FIG. 2 ). Once the switching node voltage v SW  transitions to a level below a predetermined threshold voltage, pull-up device  314   b  may turn on, quickly driving the negative-polarity control voltage v CTRLN  to the supply voltage (e.g., corresponding to time period t 1 ′ depicted in  FIG. 2 ). 
     Accordingly, falling-edge negative-polarity portion  304  may ensure a fast switching transition of negative-polarity control voltage v CTRLN  in order to maintain a desired level of timing and/or power efficiency (e.g., by quickly pulling up negative-polarity control voltage v CTRLN  from the plateau voltage to its maximum voltage) while also controlling the rising edge of negative-polarity control voltage v CTRLN  to reduce or eliminate its tendency to cause overshoot or ringing on the switching node voltage v SW  (e.g., by slowly pulling up negative-polarity control voltage v CTRLN  from the ground voltage to the plateau voltage and maintaining the plateau voltage relative to the rate at which falling-edge negative-polarity portion  304  pulls up negative-polarity control voltage v CTRLN  from the plateau voltage to its maximum voltage). Thus, based on an input indicating the switching node voltage v SW , falling-edge negative-polarity portion  304  may select a drive strength of a pull-up circuit, thus selecting an effective impedance for the gate terminal of switch  308  which is based on the drive strength, such that falling-edge negative-polarity portion  304  is configured to increase the drive strength as the switching node voltage v SW  decreases from its maximum voltage to the ground voltage. 
     Positive-polarity portion  320  may comprise pull-down device  322  (implemented as an n-type metal-oxide-semiconductor field effect transistor in the embodiments represented by  FIG. 3 ), pull-up device  324  (implemented as a p-type metal-oxide-semiconductor field effect transistor in the embodiments represented by  FIG. 3 ), logic AND gate  326 , logic NAND gate  328 , and logic inverter  330 . Pull-down device  322  may be coupled at its non-gate terminals between a ground voltage and the node for positive-polarity control voltage v CTRLP  and may be driven at its gate terminal by logic AND gate  326 . Pull-up device  324  may be coupled at its non-gate terminals between a supply voltage and the node for positive-polarity control voltage v CTRLP  and may also be driven at its gate terminal by logic AND gate  326 . Logic AND gate  326  may be driven at one of its input terminals by input control voltage v CTRL  and driven at its other input terminal by the output terminal of logic NAND gate  328 . Logic NAND gate  328  may be driven at one of its input terminals by the negative-polarity control voltage v CTRLN  and driven at its other input terminal by logic inverter  330 . Logic inverter  330  may be driven at its input terminal by the switching node voltage v SW . When the switching node voltage v SW  transitions from the ground voltage to its maximum voltage, the positive-polarity control voltage v CTRLP  may be driven to the ground voltage in response to the negative-polarity control voltage v CTRLN  falling and/or the switching node voltage v SW  rising, thus ensuring smooth transition between switch  308  and switch  310  and therefore, reducing the output voltage ringing of boost converter  302 . 
     Accordingly, positive-polarity portion  320  may further improve the edge control functionality of falling-edge negative-polarity portion  304 . In particular, as input control voltage v CTRL  decreases from its maximum voltage to the ground voltage, it may cause pull-up device  324  of positive-polarity portion  320  to pull up the positive-polarity control voltage v CTRLP  to the supply voltage, in turn enabling pull-up device  314   a  of falling-edge negative-polarity portion  304 , thus beginning the transition of negative-polarity control voltage v CTRLN  from the ground voltage to the plateau voltage. 
     As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication whether connected indirectly or directly, without or without intervening elements. 
     This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. 
     All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosures have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.