Patent Publication Number: US-11049450-B2

Title: Pixel circuit and method for driving pixel circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a National Stage Application, filed under 35 U.S.C. 371, of International Patent Application No. PCT/CN2018/084996, filed on Apr. 28, 2018, which claims priority to Chinese patent application No. 201710617336.6 filed on Jul. 26, 2017, contents of both of which are incorporated herein by reference in their entireties. 
     TECHNICAL FIELD 
     The present disclosure relates to the field of pixel driving technology and, for example, to a pixel circuit and a pixel circuit driving method. 
     BACKGROUND 
     Active-matrix organic light emitting diode (AMOLED) display technology gradually replaces the conventional display technology (such as liquid crystal display) for its advantages of wide color gamut, wide viewing angle, high contrast and low power consumption. In an AMOLED screen, a pixel circuit is used as a signal control circuit of pixels, and plays an important role in a display panel. At present, the defects in the mainstream Low Temperature Poly-silicon (LTPS) process has non-uniform voltage threshold (Vth), so the pixel circuit is mainly used for compensating the Vth. For a product (such as a micro-display) with high pixels per inch (PPI), the line width of the pixel circuit layout diagram is narrowed due to smaller pixel layout space. Therefore, a voltage drop of a supply voltage of a power source is increased, and writing of screen signals is inconsistent. Therefore, non-uniform display is caused. 
     SUMMARY 
     In view of this, the present disclosure provides a pixel circuit and a pixel circuit driving method. 
     The present disclosure provides the pixel circuit provided, which is applied to an AMOLED screen. The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first scan signal line, a second scan signal line, a data signal line, a control signal line, a capacitor and a light emitting diode (LED). 
     A gate electrode of the first transistor is connected to the first scan signal line, a source electrode of the first transistor is connected to a first plate of the capacitor, and a drain electrode of the first transistor is connected to a source electrode of the second transistor. 
     A second plate of the capacitor is connected to a drain electrode of the third transistor. 
     A gate electrode of the second transistor is connected to the second scan signal line, a drain electrode of the second transistor is connected to a gate electrode of the fourth transistor, and the source electrode of the second transistor is connected to the data signal line. 
     A source electrode of the third transistor is configured to be connected to a power source, the drain electrode of the third transistor is connected to a source electrode of the fourth transistor, and a gate electrode of the third transistor is connected to the control signal line. 
     A drain electrode of the fourth transistor is connected to an anode of the LED. 
     A cathode of the LED is configured to be connected to ground. 
     The first scan signal line is configured to transmit a control signal to the gate electrode of the first transistor to control the first transistor to turn on or off. The second scan signal line is configured to transmit a control signal to the gate electrode of the second transistor to control the second transistor to turn on or off. The control signal line is configured to transmit a control signal to the gate electrode of the third transistor to control the third transistor to turn on or off. 
     The present disclosure further provides a pixel circuit driving method, which is applied to the above pixel circuit. The method includes steps described below. 
     The first scan signal line is configured to transmit a control signal to the gate electrode of the first transistor to control the first transistor to turn on or off. 
     The second scan signal line is configured to transmit a control signal to the gate electrode of the second transistor to control the second transistor to turn on or off. 
     The data signal line is configured to write a digital signal transmitted from the data signal line into the fourth transistor through the second transistor. 
     The digital signal from the data signal line may be written into the capacitor through the first transistor. 
     A signal from the power source may be written into the fourth transistor through the third transistor. 
     The present disclosure further provides a pixel circuit driving method, which is applied to the above pixel circuit. The method includes steps described below. 
     In a first stage, the first scan signal line is configured to control the first transistor to turn on, the second scan signal line is configured to control the second transistor to turn on, and the data signal line is configured to write a first signal at a low level into the gate electrode of the fourth transistor and the first plate of the capacitor. 
     In a second stage, the first scan signal line is configured to control the first transistor to turn off, the second scan signal line is configured to control the second transistor to turn on, and the data signal line is configured to write a second signal at a high level into the gate electrode of the fourth transistor to clamp a voltage at the source of the fourth transistor to a third signal. The third signal is determined by the second signal and a threshold voltage of the fourth transistor. 
     In a third stage, the first scan signal line is configured to control the first transistor to turn on, the control signal line is configured to control the third transistor to turn on, to make a voltage at the source electrode of the fourth transistor equal to a supply voltage of the power source. Under a coupling action of the capacitor, a voltage at the gate electrode of the fourth transistor is clamped to a fourth signal. The fourth signal is determined by the first signal, the third signal and the supply voltage. 
     According to the pixel circuit and the pixel circuit driving method provided by the present disclosure, the effect of the supply voltage and the threshold voltage of the fourth transistor can be effectively cancelled through fewer transistors and capacitors, so that the display of a display connected to the pixel circuit is more uniform. In addition, the pixel circuit provided by the present disclosure has the advantages of simple structure, less signals and relatively simpler circuit layout. Therefore, it is beneficial to the layout of the pixel circuit. 
    
    
     
       DESCRIPTION OF DRAWINGS 
       In order to more clearly describe the embodiments of the present disclosure, the drawings required in the embodiments are briefly described below. It should be understood that the following drawings only show some embodiments of the present disclosure and should not be considered as the limitation of the scope. 
         FIG. 1  is a structural diagram of a pixel circuit provided by an embodiment of the present disclosure; 
         FIG. 2  is a timing diagram of a pixel circuit provided by an embodiment of the present disclosure; 
         FIG. 3  is a structural diagram of another pixel circuit provided by an embodiment of the present disclosure; 
         FIG. 4  is a structural diagram of another pixel circuit provided by an embodiment of the present disclosure; 
         FIG. 5  is a structural diagram of another pixel circuit provided by an embodiment of the present disclosure; and 
         FIG. 6  is a flowchart of a pixel circuit driving method provided by an embodiment of the present disclosure. 
     
    
    
     REFERENCE SIGNS 
     M 1 : First transistor; M 2 : Second transistor; M 3 : Third transistor; M 4 : Fourth transistor; M 5 : Fifth transistor; M 6 : Sixth transistor; Scan 1 : First scan signal line; Scan 2 : Second scan signal line; Vdate: Data signal line; EM: Control signal line; OLED: Organic light emitting diode; Vd: Power source; C: Capacitor; Vss: Ground power source. 
     DETAILED DESCRIPTION 
     The embodiments of the present disclosure will be described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some, but not all embodiments of the present disclosure. The following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the protection scope of the present disclosure, and is only representative of selected embodiments of the present disclosure. 
     It should be noted that similar reference numbers and letters in the following drawings refer to similar items. Therefore, once an item is defined in one figure, the item does not need to be further defined and explained in subsequent figures. Meanwhile, in the description of the present disclosure, the terms such as “first” and “second” are only used for distinguishing descriptions and are not to be understood as indicating or implying relative importance. 
     First Embodiment 
     The embodiment provides a pixel circuit. As shown in  FIG. 1 , the pixel circuit includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a first scan signal line Scan 1 , a second scan signal line Scan 2 , a data signal line Vdate, a control signal line EM, a capacitor C and a light emitting diode LED. 
     In the embodiment, a gate electrode of the first transistor M 1  is connected to the first scan signal line Scan 1 , a source electrode of the first transistor M 1  is connected to a first plate of the capacitor C, and a drain electrode of the first transistor M 1  is connected to a source electrode of the second transistor M 2 . 
     In an implementation, as shown in  FIG. 3 , the first transistor M 1  may be a dual-gate transistor, and both gates of the first transistor M 1  are connected to the first scan signal line Scan 1 . Leakage current may be significantly reduced through using the dual-gate transistor, so that the stability of a signal of the capacitor C connected to the first transistor M 1  is improved. 
     In the embodiment, a second plate of the capacitor C is connected to a drain electrode of the third transistor M 3 . 
     In the embodiment, a gate electrode of the second transistor M 2  is connected to the second scan signal line Scan 2 , a drain electrode of the second transistor M 2  is connected to a gate electrode of the fourth transistor M 4 , and the source electrode of the second transistor M 2  is connected to the data signal line Vdata. 
     In the embodiment, a source electrode of the third transistor M 3  is configured to be connected to a power source Vd, the drain electrode of the third transistor M 3  is connected to a source electrode of the fourth transistor M 4 , and a gate electrode of the third transistor M 3  is connected to the control signal line EM. 
     In the embodiment, a drain electrode of the fourth transistor M 4  is connected to an anode of the LED. A cathode of the LED is connected to ground. As shown in  FIG. 1 , the LED is connected to a ground power source Vss. 
     In the embodiment, the first scan signal line Scan 1  is configured to transmit a control signal to the gate electrode of the first transistor M 1  to control the first transistor M 1  to turn on or off. The second scan signal line Scan 2  is configured to transmit a control signal to the gate electrode of the second transistor M 2  to control the second transistor M 2  to turn on or off. The control signal line EM is configured to transmit a control signal to the gate electrode of the third transistor M 3  to control the third transistor M 3  to turn on or off. 
     In an embodiment, each of the first transistor M 1 , the second transistor M 2 , the third transistor M 3  and the fourth transistor M 4  may be made of N-type Metal-Oxide Semiconductor (NMOS), or P-type Metal-Oxide Semiconductor (PMOS). 
     In an implementation, the pixel circuit may be driven through following three stages to implement that the pixel circuit cancels a supply voltage of the power source and a threshold voltage of the fourth transistor M 4 . 
     In a first stage, the first scan signal line Scan 1  is configured to control the first transistor M 1  to turn on, the second scan signal line Scan 2  is configured to control the second transistor M 2  to turn on, and the data signal line is configured to write a first signal at a low level into the gate electrode of the fourth transistor M 4  and the first plate of the capacitor C. 
     In a second stage, the first scan signal line Scan 1  is configured to control the first transistor M 1  to turn off, the second scan signal line Scan 2  is configured to control the second transistor M 2  to turn on, and the data signal line Vdate is configured to write a second signal at a high level into the gate electrode of the fourth transistor M 4  to clamp a voltage at the source of the fourth transistor M 4  to a third signal. The third signal is determined by the second signal and the threshold voltage of the fourth transistor M 4 . 
     In a third stage, the first scan signal line Scan 1  is configured to control the first transistor M 1  to turn on, the control signal line EM is configured to control the third transistor M 3  to turn on, to make a voltage at the source electrode of the fourth transistor M 4  equal to the supply voltage. Under a coupling action of the capacitor C, a voltage at the gate electrode of the fourth transistor M 4  is clamped to a fourth signal. The fourth signal is determined by the first signal, the third signal and the supply voltage. 
     In an example, a transistor is turned on when a low level is inputted at a gate electrode of the transistor. As shown in  FIG. 2 , in the first stage T 1 , the first scan signal line Scan 1  and the second scan signal line Scan 2  respectively provide a low level to control the first transistor M 1  and the second transistor M 2  to turn on. The data signal line Vdate is configured to write a first signal at a low level into the gate electrode of the fourth transistor M 4  and the first plate of the capacitor C. In an example, the first signal is recorded as Vdate 1 . In other examples, the transistors in the embodiment may further be turned on when a high level is inputted at the gate electrode of the transistor. The embodiment of the present disclosure is not limited to the manner in which the transistors are turned on or off. The following is an example of the transistor being turned on when a low level is inputted at the gate electrode of the transistor. 
     In the second stage T 2 , the first scan signal line Scan 1  provides a high level, and the first transistor M 1  is turned off after receiving a signal provided by the first scan signal line Scan 1 . The second scan signal line Scan 2  provides a low level, and the second transistor M 2  is turned on after receiving a signal provided by the second scan signal line Scan 2 . At this time, the data signal line Vdate outputs a second signal at a high level. The fourth transistor M 4  is turned off after receiving the second signal output from the data signal line Vdate. The voltage at the source electrode of the fourth transistor M 4  is clamped to the third signal. The third signal is determined by the second signal input from the data signal line Vdate and the threshold voltage of the fourth transistor M 4 . In an example, the second signal is recorded as Vdate 2 , the threshold voltage is recorded as Vth, and the third signal is recorded as Vdate 2 −Vth. 
     In the third stage T 3 , the second scan signal line Scan 2  provides a high level to control the second transistors M 2  to turn off. The first scan signal line Scan 1  and the control signal line EM provide a low level, and the first transistor M 1  and the third transistor M 3  are turned on after receiving a signal at the low level. At this time, the voltage at the source electrode of the fourth transistor M 4  is the supply voltage. In an example, the supply voltage of the power source Vd is recorded as Vdd. Under the coupling action of the capacitor C, a voltage at the gate electrode of the fourth transistor M 4  is recorded as Vdata 1 +(Vdd−Vdata 2 +Vth). 
     A difference between the voltage at the gate electrode of the fourth transistor M 4  and the voltage at the source electrode of the fourth transistor M 4  in the third stage T 3  is the following: 
     
       
         
           
             
               
                 
                   
                     Vgs 
                     = 
                       
                     ⁢ 
                     
                       
                         Vdata 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         ( 
                         
                           Vdd 
                           - 
                           
                             Vdata 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                           + 
                           Vth 
                         
                         ) 
                       
                       - 
                       Vdd 
                     
                   
                 
               
               
                 
                   
                     = 
                       
                     ⁢ 
                     
                       
                         Vdata 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       - 
                       
                         
                           ( 
                           
                             
                               Vdata 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             - 
                             Vth 
                           
                           ) 
                         
                         . 
                       
                     
                   
                 
               
             
               
           
         
       
     
     Vgs represents the difference between the voltage at the gate electrode of the fourth transistor M 4  and the voltage at the source electrode of the fourth transistor M 4 , Vdate 1  represents the first signal, Vdate 2  represents the second signal, Vth represents the threshold voltage of the fourth transistor M 4 , and Vdd represents the supply voltage. 
     At this time, a current flowing through the fourth transistor M 4  is the following: 
     
       
         
           
             
               
                 
                   
                     Ids 
                     = 
                       
                     ⁢ 
                     
                       
                         β 
                         2 
                       
                       ⁢ 
                       
                         
                           ( 
                           
                             Vgs 
                             - 
                             Vth 
                           
                           ) 
                         
                         2 
                       
                     
                   
                 
               
               
                 
                   
                     = 
                       
                     ⁢ 
                     
                       
                         β 
                         2 
                       
                       ⁢ 
                       
                         { 
                         
                           
                             ( 
                             
                               
                                 Vdate 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                               - 
                               
                                 ( 
                                 
                                   
                                     Vdate 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                   - 
                                   Vth 
                                 
                                 ) 
                               
                               - 
                               Vth 
                             
                             } 
                           
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   
                     = 
                       
                     ⁢ 
                     
                       
                         β 
                         2 
                       
                       ⁢ 
                       
                         
                           
                             ( 
                             
                               
                                 Vdate 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                               - 
                               
                                 Vdate 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                             ) 
                           
                           2 
                         
                         . 
                       
                     
                   
                 
               
             
               
           
         
       
     
     Ids represents the current flowing through the fourth transistor M 4 , and β represents an amplification factor of the fourth transistor M 4 . 
     From the above calculation result of Ids, it should be known that the current flowing through the fourth transistor M 4  at this time is not affected by the supply voltage and the threshold voltage of the fourth transistor M 4 . The pixel circuit can effectively cancel the effect of the supply voltage and the threshold voltage of the fourth transistor M 4  on the display effect of the LED under the condition of using fewer components. In addition, the pixel circuit provided by the embodiment of the present disclosure has the advantages of simple structure, less signals and relatively simpler circuit layout. Therefore, it is beneficial to the layout of the pixel circuit. 
     Second Embodiment 
     The embodiment provides a pixel circuit. The embodiment is similar to the first embodiment except that the pixel circuit in the embodiment is added with a fifth transistor M 5  compared with the pixel circuit in the first embodiment. As shown in  FIG. 3 , the pixel circuit further includes the fifth transistor M 5 . 
     In the embodiment, a drain electrode of the fifth transistor M 5  is connected to the anode of the LED, a source electrode of the fifth transistor M 5  is connected to the drain electrode of the fourth transistor M 4 , and a gate electrode of the fifth transistor M 5  is connected to the control signal line EM. The control signal line EM is configured to transmit a control signal to the gate electrode of the fifth transistor M 5  to control the fifth transistor M 5  to turn on or off. 
     Other details about the embodiment may be referred to the description in the first embodiment, and are not described herein again. 
     According to the pixel circuit in the embodiment, the fifth transistor M 5  is added on the basis of the first embodiment. Therefore, the brightness anomaly of the LED, caused by the leakage current flowing into the LED when the fourth transistor M 4  is in an off state, can be effectively prevented. 
     Third Embodiment 
     The embodiment provides a pixel circuit. The embodiment is similar to the first embodiment except that the pixel circuit in the embodiment is added with a sixth transistor M 6  and a reference level signal line compared with the pixel circuit in the first embodiment. Referring to  FIG. 5 , the pixel circuit further includes the sixth transistor M 6  and a reference level signal line Verf. 
     In the embodiment, a gate electrode of the sixth transistor M 6  is connected to the first scan signal line Scan 1 , and a drain electrode of the sixth transistor M 6  is connected to the LED. The first scan signal line Scan 1  is configured to transmit a control signal line to the gate electrode of the sixth transistor M 6  to control the sixth transistor M 6  to turn on or off. 
     The reference level signal line Verf is connected to a source electrode of the sixth transistor M 6 . The reference level signal line Verf is configured to provide an initial current to flow into the LED through the sixth transistor M 6  to initialize the LED. 
     Other details about the embodiment may be referred to the description in the first embodiment, and are not described herein again. 
     According to the pixel circuit in the embodiment, the sixth transistor M 6  and the reference level signal line Verf are added, and the LED is initialized through the reference level signal line Verf providing a signal. Therefore, the effect of a parasitic charge of the LED on the signal received later is prevented, and the stability of the LED is improved. 
     In other embodiments, as shown in  FIG. 5 , the pixel circuit may include all the elements of the first embodiment, the second embodiment and the third embodiment. Other contents about the embodiment may be referred to the descriptions in the first, second and third embodiments, and are not described in detail herein again. 
     Fourth Embodiment 
     The embodiment provides a pixel circuit deriving method. The method includes steps described below. 
     The first scan signal line Scan 1  is configured to transmit a control signal to the gate source of the first transistor M 1  to control the first transistor M 1  to turn on or turn off. 
     The second scan signal line Scan 2  is configured to transmit a control signal to the gate source of the second transistor M 2  to control the second transistor M 2  to turn on or turn off. 
     The data signal line Vdate is configured to write a digital signal transmitted from the data signal line into the fourth transistor M 4  through the second transistor M 2 . 
     The digital signal from the data signal line Vdate may be written into the capacitor C or the fourth transistor M 4  through the first transistor M 1 . 
     A signal from the power source may be written to the fourth transistor M 4  through the third transistor M 3 . 
     In an implementation, the pixel circuit driving method in the embodiment controls the pixel circuit through three stages. The above method may be applied to any pixel circuit. As shown in  FIG. 6 , the above method includes steps described below. 
     In a first stage  101 , the first scan signal line Scan 1  is configured to control the first transistor M 1  to turn on, the second scan signal line Scan 2  configured to control the second transistor M 2  to turn on, and the data signal line Vdate is configured to write a first signal at a low level into the gate electrode of the fourth transistor M 4  and the first plate of the capacitor C. 
     In a second stage  102 , the first scan signal line Scan 1  is configured to control the first transistor M 1  to turn off, the second scan signal line Scan 2  is configured to control the second transistor M 2  to turn on, and the data signal line Vdate is configured to write a second signal at a high level into the gate electrode of the fourth transistor M 4  to clamp a voltage at the source of the fourth transistor M 4  to a third signal. The third signal is determined by the second signal and a threshold voltage of the fourth transistor. 
     In a third stage  103 , the first scan signal line Scan 1  is configured to control the first transistor M 1  to turn on, and the control signal line EM is configured to control the third transistor M 3  to turn on, to make a voltage at the source electrode of the fourth transistor M 4  equal to a supply voltage of the power source Vd. Under the coupling action of the capacitor C, the voltage at the gate electrode of the fourth transistor M 4  is clamped to the fourth signal. The fourth signal is determined by the first signal, the third signal and the supply voltage. 
     In the embodiment, the third signal in the second stage  102  is a difference between the second signal and the threshold voltage of the fourth transistor M 4 . 
     The difference between the voltage at the gate electrode of the fourth transistor M 4  and the voltage at the source electrode of the fourth transistor M 4  in the third stage  103  is the following: 
     
       
         
           
             
               
                 
                   
                     Vgs 
                     = 
                       
                     ⁢ 
                     
                       
                         Vdata 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         ( 
                         
                           Vdd 
                           - 
                           
                             Vdata 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                           + 
                           Vth 
                         
                         ) 
                       
                       - 
                       Vdd 
                     
                   
                 
               
               
                 
                   
                     = 
                       
                     ⁢ 
                     
                       
                         Vdata 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       - 
                       
                         
                           ( 
                           
                             
                               Vdata 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             - 
                             Vth 
                           
                           ) 
                         
                         . 
                       
                     
                   
                 
               
             
               
           
         
       
     
     Vgs represents the difference between the voltage at the gate electrode of the fourth transistor and the voltage at the source electrode of the fourth transistor, Vdate 1  represents the first signal, Vdate 2  represents the second signal, Vth represents the threshold voltage of the fourth transistor, and Vdd represents the supply voltage. 
     At this time, a current flowing through the fourth transistor is the following: 
     
       
         
           
             
               
                 
                   
                     Ids 
                     = 
                       
                     ⁢ 
                     
                       
                         β 
                         2 
                       
                       ⁢ 
                       
                         
                           ( 
                           
                             Vgs 
                             - 
                             Vth 
                           
                           ) 
                         
                         2 
                       
                     
                   
                 
               
               
                 
                   
                     = 
                       
                     ⁢ 
                     
                       
                         β 
                         2 
                       
                       ⁢ 
                       
                         { 
                         
                           
                             ( 
                             
                               
                                 Vdate 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                               - 
                               
                                 ( 
                                 
                                   
                                     Vdate 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                   - 
                                   Vth 
                                 
                                 ) 
                               
                               - 
                               Vth 
                             
                             } 
                           
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   
                     = 
                       
                     ⁢ 
                     
                       
                         β 
                         2 
                       
                       ⁢ 
                       
                         
                           
                             ( 
                             
                               
                                 Vdate 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                               - 
                               
                                 Vdate 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                             ) 
                           
                           2 
                         
                         . 
                       
                     
                   
                 
               
             
               
           
         
       
     
     Ids represents the current flowing through the fourth transistor, and β represents an amplification factor of the fourth transistor. 
     In the embodiment, when the pixel circuit includes the fifth transistor M 5  connected between the fourth transistor M 4  and the LED, the method further includes a following step: when a current flows through the fourth transistor M 4 , the current flows into the LED after the current flows through the fifth transistor M 5 . 
     In the embodiment, when the pixel circuit includes the sixth transistor M 6  and the reference level signal line, the method further includes a following step: the first scan signal line Scan 1  is configured to transmit an initialization control signal to the sixth transistor M 6  to control the sixth transistor M 6  to turn on. The reference level signal line is configured to provide an initial current to flow into the LED through the six transistor M 6 , to initialize the LED. 
     Other details about the embodiment may be referred to the descriptions in the first, second and third embodiments, and are not described herein again. 
     According to the method in the embodiment, the effect of the power supply voltage and the threshold voltage of the fourth transistor can be effectively cancelled through fewer transistors and capacitors, so that the display of a display connected with the pixel circuit is more uniform. In addition, the pixel circuit provided by the embodiment of the present disclosure has the advantages of simple structure, less signals and relatively simpler circuit layout. Therefore, it is beneficial to the layout of the pixel circuit. 
     INDUSTRIAL APPLICABILITY 
     According to the pixel circuit and the pixel circuit driving method provided by the present disclosure, the effect of the supply voltage and the threshold voltage of the fourth transistor can be effectively cancelled through fewer transistors and capacitors, so that the display of the LED is more uniform. The structure of the pixel circuit is simple, which is beneficial to the layout of the pixel circuit.