Patent Publication Number: US-7590899-B2

Title: Processor memory array having memory macros for relocatable store protect keys

Description:
RELATED APPLICATION 
   This application is related to a co-pending application owned by the assignee International Business Machines Corporation, Sep. 15, 2006 entitled “Relocatable Storage Protect Keys for System Main Memory”, by inventors Kevin Kark et al. U.S. Ser. No. 11/532294. 
   TRADEMARKS 
   IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other company. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates in general to an improved method of managing computer memory for computers and digital systems and, in particular, to the management of processor memory arrays with store protect keys by integrating storage protect keys (SP Keys) in main storage to share the same physical memory. 
   2. Description of Background 
   In past generations of digital and computer designs in the IBM z-Series architecture, there was provided a Store Protect Key (SP Key) which was a logical SP Key for every 4 KB of storage. Each SP key was 7 bits in length. The operating system, such as z/OS managed data access via these SP Keys. In a typical IBM z-Series system, having 512 GB of memory provided for main storage, this resulted in 128 million SP Keys. These keys were packages in prior systems with SRAM or a separate DRAM infrastructure. 
   As the technologies and designs have evolved, this is becoming increasingly more difficult. For example, there is a need to improve granularity and cost/performance in the memory storage capacity of advanced computer memory systems with higher density DRAM technology and packaging such as that provided by the memory described in IBM&#39;s “A high Reliability Memory Module with a Fault Tolerant Address and Common Bus”, U.S. Pat. No. 7,234,099, granted Jun. 19, 2007, based on a application filed by Kevin C. Gower et al. U.S.Ser. No. 10/413605 of Apr. 14, 2003, which is incorporated herein by reference. 
   What is needed is a method and hardware that allows for maintaining a single copy of data sets with a plurality of instances in a mainframe computer system with increasing storage needs. 
   SUMMARY OF THE INVENTION 
   The present invention allows for the use of one copy of common data sets along with a plurality of instances in a mainframe computer system having massive storage needs by providing a relocatable SP Key region within the common physical memory as in main storage of the computer system. 
   The manner by which the present invention seeks to achieve these goals is by application of the disclosed method steps which can be generally applied to any memory design structure either hierarchical or flat in nature. Furthermore, our invention allows for compliance with the rules set forth in most common design environments requiring a consistent nomenclature for data sets representing a particular design entity. 
   Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
       FIG. 1  shows a typical physical design topology for which our invention is intended to be used in a main storage DIMM, which illustrates stacked DRAMs, as opposed to the alternative view of single DRAMs illustrated by the memory module  20  shown in  FIG. 2   
       FIG. 2  describes the preferred memory main storage subsystem having a memory card arrangement of DIMMs for a mainframe computer system. 
       FIG. 3  shows the method mapping an absolute to physical address in the memory in which the SP keys are part of the physical main storage for memory of a mainframe computer system with a storage controller configuration array. 
   

   The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings. 
   DETAILED DESCRIPTION OF THE INVENTION 
   Turning now to the drawings in greater detail, it will be seen that  FIG. 1  depicts a typical physical design structure for a common physical memory as described in IBM&#39;s “A high Reliability Memory Module with a Fault Tolerant Address and Common Bus”, U.S. patent referenced above, which is incorporated herein by reference. 
   In accordance with our invention the DIMM shown therein has been modified to provide in the DIMM shown in  FIG. 1  comprising one of a plurality of storage regions defined in physical entities hereafter referred to as memory macro segments which are relocatable regions which contain SP Keys and data set main storage in the DIMM physical memory. These memory macro segments, including SP Key regions and data set main storage element regions, define an arbitrary logic structure for main storage which have a hard physical boundary with absolute dimensions, aspect ratios, wiring layers, and they serve as the lowest level objects in the design hierarchy and the SP Key regions can be physically relocated/moved to different main storage locations with their integrated SP Keys. The preferred DIMM differs from the referenced US patent incorporated by reference in that it is a DDR SDRAM DIMM for a mainframe main storage subsystem which has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length  55  (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends ( 51 , 52 ) having a width  56  smaller than the length  55 ; a first plurality of connector locations  24  on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations  24  of the second side extending on the first edge of the board, a locating key  52  having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide (shown by arrows as width of locating key  52 ) centered at  53 , 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered  54 , at 67.58 or 65.675 from the second end of the board. Unlike the memory described in the referenced patent, each DIMM has memory regions which form part of the main storage of the mainframe computer system memory subsystem comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory which may be spread across several DIMMs. These memory macros SP Key regions define an arbitrary logic structure for main storage which have a hard physical boundary. In addition, we have provided in the registered buffer for the memory module special triple detect and double correct ECC matrix registered buffer SP Key protection. 
     FIG. 1  illustrates a stacked version of the memory module  20  having DRAMs  22  and a register buffer  21  with connectors  24  for coupling to a memory subsystem board where the layout is at the right of the top and back illustrations of the stacked version of the memory module. In  FIG. 1  the register buffer is an IBM chip conforming to the AMB (Advanced Memory Buffer) used on the industry standard FBDIMM (Fully Buffered DIMM). 
   This improves Reliability, Availability and Serviceability and design commonality, and contributes to improved costs and performance. This was not possible with prior designs. In  FIG. 1 , the DIMM memory module has a plurality of DRAMS, and a register buffer for the memory module. Consistent with the design the register buffer manufactured by Philips Semiconductor as Part No. SSTU32964 shown in  FIG. 2  conforming to the above referenced IBM patent, the Nova Buffer  21  shown in  FIG. 1  is consistent with the forthcoming industry standard FBDIMM and is configured to provide a triple detect and double correct ECC matrix in the register buffer for SP Keys as well as data sets within the memory. Prior designs for SP Key regions were only provided with parity protection. In the register buffer a physical key consists of 7 bits of data and 9 bits of ECC which is 2 bytes in length. This additional ECC protection for SP Keys aids performance. 
     FIG. 2  illustrates the memory subsystem having a storage controller interface and preferred memory card arrangement for a mainframe computer system by enhancing an IBM clipper card arrangement holding a plurality of DIMMs with a DIMM having a plurality of DRAMs and the improved triple detect and double correct ECC matrix registered buffer for SP Keys as well as data sets within the memory.  FIG. 2  shows the locating key having its center positioned on the first edge and located at 81.58 mm from the first end of the board and located centered at 67.58 mm from the second end of the board.  FIG. 2  illustrates a straight layout version of the memory module  20  having DRAMs  22  and a register buffer  21  with connectors  24  for coupling to a memory subsystem board where the layout is at the right of the top and back illustrations of the stacked version of the memory module. 
   The alternative  FIG. 2  DIMM has an optimized spacing of the locating key for a mainframe computer memory subsystem would provide the locating key having it centered positioned on the first edge and located at 85.67 mm from the first end of the board and located centered at 65.675 mm from the second end of the board. Generally herein, all dimensions can fall within 3.0 mm from the optimized position. 
     FIG. 3  shows the method mapping an absolute to physical address in the memory in which the SP keys are part of the physical main storage for memory of a mainframe computer system. As illustrated in  FIG. 3 , the main storage provided by a plurality of DIMMs has integrated SP Keys in a relocatable physical address. The system employs an IBM SSDRAM having DDR SDRAMs and a common interface through the main storage controller (MSC) for memory for both data sets and the SP Key. As there are no unique SP key components in the memory cards, the memory selftest runtime is streamlined, as the main storage selftest is a test of the entire physical memory. With the use of the registered buffer with triple detect and double correct ECC matrix. The ECC is provided throughout the entire storage domain. And the SP Key region shown is relocatable. The SP Key region within main storage is reserved and not accessible by customer applications. The Key Cache Controller and MSC have programmable “offset” addresses within the Main Storage. In the preferred embodiment the relocatable physical segment or band of storage is 256 MB and that is reserved as a relocatable SP Key region based on a Configuration Array mapping by the Storage Controller (SC Configuration Array). The absolute address provided to the Configuration array is addressed by the SC with the physical address of main storage. If during IML (start up) the target regions has too many memory correctable errors (CEs) or uncorrectable errors (UEs) then the entry for the SP Key Region based upon a configuration array mapping can be relocated. 
   Thus by using the SC Configuration array which maps absolute address into physical address, firmware can assign the SP Keys anywhere within a physical memory (as opposed to the fixed/non-moveable DRAM physical location in prior designs). This additionally improves Reliability, Availability and Serviceability (RAS) capability by providing for relocation of the SP Key region to another storage region if there are excessive DRAM errors located during IML startup testing. Unlike prior systems where excessive Key UEs would result in system outages if not sparing was available, the relocatable storage SP Key regions reduce system outages. 
   While the foregoing disclosure shows a number of illustrative embodiments of the invention, it will be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the scope of the invention as defined by the appended claims. Furthermore, although elements of the invention may be described or claimed in the singular, as one means at least one, the plural is contemplated unless limitation to the singular is explicitly stated.