Patent Publication Number: US-9406765-B1

Title: Hybrid dielectric non-volatile memory with nano particles (Si/SiO2 core/shell) as charge trapping layer

Description:
COPYRIGHT NOTICE 
     A portion of the disclosure of this patent document contains material, which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. 
     FIELD OF THE INVENTION 
     The present invention relates to a printable non-volatile memory, and particularly relates to a method for preparing hybrid organic-inorganic dielectric layers for flash memory transistors by solution process at low temperature, and more particularly relates to a method for fabricating a non-volatile memory with nano particles as charge trapping layer. 
     BACKGROUND 
     The following references are cited in the specification. Disclosures of these references are incorporated herein by reference in their entirety. 
     LIST OF REFERENCES 
     
         
         [1]. Y. J. Park et al., IEEE Trans on Dielectrics and Electrical Insulation 17(4), 1135-1163 (2010) 
         [2]. Introduction to Flash Memory, PROCEEDINGS OF THE IEEE 91(4), APRIL 2003 [3]. Kim et al., Appl. Phys. Lett. 96, 033302 (2010) 
         [4]. T. Sekitani, Science 326, 1516-1519 (2009) 
         [5]. C. C. Leu, S. T. Chen, F. K. Liu and C. X. Wu, J. Mater. Chem. 22, 2089-2098 (2012) 
         [6]. B. Chandar Shekar, Jiyeon Lee and Shi-Woo Rhee, Korean J. Chem. Eng., 21(1), 267-285 (2004) 
         [7]. C. Z. Zhao et al., IEEE TRANSACTIONS ON ELECTRON DEVICES 55(7), 1647-1656 (2008) 
         [8]. June Whan Choi, Ho Gyu Yoon, Jai Kyeong Kim, Organic Electronics 11, 1145-1148 (2010) 
         [9]. Jin-Yong Lee et al., Appl. Phys. Lett. 104, 093514 (2014) 
       
    
     Electronic devices are traditionally fabricated using rigid semiconductors and high-temperature manufacturing method. In contrast, printed devices can be processed at low temperatures and on large-area polymeric substrates. Data storage is one key requirement in many electronic devices. Plenty of efforts have been spent on printed memory devices in order to realize large-area, flexible, and low-cost electronic devices. For example, ferroelectric (Fe) polymer, P(VDF-TrFE), was developed for electrical switching [1]. The electrical switching of Fe polymers, P(VDF-TrFE), requires a relatively large coercive field of ˜MV/cm with thickness down to 100 nm, and the coercive field required to reverse the macroscopic polarization increases with decreasing film thickness. Thus, it is difficult to obtain large enough memory window with program and erase voltages below 20V, which is challenging printed memories for low-power applications. Therefore, these memory transistors based on Fe polymer are not compatible with commercial reading systems which operate under low power and low voltage [2]. 
     In order to make nonvolatile memory transistors operated under low voltage (&lt;10V) and be printable on flexible substrates, floating gate thin film transistors are developed with dielectric gate layer thin enough [3,4]. The charge leakage from the Au NPs (nano particles) floating gate can be suppressed by improving the NPs/dielectric interface with Au NPs spin-coated on 3-aminopropyltrimethoxysilane (APTMS)-modified SiO 2 . Furthermore, a simple but effective self-assembly monolayer (SAM) method was used to construct an Au—SiO 2  core-shell NC capacitor by use of APTMS as a mediator [5]. But the process temperature for this memory device is higher than 400° C. and then this device is not able to be fabricated by printing techniques. 
     The significance of dielectric layer is attracting more and more interests in order to develop high-performance printable floating gate memory transistors. Many studies have tried to find better gate dielectrics with polymeric materials, inorganic/organic hybrids, inorganic/organic bilayers, and organic/inorganic hybrids via sol-gel reaction. In the case of a polymer dielectric film, one of the drawbacks is the high operating voltage in devices due to its thickness and low dielectric constant (PMMA 2.5-4.5, polyimide 2.6-3.3, Teflon 1.9), compared with inorganic dielectrics (Al 2 O 3  9 and Ta 2 O 5  26) [6]. To solve this problem, high-k inorganic materials such as Al 2 O 3  and Ta 2 O 5  had been used as gate insulators due to their dielectric constants which are much higher than those of polymers. But metal oxide has relatively high leakage current and these films can be produced with the vacuum techniques, such as chemical vapor deposition, sputtering or flame hydrolysis. Vacuum equipment is not suitable for a low temperature and low cost process required by printing techniques. Alternatively, high-k inorganic nanoparticles can be dispersed in polymer matrix. However, a nanocomposite dielectric layer with high-k NPs embedded in polymer matrix has a rough surface and high gate leakage current to have a low on/off current ratio. In addition, it is difficult to eliminate fixed-charge trapping defects generated by high-k NPs in dielectric layer. These fixed-charge associated trapping defects in dielectrics will become deadly shielding of preventing the mobile charging/discharging progress in memory transistors. The sol-gel derived siloxane based organic-inorganic hybrid materials (hybrimers) are nanocomposite materials in which inorganic and organic components are intimately linked at molecular scale by a covalent bond and nano-sized oligomers are well-dispersed. Since they combine the characteristics of both glass and polymers, it has low leakage current density and has potential chances of removing fixed-charge trapping defects in hybrid organic-inorganic dielectrics. 
     However, the memory behaviour and the production cost of the conventional technologies still fail to meet the need of the market. 
     Consequently, there is an unmet need to have a method for fabricating nonvolatile memory transistors being applicable for printed electronics with desirable memory behavior and low production cost. 
     SUMMARY OF THE INVENTION 
     To satisfy the requirements of manipulating the trap levels and trap sites for floating gate transistors, employment on nano-crystals floating gate is considered to be an alternative approach to replace the traditional planar floating gate for information storage. The present invention has focused on incorporating Si NPs as the charge storage elements in non-volatile memory devices. Nanoparticle-based memories benefit from reduced lateral discharge paths, and promise larger retention time, lower power consumption, and faster operation. Compared to metal NPs (Au, Ag, Al, etc.), applying Si nanocrystals as floating gate can remove metal contaminations in gate dielectrics, which is critical to reduce device leakage. 
     In the present invention, Si/SiO 2  core/shell nanostructures are used to work as trapping sites in floating gate memory. Uniform SiO 2  shell of 3 nm to 5 nm in thickness surrounding each Si NPs is formed by silicon cores simultaneously oxidized in solutions and it reduces lateral discharging with retention properties improved. More importantly, with monolayer of Si NPs trapping layers, this ultrathin/uniform SiO 2  shell functions as tunneling layer of flash memory devices and leads to quite low operation voltage for printable NPs floating-gate memory devices. Compared to traditional memory stacks (substrate/tunnel layer/charge trapping layer/control layer/gate electrode) [2, 3, 4 5], the present invention didn&#39;t involve separate tunnel layer, and the high-quality SiO 2  shell acts as tunnel layer. 
     Also hybrid organic/inorganic dielectrics layer is prepared by sol-gel method. With sol-gel formula optimized and curing conditions improved at low temperature, memory devices with this novel hybrid dielectrics show relatively low leakage current density and more importantly it is successful to remove fixed-charge associated trapping defects in dielectrics. 
     Accordingly, a first aspect of the presently claimed invention is to provide a printable floating gate transistor for non-volatile memory. 
     According to an embodiment of the presently claimed invention, a floating gate memory device comprises: a substrate; a charge trapping layer formed on the substrate, wherein the charge trapping layer comprises a hybrid organic/inorganic dielectric material and silicon/silicon dioxide (Si/SiO 2 ) core/shell nanostructures, and the Si/SiO 2  core/shell nanostructures are embedded within the hybrid organic/inorganic dielectric material; a hybrid organic/inorganic dielectric layer formed on the charge trapping layer; and a gate electrode formed on the hybrid organic/inorganic layer; and wherein each of the Si/SiO 2  core/shell nanostructures comprises a Si core enclosed by a SiO 2  shell acting as a tunnel layer for the floating gate memory device. 
     A second aspect of the presently claimed invention is to provide a method for fabricating a floating gate transistor. 
     According to an embodiment of the presently claimed invention, a method for fabricating a floating gate memory device comprises: providing a substrate; mixing silicon particles with a solution comprising an organic solvent and hydrogen peroxide to form a silicon/silicon dioxide (Si/SiO 2 ) core/shell nanostructures solution, wherein the silicon particles comprises a size of 10 nm to 50 nm; coating the Si/SiO 2  core/shell nanostructure solution on the substrate; drying the Si/SiO 2  core/shell nanostructure solution with a drying temperature in a range of 60° C. to 150° C. to form a charge trapping layer; mixing 3-methacryloxypropyltrimethoxysilane (MEMO), zirconium propoxide (ZrPO), methacrylic acid (MAA), and a photoinitiator to form a hybrid organic/inorganic dielectric solution, coating the hybrid organic/inorganic dielectric solution on the charge trapping layer; curing the hybrid organic-inorganic dielectric solution on the charge trapping layer by UV light; curing the hybrid organic/inorganic dielectric solution thermally with a curing temperature in a range of 130° C. to 180° C. to form a hybrid organic/inorganic layer; and forming a gate electrode on the hybrid organic/inorganic layer. 
     The sol-gel derived organic-inorganic hybrid materials of the dielectric layer are nano-composite materials in which inorganic and organic components are intimately linked at the molecular scale by a covalent bond and nano-sized oligomers are well dispersed. The trap sites of the charge trapping layer directly relate to memory window which can be controlled by varying the density of nanoparticles. The memory transistor of the present invention exhibits a memory window of 4.2 V, long retention time (100 ks) with low operating voltage (&lt;7 V). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention are described in more detail hereinafter with reference to the drawings, in which: 
         FIG. 1A  shows a schematic diagram of a printable floating gate non-volatile memory device with Si/SiO 2  core/shell structures as charge trapping layer according to an embodiment of the presently claimed invention; 
         FIG. 1B  shows a schematic structure of a traditional floating gate non-volatile memory device in a prior art; 
         FIG. 2  shows a flow chart of a method for fabricating a non-volatile memory device according to an embodiment of the presently claimed invention; 
         FIG. 3  is a graph showing leakage current density at different bias fields according to an embodiment of the presently claimed invention; 
         FIG. 4  is a flowchart showing process flow for preparing a hybrid Sol-Gel solution according to an embodiment of the presently claimed invention; 
         FIG. 5A  is an atomic force microscopy AFM image of monolayer Si/SiO 2  core/shell structures coating according to an embodiment of the presently claimed invention; 
         FIG. 5B  is a TEM image of Si/SiO 2  core/shell structures with shell thickness of ˜5 nm according to an embodiment of the presently claimed invention; 
         FIG. 6  is a graph showing memory effects of Si/SiO 2  core/shell structures according to an embodiment of the presently claimed invention; 
         FIG. 7A  is a graph showing memory behavior tuned via varying the voltage stress time according to an embodiment of the presently claimed invention; 
         FIG. 7B  is a graph showing memory behavior tuned via varying the stress voltage amplitude according to an embodiment of the presently claimed invention; 
         FIG. 8  is a graph showing retention properties of memory based on Si/SiO 2  core/shell NPs according to an embodiment of the presently claimed invention; and 
         FIGS. 9A-D  are CV loops measured under different voltage stress time for samples 1, 2, 3, and 4 respectively according to an embodiment of the presently claimed invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     In the following description, a memory device, and the corresponding embodiments of the fabrication methods are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation. 
     Si/SiO 2  core/shell nanostructures with sizes below 30 nm as trapping points in UV curable hybrid organic-inorganic gate dielectrics are presented in the present invention. Not only does the novelty of the present invention comes from fabricating high-quality hybrid organic/inorganic gate dielectric stacks by Sol-Gel process at low temperature but also incorporating the monolayer of high-density of Si nanoparticles (NPs) without obvious interface defects and keeping the high-quality of dielectric layers. In the present memory devices fabricated by solution process at low temperature, fixed-charge trapping points associated with as synthesized defects are successfully removed from dielectric layer and clear memory effects are demonstrated with trapping functions solely related to Si/SiO 2  core/shell nanostructures. 
     As shown in  FIG. 1A , a floating gate transistor  100  of the present invention comprises a Si substrate  101 , a charge trapping comprising a plurality of Si/SiO 2  core/shell nanostructures  105  embedded within a hybrid organic/inorganic dielectric material  106 , a hybrid organic/inorganic dielectric layer  103 , and a gate electrode  104 . The charge trapping layer  102  is formed on the Si substrate  101 . The hybrid organic/inorganic dielectric layer  103 , acting as a control layer for memory device, is formed on the charge trapping layer  102 , and the gate electrode  104  is formed on the hybrid organic/inorganic dielectric layer  103 . The Si/SiO 2  core/shell nanostructures  105  are located on the surface of the substrate  101 . The charge trapping layer  102  comprises a monolayer of the Si/SiO 2  core/shell nanostructures  105 . The hybrid organic/inorganic dielectric layer  103  comprises the same material as the hybrid organic/inorganic dielectric material  106 . Typical gate stacks for traditional floating gate transistor include substrate/tunnel layer/charge trapping layer/control layer/gate electrode as shown in  FIG. 1B  [2, 3, 4, 5]. Normally, very thin oxide as tunnel layer for flash memory transistors must be fabricated by high temperature and/or, slow vacuum process [2, 5]. The present invention didn&#39;t involve separate fabrication of tunnel layer and it significantly simplifies the fabrication of flash gate transistors. 
     Preferably, the size of Si/SiO 2  core/shell nanostructures is in a range of 10 nm to 50 nm, and the thickness of the charge trapping layer is in a range of 10 nm to 50 nm since the trapping points are formed into a monolayer coating. The charge trapping layer comprises a density of the nanostructures in a range of 1×10 10  cm −2  to 1×10 12  cm −2 . The SiO 2  shell with thickness of 3 nm to 5 nm functions as a tunnel layer in flash memory device in the present invention. Preferably, the thickness of the SiO 2  shell is 5 nm. The thickness of the dielectric layer is in a range of 300 nm to 800 nm. 
       FIG. 2  shows a flow chart of a method for fabricating of a non-volatile memory device according to an embodiment of the presently claimed invention. In step  201 , a substrate is provided. In step  202 , a Si/SiO 2  core/shell nanostructure solution is prepared. In step  203 , the Si/SiO 2  core/shell nanostructure solution is coated on the substrate. In step  204 , the Si/SiO 2  core/shell nanostructure solution is dried to form a charge trapping layer. In step  205 , a hybrid organic/inorganic dielectric solution is prepared. In step  206 , the hybrid organic/inorganic dielectric solution is coated on the charge trapping layer. In step  207 , the hybrid organic/inorganic dielectric solution is cured to form a hybrid organic/inorganic dielectric layer with UV curing and thermal curing. In step  208 , a gate electrode is attached on the dielectric layer. 
     The Si/SiO 2  core/shell nanostructure solution is prepared by mixing Si nanoparticles with ethanol and hydrogen peroxide. The average size of the Si nanoparticles is below 30 nm. This size (˜30 nm) of NPs is able to be obtained with significantly higher production yield than quantum sizes of 1 nm to 5 nm. Also as proved in the present invention, 30 nm-NPs can form effective charge-trapping layer for non-volatile memory. Larger NPs (&gt;50 nm) will challenge the film quality of followed hybrid dielectrics. The Si/SiO 2  core/shell nanostructure solution is coated on the substrate by dipping. The nanostructure solution can also be coated on the substrate by other methods, such as spray, doctor-blade, inkjet printing, or spin coating. Preferably, these nanostructures are coated on the substrate to form a monolayer for reducing charge leakage. 
     Preferably, the weight ratio of Si particles in the nanostructure solution may be in the range of 1% to 10%, dependent on what coating method is used. The solvents of Si NPs solution can include but not limited to Isopropanol, n-Propanol, Ethanol, Methanol, Acetone, etc. A volume ratio of H 2 O 2  to the solvents is in the range of 5% to 20%. 
     The hybrid organic/inorganic dielectric solution is prepared by mixing 3-methacryloxypropyltrimethoxysilane (MEMO), zirconium propoxide (ZrPO) and methacrylic acid (MAA). The ratio of MEMO:ZrPO is related to hybrid composites of organics versus inorganics, preferred to be in the range of 7:3 or 6:4, to 5:5. The photoinitiator is added for UV curing to reduce the curing temperature for thermal curing to below 180° C. for high-quality hybrid dielectric layer. 
     The hybrid organic-inorganic dielectric solution is coated on the charge trapping layer by dip-coating, and then cured by UV and thermal curing at low temperature of 130° C. to 180° C. The sol-gel solution can also be coated on the charge trapping layer by other methods, such as spray, doctor-blade, inkjet printing, or spin coating. 
     UV curing is critical to fabricate high-quality hybrid dielectrics for floating gate memory. UV curing followed by low-temperature thermal curing will efficiently remove the fixed-charge defects in as-synthesized hybrid dielectrics. Pre-drying the hybrid organic-inorganic dielectric solution with a pre-drying temperature in a range of 60° C. to 150° C. can be performed before UV curing. 
     EXAMPLES 
     Example 1 
     The preferred embodiments for fabrication of Non-Volatile Memory devices with Si/SiO 2  core/shell nanostructures as charge trapping layer are shown as below. Lightly-doped silicon wafer with resistivity of 15-25 Ohm-cm was selected as substrate and then monolayer Si/SiO 2  core/shell nanostructures were coated as charge trapping layer. Afterwards, 0.5 um-1.0 um thick hybrid dielectrics layer was formed by dip coating as control layer. Eventually, top and bottom electrodes were formed by printing Ag paste. The device area was defined as 2 mm×2 mm. 
     The organic-inorganic hybrid gate dielectric solution in this invention is synthesized by using sol-gel reactions between 3-methacryloxypropyltrimethoxysilane (MEMO), Zirconium propoxide (ZrPO) and methacrylic acid (MAA). With this organic/inorganic hybrid precursor solution, high-k dielectric layer can be obtained by dip-coating method to control the dielectric thickness. After UV curing and thermal curing, current densities passing through hybrid dielectric layers are relatively low as shown in  FIG. 3 , where Hybrid 1, 2, and 3 in  FIG. 3  represent different samples in one batch. 
     The process flow for Sol-Gel process of hybrid organic/inorganic dielectrics and dip coating is shown in  FIG. 4 . For example, 3-methacryloxypropyltrimethoxysilane (MEMO, 19.5 mmol) was first partially hydrolyzed with HCl as a catalyst. The pH value was controlled by HCl to enhance the hydrolysis. 10.5 mmol of each of Zirconium propoxide (ZrPO) and methacrylic acid (MAA) were mixed in 5 mL 1-propanol. After MEMO was stirred for 30 min, the two solutions were mixed. More DI water was added to facilitate the reaction. The molar ratio of MEMO:ZrPO:MAA:water was 6.5:3.5:3.5:18. The solution was sealed and stirred overnight, then added with 1 wt % photo-initiator 1-hydroxycyclohexylphenylketone (HCHPK) and diluted with 1-propanol to control the concentration. The solution was filtered with 0.22 um Millipore membrane. Afterwards, the solution was deposited on substrate (PET, glass, or Si wafer) by typical dip coater. Then, the coating was first pre-dried on a hotplate at 110° C. for 30 min. UV curing was performed with Dymax Bluewave 200 at 20 mW/cm 2  for 5 min. Lastly, thermal curing was done in a thermal oven at 170° C. for 3 h. 
     Si nanoparticles (NPs) can be easily oxidized in an ethanol (EtOH)/H 2 O 2  solution to form Si/SiO 2  core/shell structures. These nanostructures with average size of &lt;30 nm were dispersed into ethanol solution and coated on substrate by dipping. Typical monolayer coating is shown in  FIG. 5A  under atomic force microscopy (AFM). High-resolution transmission electron microscopy (TEM) image in  FIG. 5B  showed the SiO 2  shell is ˜5 nm in thickness. 
     The memory behavior as shown in  FIG. 6  was clearly observed to come from mobile charging/discharging solely related to Si/SiO 2  core/shell nanostructures on the charge trapping layer. Regarding the capacitance versus voltage (CV) characterization of samples without Si nanostructures, its charge trapping layer didn&#39;t show any hysteresis, indicating high-quality hybrid dielectrics without any fixed-charge defects. The memory window (the width of CV loop) has been tuned via varying the voltage stress time ( FIG. 7A ) and the stress voltage amplitude ( FIG. 7B ), which offers relatively easy control ability for different flexible electronics applications. 
     Although nano-floating gate transistor memory based on Si/SiO 2  core/shell NPs drives voltage not larger than 10V, memory window remained 75% after 10 4  s program/erase (P/E) tests with P/E speed within 75 ms as shown in  FIG. 8 . 
     Example 2 
     In order to optimize sol-gel process for high-quality hybrid dielectric layer, below samples for different hybrid dielectrics were investigated as shown in Table 1. All samples use the same device structures as Example 1. Loops of capacitance versus voltage (CV) were measured for these devices under different time of voltage stress at gate. The pulse width time of applied voltage stress can change the width of CV loops during memory charging/discharging process. However, if there are dominant fixed charge defects in dielectrics, the charging/discharging process of memory devices will be screened and the width of CV loops will become insensitive to voltage stress time [7]. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Investigation of hybrid dielectrics for nano 
               
               
                 floating gate memory devices 
               
            
           
           
               
               
               
               
            
               
                   
                   
                   
                 Thermal  
               
               
                 Samples 
                 Formula 
                 UV cure 
                 Cure 
               
               
                   
               
            
           
           
               
               
               
               
            
               
                 1 
                 MEMO:ZrPO = 6.5:3.5 
                 20 mW/cm 2 ,  
                 170° C., 3 h 
               
               
                   
                   
                 5 min 
                   
               
               
                 2 
                 MEMO:ZrPO = 8:2 
                 20 mW/cm 2 ,  
                 170° C., 3 h 
               
               
                   
                   
                 5 min 
                   
               
               
                 3 
                 MEMO:ZrPO = 6.5:3.5 
                 NO 
                 170° C., 3 h 
               
               
                 4 
                 TiO 2  NPs dispersed in PMMA 
                 NO 
                 170° C., 3 h 
               
               
                   
               
            
           
         
       
     
     Sample 1 is similar to the sample in Example 1 and it is cured by UV 20 mW/cm 2 , 5 min followed by thermal curing with 170° C., 3 h. Sample 2 incorporates fewer ZrPO into dielectrics and is also cured by 20 mW/cm 2 , 5 min and 170° C., 3 h. From CV loops under different voltage stress time for both sample 1 ( FIG. 9A ) and sample 2 ( FIG. 9B ), loop width significantly increases with longer stress time. This is a typical charging/discharging process by trapping layers in memory device. There are fewer high-k components of ZrPO in sample 2. So the flat-band capacitance of sample 2 is ˜114 pF, a little bit lower than 165 pF of sample 1. 
     However, sample 3 without UV curing may indicate some fixed defects in dielectrics and it involved some —OH groups with hybrid materials [8]. Its CV loops stay insensitive to voltage stress time as shown in  FIG. 9C . UV light irradiation should be very critical to form good crosslinks at molecular scale between inorganic (high-k) and organic components. Comparing sample 1 with sample 3, the high-intensity UV light may inhibit the formation of —OH group efficiently. Benefiting from improved sol-gel formula and more powerful UV light, hybrid dielectrics in Sample 1 shows better performance than that case in ref. [8]. Then this high-quality hybrid dielectrics can meet stringent requirements for non-volatile memory devices. 
     As additional reference, in sample 4 TiO 2  NPs were dispersed into PMMA and fabricated into memory devices as dielectric layer. The evolution of CV loops under voltage stress time for sample 4 is shown in  FIG. 9D . Loop width didn&#39;t become sensitive to stress time even though the pulse of 500 ms was applied on gate. There should be strongly fixed-charge defects in dielectrics of sample 4 and be related to interfacial defects on TiO 2  NPs to PMMA. Inorganic NPs blended in polymer matrix act as charged centers has been described in [8] and these fixed charges in dielectrics will deteriorate charge-trapping-layer for floating gate memory structures. 
     This hybrid dielectrics of the present invention can also find critical applications in other thin-film transistors, or nano floating gate transistors, or planar floating gate transistors. 
     These Si/SiO 2  core/shell nanostructures of the present invention can also act as superior charge trapping points in resistive switching memory device (named as memoristor) as in ref. [9]. 
     The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art. 
     The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalence.