Patent Publication Number: US-10770792-B2

Title: Scanning antenna

Description:
TECHNICAL FIELD 
     The disclosure relates to a scanning antenna, and more particularly relates to a scanning antenna and a method for manufacturing thereof in which an antenna unit (also referred to as an “element antenna”) has a liquid crystal capacitance (also referred to as a “liquid crystal array antenna”). 
     BACKGROUND ART 
     Antennas for mobile communication and satellite broadcasting require functions that can change the beam direction (referred to as “beam scanning” or “beam steering”). An antenna (hereinafter referred to as a “scanning antenna”) having such functionality, phased array antennas equipped with antenna units are a known example. However, existing phased array antennas are expensive, which is an obstacle for popularization as a consumer product. In particular, as the number of antenna units increases, the cost rises considerably. 
     Therefore, scanning antennas that utilize the high dielectric anisotropy (birefringence) of liquid crystal materials (including nematic liquid crystals and polymer dispersed liquid crystals) have been proposed (PTL 1 to PTL 5 and NPL 1). Since the dielectric constant of liquid crystal materials has a frequency dispersion, in the present specification, the dielectric constant (also referred to as the “dielectric constant for microwaves”) is particularly denoted as “dielectric constant M(ε M )”. 
     PTL 3 and NPL 1 describe how an inexpensive scanning antenna can be obtained by using liquid crystal display (hereinafter referred to as “LCD”) device technology. 
     CITATION LIST 
     Patent Literature 
     
         
         PTL 1: JP 2007-116573 A 
         PTL 2: JP 2007-295044 A 
         PTL 3: JP 2009-538565 A 
         PTL 4: JP 2013-539949 A 
         PTL 5: WO 2015/126550 
       
    
     Non Patent Literature 
     
         
         NPL 1: R. A. Stevenson et al., “Rethinking Wireless Communications: Advanced Antenna Design using LCD Technology”, SID 2015 DIGEST. pp. 827-830. 
         NPL 2: M. ANDO et al., “A Radial Line Slot Antenna for 12 GHz Satellite TV Reception”, IEEE Transactions of Antennas and Propagation, Vol. AP-33, No. 12, pp. 1347-1353 (1985). 
       
    
     SUMMARY 
     Technical Problem 
     As described above, although the idea of realizing an inexpensive scanning antenna by applying LCD technology is known, there are no documents that specifically describe the structure, the manufacturing method, and the driving method of scanning antennas using LCD technology. 
     Accordingly, an object of the disclosure is to provide a scanning antenna which can be mass-manufactured by utilizing existing manufacturing techniques of LCDs and a manufacturing method thereof. 
     Solution to Problem 
     A scanning antenna according to an embodiment of the disclosure is a scanning antenna in which a plurality of antenna units are arranged, the scanning antenna including: a TFT substrate including a first dielectric substrate, a plurality of TFTs supported on the first dielectric substrate, a plurality of gate bus lines, a plurality of source bus lines, a plurality of patch electrodes, and a first alignment film covering the plurality of patch electrodes; a slot substrate including a second dielectric substrate, a slot electrode formed on a first main surface of the second dielectric substrate, the slot electrode including a plurality of slots arranged corresponding to the plurality of patch electrodes, and a second alignment film covering the slot electrode; a liquid crystal layer provided between the TFT substrate and the slot substrate, the liquid crystal layer containing a liquid crystal molecule having an isothiocyanate group; and a reflective conductive plate disposed to face a second main surface on an opposite side to the first main surface of the second dielectric substrate with a dielectric layer interposed therebetween, wherein the plurality of patch electrodes and the slot electrodes are each formed of a Cu layer or an Al layer, and wherein the first alignment film and the second alignment film each include a compound having an atomic group forming a coordinate bond with Cu or Al. 
     In an embodiment, at least one of the first alignment film and the second alignment film include an upper layer close to the liquid crystal layer and a lower layer, wherein the compound is contained in the lower layer. 
     A scanning antenna according to another embodiment of the disclosure is a scanning antenna in which a plurality of antenna units are arranged, the scanning antenna including: a TFT substrate including a first dielectric substrate, a plurality of TFTs supported on the first dielectric substrate, a plurality of gate bus lines, a plurality of source bus lines, a plurality of patch electrodes, and a first alignment film covering the plurality of patch electrodes; a slot substrate including a second dielectric substrate, a slot electrode formed on a first main surface of the second dielectric substrate, the slot electrode including a plurality of slots arranged corresponding to the plurality of patch electrodes, and a second alignment film covering the slot electrode; a liquid crystal layer provided between the TFT substrate and the slot substrate, the liquid crystal layer containing a liquid crystal molecule having an isothiocyanate group; and a reflective conductive plate disposed to face a second main surface of a second dielectric substrate on an opposite side to the first main surface with a dielectric layer interposed therebetween, wherein the plurality of patch electrodes and the slot electrodes are each formed of a Cu layer or an Al layer, and wherein between the first alignment film and the plurality of patch electrodes and between the second alignment film and the slot electrode are each independently provided with a resin layer containing a compound having an atomic group forming a coordinate bond with Cu or Al. 
     In an embodiment, the resin layer includes a cured acrylate. 
     In an embodiment, the compound has an amide bond and a benzene ring. 
     In an embodiment, the compound has a molecular weight of less than 1000. 
     In an embodiment, an insulating layer covering the plurality of patch electrodes and a further insulating layer covering the slot electrode are provided. 
     Advantageous Effects of Disclosure 
     According to an embodiment of the disclosure, a scanning antenna that can be mass-produced using known LCD manufacturing technologies and a method of manufacturing the scanning antenna is provided. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a cross-sectional view schematically illustrating a portion of a scanning antenna  1000  according to a first embodiment. 
         FIG. 2A  and  FIG. 2B  are schematic plan views illustrating a TFT substrate  101  and a slot substrate  201  in the scanning antenna  1000 , respectively. 
         FIG. 3A  and  FIG. 3B  are a cross-sectional view and a plane view schematically illustrating an antenna unit region U of the TFT substrate  101 , respectively. 
         FIG. 4A  to  FIG. 4C  are cross-sectional views schematically illustrating a gate terminal section GT, a source terminal section ST, and a transfer terminal section PT of the TFT substrate  101 , respectively. 
         FIG. 5  is a diagram illustrating an example of a manufacturing process of the TFT substrate  101 . 
         FIG. 6  is a cross-sectional view schematically illustrating an antenna unit region U and a terminal section IT in the slot substrate  201 . 
         FIG. 7  is a schematic cross-sectional view for illustrating a transfer section in the TFT substrate  101  and the slot substrate  201 . 
         FIG. 8A  to  FIG. 8C  are cross-sectional views illustrating the gate terminal section GT, the source terminal section ST, and the transfer terminal section PT, respectively, of a TFT substrate  102  in a second embodiment. 
         FIG. 9  is a diagram illustrating an example of a manufacturing process of the TFT substrate  102 . 
         FIG. 10A  to  FIG. 10C  are cross-sectional views illustrating the gate terminal section GT, the source terminal section ST, and the transfer terminal section PT, respectively, of a TFT substrate  103  in the third embodiment. 
         FIG. 11  is a diagram illustrating an example of a manufacturing process of the TFT substrate  103 . 
         FIG. 12  is a cross-sectional view for illustrating a transfer section in the TFT substrate  103  and a slot substrate  203 . 
         FIG. 13A  is a schematic plan view of a TFT substrate  104  including a heater resistive film  68 , and  FIG. 13B  is a schematic plan view for illustrating the sizes of slots  57  and patch electrodes  15 . 
         FIG. 14A  and  FIG. 14B  are diagrams illustrating the schematic structure and current distribution of resistance heating structures  80   a  and  80   b.    
         FIG. 15A  to  FIG. 15C  are diagrams illustrating the schematic structure and current distribution of resistance heating structures  80   c  to  80   e.    
         FIG. 16A  is a schematic cross-sectional view of the liquid crystal panel  100 Pa having the heater resistive film  68 , and  FIG. 16B  is a schematic cross-sectional view of the liquid crystal panel  100 Pb having the heater resistive film  68 . 
         FIG. 17  is a view of an equivalent circuit of one antenna unit of scanning antenna according to an embodiment of the disclosure. 
         FIGS. 18A to 18C  and  FIGS. 18E to 18G  are diagrams illustrating examples of waveforms of respective signals used for driving the scanning antenna according to an embodiment,  FIG. 18D  is a diagram illustrating the waveform of a display signal of an LCD panel driven by dot inversion driving. 
         FIGS. 19A to 19E  are diagrams illustrating another example of the waveform of each of the signals used for driving the scanning antenna of an embodiment. 
         FIGS. 20A to 20E  are diagrams illustrating still another example of the waveform of each of the signals used for driving the scanning antenna of an embodiment. 
         FIG. 21  is a schematic cross-sectional view of the liquid crystal panel  100 A included in a scanning antenna according to an embodiment of the disclosure. 
         FIG. 22  is a schematic cross-sectional view of the liquid crystal panel  100 B included in a scanning antenna according to an embodiment of the disclosure. 
         FIG. 23  is a schematic cross-sectional view of the liquid crystal panel  100 C included in a scanning antenna according to an embodiment of the disclosure. 
         FIG. 24  is a schematic cross-sectional view of the liquid crystal panel  100 D included in a scanning antenna according to an embodiment of the disclosure. 
         FIG. 25A  is a schematic diagram illustrating the structure of a known LCD  900 , and  FIG. 25B  is a schematic sectional view of the LCD panel  900   a.    
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Hereinafter, a scanning antenna and a manufacturing method thereof according to embodiments of the disclosure will be described with reference to the drawings. In the following description, first, the structure and manufacturing method of a known TFT-type LCD (hereinafter referred to as a “TFT-LCD”) will be described. However, the description of matters well-known within the technical field of LCDs may be omitted. For a description of basic LCD technology, please refer to, for example, Liquid Crystals, Applications and Uses, Vol. 1-3 (Editor: Birenda Bahadur, Publisher: World Scientific Pub Co Inc), or the like. For reference, the entire contents of the disclosures of the above documents are incorporated herein. 
     A structure and an operation of a transmissive-type TFT-LCD (hereinafter simply referred to as “LCD”)  900  having normal structure will be described with reference to  FIGS. 25A and 25B . Here, an LCD  900  with a vertical electric field mode (for example, a TN mode or a vertical alignment mode) in which a voltage is applied in a thickness direction of a liquid crystal layer is provided as an example. The frame frequency (which is typically twice the polarity inversion frequency) of the voltage applied to the liquid crystal capacitance of the LCD is 240 Hz even at quad speed driving, and the dielectric constant s of the liquid crystal layer that serves as the dielectric layer of the liquid crystal capacitance of the LCD is different from the dielectric constant M (ε M ) of microwaves (for example, satellite broadcasting, the Ku band (from 12 to 18 GHz), the K band (from 18 to 26 GHz), and the Ka band (from 26 to 40 GHz)). 
     As schematically illustrated in  FIG. 25A , the transmissive-type LCD  900  includes a liquid crystal display panel  900   a , a control circuit CNTL, a backlight (not illustrated), a power supply circuit (not illustrated), and the like. The liquid crystal display panel  900   a  includes a liquid crystal display cell LCC and a driving circuit including a gate driver GD and a source driver SD. The driving circuit may be, for example, mounted on a TFT substrate  910  of the liquid crystal display cell LCC, or all or a part of the driving circuit may be integrated (monolithic integration) with the TFT substrate  910 . 
       FIG. 25B  is a schematic cross-sectional view of a liquid crystal display panel (hereinafter referred to as “LCD panel”)  900   a  included in the LCD  900 . The LCD panel  900   a  includes the TFT substrate  910 , a counter substrate  920 , and a liquid crystal layer  930  provided therebetween. Both the TFT substrate  910  and the counter substrate  920  include transparent substrates  911  and  921 , such as glass substrates. In addition to glass substrates, plastic substrates may also be used as the transparent substrates  911  and  921  in some cases. The plastic substrates are formed of, for example, a transparent resin (for example, polyester) and a glass fiber (for example, nonwoven fabric). 
     A display region DR of the LCD panel  900   a  is configured of pixels P arranged in a matrix. A frame region FR that does not serve as part of the display is formed around the display region DR. The liquid crystal material is sealed in the display region DR by a sealing portion (not illustrated) formed surrounding the display region DR. The sealing portion is formed by curing a sealing material including, for example, an ultraviolet curable resin and a spacer (for example, resin beads or silica beads), and bonds and secures the TFT substrate  910  and the counter substrate  920  to each other. The spacer in the sealing material controls a gap between the TFT substrate  910  and the counter substrate  920 , that is, a thickness of the liquid crystal layer  930 , to be constant. To suppress an in-plane variation in the thickness of the liquid crystal layer  930 , columnar spacers are formed on light blocking portions (for example, on a wiring line) in the display region DR by using an ultraviolet curable resin. In recent years, as seen in LCD panels for liquid crystal televisions and smart phones, a width of the frame region FR that does not serve as part of the display is very narrow. 
     In the TFT substrate  910 , a TFT  912 , a gate bus line (scanning line) GL, a source bus line (display signal line) SL, a pixel electrode  914 , an auxiliary capacitance electrode (not illustrated), and a CS bus line (auxiliary capacitance line) (not illustrated) are formed on the transparent substrate  911 . The CS bus line is provided parallel to the gate bus line. Alternatively, the gate bus line of the next stage may be used as the CS bus line (CS on-gate structure). 
     The pixel electrode  914  is covered with an alignment film (for example, a polyimide film) for controlling the alignment of the liquid crystals. The alignment film is provided so as to be in contact with the liquid crystal layer  930 . The TFT substrate  910  is often disposed on the backlight side (the side opposite to the viewer). 
     The counter substrate  920  is often disposed on the observer side of the liquid crystal layer  930 . The counter substrate  920  includes a color filter layer (not illustrated), a counter electrode  924 , and an alignment film (not illustrated) on the transparent substrate  921 . Since the counter electrode  924  is provided in common to a plurality of pixels P constituting the display region DR, it is also referred to as a common electrode. The color filter layer includes a color filter (for example, a red filter, a green filter, and a blue filter) provided for each pixel P, and a black matrix (light shielding layer) for blocking light unnecessary for display. The black matrix is arranged, for example, so as to block light between the pixels P in the display region DR and at the frame region FR. 
     The pixel electrode  914  of the TFT substrate  910 , the counter electrode  924  of the counter substrate  920 , and the liquid crystal layer  930  therebetween constitute a liquid crystal capacitance Clc. Individual liquid crystal capacitances correspond to the pixels. To retain the voltage applied to the liquid crystal capacitance Clc (so as to increase what is known as the voltage holding rate), an auxiliary capacitance CS electrically connected in parallel with the liquid crystal capacitance Clc is formed. The auxiliary capacitance CS is typically composed of an electrode having the same potential as the pixel electrode  914 , an inorganic insulating layer (for example, a gate insulating layer (SiO 2  layer)), and an auxiliary capacitance electrode connected to the CS bus line. Typically, the same common voltage as the counter electrode  924  is supplied from the CS bus line. 
     Factors responsible for lowering the voltage (effective voltage) applied to the liquid crystal capacitance Clc are (1) those based on the CR time constant which is the product of the capacitance value C Clc  of the liquid crystal capacitance Clc and the resistance value R, and (2) interfacial polarization due to ionic impurities included in the liquid crystal material and/or the orientation polarization of liquid crystal molecules. Among these, the contribution of the CR time constant of the liquid crystal capacitance Clc is large, and the CR time constant can be increased by providing an auxiliary capacitance CS electrically connected in parallel with the liquid crystal capacitance Clc. Note that the volume resistivity of the liquid crystal layer  930  that serves as the dielectric layer of the liquid crystal capacitance Clc exceeds the order of 10 12  Ω·cm in the case of widely used nematic liquid crystal materials. 
     A display signal supplied to the pixel electrode  914  is a display signal that is supplied to the source bus line SL connected to the TFT  912  when the TFT  912  selected by a scanning signal supplied from the gate driver GD to the gate bus line GL is turned on. Accordingly, the TFTs  912  connected to a particular gate bus line GL are simultaneously turned on, and at that time, corresponding display signals are supplied from the source bus lines SL connected to the respective TFTs  912  of the pixels P in that row. By performing this operation sequentially from the first row (for example, the uppermost row of a display surface) to the mth row (for example, the lowermost row of the display surface), one image (frame) is written in the display region DR composed of m rows of pixels and is displayed. Assuming that the pixels P are arranged in a matrix of m rows and n columns, at least n source bus lines SL are provided in total such that at least one source bus line SL corresponds to each pixel column. 
     Such scanning is referred to as line-sequential scanning, a time between one pixel row being selected and the next pixel row being selected is called a horizontal scan period, (1H), and a time between a particular row being selected and then being selected a second time is called a vertical scanning period, (1V), or a frame. Note that, in general, 1V (or 1 frame) is obtained by adding the blanking period to the period m·H for selecting all m pixel rows. 
     For example, when an input video signal is an NTSC signal, 1V (=1 frame) of an existing LCD panel is 1/60 of a second (16.7 milliseconds). The NTSC signals are interlaced signals, the frame frequency is 30 Hz, and the field frequency is 60 Hz, but in LCD panels, since it is necessary to supply display signals to all the pixels in each field, they are driven with 1V=( 1/60) second (driven at 60 Hz). Note that, in recent years, to improve the video display characteristics, there are LCD panels driven at double speed drive (120 Hz drive, 1V=( 1/120 second)), and some LCD panels are driven at quad speed (240 Hz drive, 1V=( 1/240 second)) for 3D displays. 
     When a DC voltage is applied to the crystal layer  930 , the effective voltage decreases and the luminance of the pixel P decreases. Since the above-mentioned interface polarization and/or the orientation polarization contribute to the decrease in the effective voltage, it is difficult for the auxiliary capacitance CS to prevent the decrease in the effective voltage completely. For example, when a display signal corresponding to a particular intermediate gray scale is written into every pixel in every frame, the luminance fluctuates for each frame and is observed as flicker. In addition, when a DC voltage is applied to the liquid crystal layer  930  for an extended period of time, electrolysis of the liquid crystal material may occur. Furthermore, impurity ions segregate at one side of the electrode, so that the effective voltage may not be applied to the liquid crystal layer and the liquid crystal molecules may not move. To prevent this, the LCD panel  900   a  is subjected to so-called AC driving. Typically, frame-reversal driving is performed in which the polarity of the display signal is inverted every frame (every vertical scanning period). For example, in existing LCD panels, the polarity inversion is performed every 1/60 seconds (a polarity inversion cycle is 30 Hz). 
     In addition, dot inversion driving, line reversal driving, or the like is performed in order to uniformly distribute the pixels having different polarities of applied voltages even within one frame. This is because it is difficult to completely match the magnitude of the effective voltage applied to the liquid crystal layer between a positive polarity and a negative polarity. For example, in a case where the volume resistivity of the liquid crystal material exceeds the order of 10 12  Ω·cm, flicker is hardly recognizable in a case where dot inversion or line reversal driving is performed every 1/60 seconds. 
     With respect to the scanning signal and the display signal in the LCD panel  900   a , on the basis of the signals supplied from the control circuit CNTL to the gate driver GD and the source driver SD, the gate driver GD and the source driver SD supply the scanning signal and the display signal to the gate bus line GL and the source bus line SL, respectively. For example, the gate driver GD and the source driver SD are each connected to corresponding terminals provided on the TFT substrate  910 . The gate driver GD and the source driver SD may be mounted on the frame region FR of the TFT substrate  910  as a driver IC, for example, or may be monolithically formed in the frame region FR of the TFT substrate  910 . 
     The counter electrode  924  of the counter substrate  920  is electrically connected to a terminal (not illustrated) of the TFT substrate  910  with a conductive portion (not illustrated) known as a transfer therebetween. The transfer is formed, for example, so as to overlap with the sealing portion, or alternatively so as to impart conductivity to a part of the sealing portion. This is done to narrow the frame region FR. A common voltage is directly or indirectly supplied to the counter electrode  924  from the control circuit CNTL. Typically, the common voltage is also supplied to the CS bus line as described above. 
     Basic Structure of Scanning Antenna 
     By controlling the voltage applied to each liquid crystal layer of each antenna unit corresponding to the pixels of the LCD panel and changing the effective dielectric constant M (ε M ) of the liquid crystal layer for each antenna unit, a scanning antenna equipped with an antenna unit that uses the anisotropy (birefringence index) of a large dielectric constant M (ε M ) of a liquid crystal material forms a two-dimensional pattern by antenna units with different capacities (corresponding to displaying of an image by an LCD). An electromagnetic wave (for example, a microwave) emitted from an antenna or received by an antenna is given a phase difference depending on the electrostatic capacitance of each antenna unit, and gains a strong directivity in a particular direction depending on the two-dimensional pattern formed by the antenna units having different electrostatic capacitances (beam scanning). For example, an electromagnetic wave emitted from an antenna is obtained by integrating, with consideration for the phase difference provided by each antenna unit, spherical waves obtained as a result of input electromagnetic waves entering each antenna unit and being scattered by each antenna unit. It can be considered that each antenna unit functions as a “phase shifter”. For a description of the basic structure and operating principles of a scanning antenna that uses a liquid crystal material, refer to PTL 1 to PTL 4 as well as NPL 1 and NPL 2. NPL 2 discloses the basic structure of a scanning antenna in which spiral slots are arranged. For reference, the entire contents of the disclosures of PTL 1 to PTL 4 as well as NPL 1 and NPL 2 are incorporated herein. 
     Note that although the antenna units in the scanning antenna according to the embodiments of the disclosure are similar to the pixels of the LCD panel, the structure of the antenna units is different from the structure of the pixel of the LCD panel, and the arrangement of the plurality of antenna units is also different from the arrangement of the pixels in the LCD panel. A basic structure of the scanning antenna according to the embodiments of the disclosure will be described with reference to  FIG. 1 , which illustrates a scanning antenna  1000  of a first embodiment to be described in detail later. Although the scanning antenna  1000  is a radial in-line slot antenna in which slots are concentrically arranged, the scanning antennas according to the embodiments of the disclosure are not limited to this. For example, the arrangement of the slots may be any of various known arrangements. In particular, with respect to the slot and/or antenna unit arrangements, the entire disclosure of PTL 5 is incorporated herein by reference. 
       FIG. 1  is a cross-sectional view schematically illustrating a portion of the scanning antenna  1000  of the present embodiment, and schematically illustrates a part of the cross-section along the radial direction from a power feed pin  72  (see  FIG. 2B ) provided near the center of the concentrically arranged slots. 
     The scanning antenna  1000  includes a TFT substrate  101 , a slot substrate  201 , a liquid crystal layer LC provided therebetween, and a reflective conductive plate  65  opposing the slot substrate  201  with an air layer  54  interposed between the slot substrate  210  and the reflective conductive plate  65 . The scanning antenna  1000  transmits and receives microwaves from a side closer to the TFT substrate  101 . 
     The TFT substrate  101  includes a dielectric substrate  1  such as a glass substrate, a plurality of patch electrodes  15  and a plurality of TFTs  10  formed on the dielectric substrate  1 . Each patch electrode  15  is connected to a corresponding TFT  10 . Each TFT  10  is connected to a gate bus line and a source bus line. 
     The slot substrate  201  includes a dielectric substrate  51  such as a glass substrate and a slot electrode  55  formed on a side of the dielectric substrate  51  closer to the liquid crystal layer LC. The slot electrode  55  includes a plurality of slots  57 . 
     The reflective conductive plate  65  is disposed opposing the slot substrate  201  with the air layer  54  interposed between the reflective conductive plate  65  and the slot substrate  201 . In place of the air layer  54 , a layer formed of a dielectric (for example, a fluorine resin such as PTFE) having a small dielectric constant M for microwaves can be used. The slot electrode  55 , the reflective conductive plate  65 , and the dielectric substrate  51  and the air layer  54  therebetween function as a waveguide  301 . 
     The patch electrode  15 , the portion of the slot electrode  55  including the slot  57 , and the liquid crystal layer LC therebetween constitute an antenna unit U. In each antenna unit U, one patch electrode  15  is opposed to a portion of the slot electrode  55  including one slot  57  with a liquid crystal layer LC interposed therebetween, thereby constituting the liquid crystal capacitance. The structure in which the patch electrode  15  and the slot electrode  55  face each other with the liquid crystal layer LC interposed therebetween is similar to the structure in which the pixel electrode  914  and the counter electrode  924  of the LCD panel  900   a  illustrated in  FIG. 25A  and  FIG. 25B  face each other with the liquid crystal layer  930  interposed therebetween. That is, the antenna unit U of the scanning antenna  1000  and the pixel P of the LCD panel  900   a  have a similar configuration. In addition, the antenna unit has a configuration similar to that of the pixel P in the LCD panel  900   a  in that the antenna unit has an auxiliary capacitance electrically connected in parallel with the liquid crystal capacitance (see  FIG. 13A  and  FIG. 17 ). However, the scanning antenna  1000  has many differences from the LCD panel  900   a.    
     First, the performance required for the dielectric substrates  1  and  51  of the scanning antenna  1000  is different from the performance required for the substrate of the LCD panel. 
     Generally, transparent substrates that are transparent to visible light are used for LCD panels. For example, glass substrates or plastic substrates are used. In reflective LCD panels, since the substrate on the back side does not need transparency, a semiconductor substrate may be used in some cases. In contrast to this, it is preferable for the dielectric substrates  1  and  51  used for the antennas to have small dielectric losses with respect to microwaves (where the dielectric tangent with respect to microwaves is denoted as tan δ M ). The tan δ M  of the dielectric substrates  1  and  51  is preferably approximately less than or equal to 0.03, and more preferably less than or equal to 0.01. Specifically, a glass substrate or a plastic substrate can be used. Glass substrates are superior to plastic substrates with respect to dimensional stability and heat resistance, and are suitable for forming circuit elements such as TFTs, a wiring line, and electrodes using LCD technology. For example, in a case where the materials forming the waveguide are air and glass, as the dielectric loss of glass is greater, from the viewpoint that thinner glass can reduce the waveguide loss, it is preferable for the thickness to be less than or equal to 400 μm, and more preferably less than or equal to 300 μm. There is no particular lower limit, provided that the glass can be handled such that it does not break in the manufacturing process. 
     The conductive material used for the electrode is also different. In many cases, an ITO film is used as a transparent conductive film for pixel electrodes and counter electrodes of LCD panels. However, ITO has a large tan δ M  with respect to microwaves, and as such cannot be used as the conductive layer in an antenna. The slot electrode  55  functions as a wall for the waveguide  301  together with the reflective conductive plate  65 . Accordingly, to suppress the transmission of microwaves in the wall of the waveguide  301 , it is preferable that the thickness of the wall of the waveguide  301 , that is, the thickness of the metal layer (Cu layer or Al layer) be large. It is known that in a case where the thickness of the metal layer is three times the skin depth, electromagnetic waves are attenuated to 1/20 (−26 dB), and in a case where the thickness is five times the skin depth, electromagnetic waves are attenuated to about 1/150 (−43 dB). Accordingly, in a case where the thickness of the metal layer is five times the skin depth, the transmittance of electromagnetic waves can be reduced to 1%. For example, for a microwave of 10 GHz, in a case where a Cu layer having a thickness of greater than or equal to 3.3 μm and an Al layer having a thickness of greater than or equal to 4.0 μm are used, microwaves can be reduced to 1/150. In addition, for a microwave of 30 GHz, in a case where a Cu layer having a thickness of greater than or equal to 1.9 μm and an Al layer having a thickness of greater than or equal to 2.3 μm are used, microwaves can be reduced to 1/150. In this way, the slot electrode  55  is preferably formed of a relatively thick Cu layer or Au layer. There is no particular upper limit for the thickness of the Cu layer or the Al layer, and the thicknesses can be set appropriately in consideration of the time and cost of film formation. The usage of a Cu layer provides the advantage of being thinner than the case of using an Al layer. Relatively thick Cu layers or Al layers can be formed not only by the thin film deposition method used in LCD manufacturing processes, but also by other methods such as bonding Cu foil or Al foil to the substrate. The thickness of the metal layer, for example, ranges from 2 μm to 30 μm. When the thin film deposition methods are used, the thickness of the metal layer is preferably less than or equal to 5 μm. Note that aluminum plates, copper plates, or the like having a thickness of several mm can be used as the reflective conductive plate  65 , for example. 
     Since the patch electrode  15  does not configure the waveguide  301  like the slot electrode  55 , a Cu layer or an Al layer can be used that has a smaller thickness than that of the slot electrode  55 . However, to avoid losses caused by heat when the oscillation of free electrons near the slot  57  of the slot electrode  55  induces the oscillation of the free electrons in the patch electrode  15 , it is preferable that the resistance be low. From the viewpoint of mass production, it is preferable to use an Al layer rather than a Cu layer, and the thickness of the Al layer is preferably greater than or equal to 0.3 μm and less than or equal to 2 μm, for example. 
     In addition, an arrangement pitch of the antenna units U is considerably different from that of a pixel pitch. For example, considering an antenna for microwaves of 12 GHz (Ku band), the wavelength λ is 25 mm, for example. Then, as described in PTL 4, since the pitch of the antenna unit U is less than or equal to λ/4 and/or less than or equal to λ/5, the arrangement pitch becomes less than or equal to 6.25 mm and/or less than or equal to 5 mm. This is ten times greater than the pixel pitch of the LCD panel. Accordingly, the length and width of the antenna unit U are also roughly ten times greater than the pixel length and width of the LCD panel. 
     Of course, the arrangement of the antenna units U may be different from the arrangement of the pixels in the LCD panel. Herein, although an example is illustrated in which the antenna units U are arranged in concentric circles (for example, refer to JP 2002-217640 A), the present disclosure is not limited thereto, and the antenna units may be arranged in a spiral shape as described in NPL 2, for example. Furthermore, the antenna units may be arranged in a matrix as described in PTL 4. 
     The properties required for the liquid crystal material of the liquid crystal layer LC of the scanning antenna  1000  are different from the properties required for the liquid crystal material of the LCD panel. In the LCD panel, a change in a refractive index of the liquid crystal layer of the pixels allows a phase difference to be provided to the polarized visible light (wavelength of from 380 nm to 830 nm) such that the polarization state is changed (for example, the change in the refractive index allows the polarization axis direction of linearly polarized light to be rotated or the degree of circular polarization of circularly polarized light to be changed), whereby display is performed. In contrast, in the scanning antenna  1000  according to the embodiment, the phase of the microwave excited (re-radiated) from each patch electrode is changed by changing the electrostatic capacitance value of the liquid crystal capacitance of the antenna unit U. Accordingly, the liquid crystal layer preferably has a large anisotropy (Δε M ) of the dielectric constant M (ε M ) with respect to microwaves, and δ M  is preferably small. For example, the Δε M  of greater than or equal to 4 and the δ M  of less than or equal to 0.02 (values of 19 GHz in both cases) described in SID 2015 DIGEST pp. 824-826 written by M. Witteck et al, can be suitably used. In addition, it is possible to use a liquid crystal material having a Δε M  of greater than or equal to 0.4 and a δ M  of less than or equal to 0.04 as described in POLYMERS 55 vol. August issue pp. 599-602 (2006), written by Kuki. 
     In general, the dielectric constant of a liquid crystal material has a frequency dispersion, but the dielectric anisotropy Δε M  for microwaves has a positive correlation with the refractive index anisotropy Δn with respect to visible light. Accordingly, it can be said that a material having a large refractive index anisotropy Δn with respect to visible light is preferable as a liquid crystal material for an antenna unit for microwaves. The refractive index anisotropy Δn of the liquid crystal material for LCDs is evaluated by the refractive index anisotropy for light having a wavelength of 550 nm. Here again, when a Δn (birefringence index) is used as an index for light having a wavelength of 550 nm, a nematic liquid crystal having a Δn of greater than or equal to 0.3, preferably greater than or equal to 0.4, can be used for an antenna unit for microwaves. An has no particular upper limit. However, since liquid crystal materials having a large Δn tend to have a strong polarity, there is a possibility that reliability may decrease. From the viewpoint of reliability, Δn is preferably less than or equal to 0.4. The thickness of the liquid crystal layer is, for example, from 1 μm to 500 μm. 
     Hereinafter, the structure and manufacturing method of the scanning antenna according to the embodiments of the disclosure will be described in more detail. 
     First Embodiment 
     First, a description is given with reference to  FIG. 1  and  FIGS. 2A and 2B .  FIG. 1  is a schematic partial cross-sectional view of the scanning antenna  1000  near the center thereof as described above, and  FIG. 2A  and  FIG. 2B  are schematic plan views illustrating the TFT substrate  101  and the slot substrate  201  in the scanning antenna  1000 , respectively. 
     The scanning antenna  1000  includes a plurality of antenna units U arranged two-dimensionally. In the scanning antenna  1000  exemplified here, the plurality of antenna units are arranged concentrically. In the following description, the region of the TFT substrate  101  and the region of the slot substrate  201  corresponding to the antenna units U will be referred to as “antenna unit region”, and be denoted with the same reference numeral U as the antenna units. In addition, as illustrated in  FIG. 2A  and  FIG. 2B , in the TFT substrate  101  and the slot substrate  201 , a region defined by the plurality of two-dimensionally arranged antenna unit regions is referred to as “transmission and/or reception region R 1 ”, and a region other than the transmission and/or reception region R 1  is called a “non-transmission and/or reception region R 2 ”. A terminal section, a driving circuit, and the like are provided in the non-transmission and/or reception region R 2 . 
       FIG. 2A  is a schematic plan view illustrating the TFT substrate  101  in the scanning antenna  1000 . 
     In the illustrated example, the transmission and/or reception region R 1  has a donut-shape when viewed from a normal direction of the TFT substrate  101 . The non-transmission and/or reception region R 2  includes a first non-transmission and/or reception region R 2   a  located at the center of the transmission and/or reception region R 1  and a second non-transmission and/or reception region R 2   b  located at the periphery of the transmission and/or reception region R 1 . An outer diameter of the transmission and/or reception region R 1 , for example, is from 200 mm to 1500 mm, and is configured according to a data traffic volume or the like. 
     A plurality of gate bus lines GL and a plurality of source bus lines SL supported by the dielectric substrate  1  are provided in the transmission and/or reception region R 1  of the TFT substrate  101 , and the antenna unit regions U are defined by these wiring lines. The antenna unit regions U are, for example, arranged concentrically in the transmission and/or reception region R 1 . Each of the antenna unit regions U includes a TFT and a patch electrode electrically connected to the TFT. The source electrode of the TFT is electrically connected to the source bus line SL, and the gate electrode is electrically connected to the gate bus line GL. In addition, the drain electrode is electrically connected to the patch electrode. 
     In the non-transmission and/or reception region R 2  (R 2   a , R 2   b ), a seal region Rs is disposed surrounding the transmission and/or reception region R 1 . A sealing material (not illustrated) is applied to the seal region Rs. The sealing material bonds the TFT substrate  101  and the slot substrate  201  to each other, and also encloses liquid crystals between these substrates  101 ,  201 . 
     A gate terminal section GT, the gate driver GD, a source terminal section ST, and the source driver SD are provided outside the sealing region Rs in the non-transmission and/or reception region R 2 . Each of the gate bus lines GL is connected to the gate driver GD with the gate terminal section GT therebetween. Each of the source bus lines SL is connected to the source driver SD with the source terminal section ST therebetween. Note that, in this example, although the source driver SD and the gate driver GD are formed on the dielectric substrate  1 , one or both of these drivers may be provided on another dielectric substrate. 
     Also, a plurality of transfer terminal sections PT are provided in the non-transmission and/or reception region R 2 . The transfer terminal section PT is electrically connected to the slot electrode  55  ( FIG. 2B ) of the slot substrate  201 . In the present specification, the connection section between the transfer terminal section PT and the slot electrode  55  is referred to as a “transfer section”. As illustrated in drawings, the transfer terminal section PT (transfer section) may be disposed in the seal region Rs. In this case, a resin containing conductive particles may be used as the sealing material. In this way, liquid crystals are sealed between the TFT substrate  101  and the slot substrate  201 , and an electrical connection can be secured between the transfer terminal section PT and the slot electrode  55  of the slot substrate  201 . In this example, although a transfer terminal section PT is disposed in both the first non-transmission and/or reception region R 2   a  and the second non-transmission and/or reception region R 2   b , the transfer terminal section PT may be disposed in only one of them. 
     Note that the transfer terminal section PT (transfer section) need not be disposed in the seal region Rs. For example, the transfer terminal section PT may be disposed outside the seal region Rs in the non-transmission and/or reception region R 2 . 
       FIG. 2B  is a schematic plan view illustrating the slot substrate  201  in the scanning antenna  1000 , and illustrates the surface of the slot substrate  201  closer to the liquid crystal layer LC. 
     In the slot substrate  201 , the slot electrode  55  is formed on the dielectric substrate  51  extending across the transmission and/or reception region R 1  and the non-transmission and/or reception region R 2 . 
     In the transmission and/or reception region R 1  of the slot substrate  201 , a plurality of slots  57  are formed in the slot electrode  55 . The slots  57  are formed corresponding to the antenna unit region U on the TFT substrate  101 . For the plurality of slots  57  in the illustrated example, a pair of slots  57  extending in directions substantially orthogonal to each other are concentrically disposed so that a radial inline slot antenna is configured. Since the scanning antenna  1000  includes slots that are substantially orthogonal to each other, the scanning antenna  1000  can transmit and receive circularly polarized waves. 
     A plurality of terminal sections IT of the slot electrode  55  are provided in the non-transmission and/or reception region R 2 . The terminal section IT is electrically connected to the transfer terminal section PT ( FIG. 2A ) of the TFT substrate  101 . In this example, the terminal section IT is disposed within the seal region Rs, and is electrically connected to a corresponding transfer terminal section PT by a sealing material containing conductive particles. 
     In addition, the power feed pin  72  is disposed on a rear surface side of the slot substrate  201  in the first non-transmission and/or reception region R 2   a . The power feed pin  72  allows microwaves to be inserted into the waveguide  301  constituted by the slot electrode  55 , the reflective conductive plate  65 , and the dielectric substrate  51 . The power feed pin  72  is connected to a power feed device  70 . Power feeding is performed from the center of the concentric circle in which the slots  57  are arranged. The power feed method may be either a direct coupling power feed method or an electromagnetic coupling method, and a known power feed structure can be utilized. 
     In  FIG. 2A  and  FIG. 2B , an example is illustrated in which the seal region Rs is provided so as to surround a relatively narrow region including the transmission and/or reception region R 1 , but the arrangement of the seal region Rs is not limited to this. In particular, the seal region Rs provided outside the transmission and/or reception region R 1  may be provided nearby the side of the dielectric substrate  1  and/or the dielectric substrate  51 , for example, so as to maintain a certain distance or more from the transmission and/or reception region R 1 . Of course, the terminal section and the driving circuit, for example, that are provided in the non-transmission and/or reception region R 2  may be formed outside the seal region Rs (that is, the side where the liquid crystal layer is not present). By forming the seal region Rs at a position separated from the transmission and/or reception region R 1  by a certain distance or more, it is possible to prevent the antenna characteristics from deteriorating due to the influence of impurities (in particular, ionic impurities) contained in the sealing material (in particular, a curable resin). 
     In the following, each component of the scanning antenna  1000  will be described in detail with reference to drawings. 
     Structure of TFT Substrate  101   
     Antenna Unit Region U 
       FIG. 3A  and  FIG. 3B  are a cross-sectional view and a plane view schematically illustrating the antenna unit region U of the TFT substrate  101 , respectively. 
     Each of the antenna unit regions U includes a dielectric substrate (not illustrated), a TFT  10  supported by the dielectric substrate, a first insulating layer  11  covering the TFT  10 , a patch electrode  15  formed on the first insulating layer  11  and electrically connected to the TFT  10 , and a second insulating layer  17  covering the patch electrode  15 . The TFT  10  is disposed, for example, at or near an intersection of the gate bus line GL and the source bus line SL. 
     The TFT  10  include a gate electrode  3 , an island-shaped semiconductor layer  5 , a gate insulating layer  4  disposed between the gate electrode  3  and the semiconductor layer  5 , a source electrode  7 S, and a drain electrode  7 D. The structure of the TFT  10  is not particularly limited to a specific structure. In this example, the TFT  10  is a channel etch-type TFT having a bottom gate structure. 
     The gate electrode  3  is electrically connected to the gate bus line GL, and a scanning signal is supplied via the gate bus line GL. The source electrode  7 S is electrically connected to the source bus line SL, and a data signal is supplied via the source bus line SL. The gate electrode  3  and the gate bus line GL may be formed of the same conductive film (gate conductive film). The source electrode  7 S, the drain electrode  7 D, and the source bus line SL may be formed from the same conductive film (source conductive film). The gate conductive film and the source conductive film are, for example, metal films. In the present specification, layers formed using a gate conductive film may be referred to as “gate metal layers”, and layers formed using a source conductive film may be referred to as “source metal layers”. 
     The semiconductor layer  5  is disposed overlapping with the gate electrode  3  with the gate insulating layer  4  interposed therebetween. In the illustrated example, a source contact layer  6 S and a drain contact layer  6 D are formed on the semiconductor layer  5 . The source contact layer  6 S and the drain contact layer  6 D are disposed on both sides of a region where a channel is formed in the semiconductor layer  5  (channel region). The semiconductor layer  5  may be an intrinsic amorphous silicon (i-a-Si) layer, and the source contact layer  6 S and the drain contact layer  6 D may be n +  type amorphous silicon (n + -a-Si) layers. 
     The source electrode  7 S is provided in contact with the source contact layer  6 S and is connected to the semiconductor layer  5  with the source contact layer  6 S interposed therebetween. The drain electrode  7 D is provided in contact with the drain contact layer  6 D and is connected to the semiconductor layer  5  with the drain contact layer  6 D interposed therebetween. 
     The first insulating layer  11  includes a contact hole CH 1  that at least reaches the drain electrode  7 D of the TFT  10 . 
     The patch electrode  15  is provided on the first insulating layer  11  and within the contact hole CH 1 , and is in contact with the drain electrode  7 D in the contact hole CH 1 . The patch electrode  15  includes a metal layer. The patch electrode  15  may be a metal electrode formed only from a metal layer. The material of the patch electrode  15  may be the same as that of the source electrode  7 S and the drain electrode  7 D. However, a thickness of the metal layer in the patch electrode  15  (a thickness of the patch electrode  15  when the patch electrode  15  is a metal electrode) is set to be greater than thicknesses of the source electrode  7 S and the drain electrode  7 D. The thickness of the metal layer in the patch electrode  15  is set to, for example, greater than or equal to 0.3 μm when it is formed of an Al layer. 
     A CS bus line CL may be provided using the same conductive film as that of the gate bus line GL. The CS bus line CL may be disposed overlapping with the drain electrode (or extended portion of the drain electrode)  7 D with the gate insulating layer  4  interposed therebetween, and may constitute the auxiliary capacitance CS having the gate insulating layer  4  as a dielectric layer. 
     An alignment mark (for example, a metal layer)  21  and a base insulating film  2  covering the alignment mark  21  may be formed at a position closer to the dielectric substrate than a position of the gate bus line GL. The alignment mark  21  is used as follows. When manufacturing m TFT substrates from one glass substrate, in a case where the number of photomasks is n (where n&lt;m), for example, it is necessary to perform each exposure process multiple times. In this way, when the number (n) of photomasks is less than the number (m) of TFT substrates  101  manufactured from one glass substrate  1 , the alignment mark  21  can be used for alignment of the photomasks. The alignment mark  21  may be omitted. 
     In the present embodiment, the patch electrode  15  is formed in a layer different from the source metal layer. This provides the advantages described below. 
     Since the source metal layer is typically formed using a metal film, it is conceivable to form a patch electrode in the source metal layer. However, it is preferable that the patch electrode have a low resistance to the extent that the vibration of electrons is not hindered. The patch electrode is formed of a comparatively thick Al layer having a thickness of greater than or equal to 0.3 μm, for example. From the viewpoint of antenna performance, it is preferable that the patch electrode be thick. Depending on the configuration of the TFT, however, when a patch electrode having a thickness exceeding 1 μm is formed in the source metal layer, a problem arises in that the desired patterning accuracy cannot be obtained. For example, there may be a problem that the gap between the source electrode and the drain electrode (corresponding to the channel length of the TFT) cannot be controlled with high accuracy. In contrast, in the present embodiment, since the patch electrode  15  is formed separately from the source metal layer, the thickness of the source metal layer and the thickness of the patch electrode  15  can be controlled independently. This allows the controllability for forming the source metal layer to be secured and a patch electrode  15  having a desired thickness to be formed. 
     In the present embodiment, the thickness of the patch electrode  15  can be set with a high degree of freedom separately from the thickness of the source metal layer. Note that since the size of the patch electrode  15  needs not be controlled as strictly as the source bus line SL or the like, it is acceptable for the line width shift (deviation from the design value) to be increased by thickening the patch electrode  15 . Note that a case where the thickness of the patch electrode  15  is equal to the thickness of the source metal layer is not excluded. 
     The patch electrode  15  may include a Cu layer or an Al layer as a main layer. A performance of the scanning antenna correlates with an electric resistance of the patch electrode  15 , and a thickness of the main layer is set so as to obtain a desired resistance. In terms of the electric resistance, there is a possibility that the thickness of the patch electrode  15  can be made thinner in the Cu layer than in the Al layer. 
     Gate Terminal Section GT, Source Terminal Section ST, and Transfer Terminal Section PT 
       FIG. 4A  to  FIG. 4C  are cross-sectional views schematically illustrating the gate terminal section GT, the source terminal section ST, and the transfer terminal section PT, respectively. 
     The gate terminal section GT includes a gate bus line GL formed on the dielectric substrate, an insulating layer covering the gate bus line GL, and a gate terminal upper connection section  19   g . The gate terminal upper connection section  19   g  is in contact with the gate bus line GL within the contact hole CH 2  formed in the insulating layer. In this example, the insulating layer covering the gate bus line GL includes the gate insulating layer  4 , the first insulating layer  11  and the second insulating layer  17  in that order from the dielectric substrate side. The gate terminal upper connection section  19   g  is, for example, a transparent electrode formed of a transparent conductive film provided on the second insulating layer  17 . 
     The source terminal section ST includes the source bus line SL formed on the dielectric substrate (here, on the gate insulating layer  4 ), the insulating layer covering the source bus line SL, and the source terminal upper connection section  19   s . The source terminal upper connection section  19   s  is in contact with the source bus line SL within the contact hole CH 3  formed in the insulating layer. In this example, the insulating layer covering the source bus line SL includes the first insulating layer  11  and the second insulating layer  17 . The source terminal upper connection section  19   s  is, for example, a transparent electrode formed of a transparent conductive film provided on the second insulating layer  17 . 
     The transfer terminal section PT includes a patch connection section  15   p  formed on the first insulating layer  11 , the second insulating layer  17  covering the patch connection section  15   p , and a transfer terminal upper connection section  19   p . The transfer terminal upper connection section  19   p  is in contact with the patch connection section  15   p  within a contact hole CH 4  formed in the second insulating layer  17 . The patch connection section  15   p  is formed of the same conductive film as that of the patch electrode  15 . The transfer terminal upper connection section (also referred to as an upper transparent electrode)  19   p  is, for example, a transparent electrode formed of a transparent conductive film provided on the second insulating layer  17 . In the present embodiment, the upper connection sections  19   g ,  19   s , and  19   p  for the respective terminal sections are formed of the same transparent conductive film. 
     In the present embodiment, it is advantageous that the contact holes CH 2 , CH 3 , and CH 4  of the respective terminal sections can be simultaneously formed by the etching process after the formation of the second insulating layer  17 . The detailed manufacturing process thereof will be described later. 
     TFT Substrate  101  Manufacturing Method 
     As an example, the TFT substrate  101  can be manufactured by the following method.  FIG. 5  is a diagram exemplifying the manufacturing process of the TFT substrate  101 . 
     First, a metal film (for example, a Ti film) is formed on a dielectric substrate and patterned to form an alignment mark  21 . A glass substrate, a plastic substrate (resin substrate) having heat resistance, or the like can be used as the dielectric substrate, for example. Next, the base insulating film  2  is formed so as to cover the alignment mark  21 . An SiO 2  film is used as the base insulating film  2 . 
     Subsequently, a gate metal layer including the gate electrode  3  and the gate bus line GL is formed on the base insulating film  2 . 
     The gate electrode  3  can be formed integrally with the gate bus line GL. Here, a non-illustrated gate conductive film (with a thickness of greater than or equal to 50 nm and less than or equal to 500 nm) is formed on the dielectric substrate by a sputtering method or the like. Next, the gate conductive film is patterned to obtain the gate electrode  3  and the gate bus line GL. The material of the gate conductive film is not particularly limited to a specific material. A film containing a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), an alloy thereof, or alternatively a metal nitride thereof can be appropriately used. Here, as a gate conductive film, a layered film is formed by layering MoN (having a thickness of 50 nm, for example), Al (having a thickness of 200 nm, for example), and MoN (having a thickness of 50 nm, for example) in this order. 
     Next, the gate insulating layer  4  is formed so as to cover the gate metal layer. The gate insulating layer  4  can be formed by a CVD method or the like. As the gate insulating layer  4 , a silicon oxide (SiO 2 ) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy; x&gt;y) layer, a silicon nitride oxide (SiNxOy; x&gt;y) layer, or the like may be used as appropriate. The gate insulating layer  4  may have a layered structure. Here, a SiNx layer (having a thickness of 410 nm, for example) is formed as the gate insulating layer  4 . 
     Next, the semiconductor layer  5  and a contact layer are formed on the gate insulating layer  4 . Here, an intrinsic amorphous silicon film (with a thickness of 125 nm, for example) and an n +  type amorphous silicon film (with a thickness of 65 nm, for example) are formed in this order and patterned to obtain an island-shaped semiconductor layer  5  and a contact layer. The semiconductor film used for the semiconductor layer  5  is not limited to an amorphous silicon film. For example, an oxide semiconductor layer may be formed as the semiconductor layer  5 . In this case, it is not necessary to provide a contact layer between the semiconductor layer  5  and the source/drain electrodes. 
     Next, a source conductive film (having a thickness of greater than or equal to 50 nm and less than or equal to 500 nm, for example) is formed on the gate insulating layer  4  and the contact layer, and patterned to form a source metal layer including the source electrode  7 S, the drain electrode  7 D, and the source bus line SL. At this time, the contact layer is also etched, and the source contact layer  6 S and the drain contact layer  6 D separated from each other are formed. 
     The material of the source conductive film is not particularly limited to a specific material. A film containing a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), an alloy thereof, or alternatively a metal nitride thereof can be appropriately used. Here, as a source conductive film, a layered film is formed by layering MoN (having a thickness of 30 nm, for example), Al (having a thickness of 200 nm, for example), and MoN (having a thickness of 50 nm, for example) in this order. Instead, as a source conductive film, a layered film may be formed by layering Ti (having a thickness of 30 nm, for example), MoN (having a thickness of 30 nm, for example), Al (having a thickness of 200 nm, for example), and MoN (having a thickness of 50 nm, for example) in this order. 
     Here, for example, a source conductive film is formed by a sputtering method and the source conductive film is patterned by wet etching (source/drain separation). Thereafter, a portion of the contact layer located on the region that will serve as the channel region of the semiconductor layer  5  is removed by dry etching, for example, to form a gap portion, and the source contact layer  6 S and the drain contact layer  6 D are separated. At this time, in the gap portion, the area around the surface of the semiconductor layer  5  is also etched (overetching). 
     Note that, when a layered film in which a Ti film and an Al film layered in this order is used as a source conductive film, for example, after patterning the Al film by wet etching using, for example, an aqueous solution of phosphoric acid, acetic acid, and nitric acid, the Ti film and the contact layer (n +  type amorphous silicon layer)  6  may be simultaneously patterned by dry etching. Alternatively, it is also possible to collectively etch the source conductive film and the contact layer. However, in the case of simultaneously etching the source conductive film, or the lower layer thereof and the contact layer  6 , it may be difficult to control the distribution of the etching amount of the semiconductor layer  5  (the amount of excavation of the gap portion) of the entire substrate. In contrast, as described above, in a case where etching is performed in an etching step separate from the source/drain separation and the gap portion formation, the etching amount of the gap portion can be more easily controlled. 
     Next, the first insulating layer  11  is formed so as to cover the TFT  10 . In this example, the first insulating layer  11  is disposed so as to be in contact with the channel region of the semiconductor layer  5 . In addition, the contact hole CH 1  that at least reaches the drain electrode  7 D is formed in the first insulating layer  11  by a known photolithographic method. 
     The first insulating layer  11  may be an inorganic insulating layer such as a silicon oxide (SiO 2 ) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x&gt;y) film, or a silicon nitride oxide (SiNxOy; x&gt;y) film, for example. Here, as the first insulating layer  11 , a SiNx layer having a thickness of 330 nm, for example, is formed by a CVD method. 
     Next, a patch conductive film is formed on the first insulating layer  11  and within the contact hole CH 1 , and this is subsequently patterned. In this way, the patch electrode  15  is formed in the transmission and/or reception region R 1 , and the patch connection section  15   p  is formed in the non-transmission and/or reception region R 2 . The patch electrode  15  is in contact with the drain electrode  7 D within the contact hole CH 1 . Note that, in the present specification, the layer including the patch electrode  15  and the patch connection section  15   p  formed from the patch conductive film may be referred to as a “patch metal layer” in some cases. 
     The same material as that of the gate conductive film or the source conductive film can be used as the material of the patch conductive film. However, the patch conductive film is set to be thicker than the gate conductive film and the source conductive film. Accordingly, by reducing the sheet resistance of the patch electrode, the loss resulting from the oscillation of free electrons in the patch electrode changing to heat can be reduced. A suitable thickness of the patch conductive film is, for example, greater than or equal to 0.3 μm. In a case where the thickness of the patch conductive film becomes thinner than this, the sheet resistance becomes greater or equal to 0.10 Ω/sq, and there is a possibility that the loss increases. The thickness of the patch conductive film is, for example, less than or equal to 3 μm, and more preferably less than or equal to 2 μm. In a case where the thickness is thicker than this, warping of the substrate may occur. In a case where the warping is large, problems such as conveyance troubles, chipping of the substrate, or cracking of the substrate may occur in the mass production process. 
     Here, as a patch conductive film, a layered film (MoN/Al/MoN) is formed by layering MoN (having a thickness of 50 nm, for example), Al (having a thickness of 1000 nm, for example), and MoN (having a thickness of 50 nm, for example) in this order. Instead, a layered film (MoN/Al/MoN/Ti) may be formed by layering Ti (having a thickness of 50 nm, for example), MoN (having a thickness of 50 nm, for example), Al (having a thickness of 2000 nm, for example), and MoN (having a thickness of 50 nm, for example) in this order. Alternatively, instead, a layered film (MoN/Al/MoN/Ti) may be formed by layering Ti (having a thickness of 50 nm, for example), MoN (having a thickness of 50 nm, for example), Al (having a thickness of 500 nm, for example), and MoN (having a thickness of 50 nm, for example) in this order. Alternatively, a layered film (Ti/Cu/Ti) in which a Ti film, a Cu film, and a Ti film are layered in this order, or a layered film (Cu/Ti) in which a Ti film and a Cu film are layered in this order may be used. 
     Next, the second insulating layer (having a thickness of greater than or equal to 100 nm and less than or equal to 300 nm)  17  is formed on the patch electrode  15  and the first insulating layer  11 . The second insulating layer  17  is not particularly limited to a specific film, and, for example, a silicon oxide (SiO 2 ) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x&gt;y) film, a silicon nitride oxide (SiNxOy; x&gt;y) film, or the like can be used as appropriate. Here, as the second insulating layer  17 , for example, a SiNx layer having a thickness of 200 nm is formed. 
     Thereafter, the inorganic insulating films (the second insulating layer  17 , the first insulating layer  11 , and the gate insulating layer  4 ) are etched collectively by dry etching using a fluorine-based gas, for example. During the etching, the patch electrode  15 , the source bus line SL, and the gate bus line GL each function as an etch stop. In this way, the contact hole CH 2  that at least reaches the gate bus line GL is formed in the second insulating layer  17 , the first insulating layer  11 , and the gate insulating layer  4 , and the contact hole CH 3  that at least reaches the source bus line SL is formed in the second insulating layer  17  and the first insulating layer  11 . In addition, the contact hole CH 4  that at least reaches the patch connection section  15   p  is formed in the second insulating layer  17 . 
     In this example, since the inorganic insulating films are etched collectively, side surfaces of the second insulating layer  17 , first insulating layer  11 , and gate insulating layer  4  are aligned on a side wall of the obtained contact hole CH 2 , and the side walls of the second insulating layer  17  and first insulating layer  11  are aligned on a side wall of the contact hole CH 3 . Note that, in the present embodiment, the expression that “the side surfaces of different two or more layers are aligned” within the contact hole does not only refer to when the side surfaces exposed in the contact hole in these layers are flush in the vertical direction, but also includes cases where inclined surfaces such as continuous tapered shapes are formed. Such a structure can be obtained, for example, by etching these layers using the same mask, or alternatively by using one of these layers as a mask to etch the other layer. 
     Next, a transparent conductive film (having a thickness of greater than or equal to 50 nm and less than or equal to 200 nm) is formed on the second insulating layer  17  and within the contact holes CH 2 , CH 3 , and CH 4  by a sputtering method, for example. An indium tin oxide (ITO) film, an IZO film, a zinc oxide (ZnO) film or the like can be used as the transparent conductive film. Here, an ITO film having a thickness of, for example, 100 nm is used as the transparent conductive film. 
     Next, the transparent conductive film is patterned to form the gate terminal upper connection section  19   g , the source terminal upper connection section  19   s , and the transfer terminal upper connection section  19   p . The gate terminal upper connection section  19   g , the source terminal upper connection section  19   s , and the transfer terminal upper connection section  19   p  are used for protecting the electrodes or wiring lines exposed at each terminal section. In this way, the gate terminal section GT, the source terminal section ST, and the transfer terminal section PT are obtained. 
     Structure of Slot Substrate  201   
     Next, the structure of the slot substrate  201  will be described in greater detail. 
       FIG. 6  is a cross-sectional view schematically illustrating the antenna unit region U and the terminal section IT in the slot substrate  201 . 
     The slot substrate  201  includes the dielectric substrate  51  having a front surface and a rear surface, a third insulating layer  52  formed on the front surface of the dielectric substrate  51 , the slot electrode  55  formed on the third insulating layer  52 , and a fourth insulating layer  58  covering the slot electrode  55 . The reflective conductive plate  65  is disposed opposing the rear surface of the dielectric substrate  51  with the dielectric layer (air layer)  54  interposed therebetween. The slot electrode  55  and the reflective conductive plate  65  function as walls of the waveguide  301 . 
     In the transmission and/or reception region R 1 , a plurality of slots  57  are formed in the slot electrode  55 . The slot  57  is an opening that opens through the slot electrode  55 . In this example, one slot  57  is disposed in each antenna unit region U. 
     The fourth insulating layer  58  is formed on the slot electrode  55  and within the slot  57 . The material of the fourth insulating layer  58  may be the same as the material of the third insulating layer  52 . By covering the slot electrode  55  with the fourth insulating layer  58 , the slot electrode  55  and the liquid crystal layer LC are not in direct contact with each other, such that the reliability can be enhanced. In a case where the slot electrode  55  is formed of a Cu layer, Cu may elute into the liquid crystal layer LC in some cases. In addition, in a case where the slot electrode  55  is formed of an Al layer by using a thin film deposition technique, the Al layer may include a void. The fourth insulating layer  58  can prevent the liquid crystal material from entering the void of the Al layer. Note that in a case where the slot electrode  55  is formed by bonding an aluminum foil as the Al layer on the dielectric substrate  51  with an adhesive and patterning it, the problem of voids can be avoided. 
     The slot electrode  55  includes a main layer  55 M such as a Cu layer or an Al layer. The slot electrode  55  may have a layered structure that includes the main layer  55 M, as well as an upper layer  55 U and a lower layer  55 L disposed sandwiching the main layer  55 M therebetween. A thickness of the main layer  55 M may be set in consideration of the skin effect depending on the material, and may be, for example, greater than or equal to 2 μm and less than or equal to 30 rpm. The thickness of the main layer  55 M is typically greater than the thickness of the upper layer  55 U and the lower layer  55 L. 
     In the illustrated example, the main layer  55 M is a Cu layer, and the upper layer  55 U and the lower layer  55 L are Ti layers. By disposing the lower layer  55 L between the main layer  55 M and the third insulating layer  52 , the adhesion between the slot electrode  55  and the third insulating layer  52  can be improved. In addition, by providing the upper layer  55 U, corrosion of the main layer  55 M (e.g., the Cu layer) can be suppressed. 
     Since the reflective conductive plate  65  constitutes the wall of the waveguide  301 , it is desirable that the reflective conductive plate  65  has a thickness that is three times or greater than the skin depth, and preferably five times or greater. An aluminum plate, a copper plate, or the like having a thickness of several millimeters manufactured by a cutting out process can be used as the reflective conductive plate  65 . 
     The terminal section IT is provided in the non-transmission and/or reception region R 2 . The terminal section IT includes the slot electrode  55 , the fourth insulating layer  58  covering the slot electrode  55 , and an upper connection section  60 . The fourth insulating layer  58  includes an opening that at least reaches the slot electrode  55 . The upper connection section  60  is in contact with the slot electrode  55  within the opening. In the present embodiment, the terminal section IT is disposed in the seal region Rs, and is connected to the transfer terminal section on the TFT substrate (transfer section) by a sealing resin containing conductive particles. 
     Transfer Section 
       FIG. 7  is a schematic cross-sectional view for illustrating the transfer section connecting the transfer terminal section PT of the TFT substrate  101  and the terminal section IT of the slot substrate  201 . In  FIG. 7 , the same reference numerals are attached to the same components as those in  FIG. 1  to  FIG. 4C . 
     In the transfer section, the upper connection section  60  of the terminal section IT is electrically connected to the transfer terminal upper connection section  19   p  of the transfer terminal section PT in the TFT substrate  101 . In the present embodiment, the upper connection section  60  and the transfer terminal upper connection section  19   p  are connected with a resin (sealing resin)  73  (also referred to as a sealing portion  73 ) including conductive beads  71  therebetween. 
     Each of the upper connection sections  60  and  19   p  is a transparent conductive layer such as an ITO film or an IZO film, and there is a possibility that an oxide film is formed on the surface thereof. When an oxide film is formed, the electrical connection between the transparent conductive layers cannot be ensured, and the contact resistance may increase. In contrast, in the present embodiment, since these transparent conductive layers are bonded with a resin including conductive beads (for example. Au beads)  71  therebetween, even in a case where a surface oxide film is formed, the conductive beads pierce (penetrate) the surface oxide film, allowing an increase in contact resistance to be suppressed. The conductive beads  71  may penetrate not only the surface oxide film but also penetrate the upper connection sections  60  and  19   p  which are the transparent conductive layers, and directly contact the patch connection section  15   p  and the slot electrode  55 . 
     The transfer section may be disposed at both a center portion and a peripheral portion (that is, inside and outside of the donut-shaped transmission and/or reception region R 1  when viewed from the normal direction of the scanning antenna  1000 ) of the scanning antenna  1000 , or alternatively may be disposed at only one of them. The transfer section may be disposed in the seal region Rs in which the liquid crystals are sealed, or may be disposed outside the seal region Rs (opposite to the liquid crystal layer). 
     Method of Manufacturing Slot Substrate  201   
     The slot substrate  201  can be manufactured by the following method, for example. 
     First, the third insulating layer (having a thickness of 200 nm, for example)  52  is formed on the dielectric substrate. A substrate such as a glass substrate or a resin substrate having a high transmittance to electromagnetic waves (the dielectric constant ε M  and the dielectric loss tan δ M  are small) can be used as the dielectric substrate. The dielectric substrate is preferably thin in order to suppress the attenuation of the electromagnetic waves. For example, after forming the constituent elements such as the slot electrode  55  on the front surface of the glass substrate by a process to be described later, the glass substrate may be thinned from the rear side. This allows the thickness of the glass substrate to be reduced to 500 μm or less, for example. 
     When a resin substrate is used as the dielectric substrate, constituent elements such as TFTs may be formed directly on the resin substrate, or may be formed on the resin substrate by a transfer method. In a case of the transfer method, for example, a resin film (for example, a polymide film) is formed on the glass substrate, and after the constituent elements are formed on the resin film by the process to be described later, the resin film on which the constituent elements are formed is separated from the glass substrate. Generally, the dielectric constant ε M  and the dielectric loss tan δ M  of resin are smaller than those of glass. The thickness of the resin substrate is, for example, from 3 μm to 300 μm. Besides polyimide, for example, a liquid crystal polymer can also be used as the resin material. 
     The third insulating layer  52  is not particularly limited to a specific film, and, for example, a silicon oxide (SiO 2 ) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x&gt;y) film, a silicon nitride oxide (SiNxOy; x&gt;y) film, or the like can be used as appropriate. 
     Next, a metal film is formed on the third insulating layer  52 , and this is patterned to obtain the slot electrode  55  including the plurality of slots  57 . As the metal film, a Cu film (or Al film) having a thickness of from 2 μm to 5 μm may be used. Here, a layered film obtained by layering a Ti film, a Cu film, and a Ti film in this order is used. Instead, a layered film may be formed by layering Ti (having a thickness of 50 nm, for example) and Cu (having a thickness of 5000 nm, for example) in this order. 
     Thereafter, the fourth insulating layer (having a thickness of 100 nm or 200 nm, for example) 58 is formed on the slot electrode  55  and within the slot  57 . The material of the fourth insulating layer  58  may be the same as the material of the third insulating layer. Subsequently, in the non-transmission and/or reception region R 2 , an opening that at least reaches the slot electrode  55  is formed in the fourth insulating layer  58 . 
     Next, a transparent conductive film is formed on the fourth insulating layer  58  and within the opening of the fourth insulating layer  58 , and is patterned to form the upper connection section  60  in contact with the slot electrode  55  within the opening. In this way, the terminal section IT is obtained. 
     Material and Structure of TFT  10   
     In the present embodiment, a TFT including a semiconductor layer  5  as an active layer is used as a switching element disposed in each pixel. The semiconductor layer  5  is not limited to an amorphous silicon layer, and may be a polysilicon layer or an oxide semiconductor layer. 
     In a case where an oxide semiconductor layer is used, the oxide semiconductor included in the oxide semiconductor layer may be an amorphous oxide semiconductor or a crystalline oxide semiconductor including a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or a crystalline oxide semiconductor having a c-axis oriented substantially perpendicular to the layer surface. 
     The oxide semiconductor layer may have a layered structure of two or more layers. In cases where the oxide semiconductor layer has a layered structure, the oxide semiconductor layer may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, the oxide semiconductor layer may include a plurality of crystalline oxide semiconductor layers having different crystal structures. In addition, the oxide semiconductor layer may include a plurality of amorphous oxide semiconductor layers. In cases where the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor included in the upper layer is preferably greater than the energy gap of the oxide semiconductor included in the lower layer. However, when the different in the energy gap between these layers is relatively small, the energy gap of the lower layer oxide semiconductor may be greater than the energy gap of the upper layer oxide semiconductor. 
     JP 2014-007399 A, for example, describes materials, structures, film formation methods, and the configuration of oxide semiconductor layers having layered structures for amorphous oxide semiconductors and each of the above described crystalline oxide semiconductors. For reference, the entire contents of JP 2014-007399 A are incorporated herein. 
     The oxide semiconductor layer may include, for example, at least one metal element selected from In, Ga, and Zn. In the present embodiment, the oxide semiconductor layer includes, for example, an In—Ga—Zn—O based semiconductor (for example, indium gallium zinc oxide). Here, the In—Ga—Zn—O based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited to a specific value. For example, the ratio includes In:Ga:Zn=2:2:1. In:Ga:Zn=1:1:1, or In:Ga:Zn=1:1:2. Such an oxide semiconductor layer can be formed from an oxide semiconductor film including an In—Ga—Zn—O based semiconductor. Note that a channel etch type TFT having an active layer including an oxide semiconductor such as an In—Ga—Zn—O based semiconductor may be referred to as “CE-OS-TFT”. 
     The In—Ga—Zn—O based semiconductor may be an amorphous semiconductor or a crystalline semiconductor. A crystalline In—Ga—Zn—O based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable as the crystalline In—Ga—Zn—O based semiconductor. 
     Note that the crystal structure of the crystalline In—Ga—Zn—O based semiconductor is disclosed in, for example, the above-mentioned JP 2014-007399 A, JP 2012-134475 A, and JP 2014-209727 A. For reference, the entire contents of JP 2012-134475 A and 2014-209727 A are incorporated herein. Since a TFT including an In—Ga—Zn—O based semiconductor layer has high mobility (more than 20 times in comparison with a-Si TFTs) and low leakage current (less than 1/100th in comparison with a-Si TFTs), such a TFT can suitably be used as a driving TFT (for example, a TFT included in a driving circuit provided in the non-transmission and/or reception region) and a TFT provided in each antenna unit region. 
     In place of the In—Ga—Zn—O based semiconductor, the oxide semiconductor layer may include another oxide semiconductor. For example, the oxide semiconductor layer may include an In—Sn—Zn—O based semiconductor (for example, In 2 O 3 —SnO 2 —ZnO; InSnZnO). The In—Sn—Zn—O based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In—Al—Zn—O based semiconductor, an In—Al—Sn—Zn—O based semiconductor, a Zn—O based semiconductor, an In—Zn—O based semiconductor, a Zn—Ti—O based semiconductor, a Cd—Ge—O based semiconductor, a Cd—Pb—O based semiconductor, CdO (cadmium oxide), a Mg—Zn—O based semiconductor, an In—Ga—Sn—O based semiconductor, an In—Ga—O based semiconductor, a Zr—In—Zn—O based semiconductor, an Hf—In—Zn—O based semiconductor, an Al—Ga—Zn—O based semiconductor, or a Ga—Zn—O based semiconductor. 
     In the example illustrated in  FIG. 3A  and  FIG. 3B , the TFT  10  is a channel etch type TFT having a bottom gate structure. The channel etch type TFT does not include an etch stop layer formed on the channel region, and a lower face of an end portion of each of the source and drain electrodes, which is closer to the channel, is provided so as to be in contact with an upper face of the semiconductor layer. The channel etch type TFT is formed by, for example, forming a conductive film for a source/drain electrode on a semiconductor layer and performing source/drain separation. In the source/drain separation process, the surface portion of the channel region may be etched. 
     Note that the TFT  10  may be an etch stop type TFT in which an etch stop layer is formed on the channel region. In the etch stop type TFT, the lower face of an end portion of each of the source and drain electrodes, which is closer to the channel, is located, for example, on the etch stop layer. The etch stop type TFT is formed as follows; after forming an etch stop layer covering the portion that will become the channel region in a semiconductor layer, for example, a conductive film for the source and drain electrodes is formed on the semiconductor layer and the etch stop layer, and source/drain separation is performed. 
     In addition, although the TFT  10  has a top contact structure in which the source and drain electrodes are in contact with the upper face of the semiconductor layer, the source and drain electrodes may be disposed to be in contact with the lower face of the semiconductor layer (a bottom contact structure). Furthermore, the TFT  10  may have a bottom gate structure having a gate electrode on the dielectric substrate side of the semiconductor layer, or a top gate structure having a gate electrode above the semiconductor layer. 
     Second Embodiment 
     The scanning antenna of a second embodiment will be described with reference to drawings. The TFT substrate of the scanning antenna of the present embodiment differs from the TFT substrate  101  illustrated in  FIG. 2A  in that a transparent conductive layer that serves as an upper connection section for each terminal section is provided between the first insulating layer and the second insulating layer of the TFT substrate. 
       FIG. 8A  to  FIG. 8C  are cross-sectional views illustrating the gate terminal section GT, the source terminal section ST, and the transfer terminal section PT, respectively, of a TFT substrate  102  in the present embodiment. Constituent elements similar to those in  FIG. 4A  to  FIG. 4C  are denoted by the same reference numerals, and the description thereof is omitted. Since the cross-sectional structure of the antenna unit region U is similar to that of the above-described embodiments ( FIG. 3A  and  FIG. 3B ), the illustration and description thereof will be omitted. 
     The gate terminal section GT in the present embodiment includes the gate bus line GL formed on a dielectric substrate, the insulating layer covering the gate bus line GL, and the gate terminal upper connection section  19   g . The gate terminal upper connection section  19   g  is in contact with the gate bus line GL within the contact hole CH 2  formed in the insulating layer. In this example, the insulating layer covering the gate bus line GL includes the gate insulating layer  4  and the first insulating layer  11 . The second insulating layer  17  is formed on the gate terminal upper connection section  19   g  and the first insulating layer  11 . The second insulating layer  17  includes an opening  18   g  exposing a part of the gate terminal upper connection section  19   g . In this example, the opening  18   g  of the second insulating layer  17  may be disposed so as to expose the entire contact hole CH 2 . 
     The source terminal section ST includes the source bus line SL formed on the dielectric substrate (here, on the gate insulating layer  4 ), the insulating layer covering the source bus line SL, and the source terminal upper connection section  19   s . The source terminal upper connection section  19   s  is in contact with the source bus line SL within the contact hole CH 3  formed in the insulating layer. In this example, the insulating layer covering the source bus line SL includes only the first insulating layer  11 . The second insulating layer  17  extends over the source terminal upper connection section  19   s  and the first insulating layer  11 . The second insulating layer  17  includes an opening  18   s  exposing a part of the source terminal upper connection section  19   s . The opening  18   s  of the second insulating layer  17  may be disposed so as to expose the entire contact hole CH 3 . 
     The transfer terminal section PT includes a source connection wiring line  7   p  formed from the same conductive film (source conductive film) as that of the source bus line SL, the first insulating layer  11  extending over the source connection wiring line  7   p , and the transfer terminal upper connection section  19   p  and the patch connection section  15   p  formed on the first insulating layer  11 . 
     Contact holes CH 5  and CH 6  are provided in the first insulating layer  11  to expose the source connection wiring line  7   p . The transfer terminal upper connection section  19   p  is disposed on the first insulating layer  11  and within the contact hole CH 5 , and is in contact with the source connection wiring line  7   p  within the contact hole CH 5 . The patch connection section  15   p  is disposed on the first insulating layer  11  and within the contact hole CH 6 , and is in contact with the source connection wiring line  7   p  within the contact hole CH 6 . The transfer terminal upper connection section  19   p  is a transparent electrode formed of a transparent conductive film. The patch connection section  15   p  is formed of the same conductive film as that of the patch electrode  15 . Note that the upper connection sections  19   g ,  19   s , and  19   p  of the respective terminal sections may be formed of the same transparent conductive film. 
     The second insulating layer  17  extends over the transfer terminal upper connection section  19   p , the patch connection section  15   p , and the first insulating layer  11 . The second insulating layer  17  includes an opening  18   p  exposing a part of the transfer terminal upper connection section  19   p . In this example, the opening  18   p  of the second insulating layer  17  is disposed so as to expose the entire contact hole CH 5 . In contrast, the patch connection section  15   p  is covered with the second insulating layer  17 . 
     In this way, in the present embodiment, the source connection wiring line  7   p  formed in the source metal layer electrically connects the transfer terminal upper connection section  19   p  of the transfer terminal section PT and the patch connection section  15   p . Although not illustrated in drawings, similar to the above-described embodiment, the transfer terminal upper connection section  19   p  is connected to the slot electrode of the slot substrate  201  by a sealing resin containing conductive particles. 
     In the previously described embodiment, the contact holes CH 1  to CH 4  having different depths are collectively formed after the formation of the second insulating layer  17 . For example, while the relatively thick insulating layers (the gate insulating layer  4 , the first insulating layer  11  and the second insulating layer  17 ) are etched in the gate terminal section GT, only the second insulating layer  17  is etched in the transfer terminal section PT. Accordingly, there is a possibility that the conductive film (for example, a patch electrode conductive film) that serves as the base of the shallow contact holes is considerably damaged during etching. 
     In contrast, in the present embodiment, the contact holes CH 1  to CH 3 , CH 5 , and CH 6  are formed prior to formation of the second insulating layer  17 . Since these contact holes are formed only in the first insulating layer  11  or in the layered film of the first insulating layer  11  and the gate insulating layer  4 , the difference in depth of the collectively formed contact holes can be reduced more than in the previous embodiment. Accordingly, damage to the conductive film that serves as the base of the contact holes can be reduced. In particular, when an Al film is used for the patch electrode conductive film, since a favorable contact cannot be obtained in a case where the ITO film and the Al film are brought into direct contact with each other, a cap layer such as a MoN layer may be formed on the Al film in some cases. In these cases, there is the advantage that the thickness of the cap layer need not be increased to compensate for damage during etching. 
     TFT Substrate  102  Manufacturing Method 
     The TFT substrate  102  is manufactured by the following method, for example.  FIG. 9  is a diagram illustrating an example of a manufacturing process of the TFT substrate  102 . Note that in the following description, in cases where the material, thickness, formation method, or the like of each layer are the same as that of the TFT substrate  101  described above, the description thereof is omitted. 
     First, an alignment mark, a base insulating layer, a gate metal layer, a gate insulating layer, a semiconductor layer, a contact layer, and a source metal layer are formed on a dielectric substrate in the same manner as in the TFT substrate  101  to obtain a TFT. In the step of forming the source metal layer, in addition to the source and drain electrodes and the source bus line, the source connection wiring line  7   p  is also formed from the source conductive film. 
     Next, the first insulating layer  11  is formed so as to cover the source metal layer. Subsequently, the first insulating layer  11  and the gate insulating layer  4  are collectively etched to form the contact holes CH 1  to CH 3 , CH 5 , and CH 6 . During etching, each of the source bus line SL and the gate bus line GL functions as an etch stop. In this way, in the transmission and/or reception region R 1 , the contact hole CH 1  that at least reaches the drain electrode of the TFT is formed in the first insulating layer  11 . In addition, in the non-transmission and/or reception region R 2 , the contact hole CH 2  that at least reaches the gate bus line GL is formed in the first insulating layer  11  and the gate insulating layer  4 , and the contact hole CH 3  that at least reaches the source bus line SL and contact holes CH 5  and CH 6  that at least reach the source connection wiring line  7   p  are formed in the first insulating layer  11 . The contact hole CH 5  may be disposed in the seal region Rs and the contact hole CH 6  may be disposed outside the seal region Rs. Alternatively, both may be disposed outside the seal region Rs. 
     Next, a transparent conductive film is formed on the first insulating layer  11  and within the contact holes CH 1  to CH 3 , CH 5 , and CH 6 , and patterned. In this way, the gate terminal upper connection section  19   g  in contact with the gate bus line GL within the contact hole CH 2 , the source terminal upper connection section  19   s  in contact with the source bus line SL within the contact hole CH 3 , and the transfer terminal upper connection section  19   p  in contact with the source connection wiring line  7   p  within the contact hole CH 5  are formed. 
     Next, a patch electrode conductive film is formed on the first insulating layer  11 , the gate terminal upper connection section  19   g , the source terminal upper connection section  19   s , the transfer terminal upper connection section  19   p , and within the contact holes CH 1  and CH 6  and patterned. In this way, the patch electrode  15  in contact with the drain electrode  7 D within the contact hole CH 1  is formed in the transmission and/or reception region R 1 , and the patch connection section  15   p  in contact with the source connection wiring line  7   p  within the contact hole CH 6  is formed in the non-transmission and/or reception region R 2 . Patterning of the patch electrode conductive film may be performed by wet etching. Here, an etchant capable of increasing the etching selection ratio between the transparent conductive film (ITO or the like) and the patch electrode conductive film (for example, an Al film) is used. In this way, when patterning the patch electrode conductive film, the transparent conductive film can function as an etch stop. Since the portions of the source bus line SL, the gate bus line GL, and the source connection wiring line  7   p  exposed by the contact holes CH 2 , CH 3 , and CH 5  are covered with an etch stop (transparent conductive film), they are not etched. 
     Subsequently, the second insulating layer  17  is formed. Thereafter, the second insulating layer  17  is patterned by, for example, dry etching using a fluorine-based gas. In this way, the opening  18   g  exposing the gate terminal upper connection section  19   g , the opening  18   s  exposing the source terminal upper connection section  19   s , and the opening  18   p  exposing the transfer terminal upper connection section  19   p  are provided in the second insulating layer  17 . In this manner, the TFT substrate  102  is obtained. 
     Third Embodiment 
     The scanning antenna of a third embodiment will be described with reference to drawings. The TFT substrate in the scanning antenna of the present embodiment differs from the TFT substrate  102  illustrated in  FIGS. 8A to 8C  in that the upper connection section made of a transparent conductive film is not provided in the transfer terminal section. 
       FIG. 10A  to  FIG. 10C  are cross-sectional views illustrating the gate terminal section GT, the source terminal section ST, and the transfer terminal section PT, respectively, of a TFT substrate  103  in the present embodiment. Constituent elements similar to those in  FIG. 8A  to  FIG. 8C  are denoted by the same reference numerals. Since the structure of the antenna unit region U is similar to that of the above-described embodiments ( FIG. 3A  and  FIG. 3B ), the illustration and description thereof will be omitted. 
     The structures of the gate terminal section GT and the source terminal section ST are similar to the structures of the gate terminal section and the source terminal section of the TFT substrate  102  illustrated in  FIG. 8A  and  FIG. 8B . 
     The transfer terminal section PT includes the patch connection section  15   p  formed on the first insulating layer  11  and a protective conductive layer  23  layered on the patch connection section  15   p . The second insulating layer  17  extends over the protective conductive layer  23  and includes an opening  18   p  exposing a part of the protective conductive layer  23 . In contrast, the patch electrode  15  is covered with the second insulating layer  17 . 
     TFT Substrate  103  Manufacturing Method 
     The TFT substrate  103  is manufactured by the following method, for example.  FIG. 11  is a diagram illustrating an example of a manufacturing process of the TFT substrate  103 . Note that in the following description, in cases where the material, thickness, formation method, or the like of each layer are the same as that of the TFT substrate  101  described above, the description thereof is omitted. 
     First, an alignment mark, a base insulating layer, a gate metal layer, a gate insulating layer, a semiconductor layer, a contact layer, and a source metal layer are formed on a dielectric substrate in the same manner as in the TFT substrate  101  to obtain a TFT. 
     Next, the first insulating layer  11  is formed so as to cover the source metal layer. Subsequently, the first insulating layer  11  and the gate insulating layer  4  are collectively etched to form the contact holes CH 1  to CH 3 . During etching, each of the source bus line SL and the gate bus line GL functions as an etch stop. In this way, the contact hole CH 1  that at least reaches the drain electrode of the TFT is formed in the first insulating layer  11 , the contact hole CH 2  that at least reaches the gate bus line GL is formed in the first insulating layer  11  and the gate insulating layer  4 , and the contact hole CH 3  that at least reaches the source bus line SL is formed in the first insulating layer  11 . No contact hole is formed in the region where the transfer terminal section is formed. 
     Next, a transparent conductive film is formed on the first insulating layer  11  and within the contact holes CH 1 , CH 2 , and CH 3 , and patterned. In this way, the gate terminal upper connection section  19   g  in contact with the gate bus line GL within the contact hole CH 2  and the source terminal upper connection section  19   s  in contact with the source bus line SL within the contact hole CH 3  are formed. In the region where the transfer terminal section is formed, the transparent conductive film is removed. 
     Next, a patch electrode conductive film is formed on the first insulating layer  11 , on the gate terminal upper connection section  19   g  and the source terminal upper connection section  19   s , and within the contact hole CH 1 , and patterned. In this way, the patch electrode  15  in contact with the drain electrode  7 D within the contact hole CH 1  is formed in the transmission and/or reception region R 1 , and the patch connection section  15   p  is formed in the non-transmission and/or reception region R 2 . Similar to the previous embodiments, an etchant capable of ensuring an etching selection ratio between the transparent conductive film (ITO or the like) and the patch electrode conductive film is used for patterning the patch electrode conductive film. 
     Subsequently, the protective conductive layer  23  is formed on the patch connection section  15   p . A Ti layer, an ITO layer, and an indium zinc oxide (IZO) layer (having a thickness of greater than or equal to 50 nm and less than or equal to 100 nm, for example), or the like can be used as the protective conductive layer  23 . Here, a Ti layer (having a thickness of 50 nm, for example) is used as the protective conductive layer  23 . Note that the protective conductive layer may be formed on the patch electrode  15 . 
     Next, the second insulating layer  17  is formed. Thereafter, the second insulating layer  17  is patterned by, for example, dry etching using a fluorine-based gas. In this way, the opening  18   g  exposing the gate terminal upper connection section  19   g , the opening  18   s  exposing the source terminal upper connection section  19   s , and the opening  18   p  exposing the protective conductive layer  23  are provided in the second insulating layer  17 . In this manner, the TFT substrate  103  is obtained. 
     Structure of Slot Substrate  203   
       FIG. 12  is a schematic cross-sectional view for illustrating a transfer section that connects the transfer terminal section PT of the TFT substrate  103  and a terminal section IT of a slot substrate  203  in the present embodiment. In  FIG. 12 , the same reference numerals are attached to the same constituent elements as those in the embodiments described above. 
     First, the slot substrate  203  in this embodiment will be described. The slot substrate  203  includes the dielectric substrate  51 , the third insulating layer  52  formed on the front surface of the dielectric substrate  51 , the slot electrode  55  formed on the third insulating layer  52 , and the fourth insulating layer  58  covering the slot electrode  55 . The reflective conductive plate  65  is disposed opposing the rear surface of the dielectric substrate  51  with the dielectric layer (air layer)  54  interposed therebetween. The slot electrode  55  and the reflective conductive plate  65  function as walls of the waveguide  301 . 
     The slot electrode  55  has a layered structure in which a Cu layer or an Al layer is the main layer  55 M. In the transmission and/or reception region R 1 , a plurality of slots  57  are formed in the slot electrode  55 . The structure of the slot electrode  55  in the transmission and/or reception region R 1  is the same as the structure of the slot substrate  201  described above with reference to  FIG. 6 . 
     The terminal section IT is provided in the non-transmission and/or reception region R 2 . The terminal section IT includes an opening exposing the front surface of the slot electrode  55  provided in the fourth insulating layer  58 . The exposed area of the slot electrode  55  serves as a contact surface  55   c . As described above, in the present embodiment, the contact surface  55   c  of the slot electrode  55  is not covered with the fourth insulating layer  58 . 
     In the transfer section, the protective conductive layer  23  covering the patch connection section  15   p  of the TFT substrate  103  and the contact surface  55   c  of the slot electrode  55  of the slot substrate  203  are connected with a resin (sealing resin) containing the conductive beads  71  therebetween. 
     As in the above-described embodiments, the transfer section in the present embodiment may be disposed at both the central portion and the peripheral portion of the scanning antenna, or may be disposed in only one of them. In addition, the transfer section may be disposed within the seal region Rs or may be disposed outside the seal region Rs (opposite to the liquid crystal layer). 
     In the present embodiment, no transparent conductive film is provided on the transfer terminal PT and the contact surface of the terminal section IT. Accordingly, the protective conductive layer  23  and the slot electrode  55  of the slot substrate  203  can be connected with a sealing resin containing conductive particles therebetween. 
     Furthermore, in the present embodiment, since the difference in the depth of the collectively formed contact holes is small in comparison with the first embodiment ( FIG. 3A  to  FIG. 4C ), the damage to the conductive film that serves as the base of the contact holes can be reduced. 
     Slot Substrate  203  Manufacturing Method 
     The slot substrate  203  is manufactured as follows. Since the material, the thickness, and the formation method of each layer are the same as those of the slot substrate  201 , the description thereof is omitted. 
     First, the third insulating layer  52  and the slot electrode  55  are formed on the dielectric substrate in the same manner as the slot substrate  201 , and a plurality of slots  57  are formed in the slot electrode  55 . Next, the fourth insulating layer  58  is formed on the slot electrode  55  and within the slot. Subsequently, the opening  18   p  is formed in the fourth insulating layer  58  so as to expose a region that will become the contact surface of the slot electrode  55 . In this way, the slot substrate  203  is manufactured. 
     Internal Heater Structure 
     As described above, it is preferable that the dielectric anisotropy Δε M  of the liquid crystal material used for the antenna unit of the antenna be large. However, the viscosity of liquid crystal materials (nematic liquid crystals) having large dielectric anisotropies Δε M  is high, and the slow response speed may lead to problems. In particular, as the temperature decreases, the viscosity increases. The environmental temperature of a scanning antenna mounted on a moving body (for example, a ship, an aircraft, or an automobile) fluctuates. Accordingly, it is preferable that the temperature of the liquid crystal material can be adjusted to a certain extent, for example 30° C. or higher, or 45′C or higher. The set temperature is preferably set such that the viscosity of the nematic liquid crystal material is about 10 cP (centipoise) or less. 
     In addition to the above structure, the scanning antenna according to the embodiments of the disclosure preferably has an internal heater structure. A resistance heating type heater that uses Joule heat is preferable as the internal heater. The material of the resistive film for the heater is not particularly limited to a specific material, but a conductive material having relatively high specific resistance such as ITO or IZO can be utilized, for example. In addition, to adjust the resistance value, a resistive film may be formed with thin lines or meshes made of a metal (e.g., nichrome, titanium, chromium, platinum, nickel, aluminum, and copper). Thin lines or meshes made of ITO and IZO may be also used. The resistance value may be set according to the required calorific value. 
     For example, to set the heat generation temperature of the resistive film to 30° C. for an area (roughly 90000 mm 2 ) of a circle having a diameter of 340 mm with 100 V AC (60 Hz), the resistance value of the resistive film should be set to 139Ω, the current should be set to 0.7 A, and the power density should be set to 800 W/m 2 . To set the heat generation temperature of the resistive film to 45° C. for the same area with 100 V AC (60 Hz), the resistance value of the resistive film should be set to 82Ω, the current should be set to 1.2 A, and the power density should be set to 1350 W/m 2 . 
     The resistive film for the heater may be provided anywhere as long as it does not affect the operation of the scanning antenna, but to efficiently heat the liquid crystal material, the resistive film is preferably provided near the liquid crystal layer. For example, as illustrated in a TFT substrate  104  illustrated in  FIG. 13A , a resistive film  68  may be formed on almost the entire surface of the dielectric substrate  1 .  FIG. 13A  is a schematic plan view of the TFT substrate  104  including the heater resistive film  68 . The resistive film  68  is covered with, for example, the base insulating film  2  illustrated in  FIG. 3A . The base insulating film  2  is formed to have a sufficient dielectric strength. 
     The resistive film  68  preferably has openings  68   a ,  68   b , and  68   c . When the TFT substrate  104  and the slot substrate are bonded to each other, the slots  57  are positioned to oppose the patch electrodes  15 . At this time, the opening  68   a  is disposed such that the resistive film  68  is not present within an area having a distance d from an edge of the slot  57 . The distance d is 0.5 mm, for example. In addition, it is also preferable to dispose the opening  68   b  under the auxiliary capacitance CS and to dispose the opening  68   c  under the TFT. 
     Note that the size of the antenna unit U is, for example, 4 mm×4 mm. In addition, as illustrated in  FIG. 13B , a width s 2  of the slot  57  is 0.5 mm, a length s 1  of the slot  57  is 3.3 mm, a width p 2  of the patch electrode  15  in a width direction of the slot  57  is 0.7 mm, and a width p 1  of the patch electrode  15  in the length direction of the slot  57  is 0.5 mm. Note that the size, shape, arrangement relationships, and the like of the antenna unit U, the slot  57 , and the patch electrode  15  are not limited to the examples illustrated in  FIG. 13A  and  FIG. 13B . 
     To further reduce the influence of the electric field from the heater resistive film  68 , a shield conductive layer may be formed. The shield conductive layer is formed, for example, on the base insulating film  2  over almost the entire surface of the dielectric substrate  1 . While the shield conductive layer need not include the openings  68   a  and  68   b  like in the resistive film  68 , the opening  68   c  is preferably provided therein. The shield conductive layer is formed of, for example, an aluminum layer, and is set to ground potential. 
     In addition, the resistive film preferably has a distribution of the resistance value so that the liquid crystal layer can be uniformly heated. The temperature distribution of the liquid crystal layer is preferably such that difference between the maximum temperature and the minimum temperature (temperature fluctuation) is, for example, less than or equal to 15° C. When the temperature fluctuation exceeds 15° C., there are cases that the phase difference modulation varies within the plane, and good quality beam formation cannot be achieved. Furthermore, when the temperature of the liquid crystal layer approaches the Tni point (for example, 125° C.), Δε M  becomes small, which is not preferable. 
     With reference to  FIG. 14A ,  FIG. 14B , and  FIG. 15A  to  FIG. 15C , the distribution of the resistance value in the resistive film will be described.  FIG. 14A .  FIG. 14B , and  FIG. 15A  to  FIG. 15C  illustrate schematic structures of resistance heating structures  80   a  to  80   e  and a current distribution. The resistance heating structure includes a resistive film and a heater terminal. 
     The resistance heating structure  80   a  illustrated in  FIG. 14A  includes a first terminal  82   a , a second terminal  84   a , and a resistive film  86   a  connected thereto. The first terminal  82   a  is disposed at the center of the circle, and the second terminal  84   a  is disposed along the entire circumference. Here, the circle corresponds to the transmission and/or reception region R 1 . When a DC voltage is applied between the first terminal  82   a  and the second terminal  84   a , for example, a current IA flows radially from the first terminal  82   a  to the second terminal  84   a . Accordingly, even though an in-plane resistance value is constant, the resistive film  86   a  can uniformly generate heat. Of course, the direction of a current flow may be a direction from the second terminal  84   a  to the first terminal  82   a.    
     The resistance heating structure  80   b  illustrated in  FIG. 14B  includes a first terminal  82   b , a second terminal  84   b , and a resistive film  86   b  connected thereto. The first terminal  82   b  and the second terminal  84   b  are disposed adjacent to each other along the circumference. A resistance value of the resistive film  86   b  has an in-plane distribution such that an amount of heat generated per unit area by the current IA flowing between the first terminal  82   b  and the second terminal  84   b  in the resistive film  86   b  is constant. In a case where the resistive film  86   b  is formed of a thin line, for example, the in-plane distribution of the resistance value of the resistive film  86  may be adjusted by the thickness of the thin line and the density of the thin line. 
     The resistance heating structure  80   c  illustrated in  FIG. 15A  includes a first terminal  82   c , a second terminal  84   c , and a resistive film  86   c  connected thereto. The first terminal  82   c  is disposed along the circumference of the upper half of the circle, and the second terminal  84   c  is disposed along the circumference of the lower half of the circle. When the resistive film  86   c  is constituted by thin lines extending vertically between the first terminal  82   c  and the second terminal  84   c , for example, a thickness and a density of the thin lines near the center are adjusted such that the amount of heat generated per unit area by the current IA is constant in the plane. 
     The resistance heating structure  80   d  illustrated in  FIG. 15B  includes a first terminal  82   d , a second terminal  84   d , and a resistive film  86   d  connected thereto. The first terminal  82   d  and the second terminal  84   d  are provided so as to extend in the vertical direction and the horizontal direction, respectively, along the diameter of the circle. Although simplified in drawings, the first terminal  82   d  and the second terminal  84   d  are electrically insulated from each other. 
     In addition, the resistance heating structure  80   e  illustrated in  FIG. 15C  includes a first terminal  82   e , a second terminal  84   e , and a resistive film  86   e  connected thereto. Unlike the resistance heating structure  80   d , both the first terminal  82   e  and the second terminal  84   e  of the resistance heating structure  80   e  include four portions extending from the center of the circle in four directions upward, downward, left, and right. The portions of the first terminal  82   e  and the second terminal  84   e  that form a 90 degree angle with each other are disposed such that the current IA flows clockwise. 
     In both of the resistance heating structure  80   d  and the resistance heating structure  80   e , the thin line closer to the circumference is adjusted to be thick and have a higher density, for example, so that the closer to the circumference the more the current IA increases and the amount of heat generated per unit area becomes uniform within the plane. 
     Such an internal heater structure may automatically operate, for example, when it is detected that the temperature of the scanning antenna has fallen below a preset temperature. Of course, it may also operate in response to the operation of a user. 
     External Heater Structure 
     Instead of the internal heater structure described above, or in addition to the internal heater structure, the scanning antenna according to the embodiments of the disclosure may include an external heater structure. A resistance heating type heater that uses Joule heat is preferable as the external heater although various known heaters can be used. Assume that a part generating heat in the heater is a heater section. In the following description, an example in which a resistive film is used as the heater section is described. In the following description also, the resistive film is denoted by the reference numeral  68 . 
     For example, the heater resistive film  68  is preferably disposed as in a liquid crystal panel  100 Pa or  100 Pb illustrated in  FIGS. 16A and 16B . Here, the liquid crystal panels  100 Pa and  100 Pb includes the TFT substrate  101 , the slot substrate  201 , and the liquid crystal layer LC provided therebetween in the scanning antenna  1000  illustrated in  FIG. 1 , and further includes a resistance heating structure including the resistive film  68  on an outer side of the TFT substrate  101 . The resistive film  68  may be formed on a side of the dielectric substrate  1  of the TFT substrate  101  closer to the liquid crystal layer LC. However, such a configuration complicates a manufacturing process of the TFT substrate  101 , and thus the resistive film  68  is preferably disposed on the outer side of the TFT substrate  101  (opposite to the liquid crystal layer LC). 
     The liquid crystal panel  100 Pa illustrated in  FIG. 16A  includes the heater resistive film  68  formed on an outer surface of the dielectric substrate  1  of the TFT substrate  101  and a protection layer  69   a  covering the heater resistive film  68 . The protection layer  69   a  may be omitted. The scanning antenna is housed in a case made of plastic, for example, and therefore, the resistive film  68  is not directly contacted by the user. 
     The resistive film  68  can be formed on the outer surface of the dielectric substrate  1  by use of, for example, a known thin film deposition technique (e.g., sputtering, CVD), a coating method, or a printing method. The resistive film  68  is patterned as needed. Patterning is performed through a photolithographic process, for example. 
     The material of the heater resistive film  68  is not particularly limited to a specific material as described above for the internal heater structure, but a conductive material having relatively high specific resistance such as ITO or IZO can be utilized, for example. In addition, to adjust the resistance value, the resistive film  68  may be formed with thin lines or meshes made of a metal (e.g., nichrome, titanium, chromium, platinum, nickel, aluminum, and copper). Thin lines or meshes made of ITO and IZO may be also used. The resistance value may be set according to the required calorific value. 
     The protection layer  69   a  is made of an insulating material and formed to cover the resistive film  68 . The protection layer  69   a  may not be formed on a portion where the resistive film  68  is patterned and the dielectric substrate  1  is exposed. The resistive film  68  is patterned so as not to decrease the antenna performance as described later. In a case where a presence of the material forming the protection layer  69   a  causes the antenna performance to decrease, the patterned protection layer  69   a  is preferably used similar to the resistive film  68 . 
     The protection layer  69   a  may be formed by any of a wet process and a dry process. For example, a liquid curable resin (or precursor of resin) or a solution is applied on the surface of the dielectric substrate  1  on which the resistive film  68  is formed, and thereafter, the curable resin is cured to form the protection layer  69   a . The liquid resin or the resin solution is applied to the surface of the dielectric substrate  1  to have a predetermined thickness by various coating methods (e.g., using a slot coater, a spin coater, a spray) or various printing methods. After that, the resultant substrate is subjected to room temperature curing, thermal curing, or light curing depending on a kind of the resin to form the protection layer  69   a  which is an insulating resin film. The insulating resin film may be patterned by a photolithographic process, for example. 
     A curable resin material is preferably used as a material for forming the protection layer  69   a . The curable resin material includes a thermal curing type resin material and a light curing type resin material. The thermal curing type includes a thermal cross-linking type and a thermal polymerization type. 
     Examples of the resin material of thermal cross-linking type include a combination of an epoxy-based compound (e.g., an epoxy resin) and amine-based compound, a combination of an epoxy-based compound and a hydrazide-based compound, a combination of an epoxy-based compound and an alcohol-based compound (e.g., including a phenol resin), a combination of an epoxy-based compound and a carboxylic acid-based compound (e.g., including an acid anhydride), a combination of an isocyanate-based compound and an amine-based compound, a combination of an isocyanate-based compound and a hydrazide-based compound, a combination of an isocyanate-based compound and an alcohol-based compound (e.g., including an urethane resin), and a combination of an isocyanate-based compound and a carboxylic acid-based compound. Examples of a cationic polymerization type adhesive include a combination of an epoxy-based compound and a cationic polymerization initiator (a representative cationic polymerization initiator: aromatic sulfonium salt). Examples of the resin material of radical polymerization type include a combination of a monomer and/or an oligomer containing a vinyl group of various acrylic, methacrylic, and urethane modified acrylic (methacrylic) resins and a radical polymerization initiator (a representative radical polymerization initiator: azo-based compound (e.g., azobisisobutyronitrile (AIBN))), and examples of the resin material of ring-opening polymerization type include an ethylene oxide-based compound, an ethyleneimine-based compound, and a siloxane-based compound. In addition, examples of the resin material may also include a maleimide resin, a combination of a maleimide resin and an amine, a combination of maleimide and a methacrylic compound, a bismaleimide-triazine resin, and a polyphenylene ether resin. Moreover, polyimide can be preferably used. Note that “polyimide” including polyamic acid that is a precursor of polyimide is used. Polyimide is used in combination with an epoxy-based compound or an isocyanate-based compound, for example. 
     In terms of heat resistance, chemical stability, and mechanical characteristics, the thermal curing type resin material is preferably used. Particularly, the resin material containing an epoxy resin or a polyimide resin is preferable, and in terms of the mechanical characteristics (in particular, mechanical strength) and hygroscopicity, the resin material containing a polyimide resin is preferable. A polyimide resin and an epoxy resin may be mixed to be used. A polyimide resin and/or an epoxy resin may be mixed with a thermoplastic resin and/or an elastomer. Furthermore, rubber-modified polyimide resin and/or epoxy resin may be mixed. A thermoplastic resin or an elastomer can be mixed to improve flexibility or toughness. Even when the rubber-modified resin is used, the same effect can be obtained. 
     A cross-linking reaction and/or a polymerization reaction of the light curing type material is caused by ultraviolet light or visible light, and the light curing type material cures. The light curing type includes a radical polymerization type and a cationic polymerization type, for example. Representative examples of the radical polymerization type material include a combination of an acrylic resin (epoxy modified acrylic resin, urethane modified acrylic resin, silicone modified acrylic resin) and a photopolymerization initiator. Examples of an ultraviolet radical polymerization initiator include an acetophenone type initiator and a benzophenone type initiator. Examples of a visible light radical polymerization initiator include a benzylic type initiator and a thioxanthone type initiator. A combination of an epoxy compound and a photo cationic polymerization initiator is a representative example of the cationic polymerization type. Examples of a photo cationic polymerization initiator include an iodonium salt-based compound. A resin material having both light curing and thermal curing characteristics can be used also. 
     The liquid crystal panel  100 Pb illustrated in  FIG. 16B  is different from the liquid crystal panel  100 Pa in that the liquid crystal panel  100 Pb further includes an adhesive layer  67  between the resistive film  68  and the dielectric substrate  1 . Moreover, the liquid crystal panel  100 Pb is different from the liquid crystal panel  100 Pa in that the protection layer  69   b  is formed using a polymer film or glass plate fabricated in advance. 
     For example, the liquid crystal panel  100 Pb including the protection layer  69   b  formed of a polymer film is manufactured as below. 
     First, an insulating polymer film that will become the protection layer  69   b  is prepared. Examples of a polymer film include a polyester film made of polyethylene terephthalate, polyethylene naphthalate or the like, and a film made of super engineering plastic such as polyphenylene sulfone, polyimide, or polyamide. A thickness of the polymer film (that is, a thickness of the protection layer  69   b ) is greater than or equal to 5 μm and less than or equal to 200 μm, for example. 
     The resistive film  68  is formed on one surface of this polymer film. The resistive film  68  can be formed by the above method. The resistive film  68  may be patterned, and the polymer film may be also patterned as needed. 
     The polymer film on which the resistive film  68  is formed (that is, a member integrally formed of the protection layer  69   b  and the resistive film  68 ) is bonded to the dielectric substrate  1  with an adhesive. Examples of the adhesive include the same curable resin as the curable resin used to form the protection layer  69   a  described above. Furthermore, a hot-melt type resin material (adhesive) can be used. The hot-melt type resin material contains a thermoplastic resin as a main component, and melts by heating and solidifies by cooling. Examples of the hot-melt type resin material include polyolefin-based (e.g., polyethylene, polypropylene), polyamide-based, and ethylene vinyl acetate-based resins. A reactive urethane-based hot-melt resin material (adhesive) is also available. In terms of adhesive and durability, the reactive urethane-based resin is preferable. 
     The adhesive layer  67  may be patterned similar to the resistive film  68  and the protection layer (polymer film)  69   b . However, the adhesive layer  67  needs only fix the resistive film  68  and the protection layer  69   b  to the dielectric substrate  1 , and may be smaller than the resistive film  68  and the protection layer  69   b.    
     In place of the polymer film, the glass plate may be also used to form the protection layer  69   b . A manufacturing process may be the same as the case using the polymer film. A thickness of the glass plate is preferably less than or equal to 1 mm and further preferably less than or equal to 0.7 mm. A lower limit of the thickness of the glass plate is not specifically specified, but in terms of handling, the thickness of the glass plate is preferably greater than or equal to 0.3 mm. 
     In the liquid crystal panel  100 Pb illustrated in  FIG. 16B , the resistive film  68  formed on the protection layer (polymer film or glass plate)  69   b  is fixed to the dielectric substrate  1  via the adhesive layer  67 , but the resistive film  68  needs only be disposed in contact with the dielectric substrate  1 , and the resistive film  68  and the protection layer  69   b  are not necessarily fixed (bonded) to the dielectric substrate  1 . In other words, the adhesive layer  67  may be omitted. For example, the polymer film on which the resistive film  68  is formed (that is, a member integrally formed of the protection layer  69   b  and the resistive film  68 ) may be disposed such that the resistive film  68  is brought into contact with the dielectric substrate  1  and is pressed against the dielectric substrate  1  with the case housing the scanning antenna. For example, since the thermal contact resistance possibly increases when the polymer film on which the resistive film  68  is formed is merely disposed only, the polymer film is preferably pressed against the dielectric substrate to decrease the thermal contact resistance. Using such a configuration allows the member integrally formed of the resistive film  68  and the protection layer (polymer film or glass plate)  69   b  to be detachable. 
     Note that in a case where the resistive film  68  (and the protection layer  69   b ) is patterned as described later, the resistive film  68  (and the protection layer  69   b ) is preferably fixed to the dielectric substrate  1  to a degree not to shift in a position with respect to the TFT substrate so that the antenna performance does not decrease. 
     The heater resistive film  68  may be provided anywhere as long as it does not affect the operation of the scanning antenna, but to efficiently heat the liquid crystal material, the resistive film is preferably provided near the liquid crystal layer. Therefore, the heater resistive film  68  is preferably provided on the outer side of the TFT substrate  101  as illustrated in  FIGS. 16A and 16B . In addition, the resistive film  68  directly provided on the outer side of the dielectric substrate  1  of the TFT substrate  101  as illustrated in  FIG. 16A  is preferable, because an energy efficiency is higher, and controllability of the temperature is higher than those in a case in which the resistive film  68  is provided on the outer side of the dielectric substrate  1  with the adhesive layer  67  therebetween as illustrated in  FIG. 16B . 
     For example, the resistive film  68  may be formed on almost the entire surface of the dielectric substrate  1  of the TFT substrate  104  illustrated in  FIG. 13A . The resistive film  68  preferably includes the openings  68   a ,  68   b , and  68   c  as described for the internal heater structure. 
     The protection layers  69   a  and  69   b  may be formed on the entire surface to cover the resistive film  68 . As described above, in a case where the protection layer  69   a  or  69   b  has an adverse effect on antenna characteristics, openings corresponding to the openings  68   a ,  68   b , and  68   c  of the resistive film  68  may be provided. In this case, the openings of the protection layer  69   a  or  69   b  are formed inside the openings  68   a ,  68   b , and  68   c  of the resistive film  68 . 
     To further reduce the influence of the electric field from the heater resistive film  68 , a shield conductive layer may be formed. The shield conductive layer is formed on the side of the resistive film  68  closer to the dielectric substrate  1  with an insulating film therebetween, for example. The shield conductive layer is formed on almost the entire surface of the dielectric substrate  1 . While the shield conductive layer need not include the openings  68   a  and  68   b  like in the resistive film  68 , the opening  68   c  is preferably provided therein. The shield conductive layer is formed of, for example, an aluminum layer, and is set to ground potential. In addition, the resistive film preferably has a distribution of the resistance value so that the liquid crystal layer can be uniformly heated. These structures are similar to the structures of the internal heater structure described above. 
     The resistive film needs only heat the liquid crystal layer LC in the transmission and/or reception region R 1 , and may be provided on an area corresponding to the transmission and/or reception region R 1  as an example described above. However, the structure of the resistive film is not limited to this structure. For example, as illustrated in  FIG. 2A , in a case where the TFT substrate  101  has an outline capable of defining a rectangular area encompassing the transmission and/or reception region R 1 , the resistive film may be provided on an area corresponding to the rectangular area encompassing the transmission and/or reception region R 1 . Of course, the outline of the resistive film is not limited to a rectangle, and may be any shape encompassing the transmission and/or reception region R 1 . 
     In the above example, the resistive film is disposed on the outer side of the TFT substrate  101 , but the resistive film may be disposed on an outer side of the slot substrate  201  (opposite to the liquid crystal layer LC). In this case also, the resistive film may be formed directly on the dielectric substrate  51  similar to the liquid crystal panel  100 Pa in  FIG. 16A , or the resistive film formed on the protection layer (polymer film or glass plate) with the adhesive layer therebetween may be fixed to the dielectric substrate  51  similar to the liquid crystal panel  100 Pb in  FIG. 16B . Alternatively, the protection layer on which the resistive film is formed without the adhesive layer (that is, the member integrally formed of the protection layer and the resistive film) may be disposed such that the resistive film is in contact with the dielectric substrate  51 . For example, since the thermal contact resistance possibly increases in a case where the polymer film on which the resistive film is formed is merely disposed only, the polymer film is preferably pressed against the dielectric substrate  51  to decrease the thermal contact resistance. Using such a configuration allows the member integrally formed of the resistive film and the protection layer (polymer film or glass plate) to be detachable. Note that in a case where the resistive film (and the protection layer) is patterned, the resistive film (and the protection layer) is preferably fixed to the dielectric substrate to a degree not to shift in a position with respect to the slot substrate so that the antenna performance does not decrease. 
     In a case where the resistive film is disposed on the outer side of the slot substrate  201 , openings are preferably provided in the resistive film at positions corresponding to the slots  57 . The resistive film has preferably a thickness enough to transmit microwaves. 
     Here, the example in which the resistive film is used as the heater section is described, but other than the example, a nichrome line (e.g., winding wire), an infrared light heater section, and the like may be used as the heater section, for example. In the cases like these also, the heater section is preferably disposed not to decrease the antenna performance. 
     Such an external heater structure may automatically operate, for example, when it is detected that the temperature of the scanning antenna has fallen below a preset temperature. Of course, it may also operate in response to the operation of a user. 
     As a temperature control device for making the external heater structure automatically operate, various known thermostats can be used, for example. For example, a thermostat using bimetal may be connected between one of two terminals connected with the resistive film and a power source. Of course, a temperature control device may be used which supplies current to the external heater structure from the power source to prevent the temperature from falling below a preset temperature by use of a temperature sensor. 
     Driving Method 
     Since an antenna unit array of the scanning antenna according to the embodiments of the disclosure has a structure similar to that of an LCD panel, line sequential driving is performed in the same manner as an LCD panel. However, in a case where existing driving methods for LCD panels are applied, the following problems may occur. Problems that may occur in the scanning antenna will be described with reference to the equivalent circuit diagram of one antenna unit of the scanning antenna illustrated in  FIG. 17 . 
     First, as mentioned above, since the specific resistance of liquid crystal materials having large dielectric anisotropies Δε M  (birefringence Δn with respect to visible light) in the microwave range is low, in a case where driving methods for LCD panels are applied as is, the voltage applied to the liquid crystal layer cannot be sufficiently maintained. Then, the effective voltage applied to the liquid crystal layer decreases, and the electrostatic capacitance value of the liquid crystal capacitance does not reach the target value. 
     In this way, when the voltage applied to the liquid crystal layer deviates from the predetermined value, the direction in which the gain of the antenna becomes maximum deviates from the intended direction. Then, for example, communication satellites cannot be accurately tracked. To prevent this, an auxiliary capacitance CS is provided electrically in parallel with the liquid crystal capacitance Clc, and the capacitance value C-Ccs of the auxiliary capacitance CS is sufficiently increased. It is desirable that the capacitance value C-Ccs of the auxiliary capacitance CS is appropriately set, so that the voltage holding rate of the liquid crystal capacitance Clc may be, for example, at least 30%, and preferably 55% or more. The capacitance value C-Ccs of the auxiliary capacitance CS depends on the area of electrodes CSE 1  and CSE 2 , and the thickness and the dielectric constant of the dielectric layer between the electrode CSE 1  and the electrode CSE 2 . Typically, the same voltage as that of the patch electrode  15  is supplied to the electrode CSE 1 , and the same voltage as that of the slot electrode  55  is supplied to the electrode CSE 2 . 
     In addition, when a liquid crystal material having a low specific resistance is utilized, a voltage drop due to the interface polarization and/or the orientation polarization also occurs. To prevent the voltage drop due to these polarizations, it is conceivable to apply a sufficiently high voltage in anticipation of the voltage drop. However, when a high voltage is applied to a liquid crystal layer having a low specific resistance, a dynamic scattering effect (DS effect) may occur. The DS effect is caused by the convection of ionic impurities in the liquid crystal layer, and the dielectric constant ε M  of the liquid crystal layer approaches the average value ((ε M //+2ε M ⊥)/3). Also, to control the dielectric constant ε M  of the liquid crystal layer in multiple stages (multiple gray scales), it is not always possible to apply a sufficiently high voltage. 
     To suppress the above-described DS effect and/or the voltage drop due to the polarization, the polarity inversion period of the voltage applied to the liquid crystal layer may be sufficiently shortened. As is well known, in a case where the polarity inversion period of the applied voltage is shortened, a threshold voltage at which the DS effect occurs becomes higher. Accordingly, the polarity inversion frequency may be determined such that the maximum value of the voltage (absolute value) applied to the liquid crystal layer is less than the threshold voltage at which the DS effect occurs. For the polarity inversion frequency of 300 Hz or greater, even in a case where a voltage with an absolute value of 10 V is applied to a liquid crystal layer having a specific resistance of 1×10 10  Ω·cm and a dielectric anisotropy Δε (@1 kHz) of about −0.6, a good quality operation can be ensured. In addition, in a case where the polarity inversion frequency (typically equal to twice the frame frequency) is 300 Hz or greater, the voltage drop caused by the polarization is also suppressed. From the viewpoint of power consumption and the like, the upper limit of the polarity inversion period is preferably about less than or equal to 5 KHz. 
     The polarity inversion frequency of the voltage applied to the liquid crystal layer naturally depends on the liquid crystal material (particularly the specific resistance). Accordingly, depending on the liquid crystal material, even in a case where a voltage with a polarity inversion period of less than 300 Hz is applied, the above described problem does not arise. However, since the liquid crystal material used for the scanning antenna according to the embodiments of the disclosure has a lower specific resistance than that of the liquid crystal material used for LCDs, it is preferable for the liquid crystal layer to be driven at roughly 60 Hz or greater. 
     As described above, since the viscosity of the liquid crystal material depends on the temperature, it is preferable that the temperature of the liquid crystal layer be appropriately controlled. The physical properties and driving conditions of the liquid crystal material described here are values under the operating temperature of the liquid crystal layer. Conversely, the temperature of the liquid crystal layer is preferably controlled such that it can be driven under the above conditions. 
     An example of a waveform of a signal used for driving the scanning antenna will be described with reference to  FIG. 18A  to  FIG. 18G . Note that  FIG. 18D  illustrates the waveform of the display signal Vs (LCD) supplied to the source bus line of the LCD panel for comparison. 
       FIG. 18A  illustrates the waveform of a scanning signal Vg supplied to a gate bus line G-L 1 ,  FIG. 18B  illustrates the waveform of a scanning signal Vg supplied to a gate bus line G-L 2 ,  FIG. 18C  illustrates the waveform of a scanning signal Vg supplied to a gate bus line G-L 3 ,  FIG. 18E  illustrates the waveform of a data signal Vda supplied to the source bus line,  FIG. 18F  illustrates the waveform of a slot voltage Vidc supplied to the slot electrode of the slot substrate (slot electrode), and  FIG. 18G  illustrates the waveform of the voltage applied to the liquid crystal layer of each antenna unit. 
     As illustrated in  FIG. 18A  to  FIG. 18C , the voltage of the scanning signal Vg supplied to the gate bus line sequentially changes from a low level (VgL) to a high level (VgH). VgL and VgH can be appropriately set according to the characteristics of the TFT. For example, VgL=from −5 V to 0 V, and VgH=+20 V. Also, VgL=−20 V and VgH=+20 V are possible. A period from the time when the voltage of the scanning signal Vg of a particular gate bus line switches from the low level (VgL) to the high level (VgH) until the time when the voltage of the next gate bus line switches from VgL to VgH will be referred to as one horizontal scan period (1H). In addition, the period during which the voltage of each gate bus line is at the high level (VgH) will be referred to as a selection period PS. In this selection period PS, the TFTs connected to the respective gate bus lines are turned on, and the current voltage of the data signal Vda supplied to the source bus line is supplied to the corresponding patch electrode. The data signal Vda is, for example, from −15 V to 15 V (an absolute value is 15 V), and, for example, a data signal Vda having different absolute values corresponding to 12 gray scales, or preferably corresponding to 16 gray scales is used. 
     Here, a case is exemplified where an intermediate voltage is applied to all antenna units. That is, it is assumed that the voltage of the data signal Vda is constant with respect to all antenna units (assumed to be connected to m gate bus lines). This corresponds to the case where the gray levels are displayed on the LCD panel over the whole surface thereof. At this time, dot inversion driving is performed in the LCD panel. That is, in each frame, the display signal voltage is supplied such that the polarities of adjacent pixels (dots) are opposite to each other. 
       FIG. 18D  illustrates the waveform of the display signal of the LCD panel on which the dot inversion driving is performed. As illustrated in  FIG. 18D , the polarity of Vs (LCD) is inverted every 1H. The polarity of the Vs (LCD) supplied to a source bus line adjacent to a source bus line supplied with the Vs (LCD) having this waveform is opposite to the polarity of the Vs (LCD) illustrated in  FIG. 18D . Furthermore, the polarity of the display signal supplied to all the pixels is inverted for each frame. In the LCD panels, it is difficult to perfectly match the magnitude of the effective voltage applied to the liquid crystal layer between the positive polarity and the negative polarity, and further, the difference in effective voltage becomes a difference in luminance, which is observed as flicker. To make this flicker less noticeable, the pixels (dots) to which voltages of different polarities are applied are spatially dispersed in each frame. Typically, by performing the dot inversion driving, the pixels (dots) having different polarities are arranged in a checkered pattern. 
     In contrast, in the scanning antenna, the flicker itself is not problematic. That is, it is sufficient for the electrostatic capacitance value of the liquid crystal capacitance to be an intended value, and the spatial distribution of the polarity in each frame is not problematic. Accordingly, from the perspective of low power consumption or the like, it is preferable to reduce the number of times of polarity inversion of the data signal Vda supplied from the source bus line; that is, to lengthen the period of polarity inversion. For example, as illustrated in  FIG. 18E , the period of polarity inversion may be set to 10 H (such that polarity inversion occurs every 5 H). Of course, in a case where the number of antenna units connected to each source bus line (typically equal to the number of gate bus lines) is m, the period of polarity inversion of the data signal Vda may be 2 m·H (polarity inversion occurs each m·H). The period of polarity inversion of the data signal Vda may be equal to 2 frames (a polarity inversion occurs each frame). 
     In addition, the polarity of the data signal Vda supplied from all the source bus lines may be the same. Accordingly, for example, in a particular frame, a positive polarity data signal Vda may be supplied from all the source bus lines, and in the next frame, a negative polarity data signal Vda may be supplied from all the source bus lines. 
     Alternatively, the polarities of the data signals Vda supplied from the adjacent source bus lines may be opposite to each other. For example, in a particular frame, a positive polarity data signal Vda is supplied from odd-numbered source bus lines, and a negative polarity data signal Vda may be supplied from even-numbered source bus lines. Then, in the next frame, the negative polarity data signal Vda is supplied from the odd-numbered source bus lines, and the positive polarity data signal Vda is supplied from the even-numbered source bus lines. In the LCD panels, such a driving method is referred to as source line inversion driving. In a case where the data signals Vda supplied from adjacent source bus line are made to have opposite polarity, by connecting (short-circuiting) adjacent source bus lines to each other before inverting the polarity of the data signals Vda supplied between frames, it is possible to cancel electric charges stored in the liquid crystal capacitance between adjacent columns. Accordingly, an advantage can be obtained such that the amount of electric charge supplied from the source bus line in each frame can be reduced. 
     As illustrated in  FIG. 18F , the voltage Vidc of the slot electrode is, for example, a DC voltage, and is typically a ground potential. Since the capacitance value of the capacitance (liquid crystal capacitance and auxiliary capacitance) of the antenna units is greater than the capacitance value of the pixel capacitance of the LCD panel (for example, about 30 times in comparison with 20-inch LCD panels), there is no affect from the pull-in voltage due to the parasitic capacitance of the TFT, and even in a case where the voltage Vide of the slot electrode is the ground potential and the data signal Vda is a positive or negative symmetrical voltage with reference to the ground potential, the voltage supplied to the patch electrode is a positive and negative symmetrical voltage. In the LCD panels, although the positive and negative symmetrical voltages are applied to the pixel electrode by adjusting the voltage (common voltage) of the counter electrode in consideration of the pull-in voltage of the TFT, this is not necessary for the slot voltage of the scanning antenna, and ground potential may be used. Also, although not illustrated in  FIG. 18A  to  FIG. 18G , the same voltage as the slot voltage Vide is supplied to the CS bus line. 
     Since the voltage applied to the liquid crystal capacitance of each antenna unit is the voltage of the patch electrode with respect to the voltage Vidc ( FIG. 18F ) of the slot electrode (that is, the voltage of the data signal Vda illustrated in  FIG. 18E ), when the slot voltage Vidc is the ground potential, as illustrated in  FIG. 18G , the voltage coincides with the waveform of the data signal Vda illustrated in  FIG. 18E . 
     The waveform of the signal used for driving the scanning antenna is not limited to the above example. For example, as described below with reference to  FIG. 19A  to  FIG. 19E  and  FIG. 20A  to  FIG. 20E , a Viac having an oscillation waveform may also be used as the voltage of the slot electrode. 
     For example, signals such as those exemplified in  FIG. 19A  to  FIG. 19E  can be used. In  FIG. 19A  to  FIG. 19E , although the waveform of the scanning signal Vg supplied to the gate bus line is omitted, the scanning signal Vg described with reference to  FIG. 18A  to  FIG. 18C  is also used here. 
     As illustrated in  FIG. 19A , similar to that illustrated in  FIG. 18E , a case where the waveform of the data signal Vda is inverted in polarity at a 10H period (every 5 H) will be exemplified. Here, a case where the amplitude is the maximum value |Vda max | is illustrated as the data signal Vda. As described above, the waveform of the data signal Vda may be inverted in polarity at a two frame period (each frame). 
     Here, as illustrated in  FIG. 19C , the voltage Viac of the slot electrode is an oscillation voltage such that the polarity of the voltage Viac of the slot electrode is opposite to the polarity of the data signal Vda (ON), and the oscillation period of the slot electrode is the same as that of data signal Vda (ON). The amplitude of the voltage Viac of the slot electrode is equal to the maximum value |Vda max | of the amplitude of the data signal Vda. That is, the slot voltage Viac is set to a voltage that oscillates between −Vda max  and +Vda max  with the same period of polarity inversion as that of the data signal Vda (ON) and opposite polarity (the phase differs by 180°). 
     Since the voltage Vie applied to the liquid crystal capacitance of each antenna unit is the voltage of the patch electrode with respect to the voltage Viac of the slot electrode ( FIG. 19C ) (that is, the voltage of the data signal Vda (ON) illustrated in  FIG. 19A ), when the amplitude of the data signal Vda oscillates at ±Vda max , the voltage applied to the liquid crystal capacitance has a waveform that oscillates with an amplitude twice Vda max  as illustrated in  FIG. 19D . Accordingly, the maximum amplitude of the data signal Vda required to make the maximum amplitude of the voltage Vie applied to the liquid crystal capacitance±Vda max  is +Vda max /2. 
     Since the maximum amplitude of the data signal Vda can be halved by using such a slot voltage Viac, there is the advantage that a general-purpose driver IC with a breakdown voltage of 20 V or less can be used as a driver circuit for outputting the data signal Vda, for example. 
     Note that, as illustrated in  FIG. 19E , to make the voltage Vlc (OFF) applied to the liquid crystal capacitance of each antenna unit zero, as illustrated in  FIG. 19B , it may be preferable for the data signal Vda (OFF) to have the same waveform as that of the slot voltage Viac. 
     Consider, for example, a case where the maximum amplitude of the voltage Vlc applied to the liquid crystal capacitance is ±15 V. When the Vidc illustrated in  FIG. 18F  is used as the slot voltage and Vidc=0 V, the maximum amplitude of Vda illustrated in  FIG. 18E  becomes ±15 V. In contrast, when the Viac illustrated in  FIG. 19C  is used as the slot voltage and the maximum amplitude of Viac is ±7.5 V, the maximum amplitude of Vda (ON) illustrated in  FIG. 19A  becomes ±7.5 V. 
     When the voltage Vlc applied to the liquid crystal capacitance is 0 V, the Vda illustrated in  FIG. 18E  may be set to 0 V, and the maximum amplitude of the Vda (OFF) illustrated in  FIG. 19B  may be set to ±7.5 V. 
     In a case where the Viac illustrated in  FIG. 19C  is utilized, the amplitude of the voltage Vlc applied to the liquid crystal capacitance is different from the amplitude of Vda, and therefore appropriate conversions are necessary. 
     Signals such as those exemplified in  FIG. 20A  to  FIG. 20E  can also be used. The signals illustrated in  FIG. 20A  to  FIG. 20E  are the same as the signals illustrated in  FIG. 19A  to  FIG. 19E  in that the voltage Viac of the slot electrode is an oscillation voltage such that the oscillation phase thereof is shifted by 180° from the oscillation phase of the data signal Vda (ON) as illustrated in  FIG. 20C . However, as illustrated in each of FIG.  20 A to  FIG. 20C , all of the data signals Vda (ON), Vda (OFF) and the slot voltage Viac are voltages oscillating between 0 V and a positive voltage. The amplitude of the voltage Viac of the slot electrode is equal to the maximum value |Vda max | of the amplitude of the data signal Vda. 
     When such a signal is utilized, the driving circuit only needs to output a positive voltage, which contributes to cost reduction. As described above, even in a case where a voltage oscillating between 0 V and a positive voltage is used, as illustrated in  FIG. 20D , the polarity of the voltage Vlc (ON) applied to the liquid crystal capacitance is inverted. In the voltage waveform illustrated in  FIG. 20D , +(positive) indicates that the voltage of the patch electrode is higher than the slot voltage, and − (negative) indicates that the voltage of the patch electrode is lower than the slot voltage. That is, the direction (polarity) of the electric field applied to the liquid crystal layer is inverted similarly to the other examples. The amplitude of the voltage Vlc (ON) applied to the liquid crystal capacitance is Vda max . 
     Note that, as illustrated in  FIG. 20E , to make the voltage Vlc (OFF) applied to the liquid crystal capacitance of each antenna unit zero, as illustrated in  FIG. 20B , it may be preferable for the data signal Vda (OFF) to have the same waveform as that of the slot voltage Viac. 
     The driving method described with reference to  FIG. 19A  to  FIG. 19E  and  FIG. 20A  to  FIG. 20E  of oscillating (inverting) the voltage Viac of the slot electrodes corresponds to a driving method of inverting the counter voltage in the driving method of the LCD panels (sometimes referred to as a “common inversion drive”). In the LCD panels, since the flicker cannot be sufficiently suppressed, the common inversion drive is not utilized. In contrast, in the scanning antennas, since the flicker does not matter, the slot voltage can be inverted. Oscillation (inversion) is performed in each frame, for example (the 5H in  FIG. 19A  to  FIG. 19E  and  FIG. 20A  to  FIG. 20E  is set to 1 V (vertical scanning period or frame)). 
     In the above description, although an example of the voltage Viac of the slot electrode is described in which one voltage is applied; that is, an example in which a common slot electrode is provided for all patch electrodes, the slot electrode may be divided corresponding to one row or two or more rows of the patch electrode. Here, a row refers to a set of patch electrodes connected to one gate bus line with a TFT therebetween. By dividing the slot electrode into a plurality of row portions in this way, the polarities of the voltages of the respective portions of the slot electrode can be made independent from each other. For example, in a freely-selected frame, the polarity of the voltage applied to the patch electrodes can be inverted between the patch electrodes connected to adjacent gate bus lines. In this way, it is possible to perform row inversion in which the polarity is inverted not only for each single row (1H inversion) of the patch electrode, but also m row inversion (mH inversion) in which the polarity is inverted for every two or more rows. Of course, row inversion and frame inversion can be combined. 
     From the viewpoint of simplicity of driving, it is preferable that the polarity of the voltage applied to the patch electrode be the same in any frame, and the polarity be inverted every frame. 
     Example of Connection of Antenna Unit Array, Gate Bus Line, and Source Bus Line 
     In the scanning antenna according to the embodiments of the disclosure, the antenna units are arranged concentrically, for example. 
     For example, in a case where the antenna units are arranged in m concentric circles, one gate bus line is provided for each circle, for example, such that a total of m gate bus lines is provided. For example, assuming that the outer diameter of the transmission and/or reception region R 1  is 800 mm, m is 200, for example. Assuming that the innermost gate bus line is the first one, n (30, for example) antenna units are connected to the first gate bus line and nx (620, for example) antenna units are connected to the mth gate bus line. 
     In such an arrangement, the number of antenna units connected to each gate bus line is different. In addition, although m antenna units are connected to a number n of the source bus lines that are also connected to the antenna units constituting the innermost circle, among the nx number of source bus lines connected to nx number antenna units that constitute the outermost circle, the number of antenna units connected to other source bus lines is less than m. 
     In this way, the arrangement of antenna units in the scanning antenna is different from the arrangement of pixels (dots) in the LCD panel, and the number of connected antenna units differs depending on the gate bus line and/or source bus line. Accordingly, in a case where the capacitances (liquid crystal capacitances+auxiliary capacitances) of all the antenna units are set to be the same, depending on the gate bus line and/or the source bus line, the electrical loads of the antenna units connected thereto differ. In such a case, there is a problem where variations occur in the writing of the voltage to the antenna unit. 
     Accordingly, to prevent this, the capacitance value of the auxiliary capacitance is preferably adjusted, or the number of antenna units connected to the gate bus line and/or the source bus line is preferably adjusted, for example, to make the electrical loads of the antenna units connected to the gate bus lines and the source bus lines substantially the same. 
     As described above, the scanning antenna according to the embodiment of the disclosure uses a nematic liquid crystal material having large dielectric anisotropies Δε M  with respect to microwaves (birefringence index Δn with respect to visible light). As the liquid crystal material having large dielectric anisotropies Δε M  in the microwave region, a liquid crystal material containing a liquid crystal molecule having an isothiocyanate group (—NCS) is used. In general, since the liquid crystal material is a mixture of a plurality of types of liquid crystal molecules (liquid crystal compounds), all liquid crystal molecules contained in the liquid crystal material need not have an isothiocyanate group. 
     The isothiocyanate group is included in the liquid crystal molecule as an atomic group represented by the following chemical formula (Formula 1), for example. 
     
       
         
         
             
             
         
       
     
     The holding rate of the voltage applied to the liquid crystal capacitance is low due to the low specific resistance of the liquid crystal material containing a liquid crystal molecule having an isothiocyanate group. When the liquid crystal material deteriorates, the specific resistance further decreases, and the voltage holding rate (sometimes abbreviated as “VHR”) further decreases. A decrease of the VHR prevents the liquid crystal molecules from being aligned in a predetermined direction (that is, a desired phase difference cannot be given to the microwave), thereby deteriorating the antenna characteristics. 
     The inventor of the disclosure has discovered that the following mechanism acts as one of reasons for the deterioration of the VHR occurring when using a liquid crystal material containing liquid crystal molecules each having an isothiocyanate group. 
     The carbon atom in the isothiocyanate group has high electrophilicity and positively charges due to its polarization. Thus, a highly active metal (such as Cu or Al), its oxide, or its ion allow the carbon atom to be readily ionized (C 2+ ) as illustrated in Formula 2, causing a deterioration of the VHR. Although Formula 2 represents a reaction formula in which an isothiocyanate group is ionized by copper (Cu), it is conceivable that aluminum (Al) may also cause an ionization by a similar reaction. 
     
       
         
         
             
             
         
       
     
     The inventor has found that through conducting various experiments, as will be described later by partially demonstrating the experimental examples, a compound having an atomic group forming a coordinate bond with Cu or Al (hereinafter referred to as “coordination bond compound”) formed to be in contact with the patch electrode and the slot electrode suppresses an isocyanate group from being ionized by Cu or Al. The resin layer may be formed of an alignment film or may be additionally formed between an alignment film and an electrode. In a case when the patch electrode and the slot electrode are covered with an insulating film, the resin layer may be formed on the insulating film. Coordination bond compounds have, for example, an amide bond and a benzene ring (for example, as a phenyl group or a phenylene group). The coordination bond compounds may be, for example, oxalic acid derivatives. Hereinafter, there will be described an example of the coordination bond compounds, which is, but not limited to, oxalic acid derivatives. The resin layer may contain several types of coordination bond compounds. In addition, the resin layer provided on the patch electrode side may contain a different type of coordination bond compound from the resin layer provided on the slot electrode side. 
     As the coordination bond compounds, oxalic acid derivatives of the following compounds 1 to 5 are exemplified. The molecular weights of the compounds 1 to 5 are 294, 696, 256, 526, and 490, respectively. The molecular weight of the coordination bond compounds is preferably 1000 or less. When the molecular weight is greater than 1000, the mobility and diffusibility of the molecule may be lowered, causing the formation of coordination bonds to be suppressed. Also, a rigid structure as in polyimides also suppresses the formation of coordination bonds. Accordingly, coordination bond compounds having a structure single bonded to a benzene ring are preferred as exemplified in the compounds 1 to 5 of the following Formula 3. 
     
       
         
         
             
             
         
       
     
     Oxalic acid derivatives form coordination bonds (form complexes) with Cu ions or Al ions, suppressing an isothiocyanate group from being reacted with these ions. This allows the probability of generation of ions by the reaction illustrated in Formula 2 to be drastically reduced, thereby suppressing the VHR from being reduced. 
     The amount of the oxalic acid derivatives contained in the resin film is preferably as large as possible in order to increase the probability of forming coordination bonds (complexes). In addition, in a case when an alignment film is used as the resin layer, it is preferred that the oxalic acid derivatives are unevenly distributed on the side close to the electrode. 
     As the alignment film, an alignment film containing polyimide and/or polyamic acid (also referred to as “polyamide acid”) is widely used. By heating and imidizing the polyamic acid is produced polyimide. The polyamic acid is not necessarily fully imidized (imidization ratio=100%), but the imidization ratio can be adjusted depending on thermal condition (temperature and time). Herein, the alignment film containing polyimide and/or polyamic acid is referred to as “polyimide-based alignment film”, and the material for forming “polyimide-based alignment film” is referred to as “polyimide-based alignment film material”. 
     In a case when an alignment film including a double-layer structure is used as the alignment film, it is preferred to adopt a configuration in which a large amount of oxalic acid derivatives is contained in the lower layer (layer closer to the electrode). For example, if a polyamic acid remains on the alignment film, an advantage of reducing the residual DC (for example, WO 2010/047011) is provided. By adjusting the thermal condition using an alignment film material containing polyamic acid and polyimide, a polyamic acid-rich layer can be formed at the lower layer (electrode side) while a polyimide-rich layer at the upper layer (liquid crystal layer side). Of course, the polyamic acid-rich layer at the lower layer may be separately formed from the polyimide-rich layer at the upper layer. The lower layer preferably contains a large amount of oxalic acid derivatives. While the upper layer (layer closer to the liquid crystal layer) may not contain oxalic acid derivatives. 
     A resin layer containing oxalic acid derivatives, which is formed separately from the alignment film, may be formed, for example, by removing the solvent from a solution containing a soluble polymer and oxalic acid derivatives. As the soluble polymer, for example, an acrylic polymer may be suitably used. A thermosetting resin may also be used. As the thermosetting resin, for example, acrylate monomers (including acrylate oligomers) may be suitably used. A thermal polymerization initiator may be further added to the acrylate monomers as necessary. Note that, in this specification, acrylic and acrylate are used to represent including methacrylic and methacrylate, respectively. 
     Incidentally, the amount of the oxalic acid derivatives contained in the resin layer is preferably set at 30 mass % or less with respect to the resin. If the amount is greater than 30 mass %, the film forming properties may be deteriorated. The resin layer containing the oxalic acid derivatives may be formed using a known coating method (for example, a slot coating method) and/or a printing method (for example, a screen printing method or an ink jet method). 
     Hereinafter, a structure of a scanning antenna including an alignment film that includes a resin layer containing coordination bond compounds (hereinafter, oxalic acid derivatives) and a method of manufacturing the scanning antenna will be described. Note that the structure of the liquid crystal panel in the scanning antenna will be described below. The liquid crystal panel includes a TFT substrate, a slot substrate, and a liquid crystal layer LC provided therebetween, and liquid crystal panels  10 A,  100 B,  100 C, and  100 D exemplified below are each featured in the structure of the alignment film and the method of forming the alignment film. The liquid crystal panels  100 A,  100 B,  100 C, and  100 D may be applied to any one of the above-described scanning antennas. In  FIG. 21  to  FIG. 24  illustrating the liquid crystal panels  100 A,  100 B,  100 C, and  100 D, common reference numbers are denoted to structural elements common to the previous drawings, and no descriptions for such structural elements may be provided below. 
       FIG. 21  is a schematic cross-sectional view of the liquid crystal panel  100 A. The liquid crystal panel  100 A includes a TFT substrate  101 A, a slot substrate  201 A, and a liquid crystal layer LC provided therebetween. The patch electrode  15  of the TFT substrate  101 A and the slot electrode  55  of the slot substrate  201 A are covered with alignment films  32 A and  42 A, respectively. The patch electrode  15  and the slot electrode  55  are each independently formed of, for example, Al or Cu. The alignment films  32 A and  42 A are formed of a polyimide-based alignment film material each independently selected, and each of the films contains coordination bond compounds. 
       FIG. 22  is a schematic cross-sectional view of the liquid crystal panel  100 B. In the liquid crystal panel  100 B, the patch electrode  15  of the TFT substrate  101 B and the slot electrode  55  of the slot substrate  201 B are covered with alignment films  32 B and  42 B, respectively. 
     The alignment films  32 B and  42 B include polyamic acid (-rich) layers  32   a  and  42   a  at the lower layer (substrate side) and polyimide (-rich) layers  32   b  and  42   b  at the upper layer (liquid crystal layer side). The polyamic acid (-rich) layers  32   a  and  42   a  at the lower layer contains coordination bond compounds, while the upper polyimide (-rich) layers  32   b  and  42   b  contains no coordination bond compounds. 
       FIG. 23  is a schematic cross-sectional view of the liquid crystal panel  100 C. In the liquid crystal panel  100 C, the patch electrode  15  of the TFT substrate  101 C and the slot electrode  55  of the slot substrate  201 C are covered with resin layers  34  and  44  containing coordination bond compounds, respectively. The resin layers  34  and  44  are covered with alignment films  32 C and  44 C, respectively. 
       FIG. 24  is a schematic cross-sectional view of the liquid crystal panel  100 D. In the liquid crystal panel  100 D, the patch electrode  15  of the TFT substrate  101 D and the slot electrode  55  of the slot substrate  201 D are covered with a second insulating layer  27  and a fourth insulating layer  58 , respectively, and the second insulating layer  27  and the fourth insulating layer  58  are covered with alignment films  32 A and  42 A, respectively. That is, the liquid crystal panel  100 D corresponds to the liquid crystal panel  100 A further provided with the second insulating film  17  and the fourth insulating film  58  covering the patch electrode  15  and the slot electrode  55 . 
     Similarly, the second insulating film  17  and the fourth insulating film  58  may be provided to cover the patch electrode  15  and the slot electrode  55  in the liquid crystal panels  100 B and  100 C. 
     EXPERIMENTAL EXAMPLES 
     Hereinafter, Experimental Examples are described to explain that a provision of a resin layer containing coordination bond compounds suppresses the deterioration of the antenna characteristics of the scanning antenna occurring when using a liquid crystal material containing liquid crystal molecules each having an isothiocyanate group. 
     Experimental Example 1 
     As illustrated in the Table 1 below, test panels (Samples 2 to 4) including the structure of the liquid crystal panel  100 A illustrated in  FIG. 21  were prepared varying mass % of the oxalic acid derivatives of the compound 1 to be blended into the polyimide-based alignment film material. The patch electrode  15  and the slot electrode  55  were each formed with an Al layer. 
     Polyimide alignment film materials were used in which X in the structural formulas (1) and (2) denoted in Formula 4 is represented by the following Formula 5 and Y is represented by the following Formula 6. The initial imidization ratio was approximately 50%. The degree of polymerization m determined by GPC was within the range of approximately from 50 to 400. 
     
       
         
         
             
             
         
       
     
     Samples 2, 3, and 4 were prepared by liquid crystal panels in which the alignment films are formed using polyimide-based alignment film materials into which the oxalic acid derivatives of the compound 1 are blended by 10 mass %, 20 mass %, and 30 mass % with respect to the alignment film material. Sample 1 was prepared by a liquid crystal panel in which the alignment film is formed using a polyimide-based alignment film material not containing the compound 1. The smaller the introduction amount (mass %) of the oxalic acid derivatives with respect to the polyimide-based alignment film material, although the film forming properties are maintained, the less the effect of improving the reliability due to the formation of the complexes. Meanwhile, the larger the introduction amount of the oxalic acid derivatives, the higher the effect of improving the reliability due to the formation of the complexes, however, if the introduction amount exceeds 30 mass % with respect to the resin, the film may become opaque. When the film becomes opaque, for example, a film peeling may occur at the time of rubbing, exerting influence on the alignment properties of the liquid crystal. 
     Alignment film solutions (solid content concentration: 3 mass %) in which each of the alignment film materials described above is dissolved in a solvent (mixed solvent of NMP and γ-butyl lactone) were prepared and applied onto a TFT substrate and a slot substrate. Subsequently, a temporary baking was carried out at 80° C. for 2 minutes, followed by the final baking at 200° C. for 40 minutes. After performing a rubbing treatment as an alignment treatment, the two substrates were bonded together using a thermosetting sealing material. Note that the cell gap (=the thickness of the liquid crystal layer) was adjusted to 3.0 μm by a spacer. The sealing material was cured by heating at 150° C. for 40 minutes. A liquid crystal material having liquid crystal molecules each having an isothiocyanate group was injected. Lastly, the injection port was sealed with an ultraviolet light curable sealing material to prepare test panels. 
     The voltage holding rate (VHR) was evaluated before and after the high-temperature test. The VHR was measured, using a 6254 type VHR measurement system available from Toyo Technica Co., Ltd., by applying a rectangular wave having an amplitude of ±1 V and a frequency of 60 Hz. The measurement temperature was set at 70° C. The high-temperature test was conducted in a thermostat at 90° C. for 24 hours. The values of the VHR before and after the high-temperature test are listed in Table 1. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                   
                 After high- 
               
               
                   
                 Coordination bond compound 1 
                 Initial 
                 temperature 
               
               
                   
                 in Alignment film 1 
                 stage 
                 test 
               
               
                   
                 Contained amount (mass %) 
                 VHR (%) 
                 VHR (%) 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                 Sample 1 
                 0 
                 93 
                 54 
               
               
                 Sample 2 
                 10 
                 92 
                 66 
               
               
                 Sample 3 
                 20 
                 92 
                 75 
               
               
                 Sample 4 
                 30 
                 93 
                 75 
               
               
                   
               
            
           
         
       
     
     In Sample 1 not containing oxalic acid derivatives in the alignment film, the VHR was decreased to 54% after the high-temperature test. The electrode formed of an Al layer conceivably leads to, like the case of Cu described above, an ionization of Al, and an ionization of an isothiocyanate group caused by the reaction of Al and isothiocyanate group. 
     Samples 2 to 4 containing the oxalic acid derivatives of the compound 1 maintains, even after the high-temperature test, the VHR at a value of 65% or more and Samples 3 and 4 containing 20 mass % or more of the compound 1 maintains the VHR at a value of 75%. It is conceivable that the oxalic acid derivatives contained in the alignment film form coordination bonds with Al (ions) to inactivate the Al, thereby suppressing the ionization of the isothiocyanate group and preventing the decrease of the VHR. 
     Experimental Example 2 
     Test panels (Samples 5 to 8) including the structure of the liquid crystal panel  100 B illustrated in  FIG. 22  were prepared. The patch electrode  15  and the slot electrode  55  were each formed with an Al layer. A polyimide-based alignment film material having the basic structure as in Experimental Example 1 was used. However, to form the lower layer of the alignment film was used an alignment film material of the imidization ratio of 0%, that is, an alignment film material consisting only of the polyamic acid of the structural formula (2). 
     Samples 6, 7, and 8 were prepared by liquid crystal panels in which the alignment films are formed using alignment film materials of a polyamic acid (imidization ratio 0%) into which the oxalic acid derivatives of the compound 2 are blended by 10 mass %, 20 mass %, and 30 mass % with respect to the alignment film material. Sample 5 was prepared by a liquid crystal panel in which the alignment film is formed using a polyimide-based alignment film material not containing the compound 2. 
     Alignment film solutions (solid content concentration: 3 mass %) in which each of the alignment film materials for the lower layers described above is dissolved in a solvent (mixed solvent of NMP, butyl cellosolve, and γ-butyl lactone) were prepared and applied onto a TFT substrate and a slot substrate. Subsequently, a temporary baking was carried out at 80° C. for 2 minutes, followed by the final baking at 160° C. for 40 minutes. 
     Next, as alignment film materials for the upper layers, alignment film solutions (solid content concentration: 3 mass %) in which a polyimide-based alignment film material (not containing oxalic acid derivatives) of the imidization ratio 50% is dissolved in a solvent (mixed solvent of NMP and butyl cellosolve) were prepared and applied onto the lower layers formed as described above, and to which a temporary baking was carried out at 80° C. for 2 minutes, followed by the final baking at 200° C. for 40 minutes. After performing a rubbing treatment as an alignment treatment, test panels were prepared in the same manner as in Experimental Example 1. 
     The test panels (Samples 5 to 8) thus prepared were evaluated in the same manner as in Experimental Example 1. The results are listed in Table 2 below. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                   
                   
                 After high- 
               
               
                   
                 Coordination bond compound 2 in 
                 Initial 
                 temperature 
               
               
                   
                 the lower layer of the alignment 
                 stage 
                 test 
               
               
                   
                 film Contained amount (mass %) 
                 VHR (%) 
                 VHR (%) 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                 Sample 5 
                 0 
                 95 
                 59 
               
               
                 Sample 6 
                 10 
                 93 
                 76 
               
               
                 Sample 7 
                 20 
                 95 
                 80 
               
               
                 Sample 8 
                 30 
                 95 
                 84 
               
               
                   
               
            
           
         
       
     
     In Sample 5 not containing the oxalic acid derivatives of the compound 2 in the lower layers of the alignment film, the VHR was decreased to 60% or less after the high-temperature test. Meanwhile, in Samples 6 to 8 containing the oxalic acid derivatives of the compound 2, the VHRs were maintained at a high value of 75% or more even after the high-temperature test, and in Samples 7 and 8 containing the compound 2 at 20 mass % or more, the VHRs were maintained at a high value of 85% or more. This proves that oxalic acid derivatives are blended into only the lower layers (electrode side) of the alignment film including the double-layer structure, whereby the VHR is effectively improved. 
     Experimental Example 3 
     Test panels (Samples 11 to 13) including the structure of the liquid crystal panel  100 C illustrated in  FIG. 23  were prepared. A test panel (Sample 9) not including the resin layers  34  and  44  and a test panel (Sample 10) provided with a resin layer not including oxalic acid derivatives were also prepared for comparison. The patch electrode  15  and the slot electrode  55  were formed with a Cu layer. 
     Solutions were prepared by blending into NMP solutions of ethyl acrylate polymer, 10 mass %, 20 mass %, and 30 mass % of the oxalic acid derivatives of the compound 1 with respect to the polymer. Each of the solutions was applied onto a TFT substrate and a slot substrate. Subsequently, a baking was carried out at 180° C. for 15 minutes to form the resin layers  34  and  44  containing the compound 1. 
     Next, alignment film solutions (solid content concentration: 3 mass %) in which a polyimide-based alignment film material (not containing oxalic acid derivatives) is dissolved in a solvent (mixed solvent of NMP, butyl cellosolve, and γ-butyl lactone) were prepared and applied onto the resin layers formed as described above, and to which a temporary baking was carried out at 80° C. for 2 minutes, followed by the final baking at 230° C. for 40 minutes. After performing a rubbing treatment as an alignment treatment, test panels were prepared in the same manner as in Experimental Example 1. 
     The test panels (Samples 9 to 13) thus prepared were evaluated in the same manner as in Experimental Example 1. The results are listed in Table 3 below. 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                   
                 Coordination bond 
                   
                 After high- 
               
               
                   
                 Acrylic 
                 compound 1 in Acrylic 
                 Initial 
                 temperature 
               
               
                   
                 resin 
                 resin layer Contained 
                 stage 
                 test 
               
               
                   
                 layer 
                 amount (mass %) 
                 VHR (%) 
                 VHR (%) 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 Sample 9 
                 No 
                 — 
                 93 
                 50 
               
               
                 Sample 10 
                 Yes 
                  0 
                 94 
                 51 
               
               
                 Sample 11 
                 Yes 
                 10 
                 93 
                 60 
               
               
                 Sample 12 
                 Yes 
                 20 
                 93 
                 70 
               
               
                 Sample 13 
                 Yes 
                 30 
                 94 
                 71 
               
               
                   
               
            
           
         
       
     
     In Sample 9 not including a resin layer and in Sample 10 including a resin layer but not including oxalic acid derivatives, the VHRs were decreased to nearly 50% after the high-temperature test. Meanwhile, in Samples 11 to 13 containing the oxalic acid derivatives of the compound 1, the VHRs are maintained at a high value of 60% or more even after the high-temperature test, and in Samples 12 and 13 containing the compound 1 at 20 mass % or more, the VHRs are maintained at a high value of 70% or more. It is conceivable that the oxalic acid derivatives contained in the resin layer form coordination bonds with Cu (ions) to inactivate the Cu, thereby suppressing the ionization of the isothiocyanate group and preventing the decrease of the VHR. 
     Experimental Example 4 
     Test panels (Samples 15 to 17) including the structure of the liquid crystal panel  100 D illustrated in  FIG. 24  were prepared. A test panel (sample 14) provided with a resin layer not containing oxalic acid derivatives in the alignment film was also prepared for comparison. The patch electrode  15  and the slot electrode  55  were formed with a Cu layer. The insulating layers  17  and  58  covering the patch electrode  15  and the slot electrode  55  were formed with a SiN layer (thickness 200 nm). 
     A polyimide-based alignment film material (imidization ratio 50%) as in Experimental Example 1 was used. Samples 15, 16, and 17 were prepared by liquid crystal panels in which the alignment films are formed using polyimide-based alignment film materials into which the oxalic acid derivatives of the compound 2 are blended by 10 mass %, 20 mass %, and 30 mass % with respect to the alignment film material. Sample 14 was prepared by a liquid crystal panel in which the alignment film is formed using a polyimide-based alignment film material not containing the compound 2. 
     Alignment film solutions (solid content concentration: 3 mass %) in which each of the alignment film materials described above is dissolved in a solvent (mixed solvent of NMP, butyl cellosolve, and γ-butyl lactone) were prepared and applied onto a TFT substrate and a slot substrate. Subsequently, a temporary baking was carried out at 80° C. for 2 minutes, followed by the final baking at 230° C. for 40 minutes. After performing a rubbing treatment as an alignment treatment, test panels were prepared in the same manner as in Experimental Example 1. 
     The test panels (Samples 14 to 17) thus prepared were evaluated in the same manner as in Experimental Example 1. The results are listed in Table 4 below. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 4 
               
               
                   
                   
               
               
                   
                   
                   
                 After high- 
               
               
                   
                 Coordination bond compound 2 
                 Initial 
                 temperature 
               
               
                   
                 in Alignment film 
                 stage 
                 test 
               
               
                   
                 Contained amount (mass %) 
                 VHR (%) 
                 VHR (%) 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                 Sample 14 
                 0 
                 96 
                 78 
               
               
                 Sample 15 
                 10 
                 96 
                 89 
               
               
                 Sample 16 
                 20 
                 96 
                 91 
               
               
                 Sample 17 
                 30 
                 96 
                 91 
               
               
                   
               
            
           
         
       
     
     In view of the result of Sample 14, it can be recognized that a configuration in which the patch electrode and the slot electrode are covered with an insulating layer formed from an SiN layer makes it possible to maintain, even when using an alignment film not containing oxalic acid derivatives, the VHR at a high value of 78% after the high-temperature test. In Samples 15 to 17 containing the oxalic acid derivatives of the compound 2, the VHRs are approximately 90% after the high-temperature test, thereby further improving the reliability. 
     As described above, the scanning antenna according to the embodiment of the disclosure suppresses the deterioration of the antenna characteristic occurring when using a liquid crystal material including liquid crystal molecules each having an isothiocyanate group. 
     The scanning antenna according to the embodiments of the disclosure is housed in a plastic housing as necessary, for example. It is preferable to use a material having a small dielectric constant ε M  that does not affect microwave transmission and/or reception in the housing. In addition, the housing may include a through-hole provided in a portion thereof corresponding to the transmission and/or reception region R 1 . Furthermore, the housing may include a light blocking structure such that the liquid crystal material is not exposed to light. The light blocking structure is, for example, provided so as to block light that propagates through the dielectric substrate  1  and/or  51  from the side surface of the dielectric substrate  1  of the TFT substrate  101  and/or the side surface of the dielectric substrate  51  of the slot substrate  201  and is incident upon the liquid crystal layer. A liquid crystal material having a large dielectric anisotropy Δε M  may be prone to photodegradation, and as such it is preferable to shield not only ultraviolet rays but also short-wavelength blue light from among visible light. By using a light-blocking tape such as a black adhesive tape, for example, the light blocking structure can be easily formed in necessary locations. 
     INDUSTRIAL APPLICABILITY 
     The embodiments according to the disclosure are used, for example, for a scanning antenna for satellite communication or satellite broadcasting installed on a moving body (for example, a ship, an airplane, or a car) and a method of manufacturing the scanning antenna. 
     REFERENCE SIGNS LIST 
     
         
           1  Dielectric substrate 
           2  Base insulating film 
           3  Gate electrode 
           4  Gate insulating layer 
           5  Semiconductor layer 
           6 D Drain contact layer 
           6 S Source contact layer 
           7 D Drain electrode 
           7 S Source electrode 
           7   p  Source connection wiring line 
           11  First insulating layer 
           15  Patch electrode 
           15   p  Patch connection section 
           17  Second insulating layer 
           18   g ,  18   s ,  18   p  Opening 
           19   g  Gate terminal upper connection section 
           19   p  Transfer terminal upper connection section 
           19   s  Source terminal upper connection section 
           21  Alignment mark 
           23  Protective conductive layer 
           32 A,  32 B,  32 C Alignment film 
           34  Resin layer 
           42 A,  42 B,  42 C Alignment film 
           44  Resin layer 
           51  Dielectric substrate 
           52  Third insulating layer 
           54  Dielectric layer (air Layer) 
           55  Slot electrode 
           55 L Lower layer 
           55 M Main layer 
           55 U Upper layer 
           55   c  Contact surface 
           57  Slot 
           58  Fourth insulating layer 
           60  Upper connection section 
           65  Reflective conductive plate 
           67  Adhesive layer 
           68  Heater resistive film 
           70  Power supply device 
           71  Conductive beads 
           72  Power feed pin 
           73  Sealing portion 
           101 ,  102 ,  103 ,  104  TFT substrate 
           201 ,  203  Slot substrate 
           1000  Scanning antenna 
         CH 1 , CH 2 , CH 3 , CH 4 , CH 5 , CH 6  Contact hole 
         GD Gate driver 
         GL Gate bus line 
         GT Gate terminal section 
         SD Source driver 
         SL Source bus line 
         ST Source terminal section 
         PT Transfer terminal section 
         IT Terminal section 
         LC Liquid crystal layer 
         R 1  Transmission and/or reception region 
         R 2  Non-transmission and/or reception region 
         Rs Seal region 
         U, U 1 , U 2  Antenna unit, Antenna unit region