Patent Publication Number: US-6905893-B1

Title: Method and structure for determining a concentration profile of an impurity within a semiconductor layer

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation in part of Ser. No. 10/023,065, filed Dec. 17, 2001, now U.S. Pat. No. 6,664,120. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to determining material composition, and more particularly to a method and a structure for determining one or more component concentrations contained in a material. 2. Description of the Related Art 
   The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section. 
   Compositional analysis of materials is desirable for many applications. For example, the type of adhesive applied to a tape product or the type of metal or paint applied to a product for corrosion protection is critical for the functionality of the products. The method and structure described herein are discussed primarily with respect to the analysis of thin films within semiconductor devices. The term “thin film” is commonly used within the semiconductor industry when referring to layers deposited upon a semiconductor wafer during the fabrication of a transistor. Specialized materials are selected for thin films to perform specific functions of the transistor. In order for a thin film to be effective, it must conform to strict electrical, chemical, and structural requirements. Thin film materials may include, but are not limited to, metallic, semiconducting, and dielectric materials or a combination of such materials. Often, thin films are doped with impurities to heighten the effectiveness of the material used. 
   Inaccurate analysis of one or more process parameters within the fabrication of a semiconductor device, such as a transistor, may hinder or prohibit the function of the device, leading to a reduction in production efficiency and device quality. The characterization of thin films is especially important, since the effectiveness and reliability of thin films play an important, central role in the operation of a semiconductor device. Therefore, thin films must be accurately analyzed in order to meet a semiconductor device&#39;s functionality requirements. In addition, as production volumes and efforts to improve process control increase in the integrated circuit fabrication industry, the ability to accurately characterize semiconductor processes and the materials associated with such processes in a timely manner becomes more critical. 
   At present, it is difficult to find an analytical technique suitable for use in semiconductor fabrication that can characterize the composition of a thin film in a simple, accurate, and cost-effective manner. Many current techniques require large pieces of equipment, such as spectrometers that are not used within a fabrication area due to size and cleanliness requirements. Some of these techniques may include, for example, Secondary Ion Mass Spectroscopy (SIMS), Auger Electron Spectroscopy (AES), and X-ray Photoelectron Spectroscopy (XPS). In addition, current techniques typically employ expensive equipment, thereby increasing the fabrication cost of the semiconductor devices. In some cases, a manufacturer may decide to forego the additional costs of purchasing a piece of analytical equipment and send samples to an outside testing facility. Such an option requires additional time for the analysis to be conducted. Often, the amount of time required for such an outside analysis is on the order of a few days or weeks. As a result, production throughput and efficiency is sacrificed due to the increased process cycle time of the devices. Consequently, many current analysis techniques do not coincide with the desire within the semiconductor fabrication industry to increase production efficiency and improve process control. 
   It would, therefore, be advantageous to create a method and a structure with which to determine the composition of a material in a simple, accurate, and cost-effective manner. Such a method and structure would be particularly beneficial for determining the concentrations of an impurity within a thin film of a semiconductor device. 
   SUMMARY OF THE INVENTION 
   The problems outlined above may be in large part addressed by a method and a structure for measuring a concentration of an impurity within a layer arranged upon an underlying layer. Such an impurity may include any species adapted to enhance or retard oxidation of the layer. For example, the impurity may include nitrogen, fluorine, xenon, iodine, or silicon. In some cases, the method may include designating a plurality of measurement locations on the layer. In this manner, a concentration profile of the impurity within the layer may be determined. In some embodiments, the method may produce a lateral concentration profile. As such, designating the measurement locations along the layer may include identifying a plurality of points on the layer having the substantially similar thicknesses in some embodiments. In an alternative embodiment, the method may produce a depth concentration profile. In such an embodiment, designating the measurement locations may include identifying a plurality of points on the layer, which correspond to different thickness increments of the layer. In yet another embodiment, the method may produce a lateral and a depth concentration profile. In any of the embodiments, designating the measurement locations may further include identifying a subset of the plurality of points on the layer. For example, designating the measurement locations may include identifying a subset of the plurality of points located at an equal distance from the center of the semiconductor topography. 
   In general, the methods for determining a concentration of an impurity may include comparing first and second attributes of an upper portion of the semiconductor topography comprising the layer. In a preferred embodiment, the first attribute may be obtained prior to an oxidation process used to fabricate the semiconductor topography and the second attribute may be obtained subsequent to such an oxidation process. In some cases, the first attribute may include thicknesses of the layer within the upper portion of the semiconductor topography and the second attribute may include thicknesses of total dielectric within the upper portion of the semiconductor topography. In other embodiments, the first attribute may include depth localities within the layer relative to a prior upper surface of the layer. Alternatively, the first attribute may include positions arranged across the layer relative to a specific location. In either case, the second attribute may include concentrations of the impurity within the layer. More specifically, the concentrations of the impurity may include concentrations specific to thickness increments of the layer in some cases. In yet other embodiments, the concentrations of the impurity may include concentrations of the impurity within the entire layer. In any case, the method may include determining the concentration profile of the impurity from the comparison of the first and second attributes. In some cases, such a comparison may include plotting the first attribute versus the second attribute. In yet other embodiments, the comparison may include calculating thickness deltas between the first and second attributes and correlating the thickness deltas to concentrations of the component. 
   As noted above, the first and second attributes may be obtained prior to and subsequent to an oxidation process used to fabricate the semiconductor topography. As such, in some embodiments, the method may include exposing the layer and an underlying layer to oxidizing conditions. Such a step of exposing the layer and underlying layer may include forming an oxidized interface between the layer and the underlying layer. Preferably, the oxidized interface is thicker underneath portions of the layer with a relatively low concentration of the impurity than underneath portions of the layer with a relatively high concentration of the impurity. Consequently, the method may further include determining a difference in total dielectric thickness above the underlying layer before and after exposing the layer and the underlying layer. 
   In some embodiments, the method may further include removing a portion of the layer including the measurement locations prior to exposing the layer and semiconductor substrate. In some cases, removing the portion of the layer may include forming a substantially level surface across the entirety of the layer. Alternatively, removing the portion of the layer may include forming a sloped or stepped surface across at least a portion of the layer. In such an embodiment, the thickness increments of the measurement locations may range from greater than approximately 0 angstroms to the thickness of the layer prior to removing the portion of the layer. In addition or alternatively, the thickness increments of the measurement locations, in such an embodiment, may vary incrementally by less than 20% of the thickness of the layer prior to removing the portion of the layer. In a preferred embodiment, correlating the thickness delta to the concentration of the impurity may include subtracting a concentration of the impurity within a first thickness increment of the layer from a concentration of the impurity within a second thickness increment of the layer. In such an embodiment, the second thickness increment is preferably greater than the first thickness increment. 
   A semiconductor topography is also contemplated herein. Such a semiconductor topography may include an oxidized interface between a semiconductor substrate and a layer comprising an impurity, wherein a thickness of the oxidized interface is dependent upon a concentration of the impurity within a respective portion of the layer. For example, in some embodiments, the first thickness of the oxidized interface may be larger than a second thickness of the oxidized interface. In such an embodiment, the concentration of the impurity within a portion of the layer corresponding to the portion of the oxidized interface with the first thickness may be larger than the concentration of the impurity within a portion of the layer corresponding to the portion of the oxidized interface with the second thickness. In some embodiments, the layer may include a sloped surface. In other embodiments, the layer may include a stepped surface. In yet another embodiment, the layer may include a substantially level surface. In some cases, the thickest portion of the layer may be approximately 100 angstroms or less. More specifically, the thickest portion of the layer may be approximately 35 angstroms or less. In either embodiment, the layer may include, for example, silicon oxynitride, silicon dioxide/silicon nitride/silicon dioxide, or fluorine doped silicon oxide. 
   There may be several advantages to determining the concentration of an impurity within a layer using the method and structure described herein. For example, the method and structure described herein may offer a manner with which to analyze the impurity concentration of a thin film of a semiconductor device in an accurate and timely manner. In particular, the method described herein may determine an impurity concentration of a thin film within a semiconductor fabrication area in less than approximately one hour. Such a method may be particularly advantageous over the conventional method of sending samples to an outside testing facility and waiting days or weeks for the results. As such, process cycle time may be decreased, thereby increasing production efficiency. In addition, the method described herein may advantageously reduce fabrication costs. In particular, outside testing fees and/or expensive equipment used for in-house analysis do not have to be expensed or purchased, thereby decreasing fabrication costs. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: 
       FIG. 1  depicts a partial cross-sectional view of a semiconductor topography in with a layer arranged above a semiconductor substrate; 
       FIG. 2   a  depicts a partial cross-sectional view of the semiconductor topography in which a portion of the layer of  FIG. 1  is removed to form a sloped surface; 
       FIG. 2   b  depicts a partial cross-sectional view of the semiconductor topography, in an alternative embodiment, in which a portion of the layer of  FIG. 1  is removed to form a stepped surface; 
       FIG. 2   c  depicts a partial cross-sectional view of the semiconductor topography, in an alternative embodiment, in which a portion of the layer of  FIG. 1  is removed to form a different stepped surface; 
       FIG. 3  depicts a top view of the semiconductor topography of  FIG. 1 ,  2   a ,  2   b , or  2   c  with a plurality of measurement points; 
       FIG. 4  depicts a partial cross-sectional view of the semiconductor topography in which the layer and semiconductor substrate are exposed to oxidizing conditions subsequent to the sloped surface formation of  FIG. 2   a;    
       FIG. 5  depicts a flowchart of a method for measuring the impurity concentration of a material; 
       FIG. 6  depicts a plot of impurity concentrations with respect to thickness increments of a layer; and 
       FIG. 7  depicts an impurity concentration profile of a layer. 
   

   While the invention may include various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Turning to the drawings, exemplary embodiments of a method for measuring a concentration of an impurity within a layer of a semiconductor topography is shown in  FIGS. 1-7 . Moreover,  FIGS. 1-7  illustrate a method for determining a concentration profile of an impurity within such a layer. In general, the arrangement of impurities within a material may differ. In particular, one or more portions of a layer may include higher concentrations of an impurity than other portions of the layer. The method described herein offers a technique by which to determine the concentration of an impurity within a particular location of a layer. In addition or alternatively, the method described herein may be used to determine the concentration profile of an impurity within a layer with a graded refractive index. In general, an impurity may refer to any species deliberately introduced into a material. In a preferred embodiment of the method described herein, the impurity may include any species adapted to enhance or retard oxidation of the material. For example, the impurity may include nitrogen, fluorine, xenon, iodine, or silicon. 
     FIG. 1  depicts a partial cross-sectional view of semiconductor topography  10  with dielectric  14  formed above semiconductor substrate  12 . More specifically,  FIG. 1  shows semiconductor topography  10  with dielectric  14  formed upon and in contact with semiconductor substrate  12 . Semiconductor substrate  12  preferably includes silicon. As such, semiconductor substrate  12  may be a monocrystalline silicon substrate. In other embodiments, semiconductor substrate  12  may include an epitaxial silicon layer grown on a monocrystalline silicon substrate or a silicon on insulator (SOI) layer formed upon a monocrystalline substrate. In addition or alternatively, semiconductor substrate  12  may be doped either n-type or p-type. Dielectric  14  may include any of various dielectric materials containing silicon, oxygen, and/or one or more impurity species. For example, dielectric  14  may include silicon-rich oxide, nitrided silicon dioxide, silicon oxynitride, fluorine-doped silicon dioxide, xenon-doped silicon dioxide, iodine-doped silicon dioxide, or any combination of such materials. Dielectric  14  is preferably a thin film and, therefore, may have a thickness between approximately 30 angstroms and approximately 100 angstroms. However, larger or smaller thicknesses of dielectric  14  may be appropriate depending on the process conditions of the method described herein. 
     FIGS. 2   a - 2   c  illustrate the removal of a portion of dielectric  14  across semiconductor topography  10 . In particular,  FIG. 2   a  illustrates the removal of a portion of dielectric  14  such that a sloped surface is formed. In contrast,  FIG. 2   b  illustrates the removal of a portion of dielectric  14  such that a stepped surface is formed. In either embodiment, the removal of dielectric  14  may be particularly advantageous for determining a depth concentration profile of an impurity within dielectric  14 . On the other hand,  FIG. 2   c  shows an alternative embodiment, in which a stepped surface of a different configuration is formed within dielectric  14 . Such an alternative configuration may be particularly advantageous for compiling a combination concentration profile, detailing both lateral and depth concentration variations of an impurity within dielectric  14 . More specifically, the configuration of  FIG. 2   c  may allow a depth concentration profile on both sides of measurement location  26  to be determined, thereby allowing portions of dielectric  14  to be laterally compared. 
   In yet another embodiment (not shown), a portion of dielectric  14  may be removed such that a substantially level surface is formed, i.e., an upper portion of dielectric  14  comprising a substantially uniform thickness may be removed to form an upper surface similar to that of FIG.  1 . Such a removal of dielectric  14  may be particularly advantageous for determining a lateral concentration profile of an impurity at a specific depth within dielectric  14 . In yet other embodiments, portions of dielectric  14  may not be removed for the method described herein. In such a case, the method may be used to determine a lateral concentration profile of an impurity within the upper surface or the entirety of the layer. In any of the embodiments, lateral surfaces  16  and  18  of semiconductor topography  10  are drawn to indicate the continuation of semiconductor topography  10  across a semiconductor wafer. As such, the removal of portions of dielectric  14 , in some embodiments, may only be across a portion of a wafer. In other embodiments, however, lateral surfaces  16  and  18  of semiconductor topography  10  may indicate the outer edge of a semiconductor wafer. In such an embodiment, the removal of portions of dielectric  14  may extend across an entire wafer. 
   The removal of portions of dielectric  14  may be conducted in a variety of manners. For example, portions of dielectric  14  may be patterned by a photolithography process to subsequently form a stepped surface. In an alternative embodiment, dielectric  14  may be etched to form a substantially level or sloped surface. In either embodiment, the removal of portions of dielectric  14  may include using either wet or dry etch techniques. For example, in one embodiment, a semiconductor wafer comprising semiconductor topography  10  may be exposed to a wet etch chemistry such that a sloped surface may be obtained. Such a method may include positioning lateral surface  18  in the chemistry and gradually moving the remainder of the wafer such that lateral surface  16  is the last portion of the wafer to be submerged in the chemistry. The method may further continue by removing the wafer from the chemistry along the path of entry. In this manner, the portion of dielectric  14  arranged between lateral surfaces  16  and  18  may be graded or sloped, since the portions of dielectric  14  arranged adjacent to lateral surface  18  may be etched progressively longer than the portions of dielectric  14  arranged adjacent to lateral surface  16 . Several other methods known to those in semiconductor fabrication for removing portions of a dielectric material may be performed to obtain a desired cross-sectional profile of dielectric  14 . As such, the methods for removal of portions of dielectric  14  are not restricted to the methods described herein for removing portions of dielectric  14 . 
   In general, any of the structures of  FIGS. 1-2   c  may be used in the method described herein for measuring the concentration of an impurity within dielectric  14 . Likewise, any of the structures of  FIGS. 1-2   c  may be used to determine a concentration profile of an impurity within dielectric  14 . In particular, configurations with a substantially level surface, such as that of  FIG. 1 , may be used to determine a lateral concentration profile of an impurity within dielectric  14 , while  FIGS. 2   a - 2   c  may be used to determine depth or combination concentration profiles of an impurity within dielectric  14  as noted above. In addition, several other structures with alternative configurations of dielectric  14  may be used in the method described herein. For example, a structure with a dielectric layer with opposing sloped surfaces similar to the opposing stepped surfaces of  FIG. 2   c  may be used. In addition, a structure with a portion of dielectric  14  removed but comprising a substantially level surface may be used. Furthermore, the surface configuration of dielectric  14  need not be symmetrical or uniform in order for it to be used in the method described herein. In this manner, the surface configuration of dielectric  14  may include a variety of stepped surface configurations disproportionate from each other. In addition or alternatively, the surface configuration may include a variety of sloped surfaces of different angles and lengths. As such, the configurations of dielectric  14  illustrated in  FIGS. 1-2   c  are shown as exemplary embodiments and are not to be construed as the only configurations available for use in the method described herein. 
   As shown in  FIGS. 1-2   c , measurement locations  20 - 32  may be designated across semiconductor topography  10  and more specifically upon dielectric  14 . Such a designation of measurement points may be performed before or after the removal of portions of dielectric  14 . In general, the measurement points may be located with respect to various references, such as wafer flats or alignments marks formed on the substrate. In an embodiment in which a lateral concentration profile is to be determined, designating measurement locations  20 - 32  may include identifying a plurality of points on dielectric  14  having substantially the same thickness as shown in FIG.  1 . In an embodiment in which a depth concentration profile is to be determined, designating measurement locations  20 - 32  may include identifying a plurality of points corresponding to different thickness increments of dielectric  14  as shown in  FIGS. 2   a - 2   c . In this manner, each of the measurement locations may represent a different thickness increment of the dielectric. 
   The thickness increments of the dielectric may refer to distinct sublayers of the dielectric. An illustration of such thickness increments may be most easily illustrated in  FIG. 2   b  with the stepped surface of dielectric  12 . In particular, thickness increments  31   a - 31   g  are shown relative to the stepped surface of dielectric  14 . As such, thickness increment  31   a  may represent an uppermost portion of dielectric  14  residing above thickness increment  31   b  and thickness increment  31   g  may represent a lowermost portion of dielectric  14  residing below thickness increment  31   f . Thickness increments  31   a - 31   g  may individually represent sublayers of dielectric  14  interposed between respective overlying and underlying thickness increments. Although thickness increments  31   a - 31   g  are shown relative to the stepped surface of dielectric  14  in  FIG. 2   b , such an assignment of thickness increments may be applied to the sloped surfaces of FIGS  2   a  as well. In addition, although thickness increments  31   a - 31   g  are shown in sequential order of thickness, the upper surface of dielectric  14  may vary such that thickness increments  31   a - 31   g  are not incrementally aligned. For example, dielectric  14 .in the embodiment of  FIG. 2   c  may include thickness increments of varying depths on either side of semiconductor topography  10 . 
   As shown in  FIGS. 2   b , dielectric  14  may be divided into several thickness increments. In some embodiments, the number of thickness increments may correspond to the number of measurement locations designated upon dielectric  14 . For example, in the embodiments of  FIGS. 1-2   c , dielectric  14  may include seven distinct thickness increments. Fewer or more thickness increments, however, may be included depending on the intricacy of the desired concentration profile. For example, more than one measurement point may be designated per thickness increment. In this manner, a greater number of measurement points than thickness increments may be designated across the topography. In particular, one or more of thickness increments  31   a - 31   g  may include a plurality of measurement points. In other embodiments, fewer measurement points than thickness increments may be designated across a topography. For example, in an embodiment in which a stepped surface is formed, each thickness increment of the stepped surface may not include a measurement point. In a preferred embodiment, however, at least one measurement location is designated for each thickness increment defined by the stepped surface. 
   In a preferred embodiment, the measurement locations may vary uniformly across the dielectric. In other words, the measurement locations may be evenly spaced across the semiconductor topography. In this manner, the thickness increments corresponding to each of the measurement locations may be substantially the same. As such, the thickness of each thickness increment may depend on the number measurement locations designated. For example, in an embodiment in which seven measurement locations are designated along a dielectric, each thickness increment may be approximately 14% of the total thickness of the original dielectric layer. Smaller or greater thickness increments may be used, however, depending on the intricacy of the desired concentration profile. In a preferred embodiment, each of the thickness increments may be less than approximately 20% of the total thickness of the original dielectric layer. Consequently, in an embodiment in which the thickness increments are substantially equal, the thickness increments may vary incrementally by less than approximately 20% of the thickness of the original dielectric layer. 
   In an alternative embodiment, the thickness increments may be substantially unequal. In this manner, each of the thickness increments may not have the same thickness. Embodiments with such unequal thickness increments may occur if measurement locations  20 - 32  are designated at an unequal distance from each other along sloped surface of dielectric  14  in  FIG. 2   a , for example. In another embodiment, unequal thickness increments may be obtained if stepped portions of dielectric  14  in  FIG. 2   b  are dissimilar in thickness, for example. In either embodiment, the thickness increments may range from greater than approximately 0 angstroms to the thickness of dielectric  14  prior to removing the upper portion of dielectric  14  to form the sloped or stepped surfaces. Narrower ranges of thickness increments, however, may be appropriate depending on the desired concentration profile. 
   Although  FIGS. 1-2   c  show seven measurement locations, any number of measurement locations may be used depending on the intricacy of the desired concentration profile. In particular, additional measurement locations may be included along semiconductor topography  10 . In other embodiments, less than seven measurement locations may be designated across semiconductor topography  10 . In addition or alternatively, a plurality of measurement points other than measurement locations  20 - 32  may be designated across semiconductor topography  10  as illustrated in FIG.  3 .  FIG. 3  is a top view of a wafer comprising semiconductor topography  10 . The cross sectional views of semiconductor  10  in  FIGS. 1-2   c  are taken along line A—A of FIG.  3 . In addition, the measurement locations may be designated symmetrically upon dielectric  14  as shown in  FIGS. 1-2   c . Alternatively, the measurement locations may be designated asymmetrically upon dielectric  14 . 
   In either embodiment, designating measurement locations may include identifying subsets of the plurality of measurement points designated across semiconductor topography  10 . Designating a subset of measurement points may advantageously allow variations of impurity concentrations within certain regions of the wafer to be analyzed. Examples of such subsets (i.e, subsets B, C, and D) are outlined in  FIG. 3  by dotted lines. Subset B, for example, may include a subset of points located at an equal distance from the center of the wafer. In particular, subset B may represent a plurality of measurement points designated along the outer edge of the wafer as shown in  FIG. 3. A  similar circular set of measurement points may be designated near the center of the wafer or in between the center and outer edge of the wafer as illustrated in FIG.  3 . 
   Subset C, on the other hand, may include a subset of points located along a strip of semiconductor topography  10  extending from opposite edges of the wafer. For example, subset C may represent a plurality of measurement points designated along a center strip of the wafer as shown in  FIG. 3. A  similar set of measurement points may be designated along an off-centered strip of the wafer. In contrast, subset D may include, for example, a subset of points located within a quadrant of semiconductor topography  10  as shown in FIG.  3 . In general, several regions of the wafer, including smaller and larger regions and regions of more or fewer measurement points than those referenced in subsets B, C, and D, may be designated as subsets of measurement points. Alternatively or in addition, a plurality of randomly designated points may be designated as a subset. Accordingly, the arrangement of measurement points and subsets illustrated in  FIG. 3  are shown as exemplary embodiments and are not to be construed as the only subset configurations available for use in the method described herein. 
     FIG. 4  illustrates a partial cross sectional view of semiconductor topography  10  of  FIG. 2   a  (i.e., semiconductor topography  10  with the sloped surface) subsequent to its exposure to oxidizing conditions. Such an oxidation process may form oxidized interface  34  between dielectric  14  and semiconductor substrate  12 . More specifically, such an oxidation process may oxidize portions of dielectric  14  and semiconductor substrate  12  to form oxidized interface  34 . In other embodiments, topographies including a substantially level surface as in  FIG. 1  or a stepped surface as in  FIGS. 2   b  and  2   c  may be exposed to oxidizing conditions to form an oxidized interface between dielectric  14  and semiconductor substrate  12 . Such an oxidized interface may be similar to that of oxidized interface  34  of  FIG. 4  or substantially different from oxidized interface  34 , depending on the surface configuration of dielectric  14 . 
   More specifically, the oxidation step may be adapted such that upon a bare silicon surface a certain thickness of silicon dioxide will grow. For example, in some embodiments, the oxidation step may be adapted such that upon a bare silicon surface approximately 50 angstroms of silicon dioxide will grow. In other embodiments, the oxidation step may be adapted to grow larger or smaller thicknesses of silicon dioxide, depending on the concentration of the impurity within the layer and the material of the layer being analyzed. As such, the surface configuration of the layer upon a bare silicon surface will affect the shape and size of the oxidized interface formed between the dielectric and the silicon surface. In any case, the oxidized interface generated from the topography of  FIG. 2   b  may be substantially similar to oxidized interface  34  of FIG.  4 . In contrast, the oxidized interface generated from the topographies of  FIG. 1 and 2   c  may be substantially different from oxidized interface  34  of FIG.  4 . 
   In addition, the concentration of an impurity within dielectric  14  may influence the amount of oxidation that may occur with a layer, and therefore may affect the thickness of oxidized interface  34 . For example, nitrogen generally blocks the diffusion of oxygen. In particular, the higher the concentration of nitrogen contained with a layer, the less the diffusion of oxygen through the layer during an oxidization process. Since the concentration of an impurity may vary laterally and vertically within a layer, the thickness of an oxidized interface may vary as shown in FIG.  4 . In addition, oxygen generally diffuses linearly such that the thickness of an oxidized interface may represent the amount of oxygen diffused through a layer for a given portion of that layer. Consequently, the thickness of a portion of an oxidized interface may relate to the concentration of an impurity contained within a respective portion of an overlying layer. “Respective” portions of overlying and underlying layers may refer to portions of the layers laterally bounded and directly aligned with each other. 
   As such, a high concentration of nitrogen contained within a portion of dielectric  14  may produce an oxidized interface with a smaller thickness than an oxidized interface produced by oxidizing a portion of dielectric  14  containing a low concentration of nitrogen. Consequently, the concentration of an impurity at a particular measurement location within dielectric  14  may be determined by calculating the thickness delta of total dielectric residing above semiconductor substrate  12  from before exposing semiconductor topography  10  to oxidizing conditions to after exposing semiconductor topography  10  to oxidizing conditions. The reference of total dielectric residing above semiconductor  12  preferably includes that of oxidized interface  34  and dielectric  14 . 
   A flow chart of the method described herein is illustrated in FIG.  5 . In particular, the method may include step  40 , which includes measuring the thickness of a layer at one or more measurement locations. Such a step may be conducted after designating measurement locations and/or removing an upper portion of the layer as described in  FIGS. 1-3 . The thickness of the layer may be prepared in a variety of manners known in the semiconductor fabrication industry. For example, the thickness of the layer may be determined by standard optical techniques, such as ellipsometry. The method may further include step  42 , which involves exposing the semiconductor topography comprising the layer to oxidizing conditions. More specifically, step  42  includes exposing the layer and underlying substrate to oxidizing conditions. The method may further include step  44  for measuring the thickness of the layer and oxidized portions of the layer and underlying semiconductor substrate at each of the measurement locations after exposing the semiconductor topography to oxidizing conditions. In a preferred embodiment, the thickness of the layer and oxidized portions of the layer and underlying semiconductor substrate may be measured by the same method as used for measuring the thickness of the layer prior to oxidation. In yet other embodiments, different thickness measurements techniques may be used for steps  40  and  44 . In either case, the thicknesses of the layer prior to the oxidation step and the total dielectric residing above the semiconductor substrate subsequent to the oxidation step may be compared to determine a concentration and/or a concentration profile of an impurity in the layer as indicated in step  46 . 
   As stated above, the thickness delta of the dielectric residing above a semiconductor substrate may be correlated to a concentration of an impurity in layer arranged above the substrate. As such, the step of comparing the thickness measurements of the layer and the oxidized interface may include determining a difference or thickness delta between such thickness measurements. In such an embodiment, correlating the thickness delta to an impurity concentration may include comparing the difference in thickness measurements to calibration data. The calibration data may be prepared in a variety of manners known in the semiconductor fabrication industry. For example, the calibration data may be contrived from SIMS analysis of a plurality of samples with known impurity concentrations. In addition, the calibration data may be representative of particular deposition techniques. For instance, different calibration data may be needed to differentiate between Rapid Thermal Oxidation (RTO) deposited nitrogen oxides and furnace grown nitrided oxides. 
   Upon correlating the thickness delta of each measurement location, a concentration profile of the impurity within the layer may be determined. Such a formation of a concentration profile may involve subtracting the impurity concentration of a measurement location corresponding to a lower thickness increment from the impurity concentration of the measurement location corresponding to the thickness increment being calculated. For example, in the embodiment of  FIG. 2   b , the impurity concentration within thickness increment  31   c  may be calculated by subtracting the correlated impurity concentration of measurement location  26  from the correlated impurity concentration of measurement location  24 . More specifically, in an embodiment in which, the correlated impurity concentration of measurement location  26  is approximately 125.72×10 13  cm −3  and the correlated impurity concentration of measurement location  28  is approximately 68.36×10 13  cm −3 , thickness increment  31   d  may include an impurity concentration of approximately 57.36×10 13  cm −3 . 
   Preferably, the calculated impurity concentration corresponding to each of the thickness increments may be plotted to show the distribution of the impurity within the layer. An example of such a concentration profile is illustrated in  FIG. 6  using the data of Table 1 below. Table 1 includes a first column detailing the amount of dielectric removed respective to an original upper surface of the dielectric. The second column of Table 1 outlines the thickness of the dielectric subsequent to the removal of upper portions of the dielectric, but prior to the oxidation process. As shown in Table 1, the original thickness of the dielectric is approximately 32 angstroms and thickness increments of approximately 5 angstroms are designated through the layer. Larger or smaller thickness increments and layers, however, may be used for the method described herein. The third column of Table 1 lists the thickness of total dielectric residing above the substrate after the oxidation process, while the fourth column yields the thickness delta between the values of the second and third columns. The last two columns list the impurity concentration relative to the calculated thickness delta of the fourth column and the impurity concentration corresponding to the respective thickness increment, respectively. 
   
     
       
         
             
             
             
             
             
             
           
             
               TABLE 1 
             
             
                 
             
             
                 
                 
               Thickness 
                 
                 
               Impurity 
             
             
               Amount 
                 
               of 
                 
                 
               Concen- 
             
             
               of 
               Thickness 
               Dielectric 
                 
                 
               tration 
             
             
               Dielectric 
               of 
               above the 
                 
                 
               within 
             
             
               Removed 
               Dielectric 
               Substrate 
                 
                 
               Respective 
             
             
               Prior to 
               Prior to 
               after 
               Thickness 
               Impurity 
               Thickness 
             
             
               Oxidation 
               Oxidation 
               Oxidation 
               Delta 
               Concen- 
               Increment 
             
             
               (Ang- 
               (Ang- 
               (Ang- 
               (Ang- 
               tration 
               (10 13   
             
             
               stroms) 
               stroms) 
               stroms) 
               stroms) 
               (10 13  cm −3 ) 
               cm −3 ) 
             
             
                 
             
           
          
             
                 
             
          
         
         
             
             
             
             
             
             
          
             
               0 
               32 
               35 
               3 
               171.61 
               0.00 
             
             
               5 
               27 
               30 
               3 
               171.61 
               11.47 
             
             
               10 
               22 
               28 
               6 
               160.14 
               34.42 
             
             
               15 
               17 
               32 
               15 
               125.72 
               57.36 
             
             
               20 
               12 
               42 
               30 
               68.36 
               45.89 
             
             
               25 
               7 
               49 
               42 
               22.47 
               21.03 
             
             
               30 
               2 
               49.5 
               47.5 
               1.44 
               1.44 
             
             
                 
             
          
         
       
     
   
   The plot of  FIG. 6  illustrates the impurity concentration of a plurality of thickness increments within a layer. As such, the plot of  FIG. 6  illustrates a depth concentration profile of a layer. Consequently, regions of the layer having relatively high or low impurity concentrations may be determined. As shown in  FIG. 6 , the plot includes the impurity concentrations within respective thickness increments of a dielectric as listed in the last column of Table 1 versus the amount of dielectric removed prior to oxidation as listed in the first column of Table 1. More specifically, the plot of  FIG. 6  may include values listed in the last column of Table 1 along the y-axis of the graph and the values listed in the first column of Table 1 along the x-axis of the graph. In this manner, the plot illustrates, from left to right, the impurity concentration of each thickness increment of the layer starting with the uppermost thickness increment and ending with the lowermost thickness increment. 
   In an alternative embodiment, the depth concentration profile may include plotting the values listed in the last column of Table 1 versus the values listed in the second column of Table 1. In such an embodiment, the plot may illustrate, from left to right, the impurity concentration of each thickness increment of the layer starting with the lowermost thickness increment and ending with the uppermost thickness increment. In yet another embodiment, a depth concentration profile may be formed by plotting the values listed in the fifth column of Table 1 versus either the first or second column of Table 1. Such a plot may illustrate the impurity concentrations within the layer relative to the layer&#39;s thickness at given measurement locations. Consequently, the regions within the thickness of the layer having relatively high or low impurity concentrations may be determined by comparing relative increases or decreases in the plot. 
   As shown in the embodiment in  FIG. 6 , the highest concentration of the impurity within the dielectric layer is located approximately 15 angstroms from the original upper surface of the dielectric layer. In addition, the upper and lower most surfaces of the dielectric layer include little or no concentration of the impurity. Such a configuration profile may be indicative of a Rapid Thermal Oxidation (RTO) deposited nitrogen oxide, in an embodiment in which the impurity includes nitrogen. It is noted that  FIG. 6  is merely illustrated an example concentration profile. Several other concentration profiles may exist depending on the deposition process parameters and the impurities contained within the dielectric layer. For example, a concentration profile which may be indicative of a furnace grown nitrided oxide may include a high concentration of nitrogen near the lowermost surface of the dielectric and a substantially lower, but constant impurity concentration in the upper half of the dielectric. 
   Other concentration profiles may be plotted using the information obtained from the method described herein as well. For example, a lateral concentration profile of an impurity within a layer may be plotted using the method described herein. More specifically, a concentration profile may be formed which outlines the concentration of an impurity relative to lateral positions within a layer rather than depth localities within the layer. For example, rather than plotting the amount of the layer removed prior to the oxidation of the layer or the thickness of the layer at given measurement locations, the lateral position of the measurement locations along the layer may be plotted versus impurity concentrations of the layer. More specifically, the lateral position of measurement locations relative to a specific location on the semiconductor topography may be plotted. For example, the lateral position of measurement locations relative to one side of the semiconductor topography may be plotted. In other embodiments, the lateral position of measurement locations relative to the center of the semiconductor topography may be plotted. In general, any location upon the semiconductor topography may be used as a specific location for referencing the lateral positions of the measurement locations. 
   In any case, such a plot may illustrate an impurity concentration profile across a layer. In some embodiments, the plot may illustrate an impurity concentration profile across and at a specific depth of the layer. In such an embodiment, the layer may be substantially planar prior to the oxidation step such that the measurement locations have substantially similar thicknesses. In yet other embodiments, the plot may illustrate a lateral concentration profile of impurities at varying depths of the layer. In such an embodiment, the layer may be substantially nonplanar prior to the oxidation step such that the measurement locations have substantially different thicknesses. In addition, in some cases, the plot illustrating a lateral concentration profile of impurities at varying depths of the layer may include an additional x-axis parameter which is characteristic of the depth of the layer. More specifically, the x-axis of the plot may include the values listed, for example, in the first or second columns of Table 1, as well as the lateral position of the measurement locations across a layer versus the concentration of the impurities at such locations. Consequently, such a plot may illustrate both a lateral and depth concentration profile of an impurity within the layer. Such a plot may be particularly advantageous in an embodiment in which a layer is formed having a symmetrical surface configuration about the center of the layer as shown in  FIG. 2   c , for example. Other surface configurations, including symmetrical and asymmetrical configurations, however, may also be used for such lateral and depth concentration profiles. 
   In some embodiments, the step of comparing the thickness measurements of the layer taken prior to the oxidation step to the thickness measurements of the oxidized interface taken subsequent to the oxidation step to determine a concentration profile of an impurity within the layer may include plotting such thickness measurements versus each other. In particular, step  46  of  FIG. 5  may include plotting the thickness measurements of the layer prior to the oxidation step versus the thickness measurements of the oxidized interface taken subsequent to the oxidation step. An exemplary embodiment of such a plot is illustrated in FIG.  7 . In particular,  FIG. 7  illustrates the thickness of dielectric prior to oxidation as listed in the second column of Table 1 versus the thickness of total dielectric above a substrate after oxidation as listed in the third column of Table 1. More specifically, the plot of  FIG. 7  includes values listed in the third column of Table 1 along the y-axis of the graph and the values listed in the second column of Table 1 along the x-axis of the graph. Consequently, a concentration profile of an impurity within the layer is produced. 
   In particular,  FIG. 7  illustrates an impurity concentration profile which illustrates very little or no impurity concentration along the lowermost surface of the layer as indicated by the post-oxidation thickness of approximately 50 angstroms at a pre-oxidation thickness of approximately 2 angstroms. As stated above, the oxidation step may be adapted such that approximately 50 angstroms of silicon dioxide will grow upon a bare silicon surface. As such, the post-oxidation measurement of approximately 50 angstroms upon a substrate having a pre-oxidation measurement of approximately 2 angstroms indicates very little retardation of the oxidation process at such a thickness of the layer. A slightly higher impurity concentration is shown for the region of the layer extending approximately 7 angstroms for the lowermost surface of the layer. In particular,  FIG. 7  illustrates a post-oxidation thickness of approximately 50 angstroms plotted versus a pre-oxidation thickness of approximately  7  angstroms, indicating a low impurity concentration within such a region of the layer. 
   On the contrary, the large decreases of the plot shown for the regions of the layer extending approximately 12 and 17 angstroms from the lowermost surface of the layer indicate larger concentrations of the impurity within the layer at such regions. In particular, the large decreases between pre-oxidation thicknesses of approximately 7 angstroms and approximately 12 angstroms and pre-oxidation thicknesses of approximately 12 angstroms and approximately 17 angstroms indicate a significant increase in retardation of the oxidation process relative to the other measurement locations of the layer. In fact, the change between pre-oxidation thicknesses of approximately 12 angstroms and approximately 17 angstroms is the largest within the graph, indicating the highest concentration of the impurity within the layer is located approximately 17 angstroms from the lowermost surface of the layer. The slight decrease and increases in post oxidation measurements corresponding to the pre-oxidation thickness measurements greater than approximately 22 angstroms indicates a progressive decrease in the impurity concentration at those respective regions of the layer. 
   It is noted that the values included in Table 1 and the graphs of  FIGS. 6 and 7  are exemplary. In particular, the method described herein is not restricted to the embodiments described in reference to Table 1 and the graphs of  FIGS. 6 and 7 . For example, the pre-oxidation and post-oxidation measurements and/or the impurity concentrations may be larger or smaller than those described herein. In addition, depths at which impurity concentrations are determined may differ from those described herein. Furthermore, the values listed in Table 1 and the graphs of  FIGS. 6 and 7  indicate an impurity which retards oxidation. However, the method described herein may additionally or alternatively be used for impurities which enhance oxidation. 
   It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to provide a method and a system for processing a semiconductor topography. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. For example, the method described herein could be used to determine the concentration or concentration profile of a variety of impurities, which impact the growth of oxidation. Furthermore, any number of measurement locations and thickness increments may be designated for a given topography depending on the intricacy of the desired concentration profile. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the drawings and the specification are to be regarded in an illustrative rather than a restrictive sense.