Patent Publication Number: US-7709908-B2

Title: High-voltage MOS transistor device

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to a high-voltage MOS transistor device, and particularly, to a high-voltage MOS transistor device having a plurality of first field plate rings. A voltage is applied upon the first field plate rings to maintain a constant electric field within the high-voltage MOS transistor device and prevent breakdown of the high-voltage MOS transistor device. 
   2. Description of the Prior Art 
   Current power systems provide an alternating current having a variety of frequencies ranging from 50 to 60 Hz, and a voltage ranging from 100 to 240 volts (V). Every electrical device has a particular working voltage and frequency condition, and therefore, electrical devices and related passive elements utilized in the electrical devices, such as inductors, capacitors, resistors and transformers, act as a switch to determine the value of the voltage and the type of the current thereof. For example, a conventional air conditioner utilizes a power supply providing a low-voltage current for the inner facilities. The power supply switch reduces the voltage provided by the outer power system to an appropriate voltage for the inner facilities. In addition, the power supply switch has the characteristics of high efficiency, low weight, small size and reduced power consumption. 
   High-voltage metal-oxide semiconductors may function as switches and are broadly utilized in CPU power supplies, power management systems, AC/DC converters, LCD/plasma TV drivers, automobile electronic components, PC peripheral devices, small DC motor controllers, and other consumer electronic devices. The power source supplied by the outer voltage source is an AC power. The usual waveform of an AC power circuit is a sine wave, and a 240V AC power may alter its voltage from −300V to +300V. The voltage may over 600V in an instant. This is greater than the breakdown voltage of most HV MOS transistor devices in the field and leads to HV MOS transistor device damage. Therefore, an HV MOS transistor device capable of withstanding high-voltages is required. 
   SUMMARY OF THE INVENTION 
   The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. 
   The present invention relates to a high-voltage MOS transistor device having a plurality of field plate rings, and particularly to a high-voltage MOS transistor device capable of preventing breakdown by applying a bias to one of the field plate ring thereof. 
   Therefore, a high-voltage MOS transistor device is provided. The high-voltage MOS transistor device has a substrate of a first conductive type, a source of a second conductive type, a drain of the second conductive type, at least a second doped region, and a third ion well disposed around the second doped region. Furthermore, the high-voltage MOS transistor device has an isolation structure positioned on a part of the third ion well, and a gate dielectric layer disposed on a surface of the substrate between the source and the isolation structure. The high-voltage MOS transistor also has a first dielectric layer covering the gate, the doped regions, and the isolation structure. In addition, a plurality of first field plate and a first conductive layer disposed across the first field plate rings are positioned on the first dielectric layer. The first conductive layer has a first end electrically connected to the drain, a second end electrically connected to at least one of the first field plate rings, and a third end electrically connected to a pad. 
   The present invention utilizes the electrical connection between the first conductive layer, the drain, and the first field plate rings to induce a corresponding electrode field to decrease the electrical field nearby the interface between the first doped region and the third ion well, which is positioned next to the drain. The minimum breakdown voltage of the high MOS transistor device of the present invention is about 700V. Therefore, the high-voltage MOS transistor device of the present invention has a better voltage capability than prior art HV MOS transistor devices. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  and  FIG. 2  are schematic diagrams of a high-voltage MOS transistor device according to a first embodiment of the present invention. 
       FIG. 3  shows another high-voltage MOS transistor device according to a second embodiment of the present invention. 
       FIG. 4  further shows a high-voltage MOS transistor device according to a third embodiment of the present invention. 
       FIG. 5  and  FIG. 6  are schematic diagrams of a high-voltage MOS transistor device according to a fourth embodiment of the present invention. 
       FIG. 7  is an electrical field-voltage plot of the high-voltage MOS transistor device of the present invention. 
   

   DETAILED DESCRIPTION 
   Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, in which components with substantially the same functions are identified by the same reference numeral for the sake of simplicity. The following description of the present invention will focus on a high-voltage MOS transistor device with a high breakdown voltage of at least 700V. It should be noted, however, that the present invention is in no way limited to the following illustrative embodiments. 
   A high-voltage MOS transistor device according to a first embodiment of the present invention will be described with reference to  FIG. 1  and  FIG. 2 .  FIG. 1  shows a cross-section diagram of the high-voltage MOS transistor device of the present invention.  FIG. 2  shows a top view of the high-voltage MOS transistor device of the present invention, where the region between A and A′ in  FIG. 1  corresponds to the region between A and A′ in  FIG. 2 . The high-voltage MOS transistor device  100  is formed on a substrate  40 , such as a P doped silicon substrate, and the active area of the high-voltage MOS transistor device  100  is isolated by at least an isolation structure, such as a field oxide layer  42 , or at least a shallow trench isolation (not shown). The high-voltage MOS transistor device  100  has a source  44 , a gate  46 , and a drain  48 . The source  44  is a heavily N doped region and positioned next to a first heavily P doped region  50 . Both the source  44  and the first heavily P doped region  50  are formed in a first P ion well  52 . Next to the first P ion well  52  is a high-voltage P doped well  53 . The drain  48  is a heavily N doped region and is formed within a second N ion well  54 , which is formed within a third deep N well  56 , forming a triple-well structure. As shown in  FIG. 1 , another isolation structure is disposed on a part of the third deep N well  56  and next to the second N well  54 . The isolation structure may be a field oxide  58  or at least an STI (not shown). Moreover, at least a second P doped region  60  is formed under the field oxide  58 , and positioned between the first P ion well  52  and the second N ion well  54 . For the sake of simplicity, only one second P doped region  60  is shown in  FIG. 1 . The high-voltage MOS transistor device  100  of the present invention may have more than one second P doped region  60 . The number of the second P doped region  60  is adaptable depending on the requirement. The high-voltage MOS transistor device  100  further has a gate dielectric layer  62  formed on a surface of the substrate  40  between the source  44  and the field oxide  58 . Therefore, the gate  46  of the high-voltage MOS transistor device  1   00  is disposed on the gate dielectric layer  62  and extended to approach the field oxide  58 . The high-voltage MOS transistor device  100  also has a first dielectric layer  64  covering the gate  46 , the doped regions, the ion wells and the field oxide  58 . 
   As shown in  FIG. 1 , PN junctions are formed between the second P doped region  60  and the third deep N well  60 . When the high-voltage MOS transistor device  100  is working, the distribution of the electrical field at the PN junctions nearing the source  44  and the drain  48  are intensive, especially the PN junction positioned next to the drain  48 . This results in breakdown of the high-voltage MOS transistor device  100 . In order to prevent the high-voltage MOS transistor device  100  from breakdown, the high-voltage MOS transistor device  100  of the present invention further has a plurality of first field plate rings and a first conductive layer  68  disposed on the first dielectric layer  64 . Please refer to  FIG. 1  and  FIG. 2  together.  FIG. 2  shows a vertical view of the high-voltage MOS transistor device  100 . For the sake of simplicity, five field plate rings  70   a,    70   b,    70   c,    70   d,  and  70   e  are shown in the present embodiment. The field plate rings  70   a - e  all have the same critical dimension and are positioned as concentric circles. The critical dimension of the field plate rings  70   a - e,  the interval between each field plate rings  70   a - e,  and the quantities of the field plate rings  70   a - e  may be modified as required. As shown in  FIG. 2 , the first conductive layer  68  has at least three ends electrically connected to other components of the high-voltage MOS transistor device  100  or peripheral electronic facilities thereof. The first field plate  68  has a first end  76  electrically connected to the drain  48 , a second end  78  electrically connected to the first field plate ring  70   d,  and a third end  82  electrically connected to a pad  80 . The second end  78  connected to the first field plate  70   d  is positioned above the PN junction between the third N ion well  56  and the second P doped region  60  next to the source  44 . Except for the first field plate ring  70   d  connected to the first conductive layer  60 , the field plate rings  70   a,    70   b,    70   c,  and  70   e  are floating rings. 
   As can be seen from  FIG. 1  and  FIG. 2 , the first conductive layer  68  applies a voltage from the drain  48  through a first via plug  84 , the first end  76 , and the second end  78  to the first field plate ring  70   d.  The voltage may induce an electrical field to decrease the electrical field at the PN junction next to the source  44  and the PN junction next to the drain  48  through a coupling effect. As a result, a breakdown effect is prevented. 
   A second embodiment of the present disclosure is illustrated in conjunction with  FIG. 3 .  FIG. 3  shows another high-voltage transistor device  200  according to a second embodiment of the present invention. Components with substantially the same functions as those of the high-voltage MOS transistor  100  are identified by the same reference numeral for the sake of simplicity. These components are numbered as those of the high-voltage transistor device  100 . As shown in  FIG. 3 , the high-voltage transistor device  200  has a plurality of second field plate rings  86   a,    86   b,    86   c,  and  86   d  disposed between the first field plate rings  70   a - e  and the field oxide  58 . The preferred material of the second field plate rings  86   a - d  comprises polysilicon or other materials having similar electrical properties as polysilicon. The second field plate rings  86   a - d  are respectively positioned between each of the field plate rings  70   a - e.  In addition to the mechanism illustrated in the first embodiment, the high-voltage MOS transistor device  200  may utilize other mechanisms to decrease the electrical field at the PN junction nearing the drain  48  and the source  44 . For instance, another voltage may be applied to one of the second field plate rings  86   a - d  directly to induce its corresponding electrical field in order to decrease the electrical field near the PN junction next to the source  44  and the PN junction next the drain  48 . 
     FIG. 4  is a schematic diagram of a high-voltage MOS transistor device  300  according to a third embodiment of the present invention. Components with substantially the same functions as those of the first embodiment or the second embodiment are identified by the same reference numeral for the sake of simplicity. In addition to the second plate rings  86   a - d,  the high-voltage MOS transistor device  300  additionally has a second dielectric layer  88  and a plurality of third field plate rings  90   a,    90   b,    90   c,    90   d,  and  90   e  disposed on the second dielectric layer  88 . The preferred material of the third field plate rings  90   a - e  may include metal or other conductive materials. The third field plate rings  90   a - e  are respectively positioned between each of the first field plate rings  70   a - e.  When the high-voltage MOS transistor device  300  is working, a voltage may be applied directly to the third field plate rings  90   a - e  and form a corresponding electrical field coupled to the first field plate rings  70   a - e  or the second field plate rings  86   a - d.  This is to ensure that the electrical field that lies near the PN junctions between the third N ion well  56  and the second P doped region  60  approaching to the source  44  and the drain  48  will be decreased. 
   Based on the spirit of the present invention, a fourth embodiment is disclosed with reference to  FIG. 5  and  FIG. 6 , which are schematic diagrams of a plurality of first field plate rings  96   a,    96   b,    96   c,    96   d,    96   e  and a first conductive layer  94  of a high-voltage MOS transistor device. Other components of the high-voltage MOS transistor devices are the same as the prior embodiments. The field plate rings  96   a - e  are floating field plate rings. At least one of the floating field plate rings, such as the first field plate ring  96   d  in  FIG. 6 , is electrically connected to a first power supply  104 . Therefore, a voltage from the first power supply  104  is applied to the first field plate ring  96   d  to decrease the electrical field near the PN junction next to the drain (not shown) and the PN junction next to the source (not shown). The value of the voltage may be equal to or less than that of the drain. Additionally, each of the floating first field plate rings  96   a - e  may be connected to a respective power supply. As shown in  FIG. 6 , the first field plate ring  96   a  is electrically connected to a second power supply  106 , and the first field plate ring  96   b  is electrically connected to a third power supply  108 . The first field plate ring  96   c  is electrically connected to a fourth power supply  110 , and the first field plate ring  96   d  is electrically connected to the first power supply  104 . Furthermore, the first field plate ring  96   e  is electrically connected to a fifth power supply  112 . The value of the voltage provided by the power supplies may be modified as a proper value for the high-voltage MOS transistor. 
     FIG. 7  shows an electrical field (E)-potential (V) plot of the high-voltage MOS transistor device. According to the prior embodiments, the high-voltage MOS transistors utilize the first conductive layer to apply a voltage to at least one of the first field plate rings and decrease the electrical field at the PN junction next to the drain or the source through coupling. Therefore, the high-voltage MOS transistor device has a constant electrical field. The voltage distribution of the high-voltage MOS transistor device decreases gradually from the drain to the source. Therefore, when the high-voltage MOS transistor is utilized as a component of the power supply system, the high-voltage MOS transistor is capable of reducing the incoming voltage to a working voltage of the internal electrical system. 
   According to the above-mentioned embodiments, the high-voltage MOS transistor device of the present invention connects the first conductive layer and at least one of the first field plate rings to maintain a constant electrical field inside the high-voltage MOS transistor device. Additionally, the high-voltage MOS transistor device of the present invention may have two or more connecting ends between the first field plate rings and the first conductive layer. These connecting ends may be separate or positioned next to each other. Locating the first field plate rings and the first conductive layer on different planes is also allowable. If the first field plate rings and the first conductive layer are positioned on different planes, a second via plug may be utilized to connect the first conductive layer and the field plate rings electrically. Furthermore, each of the above-mentioned embodiments applies a voltage to the first field plate as an example. The voltage may be applied to the second field plate rings or the third field plate rings and has the same effect as being applied to the first field plate. Moreover, the shape of the field plate rings, although illustrated as concentric circles in the embodiments, may be rectangular rings, or polygonal rings that have the same function. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.