Patent Publication Number: US-6987416-B2

Title: Low-voltage curvature-compensated bandgap reference

Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to a voltage reference circuit with low sensitivity to temperature, and more specifically, to a low-voltage bandgap reference circuit. 
   2. Description of the Prior Art 
   Reference voltage generators are widely used in both analog and digital circuits such as DRAM and flash memories. A bandgap reference (also termed BGR) is a circuit that provides a stable output voltage with low sensitivity to temperature and supply voltage. 
   A conventional bandgap reference output is about 1.25 V, which is almost equal to the silicon energy gap measured in electron volts. However, in modern deep-submicron technology, a voltage of around 1 V is preferred. As such, the conventional bandgap reference is inadequate for current requirements. 
   The 1 V minimum supply voltage is constrained by two factors. First, the reference voltage of about 1.25 V exceeds 1 V. Second, low voltage design of proportional to-absolute-temperature (PTAT) current generation loops is limited by the input common-mode voltage of the amplifier. The effects of these constraints can be reduced by resistive subdivision methods and by using low threshold voltage devices or BiCMOS processes. However, both of these solutions require costly special process technology. 
   Bandgap references can be divided into two groups: type-A and type-B. Type-A bandgap references sum voltages of two elements having opposite temperature components. Type-B bandgap references combine the currents of two elements. Both type A and type B bandgap references can be designed to function with a normal supply voltage of greater than 1 V and a sub-1-V supply voltage. 
     FIG. 1  illustrates a conventional type-A bandgap reference circuit  10 . The bandgap reference circuit  10  includes an operational amplifier  12 , two transistors M 1  and M 2 , two resistors R 1  and R 2 , and two diodes Q 1  and Q 2 . The sources of the transistors M 1 , M 2  are connected to a supply voltage V DD . The drain of the transistor M 1  is connected to the emitter of the diode Q 1  through the resistor R 1  and to the positive input of the amplifier  12 . Similarly, the drain of the transistor M 2  is connected to the emitter of the diode Q 2  through the resistor R 2  and to the negative input of the amplifier  12 . The gates of the transistors M 1 , M 2  are connected to the output of the amplifier  12 . In CMOS applications, each diode Q 1 , Q 2  is formed with a parasitic vertical bipolar transistor having a collector and base connected to ground. 
   Neglecting base current, the emitter-base voltage of a forward active operation diode can be expressed as: 
               V   EB     =         k   ⁢           ⁢   T     q     ⁢     ln   ⁡     (       I   C       I   S       )                 (   1   )             
 
where:
 
   k is Boltzmanns constant (1.38×10 −23  J/K), 
   q is the electronic charge (1.6×10 −19  C), 
   T is temperature, 
   I C  is the collector current, and 
   I S  is the saturation current. 
   When the input voltages of the amplifier  12  are forced to be the same, and the size of the diode Q 1  is N times that of the diode Q 2 , the emitter-base voltage difference between diodes Q 1  and Q 2 , ΔV EB , becomes: 
               Δ   ⁢           ⁢     V   EB       =         V   EB2     -     V   EB1       =         k   ⁢           ⁢   T     q     ⁢   ln   ⁢           ⁢   N               (   2   )             
 
where:
 
   V EB1  is the emitter-base voltage of diode Q 1 , and 
   V EB2  is the emitter-base voltage of diode Q 2 . 
   Finally, when the current through resistor R 1  is equal to the current through resistor R 2  and is set to be PTAT, an output reference voltage, V REF , can be obtained by: 
               V   REF     =         V   EB2     +         R   2       R   1       ⁢   Δ   ⁢           ⁢     V   EB         ≡     V     REF   ⁢     -     ⁢   CONV                 (   3   )             
 
where:
 
   R 1  is the resistance of resistor R 1 , 
   R 2  is the resistance of resistor R 2 , and 
   V REF-CONV  is the reference voltage (conventional). 
   The emitter-base voltage, V EB , has a negative temperature coefficient of −2 mV/° C., while the emitter-base voltage difference, ΔV EB , has a positive temperature coefficient of 0.085 mV/° C. Hence, if a proper ratio of resistances of resistors R 1  and R 2  is selected, the output reference voltage, V REF , will have low sensitivity to temperature. In general, the supply voltage, V DD , is set to about 3–5 V and the output reference voltage, V REF , is about 1.25 V, as the conventional bandgap circuit  10  cannot be used at a lower voltage such as 1 V. 
     FIG. 2  illustrates a conventional type-B bandgap reference circuit  20 . Elements in  FIG. 2  having the same reference numbers of those in  FIG. 1  are the same. The bandgap reference circuit  20  includes an operational amplifier  22 ; three transistors M 1 , M 2 , and M 3 ; four resistors R 1 , R 2 , R 3 , and R 4 ; and two diodes Q 1  and Q 2  interconnected as illustrated in  FIG. 2 . 
   Compared with the type-A circuit  10 , the type-B circuit  20  is more suitable for operating with a low supply voltage. Instead of stacking two complementary voltages, the type-B bandgap reference  20  adds two currents with opposite temperature dependencies. In the bandgap reference of  FIG. 2 , the current through the resistor R 3  is PTAT. If the resistances of the resistors R 1  and R 2  are equal, then the current through the MOS transistor M 3  mirrored from transistors M 1  and M 2  can be expressed as: 
               I   M3     =       1     R   1       ⁢     (       V   EB2     +         R   1       R   3       ⁢       k   ⁢           ⁢   T     q     ⁢   ln   ⁢           ⁢   N       )               (   4   )             
 
with the reference voltage being expressed as: 
               V   REF     =           R   4       R   1       ⁢     (       V   EB2     +         R   1       R   3       ⁢       k   ⁢           ⁢   T     q     ⁢   ln   ⁢           ⁢   N       )       =         R   4       R   1       ·     V     REF   ⁢     -     ⁢   CONV                   (   5   )             
 
   Thus, in the bandgap reference circuit  20  of  FIG. 2 , as ratios of resistances are key, the variations in individual resistances due to process conditions does not greatly affect the reference voltage. In general, the supply voltage, V DD , is set to about 1.5 V and the output reference voltage, V REF , is about 1.2 V. 
     FIG. 3  illustrates a conventional type-B bandgap reference circuit  30  capable of sub-1-V operation. Elements in  FIG. 3  having the same reference numbers of those in  FIG. 2  are the same. The bandgap reference circuit  30  includes an operational amplifier  32 ; three transistors M 1 , M 2 , and M 3 ; six resistors R 1   a , R 1   b , R 2   a , R 2   b , R 3 , and R 4 ; and two diodes Q 1  and Q 2  interconnected as illustrated in  FIG. 3 . The supply voltage is limited by the input common-mode voltage of the amplifier  32 , which must be low enough to ensure that the input pair operate in the saturation region. 
   The improvement of low supply voltage realized with the bandgap reference circuit  30  is based on the positions of the input pair of the operational amplifier  32 . The established feedback loop produces a PTAT voltage across the resistor R 3 . The resistance ratio of the resistors R 1   a  and R 2   a  causes the voltage between the supply voltage and the input common voltage of the operational amplifier  32  to become increased. This makes the p-channel input pair operate in the saturation region even when the supply voltage is under 1V. The sub-1-V reference voltage output by the circuit  30  can be expressed as: 
               V     REF   ⁢     -     ⁢   SUB1F       =           R   4       R   1       ⁢     (       V   EB2     +         R   1       R   3       ⁢       k   ⁢           ⁢   T     q     ⁢   ln   ⁢           ⁢   N       )       =         R   4       R   1       ·     V     REF   ⁢     -     ⁢   CONV                   (   6   )             
 
which is similar to the circuit  20  of  FIG. 2 . During operation of the circuit  30 , the supply voltage, V DD , is set to about 1.0–1.9 V and the output reference voltage, V REF , is about 0.6 V.
 
   Given the state-of-the-art bandgap reference circuits  10 ,  20 , and  30  described above, it is clear that an improved and inexpensive low-voltage bandgap reference circuit is required. 
   SUMMARY OF INVENTION 
   It is therefore a primary objective of the claimed invention to provide a low-voltage curvature-compensated bandgap reference circuit having low sensitively to temperature. 
   Briefly summarized, the claimed invention includes a first bandgap reference unit having an output connected to a first node, a second bandgap reference unit having an output connected to a second node, and a subtractor connecting the first and second bandgap reference units at the first and second nodes. The subtractor comprises a first transistor having a source connected to a first voltage, and a drain and a gate both connected to the second node; a second transistor having a source connected to the first voltage, a drain connected to a third node, and a gate connected to the gate of the first transistor; a third transistor having a source connected to a second voltage, and a drain and a gate both connected to the first node; a fourth transistor having a source connected to the second voltage, a drain connected to the third node, and a gate connected to the gate of the third transistor; and an output resistor connected between the third node and to the second voltage. 
   It is an advantage of the claimed invention that a temperature insensitive reference voltage of less than 1 volt can be obtained at the third node when the first and second voltages are set appropriately. 
   It is a further advantage of the claimed invention that the bandgap reference circuit is compatible with established CMOS technology. 
   It is a further advantage of the claimed invention that no low-threshold voltage or BiCMOS devices are required. 
   These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a circuit diagram of a conventional bandgap reference. 
       FIG. 2  is a circuit diagram of a conventional low-voltage bandgap reference. 
       FIG. 3  is a circuit diagram of a conventional low-voltage bandgap reference. 
       FIG. 4  is a graph of base-emitter voltage versus temperature of two diodes of a bandgap reference. 
       FIG. 5  is a graph of the difference of the diode base-emitter voltages of  FIG. 4  versus temperature. 
       FIG. 6  is a graph of a family of output reference voltage curves. 
       FIG. 7  is a circuit diagram of a low-voltage curvature-compensated bandgap reference circuit according to a first embodiment. 
       FIG. 8  is a graph of the currents and a reference voltage of the circuit of  FIG. 7 . 
       FIG. 9  is a schematic diagram of a parasitic vertical NPN CMOS BJT. 
       FIG. 10  is a circuit diagram of a low-voltage curvature-compensated bandgap reference circuit according to a second embodiment. 
       FIG. 11  is a circuit diagram of a low-voltage curvature-compensated bandgap reference circuit according to a third embodiment. 
       FIG. 12  is a graph of reference voltage versus temperature for the bandgap reference of  FIG. 11 . 
       FIG. 13  is a graph of minimum supply voltage for the bandgap reference of  FIG. 11 . 
   

   DETAILED DESCRIPTION 
   As a basis for the explaining the present invention, please refer to  FIG. 4  and  FIG. 5 .  FIG. 4  illustrates base-emitter voltage of two diodes Q 1 , Q 2  (discussed later) with respect to temperature.  FIG. 5  illustrates the difference of the diode base-emitter voltages with respect to temperature. It can be seen that the base-emitter voltage, V EB , has a negative temperature coefficient of about −2 mV/° C. with V EB =0.55 V and T=300 K. The difference of the diode base-emitter voltages, ΔV EB , with respect to temperature, as shown in  FIG. 5 , is used in the present invention to produce a PTAT to eliminate the effect of the negative temperature coefficient. 
   As a further basis, consider that the output reference voltage, V REF , of a conventional bandgap circuit is given by: 
               V   REF     =       E   G     +         V   T     ⁡     (     γ   -   α     )       ⁢     (     1   +     ln   ⁢       T   0     T         )                 (   7   )             
 
where:
 
   γ is from
 
{overscore (μ)}=CT γ−4  
 
   defining the average hole mobility in the base, 
   α is from
 
I C =GT α 
 
   E G  is the bandgap voltage of silicon, 
   T 0  is the temperature in Kelvin where the temperature coefficient of V REF  is zero, and 
   T 0  is temperature in Kelvin. 
   Neglecting the temperature dependence of the bandgap voltage of silicon, E G , and differentiating (7) once and twice with respect to temperature yields: 
                 ∂     V   REF         ∂   T       =       k   q     ⁢     (     γ   -   α     )     ⁢   ln   ⁢       T   0     T               (   8   )             
 
and 
                 ∂     ∂   T       ⁢     (       ∂     V   REF         ∂   T       )       =       -     k   q       ⁢       (     γ   -   α     )     T               (   9   )             
 
   It should be noted that the term (γ−α) in (9) controls the curvature of the V REF  curve of (7). So that if the term (γ−α) is positive then V REF  is concave down everywhere, and if the term (γ−α) is negative then V REF  is concave up everywhere. 
   Referring to  FIG. 6 , illustrating a family of concave up output reference voltage curves according to (7).  FIG. 6  shows several curves of different zero-reference-temperatures T 0  according to a simulation specifying a bandgap circuit with PNP bipolar transistors of a TSMC 0.25 μm 1P5M process, pure p-type silicon near room temperature, and γ=1.8 and α=0. 
   Please refer to  FIG. 7  illustrating a low-voltage curvature-compensated bandgap reference circuit  70  according to a first embodiment of the present invention. The bandgap reference circuit  70  is a CMOS circuit, however other implementations are certainly possible. The circuit  70  includes a first bandgap reference unit  72  having an output connected to a first node n 1 , a second bandgap reference unit  74  having an output connected to a second node n 2 , and a subtractor  76  connected between the bandgap reference  72 ,  74 . The first bandgap reference unit  72  is a p-channel device that outputs a current I 1 , and the second bandgap reference unit  74  is an n-channel device that outputs a current I 2 . 
   The subtractor  76  includes a first transistor M 4  having a source connected to a first voltage V DD  and a drain and gate both connected to the second node n 2 , and a second transistor M 5  having a source also connected to the first voltage V DD , a drain connected to a third node n 3 , and a gate connected to the gate of the first transistor M 4 . The transistors M 4  and M 5  and PNP devices. The subtractor  76  further comprises a third transistor M 6  having a source connected to ground and a drain and gate both connected to the first node n 1 , and a fourth transistor M 7  having a source connected to ground, a drain connected to the third node n 3 , and a gate connected to the gate of the third transistor M 6 . The transistors M 6  and M 7  are NPN devices. An output resistor RREF is connected between the third node n 3  and ground. 
   Please refer to  FIG. 8  illustrating the currents and reference voltage of the circuit  70  of  FIG. 7 . The currents I 1  and I 2  are both concave up and both have similar curvature when the first and second reference units  72 ,  74  are designed to have close values of T 0 . As can be seen in  FIG. 8 , a fundamental operation of the subtractor  76  is to subtract the smaller current I 1  generated by the first bandgap reference  72  from the larger current I 2  generated by the second bandgap reference  74 . The result of this operation is a temperature insensitive and curvature-compensated voltage V REF  across the resistor RREF. In addition,  FIG. 9  illustrates a schematic diagram of a parasitic vertical NPN bipolar junction transistor (BJT) made with standard CMOS processes with a deep n-well, which is one kind of device that can be used to realize the present invention. 
   Please refer to  FIG. 10  illustrating a circuit diagram of a low-voltage curvature-compensated bandgap reference circuit  100  according to a second embodiment of the present invention. The circuit  100  includes a p-channel bandgap reference unit  102  (similar to the unit  72 ) and an n-channel bandgap reference unit  104  (similar to the unit  74 ) mutually connected by the subtractor  76 . The circuit  100  can be considered as a more specific embodiment of the circuit  70 , and consequently the previous description of the circuit  70  also applies to the circuit  100 . 
   The p-channel bandgap reference unit  102  is similar to the bandgap reference circuit  20  of  FIG. 2 , and as such, components with same reference numerals are the same. The p-channel bandgap reference unit  102  includes a first operational amplifier  112 ; a fifth transistor M 1  having a source connected to the first voltage V DD , a drain connected to the positive input end of the amplifier  112 , and a gate connected to the output end of the amplifier  112 ; and a sixth transistor M 2  having a source connected to the first voltage V DD , a drain connected to the negative input end of the amplifier  112 , and a gate connected to the output end of the amplifier  112 . The circuit  102  further comprises a first resistor R 1  connected between ground and the positive input end of the amplifier  112 , a second resistor R 2  connected between ground and the negative input end of the amplifier  112 , a first diode Q 1  having a collector and base connected to ground and an emitter connected to the positive input end of the amplifier  112  through a third resistor R 3 , and a second diode Q 2  having a collector and base connected to ground and an emitter connected to the positive input end of the amplifier  112 . Finally, the circuit  102  comprises a seventh transistor M 3  having a source connected to the first voltage V DD , a gate connected to the output end of the amplifier  112 , and a drain connected to the first node n 1 . The transistors M 1 , M 2 , M 3  and the diodes Q 1 , Q 2  are PNP. 
   The n-channel bandgap reference unit  104  is similar to an n-channel version of the bandgap reference circuit  20  of  FIG. 2 . The n-channel bandgap reference unit  104  includes a second operational amplifier  114 ; an eighth transistor M 1  having a source connected to ground, a drain connected to the positive input end of the operational amplifier  114 , and a gate connected to the output end of the operational amplifier  114 ; and a ninth transistor M 2  having a source connected to ground, a drain connected to the negative input end of the amplifier  114 , and a gate connected to the output end of the amplifier  114 . The circuit  104  further comprises a fourth resistor R 1  connected between the first voltage V DD  and the positive input end of the amplifier  114 , a fifth resistor R 2  connected between the first voltage V DD  and the negative input end of the amplifier  114 , a third diode Q 1  having a collector and base connected to the first voltage V DD  and an emitter connected to the positive input end of the amplifier  114  through a sixth resistor R 3 , and a fourth diode Q 2  having a collector and base connected to the first voltage V DD , and an emitter connected to the positive input end of the amplifier  114 . Finally, the circuit  104  comprises a tenth transistor M 3  having a source connected to ground, a gate connected to the output end of the amplifier  114 , and a drain connected to the second node n 2 . The transistors M 1 , M 2 , M 3  and the diodes Q 1 , Q 2  are NPN. 
   From (4), the current produced by the p-channel bandgap reference unit  102  at the node n 1  is given by: 
               I   1     =         1     R   1       ⁢     (       V   EB2     +         R   1       R   3       ⁢       k   ⁢           ⁢   T     q     ⁢   ln   ⁢           ⁢     N   PNP         )       =       V   REF_PNP       R   1                 (   10   )             
 
where:
 
   R 1  is the resistance of the resistor R 1 , 
   R 3  is the resistance of the resistor R 3 , 
   V EB2  is the emitter-base voltage of diode Q 2 , 
   N PNP  is the ratio of the sizes of diodes Q 1  and Q 2 , and 
   V REF     —     PNP  is the voltage at the first node n 1 . 
   Similarly, the current produced by the n-channel bandgap reference unit  104  at the node n 2  can be expressed as: 
               I   2     =         1     R   1   ′       ⁢     (       V   BE2     +         R   1   ′       R   3   ′       ⁢       k   ⁢           ⁢   T     q     ⁢   ln   ⁢           ⁢     N   NPN         )       =       V   REF_NPN       R   1   ′                 (   11   )             
 
where:
 
   R 1  is the resistance of the resistor R 1 , 
   R 3  is the resistance of the resistor R 3 , 
   V BE2  is the base-emitter voltage of the diode Q 2 , 
   N NPN  is the ratio of the sizes of diodes Q 1  and Q 2 , and 
   V REF     —     NPN  is the voltage at the second node n 2 . 
   Then, applied with (7) the difference current ΔI=I 2 −I 1  is: 
               Δ   ⁢           ⁢   I     =         E   G     ⁡     (       1     R   1   ′       -     1     R   1         )       +         V   T     ⁡     (     1   +     ln   ⁢       T   0     T         )       ⁢     (           (     γ   -   α     )     NPN       R   1   ′       -         (     γ   -   α     )     PNP       R   1         )                 (   12   )             
 
where:
 
   γ for NPN circuit  104  is 1.58 for silicon at room temperature, and 
   γ for PNP circuit  102  is 1.8 for silicon at room temperature. 
   When suitable resistance values for the resistors R 1  and R 1  are selected, the latter term in (12) can be eliminated. Neglecting the temperature dependence of E G , ΔI becomes a temperature independent current. Therefore, a temperature independent current is achieved across the resistor RREF, and the corresponding output reference voltage can be expressed as: 
               V   REF     =         R   REF     ⁡     (       I   2     -     I   1       )       =         R   REF       R   1       ⁢     (       (       V   BE2     -     V   EB2       )     +       (       1     R   3   ′       -     1     R   3         )     ⁢     R   1     ⁢       k   ⁢           ⁢   T     q     ⁢   ln   ⁢           ⁢   N       )                 (   13   )             
 
where:
 
   R REF  is the resistance of the resistor RREF, and 
   R 1 =R 1  and N NPN =N PNP . 
   By tuning the resistors, close values of T 0  for the bandgap units  102 ,  104  can be obtained easily. Thus, the bandgap units  102 ,  104  produce two currents (I 1  and I 2  respectively) of different magnitudes but similar T 0 , such that the subtractor  76  can produce the temperature insensitive voltage V REF  at node n 3 . 
   For the second embodiment bandgap reference circuit  100 , the minimum supply voltage, V DD(min) , is given by:
 
 V   DD(min) =Max└( V   EB2     —     PNP   +|V   TP |+2 ·|V   DSsat |), ( V   BE2     —NPN     +V   TN +2 V   DSsat )┘  (14)
 
where:
 
   V EB2     —     PNP  is the emitter-base voltage of the diode Q 2 , 
   V BE2     —     NPN  is the base-emitter voltage of the diode Q 2 , 
   V TP  is the PNP threshold voltage, 
   V TN  is the NPN threshold voltage, and 
   V DSSat  is the drain-source saturation voltage. 
   Please refer to  FIG. 11  illustrating a circuit diagram of a low-voltage curvature-compensated bandgap reference circuit  200  according to a third embodiment of the present invention. The circuit  200  includes a p-channel bandgap reference unit  202  (similar to the units  72 ,  102 ) and an n-channel bandgap reference unit  204  (similar to the units  74 ,  104 ) mutually connected by the subtractor  76 . The circuit  200  can be considered as a more specific embodiment of the circuit  70 , and consequently the previous description of the circuit  70  also applies to the circuit  200 . 
   The p-channel bandgap reference unit  202  is similar to the bandgap reference circuit  30  of  FIG. 3 , and as such, components with same reference numerals are the same. The p-channel bandgap reference unit  202  includes the operational amplifier  112 ; the transistor M 1  having the source connected to the voltage V DD , the drain connected to the positive input end of the amplifier  112  through a seventh resistor R 1   a , and the gate connected to the output end of the amplifier  112 ; and the transistor M 2  having the source connected to the voltage V DD , the drain connected to the negative input end of the amplifier  112  through an eighth resistor R 2   a , and the gate connected to the output end of the amplifier  112 . The circuit  202  further comprises a ninth resistor R 1   b  connected between ground and the positive input end of the amplifier  112 , a tenth resistor R 2   b  connected between ground and the negative input end of the amplifier  112 , the diode Q 1  with collector and base connected to ground and emitter connected to the drain of the transistor M 1  through the third resistor R 3 , and the diode Q 2  with collector and base connected to ground and emitter connected to the drain of the transistor M 2 . Finally, the circuit  202  comprises the transistor M 3  having the source connected to the voltage V DD , the gate connected to the output end of the amplifier  112 , and the drain connected to the first node n 1 . In the p-channel bandgap reference unit  202 , as in the unit  102 , the transistors M 1 , M 2 , M 3  and diodes Q 1 , Q 2  are PNP. 
   The n-channel bandgap reference unit  204  is similar to an n-channel version of the bandgap reference circuit  30  of  FIG. 3 . The n-channel bandgap reference unit  204  includes the operational amplifier  114 ; the transistor M 1  having the source connected to ground, the drain connected to the positive input end through an eleventh resistor R 1   a , and the gate connected to the output end of the amplifier  114 ; the transistor M 2  having the source connected to ground, a drain connected to the negative input end of the amplifier  114  through a twelfth resistor R 2   a , and a gate connected to the output end of the amplifier  114 ; a thirteenth resistor R 1   b  connected between the voltage V DD  and the positive input end of the amplifier  114 ; and a fourteenth resistor R 2   b  connected between the voltage V DD  and the negative input end of the amplifier  114 . The circuit  204  further comprises the diode Q 1  with collector and base connected to the voltage V DD  and emitter connected to the drain of the transistor M 1  through the resistor R 3 , and the diode Q 2  with collector and base connected to the voltage V DD  and emitter connected to the drain of the transistor M 2 . Finally the circuit includes the transistor M 3  having the source connected to ground, the gate connected to the output end of the amplifier  114 , and the drain connected to the second node n 2 . In the n-channel bandgap reference unit  204 , as in the unit  104 , the transistors M 1 , M 2 , M 3  and diodes Q 1 , Q 2  are NPN. 
   For the third embodiment bandgap reference circuit  200 , the minimum supply voltage, V DD(min) , is given by: 
               V     DD   ⁡     (   min   )         =     Max   ⁡     [             (           R     1   ⁢   b           R     1   ⁢   a       +     R     1   ⁢   b           ⁢     V   EB2_PNP       +          V   TP          +     2   ·          V   DSsat              )     ,               (           R     1   ⁢   b     ′         R     1   ⁢   a     ′     +     R     1   ⁢   b     ′         ⁢     V   BE2_NPN       +     V   TN     +     2   ⁢     V   DSsat         )           ]               (   15   )             
 
where:
         R 1a , R 1b , R 1a , and R 1b  are the resistances of the resistors R 1   a , R 1   b , R 1   a , and R 1   b , respectively.       

   Operation and results of the first, second, and third embodiment circuits  70 ,  100 ,  200  are similar. In the third embodiment, equation ( 13 ) still applies, however, the value of R 1  is really R 1a +R 1b =R 1a + 1b . Generally, the second embodiment circuit  100  is more accurate requiring a supply voltage V DD =1.5 V, while third embodiment circuit  200  is less accurate but only requires the supply voltage V DD =0.9 V. 
     FIG. 12  is a graph of reference voltage versus temperature, and  FIG. 13  is a graph of minimum supply voltage for the third embodiment bandgap reference circuit  200  of  FIG. 11 .  FIG. 12  and  FIG. 13  plot results of a simulation of the circuit  200  which specified TSMC 0.25 μm technology.  FIG. 12  shows a 10.7 ppm/° C. bandgap voltage reference from −10 to 120° C.  FIG. 13  shows the minimum supply voltage of 0.9 V. 
   While the bandgap reference circuits  70 ,  100 , and  200  were previously described as CMOS circuits, there is no reason why they cannot be implemented with other technologies such as with discrete components, BiCMOS, or emerging semiconductor processes. Furthermore, suitable combinations, where a mix of component types are used, of current or new technologies can also be used to realize the present invention. 
   In contrast to the prior art, the present invention provides a curvature-compensated low-voltage bandgap reference having a temperature insensitive reference voltage of less than 1 volt at the third node. Such a circuit can be readily manufactured with established CMOS method, and no low-threshold voltage or BiCMOS devices are required. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.