Patent Publication Number: US-11037502-B2

Title: Shift register and driving method thereof, gate driving circuit, array substrate, and display device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is a US National Stage of International Application No. PCT/CN2019/098230, filed Jul. 29, 2019, which claims priority to Chinese Patent Application No. 201811345137.5 filed with Chinese Patent Office on Nov. 13, 2018, and entitled “Shift Register and Driving Method Thereof, and Gate Driving Circuit and Relevant Devices”, which is hereby incorporated by reference in its entirety. 
     FIELD 
     The present disclosure relates to the field of displaying, and particularly to a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device. 
     BACKGROUND 
     With the rapid development of display technologies, display panels are increasingly developed toward high integration and low cost. A gate driver on array (GOA) technology integrates a thin film transistor (TFT) gate driving circuit on an array substrate of a display panel to form a scanning driver for the display panel, thereby eliminating a wiring space for a bonding region and a fan-out region of a gate integrated circuit (IC). The general gate driving circuit includes a plurality of cascaded shift registers, and each stage of shift register is connected to one corresponding gate line, so as to sequentially input a scanning signal to each row of gate line on the display panel through each stage of shift register. However, since the gate line in each row is correspondingly connected to one shift register, the gate driving circuit is complicated in structural design, and occupies a larger space of the display panel, thereby being not conducive to a narrow-bezel design. 
     SUMMARY 
     An embodiment of the present disclosure provides a shift register. The shift register includes: a signal control circuit, coupled to an input signal terminal and a reset signal terminal; a branch control circuit, coupled to a first output terminal of the signal control circuit; a cascade signal output circuit, coupled to a cascade signal output terminal and a second output terminal of the signal control circuit; and at least two scanning signal output circuits, wherein one of the at least two scanning signal output circuits is coupled to the second output terminal of the signal control circuit, at least one corresponding scanning signal output terminal, and one corresponding output terminal of the branch control circuit. 
     Optionally, in the embodiment of the present disclosure, the cascade signal output circuit is coupled to the first output terminal of the signal control circuit. 
     Optionally, in the embodiment of the present disclosure, the at least two scanning signal output circuits include two scanning signal output circuits, which are a first scanning signal output circuit, and a second scanning signal output circuit. The first scanning signal output circuit is coupled to a first output terminal of the branch control circuit, and the second scanning signal output circuit is coupled to a second output terminal of the branch control circuit. 
     Optionally, in the embodiment of the present disclosure, the branch control circuit includes: a first transistor and a second transistor. The first transistor is configured to connect the first output terminal of the signal control circuit with the first output terminal of the branch control circuit under control of an active level, and the second transistor is configured to connect the first output terminal of the signal control circuit with the second output terminal of the branch control circuit under control of the active level. 
     Optionally, in the embodiment of the present disclosure, a gate and a first electrode of the first transistor are both coupled to the first output terminal of the signal control circuit, and a second electrode of the first transistor is the first output terminal of the branch control circuit; and a gate and a first electrode of the second transistor are both coupled to the first output terminal of the signal control circuit, and a second electrode of the second transistor is the second output terminal of the branch control circuit. 
     Optionally, in the embodiment of the present disclosure, the gate of the first transistor is coupled to a first reference signal terminal. The first electrode of the first transistor is coupled to the first output terminal of the signal control circuit, and the second electrode of the first transistor is the first output terminal of the branch control circuit; and the gate of the second transistor is coupled to the first reference signal terminal, the first electrode of the second transistor is coupled to the first output terminal of the signal control circuit, and the second electrode of the second transistor is the second output terminal of the branch control circuit. 
     Optionally, in the embodiment of the present disclosure, the first scanning signal output circuit includes: at least one first subscanning signal output circuit, wherein one first subscanning signal output circuit is coupled to a second reference signal terminal, one corresponding first clock signal terminal, and one corresponding first subscanning signal output terminal. 
     Optionally, in the embodiment of the present disclosure, the first subscanning signal output circuit includes: a third transistor, a fourth transistor, and a first capacitor; a gate of the third transistor is coupled to the first output terminal of the branch control circuit, a first electrode of the third transistor is coupled to the first clock signal terminal, and a second electrode of the third transistor is coupled to the corresponding first subscanning signal output terminal; a gate of the fourth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the fourth transistor is coupled to the second reference signal terminal, and a second electrode of the fourth transistor is coupled to the corresponding first subscanning signal output terminal; and the first capacitor is coupled between the gate of the third transistor and the first subscanning signal output terminal. 
     Optionally, in the embodiment of the present disclosure, the second scanning signal output circuit includes: at least one second subscanning signal output circuit, wherein one second subscanning signal output circuit is coupled to the second reference signal terminal, one corresponding second clock signal terminal, and one corresponding second subscanning signal output terminal. 
     Optionally, in the embodiment of the present disclosure, the second subscanning signal output circuit includes: a fifth transistor, a sixth transistor, and a second capacitor; a gate of the fifth transistor is coupled to the second output terminal of the branch control circuit, a first electrode of the fifth transistor is coupled to the second clock signal terminal, and a second electrode of the fifth transistor is coupled to the corresponding second subscanning signal output terminal; a gate of the sixth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the sixth transistor is coupled to the second reference signal terminal, and a second electrode of the sixth transistor is coupled to the corresponding second subscanning signal output terminal; and the second capacitor is coupled between the gate of the fifth transistor and the second subscanning signal output terminal. 
     Optionally, in the embodiment of the present disclosure, the cascade signal output circuit includes: a seventh transistor, an eighth transistor, and a third capacitor; a gate of the seventh transistor is coupled to the first output terminal of the signal control circuit, a first electrode of the seventh transistor is coupled to a third clock signal terminal, and a second electrode of the seventh transistor is coupled to the cascade signal output terminal; a gate of the eighth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the eighth transistor is coupled to a third reference signal terminal, and a second electrode of the eighth transistor is coupled to the cascade signal output terminal; and the third capacitor is coupled between the gate of the seventh transistor and the cascade signal output terminal. 
     Optionally, in the embodiment of the present disclosure, the signal control circuit includes: an input circuit, a reset circuit, and a node control circuit. The input circuit is coupled to the input signal terminal, the first reference signal terminal, and the first output terminal of the signal control circuit; the reset circuit is coupled to the reset signal terminal, the third reference signal terminal, and the first output terminal and the second output terminal of the branch control circuit; and the node control circuit is coupled to the third reference signal terminal, the first output terminal and the second output terminal of the signal control circuit, and the first output terminal and the second output terminal of the branch control circuit. 
     Optionally, in the embodiment of the present disclosure, the input circuit includes: a ninth transistor, wherein a gate of the ninth transistor is coupled to the input signal terminal, a first electrode of the ninth transistor is coupled to the first reference signal terminal, and a second electrode of the ninth transistor is coupled to the first output terminal of the signal control circuit; the reset circuit includes: a tenth transistor and an eleventh transistor, wherein a gate of the tenth transistor is coupled to the reset signal terminal, a first electrode of the tenth transistor is coupled to the third reference signal terminal, and a second electrode of the tenth transistor is coupled to the first output terminal of the branch control circuit; and a gate of the eleventh transistor is coupled to the reset signal terminal, a first electrode of the eleventh transistor is coupled to the third reference signal terminal, and a second electrode of the eleventh transistor is coupled to the second output terminal of the branch control circuit; and the node control circuit includes: a twelfth transistor, a thirteenth transistor, and an inverter, wherein a gate of the twelfth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the twelfth transistor is coupled to the third reference signal terminal, and a second electrode of the twelfth transistor is coupled to the first output terminal of the branch control circuit; a gate of the thirteenth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the thirteenth transistor is coupled to the third reference signal terminal, and a second electrode of the thirteenth transistor is coupled to the second output terminal of the branch control circuit; an input terminal of the inverter is coupled to the first output terminal of the signal control circuit, and an output terminal of the inverter is coupled to the second output terminal of the signal control circuit. 
     Optionally, in the embodiment of the present disclosure, the reset circuit further includes: a fourteenth transistor, wherein the first electrode of the tenth transistor and the first electrode of the eleventh transistor are respectively coupled to the third reference signal terminal through the fourteenth transistor, and a gate of the fourteenth transistor is coupled to the reset signal terminal; and the node control circuit further includes: a fifteenth transistor, wherein the first electrode of the twelfth transistor and the first electrode of the thirteenth transistor are respectively coupled to the third reference signal terminal through the fifteenth transistor, and a gate of the fifteenth transistor is coupled to the second output terminal of the signal control circuit. 
     Optionally, in the embodiment of the present disclosure, the shift register further includes: a detection circuit. The detection circuit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a fourth capacitor; a gate of the sixteenth transistor is coupled to a first detection control signal, a first electrode of the sixteenth transistor is coupled to the input signal terminal, and a second electrode of the sixteenth transistor is coupled to a first electrode of the eighteenth transistor; a gate of the seventeenth transistor is coupled to the first detection control signal, a first electrode of the seventeenth transistor is coupled to a gate of the nineteenth transistor, and a second electrode of the seventeenth transistor is coupled to the first electrode of the eighteenth transistor; a gate of the eighteenth transistor is coupled to the gate of the nineteenth transistor, and a second electrode of the eighteenth transistor is coupled to a fourth reference signal terminal; a first electrode of the nineteenth transistor is coupled to the fourth reference signal terminal, and a second electrode of the nineteenth transistor is coupled to a first electrode of the twentieth transistor; a gate of the twentieth transistor is coupled to a second detection control signal terminal, and a second electrode of the twentieth transistor is coupled to the first output terminal of the signal control circuit; and the fourth capacitor is coupled between the first electrode of the nineteenth transistor and the gate of the nineteenth transistor. 
     Correspondingly, an embodiment of the present disclosure further provides a gate driving circuit, including a plurality of the cascaded shift registers provided by the embodiment of the present disclosure; an input signal terminal of a first-stage shift register is coupled to a frame start signal terminal; in every four adjacent stages of shift registers, an input signal terminal of a fourth-stage shift register is coupled to a cascade signal input terminal of the first-stage shift register; and in every five adjacent stages of shift registers, a reset signal terminal of the first-stage shift register is coupled to a cascade signal input terminal of a fifth-stage shift register. 
     Correspondingly, an embodiment of the present disclosure further provides an array substrate including the gate driving circuit according to the embodiment of the present disclosure. 
     Correspondingly, the embodiment of the present disclosure further provides a display device, including the array substrate according to the embodiment of the present disclosure. 
     Correspondingly, an embodiment of the present disclosure further provides a driving method of the shift register according to the embodiment of the present disclosure. The driving method includes: a display scanning period, the display scanning period includes: an input period, an output period, and a reset period; in the input period, the signal control circuit controls a signal of the first output terminal of the signal control circuit and a signal of the second output terminal of the signal control circuit in response to a signal of the input signal terminal; the branch control circuit controls output signals of the output terminals of the branch control circuit in response to the signal of the first output terminal of the signal control circuit; the cascade signal output circuit controls the cascade signal output terminal to output a cascade signal in response to the signal of the first output terminal of the signal control circuit. The scanning signal output circuits control at least one corresponding scanning signal output terminal to output different scanning signals in response to signals of corresponding output terminals of the branch control circuit. In the output period, the branch control circuit controls output signals of the output terminals of the branch control circuit in response to the signal of the first output terminal of the signal control circuit. The cascade signal output circuit controls the cascade signal output terminal to output a cascade signal in response to the signal of the first output terminal of the signal control circuit. The scanning signal output circuits control at least one corresponding scanning signal output terminal to output different scanning signals in response to signals of corresponding output terminals of the branch control circuit. In the reset period, the signal control circuit controls the signal of the first output terminal of the signal control circuit and the signal of the second output terminal of the signal control circuit in response to a signal of the reset signal terminal. The cascade signal output circuit controls the cascade signal output terminal to output the cascade signal in response to the signal of the first output terminal of the signal control circuit. The scanning signal output circuits control at least one corresponding scanning signal output terminal to output different scanning signals in response to signals of corresponding output terminals of the branch control circuit. 
     Optionally, in the embodiment of the present disclosure, the scanning signal output circuits include two scanning signal output circuits, which are a first scanning signal output circuit and a second scanning signal output circuit. The first scanning signal output circuit includes: a plurality of first subscanning signal output circuits, and the second scanning signal output circuit includes: a plurality of second subscanning signal output circuits. In the input period and the output period, the first subscanning signal output circuit provides a signal of the corresponding first clock signal terminal to one corresponding first subscanning signal output terminal in response to the signal of the first output terminal of the branch control circuit, the second subscanning signal output circuit provides a signal of the corresponding second clock signal terminal to one corresponding second subscanning signal output terminal in response to the signal of the second output terminal of the branch control circuit, and the cascade signal output circuit provides a signal of the third clock signal terminal to the cascade signal output terminal in response to the signal of the first output terminal of the signal control circuit. In the reset period, the first subscanning signal output circuit provides a signal of the second reference signal terminal to the corresponding first subscanning signal output terminal in response to the signal of the second output terminal of the signal control circuit, the second subscanning signal output circuit provides the signal of the second reference signal terminal to the corresponding second subscanning signal output terminal in response to the signal of the second output terminal of the signal control circuit, and the cascade signal output circuit provides a signal of the third reference signal terminal to the cascade signal output terminal in response to the signal of the second output terminal of the signal control circuit. 
     Optionally, in the embodiment of the present disclosure, in the display scanning period, signal timings of the first clock signal terminals are the same, signal timings of the second clock signal terminals are the same, and the signal timings of the first clock signal terminals and the signal timings of the second clock signal terminals are different. 
     Optionally, in the embodiment of the present disclosure, signal cycles of the first clock signal terminal, the second clock signal terminal and the third clock signal terminal are the same. In a same signal cycle, a signal rising edge of the third clock signal terminal appears before a signal rising edge of the second clock signal terminal, and a signal falling edge of the third clock signal terminal appears after a signal falling edge of the first clock signal terminal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic structural diagram of a shift register in the related art; 
         FIG. 2  is a simulation signal diagram of the shift register shown in  FIG. 1 ; 
         FIG. 3  is a schematic structural diagram of a shift register in accordance with an embodiment of the present disclosure; 
         FIG. 4  is a specific schematic structural diagram of a shift register in accordance with an embodiment of the present disclosure; 
         FIG. 5  is a circuit timing diagram in accordance with an embodiment of the present disclosure; 
         FIG. 6  is a simulation timing diagram of the shift register shown in  FIG. 4  after simulation is performed on the shift register; 
         FIG. 7  is another specific schematic structural diagram of a shift register in accordance with an embodiment of the present disclosure; 
         FIG. 8  is another circuit timing diagram in accordance with an embodiment of the present disclosure; 
         FIG. 9  is another specific schematic structural diagram of a shift register in accordance with an embodiment of the present disclosure; 
         FIG. 10  is a schematic structural diagram of a pixel circuit in accordance with an embodiment of the present disclosure; 
         FIG. 11  is another circuit timing diagram in accordance with an embodiment of the present disclosure; 
         FIG. 12  is another specific schematic structural diagram of a shift register in accordance with an embodiment of the present disclosure; 
         FIG. 13  is a flow diagram of a driving method in accordance with an embodiment of the present disclosure; 
         FIG. 14 a    is a schematic structural diagram of a gate driving circuit in accordance with an embodiment of the present disclosure; and 
         FIG. 14 b    is another schematic structural diagram of a gate driving circuit in accordance with an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In order to make the objects, technical solutions and advantages of the present disclosure clearer, the implementations of a shift register and a driving method thereof, a gate driving circuit, and a display device according to embodiments of the present disclosure are described below in detail in combination with the accompanying drawings. It should be understood that the preferred embodiments described below are merely to illustrate and explain the present disclosure, and not intended to limit the present disclosure. Furthermore, the embodiments in the present disclosure and features in the embodiments may be combined with each other under the condition of no confliction. It should be noted that shapes in the accompanying drawings do not reflect real proportions, and are merely to illustrate the contents of the present disclosure. Furthermore, same or similar reference numerals throughout indicate same or similar elements or elements with same or similar functions. 
     As shown in  FIG. 1 , in order to output a plurality of scanning signals, a shift register may include a plurality of scanning signal output circuits  01 . For example, in  FIG. 1 , two scanning signal output circuits  01  are provided, wherein one scanning signal output circuit  01  outputs a scanning signal G 1 , and the other scanning signal output circuit  01  outputs a scanning signal G 2 . Specifically, a signal of a pull-up node A and a signal of a pull-down node B are controlled through a signal control circuit. The scanning signal output circuit  01  that outputs the scanning signal G 1  includes transistors M 01  and M 02 , and a capacitor C 01 , wherein a gate of the transistor M 01  is coupled to the pull-up node A, a first electrode of the transistor M 01  is configured to receive a clock signal CK 1 , and a second electrode of the transistor M 01  is configured to output the scanning signal G 1 . A gate of the transistor M 02  is coupled to the pull-down node B, a first electrode of the transistor M 02  is configured to receive a signal VGL, and a second electrode of the transistor M 02  is coupled to the second electrode of the transistor M 01 . The capacitor C 01  is coupled between the pull-up node A and the second electrode of the transistor M 01 . The scanning signal output circuit  01  that outputs the scanning signal G 2  includes: transistors M 03  and M 04 , and a capacitor C 02 , wherein a gate of the transistor M 03  is coupled to the pull-up node A, a first electrode of the transistor M 03  is configured to receive a clock signal CK 2 , and a second electrode of the transistor M 03  is configured to output the scanning signal G 2 . A gate of the transistor M 04  is coupled to the pull-down node B, a first electrode of the transistor M 04  is configured to receive the signal VGL, and a second electrode of the transistor M 04  is coupled to the second electrode of the transistor M 03 . The capacitor C 02  is coupled between the pull-up node A and the second electrode of the transistor M 03 . The transistor M 01  may provide a signal of the clock signal CK 1  to a second terminal of the transistor M 01  under control of a signal of the pull-up node A, and the clock signal CK 1  is output as the scanning signal G 1 . The transistor M 03  may provide a signal of the clock signal CK 2  to a second terminal thereof under control of the signal of the pull-up node A, and the clock signal CK 2  is output as the scanning signal G 2 . A simulation timing diagram may be obtained by simulating the clock signals CK 1  and CK 2 , the signal a of the pull-up node A, the signal b of the pull-down node B, and the scanning signals G 1  and G 2 , as shown in  FIG. 2 . Since a high level of the clock signal CK 1  appears earlier than a high level of the clock signal CK 2 , the transistor M 01  is turned on under control of the signal of the pull-up node A, to pull up the level of the pull-up node A when the high-level signal of the clock signal CK 1  is output as the scanning signal G 1 . The transistor M 03  is turned on under control of the signal of the pull-up node A, to further pull up the level of the pull-up node A when the high-level signal of the clock signal CK 2  is output as the scanning signal G 2 . The transistor M 01  and the transistor M 03  are both controlled by the signal of the same pull-up node A, and the high level of the clock signal CK 1  is preferentially converted into a low level, and as a result, the fall time RFT (12 us) of the scanning signal G 1  recovered from the high level to the low level is shorter than the fall time RFT (14 us) of the scanning signal G 2  recovered from the high level to the low level, thereby resulting in differences between waveforms of the output scanning signals G 1  and G 2 . 
     Based on the above contents, an embodiment of the present disclosure provides a shift register, as shown in  FIG. 3 . The shift register may include a signal control circuit  10 , a branch control circuit  20 , a cascade signal output circuit  30 , and at least two scanning signal output circuits  40 _ m  (1≤m≤M, wherein M denotes a total number of the scanning signal output circuits.  FIG. 3  takes M being equal to 2 as an example). 
     The signal control circuit  10  is coupled to an input signal terminal INPUT and a reset signal terminal RE, that is, the signal control circuit  10  is configured to control signals of a first output terminal and a second output terminal of the signal control circuit  10  in response to an input signal INPUT and a reset signal RE. For the sake of convenience in description, the first output terminal of the signal control circuit  10  is denoted by a signal of a first node PU, and the second output terminal of the signal control circuit  10  is denoted by a signal of a second node PD. 
     The branch control circuit  20  is coupled to the first output terminal of the signal control circuit  10 , that is, the branch control circuit  20  is configured to control signals of output control nodes PO_m one-to-one corresponding to the scanning signal output circuits  40 _ m  in response to the signal of the first node PU. For the sake of convenience in description, output terminals of the branch control circuit  20  are denoted by the output control nodes PO_m. 
     The cascade signal output circuit  30  is coupled to a cascade signal output terminal CROUT, and the first output terminal and the second output terminal of the signal control circuit  10 , that is, the cascade signal output circuit  30  is configured to output a cascade signal CR in response to the signals of the first node PU and the second node PD. That is, the cascade signal output circuit  30  is directly coupled to the first output terminal of the signal control circuit  10  without the branch control circuit  20 . 
     Each scanning signal output circuit  40 _ m  is coupled to the second output terminal of the signal control circuit  10 , at least one corresponding scanning signal output terminal goutm, and one corresponding output terminal of the branch control circuit  20 . That is, each scanning signal output circuit  40 _ m  is configured to output different scanning signal goutm in response to the signal of the corresponding output control node PO_m and the signal of the second node PD. 
     The shift register according to the embodiment of the present disclosure, the signal control circuit controls the signal of the first node and the signal of the second node in response to the signals of the input signal terminal and the reset signal terminal. Since the branch control circuit is configured to control the signals of the output control nodes which one-to-one corresponds to the scanning signal output circuits in response to the signal of the first node, the different output control nodes may be separated, and therefore, the variation of the signal of one output control node may not affect the signals of other output control nodes. In response to the signals of the first node and the second node, the cascade signal output circuit outputs the cascade signal to provide an input signal to the next stage of shift register. Through the arrangement of the plurality of scanning signal output circuits, the scanning signal output circuits output different scanning signals in response to the signals of the corresponding output control nodes and the signal of the second node. In this way, each shift register may output a plurality of scanning signals which correspond to different gate lines in an array substrate. Compared with the shift register in the related art, which may only output one scanning signal, the shift register in the present disclosure may has the advantages that the number of the shift registers in a gate driving circuit is reduced, an occupation space of the gate driving circuit is reduced, and an ultra-narrow-bezel design is realized; and furthermore, the signals of the different output control nodes do not affect each other, so that the stability of the waveforms of the output scanning signals may also be improved, and the differences in the waveforms of the scanning signals are avoided. 
     During specific implementation, in the embodiment of the present disclosure, the first node PU may be a pull-up node, and the second node PD may be a pull-down node. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the signal control circuit  10  may include an input circuit  11 , a reset circuit  12 , and a node control circuit  13 . In this way, levels of the signals of the first node PU, the output control nodes PO_m and the second node PD may be controlled by cooperation of the input circuit  11 , the reset circuit  12 , and the node control circuit  13 . The input circuit  11  is coupled to the input signal terminal INPUT, a first reference signal terminal VREF 1 , and the first output terminal of the signal control circuit, and the input circuit  11  is configured to provide a signal of the first reference signal terminal VREF 1  to the first node PU in response to the signal of the input signal terminal INPUT. The reset circuit  12  is coupled to the reset signal terminal RE, a third reference signal terminal VREF 3 , and the first output terminal and the second output terminal of the branch control circuit  20 , and the reset circuit  12  is configured to provide a signal of the third reference signal terminal VREF 3  to the output control nodes PO_m corresponding to the scanning signal output circuits  40 _ m  in response to the signal of the reset signal terminal RE. The node control circuit  13  is coupled to the first reference signal terminal VREF 1 , the third reference signal terminal VREF 3 , the first output terminal and the second output terminal of the signal control circuit  10 , and the first output terminal and the second output terminal of the branch control circuit  20 , and the node control circuit  13  is configured to control the signal of the first node PU and the signals of the output control nodes PO_m to be respectively opposite to the level of the signal of the second node PD. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the cascade signal output circuit  30  is configured to provide a signal of a third clock signal terminal CLK 3  to the cascade signal output terminal CROUT in response to the signal of the first node PU, and provide the signal of the third reference signal terminal VREF 3  to the cascade signal output terminal CROUT in response to the signal of the second node PD. 
     The present disclosure is described in detail below in combination of specific embodiments. It should be noted that the present embodiment is to better explain the present disclosure, and not intended to limit the present disclosure. 
     Embodiment I 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 3  and  FIG. 4 , two scanning signal output circuits  40 _ m  may be configured, or, three, four, five and other numbers of scanning signal output circuits  40 _ m  may also be configured. Of course, in actual application, the number of the scanning signal output circuits  40 _ m  may be designed and determined according to an actual application environment, which is not limited herein. Two scanning signal output circuits  40 _ m  are taken as an example for illustration below. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , a first scanning signal output circuit  40 _ 1  in the two scanning signal output circuits may include at least one first subscanning signal output circuit  41 _ n  (1≤n≤N, wherein N denotes a total number of the first subscanning signal output circuits, and in  FIG. 4 , N being equal to 1 is taken as an example). One first subscanning signal output circuit  41 _ n  is coupled to a second reference signal terminal VREF 2 , one corresponding first clock signal terminal CLK 1 _ n , and one corresponding first subscanning signal output terminal GOUT 1 _ n  respectively. The first subscanning signal output circuits  41 _ n  one-to-one correspond to the first clock signal terminals CLK 1 _ n , and the first subscanning signal output circuits  41 _ n  one-to-one correspond to the first subscanning signal output terminals GOUT 1 _ n . Furthermore, the first subscanning signal output circuit  41 _ n  is configured to respond to the signal of the same output control node, that is, the first subscanning signal output circuit  41 _ n  is configured to provide a signal of the corresponding first clock signal terminal CLK 1 _ n  to the corresponding first subscanning signal output terminal GOUT 1 _ n  in response to a signal of an output control node PO_ 1 ; and provide a signal of the second reference signal terminal VREF 2  to the corresponding first subscanning signal output terminal GOUT 1 _ n  in response to a signal of a second node PD. Furthermore, the first subscanning signal output terminal GOUT 1 _ n  outputs a scanning signal gout 1 _ n.    
     Further, during specific implementation, as shown in  FIG. 4 , one first subscanning signal output circuit may be set, or two first subscanning signal output circuits may be set. In actual application, the specific number of the first subscanning signal output circuits may be designed and determined according to an actual application environment, which is not limited herein. One first subscanning signal output circuit is taken as an example for illustration below. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , a second scanning signal output circuit  40 _ 2  in the two scanning signal output circuits may include: at least one second subscanning signal output circuit  42 _ k  (1≤k≤K, wherein K denotes a total number of the second subscanning signal output circuits, and in  FIG. 4 , K is equal to 1). One second subscanning signal output circuit  42 _ k  is coupled to the second reference signal terminal VREF 2 , one corresponding second clock signal terminal CLK 2 _ k , and one corresponding second subscanning signal output terminal respectively. The second subscanning signal output circuits  42 _ k  one-to-one correspond to the second clock signal terminals CLK 2 _ k , and the second subscanning signal output circuits  42 _ k  one-to-one correspond the second subscanning signal output terminals GOUT 2 _ k . Furthermore, the second subscanning signal output circuits  42 _ k  are configured to respond to a signal of a same output control node, that is, each second subscanning signal output circuit  42 _ k  is configured to provide a signal of the corresponding second clock signal terminal CLK 2 _ k  to the corresponding second subscanning signal output terminal GOUT 2 _ k  in response to a signal of an output control node PO_ 2 ; and provide the signal of the second reference signal terminal VREF 2  to the corresponding second subscanning signal output terminal GOUT 2 _ k  in response to the signal of the second node PD. Furthermore, the second subscanning signal output terminal GOUT 2 _ k  outputs a scanning signal gout 2 _ k.    
     Further, during specific implementation, as shown in  FIG. 4 , one second subscanning signal output circuit may be set, or two second subscanning signal output circuits may be set. In actual application, the number of the second subscanning signal output circuits may be designed and determined according to an actual application environment, which is not limited herein. One second subscanning signal output circuit is taken as an example for illustration below. 
     Further, during specific implementation, in the embodiment of the present disclosure, N may be equal to K, and n may be equal to k. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the branch control circuit  20  may include a first transistor M 1  and a second transistor M 2 . The first transistor M 1  is configured to connect the first output terminal of the signal control circuit  10  to the first output terminal of the branch control circuit  20  under control of an active level, and the second transistor M 2  is configured to connect the first output terminal of the signal control circuit  10  to the second output terminal of the branch control circuit  20  under control of the active level. 
     Specifically, a gate and a first electrode of the first transistor M 1  are both coupled to the first node PU, and a second electrode of the first transistor M 1  is coupled to the output control node PO_ 1  corresponding to the first scanning signal output circuit  40 _ 1  in the two scanning signal output circuits. A gate and a first electrode of the second transistor M 2  are both coupled to the first node PU, and a second electrode of the second transistor M 2  is coupled to the output control node PO_ 2  corresponding to the second scanning signal output circuit  40 _ 2  in the two scanning signal output circuits. 
     During specific implementation, the gate of the first transistor M 1  is coupled to the first electrode of the first transistor M 1 , so that the first transistor M 1  forms a diode connection. In this way, when the voltage of the gate of the first transistor M 1  is larger than the voltage of the second electrode of the transistor M 1 , the first transistor M 1  may be turned on to enable the first node PU to be connected to the output control node PO_ 1 ; and when the voltage of the gate of the first transistor M 1  is not larger than the voltage of the second electrode of the first transistor M 1 , the first transistor M 1  may be turned off to enable the first node PU to be disconnected from the output control node PO_ 1 . Similarly, when the voltage of the gate of the second transistor M 2  is larger than the voltage of the second electrode of the second transistor M 2 , the second transistor M 2  may be turned on to enable the first node PU to be connected to the output control node PO_ 2 ; and when the voltage of the gate of the second transistor M 2  is not larger than the voltage of the second electrode of the second transistor M 2 , the second transistor M 2  may be turned off to enable the first node PU to be disconnected from the output control node PO_ 2 . 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the first subscanning signal output circuit  41 _ n  may include: a third transistor M 3 , a fourth transistor M 4 , and a first capacitor C 1 . A gate of the third transistor M 3  is coupled to the corresponding output control node PO_ 1 , a first electrode of the third transistor M 3  is configured to receive the signal of the corresponding first clock signal terminal CLK 1 _ n , and a second electrode of the third transistor M 3  is coupled to the corresponding first subscanning signal output terminal GOUT 1 _ n . A gate of the fourth transistor M 4  is coupled to the second node PD, a first electrode of the fourth transistor M 4  is configured to receive the signal of the second reference signal terminal VREF 2 , and a second electrode of the fourth transistor M 4  is coupled to the corresponding first subscanning signal output terminal GOUT 1 _ n . The first capacitor C 1  is coupled between the gate of the third transistor M 3 , i.e., the corresponding output control node PO_ 1 , and the first subscanning signal output terminal GOUT 1 _ n.    
     During specific implementation, in the embodiment of the present disclosure, the third transistor M 3  in each first subscanning signal output circuit  41 _ n  may be turned on under control of the signal of the output control node PO_ 1 , so as to provide the signal of the corresponding first clock signal terminal CLK 1 _ n  to the corresponding first subscanning signal output terminal GOUT 1 _ n . The fourth transistor M 4  in each first subscanning signal output circuit  41 _ n  may be turned on under control of the signal of the second node PD, so as to provide the signal of the second reference signal terminal VREF 2  to the corresponding first subscanning signal output terminal GOUT 1 _ n . The first capacitor C 1  may maintain the level of the connected output control node PO_ 1  and the level of the first subscanning signal output terminal GOUT 1 _ n , and may maintain the stability of a voltage difference between the output control node PO_ 1  and the first subscanning signal output terminal GOUT 1 _ n  when the output control node PO_ 1  is floating. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the second subscanning signal output circuit  42 _ k  may include a fifth transistor M 5 , a sixth transistor M 6 , and a second capacitor C 2 . A gate of the fifth transistor M 5  is coupled to the corresponding output control node PO_ 2 , a first electrode of the fifth transistor M 5  is configured to receive the signal of the corresponding second clock signal terminal CLK 2 _ k , and a second electrode of the fifth transistor M 5  is coupled to the corresponding second subscanning signal output terminal GOUT 2 _ k . A gate of the sixth transistor M 6  is coupled to the second node PD, a first electrode of the sixth transistor M 6  is configured to receive the signal of the second reference signal terminal VREF 2 , and a second electrode of the sixth transistor M 6  is coupled to the corresponding second subscanning signal output terminal GOUT 2 _ k . The second capacitor C 2  is coupled between the corresponding output control node PO_ 2  and the second subscanning signal output terminal GOUT 2 _ k.    
     During specific implementation, in the embodiment of the present disclosure, the fifth transistor M 5  in each second subscanning signal output circuit  42 _ k  may be turned on under control of the signal of the output control node PO_ 2 , so as to provide the signal of the corresponding second clock signal terminal CLK 2 _ k  to the corresponding second subscanning signal output terminal GOUT 2 _ k . The sixth transistor M 6  in each second subscanning signal output circuit  42 _ k  may be turned on under control of the signal of the second node PD, so as to provide the signal of the second reference signal terminal VREF 2  to the corresponding second subscanning signal output terminal GOUT 2 _ k . The second capacitor C 2  may maintain the level of the connected output control node PO_ 2  and the level of the second subscanning signal output terminal GOUT 2 _ k , and may maintain the stability of a voltage difference between the output control node PO_ 2  and the second subscanning signal output terminal GOUT 2 _ k  when the output control node PO_ 2  is in floating. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the input circuit  11  may include a ninth transistor M 9 . A gate of the ninth transistor M 9  is configured to receive the signal of the input signal terminal INPUT, a first electrode of the ninth transistor M 9  is configured to receive the signal of the first reference signal terminal VREF 1 , and a second electrode of the ninth transistor M 9  is coupled to the first node PU. The ninth transistor M 9  may be turned on under control of the input signal terminal INPUT, to provide the signal of the first reference signal terminal VREF 1  to the first node PU. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the reset circuit  12  may include a tenth transistor M 10  and an eleventh transistor M 11 . A gate of the tenth transistor M 10  is configured to receive the signal of the reset signal terminal RE, a first electrode of the tenth transistor M 10  is configured to receive the signal of the third reference signal terminal VREF 3 , and a second electrode of the tenth transistor M 10  is coupled to one output control node, i.e., the output control node PO_ 1 . A gate of the eleventh transistor M 11  is configured to receive the signal of the reset signal terminal RE, a first electrode of the eleventh transistor M 11  is configured to receive the signal of the third reference signal terminal VREF 3 , and a second electrode of the eleventh transistor M 11  is coupled to the other output control node, i.e., the output control node PO_ 2 . The tenth transistor M 10  may be turned on under control of an active pulse signal of the reset signal terminal RE, to provide the signal of the third reference signal terminal VREF 3  to the output control node PO_ 1 . The eleventh transistor M 11  may be turned on under control of the reset signal terminal RE, to provide the signal of the third reference signal terminal VREF 3  to the output control node PO_ 2 . 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the node control circuit  13  may include: a twelfth transistor M 12 , a thirteenth transistor M 13 , and an inverter ND, wherein a gate of the twelfth transistor M 12  is coupled to the second node PD, a first electrode of the twelfth transistor M 12  is configured to receive the signal of the third reference signal terminal VREF 3 , and a second electrode of the twelfth transistor M 12  is coupled to one output control node, i.e., the output control node PO_ 1 . A gate of the thirteenth transistor M 13  is coupled to the second node PD, a first electrode of the thirteenth transistor M 13  is configured to receive the signal of the third reference signal terminal VREF 3 , and a second electrode of the thirteenth transistor M 13  is coupled to the other output control node, i.e., the output control node PO_ 2 . An input terminal of the inverter ND is coupled to the first node PU, and an output terminal of the inverter ND is coupled to the second node PD. The twelfth transistor M 12  may be turned on under control of the signal of the second node PD, to provide the signal of the third reference signal terminal VREF 3  to the output control node PO_ 1 . The thirteenth transistor M 13  may be turned on under control of the signal of the second node PD, to provide the signal of the third reference signal terminal VREF 3  to the output control node PO_ 2 . The inverter may enable the levels of the input terminal and the output terminal to be opposite. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 4 , the cascade signal output circuit  30  may include a seventh transistor M 7 , an eighth transistor M 8 , and a third capacitor C 3 . A gate of the seventh transistor M 7  is coupled to the first node PU, a first electrode of the seventh transistor M 7  is configured to receive the signal of the third clock signal terminal CLK 3 , and a second electrode of the seventh transistor M 7  is coupled to the cascade signal output terminal CROUT. A gate of the eighth transistor M 8  is coupled to the second node PD, a first electrode of the eighth transistor M 8  is configured to receive the signal of the third reference signal terminal VREF 3 , and a second electrode of the eighth transistor M 8  is coupled to the cascade signal output terminal CROUT. The third capacitor C 3  is coupled between the first node PU and the cascade signal output terminal CROUT. The seventh transistor M 7  may be turned on under control of the signal of the first node PU, to provide the signal of the third clock signal terminal CLK 3  to the cascade signal output terminal CROUT. The eighth transistor M 8  may be turned on under control of the signal of the second node PD, to provide the signal of the third reference signal terminal VREF 3  to the cascade signal output terminal CROUT. The third capacitor C 3  may maintain the level of the first node PU and the level of the cascade signal output terminal CROUT, and may maintain the stability of a voltage difference between the first node PU and the cascade signal output terminal CROUT when the first node PU is in floating. 
     The foregoing is only for exemplifying the specific structures of the circuits in the shift register. During specific implementation, the specific structures of the above circuits are not limited to the above structures provided by the embodiment of the present disclosure, and may also be other structures known by those skilled in the art, and are not limited herein. 
     During specific implementation, in order to unify the manufacturing process, in the embodiment of the present disclosure, as shown in  FIG. 4 , the switching transistors may be N-type transistors. It should be noted that the embodiment of the present disclosure is only illustrated by taking the transistors in the shift register being the N-type transistors as an example. For such a case that the transistors are P-type transistors, the design principle is the same as that of the present disclosure, and also falls within the scope of the protection of the present disclosure. 
     It should be noted that in the embodiment of the present disclosure, when the transistors are the N-type transistors, the signal of the first reference signal terminal is a high-level signal, and the signal of the second reference signal terminal and the signal of the third reference signal terminal are both low-level signals. When the transistors are the P-type transistors, the signal of the first reference signal terminal is a low-level signal, and the signal of the second reference signal terminal and the signal of the third reference signal terminal are both high-level signals. It should be noted that the levels of the signals, which are described in the embodiment of the present disclosure only denote logic levels instead of voltage values actually applied to the signals during specific implementation. 
     Generally, one frame period during display driving may include a display scanning period and a blanking time period. During specific implementation, in the display scanning period, timing of the signals of the first clock signal terminals are the same, timing of the signals of the second clock signal terminals are the same, and the timing of the signals of the first clock signal terminals and the second clock signal terminals are different. For example, as shown in  FIG. 5 , the timing of the first clock signal terminal CLK 1 _ 1  and timing of the second clock signal terminal CLK 2 _ 1  are different. It should be noted that voltage values of the high-level signals described in the embodiment of the present disclosure are the same, for example, the high-level voltage value of the input signal terminal INPUT, the high-level voltage value of the first clock signal terminal CLK 1 _ 1 , the high-level voltage value of the second clock signal terminal CLK 2 _ 1 , and the voltage value of the first reference signal terminal VREF 1  are the same. Further, voltage values of the low-level signals described in the embodiment of the present disclosure may also be the same, for example, the low-level voltage value of the input signal terminal INPUT, the low-level voltage value of the first clock signal terminal CLK 1 _ 1 , the low-level voltage value of the second clock signal terminal CLK 2 _ 1 , and the voltage values of the second reference signal terminal VREF 2  and the third reference signal terminal VREF 3  are the same. In order to reduce the number of signal terminals and reduce spaces occupied by signal lines, the second reference signal terminal VREF 2  and the third reference signal terminal VREF 3  may be set to have a same signal, that is, the same reference signal terminal is used to provide the signals of the second reference signal terminal VREF 2  and the third reference signal terminal VREF 3 . Or, the voltage values of the second reference signal terminal VREF 2  and the third reference signal terminal VREF 3  may also be different, and are not limited herein. 
     During specific implementation, as shown in  FIG. 5 , the cycles of the first clock signal terminal CLK 1 _ n , the second clock signal terminal CLK 2 _ n  and the third clock signal terminal CLK 3  are the same. For example, in one cycle, the duration of the high-level signal of the first clock signal terminal CLK 1 _ n  may be 4a, and the duration of the low-level signal of the first clock signal terminal CLK 1 _ n  may be 6a, so that the duration of one cycle of the signal of the first clock signal terminal CLK 1 _ n  is 10a. In one cycle, the duration of the high-level signal of the second clock signal terminal CLK 2 _ n  may be 4a, and the duration of the low-level signal of the second clock signal terminal CLK 2 _ n  may be 6a, so that the duration of one cycle of the signal of the second clock signal terminal CLK 2 _ n  is 10a. In one cycle, the duration of the high-level signal of the third clock signal terminal CLK 3  may be 5a, and the duration of the low-level signal of the third clock signal terminal CLK 3  may be 5a, so that the duration of one cycle of the signal of the third clock signal terminal CLK 3  is also 10a. Further, in the same cycle, a rising edge of the third clock signal terminal CLK 3  appears before a rising edge of the first clock signal terminal CLK 1 _ n , and a falling edge of the third clock signal terminal CLK 3  appears after a falling edge of the second clock signal terminal CLK 2 _ n . For example, as shown in  FIG. 5 , in the same cycle, the rising edge of the third clock signal terminal CLK 3  is aligned with a rising edge of the first clock signal terminal CLK 1 _ 1 , and the falling edge of the third clock signal terminal CLK 3  is aligned with a falling edge of the second clock signal terminal CLK 2 _ 1 . 
     During specific implementation, in the shift register according to the embodiment of the present disclosure, the N-type transistors are turned on under a high-level signal and turned off under a low-level signal. The P-type transistors are turned on under the low-level signal and turned off under the high-level signal. During specific implementation, the first electrode of each transistor may be used as a source electrode, and the second electrode of each transistor may be used as a drain electrode, or the first electrode of each transistor may be used as the drain electrode, and the second electrode of each transistor may be used as the source electrode. No specific distinction is made here. 
     The structure of the shift register shown in  FIG. 4  is exemplified below to describe the working process of the above shift register according to the embodiment of the present disclosure in combination with the circuit timing diagram, i.e.,  FIG. 5 . In the following description, 1 denotes a high-level signal, and 0 denotes a low-level signal. 1 and 0 represent logic levels, which are merely to better explain the working process of the above shift register according to the embodiment of the present disclosure, instead of indicating the voltage value applied to the gate of each transistor during specific implementation. 
     Specifically, an input period T 1 , an output period T 2  and a reset period T 3  in the circuit timing diagram as shown in  FIG. 5  are selected. 
     In the input period T 1 , INPUT is equal to 1, CLK 1 _ 1  is equal to 0, CLK 2 _ 1  is equal to 0, CLK 3  is equal to 0, and RE is equal to 0. 
     Since INPUT is equal to 1, the ninth transistor M 9  is turned on, to provide a high level of the first reference signal terminal VREF 1  to the first node PU, to enable the signal of the first node PU to be a high-level signal. Since the signal of the first node PU is the high-level signal, the seventh transistor M 7  is turned on, and enables the signal of the second node PD to be a low-level signal under the inverter ND. Therefore, the fourth transistor M 4 , the sixth transistor M 6 , the eighth transistor M 8 , the twelfth transistor M 12 , and the thirteenth transistor M 13  are all controlled to be turned off. The turned-on seventh transistor M 7  provides a low level of the third clock signal terminal CLK 3  to the cascade signal output terminal CROUT, so as to output a low-level cascade signal CR. Since the first transistor M 1  and the second transistor M 2  form a diode connection structure, the signals of the output control nodes PO_ 1  and PO_ 2  are also high-level signals. Since the signal of the output control node PO_ 1  is the high-level signal, the third transistor M 3  is turned on to provide a low level of the first clock signal terminal CLK 1 _ 1  to the first subscanning signal output terminal GOUT 1 _ 1  to output a low-level scanning signal gout 1 _ 1 , and the first capacitor C 1  is charged. Since the signal of the output control node PO_ 2  is the high-level signal, the fifth transistor M 5  is turned on to provide a low level of the second clock signal terminal CLK 2 _ 1  to the second subscanning signal output terminal GOUT 2 _ 1  to output a low-level scanning signal gout 2 _ 1 , and the second capacitor C 2  is charged. Furthermore, RE is equal to 0, so that the tenth transistor M 10  and the eleventh transistor M 11  are both turned off. 
     In the output period T 2 , INPUT is equal to 0, CLK 1 _ 1  is equal to 1, CLK 2 _ 1  is equal to 0, CLK 3  is equal to 1, and RE is equal to 0. 
     INPUT is equal to 1, so that the ninth transistor M 9  is turned off, and the first node PU is in floating. Under the action of the third capacitor C 3 , the signal of the first node PU may be maintained to be the high-level signal, and the seventh transistor M 7  may be turned on, and under the inverter ND, the signal of the second node PD is the low-level signal, so that the fourth transistor M 4 , the sixth transistor M 6 , the eighth transistor M 8 , the twelfth transistor M 12 , and the thirteenth transistor M 13  are controlled to be turned off. The turned-on seventh transistor M 7  provides a high level of the third clock signal terminal CLK 3  to the cascade signal output terminal CROUT. Due to the floating of the first node PU and under the third capacitor C 3 , the level of the first node PU may be pulled up to enable the seventh transistor M 7  to provide the high level of the third clock signal terminal CLK 3  to the cascade signal output terminal CROUT and output a high-level cascade signal CR. Furthermore, the level of the first node PU is pulled up, so that the levels of the output control nodes PO_ 1  and PO_ 2  are also pulled up. Since the level of the output control node PO_ 1  is pulled up, the third transistor M 3  is turned on to provide the low level of the first clock signal terminal CLK 1 _ 1  to the first subscanning signal output terminal GOUT 1 _ 1  to output a low-level scanning signal gout 1 _ 1 . Under the first capacitor C 1 , the level of the output control node PO_ 1  is further pulled up, so that the third transistor M 3  provides the high level of the first clock signal terminal CLK 1 _ 1  to the first subscanning signal output terminal GOUT 1 _ 1  to output a high-level scanning signal gout 1 _ 1 . When the first node PU is pulled up, and the level of the output control node PO_ 1  is further pulled up, the first transistor M 1  forms a diode connection, so that the first node PU and the output control node PO_ 1  are turned off to avoid that the signal of the output control node PO_ 2  is affected when the output control node PO_ 1  is further pulled up. Since the level of the output control node PO_ 2  is pulled up, the fifth transistor M 5  is turned on to provide the low level of the second clock signal terminal CLK 2 _ 1  to the second subscanning signal output terminal GOUT 2 _ 1  to output a low-level scanning signal gout 2 _ 1 . Furthermore, RE is equal to 0, so that the tenth transistor M 10  and the eleventh transistor M 11  are both turned off. 
     Then, the second clock signal terminal CLK 2 _ 1  is converted from the low-level signal to the high-level signal, i.e., from CLK 2 _ 1 =0 to CLK 2 _ 1 =1, and other signals do not change. At the moment, since the fifth transistor M 5  provides the high level of the second clock signal terminal CLK 2 _ 1  to the second subscanning signal output terminal GOUT 2 _ 1 , under the action of the second capacitor C 2 , the level of the output control node PO_ 2  may be further pulled up to enable the fifth transistor M 5  to provide the high level of the second clock signal terminal CLK 2 _ 1  to the second subscanning signal output terminal GOUT 2 _ 1  to output a high-level scanning signal gout 2 _ 1 . When the first node PU is pulled up, and the level of the output control node PO_ 2  is further pulled up, the second transistor M 2  forms a diode connection, so that the first node PU and the output control node PO_ 2  are turned off to avoid that the signal of the output control node PO_ 1  is affected when the output control node PO_ 2  is further pulled up. 
     Then, the first clock signal terminal CLK 1 _ 1  is converted from the high-level signal to the low-level signal, i.e., from CLK 1 _ 1 =1 to CLK 1 _ 1 =0, and other signals do not change. In this way, the third transistor M 3  provides the low level of the first clock signal terminal CLK 1 _ 1  to the first subscanning signal output terminal GOUT 1 _ 1  to output a low-level scanning signal gout 1 _ 1 . 
     In the reset period T 3 , INPUT is equal to 0, and RE is equal to 1. 
     INPUT is equal to 0, so that the ninth transistor M 9  is turned off RE is equal to 1, so that the tenth transistor M 10  and the eleventh transistor M 11  are both turned on. The turned-on tenth transistor M 10  provides the low level of the third reference signal terminal VREF 3  to the output control node PO_ 1  to enable the signal of the output control node PO_ 1  to be the low-level signal, and the turned-on eleventh transistor M 11  provides the low level of the third reference signal terminal VREF 3  to the output control node PO_ 2  to enable the signal of the output control node PO_ 2  to be the low-level signal, so that the first node PU may be discharged to have the low-level signal. In this way, under the action of the inverter ND, the second node PD may have the high-level signal. The signal of the second node PD is the high-level signal, so that the fourth transistor M 4 , the sixth transistor M 6 , the eighth transistor M 8 , the twelfth transistor M 12 , and the thirteenth transistor M 13  are controlled to be turned on. The turned-on fourth transistor M 4  provides the low level of the second reference signal terminal VREF 2  to the first subscanning signal output terminal GOUT 1 _ 1 , so as to output a low-level scanning signal gout 1 _ 1 . The turned-on sixth transistor M 6  provides the low level of the second reference signal terminal VREF 2  to the second subscanning signal output terminal GOUT 2 _ 1 , so as to output a low-level scanning signal gout 2 _ 1 . The turned-on eighth transistor M 8  provides the low level of the third reference signal terminal VREF 3  to the cascade signal output terminal CROUT, so as to output a low-level cascade signal CR. The turned-on twelfth transistor M 12  provides the low level of the third reference signal terminal VREF 3  to the output control node PO_ 1 , so that the signal of the output control node PO_ 1  is further to be at a low level. The turned-on thirteenth transistor M 13  provides the low level of the third reference signal terminal VREF 3  to the output control node PO_ 2 , so that the signal of the output control node PO_ 2  is further made to be at a low level. 
     After the reset period T 3 , INPUT is equal to 0, and RE is equal to 0, so that the signal of the output control node PO_ 1  is maintained to be the low-level signal through the first capacitor C 1 , the signal of the output control node PO_ 2  is maintained to be the low-level signal through the second capacitor C 2 , and the signal of the first node PU is maintained to be the low-level signal through the third capacitor C 3 , so that the signal of the second node PD is the high-level signal, and the fourth transistor M 4 , the sixth transistor M 6 , the eighth transistor M 8 , the twelfth transistor M 12 , and the thirteenth transistor M 13  are controlled to be turned on. The turned-on fourth transistor M 4  provides the low level of the second reference signal terminal VREF 2  to the first subscanning signal output terminal GOUT 1 _ 1 , so as to output a low-level scanning signal gout 1 _ 1 . The turned-on sixth transistor M 6  provides the low level of the second reference signal terminal VREF 2  to the second subscanning signal output terminal GOUT 2 _ 1 , so as to output a low-level scanning signal gout 2 _ 1 . The turned-on eighth transistor M 8  provides the low level of the third reference signal terminal VREF 3  to the cascade signal output terminal CROUT, so as to output a low-level cascade signal CR. The turned-on twelfth transistor M 12  provides the low level of the third reference signal terminal VREF 3  to the output control node PO_ 1 , so that the signal of the output control node PO_ 1  is further to be at a low level. The turned-on thirteenth transistor M 13  provides the low level of the third reference signal terminal VREF 3  to the output control node PO_ 2 , so that the signal of the output control node PO_ 2  is further to be at a low level. 
     Furthermore, the shift register according to the present disclosure may enable the signals of different output control nodes to not affect each other, so that the stability of the waveforms of the output scanning signals may be improved, and a difference in the waveforms of the scanning signals is avoided. A simulation diagram as shown in  FIG. 6  is obtained through simulation of the shift register in Embodiment I. It can be seen from  FIG. 6  that durations of converting the scanning signal gout 1 _ 1  and the scanning signal gout 2 _ 1  from the high-level signals to the low-level signals are both 12 us, so that the waveforms of the scanning signal gout 1 _ 1  and the scanning signal gout 2 _ 1  may be higher in similarity and have relatively smaller difference. 
     In actual application, the shift register in Embodiment I is applied to an array substrate of a display device. The array substrate includes a plurality of gate lines, so that the shift register in Embodiment I outputs scanning signals having a phase difference to two gate lines. The display device may be an organic light-emitting diode (OLED) display device, or may be a liquid crystal display (LCD), which is not limited herein. 
     Furthermore, in the output period, since the first node PU is pulled up by the third capacitor, the levels of the output control nodes PO_ 1  and PO_ 2  may be further pulled up under a pulling up condition, and the driving capacity of the third transistor M 3  and the driving capacity of the fifth transistor M 5  are improved. 
     Embodiment II 
     The same parts of a shift register provided by Embodiment II of the present disclosure as those of the shift register provided by Embodiment I are not repeated herein, and only the different parts will be described below. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 7 , the shift register is provided with two first subscanning signal output circuits  41 _ 1  and  41 _ 2 , and two second subscanning signal output circuits  42 _ 1  and  42 _ 2 . The first subscanning signal output circuit  41 _ 1  corresponds to a first clock signal terminal CLK 1 _ 1  and a first subscanning signal output terminal GOUT 1 _ 1 . The first subscanning signal output circuit  41 _ 2  corresponds to a first clock signal terminal CLK 1 _ 2  and a first subscanning signal output terminal GOUT 1 _ 2 . The second subscanning signal output circuit  42 _ 1  corresponds to a second clock signal terminal CLK 2 _ 1  and a second subscanning signal output terminal GOUT 2 _ 1 . The second subscanning signal output circuit  42 _ 2  corresponds to a second clock signal terminal CLK 2 _ 2  and a second subscanning signal output terminal GOUT 2 _ 2 . 
     The working process of the above shift register provided by the present embodiment is described below in combination with a circuit timing diagram shown in  FIG. 8 . Specifically, an input period T 1 , an output period T 2  and a reset period T 3  in the circuit timing diagram as shown in  FIG. 8  are selected. 
     In the input period T 1 , INPUT is equal to 1, CLK 1 _ 1  is equal to 0, CLK 1 _ 2  is equal to 0, CLK 2 _ 1  is equal to 0, CLK 2 _ 2  is equal to 0, CLK 3  is equal to 0, and RE is equal to 0. Only a third transistor M 3 , a fourth transistor M 4 , and a first capacitor C 1  in the first subscanning signal output circuit  41 _ 2 , and a fifth transistor M 5 , a sixth transistor M 6 , and a second capacitor C 2  in the second subscanning signal output circuit  42 _ 2  are described below. The rest working process in the input period may be basically the same as the working process of the input period T 1  in Embodiment I, and no more details are described herein. Specifically, since a signal of an output control node PO_ 1  is a high-level signal, the third transistor M 3  is turned on to provide a low level of the first clock signal terminal CLK 1 _ 2  to the first subscanning signal output terminal GOUT 1 _ 2  to output a low-level scanning signal gout 1 _ 2 , and the first capacitor C 1  is charged. Since a signal of the output control node PO_ 2  is a high-level signal, the fifth transistor M 5  is turned on to provide a low level of the second clock signal terminal CLK 2 _ 2  to the second subscanning signal output terminal GOUT 2 _ 2  to output a low-level scanning signal gout 2 _ 2 , and the second capacitor C 2  is charged. 
     In the output period T 2 , INPUT is equal to 0, CLK 1 _ 1  is equal to 1, CLK 1 _ 2  is equal to 1, CLK 2 _ 1  is equal to 0, CLK 2 _ 2  is equal to 0, CLK 3  is equal to 1, and RE is equal to 0. Only the third transistor M 3 , the fourth transistor M 4 , and the first capacitor C 1  in the first subscanning signal output circuit  41 _ 2 , and the fifth transistor M 5 , the sixth transistor M 6 , and the second capacitor C 2  in the second subscanning signal output circuit  42 _ 2  are described below. The rest working process of the output period may be basically the same as the working process of the output period T 2  in Embodiment I, and no more details are described herein. Since a level of the output control node PO_ 1  is further pulled up, the third transistor M 3  provides a high level of the first clock signal terminal CLK 1 _ 2  to the first subscanning signal output terminal GOUT 1 _ 2  to output a high-level scanning signal gout 1 _ 2 . Then, the second clock signal terminal CLK 2 _ 2  is converted from the low-level signal to the high-level signal. Since a level of the output control node PO_ 2  is further pulled up, the fifth transistor M 5  provides a high level of the second clock signal terminal CLK 2 _ 2  to the second subscanning signal output terminal GOUT 2 _ 2  to output a high-level scanning signal gout 2 _ 2 . Then, the first clock signal terminal CLK 1 _ 2  is converted from the high-level signal to the low-level signal, i.e., from CLK 1 _ 2 =1 to CLK 1 _ 2 =0, and other signals do not change. In this way, the third transistor M 3  provides the low level of the first clock signal terminal CLK 1 _ 2  to the first subscanning signal output terminal GOUT 1 _ 2  to output a low-level scanning signal gout 1 _ 2 . 
     In the reset period T 3 , INPUT is equal to 0, and RE is equal to 1. Only the third transistor M 3 , the fourth transistor M 4 , and the first capacitor C 1  in the first subscanning signal output circuit  41 _ 2 , and the fifth transistor M 5 , the sixth transistor M 6 , and the second capacitor C 2  in the second subscanning signal output circuit  42 _ 2  are described below. The rest working process of the reset period may be basically the same as the working process of the reset period T 3  in Embodiment I, and no more details are described herein. The third transistor M 3  and the fifth transistor M 5  are both turned off, and the fourth transistor M 4  and the sixth transistor M 6  are both turned on. The turned-on fourth transistor M 4  provides a low level of a second reference signal terminal VREF 2  to the first subscanning signal output terminal GOUT 1 _ 2 , so as to output a low-level scanning signal gout 1 _ 2 . The turned-on sixth transistor M 6  provides the low level of the second reference signal terminal VREF 2  to the second subscanning signal output terminal GOUT 2 _ 2 , so as to output a low-level scanning signal gout 2 _ 2 . 
     After the reset period T 3 , INPUT is equal to 0, and RE is equal to 0. Only the third transistor M 3 , the fourth transistor M 4 , and the first capacitor C 1  in the first subscanning signal output circuit  41 _ 2 , and the fifth transistor M 5 , the sixth transistor M 6 , and the second capacitor C 2  in the second subscanning signal output circuit  42 _ 2  are described below. The third transistor M 3  and the fifth transistor M 5  are both turned off, and the fourth transistor M 4  and the sixth transistor M 6  are both turned on. The turned-on fourth transistor M 4  provides the low level of the second reference signal terminal VREF 2  to the first subscanning signal output terminal GOUT 1 _ 2 , so as to output a low-level scanning signal gout 1 _ 2 . The turned-on sixth transistor M 6  provides the low level of the second reference signal terminal VREF 2  to the second subscanning signal output terminal GOUT 2 _ 2 , so as to output a low-level scanning signal gout 2 _ 2 . 
     In this way, the first subscanning signal output circuit  41 _ 1  and the first subscanning signal output circuit  41 _ 2  may output scanning signals having same timing and waveforms, and may input the two scanning signals into a same gate line in one row to improve the driving capacity. In the similar way, the second subscanning signal output circuit  42 _ 1  and the second subscanning signal output circuit  42 _ 2  may output scanning signals having same timing and waveforms, and may input the two scanning signals into a same gate line in a next row to improve the driving capacity. 
     Embodiment III 
     The same parts of a shift register provided by Embodiment III of the present disclosure as those of the shift register provided by Embodiment II are not repeated herein, and only the different parts will be described below. 
     During specific implementation, two scanning signal output circuits are provided. In the embodiment of the present disclosure, as shown in  FIG. 9 , the reset circuit  12  may further include: a fourteenth transistor M 14 , wherein the first electrode of the tenth transistor M 10  and the first electrode of the eleventh transistor M 11  respectively receive the signal of the third reference signal terminal VREF 3  through the fourteenth transistor M 14 . A gate of the fourteenth transistor M 14  is configured to receive a reset signal RE, a first electrode of the fourteenth transistor M 14  is configured to receive the signal of the third reference signal terminal VREF 3 , a second electrode of the fourteenth transistor M 14  is coupled to the first electrode of the tenth transistor M 10  and the first electrode of the eleventh transistor M 11 , respectively. The fourteenth transistor M 14  is turned on under control of a high-level signal of a reset signal terminal RE, to provide the signal of the third reference signal terminal VREF 3  to the first electrode of the tenth transistor M 10  and the first electrode of the eleventh transistor M 11 , respectively. In this way, the influence on the tenth transistor M 10  and the eleventh transistor M 11  caused by varying of the signal of the third reference signal terminal VREF 3  may be avoided, and the circuit stability is improved. 
     During specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 9 , the node control circuit  13  further includes: a fifteenth transistor M 15 , wherein the first electrode of the twelfth transistor M 12  and the first electrode of the thirteenth transistor M 13  respectively receive the signal of the third reference signal terminal VREF 3  through the fifteenth transistor M 15 . A gate of the fifteenth transistor M 15  is coupled to the second node PD, a first electrode of the fifteenth transistor M 15  is configured to receive the signal of the third reference signal terminal VREF 3 , and a second electrode of the fifteenth transistor M 15  is coupled to the first electrode of the twelfth transistor M 12  and the first electrode of the thirteenth transistor M 13 , respectively. The fifteenth transistor M 15  is turned on under control of a high-level signal of the second node PD, to provide the signal of the third reference signal terminal VREF 3  to the first electrode of the twelfth transistor M 12  and the first electrode of the thirteenth transistor M 13 , respectively. In this way, the influence on the twelfth transistor M 12  and the thirteenth transistor M 13  caused by varying of the signal of the third reference signal terminal VREF 3  may be avoided, and the circuit stability is improved. 
     Generally, in an organic light-emitting diode (OLED) display device, a pixel circuit in a 3T1C form shown in  FIG. 10  is adopted to drive an OLED to emit light, and to perform external threshold compensation on the OLED. The pixel circuit includes: a driving transistor T 01 , transistors T 02 -T 03 , and a storage capacitor Cst. The pixel circuit controls the transistor T 02  to be turned on to write data voltage of a data signal terminal Data into a gate of the driving transistor T 01 , and controls the driving transistor T 01  to generate working current to drive an OLED L to emit light. A signal carrying threshold voltage information of the driving transistor T 01  is output by the transistor T 03  through a detection line SL. In this way, one row of pixel circuits need to correspond to two gate lines, so as to respectively input signals G 01  and G 02 . In order to control the above pixel circuit, during specific implementation, in the embodiment of the present disclosure, as shown in  FIG. 9 , the shift register may further include: a detection circuit  50 . The detection circuit  50  may include: a sixteenth transistor M 16 , a seventeenth transistor M 17 , an eighteenth transistor M 18 , a nineteenth transistor M 19 , a twentieth transistor M 20 , and a fourth capacitor C 4 . A gate of the sixteenth transistor M 16  is configured to receive a signal of a first detection control signal terminal VC 1 , a first electrode of the sixteenth transistor M 16  is configured to receive the signal of the input signal terminal INPUT, and a second electrode of the sixteenth transistor M 16  is coupled to a first electrode of the eighteenth transistor M 18 . A gate of the seventeenth transistor M 17  is configured to receive the signal of the first detection control signal terminal VC 1 , a first electrode of the seventeenth transistor M 17  is coupled to a gate of the nineteenth transistor M 19 , and a second electrode of the seventeenth transistor M 17  is coupled to the first electrode of the eighteenth transistor M 18 . A gate of the eighteenth transistor M 18  is coupled to the gate of the nineteenth transistor M 19 , and a second electrode of the eighteenth transistor M 18  is configured to receive a signal of a fourth reference signal terminal VREF 4 . A first electrode of the nineteenth transistor M 19  is configured to receive the signal of the fourth reference signal terminal VREF 4 , and a second electrode of the nineteenth transistor M 19  is coupled to a first electrode of the twentieth transistor M 20 . A gate of the twentieth transistor M 20  is configured to receive a signal of a second detection control signal VC 2 , and a second electrode of the twentieth transistor M 20  is coupled to the first node PU. The fourth capacitor C 4  is coupled between the first electrode of the nineteenth transistor M 19  and the gate of the nineteenth transistor M 19 . Specifically, the sixteenth transistor M 16  may be turned on under control of the first detection control signal terminal VC 1 , so as to provide the signal of the input signal terminal INPUT to the first electrode of the eighteenth transistor M 18  and the second electrode of the seventeenth transistor M 17 . The seventeenth transistor M 17  may be turned on under control of the first detection control signal terminal VC 1 , so as to provide a signal of the second electrode of the seventeenth transistor M 17  to the gate of the nineteenth transistor M 19  and the gate of the eighteenth transistor M 18 . The eighteenth transistor M 18  may be turned on under control of a signal of the gate of the eighteenth transistor M 18 . The nineteenth transistor M 19  may be turned on under control of a signal of the gate of the nineteenth transistor M 19 , so as to provide the signal of the fourth reference signal terminal VREF 4  to the first electrode of the twentieth transistor M 20 . The twentieth transistor M 20  may be turned on under control of the second detection control signal terminal VC 2 , so as to provide a signal of the first electrode of the twentieth transistor M 20  to the first node PU. 
     During specific implementation, a high-level signal may be loaded to the fourth reference signal terminal. Further, the voltage value of the fourth reference signal terminal may be equal to the voltage value of the first reference signal terminal. In order to reduce the number of signal terminals and reduce spaces occupied by signal lines, the fourth reference signal terminal and the first reference signal terminal may be set to have a same signal, that is, a same reference signal terminal is used to provide the signals of the fourth reference signal terminal and the first reference signal terminal. 
     The working process of the above shift register provided by the present embodiment is described below in combination with a circuit timing diagram shown in  FIG. 11 . Specifically, one frame period is divided into a display scanning period DP and a blanking time period BT. Signal timings of the first clock signal terminals CLK 1 _ n  in the display scanning period DP are the same, and signal timings of the first clock signal terminals CLK 1 _ n  in the blanking time period BT are different. In the similar way, signal timings of the second clock signal terminals CLK 2 _ n  in the display scanning period DP are the same, and signal timings of the second clock signal terminals CLK 2 _ n  in the blanking time period BT are different. 
     Specifically, the display scanning period DP includes: an input period T 1 , an output period T 2 , and a reset period T 3 . In the input period T 1 , INPUT is equal to 1, CLK 1 _ 1  is equal to 0, CLK 1 _ 2  is equal to 0, CLK 2 _ 1  is equal to 0, CLK 2 _ 2  is equal to 0, CLK 3  is equal to 0, RE is equal to 0, VC 1  is equal to 1, and VC 2  is equal to 0. Since RE is equal to 0, so that the fourteenth transistor M 14  is turned off. Since the signal of the second node PD is a low-level signal, the fifteenth transistor M 15  is turned off. Since VC 1  is equal to 1, the sixteenth transistor M 16  and the seventeenth transistor M 17  are both turned on, to provide the high-level signal of the input signal terminal INPUT to the gate of the nineteenth transistor M 19 , and the fourth capacitor C 4  maintains the high-level signal, and controls the nineteenth transistor M 19  to be turned on, so as to provide the high level of the fourth reference signal terminal VREF 4  to the twentieth transistor M 20 . However, since VC 2  is equal to 0, the twentieth transistor M 20  is turned off, thereby not affecting the signal of the first node PU. The rest working process of the input period may be basically the same as the working process of the input period T 1  in Embodiment II, and no more details are described herein. Furthermore, the working processes of the output period T 2  and the reset period T 3  in Embodiment III may be basically the same as the working processes of the output period T 2  and the reset period T 3  in Embodiment II, and no more details are described herein. 
     The blanking time period BT may include: a detection input period T 4 , a detection output period T 5 , and a detection reset period T 6 . At the blanking time period BT, low-level signals are applied to the input signal terminal INPUT, the reset signal RE, the second clock signal terminals CLK 2 _ 1 -CLK 2 _ 2 , the third clock signal terminal CLK 3 , and the first to fourth reference signal terminals VREF 4 . 
     In the detection input period T 4 , VC 1  is equal to 0, VC 2  is equal to 1, CLK 1 _ 1  is equal to 0, and CLK 1 _ 2  is equal to 0. Since VC 1  is equal to 0, the sixteenth transistor M 16  and the seventeenth transistor M 17  are both turned off. Under the action of the fourth capacitor C 4 , the gate of the nineteenth transistor M 19  is a high-level signal, so as to control the nineteenth transistor M 19  to be turned on. Since VC 2  is equal to 1, the twentieth transistor M 20  is turned on, so as to provide the high level of the fourth reference signal terminal VREF 4  to the first node PU. Since the signal of the first node PU is the high-level signal, the seventh transistor M 7  is turned on, and enables the signal of the second node PD to be a low-level signal under the action of the inverter ND. Therefore, the fourth transistor M 4 , the sixth transistor M 6 , the eighth transistor M 8 , the twelfth transistor M 12 , and the thirteenth transistor M 13  are controlled to be turned off. The turned-on seventh transistor M 7  provides the low level of the third clock signal terminal CLK 3  to the cascade signal output terminal CROUT, so as to output a low-level cascade signal CR. Since the first transistor M 1  and the second transistor M 2  form a diode connection structure, the signals of the output control nodes PO_ 1  and PO_ 2  are also high-level signals. The signal of the output control node PO_ 1  is the high-level signal, so that the two third transistors M 3  are both turned on. The third transistor M 3  in the first subscanning signal output circuit  41 _ 1  provides the signal of the first clock signal terminal CLK 1 _ 1  to the first subscanning signal output terminal GOUT 1 _ 1  to output a low-level scanning signal gout 1 _ 1 . The third transistor M 3  in the first subscanning signal output circuit  41 _ 2  provides the signal of the first clock signal terminal CLK 1 _ 2  to the first subscanning signal output terminal GOUT 1 _ 2  to output a low-level scanning signal gout 1 _ 2 . The signal of the output control node PO_ 2  is the high-level signal, so that the two fifth transistors M 5  are both turned on. The fifth transistor M 5  in the second subscanning signal output circuit  42 _ 1  provides the signal of the second clock signal terminal CLK 2 _ 1  to the second subscanning signal output terminal GOUT 2 _ 1  to output a low-level scanning signal gout 2 _ 1 . The fifth transistor M 5  in the second subscanning signal output circuit  42 _ 2  provides the signal of the second clock signal terminal CLK 2 _ 2  to the second subscanning signal output terminal GOUT 2 _ 2  to output a low-level scanning signal gout 2 _ 2 . 
     In the detection output period T 5 , VC 1  is equal to 0, VC 2  is equal to 0, the first clock signal terminal CLK_ 1  has two high-level pulses, and the first clock signal terminal CLK 1 _ 2  has one high-level pulse. Specifically, under the action of the first capacitor C 1 , the signal of the output control node PO_ 1  is the high-level signal, so that the two third transistors M 3  are both turned on. The third transistor M 3  in the first subscanning signal output circuit  41 _ 1  provides the signal of the first clock signal terminal CLK 1 _ 1  to the first subscanning signal output terminal GOUT 1 _ 1  to output a scanning signal gout 1 _ 1  having two high-level pulses. The third transistor M 3  in the first subscanning signal output circuit  41 _ 2  provides the signal of the first clock signal terminal CLK 1 _ 2  to the first subscanning signal output terminal GOUT 1 _ 2  to output a scanning signal gout 1 _ 2  having one high-level pulse. Under the action of the second capacitor C 2 , the signal of the output control node PO_ 2  is maintained to be the high-level signal, so that the two fifth transistors M 5  are both turned on. The fifth transistor M 5  in the second subscanning signal output circuit  42 _ 1  provides the signal of the second clock signal terminal CLK 2 _ 1  to the second subscanning signal output terminal GOUT 2 _ 1  to output a low-level scanning signal gout 2 _ 1 . The fifth transistor M 5  in the second subscanning signal output circuit  42 _ 2  provides the signal of the second clock signal terminal CLK 2 _ 2  to the second subscanning signal output terminal GOUT 2 _ 2  to output a low-level scanning signal gout 2 _ 2 . 
     In the detection reset period T 6 , VC 1  is equal to 1, VC 2  is equal to 0, CLK 1 _ 1  is equal to 0, and CLK 1 _ 2  is equal to 0. 
     Since VC 2  is equal to 0, the twentieth transistor M 20  is turned off. Since VC 1  is equal to 1, the sixteenth transistor M 16  and the seventeenth transistor M 17  are turned on, so as to provide the low level of the input signal terminal INPUT to the gate of the nineteenth transistor M 19  to control the nineteenth transistor M 19  to be turned off. Under the action of the first capacitor C 1 , the signal of the output control node PO_ 1  is maintained to be the high-level signal, so that the two third transistors M 3  are both turned on. The third transistor M 3  in the first subscanning signal output circuit  41 _ 1  provides the low level of the first clock signal terminal CLK 1 _ 1  to the first subscanning signal output terminal GOUT 1 _ 1  to output a low-level scanning signal gout 1 _ 1 . The third transistor M 3  in the first subscanning signal output circuit  41 _ 2  provides the low level of the first clock signal terminal CLK 1 _ 2  to the first subscanning signal output terminal GOUT 1 _ 2  to output a low-level scanning signal gout 1 _ 2 . Under the action of the second capacitor C 2 , the signal of the output control node PO_ 2  is maintained to be the high-level signal, so that the two fifth transistors M 5  are both turned on. The fifth transistor M 5  in the second subscanning signal output circuit  42 _ 1  provides the signal of the second clock signal terminal CLK 2 _ 1  to the second subscanning signal output terminal GOUT 2 _ 1  to output a low-level scanning signal gout 2 _ 1 . The fifth transistor M 5  in the second subscanning signal output circuit  42 _ 2  provides the signal of the second clock signal terminal CLK 2 _ 2  to the second subscanning signal output terminal GOUT 2 _ 2  to output a low-level scanning signal gout 2 _ 2 . 
     Generally, in the blanking time period, the OLED is subjected to external compensation detection. In this way, the signals G 01  and G 02  are input into two gate lines in one row respectively through the scanning signals gout 1 _ 1  and gout 1 _ 2  output by the shift register in Embodiment III, so that the OLED in the row is controlled to realize a display function at the display scanning period in one frame, and is controlled to realize an external compensation detection function at the blanking time period BT. Furthermore, the signals G 01  and G 02  are input into two gate lines in a next row respectively through the scanning signals gout 2 _ 1  and gout 2 _ 2 , so as to meet the requirements of OLED displaying. 
     Embodiment IV 
     The same parts of a shift register provided by Embodiment IV of the present disclosure as those of the shift register provided by Embodiment III are not repeated herein, and only the different parts will be described below. 
     During specific implementation, two scanning signal output circuits are provided. In the embodiment of the present disclosure, as shown in  FIG. 12 , the branch control circuit  20  may include: a first transistor M 1  and a second transistor M 2 , wherein a gate of the first transistor M 1  is configured to receive the signal of the first reference signal terminal VREF 1 , a first electrode of the first transistor M 1  is coupled to the first node PU, a second electrode of the first transistor M 1  is coupled to the output control node PO_ 1  corresponding to the first scanning signal output circuit. A gate of the second transistor M 2  is configured to receive the signal of the first reference signal terminal VREF 1 , a first electrode of the second transistor M 2  is coupled to the first node PU, and a second electrode of the second transistor M 2  is coupled to the output control node PO_ 2  corresponding to the second scanning signal output circuit. 
     During specific implementation, the first reference signal terminal is a high-level signal in the display scanning period DP and the blanking time period BT. Furthermore, the voltage value of the first reference signal terminal is the same as the voltage value of the first clock signal terminal and the voltage value of the second clock signal terminal. In this way, in the input period T 1 , when the first node PU is the high-level signal, the voltage value of the gate of the first transistor M 1  is the same as the voltage value of the first electrode of the first transistor M 1 , being equivalent to forming a diode connection structure, and the voltage value of the gate of the second transistor M 2  is the same as the voltage value of the first electrode of the second transistor M 2 , being equivalent to forming a diode connection structure. The rest working process of the input period may be basically the same as the working process of the input period T 1  in Embodiment III, and no more details are described herein. 
     In the output period T 2 , since the output control signals PO_ 1 -PO_ 2  are further pulled up, gate-source voltages of the first transistor M 1  and the second transistor M 2  are higher, which causes the first transistor M 1  and the second transistor M 2  to be turned off, and thus, the further pulled-up output control signals PO_ 1 -PO_ 2  can not affect each other through the first node PU, and further, the circuit stability is improved. The rest working process of the output period may be basically the same as the working process of the output period T 2  in Embodiment III, and no more details are described herein. 
     In the reset period T 3 , the first transistor M 1  and the second transistor M 2  are turned on all the time. The rest working process of the reset period may be basically the same as the working process of the reset period T 3  in Embodiment III, and no more details are described herein. 
     In the detection input period T 4 , the detection output period T 5 , and the detection reset period T 6 , the first transistor M 1  and the second transistor M 2  are turned on all the time. The rest working processes of the detection input period T 4 , the detection output period T 5 , and the detection reset period T 6  may be basically the same as the working processes of the detection input period T 4 , the detection output period T 5 , and the detection reset period T 6  in Embodiment III, and no more details are described herein. 
     Based on the same inventive concept, an embodiment of the present disclosure further provides a driving method of the shift register provided by the embodiment of the present disclosure. The driving method drives the shift register according to the embodiment of the present disclosure, so that the shift register may output a plurality of different scanning signals. Furthermore, the implementation of the driving method may refer to the implementation of the above shift register, and repeated parts are not described herein. 
     During specific implementation, in the embodiment of the present disclosure, a display scanning period may include: an input period, an output period, and a reset period. Specifically, as shown in  FIG. 13 , the driving method may include the following steps. 
     S 1301 , in the input period, the signal control circuit controls the signal of the first node and a signal of the second node in response to the signal of the input signal terminal; the branch control circuit controls signals of output control nodes which one-to-one correspond to scanning signal output circuits in response to the signal of the first node; the cascade signal output circuit outputs the cascade signal in response to the signal of the first node; and the scanning signal output circuits output different scanning signals in response to the signals of the corresponding output control nodes. 
     S 1302 , in the output period, the branch control circuit controls the signals of the output control nodes which one-to-one correspond to the scanning signal output circuits in response to the signal of the first node; the cascade signal output circuit outputs the cascade signal in response to the signal of the first node; and the scanning signal output circuits output different scanning signals in response to the signals of the corresponding output control nodes. 
     S 1303 , in the reset period, the signal control circuit controls the signal of the first node and the signal of the second node in response to the reset signal; the cascade signal output circuit outputs the cascade signal in response to the signal of the first node; and the scanning signal output circuits output different scanning signals in response to the signals of the corresponding output control nodes. 
     During specific implementation, two scanning signal output circuits are provided. A first scanning signal output circuit in the two scanning signal output circuits includes a plurality of first subscanning signal output circuits, and the second scanning signal output circuit in the two scanning signal output circuits includes a plurality of second subscanning signal output circuits. It should be noted that the specific description of the part refers to Embodiment I, and no more details are described herein. 
     In the embodiment of the present disclosure, in the input period and the output period, each first subscanning signal output circuit provides a corresponding first clock signal to a corresponding first subscanning signal output terminal in response to the signal of the corresponding output control node; each second subscanning signal output circuit provides a corresponding second clock signal to a corresponding second subscanning signal output terminal in response to the signal of the corresponding output control node; and the cascade signal output circuit provides a third clock signal to a cascade signal output terminal in response to the signal of the first node. 
     In the reset period, each first subscanning signal output circuit provides a second reference signal to the corresponding first subscanning signal output terminal in response to the signal of the second node; each second subscanning signal output circuit provides the second reference signal to the corresponding second subscanning signal output terminal in response to the signal of the second node; and the cascade signal output circuit provides a third reference signal to the cascade signal output terminal in response to the signal of the second node. 
     In the embodiment of the present disclosure, in the display scanning period, signal timing of the first clock signal terminals are the same, signal timings of the various second clock signal terminals are the same, and the signal timings of the first clock signal terminals and the signal timings of the second clock signal terminals are different. 
     In the embodiment of the present disclosure, signal cycles of the first clock signal terminal, the second clock signal terminal and third clock signal terminal are the same. Furthermore, in the same cycle, the signal rising edge of the third clock signal terminal appears before the signal rising edge of the second clock signal terminal, and the signal falling edge of the third clock signal terminal appears after the signal falling edge of the first clock signal terminal. For example, as shown in  FIG. 5 ,  FIG. 8  and  FIG. 11 , the signal rising edge of the third clock signal terminal CLK 3  is aligned with the rising edge of the first clock signal terminal CLK 1 _ n , and the signal falling edge of the third clock signal terminal CLK 3  is aligned with the signal falling edge of the second clock signal terminal CLK 2 _ k.    
     Further, during specific implementation, the shift register further includes a detection circuit. In this way, the shift register may be applied to an organic light-emitting diode (OLED) display device. In the embodiment of the present disclosure, the driving method may further include: a blanking time period. The blanking time period may include: a detection input period, a detection output period, and a detection reset period. The working processes of the detection circuit in these periods refer to Embodiment III, and no more details are described herein. 
     Based on the same inventive concept, an embodiment of the present disclosure further provides a gate driving circuit, as shown in  FIG. 14 a    and  FIG. 14 b   , including a plurality of the cascaded shift registers according to the embodiments of the present disclosure: SR(n−2), SR(n−1), SR(n), SR(n+1) and SR(n+2) (N shift registers in total, n being an integer more than or equal to 1 and less than or equal to N). 
     An input signal of a first-stage shift register is input through a frame start signal terminal. 
     In every four adjacent stages of shift registers, an input signal INPUT of a fourth-stage shift register SR(n+1) is input by a cascade signal CR of the first-stage shift register SR(n−2). 
     In every five adjacent stages of shift registers, a reset signal RE of the first-stage shift register SR(n−2) is input by a cascade signal CR of a fifth-stage shift register SR(n+2). 
     It should be noted that  FIG. 14 a    illustrates a structure of the shift register by taking the structure shown in  FIG. 4  as an example.  FIG. 14 b    illustrates a structure of the shift register by taking the structure shown in  FIG. 9  as an example. 
     During specific implementation, when the structure of the shift register uses the structure shown in  FIG. 4 , a first clock signal terminal CLK 1 _ 1  of a (5y-4)th-stage shift register is provided by a same clock signal line clk 1 _ 1 , a second clock signal terminal CLK 2 _ 1  of the (5y-4)th-stage shift register is provided by a same clock signal line clk 2 _ 1 , and a third clock signal terminal CLK 3  of the (5y-4)th-stage shift register is provided by a same clock signal line clk 3 _ 1 . A first clock signal terminal CLK 1 _ 1  of a (5y-3)th-stage shift register is provided by a same clock signal line clk 1 _ 2 , a second clock signal terminal CLK 2 _ 1  of the (5y-3)th-stage shift register is provided by a same clock signal line clk 2 _ 2 , and a third clock signal terminal CLK 3  of the (5y-3)th-stage shift register is provided by a same clock signal line clk 3 _ 2 . A first clock signal terminal CLK 1 _ 1  of a (5y-2)th-stage shift register is provided by a same clock signal line clk 1 _ 3 , a second clock signal terminal CLK 2 _ 1  of the (5y-2)th-stage shift register is provided by a same clock signal line clk 2 _ 3 , and a third clock signal terminal CLK 3  of the (5y-2)th-stage shift register is provided by a same clock signal line clk 3 _ 3 . A first clock signal terminal CLK 1 _ 1  of a (5y−1)th-stage shift register is provided by a same clock signal line clk 1 _ 4 , a second clock signal terminal CLK 2 _ 1  of the (5y−1)th-stage shift register is provided by a same clock signal line clk 2 _ 4 , and a third clock signal terminal CLK 3  of the (5y−1)th-stage shift register is provided by a same clock signal line clk 3 _ 4 . A first clock signal terminal CLK 1 _ 1  of a (5y)th-stage shift register is provided by a same clock signal line clk 1 _ 5 , a second clock signal terminal CLK 2 _ 1  of the (5y)th-stage shift register is provided by a same clock signal line clk 2 _ 5 , and a third clock signal terminal CLK 3  of the (5y)th-stage shift register is provided by a same clock signal line clk 3 _ 5 , and k is a positive integer. 
     During specific implementation, when the structure of the shift register uses the structure shown in  FIG. 9 , the first clock signal terminal CLK 1 _ 1  of the (5y−4)th-stage shift register is provided by a same clock signal line clk 1 _ 11 , a first clock signal terminal CLK 1 _ 2  of the (5y−4)th-stage shift register is provided by a same clock signal line clk 1 _ 21 , the second clock signal terminal CLK 2 _ 1  of the (5y−4)th-stage shift register is provided by a same clock signal line clk 2 _ 11 , a second clock signal terminal CLK 2 _ 2  of the (5y−4)th-stage shift register is provided by a same clock signal line clk 2 _ 21 , and the third clock signal terminal CLK 3  of the (5y−4)th-stage shift register is provided by a same clock signal line clk 3 _ 1 . The first clock signal terminal CLK 1 _ 1  of the (5y−3)th-stage shift register is provided by a same clock signal line clk 1 _ 12 , a first clock signal terminal CLK 1 _ 2  of the (5y−3)th-stage shift register is provided by a same clock signal line clk 1 _ 22 , the second clock signal terminal CLK 2 _ 1  of the (5y−3)th-stage shift register is provided by a same clock signal line clk 2 _ 12 , a second clock signal terminal CLK 2 _ 2  of the (5y−3)th-stage shift register is provided by a same clock signal line clk 2 _ 22 , and the third clock signal terminal CLK 3  of the (5y−3)th-stage shift register is provided by a same clock signal line clk 3 _ 2 . The first clock signal terminal CLK 1 _ 1  of the (5y−2)th-stage shift register is provided by a same clock signal line clk 1 _ 13 , a first clock signal terminal CLK 1 _ 2  of the (5y−2)th-stage shift register is provided by a same clock signal line clk 1 _ 23 , the second clock signal terminal CLK 2 _ 1  of the (5y−2)th-stage shift register is provided by a same clock signal line clk 2 _ 13 , a second clock signal terminal CLK 2 _ 2  of the (5y−2)th-stage shift register is provided by a same clock signal line clk 2 _ 23 , and the third clock signal terminal CLK 3  of the (5y−2)th-stage shift register is provided by a same clock signal line clk 3 _ 3 . The first clock signal terminal CLK 1 _ 1  of the (5y−1)th-stage shift register is provided by a same clock signal line clk 1 _ 14 , a first clock signal terminal CLK 1 _ 2  of the (5y−1)th-stage shift register is provided by a same clock signal line clk 1 _ 24 , the second clock signal terminal CLK 2 _ 1  of the (5y−1)th-stage shift register is provided by a same clock signal line clk 2 _ 14 , a second clock signal terminal CLK 2 _ 2  of the (5y−1)th-stage shift register is provided by a same clock signal line clk 2 _ 24 , and the third clock signal terminal CLK 3  of the (5y−1)th-stage shift register is provided by a same clock signal line clk 3 _ 4 . The first clock signal terminal CLK 1 _ 1  of the 5yth-stage shift register is provided by a same clock signal line clk 1 _ 15 , a first clock signal terminal CLK 1 _ 2  of the (5y)th-stage shift register is provided by a same clock signal line clk 1 _ 25 , the second clock signal terminal CLK 2 _ 1  of the (5y)th-stage shift register is provided by a same clock signal line clk 2 _ 15 , a second clock signal terminal CLK 2 _ 2  of the (5y)th-stage shift register is provided by a same clock signal line clk 2 _ 25 , and the third clock signal terminal CLK 3  of the (5y)th-stage shift register is provided by a same clock signal line clk 3 _ 5 , and k is a positive integer. 
     During specific implementation, first detection control signals of the various stages of shift registers are a same signal, to control the various stages of shift registers within one frame period. Second detection control signals of the various stages of shift registers are different. Within one frame period, the second detection control signal of only one stage of shift register has a high-level pulse signal, so that the stage of shift register outputs scanning signals gout 1 _ 1 , gout 1 _ 2 , gout 2 _ 1  and gout 2 _ 2  shown in  FIG. 11  at the blanking time period. The residual shift registers output low-level signals at the blanking time period. 
     Specifically, the specific structure of each shift register in the above gate driving circuit is the same as the above shift register of the present disclosure in function and structure, and repeated parts are not described. 
     Based on the same inventive concept, an embodiment of the present disclosure further provides an array substrate including the above gate driving circuit according to the embodiment of the present disclosure. The principle of the array substrate for solving problems is similar to that of the above gate driving circuit, so that the implementation of the array substrate may refer to the implementation of the above gate driving circuit, and repeated parts are not described herein. 
     The above array substrate provided by the embodiment of the present disclosure includes the above gate driving circuit, and the various stages of shift registers in the gate driving circuit provide scanning signals to the gate lines on the array substrate. The specific implementation may refer to the description of the above shift register, and the same parts are not described. 
     Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, including the above array substrate according to the embodiment of the present disclosure. The display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame and a navigator. Other indispensable components of the display device should be understood by those skilled in the art, are not described repeatedly herein, and should not limit the present disclosure. The implementation of the display device may refer to the embodiment of the above array substrate, and repeated parts are not described. 
     According to the shift register and the driving method thereof, the gate driving circuit, the array substrate and the display device which are provided by the embodiments of the present disclosure, the signal control circuit controls the signal of the first node and the signal of the second node in response to the signals of the input signal terminal and the reset signal terminal. The branch control circuit is configured to control the signals of the output control nodes one-to-one correspondence to the scanning signal output circuits in response to the signal of the first node, and the different output control nodes may be separated, so that the variation of the signal of one output control node may not affect the signals of other output control nodes. The cascade signal output circuit outputs the cascade signal in response to the signals of the first node and the second node to provide an input signal to the next-stage shift register. A plurality of scanning signal output circuits are arranged, the scanning signal output circuits output different scanning signals in response to the signals of the corresponding output control nodes and the signal of the second node. In this way, each shift register may output a plurality of scanning signals which correspond to different gate lines in the array substrate. Compared with the shift register in the related art, which may only output one scanning signal, the shift register has the advantages that the number of the shift registers in the gate driving circuit may be reduced, the occupation space of the gate driving circuit is reduced, and an ultra-narrow-bezel design is realized. Furthermore, the signals of different output control nodes do not affect each other, so that the stability of the waveforms of the output scanning signals may also be improved, and a difference in the waveforms of the scanning signals is avoided. 
     Evidently those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus the invention is also intended to encompass these modifications and variations therein as long as these modifications and variations come into the scope of the claims of the invention and their equivalents.