Patent Publication Number: US-6212365-B1

Title: Push-to-talk interface circuit for a radio communication system

Description:
FIELD OF THE INVENTION 
     This invention relates generally to interface circuits for communication systems and, more particularly to an interface circuit for a push-to-talk radio having a single transistor and a minimal number of components for providing an indication to the radio to initiate transmission. 
     BACKGROUND OF THE INVENTION 
     Devices such as tactical radios often use an indicator signal to command the radio to begin transmission. The most common method of accomplishing this command is to provide a mechanical switch on the radio&#39;s handset. This switch provides an electrical signal to the radio to begin transmission. In other applications, this Push-to-Talk (PTT) signal is generated either electronically or electromechanically (via a relay). 
     The normal signaling protocol is for a closure to ground (zero volts) to command ‘transmit’. The command “don&#39;t transmit” is exemplified by an open circuit or via a high potential voltage or low voltage across the terminals of a circuit. 
     Due to the nature of how PTT signals are generated, with mechanical switches and electromechanical relays, there is often significant noise and high-voltage ringing present on PTT lines. In some applications, significant Lengths of cable are present on the PTT line providing additional opportunity for high voltage transients and noise to infiltrate the PTT interface. 
     Previous designs of PTT interfaces have used circuits with high cost components or large numbers of components. FIG. 3 shows the traditional design used in the present production of a push-to-talk SINCGARS radio. As shown in FIG. 3, such design requires 2 transistors (Q 1 ,Q 2 )and 13 total components including a power supply. FIG. 4 shows another prior art implementation of a PTT interface. This design, while requiring only nine components, however, further includes a costly differential amplifier  100  and also requires both a positive supply V 2  and negative supply voltage V 3  to operate. The high component count, high cost, and the need for negative supply voltages associated with prior art PTT interface circuits make it extremely desirable to obtain a low cost, low power interface circuit which is operable with a minimal number of components. 
     As can be seen in FIG. 1, the design according to the present invention overcomes these shortcomings by the judicious use of a single, low cost field effect transistor. Current routing with diodes precludes the need for a negative supply voltage. 
     SUMMARY OF THE INVENTION 
     A circuit for selectively enabling communications by providing an output signal voltage of a first level indicative of a first transmission state and a second level corresponding to a second non-transmission state, the circuit comprising an FET having a gate, source, and drain, the source coupled to a first controlling means for providing a voltage Vs to the source, the drain coupled to an output terminal of the circuit for providing the output signal, and the gate coupled to a second control means for providing a voltage Vg to the gate, the FET operable in a first conducting mode when a gate to source voltage Vgs exceeds a predetermined threshold, indicative of a non-zero crossing amplitude region of an input voltage signal, to cause the output signal voltage to be at the second level corresponding to the non-transmission state, and in a second non-conducting mode, wherein the Vgs of the FET is less than the threshold, indicative of a zero-crossing of the input signal, for causing the output signal voltage to go to the first level, indicative of the transmission state, wherein the first and second control means responsive to the input voltage signal operate to vary the FET gate to source voltage and route current through the circuit to cause the FET to operate in the conducting and non-conducting modes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which: 
     FIG. 1 is a schematic illustration of the push-to-talk interface circuit according to the present invention. 
     FIG. 2 is a graphical representation of the output voltage signal in response to input voltage conditions as a function of time in the embodiment of FIG.  1 . 
     FIG. 3 is a prior art schematic of a push-to-talk circuit. 
     FIG. 4 is a second prior art schematic of a push-to-talk circuit. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to FIG. 1, there is shown a particular embodiment of the push-to-talk (PTT) interface circuit  10  according to the present invention. In FIG. 1, input voltage generator V 1  and switch  90  represent the mechanism generating the PTT input  20 . Such input may be implemented via a mechanical switch, an electromechanical relay or a semiconductor device, for example. The output of the circuit is represented by reference numeral  30 . Using conventional signaling protocol, below are listed the possible input conditions at terminal  20  and desired output conditions at terminal  30 : 
     
       
         
           
               
               
               
             
               
                   
                   
               
               
                   
                 Input Condition 
                 Desired Output Condition 
               
               
                   
                   
               
             
            
               
                   
                 high positive voltage 
                 inactive (low voltage level) 
               
               
                   
                 high negative voltage 
                 inactive (low voltage level) 
               
               
                   
                 open circuit 
                 inactive (low voltage level) 
               
               
                   
                 ground (zero volts) 
                 active (high voltage level) 
               
               
                   
                   
               
            
           
         
       
     
     As shown in FIG. 1, a first resistor R 1  is coupled at a first terminal  15  to the source electrode of MOSFET M 1  and to the anode of diode D 1 , and at a second terminal  25  to the input terminal  20 . The gate (G) electrode of MOSFET M 1  is coupled at node  40  to a first terminal of resistor R 3  and to the cathode electrode of a diode D 2  positioned in a reverse bias orientation and having the anode electrode coupled to ground potential  50 . The drain (D) electrode of MOSFET M 1  is coupled to the output terminal  30  and to the cathode of clamping diode D 4  which has its anode connected to ground  50 . Pull-up resistor R 4  is connected to the positive terminal of a power supply and operates, as will be described later, for pulling the output signal level at terminal  30  to a high voltage level corresponding to the power supply voltage V 2 . Resistor R 2  is coupled between the positive terminal of the power supply V 2  and the input terminal  20  via node  35 . Resistor R 2 , for the case of an open circuit applied at input  20 , operates to allow current to pass through resistor R 1  and diode D 1 . Diode D 1  has the anode coupled to terminal  15  and the cathode coupled to ground. The diode D 1  provides a limiting positive voltage at the source of MOSFET M 1  when the voltage at input terminal  20  is positive, and for permitting M 1  to vary according to the input  20  when V 1  is negative. Note that while M 1  is illustrated as an n-type MOSFET, a p-type MOSFET may also be used in configuring the circuit. The diodes and voltages are adjusted accordingly. 
     The operation of circuit  10  will now be described with the various input conditions at input terminal  20  mentioned above. Note that while exemplary numerical values have been assigned to each of the electronic components, other values may be used and tailored according to the particular application. 
     Case a) In the case where switch  90  is closed and input  20  is represented by a high positive input voltage from input signal generator V 1 , current flows through resistor R 1  and diode D 1  to ground  50 . This clamps the source S of MOSFET M 1  at one diode drop or approximately 0.7 volts above ground potential. The input voltage  20  is applied to the gate of M 1  through R 3 , making the voltage level at the gate of M 1  approximately equal to the input voltage (diode D 1  is reverse biased). When the gate to source voltage of M 1  exceeds 1 to 2 volts positive, M 1  conducts making the drain of M 1  approximately 0.7 volts (source voltage). The signal at the drain of M 1  (reference numeral  30 ) is the output of the PTT circuit and may be input into standard 3.3 volt CMOS digital circuit, as indicated by module  80 . In this configuration, D 4  and D 2  are reverse biased and of no consequence in the circuit  10 . 
     Case b) In the case where switch  90  is closed and input  20  is represented by a high negative voltage input from input signal generator V 1 , the negative voltage is applied to the source of M 1  through R 1  (diode D 1  is reverse biased). This places the source of M 1  approximately at the input voltage  20 . Also, current flows through D 2  and R 3  to the input clamping the voltage at the gate (G) of M 1  to one diode drop below ground or approximately −0.7 v. When the gate to source voltage Vgs of M 1  exceeds 1 to 2 volts positive, M 1  conducts making the drain of M 1  approximately −0.7 volts. The signal at the drain D of M 1  (reference numeral  30 ) is the output of the PTT circuit and may be input into standard 3.3 volt CMOS digital circuits. In this case, diode D 1  is reverse biased and of no consequence in this condition. Diode D 4  operates to clamp the output of the circuit to one diode drop below ground or approximately −0.7 v. This is compatible with a standard 3.3 v CMOS digital circuit. 
     Case c) In the case where switch  90  is closed and input  20  is represented by an input voltage of zero volts from input signal generator V 1 , both the gate G and source S of M 1  are approximately at zero volts and M 1  is in the “off” or non-conducting state. In this case, resistor R 4  pulls the output  30  up to the V 2  supply voltage of 3.3 v, providing a logic ‘1’ output at terminal  30  (diode D 4  is reverse biased). This signal input to CMOS digital processor  80  thus operates as a signal indicator to notify the digital circuit in a push-to-talk radio, for instance, to begin transmission of communications. 
     Case d) In the case where switch  90  is open and thus, input  20  is represented by an open circuit input, resistor R 2  and R 1  provide a high positive voltage to the gate G of M 1 . Diode D 1  is forward biased through resistors R 2  and R 1 , thus providing +0.7 v to the source S of M 1 . M 1  then turns on, providing a logic ‘0’ output from the circuit at the drain D indicative of a +0.7 v output at terminal  30 . 
     FIG. 2 provides a graphical representation of the various conditions described above. These conditions were modeled and tested using Microsim version 7.1. An 8 vp-p sine wave was used as input for 1.5 msec. At that point, a switch was then opened to simulate an open circuit condition. 
     The aforementioned circuit is applicable to any situation where a mechanical or electromechanical device needs to interface to a low voltage digital logic circuit. Such applications include but are not limited to radio push to talk circuits, relay circuits, and inductive interfaces. It should be understood that a person may make many variations and modifications to the embodiments utilizing functionally equivalent elements to those described herein. Any and all such modifications as well as others which may become apparent to those skilled in the art, are intended to be included within the scope of the invention as defined by the appended claims.