Patent Publication Number: US-9425287-B2

Title: Reducing variation by using combination epitaxy growth

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a divisional of Ser. No. 13/030,850, filed on Feb. 18, 2011 entitled “Reducing Variation by Using Combination Epitaxy Growth,” which is a continuation-in-part of U.S. patent application Ser. No. 12/784,344, filed on May 20, 2010, entitled “Selective Etching in the Formation of Epitaxy Regions in MOS Devices,” which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     To enhance the performance of metal-oxide-semiconductor (MOS) devices, stress may be introduced in the channel regions of the MOS devices to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (“NMOS”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type MOS (“PMOS”) device in a source-to-drain direction. 
     A commonly used method for applying compressive stress to the channel regions of PMOS devices is growing SiGe stressors in the source and drain regions. Such a method typically includes the steps of forming a gate stack on a silicon substrate, forming spacers on sidewalls of the gate stack, forming recesses in the silicon substrate and adjacent the gate spacers, and epitaxially growing SiGe stressors in the recesses. An annealing is then performed. Since SiGe has a greater lattice constant than silicon, it expands after annealing and applies a compressive stress to the channel region of the respective MOS device, which is located between a source SiGe stressor and a drain SiGe stressor. 
     A chip may have different regions having different pattern densities. Due to the pattern loading effect, the growth of SiGe stressors in different regions may have different rates. For example,  FIG. 1  illustrates the formation of SiGe regions for PMOS devices in logic device region  300  and static random access memory (SRAM) region  400 . Since the pattern density of the PMOS devices in SRAM region  400  is generally higher than the pattern density of the PMOS devices in logic region  300 , and the sizes of SiGe regions  410  are typically smaller than the sizes of SiGe regions  310 , SiGe regions  410  are grown faster than SiGe regions  310 . As a result, height H 2 , which is the height of the portions of SiGe regions  410  over the top surface of substrate  320 , may be significantly greater than height H 1  of SiGe regions  310 . For example, height H 2  may be about 20 nm, while height H 1  may be only about 5 nm, even if SiGe regions  310  and  410  are formed simultaneously. With the great height H 2  and the small horizontal sizes, SiGe regions  410  may have pyramid top portions, with the slopes of the top portions being on (111) planes. This creates significant problems for the subsequent process steps such as the formation of source and drain silicide regions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  illustrates a cross-sectional view of an intermediate stage in the formation of a conventional integrated structure comprising PMOS devices, wherein SiGe stressors in different device regions have different heights due to the pattern-loading effect; 
         FIGS. 2 through 5A ,  FIGS. 7A through 7F , and  FIGS. 10 and 11  are cross-sectional views of intermediate stages in the manufacturing of an integrated structure in accordance with various embodiments; 
         FIG. 5B  illustrates a top view of device regions and recesses formed in the device regions; 
         FIG. 6A  illustrates growth rates of epitaxy regions as a function of E/G ratios; 
         FIG. 6B  schematically illustrates growth rates of epitaxy regions as a function of erase-to-growth (E/G) ratios, wherein the growth rates in devices regions  100  and  200  as shown in  FIG. 5B  are illustrated; 
         FIG. 8A through 8D  illustrate exemplary E/G ratios in various growth/etching stages; and 
         FIGS. 9A through 9C  illustrate the normalized growth rates in various regions. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure. 
     A novel method for forming metal-oxide-semiconductor (MOS) devices with stressed channel regions is provided. The intermediate stages of manufacturing an embodiment are illustrated. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. 
       FIG. 2  illustrates substrate  2 , which may be a portion of wafer  1  that comprises a first portion in device region  100  and a second portion in device region  200 . In an embodiment, device region  100  is a logic device region, which may be, for example, a core circuit region, an input/output (I/O) circuit region, and/or the like, while device region  200  is a memory circuit region comprising memory cells such as static random access memory (SRAM) cells. Accordingly, device region  200  may be an SRAM region in an exemplary embodiment. In alternative embodiments, device region  100  is a region with a lower density of devices (such as transistors) than device region  200 . The size of active region  101  in device region  100  may be greater than the size of active region  201  in device region  200  (please refer to  FIG. 5B ). Shallow trench isolation (STI) regions  4  are formed to isolate device regions  100  and  200 . Substrate  2  may comprise bulk semiconductor material such as silicon, or have a composite structure, such as silicon-on-insulator (SOI) structure. 
     Gate stack  102  comprising gate dielectric  104  and gate electrode  106  is formed in device region  100  and over substrate  2 . Gate stack  202  comprising gate dielectric  204  and gate electrode  206  is formed in device region  200  and over substrate  2 . Gate dielectrics  104  and  204  may comprise silicon oxide or high-k materials having high k values, for example, higher than about 7. Gate electrodes  106  and  206  may include commonly used conductive materials such as doped polysilicon, metals, metal silicides, metal nitrides, and combinations thereof. Further, dummy gate stacks  502  are formed in both device region  100  and device region  200 . Dummy gate stacks  502  include dummy gate dielectrics  504  and dummy gate electrodes  506 , wherein dummy gate electrodes  506  may be electrically floating. 
     Referring to  FIG. 3 , lightly doped drain/source (LDD) regions  110  and  210  are formed, for example, by implanting a p-type impurity. Gate stacks  102  and  202  act as masks so that the inner edges of LDD regions  110  and  210  are substantially aligned with the edges of gate stacks  102  and  202 , respectively. 
     Referring to  FIG. 4 , gate spacers  116  and  216 , and dummy gate spacers  516 , are formed. In an embodiment, each of gate spacers  116 ,  216  and  516  includes a liner oxide layer and a nitride layer over the liner oxide layer. In alternative embodiments, each of gate spacers  116 ,  216  and  516  may include one or more layers, each comprising oxide, silicon nitride, silicon oxynitride (SiON) and/or other dielectric materials, and may be formed using commonly used techniques, such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), or the like. The formation of gate spacers  116 ,  216  and  516  may include blanket forming gate spacer layers, and then performing etching steps to remove the horizontal portions of the gate spacer layers, so that the remaining vertical portions of the gate spacer layers form gate spacers  116 ,  216  and  516 . 
     Referring to  FIG. 5A , recesses  118  and  218  are formed by etching substrate  2  isotropically or anisotropically. Depth D of recesses  118  and  218  may be between about 500 Å and about 1000 Å, although different depth D may also be used. One skilled in the art will realize, however, that the dimensions recited throughout the description are merely examples, and will change if different formation technologies are used. In an embodiment, recesses  118  have a spear shape in the cross-sectional view, except the bottoms are flat. 
     In subsequent process steps, a semiconductor material, such as silicon germanium (SiGe), is epitaxially grown in recesses  118  and  218  by a selective epitaxial growth (SEG). The semiconductor material may have a greater lattice constant than silicon substrate  2 . Desired impurities may be, or may not be, doped while the epitaxial growth proceeds. After being annealed, SiGe will try to restore its lattice constant, thus introducing compressive stresses to the channel regions of the resulting PMOS devices. Throughout the description, the SiGe epitaxy regions are alternatively referred to as SiGe stressors. 
     The precursor for growing SiGe may include growth gases such as germane (GeH 4 , which provides germanium), dichloro-silane (DCS, which provides silicon), and the like. The silicon precursors may include SiH 4 , Si x H y Cl z , and/or the like. Furthermore, a carbon containing silicon-source (such as Monomethylsilane (SiCH 3 ) or SiCxH 4-x ) and/or a carbon containing germane-source (such as GeCH 3  or GeC x H 4- x) may be added. An etching gas selected from HCl, HF, Cl 2 , and combinations thereof, is introduced for removing the undesirable SiGe portions grown on dielectric materials such as gate spacers  116  and  216  and STI regions  4 . Alternatively, the etching gas comprises a gas selected from the group consisting essentially of C x F y H z , C x Cl y H z , Si x F y H z , Si x Cl y H z , with values x, y, and z represent the percentage of the respective elements. In alternative embodiments, instead of forming SiGe films/regions, the epitaxy films may be silicon films/regions doped with phosphorus or boron (Si:B/Si:P), wherein B 2 H 6  and PH 3  doping gases are used as precursors. The etching gas also has the effect of reducing pattern-loading effects. Accordingly, during the epitaxial growth, both growth and etch co-exist. In different epitaxy stages of the embodiments, the growth rate may be greater than or smaller than the etch rate, and hence the corresponding net effects may be growth or etching. In an exemplary embodiment, the selective epitaxy is performed using low pressure chemical vapor deposition (LPCVD) in a chamber, in which the total pressure of gases may be between about 1 torr and about 200 torrs, or between about 3 torrs and 50 torrs, and the temperature may be between about 400° C. and about 800° C. To determine the optimum conditions for growing SiGe, an etch-back to growth ratio (also referred to as etch-to-growth ratio, or E/G ratio) may be used to define the process conditions. The E/G ratio is the ratio of the partial pressure of etch-back gas(es) (such as HCl) to the weighted partial pressure of the growth gas(es) (such as GeH 4  and DCS). In an exemplary embodiment in which GeH 4 , HCl, and DCS are used, the E/G ratio may be expressed as:
 
 E/G  ratio= P   HCl /( P   DCS +100 ×P   GeH4 )  [Eq. 1]
 
With P HCl , P DCS , and P GeH4  being the partial pressures of HCl, DCS, and GeH 4 , respectively. The value “100” represents an estimated weight of GeH 4 . The accurate estimated weight of GeH 4  may need to be found through experiments. It was observed that GeH 4  has a much higher effect to the growth than DCS. In other words, to increase the growth rate, it is much more effective to introduce more GeH 4  than to introduce more DCS. The weight  100  thus indicates the significantly greater effect of GeH 4  over DCS, although an actual weight may be slightly different.
 
     Alternatively, the E/G ratio may be expressed using flow rates of the process gases:
 
 E/G  ratio=FR HCl /(FR DCS +100×FR GeH4 )  [Eq. 2]
 
With FR HCl , FR DCS , and FR GeH4  being the flow rates of HCl, DCS, and GeH 4 , respectively. The value “100” again represents an estimated weight of GeH 4 . The accurate estimated weight of GeH 4  may need to be found through experiments. At a constant temperature and a constant total volume of HCl, DCS, and GeH 4 , Equations 1 and 2 are equivalent. Alternatively stating, if the temperature and the total volume of HCl, DCS, and GeH 4  are constant, the E/G ratio expressed using Equation 1 may be converted to (or from) the E/G ratio expressed using Equation 2 by simply changing the symbols “P” to (or from) the symbols “FR.” If, however, the temperature and/or the total volume are not constant, the E/G ratio expressed using Equation 1 may not be converted to (or from) the E/G ratio expressed using Equation 2 by simply changing the symbols “P” to (or from) the symbols “FR,” and further modification, such as the modification of the estimated weight of GeH 4  may be needed. Furthermore, the if the temperature and/or the total volume are not constant, the E/G ratio calculated using Equation 1 may be slightly different from the E/G ration calculated using Equation 2.
 
       FIG. 5B  illustrates a top view of device regions  100  and  200 . In addition, region  300  is also illustrated. The cross-sectional view of the structure shown in  FIG. 5A  may be obtained from the plane crossing lines  5 A- 5 A in  FIG. 5B . In an embodiment, recesses  118  as in  FIG. 5A  represent the largest recesses in a wafer in which SiGe is to be grown, while recesses  218  represent the smallest recesses in the same wafer in which SiGe is to be grown, although recesses  118  and  218  may represent any recesses have other sizes. In an exemplary embodiment, as shown in  FIG. 5B , recesses  118  in device region  100  have length L 1  equal to about 5.0 μm and width W 1  equal to about 0.05 μm. Recesses  218  in device region  200  have length L 2  equal to about 0.05 μm and width W 2  equal to about 0.05 μm. Recesses  318  have sizes between the sizes of recesses  118  and  218 . In an example, recesses  318  in device region  300  have length L 3  equal to about 1.0 μm and width W 3  equal to about 0.05 μm. It is expected that if the SiGe regions formed in recesses  118  and  218  have substantially the same thickness, the SiGe regions formed in recesses  318  will also have the same thickness as the SiGe regions formed in recesses  118  and  218 . 
       FIG. 6A  illustrates the growth rates of epitaxy regions as functions of E/G ratios, wherein the growth rates in  FIG. 6A  reflect the growth of SiGe in device region  200 . It is appreciated that when the growth rates have negative values, the growth is equivalent to an etching. It is observed that when the E/G ratio increases, the epitaxy process enters into stages A, B, C 1 , C 2 , D, and E. Since some of these stages have the net growth effect and some have the net etching effect, stages A, B, C 1 , C 2 , D, and E are also referred to as growth/etching stages. The details in determining the dividing points Q, R, S, T, and U between different stages are shown in  FIG. 6B . 
     Stage A is a fast epitaxy region with a high growth rate. However, the defect rate of the resulting SiGe formed with the corresponding growth being in stage A is also high. When the E/G ratio increases so that the epitaxy process goes into stage B, the growth rate is still high, and the defect rate of the corresponding grown SiGe is reduced compared to stage A. Accordingly, stage B may be used, while stage A is not used for growing SiGe in embodiments. The dividing point of stages A and B is point Q, at which the growth rate is the highest. In stage C 1 , a balance growth may be achieved, wherein due to the increase in the etching gas (and hence higher E/G ratio), the etching effect is increased, although the net effect is still a growth. The quality of the grown SiGe is high due to the relatively high etching effect. 
     Stage C 2  is a balanced etching stage, wherein due to the further increase in etching gas, the etching effect exceeds that of growth, and hence the net effect is selective etching. Stage D is also a selective etching stage with both growth and etching effect exist at the same time, and the etching effect is further increased over that of stage C 2 . In stages C 2  and D, self-pinning effect occurs, which means that in these growth/etching stages, the surfaces of the grown SiGe regions have the tendency of being pinned to stable crystal surface planes such as (001) planes. Accordingly, the abnormal growth may be etched away, and SiGe regions that are grown faster will be etched more than the regions grown slower. The thickness uniformity in SiGe regions throughout wafer  1  thus may be improved. 
     In stage E, the growth effect, if any, is negligible, and hence stage E is a pure etching stage or substantially pure etching stage. Growth/etching stage E may be achieved using in-situ pure dry etching in a reduction atmosphere (for example, using 99 percent hydrogen (H 2 ) gas). Growth/etching stage E can be performed before any SiGe regions are grown in recesses  118 / 218 / 318  ( FIGS. 5A and 5B ), so that silicon substrate  2  is etched, and the exposed surfaces of recesses  118 / 218 / 318  are pinned to stable surfaces including (111) and (001) surface planes. As a result, the angles between the surface planes of recesses  118 / 218 / 318  may be set to 54.7 degrees. Further, the effective channel lengths of the resulting MOS devices may be adjusted through stage E. By performing growth/etching stage E, recesses  118 / 218 / 318  may extend under the respective spacers, and hence the channel lengths of the resulting MOS devices may be reduced. 
       FIG. 6B  schematically illustrates experiment results that revealed the growth rates of epitaxy as functions of E/G ratios, wherein the growth rates of SiGe in device regions  100  and  200  are shown. Line  400  schematically illustrates the behavior of the SiGe growth in device region  100 , and line  402  schematically illustrates the behavior of the SiGe growth in device region  200 . Although lines  400  and  402  are illustrated as being straight lines, they may actually be curved similar to what is shown in  FIG. 6A . In the following discussed embodiments, it is assumed that line  400  represents the behavior of the largest recesses (for example, recesses  118  in  FIG. 5B ) in wafer  1 , while line  402  represents the behavior of the smallest recesses (for example, recesses  218  in  FIG. 5B ) in wafer  1 . Lines  400  and  402  revealed that when SiGe is grown in recesses of different sizes, depending on the sizes of the recesses, the growth/or etch behavior in different recesses may fall into different stages. For example, when the E/G ratio is greater than EG 3  and smaller than EG 4 , line  400  is in a selective growth stage, while line  402  is in a selective etching stage. The marked stages A, B, C 1 , C 2 , D, and E are actually the stages of line  402 , which is for the smallest recesses in the respective wafer. Reference E/G ratios EG 1  through EG 5  are marked to show the respective E/G ratios of dividing points Q, R, S, T, and U between stages A, B, C 1 , C 2 , D, and E. 
     Referring to  FIG. 6B , the dividing point between stages A and B is point Q. In stage A, the growth rates in recesses  118  and  218  are high. The dividing point between stages B and C 1  is point R, at which the growth in recesses  118  and  218  have the same growth rate. Accordingly, reference E/G ratio EG 2  is also referred to as a uniform E/G ratio, and point R is referred to as a balance point. At the uniform E/G ratio, all recesses having different sizes may have substantially the same, or at least, similar, growth rate. Between E/G ratios EG 1  and EG 2 , both lines  400  and  402  are in selective growth stages. The dividing point between stages C 1  and C 2  is point S (corresponding to EG 3 ), at which line  402  enters a selective etching stage from a selective growth stage. However, line  400  is still in a selective growth stage. The dividing point between stages C 2  and D is point T (corresponding to EG 4 ), at which line  400  also enters into a selective etching stage from the selective growth stage. The dividing point between stages D and E is point U (corresponding to EG 5 ), at which both lines  400  and  402  enters into substantially pure etch stages. Since E/G ratios EG 1  through EG 5  are related to the process used in the epitaxial growth, experiments may be performed to determine the values of E/G ratios EG 1  through EG 5 . In an embodiment, experiment results revealed that in an exemplary embodiment wherein recesses  118  ( FIG. 5B ) have a length of 5 μm and a width of 0.05 μm, and recesses  218  ( FIG. 5B ) have a length of 0.05 μm and a width of 0.05 μm, E/G ratios EG 1 , EG 2 , EG 3 , EG 4 , and EG 5  are about 0.1, 0.6, 1.2, 1.5, and 3.0, respectively. 
       FIG. 6B  also schematically illustrates the behavior of germanium concentrations. For example, the germanium concentration of the SiGe grown from small recesses (such as recesses  218  in device region  200  in  FIG. 5B ) tend to have higher germanium concentrations than the germanium concentration of the SiGe grown from large recesses such as recesses  118 . In the selective etching of the SiGe regions, the trend is reversed, and more germanium may be removed from the small recesses than from large recesses. Accordingly, by using stages C 1  and/or C 2  to grow SiGe regions, the germanium concentration throughout the respective chip/wafer may be more uniform, with the difference between large recesses and small recesses being smaller than about one percent, for example. 
     By combining the epitaxy growth/etching stages as shown in  FIG. 6B  into different combinations, the pattern loading effect in the epitaxy growth may be reduced, and the quality of the resulting epitaxy regions may be improved.  FIGS. 7A through 7D  illustrate the epitaxy regions formed using different combinations. In the discussion of  FIGS. 7A through 7D , normalized flow rates of process gases are used, wherein the normalization is performed by dividing the flow rates of HCl and DCS by the flow rate of HCl used in grow stage B. The normalization of the flow rate of GeH4 is performed through dividing the flow rate of GeH4 by the flow rate of HCl in growth stage B, and then times  100 . The E/G ratio may be calculated using Equation 2. For example, assuming that the flow rates of HCl, DCS, and GeH 4  are 50 sccm, 100 sccm, and 2 sccm, respectively, then the normalized flow rates of HCl, DCS, and GeH 4  are 1×, 2×, and 2×, respectively, and the E/G ratio according to Equation 2 is 1/6. 
       FIG. 7A  illustrates SiGe regions  120  and  220  formed in recesses  118  and  218  ( FIGS. 5A and 5B ), respectively, wherein a first growth combination is used. In the first growth combination, SiGe regions  120 -B and  220 -B are first grown with the E/G ratio being set in stage B ( FIG. 6B ). In an exemplary embodiment, during the formation of regions  120 -B and  220 -B, the normalized flow rates of HCl, DCS, and GeH 4  are 1×, 2×, and 2×, respectively. Accordingly, per Equation 2, the E/G ratio is 0.25. 
     Next, the process condition is adjusted, and the composition of the etching gas is increased so that the growth of SiGe is changed to the growth of regions  120 -C 1  and  220 -C 1 . In an exemplary embodiment, during stage C 1  ( FIG. 6 ), the normalized flow rates of HCl, DCS, and GeH 4  are 2×, 1×, and 1×, respectively. Accordingly, per Equation 2, the E/G ratio is 1. The flow rates of process gases may be changed gradually to reduce the abrupt change in the composition in the resulting SiGe regions.  FIG. 8A  illustrates exemplary E/G ratios corresponding to  FIG. 7A , wherein the E/G ratios are shown as a function of time. In an embodiment, the E/G ratio increases gradually with time, and goes into stage C 1  from stage B. 
     As shown in  FIG. 7A , during stage B, since line  402  in stage B has higher growth rates than line  400  in stage B ( FIG. 6B ), the resulting SiGe region  220 -B has a greater thickness T 1  than thickness T 3  of SiGe region  120 -B. Conversely, during stage C 1 , since line  402  in stage C 1  has lower growth rates than line  400  ( FIG. 6B ), the resulting SiGe region  220 -C 1  has a smaller thickness T 2  than thickness T 4  of SiGe region  120 -C 1 . Accordingly, the differences in the growth rates in growth stages B and C 1  compensate for each other, and hence the total thickness T 3 +T 4  of SiGe region  120  may be adjusted to substantially equal to thickness T 1 +T 2  of SiGe region  220 . The adjustment of thicknesses of T 1 , T 2 , T 3 , and T 4  may be achieved by adjusting the durations of the epitaxy process in stages B and/or C 1 , and/or the E/G ratios in stages B and/or C 1 . 
       FIG. 7B  illustrates SiGe regions  120  and  220  formed in recesses  118  and  218  ( FIGS. 5A and 5B ), respectively, wherein a second growth combination is used. In the second growth combination, SiGe regions  120 -C 1 - 1  and  220 -C 1 - 1  are first grown with the respective E/G ratio being set in stage C 1  in  FIG. 6B . In an exemplary embodiment, during the formation of SiGe regions  120 -C 1 - 1  and  220 -C 1 - 1 , the normalized flow rates of HCl, DCS, and GeH 4  are 4×, 2×, and 2×, respectively. Accordingly, per Equation 2, the E/G ratio is 1.0. 
     Next, the process condition is adjusted, and the composition of the etching gas is reduced so that the growth of SiGe is changed to grow regions  120 -B and  220 -B, during which the E/G ratio is in stage B. In an exemplary embodiment, during stage B for forming regions  120 -B and  220 -B, the normalized flow rates of HCl, DCS, and GeH 4  are 1×, 1×, and 1×, respectively. Accordingly, per Equation 2, the E/G ratio is 0.5. 
     Next, the process condition is further adjusted, and the composition of the etching gas is increased so that the formation of SiGe is changed to form regions  120 -C 1 - 2  and  220 -C 1 - 2  with the respective E/G ratio being set in stage C 1  in  FIG. 6B . In an exemplary embodiment, during the stage C 1  for forming regions  120 -C 1 - 2  and  220 -C 1 - 2 , the normalized flow rates of HCl, DCS, and GeH 4  are 2×, 1×, and 1×, respectively. Accordingly, per Equation 2, the E/G ratio is 1.0.  FIG. 8B  illustrates an exemplary E/G ratio profile in the second growth combination, wherein E/G ratios are illustrated as a function of time. 
     As shown in  FIG. 7B , during stage B, SiGe region  220 -B has a greater thickness than the thickness of SiGe region  120 -B. Conversely, during the two growth/etching stages C 1 , the resulting SiGe regions  220 -C 1 - 1  and  220 -C 1 - 2  have smaller thicknesses than the thicknesses of the respective SiGe region  120 -C 1 - 1  and  120 -C 1 - 2 . Accordingly, the differences in growth rates in growth stage B and growth stages C 1  compensate for each other, and hence the total thickness of SiGe region  120  may be adjusted to substantially equal to the thickness of SiGe region  220 . The adjustment in the thicknesses of SiGe regions  120  and  220  may be achieved by adjusting the duration of stages B and/or C 1 , and/or the E/G ratios in stages B and/or C 1 . 
       FIG. 7C  illustrates SiGe regions  120  and  220  formed in recesses  118  and  218  ( FIGS. 5A and 5B ), respectively, wherein a third growth combination is used. SiGe regions  120 -B and  220 -B are first grown with the E/G ratio being set in stage B. In an exemplary embodiment, during the stage B for forming SiGe regions  120 -B and  220 -B, the normalized flow rates of HCl, DCS, and GeH 4  are 1×, 1×, and 2×, respectively. Accordingly, per Equation 2, the E/G ratio is 0.33. 
     Next, the process condition is adjusted, and the composition of the etching gas is increased so that the growth of SiGe is changed to grow SiGe regions  120 -C 1  and  220 -C 1  with the E/G ration being set in stage C 1 . Dotted lines  121  and  221  schematically illustrate the top surfaces of SiGe regions  120 -C 1  and  220 -C 1 , respectively. In an exemplary embodiment, during stage C 1 , the normalized flow rates of HCl, DCS, and GeH 4  are 2×, 1×, and 1×, respectively. Accordingly, per Equation 2, the E/G ratio is 1. The flow rates of process gases may be changed gradually to reduce the abrupt change in the composition in the resulting SiGe regions. 
     A growth/etching stage D is then performed to remove portions of SiGe regions (marked as SiGe regions  120 -D and  220 -D) from the previously grown SiGe regions  120  and  220 , respectively. In an exemplary embodiment, during stage D, the normalized flow rates of HCl, DCS, and GeH 4  are 4×, 1×, and 1×, respectively. Accordingly, per Equation 2, the E/G ratio is 2.0. In stage D, selective etching is performed in both device regions  100  and  200 , and hence the top surface of SiGe region  120  is reduced from position  121  to position  123 , and the top surface of SiGe region  220  is reduced from position  221  to position  223 . The selective etching reduces or substantially removes the likely abnormal growth of SiGe regions  120  and  220 , so that SiGe regions  120  and  220  may have an improved quality. Besides, the selective etching could reduce SiGe region abnormal growth due to layout or other process excursions. 
     Next, the process condition is further adjusted, and the composition of the etching gas is reduced so that the formation of SiGe is changed to grow regions  120 -C 1 - 2  and  220 -C 1 - 2  with the E/G ratio being set in stage C 1 , which growth starts from positions 123 and 223, respectively. In an exemplary embodiment, during this specific stage C 1 , the normalized flow rates of HCl, DCS, and GeH 4  are 2×, 1×, and 1×, respectively. Accordingly, per Equation 2, the E/G ratio is 1.0. 
     During growth/etching stage B, the thickness of SiGe region  220  is grown to be greater than the thickness of SiGe region  120 . The two growth/etching stages C 1  cause the difference in the thicknesses of SiGe regions  120  and  220  to be reduced partially. Furthermore, during growth stage D, the thickness of SiGe region  220  is reduced more than that of SiGe region  120 . Accordingly, the combined effect of stages B, C 1 , D, and C 1  may result in a same thickness in SiGe regions  120  and  220 . The adjustment in the thicknesses of SiGe regions  120  and  220  may be achieved by adjusting the duration of stages B, C 1 , D, and C 1 , and/or the E/G ratios in these stages.  FIG. 8C  illustrates an exemplary E/G ratio profile in the third growth combination as shown in  FIG. 7C , wherein E/G ratios are illustrated as a function of time. 
     An additional embodiment may be similar to the embodiment as shown in  FIG. 7C , except that stage B is performed, followed by stage D. Stages C 1  as in  FIG. 7C , however, are omitted. Through this combination, SiGe regions  120  and  220  may also have substantially the same thickness. 
       FIG. 7D  illustrates SiGe regions  120  and  220  formed in recesses  118  and  218  ( FIGS. 5A and 5B ), respectively, wherein a fourth growth combination is used. In the fourth growth combination, stage E for pure etch stage is first performed, so that the profile of recesses  118  and  218  is improved, and the surface planes of recesses  118  and  218  are pinned (symbolized by arrows) to stable crystal surface planes such as (001) and (111) planes. Accordingly, the resulting SiGe regions subsequently grown in recesses  118  and  218  may have an improved quality. In one embodiment, stage D is performed instead of stage E. Stage D selectively etches the surface planes of recesses  118  and  218  so that the profile of recesses  118  and  218  is improved. 
     Next, SiGe regions  120 -B and  220 -B are grown with the E/G ratio being set to stage B in  FIG. 6B . In an exemplary embodiment, during growth/etching stage B, the normalized flow rates of HCl, DCS, and GeH 4  are 1×, 1×, and 2×, respectively. Accordingly, per Equation 2, the E/G ratio is 0.33. 
     Next, the process condition is adjusted, and the composition of the etching gas is increased so that the growth of SiGe is changed to form regions  120 -C 1  and  220 -C 1  with the E/G ratio being set to stage C 1 . In an exemplary embodiment, during stage C 1 , the normalized flow rates of HCl, DCS, and GeH 4  are 2×, 1×, and 1×, respectively. Accordingly, per Equation 2, the E/G ratio is 1. Thicknesses of SiGe regions  120  and  220  may be adjusted by adjusting the duration of stages B and/or C 1 , and/or the E/G ratios in stages B and/or C 1 , so that a uniform thickness may be achieved for SiGe regions throughout the respective wafer.  FIG. 8D  illustrates an exemplary E/G ratio profile in the fourth growth combination as shown in  FIG. 7D , wherein E/G ratios are illustrated as a function of time. 
     Referring to  FIG. 7E , the growth of SiGe regions  120  and  220  is performed using the process conditions in stage C 1 , with the E/G ratio of the growth close to the E/G ratio EG 2  at balance point R as shown in  FIG. 6B . The resulting SiGe regions  120  and  220  are illustrated as  120 -C 1  and  220 -C 1 , respectively. In an exemplary embodiment, assuming the E/G ratio for growing SiGe regions  120  and  220  is EG′, the difference (EG′-EG 2 )/EG 2  may be smaller than about 0.2, and may be smaller than about 0.1. Since the balance point R is the point SiGe regions  120  and  220  have the same growth rate, as the E/G ratio close to EG 2  at balance point R as in  FIG. 6B , the resulting SiGe regions  120  and  220  have substantially the same thickness. In addition, the germanium concentrations in SiGe regions  120  and  220  will be close to each other. 
       FIG. 7F  illustrates SiGe regions  120  and  220  formed in recesses  118  and  218  ( FIGS. 5A and 5B ), respectively, wherein a fifth growth combination is used. In the fifth growth combination, C 2  stage is perform first so that a selective growth is performed in recesses  118 , while a selective etching is simultaneously performed in recesses  218 . The etching rate in recesses  218  is low. Therefore, the net effect is similar to growing SiGe regions  120  in recesses  118 , while no SiGe is grown in recesses  218 . The respective SiGe  120  in recesses  118  is referred to as SiGe regions  120 -C 2 . The thickness T 5  of SiGe regions  120 -C 2  is related to the difference in growth rates in subsequently performed SiGe growth in stage B. 
     Next, SiGe regions  120 -B and  220 -B are grown with the E/G ratio being set to stage B in  FIG. 6B . In an exemplary embodiment, during growth/etching stage B, the normalized flow rates of HCl, DCS, and GeH 4  are 1×, 1×, and 2×, respectively. Accordingly, per Equation 2, the E/G ratio is 0.33. 
     As shown in  FIG. 6B , in stage B, the growth rate of SiGe regions  120 -B ( FIG. 7F ) is lower than the growth rate of SiGe regions  220 -B. Accordingly, thickness T 6  of SiGe regions  120 -B is smaller than thickness T 7  of SiGe regions  220 -B. With the proceeding in the growth of SiGe regions  120 -B and  220 -B, the difference between the thicknesses of SiGe regions  120  and  220  becomes increasingly smaller, and eventually, the thicknesses of SiGe regions  120  and  220  will be equal. 
     In the above-discussed embodiments as shown in  FIG. 7F , the materials of regions  120 B and  220 B may be different from the material of regions  120 -C 2 . For example, the germanium concentrations of regions  120 B and  220 B may be different from that of regions  120 -C 2 . Alternatively, one of regions  120 B/ 220 B and  120 -C 2  may be silicon germanium regions, while the other regions may be silicon regions, silicon carbon regions, or the like. 
     In each of the growth combinations, the orders of the stages in the respective combinations may be changed to other possible combinations. It is also appreciated that  FIGS. 7A through 7D  illustrate samples of various possible combinations. One skilled in the art will realize that there are various additional combinations that may be used to achieve a uniform SiGe growth and to form SiGe regions with improved quality. 
       FIGS. 9A through 9C  illustrate the normalized SiGe thicknesses (or normalized Ge concentrations in the grown SiGe regions) in device regions  100 ,  200 , and  300 . By using the embodiments shown in  FIGS. 7A through 7D , as shown in  FIG. 9A , a uniform thickness may be achieved for regions  100  and  200 . When recesses  118  in device region  100  and recesses  218  in device regions  200  are the largest and the smallest SiGe regions, respectively in the respective wafer, achieving a uniform SiGe growth for regions  100  and  200  also means that any SiGe region (device regions  300 ) having recess sizes between that of device regions  100  and  200  will also have a similar thickness as that in device regions  100  and  200 . Accordingly, across the entire wafer, a uniform thickness of SiGe regions may be achieved and SiGe growth variation can be reduced. 
     In some embodiments, the thickness profile as shown in  FIG. 9B  may be needed, wherein the SiGe regions in device region  200  may have a smaller thickness than the SiGe regions in device region  100 . Conversely, in some other embodiments, the thickness profile as shown in  FIG. 9C  may be needed, wherein the SiGe regions in device region  100  may have a smaller thickness than the SiGe regions in device region  200 . For example, it may be desired that the thicknesses of the SiGe regions in device regions  100  and  200  have a difference of about 10 percent, for example. It is realized that by applying the teaching of the embodiments, the thickness profiles as shown in  FIGS. 9A, 9B, and 9C  may be achieved. 
     Although  FIGS. 6A through 8D  illustrate the growth of SiGe regions, the teaching may be applied to the epitaxial growth of other semiconductor materials such as SiC, silicon, or the like. Accordingly, experiments may be performed to find the process conditions including the process gases and the partial pressures (or flow rates) for each growth/etching stages as shown in  FIGS. 6A and 6B . The process conditions corresponding to the growth/etching stages may then be used to derive different combinations of the growth/etching stages. Accordingly, a uniform growth throughout a wafer and an improved quality in the grown material may be achieved. 
       FIG. 10  illustrates the formation of silicon caps or SiGe caps  130  and  230  (referred to as Si/SiGe caps, or silicon-containing caps hereinafter), which may also be formed using selective epitaxial growth. When germanium is contained in silicon-containing caps, the germanium atomic percentage in silicon-containing caps  130  and  230  will be lower than the germanium atomic percentage in the respective underlying SiGe regions  120  and  220 , respectively. Further, the germanium atomic percentage in silicon-containing caps  130  and  230  may be lower than about 20 percent. Silicon-containing caps  130  and  230  are beneficial for the subsequent formation of source and drain silicide regions due to the low resistivity of silicide formed on silicon rather than on SiGe. The process gases for forming silicon-containing caps  130  and  230  may include silane (SiH 4 ) and HCl. Again, in the selective growth of silicon-containing caps  130  and  230 , both growth and etch back exist, while the net effect is growth. Facets may also be formed on silicon-containing caps  130  and  230 . Accordingly, similar to the formation of SiGe regions  120  and  220 , after the selective growth of silicon-containing caps  130  and  230 , an optional selective etch-back may be performed to reduce the pattern-loading effect and to improve the profiles of silicon-containing caps  130  and  230 . The dotted lines schematically illustrate the profile of silicon-containing caps  130  and  230  at the time the selective etch-back starts, while the profile of silicon-containing caps  130  and  230  after the selective etch-back is illustrated using solid lines. Again, the selective etch-back of silicon-containing caps  130  and  230  may be in-situ performed with the respective selective growth. In the selective etch-back of silicon-containing caps  130  and  230 , both growth and etch-back exist, while the net effect is etch-back. The transition from selective growth to selective etch-back may be achieved by adjusting the process conditions such as increasing the partial pressure of HCl and/or reducing the partial pressure of silane. 
       FIG. 11  illustrates the formation of silicide regions  134  and  234 , etch stop layer (ESL)  36 , and contact plugs  140  and  240 . Silicide regions  134  and  234  may be formed by depositing a thin layer of metal, such as titanium, cobalt, nickel, or the like, over the devices, including the exposed surfaces of silicon-containing caps  130  and  230  and gate electrode  106  and  206 . Wafer  1  is then heated, which causes the silicide reaction to occur wherever the metal is in contact with silicon. After the reaction, a layer of metal silicide is formed between silicon and metal. The un-reacted metal is selectively removed through the use of an etchant that attacks metal but does not attack silicide. Further, no contact plugs are formed to connect to dummy gate stacks  502 . 
     ESL  36  is blanket deposited. ESL  36  may be formed using plasma enhanced chemical vapor deposition (PECVD), but other CVD methods, such as low pressure chemical vapor deposition (LPCVD), and thermal CVD may also be used. Inter-level dielectric (ILD)  38  is next deposited. ILD layer  38  may comprise boronphospho-silicate glass (BPSG) or other applicable materials. ILD layer  38  provides insulation between MOS devices and overlying metal lines. Contact plugs  140  and  240  are then formed providing access to the source/drain region and gate electrodes through silicide regions  134  and  234 . 
     In the above-discussed embodiments, the growth of SiGe stressors for planar devices is illustrated. The teaching, however, may also be applied to the growth of SiGe stressors for fin field-effect transistors (FinFETs). The process may include forming a gate stack on a semiconductor fin (not shown), etching the exposed portions of the semiconductor fin not covered by the gate stack, and performing a selective growth followed by a selective etch-back to form SiGe stressors. The process details may be realized through the teaching in the embodiments, and hence are not discussed herein. In addition, the teaching of the embodiments may also be applied to the formation of stressors (such as SiC stressors) for NMOS devices. The selective etch-back as discussed in the preceding embodiments, besides used for the formation of CMOS devices, bipolar junction transistors (BJTs) may also be used for the formation other devices such as solar cell, micro-electro-mechanical-systems (MEMS) devices, micro-optical structures, etc. 
     In the above-illustrated embodiments, epitaxial regions are grown from recesses formed in semiconductor substrates. In the formation of some other integrated circuit structures, such as the formation of MEMS devices or micro-optical structures, epitaxial semiconductor regions such as epitaxial SiGe regions may grown on the surface of semiconductor substrates or other semiconductor materials formed over semiconductor substrates, rather than from inside recesses. In these embodiments, the epitaxial semiconductor regions may not be formed as source/drain regions, and hence may not be adjacent to gate stacks of MOS transistors. The respective formation processes and the materials may be essentially the same as illustrated in  FIGS. 6A through 9C , and as provided in the discussion of the respective embodiments. 
     In the embodiments, by reducing pattern-loading effects through the selective etch-back processes, more uniform formation of epitaxy regions (such as SiGe stressors) is achieved, and the profiles of the epitaxy regions are improved. The (111) facets pinning of the epitaxy regions can be reduced, or even substantially eliminated. Additionally, the selective etch-back can be performed in-situ with the selective growth, thus minimal extra cost is involved and SiGe growth variation can be reduced. 
     In accordance with embodiments, a method includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first E/G ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio. 
     In accordance with other embodiments, a method includes a forming a first gate stack and a second gate stack over a semiconductor substrate in a wafer; and forming a first recess and a second recess in the semiconductor substrate and adjacent the first and the second gate stacks, respectively. The first recess has an area greater than an area of the second recess. The method further includes performing a selective epitaxial growth to grow a semiconductor material in the first recess and the second recess. The step of performing the selective epitaxial growth includes performing a first and a second growth stage. In the first growth stage, a first growth rate of the semiconductor material in the first recess is greater than a second growth rate of the semiconductor material in the second recess. In the second growth stage, a third growth rate of the semiconductor material in the first recess is smaller than a fourth growth rate of the semiconductor material in the second recess. 
     In accordance with yet other embodiments, a method includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow SiGe in the recess using process gases comprising GeH 4 , HCl, and dichloro silane (DCS). The step of performing the selective epitaxial growth includes performing a first growth/etching stage with a first E/G ratio of the process gases used in the first growth stage; and performing a second growth/etching stage with a second E/G ratio of the process gases used in the second growth stage different from the first E/G ratio. The first and the second E/G ratios are calculated using an equation:
 
 E/G  ratio=FR HCl /(FR DCS +100×FR GeH4 )
 
wherein FR HCl , FR DCS , and FR GeH4  are flow rates of HCl, DCS, and GeH 4 , respectively, and wherein the first E/G ratio is smaller than 0.6, and the second E/G ratio is greater than 0.6.
 
     Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.