Patent Publication Number: US-2021175343-A1

Title: High electron mobility transistor and method for fabricating the same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a high electron mobility transistor (HEMT) and method for fabricating the same. 
     2. Description of the Prior Art 
     High electron mobility transistor (HEMT) fabricated from GaN-based materials have various advantages in electrical, mechanical, and chemical aspects of the field. For instance, advantages including wide band gap, high break down voltage, high electron mobility, high elastic modulus, high piezoelectric and piezoresistive coefficients, and chemical inertness. All of these advantages allow GaN-based materials to be used in numerous applications including high intensity light emitting diodes (LEDs), power switching devices, regulators, battery protectors, display panel drivers, and communication devices. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer. 
     According to another aspect of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; patterning the p-type semiconductor layer; and forming a spacer adjacent to the p-type semiconductor layer. 
     According to yet another aspect of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a first barrier layer on the buffer layer; a p-type semiconductor layer on the first barrier layer; and a spacer adjacent to the p-type semiconductor layer. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-5  illustrate a method for fabricating a HEMT according to an embodiment of the present invention. 
         FIG. 6  illustrates a structural view of a HEMT according to an embodiment of the present invention. 
         FIGS. 7-12  illustrate a method for fabricating a HEMT according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to the  FIGS. 1-5 ,  FIGS. 1-5  illustrate a method for fabricating a HEMT according to an embodiment of the present invention. As shown in the  FIG. 1 , a substrate  12  such as a substrate made from silicon, silicon carbide, or aluminum oxide (or also referred to as sapphire) is provided, in which the substrate  12  could be a single-layered substrate, a multi-layered substrate, gradient substrate, or combination thereof. According to other embodiment of the present invention, the substrate  12  could also include a silicon-on-insulator (SOI) substrate. 
     Next, a buffer layer  14  is formed on the substrate  12 . According to an embodiment of the present invention, the buffer layer  14  is preferably made of III-V semiconductors such as gallium nitride (GaN), in which a thickness of the buffer layer  14  could be between 0.5 microns to 10 microns. According to an embodiment of the present invention, the formation of the buffer layer  14  could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. 
     Next, a first barrier layer  16  is formed on the surface of the buffer layer  14 . In this embodiment, the first barrier layer  16  is preferably made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0&lt;x&lt;1, x being less than or equal to 20%, and the first barrier layer  16  preferably includes an epitaxial layer formed through epitaxial growth process. Similar to the buffer layer  14 , the formation of the first barrier layer  16  on the buffer layer  14  could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. 
     Next, a p-type semiconductor layer  18  and a hard mask  20  are sequentially formed on the surface of the first barrier layer  16 . In this embodiment, the p-type semiconductor layer  18  is preferably a III-V compound layer including p-type GaN (p-GaN) and the formation of the p-type semiconductor layer  18  on the first barrier layer  16  could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. The hard mask  20  could include dielectric, conductive, or metal material including but not limited to for example silicon nitride, silicon oxide, or titanium nitride. 
     Next, as shown in  FIG. 2 , a pattern transfer process is conducted to pattern the hard mask  20  and the p-type semiconductor layer  18  by first using a patterned mask (not shown) as mask to remove part of the hard mask  20  and part of the p-type semiconductor layer  18  for exposing the surface of the first barrier layer  16  adjacent to two sides of the patterned p-type semiconductor layer  18 , in which the patterned p-type semiconductor layer  18  preferably becomes a part of the gate structure of the HEMT in the later process. It should be noted that to prevent a continuous p-type semiconductor layer  18  from inducing a micro loading effect, the pattern transfer process conducted at this stage preferably removes all of the remaining p-type semiconductor layer  18  adjacent to two sides of the patterned p-type semiconductor layer  18  during the patterning process to expose the surface of the first barrier layer  16  so that the top surface of the first barrier layer  16  adjacent to two sides of the patterned p-type semiconductor layer  18  could be even with or slightly lower than the top surface of the first barrier layer  16  directly under the p-type semiconductor layer  18 . 
     Next, as shown in  FIG. 3 , a spacer  22  is formed adjacent to the hard mask  20  and the p-type semiconductor layer  18 . Specifically, the formation of the spacer  22  could be accomplished by first forming a liner (not shown) made of dielectric material on the substrate  12  to cover the first barrier layer  16  and the hard mask  20 , and an etching back process is conducted to remove part of the liner for forming a spacer  22  on sidewalls of the p-type semiconductor layer  18  and the hard mask  20 , in which the top surface of the spacer  22  is preferably even with the top surface of the hard mask  20 . It should be noted that even though the spacer  22  pertains to be a single spacer in this embodiment, it would also be desirable to adjust the number of the liner being deposited to form one or more spacers including two, three, or even four spacers on sidewalls of the p-type semiconductor layer  18  and the hard mask  20 . Preferably, each of the spacers  22  could include an I-shape and/or L-shape cross-section and each of the spacers could include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combination thereof. 
     Next, as shown in  FIG. 4 , a second barrier layer  24  is formed on the surface of the first barrier layer  16  adjacent to two sides of the spacer  22 . Preferably, the first barrier layer  16  and the second barrier layer  24  are made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N) and each of the two layers includes an epitaxial layer formed through epitaxial growth process. In this embodiment, the first barrier layer  16  and the second barrier layer  24  preferably include different thicknesses such as the thickness of the first barrier layer  16  is preferably less than the thickness of the second barrier layer  24 . 
     Moreover, the first barrier layer  16  and the second barrier layer  24  preferably include different concentrations of aluminum or more specifically the aluminum concentration of the first barrier layer  16  is less than the aluminum concentration of the second barrier layer  24 . For instance, the first barrier layer  16  is made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0&lt;x&lt;1, x being 5-15% and the second barrier layer  24  is made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0&lt;x&lt;1, x being 15-50%. Similar to the formation of the first barrier layer  16 , the formation of the second barrier layer  24  on the first buffer layer  16  could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. 
     Next, as shown in  FIG. 5 , a passivation layer  26  is formed on the surfaces of the second barrier layer  24 , the spacer  22 , and the hard mask  20 , and a gate electrode  28  is formed on the hard mask  20  and a source electrode  30  and a drain electrode  32  are formed adjacent to two sides of the gate electrode  28 , in which the p-type semiconductor layer  18 , the hard mask  20 , and the gate electrode  28  could constitute a gate structure  34  altogether. In this embodiment, it would be desirable to conduct a photo-etching process to remove part of the passivation layer  26  directly on top of the p-type semiconductor layer  18  or hard mask  20  to form a recess (not shown), form a gate electrode  28  in the recess, remove part of the passivation layer  26  adjacent to two sides of the spacer  22  to form two recesses, and then form source electrode  30  and drain electrode  32  in the two recesses adjacent to two sides of the gate electrode  28 . 
     It should be noted that the hard mask  20  in this embodiment is preferably made of conductive material such as titanium nitride (TiN) so that the gate electrode  28  could be disposed directly on the surface of the hard mask  20  without contacting the p-type semiconductor layer  18  directly. Moreover, the gate electrode  28 , the source electrode  30 , and the drain electrode  32  are preferably made of metal, in which the gate electrode  28  is preferably made of Schottky metal while the source electrode  30  and the drain electrode  32  are preferably made of ohmic contact metals. According to an embodiment of the present invention, each of the gate electrode  28 , source electrode  30 , and drain electrode  32  could include gold (Au), Silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), palladium (Pd), or combination thereof. Preferably, it would be desirable to conduct an electroplating process, sputtering process, resistance heating evaporation process, electron beam evaporation process, physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, or combination thereof to form electrode materials in the aforementioned recesses, and then pattern the electrode materials through one or more etching processes to form the gate electrode  28 , source electrode  30 , and the drain electrode  32 . This completes the fabrication of a HEMT according to an embodiment of the present invention. 
     Referring to  FIG. 6 ,  FIG. 6  illustrates a structural view of a HEMT according to an embodiment of the present invention. As shown in  FIG. 6 , the HEMT similar to the embodiment disclosed in  FIG. 5  also includes a buffer layer  14  disposed on the substrate  12 , a first barrier layer  16  disposed on the buffer layer  14 , a p-type semiconductor layer  18  disposed on the first barrier layer  16 , a gate electrode  28  disposed on the p-type semiconductor layer  18 , a hard mask  20  disposed on the p-type semiconductor layer  18 , a spacer  22  disposed adjacent to the p-type semiconductor layer  18  and the hard mask  20 , a second barrier layer  24  disposed on the first barrier layer  16  adjacent to the spacer  22 , and a source electrode  30  and drain electrode  32  disposed on the second barrier layer  24  adjacent to two sides of the spacer  22 . 
     In contrast to the hard mask  20  in  FIG. 5  made of conductive material, the hard mask  20  in this embodiment could be made of conductive or dielectric material including but not limited to for example TiN, silicon oxide, or silicon nitride. In this approach, it would be desirable to have the gate electrode  28  penetrating the hard mask  20  and contacting the surface of the p-type semiconductor layer  18  directly, or if viewed from another perspective the hard mask  20  is disposed on the p-type semiconductor layer  18  and surrounding the gate electrode  28 . 
     Referring to  FIGS. 7-12 ,  FIGS. 7-12  illustrate a method for fabricating a HEMT according to an embodiment of the present invention. As shown in the  FIG. 7 , a substrate  42  such as a substrate made from silicon, silicon carbide, or aluminum oxide (or also referred to as sapphire) is provided, in which the substrate  42  could be a single-layered substrate, a multi-layered substrate, gradient substrate, or combination thereof. According to other embodiment of the present invention, the substrate  42  could also include a silicon-on-insulator (SOI) substrate. 
     Next, a buffer layer  44  is formed on the substrate  12 . According to an embodiment of the present invention, the buffer layer  44  is preferably made of III-V semiconductors such as gallium nitride (GaN), in which a thickness of the buffer layer  44  could be between 0.5 microns to 10 microns. According to an embodiment of the present invention, the formation of the buffer layer  44  could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. 
     Next, a first barrier layer  46  is formed on the surface of the buffer layer  44 . In this embodiment, the first barrier layer  46  is preferably made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0&lt;x&lt;1, x being less than or equal to 20%, and the first barrier layer  46  preferably includes an epitaxial layer formed through epitaxial growth process. Similar to the buffer layer  44 , the formation of the first barrier layer  46  on the buffer layer  44  could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. 
     Next, a p-type semiconductor layer  48  is formed on the surface of the first barrier layer  46 . In this embodiment, the p-type semiconductor layer  48  is preferably a III-V compound layer including p-type GaN (p-GaN) and the formation of the p-type semiconductor layer  48  on the first barrier layer  46  could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. 
     Next similar to  FIG. 2 , a pattern transfer process is conducted to pattern the p-type semiconductor layer  48  by first using a patterned mask (not shown) as mask to remove part of part of the p-type semiconductor layer  48  for exposing the surface of the first barrier layer  46  adjacent to two sides of the patterned p-type semiconductor layer  48 , in which the patterned p-type semiconductor layer  48  preferably becomes a part of the gate structure of the HEMT in the later process. Similar to the aforementioned embodiment of preventing a continuous p-type semiconductor layer  48  from inducing a micro loading effect, the pattern transfer process conducted at this stage preferably removes all of the remaining p-type semiconductor layer  48  adjacent to two sides of the patterned p-type semiconductor layer  48  during the patterning process to expose the surface of the first barrier layer  46  so that the top surface of the first barrier layer  46  adjacent to two sides of the patterned p-type semiconductor layer  48  could be even with or slightly lower than the top surface of the first barrier layer  46  directly under the p-type semiconductor layer  48 . 
     Next, as shown in  FIG. 8 , a spacer  50  is formed adjacent to the p-type semiconductor layer  48 . Specifically, the formation of the spacer  50  could be accomplished by first forming a liner (not shown) made of dielectric material on the substrate  42  to cover the first barrier layer  46  and p-type semiconductor layer  48 , and an etching back process is conducted to remove part of the liner for forming a spacer  50  on sidewalls of the p-type semiconductor layer  48 . Since no hard mask is formed on top of the p-type semiconductor layer  48 , the top surface of the spacer  50  is preferably even with the top surface of the p-type semiconductor layer  48 . It should be noted that even though the spacer  50  pertains to be a single spacer in this embodiment, it would also be desirable to adjust the number of the liner being deposited to form one or more spacers including two, three, or even four spacers on sidewalls of the p-type semiconductor layer  48 , which each of the spacers  50  could include an I-shape and/or L-shape cross-section and each of the spacers could include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combination thereof, which are all within the scope of the present invention. 
     Next, as shown in  FIG. 9 , a second barrier layer  52  is formed on the surface of the first barrier layer  46  adjacent to two sides of the spacer  50  and the top surface of the p-type semiconductor layer  48 . Preferably, the first barrier layer  46  and the second barrier layer  52  are made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N) and each of the two layers includes an epitaxial layer formed through epitaxial growth process. In this embodiment, the first barrier layer  46  and the second barrier layer  52  preferably include different thicknesses such as the thickness of the first barrier layer  46  is preferably less than the thickness of the second barrier layer  52 . 
     Moreover, the first barrier layer  46  and the second barrier layer  52  preferably include different concentrations of aluminum or more specifically the aluminum concentration of the first barrier layer  46  is less than the aluminum concentration of the second barrier layer  52 . For instance, the first barrier layer  46  is made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0&lt;x&lt;1, x being 5-15% and the second barrier layer  52  is made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0&lt;x&lt;1, x being 15-50%. Similar to the formation of the first barrier layer  46 , the formation of the second barrier layer  52  on the first buffer layer  46  could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. 
     Next, as shown in  FIG. 10 , a hard mask  54  is formed to cover the second barrier layer  52  and the exposed spacer  50  entirely. In this embodiment, the hard mask  54  could include be made of conductive or dielectric material including but not limited to for example silicon oxide, silicon nitride, TiN, or aluminum oxide (AlO). 
     Next, as shown in  FIG. 11 , a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the hard mask  54  and the entire second barrier layer  52  disposed directly on top of the p-type semiconductor layer  48  so that the top surface of the remaining hard mask  54  adjacent to two sides of the spacer  50  is even with the top surface of the p-type semiconductor layer  48 . 
     Next, as shown in  FIG. 12 , a passivation layer  56  is formed on the surface of the hard mask  54 , and a gate electrode  58  is formed in the passivation layer  56  on top of the p-type semiconductor layer  48  and a source electrode  60  and a drain electrode  62  are formed adjacent to two sides of the gate electrode  58 , in which the p-type semiconductor layer  48  and the gate electrode  58  could constitute a gate structure  64  altogether. In this embodiment, it would be desirable to conduct a photo-etching process to remove part of the passivation layer  56  directly on top of the p-type semiconductor layer  48  to form a recess (not shown), form a gate electrode  58  in the recess, remove part of the passivation layer  56  and part of the hard mask  54  adjacent to two sides of the spacer  50  to form two recesses, and then form the source electrode  60  and drain electrode  62  in the two recesses adjacent to two sides of the gate electrode  58 . 
     In this embodiment, the gate electrode  58 , the source electrode  60 , and the drain electrode  62  are preferably made of metal, in which the gate electrode  58  is preferably made of Schottky metal while the source electrode  60  and the drain electrode  62  are preferably made of ohmic contact metals. According to an embodiment of the present invention, each of the gate electrode  58 , source electrode  60 , and drain electrode  62  could include gold (Au), Silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), palladium (Pd), or combination thereof. Preferably, it would be desirable to conduct an electroplating process, sputtering process, resistance heating evaporation process, electron beam evaporation process, physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, or combination thereof to form electrode materials in the aforementioned recesses, and then pattern the electrode materials through one or more etching processes to form the gate electrode  58 , source electrode  60 , and the drain electrode  62 . This completes the fabrication of a HEMT according to an embodiment of the present invention. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.