Patent Publication Number: US-6657456-B1

Title: Programmable logic with on-chip DLL or PLL to distribute clock

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. 09/588,034, filed Jun. 5, 2000, now U.S. Pat. No. 6,292,016, which is a continuation of U.S. patent application Ser. No. 09/165,463, filed Oct. 2, 1998, now U.S. Pat. No. 6,130,552, which is a division of U.S. patent application Ser. No. 08/971,315, filed Nov. 17, 1997, now U.S. Pat. No. 5,963,069, which is a continuation of U.S. patent application Ser. No. 08/543,420, filed Oct. 16, 1995, now U.S. Pat. No. 5,744,991, which are incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates generally to clock distribution in integrated circuits and specifically to a clock distribution scheme using a phase-locked loop or a delay-locked loop in a programmable logic circuit. 
     As the level of integration in semiconductor integrated circuits (ICs) increases, signal delays due to parasitic resistance-capacitance loading become larger. This is especially true of high fan-out global signal lines such as synchronous clocks. Clock signals in modem programmable logic devices may drive several thousand registers. This is a considerable load to the clock driver. Clock tree structures can be implemented on-chip to minimize clock skew among registers. However, the base trunk clock driver must be capable of driving this clock tree structure and, as a result, a buffer delay of several nanoseconds is typically incurred. 
     One approach to clock distribution uses a phase-locked loop (PLL). This approach uses a phase-locked loop to synchronize a clock distribution signal to a reference clock signal. Since the phase-locked loop generates an internal clock signal and synchronizes it to the reference clock signal from an external source, the reference clock signal does not drive the clock tree structure. 
     However, some problems exist with implementing a PLL in a typical integrated circuit since the PLL uses analog devices such as a phase frequency detector (PFD), charge pump, and low pass filter. These problems include, among others, poor stability and performance in a noisy environment. 
     Therefore, it is desirable to use a circuit which achieves clock distribution while minimizing the number of components, thus reducing the area on the chip used by the clock distribution circuit. 
     SUMMARY OF THE INVENTION 
     The present invention is a programmable logic device (PLD) with an on-chip clock synchronization circuit to synchronize a reference clock signal. In one implementation, the clock synchronization circuit is a delay-locked loop (DLL) circuit and in another implementation, a phase-locked loop (PLL) circuit. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit provides a synchronized clock signal that is distributed throughout the programmable logic integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The synchronized clock may be programmably connected to or through such programmable resources as look-up tables, sequential machines, registers, function generators, programmable interconnect, multiplexers, and others. 
     The clock synchronization circuit improves the overall performance of the PLD or FPGA. In particular, the clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. A specific embodiment of the present invention achieves zero nanoseconds clock skew delay. By minimizing clock skew, the programmable integrated circuit&#39;s performance is improved because there will be no clock skew in the clocks received by individual programmable logical components of the integrated circuit. 
     In one embodiment, the present invention is a PLD with a digital DLL including a reference clock input for receiving an external reference signal, a feedback clock signal derived from the reference clock signal, and a digital phase detector connected to the reference clock signal and the feedback clock signal. The digital phase detector determines the phase difference between the reference clock signal and the feedback clock signal and outputs a phase error signal output. The DLL further includes a delay selector which is connected to the phase error signal and the reference clock signal. The delay selector outputs a synchronized clock output which may be used to generate the feedback clock signal. 
     In another embodiment, the programmable logic device includes an array of logic blocks configurable to perform logical functions. Each logic block has inputs and outputs. The programmable logic device includes an interconnect structure including first conductors in a first direction and second conductors in a second direction. The first conductors may be between rows of the array and the second conductors may be between columns of the array. The interconnect structure is configurable to connect signals from one logic block in the array to another logic block in the array. The programmable logic device includes clock synchronization circuitry to receive a reference clock signal and a feedback clock signal and to generate a synchronized clock output signal. The programmable logic device includes a multiplexer having a first input connected to the reference clock signal and a second input connected to the synchronized clock output signal. The reference clock signal or synchronized clock output signal is selectably coupled to an input of a logic block through the multiplexer. In an implementation, the clock synchronization circuit is a delay-locked loop circuit. The clock synchronization circuit minimizes skew for n clock signals, where each of the n clock signals is received at one of n logic blocks. 
     In a further embodiment, a programmable logic device includes a clock synchronization circuit which provides a plurality of synchronized clock output signals, each to a different logic block in the array. The clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks. 
    
    
     Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a block diagram of a digital system incorporating a programmable logic device integrated circuit; 
     FIG. 1B is a block diagram showing the overall architecture of a programmable logic device; 
     FIG. 1C is a simplified block diagram of a logic array block (LAB) of a programmable logic device; 
     FIG. 1D shows the basic functional blocks in a digital or analog delay-locked loop circuit of the present invention; 
     FIG. 2 shows a timing diagram of the signals in the circuit of FIG. 1D; 
     FIG. 3A is a diagram of a circuit for achieving a phase frequency detector function; 
     FIG. 3B is a timing diagram showing a reference clock and flip-flop input waveforms; 
     FIG. 4 shows a delay-locked loop block diagram using macro and micro phase detectors; 
     FIG. 5 shows a circuit diagram where synchronized or reference clocks are selectable for distribution to different parts of an integrated circuit; 
     FIG. 6 shows the circuit of FIG. 5 with more detail for one of the functional blocks; 
     FIG. 7 is a state diagram for the delay-locked loop block diagram of FIG. 4; 
     FIG. 8 shows a macro phase error detector circuit; 
     FIG. 9 shows a micro phase error detector circuit; 
     FIG. 10 shows a more detailed view of a logic element; and 
     FIG. 11 shows a logic element to logic element connection. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1A shows a block diagram of a digital system within which the present invention may be embodied. In the particular embodiment of FIG. 1A, a processing unit  101 A is coupled to a memory  105  and an I/O  111 A and incorporates a programmable logic device (PLD)  121 A. PLD  121 A may be specially coupled to memory  105 A through connection  131 A and to I/O  111 A through connection  135 A. The system may be a programed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, the system may be a general purpose computer, a special purpose computer (such as telecommunications equipment) optimized for an application-specific task such as programming PLD  121 A, or a combination of a general purpose computer and auxiliary special purpose hardware. 
     Processing unit  101 A may direct data to an appropriate system component for processing or storage, execute a program stored in memory  105 A or input using I/O  111 A, or other similar function. Processing unit  101 A may be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, programmable logic device programmed for use as a controller, or other processing unit. Furthermore, in many embodiments, there is often no need for a CPU. For example, instead of a CPU, one or more PLDs  121 A may control the logical operations of the system. 
     In some embodiments, processing unit  101 A may even be a computer system. In one embodiment, source code may be stored in memory  105 A, compiled into machine language, and executed by processing unit  101 A. Processing unit  101 A need not contain a CPU and in one embodiment, instructions may be executed by one or more PLDs  121 A. Instead of storing source code in memory  105 A, only the machine language representation of the source code, without the source code, may be stored in memory  105 A for execution by processing unit  101 A. Memory  105 A may be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, PC Card flash disk memory, tape, or any other storage retrieval means, or any combination of these storage retrieval means. 
     Processing unit  101 A uses I/O  111 A to provide an input and output path for user interaction. For example, a user may input logical functions to be programmed into programmable logic device  121 A. I/O  111 A may be a keyboard, mouse, track ball, digitizing tablet, text or graphical display, touch screen, pen tablet, printer, or other input or output means, or any combination of these means. In one embodiment, I/O  111 A includes a printer used for printing a hard copy of any processing unit  101 A output. In particular, using I/O  111 A, a user may print a copy of a document prepared using a word processing program executed using processing unit  101 A. In other cases, a user may print out a copy of the source code or a listing of the logical functions contained within PLD  121 A. 
     PLD  121 A may serve many different purposes within the system in FIG.  1 A. PLD  121 A may be a logical building block of processing unit  101 A, supporting its internal and external operations. PLD  121 A is programmed to implement the logical functions necessary to carry on its particular role in system operation. 
     FIG. 1B is a simplified block diagram of the overall internal architecture and organization of PLD  121 A of FIG.  1 A. Many details of PLD architecture, organization, and circuit design are not necessary for an understanding of the present invention and such details are not shown in FIG.  1 B. 
     FIG. 1B shows a six-by-six two-dimensional array of thirty-six logic array blocks (LABs)  200 A. LAB  200 A is a physically grouped set of logical resources that is configured or programmed to perform logical functions. The internal architecture of a LAB will be described in more detail below in connection with FIG.  1 C. PLDs may contain any arbitrary number of LABs, more or less than the PLD  121 A shown in FIG.  1 B. Generally, in the future, as technology advances and improves, programmable logic devices with even greater numbers of logic array blocks will undoubtedly be created. Furthermore, LABs  200 A need not be organized in a square matrix; for example, the array may be organized in a five-by-seven or a twenty-by-seventy matrix of LABs. 
     LAB  200 A has inputs and outputs (not shown) which may or may not be programmably connected to a global interconnect structure, comprising an array of global horizontal interconnects (GHs)  210 A and global vertical interconnects (GVs)  220 A. Although shown as single lines in FIG. 1B, each GH  210 A and GV  220 A line represents a plurality of signal conductors. The inputs and outputs of LAB  200 A are programmably connectable to an adjacent GH  210 A and an adjacent GV  220 A. Utilizing GH  210 A and GV  220 A interconnects, multiple LABs  200 A may be connected and combined to implement larger, more complex logic functions than can be realized using a single LAB  200 A. 
     In one embodiment, GH  210 A and GV  220 A conductors may or may not be programmably connectable at intersections  225 A of these conductors. Moreover, GH  210 A and GV  220 A conductors may make multiple connections to other GH  210 A and GV  220 A conductors. Various GH  210 A and GV  220 A conductors may be programmably connected together to create a signal path from a LAB  200 A at one location on PLD  121 A to another LAB  200 A at another location on PLD  121 A. Furthermore, an output signal from one LAB  200 A can be directed into the inputs of one or more LABs  200 A. Also, using the global interconnect, signals from a LAB  200 A can be fed back into the same LAB  200 A. In other embodiments or the present invention, only selected GH  210 A conductors are programmably connectable to a selection of GV  220 A conductors. Furthermore, in still further embodiments, GH  210 A and GV  220 A conductors may be specifically used for passing signal in a specific direction, such as input or output, but not both. 
     The PLD architecture in FIG. 1B further shows at the peripheries of the chip, input-output drivers  230 A. Input-output drivers  230 A are for interfacing the PLD to external, off-chip circuitry. FIG. 1B shows thirty-two input-output drivers  230 A; however, a PLD may contain any number of input-output drivers, more or less than the number depicted. Each input-output driver  230 A is configurable for use as an input driver, output driver, or bidirectional driver. 
     FIG. 1C shows a simplified block diagram of LAB  200 A of FIG.  1 B. 
     LAB  200 A is comprised of a varying number of logic elements (LEs)  300 A, sometimes referred to as “logic cells,” and a local (or internal) interconnect structure  310 A. LAB  200 A has eight LEs  300 A, but LAB  200 A may have any number of LEs, more or less than eight. In a further embodiment of the present invention, LAB  200 A has two “banks” of eight LEs for a total of sixteen LEs, where each bank has separate inputs, outputs, control signals, and carry chains. 
     A general overview of LE  300 A is presented here, sufficient to provide a basic understanding of the present invention. LE  300 A is the smallest logical building block of a PLD. Signals external to the LAB, such as from GHs  210 A and GVs  220 A, are programmably connected to LE  300 A through local interconnect structure  310 A, although LE  300 A may be implemented in many architectures other than those shown in FIGS. 1A-C. In one embodiment, LE  300 A of the present invention incorporates a function generator that is configurable to provide a logical function of a number of variables, such a four-variable Boolean operation. As well as combinatorial functions, LE  300 A also provides support for sequential and registered functions using, for example, D flip-flops. 
     LE  300 A provides combinatorial and registered outputs that are connectable to the GHs  210 A and GVs  220 A, outside LAB  200 A. Furthermore, the outputs from LE  300 A may be internally fed back into local interconnect structure  310 A; 
     through local interconnect structure  310 A, an output from one LE  300 A may be programmably connected to the inputs of other LEs  300 A, without using the global interconnect structure&#39;s GHs  210 A and GVs  220 A. Local interconnect structure  310 A allows short-distance interconnection of LEs, without utilizing the limited global resources, GHs  210 A and GVs  220 A. Through local interconnect structure  310 A and local feedback, LEs  300 A are programmably connectable to form larger, more complex logical functions than can be realized using a single LE  300 A. Furthermore, because of its reduced size and shorter length, local interconnect structure  310 A has reduced parasitics compared to the global interconnection structure. Consequently, local interconnect structure  310 A generally allows signals to propagate faster than through the global interconnect structure. 
     The present invention may be used in various places in many types of integrated circuits, including a PLD as described above. For example, in a PLD, the present invention may be used to drive a clock signal throughout the PLD components, with minimal clock skew between the components. In one embodiment of the present invention, there is no clock skew between the components. A clock generated using the techniques of the present invention may be routed to the look-up tables, sequential machines, registers, function generators, programmable interconnect, multiplexers, I/Os, and other components of the PLD. 
     FIG. 1D shows the basic functional blocks in a DLL circuit  100 , which may be embodied in the digital system of FIG.  1 A. The circuit may be digital, analog, or a combination of both. In FIG. 1D, a reference clock  102  is provided from a source external to circuit  100 . Reference clock  102  is input along with an internal, or “feedback” clock  104 , to PFD  106 . PFD  106  outputs signals UP  108  and DWN  110  which are input to current pump  112 . PFD  106  detects frequency and phase differences between reference clock  102  and internal clock  104 . 
     FIG. 2 shows a timing diagram of signals in the DLL circuit  100  of FIG.  1 D. In FIG. 2, reference clock  102  is shown as waveform  150 , while internal clock  104  is shown as waveform  152 . The phase difference between reference clock waveform  150  and internal clock waveform  152  is shown, for example, at  154 . Because internal clock waveform  152 , rises from low to high, before reference clock waveform  150 , the internal clock signal is said to “lead” the reference clock signal. 
     The amount of lead in the internal clock waveform  152  is used to generate a signal on UP signal  108 . Signal  108  is in the form of a square wave having a duration of the same interval as the lead time between clock waveforms  150  and  152 . Signal  108  is shown at  160  in the timing diagram of FIG.  2 . Similarly, the case where the internal clock waveform  152  “lags,” the reference clock waveform  150  is shown at  162 . In this case, PFD  106  outputs a signal on the DWN signal line to produce a square wave with a duration equivalent to the amount of lag between the clock waveforms. DWN signal  110  is shown at  164  in the timing diagram of FIG.  2 . 
     Returning to FIG. 1D, the UP and DWN signals  108  and  110  respectively, are input to current pump  112 . Current pump  112  sends a charge to low pass filter  114  corresponding to signals  108  and  110  from PFD  106 . The output of low pass filter  114  is an analog voltage level as shown by waveform  166  of FIG.  2 . This analog signal output by low pass filter  114  is shown as signal  116  in FIG.  1 D. Signal  116  is fed to delay chain  118  to control the amount of delay applied to the reference clock signal. The delayed reference clock signal is output at  120  to delay element  122 . The output  120  is also the clock output distributed to components on the integrated circuit in which the digital/analog DLL of FIG. 1D is acting as the clock distribution circuit. Delay element  122  serves to further delay the already delayed reference clock signal from delay chain  118 . This further delay compensates for internal delays across a chip on which the circuit is fabricated. By matching all of the delays on the chip the DLL can compensate for the worst case delay. The output of delay element  122  is used as the input to PFD  106 . 
     The method of distributing the clock throughout the integrated circuit may include programmable delay elements. For example, the clock output may be distributed to components of an integrated circuit through a plurality of programmable delay elements. These programmable delay elements may programmed to provide a uniform delay for the synchronized clock throughout the integrated circuit. For example, for a component a longer distance away from the clock generator, a longer programmable delay may be used that for a component closer to the clock generator. Programmable delays may be used in this way to equalize the delay and skew of the clock signal at the various components, regardless of their distance from the clock generator. In a preferred embodiment, the programmable delay elements may be programmable metal elements, providing an RC delay. Similarly, delay chain  118  and delay element  122  may be implemented using programmable delay elements. 
     There are many benefits due to clock synthesis. For example, on many integrated circuits, a clock signal is routed long distances from the clock source. The present invention permits these long runs of a clock signal line, and minimizes the clock skew between the signal lines. A zero nanoseconds clock skew may be obtained with the present invention. By minimizing the skew between the clock lines, this may improve, for example, the setup and hold times for components, functional blocks, and I/Os on the integrated circuit. 
     There are many ways of implementing the functional blocks of FIG.  1 D. Next, some of the possible implementations are discussed as preferred embodiments. 
     FIG. 3A is a diagram of a circuit for achieving the PFD function shown in FIG.  1 D&#39;s PFD  106 . FIG. 3A shows a digital approach to implementing a PFD. The circuit of  3 A is only a phase detector, since it is incapable of detecting frequency errors, as discussed below. An advantage to using the digital phase-only circuit detector of FIG. 3A is that the space required to fabricate the circuit on a silicon substrate is small. Also, the circuit of FIG. 3A uses standard digital components and is easily fabricated in an integrated circuit. 
     FIG. 3A shows two flip-flops, FF 1  and FF 2 . These flip-flops are of the D-latch type as is commonly known in the art. Each flip-flop is clocked by the reference clock signal, REF CLK. The input to each flip-flop is derived from the feedback clock signal shown as the internal clock signal  104  in FIG.  1 D. FF 1  receives a delayed feedback clock. The delay is due to inverters at  180 . The use of two inverters is arbitrary and affects the phase error detection as discussed below. It will be apparent that any number of inverters and/or buffers may be used in place of the two inverters at  180  to create a delay for the input signal to FF 1 . FF 2  receives the undelayed feedback clock as shown in FIG.  3 A. 
     FIG. 3B is a timing diagram showing the reference clock signal, FF 1  input signal and FF 2  input signal, respectively, as waveforms  182 ,  184  and  186 . Since the input to FF 1 , labelled “FF 1  D,” is delayed with respect to the input of FF 2 , there is an interval, “d,” between the leading edges of each of these waveforms as shown in FIG.  3 B. When the feedback clock is synchronized to the reference clock, each rising edge of the reference clock occurs between the leading edges of the FF 1  and FF 2  signal inputs. An example is at time t=1 in the timing diagram of FIG. 3B where the leading edge of the reference clock occurs at t=1, in between the occurrences of the leading edge of the FF 2  D and FF 1  D waveforms. 
     Combinational logic at  188  in FIG. 3A receives the outputs of FF 1  and FF 2  and generates a combined signal output. For example, combinational logic  188  could be a simple 2-input exclusive OR gate with the inputs to the exclusive OR gate being the outputs of each of FF 1  and FF 2 . In this case, in normal operation when the feedback clock is synchronized to the reference clock in normal operation, the output of combinational logic  188  will be high, or a “1.” This is because the outputs of FF 1  and FF 2  will not be the same at the leading edge of the reference clock since the reference clock goes high after FF 2  has gone high and before FF 1  has gone high. 
     However, in the case where the feedback clock is not synchronized closely to the reference clock, (i.e., the phase error between the reference clock and the feedback clock is large), then the outputs of FF 1  and FF 2  are the same and the output of the exclusive OR gate (i.e., the output of combinational logic  188 ) is a low or “0” logic level. 
     For example, where the input to FF 2  has a leading edge which does not rise until after t=1, then the reference clock leading edge samples a low signal on both the inputs to FF 1  and FF 2 . Also, where the feedback clock is leading the reference clock sufficiently so that the leading edge of FF 1  (which is delayed) occurs before t=1, the reference clock will, likewise, sample a high signal on both of the inputs to FF 1  and FF 2  resulting in a low logic output from combinational logic  188 . 
     Another possibility for combinational logic  188 , is to use an AND gate to output a high logic signal when the feedback clock is leading the reference clock by a sufficient margin so that high signals on both of the FF 1  and FF 2  inputs are sampled. A NOR gate could be used to output a logic high when the feedback clock is sufficiently lagging the reference clock so that the reference clock leading edge samples a low signal on both of the FF 1  and FF 2  inputs. In this latter case, there are two lines output from combinational logic  188 . Many approaches, including different combinations of gates, to detect and generate a phase error signal are possible. 
     The present invention applies digital delay-locked loops (DDLL), analog delay-locked loops, (ADLL), and phase-locked loops (PLL), to name a few. An example of an embodiment with DDLL is described below. 
     FIG. 4 shows a digital DLL (DDLL) block diagram using macro and micro phase detectors. This circuit functions similarly to the circuits discussed above for a DLL, except that the phase error detection and delay selection is implemented in two separate stages amounting to a coarse and fine adjustment of the delay. Further, the circuit of FIG. 4 uses standard digital parts such as a shift register and a counter to implement the delay selection function, shown as delay chain  118  of FIG. 1D, discussed above. In FIG. 4, block diagram  200  shows macro phase detector  202  having a REF CLK input at  204  and a feedback clock input at  206 . 
     Macro phase detector  202  can be implemented by a circuit similar to that of FIG. 3A discussed above. Macro phase detector  202  outputs a left/right/idle signal  208  to shift register  210 . The left/right/idle signal can be one or more lines that indicate to shift register  210  whether the reference clock is leading or lagging the internal clock by at least a fixed time duration called the macro error threshold. 
     Micro phase detector  218  functions similarly to macro phase detector  202 , except that micro detector  218  is sensitive to a smaller fixed time duration, (i.e., the micro error threshold), than macro detector  202 . In other words, micro phase detector  218  will have a smaller value for d, shown in FIG. 3B, so that micro phase detector  218  can be used to detect smaller phase differences between the internal, or feedback, clock and reference clock. Micro phase detector  218  outputs up/down/idle signal  222  to counter  220 . 
     Examples of a macro phase error detector circuit and a micro phase error detector circuit are shown in FIGS. 8 and 9, respectively. In FIG. 8, signals NDN, NUP, and  1 DLE implement the left/right/idle signal  208  of FIG.  4 . The left/right/idle signal is implemented with three signals, NDN, NUP, and  1 DLE for controlling shift register  210 . When NUP is active shift register  210  shifts right, when NDN is active shift register  210  shifts left, when  1 DLE is active no shifting occurs. 
     The micro phase error detector circuit of FIG. 9 operates similarly to the macro phase error detector circuit of FIG.  8 . In FIG. 9, signals DN, UP, and LOCK are used to, respectively, increment, decrement, and preserve a count in counter  220 . The micro phase error detector circuit of FIG. 9 is provided with control signals INCWIN and DECWIN for modifying the delay “window” to make the circuit more or less sensitive to timing differences between the CLK and NREFCLK signals. Signals INCWIN and DECWIN may be controlled by external circuitry, such as other circuitry on the same chip as the delay-locked loop circuit. 
     Shift register  210 , along with variable macro delay  212 , perform a macro delay selector function to delay the reference clock signal according to the phase error detected by macro phase detector  202 . In a preferred embodiment, shift register  210  is preset with a value that is shifted according to the signal  208  from macro phase detector  202 . For example, shift register  210  can be preset with a value such as binary 11100 (or 11000; 10000) that is shifted left when macro phase detector  202  indicates that the feedback clock on line  206  is leading the reference clock  204 . Likewise, shift register  210  could shift the preset value to the right when macro phase detector  202  indicates that the feedback clock  206  lags the reference clock  204 . The shifting left or right of the value of in shift register  210  will, respectively, increase or decrease the value. This value is output to variable macro delay  212  via line  211 . Variable macro delay  212  can be, for example, a multiplexer that selects one of several delay values to apply to the reference clock input to variable macro delay  212  via line  213 . The choice of using a counter or shift register devices can be made according to layout considerations and speed of the specific device. The preferred embodiment uses a shift register for the macro delay and a counter for the micro delay. 
     Once the delay is applied by variable macro delay  212 , the delayed reference clock signal is output to variable micro delay  216  via line  215 . Variable micro delay  216  and counter  220  form a micro delay selector similar to the macro delay selector described above. Micro phase detector  218  outputs the up/down/idle signal  222  to counter  220 . Counter  220  uses the signal  222  to increment or decrement a count value depending on whether the micro phase detector  218  determines that the feedback clock signal on line  230  leads, or lags, respectively, the reference clock signal on line  232 . For example, if micro phase detector  218  determines that the feedback clock signal  230  leads the reference clock signal  232 , then micro phase detector will output an up signal on signal  222  to direct counter  220  to increment its count value. 
     The count value is transferred to variable micro delay  216  along line  219 . Variable micro delay  216  selects one of several delay values to apply to the delayed reference clock on line  215 . This generates a further delayed reference clock signal that is output by variable micro delay  216  onto line  217 . Note that CLK OUT signal is obtained from line  217  as the clock signal to be distributed to the various components on the integrated circuit for which the digital delay-locked loop (DDLL) of FIG. 4 is acting as the clock distribution circuit. Finally, lumped delay  214  receives the further delayed reference clock signal on line  217 , applies a fixed delay, and outputs the feedback clock signal at  221 . Lumped delay  214  matches loading seen on the chip. 
     FIG. 5 shows a circuit diagram where a PLL or DLL (P/DLL) generates a synchronized clock signal  302  from a reference clock signal input at pad  300  and where the synchronized or reference clocks are selectable for distribution to different parts of the integrated circuit on which the P/DLL resides. The advantage to this scheme is that the P/DLL is placed near the pads so that the reference clock is not delayed much before it reaches the P/DLL. For the P/DLL to work properly a very stable reference clock must be provided. If the reference clock is not stable then an external circuit can switch the P/DLL off and the reference clock can be used to directly feed the circuitry on the chip. 
     The circuit shown in FIG. 5 allows either the synchronized or reference clocks to be distributed to five different areas of an integrated circuit, or chip. The selection of one of the clocks is performed by the five multiplexers shown as MUX  304 ,  306 , 308 , 310 , and  312 . The multiplexers are used to select one oft he two clocks via control signals (not shown) which may be driven by, for example, a register that is loadable under the direction of a micro processor on the chip. Delay elements L 1 -S are used to match the delay across the chip. By modifying the amount of delay at each of the elements through line matching, the GCLKs can be brought into close synchronization. The synchronized clock is output by P/DLL circuitry in block  320  and may be, for example, the DLL circuit discussed above in connection with FIGS. 1-4. 
     FIG. 6 shows the circuit of FIG. 5 with more detail in P/DLL block  320  of FIG.  5 . FIG. 6 shows that any of three synchronization approaches can be selected by using demultiplexer  350  and multiplexer  352  within P/DLL block  354 . By using demultiplexer  350  and multiplexer  352 , any of the three clock synchronization systems shown as DDLL, ADLL, and APLL may be selected. These clock synchronization systems are, respectively, a digital delay-locked loop, an analog delay-locked loop and an analog phase-locked loop. The digital delay-locked loop may be implemented by, for example, a circuit as shown in FIG. 1D, and may include any of the additional circuit details discussed in FIGS. 2-4. The analog delay-locked loop can be implemented with the circuit as shown in FIG. 1D by using an analog design approach as is known in the art. The analog phase-locked loop may be implemented with an analog phase-locked loop design as is known in the art. 
     FIG. 7 is a state diagram  400  for the delay-locked loop circuit of FIG.  4 . In FIG. 7, at state  402  the circuit of FIG. 4 is initialized. This includes, for example, resetting shift register  210  and counter  220 . Also, if the circuit of FIG. 3A is used to perform phase detection then flip-flops FF 1  and FF 2  may be reset. From state  402  macro phase detector  202  determines whether to shift up or down. State  404  represents the state where the feedback clock is lagging behind the reference clock so that the shift register shifts up. State  406  represents the state where the feedback clock is leading the reference clock so that the shift register shifts down. 
     State  404  remains the current state for as long as the circuit of FIG. 4 is in a condition where the feedback clock signal lags the reference clock signal by an amount that equals or exceeds a macro error threshold. In the preferred embodiment, the value for the macro error threshold is 1.5 nanoseconds while the micro error threshold, or window, is 0.2 nanoseconds. As long as there is at least this much delay between the feedback clock signal and the reference clock signal the state remains at state  404  and shift register  210  is shifted up. An analogous operation pertains to state  406  where the shift register is shifted down as long as the feedback clock leads the reference clock by an amount that is greater than the macro error threshold. 
     Assuming that the phase error between the feedback and reference clocks is no longer greater than the macro error threshold, the state progresses from state  404  to state  414 , or from state  406  to state  418 . At state  414 , the micro phase detector will increment the counter  220  as long as the feedback clock lags the reference clock by at east the micro error threshold amount. Similarly, at state  418  the micro phase detector decrements the counter as long as the feedback clock leads the reference clock by at least the micro error threshold amount. If the counter overflows at state  414  then states  410  and  408  are entered to reset the counter. The counter reset changes the micro delay to approximately match the delay change in the macro delay. If the counter underflows from the decrement operation at state  418  then states  412  and  408  are entered to reset the counter. From state  408 , state  404  is entered if the counter has rolled over to perform a macro adjustment to increase the delay to the feedback signal. Similarly, if the counter has rolled under then from state  408  state  406  is entered to perform a macro adjustment to decrease the delay to the feedback signal. 
     Assuming, from either of states  414  or  418  that the feedback clock attains synchronization with the reference clock, then state  416  is entered to indicate that the feedback and reference clocks are locked together. This occurs when the phase error difference between the two clock signals is less than the micro error threshold. Should the phase error increase beyond the micro error threshold then either state  414  or state  418  is again entered depending on whether the phase error indicates that the feedback clock leads the reference clock or lags the reference clock, respectively. 
     FIG. 10 shows a more detailed view of a logic element having a function generator or look-up table connected to a register. A clock generated using the techniques of the present invention may be routed to the look-up table or function generator or register. 
     FIG. 11 shows a logic element to logic element connection. This connection is made without utilizing the global interconnect. 
     In the foregoing specification, the invention has been described with reference to a specific exemplary embodiment there of. It will, however, be evident that various modifications and changes may be made without departing from the broader spirit and scope of the invention as set forth in the appended claims. Many such changes or modifications will be readily apparent to one of ordinary skill in the art. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense, the invention being limited only by the provided claims.