Patent Publication Number: US-6982910-B2

Title: Reverse voltage generation circuit

Description:
CROSS-REFERENCE OF THE INVENTION 
   This invention is based on Japanese Patent Application No. 2004-042462, the content of which is incorporated herein by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to a reverse voltage generation circuit that generates a voltage of the opposite polarity to an input voltage. 
   2. Description of the Related Art 
   The reverse voltage generation circuit is used as a power supply to an LCD (Liquid Crystal Display) driver circuit that provides an active matrix type LCD panel with gate signals, for example. The reverse voltage generation circuit generates a negative voltage (−15V) from a positive voltage (+15V), for example. 
     FIG. 5  is a circuit diagram of a reverse voltage generation circuit according to prior art. The reverse voltage generation circuit is composed of a first and a second charge transfer MOS transistors TR 21  and TR 22  of an N-channel type, a first and a second level shift circuits LS 21  and LS 22  which control turning on and off of the first and the second charge transfer MOS transistors TR 21  and TR 22  respectively, a capacitor  10  (usually a capacitor externally connected to an integrated circuit) and a driver circuit  11  that is a CMOS inverter made of a first driver MOS transistor TR 23  of a P-channel type and a second driver MOS transistor TR 24  of the N-channel type. 
   The first and the second charge transfer transistors TR 21  and TR 22  are simply referred to as TR 21  and TR 22  in the following explanation, as well as referring to the first and the second driver MOS transistors TR 23  and TR 24  simply as TR 23  and TR 24 . 
   An example operation of the circuit will be described hereafter. An input signal S 23  to a gate of TR 23  and an input signal S 24  to a gate of TR 24  are turned to a low level (Vss) to turn TR 23  on and turn TR 24  off, after TR 22  is turned off by the second level shift circuit LS 22 . Then TR 21  is turned on by the first level shift circuit LS 21 . As a result, a node N 23  that is an output node of the driver circuit  11  is set to a voltage VH, while a node N 21  that is a point of connection between TR 21  and TR 22  is pulled to a ground voltage (reference voltage) Vss. 
   Next, after turning TR 21  off, the input signal S 23  to the gate of TR 23  and the input signal S 24  to the gate of TR 24  are turned to a high level (VH) to turn TR 23  off and turn TR 24  on. After that, when TR 22  is turned on, a voltage at the node N 21  is lowered due to a capacitive coupling through the capacitor  10 , a current flows from the node N 22  to the node N 21  through TR 22  and a voltage at the node N 22  and a voltage at an output terminal  20  connected to the node N 22  are lowered. 
   Next, after turning TR 22  off, the input signal S 23  to the gate of TR 23  and the input signal S 24  to the gate of TR 24  are turned to the low level (Vss) to turn TR 23  on and turn TR 24  off. Then TR 21  is turned on by the first level shift circuit LS 21  to return to the initial state. Repeating the operation described above brings the node N 22  to −VH that is a reverse polarity voltage of the voltage VH. Therefore, the negative voltage −VH is generated from the positive voltage VH with this reverse voltage generation circuit. 
   The input signals S 21  and S 22  to the first and the second level shift circuits LS 21  and LS 22  are determined based on a voltage-logic assuming the voltage VH as the high level and the ground voltage Vss as the low level. The first and the second level shift circuits LS 21  and LS 22  convert the input signals swinging between the voltage VH and the ground voltage Vss to signals swinging between the voltage VH and a voltage at the node N 22 , in order that TR 21  and TR 22  are completely turned off. When the reverse voltage generation circuit reaches a stationary state after repeating the operation described above, the voltage at the node N 21  swings between the ground voltage Vss and −VH and the voltage at the node N 22  becomes −VH. 
   The reverse voltage generation circuit described above has been manufactured by a CMOS process using an N-type semiconductor substrate. Relevant descriptions on the technologies mentioned above are provided, for example, Japanese Patent Publication No. 2001-258241. 
   A lowest voltage provided to an LSI (Large Scale Integration) is applied to a substrate of N-channel MOS transistors in an ordinary LSI in order to reverse-bias P-N junctions. In a reverse voltage generation circuit LSI that generates a negative voltage from a positive voltage, however, a substrate of an N-channel MOS transistor connected to the generated voltage needs to be connected to the generated voltage or a voltage lower than the generated voltage, since the reverse voltage generation circuit generates the voltage lower than the voltage provided to the LSI. 
   And if the substrate voltage of all N-channel MOS transistors in the reverse voltage generation circuit is unified to the generated voltage, driving capacity of an N-channel transistor having a source connected to the ground voltage Vss (TR 21  and TR 24 , for example) is reduced since a back-gate bias is applied to the N-channel MOS transistor. Therefore, the N-channel MOS transistors are separated from each other with individual P-wells. 
   Increasing need in recent years for integrating the reverse voltage generation circuit into an LSI as a power supply requires integrating the reverse voltage generation circuit not only into an LSI using an N-type semiconductor substrate but also into an LSI using a P-type semiconductor substrate. 
   However, when the reverse voltage generation circuit of  FIG. 5  is formed in the P-type semiconductor substrate, there arises a problem described below. The N-channel MOS transistors TR 21 , TR 22  and TR 24  are formed in the P-type semiconductor substrate. And the substrate voltage of these transistors is made to be the output voltage of the reverse voltage generation circuit (the output voltage of TR 22 ). However, the output voltage is not yet generated at the time the power supply is turned on (at the beginning of the operation of the circuit). As a result, the substrate voltage of the transistors is unstable when the power supply is turned on. If the substrate voltage is somewhat higher than the ground voltage Vss, the transistor with its source connected to the ground voltage Vss is back-gate biased with a reverse voltage, leading to a reduction in a threshold voltage and possibly to causing a leakage current in the transistor. 
   SUMMARY OF THE INVENTION 
   A reverse voltage generation circuit of this invention includes a first charge transfer MOS transistor having a first diffused region connected to a ground, a second charge transfer MOS transistor having a first diffused region connected to a second diffused region of the first charge transfer MOS transistor, a first driver MOS transistor having a first diffused region to which a power supply voltage VH is provided, a second driver MOS transistor having a first diffused region connected to a second diffused region of the first driver MOS transistor and a second diffused region connected to the ground, a capacitor with one end connected to a connecting point between the first charge transfer MOS transistor and the second charge transfer MOS transistor and the other end connected to a connecting point between the first driver MOS transistor and the second driver MOS transistor and a control circuit that controls turning on and off of the first and the second charge transfer MOS transistors and the first and the second driver MOS transistors, and outputs a reverse voltage −VH that is an inverted polarity voltage of the power supply voltage VH from a second diffused region of the second charge transfer MOS transistor. The first charge transfer MOS transistor and the first and the second driver MOS transistors are formed of a P-channel type, while the second charge transfer MOS transistor is formed of an N-channel type. The second charge transfer MOS transistor is formed in a surface of a P-type semiconductor substrate, the first charge transfer MOS transistor is formed in a first N-well formed in the P-type semiconductor substrate and its first diffused region is connected to the first N-well, the first driver MOS transistor is formed in a second N-well formed in the P-type semiconductor substrate and its first diffused region is connected to the second N-well and the second driver MOS transistor is formed in a third N-well formed in the P-type semiconductor substrate and its first diffused region is connected to the third N-well. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram showing a reverse voltage generation circuit according to an embodiment of this invention. 
       FIG. 2  is a circuit diagram showing a level shift circuit according to the embodiment of this invention. 
       FIG. 3  is a cross-sectional view showing MOS transistors constituting the reverse voltage generation circuit according the embodiment of this invention. 
       FIG. 4  is a timing chart showing an operation of the reverse voltage generation circuit according to the embodiment of this invention. 
       FIG. 5  is a circuit diagram showing a reverse voltage generation circuit according to a prior art. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   A reverse voltage generation circuit according to an embodiment of this invention will be explained referring to  FIG. 1  hereafter. 
   The reverse voltage generation circuit is formed in a P-type semiconductor substrate and includes a first charge transfer MOS transistor TR 11  of a P-channel type, a second charge transfer MOS transistor TR 12  of an N-channel type and a driver circuit  15  made of an EE (Enhancement-Enhancement) inverter including a first driver MOS transistor TR 13  of the P-channel type and a second driver MOS transistor TR 14  of the P-channel type. 
   The reverse voltage generation circuit further includes a level shift circuit LS 20  which converts an input signal S 10  swinging between a first power supply voltage Vdd and a ground voltage (reference voltage) Vss to a signal swinging between a second power supply voltage VH (VH&gt;Vdd) and the ground voltage Vss, a timing control circuit  30  which generates timing control signals S 11 , S 12 , S 13  and S 14  based on an output of the level shift circuit LS 20  and controls turning on and off of the first and the second charge transfer MOS transistors TR 11  and TR 12  and the first and the second driver MOS transistors TR 13  and TR 14  according to the timing control signals and a capacitor  10  (a capacitor externally connected to an integrated circuit, for example) connected between a connecting point (node N 11 ) between the first charge transfer MOS transistor TR 11  and the second charge transfer MOS transistor TR 12  and an output node (node N 13 ) of the driver circuit  15 . 
   The reverse voltage generation circuit outputs a voltage −VH, a reverse polarity voltage of the second power supply voltage VH, from an output terminal  20  connected to a second diffused region (hereafter referred to as a drain) (node N 12 ) of the second charge transfer MOS transistor TR 12 . The first and the second charge transfer transistors TR 11  and TR 12  are simply referred to as TR 11  and TR 12  in the following explanation, as well as referring to the first and the second driver MOS transistors TR 13  and TR 14  simply as TR 13  and TR 14 . 
     FIG. 2  is a circuit diagram showing the level shift circuit LS 20 . The input signal S 10  (clock signal) is applied to a non-inverted input terminal (+) of a comparator  41  while the input signal S 10  inverted by an inverter  40  is applied to an inverted input terminal (−) of the comparator  41 . The comparator  41  is provided with the second power supply VH as a positive power supply voltage and a voltage V 12  at the node N 12  as a negative power supply voltage. An output of the comparator  41  is applied to an inverter  42 . The inverter  42  is also provided with the same positive power supply voltage VH and the negative power supply voltages V 12  as the comparator  41 . And the inverter  42  outputs a level-shifted voltage. The input signal S 10  swinging between Vdd and Vss can be converted to a signal swinging between VH and the voltage V 12  at the node N 12  with the level shift circuit LS 20 . 
   Next, device structures of the first and the second charge transfer MOS transistors TR 11  and TR 12  and the first and the second driver transistors TR 13  and TR 14  will be explained referring to  FIG. 3 . The transistors TR 11 , TR 12 , TR 13  and TR 14  are formed in a P-type semiconductor substrate  50 . 
   TR 11  is formed in a first N-well  51  formed in a surface of the P-type semiconductor substrate  50 . A P + -type first diffused region (hereafter referred to as a source layer)  53  of TR 11  is connected with the first N-well  51  through an N + -type layer  52  formed in a surface of the first N-well  51 . TR 11  is electrically separated from the P-type semiconductor substrate  50  and the other transistors with the first N-well  51 . The ground voltage Vss is applied to the P + -type source layer  53 . As a result, a voltage of the first N-well  51  is stabilized at Vss, not being influenced by fluctuation in voltage of the P-type semiconductor substrate  50  or the other transistors and keeping TR 51  from the back-gate bias effect. 
   TR 12  is formed in the surface of the P-type semiconductor substrate  50 . An N + -type first diffused region (hereafter referred to as a source layer)  55  of TR 12  is connected to a P + -type second diffused region (hereafter referred to as a drain layer)  54  of TR 11 . An N + -type second diffused region (hereafter referred to as a drain layer)  56  of TR 12  is connected to the P-type semiconductor substrate  50  through a P + -type layer  57  formed in the surface of the P-type semiconductor substrate  50 . Although the P-type semiconductor substrate  50  is set at the output voltage of the reverse voltage generation circuit generated at the drain layer  56  of TR 12 , the back-gate bias effect is prevented because the drain layer  56  is connected with the P-type semiconductor substrate  50 . 
   TR 13  is formed in a second N-well  58  formed in the surface of the P-type semiconductor substrate  50 . A P + -type first diffused region (hereafter referred to as a source layer)  60  of TR 13  is connected with the second N-well  58  through an N + -type layer  59  formed in a surface of the second N-well  58 . TR 13  is electrically separated from the P-type semiconductor substrate  50  and the other transistors with the second N-well  58 . The second power supply voltage VH is applied to the source layer  60 . As a result, a voltage of the second N-well  58  is stabilized at VH, not being influenced by fluctuation in voltage of the P-type semiconductor substrate  50  or the other transistors and keeping TR 13  from the back-gate bias effect. 
   TR 14  is formed in a third N-well  62  formed in the surface of the P-type semiconductor substrate  50 . A P + -type first diffused region (hereafter referred to as a source layer)  64  of TR 14  is connected with the third N-well  62  through an N + -type layer  63  formed in a surface of the third N-well  62 . TR 14  is electrically separated from the P-type semiconductor substrate  50  and the other transistors with the third N-well  62 . As a result, a voltage of the third N-well  62  is stabilized at a voltage of the source layer  64 , not being influenced by fluctuation in voltage of the P-type semiconductor substrate  50  or the other transistors and keeping TR 14  from the back-gate bias effect. 
   Next, an example of operation of the reverse voltage generation circuit will be explained referring to  FIG. 4 .  FIG. 4  is an operational timing chart of the circuit in a stationary state. After the signal S 12  is turned to the low level (the voltage V 12  at the node N 12 ) to turn TR 12  off, the input signal S 13  to a gate of TR 13  is turned to the low level (V 12 ) and the input signal S 14  to a gate of TR 14  is turned to the high level (VH) by the timing control circuit  30  to turn TR 13  on and turn TR 14  off. 
   Then the signal S 11  is turned to the low level (V 12 ) to tu TR 11  on. As a result, the node N 13  that is the output node of the driver circuit  15  is set to the voltage VH while the node N 11  that is the connecting point between TR 11  and TR 12  is pulled to the ground voltage Vss. The reason why TR 12  is turned off at first is to prevent a reverse current from the node N 11  to the node N 12  through TR 12 . 
   Next, after the signal S 11  is turned to the high level (VH) to turn TR 11  off, the input signal S 13  to the gate of TR 13  is turned to the high level (VH) and the input signal S 14  to the gate of TR 14  is turned to the low level (V 2 ) to turn TR 13  off and TR 14  on. As a result, the voltage at the node N 13 , that is the output node of the driver  15 , varies from VH to Vss and the voltage at the node N 11  is pulled down by capacitive coupling through the capacitor  10 . Then, by turning the signal S 12  to the high level (VH) to turn TR 12  on, a current flows from the node N 12  to the node N 11  to lower the voltage V 12  at the node N 12  and thus the voltage at the output terminal  20  that is connected to the node N 12 . The reason why the output of the driver circuit  15  is varied after turning TR 11  off is to prevent a reverse current from the ground to the node N 11  through TR 11  from occurring. 
   Next, after the signal S 12  is turned to the low level (V 12 ) to turn TR 12  off, the input signal S 13  to the gate of TR 13  is turned to the low level (V 12 ) and the input signal S 14  to the gate of TR 14  is tued to the high level (VH) to turn TR 13  on and TR 14  off. Then the signal S 11  is turned to the low level (V 12 ) to turn TR 11  on, resuming to the initial state. Repeating the operation described above brings the node N 12  to −VH that is a reverse voltage of the second power supply voltage VH. 
   It is made possible according to the embodiment as described above that the negative voltage −VH is obtained from the positive voltage VH, and that the leakage current due to the back-gate bias effect is prevented since the P-channel transistors TR 11 , TR 13  and TR 14  are formed in the first, the second and the third N-wells  51 ,  58  and  62  respectively and electrically separated from each other and the P-type semiconductor substrate  50 . 
   Although the reverse voltage generation circuit in the embodiment generates the negative voltage (−15V, for example) from the positive voltage (+15v, for example), it is also possible to generate a positive voltage (+15V, for example) from a negative voltage (−15V, for example) based on the same technical idea. In this case, an N-type semiconductor substrate is used instead of the P-type semiconductor substrate  50  and the conductivity type of the wells and the channel types of the MOS transistors are reversed. 
   To describe more specifically, the first charge transfer MOS transistor TR 11 , the first driver MOS transistor TR 13  and the second driver MOS transistor TR 14  are made of N-channel MOS transistors and each of them is formed in an individual P-well isolated from each other. The second charge transfer MOS transistor TR 12  is made of a P-channel MOS transistor and formed in a surface of the N-type semiconductor substrate. The level shift circuit LS 20  is modified to convert the input signal S 10  to a signal swinging between the negative voltage (−15V) and the voltage at the node N 12 . 
   As a result, the transistors can be controlled based on the output signals S 11 , S 12 , S 13  and S 14  of the timing control circuit  30 . The first diffused region of the first driver MOS transistor TR 13  is connected to the negative voltage (−15V) while the second diffused region of the second driver MOS transistor TR 14  is connected to the ground voltage Vss. As a result, the positive voltage (+15V) is generated and outputted from the second diffused region of the second charge transfer MOS transistor TR 12 . 
   According to this invention, the reverse voltage generation circuit is formed in a single semiconductor substrate, leakage current of the constituting MOS transistors is prevented and the operation of the circuit is stabilized. The reverse voltage generation circuit of this invention is suited for a power supply circuit to an LCD driver circuit that provides an active matrix type LCD panel with gate signals.