Patent Publication Number: US-7902081-B2

Title: Methods of etching polysilicon and methods of forming pluralities of capacitors

Description:
TECHNICAL FIELD 
     Embodiments disclosed herein pertain to methods of etching polysilicon and to methods of forming pluralities of capacitors. 
     BACKGROUND OF THE INVENTION 
     Capacitors are one type of component commonly used in the fabrication of integrated circuits, for example in DRAM and other circuitry. A typical capacitor is comprised of two conductive electrodes separated by a non-conducting dielectric region. As integrated circuitry density has increased, there is a continuing challenge to maintain sufficiently high storage capacitance despite typical decreasing capacitor area. The increase in density of integrated circuitry has typically resulted in greater reduction in the horizontal dimension of capacitors as compared to the vertical dimension. In many instances, the vertical dimension of capacitors has increased. 
     Several techniques have been developed to increase the storage capacity of a capacitor. One such technique is to fabricate a capacitor wherein at least one of the capacitor electrodes is double-sided and container-shaped. For example, an array of capacitor electrode openings for individual capacitors is typically fabricated in a suitable capacitor electrode-forming material, for example silicon dioxide doped with one or both of phosphorus and boron. Such openings are typically formed by dry anisotropic etching, and then lined with one or more conductive materials from which individual container-shaped capacitors are formed. It is then often desirable to etch away most if not all of the capacitor electrode-forming material to expose outer sidewall surface of the electrodes to provide increased area, and associated increased capacitance for the capacitors being formed. It may be desirable to form a lattice-like support for the capacitor electrode containers prior to etching to expose the outer container sidewalls, hopefully to preclude any subsequent toppling of the containers. For example and by way of example only, U.S. Pat. No. 6,667,502 and U.S. Published Application No. 2005/0051822 teach the provision of brace or lattice-like retaining structures intended to preclude such toppling. 
     Regardless, the vertical dimension of such capacitors has continued to increase while the horizontal dimension stays the same or decreases. Such dimensional variations result in the capacitor electrode openings needing to be etched deeper into the capacitor electrode-forming material. It is difficult to etch extremely deep capacitor electrode openings within doped silicon dioxides, such as phosphosilicate glass (PSG). However, doped silicon dioxides do provide the advantage of enabling a comparatively easy subsequent wet etch for exposing the outer sidewall surfaces of container-shaped electrodes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Some embodiments of the invention are described below with reference to the following drawings. 
         FIG. 1  is a diagrammatic cross section of a substrate fragment illustrative of commencement of processing according to an embodiment of the invention. 
         FIG. 2  is a diagrammatic top plan view of a larger scale portion of the  FIG. 1  substrate. 
         FIG. 3  is a view of the  FIG. 1  substrate fragment at a processing step subsequent to that shown by  FIG. 1 , and taken through line  3 - 3  in  FIG. 4 . 
         FIG. 4  is a diagrammatic top plan view of the  FIG. 3  substrate fragment. 
         FIG. 5  is a view of the  FIG. 3  substrate fragment at a processing step subsequent to that shown by  FIG. 3 . 
         FIG. 6  is a view of the  FIG. 5  substrate fragment at a processing step subsequent to that shown by  FIG. 5 . 
         FIG. 7  is a view of the  FIG. 6  substrate fragment at a processing step subsequent to that shown by  FIG. 6 , and taken through line  7 - 7  in  FIG. 9 . 
         FIG. 8  is a view of the  FIG. 7  substrate fragment taken through line  8 - 8  in  FIG. 9 . 
         FIG. 9  is a diagrammatic top plan view of the  FIGS. 7 and 8  substrate fragment. 
         FIG. 10  is a view of the  FIG. 7  substrate fragment at a processing step subsequent to that shown by  FIG. 7 , and taken through line  10 - 10  in  FIG. 12 . 
         FIG. 11  is a view of the  FIG. 10  substrate fragment taken through line  11 - 11  in  FIG. 12 . 
         FIG. 12  is a diagrammatic top plan view of the  FIGS. 10 and 11  substrate fragment. 
         FIG. 13  is a view of the  FIG. 10  substrate fragment at a processing step subsequent to that shown by  FIG. 10 . 
         FIG. 14  is a diagrammatic representation of DRAM circuitry. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments are described below primarily in the context of fabricating a plurality of capacitors, for example in an array of capacitors in the fabrication of DRAM. However, the invention is in no way so limited, encompassing fabrication of other integrated circuitry and encompassing any method of etching polysilicon from any substrate. 
     Embodiments of methods of forming pluralities of capacitors are described with reference to  FIGS. 1-14 . Referring initially to  FIGS. 1 and 2 , a substrate, such as a semiconductor substrate, is indicated generally with reference numeral  10 . In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Accordingly, and by way of example only, substrate fragment  10  may comprise a bulk semiconductor material (not shown), for example bulk monocrystalline, and/or comprise semiconductor-on-insulator layers or substrates. 
     Substrate  10  can be considered as comprising a capacitor array area  25 , a circuitry area  75  other than capacitor array area  25 , and an intervening area  50  between capacitor array area  25  and circuitry area  75 . In the depicted embodiment, intervening area  50  completely surrounds and encircles capacitor array area  25  ( FIG. 2 ), and circuitry area  75  comprises a peripheral circuitry area to that of capacitor array area  25 . Alternate constructions are contemplated, of course, for example those configurations wherein neither intervening area  50  nor circuitry area  75  completely or partially encircles a capacitor array area  25 . 
       FIG. 1  depicts an insulative material  12  having electrically conductive storage node pillars  14  formed therethrough. Materials  12  and  14  may be fabricated over some suitable underlying material, for example bulk monocrystalline and/or underlying circuitry. Suitable compositions for insulative material  12  include doped and undoped silicon dioxides, for example silicon dioxide deposited by the decomposition of tetraethylorthosilicate (TEOS) and/or borophosphosilicate glass (BPSG) and/or silicon nitride. Alternatively and by way of example only, material  12  may comprise anisotropically etched insulative sidewall spacers, for example formed about transistor gate lines (not shown). One suitable material  14  is conductively doped polysilicon. Conductive material  14  may be considered as comprising or defining a plurality of capacitor storage node locations  15 ,  16 ,  17  and  18  on substrate  10 . Storage node locations  15 ,  16 ,  17  and  18  are examples only, and regardless, may be conductive at this point in the process or made conductive subsequently. 
     A layer  22  has been formed over material  12  and capacitor storage node locations  15 ,  16 ,  17  and  18 . Suitable compositions of material for layer  22  comprise silicon nitride and/or undoped silicon dioxide deposited to an example thickness range of from about 100 Angstroms to about 2,000 Angstroms. Layer  22  may be included to provide an etch stop function. 
     A polysilicon-comprising layer  24  is received over substrate  12 / 14 / 22 . Layer  24  may be homogeneous or comprise multiple different compositions and/or layers. Suitable materials, without limitation, include those which comprise, consist essentially of, or consist of doped or undoped polysilicon, with dopant presence being with respect to a conductivity modifying impurity. In the context of this document, undoped polysilicon is polysilicon having from zero to no greater than about 1×10 14  atoms/cm 3  of a conductivity modifying impurity, for example phosphorus and/or arsenic. If doped with a conductivity modifying impurity, one total concentration range of the dopant(s) is from about 1×10 16  atoms/cm 3  to about 1×10 23  atoms/cm 3 , with from about 1×10 20  atoms/cm 3  to about 1×10 22  atoms/cm 3  being more preferred. One contemplated thickness range for material  24  is from about 5,000 Angstroms to about 10 microns, with 3 microns being a specific example. Thinner and greater thicknesses are, of course, contemplated. 
     A layer  26  is received over polysilicon-comprising material  24 . Such may comprise, consist essentially of, or consist of silicon nitride. One contemplated thickness range is from 200 Angstroms to 5,000 Angstroms. Some or all of layer  26  may be removed, or some or all of layer  26  may remain over the substrate as part of finished circuitry construction incorporating a plurality of capacitors being fabricated. Material other than silicon nitride may also be utilized, and embodiments which do not necessarily include a silicon nitride-comprising or masking layer  26  are also contemplated. 
     Referring to  FIGS. 3 and 4 , a plurality of capacitor electrode openings  28  have been formed within silicon nitride-comprising layer  26 , polysilicon-comprising layer  24 , and layer  22  over individual capacitor storage node locations  15 ,  16 ,  17  and  18 . Further, a trench  30  has been formed in intervening area  50  within materials  26 ,  24  and  22 . In one embodiment, trench  30  completely surrounds capacitor area  25 . One suitable technique for forming capacitor electrode openings  28  and trench  30  comprises photolithographic patterning and selective anisotropic dry etching to produce the  FIGS. 3 and 4  constructions. One contemplated minimum width of trench opening  30  is from about 200 Angstroms to about 5,000 Angstroms, while another contemplated minimum width for capacitor electrode openings  28  is from about 200 Angstroms to about 5,000 Angstroms. 
     Referring to  FIG. 5 , conductive material  32  has been formed within capacitor electrode openings  28  and within trench  30 . In the depicted embodiment, conductive material  32  less than fills capacitor electrode openings  28  and trench  30 . Alternately, conductive material  32  may fill capacitor electrode openings  28  and/or trench  30 . One contemplated thickness range for conductive material  32  is from about 20 Angstroms to about 1,000 Angstroms. In one embodiment, conductive material  32  comprises at least one of a conductive metal nitride, Pt, and Au. Suitable conductive metal nitrides include TiN, TaN, WN, and mixtures thereof. Material  32  may comprise multiple conductive materials, for example multiple conductive metal nitrides and/or at least two of a conductive metal nitride, Pt, and Au. The use of other conductive materials alone or in combination with any one of a conductive metal nitride, Pt, and Au is also contemplated. Regardless, one preferred and reduction-to-practice conductive metal nitride is TiN. 
     Referring to  FIG. 6 , conductive layer  32  has been planarized back at least to an outer surface of silicon nitride-comprising layer  26 , forming isolated/separate capacitor electrodes  33  within capacitor electrode openings  28  and an isolation structure within trench  30 . 
     Such provides but one example of a method of forming individual conductive capacitor electrodes  33  ( FIG. 6 ) within individual of the capacitor electrode openings  28 . In the depicted embodiment, such capacitor electrodes are formed to comprise conductive container shapes. 
     Referring to  FIGS. 7-9 , etch openings  45  have been formed through silicon nitride-comprising layer  26  within capacitor array area  25  effective to expose polysilicon-comprising layer  24  within capacitor array area  25  while leaving the elevationally outermost surfaces of polysilicon-comprising material  24  within circuitry area  75  completely covered with silicon nitride-comprising layer  26 . Such a configuration provides access for etchant to get to and etch material  24  within capacitor array area  25 . 
     Referring to  FIGS. 10-12 , substrate  10 , including polysilicon-comprising layer  24 , has been exposed to a solution comprising water and HF under conditions effective to etch polysilicon-comprising layer  24  to expose the outer sidewall portions of conductive capacitor electrodes  33 . The solution also comprises at least one of a conductive metal nitride, Pt, and Au. A layer consisting essentially of doped or undoped polysilicon wet etches very slowly with etching solutions that consist essentially of water and HF, typically on the order considerably less than about 10 Angstroms per minute. Such etch rate is ineffective to appreciably expose the outer sidewall portions of a conductive capacitor electrode for fabrication of a plurality of capacitors. However, it has been discovered that presence of at least one of a conductive metal nitride, Pt, and Au can result in significantly increased etch rates of polysilicon-comprising layers. Accordingly, at least one of a conductive metal nitride, Pt, and Au is provided in the presence of the solution for etching of the polysilicon. Such at least one of conductive metal nitride, Pt, and Au may be present in the solution in one or both of solid form and/or partially or wholly dissolved therein. Suitable conductive metal nitrides are those referred to above, namely at least one of TiN, TaN, WN, and mixtures thereof. 
     In one embodiment of forming a plurality of capacitors, individual conductive capacitor electrodes are formed to comprise at least one of a conductive metal nitride, Pt, and Au. In one embodiment, the exposing of such to a solution comprising water and HF derives at least one of a conductive metal nitride, Pt, and Au at least in part by etching the at least one of conductive metal nitride, Pt, and Au from the conductive capacitor electrodes. For example and by way of example only, conductive metal nitrides will etch in a solution consisting essentially of water and HF at about atmospheric pressure and about 29° C. at from about 1 Angstrom to about 3 Angstroms per minute. Accordingly in one embodiment, the at least one of conductive metal nitride, Pt, and Au may result from the etching of material of the capacitor electrodes. In one embodiment, the at least one of a conductive metal nitride, Pt, and Au present in the solution may be derived only by etching the at least one of the conductive metal nitride, Pt, and Au from the conductive capacitor electrodes. Additionally, the solution to which the polysilicon-comprising layer is exposed may have been provided with at least one of a conductive metal nitride, Pt, and Au in addition to any such material going into the solution the result of any etching of such materials of the conductive capacitor electrodes. However, embodiments of the invention also contemplate methods of forming a plurality of capacitors wherein the conductive capacitor electrodes are devoid of any of the conductive metal nitride, Pt, and Au wherein such is provided in the presence of the etching solution either prior to exposure of the solution to the substrate and/or entering into solution after exposure of such from elsewhere on the substrate other than from the conductive capacitor electrodes. Regardless, in one embodiment, the etching solution, other than the inclusion of water, may be devoid of any oxidizer (i.e., devoid of any H 2 O 2 , HNO 3 , etc.) and devoid of any OH −  (i.e., devoid of any base/hydroxides). 
     In one embodiment, the exposing conditions are effective to etch the polysilicon-comprising layer at a rate of at least about 500 Angstroms per minute, and even more preferably at a rate of at least about 1,000 Angstroms per minute. The exposing may be effective to etch all of the polysilicon-comprising layer from the substrate, for example as shown in  FIGS. 10-12 , or may be ineffective to etch all of the polysilicon-comprising layer from the substrate. 
     An example concentration of HF in the solution is from about 2% to about 40% by weight relative to the water, and more preferably from about 5% to about 15% by weight relative to the water. The at least one of a conductive metal nitride, Pt, and Au is preferably in the solution (either as solid, dissolved, or both) at from about 0.5 weight percent to about 5 weight percent by weight relative to the water, and more preferably from about 1% to about 1.5% by weight relative to the water. Other example process conditions comprise a temperature of from about 20° C. to about 40° C., and a pressure from about 0.5 atmosphere to about 1.5 atmospheres. 
     The invention was reduced-to-practice with a polysilicon-comprising material that was doped with phosphorus at a concentration of about 1×10 21  atoms/cm 3 , and wherein the conductive capacitor electrodes consisted essentially of TiN. Such was exposed at atmospheric pressure to a solution at about 29° C. that consisted essentially of water and HF at about 10.9% HF by weight relative to the water. Such etched about 1.5 microns of polysilicon in about 90 seconds. TiN is believed to have been etched into solution to facilitate the polysilicon etch, with TiN being present in solution in a small quantity at less than about 5% by weight relative to the water. 
     Conductive capacitor electrodes  33  of  FIGS. 10-12  within capacitor array area  25  are incorporated into a plurality of capacitors. For example,  FIG. 13  depicts the deposition of a capacitor dielectric layer  60 . By way of example only, suitable materials are any one or combination of silicon dioxide, silicon nitride or any suitable high k dielectric (i.e., k greater than or equal to 5), and whether existing or yet-to-be developed. By way of example only, suitable high k dielectrics include Ta 2 O 5  and barium strontium titanate. 
     An outer capacitor electrode layer  70  has been deposited over capacitor dielectric layer  60  to define capacitors  81 ,  82 ,  83 , and  84 . Such are depicted as comprising a common cell capacitor plate  70  to all of the depicted capacitors, for example as may be utilized in DRAM or other circuitry, but may of course be constructed otherwise. By way of example only,  FIG. 14  depicts an embodiment of a DRAM cell incorporating capacitor  81 . Such comprises an example transistor gate wordline  87  having insulative sidewall spacers  89 , an insulative cap  91 , and a conductive region  94  under cap  91  and which includes a silicide layer  95  over a conductive polysilicon-comprising region  96 . A gate dielectric region  97  is received under polysilicon-comprising region  96 . Source/drain regions  80  are shown formed within semiconductive material operatively proximate wordline gate  87 . One of such electrically connects with capacitor  81 , and another of such electrically connects with a bitline  85 . 
     The above-described embodiments were in the context of methods of forming pluralities of capacitors. However, embodiments of the invention encompass methods of etching polysilicon independent of capacitor fabrication. In one embodiment, a method of etching polysilicon comprises exposing a substrate comprising polysilicon to a solution comprising water, HF, and at least one of a conductive metal nitride, Pt, and Au under conditions effective to etch polysilicon from the substrate. All or only some of the polysilicon exposed to such solution may be etched from the substrate. Desirable attributes are also as described above with respect to the embodiments of  FIGS. 1-13 . In one embodiment, the exposing comprises providing the substrate to comprise at least one of outwardly exposed conductive metal nitride, Pt, and Au during such exposing, for example during all or only part of the exposing of the substrate to such a solution comprising at least water and HF. In one embodiment, the exposing also contemplates providing the substrate to be devoid of any outwardly exposed conductive metal nitride, Pt, and Au during all of the act of exposing. In such instance, for example, the at least one of a conductive metal nitride, Pt, and Au would be provided relative to the solution in some manner other than exposure of such a material or materials on the substrate from which polysilicon is being etched. 
     In one embodiment, a method of etching polysilicon from a substrate comprises exposing a substrate first region comprising polysilicon and a substrate second region comprising at least one of a conductive metal nitride, Pt, and Au to a solution comprising water and HF. By way of example only, material  24  comprises an example such first region, and material  32  comprises an example second such region. The solution is devoid of any detectable conductive metal nitride, Pt, and Au prior to the act of exposing. 
     At least some of the at least one of a conductive metal nitride, Pt, and Au of the second region is etched upon the act of exposing. Upon such etch, polysilicon is etched from the first region at a faster rate than any etch rate (if any etch) of the first region polysilicon prior to the etching of at least some of the material of the second region. 
     In one embodiment, the first region contacts the second region during the exposing. By way of example only with respect to the first-described embodiments, material  24  is depicted as contacting material  32  during the exposing. However, an embodiment of the invention also contemplates the first region and the second region being spaced from one another to be non-contacting relative to one another. 
     In one embodiment, the solution prior to the etching of at least some of the conductive metal nitride, Pt, and/or Au consists essentially of water and HF. Regardless, only some or all of the at least one of a conductive metal nitride, Pt, and Au may be etched from the substrate. Regardless, all or only some of the polysilicon of the first region may be etched from the substrate. 
     In one embodiment, a method of etching polysilicon comprises providing a substrate comprising polysilicon. An etching solution is provided which is displaced from the substrate, in other words at least initially provided in a manner in which the substrate is not contacted by the etching solution. The etching solution as so provided in displaced manner comprises water, HF, and at least one of a conductive metal nitride, Pt, and Au. The etching solution is applied to the substrate effective to etch polysilicon from the substrate. 
     In one embodiment, the polysilicon which is etched by the applying is exposed on the substrate prior to the applying. By way of example only, the embodiment depicted in the figures shows polysilicon material  24  at least partially being exposed on the substrate prior to exposure to the etching solution. 
     However, an embodiment of the invention also contemplates the polysilicon which is ultimately etched by the act of such applying not being exposed anywhere on the substrate prior to the applying. By way of example only, one or more layers may be provided over the polysilicon to be etched at the time of initially applying the etching solution to the substrate. For example and by way of example only, the polysilicon may be covered at least by an oxide (i.e., silicon dioxide) prior to the applying, with the etching solution by the act of applying to the substrate also etching the oxide. In one embodiment, the polysilicon which is etched by the applying is covered only by an oxide immediately prior to the applying, with the act of applying etching the oxide effective to expose the polysilicon. For example and by way of example only, a thin native oxide may form over the polysilicon and be etched away by exposure to the etching solution. 
     In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.