Patent Publication Number: US-6211717-B1

Title: Multiple differential pair transistor architecture having transconductance proportional to bias current for any transistor technology

Description:
FIELD OF THE INVENTION 
     The present invention relates to multiple differential transistor pair circuits, and more particularly, to linear multiple differential transistor pair circuits. 
     BACKGROUND OF THE INVENTION 
     Multiple differential pair circuits consist of N differential pairs of transistors operating in parallel, each having an appropriate input offset voltage. Multiple differential pair circuits are well-known and have many applications, including amplifiers, mixers, filters and other active elements. For a detailed discussion of conventional multiple differential pair circuits implemented in bipolar technology and their applications, see, for example, B. Gilbert, “The Multi-Tanh Principle: A Tutorial Overview,” IEEE J. of Solid-State Circuits, Vol. 33, 2-17 (January 1998), incorporated by reference herein. 
     FIG. 1 illustrates a conventional multiple differential pair circuit  100 . The illustrative multiple differential pair circuit  100  consists of five (5) differential pairs of transistors  200 - 1  through  200 - 5  coupled in parallel. A representative differential transistor pair circuit  200  is discussed below in conjunction with FIG.  2 . Four (4) of the five (5) differential transistor pair circuits  200 - 1 ,  200 - 2 ,  200 - 4 ,  200 - 5 , each have a corresponding well-defined offset voltage Δ- 1 , Δ- 2 , Δ- 3 , Δ- 4 , shown in FIG.  1 . Thus, the differential transistor pair circuit  200 - 3  in the middle of the multiple differential pair circuit  100  does not have an offset voltage, while the other differential transistor pair circuits  200 - 1 ,  200 - 2 ,  200 - 4 ,  200 - 5  have a corresponding offset, Δ. As the differential transistor pair circuits  200 -N progress away from the center differential transistor pair circuit  200 - 3 , the offset voltage, Δ, increases progressively, taking values of ±Δ, ±2Δ and so on, in a known manner. When configured in this manner, such circuits are referred to as equidistant-offset multiple differential pair circuits. 
     FIG. 2 is a schematic block diagram of a representative differential transistor pair circuit  200 . The two transistor devices  210 - 1  and  210 - 2  that comprise the differential transistor pair circuit  200  are identical (i.e., perfectly matched), in a known manner. For a given applied voltage, V IN , a desired output current, I 1 , I 2 , can be obtained from the differential transistor pair circuit  200  by varying the bias current, I O . 
     Bipolar transistors, and thus, bipolar differential transistor pair circuits  200 , have well-defined voltage-current (V-I) characteristics. Differential transistor pair circuits  200  have been implemented using bipolar transistors (or CMOS transistors operating in sub-threshold ranges where they behave like bipolar transistors), where the voltage-current (V-I) characteristic is exponential. FIG. 3 illustrates the voltage-current (V-I) characteristic  300  of the differential transistor pair circuit  200 , shown in FIG.  2 . Transistors having exponential voltage-current (V-I) characteristics were thought to be required in order to obtain multiple differential pair circuits  100  having a transconductance, g m , that is linearly proportional to the bias current. 
     As apparent from the above-described deficiencies with conventional multiple differential pair circuits, a need exists for multiple differential pair circuits comprised of pairs of transistors having non-exponential voltage-current (V-I) characteristics. A further need exists for a multiple differential pair circuit that provides both linearity and linear tuning capabilities, independent of the transistor technology. 
     SUMMARY OF THE INVENTION 
     Generally, a multiple differential pair circuit is disclosed having a transconductance, g m , proportional to the bias current, I 0 , for any transistor technology. According to one aspect of the invention, the transistors utilized to construct each of the differential transistor pairs in a multiple differential pair circuit are permitted to have a non-exponential voltage-current (V-I) characteristic. In one implementation, the transistors are embodied as MOS transistors. The present invention thus allows multiple differential pair circuits with transconductance, g m , proportional to bias current to be fabricated in any transistor technology. 
     As multiple differential pair circuits are linearized, the effective transconductance, g m , becomes (i) linearly dependent on bias current, and (ii) insensitive to the voltage-current (V-I) characteristics of the utilized devices. Thus, the present invention recognizes that multiple differential pair circuit having a transconductance, g m , that is linearly dependent on bias current can be fabricated using any transistor technology. Thus, transistors having an exponential voltage-current (V-I) characteristic are not required. In this manner, the present invention allows multiple differential pair circuits to be migrated from one technology to another without significantly impacting the operation of such multiple differential pair circuits. 
     Methods and apparatus are disclosed that provide a linear transconductance, g m , with respect to the bias current, I 0 , using differential pairs of transistors where each transistor has a non-exponential voltage-current (V-I) characteristic. 
     A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a conventional multiple differential pair circuit; 
     FIG. 2 is a schematic block diagram of a representative differential transistor pair circuit of FIG. 1; 
     FIG. 3 illustrates the voltage-current (V-I) characteristic of the differential transistor pair circuit of FIG. 2; 
     FIG. 4 illustrates the transconductance characteristic, g m , of the differential transistor pair circuit of FIG. 2; 
     FIG. 5 illustrates the transconductance characteristic, gm mdp , of a multiple differential pair circuit as a sum of identical Δ-spaced gm dp  functions; 
     FIG. 6 illustrates the transconductance characteristic, gm mdp , of a multiple differential pair circuit in a Δ region as a “sliced and overlaid” gm dp  function; and 
     FIG. 7 illustrates the transconductance characteristic, g m , of an equidistant-offset multiple differential pair circuit implemented in MOS technology, in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     The multiple differential pair circuits of the present invention may be constructed in the same manner as the conventional multiple differential pair circuit  100  shown in FIG. 1, as modified herein to provide the features and functions of the present invention. According to a feature of the present invention, the transistors  210 - 1 ,  210 - 2  in each of the differential transistor pair circuits  200 -N have a non-exponential voltage-current (V-I) characteristic, such as MOS transistors. In this manner, the multiple differential pair circuits  100  of the present invention can be fabricated without regard to the transistor technology. 
     Multiple differential pair circuits  100  have a transconductance, g m , that is proportional to the bias current. Again, such linear tunability was previously thought to be obtainable only from bipolar or bipolar-like (i.e., having an exponential voltage-current (V-I) characteristic) transistor technologies. The transconductance characteristic, g m ,  400  of the differential transistor pair circuit  200  is shown in FIG.  4 . Generally, the transconductance, g m , is the ratio of the incremental change in the output current, I 1 , I 2 , of the differential transistor pair circuit  200  to the incremental change in the input voltage, V IN , when the bias current, I 0 , is kept constant. 
     When the two transistors  210 - 1 ,  210 - 2  in each differential transistor pair circuit  200 , the incremental transconductance, g m , of the differential transistor pair circuit  200  can be expressed as follows:                  gm   dp          (     V     i                 n       )       =              ∂     I   1         ∂     V     i                 n                =            ∂     I   2         ∂     V     i                 n                          Eq   .     (   1   )                           
     As shown in FIG. 4, the transconductance characteristic, g m ,  400  is a symmetric function of V in . The shape of the transconductance characteristic, g m ,  400  strongly depends on the voltage-current (V-I) characteristic of the transistors  210 - 1 ,  210 - 2  in each differential transistor pair circuit  200 . The present invention recognizes, however, that the area under the transconductance characteristic, g m ,  400  is completely independent of the device characteristics. The area under the transconductance characteristic, g m ,  400  equals the absolute change of the output current, I 1 , I 2 . 
     As shown in FIG. 3, the absolute change of the output current, I 1 , I 2 , is equal to the bias or tail current, I 0 . Thus, the following expression holds:                  ∫     -   ∞     ∞              gm   dp          (   x   )               x         =     I   0             Eq   .              2                         
     The symmetry of the transconductance characteristic, g m ,  400  and the constancy of the area under the transconductance characteristic, g m ,  400  are the two properties exploited by the present invention. 
     First, consider a hypothetical multiple differential pair circuit  100  consisting of an infinite number of differential transistor pair circuits  200 . FIG. 5 illustrates the transconductance, gm mdp , of a multiple differential pair circuit  100  as a sum of identical Δ-spaced gm dp  functions. As shown in FIG. 5, the transconductance function, g m , of such a circuit is the sum of the infinitely many identical Δ-spaced gm dp  functions. In other words,                  gm   mdp          (     V     i                 n       )       =       ∑     k   =     -   ∞       ∞            gm   dp          (       V     i                 n       +     k                 Δ       )                 Eq   .              3                         
     The transconductance, g m , is clearly an even periodic function of V in  (with a period of Δ). Thus, the transconductance, g m , can be written in the form:                  gm   mdp          (     V     i                 n       )       =         ∑     k   =   0     ∞            a   k          cos        (     2      π                 k          V     i                 n       Δ       )           =       a   0          [     1   +     R        (     V     i                 n       )         ]                 Eq   .              4                         
     where all a k  coefficients have dimensions A/V and          R        (     V     i                 n       )              ∑     k   =   1     ∞              a   k       a   0              cos        (     2      π                 k          V     i                 n       Δ       )       .                         
     Thus, a 0  determines the average value of gm mdp , while all higher-order coefficients (a k , k≧1) determine its ripple. 
     The periodicity allows only the behavior of gm mdp  to be considered only in the region        ±       Δ   2     .                     
     FIG. 6 illustrates the transconductance, gm mdp , of a multiple differential pair circuit  100  in a Δ region as a “sliced and overlaid” gm dp  function. In other words, as shown in FIG. 6, the gm mdp  in the region        ±     Δ   2                     
     can be viewed as a result of slicing a single gm dp  function into Δ-pieces and overlaying them on top of each other. Thus, the area under the gm mdp  in the region        ±     Δ   2                     
     equals the total area under a single gm dp  curve.                  ∫     -       Δ                 V     2           Δ                 V     2                gm   mdp          (   x   )               x         =         ∫     -   ∞     ∞              gm   dp          (   x   )               x         =     I   0               Eq   .              5                         
     Using equation 5, it can be shown that a 0  is given by:                a   0     =       I   0     Δ             Eq   .              6                         
     Thus, a 0  depends only on the biasing (I 0  and Δ) and not on the voltage-current (V-I) characteristic of the utilized transistors. High linearity (small R(V in )) can be achieved by proper selection of the offset voltage, Δ. 
     If it is assumed that the offset voltage, Δ, is selected such that          R   max     =       Δ     I   0                   ∑     k   =   1     ∞          a   k                              
     is much smaller than 1, then the following is true:                  gm   mdp          (     V     i                 n       )       ≈     a   0     ≈         I   0     Δ     .             Eq   .              7                         
     Equation 7 shows that as a multiple differential pair circuit  100  is being linearized, the effective transconductance, g m , becomes (i) linearly dependent on bias current, and (ii) insensitive to the voltage-current (V-I) characteristics of the utilized devices  210 . In addition, equation 7 suggests that the transconductance, g m , can be made nearly temperature, supply and process independent by making I 0  and Δ temperature, supply and process independent. This task can be accomplished in any technology using well-known band-gap-based bias techniques. 
     The transconductance, g m , of a multiple differential pair circuit  100  employing a finite number of differential transistor pair circuits  200  has three different regions, namely, a middle region and two end regions. The middle region is the range of input voltages V in  for which the following holds:                  ∫       V     i                 n       -     Δ   2           V     i                 n       +     Δ   2                  gm   mdp          (   x   )               x         =     I   0             Eq   .              8                         
     Therefore, in the middle region, the operation and the properties of the finite-pair circuit  100  are identical to those of the infinite-pair circuit  100 , discussed above. Depending on (i) the number of pairs used in the multiple differential pair circuit  100 , (ii) the selected technology and (iii) the offset voltage, Δ, the middle region may or may not exist. 
     The effect of having a finite number of transistor pairs  200  in the multiple differential pair circuit  100  is observed in the end regions. In the end regions,                  ∫       V     i                 n       -       Δ                2           V     i                 n       +       Δ                2                  gm   mdp          (   x   )                 V   x           &lt;     I   0             Eq   .              9                         
     and gm mdp  has a value that is smaller than the nominal (and desired) I 0 /Δ. The end regions of a bipolar circuit do not change with I 0  while those of MOS circuits grow with I 0 . This difference is the direct consequence of the fact that the spread of gm dp  of a bipolar differential transistor pair circuit  200  does not change with I 0  while the spread of the gm dp  of a MOS differential transistor pair circuit  200  increases with I 0   2 . 
     FIG. 7 illustrates the transconductance characteristic, g m ,  700  of an equidistant-offset multiple differential pair circuit implemented in MOS technology. As shown in FIG. 7, the increase of the end regions, such as the end regions  710 ,  730 , in MOS multiple differential pair circuits  100  causes a decrease of the available mid-region  720 . Nevertheless, multiple differential pair circuit  100  implemented in MOS technology, can provide reasonable input linear range and a decade of linear-with-current tuning. 
     It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.