Patent Publication Number: US-9411538-B2

Title: Memory systems and methods for controlling the timing of receiving read data

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This application is a continuation of U.S. patent application Ser. No. 13/956,045, filed Jul. 31, 2013, issued as U.S. Pat. No. 8,751,754 on Jun. 10, 2014, which is a continuation of U.S. patent application Ser. No. 12/128,883, filed May 29, 2008, and issued as U.S. Pat. No. 8,521,979 on Aug. 27, 2013. These applications and patents are incorporated herein by reference, in their entirety, for any purpose. 
    
    
     TECHNICAL FIELD 
     Embodiments of the invention relate to memory systems and methods for controlling memory devices. 
     BACKGROUND OF THE INVENTION 
     Processor-based systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data (e.g. representing instructions, data to be processed, etc.) that are accessed by the processor. In a typical computer system, the processor communicates with the system memory including the memory devices through a processor bus and one or more memory controllers. In some memory systems, a group of memory devices of the system memory are controlled by an associated memory controller. The processor issues to the memory controller a memory request including a memory command, such as a read command, and an address designating the location from which data are to be read from memory. The memory controller uses the command and address to generate appropriate memory commands as well as row and column addresses, which are applied to the memory devices associated with that memory controller. In response to the commands and addresses, data is transferred between the memory devices and the processor. 
     Memory devices require a certain amount of time to service a memory request due to the time necessary to access the appropriate rows and columns of the memory device and actually retrieve the requested data. Further time is required to drive read data and read commands onto and off of a common interface between the memory devices and the controller. Although the operating speed of memory devices is continually increasing, the increase in device speed has not kept pace with increases in the operating speed of processors. The operation of the memory device itself therefore often limits the bandwidth of communication between the processor and the system memory. 
     To improve overall memory access bandwidth, one memory controller typically controls access to more than one memory device. In some systems, the processor interfaces with several memory controllers, each of which in turn control access to several memory devices. In this manner, further memory commands may be issued by a processor or memory controller while waiting for a memory device to respond to an earlier command, and bandwidth is improved. When a memory controller shares a common interface with multiple memory devices however, timing problems may occur. Commands and addresses sent from the memory controller, which are represented by electrical signals coupled to conductive signal lines of the interface, may reach different memory devices at different times, depending on the layout of the memory system. Furthermore, different memory devices may take different amounts of time to respond to memory commands depending on the process variations that occurred during fabrication of the memory devices. Variations in temperature may also cause variation in response time between memory devices. 
     Accordingly, there is a danger of a conflict on the common interface between multiple memory devices and a memory controller. For example, one memory device may attempt to place read data on the interface at the same time as data from another memory device is being carried by the interface. Such a data collision would result in a loss of usable data and is unacceptable. This problem can be alleviated by providing a common clock signal to each memory device that is synchronized to a system clock signal used by the memory controller. Each memory device may then decide when to place data on the interface by counting received clock periods. By referencing a common clock signal the memory device can ensure it places data onto the bus during a clock cycle designated for its use. When the memory device places data onto the interface, it then also sends a data strobe signal for use by the controller in identifying and synchronizing received read data. The use of common clock signals for synchronizing operation of the memory devices and strobe signals may require additional circuitry and further pins on the memory device. 
     However, the transmission of clock signals for each memory device may increase complexity of the system and consumes space and power at the memory device. Further, it may be desirable to decrease the number of output pins on the memory device. What is needed is a system that avoids data collisions on a common interface but does not rely on the use of a common clock signal at the memory device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified block diagram of a memory device according to an embodiment of the present invention. 
         FIG. 2  is a timing diagram illustrating various signals during operation of a conventional timing protocol. 
         FIG. 3  is a timing diagram illustrating various signals during operation of another embodiment of the present invention. 
         FIG. 4  is a timing diagram illustrating various signals during operation of another embodiment of the present invention. 
         FIG. 5  is a timing diagram illustrating various signals during operation of another embodiment of the present invention. 
         FIG. 6  is a simplified block diagram of a processor-based system according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention are directed toward memory systems and methods for controlling memory devices. Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without various of these particular details. In some instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the described embodiments of the invention. 
     A system  100  according to an embodiment of the present invention is shown in  FIG. 1 . The system  100  includes a plurality of memory devices, including memory device  105 . The memory device  105  and other memory devices (not shown) share an interface  110  with a controller  115 . The interface  110  may be implemented, for example, as a bus including a high-speed bus. In some embodiments, the memory device  105  may be physically stacked with one or more other memory devices and optionally also the controller  115 . The interface  110  may then be implemented as a set of through-substrate interconnects. The through-substrate interconnects may be formed by metallizing through-substrate vias created in each memory device substrate, or by any other method. 
     The controller  115  is configured to transmit commands, addresses and data, which are represented as electrical signals, and control signals to the memory devices over the interface  110 . In some embodiments, however, only data signals are transmitted on the shared interface  110  and command or address signals, or both may be transmitted over another interface. The controller transmits a variety of commands to ensure proper operation of the memory devices. The controller determines when to transmit commands using a controller clock signal. 
     A read operation will now be described to generally illustrate operation of the system  100 . The controller  115  transmits a read command onto the interface  110 . Read commands for the memory device  105  (shown in  FIG. 1  as vColumAddr) are captured in a capture buffer  120 . The read command is latched in capture buffer  120  by access signal, vArrayCyc, which transmitted by the controller  115  to a control input of the capture buffer  120 . By adjusting the timing of the vArrayCyc signal, the controller  115  can adjust when the read command is output from the capture buffer  120 . The read command is then passed to an access generation circuit  125  which generates internal control signals to access the array of memory cells  130  to retrieve read data. It takes a certain access time, t ACL , from the time vArrayCyc is transmitted to the memory device until the time the corresponding memory cell is accessed and the read data becomes available. The read data is placed in an output register  135  until an output control signal, vStrobe 0 , is transmitted by the controller  115  to a control input of the output register  135 , at which time the read data is moved from the output register  135  onto the interface  110  for communication with the controller  115 . The output control signal vStrobe 0  is specific for the memory device  105  and does not cause data to be coupled to the interface  110  from any of the other memory devices in the system  100 . 
     Data may be read from the array  130  in a burst manner. After specifying an initial address, data from several memory cells in the array  130  may be read sequentially. A larger amount of data may be read from the array  130  than can be placed on the interface  110  at one time. In such a case, the read data is serialized for transmission on the interface  110 . For example, as indicated in  FIG. 1 , 128 bits of data may be read from the array  130  and serialized into 32 bit groups for transmission on the interface  110 . 
     As will be described in more detail below, the functional blocks shown in  FIG. 1  in dashed lines (for example, delay  150  and memory  140 ) may be included in other embodiments of the invention, and can be optionally included depending on which embodiment of the invention is desired. 
     As described above with reference to  FIG. 1 , the controller  115  generates commands and addresses for several memory devices, including the memory device  105 . Because the different devices may be placed different distances from the controller  115 , the commands, addresses, and control signals, such as vColumAddr, vArrayCyc, and the memory device-specific vStrobe may take different amounts of time to reach each memory device. Further, the memory arrays associated with each memory device may have a different access time, t ACL , due to process or temperature variations. These timing differences between memory devices could cause read data from more than one device to be applied to the shared interface simultaneously if the memory devices apply the data to the interface at the time it becomes ready. Some delay can be used when reading from different memory devices consecutively. Delay can also be used between a read and a write request, either to a same or different memory devices. 
     In an example of a conventional timing protocol implemented by the system of  FIG. 1 , the controller  115  may be configured to delay a read command sent to a different memory device by a complete controller clock cycle. An example of the timing for this delay is shown in  FIG. 2 . The controller clock signal  200  is shown to illustrate the relative timing. The controller transmits a read command  210  for retrieving data from a first memory device, DRAM 0 , at time T 0 . Although DRAM devices are discussed as examples herein, any type of memory may generally be used. The controller transmits an array access signal vArrayCyc  220  to cause the memory devices to capture the command, as described above. As shown in  FIG. 2 , the vArrayCyc signal  220  contains a positive pulse corresponding to a high to low transition of the controller clock signal  200 . Read data will be available in the output register  135  a time t ACL  after the command is transmitted, as shown in  FIG. 2  mid-way between T 2  and T 3 . At that time, read data  225  is available to be placed on the interface  110 . 
     Read data is output by the memory in a certain unit time interval. A unit time interval corresponds to a single data transmission. The example in  FIG. 2  illustrates a system having quad-data rate devices and a burst length of four. A quad-data rate device can output read data four times every clock cycle. A burst length of four results in data from four consecutive memory locations being returned following the single read command  210 . The data from the four different locations are shown in  FIG. 2  as read data  225  (labeled ‘00, 01, 02, 03’). As a result of the quad-data rate devices, the unit time interval for the embodiment of  FIG. 2  corresponds to one-quarter of the controller clock period. Although a quad-data rate memory is described, any data rate may generally be used, including single or double data rate. 
     The next read command  230  is directed to a different memory device, DRAM 1 . If the read command were directed to the same memory device as the read command  210 , the controller could transmit the command immediately following the initial read command  210 , at time T 1 . However, because the read command  230  is directed to a different memory device (i.e., DRAM 1 ), the controller delays transmission of the read command  230  by one controller clock period, shown as the “no operation” (NOP) command  235  in  FIG. 2 . The data requested by the read command  230  is available for readout at time t ACL  later, a time between T 4  and T 5  as shown in  FIG. 2 . By waiting a clock cycle between the transmission of read command  210  and read command  230 , there are now four unit time intervals between the time all four data—00, 01, 02 and 03—(from a first memory device) are available for retrieval, and the time a first data is available responsive to the second read command  230 —(from a second memory device) shown as data  240  in  FIG. 2 . These four unit time intervals are sufficient to account for the variable time the commands, addresses, and control signals take to reach the different memory devices and different access times for the different devices to avoid data collision on the interface  10 . Accordingly, a data strobe signal (not shown) may be sent to the second memory device to place the first data of data  240  onto the interface  110  as soon as the data is ready, shown as a time between T 4  and T 5  in  FIG. 2 . 
     The method described with reference to  FIG. 2  delays the transmission of a read command when the read command is directed to a different memory device than the previously issued read command. That is, a memory device transition occurs when consecutive read commands are transmitted by the controller to different memory devices. The controller then delays the time corresponding read data from the later read command is placed on the interface. A memory device transition may be to a new memory device or back to a previously accessed memory device. For example, a first read command to DRAM 0  followed by a second read command to DRAM 1  would be a memory device transition. If the next read command is to DRAM 0  or DRAM 2  or any other memory device besides DRAM 1 , that is also a memory device transition. Any number of consecutive commands to a same memory device may be issued between memory device transitions. In the embodiment of  FIG. 2 , in summary a conventional timing protocol may be implemented where an entire controller clock cycle of delay is inserted between successive read commands transmitted to different devices. While this timing ensures proper operation despite signal transmission and access time differences between the memory devices, it decreases bandwidth in some embodiments. For example, in a single data rate system where the data rate is matched to the controller clock rate, the bandwidth penalty is equal to 1/(1+BL) where BL is the burst length. Using an exemplary burst length of 4, the bandwidth penalty is thus 1/5 or 20%. That is, in a worst-case bandwidth scenario, where each read command is issued to a different memory device than the last read command, and a controller clock is inserted between each one, there would be four controller clock cycles to retrieve the four data elements in the burst length, and one extra clock cycle of wait time. In a double data-rate system where data may be transmitted at a leading and falling edge of a clock signal, the bandwidth penalty is equal to 2/(2+BL). Assuming a burst length of 4, the penalty is ⅓ or roughly 33.33%. This corresponds to a scenario where each subsequent read command is sent to a different memory device, it takes two controller clocks to transfer the four elements of read data in the burst, and one extra controller clock is inserted prior to the next read command. In a quad-data rate system, assuming a burst length of four, the bandwidth penalty is greater still at 4/(4+BL), that is, the bandwidth penalty is 50%. 
     One or more embodiments of the present invention reduce the bandwidth penalty associated with the operation of the system  100 . It may not be necessary to insert a full controller clock period in between consecutive reads to different memory devices. The variation in travel time for signals to different devices and the variation in access time for the devices may be such that one unit time interval of time delay is sufficient. Accordingly, some embodiments of the invention delay the retrieval of available read data from a memory device by one unit time interval when consecutive read commands are issued to different devices. An example of a timing diagram illustrating such an embodiment is shown in  FIG. 3 . A read command  210  is transmitted at time T 0  to a first memory device, DRAM 0 . The vArrayCyc signal  220  causes the memory device to capture the read command  210 . The associated read data  225  becomes available a time t ACL  later, between T 2  and T 3  in  FIG. 3 . The read data  225  may be read out at that time using the vStrobe signal  300  for DRAM 0 . When the next read command  230  is transmitted at time  1  to DRAM 1  in  FIG. 3 , the associated data  310  becomes available a time t ACL  later, between T 3  and T 4  in  FIG. 3 . However, the vStrobe signal  315  for DRAM 1  is delayed one unit time interval following t ACL , that is, one-quarter of the controller clock period in the example of  FIG. 3 . Accordingly, one unit time interval separates the time read data  225  is finished being output (from DRAM 0 ) to the interface  110  and the time the read data  310  (from DRAM 1 ) may begin being placed onto the interface  110 . The single unit time interval, one-quarter the clock period in  FIG. 3 , is sufficient in many cases to account for variations in signal transit time and access time variations to avoid data collision on the interface  110 . 
     The next read command  320  is also transmitted to a different memory device than the previous read command  230 . In  FIG. 3 , the read command  320  is destined for DRAM 2 . The vStrobe signal  330  for DRAM 2  is accordingly delayed yet another unit time interval, for a total of a two unit time interval delay following t ACL . The read data  325  (from DRAM 2 ) associated with the read command  320  is available at a time t ACL  after the read address  320  is sent, shown in  FIG. 3  as between T 4  and T 5 . However, the vStrobe signal  330  is not transmitted until two unit time intervals later, at time T 5 . This again leaves a one unit time interval separation between the time the last of the data  310  have been placed on the interface  110  and the time the first of the data  325  may be placed onto the interface  110 . The next read command  335  is transmitted at time T 3 , representing a read command transmitted to DRAM 1 . Since the read command  335  is directed to a different device that the previous read command  320 , the vStrobe signal for DRAM 1  will be delayed another one unit time interval, for a total of a three unit time interval delay beyond t ACL . The vStrobe signal and read data corresponding to the read command  335  are not shown on  FIG. 3 , however, for ease of illustrating the remainder of the timing diagram. The next read command  340  is directed to DRAM 0 , and again represents a change of memory device relative to the previous read command  335 . The vStrobe signal for DRAM 0  will accordingly be delayed an additional unit time interval, for a total for four unit time intervals. However, recall that a unit time interval in  FIG. 3  corresponds to one-quarter of the controller clock period. Accordingly, instead of delaying a vStrobe signal for DRAM 0  by four unit time intervals, the controller may simply delay transmission of the next read command by one controller clock, as shown by the NOP command  345 . The vStrobe signal for DRAM 0  corresponding to the read command  340  may then be transmitted at time t ACL  after T 5  (i.e., without any vStrobe delay), when the read command was transmitted  340 . 
     Each consecutive read command  210 ,  230 ,  320 ,  335 , and  340  in  FIG. 3  is directed to a different memory device than the previous signal for ease of illustrating timing techniques for operation of some embodiments of the invention. When consecutive read commands are transmitted to the same memory device, however, the delay for sending a corresponding vStrobe signal is not increased. By way of summary, a vStrobe signal is generally transmitting to retrieve read data and access time, t ACL , after transmitting the read command. When the destination memory device changes relative to the previous read command, the vStrobe signal is delayed by one unit time interval and is transmitted one unit time interval after t ACL  has elapsed. This timing of the vStrobe signal is maintained until a read address is transmitted to a different memory device, at which time the vStrobe signal is delayed two unit time intervals, and so on. Once a delay of four unit time intervals is needed, the controller simply waits one controller clock period before transmitting the read command. In this manner, assuming an exemplary burst length of four, the bandwidth penalty for a single data rate system is at most 1/16 or approximately 6%. One-quarter clock period is used as delay following each four data elements. So, after transmitting 16 data elements, an entire clock period of delay has been used. In the embodiment shown in  FIG. 3 , one-quarter clock period is used as the delay increment. In other embodiments, however, other time periods could be used such that instead of progressively delaying the vStrobe signal by one unit time interval, a fraction of the time interval is used, such as one-half a unit time interval. Each time a read command is transmitted to a different memory device, the vStrobe signal is delayed an additional delay increment. Once the total delay equals a controller clock period, issuance of the next read command to a different memory device is delayed by a clock period. 
     As shown in  FIG. 3 , a data strobe signal may be delayed relative to a time when the read data has been accessed from the memory array and is available for transmission on the interface  110 . The data should be stored during this delay period. Furthermore, additional data may be accessed from the memory array  130  during the delay period. Accordingly, a buffer memory  140  ( FIG. 1 ) can be included in the memory device  105 . In some embodiments, the buffer memory  140  may be positioned generally anywhere between the array  130  and the interface  110 . The buffer memory  140  stores the retrieved read data from the memory array  130  until such time as the vStrobe signal is received. The buffer memory  140  can have sufficient memory to store as much data as may be retrieved from the array  130  during the delay of the vStrobe signal. Accordingly, in one embodiment of the buffer memory  140  includes a FIFO memory capable of storing additional groups of read data. Generally, the longest delay of the vStrobe signal in the embodiment of  FIG. 3  is three unit time intervals, during which an additional memory request could be serviced by the array while data from the previous read access is applied to the data bus. Accordingly, the buffer memory  140  is capable of storing an additional group of read data. 
     The buffer memory  140  may include a read and a write pointer to indicate where data can be written and where data can be read. The vStrobe signal causes data to be transmitted from the output register  135  to the interface  110 , as described above. The vStrobe signal may also cause the read pointer of the buffer memory  140  to increment, passing the next stored data to the output register  135 . The memory array  130  may transmit a data strobe signal to the buffer memory  140  when read data is available, incrementing the write pointer such that the retrieved data is written to correct locations. In summary, operation of an embodiment of the invention as discussed above with reference to  FIG. 3  should improve the bandwidth penalty incurred to avoid conflicts on the interface  110  by delaying vStrobe signals a unit time interval each time a different memory device is addressed. However, a buffer memory  140  may be used to store the data retrieved from the memory array  130  during the delay of the vStrobe signal. 
     Another embodiment of the present invention may reduce the required memory in the buffer memory  140 . Recall the buffer memory  140  has sufficient memory to store read data that may be obtained from the array  130  during a period the vStrobe signal is delayed, which may be as much as three unit time intervals in one embodiment. To reduce the size of the buffer memory  140 , or in some embodiments, eliminate a need for the buffer memory  140 , timing of the transmission of read commands may be varied instead of the timing of the strobe signal, as shown in  FIG. 4 . In this embodiment, the controller again utilizes the controller clock signal  200 . However, the controller can transmit read commands  400  at a higher speed, able to transmit one address command during each half-period of the controller clock  200 . A first read command  210  is transmitted at time T 0 . If a next read command corresponds to the same memory device, the signal is sent at time T 1 , one controller clock period later. However, if the next read command is for a different memory device, as shown in  FIG. 4  by the read command  230  transmitted to DRAM 1 , the read command is delayed an extra two unit time intervals, one-half a controller clock period in  FIG. 3 . Accordingly, the read command  230  is transmitted between time T 1  and T 2  as shown. Read data associated with the address  210  becomes available an access time t ACL  after the read command  210  is sent, and a vStrobe signal (not shown) for DRAM 0  may be transmitted at that time, between T 2  and T 3  in  FIG. 4 , to retrieve the data  225 . By waiting two unit time intervals into the clock cycle T 1 , the first of data  310  (from DRAM 1 ) associated with the read command  230  becomes available two unit time intervals after the last of data  225  (from DRAM 0 ) has been placed onto the interface  110 . The data  310  may be retrieved by transmitting a vStrobe command (not shown in  FIG. 4 ) for DRAM 1  at the time the data  310  is available, between T 3  and T 4  in  FIG. 4 . 
     In this manner, read commands are transmitted by the controller either four unit time intervals or six unit time intervals apart. A subsequent read command may be transmitted four unit time intervals following the transmission of a previous read command when reading from a same memory device, and six unit time intervals following issuance of a previous read command when reading from a different memory device. The vArrayCyc signal is changed to transmit pulses both four and six unit time intervals after an transmitted read command, as shown in  FIG. 4 , to latch a subsequent read command. Accordingly, the memory devices are able to capture a read command transmitting in either timing slot. Since data can be retrieved from the memory device t ACL  after the read command is transmitted, less space is required in the buffer memory  140 , as the read data will not need to be stored an additional amount of time on the memory device. 
     As discussed above with reference to  FIG. 4 , read commands may be delayed an extra two unit time intervals when the read commands are directed to a different memory device than the previous read command. In another embodiment of the invention, a timing margin of one unit time interval can be provided when switching between different memory devices by delaying processing of a subsequent read command. Referring back to  FIG. 1 , in some embodiments of the present invention a delay circuit  150  is optionally included in the memory device  105  between the capture circuit  120  and the array access generation circuit  125 . The delay circuit  150  delays the application of a received command to the array access generation circuit  125 , which as previously discussed, generates internal control signals to initiate access to the array of memory cells  130  and retrieve read data. In one embodiment, the delay circuit  150  receives the vArrayCyc signal. A read command is captured by the capture circuit  120  on a rising edge of the vArrayCyc signal, but is delayed by the delay circuit  150  until a falling edge of the vArrayCyc signal to be provided to the access generation circuit  125 . This delays the signal by the width of the vArrayCyc pulse, one unit time interval in the example described now with reference to  FIG. 5 . 
     A delay control signal  500  is provided to the delay circuit  150  to indicate whether the delay circuit  150  should be used to delay the command signal. When the delay control signal  500  is low, the read command  210  will be captured by the DRAM 0  on a rising edge of the vArrayCyc signal  220 , at a time shortly after T 0  in  FIG. 5 , and passed to the array access generation circuit  125  to begin retrieval of the read data. The associated data  225  are placed onto the interface  110  a time t ACL  later, shortly after T 2  in  FIG. 5 . Additional read commands may then be transmitted to the same memory device without additional delay. However, the next read command shown in  FIG. 5 , read command  230 , is directed to a different memory device, DRAM 1 . The delay control signal  500  goes high and the read command  230  will be captured on a rising edge of the vArrayCyc signal, but forwarding of the read command  230  to the array access generation circuit  125  will be delayed by the delay circuit  150  until a falling edge of the vArrayCyc signal. The associated data  310  is placed on the interface  110  a time t ACL  after the falling edge of the vArrayCyc signal, as shown in  FIG. 5 . In this manner, the placement of the data on the interface is delayed by the width of the vArrayCyc signal, that is, one unit time interval in  FIG. 5 . In other embodiments, any interval or fraction of an interval may be used, such as half a unit time interval. 
     When a read command is again transmitted to a different memory device, the command itself may be delayed by two unit time intervals, as shown by read command  320  in  FIG. 5  and is generally described above with reference to  FIG. 4 . By way of summary, the first time a different memory device is accessed, the device itself may create a one unit time interval delay by delaying application of the incoming read command to the array access generation circuit to initiate the read operation. The next time a different memory device is accessed, the command itself may be delayed two unit time intervals before transmission to the memory device. Then, the next time a different memory device is accessed, the memory device itself may delay the command, and so on. 
     An embodiment of a processor-based system  700  according to the present invention is shown in  FIG. 6 . The controller  115  communicates with multiple memory devices  105 ,  600 ,  605  and  610  over an interface  110 . Although four memory devices are shown in  FIG. 6 , the controller  115  may communicate with any number. The interface  110  may be any type of interface, as described above. In some embodiments, however the memory system shown in  FIG. 6  is implemented as a physical stack, with each memory device  105 ,  600 ,  605 ,  610  fabricated on a semiconductor substrate, and the semiconductor substrates placed one on top of the other. The interface  110  may then be implemented using a series of through-silicon vias. Although DRAM devices are shown in  FIG. 6 , any type of memory device may be used alternatively or in addition to the devices shown. 
     The controller  115  may be part of a larger logic die  630  that may communicate with a processor  705  through a relatively narrow high-speed bus  706  that may be divided into downstream lanes and separate upstream lanes (not shown in  FIG. 6 ). The DRAM devices  105 ,  600 ,  605  and  610  may be stacked on top of the logic die  630  which serves as the interface with the processor  705 . The logic die  630  can implement a variety of functions to limit the number of functions that must be implemented in the DRAM devices. For example, the logic die  630  may perform memory management functions, such power management and refresh of memory cells in the DRAM devices  105 ,  600 ,  605  and  610 . In some embodiments, the logic die  630  may implement test and/or repair capabilities, and it may perform error checking and correcting (“ECC”) functions. 
     The DRAM devices  105 ,  600 ,  605  and  610  are connected to each other and to the logic die  630  by a relatively wide interface  110 . The interface  110  may be implemented using through silicon vias (“TSVs”), as described above, which allow for formation of a large number of conductors extending through the DRAM devices  105 ,  600 ,  605 ,  610  at the same locations and connect to respective conductors formed on the devices  105 ,  600 ,  605 ,  610  to form vertical interfaces. In one embodiment, each of the DRAM devices  405 ,  600 ,  605 ,  610  are divided into 16 autonomous partitions, each of which may contain 2 or 4 independent memory banks. In such case, the partitions of each device  105 ,  600 ,  605 ,  610  that are stacked on top each other may be independently accessed for read and write operations. Each set of 16 stacked partitions may be referred to as a “vault.” Thus, memory device  105  may contain 16 vaults. In one embodiment, the controller  115  is coupled to one vault through the interface  110  and a separate controller is provided for other vaults in the devices  105 ,  600 ,  605 ,  610 . 
     The computer system  700  includes a processor  705  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor  705  may be coupled to input devices  710 , or output devices  715 , or both. In some cases, a device may perform both an input and output function. Any type of input and output devices may be used such as storage media, keyboards, printers and displays. The processor generally communicates with the controller  115  over a processor bus  706 , and may communicate address, command, and data signals. The controller then communicates with the memory devices over a further interface, as discussed above. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.