Patent Publication Number: US-6657283-B2

Title: Reducing relative stress between HDP layer and passivation layer

Description:
This application is a continuous-in-part of the original application numbered as Ser. No. 09/365,008, which filed Aug. 2, 1999 now U.S. Pat. No. 6,426,546. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to integrated circuits, and particularly relates to reducing the relative stress between a passivation layer and a high density plasma layer that is formed with a high density plasma. 
     2. Description of the Prior Art 
     In fabrication of integrated circuit (IC) that comprises a substrate and at least a set of interconnects, a passivation layer is formed over the entire top surface of the substrate. This is an insulating, protective layer that prevents mechanical and chemical damages during assembly and packaging. 
     In general, passivation layer must satisfy following desired properties: 
     (1) provides good scratch protection to underling structures. 
     (2) Impermeable to moisture. 
     (3) Exhibits low stress. 
     (4) Conformal step coverage. 
     (5) High thickness uniformity. 
     (6) Impermeable to sodium atoms and other high mobile impurities. 
     (7) Easily patterned. 
     (8) Good adhesion to conductor. 
     A serious defection of passivation layer is owing to the fact that passivation layer is broadly formed by chemical vapor deposition (CVD) process in contemporary technique. Therefore, the coverage ability of CVD induces a disadvantage that adjacent conductive lines on top surface of integrated circuit may be not properly isolate by the passivation layer, which is more serious when integration of the integrated circuit is increased. 
     Referring to FIG. 1 where a roughly illustration of cross-section view of an integrated circuit with some disadvantages is provided. Isolation  11 , gate  12 , spacer  13 , source  14  and drain  15  are located in and on substrate  10 . Beside, interconnects  16 , contacts  17  and dielectric layers  18  are formed on substrate to provide required metallization structure. Additionally, conductive lines  19  are formed on the metallization structure and affected as interconnects. Therefore, when passivation layer  193  is formed on the metallization structure by CVD, owing to the coverage of CVD, it is possible that void  196  is formed between two adjacent conductive lines  19  and increases the risk that adjacent conductive lines  19  are not properly isolated. 
     A well-known method, which is broadly applied in fabrication of integrated circuit that critical dimension is less than 0.5 m, to overcome the previous disadvantage is forming passivation layer  196  that directly covers conductive lines  19  by CVD with a high density plasma, as shown in FIG.  2 . Characteristic of the method is that during deposition, a DC bias is applied on wafer and then particles of plasma such as Ar will collide the deposited high density plasma layer  195 . Therefore, owing to the fact that colliding frequency is proportional to the electric field and the field is larger in edges of high density plasma layer  195 , hinges of high density plasma layer  195  is eliminated by collision and then no void is formed. Incidentally, owing to the fact the colliding frequency is larger in the edge and is smaller in the top, the thickness of high density plasma layer  195  is not uniform even it covers a smooth surface. 
     No matter how, owing to the truth that high density plasma layer  195  can not properly protect permeation of wafer and gas. An improved method is provided that passivation layer  193  is formed on high density plasma layer  195  to improve quality of passivation of integrated circuit. In other words, an integrated circuit is protected by a complex passivation layer that is formed by HDP and deposition in sequence. 
     However, an inevitable disadvantage of the improved method is that the absolute value of relative stress between high density plasma layer  195  and passivation layer  193  is about 1.8E08 dynes/cm 2 , such a high relative stress increases the risk that passivation of integrated circuit is degraded by cracks and pealing of passivation. FIG. 3 shows the possible result of high relative stress. Where there are a plurality of cracks and pealing in passivation layer  193 , and other parts of the integrated circuit are omitted. 
     Therefore, it is indisputable that development of a new structure of passivation to overcome the disadvantage of high relative stress is desired, and the new structure of passivation is more important as high density plasma layer  195  is irreplaceable. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to propose some structures that efficiently prevent crack and pealing which are induced by high relative stress. 
     It is another object of the invention to provide some structures that prevent formation of void by employing a high density passivation layer (HDP layer) which is formed by high density plasma. 
     It is a further object of the invention to provide some structures that are manufacturable. 
     In order to realize of the invention, some structures are provided. These structures can be divided into two main categories: 
     First category, a low stress passivation layer is directly formed on a HDP layer. 
     Second category, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. 
     Therefore, possible structures of the invention comprise following varieties: 
     First, a low stress passivation layer is located between a passivation layer and a HDP layer. 
     Second, a lower stress passivation layer directly locates on a HDP layer. 
     Third, a low stress layer is formed between a passivation layer and a HDP layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a rough illustration of cross-section view of an integrated circuit that forms passivation layer by deposition; 
     FIG. 2 is another rough illustration of cross-section view of an integrated circuit that forms passivation layers by HDP and deposition in sequence; 
     FIG. 3 is a qualitative illustration about disadvantage between passivation formed by deposition and passivation layer formed by high density plasma, where other parts of the integrated circuit are omitted; 
     FIG. 4 is a brief illustration of cross-section view of an integrated circuit with a structure that is the first proposed structure of the invention; 
     FIG. 5 is a brief illustration of cross-section view of an integrated circuit with a structure that is the second proposed structure of the invention; and 
     FIG. 6 is a brief illustration of cross-section view of an integrated circuit with a structure that is the third proposed structure of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The spirit of the proposed invention can be explained and understood by following three embodiments with corresponding figures. 
     The first embodiment is a structure for reducing relative stress between a passivation layer and a HDP layer. A typical absolute value of relative stress between a HDP layer that material is SiO 2  and passivation layer that material is SiN is about 8.0E09 dynes/cm 2 . 
     Referring to FIG. 4, the structure of first embodiment comprises substrate  40 , multi-level structure  405 , a plurality of metal lines  49 , HDP layer  50 , low stress passivation layer  51  and passivation layer  52 . In additional, though FIG. 4 only illustrates two-level case of multi-level structure  405 , the embodiment is not restricted by it. 
     These parts must satisfy following requirements: 
     (1) Material of substrate  40  comprises silicon and substrate  40  comprises a plurality of elements such as isolations  41  and metal oxide semiconductor transistors  42 . 
     (2) Multi-level structure  405  locates on substrate  40 , wherein number of layer of multi-level structure  405  varies from about 2 to about 10. Beside, multi-level structure  405  comprises a plurality of interconnects  46 , a plurality of contacts  47  and a plurality of dielectric layers  48 . 
     (3) A plurality of metal lines  49  that locate on a top surface of multi-level structure  405 , where material of metal lines  49  comprises aluminum and copper. 
     (4) HDP layer  50  that covers top surface of multi-level structure  405  and isolates each of metal lines  49  from other metal lines  49 . Wherein HDP  50  layer is formed by deposition with a high density plasma and material of HDP layer  50  comprises low dielectric constant dielectric. 
     (5) Low stress passivation layer  51  that covers HDP layer  50 , wherein stress of low stress passivation layer  51  is stronger than stress of HDP layer  50 , and material of low stress passivation layer  51  comprises silicon nitride. Moreover, methods for reducing stress of low stress passivation layer  51  comprise adjusting a low frequency power source of a reactor which is used to form low stress passivation layer  51 . 
     (6) Passivation layer  52  that covers low stress passivation layer  51 , where stress of passivation layer  52  is stronger than stress of low stress passivation layer  51 . Herein, material of passivation layer  52  comprises silicon nitride and methods of forming passivation layer  52  comprise chemical vapor deposition. Beside, the embodiment further comprises a chemical mechanical polishing process to level a top surface of passivation layer  52 . 
     Therefore, because both relative stress between HDP layer  50  and low stress passivation layer  51  and relative stress between low stress passivation layer  51  and passivation layer  52  are smaller than relative stress between HDP layer  50  and passivation layer  52 , disadvantages of high relative stress such as crack and pealing are efficiently protected by the first embodiment. 
     Beside, because low stress passivation layer  51  also has ability to prevent chemical and mechanical damage, as other conditions are equivalent, required thickness of passivation layer  52  in the embodiment is smaller than required thickness of passivation layer  193  of well-known fabrication which is shown in FIG.  2 . On the other hand owing to the fact that forming rate of low stress passivation layer  51  is slower than forming rate of passivation layer  52 , especially when low stress passivation layer  51  is formed by adjusting a low frequency power, the throughput of the embodiment is degraded by formation of low stress passivation layer  51 . 
     The second embodiment, briefly illustrated in FIG. 5, relates to a structure for reducing relative stress between passivation layer  54  and HDP layer  53 , wherein HDP layer  53  is formed by a high density plasma. 
     The second embodiment comprises following parts: substrate  40  that comprises a plurality of elements; level structure  407  that locates on substrate  40 . Level structure  407  comprises a plurality of contacts  47  and dielectric layer  48 ; a plurality of metal lines  49  that locates on a top surface of level structure  407 ; HDP layer  53  that covers the top surface of level structure  407  and isolates each metal line  49  from other metal lines  49 ; low stress passivation layer  54  that covers HDP layer  53 , wherein stress of low stress passivation layer  54  is a different to stress of HDP layer  53 . Consequentially, these parts of the proposed embodiment also must satisfy following additional conditions: 
     First, elements of substrate  40  comprise isolations  41  and metal oxide semiconductor transistors  42 . 
     Second, material of metal lines  49  comprises aluminum and copper. 
     Third, material of HDP layer  53  comprises silicon oxide and doped oxide. 
     Fourth, material of low stress passivation layer  54  comprises silicon nitride, silicon oxynitride, PE oxide, TEOS oxide, doped oxide and PSG. 
     Fifth, stress of low stress passivation layer  54  is reduced by adjusting a low frequency power source of a reactor that is used to form low stress passivation layer  54 . 
     Sixth, the provided embodiment further comprises leveling a top surface of low stress passivation layer  54 . 
     Obviously, owing to the fact that relative stress between HDP layer  53  and low stress passivation layer  54  is smaller than relative stress between HDP layer  195  and passivation layer  193 , disadvantages of high relative stress such as crack and pealing also are protected by the second embodiment. 
     Additionally, as previous embodiment, because forming rate of low stress passivation layer  54  is slower, especially when low stress passivation layer  53  is formed by adjusting a low frequency power, the throughput of the embodiment is degraded by formation of low stress passivation layer  54 . Particularly, since in the second embodiment only low stress passivation layer  54  is formed on HDP layer  53 , throughput of the second embodiment is slower than the first embodiment. No matter how, the second embodiment has an advantage that fabrication is simple for forming process of low stress passivation layer  54  does not need to be adjusted. 
     Consequently, referring to FIG. 6, the third embodiment is a structure for reducing relative stress between passivation layer  57  and oxide layer  55 , where a chemical vapor deposition process with a high density plasma is used to form the oxide layer  55 . 
     As shown in FIG. 6, the third embodiment comprises substrate  40 , a plurality of semiconductor structures that locate on substrate  40 , a plurality of conductive line  495  that locate on a top surface of these semiconductor structures, oxide layer  55  that covers a top surface of these semiconductor structures and isolates each conductive line  495  from other conductive lines  495 , a layer  56  with different stress to stress of oxide layer  55  that covers oxide layer  55 , and passivation layer  57  that covers layer  56 . 
     Indisputably, to efficiently reduce the relative stress, stress of layer  56  is different from stress of oxide layer  55  and stress of passivation layer  57 . 
     Beside, in the embodiment, a plurality of elements locate in and on the substrate where elements comprise isolations  41  and metal oxide semiconductor transistors  42 . And these semiconductor structures comprise a plurality of interconnects  46 , a plurality of contacts  47  and at least one dielectric layer  48 . 
     Moreover, material of conductive lines  495  is chosen from a group consisting of metal, polysilicon and silicide. And material of layer  56  comprises PR oxide, TEOS oxide, PSG, doped oxide, and silicon oxynitride. 
     Herein, layer  56  comprises a thin film with adjustable stress, and a typical thickness of layer  56  is from about 300 angstroms to 5000 angstroms. In additional, material of passivation layer  57  comprises silicon nitride. 
     As a matter of fact, in the third embodiment, layer  56  needs not have the ability to protect chemical and mechanical damage. Therefore, any material with stress different from stress of oxide layer  55  and stress of passivation layer  57  can be used to form layer  56 , and then high relative stress between oxide layer  55  and passivation layer  57  can be more efficiently reduced by the third embodiment. Of course, an unavoidable disadvantage of the third embodiment is that fabrication is complicated by the formation of layer  56 . 
     While the invention has been described by three embodiments, the invention is not limited there to. To the contrary, it is intended to cover various modifications, procedures and products, and the scope of the appended claims therefore should be accorded to the broadest interpretation so as to encompass all such modifications and similar arrangement, procedures and products.