Patent Publication Number: US-6911862-B2

Title: Ultra-low current band-gap reference

Description:
RELATED APPLICATIONS 
   This is a continuation application of U.S. patent application Ser. No. 10/365,675, filed Feb. 12, 2003, titled “Ultra-Low Current Band-Gap Reference,” which issued as U.S. Pat. No. 6,801,079 on Oct. 5, 2004 and claims priority to Italian Patent Application Serial No. RM2002A000500, filed Oct. 4, 2002, entitled “Ultra-Low Current Band-Gap Reference,” both of which are commonly assigned. 

   TECHNICAL FIELD 
   The present invention is related in general to a voltage reference generator for an integrated circuit (IC), and, in particular, to a voltage reference generator for a flash memory for a portable device such as a cellular telephone. 
   BACKGROUND INFORMATION 
   In many integrated circuits and particularly in flash memories such as for use in cellular telephones and the like, a voltage reference generator circuit is used. The output of the voltage reference is needed in many blocks of the IC for a variety of functions. Some important requirements for a voltage reference generator for flash memories for use in portable instruments such as cellular phones include:
         1. Stability over the extended temperature range from −40 to +85 degrees C.;   2. Stability over process parameter ranges;   3. Low voltage operation to reduce power consumption;   4. Low current drawn from the power supply in active and standby modes of operation to extend the battery life (the voltage reference circuit is generally also left on in the flash standby mode to allow fast recovery from standby); and   5. Low cost deriving from both small silicon real estate and by avoiding extra process steps needed to build non-standard devices to implement the voltage reference circuit.       

   One example of a design for a voltage reference circuit is the band gap voltage reference (BGVR) circuit. While this circuit has been successfully used in a number of applications, unfortunately it is not well suited for flash memory circuits in portable battery operated devices such as cellular telephones and the like, where low current consumption and low operating voltages are required for at least the following reasons:
         The minimum operating Vcc power supply for a cellular telephone is increasingly very low, for example, present devices have a nominal Vcc as low as 1.42 V, ruling out many of the available variations of the BGVR;   Stability over a wide temperature range and process variations is necessary for flash memories used in portable battery operated devices. BGVRs are typically not sufficiently stable for practical needs of other parts of the memory served by the BGCR output;   The current drawn by state-of-art BGVRs is typically not less than 10 μA, which is too much for a cellular telephone or similar battery operated flash memory application; and   Bipolar transistors, key components in the BGVR, such as those that are available in standard flash memory manufacturing processes, do not have adequate performances for a quality BGVR circuit.       

   Accordingly, what is needed is a simple band-gap voltage reference circuit for a portable flash memory device such as a cellular telephone that will work at acceptable voltages and currents over an extended temperature range and have adequate process stability, using a standard flash technology. 
   The above-mentioned problems with band-gap voltage reference circuits, as well as other problems, are addressed by the present invention and will be understood by reading and studying the following specification. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a computer system including a memory circuit, a power supply, and an on-chip reference voltage source according to the teachings of the present invention. 
       FIG. 2  shows an illustration of one embodiment of band-gap voltage reference circuit according to the teachings of the present invention. 
       FIGS. 3   a  and  3   b  are layout and cross-section views, respectively, of a vertical NPN transistor which may be utilized in embodiments of the present invention. 
       FIG. 4  is a graph of the transistor gain (hfe) versus collector current (Ic) for a vertical NPN transistor found in a memory manufactured by a standard flash memory process. 
       FIGS. 5   a  and  5   b  are layout and cross-section views, respectively, of a lateral bipolar transistor which may be utilized in embodiments of the present invention. 
       FIG. 6  is a graph of the transistor gain (h fe ) versus collector current (I c ) for an NPN gated bipolar junction transistor according to the present invention. 
   

   SUMMARY 
   A band-gap voltage reference circuit according to one aspect of the present invention includes a plurality of horizontal gate bipolar junction transistors that show improved gain at low collector currents. The horizontal gate bipolar transistors include an emitter formed by the NMOS memory device n+ source region, a base formed by the NMOS memory device p+ channel region(when the NMOS is off), and a drain formed by the NMOS memory device n+ collector region, in which the base/channel region is less than 0.4 μm in width. Advantageously, the circuit may be fabricated by standard flash memory manufacturing processes. Other advantages and aspects of the present invention will become apparent to those of ordinary skill in the art after examining the detailed description which appears below. 
   DETAILED DESCRIPTION 
   In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. 
     FIG. 1  shows a computer system  100  including a memory circuit  110 , a power supply  130 , a band gap voltage reference source  200  for providing stable reference voltages for operation of the memory and a processor  140 . Memory  110  includes a memory array  112  of nonvolatile memory cells (which may be flash memory), and a controller  120  that controls detailed operations of memory  110  such as the various individual steps necessary for carrying out writing, reading, and erasing operations. Memory  110  also includes an address decoder circuit  122  for decoding and selecting addresses provided by processor  140  to access appropriate memory cells in memory array  112 , and an I/O circuit  124  for providing bi-directional communications between processor  140  and memory circuit  110 . 
   A more detailed drawing of a basic band gap voltage reference (BGVR)  200  according to the present invention is shown in FIG.  2 . BGVR  200 , as constructed according to the present invention, is capable of working at low power supply voltages and of providing stable reference voltages needed to operate a flash memory circuit in a portable device such as cellular telephone. In this circuit, bipolar transistors Q 2  and Q 1  are respectively of area  1  and of area N (i.e., N times greater than area  1 ). Q 1  and Q 2  are symmetrical in layout. To simplify fabrication, Q 1  may be constructed of a number N of individual transistors each having an area of 1. BVGR  200  also includes a pair of PMOS transistors, T 1  and T 2 . The source/drain of T 1  is connected between the collector of Q 1  and Vcc and the source/drain of T 2  is connected between Vcc and tapped resistor R 2  which in turn is connected to the collectors of Q 2  (the double collector feature of Q 1  and Q 2  shown in  FIG. 2  will be explained below). The emitter(s) of Q 1  are connected to a common reference or ground  250  through R 1 , which in this example is a 17.9 K Ohm resistor. The emitter of Q 2  is connected to a common reference or ground  260 . 
   The gate of T 1  is tied to the gate of T 2  and is also connected to the collector of Q 1 . The bases of Q 1  and Q 2  are tied together and also connected to collector of Q 2 . To a good approximation, the currents I 1  and I 2  are the same. In fact, I 1  and I 2  flow through T 1  and T 2 , which have the same gate and source voltages. The drain voltage however is actually slightly different, but since the gate and the drain of T 1  are shorted, this transistor is saturated. In such condition, because of the typical I-V ds  characteristics of the MOS transistor with V gs =constant, the variation of the current due to variations of V ds  is negligible. Even if V ds2  is slightly different from V ds1 , to a good approximation
 
 I   1   =I   2   (1)
 
In other words, I 2 , is the “mirrored” current of I 1 . The circuit formed by T 1  and T 2  is commonly referred to as a current mirror.
 
   From the basic silicon junction diode equation, the forward current I b  of the base-emitter diode of bipolar transistors such as Q 1  and Q 2  is:
 
 I   b   =I   0   e   V     be/Vt     (2)
         where:   I 0 =diode saturation current, proportional to the area of the base-emitter;   V be =base-emitter voltage;   V t =kT/q; and:
           k=Boltzmann constant;   
           T=absolute temperature; and   q=electron charge.       

   Since the base-emitter area of Q 1  is N times greater than the base-emitter area of Q 2 ,
 
 I   b1   =NI   0   e   (vbe−Ve)/Vt   (3)
 
 I   b2   =I   0   e   V     be     /Vt   (4)
 
   The collector currents I c1  and I c2  are:
 
 I   c1 =β 1   I   b1   (5)
 
 I   c2 =β 2   I   b2   (6)
         where β 1  and β 2  are the gains (h fe ) of transistors Q 1  and Q 2 .β 1  and β 2  are a function of the bipolar transistor characteristics (which are the same for Q 1  and Q 2  since they are on the same chip) and are also a function of the current flowing through the transistors. From Kirkhoff&#39;s first law applied to the collector node of Q 2 :
 
 I   2   =I   c2   +I   b1   +I   b2   (7)
       

   Assuming β 1  and β 2  quite large, I b1  and I b2  can be ignored in a first approximation. Therefore:
 
 I   c2   =I   2   (8)
 
   Since
 
 I   1   =I   c1   (9)
 
   From Equations (8), (9) and (1),
 
 I   c2   =I   c1   (10)
 
   If it is assumed that:
 
β 1 =β 2   (11)
         and from Equations (5), (6), (10) and (11) it can be determined that:
 
 I   b2   =I   b1   (12)
       

   from Equations (3), (4) and (12):
 
 NI   0   e   (V   be − V   e   )/V   t   =I   0   e   V   be   /V   1   (13)
 
   Rewriting Equation (13):
 
V e   =V   t In  N =( kT  In  N )/ q   (14)
 
Now
 
 V   bg   =V   be   +R   2   I   2   (15)
 
   and
 
 I   1   =V   e   /R   1   +I   b1   =V   e   /R   1   +I   c1 /β 1   (15′)
 
   Assuming β 1  is quite large, the term I c1 /β 1  may be neglected, thus
 
 I   1   =V   e   /R   1   (16)
 
   From Equations (1) and (16):
 
 I   2   =V   e   /R   1   (17)
 
   From Equations (14), (15) and (17):
 
 V   bg   =V   be   +R   2   kT  In  N/R   1   q   (18)
 
   It is well known that V be  changes with temperature, typically reducing its value by −2 mV/Degree C. for a junction silicon diode. By proper selection of R 2 , N and R 1  it is possible to have R 2  kT In N/R 1 q change by +2 mV/deg C., therefore compensating for the temperature induced changes in V bg . 
   Writing Equation (18) for two different temperatures T 1  and T 2  (T 2 &gt;T 1 )
 
 V   bg2   =V   be2   +R   2   kT   2  in  N/R   1   q   (19)
 
 V   bg1   =V   be1   +R   2   kT   1  In  N/R   1   q   (20)
 
   From Equations (19) and (20):
 
 V   bg2   −V   bg1   =V   be2   −V   be1   +R   2   k ( T   2   −T   1 ) In  N/R   1   q   (21)
 
   The values of R 2 , N, and R 1  should be such that there is no variation of band gap voltage with changes in temperature. Thus, the left hand side of Equation (21) is set to 0.
 
0 =V   be2   −V   be1   +R   2   k ( T   2   −T   1 ) In  N/R   1   q   (23)
 
Hence,
 
 V   be2   −V   be1   =−R   2   k ( T   2   −T   1 ) In  N/R   1   q   (24)
 
 V   be2   −V   be1 /( T   2   −T   1 )=− R   2   k  In  N/R   1   q 
 
As noted, the V be  variation with temperature for a junction silicon diode is −2 mV/ DegC.
 
Thus,
 
−2×10 −3   =−R   2   k  In  N/R   1   q   (25)
         and
 
 R   2 =2 R   1   q/ 10 3   k  In  N   (26)
       

   For stability of BGVR circuit  200  over process variations, bipolar transistors Q 1  and Q 2  must be drawn exactly with the same layout. Since the emitter of Q 1  is N times greater than the emitter of Q 2 , one simple approach for Q 1  is to draw N transistors identical to Q 2  and tie together their collectors, their bases and their emitters. This implies that N is an integer number. To minimize silicon area and because N must be greater than 1, N=2 is selected. 
     R   2 =2 R   1   q/ 10 3   k  In 2  (27) 
   From Equation (27) there are numerous possible choices of values for R 2  and R 1 . An additional condition can be used to set the value R 2  and R 1  setting the current consumption of the BGVR circuit at ambient temperature.
 
 i   e   =V   e   /R   1   (28)
 
From Equation (14) and using N=2:
 
 i   e   =kT  In 2 R   1   q   (29)
 
Setting i e =1 μA:
 
 R   1 =10 −6   kT  In 2 /q   (30)
 
Substituting in Equation (27):
 
 R   2 =2 10 3   T   (31)
 
For T=300° K
 
 R   2 =600 K′Ω  (32)
 
At the same T=300° K, using actual values of the Boltzmann constant k=1.38×10 −23  and of the electron charge q=1.602×10 −19 :
 
R 1 =17.9 K′Ω  (33)
 
The above values of R 1  and R 2  may thus be used for a temperature compensated BGVR.
 
   The above calculations are all based on the assumption that h fe  (the “gain” or β of the bipolar transistors) is quite high. Unfortunately, high gain bipolar transistors have not been available in standard flash memory fabrication processes. One configuration of bipolar transistor, in theory, available in standard flash memory technology, is the vertical NPN bipolar transistor, i.e., a transistor in which the emitter, base and collector are aligned along a line perpendicular to the wafer surface. With reference to  FIGS. 3   a  and  3   b,  vertical NPN bipolar transistors are formed by n+ diffusion region  301  as emitter, an n+ diffusion region  302  (deep Nwell) as vertical collector, and a p+ diffusion region  303  used as base. However, there is a practical problem with the vertical bipolar transistors available in standard flash memory technology. To ensure the validity of the relationships of Equations (8), (16) and (29), the h fe  (the β or “gain” of bipolar transistors) must be the highest possible. It is thus desirable to select a value of I e  that maximizes h fe .  FIG. 4  shows a graph of h fe  versus collector current for typical vertical NPN bipolar transistors found in standard flash processes. Unfortunately, from the characteristics shown in  FIG. 4 , h fe  max is ˜26 for I c  between 20 and 80 μA. Moreover, this current is too high for an acceptable standby current of a flash memory chip designed for use in cellular telephone and other low power flash memory applications. Setting a maximum total current of 2 μA (1 μA for each of the two branches of the BGVR circuit), h fe  comes down to ˜20. The above calculations are based on the assumption that β 1  and β 2  are quite large. For h fe =20, the relationships of Equations (8), (16) and (29) become inaccurate enough to impair the overall stability of the BGVR circuit. In particular, it can be demonstrated that, for vertical NPN bipolar transistors such as are found in standard flash memories, with h fe =20, the temperature stability over the extended temperature range of −40/+85 deg C. is −14% to 8%. Such variations are generally unacceptable for flash memories devices intended for cellular phones and other applications where extended range temperature stability and low power consumption must be observed. 
   In an effort to overcome the foregoing problems, some variations have been introduced in the basic band gap reference circuit. For example, “Temperature Compensated Ultra-Low Voltage Band-Gap Reference” by Giulio Marotta and Agostino Macerola, Italian Patent Application Serial No. RM2002A000236, filed on Apr. 30, 2002 (U.S. Patent application Ser. No. 10/365,586, filed on Feb. 12, 2003), commonly assigned with the present invention and incorporated herein by reference as if fully set forth, represents one effort to improve the basic band gap reference circuit. Even with the variation shown in that application, standby current needs to be not less than about 10-12 μA for an acceptable compromise on temperature stability. As the foregoing calculations show, another solution to the problem would be to use bipolar transistors with high h fe . This solution has the advantage of avoiding implementing circuit variations to the basic band gap reference circuit. Unfortunately, as noted, the basic vertical NPN bipolar transistors found in standard flash memory technology do not provide high enough gain. 
   There is another bipolar transistor that can be found in standard flash memory technology. This transistor is “lateral” or “horizontal” since it has the emitter, base and collector junctions on a plane parallel to the silicon wafer surface. One such horizontal bipolar transistor is formed by the NMOS source region (n+ as emitter), the channel region when the NMOS is off (as the base), and the NMOS drain region (n+ as the collector). Unfortunately, the horizontal bipolar transistor in standard flash memory has demonstrated poor h fe . Because of the poor gain performance such transistors have been considered to be impractical and treated as gate parasitic transistors, i.e., devices that detract from the performance of other circuit elements and are shut off in any working mode of the chip. As MOS technology has improved over the years, the channel length of the standard MOS transistor has been reduced accordingly. As channel lengths have approached values as low as 0.18 mm or less for low voltage NMOS transistors (0.32 mm for high voltage NMOS transistors), the base width of the horizontal bipolar transistors has correspondingly been reduced. Because of these structural changes the performance of the horizontal bipolar transistor is now greatly improved. Such devices are referred to herein as Gate Bipolar Junction Transistors (GBJTs) because their characteristics are also a function of the gate voltage bias. In particular, for short channel lengths, GBJTs show a significantly higher and thus more useful h fe . 
   Referring to  FIGS. 5   a  and  5   b,  a top view and cross-section, respectively, of a horizontal GBJT structure  500  according to the present invention includes an emitter  502  made by the same n+ diffusion process used in fabricating the source/drain for standard NMOS transistors, a gate  504 , with a base region  508  underneath the gate  504 , and with a collector region  506  surrounding the gate  504 , also made by the n+ diffusion process used in fabricating the source/drain for NMOS transistors. It should be noted that the vertical NPN transistors formed from n+ NMOS source/drain regions  502  and  506  (emitter), Iso-pwell  503  (base), and deep well  505  (collector), are also present in parallel with the GBJT. This accounts for the double collector found in the symbol of the GBJTs used in the schematic of FIG.  2 . 
   One example of the h fe  curves of the GBJT of structure  500 , with the gate grounded, is plotted in  FIG. 6  with different values of the channel length (=base width). As shown by the legend on  FIG. 6 , an “X” designates the h fe  curve relative to a BJT transistor of length L=0.64 microns. Similarly, the h fe  curve relative to a BJT transistor of length L=0.48 microns is designated in the legend by “o.” The other two curves, related to BJT&#39;s of L=0.32 and L=0.24 microns, are charted as sequences of small squares “[ ]” and “−” respectively. The h fe  is 120 for a base width L=0.32 mm and with a collector (emitter) current of 1 μA. With h fe =120 the relationships of Equations (8), (16) and (29) can be considered valid to a much higher approximation. Thus, a sufficiently high temperature stability is achieved of +/−1% over the extended temperature range, and the overall current drawn by the BGVR is only ˜2 μA. 
   One example of a schematic of the BGVR circuit using Gate Bipolar Junction Transistors according to the present invention is shown in  FIG. 2  where the R 2 =600 K′Ω resistor has been designed with taps in order to allow trimming of the voltage reference. Other designs and variations on this circuit and other applications of the present invention will be readily apparent to those of ordinary skill in the art. 
   CONCLUSION 
   A voltage reference generator has been described. The voltage reference generator includes a number of horizontal Gate Bipolar Junction Transistor (GBJT) that exhibit a higher and thus more useful h fe  at collector currents that are 10 μA and below and can be used in a band-gap voltage reference circuit for integrated circuits and in particular for a portable flash memory device such as a cellular telephone working at acceptable voltages and currents with acceptable temperature and process stability, using a standard flash technology. 
   Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.