Patent Publication Number: US-6709983-B2

Title: Semiconductor processing methods utilizing low concentrations of reactive etching components

Description:
RELATED PATENT DATA 
     This patent resulted from a divisional application of U.S. patent application Ser. No. 10/057,578, which was filed on Jan. 25, 2002. 
    
    
     TECHNICAL FIELD 
     The invention pertains to semiconductor processing methods, and in particular applications pertains to reactive ion etching of semiconductor substrates utilizing low concentrations of reactive etching components. 
     BACKGROUND OF THE INVENTION 
     It is frequently desired during semiconductor processing to form openings in a material. Prior to, or during, the formation of the openings, a patterned mass (such as, for example, an antireflective coating), is frequently provided over the material. After the openings are etched into the material, it is frequently desired to remove the mass from over an upper surface of the material without extending a depth or width of the openings. This has proven difficult, and it would be desirable to develop improved methods for removing a mass from over an upper surface of a material. 
     SUMMARY OF THE INVENTION 
     In one aspect, the invention encompasses a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF 3 . 
     In one aspect, a semiconductor substrate includes a first mass of material, a second mass over the first mass, and an opening extending through the first mass and into the second mass. The second mass has a thickness and the opening has a width. The substrate is subjected to etching conditions which remove at least 250 angstroms from the thickness of the second mass, and which extend the width of the opening by no more than 100 angstroms, in some aspects by no more than 50 angstroms; and in some aspects by no more than 10 angstroms. In further aspects, the etching conditions extend a depth of the opening by no more than 50 angstroms, and in some aspects by no more than 10 angstroms. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Preferred embodiments of the invention are described below with reference to the following accompanying drawings. 
     FIG. 1 is a diagrammatic, cross-sectional view of a semiconductor wafer fragment at a preliminary processing step of a method of the present invention. 
     FIG. 2 is a view of the FIG. 1 wafer fragment shown at a processing step subsequent to that of FIG.  1 . 
     FIG. 3 is a view of the FIG. 1 wafer fragment shown at a processing step subsequent to that of FIG.  2 . 
     FIG. 4 is a view of the FIG. 1 wafer fragment shown at a processing step subsequent to that of FIG.  3 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In particular aspects the invention includes methods in which a biased-substrate plasma is utilized at relatively high pressures (at least 300 mTorr, and in some applications at least about 1000 mTorr) and tow reactive gas concentrations (less than 4.5% by volume, more preferably less than 2% by volume, and even more preferably less, than 1% by volume) to accomplish removal of a top layer of an integrated circuit construction without substantially affecting materials that are in exposed areas at the bottoms or sidewalls of high aspect ratio trenches or contacts. 
     In particular aspects, the invention takes advantage of an etch lag to accomplish desired selectivity of etching various surface features relative to one another. 
     An exemplary method of the present invention is described with reference to FIGS. 1-4. 
     Referring initially to FIG. 1, a fragment of a semiconductor wafer construction  10  is illustrated. Wafer construction  10  comprises a substrate  12 , having an upper surface  15 . Substrate  12  can comprise, for example, monocrystalline silicon. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. 
     An insulative material  14  is formed over substrate  12 . Insulative material  14  can comprise, for example, borophosphosilicate glass (BPSG). 
     A mass  16  is formed over insulative material  14 . Mass  16  can be an antireflective coating  16 . Antireflective coating  16  can be, for example, a dielectric antireflective coating (DARC), and can comprise, for example, silicon oxynitride (SiO x N y , wherein x and y are greater than zero). 
     A patterned masking layer  18  is formed over antireflective coating  16 . Masking layer  18  can comprise, for example, photoresist, and can be patterned utilizing photolithographic methods. 
     An opening  20  extends through patterned masking layer  18 . 
     Referring to FIG. 2, opening  20  is extended through antireflective coating layer  16  and insulative material  14 , and to the upper surface  15  of substrate  12 . Although opening  20  is shown extending entirely through insulative mass  14 , it is to be understood that opening  20  can alternatively extend only partially into insulative mass  14 . Also, it is to be understood that although opening  20  is shown terminating at upper surface  15  of substrate  12 , the opening can also extend into substrate  12 . In any event, opening  20  comprises a bottom periphery  24 , and sidewall peripheries  26 . 
     An electrical node  22  is provided within substrate  12  by implanting a conductivity-enhancing dopant through opening  20  and into the semiconductive material of substrate  12 . Electrical node  22  can comprise either an n-type doped region or a p-type doped region. 
     It is to be understood that the methodology described with reference to FIGS. 1 and 2 for providing electrical node  22  at a base of opening  20  is but one exemplary method, and that other methods can be utilized. For instance, electrical node  22  can comprise a conductive plug formed over or within substrate  12  prior to formation of insulative material  14 . Opening  20  can then be extended to an upper surface of the conductive plug. In such embodiments, the conductive plug can comprise one or more ofconductively-doped silicon (such as polycrystalline silicon), metal, and metal silicide, for example. 
     Opening  20  will preferably be a high aspect ratio opening, and specifically will preferably comprise an aspect ratio of at least 3, more preferably of at least 5, yet more preferably of at least 6, even more preferably of at least about 6.5, and yet more preferably of at least about 7. High aspect ratio openings are typically preferred in semiconductor processing applications over lower aspect ratio openings, in that higher aspect ratio openings consume a lower footprint of valuable semiconductor real estate than do lower aspect ratio openings. 
     Referring to FIG. 3, masking material  18  (FIG. 2) is removed to leave mass  16  over material  14 . Mass  16  has a thickness “X”, and such thickness can be, for example, at least 250 angstroms; in particular applications at least 300 angstroms, and even at least 320 angstroms. 
     Opening  20  has a depth “D” within insulative material  14  and a width “W”. An exemplary depth can be, for example, about 2 microns, and an exemplary width can be, for example, about 0.3 microns. Further, opening  20  can, in particular applications, comprise a circular periphery, such that the width is a diameter of the circle. 
     In particular aspects of the invention, material  14  can be considered a first mass, coating  16  a second mass, and substrate  12  a third mass. Accordingly, opening  20  can be considered to extend through first and second masses  14  and  16 , and to terminate proximate surface  15  of third mass  12 . Alternatively, masses  12 ,  14  and  16  can be considered a first material, second material and third material, respectively; and opening  20  can be considered to extend through second and third materials  14  and  16 , and to terminate proximate surface  15  of first material  12 . 
     Wafer  10  is subsequently exposed to etching conditions which remove a substantial portion of material  16  from over mass  14 . In particular embodiments, an entirety of material  16  is removed to form the resulting structure shown in FIG.  4 . The etching conditions preferably comprise reactive ion etching conditions in which exposed surfaces of wafer  10  are subjected to a gas having components therein which are reactive with material  16 . The components can also be reactive with exposed portions of materials  12  and  14 . In particular applications, the reactive components can comprise fluorine-containing molecules, such as, for example, NF 3 . A total concentration of the reactive components within the gas utilized for reactive etching of material  16  is preferably less than 4.5%, by volume; more preferably less than 2%, by volume; and even more preferably less than 1%, by volume. 
     The reactive ion etching of material  16  will typically occur within a reactive ion etch plasma reactor, and preferably a pressure within the reactor to which wafer  10  is exposed during etching of material  16  will be from about 300 mTorr to about 1000 mTorr. Further, wafer  10  will preferably be subjected to a bias of from about 50 watts to about 2000 watts in the reactive ion etch plasma reactor during etching of material  16 , and can be subjected to an exemplary bias of from about 50 watts to about 500 watts, or from about 350 watts to about 400 watts. A suitable reactor is the Iridia™ reactor marketed by Novellus Systems, Inc. 
     The above-described etching conditions are substantially different than the conditions typically utilized within a reactive ion etch reactor. Specifically, etching within reactive ion reactors would typically be conducted at a pressure of less than 200 mTorr, and with a reactive gas concentration of from about 5% to about 100%, by volume. However, the typical reactive ion etch will remove large amounts of material from exposed surfaces within an opening (such as opening  20 ), as well as from exposed upper surfaces of wafer  10 . In contrast, methodology of the present invention can substantially selectively remove material  16  from exposed upper surfaces of wafer  10 , while not removing material from within opening  20 . More specifically, methodology of the present invention can remove at least 250 angstroms of material  16  from over mass  14  while extending the depth “D” of opening  20  by no more than 50 angstroms. In particular embodiments, at least 300 angstroms of material  16  can be removed from over mass  14 , or least 320 angstroms of material  16  can be removed from over mass  14 , while not extending the depth “D” of opening  20  by more than 50 angstroms; and in further embodiments an entirety of material  16  can be removed from over mass  14  while not extending the depth “D” of opening  20  by more than 50 angstroms. 
     It is noted that bottom periphery  24  is exposed to the etching conditions utilized to remove material  16  during the etch of material  16 , but the low concentration of reactive components of the etching gas, and the high pressure within the reactor, together result in material  16  being removed much more rapidly than is material within opening  20 . The selectivity for material  16  can be enhanced by utilizing openings  20  having a high critical dimension, and accordingly methodology of the present invention can work particularly well for openings having an aspect ratio of at least about 3, even better if the aspect ratio is at least about 6, better if the aspect ratio is at least about 6.5, and better yet if the aspect ratio is at least about 7. 
     It is found that a suitable exposure time for removing 325 angstroms of material  16  from over mass  14  is from about 60 seconds to about 3 minutes in applications in which material  16  comprises silicon oxynitride and mass  14  comprises BPSG. Also, it is found that less than 50 angstroms of material will be etched from a monocrystalline substrate  12  exposed at a bottom of an opening  20  having a width “W” of 0.3 microns, and a depth “D” of about 2 microns during such exposure time and under preferred exposure conditions of the present invention. In a particular embodiment, the initial width “W” of opening  20  is 0.3 microns, the initial depth “D” is 2 microns, and 320 angstroms of material  16  is removed from over mass  14  while extending depth “D” by only from about 0.005 microns to about 0.007 microns into a monocrystalline silicon substrate  12 . 
     A further advantage of methodology of the present invention is that such can avoid increasing width “W” by any significant amount during the removal of material  16 . In particular embodiments, etching conditions of the present invention can remove at least 250 angstroms of thickness “X” of material  16  (FIG. 3) from over mass  14  and yet extend the width “W” of the opening by no more than about 0.010 microns. In particular embodiments, the thickness “X” is reduced by at least about 300 angstroms, or at least about 320 angstroms, and yet the width “W” of opening  20  is not extended by more than 0.010 microns (100 angstroms). In particular aspects of the invention, the width is extend by from about 5 nanometers to about 7 nanometers. 
     Exemplary processes of the present invention include applications other than those discussed above. For instance, in particular aspects the invention includes methods in which a top surface treatment is utilized at relatively high pressures (at least about 300 mTorr, and in particular applications at least about 1000 mTorr, and in further applications from about 300 mTorr to about 4000 mTorr) and low reactive gas concentrations (less than 4.5% by volume, more preferably less than 2% by volume, and even more preferably less than 1% by volume) to accomplish spot planarization across a surface of a semiconductor substrate. Specifically, it is found that the combination of high pressure and low reactive gas concentrations can remove peaks and valleys from across a semiconductor substrate to planarize the surface. In a particular application, a layer of in situ p-type doped polycrystalline silicon (polysilicon) is exposed to a reactive gas comprising O 2  and a low concentration of CF 4 , at a pressure of about 1000 mTorr, to reduce a thickness of the polysilicon from 2200 Å to 1600 Å. Microwave power utilized in the etch is 1500 W. The etching not only reduces the thickness of the polysilicon, but also removes surface defects, and specifically can remove dimples that are 800 Å deep in the initial (2200 Å thick) polysilicon. The etching can occur with little or no power bias (e.g., radiofrequency bias) in order to be relatively isotropic. 
     Particular aspects of the present invention can resemble prior art cleaning procedures. A distinction between etching of the particular aspects of the present invention and the prior art cleaning procedures is that typically only some of a material is removed in the etches, whereas all of a material is typically removed in a cleaning procedure. 
     In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.