Patent Publication Number: US-2022239288-A1

Title: Gated tri-state inverter, and low power reduced area phase interpolator system including same, and method of operating same

Description:
PRIORITY CLAIM 
     This application is a continuation of U.S. application Ser. No. 17/020,528, filed Sep. 14, 2020, which claims the priority of U.S. Provisional Application No. 63/003,035, filed Mar. 31, 2020, each of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     In recent years, demand of high-speed memory interfaces has increased due to progressively increasing requirement to transfer large amounts of data using large bandwidth. 
     In memory interface systems, a phase interpolator generates (interpolates) an intermediate phase clock that is interpolated from (based on) two clocks which have certain phase spacing with respect to each other. In general, a PI facilitates tuning of timing and/or phase alignment. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout. The drawings are not to scale, unless otherwise disclosed. 
         FIGS. 1A, 1B and 1C  are corresponding block diagrams of semiconductor devices, in accordance with at least one embodiment of the present disclosure. 
         FIG. 2  is a block diagram of a Phase-Interpolating system, in accordance with some embodiments. 
         FIG. 3A  is a block diagram of low power, Phase-Interpolating stage, in accordance with some embodiments. 
         FIG. 3B  is a circuit diagram of a gated tri-state (G3S) inverter, in accordance with some embodiments. 
         FIG. 3B ′ is a more-detailed version of  FIG. 3B , in accordance with some embodiments. 
         FIG. 3C  is a circuit diagram of a tri-state (3S) inverter, in accordance with some embodiments. 
         FIG. 3C ′ is a more-detailed version of  FIG. 3C , in accordance with some embodiments. 
         FIG. 3D  is a graph of various waveforms, in accordance with some embodiments. 
         FIGS. 3E, 3F and 3G  are corresponding transistor-state circuit diagrams, in accordance with some embodiments. 
         FIG. 4A  is a circuit diagram of a low-area, tunable capacitive-loading amplifying stage, in accordance with some embodiments. 
         FIG. 4B  is a circuit diagram of a low-area, tunable capacitive-loading amplifying stage, in accordance with some embodiments. 
         FIG. 5  is a flowchart of a method of operating a gated tri-state inverter, in accordance with some embodiments. 
         FIG. 6  is a flowchart of a method of operating a Phase-Interpolating system, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In some embodiments, a phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a weighting signal, and generate an interpolated clock signal, the PI stage having a low power configuration; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a tunable capacitive component, the capacitive component having a Miller effect configuration. 
     According to a first other approach for a PI system, short-circuit currents are suffered which has a disadvantage in that, under certain circumstances, a PI stage thereof suffers a pull-up/pull-down (PUPD) short-circuit situation (discussed below) which increases power consumption and so is referred to as a high power PI stage. According to a second other approach for a PI system, PUPD short-circuits are reduced with the use of discrete combinatorial logic circuitry which, among other things, has a disadvantage of an increased size/footprint and so is referred to as a large footprint PI stage. At least some embodiments provide a PI system which avoids the PUPD short-circuit situation through the use of a low-power PI stage which nevertheless does not suffer and increased size/footprint and so is referred to as small footprint PI stage, and wherein the low power, small footprint PI stage includes: a first cell including parallel connected tri-state (3S) inverters; and a second cell including parallel connected gated tri-state (G3S) inverters. At least some embodiments provide a PI stage which avoids the short-circuit situation because any given 3S inverter, and its corresponding G3S inverter, are reciprocally operated such that: when the given 3S inverter is controlled to be output a logical high signal, the corresponding G3S inverter is controlled to output a logical high signal; and when the given 3S inverter is controlled to be output a logical low signal, the corresponding G3S inverter is controlled to output a logical low signal. Relative to the high power PI stage according to the other approach, PI stage  304  is regarded as low power. At least some embodiments of a PI system achieve a reduced area by using an amplifying stage which includes: an amplifier configured with a feedback loop which capacitively couples an output of the amplifier to an input of the amplifier, thereby exploiting the Miller effect. 
       FIGS. 1A, 1B and 1C  are corresponding block diagrams of corresponding semiconductor devices  100 A,  100 B and  100 C, in accordance with at least one embodiment of the present disclosure. 
     In  FIG. 1A , semiconductor device  100 A includes a Phase-Interpolating (PI) system  102 A. PI system  102 A includes: a low-power, Phase-Interpolating (PI) stage  104 A; and a low-area, tunable-capacitance amplifying stage  106 A. 
     In  FIG. 1B , semiconductor device  100 B includes a PI system  102 B. PI system  102 B includes: low-power PI stage  104 A; and an amplifying stage  106 B. Relative to low-area, tunable-capacitance amplifying stage  106 A of  FIG. 1A , amplifying stage  106 B is not low-area, nor does it have tunable-capacitance. 
     In  FIG. 1C , semiconductor device  100 C includes a PI system  102 C. PI system  102 C includes: a PI stage  104 A; and a low-area, tunable-capacitance amplifying stage  106 A. Relative to the low-power PI stage  104 A of  FIG. 1A , PI stage  1044 C is not low-power. 
       FIG. 2  is a block diagram of a Phase-Interpolating (PI) system  202 , in accordance with some embodiments. 
     PI system  202  includes a low-power, Phase-Interpolating (PI) stage  204 ; and a low-area, tunable-capacitance amplifying stage  206 . 
     PI stage  204  is configured to receive a first clock CLK 1 , a second clock CLK 2  and a multi-bit, binary weighting signal W&lt;(M−1):0&gt;, where M is a positive integer and 2≤M. In  FIG. 2 , for purposes of facilitating discussion, a value of M is assumed, namely M=4, and so W&lt;(M−1):0&gt; is W&lt;3:1&gt;. In some embodiments, 2&lt;M and M≠4. PI stage  204  is configured to output a first phase-interpolated signal OUT 1  at a node  212 . More detail regarding PI stage  204  is provided in the discussion of  FIGS. 3A, 3B, 3B ′,  3 C,  3 C′ and  3 D- 3 F. 
     Low-area, tunable-capacitance amplifying stage  206  is configured to receive signal OUT 1  at node  212 , a multi-bit capacitance-tuning signal CAP&lt;(N−1):0&gt;, where N is a positive integer and 2&lt;N. In  FIG. 2 , N=3, and so CAP&lt;(N−1):0&gt; is CAP&lt;2:0&gt;. In some embodiments, 2≤N and N≠3. Amplifying stage  206  is configured to output an amplified version of first phase-interpolated signal OUT 1  as signal OUT 2  at a node  219 . 
     Amplifying stage  206  includes an inverting amplifier  209  and a tunable capacitance  208 . Inverting amplifier  209  is an analog device, as contrasted with a logical inverter which is a digital device. Inverting amplifier  209  has a gain, G. Tunable capacitance  208  has a variable capacitance C M  and is shown in a Miller-equivalent configuration in  FIG. 2 . In the Miller-equivalent configuration, tunable capacitance  208  is shown as coupled between node  212  and a first system reference voltage, which is ground in  FIG. 2 . In some embodiments, the first system reference voltage is VSS. Tunable capacitance  208  is configured to receive capacitance-tuning signal CAP&lt;(N−1):0&gt;, and thereby adjust the value of variable capacitance C M . More detail regarding amplifying stage  206  is provided by the discussion of  FIGS. 4A-4B . 
       FIG. 3A  is a block diagram of low power, Phase-Interpolating (PI) stage  304 , in accordance with some embodiments. 
     PI stage  304  includes: tri-state (3S) inverters  310 ( 1 ),  310 ( 2 ),  310 ( 3 ) and  310 ( 4 ); and gated tri-state (G3S) inverters  314 ( 1 ),  314 ( 2 ),  314 ( 3 ) and  314 ( 4 ). PI stage  304  is configured to output first phase-interpolated signal OUT 1  at a node  312 . The 3S inverters  310 ( 1 )- 310 ( 4 ) are arranged into a cell  311 . G3S inverters  314 ( 1 )- 314 ( 4 ) are arranged into a cell  315 . 
     Each one of 3S inverters  310 ( 1 )- 310 ( 4 ) includes an input terminal IN, an enable terminal EN and an output terminal. A more detailed view of each of 3S inverters  310 ( 1 )- 310 ( 4 ) is provided in  FIG. 3C . Input terminal IN of each of 3S inverters  310 ( 1 )- 310 ( 4 ) is configured to receive a logical inverse of first clock CLK 1  (CLK 1 _bar). For simplicity of illustration, circuitry to produce CLK 1 _bar from CLK 1  is not shown in  FIG. 3A . The output terminal of each of 3S inverters  310 ( 1 )- 310 ( 4 ) is coupled to node  312 . 
     In  FIG. 3A , for purposes of providing a detailed example of the operation of PI stage  304 , a value of multi-bit, binary weighting signal W&lt;3:0&gt; is assumed, namely W&lt;3:0&gt;=0011. In some embodiments, W&lt;3:0&gt; takes various values other than W&lt;3:0&gt;=0011. Also, it should be recalled that W&lt;3:0&gt; itself is an example of the more general multi-bit, binary weighting signal W&lt;(M−1):0&gt;. 
     Enable terminal EN of 3S inverter  310 ( 1 ) is configured to receive a logical inverse of a first bit W&lt;0&gt;(W&lt;0&gt;_bar) of multi-bit weighting signal W&lt;3:0&gt;. Enable terminal EN of 3S inverter  310 ( 2 ) is configured to receive a logical inverse of a second bit W&lt;1&gt;(W&lt;1&gt;_bar) of multi-bit weighting signal W&lt;3:0&gt;. Enable terminal EN of 3S inverter  310 ( 3 ) is configured to receive a logical inverse of a third bit W&lt;2&gt;(W&lt;2&gt;_bar) of multi-bit weighting signal W&lt;3:0&gt;. Enable terminal EN of 3S inverter  310 ( 4 ) is configured to receive a logical inverse of a fourth bit W&lt;3&gt;(W&lt;3&gt;_bar) of multi-bit weighting signal W&lt;3:0&gt;. For simplicity of illustration, circuitry to produce W&lt;0&gt;_bar-W&lt;3&gt;_bar correspondingly from W&lt;0&gt;-W&lt;3&gt; is not shown in  FIG. 3A . 
     There is one instance, namely 2 bit_position{W&lt;0&gt;}  instance, of 3S inverter  310 ( 1 ) included in PI stage  304 . A label “x1” is shown proximal to 3S inverter  310 ( 1 ). As bit_position{W&lt;1&gt;} is zero, there is 2 bit_position{W&lt;0&gt;} =2 0 =1 instance of 3S inverter  310 ( 1 ) in PI stage  304 , which represents a corresponding group albeit with one member. There are multiple instances, namely 2 bit_position{W&lt;1&gt;}  instances, of 3S inverter  310 ( 2 ) included in PI stage  304 . As bit_position{W&lt;1&gt;} is one, there is 2 bit_position{W&lt;1&gt;} =2 1 =2 instance of 3S inverter  310 ( 2 ) in PI stage  304 , which together represent a corresponding group having multiple members. For simplicity of illustration, only one instance of 3S inverter  310 ( 2 ) is shown in  FIG. 3A . A label “x2” is shown proximal to 3S inverter  310 ( 2 ). There are multiple instances, namely 2 bit_position{W&lt;2&gt;}  instances, of 3S inverter  310 ( 3 ) included in PI stage  304 . As bit_position{W&lt;2&gt;} is two, there are 2 bit_position{W&lt;2&gt;} =2 2 =4 instance of 3S inverter  310 ( 3 ) in PI stage  304 , which together represent a corresponding group having multiple members. For simplicity of illustration, only one instance of 3S inverter  310 ( 3 ) is shown in  FIG. 3A . A label “x4” is shown proximal to 3S inverter  310 ( 3 ). There are multiple instances, namely 2 bit_position{W&lt;3&gt;}  instances, of 3S inverter  310 ( 4 ) included in PI stage  304 . As bit_position{W&lt;3&gt;} is three, there are 2 bit_position{W&lt;3&gt;} =2 3 =8 instance of 3S inverter  310 ( 4 ) in PI stage  304 , which together represent a corresponding group having multiple members. A label “x8” is shown proximal to 3S inverter  310 ( 4 ). For simplicity of illustration, only one instance of 3S inverter  310 ( 3 ) is shown in  FIG. 3A . 
     In  FIG. 3A , each one of G3S inverters  314 ( 1 )- 314 ( 4 ) includes an input terminal IN, an enable terminal EN, a gating terminal G and an output terminal. A more detailed view of each of G3S inverters  314 ( 1 )- 314 ( 4 ) is provided in  FIG. 3B . 
     Input terminal IN of each of G3S inverters  314 ( 1 )- 314 ( 4 ) is configured to receive a logical inverse of second clock CLK 2  (CLK 2 _bar). For simplicity of illustration, circuitry to produce CLK 2 _bar from CLK 2  is not shown in  FIG. 3A . Gating terminal G of each of G3S inverters  314 ( 1 )- 314 ( 4 ) is configured to receive CLK 1 _bar. 
     Each enable terminal EN of corresponding G3S inverters  314 ( 1 )- 314 ( 4 ) is configured to receive a corresponding bit W&lt;i&gt; of multi-bit weighting signal W&lt;3:0&gt;. More particularly, enable terminal EN of G3S inverter  314 ( 1 ) is configured to receive a first bit W&lt;0&gt; of multi-bit weighting signal W&lt;3:0&gt;. Enable terminal EN of G3S inverter  314 ( 2 ) is configured to receive a second bit W&lt;1&gt; of multi-bit weighting signal W&lt;3:0&gt;. Enable terminal EN of G3S inverter  314 ( 3 ) is configured to receive a third bit W&lt;2&gt; of multi-bit weighting signal W&lt;3:0&gt;. Enable terminal EN of G3S inverter  314 ( 4 ) is configured to receive fourth bit W&lt;3&gt; of multi-bit weighting signal W&lt;3:0&gt;. 
     There is one instance, namely 2 bit_position{W&lt;0&gt;}  instance, of G3S inverter  314 ( 1 ) included in PI stage  304 . As bit_position{W&lt;1&gt;} is zero, there is 2 bit_position{W&lt;0&gt;} =2 0 =1 instance of G3S inverter  314 ( 1 ) in PI stage  304 , which represents a corresponding group albeit with one member. A label “x1” is shown proximal to G3S inverter  314 ( 1 ). There are multiple instances, namely 2 bit_position{W&lt;1&gt;}  instances, of G3S inverter  314 ( 2 ) included in PI stage  304 . As bit_position{W&lt;1&gt;} is one, there is 2 bit_position{W&lt;1&gt;} =2 1 =2 instance of G3S inverter  314 ( 2 ) in PI stage  304 , which together represent a corresponding group having multiple members. For simplicity of illustration, only one instance of G3S inverter  314 ( 2 ) is shown in  FIG. 3A . A label “x2” is shown proximal to G3S inverter  314 ( 2 ). There are multiple instances, namely 2 bit_position{W&lt;2&gt;}  instances, of G3S inverter  314 ( 3 ) included in PI stage  304 . As bit_position{W&lt;2&gt;} is two, there are 2 bit_position{W&lt;2&gt;} =2 2 =4 instance of G3S inverter  314 ( 3 ) in PI stage  304 , which together represent a corresponding group having multiple members. For simplicity of illustration, only one instance of G3S inverter  314 ( 3 ) is shown in  FIG. 3A . A label “x4” is shown proximal to G3S inverter  314 ( 3 ). There are multiple instances, namely 2 bit_position{W&lt;3&gt;}  instances, of G3S inverter  314 ( 4 ) included in PI stage  304 . As bit_position{W&lt;3&gt;} is three, there are 2 bit_position{W&lt;3&gt;} =2 3 =8 instance of G3S inverter  314 ( 4 ) in PI stage  304 , which together represent a corresponding group having multiple members. A label “x8” is shown proximal to G3S inverter  314 ( 4 ). For simplicity of illustration, only one instance of G3S inverter  314 ( 3 ) is shown in  FIG. 3A . 
     According to a first other approach, a PI stage otherwise corresponding to PI stage  304  uses first and second groups each of which has only 3S inverters rather than cell  311  of 3S inverters  310 ( 1 )- 310 ( 4 ) and cell  315  of G3S inverters  314 ( 1 )- 314 ( 5 ) of PI stage  304 . According to the first other approach, some combinations of states of CLK 1  and CLK 2  create circumstances in which one or more of the 3S inverters are controlled to pull the common output node up towards VDD while one or more of the 3S inverters are controlled to pull the common output node down towards VSS, which represents a pull-up/pull-down (PUPD) type of short-circuit (PUPD short-circuit) situation that consumes a large amount of power. Accordingly, the first other approach is described as a high power PI stage. According to a second other approach for a PI system, PUPD short-circuits are reduced by combining the first and second 3S-inverter-only groups of the first other approach with discrete gating circuitry which, among other things, has a disadvantage of an increased size/footprint and so is referred to as a large footprint PI stage. An advantage of PI stage  304  is that it avoids the PUPD short-circuit situation without having to use discrete combinatorial logic circuitry in contrast the second other approach, which is because any given 3S inverter, e.g.,  310 ( 1 ), and its corresponding G3S inverter, e.g.,  314 ( 1 ) are reciprocally operated by (among other signals) corresponding weighting signals W&lt;0&gt;_bar and W&lt;0&gt;. 
     such that: when 3S inverter  310 ( 1 ) is controlled to output a logical high signal, corresponding G3S inverter  314 ( 1 ) is controlled to output a logical high signal; and when 3S inverter  310 ( 1 ) is controlled to output a logical low signal, corresponding G3S inverter  314 ( 1 ) is controlled to output a logical low signal. Relative to the high power PI stage according to the other approach, PI stage  304  is regarded as low power. 
       FIG. 3B  is a circuit diagram of a gated tri-state (G3S) inverter  314 ( 5 ), in accordance with some embodiments. 
       FIG. 3B ′ is a more-detailed version  314 ( 5 )′ of G3S inverter  314 ( 5 ) of  FIG. 3B , in accordance with some embodiments. 
     G3S inverter  314 ( 5 ) in  FIG. 3B  is an example of each of G3S inverters  314 ( 1 )- 314 ( 4 ) of  FIG. 3A . G3S inverter  314 ( 5 ) has applications other than its inclusion in PI stage  304 . Accordingly,  FIG. 3B  shows G3S inverter  314 ( 5 ) as a separate device and so does not introduce the signal-coupling of PI stage  304 . By contrast,  FIG. 3B ′ shows G3S inverter  314 ( 5 )′ in the context of the signal-coupling of PI stage  304 . 
     G3S inverter  314 ( 5 ) includes transistors P 1 , P 2 , P 3 , N 1 , N 2  and N 3  serially coupled (or daisy-chained) between a second system reference voltage, which is VDD in  FIG. 3B  (and also in  FIGS. 3B ′,  3 C and  3 C′), and VSS. In some embodiments, the second system reference voltage is a different voltage than VSS other than VDD. In some embodiments, each of transistors P 1 -P 3  is a PMOS transistor. In some embodiments, each of transistors N 1 -N 3  is an NMOS transistor. 
     In  FIG. 3B , transistor P 1  is coupled between VDD and a node  318 ( 1 ). Transistor P 2  is coupled between node  318 ( 1 ) and a node  318 ( 2 ). Transistor P 3  is coupled between node  318 ( 2 ) and a node  318 ( 3 ). Transistor N 1  is coupled between node  318 ( 3 ) and a node  318 ( 4 ). Transistor N 2  is coupled between node  318 ( 4 ) and a node  318 ( 5 ). Transistor N 3  is coupled between node  318 ( 5 ) and VSS. 
     A gate terminal of each of transistors P 1  and N 3  is configured to receive an input signal on the input terminal IN of G3S inverter  314 ( 5 ). As such, the gate terminal of transistor P 1  is coupled to the gate terminal of transistor N 3 . A gate terminal of each of transistors P 2  and N 2  is configured to receive a gating signal on the gating terminal G of G3S inverter  314 ( 5 ). As such, the gate terminal of transistor P 2  is coupled to the gate terminal of transistor N 2 . An example of a difference between  FIG. 3B ′ and  FIG. 3B  is that  FIG. 3B ′ shows a signal line which couples the gate terminals of transistors P 2  and N 2 . 
     A gate terminal of transistor N 1  is configured to receive an enable signal on the enable terminal EN of G3S inverter  314 ( 5 ). A gate terminal of transistor P 3  is configured to receive a logical inverse of the enable signal (enable_bar signal) on the enable terminal EN of G3S inverter  314 ( 5 ). 
     Again,  FIG. 3B ′ shows G3S inverter  314 ( 5 )′ in the context of the signal-coupling of PI stage  304 . Accordingly, in  FIG. 3B ′, the following is shown: node  318 ( 3 ) is the same as node  312  in  FIG. 3A ; the input signal on the gate terminal of each of transistors P 1  and N 3  is CLK 2 _bar; the gating signal on the gate terminal of each of transistors P 2  and N 2  is CLK 1 _bar; the enable signal on the gate terminal of transistor N 1  is corresponding bit W&lt;i&gt; of multi-bit weighting signal W&lt;3:0&gt;; and the enable_bar signal on the gate terminal of transistor P 3  is a logical inverse of corresponding bit W&lt;i&gt;(W&lt;i&gt;_bar) of multi-bit weighting signal W&lt;3:0&gt;. 
     The operation of G3S inverter  314 ( 5 )′ of  FIG. 3B ′ is further described by the following Truth Tables 1-5. 
     In Truth Table 1 (below), the enable (E) signal has a logical low state (logical zero), where E=0=W&lt;i&gt;. Accordingly, each of transistors P 3  and N 1  is turned off, thereby present a high impedance (high Z) to node  318 ( 3 ) in  FIG. 3B ′ (which, again, is the same as node  312  in FIG.  3 A). When E=0=W&lt;i&gt;, the logical states of the input signal CLK 2 _bar and the gating signal CLK 1 _bar do not substantially affect the state of the signal on node  318 ( 3 ). As such, in Truth Table 1, the logical states of the input signal CLK 2 _bar and the gating signal CLK 1 _bar are labeled “don&#39;t care” (dc). 
     
       
         
           
               
            
               
                   
               
               
                 Truth Table 1 
               
            
           
           
               
               
               
               
               
            
               
                   
                 CLK2 = dc 
                 CLK1 = dc 
                   
                   
               
               
                   
                 CLK2_bar = dc 
                 CLK1_bar = dc 
               
               
                   
                 IN = dc 
                 G = dc 
                 E = 0 
                 OUT 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
            
               
                 P1 
                 don&#39;t care (dc) 
                   
                   
                   
               
               
                 P2 
                   
                 don&#39;t care 
               
               
                 P3 
                   
                   
                 OFF 
               
               
                 N1 
                   
                   
                 OFF 
               
               
                 N2 
                   
                 don&#39;t care 
               
               
                 N3 
                 don&#39;t care 
               
               
                 OUT 
                   
                   
                   
                 Z 
               
               
                   
               
            
           
         
       
     
     In each of Truth Tables 2-5 (below), the enable (E) signal has a logical high state (logical one), where E=1=W&lt;i&gt;. Accordingly, each of transistors P 3  and N 1  is turned on. When E=1=W&lt;i&gt;, the state of the signal on node  318 ( 3 ) is controlled by the states of the input signal CLK 2 _bar and the gating signal CLK 1 _bar. 
     In Truth Table 2 (below), the input signal CLK 2 _bar has a logical low state such that IN=CLK 2 _bar=0, and the gating signal CLK 1 _bar has a logical high state such that G=CLK 1 _bar=1. When IN=CLK 2 _bar=0, transistor P 1  is turned on and transistor N 3  is turned off. When G=CLK 1 _bar=1, transistor P 2  is turned off and transistor N 2  is turned on. As a result of each of transistors P 2  and N 3  being turned off, a high impedance (high Z) is presented to node  318 ( 3 )/ 312  in  FIG. 3B ′. 
     
       
         
           
               
            
               
                   
               
               
                 Truth Table 2 
               
            
           
           
               
               
               
               
               
            
               
                   
                 CLK2 = 1 
                 CLK1 = 0 
                   
                   
               
               
                   
                 CLK2_bar = 0 
                 CLK1_bar = 1 
               
               
                   
                 IN = 0 
                 G = 1 
                 E = 1 
                 OUT 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
            
               
                 P1 
                 ON 
                   
                   
                   
               
               
                 P2 
                   
                 OFF 
               
               
                 P3 
                   
                   
                 ON 
               
               
                 N1 
                   
                   
                 ON 
               
               
                 N2 
                   
                 ON 
               
               
                 N3 
                 OFF 
               
               
                 OUT 
                   
                   
                   
                 Z 
               
               
                   
               
            
           
         
       
     
     In Truth Table 3 (below), the input signal CLK 2 _bar has a logical high state such that IN=CLK 2 _bar=1, and the gating signal CLK 1 _bar has a logical low state such that G=CLK 1 _bar=0. When IN=CLK 2 _bar=1, transistor P 1  is turned off and transistor N 3  is turned ON. When G=CLK 1 _bar=0, transistor P 2  is turned on and transistor N 2  is turned off. As a result of each of transistors P 1  and N 2  being turned off, a high impedance (high Z) is presented to node  318 ( 3 )/ 312  in  FIG. 3B ′. 
     
       
         
           
               
            
               
                   
               
               
                 Truth Table 3 
               
            
           
           
               
               
               
               
               
            
               
                   
                 CLK2 = 0 
                 CLK1 = 1 
                   
                   
               
               
                   
                 CLK2_bar = 1 
                 CLK1_bar = 0 
               
               
                   
                 IN = 1 
                 G = 0 
                 E = 1 
                 OUT 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
            
               
                 P1 
                 OFF 
                   
                   
                   
               
               
                 P2 
                   
                 ON 
               
               
                 P3 
                   
                   
                 ON 
               
               
                 N1 
                   
                   
                 ON 
               
               
                 N2 
                   
                 OFF 
               
               
                 N3 
                 ON 
               
               
                 OUT 
                   
                   
                   
                 Z 
               
               
                   
               
            
           
         
       
     
     In Truth Table 4 (below), the input signal CLK 2 _bar has a logical low state such that IN=CLK 2 _bar=0, and the gating signal CLK 1 _bar has a logical low state such that G=CLK 1 _bar=0. When IN=CLK 2 _bar=0, transistor P 1  is turned on and transistor N 3  is turned off. When G=CLK 1 _bar=0, transistor P 2  is turned on and transistor N 2  is turned off. As a result of each of transistors P 1  and P 2  being turned on, and each of transistors N 2  and N 3  being turned off, node  318 ( 3 )/ 312  in  FIG. 3B ′ is pulled up to a logical high state. 
     
       
         
           
               
            
               
                   
               
               
                 Truth Table 4 
               
            
           
           
               
               
               
               
               
            
               
                   
                 CLK2 = 1 
                 CLK1 = 1 
                   
                   
               
               
                   
                 CLK2_bar = 0 
                 CLK1_bar = 0 
               
               
                   
                 IN = 0 
                 G = 0 
                 E = 1 
                 OUT 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
            
               
                 P1 
                 ON 
                   
                   
                   
               
               
                 P2 
                   
                 ON 
               
               
                 P3 
                   
                   
                 ON 
               
               
                 N1 
                   
                   
                 ON 
               
               
                 N2 
                   
                 OFF 
               
               
                 N3 
                 OFF 
               
               
                 OUT 
                   
                   
                   
                 1 
               
               
                   
               
            
           
         
       
     
     In Truth Table 5 (below), the input signal CLK 2 _bar has a logical high state such that IN=CLK 2 _bar=1, and the gating signal CLK 1 _bar has a logical high state such that G=CLK 1 _bar=1. When IN=CLK 2 _bar=1, transistor P 1  is turned off and transistor N 3  is turned on. When G=CLK 1 _bar=1, transistor P 2  is turned off and transistor N 2  is turned on. As a result of each of transistors P 1  and P 2  being turned off, and each of transistors N 2  and N 3  being turned on, node  318 ( 3 )/ 312  in  FIG. 3B ′ is pulled down to a logical low state. 
     
       
         
           
               
            
               
                   
               
               
                 Truth Table 5 
               
            
           
           
               
               
               
               
               
            
               
                   
                 CLK2 = 0 
                 CLK1 = 0 
                   
                   
               
               
                   
                 CLK2_bar = 1 
                 CLK1_bar = 1 
               
               
                   
                 IN = 1 
                 G = 1 
                 E = 1 
                 OUT 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
            
               
                 P1 
                 OFF 
                   
                   
                   
               
               
                 P2 
                   
                 OFF 
               
               
                 P3 
                   
                   
                 ON 
               
               
                 N1 
                   
                   
                 ON 
               
               
                 N2 
                   
                 ON 
               
               
                 N3 
                 ON 
               
               
                 OUT 
                   
                   
                   
                 0 
               
               
                   
               
            
           
         
       
     
       FIG. 3C  is a circuit diagram of a tri-state (3S) inverter  310 ( 5 ), in accordance with some embodiments. 
       FIG. 3C ′ is a more-detailed version  310 ( 5 )′ of 3S inverter  310 ( 5 ) of  FIG. 3C , in accordance with some embodiments. 
     The 3S inverter  310 ( 5 ) in  FIG. 3C  is an example of each of 3S inverters  310 ( 1 )- 310 ( 4 ) of  FIG. 3A . The 3S inverter  310 ( 5 ) has applications other than its inclusion in PI stage  304 . Accordingly,  FIG. 3C  shows 3S inverter  310 ( 5 ) as a separate device and so does not introduce the signal-coupling of PI stage  304 . By contrast,  FIG. 3C ′ shows 3S inverter  310 ( 5 )′ in the context of the signal-coupling of PI stage  304 . 
     The 3S inverter  310 ( 5 ) includes transistors P 4 , P 5 , N 4  and N 5  serially coupled (or daisy-chained) between VDD and VSS. In some embodiments, each of transistors P 4 -P 5  is a PMOS transistor. In some embodiments, each of transistors N 4 -N 5  is an NMOS transistor. 
     In  FIG. 3C , transistor P 4  is coupled between VDD and a node  316 ( 1 ). Transistor P 5  is coupled between node  316 ( 1 ) and a node  316 ( 2 ). Transistor N 4  is coupled between node  316 ( 2 ) and a node  316 ( 3 ). Transistor N 5  is coupled between node  316 ( 3 ) and VSS. 
     A gate terminal of each of transistors P 4  and N 5  is configured to receive an input signal on the input terminal IN of 3S inverter  310 ( 5 ). As such, the gate terminal of transistor P 4  is coupled to the gate terminal of transistor N 5 . A gate terminal of transistor N 4  is configured to receive an enable signal on the enable terminal EN of 3S inverter  310 ( 5 ). A gate terminal of transistor P 5  is configured to receive a logical inverse of the enable signal (enable_bar signal) on the enable terminal EN of 3S inverter  310 ( 5 ). 
     Again,  FIG. 3C ′ shows 3S inverter  310 ( 5 )′ in the context of the signal-coupling of PI stage  304 . Accordingly, in  FIG. 3C ′, the following is shown: node  316 ( 2 ) is the same as node  312  in  FIG. 3A ; the input signal on the gate terminal of each of transistors P 4  and N 5  is CLK 1 _bar; the enable_bar signal on the gate terminal of transistor P 5  is corresponding bit W&lt;i&gt; of multi-bit weighting signal W&lt;3:0&gt;; and the enable signal on the gate terminal of transistor N 4  is W&lt;i&gt;_bar, which (again) is the logical inverse of corresponding bit W&lt;i&gt; ( ) of multi-bit weighting signal W&lt;3:0&gt;. 
       FIG. 3D  is a graph of various waveforms related to the operation of PI stage  304 , in accordance with some embodiments. 
       FIGS. 3E, 3F and 3G  are corresponding transistor-state circuit diagrams which relate G3S inverter  314 ( 5 )′ of  FIG. 3B ′ and 3S inverter  310 ( 5 )′ of  FIG. 3C ′ to the waveforms of  FIG. 3D , in accordance with some embodiments. 
       FIG. 3D  includes: a waveform  320  representing CLK 1  of  FIG. 3A ; a waveform  322  representing CLK 2  of  FIG. 3A ; and a waveform  324  representing OUT 1  of  FIG. 3A .  FIG. 3D  includes points in time T 1 , T 2 , T 3  and T 4 . 
     In each of  FIGS. 3E-3F , the enable (E) signal has a logical high state (logical one), where E=1=W&lt;i&gt;. Accordingly, each of transistors P 3  and N 1  is turned on. When E=1=W&lt;i&gt;, the operation of G3S  314 ( 5 )′ is controlled by the states of the input signal CLK 2 _bar and the gating signal CLK 1 _bar, and the operation of 3S inverter  310 ( 5 )′ is controlled by the state of the input signal CLK 1 _bar. 
       FIG. 3E  corresponds to time T 1  in  FIG. 3D , and to Truth Table 5 (above). Regarding 3S inverter  310 ( 5 )′ in  FIG. 3E , when the input signal CLK 1 _bar=1, transistor P 4  is turned off and transistor N 5  is turned on. As a result, transistors N 4  and N 5  pull node  316 ( 2 )/ 312  down to a logical low state so that waveform  324  of signal OUT 1  has a logical low value in  FIG. 3D  at time T 1 . 
       FIG. 3F  corresponds to time T 2  in  FIG. 3D .  FIG. 3F  also corresponds to Truth Table 3 (above) so that G3S inverter  314 ( 5 )′ presents a high impedance (high Z) to node  318 ( 3 )/ 312  in  FIG. 3B ′. Regarding 3S inverter  310 ( 5 )′ in  FIG. 3F , when the input signal CLK 1 _bar=0, transistor P 4  is turned on and transistor N 5  is turned off. As a result, transistors P 4  and P 5  pull node  316 ( 2 )/ 312  up towards VDD so that waveform  324  of signal OUT 1  in  FIG. 3D  has a value that rises from VSS after time T 2  to a value approximately midway between VSS and VDD at time T 3 . 
       FIG. 3G  corresponds to time T 3  in  FIG. 3D .,  FIG. 3G  also corresponds to Truth Table 4 (above) so that G3S inverter  314 ( 5 )′ pulls node  318 ( 3 )/ 312  up towards VDD. Regarding 3S inverter  310 ( 5 )′ in  FIG. 3G , when the input signal CLK 1 _bar=0, transistor P 4  is turned on and transistor N 5  is turned off. As a result, transistors P 4  and P 5  pull node  316 ( 2 )/ 312  up towards VDD so that waveform  324  of signal OUT 1  in  FIG. 3D  has a value that rises from a value approximately midway between VSS and VDD at time T 3  to approximately VDD at time T 4 . In some embodiments, a maximum value of signal OUT 1  is VDD. 
       FIG. 4A  is a circuit diagram of a low-area, tunable capacitive-loading amplifying stage  406 , in accordance with some embodiments. 
     Amplifying stage  406  corresponds to amplifying stage  206  of  FIG. 2 . Amplifying stage  406  includes an inverting amplifier  409 ( 1 ) and a tunable capacitance  408 . Inverting amplifier  409 ( 1 ) is an analog inverting amplifier that has a gain G and that corresponds to inverting amplifier  209 . Tunable capacitance  408  has a variable capacitance C C  and corresponds to tunable capacitance  208  of  FIG. 2 . Tunable capacitance  408  is configured to receive capacitance-tuning signal CAP&lt;(N−1):0&gt;, and thereby adjust the value of variable capacitance C C . 
     Tunable capacitance  408  is arranged in a feedback loop and so is coupled between an output and an input of inverting amplifier  409 ( 1 ). For a given capacitor which has a first capacitance when measured as a discrete element, when the given capacitor is included in a circuit and more particularly is arranged in feedback loop of an inverting amplifier such tunable capacitance  408  in  FIG. 4A , the given capacitor interacts with internal capacitances (not shown) of the inverting amplifier so as to behave in the circuit as if the given capacitor has a larger second capacitance. This behavior is referred to as the Miller effect, and the effective larger second capacitance is referred to as the Miller capacitance, C M . In particular, C M =C c  (1+G). Recalling that tunable capacitance  408  of  FIG. 4A  corresponds to tunable capacitance  208  of  FIG. 2 , the depiction of tunable capacitance  208  in  FIG. 2  uses the Miller-equivalent configuration to represent the feedback arrangement of tunable capacitance  408  in  FIG. 4A . 
     According to another approach, an amplifying stage otherwise corresponding to amplifying stage  406  does not use a capacitive element in a feedback loop of an inverting amplifier. Compared to the other approach, an advantage of amplifying stage  406  is a reduced size of tunable capacitance  408  that is achieved by the Miller effect of the feedback loop, wherein the corresponding footprint of amplifying stage  406  is reduced. 
       FIG. 4B  is a circuit diagram of a low-area, tunable capacitive-loading amplifying stage  406 ′, in accordance with some embodiments. 
     Amplifying stage  406 ′ of  FIG. 4B  corresponds to amplifying stage  406  of  FIG. 4A . Tunable capacitance  408  of  FIG. 4A  is shown as tunable capacitor network  408 ′ in  FIG. 4B . Coupled in parallel between the input and the output of inverting amplifier  409 ( 2 ), tunable capacitor network  408 ′ includes: a series-coupling of a switch  428 ( 1 ) and a capacitor  416 ( 1 ); a series-coupling of a switch  428 ( 2 ) and a capacitor  416 ( 2 ); and a series-coupling of a switch  428 ( 3 ) and a capacitor  416 ( 3 ). 
     In  FIG. 4B , capacitor  426 ( 1 ) has a capacitance of Cx, where Cx represents a unit of capacitance. Capacitor  426 ( 2 ) has a capacitance of 2*Cx. Capacitor  426 ( 3 ) has a capacitance of 4*Cx. In some embodiments, the values of capacitors  426 ( 1 )- 426 ( 3 ) are various combinations of values other than the corresponding ratio of 1:2:4. 
     Each of switches  428 ( 1 )- 428 ( 3 ) is configured to receive a corresponding bit CAP&lt;i&gt; of multi-bit capacitance-tuning signal CAP&lt;2:0&gt;. More particularly, switch  428 ( 1 ) is configured to receive a first bit CAP&lt;0&gt; of CAP&lt;2:0&gt;. Switch  428 ( 2 ) is configured to receive a second bit CAP&lt;1&gt; of CAP&lt;2:0&gt;. Switch  428 ( 3 ) is configured to receive a third bit CAP&lt;2&gt; of CAP&lt;2:0&gt;. Accordingly, CAP&lt;2:0&gt; is used to selectively connect one of more of capacitors  426 ( 1 )- 426 ( 3 ) between the input and the output of inverting amplifier  409 ( 2 ), and thereby adjust the total capacitance between the input and the output of inverting amplifier  409 ( 2 ). 
     As compared to amplifying stage  406  of  FIG. 4A , amplifying stage  406 ′ further includes an analog inverting amplifier  409 ( 2 ). The input of inverting amplifier  409 ( 2 ) is coupled to the output of inverting amplifier  409 ( 1 ) and so is configured to receive signal OUT 2 . The output of inverting amplifier  409 ( 2 ) is configured to provide a signal OUTS. 
       FIG. 5  is a flowchart of a method  500  of operating a gated tri-state (G3S) inverter, in accordance with some embodiments. 
     Method  500  includes blocks  502 - 514 . At block  4502 , an input signal, a gating signal and an enable signal are received by the G3S inverter. An example of the G3S inverter is G3S inverter  314 ( 5 ) of  FIG. 3B . From block  502 , flow proceeds to block  504 . 
     At block  504 , a decision is made whether the enable signal has a logical low value. If the answer at decision block  504  is yes, then flow proceeds to block  506 . At block  506 , a high impedance (high Z) is generated at the output of the G3S inverter. An example of a high impedance (high Z) being generated at the output of the G3S inverter is the context of Truth Table 1. If, however, the answer at decision block  504  is no, then flow proceeds to block  508 . 
     At block  508 , a decision is made whether each of the input signal and the gating signal has the same logical state. If the answer at decision block  508  is no, then flow proceeds to block  506 . Examples of the input signal and the gating signal not having the same logical state are the context of Truth Table 2 and the context of Truth Table 3. If, however, the answer at decision block  508  is yes, then flow proceeds to block  508 . 
     At block  510 , a decision is made whether each of the input signal and the gating signal has a logical low state. If the answer at decision block  510  is no, then flow proceeds to block  512 . At block  512 , a logical low state is generated at the output of the G3S inverter. An example a logical low state being generated at the output of the G3S inverter is the context of Truth Table 5. If, however, the answer at decision block  510  is yes, then flow proceeds to block  514 . At block  514 , a logical high state is generated at the output of the G3S inverter. An example a logical high state being generated at the output of the G3S inverter is the context of Truth Table 4. 
       FIG. 6  is a flowchart of a method  600  of operating a Phase-Interpolating (PI) system, in accordance with some embodiments. 
     An example of the PI system operated according to method  600  is PI system  202 , which includes PI stage  204  and amplifying stage  206 . An example of PI stage  204  is PI stage  304  of  FIG. 3A , where PI stage  304  includes 3S inverters  310 ( 1 )- 310 ( 4 ) and G3S inverters  314 ( 1 )- 314 ( 4 ). An example of each of 3S inverters  310 ( 1 )- 310 ( 4 ) is 3S inverter  310 ( 5 )′ of  FIG. 3C ′. An example of each of G3S inverters  314 ( 1 )- 314 ( 4 ) is G3S inverter  314 ( 5 )′ of  FIG. 3B ′. 
     Method  600  includes blocks  602 - 612 . Flow proceeds in parallel to each of blocks  602  and  606 . Blocks  602 - 604  relate to the operation of the G3S inverters included in PI stage  304 . At block  602 , a first clock, a second clock signal and a corresponding bit component of a multi-bit weighting signal are received by each of the G3S inverters in the PI stage. Again, an example of the G3S inverters included in PI stage  304  is G3S inverter  314 ( 5 )′ of  FIG. 3B ′. An example of the first clock signal is CLK 1 , wherein an inverted version (CLK 1 _bar) of CLK 1  is received at the gating terminal G of G3S inverter  314 ( 5 )′. An example of the second clock signal is CLK 2 , wherein an inverted version (CLK 2 _bar) of CLK 2  is received at the input terminal IN of G3S inverter  314 ( 5 )′. An example of the corresponding bit component of the multi-bit weighting signal is W&lt;i&gt;. 
     Block  602  includes block  620 . At block  620 , for each G3S group, the same corresponding bit component is received at each G3S inverter in the G3S group. An example of each G3S inverter in a given group receiving the same bit component is the eight instances of G3S inverter  314 ( 4 ) in  FIG. 3A  that each receive W&lt;3&gt;. From block  620 , flow exits block  602  and proceeds to block  604 . 
     At block  604 , each of the G3S inverters provides a corresponding first signal to a common node. An example of the common node is node  312  in  FIG. 3A . Block  604  includes blocks  640 - 644 . 
     At block  640 , for each of the G3S inverters, a decision is made whether the corresponding bit component has a logical high state. If the answer at decision block  640  is no, then flow proceeds to block  642 . At block  642 , the corresponding G3S inverter is controlled to output a logical low signal. An example of controlling the G3S inverter to output a logical low signal is shown in  FIG. 3E . If, however, the answer at decision block  640  is yes, then flow proceeds to block  644 . At block  644 , the corresponding G3S inverter is controlled to output a logical high signal. An example of controlling the G3S inverter to output a logical high signal is shown in  FIG. 3G . From each of blocks  642  and  644 , flow exits block  604  and proceeds to block  610 . 
     Blocks  606 - 608  relate to the operation of the 3S inverters included in PI stage  304 . Again, an example of the 3S inverters included in PI stage  304  is 3S inverter  310 ( 5 )′ of  FIG. 3C ′. 
     At block  606 , a first clock and a corresponding bit_bar component of the multi-bit weighting signal are received by each of the 3S inverters in the PI stage. Again, an example of the 3S inverters included in PI stage  304  is 3S inverter  310 ( 5 )′ of  FIG. 3C ′. An example of the first clock signal is CLK 1 , wherein an inverted version (CLK 1 _bar) of CLK 1  is received at the input terminal IN of 3S inverter  310 ( 5 )′. An example of the corresponding bit_bar component of the multi-bit weighting signal is W&lt;i&gt;_bar. 
     Block  606  includes block  630 . At block  630 , for each 3S group, the same corresponding bit_bar component is received at each 3S inverter in the 3S group. An example of each 3S inverter in a given group receiving the same bit_bar component is the eight instances of 3S inverter  310 ( 4 ) in  FIG. 3A  that each receive W&lt;3&gt;. From block  630 , flow exits block  606  and proceeds to block  608 . 
     At block  608 , each of the 3S inverters provides a corresponding second signal to the common node. Again, an example of the common node is node  312  in  FIG. 3A . Block  608  includes blocks  650 - 654 . 
     At block  650 , for each of the 3S inverters, a decision is made whether the corresponding bit_bar component has a logical low state. If the answer at decision block  650  is no, then flow proceeds to block  652 . At block  652 , the corresponding 3S inverter is controlled to output a logical low signal. An example of controlling the 3S inverter to output a logical low signal is shown in each of  FIG. 3E . If, however, the answer at decision block  650  is yes, then flow proceeds to block  654 . At block  654 , the corresponding 3S inverter is controlled to output a logical high signal. An example of controlling the 3S inverter to output a logical high signal is shown in  FIG. 3G . From each of blocks  652  and  654 , flow exits block  608  and proceeds to block  610 . 
     At block  610 , the first and second signals on the common node are summed to form an interpolated signal. Again, an example of the common node is node  312  in  FIG. 3A . An example of summing the first and second signals on the common node to form an interpolated signal is shown in each of  FIGS. 3F and 3G . From block  610 , flow proceeds to block  612 . 
     At block  612 , the sum of the first and second signals (representing the interpolated signal) is amplified. An example of amplifying the sum of the first and second signals (representing the interpolated signal) is signal OUT 2  at the output of inverting amplifier  409 ( 1 ) in  FIG. 4B , which is yet further amplified by inverting amplifier  409 ( 2 ) to produce signal OUTS. 
     In an embodiment, a phase interpolating (PI) system includes: a PI stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component. The capacitive component is tunable to exhibit non-zero capacitances. The capacitive component has a Miller effect configuration resulting in a reduced footprint of the amplifying stage. 
     In some embodiments, the amplifying stage includes: an amplifier, an input of the amplifier being configured to receive an output of the PI stage, and an output of the amplifier representing an output of the amplifying stage; and the capacitive component is a feedback loop which couples the output of the amplifier to the input of the amplifier. In some embodiments, the feedback loop includes: a network of selectable, parallel connected capacitive paths coupled between the input and output of the amplifier. In some embodiments, the network of selectable, parallel connected capacitive paths includes: a switchable first capacitive path represents a first capacitance; a switchable second capacitive path represents a second capacitance; and a switchable third capacitive path represents a third capacitance; and wherein the first capacitance is less than the second capacitance; and the second capacitance is less than the third capacitance. In some embodiments, the first capacitance represents a unit value (x) of capacitance; the second capacitance represents a 2× value of capacitance; and the third capacitance represents a 4× value of capacitance. 
     In some embodiments, the PI stage is further configured to avoid a pull-up/pull-down (PUPD) short-circuit situation by using the multi-bit weighting signal and a logical inverse thereof (multi-bit weighting_bar signal). In some embodiments, the PI stage includes: a first cell including parallel connected gated tri-state (G3S) inverters; each of the G3S inverters being configured to receive the first clock signal, the second clock signal and a corresponding bit component of the multi-bit weighting signal, and to provide a corresponding signal on a common output node; and a second cell including parallel connected tri-state (3S) inverters; and each of the 3S inverters being configured to receive the first clock signal and a logical inverse of the corresponding bit component (corresponding bit_bar component) of the multi-bit weighting signal, and to provide a corresponding signal on the common output node. In some embodiments, each G3S inverter includes: first, second and third PMOS transistors and first, second and third NMOS transistors serially connected between a first reference voltage and second reference voltage; and wherein gate terminals of an alpha one of the first, second and third PMOS transistors and an alpha one of the first, second and third NMOS transistors are configured to receive an input signal of the G3S inverter; gate terminals of a beta one of the first, second and third PMOS transistors and a beta one of the first, second and third NMOS transistors are configured to receive a gating signal of the G3S inverter; and a gate terminal of a gamma one of the first, second and third NMOS transistors is configured to receive an enable signal; and a gate terminal of a gamma one of the first, second and third PMOS transistors is configured to receive an enable_bar signal. In some embodiments, the first PMOS transistor is coupled between the first reference voltage and a first node; the second PMOS transistor is coupled between the first node and a second node; the third PMOS transistor is coupled between the second node and a third node, the third node representing an output of the GS3 inverter; the first NMOS transistor is coupled between the third node and a fourth node; the second NMOS transistor is coupled between the fourth node and a fifth node; and the third NMOS transistor is coupled between the fifth node and the second reference voltage. 
     In some embodiments, each G3S inverter includes: an input terminal configured to receive the second clock signal; an output terminal coupled to a common node; an enable terminal configured to receive the corresponding bit component of the multi-bit weighting signal; and a gating terminal configured to receive the first clock signal; and each 3S inverter includes: an input terminal configured to receive the first clock signal; an output terminal coupled to the common node; and an enable terminal configured to receive the corresponding bit_bar component of the multi-bit weighting signal. In some embodiments, the G3S inverters in the first cell are organized into G3S groups; the 3S inverters in the second cell are organized into 3S groups which correspond to the G3S groups; for each G3S group, the G3S inverters included therein receive a same corresponding bit component of the multi-bit weighting signal; and for each 3S group, the 3S inverters included therein receive a same corresponding bit_bar component of the multi-bit weighting signal. In some embodiments, the G3S groups have different corresponding total numbers of G3S inverters included therein; for each G3S group, a total number of the G3S inverters included therein is a binary value represented by a bit_position of the corresponding bit component of the multi-bit weighting signal; and the 3S groups have different corresponding total numbers of 3S inverters included therein; and for each 3S group, a total number of the 3S inverters included therein is a binary value represented by a bit_position of the corresponding bit_component of the multi-bit weighting signal. 
     In some embodiments, a gated tri-state (G3S) inverter includes: first, second and third PMOS transistors and first, second and third NMOS transistors serially connected between a first reference voltage and second reference voltage; and wherein gate terminals of an alpha one of the first, second and third PMOS transistors and an alpha one of the first, second and third NMOS transistors are configured to receive an input signal of the G3S inverter; gate terminals of a beta one of the first, second and third PMOS transistors and a beta one of the first, second and third NMOS transistors are configured to receive a gating signal of the G3S inverter; and a gate terminal of a gamma one of the first, second and third NMOS transistors is configured to receive an enable signal; and a gate terminal of a gamma one of the first, second and third PMOS transistors is configured to receive an enable_bar signal. 
     In some embodiments, the first PMOS transistor is coupled between the first reference voltage and a first node; the second PMOS transistor is coupled between the first node and a second node; the third PMOS transistor is coupled between the second node and a third node, the third node representing an output of the GS3 inverter; the first NMOS transistor is coupled between the third node and a fourth node; the second NMOS transistor is coupled between the fourth node and a fifth node; and the third NMOS transistor is coupled between the fifth node and the second reference voltage. In some embodiments, the alpha one of the first, second and third PMOS transistors is the first PMOS transistor; the alpha one of the first, second and third NMOS transistors is the third NMOS transistor; the beta one of the first, second and third PMOS transistors is the second PMOS transistor; the beta one of the first, second and third NMOS transistors is the second NMOS transistor; the gamma one of the first, second and third PMOS transistors is the third PMOS transistor; and the gamma one of the first, second and third NMOS transistors is the first PMOS transistor. 
     In some embodiments, a method (of operating a gated tri-state (G3S) inverter) includes: receiving a gating signal, an enable signal and an input signal; when the enable signal has a first logical state, then generating a high impedance at an output of the G3S inverter; and when the enable signal has a second logical state: and also when each of the gating signal and the input signal has a first logical state, then generating a signal at the output of the G3S inverter which has a logical high state; or and also when each of the gating signal and the input signal has a second logical state, then generating a signal at the output of the G3S inverter which has a logical low state. 
     In some embodiments, the method further includes: when the enable signal has the logical high state, and also when the gating signal has the first logical state and the input signal has the second logical state, then generating the high impedance at the output of the G3S inverter. In some embodiments, the G3S inverter includes first, second and third PMOS transistors and first, second and third NMOS transistors serially connected between a first reference voltage and second reference voltage; and the method further includes: coupling the input signal to an alpha one of the first, second and third PMOS transistors and an alpha one of the first, second and third NMOS transistors; coupling the gating signal to gate terminals of a beta one of the first, second and third PMOS transistors and a beta one of the first, second and third NMOS transistors; and coupling the enable signal to a gate terminal of a gamma one of the first, second and third NMOS transistors; and coupling an enable_bar signal to a gate terminal of a gamma one of the first, second and third PMOS transistors. In some embodiments, the alpha one of the first, second and third PMOS transistors is the first PMOS transistor; the alpha one of the first, second and third NMOS transistors is the third NMOS transistor; the beta one of the first, second and third PMOS transistors is the second PMOS transistor; the beta one of the first, second and third NMOS transistors is the second NMOS transistor; the gamma one of the first, second and third PMOS transistors is the third PMOS transistor; and the gamma one of the first, second and third NMOS transistors is the first PMOS transistor. In some embodiments, the G3S inverter includes first, second and third PMOS transistors and first, second and third NMOS transistors serially connected between a first reference voltage and second reference voltage; and the first logical state is a low logical state. 
     It will be readily seen by one of ordinary skill in the art that one or more of the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.