Patent Publication Number: US-2012041706-A1

Title: Testing system for portable electronic device

Description:
BACKGROUND 
     1. Technical field 
     The disclosure generally relates to testing systems, and more particularly to a testing system for portable electronic devices according to test sequence. 
     2. Description of the Related Art 
     In manufacturing, notebooks, mobile phones and other electronic devices require different tests, such as surface pressure tests, communication performance tests, video performance tests, and user interface (UI) performance tests, to obtain various performance indicators. 
     In such tests, computers are typically used to control test equipment to automatically test devices under test (DUT) of the electronic device and obtain different test parameters. However, in practice, test sequences of the DUT are difficult to control and manage, which may cause disordering of transmitting test commands and receiving test results. Thus, it is difficult to confirm the test result corresponding to each test command, which may reduce test efficiency and accuracy. 
     Therefore, there is room for improvement within the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Many aspects of an exemplary portable electronic device testing system can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the exemplary portable electronic device testing system. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment. 
         FIG. 1  is a block diagram of a testing system for a portable electronic device including a sequential control card, a group of switches, a group of test devices, and a main controller, according to an exemplary embodiment. 
         FIG. 2  is a circuit view of the sequential control card, the group of switches and the main controller of the testing system of one embodiment of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a testing system  100  for a portable electronic device  300  including a sequential control card  10 , a group of switches S 0 -S 127 , and a group of test devices K 0 -K 127 , and a main controller  20 , according to an exemplary embodiment. The testing system  100  can be used to test and manage the portable electronic device  300 , such as a mobile phone, or a notebook, according to a predetermined test sequence. 
     Also referring to  FIG. 2 , the sequential control card  10  includes a main control module  12 , a timing selection module  13 , and a group of data transmission modules U 0 -U 15 . The main control module  12  can be an AT89S52 microcontroller and includes a power port (not shown), a group of timing selection ports P 0 . 0 -P 0 . 3 , a group of signal control ports P 1 . 0 -P 1 . 7 , and a signal receiving port RXD. In this exemplary embodiment, the power port of the main control module  12  may be electrically connected to a battery (not shown). 
     The timing selection module  13  can be a DM74LS154N 4-line to 16-line decoder and includes a group of timing signal input ports A 0 -A 3  and a group of timing signal output ports Y 0 -Y 15 . The timing signal input ports A 0 -A 3  are electrically connected to the timing selection ports P 0 . 0 -P 0 . 3 , respectively. In detail, the timing signal input port A 0  is electrically connected to the timing selection port P 0 . 0 , the timing signal input port A 1  is electrically connected to the timing selection port P 1 , and the timing signal input port A 3  is electrically connected to the timing selection port P 0 . 3 . The timing signal input ports A 0 -A 3  receive high voltage signal (e.g., logic 1) or low voltage signal (e.g., logic 0) from the timing selection ports P 0 . 0 -P 0 . 3  to logically and selectably control the level of the output voltage of the timing signal output ports Y 0 -Y 15 . 
     The timing selection ports P 0 . 0 -P 0 . 3  are four logic ports and have sixteen different logic combinations, such as 0000, 0001, 0010 . . . 1110, 1111, corresponding to the timing signal output ports Y 0 -Y 15 . The timing signal input ports A 0 -A 3  receive the logic combinations from the timing selection ports P 0 . 0 -P 0 . 3 , and one corresponding of the timing signal output ports Y 0 -Y 15  outputs a high or a low voltage signal. In detail, for example, when the timing selection ports P 0 . 0 -P 0 . 3  output the logic combination of 0000, the timing signal output port Y 0  then outputs a low voltage signal, the timing signal output ports Y 1 -Y 15  then output high voltage signals. Similarly, when the timing selection ports P 0 . 0 -P 0 . 3  output the logic combination of 0001, the timing signal output port Y 1  outputs a low voltage signal, the timing signal output ports Y 0  and Y 2 -Y 15  output high voltage signals. When the timing selection ports P 0 . 0 -P 0 . 3  output the logic combination of 0011, the timing signal output port Y 3  outputs a low voltage signal, the timing signal output ports Y 0 -Y 2  and Y 4 -Y 15  output high voltage signals. When the timing selection ports P 0 . 0 -P 0 . 3  output the logic combination of 1111, the timing signal output port Y 15  outputs a low voltage signal, the timing signal output ports Y 0 -Y 14  output high voltage signals. 
     Each of the data transmission modules U 0 -U 15  can be a SN74LS245N integrated circuit (IC) and includes a group of data input ports B 0 -B 7 , a group of data output ports C 0 -C 7 , and two enable signal ports OE and DIR. The enable signal ports OE and DIR are low enabled ports. The data input ports B 0 -B 7  of each data transmission module are electrically connected to the signal control ports P 1 . 0 -P 1 . 7 , respectively. The enable signal ports OE and DIR of the data transmission modules U 0 -U 15  are electrically connected to the timing signal output port Y 0 -Y 15 , respectively. In detail, the data input ports B 1  of the data transmission modules U 0 -U 15  are electrically connected to the signal control ports P 1 . 1  of the signal control module  12 , and the enable signal ports OE and DIR of the data transmission module U 1  are electrically connected to the timing signal output port Y 1 . Similarly, the data input ports B 2  of the data transmission modules U 0 -U 15  are electrically connected to the signal control ports P 1 . 2  of the signal control module  12 , and the enable signal ports OE and DIR of the data transmission module U 2  are electrically connected to the timing signal output port Y 2 . 
     In this exemplary embodiment, the data transmission module U 0  is used as an example to illustrate the circuit connections of the data transmission module U 0 , the signal control module  12  and the timing selection module  13 . The data input ports B 0 -B 7  of the data transmission module U 0  are electrically connected to the signal control ports P 1 . 0 -P 1 . 7  of the signal control module  12  respectively, and the enable signal ports OE and DIR are electrically connected to the timing signal output port Y 0  of the timing selection module  13 . In detail, the timing selection ports P 0 . 0 -P 0 . 3  output the logic combination of 0000, the timing signal output port Y 0  then outputs a low voltage signal, the enable signal ports OE and DIR receive the low voltage signal and are enabled, and the data transmission module U 0  is activated. Accordingly, the signal control ports P 1 . 0 -P 1 . 7  provide and output corresponding command signals, such as logic 1, to the data transmission module U 0  through the data input ports B 0 -B 7  and the command signals are transmitted to the switches S 0 -S 7  through the data output ports C 0 -C 7  to activate one of the switches S 0 -S 7 . When the timing signal output port Y 0  outputs a high voltage signal to the enable signal ports OE and DIR, the signal control ports P 1 . 0 -P 1  stop the transmission of the command signals. 
     The switches S 0 -S 127  can be relays. One end of each switch is electrically connected to the data output port of the data transmission modules U 0 -U 15 , and the other end of each switch is electrically connected to one corresponding of the test devices K 0 -K 127 . In detail, the switch S 0  electrically connects the data output port C 0  of the data transmission module U 0  and the test device K 0 . The switch S 9  electrically connects the data output port C 1  of the data transmission module U 1  and the test device K 9 . The switches S 0 -S 127  are activated when receiving high voltage signals. 
     The main controller  20  can be a computer and is electrically connected to the switches S 0 -S 127  through a printed circuit board (PCB), a flexible PCB (FPC), or a switch interface. The main controller  20  includes a signal transmitting port TXD, which is electrically connected to the signal receiving port RXD of the signal control module  12 . The main controller  20  includes different control programs to provide different command signals for the signal control module  12 . 
     Further referring to  FIGS. 1 and 2 , in testing, the test devices K 0 -K 127  are electrically connected to devices under test (DUT) of the portable electronic device  300 , respectively. For example, the test device K 0  is used to test the camera performance and is electrically connected to the camera of the portable electronic device  300 ; the test device K 1  is used to test communication performance and is electrically connected to the antenna of the portable electronic device  300 ; the test device K 2  is used to test the user interface (UI) performance and is electrically connected to the touch panel and the liquid crystal display (LCD) of the portable electronic device  300 . The test devices K 0 -K 127  are then electrically connected to the switches S 0 -S 127  and the switches S 0 -S 127  are electrically connected to the main controller  20  through the FPC or the switch interface. 
     When testing the DUT of the portable electronic device  300  according to predetermined test sequence, the main controller  20  provides and outputs command signals to the signal control module  12  to activate the switches S 0 -S 127  according to the predetermined test sequence. For example, the predetermined priority of K 1  is higher than that of K 0 , and the predetermined priority of K 0  is higher than that of the K 2  according to the test sequence. Thus, the main controller  20  firstly sends a corresponding command signal to the signal control module  12  through the signal transmitting port TXD, the timing selection ports P 0 . 0 -P 0 . 3  output the logic combination of 0001 to the timing signal input ports A 0 -A 3 , the timing signal output port Y 1  outputs a low voltage signal, and the data transmission module U 1  is activated and selected. 
     The main controller  20  then controls the signal control ports P 1 . 0 -P 1 . 7  of the signal control module  12  to output a logic combination of 00000010 to the data input ports B 0 -B 7  of the data transmission module U 1 , so the data output port C 1  outputs a high voltage signal to the switch S 1 , and the switch S 1  is selected and is switched on according to the high voltage signal. Thus, the test device K 1  is activated and controlled to test the corresponding DUT of the portable electronic device  300 . The main controller  20  receives the test result of the DUT of the portable electronic device  300  through the switch S 0  and the sequential control card  10 . 
     According, the main controller  20  sends another command signal to the signal control module  12  according test priority, the timing selection ports P 0 . 0 -P 0 . 3  output the logic combination of 0000 to the timing signal input ports A 0 -A 3 , the timing signal output port Y 0  outputs a low voltage signal, and the data transmission module U 0  is activated and selected. The signal control ports P 1 . 0 -P 1 . 7  of the signal control module  12  outputs a logic combination of 00000001 to the data input ports B 0 -B 7  of the data transmission module U 0 , and the switch S 1  is switched on. Thus, the test device K 0  is activated to test the corresponding DUT of the portable electronic device  300 . 
     Similarly, the timing selection ports P 0 . 0 -P 0 . 3  output the logic combination of 0010 to the timing signal input ports A 0 -A 3 , and the data transmission module U 2  is activated and selected. The signal control ports P 1 . 0 -P 1 . 7  of the signal control module  12  output a logic combination of 00000100 to the data transmission module U 3 , and the switch S 2  is selected and switched on. Thus, the test device K 2  is then activated to test the corresponding DUT of the portable electronic device  300 . 
     In summary, in the testing system for portable electronic device  100  of the exemplary embodiment, the switches S 0 -S 127  are switched on or off under the control of the main controller  20  according to the predetermined test sequence, and the corresponding test devices K 0 -K 127  are activated and controlled to test various performances of the portable electronic device  300  according to the test priority. In addition, the testing system  100  has a simple circuit connection, and can control and conduct a number of performance tests of one or more of the portable electronic device  300  according to the predetermined test sequence, which can improve test efficiency and accuracy. 
     It is to be understood, however, that even though numerous characteristics and advantages of the exemplary disclosure have been set forth in the foregoing description, together with details of the structure and function of the exemplary disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of exemplary disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.