Patent Publication Number: US-11395405-B2

Title: Wiring substrate and electronic device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a national stage entry according to 35 U.S.C. 371 of International Application No. PCT/JP2019/033526 filed on Aug. 27, 2019, which claims priority to Japanese Patent Application No. 2018-159435 filed on Aug. 28, 2018, the contents of which are entirely incorporated herein by reference. 
     TECHNICAL FIELD 
     The present disclosure relates to a wiring substrate and an electronic device. 
     BACKGROUND 
     Heretofore a wiring substrate including an insulating substrate with a wiring line located thereon, an electronic component-mounted electronic device, etc. are known (refer to Japanese Unexamined Patent Publication JP-A 2001-102722, for example). 
     SUMMARY 
     A wiring substrate according to the disclosure includes: an insulating substrate including a principal face; a wiring line located on the principal face; and a protruding portion on a side of the wiring line, the protruding portion being smaller in thickness than the wiring line and protrudes from the side along the principal face. 
     An electronic device according to the disclosure includes: the wiring substrate described above; and an electronic component mounted on the wiring substrate. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a vertical sectional view showing an electronic device according to an embodiment of the disclosure; 
         FIG. 2  is an enlarged view of main parts in Part A shown in  FIG. 1 ; 
         FIG. 3  is an enlarged view of main parts in Part B shown in  FIG. 2 ; 
         FIG. 4  is a main-part enlarged view showing another example of the electronic device according to the embodiment; 
         FIG. 5  is a main-part enlarged view, corresponding to Part A shown in  FIG. 1 , showing still another example of the electronic device according to the embodiment; 
         FIG. 6  is an enlarged view of main parts in Part B shown in  FIG. 5 ; 
         FIG. 7  is a main-part enlarged view showing still another example of the electronic device according to the embodiment; and 
         FIG. 8  is a main-part enlarged view showing still another example of the electronic device according to the embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the disclosure will now be described with reference to the accompanying drawings. 
     Referring to  FIGS. 1 to 8 , an electronic device according to an embodiment of the disclosure will be described. The electronic device according to this embodiment includes: a wiring substrate  1 ; a resistor layer  4 ; and an electronic component  2 . 
     In this embodiment, for example, the wiring substrate  1  includes: an insulating substrate  11  including a principal face  11   a ; and a wiring line (a thin-film wiring line, for instance)  12  located on the principal face  11   a.    
     The insulating substrate  11  may be made of ceramics, e.g. an aluminum oxide sintered body (alumina ceramics), an aluminum nitride sintered body, a mullite sintered body, or a glass ceramics sintered body. 
     In the case where the insulating substrate  11  is made of a resin material, for example, it is possible to use epoxy resin, polyimide resin, acrylic resin, phenol resin, polyester resin, and fluorine resin typified by tetrafluoroethylene resin. 
     For example, if using an aluminum nitride sintered body for the insulating substrate  11 , the insulating substrate  11  is produced by preparing a slurry by admixing suitable organic binder, solvent, etc. in powder of raw materials, including aluminum nitride used as a main component, and yttria, erbia, etc. used as sintering aids; shaping the slurry into a sheet by using, for example, a doctor blade method or a calender roll method to obtain a ceramic green sheet; subjecting the ceramic green sheet to a suitable punching process; stacking a plurality of ceramic green sheets into a green laminate for forming the insulating substrate  11 ; and firing the green laminate at a high temperature (about 1800° C.). Note that aluminum nitride is defined as a main component so long as it is contained in the insulating substrate  11  in an amount of greater than or equal to 80% by mass based on 100% by mass set as the total mass of the insulating substrate  11 . An aluminum nitride content in the insulating substrate  11  may be set at or above 95% by mass. The insulating substrate  11  having an aluminum nitride content of 95% by mass or greater is likely to exhibit a thermal conductivity of 150 W/mK or greater, thus allowing the wiring substrate  1  to deliver good heat dissipation performance. 
     The insulating substrate  11  is intended for the installation of the electronic component  2  such as a semiconductor laser device. As in examples shown in  FIGS. 1 to 8 , the insulating substrate  11  is quadrangular in plan configuration. 
     For example, the wiring line  12  has the form of thin-film wiring line including a plurality of metallic layers located on the principal face  11   a  of the insulating substrate  11 , and more specifically, the wiring line  12  includes: at least one metallic layer selected from an adherent layer  12   ca  and a barrier layer  12   cb  as an inner layer; and a principal conductor layer  12   cc  as an outermost layer. For example, the outermost layer of the wiring line  12 , i.e., the principal conductor layer  12   cc , is formed of a layer of gold, which is a metal that has a hardness of as low as 20 to 50 hv, exhibits low electrical resistance, and excels in electrical conductivity. 
     For example, the wiring line  12  is formed so as to lie on the principal face  11   a  of the insulating substrate  11  by using a thin-film forming technique such as lift-off technique. Moreover, for enhanced adhesion between the insulating substrate and the principal conductor layer  12   cc  constituting the outermost layer of the wiring line  12 , i.e., the gold layer, the adherent layer  12   ca  is disposed as an inner layer between the insulating substrate  11  and the principal conductor layer  12   cc . For example, the adherent layer  12   ca  is formed of a layer of titanium, which is a metal having good adherability. The titanium layer has a hardness of about 140 hv. 
     Moreover, between the principal conductor layer  12   cc  in gold-layer form and the adherent layer  12   ca  in titanium-layer form, there is provided the barrier layer  12   cb  serving as a barrier to restrain gold from spreading to the adherent layer  12   ca  in titanium-layer form. The barrier layer  12   cb  is formed of at least one selected from a platinum layer and a palladium layer. Platinum and palladium are metals that deliver good barrier performance. The platinum layer has a hardness of 50 to 110 hv, and the palladium layer has a hardness of 40 to 110 hv. 
     Moreover, in the wiring line  12 , the adherent layer  12   ca  is set to 0.02 to 0.2 μm in thickness, the barrier layer  12   cb  is set to 0.05 to 0.5 μm in thickness, and the principal conductor layer  12   cc  is set to 0.2 to 5.0 μm in thickness. 
     Following is an example of the method of producing the wiring line  12 . A copper metallic layer is formed on the entire principal face  11   a  of the insulating substrate  11  made of an aluminum nitride sintered body by using a thin-film forming technique such as vapor deposition, ion plating, or sputtering. 
     Next, resist processing is performed to provide a resist for wiring line  12 -pattern formation, and, after a copper plating layer is formed on the copper metallic layer exposed by means of plating or otherwise, the resist is removed. Then, the exposed copper metallic layer is removed by etching to form a lift-off mold for the formation of the wiring line  12 . For example, copper is dissoluble in an ammonium persulfate solution, and hence the use of such a solution permits easy etching of the exposed copper metallic layer. Moreover, if the concentration of dissolved copper in the ammonium persulfate solution is adjusted to 1 to 10 g/L, such a control stabilizes the rate of copper etching, ensuring the formation of a high-precision lift-off mold. 
     After that, the adherent layer  12   ca  in titanium-layer form, the barrier layer  12   cb  which is at least one selected from a platinum layer and a palladium layer, and the principal conductor layer  12   cc  in gold-layer form are formed one after another on the entire surface of the insulating substrate  11  bearing the mold by using a thin-film forming technique such as vapor deposition, ion plating, or sputtering. Then, a lift-off process is performed to remove the mold. The method thus far described permits the formation of the wiring line  12  of predetermined pattern. In the above-described method, metallic particles constituting each layer to be deposited by means of vapor deposition, ion plating, sputtering, or otherwise can be caused to enter at a right angle with respect to the insulating substrate  11  in the interest of higher removability of the mold in the subsequent lift-off process. 
     Moreover, like the wiring line  12 , a wiring conductor other than the wiring line  12  may also be provided so as to lie on the principal face  11   a  of the insulating substrate  11  by using a thin-film forming technique such as the lift-off technique. Other wiring conductor than the wiring line  12  may be formed concurrently with the formation of the wiring line  12 . 
     Moreover, in the making of the wiring substrate  1  of small size, a multi-piece substrate including a matrix of a plurality of insulating substrate  11 -forming regions may be used for ease of handling and efficient production of many wiring substrates  1 . In the above-described case, the plurality of insulating substrate  11 -forming regions are each formed with the wiring line  12  at one time, and then the substrate is cut along the outer edge of each insulating substrate  11 -forming region by slicing operation, for example. This procedure permits efficient formation of the wiring substrate  1  including the wiring line  12  located on the principal face  11   a.    
     As described above, the wiring substrate  1  includes: the insulating substrate  11  including the principal face  11   a ; and the wiring line  12  located on the principal face  11   a , and on a side of the wiring line  12  being provided a protruding portion  12   a  which is smaller in thickness than the wiring line  12 , and protrudes from the side along the principal face  11   a . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and ensuing heat dissipation, etc., which result in a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , the placement of the protruding portion  12   a  of small thickness on the side of the wiring line  12  makes it possible to lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . The protruding portion  12   a  is set to 5 to 100 nm in thickness. 
     Moreover, as in an example shown in  FIG. 1 , the protruding portion  12   a  may be provided on each of the opposed sides of the wiring line  12 . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the opposed sides of the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and ensuing heat dissipation, etc., which result in a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , the placement of the protruding portion  12   a  of small thickness on each of the opposed sides of the wiring line  12  makes it possible to lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, the wiring line  12  includes the adherent layer  12   ca , the barrier layer  12   cb , and the principal conductor layer  12   cc  that are arranged, in multi-layer form, in the order from the principal face  11   a  of the insulating substrate  11 . Moreover, the protruding portion  12   a  contains a part of the principal conductor layer  12   cc . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the side of the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and ensuing heat dissipation, etc., which result in a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , the placement of the protruding portion  12   a  of small thickness, which contains the part of the principal conductor layer  12   cc  in the form of a low-hardness gold layer for example, on the side of the wiring line  12  makes it possible to further lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, if the protruding portion  12   a  is made smaller in thickness than the adherent layer  12   ca , for example, in the case where the resistor layer  4  is disposed on the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and ensuing heat dissipation, etc., which result in a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , the placement of the protruding portion  12   a , which is smaller in thickness than the adherent layer  12   ca , on the side of the wiring line  12  makes it possible to further lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, as in examples shown in  FIGS. 4 to 8 , if the protruding portion  12   a  contains a part of the barrier layer  12   cb  located between the part of the principal conductor layer  12   cc  of the protruding portion  12   a  and the principal face  11   a  of the insulating substrate  11 , for example, in the case where the resistor layer  4  is disposed on the side of the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., the principal conductor layer  12   cc  of the protruding portion  12   a , in the form of a gold layer for example, is less prone to being diffused toward the insulating substrate  11 , and the part of the principal conductor layer  12   cc  is thus contained in the protruding portion  12   a . Furthermore, even if a difference in thermal shrinkage arises between the wiring line  12  and the insulating substrate  11  due to heat dissipation that ensued, etc., the placement of the protruding portion  12   a  of small thickness, which contains the part of the principal conductor layer  12   cc , on the side of the wiring line  12  makes it possible to further lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, as in the examples shown in  FIGS. 4 to 8 , if the protruding portion  12   a  contains a part of the adherent layer  12   ca  located between the barrier layer  12   cb  of the protruding portion  12   a  and the principal face  11   a  of the insulating substrate  11 , for example, in the case where the resistor layer  4  is disposed on the side of the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and also, even with a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11  caused by heat dissipation that ensued, etc., the placement of the protruding portion  12   a  of small thickness on the principal face  11   a  of the insulating substrate  11 , as well as the placement of the protruding portion  12   a  of small thickness, which contains the part of the principal conductor layer  12   cc  in the form of a low-hardness gold layer for example, on the side of the wiring line  12 , makes it possible to further lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, in a vertical sectional view, a part of the principal conductor layer  12   cc  is located on the side of the barrier layer  12   cb . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and ensuing heat dissipation, etc., which result in a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , the placement of the principal conductor layer  12   cc , in the form of a low-hardness gold layer for example, on the side of the barrier layer  12   cb  makes it possible to further lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, as in the examples shown in  FIGS. 4 to 8 , in a vertical sectional view, a part of the barrier layer  12   cb  and a part of the principal conductor layer  12   cc  are arranged on the side of the adherent layer  12   ca  and are arranged in that order from the side of the adherent layer  12   ca . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the side of the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., the placement of the principal conductor layer  12   cc  in the form of, for example, a low-hardness gold layer at the side of the adherent layer  12   ca  makes it possible to further lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, a part of the principal conductor layer  12   cc  continuously extends along the side of the wiring line  12  and further along the protruding portion  12   a . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and ensuing heat dissipation, etc., which result in a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , the placement of the principal conductor layer  12   cc  in the form of, for example, a low-hardness gold layer at and around the boundary between the wiring line  12  and the insulating substrate  11  makes it possible to effectively lessen a stress resulting from the difference in thermal shrinkage between the wiring line and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, a part of the barrier layer  12   cb  continuously extends along the side of the wiring line  12  and further along the protruding portion  12   a . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the side of the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., in the range from the side of the wiring line  12  to the protruding portion  12   a , the principal conductor layer  12   cc  of the protruding portion  12   a , in the form of a gold layer for example, is less prone to being diffused over the adherent layer  12   ca  toward the insulating substrate  11 . Furthermore, even if a difference in thermal shrinkage arises between the wiring line  12  and the insulating substrate  11  due to heat dissipation that ensued, etc., the placement of the principal conductor layer  12   cc  extending along the side of the wiring line  12  and further along the protruding portion  12   a  makes it possible to effectively lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, a part of the adherent layer  12   ca  continuously extends along the side of the wiring line  12  and further along the protruding portion  12   a . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the side of the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and also, even with a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11  caused by heat dissipation that ensued, etc., the placement of the principal conductor layer  12   cc  extending along the side of the wiring line  12  and further along the protruding portion  12   a  makes it possible to effectively lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, as in an example shown in  FIG. 8 , if the protruding portion  12   a  is configured so that a thickness thereof becomes smaller gradually from one end located toward the side of the wiring line  12  to the other opposite end, for example, in the case where the resistor layer  4  is disposed on the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and ensuing heat dissipation, etc., which result in a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , the described configuration of the protruding portion  12   a  makes it possible to minimize the concentration of a stress, which results from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , on the boundary between the wiring line  12  and the insulating substrate  11 , and thereby reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     Moreover, as in examples shown in  FIGS. 5 to 8 , the wiring line  12  may include at the side, an inclined portion  12   b  inclined toward the protruding portion  12   a , and the inclined portion  12   b  may be connected to the protruding portion  12   a . With the above-described design, for example, in the case where the resistor layer  4  is disposed on the wiring line  12 , even with the transmission of external heat or the application of heat liberated from the resistor layer  4  and the wiring line  12  during operation of the electronic device, etc., and ensuing heat dissipation, etc., which result in a difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , the placement of the inclined portion  12   b  inclined toward the protruding portion  12   a , which allows the resistor layer  4  to have an obtuse-angled bend, as well as the placement of the inclined portion  12   b  inclined toward the protruding portion  12   a  and the protruding portion  12   a  of small thickness connected to the inclined portion  12   b , makes it possible to effectively lessen a stress resulting from the difference in thermal shrinkage between the wiring line  12  and the insulating substrate  11 , and thereby further reduce the occurrence of a break in the resistor layer  4  at the boundary between the wiring line  12  and the insulating substrate  11  in the resistor layer  4 . 
     The electronic device is produced by mounting the electronic component  2  such as a semiconductor laser device on the wiring substrate  1  provided with the resistor layer  4  located on the wiring line  12 . In the case where the electronic component  2  is of the type to be mounted by wire bonding, the electronic component  2  is secured onto a wiring conductor via a joining material such as solder first, and is then electrically connected at an electrode thereof to the wiring line  12 , etc. via a connecting member  3  such as a bonding wire. The electronic component  2  is thus mounted on the wiring substrate  1 . 
     The disclosure is not limited to the described embodiments, and hence various changes and modifications may be made therein. For example, although the insulating substrate  11  is illustrated as being quadrangular in plan configuration, it may be circular in plan configuration instead. Moreover, a plurality of electronic components  2  may be mounted on the wiring substrate  1 .