Patent Publication Number: US-5257039-A

Title: Non-impact printhead and driver circuit for use therewith

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to driver circuitry for driving recording elements for non-impact printing and more particularly relates to driver circuitry for driving light-emitting diodes (LEDs) on a printhead with improved compensation for nonuniformities in light outputs arising from temperature differences on the printhead. 
     2. Description of the Prior Art 
     In the prior art, as exemplified by U.S. Pat. No. 4,885,597, the contents of which are incorporated herein by this reference, an LED printhead is described for recording by modifying an electrostatic charge on a photoconductive web. LED printheads, as known in the art, include a single row of LEDs formed in chip arrays. Each array may contain say 192 LEDs. As may be seen from FIG. 1, the arrays 31 are mounted end to end on the printhead 20 so that a single row of several thousand LEDs 30 is provided. Driver chips 40 may be mounted on one or both sides of this row of LEDs and these chips incorporate the circuitry for handling the data signals to determine which LEDs are to be turned on or illuminated during a pixel (picture element) recording period and for providing the driving currents to the LEDs turned on. In one typical application, two driver chips incorporate the circuitry for driving the 192 LEDs on a chip array. One of these driver chips will be used to drive the 96 odd-numbered LEDs and the other will be used to drive the  96 even-numbered LEDs. Signal carrying lines 33, 34, 35, 36 and 37 are provided to carry signals from a logic control unit and power supply to control operation of the printhead. 
     As noted in this patent, temperature gradients appear along the length of the printheads. The LEDs are temperature-sensitive and their respective light outputs for the same amount of driving currents are adversely affected. Thus, illumination uniformity suffers and concomitant image deterioration results. To offset this, the referenced patent teaches the use of modifying the driver currents respectively in accordance with temperature measured close to the driver chips to compensate for the change in light output due to the LEDs rise in temperature. In accordance with the circuit described in this referenced patent, a digitally addressable current regulation circuit is provided on each driver chip. This circuit drives the LEDs through a current mirror with the currents through the LEDs being slaved to that in the master circuit. The current in the master circuit is regulated with a digital word stored on the driver chip. This digital word is changed periodically with changes of temperature, thereby causing change in the level of current in the master circuit, and concomitantly, in the level of current to the LEDs. This approach works well when temperature changes are relatively slow so that infrequent changes to the digital word may be made. However, where exacting image reproduction is desired, the circuit described in this patent presents some problems. In order to change the digital word more frequently, communication with say a logic controller must be had requiring lines and attachment connections. Additional lines and connections to a printhead use up precious &#34;real estate&#34; on the printhead. To minimize the use of this real estate, it has been proposed in U.S. application Ser. No. 07/543,929, filed Jun. 26 1990 in the names of Potucek et al to employ data lines for passing image data signals to the printhead for also passing digital current regulation data. While this approach alone saves &#34;real estate&#34;, the passing of current regulation data may be required only during interframes for recording or other nonproduction intervals. While an embodiment disclosed in the Potucek et al application describes a circuit for accomplishing line by line changes to both image data and current regulation data, such circuit may require a higher speed clocking capability than desired. The Potucek et al application also overcomes the problem of temperature-related changes in LED uniformity by providing a circuit including a resistor having a positive temperature coefficient in combination with a bipolar transistor. Incorporating such a resistor on a so-called V T  (thermal voltage) reference source provides a current that increases with temperature. This current is then used as a reference for generating the master current in the driver circuit for driving the LEDs. Thus, as temperature of the driver chip increases, and concomitantly its adjacent LED array, the current to the LEDs increase to offset reduction in efficiency due to temperature. 
     A problem with the above approach is providing a reference current that increases linearly with temperature. Such an increase is desirable since it provides a reasonably satisfactory approximation of the requirements of the LEDs for maintaining uniformity of light output. A further problem is that it would be desirable to provide such a reference current source that has a temperature coefficient that is programmable to provide further flexibility in allowing adjustments to be made to best approximate the behavior of the LEDs. For example, LEDs produced from different batches may exhibit uniformity fall-off at different rates. A circuit that can be programmed to offset this fall-off with good approximation would be highly desirable. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide an improved printhead and circuit for a driver chip for use in overcoming the problems set forth above. These and other objects which will become apparent are realized in accordance with one aspect of the invention by a printhead including a recording element energizable for emitting radiation used in recording; and driver circuitry for providing driving current to energize the recording element, the driver circuitry including a plurality of MOS transistors arranged in a cascode current mirror configuration and biased in the weak-inversion saturated region to generate a driving current with a generally linear temperature profile. 
     In accordance with another aspect of the invention, there is provided a printhead comprising: a plurality of recording elements energizable for emitting radiation used in recording; and driver circuitry means including a plurality of master-slave current mirrors for generating driving currents to energize respective recording elements, each recording element being a part of a slave leg of each current mirror and each master circuit being associated with only one recording element. 
     In accordance with yet another aspect of the invention, there is provided a printhead comprising: a recording element energizable for emitting radiation used in recording, and driver circuitry for providing driving current to energize the recording element; the driver circuitry including a digital-to-analog converter for modifying a level of current to the recording element, the converter including a plurality of unit transistors arranged in a common centroid configuration, wherein the unit transistors of the converter are connected in groups to form binary weighted transistor groups, and wherein binary weighted groups of progressively higher binary weight are located progressively farther from the centroid. 
     In accordance with other aspects of the invention, there is provided driver circuitry as described above. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic in block diagram form of a printhead in accordance with the prior art; 
     FIG. 2 is a schematic in block diagram form of a portion of a circuit used in a driver chip to which the invention pertains and which driver chip may be used on a printhead of the type illustrated in FIG. 1; 
     FIGS. 3A through 3G are a schematic of the portion of the driver chip shown in FIG. 2; 
     FIGS. 4A, 4B is a chart of the width to length parameters in microns of the transistors illustrated in FIGS. 3A through 3G; and 
     FIG. 5 is a schematic illustrating a layout of a portion of a digital-to-analog converter showing transistors arranged as groups of unit transistors in a common centroid configuration. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the description below, details are provided regarding one or more exemplary embodiments forming the present invention. Apparatus and/or circuitry not specifically shown or described herein are selectable from those known in the prior art. 
     With reference to FIG. 2, a block diagram of a portion of an integrated circuit driver chip 10 that serves to control current to each of 96 LEDs served by that driver chip is illustrated. As noted above, also associated with such driver chip are image data handling circuitry for controlling the pulse durations of pixel recording periods. Circuitry for control of data is described in aforementioned U.S. Pat. No. 4,885,597 and aforementioned U.S. application Ser. No. 07/543,929. Circuitry for controlling pulse duration in a grey level printer is further described in U.S. Pat. No. 4,750,010 to Ayers et al and in U.S. application Ser. No. 07/290,002 filed in the names of Pham et al, the contents of which are also incorporated by this reference. 
     As noted above, the portion of such a driver circuit to which the invention pertains is that for controlling the amount of driving current to each of the LEDs once the LEDs have been switched on by logic circuitry controlled by the data handling circuit portions of the driver chip. The integrated circuit driver chip 10 illustrated can be divided into five functional building blocks, circuits Y1 through Y5, which cooperate to supply the desired forward currents (for example, 2 mA to 11 mA) to LEDs, DL1 through DL96, to generate proper operating electroluminescence. A special portion of the circuit Y4 is so designed as to respond directly to temperature changes in conformance with a desired thermal profile, while the rest of the system circuits function with negligible temperature coefficients. In the present embodiment, which employs silicon CMOS technology, a current is generated in circuit Y4 which varies linearly with temperature. The desired temperature dependency is achieved by a deliberate choice of circuit topology, wherein transistors are specially sized and biased so that operation in the weak-inversion (or subthreshold) region is achieved. This temperature dependency is then faithfully propagated throughout the remainder of the LED printhead driver system by the action of cascoded current mirrors. This temperature sensitive portion of the circuitry functions in a different manner from a conventional, localized temperature sensor, in that it is spatially distributed over an extended area of approximately 0.84 mm by 0.25 mm, and that the thermal current generated by it is directly amplified to produce the LED drive currents without the deployment of any intermediate feedback circuitry. In other words, the change in current with respect to temperature is automatic and requires no external sensors. 
     Unless otherwise stated, each transistor described in these circuits is biased to operate in the above-threshold saturation region, in which the following relationship is valid: 
     
         0&lt;V.sub.GS -V.sub.T &lt;V.sub.DS                              (Eqn. 1.1) 
    
     where V GS , V T  and V DS  are the gate-to-source voltage, the threshold voltage, and the drain-to-source voltage of the transistor, respectively. First order approximation of the transfer characteristics of a MOSFET in the saturation region can be expressed by the following known model in which the drain-to-source current is described as a parabolic function of the gate-to-source voltage modulated by the drain-to-source voltage, namely: 
     
         I.sub.DS =μ.sub.0 C.sub.ox (W/L)(V.sub.GS -V.sub.T).sup.2 (1+λV.sub.DS)                                      (Eqn 1.2) 
    
     where 
     μ 0  is the surface mobility of the channel for the transistor 
     C OX  is the gate oxide capacitance per unit area 
     W/L is the effective channel width-to-length ratio and 
     λ is the channel length modulation parameter. 
     The following paragraphs provide a brief summary of the function and operation of each of the functional block circuits. 
     With reference to FIG. 3A, circuit Y5 serves as a programmable constant current source made up of a bootstrap (self-biasing) current reference circuit feeding into an 8-bit, multiplying digital-to-analog converter, DAC, (DA8Y). An externally supplied 8-bit digital word, H[0:7], regulates the output current I 5  &#39; that is mirrored to circuit Y4 (FIG. 3B) and, along with another externally supplied digital word, S[0:3], is responsible for controlling the temperature coefficient of the current I 4  which is generated in circuit Y4 (FIG. 3B) and varies linearly with temperature. The 4-bit input word S[0:3] can be either preloaded by the logic and control unit with a fixed value by means of signal LOAD or set in the field by means of signal CLK. The temperature coefficient may be digitally varied from 0.3% to 1% per degree Celsius. 
     The magnitude of the output current from circuit Y4, is subsequently amplified by circuits Y3 (FIG. 3C) and Y2 (FIG. 3D), both of which are fully cascoded, 8-bit current steering, multiplying DACs. An externally supplied 8-bit digital word, G[0:7], intended for global control, is used to set the same nominal current for all the printhead driver chips, each of which consists of 96 current driver channels; while another externally supplied 8-bit digital word, F[0:7], intended for fine control, is used to adjust the LED currents on each individual driver chip so that uniformity in LED luminescence can be attained throughout the entire printhead. The combined application of G[0:7] and F[0:7] results in an effective 16-bit resolution of LED drive current adjustment capability. In this regard, reference to U.S. Pat. No. 4,885,597 is made. All the 8-bit DACs used in circuits Y2, Y3 and Y5 are constructed such that all the current mirroring devices responding to each input data bit are laid out in respective exact multiples of a unit cell transistor and arranged in a common centroid configuration. As a consequence of this strategic segmentation and placement of critical transistors, the transfer characteristics of each of the 8-bit DACs is highly linear. The combination of this layout technique along with the fully cascoded current-mirror circuit topology allows the temperature profile obtained in circuit Y4 to faithfully propagate throughout the ensuing stages of the printhead driver system. 
     Circuit Y1 (FIG. 3E) is a high-impedance, linear current amplifier/driver that boosts the output current I 1  generated from circuit Y2 (which falls within the range up to about 200 microamperes) to that required for normal LED electroluminescence operation (which is typically on the order of a few milliamperes). The light output from the xth LED is switched by bit Px, where x=1, . . . , 96 in accordance with a scheme using pulsewidth modulation to provide gray-scale printing operation in accordance with techniques more fully described in the prior art noted above. In this circuit, a separate power supply, V LED , is used to minimize noise emanating from the switching of the LEDs. The use of the cascoded current mirror configuration provides very high insensitivity to power supply fluctuations, significant reduction in silicon die real-estate, extended region of linear current amplification operation, and excellent current regulation in response to wide excursions of LED loading conditions. 
     Thermal Offset Current Adjust Circuit (Circuit Y5) 
     FIG. 3A shows the schematic diagram of the thermal offset current adjust circuit Y5. Its function is to provide a current, I 5  &#39;, to be mirrored to the following linear thermal current source circuit Y4 for effecting the adjustability of the latter&#39;s output current temperature coefficient. This is achieved by means of subcircuit DA8Y5, an 8-bit current-steering multiplying digital-to-analog converter (DAC) which multiplies a digital word, H[0:7], with an input current, I 10 , that is reflected from a preceding bootstrap current reference subcircuit to yield an output current, I 5 . Circuit DA8Y5, as described in further detail below, is designed to operate with an input current range centering around 5 μA and an output current range also centering around 5 μA when the digital word input H[0:7] is set to midrange, i.e., 80(hex). Transistors MO1 through MO4 form a current-matching buffer for interfacing DA8Y5 with the following stage Y4. All the transistors in this circuit are biased to operate in the saturation region. Detailed discussion of the operation of the circuit is described in the following paragraphs. 
     Transistors MJ1 and MJ2 are the cascoded master current-mirror pair driving the DAC subcircuit DA8Y5. These two transistors in conjunction with transistors MI1, MI2, MJ4 and MI4, and resistor R J  are connected in a negative feedback configuration, in which node NT is caused to equilibrate at a voltage value, V NT . Accordingly, a stable current of value I 10  of about 27 μA is generated where R J  =50K ohms and MI4 is a n-channel MOSFET fabricated with a 1.6 μm N-well CMOS double-metal, single-poly process with a gatewidth-to-length ratio of 2. 
     The digitally-controlled output current from sub-circuit DA8Y5 is reflected to the slave cascoded current-mirror pair transistors MO1 and MO2 to yield the output current I 5  &#39;. It may be noted that each pair of cascoded transistors described herein have their respective gate electrodes coupled to the gates of corresponding transistors of another cascode pair to which they are connected in a current mirror relationship. I 5  &#39; is in turn mirrored to the following linear thermal current source circuit Y4 by means of diode-connected transistors MO3 and MO4 through the voltages developed at nodes DT1 and DT2. As a result, I 5  &#39; and I 5  (FIG. 3B) are linearly proportional to I 10  with the proportionality constant being determined by the input digital word H[0:7]. Mathematically: ##EQU1## where H k  is the digital weight of the input word H[0:7]. The current I 5  &#39; is the same level as that of I 5  but this 1:1 mirrored relationship is not critical. 
     Linear Thermal Current Source Circuit Y4 With Programmable Temperature Coefficient 
     FIG. 3B shows the schematic diagram of the Linear Thermal Current Source Circuit Y4 with programmable temperature coefficient control capability. Its function is to generate a variable output current, I 4 , that exhibits a linearly (straight line) increasing dependency on temperature, upon which the thermal characteristics of the entire analog driver system is derived. The desired temperature dependency is achieved by biasing and sizing a portion of the circuit in the weak-inversion (or subthreshold) saturated region, and this dependency then propagates throughout the rest of the printhead driver circuit by the action of the current mirrors. The temperature derivative of the output current, dI 4  /dT, is determined by means of the Temperature Slope Adjust Circuit, Y4P, while the temperature coefficient, defined as: ##EQU2## referenced to temperature T 0  can be adjusted by varying an offset current, I 5 , which is mirrored from the preceding Thermal Offset Current Adjust Circuit Y5. The output current I 4  is subsequently amplified through three following stages: an eight-bit Global-Adjust Current Control Circuit, Y3, an eight-Bit Fine-Adjust Current Control Circuit, Y2, and finally a Linear Cascoded LED Current Amplifier/Driver Circuit, Y1, to provide optimal drive currents for 96 channels of LEDs in each printhead driver chip. Detailed discussion of the operation of the circuit Y4 is described in the following paragraphs. 
     The characteristic temperature dependency of the driver chip is principally derived from the major subcircuit comprising transistors M1, M1B, M2, M2B, M3, M3B, M4, and M4B in conjunction with resistor R B  and subcircuit Y4P. All the transistors in this major subcircuit are designed to operate in the subthreshold saturation region such that the conditions: 
     
         V.sub.G -V.sub.S &lt;V.sub.T                                  (Eqn. 2.1) 
    
     
         and 
    
     
         |V.sub.D -V.sub.S |&gt;3U.sub.T             (Eqn. 2.2) 
    
     are valid, and the MOSFET transfer characteristics follow the exponential relationship: 
     
         I.sub.D ≅(W/L)I.sub.0 exp {V.sub.G /ηU.sub.T }exp {V.sub.S /U.sub.T }                                                (Eqn. 2.3) 
    
     where 
     I D  is the drain current; 
     V G  is the gate-to-substrate voltage; 
     V S  is the source-to-substrate voltage; 
     V D  is the drain-to-substrate voltage; 
     V T  is the threshold voltage; 
     W/L is the width-to-length ratio of the transistor; 
     I 0  is a process-dependent parameter (in Amperes); 
     η is the slope parameter for the weak inversion region (typically 1.4-1.8); 
     U T  is the thermal voltage (=kT/q); 
     k is Boltzmann&#39;s constant; 
     T is the absolute temperature, in °K. (degrees Kelvin); and 
     q is the electronic charge. 
     The components in the major subcircuit are connected in a negative feedback configuration (as shown in FIG. 3B), which cause the node NT to stabilize toward the voltage ##EQU3## is a constant dependent only on the sizings of the transistors. 
     If R T  represents the sum of R B  and the resistance value R P  generated by the Temperature Slope Adjust Circuit, Y4P, then the current I 9  flowing through R T  is given by: 
     
         V.sub.R /R.sub.T =U.sub.T γ/R.sub.T 
    
     which can be rewritten to expressly indicate the temperature dependency as follows: 
     
         I.sub.9 =αT/R.sub.T 
    
     where α is a temperature independent constant: 
     
         α=kγ/q                                         (Eqn. 2.4) 
    
     The temperature coefficient of I 9 , θ 9 , referenced to temperature T 0  is then given by: ##EQU4## Substituting Eqn. 2.4 into the above equation, and noting that both η and γ have negligible temperature dependencies on T, Eqn. 2.5 can be evaluated to yield: ##EQU5## Now, resistance can be modeled to first order as: 
     
         R.sub.T =R.sub.T0 {1+κ(T-T.sub.o)}                   Eqn. 2.7 
    
     where κ is the temperature coefficient of the resistance R T  in units of %/°K. (or, equivalently, °C.), and R T0  is the resistance value at temperature, T 0 . 
     By virtue of Eqn. 2.7, the expression for the temperature coefficient of I 9  from Eqn. 2.6 can be simplified to give: 
     
         θ.sub.9 =1/T.sub.0 -κ 
    
     At T 0  =300° K., 1/T 0  ˜0.33%/°K. For polysilicon resistors, κ is approximately 0.08%/°K. This gives the temperature coefficient of I 9  to be approximately 0.25%/°K. The following paragraphs describe how a variable temperature coefficient can be obtained by means of additional circuitry. 
     The thermally dependent current I 9  from the master cascoded transistor pairs M4 and M4B is mirrored to the slave cascoded transistor pairs M14 and M14B to give current I 8 . As indicated above, all of the transistors in the above-mentioned major subcircuit operate in the subthreshold saturation region, whose transfer characteristics are governed by Eqn. 2.1, Eqn. 2.2 and Eqn. 2.3. Operation is converted back to the normal (above-threshold) saturation region, as described in Eqn. 1.1 and Eqn. 1.2, by the appropriate sizing of transistors M13 and M13B. After two subsequent cascoded current mirror actions employing one set of transistors consisting of M13, M13B, M23, and M23B, and another set consisting of M24, M24B, M34, and M34B, all operating in the normal saturation region, a resultant current, I 6 , flowing through transistors M34 and M34B is obtained. Since the action of current mirroring is essentially a multiplicative process, I 6  is by corollary also a linear function of temperature and can, therefore, be given by: 
     
         I.sub.6 =βT/R.sub.T 
    
     where β is a temperature independent parameter: ##EQU6## 
     It can be shown that the temperature contribution from transistors operating in the cascoded current-mirror configuration is negligible. Thus, the temperature derivative of I 6  can be similarly given as: 
     
         I.sub.6 =I.sub.60 [1+θ.sub.6 (T-T.sub.0)],           Eqn. 2.8 
    
     with its temperature coefficient defined as: ##EQU7## where I 60  is the value of I 6  at reference temperature, T 0 , namely: ##EQU8## For κ=0.08%/°K., it can be readily calculated that θ 6  ≈0.25%/°K. at T 0  =300° K., same as for θ 9 . 
     A branch consisting of transistors M43 and M43B is inserted into the circuit so that the offset current I 5  is subtracted from I 6  to yield the output current I 4  flowing through transistors M33 and M33B. I 5  is mirrored from the preceding Thermal Offset Current Adjust Circuit Y5 (FIG. 3A) through the voltages developed at nodes DT1 and DT2. Hence, the output current I 4  can be written as: 
     
         I.sub.4 =I.sub.6 -I.sub.5 =βT/R.sub.T -I.sub.5. 
    
     Substituting Eqn. 2.8 for I 6  and for I 5 , I 5  =I 50  [1+θ 5  (T-T 0 )], which equation approximates the thermal behavior of I 5  to first order and where I 50  is the value of I 5  at T and θ 5  is the temperature coefficient of I 5  with respect to reference temperature T 0  or: ##EQU9## and thus yields I 4  =I 40  [1+θ 4  (T-T 0 )] where I 40  is the value of I 4  at temperature T 0  : I 40  =I 60  -I 50 , and θ 4  is the temperature coefficient of I 4  : ##EQU10## which explicitly shows the deviation of the value of the temperature coefficient of I 4  from θ 6  as a consequence of introducing the offset current I 5 , and where use has been made of the fact that θ 5  &lt;0. It is evident from this equation that θ 4  can attain values larger than θ 6  by ensuring that I 50  &lt;I 60 . In a preferred embodiment, θ 6  ≈0.25%/°K and |θ 5  |≈0.1%/°K. In this case, one obtains, numerically, ##EQU11## If the offset current from circuit Y5 is programmed so that I 60  =2I 50 , then one obtains the value of θ 4  ≈0.6%/°K. 
     The temperature coefficient for I 4  can also be shown as: ##EQU12## where Γ 0  =L/(μ n  C ox  WR JO  V T ). where 
     V T  is the threshold voltage of transistor MI4; 
     W/L is the channel width-to-length ratio of transistor MI4; 
     μ n  is the n-channel electron surface mobility; and 
     C ox  is the gate oxide capacitance per unit area. 
     Note that the quantity, ##EQU13## is the temperature coefficient of resistor R T . 
     In summary, circuit Y4 produces an output current, I 4 , which increases linearly, i.e., along a straight line, with temperature, and whose temperature coefficient can be adjusted by varying R T0  and I 50 . In practice, R T0  is chosen to be in such a range that allows transistors M1 through M4B to stay within the subthreshold saturation region, and I 50  is then restricted to vary in value so that: 
     
         I.sub.50 &lt;βT.sub.0 /R.sub.T0 =I.sub.60. 
    
     Temperature Slope Adjust Circuit Y4P 
     The schematic diagram of the Temperature Slope Adjust subcircuit Y4P is shown in FIG. 3F. This circuit serves as a four-bit digital potentiometer for the purpose of providing a variable resistance, R T , the function of which is to adjust the thermal current I 9  for optimal operation of the parent Linear Thermal Current Source Circuit Y4. As shown above, the relationship between I 9  and R T  is given by: 
     
         I.sub.9 =αT/R.sub.T =αT/(R.sub.B +R.sub.P).    Eqn. 3.0 
    
     R T  consists of two components: a fixed component, R B , and a variable component, R P . Both R B  and R P  may be implemented using polysilicon. Tunability of R T  is highly desirable because precision resistance values using polysilicon cannot be readily achieved using currently available CMOS processes due to limitations in impurities-doping and photolithographic controls resulting in process variations over different wafer runs. The variable component of the resistance R P  appearing between terminals NU and ND is determined by an externally supplied digital word, S[0:3], from the logic and control unit, and is so selected that transistors M1 through M4B operate well within the subthreshold saturation region, where the above expression for the temperature dependency is valid. Detailed discussion of the operation for the circuit is described in the following paragraphs. 
     The four-bit potentiometer represented by subcircuit Y4P is made up of a resistor chain consisting of sixteen serially connected identical resistor segments, R a , and terminating at nodes NU and ND. A 4-to-16 decoder, U2, is then used to select which one, and only one, of the 16 segments of the chain is to be shorted to node ND via by-pass transistors MRO through MR15. An externally supplied, four-bit digital word, S[0:3], can either be preloaded to latch U1 upon power-up by setting the e,ovs/load/  input signal low or clocked in at any specific time at the falling edge of the CLK signal. 
     From the schematic shown in FIG. 3F, it is straight forward to see that: 
     
         R.sub.P =nR.sub.a,                                         (Eqn. 3.1) 
    
     when by-pass transistor MRn (n=1, . . . , 15) is activated by the output of the decoder U2. All the by-pass transistors are sized such that their on-resistances are very small compared to R a . Meanwhile, the combined transfer characteristics of latch U1 and decoder U2 can be expressed as: ##EQU14## where n is the output channel index from U2, and S i  is the binary weight of the input word S[0:3]. 
     By combining Eqn. 3.1 and Eqn. 3.2, the variable resistance component, R P  can be expressed by the following equation, appropriate for a four-bit digital potentiometer: ##EQU15## Substituting Eqn. 3.3 into Eqn. 3.0, the thermal current I 9  assumes the form: ##EQU16## Typical currents when S[0:3] is set to 3 (decimal) are I 9  ≈0.7 μA, and I 4  ≈1.8 μA. 
     Eight Bit Global-Adjust Current Control Circuit Y3 
     FIG. 3C shows the schematic diagram of the Eight-Bit Global-Adjust Current Control Circuit Y3. It is, functionally speaking, a current-controlled current-source with digitally programmable gain. Its purpose is to provide a variable output current, I 2&#39; , that is mirrored to the following Eight-Bit Fine-Adjust Current Control Circuit Y2. With this current, circuit Y2 generates a fine-adjust control current, I 1 , which is subsequently fed into the following Liner Cascoded LED Current Amplifier/Driver Circuit Y1 to be described below. This function is achieved by means of an Eight-Bit Current-Steering Multiplying Digital-to-Analog Converter subcircuit, DA8Y3, which multiplies an input current, I 3 , obtained by mirroring the output thermal current I 4  of the preceding Linear Thermal Current Source Circuit Y4 with an externally supplied eight-bit digital word, G[0:7], to produce a global-adjust control current, I 2 . Detailed operation of circuit DA8Y is described below. The value of G[0:7] is set to be the same for all the printhead driver chips, each of which consists of 96 channels of LEDs. The purpose of G[0:7] is to place each driver chip in the same nominal operation condition. Transistors MI1 through MI4 together form a current-matching buffer for interfacing DA8Y3 with the preceding stage Y4; while transistors MO1 through MO4 form the counterpart for interfacing DA8Y3 with the following stage Y2. Detailed discussion of the operation of the circuit is described in the following paragraphs. 
     Transistors MI1 and MI2 determine the value of the input current I 3  in response to the gate voltages developed at nodes TD1 and TD2 by the action of cascoded current-mirroring with the preceding stage Y4. I 3  is then used to drive the inputs of circuit DA8Y3 by means of the master cascoded current-mirror input pair MI3 and MI4. The resultant digitally-controlled output current from circuit DA8Y3 is reflected to the slave cascoded current-mirror transistors MO3 and MO4 to produce the output current I 2  &#39;. This global-adjust control current I 2  &#39; is in turn mirrored to the following Eight-Bit Fine-Adjust Current Control Circuit Y2 by means of diode-connected transistors MO1 and MO2 through the voltages developed at nodes DD1 and DD2. Accordingly, I 2  &#39; is linearly proportional to I 3  by virtue of current-mirror action, with the proportionality constant being determined by the externally supplied digital word G[0:7]. The result can be summarized mathematically as follows: ##EQU17## where G j  is the digital weight of the input word G[0:7]. 
     In accordance with the transistor sizing information given in FIGS. 4A, 4B, I 3  may be maintained at 5 μA and with the digital word set at mid-range, i.e., G[0:7]=128 (decimal), the output current I 2  &#39; is the same as the input current I 3  =5 μA. 
     Eight-Bit Fine-Adjust Current Control Circuit Y2 
     FIG. 3D shows the schematic diagram of the Eight-Bit Fine-Adjust Current Control Circuit. It is, functionally speaking, a current-controlled current-source with digitally programmable gain. Its purpose is to provide a variable output current, I 1 , that is mirrored to the following Linear Cascoded LED Current Amplifier/Driver Circuit Y1 to accurately control the drive currents I Lx  (x=1, . . ., 96) for the 96 LED current driver channels on board each printhead driver chip, as will be discussed below. This function is achieved by means of an Eight-Bit Current-Steering Multiplying Digital-to-Analog Converter subcircuit, DA8Y2, which multiplies an input global-adjust control current, I 2 , derived by the preceding Eight-Bit Global-Adjust Current Control Circuit Y3 with an externally supplied from the logic and control unit eight-bit digital word, F[0:7], to produce a fine-adjust control current, I 1 . Detailed operation of circuit DA8Y2 will be described below. In contrast to that of G[0:7] as discussed above, the value of F[0:7] typically varies for each individual printhead driver chip in order to compensate for fabrication process variations. While the action of G[ 0:7] is to endow all the driver chips with the same nominal operation currents, the purpose of F[0:7] is to fine-tune the LED currents on each individual ASIC so that uniformity in LED luminescence can be attained throughout the entire printhead. Transistors MI1 through MI4 together form a current-matching buffer for interfacing DA8Y2 with the preceding stage Y3; while transistors MO1 through MO4 form the counterpart for interfacing DA8Y2 with the following stage Y1. Detailed discussion of the operation of the circuit will now be described. 
     Transistors MI1 and MI2 determine the value of the input current I 2  in response to the gate voltages developed at nodes DD1 and DD2 by the action of cascoded current-mirroring with the preceding stage Y3. This current is then used to drive the inputs of DA8Y2 by means of the master cascoded current-mirror input pair MI3 and MI4. The resultant, digitally-controlled output current from circuit DA8Y2 is reflected to the slave cascoded current-mirror transistors MO3 and MO4 to produce the output current I 1 . This fine-adjust control current I 1  is in turn mirrored to the following Linear Cascoded LED Current Amplifier/Driver Circuit Y1 by means of diode-connected transistors MO1 and MO2 through the voltages developed at nodes DL1 and DL2. Accordingly, I 1  is linearly proportional to I 2  by virtue of current-mirror action, with the proportionality constant being determined by the externally supplied digital word F[0:7]. The result can be summarized mathematically as follows: ##EQU18## where F 1  is the digital weight of the input word F[0:7]. 
     With the transistor sizing information given in FIGS. 4A, 4B, typical exemplary values for I 2  are 5 μA and I 1  =72 μA, F[0:7] set at 162 (decimal). 
     Linear Cascoded LED Current Amplifier/Driver Circuit Y1 
     FIG. 3E shows the schematic diagram of one of the 96 linear cascoded LED current amplifier/driver circuits on board of each one of the printhead driver chips. It is, functionally speaking, a high-impedance, linear, constant-current source that is insensitive to power supply fluctuations. Its purpose is to provide to the xth LED (where x=1,2, . . . ,96) attached between node NLEDx and ground, a drive current, I L1X , that varies monotonically with a master control current, I LX . I 1X  is the mirrored counterpart of, and is numerically equal to, the fine-adjust control current I 1  generated from the preceding 8-bit fine-adjust current control circuit Y2, as discussed above. Transistors MOAx and MOBx form the master cascoded current-mirror pair, while transistors M1Ax and M1Bx form the slave cascoded current-mirror pair, and transistors, M2Ax and M2Bx form the LED current on/off switch controlled by a digital input bit, Px. Detailed discussion of the operation of the circuit is described in the following paragraphs. 
     Transistors MOCx and MODx determine the master control current I 1x  on the input leg of the circuit in response to the gate voltages developed at nodes DL1 and DL2 by the action of current mirroring with the preceding circuit Y2. Transistors M2Ax and M2Bx together constitute a STDP (single-throw-double-pole) switch responding to the state of the digital input bit, Px. When Px is set low, conduction through transistor M1Bx is cut off, because (V GS ) M1Bx  &lt;0, thereby allowing no current to flow into the LED. When Px is set high, nodes NCOx and NC1x are connected together, enabling the action of current mirroring to be established between the master and slave-cascoded transistors pairs MOAx and MOBx, and M1Ax and M1Bx, respectively. This causes the LED drive current, I L1X , in the slave leg to be linearly proportional to the master control current, I 1x , when all four transistors are maintained in the saturation region. The input-to-output magnification factor is equal to the ratio of the W/L value of MOAx to that of M1Ax, to first order, namely: ##EQU19## It is important to note that since each LED channel driver has its own independent master current mirror section instead of sharing a common one, the switching of the yth LED channel by digital input bit Py will not affect the loading condition presented to the master cascoded current-mirror transistor, MOBx, of the xth channel. Therefore, cross-talk amongst the LED channels are greatly minimized, leading to very stable LED drive current in each channel. Another benefit is that during switching, the LED rise and fall times do not suffer regardless of how many other LED channels are turned on at one time due to the fact that one master is responsible for driving only one slave at all times. Since the sizes of transistors MOAx, MOBx, MOCx and MODx in the master control section are much smaller than those of the slave driver transistors, M1Ax and M1Bx, the added area to implement this is almost negligible. In order to provide a nominal current of 4 mA flowing through the LED when it is turned on at 30° C., the master control current, I 1x , is set to approximately 72 μA. The deployment of the cascoded current mirror configuration greatly reduces the effects of channel-length modulation (i.e., the sensitivity of I DS  with respect to V DS ) on the drive transistors (M1Ax, M1Bx) operating in the saturation region. Typically, M1A and M1B may be of identical sizes, and have a dc-gain, A v , that is much greater than unity. 
     The cascoded driver circuit offers an increase in output impedance over that of a single-transistor driver circuit by a factor of about 45 higher than that of a single-transistor current-mirror driver circuit of the same size. As a consequence, excellent current regulation is achieved: the voltage at node NLEDx can vary as much as +1 volt about the operating point without affecting the LED currents, I L1X , by more than 0.16%. A third advantage of the cascoded current-mirror configuration is an excellent power supply rejection. The present circuit is suited to operate at an LED power supply, VLED, of 5 volts. As long as VLED is not reduced to below 4 volts, the circuit will stay in the saturation region. Under this condition, as VLED is varied, the gate voltages at the diode-connected transistors, MOAX and MOBY, will be adjusted automatically to sustain the same drain-to-source current, I 1X , thereby keeping the gate-to-source voltages of these two transistors, (V GS ) MOAX  and (V GS ) MOBX , fixed. Since the gates of M1AX and M1BX are tied to those of MOAX and MOBX, respectively, (V GS ) M1AX  and (V GS ) M1BX  also remains unchanged, thus causing the mirrored current, I L1X , to stay constant. 
     8-Bit Current-Steering Multiplying Digital-to-Analog Converter (Circuit DA8Y) 
     FIG. 3G shows the schematic diagram of the 8-bit current-steering multiplying digital-to-analog converter used in circuits Y2, Y3 and Y5. It is functionally speaking, a current-controlled current source with digitally programmable gain, whose transfer characteristics can be expressed by the following relationship: ##EQU20## where D k  is the binary weight of the input word D[0:7], I DI  is the input current, and I OUT  is the output current. 
     Circuit DA8Y is sized and biased to operate with both the input and output current range centering around 5 μa when the input digital word, D[0:7], is set to mid-range, i.e., 80(hex). Detailed discussion of the operation of the circuit is described in the following paragraphs. 
     The value of the input current, I DI , is set up by transistors MI1 and MI2 in response to the gate voltages developed at nodes DAI1 and DAI2 by the action of cascoded current-mirroring with its preceding stage. This current is then reflected to an array of eight slave cascoded current-mirror pairs, Mx3 and Mx4, where x=0,1,2, . . . 7 from the master input transistor pair, MI3 and MI4, through the voltages developed at nodes NM1 and NM2, depending on the states of the corresponding bits of the input digital word, D[0:7]. 
     Transistors Mx1 and Mx2 constitute a STDP (single-throw double-pole) switch responding to the state of the digital input bit D x . When D x  is set high, nodes NSx and NM1 are connected together, enabling the action of current mirroring to be established between the master and slave-cascoded transistors pairs, MI3 and MI4, and Mx3 and Mx4, respectively. A reflected current, I DX , is thus caused to flow through transistor pair, Mx3 and Mx4 whose value can be expressed by the following equation: ##EQU21## where x=0,1,2, . . . 7. 
     When transistors Mx4 (and similarly Mx3) are sized such that ##EQU22## the expression for the reflected current can be simplified to assume the form: 
     
         I.sub.Dx =2.sup.x I.sub.DI. 
    
     When the data bit, D x , is set low, transistor Mx2 is turned on, causing node NSx to be shorted to ground. As a result, transistor Mx3 is turned off, because at this point (V GS ) Mx3  ≦0, thereby prohibiting current flow through the cascoded-slave current-mirror pair, Mx3 and Mx4, namely, I Dx  =0 when D x  =0. The action of the digital input bit, D x , on the branch current, I Dx  can be summarized as: 
     
         I.sub.Dx =2.sup.x I.sub.DI D.sub.x. 
    
     Note that the drain outputs of all the slave current-mirror transistors are tied together at node DA02. This means that the branch currents, I D0  through I D7 , are in effect summed to yield the output current I OUT  : ##EQU23## which can be expressed in terms of the input current I DI  as follows ##EQU24## Thus, this circuit provides an output current which is a product of the input current, I DI , and the binary weighted sum of the input digital word, D[0:7]. This digitally-controlled output current from circuit DA8Y can be subsequently reflected to a following stage by means of the diode-connected transistor, MJ1 and MJ2, through the voltages developed at nodes DA01 and DA02. 
     One of the design considerations for this is that when I OUT  varies from zero to full range, i.e., from 0 to 256 I D0 , all the transistors must be so biased that they continue to operate in the saturation region. This necessary condition is achieved by properly sizing the output summing transistors, MJ1 and MJ2, in such a way that when only the most significant bit (MSB) current, I D7 , is turned on, the voltage developed at node DAO2 is almost identical to that developed at node NM1. 
     Another design consideration is the deviation from ideal current mirroring when ΔL and ΔW, the uncertainties in the channel length and channel width of a transistor due to process and photolithographic limitations, respectively, are taken into account. Deviation from perfect current mirroring can become quite substantial when the channel widths differ by more than one order of magnitude. This is particularly a problem where the channel width of the MSB transistor M74 is 128 times that of the LSB transistor MO4. This can lead to gross non-linearity in the DAC transfer characteristics because the binary-weighted sum would not provide a faithful representation of the expected analog value. Such non-idealities of current mirroring due to process and photolithographic limitations can be circumvented by employing the concept of unit cell transistors arranged in a common centroid configuration. This is achieved by segmenting the slave transistor pairs, Mx3 and Mx4, such that each of them are composed of exactly 2 x  number of unit transistors connected in parallel, with the size of the unit cell transistor coinciding with that of the LSB transistor, MO4. In this scheme, the ratio of the active branch current corresponding to the xth bit, D x , to that of D 0  is calculated to be: ##EQU25## as desired for a faithful digital-to-analog conversion operation. 
     Another source of non-idealities in current mirrors can be attributed to the variation in threshold voltage over different areas of the wafer due to process non-uniformity. 
     In addition to placing the master and slave transistors in as close proximity as possible, this non-ideality in current mirroring due to threshold voltage variation can be compensated for by the use of a common centroid configuration in the layout of the circuit, as shown in FIG. 5. Each slave transistor corresponding to the xth bit, Mx4 (and similarly for Mx3) is divided into two halves, each of which consists of 2 x-1  unit cell transistors connected in parallel. The two composite transistor halves of Mx4 are arranged symmetrically so that they nestle around those of the transistor corresponding to the lower order bit, M(x-1)4, with the least significant bit, LSB transistor being at the center, and the MSB halves at the outermost positions. 
     The definition of the centroid with respect to the threshold voltage can be shown to correspond mathematically to the normalized first moment of the statistical variable, V T . From elementary statistics theory, it can be concluded from the above discussions that each one of the composite slave transistors laid out in this geometrical arrangement can be treated as a single transistor located at the centroid O with the same equivalent threshold voltage, V T . Accordingly, errors in threshold voltage and current through each transistor can be made negligible by using such a technique, thereby allowing faithful current mirroring to be obtained. 
     As may be seen from FIG. 5, the transistors are formed into binary weighted groups of unit transistors which groups progressively increase in weight or size with distance from the centroid O. Thus, at the centroid is the single unit transistor M04 having a binary weight 2°. This unit transistor is comprised of a polysilicon gate overlapping a diffusion region whose two terminals form the drain and source. Just outwardly from the centroid are the two unit transistors each forming a half of the transistor M14 that are connected together by a metal lead. The two unit transistors are disposed, one one each side of the centroid and connected by lead L 1 . The remaining binary weighted transistor groups are similarly formed except that starting for transistor M54 where 16 transistors are formed on each side of the centroid to form the 32 unit transistors comprising M54, two banks of eight unit transistors are formed and connected together in lieu of having a line of 16 transistors which may also be done. The still higher binary weighted transistors (not shown) follow the pattern of tying together the banks of 8 unit transistors as shown. Thus as can be seen, at least some of transistors forming the D/A converter can be formed as unit transistors and arranged in the common centroid pattern to provide the advantages described above. 
     There has thus been described a circuit where an output current can be made to be linearly dependent on temperature with programmable temperature coefficients. An application for this circuit is to compensate for the derating in the LED currents in a printhead as temperature increases. The slope of linearity, both in magnitude and in polarity, can be adjusted by means of an input current source, either through digital or analog control, or both. In this regard, a circuit providing a negative temperature coefficient may be provided by modifying the circuit Y4 so that the circuit-generating current I 5  is relocated to feed current I 5  into a node that sums currents I 5  and I 6  so that I 4  =I 5  +I 6 . In such a case, the ratio of I 50  /I 60  in equation 2.9 can be adjusted so that the numerator of equation 2.9 becomes negative, Linearity is achieved by a novel design such that one portion of the circuit operates in the weak-inversion region of MOS devices. Also, high power-supply rejection ratio is obtained by full utilization of the cascode current mirror configuration. 
     In-situ temperature monitoring is thus provided with programmable temperature profile for LED driving current. 
     Fully linear control from digital words to LED driving currents over desired operating ranges is also provided. 
     The system operates totally in the current mode, and true cascode current mirror configuration is used throughout to achieve a very high power-supply rejection ratio. The LED cascode driver stage has the advantages of significant area reduction, excellent current regulation regardless of LED load, fully linear control of LED current by input current over desired LED operating region and extremely high power-supply rejection ratio. 
     The invention has been described in detail with particular reference to preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.