Patent Publication Number: US-9838021-B2

Title: Configurable gate array based on three-dimensional writable memory

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priorities from Chinese Patent Application No. 201610125227.8, filed Mar. 5, 2016, Chinese Patent Application No. 201610307102.7, filed May 10, 2016, in the State Intellectual Property Office of the People&#39;s Republic of China (CN). 
     This application is also a continuation-in-part of U.S. patent application Ser. No. 15/450,017, filed Mar. 5, 2017, the disclosure of which are incorporated herein by reference in their entireties. 
     BACKGROUND 
     1. Technical Field of the Invention 
     The present invention relates to the field of integrated circuit, and more particularly to configurable gate array. 
     2. Prior Art 
     A configurable gate array is a semi-custom integrated circuit designed to be configured by a customer after manufacturing. U.S. Pat. No. 4,870,302 issued to Freeman on Sep. 26, 1989 (hereinafter referred to as Freeman) discloses a configurable gate array. It contains an array of configurable logic elements (also known as configurable logic blocks) and a hierarchy of configurable interconnects (also known as programmable interconnects) that allow the configurable logic elements to be wired together. Each configurable logic element in the array is in itself capable of realizing any one of a plurality of logic functions (e.g. shift, logic NOT, logic AND, logic OR, logic NOR, logic NAND, logic XOR, arithmetic addition “+”, arithmetic subtraction “−”, etc.) depending upon a first configuration signal. Each configurable interconnect can selectively couple or de-couple interconnect lines depending upon a second configuration signal. 
     Complex math functions are widely used in various applications. To meet the speed requirements, many high-performance applications require that these complex math functions be implemented in hardware. In conventional configurable gate arrays, complex math functions are implemented in fixed computing elements, which are part of hard blocks and not configurable, i.e. the circuits implementing these complex math functions are fixedly connected and are not subject to change by programming. Apparently, fixed computing elements would limit further applications of the configurable gate array. To overcome this difficulty, the present invention expands the original concept of the configurable gate array by making the fixed computing elements configurable. In other words, besides configurable logic elements, the configurable gate array comprises configurable computing elements, which can realize any one of a plurality of math functions. 
     OBJECTS AND ADVANTAGES 
     It is a principle object of the present invention to extend the applications of a configurable gate array to the field of complex math computation. 
     It is a further object of the present invention to provide a configurable gate array where not only logic functions can be customized, but also math functions. 
     It is a further object of the present invention to provide a configurable gate array with more computing power. 
     It is a further object of the present invention to provide a configurable gate array with smaller die size and lower die cost. 
     In accordance with these and other objects of the present invention, the present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). 
     SUMMARY OF THE INVENTION 
     The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function. The usage cycle of the configurable computing element comprises two stages: a configuration stage and a computation stage. In the configuration stage, the LUT for a desired math function is loaded into the 3D-W array. In the computation stage, the functional value of the desired math function is read out from the LUT. For an electrically re-programmable 3D-W, a configurable computing element can be re-configured to realize different math functions. 
     Besides configurable computing elements, the preferred configurable gate array further comprises configurable logic elements and configurable interconnects. During operation, a complex math function is first decomposed into a number of basic math functions. Each basic math function is then realized by programming the associated configurable computing element. Finally, the complex math function is realized by programming the corresponding configurable logic elements and configurable interconnects. 
     Using 3D-W for configurable computing element offers many advantages. First of all, because it has a large storage density, 3D-W can be used to store a large LUT for a better math precision; or, more LUTs for more math functions. Being electrically programmable, the math functions that can be realized in a 3D-W array are essentially boundless. This is superior to the configurable gate array based on three-dimensional printed memory (3D-P), which supports a limited math library (referring to the co-pending U.S. patent application Ser. No. 15/450,017). Secondly, because they can be vertically stacked, the 3D-W arrays belonging to different configurable computing elements can be stacked together within a single 3D-W block. This would save substantial die area. Thirdly, because the 3D-W array does not occupy any substrate area, the configurable logic elements and/or the configurable interconnects can be formed underneath the 3D-W arrays. This would further save die area. 
     Accordingly, the present invention discloses a configurable gate array, comprising: at least a configurable logic element formed on a semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; at least a first portion of a first configurable computing element formed in a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, wherein said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function. 
     The present invention further discloses another configurable gate array, comprising: at least a configurable interconnect formed on a semiconductor substrate, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; at least a first portion of a first configurable computing element formed in a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, wherein said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function. 
     The present invention further discloses yet another configurable gate array, comprising: an array of configurable computing elements including a configurable computing element, wherein said configurable computing element is electrically programmable and can be loaded with a look-up table (LUT) for a math function; an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library; an array of configurable interconnects including a configurable interconnect, wherein said array of configurable interconnects couple said array of configurable computing elements with said array of configurable logic elements; wherein said configurable gate array realizes a complex math function by programming said array of configurable computing elements, said array of configurable logic elements and said array of configurable interconnects. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of a three-dimensional writable memory (3D-W); 
         FIG. 2  discloses a symbol for a preferred configurable computing element; 
         FIG. 3  is a substrate layout view of a preferred configurable computing element; 
         FIG. 4  discloses two usage cycles of a preferred re-configurable computing element; 
         FIG. 5A  shows an interconnect library supported by a preferred configurable interconnect;  FIG. 5B  shows a logic library supported by a preferred configurable logic element; 
         FIG. 6  is a circuit block diagram of a first preferred configurable gate array; 
         FIG. 7  is a substrate layout view of a first implementation of the first preferred configurable gate array; 
         FIG. 8A  is a cross-sectional view of a second implementation of the first preferred configurable gate array;  FIG. 8B  is its substrate layout view; 
         FIG. 9  shows an instantiation of the first preferred configurable gate array implementing a complex math function; 
         FIG. 10  is a circuit block diagram of a second preferred configurable gate array; 
         FIGS. 11A-11B  show two instantiations of the second preferred configurable gate array. 
     
    
    
     It should be noted that all the drawings are schematic and not drawn to scale. Relative dimensions and proportions of parts of the device structures in the figures have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference symbols are generally used to refer to corresponding or similar features in the different embodiments. In the present invention, the terms “program” and “configure” are used interchangeably. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Those of ordinary skills in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons from an examination of the within disclosure. 
     Referring now to  FIG. 1 , a preferred three-dimensional writable memory (3D-W)  10  is shown. 3D-W is a type of three-dimensional memory (3D-M) whose memory cells are electrically programmable. Based on the number of programming allowed, a 3D-W can be categorized into three-dimensional one-time-programmable memory (3D-OTP) and three-dimensional multiple-time-programmable memory (3D-MTP). A common 3D-W is 3D-XPoint. Other types of 3D-M include memristor, resistive random-access memory (RRAM or ReRAM), phase-change memory, programmable metallization cell (PMC), conductive-bridging random-access memory (CBRAM), and the like. 
     The 3D-W  10  comprises a substrate circuit OK formed on the substrate  0 . A first memory level  16 A is stacked above the substrate circuit OK, with a second memory level  16 B stacked above the first memory level  16 A. The substrate circuit OK includes the peripheral circuits of the memory levels  16 A,  16 B. It comprises transistors  0 t and the associated interconnect  0 i (including  0 M 1 - 0 M 3 ). Each of the memory levels (e.g.  16 A,  16 B) comprises a plurality of first address-lines (i.e. y-lines, e.g.  2   a,    4   a ), a plurality of second address-lines (i.e. x-lines, e.g.  1   a,    3   a ) and a plurality of 3D-W cells (e.g.  1   aa,    2   aa ). The first and second memory levels  16 A,  16 B are coupled to the substrate circuit OK through contact vias  1   av,    3   av,  respectively. 
     In a 3D-W, each memory level comprises at least a 3D-W array. A 3D-W array is a collection of 3D-W cells in a memory level that share at least one address-line. Within a single 3D-W array, all address-lines are continuous; between adjacent 3D-W arrays, address-lines are not continuous. On the other hand, a 3D-W die comprises a plurality of 3D-W blocks. Each 3D-W block includes all memory levels in a 3D-W and its topmost memory level only comprises a single 3D-W array, whose projection on the substrate defines the boundary of the 3D-W block. 
     A 3D-W cell  1   aa  comprises a programmable layer  12  and a diode layer  14 . The programmable layer  12  could be an antifuse layer (used for 3D-OTP) or a re-programmable layer (used for 3D-MTP). The diode layer  14  is broadly interpreted as any layer whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. The diode could be a semiconductor diode (e.g. p-i-n silicon diode), or a metal-oxide (e.g. TiO 2 ) diode. 
     Referring now to  FIG. 2 , a symbol for a preferred configurable computing element  100  is shown. The input port IN includes input data  115 , the output port OUT includes output data  135 , and the configuration port CFG includes at least a configuration signal  125 . When the configuration signal  125  is “write”, the LUT for a desired math function is loaded into the configurable computing element  100 ; when the configuration signal  125  is “read”, the functional value of the desired math function is read out from the LUT. 
       FIG. 3  discloses a preferred configurable computing element  100 . This figure is a layout view of its substrate circuit OK. Because the 3D-W arrays are stacked above the substrate OK and not located in the substrate  0 , their projections on the substrate  0 , not the 3D-W arrays themselves, are shown in the areas enclosed by dash lines. In this preferred embodiment, the LUT is stored in at least a 3D-W array  110 . The substrate circuit OK includes the X decoder  15 , Y decoder (including read-out circuit)  17  and Z decoder  19  for the 3D-W array  110 . 
     Referring now to  FIG. 4 , two usage cycles  620 ,  660  of a preferred re-configurable computing element  100  are shown. For the re-configurable computing element  100 , the 3D-W array  110  is electrically re-programmable. The first usage cycle  620  comprises two stages: a configuration stage  610  and a computation stage  630 . In the configuration stage  610 , the LUT of a first desired math function is loaded into the 3D-W array  110 . In the computation stage  630 , the functional value of the first desired math function is read out from the LUT. Being electrically re-programmable, the re-configurable computing element  100  can realize different math functions during different usage cycles  620 ,  660 . During the second usage cycle  660  (including two stages  650 ,  670 ), a second desired math function is loaded and then read out. The re-configurable computing element  100  is particularly suitable for single-instruction-multiple-data (SIMD)-type of data processing. Once the LUTs are loaded into the 3D-W arrays  110  in the configuration stage, a large amount of data can be fed into the re-configurable computing element  100  and processed in high speed. SIMD has many applications, e.g. vector processing in image processing, massively parallel processing in scientific computing. 
     Referring now to  FIGS. 5A-5B , an interconnect library and a logic library are shown.  FIG. 5A  shows the interconnect library supported by a preferred configurable interconnect  300 . An interconnect library is a collection of all interconnects supported by a configurable interconnect. This interconnect library includes the followings: a) the interconnects  302 / 304  are coupled, the interconnects  306 / 308  are coupled, but  302 / 304  are not connected with  306 / 308 ; b) the interconnects  302 / 304 / 306 / 308  are all coupled; c) the interconnects  306 / 308  are coupled, but the interconnects  302 ,  304  are not coupled, neither are  302 ,  304  connected with  306 / 308 ; d) the interconnects  302 / 304  are coupled, but the interconnects  306 ,  308  are not coupled, neither are  306 ,  308  connected with  302 / 304 ; e) interconnects  302 ,  304 ,  306 ,  308  are not coupled at all. As used herein, the symbol “/” between two interconnects means that these two interconnects are coupled, while the symbol “,” between two interconnects means that these two interconnects are not coupled. More details on the configurable interconnects are disclosed in Freeman. 
       FIG. 5B  shows the logic library supported by a preferred configurable logic element  200 . A logic library is a collection of all logic functions supported by a configurable logic element. In this preferred embodiment, the inputs A and B are input data  210 ,  200 , and the output C is the output data  230 , the logic library includes the followings: C=A, NOT A, A shift by n bits, AND(A,B), OR(A,B), NAND(A,B), NOR(A,B), XOR(A,B), A+B, A−B. To facilitate pipelining, the configurable logic element  200  may comprise sequential logic such as flip-flops and registers. More details on the configurable logic elements are disclosed in Freeman. 
     Referring now to  FIG. 6 , a first preferred configurable gate array  400  is disclosed. It comprises first and second configurable slices  400 A,  400 B. Each configurable slice (e.g.  400 A) comprises a first array of configurable computing elements (e.g.  100 AA- 100 AD) and a second array of configurable logic elements (e.g.  200 AA- 200 AD). A configurable channel  320  is placed between the first array of configurable computing elements (e.g.  100 AA- 100 AD) and the second array of configurable logic elements (e.g.  200 AA- 200 AD). The configurable channels  310 ,  330 ,  350  are also placed between different configurable slices  300 A,  300 B. The configurable channels  310 - 350  comprise an array of configurable interconnects  300 . For those skilled in the art, besides configurable channels, sea-of-gates may also be used. 
       FIG. 7  shows a first implementation of the first preferred configurable gate array  400  is shown. Because it does not occupy any substrate area, the 3D-W array  110  can be stacked above the configurable logic element  200  and at least partially cover the configurable logic element  200 . Similarly, the 3D-W array  110  can be stacked above the configurable interconnect  300  and at least partially cover the configurable interconnect  300 . Apparently, this would save die area. 
       FIGS. 8A-8B  show a second implementation of the first preferred configurable gate array  400  is shown. This implementation corresponds to the configurable slice  400 A of  FIG. 6 . For the configurable computing elements  100 AA- 100 AD, their 3D-W arrays  110 AA- 110 AD can be vertically stacked in a single 3D-W module. To be more specific, the substrate circuit OK comprises the configurable logic elements  200 AA- 200 AD; the 3D-W array  110 AA for the configurable computing element  100 AA (storing the LUT A for a first math function) is placed in the first memory level  16 A and stacked above the substrate OK (along the +Z direction), the 3D-W array  110 AB for the configurable computing element  100 AB (storing the LUT B for a second math function) is placed in the second memory level  16 B and stacked above the 3D-W array  110 AA (along the +Z direction), the 3D-W array  110 AC for the configurable computing element  100 AC (storing the LUT C for a third math function) is placed in the third memory level  16 C and stacked above the 3D-W array  110 AB (along the +Z direction), and the 3D-W array  110 AD for the configurable computing element  100 AD (storing the LUT D for a fourth math function) is placed in the fourth memory level  16 D and stacked above the 3D-W array  110 AC (along the +Z direction). This arrangement becomes more apparent in the substrate layout view of  FIG. 8B . The projections of the 3D-W arrays  110 AA- 110 AD (storing the LUTs A-D) overlap each other on the substrate  0 . This would save substantial die area and lead to a compact configurable gate array  400 . 
       FIG. 9  discloses an instantiation of the first preferred configurable gate array implementing a complex math function e=a·sin(b)+c·cos(d) is disclosed. The configurable interconnects  300  in the configurable channel  310 - 350  use the same convention as  FIG. 5A : the interconnects with dots at the intersection mean that the interconnects are connected; the interconnects without dots at the intersection mean that the interconnects are not connected; a broken interconnect means that two broken sections are two un-coupled interconnect lines. In this preferred implementation, the configurable computing element  100 AA is configured to realize the function log( ) whose result log(a) is sent to a first input of the configurable logic element  200 A. The configurable computing element  100 AB is configured to realize the function log[sin( )], whose result log[sin(b)] is sent to a second input of the configurable logic element  200 A. The configurable logic element  200 A is configured to realize arithmetic addition, whose result log(a)+log[sin(b)] is sent the configurable computing element  100 BA. The configurable computing element  100 BA is configured to realize the function exp( ) whose result exp{log(a)+log[sin(b)]}=a·sin(b) is sent to a first input of the configurable logic element  200 BA. Similarly, through proper configurations, the results of the configurable computing elements  100 AC,  100 AD, the configurable logic elements  200 AC, and the configurable computing element  100 BC can be sent to a second input of the configurable logic element  200 BA. The configurable logic element  200 BA is configured to realize arithmetic addition, whose result a·sin(b)+c·cos(d) is sent to the output e. Apparently, by changing its configuration, the configurable gate array  400  can realize other complex math functions. 
     Referring now to  FIG. 10 , a second preferred configurable gate array  400  is shown. Besides configurable computing elements  100 A,  100 B and configurable logic element  200 A, this preferred embodiment further comprises a multiplier  500 . The configurable channels  360 - 380  comprise a plurality of configurable interconnects. With the addition of the multiplier  500 , the preferred configurable gate array  400  can realize more math functions and its computational power will become more powerful. 
       FIGS. 11A-11B  disclose two instantiations of the second preferred configurable gate array  400 . In the instantiation of  FIG. 11A , the configurable computing element  100 A is configured to realize the function exp(f), while the configurable computing element  100 B is configured to realize the function inv(g). The configurable channel  370  is configured in such a way that the outputs of  100 A,  100 B are fed into the multiplier  500 . The final output is then h=exp(f)*inv(g). On the other hand, in the instantiation of  FIG. 11B , the configurable computing element  100 A is configured to realize the function sin(f), while the configurable computing element  100 B is configured to realize the function cos(g). The configurable channel  370  is configured in such a way that the outputs of  100 A,  100 B are fed into the configurable logic element  200 A, which is configured to realize arithmetic addition. The final output is then h=sin(f)+cos(g). [Para  47 ] While illustrative embodiments have been shown and described, it would be apparent to those skilled in the art that many more modifications than that have been mentioned above are possible without departing from the inventive concepts set forth therein. The invention, therefore, is not to be limited except in the spirit of the appended claims.