Patent Publication Number: US-11038103-B2

Title: Tightly integrated 1T1R ReRAM for planar technology

Description:
BACKGROUND 
     The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure that includes an oxide resistive random access memory (ReRAM) co-integrated with a drain region of a field effect transistor (FET). 
     Many modern day electronic devices contain electronic memory. Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory retains its stored data in the absence of power, whereas volatile memory loses its stored data when power is lost. Resistive random access memory (ReRAM or RRAM) is one promising candidate for the next generation of non-volatile memory due to its simple structure and its compatibility with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes. 
     For oxide ReRAMs, electroforming of a current conducting filament is needed. This process relies on randomness and thus the position of the filament of the oxide ReRAM is not well controlled. This results in a higher forming voltage as the ReRAM cell is scaled and higher device variability. Also, oxide ReRAMs typically require a current control field effect transistor to form a 1T1R (e.g., one-transistor one-resistive element) structure. This makes the process integration complicated. Co-integration of a FET with an oxide ReRAM in tight spacing is thus needed. 
     SUMMARY 
     A semiconductor structure includes an oxide ReRAM co-integrated with a drain region of a field effect transistor (FET). The oxide ReRAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide ReRAM and thus helps to control forming of the conductive filament of the oxide ReRAM. 
     In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes an oxide resistive random access memory (ReRAM) device co-integrated with a field effect transistor (FET), wherein the ReRAM device has a tip region that contacts a faceted upper surface of a drain region of the FET. 
     In another aspect of the present application, a method of forming a semiconductor structure is provided. In one embodiment, the method includes providing a sacrificial gate structure on a surface of a semiconductor substrate, wherein a first dielectric spacer and a second dielectric spacer laterally surround the sacrificial gate structure. A source region and a drain region are formed in the semiconductor substrate and on opposite sides of the gate structure. The source region and the drain region have faceted sidewall surfaces. A self-limiting etch is then performed on the drain region to provide a faceted upper surface to the drain region, and elements of an oxide resistive random access memory (ReRAM) device are formed in contact with the faceted upper surface of the drain region. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is a cross sectional view of an exemplary semiconductor structure of the present application during an early stage of fabrication and including a plurality of sacrificial gate structures located on a surface of a semiconductor substrate, wherein a first dielectric spacer laterally surrounds each sacrificial gate structure. 
         FIG. 2  is a cross sectional view of the exemplary semiconductor structure of  FIG. 1  after forming a source region and a drain region in the semiconductor substrate and at a footprint of each sacrificial gate structure. 
         FIG. 3  is a cross sectional view of the exemplary semiconductor structure of  FIG. 2  after forming a second dielectric spacer on the first dielectric spacer, and subsequently forming an interlayer dielectric (ILD) material layer. 
         FIG. 4  is a cross sectional view of the exemplary semiconductor structure of  FIG. 3  after forming an opening in the ILD material layer which physically exposes a surface of the drain region. 
         FIG. 5  is a cross sectional view of the exemplary semiconductor structure of  FIG. 4  after performing a self-limiting etch into the physically exposed drain region to provide a faceted upper surface to the drain region. 
         FIG. 6  is a cross sectional view of the exemplary semiconductor structure of  FIG. 5  after forming a resistive switching layer and a top electrode material in the opening. 
         FIG. 7  is a cross sectional view of the exemplary semiconductor structure of  FIG. 6  after recessing the resistive switching layer and the top electrode material. 
         FIG. 8  is a cross sectional view of the exemplary semiconductor structure of  FIG. 7  after filling in an upper portion of the opening with additional ILD material and replacing each sacrificial gate structure with a functional gate structure. 
         FIG. 9  is a cross sectional view of the exemplary semiconductor structure of  FIG. 8  after forming contact structures. 
         FIG. 10  is a cross sectional view of another exemplary semiconductor structure of the present application including a ReRAM device that includes a bottom electrode, a resistive switching liner, and a top electrode. 
     
    
    
     DETAILED DESCRIPTION 
     The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals. 
     In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application. 
     It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present. 
     Referring first to  FIG. 1 , there is illustrated an exemplary semiconductor structure of the present application during an early stage of fabrication and including a plurality of sacrificial gate structures located on a surface of a semiconductor substrate  10 , wherein a first dielectric spacer  16  laterally surrounds each sacrificial gate structure. Although a plurality of sacrificial gate structures are described and illustrated, the present application can be employed when a single sacrificial gate structure is employed. 
     The semiconductor substrate  10  that can be employed in the present application includes at least one semiconductor material that has semiconducting properties. Examples of semiconductor materials that can be used as the semiconductor substrate  10  include, for example, silicon (Si), a silicon germanium (SiGe) alloy, a silicon germanium carbide (SiGeC) alloy, germanium (Ge), III/V compound semiconductors or II/VI compound semiconductors. In one embodiment, the semiconductor substrate  10  is a bulk semiconductor substrate. The term “bulk semiconductor substrate” denotes a substrate that is composed entirely of one or more semiconductor materials. In one example, the bulk semiconductor substrate is composed entirely of Si. 
     In some embodiments, the semiconductor substrate  10  is composed of a semiconductor-on-insulator (SOI) substrate. A SOI substrate typically includes a handle substrate, an insulator layer and a topmost semiconductor material layer. In some embodiments, the handle substrate of the SOI substrate may include a semiconductor material, as described above. In other embodiments, the handle substrate may be omitted, or the handle substrate may be composed of a conductive material and/or an insulator material. The insulator layer of the SOI substrate may include a crystalline or non-crystalline dielectric material. In one example, the insulator layer of the SOI substrate may be composed of silicon dioxide and/or boron nitride. The topmost semiconductor layer of the SOI substrate is composed of a semiconductor material, as defined above. 
     Each sacrificial gate structure typically includes a sacrificial gate material  12  and a sacrificial gate cap material  14 . In some embodiments (not shown), each sacrificial gate structure may also include a sacrificial gate dielectric material located beneath the sacrificial gate material  12 . In yet other embodiments, the sacrificial gate structures are entirely composed of the sacrificial gate material  12 . 
     The sacrificial gate structures may be formed by a blanket layer (or layers) of a sacrificial material (or various sacrificial materials) and then patterning the sacrificial material (or various sacrificial materials) by lithography and an etch. In one embodiment, the sacrificial gate structures can be formed by first depositing a blanket layer of a sacrificial gate dielectric material. The sacrificial gate dielectric material can be an oxide, nitride, and/or oxynitride. In one example, the sacrificial gate dielectric material can be a high k material having a dielectric constant greater than silicon dioxide. In some embodiments, a multilayered dielectric structure comprising different dielectric materials, e.g., silicon dioxide, and a high k dielectric can be formed and used as the sacrificial gate dielectric material. The sacrificial gate dielectric material can be formed by any deposition technique including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. 
     After forming the blanket layer of sacrificial gate dielectric material, a blanket layer of a sacrificial gate material  12  can be formed on the blanket layer of sacrificial gate dielectric material. The sacrificial gate material  12  can include any material including, for example, polysilicon, amorphous silicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals or multilayered combinations thereof. The sacrificial gate material  12  can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other like deposition processes. 
     After forming the blanket layer of sacrificial gate material  12 , a blanket layer of a sacrificial gate cap material  14  can be formed. The sacrificial gate cap material  14  may include a hard mask material such as, for example, silicon dioxide and/or silicon nitride. The sacrificial gate cap material  14  can be formed by any suitable deposition process such as, for example, chemical vapor deposition or plasma enhanced chemical vapor deposition. The various blanket layers of sacrificial materials are then patterned by lithography and etching to provide the sacrificial gate structures on the surface of semiconductor substrate  10 . 
     The first dielectric spacers  16  can be formed by deposition of a first dielectric spacer material and then etching the first dielectric spacer material. Illustrative examples of first dielectric spacer materials that may be employed in the present application include, but are not limited to, silicon dioxide, silicon nitride or silicon oxynitrides. In some embodiments, the first dielectric spacer material (and thus the first dielectric spacers  16 ) and the sacrificial gate cap material are both composed of a same dielectric material such as, for example, silicon nitride. The deposition process that can be employed in providing the first dielectric spacer material includes, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). The etch used to etch the deposited first dielectric spacer material may comprise a dry etching process such as, for example, reactive ion etching. 
     Referring now to  FIG. 2 , there is illustrated the exemplary semiconductor structure of  FIG. 1  after forming a source region  18 S and a drain region  18 D in the semiconductor substrate  10  and at a footprint of each sacrificial gate structure. When an SOI substrate is employed, the source region  18 S and drain region  18 D are formed into the topmost semiconductor layer of the SOI substrate. The source region  18 S and drain region  18 D can be formed by first performing a self-limiting etch. The term “self-limiting etch” is used throughout the present application to denote an etch that removes certain planes of a material faster than other planes of the same material. For example, a self-limiting etch of silicon removes {100} and/or {110} planes faster than {111} planes. The self-limiting etch may also be referred to herein as a crystallographic etch. One example of a self-limiting etch is a sigma etch. Some illustrative examples of etchants that may be used during the self-limiting etch include tetramethylammonium hydroxide (TMAH), ammonia (NH 4 OH), and/or potassium hydroxide (KOH). In the present application, this self-limiting etch provides source/drain trenches (and thus the source region  18 S and the drain region  18 D) having faceted sidewall surfaces. In one embodiment, the source/drain trenches (and thus the source region  18 S and the drain region  18 D) are sigma shaped. 
     A doped semiconductor material which provides the source region  18 S and the drain region  18 D is then formed into each of the source/drain trenches utilizing an epitaxial growth (or deposition) process. The terms “epitaxially growing and/or depositing” and “epitaxially grown and/or deposited” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. 
     Examples of various epitaxial growth process apparatuses that can be employed in the present application include, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition typically ranges from 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. The epitaxial growth of the doped semiconductor material can be performed utilizing any well known precursor gas or gas mixture. Carrier gases like hydrogen, nitrogen, helium and argon can be used. 
     The semiconductor material that provides the doped semiconductor material and thus the source region  18 S and the drain region  18 D may include a same or different semiconductor material than the semiconductor substrate  10 . In an example, the doped semiconductor material and the semiconductor substrate  10  are both composed of silicon. 
     The doped semiconductor material also includes a dopant which is typically introduced into the precursor gas mixture that provides the semiconductor material of the source region  18 S and drain region  18 D during the epitaxial growth process. The dopant can be either a p-type dopant or an n-type dopant. The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium and indium. “N-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic and phosphorous. In one example, the doped semiconductor material provides the source region  18 S and the drain region  18 D comprises silicon or a silicon germanium alloy that has a dopant concentration of from 4×10 20  atoms/cm 3  to 3×10 21  atoms/cm 3 . 
     Referring now to  FIG. 3 , there is illustrated the exemplary semiconductor structure of  FIG. 2  after forming a second dielectric spacer  20  on the first dielectric spacer  16 , and subsequently forming an interlayer dielectric (ILD) material layer  22 . The second dielectric spacer  20  is formed on an outermost sidewall of the first dielectric spacer  16  and has a bottommost surface that is formed on a portion of the source region  18 S or drain region  18 D. The ILD material layer  22  laterally surrounds, and is present above, each sacrificial gate structure, and the first and second dielectric spacers ( 16 ,  20 ). 
     The second dielectric spacer  20  can be formed by deposition of a second dielectric spacer material and then etching the second dielectric spacer material. In some embodiments, the second dielectric spacer material is composed of a different dielectric spacer material than the first dielectric spacer material. In other embodiments, the second dielectric spacer material is composed of a same dielectric spacer material as the first dielectric spacer material. Illustrative examples of second dielectric spacer materials that may be employed in the present application include, but are not limited to, silicon dioxide, silicon nitride or silicon oxynitrides. In one embodiment, the first dielectric spacer material (and thus the first dielectric spacers  16 ) and the sacrificial gate cap material are both composed of silicon nitride, while the second dielectric spacer material (and thus the second dielectric spacers  20 ) is composed of silicon dioxide The deposition process that can be employed in providing the second dielectric spacer material includes, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). The etch used to etch the deposited second dielectric spacer material may comprise a dry etching process such as, for example, reactive ion etching. 
     ILD material layer  22  can be composed of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer or any combination thereof. The term “low-k” as used throughout the present application denotes a dielectric material that has a dielectric constant of less than silicon dioxide. In another embodiment, a self-planarizing material such as a spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK™ can be used as ILD material layer  22 . In one embodiment, the ILD material layer  22  can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation or spin-on coating. 
     Referring now to  FIG. 4 , there is illustrated the exemplary semiconductor structure of  FIG. 3  after forming an opening  26  within the ILD material layer  22  which physically exposes a surface of the drain region  18 D. The opening  26  can be formed by first providing a patterned mask  24  on the ILD material layer  22 . The patterned mask  24  may include a hard mask material such as, for example, silicon nitride. The patterned mask  24  may be formed by depositing a blanket layer of the hard mask material, and thereafter patterning the blanket layer of the hard mask material. The patterning of the blanket layer of the hard mask material may include an etch such as, for example, a reactive ion etch. This etch, or a separate etch, may be used to provide the opening  26  in the ILD material layer  22 . 
     Referring now  FIG. 5 , there is illustrated the exemplary semiconductor structure of  FIG. 4  after performing a self-limiting etch into the physically exposed drain region  18 D. The self-limiting etch used in this step of the present application is the same as that mentioned above. The etched drain region  18 D has a faceted upper surface  19  defined by an indentation formed in the drain region  18 D which will provide a tip region for the subsequently formed ReRAM device. After the self-limiting etching of the drain region  18 D, the patterned mask  24  is removed from the structure utilizing any material removal process such as, for example, chemical mechanical polishing (CMP). The source region  18 S is not etched during this step of the present application since the patterned mask  24  and the ILD material layer  22  protect the same. 
     Referring now to  FIG. 6 , there is illustrated the exemplary semiconductor structure of  FIG. 5  after forming a resistive switching layer  28  and a top electrode material  30  in the opening  26 . In some embodiments (not shown), a bottom electrode material layer can be formed into the opening  26  prior to forming the resistive switching layer  28  and the top electrode material  30 . When present, the bottom electrode material layer is formed into the opening  26  and a portion of the bottom electrode material layer is in direct physical contact with the faceted upper surface of the drain region  16 D′. The bottom electrode material layer may include, for example, a conductive metal, or a conductive metal nitride. The conductive metal that can provide the bottom electrode material layer may include at least one metal selected from Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The conductive metal nitride the can provide the bottom electrode material layer may include a nitride of at least one metal selected from Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. In one embodiment, the bottom electrode material layer is composed of TiN or an alloy of TiN and TiAlC. The bottom electrode material layer may be formed by a deposition process such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or sputtering. The bottom electrode material layer may have a thickness from 2 nm to 10 nm. Other thicknesses are possible for the bottom electrode material layer as long as bottom electrode material layer does not fill in the entirety of the opening  26 . 
     The resistive switching layer  28  may include an insulating metal oxide. In some embodiments, the insulating metal oxide that provides the resistive switching layer  28  has an energy gap smaller than 5 eV. The insulating metal oxide includes at least one insulating material selected from the group consisting of TiO 2 , NiO, HfO, HfO 2 , ZrO, ZrO 2 , Ta 2 O 5 , ZnO, WO 3 , CoO and Nb 2 O 5 . Though the present application is not limited thereto, and in other embodiments, the energy gap of the resistive switching layer  28  can be adjusted according to an actual requirement. The resistive switching layer  28  may be formed by a deposition process such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or sputtering. The resistive switching layer  28  may have a thickness from 2 nm to 10 nm. Other thicknesses are possible for the resistive switching layer  28  as long as the resistive switching layer  28  does not fill in the entirety of the opening  26 . 
     Top electrode material  30  is formed on the surface of the resistive switching layer  28 . The top electrode material  30  includes one of the conductive metals or conductive metal nitrides mentioned above for the bottom electrode material layer. In some embodiments, the top electrode material  30  and the bottom electrode material are composed of a same conductive metal or conductive metal nitride. In other embodiments, the top electrode material  30  is composed of a different conductive metal or conductive metal nitride than the bottom electrode material. In one embodiment, the top electrode material  30  is composed of TiN, or an alloy of TiN and TiAlC. The top electrode material  30  may be formed by a deposition process such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or sputtering. The top electrode material  30  completely fills in the remaining volume of opening  26 . 
     The structure shown in  FIG. 6  can be formed by first depositing the various material layers (i.e., optional bottom electrode material layer, the resistive switching layer  28  and the top electrode material  30 ) into the opening  26  and atop the ILD material layer  22  and then a planarization process is used to remove the optional bottom electrode material layer, the resistive switching layer  28  and the top electrode material  30  from the topmost surface of the ILD material layer  22 . 
     Referring now to  FIG. 7 , there is illustrated the exemplary semiconductor structure of  FIG. 6  after recessing the resistive switching layer  28  and the top electrode material  30  from an upper portion of the opening  26 , while maintaining a portion of the resistive switching layer  28  and a portion of the top electrode material  30  within a lower portion of the opening  26 . The recessing of the resistive switching layer  28  and the top electrode material  30  from an upper portion of the opening  26  can be performed utilizing one or more anisotropic etching processes such as, for example, reactive ion etching. 
     The remaining portion of the resistive switching layer  28  may be referred to as a resistive switching liner  28 L and the remaining portion of the top electrode material  30  may be referred to herein as a top electrode  30 S. In this embodiment, a ReRAM device is provided in the lower portion of the opening  26  that includes an upper portion (i.e., the faceted upper surface  19 ) of the etched drain region  18 D as a bottom electrode, the resistive switching liner  28 L, and the top electrode  30 S. In some embodiments (see, for example,  FIG. 10 ), the ReRAM device includes a deposited bottom electrode material layer as the bottom electrode, the resistive switching liner  28 L, and the top electrode  30 S. 
     In the present application, the resistive switching liner  28 L is present directly beneath an entirety of the top electrode  30 S, and the resistive switching liner  28 L and the top electrode  30 S have topmost surfaces that are coplanar with each other. In embodiments in which a bottom electrode composed of a deposited conductive metal or metal nitride is formed (see, for example,  FIG. 10 ), the bottom electrode is present beneath the entirety of the resistive switching liner  28 L, and the bottom electrode, the resistive switching liner  28 L and the top electrode  30 S have topmost surfaces that are coplanar with each other. 
     Referring now to  FIG. 8 , there is illustrated the exemplary semiconductor structure of  FIG. 7  after filling in the upper portion of the opening  26  with additional ILD material and replacing the sacrificial gate structures  12  with a functional gate structure ( 32 ,  34 ). The additional ILD material is typically a same ILD material as ILD material layer  22 . The additional ILD material can be formed utilizing the technique mentioned above for forming the ILD material layer  22 . Collectively, the additional ILD material and the ILD material layer  22  may be referred to as ILD material structure  22 S. 
     The sacrificial gate structures  12  and, if present the sacrificial gate cap material  14 , are then removed utilizing one of more anisotropic etching process such as, for example, reactive ion etching. During this etch, a portion of the ILD material structure  22 S (not shown in the cross sectional views) may be removed prior to removing the sacrificial gate structures  12  and, if present the sacrificial gate cap material  14 . Gate cavities (not shown) are formed by removing the sacrificial gate structures  12  and, if present the sacrificial gate cap material  14 . A functional gate structure ( 32 ,  34 ) is then formed in the gate cavities. By “functional gate structure” it is meant a permanent gate structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields. 
     The functional gate structures may include a gate dielectric portion  32  and a gate conductor portion  34 . The gate dielectric portion  32  may include a gate dielectric material. The gate dielectric material can be an oxide, nitride, and/or oxynitride. In one example, the gate dielectric material can be a high-k material having a dielectric constant greater than silicon dioxide. Exemplary high-k dielectrics include, but are not limited to, HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , SiON, SiN x , a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. In some embodiments, a multilayered gate dielectric structure comprising different gate dielectric materials, e.g., silicon dioxide, and a high-k gate dielectric, can be formed and used as the gate dielectric portion  32 . 
     The gate dielectric material can be formed by any deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. In one embodiment of the present application, the gate dielectric material used in providing can have a thickness in a range from 1 nm to 10 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the gate dielectric material that may provide the gate dielectric portion  32 . 
     The gate conductor portion  34  may be composed of a gate conductor material. The gate conductor material can include any conductive material including, for example, doped polysilicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals, an elemental metal nitride (e.g., tungsten nitride, aluminum nitride, and titanium nitride), an elemental metal silicide (e.g., tungsten silicide, nickel silicide, and titanium silicide) or multilayered combinations thereof. In one embodiment, the gate conductor portion  34  may comprise an nFET gate metal. In another embodiment, the gate conductor portion  34  may comprise a pFET gate metal. 
     The gate conductor material can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other like deposition processes. When a metal silicide is formed, a conventional silicidation process is employed. In one embodiment, the gate conductor material can have a thickness from 50 nm to 200 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the gate conductor material. 
     The functional gate structure can be formed by providing a functional gate material stack of the gate dielectric material, and the gate conductor material. A planarization process may follow the formation of the functional gate material stack. 
     Referring now to  FIG. 9 , there is illustrated the exemplary semiconductor structure of  FIG. 8  after forming contact structures, namely a source contact structure  36 , a gate contact structure  38 , and a ReRAM contact structure  40  are formed as shown in  FIG. 9 . The various contact structures ( 36 ,  38  and  40 ) can be formed by first providing contact openings to expose a conductive region (i.e., the source region  18 S, the gate conductor portion  34 , the top electrode  30 S) of the structure. The contact openings can be formed by lithography and etching. Each contact opening is the filled with a contact metal or metal alloy. Examples of contact metals include, but are not limited to, tungsten (W), aluminum (Al), copper (Cu), or cobalt (Co). An example of a contact metal alloy is Cu—Al alloy. A planarization process may follow the filling of each contact opening with the contact metal or metal alloy. The various contact structures ( 36 ,  38 ,  40 ) are embedded in the ILD material structure  22 S. 
       FIG. 9  represents one exemplary semiconductor structure including an oxide resistive random access memory (ReRAM) device  52  co-integrated with a drain region  18 D of a field effect transistor (FET)  50 ; the FET includes a source region  18 S and a functional gate structure ( 32 ,  34 ). The ReRAM device  52  has a tip region  42  defined by a pointed cone that contacts a faceted upper surface  19  of the drain region  18 D of the FET  50 . The tip region  42  enhances the electroforming of a current conducting filament of the ReRAM device  52 . Thus, the randomness of electroforming of the current conducting filament is reduced in the ReRAM device  52  of the present application. As is shown, the ReRAM device  52  is located laterally adjacent the functional gate structure ( 32 ,  34 ) and is spaced apart from the functional gate structure ( 32 ,  34 ) by the first dielectric spacer  16  and the second dielectric spacer  20 . As is further shown, the source region  18 S and the drain region  18 D are embedded in the semiconductor substrate  10  and each has faceted sidewall surfaces. 
     Referring now to  FIG. 10 , there is illustrated another exemplary semiconductor structure of the present application including a ReRAM device  52  that includes a bottom electrode  27 S, a resistive switching liner  28 L, and a top electrode  30 S. In this embodiment, element  54 L denotes a material stack that includes the bottom electrode  27 S and the resistive switching liner  28 L. In this embodiment, the bottom electrode  27 S is composed of a deposited bottom electrode material as described above. The exemplary structure of  FIG. 10  is formed utilizing the same basic processes steps as described above and as are depicted in  FIGS. 1-9 . The exemplary structure of  FIG. 10  includes an oxide resistive random access memory (ReRAM) device  52  co-integrated with a drain region  18 D of a field effect transistor (FET)  50 . The ReRAM device  52  has a tip region  42  that contacts the faceted upper surface  19  of the drain region  18 D of the FET  50 . The tip region  42  enhances the electroforming of a current conducting filament of the ReRAM device  52 . Thus, the randomness of electroforming of the current conducting filament is reduced in the ReRAM device  52  of the present application. As is further shown, the source region  18 S and the drain region  18 D are embedded in the semiconductor substrate  10  and each has faceted sidewall surfaces. 
     While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.