Patent Publication Number: US-7583114-B2

Title: Supply voltage sensing circuit

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2006-105607, filed on Apr. 6, 2006, the entire contents of which are incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a supply voltage sensing circuit for sensing a variation in supply voltage. 
   2. Description of the Related Art 
   A supply voltage sensing circuit is a circuit that senses a supply voltage and provides a detection signal when the supply voltage rises to a certain range and when it lowers to a certain range. The supply voltage sensing circuit is used in an SRAM, a DRAM, an EEPROM, an FeRAM (Ferroelectric Random Access Memory) and the like that require fast detection of a variation in supply voltage. 
   One of conventionally proposed supply voltage sensing circuits includes a p-type MOS transistor, which has a source supplied with the supply voltage, a drain grounded via a current control resistor, and a gate supplied with an output voltage from a divider circuit that resistance-divides the supply voltage. In this arrangement, when the supply voltage rises above a desired value, the p-type MOS transistor turns on and senses a rise in the supply voltage. On the other hand, when the supply voltage lowers below a desired value, the p-type MOS transistor turns off and senses a drop in the supply voltage. 
   In the supply voltage circuit thus configured, if the supply voltage drops slower compared to the RC time constant of the current control resistor and thus the RC time constant is negligible, the drop in the supply voltage can be sensed without problems. If the supply voltage drops faster compared to the RC time constant, a problem arises because the drop therein can not be sensed. Namely, when the supply voltage drops faster, the potential difference between the gate and the source of a p-type MOS transistor lowers below the threshold voltage to turn off the transistor. Even in such the case, the RC time constant prevents a drop in drain voltage. This is not transmitted to the following stage circuit and causes a problem because a drop in the supply voltage cannot be sensed. 
   To solve such the problem, JP 2002-300020A ( FIG. 1  and paragraphs 0032-0044) discloses a supply voltage sensing circuit as known. The circuit includes a p-type MOS transistor having a source given the supply voltage via a RC delay circuit. In the sensing circuit, when the supply voltage drops, the gate voltage lowers while the source voltage lowers with delay because of the presence of the RC delay circuit. Therefore, when the supply voltage lowers below a certain value, the p-type MOS transistor turns on. Sensing the p-type MOS transistor being turned on enables a drop in the supply voltage to be sensed. As for a rise in the supply voltage, the above conventional circuit is separately provided in parallel for detection. In the circuit of JP 2002-300020A, the CR time constant of the current control resistor connected between the drain of the p-type MOS transistor and the ground terminal cannot affect thereon and accordingly a fast drop in the supply voltage can be sensed as well. 
   In the circuit of JP 2002-300020A, however, the threshold voltage on the p-type MOS transistor has a temperature dependence. Due to variance factors including such the temperature dependence, a problem arises because an output timing of a power-off signal to sense the drop in the supply voltage varies. 
   SUMMARY OF THE INVENTION 
   In one aspect the present invention provides a supply voltage sensing circuit sensing a variation in a supply voltage, comprising: an internal power supply circuit providing a constant output voltage regardless of the supply voltage; a delay circuit generating a delayed signal by delaying a variation in the output voltage; a divider circuit generating a divided voltage by dividing the supply voltage at a certain division ratio; a p-type MOS transistor having a source given the delayed signal and a gate given the divided voltage and turning on when the supply voltage lowers below a certain value; and an output circuit providing an output voltage based on a drain voltage on the p-type MOS transistor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows an arrangement of a supply voltage sensing circuit  1  according to a first embodiment of the present invention. 
       FIG. 2  shows an application example of the supply voltage sensing circuit  1  of  FIG. 1 . 
       FIG. 3  is a circuit diagram illustrative of an arrangement example of the bandgap reference circuit  14  of  FIG. 1 . 
       FIG. 4  is a circuit diagram illustrative of another arrangement example of the bandgap reference circuit  14  of  FIG. 1 . 
       FIG. 5  is a graph illustrative of operation of the supply voltage sensing circuit  1  of the first embodiment. 
       FIG. 6  is a graph illustrative of operation of the supply voltage sensing circuit  1  of the first embodiment 1. 
       FIG. 7  shows an arrangement of a supply voltage sensing circuit  1 B according to a second embodiment of the present invention. 
       FIG. 8  illustrates an arrangement of a ferroelectric memory of a TC parallel unit series-connection type. 
       FIG. 9  is a graph illustrative of operation of the supply voltage sensing circuit  1 B of the second embodiment. 
       FIG. 10  is a graph illustrative of operation of the supply voltage sensing circuit  1 B of the second embodiment. 
   

   DETAILED DESCRIPTION OF THE EMBODIMENTS 
   The embodiments of the present invention will now be described in detail below with reference to the drawings. 
   First Embodiment 
     FIG. 1  shows an arrangement of a supply voltage sensing circuit  1  according to a first embodiment of the present invention. The supply voltage sensing circuit  1  is a circuit to sense that a supply voltage Vcc drops below a certain value, and includes a p-type MOS transistor  11 . The p-type MOS transistor  11  is a normally-off transistor having a negative threshold voltage Vth. 
   The p-type MOS transistor  11  has a gate, which is connected to a resistance divider circuit  12  including a resistor  12 A (resistance value of R 4 ) and a resistor  12 B (resistance value of R 5 ) serially connected. The gate of the p-type MOS transistor  11  is connected to a node  3  between the resistors  12 A and  12 B. The other end of the resistor R 4  is given the supply voltage VDD to be detected while the other end of the resistor R 5  is given the ground potential Vss. Thus, the node  3  or the gate of the p-type MOS transistor  11  is supplied with a potential VDD×R 5 /(R 4 +R 5 ). 
   The p-type MOS transistor  11  has a source, which is connected to a RC delay circuit  13  including a resistor R 7  and a capacitor C 7 . A bandgap reference circuit (BGR circuit)  14  serving as an internal power supply circuit is connected upstream to the delay circuit. The BGR circuit  14  has an input terminal, which is connected to a diode-connected, n-type MOS transistor  15 . 
   The transistor  15  has a drain, which is given the supply voltage VDD to be detected. Between the source and the ground potential Vss, a stabilizing capacitor  16  is connected to pool charges thereon. The BGR circuit  14  has characteristic values of its various internal elements that are set such that the output voltage lowers as the temperature elevates, that is, the circuit has a negative temperature characteristic. In consideration of the temperature characteristic of the p-type MOS transistor  11  as to the absolute value of the threshold voltage Vth, the negative temperature characteristic of the BGR circuit  14  is determined to have a gradient so that it can cancel out variations in the temperature characteristic of the p-type MOS transistor  11 . 
   Between the drain of the p-type MOS transistor  11  and the ground terminal, a current control resistor  17  (resistance value of R 6 ) is connected to limit the current flowing in the p-type MOS transistor  11  when it is turned on. A node  4  on the drain side of the current control resistor  17  is connected to an inverter circuit (output circuit), which includes two-stage inverters  181 ,  182  and provides an output signal or a power-off signal PWOFF indicating that the supply voltage VDD drops below a certain value. 
   Sensing that the supply voltage VDD rises above a certain value may be executed in a supply voltage sensing circuit  1 A separately used as shown in  FIG. 2 . A NOR gate  20  is arranged to provide a logical sum of the detection signal from the circuit  1 A and the detection signal from the circuit  1  shown in  FIG. 1  to sense both the rise and the drop in the supply voltage. The supply voltage sensing circuit  1 A itself is publicly known in the above JP2002-300020A and the like and has components similar to the supply voltage sensing circuit of  FIG. 1  except that a p-type MOS transistor  1 A has a source directly connected to the supply voltage VDD. Therefore, such components are given a subscript “A” in  FIG. 2  and omitted from the following detailed description. 
   A specific arrangement of the BGR circuit  14  of  FIG. 1  is shown in  FIG. 3 . The BGR circuit  14  has a first current path including a resistor  141  (resistance value of R 1 ) and a diode  142  serially connected between the output terminal  14 B and the ground potential Vss. It also has a second current path including a resistor  143  (resistance value of R 2 ), a resistor  144  (resistance value of R 3 ) and a diode  145  serially connected between the output terminal  14 B and the ground potential Vss as well. The diode  145  has an N-fold area compared to the diode  142 . 
   The BGR circuit  14  includes an operational amplifier  146 , and an n-type MOS transistor  147 . The operational amplifier  146  has anon-inverting input terminal connected to anode between the resistors  143  and  144  and an inverting input terminal connected to a node between the resistor  141  and the diode  142 . The operational amplifier  146  compares an input voltage Va on the inverting input terminal with an input voltage Vb on the non-inverting input terminal and controls the output voltage such that both input voltages become equal. 
   The p-type MOS transistor  147  has a gate connected to the output terminal of the operational amplifier  146 . The p-type MOS transistor  147  has a drain used as an input terminal  14 A of the BGR circuit  14  and supplied with an input voltage Vin, and a source connected to the output terminal  14 B. 
   In  FIG. 2 , when the current in the first current path and the current in the second current path are denoted with I 1  and I 2 , respectively, then I 1  and I 2  can be represented by:
 
 I 1 =Is ×exp( q×Vf 1/( k·T ))
 
 I 2 =N×Is ×exp( q×Vf 2/( k·T ))  [Expression 1]
 
where Is denotes a backward-direction saturation current in the diode  142 ,  145 ; Vf 1  and Vf 2  denote respective forward-direction voltages of the diodes  142 ,  145 ; k denotes the Boltzmann constant; T denotes an absolute temperature; and q denotes the charge on an electron.
 
   A replacement of VT=k×T/q yields the following. 
   
     
       
         
           
             
               
                 
                   
                     
                       
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   In this case, I 1 ×R 1 =I 2 ×R 2  can be established in the BGR circuit  14 . Therefore, a potential difference dVf applied between both terminals of the resistor  144  (resistance value of R 3 ) can be represented by:
 
 dVf=Vf 1 −Vf 2 =VT ×Log( N×R 2 /R 1)  [Expression 3]
 
   A potential difference applied between both terminals of the resistor  141  (resistance value of R 1 ) and resistor  143  (resistance value of R 2 ) can be represented by R 2 /R 3 ×dVf. Therefore, the output voltage VBGR from the BGR circuit  14  can be represented by: 
   
     
       
         
           
             
               
                 
                   
                     
                       VBGR 
                       = 
                       
                         
                           Vf 
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   Vf 1  has a temperature characteristic of −2 [mV/° C.] while VT has a temperature characteristic of +0.086 [mV/° C.]. Accordingly, depending on the selection of the resistances R 1 , R 2 , R 3 , the gradient of the temperature characteristic curve of the output voltage VGBR can be adjusted either positive or negative. In this embodiment, the temperature characteristic of the p-type MOS transistor  11  as to the absolute value of the threshold voltage Vth has a negative gradient (the absolute value of the threshold voltage Vth decreases as the temperature elevates) as described above. In consideration of this fact, the resistances R 1 , R 2 , R 3  are adjusted such that the output voltage VBGR from the BGR circuit  14  has a negative temperature characteristic. 
   Another specific arrangement of the BGR circuit  14  is shown in  FIG. 4 . The BGR circuit  14  includes an operational amplifier  151 . Between the input terminal  14 A and the ground potential Vss, a first current path is formed including a p-type MOS transistor  152 , a diode  153 , and a resistor  154  (resistance value of R 1 ) connected in parallel with the diode. 
   In parallel with the first current path, a second current path is formed including a p-type MOS transistor  155 , a resistor  156  (resistance value of R 3 ), N pieces of parallel-connected diodes  157 , and a resistor  158  (resistance value of R 2 ) connected in parallel with the resistor  156  and diodes  157 . In parallel with the first and second current paths, a third current path is similarly formed including a p-type MOS transistor  159 , and a resistor  160  (resistance value of R 4 ). 
   The transistors  152 ,  155  and  159  are equally sized transistors, which have gates commonly connected to the output terminal of the operational amplifier  151  to form a current mirror circuit. This circuit allows currents I 1 , I 2 , and I 3  (I 1 =I 2 =I 3 ) with the same value to flow in the first, second and third current paths. As a result, the potential on a node N 1  between the transistor  152  and the diode  153  and the potential on a node N 2  between the transistor  155  and the resistor  156  (V+, V−) become equal. A node between the transistor  159  and the resistor  160  is used as an output terminal to provide the output voltage VBGR from the BGR circuit  14 . 
   The potential on the node N 1  is fed to the inverting input terminal of the operational amplifier  151  and the potential on the node N 2  is fed to the non-inverting input terminal of the operational amplifier  151 . 
   In this case, the current flowing in the diode  153  is denoted with I 1 A while the current flowing in the resistor  154  is denoted with I 1 B (I 1 =I 1 A+I 1 B). The current flowing in the resistor  156  is denoted with I 2 A while the current flowing in the diode  158  is denoted with I 2 B (I 2 =I 2 A+I 2 B). When R 1 =R 2 , the following expression is derived.
 
I1A=I1B
 
I2A=I2B
 
 V−=VF 1
 
 V+=Vf 2 +dVf  
 
 dVf=Vf 1 −Vf 2  [Expression 5]
 
   The voltage across both ends of the resistor  156  is dVf. Accordingly, the following is given.
 
 I 2 A=dVf/R 3
 
 I 2 B=Vf 1 /R 2  [Expression 6]
 
Therefore, the following can be represented.
 
 I 2 =I 2 A+I 2 B=Vf 1 /R 2 +dVf/R 3  [Expression 7]
 
Therefore, the following can represent the output voltage VGBR.
 
   
     
       
         
           
             
               
                 
                   
                     
                       VBGR 
                       = 
                       
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   Vf 1  has a temperature characteristic of −2 [mV/° C.] while VT has a temperature characteristic of +0.086 [mV/° C.]. Accordingly, depending on the selection of the resistances R 2 , R 3 , the gradient of the temperature characteristic curve of the output voltage VGBR can be adjusted either positive or negative. In accordance with the negative gradient of the temperature characteristic of the p-type MOS transistor  11  as to the absolute value of the threshold voltage Vth, the resistances R 2 , R 3  can be adjusted also in the circuit of  FIG. 4  such that the output voltage VBGR from the BGR circuit  14  has a negative temperature characteristic. 
   Operation of the supply voltage sensing circuit  1  according to the first embodiment is described with reference to  FIGS. 5 and 6 .  FIG. 5  shows an example of variations in voltage on the each node in response to variations in the supply voltage VDD at a temperature T=T 1 .  FIG. 6  shows an example of variations in voltage on the each node in response to variations in the supply voltage VDD at a temperature T=T 2  higher than T 1 . 
   In the case of the temperature T=T 1  ( FIG. 5 ), the supply voltage VDD starts at time t 1  to rise gradually from zero and reaches a steady-state value at time t 2 . On the other hand, the output voltage VBGR from the BGR circuit  14  stabilizes at a constant value VBGR 1 . In response to this variation, the voltage on the node  5  reaches VBGR 1  after a delay of the time constant of the RC delay circuit  13 . As the resistance divider circuit  12  has a division ratio of R 5 /(R 4 +R 5 ), the voltage on the node  3  varies along a slow gradient due to the division ratio during the rise/drop in VDD and reaches R 5 /(R 4 +R 5 )×VDD at the time of steady state. Sensing that the supply voltage VDD rises above a certain value is executed in another supply voltage sensing circuit  1 A shown in  FIG. 2 . 
   As the supply voltage VDD starts at time t 3  to lower gradually from the steady-state value, the voltage on the node  3  also starts to lower almost at the same time. However, the input voltage Vin is kept at near VDD for a while by the stabilizing capacitor  16 . Accordingly, the output voltage VBGR from the BGR circuit  14  remains almost VBGR 1  subsequently and the voltage on the node  5  is held at about VBGR 1 . 
   In this way, the voltage on the node  5  is held at VBGR 1  while the voltage on the node  3  lowers almost in synchronization with the decrease in the supply voltage. Accordingly, when the potential difference between both voltages at time t 4  exceeds the absolute value |Vth| of the threshold voltage Vth 1  at the temperature T=T 1  of the p-type MOS transistor  11 , the p-type MOS transistor  11  turns on. Thus, current flows in the current control resistor  17  and charges up a capacitive component thereof to raise the potential on the node  4  fast accordingly. As a result, the power-off signal PWOFF switches near time t 4  from “L” to “H”, which indicates that a drop in the supply voltage VDD below a certain value is sensed. 
   If the temperature T is equal to T 2  higher than T 1  (T 2  &gt;T 1 ), the absolute value of the threshold voltage Vth 2  of the p-type MOS transistor  11  becomes equal to |Vth 2 | (&lt;|Vth 1 |), which is lower than |Vth 1 | at T=T 1 . Therefore, if the voltage on the node  5  at T=T 1  is equal to that at T=T 2 , the output timing of the power-off signal PWOFF varies and prevents accurate supply voltage sensing. 
   In the present embodiment, therefore, the resistances of the internal resistors (such as the resistors  141 ,  143 ,  144  in  FIG. 3 ) are set as described above such that the output voltage VBGR from the BGR circuit  14  has a negative temperature characteristic. Namely, compared to the output voltage VBGR 1  from the BGR circuit  14  at T=T 1 , the output voltage VBGR 2  at T=T 2  is made lower. It is suitable if a difference between VBGR 1  and VBGR 2  meets the difference between the thresholds of the p-type MOS transistor  11 . Thus, the present embodiment makes it possible to cause no variation in the output timing of the power-off signal based on the temperature dependence and to provide the power-off signal in the presence of a constant supply voltage. Accordingly, it is possible to execute accurate supply voltage sensing. 
   Second Embodiment 
   An arrangement of a supply voltage sensing circuit  1 B according to a second embodiment of the present invention is described next with reference to  FIG. 7 . The same components in  FIG. 7  as those in  FIG. 1  are denoted with the same reference numerals and omitted from the following duplicated description. 
   In the supply voltage sensing circuit  1 B of  FIG. 7 , an n-type, stepdown transistor  22 , which is used in an internal power supply circuit inside a semiconductor memory device, is provided, instead of the BGR circuit  14 , to configure an internal power supply circuit. The stepdown transistor  22  has a drain supplied with a boosted voltage VPP, which is applied, for example, to a word line of a ferroelectric memory. 
   On the other hand, the gate thereof is supplied with a gate potential NGAA on a source-follower stepdown transistor that generates an internal supply potential VAA for use in a ferroelectric memory, while the source thereof is connected to the RC delay circuit  13 . The boosted voltage VPP can be generated in a booster circuit, not shown, by boosting the supply voltage VDD. It is an example of another voltage that varies with delay compared to a variation in the supply voltage VDD. 
     FIG. 8  shows an arrangement of a memory unit in a ferroelectric memory of a TC parallel unit series-connection type. This ferroelectric memory configures a memory unit structured such that a plurality (eight in  FIG. 8 ) of memory cells Mj are serially connected. One memory cell Mj is structured to include one transistor Tj and one ferroelectric capacitor Cj connected in parallel. 
   In the ferroelectric memory, all word lines WLj are kept at the boosted voltage VPP (“H”) in standby state to hold both ends of the ferroelectric capacitor Cj short-circuited. In this state, the word line of a selected memory cell is set at 0 V (“L”) and a plate line PL is driven to perform reading and writing. As all word lines WLj are kept at the boosted voltage VPP in standby state, and the ferroelectric memory has a large gate capacitance, the boosted voltage VPP can be retained at a higher voltage for a while even after the supply voltage VDD sharply drops. 
   This arrangement allows the boosted voltage VPP to fall slowly even if the supply voltage VDD sharply drops, and the variation is further delayed through the RC delay circuit  13 . Therefore, the potential on the node  8  can be maintained almost constant even after the sharp drop in VDD. 
   The circuit of this embodiment comprises a switching circuit  21 . The switching unit  21  includes a plurality of transfer gates SWj (two in  FIG. 7 : SW 1 , SW 2 ). Each transfer gate SWj is connected to a node between a plurality of resistors (three in  FIG. 7 : R 8 , R 9 , R 10 ) in the resistance divider circuit  12 . The transfer gates SW 1 , SW 2  are switching-controlled by a switching controller  23 . 
   Trimming is required to vary the internal supply voltage VAA. Therefore, trimming is also required to vary the gate voltage NGAA on the source-follower stepdown transistor for generating the internal supply potential VAA. If the gate voltage NGAA varies through trimming, the potential on the source (node  8 ) of the p-type MOS transistor  11  also varies, and inevitably the potential on the node  6  used to turn on the p-type MOS transistor varies. 
   Accordingly, in order to turn on the p-type MOS transistor  11  in the presence of the same supply voltage VDD at all times even if the gate voltage NGAA is varied through trimming, the switching unit  21  must be switched in response to the variation in the gate voltage NGAA after trimming. Namely, the switching controller  23  senses the level of the gate voltage NGAA and, in accordance with the sensed result, selectively turns on any one of the transfer gates SWi and turns off the others. Namely, the switching unit  21  and the switching controller  23  together serve as a division ratio changing circuit that changes the division ratio of the resistance divider circuit  12 . 
   In accordance with this arrangement, when the gate voltage NGAA is high, only the transfer gate SW 1  is turned on to apply a higher voltage to the node  6 . On the other hand, when the gate voltage NGAA is low, only the transfer gate SW 2  is turned on to lower the voltage on the node  6 . This makes it possible to achieve an almost constant potential difference between the nodes  6  and  8  without depending on the level of the gate voltage NGAA as shown in  FIGS. 9 and 10 . It is also made possible to achieve a constant detection timing of the drop in the supply voltage VDD, and to provide the power-off signal in the presence of the same supply voltage. In this example, the application to the ferroelectric memory of the TC parallel unit series-connection type is described for facilitation of understanding though the circuit is also applicable to other semiconductor memory devices, of course. For example, the boosted voltage VPP may be a boosted voltage that is supplied to a decoder in a flash EEPROM. 
   The voltage applied to the drain of the stepdown transistor  22  is not required to be the boosted voltage VPP but may be one if it varies in relation to the supply voltage VDD to be sensed and the variation has a delay relative to the variation in VDD. 
   The embodiments of the present invention have been described above though the present invention is not limited to these embodiments but rather can be given various modifications, replacements, deletions and additions without departing from the spirit and scope of the invention. For example, the switching unit  21  described in the second embodiment ( FIG. 7 ) is not only applied to the case of  FIG. 7  that uses the stepdown transistor  22  as the internal power supply circuit. It is also applicable to supply voltage sensing circuits that use other internal power supply circuits.