Patent Publication Number: US-7215670-B1

Title: Hardware acceleration for reassembly of message packets in a universal serial bus peripheral device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit, under 35 U.S.C. §119(e)(1), of U.S. Provisional Application No. 60/166,893 (TI-29870PS), filed Nov. 22, 1999, and incorporated herein by this reference. 

   STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
   Not applicable. 
   BACKGROUND OF THE INVENTION 
   This invention is in the field of data communications, and is more specifically directed to Asynchronous Transfer Mode (ATM) data communications by way of a Universal Serial Bus (USB) peripheral device. 
   The present embodiments relate to universal serial bus (“USB”) systems, and are more particularly directed to increasing the rate and flexibility of communications between a USB host and a peripheral. 
   USB is a recently-developed technology established by a joint effort of various companies, resulting in an adopted standard set forth in  Universal Serial Bus Specification, Revision  1.1, Sep. 23, 1998, which is hereby incorporated herein by reference. The USB Specification is directed to a goal of improving the user-friendliness of various aspects of computers and the peripheral devices typically used with such computers, and to this end governs many aspects about USB systems. In a USB system, peripheral devices are coupled to the host personal computer or workstation computer in a tiered-star topology over the USB bus; in this topology, external devices are physically connected to the USB bus by way of a standardized USB cable, rather than by way of specialized serial and parallel ports. The USB bus is mastered by a USB host, resident in the host personal computer or workstation, with the USB peripherals operating as slave devices on that bus. 
   The USB technology provides significant advantages to the computer system user, including the ability to connect up to 127 peripheral devices, in a “daisy-chain” tiered-star topology, to a single USB port on the host computer. The USB technology also permits the user to connect and disconnect USB peripheral devices to or from the USB system without requiring system power-down, and generally with little or no configuration input required from the user. This capability provides considerable flexibility and possible cost reduction in comparison to many contemporary systems, particularly those which can only support one peripheral device per port. USB systems also can easily integrate various functions such as data, voice, and video, into the system through a single serial-data transfer protocol, without requiring add-on cards and the availability of their associated mainboard slots. Additionally, the master-slave arrangement permits the relatively high processing capacity of the host computer to perform and manage much of the data processing required for the peripheral function. 
   By way of further background, various techniques have been developed in the field of digital communications for routing messages among the nodes of a network. One such approach is referred to as packet-based data communications, in which certain network nodes operate as concentrators to receive portions of messages, referred to as packets, from the sending units. These packets may be stored at the concentrator, and are then routed to a destination concentrator to which the receiving unit indicated by the packet address is coupled. The size of the packet refers to the maximum upper limit of information that can be communicated between concentrators (i.e., between the store and forward nodes), and is typically a portion of a message or file. Each packet includes header information relating to the source and destination network addresses, permitting proper routing of the message packet. Packet switching with short length packets ensures that routing paths are not unduly dominated by long individual messages, and thus reduces transmission delay in the store-and-forward nodes. Packet-based data communications technology has enabled communications to be carried out at high data rates, up to and exceeding hundreds of megabits per second. 
   A well-known fast packet switching protocol, which combines the efficiency of packet switching with the predictability of circuit switching, is Asynchronous Transfer Mode (generally referred to as “ATM”). According to ATM protocols, message packets are subdivided into cells of fixed length and organization, regardless of message length or data type (i.e., voice, data, or video). Each ATM cell is composed of fifty-three bytes, five of which are dedicated to the header and the remaining forty-eight of which serve as the payload. According to this protocol, ATM packets are made up of a number of fixed-length ATM cells; for the example of AAL5 protocol, the number of ATM cells in a packet is currently limited to a maximum of 1366 cells, corresponding to a maximum payload of 64 k bytes. The fixed size of the ATM cells enables packet switching to be implemented in hardware, as opposed to software, resulting in transmission speeds in the gigabits-per-second range. In addition, the switching of cells rather than packets permits scalable user access to the network, from a few Mbps to several Gbps, as appropriate to the application. 
   The ATM technology is particularly well suited for communications among computers over the worldwide and public medium commonly referred to as the Internet, because of the flexibility and recoverability provided by this packet-based approach. A relatively recent technology by way of which remote, home, or small office workstations can now connect to the Internet is referred to in the art as digital subscriber loop (“DSL”). DSL refers generically to a public network technology that delivers relatively high bandwidth, far greater than current voice modem data rates, over conventional telephone company copper wiring at limited distances. As such, DSL modulator/demodulators (“modems”) are now available for implementation with workstations and personal computers for ATM communications to and from the Internet, with data rates provided by DSL modems ranging from on the order of 500 Kbps to 18 Mbps or higher, according to conventional techniques. 
   Given the benefits of USB peripherals discussed above, USB-based DSL modems are now being introduced into the marketplace. Conventional USB-based DSL modems rely upon the host workstation or personal computer to perform such operations as segmentation of message data to be transmitted into ATM cells, and also the reassembly of received ATM cells into the message. This reliance upon the host processor is typical for USB-based peripherals, as noted above. 
   BRIEF SUMMARY OF THE INVENTION 
   It is therefore an object of the present invention to provide a USB-based modem that more efficiently utilizes the USB bus for the communication of data than in conventional USB modems. 
   It is a further object of the present invention to provide such a modem in which a portion of the reassembly of ATM cells into messages is performed in the modem, thus reducing the amount of ATM overhead that is transmitted over the USB bus. 
   It is a further object of the present invention to provide such a modem for use in Digital Subscriber Line (DSL) communications. 
   It is a further object of the present invention to provide such a modem that may also communicate over the voice-band. 
   Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings. 
   The present invention may be implemented into a USB peripheral device, in which ATM acceleration logic is embodied within the USB interface. ATM cells that are received by the USB peripheral are read by the ATM acceleration logic, and ATM connection information is interrogated thereby, from the ATM cell header, to determine the appropriate connection to which the ATM cells are directed in the host system. The data payload portion of the received ATM cells are then written into a bulk USB endpoint in shared memory of the USB interface, corresponding to the indicated connection information; the ATM cell header information is not forwarded to the USB endpoint. The host system is then able to retrieve the incoming ATM packets from the USB endpoint, by way of bulk USB packets, in an efficient manner. Additionally, cyclic redundancy check calculations may be performed by the ATM acceleration logic to ease the computational burden of the host system. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
       FIG. 1   a  is an electrical diagram, in block form, of a USB-based system into which the preferred embodiment of the present invention is incorporated. 
       FIG. 1   b  is an electrical diagram, in block form, of the system of  FIG. 1   a , illustrating the USB interconnections among the various elements therein. 
       FIG. 2  is an electrical diagram, in block form, of a USB-based peripheral device according to the preferred embodiment of the present invention. 
       FIG. 3  is an electrical diagram, in block form, of an exemplary architecture of the USB-to-DSP (digital signal processor) interface in the device of  FIG. 2  according to the preferred embodiment of the present invention. 
       FIG. 4  is an electrical diagram, in block form, of the digital signal processor interface and ATM acceleration logic in the USB-to-DSP interface of  FIG. 3 , according to the preferred embodiment of the invention. 
       FIG. 5  is an electrical diagram, in block form, of an ATM receive controller in the logic of  FIG. 3 , constructed according to the preferred embodiment of the invention. 
       FIG. 6  is a flow diagram illustrating the operation of the reassembly logic in the ATM receive controller of  FIG. 5  according to the preferred embodiment of the invention. 
       FIG. 7  is a flow diagram illustrating the operation of the bus logic in the ATM receive controller of  FIG. 5  according to the preferred embodiment of the invention. 
       FIG. 8  is a flow diagram illustrating the operation of the reassembly logic in the ATM receive controller of  FIG. 5  in processing an OAM packet according to the preferred embodiment of the invention. 
       FIG. 9  is a flow diagram illustrating the operation of the reassembly logic in the ATM receive controller of  FIG. 5  in processing an ATM cell according to the preferred embodiment of the invention. 
       FIG. 10  is an electrical diagram, in block form, of an ATM transmit controller in the logic of  FIG. 3 , constructed according to the preferred embodiment of the invention. 
       FIG. 11  is a memory space diagram illustrating the organization of various ATM packets that may be handled by the ATM transmit controller of the preferred embodiment of the invention. 
       FIG. 12  is a flow diagram illustrating the operation of the segmentation logic in the ATM transmit controller of  FIG. 10  according to the preferred embodiment of the invention. 
       FIG. 13  is a flow diagram illustrating the operation of the segmentation logic in the ATM transmit controller of  FIG. 10  in generating and transmitting an ATM cell header according to the preferred embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   As will be apparent from the following description, the present invention may be beneficially used in connection with many different alternative system implementations. It is therefore contemplated that those skilled in the art having reference to this description will be readily able to implement the present invention in many alternative realizations, over a wide range of electronic functions and systems. As such, it will be understood that the following description is provided by way of example only. 
     FIG. 1   a  illustrates an exemplary USB system  10  into which the preferred embodiments may be implemented. By way of introduction, system  10  includes aspects known in the USB art and further includes the preferred embodiments. System  10  includes a USB host  12  which, in the present example, is a personal computer (“PC”). USB host  12  includes a motherboard (not separately shown) which communicates with USB software that automatically loads device drivers in a manner that is typically transparent to the user of the PC, where the drivers support the remaining devices external from USB host  12 . 
   As further detailed later in connection with  FIG. 1   b , for purposes of USB communications, USB peripheral devices may be directly connected to USB host  12 , or may be indirectly coupled to USB host  12  through other USB devices that are directly connected to USB host  12 , as shown in  FIG. 1   a . More particularly, in system  10  external modem  14 , a monitor  16 , and a keyboard  18  are directly connected to USB ports of USB host. In contrast, the remaining devices in system  10  are coupled to USB host  12  by way of one of these directly-connected USB devices. For example, speakers  20   L  and  20   R  and microphone  22  are connected to USB host  12  by way of USB connections to monitor  16 , which in turn has a USB connection to host  12 ; it should be noted that, typically, video data to be displayed by monitor  16  will not be communicated thereto by host  12  over a USB connection, but will instead be communicated over a separate standard video connection (not shown in  FIGS. 1   a  and  1   b ). Similarly, mouse  24  and scanner  26  are coupled to USB host  12  via USB connections to keyboard  18 , which is a USB device connected to a USB port of host  12 . While each of the illustrated peripheral devices in system  10  is shown as a USB device, it is of course to be understood that, alternatively, only a subset of these devices may be USB devices. 
   The operation of system  10  includes numerous aspects known in both the general-purpose computer and USB arts. As to the former, a detailed discussion is not presented in this document because the preferred embodiments are particularly directed to USB aspects; thus, briefly it may be appreciated that each of the devices in system  10  operates to perform the known functionality for such a device and with respect to the PC forming USB host  12 , such as data input from keyboard  18 , mouse  24 , scanner  26 , and microphone  22 , data communication to and from a remote location by modem  14 , and data presentation by monitor  16  and speakers  20   L  and  20   R . The USB operation of system  10  is detailed throughout the remainder of this document. 
     FIG. 1   b  illustrates an electrical diagram of the USB hierarchy of connections among the devices of  FIG. 1   a . As shown by the legend toward the right of  FIG. 1   b , each device in the upper half of  FIG. 1   b  is referred to in the art as a hub and, thus, the hubs in system  12  include USB host  12  (i.e., the PC), keyboard  18 , and monitor  16 . In a USB system, the system includes a single USB host (e.g., host  12 ) that also serves as a hub, where this and any other hub in system  10  is a wiring concentrator for connecting to one or more other USB devices. To facilitate such connections, each hub (other than the USB host) includes at least one upstream port through which it is connected either directly to the USB host or to another hub, and one or more downstream ports to which other USB devices may be connected, all connections being achieved using USB cables. Each USB cable includes four conductors, two for providing power to a USB device if the device does not obtain power via some other source, and two for data communications. The connectors on each end of a USB cable differ from one another so as to ensure that a proper end of the cable is connected in the upstream direction toward USB host  12  while ensuring that the opposing end is connected in the downstream direction away from USB host  12 . Looking to the connections of the hubs in system  10 , USB host  12  is connected from a port  12   1 , via a USB cable C 1 , to a port  18   1  of keyboard  18 , and from a port  12   2 , via a USB cable C 2 , to a port  16   1  of monitor  16 . Typically, in modem USB computer systems, monitor  16  serves as a USB hub in parallel with its primary function as a display device, and receives its video display signals from host  12  over a direct video display connection and not over the USB connection. As also shown by the  FIG. 1   b  legend, each device in the lower half of the Figure is referred to in the art as a function, although such devices are sometimes referred to (perhaps less precisely) as peripherals. A function is a USB device that provides a capability to the host. In the present example, therefore, the functions include microphone  22 , speakers  20 , modem  14 , mouse  24 , and scanner  26 . In addition, however, a USB device functioning as a hub may also itself serve as a function; for example, keyboard  18  is an example of a device that is both a hub and a USB function. Each of the functions is also connected via a corresponding USB cable to a hub. For example, a cable C 3  connects modem  14 , via a port  14   1 , to USB host  12  via its port  12   3 . The remaining cable connections in system  10  will be readily ascertainable by one skilled in the art. 
   In its general operation, USB host  12  operates in a master/slave relationship relative to each of the functions, where USB host  12  always serves as the master and each of the functions always serves as a slave. Further in this regard, USB host  12  includes a serial interface engine (“SIE”) (not separately shown) that is typically incorporated into a USB controller also included with the host so that USB host  12  may communicate serial information between itself and the functions. Particularly, the serial data passes along the data conductors in the cables shown, where typically the communications at the data conductor level are referred to as USB communications along a USB bus. To facilitate its master operations, USB host  12  generally includes three software levels which, from highest to lowest are: (1) a host controller driver which links whatever specific type of device that is chosen as a USB host controller to the remaining USB software structure; (2) USB system software that communicates between the host controller driver and client software; and (3) client software which is associated with a particular function and is often provided by the manufacturer of the function so that USB host  12  may communicate with and receive the functionality of that function. Given its software levels, USB host  12  monitors the network created by the connections of system  10 , and detects when a function is added thereto (or removed therefrom). More particularly, upon attachment of a function to the network, USB host  12  as master detects the added function, and its communication speed, in response to a resistance change due to one or more resistors connected inside the function and which thereby change the resistive load when a USB cable thereto. In response, USB host  12  electrically configures a port connection to the newly-added function. Next, USB host  12  interrogates the function in connection with a four-step process, referred to in the art as enumeration, to identify information about the function and to assign a unique address thereto. Also in connection with this process, or thereafter, USB host  12  may configure the function. Finally, USB host  12  loads the appropriate driver to communicate with the function, and thereafter USB communications may proceed according to a USB protocol discussed below. 
   The USB protocol divides the time of communication along the USB bus into one millisecond frames. During each frame the bandwidth is shared among all devices connected to the USB system, and each frame is subdivided into one or more packets. The use and length of packets are constrained according to various criteria set forth in the USB Specification. In general, USB host  12 , as master, begins each frame by communicating a start of frame (“SOF”) packet. Thereafter, communications during the frame occur according to a token protocol, in which a transaction between host and a function occurs in response to the issuance of a token followed by an order of response. Thus, USB host  12  sends a token packet which includes an address directed to one of the functions, as well as an indication of whether the data to be communicated is a read (i.e., from the addressed function to USB host  12 ) or a write (i.e., from USB host  12  to the addressed function). The address specifically identifies what is referred to in the USB art as an endpoint (or “device endpoint”), which is a uniquely addressable portion of a USB function that is the source or sink of information in a communication flow between the USB host and the function. The endpoint gets its name from the fact that it is typically a location in a first-in-first-out (“FIFO”) memory space of the function, so for data written to the function it is written to the end, or endpoint, of a write FIFO whereas for data read from the function it is read from the end, or endpoint, of a read FIFO. Returning to the token operation, when the token reaches the addressed function, that function decodes the address and identifies itself as the destination. Next, one or more data packets are communicated along the network, where the destination function acts accordingly (i.e., either receives or transmits the data). Finally, once the data communication is complete, the recipient of the data issues a handshake packet to indicate whether the transmission was successful. This handshake indication may be either a positive acknowledgment (“ACK”) or a negative acknowledgment (“NAK”). Further, in the case of a function as a data recipient, the function may provide a handshake indication of a STALL where either the intended endpoint is halted or a control request is not supported. 
   The USB Specification ( Universal Serial Bus Specification, Revision  1.1, Sep. 23, 1998) requires that USB data packet transfers fall into one of four data categories: (1) control transfers; (2) bulk data transfers; (3) interrupt data transfers; and (4) isochronous data transfers. In the prior art, each of these transfer types is performed to a like kind of endpoint. Further, in the art and as a logical construct, each such communication is referred to as along a pipe to the endpoint. For example, if a host communicates an isochronous data packet to a function, then it more particularly communicates it to an isochronous endpoint in the function and is said to be along a pipe to that endpoint. Similarly, if a host communicates a bulk data packet to a function, then it communicates it along a pipe to a bulk data endpoint in the function. One skilled in the art will appreciate the application of this terminology to the remaining data transfer and corresponding endpoint types. Finally, while not fully detailed herein, the USB Specification places different constraints on different ones of the data transfer types, such as the number of bytes permitted per packet and the number of packet per frame or for a given number of frames. Some of these constraints are discussed later in this document. 
   Control transfers allow USB host  12  to access different parts of a function, to obtain information about the function, and to change the behavior of the function. More particularly, control transfers support configuration, command, and status type communication flows between client software in USB host  12  and a function corresponding to that software. For example, control data is used by USB host  12  to configure a function when it is first attached to system  10 . Further, each USB function is required to implement an IN control pipe, with a corresponding endpoint  0 , as a default control pipe which is used by the USB system software to write control information to the function. Each USB device is also required to have an OUT control pipe (and endpoint) to output control information. The default IN control pipe provides host  12  with access to information pertaining to a USB function such as its configuration, status, and control information. Further, the USB Specification defines requests that can be used to manipulate the state of a function, and descriptors are also defined that can be used to contain different information on the device. Finally, a function optionally may provide endpoints for additional control pipes for other implementation needs, such as to accommodate implementation-specific functionality provided via customer software on USB host  12 . 
   Bulk transfers permit communication of relatively large data groups where the data may be communicated at highly variable times and the transfer may use any available bandwidth. Bulk transfers are unidirectional and, thus, a given transfer may be only from host to function or function to host; thus, if both directions are desired, then a function must have both an IN bulk endpoint and an OUT bulk endpoint or, alternatively, two pipes may be associated with the same endpoint. Examples of bulk transfers include the communication of data to a printer (not shown), or receipt of data collected by scanner  26 . Error detection is included in hardware and implements a limited number of retries for bulk data transfers so as to greatly enhance the likelihood of successful data delivery. However, a tradeoff involved with the communication of bulk data is the possibility of latency. Lastly, the amount of bandwidth per USB frame allotted to bulk data may vary depending on other bus demands arising from other data transfers by either the same or a different function. 
   Interrupt transfers are relatively small transfers to or from a USB function. Such data may be presented for transfer by a function at any time, but because USB host  12  is a master it cannot be interrupted. Instead, USB host  12  periodically polls each function and, in response to a notification that interrupt data has been posted, USB host  12  retrieves the interrupt information. Interrupt data typically consists of event notification, characters, or coordinates that are organized as one or more bytes. For example, interrupt data may be presented by keyboard  18  or mouse  24  (or some other pointing device). 
   Isochronous data is continuous and real-time in creation, communication, and use. Isochronous transfers are unidirectional and, thus, can be only from host to function or function to host; thus, if both directions are desired, then a function must have both an IN isochronous endpoint and an OUT isochronous endpoint (or two pipes associated with the same endpoint). Timing-related information is implied by the steady rate at which isochronous data is received and transferred. Isochronous data must be delivered at the rate received to maintain its timing. Isochronous data also may be sensitive to delivery delays. For isochronous pipes, the bandwidth required is typically based upon the sampling characteristics of the associated function. The latency required is related to the buffering available at each endpoint. A typical example of isochronous data would be real-time video information received by modem  14 . Due to its real-time nature, the delivery; rate of isochronous data must be maintained or else drop-outs in the data stream will occur. Isochronous communications are not corrected such as by hardware retries, with the benefit being that timely delivery is ensured (assuming no other latency, such as in software) with the drawback being that data communication may be lossy. In practice, the bit error rate of USB is predicted to be relatively small so that applications using the types of data being communicated as isochronous data are not appreciably affected in a negative manner. Lastly, USB isochronous data streams are allocated a dedicated portion of USB bandwidth to ensure that data can be delivered at the desired rate. 
     FIG. 2  illustrates a block diagram of a function card  28  according to the preferred embodiment. Function card  28  represents an electrical computer-type circuit board in general, and in  FIG. 2  the blocks shown are those implemented in the preferred manner of forming modem  14  of  FIGS. 1   a  and  1   b ; thus, function card  28  is intended to be enclosed within the external housing of modem  14  and connected electrically to the USB bus as known generally in the art. Further, while function card  28  includes various inventive aspects detailed below in the context of modem  14 , one skilled in the art should appreciate that various of these aspects may apply to any one or more of the other functions in system  10 . Lastly, by way of example and also for further introduction, in the preferred embodiment modem  14  is a hybrid modem serving both voice-band (e.g., V.90) and DSL communications. 
   Turning to certain connections of function card  28 , the USB bus is shown to the left of  FIG. 2 , and corresponds to the two data conductors of a USB cable, for example the data conductors of cable C 3  where function card  28  corresponds to modem  14 . The USB bus is coupled to a USB interface device  30  which, as detailed below, includes various other functional blocks that are formed using one or more integrated circuits. USB interface device  30  is further connected to host port interface bus HPIF which is further connected to a digital signal processor (“DSP”)  32  or some other desirable processing circuit. By way of example, DSP  32  may be one of various types of DSPs commercially available from Texas Instruments Incorporated, such as the TMS320C6201, TMS320C6202, or TMS320C6205. In the case of DSP devices such as the TMS320C6201 that have an external host port interface (“HPIF”), bus HPIF corresponds to such a host port interface bus, which is in this case a sixteen bit bus. On the other hand, DSP devices such as the TMS320C6202 have an Xbus (extended bus) interface that supports various operational modes, one of which is a thirty-two bit host port interface mode. Accordingly, where DSP  32  is implemented by way of a device having an Xbus interface, bus HPIF corresponds to an Xbus bus operating in the host port interface mode. 
   DSP  32  is further connected to two different analog front end (“AFE”) circuits, namely, a V.90 (i.e., voice-band) AFE  34  and an xDSL AFE  36 . Each AFE  34  and  36  is connected to a physical connector  38  for connecting to the communications facility (not shown) over which modem communications are carried out. 
   According to the preferred embodiment of the invention, in which function card  28  corresponds to a hybrid modem, DSP  32  includes some amount of on-chip memory useful for the storage of communication data that has been received or that is about to be transmitted. In particular, as shown in  FIG. 2 , a portion of this on-chip memory of DSP  32  corresponds to receive FIFO  33 , which is a first-in-first-out buffer within which data received from AFE  34  or  36 , as the case may be, are stored prior to forwarding to USB interface device  30  and host  12 . In the case of Asynchronous Transfer Mode (ATM) communications, receive FIFO  33  stores incoming ATM cells. Conversely, another portion of the on-chip memory of DSP  32  corresponds to transmit FIFO  35 , within which data (e.g., ATM cells) are buffered after receipt from host  12  via USB interface device  30 , prior to transmission via the appropriate one of AFEs  34 ,  36 . 
   Returning to USB interface device  30  and examining the blocks therein, the USB bus connects within USB interface device  30  to a USB interface module  40 . USB interface module  40  is further connected to a bus B. Also connected to bus B is a USB-to-DSP controller  42 , which is further connected to bus HPIF. Lastly, USB interface device  30  includes a shared memory  44  connected to bus B, and that is given its name because it is accessible by both USB interface module  40  and USB-to-DSP controller  42  via bus B. Further in this regard, shared memory  44  includes various locations reserved as USB endpoints. 
   A brief description of the operation of function card  28  is now presented, with further details presented later in connection with a more detailed examination of certain of the blocks therein. In general, function card  28  interfaces at both the physical and protocol levels with the USB system and, hence, permits communications between function card  28  and USB host  12 . USB host  12  communicates data along the USB bus to function card  28 , and that information is received by USB interface module  40  and processed according to principles known in the USB art. Further in this respect, USB interface module  40  may write transfers of any of the four above-described types to the endpoints in shared memory  44 , where such information is written via bus B. In addition, USB-to-DSP controller  42  also may access the endpoints in shared memory  44  via bus B. Accordingly, given this access, data written to the endpoints from USB interface module  40  may be read by DSP  32  via bus HPIF or, alternatively, data written by DSP  32  to bus HPIF may be transferred by USB-to-DSP controller  42  to the endpoints in shared memory  32 . Further in this regard, DSP  32  is programmed and configured to provide the general functionality supported as a USB function which, for the present example, is a modem functionality given that card  28  is associated with modem  14 . Moreover, DSP  32  is programmed in this respect to support both voice and xDSL communications, and the two AFEs  34  and  36  provide electrical interfaces to and from DSP  32  further in this regard. DSP  32  also may be programmed to communicate with respect to USB-to-DSP controller  42  in various manners according to the preferred embodiments, as will be discussed below. 
   Referring now to  FIG. 3 , an exemplary architecture of USB interface device  30  in modem  14  of  FIG. 2 , according to the preferred embodiment of the invention, will now be described. Of course, USB interface device  30  may be constructed according to any one of a number of architectures and arrangements. As such, it is to be understood that the exemplary architecture illustrated in  FIG. 3  and described herein is presented by way of example only. 
   USB interface device  30  of  FIG. 3  includes functions similar to those provided by the TUSB3200 USB peripheral interface devices available from Texas Instruments Incorporated, and includes some common architectural features therewith. In this regard, USB interface device  30  includes microcontroller unit (MCU)  100 , which may be a standard 8052 microcontroller core. MCU  100  is in communication with various memory resources over bus B, including program read-only memory (ROM)  102 , and random access memory (RAM) banks  104 ,  106 . RAM bank  104  is utilized primarily as code space that may be loaded from USB host  12  over the USB bus, or alternatively from another device over another one of the ports provided in USB interface device  30 . As will be described in further detail hereinbelow, USB endpoint buffers reside within synchronous RAM bank  106 ; in this sense, RAM  106  serves as shared memory  44  as shown in  FIG. 2 . MCU  100 , as well as the other synchronous functions of USB interface device  30 , are clocked at the appropriate clock rates by phase-locked loop (PLL) and adaptive clock generator (ACG)  110 , which generates various frequencies divided down from a reference clock generated by oscillator  108  according to the frequency set by external crystal  109 . PLL and ACG  110  preferably provides clocks suitable for supporting the available USB synchronization modes, including asynchronous, synchronous, and adaptive modes for isochronous endpoints. 
   For USB communications with USB host  12 , USB interface device  30  includes USB transceiver  112 , which preferably supports full speed (12 Mb/sec) data transfers, and includes a differential input receiver, a differential output driver, and two single ended input buffers. USB transceiver  112  is coupled to USB serial interface engine (SIE)  114 , which manages the USB packet protocol requirements for data transmitted and received by USB interface device  30  over the USB bus. In general, SIE  114  decodes packets received over the USB bus to validate and identify the packet identifier (PID), and generates the correct PID for packets to be transmitted over the USB bus. Other receive functions performed by SIE  114  include cyclic redundancy check (CRC) verification, and serial-to-parallel conversion; for transmit, SIE generates the CRC value and also effects parallel-to-serial conversion. SIE  114  bidirectionally communicates with USB buffer manager (UBM)  116 , which controls reads and writes of data from and to the appropriate USB endpoint buffers in RAM  104 ,  106 . In this regard, UBM  116  decodes the USB function address in received packets to determine whether the packet is in fact addressed to USB interface device  30  itself, as well as decoding the endpoint address contained in the received packet (which may include a polling packet from USB host  12 ). Suspend and resume logic  117  is also provided for detecting suspend and resume conditions on the USB bus, and for controlling SIE  114  accordingly. 
   Other various functions are also provided within USB interface device  30 . Inter-IC (I 2 C) controller  122  is coupled to bus B, and supports communications to and from other integrated circuits over a two-wire serial connection; for example, code RAM  104  may be loaded from such an external integrated circuit over the I 2 C port, under the control of I 2 C controller  122 . General purpose port logic  124  interfaces bus B to general purpose parallel input/output ports, numbering two in this example. Timers  126  provide one or more timer functions for controlling the operation of USB interface device  30 . Reset and interrupt logic  128  monitors various interrupt and reset conditions, to provide interrupt and reset control for MCU  100 . Additionally, extra internal memory is provided by asynchronous RAM  130 , which is externally accessible, for example to DSP  32  by way of a dedicated RAM interface (and thus permitting reads and writes in a manner independently from and asynchronously with the USB functionality of USB interface device  30 ). 
   In addition to the USB interface functions described above, which are substantially common with the TUSB3200 USB peripheral interface devices available from Texas Instruments Incorporated and which effectively correspond to USB interface module  40  of  FIG. 2 , USB interface device  30  according to the preferred embodiment of the invention includes DSP interface and ATM acceleration logic  120 . DSP interface and ATM acceleration logic  120  processes data received from USB host  12  over the USB bus for application to DSP  32  by way of VBUS-to-HPIF bridge  118 , and conversely processes data received from DSP  32  before transmission to USB host  12  over the USB bus. The construction and operation of DSP interface and ATM acceleration logic  120  will be described in further detail hereinbelow. VBUS-to-HPIF bridge  118  supports reads and writes to on-chip memory of DSP  32  in either a sixteen bit or thirty-two bit mode. Referring back to  FIG. 2 , DSP interface and ATM acceleration logic  120 , in combination with VBUS-to-HPIF bridge  118 , implement USB-to-DSP controller  42  within USB interface device  30 . 
   Referring now to  FIG. 4 , the construction of DSP interface and ATM acceleration logic  120  according to the preferred embodiment of the present invention will now be described. As shown in  FIG. 4 , multiple controllers within DSP interface and ATM acceleration logic  120  are coupled to bus B ( FIG. 3 ). According to this embodiment of the invention, in which USB interface device  30  is implemented into modem  14 , DSP interface and ATM acceleration logic  120  includes ATM transmit controller  132  and ATM receive controller  134 , each of which is coupled between bus B and controller  140 , and are utilized to carry out ATM communications processing, including such functions as segmentation and reassembly, respectively. The operation of ATM transmit controller  132  and ATM receive controller  134  will be described in further detail hereinbelow, relative to the preferred embodiment of the invention. Host interface controller  135  is bidirectionally coupled between bus B and controller  140 , while code overlay controller  136  unidirectionally communicates data (corresponding to program instructions for DSP  32 ) from bus B to controller  140 . According to the preferred embodiment of the invention, each of controllers  132 ,  134 ,  135 ,  136  includes an interface to MCU  100  ( FIG. 3 ), by way of which controllers  132 ,  134 ,  135 ,  136  are configured to point to the corresponding assigned USB endpoint buffers in shared memory  44  (e.g., in RAM  106  of the implementation of  FIG. 3 ). 
   Controller  140  arbitrates access by controllers  132 ,  134 ,  135 ,  136  to bus VBus (which appears as a “virtual” bus to devices external to USB interface device  30 ), and further permits access to VBUS-to-HPIF bridge  118  and internal registers  138 , as slaves on bus VBus. Specifically, in response to one of controllers  132 ,  134 ,  135 ,  136  issuing a request to master bus VBus, controller  140  operates to grant access to bus VBus according to a corresponding bus protocol, after arbitration among competing bus requests. The bank of internal registers  138  also communicate with controller  140 , and resides as a slave on bus VBus, for storing configuration information for DSP interface and ATM acceleration logic  120  and its functional modules. As noted above, endpoint buffer information is preferably configured internally to each of controllers  132 ,  134 ,  135 ,  136 ; the configuration information stored by internal registers  138  includes such other configuration and status information as appropriate for the operation of DSP interface and ATM acceleration logic  120 , for example in the manner described hereinbelow. 
   VBUS-to-HPIF bridge  118  operates effectively as a bridge between the bus connected to DSP  32  and internal bus VBus which, as noted above, is accessible to controllers  132 ,  134 ,  135 ,  136 . For example, if the interface from USB interface device  30  to DSP  32  is by way of its host-port interface (HPIF), such as incorporated into the TMS320C6201 digital signal processor (DSP) available from Texas Instruments Incorporated, VBUS-to-HPIF bridge  118  operates effectively as a bridge to that interface, formatting and translating the communicated data signals from those on bus VBus into a format appropriate for the bus protocol of the host-port interface. 
   ATM Cell Reassembly 
   As noted above relative to  FIGS. 2 and 3 , modem  14  in system  10  according to the preferred embodiment of the invention provides a USB-based DSL modem, over which ATM packets may be transmitted and received. According to the preferred embodiment of the invention, ATM packets are received by modem  14  and are reassembled in USB interface device  30  to a significant extent, thus relieving host  12  from performing a large portion of the computationally intensive reassembly operations, which are conventionally performed by host software. Specifically, it is contemplated that USB interface device  30  is able to efficiently perform the ATM reassembly operations of VPI/VCI lookup, OAM cell filtering, and CRC check. Additionally, according to the preferred embodiment of the invention, USB interface device  30  is able to receive ATM cells, in their fifty-three byte form with five bytes of header, and to forward only the payload portion of the received cells over the USB bus. The efficiency of USB communication is thus improved not only by not transmitting the ATM headers thereover, but also by concatenating the forty-eight byte payloads of adjacent ATM cells into sixty-four byte USB packets, thus greatly improving the ratio of effective data to protocol overhead communicated over the USB bus. Additionally, because the USB interface device reassembles ATM packets directly into host memory by way of USB endpoints, and then notifies the host of the completion of the reassembly of a packet, no on-chip memory is required for the USB interface device beyond the USB endpoint FIFOs, thus enabling the implementation of the present invention into relatively low cost peripheral devices. 
   Referring now to  FIG. 5 , the construction of ATM receive controller  134  according to the preferred embodiment of the present invention will now be described in detail. Of course, while the preferred implementation of ATM receive controller  134  is illustrated in  FIG. 5  by way of example, it is contemplated that variations in the construction and architecture may be utilized by those skilled in the art having reference to this specification within the scope of the present invention. 
   As shown in  FIG. 5 , and as discussed above relative to  FIG. 4 , ATM receive controller  134  is connected to bus B in USB interface device  30 . According to the preferred embodiment of the invention, ATM receive controller  134  is associated with particular USB endpoints resident in shared memory  44 . The particular memory addresses of these endpoints are stored in configuration registers  52  of ATM receive controller  134 , written thereto by MCU  100 . For control purposes, completion endpoint  51   0  is a bulk endpoint that is associated with ATM receive controller  134 . According to this exemplary embodiment of the invention, ATM receive controller  134  is capable of handling multiple ATM connections simultaneously. In this example, three endpoints  51   2 ,  51   3 ,  51   4  in shared memory  44  are accessible to ATM receive controller  134 , to which ATM payload corresponding to three virtual connections (VCIs) may be written. Filter endpoint  51   1  is also accessible by ATM receive controller  134 , and is configurable to receive Operation and Maintenance (OAM) cells; alternatively, endpoint  51   1  may be configured to receive ATM payload for an additional VCI (e.g., VCI 0 ), in which case ATM receive controller  134  supports four virtual connections. According to this preferred embodiment of the present invention, each of endpoints  51   1 ,  51   2 ,  51   3 ,  51   4  is a bulk USB endpoint. Bulk USB endpoints  51   1 ,  51   2 ,  51   3 ,  51   4  are each preferably implemented as at least two sixty-four byte buffers arranged according to a conventional FIFO scheme to permit substantially continuous access, such as a “Ping-Pong” arrangement of a pair of buffers, or an elastic FIFO if three or more buffers are provided. Alternatively, some or all of endpoints  51  may be isochronous endpoints, if latency is an issue. In any case, endpoints  51  in shared memory  44  are much smaller in capacity than would be required for the storage of a maximum size (64 k byte) ATM packet, as the packet reassembly according to the preferred embodiment of the invention is effectively made into host memory by way of these endpoints  51 , rather than into memory within USB interface device  30 . 
   According to the preferred embodiment of the invention, the operational logic of ATM receive controller  134  is provided by way of three state machines, namely receive state machine  50 , reassembly state machine  60 , and VBus state machine  70 . Each of state machines  50 ,  60 ,  70  is preferably realized by way of sequential logic, suitable for performing their respective functions as will be described hereinbelow. In this regard, receive state machine  50  controls the data communication to endpoints  51  over bus B, reassembly state machine  60  controls the performing of various ATM reassembly functions as will be described hereinbelow, and VBus state machine  70  controls the issuing of bus requests from, and receipt of bus grant signals by, receive ATM controller  134 , as well as the communication of data from bus VBus. It is contemplated that those skilled in the art will be readily able to implement the appropriate logic for carrying out these functions, from the description of their operation as set forth hereinbelow. 
   As noted above, receive state machine  50  controls the data communication to endpoints  51  over bus B, specifically by receiving data bytes from byte buffers  58  via multiplexer  56  and by applying the bytes to bus B in combination with the appropriate memory address for the corresponding endpoint  51  in shared memory  44 . In this regard, receive state machine  50  accesses configuration registers  52  that contain the endpoint memory addresses, as noted above. Receive state machine  50  is enabled and otherwise controlled by the state of bits set by MCU  100  in control/status registers  53 ; receive state machine  50  can also set status flags in registers  53  for response by MCU  100 , for example to initiate exception handling by MCU  100 . As evident from  FIG. 5 , each of four byte buffers  58  stores one byte of a thirty-two bit data word, and provides its stored contents to multiplexer  56  and thus to receive state machine  50 . Receive state machine  50  is also in communication with current buffer pointer  54  by way of which the appropriate buffer in the FIFO arrangement of the corresponding endpoint in shared memory  44  is accessed, and with buffer byte counter  55  that maintains a byte count for that buffer, as used in carrying out a handshaking protocol with USB buffer management circuitry (e.g., UBM  116  of  FIG. 3 ). 
   Reassembly state machine  60 , according to the preferred embodiment of the invention, controls various ATM reassembly functions that are performed by receive ATM controller  134  in USB interface device  30 ; as noted above, these reassembly operations are performed by the USB host, according to software routines, in conventional USB-based systems. These reassembly functions include calculation of CRC checksums (CRC-10 for OAM cells, and CRC-32 for AAL5 packets) as performed by CRC logic  64 . Forwarding of received data is controlled by reassembly state machine  60  according to information stored in DMA table  66 . DMA table  66  is a table of entries (e.g., four entries), each for storing information regarding a current ATM connection being processed by receive ATM controller  134 . Each entry of DMA table  66  includes an identifier of the endpoint  51  in shared memory  44  associated with the connection, identification of the type of cells being processed, and also status flags (error, overflow, etc.) associated with the current packet for that connection. DMA table  66  also includes, for each of its multiple entries, a field for storing partial CRC-32 calculation results for the packet. Reassembly state machine  60  is also in communication with VPI/VCI look-up table  68 , which includes an entry that stores, for each valid connection, an index into DMA table  66 ; as such, reassembly state machine  60  operates in combination with VPI/VCI look-up table  68  to determine whether a received ATM packet is directed to a known connection into host  12 . ATM registers  62  are illustrated in  FIG. 5  as being in communication with reassembly state machine  60 , and include status and control information regarding the reassembly processing. 
   VBus state machine  70  is in communication with bus VBus within controller  140  ( FIG. 4 ), and handles both the generation of bus request signals to controller  140 , as well as the receipt of ATM data therefrom. The operation of VBus state machine  70  is configured by receive controller VBus registers  72 , which are preferably a subset of registers  138  residing on bus VBus as shown in  FIG. 4 . Word counter  74  and current FIFO address register  76  store the indicated information concerning the source of the received ATM data, which in this example is DSP  32  in modem  14 . In particular, current FIFO address register  76  stores a pointer into receive FIFO  33  in the on-chip memory of DSP  32 . Word counter register  74  counts the number of data words received in connection with a given packet, so that overflow conditions may be detected and handled by receive ATM controller  134 . 
   The operation of receive ATM controller  134  according to the preferred embodiment of the invention will now be described in detail relative to  FIGS. 6 through 9 . 
     FIG. 6  illustrates the operation of receive ATM controller  134 , and particularly of reassembly state machine  60  therein, in the reassembly of an ATM packet according to the preferred embodiment of the invention. As is well known in the art, ATM transmissions consist of individual cells of fifty-three bytes, with five bytes corresponding to the ATM header of the cell and with the remaining forty-eight bytes available for data (i.e., “payload”); an ATM packet, for example according to AAL5 protocol, in turn is comprised of multiple cells. According to the preferred embodiment of the invention, reassembly state machine  60  operates to effectively remove the ATM header from each received ATM cell, and to direct the payload portion of the received cell to a USB endpoint corresponding to the particular ATM connection indicated in the ATM header; other processing is also performed, as will be described herein. 
   The operation of reassembly state machine  60  begins with process  75 , in which reassembly state machine  60  causes VBus state machine  70  to poll the status of the receive FIFO buffer  33  resident in DSP  32  of modem  14 , and thus to determine whether an ATM cell has been received by DSP  32 . Decision  77  is then performed by reassembly state machine  60  to determine whether such a cell is available; if not (decision  77  is NO), poll process  75  is then repeated until such time as a cell becomes available (decision  77  is YES), in response to which control passes to process  78  for the initiation of processing for the ATM cell. 
   According to the preferred embodiment of the invention, as evident from  FIG. 5 , the various state machines  50 ,  60 ,  70  of receive ATM controller  134  can operate in parallel with one another to carry out their respective functions. In the case of VBus state machine  70 , accesses of DSP  32  via controller  140  and VBUS-to-HPIF bridge  118  ( FIG. 4 ) may be carried out in parallel with the processing of previously received ATM cells by reassembly state machine  60 .  FIG. 7  illustrates an example of the operation of VBus state machine  70  to access ATM cells from DSP  32  in response to a poll request issued by reassembly state machine  60  in process  75 . 
   The operation of VBus state machine  70  in response to poll process  75  begins with decision  91  in which VBus state machine  70  polls DSP  32  to determine whether receive FIFO  33  therein is empty. If so (decision  91  is YES), decision  91  repeats. Upon data being stored within receive FIFO  33  of DSP  32  (decision  91  is NO, as receive FIFO  33  is no longer empty), VBus state machine  70  executes process  92  to present the appropriate memory address upon bus VBus, internally within USB interface device  30 . As shown in  FIG. 7 , process  92  builds the Vbus address from the current contents of current FIFO address  76 , and includes control values and signals (e.g., length=1, Direction=READ, VBus access request=TRUE, etc.); upon grant of VBus access by controller  140  to VBus state machine  70 , VBus state machine  70  applies the VBus address and control signals to bus VBus, following which VBUS-to-HPIF bridge  118  converts the VBus address and signals into the appropriate address for accessing DSP  32 . VBus state machine  70  then executes decision  93  to determine whether bus VBus indicates that the read to DSP  32  is ready; if the read has not yet been accomplished (decision  93  is NO), VBus state machine  70  continues to wait by reexecuting decision  93 . Upon the completion of the read by DSP  32  applying the contents of receive FIFO  33 , as translated by VBUS-to-HPIF bridge  118  onto bus VBus (decision  93  is YES), VBus state machine  70  receives the data word then present on bus VBus and stores it into a buffer location for forwarding to reassembly state machine  60  as requested, in process  94 . The contents of current FIFO address register  76  is then incremented, in process  96 , and control passes back to decision  91  for polling of the state of receive FIFO  33  of DSP  32  as noted above. 
   As noted above, the data retrieval operation performed by VBus state machine  70  is performed in parallel with the continued operation of reassembly state machine  60  such as illustrated in  FIG. 6 . This parallel operation permits the forwarding and processing of data in the manner described herein, while reducing the extent to which the operation stalls to await data. Additionally, as will be noted below, this operation permits the forwarding of a leading portion of an ATM data packet to host  12  even before the entire packet has been retrieved from DSP  32 . 
   Referring back to  FIG. 6 , upon reassembly state machine  60  determining that an ATM cell is available (decision  77  is YES), reassembly state machine  60  then performs process  78  to retrieve the first four bytes of the new ATM cell. As is known in the art, these first four bytes of the five byte ATM header include connection information presented in the VPI/VCI field, as well as an indication of the type of ATM cell that is received. In process  78 , reassembly state machine  60  interrogates the information in these first four bytes in order to carry out a series of decisions and operations for processing the received cell, as will now be described. 
   In decision  79 , reassembly state machine  60  determines whether the received cell is an OAM cell. As is known in the art, an OAM cell is an “Operation and Maintenance” cell, and constitutes a single-cell message packet for communication of maintenance and configuration information regarding the ATM connection. If the received cell is an OAM cell (decision  79  is YES), control passes to process  80  in which reassembly state machine  60  processes the OAM cell, which will now be described with reference to  FIG. 8 . In this regard, it should be noted that reassembly state machine  60  may be configured to respond to decision  79  only in connection with specific classes of OAM cells. For example, only OAM cells of only one of the F4 or F5 flow types may be processed by process  80 ; alternatively, OAM cells of either class may be processed and forwarded in the manner described below. 
   According to the preferred embodiment of the invention, the execution of process  80  begins with process  200 , in which the remainder of the OAM ATM cell (specifically, the remaining forty-nine bytes) is fetched. As noted above relative to  FIG. 7  and the description of the operation of VBus state machine  70 , the fetching of cell contents is preferably performed in parallel with the operation of reassembly state machine  60 , and as such is not a separate sequentially-performed process in the strict sense, as may be suggested by  FIG. 8 . In any event, once the current ATM cell is received through process  200 , reassembly state machine  60  and receive state machine  50  forward the received cell payload to filter endpoint  51   1  of shared memory  44  in process  202 ; the retrieved ATM header need not be forwarded, as its information has been utilized in the determination of the cell type (OAM) and also the destination (filter endpoint  51   1 ), and is no longer necessary. In addition to forwarding the received cell payload, CRC logic  64  performs a ten-bit cyclic redundancy check (CRC) on the received cell payload and, in decision  203 , reassembly state machine  60  evaluates the result of the CRC-10 operation. If an error is detected (decision  203  is NO), reassembly state machine  60  sets a CRC error bit in process  204 . In either case (i.e., decision  203  is YES, or after process  204  if decision  203  is NO), reassembly state machine  60  then performs process  206  to generate an end-of-packet (EOP) notification to host  12 . As discussed above, such notifications are generally performed by way of a write to completion endpoint  51   0  in shared memory  44 . In this case, the state of the CRC error bit is forwarded to host  12  via completion endpoint  51   0 , indicating the validity of the OAM cell previously forwarded. Processing of the OAM cell is then completed, and control passes back to polling process  75  ( FIG. 6 ) to await the next received ATM cell. Host  12  will decode and respond to the OAM cell as appropriate; according to this preferred embodiment of the invention, no ATM maintenance functions are carried out by USB interface device  30 . 
   As noted above, receive state machine  50  communicates with the appropriate endpoints  51  in shared memory  44  over bus B, independently from and simultaneously with the processing being carried out by reassembly state machine  60 . In processes  202 ,  206  noted above, as well as in the other forwarding processes noted hereinbelow, receive state machine  50  operates in conjunction with multiplexer  106  and buffer byte counter  55  to receive a complete data word (i.e., the four bytes of byte buffers  58 ), and to forward the same to the appropriate buffer location indicated by the contents of current buffer pointer  54 , at the memory address for the corresponding pointer location as provided in configuration registers  52 . It is contemplated that those skilled in the art having reference to this specification will be readily able to implement this function by way of sequential logic, as noted above. 
   Referring back to  FIG. 6 , if the received cell is not an OAM cell (decision  79  is NO), the received cell then likely corresponds to an ATM cell that is part of a communication packet. Reassembly state machine  60  then performs decision  81  to evaluate whether the retrieved ATM header information indicates that the cell belongs to an ATM connection (virtual connection) that is known by USB interface device  30  and host  12 . The evaluation of decision  81  is performed by reassembly state machine  60  applying the corresponding VPI/VCI fields from the ATM cell header to VPI/VCI look-up table  68 ; if the connection is unknown, no valid index will be returned from look-up table  68  and the result of decision  81  will be NO. In this event, reassembly state machine  60  will write the value of the received VPI/VCI fields from the ATM cell header to one of ATM registers  62 , specifically a receive-unknown register therein in process  82 , will increment a counter corresponding to unknown protocol (such counter also preferably resident in ATM registers  62 ), and will initiate a flush of the remainder of this unknown connection cell from receive FIFO  33  in DSP  32 . Control then passes back to polling process  75  to await the next ATM cell. 
   If look-up table  68  returns a valid index, the connection is known and decision  81  is YES. Reassembly state machine  68  then performs process  86  to retrieve the connection information for the VPI/VCI value in the received ATM header. As noted above, ATM receive controller  134  is capable of simultaneously supporting three ATM virtual connections, via three endpoints  51   2  through  51   4 . As such, successive cells processed by reassembly state machine  60  will generally not be associated with the same packet. Accordingly, each instance of polling process  75  will simply be interrogating receive FIFO  33  in DSP  32  for any cell, rather than a received cell for a particular packet, with decision  81  and process  86  serving to associated the current cell with the correct packet and virtual connection. According to the preferred embodiment of the invention, process  86  is performed by reassembly state machine  60  retrieving endpoint information from the location of DMA table  66  to which the returned index from VPI/VCI look-up table  68  points. The retrieved connection information includes information regarding the type of packet for the connection to which the received cell belongs, the one of endpoints  51  in shared memory  44  to which the received cell is to be forwarded, as well as status information regarding the cells of the corresponding ATM packet that have been already received and processed (such status information including the length of the ATM packet so far, error and status bits, and also the partial CRC results so far). Following the retrieval of this information, reassembly state machine  60  executes process  88  to process the payload portion of the current cell, as will now be described relative to  FIG. 9 . 
   Process  88  begins with the fetching of the remainder of the received ATM cell from receive FIFO  33  of DSP  32 , as performed by VBus state machine  70  in conjunction with VBUS-to-HPIF bridge  118  in process  208 ; as noted above, process  208  may be performed in parallel with the operations of reassembly state machine  60 , and as such need not necessarily be performed as a sequential process. Reassembly state machine  60  then determines, in decision  209 , whether the current received cell is the first cell of an ATM packet. As is known in the art, the first cell of an ATM packet is not expressly indicated in the ATM cell header. Rather, it is contemplated that decision  209  is performed by testing a flag or other internal status indicator that is set in connection with the completion of the only or last cell of a previous ATM packet. For example, if the previously processed cell for the current connection was the cell at the end of a packet, this flag would be set to indicate that the next cell to be processed is necessarily the first cell of the next packet for this connection, permitting reassembly state machine  60  to properly determine whether the current cell is the first one. Alternatively, various packet data as stored in DMA table  66  for the connection may be cleared upon completion of a packet, in which case reassembly state machine  60  can determine that the current received cell is the first cell of a packet, by virtue of the invalid status information for that connection. 
   In any event, for the first cell of a packet (decision  209  is YES), reassembly state machine  60  controls CRC logic  64  to begin the CRC-32 calculation for the packet with which the current cell is associated. As known in the art, multiple-cell ATM packets, such as those corresponding to the AAL5 protocol, include a thirty-two bit cyclic redundancy check sum that is calculated over the payload of the entire packet. According to the preferred embodiment of the invention, CRC logic  64  in ATM receive controller  134  is dedicated hardware for calculating this CRC checksum (as well as the ten-bit CRC value used for single-cell OAM packets, discussed above). The partial results of CRC calculation process  210  are stored in the entry of DMA table  66  associated with the current connection. This hardware calculation is performed in parallel with the other processing of reassembly state machine  60  in processing the cells of a packet, rather than in host software as conventionally performed; as is known in the art, CRC calculations performed by general purpose programmable devices is a relatively complex process, particularly over long data streams such as multiple-cell ATM payloads. This CRC check performed in hardware according to the preferred embodiment of the invention is thus significantly more efficient than these conventional software-based approaches. 
   The processing of the first cell of the packet continues with process  212 , in which the entry of DMA table  66  corresponding to the cell count of the associated packet is set to “1”, indicating that one cell has been received so far for this packet. In process  214 , reassembly state machine  60  and receive state machine  50  forward the payload of the current received cell to the bulk endpoint  51   2  through  51   4  indicated by the connection information stated in DMA table  66 , as indexed by VPI/VCI look-up table  68 . As noted above, the forwarding of the payload to this endpoint  51  is performed by receive state machine  50  being signaled that a full data word is ready in byte buffers  58 , following which receive state machine  50  obtains access to bus B and writes the data to the corresponding endpoint in shared memory  44 . 
   As is evident from the foregoing description, these bytes correspond to the payload portion of the ATM cells, and do not include the header portion of the ATM cells, which is effectively stripped by reassembly state machine  60  (i.e., the ATM cell header is simply not forwarded by reassembly state machine  60  to byte buffers  58 ). Additionally, boundaries between ATM cells are effectively ignored in the writing of the payload to shared memory  44 , such that the payload portion of successive ATM cells in the same ATM packet are contiguously stored in shared memory  44  at the endpoint  51  corresponding to the virtual connection. These contiguous cell payloads are thus contiguously retrieved from shared memory  44  by host  12  over the USB bus. 
   As noted above, this forwarding to shared memory  44  can also be performed in parallel with the other operations of ATM receive controller  134 , including the fetching of additional cell data from DSP  32  and the processing of cells by reassembly state machine  60 , including the CRC calculation. Control then passes back to polling process  75  to await the receipt of the next ATM cell. 
   If the current received cell is not the first cell of a packet (decision  209  is NO), reassembly state machine  60  then executes decision  211  to determine whether the received cell is the cell at the end of a packet. This determination is made by examination of the ATM header for the current received cell, as is known in the art. If the received packet is not an end-of-packet cell (decision  211  is NO), control then passes to process  216 , in which CRC logic  64  is directed, by reassembly state machine  60 , to continue the CRC-32 calculation with the payload data fetched in connection with the current cell. This calculation begins with the partial CRC results for the associated connection, retrieved from DMA table  66 , and upon the completion of the partial CRC calculation for the current cell payload, this entry of DMA table  66  is then rewritten with the updated value of these intermediate results. The cell count in the corresponding entry of DMA table  66  with the current connection is incremented to reflect the processing of another cell, in process  218 . The cell payload (i.e., without the ATM header) is then forwarded to the appropriate endpoint  51 , in process  214  as described above. 
   Upon reaching the last cell in the packet (decision  211  is YES), reassembly state machine  60  then executes various steps to complete the forwarding of the packet to host  12 . According to this embodiment of the invention, a YES result returned by decision  211  passes control to process  220 , in which the cell count in the corresponding entry of DMA table  66  is incremented to reflect the receipt of another (and final) cell associated with the current packet for the corresponding connection. This final cell count value will be used in generating the end-of-packet notification, described hereinbelow. In addition, this final cell count value is retrieved by reassembly state machine  60  and compared, in decision  221 , against a maximum cell count. In this exemplary embodiment of the invention, the maximum cell count is 1366 10 , which corresponds to the 64 k byte maximum length of an ATM packet according to current standards. If the number of received cells exceeds this maximum length, one may conclude that a previous end-of-packet indicator was not detected, because of a transmission error or some other reason. In this event, some of the previously received cells that have been associated with the current packet may not properly be part of the current packet. According to the preferred embodiment of the invention, reassembly state machine  60  detects such an event by decision  221  detecting that the cell count exceeds the maximum length limit (a YES result), and by executing process  222  to set a packet overflow bit in the corresponding entry of DMA table  66  for this packet. 
   In either case (decision  221  YES or NO), reassembly state machine  60  next executes decision  225  to determine whether the current packet is an AAL5 protocol packet; this determination is made by interrogating the entry of DMA table  66  corresponding to the current packet. If the current packet is not an AAL5 packet (decision  225  is NO), control passes to process  226  for completion of the processing of the current packet by forwarding of the payload of the last cell to the appropriate endpoint  51  in process  226  (performed in cooperation with receive state machine  50  as described above). In this case, as in the case of previously-received cells, the ATM header information for this cell is not forwarded to the endpoint. Additionally, reassembly state machine  60  performs process  228  to generate an end-of-packet notification to host  12 . This notification, similarly as described above relative to  FIG. 7  for the case of OAM cell processing, involves the writing of data to endpoint  51   0  in shared memory  44 , including information regarding the packet (including at least the state of the packet overflow bit, which may have been set in process  22 ). The processing of this non-AAL5 packet, in this example, is then complete. 
   In the case of an AAL5 packet (decision  225  is YES), as typically utilized in modern ATM communications, certain trailer information is received, for analysis and forwarding following the final cell payload. Decision  227  is next executed by reassembly state machine  60  to determine if the packet length value in the AAL5 trailer has the value “0”. If so (decision  227  is YES), an error in the packet was encountered somewhere along its transmission; reassembly state machine  60  then sets an AAL5 abort bit in the status information of the entry of DMA table  66  corresponding to the current packet. Control then passes to process  226  for forwarding of the cell payload to the appropriate endpoint  51 , and to process  228  for generation of the EOP notification to host  12  (including the state of the AAL5 abort bit, as set in process  230 ). 
   If the length value of the AAL5 trailer does not indicate an abort code (decision  227  is NO), reassembly state machine  60  will then execute decision  231  to evaluate the result of the CRC-32 calculation carried out by CRC logic  64 . Upon receipt and fetching of the last cell in the packet, CRC logic  64  will have calculated the entire CRC-32 value over the payload of the multiple cells in the packet. In decision  231 , reassembly state machine  60  compares the result of the CRC calculation by CRC logic  64  with the expected (i.e., valid) value communicated as part of the last four bytes of the received cell. If the two values do not match (decision  231  is NO), an error is present in the received packet, and reassembly state machine  60  sets the CRC error bit in the entry of DMA table  66  corresponding to the current packet; in process  232 . 
   In either case (decision  231  YES or NO), control passes to process  226  for the forwarding of the cell payload to the appropriate endpoint  51  in shared memory  44 , as noted above. Reassembly state machine  60  then executes process  228  to generate the end-of-packet notification, for forwarding to completion endpoint  51   0 . This EOP notification includes various status information contained within the corresponding entry of DMA table  66  for this packet, including the clear state of the AAL5 abort bit, the state of the CRC error bit (as may have been set in process  232 ), and of course an indication that a complete packet has now been forwarded to the endpoint  51  associated with the current virtual connection. 
   Alternatively, an end-of-packet completion notification may be appended to the payload forwarded to the appropriate endpoint  51   1  through  51   4 , in which case a separate completion endpoint  51   0  need not be maintained within shared memory  44 . 
   Once the EOP notification has been written to completion endpoint  51   0 , host  12  will be notified, during its next poll of this bulk endpoint, that cells for an ATM packet are now stored in shared memory  44 , at the appropriate IN endpoint  51 . Host  12  may then begin reading the payload data stored at endpoint  51 , over the USB bus, in the form of USB packets. According to current standards, USB packets for communication with bulk endpoints are sixty-four byte packets. Referring to  FIG. 3 , serial interface engine  114  then effects the communication of the contents of RAM  106  (i.e., shared memory  44  of  FIG. 2 ) to host  12  over bus USB. Because of the arrangement of the cell payloads in shared memory  44  (or RAM  106 ) as a contiguous data block, without ATM headers, the fifty-three byte format of ATM cells need not be followed in the communication of the payload data to host  12  over bus USB; instead, the data may be forwarded in full sixty-four byte USB packets. 
   As is evident from the foregoing description, the construction and operation of ATM receive controller  134  within USB interface device  30  provides important advantages in the efficiency of ATM communications. One such advantage is a significant improvement in the efficiency and utilization of the USB bus in the communication of the ATM data. The processing performed by ATM receive controller  134 , particularly in associating the ATM packet with a specific endpoint, permits the five-byte ATM header to be effectively stripped from the ATM cells prior to forwarding over bus USB, thus reducing the amount of overhead transmitted over bus USB and improving the bus efficiency by on the order of ten percent. Improved bus utilization is also provided by the ability to use the entire maximum sixty-four byte USB packet for payload communication, as the ATM cell boundaries need not be maintained over the USB bus because of the processing provided by ATM receive controller  134 ; in contrast, conventional systems in which the fifty-three byte ATM cells are communicated over the USB bus necessarily include eleven vacant bytes within each USB packet (indeed, sixteen bytes having no payload), in order to preserve the USB cell boundaries. Furthermore, the amount of memory required in the USB interface device is greatly reduced from that in conventional interface devices, as the ATM packets are reassembled directly into the memory of the host via the USB endpoints. As a result, the shared memory in the USB interface device need not be sufficiently large to store an entire maximum-size ATM packet; rather, the packet reassembly may be fully handled through the endpoint FIFO buffers. Processing efficiency is also provided by way of the present invention, since computationally intensive operations such as CRC calculation may be performed in hardware in the USB interface device, rather than in software at the host, which is necessarily less efficient and cumbersome; the offloading of the reassembly function to the USB interface device also dramatically simplifies the development and installation of the ATM communications driver at the host. 
   ATM Cell Segmentation 
   USB-based DSL modem  14  in system  10  according to the preferred embodiment of the invention not only handles received ATM packets, but of course also provides the functionality of transmission, in ATM packets, of data generated by host  12 . According to the preferred embodiment of the invention, much of the processing required for the segmentation of ATM packets is carried out in USB interface device  30 , thus relieving host  12  from performing a significant portion of the computationally intensive segmentation operations, as now executed by host software in conventional USB-based DSL modems. Specifically, it is contemplated that USB interface device  30  efficiently performs the ATM segmentation of sixty-four byte USB packets into the fifty-three byte standard ATM cells, including generation of the ATM header for each cell; USB interface device  30  also receives and forwards the necessary “padding” of the ATM cells to fill the fifty-three byte cells, and also calculates and appends of the appropriate cyclic redundancy check (CRC) value to the packet. USB communication is thus made more efficient by not requiring the host to forward each copy of the ATM header over the USB bus, and by concatenating payload data into the maximum size sixty-four byte USB packets, thus greatly reducing the amount of null bytes over the USB bus. 
   Referring now to  FIG. 10 , the construction of ATM transmit controller  132  according to the preferred embodiment of the invention will now be described. As shown in  FIG. 10 , ATM transmit controller  132  is primarily controlled by state machines, namely transmit state machine  250 , segmentation state machine  260 , and VBus state machine  270 , each of which is preferably implemented by sequential logic. It is contemplated that those skilled in the art, having reference to this specification, will be readily able to implement state machines  250 ,  260 ,  270  to perform the functions described herein, and in a manner suitable for particular realizations. 
   Transmit state machine  250  is coupled to bus B in USB interface device  30 , for controlling communication with transmit endpoint  240  in shared memory  44  (which, in the exemplary realization of  FIG. 3 , resides in RAM  106 ). According to the preferred embodiment of the present invention, both ATM header information and also the ATM packet payload are written into transmit endpoint  240  by host  12 ; alternatively, separate header and payload endpoints may be established in shared memory  44 , if desired. According to this embodiment of the invention, transmit endpoint  240  is a bulk USB endpoint, implemented by one or more sixty-four byte buffers in a conventional FIFO manner (e.g., a pair of “Ping-Pong” buffers or an elastic FIFO arrangement). Transmit state machine  250  is in communication with endpoint configuration register  242 , which is written by MCU  100  with the memory address of endpoint  240  in shared memory  44 . Additionally, transmit state machine  250  is controlled by the contents of current buffer pointer  244 , which indicates the FIFO buffer at endpoint  240  from which data is being retrieved, and by buffer byte counter  246  which indicates the byte position within the accessed FIFO buffer, as used in handshaking operations with USB buffer management circuitry, as noted above. 
   Segmentation state machine  260  receives data bytes from transmit state machine  250 , and performs segmentation operations as appropriate for the particular packet upon such bytes. The bytes processed by segmentation state machine  260  are forwarded, by way of demultiplexer  266 , to the appropriate one of byte buffers  268 . The operation of segmentation state machine  260 , which will be described in further detail hereinbelow, is carried out in combination with header register  252 , packet length register  254 , and packet type register  256 , each of which stores results useful in the generation of ATM headers. Segmentation state machine  250  also operates in cooperation with CRC logic  258 , which performs CRC calculations to generate the CRC filler of the transmitted ATM packets. Additionally, cell counter  262  counts the number of ATM cells being generated by segmentation state machine  260  for the current packet, and byte counter  264  counts the number of bytes within the current ATM cell that have been processed by segmentation state machine  250 . 
   As noted above, demultiplexer  266  receives each byte processed by segmentation state machine  260 , and forwards it to the appropriate one of byte buffers  268 . The contents of byte registers  268  are simultaneously received, as a thirty-two bit data word, by VBus state machine  270 . In combination with word counter  274  and transmit configuration registers  272 , VBus state machine  270  operates to apply the data word to; bus VBus, and thus to transmit FIFO  35  in DSP  32  ( FIG. 2 ) over bus VBus and via VBUS-to-HPIF bridge  118  (if present, as in  FIG. 3 ). 
   The operation of transmitting ATM communications begins, of course, with host  12  generating the message to be transmitted. According to the preferred embodiment of the invention, host  12  generates the data packet from its own data processing operations, and also generates an ATM header and appropriate control information for the overall packet; as segmentation is not performed by host  12  according to this embodiment of the invention, the message data is not segmented into ATM cells by host  12 , nor is an ATM header generated for each such ATM cell. Host  12  formats this packet into sixty-four byte USB packets, and transmits the USB packet containing the ATM header and control information over the USB bus to transmit endpoint  240  in shared memory  44 , followed in the same packet by the payload, or message data, which are also written to transmit endpoint  240 . Host  12  will, of course, control the scheduling of these USB packets over the USB. Furthermore, to avoid error according to the preferred embodiment of the invention, host  12  is to communicate only one ATM packet over the USB bus at a time, and ATM transmit controller  132  is to process that one ATM packet, (i.e., only the one virtual connection) at a time; it is of course contemplated that multiple instances of ATM transmit controller  132 , and associated endpoints  240 , may be implemented in order to handle multiple connections, if desired. 
     FIG. 11  illustrates the arrangement of the packet formats (i.e., packet definition units, or PDUs) that may be transmitted from host  12  to USB interface device  30 , and that may be segmented by ATM transmit controller  132  according to the preferred embodiment of the present invention. AAL5 PDU  230 , as shown in  FIG. 11 , includes a seven-byte header, followed by up to 64 k bytes of payload data. A pad portion of up to 47 bytes follows the payload, and simply contains a number of null bytes sufficient to fill out a forty-eight byte boundary, including a two-byte control field, a two-byte length field, and a four byte CRC-32 filler that all follow the payload, and not including the seven-byte header. OAM PDU  232  includes a seven-byte header, followed by payload data of forty-six bytes and six bits, which in turn is followed by the ten-bit CRC-10 checksum value. These AAL5 and OAM cells are well-known in the art. 
   Two other PDUs that may be handled by ATM transmit controller  132  according to the preferred embodiment of the invention include a PTI-based Null-AAL shown as PDU  234  of  FIG. 11 , and transparent packet PDU  236  which is useful in generic streaming applications. According to this embodiment of the invention, PTI Null PDU  234  consists simply of a seven-byte header, and up to 64 k bytes of payload data, with up to forty-seven bytes of pad to fill out the forty-eight byte boundaries; as such, PTI Null PDU  234  is sufficiently generic to be used, in connection with downstream software, to support AAL1, AAL2, and AAL3/4 protocols. Transparent PDU  236  is simply a fifty-three byte packet with seven bytes of header and forty-eight bytes of data, similar to a conventional ATM cell. 
   Referring now to  FIG. 12 , the operation of ATM transmit controller  132 , and particularly segmentation state machine  260  therein, in performing the segmentation of the ATM packet generated by host  12  into ATM cells for transmission via modem  14 . The operation of ATM transmit controller  132  begins with decision  281 , in which segmentation state machine  260  interrogates the state of byte buffers  268  to determine whether a location is available to which to forward another byte of packet data. If not (decision  281  is YES because byte buffers  268  are full), segmentation state machine  260  must wait until VBus state machine  270  reads the data word from the contents of byte buffers  268 , following which decision  281  will return a NO result, permitting control to pass to decision  283 . 
   As noted above, VBus state machine  270  writes the transmit data words to transmit FIFO  35  of DSP  32  independently from, and thus simultaneously with, the operation of segmentation state machine  260  described herein. This operation by VBus state machine  270  consists of requesting access to bus VBus and, upon receiving a grant of such access, reading the contents of byte buffers  268  as a transmit data word, and then presenting the transmit data word to bus VBus; as such, VBus state machine  270  operates substantially similarly with VBus state machine  70  of ATM receive controller  134  described hereinabove, except writing data to bus VBus rather than reading data therefrom. Similarly as described above, VBus state machine  70  maintains the current transmit FIFO address in its current FIFO address  276 , so that the proper memory address may be presented in combination with the data word to be transmitted. VBus-to-HPIF bridge  118  then translates, or “bridges”, this address and data information into the HPIF format comprehendible by DSP  32 . Once VBus state machine  270  clears byte buffers  268 , as noted above, decision  281  will return a NO result to indicate that space is available in byte buffers  268  for the next byte to be processed. 
   In decision  283 , segmentation state machine  260  in combination with transmit state machine  250  determine whether new data is present at endpoints  240 , either at header endpoint  240   0  or data endpoint  240   1 . If not (decision  283  is NO), segmentation state machine  260  must wait for such data to appear. Upon data being written to endpoints  240  from host  12  for an ATM packet, decision  283  will return a YES result, and segmentation state machine  260  proceeds to execution of decision  285 . 
   In decision  285 , segmentation state machine  260  determines whether the ATM header for the current packet has yet been configured. Upon receiving the initial packet information, typically the ATM header and control information at endpoint  240   0 , the ATM header will not have yet been configured. In this case (decision  285  is NO), segmentation state machine  260  copies the received ATM header and control information into its registers  252 ,  254 ,  256 , shown in  FIG. 10 . Specifically, the first four bytes of the seven-byte ATM header information read from endpoint  240   0 , corresponding to the GFC, VPI, and VCI connection information, are stored in header register  252 , the fifth and sixth bytes corresponding to the length of the packet are written into length register  254 , and the seventh byte corresponding to the packet type is written into packet type register  256 . Following the storing of this information in registers  252 ,  254 ,  256 , segmentation state machine  260  retains the information necessary for generation of the five-byte ATM cell headers for each ATM cell segmented and forwarded by ATM transmit controller  132 . Control then passes to process  288 , for transmission of header bytes to DSP  32 , as will now be described relative to  FIG. 13 . 
   As noted above and as well known in the art, conventional ATM cell headers are five bytes in length; however, only a thirty-two bit data word is communicated over bus VBus to bus HPIF, and thus to DSP  32 . As such, the transmission of an ATM cell header requires two data words for complete transmission. However, as is also well known in the art, the fifth byte of an ATM cell header is dedicated for the HEC field, which will be generated by the transmission convergence layer at DSP  32 . As such, while segmentation state machine  260  must generate a five byte ATM cell header, the fifth byte of this header is a null, or don&#39;t care, byte, prior to processing by DSP  32 . Process  288  is thus a two-pass process, and begins with decision  311  in which segmentation state machine  260  determines whether the four-byte partial header has previously been transmitted to VBus state machine  270 . If not (decision  311  is NO), control passes to decision  313 . 
   In decision  313 , segmentation state machine  260  determines, from the packet type ATM header information stored in packet type register  256 , whether the current packet is an OAM packet. If so (decision  313  is YES), the transmitted packet will be a single cell packet, and as such control passes directly to process  314  by way of which segmentation state machine  260  transfers the first four bytes of the ATM cell header to byte buffers  268  via demultiplexer  266 . As is known in the ATM art, these four bytes include the GFC, VPI, VCI, PTI, and CLP fields. Control then passes back to decisions  281  and  283  to wait for byte buffers  268  to clear and for additional data to be written to endpoint  240   1 . 
   If decision  313  is not an OAM or a transparent packet (decision  313  is NO), segmentation state machine  260  performs decision  315  to determine whether the last ATM cell is about to be transmitted for the current ATM packet. If so (decision  315  is YES), process  316  is performed by segmentation state machine  260  to rewrite the PTI field in the four-byte ATM header to include the end-of-packet indicator for that cell. In either case (decision  315  is NO, or following process  316 ), segmentation state machine  260  transfers the first four bytes of the ATM cell header to byte buffers  268 , in process  314 . 
   Following process  314 , control passes back to decision  281  to await the reading of the previous header information from byte buffers  268 . Once byte buffers  268  are read, and upon decision  283  returning a YES, indicating the presence of new data at endpoint  240   1  decision  285  again returns a NO result since the header has not been completely configured and transmitted. Process  286  may be skipped for this second pass (considering that the ATM header information is already stored in registers  252 ,  254 ,  256 ) and control passes to decision  311  of process  288  which returns a YES result indicating that the four-byte partial header has already been set. Segmentation state machine  260  then transmits a null byte to one of byte buffers  268  (i.e., the zeroth byte) for eventual transmission to DSP  32 . Control then returns back to decision  281  (which necessarily returns a NO result at this point), and decisions  283 ,  285  (each of which returns a YES result), following which segmentation state machine  260  next performs decision  287 . 
   Decision  287  determines whether the current byte count value, which is stored in byte counter  264 , has the value forty-eight, which is the maximum number of bytes of payload in an ATM cell, as is known in the art. If not (decision  287  is NO), the next byte of data to be processed will not be the final byte in the current ATM cell. Decision  293  is then performed by segmentation state machine  260  to determine whether the current ATM cell is the last cell in the ATM packet, by comparing the current value of cell counter  262  with a terminal cell count that may be derived from the current contents of length register  254 ; in this regard, since all OAM packets consist of only a single cell, a packet type identifier (register  256 ) indicating an OAM packet will also cause decision  293  to return a YES result. 
   If the current ATM cell being produced is not the last cell in the packet, process  294  is performed to cause transmit state machine  250  to fetch the next data byte from endpoint  240   1  of shared memory  44 ; this next data byte is received by segmentation state machine  260 , and CRC logic  258  initiates or continues the calculation of the CRC value for the current ATM packet. As discussed above relative to the receive and reassembly of ATM packets, AAL5 ATM packets include a trailer containing a thirty-two bit CRC checksum for the payload of all cells within the ATM packet. CRC logic  258  provides dedicated hardware for the calculation of this CRC checksum in an ongoing manner, effectively in parallel with the processing carried out by segmentation state machine  260 . Following the fetch of the next data byte (but not necessarily the completion of the CRC calculation, as noted above), segmentation state machine  260  next increments the value of byte counter  264 , in process  296 , and then transfers the fetched data byte to the next open location in byte buffers  268 . As noted above, VBus state machine  270  retrieves the contents of all four byte buffers  268 , in the form of a thirty-two bit data word, once these buffers are filled. Whether read by VBus state machine  270  or not, after the transfer of the data byte to byte buffers  268 , control passes back to decision  281 , where segmentation state machine  260  determines whether an available byte buffer remains, and then whether data is present at endpoint  240   1 , as noted above. 
   If the current cell is the last cell in the ATM packet (i.e., decision  293  is YES), additional processing is required to generate trailing information, or at least to prepare ATM transmit controller  132  for the next packet. Decision  299  is first performed to determine whether the current cell corresponds to an AAL5 or OAM packet; if it is of neither type (decision  299  is NO), process  302  is then performed to simply fetch the next data byte from endpoint  240   1 . If, on the other hand, the current packet is an AAL5 or OAM packet, process  300  is performed by segmentation state machine  260  to substitute the final CRC value (either CRC-32 or CRC-10, as the case may be) for the appropriate data portion of the cell. In either case (after process  302  or process  304 , as the case may be), decision  303  is next performed to determine whether the current byte is the last byte in this the last cell of the packet. If not (decision  303  is NO), process  296  is performed to increment the byte count and the current byte is transferred to the appropriate byte buffer  268  in process  298 , with control returning to decision  281  for receipt of the next byte. 
   Upon reaching the last byte of the cell (decision  303  is YES), the ATM packet may be completed. In process  304 , the header and control configuration information stored in registers  252 ,  254 ,  256  is cleared by segmentation state machine  260 , so that the next packet will have its own ATM cell headers configured and transmitted via decision  285  and processes  286 ,  288 . The contents of byte counter  264  are cleared in process  306 , and the contents of cell counter  262  are cleared in process  308 . This final byte is then transferred to byte buffers  268 , in process  298 , and the transmission of the ATM packet is then complete. Control then returns to decisions  281 ,  283  to await the emptying of byte buffers  268  and the receipt of new data at endpoints  240 , with the process then repeating for the next ATM packet. 
   According to the present invention, therefore, significant advantages are obtained by the segmentation of ATM packets into ATM cells at the USB interface device, as described above. The USB bus is more efficiently utilized according to the present invention, as compared with conventional USB-based devices, because the ATM header information need only be communicated over the USB bus once according to the present invention; the segmentation logic in the USB interface device itself then generates the ATM cell headers. Secondly, the host is able to communicate the ATM packet payload by way of full USB packets (e.g., sixty-four byte bulk packets), without regard to ATM cell boundaries, as opposed to conventional devices in which the fifty-three byte ATM packets are transmitted within individual sixty-four byte USB packets with eleven null bytes. The computationally intensive operations of segmentation, CRC calculation, and the like are also performed in the USB peripheral according to the present invention, preferably in dedicated hardware, thus relieving the host from performing these functions in software. Accordingly, the development and implementation of host drivers for the ATM transmission is significantly facilitated by the present invention. 
   While the present invention has been described according to its preferred embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.