Patent Publication Number: US-2004044864-A1

Title: Data storage

Description:
FIELD  
       [0001] This disclosure relates to the field of data storage.  
       BACKGROUND  
       [0002] In a data backup technique, a redundant copy of data stored in a data storage system may be made. In the event that data stored in the system becomes lost and/or corrupted, it may be possible to recover the lost and/or corrupted data from the redundant copy. Unless the data backup technique is capable of copying the system&#39;s data to the redundant copy in a way that maintains the coherency of the system&#39;s data in the redundant copy, it may not be possible to recover meaningful data from the redundant copy. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0003] Features and advantages of embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and in which:  
     [0004]FIG. 1 is a diagram illustrating a system embodiment.  
     [0005]FIG. 2 is a diagram illustrating information that may be encoded on a tape data storage medium according to one embodiment.  
     [0006]FIG. 3 is a diagram illustrating data volumes and data segments that may be stored in mass storage according to one embodiment.  
     [0007]FIG. 4 is a flowchart illustrating operations that may be performed in the system of FIG. 1 according to one embodiment. 
    
    
     [0008] Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.  
     DETAILED DESCRIPTION  
     [0009]FIG. 1 illustrates a system embodiment  100 . System  100  may include a host processor  12  coupled to a chipset  14 . Host processor  12  may comprise, for example, an Intel® Pentium® III or IV microprocessor commercially available from the Assignee of the subject application. Of course, alternatively, host processor  12  may comprise another type of microprocessor, such as, for example, a microprocessor that is manufactured and/or commercially available from a source other than the Assignee of the subject application, without departing from this embodiment.  
     [0010] Chipset  14  may comprise a host bridge/hub system (not shown) that may couple host processor  12 , a system memory  21  and a user interface system  16  to each other and to a bus system  22 . Chipset  14  may also include an input/output (I/O) bridge/hub system (not shown) that may couple the host bridge/bus system to bus  22 . Chipset  14  may comprise integrated circuit chips, such as those selected from integrated circuit chipsets commercially available from the Assignee of the subject application (e.g., graphics memory and I/O controller hub chipsets), although other integrated circuit chips may also, or alternatively be used, without departing from this embodiment. Additionally, chipset  14  may include an interrupt controller (not shown) that may be coupled, via one or more interrupt signal lines (not shown), to other components, such as, e.g., I/O controller circuit card  20 A, I/O controller card  20 B, and/or one or more tape drives (collectively and/or singly referred to herein as “tape drive  46 ”), when card  20 A, card  20 B, and/or tape drive  46  are inserted into circuit card bus extension slots  30 B,  30 C, and  30 A, respectively. This interrupt controller may process interrupts that it may receive via these interrupt signal lines from the other components in system  100 .  
     [0011] The operative circuitry  42 A and  42 B described herein as being comprised in cards  20 A and  20 B, respectively, need not be comprised in cards  20 A and  20 B, but instead, without departing from this embodiment, may be comprised in other structures, systems, and/or devices that may be, for example, comprised in motherboard  32 , coupled to bus  22 , and exchange data and/or commands with other components in system  100 . User interface system  16  may comprise, e.g., a keyboard, pointing device, and display system that may permit a human user to input commands to, and monitor the operation of, system  100 .  
     [0012] Bus  22  may comprise a bus that complies with the Peripheral Component Interconnect (PCI) Local Bus Specification, Revision 2.2, Dec. 18, 1998 available from the PCI Special Interest Group, Portland, Oreg., U.S.A. (hereinafter referred to as a “PCI bus”). Alternatively, bus  22  instead may comprise a bus that complies with the PCI-X Specification Rev. 1.0a, Jul. 24, 2000, available from the aforesaid PCI Special Interest Group, Portland, Oreg., U.S.A. (hereinafter referred to as a “PCI-X bus”). Also alternatively, bus  22  may comprise other types and configurations of bus systems, without departing from this embodiment.  
     [0013] I/O controller card  20 A may be coupled to and control the operation of a set of one or more magnetic disk, optical disk, solid-state, and/or semiconductor mass storage devices (hereinafter collectively or singly referred to as “mass storage  28 A”). In this embodiment, mass storage  28 A may comprise, e.g., a mass storage subsystem comprising one or more redundant arrays of inexpensive disk (RAID) mass storage devices  29 A.  
     [0014] I/O controller card  20 B may be coupled to and control the operation of a set of one or more magnetic disk, optical disk, solid-state, and/or semiconductor mass storage devices (hereinafter collectively or singly referred to as “mass storage  28 B”). In this embodiment, mass storage  28 B may comprise, e.g., a mass storage subsystem comprising one or more redundant arrays of inexpensive disk (RAID) mass storage devices  29 B.  
     [0015] Processor  12 , system memory  21 , chipset  14 , PCI bus  22 , and circuit card slots  30 A,  30 B, and  30 C may be comprised in a single circuit board, such as, for example, a system motherboard  32 . Mass storage  28 A and/or mass storage  28 B may be comprised in one or more respective enclosures that may be separate from the enclosure in which motherboard  32  and the components comprised in motherboard  32  are enclosed.  
     [0016] Depending upon the particular configuration and operational characteristics of mass storage  28 A and mass storage  28 B, I/O controller cards  20 A and  20 B may be coupled to mass storage  28 A and mass storage  28 B, respectively, via one or more respective network communication links or media  44 A and  44 B. Cards  20 A and  20 B may exchange data and/or commands with mass storage  28 A and mass storage  28 B, respectively, via links  44 A and  44 B, respectively, using any one of a variety of different communication protocols, e.g., a Small Computer Systems Interface (SCSI), Fibre Channel (FC), Ethernet, Serial Advanced Technology Attachment (S-ATA), or Transmission Control Protocol/Internet Protocol (TCP/IP) communication protocol. Of course, alternatively, I/O controller cards  20 A and  20 B may exchange data and/or commands with mass storage  28 A and mass storage  28 B, respectively, using other communication protocols, without departing from this embodiment.  
     [0017] In accordance with this embodiment, a SCSI protocol that may be used by controller cards  20 A and  20 B to exchange data and/or commands with mass storage  28 A and  28 B, respectively, may comply or be compatible with the interface/protocol described in American National Standards Institute (ANSI) Small Computer Systems Interface-2 (SCSI-2) ANSI X3.131-1994 Specification. If a FC protocol is used by controller cards  20 A and  20 B to exchange data and/or commands with mass storage  28 A and  28 B, respectively, it may comply or be compatible with the interface/protocol described in ANSI Standard Fibre Channel (FC) Physical and Signaling Interface-3 X3.303:1998 Specification. Alternatively, if an Ethernet protocol is used by controller cards  20 A and  20 B to exchange data and/or commands with mass storage  28 A and  28 B, respectively, it may comply or be compatible with the protocol described in Institute of Electrical and Electronics Engineers, Inc. (IEEE) Std. 802.3, 2000 Edition, published on Oct. 20, 2000. Further, alternatively, if a S-ATA protocol is used by controller cards  20 A and  20 B to exchange data and/or commands with mass storage  28 A and  28 B, respectively, it may comply or be compatible with the protocol described in “Serial ATA: High Speed Serialized AT Attachment,” Revision 1.0, published on Aug. 29, 2001 by the Serial ATA Working Group. Also, alternatively, if TCP/IP is used by controller cards  20 A and  20 B to exchange data and/or commands with mass storage  28 A and  28 B, respectively, it may comply or be compatible with the protocols described in Internet Engineering Task Force (IETF) Request For Comments (RFC) 791 and 793, published September 1981.  
     [0018] Circuit card slots  30 A,  30 B, and  30 C may comprise respective PCI expansion slots that may comprise respective PCI bus connectors  36 A,  36 B, and  36 C. Connectors  36 A,  36 B, and  36 C may be electrically and mechanically mated with PCI bus connectors  50 ,  34 A, and  34 B that may be comprised in tape drive  46 , card  20 A, and card  20 B, respectively. Circuit cards  20 A and  20 B also may comprise respective operative circuitry  42 A and  42 B. Circuitry  42 A may comprise a respective processor (e.g., an Intel® Pentium® III or IV microprocessor) and respective associated computer-readable memory (collectively and/or singly referred to hereinafter as “processor  40 A”). Circuitry  42 B may comprise a respective processor (e.g., an Intel® Pentium® III or IV microprocessor) and respective associated computer-readable memory (collectively and/or singly referred to hereinafter as “processor  40 B”). The respective associated computer-readable memory that may be comprised in processors  40 A and  40 B may comprise one or more of the following types of memories: semiconductor firmware memory, programmable memory, non-volatile memory, read only memory, electrically programmable memory, random access memory, flash memory, magnetic disk memory, and/or optical disk memory. Either additionally or alternatively, such computer-readable memory may comprise other and/or later-developed types of computer-readable memory. Also either additionally or alternatively, processors  40 A and  40 B each may comprise another type of microprocessor, such as, for example, a microprocessor that is manufactured and/or commercially available from a source other than the Assignee of the subject application, without departing from this embodiment.  
     [0019] Respective sets of machine-readable firmware program instructions may be stored in the respective computer-readable memories associated with processors  40 A and  40 B. These respective sets of instructions may be accessed and executed by processors  40 A and  40 B, respectively. When executed by processors  40 A and  40 B, these respective sets of instructions may result in processors  40 A and  40 B performing the operations described herein as being performed by processors  40 A and  40 B.  
     [0020] Circuitry  42 A and  42 B may also comprise cache memory  38 A and cache memory  38 B, respectively. In this embodiment, cache memories  38 A and  38 B each may comprise one or more respective semiconductor memory devices. Alternatively or additionally, cache memories  38 A and  38 B each may comprise respective magnetic disk and/or optical disk memory. Processors  40 A and  40 B may be capable of exchanging data and/or commands with cache memories  38 A and  38 B, respectively, that may result in cache memories  38 A and  38 B, respectively, storing in and/or retrieving data from cache memories  38 A and  38 B, respectively, to facilitate, among other things, processors  40 A and  40 B carrying out their respective operations.  
     [0021] Tape drive  46  may include cabling (not shown) that couples the operative circuitry (not shown) of tape drive  46  to connector  50 . Connector  50  may be electrically and mechanically coupled to connector  36 A. When connectors  50  and  36 A are so coupled to each other, the operative circuitry of tape drive  46  may become electrically coupled to bus  22 . Alternatively, instead of comprising such cabling, tape drive  46  may comprise a circuit card that may include connector  50 .  
     [0022] Tape drive  46  also may include a tape read/write mechanism  52  that may be constructed such that a mating portion  56  of a tape cartridge  54  may be inserted into mechanism  52 . When mating portion  56  of cartridge  54  is properly inserted into mechanism  52 , tape drive  46  may use mechanism  52  to read data from and/or write data to one or more tape data storage media  48  (also referenced herein in the singular as, for example, “tape medium  48 ”) comprised in cartridge  54 , in the manner described hereinafter. Tape medium  48  may comprise, e.g., an optical and/or magnetic mass storage tape medium. When tape cartridge  54  is inserted into mechanism  52 , cartridge  54  and tape drive  46  may comprise a backup mass storage subsystem  72 .  
     [0023] Slots  30 B and  30 C are constructed to permit cards  20 A and  20 B to be inserted into slots  30 B and  30 C, respectively. When card  20 A is properly inserted into slot  30 B, connectors  34 A and  36 B become electrically and mechanically coupled to each other. When connectors  34 A and  36 B are so coupled to each other, circuitry  42 A in card  20 A may become electrically coupled to bus  22 . When card  20 B is properly inserted into slot  30 C, connectors  34 B and  36 C become electrically and mechanically coupled to each other. When connectors  34 B and  36 C are so coupled to each other, circuitry  42 B in card  20 B may become electrically coupled to bus  22 . When tape drive  46 , circuitry  42 A in card  20 A, and circuitry  42 B in card  20 B are electrically coupled to bus  22 , host processor  12  may exchange data and/or commands with tape drive  46 , circuitry  42 A in card  20 A, and circuitry  42 B in card  20 B, via chipset  14  and bus  22 , that may permit host processor  12  to monitor and control operation of tape drive  46 , circuitry  42 A in card  20 A, and circuitry  42 B in card  20 B. For example, host processor  12  may generate and transmit to circuitry  42 A and  42 B in cards  20 A and  20 B, respectively, via chipset  14  and bus  22 , I/O requests for execution by mass storage  28 A and  28 B, respectively. Circuitry  42 A and  42 B in cards  20 A and  20 B, respectively, may be capable of generating and providing to mass storage  28 A and  28 B, via links  44 A and  44 B, respectively, commands that, when received by mass storage  28 A and  28 B may result in execution of these I/O requests by mass storage  28 A and  28 B, respectively. These I/O requests, when executed by mass storage  28 A and  28 B, may result in, for example, reading of data from and/or writing of data to mass storage  28 A and/or mass storage  28 B.  
     [0024] As shown in FIG. 3, RAID  29 A may comprise a plurality of user data volumes  200  and  202 . Of course, RAID  29 A may comprise any number of user data volumes without departing from this embodiment. Each of the data volumes  200  and  202  may comprise a respective logical data volume that may span a respective set of physical disk devices (not shown) in mass storage  28 A. For example, data volume  200  may comprise a plurality of logical user data segments  300 A,  300 B, . . .  300 N, and data volume  202  may comprise a plurality of logical data segments  400 A,  400 B, . . .  400 N. Depending upon the particular RAID technique implemented in RAID  29 A, each respective logical data segment  300 A,  300 B, . . .  300 N in volume  200  and each respective logical data segment  400 A,  400 B, . . .  400 N in volume  202  may comprise a respective plurality of logically related physical data segments (not shown) that are distributed in multiple physical mass storage devices (not shown), and from which the respective logical data segment may be calculated and/or obtained. For example, if RAID Level 1 (i.e., mirroring) is implemented in RAID  29 A, then each logical data segment  300 A,  300 B, . . .  300 N in volume  200  and each logical data segment  400 A,  400 B, . . .  400 N in volume  202  may comprise a respective pair of physical data segments (not shown) that are copies of each other and are distributed in two respective physical mass storage devices (not shown). Alternatively, other RAID techniques may be implemented in RAID  29 A without departing from this embodiment. Each of the logical data segments in RAID  29 A may have a predetermined size, such as, for example, 16 or 32 kilobytes (KB). Alternatively, or additionally, each of the logical data segments in RAID  29 A may have predetermined size that corresponds to a predetermined number of disk stripes. Of course, the number and size of the logical data segments in RAID  29 A may differ without departing from this embodiment.  
     [0025] The operations that may implement the RAID technique implemented in RAID  29 A may be carried out by RAID circuitry (not shown) that may be comprised in, e.g., mass storage  28 A. Alternatively, card  20 A may comprise such RAID circuitry. Processor  40 A may exchange data and/or commands with such RAID circuitry that may result in data segments being written to and/or read from RAID  29 A in accordance with the RAID technique implemented by RAID  29 A. Alternatively, processor  40 A may be programmed to emulate operation of such RAID circuitry, and may exchange data and/or commands with mass storage  28 A that may result in RAID  29 A being implemented in mass storage  28 A. Further alternatively, host processor  12  may be programmed to emulate operation of such RAID circuitry, and may exchange data and/or commands with mass storage  28 A and/or processor  40 A that may result in RAID  29 A being implemented in mass storage  28 A.  
     [0026] Also shown in FIG. 3, RAID  29 B may comprise a plurality of user data volumes  200 ′ and  202 ′. Of course, RAID  29 B may comprise any number of user data volumes without departing from this embodiment. Each of the data volumes  200 ′ and  202 ′ may comprise a respective logical data volume that may span a respective set of physical disk devices (not shown) in mass storage  28 B. For example, data volume  200 ′ may comprise a plurality of logical user data segments  300 A′,  300 B′, . . .  300 N′, and data volume  202 ′ may comprise a plurality of logical data segments  400 A′,  400 B′, . . .  400 N′. Depending upon the particular RAID technique implemented in RAID  29 B, each respective logical data segment  300 A′,  300 B′, . . .  300 N′ in volume  200 ′ and each respective logical data segment  400 A′,  400 B′, . . .  400 N′ in volume  202 ′ may comprise a respective plurality of logically related physical data segments (not shown) that are distributed in multiple physical mass storage devices (not shown), and from which the respective logical data segment may be calculated and/or obtained. For example, if RAID Level  1  (i.e., mirroring) is implemented in RAID  29 B, then each logical data segment  300 A′,  300 B′, . . .  300 N′ in volume  200 ′ and each logical data segment  400 A′,  400 B′, . . .  400 N′ in volume  202 ′ may comprise a respective pair of physical data segments (not shown) that are copies of each other and are distributed in two respective physical mass storage devices (not shown). Alternatively, other RAID techniques may be implemented in RAID  29 B without departing from this embodiment. Each of the logical data segments in RAID  29 B may have a predetermined size, such as, for example, 16 or 32 kilobytes (KB). Alternatively, or additionally, each of the logical data segments in RAID  29 B may have predetermined size that corresponds to a predetermined number of disk stripes. Of course, the number and size of the logical data segments in RAID  29 B may differ without departing from this embodiment.  
     [0027] The operations that may implement the RAID technique implemented in RAID  29 B may be carried out by RAID circuitry (not shown) that may be comprised in, e.g., mass storage  28 B. Alternatively, card  20 B may comprise such RAID circuitry. Processor  40 B may exchange data and/or commands with such RAID circuitry that may result in data segments being written to and/or read from RAID  29 B in accordance with the RAID technique implemented by RAID  29 B. Alternatively, processor  40 B may be programmed to emulate operation of such RAID circuitry, and may exchange data and/or commands with mass storage  28 B that may result in RAID  29 B being implemented in mass storage  28 B. Further alternatively, host processor  12  may be programmed to emulate operation of such RAID circuitry, and may exchange data and/or commands with mass storage  28 B and/or processor  40 B that may result in RAID  29 B being implemented in mass storage  28 B.  
     [0028] Firmware program instructions executed by processors  40 A and  40 B may result in, among other things, processors  40 A and  40 B issuing appropriate control signals to circuitry  42 A and  42 B in cards  20 A and  20 B, respectively, that may result in data storage, backup, and/or recovery operations, in accordance with one embodiment, being performed in system  100 . FIG. 4 is a flowchart that illustrates operations  500  that may be carried out in system  100 , in accordance with this embodiment.  
     [0029] In accordance with one embodiment, a human user (not shown) may issue a command to host processor  12  via user interface system  16  to create a redundant backup copy of data stored in RAID  29 A and RAID  29 B in mass storage  28 A and mass storage  28 B, respectively. This may result in host processor  12  generating and issuing to circuitry  42 A and  42 B in cards  20 A and  20 B, respectively, commands to initiate the creation of such a redundant backup copy.  
     [0030] As illustrated by operation  502  in FIG. 4, circuitry  42 A in I/O controller card  20 A may receive a command, issued from host processor  12 , to initiate the creation of a redundant backup copy of data stored in RAID  29 A in mass storage  28 A. In response to receipt of this command from host processor  12 , processor  40 A may signal circuitry  42 A. This may result in circuitry  42 A in I/O controller card  20 A entering one mode of operation, as illustrated by operation  504  in FIG. 4. In this one mode of operation, processor  40 A may permit and/or initiate execution by mass storage  28 A of all pending I/O requests (e.g., I/O write requests), if any, received prior to the entry of circuitry  42 A in card  20 A into the one mode of operation, that may result in modification of one or more of logical data segments in RAID  29 A, as illustrated by operation  506  in FIG. 4. More specifically, in this one mode of operation, processor  40 A may examine an I/O request queue (not shown) that may be maintained by processor  40 A in, for example, cache memory  38 A or the memory associated with processor  40 A in card  20 A, to determine whether any pending I/O requests, received prior to the entry of circuitry  42 A in card  20 A into the first mode of operation, that involve modifying data in one or more data segments in RAID  29 A in mass storage  28 A, are currently queued in the request queue for execution. As used herein, a “pending” I/O request is an I/O transaction of which a device assigned to perform, execute, and/or initiate the transaction has been informed, but whose performance, execution, and/or initiation has yet to be completed. If any such pending I/O requests are currently queued in the I/O request queue, processor  40 A may signal circuitry  42 A in card  20 A. This may result in circuitry  42 A issuing one or more commands via links  44 A to mass storage  28 A that may result in mass storage  28 A executing all such pending I/O requests.  
     [0031] Also in this one mode of operation, processor  40 A may signal circuitry  42 A; this may result in circuitry  42 A periodically polling for an indication that the other circuitry  42 B is ready to begin copying to tape medium  48  a redundant backup copy of data stored in RAID  29 B in mass storage  28 B, as illustrated by operation  508  in FIG. 4. That is, in this one mode of operation, circuitry  42 A in controller card  20 A may periodically issue, via bus  22 , a request to circuitry  42 B in controller card  20 B that circuitry  42 B in controller card  20 B provide to circuitry  42 A an indication whether circuitry  42 B in controller card  20 B is ready to begin such copying. In response to such request, circuitry  42 B may provide to circuitry  42 A, via bus  22 , a response that may indicate to circuitry  42 A whether circuitry  42 B is ready to begin such copying.  
     [0032] Alternatively, host processor  12  may periodically issue a request to circuitry  42 B that circuitry  42 B provide to host processor  12  an indication whether circuitry  42 B is ready to begin such copying. In response to such request, circuitry  42 B may provide to host processor  12  a response that may indicate whether circuitry  42 B is ready to begin such copying. When host processor  12  receives from circuitry  42 B an indication that circuitry  42 B is ready to begin such copying, host processor  12  may provide circuitry  42 A in controller card  20 A with such indication.  
     [0033] Also in one mode of operation, circuitry  42 A may store and/or queue for future execution any I/O requests (e.g., I/O write requests), received by circuitry  42 A after entry of circuitry  42 A into the one mode of operation, that if executed may result in modification of one or more logical data segments stored in RAID  29 A in mass storage  28 A, as illustrated by operation  510  in FIG. 4. For example, after the entry of circuitry  42 A into the one mode of operation, host processor  12  may issue to circuitry  42 A one or more I/O write requests that, if executed, may result in modification of one or more logical data segments in RAID  29 A in mass storage  28 A. If, while in the one mode of operation, circuitry  42 A receives any such I/O write requests issued by host processor  12 , processor  40 A may signal circuitry  42 A. This may result in circuitry  42 A in card  20 A storing and/or queuing such received I/O write request in the I/O request queue. This may also result in circuitry  42 A being prevented from commanding, until after the one or more logical data segments that may modified by such received I/O write requests have been copied to tape medium  48 , mass storage  28 A to execute any such received I/O write requests from being executed by mass storage  28 A. This may prevent mass storage  28 A from executing any such received I/O request until after the one or more logical data segments that may modified by such received I/O write requests have been copied to tape medium  48 .  
     [0034] Thus, after circuitry  42 A enters this one mode of operation as a result of operation  504 , and thereafter, while in this one mode of operation, operations  506 ,  508 , and  510  may be performed. Also, while in this one mode of operation, processor  40 A may periodically determine whether circuitry  42 A and circuitry  42 B are ready to copy the logical data segments in RAID  29 A and RAID  29 B, respectively, to tape medium  48 , as illustrated by operation  512  in FIG. 4. Processor  40 A may determine whether circuitry  42 B is ready to copy to tape medium  48  the logical data segments in RAID  29 B based, at least in part, upon whether circuitry  42 A has received an indication generated, as a result, for example, at least in part, of operation  508 , that circuitry  42 B is ready to begin such copying.  
     [0035] In operation  512 , processor  40 A may also examine the I/O request queue stored in circuitry  42 A to determine whether all of the pending I/O requests, if any, received prior to the entry of circuitry  42 A into the one mode of operation, that if executed would result in modification of one or more of the logical data segments in RAID  29 A, have been executed. After all of such pending I/O requests, if any, have been executed, processor  40 A may determine that circuitry  42 A is ready to begin copying to tape medium  48  a redundant backup copy of the data stored in RAID  29 A.  
     [0036] If processor  40 A determines, as a result of operation  512 , that either or both of circuitry  42 A and  42 B are not ready to begin copying the logical data segments in RAID  29 A and RAID  29 B in mass storage  28 A and  28 B, respectively, to tape medium  48 , processor  40 A may signal circuitry  42 A. If all of the pending I/O write requests, if any, received prior to the entry of circuitry  42 A into the one mode of operation as a result of operation  504 , that if executed would result in modification of one or more of the logical data segments in RAID  29 A, have already been executed, for example, as a result of operation  506 , this signaling of circuitry  42 A by processor  40 A may result in circuitry  42 A remaining in the one mode of operation, with processing continuing with periodic executions of operations  508 ,  510 , and  512 , as illustrated in FIG. 4. Conversely, all of such I/O write requests, if any, have not already been executed, this signaling of circuitry  42 A by processor  40 A may result in circuitry  42 A remaining in the one mode of operation, with processing continuing with execution of operation  506  and periodic execution of operations  508 ,  510 , and  512 .  
     [0037] Conversely, if processor  40 A determines, as a result of operation  512 , that both circuitry  42 A and circuitry  42 B are ready to begin copying the logical data segments in RAID  29 A and RAID  29 B in mass storage  28 A and  28 B, respectively, to tape medium  48 , processor  40 A may signal circuitry  42 A. This may result in circuitry  42 A in card  20 A entering another mode of operation that is different from the mode of operation that circuitry  42 A entered as a result of operation  504 , as illustrated by operation  516 . In this other mode of operation, circuitry  42 A may continue to store and/or queue for future execution by mass storage  28 A any I/O request that circuitry  42 A may have received after entry of circuitry  42 A into the one mode of operation and prior to operation  522 , if the I/O request, if executed, would result in modification of a logical data segment stored in RAID  29 A in mass storage  28 A, as illustrated by operation  518  in FIG. 4. More specifically, as a result of operation  518 , during this other mode of operation of circuitry  42 A, any such received I/O request received may continue to be queued for future execution by mass storage  28 A. Processor  40 A may signal circuitry  42 A; this may result in circuitry  42 A being prevented from commanding, until after the logical data segment in RAID  29 A that may be modified by execution of such received I/O request has been copied to tape medium  48  as a result of operation  522 , mass storage  28 A to execute any such received I/O request. This may result in mass storage  28 A being prevented from executing any such received I/O request until after the logical data segment in RAID  29 A that may be modified by execution of such received I/O request has been copied to tape medium  48  as a result of operation  522 .  
     [0038] Also in this other mode of operation of circuitry  42 A, processor  40 A may signal circuitry  42 A. This may result in circuitry  42 A determining whether it has been granted access to tape medium  48  to copy the logical data segments stored in RAID  29 A to tape medium  48 , as illustrated by operation  520 . For example, as a result of operation  520 , circuitry  42 A may use a conventional arbitration process to arbitrate with the other circuitry  42 B for grant of such access to tape medium  48 .  
     [0039] If the arbitration between circuitry  42 A and  42 B results in the grant of such access to circuitry  42 A, then circuitry  42 A may determine, as a result of operation  520 , that circuitry  42 A has been granted access to tape medium  48  to begin copying the logical data segments in RAID  29 A to tape medium  48 . Conversely, if this arbitration results in the grant of such access to circuitry  42 B, then circuitry  42 B may begin to copy the logical data segments in RAID  29 B to tape medium  48 . While circuitry  42 B is copying these logical data segments to tape medium  48 , circuitry  42 A may continue to perform operation  518 , and may periodically determine whether circuitry  42 B has finished copying the logical data segments in RAID  29 B to tape medium  48 . That is, after circuitry  42 B has finished copying the logical data segments in RAID  29 B to tape medium  48 , circuitry  42 B may signal circuitry  42 A to indicate same. Alternatively, after circuitry  42 B has finished copying the logical data segments in RAID  29 B to tape medium  48 , circuitry  42 B may signal host processor  12  to indicate same, and host processor  12  may signal circuitry  42 A. In either case, this signaling of circuitry  42 A by circuitry  42 B or host processor  12  may result in circuitry  42 A determining, as a result of operation  520 , that circuitry  42 A has been granted access to tape medium  48  to begin copying the logical data segments in RAID  29 A to tape medium  48 .  
     [0040] After circuitry  42 A in card  20 A has determined, as a result of operation  520 , that it has been granted such access to tape medium  48 , processor  40 A may select a logical data segment from RAID  29 A that has yet to be backed up (i.e., copied) to tape medium  48 , and may signal tape drive  46  to copy this logical data segment to tape medium  48 , as illustrated by operation  522  in FIG. 4. Processor  40 A may make this selection based, at least in part, upon an examination of a bitmap  70 A that may be stored in cache memory  38 A in card  20 A. That is, based upon signals provided to cache memory  38 A from processor  40 A, cache memory  38 A may store and maintain bitmap  70 A that may contain a sequence of bit values (not shown). Each of these bit values may correspond to and/or represent a respective logical data segment in RAID  29 A. When circuitry  42 A enters the other mode of operation as a result of operation  516 , processor  40 A may signal cache memory  38 A to clear the bit values in bitmap  70 A. Thereafter, after a respective logical data segment is transmitted to tape drive  46  for copying to tape medium  48 , processor  40 A may signal cache memory  38 A to set the bit value in bitmap  70 A that corresponds to the respective logical data segment. As used herein, a bit value is considered to be set when it is equal to a value that indicates a first Boolean logical condition (e.g., True), and conversely, a bit value is considered to be cleared when it is equal to a value that indicates a second Boolean logical condition (e.g., False) that is opposite to the first Boolean logical condition. Thus, by examining bitmap  70 A in operation  522 , processor  40 A may determine which of the logical data segments in RAID  29 A have yet to be copied to tape medium  48 .  
     [0041] Based upon signals provided to cache memory  38 B from processor  40 B, cache memory  38 B may store and maintain bitmap  70 B that may contain a sequence of bit values (not shown) that may correspond to and/or represent respective logical data segments in RAID  29 B. Bitmap  70 B may be stored and/or maintained in cache memory  38 B in a manner that is substantially similar to the above-described manner in which bitmap  70 A may be stored and/or maintained.  
     [0042] Also in operation  522 , processor  40 A may examine the I/O request queue in card  20 A to determine whether there are any pending I/O requests in the I/O request queue that, if executed, may result in modification of any of the logical data segments in RAID  29 A. If any such pending I/O requests are in the I/O request queue, processor  40 A may determine the logical data segment or segments that may be modified if such requests were executed, and any such segment or segments that have yet to be copied to tape medium  48  may be assigned higher relative priorities than other logical data segments in RAID  29 A for selection by processor  40 A for copying to tape medium  48 . Processor  40 A may select for copying to tape medium  48  logical data segments that are assigned a higher relative priorities before selecting for copying to tape medium logical data segments that are assigned lower relative priorities. Thus, processor  40 A may also base its selection of which of the logical data segments to copy to tape  48 , at least in part, upon these relative priorities that may be assigned by processor  40 A to the logical data segments in RAID  29 A.  
     [0043] In operation  522 , after selecting a logical data segment (e.g., segment  300 A) in RAID  29 A to be copied to tape medium  48 , processor  40 A may permit the selected segment to be copied to tape medium  48 . More specifically, processor  40 A may signal circuitry  42 A in card  20 A. This may result in circuitry  42 A signaling mass storage  28 A. This may result in mass storage  28 A retrieving selected logical data segment  300 A from RAID  29 A and supplying selected logical data segment  300 A to circuitry  42 A. Circuitry  42 A then may transmit to tape drive  46  selected logical data segment  300 A and information indicating the location of the segment  300 A in RAID  29 A. Circuitry  42 A also may signal tape drive  46  to copy to tape medium  48  data segment  300 A and the information that indicates the location of segment  300 A in RAID  29 A. As used herein, a “location” of data or a data segment may be, comprise, or be specified by, one or more identifiers, such as, for example, one or more logical and/or physical addresses, volumes, heads and/or sectors of and/or corresponding to the data or data segment, that may be used to identify the data or data segment for the purpose of enabling reading and/or modification of a data or data segment. Processor  40 A then may signal cache  38 A to set the bit value in bitmap  70 A that corresponds to logical data segment  300 A that was transmitted to tape drive  46 .  
     [0044] After circuitry  42 A has begun copying logical data segments in RAID  29 A to tape medium  48  in this other mode of operation, if circuitry  42 A receives an I/O request, processor  40 A may examine the I/O request and bitmap  70 A to determine whether the I/O request, if executed, may result in modification of a logical data segment in RAID  29 A that has yet to be copied to tape medium  48 . If processor  40 A determines that the received I/O request, if executed, either would not result in modification of a logical data segment in RAID  29 A or may result in modification of a logical data segment in RAID  29 A that has been copied to tape medium  48 , processor  40 A may permit the received I/O request to be executed. Conversely, if processor  40 A determines that the received I/O request, if executed, may result in modification of a logical data segment in RAID  29 A that has yet to be copied to tape medium  48 , processor  40 A may signal circuitry  42 A. This may result in circuitry  42 A storing/queuing that I/O request in the I/O request queue in card  20 A. This may also result in circuitry  42 A being prevented from commanding mass storage  28 A to execute the I/O request until after the segment has been copied to tape medium  48 , as illustrated by operation  524  in FIG. 4. This may prevent mass storage  28 A from executing the I/O request until after the segment has been copied to tape medium  48 .  
     [0045] Also, as part of operation  524 , processor  40 A may examine the I/O requests, if any, queued in the I/O request queue in card  20 A, and also may examine bitmap  70 A to determine which, if any, of these I/O requests, if executed, may not result in modification of a logical data segment in RAID  29 A or may result in modification of a logical data segment in RAID  29 A that has been copied to tape medium  48 . As part of operation  524 , if processor  40 A determines that any I/O requests are queued in the I/O request queue that, if executed, either would not result in modification of a logical data segment in RAID  29 A or may result in modification of a logical data segment in RAID  29 A that has been copied to tape medium  48 , processor  40 A may permit any such I/O requests to be executed.  
     [0046] In response to the transmission to tape drive  46  of segment  300 A and the information indicating the location of the segment  300 A in RAID  29 A, and the signaling of tape drive  46  to copy same to tape medium  48 , tape drive  46  may signal mechanism  52 . This may result in mechanism  52  copying to tape medium  48  data segment  300 A and the information. More specifically, mechanism  52  may copy the information and data segment  300 A to tape medium  48  in such a way that the portion of tape medium  48  that may encode the information may be directly adjacent to the portion of tape medium  48  that may encode data segment  300 A. The manner in which tape drive  46  may encode data from RAID  29 A and RAID  29 B on tape medium  48  will be described below.  
     [0047] After processor  40 A signals cache  38 A to set the bit value in bitmap  70 A that corresponds to logical data segment  300 A, processor  40 A may examine bitmap  70 A to determine whether all of the logical data segments in RAID  29 A have been copied to tape medium  48 , as illustrated by operation  526  in FIG. 4. If, as a result of operation  526 , processor  40 A determines that one or more logical data segments in RAID  29 A have yet to be copied to tape medium  48 , processing may loop back to operation  522 , as illustrated in FIG. 4. Thereafter, operations  522 ,  524 , and  526  may be repeated until all logical data segments in volumes  200  and  202  in RAID  29 A have been copied to tape medium  48 .  
     [0048] If, as a result of operation  526 , processor  40 A determines that all logical data segments in RAID  29 A have been copied to tape medium  48 , processor  40 A may signal circuitry  42 A. As illustrated by operation  527 , this may result in circuitry  42 A in card  20 A exiting the other mode of operation that it entered as a result of operation  516 . Thereafter, circuitry  42 A in card  20 A may re-enter a mode of operation that circuitry  42 A was in prior to entering the one mode of operation as result of operation  504 .  
     [0049] In this embodiment, in general, card  20 B, processor  40 B, circuitry  42 B, cache memory  38 B, mass storage  28 B, and/or links  44 B may perform respective operations that may correspond to operations  500 , however, instead of being performed, in the manner previously described herein in connection with operations  500 , by card  20 A, processor  40 A, circuitry  42 A, cache memory  38 A, mass storage  28 A, and/or links  44 A, these respective operations may be performed by card  20 B, processor  40 B, circuitry  42 B, cache memory  38 B, mass storage  28 B, and/or links  44 B, respectively. Also, in the respective subset of these respective operations that may correspond to operation  508 , polling may be performed to obtain an indication whether circuitry  42 A in card  20 A is ready to begin copying logical data segments from RAID  29 A to tape medium  48 . Additionally, in the respective subset of these respective operations that may correspond to operation  520 , circuitry  42 B may arbitrate with circuitry  42 A for access to tape medium  48  to begin copying logical data segments from RAID  29 B to tape medium  48 .  
     [0050] With particular reference now being made to FIG. 2, the manner in which tape drive  46  may encode data from RAID  29 A and RAID  29 B on tape medium  48  will be described. As shown in FIG. 2, after the logical data segments of RAID  29 A and  29 B have been encoded on tape medium  48  in accordance with one embodiment, tape medium  48  may include a plurality of portions  130 ,  132 ,  134 , and  136  that encode logical data segments from RAID  29 A and RAID  29 B. For example, depending upon the direction in which mechanism  52  may advance tape medium  48  for the purpose of encoding data on tape medium  48 , if as a result of the arbitration process between circuitry  42 A and  42 B in operation  520 , circuitry  42 A was granted access to tape medium  48  prior to circuitry  42 B being granted access to tape medium  48 , portions  130 ,  132 ,  134 , and  136  may encode the logical data segments from volumes  200 ,  202 ,  200 ′, and  202 ′, respectively. In portion  130 , encoded portions  110 A,  110 B, . . .  110 N may encode copies of respective logical data segments from volume  200 . Also in portion  130 , encoded portions  112 A,  112 B, . . .  112 N may encode respective information that may identify the respective locations of the respective logical data segments in volume  200  whose data may be encoded in portions  110 A,  110 B, . . .  110 N. In portion  132 , encoded portions  114 A,  114 B, . . .  114 N may encode copies of respective logical data segments in volume  202 . Also in portion  132 , encoded portions  116 A,  116 B, . . .  116 N may encode respective information that may identify the respective locations of the respective logical data segments from volume  202  whose data may be encoded in portions  114 A,  114 B, . . .  114 N. In portion  134 , encoded portions  118 A,  118 B, . . .  118 N may encode copies of respective logical data segments in volume  200 ′. Also in portion  132 , encoded portions  120 A,  120 B, . . .  120 N may encode respective information that may identify the respective locations of the respective logical data segments from volume  200 ′ whose data may be encoded in portions  118 A,  118 B, . . .  118 N. In portion  136 , encoded portions  122 A,  122 B, . . .  122 N may encode copies of respective logical data segments from volume  202 ′. Also in portion  136 , encoded portions  124 A,  124 B, . . .  124 N may encode respective information that may identify the respective locations of the respective logical data segments from volume  202 ′ whose data may be encoded in portions  122 A,  122 B, . . .  122 N. Thus, according to one embodiment, portions  110 A,  110 B, . . .  110 N,  114 A,  114 B, . . .  114 N,  118 A,  118 B, . . .  118 N, and  122 A,  122 B, . . .  122 N of tape medium  48  that may encode copies of respective logical data segments from volumes  200 ,  202 ,  200 ′, and  202 ′, may be located adjacent portions  112 A,  112 B, . . .  112 N,  116 A,  116 B, . . .  116 N,  120 A,  120 B, . . .  120 N, and  124 A,  124 B, . . .  124 N of tape medium  48  that may encode respective information that may identify the respective locations of the respective logical data segments whose data is copied in portions  110 A,  110 B, . . .  110 N,  114 A,  114 B, . . .  114 N,  118 A,  118 B, . . .  118 N, and  122 A,  122 B, . . .  122 N, respectively. Of course, the particular order of portions  110 A,  110 B, . . .  110 N,  114 A,  114 B, . . .  114 N,  118 A,  118 B, . . .  118 N, and  122 A,  122 B, . . .  122 N relative to portions  112 A,  112 B, . . .  112 N,  116 A,  116 B, . . .  116 N,  120 A,  120 B, . . .  120 N, and  124 A,  124 B, . . .  124 N, and the particular order of portions  130 ,  132 ,  134 , and  136  may vary without departing from this embodiment. Advantageously, since, in this embodiment, the respective copy of each respective logical data segment from RAID  29 A and  29 B is encoded on tape  48  adjacent to the respective information that identifies the respective location of that respective logical data segment, the logical data segments in RAID  29 A and  29 B may be copied, without loss of such information, to tape medium  48  in a sequence order that is independent of the respective locations of the logical data segments in RAID  29 A and  29 B.  
     [0051] Thus, in summary, in one system embodiment, first, second, and third storage subsystems are provided. A first circuit card also is provided that includes first circuitry capable of being coupled to the first and the third storage subsystems. Additionally, in this system embodiment, a second circuitry card is provided that includes second circuitry capable of being coupled to the second and to the third storage subsystems. When the first circuitry is coupled to the first storage subsystem and to the third storage subsystem, the first circuitry is capable of entering one mode of operation and another mode of operation. In the one mode of operation of the first circuitry, if an input/output (I/O) request is received by the first circuitry when the first circuitry is the one mode of operation, the first circuitry prevents the I/O request from being executed by the first storage subsystem and stores the I/O request for future execution by the first storage subsystem. In the other mode of operation, the first circuitry also is capable of entering another mode of operation in which the first circuitry permits data stored in the first storage subsystem to be copied to the third storage subsystem. The entry of the first circuitry into the another mode of operation may be based, at least in part, upon a determination by the first circuitry of whether second circuitry is ready to permit data stored in the second storage subsystem to be copied to the third storage subsystem. The third storage subsystem may include one or more media on which to copy the data stored in the first storage subsystem and the data stored in the second storage subsystem.  
     [0052] Advantageously, these features of this embodiment may permit, among other things, a coherent backup copy of data stored in at least the first storage subsystem to be made in the third storage subsystem, while at least the first circuitry may remain capable of receiving and storing for future execution a received I/O request, such as, for example, an I/O request from a host processor.  
     [0053] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. For example, without departing from this embodiment, the respective numbers of I/O controller cards, tape drives, and/or mass storage may vary from the respective numbers thereof previously described herein as being comprised in system  100 .  
     [0054] Also, for example, in mass storage  72 , the one or more tape drives  46  may comprise a plurality of tape drives, and the one or more tape media  48  may comprise a plurality of tape media. One of these tape drives may encode onto one of these tape media data copied from mass storage  28 A and/or RAID  29 A, and another of these tape drives may encode onto another of these tape media data copied from mass storage  28 B and/or RAID  29 B.  
     [0055] Other modifications are also possible. Accordingly, the claims are intended to cover all such equivalents.