Patent Publication Number: US-2022215791-A1

Title: Shift register having two output signals with phase lagging and driving method thereof, scan driving circuit, display panel and display device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority of Chinese Patent Application No. CN202110009334.5, filed on Jan. 5, 2021, the entire contents of all of which are incorporated herein by reference. 
     FIELD OF THE DISCLOSURE 
     The present disclosure generally relates to the field of display technologies and, in particular, relates to a shift register and a driving method thereof, a scan driving circuit, a display panel, and a display device. 
     BACKGROUND 
     With development of electronic technologies, display panels have been widely used in various electronic products in various fields, such as televisions, mobile phones, computers, personal digital assistants, and other electronic products, becoming an indispensable part of people&#39;s life and work. 
     Existing display panels scan multiple rows of pixels in a pixel array through a scan driving circuit located in a non-display area, to drive the pixel array to display images. However, due to a relatively large layout space occupied by the scan driving circuit, a proportion of the non-display area in the display panels cannot be further reduced, which is not conducive to realization of a full screen. 
     BRIEF SUMMARY OF THE DISCLOSURE 
     One aspect of the present disclosure provides a shift register, including: an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal; a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal; a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal; a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to the voltage of the first node; a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node; and a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, that a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module. 
     Another aspect of the present disclosure provides a driving method of the disclosed shift register, including: in a first stage, the signal input terminal inputs a low level, the first clock signal terminal inputs a low level, the second clock signal terminal inputs a high level, and the third clock signal terminal inputs a high level, configured to provide the low level input from the signal input terminal to the first node, and provide the low level input from the first clock signal terminal to the second node, so that the first output terminal and the second output terminal both output high levels; in a second stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a high level, the second clock signal terminal inputs a low level, and the third clock signal terminal inputs a high level, configured to provide the high level input from the first clock signal terminal to the second node, so that the first output terminal outputs a low level, and the second output terminal outputs a high level; in a third stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a high level, the second clock signal terminal inputs a high level, and the third clock signal terminal inputs a low level, configured to provide the high level input from the first clock signal terminal to the second node, so that the first output terminal outputs a high level, and the second output terminal outputs a low level; and in a fourth stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a low level, the second clock signal terminal inputs a high level, and the third clock signal terminal inputs a high level, configured to provide the high level input from the input signal terminal to the first node, and provide a low level of the second voltage terminal to the second node, so that the first output terminal and the second output terminal both output high levels. 
     Another aspect of the present disclosure provides a scan driving circuit, including: shift registers, arranged in a cascaded manner, that each of the shift registers includes: an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal; a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal; a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal; a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to the voltage of the first node; a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node; and a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, that a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module; an initial signal line; a first clock signal line; a second clock signal line; and a third clock signal line, that the signal input terminal of a first-stage shift register is electrically connected to the initial signal line; except for the first-stage shift register, the signal input terminal of each stage shift register is electrically connected to one of the second output terminal and the first output terminal of a previous stage shift register; for a 3n-th stage shift register, a first clock signal terminal thereof is electrically connected to the first clock signal line, a second clock signal terminal thereof is electrically connected to the second clock signal line, and a third clock signal terminal thereof is electrically connected to the third clock signal line; for a 3n+1st stage shift register, a first clock signal terminal thereof is electrically connected to the third clock signal line, a second clock signal terminal thereof is electrically connected to the first clock signal line, and a third clock signal terminal thereof is electrically connected to the second clock signal line; for a 3n+2nd stage shift register, a first clock signal terminal thereof is electrically connected to the second clock signal line, a second clock signal terminal thereof is electrically connected to the third clock signal line, and a third clock signal terminal thereof is electrically connected to the first clock signal line; and pulses of the first clock signal line, the second clock signal line, and the third clock signal line do not overlap with each other, and are arranged sequentially in time, that n is 0 or a positive integer. 
     Another aspect of the present disclosure provides a display panel, including: a scan driving circuit, including: shift registers, arranged in a cascaded manner, that each of the shift registers includes: an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal; a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal; a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal; a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to the voltage of the first node; a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node; and a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, that a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module; an initial signal line; a first clock signal line; a second clock signal line; and a third clock signal line, that the signal input terminal of a first-stage shift register is electrically connected to the initial signal line; except for the first-stage shift register, the signal input terminal of each stage shift register is electrically connected to one of the second output terminal and the first output terminal of a previous stage shift register; for a 3n-th stage shift register, a first clock signal terminal thereof is electrically connected to the first clock signal line, a second clock signal terminal thereof is electrically connected to the second clock signal line, and a third clock signal terminal thereof is electrically connected to the third clock signal line; for a 3n+1st stage shift register, a first clock signal terminal thereof is electrically connected to the third clock signal line, a second clock signal terminal thereof is electrically connected to the first clock signal line, and a third clock signal terminal thereof is electrically connected to the second clock signal line; for a 3n+2nd stage shift register, a first clock signal terminal thereof is electrically connected to the second clock signal line, a second clock signal terminal thereof is electrically connected to the third clock signal line, and a third clock signal terminal thereof is electrically connected to the first clock signal line; and pulses of the first clock signal line, the second clock signal line, and the third clock signal line do not overlap with each other, and are arranged sequentially in time, that n is 0 or a positive integer; a plurality of scan signal lines; and a plurality of pixel driving circuits, that the first output terminal and the second output terminal of the shift registers of the scan driving circuit are electrically connected to the plurality of scan signal lines; and the plurality of scan signal lines is electrically connected to the plurality of pixel driving circuits. 
     Another aspect of the present disclosure provides a display device, including: the disclosed display panel. 
     Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       To more clearly illustrate the technical solution of the present disclosure, the accompanying drawings used in the description of the disclosed embodiments are briefly described hereinafter. The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure. Other drawings may be derived from such drawings by a person with ordinary skill in the art without creative efforts. 
         FIG. 1  is a schematic structural view of an exemplary shift register according to various embodiments of the present disclosure; 
         FIG. 2  is a timing diagram of a signal output from a second output module and a signal output from a first output module according to various embodiments of the present disclosure; 
         FIG. 3  is a schematic structural view of an exemplary pixel driving circuit according to various embodiments of the present disclosure; 
         FIG. 4  is a timing diagram of signals input from an input terminal Si and an input terminal S 2  in an exemplary pixel driving circuit shown in  FIG. 3 ; 
         FIG. 5  is a schematic structural view of an exemplary shift register according to various embodiments of the present disclosure; 
         FIG. 6  is a signal timing diagram of a first clock signal terminal CLK 1 , a second clock signal terminal CLK 2 , and a third clock signal terminal CLK 3  according to various embodiments of the present disclosure; 
         FIG. 7  is a signal timing diagram of each node in an exemplary shift register according to various embodiments of the present disclosure; 
         FIG. 8  is an enlarged view of a signal of a first node N 1  according to various embodiments of the present disclosure; 
         FIG. 9  is a signal timing diagram of a first output terminal OUT 1  and a second output terminal OUT 2  when a capacitance of a second capacitor C 2  and a capacitance of a third capacitor C 3  are equal according to various embodiments of the present disclosure; 
         FIG. 10  is a signal timing diagram of a first output terminal OUT 1  and a second output terminal OUT 2  when a capacitance of a second capacitor C 2  is smaller than a capacitance of a third capacitor C 3  according to various embodiments of the present disclosure; 
         FIG. 11  is a schematic structural view of an exemplary shift register according to various embodiments of the present disclosure; 
         FIG. 12  is a signal timing diagram of each node in an exemplary shift register according to various embodiments of the present disclosure; 
         FIG. 13  is a schematic structural view of a layout of an exemplary shift register according to various embodiments of the present disclosure; 
         FIG. 14  is a flowchart of a driving method of an exemplary shift register according to various embodiments of the present disclosure; 
         FIG. 15  is a schematic structural view of an exemplary scan driving circuit according to various embodiments of the present disclosure; 
         FIG. 16  is a timing diagram of signals output from each output terminal of cascaded shift registers shown in  FIG. 15 ; 
         FIG. 17  is a schematic structural view of an exemplary scan driving circuit according to various embodiments of the present disclosure; 
         FIG. 18  is a timing diagram of signals output from each output terminal of cascaded shift registers shown in  FIG. 17 ; 
         FIG. 19  is a schematic structural top view of an exemplary display panel according to various embodiments of the present disclosure; and 
         FIG. 20  is a schematic structural view of an exemplary display device according to various embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     As described in the background, in existing display panels, a layout space of a scan driving circuit is relatively large. The scan driving circuit includes a plurality of cascaded shift registers. An output terminal of each shift register is electrically connected to a gate line. The plurality of shift registers scans multiple rows of pixels, through outputting scan signals to a plurality of gate lines respectively. Since each shift register can only output a scan signal to one gate line, the layout space of the multiple shift registers, that is, the scan driving circuit, is relatively large. 
     Based on this, the present disclosure provides a shift register and a driving method thereof, a scan driving circuit, a display panel, and a display device to overcome the above-mentioned problems. The shift register includes: 
     an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal; 
     a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal; 
     a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal; 
     a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to the voltage of the first node; 
     a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node; and 
     a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node. 
     A phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module. 
     Due to action of the same input module, control module, and reset module, the first output module and the second output module can output two signals respectively, and the phase of the signal output from the second output module lags behind the phase of the signal output from the first output module, and does not overlap with the phase of the signal output from the first output module. Therefore, the signals output from the first output module and the second output module can be electrically connected to two gate lines respectively to scan two rows of pixels separately. Compared with the solution of scanning two rows of pixels through two shift registers in the prior art, the solution of scanning two rows of pixels through one shift register in the present disclosure greatly reduces a layout area of the scan driving circuit. 
     The above is the core idea of the present disclosure. To make the above objectives, features, and advantages of the present disclosure clearer and easier to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. The described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present disclosure. 
     The embodiments of the present disclosure provide a shift register.  FIG. 1  is a schematic structural view of an exemplary shift register according to various embodiments of the present disclosure. As shown in  FIG. 1 , the shift register includes an input module  10 , a control module  20 , a reset module  30 , a first output module  40 , a second output module  50 , and a stabilization module  60 . 
     The input module  10  is electrically connected to a signal input terminal IN and a first clock signal terminal CLK 1 , and is configured to provide a signal of the signal input terminal IN to a first node N 1  in response to a signal of the first clock signal terminal CLK 1 . 
     The control module  20  is electrically connected to a first voltage terminal VGH, a second clock signal terminal CLK 2 , and a second node N 2 , and is configured to provide a voltage of the first voltage terminal VGH to the first node N 1  in response to a voltage of the second node N 2  and a signal of the second clock signal terminal CLK 2 . 
     The reset module  30  is electrically connected to a second voltage terminal VGL and the first clock signal terminal CLK 1  to provide a voltage of the second voltage terminal VGL to the second node N 2  in response to the signal of the first clock signal terminal CLK 1 . 
     The first output module  40  is electrically connected to the first node N 1  and the second clock signal terminal CLK 2 , and is configured to provide the signal of the second clock signal terminal CLK 2  to a first output terminal OUT 1  in response to the voltage of the first node N 1 . 
     The second output module  50  is electrically connected to the first node N 1  and a third clock signal terminal CLK 3 , and is configured to provide a signal of the third clock signal terminal CLK 3  to a second output terminal OUT 2  in response to the voltage of the first node N 1 . 
     The stabilization module  60  is electrically connected to the second node N 2  and the first voltage terminal VGH, and is configured to provide the voltage of the first voltage terminal VGH to the first output terminal OUT 1  and the second output terminal OUT 2  in response to the voltage of the second node N 2 . 
     In addition, a phase of a signal output from the second output module  50  lags behind a phase of a signal output from the first output module  40 , and the phase of the signal output from the second output module  50  does not overlap with the phase of the signal output from the first output module  40 . That is, a phase of a signal output from the second output terminal OUT 2  lags behind a phase of a signal output from the first output terminal OUT 1 , and the phase of the signal output from the second output terminal OUT 2  does not overlap with the phase of the signal output from the first output terminal OUT 1 . 
     Due to action under the same input module  10 , control module  20 , and reset module  30 , the first output module  40  and the second output module  50  can respectively output two signals, and the phase of the signal output from the second output module  50  lags behind the phase of the signal output from the first output module  40 , and does not overlap with the phase of the signal output from the first output module  40 . Therefore, the signals output from the first output module  40  and the second output module  50  can be electrically connected to two gate lines respectively to scan two rows of pixels respectively. 
     Compared with the solution of scanning two rows of pixels through two shift registers in the prior art, the solution of scanning two rows of pixels through one shift register in the present disclosure greatly reduces the layout area of the scan driving circuit. Therefore, a layout space occupation ratio of the scan driving circuit is reduced, so that a non-display area in the display panel can be further reduced, which is more conducive to realization of a full screen. 
     In addition, in response to the voltage of the second node N 2 , the stabilization module  60  in the present disclosure provides the voltage of the first voltage terminal VGH to the first output terminal OUT 1  and the second output terminal OUT 2 , respectively, so that when the output signal of the first output terminal OUT 1  and the output signal of the second output terminal OUT 2  are high levels, stable outputs of the first output terminal OUT 1  and the second output terminal OUT 2  are ensured. 
       FIG. 2  is a timing diagram of a signal output from a second output module and a signal output from a first output module according to various embodiments of the present disclosure. In some embodiments of the present disclosure, as shown in  FIG. 2 , a pulse width L 2  of the signal output from the second output module  50  is equal to a pulse width L 1  of the signal output from the first output module  40 , so that there is no difference in signal characteristics between two signals successively output from a same shift register. 
     The present disclosure is not limited to this. In practical applications, under influence of factors such as manufacturing process differences and circuit leakage currents, the pulse width of the signal output from the second output module  50  may also be slightly different from the pulse width of the signal output from the first output module  40 , or, according to different application requirements, the pulse width L 2  of the signal output from the second output module  50  may be different from the pulse width L 1  of the signal output from the first output module  40 , which will not be repeated here. 
     In some application scenarios that there is no high requirement for the layout area of the scan driving circuit, that is, in some display panels with a larger applicable scan driving circuit layout space, the first output terminal OUT 1  and the second output terminal OUT 2  can be provided to pixel driving circuits of a row of pixels as different driving signals of the pixel driving circuits. 
       FIG. 3  is a schematic structural view of an exemplary pixel driving circuit according to various embodiments of the present disclosure. As shown in  FIG. 3 , a pixel driving circuit includes transistors M 1  to M 6 , which drive a light emitting device  30  to emit light, under control of input signals of input terminals S 1 , S 2 , Ref, and Emit. The light emitting device  30  may be an LED or an OLED or the like. 
       FIG. 4  is a timing diagram of signals input from an input terminal Si and an input terminal S 2  in an exemplary pixel driving circuit shown in  FIG. 3 . As shown in  FIG. 4 , a phase of a signal input from the input terminal S 2  lags behind a phase of a signal input from the input terminal S 1 , and the phase of the signal input from the input terminal Si does not overlap the phase of the signal input from the input terminal S 2 . Therefore, the signal output from the second output terminal OUT 2  can be used as the signal input from the input terminal S 2 , and the signal output from the first output terminal OUT 1  can be used as the signal input from the input terminal S 1 . 
       FIG. 5  is a schematic structural diagram of an exemplary shift register according to various embodiments of the present disclosure. In some embodiments of the present disclosure, as shown in  FIG. 5 , the stabilization module  60  includes a first transistor M 1 , a second transistor M 2 , and a first capacitor C 1 . The first output module  40  includes a third transistor M 3  and a second capacitor C 2 . The second output module  50  includes a fourth transistor M 4  and a third capacitor C 3 . The input module  10  includes a seventh transistor M 7  and an eighth transistor M 8 . The control module  20  includes a ninth transistor M 9  and a tenth transistor M 10 . The reset module  30  includes an eleventh transistor M 11 . 
     A first terminal of the first transistor M 1  is electrically connected to the first voltage terminal VGH, a second terminal of the first transistor M 1  is electrically connected to the first output terminal OUT 1 , and a control terminal of the first transistor M 1  is electrically connected to the second node N 2 . A first terminal of the second transistor M 2  is electrically connected to the first voltage terminal VGH, a second terminal of the second transistor M 2  is electrically connected to the second output terminal OUT 2 , and a control terminal of the second transistor M 2  is electrically connected to the second node N 2 . A first plate of the first capacitor C 1  is electrically connected to the first voltage terminal VGH, and a second plate of the first capacitor C is electrically connected to the second node N 2 . 
     A first terminal of the third transistor M 3  is electrically connected to the first output terminal OUT 1 , a second terminal of the third transistor M 3  is electrically connected to the second clock signal terminal CLK 2 , and a control terminal of the third transistor M 3  is electrically connected to the first node N 1 . A first plate of the second capacitor C 2  is electrically connected to the first output terminal OUT 1 , and a second plate of the second capacitor C 2  is electrically connected to the control terminal of the third transistor M 3 . A first terminal of the fourth transistor M 4  is electrically connected to the second output terminal OUT 2 , a second terminal of the fourth transistor M 4  is electrically connected to the third clock signal terminal CLK 3 , and a control terminal of the fourth transistor M 4  is electrically connected to the first node N 1 . A first plate of the third capacitor C 3  is electrically connected to the second output terminal OUT 2 , and a second plate of the third capacitor C 3  is electrically connected to the control terminal of the fourth transistor M 4 . 
     A first terminal of the seventh transistor M 7  is electrically connected to the signal input terminal IN, a second terminal of the seventh transistor M 7  is electrically connected to the first node N 1 , and a control terminal of the seventh transistor M 7  is electrically connected to the first clock signal terminal CLK 1 . A first terminal of the eighth transistor M 8  is electrically connected to the first clock signal terminal CLK 1 , a second terminal of the eighth transistor M 8  is electrically connected to the second node N 2 , and a control terminal of the eighth transistor M 8  is electrically connected to the first node N 1 . 
     A first terminal of the ninth transistor M 9  is electrically connected to the first voltage terminal VGH, and a control terminal of the ninth transistor M 9  is electrically connected to the second node N 2 . A first terminal of the tenth transistor M 10  is electrically connected to a second terminal of the ninth transistor M 9 , a second terminal of the tenth transistor M 10  is electrically connected to the first node N 1 , and a control terminal of the tenth transistor M 10  is electrically connected to the second clock signal terminal CLK 2 . 
     A first terminal of the eleventh transistor M 11  is electrically connected to the second voltage terminal VGL, a second terminal of the eleventh transistor M 11  is electrically connected to the second node N 2 , and a control terminal of the eleventh transistor M 11  is electrically connected to the first clock signal terminal CLK 1 . 
       FIG. 5  only takes a circuit structure of a shift register as an example, and is not limited to this. In other embodiments, the shift register may also have other circuit structures, as long as it can realize functions of each module of the shift register. 
     In some embodiments of the present disclosure, as shown in  FIG. 5 , the first transistor Ml, the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the seventh transistor M 7 , the eighth transistor M 8 , the ninth transistor M 9 , the tenth transistor M 10 , and the eleventh transistor M 11  are all PMOS transistors. However, the present disclosure is not limited to this. In other embodiments, the first transistor Ml, the second transistor M 2 , the third transistor M 3 , the four transistors M 4 , the seventh transistor M 7 , the eighth transistor M 8 , the ninth transistor M 9 , the tenth transistor M 10 , and the eleventh transistor M 11  may all be NMOS transistors, or some of the transistors are NMOS transistors and some of the transistors are PMOS transistors. 
     When types of the transistors are different, for each module in the shift register to realize the above-mentioned function, waveforms or levels of signals that control the transistors need to be different. For example, a signal that controls a PMOS transistor to be turned on is a low level, a signal that controls a PMOS transistor to be turned off is a high level, a signal that controls an NMOS transistor to be turned on is a high level, and a signal that controls an NMOS transistor to be turned off is a low level. 
       FIG. 6  is a signal timing diagram of a first clock signal terminal CLK 1 , a second clock signal terminal CLK 2 , and a third clock signal terminal CLK 3  according to various embodiments of the present disclosure. In the embodiments of the present disclosure, as shown in  FIG. 6 , the first clock signal terminal CLK 1  provides a first clock signal, the second clock signal terminal CLK 2  provides a second clock signal, and the third clock signal terminal CLK 3  provides a third clock signal. Pulses of the first clock signal, the second clock signal, and the third clock signal do not overlap with each other, and are arranged sequentially in time, so that the phase of the signal output from the second output terminal OUT 2  lags behind the phase of the signal output from the first output terminal OUT 1 , and the phase of the signal output from the first output terminal OUT 1  and the phase of the signal output from the second output terminal OUT 2  do not overlap with each other. Optionally, a duty cycle of the first clock signal is greater than ¼, and less than or equal to ⅓. As shown in  FIG. 6 , the duty cycle of the first clock signal is a ratio of a low level time T 1  over one cycle time T. 
     In some embodiments of the present disclosure, as shown in  FIG. 5 , when the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the seventh transistor M 7 , the eighth transistor M 8 , the ninth transistor M 9 , the tenth transistor M 10 , and the eleventh transistor M 11  are PMOS transistors, the input module  10  responds to a low level of the first clock signal terminal CLK 1  to provide a signal of the input signal terminal IN to the first node N 1 , the control module  20  responds to a low level of the second clock signal terminal CLK 2  and a low level of the second node N 2  to provide a first voltage V GH  of the first voltage terminal V GH  to the first node N 1 , and the reset module  30  responds to a low level of the first clock signal terminal CLK 1  to provide a second voltage V GL  of the second voltage terminal V GL  to the second node N 2 . The first voltage V GH  is greater than the second voltage V GL , optionally, 6 V≤V GH ≤14 V, for example, V GH  is 8 V, or V GH  is 10 V; and −14 V≤V GL ≤−6 V, for example, V GL  is −10 V, or V GL  is −7 V. The first output module  40  responds to a first low level and a second low level of the first node N 1  to provide the signal of the second clock signal terminal CLK 2  to the first output terminal OUT 1 , and the second output module  50  responds at least to a third low level of the first node N 1  to provide the signal of the third clock signal terminal CLK 3  to the second output terminal OUT 2 , where the second low level is less than the first low level, and the third low level is less than the second low level. 
     The above process, that is, a working process of the shift register, will be described below in conjunction with a timing diagram of each node signal in the shift register and the structure of the shift register shown in  FIG. 5 . 
       FIG. 7  is a signal timing diagram of each node in an exemplary shift register according to various embodiments of the present disclosure, and  FIG. 8  is an enlarged diagram of a signal of a first node N 1  according to various embodiments of the present disclosure. As shown in  FIG. 7  and  FIG. 8 , in a first stage T 1 , the signal input from the input signal terminal IN is a low level, and the first clock signal input from the first clock signal terminal CLK 1  is a low level. The turned-on seventh transistor M 7  provides the low level of the input signal terminal IN to the first node N 1 , so that the first node N 1  is at a first low level V 1 , and the first low level V 1  turns on the third transistor M 3  and the fourth transistor M 4 . The turned-on third transistor M 3  transmits the second clock signal of the second clock signal terminal CLK 2 , that is, a high level, to the first output terminal OUT 1 , so that the first output terminal OUT 1  outputs a high level. The turned-on fourth transistor M 4  transmits the third clock signal of the third clock signal terminal CLK 3 , that is, a high level, to the second output terminal OUT 2 , so that the second output terminal OUT 2  outputs a high level. At a same time, the turned-on eleventh transistor M 11  provides the second voltage to the second node N 2 , so that the second node N 2  is at a low level, the turned-on first transistor M 1  transmits the first voltage of the first voltage terminal VGH, that is, a high level, to the first output terminal OUT 1 , and the turned-on second transistor M 2  transmits the first voltage of the first voltage terminal VGH, that is, a high level, to the second output terminal OUT 2 , thereby further ensuring stability of the high levels output from the first output terminal OUT 1  and the second output terminal OUT 2 . 
     In a second stage T 2 , the signal input from the input signal terminal IN is a high level, the first clock signal input from the first clock signal terminal CLK 1  is a high level, and the seventh transistor M 7  and the eleventh transistor M 11  are turned off. The turned-on eighth transistor M 8  transmits the high level input from the first clock signal terminal CLK 1  to the second node N 2 , so that the first transistor M 1  and the second transistor M 2  are turned off. Under bootstrapping of the second capacitor C 2 , the voltage of the first node N 1  is pulled lower, so that the voltage of the first node N 1  is a second low level V 2 , the second low level V 2  is less than the first low level V 1 , and the second low level turns on the third transistor M 3  and the fourth transistor M 4 . The turned-on third transistor M 3  transmits the second clock signal of the second clock signal terminal CLK 2 , that is, a low level, to the first output terminal OUT 1 , so that the first output terminal OUT 1  outputs a low level. The turned-on fourth transistor M 4  transmits the third clock signal of the third clock signal terminal CLK 3 , that is, a high level, to the second output terminal OUT 2 , so that the second output terminal OUT 2  outputs a high level. 
     In a third stage T 3 , the signal input from the input signal terminal IN is a high level, the first clock signal input from the first clock signal terminal CLK 1  is a high level, and the seventh transistor M 7  and the eleventh transistor M 11  are continuously turned off. The turned-on eighth transistor M 8  transmits the high level input from the first clock signal terminal CLK 1  to the second node N 2 , so that the first transistor M 1  and the second transistor M 2  are turned off. Under bootstrapping of the third capacitor C 3 , the voltage of the first node N 1  is pulled lower, so that the voltage of the first node N 1  is a third low level V 3 , the third low level V 3  is less than the second low level V 2 , and the third low level V 3  turns on the third transistor M 3  and the fourth transistor M 4 . The turned-on third transistor M 3  transmits the second clock signal of the second clock signal terminal CLK 2 , that is, a high level, to the first output terminal OUT 1 , so that the first output terminal OUT 1  outputs a high level. The turned-on fourth transistor M 4  transmits the third clock signal of the third clock signal terminal CLK 3 , that is, a low level, to the second output terminal OUT 2 , so that the second output terminal OUT 2  outputs a low level. 
     In a fourth stage T 4 , the signal input from the input signal terminal IN is a high level, the first clock signal input from the first clock signal terminal CLK 1  is a low level, and the seventh transistor M 7  and the eleventh transistor M 11  are turned on. The turned-on seventh transistor M 7  provides the high level of the input signal terminal IN to the first node N 1 , so that the first node N 1  is at a high level V 0 , and VO is greater than V 1 , so that the eighth transistor M 8 , the third transistor M 3 , and the fourth transistor M 4  are turned off. The turned-on eleventh transistor M 11  transmits the second voltage of the second voltage terminal VGL, that is, a low level, to the second node N 2 , so that the first transistor M 1  and the second transistor M 2  are turned on. The turned-on first transistor M 1  transmits the first voltage of the first voltage terminal VGH to the first output terminal OUT 1 , and the turned-on second transistor M 2  transmits the first voltage of the first voltage terminal VGH to the second output terminal OUT 2 , so that both the first output terminal OUT 1  and the second output terminal OUT 2  output high levels. 
     During operations of the shift register, when the input signal terminal IN inputs a trigger signal (such as a low level period from the input signal terminal IN in  FIG. 5 ) and the signal input from the first clock signal terminal CLK 1  is a low level, the shift register will perform the first stage T 1  to the fourth stage T 4 , so that the first output terminal OUT 1  and the second output terminal OUT 2  output required signals. 
     In some embodiments of the present disclosure, to make a pulse width of the signal output from the first output terminal OUT 1  equals to a pulse width of the signal output from the second output terminal OUT 2 , a capacitance of the second capacitor C 2  and a capacitance of the third capacitor C 3  are equal, and the third transistor M 3  and the fourth transistor M 4  have same aspect ratio and other parameters. In some optional embodiments, a capacitance range of the second capacitor C 2  and the third capacitor C 3  is from about 200 f to about 500 f, preferably about 200 f. 
     However, in practical applications, after bootstrapping of the second capacitor C 2  occurs in the second stage T 2 , compared to the voltage V 1  of the first node N 1  in the first stage T 1 , the voltage of the first node N 1  in the second stage T 2  is lower, and the voltage of the first node N 1  is V 2 . Therefore, a leakage current will occur in the circuit, affecting the voltage of the first node N 1 , causing the voltage of the first node N 1  to rise, thereby causing a delay of a falling edge of the signal output from the second output terminal OUT 2  to be greater than a delay of a falling edge of the signal output from the first output terminal OUT 1 , when the third capacitor C 3  is bootstrapped in the third stage T 3 .  FIG. 9  is a signal timing diagram of a first output terminal OUT 1  and a second output terminal OUT 2  when a capacitance of a second capacitor C 2  and a capacitance of a third capacitor C 3  are equal according to various embodiments of the present disclosure. As shown in  FIG. 9 , a delay time of the falling edge of the signal output from the second output terminal OUT 2  is 402 ns, that is, a falling time between point C and point D is 402 ns. A delay time of the falling edge of the signal output from the first output terminal OUT 1  is 360 ns, that is, a falling time between point A and point B is 360 ns. The delay of the signal output from the output terminal OUT 1  and the delay of the signal output from the second output terminal OUT 2  are caused to be different. 
     Based on this, in some other embodiments of the present disclosure, the capacitance of the third capacitor C 3  is greater than the capacitance of the second capacitor C 2 , so that when the third capacitor C 3  is bootstrapped, the voltage of the first node N 1  is the third low level V 3 , which is lower than the second low level V 2 , to reduce the difference between the delay of the falling edge of the signal output from the second output terminal OUT 2  and the delay of the falling edge of the signal output from the first output terminal OUT 1 . 
       FIG. 10  is a signal timing diagram of a first output terminal OUT 1  and a second output terminal OUT 2  when a capacitance of a second capacitor C 2  is smaller than a capacitance of a third capacitor C 3  according to various embodiments of the present disclosure. As shown in  FIG. 10 , the delay time of the falling edge of the signal output from the second output terminal OUT 2  is 380 ns, that is, a falling time between point G and point H is 380 ns. The delay time of the falling edge of the signal output from the first output terminal OUT 1  is 381 ns, that is, a falling time between point E and point F is 381 ns. The delay of the falling edge of the signal output from the second output terminal OUT 2  is substantially the same as the delay of the falling edge of the signal output from the first output terminal OUT 1 . 
     In some embodiments of the present disclosure, a ratio K of the capacitance of the third capacitor C 3  over the capacitance of the second capacitor C 2  ranges from about 1.01 to about 2. In other embodiments of the present disclosure, to further reduce the difference between the delay of the falling edge of the signal output from the second output terminal OUT 2  and the delay of the falling edge of the signal output from the first output terminal OUT 1 , the ratio K of the capacitance of the third capacitor C 3  over the capacitance of the second capacitor C 2  ranges from about 1.1 to about 1.5, including endpoint values. In other embodiments of the present disclosure, to further reduce the difference between the delay of the falling edge of the signal output from the second output terminal OUT 2  and the delay of the falling edge of the signal output from the first output terminal OUT 1 , the ratio K of the capacitance of the third capacitor C 3  over the capacitance of the second capacitor C 2  ranges from about 1.1 to about 1.2, including endpoint values. The delay of the falling edge of the signal output from the second output terminal OUT 2  and the delay of the signal output from the first output terminal OUT 1  are ensured to be similar or the same, and the difference between the signals output from the two output terminals is reduced. 
     On this basis, in some embodiments of the present disclosure, the capacitance of the second capacitor C 2  is 200 f, and the capacitance of the third capacitor C 3  ranges from about 202 f to about 400 f, including endpoint values. In other embodiments, the capacitance of the third capacitor C 3  ranges from about 220 f to about 300 f, including endpoint values. In other embodiments, the capacitance of the third capacitor C 3  ranges from about 220 f to about 240 f, including endpoint values. 
     A function of the first capacitor C 1  is only to generate a sufficient voltage difference between the first voltage terminal VGH and the second node N 2 , while functions of the second capacitor C 2  and the third capacitor C 3  are to pull down voltages of gates of transistors through bootstrapping. Therefore, the capacitance of the second capacitor C 2  and the third capacitor C 3  can be set larger, that is, the capacitance of the second capacitor C 2  and the third capacitor C 3  can be greater than a capacitance of the first capacitor C 1 . In some optional embodiments, the capacitance of the first capacitor C 1  is 100 f, and the capacitance of the second capacitor C 2  and the third capacitor C 3  is 200 f. 
     To further improve the influence of the leakage current on the voltage of the first node N 1 , and reduce the difference between the delay of the falling edge of the signal output from the second output terminal OUT 2  and the delay of the falling edge of the signal output from the first output terminal OUT 1 , on the basis of the structure shown in  FIG. 5 , in other embodiments of the present disclosure, the first output module  40  further includes the fifth transistor M 5 , and the second output module  50  further includes the sixth transistor M 6 , as shown in  FIG. 11 , which is a schematic structural view of an exemplary shift register according to various embodiments of the present disclosure. 
     A first terminal of the fifth transistor M 5  is electrically connected to the first node N 1 , a second terminal of the fifth transistor M 5  is electrically connected to the control terminal of the third transistor M 3 , and a third node N 3 , and a control terminal of the fifth transistor M 5  is electrically connected to the second voltage terminal VGL. A first terminal of the sixth transistor M 6  is electrically connected to the first node N 1 , a second terminal of the sixth transistor M 6  is electrically connected to the control terminal of the fourth transistor M 4 , and a fourth node N 4 , and a control terminal of the sixth transistor M 6  is electrically connected to the second voltage terminal VGL. 
     In some embodiments of the present disclosure, the fifth transistor M 5  and the sixth transistor M 6  are both PMOS transistors. The present disclosure is not limited to this. In other embodiments, the fifth transistor M 5  and the sixth transistor M 6  may both be NMOS transistors, or, one is a PMOS transistor and the other is an NMOS transistor, which will not be repeated here. 
     Since the fifth transistor M 5  and the sixth transistor M 6  are turned on for a long time under control of a low level of the second voltage terminal VGL, voltages of the third node N 3  and the fourth node N 4  are substantially equal to the voltage of the first node N 1 . However, there is a certain resistance between a source and a drain of the turned-on fifth transistor M 5  and sixth transistor M 6 . Therefore, even if the voltages of the third node N 3  and the fourth node N 4  are pulled down due to capacitor bootstrapping, it will not have much influence on the voltage of the first node N 1 . Since the voltage of the first node N 1  is basically unaffected, the influence of the leakage current on the voltages of the third node N 3  and the fourth node N 4  will also be improved to a certain extent, thereby reducing the difference between the delay of the falling edge of the signal output from the first output terminal OUT 1  and the delay of the falling edge of the signal output from the second output terminal OUT 2 . 
       FIG. 12  is a signal timing diagram of each node in an exemplary shift register according to various embodiments of the present disclosure. A working process of the shift register with the structure shown in  FIG. 11  is basically the same as that of the shift register with the structure shown in  FIG. 5 . However, as shown in  FIG. 12 , in the second stage T 2 , after the second capacitor C 2  is bootstrapped, the voltage of the third node N 3  is pulled lower, and the voltage of the third node N 3  is lower than the voltage of the first node N 1 ; and in the third stage T 3 , after the third capacitor C 3  is bootstrapped, the voltage of the fourth node N 4  is pulled lower, and the voltage of the fourth node N 4  is lower than the voltage of the first node N 1 . 
     In some embodiments of the present disclosure, the fifth transistor M 5  and the sixth transistor M 6  are not designed to be differentiated, and the third transistor M 3  and the fourth transistor M 4  are not designed to be differentiated, that is, parameters such as the aspect ratio of the fifth transistor M 5  and the sixth transistor M 6  are the same, and parameters such as the aspect ratio of the third transistor M 3  and the fourth transistor M 4  are the same. Only through the difference in the capacitance of the second capacitor C 2  and the third capacitor C 3 , the difference between the delay of the falling edge of the signal output from the second output terminal OUT 2  and the delay of the falling edge of the signal output from the first output terminal OUT 1  is reduced. However, the present disclosure is not limited to this. In other embodiments, the fifth transistor M 5  and the sixth transistor M 6  can also be designed differently, such as making the fifth transistor M 5  and the sixth transistor M 6  have different parameters such as the aspect ratio, to reduce the difference between the delay of the falling edge of the signal output from the second output terminal OUT 2  and the delay of the falling edge of the signal output from the first output terminal OUT 1 . In other embodiments, the third transistor M 3  and the fourth transistor M 4  can also be designed differently. For example, the third transistor M 3  and the fourth transistor M 4  have different parameters such as the aspect ratio to reduce the difference between the delay of the falling edge of the output signal from the second output terminal OUT 2  and the delay of the falling edge of the signal output from the first output terminal OUT 1 . 
       FIG. 13  is a schematic structural diagram of a layout of an exemplary shift register according to various embodiments of the present disclosure. In some embodiments of the present disclosure, as shown in  FIG. 13 , an area where the third transistor M 3  is located is a first area A 1 , and an area where the fourth transistor M 4  is located is a second area A 2 . The first area A 1  and the second area A 2  are arranged along a first direction Y. A size of the first area A 1  in the first direction Y is W 1 , and a size in a second direction X is L 1 . A size of the second area in the first direction Y is W 2 , and a size in the second direction X is L 2 , where W 1 &gt;W 2  and L 1 &lt;L 2 . The first direction Y intersects the second direction X. 
     An area where the second capacitor C 2  is located is a third area A 3 , and an area where the third capacitor C 3  is located is a fourth area A 4 . The third area A 3  and the fourth area A 4  are both L-shaped. The third area A 3  includes a first sub-area A 31  extending in the first direction Y and a second sub-area A 32  extending in the second direction X. The fourth area includes a third sub-area A 41  extending in the first direction Y and a fourth sub-area A 42  extending in the second direction X. The third area A 3  half-surrounds the first area A 1 , and the fourth area A 4  half-surrounds the second area A 2 . 
     A size of the first sub-area A 31  in the first direction Y is L 3 , and a size of the second sub-area A 32  in the second direction X is L 4 . A size of the third sub-area A 41  in the first direction Y is L 5 , and a size of the fourth sub-area A 42  in the second direction X is L 6 , where |L 1 -L 2 |&gt;|W 1 -W 2 |,|L 4 -L 6 |&gt;L 3 -L 5 |, so that the capacitance of the third capacitor C 3  is greater than that of the second capacitor C 2 . 
     An area where a transistor is located in  FIG. 13  refers to an area occupied by a gate, source, drain, and active layer of the transistor, and an overlapping portion between the areas where transistors are located refers to a portion between the transistors that are electrically connected to each other. Non-overlapping between areas where the transistors are does not mean that there is not a connection relationship between the transistors. The connection relationship can also be achieved through wiring between the areas. To avoid too many wires, no description is given on the wiring, etc. 
     The embodiments of the present disclosure also provide a driving method of a shift register, which is applied to the shift register provided in any of the above embodiments.  FIG. 14  is a flowchart of a driving method of an exemplary shift register according to various embodiments of the present disclosure. As shown in  FIG. 14 , the driving method includes S 101 , S 102 , S 103 , and S 104 . 
     S 101 : in a first stage, a signal input terminal inputs a low level, a first clock signal terminal inputs a low level, a second clock signal terminal inputs a high level, and a third clock signal terminal inputs a high level, configured to provide the low level input from the signal input terminal to a first node, and provide the low level input from the first clock signal terminal to a second node, so that both a first output terminal and a second output terminal output high levels. 
     S 102 : in a second stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a high level, the second clock signal terminal inputs a low level, and the third clock signal terminal inputs a high level, configured to provide the high level input from the first clock signal terminal to the second node, so that the first output terminal outputs a low level, and the second output terminal outputs a high level. 
     S 103 : in a third stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a high level, the second clock signal terminal inputs a high level, and the third clock signal terminal inputs a low level, configured to provide the high level input from the first clock signal terminal to the second node, so that the first output terminal outputs a high level and the second output terminal outputs a low level. 
     S 104 : in a fourth stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a low level, the second clock signal terminal inputs a high level, and the third clock signal terminal inputs a high level, configured to provide the high level input from the signal input terminal to the first node, and provide a low level of the second voltage terminal to the second node, so that both the first output terminal and the second output terminal output high levels. 
     Referring to  FIG. 5  and  FIG. 7 , in the first stage T 1 , the signal input from the input signal terminal IN is a low level, the first clock signal input from the first clock signal terminal CLK 1  is a low level, and the turned-on seventh transistor M 7  provides the low level of the input signal terminal IN to the first node N 1 , so that the first node N 1  is at the first low level V 1 , and the first low level V 1  turns on the third transistor M 3  and the fourth transistor M 4 . The turned-on third transistor M 3  transmits the second clock signal of the second clock signal terminal CLK 2 , that is, a high level, to the first output terminal OUT 1 , so that the first output terminal OUT 1  outputs a high level. The turned-on fourth transistor M 4  transmits the third clock signal of the third clock signal terminal CLK 3 , that is, a high level, to the second output terminal OUT 2 , so that the second output terminal OUT 2  outputs a high level. At a same time, the turned-on eleventh transistor M 11  provides the second voltage to the second node N 2 , so that the second node N 2  is at a low level, the turned-on first transistor M 1  transmits the first voltage of the first voltage terminal VGH to the first output terminal OUT 1 , and the turned-on second transistor M 2  transmits the first voltage of the first voltage terminal VGH, that is, a high level, to the second output terminal OUT 2 , thereby further ensuring the stability of the high levels output from the first output terminal OUT 1  and the second output terminal OUT 2 . 
     In the second stage T 2 , the signal input from the input signal terminal IN is a high level, the first clock signal input from the first clock signal terminal CLK 1  is a high level, and the seventh transistor M 7  and the eleventh transistor M 11  are turned off. The turned on eighth transistor M 8  transmits the high level input from the first clock signal terminal CLK 1  to the second node N 2 , so that the first transistor M 1  and the second transistor M 2  are turned off. Under bootstrapping of the second capacitor C 2  and the third capacitor C 3 , the voltage of the first node N 1  is pulled lower, so that the voltage of the first node N 1  is the second low level V 2 , the second low level V 2  is less than the first low level V 1 , and the second low level turns on the third transistor M 3  and the fourth transistor M 4 . The turned-on third transistor M 3  transmits the second clock signal of the second clock signal terminal CLK 2 , that is, a low level, to the first output terminal OUT 1 , so that the first output terminal OUT 1  outputs a low level. The turned-on fourth transistor M 4  transmits the third clock signal of the third clock signal terminal CLK 3 , that is, a high level, to the second output terminal OUT 2 , so that the second output terminal OUT 2  outputs a high level. 
     In the third stage T 3 , the signal input from the input signal terminal IN is a high level, the first clock signal input from the first clock signal terminal CLK 1  is a high level, and the seventh transistor M 7  and the eleventh transistor M 11  are continuously turned off. The turned-on eighth transistor M 8  transmits the high level input from the first clock signal terminal CLK 1  to the second node N 2 , so that the first transistor M 1  and the second transistor M 2  are turned off. Under bootstrapping of the second capacitor C 2  and the third capacitor C 3 , the voltage of the first node N 1  is pulled lower, so that the voltage of the first node N 1  is the third low level V 3 , the third low level V 3  is less than the second low level V 2 , and the third low level V 3  turns on the third transistor M 3  and the fourth transistor M 4 . The turned-on third transistor M 3  transmits the second clock signal of the second clock signal terminal CLK 2 , that is, a high level, to the first output terminal OUT 1 , so that the first output terminal OUT 1  outputs a high level. The turned-on fourth transistor M 4  transmits the third clock signal of the third clock signal terminal CLK 3 , that is, a low level, to the second output terminal OUT 2 , so that the second output terminal OUT 2  outputs a low level. 
     In the fourth stage T 4 , the signal input from the input signal terminal IN is a high level, the first clock signal input from the first clock signal terminal CLK 1  is a low level, and the seventh transistor M 7  and the eleventh transistor M 11  are turned on. The turned on seventh transistor M 7  provides the high level of the input signal terminal IN to the first node N 1 , so that the first node N 1  is at the high level V 0 , and V 0  is greater than V 1 , so that the eighth transistor M 8 , the third transistor M 3 , and the fourth transistor M 4  are turned off. The turned-on eleventh transistor M 11  transmits the second voltage of the second voltage terminal VGL, that is, a low level, to the second node N 2 , so that the first transistor M 1  and the second transistor M 2  are turned on. The turned-on first transistor M 1  transmits the first voltage of the first voltage terminal VGH to the first output terminal OUT 1 , and the turned-on second transistor M 2  transmits the first voltage of the first voltage terminal VGH, that is, a high level, to the second output terminal OUT 2 , so that both the first output terminal OUT 1  and the second output terminal OUT 2  output high levels. 
     The first output terminal OUT 1  and the second output terminal OUT 2  can respectively output two signals, and the phase of the signal output from the second output terminal OUT 2  lags behind the phase of the signal output from the first output terminal OUT 1 , and does not overlap the phase of the signal output from the first output terminal OUT 1 . Therefore, the signals output from the first output terminal OUT 1  and the second output terminal OUT 2  can be electrically connected to two gate lines, respectively, to scan two rows of pixels respectively. 
     In addition, when the second node N 2  is at a low level, the turned-on first transistor M 1  transmits the first voltage of the first voltage terminal VGH, that is, a high level, to the first output terminal OUT 1 , and the turned-on second transistor M 2  transmits the first voltage of the first voltage terminal VGH, that is, a high level, to the second output terminal OUT 2 , thereby further ensuring the stability of the high levels output from the first output terminal OUT 1  and the second output terminal OUT 2 . 
     The embodiments of the present disclosure also provide a scan driving circuit.  FIG. 15  is a schematic structural diagram of an exemplary scan driving circuit according to various embodiments of the present disclosure. As shown in  FIG. 15 , the scan driving circuit includes shift registers ASG 1  to ASGN (N≤ 2 ) arranged in multiple cascaded stages, an initial signal line STV, a first clock signal line XCLK 1 , a second clock signal line XCLK 2 , and a third clock signal line XCLK 3 , where the shift registers are the shift register provided by any of the above embodiments. 
     In some embodiments of the present disclosure, as shown in  FIG. 15 , the signal input terminal IN of a first-stage shift register ASG 1  is electrically connected to the initial signal line STV, and the initial signal line STV is configured to input a signal to the signal input terminal IN. Except for the first-stage shift register ASG 1 , the signal input terminal IN of each stage shift register is electrically connected to the second output terminal OUT 2  of a previous stage shift register to use a signal output from the second output terminal OUT 2  of the previous stage shift register as a signal of the signal input terminal IN of a next stage shift register, so that the cascaded shift registers ASG 1  to ASGN sequentially output signals. 
     For a 3n-th-stage shift register, a first clock signal terminal CLK 1  thereof is electrically connected to the first clock signal line XCLK 1 , a second clock signal terminal CLK 2  thereof is electrically connected to the second clock signal line XCLK 2 , and a third clock signal terminal CLK 3  thereof is electrically connected to the third clock signal line XCLK 3 . For a 3n+1st-stage shift register, a first clock signal terminal CLK 1  thereof is electrically connected to the third clock signal line XCLK 3 , a second clock signal terminal CLK 2  thereof is electrically connected to the first clock signal line XCLK 1 , and a third clock signal terminal CLK 3  thereof is electrically connected to the second clock signal line XCLK 2 . For a 3n+2nd stage shift register, a first clock signal terminal CLK 1  thereof is electrically connected to the second clock signal line XCLK 2 , a second clock signal terminal CLK 2  thereof is electrically connected to the third clock signal line XCLK 3 , and a third clock signal terminal CLK 3  thereof is electrically connected to the first clock signal line XCLK 1 . The n is 0 or a positive integer. 
     As shown in  FIG. 15 , when n is equal to 0, for the first-stage shift register ASG 1 , a first clock signal terminal CLK 1  thereof is electrically connected to the third clock signal line XCLK 3 , a second clock signal terminal CLK 2  thereof is electrically connected to the first clock signal line XCLK 1 , and a third clock signal terminal CLK 3  thereof is electrically connected to the second clock signal line XCLK 2 . For a second-stage shift register ASG 2 , a first clock signal terminal CLK 1  thereof is electrically connected to the second clock signal line XCLK 2 , a second clock signal terminal CLK 2  thereof is electrically connected to the third clock signal line XCLK 3 , and a third clock signal terminal CLK 3  thereof is electrically connected to the first clock signal line XCLK 1 . When n is equal to 1, for a third-stage shift register ASG 3 , a first clock signal terminal CLK 1  thereof is electrically connected to the first clock signal line XCLK 1 , a second clock signal terminal CLK 2  thereof is electrically connected to the second clock signal line XCLK 2 , and a third clock signal terminal CLK 3  thereof is electrically connected to the third clock signal line XCLK 3 . Other shift registers can be deduced by analogy, which will not be repeated here. 
       FIG. 16  is a timing diagram of signals output from each output terminal of cascaded shift registers shown in  FIG. 15 . As shown in  FIG. 16 , not only the phases of the signals output from the first output terminal OUT 1  and the second output terminal OUT 2  of a same shift register do not overlap with each other, but also the phases of the signals output from the first output terminal OUT 1  and the second output terminal OUT 2  of different shift registers do not overlap with each other. Based on this, the signals output from the output terminals of the cascaded shift registers can be connected to multiple gate lines in a display panel, respectively, to provide scan signals to multiple rows of pixels in the display panel. 
     The present disclosure is not limited to this.  FIG. 17  is a schematic structural view of an exemplary scan driving circuit according to various embodiments of the present disclosure. In other embodiments, as shown in  FIG. 17 , the signal input terminal IN of the first-stage shift register ASG 1  is electrically connected to the initial signal line STV, and the initial signal line STV is configured to input a signal to the signal input terminal IN. Except for the first-stage shift register ASG 1 , the signal input terminal IN of each stage shift register is electrically connected to the first output terminal OUT 1  of the previous stage shift register to use a signal output from the first output terminal OUT 1  of the previous stage shift register as a signal of the signal input terminal IN of the next stage shift register. 
       FIG. 18  is a timing diagram of signals output from each output terminal of cascaded shift registers shown in  FIG. 17 . As shown in  FIG. 18 , the phases of the signals output from the first output terminal OUT 1  and the second output terminal OUT 2  of a same shift register do not overlap with each other. However, the phases of the signal output from the first output terminal OUT 1  of the next stage shift register and the signal output from the second output terminal OUT 2  of the previous stage shift register overlap with each other. Based on this, the signals output from the first output terminal OUT 1  and the second output terminal OUT 2  of a same shift register can be provided to pixel driving circuits of a same row of pixels, as the signals of the S 1  and S 2  input terminals in the pixel driving circuits, respectively. 
     Based on the above, in the embodiments of the present disclosure, pulses of the first clock signal line XCLK 1 , the second clock signal line XCLK 2 , and the third clock signal line XCLK 3 , do not overlap with each other, and are arranged sequentially in time, so that pulse signals of the first clock signal terminal CLK 1 , the second clock signal terminal CLK 2 , and the third clock signal terminal CLK 3 , do not overlap with each other, and are arranged sequentially in time. 
     The embodiments of the present disclosure also provide a display panel.  FIG. 19  is a schematic diagram of a top view structure of an exemplary display panel according to various embodiments of the present disclosure. As shown in  FIG. 19 , the display panel includes a scan driving circuit  11  provided in the above embodiments, a plurality of scan signal lines G, and a plurality of pixel driving circuits  12 . As shown in  FIG. 19 , the display panel provided by the embodiments of the present disclosure further includes a plurality of data lines D and driving chips  13 , which are not described here. 
     In some embodiments of the present disclosure, the first output terminal OUT 1  and the second output terminal OUT 2  of shift registers of the scan driving circuit  11  are electrically connected to the plurality of scan signal lines G. The plurality of scan signal lines G is electrically connected to the plurality of pixel driving circuits  12 . Optionally, the first output terminal OUT 1  and the second output terminal OUT 2  of a same shift register are respectively electrically connected to two adjacent scan signal lines G, so as to drive pixel driving circuits  12  in two adjacent rows of pixels. 
     The display panel in the embodiments of the present disclosure may be a liquid crystal display panel, an OLED display panel, and the like. When the display panel is the liquid crystal display panel, a pixel driving circuit  12  includes a transistor, and controls whether a pixel emits light to display an image through the transistor. When the display panel is the OLED display panel, as shown in  FIG. 3 , the pixel driving circuit  12  includes at least two connected transistors and one capacitor, and controls a pixel to emit light to display an image through the at least two transistors and one capacitor. 
     In the embodiments of the present disclosure, only the first output terminal OUT 1  and the second output terminal OUT 2  of a same shift register are electrically connected to two adjacent scan signal lines G as an example. However, the present disclosure is not limited to this. In other embodiments, the first output terminal OUT 1  and the second output terminal OUT 2  of a same shift register may also be electrically connected to two non-adjacent scan signal lines G, such as the first output terminal OUT 1  of a first shift register is electrically connected to a first scan signal line G, the second output terminal OUT 2  is electrically connected to a third scan signal line G, the first output terminal OUT 1  of a second shift register is electrically connected to a second scan signal line G, and the second output terminal OUT 2  is electrically connected to a fourth scan signal line G, where the first scan signal line G and the second scan signal line G provide scan signals to pixel driving circuits  12  of pixels in a same row, and the third scan signal line G and the fourth scan signal line G provide scan signals to pixel driving circuits  12  of pixels in a same row. 
     In the embodiments of the present disclosure, only one side of the display panel has a scan driving circuit as an example for description. The present disclosure is not limited to this. In other embodiments, opposite sides of the display panel may have scan driving circuits, which will not be repeated here. 
     The embodiments of the present disclosure also provide a display device including the display panel provided in the above embodiments.  FIG. 20  is a schematic structural diagram of an exemplary display device according to various embodiments of the present disclosure. As shown in  FIG. 20 , a display device P includes, but is not limited to, a full-screen mobile phone, a tablet computer, and a digital camera. Moreover, the display device P may be a liquid crystal display device, an LED display device, an OLED display device, a flexible display device, and the like. 
     Compared with the prior art, the technical solutions provided by the present disclosure have the following advantages. 
     In the shift register and the driving method thereof, the scan driving circuit, the display panel, and the display device, provided by the present disclosure, the first output module and the second output module can respectively output two outputs under action of the same input module, control module, and reset module. The phase of the signal output from the second output module lags behind the phase of the signal output from the first output module, and does not overlap with the phase of the signal output from the first output module. Therefore, the signals output from the first output module and the second output module can be respectively electrically connected to two gate lines to respectively scan two rows of pixels. 
     Compared with the solution of scanning two rows of pixels through two shift registers in the prior art, the solutions of scanning two rows of pixels through one shift register in the present disclosure greatly reduce the layout area of the scan driving circuit. Therefore, the layout space occupation ratio of the scan driving circuit is reduced, so that the non-display area in the display panel can be further reduced, which is more conducive to the realization of a full screen. 
     In addition, the stabilization module of the present disclosure provides the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, thereby ensuring stable output of the first output terminal and the second output terminal. 
     The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on differences from other embodiments, and same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and relevant parts can be referred to the description of the method. 
     The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and general principles defined in this document can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments shown in this document, but should conform to a widest scope consistent with the principles and novel features disclosed in this document.