Patent Publication Number: US-2017365451-A1

Title: Sputtering apparatus and method for forming semiconductor film using sputtering apparatus

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     One embodiment of the present invention relates to a sputtering apparatus and a method for forming a semiconductor film using the sputtering apparatus. 
     Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the present invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, and a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, and a manufacturing method thereof. 
     In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may each include a semiconductor device. 
     2. Description of the Related Art 
     As a semiconductor material that can be used in a transistor, an oxide semiconductor has been attracting attention. For example, Patent Document 1 discloses a semiconductor device whose field-effect mobility (in some cases, simply referred to as mobility or μFE) is improved by stacking a plurality of oxide semiconductor layers, among which the oxide semiconductor layer serving as a channel contains indium and gallium where the proportion of indium is higher than the proportion of gallium. 
     Non-Patent Document 1 discusses a structure in which an active layer of a transistor includes two layers of oxide semiconductors, an In—Zn oxide and an In—Ga—Zn oxide. 
     Non-Patent Document 2 discusses a structure in which an active layer of a transistor includes a metal oxide having an X—O—Y structure. 
     Patent Document 2 proposes a sputtering apparatus for depositing an In—Ga—Zn oxide which is an oxide semiconductor. With the apparatus, the partial pressures of a reaction gas at surfaces of a plurality of targets are set equal in order to perform sputtering of the targets at the same speed. 
     REFERENCE 
     Patent Document 
     
         
         [Patent Document 1] Japanese Published Patent Application No. 2014-007399 
         [Patent Document 2] Japanese Published Patent Application No. 2013-049884 
       
    
     Non-Patent Document 
     
         
         [Non-Patent Document 1] John F. Wager, “Oxide TFTs: A Progress Report”, Information Display 1/16, SID 2016, January/February 2016, Vol. 32, No. 1, pp. 16-21 
         [Non-Patent Document 2] T. Xiao, “Metal Oxide TFT Turnkey Manufacturing Solutions for a-Si TET Lines”, SID 2016 DIGEST, pp. 318-321 
       
    
     SUMMARY OF THE INVENTION 
     In Non-Patent Document 1, a channel-protective bottom-gate transistor achieves a high field-effect mobility (μ=62 cm 2 V −1 s −1 ). An active layer of the transistor is a two-layer stack of an In—Zn oxide and an In—Ga—Zn oxide, and the thickness of the In—Zn oxide where a channel is formed is 10 nm. However, the S value (the subthreshold swing (SS)), which is one of transistor characteristics, is as large as 0.41 V/decade. Moreover, the threshold voltage (Vth), which is also one of transistor characteristics, is −2.9 V, which means that the transistor has a normally-on characteristic. 
     The field-effect mobility of a transistor that includes an oxide semiconductor film as a channel region is preferably as high as possible. However, when the field-effect mobility is increased, the transistor has a problem with its characteristics, that is, the transistor tends to be normally on. Note that “normally on” means a state where a channel exists without application of voltage to a gate electrode and current flows through the transistor. 
     Non-Patent Document 2 discloses, as an example, a structure in which a metal oxide has an X—O—Y structure where X—O having an ionic bond (X represents In, Ga, Zn, Cd, or the like) and Y—O having a covalent bond (Y represents B, Si, Ge, Al, or the like) are integrated. Note that X having a weak bond property to oxygen (O) and Y having a strong bond property to oxygen (O) are integrated, so that oxygen vacancies in the metal oxide are suppressed. 
     Non-Patent Document 2 does not disclose a structure in which X—O and Y—O in the metal oxide are functionally separated. 
     Non-Patent Document 2 discloses a sputtering apparatus in which sputtering using a plurality of targets can be performed at the same speed. In other words, Non-Patent Document 2 does not disclose a sputtering apparatus in which sputtering using a plurality of targets of different materials is performed at different speeds. 
     In view of the above-described problem, an object of one embodiment of the present invention is to provide a novel sputtering apparatus. Another object of one embodiment of the present invention is to provide a novel sputtering apparatus capable of separating functions. Another object of one embodiment of the present invention is to provide a method for forming a semiconductor film using the sputtering apparatus. Another object of one embodiment of the present invention is to provide a method for forming a semiconductor film in which functions can be separated with the use of the sputtering apparatus. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing the novel semiconductor device. 
     Note that the description of the above objects does not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Objects other than the above objects will be apparent from and can be derived from the description of the specification and the like. 
     One embodiment of the present invention is a sputtering apparatus capable of forming a semiconductor film. The sputtering apparatus includes a first target, a first power source connected to the first target, a first shutter facing the first target, a first driver portion connected to the first shutter, a second target, a second power source connected to the second target, a second shutter facing the second target, and a second driver portion connected to the second shutter. The first driver portion and the second driver portion operate in conjunction with each other. 
     In the above embodiment, it is preferable that the first target contain a conductive material and that the second target contain an insulating material. 
     In the above embodiment, it is preferable that the first target contain at least one of indium oxide and zinc oxide and that the second target contain an oxide of an element M (the element M is at least one of aluminum, silicon, boron, gallium, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). 
     Another embodiment of the present invention is a sputtering apparatus capable of forming a semiconductor film. The sputtering apparatus includes a first target, a first power source connected to the first target, a first shutter facing the first target, a first driver portion connected to the first shutter, a second target, a second power source connected to the second target, a second shutter facing the second target, a second driver portion connected to the second shutter, a third target, a third power source connected to the third target, a third shutter facing the third target, and a third driver portion connected to the third shutter. The first driver portion, the second driver portion, and the third driver portion operate in conjunction with each other. 
     In the above embodiment, it is preferable that the first target and the third target contain a conductive material and that the second target contain an insulating material. 
     In the above embodiment, it is preferable that the first target contain indium oxide, that the second target contain an oxide of an element M (the element M is at least one of aluminum, silicon, boron, gallium, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and that the third target contain zinc oxide. 
     Another embodiment of the present invention is a method for forming a semiconductor film using a sputtering apparatus. The sputtering apparatus includes a first target, a first power source connected to the first target, a first shutter facing the first target, a first driver portion connected to the first shutter, a second target, a second power source connected to the second target, a second shutter facing the second target, and a second driver portion connected to the second shutter. The method includes a first step of turning on the first power source, a second step of turning on the second power source, a third step of operating the first driver portion to open the first shutter, and a fourth step of operating the second driver portion to open the second shutter. A period during which the first step is performed and a period during which the second step is performed at least partly overlap with each other. The third step and the fourth step are performed in conjunction with each other. 
     Another embodiment of the present invention is a method for forming a semiconductor film using a sputtering apparatus. The sputtering apparatus includes a first target, a first power source connected to the first target, a first shutter facing the first target, a first driver portion connected to the first shutter, a second target, a second power source connected to the second target, a second shutter facing the second target, a second driver portion connected to the second shutter, a third target, a third power source connected to the third target, a third shutter facing the third target, and a third driver portion connected to the third shutter. The method includes a first step of turning on the first power source, a second step of turning on the second power source, a third step of turning on the third power source, a fourth step of operating the first driver portion to open the first shutter, a fifth step of operating the second driver portion to open the second shutter, and a sixth step of operating the third driver portion to open the third shutter. A period during which the first step is performed, a period during which the second step is performed, and a period during which the third step is performed at least partly overlap with each other. The fourth step, the fifth step, and the sixth step are performed in conjunction with each other. 
     In the above embodiment, it is preferable that the first target contain indium oxide, that the second target contain an oxide of an element M (the element M is at least one of aluminum, silicon, boron, gallium, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), that the third target contain zinc oxide, and that the fourth step, the fifth step, and the sixth step be each independently performed at higher than or equal to room temperature and lower than 200° C. after the output of the first power source in the first step be adjusted, the output of the second power source in the second step be adjusted, and the output of the third power source in the third step be adjusted. 
     In the above embodiment, it is preferable that the output of the first power source, the output of the second power source, and the output of the third power source be adjusted such that the atomic ratio of indium oxide to the element M and zinc oxide is 5:1:6 or in the neighborhood thereof. 
     In the above embodiment, it is preferable that the output of the first power source, the output of the second power source, and the output of the third power source be adjusted such that the atomic ratio of indium oxide to the element M and zinc oxide is 4:2:3 or in the neighborhood thereof. 
     In the above embodiment, it is preferable that the output of the first power source, the output of the second power source, and the output of the third power source be adjusted such that the atomic ratio of indium oxide to the element M and zinc oxide is 1:1:1 or in the neighborhood thereof. 
     According to one embodiment of the present invention, a novel sputtering apparatus can be provided. According to one embodiment of the present invention, a novel sputtering apparatus capable of separating functions can be provided. According to one embodiment of the present invention, a method for forming a semiconductor film using the sputtering apparatus can be provided. According to one embodiment of the present invention, a method for forming a semiconductor film in which functions can be separated with the use of the sputtering apparatus can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing the novel semiconductor device can be provided. 
     Note that the description of these effects does not disturb the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a perspective view illustrating a deposition chamber of a sputtering apparatus. 
         FIG. 2  is a perspective view illustrating a deposition chamber of a sputtering apparatus. 
         FIG. 3  is a cross-sectional view illustrating a deposition chamber of a sputtering apparatus. 
         FIG. 4  is a top view illustrating a sputtering apparatus. 
         FIGS. 5A to 5C  are cross-sectional views illustrating a sputtering apparatus. 
         FIGS. 6A and 6B  are a flow chart and a timing chart of a method for forming a semiconductor film. 
         FIGS. 7A and 7B  are a flow chart and a timing chart of a method for forming a semiconductor film. 
         FIG. 8  is a cross-sectional view illustrating a deposition chamber of a sputtering apparatus. 
         FIG. 9  is a cross-sectional view illustrating a concept of a composition of an oxide semiconductor film. 
         FIG. 10  is a cross-sectional view illustrating a concept of a composition of an oxide semiconductor film. 
         FIG. 11  shows measured XRD spectra. 
         FIGS. 12A and 12B  are TEM images of samples and  FIGS. 12C to 12L  are electron diffraction patterns thereof. 
         FIGS. 13A to 13C  show EDX mapping images of a sample. 
         FIGS. 14A to 14C  each illustrate the atomic ratio of an oxide semiconductor film. 
         FIGS. 15A to 15C  are a top view and cross-sectional views illustrating a semiconductor device. 
         FIGS. 16A to 16C  are a top view and cross-sectional views illustrating a semiconductor device. 
         FIGS. 17A to 17D  are cross-sectional views illustrating a method for manufacturing a semiconductor device. 
         FIGS. 18A to 18C  are cross-sectional views illustrating the method for manufacturing a semiconductor device. 
         FIGS. 19A to 19C  are cross-sectional views illustrating the method for manufacturing a semiconductor device. 
         FIGS. 20A to 20C  are a top view and cross-sectional views illustrating a semiconductor device. 
         FIGS. 21A to 21C  are a top view and cross-sectional views illustrating a semiconductor device. 
         FIG. 22  is a top view illustrating one embodiment of a display device. 
         FIG. 23  is a cross-sectional view illustrating one embodiment of a display device. 
         FIG. 24  is a cross-sectional view illustrating one embodiment of a display device. 
         FIG. 25  illustrates a structure example of a display panel. 
         FIG. 26  illustrates a structure example of a display panel. 
         FIGS. 27A to 27C  are a block diagram and circuit diagrams illustrating a display device. 
         FIG. 28  illustrates a display module. 
         FIGS. 29A to 29E  illustrate electronic devices. 
         FIGS. 30A to 30G  illustrate electronic devices. 
         FIGS. 31A and 31B  each illustrate an energy band of a semiconductor film. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments. 
     In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, the size, the layer thickness, or the region is not limited to the illustrated scale. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings. 
     Note that in this specification, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically. 
     In this specification, terms for describing arrangement, such as “over”, “above”, “under”, and “below”, are used for convenience in describing a positional relation between components with reference to the drawings. Furthermore, the positional relation between components is changed as appropriate in accordance with a direction in which each component is described. Thus, there is no limitation on terms used in this specification, and description can be made appropriately depending on the situation. 
     In this specification and the like, a transistor is an element including at least three terminals of a gate, a drain, and a source. The transistor includes a channel region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode) and current can flow between the source and the drain through the channel region. Note that in this specification and the like, a channel region refers to a region through which current mainly flows. 
     Furthermore, functions of a source and a drain might be switched when transistors having different polarities are employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be switched in this specification and the like. 
     Note that in this specification and the like, the term “electrically connected” includes the case where components are connected through an object having any electric function. There is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Examples of an “object having any electric function” include a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions as well as an electrode and a wiring. 
     In this specification and the like, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. 
     In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases. 
     Unless otherwise specified, off-state current in this specification and the like refers to drain current of a transistor in an off state (also referred to as a non-conducting state and a cutoff state). Unless otherwise specified, the off state of an n-channel transistor means that the voltage between its gate and source (Vgs: gate-source voltage) is lower than the threshold voltage Vth, and the off state of a p-channel transistor means that the gate-source voltage Vgs is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current that flows when the gate-source voltage Vgs is lower than the threshold voltage Vth. 
     The off-state current of a transistor depends on Vgs in some cases. Thus, “the off-state current of a transistor is lower than or equal to 1” may mean “there is Vgs with which the off-state current of the transistor becomes lower than or equal to I”. Furthermore, “the off-state current of a transistor” means “the off-state current in an off state at predetermined Vgs”, “the off-state current in an off state at Vgs in a predetermined range”, “the off-state current in an off state at Vgs with which sufficiently reduced off-state current is obtained”, or the like. 
     As an example, the assumption is made of an n-channel transistor where the threshold voltage Vth is 0.5 V and the drain current is 1×10 −9  A at a voltage Vgs of 0.5 V, 1×10 −13  A at a voltage Vgs of 0.1 V, 1×10 −19  A at a voltage Vgs of −0.5 V, and 1×10 −22  A at a voltage Vgs of −0.8 V. The drain current of the transistor is lower than or equal to 1×10 −19  A at Vgs of −0.5 V or at Vgs in the range of −0.8 V to −0.5 V; therefore, it can be said that the off-state current of the transistor is lower than or equal to 1×10 −19  A. Since there is Vgs at which the drain current of the transistor is lower than or equal to 1×10 −22  A, it may be said that the off-state current of the transistor is lower than or equal to 1×10 −22  A. 
     In this specification and the like, the off-state current of a transistor with a channel width W is sometimes represented by a current value per channel width W or by a current value per given channel width (e.g., 1 μm). In the latter case, off-state current may be expressed in the unit with the dimension of current per length (e.g., A/μm). 
     The off-state current of a transistor depends on temperature in some cases. Unless otherwise specified, off-state current in this specification may be an off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C. Alternatively, the off-state current may be an off-state current at a temperature at which the reliability of a semiconductor device or the like including the transistor is ensured or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5° C. to 35° C.). The description “the off-state current of a transistor is lower than or equal to 1” may refer to a situation where there is Vgs at which the off-state current of a transistor is lower than or equal to I at room temperature, 60° C., 85° C., 95° C., 125° C., a temperature at which the reliability of a semiconductor device or the like including the transistor is ensured, or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5° C. to 35° C.). 
     The off-state current of a transistor depends on voltage Vds between its drain and source in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, off-state current might be an off-state current at Vds at which the reliability of a semiconductor device or the like including the transistor is ensured or Vds at which the semiconductor device or the like including the transistor is used. The description “the off-state current of a transistor is lower than or equal to a current I” may mean that there is Vgs at which the off-state current of the transistor is lower than or equal to the current I at Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V, at Vds at which the reliability of a semiconductor device or the like including the transistor is ensured, or at Vds at which the semiconductor device or the like including the transistor is used. 
     In the above description of off-state current, a drain may be replaced with a source. That is, off-state current sometimes refers to a current that flows through a source of a transistor in an off state. 
     In this specification and the like, the term “leakage current” sometimes expresses the same meaning as “off-state current”. In this specification and the like, off-state current sometimes refers to a current that flows between a source and a drain of a transistor in an off state, for example. 
     In this specification and the like, the threshold voltage of a transistor refers to a gate voltage (Vg) at which a channel is formed in the transistor. Specifically, in a graph where the horizontal axis represents gate voltage (Vg) and the vertical axis represents the square root of drain current (Id), the threshold voltage of a transistor may refer to a gate voltage (Vg) at the intersection of the square root of drain current (Id) of 0 (Id=0 A) and an extrapolated straight line that is tangent with the highest inclination to a plotted curve (Vg−√Id characteristics). Alternatively, the threshold voltage of a transistor may refer to a gate voltage (Vg) at which the value of Id [A]×L [μm]/W [μm] is 1×10 −9  [A] where L is the channel length and W is the channel width. 
     In this specification and the like, a “semiconductor” has characteristics of an “insulator” in some cases when the conductivity is sufficiently low, for example. Furthermore, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “insulator” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. An “insulator” in this specification and the like can be called a “semi-insulator” in some cases. 
     In this specification and the like, a “semiconductor” has characteristics of a “conductor” in some cases when the conductivity is sufficiently high, for example. Furthermore, a “semiconductor” and a “conductor” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “conductor” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called a “conductor” in some cases. Similarly, a “conductor” in this specification and the like can be called a “semiconductor” in some cases. 
     In this specification and the like, an impurity in a semiconductor refers to an element that is not a main component of a semiconductor film. For example, an element with a concentration of lower than 0.1 atomic % is an impurity. If a semiconductor contains an impurity, the density of states (DOS) may be formed therein, the carrier mobility may be decreased, or the crystallinity may be decreased, for example. In the case where the semiconductor includes an oxide semiconductor, examples of an impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specific examples are hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is an oxide semiconductor, oxygen vacancies may be formed by entry of impurities such as hydrogen, for example. Furthermore, in the case where the semiconductor includes silicon, examples of an impurity which changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements. 
     In this specification and the like, “In:M:Zn=5:1:6 or the neighborhood of In:M:Zn=5:1:6” refers to an atomic ratio where, when In is 5 with respect to the total number of atoms, M is greater than 0.1 and less than or equal to 2 (0.1&lt;M≦2) and Zn is greater than or equal to 5 and less than or equal to 7 (5≦Zn≦7). In addition, “In:M:Zn=4:2:3 or the neighborhood of In:M:Zn=4:2:3” refers to an atomic ratio where, when In is 4 with respect to the total number of atoms, M is greater than or equal to 1 and less than or equal to 3 (1≦V≦3) and Zn is greater than or equal to 2 and less than or equal to 4 (2≦Zn≦4). Furthermore, “In:M:Zn=1:1:1 or the neighborhood of In:M:Zn=1:1:1” refers to an atomic ratio where, when In is 1 with respect to the total number of atoms, M is greater than 0.1 and less than or equal to 2 (0.1&lt;M≦2) and Zn is greater than 0.1 and less than or equal to 2 (0.1&lt;Zn≦2). 
     Embodiment 1 
     In this embodiment, a sputtering apparatus of one embodiment of the present invention and a method for forming a semiconductor film with the use of the sputtering apparatus are described. 
     &lt;1-1. Structure Example of Sputtering Apparatus&gt; 
     One embodiment of the present invention is a sputtering apparatus with which a semiconductor film can be formed. The sputtering apparatus includes a first target, a first power source connected to the first target, a first shutter facing the first target, a first driver portion connected to the first shutter, a second target, a second power source connected to the second target, a second shutter facing the second target, and a second driver portion connected to the second shutter. The first driver portion and the second driver portion operate in conjunction with each other. 
     With the use of the sputtering apparatus of one embodiment of the present invention, a semiconductor film in which a conductive region and an insulating region are separated and function complementarily can be formed. 
     Examples of the semiconductor film include an oxide semiconductor film, typically, a film formed of IGZO. Here, a compound including In, Ga, Zn, and O is also known as IGZO. Typical examples of IGZO include a crystalline compound represented by InGaO 3 (ZnO) m1  (m1 is a natural number) and a crystalline compound represented by In (1+x0) Ga (1−x0) O 3 (ZnO) m0  (−1≦x0≦1; m0 is a given number). 
     For example, a semiconductor film formed of a compound including In, Ga, Zn, and O might have a low field-effect mobility. 
     In one embodiment of the present invention, a conductive region and an insulating region are separated and function complementarily in a semiconductor film, so that the semiconductor film can have a high field-effect mobility. 
     In this specification and the like, a semiconductor film in which regions functioning as a conductor and regions functioning as an insulator or a dielectric are mixed and which functions as a semiconductor as a whole is defined as a cloud aligned composite oxide semiconductor (CAC-OS) or a CAC-metal oxide. Note that a semiconductor film of one embodiment of the present invention is a kind of matrix composite or metal matrix composite, in which materials having different physical properties are mixed. 
     The sputtering apparatus of one embodiment of the present invention is preferably used, because a semiconductor film in which the impurity concentration is low and the density of defect states is low can be formed and a transistor with excellent electric characteristics can be formed. Here, the state where the impurity concentration is low and the density of defect states is low (the number of oxygen vacancies is small) is referred to as “highly purified intrinsic” or “substantially highly purified intrinsic”. Note that impurities in a semiconductor film are typically water, hydrogen, and the like. In this specification and the like, reducing or removing water and hydrogen from the semiconductor film is referred to as dehydration or dehydrogenation in some cases. Moreover, adding oxygen to the semiconductor film is referred to as oxygen addition in some cases, and a state where oxygen in excess of the stoichiometric composition is contained is referred to as an oxygen-excess state in some cases. 
     A highly purified intrinsic or substantially highly purified intrinsic semiconductor film has few carrier generation sources and thus can have a low carrier density. Thus, a transistor in which a channel region is formed in the semiconductor film rarely has a negative threshold voltage (is rarely normally on). A highly purified intrinsic or substantially highly purified intrinsic semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases. Furthermore, the highly purified intrinsic or substantially highly purified intrinsic semiconductor film has an extremely low off-state current; even when an element has a channel width of 1×10 6  μm and a channel length L of 10 μm, the off-state current can be lower than or equal to the measurement limit of a semiconductor parameter analyzer, that is, lower than or equal to 1×10 −13  A, at a voltage (drain voltage) between a source electrode and a drain electrode of from 1 V to 10 V. 
     First, the details of a structural example of the sputtering apparatus of one embodiment of the present invention, which is capable of forming a semiconductor film, are described with reference to  FIG. 1 ,  FIG. 2 ,  FIG. 3 ,  FIG. 4 , and  FIGS. 5A to 5C . With the use of the sputtering apparatus illustrated in  FIG. 1 ,  FIG. 2 ,  FIG. 3 ,  FIG. 4 , and  FIGS. 5A to 5C , a conductive region and an insulating region can be separated in the semiconductor film. 
       FIG. 1  and  FIG. 2  are perspective views each illustrating a deposition chamber (also simply referred to as a chamber in some cases)  26   b  of a sputtering apparatus  10 .  FIG. 3  is a cross-sectional view of the deposition chamber  26   b  of the sputtering apparatus  10 .  FIG. 4  is a top view of the sputtering apparatus  10 .  FIGS. 5A to 5C  are cross-sectional views along the dashed-dotted lines B 1 -B 2 , B 3 -B 4 , and B 4 -B 5 , respectively, of the sputtering apparatus  10  illustrated in  FIG. 4 . 
     First, the sputtering apparatus  10  is described with reference to  FIG. 4  and  FIGS. 5A to 5C . 
     The sputtering apparatus  10  illustrated in  FIG. 4  includes an atmosphere-side substrate supply chamber  16  including a cassette port  12  for storing substrates and an alignment port  14  for performing alignment of substrates, an atmosphere-side substrate transfer chamber  18  through which a substrate is transferred from the atmosphere-side substrate supply chamber  16 , a load lock chamber  20   a  where a substrate is carried in and the pressure is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber  20   b  where a substrate is carried out and the pressure is switched from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber  22  where a substrate is transferred in a vacuum, a substrate heating chamber  24  where a substrate is heated, and deposition chambers  26   a ,  26   b , and  26   c  in each of which a target is placed for deposition. 
     Note that a plurality of the cassette ports  12  may be provided as illustrated in  FIG. 4  (in  FIG. 4 , three cassette ports  12  are provided). 
     The atmosphere-side substrate transfer chamber  18  is connected to the load lock chamber  20   a  and the unload lock chamber  20   b , the load lock chamber  20   a  and the unload lock chamber  20   b  are connected to the transfer chamber  22 , and the transfer chamber  22  is connected to the substrate heating chamber  24  and the deposition chambers  26   a ,  26   b , and  26   c.    
     Note that gate valves  28  are provided in connecting portions between the chambers so that each chamber excluding the atmosphere-side substrate supply chamber  16  and the atmosphere-side substrate transfer chamber  18  can be independently kept in a vacuum state. In each of the atmosphere-side substrate transfer chamber  18  and the transfer chamber  22 , a substrate transfer robot  30  is provided, which is capable of transferring glass substrates. 
     It is preferable that the substrate heating chamber  24  also serve as a plasma treatment chamber. In the sputtering apparatus  10 , it is possible to transfer a substrate without exposure to the air between treatment and treatment; therefore, adsorption of impurities on a substrate can be suppressed. In addition, the order of film formation, heat treatment, or the like can be freely determined. Note that the number of transfer chambers, the number of deposition chambers, the number of load lock chambers, the number of unload lock chambers, and the number of substrate heating chambers are not limited to the above, and the numbers thereof can be set as appropriate depending on the space for installation or the process conditions. 
       FIG. 5A  is a cross-sectional view of the substrate heating chamber  24  and the transfer chamber  22 . The substrate heating chamber  24  illustrated in  FIG. 5A  includes a plurality of heating stages  32  which can hold a substrate. 
     Note that although the substrate heating chamber  24  including the seven heating stages  32  is illustrated in  FIG. 5A , one embodiment of the present invention is not limited to such a structure. The number of heating stages  32  may be greater than or equal to one and less than seven. Alternatively, the number of heating stages  32  may be greater than or equal to eight. It is preferable to increase the number of the heating stages  32  because a plurality of substrates can be subjected to heat treatment at the same time, which leads to an increase in productivity. Furthermore, the substrate heating chamber  24  is connected to a vacuum pump  34  through a valve. As the vacuum pump  34 , a dry pump and a mechanical booster pump can be used, for example. 
     As a heating mechanism which can be used for the substrate heating chamber  24 , a resistance heater may be used for heating, for example. Alternatively, a heating mechanism in which heating is performed by heat conduction or heat radiation from a medium such as a heated gas may be employed. For example, a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be employed. The LRTA apparatus is an apparatus for heating an object by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. In the GRTA apparatus, heat treatment is performed using a high-temperature gas. An inert gas is used as the gas. 
     The substrate heating chamber  24  is connected to a gas refining device  38  through a gas supply device  36 . Note that although the number of gas supply devices  36  and the number of gas refining devices  38  are the same as the number of kinds of gases, the drawing illustrates only one gas supply device  36  and one gas refining device  38  for simplicity. As the gases introduced into the substrate heating chamber  24 , a gas whose dew point is lower than or equal to −80° C., preferably lower than or equal to −100° C., more preferably lower than or equal to −120° C. can be used; for example, an oxygen gas, a nitrogen gas, and a rare gas (e.g., an argon gas) can be used. 
     The transfer chamber  22  includes the transfer robot  30 . The transfer robot  30  includes a plurality of movable portions and an arm for holding a substrate and can transfer a substrate to each chamber. Furthermore, the transfer chamber  22  is connected to the vacuum pump  34  and a cryopump  40  through valves. With such a structure, evacuation is performed inside the transfer chamber  22  using the vacuum pump  34  from the atmospheric pressure to a low or medium vacuum (approximately several hundred pascals to 0.1 pascals) and then the valves are switched and evacuation is performed using the cryopump  40  from the medium vacuum to a high or ultrahigh vacuum (approximately 0.1 Pa to 1×10 −7  Pa). 
     Alternatively, two or more cryopumps  40  may be connected in parallel to the transfer chamber  22 . With such a structure, even when one of the cryopumps is in regeneration, evacuation can be performed using any of the other cryopumps. Note that the above regeneration refers to treatment for discharging molecules (or atoms) entrapped in the cryopump. When molecules (or atoms) are entrapped too much in a cryopump, the exhaust capability of the cryopump is lowered; therefore, regeneration is performed regularly. 
       FIG. 5B  is a cross-sectional view of the deposition chamber  26   b , the transfer chamber  22 , and the load lock chamber  20   a.    
     The deposition chamber  26   b  is connected to the gas supply device  36  through a gas heating mechanism  50 . The gas heating mechanism  50  is connected to the gas refining device  38  through the gas supply device  36 . With the gas heating mechanism  50 , gases to be introduced into the deposition chamber  26   b  can be heated to a temperature higher than or equal to 40° C. and lower than or equal to 400° C., preferably higher than or equal to 50° C. and lower than or equal to 200° C. Note that although the number of gas heating mechanisms  50 , the number of gas supply devices  36 , and the number of gas refining devices  38  are the same as the number of kinds of gases, the drawing illustrates one gas heating mechanism  50 , one gas supply device  36 , and one gas refining device  38  for simplicity.  FIG. 5B  illustrates a structure provided with the gas heating mechanism  50 , but one embodiment of the present invention is not limited to this structure. The gas heating mechanism  50  is not necessarily provided. 
     The gas supply device  36  has a function of supplying one or more of an argon gas, an oxygen gas, and a nitrogen gas. 
     The semiconductor film of one embodiment of the present invention can be formed using, for example, an argon gas, a nitrogen gas, an oxygen gas, a combination of an argon gas and an oxygen gas, a combination of an argon gas and a nitrogen gas, or a combination of an argon gas, a nitrogen gas, and an oxygen gas. 
     The deposition chamber  26   b  is connected to a turbo molecular pump  52  and the vacuum pump  34  through valves. Note that the evacuation method of the deposition chamber  26   b  is not limited to the above, and a structure similar to that of the evacuation method described above for the transfer chamber  22  (the evacuation method using the cryopump and the vacuum pump) may be employed. Needless to say, the evacuation method of the transfer chamber  22  may have a structure similar to that of the deposition chamber  26   b  (the evacuation method using the turbo molecular pump and the vacuum pump). The evacuation method of the deposition chamber  26   b  may have a structure (not illustrated) using a vacuum pump and a cryotrap in combination. In other words, the evacuation method of the deposition chamber  26   b  preferably has at least a function of adsorbing water molecules. 
     The details of the deposition chamber  26   b  are described later. 
     Next, the details of the transfer chamber  22  and the load lock chamber  20   a  illustrated in  FIG. 5B  and the atmosphere-side substrate transfer chamber  18  and the atmosphere-side substrate supply chamber  16  illustrated in  FIG. 5C  are described. Note that  FIG. 5C  is a cross-sectional view of the atmosphere-side substrate transfer chamber  18  and the atmosphere-side substrate supply chamber  16 . 
     For the transfer chamber  22  illustrated in  FIG. 5B , the description of the transfer chamber  22  illustrated in  FIG. 5A  may be referred to. 
     The load lock chamber  20   a  includes a substrate delivery stage  56 . When the pressure in the load lock chamber  20   a  becomes an atmospheric pressure by being increased from reduced pressure, the substrate delivery stage  56  receives a substrate from the transfer robot  30  provided in the atmosphere-side substrate transfer chamber  18 . After that, the load lock chamber  20   a  is evacuated to vacuum so that the pressure therein becomes reduced pressure and then the transfer robot  30  provided in the transfer chamber  22  receives the substrate from the substrate delivery stage  56 . 
     The load lock chamber  20   a  is connected to the vacuum pump  34  and the cryopump  40  through valves. For a method for connecting evacuation systems such as the vacuum pump  34  and the cryopump  40 , the description of the method for connecting the evacuation systems to the transfer chamber  22  can be referred to, and the description thereof is omitted here. Note that the unload lock chamber  20   b  illustrated in  FIG. 4  can have a structure similar to that of the load lock chamber  20   a.    
     Since the atmosphere-side substrate transfer chamber  18  includes the transfer robot  30 , delivery and receipt of a substrate between the cassette port  12  and the load lock chamber  20   a  can be performed using the transfer robot  30 . Furthermore, a mechanism for suppressing entry of dust or a particle, such as a high efficiency particulate air (HEPA) filter, may be provided above the atmosphere-side substrate transfer chamber  18  and the atmosphere-side substrate supply chamber  16 . The cassette port  12  can hold a plurality of substrates. 
     The semiconductor film is preferably formed with the use of the above sputtering apparatus, because the entry of impurities into the semiconductor film can be suppressed. 
     &lt;1-2. Structural Example of Deposition Chamber&gt; 
     Next, the details of the deposition chamber  26   b  of the sputtering apparatus  10  are described with reference to  FIG. 1 ,  FIG. 2 , and  FIG. 3 . First, the deposition chamber  26   b  is described with reference to  FIG. 2 . 
     The deposition chamber  26   b  of the sputtering apparatus  10  illustrated in  FIG. 2  includes a first target  42   a , a first power source connected to the first target  42   a , a first shutter  43   a  facing the first target  42   a , a first driver portion  61   a  connected to the first shutter  43   a , a second target  42   b , a second power source connected to the second target  42   b , a second shutter  43   b  facing the second target  42   b , a second driver portion  61   b  connected to the second shutter  43   b , a third target  42   c , a third power source connected to the third target  42   c , a third shutter  43   c  facing the third target  42   c , and a third driver portion  61   c  connected to the third shutter  43   c . The first driver portion  61   a , the second driver portion  61   b , and the third driver portion  61   c  operate in conjunction with each other. 
     A substrate  48  is put in the deposition chamber  26   b  illustrated in  FIG. 2 . The formation surface of the substrate  48  is a surface facing the first target  42   a , the second target  42   b , and the third target  42   c . Some components are not illustrated in  FIG. 2  for clarity; for example, the first to third power sources are not illustrated. 
       FIG. 2  illustrates an example in which the deposition chamber  26   b  of the sputtering apparatus  10  includes three targets; however, one embodiment of the present invention is not limited thereto. The sputtering apparatus of one embodiment of the present invention preferably includes at least two targets and can include three or more targets. 
     For example, when the sputtering apparatus of one embodiment of the present invention includes two targets, the following structure can be employed. 
     The deposition chamber  26   b  of the sputtering apparatus includes the first target  42   a , the first power source connected to the first target  42   a , the first shutter  43   a  facing the first target  42   a , the first driver portion  61   a  connected to the first shutter  43   a , the second target  42   b , the second power source connected to the second target  42   b , the second shutter  43   b  facing the second target  42   b , and the second driver portion  61   b  connected to the second shutter  43   b . The first driver portion  61   a  and the second driver portion  61   b  operate in conjunction with each other. 
     Note that the first driver portion  61   a , the second driver portion  61   b , and the third driver portion  61   c  illustrated in  FIG. 2  operate in conjunction with each other, so that the first shutter  43   a , the second shutter  43   b , and the third shutter  43   c  can operate at the same timing; for example, they can be opened or closed at the same timing. 
     Next, the deposition chamber  26   b  is described with reference to  FIG. 3 . 
       FIG. 3  schematically illustrates the cross section of the inside of the deposition chamber  26   b . A substrate stage  46 , the substrate  48 , the first shutter  43   a , the second shutter  43   b , the third shutter  43   c , the first target  42   a , the second target  42   b , the third target  42   c , a first backing plate  60   a , a second backing plate  60   b , a third backing plate  60   c , and the like are illustrated. 
     The first backing plate  60   a  is provided with a target holder  64   a  and a target holder  64   b , and a magnet unit  62  is provided in a region surrounded by the first backing plate  60   a , the target holder  64   a , and the target holder  64   b.    
     Like the first backing plate  60   a , the second backing plate  60   b  and the third backing plate  60   c  are each provided with a pair of target holders and a magnet unit. Since the functions of the pair of target holders and the magnet unit are the same as those of the target holder  64   a , the target holder  64   b , and the magnet unit  62 , reference numerals are omitted. 
     The target  42   a  is placed over the backing plate  60   a . The backing plate  60   a  is placed over the target holder  64   a . The magnet unit  62  is placed under the target  42   a  with the backing plate  60   a  positioned therebetween. 
     As illustrated in  FIG. 3 , the magnet unit  62  includes a magnet  68 N 1 , a magnet  68 N 2 , a magnet  68 S, and a magnet holder  70 . Note that in the magnet unit  62 , the magnet  68 N 1 , the magnet  68 N 2 , and the magnet  68 S are placed over the magnet holder  70 . The magnet  68 N 1 , the magnet  68 N 2 , and the magnet  68 S are spaced. Note that when the substrate  48  is transferred to the deposition chamber  26   b , the substrate  48  is placed in contact with the substrate stage  46 . 
     The target holder  64   a  and the backing plate  60   a  are fixed to each other with a screw (e.g., a bolt) and have the same potential. The target holder  64   a  has a function of supporting the target  42   a  with the backing plate  60   a  positioned therebetween. The target holder  64   b  and the backing plate  60   a  are fixed to each other with a screw (e.g., a bolt) and have the same potential. The target holder  64   b  has a function of supporting the target  42   a  with the backing plate  60   a  positioned therebetween. The backing plate  60   a  has a function of fixing the target  42   a.    
     A terminal V 0  is electrically connected to the substrate stage  46 , a terminal V 1   a  is electrically connected to the target holder  64   a , a terminal V 1   c  is electrically connected to the target holder  64   b , and a terminal V 1   b  is electrically connected to the magnet holder  70 . 
     Lines of magnetic force  72   a  and  72   b  formed by the magnet unit  62  are illustrated in  FIG. 3 . For example, the magnet unit  62  is capable of oscillating laterally or rotating. For example, in the case where the magnet unit  62  is capable of oscillating laterally, the magnet unit  62  may be oscillated with a beat greater than or equal to 0.1 Hz and less than or equal to 1 kHz. The magnetic field over the target  42   a  changes in accordance with oscillation or rotation of the magnet unit  62 . A region with an intense magnetic field is a high-density plasma region; thus, sputtering of the target  42   a  easily occurs in the vicinity of the region. 
     Since the magnet unit  62  is capable of oscillating or rotating, the uniformity of the thickness or film quality of the semiconductor film can be increased. Thus, a method for forming a semiconductor film with a high yield can be provided. 
     Next, the deposition chamber  26   b  is described with reference to  FIG. 1 . 
       FIG. 1  is a perspective view illustrating a state where the first shutter  43   a , the second shutter  43   b , and the third shutter  43   c  in the deposition chamber  26   b  illustrated in  FIG. 2  operate in conjunction with each other and are opened. When the first shutter  43   a , the second shutter  43   b , and the third shutter  43   c  are opened, part of the surfaces or the entire surfaces of the first target  42   a , the second target  42   b , and the third target  42   c  are made to face the substrate  48 . 
       FIG. 1  schematically illustrates sputtering performed in the deposition chamber  26   b . A particle  63   a  is ejected from the first target  42   a , a particle  63   b  is ejected from the second target  42   b , and a particle  63   c  is ejected from the third target  42   c.    
     By supplying power to the first target  42   a , the second target  42   b , and the third target  42   c  at the same time as illustrated in  FIG. 1 , a mixed material of a material (or a component) contained in the first target  42   a , a material (or a component) contained in the second target  42   b , and a material (or a component) contained in the third target  42   c  can be deposited over the substrate  48 . Accordingly, one embodiment of the present invention is a sputtering apparatus capable of co-sputtering. 
     &lt;1-3. Process Flow  1  for Describing Method for Forming Semiconductor Film&gt; 
     Next, a method for forming a semiconductor film with the use of the sputtering apparatus illustrated in  FIG. 1 ,  FIG. 2 ,  FIG. 3 ,  FIG. 4 , and  FIGS. 5A to 5C  is described with reference to  FIG. 1 ,  FIG. 3 , and  FIGS. 6A and 6B . 
       FIG. 6A  is a flow chart for describing a method for forming a semiconductor film, and  FIG. 6B  is a timing chart of the method for forming a semiconductor film.  FIG. 6B  shows the timing of operation of a first power source V 1 , a second power source V 2 , a first shutter (Sh 1 ), and a second shutter (Sh 2 ). 
     [First Step] 
     First, the first power source is turned on (see Step S 101  in  FIG. 6A ). 
     In the first step, for example, voltage is applied to the target holder  64   a  and the target holder  64   b  in the deposition chamber  26   b  illustrated in  FIG. 3 . As an example, a potential applied to the terminal V 1   a  connected to the target holder  64   a  may be lower than a potential applied to the terminal V 0  connected to the substrate stage  46 . In addition, a potential applied to the terminal V 1   c  connected to the target holder  64   b  may be lower than a potential applied to the terminal V 0  connected to the substrate stage  46 . A potential applied to the terminal V 0  connected to the substrate stage  46  may be a ground potential. A potential applied to the terminal V 1   b  connected to the magnet holder  70  may be a ground potential. 
     Note that the potentials applied to the terminals V 0 , V 1   a , V 1   b , and V 1   c  are not limited to the above-described potentials. Note that a power source (the first power source V 1 ) capable of controlling the potential applied to the terminal V 1   a  and the terminal V 1   c  is electrically connected to the terminal V 1   a  and the terminal V 1   c . As the power source, a DC power source, an AC power source, or an RF power source may be used. 
     [Second Step] 
     Next, the second power source is turned on (see Step S 201  in  FIG. 6A ). 
     In the second step, for example, voltage is applied to the terminal V 0 , the terminal V 2   a , the terminal V 2   b , and the terminal V 2   c  in the deposition chamber  26   b  illustrated in  FIG. 3 . The potentials applied to the terminal V 0 , the terminal V 2   a , the terminal V 2   b , and the terminal V 2   c  may be the same as those applied to the terminal V 0 , the terminal V 1   a , the terminal V 1   b , and the terminal V 1   c , respectively. 
     The first power source and the second power source are preferably independently controlled; in this way, the deposition speed for the first target, the deposition speed for the second target, and the like can be independently adjusted. 
     In addition, in the case where an oxygen gas is used as a deposition gas in the first step and the second step, by setting the proportion of the oxygen gas in the whole of introduced gases (also referred to as an oxygen flow rate ratio) high, a semiconductor film with high crystallinity can be formed. In contrast, by setting the oxygen flow rate ratio low, the semiconductor film can have a low crystallinity and a high carrier mobility. 
     Specifically, in order to increase the crystallinity of the semiconductor film, the proportion of the oxygen gas in the whole of introduced gases in the second step is preferably higher than 30% and lower than or equal to 100%. By setting the oxygen flow rate ratio in the above range, a CAAC-OS described later can be favorably formed. 
     In order to decrease the crystallinity of the semiconductor film, the proportion of the oxygen gas in the whole of introduced gases in the second step is preferably higher than or equal to 0% and lower than or equal to 30%. By setting the oxygen flow rate ratio in the above range, a CAC-OS described later can be favorably formed. 
     In the case where a nitrogen gas is used as a deposition gas in the second step, the proportion of the nitrogen gas in the whole of introduced gases (also referred to as a nitrogen flow rate ratio) is preferably higher than or equal to 10% and lower than or equal to 100%. By setting the nitrogen flow rate ratio in the above range, vacancies in the semiconductor film can be filled with nitrogen and the carrier density thereof can be increased in some cases. 
     [Third Step] 
     Then, the first shutter is opened (see Step S 301  in  FIG. 6A ). 
     In the third step, for example, the first shutter  43   a  is operated and opened in the deposition chamber  26   b  illustrated in  FIG. 3 . The first shutter  43   a  is opened as illustrated in  FIG. 1 , for example. When the first shutter  43   a  is operated, the first driver portion  61   a  connected to the first shutter  43   a  may be rotated. 
     [Fourth Step] 
     Then, the second shutter is opened (see Step S 401  in  FIG. 6A ). 
     In the fourth step, for example, the second shutter  43   b  is operated and opened in the deposition chamber  26   b  illustrated in  FIG. 3 . The second shutter  43   b  is opened as illustrated in  FIG. 1 , for example. When the second shutter  43   b  is operated, the second driver portion  61   b  connected to the second shutter  43   b  may be rotated. 
     Next,  FIG. 6B  is described. 
     In a period P 1 , the first power source V 1  is turned on. Then, the power source is kept on in a period P 2  and turned off in a period P 3 . In the period P 1 , the second power source V 2  is turned on. Then, the power source is kept on in the period P 2  and turned off in the period P 3 . 
     Note that the first power source V 1  and the second power source V 2  are not necessarily turned on at exactly the same timing and may be turned on at substantially the same timing. Note that the period P 2  for Step S 101  and the period P 2  for Step S 201  overlap at least partly with each other as shown in  FIG. 6B . Accordingly, a semiconductor film in which the component of the first target and the component of the second target coexist can be formed. 
     In Step S 301 , the first shutter (Sh 1 ) is turned on, that is, the first shutter (Sh 1 ) is opened at a timing between the period P 1  and the period P 2 . In Step S 401 , the second shutter (Sh 2 ) is turned on, that is, the second shutter (Sh 2 ) is opened at a timing between the period P 1  and the period P 2 . In other words, Step S 301  and Step S 401  are performed in conjunction with each other. 
     In  FIG. 6B , the period P 1  is a period during which the power source for applying voltage to the target is turned on, the period P 2  is a period during which a sputtering particle is ejected from the target, that is, a period during deposition, and the period P 3  is a period during which the power source for applying voltage to the target is turned off. 
     &lt;1-4. Process Flow  2  for Describing Method for Forming Semiconductor Film&gt; 
     Next, a method for forming a semiconductor film with the use of the sputtering apparatus illustrated in  FIG. 1 ,  FIG. 2 ,  FIG. 3 ,  FIG. 4 , and  FIGS. 5A to 5C  will be described with reference to  FIG. 1 ,  FIG. 3 , and  FIGS. 7A and 7B . 
       FIG. 7A  is a flow chart for describing a method for forming a semiconductor film, and  FIG. 7B  is a timing chart of the method for forming a semiconductor film.  FIG. 7B  shows the timing of operation of the first power source V 1 , the second power source V 2 , a third power source V 3 , the first shutter (Sh 1 ), the second shutter (Sh 2 ), and a third shutter (Sh 3 ). 
     [First Step] 
     First, the first power source is turned on (see Step S 102  in  FIG. 7A ). 
     The first step may be performed in a manner similar to that of Step S 101 . 
     [Second Step] 
     Next, the second power source is turned on (see Step S 202  in  FIG. 7A ). 
     The second step may be performed in a manner similar to that of Step S 201 . 
     [Third Step] 
     Next, the third power source is turned on (see Step S 302  in  FIG. 7A ). 
     In the third step, for example, voltage is applied to the terminal V 0 , a terminal V 3   a , a terminal V 3   b , and a terminal V 3   c  in the deposition chamber  26   b  illustrated in  FIG. 3 . The potentials applied to the terminal V 0 , the terminal V 3   a , the terminal V 3   b , and the terminal V 3   c  may be the same as those applied to the terminal V 0 , the terminal V 1   a , the terminal V 1   b , and the terminal V 1   c , respectively. 
     The first power source, the second power source, and the third power source are preferably independently controlled; in this way, the deposition speed for the first target, the deposition speed for the second target, the deposition speed for the third target, and the like can be independently controlled. 
     [Fourth Step] 
     Then, the first shutter is opened (see Step S 402  in  FIG. 7A ). 
     The fourth step may be performed in a manner similar to that of Step S 301 . 
     [Fifth Step] 
     Then, the second shutter is opened (see Step S 502  in  FIG. 7A ). 
     The fifth step may be performed in a manner similar to that of Step S 401 . 
     [Sixth Step] 
     Then, the third shutter is opened (see Step S 602  in  FIG. 7A ). 
     In the sixth step, for example, the third shutter  43   c  is operated and opened in the deposition chamber  26   b  illustrated in  FIG. 3 . The third shutter  43   c  is opened as illustrated in  FIG. 1 , for example. When the third shutter  43   c  is operated, the third driver portion  61   c  connected to the third shutter  43   c  may be rotated. 
     Next,  FIG. 7B  is described. 
     In the period P 1 , the first power source V 1  is turned on. Then, the power source is kept on in the period P 2  and turned off in the period P 3 . In the period P 1 , the second power source V 2  is turned on. Then, the power source is kept on in the period P 2  and turned off in the period P 3 . In the period P 1 , the third power source V 3  is turned on. Then, the power source is kept on in the period P 2  and turned off in the period P 3 . 
     Note that the first power source V 1 , the second power source V 2 , and the third power source V 3  are not necessarily turned on at exactly the same timing and may be turned on at substantially the same timing. Note that the period P 2  for Step S 102 , the period P 2  for Step S 202 , and the period P 2  for Step S 302  overlap at least partly with each other as shown in  FIG. 7B . Accordingly, a semiconductor film in which the component of the first target, the component of the second target, and the component of the third target coexist can be formed. 
     In Step S 402 , the first shutter (Sh 1 ) is turned on, that is, the first shutter (Sh 1 ) is opened at a timing between the period P 1  and the period P 2 . In Step S 502 , the second shutter (Sh 2 ) is turned on, that is, the second shutter (Sh 2 ) is opened at a timing between the period P 1  and the period P 2 . In Step S 602 , the third shutter (Sh 3 ) is turned on, that is, the third shutter (Sh 3 ) is opened at a timing between the period P 1  and the period P 2 . In other words, Step S 402 , Step S 502 , and Step S 602  are performed in conjunction with each other. 
     In  FIG. 7B , the period P 1  is a period during which the power source for applying voltage to the target is turned on, the period P 2  is a period during which a sputtering particle is ejected from the target, that is, a period during deposition, and the period P 3  is a period during which the power source for applying voltage to the target is turned off. 
     &lt;1-5. Deposition Model of Semiconductor Film&gt; 
     Next, a deposition model of a semiconductor film is described with reference to  FIG. 8 .  FIG. 8  is a cross-sectional view of the deposition chamber  26   b  which is observed from the direction of an arrow X 1  in  FIG. 1 . In  FIG. 8 , some components (e.g., a shutter) are omitted for clarity. 
       FIG. 8  illustrates a structure that is based on the assumption that the composition of the first target  42   a  includes indium oxide, the composition of the second target  42   b  includes gallium oxide, and the composition of the third target  42   c  includes zinc oxide. 
     In the deposition chamber  26   b  illustrated in  FIG. 8 , a deposition gas (an argon gas, an oxygen gas, or a nitrogen gas) is ionized and separated into cations  71  and electrons (not illustrated), and plasma  73  is generated. Then, the cations  71  in the plasma  73  are accelerated toward the first target  42   a , the second target  42   b , and the third target  42   c.    
     The cation  71  collides with the first target  42   a , and the particle  63   a  is ejected from the first target  42   a . The cation  71  collides with the second target  42   b , and the particle  63   b  is ejected from the second target  42   b . The cation  71  collides with the third target  42   c , and the particle  63   c  is ejected from the third target  42   c.    
     In some cases, the particle  63   b  and the particle  63   c  are more likely to be ejected than the particle  63   a . This is because the relative atomic masses of the particle  63   b  including the component of gallium oxide and the particle  63   c  including the component of zinc oxide are lower than that of the particle  63   a  including the component of indium oxide. 
     The particle  63   a  including the component of indium oxide, the particle  63   b  including the component of gallium oxide, and the particle  63   c  including the component of zinc oxide are deposited over the substrate  48 , so that a CAC-OS which is a semiconductor film of one embodiment of the present invention can be formed. 
     In the above description, the composition of the second target  42   b  includes gallium oxide. However, one embodiment of the present invention is not limited thereto, and a target including, in addition to gallium oxide, an oxide of an element M (M is one or more of aluminum, silicon, boron, gallium, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) may be used. It is particularly preferable that the element M be aluminum, silicon, boron, or gallium. In addition, the first target  42   a  may include indium oxide and zinc oxide. 
     In the case where voltage is applied to the first target  42   a , the second target  42   b , and the third target  42   c , the output of the first power source connected to the first target  42   a , the output of the second power source connected to the second target  42   b , and the output of the third power source connected to the third target  42   c  are preferably adjusted such that the atomic ratio of indium oxide to the element M and zinc oxide can be 5:1:6 or in the neighborhood thereof. 
     Alternatively, in the case where voltage is applied to the first target  42   a , the second target  42   b , and the third target  42   c , the output of the first power source connected to the first target  42   a , the output of the second power source connected to the second target  42   b , and the output of the third power source connected to the third target  42   c  are preferably adjusted such that the atomic ratio of indium oxide to the element M and zinc oxide can be 4:2:3 or in the neighborhood thereof. 
     Alternatively, in the case where voltage is applied to the first target  42   a , the second target  42   b , and the third target  42   c , the output of the first power source connected to the first target  42   a , the output of the second power source connected to the second target  42   b , and the output of the third power source connected to the third target  42   c  are preferably adjusted such that the atomic ratio of indium oxide to the element M and zinc oxide can be 1:1:1 or in the neighborhood thereof. 
     The temperature of the substrate  48  in deposition influences the electric properties of a semiconductor film. The higher the substrate temperature is, the higher the crystallinity and reliability of the semiconductor film can be. In contrast, the lower the substrate temperature is, the lower the crystallinity of the semiconductor film can be and the higher the carrier mobility thereof can be. In particular, the lower the substrate temperature in deposition is, the more the field-effect mobility at a low gate voltage (e.g., higher than 0 V and lower than or equal to 2 V) is notably increased in a transistor including the semiconductor film. 
     The temperature of the substrate  48  may be higher than or equal to room temperature (25° C.) and lower than 200° C., preferably higher than or equal to room temperature and lower than or equal to 150° C. (typically 130° C.). The substrate temperature in the above range is suitable for the case of using a large glass substrate. In particular, when the substrate temperature in deposition of the semiconductor film is room temperature, i.e., the substrate is not heated intentionally, the substrate can be favorably prevented from bending or warping. 
     By setting the temperature of the substrate  48  to higher than or equal to 100° C. and lower than or equal to 150° C. (typically 130° C.), water in the semiconductor film can be removed. Water that is an impurity is removed in this manner, whereby the field-effect mobility and the reliability of a transistor can be improved at the same time. 
     The temperature of the substrate  48  is set to higher than or equal to 100° C. and lower than or equal to 150° C. for removal of water, whereby the sputtering apparatus can be prevented from warping due to overheat. This leads to an improvement in productivity of a semiconductor device. The productivity is stabilized, so that a large-scale production apparatus is easy to employ. Thus, a large display device manufactured using a large substrate can be easily manufactured. 
     When deposition is performed with the temperature of the substrate  48  set to higher than or equal to room temperature and lower than or equal to 150° C., shallow defect states (also referred to as sDOS) in the oxide semiconductor can be reduced. 
     At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate. 
     Embodiment 2 
     An oxide semiconductor film that can be used as a semiconductor film of one embodiment of the present invention is described in this embodiment. 
     An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a cloud aligned composite oxide semiconductor (CAC-OS), a c-axis-aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. Among the non-single-crystal structure, the amorphous structure has the highest density of defect states, whereas a CAAC-OS has the lowest density of defect states. 
     First, the structure of the CAC-OS that is an oxide semiconductor film is described with reference to  FIG. 9  and  FIG. 10 . Note that  FIG. 9  and  FIG. 10  are schematic cross-sectional views each illustrating the concept of the CAC-OS. 
     &lt;2-1. Composition of CAC-OS&gt; 
     For example, in the CAC-OS, as illustrated in  FIG. 9 , elements included in the oxide semiconductor film are unevenly distributed to form regions  001  mainly including an element, regions  002  mainly including another element, and regions  003  mainly including another element. The regions  001 ,  002 , and  003  are mixed to form a mosaic pattern. The CAC-OS has, for example, a composition in which elements included in an oxide semiconductor film are unevenly distributed. Materials including unevenly distributed elements each have a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size. Note that in the following description of an oxide semiconductor film, a state where one or more metal elements are unevenly distributed and regions including the metal elements are mixed is referred to as a mosaic pattern or a patch-like pattern. The region has a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size. 
     Indium is preferably contained in an oxide semiconductor film. In particular, indium and zinc are preferably contained. In addition, an element M (the element M is one or more of aluminum, silicon, boron, gallium, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) may be contained. 
     For example, an In-M-Zn oxide including the CAC-OS composition has a composition in which materials are separated into indium oxide (InO X1 , where X1 is a real number greater than 0) or indium zinc oxide (In X2 Zn Y2 O Z2 , where X2, Y2, and Z2 are real numbers greater than 0), and an oxide of the element M (MO X3 , where X3 is a real number greater than 0) or an M-Zn oxide (M X4 Zn Y4 O Z4 , where X4, Y4, and Z4 are real numbers greater than 0), and a mosaic pattern is formed. InO X1  or In X2 Zn Y2 O Z2  forming the mosaic pattern is distributed in the film. This composition is also referred to as a cloud-like composition. 
     Let a concept in  FIG. 9  illustrate an In-M-Zn oxide including the CAC-OS composition. In that case, the region  001  mainly includes MO X3 , the region  002  mainly includes In X2 Zn Y2 O Z2  or InO X1 , and the region  003  includes at least Zn. Surrounding portions of the region mainly including MO X3 , the region mainly including In X2 Zn Y2 O Z2  or InO X1 , and the region including at least Zn are unclear (blurred), so that the boundaries are not clearly observed in some cases. 
     In other words, the In-M-Zn oxide including the CAC-OS composition is an oxide semiconductor film in which the region including MO X3  as a main component and the region including In X2 Zn Y2 O Z2  or InO X1  as a main component are mixed. For this reason, the oxide semiconductor film is referred to as a composite oxide semiconductor film in some cases. Note that in this specification, for example, when the atomic ratio of In to the element M in the region  002  is greater than the atomic ratio of In to the element M in the region  001 , the region  002  has a higher In concentration than the region  001 . 
     Note that in the oxide semiconductor film including the CAC-OS composition, a stacked-layer structure including two or more films with different compositions is not included. For example, a two-layer structure of a film including In as a main component and a film including Ga as a main component is not included. 
     Specifically, of the CAC-OS, an In—Ga—Zn oxide including the CAC-OS composition (such an In—Ga—Zn oxide may be particularly referred to as CAC-IGZO) is described. In an In—Ga—Zn oxide including the CAC-OS composition, materials are separated into InO X1  or In X2 Zn Y2 O Z2 , and gallium oxide (GaO X5 , where X5 is a real number greater than 0) or gallium zinc oxide (Ga X6 Zn Y6 O Z6 , where X6, Y6, and Z6 are real numbers greater than 0), for example, and a mosaic pattern is formed. InO X1  or In X2 Zn Y2 O Z2  forming the mosaic pattern is a cloud-like oxide semiconductor film. 
     In other words, an In—Ga—Zn oxide including the CAC-OS composition is a composite oxide semiconductor film having a composition in which a region including GaO X3  as a main component and a region including In X2 Zn Y2 O Z2  or InO X1  as a main component are mixed. Surrounding portions of the region including GaO X3  as a main component and the region including In X2 Zn Y2 O Z2  or InO X1  as a main component are unclear (blurred), so that the boundaries are not clearly observed in some cases. 
     Note that the sizes of the regions  001  to  003  can be obtained by EDX mapping. For example, the diameter of the region  001  is greater than or equal to 0.5 nm and less than or equal to 10 nm, or greater than or equal to 1 nm and less than or equal to 2 nm in the EDX mapping image of a cross-sectional photograph in some cases. The density of an element which is a main component is gradually lowered from the central portion of the region toward the surrounding portion. For example, when the number (abundance) of atoms of an element countable in an EDX mapping image gradually changes from the central portion toward the surrounding portion, the surrounding portion of the region is unclear (blurred) in the EDX mapping image of the cross-sectional photograph. For example, from the central portion toward the surrounding portion in the region including GaO X3  as a main component, the number of Ga atoms gradually reduces and the number of Zn atoms gradually increases, so that the region including Ga X6 Zn Y6 O Z6  as a main component gradually appears. Accordingly, the surrounding portion of the region including GaO X3  as a main component is unclear (blurred) in the EDX mapping image. 
     Note that a compound including In, Ga, Zn, and O is also known as IGZO. Typical examples of IGZO include a crystalline compound represented by InGaO 3 (ZnO) m1  (m1 is a natural number) and a crystalline compound represented by In (1+x0) Ga (1−x−0) O 3 (ZnO) m0  (−1≦x0≦1; m0 is a given number). 
     The above crystalline compounds have a single crystal structure, a polycrystalline structure, or a c-axis-aligned crystalline (CAAC) structure. Note that the CAAC structure is a layered crystal structure in which a plurality of IGZO nanocrystals have c-axis alignment and are connected in the a-b plane direction without alignment. 
     Meanwhile, the crystal structure is a secondary element for an In—Ga—Zn oxide including the CAC-OS composition. In this specification, CAC-IGZO can be defined as an oxide semiconductor film including In, Ga, Zn, and O in the state where a plurality of regions including Ga as a main component and a plurality of regions including In as a main component are each dispersed randomly in a mosaic pattern. 
     For example, in the conceptual view in  FIG. 9 , the region  001  corresponds to the region including Ga as a main component and the region  002  corresponds to the region including In as a main component. In addition, in the conceptual view in  FIG. 9 , the region  003  corresponds to the region including zinc. Note that the region including Ga as a main component and the region including In as a main component may each be referred to as a nanoparticle. The diameter of the nanoparticle is greater than or equal to 0.5 nm and less than or equal to 10 nm, typically greater than or equal to 1 nm and less than or equal to 2 nm. Surrounding portions of the nanoparticles are unclear (blurred), so that the boundaries are not clearly observed in some cases. 
       FIG. 10  illustrates a modification example of the conceptual view in  FIG. 9 . As illustrated in  FIG. 10 , the region  001 , the region  002 , and the region  003  have different shapes or densities depending on conditions for forming the oxide semiconductor film in some cases. 
     The crystallinity of an In—Ga—Zn oxide including the CAC-OS composition can be analyzed by electron diffraction. For example, a ring-like region with high luminance is observed in an electron diffraction pattern image. Furthermore, a plurality of spots are observed in the ring-like region in some cases. 
     As described above, an In—Ga—Zn oxide including the CAC-OS composition has a structure different from that of an IGZO compound in which metal elements are evenly distributed, and has characteristics different from those of the IGZO compound. That is, in an In—Ga—Zn oxide including the CAC-OS composition, regions including GaO X5  or the like as a main component and regions including In X2 Zn Y2 O Z2  or InO X1  as a main component are separated to form a mosaic pattern. 
     In the case where one or more of aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like are contained instead of gallium in a CAC-OS, nanoparticle regions including the metal element(s) as a main component(s) are observed in part of the CAC-OS and nanoparticle regions including In as a main component are observed in part thereof, and these nanoparticle regions are randomly dispersed to form a mosaic pattern in the CAC-OS. 
     The conductivity of a region including In X2 Zn Y2 O Z2  or InO X1  as a main component is higher than that of a region including GaO X3  or the like as a main component. In other words, in the region with high conductivity, the proportion of In is relatively high. In the following description, the region with a relatively high proportion of In may be referred to as an In-rich region for convenience. That is, when carriers flow through regions including In X2 Zn Y2 O Z2  or InO X1  as a main component, the conductivity of an oxide semiconductor is exhibited. Accordingly, when regions including In X2 Zn Y2 O Z2  or InO X1  as a main component are distributed in an oxide semiconductor like a cloud, a high field-effect mobility (μ) can be achieved. 
     In contrast, the insulating property of a region including GaO X3  or the like as a main component is higher than that of a region including In X2 Zn Y2 O Z2  or InO X1  as a main component. In other words, in the region with a high insulating property, the proportion of Ga is relatively high. In the following description, the region with a relatively high proportion of Ga may be referred to as a Ga-rich region for convenience. That is, when regions including GaO X3  or the like as a main component are distributed in an oxide semiconductor, leakage current can be suppressed and favorable switching operation can be achieved. 
     Accordingly, when an In—Ga—Zn oxide including the CAC-OS composition is used for a semiconductor element, the insulating property derived from GaO X5  or the like and the conductivity derived from In X2 Zn Y2 O Z2  or InO X1  complement each other, whereby a high on-state current (Ion), high field-effect mobility (μ), and a low off-state current (I off ) can be achieved. 
     In a region including GaO X3  with an excellent insulating property or the like as a main component and in the vicinity thereof, an electron is localized. Thus, in some cases, electric conduction is caused when an electron serving as a carrier hops the region including GaO X3  with an excellent insulating property or the like as a main component. Note that it is presumed that a hopping process is caused by thermal vibration of an atom, for example, and electric conductivity increases with the increasing temperature in some cases. Alternatively, the hopping process is caused by action from the outside, such as electrical action, in some cases. Specifically, the hopping process might be caused when an electric field is applied to a CAC-OS. 
     An example of the hypothesis about the conduction mechanism of a CAC-OS is described with reference to  FIGS. 31A and 31B .  FIGS. 31A and 31B  are energy band diagrams for describing the conduction mechanism of a CAC-OS. 
     As shown in  FIG. 31A , an In-rich region in the CAC-OS has a narrow band gap and its Ec edge is located at a low level, whereas a Ga-rich region in the CAC-OS has a wide band gap and its Ec edge is located at a high level (see  FIG. 31A ). 
     In the CAC-OS of one embodiment of the present invention, the In-rich region and the Ga-rich region are distributed and formed in a composite manner. In addition, the In-rich region surrounds the Ga-rich region. Therefore, owing to variations in the composition due to aggregate of materials in the CAC-OS or the like, it is assumed that the energy band structure in  FIG. 31A  is changed to an energy band structure in  FIG. 31B  in which a bonding portion of the In-rich region and the Ga-rich region is not discontinuous, that is, continuously deranged. 
     In a transistor including the CAC-OS of one embodiment of the present invention having the energy band structure shown in  FIG. 31B , the In-rich region and the Ga-rich region electrically interact with each other, so that electrons flow to the In-rich region with a low Ec edge when forward bias is applied. As electrons flow to the In-rich region, the Ec edge of the Ga-rich region in the vicinity of the In-rich region is curved toward the Ec edge of the In-rich region, so that electrons easily flow and electrons also flow to the Ga-rich region with a high Ec edge. Accordingly, the transistor including the CAC-OS of one embodiment of the present invention can have a high field-effect mobility when being turned on. 
     A semiconductor element including an In—Ga—Zn oxide including the CAC-OS composition has high reliability. Thus, an In—Ga—Zn oxide including the CAC-OS composition is suitably used in a variety of semiconductor devices typified by a display. 
     &lt;2-2. Analysis of CAC-OS&gt; 
     Next, analysis results of a CAC-OS deposited over a substrate by various measurement methods are described. 
     [Structure of Samples and Formation Method Thereof] 
     Nine samples of one embodiment of the present invention are described below. The samples are formed at different substrate temperatures and with different oxygen gas flow rate ratios in formation of oxide semiconductor films. Note that each sample includes a substrate and an oxide semiconductor film over the substrate. 
     A method for forming the samples is described. 
     A glass substrate is used as the substrate. Over the glass substrate, a 100-nm-thick In—Ga—Zn oxide is formed as the oxide semiconductor film with a sputtering apparatus. The film formation conditions are as follows: the pressure in a chamber is 0.6 Pa, and a metal oxide target (with an atomic ratio of In:Ga:Zn=4:2:4.1) is used as a target. The metal oxide target provided in the sputtering apparatus is supplied with an AC power of 2500 W. 
     As for the conditions in the formation of the oxide of the nine samples, the substrate temperature is set to a temperature that is not increased by intentional heating (hereinafter such a temperature is also referred to as R.T.), to 130° C., and to 170° C. The ratio of the flow rate of an oxygen gas to the flow rate of a mixed gas of Ar and oxygen (also referred to as an oxygen gas flow rate ratio) is set to 10%, 30%, and 100%. 
     [Analysis by X-Ray Diffraction] 
     In this section, the results of X-ray diffraction (XRD) measurement performed on the nine samples are described. As an XRD apparatus, D8 ADVANCE manufactured by Bruker AXS is used. The conditions are as follows: scanning is performed by an out-of-plane method at θ/2θ, the scanning range is 15 deg. to 50 deg., the step width is 0.02 deg., and the scanning speed is 3.0 deg./min. 
       FIG. 11  shows XRD spectra measured by an out-of-plane method. In  FIG. 11 , the top row shows the measurement results of the samples formed at a substrate temperature of 170° C.; the middle row shows the measurement results of the samples formed at a substrate temperature of 130° C.; and the bottom row shows the measurement results of the samples formed at a substrate temperature of R.T. The left column shows the measurement results of the samples formed with an oxygen gas flow rate ratio of 10%; the middle column shows the measurement results of the samples formed with an oxygen gas flow rate ratio of 30%; and the right column shows the measurement results of the samples formed with an oxygen gas flow rate ratio of 100%. 
     In the XRD spectra shown in  FIG. 11 , the higher the substrate temperature at the time of formation is or the higher the oxygen gas flow rate ratio at the time of formation is, the higher the intensity of the peak at around 2θ=31° is. Note that it is found that the peak at around 2θ=31° is derived from a crystalline IGZO compound whose c-axes are aligned in a direction substantially perpendicular to a formation surface or a top surface of the crystalline IGZO compound (such a compound is also referred to as c-axis aligned crystalline (CAAC-) IGZO). 
     As shown in the XRD spectra in  FIG. 11 , as the substrate temperature at the time of formation is lower or the oxygen gas flow rate ratio at the time of formation is lower, a peak becomes less clear. Accordingly, it is found that there are no alignment in the a-b plane direction and c-axis direction in the measured areas of the samples that are formed at a lower substrate temperature or with a lower oxygen gas flow rate ratio. 
     [Analysis with Electron Microscope] 
     This section describes the observation and analysis results of the samples formed at a substrate temperature of R.T. and with an oxygen gas flow rate ratio of 10% with a high-angle annular dark-field scanning transmission electron microscope (HAADF-STEM). An image obtained with a HAADF-STEM is also referred to as a TEM image. 
     Described are the results of image analysis of plan-view images and cross-sectional images obtained with a HAADF-STEM (also referred to as plan-view TEM images and cross-sectional TEM images, respectively). The TEM images are observed with a spherical aberration corrector function. The HAADF-STEM images are obtained using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. under the following conditions: the acceleration voltage is 200 kV, and irradiation with an electron beam with a diameter of approximately 0.1 nm is performed. 
       FIG. 12A  is a plan-view TEM image of the sample formed at a substrate temperature of R.T. and with an oxygen gas flow rate ratio of 10%.  FIG. 12B  is a cross-sectional TEM image of the sample formed at a substrate temperature of R.T. and with an oxygen gas flow rate ratio of 10%. 
     [Analysis of Electron Diffraction Patterns] 
     This section describes electron diffraction patterns obtained by irradiation of the sample formed at a substrate temperature of R.T. and an oxygen gas flow rate ratio of 10% with an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam). 
     Electron diffraction patterns of points indicated by black dots a 1 , a 2 , a 3 , a 4 , and a 5  in the plan-view TEM image in  FIG. 12A  of the sample formed at a substrate temperature of R.T. and an oxygen gas flow rate ratio of 10% are observed. Note that the electron diffraction patterns are observed while electron beam irradiation is performed at a constant rate for 35 seconds.  FIGS. 12C, 12D, 12E, 12F, and 12G  show the results of the points indicated by the black dots a 1 , a 2 , a 3 , a 4 , and a 5 , respectively. 
     In  FIGS. 12C, 12D, 12E, 12F, and 12G , regions with high luminance in a circular (ring) pattern are shown. Furthermore, a plurality of spots are shown in a ring-like shape. 
     Electron diffraction patterns of points indicated by black dots b 1 , b 2 , b 3 , b 4 , and b 5  in the cross-sectional TEM image in  FIG. 12B  of the sample formed at a substrate temperature of R.T. and an oxygen gas flow rate ratio of 10% are observed.  FIGS. 12H, 12I, 12J, 12K, and 12L  show the results of the points indicated by the black dots b 1 , b 2 , b 3 , b 4 , and b 5 , respectively. 
     In  FIGS. 12H, 12I, 12J, 12K, and 12L , regions with high luminance in a ring pattern are shown. Furthermore, a plurality of spots are shown in a ring-like shape. 
     For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO 4  crystal in a direction parallel to the sample surface, a diffraction pattern including a spot derived from the (009) plane of the InGaZnO 4  crystal is obtained. That is, the CAAC-OS has c-axis alignment and the c-axes are aligned in the direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, a ring-like diffraction pattern is shown when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. That is, it is found that the CAAC-OS has neither a-axis alignment nor b-axis alignment. 
     Furthermore, a diffraction pattern like a halo pattern is observed when an oxide semiconductor film including a nanocrystal (a nanocrystalline oxide semiconductor (nc-OS)) is subjected to electron diffraction using an electron beam with a large probe diameter (e.g., 50 nm or larger). Meanwhile, bright spots are shown in a nanobeam electron diffraction pattern of the nc-OS obtained using an electron beam with a small probe diameter (e.g., smaller than 50 nm). In a nanobeam electron diffraction pattern of the nc-OS, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of bright spots are shown in a ring-like shape in some cases. 
     The electron diffraction pattern of the sample formed at a substrate temperature of R.T. and with an oxygen gas flow rate ratio of 10% has regions with high luminance in a ring pattern and a plurality of bright spots appear in the ring-like pattern. Accordingly, the sample formed at a substrate temperature of R.T. and with an oxygen gas flow rate ratio of 10% exhibits an electron diffraction pattern similar to that of the nc-OS and does not show alignment in the plane direction and the cross-sectional direction. 
     According to what is described above, an oxide semiconductor film formed at a low substrate temperature or with a low oxygen gas flow rate ratio is likely to have characteristics distinctly different from those of an oxide semiconductor film having an amorphous structure and an oxide semiconductor film having a single crystal structure. 
     [Elementary Analysis] 
     This section describes the analysis results of elements included in the sample formed at a substrate temperature of R.T. and with an oxygen gas flow rate ratio of 10%. For the analysis, by energy dispersive X-ray spectroscopy (EDX), EDX mapping images are obtained. An energy dispersive X-ray spectrometer AnalysisStation JED-2300T manufactured by JEOL Ltd. is used as an elementary analysis apparatus in the EDX measurement. A Si drift detector is used to detect an X-ray emitted from the sample. 
     In the EDX measurement, the EDX spectrum of a point is obtained in such a manner that electron beam irradiation is performed on the point in a detection target region of a sample, and the energy of characteristic X-ray of the sample generated by the irradiation and its frequency are measured. In this embodiment, peaks of the EDX spectrum of the point are attributed to electron transition to the L shell in an In atom, electron transition to the K shell in a Ga atom, and electron transition to the K shell in a Zn atom and the K shell in an O atom, and the proportions of the atoms in the point are calculated. An EDX mapping image indicating distributions of proportions of atoms can be obtained through the process in an analysis target region of a sample. 
       FIGS. 13A to 13C  show EDX mapping images in a cross section of the sample formed at a substrate temperature of R.T. and with an oxygen gas flow rate ratio of 10%.  FIG. 13A  shows an EDX mapping image of Ga atoms. The proportion of the Ga atoms in all the atoms is 1.18 atomic % to 18.64 atomic %.  FIG. 13B  shows an EDX mapping image of In atoms. The proportion of the In atoms in all the atoms is 9.28 atomic % to 33.74 atomic %.  FIG. 13C  shows an EDX mapping image of Zn atoms. The proportion of the Zn atoms in all the atoms is 6.69 atomic % to 24.99 atomic %.  FIGS. 13A to 13C  show the same region in the cross section of the sample formed at a substrate temperature of R.T. and with an oxygen flow rate ratio of 10%. In the EDX mapping images, the proportion of an element is indicated by grayscale: the more measured atoms exist in a region, the brighter the region is; the less measured atoms exist in a region, the darker the region is. The magnification of the EDX mapping images in  FIGS. 13A to 13C  is 7200000 times. 
     The EDX mapping images in  FIGS. 13A to 13C  show relative distribution of brightness indicating that each element has a distribution in the sample formed at a substrate temperature of R.T. and with an oxygen gas flow rate ratio of 10%. Areas surrounded by solid lines and areas surrounded by dashed lines in  FIGS. 13A to 13C  are examined. 
     In  FIG. 13A , a relatively dark region occupies a large area in the area surrounded by the solid line, while a relatively bright region occupies a large area in the area surrounded by the dashed line. In  FIG. 13B , a relatively bright region occupies a large area in the area surrounded by the solid line, while a relatively dark region occupies a large area in the area surrounded by the dashed line. 
     That is, the areas surrounded by the solid lines are regions including a relatively large number of In atoms and the areas surrounded by the dashed lines are regions including a relatively small number of In atoms. In  FIG. 13C , the right portion of the area surrounded by the solid line is relatively bright and the left portion thereof is relatively dark. Thus, the area surrounded by the solid line is a region including In X2 Zn Y2 O Z2 , InO X1 , or the like as a main component. 
     The area surrounded by the solid line is a region including a relatively small number of Ga atoms and the area surrounded by the dashed line is a region including a relatively large number of Ga atoms. In  FIG. 13C , the upper left portion of the area surrounded by the dashed line is relatively bright and the lower right portion thereof is relatively dark. Thus, the area surrounded by the dashed line is a region including GaO X3 , Ga X4 Zn Y4 O Z4 , or the like as a main component. 
     Furthermore, as shown in  FIGS. 13A to 13C , the In atoms are relatively more uniformly distributed than the Ga atoms, and regions including InO X1  as a main component are seemingly joined to each other through a region including In X2 Zn Y2 O Z2  as a main component. Thus, the regions including In X2 Zn Y2 O Z2  and InO X1  as main components extend like a cloud. 
     An In—Ga—Zn oxide having a composition in which the regions including GaO as a main component and the regions including In X2 Zn Y2 O Z2  or InO X1  as main components are unevenly distributed and mixed can be referred to as CAC-IGZO. 
     As shown in  FIGS. 13A to 13C , each of the regions including GaO X3  as a main component and the regions including In X2 Zn Y2 O Z2  or InO X1  as a main component has a size greater than or equal to 0.5 nm and less than or equal to 10 nm, or greater than or equal to 0.3 nm and less than or equal to 3 nm. Note that it is preferable that the diameter of a region including each metal element as a main component be greater than or equal to 1 nm and less than or equal to 2 nm in the EDX mapping images. 
     As described above, an In—Ga—Zn oxide including the CAC-OS composition has a structure different from that of an IGZO compound in which metal elements are evenly distributed, and has characteristics different from those of the IGZO compound. That is, the In—Ga—Zn oxide including the CAC-OS composition includes regions including GaO X3  or the like as a main component and regions including In X2 Zn Y2 O Z2  or InO X1  as a main component. Accordingly, when the In—Ga—Zn oxide including the CAC-OS composition is used for a semiconductor element, the property derived from GaO X3  or the like and the property derived from In X2 Zn Y2 O Z2  or InO X1  complement each other, whereby a high on-state current (Ion) and a high field-effect mobility (μ) can be achieved. 
     At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate. 
     Embodiment 3 
     An oxide semiconductor film that can be used as a semiconductor film of one embodiment of the present invention is described in this embodiment. In this embodiment, the atomic ratio of elements included in the oxide semiconductor film is described with reference to  FIGS. 14A to 14C . 
     &lt;3. Atomic Ratio of Oxide Semiconductor Film&gt; 
     An oxide semiconductor film in this embodiment contains indium, an element M (the element M is one or more of aluminum, silicon, boron, gallium, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like), and zinc. 
     Phase diagrams in  FIGS. 14A to 14C  can be used to show the atomic ratio of elements in the case where an oxide semiconductor film contains In, the element M, and Zn. The atomic ratio of In to the element M and Zn is denoted by x:y:z. This atomic ratio can be shown as coordinates (x:y:z) in  FIGS. 14A to 14C . Note that the proportion of oxygen atoms is not shown in  FIGS. 14A to 14C . 
     In  FIGS. 14A to 14C , dashed lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):1 (where −1≦α≦1), a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):2, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):4, and a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):5. 
     Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β (where β≧0), a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:7:β, a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β, and a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β. 
     An oxide semiconductor having an atomic ratio of [In]:[M]:[Zn]=0:2:1 or the neighborhood thereof in  FIGS. 14A to 14C  tends to have a spinel crystal structure. 
     A region A in  FIG. 14A  represents examples of the preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor. 
     The oxide semiconductor containing indium in a higher proportion can have a higher carrier mobility (electron mobility). Therefore, an oxide semiconductor having a high content of indium has a higher carrier mobility than an oxide semiconductor having a low content of indium. 
     In contrast, when the indium content and the zinc content in an oxide semiconductor become lower, carrier mobility becomes lower. Thus, with an atomic ratio [In]:[M]:[Zn] of 0:1:0 and the neighborhood thereof (e.g., a region C in  FIG. 14C ), insulation performance becomes better. 
     Accordingly, an oxide semiconductor of one embodiment of the present invention preferably has an atomic ratio represented by the region A in  FIG. 14A . With the atomic ratio, a layered structure with high carrier mobility and a few grain boundaries is easily obtained. 
     An oxide semiconductor with an atomic ratio in the region A, particularly in a region B in  FIG. 14B , is excellent because the oxide semiconductor easily becomes a CAAC-OS and has high carrier mobility. 
     The CAAC-OS is an oxide semiconductor with high crystallinity. In contrast, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur because a clear grain boundary cannot be observed. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including a CAAC-OS is physically stable. Therefore, the oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability. 
     Note that the region B includes an atomic ratio [In]:[M]:[Zn] of 4:2:3 to 4:2:4.1 and the neighborhood thereof. The neighborhood includes an atomic ratio [In]:[M]:[Zn] of 5:3:4. Note that the region B includes an atomic ratio [In]:[M]:[Zn] of 5:1:6 and the neighborhood thereof and an atomic ratio [In]:[M]:[Zn] of 5:1:7 and the neighborhood thereof. 
     Note that the property of an oxide semiconductor is not uniquely determined by an atomic ratio. Even with the same atomic ratio, the property of an oxide semiconductor might be different depending on a formation condition. For example, in the case where the oxide semiconductor is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. 
     In particular, [Zn] in the film might be smaller than [Zn] in the target depending on the substrate temperature in deposition. Thus, the illustrated regions each represent an atomic ratio with which an oxide semiconductor tends to have specific characteristics, and boundaries of the regions A to C are not clear. 
     At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate. 
     Embodiment 4 
     A semiconductor device which can be manufactured with the sputtering apparatus of one embodiment of the present invention and a method for manufacturing the semiconductor device are described with reference to  FIGS. 15A to 15C ,  FIGS. 16A to 16C ,  FIGS. 17A to 17D ,  FIGS. 18A to 18C ,  FIGS. 19A to 19C ,  FIGS. 20A to 20C , and  FIGS. 21A to 21C . 
     Note that a transistor that includes the semiconductor film formed with the sputtering apparatus of one embodiment of the present invention can have a high carrier mobility and high switching characteristics. In addition, the transistor can have high reliability. 
     An oxide semiconductor film with a low carrier density is preferably used for the transistor. For example, an oxide semiconductor film whose carrier density is lower than 8×10 11 /cm 3 , preferably lower than 1×10 11 /cm 3 , more preferably lower than 1×10 10 /cm 3 , and higher than or equal to 1×10 −9 /cm 3  is used as the oxide semiconductor film. 
     An oxide semiconductor film of one embodiment of the present invention is a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases. 
     Charges trapped by the trap states in the oxide semiconductor film take a long time to be released and may behave like fixed charges. Thus, the transistor whose channel region is formed in the oxide semiconductor having a high density of trap states has unstable electric characteristics in some cases. 
     To obtain stable electric characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor film. In order to reduce the concentration of impurities in the oxide semiconductor film, the concentration of impurities in a film that is adjacent to the oxide semiconductor film is preferably reduced. Examples of impurities include hydrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon. 
     Here, the influence of impurities in the oxide semiconductor film is described. Note that the concentration of impurities in the oxide semiconductor film can be measured by secondary ion mass spectrometry (SIMS). 
     When the oxide semiconductor film contains an alkali metal or alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide semiconductor film which contains an alkali metal or alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of an alkali metal or alkaline earth metal in the oxide semiconductor film. Specifically, the concentration of an alkali metal or alkaline earth metal in the oxide semiconductor film measured by SIMS is set to lower than or equal to 1×10 18  atoms/cm 3 , preferably lower than or equal to 2×10 16  atoms/cm 3 . 
     Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy (V o ), in some cases. Due to entry of hydrogen into the oxygen vacancy (V o ), an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor which contains hydrogen is likely to be normally on. Accordingly, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is set to lower than 1×10 20  atoms/cm 3 . 
     The oxygen vacancies (V o ) in the oxide semiconductor film can be reduced by introduction of oxygen into the oxide semiconductor film. That is, the oxygen vacancies (V o ) in the oxide semiconductor film disappear when the oxygen vacancies (V o ) are filled with oxygen. Accordingly, diffusion of oxygen into the oxide semiconductor film can reduce the amount of oxygen vacancies (V o ) in a transistor and improve the reliability of the transistor. 
     As a method for introducing oxygen into the oxide semiconductor film, for example, an oxide in which the oxygen content is higher than that in the stoichiometric composition is provided in contact with the oxide semiconductor film. That is, in the oxide, a region including oxygen in excess of that in the stoichiometric composition (hereinafter also referred to as an excess oxygen region) is preferably formed. In particular, in the case of using an oxide semiconductor film in a transistor, an oxide including an excess oxygen region is provided in a base film, an interlayer film, or the like in the vicinity of the transistor, whereby oxygen vacancies in the transistor are reduced, and the reliability can be improved. 
     When an oxide semiconductor film with a sufficiently reduced impurity concentration is used for a channel formation region of a transistor, the transistor can have stable electric characteristics. 
     &lt;4-1. Structure Example 1 of Semiconductor Device&gt; 
       FIG. 15A  is a top view of a transistor  100  that is a semiconductor device of one embodiment of the present invention.  FIG. 15B  is a cross-sectional view taken along dashed dotted line X 1 -X 2  in  FIG. 15A , and  FIG. 15C  is a cross-sectional view taken along dashed dotted line Y 1 -Y 2  in  FIG. 15A . Note that in  FIG. 15A , some components of the transistor  100  (e.g., an insulating film serving as a gate insulating film) are not illustrated to avoid complexity. The direction of the dashed-dotted line X 1 -X 2  may be called a channel length direction, and the direction of the dashed-dotted line Y 1 -Y 2  may be called a channel width direction. As in  FIG. 15A , some components might not be illustrated in some top views of transistors described below. 
     The transistor  100  illustrated in  FIGS. 15A to 15C  is what is called a top-gate transistor. 
     The transistor  100  includes an insulating film  104  over a substrate  102 , an oxide semiconductor film  108  over the insulating film  104 , an insulating film  110  over the oxide semiconductor film  108 , a conductive film  112  over the insulating film  110 , and an insulating film  116  over the insulating film  104 , the oxide semiconductor film  108 , and the conductive film  112 . The oxide semiconductor film  108  can be formed with the sputtering apparatus described in Embodiment 1. 
     The oxide semiconductor film  108  over the insulating film  104  has a channel formation region in a region overlapping with the conductive film  112 . For example, the oxide semiconductor film  108  preferably contains In, M (M represents one or more of Al, Si, Y, B, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu), and Zn. 
     The oxide semiconductor film  108  includes regions  108   n  which do not overlap with the conductive film  112  and are in contact with the insulating film  116 . The regions  108   n  are n-type regions in the oxide semiconductor film  108  described above. Note that the regions  108   n  are in contact with the insulating film  116 , and the insulating film  116  contains nitrogen or hydrogen. Nitrogen or hydrogen in the insulating film  116  is added to the regions  108   n  to increase the carrier density, thereby making the regions  108   n  n-type. 
     The oxide semiconductor film  108  preferably includes a region in which the atomic proportion of In is larger than the atomic proportion of M. For example, the atomic ratio of In to M to Zn in the oxide semiconductor film  108  is preferably In:M:Zn=4:2:3 or in the neighborhood thereof. 
     The composition of the oxide semiconductor film  108  is not limited to the above. For example, the atomic ratio of In to M to Zn in the oxide semiconductor film  108  may be In:M:Zn=5:1:6 or in the neighborhood thereof. The term “neighborhood” includes the following: when In is 5, M is greater than or equal to 0.5 and less than or equal to 1.5, and Zn is greater than or equal to 5 and less than or equal to 7. 
     When the oxide semiconductor film  108  includes a region in which the atomic proportion of In is larger than the atomic proportion of M, the transistor  100  can have a high field-effect mobility. Specifically, the field-effect mobility of the transistor  100  can be higher than 50 cm 2 /Vs, preferably higher than 100 cm 2 /Vs. 
     For example, the use of the transistor with a high field-effect mobility in a gate driver that generates a gate signal allows a display device to have a narrow frame. The use of the transistor with a high field-effect mobility in a source driver (particularly in a demultiplexer connected to an output terminal of a shift register included in a source driver) that is included in a display device and supplies a signal from a signal line can reduce the number of wirings connected to the display device. 
     Even when the oxide semiconductor film  108  includes a region where the atomic proportion of In is higher than that of M, if the oxide semiconductor film  108  has a high crystallinity, the transistor  100  has a low field-effect mobility in some cases. 
     Furthermore, oxygen vacancies formed in the oxide semiconductor film  108  adversely affect the transistor characteristics and therefore cause a problem. For example, oxygen vacancies formed in the oxide semiconductor film  108  are bonded to hydrogen to serve as a carrier supply source. The carrier supply source generated in the oxide semiconductor film  108  causes a change in the electric characteristics, typically, shift in the threshold voltage, of the transistor  100  including the oxide semiconductor film  108 . Therefore, it is preferable that the amount of oxygen vacancies in the oxide semiconductor film  108  be as small as possible. 
     In one embodiment of the present invention, the insulating film in the vicinity of the oxide semiconductor film  108  contains excess oxygen. Specifically, one or both of the insulating film  110  which is formed over the oxide semiconductor film  108  and the insulating film  104  which is formed below the oxide semiconductor film  108  contain excess oxygen. Oxygen or excess oxygen is transferred from the insulating film  104  and/or the insulating film  110  to the oxide semiconductor film  108 , whereby oxygen vacancies in the oxide semiconductor film can be reduced. 
     Impurities such as hydrogen or moisture entering the oxide semiconductor film  108  adversely affect the transistor characteristics and therefore cause a problem. Therefore, it is preferable that the amount of impurities such as hydrogen or moisture in the oxide semiconductor film  108  be as small as possible. 
     Note that it is preferable to use, as the oxide semiconductor film  108 , an oxide semiconductor film in which the impurity concentration is low and the density of defect states is low, in which case the transistor can have excellent electric characteristics. Here, the state where the impurity concentration is low and the density of defect states is low (the number of oxygen vacancies is small) is referred to as “highly purified intrinsic” or “substantially highly purified intrinsic”. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Thus, a transistor in which a channel region is formed in the oxide semiconductor film rarely has a negative threshold voltage (is rarely normally on). A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases. Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film exhibits an extremely low off-state current. The off-state current of an element having a channel width of 1×10 6  μm and a channel length of 10 μm can be lower than or equal to the measurement limit of a semiconductor parameter analyzer, i.e., lower than or equal to 1×10 −13  A at a voltage between a source electrode and a drain electrode (drain voltage) of 1 V to 10 V. 
     As illustrated in  FIGS. 15A to 15C , the transistor  100  may further include an insulating film  118  over the insulating film  116 , a conductive film  120   a  electrically connected to the region  108   n  through an opening  141   a  formed in the insulating films  116  and  118 , and a conductive film  120   b  electrically connected to the region  108   n  through an opening  141   b  formed in the insulating films  116  and  118 . 
     In this specification and the like, the insulating film  104  may be referred to as a first insulating film, the insulating film  110  may be referred to as a second insulating film, the insulating film  116  may be referred to as a third insulating film, and the insulating film  118  may be referred to as a fourth insulating film. The conductive film  112  functions as a gate electrode, the conductive film  120   a  functions as a source electrode, and the conductive film  120   b  functions as a drain electrode. 
     The insulating film  110  functions as a gate insulating film. The insulating film  110  includes an excess oxygen region. Since the insulating film  110  includes the excess oxygen region, excess oxygen can be supplied to the oxide semiconductor film  108 . As a result, oxygen vacancies that might be formed in the oxide semiconductor film  108  can be filled with excess oxygen, and the semiconductor device can have high reliability. 
     To supply excess oxygen to the oxide semiconductor film  108 , excess oxygen may be supplied to the insulating film  104  that is formed under the oxide semiconductor film  108 . In that case, excess oxygen contained in the insulating film  104  might also be supplied to the regions  108   n , which is not desirable because the resistance of the regions  108   n  might be increased. In contrast, in the structure in which the insulating film  110  formed over the oxide semiconductor film  108  contains excess oxygen, excess oxygen can be selectively supplied only to a region overlapping with the conductive film  112 . 
     &lt;4-2. Components of Semiconductor Device&gt; 
     Next, components of the semiconductor device of this embodiment are described in detail. 
     [Substrate] 
     There is no particular limitation on the property of a material and the like of the substrate  102  as long as the material has heat resistance enough to withstand at least heat treatment to be performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate  102 . Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOT substrate, or the like may be used as the substrate  102 . Further alternatively, any of these substrates provided with a semiconductor element may be used as the substrate  102 . In the case where a glass substrate is used as the substrate  102 , a glass substrate having any of the following sizes can be used: the 6th generation (1500 mm×1850 mm), the 7th generation (1870 mm×2200 mm), the 8th generation (2200 mm×2400 mm), the 9th generation (2400 mm×2800 mm), and the 10th generation (2950 mm×3400 mm). Thus, a large-sized display device can be fabricated. 
     Alternatively, a flexible substrate may be used as the substrate  102 , and the transistor  100  may be provided directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate  102  and the transistor  100 . The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate  102  and transferred onto another substrate. In such a case, the transistor  100  can be transferred to a substrate having low heat resistance or a flexible substrate as well. 
     [First Insulating Film] 
     The insulating film  104  can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. For example, the insulating film  104  can be formed to have a single-layer structure or stacked-layer structure including an oxide insulating film and/or a nitride insulating film. To improve the properties of the interface with the oxide semiconductor film  108 , at least a region of the insulating film  104  which is in contact with the oxide semiconductor film  108  is preferably formed using an oxide insulating film. When the insulating film  104  is formed using an oxide insulating film from which oxygen is released by heating, oxygen contained in the insulating film  104  can be moved to the oxide semiconductor film  108  by heat treatment. 
     The thickness of the insulating film  104  can be greater than or equal to 50 nm, greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating film  104 , the amount of oxygen released from the insulating film  104  can be increased, and interface states at the interface between the insulating film  104  and the oxide semiconductor film  108  and oxygen vacancies included in the oxide semiconductor film  108  can be reduced. 
     For example, the insulating film  104  can be formed to have a single-layer structure or stacked-layer structure including silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn oxide, or the like. In this embodiment, the insulating film  104  has a stacked-layer structure including a silicon nitride film and a silicon oxynitride film. With the insulating film  104  having such a stacked-layer structure including a silicon nitride film as a lower layer and a silicon oxynitride film as an upper layer, oxygen can be efficiently introduced into the oxide semiconductor film  108 . 
     [Conductive Film] 
     The conductive film  112  functioning as a gate electrode and the conductive films  120   a  and  120   b  functioning as a source electrode and a drain electrode can each be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co); an alloy including any of these metal elements as its component; an alloy including a combination of any of these metal elements; or the like. 
     Furthermore, the conductive films  112 ,  120   a , and  120   b  can be formed using an oxide conductor or an oxide semiconductor, such as an oxide including indium and tin (In—Sn oxide), an oxide including indium and tungsten (In—W oxide), an oxide including indium, tungsten, and zinc (In—W—Zn oxide), an oxide including indium and titanium (In—Ti oxide), an oxide including indium, titanium, and tin (In—Ti—Sn oxide), an oxide including indium and zinc (In—Zn oxide), an oxide including indium, tin, and silicon (In—Sn—Si oxide), or an oxide including indium, gallium, and zinc (In—Ga—Zn oxide). 
     Here, an oxide conductor is described. In this specification and the like, an oxide conductor may be referred to as OC. Oxygen vacancies are formed in an oxide semiconductor, and then hydrogen is added to the oxygen vacancies, so that a donor level is formed in the vicinity of the conduction band. This increases the conductivity of the oxide semiconductor; accordingly, the oxide semiconductor becomes a conductor. The oxide semiconductor having become a conductor can be referred to as an oxide conductor. Oxide semiconductors generally transmit visible light because of their large energy gap. An oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the influence of absorption due to the donor level is small in an oxide conductor, and an oxide conductor has a visible light transmitting property comparable to that of an oxide semiconductor. 
     In particular, the above-described oxide conductor is favorably used as the conductive film  112  because excess oxygen can be added to the insulating film  110 . 
     A Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive films  112 ,  120   a , and  120   b . The use of a Cu—X alloy film results in lower fabrication costs because the film can be processed by wet etching. 
     Among the above-mentioned metal elements, any one or more elements selected from titanium, tungsten, tantalum, and molybdenum are preferably included in the conductive films  112 ,  120   a , and  120   b . In particular, a tantalum nitride film is preferably used as the conductive films  112 ,  120   a , and  120   b . A tantalum nitride film has conductivity and a high barrier property against copper or hydrogen. Because a tantalum nitride film releases little hydrogen from itself, it can be favorably used as the conductive film in contact with the oxide semiconductor film  108  or the conductive film in the vicinity of the oxide semiconductor film  108 . 
     The conductive films  112 ,  120   a , and  120   b  can be formed by electroless plating. As materials that can be formed by electroless plating, for example, one or more selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used. It is further favorable to use Cu or Ag because the conductive film can have reduced resistance. 
     [Second Insulating Film] 
     As the insulating film  110  functioning as a gate insulating film of the transistor  100 , an insulating layer including at least one of the following films formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like can be used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that the insulating film  110  may have a two-layer structure or a layered structure including three or more layers. 
     The insulating film  110  that is in contact with the oxide semiconductor film  108  functioning as a channel region of the transistor  100  is preferably an oxide insulating film and preferably includes a region containing oxygen in excess of the stoichiometric composition (oxygen-excess region). In other words, the insulating film  110  is an insulating film capable of releasing oxygen. In order to provide the oxygen-excess region in the insulating film  110 , the insulating film  110  is formed in an oxygen atmosphere, or the deposited insulating film  110  is subjected to heat treatment in an oxygen atmosphere, for example. 
     In the case of using hafnium oxide for the insulating film  110 , the following effects are attained. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, by using hafnium oxide, the thickness of the insulating film  110  can be made large as compared with the case of using silicon oxide; thus, leakage current due to tunnel current can be low. That is, it is possible to provide a transistor with a low off-state current. Moreover, hafnium oxide with a crystal structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, it is preferable to use hafnium oxide with a crystal structure in order to provide a transistor with a low off-state current. Examples of the crystal structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to the above examples. 
     It is preferable that the insulating film  110  have few defects and typically have as few signals observed by electron spin resonance (ESR) spectroscopy as possible. Examples of the signals include a signal due to an E′ center observed at a g-factor of 2.001. Note that the E′ center is due to the dangling bond of silicon. As the insulating film  110 , a silicon oxide film or a silicon oxynitride film whose spin density of a signal due to the E′ center is lower than or equal to 3×10 17  spins/cm 3 , preferably lower than or equal to 5×10 16  spins/cm 3 , may be used. 
     [Oxide Semiconductor Film] 
     For the oxide semiconductor film  108 , the oxide semiconductor described in the above embodiment can be used. 
     [Third Insulating Film] 
     The insulating film  116  contains nitrogen or hydrogen. The insulating film  116  is a nitride insulating film, for example. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, silicon oxynitride, or the like. The hydrogen concentration in the insulating film  116  is preferably higher than or equal to 1×10 22  atoms/cm 3 . The insulating film  116  is in contact with the region  108   n  of the oxide semiconductor film  108 . Thus, the concentration of an impurity (nitrogen or hydrogen) in the region  108   n  in contact with the insulating film  116  is increased, leading to an increase in the carrier density of the region  108   n.    
     [Fourth Insulating Film] 
     As the insulating film  118 , an oxide insulating film can be used. Alternatively, a stack including an oxide insulating film and a nitride insulating film can be used as the insulating film  118 . The insulating film  118  can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide. 
     Furthermore, the insulating film  118  preferably functions as a barrier film against hydrogen, water, and the like from the outside. 
     The thickness of the insulating film  118  can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm. 
     &lt;4-3. Structural Example 2 of Semiconductor Device&gt; 
     A structure which is different from that of the transistor illustrated in  FIGS. 15A to 15C  is described with reference to  FIGS. 16A to 16C . 
       FIG. 16A  is a top view of a transistor  150 .  FIG. 16B  is a cross-sectional view taken along dashed-dotted line X 1 -X 2  in  FIG. 16A .  FIG. 16C  is a cross-sectional view taken along dashed-dotted line Y 1 -Y 2  in  FIG. 16A . 
     The transistor  150  illustrated in  FIGS. 16A to 16C  includes a conductive film  106  over the substrate  102 , the insulating film  104  over the conductive film  106 , the oxide semiconductor film  108  over the insulating film  104 , the insulating film  110  over the oxide semiconductor film  108 , the conductive film  112  over the insulating film  110 , and the insulating film  116  over the insulating film  104 , the oxide semiconductor film  108 , and the conductive film  112 . 
     Note that the oxide semiconductor film  108  has a structure similar that in the transistor  100  illustrated in  FIGS. 15A to 15C . The transistor  150  illustrated in  FIGS. 16A to 16C  includes the conductive film  106  and an opening  143  in addition to the components of the transistor  100  described above. 
     Note that the opening  143  is provided in the insulating films  104  and  110 . The conductive film  106  is electrically connected to the conductive film  112  through the opening  143 . Thus, the same potential is applied to the conductive film  106  and the conductive film  112 . Note that different potentials may be applied to the conductive film  106  and the conductive film  112  without providing the opening  143 . Alternatively, the conductive film  106  may be used as a light-blocking film without providing the opening  143 . When the conductive film  106  is formed using a light-blocking material, for example, light delivered to the active layer of the oxide semiconductor film  108  from the bottom can be reduced. 
     In the case of using the transistor  150 , the conductive film  106  functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive film  112  functions as a second gate electrode (also referred to as a top gate electrode). The insulating film  104  functions as a first gate insulating film, and the insulating film  110  functions as a second gate insulating film. 
     The conductive film  106  can be formed using a material similar to the above-described materials of the conductive films  112 ,  120   a , and  120   b . It is particularly suitable to use a material containing copper for the conductive film  106  because the resistance can be reduced. It is suitable that, for example, each of the conductive films  106 ,  120   a , and  120   b  has a stacked-layer structure in which a copper film is provided over a titanium nitride film, a tantalum nitride film, or a tungsten film. In that case, by using the transistor  150  as a pixel transistor and/or a driving transistor of a display device, parasitic capacitance generated between the conductive films  106  and  120   a  and between the conductive films  106  and  120   b  can be reduced. Thus, the conductive films  106 ,  120   a , and  120   b  can be used not only as the first gate electrode, the source electrode, and the drain electrode of the transistor  150 , but also as power source supply wirings, signal supply wirings, connection wirings, or the like of the display device. 
     In this manner, unlike the transistor  100  described above, the transistor  150  in  FIGS. 16A to 16C  has a structure in which conductive films functioning as a gate electrode are provided over and under the oxide semiconductor film  108 . As in the transistor  150 , a semiconductor device of one embodiment of the present invention may include a plurality of gate electrodes. 
     As illustrated in  FIGS. 16B and 16C , the oxide semiconductor film  108  is positioned to face the conductive film  106  functioning as the first gate electrode and the conductive film  112  functioning as the second gate electrode and is interposed between the two conductive films which function as gate electrodes. 
     Furthermore, the length of the conductive film  112  in the channel width direction is larger than the length of the oxide semiconductor film  108  in the channel width direction. In the channel width direction, the whole oxide semiconductor film  108  is covered with the conductive film  112  with the insulating film  110  placed therebetween. Since the conductive film  112  is connected to the conductive film  106  through the opening  143  provided in the insulating films  104  and  110 , a side surface of the oxide semiconductor film  108  in the channel width direction faces the conductive film  112  with the insulating film  110  placed therebetween. 
     In other words, the conductive film  106  and the conductive film  112  are connected through the opening  143  provided in the insulating films  104  and  110 , and each include a region positioned outside an edge portion of the oxide semiconductor film  108 . 
     Such a structure enables the oxide semiconductor film  108  included in the transistor  150  to be electrically surrounded by electric fields of the conductive film  106  functioning as the first gate electrode and the conductive film  112  functioning as the second gate electrode. A device structure of a transistor, like that of the transistor  150 , in which electric fields of the first gate electrode and the second gate electrode electrically surround the oxide semiconductor film  108  in which a channel region is formed can be referred to as a surrounded channel (S-channel) structure. 
     Since the transistor  150  has the S-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film  108  by the conductive film  106  or the conductive film  112 ; thus, the current drive capability of the transistor  150  can be improved and high on-state current characteristics can be obtained. Since the on-state current can be increased, it is possible to reduce the size of the transistor  150 . Furthermore, since the transistor  150  has a structure in which the oxide semiconductor film  108  is surrounded by the conductive film  106  and the conductive film  112 , the mechanical strength of the transistor  150  can be increased. 
     When seen in the channel width direction of the transistor  150 , an opening different from the opening  143  may be formed on the side of the oxide semiconductor film  108  on which the opening  143  is not formed. 
     When a transistor includes a pair of gate electrodes between which a semiconductor film is positioned as in the transistor  150 , one of the gate electrodes may be supplied with a signal A, and the other gate electrode may be supplied with a fixed potential Vb. Alternatively, one of the gate electrodes may be supplied with the signal A, and the other gate electrode may be supplied with a signal B. Alternatively, one of the gate electrodes may be supplied with a fixed potential Va, and the other gate electrode may be supplied with the fixed potential Vb. 
     Except the above-mentioned points, the transistor  150  has a structure and an effect similar to those of the transistor  100  described above. 
     An insulating film may further be formed over the transistor  150 . The transistor  150  illustrated in  FIGS. 16A to 16B  includes an insulating film  122  over the conductive films  120   a  and  120   b  and the insulating film  118 . 
     The insulating film  122  has a function of covering unevenness and the like caused by the transistor or the like. The insulating film  122  has an insulating property and is formed using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film. Examples of the organic material include photosensitive resin materials such as an acrylic resin and a polyimide resin. 
     &lt;4-4. Method for Manufacturing Semiconductor Device&gt; 
     Next, an example of a method for manufacturing the transistor  150  illustrated in  FIGS. 16A to 16C  is described with reference to  FIGS. 17A to 17D ,  FIGS. 18A to 18C , and  FIGS. 19A to 19C . Note that  FIGS. 17A to 17D ,  FIGS. 18A to 18C , and  FIGS. 19A to 19C  are cross-sectional views in the channel length direction and the channel width direction illustrating the method for manufacturing the transistor  150 . 
     First, the conductive film  106  is formed over the substrate  102 . Then, the insulating film  104  is formed over the substrate  102  and the conductive film  106 , and an oxide semiconductor film is formed over the insulating film  104 . Then, the oxide semiconductor film is processed into an island shape, whereby an oxide semiconductor film  108   a  is formed (see  FIG. 17A ). 
     The conductive film  106  can be formed using a material selected from the above-mentioned materials. In this embodiment, as the conductive film  106 , a layered film of a 50-nm-thick tungsten film and a 400-nm-thick copper film is formed with a sputtering apparatus. 
     To process the conductive film to be the conductive film  106 , a wet etching method and/or a dry etching method can be used. In this embodiment, in the processing of the conductive film into the conductive film  106 , the copper film is etched by a wet etching method and then the tungsten film is etched by a dry etching method. 
     The insulating film  104  can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, as the insulating film  104 , a 400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitride film are formed with a PECVD apparatus. 
     After the insulating film  104  is formed, oxygen may be added to the insulating film  104 . As oxygen added to the insulating film  104 , an oxygen radical, an oxygen atom, an oxygen atomic ion, an oxygen molecular ion, or the like may be used. Oxygen can be added by an ion doping method, an ion implantation method, a plasma treatment method, or the like. Alternatively, a film that suppresses oxygen release may be formed over the insulating film  104 , and then, oxygen may be added to the insulating film  104  through the film. 
     The film that suppresses oxygen release can be formed using a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten. 
     In the case where oxygen is added by plasma treatment in which oxygen is excited by a microwave to generate high-density oxygen plasma, the amount of oxygen added to the insulating film  104  can be increased. 
     For the formation of the oxide semiconductor film  108   a , description in the above embodiment can be referred to. Impurities (in particular, hydrogen and water) can be reduced in the oxide semiconductor film  108   a  formed with the sputtering apparatus of one embodiment of the present invention. 
     The thickness of the oxide semiconductor film  108   a  is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 3 nm and less than or equal to 60 nm. 
     However, in the case where a large-sized glass substrate (e.g., the 6th generation to the 10th generation) is used as the substrate  102  and the oxide semiconductor film  108   a  is formed at a substrate temperature higher than or equal to 200° C. and lower than or equal to 300° C., the substrate  102  might be changed in shape (distorted or warped). In the case where a large-sized glass substrate is used, the change in the shape of the glass substrate can be suppressed by forming the oxide semiconductor film  108   a  at a substrate temperature higher than or equal to room temperature and lower than 200° C. 
     Note that the deposited oxide semiconductor film may be processed into the oxide semiconductor film  108   a  by a wet etching method, a dry etching method, or both. 
     After the oxide semiconductor film  108   a  is formed, dehydrogenation or dehydration of the oxide semiconductor film  108   a  may be performed by heat treatment. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, higher than or equal to 250° C. and lower than or equal to 450° C., or higher than or equal to 300° C. and lower than or equal to 450° C. 
     The heat treatment can be performed in an inert atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, the heat treatment may be performed in an inert atmosphere first, and then, in an oxygen atmosphere. It is preferable that the above inert gas atmosphere and the above oxygen atmosphere do not contain hydrogen, water, and the like. The treatment time may be longer than or equal to 3 minutes and shorter than or equal to 24 hours. 
     An electric furnace, an RTA apparatus, or the like can be used for the heat treatment. The use of an RTA apparatus allows the heat treatment to be performed at a temperature higher than or equal to the strain point of the substrate if the heating time is short. Therefore, the heat treatment time can be shortened. 
     By depositing the oxide semiconductor film while it is heated or by performing heat treatment after the formation of the oxide semiconductor film, the hydrogen concentration in the oxide semiconductor film, which is measured by SIMS, can be lower than or equal to 5×10 19  atoms/cm 3 , lower than or equal to 1×10 19  atoms/cm 3 , lower than or equal to 5×10 18  atoms/cm 3 , lower than or equal to 1×10 18  atoms/cm 3 , lower than or equal to 5×10 17  atoms/cm 3 , or lower than or equal to 1×10 16  atoms/cm 3 . 
     Next, an insulating film  110 _ 0  is formed over the insulating film  104  and the oxide semiconductor film  108   a  (see  FIG. 17B ). 
     For the insulating film  110 _ 0 , a silicon oxide film or a silicon oxynitride film can be formed with a plasma-enhanced chemical vapor deposition apparatus (a PECVD apparatus or simply referred to as a plasma CVD apparatus). In that case, a deposition gas containing silicon and an oxidizing gas are preferably used as a source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide. 
     A silicon oxynitride film having few defects can be formed as the insulating film  110 _ 0  with a PECVD apparatus under the conditions that the flow rate of the oxidizing gas is more than 20 times and less than 100 times, or more than or equal to 40 times and less than or equal to 80 times the flow rate of the deposition gas and that the pressure in a treatment chamber is lower than 100 Pa, or lower than or equal to 50 Pa. 
     As the insulating film  110 _ 0 , a dense silicon oxide film or a dense silicon oxynitride film can be formed under the following conditions: the substrate placed in a vacuum-evacuated treatment chamber of a PECVD apparatus is held at a temperature higher than or equal to 280° C. and lower than or equal to 400° C., the pressure in the treatment chamber into which a source gas is introduced is set to higher than or equal to 20 Pa and lower than or equal to 250 Pa, preferably higher than or equal to 100 Pa and lower than or equal to 250 Pa, and a high-frequency power is supplied to an electrode provided in the treatment chamber. 
     The insulating film  110 _ 0  may be formed by a PECVD method using a microwave. A microwave refers to a wave in the frequency range of 300 MHz to 300 GHz. In a microwave, electron temperature and electron energy are low. Furthermore, in supplied power, the proportion of power used for acceleration of electrons is low, and therefore, much more power can be used for dissociation and ionization of more molecules. Thus, plasma with high density (high-density plasma) can be excited. This method causes little plasma damage to the deposition surface or a deposit, so that the insulating film  110 _ 0  having few defects can be formed. 
     Alternatively, the insulating film  110 _ 0  can also be formed by a CVD method using an organosilane gas. As the organosilane gas, any of the following silicon-containing compounds can be used: tetraethyl orthosilicate (TEOS) (chemical formula: Si(OC 2 H 5 ) 4 ), tetramethylsilane (TMS) (chemical formula: Si(CH 3 ) 4 ); tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2 H 5 ) 3 ), trisdimethylaminosilane (SiH(N(CH 3 ) 2 ) 3 ), and the like. By a CVD method using an organosilane gas, the insulating film  110 _ 0  having high coverage can be formed. 
     In this embodiment, as the insulating film  110 _ 0 , a 100-nm-thick silicon oxynitride film is formed with a PECVD apparatus. 
     Next, a mask is formed by lithography in a desired position over the insulating film  110 _ 0 , and then, the insulating film  110 _ 0  and the insulating film  104  are partly etched, so that the opening  143  reaching the conductive film  106  is formed (see  FIG. 17C ). 
     To form the opening  143 , a wet etching method and/or a dry etching method can be used. In this embodiment, the opening  143  is formed by a dry etching method. 
     Next, a conductive film  1120  is formed over the conductive film  106  and the insulating film  110 _ 0  so as to cover the opening  143 . In the case where a metal oxide film is used as the conductive film  112 _ 0 , for example, oxygen might be added to the insulating film  110 _ 0  during the formation of the conductive film  112 _ 0  (see  FIG. 17D ). 
     In  FIG. 17D , oxygen added to the insulating film  110 _ 0  is schematically shown by arrows. Furthermore, the conductive film  112 _ 0  formed to cover the opening  143  is electrically connected to the conductive film  106 . 
     In the case where a metal oxide film is used as the conductive film  1120 , the conductive film  112 _ 0  is preferably formed by a sputtering method in an atmosphere containing an oxygen gas. Formation of the conductive film  112 _ 0  in an atmosphere containing an oxygen gas allows suitable addition of oxygen to the insulating film  110 _ 0 . Note that a method for forming the conductive film  112 _ 0  is not limited to a sputtering method, and other methods such as an ALD method may be used. 
     In this embodiment, a 100-nm-thick IGZO film containing an In—Ga—Zn oxide (In:Ga:Zn=4:2:4.1 [atomic ratio]) is formed as the conductive film  112 _ 0  by a sputtering method. Note that oxygen addition treatment may be performed on the insulating film  110 _ 0  before or after the formation of the conductive film  112 _ 0 . The oxygen addition treatment can be performed in a manner similar to that of the oxygen addition treatment that can be performed after the formation of the insulating film  104 . 
     Next, a mask  140  is formed by a lithography process in a desired position over the conductive film  112 _ 0  (see  FIG. 18A ). 
     Next, etching is performed from above the mask  140  to process the conductive film  112 _ 0  and the insulating film  110 _ 0 . After the processing of the conductive film  112 _ 0  and the insulating film  110 _ 0 , the mask  140  is removed. As a result of the processing of the conductive film  112 _ 0  and the insulating film  110 _ 0 , the island-shaped conductive film  112  and the island-shaped insulating film  110  are formed (see  FIG. 18B ). 
     In this embodiment, the conductive film  112 _ 0  and the insulating film  110 _ 0  are processed by a dry etching method. 
     In the processing into the conductive film  112  and the insulating film  110 , the thickness of the oxide semiconductor film  108   a  in a region that does not overlap with the conductive film  112  is decreased in some cases. In other cases, in the processing into the conductive film  112  and the insulating film  110 , the thickness of the insulating film  104  in a region that does not overlap with the oxide semiconductor film  108   a  is decreased. In the processing of the conductive film  112 _ 0  and the insulating film  110 _ 0 , an etchant or an etching gas (e.g., chlorine) might be added to the oxide semiconductor film  108   a  or the constituent element of the conductive film  112 _ 0  or the insulating film  110 _ 0  might be added to the oxide semiconductor film  108   a.    
     Then, the insulating film  116  is formed over the insulating film  104 , the oxide semiconductor film  108   a , and the conductive film  112 . By the formation of the insulating film  116 , part of the oxide semiconductor film  108   a  that is in contact with the insulating film  116  becomes the regions  108   n . Here, the oxide semiconductor film  108   a  overlapping with the conductive film  112  is the oxide semiconductor film  108  (see  FIG. 18C ). 
     Note that the insulating film  116  can be formed using a material selected from the above-mentioned materials. In this embodiment, as the insulating film  116 , a 100-nm-thick silicon nitride oxide film is formed with a PECVD apparatus. In the formation of the silicon nitride oxide film, plasma treatment and deposition treatment are performed at 220° C. The plasma treatment is performed under the following conditions: an argon gas at a flow rate of 100 sccm and a nitrogen gas at a flow rate of 1000 sccm are introduced into a chamber before deposition; the pressure in the chamber is set to 40 Pa; and a power of 1000 W is supplied to an RF power source (27.12 MHz). The deposition treatment is performed under the following conditions: a silane gas at a flow rate of 50 sccm, a nitrogen gas at a flow rate of 5000 sccm, and an ammonia gas at a flow rate of 100 sccm are introduced into the chamber; the pressure in the chamber is set to 100 Pa; and a power of 1000 W is supplied to the RF power source (27.12 MHz). 
     When the insulating film  116  includes a silicon nitride oxide film, nitrogen or hydrogen in the silicon nitride oxide film can be supplied to the region  108   n  in contact with the insulating film  116 . In addition, when the formation temperature of the insulating film  116  is the above temperature, release of excess oxygen contained in the insulating film  110  to the outside can be suppressed. 
     Next, the insulating film  118  is formed over the insulating film  116  (see  FIG. 19A ). 
     The insulating film  118  can be formed using a material selected from the above-mentioned materials. In this embodiment, as the insulating film  118 , a 300-nm-thick silicon oxynitride film is formed with a PECVD apparatus. 
     Then, a mask is formed in desired positions over the insulating film  118  by lithography, and the insulating film  118  and the insulating film  116  are partly etched. Thus, the openings  141   a  and  141   b  reaching the regions  108   n  are formed (see  FIG. 19B ). 
     To etch the insulating film  118  and the insulating film  116 , a wet etching method and/or a dry etching method can be used. In this embodiment, the insulating film  118  and the insulating film  116  are processed by a dry etching method. 
     Next, a conductive film is formed over the region  108   n  and the insulating film  118  to cover the openings  141   a  and  141   b , and processed into desired shapes, so that the conductive films  120   a  and  120   b  are formed (see  FIG. 19C ). 
     The conductive films  120   a  and  120   b  can be formed using a material selected from the above-mentioned materials. In this embodiment, for the conductive films  120   a  and  120   b , a stack including a 50-nm-thick tungsten film and a 400-nm-thick copper film is formed with a sputtering apparatus. 
     To process the conductive film to be the conductive films  120   a  and  120   b , a wet etching method and/or a dry etching method can be used. In this embodiment, in the processing of the conductive film into the conductive films  120   a  and  120   b , the copper film is etched by a wet etching method and then the tungsten film is etched by a dry etching method. 
     Then, the insulating film  122  is formed to cover the conductive films  120   a  and  120   b  and the insulating film  118 . 
     Through the above steps, the transistor  150  in  FIGS. 16A to 16C  can be manufactured. 
     &lt;4-5. Structural Example 3 of Semiconductor Device&gt; 
     Next, a structure that is different from the structures of the above-described transistors is described with reference to  FIGS. 20A to 20C  and  FIGS. 21A to 21C . 
       FIG. 20A  is a top view of a transistor  300 A.  FIG. 20B  is a cross-sectional view taken along the dashed-dotted line X 1 -X 2  in  FIG. 20A .  FIG. 20C  is a cross-sectional view taken along the dashed-dotted line Y 1 -Y 2  in  FIG. 20A . Note that in  FIG. 20A , some components of the transistor  300 A (e.g., an insulating film functioning as a gate insulating film) are not illustrated to avoid complexity. The direction of the dashed-dotted line X 1 -X 2  may be called a channel length direction, and the direction of the dashed-dotted line Y 1 -Y 2  may be called a channel width direction. As in  FIG. 20A , some components might not be illustrated in some top views of transistors described below. 
     The transistor  300 A illustrated in  FIGS. 20A to 20C  includes a conductive film  304  over a substrate  302 , an insulating film  306  over the substrate  302  and the conductive film  304 , an insulating film  307  over the insulating film  306 , an oxide semiconductor film  308  over the insulating film  307 , a conductive film  312   a  over the oxide semiconductor film  308 , and a conductive film  312   b  over the oxide semiconductor film  308 . Over the transistor  300 A, specifically, over the conductive films  312   a  and  312   b  and the oxide semiconductor film  308 , an insulating film  314 , an insulating film  316 , and an insulating film  318  are provided. 
     In the transistor  300 A, the insulating films  306  and  307  each function as a gate insulating film of the transistor  300 A, and the insulating films  314 ,  316 , and  318  each function as a protective insulating film of the transistor  300 A. Moreover, in the transistor  300 A, the conductive film  304  functions as a gate electrode, the conductive film  312   a  functions as a source electrode, and the conductive film  312   b  functions as a drain electrode. 
     In this specification and the like, the insulating films  306  and  307  may be referred to as a first insulating film, the insulating films  314  and  316  may be referred to as a second insulating film, and the insulating film  318  may be referred to as a third insulating film. 
     The transistor  300 A illustrated in  FIGS. 20A to 20C  is a channel-etched transistor. The oxide semiconductor film of one embodiment of the present invention can be used suitably for the channel-etched transistor. 
     &lt;4-6. Structure Example 4 of Semiconductor Device&gt; 
       FIG. 21A  is a top view of a transistor  300 B.  FIG. 21B  is a cross-sectional view taken along the dashed-dotted line X 1 -X 2  in  FIG. 21A .  FIG. 21C  is a cross-sectional view taken along the dashed-dotted line Y 1 -Y 2  in  FIG. 21A . 
     The transistor  300 B in  FIGS. 21A to 21C  includes the conductive film  304  over the substrate  302 , the insulating film  306  over the substrate  302  and the conductive film  304 , the insulating film  307  over the insulating film  306 , the oxide semiconductor film  308  over the insulating film  307 , the conductive film  312   a  over the oxide semiconductor film  308 , the conductive film  312   b  over the oxide semiconductor film  308 , the insulating film  314  over the oxide semiconductor film  308  and the conductive films  312   a  and  312   b , the insulating film  316  over the insulating film  314 , the insulating film  318  over the insulating film  316 , and conductive films  320   a  and  320   b  over the insulating film  318 . 
     In the transistor  300 B, the insulating films  306  and  307  function as first gate insulating films of the transistor  300 B, and the insulating films  314 ,  316 , and  318  function as second gate insulating films of the transistor  300 B. Furthermore, in the transistor  300 B, the conductive film  304  functions as a first gate electrode, the conductive film  320   a  functions as a second gate electrode, and the conductive film  320   b  functions as a pixel electrode used for a display device. The conductive film  312   a  and the conductive film  312   b  function as a source electrode and a drain electrode, respectively. 
     As illustrated in  FIG. 21C , the conductive film  320   a  is connected to the conductive film  304  through an opening  342   b  and an opening  342   c  provided in the insulating films  306 ,  307 ,  314 ,  316 , and  318 . Thus, the same potential is applied to the conductive film  320   a  and the conductive film  304 . 
     The structure of the transistor  300 B is not limited to that described above, in which the openings  342   b  and  342   c  are provided so that the conductive film  320   a  is connected to the conductive film  304 . For example, a structure in which only one of the openings  342   b  and  342   c  is provided so that the conductive film  320   a  is connected to the conductive film  304 , or a structure in which the conductive film  320   a  is not connected to the conductive film  304  without providing the openings  342   b  and  342   c  may be employed. Note that in the case where the conductive film  320   a  is not connected to the conductive film  304 , it is possible to apply different potentials to the conductive film  320   a  and the conductive film  304 . 
     The conductive film  320   b  is connected to the conductive film  312   b  through an opening  342   a  provided in the insulating films  314 ,  316 , and  318 . 
     Note that the transistor  300 B has the S-channel structure described above. 
     Note that the films included in the transistor described in this embodiment (the insulating film, the metal oxide film, the oxide semiconductor film, the conductive film, and the like) can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, or an ALD method. Alternatively, a coating method or a printing method can be used. Although a sputtering method and a plasma-enhanced chemical vapor deposition (PECVD) method are typical examples of the film formation method, a thermal CVD method may be used. As an example of a thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method can be given. 
     At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate. 
     Embodiment 5 
     In this embodiment, an example of a display device that includes any of the transistors described in the above embodiment is described below with reference to  FIG. 22 ,  FIG. 23 , and  FIG. 24 . 
       FIG. 22  is a top view of an example of a display device. A display device  700  in  FIG. 22  includes a pixel portion  702  provided over a first substrate  701 , a source driver circuit portion  704  and a gate driver circuit portion  706  that are provided over the first substrate  701 , a sealant  712  provided to surround the pixel portion  702 , the source driver circuit portion  704 , and the gate driver circuit portion  706 , and a second substrate  705  provided to face the first substrate  701 . The first substrate  701  and the second substrate  705  are sealed with the sealant  712 . That is, the pixel portion  702 , the source driver circuit portion  704 , and the gate driver circuit portion  706  are sealed with the first substrate  701 , the sealant  712 , and the second substrate  705 . Although not illustrated in  FIG. 22 , a display element is provided between the first substrate  701  and the second substrate  705 . 
     In the display device  700 , a flexible printed circuit (FPC) terminal portion  708  electrically connected to the pixel portion  702 , the source driver circuit portion  704 , and the gate driver circuit portion  706  is provided in a region different from the region which is surrounded by the sealant  712  and positioned over the first substrate  701 . Furthermore, an FPC  716  is connected to the FPC terminal portion  708 , and a variety of signals and the like are supplied to the pixel portion  702 , the source driver circuit portion  704 , and the gate driver circuit portion  706  through the FPC  716 . Furthermore, a signal line  710  is connected to the pixel portion  702 , the source driver circuit portion  704 , the gate driver circuit portion  706 , and the FPC terminal portion  708 . The variety of signals and the like are supplied to the pixel portion  702 , the source driver circuit portion  704 , the gate driver circuit portion  706 , and the FPC terminal portion  708  via the signal line  710  from the FPC  716 . 
     A plurality of gate driver circuit portions  706  may be provided in the display device  700 . An example of the display device  700  in which the source driver circuit portion  704  and the gate driver circuit portion  706  are formed over the first substrate  701  where the pixel portion  702  is also formed is described; however, the structure is not limited thereto. For example, only the gate driver circuit portion  706  may be formed over the first substrate  701  or only the source driver circuit portion  704  may be formed over the first substrate  701 . In that case, a substrate over which a source driver circuit, a gate driver circuit, or the like is formed (e.g., a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate  701 . Note that there is no particular limitation on the method for connecting a separately prepared driver circuit substrate, and a chip on glass (COG) method, a wire bonding method, or the like can be used. 
     The pixel portion  702 , the source driver circuit portion  704 , and the gate driver circuit portion  706  included in the display device  700  include a plurality of transistors. As the plurality of transistors, any of the transistors that are the semiconductor devices of embodiments of the present invention can be used. 
     The display device  700  can include any of a variety of elements. Examples of the elements include an electroluminescent (EL) element (e.g., an EL element containing organic and inorganic materials, an organic EL element, an inorganic EL element, or an LED), a light-emitting transistor element (a transistor which emits light depending on current), an electron emitter, a liquid crystal element, an electronic ink display, an electrophoretic element, an electrowetting element, a plasma display panel (PDP), a micro electro mechanical systems (MEMS) display (e.g., a grating light valve (GLV), a digital micromirror device (DMD), a digital micro shutter (DMS) element, or an interferometric modulator display (IMOD) element), and a piezoelectric ceramic display. 
     Examples of a display device including an EL element include an EL display. Examples of a display device including an electron emitter include a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of a display device including a liquid crystal element include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of a display device including electronic ink or an electrophoretic element include electronic paper. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes. Thus, the power consumption can be further reduced. 
     As a display method in the display device  700 , a progressive method, an interlace method, or the like can be employed. Furthermore, color elements controlled in a pixel at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, four pixels of the R pixel, the G pixel, the B pixel, and a W (white) pixel may be included. Alternatively, a color element may be composed of two colors among R, G, and B as in PenTile layout. The two colors may differ among color elements. Alternatively, one or more colors of yellow, cyan, magenta, and the like may be added to RGB. Furthermore, the size of a display region may be different depending on respective dots of the color elements. Embodiments of the disclosed invention are not limited to a display device for color display; the disclosed invention can also be applied to a display device for monochrome display. 
     A coloring layer (also referred to as a color filter) may be used to obtain a full-color display device in which white light (W) is used for a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp). As the coloring layer, red (R), green (G), blue (B), yellow (Y), or the like may be combined as appropriate, for example. With the use of the coloring layer, a higher color reproducibility can be obtained than in the case without the coloring layer. In that case, by providing a region with the coloring layer and a region without the coloring layer, white light in the region without the coloring layer may be directly utilized for display. By partly providing the region without the coloring layer, a decrease in luminance due to the coloring layer can be suppressed, and 20% to 30% of power consumption can be reduced in some cases when an image is displayed brightly. Note that in the case where full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, elements may emit light of their respective colors R, G, B, Y, and W. By using a self-luminous element, power consumption can be further reduced as compared with the case of using the coloring layer in some cases. 
     As a coloring system, any of the following systems may be used: the above-described color filter system in which part of white light is converted into red light, green light, and blue light through color filters; a three-color system in which red light, green light, and blue light are used; and a color conversion system or a quantum dot system in which part of blue light is converted into red light or green light. 
     In this embodiment, structures including a liquid crystal element and an EL element as display elements are described with reference to  FIG. 23  and  FIG. 24 .  FIG. 23  is a cross-sectional view taken along the dashed-dotted line Q-R in  FIG. 22  and shows a structure including an EL element as a display element.  FIG. 24  is a cross-sectional view taken along the dashed-dotted line Q-R in  FIG. 22  and shows a structure including a liquid crystal element as a display element. 
     Common portions between  FIG. 23  and  FIG. 24  are described first, and then different portions are described. 
     &lt;5-1. Portions Common to Display Devices&gt; 
     The display device  700  illustrated in  FIG. 23  and  FIG. 24  includes a lead wiring portion  711 , the pixel portion  702 , the source driver circuit portion  704 , and the FPC terminal portion  708 . Note that the lead wiring portion  711  includes the signal line  710 . The pixel portion  702  includes a transistor  750  and a capacitor  790 . The source driver circuit portion  704  includes a transistor  752 . 
     The transistor  750  and the transistor  752  each have a structure similar to that of the transistor  100  described above. Note that the transistor  750  and the transistor  752  may each have the structure of any of the other transistors described in the above embodiments. 
     The transistors used in this embodiment each include an oxide semiconductor film which is highly purified and in which formation of oxygen vacancies is suppressed. The transistor can have a low off-state current. Accordingly, an electric signal such as an image signal can be held for a longer period, and a writing interval can be set longer in an on state. Accordingly, the frequency of refresh operation can be reduced, which leads to an effect of suppressing power consumption. 
     In addition, the transistor used in this embodiment can have a relatively high field-effect mobility and thus is capable of high speed operation. For example, with such a transistor which can operate at high speed used for a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor in a driver circuit portion can be formed over one substrate. That is, a semiconductor device formed using a silicon wafer or the like is not additionally needed as a driver circuit, by which the number of components of the semiconductor device can be reduced. In addition, the transistor which can operate at high speed can be used also in the pixel portion, whereby a high-quality image can be provided. 
     The capacitor  790  includes a lower electrode that is formed through a step of processing the same conductive film as a conductive film functioning as a first gate electrode of the transistor  750  and an upper electrode that is formed through a step of processing the same conductive film as a conductive film functioning as a source electrode or a drain electrode of the transistor  750 . Between the lower electrode and the upper electrode, an insulating film formed through a step of forming the same insulating film as an insulating film functioning as a first gate insulating film of the transistor  750  is provided. That is, the capacitor  790  has a stacked-layer structure in which the insulating films functioning as a dielectric film are positioned between a pair of electrodes. 
     In  FIG. 23  and  FIG. 24 , a planarization insulating film  770  is provided over the transistor  750 , the transistor  752 , and the capacitor  790 . 
     The planarization insulating film  770  can be formed using a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. Note that the planarization insulating film  770  may be formed by stacking a plurality of insulating films formed from these materials. Alternatively, a structure without the planarization insulating film  770  may be employed. 
     Although  FIG. 23  and  FIG. 24  each illustrate an example in which the transistor  750  included in the pixel portion  702  and the transistor  752  included in the source driver circuit portion  704  have the same structure, one embodiment of the present invention is not limited thereto. For example, the pixel portion  702  and the source driver circuit portion  704  may include different transistors. Specifically, a structure in which a staggered transistor is used in the pixel portion  702  and the inverted staggered transistor described in Embodiment 1 is used in the source driver circuit portion  704 , or a structure in which the inverted staggered transistor described in Embodiment 1 is used in the pixel portion  702  and a staggered transistor is used in the source driver circuit portion  704  may be employed. Note that the term “source driver circuit portion  704 ” can also be replaced by the term “gate driver circuit portion”. 
     The signal line  710  is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors  750  and  752 . In the case where the signal line  710  is formed using a material containing a copper element, signal delay or the like due to wiring resistance is reduced, which enables display on a large screen. 
     The FPC terminal portion  708  includes a connection electrode  760 , an anisotropic conductive film  780 , and the FPC  716 . Note that the connection electrode  760  is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors  750  and  752 . The connection electrode  760  is electrically connected to a terminal included in the FPC  716  through the anisotropic conductive film  780 . 
     For example, a glass substrate can be used as the first substrate  701  and the second substrate  705 . A flexible substrate may be used as the first substrate  701  and the second substrate  705 . Examples of the flexible substrate include a plastic substrate. 
     A structure body  778  is provided between the first substrate  701  and the second substrate  705 . The structure body  778  is a columnar spacer obtained by selective etching of an insulating film and provided to control the distance (cell gap) between the first substrate  701  and the second substrate  705 . Note that a spherical spacer may be used as the structure body  778 . 
     Furthermore, a light-blocking film  738  functioning as a black matrix, a coloring film  736  functioning as a color filter, and an insulating film  734  in contact with the light-blocking film  738  and the coloring film  736  are provided on the second substrate  705  side. 
     &lt;5-2. Structure Example of Input/Output Device of Display Device&gt; 
     In the display device  700  illustrated in  FIG. 23  and  FIG. 24 , a touch panel  791  as an input/output device is provided. Note that the display device  700  that does not include the touch panel  791  may also be used. 
     The touch panel  791  illustrated in  FIG. 23  and  FIG. 23  is what is called an in-cell touch panel provided between the second substrate  705  and the coloring film  736 . The touch panel  791  is formed on the second substrate  705  side before the light-blocking film  738  and the coloring film  736  are formed. 
     The touch panel  791  includes the light-blocking film  738 , an insulating film  792 , an electrode  793 , an electrode  794 , an insulating film  795 , an electrode  796 , and an insulating film  797 . A change in the mutual capacitance between the electrode  793  and the electrode  794  can be sensed when an object such as a finger or a stylus approaches, for example. 
     A portion in which the electrode  793  intersects with the electrode  794  is illustrated in the upper portion of the transistor  750  in  FIG. 23  and  FIG. 24 . Through openings in the insulating film  795 , the electrode  796  is electrically connected to the two electrodes  793  between which the electrode  794  is positioned. Note that a structure in which a region where the electrode  796  is provided is provided in the pixel portion  702  is illustrated in  FIG. 23  and  FIG. 24  as an example; however, one embodiment of the present invention is not limited thereto. For example, the region where the electrode  796  is provided may be provided in the source driver circuit portion  704 . 
     The electrodes  793  and  794  are provided in a region overlapping with the light-blocking film  738 . As illustrated in  FIG. 23 , it is preferable that the electrode  793  do not overlap with a light-emitting element  782 . As illustrated in  FIG. 24 , it is preferable that the electrode  793  do not overlap with a liquid crystal element  775 . In other words, the electrode  793  includes an opening in a region overlapping with the light-emitting element  782  and the liquid crystal element  775 . That is, the electrode  793  has a mesh shape. With this structure, the electrode  793  does not block light emitted from the light-emitting element  782 . Alternatively, the electrode  793  can have a structure in which light transmitted through the liquid crystal element  775  is not blocked. Thus, since luminance is hardly reduced even when the touch panel  791  is placed, a display device with high visibility and low power consumption can be achieved. Note that the electrode  794  can have a similar structure. 
     In addition, since the electrodes  793  and  794  do not overlap with the light-emitting element  782 , the electrodes  793  and  794  can be formed using a metal material with a low visible light transmittance. Furthermore, since the electrode  793  and the electrode  794  do not overlap with the liquid crystal element  775 , a metal material having a low transmittance with respect to visible light can be used for the electrode  793  and the electrode  794 . 
     Accordingly, the resistance of the electrodes  793  and  794  can be reduced as compared with an electrode using an oxide material with a high visible light transmittance, so that the sensitivity of the touch panel can be increased. 
     For example, conductive nanowires may be used for the electrodes  793 ,  794 , and  796 . The nanowires may have a mean diameter greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, more preferably greater than or equal to 5 nm and less than or equal to 25 nm. As the nanowire, a carbon nanotube or a metal nanowire such as an Ag nanowire, a Cu nanowire, or an Al nanowire may be used. For example, in the case where an Ag nanowire is used for any one of or all of the electrodes  793 ,  794 , and  796 , the transmittance of visible light can be greater than or equal to 89% and the sheet resistance can be greater than or equal to 40 Ω/square and less than or equal to 100 Ω/square. 
     Although the structure of the in-cell touch panel is illustrated in  FIG. 23  and  FIG. 24 , one embodiment of the present invention is not limited thereto. For example, a touch panel formed over the display device  700 , what is called an on-cell touch panel, or a touch panel attached to the display device  700 , what is called an out-cell touch panel may be used. In this manner, the display device  700  of one embodiment of the present invention can be combined with various types of touch panels. 
     &lt;5-3. Display Device Including Light-Emitting Element&gt; 
     The display device  700  illustrated in  FIG. 23  includes the light-emitting element  782 . The light-emitting element  782  includes a conductive film  772 , an EL layer  786 , and a conductive film  788 . The display device  700  in  FIG. 23  is capable of displaying an image by light emission from the EL layer  786  included in the light-emitting element  782 . Note that the EL layer  786  contains an organic compound or an inorganic compound such as a quantum dot. 
     Examples of a material that can be used for an organic compound include a fluorescent material and a phosphorescent material. Examples of a material that can be used for a quantum dot include a colloidal quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material. The quantum dot containing elements belonging to Groups 12 and 16, elements belonging to Groups 13 and 15, or elements belonging to Groups 14 and 16, may be used. Alternatively, a quantum dot material containing an element such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), or aluminum (Al) may be used. 
     In the display device  700  in  FIG. 23 , an insulating film  730  is provided over the planarization insulating film  770  and the conductive film  772 . The insulating film  730  covers part of the conductive film  772 . Note that the light-emitting element  782  has a top emission structure. Therefore, the conductive film  788  has a light-transmitting property and transmits light emitted from the EL layer  786 . Although the top-emission structure is described as an example in this embodiment, one embodiment of the present invention is not limited thereto. A bottom-emission structure in which light is emitted to the conductive film  772  side, or a dual-emission structure in which light is emitted to both the conductive film  772  side and the conductive film  788  side may be employed. 
     The coloring film  736  is provided to overlap with the light-emitting element  782 , and the light-blocking film  738  is provided to overlap with the insulating film  730  and to be included in the lead wiring portion  711  and in the source driver circuit portion  704 . The coloring film  736  and the light-blocking film  738  are covered with the insulating film  734 . A space between the light-emitting element  782  and the insulating film  734  is filled with a sealing film  732 . Although a structure with the coloring film  736  is described as the display device  700  in  FIG. 23 , the structure is not limited thereto. In the case where the EL layer  786  is formed by a separate coloring method, the coloring film  736  is not necessarily provided. 
     &lt;5-4. Structure Example of Display Device Including Liquid Crystal Element&gt; 
     The display device  700  in  FIG. 24  includes the liquid crystal element  775 . The liquid crystal element  775  includes a conductive film  772 , an insulating film  773 , a conductive film  774 , and a liquid crystal layer  776 . The conductive film  774  functions as a common electrode, and an electric field generated between the conductive film  772  and the conductive film  774  through the insulating film  773  can control the alignment state in the liquid crystal layer  776 . The display device  700  in  FIG. 24  can display an image in such a manner that transmission or non-transmission of light is controlled by the alignment state in the liquid crystal layer  776  which is changed depending on the voltage applied between the conductive film  772  and the conductive film  774 . 
     The conductive film  772  is electrically connected to the conductive film functioning as the source electrode or the drain electrode of the transistor  750 . The conductive film  772  is formed over the planarization insulating film  770  to function as a pixel electrode, i.e., one electrode of the display element. 
     A conductive film that transmits visible light or a conductive film that reflects visible light can be used as the conductive film  772 . For example, a material including one kind selected from indium (In), zinc (Zn), and tin (Sn) is preferably used for the conductive film that transmits visible light. For example, a material including aluminum or silver may be used for the conductive film that reflects visible light. In this embodiment, the conductive film that reflects visible light is used as the conductive film  772 . 
     Although  FIG. 24  illustrates an example in which the conductive film  772  is connected to the conductive film functioning as the drain electrode of the transistor  750 , one embodiment of the present invention is not limited to this example. For example, the conductive film  772  may be electrically connected to the conductive film functioning as the drain electrode of the transistor  750  through a conductive film functioning as a connection electrode. 
     Although not illustrated in  FIG. 24 , an alignment film may be provided in contact with the liquid crystal layer  776 . Although not illustrated in  FIG. 24 , an optical member (optical substrate) or the like, such as a polarizing member, a retardation member, or an anti-reflection member, may be provided as appropriate. For example, circular polarization may be employed by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, or the like may be used as a light source. 
     In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions. 
     Alternatively, in the case of employing a horizontal electric field mode, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while the temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which several weight percent or more of a chiral material is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition which includes liquid crystal exhibiting a blue phase and a chiral material has a short response time and optical isotropy, which makes the alignment process unneeded. An alignment film does not need to be provided and rubbing treatment is thus not necessary; accordingly, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. Moreover, the liquid crystal material which exhibits a blue phase has a small viewing angle dependence. 
     In the case where a liquid crystal element is used as the display element, a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, or the like can be used. 
     Furthermore, a normally black liquid crystal display device such as a transmissive liquid crystal display device utilizing a vertical alignment (VA) mode may also be used. There are some examples of a vertical alignment mode; for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASV mode, or the like can be employed. 
     At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate. 
     Embodiment 6 
     In this embodiment, an example of a display panel which can be used for a display portion or the like in a display device including the semiconductor device of one embodiment of the present invention is described with reference to  FIG. 25  and  FIG. 26 . The display panel described below as an example includes both a reflective liquid crystal element and a light-emitting element and can display an image in both the transmissive mode and the reflective mode. 
     &lt;6-1. Structure Example of Display Panel&gt; 
       FIG. 25  is a schematic perspective view illustrating a display panel  600  of one embodiment of the present invention. In the display panel  600 , a substrate  651  and a substrate  661  are attached to each other. In  FIG. 25 , the substrate  661  is denoted by a dashed line. 
     The display panel  600  includes a display portion  662 , a circuit  659 , a wiring  666 , and the like. The substrate  651  is provided with the circuit  659 , the wiring  666 , a conductive film  663  which serves as a pixel electrode, and the like. In  FIG. 25 , an IC  673  and an FPC  672  are mounted on the substrate  651 . Thus, the structure illustrated in  FIG. 25  can be referred to as a display module including the display panel  600 , the FPC  672 , and the IC  673 . 
     As the circuit  659 , for example, a circuit functioning as a scan line driver circuit can be used. 
     The wiring  666  has a function of supplying a signal or electric power to the display portion or the circuit  659 . The signal or electric power is input to the wiring  666  from the outside through the FPC  672  or from the IC  673 . 
       FIG. 25  illustrates an example in which the IC  673  is provided on the substrate  651  by a chip on glass (COG) method or the like. As the IC  673 , an IC functioning as a scan line driver circuit, a signal line driver circuit, or the like can be used. Note that it is possible that the IC  673  is not provided when, for example, the display panel  600  includes circuits serving as a scan line driver circuit and a signal line driver circuit and when the circuits serving as a scan line driver circuit and a signal line driver circuit are provided outside and a signal for driving the display panel  600  is input through the FPC  672 . Alternatively, the IC  673  may be mounted on the FPC  672  by a chip on film (COF) method or the like. 
       FIG. 25  also shows an enlarged view of part of the display portion  662 . The conductive films  663  included in a plurality of display elements are arranged in a matrix in the display portion  662 . The conductive film  663  has a function of reflecting visible light and serves as a reflective electrode of a liquid crystal element  640  described later. 
     As illustrated in  FIG. 25 , the conductive film  663  includes an opening. A light-emitting element  660  is positioned closer to the substrate  651  than the conductive film  663  is. Light is emitted from the light-emitting element  660  to the substrate  661  side through the opening in the conductive film  663 . 
     &lt;6-2. Cross-Sectional Structure Example&gt; 
       FIG. 26  illustrates an example of cross sections of part of a region including the FPC  672 , part of a region including the circuit  659 , and part of a region including the display portion  662  of the display panel illustrated in  FIG. 25 . 
     The display panel includes an insulating film  620  between the substrates  651  and  661 . The display panel also includes the light-emitting element  660 , a transistor  601 , a transistor  605 , a transistor  606 , a coloring layer  634 , and the like between the substrate  651  and the insulating film  620 . Furthermore, the display panel includes the liquid crystal element  640 , a coloring layer  631 , and the like between the insulating film  620  and the substrate  661 . The substrate  661  and the insulating film  620  are bonded with an adhesive layer  641 . The substrate  651  and the insulating film  620  are bonded with an adhesive layer  642 . 
     The transistor  606  is electrically connected to the liquid crystal element  640  and the transistor  605  is electrically connected to the light-emitting element  660 . Since the transistors  605  and  606  are formed on a surface of the insulating film  620  which is on the substrate  651  side, the transistors  605  and  606  can be formed through the same process. 
     The substrate  661  is provided with the coloring layer  631 , a light-blocking film  632 , an insulating film  621 , a conductive film  613  serving as a common electrode of the liquid crystal element  640 , an alignment film  633   b , an insulating film  617 , and the like. The insulating film  617  serves as a spacer for keeping a cell gap of the liquid crystal element  640 . 
     Insulating layers such as an insulating film  681 , an insulating film  682 , an insulating film  683 , an insulating film  684 , and an insulating film  685  are provided on the substrate  651  side of the insulating film  620 . Part of the insulating film  681  functions as a gate insulating layer of each transistor. The insulating films  682 ,  683 , and  684  are provided to cover each transistor. The insulating film  685  is provided to cover the insulating film  684 . The insulating films  684  and  685  each function as a planarization layer. Note that an example in which the three insulating layers, the insulating films  682 ,  683 , and  684 , are provided to cover the transistors and the like is described here; however, one embodiment of the present invention is not limited to this example, and four or more insulating layers, a single insulating layer, or two insulating layers may be provided. The insulating film  684  functioning as a planarization layer is not necessarily provided when not needed. 
     The transistors  601 ,  605 , and  606  each include a conductive film  654  part of which functions as a gate, a conductive film  652  part of which functions as a source or a drain, and a semiconductor film  653 . Here, a plurality of layers obtained by processing the same conductive film are shown with the same hatching pattern. 
     The liquid crystal element  640  is a reflective liquid crystal element. The liquid crystal element  640  has a stacked structure of a conductive film  635 , a liquid crystal layer  612 , and the conductive film  613 . In addition, the conductive film  663  which reflects visible light is provided in contact with the surface of the conductive film  635  that faces the substrate  651 . The conductive film  663  includes an opening  655 . The conductive films  635  and  613  contain a material which transmits visible light. In addition, an alignment film  633   a  is provided between the liquid crystal layer  612  and the conductive film  635  and the alignment film  633   b  is provided between the liquid crystal layer  612  and the conductive film  613 . A polarizing plate  656  is provided on an outer surface of the substrate  661 . 
     In the liquid crystal element  640 , the conductive film  663  has a function of reflecting visible light and the conductive film  613  has a function of transmitting visible light. Light entering from the substrate  661  side is polarized by the polarizing plate  656 , passes through the conductive film  613  and the liquid crystal layer  612 , and is reflected by the conductive film  663 . Then, the light passes through the liquid crystal layer  612  and the conductive film  613  again and reaches the polarizing plate  656 . In that case, alignment of the liquid crystal is controlled with a voltage that is applied between the conductive film  613  and the conductive film  663 , and thus optical modulation of light can be controlled. That is, the intensity of light emitted through the polarizing plate  656  can be controlled. Light excluding light in a particular wavelength region is absorbed by the coloring layer  631 , and thus, emitted light is red light, for example. 
     The light-emitting element  660  is a bottom-emission light-emitting element. The light-emitting element  660  has a structure in which a conductive film  643 , an EL layer  644 , and a conductive film  645   b  are stacked in this order from the insulating film  620  side. In addition, a conductive film  645   a  is provided to cover the conductive film  645   b . The conductive film  645   b  contains a material which reflects visible light, and the conductive films  643  and  645   a  contain a material which transmits visible light. Light is emitted from the light-emitting element  660  to the substrate  661  side through the coloring layer  634 , the insulating film  620 , the opening  655 , the conductive film  613 , and the like. 
     Here, as illustrated in  FIG. 26 , the conductive film  635  which transmits visible light is preferably provided in the opening  655 . Accordingly, the liquid crystal layer  612  is aligned in a region overlapping with the opening  655  as well as in the other regions, in which case an alignment defect of the liquid crystal is prevented from being generated in the boundary portion of these regions and undesired light leakage can be suppressed. 
     As the polarizing plate  656  provided on an outer surface of the substrate  661 , a linear polarizing plate or a circularly polarizing plate can be used. An example of a circularly polarizing plate is a stack including a linear polarizing plate and a quarter-wave retardation plate. Such a structure can reduce reflection of external light. The cell gap, alignment, drive voltage, and the like of the liquid crystal element used as the liquid crystal element  640  are controlled depending on the kind of the polarizing plate so that a desirable contrast is obtained. 
     In addition, an insulating film  647  is provided on the insulating film  646  covering an end portion of the conductive film  643 . The insulating film  647  has a function as a spacer for preventing the insulating film  620  and the substrate  651  from getting closer more than necessary. In the case where the EL layer  644  or the conductive film  645   a  is formed using a blocking mask (metal mask), the insulating film  647  may have a function of preventing the blocking mask from being in contact with a surface on which the EL layer  644  or the conductive film  645   a  is formed. Note that the insulating film  647  is not necessarily provided when not needed. 
     One of a source and a drain of the transistor  605  is electrically connected to the conductive film  643  of the light-emitting element  660  through a conductive film  648 . 
     One of a source and a drain of the transistor  606  is electrically connected to the conductive film  663  through a connection portion  607 . The conductive films  663  and  635  are in contact with and electrically connected to each other. Here, in the connection portion  607 , the conductive layers provided on both surfaces of the insulating film  620  are connected to each other through an opening in the insulating film  620 . 
     A connection portion  604  is provided in a region where the substrates  651  and  661  do not overlap with each other. The connection portion  604  is electrically connected to the FPC  672  through a connection layer  649 . The connection portion  604  has a structure similar to that of the connection portion  607 . On the top surface of the connection portion  604 , a conductive layer obtained by processing the same conductive film as the conductive film  635  is exposed. Thus, the connection portion  604  and the FPC  672  can be electrically connected to each other through the connection layer  649 . 
     A connection portion  687  is provided in part of a region where the adhesive layer  641  is provided. In the connection portion  687 , the conductive layer obtained by processing the same conductive film as the conductive film  635  is electrically connected to part of the conductive film  613  with a connector  686 . Accordingly, a signal or a potential input from the FPC  672  connected to the substrate  651  side can be supplied to the conductive film  613  formed on the substrate  661  side through the connection portion  687 . 
     As the connector  686 , a conductive particle can be used, for example. As the conductive particle, a particle of an organic resin, silica, or the like coated with a metal material can be used. It is preferable to use nickel or gold as the metal material because contact resistance can be decreased. It is also preferable to use a particle coated with layers of two or more kinds of metal materials, such as a particle coated with nickel and further with gold. As the connector  686 , a material capable of elastic deformation or plastic deformation is preferably used. As illustrated in  FIG. 26 , the connector  686  which is the conductive particle has a shape that is vertically crushed in some cases. With the crushed shape, the contact area between the connector  686  and a conductive layer electrically connected to the connector  686  can be increased, thereby reducing contact resistance and suppressing the generation of problems such as disconnection. 
     The connector  686  is preferably provided so as to be covered with the adhesive layer  641 . For example, the connectors  686  are dispersed in the adhesive layer  641  before curing of the adhesive layer  641 . 
       FIG. 26  illustrates an example of the circuit  659  in which the transistor  601  is provided. 
     The structure in which the semiconductor film  653  where a channel is formed is provided between two gates is used as an example of the transistors  601  and  605  in  FIG. 26 . One gate is formed using the conductive film  654  and the other gate is formed using a conductive film  623  overlapping with the semiconductor film  653  with the insulating film  682  provided therebetween. Such a structure enables control of threshold voltages of transistors. In that case, the two gates may be connected to each other and supplied with the same signal to operate the transistors. Such transistors can have a higher field-effect mobility and thus have higher on-state current than other transistors. Consequently, a circuit capable of high-speed operation can be obtained. Furthermore, the area occupied by a circuit portion can be reduced. The use of the transistor having high on-state current can reduce signal delay in wirings and can reduce display unevenness even in a display panel in which the number of wirings is increased because of increase in size or definition. 
     Note that the transistor included in the circuit  659  and the transistor included in the display portion  662  may have the same structure. A plurality of transistors included in the circuit  659  may have the same structure or different structures. A plurality of transistors included in the display portion  662  may have the same structure or different structures. 
     A material through which impurities such as water and hydrogen do not easily diffuse is preferably used for at least one of the insulating films  682  and  683  which cover the transistors. That is, the insulating film  682  or the insulating film  683  can function as a barrier film. Such a structure can effectively suppress diffusion of the impurities into the transistors from the outside, and a highly reliable display panel can be provided. 
     The insulating film  621  is provided on the substrate  661  side to cover the coloring layer  631  and the light-blocking film  632 . The insulating film  621  may have a function as a planarization layer. The insulating film  621  enables the conductive film  613  to have an almost flat surface, resulting in a uniform alignment state of the liquid crystal layer  612 . 
     An example of the method for manufacturing the display panel  600  is described. For example, the conductive film  635 , the conductive film  663 , and the insulating film  620  are formed in order over a support substrate provided with a separation layer, and the transistor  605 , the transistor  606 , the light-emitting element  660 , and the like are formed. Then, the substrate  651  and the support substrate are bonded with the adhesive layer  642 . After that, separation is performed at the interface between the separation layer and each of the insulating film  620  and the conductive film  635 , whereby the support substrate and the separation layer are removed. Separately, the coloring layer  631 , the light-blocking film  632 , the conductive film  613 , and the like are formed over the substrate  661  in advance. Then, liquid crystal is dropped onto the substrate  651  or  661  and the substrates  651  and  661  are bonded with the adhesive layer  641 , whereby the display panel  600  can be manufactured. 
     A material for the separation layer can be selected as appropriate such that separation at the interface with the insulating film  620  and the conductive film  635  occurs. In particular, it is preferable that a stacked layer of a layer including a high-melting-point metal material, such as tungsten, and a layer including an oxide of the metal material be used as the separation layer, and a stacked layer of a plurality of layers, such as a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer be used as the insulating film  620  over the separation layer. The use of the high-melting-point metal material for the separation layer can increase the formation temperature of a layer formed in a later step, which reduces the impurity concentration and achieves a highly reliable display panel. 
     As the conductive film  635 , an oxide or a nitride such as a metal oxide, a metal nitride, or an oxide semiconductor whose resistance is reduced is preferably used. In the case of using an oxide semiconductor, a material in which at least one of the concentrations of hydrogen, boron, phosphorus, nitrogen, and other impurities and the number of oxygen vacancies is made to be higher than those in a semiconductor layer of a transistor is used for the conductive film  635 . 
     &lt;6-3. Components&gt; 
     The above components are described below. Note that the description of structures having functions similar to those in the above embodiments is omitted. 
     [Adhesive Layer] 
     As the adhesive layer, a variety of curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, an anaerobic adhesive, and a photocurable adhesive such as an ultraviolet curable adhesive can be used. Examples of these adhesives include an epoxy resin, an acrylic resin, a silicone resin, a phenol resin, a polyimide resin, an imide resin, a polyvinyl chloride (PVC) resin, a polyvinyl butyral (PVB) resin, and an ethylene vinyl acetate (EVA) resin. In particular, a material with low moisture permeability, such as an epoxy resin, is preferred. Alternatively, a two-component type resin may be used. Alternatively, an adhesive sheet or the like may be used. 
     Furthermore, the resin may contain a drying agent. For example, a substance that adsorbs moisture by chemical adsorption, such as an oxide of an alkaline earth metal (e.g., calcium oxide or barium oxide), can be used. Alternatively, a substance that adsorbs moisture by physical adsorption, such as zeolite or silica gel, may be used. The drying agent is preferably contained because it can prevent impurities such as moisture from entering the element, thereby improving the reliability of the display panel. 
     In addition, it is preferable to mix a filler with a high refractive index or a light-scattering member into the resin, in which case light extraction efficiency can be enhanced. For example, titanium oxide, barium oxide, zeolite, zirconium, or the like can be used. 
     [Connection Layer] 
     As the connection layers, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like can be used. 
     [Coloring Layer] 
     Examples of a material that can be used for the coloring layers include a metal material, a resin material, and a resin material containing a pigment or dye. 
     [Light-Blocking Layer] 
     Examples of a material that can be used for the light-blocking layer include carbon black, titanium black, a metal, a metal oxide, and a composite oxide containing a solid solution of a plurality of metal oxides. The light-blocking layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. Stacked films containing the material of the coloring layer can also be used for the light-blocking layer. For example, a stacked-layer structure of a film containing a material of a coloring layer which transmits light of a certain color and a film containing a material of a coloring layer which transmits light of another color can be employed. It is preferable that the coloring layer and the light-blocking layer be formed using the same material because the same manufacturing apparatus can be used and the process can be simplified. 
     The above is the description of the components. 
     &lt;6-4. Manufacturing Method Example&gt; 
     A manufacturing method example of a display panel using a flexible substrate is described. 
     Here, layers including a display element, a circuit, a wiring, an electrode, optical members such as a coloring layer and a light-blocking layer, an insulating layer, and the like, are collectively referred to as an element layer. The element layer includes, for example, a display element, and may additionally include a wiring electrically connected to the display element or an element such as a transistor used in a pixel or a circuit. 
     In addition, here, a flexible member which supports the element layer at a stage at which the display element is completed (the manufacturing process is finished) is referred to as a substrate. For example, a substrate includes an extremely thin film with a thickness greater than or equal to 10 nm and less than or equal to 300 μm and the like. 
     As a method for forming an element layer over a flexible substrate provided with an insulating surface, typically, there are two methods described below. One of them is to directly form an element layer over the substrate. The other method is to form an element layer over a supporting base that is different from the substrate and then to separate the element layer from the supporting base to be transferred to the substrate. Although not described in detail here, in addition to the above two methods, there is a method in which the element layer is formed over a substrate which does not have flexibility and the substrate is thinned by polishing or the like to have flexibility. 
     In the case where a material of the substrate can withstand heating temperature in a process for forming the element layer, it is preferable that the element layer be formed directly over the substrate, in which case a manufacturing process can be simplified. At this time, the element layer is preferably formed in a state where the substrate is fixed to the supporting base, in which case transfer thereof in an apparatus and between apparatuses can be easy. 
     In the case of employing the method in which the element layer is formed over the supporting base and then transferred to the substrate, first, a separation layer and an insulating layer are stacked over the supporting base, and then, the element layer is formed over the insulating layer. Next, the element layer is separated from the supporting base and then transferred to the substrate. At this time, a material is selected that would cause separation at the interface between the supporting base and the separation layer, at the interface between the separation layer and the insulating layer, or in the separation layer. In this method, it is preferred that a material having high heat resistance be used for the supporting base or the separation layer, in which case the upper limit of the temperature applied when the element layer is formed can be higher, and an element layer including a more reliable element can be formed. 
     For example, it is preferable that a stack of a layer containing a high-melting-point metal material such as tungsten and a layer containing an oxide of the metal material be used as the separation layer, and a stack of a plurality of layers such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer be used as the insulating layer over the separation layer. 
     The element layer and the supporting base can be separated by applying mechanical power, by etching the separation layer, by injecting a liquid into the separation interface, or the like. Alternatively, separation may be performed by heating or cooling two layers of the separation interface by utilizing a difference in thermal expansion coefficient. 
     The separation layer is not necessarily provided in the case where separation can occur at the interface between the supporting base and the insulating layer. 
     For example, glass and an organic resin such as polyimide can be used as the supporting base and the insulating layer, respectively. In that case, a separation trigger may be formed by, for example, locally heating part of the organic resin with laser light or the like, or by physically cutting part of or making a hole through the organic resin with a sharp tool, so that separation may be performed at the interface between the glass and the organic resin. As the above-described organic resin, a photosensitive material is preferably used because an opening or the like can be easily formed. The above-described laser light preferably has a wavelength region, for example, from visible light to ultraviolet light. For example, light having a wavelength greater than or equal to 200 nm and less than or equal to 400 nm, preferably greater than or equal to 250 nm and less than or equal to 350 nm can be used. In particular, an excimer laser having a wavelength of 308 nm is preferably used because the productivity is increased. Alternatively, a solid-state UV laser (also referred to as a semiconductor UV laser), such as a UV laser having a wavelength of 355 nm which is the third harmonic of an Nd:YAG laser, may be used. 
     Alternatively, a heat-generation layer may be provided between the supporting base and the insulating layer formed of an organic resin, and separation may be performed at the interface between the heat-generation layer and the insulating layer by heating the heat-generation layer. The heat-generation layer can be formed using a variety of materials such as a material that generates heat when current flows therethrough, a material that generates heat when absorbs light, or a material that generates heat when applied with a magnetic field. For example, a semiconductor, a metal, or an insulator can be selected for the heat-generation layer. 
     In the aforementioned methods, the insulating layer formed of an organic resin can be used as a substrate after the separation. 
     The above is the description of a manufacturing method of a flexible display panel. 
     At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate. 
     Embodiment 7 
     In this embodiment, a display device that includes a semiconductor device of one embodiment of the present invention is described with reference to  FIGS. 27A to 27C . 
     &lt;7. Circuit Configuration of Display Device&gt; 
     The display device illustrated in  FIG. 27A  includes a region including pixels of display elements (hereinafter the region is referred to as a pixel portion  502 ), a circuit portion provided outside the pixel portion  502  and including a circuit for driving the pixels (hereinafter the portion is referred to as a driver circuit portion  504 ), circuits each having a function of protecting an element (hereinafter the circuits are referred to as protection circuits  506 ), and a terminal portion  507 . Note that the protection circuits  506  are not necessarily provided. 
     Part or the whole of the driver circuit portion  504  is preferably formed over a substrate over which the pixel portion  502  is formed. Thus, the number of components and the number of terminals can be reduced. When part or the whole of the driver circuit portion  504  is not formed over the substrate over which the pixel portion  502  is formed, the part or the whole of the driver circuit portion  504  can be mounted by COG or tape automated bonding (TAB). 
     The pixel portion  502  includes a plurality of circuits for driving display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more) (hereinafter, such circuits are referred to as pixel circuits  501 ). The driver circuit portion  504  includes driver circuits such as a circuit for supplying a signal (scan signal) to select a pixel (hereinafter, the circuit is referred to as a gate driver  504   a ) and a circuit for supplying a signal (data signal) to drive a display element in a pixel (hereinafter, the circuit is referred to as a source driver  504   b ). 
     The gate driver  504   a  includes a shift register or the like. The gate driver  504   a  receives a signal for driving the shift register through the terminal portion  507  and outputs a signal. For example, the gate driver  504   a  receives a start pulse signal, a clock signal, or the like and outputs a pulse signal. The gate driver  504   a  has a function of controlling the potentials of wirings supplied with scan signals (hereinafter, such wirings are referred to as scan lines GL_ 1  to GL_X). Note that a plurality of gate drivers  504   a  may be provided to control the scan lines GL_ 1  to GL_X separately. Alternatively, the gate driver  504   a  has a function of supplying an initialization signal. Without being limited thereto, the gate driver  504   a  can supply another signal. 
     The source driver  504   b  includes a shift register or the like. The source driver  504   b  receives a signal (image signal) from which a data signal is derived, as well as a signal for driving the shift register, through the terminal portion  507 . The source driver  504   b  has a function of generating a data signal to be written to the pixel circuit  501  which is based on the image signal. In addition, the source driver  504   b  has a function of controlling output of a data signal in response to a pulse signal produced by input of a start pulse signal, a clock signal, or the like. Furthermore, the source driver  504   b  has a function of controlling the potentials of wirings supplied with data signals (hereinafter such wirings are referred to as data lines DL_ 1  to DL_Y). Alternatively, the source driver  504   b  has a function of supplying an initialization signal. Without being limited thereto, the source driver  504   b  can supply another signal. 
     The source driver  504   b  includes a plurality of analog switches, for example. The source driver  504   b  can output, as the data signals, signals obtained by time-dividing the image signal by sequentially turning on the plurality of analog switches. The source driver  504   b  may include a shift register or the like. 
     A pulse signal and a data signal are input to each of the plurality of pixel circuits  501  through one of the plurality of scan lines GL supplied with scan signals and one of the plurality of data lines DL supplied with data signals, respectively. Writing and holding of the data signal to and in each of the plurality of pixel circuits  501  are controlled by the gate driver  504   a . For example, to the pixel circuit  501  in the m-th row and the n-th column (m is a natural number less than or equal to X, and n is a natural number less than or equal to Y), a pulse signal is input from the gate driver  504   a  through the scan line GL_m, and a data signal is input from the source driver  504   b  through the data line DL_n in accordance with the potential of the scan line GL_m. 
     The protection circuit  506  illustrated in  FIG. 27A  is connected to, for example, the scan line GL between the gate driver  504   a  and the pixel circuit  501 . Alternatively, the protection circuit  506  is connected to the data line DL between the source driver  504   b  and the pixel circuit  501 . Alternatively, the protection circuit  506  can be connected to a wiring between the gate driver  504   a  and the terminal portion  507 . Alternatively, the protection circuit  506  can be connected to a wiring between the source driver  504   b  and the terminal portion  507 . Note that the terminal portion  507  means a portion having terminals for inputting power, control signals, and image signals to the display device from external circuits. 
     The protection circuit  506  is a circuit that electrically connects a wiring connected to the protection circuit to another wiring when a potential out of a certain range is applied to the wiring connected to the protection circuit. 
     As illustrated in  FIG. 27A , the protection circuits  506  are provided for the pixel portion  502  and the driver circuit portion  504 , so that the resistance of the display device to overcurrent generated by electrostatic discharge (ESD) or the like can be improved. Note that the configuration of the protection circuits  506  is not limited thereto; for example, the protection circuit  506  may be configured to be connected to the gate driver  504   a  or the protection circuit  506  may be configured to be connected to the source driver  504   b . Alternatively, the protection circuit  506  may be configured to be connected to the terminal portion  507 . 
     In  FIG. 27A , an example in which the driver circuit portion  504  includes the gate driver  504   a  and the source driver  504   b  is illustrated; however, the structure is not limited thereto. For example, only the gate driver  504   a  may be formed and a separately prepared substrate where a source driver circuit is formed (e.g., a driver circuit substrate formed with a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted. 
     Each of the plurality of pixel circuits  501  in  FIG. 27A  can have a configuration illustrated in  FIG. 27B , for example. 
     The pixel circuit  501  illustrated in  FIG. 27B  includes a liquid crystal element  570 , a transistor  550 , and a capacitor  560 . As the transistor  550 , any of the transistors described in the above embodiment, for example, can be used. 
     The potential of one of a pair of electrodes of the liquid crystal element  570  is set in accordance with the specifications of the pixel circuit  501  as appropriate. The alignment state of the liquid crystal element  570  depends on written data. A common potential may be supplied to one of the pair of electrodes of the liquid crystal element  570  included in each of the plurality of pixel circuits  501 . Furthermore, the potential supplied to one of the pair of electrodes of the liquid crystal element  570  in the pixel circuit  501  in one row may be different from the potential supplied to one of the pair of electrodes of the liquid crystal element  570  in the pixel circuit  501  in another row. 
     Examples of a driving method of the display device including the liquid crystal element  570  include a TN mode, an STN mode, a VA mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an MVA mode, a patterned vertical alignment (PVA) mode, an IPS mode, an FFS mode, and a transverse bend alignment (TBA) mode. Other examples of the driving method of the display device include an electrically controlled birefringence (ECB) mode, a polymer-dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (PNLC) mode, and a guest-host mode. Without being limited thereto, various liquid crystal elements and driving methods can be used. 
     In the pixel circuit  501  in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor  550  is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element  570 . A gate electrode of the transistor  550  is electrically connected to the scan line GL_m. The transistor  550  has a function of controlling whether to write a data signal by being turned on or off. 
     One of a pair of electrodes of the capacitor  560  is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element  570 . The potential of the potential supply line VL is set in accordance with the specifications of the pixel circuit  501  as appropriate. The capacitor  560  functions as a storage capacitor for storing written data. 
     For example, in the display device including the pixel circuit  501  in  FIG. 27B , the pixel circuits  501  are sequentially selected row by row by the gate driver  504   a  illustrated in  FIG. 27A , whereby the transistors  550  are turned on and a data signal is written. 
     When the transistors  550  are turned off, the pixel circuits  501  in which the data has been written are brought into a holding state. This operation is sequentially performed row by row; thus, an image is displayed. 
     Alternatively, each of the plurality of pixel circuits  501  in  FIG. 27A  can have a configuration illustrated in  FIG. 27C , for example. 
     In addition, the pixel circuit  501  illustrated in  FIG. 27C  includes transistors  552  and  554 , a capacitor  562 , and a light-emitting element  572 . Any of the transistors described in the above embodiment, for example, can be used as one or both of the transistors  552  and  554 . 
     One of a source electrode and a drain electrode of the transistor  552  is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as the signal line DL_n). A gate electrode of the transistor  552  is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as the scan line GL_m). 
     The transistor  552  has a function of controlling whether to write a data signal by being turned on or off. 
     One of a pair of electrodes of the capacitor  562  is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor  552 . 
     The capacitor  562  functions as a storage capacitor for storing written data. 
     One of a source electrode and a drain electrode of the transistor  554  is electrically connected to the potential supply line VL_a. Furthermore, a gate electrode of the transistor  554  is electrically connected to the other of the source electrode and the drain electrode of the transistor  552 . 
     One of an anode and a cathode of the light-emitting element  572  is electrically connected to a potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor  554 . 
     As the light-emitting element  572 , an organic electroluminescent element (also referred to as an organic EL element) can be used, for example. Note that the light-emitting element  572  is not limited to an organic EL element; an inorganic EL element including an inorganic material may be used. 
     Note that a high power supply potential VDD is supplied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is supplied to the other. 
     For example, in the display device including the pixel circuit  501  in  FIG. 27C , the pixel circuits  501  are sequentially selected row by row by the gate driver  504   a  illustrated in  FIG. 27A , whereby the transistors  552  are turned on and a data signal is written. 
     When the transistors  552  are turned off, the pixel circuits  501  in which the data has been written are brought into a holding state. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor  554  is controlled in accordance with the potential of the written data signal. The light-emitting element  572  emits light with luminance corresponding to the amount of flowing current. This operation is sequentially performed row by row; thus, an image is displayed. 
     At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate. 
     Embodiment 8 
     In this embodiment, a display module and electronic devices, each of which includes a semiconductor device of one embodiment of the present invention, are described with reference to  FIG. 28 ,  FIGS. 29A to 29E , and  FIGS. 30A to 30G . 
     &lt;8-1. Display Module&gt; 
     In a display module  7000  illustrated in  FIG. 28 , a touch panel  7004  connected to an FPC  7003 , a display panel  7006  connected to an FPC  7005 , a backlight  7007 , a frame  7009 , a printed board  7010 , and a battery  7011  are provided between an upper cover  7001  and a lower cover  7002 . 
     The semiconductor device of one embodiment of the present invention can be used for the display panel  7006 , for example. 
     The shapes and sizes of the upper cover  7001  and the lower cover  7002  can be changed as appropriate in accordance with the sizes of the touch panel  7004  and the display panel  7006 . 
     The touch panel  7004  can be a resistive touch panel or a capacitive touch panel and overlap with the display panel  7006 . Alternatively, a counter substrate (sealing substrate) of the display panel  7006  can have a touch panel function. Alternatively, a photosensor may be provided in each pixel of the display panel  7006  to form an optical touch panel. 
     The backlight  7007  includes a light source  7008 . One embodiment of the present invention is not limited to the structure in  FIG. 28 , in which the light source  7008  is provided over the backlight  7007 . For example, a structure in which the light source  7008  is provided at an end portion of the backlight  7007  and a light diffusion plate is further provided may be employed. Note that the backlight  7007  needs not be provided in the case where a self-luminous element such as an organic EL element is used or in the case where a reflective panel or the like is employed. 
     The frame  7009  protects the display panel  7006  and functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board  7010 . The frame  7009  may also function as a radiator plate. 
     The printed board  7010  includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or the separate battery  7011  may be used. The battery  7011  can be omitted in the case where a commercial power source is used. 
     The display module  7000  may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet. 
     &lt;8-2. Electronic Device  1 &gt; 
     Next,  FIGS. 29A to 29E  illustrate examples of an electronic device. 
       FIG. 29A  is an external view of a camera  8000  to which a finder  8100  is attached. 
     The camera  8000  includes a housing  8001 , a display portion  8002 , an operation button  8003 , a shutter button  8004 , and the like. Furthermore, a detachable lens  8006  is attached to the camera  8000 . 
     Although the lens  8006  of the camera  8000  here is detachable from the housing  8001  for replacement, the lens  8006  may be included in the housing  8001 . 
     Images can be taken with the camera  8000  at the press of the shutter button  8004 . In addition, images can be taken at the touch of the display portion  8002  which serves as a touch panel. 
     The housing  8001  of the camera  8000  includes a mount including an electrode, so that the finder  8100 , a stroboscope, or the like can be connected to the housing  8001 . 
     The finder  8100  includes a housing  8101 , a display portion  8102 , a button  8103 , and the like. 
     The housing  8101  includes a mount for engagement with the mount of the camera  8000  so that the finder  8100  can be connected to the camera  8000 . The mount includes an electrode, and an image or the like received from the camera  8000  through the electrode can be displayed on the display portion  8102 . 
     The button  8103  functions as a power button. With the button  8103 , the display portion  8102  can be turned on and off. 
     The display device of one embodiment of the present invention can be used in the display portion  8002  of the camera  8000  and the display portion  8102  of the finder  8100 . 
     Although the camera  8000  and the finder  8100  are separate and detachable electronic devices in  FIG. 29A , the housing  8001  of the camera  8000  may include a finder having a display device. 
       FIG. 29B  is an external view of a head-mounted display  8200 . 
     The head-mounted display  8200  includes a mounting portion  8201 , a lens  8202 , a main body  8203 , a display portion  8204 , a cable  8205 , and the like. The mounting portion  8201  includes a battery  8206 . 
     Power is supplied from the battery  8206  to the main body  8203  through the cable  8205 . The main body  8203  includes a wireless receiver or the like to receive video data, such as image data, and display it on the display portion  8204 . The movement of the eyeball and the eyelid of a user is captured by a camera in the main body  8203  and then coordinates of the points the user looks at are calculated using the captured data to utilize the eye of the user as an input means. 
     The mounting portion  8201  may include a plurality of electrodes so as to be in contact with the user. The main body  8203  may be configured to sense current flowing through the electrodes in accordance with the movement of the user&#39;s eyeball to recognize the direction of his or her eyes. The main body  8203  may be configured to sense current flowing through the electrodes to monitor the user&#39;s pulse. The mounting portion  8201  may include sensors, such as a temperature sensor, a pressure sensor, or an acceleration sensor so that the user&#39;s biological information can be displayed on the display portion  8204 . The main body  8203  may be configured to sense the movement of the user&#39;s head or the like to move an image displayed on the display portion  8204  in synchronization with the movement of the user&#39;s head or the like. 
     The display device of one embodiment of the present invention can be used in the display portion  8204 . 
       FIGS. 29C to 29E  are external views of a head-mounted display  8300 . The head-mounted display  8300  includes a housing  8301 , a display portion  8302 , a band-shaped object  8304  for fixing the display, and a pair of lenses  8305 . 
     A user can see display on the display portion  8302  through the lenses  8305 . It is favorable that the display portion  8302  be curved. When the display portion  8302  is curved, a user can feel high realistic sensation of images. Although the structure described in this embodiment as an example has one display portion  8302 , the number of display portions  8302  provided is not limited to one. For example, two display portions  8302  may be provided, in which case one display portion is provided for one corresponding user&#39;s eye, so that three-dimensional display using parallax or the like is possible. 
     The display device of one embodiment of the present invention can be used in the display portion  8302 . The display device including the semiconductor device of one embodiment of the present invention has an extremely high resolution; thus, even when an image is magnified using the lenses  8305  as illustrated in  FIG. 29E , the user does not perceive pixels, and thus a more realistic image can be displayed. 
     &lt;8-3. Electronic Device  2 &gt; 
     Next,  FIGS. 30A to 30G  illustrate examples of electronic devices that are different from those illustrated in  FIGS. 29A to 29E . 
     Electronic devices illustrated in  FIGS. 30A to 30G  include a housing  9000 , a display portion  9001 , a speaker  9003 , an operation key  9005  (including a power switch or an operation switch), a connection terminal  9006 , a sensor  9007  (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared ray), a microphone  9008 , and the like. 
     The electronic devices illustrated in  FIGS. 30A to 30G  can have a variety of functions, for example, a function of displaying a variety of data (e.g., a still image, a moving image, and a text image) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of controlling a process with a variety of software (programs), a wireless communication function, a function of being connected to a variety of computer networks with a wireless communication function, a function of transmitting and receiving a variety of data with a wireless communication function, and a function of reading a program or data stored in a memory medium and displaying the program or data on the display portion. Note that functions of the electronic devices in  FIGS. 30A to 30G  are not limited thereto, and the electronic devices can have a variety of functions. Although not illustrated in  FIGS. 30A to 30G , the electronic devices may include a plurality of display portions. The electronic devices may include a camera or the like and have a function of taking a still image, a function of taking a moving image, a function of storing the taken image in a memory medium (an external memory medium or a memory medium incorporated in the camera), a function of displaying the taken image on the display portion, or the like. 
     The electronic devices illustrated in  FIGS. 30A to 30G  are described in detail below. 
       FIG. 30A  is a perspective view illustrating a television device  9100 . The television device  9100  can include the display portion  9001  having a large screen size of, for example, 50 inches or more, or 100 inches or more. 
       FIG. 30B  is a perspective view of a portable information terminal  9101 . The portable information terminal  9101  functions as, for example, one or more of a telephone set, a notebook, and an information browsing system. Specifically, the portable information terminal can be used as a smartphone. Note that the portable information terminal  9101  may include the speaker  9003 , the connection terminal  9006 , the sensor  9007 , or the like. The portable information terminal  9101  can display characters and image information on its plurality of surfaces. For example, three operation buttons  9050  (also referred to as operation icons, or simply, icons) can be displayed on one surface of the display portion  9001 . Furthermore, information  9051  indicated by dashed rectangles can be displayed on another surface of the display portion  9001 . Examples of the information  9051  include display indicating reception of an incoming email, social networking service (SNS) message, call, and the like; the title and sender of an email and SNS message; the date; the time; remaining battery; and the reception strength of an antenna. Instead of the information  9051 , the operation buttons  9050  or the like may be displayed on the position where the information  9051  is displayed. 
       FIG. 30C  is a perspective view of a portable information terminal  9102 . The portable information terminal  9102  has a function of displaying information on three or more surfaces of the display portion  9001 . Here, information  9052 , information  9053 , and information  9054  are displayed on different surfaces. For example, a user of the portable information terminal  9102  can see the display (here, the information  9053 ) with the portable information terminal  9102  put in a breast pocket of his/her clothes. Specifically, a caller&#39;s phone number, name, or the like of an incoming call is displayed in a position that can be seen from above the portable information terminal  9102 . Thus, the user can see the display without taking out the portable information terminal  9102  from the pocket and decide whether to answer the call. 
       FIG. 30D  is a perspective view of a watch-type portable information terminal  9200 . The portable information terminal  9200  is capable of executing a variety of applications such as mobile phone calls, e-mailing, viewing and editing texts, music reproduction, Internet communication, and computer games. The display surface of the display portion  9001  is curved, and images can be displayed on the curved display surface. The portable information terminal  9200  can employ near field communication that is a communication method based on an existing communication standard. In that case, for example, mutual communication between the portable information terminal  9200  and a headset capable of wireless communication can be performed, and thus hands-free calling is possible. The portable information terminal  9200  includes the connection terminal  9006 , and data can be directly transmitted to and received from another information terminal via a connector. Power charging through the connection terminal  9006  is possible. Note that the charging operation may be performed by wireless power feeding without using the connection terminal  9006 . 
       FIGS. 30E, 30F, and 30G  are perspective views of a foldable portable information terminal  9201  that is opened, that is shifted from the opened state to the folded state or from the folded state to the opened state, and that is folded, respectively. The portable information terminal  9201  is highly portable when folded. When the portable information terminal  9201  is opened, a seamless large display region is highly browsable. The display portion  9001  of the portable information terminal  9201  is supported by three housings  9000  joined together by hinges  9055 . By folding the portable information terminal  9201  at a connection portion between two housings  9000  with the hinges  9055 , the portable information terminal  9201  can be reversibly changed in shape from the opened state to the folded state. For example, the portable information terminal  9201  can be bent with a radius of curvature of greater than or equal to 1 mm and less than or equal to 150 mm. 
     The electronic devices described in this embodiment each include the display portion for displaying some sort of data. Note that the semiconductor device of one embodiment of the present invention can also be used for an electronic device that does not include a display portion. 
     At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate. 
     This application is based on Japanese Patent Application Serial No. 2016-120802 filed with Japan Patent Office on Jun. 17, 2016, the entire contents of which are hereby incorporated by reference.