Patent Publication Number: US-5254497-A

Title: Method of eliminating degradation of a multilayer metallurgy/insulator structure of a VLSI integrated circuit

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     This invention relates in general to semiconductor device processing, and more particularly to a method of fabricating a multilayer metallurgy/insulator structure of a very large scale integrated (VLSI) circuit. 
     (2) Description of the Prior Art 
     Degradation of polysilicon load resistance in a double polysilicon interconnection metallurgy system, particularly in fabricating double polysilicon 4 transistor static random access memory devices. The fabrication of such devices depend on the use of multilayer metallurgy systems which contain a sandwich insulation composite layer of silicon oxide, spin-on-glass and silicon oxide, and the process steps for forming such silicon layers that utilize plasma enhanced oxidation. 
     Spin-on-glass is a very desirable material to be used in such methods and resulting structures to overcome the irregularity or substantially nonplanar surfaces of the first level of metallurgy. This irregular or nonplanar surface problem causes loss of resolution in the lithographic masking processing. The problem increases with higher level of metallurgy. 
     These problems have been recognized in the prior art and attempts have been made to overcome these topographical problems principally in the one micron and above feature dimensions. These techniques can be generally grouped in categories of planarization either involving etchback or nonetchback techniques. 
     In the case of etchback processing, typically a coating is formed on top of the irregular surfaces by an means of spin-on-glass or thermoplastic deposition techniques which produces a planar surface. A plasma, reactive or chemical wet etching is used uniformly across the planar surface to remove the deposited layer and the tops of the irregular humps or the like to produce a planar surface at the desired depth. 
     In the early nonetchback processing, the usual technique was to heat the dielectric layer, which was typically glass until the flow of the glass reduced the irregularities. 
     More recently the nonetchback planarization using a spin-on-glass sandwich has found interest at the about one micron feature dimension integrated circuit processing. This technique is described in U.S. Pat. No. 5,003,062 to Daniel L. Yen and assigned to the same assignee of the present invention. In this patent a sandwich dielectric structure is formed and used in one micron or less processing of spin-on-glass sandwiched between two silicon oxide layers. The spin-on-glass layer functions as the means for planarizing the irregularities. 
     In the Yen U.S. Pat. No. 5,003,062, spin-on-glass that has been cured still remains in the final product. However, workers in the field such as A. Malazgirt et al U.S. Pat. No. 4,986,878 has found that spin-on-glass even after curing by conventional techniques causes reliability problems, such as the presence therein of mobile ions, e.g. sodium to the point that they use the spin-on-glass in an etchback process for planarization and then completely remove the remaining material. Then a conventional insulator is deposited. 
     In the paper entitled &#34;FIELD INVERSION IN CMOS DOUBLE METAL CIRCUITS DUE TO CARBON BASED SOGS&#34; by D. Pramanik et al, a further discussion of the reliability problems in the use of spin-on-glass (SOG) is considered. They conclude that the use of SOG must be heavily restricted to overcome field inversion, that is a positive charge build up between the SOG layer and the other dielectric layers. They state that SOG must be purely inorganic phosphosilicate glass, since organic based SOG emanates hydrogen. Further, the require that etchback be used to reduce the thickness of the SOG to the bare minimum in the final product. Still further, they require that the layer covering the SOG be formed of a material that does not liberate hydrogen, such as silicon dioxide. Normal processes for depositing silicon nitride or oxynitride do liberate hydrogen. 
     In the U.S. Pat. application Ser. No. 07/743,779 Aug. 12, 1991 by L. S. Tsai et al entitled &#34;Method and Resulting Device for Field Inversion Free Multiple Layer Metallurgy VLSI Processing&#34; it is proposed that the inversion problem can be overcome by the incorporation of a specific dielectric between the Via 1 dielectric layer and the spin-on-glass (SOG) layer. This is a successful technique. 
     In another U.S. Pat. application Ser. No. 07/825,371 dated Jan. 24, 1992 by K. M. Lin et al entitled &#34;A Nitrogen Treatment to Prevent Field Device Leakage in VLSI Processing&#34; it is proposed that the inversion problem can be overcome by use of a nitrogen treatment of the first silicon oxide layer. This has been successful. 
     Accordingly it is a principal object of the present invention to provide a novel process for eliminating or substantially eliminating degradation of polysilicon metallurgy used in semiconductor devices. 
     Another object of the present invention is to provide a novel process for dispelling positive electrical charges in the multilayer metallurgy structures of VLSI circuits that would otherwise degrade the electrical characteristics of such devices without changing the established processes. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, and the above objects of the invention, there is provided a novel process wherein degradation of the multilayer metallurgy/insulator structure in a semiconductor device can be eliminated without changing the processing steps, but by adding a step of illuminating the device with ultra violet radiation. 
     A method is described for forming multiple metal, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion. A semiconductor substrate is provide having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within the semiconductor substrate electrically separating certain of these source/drain regions from one another. A first passivation layer is formed over the surfaces of the patterns. The multilayer metallurgy is formed thereover by opening a pattern of openings through the passivation layer to at least some of the source/drain regions. A first metallurgy layer is deposited and patterned in contact with the pattern of openings. A first silicon oxide via dielectric layer is formed over the pattern of first metallurgy layer. A spin-on-glass layer is formed over the via dielectric layer and the layer is cured. A second silicon oxide via dielectric layer is formed over the spin-on-glass layer. A pattern of openings is formed in the second via layer, the spin-on-glass layer, and the first via layer. A second metallurgy layer is deposited and patterned in contact with the pattern of openings to make electrical contact with the first metallurgy layer. A second passivating dielectric layer is formed over the second metallurgy layer. Finally, the structure is illuminated with ultra violet radiation for a time sufficient to neutralize the positive charges in the multilevel metallurgy structure wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a vertical cross sectional view, in broken section and in greatly enlarged scale, of a typical semiconductor device structure, which is likely to experience multilayer metallurgy/insulator structure degradation. 
     FIG. 2 is also a vertical cross sectional view of a semiconductor device provided with a polysilicon resistor, which illustrates the method of our invention for eliminating degradation. 
     FIG. 3 shows the final step in our process for making an inversion free multilayer metallurgy/insulating structure. 
     FIG. 4 is a cross-sectional schematic drawing of a double polysilicon, double metal static RAM device. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the aforedescribed figures of the drawings, and FIG. 1 in particular, there is shown an illustration of a partially completed, single field effect transistor (FET) having a polysilicon resistor structure. The first series of steps involve the formation of the dielectric isolation regions 8 for isolating semiconductor surface regions from other such regions in the semiconductor substrate 10. The semiconductor substrate is preferably composed of silicon having a (100) crystallographic orientation. In an effort to simplify the description and the drawings the dielectric isolation between devices has been only partially shown and will not be described in detail, because they are conventional. For example, one method is described by E. Kooi in his U.S. Pat. No. 3,970,486 wherein certain selected surface portions of a silicon semiconductor substrate is masked against oxidation, and then the exposed unmasked surface is oxidized to grow a thermal oxide which in effect sinks into the silicon surface at the unmasked areas. The masked silicon remains as a mesa surrounded by the sunken silicon dioxide or Field OXide pattern, FOX 8. Then semiconductor devices can be provided in the silicon mesas according to the following processes. 
     The surface of the silicon substrate 10 is thermally oxidized to form the desired gate oxide 11 thickness. The preferred thickness is between about 70 to 200 Angstroms. The polysilicon layer 12 is blanket deposited by LPCVD (Low Pressure Chemical Vapor Deposition) method. The preferred thickness of the polysilicon layer 12 is between about 3000 to 4400 Angstroms. The polysilicon layer 12 is ion implanted with phosphorous or arsenic ions by conventional methods and dosages to render the polysilicon layer conductive or doped with phosphorus oxychloride at a temperature about 900° C. The surface of the layer is either thermally oxidized or a chemical vapor deposition process to form silicon oxide layer 13. The layers 11, 12 and 13 are patterned by conventional lithography and anisotropic etching techniques as are conventional in the art to provide a desired pattern of gate electrodes and structure on the FOX 8 surfaces or elsewhere as seen in FIG. 1. 
     The source/drain structure of the MOS FET may now be formed by the following steps. The FIG. 1 illustrates the formation of N channel FET integrated circuit device wherein the substrate or well is doped as P-. However, it is well understood by those skilled in the art that a P channel FET integrated circuit device could also be formed by simply substituting opposite polarities to those given for the N channel embodiment. Also, a CMOS FET could in a similar way be formed by making both N channel and P channel devices upon the same substrate. 
     FIG. 1, for example shows the device regions, typically source/drain regions 14 in the substrate as of N+ dopants. Lithographic masks may be required to protect the areas not to be subjected to that particular N ion implantation. The formation of the lithographic masks are done by conventional lithography and etching techniques. Although not illustrated for simplicity sake, lightly doped drain structures can be formed using the conventional and well known techniques. Sidewall spacer structures 5 and N-regions which are used in this process are shown in the drawings. 
     The N+ source/drain ion implantation uses typically Arsenic, As75 with a dose of between about 1 E 15 to 6 E 15 atoms/cm. 2  and energy of between about 70 to 100 Kev. to complete the source/drain regions 14 of the N channel MOS FET integrated circuits device as seen in the FIGS. 1 and 4. 
     After the device formation, the surface silicon oxide is removed from the source/drain regions and a first polysilicon layer 50 is deposited and patterned as seen in FIG. 4. A silicon oxide layer 13 is deposited as an insulating layer. This layer may be formed by any of the known techniques such as low pressure CVD, atmospheric pressure CVD, plasma enhance CVD or thermally grown. Then a contact layer is formed by opening by dry etching for the connections of second polysilicon layer resistor layer, source/drain regions 14 and first polysilicon layer 50. The second polysilicon layer is then deposited in a low pressure CVD process with temperature of between about 600° to 630° C. The thickness of this layer is between about 1000 to 2500 Angstroms. This layer is then patterned and isotropically etched for stringer sidewalls. The second polysilicon layer is then adjusted by ion implantation at 1 E 13 to 1 E 14 or kept intrinsic to the desired resistance value. The ion implantation can be done before or after the patterning step. A masking layer for interconnection is used to block the lightly doped or intrinsic region 17 of the second polysilicon. The rest of the second polysilicon layer 15 is heavily doped by ion implantation at 1 E 15 to 6 E 15. 
     A passivation or insulating layer 16 is now formed over the surfaces of the patterns. This layer may be composed of multilayers such as a thin layer of silicon oxide and a much thicker layer of borophophosilicate glass, phosphosilicate glass or similar insulating layer. The operational thicknesses of these layers are between about 800 to 1400 Angstroms for the oxide layer and between about 2000 to 8000 or more Angstroms for the glasseous layer. These layers are typically deposited by chemical vapor deposition in low pressure or atmospheric pressure, or in a plasma enhanced reactive chamber. 
     As seen in the FIGS., the contact windows are openings are formed through the insulating structure to the source/drain regions 14. Conventional lithography and etching techniques are used to form this pattern of openings. 
     The first metallurgy contact layer 20 is now deposited over the surface of the structure and within the pattern of contact openings to the source/drain regions 14 and to the resistor 15, 17 contact regions. The metallurgy is preferably Aluminum/silicon/copper having a thickness of between about 5000 to 10,000 Angstroms. However, other possible metallurgy include polysilicon, titanium, titanium/tungsten, titanium nitride or the like. The preferred method of depositing this metallurgy is by sputtering under the processing conditions of about 2 to 8  kilowatts of power, 25° to 450° C., and 0.1 to 2 Pascal. However, other possible methods of deposition include chemical vapor deposition. The metallurgy is now patterned into the desired conductive lines by conventional lithography and etching techniques to form the pattern of metal layer 20 in FIG. 1. 
     The important planarization and dielectric layered structure between the first metallurgy layer pattern 20 and the second metallurgy layer pattern 36 which is shown in FIG. 2. 
     The usual first dielectric silicon oxide layer 22 of the spin-on-glass sandwich planarization structure is now formed above the first metallurgy pattern 20. It is typically in the range of between about 1000 to 4000 angstroms in thickness. This layer is deposited either by the silane method or by the TEOS method. The following is the silane method process conditions of pressure of about 2.95 Torr, power of about 180 watts, temperature of about 400° C., spacing of about 270 mils, silane of about 32 ccm, and dinitrogen oxide (N 2  O) of 900 ccm. However, TEOS method is preferred to give the best step coverage over the surfaces being deposited thereon. 
     The spin-on-glass materials and how they are processed are critical to the success of the process for planarization of integrated circuits as described in the above cited in the Daniel L. Yen Patent. The most useful materials are silicates--Si (OH) 4  and siloxanes --(RO)nSi(OH) 4-n . These types of materials are generally known and available. Examples of the silicate type is OCD Type 2 made by Tokyo Okha Corp. and siloxane type is OCD Type 6 made by Tokyo Okha Corp. It is possible to use multiple coating of spin-on-glass. Each spin-on-glass coating is less than about 0.3 micrometers and preferably between about 0.08 and 0.2 micrometers. The more coatings that are used, the better the planarity. The material to be applied is thoroughly mixed in a suitable solvent which is usually a combination of a high boiling point solvent and a low boiling point solvent. 
     The preferred low boiling point solvents are methanol, ethanol, and propanol. The middle boiling point solvents are buthanol, penthanol, hexanol and methyl cellosolve. The high boiling point solvents are butyl cellosolve, propylene glycol, diethylene glycol and Carbindol. Other potential vehicles or solvents are NMP, HMPA, N.N-dimethylacetoamide, acetyl acetone, and malonic acid diethylester and the like. 
     The spin-on-glass material suspended in the vehicle or solvent is deposited onto the semiconductor wafer surface and uniformly spread thereover by the action of spinning the wafer. The material fills the indentations in the integrated circuit wafer surface, that is planarization. Most of the vehicle or solvent is driven off by a low temperature baking step. At this point, the critical vacuum degassing step is accomplished by subjecting the wafer to a vacuum of less than about 100 mtorr and 350 degrees C. This last step removes chemical materials which could during latter processing cause cracking and corrosion of the next level conductor material. Other coatings of the spin-on-glass material are applied, baked and vacuum degassed until the desired spin-on-glass (SOG) layer 34 is formed. 
     The final step in the making of the spin-on-glass layer is curing. Curing is a high temperature heating step to cause the breakdown of the silicate or siloxane material to a silicon dioxide like cross linked material. Water in the form of steam is the major reaction product of this reaction. The silicate spin-on-glass is cured at about 390° to 420° C. and siloxane spin-on-glass is cured at about 450° C. in nitrogen. The spin-on-glass (SOG) layer 34 is now complete. 
     The second via dielectric layer 26 is now formed on top of the SOG layer 24. This layer is formed in a similar manner as was the first via layer 22. This layer can be deposited by either the TEOS or the silane method. The preferred thickness of this layer is between about 2000 to 6000 Angstroms and the preferred material is silicon oxide. 
     Openings are now made through the second via layer 26, the SOG layer 34, barrier layer 23, the first via layer 22 to the first metallurgy layer 20. These openings are made using conventional lithography and with the preferred etching conditions at a pressure of 800 mtorrs, power of 750 watts, gap of 0.8 cm., argon flow of 400 ccm, carbon tetrafluoride flow of 23 ccm, and CHF 3  flow of 12 ccm. 
     The second metallurgy contact layer 36 is now deposited over the surface of the structure and within the pattern of contact openings to the first metallurgy layer 20. The metallurgy is preferably aluminum/silicon/copper having a thickness of between about 5000 to 11,000 Angstroms. However, other possible metallurgy include polysilicon, titanium, titanium/tungsten, titanium nitride or the like. The preferred method of depositing this metallurgy is by sputtering under the same processing conditions as given for the first metallurgy layer 20. However, other possible methods of deposition include chemical vapor deposition as is known in the art. The metallurgy is now patterned into the desired conductive lines by conventional lithography and etching techniques to form the pattern of metal layer 36 in FIG. 2. Plasma enhanced silicon oxide layer 40 is now deposited over the second metallurgy 36. 
     The critical process steps to overcome inversion caused degradation in the multilayer metallurgy and insulator layers. The structure is illuminated, as shown in FIG. 2 by ultra violet light. The exposure involves the use of a grid lamps (mercury lamp) having a typical peak intensity of about 18500 milli watts/ square centimeters. The distance of the light to the wafer is about 10 cm. The operating conditions needed to remove the positive charge that degrades the integrated circuit structure is a dosage of between about 5 watt-seconds/square cm. to 30 watt-seconds/square cm.; a time of between about 5 to 30 minutes; and using a ultra violet wavelength of about 254 nanometers. 
     The integrated circuit may now be completed with higher levels of metallurgy and passivation as is known to those skilled in the art or similar additional multilevel metallurgy layers as described above are repeated to make triple or higher metallurgy levels on the integrated circuit structure. 
     FIG. 3 shows the completion of one structure wherein a second passivation layer 42, such as plasma enhanced silicon nitride layer 42 is formed over layer 40. Openings are made in layers 40, 42 to the second metallurgy layer 36 using conventional lithography and etching techniques. Metallurgy contacts 44 are made to the metallurgy 36. A gold bond or the like 46 is the final contact to off chip circuits as is known in the art. 
     FIG. 4 shows a schematic cross-sectional representation of a double polysilicon double metal static random access memory device made by the process of the present invention. It features a resistor having its heavily doped regions 15 connected to a source/drain region 14 and to a polysilicon layer 50 which also contacts the source/drain region 14. The intrinsic or lightly doped polysilicon resistor portion 17 is also in contact with the region 15. The illumination of ultra violet light is done to remove the positive charge problem in layer 22 before the passivation layer 42 is formed. Alternatively, where the passivation layer is highly transparent, such as silicon nitride or oxynitride the illumination can be done after the passivation layer has been deposited. 
     The following Examples are given to show the important features of the invention and to aid in the understanding thereof and variations may be made by one skilled in the art without departing from the spirit and scope of the invention. 
     EXAMPLES 
     The Examples were made using MOS field effect transistor test devices with a polysilicon resistor of the type shown in the FIGS. 1-3. The resistance load values given in the following TABLE I is in giga ohm per square. The UV light exposure used a grip mercury lamp having a wattage of 18500 milli watts/square cm. and a wavelength of 254 nanometers. The exposure was for 15 minutes in TABLE I. 
     
                       TABLE I                                                     
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                     @ Metal II  @ Metal II                               
Example @ Metal I    (w/o UV)    (with UV)                                
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1       368.2 + 79.6 1.85 + 1.17 132.0 + 40.9                             
2        412.6 + 105.2                                                    
                     1.241 + 0.623                                        
                                 160.8 + 86.3                             
3       301.1 + 90.2 1.848 + 2.963                                        
                                 592.6 + 149.0                            
4       499.8 + 95.1 --          578.4 + 112.7                            
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     It is seen that the resistance measured after the polysilicon resistor measured after the passivation oxide layer 40 (@ Metal II without UV exposure) is degraded substantially from the resistance measured after the Metal I was deposited. The same resistance measurement was substantially returned to the normal desired values after the 15 minute UV exposure of the structure as seen in the last column of TABLE I. 
     The Example 2 wafer was exposed to UV radiation for 15; 20; 25 and 35 minutes and under the conditions above. The resistance was measured as given in TABLE II. 
     
                       TABLE II                                                    
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       15 min. 20 min.   25 min.   35 min.                                
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Example 2                                                                 
         160.8 +   180.4 +   191.2 + 181.5 +                              
         86.3      43.2      19.1    42.8                                 
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     It is seen from TABLE II that after a certain time the resistance saturates and further exposure to UV is of little consequence. That UV exposure of saturation is about 20 minutes. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art, that various changes in form and details may be made without departing from the spirit and scope of the invention.