Patent Publication Number: US-6989286-B2

Title: Method of manufacturing optical devices and related improvements

Description:
FIELD OF INVENTION 
     This invention relates to a method of manufacturing of optical devices, and in particular, though not exclusively, to manufacturing integrated optical devices or optoelectronic devices, for example, semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, and the like. The invention further relates to Optoelectronic Integrated Circuits (OEICs) and Photonic Integrated Circuits (PICs) including such devices. 
     BACKGROUND OF INVENTION 
     Quantum Well Intermixing (QWI) is a process which has been reported as providing a possible route to monolithic optoelectronic integration. QWI may be performed in III–V semiconductor materials, eg Aluminium Gallium Arsenide (AlGaAs) and Indium Gallium Arsenide Phosphide (InGaAsP), which may be grown on binary substrates, eg Gallium Arsenide (GaAs) or Indium Phosphide (InP). QWI alters the band-gap of an as-grown structure through interdiffusion of elements of a Quantum Well (QW) and associated barriers to produce an alloy of the constituent components. The alloy has a band-gap which is larger than that of the as-grown QW. Any optical radiation (light) generated within the QW where no QWI has taken place can therefore pass through a QWI or “intermixed” region of alloy which is effectively transparent to the said optical radiation. 
     Various QWI techniques have been reported in the literature. For example, QWI can be performed by high temperature diffusion of elements such as Zinc into a semiconductor material including a QW. 
     QWI can also be performed by implantation of elements such as silicon into a QW semiconductor material. In such a technique the implantation element introduces point defects in the structure of the semiconductor material which are moved through the semiconductor material inducing intermixing in the QW structure by a high temperature annealing step. 
     Such QWI techniques have been reported in “Applications of Neutral Impurity Disordering in Fabricating Low-Loss Optical Waveguides and Integrated Waveguide Devices”, Marsh et al, Optical and Quantum Electronics 23, 1991, s941–s957, the content of which is incorporated herein by reference. 
     A problem exists with such techniques in that although the QWI will alter (increase) the band-gap of the semiconductor material post-growth, residual diffusion or implantation dopants can introduce large losses due to the free carrier absorption coefficient of these dopant elements. 
     A further reported QWI technique providing intermixing, is Impurity Free Vacancy Diffusion (IFVD). When performing IFVD the top cap layer of the III–V semiconductor structure is typically GaAs or Indium Gallium Arsenide (InGaAs). Upon the top layer is deposited a silica (SiO 2 ) film. Subsequent rapid thermal annealing of the semiconductor material causes bonds to break within the semiconductor alloy and Gallium ions or atoms—which are susceptible to silica (SiO 2 )—to dissolve into the silica so as to leave vacancies in the cap layer. The vacancies then diffuse through the semiconductor structure inducing layer intermixing, eg in the QW structure. 
     IFVD has been reported in “Quantitative Model for the Kinetics of Compositional Intermixing in GaAs—AlGaAs Quantum—Confined Heterostructures”, by Helmy et al, IEEE Journal of Selected Topics in Quantum Electronics, Vol 4, No 4, July/August 1998, pp 653–660, the content of which is incorporated herein by reference. 
     Reported QWI, and particularly IFVD methods, suffer from a number of disadvantages, eg the temperature at which Gallium out diffuses from the semiconductor material to the silica (SiO 2 ) film. 
     It is an object of at least one aspect of the present invention to obviate or at least mitigate at least one of the aforementioned disadvantages/problems in the prior art. 
     It is also an object of at least one aspect of the present invention to provide an improved method of manufacturing an optical device using an improved QWI process. 
     SUMMARY OF INVENTION 
     According to a first aspect of the present invention, there is provided a method of manufacturing an optical device, a device body portion from which the device is to be made including a Quantum Well (QW) structure, the method including the step of:
         depositing a dielectric layer on at least part of a surface of the device body portion so as to introduce structural defects at least into a portion of the device body portion adjacent the dielectric layer.       

     According to a further aspect, the present invention provides a method of manufacturing an optical device, a device body portion from which the device is to be made including a Quantum Well (QW) structure, the method including the step of performing a plasma etch on at least part of a surface of the device body portion so as to introduce structural defects at least into a portion of the device body portion adjacent the surface layer, subsequent to which the etched surface is encapsulated with a dielectric layer. 
     The structural defects may include “point” defects. 
     Preferably, and advantageously, the plasma etch and dielectric layer deposition are performed by sputtering. 
     In a preferred embodiment the dielectric layer is deposited by sputtering using a diode sputterer. 
     The dielectric layer may beneficially substantially comprise silica (SiO 2 ), or may comprise another dielectric material such as aluminium oxide (Al 2 O 3 ). 
     Preferably, the sputterer includes a chamber which may be substantially filled with an inert gas such as argon, preferably at a pressure of around 2 microns of Hg, or a mixture of argon and oxygen, eg in the proportion 90% / 10%. 
     The step of depositing the dielectric layer may comprise part of a Quantum Well Intermixing (QWI) process used in manufacture of the device. 
     The QWI process may comprise Impurity-Free Vacancy Disordering (IFVD). 
     Preferably, the method of manufacture also includes the subsequent step of annealing the device body portion including the dielectric layer at an elevated temperature. 
     It has been surprisingly found that by etching the semiconductor surface prior to depositing the dielectric layer used in QWI techniques such as IFVD by sputtering, damage induced point defects appear to be introduced into the portion of the device body portion adjacent the dielectric cap; the portion may, for example, comprise a top or “capping” layer. It is believed that the damage arises due to breakage of bonds in the capping layer before annealing, eg the application of thermal energy by rapid thermal annealing, thereby expediting transfer of Gallium and/or Indium from the capping layer into the dielectric layer. 
     Preferably the method of manufacture also includes the preceding steps of: providing a substrate; growing on the substrate a first optical cladding layer, a core guiding layer including a Quantum Well (QW) structure, and a second optical cladding layer. 
     The first optical cladding layer, core guiding layer, and second optical cladding layer may be grown by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition (MOCVD). 
     In a first embodiment the method may also include the step of defining a pattern in photoresist on a surface of the device body portion, performing the etch and subsequent dielectric layer deposition and lifting off the photoresist so as to provide the dielectric layer on the said at least part of the surface of the device body portion. 
     In said first embodiment, the method may also include the step of depositing a further dielectric layer on the surface of the device body and on a surface of the dielectric layer prior to annealing, preferably without a plasma etch stage, by a technique other than sputtering, eg Plasma Enhanced Chemical Vapour Deposition (PECVD). 
     In a second embodiment the method may include the steps of depositing the further dielectric layer and then performing the substrate etch and depositing the dielectric layer. 
     In said first and second embodiments, the dielectric layer which encapsulates the previously etched layer may comprise an intermixing cap; the further dielectric layer may comprise an intermixing suppressing cap. 
     The plasma etch may typically be performed for a duration between 0.5 and 10 minutes and the thickness of the encapsulating dielectric layer may be between 10 nanometers to a few hundred nanometers. 
     The annealing step may occur at a temperature of around 650° C. to 850° C. for around 0.5 to 5 minutes, and in one embodiment at substantially 800° C. for around 1 minute. 
     According to a second aspect of the present invention there is provided a method of manufacturing an optical device, a device body portion from which the device is to be made including a Quantum Well (QW) structure, the method including the step of depositing a dielectric layer on at least part of a surface of the device body portion by sputtering. 
     According to a third aspect of the present invention there is provided an optical device fabricated from a method according to either of the first or second aspects of the present invention. 
     The optical device may be an integrated optical device or an optoelectronic device. 
     The device body portion may be fabricated in a III–V semiconductor materials system. 
     In one embodiment the III–V semiconductor materials system may be a Gallium Arsenide (GaAs) based system, and may therefore operate at one or more wavelengths in the range 600 to 1300 nm. Alternatively, in a preferred embodiment the III–V semiconductor materials system may be an Indium Phosphide based system, and may therefore operate at one or more wavelength in the range 1200 to 1700 nm. The device body portion may be made at least partly from Aluminium Gallium Arsenide (AlGaAs), Indium Gallium Arsenide (InGaAs), Indium Gallium Arsenide Phosphide, (InGaAsP), Indium Gallium Aluminium Arsenide (InGaAlAs) and/or Indium Gallium Aluminium Phosphide (InGaAlP). 
     The device body portion may comprise a substrate upon which are provided a first optical cladding layer, a core guiding layer, and a second optical cladding layer. 
     Preferably the Quantum Well (QW) structure is provided within the core guiding layer. 
     The core guiding layer, as grown, may have a smaller band-gap and higher refractive index than the first and second optical cladding layers. 
     According to a fourth aspect of the present invention, there is provided an optical integrated circuit, optoelectronic integrated circuit (OEIC), or photonic integrated circuit (PIC) including at least one optical device according to the third aspect of the present invention. 
     According to a fifth aspect of the present invention, there is provided a device body portion (“sample”) when used in a method according to either the first or the second aspects of the present invention. 
     According to a sixth aspect of the present invention, there is provided a wafer of material including at least one device body portion when used in a method according to either of the first or second aspects of the present invention. 
     According to a seventh aspect of the present invention, there is provided a sputtering apparatus when used in a method according to the second aspect of the present invention. 
     Preferably the sputtering apparatus is a diode sputterer. 
     According to an eighth aspect of the present invention, there is provided use of a sputtering apparatus in a method according to either of the first or second aspects of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       An embodiment of the present invention will now be described, by way of example only, and with reference to the accompanying drawings: 
         FIG. 1  is a side view of a device body portion, as grown, for use in a method of manufacture of an optical device according to an embodiment of the present invention; 
         FIG. 2  is a side view of an optical device according to an embodiment of the present invention manufactured from the device body portion of  FIG. 1 ; 
         FIG. 3  is a schematic view of band-gap energies of a part of the device body portion of  FIG. 1  the part comprising a core layer including a Quantum Well therein; 
         FIG. 4  is a schematic view similar to  FIG. 3  of band-gap energies of a corresponding part of the optical device of  FIG. 2  when Quantum Well Intermixed; 
         FIGS. 5(   a ) to  5 ( f ) are a series of schematic side views of a device body portion during various steps of a method of manufacture of the optical device of  FIG. 2 ; 
         FIG. 6   a  is schematic representation of a diode sputterer apparatus for use in deposition of a dielectric layer on the device body portion of  FIGS. 5  ( a ) to ( f ) during a dielectric layer deposition step shown in  FIG. 5(   c ); and 
         FIGS. 7(   a ) and ( b ) are more detailed schematic side views of the device body portion of  FIGS. 5  ( a ) to ( f ) before and after an annealing step shown in  FIG. 5(   f ). 
     
    
    
     DETAILED DESCRIPTION OF DRAWINGS 
     Referring initially to  FIG. 1 , there is shown a device body portion, generally designated  5 , as grown, for use in a method of manufacture of an optical device according to a first embodiment of the present invention. The optical device is an integrated optical device or an optoelectronic device. 
     The device body portion  5  is suitably fabricated in a III–V semiconductor material system such as Gallium Arsenide (GaAs), and therefore operates at one or more wavelength in the range 600 to 1300 nm. Alternatively, and beneficially, the device body portion is fabricated in an Indium Phosphide (InP) semiconductor system and therefore operates at one or more wavelength in the range 1200 to 1700 nm. The device body portion  5  may be made at least partly from Aluminium Gallium Arsenide (AlGaAs), Indium Gallium Arsenide (InGaAs), Indium Gallium Arsenide Phosphide (InGaAsP), Indium Aluminium Gallium Arsenide (InAlGaAs) and/or Indium Gallium Aluminium Phosphide (InGaAlP). In this described first embodiment, the device body portion is made from AlGaAs. 
     The device body portion  5  may form part of a semiconductor wafer (see  FIG. 1 ) together with a plurality of other possibly like optical devices which may be cleaved from the wafer after processing. The device body portion  5  comprises substrate  10  upon which is provided a first optical cladding layer  15 , a core guiding layer  20 , and a second optical cladding layer  25 . A Quantum Well (QW) structure  30 , including at least one Quantum Well, is provided within the core guiding layer  20 , as grown. On the second optical cladding layer  30  there is provided a capping layer  35 . 
     As will be appreciated, the core guiding layer  20 , as grown, has a smaller band-gap and higher refractive index than the first and second optical cladding layer  15 ,  25 . 
     Referring now to  FIG. 2 , there is shown an optical device, generally designated  40 , manufactured from the device body portion  5  of  FIG. 1 , by a method which will be described in detail hereinafter. As can be seen from  FIG. 2 , the device  40  comprises an active region  45  and a passive region  50 . In this embodiment the active region  45  comprises a Quantum Well (QW) amplifier. However, it should be understood that the active region  45  may, in other embodiments, comprise a laser, modulator switch, detector or like active (electrically controlled) optical device. Further, the passive region  50  comprises a low-loss waveguide wherein the Quantum Well structure  30  has been at least partially removed by a Quantum Well Intermixing (QWI) technique, as will hereinafter be described in greater detail. 
     The device  40  has excellent alignment between the core layer  20  waveguiding regions of the active region  45  and passive region  50 , and has a reflection coefficient between the active region  45  and passive region  50  which is substantially negligible (of the order of 10 −6 ). Further, mode matching between the active region  45  and the passive region  50  is intrinsic to the device  40 . 
     Typically, the substrate  10  is n-type doped to a first concentration, while the first cladding layer  15  is n-type doped to a second concentration. Further, the core layer  20  is typically substantially intrinsic, while the second cladding layer  25  is typically p-type doped to a third concentration. Further, the cap layer (or contact layer)  35  is p-type doped to a fourth concentration. It will be appreciated by those skilled in the art, that the cap layer  35  and second cladding layer  25  may be etched into a ridge (not shown), the ridge acting as an optical waveguide to confine optical modes within the core layer  20 , both within the optically active region  45  and the optically passive region  50 . Further, contact metallisations (not shown) may be formed on at least a portion of the top surface of the ridge within the optically active region  45 , and also on an opposing surface of the substrate  10 , as is known in the art. 
     It will further be appreciated that the device  40  may comprise part of an optical integrated circuit, optoelectronic integrated circuit (OEIC), or photonic integrated circuit (PIC) which may comprise one or more of such optical devices  40 . 
     Referring now to  FIG. 3 , there is shown a schematic representation of the band-gap energies of a Quantum Well  31  of the Quantum Well structure  30  within the core layer  20  of the device body portion  5 , as grown. As can be seen from  FIG. 3 , the AlGaAs core layer  20  includes at least one Quantum Well  31 , with the Quantum Well structure  30  having a lower aluminium content than the surrounding core layer  20 , such that the band-gap energy of the Quantum Well structure  30  is less than that of the surrounding AlGaAs core layer  20 . The Quantum Well structure  30  is typically around 3 to 20 nm thick, and more typically around 10 nm in thickness. 
     It will be understood that the description of  FIG. 3  also applies with suitable amendment to a system with an InGaAsP core layer, or any of the other III–V systems discussed above. 
     Referring now to  FIG. 4 , there is shown a corresponding portion  32  of the core layer  20  as in  FIG. 3 , but which has been Quantum Well Intermixed (QWI) so as to effectively increase the band-gap energy (meV) of the part  32  which corresponds to the Quantum Well  31  of the Quantum Well structure  30 . Quantum Well Intermixing (QWI) therefore essentially “washes out” the Quantum Well structure  30  from the core layer  20 . The portion shown in  FIG. 4  relates to the passive region  50  of the device  40 . As will be understood, optical radiation transmitted from or generated within the optically active region  45  of device  40  will be transmitted through the low loss waveguide provided by the Quantum Well Intermixed (QWI) region  32  of the core layer  20  of the passive region  50 . 
     Referring now to  FIGS. 5(   a ) to ( f ), there is illustrated a first embodiment of a method of manufacturing an optical device  40  from a device body portion  5 , including a Quantum Well (QW) structure  30  according to the present invention, the method including the steps (see  FIGS. 5(   b ) to ( d )) of performing a plasma etch and subsequent deposition of a dielectric layer  51  on at least part of a surface  52  of the device body portion  5  so as to introduce point defects into a portion  53  of the device body portion  5  adjacent the dielectric layer  51 . 
     The method of manufacture begins with the step of providing a substrate  10 , growing on the substrate  10  first optical cladding layer  15 , core guiding layer  20  including at least one Quantum Well (QW)  30 , second optical cladding layer  25 , and cap layer  35 . 
     The first optical cladding layer  15 , core guiding layer  20 , second optical cladding layer  25 , and cap layer  35  may be grown by known semiconductor epitaxial growth techniques such as Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition (MOCVD). Once the device body  5  has been grown—normally as part of a wafer (not shown) including a plurality of such device body portions  5 —a pattern may be defined in photoresist (PR)  55  on surface  52  of the device body portion  5 . 
     The plasma etch is performed on surface prior to the deposition of the dielectric layer  51  on the surface  52 , and the photoresist  55  lifted off so as to leave the dielectric layer  51  on the said at least part of the surface  52  of the device body portion  5 . As can be seen from  FIGS. 5(   c ) and  5 ( d ), the plasma etch performed on, and/or dielectric layer  51  deposited on, at least part of the surface  52  of device body portion  5 , causes localised damage in region  53  of the cap layer  35 , and introduces point defects into the cap layer  35 . 
     Referring briefly to  FIG. 6 , the plasma etch and dielectric layer  51  deposition are effected by sputtering, and in this embodiment the etch and dielectric layer  51  deposition are performed by sputtering using a diode sputterer apparatus, generally designated  65 . The dielectric layer  51  substantially comprises silica (SiO 2 ), but may in a modification comprise another dielectric material such as aluminium oxide (Al 2 O 3 ). 
     As can be seen from  FIG. 6 , the sputterer apparatus  65  includes a chamber  70  which in use is substantially filled with an inert gas such as argon which is preferably provided within the chamber  70  at a pressure of around 2 microns of Hg. The sputterer  65  also comprises an RF source  75  which can be connected to either (a) the target electrode (cathode)  80  of the diode sputterer  65  for dielectric layer deposition, or (b) the substrate electrode  85  for plasma etch of the device body portion. 
     A silica target  81  is provided on the target electrode (cathode)  80 , while the device body portion  5  (on wafer  82 ) is provided on the substrate electrode (anode)  85  of the sputterer  65 . In use, as can be seen from  FIG. 6 , an argon plasma  86  is generated between the cathode  80  and anode  85  with first and second dark spaces  90 , 95  being provided between the silica target  81  and the argon plasma  86  and between the argon plasma and the device body portion  5 , respectively. 
     The steps of plasma etching the semiconductor surface and depositing the dielectric layer  51  comprises part of a Quantum Well Intermixing (QWI) process used in the manufacture of the device  40 , the QWI process comprising (in a preferred embodiment) an Impurity-Free Vacancy Disordering (IFVD) technique. It has been surprisingly found that by plasma etching the semiconductor surface and subsequently depositing the dielectric layer  51  used in QWI techniques such as IFVD by sputtering using the sputterer  65 , damage induced defects appear to be introduced into the portion  53  of the device body portion  5  adjacent dielectric cap  51 ; the portion  53  in this case comprising part of the cap layer  35 . It is believed that the damage breaks bonds in the cap layer  35  prior to annealing (which will hereinafter be described), eg the application of thermal energy by rapid thermal annealing, thereby expediting the transfer of gallium and/or indium from the cap layer  35  into the dielectric layer  51 . 
     The dielectric layer  51  is typically between 10 to 1000 nm, and typically 200 or 300 nm in thickness. The method of manufacture includes a further step as shown in  FIG. 5(   e ) of depositing further dielectric layer  60  on the surface  52  of device body  5  and on a surface of the dielectric layer  51  prior to annealing. The further dielectric layer  60  is deposited without a preliminary plasma etch and preferably also by a technique other than diode sputtering, and preferably by a technique other than sputtering per se, eg Plasma Enhanced Chemical Vapour Deposition (PECVD). 
     The dielectric layer  51  encapsulating the plasma etched layer therefore comprises an intermix cap layer, while the further dielectric layer  60  comprises an intermix suppressing cap layer. The intermix suppressing cap layer is used to protect the surface  52  from arsenic and/or phosphorus desorption. The method will work without the intermix suppressing cap layer; however the quality of the surface  52  may not be so good. 
     As shown in  FIG. 5(   f ), subsequent to deposition of the further dielectric layer  60 , the device body portions including the dielectric layer  51  and further dielectric layer  60  are annealed at an elevated temperature. The annealing stage comprises a rapid thermal annealing stage, the annealing temperature being around 700° C. to 1000° C., or more preferably 650° C. to 850° C., for around 0.5 to 5 minutes, and in one implementation, at approximately 800° C. for about 1 minute. 
     The action of the annealing step of  FIG. 5   f ) is illustrated diagrammatically in  FIGS. 7(   a ) and ( b ). As can be seen from  FIGS. 7(   a ) and ( b ), the annealing step causes “out diffusion” of gallium and/or indium from the cap layer  35  to the intermixing cap, ie dielectric layer  51 . However, portions of the cap layer  35  below the suppressing cap, ie further dielectric layer  60 , are not subject to gallium and/or indium “out-diffusion”. The portions of the cap layer  35  which lie within an area of the intermixing cap, ie dielectric cap  51 , are subject to out-diffusion of gallium and/or indium as shown in  FIG. 7(   b ). The out-diffusion of gallium and/or indium leaves vacancies behind which vacancies migrate from the cap layer  35 , through the second cladding layer  25 , and into the core layer  20 , and hence to the Quantum Well structure(s)  30 , thereby changing the effective band-gap of the Quantum Well (QW) structure  30 , and effectively washing-out the Quantum Wells of the Quantum Well structure  30  below the intermixing cap layer. 
     It will be appreciated that the intermixing cap, ie the dielectric layer  51  encapsulating the plasma etched surface  52 , is provided within the area of the passive region  50  to be formed in device  40 , while the suppressing cap, ie further dielectric layer  60 , is provided on the device body portion  5  in areas such as the optically active region  45  to be formed on the device  5 , which areas are not to be Quantum Well Intermixed (QWI). 
     Once the device body portion  5  has been processed to the stage of  FIG. 5(   f ), and annealed, the dielectric layer  51  and further dielectric layer  60  may be removed by conventional methods, eg wet or dry etching. 
     EXAMPLE 
     There now follows examples which illustrate typical band-gap shifts which can be obtained using IFVD in a method of manufacturing an optoelectronic device according to the present invention in a long wavelength aluminium alloy such as Indium Aluminium Gallium Arsenide, (InAlGaAs), or InGaAsP, (InGaAsP), grown on an Indium Phosphide (InP) substrate. 
     The dielectric layer  51  deposition requires a sputter chamber  70  configured with a target-substrate electrode (plate) separation of the order of 50 to 100 mm. The target electrode  80  and substrate electrode  85  are each configured as substantially eight inch circular plates. The gas used in this example for sputter etch and deposition is typically argon, but other suitable inert gases may be used, and also small amounts of oxygen may be added to the argon plasma  86 , eg approximately 10% by volume, to improve the stoichiometry of the deposited dielectric layer  51 . The dielectric material used in the method is typically silica (SiO 2 ), but other dielectric materials such as aluminium oxide (Al 2 O 3 ) can be used. 
     It has been found that a preferred pressure range in the chamber  70  for the method is between 1 and 5 microns of Hg. For sputter etch RF power values shown in Table 1 below, a one minute sputter etch was carried out on the surface of the semiconductor wafer  52 , including at least one device body portion  5 . The thickness of the subsequently deposited dielectric film  45  was from 10 to a few hundred nm. The band-gap shift figures in Table 1 illustrate the band-gap shift in an InGaAs—InAlGaAs QW structure  30  for an anneal at a temperature of 800° C. for a time of 1 minute. 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Sputter etch RF power 
                 Deposition Conditions 
                 Band gap shift (nm) 
               
               
                   
               
             
            
               
                 None 
                 PECVD (SiO 2 ) 
                  1 
               
               
                 300 W 
                 Sputtered (SiO 2 ) 
                 12 
               
               
                 500 W 
                 Sputtered (SiO 2 ) 
                 21 
               
               
                 700 W 
                 Sputtered (SiO 2 ) 
                 38 
               
               
                   
               
            
           
         
       
     
     Table 1 illustrates that etching the surface of the semiconductor  52  followed by encapsulation with sputtered silica provides an enhancement in intermixing compared to non-sputtered silica (SiO 2 ), and also illustrates that the effectiveness of the pre-etched sputtered silica (SiO 2 ) cap increases with RF power used during the sputter etch. 
     Further data from plasma etching the surface  53  of an InGaAs—InGaAsP QW structure followed by deposition of sputtered SiO 2  layer  51  is presented in Table 2. Two sputter etch powers are shown in Table 2, along with two sputtering pressure settings, each referring to a one minute sputter etch of the semiconductor surface  52 , including at least one device body portion  5 . The thickness of the subsequently deposited dielectric film  51  was from 10 to a few hundred nm. The band-gap shift figures in Table 2 illustrate the band-gap shift in an InGaAs—InGaAsP QW structure  30  for an anneal at a temperature of 700° C. for a time of 1 minute. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 Sputter etch 
                 Sputter etch 
                   
                 Band gap shift 
               
               
                 RF Power 
                 pressure 
                 Deposition Conditions 
                 (nm) 
               
               
                   
               
             
            
               
                 NONE 
                 NONE 
                 PECVD (SiO 2 ) 
                 11 
               
               
                 300 
                 1 
                 Sputtered (SiO 2 ) 
                 61 
               
               
                 300 
                 3 
                 Sputtered (SiO 2 ) 
                 58 
               
               
                 750 
                 1 
                 Sputtered (SiO 2 ) 
                 78 
               
               
                 750 
                 3 
                 Sputtered (SiO 2 ) 
                 45 
               
               
                   
               
            
           
         
       
     
     Table 2 again illustrates that etching the surface  52  of the semiconductor followed by encapsulation with sputtered silica  51  provides an enhancement in intermixing compared to non-sputtered silica (SiO 2 ), and also illustrates that the effectiveness of the pre-etched sputtered silica (SiO 2 ) cap  51  is not strongly dependent on pressure for low power etches but is dependent upon pressure for higher power etches, the effectiveness decreasing with increasing sputter pressure. Table 2 also illustrates the lower thermal stability of the InGaAs—InGaAsP QW material compared to InGaAs—InAlGaAs QW material, as, for a given sputter etch power, larger shifts are obtained at reduced annealing temperatures. 
     In a second embodiment of a method of manufacturing an optical device  40  according to the present invention, to process a wafer to produce more than one band-gap a film of PECVD SiO 2  is deposited on to the wafer to provide further dielectric layer  60 . Photolithography techniques are then used to delineate a pattern on top of the PECVD SiO 2 . Either wet or dry etching can then be used to transfer the pattern into the PECVD (SiO 2 ). 
     Patterned photoresist (PR) is then left on top of the patterned PECVD (SiO 2 ), and the sample/wafer is then placed into the sputtering apparatus  65  for plasma etching of the uncoated surface  52  and subsequent deposition of the dielectric layer  51 . After deposition the sample is immersed in acetone and the sputtered SiO 2  on the photoresist is removed in a “lift-off” process. 
     A rapid thermal anneal is now performed at a suitable temperature (650–850° C.) for the required period of time (0.5–5 min). This enables the point defects generated at the surface  52  to propagate through the device body portion  5  and cause interdiffusion of the elements. 
     It will be appreciated that the embodiment of the invention hereinbefore described are given by way of example only, and are not meant to limit the scope thereof in any way. 
     It should be particularly understood that the damage induced in the semiconductor device body portion  5  adjacent to the sputtered dielectric layer  51  is believed to arise from bombardment of ions and/or radiation in the form of secondary electrons and soft x-rays. The damage to the surface  50  of the semiconductor device body portion  5  or wafer  82 , can be introduced by various means in the sputtering apparatus  65 , an effective method being to use a diode configuration in the deposition chamber  70 . 
     Using a diode configuration is also believed to permit more radiation damage to the device body portion  5  (or “sample”) than in the more usual magnetron machine arrangement wherein magnets create a high local field which it is believed stop particles travelling from the dielectric target  81  to the device body portion  5  provided on the wafer  82  of semiconductor material.) 
     It will further be appreciated that an optical device according to the present invention may include a waveguide such as a ridge or buried heterostructure or indeed any other suitable waveguide. 
     It will also be appreciated that the Quantum Well Intermixed (QWI) regions may comprise optically active device(s). 
     Further, it will be appreciated that sequential processing including using several RF powers may be used to provide a device with several different QWI band-gaps.