Patent Publication Number: US-8537043-B1

Title: Digital-to-analog converter with controlled gate voltages

Description:
FIELD OF THE INVENTION 
     The present invention is generally directed to digital-to-analog converters (DACs), in particular, to methods and apparatus that may control gate voltages of NMOS and PMOS switches used in R-2R voltage-mode DACs. 
     BACKGROUND INFORMATION 
     A voltage-mode R-2R digital-to-analog converter (DAC) includes resistor legs that are switched between two reference voltages (Vref and the ground Vgnd) using a single-pole, double-throw switch.  FIG. 1  illustrates a segmented voltage-mode R-2R DAC  100  that converts a digital code input into an analog voltage output (Vout). The segmented voltage-mode R2R DAC  100  may include a resistor ladder that further includes a number of legs. Each leg may include a resistor (2R) and a switch  106 . 1 - 106 . 6  so that the resistor (2R) is switchably connected to either a first position that connects to the ground (Vgnd) or a second position that connects to a reference voltage potential (Vref). The switches  106 . 1 - 106 . 6  are MOS switch pairs that are discussed in detail along with  FIG. 2 . Each leg of the resistor ladder (including a corresponding switch pair) is controlled by a bit of the digital code according to an order of a least significant bit (LSB) at the left side to a most significant bit (MSB) at the right side. If the bit value equals zero, the switch is switched to the first position so that the corresponding leg is connected to Vgnd; if the bit value equals one, the switch is switched to the second position so that the corresponding leg is connected to Vref. Thus, the digital code may be converted into an analog voltage output (Vout) through voltage attenuation over the resistor ladder. 
     The segmented voltage-mode R-2R DAC  100  may be divided into two portions. A first portion on the left side of the dashed line is an R-2R DAC  102 , and a second portion on the right side of the dashed line is a segmental DAC  104 . The R-2R DAC  102  may include digital bits of lower significance, while the segmented DAC may include bits of higher significance. Together, the R-2R DAC  102  and the segmental DAC  104  form the segmented voltage-mode R-2R DAC  100 . 
       FIG. 2  illustrates a detailed circuit schematic for the MOS switches  106 . 1 - 106 . 6 . Referring to  FIG. 2 , a switch  200  (that can be any one of the MOS switches  106 . 1 - 106 . 6 ) receives a digital bit B(N) and outputs a voltage of Vgnd or Vref to the resistor (2R) in a leg of the segmented voltage-mode R-2R DAC. The switch  200  includes drivers  202 ,  204 , and a p-channel MOSFET (PMOS)  206 , and an n-channel MOSFET (NMOS)  208 . The drivers  202 ,  204  respectively receive the digital bit B(N), while the outputs of drivers  202 ,  204  are coupled to the gates of the PMOS  206  and NMOS  208 , respectively. Based on the digital input, the output of driver  202  may be driven to either a reference voltage Vgp or a positive supply voltage Vdd, and the output of driver  204  may be driven to either a reference voltage Vgn or a negative supply voltage Vss. In operation, the PMOS  206  and the NMOS  208  form a complementary MOS switch pair so that, at any moment, if the gate voltage of the PMOS  206  is at Vgp, the gate voltage of the NMOS  208  is at Vss; or alternatively, if the gate voltage of the PMOS  206  is at Vdd, the gate voltage of the NMOS  208  is at Vgn. Therefore, at any moment, only one of PMOS  206  and NMOS  208  is on. 
     An ideal switch, when it is ON (or engaged), has zero resistance. However, in practice, when PMOS  206  or NMOS  208  is ON, each of the MOS switches has an ON resistance. Further, the ON resistance for PMOS  206  is commonly different from the ON resistance for NMOS  208 . This unequal ON resistances between PMOS  206  and NMOS  208  cause inaccuracy in the DAC output. U.S. Pat. No. 5,075,677 (the &#39;677 patent) (assigned to the assignee of the present application) describes a Vgn generator circuit that supplies adjustable Vgn (or similarly, adjustable Vgp) to driver  204  (or similarly, driver  202 ) so that the apparent ON resistances for the PMOS and NMOS switches are substantially same. 
       FIG. 3  illustrates a Vgn generator as described in the &#39;677 patent. Referring to  FIG. 3 , the Vgn generator  300  includes an op-amp  302 , a PMOS  304 , an NMOS  306 , and resistors  308 - 314 . Resistors  308 ,  310  are selected to have a same first resistance (R 1 ) within a precision range, and resistors  312 ,  314  are selected to have a same second resistance (R 2 ) within a precision range. Since the resistors  312 ,  314  are selected to have a same second resistance, the voltage at node  318  is Vref/2 which is supplied to the inverted input of the op-amp  302 . By operation of the op-amp  302 , the voltage at the non-inverted input of the op-amp  302  follows the inverted input and also equals to Vref/2. Further, since resistors  308 ,  310  also have the same resistance, the voltage drops over resistors  308 ,  310  are also the same and thereby Vds for PMOS  304  equals Vds for NMOS  306 . The Vds balance between PMOS  304  and NMOS  306  is achieved by adjusting Vgn as the gate of the NMOS  306 . The adjustable Vgn is applied to the gate of the NMOS switch  208 . In this way, the &#39;677 patent chooses Vgn for NMOS switch which results in equalizing the ON resistances between the NMOS switch  208  and the PMOS switch  206 . While  FIG. 3  illustrates a Vgn generator, a person of ordinary skill in the art would understand that a Vgp generator may be similarly constructed with the output being coupled to the gate of PMOS  304  and the gate of NMOS  306  being coupled to Vref. Therefore, the following embodiments are discussed in terms of the Vgn generator for convenience. 
     To reduce sensitivity to the input offset (Vos) of op-amp  302  and to reduce sensitivity to resistor mismatches, current art uses a moderately large Vds for the PMOS  304  and NMOS  306  in the Vgn generator so that they are much larger than Vds for PMOS  206  and NMOS  208 , namely, Vds [Vgn]&gt;&gt;Vds [DAC]. However, as shown in the following, this causes non-linearity in the resistor legs in the DAC, which is undesirable, especially for bits of higher significance such as MSB. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a segmented voltage-mode R-2R digital-to-analog converter. 
         FIG. 2  illustrates a switch including a complementary PMOS and NMOS pair. 
         FIG. 3  illustrates a Vgn generator. 
         FIG. 4  illustrates a Vgn generator according to an exemplary embodiment of the present invention. 
         FIG. 5  illustrates a Vgn generator according to another exemplary embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS 
     The current I DS  going through a MOS transistor may include a non-linear factor with respect to Vds. For example, with respect to NMOS  306  as shown in  FIG. 3 , it is known that I DS , i.e., the current from drain to source 
                         I   DS     =       K   ′     ⁢     W   L     ⁢     {         (       V   GS     -     V   T       )     ⁢     V   DS       -       V   DS   2     2       )         }     =       K   ′     ⁢     W   L     ⁢     (       V   GS     -     V   T     -       V   DS     2       )     ⁢     V     DS   ′                 (   1   )               
where K′ is a constant coefficient, W/L is the width to length ratio of the NMOS, V GS  is gate-to-source voltage, V T  is a threshold voltage over which the NMOS is ON, and V DS  is the voltage drop from drain to source. Therefore, ON resistance R ON  (=V DS /I DS ) may depend on V DS , including a non-linear factor which may increase when V DS  is large. However, the resistor legs of the DAC are usually designed so that the NMOS switches may have a small Vds, particularly in the switches for MSB resistor legs. Thus, a conflict exists between linearity and accuracy of the output of the DAC. Although it is desirable that V DS  is large so that operation of the “Vgn Generator” is less sensitive to op-amp offset and resistor mismatc, large V DS  unfortunately also generates non-linearity in the ON resistance which in turn may cause non-linearity in the DAC. Current art makes compromises by using a moderately large V DS , and subsequently trimming the circuit such as laser trimming to reduce errors that result from the compromised sensitivity of the “Vgn Generator” to op-amp offsets and resistor mismatches.
 
     It is an objective of this invention to provide good output accuracy without the need for subsequent trimming or calibration. It is also an objective of the present invention to provide good output accuracy without the need for adding an additional negative supply rail. 
     Embodiments of the present invention may include a digital-to-analog converter (DAC) that may include at least one resistor leg that is switchably connected to one of a first voltage reference via a first n-channel MOSFET (NMOS) and to a second voltage reference via a first p-channel MOSFET (PMOS), and a generator circuit that may include a first sub-circuit for generating a first drive voltage (Vgn) and a second sub-circuit for a) offsetting the first drive voltage by an offset voltage to generate a second drive voltage, and b) supplying the second drive voltage to a gate of one of the first NMOS and the first PMOS. 
     Embodiments of the present invention may include a generator circuit for a digital-to-analog converter. The generator circuit may include a first sub-circuit for generating a first drive voltage (Vgn), and a second sub-circuit for a) offsetting the first drive voltage by an offset voltage to generate a second drive voltage, and b) supplying the second drive voltage to a gate of one of the first NMOS and the first PMOS. 
     Embodiments of the present invention may include a digital-to-analog converter (DAC) that may include a plurality of resistor legs, each resistor leg corresponding to a digital bit having a bit significance, each resistor leg being switchably connected to one of a first voltage reference and to a second voltage reference via a respective MOS pair, the respective MOS pair each including a first NMOS and a first PMOS, and a generator circuit that may include a first sub-circuit for generating a first drive voltage (Vgn), and a second sub-circuit for a) offsetting the first drive voltage by a plurality of offset voltages to generate a plurality of second drive voltages and b) supplying each of the plurality of the second drive voltages and the corresponding offset voltages to the respective MOS pair. 
     Embodiments of the present invention may include a generator circuit that may include additional circuitry that cancels the non-linear error term. As shown in Equation (1), the nonlinearity may be reduced if Vgs is reduced by a certain amount, preferably by Vds/2.  FIG. 4  illustrates a Vgn/Vgp generator according to an exemplary embodiment of the present invention. The Vgn/Vgp generator  400  may include a first sub-circuit  426  and a second sub-circuit  428 . Further, for convenience of illustration,  FIG. 4  also shows a resistor leg of a DAC including a PMOS switch  414 , an NMOS switch  416  that are driven by a driver circuit  424 , and two resistors (Rdac). The first sub-circuit  426  and the second sub-circuit  428  together may form the Vgn/Vgp generator  400 , whereas the first sub-circuit  426  reflects the Vgn generator as shown in  FIG. 3 , and the second sub-circuit  428  is a circuit that may be used to subtract Vds/2 (in the Vgn/Vgp generator) from the output of the first sub-circuit  426 . 
     In one embodiment of the present invention, the first sub-circuit  426  may include an op-amp  402 , stacked PMOS  404 ,  406 , stacked NMOS pair  408 ,  410 , and two resistor pairs R 1 , R 2 . The first sub-circuit  426  may operate in essentially the same as way as the Vgn generator as shown in  FIG. 3 . The stacked PMOS pair  404 ,  406  and stacked NMOS pair  408 ,  410  are used to illustrate their respective Vds is larger than those in DAC. Thus, the Vgn of prior art (VGN_PA) at node  418 , if used in the DAC would include non-linear effects due to the extra term of Vds/2. 
     The second sub-circuit  428  may subtract Vds/2 from the voltage output at node  418  and supply appropriate gate voltages to the respective gates of PMOS switch  414  and NMOS  416 . The second sub-circuit  428  may include an op-amp  405 , an NMOS  412 , and three resistors (R 3 ). The non-inverted input of the op-amp  405  is coupled to a drain of the stacked PMOS  408  so that the non-inverted input of the op-amp  405  has an input voltage of Vds. The NMOS  412  and the three resistors (R 3 ) are serially connected so that two R 3  are serially connected between the ground Vgnd and the source of NMOS  412 , and the third R 3  is coupled between the drain of NMOS  422  and the output of op-amp  402  (or node  418 ). The inverted input of op-amp  405  is coupled to the source of the NMOS  412 , and the output of op-amp  405  is coupled to the gate of the NMOS  412 . The drain of the NMOS  412  (node  422 ) may supply Vgn to a first driver  430  (in the driver circuit  424 ) whose output may be coupled to the gate of NMOS switch  416  of the DAC, and the junction  420  (between the two serially connected R 3 ) may supply an offset voltage, here a reduction voltage, Vgp to a second driver  432  (in the driver circuit  424 ) whose output may be coupled to the gate of the PMOS switch  414  of the DAC. 
     By operation of op-amp  405 , the inverted input may follow the non-inverted input so that the voltage at node  426  is also Vds. The current at the drain of NMOS  412 , Id=Vds/(2*R 3 ), which causes a drop of Vds/2 from node  418  to node  422 , namely, at the gate of the NMOS switch  416  of the DAC. The gate voltage of PMOS switch  414  may be the same as that at node  420  at Vds/2. In this way, the gate voltages for the NMOS switch  416  and PMOS switch  414  may be shifted by Vds/2 and thus reduce the non-linearity in the DAC output. Embodiments of the present invention as shown in  FIG. 3  may have the advantage of maximizing the Vds in the Vgn/Vgp generator circuit without the need to compromise non-linearity for the more significant bits and without the need to trim the circuit. 
     In one embodiment of the present invention, the size of both PMOS and NMOS switches for different bits may be scaled from the MSB&#39;s (or switches in the segments portion of the segmented DAC) down to the LSB&#39;s (or switches in the R-2R portion of the segmented DAC). For example, the scaling scheme may be binary scaling—i.e., the size of a lower bit is half the size of the immediate higher bit. Other scaling technique such as Conroy scaling may also be used. Regardless of the scaling schemes, W/L (or the width to length ratio) of an MSB switch is much larger than W/L of the last LSB switch. Since the ON resistance is inversely proportional to the W/L ratio, the MSB&#39;s have a much smaller ON resistance than the LSB&#39;s. Thus, for a same current that flows through an MSB switch and a LSB switch, the voltage drop over the LSB switch may be much larger than the voltage drop over the MSB switch. In the present DAC setup, the current flowing through the switches and thus the voltage drop across the switches are a function of the digital input code, where the voltage drops across the switches for MSB&#39;s may be negligible, and the voltage drops across the switches for LSB&#39;s may have a large variations. 
     It is desirable to factor into the non-negligible voltage drops across the switches for LSB&#39;s by supply a smaller voltage correction for LSB&#39;s. In one exemplary embodiment, rather than Vds/2 correction for MSB&#39;s, the LSB&#39;s may be supplied with Vds/4 correction. 
     In another exemplary embodiment, the gate voltages for LSB&#39;s switches may be generated variably in accordance to the corresponding bit position. Accordingly, the gate voltage at a lower significant bit in the LSB region may have smaller voltage correction, while the gate voltage at a higher significant bit in the LSB region may have larger voltage correction.  FIG. 5  illustrates a segmented R-2R DAC that have variable gate voltages for LSB&#39;s according to an exemplary embodiment of the present invention. Referring to  FIG. 5 , a segmented R-2R DAC  504  may include a segmental portion  506  for MSB&#39;s and a R-2R portion for LSB&#39;s. The gate voltages for the MSB&#39;s in the segmental portion  506  may be similar to  FIG. 4 , including a voltage correction of Vds/2. However, the gate voltages for the LSB&#39;s in the R-2R potion may be variable, depending on the digital bit position, and supplied from Vgn/Vgp generator. As discussed in  FIG. 4 , the Vgn/Vgp generator may be similar to the first sub-circuit  406  as shown in  FIG. 4  for generating a Vgn without correction, and a second sub-circuit  502  for correcting the generated Vgn by a correction voltage. 
     The sub-circuit  502  may include an op-amp  510 , an NMOS  512 , a stack of serially connected resistors R 4 , and a stack of serially connected resistors R 5 . In one embodiment, the sum resistance of the serially connected resistors R 4  may equal the resistance of R 3  as shown in  FIG. 4 , or ΣR 4 =R 3 , and the sum resistance of the serially connected resistors R 5  may equal two times resistance of R 3 , or ΣR 5 =2*R 3 . The Pm node of the sub-circuit  502  may be at the middle point of the serially connected R 5 , namely, half of the serially connected R 5  being connected from the source of NMOS  512  to Pm and half of R 5  being connected from Pm to the ground. The serially connected R 4  may be connected between the drain of NMOS  512  and an output of a Vgn generating circuit  426  as shown in  FIG. 4 . In one embodiment, the voltage from the drain of NMOS  512  (node Nm) may be supplied to the gates of those NMOS switches of the MSB&#39;s of DAC  504 , and the voltage at node Pm may be supplied to those PMOS switches of the MSB&#39;s of DAC  504 . In a preferred embodiment, the MSB&#39;s of DAC  505  may include those bits in segmental portion  508  of the segmented R-2R DAC. Thus, the Vgn and Vgp at the gates of the MOS switches for those MSB&#39;s may be reduced by Vds/2, where the Vds is a drain to source voltage drop as shown in  FIG. 4 . 
     For those less significant bits such as those bits in the R-2R portion  506  of the DAC, Vgn and Vgp at the gates of the MOS switches for those LSB&#39;s may be reduced according to the bit positions. In one embodiment, the amount of voltage offsets may decrease from a higher bit to a lower bit for those LSB&#39;s. Referring to  FIG. 5 , as an example for illustration, bits i+1, i, i−1 may have decreasing significance. Therefore, the voltage offset amounts of Vgn/Vgp for bits i+1, i, i−1 may accordingly decrease. In one embodiment, gate voltages for NMOS switches for bits i+1, i, i−1 may be from nodes Ni+1, Ni, Ni−1 in the sub-circuit  502  (or R 4 &#39;s at positions Ni+1, Ni, Ni−1 from the drain of NMOS  512 ), and gate voltages for PMOS switches for bits i+1, i, i−1 may be from nodes Pi+1, Pi, Pi−1 in the sub-circuit  502  (or R 5 &#39;s at positions Pi+1, Pi, Pi−1 from Pm node). In this way, the voltage offset amounts may proportionally decrease in accordance to bit positions for LSB&#39;s. 
     Those skilled in the art may appreciate from the foregoing description that the present invention may be implemented in a variety of forms, and that the various embodiments may be implemented alone or in combination. Therefore, while the embodiments of the present invention have been described in connection with particular examples thereof, the true scope of the embodiments and/or methods of the present invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.