Patent Publication Number: US-6335285-B1

Title: Method for manufacturing a globally planarized semiconductor device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device providing global planarization between a cell region and a periphery region using a chemical mechanical polishing (CMP) process. 
     2. Description of the Related Art 
     The semiconductor device has entered an era of ultra-large-scale integration (ULSI) represented by 256 megabit DRAMs or 1 gigabit DRAMs toward high function, high performance and high integration. Since finer pattern formation technology is necessary for high integration of devices and three-dimensional multiple layered structures are required in various fields, introduction of new processes are being examined. 
     When ultra-fine interconnection lines are multilayered by a pattern formation technology, it is necessary to planarize an interlevel dielectric layer being under the interconnection lines. To this end, partial planarization has been employed. However, to enhance wafer fabrication performance or manufacture of high quality products, a chemical mechanical polishing (CMP) process for planarization throughout the entire surface of a wafer, i.e., global planarization, needs to be introduced. 
     In manufacturing a semiconductor device, the cases of forming fine patterns on a complete planar silicon substrate, and forming fine patterns on an uneven substrate formed by already existing patterns, are quite different. The presence of unevenness causes inhomogeneity in an interface between the substrate and a mask, and makes it impossible to attain a desirable pattern preciseness. Thus, various measures for partially alleviating unevenness have been taken. 
     FIGS. 1 through 3 are cross-sectional views for illustrating a conventional method for planarizing a cell array region and a periphery region using a chemical mechanical polishing process. 
     First, referring to FIG. 1, an isolation layer  4  for defining an active region and a field region is formed on a semiconductor substrate  2  containing a cell array region and a periphery region using a conventional isolation technology. Next, a transistor comprised of a gate insulation layer (not shown), gate electrodes  6  and  8 , and source/drain (not shown) is formed in the active region of the semiconductor substrate  2 . 
     Subsequently, an insulation material, e.g., silicon nitride, is deposited on the semiconductor substrate where the transistor is formed, and then an insulation layer  10  having a space is formed. The insulation layer  10  is for forming a contact hole in a self-aligning manner during a subsequent step. 
     Next, an insulation material providing easy planarization, e.g., boron phosphorus silicate glass (BPSG), is deposited over the entire surface of the semiconductor substrate having the insulation layer  10 , and then thermally treated at a predetermined temperature to form an interlevel dielectric layer  12 . Next, a CMP process is performed on the interlevel dielectric layer  12  to planarize the same. The part indicated by the dotted line represents an interlevel dielectric layer before being planarized. 
     Referring to FIG. 2, a photoresist pattern (not shown) is formed on the planarized interlevel dielectric layer  12  and then the interlevel dielectric layer  12  is patterned using the photoresist pattern as a mask, thereby forming a contact hole  14  exposing a source or drain region (not shown) of the semiconductor substrate  2 . 
     Referring to FIG. 3, a conductive material, e.g., an impurity-doped polysilicon layer, is deposited on the resultant structure having the contact hole, and then the polysilicon of the periphery region is removed. Next, a CMP process is performed on the polysilicon layer deposited on the cell array region, thereby forming a conductive pad  16  whose surface is planarized. The CMP process performed on the polysilicon layer employs the interlevel dielectric layer  12  as a stopper. The part indicated by the dotted line represents a polysilicon layer before being planarized. 
     According to the conventional method, a step difference between the cell array region and the periphery region is removed by performing the CMP process twice, thereby providing global planarization. However, the conventional method for manufacturing a semiconductor device consists of deposition and flow of an interlevel dielectric layer, a first CMP process for the interlevel dielectric layer, contact formation, deposition of a polysilicon layer, and a second CMP process for a pad polysilicon layer, that is, two CMP processes are necessary. Thus, the manufacturing process is complicated, and several defects, i.e., micro scratches on a substrate due to repeated CMP processes, or bridges due to the micro scratch, may be generated. 
     SUMMARY OF THE INVENTION 
     To solve the above problems, it is an objective of the present invention to provide a method for manufacturing a semiconductor device which can provide global planarization between a cell array region and a periphery region by a single CMP process. 
     Accordingly, to achieve the above objective, first, an interlevel dielectric layer is formed over the entire surface of a semiconductor substrate where a global step difference exists between a cell array region and a periphery region. A first material layer serving as a stopper is formed on the interlevel dielectric layer. A contact hole partially exposing the semiconductor substrate of the cell array region is formed by patterning the first material layer and the interlevel dielectric layer. A conductive layer is formed over the entire surface of the semiconductor substrate where the contact hole is formed. Global planarization is provided between the cell array region and the periphery region by performing a chemical mechanical polishing (CMP) process on the semiconductor substrate where the conductive layer is formed. 
     When forming the interlevel dielectric layer, a flowable insulation layer, e.g., boron phosphorus silicate glass (BPSG), is deposited over the entire surface of the semiconductor substrate where the global step difference exists between the cell array region and the periphery region, and the insulation layer is flowed by thermally treating the same at a predetermined temperature. 
     The first material layer is preferably formed of a silicon nitride layer or a silicon oxynitride layer, and is preferably formed to a thickness of 50˜2,000Å. Also, the conductive layer is preferably formed of a polysilicon layer. Preferably, the step of etching back the conductive layer is followed by the step of forming the conductive layer. Here, the step of etching back the conductive layer is preferably performed until the conductive layer formed in the periphery region is removed. 
     The CMP process is performed under the condition that an etching selectivity of the interlevel dielectric layer to the conductive layer to the first material layer is 100-200:100-200:5-50. Here, the CMP process is preferably performed using the first material layer of the periphery region as a stopper. Otherwise, the CMP process is preferably performed until the first material layer of the periphery region is removed. 
     Also, before forming the interlevel dielectric layer, the method according to the present invention further comprises the steps of sequentially forming a gate insulation layer and gate electrodes on the semiconductor substrate, //forming a source/drain on the semiconductor substrate using the gate electrodes as a mask, and //forming a spacer at side walls of the gate electrodes. The gate electrodes are formed by depositing polysilicon and silicide, and the spacer is preferably formed of a silicon nitride layer. 
     According to the present invention, a stopper layer is formed using a material which can suppress a CMP process on the interlevel dielectric layer, thereby achieving global planarization between the cell array region and the periphery region by a single CMP process. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objectives and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: 
     FIGS. 1 through 3 are cross-sectional views illustrating a conventional method for planarizing a cell array region and a periphery region; and 
     FIGS. 4 through 7 are cross-sectional views illustrating a method for manufacturing a globally planarized semiconductor device according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinbelow, the present invention will be described in more detail with reference to the accompanying drawings. 
     The present invention is implemented in various forms but is not limited to the following embodiments. These embodiments are provided only for perfecting the disclosure of the invention and making the scope of the invention known to those who have ordinary skills in the art. Throughout the drawings, components of various devices, a positional relationship therebetween and thicknesses of various films and areas are emphasized for clarity. In the drawings, the same elements are designated by the same numbers. Also, in the case when it is described that a certain layer exists “on” another layer or substrate, the certain layer may exist directly on another layer or substrate or a third layer may be interposed therebetween. 
     FIGS. 4 through 7 are cross-sectional views illustrating a method for manufacturing a globally planarized semiconductor device according to the present invention. 
     Referring to FIG. 4, an isolation layer  44  for defining an active region and a field region is formed on a semiconductor substrate  42  containing a cell array region and a periphery region using a conventional isolation technology. Next, a transistor comprised of a gate insulation layer (not shown), gate electrode  46  and  48 , and a source/drain (not shown) is formed in the active region. 
     The gate electrode  46  and  48  may be formed of an impurity-doped polysilicon layer  46 . Otherwise, to enhance the operational speed of a device, the gate electrode  46  and  48  may be formed by depositing a low-resistance conductive material, e.g., tungsten silicide (WSI)  48 , on the polysilicon layer  46 . 
     Subsequently, an insulation material, e.g., silicon nitride, is deposited on the semiconductor substrate where the transistor is formed, and then an insulation layer  50  having a spacer is formed. The insulation layer  50  is for forming a contact hole in a self-aligning manner during a subsequent step. 
     Next, an insulation material providing easy planarization, e.g., boron phosphorus silicate glass (BPSG), is deposited over the entire surface of the semiconductor substrate having the insulation layer  50 , and then thermally treated at a predetermined temperature to form an interlevel dielectric layer  52 . 
     In contrast to the conventional process, wherein the conventional interlevel dielectric layer had been formed thick in consideration of the primary CMP process, in the present invention the interlevel dielectric layer  52  is formed to be thin —just thick enough so that the gate electrodes of the periphery region are not exposed. 
     Next, a material which can serve as a stopper in the CMP process in which the interlevel dielectric layer and the polysilicon layer are etching targets, e.g., a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON), is deposited over the entire surface of the interlevel dielectric layer  52  to a predetermined thickness, thereby forming a stopping layer  54 . 
     The silicon nitride layer (SiN) may be deposited by a low pressure chemical vapor deposition (LPCVD) method, and the silicon oxynitride layer (SION) may be deposited by a plasma enhanced chemical vapor deposition (PECVD) method or LPCVD method. These layers are preferably formed to a thickness of 50˜2,000Å. 
     The stopping layer  54  increases the photolithography margin in a subsequent self aligned contact (SAC) forming process, and serves as a selective stopper for the periphery region in a subsequent CMP process. 
     Referring to FIG. 5, a photoresist pattern is coated on the stopping layer  54  and then exposure and development are performed thereon to form a photoresist pattern. The stopping layer  54  and the interlevel dielectric layer  52  are sequentially patterned using the photoresist film as a mask, thereby forming a contact hole  56  exposing a source or drain region (not shown) of the semiconductor substrate. 
     Referring to FIG. 6, a conductive material for forming a pad, e.g., an impurity-doped polysilicon layer  58 , is deposited on the resultant structure having the contact hole to a thickness sufficient to fill the contact hole. Next, the polysilicon layer is etched back to recess the same to a predetermined depth. At this time, the etch-back process for the polysilicon layer  58  is performed until the polysilicon layer of the periphery region is completely removed and the surface of the stopping layer  54  is exposed. Then, the polysilicon layer thicker than the pad to be formed remains in the cell array region. A part indicated by the dotted line represents the polysilicon layer before being etched back. 
     Referring to FIG. 7, in a state where a global step difference exists between the cell array region and the periphery region, a CMP process is performed on the resultant structure. The CMP process is performed under conditions in which there is little selectivity between the interlevel dielectric layer  52  and the polysilicon layer  58 , and the selectivity between these layers  52  and  58  and the stopping layer  54  is made large, preferably, in the range of 100-200:100-200:5-50. 
     Since the stopping layer  54  having a low etching ratio is formed comparatively thinly in the cell array region having a high step difference, the stopping layer  54  is removed when the CMP process is performed to some extent under the above-described conditions, and then the CMP process is performed faster than ever. When the CMP process is performed to some extent, the surface of the stopping layer in the periphery region is exposed. Since the stopping layer is formed wide in the periphery region, when the surface of the stopping layer is exposed, the CMP process is terminated and overall global planarization is provided. 
     The stopping layer of the periphery region may be completely removed by further performing the CMP process. 
     According to the method for manufacturing the globally planarized semiconductor device of the present invention, when a global step difference exists between the cell array region and the periphery region and the step difference is removed using a CMP process to attain global planarization, a stopping layer is formed which can suppress the CMP process on an interlevel dielectric layer. A SAC process is performed after forming the stopping layer, and a CMP process is performed after forming a pad conductive layer under the conditions that there is little selectivity between the interlevel dielectric layer and the conductive layer and the selectivity between these layers and the stopping layer is made large. Then, the stopping layer lowers a CMP progress rate for the periphery region, thereby providing global planarization between the cell array region and the periphery region by a single CMP process. Therefore, since the CMP process is performed just once, unlike the conventional process in which the CMP process is performed twice, the manufacturing process is simplified and productivity is improved. Also, several defects due to micro scratches being generated during the CMP process can be reduced.