Patent Publication Number: US-8533547-B2

Title: Continuous application and decompression of test patterns and selective compaction of test responses

Description:
RELATED APPLICATION DATA 
     This application is a continuation-in-part of U.S. patent application Ser. No. 12/891,498, filed on Sep. 27, 2010 now U.S. Pat. No. 8,108,743, which is a continuation of U.S. patent application Ser. No. 12/396,377, filed Mar. 2, 2009, now U.S. Pat. No. 7,805,649, which is a continuation of U.S. patent application Ser. No. 10/973,522, filed Oct. 25, 2004, now U.S. Pat. No. 7,500,163, which is a continuation of U.S. patent application Ser. No. 10/354,576, filed Jan. 29, 2003, now U.S. Pat. No. 6,829,740, which is a continuation of U.S. patent application Ser. No. 09/619,988, filed Jul. 20, 2000, now U.S. Pat. No. 6,557,129, which claims the benefit of U.S. Provisional Application No. 60/167,136, filed Nov. 23, 1999, all of which are hereby incorporated herein by reference. 
     This application is also a continuation-in-part of U.S. patent application Ser. No. 12/352,994, filed Jan. 13, 2009, now U.S. Pat. No. 7,877,656, which is a continuation of U.S. patent application Ser. No. 10/354,633, filed Jan. 29, 2003, now U.S. Pat. No. 7,478,296, which is a continuation of U.S. patent application Ser. No. 09/620,021, filed Jul. 20, 2000, now U.S. Pat. No. 7,493,540, which claims the benefit of U.S. Provisional Application No. 60/167,131, filed Nov. 23, 1999, all of which are hereby incorporated herein by reference. 
     This application is also a continuation-in-part of U.S. patent application Ser. No. 12/983,815, filed on Jan. 3, 2011 now abandoned, which is a continuation of U.S. patent application Ser. No. 12/402,880, filed Mar. 12, 2009, now U.S. Pat. No. 7,865,794, which is a continuation of U.S. patent application Ser. No. 11/502,655, filed Aug. 11, 2006, now U.S. Pat. No. 7,506,232, which is a continuation of U.S. patent application Ser. No. 10/736,966, filed Dec. 15, 2003, now U.S. Pat. No. 7,093,175, which is a continuation of U.S. patent application Ser. No. 09/713,664, filed Nov. 15, 2000, now U.S. Pat. No. 6,684,358, which claims the benefit of U.S. Provisional Application No. 60/167,137, filed Nov. 23, 1999, all of which are hereby incorporated herein by reference. 
     This application is also a continuation-in-part of U.S. patent application Ser. No. 11/894,393, filed on Aug. 20, 2007 now U.S. Pat. No. 8,024,387, which is a continuation of U.S. patent application Ser. No. 10/781,031, filed Feb. 17, 2004, now U.S. Pat. No. 7,260,591, which is a continuation U.S. patent application Ser. No. 10/346,699, filed Jan. 16, 2003, now U.S. Pat. No. 6,708,192, which is a continuation of U.S. patent application Ser. No. 09/957,701, filed Sep. 18, 2001, now U.S. Pat. No. 6,539,409, which is a continuation of U.S. patent application Ser. No. 09/620,023, filed Jul. 20, 2000, now U.S. Pat. No. 6,353,842, which claims the benefit of U.S. Provisional Application No. 60/167,445, filed Nov. 23, 1999, all of which are hereby incorporated herein by reference. 
     This application is also a continuation-in-part of U.S. patent application Ser. No. 12/405,409, filed on Mar. 17, 2009 now U.S. Pat. No. 7,900,104, which is a continuation of Ser. No. 11/523,111 filed Sep. 18, 2006, now U.S. Pat. No. 7,509,546, which is a continuation of U.S. patent application Ser. No. 10/355,941 filed Jan. 31, 2003, now U.S. Pat. No. 7,111,209, which is a continuation of U.S. patent application Ser. No. 09/947,160 filed Sep. 4, 2001, now U.S. Pat. No. 6,543,020, which is a continuation of U.S. patent application Ser. No. 09/619,985 filed Jul. 20, 2000, now U.S. Pat. No. 6,327,687, which claims the benefit of U.S. Provisional Application No. 60/167,446 filed Nov. 23, 1999, all of which are hereby incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     This invention relates generally to testing of integrated circuits and, more particularly, to the generation and application of test data in the form of patterns, or vectors, to scan chains within a circuit-under-test. This invention also relates generally to testing of integrated circuits and more particularly relates to compaction of test responses used in testing for faults in integrated circuits. 
     BACKGROUND 
     As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. This difficulty arises for several reasons. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. Second, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Third, applying the test data to a large circuit requires an increasingly long test application time. And fourth, present external testing equipment is unable to test such larger circuits at their speed of operation. 
     Integrated circuits are presently tested using a number of structured design for testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements like flip-flops and latches) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as testing of combinational faults is concerned, as a combinational network. The most-often used DFT methodology is based on scan chains. It assumes that during testing, all (or almost all) memory elements are connected into one or more shift registers, as shown in the U.S. Pat. No. 4,503,537. A circuit that has been designed for test has two modes of operation: a normal mode and a test, or scan, mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit, or test, responses to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit-under-test (CUT) works properly. 
     Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation (ATPG) and silicon debugging capabilities. Today, ATPG software tools are so efficient that it is possible to generate test sets (a collection of test patterns) that guarantee almost complete fault coverage of several types of fault models including stuck-at, transition, path delay faults, and bridging faults. Typically, when a particular potential fault in a circuit is targeted by an ATPG tool, only a small number of scan cells, e.g., 2-5%, must be specified to detect the particular fault (deterministically specified cells). The remaining scan cells in the scan chains are filled with random binary values (randomly specified cells). This way the pattern is fully specified, more likely to detect some additional faults, and can be stored on a tester. 
     Because of the random fill requirement, however, the test patterns are grossly over-specified. These large test patterns require extensive tester memory to store and a considerable time to apply from the tester to a circuit-under-test.  FIG. 1  is a block diagram of a conventional system  18  for testing digital circuits with scan chains. External automatic testing equipment (ATE), or tester,  20  applies a set of fully specified test patterns  22  one by one to a CUT  24  in scan mode via scan chains  26  within the circuit. The circuit is then run in normal mode using the test pattern as input, and the test response to the test pattern is stored in the scan chains. With the circuit again in scan mode, the response is then routed to the tester  20 , which compares the response with a fault-free reference response  28 , also one by one. For large circuits, this approach becomes infeasible because of large test set sizes and long test application times. It has been reported that the volume of test data can exceed one kilobit per single logic gate in a large design. The significant limitation of this approach is that it requires an expensive, memory-intensive tester and a long test time to test a complex circuit. 
     These limitations of time and storage can be overcome to some extent by adopting a built-in self-test (BIST) framework, as shown in the U.S. Pat. No. 4,503,537 and  FIG. 13 . In BIST, additional on-chip circuitry is included to generate test patterns, evaluate test responses, and control the test. For example, a pseudo-random pattern generator  121  is used to generate the test patterns, instead of having deterministic test patterns. Additionally, a multiple input signature register (MISR)  122  is used to generate and store a resulting signature from test responses. In conventional logic BIST, where pseudo-random patterns are used as test patterns, 95-96% coverage of stuck-at faults can be achieved provided that test points are employed to address random-pattern resistant faults. On average, one to two test points may be required for every 1000 gates. In BIST, all responses propagating to observable outputs and the signature register have to be known. Unknown values corrupt the signature and therefore must be bounded by additional test logic. Even though pseudo-random test patterns appear to cover a significant percentage of stuck-at faults, these patterns must be supplemented by deterministic patterns that target the remaining, random pattern resistant faults. Very often the tester memory required to store the supplemental patterns in BIST exceeds 50% of the memory required in the deterministic approach described above. Another limitation of BIST is that other types of faults, such as transition or path delay faults, are not handled efficiently by pseudo-random patterns. Because of the complexity of the circuits and the limitations inherent in BIST, it is extremely difficult, if not impossible, to provide a set of specified test patterns that fully covers hard-to-test faults. 
     Weighted pseudo-random testing is another method that is used to address the issue of the random pattern resistant faults. In principle, this approach expands the pseudo-random test pattern generators by biasing the probabilities of the input bits so that the tests needed for hard-to-test faults are more likely to occur. In general, however, a circuit may require a very large number of sets of weights, and, for each weight set, a number of random patterns have to be applied. Thus, although the volume of test data is usually reduced in comparison to fully specified deterministic test patterns, the resultant test application time increases. Moreover, weighted pseudo-random testing still leaves a fraction of the fault list left uncovered. Details of weighted random pattern test systems and related methods can be found in a number of references including U.S. Pat. Nos. 4,687,988; 4,801,870; 5,394,405; 5,414,716; and 5,612,963. Weighted random patterns have been primarily used as a solution to compress the test data on the tester. The generation hardware appears to be too complex to place it on the chip. Consequently, the voluminous test data is produced off-chip and must pass through relatively slow tester channels to the circuit-under-test. Effectively, the test application time can be much longer than that consumed by the conventional deterministic approach using ATPG patterns. 
     Several methods to compress test data before transmitting it to the circuit-under-test have been suggested. They are based on the observation that the test cubes (i.e., the arrangement of test patterns bits as they are stored within the scan chains of a circuit-under-test) frequently feature a large number of unspecified (don&#39;t care) positions. One method, known as reseeding of linear feedback shift registers (LFSRs), was first proposed in B. Koenemann, “LFSR-Coded Test Patterns For Scan Designs,”  Proc. European Test Conference , pp. 237-242 (1991). Consider an n-bit LFSR with a fixed polynomial. Its output sequence is then completely determined by the initial seed. Thus, applying the feedback equations recursively provides a system of linear equations depending only on the seed variables. These equations can be associated with the successive positions of the LFSR output sequence. Consequently, a seed corresponding to the actual test pattern can be determined by solving the system of linear equations, where each equation represents one of the specified positions in the test pattern. Loading the resultant seed into the LFSR and subsequently clocking it will produce the desired test pattern. A disadvantage of this approach, however, is that seed, which encodes the contents of the test cube, is limited to approximately the size of the LFSR. If the test cube has more specified positions than the number of stages in LFSR, the test cube cannot be easily encoded with a seed. Another disadvantage of this approach is the time it requires. A tester cannot fill the LFSR with a seed concurrently with the LFSR generating a test pattern from the seed. Each of these acts must be done at mutually exclusive times. This makes the operation of the tester very inefficient, i.e., when the seed is serially loaded to the LFSR the scan chains do not operate; and when the loading of the scan chains takes place, the tester cannot transfer a seed to the LFSR. 
     Another compression method is based on reseeding of multiple polynomial LFSRs (MP-LFSRs) as proposed in S. Hellebrand et al., “Built-In Test For Circuits With Scan Based On Reseeding of Multiple Polynomial Linear Feedback Shift Registers,”  IEEE Trans. On Computers , vol. C-44, pp. 223-233 (1995). In this method, a concatenated group of test cubes is encoded with a number of bits specifying a seed and a polynomial identifier. The content of the MP-LFSR is loaded for each test group and has to be preserved during the decompression of each test cube within the group. The implementation of the decompressor involves adding extra memory elements to avoid overwriting the content of the MP-LFSR during the decompression of a group of test patterns. A similar technique has been also discussed in S. Hellebrand et al., “Pattern generation for a deterministic BIST scheme,”  Proc. ICCAD , pp. 88-94 (1995). Reseeding of MP-LFSRs was further enhanced by adopting the concept of variable-length seeds as described in J. Rajski et al., “Decompression of test data using variable-length seed LFSRs”,  Proc. VLSI Test Symposium , pp. 426-433 (1995) and in J. Rajski et al., “Test Data Decompression for Multiple Scan Designs with Boundary Scan”,  IEEE Trans. on Computers , vol. C-47, pp. 1188-1200 (1998). This technique has a potential for significant improvement of test pattern encoding efficiency, even for test cubes with highly varying number of specified positions. The same documents propose decompression techniques for circuits with multiple scan chains and mechanisms to load seeds into the decompressor structure through the boundary-scan. Although this scheme significantly improves encoding capability, it still suffers from the two drawbacks noted above: seed-length limitations and mutually exclusive times for loading the seed and generating test patterns therefrom. 
     The above reseeding methods thus suffer from the following limitations. First, the encoding capability of reseeding is limited by the length of the LFSR. In general, it is very difficult to encode a test cube that has more specified positions than the length of the LFSR. Second, the loading of the seed and test pattern generation therefrom are done in two separate, non-overlapping phases. This results in poor utilization of the tester time. 
     A different attempt to reduce test application time and test data volume is described in I. Hamzaoglu et al., “Reducing Test Application Time For Full Scan Embedded Cores,”  Proc. FTCS -29, pp. 260-267 (1999). This so-called parallel-serial full scan scheme divides the scan chain into multiple partitions and shifts in the same test pattern to each scan chain through a single scan input. Clearly, a given test pattern must not contain contradictory values on corresponding cells in different chains loaded through the same input. Although partially specified test cubes may allow such operations, the performance of this scheme strongly relies on the scan chain configuration, i.e., the number of the scan chains used and the assignment of the memory elements to the scan chains. In large circuits such a mapping is unlikely to assume any desired form, and thus the solution is not easily scalable. Furthermore, a tester using this scheme must be able to handle test patterns of different scan chain lengths, a feature not common to many testers. 
     Further, some of the DFT techniques include compactors to compress the test responses from the scan chains. There are generally two types of compactors: time compactors and spatial compactors. Time compactors typically have a feedback structure with memory elements for storing a signature, which represents the results of the test. After the signature is completed it is read and compared to a fault-free signature to determine if an error exists in the integrated circuit. Spatial compactors generally compress a collection of bits (called a vector) from scan chains. The compacted output is analyzed in real time as the test responses are shifted out of the scan chains. Spatial compactors can be customized for a given circuit under test to reduce the aliasing phenomenon, as shown in the U.S. Pat. No. 5,790,562 and in few other works based on multiplexed parity trees or nonlinear trees comprising elementary gates such as AND, OR, NAND, and NOR gates. 
     Linear spatial compactors are built of Exclusive-OR (XOR) or Exclusive-NOR (XNOR) gates to generate n test outputs from the m primary outputs of the circuit under test, where n&lt;m. Linear compactors differ from nonlinear compactors in that the output value of a linear compactor changes with a change in just one input to the compactor. With nonlinear compactors, a change in an input value may go undetected at the output of the compactor. However, even linear compactors may mask errors in an integrated circuit. For example, the basic characteristic an XOR (parity) tree is that any combination of odd number of errors on its inputs propagates to their outputs, and any combination of even number of errors remains undetected. 
     An ideal compaction algorithm has the following features: (1) it is easy to implement as a part of the on-chip test circuitry, (2) it is not a limiting factor with respect to test time, (3) it provides a logarithmic compression of the test data, and (4) it does not lose information concerning faults. In general, however, there is no known compaction algorithm that satisfies all the above criteria. In particular, it is difficult to ensure that the compressed output obtained from a faulty circuit is not the same as that of the fault-free circuit. This phenomenon is often referred to as error masking or aliasing and is measured in terms of the likelihood of its occurrence. An example of error masking occurs when the spatial compactor reads two fault effects at the same time. The multiple fault effects cancel each other out and the compactor output is the same as if no faults occurred. 
     Unknown states are also problematic for error detection. An unknown state on one or more inputs of an XOR tree generates unknown values on its output, and consequently masks propagation of faults on other inputs. A common application of space compactors is to combine the observation points inserted into the CUT as a part of design-for-testability methodology. The spatial compactors can be also used to reduce the size of the time compactors by limiting the number of their parallel inputs. 
     Undoubtedly, the most popular time compactors used in practice are linear feedback shift registers (LFSRs). In its basic form, the LFSR (see  FIG. 14 ) is modified to accept an external input in order to act as a polynomial divider. An alternative implementation (called type II LFSR) is shown in  FIG. 15 . The input sequence, represented by a polynomial, is divided by the characteristic polynomial of the LFSR. As the division proceeds, the quotient sequence appears at the output of the LFSR and the remainder is kept in the LFSR. Once testing is completed, the content of the LFSR can be treated as a signature. 
       FIG. 16  shows another time compactor (which is a natural extension of the LFSR-based compactor) called a multiple-input LFSR, also known as a multiple-input signature register (MISR). The MISR is used to test circuits in the multiple scan chain environment such as shown in the U.S. Pat. No. 4,503,537. MISRs feature a number of XOR gates added to the flip-flops. The CUT scan chain outputs are then connected to these gates. 
       FIG. 17  shows an example of a pipelined spatial compactor with a bank of flip-flops separating stages of XOR gates. A clock (not shown) controls the flip-flops and allows a one-cycle delay before reading the compacted output. 
     The limitation of spatial compactors, such as the one shown in  FIG. 17 , is that unknown states can reduce fault coverage. Time compactors, such as shown in  FIGS. 14 ,  15 , and  16 , are completely unable to handle unknown states since an unknown state on any input can corrupt the compressed output generated by the compactor. With both time compactors and spatial compactors, multiple fault effects can reduce fault coverage. Additionally, if a fault effect is detected within the integrated circuit, these compactors have limited ability to localize the fault. 
     An object of the invention, therefore, is to provide an efficient compactor that can select which scan chains are analyzed. This ability to select allows the compactor to generate a valid compressed output even when receiving unknown states or multiple fault effects on its inputs. The compactor can also be used diagnostically to determine the location of faults within an integrated circuit. 
     SUMMARY 
     A method according to the invention for applying test patterns to scan chains in a circuit-under-test includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. If desired, the method may further include applying the decompressed test pattern to scan chains of the circuit-under-test as the compressed test pattern is being provided. 
     The method may also include providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern synchronously. These acts may be performed at a same clock rate. Alternatively, the compressed test pattern may be provided at a lower clock rate and the compressed test pattern decompressed and applied at a higher clock rate. In yet another alternative, the compressed pattern may be provided and decompressed at a higher clock rate and the decompressed pattern applied at a lower clock rate. 
     Decompressing the compressed test pattern may comprise generating during a time period a greater number of decompressed test pattern bits than the number of compressed test pattern bits provided during the same time period. One way the greater number of bits may be generated is by providing a greater number of outputs for decompressed test pattern bits than the number of inputs to which the compressed test pattern bits are provided. Another way the greater number of bits may be generated is by generating the decompressed test pattern bits at a higher clock rate than the clock rate at which the compressed test pattern bits are provided. 
     Decompressing the compressed test pattern may further comprise generating each bit of the decompressed pattern by logically combining two or more bits of the compressed test pattern. This logically combining may include combining the bits with an XOR operation, an XNOR operation or a combination of the two operations. 
     In one embodiment of the invention, the providing and decompressing occur within the circuit-under-test. In another embodiment of the invention, the providing and decompressing occur within a tester, the tester applying the decompressed test pattern to scan chains of the circuit-under-test. 
     A circuit according to the invention may comprise a decompressor, circuit logic, and scan chains for testing the circuit logic. The decompressor is adapted to receive a compressed test pattern of bits and decompress the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The scan chains are coupled to the decompressor and are adapted to receive the decompressed test pattern. The decompressor may comprise a linear finite state machine adapted to receive the compressed test pattern. 
     A tester according to the invention may comprise storage, a decompressor, and one or more tester channels. The storage is adapted to store a set of compressed test patterns of bits. The decompressor is coupled to the storage and adapted to receive a compressed test pattern of bits provided from the storage and to decompress the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The tester channels are coupled to the decompressor and adapted to receive a decompressed test pattern and apply the decompressed test pattern to a circuit-under-test. 
     In another embodiment, a compactor is disclosed that selects test responses in one or more scan chains to compact into a compressed output, while one or more other test responses are masked. Thus, test responses containing unknown states may be masked to ensure that the compactor generates a valid compressed output. Additionally, test responses can be masked to ensure fault masking does not occur. The compactor can also analyze test responses from individual scan chains to diagnostically localize faults in an integrated circuit. 
     A compactor includes selection circuitry that controls which scan chains are analyzed. The selection circuitry passes desired test responses from scan chains onto a compactor, while masking other test responses. In one embodiment, the selection circuitry may include an identification register that is loaded with a unique identifier of a scan chain. Based on the state of a flag register, either only the test response stored within the scan chain identified is passed to the compactor or all test responses are passed to the compactor except the test response associated with the identified scan chain. 
     In another embodiment, the selection circuitry includes a flag that controls whether only selected test responses are compacted or whether all test responses are compacted. 
     In yet another embodiment, a control register is used that individually identifies each scan chain included in compaction. In this embodiment, a variable number (e.g., 1, 2, 3, 4 . . . ) of test responses within scan chains may be included in compaction. Alternatively, the control register may store a unique identifier that is decoded to select one test response that is compacted. 
     In still another embodiment, the selection circuitry includes a control line that masks bits from scan chains on a per clock-cycle basis. Consequently, a test response may have only individual bits masked while the remaining bits of the test response are compacted. 
     These and other aspects and features of the invention are described below with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a conventional system for testing digital circuits with scan chains. 
         FIG. 2  is a block diagram of a test system according to the invention for testing digital circuits with scan chains. 
         FIG. 3  is a block diagram of a second embodiment of a system according to the invention for testing digital circuits with scan chains. 
         FIGS. 4A-B  are block diagrams of a test system according to the invention include timing diagrams illustrating different possible timing relationships possible between the components of the system. 
         FIG. 5  is a block diagram of a decompressor according to the invention, including a linear finite state machine (LFSM) and phase shifter. 
         FIG. 6  shows in more detail a first embodiment of the decompressor of  FIG. 5  coupled to a scan chain. 
         FIG. 7  shows the logical expressions for the bits stored in each scan cell in the scan chain of  FIG. 5   
         FIGS. 8A-8D  illustrate alternative embodiments of the LFSM of  FIG. 5 . 
         FIG. 9  illustrates a preferred embodiment of a 32-bit LFSM 
         FIG. 10  illustrates an alternative embodiment of the phase shifter of  FIG. 5 . 
         FIG. 11  illustrates the use of parallel-to-serial conversion for applying a compressed test pattern to the decompressor. 
         FIG. 12  is a block diagram of a tester according to the invention for testing digital circuits with scan chains. 
         FIG. 13  is a block diagram of a prior art system using a built-in-test system. 
         FIG. 14  is a circuit diagram of a prior art type I LFSR compactor. 
         FIG. 15  is a circuit diagram of a prior art type II LFSR compactor. 
         FIG. 16  is a circuit diagram of a prior art architecture of a multiple input signature register (MISR) compactor shown receiving input from scan chains. 
         FIG. 17  is a circuit diagram of a prior art pipelined spatial compactor. 
         FIG. 18  is a block diagram of a selective compactor according to the invention. 
         FIG. 19  shows one embodiment of a selective compactor, including selection circuitry and a spatial compactor, for masking test responses from scan chains. 
         FIG. 20  is another embodiment of a selective compactor including selection circuitry and a time compactor for masking test responses from scan chains. 
         FIG. 21  is yet another embodiment of a selective compactor including selection circuitry and a cascaded compactor for masking individual bits of test responses from scan chains. 
         FIG. 22  is another embodiment of a selective compactor including selection circuitry and multiple compactors for masking test responses. 
         FIG. 23  is another embodiment of a selective compactor with selection circuitry that masks any variable number of test responses from the scan chains. 
         FIG. 24  is another embodiment of a selective compactor with programmable selection of scan chains. 
         FIG. 25  is a flowchart of a method for selectively compacting test responses from scan chains. 
     
    
    
     DETAILED DESCRIPTION 
     Continuous Application and Decompression of Test Patterns to a Circuit-Under-Test 
       FIG. 2  is a block diagram of a system  30  according to the invention for testing digital circuits with scan chains. The system includes a tester  21  such as external automatic testing equipment (ATE) and a circuit  34  that includes as all or part of it a circuit-under-test (CUT)  24 . The tester  21  provides from storage a set of compressed test patterns  32  of bits, one pattern at a time, through tester channels  40  to the circuit  34  such as an IC. A compressed pattern, as will be described, contains far fewer bits than a conventional uncompressed test pattern. A compressed pattern need contain only enough information to recreate deterministically specified bits. Consequently, a compressed pattern is typically 2% to 5% of the size of a conventional test pattern and requires much less tester memory for storage than conventional patterns. As importantly, compressed test patterns require much less time to transmit from a tester to a CUT  24 . 
     Unlike in the prior reseeding techniques described above, the compressed test patterns  32  are continuously provided from the tester  21  to scan chains  26  within the CUT  24  without interruption. As the compressed test pattern is being provided by the tester  21  to the input channels of a decompressor  36  within the circuit  34 , the decompressor decompresses the compressed pattern into a decompressed pattern of bits. The decompressed test pattern is then applied to the scan chains  26 . This application is preferably done while the compressed test pattern is being provided to the circuit  34 , but it need not be so. After circuit logic within the CUT  24  is clocked with a decompressed test pattern in the scan chains  26 , the test response to that pattern is captured in the scan chains and transmitted to the tester  21  for comparison with the compressed fault-free reference responses  41  stored therein. 
     In a typical configuration, the decompressor  36  has one output per scan chain  26 , and there are more scan chains than input channels to the decompressor. However, as will be described, other configurations are also possible in which the decompressor outputs are fewer than or equal to the input channels. The decompressor generates in a given time period a greater number of decompressed bits at its outputs than the number of compressed pattern bits it receives during the same time period. This is the act of decompression, whereby the decompressor  36  generates a greater number of bits than are provided to it in a given time period. 
     To reduce the data volume of the test response and the time for sending the response to the tester, the circuit  34  can include means for compressing the test response that is read from the scan chains  26 . One structure for providing such compression is one or more spatial compactors  38 . The compressed test responses produced by the compactors  38  are then compared one by one with compressed reference responses  40 . A fault is detected if a reference response does not match an actual response.  FIG. 3  shows another structure that can be used for compressing the test response. A multiple input signature register (MISR)  42  compresses multiple test pattern responses into a signature that is then sent to the tester. There it is compared to a reference signature  44 . Compacting the test response in the above ways is desirable but not necessary to the present decompression method and system. 
     The providing of a compressed test pattern to a circuit, its decompression into a decompressed test pattern, and the application of the decompressed test pattern to the scan chains is performed synchronously, continuously, and substantially concurrently. The rate at which each act occurs, however, can vary. All acts can be performed synchronously at a same clock rate if desired. Or the acts can be performed at different clock rates. If the acts are performed at the same clock rate, or if the compressed test patterns are provided and decompressed at a higher clock rate than at which the decompressed test patterns are applied to the scan chains, then the number of outputs of decompressor  36  and associated scan chains will exceed the number of input channels of the decompressor, as in  FIG. 2 . In this first case, decompression is achieved by providing more decompressor outputs than input channels. If the compressed test patterns are provided at a lower clock rate and decompressed and applied to the scan chains at a higher clock rate, then the number of outputs and associated scan chains can be the same, fewer, or greater than the number of input channels. In this second case, decompression is achieved by generating the decompressed test pattern bits at a higher clock rate than the clock rate at which the compressed test pattern bits are provided. 
       FIG. 4A  illustrates an embodiment of the first case in which the compressed pattern is provided and decompressed at a higher clock rate and the decompressed pattern is applied synchronously to the scan chains at a lower clock rate. The tester  21  provides the bits of the compressed pattern through a tester channel  40  to an input channel  37  of the decompressor  36  at a higher rate set by clock  0  (C 0 ). The decompressor is clocked by clock  1  (C 1 ) at the same rate as the tester and produces at outputs  39  the bits of the decompressed pattern at that rate. These decompressed bits, however, are applied to the scan chains  26  at a lower rate set by clock  2  (C 2 ), which clocks the bits into the scan chains. This difference in rates is illustrated in the exemplary timing diagram in  FIG. 4A  (the actual difference can be much greater). Because of the difference therein, only every other output of the decompressor is written to the scan chains. But that is taken into account in the initial test pattern generation. One advantage of clocking the tester, decompressor, and scan chains as shown is that the tester requires fewer channels than the number of scan chains to provide the test pattern to the CUT  24 . By clocking the tester at a higher clock rate C 0 , the time required to apply the compressed test pattern to the circuit  34  is significantly reduced. Another advantage is in low power applications, where the power dissipated during test mode has to be controlled. This can be done by reducing the clock rate C 2  at which bits are shifted into the scan chains. 
       FIG. 4B  illustrates an embodiment of the second case in which the compressed test pattern is provided at a lower clock rate and decompressed and applied synchronously at a higher clock rate. Here, the tester  21  provides the bits of the compressed pattern through channels  40  to the input channels  37  of the decompressor  36  at a lower rate set by clock  0  (C 0 ). The decompressor is clocked by clock  1  (C 1 ) at a higher rate. The decompressed bits are applied through its outputs  39  to the scan chains  26  by clock  2  (C 2 ) at the same rate as clock  1 . This difference in rates is illustrated in the exemplary timing diagram in  FIG. 4B  (the actual difference can be much greater). Because of the difference, the decompressor  36  reads the same bits from the tester  21  twice before they change. The decompressor, however, includes a state machine, as will be described, and its outputs change each clock cycle because its internal states change. One advantage of clocking the tester, decompressor, and scan chains as shown in  FIG. 4B  is that one can utilize a tester  21  that has many channels but with little memory behind them. By providing bits on more tester channels per clock cycle, the lack of memory depth is overcome and the time required for applying the compressed test pattern is reduced. 
       FIG. 5  is a block diagram of a decompressor according to the invention. In a preferred embodiment, decompressor  36  comprises a linear finite state machine (LFSM)  46  coupled, if desired, through its taps  48  to a phase shifter  50 . The LFSM through the phase shifter provides highly linearly independent test patterns to the inputs of numerous scan chains in the CUT  24 . The LFSM can be built on the basis of the canonical forms of linear feedback shift registers, cellular automata, or transformed LFSRs that can be obtained by applying a number of m-sequence preserving transformations. The output of the LFSM is applied to the phase shifter, which ensures that the decompressed pattern bits present within each of the multiple scan chains  26  at any given time do not overlap in pattern (i.e., are out of phase). 
     The concept of continuous flow decompression described herein rests on the fact noted above that deterministic test patterns typically have only between 2 to 5% of bits deterministically specified, with the remaining bits randomly filled during test pattern generation. (Test patterns with partially specified bit positions are called test cubes, an example of which appears in Table 2.) These partially specified test cubes are compressed so that the test data volume that has to be stored externally is significantly reduced. The fewer the number of specified bits in a test cube, the better is the ability to encode the information into a compressed pattern. The ability to encode test cubes into a compressed pattern is exploited by having a few decompressor input channels driving the circuit-under-test, which are viewed by the tester as virtual scan chains. The actual CUT  24 , however, has its memory elements connected into a large number of real scan chains. Under these circumstances, even a low-cost tester that has few scan channels and sufficiently small memory for storing test data can drive the circuit externally. 
       FIG. 6  shows in more detail a first embodiment of the decompressor of  FIG. 5 . The LFSM is embodied in an eight stage Type 1 LFSR  52  implementing primitive polynomial h(x)=x 8 +x 4 +x 3 +x 2 +1. The phase shifter  50 , embodied in a number of XOR gates, drives eight scan chains  26 , each eight bits long. The structure of the phase shifter is selected in such a way that a mutual separation between its output channels C 0 -C 7  is at least eight bits, and all output channels are driven by 3-input (tap) XOR functions having the following forms: 
                                 TABLE 1                          C 0  = s 4  ⊕ s 3  ⊕ s 1     C 4  = s 4  ⊕ s 2  ⊕ s 1             C 1  = s 7  ⊕ s 6  ⊕ s 5     C 5  = s 5  ⊕ s 2  ⊕ s 0             C 2  = s 7  ⊕ s 3  ⊕ s 2     C 6  = s 6  ⊕ s 5  ⊕ s 3             C 3  = s 6  ⊕ s 1  ⊕ s 0     C 7  = s 7  ⊕ s 2  ⊕ s 0                          
where C i  is the ith output channel and s k  indicates the kth stage of the LFSR. Assume that the LFSR is fed every clock cycle through its two input channels  37   a ,  37   b  and input injectors  48   a ,  48   b  (XOR gates) to the second and the sixth stages of the register. The input variables “a” (compressed test pattern bits) received on channel  37   a  are labeled with even subscripts (a 0 , a 2 , a 4 , . . . ) and the variables “a” received on channel  37   b  are labeled with odd subscripts (a 1 , a 3 , a 5 , . . . ). Treating these external variables as Boolean, all scan cells can be conceptually filled with symbolic expressions being linear functions of input variables injected by tester  21  into the LFSR  52 . Given the feedback polynomial, the phase shifter  50 , the location of injectors  48   a, b  as well as an additional initial period of four clock cycles during which only the LFSR is supplied by test data, the contents of each scan cell within the scan chains  26  in  FIG. 6  can be logically determined.  FIG. 7  gives the expressions for the 64 scan cells in  FIG. 6 , with the scan chains numbered 0 through 7 in  FIG. 6  corresponding to the scan chains C 7 , C 1 , C 6 , . . . identified in  FIG. 6 . The expressions for each scan chain in  FIG. 7  are listed in the order in which the information is shifted into the chain, i.e., the topmost expression represents the data shifted in first.
 
     Assume that the decompressor  36  in  FIG. 6  is to generate a test pattern based on the following partially specified test cube in Table 2 (the contents of the eight scan chains are shown here horizontally, with the leftmost column representing the information that is shifted first into the scan chains): 
                                 TABLE 2                          x x x x x x x x   scan chain 0           x x x x x x x x   scan chain 1           x x x x 1 1 x x   scan chain 2           x x 0 x x x 1 x   scan chain 3           x x x x 0 x x 1   scan chain 4           x x 0 x 0 x x x   scan chain 5           x x 1 x 1 x x x   scan chain 6           x x x x x x x x   scan chain 7                        
The variable x denotes a “don&#39;t care” condition. Then a corresponding compressed test pattern can be determined by solving the following system of ten equations from  FIG. 7  using any of a number of well-known techniques such as Gauss-Jordan elimination techniques. The selected equations correspond to the deterministically specified bits:
 
                     TABLE 3                  a 2  ⊕ a 6  ⊕ a 11  = 1       a 0  ⊕ a 1  ⊕ a 4  ⊕ a 8  ⊕ a 13  = 1       a 4  ⊕ a 5  ⊕ a 9  ⊕ a 11  = 0       a 0  ⊕ a 2  ⊕ a 5  ⊕ a 12  ⊕ a 13  ⊕ a 17  ⊕ a 19  = 1       a 1  ⊕ a 2  ⊕ a 4  ⊕ a 5  ⊕ a 6  ⊕ a 8  ⊕ a 12  ⊕ a 15  = 0       a 0  ⊕ a 1  ⊕ a 3  ⊕ a 5  ⊕ a 7  ⊕ a 8  ⊕ a 10  ⊕ a 11  ⊕ a 12  ⊕ a 14  ⊕ a 18  ⊕ a 21  = 1       a 2  ⊕ a 3  ⊕ a 4  ⊕ a 9  ⊕ a 10  = 0       a 0  ⊕ a 1  ⊕ a 2  ⊕ a 6  ⊕ a 7  ⊕ a 8  ⊕ a 13  ⊕ a 14  = 0       a 3  ⊕ a 4  ⊕ a 5  ⊕ a 6  ⊕ a 10  = 1       a 0  ⊕ a 1  ⊕ a 3  ⊕ a 7  ⊕ a 8  ⊕ a 9  ⊕ a 10  ⊕ a 14  = 1                    
It can be verified that the resulting seed variables a 0 , a 1 , a 2 , a 3  and a 13  are equal to the value of one while the remaining variables assume the value of zero. This seed will subsequently produce a fully specified test pattern in the following form (the initial specified positions are underlined):
 
                                                         TABLE 4                          1   0   1   0   0   1   0   0           1   1   0   0   0   1   0   0           1   1   1   1     1       1     1   0           0   0     0     1   0   0     1     1           1   0   1   0     0     0   0     1             1   1     0     1     0     0   0   0           1   1     1     1     1     1   1   1           0   1   0   0   1   1   0   0                        
As can be observed, the achieved compression ratio (defined as the number of scan cells divided by the number of compressed pattern bits) is 64/(2×8+2×4)≈2.66. The fully specified test pattern is then compressed into a compressed pattern of bits using any of a number of known methods.
 
       FIGS. 8A-D  illustrate various embodiments for the LFSM  46  of  FIG. 5 .  FIG. 8A  is a Type I LFSR  60 .  FIG. 8B  is a Type II LFSR  62 .  FIG. 8C  is a transformed LFSR  64 . And  FIG. 8D  is a cellular automaton  66 . All of them implement primitive polynomials. Except for the cellular automaton  66 , in each case the LFSM includes a number of memory elements connected in a shift register configuration. In addition, there are several feedback connections between various memory cells that uniquely determine the next state of the LFSM. The feedback connections are assimilated into the design by introducing injectors in the form of XOR gates near the destination memory elements. The input channels  37  provide the bits of a compressed pattern to the LFSM through input injectors  48   a, b . The injectors are handled similarly as the other feedback connections within the LFSM except that their sources of bits are the input channels. The input channels  37  may have multiple fan-outs driving different LFSM injectors  48  to improve the encoding efficiency. 
       FIG. 9  shows a preferred embodiment of a 32-bit LFSM in the form of a re-timed LFSR  68 . The injectors are spaced equally so that the input variables are distributed optimally once they are injected into the LFSM. In practice, the size of the LFSM depends on the number of real scan chains in a circuit, the desired compression ratio of encoding, and on certain structural properties of the circuit-under-test. 
       FIG. 10  illustrates an alternative embodiment of a phase shifter  50 , constructed with an array of XNOR gates rather than XOR gates. Phase shifters can be constructed with combinations of XNOR and XOR gates as well. 
       FIG. 11  illustrates the use of parallel-to-serial conversion for applying a compressed test pattern to the decompressor. If the input channels  37  to the decompressor  36  are fewer in number than the number of channels  40  of the tester  21 , it can be advantageous to provide a parallel-to-serial converter such as registers  70  at the input to the decompressor. The registers  70  are clocked such that their contents are shifted out before the next set of bits is applied to the register from the tester  21 . The continuous flow of the test patterns is thus preserved. 
       FIG. 12  is a block diagram of a tester  21  embodiment that includes the decompressor  36 , rather than providing it in the circuit  34 . The tester decompresses the test pattern internally and transmits the decompressed test pattern to the CUT  24 . Such a tester has advantages where testing time is not as critical and it is preferred not to add a decompressor to each circuit-under-test. Storage requirements are still reduced because compressed test patterns (rather than full test patterns) need only be stored. In addition, in a variation of the above tester embodiment, the compactors  38  can also be included in the tester  21  rather than the circuit  34 . The circuit then returns uncompressed test responses to the tester. This further simplifies the circuit&#39;s design. 
     The process of decompressing a test pattern will now be described in more detail, with reference to  FIG. 5 . The LFSM  46  starts its operation from an initial all-zero state. Assuming an n-bit LFSM and m input injectors, ┌n/m┐ clock cycles may be used to initialize the LFSM before it starts generating bits corresponding to the actual test patterns. After initialization of the LFSM and assuming clocks C 0  and C 1  are running at the same rate, a new bit is loaded in parallel into each scan chain  26  every clock cycle via the phase shifter  50 . At this time, the circuit-under-test  34  is operated in the scan mode, so that the decompressed test pattern fills the scan chains  26  with 0s and 1s (and shifts out any previous test response stored there). A small number of bit positions in the scan chains, therefore, get deterministically specified values while the remaining positions are filled with random bits generated by the LFSM. The number of clock cycles for which a test pattern is shifted is determined by the length of the longest scan chain within the circuit, the number being at least as great as the number of cells in the longest scan chain. A scan-shift signal is therefore held high for all the scan chains until the longest scan chain gets the entire test pattern. The shorter scan chains in the circuit are left justified so that the first few bits that are shifted are overwritten without any loss of information. 
     Patterns from the LFSM may be linearly dependent. In other words, it is possible to determine various bit positions within the two-dimensional structure of multiple scan chains that are significantly correlated. This causes testability problems, as it is often not possible to provide the necessary stimulus for fault excitation to the gates driven by positions that have some form of dependency between them. Consequently, the phase shifter  50  (such as an array of XOR gates or XNOR gates) may be employed at the taps (outputs) of the LFSM to reduce linear dependencies between various bit positions within the scan chains. The XOR logic can be two-level or multi-level depending on the size of the XOR gates. Every scan chain in the CUT  24  is driven by signals that are obtained by XOR-ing a subset of taps  48  from the LFSM. These taps are determined so that the encoding efficiency of the test cubes is still preserved. In addition, the taps are selected in a manner so that all memory cells in the LFSM have approximately equal number of fan-out signals and the propagation delays are suitably optimized. Once a decompressed test pattern is completely loaded into the scan chains during test mode, the CUT  24  is switched to the normal mode of operation. The CUT then performs its normal operation under the stimulus provided by the test pattern in the scan chains. The test response of the CUT is captured in the scan chains. During the capture the LFSM is reset to the all-zero state before a new initialization cycle begins for loading the next test pattern. 
     Selectively Compacting Test Responses 
       FIG. 18  shows a block diagram of an integrated circuit  124  that includes multiple scan chains  126  in a circuit under test  128 . A selective compactor  130  is coupled to the scan chains  126  and includes a selector circuit  132  and a compactor  136 . The illustrated system is a deterministic test environment because the scan chains  126  are loaded with predetermined test patterns from an ATE (not shown). The test patterns are applied to the core logic of the integrated circuit to generate test responses, which are also stored in the scan chains  126  (each scan chain contains a test response). The test responses contain information associated with faults in the core logic of the integrated circuit  124 . Unfortunately, the test responses may also contain unknown states and/or multiple fault effects, which can negatively impact the effective coverage of the test responses. For example, if a memory cell is not initialized, it may propagate an unknown state to the test response. The test responses are passed to the selector circuit  132  of the selective compactor  130 . The selector circuit  132  includes control logic  134  that controls which of the test responses are passed through the selector circuit to the compactor  136 . The control logic  134  can control the selector circuit  132  such that test responses with unknown states or multiple fault effects are masked. The control logic is controlled by one or more control lines. Although not shown, the control lines may be connected directly to a channel of an ATE or they may be connected to other logic within the integrated circuit. For example, the control lines may be coupled to a Linear Finite State Machine (e.g., LSFR type 1, LSFR type 2, cellular automata, etc.) in combination with a phase shifter. The compactor  136  receives the desired test responses from the selector circuit  132  and compacts the responses into a compressed output for analysis. The compressed output is compared against a desired output to determine if the circuit under test contains any faults. The selection circuitry, compactor, and circuit under test are all shown within a single integrated circuit. However, the selection circuitry and compactor may be located externally of the integrated circuit, such as within the ATE. 
       FIG. 19  shows one example of an integrated circuit  140  that includes a selective compactor  142  coupled to multiple scan chains  144  within a circuit under test. Although only 8 scan chains are shown, the test circuit  140  may contain any number of scan chains. The selective compactor  142  includes a selector circuit  146  and a compactor  148 . The compactor  148  is a linear spatial compactor, but any conventional parallel test-response compaction scheme can be used with the selector circuit  146 , as further described below. The selector circuit  146  includes control logic  150 , which includes an input register  152 , shown in this example as a shift register. The input register  152  has a clock input  154  and a data input  156 . Each cycle of a clock on the clock input  154 , data from data input  156  shifts into the input register  152 . The register  152  has multiple fields including a scan identification field  158 , a “one/not one” field  160  and a “not all/all” field  162 . A control register  164  has corresponding bit positions to input register  152 , and upon receiving an update signal on an update line  166 , the control register  164  loads each bit position from input register  152  in parallel. Thus, the control register  164  also contains fields  158 ,  160 , and  162 . Although the control register  164  is shown generically as a shift register, the update line  166  is actually a control line to a multiplexer (not shown) that allows each bit position in register  164  to reload its own data on each clock cycle when the update line deactivated. When the update line is activated, the multiplexer passes the contents of register  152  to corresponding bit positions of the control register  164 . The control register  164  is then loaded synchronously with the clock. 
     The selector circuit  146  includes logic gates, shown generally at  168 , coupled to the control register  164 . The logic gates  168  are responsive to the different fields  158 ,  160 ,  162  of the control register  164 . For example, the scan identification field  158  contains a sufficient number of bits to uniquely identify any of the scan chains  144 . The scan identification field  158  of the control register  164  is connected to a decoder, shown at  170  as a series of AND gates and inverters. The decoder  170  provides a logic one on a decoder output depending on the scan identification field, while the other outputs of the decoder are a logic zero. 
     The one/not one field  160  of the control register  164  is used to either pass only one test response associated with the scan chain identified in the scan identification field  158  or pass all of the test responses except for the scan chain identified in the scan identification field. The all/not all field  162  is effectively an override of the other fields. In particular, field  162  controls whether all of the test responses in the scan chains  144  are passed to the compactor  148  or only the test responses as controlled by the scan identification field  158  and the one/not one field  160 . With field  162  cleared, only test responses as controlled by the scan identification field  158  and field  160  pass to the compactor  148 . Conversely, if the field  162  is set to a logic one, then all of the test responses from all of the scan chains  144  pass to the compactor  148  regardless of the scan identification field  58  and the one/not one field  160 . 
       FIG. 20  shows another embodiment of a selective compactor  180  that is coupled to scan chains  182 . The selective compactor includes a selector circuit  184 , which is identical to the selector circuit  146  described in relation to  FIG. 19 . The selective compactor  180  also includes a time compactor  184 , which is well understood in the art to be a circular compactor. The time compactor includes multiple flip-flops  186  and XOR gates  188  coupled in series. A reset line  190  is coupled to the flip-flops  186  to reset the compactor  184 . The reset line may be reset multiple times while reading the scan chains. Output register  192  provides a valid output of the compactor  84  upon activation of a read line  194 . 
     Referring to both  FIGS. 19 and 20 , in operation the scan chains  182  are serially loaded with predetermined test patterns by shifting data on scan channels (not shown) from an ATE (not shown). Simultaneously, the input register  152  is loaded with a scan identification and the controlling flags in fields  160 ,  162 . The test patterns in the scan chains  144 ,  182  are applied to the circuit under test and test responses are stored in the scan chains. Prior to shifting the test responses out of the scan chains, the update line  166  is activated, thus moving fields  158 ,  160 ,  162  to the control register  164 . The control register thereby controls the logic gates  168  to select the test responses that are passed to the compactors  148 ,  184 . If the field  162  is in a state such that selection is not overridden, then certain of the test responses are masked. In the example of  FIG. 19 , the spatial compactor  148  provides the corresponding compressed output serially and simultaneously with shifting the test responses out of the scan chains. Conversely, in  FIG. 20  the selective compactor  180  does not provide the appropriate compressed output until the read line  194  is activated. The selective compactor  180  provides a parallel compressed output as opposed to serial. The selective compactor  180  may be read multiple times (e.g., every eighth clock cycle) while reading out the test responses. 
       FIG. 21  shows another embodiment of a selective compactor  200 . Again, the selective compactor includes a selector circuit  202  and a compactor  204 . The compactor  204  is a type of spatial compactor called a cascaded compactor. N scan chains  206  include M scan cells  208 , each of which stores one bit of the test response. The selector circuit  202  includes logic gates  210 , in this case shown as AND gates, coupled to a control line  212 . The compactor  204  is a time compactor with a single serial output  214 . The control line  212  is used to mask the test responses. In particular, the control line  212  either masks all corresponding scan cells in the scan chains or allows all of the scan cells to pass to the compactor  180 . The control line  212  operates to mask each column of scan cells, rather than masking an entire scan chain. Thus, individual bits from any scan chain can be masked on a per clock-cycle basis and the remaining bits of that scan chain applied to the compactor  204 . With control line  212  activated, all bits from the scan chains pass to the compactor. With control line  212  deactivated, all bits from the scan chains are masked. Although  FIG. 21  shows only a single control line, additional control lines can be used to mask different groups of scan chains. Additionally, although control line  212  is shown as active high, it may be configured as active low. 
       FIG. 22  shows yet another embodiment of the selective compactor  220 . Automated test equipment  222  provides test patterns to the scan chains  224 . The scan chains  224  are a part of the circuit under test  226 . The patterns that are loaded into the scan chains  224  by the ATE are used to detect faults in the core logic of the circuit  226 . The test responses are stored in the scan chains  224  and are clocked in serial fashion to the selective compactor  220 . The selective compactor includes a selector circuit  228  and a compactor  230 . The selector circuit  228  includes control logic including an input register  232 , multiple control registers  234 ,  236 , and multiple decoders  237  and  239 . The register  232  is loaded with a pattern of bits that are moved to the control registers  234 ,  236  upon activation of an update line (not shown). The control registers  234 ,  236  are read by the decoders  237  and  239  and decoded to select one or more logic gates  238 . A flag  240  is used to override the decoders  237  and  239  and pass all of the test responses to the compactor  230 . Although only a single flag  240  is shown, multiple flags may be used to separately control the decoders. In this example, the compactor  230  includes multiple spatial compactors, such as compactors  242  and  244 . Each control register may be loaded with different data so that the compactors  242 ,  244  can be controlled independently of each other. 
       FIG. 23  shows yet another embodiment of the present invention with a selective compactor  250 . Control logic  252  variably controls which test responses are masked and which test responses are compacted. Thus, activating the corresponding bit position in the control logic  252  activates the corresponding logic gate associated with that bit and allows the test response to pass to the compactor. Conversely, any bit that is not activated masks the corresponding test response. 
       FIG. 24  shows another embodiment of a selective compactor  256  including a selector circuit  258  and compactor  260 . In this case, an input shift register  262  having a bit position corresponding to each scan chain  264  is used to selectively mask the scan chains. A clock is applied to line  266  to serially move data applied on data line  268  into the shift register  262 . At the appropriate time, an update line  265  is activated to move the data from the shift register to a control register  269 . Each bit position that is activated in the control register  269  allows a test response from the scan chains  264  to pass to the compactor. All other test responses are masked. Thus, the selective compactor can mask any variable number of test responses. 
     Each of the embodiments described above can be used as a diagnostic tool for localizing faults in the circuit under test. For example, each test response can be analyzed individually by masking all other test responses in the scan chains connected to the same compactor. By viewing the test response individually, the bit position in the test response containing fault effects can be determined. 
       FIG. 25  shows a flowchart of a method for selectively compacting test responses. In process block  270 , an ATE loads predetermined test patterns into scan chains within an integrated circuit. This loading is typically accomplished by shifting the test patterns serially into the scan chains. The test patterns are applied to the circuit under test (process block  272 ) and the test responses are stored in the scan chains (process block  274 ). In process block  276 , the selector circuit controls which test responses are masked. In particular, the selector circuit controls which scan chains are masked or which bits in the scan chains are masked. For example, in  FIG. 19 , the selector circuit masks the entire scan chain that is identified in the scan identification field  158 . In  FIG. 21 , only individual bits of a scan chain are masked. In any event, in process block  276 , the selector circuit typically masks unknown data or multiple fault effects so that the desired fault effect can propagate to the output (in some modes of operation, all of the test responses may pass to the output). In the event that the selector circuit includes a control register, the control register may be loaded concurrently with loading the test patterns in the scan chains or it can be loaded prior to reading the test responses. In process block  278 , the test responses (one or more of which have been masked) are passed to the compactor and the compactor generates a compressed output associated with the test responses. In process block  280 , the compressed output generated by the compactor is compared to an ideal response. If they match, the integrated circuit is assumed to be fault free. 
     Having illustrated and described the principles of the illustrated embodiments, it will be apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles. For example, any of the illustrated compactors can be used with any of the illustrated selector circuits with minimum modification to create a selective compactor. Additionally, the selector circuit can easily be modified using different logic gates to achieve the selection functionality. For example, although the update lines are shown coupled to a separate bank of flip flops, the update lines can instead be coupled to input registers having tri-state outputs for controlling the logic in the selector circuit. Still further, although the scan chains are shown as serial shift registers, logic may be added so as to output test response data in parallel to the selective compactor. Additionally, although multiple spatial and time compactors were shown, compactors having features of both spatial and time compactors may be used. Indeed, any conventional or newly developed compactor may be used with the selection circuitry. 
     In view of the many possible embodiments to which the principles of the invention may be applied, it should be understood that the illustrative embodiment is intended to teach these principles and is not intended to be a limitation on the scope of the invention. We therefore claim as our invention all that comes within the scope and spirit of the following claims and their equivalents.