Patent Publication Number: US-10789144-B2

Title: Supervisory circuit, supervisory system, motor control system

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2018-036663, filed on Mar. 1, 2018, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The embodiments discussed herein relate to a supervisory circuit, a supervisory system, and a motor control system. 
     BACKGROUND 
     In a highly-integrated semiconductor integrated circuit such as a system on a chip (SoC), a plurality of programs and a plurality of circuits perform signal processing. It is highly important to supervise the signal processing implemented by the programs and the circuits. 
     The progress of the programs is checked during program processing. However, there is a problem in that it is difficult to supervise whether the entire program processing is executed in a predetermined order, whether a plurality of sets of signal processing by the circuits are executed in a predetermined order, and whether a plurality of sets of signal processing by the programs and the circuits are executed in a predetermined order. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing a supervisory circuit according to a first embodiment; 
         FIG. 2  is a diagram showing a supervisory system according to a second embodiment; 
         FIG. 3  is a diagram showing processing steps performed by a processing circuitry according to the second embodiment; 
         FIG. 4  is a diagram showing a supervisory system according to a third embodiment; 
         FIG. 5  is a diagram showing a supervisory system according to a fourth embodiment; 
         FIG. 6  is a diagram showing a motor control system according to a fifth embodiment; 
         FIG. 7  is a flowchart showing operation of the motor control system according to the fifth embodiment; 
         FIG. 8  is a diagram showing a motor control system according to a sixth embodiment; 
         FIG. 9  is a flowchart showing operation of the motor control system according to the sixth embodiment; 
         FIG. 10  is a timing chart showing operation of the motor control system according to the sixth embodiment in synchronization. 
     
    
    
     DETAILED DESCRIPTION 
     According to one embodiment, a supervisory circuit includes a trigger determination circuit and a trigger table. The trigger determination circuit receives signal processing signals outputted from a plurality of signal processing circuits as trigger signals, determines whether processing operations by the signal processing circuits are executed in a predetermined order, and outputs an interrupt signal when detecting a trigger signal out of setting. The trigger table is provided with trigger-specific tables corresponding to the respective signal processing circuits, reads a trigger setting to occur next based on a trigger determined as being correct by the trigger determination circuit, and outputs a table read signal to the trigger determination circuit. 
     Hereinbelow, further embodiments will be described with reference to the drawings. Throughout the drawings, the same reference numerals denote the same or like portions. 
     A supervisory circuit according to a first embodiment will be described with reference to  FIG. 1 .  FIG. 1  is a diagram showing the supervisory circuit. 
     The supervisory circuit of the first embodiment supervises whether processing operations by a plurality of signal processing circuits are executed in a predetermined order. 
     As shown in  FIG. 1 , a supervisory circuit  1  includes a memory  3 , a trigger determination circuit  11 , and a trigger table  12 . The supervisory circuit  1  supervises processing operations by n signal processing circuits (where n is an integer of 2 or more), e.g., a signal processing circuit  2   a , a signal processing circuit  2   b , and a signal processing circuit  2   n.    
     The signal processing circuit  2   a , the signal processing circuit  2   b , and the signal processing circuit  2   n  each execute digital signal processing or analog-digital signal processing once or a plurality of times for example, and output a signal obtained by the signal processing to the supervisory circuit  1  as a trigger signal. Specifically, the signal processing circuit  2   a  outputs a trigger signal Strig 1  to the supervisory circuit  1 , the signal processing circuit  2   b  outputs a trigger signal Strig 2  to the supervisory circuit  1 , and the signal processing circuit  2   n  outputs a trigger signal Strign to the supervisory circuit  1 . 
     Here, the n trigger signals (namely, the trigger signal Strig 1 , the trigger signal Strig 2 , and the trigger signal Strign) are a single job signal or a plurality of job signals. The case of the plurality of job signals include the job signals being outputted in order, the job signals being outputted sequentially at predetermined intervals, and the like. 
     The digital signal processing includes hardware processing or program processing (software processing) executed by a sequential circuit, a processor, a central processing unit (CPU), a micro-processing unit (MPU), or the like. The sequential circuit includes a flip-flop, a counter, and a register. 
     The analog-digital signal processing includes analog-to-digital conversion processing executed by an analog-to-digital converter (ADC) or the like and digital-to-analog processing executed by a digital-to-analog converter (DAC) or the like. 
     The trigger determination circuit  11  receives the trigger signal Strig 1 , the trigger signal Strig 2 , the trigger signal Strign, and based on sequence determination information stored in the memory  3 , determines whether the trigger signal Strig 1 , the trigger signal Strig 2 , and the trigger signal Strign are set in a predetermined order. The predetermined order includes the trigger signal Strig 1 , the trigger signal Strig 2 , and the trigger signal Strign being outputted in a chronological order, being in an interchanged order, or being outputted alternately, being in synchronization, being out of synchronization, and the like. 
     The trigger determination circuit  11  outputs an interrupt signal Sscr when detecting a trigger signal out of setting. The interrupt signal Sscr causes the system to be initialized, for example. The purpose of the interrupt signal is not limited to the system initialization. The interrupt signal may be used as notification information to the CPU, for example. 
     Here, the sequence determination information is written and stored in the memory  3  at any time by the CPU, MPU, or an outside of the system for example. Although provided inside the supervisory circuit  1  here, the memory  3  may be provided inside the trigger determination circuit  11  or outside the supervisory circuit  1 . 
     The trigger determination circuit  11  outputs each of the trigger signal Strig 1 , the trigger signal Strig 2 , and the trigger signal Strign to the trigger table  12 . 
     The trigger table  12  includes n trigger tables (namely a trigger-specific table  13   a , a trigger-specific table  13   b , and a trigger-specific table  13   n ). In response to a trigger signal inputted, the trigger table  12  makes a trigger setting to occur next for example. The trigger table  12  reads a trigger setting to occur next based on a trigger determined as being correct by the trigger determination circuit  11 , and outputs the trigger setting to the trigger determination circuit  11  as a table read signal Stread. 
     As described above, the supervisory circuit  1  of the embodiment is provided with the memory  3 , the trigger determination circuit  11 , and the trigger table  12 . The trigger determination circuit  11  receives a plurality of trigger signals and determines, based on the sequence determination information stored in the memory  3 , whether the plurality of trigger signals are set in a predetermined order. The trigger table  12  includes a plurality of trigger-specific tables, reads a trigger setting to occur, and outputs a table read signal Stread to the trigger determination circuit  11 . 
     Thus, the supervisory circuit  1  of the embodiment can supervise the processing operations by the plurality of signal processing circuits. 
     A supervisory system according to a second embodiment will be described with reference to  FIG. 2 .  FIG. 2  is a diagram showing the supervisory system. 
     The supervisory system of the second embodiment uses a supervisory circuit to supervise whether processing operations by a plurality of signal processing circuits and program processing by a processing circuitry are executed in a predetermined order. 
     Hereinbelow, the same constituent portions as those in the first embodiment are denoted by the same reference numerals as used in the first embodiment and will not be described again. Only different portions will be described. 
     As shown in  FIG. 2 , a supervisory system  300  includes a supervisory circuit  1   a  and a processing circuitry  6 . The processing circuitry  6  is provided to a microcontroller, a processor, a CPU, a MPU, or the like for example. 
     As shown in  FIG. 3 , the processing circuitry  6  executes a cycle of n types of processing (namely first processing, second processing, and n-th processing) which are program processing (software processing) in order, and after the n-th processing, executes the first processing again, repeating the processing cycle a plurality of times. 
     Here, the first processing is program processing caused to proceed by the trigger signal Strig 1  outputted from the signal processing circuit  2   a . The second processing is program processing caused to proceed by the trigger signal Strig 2  outputted from the signal processing circuit  2   b . The n-th processing is program processing caused to proceed by the trigger signal Strign outputted from the signal processing circuit  2   n . The processing circuitry  6  selects the first processing for example, and outputs the program processing to the supervisory circuit  1   a  as a register write signal Srwrite. 
     The supervisory circuit  1   a  includes the memory  3 , a trigger determination circuit  11   a , a trigger table  12   a , and a clear code detection circuit  14 . 
     The clear code detection circuit  14  receives the register write signal Srwrite outputted from the processing circuitry  6 , selects program processing, e.g., the interrupting first processing, as a particular clear code, and outputs the particular clear code to the trigger determination circuit  11   a  as a register-specific signal Srs 1 . 
     The trigger determination circuit  11   a  receives the trigger signal Strig 1 , the register-specific signal Srs 1 , which is the particular clear code (first processing), the trigger signal Strig 2 , and the trigger signal Strign, and determines, based on the sequence determination information stored in the memory  3 , whether the trigger signal Strig 1 , the register-specific signal Srs 1 , which is the particular clear code (first processing), the trigger signal Strig 2 , and the trigger signal Strign are set in a predetermined order. 
     When determining that the trigger signal Strig 1 , the register-specific signal Srs 1 , which is the particular clear code (first processing), the trigger signal Strig 2 , and the trigger signal Strign are not set in a predetermined order, i.e., when detecting a trigger signal out of setting, the trigger determination circuit  11   a  outputs an interrupt signal Sscr. 
     The trigger determination circuit  11   a  outputs each of the trigger signal Strig 1 , the register-specific signal Srs 1 , the trigger signal Strig 2 , and the trigger signal Strign to the trigger table  12   a.    
     The trigger table  12   a  includes the n trigger tables (namely the trigger-specific table  13   a , the trigger-specific table  13   b , and the trigger-specific table  13   n ) and a register-specific table  15 . In response to a trigger inputted, the trigger table  12   a  makes a trigger setting to occur next, for example. The trigger table  12   a  reads a trigger setting to occur next based on a trigger determined as being correct by the trigger determination circuit  11   a  and outputs the trigger setting to the trigger determination circuit  1   a  as a table read signal Stread. 
     As described above, the supervisory system  300  of the embodiment is provided with the supervisory circuit  1   a  and the processing circuitry  6 . The processing circuitry  6  receives trigger signals, executes n types of program processing in order, and executes the first processing again after the n-th processing, repeating the processing cycle a plurality of times. The supervisory circuit  1   a  includes the memory  3 , the trigger determination circuit  11   a , the trigger table  12   a , and the clear code detection circuit  14 . The clear code detection circuit  14  selects a particular clear code. The trigger determination circuit  11   a  determines, based on the sequence determination information stored in the memory  3 , whether the trigger signal Strig 1 , the particular clear code, the trigger signal Strig 2 , and the trigger signal Strign are set in a predetermined order. The trigger table  12   a  includes n trigger tables and the register-specific table  15 . In response to a trigger signal inputted, the trigger table  12   a  makes a trigger setting to occur next, for example. 
     Thus, the supervisory system  300  of the embodiment can supervise processing operations by the plurality of signal processing circuits and a particular clear code (the n-th processing for example). 
     Although the register write signal Srwrite is the first processing in the second embodiment, any one of the plurality of kinds of processing may be selected. 
     A supervisory system according to a third embodiment will be described with reference to  FIG. 4 .  FIG. 4  is a diagram showing the supervisory system. 
     The supervisory system of the third embodiment uses a supervisory circuit to supervise whether processing operations by a plurality of signal processing circuits and program processing by a processing circuitry are executed in a predetermined order and within a certain period of time. 
     Hereinbelow, the same constituent portions as those in the second embodiment are denoted by the same reference numerals as used in the second embodiment and will not be described again. Only different portions will be described. 
     As shown in  FIG. 4 , a supervisory system  301  includes a supervisory circuit  1   b  and the processing circuitry  6 . The supervisory circuit  1   b  includes the memory  3 , a counter  7 , a counter upper limit setting register  8 , a comparator  9 , the trigger determination circuit  11   a , a trigger table  12   b , and the clear code detection circuit  14 . Note that in  FIG. 4 , the n-th processing is used for the register write signal outputted from the clear code detection circuit  14 . For this reason, signal arrangement is different from that in  FIG. 2 . 
     The trigger table  12   b  includes n trigger tables, the register-specific table  15 , (n+1) initial value effecting tables (an initial value effecting table  16   a , an initial value effecting table  16   b , an initial value effecting table  16   n , and an initial value effecting table  16   n+ 1). 
     The (n+1) initial value effecting tables give initialization effecting attributes to the corresponding trigger tables. For instance, when an initialization effecting attribute is given to the initial value effecting table  16   a  corresponding to the trigger-specific table  13   a , the initial value effecting table  16   a  is set to “1”, and the initial value effecting table  16   b , the initial value effecting table  16   n , and the initial value effecting table  16   n+ 1 are set to “0 (zero)”. 
     When the counter  7  receives the “1” information on the initial value effecting table  16   a , the counter  7  initializes counting, and then continues counting. The counter  7  keeps counting until the initial value effecting table  16   n+ 1 corresponding to the register-specific table  15  becomes “1”. When a watchdog timer uses for the counter  7 , the watchdog timer starts counting, initializes a count value, and continues counting. The watchdog timer always operates. 
     The counter upper limit setting register  8  sets an upper-limit value for the counter  7 . The comparator  9  compares a counter value from the counter  7  with the upper-limit value for the counter  7  stored in the counter upper limit setting register  8 . For example, when a particular clear code (a register write by the n-th processing) is not executed, a count value from the counter  7  exceeds the counter upper-limit value. Thus, the comparator  9  generates an interrupt signal Sscr. 
     As described above, the supervisory system  301  of the embodiment is provided with the supervisory circuit  1   b  and the processing circuitry  6 . The supervisory circuit  1   b  has the memory  3 , the counter  7 , the counter upper limit setting register  8 , the comparator  9 , the trigger determination circuit  11   a , the trigger table  12   b , and the clear code detection circuit  14 . The comparator  9  compares a count value from the counter  7  with the upper-limit value for the counter  7  stored in the counter upper limit setting register  8 . The comparator  9  generates an interrupt signal Sscr when a particular clear code is not executed, for example. 
     Thus, the supervisory system  301  of the embodiment can supervise whether processing operations by the plurality of signal processing circuits and a particular clear code (e.g., the n-th processing) are executed in a predetermined order within a certain period of time. 
     A supervisory system according to a fourth embodiment will be described with reference to  FIG. 5 .  FIG. 5  is a diagram showing the supervisory system. 
     The supervisory system of the fourth embodiment uses a supervisory circuit to supervise whether processing operations by a plurality of signal processing circuits and programming processing by a processing circuitry are executed in a predetermined order and to supervise whether the next trigger is inputted within a set inter-trigger time period. 
     Hereinbelow, the same constituent portions as those in the second embodiment are denoted by the same reference numerals as used in the second embodiment and will not be described again. Only different portions will be described. 
     As shown in  FIG. 5 , a supervisory system  302  includes a supervisory circuit  1   c  and the processing circuitry  6 . The supervisory circuit  1   c  includes the memory  3 , a counter  7   a , a comparator  9   a , the trigger determination circuit  11   a , a trigger table  12   c , the clear code detection circuit  14 , and an OR circuit OR 1 . 
     The trigger table  12   c  includes n trigger tables, the register-specific table  15 , (n+1) counter upper-limit value tables (a counter upper-limit value table  17   a , a counter upper-limit value table  17   b , a counter upper-limit value table  17   n , and a counter upper-limit value table  17   n+ 1). The (n+1) counter upper-limit value tables give counter upper-limit values to the trigger tables. 
     The OR circuit OR 1  receives a trigger signal Strig 1 , a trigger signal Strig 2 , a trigger signal Strign, and a register-specific signal Srs 1  and performs logical operation processing (OR processing). The counter  7   a  receives information outputted from the OR circuit OR 1  as initialization information and starts a count operation. 
     The comparator  9   a  compares information in the counter upper-limit tables with the count value from the counter  7   a . The comparator  9   a  generates an interrupt signal Sscr when the next trigger is not inputted within a set inter-trigger time period. 
     As described above, the supervisory system  302  of the embodiment is provided with the supervisory circuit  1   c  and the processing circuitry  6 . The supervisory circuit  1   c  has the memory  3 , the counter  7   a , the comparator  9   a , the trigger determination circuit  11   a , the trigger table  12   c , the clear code detection circuit  14 , and the OR circuit OR 1 . The comparator  9   a  compares a count value from the counter  7   a  with the upper-limit value in the register. The comparator  9   a  generates an interrupt signal Sscr when the next trigger is not inputted within a set inter-trigger time period. 
     Thus, the supervisory system  302  of the embodiment can supervise whether processing operations by the plurality of signal processing circuits and program processing by the processing circuitry are executed in a predetermined order and supervise whether the next trigger is inputted within a set inter-trigger time period. 
     A motor control system according to a fifth embodiment will be described with reference to  FIG. 6 .  FIG. 6  is a diagram showing the motor control system. 
     In the fifth embodiment, a supervisory system configured with a processing circuitry and a supervisory circuit is provided to a microcontroller to supervise processing operations by an AD converter, a co-processor, and a CPU. The microcontroller is also called a microcomputer. 
     Hereinbelow, the same constituent portions as those in the third embodiment are denoted by the same reference numerals as used in the third embodiment and will not be described again. Only different portions will be described. 
     As shown in  FIG. 6 , a motor control system  100  includes a microcontroller  31 , a co-processor  32 , a motor  33 , a sensor  34 , an inverter  35 , and an AD converter  36 . The microcontroller  31  includes the supervisory system  301 , a CPU  4 , and an interrupt processing circuit  5 . 
     Here, the supervisory system  301  has the same configuration and functions as the supervisory system  301  of the third embodiment, and supervises the processing operations by the AD converter, the co-processor, and the CPU. 
     When the trigger determination circuit  11   a  (not shown) of the supervisory circuit  1   b  detects a trigger signal out of setting, the interrupt processing circuit  5  receives an interrupt signal Sscr outputted from the trigger determination circuit  11   a  and invokes reset. Based on the interrupt signal Sscr, the interrupt processing circuit  5  initializes the motor control system  100 . 
     The motor  33  is a three-phase motor, for example. The sensor  34  is disposed around the motor  33  to detect the operation status, surrounding environment, and the like of the motor and outputs detection information to the CPU  4 . The inverter  35  receives a three-phase PWM output signal outputted from the co-processor  32 , and outputs a signal to control the rotation of the motor  33  to the motor  33  based on the three-phase PWM output signal. 
     The AD converter  36  is also called an analog-to-digital converter (ADC). The AD converter  36  executes analog-to-digital signal processing as a signal processing circuit. Specifically, the AD converter  36  detects a current (an analog value) supplied from the inverter  35  to the motor  33 , performs analog-to-digital conversion processing on the current to obtain a current detection signal (a digital value), outputs the current detection signal (a digital value) to the co-processor  32 , and outputs the current detection signal (a digital value) also to the supervisory system  301  as a trigger signal Strig 1 . 
     The co-processor  32  executes digital signal processing. Specifically the co-processor  32  receives a signal outputted from the AD converter  36  and performs phase transformation processing from three phases to two phases and coordinate transformation processing from αβ to dq, for example. The co-processor  32  outputs a result of the coordinate transformation to the CPU  4  and outputs the result of the coordinate transformation also to the supervisory system  301  as a trigger signal Strig 2 . The co-processor  32  receives dq-axis-system motor voltage information outputted from the CPU  4 , performs reverse coordinate transformation from dq to αβ and phase transformation from two phases to three phases, generates a three-phase PWM signal, outputs the three-phase PWM signal to the inverter  35 , and outputs the three-phase PWM signal also to the supervisory system  301  as a trigger signal Strig 2 . 
     The CPU  4  executes digital signal processing. Specifically, the CPU  4  receives a dq-axis-system motor current outputted from the co-processor  32  and receives rotor position information detected by the sensor  34 . The CPU  4  performs position detection, speed control, and current control of the motor  33 , outputs dq-axis-system motor voltage information to the co-processor  32 , and outputs the dq-axis-system motor voltage information also to the supervisory system  301  as a trigger signal Strig 3 . 
     Next, operation of the motor control system will be described with reference to  FIG. 7 .  FIG. 7  is a flowchart showing the operation of the motor control system. 
     As shown in  FIG. 7 , the motor control system  100  performs motor drive control (Step S 1 ), current detection by the AD converter  36  (Step S 2 ), phase transformation and coordinate transformation by the co-processor  32  (Step S 3 ), rotor position detection, speed control, and current control by the CPU  4  (Step S 4 ), reverse coordinate transformation, phase transformation, and PWM output by the co-processor  32  (Step S 5 ), and inverter control (Step S 6 ) in order. 
     After the inverter control ends (Step S 6 ), the motor control system  100  starts the motor drive control (Step S 1 ) again, repeating Steps S 1  to S 6  a plurality of times. 
     In one cycle from Step S 1  to Step S 6 , the supervisory system  301  receives a current detection signal from the AD converter  36  as a trigger signal Strig 1 , next receives a result of coordinate transformation from the co-processor  32  as a trigger signal Strig 2 , then receives motor voltage information from the CPU  4  as a trigger signal Strig 3 , and then receives a three-phase PWM output signal from the co-processor  32  as a trigger signal Strig 2 . 
     The supervisory system  301  supervises and determines whether the trigger signal Strig 1 , the trigger signal Strig 2 , and the trigger signal Strig 3  are set in a predetermined order. When the trigger signals are not set in a predetermined order (a preset sequence), an interrupt signal Sscr is outputted from the supervisory circuit  1   b  to the interrupt processing circuit  5  to initialize the motor control system  100 . 
     As described above, the motor control system  100  of the embodiment is provided with the microcontroller  31 , the co-processor  32 , the motor  33 , the sensor  34 , the inverter  35 , and the AD converter  36 . The microcontroller  31  includes the supervisory system  301 , the CPU  4 , and the interrupt processing circuit  5 . In one cycle of operation of the motor  33  in the motor control system  100 , the supervisory system  301  receives the trigger signal Strig 1  outputted from the AD converter  36 , the trigger signals Strig 2  outputted from the co-processor  32 , and the trigger signal Strig 3  outputted from the CPU  4 . 
     Thus, the motor control system  100  of the embodiment can determine and supervise whether the processing operations by the AD converter  36 , the co-processor  32 , and the CPU  4  are executed in a predetermined order. 
     In the fifth embodiment, the supervisory system  301  is used in the motor control system  100 . However, the invention is not necessarily limited to the above case. The supervisory system  301  may be used in various control systems. For example, the supervisory system  301  may be used in various control systems such as a vehicle autonomous driving control system and a drone flying control system. 
     Also, in the fifth embodiment, the CPU  4  is provided inside the microcontroller  31 , and the co-processor  32  performs phase transformation, coordinate transformation, reverse coordinate transformation, and PWM output. However, the invention is not necessarily limited to the above case. The processing executed by the co-processor  32  may be executed by the CPU  4 . 
     Moreover, in the fifth embodiment, the microcontroller  31  is provided with the supervisory system  301  of the third embodiment. Instead, the microcontroller  31  may be provided with the supervisory system  302  of the fourth embodiment. 
     A motor control system according to a sixth embodiment will be described with reference to  FIG. 8 .  FIG. 8  is a diagram showing the motor control system. 
     In the motor control system of the sixth embodiment to control two motors, a supervisory system to supervise each of the motors is provided to a microcontroller, and processing operations by an AD converter, a co-processor, and a CPU are supervised. 
     Hereinbelow, the same constituent portions as those in the fifth embodiment are denoted by the same reference numerals as used in the fifth embodiment and will not be described again. Only different portions will be described. 
     As shown in  FIG. 8 , a motor control system  200  includes a microcontroller  31   a , the co-processor  32 , a motor  33   a , a motor  33   b , a sensor  34   a , a sensor  34   b , an inverter  35   a , an inverter  35   b , an AD converter  36   a , and an AD converter  36   b.    
     The motor control system  200  is provided with the sensor  34   a , the inverter  35   a , and the AD converter  36   a  on the motor  33   a  side and with the sensor  34   b , the inverter  35   b , and the AD converter  36   b  on the motor  33   b  side. The motor control system  200  controls the two motors (the motor  33   a  and the motor  33   b ) using the microcontroller  31   a  and the co-processor  32 . 
     The microcontroller  31   a  includes the CPU  4 , an interrupt processing circuit  5   a , an interrupt processing circuit  5   b , a supervisory system  301   a , and a supervisory system  301   b . The supervisory system  301   a  includes a processing circuitry  6   a  and a supervisory circuit  1   ba . The supervisory system  301   b  includes a processing circuitry  6   b  and a supervisory circuit  1   bb.    
     Here, the processing circuitry  6   a  and the processing circuitry  6   b  have the same configuration as the processing circuitry  6  in  FIG. 2 . The supervisory circuit  1   ba  and the supervisory circuit  1   bb  have the same configuration as the supervisory circuit  1   b  in  FIG. 6 . 
     The AD converter  36   a  executes analog-to-digital signal processing as a signal processing circuit. Specifically, the AD converter  36   a  detects a current (an analog value) supplied from the inverter  35   a  to the motor  33   a , performs analog-to-digital conversion on the current to obtain a current detection signal (a digital value), outputs the current detection signal (a digital value) to the co-processor  32 , and outputs the current detection signal (a digital value) also to the supervisory system  301   a  as a trigger signal Strig 1 . 
     The AD converter  36   b  executes analog-to-digital signal processing as a signal processing circuit. Specifically, the AD converter  36   b  detects a current (an analog value) supplied from the inverter  35   b  to the motor  33   b , performs analog-to-digital conversion on the current to obtain a current detection signal (a digital value), outputs the current detection signal (a digital value) to the co-processor  32 , and outputs the current detection signal (a digital value) also to the supervisory system  301   b  as a trigger signal Strig 2 . 
     The co-processor  32  receives signals outputted from the AD converter  36   a  and the AD converter  36   b  and performs phase transformation processing from three phases to two phases and coordinate transformation processing from a to dq, for example. The co-processor  32  outputs coordinate transformation results for the motor  33   a  and the motor  33   b  to the CPU  4  and outputs the coordinate transformation results for the motor  33   a  and the motor  33   b  also to the supervisory system  301   a  and the supervisory system  301   b , respectively, as trigger signals Strig 3 . The co-processor  32  receives dq-axis-system motor voltage information outputted from the CPU  4 , performs reverse coordinate transformation processing from dq to αβ and phase transformation processing from two phases to three phases, generates three-phase PWM signals, outputs the three-phase PWM signals to the inverter  35   a  and the inverter  35   b , and outputs the three-phase PWM signals also to the supervisory system  301   a  and the supervisory system  301   b  as trigger signals Strig 3 . 
     The CPU  4  receives a dq-axis-system motor current outputted from the co-processor  32  and also receives rotor position information detected by the sensor  34   a  and the sensor  34   b . The CPU  4  performs position detection, speed control, and current control of the motor  33   a  and the motor  33   b , outputs dq-axis-system motor voltage information regarding the motor  33   a  and the motor  33   b  to the co-processor  32 , and outputs dq-axis-system motor voltage information regarding the motor  33   a  and the motor  33   b  also to the supervisory system  301   a  and the supervisory system  301   b  as trigger signals Strig 4 . 
     Next, operation of the motor control system will be described with reference to  FIGS. 9 and 10 .  FIG. 9  is a flowchart showing the operation of the motor control system.  FIG. 10  is a timing chart showing the operation of the motor control system in synchronization. 
     As shown in  FIG. 9 , the motor control system  200  sequentially performs motor drive control of the motor  33   a  and the motor  33   b  (Step S 11 ), current detection by the AD converter  36   a  and the AD converter  36   b  (Step S 12 ), phase transformation and coordinate transformation by the co-processor  32  (Step S 13 ), rotor position detection, speed control, and current control by the CPU  4  (Step S 14 ), reverse coordinate transformation, phase transformation, and PWM output by the co-processor  32  (Step S 15 ), and inverter control of the inverter  35   a  and the inverter  35   b  (Step S 16 ). 
     After the inverter control ends (Step S 16 ), the motor control system  200  starts the motor drive control (Step S 11 ) again, repeating the steps (Steps S 11  to S 16 ) a plurality of times. 
     In one cycle from Steps S 11  to S 16 , the supervisory system  301   a  receives a current detection signal from the AD converter  36   a  as a trigger signal Strig 1 . The supervisory system  301   b  receives a current detection signal from the AD converter  36   b  as a trigger signal Strig 2 . Next, the supervisory system  301   a  and the supervisory system  301   b  receive coordinate transformation results on the motor  33   a  and the motor  33   b  from the co-processor  32  as trigger signals Strig 3 , then receive motor voltage information on the motor  33   a  and the motor  33   b  from the CPU  4  as trigger signals Strig 4 , and next receive three-phase PWM output signals about the motor  33   a  and the motor  33   b  from the co-processor  32  as trigger signals Strig 2 . 
     The supervisory system  301   a  supervises and determines whether the trigger signal Strig 1 , the trigger signal Strig 3 , and the trigger signal Strig 4  are executed in a predetermined order. When the trigger signals are not in a predetermined order, an interrupt signal Sscr is outputted from the supervisory circuit  1   ba  to the interrupt processing circuit  5   a , and the motor control system  200  is initialized. 
     The supervisory system  301   b  supervises and determines whether the trigger signal Strig 2 , the trigger signal Strig 3 , and the trigger signal Strig 4  are executed in a predetermined order. When the trigger signals are not in a predetermined order, an interrupt signal Sscr is outputted from the supervisory circuit  1   bb  to the interrupt processing circuit  5   b , and the motor control system  200  is initialized. 
     As shown in  FIG. 10 , when triggers to the inverter  35   a  and the inverter  35   b  are in synchronization (normal operation), analog-to-digital conversion processing by the AD converter  36   b  is executed right after analog-to-digital conversion processing by the AD converter  36   a . The supervisory system  301   a  receives a trigger signal Strig 1  about the motor  33   a  (an output from ADC 1 ) at time point t 1 , and then receives a trigger signal Strig 3  about the motor  33   a  (an output from the co-processor  32 ) at time point t 2 . The supervisory system  301   b  receives a trigger signal Strig 2  about the motor  33   b  (an output from ADC 2 ) at time point t 3 , and then receives a trigger signal Strig 3  about the motor  33   b  (an output from the co-processor  32 ) at time point t 4 . 
     In  FIG. 10 , an interval for the motor  33   a  is denoted as a motor interval Tms 1 , and an interval for the motor  33   b  is denoted as a motor interval Tms 2 . For example, the motor interval Tms 1  and the motor interval Tms 2  have the same value and set to 50 μs. The interval for PWM control of the motor  33   a  by the co-processor  32  and the interval for PWM control of the motor  33   b  by the co-processor  32  are set to be the same, but may be different. 
     The CPU  4  executes vector control  1  and special control  1  for the motor  33   a  within a CPU processing time Tcpu 1 . At time point t 5  which is right after the vector control  1  and the special control  1  end, the supervisory system  301   a  receives a trigger signal Strig 4  about the motor  33   a  (a CPU output), and the CPU  4  executes vector control  2  and special control  2  for the motor  33   b  within a CPU processing time Tcpu 2 . The special control  1  is processing other than the vector control  1 . 
     The inverter  35   a  receives a three-phase PWM signal from the co-processor  32  and performs inverter control. At time point t 6 , the supervisory system  301   a  receives a trigger signal Strig 3  about the motor  33   a  (an output from the co-processor  32 ). 
     At time point t 7  which is after the vector control  2  and the special control  2  for the motor  33   b  end, the supervisory system  301   b  receives a trigger signal Strig 4  about the motor  33   b  (a CPU output). The inverter  35   b  receives a three-phase PWM signal from the co-processor  32  and performs inverter control. At time point t 8 , the supervisory system  301   b  receives a trigger signal Strig 3  about the motor  33   b  (an output from the co-processor  32 ). 
     The supervisory system  301   a  determines and supervises whether the trigger signal Strig 1  (the output from ADC 1 ), the trigger signals Strig 3  (the coordinate transformation information on the motor  33   a  from the co-processor  32  to the CPU  4  and the three-phase PWM output about the motor  33   a  from the co-processor  32  to the inverter  35   a ), and the trigger signal Strig 4  (the motor voltage information on the motor  33   a  from the CPU  4  to the co-processor  32 ) are processed in a predetermined order (specifically, time point t 1 , time point t 2 , time point t 5 , and time point t 6 ). 
     The supervisory system  301   b  determines and supervises whether the trigger signal Strig 2  (the output from ADC 2 ), the trigger signals Strig 3  (the coordinate transformation information on the motor  33   b  from the co-processor  32  to the CPU  4  and the three-phase PWM output on the motor  33   b  from the co-processor  32  to the inverter  35   b ), and the trigger signal Strig 4  (the motor voltage information on the motor  33   b  from the CPU  4  to the co-processor  32 ) are processed in a predetermined order (specifically, in the order of time point t 3 , time point t 4 , time point t 7 , and time point t 8 ). 
     As shown in  FIG. 10 , with a period of time between time point t 6  at which the inverter  35   a  (the inverter  1 ) starts driving and a time point at which the AD converter  36   a  starts AD conversion being referred to as time allowance T 11  for the motor  33   a , it is shown in  FIG. 10  that T 11 &gt;0 (zero). Similarly, with a period of time between time point t 8  at which the inverter  35   b  (the inverter  2 ) starts driving and a time point at which the AD converter  36   b  starts AD conversion being referred to as time allowance T 12  for the motor  33   b , it is shown in  FIG. 10  that T 12 &gt;0 (zero). In other words, it is shown that the operation is performed normally. 
     As described above, the motor control system  200  of the embodiment is provided with the microcontroller  31   a , the co-processor  32 , the motor  33   a , the motor  33   b , the sensor  34   a , the sensor  34   b , the inverter  35   a , the inverter  35   b , the AD converter  36   a , and the AD converter  36   b . The microcontroller  31   a  includes the supervisory system  301   a , the supervisory system  301   b , the CPU  4 , the interrupt processing circuit  5   a , and the interrupt processing circuit  5   b . During operation of the motor  33   a  in the motor control system  200 , the supervisory system  301   a  receives the trigger signal Strig 1  outputted from the AD converter  36   a , the trigger signal Strig 3  outputted from the co-processor  32 , and the trigger signal Strig 4  outputted from the CPU  4 . During operation of the motor  33   b  in the motor control system  200 , the supervisory system  301   b  receives the trigger signal Strig 2  outputted from the AD converter  36   b , the trigger signal Strig 3  outputted from the co-processor  32 , and the trigger signal Strig 4  outputted from the CPU  4 . 
     Thus, the motor control system  200  of the embodiment can determine and supervise whether the processing operations by the AD converter  36   a , the AD converter  36   b , the co-processor  32 , and the CPU  4  are executed in a predetermined order. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intend to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of the other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.