Patent Publication Number: US-9905288-B2

Title: Semiconductor memory devices and methods of operating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0037322, filed on Mar. 29, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to memory devices. More particularly, the present disclosure relates to semiconductor memory devices and methods of operating the same. 
     2. Background Information 
     In general, a semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) includes tens of millions of memory cells, and stores and outputs data in response to a command requested from a chipset. That is, if the chipset requests a write operation to the semiconductor memory device, the semiconductor memory device stores data on a memory cell corresponding to an address inputted from the chipset. If the chipset requests a read operation to/from the semiconductor memory device, the semiconductor memory device outputs the data stored on the memory, cell corresponding to the address inputted from the chipset. 
     The synchronous semiconductor memory device inputs/outputs data in synchronization with a clock signal. An amount of data may tend to increase over time. Power consumption of the synchronous semiconductor memory device increases as the amount of data increases. 
     SUMMARY 
     Some exemplary embodiments provide a semiconductor memory device, capable of reducing current consumption without increasing occupied area. 
     Some exemplary embodiments provide a memory system that includes the semiconductor memory device. 
     According to exemplary embodiments, a semiconductor memory device includes a memory cell array and a control logic circuit. The control logic circuit controls access to the memory cell array based on a command and an address. The semiconductor memory device performs a write operation to write data in the memory cell array and performs a read operation to read data from the memory cell array in synchronization with a clock signal from an external memory controller. The semiconductor memory device performs the write operation and the read operation in different data strobe modes in which the semiconductor memory device uses different numbers of data strobe signals according to a frequency of the clock signal. 
     According to exemplary embodiments, in a method of operating a semiconductor memory device that includes a memory cell array, it is determined whether a frequency of a clock signal is smaller than or equal to a reference frequency. The clock signal is provided from an external memory controller. A memory operation is performed on the memory cell array using a number of data strobe signals that varies according to the frequency of the clock signal. 
     Accordingly, in a semiconductor memory device and a method of operating a semiconductor memory device, power consumption may be reduced by reducing a second number of data strobe signals used when the frequency of the clock signal is smaller than or equal to the reference frequency, compared to a first number of data strobe signals used when the frequency of the clock signal is greater than the reference frequency. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. 
         FIG. 1  is a block diagram illustrating an electronic memory system according to exemplary embodiments. 
         FIG. 2  is a block diagram illustrating an example of the memory system in  FIG. 1  according to exemplary embodiments. 
         FIG. 3  is a block diagram illustrating an example of a semiconductor memory device of the memory system in  FIG. 2  according to exemplary embodiments. 
         FIG. 4  illustrates an example of the first bank array in the semiconductor memory device of  FIG. 3 . 
         FIG. 5  illustrates an example of the I/O circuit in the semiconductor memory device of  FIG. 3  according to exemplary embodiments. 
         FIG. 6  illustrates an example of the strobe controller in the I/O circuit of  FIG. 5  according to exemplary embodiments. 
         FIG. 7  illustrates the internal strobe signal generator and the data sampling circuit in the I/O circuit of  FIG. 5 . 
         FIG. 8  is a timing diagram illustrating operation of the memory system of  FIG. 2 . 
         FIG. 9  illustrates a portion of the I/O circuit of  FIG. 5  according to exemplary embodiments. 
         FIG. 10  is a timing diagram illustrating operation of the memory system of  FIG. 2 . 
         FIG. 11  illustrates the memory system of  FIG. 2  in the first data strobe mode. 
         FIG. 12  illustrates the memory system of  FIG. 2  in the second data strobe mode. 
         FIG. 13  illustrates the memory system of  FIG. 2  in the second sub data strobe mode or in the third sub data strobe mode. 
         FIG. 14  illustrates operation of the I/O circuit of  FIG. 9  in the second sub data strobe mode. 
         FIG. 15  is a structural diagram illustrating a semiconductor memory device according to exemplary embodiments. 
         FIG. 16  is a flow chart illustrating a method of operating a semiconductor memory device according to exemplary embodiments. 
         FIG. 17  is a flow chart illustrating a method of operating a semiconductor memory device according to exemplary embodiments. 
         FIG. 18  is a block diagram illustrating a mobile system that includes the semiconductor memory device according to exemplary embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. 
       FIG. 1  is a block diagram illustrating an electronic memory system according to exemplary embodiments. 
     Referring to  FIG. 1 , an electronic system  10  may include a host  20  and a memory system  30 . The memory system  30  may include a memory controller  100  and multiple semiconductor memory devices  200   a ˜ 200   k.    
     The host  20  may communicate with the memory system  30  through various interface protocols such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or serial attached SCSI (SAS). In addition, the host  20  may also communicate with the memory system  30  through interface protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE). 
     The memory controller  100  may control an overall operation of the memory system  30 . The memory controller  100  may control an overall data exchange between the host  20  and the semiconductor memory devices  200   a ˜ 200   k . For example, the memory controller  100  may write data in the semiconductor memory devices  200   a ˜ 200   k  or read data from the semiconductor memory devices  200   a ˜ 200   k  in response to requests from the host  20 . 
     In addition, the memory controller  100  may issue operation commands to the semiconductor memory devices  200   a ˜ 200   k  for controlling the semiconductor memory devices  200   a ˜ 200   k.    
     In some embodiments, each of the semiconductor memory devices  200   a ˜ 200   k  may be a dynamic random access memory (DRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), a Rambus dynamic random access memory (RDRAM), etc. 
       FIG. 2  is a block diagram illustrating an example of the memory system in  FIG. 1  according to exemplary embodiments. 
     In  FIG. 2 , only one semiconductor memory device  200   a  in communication with the memory controller  100  is illustrated for convenience. However, the details discussed herein related to semiconductor memory device  200   a  may equally apply to the other semiconductor memory devices  200   b ˜ 200   k.    
     Referring to  FIG. 2 , the memory system  30  may include the memory controller  100  and the semiconductor memory device  200   a . Each of the memory controller  100  and the semiconductor memory device  200   a  may be formed as a separate semiconductor chip or as a separate group of chips (e.g., semiconductor memory device  200   a  may include a stack of semiconductor chips in a semiconductor package). The memory controller  100  transmits to the semiconductor memory device  200   a  control signals such as a clock signal CLK, a command CMD, an address ADDR, data strobe signals DQS, and data DQs, and receives the data DQs and the data strobe signals DQS from the semiconductor memory device  200   a.    
     The memory controller  100  may transmit a write command and/or a read command to the semiconductor memory device  200   a . The semiconductor memory device  200   a  may perform a write operation in response to the write command and may perform a read operation in response to the read command. 
       FIG. 3  is a block diagram illustrating an example of a semiconductor memory device of the memory system in  FIG. 2  according to exemplary embodiments. 
     Referring to  FIG. 3 , the semiconductor memory device  200   a  may include a command/address input buffer  210 , a control logic circuit  220 , bank control logic  230 A˜ 230 D, a memory cell array (of bank arrays)  240 A˜ 240 D, write driver and data input/output (I/O) sense amplifiers  250 A˜ 250 D, error correction code (ECC) engines  260 A˜ 260 D, an I/O data buffer  270 , and an I/O circuit  300 . 
     The memory cell array (of bank arrays)  240 A˜ 240 D may include first through fourth bank arrays  240 A˜ 240 D, respectively, in which multiple memory cells are arrayed in rows and columns. A row decoder and a column decoder for selecting word-lines and bit-lines that are connected to the memory cells may be connected to each of the first through fourth bank arrays  240 A˜ 240 D. In the exemplary embodiment, the semiconductor memory device  200   a  includes the four bank arrays  240 A˜ 240 D, but in other embodiments, the semiconductor memory device  200   a  may include an arbitrary (i.e., different or varying) number of bank arrays. 
     The command/address input buffer  210  may receive a clock signal CLK, a command CMD, and an address ADDR from the memory controller  100  (not shown). The command CMD and the address ADDR may be input via the same terminals, i.e., CA pads. The command CMD and the address ADDR may be sequentially input via the CA pads. The command CMD issued by the memory controller  100  may include a read command and a write command. The read command indicates a read operation of/from the semiconductor memory device  200   a . The write command indicates a write operation of/to the semiconductor memory device  200   a.    
     The control logic circuit  220  may receive the command CMD and the address ADDR via the command/address input buffer  210 , and may generate an internal command ICMD, a strobe mode signal SMS and an address signal (BA/RA/CA). The internal command ICMD may include an internal read command and an internal write command. The address signal may include a bank address BA, a row address RA, and a column address CA. The internal command ICMD and the address signal BA/RA/CA may be provided to each bank control logic  230 A˜ 230 D. The control logic circuit  220  may control access to the memory cell array (of bank arrays)  240 A˜ 240 D. 
     The control logic circuit  220  may include a command decoder  221  and a mode register  222 . The command decoder  221  decodes the command CMD to generate the internal command ICMD and the mode register  222  may set an operation mode of the semiconductor memory device  200   a  based on the command CMD and the address ADDR. The mode register  222  may set a write latency in the write operation of the semiconductor memory device  200   a  and a read latency in the read operation of the semiconductor memory device  200   a  based on the command CMD and the address ADDR, according to a frequency of the clock signal CLK. Alternatively, the mode register  222  may set the write latency and read latency based on a test mode register set signal TMRS which is externally applied, according to a frequency of the clock signal CLK. The control logic circuit  222  may determine a logic level of the strobe mode signal SMS based on the write latency and the read latency and may provide the strobe mode signal SMS to the I/O circuit  300 . 
     Each bank control logic  230 A˜ 230 D may be activated while corresponding to the bank address BA. The activated bank control logic  230 A˜ 230 D may generate bank control signals in response to the internal command ICMD, the row address RA, and the column address CA. In response to the bank control signal, the row decoder and the column decoder of each of the first through fourth bank arrays  240 A˜ 240 D that are connected to the activated bank control logic  230 A˜ 230 D may be activated. 
     The row decoder of each of the first through fourth bank arrays  240 A˜ 240 D may decode the row address RA and therefore may enable a word-line that corresponds to the row address RA. The column address CA of each of the first through fourth bank arrays  240 A˜ 240 D may be temporarily stored in a column address latch. The column address latch may stepwise increase the column address CA in a burst mode. The temporarily stored or stepwise increased column address CA may be provided to the column decoder. The column decoder may decode the column address CA and therefore may activate a column selection signal CSL that corresponds to the column address CA. 
     In response to the bank control signal, each bank control logic  230 A˜ 230 D may generate an ECC encoding signal ENC and an ECC decoding signal DEC for controlling operations of the ECC engines  260 A˜ 260 D that are connected to the first through fourth bank arrays  240 A˜ 240 D, respectively. 
     The write driver and data I/O sense amplifiers  250 A˜ 250 D may sense and amplify multiple pieces of read data output from the first through fourth bank arrays  240 A˜ 240 D, respectively. The write driver and data I/O sense amplifiers  250 A˜ 250 D may transmit multiple pieces of write data to be stored in the first through fourth bank arrays  240 A˜ 240 D, respectively. 
     During the write operation, each of the ECC engines  260 A˜ 260 D may generate parity bits by performing an ECC encoding operation on the pieces of write data to be stored in each of the first through fourth bank arrays  240 A˜ 240 D, in response to the ECC encoding signal ENC output from each bank control logic  230 A˜ 230 D. 
     During the read operation, each of the ECC engines  260 A˜ 260 D may perform an ECC decoding operation in response to the ECC decoding signal DEC output from each of the first through fourth bank arrays  240 A˜ 240 D. The ECC engines  260 A˜ 260 D may perform the ECC decoding operation by using the pieces of data and parity bits that are read from each of the first through fourth bank arrays  240 A˜ 240 D. Therefore, the ECC engines may detect and correct an error bit in the pieces of read data. 
     The I/O data buffer  270  may include circuits for gating multiple pieces of data that are input to or output from the first through fourth bank arrays  240 A˜ 240 D; read data latches for storing the pieces of data output from the first through fourth bank arrays  240 A˜ 240 D; and write data latches for writing the pieces of data to the first through fourth bank arrays  240 A˜ 240 D. 
     The I/O data buffer  270  may convert parallel data bits that are output from the first through fourth bank arrays  240 A˜ 240 D into serial data bits via the read data latches. The I/O data buffer  270  may convert multiple pieces of write data that are serially received into parallel data bits by using the write data latches. 
     The I/O circuit unit  300  may receive the serial data bits output from the I/O data buffer  270 , may sequentially array the serial data bits as data bits that correspond to a burst length, and then may output together the data bits and the data strobe signal DQS to data I/O pads. The I/O circuit  300  may receive the data strobe signal DQS and the pieces of write data that correspond to the burst length and that are serially input via the data I/O pads from the memory controller  100 . The I/O circuit unit  300  may provide, to the I/O data buffer  270 , the pieces of serially input write data that correspond to the burst length. 
     The memory controller  100  in the memory system  20  may set a different data strobe mode of the semiconductor memory device  200   a  according to a frequency of the clock signal CLK. 
     For example, when the frequency of the clock signal CLK is greater than a reference frequency, the memory controller  100  may set the data strobe mode of the semiconductor memory device  200   a  to a first data strobe mode. In the first data strobe mode, the semiconductor memory device  200  may perform the write operation and the read operation on the memory cell array (of bank arrays)  240 A˜ 240 D using differential data strobe signal pairs. 
     For example, when the frequency of the clock signal CLK is smaller than or equal to the reference frequency, the memory controller  100  may set the data strobe mode of the semiconductor memory device  200   a  to a second data strobe mode. In the second data strobe mode, the semiconductor memory device  200  may perform the write operation and the read operation on the memory cell array (of bank arrays)  240 A˜ 240 D using single-ended data strobe signals. Therefore, a second number of data strobe signals associated with the write operation and the read operation in the second strobe mode is smaller than a first number of data strobe signals associated with the write operation and the read operation in the first data strobe mode. The memory system  20  therefore may reduce power consumption in the write operation and the read operation. 
     The table  1  below illustrates a write latency and read latency of the semiconductor memory device in the memory system  20  of  FIG. 2  according to the frequency of the clock signal CLK. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                   
                 LOWER CLOCK 
                 HIGHER CLOCK 
               
               
                 READ 
                 WRITE 
                 FREQUENCY 
                 FREQUENCY 
               
               
                 LATENCY 
                 LATENCY 
                 LIMIT(Mbps) 
                 LIMIT(Mbps) 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                 6 
                 4 
                 100 
                 266 
               
               
                 10 
                 6 
                 266 
                 533 
               
               
                 14 
                 8 
                 533 
                 800 
               
               
                 20 
                 10 
                 800 
                 1066 
               
               
                 24 
                 12 
                 1066 
                 1333 
               
               
                 28 
                 14 
                 1333 
                 1600 
               
               
                 32 
                 16 
                 1600 
                 1866 
               
               
                 36 
                 18 
                 1866 
                 2133 
               
               
                   
               
            
           
         
       
     
     As is noted from the table  1 , the read latency and the write latency of the semiconductor memory device  200   a  are defined in a specification of the semiconductor memory device  200   a  according to the frequency of the clock signal CLK. The memory controller  100  sets the read latency and the write latency of the semiconductor memory device  200   a  in the mode register  222  according to the frequency of the clock signal CLK. The mode register  222  may generate the strobe mode signal SMS in response to the frequency of the clock signal CLK. The read latency of the semiconductor memory device  200   a  indicates a clock cycle CLK delay between the read command and a first bit of valid output data. The write latency of the semiconductor memory device  200   a  indicates a clock cycle CLK delay between the write command and a first bit of valid write data. 
       FIG. 4  illustrates an example of the first bank array in the semiconductor memory device of  FIG. 3 . 
     Referring to  FIG. 4 , the first bank array  240 A includes multiple word-lines WL 1 ˜WL 2   m  (m is a natural number greater than two), multiple bit-lines BL 1 ˜BLn (n is a natural number greater than two), and multiple memory cells MCs disposed near intersections between the word-lines WL 1 ˜WL 2   m  and the bit-lines BL 1 ˜BLn. In one embodiment, each of the memory cells MCs may include a dynamic random access memory (DRAM) cell structure. The word-lines WL 1 ˜WL 2   m  to which the memory cells MCs are connected may be defined as rows of the first bank array  240 A and the bit-lines BL 1 ˜BLn to which the memory cells MCs are connected may be defined as columns of the first bank array  240 A. 
     In  FIG. 4 , m memory cells are coupled to a bit-line BL of the first bank array  310  and m memory cells are coupled to a word-line of the first bank array  310 . 
       FIG. 5  illustrates an example of the I/O circuit in the semiconductor memory device of  FIG. 3  according to exemplary embodiments. 
     Referring to  FIG. 5 , the I/O circuit  300  may include a strobe controller  310   a , an internal strobe signal generator  320 , a data sampling circuit  370 , an output strobe signal generator  380  and a data transmitter  390 . 
     The strobe controller  310   a  may generate a strobe control signal SCS in response to the strobe mode signal SMS. The strobe controller  310   a  may also provide the strobe control signal SCS to the internal strobe signal generator  320  and the output strobe signal generator  380 . The strobe control signal SCS may include one or more bits. 
     The internal strobe signal generator  320  generates internal strobe signals IDQSi based on one of differential data strobe signal pairs DQSi and DQSiB and single-ended data strobe signals DQSi which are selected from the differential strobe signal pairs DQSi and DQSiB, in response to the strobe control signal SCS. For example, the internal strobe signal generator  320 , in the first data strobe mode, may generate the internal strobe signals IDQSi based on the differential data strobe signal pairs DQSi and DQSiB, in response to the strobe control signal SCS. For example, the internal strobe signal generator  320 , in the second data strobe mode, may generate the internal strobe signals IDQSi based on the single-ended data strobe signals DQSi, in response to the strobe control signal SCS. 
     The data sampling circuit  370  may sample the data DQs based on the internal strobe signals IDQSi to provide the data DQs to the I/O data buffer  270 , i.e. inside of the semiconductor memory device  200   a.    
     The internal strobe signal generator  320  and the data sampling circuit  370  may be used in the write operation of the semiconductor memory device  200   a.    
     The output strobe signal generator  380  may generate one of the differential data strobe signal pairs DQSi and DQSiB and the single-ended data strobe signals DQSi in response to the strobe control signal SCS. The output strobe signal generator  380  may provide the data transmitter  390  with one of the differential data strobe signal pairs DQSi and DQSiB and the single-ended data strobe signals DQSi. The data transmitter  390  may transmit the data DQs from the I/O data buffer  270  to the memory controller  100  in synchronization with one of the differential data strobe signal pairs DQSi and DQSiB and the single-ended data strobe signals DQSi. 
     For example, the output strobe signal generator  380 , in the first data strobe mode, may generate the differential data strobe signal pairs DQSi and DQSiB in response to the strobe control signal SCS and, in the second data strobe mode, may generate the single-ended data strobe signals DQSi in response to the strobe control signal SCS. 
     The output strobe signal generator  380  and the data transmitter  390  may be used in the read operation of the semiconductor memory device  200   a.    
       FIG. 6  illustrates an example of the strobe controller  310   a  in the I/O circuit of  FIG. 5  according to exemplary embodiments. 
     Referring to  FIG. 6 , a strobe controller  310   b  may include a fuse circuit  311  and fuse signal combination logic  317 . 
     The fuse circuit  311  includes multiple fuses  312 ˜ 315 . A power supply voltage VDD is applied to first ends of the fuses  312 ˜ 315 , and second ends of the fuses  312 ˜ 315  are connected to the fuse signal combination logic  317 . The power voltage VDD applied to the fuses  312 ˜ 315  while the fuses  312 ˜ 315  are connected to the fuse signal combination logic  317  is applied to the fuse signal combining unit  417 . The power supply voltage VDD applied to the fuses  312 ˜ 315  while the fuses  312 ˜ 315  are not connected to the fuse signal combination logic  317  is not applied to the fuse signal combination logic  317 . 
     The fuse signal combination logic  317  may output the strobe control signals SCS according to which of the fuses  312 ˜ 315  are disconnected and connected to the fuse signal combination logic  317 . For example, the fuse signal combination logic  317  outputs the strobe control signal SCS corresponding to the first data strobe mode when only the fuse  312  is disconnected and the remaining fuses  313 ˜ 315  are connected. For example, the fuse signal combination logic  317  outputs the strobe control signal SCS corresponding to the second data strobe mode when the fuses  312  and  313  are disconnected and the remaining fuses  314  and  315  are connected. 
     The strobe controller  310   b  may generate the strobe control signal SCS in response to internally generated signals. 
       FIG. 7  illustrates an example of the internal strobe signal generator  320  and the data sampling circuit  370  in the I/O circuit of  FIG. 5 . 
     In  FIG. 7 , it is assumed that i in  FIG. 5  corresponds to 8. That is, there will be description on a case that the memory controller  100  and the semiconductor memory device  200   a  exchange 64-bit data DQs using 8 differential data strobe signal pairs or 8 single-ended data strobe signals. 
     Referring to  FIG. 7 , the internal strobe signal generator  320  includes multiple unit signal generators  321 ˜ 328  and the data sampling circuit  370  includes multiple data samplers  371 ˜ 378 . 
     The unit signal generator  321  may include a comparator  331  and a multiplexer  341 . The multiplexer  341  may select one of a first complementary data strobe signal DQS 1 B and a reference voltage VERF in response to a selection signal SS to output the selected one. 
     The selection signal SS may be included in the strobe control signal SCS. When the strobe mode signal SMS indicates the first data strobe mode, the multiplexer  341  may output the first complementary data strobe signal DQS 1 B in response to the selection signal SS. When the strobe mode signal SMS indicates the second data strobe mode, the multiplexer  341  may output the reference voltage VREF in response to the selection signal SS. The comparator  331  may compare a first true data strobe signal DQS 1  and an output of the multiplexer  341  to output an internal strobe signal IDQS 1  indicating a result of comparison of the first true data strobe signal DQS 1  and the output of the multiplexer  341 . Therefore, the comparator  331  may compare the first true data strobe signal DQS 1  and the first complementary data strobe signal DQS 1 B to output the internal strobe signal IDQS 1  in the first data strobe mode. The comparator  331  may compare the first true data strobe signal DQS 1  and the reference voltage VREF to output the internal strobe signal IDQS 1  in the second data strobe mode. In the second data strobe mode, the first true data strobe signal DQS 1  may serve as a first single-ended data strobe signal. 
     The unit signal generator  328  may include a comparator  338  and a multiplexer  348 . The multiplexer  348  may select one of eighth complementary data strobe signal DQS 8 B and the reference voltage VERF in response to the selection signal SS to output the selected one. 
     The comparator  338  may compare an eighth true data strobe signal DQS 8  and an output of the multiplexer  348  to output an internal strobe signal IDQS 8  indicating a result of comparison of the eighth true data strobe signal DQS 8  and the output of the multiplexer  348 . Therefore, the comparator  338  may compare the eighth true data strobe signal DQS 8  and the eighth complementary data strobe signal DQS 8 B to output the internal strobe signal IDQS 8  in the first data strobe mode. The comparator  331  may compare the first true data strobe signal DQS 8  and the reference voltage VREF to output the internal strobe signal IDQS 8  in the second data strobe mode. In the second data strobe mode, the eighth true data strobe signal DQS 8  may serve as an eighth single-ended data strobe signal. 
     Configuration and operation of each of the remaining unit signal generators  322 ˜ 327  are substantially the same as configuration and operation of each of the unit signal generators  321  and  328 , and thus detailed description on the remaining unit signal generators  322 ˜ 327  will be omitted. 
     The data sampler  371  samples data bits DQ 1 ˜DQ 8  in synchronization with the first internal strobe signal IDQS 1  to provide the sampled data bits to the I/O data buffer  270 . The data sampler  378  samples data bits DQ 57 ˜DQ 64  in synchronization with the eighth internal strobe signal IDQS 6  to provide the sampled data bits to the I/O data buffer  270 . Operation of each of the remaining data samplers (not illustrated) is substantially the same as operation of each of the data samplers  371  and  378 , and thus detailed description on the remaining data samplers will be omitted. 
     As is noted from  FIG. 8 , the memory system  30  of  FIG. 2  may sample eight data bits using one differential data strobe signal pair in the first data strobe mode and may sample eight data bits using one single-ended data strobe signal in the second data strobe mode. When the memory controller  100  performs a write operation of 64-bit data DQs on the semiconductor memory device  200   a , the memory system  30  uses 16 data strobe pins (or 8 differential data strobe signal pairs) in the first data strobe mode and uses 8 data strobe pins (or 8 single-ended data strobe signals) in the second data strobe mode. Therefore, power consumption in the second data strobe mode may be reduced than in the first data strobe mode. 
       FIG. 8  is a timing diagram illustrating operation of the memory system of  FIG. 2 . 
     Referring to  FIGS. 2 through 8 , during a first interval INT 11  in which the memory system  30  operates in the first data strobe mode in which the frequency of the clock signal CLK is greater than the reference frequency, the internal strobe signal generator  320  generates the internal strobe signals IDQS 1 ˜IDQS 8  using 8 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B. The data sampling circuit  370  samples the data bits DQ 1 ˜DQ 64  in synchronization with the internal strobe signals IDQS 1 ˜IDQS 8 . That is, each of the data samplers  371 ˜ 378  samples 8 data bits of data bits DQ 1 ˜DQ 8 , . . . , DQ 57 ˜DQ 64  using each of 8 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B in the first data strobe mode. 
     When the memory controller  100  is to change a frequency of the clock signal CLK, the memory controller  100  halts toggling of the clock signal CLK. The differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B do not toggle during a second interval INT 12  in which the clock signal CLK does not toggle. During the second interval INT 12 , the memory controller  100  changes the data strobe mode of the memory system  30  from the first data strobe mode to the second data strobe mode by setting the mode register  221  to change the write latency and the read latency. The memory controller  100  changes the data strobe mode by the test mode register set signal TMRS or by changing configuration of the fuse circuit  311  in  FIG. 6 . 
     When changing of the data strobe mode of the memory system  30  is complete, the memory controller  100  provides the semiconductor memory device  200   a  with the clock signal CLK having a frequency smaller than or equal to the reference frequency. 
     During a third interval INT 13  in which the memory system  30  operates in the second data strobe mode in which the frequency of the clock signal CLK is smaller than or equal to the reference frequency, the internal strobe signal generator  320  generates the internal strobe signals IDQS 1 ˜IDQS 8  using 8 single-ended data strobe signals DQS 1 ˜DQS 8 . The data sampling circuit  370  samples the data bits DQ 1 ˜DQ 64  in synchronization with the internal strobe signals IDQS 1 ˜IDQS 8 . That is, each of the data samplers  371 ˜ 378  samples 8 data bits of data bits DQ 1 ˜DQ 8 , . . . , DQ 57 ˜DQ 64  using each of 8 single-ended data strobe signals DQS 1 ˜DQS 8  in the second data strobe mode. 
       FIG. 9  illustrates a portion of the I/O circuit of  FIG. 5  according to exemplary embodiments. 
     Referring to  FIG. 9 , the I/O circuit  300  of  FIG. 5  may further include a repeater  360  connected between the internal strobe signal generator  320  and the data sampling circuit  370 . When the I/O circuit  300  includes the repeater  360 , each of enable signal EN 1 ˜EN 8  may be applied to each of the unit signal generators  321 ˜ 328 . The enable signal EN 1 ˜EN 8  may be included in the strobe control signal SCS. 
     When the strobe mode signal SMS indicates the first data strobe mode, as described with reference to  FIG. 7 , each of the multiplexers  341 ˜ 348  selects each of the complementary data strobe signals DQS 1 B˜DQS 8 B. Each of the comparators  331 ˜ 338  compares each of the 8 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B to output each of first internal strobe signals IDQS 1 ˜IDQS 8 . The repeater  360  buffers the first internal strobe signals IDQS 1 ˜IDQS 8  to provide second internal strobe signal IIDQS 1 ˜IIDQS 8  to the data samplers  371 ˜ 378 . In the first data strobe mode, operation of the circuit of  FIG. 7  is substantially the same as operation of the circuit of  FIG. 9 . 
     When the strobe mode signal SMS indicates that the frequency of the clock signal CLK is smaller than or equal to the reference frequency, the memory system  30  of  FIG. 2  may operate in a second sub data strobe mode or in a third sub data strobe mode. In the second sub data strobe mode, the semiconductor memory device  200   a  may sample the data bits DQ 1 ˜DQ 64  using a portion of 8 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B to reduce power consumption. In the third sub data strobe mode, the semiconductor memory device  200   a  may sample the data bits DQ 1 ˜DQ 64  using a portion of 8 single-ended data strobe signals DQS 1 ˜DQS 8  to reduce power consumption. 
     When the strobe mode signal SMS indicates the second sub data strobe mode, the enable signals EN 1 ˜EN 4  of the enable signals EN 1 ˜EN 4  are activated. The unit signal generators  321 ˜ 324  are enabled in response to the enable signals EN 1 ˜EN 4 . Each of the multiplexers  341 ˜ 344  selects each of the complementary data strobe signals DQS 1 B˜DQS 4 B in response to the selection signal SS. Each of the comparators  331 ˜ 334  compares each of the 4 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B to output each of the first internal strobe signals IDQS 1 ˜IDQS 4 . The repeater  360  buffers the first internal strobe signals IDQS 1 ˜IDQS 4  to provide second internal strobe signal IIDQS 1 ˜IIDQS 8  to each of the data samplers  371 ˜ 378  in response to a repeater control signal RCS. The repeater control signal RCS may be included in the strobe control signal SCS. 
     That is, the first internal data strobe signal IDQS 1  is repeated as the second internal data strobe signals IIDQS 1  and IIDQS 2 . The first internal data strobe signal IDQS 2  is repeated as the second internal data strobe signals IIDQS 3  and IIDQS 4 . The first internal data strobe signal IDQS 3  is repeated as the second internal data strobe signals IIDQS 5  and IIDQS 6 . The first internal data strobe signal IDQS 4  is repeated as the second internal data strobe signals IIDQS 7  and IIDQS 8 . In the second sub data strobe mode, the semiconductor memory device  200   a  may sample the data bits DQ 1 ˜DQ 64  using 4 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B to reduce power consumption. In the first data strobe mode 16 data strobe pins are used for write/read operation while in the second sub data strobe mode 8 data pins are used for write/read operation to/from reduce power consumption. 
     When the strobe mode signal SMS indicates the third sub data strobe mode, the enable signals EN 1 ˜EN 4  of the enable signals EN 1 ˜EN 4  are activated. The unit signal generators  321 ˜ 324  are enabled in response to the enable signals EN 1 ˜EN 4 . Each of the multiplexers  341 ˜ 344  selects the reference voltage VREF in response to the selection signal SS. Each of the comparators  331 ˜ 334  compares each of the 4 single-ended data strobe signals DQS 1 ˜DQS 4  with the reference voltage VREF to output each of the first internal strobe signals IDQS 1 ˜IDQS 4 . The repeater  360  buffers the first internal strobe signals IDQS 1 ˜IDQS 4  to provide second internal strobe signal IIDQS 1 ˜IIDQS 8  to each of the data samplers  371 ˜ 378  in response to the repeater control signal RCS. 
     That is, the first internal data strobe signal IDQS 1  is repeated as the second internal data strobe signals IIDQS 1  and IIDQS 2 . The first internal data strobe signal IDQS 2  is repeated as the second internal data strobe signals IIDQS 3  and IIDQS 4 . The first internal data strobe signal IDQS 3  is repeated as the second internal data strobe signals IIDQS 5  and IIDQS 6 . The first internal data strobe signal IDQS 4  is repeated as the second internal data strobe signals IIDQS 7  and IIDQS 8 . In the third sub data strobe mode, the semiconductor memory device  200   a  may sample the data bits DQ 1 ˜DQ 64  using 4 single-ended data strobe signal pairs DQS 1 ˜DQS 4  to reduce power consumption. In the first data strobe mode 16 data strobe pins are used for a write/read operation, while in the second sub data strobe mode 4 data pins are used for a write/read operation to reduce power consumption. 
     The semiconductor memory device  200   a , in the second sub data strobe mode or in the third sub data strobe mode, may perform sampling operation on data bits more than in the first data strobe mode, based on one differential data strobe signal pair or one single-ended data strobe signal. 
     The second sub data strobe mode or the third sub data strobe mode may be set by cutting one or more of the fuses  312 ˜ 315  in the fuse circuit  311  in  FIG. 6 . 
       FIG. 10  is a timing diagram illustrating operation of the memory system of  FIG. 2 . 
     Referring to  FIGS. 2 through 6, 9 and 10 , during a first interval INT 21  in which the memory system  30  operates in the first data strobe mode, the internal strobe signal generator  320  generates the first internal strobe signals IDQS 1 ˜IDQS 8  using 8 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B. The repeater  360  generates the second internal strobe signals IIDQS 1 ˜IIDQS 8  and the data sampling circuit  370  samples the data bits DQ 1 ˜DQ 64  in synchronization with the second internal strobe signals IIDQS 1 ˜IIDQS 8  as described with reference to  FIG. 9 . That is, each of the data samplers  371 ˜ 378  samples 8 data bits of data bits DQ 1 ˜DQ 8 , . . . , DQ 57 ˜DQ 64  using each of 8 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B in the first data strobe mode. 
     When the memory controller  100  is to change a frequency of the clock signal CLK, the memory controller  100  halts toggling of the clock signal CLK. The differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B do not toggle during a second interval INT 22  in which the clock signal CLK does not toggle. During the second interval INT 22 , the memory controller  100  changes the data strobe mode of the memory system  30  from the first data strobe mode to the second sub data strobe mode by setting the mode register  221  to change the write latency and the read latency. The memory controller  100  changes the data strobe mode by the test mode register set signal TMRS or by changing configuration of the fuse circuit  311  in  FIG. 6 . 
     When changing of the data strobe mode of the memory system  30  is complete, the memory controller  100  provides the semiconductor memory device  200   a  with the clock signal CLK having a frequency smaller than or equal to the reference frequency. 
     During a third interval INT 23  in which the memory system  30  operates in the second sub data strobe mode in which the frequency of the clock signal CLK is smaller than or equal to the reference frequency, the internal strobe signal generator  320  generates the first internal strobe signals IDQS 1 ˜IDQS 4  using 4 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B. The repeater  360  generates the second internal strobe signals IIDQS 1 ˜IIDQS 8  and the data sampling circuit  370  samples the data bits DQ 1 ˜DQ 64  in synchronization with the second internal strobe signals IIDQS 1 ˜IIDQS 8  as described with reference to  FIG. 9 . That is, each of the data samplers  371 ˜ 378  samples 16 data bits of data bits DQ 1 ˜DQ 8 , . . . , DQ 57 ˜DQ 64  using each of 4 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B in the second sub data strobe mode. 
       FIG. 11  illustrates the memory system of  FIG. 2  in the first data strobe mode. 
     Referring to  FIG. 11 , as described with reference to  FIG. 8 , when the memory system  30  operates in the first data strobe mode in which the frequency of the clock signal CLK is greater than the reference frequency, the memory controller  100  and the semiconductor memory device  200   a  may exchange data bits DQ 1 ˜DQ 64  using 8 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B. The memory controller  100  may include a clock generator  120  that generates the clock signal CLK and a phase-locked loop (PLL) circuit  110  that generates the data strobe signals DQS based on the clock signal CLK. The PLL circuit  110  may adjust a number of the strobe signals DQS in response to a control signal PCTL from a central processing unit (CPU) in the memory controller  100 . 
       FIG. 12  illustrates the memory system of  FIG. 2  in the second data strobe mode. 
     Referring to  FIG. 12 , as described with reference to  FIG. 8 , when the memory system  30  operates in the second data strobe mode in which the frequency of the clock signal CLK is smaller than or equal to the reference frequency, the memory controller  100  and the semiconductor memory device  200   a  may exchange data bits DQ 1 ˜DQ 64  using 8 single-ended data strobe signals DQS 1 ˜DQS 8 . The PLL circuit  110  may generate the single-ended data strobe signals DQS 1 ˜DQS 8  in response to the control signal PCTL from a CPU in the memory controller  100 . 
       FIG. 13  illustrates the memory system of  FIG. 2  in the second sub data strobe mode or in the third sub data strobe mode. 
     Referring to  FIG. 13 , as described with reference to  FIGS. 9 and 10 , when the memory system  30  operates in the second sub data strobe mode, the memory controller  100  and the semiconductor memory device  200   a  may exchange data bits DQ 1 ˜DQ 64  using 4 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B. In addition, when the memory system  30  operates in the third sub data strobe mode, the memory controller  100  and the semiconductor memory device  200   a  may exchange data bits DQ 1 ˜DQ 64  using 4 single-ended data strobe signals DQS 1 ˜DQS 4 . The PLL circuit  110  may generate the differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B or the single-ended data strobe signals DQS 1 ˜DQS 4  in response to the control signal PCTL from a CPU in the memory controller  100 . 
       FIG. 14  illustrates operation of the I/O circuit of  FIG. 9  in the second sub data strobe mode. 
     Referring to  FIG. 14 , when the strobe control signal SMS indicates the second sub data strobe mode, the internal strobe signal generator  320  generates 4 first internal strobe signals IDQS 1 ˜IDQS 4  by comparing 4 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B. The repeater  360  generates 8 second internal strobe signals IIDQS 1 ˜IIDQS 8  by repeating 4 first internal strobe signals IDQS 1 ˜IDQS 4 . That is, the first internal data strobe signal IDQS 1  is repeated as the second internal data strobe signals IIDQS 1  and IIDQS 2 . The first internal data strobe signal IDQS 2  is repeated as the second internal data strobe signals IIDQS 3  and IIDQS 4 . The first internal data strobe signal IDQS 3  is repeated as the second internal data strobe signals IIDQS 5  and IIDQS 6 . The first internal data strobe signal IDQS 4  is repeated as the second internal data strobe signals IIDQS 7  and IIDQS 8 . In the second sub data strobe mode, the semiconductor memory device  200   a  may use each of the 4 differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B for sampling 16 data bits of the data bits DQ 1 ˜DQ 64  to reduce power consumption. 
     As mentioned above, the memory system may reduce power consumption by reducing a second number of data strobe signals used when the frequency of the clock signal is smaller than or equal to the reference frequency compared to a first number of data strobe signals used when the frequency of the clock signal is greater than the reference frequency. 
       FIG. 15  is a structural diagram illustrating a semiconductor memory device according to exemplary embodiments. 
     Referring to  FIG. 15 , a semiconductor memory device  600  may include first through sth semiconductor integrated circuit layers LA 1  through LAs, in which the lowest first semiconductor integrated circuit layer LA 1  is assumed to be an interface or control chip and the other semiconductor integrated circuit layers LA 2  through LAs are assumed to be slave chips including core memory chips. The first through nth semiconductor integrated circuit layers LA 1  through LAs may transmit and receive signals therebetween through through-silicon-vias (TSVs). The lowest first semiconductor integrated circuit layer LA 1  as the interface or control chip may communicate with an external memory controller through a conductive structure formed on an external surface. A description will be made regarding structure and an operation of the semiconductor memory device  600  by mainly using the first semiconductor integrated circuit layer LA 1  or  610  as the interface or control chip and the nth semiconductor integrated circuit layer LAs or  620  as the slave chip. 
     The first semiconductor integrated circuit layer  610  may include various peripheral circuits for driving a memory region  621  provided in the sth semiconductor integrated circuit layer  620 . For example, the first semiconductor integrated circuit layer  610  may include a row (X)-driver  6101  for driving word-lines of a memory, a column (Y)-driver  6102  for driving bit lines of the memory, a data I/O circuit (Din/Dout)  6103  for controlling input/output of data, a command buffer (CMD)  6104  for receiving a command CMD from outside and buffering the command CMD, and an address buffer (ADDR)  6105  for receiving an address from outside and buffering the address. A memory region  621  may include multiple memory cells with reference to  FIG. 4 . 
     The first semiconductor integrated circuit layer  610  may further include a control logic  6107 . The control logic  6107  may control an access to the memory region  621  based on a command and an address signal from a memory controller. 
     The sth semiconductor integrated circuit layer  620  may include the memory region  621  and peripheral circuit regions  622  in which peripheral circuits for reading/writing data of the memory region  621 , e.g., a row decoder, a column decoder, a bit line sense amplifier, etc. (not illustrated) are arranged. 
     The data I/O circuit  6103  may employ the I/O circuit  300  of  FIG. 5 . Therefore, the semiconductor memory device  600  may reduce power consumption by reducing a second number of data strobe signals used when the frequency of the clock signal is smaller than or equal to the reference frequency compared to a first number of data strobe signals used when the frequency of the clock signal is greater than the reference frequency as described with reference to  FIGS. 2 through 14 . 
     In addition, a three-dimensional (3D) memory array is provided in semiconductor memory device  600 . The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. The following patent documents, which are hereby incorporated by reference, describe suitable configurations for the 3D memory arrays, in which the three-dimensional memory array is configured as multiple levels, with word-lines and/or bit-lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648. 
       FIG. 16  is a flow chart illustrating a method of operating a semiconductor memory device according to exemplary embodiments. 
     Referring to  FIGS. 2 through 14 and 16 , in a method of operating a semiconductor memory device that includes a memory cell array, it is determined whether a frequency of the clock signal CLK from a memory controller  100  is smaller than or equal to a reference frequency (S 100 ). The semiconductor memory device  200   a  performs a memory operation on the memory cell array using a different number of data strobe signals according to the frequency of the clock signal (S 200 ). 
     For example, when the frequency of the clock signal CLK is greater than the reference frequency (NO in S 100 ), the semiconductor memory device  200   a  performs the memory operation on the memory cell array (of bank arrays)  240 A˜ 240 D using differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B as described above. When the frequency of the clock signal CLK is smaller than or equal to the reference frequency (YES in S 100 ), the semiconductor memory device  200   a  performs the memory operation on the memory cell array (of bank arrays)  240 A˜ 240 D using the differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B or using single-ended data strobe signals DQS 1 ˜DQS 4  as described above. 
     When the frequency of the clock signal CLK is greater than the reference frequency, the semiconductor memory device  200   a  performs the memory operation in synchronization with the clock signal CLK using a first number of data strobe signals (S 210 ). When the frequency of the clock signal CLK is smaller than or equal to the reference frequency, the semiconductor memory device  200   a  performs the memory operation in synchronization with the clock signal CLK using a second number of data strobe signals (S 230 ). The first number may be greater than the second number. The memory operation may include the write operation on the memory cell array (of bank arrays)  240 A˜ 240 D and the read operation on the memory cell array (of bank arrays)  240 A˜ 240 D. 
       FIG. 17  is a flow chart illustrating a method of operating a semiconductor memory device according to exemplary embodiments. 
     Referring to  FIGS. 2 through 14 and 17 , in a method of operating a semiconductor memory device that includes a memory cell array, the semiconductor memory device  200   a  performs a memory operation on the memory cell array (of bank arrays)  240 A˜ 240 D in synchronization with the clock signal CLK using a first number of data strobe signals (S 310 ). The semiconductor memory device  200   a  may perform the memory operation on the memory cell array (of bank arrays)  240 A˜ 240 D using differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 8 /DQS 8 B as described above. 
     It is determined whether to change the frequency of the clock signal (S 320 ). When it is determined that the frequency of the clock signal CLK is not to be changed (NO in S 320 ), the process returns to the step (S 310 ). When it is determined that the frequency of the clock signal CLK is to be changed (YES in S 320 ), the memory controller  100  changes the frequency of the clock signal CLK to have a frequency smaller than or equal to the reference frequency (S 330 ). The semiconductor memory device  200   a  performs the memory operation on the memory cell array (of bank arrays)  240 A˜ 240 D in synchronization with the clock signal CLK using a second number, which is smaller than the first number, of data strobe signals (S 340 ). The semiconductor memory device  200   a  may perform the memory operation on the memory cell array (of bank arrays)  240 A˜ 240 D using the single-ended data strobe signals DQS 1 ˜DQS 8 , the differential data strobe signal pairs DQS 1 /DQS 1 B˜DQS 4 /DQS 4 B, or the single-ended data strobe signals DQS 1 ˜DQS 4 . 
     According to exemplary embodiments, the methods may reduce power consumption by reducing a second number of data strobe signals used when the frequency of the clock signal is smaller than or equal to the reference frequency compared to a first number of data strobe signals used when the frequency of the clock signal is greater than the reference frequency. 
       FIG. 18  is a block diagram illustrating a mobile system that includes the semiconductor memory device according to exemplary embodiments. 
     Referring to  FIG. 18 , a mobile system  700  may include an application processor  710 , a connectivity unit  720 , a user interface  730 , a nonvolatile memory device  740 , a memory sub system  750  and a power supply  760 . The memory sub system  750  may include a memory controller  751  and a semiconductor memory device  750  such as DRAM. 
     The application processor  710  may execute applications, such as a web browser, a game application, a video player, etc. The connectivity unit  720  may perform wired or wireless communication with an external device. 
     The memory sub system  750  may store data processed by the application processor  710  or operate as a working memory. The memory sub system  750  may employ the memory system  30  of  FIG. 2 . Therefore, the memory sub system  750  may reduce power consumption by reducing a second number of data strobe signals used when the frequency of the clock signal is smaller than or equal to the reference frequency compared to a first number of data strobe signals used when the frequency of the clock signal is greater than the reference frequency. 
     The nonvolatile memory device  740  may store a boot image for booting the mobile system  700 . The user interface  730  may include at least one input device, such as a keypad, a touch screen, etc., and at least one output device, such as a speaker, a display device, etc. The power supply  760  may supply a power supply voltage to the mobile system  700 . 
     In some embodiments, the mobile system  700  and/or components of the mobile device  700  may be packaged in various forms. 
     The present disclosure may be applied to systems using semiconductor memory devices. The present disclosure may be applied to systems such as be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc. 
     The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.