Patent Publication Number: US-9892792-B2

Title: Operating method of a nonvolatile memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This U.S. non-provisional patent application is a continuation application of U.S. patent application Ser. No. 14/997,730, filed on Jan. 18, 2016, now U.S. Pat. No. 9,620,219, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0009951, filed on Jan. 21, 2015, the disclosures of which are incorporated by reference herein in their entireties. 
    
    
     TECHNICAL FIELD 
     The inventive concept relates to a semiconductor memory, and more particularly, to a nonvolatile memory device and an operating method of the nonvolatile memory device. 
     DISCUSSION OF RELATED ART 
     A storage device may store data responsive to a control of a host device such as a computer, a smart phone, a smart pad, etc. A storage device may include a hard disk drive (HDD) which stores data on a magnetic disk, or a semiconductor memory which stores data in a nonvolatile memory. The semiconductor memory may be a solid state drive (SSD) or a memory card. 
     A nonvolatile memory may include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. 
     SUMMARY 
     In accordance with an exemplary embodiment of the inventive concept, a method of operating a nonvolatile memory device comprises: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution. 
     An upper limit of the first threshold voltage distribution may be higher than a verify voltage and an upper limit of the second threshold voltage distribution may be lower than the verify voltage. 
     The second programming may not be performed when an upper limit of the first threshold voltage distribution is lower than a verify voltage. 
     The target transistor may be a ground select transistor or a memory cell. 
     The second programming may include: applying a boosted voltage to a drain of the target transistor; applying a common source line voltage to a source of the target transistor; and applying a negative voltage to a gate of the target transistor. 
     The second programming may be a hot hole injection operation. 
     The first programming may comprise: supplying a low voltage to a channel of the target transistor; and supplying a high voltage to a gate of the target transistor. 
     In accordance with an exemplary embodiment of the inventive concept, a method of operating a nonvolatile memory device including a plurality of strings, each string including a plurality of sting selection transistors, a plurality of memory cells, and a plurality of ground selection transistors sequentially stacked in a direction perpendicular to a surface of a substrate on which the cell string is disposed, comprises: programming a ground selection transistor of a selected cell string, wherein the programming comprises: applying a boosted voltage to a drain of the ground selection transistor of the selected string; applying a common source line voltage to a source of the ground selection transistor of the selected string; and applying a negative voltage to a gate of the ground selection transistor of the selected string, wherein a width of threshold voltage distribution of the ground selection transistor of the selected string is decreased. 
     The boosting voltage may be generated by: initially turning on the string selection transistors of the selected string; supplying a bit line voltage to a bit line connected to the selected string; turning off the string selection transistors of the selected string; and applying a pass voltage to the memory cells of the selected string. 
     A difference between the boost voltage and the negative voltage may cause a hot hole at the ground selection transistor of the selected string. 
     The bit line voltage may be a low voltage, the common source line voltage may be a low voltage, the turned off string selection transistors may be applied with a high voltage, and an unselected ground selection transistor may be applied with a high voltage. 
     The string selection transistors, the memory cells and the ground selection transistors of the selected string may be charge trap flash cells. 
     The method may further comprise: inhibiting programming of a ground selection transistor of an unselected string while the ground selection transistor of the selected string is programmed. 
     The program inhibiting may comprise: turning on the string selection transistors of the unselected string; supplying a bit line voltage to a bit line connected to the unselected string, wherein the bit line voltage is a low voltage; and applying a pass voltage to the memory cells of the unselected string. 
     The string selection transistors, the memory cells and the ground selection transistors of the unselected string may be charge trap flash cells. 
     In accordance with an exemplary embodiment of the inventive concept, a method of operating a nonvolatile memory device including a plurality of strings, each string including at least one string selection transistor, a plurality of memory cells, and at least one ground selection transistor sequentially stacked in a direction perpendicular to a surface of a substrate on which the strings are disposed, wherein the string selection transistors of at least two strings are connected to a string selection line, the ground selection transistors of the at least two strings are connected to a ground selection line, each memory cell of the at least two strings are connected to a wordline, comprises: applying a common source line voltage to a selected string and an unselected string; applying a negative voltage to the ground selection line connected to the selected string and the unselected string; applying a pass voltage to the wordlines of the unselected string and the selected string; applying a ground voltage to a bit line of the unselected string to turn on the string selection transistor of the unselected string; and turning on, and then, turning off the string selection transistor of the selected string to apply a boost voltage to the ground selection transistor of the selected string. 
     The common source line voltage may be a ground voltage. 
     The steps of applying a common source line voltage, applying a negative voltage, applying a pass voltage, applying a ground voltage and turning on and off the string selection transistor may be performed when a threshold voltage distribution of the ground selection transistor of the selected string is greater than a verify voltage. 
     After performing the steps of applying a common source line voltage, applying a negative voltage, applying a pass voltage, applying a ground voltage and turning on and off the string selection transistor, the threshold voltage distribution of the ground selection transistor of the selected string may be less than the verify voltage. 
     The at least one string selection transistor, the memory cells and the at least one ground selection transistor of each of the strings may be charge trap flash cells. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings. 
         FIG. 1  is a block diagram illustrating a nonvolatile memory in accordance with an exemplary embodiment of the inventive concept. 
         FIG. 2  is a circuit diagram illustrating a memory block in accordance with an exemplary embodiment of the inventive concept. 
         FIG. 3  is a flowchart illustrating an operating method of a nonvolatile memory in accordance with an exemplary embodiment of the inventive concept. 
         FIG. 4  illustrates changes of threshold voltages of cell transistors in the operating method of  FIG. 3 , according to an exemplary embodiment of the inventive concept. 
         FIG. 5  is a flowchart illustrating a first program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 6  is a table illustrating voltages supplied to a memory block in the first program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 7  is a table illustrating voltages supplied to a memory block in the first program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 8  is a flowchart illustrating a second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 9  is a table illustrating voltages supplied to a memory block in the second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 10  illustrates voltages applied to a selected cell string in the second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 11  illustrates voltages applied to unselected cell strings in the second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 12  illustrates voltages applied to unselected cell strings in the second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 13  illustrates voltages applied to unselected cell strings in the second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 14  is a table illustrating voltages supplied to a memory block in the second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 15  illustrates voltages applied to a cell string selected in the second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 16  is a flowchart illustrating a second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 17  is a timing diagram illustrating control of a level of a pass voltage in a second program operation, according to an exemplary embodiment of the inventive concept. 
         FIG. 18  is a flowchart illustrating an operating method of a nonvolatile memory in accordance with an exemplary embodiment of the inventive concept. 
         FIG. 19  is a flowchart illustrating an operating method of a nonvolatile memory in accordance with an exemplary embodiment of the inventive concept. 
         FIG. 20  illustrates changes of threshold voltages of cell transistors in the operating method of  FIG. 19 , according to an exemplary embodiment of the inventive concept. 
         FIG. 21  is a block diagram illustrating a storage device in accordance with an exemplary embodiment of the inventive concept. 
         FIG. 22  is a block diagram illustrating a memory controller in accordance with an exemplary embodiment of the inventive concept. 
         FIG. 23  is a block diagram illustrating a computing device in accordance with an exemplary embodiment of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments thereof are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers may refer to like elements throughout the attached drawings and written description. 
       FIG. 1  is a block diagram illustrating a nonvolatile memory  110  in accordance with an exemplary embodiment of the inventive concept. Referring to  FIG. 1 , the nonvolatile memory  110  includes a memory cell array  111 , an address decoder circuit  113 , a page buffer circuit  115 , a data input/output circuit  117 , and a control logic circuit  119 . 
     The memory cell array  111  includes a plurality of memory blocks BLK 1 ˜BLKz, each of which has a plurality of memory cells. Each memory block may be connected to the address decoder circuit  113  through at least one ground select line GSL, a plurality of word lines WL, and at least one string select line SSL. Each memory block may be connected to the page buffer circuit  115  through a plurality of bit lines BL. The memory blocks BLK 1 ˜BLKz may be connected to the bit lines BL in common. Memory cells of the memory blocks BLK 1 ˜BLKz may have the same structures. Each of the memory blocks BLK 1 ˜BLKz may be an erase operation unit. Memory cells of the memory cell array  111  may be erased by one memory block unit. Memory cells that belong to the same memory block may be erased all at once. In an exemplary embodiment of the inventive concept, each memory block may be divided into a plurality of sub blocks. Each sub block may be an erase operation unit. 
     The address decoder circuit  113  is connected to the memory cell array  111  through a plurality of ground select lines GSL, a plurality of word lines WL, and a plurality of string select lines SSL. The address decoder circuit  113  operates according to a control of the control logic circuit  119 . The address decoder circuit  113  can receive a first address ADDR 1  from a memory controller. The address decoder circuit  113  decodes the received first address ADDR 1  and controls voltages applied to word lines WL according to the decoded address. 
     For example, in a program operation, the address decoder circuit  113  may apply a program voltage VPGM to a selected word line of a selected memory block indicated by the first address ADDR 1  and apply a pass voltage VPASS to unselected word lines of the selected memory block. In a read operation, the address decoder circuit  113  may apply a select read voltage VRD to a selected word line of a selected memory block indicated by the first address ADDR 1  and apply an unselect voltage VREAD to unselected word lines of the selected memory block. In an erase operation, the address decoder circuit  113  may apply erase voltages (for example, a ground voltage or low voltages having a level similar to the ground voltage) to a selected word line of a selected memory block indicated by the first address ADDR 1 . 
     The page buffer circuit  115  is connected to the memory cell array  111  through a plurality of bit lines BL. The page buffer circuit  115  is connected to the data input/output circuit  117  through a plurality of data lines DL. The page buffer circuit  115  operates according to a control of the control logic circuit  119 . 
     The page buffer circuit  115  can store data to be programmed in memory cells of the memory cell array  111  or data read from the memory cells of the memory cell array  111 . In a program operation, the page buffer circuit  115  can store data to be programmed in the memory cells. The page buffer circuit  115  can bias the bit lines BL on the basis of the stored data. In a program operation, the page buffer circuit  115  can function as a write driver. In a read operation, the page buffer circuit  115  can sense voltages of the bit lines BL and store a sensing result. In a read operation, the page buffer circuit  115  can function as a sense amplifier. 
     The data input/output circuit  117  is connected to the page buffer circuit  115  through a plurality of data lines DL. The data input/output circuit  117  can exchange first data DATA 1  with the memory controller. 
     The data input/output circuit  117  can temporarily store the first data DATA 1  received from the memory controller. The data input/output circuit  117  can transmit the stored first data DATA 1  to the memory controller. The data input/output circuit  117  can function as a buffer memory. 
     The control logic circuit  119  receives a first command CMD 1  and a control signal CTRL from the memory controller. The control logic circuit  119  decodes the received first command CMD 1  and can control an overall operation of the nonvolatile memory  110  according to the decoded command. 
     In a read operation, the control logic circuit  119  can generate a data strobe signal DQS from a read enable signal /RE among the received control signals CTRL and output the data strobe signal DQS. In a write operation, the control logic circuit  119  can receive a data strobe signal DQS included in the control signal CTRL. 
     The control logic circuit  119  includes a program control circuit PC. The program control circuit PC can control a program operation of the nonvolatile memory  110  by controlling the address decoder circuit  113  and the page buffer circuit  115 . For example, the program control circuit PC can control the address decoder circuit  113  and the page buffer circuit  115  so that a program is performed according to a program method in accordance with an exemplary embodiment of the inventive concept. 
       FIG. 2  is a circuit diagram illustrating a memory block BLKa in accordance with an exemplary embodiment of the inventive concept. Referring to  FIG. 2 , the memory block BLKa includes a plurality of cell strings CS 11 ˜CS 21  and CS 12 ˜CS 22 . The cell strings CS 11 ˜CS 21  and CS 12 ˜CS 22  may be arranged along a row direction and a column direction to form rows and columns. 
     For example, the cell strings CS 11  and CS 12  arranged along a row direction may form a first row and the cell strings CS 21  and CS 22  arranged along a row direction may form a second row. The cell strings CS 11  and CS 21  arranged along a column direction may form a first column and the cell strings CS 12  and CS 22  arranged along a column direction may form a second column. 
     Each cell string CS 11 ˜CS 21  and CS 12 ˜CS 22  may include a plurality of cell transistors. The cell transistors include ground select transistors GSTa and GSTb, memory cells MC 1 ˜MC 6 , and string select transistors SSTa and SSTb. The ground select transistors GSTa and GSTb, the memory cells MC 1 ˜MC 6 , and the string select transistors SSTa and SSTb of each cell string may be stacked in a direction perpendicular to a plane (for example, a plane corresponding to a surface of a substrate on which the memory block BLKa is formed) on which the cell strings CS 11 ˜CS 21  and CS 12 ˜CS 22  are arranged along rows and columns. For example, the transistors of a cell string may be stacked in the height direction. 
     The cell transistors may be charge trap type transistors having threshold voltages that change depending on an amount of charge captured by an insulating layer. 
     Sources of the lowermost ground select transistors GSTa may be connected to a common source line CSL in common. 
     Control gates of the ground select transistors GSTa and GSTb of the cell strings CS 11 ˜CS 21  and CS 12 ˜CS 22  may be connected to ground select lines GSLa and GSLb respectively. The ground select transistors of the same height (or order) may be connected to the same ground select line and the ground select transistors of different heights (or orders) may be connected to different ground select lines. For example, the ground select transistors GSTa of a first height are connected to the ground select line GSLa in common and the ground select transistors GSTb of a second height are connected to the ground select line GSLb in common. 
     Ground select transistors of the same row may be connected to the same ground select line and ground select transistors of different rows may be connected to different ground select lines. For example, the ground select transistors GSTa and GSTb of the cell strings CS 11  and CS 12  of the first row are connected to a first ground select line, and the ground select transistors GSTa and GSTb of the cell strings CS 21  and CS 22  of the second row are connected to a second ground select line. 
     Control gates of memory cells located at the same height (or order) from a substrate (or ground select transistors GST) may be connected to the same word line in common and control gates of memory cells located at different heights (or orders) from the substrate may be connected to different word lines WL 1 ˜WL 6  respectively. For example, the memory cells M 1  are connected to the word line WL 1  in common. The memory cells M 2  are connected to the word line WL 2  in common. The memory cells M 3  are connected to the word line WL 3  in common. The memory cells M 4  are connected to the word line WL 4  in common. The memory cells M 5  are connected to the word line WL 5  in common. The memory cells M 6  are connected to the word line WL 6  in common. 
     At the first string select transistors SSTa of the same height (or order) of the cell strings CS 11 ˜CS 21  and CS 12 ˜CS 22 , control gates of the first string select transistors SSTa of different rows are connected to different string select lines SSL 1   a ˜SSL 2   a  respectively. For example, the first string select transistors SSTa of the cell strings CS 11  and CS 12  are connected to the string select line SSL 1   a  in common. The first string select transistors SSTa of the cell strings CS 21  and CS 22  are connected to the string select line SSL 2   a  in common. 
     At the second string select transistors SSTb of the same height (or order) of the cell strings CS 11 ˜CS 21  and CS 12 ˜CS 22 , control gates of the second string select transistors SSTb of different rows are connected to different string select lines SSL 1   b ˜SSL 2   b  respectively. For example, the second string select transistors SSTb of the cell strings CS 11  and CS 12  are connected to the string select line SSL 1   b  in common. The second string select transistors SSTb of the cell strings CS 21  and CS 22  are connected to the string select line SSL 2   b  in common. 
     Cell strings of different rows are connected to different string select lines. String select transistors of the same height (or order) of the cell strings of the same row are connected to the same string select line. String select transistors of different heights (or orders) of the cell strings of the same row are connected to different string select lines. 
     String select transistors of the cell strings of the same row may be connected to one string select line in common. For example, the string select transistors SSTa and SSTb of the cell strings CS 11  and CS 12  of the first row may be connected to one string select line in common. For example, the string select transistors SSTa may be connected to the string select line SSL 1   a  in common and the string selected transistors SSTb may be connected to the string selected line SSL 1   b  in common. The string select transistors SSTa and SSTb of the cell strings CS 21  and CS 22  of the second row may be connected to one string select line in common. For example, the string select transistors SSTa may be connected to the string select line SSL 2   a  in common and the string selected transistors SSTb may be connected to the string selected line SSL 2   b  in common. 
     Columns of the cell strings CS 11 ˜CS 21  and CS 12 ˜CS 22  are connected to different bit lines BL 1  and BL 2  respectively. For example, the string select transistors SSTb of the cell strings CS 11  and CS 21  of the first column are connected to a bit line BL 1  in common. The string select transistors SSTb of the cell strings CS 12  and CS 22  of the second column are connected to a bit line BL 2  in common. 
     The cell strings CS 11  and CS 12  may form a first plane. The cell strings CS 21  and CS 22  may form a second plane. 
     In the memory block BLKa, memory cells of each height of each plane may from a physical page. The physical page may be a read unit and a write unit of the memory cells MC 1 ˜MC 6 . For example, one plane of the memory block BLKa may be selected by the string select lines SSL 1   a , SSL 1   b , SSL 2   a  and SSL 2   b . When a turn-on voltage is supplied to the string select lines SSL 1   a  and SSL 1   b  and a turn-off voltage is supplied to the string select lines SSL 2   a  and SSL 2   b , the cell strings CS 11  and CS 12  of the first plane are connected to the bit lines BL 1  and BL 2  respectively. In other words, the first plane is selected. When a turn-on voltage is supplied to the string select lines SSL 2   a  and SSL 2   b  and a turn-off voltage is supplied to the string select lines SSL 1   a  and SSL 1   b , the cell strings CS 21  and CS 22  of the second plane are connected to the bit lines BL 1  and BL 2  respectively. In other words, the second plane is selected. In the selected plane, one row of the memory cells MC may be selected by the word lines WL 1 ˜WL 6 . In the selected row, a select voltage may be applied to the second word line WL 2  and an unselect voltage may be applied to the remaining word lines WL 1  and WL 3 ˜WL 6 . In other words, a physical page corresponding to the second word line WL 2  of the second plane may be selected by controlling the string select lines SSL 1   a , SSL 1   b , SSL 2   a  and SSL 2   b  and the word lines WL 1 ˜WL 6 . In the memory cells MC 2  of the selected physical page, a write or read operation may be performed. 
     In the memory block BLKa, an erase operation of the memory cells MC 1 ˜MC 6  may be performed by a memory block unit or a sub block unit. When an erase operation is performed by a memory block unit, memory cells MC of the memory block BLKa may be erased all at once according to an erase request (for example, an erase request from an external memory controller). When an erase operation is performed by a sub block unit, parts of the memory cells MC 1 ˜MC 6  of the memory block BLKa may be erased all at once according to an erase request (for example, an erase request from an external memory controller) and the remaining parts may be erase-prohibited. A low voltage (for example, a ground voltage or a voltage having a level similar to the ground voltage) may be supplied to a word line connected to the memory cells being erased and a word line connected to the erase-prohibited memory cells may be floated. 
     The memory block BLKa illustrated in  FIG. 2  is illustrative. The inventive concept is not limited to the memory block BLKa illustrated in  FIG. 2 . For example, the number of rows of cell strings may be increased or decreased. As the number of rows of cell strings is changed, the number of string select lines or ground select lines connected to the rows of the cell strings and the number of cell strings connected to one bit line may also be changed. 
     The number of columns of cell strings may be increased or decreased. As the number of columns of cell strings is changed, the number of bit lines connected to the columns of the cell strings and the number of cell strings connected to one string select line may also be changed. 
     Heights of cell strings may be increased or decreased. For example, the number of ground select transistors, memory cells or string select transistors that are included in each cell string may be increased or decreased. 
     Memory cells MC that belong to one physical page can correspond to at least three logical pages. For example, k (k is an integer greater than 2) number of bits can be programmed in one memory cell MC. In memory cells MC that belong to one physical page, k number of bits programmed in each memory cell MC can form k number of logical pages respectively. 
     In an exemplary embodiment of the inventive concept, a three dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells. Such associated circuitry may be above or within such substrate. The term “monolithic” may mean that layers of each level of the array are directly deposited on the layers of each underlying level of the array. 
     In an exemplary embodiment of the inventive concept, the 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may comprise a charge trap layer. Each vertical NAND string further includes at least one select transistor located over the memory cells, the at least one select transistor having the same structure as the memory cells and being formed monolithically together with the memory cells. 
     The following patent documents U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Pat. Pub. No. 2011/0233648, which are incorporated by reference herein in their entireties, describe configurations of three-dimensional memory arrays for use in accordance with an exemplary embodiment of the inventive concept. In the aforementioned patent documents, a three-dimensional memory array is configured as a plurality of levels, with word lines and/or bit lines shared between levels. 
       FIG. 3  is a flowchart illustrating an operating method of a nonvolatile memory in accordance with an exemplary embodiment of the inventive concept. Referring to  FIGS. 1 through 3 , in step S 110 , a first program operation is performed and thereby threshold voltages of cell transistors increase. For example, the threshold voltages of cell transistors (e.g., all cell transistors) selected as a program target may increase. The program control circuit PC can control voltages applied to the memory cell array  110  so that threshold voltages of cell transistors increase. 
     In step S 120 , a second program operation is performed and thereby threshold voltages of cell transistors having threshold voltages higher than a verify voltage VFYu may decrease. For example, among cell transistors on which the first program operation is performed, cell transistors having threshold voltages higher than the verify voltage VFYu may be programmed such that their threshold voltages decrease through the second program operation. The verify voltage VFYu may be an upper limit of a target threshold voltage range of cell transistors. The program control circuit PC can control voltages applied to the memory cell array  111  so that threshold voltages of cell transistors having threshold voltages higher than the verify voltage VFYu decrease. 
       FIG. 4  illustrates changes of threshold voltages of cell transistors in the operating method of  FIG. 3 , according to an exemplary embodiment of the inventive concept. In  FIG. 4 , a horizontal axis indicates threshold voltages of cell transistors and a vertical axis indicates the number of cell transistors. In other words,  FIG. 4  shows a threshold voltage distribution of the cell transistors. 
     Referring to  FIGS. 1 through 4 , an initial threshold voltage distribution of the cell transistors may be indicated by a first line L 1 . 
     If the first program operation of the step S 110  is performed, threshold voltages of the cell transistors increase. For example, a threshold voltage distribution of the cell transistors may change from the first line L 1  to a second line L 2  through the first program operation. 
     If the second program operation of the step S 120  is performed, threshold voltages of cell transistors higher than the verify voltage VFYu decrease. For example, the threshold voltages of cell transistors higher than the verify voltage VFYu may become lower than the verify voltage VFYu. In other words, a threshold voltage distribution of the cell transistors may change from the second line L 2  to a third line L 3  through the second program operation. 
     As described above, if the first and second program operations are performed, a threshold voltage distribution of the cell transistors is reduced and threshold voltages of the cell transistors are limited to a level lower than the verify voltage VFYu. For example, a width of threshold voltage distribution identified by L 3  is less than that of L 2 . Since threshold voltages of the cell transistors are controlled within the target range, reliability of the nonvolatile memory  110  including cell transistors is increased. 
       FIG. 5  is a flowchart illustrating a first program operation, according to an exemplary embodiment of the inventive concept. Referring to  FIGS. 1, 2 and 5 , in step S 210 , a low voltage is supplied to channels of cell transistors. For example, a ground voltage or a low voltage having a level similar to the ground voltage may be supplied to channels of cell transistors selected as a program target. 
     In step S 220 , a high voltage is supplied to control gates of the cell transistors. For example, a high voltage having a level that can cause Fowler-Nordheim (F-N) tunneling may be supplied to control gates of the cell transistors selected as a program target. 
     Due to a voltage difference between the low voltage supplied to the channels of the cell transistors and the high voltage supplied to the control gate of the cell transistors, F-N tunneling occurs in the cell transistors. Thus, electrons are trapped in the cell transistors and threshold voltages of the cell transistors may increase. 
     In the first program operation, cell transistors may be programmed by a word line unit. For example, in the first program operation, threshold voltages of memory cells that belong to physical pages connected to the same word line may increase. 
       FIG. 6  is a table illustrating voltages supplied to a memory block BLKa in the first program operation, according to an exemplary embodiment of the inventive concept. An example of voltages when memory cells MC are selected as a program target is illustrated in  FIG. 6 . 
     Referring to  FIGS. 2 and 6 , first bit line voltages VBL 1  are applied to the bit lines BL 1  and BL 2 . The first bit line voltages VBL 1  may be a ground voltage or low voltages having a level similar to the ground voltage. 
     First string select line voltages VSSL 1  are applied to the string select lines SSL 1   a , SSL 1   b , SSL 2   a  and SSL 2   b . The first string select line voltages VSSL 1  may be a voltage that turns on the string select transistors SST 1   a , SST 1   b , SST 2   a  and SST 2   b . SST 1   a  and SST 1   b  correspond to the string select transistors connected to cell string CS 11  and SST 2   a  and SST 2   b  correspond to the string select transistors connected to cell string CS 12 . The first string select line voltages VSSL 1  may be a power supply voltage or high voltages having a level similar to or higher than the power supply voltage. 
     First pass voltages VPASS 1  are applied to unselected word lines. The first pass voltages VPASS 1  may be voltages that turn on memory cells connected to the unselected word lines. The first pass voltages VPASS 1  may be a power supply voltage or high voltages having a level similar to or higher than the power supply voltage. 
     A first program voltage VPGM 1  is applied to a selected word line. The first program voltage VPGM 1  may be a high voltage higher than the first pass voltages VPASS 1 . 
     First ground select line voltages VGSL 1  are applied to the ground select lines GSLa and GSLb. The first ground select line voltages VGSL 1  may be voltages that turn on the ground select transistors GSTa and GSTb. The first ground select line voltages VGSL 1  may be a power supply voltage or high voltages having a level similar to or higher than the power supply voltage. 
     A first common source line voltage VCSL 1  is applied to the common source line CSL. The first common source line voltage VCSL 1  may be a ground voltage or a low voltage having a level similar to the ground voltage. 
     In this case, the memory cells MC 3  connected to the third word line WL 3  are selected as a program target of the first program operation. Since the first pass voltages VPASS 1  are applied to the first word line WL 1 , the second word line WL 2  and the fourth through sixth word lines WL 4 ˜WL 6 , the first memory cells MC 1 , the second memory cells MC 2  and the fourth through sixth memory cells MC 4 ˜MC 6  are turned on. Since the first string select line voltages VSSL 1  are applied to the string select lines SSL 1   a , SSL 1   b , SSL 2   a  and SSL 2   b , the string select transistors SST 1   a , SST 1   b , SST 2   a  and SST 2   b  are turned on. Since the first ground select line voltages VGSL 1  are applied to the ground select lines GSLa and GSLb, the ground select transistors GSTa and GSTb are turned on. Since the first program voltage VPGM 1  is applied to the third word line WL 3 , the third memory cells MC 3  are turned on. 
     Since the first bit line voltages VBL 1  are provided to the bit lines BL 1  and BL 2 , low voltages are supplied to drains of the third memory cells MC 3  through the string select transistors SST 1   a , SST 1   b , SST 2   a  and SST 2   b  and the fourth through sixth memory cells MC 4 ˜MC 6 . In addition, the first common source line voltage VCSL 1  supplied to the common source line CSL is supplied to sources of the third memory cells MC 3  through the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2 . 
     As described with reference to  FIG. 5 , low voltages are supplied to channels of the third memory cell MC 3  selected as a target of the first program operation and a high voltage is supplied to control gates of the third cell MC 3 . Thus, threshold voltages of the third memory cell MC 3  rise. 
       FIG. 7  is a table illustrating voltages supplied to a memory block BLKa in the first program operation, according to an exemplary embodiment of the inventive concept. An example of voltages of when the ground select transistors GSTa are selected as a program target is illustrated in  FIG. 7 . 
     Referring to  FIGS. 2 and 7 , second bit line voltages VBL 2  are applied to the bit lines BL 1  and BL 2 . The second bit line voltages VBL 2  may be a ground voltage or low voltages having a level similar to the ground voltage. 
     Second string select line voltages VSSL 2  are supplied to the string select lines SSL 1   a , SSL 1   b , SSL 2   a  and SST 2   b . The second string select line voltages VSSL 2  may be voltages that turn on the string select transistors SST 1   a , SST 1   b , SST 2   a  and SST 2   b . The second string select line voltages VSSL 2  may be a power supply voltage or high voltages having a level similar to or high than the power supply voltage. 
     Second pass voltages VPASS 2  are applied to the word lines WL 1 ˜WL 6 . The second pass voltages VPASS 2  may be voltages that turn on memory cells connected to the word lines WL 1 ˜WL 6 . The second pass voltages VPASS 2  may be a power supply voltage or high voltages having a level similar to or high than the power supply voltage. 
     A second ground select line voltage VGSL 2  is applied to an unselected ground select line. The second ground select line voltage VGSL 2  may be a voltage that turns on the ground select transistors GST. The second ground select line voltage VGSL 2  may be a power supply voltage or a high voltage having a level similar to or high than the power supply voltage. 
     A second program voltage VPGM 2  is applied to a selected ground select line. The second program voltage VPGM 2  may be a high voltage higher than the second pass voltages VPASS 2 . 
     A second common line voltage VCSL 2  is applied to the common source line CSL. The second common line voltage VCSL 2  may be a ground voltage or a low voltage having a level similar to the ground voltage. 
     In this case, the ground select transistors GSTa connected to the ground select line GSLa are selected as a program target of the first program operation. Since the second pass voltages VPASS 2  are applied to the first through sixth word lines WL 1 ˜WL 6 , the first through sixth memory cells MC 1 ˜MC 6  are turned on. Since the second ground select line voltage VGSL 2  is applied to the ground select line GSLb, the ground select transistors GSTb are turned on. Since the second program voltage VPGM 2  is applied to the ground select line GSLa, the ground select transistors GSTa are turned on. 
     Since, the second bit line voltages VBL 2  are provided to bit lines BL 1  and BL 2 , low voltages are supplied to drains of the ground select transistors GSTb through the string select transistors SST 1   a , SST 1   b , SST 2   a  and SST 2   b  and the first through sixth memory cells MC 1 ˜MC 6 . In addition, the second common source line voltage VCSL 2  supplied to the common source line CSL is supplied directly to sources of the ground select transistors GSTa. 
     As described with reference to  FIG. 5 , low voltages are supplied to channels of the ground select transistors GSTa selected as a target of the first program operation and a high voltage is supplied to control gates of the ground select transistors GSTa. Thus, F-N tunneling occurs in the ground select transistors GSTa and threshold voltages of the ground select transistors GSTa rise. 
     The ground select transistors GSTb are programmed in a similar manner. For example, low voltages supplied to the bit lines BL 1  and BL 2  are transmitted to drains of the ground select transistors GSTb through cell transistors of a drain side of the ground select transistors GSTb, in other words, the string select transistors SST 1   a , SST 1   b , SST 2   a  and SST 2   b  and the memory cells MC 1 ˜MC 6 . Low voltages supplied to the common source line CSL are supplied to sources of the ground select transistors GSTb through cell transistors of a source side of the ground select transistor GSTb, in other words, the ground select transistors GSTa. If a high voltage is supplied to control gates of the ground select transistors GSTb, threshold voltages of the ground select transistors GSTb rise. 
       FIG. 8  is a flowchart illustrating a second program operation, according to an exemplary embodiment of the inventive concept. Referring to  FIGS. 1 through 3 and 8 , in step S 310 , a verify operation is performed using a verify voltage VFYu. For example, a verify operation may be performed on cell transistors on which a first program operation is performed. The verify operation may be performed by a physical page unit on the cell transistors on which the first program operation is performed. If the verify operation is performed, among the cell transistors on which the first program operation is performed, first cell transistors having threshold voltages lower than the verify voltage VFYu and second cell transistors having threshold voltages higher than the verify voltage VFYu may be distinguished from each other. 
     In step S 320 , it is determined whether the verify operation has passed. For example, in the case that the second cell transistors having threshold voltages higher than the verify voltage VFYu do not exist or the number of the second cell transistors is less than a predetermined value, the verify operation may be determined to have passed. 
     If the verify operation passes, the second program operation may be finished. If the verify operation does not pass, step S 330  is performed. 
     In the step S 330 , a program of the first cell transistors having threshold voltages lower than the verify voltage VFYu is inhibited. In step S 340 , a program of the second transistors having threshold voltages higher than the verify voltage VFYu is allowed. For example, a program may be inhibited or allowed by differently controlling voltages supplied to the first transistors and voltages supplied to the second transistors. After that, in step S 350 , a negative voltage is supplied to control gates of the first and second cell transistors. 
     The steps S 310  and S 320  may form a verify step. The steps S 330  through S 350  may form a program step. The verify step and the program step may be repeatedly performed until a result of the verify operation of the step S 310  is determined to have passed. In other words, the verify step and the program step may be repeatedly performed until threshold voltages of the cell transistors are equal to or lower than the verify voltage VFYu. 
     While the verify step and the program step are repeatedly performed, levels of voltages being applied to the cell strings CS 11 , CS 12 , CS 21  and CS 22  of the memory block BLKa may be changed. 
       FIG. 9  is a table illustrating voltages supplied to a memory block in the second program operation, according to an exemplary embodiment of the inventive concept. An example of when a second program is performed on the memory cells MC is illustrated in  FIG. 9 . 
     Referring to  FIGS. 2 and 9 , a third bit line voltage VBL 3  is applied to a selected bit line. The third bit line voltage VBL 3  may be a power supply voltage or a high voltage having a level similar to or higher than the power supply voltage. A fourth bit line voltage VBL 4  is applied to an unselected bit line. The fourth bit line voltage VBL 4  may be a ground voltage or a low voltage having a level similar to the ground voltage. 
     Third string select line voltages VSSL 3  are applied to selected string select lines. The third string select line voltages VSSL 3  may be voltages that turn on string select transistors. The third string select line voltages VSSL 3  may be a power supply voltage or high voltages having a level similar to or higher than the power supply voltage. The third string select line voltages VSSL 3  may have substantially the same levels as the third bit line voltage VBL 3 . Fourth string select line voltages VSSL 4  are applied to an unselected string select line. The fourth string select line voltages VSSL 4  may be a power supply voltage or high voltages higher than the third string select line voltages VSSL 3 . The fourth string select line voltages VSSL 4  may be high voltages. These high voltages may prevent boosting. 
     A third program voltage VPGM 3  is applied to a selected word line. The third program voltage VPGM 3  may be a negative voltage. 
     Third pass voltages VPASS 3  are applied to unselected word lines. The third pass voltages VPASS 3  may be voltages that turn on memory cells. The third pass voltages VPASS 3  may be a power supply voltage or high voltages higher than the third string select line voltages VSSL 3 . 
     Third ground select line voltages VGSL 3  are applied to the ground select lines GSLa and GSLb. The third ground select line voltages VGSL 3  may be voltages that turn on the ground select transistors GSTa and GSTb. The third ground select line voltages VGSL 3  may be a power supply voltage or high voltages having a level similar to or higher than the power supply voltage. 
     A third common source line voltage VCSL 3  is applied to the common source line CSL. The third common source line voltage VCSL 3  may be a ground voltage or a low voltage having a level similar to the ground voltage. 
     As described with reference to  FIG. 6 , the first program operation is performed on the memory cells MC 3  connected to the third word line WL 3 . In addition, among the third memory cells MC 3 , a threshold voltage of the third memory cell MC 3  that belongs to the cell string CS 11  is higher than the verify voltage VFYu and threshold voltages of the third memory cells MC 3  that belong to the remaining cell strings CS 12 , CS 21  and CS 22  are lower than the verify voltage VFYu. In other words, the string select lines SSL 1   a  and SSL 1   b  and the bit line BL 1  that correspond to the cell string CS 11  are selected and the string select lines SSL 2   a  and SSL 2   b  and the bit line BL 2  that do not correspond to the cell string CS 11  are unselected. 
       FIG. 10  illustrates voltages applied to a cell string CS 11  selected in the second program operation, according to an exemplary embodiment of the inventive concept. In  FIG. 10 , the cell string CS 11  is illustrated in a right side and a voltage (or potential) graph of channels of cell transistors of the cell string CS 11  is illustrated in a left side. In the voltage (or potential) graph, a horizontal axis indicates a channel voltage Vch and a vertical axis indicates a location (Position) of cell transistors. 
     Referring to  FIGS. 2, 9 and 10 , the third program voltage VPGM 3  which is a negative voltage is applied to the selected third word line WL 3 . Thus, the third memory cell MC 3  is turned off. For example, a channel of the third memory cell MC 3  has a first type (for example, p-type). Due to a coupling between a control gate and a channel of the third memory cell MC 3 , a voltage (or potential) of the channel of the third memory cell MC 3  may decrease. 
     The third string select line voltages VSSL 3  are applied to the selected string select lines SSL 1   a  and SSL 1   b . In an initial state when the third string select line voltages VSSL 3  are applied, the selected string select lines SSL 1   a  and SSL 1   b  may be turned on. 
     The third bit line voltage VBL 3  is supplied to the selected first bit line BL 1 . The third bit line voltage VBL 3  may be transmitted to a drain of the memory cells MC 6  through channels of the selected string select transistors SST 1   a  and SST 1   b  which are turned on. 
     If the third pass voltages VPASS 3  are applied to the fourth through sixth word lines WL 4 ˜WL 6 , the fourth through sixth memory cells MC 4 ˜MC 6  are turned on. For example, channels of the fourth through sixth memory cells MC 4 ˜MC 6  have a second type (for example, n-type). Since the third memory cell MC 3  is turned off, a voltage transmitted from the selected bit line BL 1  to a drain of the sixth memory cell MC 6  is transmitted to the channels of the fourth through sixth memory cells MC 4 ˜MC 6 . 
     After the fourth through sixth memory cells MC 4 ˜MC 6  are turned on, as voltages of control gates of the fourth through sixth memory cells MC 4 ˜MC 6  rise to target levels of the third pass voltages VPASS 3 , a coupling occurs between control gates and channels of the fourth through sixth memory cells MC 4 ˜MC 6 . Due to the coupling, voltages (or potentials) of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  may be higher than a voltage supplied from the selected first bit line BL 1  to a drain of the sixth memory cell MC 6 . At this time, the string select transistors SST 1   a  and SST 1   b  are turned off. In other words, channels of the fourth through sixth memory cells MC 4 ˜MC 6  are isolated from the first bit line BL 1  and floated between the third memory cell MC 3  which is turned off and the string select transistors SST 1   a  and SST 1   b  which are turned off. 
     For example, the third string select line voltages VSSL 3  and the third bit line voltage VBL 3  may have substantially the same level. At this time, a voltage being transmitted to a drain of the memory cell MC 6  may have a level obtained by subtracting threshold voltages of the string select transistors SST 1   a  and SST 1   b  from the third string select line voltages VSSL 3  or the third bit line voltage VBL 3 . In this case, if a drain voltage of the sixth memory cell MC 6  rises, a turn on condition of the string select transistors SST 1   a  and SST 1   b  is not satisfied and thereby the string select transistors SST 1   a  and SST 1   b  are turned off. 
     After the string select transistors SST 1   a  and SST 1   b  are turned off, voltages of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  further rise due to a coupling effect. In other words, channels of the fourth through sixth memory cells MC 4 ˜MC 6  are floated and voltages (or potentials) of the floated channels are boosted. For example, the voltages of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  may increase to a boost voltage VBOOST. In other words, the boost voltage VBOOST is supplied to a drain of the selected third memory cell MC 3 . 
     As the third pass voltages VPASS 3  are supplied to the first and second word lines WL 1  and WL 2  and the third ground select line voltages VGSL 3  are supplied to the ground select lines GSLa and GSLb, the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2  are turned on. Thus, the third common source line voltage VCSL 3  supplied to the common source line CSL is transmitted to a source of the selected third memory cell MC 3  through the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2 . 
     Due to a voltage difference between the boost voltage VBOOST supplied to the drain of the third memory cell MC 3  and the third common source line voltage VCSL 3  supplied to the source of the third memory cell MC 3 , a hot hole appears around/in the third memory cell MC 3 . Due to the third program voltage VPGM 3  which is a negative voltage being applied to the control gate of the third memory cell MC 3 , a hot hole is injected into the third memory cell MC 3 . In other words, a threshold voltage of the third memory cell MC 3  is reduced. 
     While the verify step and the program step of  FIG. 8  are repeatedly performed, a level of the third program voltage VPGM 3  may gradually increase or decrease. While the verify step and the program step of  FIG. 8  are repeatedly performed, levels of the third pass voltages VPASS are gradually increased or decreased and thereby a level of the boost voltage VBOOST may gradually increase or decrease. 
       FIGS. 11 through 13  illustrate voltages applied to cell strings CS 12 , CS 21  and CS 22  unselected in the second program operation, according to exemplary embodiments of the inventive concept. In  FIGS. 11 through 13 , the cell strings CS 12 , CS 21  and CS 22  are illustrated in a right side and voltage (or potential) graphs of channels of cell transistors of the cell strings CS 12 , CS 21  and CS 22  are illustrated in a left side. In each voltage (or potential) graph, a horizontal axis indicates a voltage of the channels Vch and a vertical axis indicates a location (Position) of the cell transistors. 
     Referring to  FIGS. 2, 9 and 11 , in the unselected cell string CS 12 , the third program voltage VPGM 3  which is a negative voltage is applied to the selected third word line WL 3 . Thus, the third memory cell MC 3  is turned off. 
     The third string select line voltages VSSL 3  are applied to the selected string select lines SSL 1   a  and SSL 1   b . Thus, the string select transistors SST 1   a  and SST 1   b  are turned on. The third pass voltages VPASS 3  are supplied to the fourth through sixth word lines WL 4 ˜WL 6 . Thus, the fourth through sixth memory cells MC 4 ˜MC 6  are turned on. 
     The fourth bit line voltage VBL 4  is supplied to the unselected second bit line BL 2 . The fourth bit line voltage VBL 4  is supplied to channels of the fourth through sixth memory cells MC 4 ˜MC 6  through the string select transistors SSTa and SSTb. Since the fourth bit line voltage VBL 4  is a low voltage, if a coupling occurs in control gates of the fourth through sixth memory cells MC 4 ˜MC 6 , a voltage of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  does not increase to turn off the string select transistors SSTa and SSTb. Thus, the boosting described with reference to  FIG. 10  does not occur and the voltage of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  becomes the fourth bit line voltage VBL 4 . 
     As the third pass voltages VPASS 3  are supplied to the first and second word lines WL 1  and WL 2  and the third ground select line voltages VGSL 3  are applied to the ground select lines GSLa and GSLb, the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2  are turned on. Thus, the third common source line voltage VCSL 3  supplied to the common source line CSL is transmitted to a source of the selected third memory cell MC 3  through the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2 . 
     A voltage difference between the fourth bit line voltage VBL 4  supplied to a drain of the third memory cell MC 3  and the third common source line voltage VSL 3  supplied to a source of the third memory cell MC 3  does not cause a hot hole. In other words, in the unselected cell string CS 12 , a program of the third memory cell MC 3  is inhibited by preventing a boosting of a drain voltage of the third memory cell MC 3 . 
     Referring to  FIGS. 2, 9 and 12 , in the unselected cell string CS 21 , the third program voltage VPGM 3  which is a negative voltage is applied to the selected third word line WL 3 . Thus, the third memory cell MC 3  is turned off. 
     The fourth string select line voltages VSSL 4  are applied to the unselected string select lines SSL 2   a  and SSL 2   b . Thus, the string select transistors SSTa and SSTb are turned on. The third pass voltages VPASS 3  are supplied to the fourth through sixth word lines WL 4 ˜WL 6 . Thus, the fourth through sixth memory cells MC 4 ˜MC 6  are turned on. 
     The third bit line voltage VBL 3  is supplied to the selected first bit line BL 1 . The third bit line voltage VBL 3  is supplied to channels of the fourth through sixth memory cells MC 4 ˜MC 6  through the string select transistors SSTa and SSTb. The fourth string select line voltages VSSL 4  are high voltages higher than the third string select line voltage VSSL 3 . For example, the fourth string select line voltages VSSL 4  may be set to be high enough so that when voltages of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  increase due to a coupling from control gates, the string select transistors SSTa and SSTb are not turned off. Thus, the boosting described with reference to  FIG. 10  does not occur and the voltages of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  become the third bit line voltage VBL 3 . 
     As the third pass voltages VPASS 3  are supplied to the first and second word lines WL 1  and WL 2  and the third ground select line voltages VGSL 3  are applied to the ground select lines GSLa and GSLb, the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2  are turned on. Thus, the third common source line voltage VCSL 3  supplied to the common source line CSL is transmitted to a source of the selected third memory cell MC 3  through the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2 . 
     A voltage difference between the third bit line voltage VBL 3  supplied to a drain of the third memory cell MC 3  and the third common source line voltage VCSL 3  supplied to a source of the third memory cell MC 3  is not enough to cause a hot hole. In other words, in the unselected cell string CS 21 , a program of the third memory cell MC 3  is inhibited by preventing a boosting of a drain voltage of the third memory cell MC 3 . 
     Referring to  FIGS. 2, 9 and 13 , in the unselected cell string CS 22 , the third program voltage VPGM 3  which is a negative voltage is applied to the selected third word line WL 3 . Thus, the third memory cell MC 3  is turned off. 
     The fourth string select line voltages VSSL 4  are applied to the unselected string select lines SSL 2   a  and SSL 2   b . Thus, the string select transistors SSTa and SSTb are turned on. The third pass voltages VPASS 3  are supplied to the fourth through sixth word lines WL 4 ˜WL 6 . Thus, the fourth through sixth memory cells MC 4 ˜MC 6  are turned on. 
     The fourth bit line voltage VBL 4  is supplied to the unselected second bit line BL 2 . The fourth bit line voltage VBL 4  is supplied to channels of the fourth through sixth memory cells MC 4 ˜MC 6  through the string select transistors SSTa and SSTb. The fourth string select line voltages VSSL 4  are high voltages higher than the third string select line voltage VSSL 3  and the fourth bit line voltage VBL 4  is a low voltage lower than the third bit line voltage VBL 3 . Thus, when voltages of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  increase due to a coupling from their control gates, the string select transistors SSTa and SSTb are not turned off. Thus, the boosting described with reference to  FIG. 10  does not occur and the voltages of the channels of the fourth through sixth memory cells MC 4 ˜MC 6  become the fourth bit line voltage VBL 4 . 
     As the third pass voltages VPASS 3  are supplied to the first and second word lines WL 1  and WL 2  and the third ground select line voltages VGSL 3  are applied to the ground select lines GSLa and GSLb, the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2  are turned on. Thus, the third common source line voltage VCSL 3  supplied to the common source line CSL is transmitted to a source of the selected third memory cell MC 3  through the ground select transistors GSTa and GSTb and the first and second memory cells MC 1  and MC 2 . 
     A voltage difference between the fourth bit line voltage VBL 4  supplied to a drain of the third memory cell MC 3  and the third common source line voltage VCSL 3  supplied to a source of the third memory cell MC 3  does not cause a hot hole. In other words, in the unselected cell string CS 22 , a program of the third memory cell MC 3  is inhibited by preventing a boosting of a drain voltage of the third memory cell MC 3 . 
       FIG. 14  is a table illustrating voltages supplied to a memory block in the second program operation, according to an exemplary embodiment of the inventive concept. An example of voltages when the second program is performed in the ground select transistors GSTa and GSTb is illustrated in  FIG. 14 . 
     Referring to  FIGS. 2 and 14 , a fifth bit line voltage VBL 5  is applied to a selected bit line. The fifth bit line voltage VBL 5  may be a power supply voltage or a high voltage having a level similar to or higher than the power supply voltage. A sixth bit line voltage VBL 6  is applied to an unselected bit line. The sixth bit line voltage VBL 6  may be a ground voltage or a low voltage having a level similar to the ground voltage. 
     Fifth string select line voltages VSSL 5  are applied to selected string select lines. The fifth string select line voltages VSSL 5  may be voltages that turn on the string select transistors. The fifth string select line voltages VSSL 5  may be a power supply voltage or high voltages having a level similar to or higher than the power supply voltage. The fifth string select line voltages VSSL 5  may have substantially the same level as the fifth bit line voltage VBL 5 . Sixth string select line voltages VSSL 6  are applied to an unselected string select line. The sixth string select line voltages VSSL 6  may be voltages that turn on the string select transistors. The sixth string select line voltages VSSL 6  may be a power supply voltage or high voltages having a level higher than the fifth string select line voltages VSSL 5 . The sixth string select line voltages VSSL 6  may be high voltages that prevent boosting. 
     Fourth pass voltages VPASS 4  are applied to the word lines WL 1 ˜WL 6 . The fourth pass voltages VPASS 4  may be voltages that turn on the first through sixth memory cells MC 1 ˜MC 6 . The fourth pass voltages VPASS 4  may be a power supply voltage or high voltages higher than the fifth string select line voltages VSSL 5 . 
     The fourth program voltage VPGM 4  is applied to the selected ground select line. The fourth program voltage VPGM 4  may be a negative voltage. 
     The fourth ground select line voltage VGSL 4  is applied to the unselected ground select line. The fourth ground select line voltage VGSL 4  may be a voltage that turns on the ground select transistors. The fourth ground select line voltage VGSL 4  may be a power supply voltage or a high voltage having a level similar to or higher than the power supply voltage. 
     The common source line voltage VCSL 4  is applied to the common source line CSL. The common source line voltage VCSL 4  may be a ground voltage or a low voltage having a level similar to the ground voltage. 
     As described with reference to  FIG. 7 , the first program operation is performed in the ground select transistor GSTa connected to the ground select line GSLa. In addition, among the ground select transistors GSTa, threshold voltages of the ground select transistors GSTa that belong to the cell string CS 11  are higher than the verify voltage VFYu and threshold voltages of the ground select transistors GSTa that belong to the remaining cell strings CS 12 , CS 21  and CS 22  are lower than the verify voltage VFYu. In other words, the string select lines SSL 1   a  and SSL 1   b  and the bit line BL 1  that correspond to the cell string CS 11  are selected and the string select lines SSL 2   a  and SSL 2   b  and the bit line BL 2  that do not correspond to the cell string CS 11  are unselected. 
       FIG. 15  illustrates voltages applied to a cell string selected in the second program operation, according to an exemplary embodiment of the inventive concept. In  FIG. 15 , the cell string CS 11  is illustrated in a right side and a voltage (or potential) graph of channels of the cell transistors of the cell string CS 11  is illustrated in a left side. In the voltage (or potential) graph, a horizontal axis indicates voltages of the channels Vch and a vertical axis indicates a location (Position) of the cell transistors. 
     Referring to  FIGS. 2, 14 and 15 , the fourth program voltage VPGM 4  which is a negative voltage is applied to the selected ground select line GSLa. Thus, the ground select transistor GSTa is turned off. For example, a channel of the ground select transistor GSTa has a first type (for example, a p-type). Due to a coupling between a control gate and the channel of the ground select transistor GSTa, a voltage of the channel of the ground select transistor GSTa may decrease. 
     The fifth string select line voltages VSSL 5  are applied to the selected string select lines SSL 1   a  and SSL 1   b . In an initial state when the fifth string select line voltages VSSL 5  are applied, the string select transistors SST 1   a  and SST 1   b  may be turned on. 
     The fifth bit line voltage VBL 5  is supplied to the selected first bit line BL 1 . The fifth bit line voltage VBL 5  may be transmitted to the memory cell MC 6  through channels of the string select transistors SST 1   a  and SST 1   b  that are turned on. 
     If the fourth pass voltages VPASS 4  are applied to the first through sixth word lines WL 1 ˜WL 6 , the first through sixth memory cells MC 1 ˜MC 6  are turned on. For example, channels of the first through sixth memory cells MC 1 ˜MC 6  have a second type (for example, an n-type). If the fourth ground select line voltage VGSL 4  is applied to the ground select line GSLb, the ground select transistor GSTb is turned on. For example, a channel of the ground select transistor GSTb has the second type. Since the ground select transistor GSTa is turned off, a voltage transmitted from the selected bit line BL 1  to a drain of the sixth memory cell MC 6  is transmitted to the first through sixth memory cells MC 1 ˜MC 6  and a channel of the ground select transistor GSTb. 
     After the first through sixth memory cells MC 1 ˜MC 6  and the ground select transistor GSTb are turned on, as voltages of control gates of the first through sixth memory cells MC 1 ˜MC 6  rise to target levels of the fourth pass voltages VPASS 4  and a voltage of a control gate of the ground select line GSLb rises to a target level of the fourth ground select line voltage VGSL 4 , a coupling occurs between control gates and channels of the first through sixth memory cells MC 1 ˜MC 6  and the ground select transistor GSTb. Due to the coupling, voltages of the channels of the first through sixth memory cells MC 1 ˜MC 6  and the ground select transistor GSTb may be higher than a voltage supplied from the first bit line VBL 1  to a drain of the sixth memory cell MC 6 . At this time, the string select transistors SST 1   a  and SST 1   b  are turned off. In other words, channels of the first through sixth memory cells MC 1 ˜MC 6  and the ground select transistor GSTb are isolated from the first bit line BL 1  and floated between the ground select transistor GSTa and the string select transistors SST 1   a  and SST 1   b  that are turned off. 
     The fifth string select line voltages VSSL 5  and the fifth bit line voltage VBL 5  may have substantially the same levels. A voltage transmitted to a drain of the memory cell MC 6  may have a level obtained by subtracting threshold voltages of the string select transistors SST 1   a  and SST 1   b  from the fifth string select line voltages VSSL 5  or the fifth bit line voltage VBL 5 . In this case, if a drain voltage of the memory cell MC 6  increases due to a coupling, a turn-on condition of the string select transistors SST 1   a  and SST 1   b  is not satisfied and thereby the string select transistors SST 1   a  and SST 1   b  are turned off. 
     After the string select transistors SST 1   a  and SST 1   b  are turned off, voltages of channels of the first through sixth memory cells MC 1 ˜MC 6  and the ground select transistor GSTb further increase due to the coupling effect. In other words, the channels of the first through sixth memory cells MC 1 ˜MC 6  and the ground select transistor GSTb are floated and voltages of the floated channels are boosted. For example, the voltages of channels of the first through sixth memory cells MC 1 ˜MC 6  and the ground select transistor GSTb may rise to a boost voltage VBOOST. In other words, the boost voltage VBOOST is supplied to a drain of the selected ground select transistor GSTa. 
     The fourth common source line voltage VCSL 4  supplied to the common source line CSL is transmitted to a source of the selected ground select transistor GSTa. 
     Due to a voltage difference between the boost voltage VBOOST supplied to the drain of the ground select transistor GSTa and the fourth common source line voltage VCSL 4  supplied to the source of the ground select transistor GSTa, a hot hole appears around/in the ground select transistor GSTa. Due to the fourth program voltage VPGM 4  which is a negative voltage applied to a control gate of the ground select transistor GSTa, a hot hole is injected into the ground select transistor GSTa. In other words, a threshold voltage of the ground select transistor GSTa is reduced. 
     In the unselected cell strings CS 12 , CS 21  and CS 22 , as described with reference to  FIGS. 11 through 13 , a program of the ground select transistor GSTa may be inhibited by preventing voltages of drains of the ground select transistor GSTa from being boosted. 
     The ground select transistor GSTb is programmed in a similar manner. For example, in a selected cell string, a drain voltage of the ground select transistor GSTb is boosted. A low voltage supplied to the common source line CSL is transmitted to a source of the ground select transistor GSTb. If a negative voltage is supplied to the ground select transistor GSTb, a threshold voltage of the ground select transistor GSTb of the selected cell string is reduced. 
     In unselected cell strings, voltages of drains of the ground select transistor GSTb are prevented from being boosted. A low voltage supplied to the common source line CSL is transmitted to sources of the ground select transistor GSTb. When a negative voltage is supplied to the ground select line GSLb, threshold voltages of the ground select transistor GSTb of the unselected cell strings are not reduced. 
     While the verify step and the program step of  FIG. 8  are repeatedly performed, a level of the fourth program voltage VPGM 4  may gradually increase or decrease. While the verify step and the program step of  FIG. 8  are repeatedly performed, levels of the fourth pass voltages VPASS 4  are gradually increased or decreased and thereby a level of the boost voltage VBOOST may gradually increase or decrease. 
       FIG. 16  is a flowchart illustrating a second program operation, according to an exemplary embodiment of the inventive concept. Referring to  FIGS. 1 through 3 and 16 , in step S 410 , a verify operation is performed using the verify voltage VFYu. If the verify operation is performed, among cell transistors on which the first program operation is performed, first cell transistors having threshold voltages lower than the verify voltage VFYu and second cell transistors having threshold voltages higher than the verify voltage VFYu are distinguished from each other. 
     In step S 420 , it is determined whether the verify operation has passed or not. If the verify operation is determined to have passed, the second program operation may be finished. If the result of the verify operation is not determined to have passed, step S 430  is performed. The steps S 410  and S 420  may be a verification step. 
     In the step S 430 , a program of the first cell transistors having threshold voltages lower than the verify voltage VFYu is inhibited. In step S 440 , a program of the second transistors having threshold voltages higher than the verify voltage VFYu is allowed. After that, in step S 450 , a negative voltage is supplied to control gates of the first and second cell transistors. 
     In step S 460 , it is determined whether a max program step is performed. For example, it may be determined whether a program step including the steps S 430  through S 450  is performed as many as a predetermined number of times. 
     As described with reference to  FIGS. 10 through 15 , in the second program operation, a threshold voltage of a selected cell transistor of a selected cell string is reduced by boosting a drain voltage of the selected cell transistor of the selected cell string. The boosted voltage may be gradually reduced due to a peripheral effect such as a leakage. If the boosted voltage is gradually reduced, a program efficiency of the selected cell transistor may be degraded. To prevent program efficiency from being degraded due to reduction of the boosted voltage, the program step including the steps S 430  through S 450  may be performed several times. 
     For example, after a kth program step is performed, a selected cell string may be restored. For example, channel voltages of cell transistors of the cell strings of the memory block BLKa may be discharged. Then, after a verification step, the voltages described with reference to  FIG. 9 or 14  are applied again and thereby a k+1th program step may be performed. 
     While a program step is repeatedly performed, voltage conditions may be controlled. For example, a level of a negative voltage applied to a control gate of the selected cell transistor may increase or decrease. Levels of the pass voltages VPASS applied to unselected word lines increase or decrease and thereby a level of the boost voltage VBOOST may increase or decrease. A level of a low voltage applied to the common source line CSL may increase or decrease. 
       FIG. 17  is a timing diagram illustrating control of a level of a pass voltage in a second program operation, according to an exemplary embodiment of the inventive concept. In  FIG. 17 , a horizontal axis indicates time T and a vertical axis indicates a level of a pass voltage VPASS. An example of controlling a level of the pass voltage VPASS in the program step of  FIG. 16  is illustrated in  FIG. 17 . 
     Referring to  FIG. 17 , the pass voltage VPASS is applied to word lines WL at a first time T 1 . After that, a level of the pass voltage VPASS increases at a second time T 2 , a third time T 3 , a fourth time T 4  and a fifth time T 5 . After that, at a sixth time T 6 , the pass voltage VPASS is discharged. 
     As described with reference to  FIG. 16 , a level of the boosted voltage VBOOST may be gradually reduced as time goes by. As illustrated in  FIG. 17 , if a level of the pass voltage VPASS gradually increases, due to a coupling, a level of the boosted voltage VBOOST gradually rises. In other words, a reduction and a rise of the boosted voltage VBOOST cancel each other and thereby a level of the boosted voltage VBOOST is maintained while the program step of the second program operation is performed. 
     As described with reference to  FIG. 16 , the program step of the second program operation is repeatedly performed but a level of the pass voltage VPASS in each program step may be controlled as described with reference to  FIG. 17 . 
       FIG. 18  is a flowchart illustrating an operating method of a nonvolatile memory in accordance with an exemplary embodiment of the inventive concept. Referring to  FIGS. 1, 2 and 18 , in step S 510 , the first program operation is performed to increase threshold voltages of the cell transistors. For example, threshold voltages of the cell transistors selected as a program target may increase. 
     In step S 520 , the second program operation is performed to decrease threshold voltages of the cell transistors having a threshold voltage higher than the verify voltage VFYu among the cell transistors. For example, among the cell transistors on which the first program operation is performed, threshold voltages of the cell transistors having a threshold voltage higher than the verify voltage VFYu may be reduced through the second program operation. For example, the verify voltage VFYu may be an upper limit of a target threshold voltage range of the cell transistors. 
     In step S 530 , it is determined a maximum number of iterations has been reached. For example, it is determined whether the first and second program operations have been performed a predetermined number of times. If the first and second program operations have not been performed the predetermined number of times, the steps S 510  and S 520  are repeated, and thus, the first program operation and the second program operation are performed again. If the first and second program operations have been performed the predetermined number of times, a program of the cell transistors is finished. 
     If an operation of increasing threshold voltages of the cell transistors through the first program operation and an operation of decreasing threshold voltages of the cell transistors having a threshold voltage higher than the verify voltage VFYu through the second program operation are repeatedly performed, a threshold voltage distribution of the cell transistors may be reduced. 
     While the first program operation is repeatedly performed, voltages applied to the cell strings CS 11 , CS 12 , CS 21  and CS 22  may be changed. For example, a level of the program voltage VPGM may gradually increase. 
     When the second program operation begins, voltages applied to the cell strings CS 11 , CS 12 , CS 21  and CS 22  may be initialized as initial values. 
       FIG. 19  is a flowchart illustrating an operating method of the nonvolatile memory  110  in accordance with an exemplary embodiment of the inventive concept. Referring to  FIGS. 1, 2 and 19 , in step S 610 , the first program operation is performed to increase threshold voltages of the cell transistors. For example, all of the threshold voltages of cell transistors selected as a program target may increase. 
     In step S 620 , the second program operation is performed to decrease threshold voltages of the cell transistors having a threshold voltage higher than the verify voltage VFYu among the cell transistors. For example, among the cell transistors on which the first program operation is performed, threshold voltages of the cell transistors having a threshold voltage higher than the verify voltage VFYu may be reduced through the second program operation. For example, the verify voltage VFYu may be an upper limit of a target threshold voltage range of the cell transistors. 
     In step S 630 , a verify operation is performed on the cell transistors using the verify voltage VFY 1 . For example, if among the cell transistors, a cell transistor having threshold voltages lower than the verify voltage VFY 1  exists, or the number of cell transistors having threshold voltages lower than the verify voltage VFY 1  is greater than a predetermined value, the verify operation may be determined to have failed. If among the cell transistors, a cell transistor having threshold voltages lower than the verify voltage VFY 1  does not exist, or the number of cell transistors having threshold voltages lower than the verify voltage VFY 1  is not greater than the predetermined value, a result of the verify operation may be determined to have passed. 
     In step S 640 , if the verify operation is determined to have passed, a program of the cell transistors is finished. If the verify operation is determined to have failed, the steps S 610  through S 630  are performed again. 
     If the number of times the steps S 610  through S 630  are repeatedly performed reaches a predetermined threshold, it may be determined that a program of the cell transistors is finished and an error occurs. 
     While the first program operation is repeatedly performed, voltages applied to the cell strings CS 11 , CS 12 , CS 21  and CS 22  may be changed. For example, a level of the program voltage VPGM may gradually increase. 
     When the second program operation begins, voltages applied to the cell strings CS 11 , CS 12 , CS 21  and CS 22  may be initialized as initial values. 
       FIG. 20  illustrates changes of threshold voltages of cell transistors in the operating method of  FIG. 19 , according to an exemplary embodiment of the inventive concept. In  FIG. 20 , a horizontal axis indicates threshold voltages Vth of the cell transistors and a vertical axis indicates the number of cell transistors. In other words,  FIG. 20  shows a threshold voltage distribution of the cell transistors. 
     Referring to  FIGS. 1, 2, 19 and 20 , an initial threshold voltage distribution of the cell transistors may be indicated by a first line L 1 . 
     If the first program operation of the step S 610  is performed, threshold voltages of the cell transistors increase. For example, a threshold voltage distribution of the cell transistors may be changed from the first line L 1  to a second line L 2 . 
     If the second program operation of the step S 620  is performed, threshold voltages of cell transistors having threshold voltages higher than the verify voltage VFYu are reduced. For example, the threshold voltages higher than the verify voltage VFYu may become lower than the verify voltage VFYu. The first and second program operations are performed until threshold voltages of the cell transistors are equal to or higher than the verify voltage VFY 1 . In other words, a threshold voltage distribution of the cell transistors may be changed from the second line L 2  to a third line L 3 . 
     As described above, if the first and second program operations are performed, a threshold voltage distribution of the cell transistors is reduced and, in particular, threshold voltages of the cell transistors are limited to a range between the verify voltage VFYu and the verify voltage VFY 1 . Since the threshold voltages of the cell transistors are controlled within a target range, reliability of the nonvolatile memory  110  including the cell transistors is increased. 
       FIG. 21  is a block diagram illustrating a storage device in accordance with an exemplary embodiment of the inventive concept. Referring to  FIG. 21 , a storage device  100  includes a nonvolatile memory  110 , a memory controller  120  and a random access memory (RAM)  130 . 
     The nonvolatile memory  110  can perform write, read and erase operations under the control of the memory controller  120 . The nonvolatile memory  110  can exchange first data DATA 1  with the memory controller  120 . For example, the nonvolatile memory  110  can receive the first data DATA 1  from the memory controller  120  and write the first data DATA 1 . The nonvolatile memory  110  can perform a read operation and output the read first data DATA 1  to the memory controller  120 . 
     The nonvolatile memory  110  can receive a first command CMD 1  and a first address ADDR 1  from the memory controller  120 . The nonvolatile memory  110  can exchange a control signal CTRL with the memory controller  120 . For example, the nonvolatile memory  110  can receive at least one of a chip select signal /CE selecting at least one semiconductor chip among a plurality of semiconductor chips constituting the nonvolatile memory  110 , a command latch enable signal CLE indicating that a signal received from the memory controller  120  is the first command CMD 1 , an address latch enable signal ALE indicating that a signal received from the memory controller  120  is the first address ADDR 1 , a read enable signal /RE which is generated by the memory controller  120  in a read operation and periodically toggled to be used to adjust timing, a write enable signal /WE activated by the memory controller  120  when the first command CMD 1  or the first address ADDR 1  is transmitted, a write preventing signal /WP activated by the memory controller  120  to prevent an unwanted erase or an unwanted write when power supply is changed, and a data strobe signal DQS which is generated by the memory controller  120  in a write operation and is periodically toggled to be used to adjust an input sync of the first data DATA 1  from the memory controller  120 . For example, the nonvolatile memory  110  can output at least one of a ready &amp; busy signal R/nB indicating whether the nonvolatile memory  110  performs a program, erase or read operation, and a data strobe signal DQS which is generated from the read enable signal /RE by the nonvolatile memory  110  and is periodically toggled to be used to adjust an output sync of the first data DATA 1  to the memory controller  120 . 
     The first data DATA 1 , the first address ADDR 1  and the first command CMD 1  can be communicated with the memory controller  120  through a first channel CH 1 . The first channel CH 1  may be an input/output channel. The control signal CTRL can be communicated with the memory controller  120  through a second channel CH 2 . The second channel CH 2  may be a control channel. 
     The nonvolatile memory  110  has the structures described with reference to  FIGS. 1 through 20  and may operate according to the methods described with reference to  FIGS. 1 through 20 . For example, the nonvolatile memory  110  can perform the first program operation of increasing threshold voltages of the cell transistors and the second program operation of reducing threshold voltages of cell transistors having threshold voltages higher than the verify voltage among the programmed cell transistors. 
     The nonvolatile memory  110  may include a flash memory. However, the nonvolatile memory  110  is not limited to include a flash memory. The nonvolatile memory  110  may include at least one of various nonvolatile memories such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FeRAM), etc. 
     The memory controller  120  is configured to control the nonvolatile memory  110 . For example, the memory controller  120  can control the nonvolatile memory  110  to perform a write, read or erase operation. The memory controller  120  can exchange the first data DATA 1  and the control signal CTRL with the nonvolatile memory  110  and output the first command CMD 1  and the first address ADDR 1  to the nonvolatile memory  110 . 
     The memory controller  120  can control the nonvolatile memory  110  under the control of an external host device. The memory controller  120  can exchange second data DATA 2  with the external host device and receive a second command CMD 2  and a second address ADDR 2  from the external host device. 
     The memory controller  120  can exchange the first data DATA 1  with the nonvolatile memory  110  by a first unit (for example, a time unit or a data unit) and exchange the second data DATA 2  with the external host device by a second unit (for example, a time unit or a data unit) different from the first unit. 
     The memory controller  120  can exchange the first data DATA 1  with the nonvolatile memory  110  according to a first format and transmit the first command CMD 1  and the first address ADDR 1  to the nonvolatile memory  110 . The memory controller  120  can exchange the second data DATA 2  with the external host device according to a second format different from the first format and receive the second command CMD 2  and the second address ADDR 2  from the external host device. 
     The memory controller  120  can use the RAM  130  as a buffer memory, a cache memory or an operation memory. For example, the memory controller  120  can receive the second data DATA 2  from the external host device, store the received second data DATA 2  in the RAM  130  and write the second data DATA 2  stored in the RAM  130  in the nonvolatile memory  110  as the first data DATA 1 . The memory controller  120  can read the first data DATA 1  from the nonvolatile memory  110 , store the read first data DATA 1  in the RAM  130  and output the first data DATA 1  stored in the RAM  130  to the external host device as the second data DATA 2 . The memory controller  120  can store data read from the nonvolatile memory  110  in the RAM  130  and write data stored in the RAM  130  in the nonvolatile memory  110  again. 
     The memory controller  120  can store data or a code used to manage the nonvolatile memory  110  in the RAM  130 . For example, the memory controller  120  can read data or a code for managing the nonvolatile memory  110  from the nonvolatile memory  110  and load it into the RAM  130  to drive the nonvolatile memory  110 . 
     The memory controller  120  may include an error correction code (ECC) block  124 . The ECC block  124  can generate a parity based on the first data DATA 1  written in the nonvolatile memory  110 . The generated parity can be written in the nonvolatile memory  110  together with the first data DATA 1 . An operation of generating the parity may be an error correction encoding operation. The ECC block  124  can receive the first data DATA 1  and the parity from the nonvolatile memory  110 . The ECC block  124  can correct an error of the first data DATA 1  using the received parity. An operation of correcting an error may be an error correction decoding operation. 
     In an error correction decoding operation, the ECC block  124  can perform a simplified error correction or a complete error correction. The simplified error correction may be an error correction having a reduced error correction time. The complete error correction may be an error correction having more reliability. The ECC block  124  can increase an operation speed and reliability of the storage device  100  by selectively performing the simplified error correction or the complete error correction. 
     The RAM  130  may include at least one of various random access memories such as a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), a PRAM, an MRAM, an RRAM, an FeRAM, etc. 
     To reduce an overhead that an erase operation creates in the nonvolatile memory  110 , the storage device  100  may perform an address mapping. For example, when an overwrite operation is requested from the external host device, the storage device  100  may store the overwrite-requested data in memory cells of a free storage space instead of erasing memory cells storing existing data to store the overwrite-requested data in the erased memory cells. The memory controller  120  can drive a flash translation layer (FTL) mapping a logical address used in the external host device and a physical address used in the nonvolatile memory  110  according to the method described above. For example, the second address ADDR 2  may be a logical address and the first address ADDR 1  may be a physical address. 
     The storage device  100  can perform a write, read or erase operation of data according to a request of the external host device. The storage device  100  may include a solid state drive (SSD) or a hard disk drive (HDD). The storage device  100  may include memory cards such as a personal computer memory card international association (PCMCIA) card, a compact flash (CF) card, a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, reduced size (RS)-MMC, MMCmicro), a secure digital (SD) card (SD, miniSD, microSD, secure digital high capacity (SDHC)), a universal flash memory device (UFS), etc. The storage device  100  may include a mounted memory such as an embedded multimedia card (eMMC), a UFS, a perfect page new (PPN), etc. 
       FIG. 22  is a block diagram illustrating a memory controller in accordance with an exemplary embodiment of the inventive concept. Referring to  FIG. 22 , the memory controller  120  includes a bus  121 , a processor  122 , a RAM  123 , an ECC block  124 , a host interface  125 , a buffer control circuit  126  and a memory interface  127 . 
     The bus  121  is configured to provide a channel among constituent elements of the memory controller  120 . 
     The processor  122  can control an overall operation of the memory controller  120  and perform a logical operation. The processor  122  can communicate with an external host device through the host interface  125 . The processor  122  can store the second command CMD 2  and the second address ADDR 2  received through the host interface  125  in the RAM  123 . The processor  122  can generate the first command CMD 1  and the first address ADDR 1  according to the second command CMD 2  and the second address ADDR 2  stored in the RAM  123  and output the generated first command CMD 1  and the first address ADDR 1  through the memory interface  127 . 
     The processor  122  can output the second data DATA 2  received through the host interface  125  through the buffer control circuit  126  or store the second data DATA 2  in the RAM  123 . The processor  122  can output data stored in the RAM  123  or data received through the buffer control circuit  126  through the memory interface  127  as the first data DATA 1 . The processor  122  can store the first data DATA 1  received through the memory interface  127  in the RAM  123  or output the first data DATA 1  through the buffer control circuit  126 . The processor  122  can output data stored in the RAM  123  or data received through the buffer control circuit  126  through the host interface  125  as the second data DATA 2  or through the memory interface  127  as the first data DATA 1 . 
     The RAM  123  may be used as an operation memory, a cache memory or a buffer memory of the processor  122 . The RAM  123  can store codes and commands executed by the processor  122 . The RAM  123  can store data processed by the processor  122 . The RAM  123  may include an SRAM. 
     The ECC block  124  can perform an error correction operation. The ECC block  124  can generate an error correction code (for example, parity) for performing an error correction on the basis of the first data DATA 1  to be output to the memory interface  127  or the second data DATA 2  received from the host interface  125 . The first data DATA 1  and the parity can be output through the memory interface  127 . The ECC block  124  can perform an error correction of the received first data DATA 1  using the first data DATA 1  and the parity received through the memory interface  127 . The ECC block  124  may be included in the memory interface  127  as a constituent element of the memory interface  127 . 
     The host interface  125  is configured to communicate with an external host device under the control of the processor  122 . The host interface  125  can receive the second command CMD 2  and the second address ADDR 2  from the external host device and exchange the second data DATA 2  with the external host device. 
     The host interface  125  may be configured to perform a communication using at least one of many different communication methods such as a universal serial bus (USB), a serial advanced technology attachment (SATA), a serial attachment small computer system interface (SAS), a high speed interchip (HSIC), a small computer system interface (SCSI), a Firewire, a peripheral component interconnection (PCI), a PCI express (PCIe), a nonvolatile memory express (NVMe), a UFS, an SD, an MMC, an eMMC, etc. 
     The buffer controller circuit  125  is configured to control the RAM  130  (refer to  FIG. 21 ) under the control of the processor  122 . The buffer control circuit  126  can write data in the RAM  130  and read data from the RAM  130 . 
     The memory interface  127  is configured to communicate with the nonvolatile memory  110  (refer to  FIG. 1 ) under the control of the processor  122 . The memory interface  127  can transmit the first command CMD 1  and the first address ADDR 1  to the nonvolatile memory  110  and exchange the first data DATA 1  and the control signal CTRL with the nonvolatile memory  110 . 
     The RAM  130  may not be provided to the storage device  100 . In other words, the storage device  100  may not have a separate memory outside the memory controller  120  and the nonvolatile memory  110 . In this case, the buffer control circuit  126  may not be provided to the memory controller  120 . A function of the RAM  130  may be performed by the internal RAM  123  of the memory controller  120 . 
     As an example, the processor  122  can control the memory controller  120  using codes. The processor  122  can load codes from nonvolatile memory (for example, read only memory) provided inside the memory controller  120 . As another example, the processor  122  can load codes received from the memory interface  127 . 
     The bus  121  of the memory controller  120  may be divided into a control bus and a data bus. The data bus may be configured to transmit data in the memory controller  120  and the control bus may be configured to transmit control information such as a command, an address, etc. in the memory controller  120 . The data bus and the control bus may be separated from each other and may not interfere or affect each other. The data bus may be connected to the host interface  125 , the buffer control circuit  126 , the ECC block  124  and the memory interface  127 . The control bus may be connected to the host interface  125 , the processor  122 , the buffer control circuit  126 , RAM  123  and the memory interface  127 . 
       FIG. 23  is a block diagram illustrating a computing device  1000  in accordance with an exemplary embodiment of the inventive concept. Referring to FIG.  23 , the computing device  1000  includes a processor  1100 , a RAM  1200 , a storage device  1300 , a modem  1400  and a user interface  1500 . 
     The processor  1100  can control an overall operation of the computing device  1000  and perform a logical operation. For example, the processor  1100  may be constituted in a system-on-chip (SoC). The processor  1100  may be a general-purpose processor, a specific-purpose processor, or an application processor. 
     The RAM  1200  can communicate with the processor  1100 . The RAM  1200  may be a main memory of the processor  1100  or the computing device  1000 . The processor  1100  can temporarily store a code or data in the RAM  1200 . The processor  1100  can execute a code and process data using the RAM  1200 . The processor  1100  can execute a variety of software such as an operating system, an application, etc. using the RAM  1200 . The processor  1100  can control an overall operation of the computing device  1000  using the RAM  1200 . The RAM  1200  may include a volatile memory such as an SRAM, a DRAM, an SDRAM, etc. or a nonvolatile memory such as a PRAM, an MRAM, an RRAM, an FeRAM, etc. 
     The storage device  1300  can communicate with the processor  1100 . The storage device  1300  can store data to be preserved for a long time. In other words, the processor  1100  can store data to be preserved for a long time in the storage device  1300 . The storage device  1300  can store a boot image for driving the computing device  1000 . The storage device  1300  can store source codes of a variety of software such as an operating system, an application, etc. The storage device  1300  can store data processed by a variety of software such as an operating system, an application, etc. 
     The processor  1100  can drive a variety of software such as an operating system, an application, etc. by loading source codes stored in the storage device  1300  into the RAM  1200  and then executing the source codes loaded into the RAM  1200 . The processor  1100  can load data stored in the storage device  1300  into the RAM  1200  and process the data loaded into the RAM  1200 . The processor  1100  can load data to be preserved for a long time among data stored in the RAM  1200  in the storage device  1300 . 
     The storage device  1300  may include a nonvolatile memory such as a flash memory, a PRAM, an MRAM, an RRAM, an FeRAM, etc. 
     The modem  1400  can communicate with an external device under the control of the processor  1100 . For example, the modem  1400  can perform a wired or wireless communication with an external device. The modem  1400  can perform a communication based on at least one of various wireless communication methods such as a long term evolution (LTE), a worldwide interoperability for microwave access (WiMax), a global system for mobile communication (GSM), a code division multiple access (CDMA), a Bluetooth, a near field communication (NFC), a wireless fidelity (WiFi), a radio frequency Identification (RFID), or at least one of various wired communication methods such as a USB, a SATA, an SCSI, a Firewire, a PCI, a PCIe, an NVMe, a UFS, an SD, a secure digital input output (SDIO), a universal asynchronous receiver transmitter (UART), a serial peripheral interface (SPI), a high speed SPI (HS-SPI), an RS232, an inter-integrated circuit (I2C), a high speed (HS)-I2C, an integrated-interchip sound (I2S), a sony/philips digital interface (S/PDIF), an MMC, an eMMC, etc. 
     The user interface  1500  can communicate with a user under the control of the processor  1100 . For example, the user interface  1500  may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, etc. The user interface  1500  may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix OLED (AMOLED) display, a light emitting diode (LED), a speaker, a motor, etc. 
     The storage device  1300  may include the storage device  100  according to exemplary embodiments of the inventive concept. The processor  1100 , the RAM  1200 , the modem  1400  and the user interface  1500  can form a host device communicating with the storage device  1300 . 
     According to exemplary embodiments of the inventive concept, threshold voltages of cell transistors, in particular, ground select transistors are programmed within the target range. Thus, a nonvolatile memory device having increased reliability and an operation method of the nonvolatile memory device are provided. 
     While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the scope of the inventive concept as defined by the following claims.