Patent Publication Number: US-7589582-B2

Title: Multi-level voltage generator

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an electronic circuit, and more particularly, to a multilevel voltage generator for generating a variety of voltage levels. 
   2. Description of the Related Art 
   A liquid crystal display (LCD) device that is a display device among electronic circuit apparatuses displays an image by controlling light transmissivity of liquid crystal using an electric field. To this end, the LCD device includes a liquid crystal panel in which liquid cells are arranged in a matrix format and a driving circuit for driving the liquid crystal panel. 
   The liquid crystal panel includes a thin film transistor formed at each of cross-points of gate lines and data lines and the liquid crystal cell connected to the thin film transistor. A gate electrode of the thin film transistor is connected to any one of the data lines in units of horizontal lines while a source electrode is connected to any one of the data lines in units of vertical lines. The thin film transistor supplies a pixel voltage signal from the data line to the liquid crystal cell in response to a scan signal from the gate line. 
   In order to drive the thin film transistor type LCD device (hereinafter, referred to as “TFr-LCD”), a gate drive for driving the gate lines of the thin film transistor and a source driver for driving the source lines of the thin film transistor are provided. The gate driver turns on the thin film transistor by applying a high voltage and the source driver applies an analog pixel signal to indicate color to the source line, so that an image is displayed on the TFT-LCD. 
   The source driver sequentially latches digital pixel data in response to a Sampling data, converts the latched digital pixel data to an analog pixel signal, and buffers and outputs the analog pixel signal. In particular, the source driver outputs a voltage corresponding to pixel data input of voltages V1-V64 corresponding to all bit combination of, for example, 6 bit pixel data, as a pixel signal. For this operation, the source driver includes blocks which are driven with a power of a variety of voltage levels. 
   The driving circuits such as the gate driver or the source driver need a variety of voltage levels and a multilevel voltage generator for generating a variety of voltage levels has been widely known. However, in accordance with the miniaturization of electronic circuit apparatuses, a multilevel voltage generator which can generate a variety of voltage levels with a reduced number of constituent elements is required. 
   SUMMARY OF THE INVENTION 
   To solve the above and/or other problems, the present invention provides a multilevel voltage generator with a reduced number of constituent elements. 
   According to an aspect of the present invention, a multilevel voltage generator comprises a first positive voltage generator generating a first output voltage using a first capacitor which receives a reference voltage and is charged to a voltage level corresponding to two times of the reference voltage, a second positive voltage generator generating a second output voltage and a third output voltage using a second capacitor and a third capacitor which receive the first output voltage and are charged to voltage levels corresponding to predetermined multiples of the reference voltage, and a negative voltage generator generating a fourth output voltage having predetermined negative voltage levels using a fourth capacitor which receives the reference voltage, the second output voltage, or the third output voltage and is charged to a voltage level corresponding to a negative voltage of the second or third output voltage. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram of a multilevel voltage generator according an embodiment of the present invention; 
       FIG. 2  is a circuit diagram of a first positive voltage generator of  FIG. 1 ; 
       FIG. 3  is an operation timing diagram of the first positive voltage generator of  FIG. 2 ; 
       FIG. 4  is a circuit diagram of a second positive voltage generator of  FIG. 1 ; 
       FIGS. 5 through 8  are operation timing diagrams of the second positive voltage generator of  FIG. 4 ; 
       FIG. 9  is a circuit diagram of a negative voltage generator of  FIG. 1 ; and 
       FIGS. 10 through 13  are timing diagrams of the negative voltage generator of  FIG. 9 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Referring to  FIG. 1 , a multilevel voltage generator  100  according to an embodiment of the present invention receives a reference voltage Vref and generates output voltages Va−Vd corresponding to a multiple of a level of the reference voltage Vref using a charge pumping method. The multilevel voltage generator  100  includes three steps of positive (+) voltage generators  100 ,  200 , and  300  and capacitors C 200 , C 300 , and C 400 . 
   The first positive (+) voltage generator  100  receives the reference voltage Vref, generates a first output voltage Va as its output, and charges the capacitor C 200  with the first output voltage Va. The second positive (+) voltage generator  200  receives the reference voltage Vref and the first output voltage Va, generates a second output voltage Vb and a third output voltage Vc, and charges the capacitor C 300  with the third output voltage Vc. The negative (−) voltage generator  400  receives the reference voltage Vref and the second and third output voltages Vb and Ve, generates a fourth output voltage Vd, and charges the capacitor C 400  with the fourth output voltage Vd. 
   The first positive voltage generator  100  receives the reference voltage Vref and generates the first output voltage Va having a level double the reference voltage Vref (2×Vref), which is shown in  FIG. 2 . Referring to  FIG. 2 , the first positive voltage generator  100  includes first through fourth switches S 202 , S 204 , S 206 , and S 208  and a first capacitor C 203 . The first switch S 202  transfer the reference voltage Vref to a node N 203  in response to a first control signal tpre 1 . The reference voltage Vref transferred to the node N 203  is charged in the first capacitor C 203 . The first capacitor C 203  is connected between a node N 207  and the node N 203  and coupled to a voltage levels of the nodes N 203  and N 207 . The voltage level of the node N 203  is transferred to the first output Va through the second switch S 204  responding to a third control signal tpass 1 . The node N 207  is connected to the third switch S 206  responding to the first control signal tpre 1  and the fourth switch S 208  responding to a second control signal tpimp 1 . The fourth switch S 208  transfers the reference voltage Vref to the node N 207  in response to the second control signal tpump 1 . The third switch S 206  and the fourth switch S 208  constitute a first level transfer portion  210  which transfers a ground voltage VSS or the reference voltage Vref. 
     FIG. 3  is an operation timing diagram of the first positive voltage generator  200  of  FIG. 2 . Referring to  FIG. 3 , in a first section, while the first control signal tpre 1  is a logic high level and the second and third control signals tpump 1  and tpass 1  are logic low levels, the node N 207 , the node N 203 , and the first output voltage Va are indicated as 0V, a Vref level, and 0V, respectively. In a second section, while the first control signal tpre 1  is a logic low level and the second and third control signals tpump 1  and tpass 1  are logic high levels, the node N 207 , the node N 203 , and the first output voltage Va are indicated as a Vref level, a Vref+ΔV 1  level, and the Vref+ΔV 1  level, respectively. After the first and second sections are repeated several times, in a section i, the node N 203  and the first output voltage Va are indicated as a 2×Vref level. 
     FIG. 4  is a circuit diagram of a second positive voltage generator of  FIG. 1 . Referring to  FIG. 4 , the second positive voltage generator  300  includes fifth through thirteenth switches S 302 , S 304 , S 306 , S 308 , S 310 , S 312 , S 314 , S 316 , and S 318  and second and third capacitors C 303  and C 311 . The fifth switch S 302  transfers the first output voltage Va output from the first positive voltage generator  200  to the second output Vb in response to a fourth control signal tpre 21 . The second capacitor C 303  is connected between the second output Vb and a node N 307  and coupled to the second output voltage Vb and the voltage of the node N 307 . 
   The voltage level of the node N 307  is determined by the sixth through eighth switches S 304 , S 406 , and S 308  which are a second level transfer portion  310 . The sixth switch S 304  transfers a ground voltage VSS level to the node N 307  in response to the fourth control signal tpre 21 . The seventh switch S 306  transfers the first output voltage Va to the node N 307  in response to a fifth control signal trump 21   a . The eighth switch S 308  transfers the reference voltage Vref to the node N 307  in response to a sixth control signal tpump 21   b.    
   The second output voltage Vb is transferred to a node N 311  via the ninth switch S 310  in response to a seventh control signal tpre 22 . The third capacitor C 311  is connected between the node  311  and a node N 315  and coupled to the voltage level of the node N 311  and the voltage level of the voltage of the node N 315 . The voltage level of the node N 315  is determined by the tenth and eleventh switches S 312  and S 314  which constitute a third level transfer portion  320 . The tenth switch S 314  transfers the ground voltage VSS to the node N 315  in response to a seventh control signal tpre 22 . The eleventh switch S 316  transfers the first output voltage Va to the node N 315  in response to an eighth control signal tpump 22 . 
   The second output voltage Vb is transferred to the third output voltage Vc via the twelfth switch S 318  in response to a ninth control signal tpass 21 . The voltage level of the node N 311  is transferred to the third output Vc via the thirteenth switch S 316  in response to a tenth control signal tpass 22 . 
     FIGS. 5 through 8  are operation timing diagrams of the second positive voltage generator of  FIG. 4 . It is assumed that the first output voltage Va is set to a 2×Vref level. 
     FIG. 5  shows a case in which both the second output voltage Vb and the third output voltage Vc are generated to a 3 ×Vref level. Referring to  FIG. 5 , in a first section, while the fourth control signal tpre 21  only is a logic high level and the other control signals such as tpump 21   b , tpump  21   a , and so on are logic low levels, the node N 307 , the second output voltage Vb, and the third output voltage Vc are indicated as 0V, a 2×Vref level, and 0V, respectively. In a second section, while the fourth control signal tpre 21  is a logic low level and the sixth and ninth control signals tpump 21   b  and tpass 21  are logic high levels, the node N 307 , the second output voltage Vb coupled to the voltage level of the node N 307 , and the third output voltage Vc are indicated as a 2×Vref level, a 2×Vref+ΔV 1  level, and the 2×Vref+ΔV 1  level which is the same as the level of the second output voltage Vb, respectively. After the first and second sections are repeated several times, in a section j, the second output voltage Vb and the third output voltage Vc are indicated as a 3×Vref level. 
     FIG. 6  shows a case in which both the second output voltage Vb and the third output voltage Vc are generated to a 4×Vref level. Referring to  FIG. 6 , in a first section, while the fourth control signal tpre 21  only is a logic high level and the other control signals such as tpump 21   b , tpump 21   a , and so on are logic low levels, the node N 307 , the second output voltage Vb, and the third output voltage Vc are indicated as 0V, a 2×Vref level, and 0V, respectively. In a second section, while the fourth control signal tpre 21  is a logic low level and the fifth and ninth control signals tpump 21   a  and tpass 21  are logic high levels, the node N 307 , the second output voltage Vb coupled to the voltage level of the node N 307 , and the third output voltage Vc are indicated as a 2×Vref level, a 2×Vref+ΔV 1  level, and the 2×Vref+ΔV 1  level which is the same as the level of the second output voltage Vb, respectively. After the first and second sections are repeated several times, in a section k, the second output voltage Vb and the third output voltage Vc are indicated as a 4×Vref level. 
     FIG. 7  shows a case in which the second output voltage Vb and the third output voltage Vc are generated to a 3×Vref level and a 5×Vref level, respectively. Referring to  FIG. 7 , in a first section, while the fourth control signal tpre 21  is a logic high level, the eight control signal tpump 22  is a logic high level, the tenth control signal tpass 22  is a logic high level, and the other control signals such as tpump 21   a , tpump 21   b , and so on are logic low levels, the node N 307 , the node N 315 , the node N 311 , the second output voltage Vb, and the third output voltage Vc are indicated as 0V, a 2×Vref level, the 2×Vref level, the 2×Vref level, and the 2×Vref level, respectively. In a second section, while the fourth control signal tpre 21  is a logic low level, the sixth control signal tpump 21   b  is a logic high level, the seventh control signal tpre 22  is a logic high level, the eighth control signal tpump 22  is a logic low level, and the tenth control signals tpass 22  is a logic low level, the node N 307 , the node N 315 , the second output voltage Vb coupled to the voltage level of the node N 307 , the node N 311  to which the second output voltage Vb is transferred, and the third output voltage Vc are indicated as a Vref level, 0V, a 2×Vref+ΔV 1  level, the 2×Vref+ΔV 1  level, and the 2×Vref level, respectively. After the first and second sections are repeated several times, in a section I, the second output voltage Vb and the third output voltage Vc are indicated as a 3×Vref level and a 5×Vref level, respectively. 
     FIG. 8  shows a case in which the second output voltage Vb and the third output voltage Vc are generated to a 4×Vref level and a 6×Vref level, respectively. Referring to  FIG. 8 , in a first section, while the fourth control signal tpre 21  is a logic high level, the eight control signal tpump 22  is a logic high level, the tenth control signal tpass 22  is a logic high level, and the other control signals such as tpump 21   a , tpump 21   b , and so on are logic low levels, the node N 307 , the node N 315 , the node N 311 , the second output voltage Vb, and the third output voltage Vc are indicated as 0V, a 2×Vref level, the 2×Vref level, the 2×Vref level, and the 2×Vref level, respectively. In a second section, while the fourth control signal tpre 21  is a logic low level, the fifth control signal tpump 21   a  is a logic high level, the seventh control signal tpre 22  is a logic high level, the eighth control signal tpump 22  is a logic low level, and the tenth control signals tpass 22  is a logic low level, the node N 307 , the node N 315 , the second output voltage Vb coupled to the voltage level of the node N 307 , the node N 311  to which the second output voltage Vb is transferred, and the third output voltage Vc are indicated as a 2×Vref level, 0V, a 2×Vref+ΔV 1  level, the 2×Vref+ΔV 1  level, and the 2×Vref level, respectively. After the first and second sections are repeated several times, in a section m, the second output voltage Vb and the third output voltage Vc are indicated as a 4×Vref level and a 6×Vref level, respectively. 
     FIG. 9  is a circuit diagram of a negative voltage generator of  FIG. 1 . Referring to  FIG. 9 , a negative voltage generator  400  includes fourteenth through nineteenth switches S 402 , S 404 , S 406 , S 408 , S 410 , and S 412  and a fourth capacitor C 405 . The fourteenth switch S 402  transfers the reference voltage Vref to a node N 405  in response to an eleventh control signal tpre 3   a . The fifteenth switch S 404  transfers the ground voltage VSS to the node N 405  in response to a twelfth control signal tpre 3   b . The fourth capacitor C 405  is connected between the node N 405  and the node N 407  and coupled to the voltage levels of the node N 405  and the node N 407 . 
   The voltage level of the node N 407  is determined by the sixteenth through eighteenth switches S 406 , S 408 , and S 410 . The sixteenth switch S 406  transfers the third output voltage Vc to the node N 407  in response to the thirteenth control signal tpre 3   c . The seventeenth switch S 406  transfers the second output voltage Vb to the node N 407  in response to the fourteenth control signal tpre 3   d . The eighteenth switch S 410  transfers the ground voltage VSS to the node N 407  in response to the fifteenth control signal tpump 3 . The nineteenth switch S 412  transfers the voltage level of the node N 405  to the fourth output Vd in response to the sixteenth control signal tpass 3 . 
     FIGS. 10 through 13  are timing diagrams of the negative voltage generator  400  of  FIG. 9   
     FIG. 10  shows a case in which the fourth output voltage Vd is generated as a negative voltage of the third output voltage Vc. Referring to  FIG. 10 , in a first section, while the eleventh control signal tpre 3   a  is a logic low level, the twelfth and thirteenth control signals tpre 3   b  and tpre 3   c  are logic high levels, and the fourteenth through sixteenth control signals tpre 3   d , tpump 3 , and tpass 3  are logic low levels, the node N 407 , the node N 405 , and the fourth output signal Vd are indicted as a Vc level, a 0V level, and the 0V level, respectively. In a second section, while the twelfth and thirteenth control signals tpre 3   b  and tpre 3   c  are logic low levels and the fifteenth and sixteenth control signals tpump 3  and tpass 3  are logic high levels, the node N 407 , the node N 405  coupled to the voltage level of the node N 407 , and the fourth output signal Vd to which the voltage level of the node N 405  is transferred are indicated as 0V, a −ΔV 1  level, and the −ΔV 1  level, respectively. After the first and second sections are repeated several times, in a section n, the fourth output voltage Vd is indicated as a negative voltage of the third output voltage Vc. 
     FIG. 11  shows a case in which the fourth output voltage Vd is generated as a negative voltage of the second output voltage Vb. Referring to  FIG. 11 , in a first section, while the eleventh control signal tpre 3   a  is a logic low level, the twelfth control signal tpre 3   b  is a logic high level, the thirteenth control signal tpre 3   c  is a logic low level, the fourteenth control signal tpre 3   d  is a logic high level, and the fifteenth and sixteenth control signals tpump 3  and tpass 3  are logic low levels, the node N 407 , the node N 405 , and the fourth output signal Vd are indicated as a Vb level, a 0V level, and the 0V level, respectively. In a second section, while the twelfth and fourteenth control signals tpre 3   b  and tpre 3   d  are logic low levels and the fifteenth and sixteenth control signals tpurnp 3  and tpass 3  are logic high levels, the node N 407 , the node N 405  coupled to the voltage level of the node N 407 , and the fourth output signal Vd to which the voltage level of the node N 405  is transferred are indicated as a 0V level, a −ΔV 1  level, and the −ΔV 1  level, respectively. After the first and second sections are repeated several times, in a section o, the fourth output voltage Vd is indicated as a negative voltage of the second output voltage Vb. 
     FIG. 12  shows a case in which the fourth output voltage Vd is generated as Voltage level (Vc−Vref) obtained by subtracting the reference voltage Vref from the negative voltage of the third output voltage Vc. Referring to  FIG. 12 , in a first section, while the eleventh control signal tpre 3   a  is a logic high level, the twelfth control signal tpre 3   b  is a logic low level, the thirteenth control signal tpre 3   c  is a logic high level, the fourteenth control signal tpre 3   d  is a logic low level, and the fifteenth and sixteenth control signals tpump 3  and tpass 3  are logic low levels, the node N 407 , the node N 405 , and the fourth output signal Vd are indicated as a Vc level, a Vref level, and a 0V level, respectively. In a second section, while the eleventh and thirteenth control signals tpre 3   a  and tpre 3   c  are logic low levels and the fifteenth and sixteenth control signals tpump 3  and tpass 3  are logic high levels, the node N 407 , the node N 405  coupled to the voltage level of the node N 407 , and the fourth output signal Vd to which the voltage level of the node N 405  is transferred are indicated as a 0V level, a Vref−ΔV 1  level, and the Vref−ΔV 1  level, respectively. After the first and second sections are repeated several times, in a section p, the fourth output voltage Vd is indicated as a voltage level (−|Vc−Vref|) obtained by subtracting the reference voltage Vref from a negative voltage of the third output voltage Vc. 
     FIG. 13  shows a case in which the fourth output voltage Vd is generated as Voltage level (Vb−Vref) obtained by subtracting the reference voltage Vref from the negative voltage of the second output voltage Vb. Referring to  FIG. 13 , in a first section, while the eleventh control signal tpre 3   a  is a logic high level, the twelfth control signal tpre 3   b  is a logic low level, the thirteenth control signal tpre 3   c  is a logic low level, the fourteenth control signal tpre 3   d  is a logic high level, and the fifteenth and sixteenth control signals tpump 3  and tpass 3  are logic low levels, the node N 407 , the node N 405 , and the fourth output signal Vd are indicated as a Vb level, a Vref level, and a 0V level, respectively. In a second section, while the eleventh and fourteenth control signals tpre 3   a  and tpre 3   d  are logic low levels and the fifteenth and sixteenth control signals tpump 3  and tpass 3  are logic high levels, the node N 407 , the node N 405  coupled to the voltage level of the node N 407 , and the fourth output signal Vd to which the voltage level of the node N 405  is transferred are indicated as a 0V level, a Vref−ΔV 1  level, and the Vref−ΔV 1  level, respectively. After the first and second sections are repeated several times, in a section q, the fourth output voltage Vd is indicated as a voltage level (−|Vb−Vref|) obtained by subtracting the reference voltage Vref from a negative voltage of the second output voltage Vb. 
   Thus, the multilevel voltage generator wording to the present invention Includes the first positive voltage generator  200 , the second positive voltage generator  300 , and the negative voltage generator  400 , each of which including the capacitors C 203 , C 303  and C 311 , and C 405 , respectively, and generates the first output voltage Va having a 2×Vref level which is twice the reference voltage Vref, the second output voltage Vb having a 3×Vref or 4×Vref level which is three or four times of the reference voltage Vref, the third output voltage Vc having a 3×Vref, 4×Vref, 5×Vref, or 6×Vref level which is three, four, five, or six times of the reference voltage Vref, the negative voltage of the third output voltage Vc, the negative voltage of the second output voltage Vb, and the fourth output voltage Vd having a voltage level (Vc−Vref) obtained by subtracting the reference voltage Vref from the negative voltage of the third output voltage Vc or a voltage level (Vb−Vref) obtained by subtracting the reference voltage Vref from the negative voltage of the second output voltage Vb. 
   As described above, awarding to the multilevel voltage generator according to The present invention, a variety of voltage levels such as the first through third output voltages which are two, three, four, five, or six times of the reference voltage, the negative second output voltage, the negative third output voltage, and the fourth output voltage having a voltage level obtained by subtracting the reference voltage from the negative second output voltage or a voltage level obtained by subtracting the reference voltage from the negative third output voltage are generated wording to the voltage level charging the capacitor by a combination of the control signals. That is, by generating a variety of voltage levels using one capacitor, the number of the constituent elements of the multilevel voltage generator are reduced. 
   While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.