Patent Publication Number: US-11658229-B2

Title: Semiconductor device and method for fabricating the same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method for fabricating semiconductor device, and more particularly to a method of using etching process to trim spacers before forming epitaxial layer. 
     2. Description of the Prior Art 
     In order to increase the carrier mobility of semiconductor structure, it has been widely used to apply tensile stress or compressive stress to a gate channel. For instance, if a compressive stress were to be applied, it has been common in the conventional art to use selective epitaxial growth (SEG) technique to form epitaxial structure such as silicon germanium (SiGe) epitaxial layer in a silicon substrate. As the lattice constant of the SiGe epitaxial layer is greater than the lattice constant of the silicon substrate thereby producing stress to the channel region of PMOS transistor, the carrier mobility is increased in the channel region and speed of MOS transistor is improved accordingly. Conversely, silicon carbide (SiC) epitaxial layer could be formed in silicon substrate to produce tensile stress for gate channel of NMOS transistor. 
     Current approach of forming MOS transistor having epitaxial layer typically conducts a lightly doped ion implantation process to form lightly doped drains (LDDs) in the substrate adjacent to two sides of the spacer before forming epitaxial layers. However, lightly doped drains formed by ion implantation process is unable to accurately control the dopant distribution within the lightly doped drains thereby resulting in leakage and short channel effect (SCE). Hence, how to improve the current fabrication to resolve this issue has become an important task in this field. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees. 
     According to another aspect of the present invention, a semiconductor device includes a gate structure on a substrate, a spacer adjacent to the gate structure, and an epitaxial layer adjacent to the spacer. Preferably, the epitaxial layer comprises a protrusion having an angle greater than 30 degrees under the spacer. 
     According to yet another aspect of the present invention, a semiconductor device includes a gate structure on a substrate, a spacer adjacent to the gate structure, a first epitaxial layer adjacent to the spacer, a second epitaxial layer having a V-shape on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 - 6    illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. 
         FIG.  7    illustrates a structural view of a semiconductor device according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS.  1 - 6   ,  FIGS.  1 - 6    illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in  FIG.  1   , a substrate  12  is provided, and gate structures  14  and  16  are formed on the substrate  12 . In this embodiment, the formation of the gate structures  14  and  16  could be accomplished by sequentially forming a gate dielectric layer, a gate material layer, and a hard mask on the substrate  12 , conducting a pattern transfer process by using a patterned resist (not shown) as mask to remove part of the hard mask, part of the gate material layer, and part of the gate dielectric layer through single or multiple etching processes, and stripping the patterned resist. This forms gate structures  14  and  16  on the substrate  12 , in which each of the gate structures  14  and  16  includes a patterned gate dielectric layer  18 , patterned gate material layer  20 , and patterned hard mask  22 . It should be noted that to emphasize the formation of epitaxial layer between the two gate structures  14  and  16  in the later process, two transistors are presented in this embodiment and only part of the transistor elements including the region between two gate structures  14  and  16  are shown in the following figures. 
     In this embodiment, the substrate  12  could be a semiconductor substrate such as a silicon substrate, an epitaxial substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The gate dielectric layer  18  could include silicon oxide (SiO 2 ), silicon nitride (SiN), or high-k dielectric material; the gate material layer  20  could include metal, polysilicon, or silicide; the material of hard mask  22  could be selected from the group consisting of SiO 2 , SiN, SiC, and SiON. 
     According to an embodiment of the present invention, a plurality of doped wells or shallow trench isolations (STIs) could be selectively formed in the substrate  12 . Despite the present invention pertains to a planar MOS transistor, it would also be desirable to apply the process of the present invention to non-planar transistors, such as FinFET devices, and in such instance, the substrate  12  shown in  FIG.  1    would be a fin-shaped structure formed atop a substrate  12 . 
     Next, at least one spacer is formed on sidewalls of each of the gate structures  14  and  16 , and an ion implantation process such as a tilted angle implantation process could be conducted to implant dopants into the substrate  12  adjacent to two sides of the gate structures  14 ,  16  for forming pocket regions  26 . In this embodiment, the spacer formed on sidewalls of each of the gate structures  14 ,  16  is preferably a composite spacer further including a spacer  28  disposed or directly contacting sidewalls of the gate structures  14 ,  16  or gate electrodes and a spacer  30  disposed on sidewalls of the spacer  28 , in which each of the inner spacer  28  and the outer spacer  30  includes an I-shape cross-section. In this embodiment, the inner spacer  28  and the outer spacer  30  could be made of same material or different materials as both the spacers  28 ,  30  could include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combination thereof. Preferably, the pocket regions  26  and the type of transistor device being fabricated include different conductive types. For instance, if a PMOS transistor were fabricated in this embodiment, the pocket regions  26  preferably include n-type dopants, but not limited thereto. 
     Next, as shown in  FIG.  2   , a first etching process is conducted to form initial recesses  32  in the substrate  12  adjacent to two sides of the spacer  30 . In this embodiment, the first etching process preferably includes dry etching process and the first etching process could further includes three stage of etching processes, in which the first stage etching process includes a vertical direction etching process conducted to remove part of the substrate  12 , the second stage etching process includes a horizontal direction etching process conducted to remove part of the substrate  12 , and the third stage etching process includes another vertical direction etching process conducted to remove part of the substrate  12  for forming the recesses  32 . 
     Specifically, the first stage etching process preferably includes hydrogen bromide (HBr) and/or helium (He), in which the flow of HBr and/or He is approximately 200/20 standard cubic centimeter per minute (sccm) and the duration of the process is approximately 11 seconds. The second stage etching process preferably includes chlorine gas (Cl 2 ) and/or ammonia (NH 3 ), in which the flow of Cl 2  and NH 3  is approximately 50/10 sccm while the duration of the process is approximately 15 seconds. The third stage etching process preferably includes hydrogen bromide (HBr) and/or helium (He), in which the flow of HBr and/or He is approximately 200/20 sccm and the duration of the process is approximately 6-10 seconds. 
     Next, as shown in  FIG.  3   , a second etching process is conducted to trim the spacer  30  for reducing the overall thickness or width of the spacer  30 . In this embodiment, the second etching process preferably includes another dry etching process and gases used in the second etching process could include trifluoromethane (CHF 3 ), tetrafluoromethane (CF 4 ), or combination thereof, in which the flow of CHF 3  or CF 4  is approximately 35/60 sccm and duration of the etching process is about 0.05 ns. It should be noted that the etching gas used during the second etching process not only trims the spacer  30  but also removes part of the substrate  12  adjacent to two sides of the spacer  30  to form voids  34  or indentations directly under the spacer  30 . Despite the width of the spacer  30  is slightly reduced during the second etching process, the bottom surface of the spacer  30  is still even with the surface of the substrate  12  so that the top surface of the voids  34  is also even with the surface of the substrate  12  directly under the gate structures  14 ,  16  or the bottom surface of the spacer  28 . According to other embodiment of the present invention, the voids  34  could not only expose the bottom surface of the spacer  30  but could also be extended inward to expose the bottom surface of the spacer  28 , which is also within the scope of the present invention. 
     Next, as shown in  FIG.  4   , a third etching process is conducted to isotropically expand or enlarge the initial recesses  32  for forming recesses  36 . In this embodiment, the third etching process preferably includes wet etching process, in which the wet etching process could be accomplished using etchant including but not limited to for example ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH). It should be noted that the formation of the recesses  36  is not limited to wet etching process disclosed in this embodiment. Instead, the recesses  36  could also be formed by single or multiple dry etching and/or wet etching processes, which are all within the scope of the present invention. According to an embodiment of the present invention, each of the recesses  36  could have various cross-section shapes, including but not limited to for example a circle, a hexagon, or an octagon. Despite the cross-section of each of the recesses  36  in this embodiment pertains to be a hexagon, it would also be desirable to form the recesses  36  with aforementioned shapes, which are all within the scope of the present invention. 
     Next, as shown in  FIG.  5   , a selective epitaxial growth (SEG) process is conducted to form buffer layers  38  and epitaxial layers  40  in the recesses  36  while filling the voids  34  completely. In this embodiment, the combination of buffer layers  38  and epitaxial layers  40  preferably constitute a hexagon shaped cross-section and a top surface of the epitaxial layers  40  is slightly higher than a top surface of the substrate  12 . Taking an epitaxial layer adjacent to one side of the gate structure such as the epitaxial layer  40  between the gate structures  14 ,  16  as an example, two protrusions including a first protrusion  42  and a second protrusion  44  are formed adjacent to two sides of the epitaxial layer  40  by filling the voids  34  with epitaxial layer  40  as the two protrusions  42 ,  44  contact the bottom surfaces of the spacers  30  directly. Preferably, each of the first protrusion  42  and the second protrusion  44  includes a V-shape directly under the spacer  30 , the included angle φ of the V-shape is preferably greater than 30 degrees and less than 90 degrees, and the depth D of each of the first protrusion  42  and the second protrusions  44  is less than ⅕ of the entire depth of the epitaxial layer  40  including but not limited to for example 5 nm to 30 nm. 
     In this embodiment, the epitaxial layers  40  could also be formed to include different material depending on the type of transistor being fabricated. For instance, if the MOS transistor being fabricated were to be a PMOS transistor, the epitaxial layers  40  could be made of material including but not limited to for example SiGe, SiGeB, or SiGeSn. If the MOS transistor being fabricated were to be a NMOS transistor, the epitaxial layers  40  could be made of material including but not limited to for example SiC, SiCP, or SiP. Moreover, the SEG process could also be adjusted to form a single-layered epitaxial structure or multi-layered epitaxial structure, in which heteroatom such as germanium atom or carbon atom of the structure could be formed to have gradient while the surface of the epitaxial layers  40  is preferred to have less or no germanium atom at all to facilitate the formation of silicide afterwards. Since the present embodiment pertains to the fabrication of PMOS transistor, the germanium content within the epitaxial layers  40  is preferably between 30% to 50% while the concentration of boron in the epitaxial layers  40  is preferably between 1.0×10 2 ° atoms/cm 3  to 1.0×10 21  atoms/cm 3 . 
     It should be noted that in contrast to using ion implantation approach for forming lightly doped drains (LDDs) in current process, the present invention preferably omits the process of conducting ion implantation process for forming LDDs but instead employs an in-situ doping approach to form doped regions with even concentration distribution during the formation of the epitaxial layers  40 . Preferably, the doped regions formed in the first protrusion  42  and the second protrusions  44  are serving as lightly doped drains  24 . After the LDDs  24  are formed, an ion implantation process could be conducted to implant dopants into substantially central region of the epitaxial layers  40  such as regions not directly under the spacer  30  and outside the first protrusion  42  and the second protrusion  44  for forming source/drain regions  46 , in which the concentration of the source/drain regions  46  is greater than the concentration of the lightly doped drains  24  formed in the first protrusion  42  and second protrusion  44  while the two regions  24 ,  46  share dopants of same conductive type. Next, a cap layer  48  is formed on the epitaxial layers  40 , in which the cap layer  48  made of pure silicon is preferably grown upward along the sidewalls of the spacer  30  and a top surface of the cap layer  48  preferably includes a planar surface. 
     Next, as shown in  FIG.  6   , a contact etch stop layer (CESL) (not shown) and an interlayer dielectric (ILD) layer  54  are formed on the gate structure  14 ,  16 , and a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the ILD layer  54  and part of the CESL to expose hard masks  22  so that the top surfaces of the hard masks  22  and ILD layer  54  are coplanar. 
     Next, a replacement metal gate (RMG) process is conducted to transform the gate structures  14 ,  16  into metal gates. For instance, the RMG process could be accomplished by first performing a selective dry etching or wet etching process, such as using etchants including but not limited to for example ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the hard masks  22 , gate material layer  20  and even gate dielectric layer  18  for forming recesses (not shown) in the ILD layer  54 . Next, a selective interfacial layer  56  or gate dielectric layer, a high-k dielectric layer  58 , a work function metal layer  60 , and a low resistance metal layer  62  are formed in the recesses, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer  62 , part of work function metal layer  60 , and part of high-k dielectric layer  58  to form gate structures  14 ,  16  made from metal gates  64 ,  66 . In this embodiment, each of the gate structures  14 ,  16  or metal gates fabricated through high-k last process of a gate last process preferably includes an interfacial layer  56  or gate dielectric layer (not shown), a U-shaped high-k dielectric layer  58 , a U-shaped work function metal layer  60 , and a low resistance metal layer  62 . 
     In this embodiment, the high-k dielectric layer  58  is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer  58  may be selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), barium strontium titanate (Ba x Sr 1-x TiO 3 , BST) or a combination thereof. 
     In this embodiment, the work function metal layer  60  is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the work function metal layer  60  having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer  60  having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer  60  and the low resistance metal layer  62 , in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer  62  may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof. 
     Next, part of the high-k dielectric layer  58 , part of the work function metal layer  60 , and part of the low resistance metal layer  62  are removed to form recesses (not shown), hard masks  68  are then formed into the recesses, and a planarizing process is conducted so that the top surfaces of the hard masks  68  and ILD layer  54  are coplanar. The hard masks  68  could be made of material including but not limited to for example SiO 2 , SiN, SiON, SiCN, or combination thereof. 
     Next, a contact plug formation could be conducted to form contact plugs  70  electrically connected to the source/drain regions  46 . In this embodiment, the formation of contact plugs  70  could be accomplished by removing part of the ILD layer  54  and part of the CESL to form contact holes (not shown), and then depositing a barrier layer (not shown) and a metal layer (not shown) into the contact holes. A planarizing process, such as CMP is then conducted to remove part of the metal layer, part of the barrier layer, and even part of the ILD layer  54  to form contact plugs  70 , in which the top surface of the contact plugs  70  is even with the top surface of the ILD layer  54 . In this embodiment, the barrier layer is selected from the group consisting of Ti, Ta, TiN, TaN, and WN, and the metal layer is selected from the group consisting of Al, Ti, Ta, W, Nb, Mo, and Cu. 
     Referring again to  FIG.  6   ,  FIG.  6    further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown in  FIG.  6   , the semiconductor device preferably includes at least a gate structure  14  made of metal gate  64  disposed on the substrate  12 , spacers  28 ,  30  disposed adjacent to the gate structure  14 , pocket regions  26  disposed in the substrate  12  adjacent to two sides of the gate structure  14 , and epitaxial layers  40  disposed in the substrate  12  adjacent to two sides of the spacers  30 , in which each of the epitaxial layers  40  includes two protrusions and each of the protrusions includes an angle greater than 30 degrees directly under the spacer  30 . 
     Specifically, the epitaxial layer adjacent to one side of the gate structure such as the epitaxial layer  40  between the gate structures  14 ,  16  includes a first protrusion  42  adjacent to one side of the epitaxial layer  40  and a second protrusion  44  adjacent to another side of the epitaxial layer  40 , in which the first protrusion  42  is disposed in the substrate  12  adjacent to one side of the gate structure  14  from another perspective while the second protrusion  44  is disposed in the substrate  12  adjacent to one side of the gate structure  16 . Viewing from a more detailed perspective, the first protrusion  42  directly contacts the bottommost surface of the spacer  30  adjacent to the gate structure  14 , the second protrusion  44  directly contacts the bottommost surface of the spacer  30  adjacent to the gate structure  16 , each of the first protrusion  42  and the second protrusion  44  includes a V-shape directly under the spacer  30 , the included angle φ of the V-shape is preferably greater than 30 degrees and less than 90 degrees, and the depth D of each of the first protrusion  42  and the second protrusions  44  is less than ⅕ of the entire depth of the epitaxial layer  40  including but not limited to for example 5 nm to 30 nm. 
     Referring to  FIG.  7   ,  FIG.  7    illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown in  FIG.  7   , it would be desirable to first form first epitaxial layers  72  in the recesses  32  filling or without filling the voids  34  after forming the buffer layer  38  shown in  FIG.  5   , conduct a fourth etching process by using hydrofluoric acid (HCl) to remove part of the first epitaxial layers  72 , forms second epitaxial layers  74  having V-shape cross-section on the first epitaxial layers  72 , forms third epitaxial layers  76  on the second epitaxial layers  74 , and then forms the cap layer  48  on the third epitaxial layers  76 . 
     It should be noted in order to improve current leakage of the device, it would be desirable to form the first epitaxial layers  72  with in-situ dopants for forming source/drain regions  46  in the first epitaxial layers  72  and the third epitaxial layers  76  and form the second epitaxial layers  74  having another in-situ dopants with opposite conductive type in the second epitaxial layers  74  for forming lightly doped drains  24 . In this embodiment for fabricating PMOS transistor, the source/drain regions  46  in the first epitaxial layers  72  and the third epitaxial layers  76  preferably include p-type dopants while the lightly doped drains  24  in the second epitaxial layers  74  include n-type dopants. 
     Overall, the second epitaxial layers  74  includes a substantially V-shape cross-section and similar to the epitaxial layers  40  from the aforementioned embodiment, two protrusions including a first protrusion  42  and a second protrusion  44  serving as lightly doped drains  24  are formed adjacent to two sides of the second epitaxial layer  74  by filling the voids  34  with second epitaxial layers  74  as the two protrusions  42 ,  44  contact the bottom surfaces of the spacers  30  directly. Preferably, each of the first protrusion  42  and the second protrusion  44  includes a V-shape directly under the spacer  30 , the included angle φ of the V-shape is preferably greater than 30 degrees and less than 90 degrees, and the depth D of each of the first protrusion  42  and the second protrusions  44  is less than ⅕ of the overall depth from the first epitaxial layers  72  to the third epitaxial layers  76  including but not limited to for example 5 nm to 30 nm. In this embodiment, the germanium content within the first epitaxial layers  72  and/or the third epitaxial layers  76  is preferably between 30% to 50% while the concentration of boron in the epitaxial layers  72  and  76  is preferably between 1.0×10 2 ° atoms/cm 3  to 1.0×10 2 ′ atoms/cm 3 . The germanium content within the second epitaxial layers  74  is preferably between 30% to 50% while the concentration of n-type dopants such as phosphorus in the epitaxial layers  74  is preferably between 1.0×10 16  atoms/cm 3  to 1.0×10 21  atoms/cm 3 . 
     Typically, an extra lightly doped ion implantation process is conducted after using ion implantation process to form pocket regions  26  and before using the aforementioned first etching process to form recesses  32  in the substrate to form lightly doped drains in the substrate adjacent to two sides of the spacer. Since lightly doped drains formed by ion implantation process is unable to accurately control the concentration distribution of dopants within the lightly doped drains thereby resulting in leakage and short channel effect (SCE), the present invention preferably omits the process of conducting ion implantation process for forming LDDs but instead employs an in-situ doping approach to form lightly doped regions (such as the first protrusion  42  and second protrusion  44 ) with uniform concentration distribution during the formation of the epitaxial layers (such as the second epitaxial layer  74 ). Moreover, another embodiment of the present invention involves performing an etching process to trim or thin the outer spacer  30  so that the lightly doped drains form by in-situ doping and epitaxial layers could be formed closer to the gate structures thereby improving the performance of the device. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.