Patent Publication Number: US-2023163790-A1

Title: Digital radio frequency transmitter and wireless communication device including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 17/196,463, filed on Mar. 9, 2021, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0062578, filed on May 25, 2020, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein in its entirety by reference. 
    
    
     BACKGROUND 
     The inventive concepts relate to digital radio frequency (RF) transmitters for reducing or minimizing an intermodulation distortion component caused by non-linear amplification of an amplifier at the time when an RF analog signal is generated and more particularly, to digital RF transmitters and/or wireless communication devices including the same. 
     Recently, wireless communication systems have been developed from single mode systems to systems, such as second generation (2G), third generation (3G), fourth generation (4G), and fifth generation (5G) systems, which simultaneously support multiple bands and/or modes. To support multiple bands and/or modes, wireless communication systems need to communicate via a frequency band corresponding to each standard, while attenuating signals in other frequency bands to reduce or minimize an influence on the other frequency bands. According to the related art, a digital RF transmitter of a wireless communication device operates based on a non-linear amplifier, and accordingly an unwanted harmonic component may be generated. Thus, an intermodulation distortion component may be generated due to the non-linearity of a power amplifier when an RF analog signal including the harmonic component passes through the power amplifier. 
     A filter is provided at the front or back end of the power amplifier to remove the intermodulation distortion component. However, the number of filters exponentially increases because recent wireless communication systems need to cover up to the millimeter-wave band, and accordingly cost and a layout area increase. 
     SUMMARY 
     The inventive concepts provide digital radio frequency (RF) transmitters including a structure for blocking an intermodulation distortion component occurring due to non-linear amplification and/or wireless communication devices including the digital RF transmitter. 
     According to an aspect of the inventive concepts, a digital RF transmitter may include processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and the I-Q binary data pair resulting from conversion of a baseband signal, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3. 
     According to another aspect of the inventive concepts, a wireless communication device may include a modem configured to modulate digital data and output “k” bits of I data, “k” bits of Q data, “k” bits of inverted I data, and “k” bits of inverted Q data, where “k” is an integer of at least 2, a digital RF transmitter configured to generate a first pattern signal having a pattern corresponding to a pattern of an I-Q binary data pair and a pattern of an inverted I-Q binary data pair, the I-Q binary data pair and the inverted I-Q binary data pair being generated based on thermometer-to-binary conversion on the I data, the Q data, the inverted I data, and the inverted Q data, and remove an n-th harmonic component of an RF analog signal by generating a second pattern signal and a third pattern signal, the second pattern signal having a first phase difference from the first pattern signal, and the third pattern signal having a second phase difference from the first pattern signal, where “n” is an integer of at least 3, and a power amplifier configured to receive the RF analog signal and to generate an RF output signal by amplifying the RF analog signal, the RF analog signal being generated by summing the first through third pattern signals. 
     According to a further aspect of the inventive concepts, a wireless communication device may include a first SC-DAC circuit including a plurality of first paths, each including a first amplifier and a first capacitor, the first SC-DAC circuit configured to receive a plurality of first pattern signals in parallel and output a first RF signal by summing the plurality of first pattern signals, a second SC-DAC circuit including a plurality of second paths, each including a second amplifier and a second capacitor, the second SC-DAC circuit configured to receive a plurality of second pattern signals in parallel and output a second RF signal by summing the plurality of second pattern signals, a third SC-DAC circuit including a plurality of third paths, each including a third amplifier and a third capacitor, the third SC-DAC circuit configured to receive a plurality of third pattern signals in parallel and output a third RF signal by summing the plurality of third pattern signals, processing circuitry configured to generate the plurality of first pattern signals based on patterns of I-Q binary data pairs and patterns of inverted I-Q binary data pairs, the plurality of second pattern signals, and the plurality of third pattern signals, the plurality of second pattern signals lagging the plurality of first pattern signals by a first phase, and the plurality of third pattern signals lagging the plurality of first pattern signals by a second phase, and a first output terminal connected to an output terminal of each of the first through third SC-DAC circuits and configured to output an RF analog signal by summing the first through third RF signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG.  1    is a schematic block diagram of a wireless communication device according to an example embodiment; 
         FIG.  2    is a block diagram of a wireless communication device according to an example embodiment; 
         FIGS.  3 A through  3 D  are graphs for describing the operation of a switched-capacitor digital-to-analog converter (SC-DAC) in  FIG.  2   , according to an example embodiment; 
         FIG.  4    is a block diagram of a pattern signal generator according to an example embodiment; 
         FIGS.  5 A through  5 C  are timing diagrams for describing operations of the pattern signal generator of  FIG.  4   ; 
         FIG.  6    is a circuit diagram of first through third SC-DAC circuits according to an example embodiment; 
         FIG.  7    is a diagram for describing a method of determining the magnitude of a first radio frequency (RF) signal in a first SC-DAC circuit, according to an example embodiment; 
         FIG.  8    is a diagram for describing equivalent capacitors of the first through third SC-DAC circuits in  FIG.  6   ; 
         FIG.  9    is a diagram for describing a supply voltage applied to amplifiers of each of the first through third SC-DAC circuits in  FIG.  6   ; 
         FIG.  10    is a diagram for describing patterns of an RF analog signal generated by summing first through third RF signals in  FIG.  6   ; 
         FIG.  11    is a block diagram of a pattern signal generator according to an example embodiment; 
         FIG.  12 A  is a block diagram of a first signal generation circuit in  FIG.  11   ;  FIG.  12 B  is a diagram illustrating an RF analog signal generated by the first signal generation circuit of  FIG.  12 A ;  FIG.  12 C  is a diagram of an example implementation of first through third component signal generation logics in  FIG.  12 A ; 
         FIG.  13 A  is a block diagram of a second signal generation circuit in  FIG.  11   ;  FIG.  13 B  is a diagram illustrating an RF analog signal generated by the second signal generation circuit of  FIG.  13 A ;  FIG.  13 C  is a diagram of an example implementation of fourth through six component signal generation logics in  FIG.  13 A ; 
         FIG.  14 A  is a block diagram of a third signal generation circuit in  FIG.  11   ;  FIG.  14 B  is a diagram illustrating an RF analog signal generated by the third signal generation circuit of  FIG.  14 A ;  FIG.  14 C  is a diagram of an example implementation of seventh through ninth component signal generation logics in  FIG.  14 A ; 
         FIG.  15 A  is a block diagram of a fourth signal generation circuit in  FIG.  11   ;  FIG.  15 B  is a diagram illustrating an RF analog signal generated by the fourth signal generation circuit of  FIG.  15 A ;  FIG.  15 C  is a diagram of an example implementation of tenth through twelfth component signal generation logics in  FIG.  15 A ; 
         FIG.  16    is a diagram for describing an operation of an SC-DAC, according to an example embodiment; 
         FIG.  17    is a diagram of the configuration of a digital RF transmitter according to an example embodiment; 
         FIG.  18    is a diagram of an example of applying a deactivation of opposite cell (DOC) logic to the wireless communication device of  FIG.  1   , wherein the DOC logic may be applied to the wireless communication device to reduce or minimize the power consumption of an SC-DAC; and 
         FIG.  19    is a block diagram of a wireless communication device, according to an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings. 
       FIG.  1    is a schematic block diagram of a wireless communication device  1  according to an example embodiment. For convenience of description, a signal output from a digital radio frequency (RF) transmitter  10  may be defined as an RF analog signal, and a signal output from a power amplifier (PA)  40  may be defined as an RF output signal. 
     Referring to  FIG.  1   , the wireless communication device  1  may include the digital RF transmitter  10 , an RF receiver  20 , a modem  30 , the PA  40 , a low-noise amplifier (LNA)  50 , a duplexer  60 , and an antenna  70 . The wireless communication device  1  may further include a balun (not shown in  FIG.  1   ) between the PA  40  and the duplexer  60 , and this will be described in  FIG.  2   . The modem  30  may modulate a signal for transmission of information (e.g., digital information) and provide a digital signal to the digital RF transmitter  10  and may demodulate a digital signal from the RF receiver  20  to reconstruct an original signal. 
     The digital RF transmitter  10  may generate an RF analog signal in an RF frequency band from a digital signal from the modem  30  and provide the RF analog signal to the PA  40 . The digital RF transmitter  10  may include a switched-capacitor digital-to-analog converter (SC-DAC)  12  and a pattern signal generation circuit  14 . In some example embodiments, the digital RF transmitter  10  may include at least one SC-DAC. The SC-DAC  12  may include a plurality of amplifiers and a plurality of capacitors, and may convert a digital signal received from the modem  30  into an analog signal. In an example embodiment, each of the amplifiers of the SC-DAC  12  may be implemented by a switching amplifier including Class D or Class G. Thus, an unwanted p-th harmonic component p th _HM (where “p” is an integer of at least 2) may be generated when the SC-DAC  12  amplifies a certain signal in a part of an operation of converting a digital signal into an analog signal. Due to non-linearity of the PA  40 , an intermodulation distortion component may be generated from the p-th harmonic component p th _HM. 
     For example, when the SC-DAC  12  generates an RF analog signal corresponding to a digital signal, the RF analog signal may include a fundamental frequency component FFC corresponding to a first frequency fx and the p-th harmonic component p th _HM corresponding to a second frequency fy. Thereafter, when the RF analog signal is amplified by the PA  40 , an intermodulation distortion component IMDp corresponding to a third frequency fz, which is hard to remove using a filter near the first frequency fx, may be generated through intermodulation between the p-th harmonic component p th _HM and the fundamental frequency component FFC. As described above, although unwanted, the p-th harmonic component p th _HM may not be removed by a frequency filter (not shown), and thus may produce the intermodulation distortion component IMDp through intermodulation with other harmonic components. In other words, when the RF analog signal, which includes the fundamental frequency component FFC and the p-th harmonic component p th _HM, is output from the SC-DAC  12  and passes through the PA  40  having non-linearity, the intermodulation distortion component IMDp may be undesirably produced by intermodulation. Because the intermodulation distortion component IMDp is not removed by a low-pass filter, and becomes critical noise when an RF output signal is generated, the p-th harmonic component p th _HM may need to be removed in advance to mitigate or prevent the intermodulation distortion component IMDp from being produced. 
     According to an example embodiment, the pattern signal generation circuit  14  may remove the p-th harmonic component p th _HM from an RF analog signal before the RF analog signal of the digital RF transmitter  10  passes through the PA  40 . The pattern signal generation circuit  14  may have a configuration associated with the SC-DAC  12  to generate an inverted-phase component, which has an opposite phase to the p-th harmonic component p th _HM of the RF analog signal and the same magnitude as the p-th harmonic component p th _HM. The inverted-phase component may be added to the p-th harmonic component p th _HM of the RF analog signal, thereby reducing or removing the p-th harmonic component p th _HM. For example, the SC-DAC  12  may be configured to remove an p th _HM of the RF analog signal by amplifying first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “p” is an integer of at least. 
     In other words, the digital RF transmitter  10  may remove the p-th harmonic component p th _HM of an RF analog signal using an additionally generated inverted-phase component. Like or similarly to the SC-DAC  12 , the pattern signal generation circuit  14  may include a plurality of amplifiers and a plurality of capacitors. The pattern signal generation circuit  14  may include capacitors having a desired (or alternatively, predetermined) capacitance such that an inverted-phase component has a magnitude equal or substantially similar to that of the p-th harmonic component p th _HM of an RF analog signal. Further, signals having a desired (or alternatively, predetermined) phase difference with signals input to the SC-DAC  12  may be input to the pattern signal generation circuit  14  such that the inverted-phase component has an opposite phase to the p-th harmonic component p th _HM of the RF analog signal. In some example embodiments, a supply voltage having a different level than a supply voltage applied to the SC-DAC  12  may be applied to the pattern signal generation circuit  14  such that the magnitude of the inverted-phase component is as approximate to the magnitude of the p-th harmonic component p th _HM of the RF analog signal as possible. 
     The PA  40  may generate an RF output signal by amplifying the RF analog signal, from which the p-th harmonic component p th _HM has been reduced or removed, and output the RF output signal to the duplexer  60 . The antenna  70  connected to the duplexer  60  may emit the RF output signal to a base station or another wireless communication device. 
     The antenna  70  may receive and transmit an RF analog signal, which is generated according to an example embodiment, to the duplexer  60 , and the low-noise amplifier  50  may perform a low-noise amplification with regard to the RF analog signal and provide an amplified RF analog signal to the RF receiver  20 . The RF receiver  20  may convert the amplified RF analog signal into a baseband digital signal and provide the baseband digital signal to the modem  30 . 
     According to an example embodiment, the digital RF transmitter  10  may remove the p-th harmonic component p th _HM, which is produced due to non-linear switching amplification, from an RF analog signal in advance, thereby generating an RF output signal, from which an intermodulation distortion component that may be noise afterwards is blocked. Accordingly, the wireless communication device  1  may support improved communication performance. 
     Hereinafter, descriptions will be focused on the case where the p-th harmonic component p th _HM is a third harmonic component, for clear understanding. However, this is just an example. According to some example embodiments, an intermodulation distortion component caused by higher order harmonics than third may be blocked. 
       FIG.  2    is a block diagram of a wireless communication device  100  according to an example embodiment. 
     Referring to  FIG.  2   , the wireless communication device  100  may include a digital signal processor  110 , a controller  120 , a memory  122 , a thermometer-to-binary converter  130 , a pattern signal generator  140 , a crystal oscillator  150 , an SC-DAC  160 , a voltage regulator  170 , a front-end circuit  180 , and an antenna  190 . The digital signal processor  110 , the controller  120 , and the memory  122  may form the modem  30  in  FIG.  1   . The thermometer-to-binary converter  130 , the pattern signal generator  140 , the crystal oscillator  150 , the SC-DAC  160 , and the voltage regulator  170  may form the digital RF transmitter  10  in  FIG.  1   . The thermometer-to-binary converter  130  and the pattern signal generator  140  may form the pattern signal generation circuit  14  in  FIG.  1   . 
     The controller  120  may control the operations of the digital signal processor  110  and circuit blocks of the wireless communication device  100  using the memory  122 . The digital signal processor  110  may output inphase (I) data I 1 , quadrature (Q) data Q 1 , inverted I data IB 1 , and inverted Q data QB 1 , each having “k” bits (where “k” is an integer of at least 2), to the thermometer-to-binary converter  130 . The thermometer-to-binary converter  130  may perform thermometer-to-binary conversion on the I data I 1 , the Q data Q 1 , the inverted I data IB 1 , and the inverted Q data QB 1  and provide I binary data I 2 , Q binary data Q 2 , inverted I binary data IB 2 , and inverted Q binary data QB 2  to the pattern signal generator  140 . For example, when the I data I 1  has three bits “011” and the Q data Q 1  has three bits “010”, the thermometer-to-binary converter  130  may generate the I binary data I 2  by converting the I data I 1  into seven bits “0000111” and the Q binary data Q 2  by converting the Q data Q 1  into seven bits “0000011”. The thermometer-to-binary converter  130  may arrange the I binary data I 2 , the Q binary data Q 2 , the inverted I binary data IB 2 , and the inverted Q binary data QB 2  bit-by-corresponding bit and provide the I binary data I 2 , the Q binary data Q 2 , the inverted I binary data IB 2 , and the inverted Q binary data QB 2  in parallel to the pattern signal generator  140 . 
     The pattern signal generator  140  may generate first and second pattern signal groups PT_Sa and PT_Sb, which include pattern signals having a certain pattern corresponding to a pattern of an I-Q binary data pair and a pattern of an inverted I-Q binary data pair, using a frequency signal F_S received from the crystal oscillator  150  and provide the first and second pattern signal groups PT_Sa and PT_Sb to the SC-DAC  160 . For example, when the I binary data I 2  is “0000011”, the Q binary data Q 2  is “0000101”, the inverted I binary data IB 2  is “1111100”, and the inverted Q binary data QB 2  is “1111010”, the pattern of an I-Q binary data pair corresponding to the last bit may be “11” and the pattern of an inverted I-Q binary data pair corresponding to the last bit may be “00”, the pattern of an I-Q binary data pair corresponding to the second last bit may be “10” and the pattern of an inverted I-Q binary data pair corresponding to the second last bit may be “01”, the pattern of an I-Q binary data pair corresponding to the third last bit may be “01” and the pattern of an inverted I-Q binary data pair corresponding to the third last bit may be “10”, and the pattern of an I-Q binary data pair corresponding to the fourth last bit may be “00” and the pattern of an inverted I-Q binary data pair corresponding to the fourth last bit may be “11”. The pattern of an I-Q binary data pair or the pattern of an inverted I-Q binary data pair may be represented with four different expressions, and accordingly, a pattern signal may have four different patterns, which will be described in detail with reference to  FIGS.  5 A through  5 C  below. The pattern signal generator  140  described herein may be implemented using hardware components or a combination of software components and hardware component. For example, the hardware components may include microcontrollers, memory modules, sensors, amplifiers, band-pass filters, analog to digital converters, and processing devices, or the like. A processing device may be implemented using one or more hardware device(s) configured to carry out and/or execute program code by performing arithmetical, logical, and input/output operations. The processing device(s) may include processing circuitry, a processor, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a field programmable array, a programmable logic unit, a microprocessor or any other device capable of responding to and executing instructions in a defined manner. The processing device(s) may run an operating system (OS) and one or more software applications that run on the OS. The processing device also may access, store, manipulate, process, and create data in response to execution of the software. For purpose of simplicity, the description of a processing device is used as singular. However, one skilled in the art will appreciate that a processing device may include multiple processing elements and multiple types of processing elements. For example, a processing device may include multiple processors or a processor and a controller. In addition, different processing configurations are possible, such as parallel processors, multi-core processors, distributed processing, or the like. 
     The first pattern signal group PT_Sa may include pattern signals generated based on the pattern of an I-Q binary data pair and the pattern of an inverted I-Q binary data pair, and the second pattern signal group PT_Sb may include pattern signals having opposite phases to the pattern signals of the first pattern signal group PT_Sa. The pattern signal generator  140  may provide in parallel as many pattern signals PT_S as the number of bits in the I binary data I 2 , the Q binary data Q 2 , the inverted I binary data IB 2 , and the inverted Q binary data QB 2  to the SC-DAC  160 . For example, when each of the I binary data I 2 , the Q binary data Q 2 , the inverted I binary data IB 2 , and the inverted Q binary data QB 2  includes seven bits, the pattern signal generator  140  may generate the first pattern signal group PT_Sa including 28 pattern signals and may output the pattern signals in parallel to the SC-DAC  160 . 
     In an example embodiment, the pattern signal generator  140  may generate a clock signal by dividing the frequency signal F_S having a certain frequency and generate a plurality of clock signals, which have a certain phase difference from each other, from the clock signal. The pattern signal generator  140  may generate pattern signals using the clock signals, and this will be described in detail with reference to  FIGS.  4  and  11    below. 
     The SC-DAC  160  may include first through sixth SC-DAC circuits  162   a ,  164   a ,  166   a ,  162   b ,  164   b , and  166   b . The first through third SC-DAC circuits  162   a  through  166   a  may receive and perform digital-to-analog conversion on the first pattern signal group PT_Sa, and the fourth through sixth SC-DAC circuits  162   b  through  166   b  may receive and perform digital-to-analog conversion on the second pattern signal group PT_Sb. The second and third SC-DAC circuits  164   a  and  166   a  and the fifth and sixth SC-DAC circuits  164   b  through  166   b  may correspond to the pattern signal generation circuit  14  in  FIG.  1   . Hereinafter, descriptions will be focused on the first through third SC-DAC circuits  162   a  through  166   a , and it will be understood that the descriptions of the first through third SC-DAC circuits  162   a  through  166   a  may also be applied to the fourth through sixth SC-DAC circuits  162   b  through  166   b.    
     The first through third SC-DAC circuits  162   a  through  166   a  may include a plurality of paths, each of which includes an amplifier and a capacitor, to pass a pattern signal. In an example embodiment, when the first pattern signal group PT_Sa includes first through third pattern signals, the first SC-DAC circuit  162   a  may include a plurality of first paths, each of which includes a first amplifier and a first capacitor, to receive the first pattern signals in parallel, the second SC-DAC circuit  164   a  may include a plurality of second paths, each of which includes a second amplifier and a second capacitor, to receive the second pattern signals in parallel, and the third SC-DAC circuit  166   a  may include a plurality of third paths, each of which includes a third amplifier and a third capacitor, to receive the third pattern signals in parallel. 
     For example, the pattern signal generator  140  may generate a first pattern signal based on a pattern of one I-Q binary data pair and a pattern of one inverted I-Q binary data pair, a second pattern signal having a first phase difference from the first pattern signal, and a third pattern signal having a second phase difference from the first pattern signal. The first SC-DAC circuit  162   a  may receive the first pattern signal through one of a plurality of first paths, the second SC-DAC circuit  164   a  may receive the second pattern signal through one of a plurality of second paths, and the third SC-DAC circuit  166   a  may receive the third pattern signal through one of a plurality of third paths. In an example embodiment, the equivalent capacitance of the second SC-DAC circuit  164   a  may be “m” times the equivalent capacitance of each of the first and third SC-DAC circuits  162   a  and  166   a , where “m” is a real number of at least 1. 
     As described above, an inverted-phase component for removing a p-th harmonic component that may produce an intermodulation distortion component may be generated using the first through third SC-DAC circuits  162   a  through  166   a , which respectively receive first through third pattern signals respectively having different phases and each of which has a desired (or alternatively, predetermined) equivalent capacitance. 
     In an example embodiment, when the second and third SC-DAC circuits  164   a  and  166   a  are configured to generate an inverted-phase component for removing a third harmonic component, the phase of a first pattern signal may lead the phase of a second pattern signal by 45 degrees and lead the phase of a third pattern signal by 90 degrees, and the capacitance of the second SC-DAC circuit  164   a  may be √{square root over (2)} times the equivalent capacitance of each of the first and third SC-DAC circuits  162   a  and  166   a . Because it may be difficult to implement the capacitance of the second SC-DAC circuit  164   a  to be exactly √{square root over (2)} times the equivalent capacitance of each of the first and third SC-DAC circuits  162   a  and  166   a  in real processes, the capacitance of the second SC-DAC circuit  164   a  may be 1.4 times the equivalent capacitance of each of the first and third SC-DAC circuits  162   a  and  166   a , wherein 1.4 is approximately √{square root over (2)}. In some example embodiments, to compensate for difficulty in making the capacitance of the second SC-DAC circuit  164   a  to be exactly √{square root over (2)} times the equivalent capacitance of each of the first and third SC-DAC circuits  162   a  and  166   a  in real processes, the voltage regulator  170  may control a supply voltage V DD  such that a first supply voltage V 1  applied to the second SC-DAC circuit  164   a  has a higher level than a second supply voltage V 2  applied to the first and third SC-DAC circuits  162   a  and  166   a . In some example embodiments, the first through third SC-DAC circuits  162   a  through  166   a  may have the same equivalent capacitance, and the first supply voltage V 1  and second supply voltage V 2  may be regulated to have different levels (e.g., the first supply voltage V 1  may be √{square root over (2)} times the second supply voltage V 2 ), so that the first through third SC-DAC circuits  162   a  through  166   a  generate an inverted-phase component for removing a third harmonic component. 
     The first SC-DAC circuit  162   a  may generate a first RF signal from a plurality of first pattern signals, the second SC-DAC circuit  164   a  may generate a second RF signal from a plurality of second pattern signals, and the third SC-DAC circuit  166   a  may generate a third RF signal from a plurality of third pattern signals. The first through third RF signals may be summed and provided as an RF analog signal (e.g., an RF output signal) RF OUT  to the front-end circuit  180  through a first output terminal  167   a.    
     The fourth SC-DAC circuit  162   b  may generate a fourth RF signal from a plurality of first inverted pattern signals, the fifth SC-DAC circuit  164   b  may generate a fifth RF signal from a plurality of second inverted pattern signals, and the sixth SC-DAC circuit  166   b  may generate a sixth RF signal from a plurality of third inverted pattern signals. The fourth through sixth RF signals may be summed and provided as an inverted RF analog signal (e.g., an inverted RF output signal) RFB OUT  to the front-end circuit  180  through a second output terminal  167   b.    
     The front-end circuit  180  may include a balun  182 , which is connected to the first and second output terminals  167   a  and  167   b , and a PA  184 . The balun  182  may receive and perform a certain conversion operation on the RF analog signal RF OUT  and the inverted RF analog signal RFB OUT . Through the certain conversion operation of the balun  182 , a first intermodulation distortion component, which is produced by a second harmonic component (or an even harmonic component) at the time of non-linear amplification of the RF analog signal RF OUT , may be added to a second intermodulation distortion component, which is produced by a second harmonic component (or an even harmonic component) at the time of non-linear amplification of the inverted RF analog signal RFB OUT , and thus the first intermodulation distortion component may be removed (e.g., cancelled out). 
     The PA  184  may amplify an RF analog signal, from which a third harmonic component (or an odd harmonic component) has been removed by the SC-DAC  160  and a second harmonic component (or an even harmonic component) has been removed by the balun  182 , thereby generating an RF output signal in which an intermodulation distortion component caused by the harmonic components has been reduced or minimized. The RF output signal of the front-end circuit  180  may be transmitted to a base station or another wireless communication device through the antenna  190 . 
       FIGS.  3 A through  3 D  are graphs for describing the operation of the SC-DAC  160  in  FIG.  2   , according to an example embodiment. In  FIGS.  3 A through  3 D , the I binary data I and the Q binary data Q is expressed by vectors. It is assumed that the I binary data I having a value of “1” or “0” has a phase of 0 degrees or 180 degrees, and the Q binary data Q having a value of “1” or “0” has a phase of 90 degrees or 270 degrees. 
     Referring to  FIG.  3 A , when the SC-DAC  160  receives a pattern signal, which includes the I binary data I corresponding to a phase of 0 degrees and the Q binary data Q corresponding to a phase of 90 degrees, third harmonic sub components 3 rd _HD_sub may be generated during non-linear amplification. A third harmonic sub component 3 rd _HD_sub may have a phase of 0 degrees, which is three times the phase of 0 degrees, and another third harmonic sub component 3 rd _HD_sub may have a phase of 270 degrees, which is three times a phase of 90 degrees, so that a third harmonic component 3 rd _HD having a magnitude, which is √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub, and a phase of 315 degrees may be generated. Accordingly, the SC-DAC  160  needs to generate an inverted-phase component IPC, which has a magnitude √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub and a phase of 135 degrees, to remove the third harmonic component 3 rd _HD. For example, the SC-DAC  160  may generate a signal, which has a magnitude √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub and a phase of 45 degrees, and the inverted-phase component IPC having a phase of 135 degrees, which is three times the phase of 45 degrees, may be generated from the signal. 
     Referring to  FIG.  3 B , when the SC-DAC  160  receives a pattern signal, which includes the I binary data I corresponding to a phase of 180 degrees and the Q binary data Q corresponding to a phase of 90 degrees, the third harmonic sub components 3 rd _HD_sub may be generated during non-linear amplification. A third harmonic sub component 3 rd _HD_sub may have a phase of 180 degrees, which is three times the phase of 180 degrees, and another third harmonic sub component 3 rd _HD_sub may have a phase of 270 degrees, which is three times a phase of 90 degrees, so that the third harmonic component 3 rd _HD having a magnitude, which is √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub, and a phase of 225 degrees may be generated. Accordingly, the SC-DAC  160  needs to generate the inverted-phase component IPC, which has a magnitude √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub and a phase of 45 degrees, to remove the third harmonic component 3 rd _HD. For example, the SC-DAC  160  may generate a signal, which has a magnitude √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub and a phase of 135 degrees, and the inverted-phase component IPC having a phase of 45 degrees, which is three times the phase of 135 degrees, may be generated from the signal. 
     Referring to  FIG.  3 C , when the SC-DAC  160  receives a pattern signal, which includes the I binary data I corresponding to a phase of 180 degrees and the Q binary data Q corresponding to a phase of 270 degrees, the third harmonic sub components 3 rd _HD_sub may be generated during non-linear amplification. A third harmonic sub component 3 rd _HD_sub may have a phase of 180 degrees, which is three times the phase of 180 degrees, and another third harmonic sub component 3 rd _HD_sub may have a phase of 90 degrees, which is three times a phase of 270 degrees, so that the third harmonic component 3 rd _HD having a magnitude, which is √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub, and a phase of 135 degrees may be generated. Accordingly, the SC-DAC  160  needs to generate the inverted-phase component IPC, which has a magnitude √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub and a phase of 315 degrees, to remove the third harmonic component 3 rd _HD. For example, the SC-DAC  160  may generate a signal, which has a magnitude √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub and a phase of 225 degrees, and the inverted-phase component IPC having a phase of 315 degrees, which is three times the phase of 225 degrees, may be generated from the signal. 
     Referring to  FIG.  3 D , when the SC-DAC  160  receives a pattern signal, which includes the I binary data I corresponding to a phase of 0 degrees and the Q binary data Q corresponding to a phase of 270 degrees, the third harmonic sub components 3 rd _HD_sub may be generated during non-linear amplification. A third harmonic sub component 3 rd _HD_sub may have a phase of 0 degrees, which is three times the phase of 0 degrees, and another third harmonic sub component 3 rd _HD_sub may have a phase of 90 degrees, which is three times a phase of 270 degrees, so that the third harmonic component 3 rd _HD having a magnitude, which is √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub, and a phase of 45 degrees may be generated. Accordingly, the SC-DAC  160  needs to generate the inverted-phase component IPC, which has a magnitude √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub and a phase of 225 degrees, to remove the third harmonic component 3 rd _HD. For example, the SC-DAC  160  may generate a signal, which has a magnitude √{square root over (2)} times the magnitude of the third harmonic sub components 3 rd _HD_sub and a phase of 315 degrees, and the inverted-phase component IPC having a phase of 225 degrees, which is three times the phase of 315 degrees, may be generated from the signal. 
       FIG.  4    is a block diagram of a pattern signal generator  140 _ 1  according to an example embodiment.  FIGS.  5 A through  5 C  are timing diagrams for describing operations of the pattern signal generator  140 _ 1  of  FIG.  4   . 
     Referring to  FIG.  4   , the pattern signal generator  140 _ 1  may include a clock signal generation circuit  142 _ 1  and a signal multiplication circuit  144 _ 1 . The clock signal generation circuit  142 _ 1  may generate a plurality of clock signals CLKs, which have a target frequency, a target duty ratio, and different phases from each other, by dividing the frequency signal F_S having a certain frequency. In an example embodiment, the clock signal generation circuit  142 _ 1  may generate the clock signals CLKs, which have phases of 0, 45, 90, 135, 180, 225, 270, and 315 degrees, respectively, and a duty ratio of 1/4, as shown in  FIGS.  5 A through  5 C . The target frequency of the clock signals CLKs may be adjusted according to an RF band, and the clock signals CLKs may be used to up-convert a frequency of a baseband digital signal into an RF band analog signal. 
     The signal multiplication circuit  144 _ 1  may receive I binary data I[ 1 ] through I[k], Q binary data Q[ 1 ] through Q[k], inverted I binary data IB[ 1 ] through IB[k], and inverted Q binary data Q[ 1 ] through Q[k] bit by bit in parallel. The signal multiplication circuit  144 _ 1  may multiply the clock signals CLKs by the I binary data I[ 1 ] through I[k], the Q binary data Q[ 1 ] through Q[k], the inverted I binary data IB [ 1 ] through IB[k], and the inverted Q binary data Q[ 1 ] through Q[k], thereby generating a plurality of first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ], a plurality of second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ], and a plurality of third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ] by bits. As described above, the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ] may be input to the first SC-DAC circuit  162   a  in  FIG.  2   , the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ] may be input to the second SC-DAC circuit  164   a  in  FIG.  2   , and the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ] may be input to the third SC-DAC circuit  166   a  in  FIG.  2   . 
     Referring further to  FIG.  5 A , the signal multiplication circuit  144 _ 1  may multiply a clock signal CLK(0°) having a phase of 0 degrees by the I binary data I[k], multiply a clock signal CLK(90°) having a phase of 90 degrees by the Q binary data Q[k], multiply a clock signal CLK(180°) having a phase of 180 degrees by the inverted I binary data IB[k], and multiply a clock signal CLK(270°) having a phase of 270 degrees by the inverted Q binary data QB[k], thereby generating multiplication result signals MR_S 1  through MR_S 4 . The signal multiplication circuit  144 _ 1  may generate the first pattern signal PT_S 1 [ k ] by summing the multiplication result signals MR_S 1  through MR_S 4 . 
     When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB[k], and the inverted Q binary data QB[k], which have values “1”, “1”, “0”, and “0”, respectively, in a first interval INT 1 , the signal multiplication circuit  144 _ 1  may generate the first pattern signal PT_S 1 [ k ] having a first pattern PT_ 11 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB[k], and the inverted Q binary data QB[k], which have values “1”, “0”, “0”, and “1”, respectively, in a second interval INT 2 , the signal multiplication circuit  144 _ 1  may generate the first pattern signal PT_S 1 [ k ] having a second pattern PT_ 12 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB [k], and the inverted Q binary data QB[k], which have values “0”, “0”, “1”, and “1”, respectively, in a third interval INT 3 , the signal multiplication circuit  144 _ 1  may generate the first pattern signal PT_S 1 [ k ] having a third pattern PT_ 13 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB [k], and the inverted Q binary data QB[k], which have values “0”, “1”, “1”, and “0”, respectively, in a fourth interval INT 4 , the signal multiplication circuit  144 _ 1  may generate the first pattern signal PT_S 1 [ k ] having a fourth pattern PT_ 14 . 
     Referring further to  FIG.  5 B , the signal multiplication circuit  144 _ 1  may multiply a clock signal CLK(45°) having a phase of 45 degrees by the I binary data I[k], multiply a clock signal CLK(135°) having a phase of 135 degrees by the Q binary data Q[k], multiply a clock signal CLK(225°) having a phase of 225 degrees by the inverted I binary data IB [k], and multiply a clock signal CLK(315°) having a phase of 315 degrees by the inverted Q binary data QB [k], thereby generating the multiplication result signals MR_S 1  through MR_S 4 . The signal multiplication circuit  144 _ 1  may generate the second pattern signal PT_S 2 [ k ] by summing the multiplication result signals MR_S 1  through MR_S 4 . 
     When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB[k], and the inverted Q binary data QB[k], which have values “1”, “1”, “0”, and “0”, respectively, in the first interval INT 1 , the signal multiplication circuit  144 _ 1  may generate the second pattern signal PT_S 2 [ k ] having a first pattern PT_ 21 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB[k], and the inverted Q binary data QB[k], which have values “1”, “0”, “0”, and “1”, respectively, in the second interval INT 2 , the signal multiplication circuit  144 _ 1  may generate the second pattern signal PT_S 2 [ k ] having a second pattern PT_ 22 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB [k], and the inverted Q binary data QB[k], which have values “0”, “0”, “1”, and “1”, respectively, in the third interval INT 3 , the signal multiplication circuit  144 _ 1  may generate the second pattern signal PT_S 2 [ k ] having a third pattern PT_ 23 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB [k], and the inverted Q binary data QB[k], which have values “0”, “1”, “1”, and “0”, respectively, in the fourth interval INT 4 , the signal multiplication circuit  144 _ 1  may generate the second pattern signal PT_S 2 [ k ] having a fourth pattern PT_ 24 . 
     Referring further to  FIG.  5 C , the signal multiplication circuit  144 _ 1  may multiply the clock signal CLK(90°) having a phase of 90 degrees by the I binary data I[k], multiply the clock signal CLK(180°) having a phase of 180 degrees by the Q binary data Q[k], multiply the clock signal CLK(270°) having a phase of 270 degrees by the inverted I binary data IB [k], and multiply the clock signal CLK(0°) having a phase of 0 degrees by the inverted Q binary data QB [k], thereby generating the multiplication result signals MR_S 1  through MR_S 4 . The signal multiplication circuit  144 _ 1  may generate the third pattern signal PT_S 3 [ k ] by summing the multiplication result signals MR_S 1  through MR_S 4 . 
     When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB[k], and the inverted Q binary data QB[k], which have values “1”, “1”, “0”, and “0”, respectively, in the first interval INT 1 , the signal multiplication circuit  144 _ 1  may generate the third pattern signal PT_S 3 [ k ] having a first pattern PT_ 31 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB[k], and the inverted Q binary data QB[k], which have values “1”, “0”, “0”, and “1”, respectively, in the second interval INT 2 , the signal multiplication circuit  144 _ 1  may generate the third pattern signal PT_S 3 [ k ] having a second pattern PT_ 32 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB[k], and the inverted Q binary data QB[k], which have values “0”, “0”, “1”, and “1”, respectively, in the third interval INT 3 , the signal multiplication circuit  144 _ 1  may generate the third pattern signal PT_S 3 [ k ] having a third pattern PT_ 33 . When the signal multiplication circuit  144 _ 1  receives the I binary data I[k], the Q binary data Q[k], the inverted I binary data IB [k], and the inverted Q binary data QB[k], which have values “0”, “1”, “1”, and “0”, respectively, in the fourth interval INT 4 , the signal multiplication circuit  144 _ 1  may generate the third pattern signal PT_S 3 [ k ] having a fourth pattern PT_ 34 . 
     Thus, the signal multiplication circuit  144 _ 1  may generate the first pattern signal PT_S 1 [ k ], the second pattern signal PT_S 2 [ k ], a phase of which lags the phase of the first pattern signal PT_S 1 [ k ] by 45 degrees, and the third pattern signal PT_S 3 [ k ], a phase of which lags the phase of the first pattern signal PT_S 1 [ k ] by 90 degrees. 
     According to the example embodiment, the inverted I binary data IB [k] and the inverted Q binary data QB [k] (or an inverted I-Q binary data pair) is used in addition to the I binary data I[k] and the Q binary data Q[k] (or an I-Q binary data pair) when the signal multiplication circuit  144 _ 1  generates a pattern signal to enable, even when the I binary data I[k] or the Q binary data Q[k] has a value “0”, the orientation thereof to be represented by a phase. Thus, according to an example embodiment, a digital RF transmitter may generate an inverted-phase component having an opposite phase to a third harmonic component (or an odd harmonic component). 
       FIG.  6    is a circuit diagram of first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  according to an example embodiment. 
     The first SC-DAC circuit  162   a _ 1  may include a plurality of first amplifiers AMP 1   a  through AMPka and a plurality of first capacitors C 1   a  through Cka. Each of the first amplifiers AMP 1   a  through AMPka and each of the first capacitors C 1   a  through Cka may form a path, through which a corresponding one of the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ] passes. In other words, the first SC-DAC circuit  162   a _ 1  may include a plurality of paths, through which the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ] pass, respectively, and may output a first RF signal RF 1  from the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ]. 
     The second SC-DAC circuit  164   a _ 1  may include a plurality of second amplifiers AMP 1   b  through AMPkb and a plurality of second capacitors C 1   b  through Ckb. Each of the second amplifiers AMP 1   b  through AMPkb and each of the second capacitors C 1   b  through Ckb may form a path, through which a corresponding one of the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ] passes. In other words, the second SC-DAC circuit  164   a _ 1  may include a plurality of paths, through which the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ] pass, respectively, and may output a second RF signal RF 2  from the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ]. 
     The third SC-DAC circuit  166   a _ 1  may include a plurality of third amplifiers AMP 1   c  through AMPkc and a plurality of third capacitors C 1   c  through Ckc. Each of the third amplifiers AMP 1   c  through AMPkc and each of the third capacitors C 1   c  through Ckc may form a path, through which a corresponding one of the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ] passes. In other words, the third SC-DAC circuit  166   a _ 1  may include a plurality of paths, through which the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ] pass, respectively, and may output a third RF signal RF 3  from the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ]. The first through third RF signals RF 1  through RF 3  may be summed and output as the RF analog signal RF OUT  through a first output terminal  167   a _ 1 . 
     In an example embodiment, the capacitance of the second capacitors C 1   b  through Ckb may be “m” times the capacitance of the first and third capacitors C 1   a  through Cka and C 1   c  through Ckc, where “m” is a real number of at least 1. For example, when “m” is V 2 , the capacitance of the capacitor Ckb of the second SC-DAC circuit  164   a _ 1  may be √{square root over (2)} times the capacitance of the capacitor Cka of the first SC-DAC circuit  162   a _ 1  and the capacitor Ckc of the third SC-DAC circuit  166   a _ 1 . In other words, the equivalent capacitance of the second SC-DAC circuit  164   a _ 1  may be √{square root over (2)} times the equivalent capacitance of each of the first and third SC-DAC circuits  162   a _ 1  and  166   a _ 1 . The reason why the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  have such capacitor configuration will be described in detail with reference to  FIG.  8    below. 
     In  FIG.  6   , each of the first through third capacitors C 1   a  through Cka, C 1   b  through Ckb, and C 1   c  through Ckc may include a plurality of unit capacitors. A unit capacitor may be an element that has a certain capacitance. In an example embodiment, the number of unit capacitors forming the capacitor Ckb of the second SC-DAC circuit  164   a _ 1  may be greater than the number of unit capacitors forming each of the capacitor Cka of the first SC-DAC circuit  162   a _ 1  and the capacitor Ckc of the third SC-DAC circuit  166   a _ 1 . For example, the number of unit capacitors forming the capacitor Ckb of the second SC-DAC circuit  164   a _ 1  may be seven, and the number of unit capacitors forming each of the capacitor Cka of the first SC-DAC circuit  162   a _ 1  and the capacitor Ckc of the third SC-DAC circuit  166   a _ 1  may be five. Through this configuration, the capacitance of the second capacitors C 1   b  through Ckb may be √{square root over (2)} times the capacitance of the first and third capacitors C 1   a  through Cka and C 1   c  through Ckc. 
     The phase of the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ] input to the first SC-DAC circuit  162   a _ 1  may lead the phase of the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ] input to the second SC-DAC circuit  164   a _ 1  by 45 degrees and the phase of the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ] input to the third SC-DAC circuit  166   a _ 1  by 90 degrees. 
     The first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  illustrated in  FIG.  6    are just examples and may be variously embodied so as to convert a digital signal into an analog signal, without being limited to the examples. 
       FIG.  7    is a diagram for describing a method of determining the magnitude of the first RF signal RF 1  in a first SC-DAC circuit  162   a _ 2 , according to an example embodiment. The descriptions below may also applied to other SC-DAC circuits. The first SC-DAC circuit  162   a _ 2  of  FIG.  7    is just an example and may be variously embodied, without being limited to the example. 
     Referring to  FIG.  7   , the first SC-DAC circuit  162   a _ 2  may include a plurality of amplifiers AMP 1   a  through AMP 3   a  and a plurality of capacitors C 1   a  through C 3   a . Each of first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ 3 ] may pass through a path, which includes one of the amplifiers AMP 1   a  through AMP 3   a  and one of the capacitors C 1   a  through C 3   a . The level of the first RF signal RF 1  may be determined to be one of first through fourth levels LV 1  through LV 4  according to the pattern of each of the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ 3 ]. In other words, different patterns of the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ 3 ] may be represented by different magnitudes of the first RF signal RF 1 , respectively, through the first SC-DAC circuit  162   a _ 2 . In this manner, a digital signal may be converted into an analog signal. As described above with reference to  FIG.  6   , each of the capacitors C 1   a  through C 3   a  may include a plurality of unit capacitors. 
       FIG.  8    is a diagram for describing equivalent capacitors Ca EQ , Cb EQ , and Cc EQ  of the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  in  FIG.  6   . 
     Referring to  FIG.  8   , the output of each of the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  may be connected to the first output terminal  167   a _ 1 , and a capacitance ratio among the equivalent capacitors Ca EQ , Cb EQ , and Cc EQ  of the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  may be 1:m:1. Accordingly, a magnitude ratio among the first through third RF signals RF 1  through RF 3  respectively corresponding to first through third pattern signals PT_S 1 , PT_S 2 , and PT_S 3  having the same pattern may be 1:m:1. As described above, each of the equivalent capacitors Ca EQ , Cb EQ , and Cc EQ  may include a plurality of unit capacitors. 
     The second RF signal RF 2  output from the second SC-DAC circuit  164   a _ 2  may include a frequency component corresponding to an inverted-phase component for removing a third harmonic component (or an odd harmonic component). The magnitude of the second RF signal RF 2  may be “m” times the magnitude of each of the first and third RF signals RF 1  and RF 3 . In an example embodiment, “m” may be √{square root over (2)} or a real number that approximates √{square root over (2)}. 
       FIG.  9    is a diagram for describing a supply voltage applied to each of the first through third amplifiers AMP 1   a  through AMPka, AMP 1   b  through AMPkb, and AMP 1   c  through AMPkc of the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  in  FIG.  6   . 
     Referring to  FIG.  9   , a voltage regulator  170 _ 1  may generate the first supply voltage V 1  and the second supply voltage V 2  from a certain supply voltage such that the second supply voltage V 2  has a different level from the first supply voltage V 1 . For example, the first supply voltage V 1  may be greater than the second supply voltage V 2 , and the voltage regulator  170 _ 1  may apply the first supply voltage V 1  to the second amplifiers AMP 1   b  through AMPkb and the second supply voltage V 2  to the first amplifiers AMP 1   a  through AMPka and the third amplifiers AMP 1   c  through AMPkc. Accordingly, the second amplifiers AMP 1   b  through AMPkb may amplify a received signal to a greater extent than the first and third amplifiers AMP 1   a  through AMPka and AMP 1   c  through AMPkc. 
     As described above, it is difficult to implement the capacitance ratio among the equivalent capacitors Ca EQ , Cb EQ , and Cc EQ  of the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  to be 1:√{square root over (2)}:1 in real processes, as illustrated in the example embodiment of  FIG.  8   . Such issues in the real processes may be solved through the example embodiment of  FIG.  9   , which generates an inverted-phase component having the same magnitude as a third harmonic component. 
       FIG.  10    is a diagram for describing first through fourth patterns PT_ 1  through PT_ 4  of the RF analog signal RF OUT  generated by summing the first through third RF signals RF 1  through RF 3  in  FIG.  6   . For clear understanding, the case where one first pattern signal, e.g., the first pattern signal PT_S 1 [ k ], among k-bit pattern signals and the second and third pattern signals PT_S 2 [ k ] and PT_S 3  [k] corresponding to the first pattern signal PT_S 1 [ k ] are input to the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1 , respectively, will be described with reference to  FIG.  10   . 
     Referring to  FIGS.  6  and  10   , when the pattern of an I-Q binary data pair is “1,1”, the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  may output the first through third RF signals RF 1  through RF 3 , respectively, and the RF analog signal RF OUT  having the first pattern PT_ 1  may be output through the first output terminal  167   a _ 1 . When the pattern of an I-Q binary data pair is “1,0”, the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  may output the first through third RF signals RF 1  through RF 3 , respectively, and the RF analog signal RF OUT  having the second pattern PT_ 2  may be output through the first output terminal  167   a _ 1 . When the pattern of an I-Q binary data pair is “0,0”, the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  may output the first through third RF signals RF 1  through RF 3 , respectively, and the RF analog signal RF OUT  having the third pattern PT_ 3  may be output through the first output terminal  167   a _ 1 . When the pattern of an I-Q binary data pair is “0,1”, the first through third SC-DAC circuits  162   a _ 1 ,  164   a _ 1 , and  166   a _ 1  may output the first through third RF signals RF 1  through RF 3 , respectively, and the RF analog signal RF OUT  having the fourth pattern PT_ 4  may be output through the first output terminal  167   a _ 1 . 
     In an example embodiment, the phase of the first RF signal RF 1  may lead the phase of the second RF signal RF 2  by 45 degrees and lead the phase of the third RF signal RF 3  by 90 degrees. The magnitude of the second RF signal RF 2  may be √{square root over (2)} times the magnitude of each of the first RF signal RF 1  and the third RF signal RF 3 . 
     As shown in  FIG.  10   , the first through fourth patterns PT_ 1  through PT_ 4  of the RF analog signal RF OUT  may be determined in advance according to I-Q binary data pairs, and accordingly, the RF analog signal RF OUT  corresponding to each I-Q binary data pair may be generated by generating in advance a plurality of clock signals having different duty ratios and combining the clock signals according to the I-Q binary data pair. This will be described with reference to  FIG.  11   . 
       FIG.  11    is a block diagram of a pattern signal generator  140 _ 2  according to an example embodiment. 
     Referring to  FIGS.  10  and  11   , the pattern signal generator  140 _ 2  may include a clock signal generation circuit  142 _ 2 , a pattern signal output circuit  144 _ 2 , and a multiplexer  144 _ 5 . The clock signal generation circuit  142 _ 2  may generate the clock signals CLKs, which have a target frequency (or a carrier frequency), a target duty ratio, and different phases from each other, by dividing the frequency signal F_S having a certain frequency. The pattern signal output circuit  144 _ 2  may be configured to generate first through third pattern signals by using at least one of the clock signals CLKs. 
     The pattern signal output circuit  144 _ 2  may include a control circuit  144 _ 3  and first through fourth signal generation circuits  144 _ 4   a  through  144 _ 4   d . Each of the first through fourth signal generation circuits  144 _ 4   a  through  144 _ 4   d  may output signals forming one of the first through fourth patterns PT_ 1  through PT_ 4  in  FIG.  10   . For example, the first signal generation circuit  144 _ 4   a  may generate component signals forming the first pattern PT_ 1 , the second signal generation circuit  144 _ 4   b  may generate component signals forming the second pattern PT_ 2 , the third signal generation circuit  144 _ 4   c  may generate component signals forming the third pattern PT_ 3 , and the fourth signal generation circuit  144 _ 4   d  may generate component signals forming the fourth pattern PT_ 4 . 
     The control circuit  144 _ 3  may receive the I binary data I[ 1 ] through I[k] and the Q binary data Q[ 1 ] through Q[k] bit by bit in parallel, and may control the first through fourth signal generation circuits  144 _ 4   a  through  144 _ 4   d  and the multiplexer  144 _ 5  such that component signals, which form a pattern corresponding to an I-Q binary data pair among the first through fourth patterns PT_ 1  through PT_ 4 , are output as the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ], the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ], and the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ]. For example, the control circuit  144 _ 3  may control activation of the first through fourth signal generation circuits  144 _ 4   a  through  144 _ 4   d , and may control the multiplexer  144 _ 5  such that each of component signals generated from each of the first through fourth signal generation circuits  144 _ 4   a  through  144 _ 4   d  is output to an SC-DAC circuit allocated for each component signal. In some example embodiments, all of the first through fourth signal generation circuits  144 _ 4   a  through  144 _ 4   d  may be activated to generate component signals in advance, and the control circuit  144 _ 3  may control the multiplexer  144 _ 5  to output each of the component signals to an SC-DAC circuit allocated therefor. 
     For example, when the I binary data I[k] and the Q binary data Q[k], which correspond to a bit index “k”, is “1,1”, the first signal generation circuit  144 _ 4   a  may output a first component signal having a first duty ratio as the first pattern signal PT_S 1 [ k ], a second component signal having a second duty ratio as the second pattern signal PT_S 2 [ k ], and a third component signal having a third duty ratio as the third pattern signal PT_S 3 [ k ]. In an example embodiment, the first duty ratio may be 1/4, the second duty ratio may be 1/2, and the third duty ratio may be 3/4. 
     In another example, components signals may have different phases. Accordingly, when a set of the I binary data I[k] and the Q binary data Q[k], which corresponds to the bit index “k”, is “1,1”, the first through third component signals for generating the first pattern PT_ 1  may be generated by the first signal generation circuit  144 _ 4   a . When the I binary data I[k_ 1 ] and the Q binary data Q[k_ 1 ], which correspond to a bit index k−1, is “1,0”, fourth through sixth component signals for generating the second pattern PT_ 2  may be generated by the second signal generation circuit  144 _ 4   b . When the I binary data I[k_ 2 ] and the Q binary data Q[k_ 2 ], which correspond to bit index k_ 2 , is “0,0”, seventh through ninth component signals for generating the third pattern PT_ 3  may be generated by the third signal generation circuit  144 _ 4   c . When the I binary data I[k_ 3 ] and the Q binary data Q[k_ 3 ], which correspond to a bit index k_ 3 , is “0,1”, tenth through twelfth component signals for generating the fourth pattern PT_ 4  may be generated by the fourth signal generation circuit  144 _ 4   d.    
     As described above, through the configuration of the pattern signal generator  140 _ 2  that outputs component signals, which have been determined in advance according to the patterns of I-Q binary data pairs, to an SC-DAC so that the RF analog signal RF OUT  in  FIG.  10    is output, communication performance may be increased and a structure may be simplified. 
       FIG.  12 A  is a block diagram of a first signal generation circuit  144 _ 4   a _ 1  corresponding to the first signal generation circuit  144 _ 4   a  in  FIG.  11   ,  FIG.  12 B  is a diagram illustrating an RF analog signal generated by the first signal generation circuit  144 _ 4   a _ 1  of  FIG.  12 A , and  FIG.  12 C  is a diagram of an example implementation of first through third component signal generation logics  144 _ 41   a ,  144 _ 42   a , and  144 _ 43   a  in  FIG.  12 A . 
     Referring to  FIG.  12 A , the first signal generation circuit  144 _ 4   a _ 1  may include the first through third component signal generation logics  144 _ 41   a  through  144 _ 43   a . The first through third component signal generation logics  144 _ 41   a  through  144 _ 43   a  may output first through third component signals CC 11 , CC 21 , and CC 31  forming the first pattern PT_ 1  in  FIG.  10   , respectively. An output end of each of the first through third component signal generation logics  144 _ 41   a  through  144 _ 43   a  may be connected to a multiplexer  144 _ 3 _ 1 . 
     The first component signal CC 11  may be selected and output by the multiplexer  144 _ 3 _ 1  as a first pattern signal corresponding to a pattern of an I-Q binary data pair among the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ], based on a control signal of the control circuit  144 _ 3  in  FIG.  11   , wherein the control signal corresponds to the pattern of an I-Q binary data pair. The second component signal CC 21  may be selected and output by the multiplexer  144 _ 3 _ 1  as a second pattern signal corresponding to a pattern of an I-Q binary data pair among the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ], based on the control signal. The third component signal CC 31  may be selected and output by the multiplexer  144 _ 3 _ 1  as a third pattern signal corresponding to a pattern of an I-Q binary data pair among the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ], based on the control signal. In other words, the multiplexer  144 _ 5  may be configured to selectively connect at least one of the first through fourth signal generation circuits  144 _ 4   a  through  144 _ 4   d  to the SC-DAC  160  based on the pattern of the I-Q binary data pair. 
     Referring further to  FIG.  12 B , the first component signal CC 11  may have a duty ratio of 1/4, the second component signal CC 21  may have a duty ratio of 1/2, and the third component signal CC 31  may have a duty ratio of 3/4. The first through third component signals CC 11  through CC 31  may have the same frequency (e.g., the carrier frequency of an RF analog signal). Each of the first through third component signals CC 11  through CC 31  may have a certain phase difference from one another, as shown in  FIG.  12 B , so that the RF analog signal RF OUT  may have the first pattern PT_ 1  in  FIG.  10   . In an example embodiment, the magnitude of the second RF signal RF 2 , which is generated when the second component signal CC 21  has passed through the second SC-DAC circuit  164   a _ 1  in  FIG.  6   , may be √{square root over (2)} times the magnitude of each of the first RF signal RF 1 , which is generated when the first component signal CC 11  has passed through the first SC-DAC circuit  162   a _ 1  in  FIG.  6   , and the third RF signal RF 3 , which is generated when the third component signal CC 31  has passed through the third SC-DAC circuit  166   a _ 1  in  FIG.  6   . 
     Referring further to  FIG.  12 C , the first component signal generation logic  144 _ 41   a  may include a first inverter IVT 1  and a second inverter IVT 2 . The clock signal CLK(45°) having a duty ratio of 1/4 and a phase of 45 degrees is input to the first inverter IVT 1 . The second component signal generation logic  144 _ 42   a  may include a first OR logic OR1, a third inverter IVT 3 , and a fourth inverter IVT 4 . The clock signal CLK(0°) having a duty ratio of 1/4 and a phase of 0 degrees and the clock signal CLK(90°) having a duty ratio of 1/4 and a phase of 90 degrees are input to the first OR logic OR1. The third component signal generation logic  144 _ 43   a  may include a fifth inverter IVT 5 , a sixth inverter IVT 6 , and a seventh inverter IVT 7 . The clock signal CLK(225°) having a duty ratio of 1/4 and a phase of 225 degrees is input to the fifth inverter IVT 5 . The first through third component signal generation logics  144 _ 41   a  through  144 _ 43   a  may respectively generate the first through third component signals CC 11  through CC 31 . 
       FIG.  13 A  is a block diagram of a second signal generation circuit  144 _ 4   b _ 1  corresponding to the second signal generation circuit  144 _ 4   b  in  FIG.  11   ,  FIG.  13 B  is a diagram illustrating an RF analog signal generated by the second signal generation circuit  144 _ 4   b _ 1  of  FIG.  13 A , and  FIG.  13 C  is a diagram of an example implementation of fourth through sixth component signal generation logics  144 _ 41   b ,  144 _ 42   b , and  144 _ 43   b  in  FIG.  13 A . 
     Referring to  FIG.  13 A , the second signal generation circuit  144 _ 4   b _ 1  may include the fourth through sixth component signal generation logics  144 _ 41   b  through  144 _ 43   b . The fourth through sixth component signal generation logics  144 _ 41   b  through  144 _ 43   b  may output fourth through sixth component signals CC 12 , CC 22 , and CC 32  forming the second pattern PT_ 2  in  FIG.  10   , respectively. An output end of each of the fourth through sixth component signal generation logics  144 _ 41   b  through  144 _ 43   b  may be connected to the multiplexer  144 _ 3 _ 1 . 
     The fourth component signal CC 12  may be selected and output by the multiplexer  144 _ 3 _ 1  as a first pattern signal corresponding to a pattern of an I-Q binary data pair among the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ], based on a control signal of the control circuit  144 _ 3  in  FIG.  11   , wherein the control signal corresponds to the pattern of an I-Q binary data pair. The fifth component signal CC 22  may be selected and output by the multiplexer  144 _ 3 _ 1  as a second pattern signal corresponding to a pattern of an I-Q binary data pair among the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ], based on the control signal. The sixth component signal CC 32  may be selected and output by the multiplexer  144 _ 3 _ 1  as a third pattern signal corresponding to a pattern of an I-Q binary data pair among the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ], based on the control signal. 
     Referring further to  FIG.  13 B , the fourth component signal CC 12  may have a duty ratio of 1/4, the fifth component signal CC 22  may have a duty ratio of 1/2, and the sixth component signal CC 32  may have a duty ratio of 3/4. The fourth through sixth component signals CC 12  through CC 32  may have the same frequency (e.g., the carrier frequency of an RF analog signal). Each of the fourth through sixth component signals CC 12  through CC 32  may have a certain phase difference from one another, as shown in  FIG.  13 B , so that the RF analog signal RF OUT  may have the second pattern PT_ 2  in  FIG.  10   . In an example embodiment, the magnitude of the second RF signal RF 2 , which is generated when the fifth component signal CC 22  has passed through the second SC-DAC circuit  164   a _ 1  in  FIG.  6   , may be √{square root over (2)} times the magnitude of each of the first RF signal RF 1 , which is generated when the fourth component signal CC 12  has passed through the first SC-DAC circuit  162   a _ 1  in  FIG.  6   , and the third RF signal RF 3 , which is generated when the sixth component signal CC 32  has passed through the third SC-DAC circuit  166   a _ 1  in  FIG.  6   . 
     Referring further to  FIG.  13 C , the fourth component signal generation logic  144 _ 41   b  may include an eighth inverter IVT 8  and a ninth inverter IVT 9 . The clock signal CLK(315°) having a duty ratio of 1/4 and a phase of 315 degrees is input to the eighth inverter IVT 8 . The fifth component signal generation logic  144 _ 42   b  may include a second OR logic OR2, a tenth inverter IVT 10 , and an eleventh inverter IVT 11 . The clock signal CLK(270°) having a duty ratio of 1/4 and a phase of 270 degrees and the clock signal CLK(0°) having a duty ratio of 1/4 and a phase of 0 degrees are input to the second OR logic OR2. The sixth component signal generation logic  144 _ 43   b  may include a twelfth inverter IVT 12 , a 13th inverter IVT 13 , and a 14th inverter IVT 14 . The clock signal CLK(135°) having a duty ratio of 1/4 and a phase of 135 degrees is input to the twelfth inverter IVT 12 . The fourth through sixth component signal generation logics  144 _ 41   b  through  144 _ 43   b  may respectively generate the fourth through sixth component signals CC 12  through CC 32 . 
       FIG.  14 A  is a block diagram of a third signal generation circuit  144 _ 4   c _ 1  corresponding to the third signal generation circuit  144 _ 4   c  in  FIG.  11   ,  FIG.  14 B  is a diagram illustrating an RF analog signal generated by the third signal generation circuit  144 _ 4   c _ 1  of  FIG.  14 A , and  FIG.  14 C  is a diagram of an example implementation of seventh through ninth component signal generation logics  144 _ 41   c ,  144 _ 42   c , and  144 _ 43   c  in  FIG.  14 A . 
     Referring to  FIG.  14 A , the third signal generation circuit  144 _ 4   c _ 1  may include the seven through ninth component signal generation logics  144 _ 41   c  through  144 _ 43   c . The seven through ninth component signal generation logics  144 _ 41   c  through  144 _ 43   c  may output seven through ninth component signals CC 13 , CC 23 , and CC 33  forming the third pattern PT_ 4  in  FIG.  10   , respectively. An output end of each of the seven through ninth component signal generation logics  144 _ 41   c  through  144 _ 43   c  may be connected to the multiplexer  144 _ 3 _ 1 . 
     The seventh component signal CC 13  may be selected and output by the multiplexer  144 _ 3 _ 1  as a first pattern signal corresponding to a pattern of an I-Q binary data pair among the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ], based on a control signal of the control circuit  144 _ 3  in  FIG.  11   , wherein the control signal corresponds to the pattern of an I-Q binary data pair. The eighth component signal CC 23  may be selected and output by the multiplexer  144 _ 3 _ 1  as a second pattern signal corresponding to a pattern of an I-Q binary data pair among the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ], based on the control signal. The ninth component signal CC 33  may be selected and output by the multiplexer  144 _ 3 _ 1  as a third pattern signal corresponding to a pattern of an I-Q binary data pair among the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ], based on the control signal. 
     Referring further to  FIG.  14 B , the seventh component signal CC 13  may have a duty ratio of 3/4, the eighth component signal CC 23  may have a duty ratio of 1/2, and the ninth component signal CC 33  may have a duty ratio of 1/4. The seventh through ninth component signals CC 13  through CC 33  may have the same frequency, i.e., the carrier frequency of an RF analog signal. Each of the seventh through ninth component signals CC 13  through CC 33  may have a certain phase difference from one another, as shown in  FIG.  14 B , so that the RF analog signal RF OUT  may have the third pattern PT_ 3  in  FIG.  10   . In an example embodiment, the magnitude of the second RF signal RF 2 , which is generated when the eighth component signal CC 23  has passed through the second SC-DAC circuit  164   a _ 1  in  FIG.  6   , may be √{square root over (2)} times the magnitude of each of the first RF signal RF 1 , which is generated when the seventh component signal CC 13  has passed through the first SC-DAC circuit  162   a _ 1  in  FIG.  6   , and the third RF signal RF 3 , which is generated when the ninth component signal CC 33  has passed through the third SC-DAC circuit  166   a _ 1  in  FIG.  6   . 
     Referring further to  FIG.  14 C , the seventh component signal generation logic  144 _ 41   c  may include a fifth inverter IVT 15 , to which the clock signal CLK(45°) having a duty ratio of 1/4 and a phase of 45 degrees is input. The eighth component signal generation logic  144 _ 42   c  may include a third OR logic OR3 and a 16th inverter IVT 16 . The clock signal) CLK(0°) having a duty ratio of 1/4 and a phase of 0 degrees and the clock signal CLK(90°) having a duty ratio of 1/4 and a phase of 90 degrees are input to the third OR logic OR3. The ninth component signal generation logic  144 _ 43   c  may include a 17th inverter IVT 17  and an 18th inverter IVT 18 . The clock signal CLK(225°) having a duty ratio of 1/4 and a phase of 225 degrees is input to the 17th inverter IVT 17 . The seven through ninth component signal generation logics  144 _ 41   c  through  144 _ 43   c  may respectively generate the seventh through ninth component signals CC 13  through CC 33 . 
       FIG.  15 A  is a block diagram of a fourth signal generation circuit  144 _ 4   d _ 1  corresponding to the fourth signal generation circuit  144 _ 4   d  in  FIG.  11   ,  FIG.  15 B  is a diagram illustrating an RF analog signal generated by the fourth signal generation circuit  144 _ 4   d _ 1  of  FIG.  15 A , and  FIG.  15 C  is a diagram of an example implementation of tenth through twelfth component signal generation logics  144 _ 41   d ,  144 _ 42   d , and  144 _ 43   d  in  FIG.  15 A . 
     Referring to  FIG.  15 A , the fourth signal generation circuit  144 _ 4   d _ 1  may include the tenth through twelfth component signal generation logics  144 _ 41   d  through  144 _ 43   d . The tenth through twelfth component signal generation logics  144 _ 41   d  through  144 _ 43   d  may respectively output tenth through twelfth component signals CC 14 , CC 24 , and CC 34  forming the fourth pattern PT_ 4  in  FIG.  10   , respectively. An output end of each of the first through third component signal generation logics  144 _ 41   a  through  144 _ 43   a  may be connected to the multiplexer  144 _ 3 _ 1 . 
     The tenth component signal CC 14  may be selected and output by the multiplexer  144 _ 3 _ 1  as a first pattern signal corresponding to a pattern of an I-Q binary data pair among the first pattern signals PT_S 1 [ 1 ] through PT_S 1 [ k ], based on a control signal of the control circuit  144 _ 3  in  FIG.  11   , wherein the control signal corresponds to the pattern of an I-Q binary data pair. The eleventh component signal CC 24  may be selected and output by the multiplexer  144 _ 3 _ 1  as a second pattern signal corresponding to a pattern of an I-Q binary data pair among the second pattern signals PT_S 2 [ 1 ] through PT_S 2 [ k ], based on the control signal. The twelfth component signal CC 34  may be selected and output by the multiplexer  144 _ 3 _ 1  as a third pattern signal corresponding to a pattern of an I-Q binary data pair among the third pattern signals PT_S 3 [ 1 ] through PT_S 3 [ k ], based on the control signal. 
     Referring further to  FIG.  15 B , the tenth component signal CC 14  may have a duty ratio of 3/4, the eleventh component signal CC 24  may have a duty ratio of 1/2, and the twelfth component signal CC 34  may have a duty ratio of 1/4. The tenth through twelfth component signals CC 14  through CC 34  may have the same frequency, i.e., the carrier frequency of an RF analog signal. Each of the tenth through twelfth component signals CC 14  through CC 34  may have a certain phase difference from one another, as shown in  FIG.  15 B , so that the RF analog signal RF OUT  may have the fourth pattern PT_ 4  in  FIG.  10   . In an example embodiment, the magnitude of the second RF signal RF 2 , which is generated when the eleventh component signal CC 24  has passed through the second SC-DAC circuit  164   a _ 1  in  FIG.  6   , may be √{square root over (2)} times the magnitude of each of the first RF signal RF 1 , which is generated when the tenth component signal CC 14  has passed through the first SC-DAC circuit  162   a _ 1  in  FIG.  6   , and the third RF signal RF 3 , which is generated when the twelfth component signal CC 34  has passed through the third SC-DAC circuit  166   a _ 1  in  FIG.  6   . 
     Referring further to  FIG.  15 C , the tenth component signal generation logic  144 _ 41   d  may include a 19th inverter IVT 19 , to which the clock signal CLK(315°) having a duty ratio of 1/4 and a phase of 315 degrees is input. The eleventh component signal generation logic  144 _ 42   d  may include a fourth OR logic OR4 and a 20th inverter IVT 20 . The clock signal CLK(270°) having a duty ratio of 1/4 and a phase of 270 degrees and the clock signal CLK(0°) having a duty ratio of 1/4 and a phase of 0 degrees are input to the fourth OR logic OR4. The twelfth component signal generation logic  144 _ 43   d  may include a 21st inverter IVT 21  and a 22nd inverter IVT 22 . The clock signal CLK(135°) having a duty ratio of 1/4 and a phase of 135 degrees is input to the 21st inverter IVT 21 . The tenth through twelfth component signal generation logics  144 _ 41   d  through  144 _ 43   d  may respectively generate the tenth through twelfth component signals CC 14  through CC 34 . 
       FIG.  16    is a diagram for describing an operation of an SC-DAC  160 _ 3 , according to an example embodiment. 
     Referring to  FIG.  16   , the SC-DAC  160 _ 3  may include first through third SC-DAC circuits  162   a _ 3 ,  164   a _ 3 , and  166   a _ 3 , and output the RF analog signal RF OUT  resulting from summation of first through third RF signals, which are output from the first through third SC-DAC circuits  162   a _ 3 ,  164   a _ 3 , and  166   a _ 3 , respectively. In an example embodiment, the first SC-DAC circuit  162   a _ 3  may output the first RF signal having a rectangular pulse at a duty ratio of 1/4 during a period from a third time t 3  to a fourth time t 4 , the second SC-DAC circuit  164   a _ 3  may output the second RF signal having a rectangular pulse at a duty ratio of 1/2 during a period from a second time t 2  to a fifth time t 5 , and the third SC-DAC circuit  166   a _ 3  may output the third RF signal having a rectangular pulse at a duty ratio of 3/4 during a period from a first time t 1  to a sixth time t 6 , so that the SC-DAC  160 _ 3  may output the RF analog signal RF OUT  that is close to a sine signal. 
       FIG.  17    is a diagram of the configuration of a digital RF transmitter  1000  according to an example embodiment. 
     Referring to  FIG.  17   , the digital RF transmitter  1000  may include a first SC-DAC  1100  and a second SC-DAC  1200 . The first SC-DAC  1100  may include first through third SC-DAC circuits  1110 ,  1120 , and  1130 . Each of the first and third SC-DAC circuits  1110  and  1130  may include 2 A-1  cells each including an amplifier AMP and a capacitor Cap having a capacitance C. The second SC-DAC circuit  1120  may include 2 A-1  cells each including the amplifier AMP and the capacitor Cap having a capacitance 1.4 C. The second SC-DAC  1200  may include fourth through sixth SC-DAC circuits  1210 ,  1220 , and  1230 . The fourth and sixth SC-DAC circuits  1210  and  1230  may include B cells each including the amplifier AMP and the capacitor Cap having the capacitance C. The fifth SC-DAC circuit  1220  may include B cells each including the amplifier AMP and the capacitor Cap having the capacitance 1.4 C. 
     When a modem (not shown) generates a digital signal having “k” bits, the first SC-DAC  1100  may receive thermometer-to-binary data, into which a digital signal having A bits among the “k” bits is converted, in the configuration described above and may perform the conversion operation described above with reference to  FIGS.  1  through  16   . The second SC-DAC  1200  may receive a digital signal having B bits among the “k” bits and perform the conversion operation described above with reference to  FIGS.  1  through  16   . For example, the A bits may correspond to most significant bits (MSBs) among the “k” bits, and the B bits may correspond to least significant bits (LSBs) among the “k” bits. 
     When all SC-DACs of the digital RF transmitter  1000  are configured to receive thermometer-to-binary data, the number of cells including the amplifier AMP and the capacitor Cap rapidly increases, making it difficult to reduce the size of the digital RF transmitter  1000 . Therefore, when only some SC-DACs, e.g., only the first SC-DAC  1100 , in the digital RF transmitter  1000  is configured to receive thermometer-to-binary data as shown in  FIG.  17   , the linearity of operations may be ensured and the size of the digital RF transmitter  1000  may also be reduced. 
       FIG.  18    is a diagram of an example of applying a deactivation of opposite cell (DOC) logic to the wireless communication device  1  of  FIG.  1   . The DOC logic may be applied to the wireless communication device  1  to reduce or minimize the power consumption of the SC-DAC  12 . 
     Referring to  FIGS.  1  and  18   , after N patterns of I-Q binary data pairs are calculated in advance in a digital region in which the modem  30  operates, some cells, each of which includes an amplifier and a capacitor, in the SC-DAC  12  are deactivated and the other cells are activated in an analog region, so that power consumption may be reduced or minimized. 
     In other words, because a pattern of “1,1” and a pattern of “−1, −1” (hereinafter, systematically expressed as ±1) cancel each other when passing through the SC-DAC  12 , the modem  30  may detect in advance the numbers of patterns of “1,1” and patterns of “−1, −1” among the N patterns and thus determine the number of cells to be deactivated. 
     In a first case [CASE1], one pattern of “1,1” remains after patterns among the N patterns cancel each other, and therefore, the modem  30  may activate only one cell of the SC-DAC  12 , and the SC-DAC  12  may output a first RF analog signal RF OUT1 . 
     In a second case [CASE2], five patterns of “−1,1” and two patterns of “1,1” remain after patterns among the N patterns cancel each other, and therefore, the modem  30  may activate seven cells respectively corresponding to the remaining patterns among the cells of the SC-DAC  12 , and the SC-DAC  12  may output a second RF analog signal RF OUT2 . 
       FIG.  19    is a block diagram of a wireless communication device  2000 , according to an example embodiment. 
     Referring to  FIG.  19   , the wireless communication device  2000  may include a digital signal processor  2100 , first through q-th digital RF transmitters  2200 _ 1  through  2200 _ q , first through q-th wideband tunable matching networks  2300 _ 1  through  2300 _ q , a multiplexer  2400 , and a plurality of output terminals, e.g., first through eighth output terminals  2500 _ 1  through  2500 _ 8 . The embodiments described above with reference to  FIGS.  1  through  18    may be applied to the first through q-th digital RF transmitters  2200 _ 1  through  2200 _ q . Each of the first through q-th wideband tunable matching networks  2300 _ 1  through  2300 _ q  may include a balun (not shown) and a PA (not shown), which are suitable for a corresponding one of the first through q-th digital RF transmitters  2200 _ 1  through  2200 _ q  respectively connected to the first through q-th wideband tunable matching networks  2300 _ 1  through  2300 _ q . The first through q-th wideband tunable matching networks  2300 _ 1  through  2300 _ q  may not include a filter that removes an intermodulation distortion component generated by a PA. Among the first through eighth output terminals  2500 _ 1  through  2500 _ 8 , the first through third output terminals  2500 _ 1  through  2500 _ 3  may respectively correspond to first through third low bands LB 1  through LB 3 , the fourth through seventh output terminals  2500 _ 4  through  2500 _ 7  may respectively correspond to first through fourth midbands MB 1  through MB 4 , and the eighth output terminal  2500 _ 8  may correspond to a high band HB. However, the configuration of the wireless communication device  2000  of  FIG.  19    is just an example embodiment, and the embodiments are not limited thereto. A wireless communication device may be implemented to support communications in various frequency bands. 
     In an example embodiment, when operating in a time division duplex mode, the digital signal processor  2100  may select one of the first through q-th digital RF transmitters  2200 _ 1  through  2200 _ q  and provide a baseband digital signal to the selected digital RF transmitter as an IQ signal. Hereinafter, it is assumed that the digital signal processor  2100  has selected the first digital RF transmitter  2200 _ 1 . In some embodiments, the second through q-th digital RF transmitters  2200 _ 2  through  2200 _ q , which have not been selected, and the second through q-th wideband tunable matching networks  2300 _ 2  through  2300 _ q  may be deactivated. 
     The first digital RF transmitter  2200 _ 1  may generate an RF analog signal, which corresponds to an I-Q pattern and a carrier frequency, and an inverted RF analog signal by operating in the same manner as in the embodiments described above to perform frequency up-conversion and digital-to-analog conversion on the baseband digital signal and may output the RF analog signal and the inverted RF analog signal to the first wideband tunable matching network  2300 _ 1  connected thereto. The first wideband tunable matching network  2300 _ 1  may generate an RF output signal using the received RF analog signal and inverted RF analog signal and may output the RF output signal through the multiplexer  2400  to an output terminal corresponding to the frequency band of the RF analog signal among the first through eighth output terminals  2500 _ 1  through  2500 _ 8 . The digital signal processor  2100  may control a switching operation of the multiplexer  2400 . 
     While the inventive concepts have been particularly shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and details may be made with regard to the disclosed example embodiments without departing from the spirit and scope of the following claims.