Patent Publication Number: US-9431164-B2

Title: High efficiency on-chip 3D transformer structure

Description:
RELATED APPLICATION DATA 
     This application is a divisional of, and claims priority to, co-pending U.S. patent application Ser. No. 13/950,008, filed on Jul. 24, 2013, which is commonly assigned and incorporated herein by reference in its entirety. This application is related to U.S. patent application Ser. No. 13/950,027, filed on Jul. 24, 2013. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present invention relates to integrated circuits, and more particularly to three-dimensional integrated circuit transformer structures configured for high turns ratios for use with high frequency applications. 
     2. Description of the Related Art 
     With an increased demand for personal mobile communications, integrated semiconductor devices such as complementary metal oxide semiconductor (CMOS) devices may, for example, include voltage controlled oscillators (VCO), low noise amplifiers (LNA), tuned radio receiver circuits, or power amplifiers (PA). Each of these tuned radio receiver circuits, VCO, LNA, and PA circuits may, however, require on-chip inductor components in their circuit designs. 
     Several design considerations associated with forming on-chip inductor components may, for example, include quality factor (i.e., Q-factor), self-resonance frequency (f SR ), and cost considerations impacted by the area occupied by the formed on-chip inductor. Accordingly, for example, a CMOS radio frequency (RF) circuit design may benefit from, among other things, one or more on-chip inductors having a high Q-factor, a small occupied chip area, and a high f SR  value. The self-resonance frequency (f SR ) of an inductor may be given by the following equation: 
                 f   SR     =     1     2   ⁢   π   ⁢     LC           ,         
where L is the inductance value of the inductor and C may be the capacitance value associated with the inductor coil&#39;s inter-winding capacitance, the inductor coil&#39;s interlayer capacitance, and the inductor coil&#39;s ground plane (i.e., chip substrate) to coil capacitance. From the above relationship, a reduction in capacitance C may desirably increase the self-resonance frequency (f SR ) of an inductor. One method of reducing the coil&#39;s ground plane to coil capacitance (i.e., metal to substrate capacitance) and, therefore, C value, is by using a high-resistivity semiconductor substrate such as a silicon-on-insulator (SOI) substrate. By having a high resistivity substrate (e.g., &gt;50 Ω-cm), the effect of the coil&#39;s metal (i.e., coil tracks) to substrate capacitance is diminished, which in turn may increase the self-resonance frequency (f SR ) of the inductor.
 
     The Q-factor of an inductor may be given by the equation: 
               Q   =       ω   ⁢           ⁢   L     R       ,         
where ω is the angular frequency, L is the inductance value of the inductor, and R is the resistance of the coil. As deduced from the above relationship, a reduction in coil resistance may lead to a desirable increase in the inductor&#39;s Q-factor. For example, in an on-chip inductor, by increasing the turn-width (i.e., coil track width) of the coil, R may be reduced in favor of increasing the inductors Q-factor to a desired value. In radio communication applications, the Q-factor value is set to the operating frequency of the communication circuit. For example, if a radio receiver is required to operate at 2 GHz, the performance of the receiver circuit may be optimized by designing the inductor to have a peak Q frequency value of about 2 GHz. The self-resonance frequency (f SR ) and Q-factor of an inductor are directly related in the sense that by increasing f SR , peak Q is also increased.
 
     On-chip transformers are formed from inductor-like structures. On-chip transformers are needed in radiofrequency (RF) circuits for a number of functions including impedance transformation, differential to single conversion and vice versa (balun), DC isolation and bandwidth enhancement to name a few. Some performance metrics of on-chip transformers may include a coefficient of coupling (K), occupied area, impedance transformation factor (turns ratio), power gain, insertion loss, efficiency and power handling capability. 
     SUMMARY 
     A transformer structure includes a first coil having two sections of spiral, with a top section including a plurality of metal layers occupying top X metal layers and a bottom section including a plurality of metal layers occupying bottom Z metal layers, where X and Z represent a number of metal layers having a specific number selected to provide a particular performance of the first coil. A second coil of the transformer is disposed between the two sections of the first coil and includes a plurality of metal layers where Y represents a number of vertically adjacent metal layers, with the specific number chosen to provide the particular performance, such that a sum X+Y+Z represents a total number of vertical metal layers for the transformer structure. 
     Another transformer structure includes a first coil having two sections of spiral, with a top section including a folded spiral occupying top X metal layers and a bottom section including a parallel stacked spiral occupying bottom Z metal layers, where X and Z represent a number of metal layers having a specific number selected to provide a particular performance. A second coil of the transformer is disposed between the two sections of the first coil and includes a parallel stacked spiral of Y metals with gradually decreasing width and increasing spacing from outermost turn to an innermost turn, where Y represents a number of vertically adjacent metal layers, with the specific number chosen to provide the particular performance, such that a sum X+Y+Z represents a total number of vertically adjacent metal layers for the transformer structure. 
     These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein: 
         FIG. 1  is a three-dimensional schematic diagram showing an in-phase transformer structure in accordance with one embodiment; 
         FIG. 2  is a three-dimensional schematic diagram showing an out-of-phase transformer structure in accordance with another embodiment; 
         FIG. 3  is a diagram showing inductor/coil configurations for use in accordance with the present principles; 
         FIG. 4  is a layout view showing layers of spirals for a transformer structure in accordance with one illustrative embodiment; 
         FIG. 5  is a cross-sectional view showing a metal layer stack for realizing the embodiment of  FIG. 4 ; 
         FIG. 6  is a plot of power gain versus frequency (GHz) for the structure of  FIG. 4  and a comparison structure; 
         FIG. 7  is a plot of insertion loss versus frequency (GHz) for the structure of  FIG. 4  and the comparison structure; 
         FIG. 8  is a layout view showing layers of spirals for a transformer structure in accordance with another illustrative embodiment; 
         FIG. 9  is a cross-sectional view showing a metal layer stack for realizing the embodiment of  FIG. 8 ; 
         FIG. 10  is a plot of power gain versus frequency (GHz) for the structure of  FIG. 8  and a comparison structure; 
         FIG. 11  is a plot of insertion loss versus frequency (GHz) for the structure of  FIG. 8  and the comparison structure; and 
         FIG. 12  is a three-dimensional schematic diagram showing another in-phase transformer structure in accordance with another embodiment. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     In accordance with the present principles, transformer structures are described that provide reduced occupied area, provide a high turns ratio and provide a higher efficiency. The transformer structures are integrated into metal layers of an integrated circuit device. A transformer in accordance with one embodiment includes a primary coil whose width and spacing varies from outer turns to inner turns optimizing ohmic and eddy current losses. A secondary coil has series parallel interconnections of a top metal portion (above the primary) and a bottom metal section (below the primary) resulting in higher impedance transformation ratio. Note the primary and secondary nomenclature can be reversed as the primary may be split into two sections above and below the secondary coil. Minimized loss in the both the primary and secondary results in higher power gain when compared to existing conventional solutions. 
     The present embodiments find utility in any device that includes or needs a transformer and, in particularly useful embodiments, the present principles provide transformers for high frequency applications such as communications applications, e.g., in GSM and CDMA frequency bands, amplifiers, power transfer devices, etc. 
     It is to be understood that the present invention will be described in terms of a given illustrative architecture formed on a wafer and integrated into a solid state device or chip; however, other architectures, structures, materials and process features and steps may be varied within the scope of the present invention. The terms coils, inductors and windings may be employed interchangeably throughout the disclosure. It should also be understood that these structures may take on any useful shape including rectangular, circular, oval, square, polygonal, etc. 
     It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     A design for an integrated circuit chip may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed. 
     Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment. 
     It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed. 
     Referring now to the drawings in which like numerals represent the same or similar elements and initially to  FIG. 1 , a three dimensional wiring diagram shows an in-phase transformer  50  in accordance with one illustrative embodiment. The transformer  50  includes a primary coil  54  disposed between portions of a secondary coil. The secondary coil includes a first secondary coil  52  and a second secondary coil  56 . The secondary coils  52  and  56  sandwich the primary coil  54 . It should be noted that the number of coils (primary and/or secondary) can be changed as needed. Transformer  50  includes a multilayer structure, which may be disposed on vertically stacked metal layers. For example, a first metal layer  60  may include M 1  or M 2 , a second metal layer  62  may include M 3 , a third metal layer  64  may include M 4 , and so on. The metal layers may correspond to the back end of the line (BEOL) region of a semiconductor device. 
     Being disposed on different layers, connections between the coils and other components, e.g., power sources, etc. is made to the coils  52 ,  54  and  56  with connections S 1  and S 2  and P 1  and P 2 . In addition, the secondary coils  52  and  56  are connected through an interlevel connection  58  (e.g., vias between metal layers). Since the winding direction in maintained in a same direction for all of the coils  52 ,  54  and  56 , wiring channels are needed in layer  62  for lines  66  and  68 . Voltage polarities are illustratively shown as +&#39;s and −&#39;s, but may be reversed as needed. 
     The three layer transformer structure  50  includes all windings in the same direction and phase, in combination with the primary coil  54  being centrally located between two halves of the secondary coil  52  and  56 , which may be connected together in series or in parallel. This structure results in a high coupling coefficient, which increases efficiency and bandwidth. It should be noted that while  FIG. 1  and  FIG. 2  represent the coils as disks, the coils may take on any number of useful structures. For example, a folded conical structure (or folded/multi-layered solenoidal spiral) may be employed for one or both portions of the secondary coil  52 ,  56  to increase the turns ratio while retaining the performance. In addition, variable wire width and wire spacings may be employed on each layer and can also increase efficiency and bandwidth. In another embodiment, parallel spiral layers are preferred to be employed to increase efficiency. The primary coil  54  may also include multiple adjacent layers of inductor coils connected in parallel. 
     Each layer (e.g.,  60 ,  62 ,  64 ) includes a number of turns in a paralleled spiral configuration. While the number of turns on each layer ( 60 ,  62 ,  64 ) is independent, the best coupling can be achieved when the primary and both secondary sections have the same number of turns and the same width, space and other dimensions. For a folded conical or folded solenoid structure improved bandwidth may be achieved by skipping one or more metal layers. It should be understood that the primary and secondary coils may be interchanged. 
     The portion  56  of the secondary coil may include a plurality of metal layers. The lower metal layers are sometimes very thin, so by connecting a number of metal layers in parallel using vias or a via pattern, a parallel stacked spiral having two or more metal layers may be achieved. 
     The inductor coils of the primary coil  54  may be reduced in number and made wider than the adjacent inductor coils in the secondary coil portion  52  and  56  to increase turns ratio, reduce series losses and increase current handling. The inductor coils of the section  52  may be decreased in width and increased in spacing, as compared to the inductor coils of the primary coil  56 , from an outermost turn to an innermost turn to reduce series losses. The inductor coils of the portion  56  may include a finer spacing than coils in the other sections  52 ,  54  to increase the turns ratio. The inductor coils of the portion  56  may include a wider track width than the inductor coils in the portion  52  to reduce series losses and increase current handling. The inductor coils of the portion  56  may be offset from the inductor coils of the primary coil  54  to increase performance. 
     Referring to  FIG. 2 , a three dimensional wiring diagram shows an out-of-phase transformer  50 ′ in accordance with another illustrative embodiment. The transformer  50 ′ includes a primary coil  54  disposed between portions of a secondary coil. The secondary coil includes a first secondary coil  52  and a second secondary coil  56 ′. The secondary coils  52  and  56 ′ sandwich the primary coil  54 . It should be noted that the number of coils (primary and/or secondary can be changed as needed). Transformer  50 ′ includes a multilayer structure, which may be disposed on vertically stacked metal layers. 
     The secondary coils  52  and  56 ′ are connected through an interlevel connection  58 ′ which is connected in a radial direction opposite that depicted in  FIG. 1 . The connection  58 ′ is made to the inside of the coil  56 ′ and the polarity of the voltage is switched to change the winding direction. By reversing the winding in the lower portion of the secondary coil  56 ′, high frequency performance in increased. Also, the two radial wiring channels ( 66 ,  68 ) needed in  FIG. 1  (in-phase) are not needed in  FIG. 2  (out-of-phase). 
     The transformer structures  50  and  50 ′ (sometimes called and used as a balun) on an integrated circuit or other layered or three dimensional wiring constructs may include spiral windings having a circular, a square, an octagonal or other polygonal shape. The windings are preferably stacked one above the other and all with a common axis. Top and bottom sets of windings or coils  52 ,  56  (or  56 ′) are combined as the secondary (or alternately as the primary winding) and are connected together in series with a winding direction so as to create a positive mutual inductance between the top and bottom portions ( 52 ,  56  (or  56 ′). 
     To generalize the structures  50 ,  50 ′, a top section includes X number of conducting layers and a bottom section includes Z number of conducting layers. A middle layer of the structure  50 ,  50 ′ forms the primary (or alternately the secondary) winding and is wound in the same direction as the top portion of the secondary winding or coil  52  and is comprised of Y number of conducting layers connected together in parallel. 
     In one embodiment, a high performance transformer includes the primary coil  54  and secondary coils  52 ,  56  (or  56 ′) where the secondary coil of the transformer comprises of two sections of spiral, with a top section being, e.g., a folded solenoidal spiral of the top X metals and the bottom section being, e.g., a parallel stacked spiral of the bottom Z metals. X, Y and Z represent an arbitrary number of vertically adjacent metal layers, with the specific number chosen to optimize performance. The primary coil  54  of the transformer  50 ,  50 ′ comprises one or more parallel spirals of Y metals with at least one gradually decreasing width and increasing spacing from outermost turn to the innermost. The sum X+Y+Z represents the total number of vertically adjacent metal layers chosen to comprise the transformer structure  50 ,  50 ′. This sum can be equal to the total number of metal layers present, or may be a smaller number chosen to optimize performance. 
     Different configurations or shapes may be employed for the coils. The coils may include a solenoid configuration, which includes a cork screw-like three-dimensional configuration. The coils may include a spiral configuration, which includes an in-plane spiral that winds from outside to inside in a spiral. The coils may include a conical configuration, which includes a cork screw-like three-dimensional configuration that spirals along an axis of the cone. Folded configurations include a reversal of direction of a shape and the coil follows the shape. For example, a folded conical includes a cone that has its apex reversed and the coils first follows the cone and then the reversed apex. 
     Referring to  FIG. 3 , a plurality of configurations is illustratively depicted and includes the following. A solenoid shape  70 , a spiral shape  72 , a conical shape  74 , a multi-layered (two) spiraled solenoid shape  76 , a stacked spiral (out-of-phase voltage)  78 , a stacked spiral (in-phase voltage)  80 , a folded conical  82  (can be folded more than once), a parallel stacked spiral (adjacent spiral are connected by vias along the spirals)  84 , etc. 
     Referring to  FIG. 4 , levels of a transformer structure  100  are shown in accordance with one embodiment. In this embodiment, a secondary coil includes a first (top) portion  90 ,  92  that includes two metal layers (e.g., M 6  and M 5 ). The secondary coil may include a solenoid shape, a folded solenoid shape or a folded conical shape. A folded solenoid shape includes winding up or down between levels in a solenoid shape. This is similar to a folded conical shape except each adjacent rotation alternates to drop down or wind up between the metal levels. 
     In the present embodiment, a folded conical or solenoidal shape is provided, which will be described using the numbers  1 - 19  in  FIG. 4 . The structure includes the secondary coil having a spiral stack of vertically folded solenoids or vertically folded conical spirals. The connections to the secondary coil are indicated by S 1  and S 2 , and the connections to the primary coil are indicated by P 1  and P 2 . 
     The top portion  90  on layer M 6  begins a point  1  and wraps around to point  2  then connects by a via to point  3  in layer M 5 . The coil wraps around to point  4  in layer M 5  and then returns back up to layer M 6  at point  5 . The coil wraps around to point  6  and then drops down again to layer M 5  at point  7 . The coil wraps around again to point  8  in the M 5  layer. Then, back up to the M 6  layer at point  9 . The coil wraps around to point  10  and then back down to the M 5  layer at point  11 . The coil wraps around again to point  12  in the M 5  layer, and then back up to point  13  in the M 6  layer. The coil wraps around again to point  14  in the M 5  layer. From point  14 , a via connects through layer M 5  in the second coil  92  of the secondary coil and continues through to point  16  in a first layer or coil  94  of a primary coil in metal layer M 4 . From point  16 , a via connects through metal layer M 3  to which provides a second layer or coil  96  of the primary coil to point  17 . Point  17  connects to point  18  in metal layer M 2  and/or M 1  to connect to point  19 , which includes an end of another coil  98  for the secondary coil. 
     The coils  90  and  92  of this embodiment include a similar spacing between lines and line width. The coil  94 , which is a primary coil, includes a variable width and spacing to reduce losses and increase electric isolation between the primary coil and the secondary coil. The coil  94  begins at point  1 ′ and warps around to point  2 ′ (a spiral) in metal layer M 4 . As the coil  94  wraps between point  1 ′ and point  2 ′, the lines width increases and the spacing between adjacent portions decreases. A via connects point  2 ′ to point  3 ′ in metal layer M 3 . Point  3 ′ is a first end of a wire channel  97 , which extends to point  4 ′ or P 2 . Providing the wire channel  97  and P 2  in the M 3  layer along with an entire coil  96  for the secondary coil substantially improves the performance of the transformer. 
     The coil  96  follows the coil pattern of the coil  98  below it. Coil  98  includes a spiral coil that connects with the coils  90  and  92  to form the secondary coil. The coil  96  in the M 3  layer is connected to coil  98  in the M 2  layer by a via pattern  101  to provide a parallel stacked spiral configuration. In addition, the coil  98  may be connected to another coil (not shown) in metal layer M 1  using the same or similar via pattern  101  to provide an additional tier for the parallel stacked spiral configuration for the lower coils of the secondary coil. 
     Referring to  FIG. 5 , a cross-sectional view of a semiconductor device or integrated circuit chip  108  is shown in accordance with one illustrative embodiment. A substrate  110  may include a silicon on-insulator (SOI) substrate, although other substrates may be employed. The SOI substrate offers less capacitance to structures formed thereon than bulk substrates. In addition, the SOI substrate permits use of lower metal layers for use in inductors and transformers.  FIG. 5  depicts metal layer M 1   112  and metal layer M 2   116  having a dielectric layer  114  therebetween. It is through this dielectric layer  114  that the via pattern (V 1 )  101  extends to connect the coils in the M 1  layer  112  and the M 2  layer  116 . Likewise, metal layer M 3   118  and metal layer M 2   116  have a dielectric layer  120  therebetween. It is through this dielectric layer  117  that the via pattern (V 2 )  101  extends to connect the coils in the M 3  layer  118  and the M 2  layer  116 . A dielectric layer  120  separates M 3  metal layer  118  from M 5  metal layer  122 . Metal layers  122  (M 4 ),  124  (M 5 ) and  130  (M 6 ) are separated by dielectric layers  124 , and  126 , respectively. Vias V 3 , V 4  and V 5  may be employed to make connections, if needed. Metal layers (M 6  and M 5 )  126 ,  130  provide sufficient thickness to permit a solenoidal or conical (or folded solenoidal or folded conical) winding in each metal layer. 
     Referring to  FIGS. 6 and 7 , simulation data is shown comparing the configuration of  FIG. 4  (present structure  154 ) with a design having spiral primary coil disposed between two spiral coils making up a secondary coil (comparison structure  152 ).  FIG. 6  plots power gain versus frequency (GHz) for the present structure  154  and the comparison structure  152 . As can be seen in region  150 , a 20-30% improvement is achieved in power gain between 2 GHz and 3 GHz. The devices tested include a turns ratio of approximately 4, K&gt;0.9 and area=300×300 sq. microns. 
       FIG. 7  plots insertion loss (dB) versus frequency (GHz) for the present structure  154  and the comparison structure  152 . As can be seen in region  156 , a 1-3 dB reduction in insertion loss is achieved between 2 GHz and 3 GHz. The devices tested include a turns ratio of approximately 4, K&gt;0.9 and area=300×300 sq. microns. 
     Referring to  FIG. 8 , levels of a transformer structure  200  are shown in accordance with another embodiment. In this embodiment, a secondary coil includes a first (top) portion that includes a coil  160  in a single metal layer (e.g., M 5 ). The secondary coil may include a solenoid shape or a spiral shape. The secondary coil also include coils  164 ,  166  and  168  which are disposed in other metal layers, e.g., M 3 , M 2  and M 1 , respectively. The connections between the coil  160  and the coil  164  occur through a via beginning at V 4 , continuing at point F 2 , through a metal layer M 4  which includes a primary coil  162  and landing on a V 2  on coil  164 . The secondary coil connections are indicated by S 1  and S 2 , and the connections to the primary coil are indicated by P 1  and P 2 . 
     The coil  160  has a different spacing between lines than for coils  164 ,  166  and  168 . The coil  162 , which is a primary coil in metal layer M 4 , includes a variable width and spacing to reduce losses and increase electric isolation between the primary coil and the secondary coil. The coil  162  begins at point V 3  and wraps around to P 1 . As the coil  162  wraps between V 3  and P 1 , the line width increases and the spacing between adjacent portions decreases. A via connects point V 3  to point FS in metal layer M 3 . FS is a first end of a wire channel  165 , which extends to P 2 . Providing the wire channel  165  and P 2  in the M 3  layer along with an entire coil  164  for the secondary coil substantially improves the performance of the transformer. 
     The coil  164  follows the coil pattern of the coil  166  below it in M 2 . Coil  164  includes a spiral coil that connects with the coil  160  and coils  166  and  168  to form the secondary coil. The coil  164  in the M 3  layer is connected to coil  166  in the M 2  layer by a via pattern  170  (V 1  and V 2 ) to provide a parallel stacked spiral configuration. In addition, the coil  166  may be connected to another coil  168  in metal layer M 1  using the same or similar via pattern  170  to provide an additional tier for the parallel stacked spiral configuration for the lower coils of the secondary coil. The via pattern  170  (and/or  101 ) may be continuous or include a plurality of discreet via connections. 
     Referring to  FIG. 9 , a cross-sectional view is of a semiconductor device or integrated circuit chip  108  is shown in accordance with another illustrative embodiment. A substrate  110  may include a silicon on-insulator (SOI) substrate, although other substrate may be employed. The SOI substrate offers less capacitance to structures formed thereon than bulk substrates. In addition, the SOI substrate permits use of lower metal layers for use in inductors and transformers.  FIG. 9  depicts metal layer M 1   130  and metal layer M 2   134  having a dielectric layer  132  therebetween. It is through this dielectric layer  132  that the via pattern (V 1 )  170  extends to connect the coils in the M 1  layer  130  and the M 2  layer  134 . Likewise, metal layer M 3   138  and metal layer M 2   134  have a dielectric layer  120  therebetween. It is through this dielectric layer  136  that the via pattern (V 2 )  170  extends to connect the coils in the M 3  layer  138  and the M 2  layer  116 . A dielectric layer  140  separates M 3  metal layer  138  from M 4  metal layer  142 . Metal layers  142  (M 4 ) and  146  (M 5 ) are separated by dielectric layer  144 . Vias at V 3  and V 4  may also be employed. 
     Referring to  FIGS. 10 and 11 , simulation data is shown comparing for the configuration of  FIG. 8  (present structure  184 ) with a design having spiral primary coil disposed between two spiral coils making up a secondary coil (comparison structure  182 ).  FIG. 10  plots power gain versus frequency (GHz) for the present structure  184  and the comparison structure  182 . As can be seen in region  180 , an 8-10% improvement is achieved in power gain between 800 MHz and 3 GHz. The devices simulated include a turns ratio of approximately 3, K&gt;0.9 and area=300×300 sq. microns. 
       FIG. 11  plots insertion loss (dB) versus frequency (GHz) for the present structure  184  and the comparison structure  182 . As can be seen in region  186 , a 0.4-0.5 dB reduction in insertion loss is achieved between 800 MHz and 3 GHz. The devices simulated include a turns ratio of approximately 3, K&gt;0.9 and area=300×300 sq. microns. 
     Referring to  FIG. 12 , a three-dimensional schematic diagram is shown for another embodiment (similar to  FIG. 8 ) to describe additional features in accordance with the present principles. A transformer  300  includes three planar spiral inductors  302 ,  304  and  306  (or modified versions thereof), each with an inner terminal  308  and outer terminal  310 . The spiral inductors  302 ,  304  and  306  are stacked vertically adjacent to each other on parallel planes with a shared common axis and all having similar outer dimensions. Inductor  304  includes a primary, and the top and bottom inductors  302  and  306  are connected as a secondary (although functionally the primary and secondary can be interchanged). All three inductors  302 ,  304  and  306  are wound in a same direction (e.g., clockwise when viewed from the top) starting at the outside edge of each winding  302 ,  304  and  306 . The inner terminals  308  of each of the three spiral inductors  302 ,  304  and  306  are connected by separate vias  312  vertically to one or more layers designated for radial connections (+S, +P, −S, −P) of inner spiral terminals  308  to an accessible outer edge of the structure  300 . The inner terminal  308  of the primary spiral  304  and the inner terminal  308  of the top portion of the secondary  302  (as a center tap of the combined secondary structure) are connected through a break through a portion of the spiral  306  (wire channels) and thereby made available at the outer edge of the structure  300 . The spiral  306  may include multiple parallel layers on different metal layers, which are connected using vias. 
     Connections to the inner terminals  308  of each of the three layered sections may be made with radial wiring channels on wiring layers above or below the transformer structure if available and desired, or they may be included as one or more of the layers used for any parallel wound spiral layer sections and with the use of vias and metal stacks for the needed vertical wiring  312 . For the series connected secondary, three radial wiring channels may be employed, one to connect the inner terminal of the upper secondary to the outer terminal of the lower secondary and two to connect the inner terminal of the primary and the lower secondary to the exterior of the transformer structure. For the parallel connected secondary, two radial wiring channels are used to connect the inner terminal of the primary and the upper or lower secondary to the exterior of the transformer structure. For the series connected secondary with out-of-phase lower secondary, one wiring channel is used to connect the inner terminal of the primary to the exterior of the transformer structure. Wires can be of fixed width and spacing on each layer or wire widths can decrease and wire space can increase as wiring progresses from the outer terminal to the inner terminal. Other configurations are contemplated. 
     It should be noted that the number of coils (primary and/or secondary can be changed as needed). The transformers described herein may include multilayered structures which may be disposed on vertically stacked metal layers that correspond to the back end of the line (BEOL) region of a semiconductor device. 
     It should be understood that the structures described herein may be further enhance by the use of magnetic core materials. These materials may be employed for planar spirals, solenoid or conical inductors, etc. to modify the performance parameters for specific applications. A magnetic material may be introduced between sections to further increase the coupling coefficient or the coils may be formed from a high permeability magnetic material. 
     In some embodiments, the primary spiral (middle section) turns can be reduced in number and made wider to increase the turns ratio, reduce series losses and increase current handling. The top section of the secondary spiral turns can also have gradually decreasing width and increasing spacing from the outermost turn to innermost turn to reduce series losses. The bottom section of the secondary spiral turns can use the advantage of finer spacing to increase the turns ratio. The bottom section of the secondary spiral turns can have wider track widths than the top section to reduce series losses and increase current handling. The bottom section of the secondary spiral turns can be offset from the primary turns to increase the high frequency performance at the cost of slightly reduced turns ratio. 
     The 3D wiring and structures of the transformers in accordance with the present principles enhance high frequency performance with the following features: high inductance density, high Q for both primary and secondary (low insertion loss), higher turns ratio (impedance transformation ratio), suitability for high power applications, etc. 
     Having described preferred embodiments for high efficiency on-chip 3D transformer structures (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.