Patent Publication Number: US-2022231173-A1

Title: Surface damage control in diodes

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Patent Application No. 63/138,078, titled “Semiconductor Device and the Method for Fabricating the Same,” filed Jan. 15, 2021, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). Such scaling down has increased the complexity of semiconductor manufacturing processes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. 
         FIGS. 1A-1B  illustrates cross-sectional views of a diode, in accordance with some embodiments. 
         FIG. 1C  illustrates device characteristics of a diode, in accordance with some embodiments. 
         FIG. 2  is a flow diagram of a method for fabricating a diode, in accordance with some embodiments. 
         FIGS. 3-19  illustrate cross-sectional views of a diode at various stages of its fabrication process, in accordance with some embodiments. 
         FIGS. 20-21  illustrate crystal structures of a capping layer used in the fabrication of a diode, in accordance with some embodiments. 
     
    
    
     Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. The discussion of elements with the same annotations applies to each other, unless mentioned otherwise. 
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the embodiments and/or configurations discussed herein. 
     Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. 
     It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein. 
     In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein. 
     The present disclosure provides example diodes (e.g., Schottky barrier diodes) and example methods of forming the same. The diode can include a metallic layer disposed on a semiconductor substrate. In some embodiments, the metallic layer can include a stack of metal silicide nitride layer and metal silicide layer. The nitrogen atoms in the metal silicide nitride layer prevent or mitigate the formation of surface traps on the metal silicide nitride layer that cause current leakage in the diode. The surface traps can be due to dangling surface bonds formed during the formation of metallic layer. Surface traps on metallic layer can trap charges and lower the Schottky barrier between metallic layer and the semiconductor material of the substrate. Lowering of the Schottky barrier can result in current leakage during the off state of the diode. In some embodiments, the surface current leakage in the diode with the stack of metal silicide nitride layer and metal silicide layer can be reduced by about 10% to about 50% compared to diodes without the metal silicide nitride layers in the metallic layers. In some embodiments, the diode can include an etch stop layer disposed on the metallic layer and a contact structure disposed on the metallic layer through the etch stop layer. 
     In some embodiments, the metal silicide layer can be formed by a silicidation process between a metal layer and the semiconductor material of the substrate. In some embodiments, a top portion of the metal silicide layer can be converted to the metal silicide nitride layer during a surface treatment process of the metallic layer performed simultaneously with the silicidation process. The surface treatment process can include introducing nitrogen atoms to the metallic layer through a capping layer disposed on the metallic layer. The capping layer can include a metal nitride material and can prevent the oxidation of the metallic layer during the silicidation process. 
     In some embodiments, for the adequate diffusion of nitrogen atoms through the capping layer during the surface treatment process, the metal nitride material of the capping layer is formed with a cubic crystal structure. The cubic packing arrangement of the metal atoms and the nitrogen atoms of the capping layer allows nitrogen gas to flow through the capping layer during the surface treatment process. In some embodiments, the formation of the capping layer with the cubic crystal structure can include forming a layer of metal nitride with a metal to nitrogen concentration ratio ranging from about 1:3 to about 1:4. using a gas mixture of argon and nitrogen-based gas. In some embodiments, the ratio of nitrogen to argon in the gas mixture ranges from about 2 to about 4 to form the metal nitride material of the capping layer with a cubic crystal structure. If the metal to nitrogen concentration ratio is outside the range of about 1:3 to about 1:4 and/or if the ratio of nitrogen to argon in the gas mixture is outside the range of about 2 to about 4, the metal atoms and the nitrogen atoms of the capping layer can be formed with other crystal structures, such as hexagonal close-packed (HCP) crystal structure. The HCP packing arrangement of the metal atoms and nitrogen atoms can block the diffusion of nitrogen atoms through the capping layer during the surface treatment process. 
       FIGS. 1A and 1B  illustrate different cross-sectional views of a diode  100 , according to some embodiments. In some embodiments, diode  100  can be a Schottky barrier diode. The discussion of elements in  FIGS. 1A-1B  with the same annotations applies to each other, unless mentioned otherwise. 
     Referring to  FIGS. 1A-1B , diode  100  can be formed on a substrate  102 . There may be other semiconductor devices, such as FETs and/or other diodes formed on substrate  102 . Substrate  102  can be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), a silicon-on-insulator (SOI) structure, other suitable semiconductor materials, and a combination thereof. In some embodiments, substrate  102  can include an epitaxial semiconductor layer, a gradient semiconductor layer, or a semiconductor layer on another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer. In some embodiments, substrate  102  can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). 
     In some embodiments, diode  100  can include (i) a first well region  104 , (ii) a second well region  106 , (iii) a third well region  108 , (iv) a fourth well region  110 , (v) first doped regions  112 , (vi) second doped regions  114 , (vii) metallic layers  116 A,  118 A, and  120 A, (viii) shallow trench isolation (STI) regions  122 , (ix) dielectric layers  124 , (x) an etch stop layer (ESL)  126 , (xi) an interlayer dielectric (ILD) layer  128 , and (xii) contact structures  130 ,  132 , and  134 . 
     The elements and/or portions of the elements of diode  100  within region  101 A can form an anode region  101 A, regions  101 B can form cathode regions  101 B, and regions  101 C can form bulk regions  101 C. In some embodiments, anode region  101 A can include fourth well region  110 , metal layer  116 A, contact structure  130 , and portions of second well region  106 , ESL  126 , and ILD layer  128  within region  101 A. In some embodiments, cathode regions  101 B can include first doped regions  112 , metal layers  118 A, contact structures  132 , and portions of second well region  106 , ESL  126 , and ILD layer  128  within region  101 B. In some embodiments, bulk regions  101 C can include second doped regions  114 , metal layers  120 A, contact structures  134 , and portions of third well region  108 , ESL  126 , and ILD layer  128  within region  101 C. diode  100  can be configured to have electric current flow from anode region  101 A to cathode regions  101 B during operation and to electrically connect bulk regions  101 C to substrate  102 . 
     First well region  104  can be a deep well region disposed within substrate  102 . In some embodiments, first well region  104  can be doped with a type of dopant (i.e., n- or p-type) that is different from the type of dopant in substrate  102 . In some embodiments, first well region  104  can be doped with n-type dopants, such as phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants with a doping concentration ranging from about 1×10 15  atoms/cm 3  to about 1×10 17  atoms/cm 3 . In some embodiments, first well region  104  can be about 4 μm to about 6 μm below ESL  126  and can have a thickness ranging from about 0.5 μm to about 4 μm. 
     Second well region  106  can be disposed on first well region  104  and within substrate  102 . In some embodiments, dimensions (e.g., widths) of first and second well regions  104  and  106  along an X-axis can be substantially equal to each other. In some embodiments, second well region  106  can be doped with a type of dopant (i.e., n- or p-type) that is the same as the type of dopant in first well region  104 , but with a doping concentration that is less than the doping concentration of first well region  104 . In some embodiments, second well region  106  can be doped with n-type dopants, such as phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants with a doping concentration ranging from about 1×10 13  atoms/cm 3  to about 1×10 16  atoms/cm 3 . 
     Third well region  108  can be disposed within substrate  102  and adjacent to and/or laterally surrounding second well region  106 . In some embodiments, third well region  108  can be doped with a type of dopant (i.e., n- or p-type) that is different from the type of dopant in second well region  106 , and with a doping concentration that is greater than the doping concentration of second well region  106  and substrate  102 . In some embodiments, third well region  108  can be doped with p-type dopants, such as boron, indium, aluminum, gallium, and other suitable p-type dopants with a doping concentration ranging from about 1×10 15  atoms/cm 3  to about 1×10 18  atoms/cm 3 . 
     In some embodiments, fourth well region  110  can include an array of well regions disposed within second well region  106 , as shown in  FIG. 1A . The array of well regions can include greater than five and less than fifteen well regions for diode  100  to adequately function without compromising device size and manufacturing cost. In some embodiments, fourth well region  110  can be doped with a type of dopant (i.e., n- or p-type) that is different from the type of dopant in second well region  106 , and with a doping concentration that is greater than the doping concentration of second well region  106  and substrate  102 . In some embodiments, fourth well region  110  can be doped with p-type dopants, such as boron, indium, aluminum, gallium, and other suitable p-type dopants with a doping concentration ranging from about 1×10 15  atoms/cm 3  to about 1×10 18  atoms/cm 3 . In some embodiments, the dimensions (e.g., heights) of fourth well region  110  along a Z-axis can greater than that of STI regions  122 . 
     First doped regions  112  can be disposed within second well region  106 . In some embodiments, first doped regions  112  can be doped with a type of dopant (i.e., n- or p-type) that is different from the type of dopant in fourth well region  110 , and with a doping concentration that is substantially equal to or greater than the doping concentration of fourth well region  110 . In some embodiments, first doped regions  112  can be doped with n-type dopants, such as phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants with a doping concentration ranging from about 1×10 17  atoms/cm 3  to about 1×10 21  atoms/cm 3 . In some embodiments, first doped regions  112  can act as the cathodes of diode  100  and can conductively couple cathode regions  101 B to a cathode terminal (not shown). The doping concentration of first doped regions  112  can be used to control electrical properties of cathode regions  101 B. 
     Second doped regions  114  can be disposed within third well region  108 . In some embodiments, second doped regions  114  can form a continuous region surrounding cathode regions  101 B. In some embodiments, second doped regions  114  can be doped with a type of dopant (i.e., n- or p-type) that is different from the type of dopant in first doped regions  112 , and with a doping concentration that is substantially equal to or greater than the doping concentration of first doped regions  112 . In some embodiments, second doped regions  114  can be doped with p-type dopants, such as boron, indium, aluminum, gallium, and other suitable p-type dopants with a doping concentration ranging from about 1×10 17  atoms/cm 3  to about 1×10 21  atoms/cm 3 . In some embodiments, second doped regions  114  can conductively couple bulk regions  101 C to a body terminal (not shown). The doping concentration of second doped regions  114  can be used to control electrical properties of bulk regions  101 C. 
     Referring to  FIG. 1A , in some embodiments, metallic layer  116 A can include (i) a metal silicide layer  136  disposed on second well region  106  and fourth well region  110 , and (ii) a metal silicide nitride layer  138  disposed on metal silicide layer  136 . In some embodiments, both metal silicide layer  136  and metal silicide nitride layer  138  can be disposed within substrate  102 . In some embodiments, a top surface  138   s  of metal silicide nitride layer  138  can be substantially coplanar with a top surface  102   s  of substrate  102 . In some embodiments, an interface  140  between metal silicide layer  136  and metal silicide nitride layer  138  can be disposed within substrate  102  and at a plane lower than top surface  142  of substrate  102 . 
     Referring to  FIG. 1B , in some embodiments, diode  100  can have a metallic layer  116 B with metal silicide layer  136  disposed within substrate  102  and metal silicide nitride layer  138  disposed on top surface  102   s  of substrate  102 . Interface  140  between metal silicide layer  136  and metal silicide nitride layer  138  can be substantially coplanar with top surface  102   s  of substrate  102 , or can be disposed at a plane higher than top surface  102   s  of substrate  102  (not shown). The relative position of metallic layers  116 A and  116 B with respect to top surface  102   s  of substrate  102  can depend on the fabrication process of diode  100 , as described in detail below. 
     Referring to  FIGS. 1A and 1B , Schottky junctions can be formed at the interfaces between metal silicide layer  136  and second well region  106  and between metal silicide layer  136  and fourth well region  110 . In some embodiments, metal silicide layer  136  can include cobalt silicide (Co x Si y ), titanium silicide (Ti x Si y ), nickel silicide (Ni x Si y ), tantalum silicide (Ta x Si y ), molybdenum (Mo x Si y ), platinum silicide (Pt x Si y ), zirconium silicide (Zr x Si y ), tungsten silicide (W x Si y ), scandium silicide (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), lutetium silicide (Lu x Si y ), erbium silicide (Er x Si y ), ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), thorium silicide (Th x Si y ), manganese silicide (Mn x Si y ), iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), iridium silicide (Ir x Si y ), osmium silicide (Os x Si y ), other suitable metal silicide materials, or a combination thereof. In some embodiments, metal silicide layer  136  can include Co x Si y , Ti x Si y , or Ni x Si y , where the value of x is equal to 1 and the value of y is equal to 1. 
     In some embodiments, metal silicide nitride layer  138  can include cobalt silicide nitride (Co x Si y N z ), titanium silicide nitride (Ti x Si y N z ), nickel silicide nitride (Ni x Si y N z ), tantalum silicide nitride (Ta x Si y N z ), molybdenum nitride (Mo x Si y N z ), platinum silicide nitride (Pt x Si y N z ), zirconium silicide nitride (Zr x Si y N z ), tungsten silicide nitride (W x Si y N z ), scandium silicide nitride (Sc x Si y N z ), yttrium silicide nitride (Y x Si y N z ), terbium silicide nitride (Tb x Si y N z ), lutetium silicide nitride (Lu x Si y N z ), erbium silicide nitride (Er x Si y N z ), ytterbium silicide nitride (Yb x Si y N z ), europium silicide nitride (Eu x Si y N z ), thorium silicide nitride (Th x Si y N z ), manganese silicide nitride (Mn x Si y N z ), iron silicide nitride (Fe x Si y N z ), rhodium silicide nitride (Rh x Si y N z ), palladium silicide nitride (Pd x Si y N z ), ruthenium silicide nitride (Ru x Si y N z ), iridium silicide nitride (Ir x Si y N z ), osmium silicide nitride (Os x Si y N z ), other suitable metal silicide nitride materials, or a combination thereof, where the value of z is ranges from about 1 to about 2. In some embodiments, metal silicide nitride layer  138  can include Co x Si y N z , Ti x Si y N z , or Ni x Si y N z , where the value of x is equal to 1, the value of y is equal to 1, and the value of z ranges from about 1 to about 2. 
     The nitrogen atoms in metal silicide nitride layer  138  prevent or mitigate the formation of surface traps on top surface  138   s  of metal silicide layer  138  and at interface  140  between metal silicide layer  136  and metal silicide nitride layer  138 . The surface traps can be due to dangling surface bonds formed during the formation of metallic layer  116 A. Surface traps on metallic layer  116 A and/or at interface  140  can trap charges and lower the Schottky barrier between metallic layer  116 A and the semiconductor material (e.g., silicon) of second well region  106  and fourth well region  110 . Lowering of the Schottky barrier can result in current leakage during the off state of diode  100 . With the use of metal silicide nitride layer  138  on metal silicide layer  136 , current leakage in diode  100  can be reduced by about 10% to about 50% compared to diodes without metal silicide nitride layer  136 . Thus, the device performance of diode  100  can be improved with the use of metal silicide nitride layer  138  in metallic layers  116 A and  116 B. 
       FIG. 1C  shows the nitrogen, metal, and silicon concentration profiles  142 ,  144 , and  146  across ESL  126 , metal silicide nitride layer  138 , metal silicide layer  136 , and second well region  106  along line A-A of  FIGS. 1A and 1B , according to some embodiments. As shown in  FIG. 1C , the peak concentration of nitrogen atoms (profile  142 ) is close to top surface  138   s  of metal silicide nitride layer  138 . In some embodiments, for adequate reduction in current leakage in diode  100 , the peak concentration of nitrogen atoms is a distance D 1  away from top surface  138   s  of metal silicide nitride layer  138 . In some embodiments, distance D 1  can range from about 0.05 nm to about 1 nm. If distance D 1  is greater than 1 nm, the resistivity and/or current leakage of diode  100  increases, and as a result, degrades the device performance. 
     Referring to  FIGS. 1A-1B , in some embodiments, for adequate device performance of diode  100  with minimal current leakage, metal silicide layer  136  can have a thickness T 1  ranging from about 20 nm to about 40 nm and metal silicide nitride layer  138  can have a thickness T 2  less than 9 nm (e.g., from about 0.1 nm to about 8.9 nm). In some embodiments, a ratio between thickness T 2  and thickness T 1  (i.e., T 2 :T 1 ) can range from about 1:3 to about 1:20. 
     The discussion of metallic layers  116 A and  116 B applies to (i) metallic layers  118 A and  118 B disposed on first doped regions  112 , and (ii) metallic layers  120 A and  120 B disposed on second doped regions  114 , unless mentioned otherwise. 
     STI regions  122  can be configured to electrically isolate anode region  101 A from cathode regions  101 B and electrically isolate cathode regions  101 B from bulk regions  101 C. In some embodiments, STI regions  122  can include an insulating material, such as silicon oxide (SiO x ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), other suitable insulating materials, and a combination thereof. In some embodiments, STI regions  122  can be disposed within substrate  102  and top surface of STI regions  122  can be substantially coplanar with top surface  102   s  of substrate  102 . In some embodiments, the top surface of STI regions  122  can be substantially coplanar with top surface  138   s  of metal silicide layer  138 , as shown in  FIG. 1A , or can be substantially coplanar with interface  140 , as shown in  FIG. 1B . In some embodiments, interface  140  can be at a plane higher than the top surface of STI regions  122  (not shown). In some embodiments, the dimensions (e.g., heights) of STI regions  122  along a Z-axis can be smaller than the dimensions (e.g., heights) of fourth well region  110  along a Z-axis. In some embodiments, the dimensions (e.g., heights) of STI regions  122  along a Z-axis can be greater than the dimensions (e.g., heights) of first doped regions  112  and second doped regions  114  along a Z-axis. 
     In some embodiments, dielectric layers  124  can include oxide layers and can be configured to control the resistivity of diode  100 . The resistivity can be controlled by adjusting the dimensions (e.g., lengths) of dielectric layers  124  along an X-axis. Extending the dimensions (e.g., lengths) of dielectric layer  124  along an X-axis to reduce distance D 2  between dielectric layers  124  can increase the resistivity of diode  100 . In addition, adjusting distance D 2  between dielectric layers  124  can control the dimensions of metallic layers  116 A and  116 B along an X-axis, and as a result control the resistivity of diode  100 . 
     In some embodiments, ESL  126  can include an insulating material, such as silicon oxide (SiO x ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), other suitable insulating materials, and a combination thereof. ESL  126  protects underlying layers from subsequent processing of ILD layer  128  and/or contact structures  130 ,  132 , and  134  of diode  100  and/or from subsequent processing of other structures (e.g., interconnect structures) on diode  100  and/or on substrate  102 . In some embodiments, ESL  126  can have a thickness T 3  ranging from about 5 nm to about 10 nm for adequate protection of underlying layers without compromising device size and manufacturing cost. In some embodiments, a ratio between thickness T 2  of metal silicide nitride layer  138  and thickness T 3  of ESL  126  (i.e., T 2 :T 3 ) can range from about 1:20 to about 1:40. 
     In some embodiments, ILD layer  128  can include an insulating material, such as silicon oxide (SiO x ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), other suitable insulating materials, and a combination thereof. Contact structures  130 ,  132 , and  134  can be disposed on metal silicide nitride layers  138  through ILD layer  128  and ESL  126 . Each of contact structures  130 ,  132 , and  134  can include a conductive material with low resistivity (e.g., resistivity of about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm, or about 10 μΩ-cm), such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), Osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), other suitable conductive materials with low resistivity, and a combination thereof. In some embodiments, the dimension (e.g., width) of contact structures  130  along an X-axis can be greater than the dimension (e.g., widths) of contact structures  132 , and  134  along an X-axis. 
       FIG. 2  is a flow diagram of an example method  200  for fabricating diode  100  with cross-sectional views shown in  FIGS. 1A and 1B , according to some embodiments. For illustrative purposes, the operations illustrated in  FIG. 2  will be described with reference to the example fabrication process for fabricating diode  100  as illustrated in  FIGS. 3-21 .  FIGS. 3-19  are cross-sectional views of diode  100  at various stages of fabrication, according to some embodiments.  FIGS. 20-21  illustrate crystal structures of a capping layer used in the fabrication of a diode  100 , according to some embodiments. Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method  200  may not produce a complete diode  100 . Accordingly, it is understood that additional processes can be provided before, during, and after method  200 , and that some other processes may only be briefly described herein. Elements in  FIGS. 3-21  with the same annotations as elements in  FIGS. 1A-1B  are described above. 
     In operation  205 , isolation regions are formed in a substrate. For example, as shown in  FIG. 3 , STI regions  122  are formed in substrate  102 . The formation of STI regions  122  can include sequential operations of (i) forming trenches (not shown) in substrate  102 , (ii) depositing a layer of insulating material within the trenches to fill the trenches (not shown), and (iii) performing a chemical mechanical polishing (CMP) process on the layer of insulating material to form the structure of  FIG. 3 . 
     Referring to  FIG. 2 , in operation  210 , well regions are formed in the substrate. For example, as described with reference to  FIGS. 4-6 , first well region  104 , second well region  106 , third well region  108 , and fourth well region  110  are formed in substrate  102 . The formation of well regions can include sequential operations of (i) forming a patterned masking layer  447  on STI regions  122 , as shown in  FIG. 4 , (ii) implanting n-type dopants within substrate  102  to form first well region  104 , as shown in  FIG. 4 , (iii) implanting n-type dopants on substrate region over first well region  104  to form the structure of  FIG. 4 , (iv) implanting p-type dopants within substrate regions adjacent to second well region  106  to form the structure of  FIG. 5 , (v) removing patterned masking layer  447  from the structure of  FIG. 5  (not shown), (vi) forming a patterned masking layer  647 , as shown in  FIG. 6 , (vii) implanting p-type dopants through openings  649  to form the structure of  FIG. 6 , and (viii) removing patterned masking layer  647 . 
     Referring to  FIG. 2 , in operation  215 , doped regions are formed between the isolation regions. For example, as shown in  FIG. 7 , first doped regions  112  and second doped regions  114  are formed between STI regions  122 . First doped regions  112  can be formed by implanting n-type dopants within second well region between STI regions  122 , as shown in  FIG. 7 . Second doped regions  114  can be formed by implanting p-type dopants within third well regions  108 , as shown in  FIG. 7 . After the formation of second doped regions  114 , dielectric layers  124  can be patterned on the structure of  FIG. 7  to form the structure of  FIG. 8 . 
     Referring to  FIG. 2 , in operation  220 , metallic layers are formed on the well regions and the doped regions. For example, as described with reference to  FIGS. 9-17 , metallic layers  116 A and  116 B are formed on second well region  106  and fourth well region  110 , metallic layers  118 A and  118 B are formed on first doped regions  112 , and metallic layers  120 A and  120 B are formed on second doped regions  114 . Metallic layers  116 A,  118 A, and  120 A can be formed at the same time and metallic layers  116 B,  118 B, and  120 B can be formed at the same time, as described below. 
     The formation of metallic layers  116 A,  118 A, and  120 A can include sequential operations of (i) depositing a metal layer  948  on the structure of  FIG. 8  to form the structure of  FIG. 9 , (ii) depositing a capping layer  1050  on the structure of  FIG. 9  to form the structure of  FIG. 10 , (iii) simultaneously performing a thermal anneal process and a surface treatment process on the structure of  FIG. 10 , as shown in  FIG. 11 , to form the structure of  FIG. 12 , and (iv) removing capping layer  1050  and unreacted metal layer  1248  to form the structure of  FIG. 14 . 
     Similarly, the formation of metallic layers  116 B,  118 B, and  120 B can include sequential operations of (i) depositing metal layer  948  on the structure of  FIG. 8  to form the structure of  FIG. 9 , (ii) depositing capping layer  1050  on the structure of  FIG. 9  to form the structure of  FIG. 10 , (iii) performing a thermal anneal process and a surface treatment process on the structure of  FIG. 10 , as shown in  FIG. 11 , to form the structure of  FIG. 13 , and (iv) removing capping layer  1050  and unreacted metal layer  1248  to form the structure of  FIG. 15 . Unreacted metal layer  1248  is a portion of metal layer  948  that did not convert into silicide. 
     In some embodiments, the thermal anneal process can include annealing the structure of  FIG. 10  with a rapid thermal anneal process at a temperature of about 550° C. to about 850° C. The thermal anneal process can initiate a silicidation reaction between metal layer  948  and the semiconductor material (e.g., silicon) of second well region  106 , third well regions  108 , and fourth well region  110  to form metal silicide layers  136 , as shown in  FIG. 12  or  FIG. 13 . The top surfaces of metal silicide layers  136  may have dangling bonds, which can create surface traps, as explained above. The surface treatment process simultaneously performed with the thermal anneal process can repair the top surfaces of metal silicide layer  136  during the silicidation reaction. 
     In some embodiments, the surface treatment process can include flowing nitrogen-based gas  1152  during the thermal anneal process, as shown in  FIG. 11 . In some embodiments, nitrogen-based gas can include nitrogen gas, ammonia gas (NH3), nitrous oxide gas (N 2 O), or other suitable nitrogen-based gas  1152 . The nitrogen atoms can react with top portions of metal silicide layers  136  and form metal silicide nitride layers  138 , as shown in  FIG. 12  or  FIG. 13 .  FIG. 12  illustrates the relative position of metal silicide layers  136  and metal silicide nitride layers  138  with respect to top surface  102   s  of substrate  102  when unreacted metal layer  1248  remains on metal silicide nitride layer  138 .  FIG. 13  illustrates the relative position of metal silicide layers  136  and metal silicide nitride layers  138  with respect to top surface  102   s  of substrate  102  when there is no unreacted metal layer  1248  on metal silicide nitride layers  138 . The presence or absence of unreacted metal layer  1248  on metal silicide nitride layers  138  depends on the anneal temperature and duration. 
     Capping layer  1050  can prevent oxidation of metallic layers  116 A and  116 B during the thermal anneal process. In some embodiments, the deposition of capping layer  1050  can include depositing a layer of metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), and other suitable metal nitride materials. For the adequate diffusion of nitrogen atoms through capping layer  1050  during the surface treatment process, the metal nitride material of capping layer  1050  is formed with a cubic crystal structure, as shown in  FIG. 20 . As illustrated in  FIG. 21 , the cubic packing arrangement of the metal atoms and the nitrogen atoms of capping layer  1050  allows nitrogen gas to flow through capping layer  1050  during the surface treatment process. The ( 100 ), ( 200 ), or ( 220 ) crystal planes (not shown) of top surface  1050   s  of capping layer  1050  exposed to nitrogen gas flow  1152  facilitate the diffusion of nitrogen atoms through capping layer  1050 . If capping layer  1050  is formed with other crystal structures, such as hexagonal closed packed (HCP) structure, the HCP packing arrangement of the metal atoms and nitrogen atoms can block the diffusion of nitrogen atoms during the surface treatment process. 
     In some embodiments, the formation of capping layer  1050  with cubic crystal structure can include forming a layer of metal nitride with a metal to nitrogen concentration ratio ranging from about 1:3 to about 1:4. If the metal to nitrogen concentration ratio is less than about 1:3, the metal nitride material may have an HCP crystal structure. In some embodiments, capping layer  1050  can be formed with a physical vapor deposition process using a gas mixture of argon and nitrogen-based gas, such as nitrogen gas, ammonia gas (NH3), nitrous oxide gas (N 2 O), or other suitable nitrogen-based gas. In some embodiments, the ratio of nitrogen to argon in the gas mixture ranges from about 2 to about 4 to form the metal nitride material of capping layer  1050  with a cubic crystal structure and with a metal to nitrogen concentration ratio of about 1:3 to about 1:4. If the ratio of nitrogen to argon in the gas mixture is outside the range of about 2 to about 4, the concentration of metal may increase and the metal nitride material may have a non-cubic crystal structure, such as an HCP crystal structure. 
     Referring to  FIG. 2 , in operation  225 , contact structures are formed on the metallic layers. For example, as shown in  FIGS. 18 and 19 , contact structures  130 ,  132 , and  134  can be formed on metal silicide nitride layers  138  through ESL  126  and ILD layer  128 . Prior to the formation of contact structures  130 ,  132 , and  134 , ESL  126  can be formed on the structure of  FIG. 14  or  FIG. 15  to form the structure of  FIG. 16  or  FIG. 17 , respectively. The formation of ESL  126  can be followed by the formation of ILD layer  128 . The formation of contact structures  130 ,  132 , and  134  can include sequential operations of (i) forming contact openings (not shown) within ILD layer  128  and ESL  126 , (ii) depositing conductive material within the contact openings, and (iii) performing a CMP process on the conductive material to form the structure of  FIG. 18  or  FIG. 19 . 
     The present disclosure provides example diodes (e.g., diode  100 ) and example methods (e.g., method  200 ) of forming the same. The diode can include a metallic layer (e.g., metallic layers  116 A- 116 B) disposed on a semiconductor substrate. In some embodiments, the metallic layer can include a stack of metal silicide nitride layer (e.g., metal silicide nitride layer  138 ) and metal silicide layer (e.g., metal silicide layer  136 ). 
     In some embodiments, the metal silicide layer can be formed by a silicidation process between a metal layer (e.g., metal layer  948 ) and the semiconductor material of the substrate. In some embodiments, a top portion of the metal silicide layer can be converted to the metal silicide nitride layer during a surface treatment process of the metallic layer performed simultaneously with the silicidation process. The surface treatment process can include introducing nitrogen atoms to the metallic layer through a capping layer (e.g., capping layer  1050 ) disposed on the metallic layer. The capping layer can include a metal nitride material (e.g., TiN) and can prevent the oxidation of the metallic layer during the silicidation process. 
     In some embodiments, for the adequate diffusion of nitrogen atoms through the capping layer during the surface treatment process, the metal nitride material of the capping layer is formed with a cubic crystal structure. The cubic packing arrangement of the metal atoms and the nitrogen atoms of the capping layer allows nitrogen gas to flow through the capping layer during the surface treatment process. In some embodiments, the formation of the capping layer with the cubic crystal structure can include forming a layer of metal nitride with a metal to nitrogen concentration ratio ranging from about 1:3 to about 1:4. using a gas mixture of argon and nitrogen-based gas. 
     In some embodiments, the surface current leakage in the diode with the stack of metal silicide nitride layer and metal silicide layer can be reduced by about 10% to about 50% compared to diodes without the metal silicide nitride layers in the metallic layers. 
     In some embodiments, a semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer. 
     In some embodiments, a semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region, The semiconductor device further includes a silicide layer disposed on the array of well regions and within the substrate, a silicide nitride layer disposed on the substrate, and a contact structure disposed on the silicide nitride layer. 
     In some embodiments, a method includes forming a first well region with a first type of dopants within a substrate and forming an array of well regions with a second type of dopants within the first well region. The second type of dopants is different from the first type of dopants. The method further includes forming a metal silicide layer on the array of well regions and within the substrate, forming a metal silicide nitride layer on the metal silicide layer and within the substrate, and forming a contact structure on the metal silicide nitride layer. 
     The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out forming a contact structure on the metal silicide nitride layer the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.