Patent Publication Number: US-2015069838-A1

Title: Integrated Switch-Capacitor DC-DC Converter and Method Thereof

Description:
This application is a continuation application of U.S. application Ser. No. 13/426,720, filed Mar. 22, 2012, the subject matter of which is incorporated herein by reference. 
    
    
     FIELD OF INVENTION 
     This present invention generally relates to DC-DC converters and more particularly to integrated switch-capacitor DC-DC converters. 
     BACKGROUND 
     A conventional DC-DC converter receives a first DC voltage from a power supply and outputs a second DC voltage to a load circuit. There are generally two types of DC-DC converters: switching regulators and linear regulators. Switching regulators are more power efficient but require large external passive components (inductors and capacitors) and therefore not cost/size effective for mixed-signal SoC (Systems on Chips) applications that require multiple independent power supply domains for various circuits. Also, switching regulators are often noisy due to switching. Linear regulators, on the other hand, are more cost/size effective and less noisy, but are not power efficient. 
     Accordingly, what is desired are DC-DC converters that are approximately as cost/size effective and clean as linear regulators, but also more power efficient, like switching regulators. 
     SUMMARY 
     In an embodiment, an apparatus comprises: a switch-capacitor network for receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1; a load capacitor for holding the load voltage; a feedback network for generating a feedback voltage proportional to the load voltage; and a controller for receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks. The switch-capacitor network comprises a parallel connection of N switch units, wherein each switch unit includes a charging capacitor for receiving a charge from the source voltage and sharing the charge with the load voltage in a manner controlled by a respective bit of the N-bit control code and a respective phase of the plurality of phase clocks. The controller outputs the N-bit control code so that in a steady state the number of bits of the N-bit control bits that are asserted is steady yet each individual bit of the N-bit control code toggles often. 
     In another embodiment, a method comprises: receiving a source voltage; receiving a reference voltage; receiving a plurality of phase clocks comprising a plurality of clock phases; coupling a load circuit to a load node; holding a load voltage at the load node with a load capacitor; deriving a feedback voltage from the load voltage such that the feedback voltage is proportional to the load voltage; updating a N-bit control code in response to a comparison between the feedback voltage and the reference voltage in a timely manner controlled by one of the plurality of clock phases; and transferring charge from the source voltage to the load voltage via a switch-capacitor network controlled by the plurality of phase clocks and the N-bit control code. The switch-capacitor network comprises a parallel connection of N switch units, wherein each switch unit includes a charging capacitor for receiving a charge from the source voltage and sharing the charge with the load voltage in a manner controlled by a respective bit of the N-bit control code and a respective phase of the plurality of phase clocks. The N-bit control code is updated so that in a steady state the number of bits of the N-bit control bits that are asserted is steady yet each individual bit of the N-bit control code toggles frequently. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a functional block diagram of a switch-capacitor DC-DC converter in accordance with an embodiment of the present invention. 
         FIG. 2  shows an exemplary timing diagram of a multi-phase clock for the converter of  FIG. 1 . 
         FIG. 3  shows a functional block diagram of a switch-capacitor network for the converter of  FIG. 1 . 
         FIG. 4  shows a schematic diagram of a switch unit for the switch-capacitor network of  FIG. 3 . 
         FIG. 5  shows a controller for the converter of  FIG. 1   
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description refers to the accompanying drawings which show, by way of illustration, various embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense. 
     A functional block diagram of a switch-capacitor DC-DC converter  100  in accordance with the present invention is depicted in  FIG. 1 . Converter  100  receives a source voltage V S  and outputs a load voltage V L  to a load circuit  120 . Converter  100  comprises: a switch-capacitor network  110  for receiving the source voltage V S  and outputting the load voltage V L  in accordance with a N-bit control code CC[N−1:0] and a N-phase clock CLK[N−1:0], where N is an integer greater than 1; a load circuit  120  as a termination to the load voltage V L ; a load capacitor C L  for holding the load voltage V L ; a feedback circuit  130  for receiving the load voltage V L  and outputting a feedback voltage V FB ; a controller  140  for receiving the feedback voltage V FB  and a reference voltage V REF  and outputting said N-bit control code CC[N−1:0] in accordance with a first phase CLK[0] of said N-phase clock CLK[N−1:0]. The feedback circuit  130  is embodied by a resistive voltage divider comprising two resistor R 1  and R 2 , so that V FB =V L ·R 2 /(R 1 +R 2 ). In a closed-loop manner, the controller  140  outputs the N-bit control code CC[N−1:0] to control the switch-capacitor network  110  so as to make the feedback voltage V FB  track the reference voltage V REF , and therefore the load voltage V L  track V REF ·(1+R 1 /R 2 ). 
     The N-phase clock CLK[N−1:0] comprises N phases that are uniformed displaced in time, with a spacing of T/N between two adjacent phases, where T is a clock period. An exemplary timing diagram of the N-phase CLK[N−1:0] for N=8 is shown in  FIG. 2 . 
     An exemplary embodiment of a switch-capacitor network  300  suitable for embodying switch-capacitor network  110  of  FIG. 1  is shown in  FIG. 3 . Switch-capacitor network  300  comprises a parallel connection of N switch units  301 ,  302 ,  303 , . . . , and  304 ; each switch unit couples to the source voltage V S  on the source side and to the load voltage V L  on the load side in accordance with a respective bit of the control code CC[n] and a respective clock phase CLK[n], for n=0, 1, 2, . . . , and N−1; each switch unit works in a two-phase switch-capacitor manner to transfer charge from the source side to the load side.  FIG. 4  depicts a schematic diagram of a switch unit  400  suitable for embodying switch units  301 ,  302 ,  303 , . . . , and  304  of  FIG. 3 . Switch unit  400  couples to the source voltage V S  on the source side and to the load voltage V L  on the load side in accordance with the respective bit of the control code CC[n] and the clock phase CLK[n], where n=0, 1, 2, . . . , N−1 for embodying switch units  301 ,  302 ,  303 , . . . , and  304 , respectively. Switch unit  400  comprises a charging capacitor C CH , a first switch  401  controlled by a first logical signal PHI 1 , and a second switch  402  controlled by a second logical signal PHI 2 . The first logical signal PHI 1  and the second logical signal PHI 2  form a non-overlapping two-phase clock, where PHI 1  and PHI 2  are never concurrently asserted; in a charging phase wherein PHI 1  is asserted, the charging capacitor C CH  is charged by the source voltage (i.e. V S ) via the first switch  401 ; in a sharing phase wherein PHI 2  is asserted, the charge on the charging capacitor C CH  is shared with the load voltage (i.e. V L ) via the second switch  402 . Switch unit  400  further comprises a clock gating circuit  430  for gating the clock signal CLK[n] in accordance with the respective bit of the control code CC[n], resulting in a gated clock CLKG; and a two-phase non-overlapping clock generator  420  for receiving the gated clock CLKG and outputting the non-overlapping two-phase clock (i.e., PHI 1  and PHI 2 ). 
     The clock gating circuit  430  comprises: a data flip flop (DFF)  431  for sampling the respective bit of the control code CC[n] with the clock signal CLK[n], resulting in a synchronized control signal ENS; an inverter  432  for receiving the clock signal CLK[n] and outputting an inverted clock signal CLKB; and a NAND gate  433  for receiving the synchronized control signal ENS and the inverted clock signal CLKB and outputting the gated clock signal CLKG. The two-phase non-overlapping clock generator  420  comprises inverters  421 ,  424 ,  425 ,  426 , and  427 , and NOR gates  422  and  423 . The two-phase non-overlapping clock generator  420  is well known in prior art and thus there is no need to be explained in detail here. By using the combination of the clock gating circuit  430  and the two-phase non-overlapping clock generator  420 , the charge on the charging capacitor C CH  will be shared with the load in accordance with a timing determined by the clock signal CLK[n] when the respective bit of the control code CC[n] is asserted. 
     Referring back to  FIG. 3 , each switch unit ( 301 - 304 ) has a respective clock signal CLK[n] and a respective bit of the control code CC[n] (for n=0, 1, 2, . . . , and N−1). Within each switch unit, there is a charging capacitor and a pair of switches (see  FIG. 4 ) controlled by a respective two-phase non-overlapping clock. The charging capacitor receives charge from the source voltage V S , and shares the charge with the load voltage V L  in a timing determined by the respective clock phase CLK[n] when the respective bit of the control code CC[n] is asserted. For each individual switch unit, the more often the respective bit of the control code CC[n] is asserted, the more the charge received from the source is transferred to the load and therefore the higher the load voltage V L  will be. For the switch network  300  as a whole, the more bits of the control code CC[N−1:0] are asserted, the more total charge is transferred to the load. 
     Referring back to  FIG. 1 , controller  140  controls the control code CC[N−1:0] so as to make the feedback voltage V FB  track the reference voltage V REF . If V FB  is lower than V REF , more bits of the control code CC[N−1:0] will be asserted to help to raise the load voltage V L  (and accordingly raise the feedback voltage V FB ). Otherwise, fewer bits of the control code CC[N−1:0] will be asserted to help to lower the load voltage V L  (and accordingly lower the feedback voltage V FB ). In a steady state, the feedback voltage V FB  is approximately equal to the reference voltage V REF , and the number of bits of the N-bit control code CC[N−1:0] that are asserted is steady (i.e., either fixed or slightly fluctuating). 
       FIG. 5  depicts a functional block diagram of a controller  500  suitable for embodying controller  140  of  FIG. 1 . Controller  500  comprises: a comparator (CMP)  501  for comparing the reference voltage V REF  with the feedback voltage V FB  and outputting a decision D; a low pass filter (LPF)  502  for receiving the decision D and outputting a first intermediate word W 1 ; a round operator  503  for receiving the first intermediate word W 1  and outputting a second intermediate word W 2 ; a thermometer-code encoder  504  for receiving the second intermediate word W 2  and outputting a N-bit primitive control code PCC[N−1:0]; and a dynamic element matching (DEM) block  505  for receiving the primitive control code PCC[N−1:0] and outputting the control code CC[N−1:0]. The decision D is set to 1 when the reference voltage V REF  is higher than the feedback voltage V FB ; otherwise, the decision D is set to −1. In an embodiment, LPF  502  comprises an integrator for integrating the decision D into the first intermediate word W 1  of word length N1. The round operator  503  rounds the first intermediate word W 1  into the second intermediate word W 2  of word length N2 by keeping only the N2 most significant bits, where N2&lt;N1. The thermometer-code encoder  504  encodes the second intermediate word W 2  into the primitive control code PCC[N−1:0] of word length N. By definition of thermometer code, PCC[n] is 1 for n&lt;W 2  and is 0 otherwise. DEM  50  maps the primitive control code PCC[N−1:0] into the control code CC[N−1:0] so that the number of bits being asserted are preserved yet the mapping is dynamic. For instance, if N=8, W 2 =4, then PCC[7:0]=00001111; in this case, CC[7:0] can be 01010101, or 10101010, or 01101010, or 10011010, and so on. 
     Preferably, the mapping is dynamic so as to make each bit of the N-bit control code CC[N−1:0] toggle often; this makes the voltage ripple at the load caused by the charge sharing of the corresponding charging capacitor within the switch-capacitor network  110  of  FIG. 1  appear to be high-frequency noise that can be readily filtered by the load capacitor C L . As a result, the overall voltage ripple at the load is spectrally shaped to high frequencies and effectively filtered by the load capacitor C L . 
     An example of dynamic element matching is taught in U.S. Pat. No. 5,684,482, and the principle of spectral shaping is explained therein and thus not described in detail here. In a steady state, the feedback voltage V FB  is approximately equal to the reference voltage V REF , the N-bit primitive control code PCC[N−1:0] is steady (i.e., either fixed or slightly fluctuating), and the number of bits of the N-bit control code CC[N−1:0] that are asserted is also steady (i.e., either fixed or slightly fluctuating), yet each individual bit of the N-bit control code toggles rather often as a result of using a dynamic element matching. 
     Referring again to  FIG. 1 , due to using multi-phase clocking and multiple charging capacitors within the switch-capacitor network  110 , the charging-sharing function of the switch network  110  is gradual and smooth, compared with using a simple switch-capacitor circuit. The more clock phases, the smother it is; however, this comes at the cost of higher hardware complexity. Due to using dynamic element matching in the controller  140 , the control code is scrambled and the switching noises are spectrally shaped to high frequencies and can be effectively filtered by the switch-capacitor network formed by the switch-capacitor network  110  and the load capacitor C L . In an embodiment, the load capacitor C L  is an external component while the rest of the converter  100  of  FIG. 1  is integrated in a single chip. In another embodiment, the entire converter  100  is fully integrated in a single chip. 
     By integrating all circuits (or all but the load capacitor C L ) into a single chip without using external inductor, converter  100  is cost/size effective. Due to using switch-capacitors without static biasing, converter  100  is power efficient. Due to using multi-phase charge sharing along with dynamic element matching, the noise in the load voltage is small. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations and variations of the embodiments discussed herein. Various embodiments use permutations and/or combinations of embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description.