Patent Publication Number: US-7710806-B2

Title: Memory device and method for improving speed at which data is read from non-volatile memory

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims foreign priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2005-0067060, filed on Jul. 23, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present disclosure relates to a memory device, and more particularly, to a memory device and method for improving a speed at which data is read from non-volatile memory. 
   2. Description of the Related Art 
   Electrically erasable programmable read-only memory (EEPROM) is widely used as a non-volatile data storage device such as a smart card or an integrated circuit card. 
     FIG. 1  is a block diagram of a conventional memory device  10 . Referring to  FIG. 1 , the memory device  10  includes a memory cell array  20 , a control circuit  30 , a high-voltage generator  40 , a row decoder  60 , and a column decoder  70 . 
   The memory cell array  20  includes a plurality of non-volatile memory cells  21 - 1  through  21 - 12  connected between word lines WL_A, WL_B, and WL_C and bit lines BL 1 , BL 2 , BL 3 , and BL 4 . As is well known to those of ordinary skill in the pertinent art, each of the plurality of non-volatile memory cells  21 - 1  through  21 - 12  includes a selection transistor  23  and an EEPROM cell  25 . 
   The control circuit  30  controls the operation of the high-voltage generator  40  in response to a clock signal CLK, a read control signal READ, an erase control signal ERASE, and a program control signal PROG, which are received from a memory controller (not shown). 
   The high-voltage generator  40  is controlled by the control circuit  30  to generate a predetermined high voltage needed to program or erase data to or from each of the non-volatile memory cells  21 - 1  through  21 - 12  and a predetermined high voltage needed to read data from each of the non-volatile memory cells  21 - 1  through  21 - 12 . 
   The row decoder  60  enables a high voltage generated by the high-voltage generator  40  to one among the word lines WL_A, WL_B, and WL_C in response to an address ADD. The column decoder  70  selects one among the bit lines BL 1 , BL 2 , BL 3 , and BL 4  in response to the address ADD. 
     FIG. 2  is a timing diagram of a read operation of the memory device  10  illustrated in  FIG. 1 . Referring to  FIGS. 1 and 2 , in a data read operation, the word line WL_A or WL_C is selected in response to the address ADD, a voltage of the selected word line WL_A or WL_C increases from a ground voltage (VSS) to a read voltage or a power supply voltage (VDD). Accordingly, data stored in EEPROM cells  21 - 1  through  21 - 4  or  21 - 9  through  21 - 12  corresponding to the word line WL_A or WL_C are transmitted to the corresponding bit lines BL 1  through BL 4 , respectively. 
   Since the plurality of EEPROM cells  21 - 1  through  21 - 4  or  21 - 9  through  21 - 12  are connected to the selected word line WL_A or WL_C and parasitic capacitance is present in the selected word line WL_A or WL_C, it takes a long time T 1  to increase the voltage from the ground voltage VSS to the power supply voltage VDD. As a result, it takes the long time T 1  to read data from the EEPROM cells  21 - 1  through  21 - 4  or  21 - 9  through  21 - 12  of the selected word line WL_A or WL_C. 
   SUMMARY OF THE INVENTION 
   The present disclosure provides a memory device and method for improving a speed at which data is read from non-volatile memory without increasing voltage or voltage driving ability of a word line. 
   According to an aspect of the present disclosure, there is provided a memory device including non-volatile memory. The memory device precharges all word lines with a predetermined precharge voltage during standby for a read operation, in which data is read from the non-volatile memory, and then, during the read operation, pulls up a voltage of only a word line selected by a row address to a read voltage and pulls down a voltage of remaining unselected word lines down to a ground voltage. 
   According to another aspect of the present disclosure, there is provided a memory device including a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines, respectively; a row decoder comprising a plurality of output terminals connected to the plurality of word lines, respectively; a voltage generator generating a precharge voltage; and a switching block supplying the precharge voltage to at least one among the plurality of word lines in response to a control signal. 
   According to still another aspect of the present disclosure, there is provided a memory device including a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines, respectively, at least one switching circuit switching in response to a control signal, and a row decoder supplying a read voltage to a word line selected among the plurality of word lines in response to a row address, wherein the at least one switching circuit supplies a precharge voltage to at least one word line among the plurality of word lines in response to the control signal. 
   According to yet another aspect of the present disclosure, there is provided a memory device including a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines, a plurality of switching circuits each connected to at least one word line to switch in response to a control signal, and a plurality of row decoders connected to the plurality of word lines, respectively, wherein each of the plurality of switching circuits precharges the corresponding at least one word line with a precharge voltage in response to the control signal, and each of the plurality of row decoders supplies a read voltage to a word line selected among the plurality of word lines in response to a row address corresponding to the word line. 
   The precharge voltage may be equal to the read voltage or half of the read voltage. Each of the plurality of switching circuits may be a transmission gate that switches in response to the control signal. 
   According to a further aspect of the present disclosure, there is provided a memory device including a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines; a row decoder comprising a plurality of output terminals connected to the plurality of word lines, respectively; and a voltage generator generating a precharge voltage and a read voltage, wherein the row decoder precharges the plurality of word lines with the precharge voltage during standby for a read operation and drives the read voltage to a word line selected by a row address and drives a ground voltage to unselected word lines during the read operation. 
   According to another aspect of the present disclosure, there is provided a method of driving a word line to read data. The method includes precharging at least one word line among a plurality of word lines in response to a control signal before a data read operation, driving a read voltage to the selected word line in response to a row address, and driving a ground voltage to remaining unselected word lines during the data read operation. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which: 
       FIG. 1  is a block diagram of a conventional memory device; 
       FIG. 2  is a timing diagram of a read operation of the memory device illustrated in  FIG. 1 ; 
       FIG. 3  is a block diagram of a memory device according to an embodiment of the present disclosure; 
       FIG. 4  is a block diagram of a memory device according to another embodiment of the present disclosure; 
       FIG. 5  is a timing diagram of a read operation of the memory devices illustrated in  FIGS. 3 and 4 ; and 
       FIG. 6  is a flowchart of a method of driving a word line to read data, according to an embodiment of the present disclosure. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The attached drawings for illustrating preferred embodiments of the present disclosure are referred to in order to gain a sufficient understanding of the present disclosure, the merits thereof, and the advantages attained by the implementation of embodiments of the present disclosure. 
   Hereinafter, the present disclosure will be described in detail by explaining preferred embodiments with reference to the attached drawings. Like reference numerals in the drawings may denote like elements. 
     FIG. 3  is a block diagram of a memory device  100  according to an embodiment of the present disclosure. Referring to  FIG. 3 , the memory device or semiconductor chip  100  includes a memory cell array  110 , a switching block  130 , a control circuit  140 , a high-voltage generator  150 , a row decoder  170 , and a column decoder  180 . 
   The memory cell array  110  includes a plurality of non-volatile memory cells  111 - 1  through  111 - 16  connected between word lines WL 1 , WL 2 , WL 3 , . . . , and WL n  (where “n” is a natural number) and bit lines BL 1 , BL 2 , BL 3 , . . . , and BL m  (where “m” is a natural number). Each of the plurality of non-volatile memory cells  111 - 1  through  111 - 16  includes an EEPROM cell  112  and a selection transistor  113 . 
   The switching block  130  includes a plurality of switching circuits  131 - 1 ,  131 - 2 ,  131 - 3 , . . . , and  131 - n . During standby for a read operation, the switching circuits  131 - 1 ,  131 - 2 ,  131 - 3 , . . . , and  131 - n  supply a precharge voltage (e.g., 0.5 VDD) to the corresponding word lines WL 1 , WL 2 , WL 3 , . . . , and WL n , respectively, in response to a control signal S. The switching circuits  131 - 1 ,  131 - 2 ,  131 - 3 , . . . , and  131 - n  supply the precharge voltage to the word lines WL 1 , WL 2 , WL 3 , . . . , and WL n  in one-to-one correspondence, but the present invention is not restricted thereto. For example, one switching circuit  131 - 1  may simultaneously drive a plurality of word lines WL 1  through WL 3 . Each of the switching circuits  131 - 1 ,  131 - 2 ,  131 - 3 , . . . , and  131 - n  is implemented as a transmission gate including a PMOS transistor and an NMOS transistor. 
   The control circuit  140  controls the operation of the high-voltage generator  150  in response to a clock signal CLK, a read control signal READ, an erase control signal ERASE, and a program control signal PROG, which are received from a memory controller. In addition, the control circuit  140  generates the control signal S to control the operation of the switching block  130  in response to the read control signal READ. 
   The high-voltage generator  150  is controlled by the control circuit  140  to generate a predetermined high voltage needed to program or erase data to or from each of the non-volatile memory cells  111 - 1  through  111 - 16 , a predetermined high voltage needed to read data from each of the non-volatile memory cells  111 - 1  through  111 - 16 , and a voltage (e.g., a read voltage of 0.5 VDD) supplied to the switching block  130 . 
   The high-voltage generator  150  shown in  FIG. 3  generates the voltage such as 0.5 VDD supplied to the switching block  130  in addition to the predetermined high voltages, but the present invention is not restricted thereto. The voltage such as 0.5 VDD supplied to the switching block  130  may be generated by a separate voltage generator. 
   The row decoder  170  enables the high voltage generated by the high-voltage generator  150  to one word line among the word lines WL 1  through WL n  in response to an address ADD. For example, during the read operation, the row decoder  170  drives one word line that is selected among the word lines WL 1  through WL n  by the address ADD with a read voltage (VDD). The column decoder  180  selects one among the bit lines BL 1  through BL m  in response to the address signal ADD. 
     FIG. 4  is a block diagram of a memory device  200  according to another embodiment of the present disclosure. The memory device  200  shown in  FIG. 4  has about the same structure as memory device  100  shown in  FIG. 3 , with the exception of a switching block  210  and a high-voltage generator  220 . 
   The row decoder  170  includes a plurality of unit row decoders  171 - 1  through  171 - n . The unit row decoders  171 - 1  through  171 - n  apply a read voltage generated by the high-voltage generator  220  to the corresponding word lines WL 1  through WL n , respectively. 
   The switching block  210  includes a plurality of switching circuits  211 - 1  through  211 - n  which precharge the corresponding word lines WL 1  through WL n , respectively, with a precharge voltage (e.g., VDD or 0.5 VDD) in response to the control signal S. Alternatively, a single switching circuit included in the switching block  210  may simultaneously precharge a plurality of word lines with the precharge voltage such as VDD or 0.5 VDD. 
   The high-voltage generator  220  is controlled by the control circuit  140  to generate a high voltage needed for a program operation, a high voltage needed for an erase operation, a high voltage (e.g., VDD) needed for a data read operation, and a precharge voltage (e.g., VDD or ½ VDD) used to precharge at least one word line among the word lines WL 1  through WL n  during standby for the data read operation. 
     FIG. 5  is a timing diagram of a read operation of the memory devices illustrated in  FIGS. 3 and 4 . The read operation of a memory device of the present disclosure will be described with reference to  FIGS. 3 through 5  below. 
   The control circuit  140  enables the control signal S, i.e., a word line precharge control signal in response to the read control signal READ. The high-voltage generator  150  is controlled by the control circuit  140  to generate a read voltage (e.g., VDD) needed for the read operation and a precharge voltage (e.g., 0.5 VDD) needed to precharge at least one among the word lines WL 1  through WL n.    
   The switching circuits  131 - 1  through  131 - n  in the switching block  130  precharge the word lines WL 1  through WL n , respectively, with the precharge voltage such as 0.5 or ½ VDD in response to the control signal S. 
   The row decoder  170  supplies the read voltage VDD generated by the high-voltage generator  150  to the word line WL 1  in response to the address ADD for selecting the word line WL 1 . Then, a voltage of the word line WL 1  increases from the precharge voltage of 0.5 VDD to the read voltage VDD, and a voltage of the remaining word lines WL 2  through WL n  decreases from the precharge voltage of 0.5 VDD to a ground voltage (VSS). 
   In addition, when the row decoder  170  supplies the read voltage VDD to the word line WL 3  in response to the address ADD for selecting the word line WL 3 , a voltage of the word line WL 3  increases from the precharge voltage of 0.5 VDD to the read voltage VDD and a voltage of the remaining word lines WL 1 , WL 2 , and WL 4  through WL n  decreases from the precharge voltage of 0.5 VDD to the ground voltage VSS. 
   Since the memory devices  100  and  200  according to embodiments of the present disclosure precharge all of the word lines WL 1  through WL n  with the precharge voltage, such as the read voltage or half of the read voltage, during the standby for the data read operation, a time T 2  taken to increase the precharge voltage to the read voltage in the data read operation according to an embodiment of the present disclosure is theoretically reduced by half as compared to the time T 1  taken to increase the ground voltage VSS to the read voltage VDD in conventional technology. Accordingly, a data reading speed of the memory device  100  or  200  according to an embodiment of the present disclosure is much faster than that of the conventional memory device  10 . 
     FIG. 6  is a flowchart of a method of driving a word line to read data, according to an embodiment of the present disclosure. Referring to  FIGS. 3 through 6 , in operation S 610 , the memory device  100  or  200  precharges all of the word lines WL 1  through WL n  with the precharge voltage (e.g., VDD or ½ VDD), before a read operation or during standby for the read operation, in a procedure of performing the read operation. 
   In operation S 620 , the row decoder  170  or  230  enables the read voltage (VDD) to a word line selected by the address ADD and enables the ground voltage (VSS) to all of unselected word lines. In another embodiment, the row decoder  170  may precharge all of the word lines WL 1  through WL n  with the precharge voltage (e.g., VDD or ½ VDD) during the standby for the read operation and then may enable the read voltage (VDD) to a word line selected by the address signal ADD and enable the ground voltage (VSS) to all of unselected word lines. As described above, according to the present disclosure, a speed at which data is read from non-volatile memory is improved without increasing the performance of word lines enabling a voltage. 
   While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the pertinent art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.