Patent Publication Number: US-2011049580-A1

Title: Hybrid Packaged Gate Controlled Semiconductor Switching Device Using GaN MESFET

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is related to the following patent applications that are incorporated herein by reference for any and all proposes: 
     U.S. application Ser. No. 11/830,951 entitled “A Multi-die DC-DC Boost Power Converter with Efficient Packaging” by Francois Hebert et al with filing date of Jul. 31, 2007, hereinafter referred to as U.S. Ser. No. 11/830,951. 
     U.S. application Ser. No. 11/830,996 entitled “A Multi-die DC-DC Buck Power Converter with Efficient Packaging” by Francois Hebert et al with filing date of Jul. 31, 2007, hereinafter referred to as U.S. Ser. No. 11/830,996. 
     U.S. application Ser. No. 12/391,251 entitled “Compact Power Semiconductor Package and Method with Stacked Inductor and Integrated Circuit Die” by Tao Feng et al with filing date of Feb. 23, 2009, hereinafter referred to as U.S. Ser. No. 12/391,251. 
     U.S. application Ser. No. 12/397,473 entitled “Compact Inductive Power Electronics Package” by Tao Feng et al with filing date of Mar. 4, 2009, hereinafter referred to as U.S. Ser. No. 12/397,473. 
    
    
     FIELD OF INVENTION 
     This invention relates generally to the field of electrical circuit. More specifically, the present invention is directed to the physical level packaging of an electrical switching circuit. 
     BACKGROUND OF THE INVENTION 
     In addition to a technically sound basic circuit design, modern day electronics frequently demand high quality and efficient packaging at the physical level. This is especially so in portable applications where compact package size, low EMI/RFI (electromagnetic interference/radio frequency interference) and flexibility of system configuration are all highly important considerations. 
     U.S. Pat. No. 5,396,085 entitled “Silicon carbide switching device with rectifying-gate” by Baliga, hereinafter referred to as U.S. Pat. No. 5,396,085, disclosed a silicon carbide switching device that includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For convenience,  FIG. 5A ,  FIG. 5B ,  FIG. 6  and  FIG. 7  of U.S. Pat. No. 5,396,085 are reproduced herein respectively as FIG. A 1 , FIG. A 2 , FIG. B 1  and FIG. B 2 . 
     Thus, FIG. A 1  schematically illustrates an electrical schematic of a three-terminal silicon carbide switching device with rectifying-gate  10 . The three-terminal switching device  10  comprises an insulated-gate field effect transistor  12  (shown as a Si MOSFET) having a first source region  14 , a first drain region  16  and an insulated-gate electrode  18 . The insulated gate field effect transistor  12  is preferably an enhancement-mode device which is nonconductive at zero potential gate bias (shown by dotted lines). Accordingly, conduction in the transistor  12  typically requires the formation of an inversion layer channel in the transistor&#39;s active region. Alternatively, the transistor  12  may also be an ACCU-FET, which is preferably designed to be nonconductive at zero potential gate bias. A rectifying-gate field effect transistor  22  (shown as a SiC MESFET), having a second source region  24 , a second drain region  26  and a rectifying-gate electrode  28  is also provided, connected to the insulated-gate field effect transistor  12 , as shown. Source and drain contacts  20  and  30 , respectively, are also provided. Accordingly, electrical connection to the three terminal device is provided by the insulated-gate electrode  18 , the source contact  20  and the drain contact  30 . FIG. A 2  schematically illustrates a three-terminal silicon carbide switching device with rectifying-gate  10 ′. The three-terminal switching device  10 ′ comprises a rectifying-gate field effect transistor  22 ′ (shown as a SiC JFET), having a second source region  24 ′, a second drain region  26 ′ and a rectifying-gate electrode  28 ′, connected to the insulated-gate field effect transistor  12 , as shown. 
     To facilitate the formation of the three-terminal switching devices  10  and  10 ′ of FIG. A 1  and FIG. A 2 , a composite semiconductor substrate  48  having regions of both SiC and Si may be used. In particular, FIG. B 1  and FIG. B 2  are respectively cross-sectional representations of the switching devices of FIG. A 1  and FIG. A 2  using the composite semiconductor substrate  48 . 
     It is remarked that, with the composite substrate of silicon and silicon carbide, the flexibility of device structural configuration of both switching devices  10  and  10 ′ can be constrained by materials and process compatibility at the silicon-silicon carbide interface. This constraint can be exacerbated by the demand of an overall compact package size of the switching devices  10  and  10 ′. Another concern associated with the silicon-silicon carbide composite substrate is the potential of increased device leakage current due to molecular level structural defects at the silicon-silicon carbide interface. It is therefore desirable to develop alternative packaging schemes for the three-terminal switching devices to avoid these constraint and concern while keeping the overall package compact. 
     SUMMARY OF THE INVENTION 
     A hybrid packaged 3-terminal gate controlled semiconductor switching device (HPSD) is proposed. The HPSD has an interconnected insulated-gate transistor (IGT) made of a first semiconductor die and a rectifying-gate transistor (RGT) made of a second semiconductor die located atop an electrically insulating substrate (EIS). The RGT device terminal electrodes are located at front surface of the second semiconductor die with the RGT gate electrode and source electrode electrically connected to the IGT source electrode and drain electrode respectively. The HPSD includes:
         A package base having numerous package terminals for interconnecting the HPSD to its external environment.   The IGT die bonded atop the package base.   A RGT die located atop an electrically insulating substrate (EIS) upon which a composite semiconductor epitaxial layer is formed for the fabrication of the RGT device. In turn, the RGT die is stacked and bonded atop the IGT die via the EIS.   A variety of interconnectors for interconnecting the IGT die, the RGT die and the package terminals.       

     As a result, the HPSD becomes a stacked package of IGT die and RGT die with reduced package footprint while allowing larger die sizes and flexible placements of device terminal electrodes on the IGT die. 
     In a more specific embodiment, the IGT is an enhancement mode Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). 
     In a particular device structural configuration, the enhancement mode MOSFET is a bottom drain MOSFET with its drain electrode located on its bottom surface but its source and gate electrodes located on its top surface. 
     More specifically, the package base can be made of a leadframe, a multi-layer circuit laminate or a chip-on-lead package and the bottom drain MOSFET die can be flip-chip bonded onto the chip-on-lead package. 
     In another particular device structural configuration, the enhancement mode MOSFET is a bottom source MOSFET with its source electrode located on its bottom surface but its gate and drain electrodes located on its top surface. 
     In a more specific embodiment, the RGT is a depletion mode metal semiconductor field effect transistor (MESFET). 
     In a more specific embodiment, the first semiconductor die is made of silicon (Si), germanium (Ge), gallium arsenide (GaAs) or silicon-germanium (SiGe) and the second semiconductor die is made of gallium nitride (GaN). 
     In a more specific embodiment, the EIS is sapphire, diamond, zinc oxide (ZnO), aluminum nitride (AlN) or semi-insulating SiC. When the EIS is sapphire the GaN can be grown on the EIS. 
     In a more detailed embodiment, the RGT die can be bonded atop the IGT die via die attach using insulating epoxy or non-insulating epoxy. 
     In a more detailed embodiment, the RGT die further includes an evaporated back metal and the RGT die can be bonded atop the IGT die via die attach using solder. 
     These aspects of the present invention and their numerous embodiments are further made apparent, in the remainder of the present description, to those of ordinary skill in the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to more fully describe numerous embodiments of the present invention, reference is made to the accompanying drawings. However, these drawings are not to be considered limitations in the scope of the invention, but are merely illustrative. 
       FIG. A 1  illustrates an electrical schematic of a first three-terminal silicon carbide switching device with rectifying-gate of the prior art U.S. Pat. No. 5,396,085; 
       FIG. B 1  is the cross-sectional representation of the switching device of FIG. A 1  using a composite semiconductor substrate; 
       FIG. A 2  illustrates an electrical schematic of a second three-terminal silicon carbide switching device with rectifying-gate of the prior art U.S. Pat. No. 5,396,085; 
       FIG. B 2  is the cross-sectional representation of the switching device of FIG. A 2  using a composite semiconductor substrate; 
         FIG. 1  is a perspective illustration of a rectifying-gate transistor die of the present invention; 
         FIG. 2A  is a perspective illustration of a first device structural configuration of a hybrid packaged 3-terminal gate controlled semiconductor switching device under the present invention; and 
         FIG. 2B  is a perspective illustration of a second device structural configuration of a hybrid packaged 3-terminal gate controlled semiconductor switching device under the present invention. 
     
    
    
     DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS 
     The description above and below plus the drawings contained herein merely focus on one or more currently preferred embodiments of the present invention and also describe some exemplary optional features and/or alternative embodiments. The description and drawings are presented for the purpose of illustration and, as such, are not limitations of the present invention. Thus, those of ordinary skill in the art would readily recognize variations, modifications, and alternatives. Such variations, modifications and alternatives should be understood to be also within the scope of the present invention. 
       FIG. 1  together with  FIG. 2A  are perspective illustrations of a first device structural configuration of a hybrid packaged  3 -terminal gate controlled semiconductor switching device (HPSD)  50 , together with a rectifying-gate transistor (RGT) die  10 , under the present invention. 
     The HPSD  50  has a package base that, in this case, includes numerous leadframe sections  30   a,    30   b,    30   c  and  30   d.  Each of the leadframe sections  30   b,    30   c  and  30   d  has a plurality of package terminals for interconnecting the HPSD  50  to its external environment. Bonded atop the package base (leadframe section  30   a ) is a silicon Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) made of a silicon semiconductor die  22  with a silicon semiconductor substrate  22   a.  Thus, the leadframe section  30   a  also acts as the main heat sink of the HPSD  50 . In particular, the silicon MOSFET can be an enhancement mode vertical MOSFET. A GaN (gallium nitride) Metal-Semiconductor Field Effect Transistor (MESFET) made of a separate semiconductor die  2  has a GaN semiconductor epitaxial layer  2   a  formed upon a sapphire substrate  1  to create a GaN rectifying-gate transistor (RGT) die  10  ( FIG. 1 ). Owing to materials and process compatibility, the GaN epitaxial layer  2   a  can be grown on the sapphire substrate  1 . In particular, the GaN MESFET can be a depletion mode lateral MESFET. The device terminal electrodes MESFET drain  2   d,  MESFET source  2   s  and MESFET gate  2   g  of the GaN MESFET are all located at its front surface. In this case, the silicon vertical MOSFET is a bottom drain MOSFET with its MOSFET drain  22   d  electrode located on its bottom surface but its MOSFET source  22   s  and MOSFET gate  22   g  electrodes located on its top surface. 
     The RGT die  10  is in turn stacked and bonded, via the sapphire substrate  1 , atop the silicon semiconductor die  22 . As sapphire is an electrically insulating material, bonding of the RGT die  10  atop the silicon semiconductor die  22  can be via die attach using either an insulating epoxy or a non-insulating epoxy. In another embodiment, a metal can be evaporated onto the back side of the RGT die  10  followed by die attaching it atop the silicon semiconductor die  22  using a solder material. In case a semi-insulating material such as SiC is used as the substrate to grow the GaN epitaxial layer, proper insulation between the RGT substrate and the MOSFET die is required. The HPSD  50  also has numerous bonding wires  32 ,  34 ,  36 ,  38  and  40  for electrically interconnecting the silicon MOSFET, the RGT die  10  and the package terminals. Thus, the MESFET gate  2   g  electrode is connected to the MOSFET source  22   s  electrode via bonding wires  38 . The MESFET source  2   s  is connected to the MOSFET drain  22   d  electrode via bonding wires  32 . The MOSFET source  22   s  is connected to the leadframe section  30   b  via bonding wires  34 . The MOSFET gate  22   g  is connected to the leadframe section  30   c  via bonding wires  36 . The MESFET drain  2   d  is connected to the leadframe section  30   d  via bonding wires  40 . As configured, the HPSD  50  constitutes a 3-terminal enhancement mode device (as opposed to a depletion mode device). Being an enhancement mode device is important in that its application environment is compatible with that of the most popular MOSFET which are enhancement mode devices that normally remain off but only turned on upon an applied gate voltage. If so desired, the HPSD  50  can be configured to be compatible with standard pin-outs of the most popular MOSFET as well. 
     The stacked package of silicon semiconductor die  22  and GaN semiconductor die  2  provides the advantages of a reduced HPSD  50  package footprint while allowing larger individual die sizes for a correspondingly reduced drain-source resistance R DS . As a particular example, an R DS  of 1 milliOhm to 2 milliOhm can be achieved for the Si MOSFET and an RDS of 5 milliOhm to 10 milliOhm can be achieved for the GaN MESFET. Additionally, to be presently illustrated, the usage of the electrically insulating sapphire substrate  1  on the RGT die  10  allows flexible placements of device terminal electrodes on the silicon semiconductor die  22 . 
       FIG. 1  together with  FIG. 2B  are perspective illustrations of a second device structural configuration of an HPSD  70 , together with its RGT die  10 , under the present invention. The HPSD  70  has a package base that includes numerous leadframe sections  44   a,    44   b  and  44   c  each having a plurality of package terminals for interconnecting the HPSD  70  to its external environment. Bonded atop the package base (leadframe section  44   a ) is a silicon vertical MOSFET made of a silicon semiconductor die  42  with a silicon semiconductor substrate  42   a.  Thus, the leadframe section  44   a,  which functions as an electric terminal of the package, also acts as the main heat sink of the HPSD  70 . 
     Except for the silicon semiconductor die  42  being a bottom source device with its MOSFET source  42   s  electrode located on its bottom surface and its gate and drain electrodes  42   g  and  42   d  located on its top surface thus isolated from the package base, the rest constituents of the HPSD  70  are similar to those of the HPSD  50 . Thus, the MESFET gate  2   g  electrode is connected to the MOSFET source  42   s  electrode via bonding wires  56 . The MESFET source  2   s  is connected to the MOSFET drain  42   d  electrode via bonding wires  52 . The MOSFET source  42   s  is bonded to the leadframe section  44   a.  The MOSFET gate  42   g  is connected to the leadframe section  44   b  via bonding wires  54 . The MESFET drain  2   d  is connected to the leadframe section  44   c  via bonding wires  58 . 
     While the main switching node (MOSFET drain  22   d ) of the HPSD  50  was electrically shorted to its main heat sink (leadframe section  30   a ), the main switching node (MOSFET drain  42   d ) of the HPSD  70  is electrically isolated from its main heat sink (leadframe section  44   a ). Thus, comparing with the HPSD  50 , the device structural configuration of HPSD  70  provides an advantage of a correspondingly reduced EMI/RFI emission. 
     An HPSD is described under the present invention. While the HPSD has been described using a RGT die  10  with a sapphire substrate  1 , other electrically insulating materials such as diamond, zinc oxide (ZnO), aluminum nitride (AlN), or semi-insulating SiC can be used as the substrate as well. With references made to U.S. Ser. No. 11/830,951, U.S. Ser. No. 11/830,996, U.S. Ser. No. 12/391,251 and U.S. Ser. No. 12/397,473, by now it should become clear to those skilled in the art that the present invention can also be practiced with the following alternatives:
         The package base made of a printed circuit board (PCB).   The package base made of a chip-on-lead package with the bottom drain silicon semiconductor die  22  flip-chip bonded with solder balls onto the chip-on-lead package.   The bonding wires replaced with three dimensionally formed interconnection plates.
 
Additionally, in general the silicon MOSFET can be replaced with a variety of insulated-gate transistors (IGT) made of silicon (Si), germanium (Ge), gallium arsenide (GaAs) or silicon-germanium (SiGe).
       

     While the description above contains many specificities, these specificities should not be constructed as accordingly limiting the scope of the present invention but as merely providing illustrations of numerous presently preferred embodiments of this invention. It will be appreciated by those of ordinary skill in the art that the present invention can be embodied in numerous other specific forms and those of ordinary skill in the art would be able to practice such other embodiments without undue experimentation. The scope of the present invention, for the purpose of the present patent document, is hence not limited merely to the specific exemplary embodiments of the foregoing description, but rather is indicated by the following claims. Any and all modifications that come within the meaning and range of equivalents within the claims are intended to be considered as being embraced within the spirit and scope of the present invention.