Patent Publication Number: US-8981750-B1

Title: Active regulator wake-up time improvement by capacitive regulation

Description:
FIELD OF THE INVENTION 
     This invention pertains generally to the field of voltage regulation circuits and, more particularly, to their wake-up behavior. 
     BACKGROUND 
     Voltage regulators are commonly found as peripheral elements on integrated circuits needing well regulated voltage levels for their operations. For example, a typical NAND memory chip has internal active and standby power supply regulators. During the transition from a standby mode to an active mode, although power supply level (the regulators&#39; output) is initialized to desired level, active regulators tend to suffer from long wake-up times. High RC time constants, associated with the regulator&#39;s feedback loop, delays loop response during wake-up. Furthermore, high load currents can cause the power supply&#39;s output level to droop. This droop can be significantly high. The impact can be seen as a wrong data transfer, which becomes more evident at double data rate (DDR) speeds. 
     SUMMARY OF THE INVENTION 
     According to a general aspect of the invention, a method of operating a voltage regulator circuit to provide an output voltage level on an output node is presented. The regulator circuit includes a pass transistor connected between a supply level and the output node of the voltage regulator circuit and has a gate connected to an output node of an op-amp having first and second inputs, where the first input of the op-amp is connected to receive a reference voltage. The method includes operating the voltage regulator in a standby mode and subsequently operating the voltage regulator circuit in an active mode. In the standby mode the op-amp&#39;s output node is connected to receive the supply level. In the active mode the op-amp&#39;s output node is not connected to receive the supply level, the output node of the voltage regulator circuit is connected to ground through a resistive voltage divider, and the second input of the op-amp is connected to a node of the resistive voltage divider. In transitioning from the standby mode to the active mode, the connection of the second input of the op-amp to the node of the resistive voltage divider is delayed relative to disconnecting of the op-amp&#39;s output node from the supply level and the connecting of the voltage regulator circuit&#39;s output node to ground through the resistive voltage divider. 
     In other aspects, voltage regulation circuitry provides an output voltage level on an output node. The voltage regulation circuitry includes an op-amp and a pass transistor. The op-amp has first and second inputs, where the first input is connected to receive a reference voltage, and an output of the op-amp is connectable to a supply level through a second switch. The pass transistor is connected between the supply level and the output node of the voltage regulator circuitry and having a gate connected to the output node of the op-amp. First and second resistances are connected in series between the voltage regulator circuitry&#39;s output node and, through a third switch, ground, wherein the second input of the op-amp is connectable to a node between the first and second resistances through a fourth switch. First and second capacitors are connected in series between the op-amp&#39;s output node and the second input of the op-amp and having an intermediate node between the first and second capacitors connected to the output node of the voltage regulator circuitry. When operating in a standby mode, the first switch and second switches are on and the third and fourth switches are off; when operating in an active mode, the first and second switches are off and the third and fourth switches are on, and, when transitioning from the standby mode to the active mode, the turning on of the fourth switch is delayed relative to the turning off of the first and second switches and the turning on of the third switch. 
     Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, whose description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of twits between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an example of a voltage regulator circuit. 
         FIG. 2  is a set of waveforms showing the wake-up behavior of the circuit of  FIG. 1 . 
         FIG. 3  shows an exemplary embodiment of a voltage regulator circuit. 
         FIG. 4  is a set of waveforms showing the wake-up behavior of the circuit of  FIG. 3 . 
         FIG. 5  is an equivalent circuit for  FIG. 3  when under capacitive regulation. 
         FIG. 6  is a version of  FIG. 4  for illustrating the behavior when under capacitive regulation. 
         FIG. 7  is a block level representation of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION 
     The following considers techniques for improving the wake-up response of voltage regulators. More specifically, the regulator&#39;s feedback loop response is improved by pushing the active regulator in capacitive feed-back mode only during wake-up. This speeds up the loop response, hence improves wake-up time. 
     For background,  FIG. 1  illustrates an example of a regulator circuit and  FIG. 2  is a set of waveforms to shows its wake-up behavior. In  FIG. 1 , a pass device M P    21  is connected between the supply level V EXT  the regulator&#39;s output node OUT that can be applied to a load, here represented by C L    31 . The gate of M P    21  is connected to output node PPG of an op-amp. The op-amp is here implemented as having its first input connected to the gate of a transistor M 1   11  and its second input connected to the gate of a transistor M 2   13 , where M 1   11  and M 2   13  are both connected to ground though a current source  19  and respectively connected to the supply level through PMOS  15  and PMOS  17 , where the gates of both of these PMOS are connected to a node between M 1   11  and PMOS  15 . The output PPG is then taken from a node between M 2   13  and PMOS  17 . Although this particular implementation of the op-amp is used in all of the following discussion, other standard implementations and variations can be used. 
     The gate of M 2   13  is connected to a reference level V REF , such as would be supplied from a band-gap circuit, for example, and the node MON for the gate of M 1   11  is also connectable (through switch SW 1   41 ) to the reference level or (through switch M SW    47 ) to an intermediate node MONB of a resistive divider formed of R 1   23  and R 2   25  connected in series between OUT and (through a switch SW 3   45 ) to ground. A coupling capacitor C C    27  and a lead capacitor C LEAD    29  are used to increase the stability of the regulator when turned on and are connected in series between PPG and MON, with their intermediate node connected at OUT. PPG is also connectable (through switch SW 2   43 ) to the supply level.  FIG. 1  also shows the parasitic capacitances C MON    53  and C MONB    51 , where C MON  represents device parasitic capacitance and routing capacitance and C MONB  represents device parasitic capacitance, the parasitic capacitance of resistors R 1   23  and R 2   25 , and routing capacitance. 
     In the exemplary embodiment, SW 1   41 , SW  3   45 , and M SW    47  are implemented as NMOS devices and SW 2   43  is implemented as a PMOS device. SW 2   43 , SW  3   45 , and M SW    47  have their gates connected to receive the enable signal EN for the regulator, while SW 1   41  receives the inverse of EN at its gate. Here, EN is the control signal that determines whether the chip is working in standby mode or active mode. Consequently, when EN is low, SW 1   41  and SW 2   43  are on, SW 3   45  and M SW    47  are off; and EN is high, SW 1   41  and SW 2   43  are off, SW 3   45  and M SW    47  are on. The regulator is enabled by EN going high. The regulator here is taken to be an example of an active regulator capable of driving the load when active. For example, a NAND memory chip typically has standby mode and active modes. Active regulators work in the active mode whereas a standby regulator is used in the standby mode to maintain voltage levels, but need not drive the active circuit. The outputs of the regulators can be connected and, depending upon the mode of the chip, either the standby or the active regulator will drive the output. Consequently, only one of the active regulator and standby regulator need to be on at any time, depending on the mode. While still able to maintain a steady supply in standby situations, the standby regulator itself consumes less power and it can deliver less power to the load, whereas the active regulator consumes more power and is capable of driving a high current load. In the exemplary embodiment, the switch SW 1   41  connects the gate of M 1   11  to V REF  during standby; more generally, as the actively regulator is turned off, this input of the op-amp could be any value while off, but connecting it to the reference level allows for faster settling. 
       FIG. 2  shows a corresponding set of control signals for  FIG. 1 . Before turning on the regulator, the regulator EN=0 and the device is in standby mode, with PPG connected to V EXT  and MON connected to V REF . The regulator output is initialized to V DD , where V DD  is the final regulation voltage, by a standby regulator (not shown in  FIG. 1  or  3 ) connectable to OUT. The MONB node is the same as V DD  due to there being no current in the resistive path. After the regulator is on (EN=1), a wake-up process begins as MONB node discharges to V REF . The MONB node has two discharge paths: through R 2   25  to ground and through M SW    47  to C LEAD    29 . The R 2  to ground current path will help in discharging, while M SW  to C LEAD  is an additional current path that is created due to different initial voltages at the MONB and MON nodes. This will make MON node rising above V REF  during the wake period, as shown at the bump. Since the potential at MON node is more than V REF , the current in M 2   13  will be less the current in M 1   11 , slowing the discharge of the PPG node and causing wake-up time to increase. If the load draws current is before the regulator is settled, the OUT droop further increases. Because of this, internal circuits using this supply may fail to respond, resulting in error in data transfer. 
     One way that wake-up time can be reduced by increasing the tail current of the op-amp; however, this increases the power consumption of the circuit. Another way to deal with the problem is to have a separate discharge path for the high capacitive node at the gate of the pass device M P    21 ; but again, this takes extra power and the duration of discharge has to be precisely controlled across process variations. If the discharge is higher than required, an unwanted overshoot will be seen at the regulator output. 
       FIG. 3  presents an exemplary embodiment of a voltage regulator circuit incorporating aspects to improve wake-up response without these drawbacks.  FIG. 3  incorporates the same elements as  FIG. 1 , but also incorporates a delay element τ D    61 . Rather than M SW    47  having its gate connected to receive EN directly, it instead receives a delayed version ENd that the delay element τ D    61  generates from EN. The delay can be implemented by a RC network, where the resistor used in the RC network can be the same as the resistor used in the voltage divider of the regulator. 
       FIG. 4  illustrates the control signals for  FIG. 3 , where the control signals for  FIG. 1  (as shown in  FIG. 2 ) are overlaid in broken lines for comparison. When EN goes high and the active regulator is turned on, the connection of MONB to MON through M SW    47  is delayed by delaying the control signal ENd. While M SW    47  is off, C LEAD    29  completes the feedback path: i.e., the regulator is in capacitive regulation mode. Due to the initial voltages at both the terminals of C LEAD , output node would be regulated to V DD . The wake-up time in capacitive regulation will be faster since any decrease in the OUT node (due to the resistive discharge path and output current) will be entirely reflected in the MON node. The MON node will not overshoot V REF  as in  FIG. 1  and PPG will discharge faster. The delay τ D  is preferably higher than the time required for the MONB node to discharge to V REF  so that the MON node will be unaffected by the discharge of MONB. For example, the MONB node can take, say, five times (R 1 ∥R 2 )*C MONB  to discharge to VREF. By using the same type of resistor in the delay element as for R 1  and R 2 , any variation in the MONB discharge time will be tracked by the delay element. The lower value of the delay is then 5*(R 1 ∥R 2 )*C MONB , but there is no maximum limit since a higher delay will not cause any problem due to the capacitive regulation. After the loop is settled, the MON node will be same as V REF  due to high loop gain, forcing the output of the regulator to settle at V DD  itself. By taking the final regulation voltage of capacitive and resistive regulation to be the same, no extra time is taken during the transition from capacitive regulation to resistive regulation. 
     To further consider the settling output level during the capacitive regulation phase,  FIG. 5  considers  FIG. 3  when EN has gone high between t 0  and t 1  in  FIG. 4 , but the delayed version of ENd is still low. At this point, SW 1   41 , SW 2   43 , and M SW    47  are off and SW 3   45  is on and  FIG. 3  is equivalent to  FIG. 5 . The OUT and MON nodes are connected through C LEAD    29 . As discussed above, C MON    53  is not an actual added circuit element, but only the parasitic capacitance seen at the MON node and which is usually negligible compared to C LEAD  (C MON &lt;&lt;C LEAD ). The final output settling voltage of the capacitive regulation and the resistive regulation is preferably the same. A detailed derivation for the settling voltage of capacitive regulation is given with reference to  FIG. 6 , which again shows the control signals of  FIG. 3  corresponds to  FIG. 4  with the broken lines (that corresponded to  FIG. 2 ) removed and a time t p  indicating when the pass device M P    21  turns on. The input-output relation of feedback network is derived first and then the final settling voltage is calculated. 
     Referring to  FIG. 6 , at any time t, V(OUT)=V OUT  and V(MON)=V MON . At t=t 0  the regulator is enabled (EN goes high) and at t=t 1  M SW  is turned on (ENd goes high). During standby (t≦t 0 ), V OUT (t≦t 0 )=V DD  and V MON (t≦t 0 )=V REF . The wake-up period is t 0 &lt;t&lt;t 1 . For t 0 &lt;t&lt;t p , regulator is in open loop (M p  is OFF) and both C LEAD  and C MON  discharge and the voltage level changes. 
     At t=t p , V OUT =V OUT     —     P  and V MON =V MON     —     P . Referring to the boxed feedback network of  FIG. 5 : 
                       Δ   ⁢           ⁢     V   MON       =     Δ   ⁢           ⁢     V     OUT   *       ⁢       C   LEAD         C   LEAD     +     C   MON             ⁢     
     ⁢         V     MON_   ⁢           ⁢   p       -     V   REF       =       (       V   OUT_P     -     V   DD       )     ·       C   LEAD         C   LEAD     +     C   MON             ⁢     
     ⁢         V   MON_P     -       V     OUT   ⁢           ⁢   _   ⁢           ⁢   P       ·       C   LEAD         C   LEAD     +     C   par             =       V   REF     -       V   DD     ·       C   LEAD         C   LEAD     +     C   MON                       (     Equation   ⁢           ⁢   1     )               
At t=t P  the PMOS pass device M P    21  turns on, the loop is closed and the regulator takes some time to settle. Again, by capacitor division, for t≧t p :
 
                           V   MON     -     V     MON   ⁢           ⁢   _   ⁢           ⁢   P         =       (       V   OUT     -     V     OUT   ⁢           ⁢   _   ⁢           ⁢   P         )     ·       C   LEAD         C   LEAD     +     C   MON             ⁢     
     ⁢     V   MON     =           C   LEAD         C   LEAD     +     C   MON         ·     V   OUT       +     (       V     MON   ⁢           ⁢   _   ⁢           ⁢   P       -       V     OUT   ⁢           ⁢   _   ⁢           ⁢   P       ·       C   LEAD         C   LEAD     +     C   MON             )         ⁢     
     ⁢       V   MON     =       β   ·     V   OUT       +   α       ⁢     
     ⁢   where   ⁢           ⁢     
     ⁢     β   =       C   LEAD         C   LEAD     +     C   MON           ⁢     
     ⁢   and   ⁢           ⁢     
     ⁢           ⁢     α   =       V     MON   ⁢           ⁢   _   ⁢           ⁢   P       -       V     OUT   ⁢           ⁢   _   ⁢           ⁢   P       ·       C   LEAD         C   LEAD     +     C   MON                       (     Equation   ⁢           ⁢   2     )               
The input and output of the feedback network are related by a feed-back factor (β) and offset (α), as represented by  FIG. 7  that is a block level representation of  FIG. 5 . This gives:
 
     
       
         
           
             
               
                 
                   
                     V 
                     OUT 
                   
                   = 
                   
                     
                       
                         
                           V 
                           REF 
                         
                         - 
                         α 
                       
                       
                         
                           1 
                           A 
                         
                         + 
                         β 
                       
                     
                     ≈ 
                     
                       
                         
                           
                             V 
                             REF 
                           
                           - 
                           α 
                         
                         β 
                       
                       ⁢ 
                       
                         ( 
                         
                           when 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           A 
                           ⁢ 
                           
                             
                                 
                             
                             ⁢ 
                             
                                 
                             
                           
                           ⁢ 
                           is 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           large 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   ) 
                 
               
             
           
         
       
     
     Putting the value of α and β from Equation 2 into Equation 3 gives: 
               V   OUT     ≈           V   REF     -     (       V     MON   ⁢           ⁢   _   ⁢           ⁢   P       -       V     OUT   ⁢           ⁢   _   ⁢           ⁢   P       ·       C   LEAD         C   LEAD     +     C   MON             )           C   LEAD         C   LEAD     +     C   MON           .           
Using Equation 1, this becomes:
 
               V   OUT     ≈         V   REF     -     (       V   REF     -       V   DD     ·       C   LEAD         C   LEAD     +     C   MON             )           C   LEAD         C   LEAD     +     C   MON           ≈     V   DD           
Consequently, the final regulation voltage of capacitive regulation is V DD , which is same as when under resistive regulation.
 
     Consequently, by employing the aspects described with respect to the embodiment of  FIG. 3 , settling time during wake-up is reduced by capacitive regulation without taking any extra power. As this technique works in a closed loop, it has less process dependency for the final settling voltage and will also reduce unwanted overshoot at the output. 
     The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.