Patent Publication Number: US-7723824-B2

Title: Methodology for recovery of hot carrier induced degradation in bipolar devices

Description:
RELATED APPLICATIONS 
   This application is a divisional of U.S. patent application Ser. No. 10/904,985, filed Dec. 8, 2004. 

   FIELD OF THE INVENTION 
   The present invention relates to bipolar transistors, and more particularly to silicon-containing, e.g., SiGe, heterojunction bipolar transistors (HBTs) that include a self-heating structure in the circuit level that obviates avalanche carrier related damages which typically decrease the drive current gain in both the forward and reverse bias mode. The present invention also provides a method for recovering hot carrier induced degradation of HBTs and other like bipolar transistors. 
   BACKGROUND OF THE INVENTION 
   Bipolar transistors are electronic devices with two p-n junctions that are in close proximity to each other. A typical bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. Ideally, two p-n junctions, i.e., the emitter-base and collector-base junctions, are separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called “bipolar transistor action”. 
   If the emitter and collector are doped n-type and the base is doped p-type, the device is an “npn” transistor. Alternatively, if the opposite doping configuration is used, the device is a “pnp” transistor. Because the mobility of minority carriers, i.e., electrons, in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher frequency operation and higher speed performances can be obtained with npn transistors. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits. 
   As the vertical dimensions of bipolar transistors are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gap is larger than the band gap of the material used in the base. Such structures are referred to in the art as ‘heterojunction’ transistors. 
   Heterostructures comprising heterojunctions can be used for both majority carrier and minority carrier devices. Among minority carrier devices, heterojunction bipolar transistors (HBTs) in which the emitter is formed of Si and the base of a silicon germanium (SiGe) alloy have recently been developed. The SiGe alloy is narrower in band gap than silicon. 
   The advanced SiGe bipolar and complementary metal oxide semiconductor (BiCMOS) technology uses a SiGe base in the HBT. In the higher-frequency (such as multi-GHz) regime, conventional compound semiconductors such as, for example, GaAs and InP, currently dominate the market for high-speed wired and wireless communication devices. SiGe BiCMOS promises not only a comparable performance to GaAs in devices such as power amplifiers, but also a substantial cost reduction due to integration of HBTs with standard CMOS, yielding the so-called “system on a chip”. 
   As silicon germanium (SiGe) heterojunction bipolar transistor (HBT) performance moves up over 200 GHz, it has become apparent that the avalanche degradation mechanism becomes the dominant reliability concern for SiGe HBT circuit applications. This is due to the fact that the high frequency performance of the bipolar transistor is achieved by vertical scaling of the device, which decreases the vertical depth of the junctions and increases the electrical field within the device. This high electrical field at the collector-base junction during operation generates high energetic carriers that can damage the insulating interfaces around the device&#39;s emitter and shallow trench isolation (STI) interfaces. Avalanche carrier related damages will decrease (or degrade) the device current gain in both forward and reverse active mode. 
   The avalanche degradation mechanism was recently discovered and it imposes a very big constraint for high frequency and high power performance of SiGe HBTs. See, for example, G. Zhang, et al., “A New Mixed-Mode Base Current Degradation Mechanism in Bipolar Transistors”, IEEE BCTM 1.4, 2002 and Z. Yang, et al., “Avalanche Current Induced Hot Carrier Degradation in 200 GHz SiGe Heterojunction Bipolar Transistors”, Proc. International Reliability Physics Symposium, pp. 339-343, 2003. 
   A sample avalanche degradation of a typical SiGe HBT is shown in  FIG. 1 . Specifically,  FIG. 1  shows the current before the stress (T 0 ) and after 3000 seconds (T 1 ) avalanche stress for an IBM 200 GHz SiGe HBT with an emitter size of 0.8×0.8 μm 2  stressed at V CB =3.0 V and IE=5.12 mA. Operation in the avalanche regime has become more and more important for SiGe HBTs in high frequency applications; See, for example, H. Li, et al., “Design of W-Band VCOs with High Output Power for Potential Application in 77 GHz Automotive Radar Systems”, IEEE GaAs Digest, pp. 263-266 (2003). V CB  denotes the collector base voltage and IE denotes the emitter current. 
   Any methods to recover the avalanche degradation will greatly benefit the SiGe HBT circuit&#39;s performance and application range. However, there has not been any recovery method reported in the prior art to date because this degradation mechanism has only been fully investigated in the last year or so. 
   In view of the above, there is a need for providing a method to recover the avalanche degradation mentioned above in order to fabricate bipolar transistors, particularly SiGe HBTs, that can operate at the high frequencies currently required for the present generation of bipolar transistors. 
   SUMMARY OF THE INVENTION 
   Avalanche degradation is caused by avalanche hot carriers, which are highly energetic carriers that originate from the impact ionization of the collector-base junction when a bipolar transistor, particularly a SiGe HBT, is operating in the forward active mode. The avalanche hot carriers create damage within the bipolar transistor and decrease the device&#39;s current gain by increasing base current. The hot carrier effect is worse for the newer generation bipolar transistor devices and it increases in the collector-base junction with the increase of device performance. Moreover, avalanche hot carriers affect the breakdown voltage of bipolar transistors, especially SiGe HBTs. Specifically, a high avalanche current results in low breakdown voltage of the bipolar transistor. 
   Despite being possible to work outside the avalanche regime (V CB  less than 1 V), operation in the avalanche region (V CB  greater than 1V) is necessary to achieve high output power for high frequency bipolar transistors, e.g., SiGe HBTs. High output power is required for radar and wireless communication applications. In SiGe HBT technologies, the avalanche reliability is the major concern. V CB  denotes the voltage between the collector and base. 
   The recovery of avalanche degradation is important since the avalanche degradation effect mentioned above is getting worse with high unity current gain frequency fT devices. For example, a 1% current gain degradation was observed for a 200 GHz SiGe HBT, while 10% current gain degradation was observed for a 300 GHz SiGe HBT, after similar stress. Moreover, it is important to recover the avalanche degradation since the device hot carrier lifetime goes with the square of the degradation. For instance, if the degradation recovers by 50%, then the lifetime will be extended by 4×. 
   In view of the above the present invention provides a method and structure for recovering the avalanche degradation that is exhibited by prior art bipolar transistors, especially SiGe HBTs. In particular, the applicants of the present invention have discovered that the degradation caused by the avalanche effect described above can be significantly recovered by increasing the collector-base junction temperature utilizing a thermal anneal. 
   Specifically, and in broad terms, the method of the present invention thus comprises subjecting an idle bipolar transistor such as a HBT exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering said avalanche degradation of said bipolar transistor. 
   In one embodiment of the present invention, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. The self-heating structure increases the temperature of the bipolar transistor to about 200° C. or greater. In a few hours, typically from about 1 to about 10 hours, the degradation will be recovered. 
   In another embodiment of the present, the annealing step is a result of providing a high forward current around the peak fT current to the bipolar transistor while operating below the avalanche condition (V CB  of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. This is due to self-heating effect of the bipolar transistor which means the device&#39;s effective temperature increases if the device is operating in the high power range. The peak fT current denotes the driving current needed for the device achieving maximum fT. 
   In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal, a spike anneal or any other like annealing step which can increase the temperature of the bipolar transistor to a temperature of about 200° C. or above. 
   In addition to the method described above, the present invention also provides a bipolar transistor, especially a HBT, structure that includes a self-heating element that is present at the device level which can be used to increase the temperature of the bipolar transistor thereby recovering avalanche degradation. Specifically, and in broad terms, the bipolar transistor structure of the present invention comprises a Si-containing semiconductor substrate having a collector located therein; a base located atop said collector, and an emitter located on said base, said emitter having extended portions which are self-aligned to outer edges of said base, said extended portions of said emitter serve as a heating element. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a plot of current gain vs. V BE  (V) showing the current gain curves of a prior art SiGe HBT before stress (T 0 ) and after 3000 seconds (T 1 ) avalanche stress. 
       FIG. 2  is a cross sectional view of a bipolar transistor of the present invention. 
       FIG. 3  is a schematic plan view of the inventive bipolar transistor during operation. 
       FIG. 4  is a schematic plan view of the inventive bipolar transistor during recovery. 
       FIG. 5  is a plot showing the Joule heating characteristics performed on a polySi gate as a heater. 
       FIG. 6  is a plot of current gain vs. V BE  (V) showing the current gain curves of the inventive structure before T 0 , after avalanche stress T 1  and after recovery T 2  by forward current. 
       FIG. 7  is a plot of current gain vs. V BE  (V) showing the current gain curves of the inventive structure before T 0 , after avalanche stress T 1  and after recovery T 2  by forward current. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention, which provides a method and structure that can be used for the recovery of device degradation cause by avalanche hot carriers, will now be described in more detail by referring to the following drawings that accompany the present application. It is noted that the drawings of the inventive structure are provided herein for illustrative purposes and thus they are not drawn to scale. 
   Reference is first made to  FIG. 2  in which the inventive bipolar transistor structure including a self-heating element is shown. The term “bipolar transistor” includes any electronic device that includes two p-n junctions in close proximity to each other. The bipolar transistors include an emitter, a collector and a base positioned between the emitter and the collector. The present invention is specifically related to HBTs, and more particularly to SiGe HBTs. Specifically,  FIG. 2  illustrates a bipolar transistor structure  10  that includes a Si-containing semiconductor substrate  12  which has a collector  14  and a trench isolation region  16  located therein. The Si-containing semiconductor substrate  12  comprises any Si-containing semiconductor such as, for example, Si, SiGe, SiC, SiGeC, a silicon-on-insulator or a silicon germanium-on-insulator. Alternatively, the substrate  12  may be a Si layer such as epitaxial Si or amorphous Si formed atop a semiconductor substrate. The substrate  12  may include various doping or well regions. 
   As shown, substrate  12  includes a collector  14  that is formed into the substrate  12  via an ion implantation step. The trench isolation region  16  is made using techniques well known in the art including, for example, lithography, etching, optionally forming a trench liner, trench filling and, if needed, planarization. The trench fill material includes a trench dielectric material such as a high-density oxide or tetraethylorthosilicate (TEOS). 
   The structure  10  shown in  FIG. 2  also includes a base  18  that is located atop the surface of the substrate  12 ; the portion of the base  18  that extends above the trench isolation region  16  is referred to as the extrinsic base. The extrinsic base is labeled by reference numeral  20  in the drawings of the present application. 
   The base  18 , including the extrinsic base  20 , is formed by a low temperature epitaxial growth process (typically 450°-700° C.). The base  18  and the extrinsic base  20  may comprise Si, SiGe or a combination of Si and SiGe. The base  18  can also be comprised of SiGeC or a combination of Si and SiGeC. Preferably, the base  18  and extrinsic base  20  are comprised of SiGe or a combination of Si and SiGeC. The base  18  is monocrystalline over the substrate  12 , while the extrinsic base  20  is polycrystalline over the trench isolation region  16 . The region, e.g., interface, in which monocrystalline material is converted to polycrystalline material is referred to as the facet region. 
   The structure  10  also includes an emitter  22  which is located atop the base  18 . In accordance with the present invention, the emitter  22  has extended portions (labeled as  22 A and  22 B) that are self-aligned to outer edges  18 A and  18 B of the base  18 . The extended portions  22 A and  22 B of the emitter  22  serve as a self-heating element within the structure. The emitter  22  comprises a doped semiconductor material such as polySi, Si or SiGe. Preferably, the emitter  22 , including the extended portions  22 A and  22 B, are comprised of polySi. In such a preferred embodiment when the emitter  22  and the extended portions  22 A and  22 B are comprised of polySi, it is preferred that the base be comprised of SiGe. 
   The emitter  22  can be a layer with variable doping concentration, or a composition that can be grown in a state-of-the-art low temperature epitaxy system. The emitter  22  can also be formed by either an in-situ doping deposition process or by first deposition a polySi, Si or SiGe layer and then doping by ion implantation. 
   After forming the emitter  22 , the emitter  22  is patterned by lithography and etching to provide the configuration shown in  FIG. 2 . Specifically, the patterning of the emitter comprises a wider patterned mask than that which is used in conventional bipolar transistor device manufacturing. The wider patterned mask allows for the formation of the inventive emitter  22  which includes the extended portions  22 A and  22 B which are self aligned with edges  18 A and  18 B, respectively, of the base  18 . 
   The structure  10  also shown in  FIG. 2  includes a dielectric material  24  that has conductively filled vias and lines located therein. The conductively filled vias are labeled by reference numeral  26 A (contact via to the collector),  26 B (contact via to the extrinsic base  20 ), and  26 C (contact via to the emitter  22 ). The conductively filled lines are labeled as  28 A (M1 collector line),  28 B (M1 base line), and  28 C (M1 emitter line). The dielectric material  24  having the conductively filled vias and lines is formed via a conventional back-end-of-the-line process. Specifically, a dielectric material such as an organosilicate glass, an oxide, or a polymeric composition, is applied to the entire structure via a deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition or spin-on coating. Via and line openings are then formed by lithography and etching. A conductive metal such as W, Al, Cu or alloys thereof is then filled into the via and line opening and, if desired, a chemical mechanical polishing (CMP) or other like planarization process can be employed. 
   As shown in  FIG. 2 , the self-heating structure represented by extended emitter portions  22 A and  22 B is in the circuit level of the bipolar transistor device and it is side by side with the emitter  22  of the bipolar transistor. Under normal operation, the self-heating structure is floating and a high electrical field is generated at the collector-base junction which causes the formation of hot carriers that damage the device. During the recovery phase that occurs after normal operation, the bipolar transistor shown in  FIG. 2  is placed in an idle mode (i.e., without biasing) and a current from another circuit (internal or external) is flown through the self-heating structure  22 A and  22 B. The self-heating structure  22 A and  22   b  increases the temperature of the bipolar transistor to about 200° C. or greater. In a few hours, degradation will be recovered. Typically, the annealing step is performed for a time period from about 1 to about 10 hours. 
     FIG. 3  shows a schematic plan view of the bipolar transistor device of  FIG. 2 . During normal operation of the bipolar transistor device, the extended portions  22 A and  22 B (which represent a resistor) are kept floating. During recovery, the device is kept floating and the extended portions  22 A and  22 B are biased to generate heat directly to the degraded bipolar transistor device. The structure during the recovery mode is depicted in  FIG. 4 . 
     FIG. 5  illustrates the temperature rise caused during the recovery operation. Specifically,  FIG. 5  shows the Joule heating characterization performed on the structure shown in  FIG. 2  which includes the self-heating element  22 A and  22 B. A temperature rise of about 125° C. is observed when about 3 mA of current is driven through the self-heater. 
     FIG. 6  shows the current gain curves of a 0.12×2 μm 2  SiGe transistor before (T 0 ), after avalanche stress (T 1 ) and after recovery (T 2 ) by forward current. The avalanche stress conditions is IE=0.288 mA with a V CB =2.5 V for 4 K seconds. The recovery was conducted at 200° C. for 20 hours without any bias. 
   In addition to employing the self-heating structure described above to cause recovery of the hot carrier degradation of the bipolar transistor, the present invention also contemplates an embodiment in which any bipolar transistor device, including the one depicted above, is subjected to an annealing step in which a high forward current is applied to the bipolar transistor while operating below the avalanche condition. By ‘high forward current’ it is meant a current that is equal to or greater than peak fT. By ‘below the avalanche condition’ it is meant a V CB  of less than 1 V, typically around 0.5 V. Under the above conditions, about 40% or greater of the degradation can be recovered. This is due to self-heating effect of the bipolar transistor which means the device effective temperature increases if the device is operating in the high power range. 
     FIG. 7  shows the current gain curves of a 0.12×2 μm 2  SiGe transistor before (T 0 ), after avalanche stress (T 1 ) and after recovery (T 2 ) by forward current. The avalanche stress conditions is 1E=0.288 mA with a V CB =2.5 V for 3 K seconds. The recovery was conducted at IE=2.88 mA with V CB =1 V. The temperature was 30° C. during the entire experiment. 
   In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal a spike anneal or any other like annealing step which can increase the temperature of the bipolar transistor to a temperature of about 200° C. or above. When such annealing processes are employed, the annealing step is typically performed in the presence of an inert ambient such as Ar, He, Ne, N 2 , Xe, Kr or mixtures thereof. 
   While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.