Patent Publication Number: US-2022238423-A1

Title: Semiconductor device

Description:
RELATED APPLICATIONS 
     This application claims priority to Japanese Patent Application No. 2021-010154, filed on Jan. 26, 2021, the entire content of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device. 
     2. Description of the Related Art 
     Hitherto, there has been devised a voltage regulator for suppressing an output voltage drop to be caused by a wiring resistance in a circuit or a bonding wire resistance, and supplying a highly accurate constant voltage.  FIG. 4  is a circuit diagram for illustrating a configuration example of a related-art voltage regulator. 
     Bonding wires  4   a  and  4   b  are fixed to a lead frame pad  10  from respective pads  3   a  and  3   b  included in a semiconductor device  40 . In this manner, a voltage at a feedback point can include a wiring resistance in a circuit and a bonding wire resistance. 
     Accordingly, the related-art voltage regulator illustrated in  FIG. 4  is capable of suppressing the output voltage drop to be caused by the wiring resistance in the circuit or the bonding wire resistance, and supplying the highly accurate constant voltage (see, for example, Japanese Patent Application Laid-open No. Hei 07-161749). 
     In the related art, however, no consideration has been given to application to a package in which the bonding wires  4   a  and  4   b  cannot be fixed to the lead frame pad  10 . That is, it has been required to prepare two types of semiconductor devices depending on whether or not double bonding of the lead frame pad of the package is allowed. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in view of the above-mentioned circumstance, and has an object to provide a semiconductor device applicable to both types of packages regardless of whether or not double bonding of a lead frame pad is allowed. 
     According to at least one embodiment of the present invention, there is provided a semiconductor device including: an operational amplifier configured to receive a reference voltage from a reference voltage generation circuit and a feedback voltage from a feedback resistor; an output transistor to be controlled by an output signal of the operational amplifier; a first pad which is connected to an output terminal of the output transistor, and is to be selectively connected to a lead frame pad by a bonding wire; a second pad to be selectively connected to the lead frame pad by a bonding wire; a connection switching element provided between the first pad and the second pad; and the feedback resistor connected to the second pad and the connection switching element, wherein, in a case in which the second pad is connected to the lead frame pad by the bonding wire, the connection switching element interrupts connection between the first pad and the second pad. 
     Further, according to at least one embodiment of the present invention, there is provided a semiconductor device including: an operational amplifier configured to receive a reference voltage from a reference voltage generation circuit and a feedback voltage from a feedback resistor; an output transistor to be controlled by an output signal of the operational amplifier; a first pad connected to an output terminal of the output transistor; and a second pad connected to the feedback resistor, wherein, in a case in which any one of the first pad and the second pad is connected to a lead frame pad by a bonding wire, the first pad and the second pad are connected to each other by a bonding wire. 
     According to the semiconductor device of the at least one embodiment of the present invention, it is possible to provide the semiconductor device applicable to both types of packages regardless of whether or not double bonding of the lead frame pad is allowed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram for illustrating a semiconductor device according to a first embodiment of the present invention. 
         FIG. 2  is a circuit diagram for illustrating another example of the semiconductor device according to the first embodiment. 
         FIG. 3  is a circuit diagram for illustrating a semiconductor device according to a second embodiment of the present invention. 
         FIG. 4  is a circuit diagram for illustrating a related-art semiconductor device. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Now, embodiments of the present invention are described with reference to the drawings. 
     First Embodiment 
       FIG. 1  is a circuit diagram for illustrating a semiconductor device according to a first embodiment of the present invention. 
     A semiconductor device  1  of  FIG. 1  includes an operational amplifier  2 , pads  3   a  and  3   b,  an output transistor  5 , a feedback resistor  6 , a reference voltage generation circuit  7 , and a connection switching element  8 . The connection switching element  8  is formed of a fuse. The output transistor  5  is formed of a PMOS transistor. 
     The operational amplifier  2  includes an inverting input terminal (−) connected to an output terminal of the reference voltage generation circuit  7 , a non-inverting input terminal (+) connected to an output terminal of the feedback resistor  6 , and an output terminal connected to a gate of the output transistor  5 . The output transistor  5  includes a source connected to a power supply terminal, and a drain connected to one end of the connection switching element  8  and the pad  3   a  corresponding to an output terminal of the semiconductor device. Another end of the connection switching element  8  is connected to the pad  3   b  and one end of the feedback resistor  6 . Another end of the feedback resistor  6  is connected to a ground terminal. Another end of the reference voltage generation circuit  7  is connected to the ground terminal. 
     Bonding of the semiconductor device of the first embodiment indicates a case of a package in which a lead frame pad  10  is not adapted to double bonding. That is, the lead frame pad  10  is connected to the pad  3   a  by a bonding wire  4   a,  but the lead frame pad  10  is not connected to the pad  3   b.    
     The semiconductor device of the first embodiment is configured as follows depending on the shape of the lead frame pad  10  of the package. 
     In the case of the package in which the lead frame pad  10  is not adapted to double bonding, the pad  3   a  is connected to the lead frame pad  10  by the bonding wire  4   a  without cutting the fuse being the connection switching element  8 . 
     In a case of a package in which the lead frame pad  10  is adapted to double bonding, the fuse being the connection switching element  8  is cut. Further, the pad  3   a  is connected to the lead frame pad  10  by the bonding wire  4   a,  and the pad  3   b  is connected to the lead frame pad  10  by a bonding wire  4   b  (not shown). 
     The semiconductor device of the first embodiment is configured as described above. In this manner, the semiconductor device of the first embodiment is applicable to both types of packages regardless of whether or not double bonding of the lead frame pad is allowed. 
       FIG. 2  is a circuit diagram for illustrating another example of the semiconductor device of the first embodiment. 
     The semiconductor device of  FIG. 2  includes a connection switching element  8   a  formed of a PMOS transistor as the connection switching element, and a control circuit  9  configured to supply a control signal for controlling the connection switching element  8   a.  Other circuits are similar to those of the semiconductor device of  FIG. 1 . Thus, description thereof is omitted. 
     The semiconductor device of  FIG. 2  can be similarly applied by turning on and off the PMOS transistor of the connection switching element  8   a  through use of the control signal supplied from the control circuit  9 , depending on the shape of the lead frame pad  10  of the package. In this case, the connection switching element  8   a  is not limited to the PMOS transistor, and may be an NMOS transistor or an analog switch. 
     The control circuit  9  may be formed of, for example, a logic circuit or a test circuit, and may be configured to supply the control signal in response to an input signal from a test terminal or the like. 
       FIG. 3  is a circuit diagram for illustrating a semiconductor device according to a second embodiment of the present invention. 
     A semiconductor device  1  of  FIG. 3  includes an operational amplifier  2 , pads  3   b  and  3   c,  an output transistor  5 , a feedback resistor  6 , and a reference voltage generation circuit  7 . The pad  3   c  is formed into a size adapted to double bonding. 
     The operational amplifier  2  includes an inverting input terminal (−) connected to an output terminal of the reference voltage generation circuit  7 , a non-inverting input terminal (+) connected to an output terminal of the feedback resistor  6 , and an output terminal connected to a gate of the output transistor  5 . The output transistor  5  includes a source connected to a power supply terminal, and a drain connected to the pad  3   c  corresponding to an output terminal of the semiconductor device. The pad  3   c  is connected to the pad  3   b  by a bonding wire  4   c.  The pad  3   b  is connected to one end of the feedback resistor  6 . Another end of the feedback resistor  6  is connected to a ground terminal. Another end of the reference voltage generation circuit  7  is connected to the ground terminal. 
     Bonding of the semiconductor device of the second embodiment indicates a case of a package in which a lead frame pad  10  is not adapted to double bonding. That is, the lead frame pad  10  is connected to the pad  3   c  by a bonding wire  4   a,  but the lead frame pad  10  is not connected to the pad  3   b.    
     The semiconductor device of the second embodiment is configured as follows depending on the shape of the lead frame pad  10  of the package. 
     In the case of the package in which the lead frame pad  10  is not adapted to double bonding, the pad  3   b  and the pad  3   c  are connected to each other by the bonding wire  4   c,  and the pad  3   c  is connected to the lead frame pad  10  by the bonding wire  4   a.    
     In a case of a package in which the lead frame pad  10  is adapted to double bonding, the pad  3   b  and the pad  3   c  are not connected to each other by the bonding wire  4   c.  The pad  3   c  is connected to the lead frame pad  10  by the bonding wire  4   a,  and the pad  3   b  is connected to the lead frame pad  10  by a bonding wire  4   b  (not shown). 
     The semiconductor device of the second embodiment is configured as described above. In this manner, the semiconductor device of the second embodiment is applicable to both types of packages regardless of whether or not double bonding of the lead frame pad is allowed. 
     The embodiments of the present invention have been described above, but the present invention is not limited to the above-mentioned embodiments. It should be understood that various modifications can be made thereto without departing from the gist of the present invention. 
     For example, in  FIG. 1  and  FIG. 2 , the pad  3   b  and the lead frame pad  10  may be connected to each other by a bonding wire. Further, for example, the pad  3   b  of  FIG. 3  may be configured similarly to the pad  3   c,  and may be connected to, in place of the pad  3   c,  the lead frame pad  10  by a bonding wire.