Patent Publication Number: US-10334628-B2

Title: Program executed in transmitter, receiver and program executed in receiver

Description:
TECHNICAL FIELD 
     The present invention relates to a program executed in a transmitter, a receiver and a program executed in such a receiver. 
     BACKGROUND ART 
     There are receivers that comply with the Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) wireless standard and detects the frame length(s) of one or more radio frames each having a desired frame length, and decodes the detected frame length(s) into a bit sequence. 
     Further, receivers that receive radio frames while avoiding interference by an undesired radio frame are known (Patent Document 1). Such a receiver uses a plurality of radio frames, performs state transition by receiving a radio frame with a desired length, and, when it has received a plurality of radio frames with desired lengths and thus a transition condition is met, decodes the plurality of frame lengths into a bit sequence.
     Patent Document 1: JP 2012-175544 A   

     DISCLOSURE OF THE INVENTION 
     When the decoding method described in Patent Document 1 is used, the CSMA/CA wireless standard defines frame lengths, and the amount of information that can be represented by one frame is limited, making it difficult to modulate a desired data sequence into frame lengths for transmission. 
     The present invention was made to solve this problem. An object of the present invention is to provide a program executed in a transmitter that can transmit desired data represented by frame lengths. 
     Another object of the present invention is to provide a receiver that can receive desired data represented by frame lengths. 
     Still another object of the present invention is to provide a program executed in a receiver that can receive desired data represented by frame lengths. 
     According to an embodiment of the present invention, a program for causing a computer to execute transmission of radio frames in a transmitter is a program for causing a computer to execute: a first step in which a generating circuitry generates a first radio frame having a frame length representing header information of data to be transmitted and a second radio frame having a frame length representing the data to be transmitted; and a second step in which a transmitting circuitry transmits the first radio frame and the second radio frame one after another in accordance with a wireless communication scheme to transmit a radio frame when a wireless communication space is available and to wait to transmit a radio frame when the wireless communication space is not available. 
     Further, a receiver according to an embodiment of the present invention includes a receiving circuitry, first and second detecting circuitry, and a decoding circuitry. The receiving circuitry sequentially receives a first radio frame having a frame length representing header information of data to be transmitted and a second radio frame having a frame length representing the data to be transmitted. The first detecting circuitry detects a beginning of the data to be transmitted based on a received radio wave of the first radio frame. When the beginning of the data to be transmitted is detected, the second detecting circuitry detects the frame length of the second radio frame based on a received radio wave of the second radio frame. The decoding circuitry decodes the detected frame length into a bit sequence representing the data to be transmitted. 
     Further, according to an embodiment of the present invention, a program for causing a computer to execute reception of radio frames in a receiver is a program for causing a computer to execute: a first step in which a receiving circuitry sequentially receives a first radio frame having a frame length representing header information of data to be transmitted and a second radio frame having a frame length representing the data to be transmitted; a second step in which a first detecting circuitry detects a beginning of the data to be transmitted based on a received wave of the first radio frame; a third step in which, when the beginning of the data to be transmitted is detected, a second detecting circuitry detects the frame length of the second radio frame based on a received radio wave of the second radio frame; and a fourth step in which a decoding circuitry decodes the detected frame length into a bit sequence representing the data to be transmitted. 
     The program executed in the transmitter according to an embodiment of the present invention causes a computer to execute sequentially transmitting a first radio frame having a frame length representing header information of data to be transmitted and a second radio frame having a frame length representing the data to be transmitted in accordance with a wireless communication scheme to transmit a radio frame when a wireless communication space is available and to wait to transmit a radio frame when the wireless communication space is not available. As a result, a receiving device can detect the beginning of the data to be transmitted based on the received radio wave of the first radio frame and decode the data to be transmitted based on the received radio wave of the second radio frame. 
     Thus, desired data may be represented by frame lengths and transmitted. 
     Further, the receiver according to an embodiment of the present invention sequentially receives first and second radio frames and detects the beginning of the data to be transmitted based on the received radio wave of the first radio frame; when it has detected the beginning of the data to be transmitted, it detects the frame length of the second radio frame based on the received radio wave of the second radio frame and decodes the detected frame length into a bit sequence representing the data to be transmitted. 
     Thus, desired data represented by frame lengths may be received. 
     Furthermore, the program executed in the receiver according to an embodiment of the present invention causes a computer to execute the operations that are the same as the operations of the above receiver. 
     Thus, desired data represented by frame lengths may be received. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a wireless communication system according to Embodiment 1 of the present invention. 
         FIG. 2  is a schematic diagram of the transmitter of  FIG. 1 . 
         FIG. 3  is a schematic diagram of the receiver of  FIG. 1 . 
         FIG. 4  conceptually illustrates a radio frame according to Embodiment 1. 
         FIG. 5  is a correspondence table illustrating the relationship between the bit value of data and frame length. 
         FIG. 6  conceptually illustrates envelope detection and bit determination. 
         FIG. 7  illustrates a specific example of a radio frame according to Embodiment 1. 
         FIG. 8  is a flow chart illustrating the operation of the wireless communication system of  FIG. 1 . 
         FIG. 9  is a schematic diagram of a wireless communication system according to Embodiment 2. 
         FIG. 10  is a schematic diagram of the transmitter of  FIG. 9 . 
         FIG. 11  is a schematic diagram of the receiver of  FIG. 9 . 
         FIG. 12  is a correspondence table illustrating the relationship between the number of data frames and the frame length of a header frame. 
         FIG. 13  illustrates a specific example of a radio frame according to Embodiment 2. 
         FIG. 14  is a flow chart illustrating the operation of the wireless communication system of  FIG. 9 . 
         FIG. 15  is a schematic diagram of a wireless communication system according to Embodiment 3. 
         FIG. 16  is a schematic diagram of the transmitter of  FIG. 15 . 
         FIG. 17  is a schematic diagram of the receiver of  FIG. 15 . 
         FIG. 18  conceptually illustrates a radio frame according to Embodiment 3. 
         FIG. 19  is a flow chart illustrating the operation of the wireless communication system of  FIG. 15 . 
         FIG. 20  is a schematic diagram of a wireless communication system according to Embodiment 4. 
         FIG. 21  is a schematic diagram of the transmitter of  FIG. 20 . 
         FIG. 22  is a schematic diagram of the receiver of  FIG. 20 . 
         FIG. 23  conceptually illustrates a radio frame according to Embodiment 4. 
         FIG. 24  is a correspondence table illustrating another relationship between the bit value of data and frame length. 
         FIG. 25  is a correspondence table illustrating the relationship between the bit value of end information and frame length. 
         FIG. 26  is a flow chart illustrating the operation of the wireless communication system of  FIG. 20 . 
         FIG. 27  is a schematic diagram of a wireless communication system according to Embodiment 5. 
         FIG. 28  is a schematic diagram of the receiver of  FIG. 27 . 
         FIG. 29  is a state transition diagram of the identification device of  FIG. 28 . 
         FIG. 30  illustrates a reception state of a radio frame in Embodiment 5. 
         FIG. 31  illustrates another reception state of a radio frame in Embodiment 5. 
         FIG. 32  is a flow chart illustrating the operation of the wireless communication system of  FIG. 27 . 
         FIG. 33  is a schematic diagram of a wireless communication system according to Embodiment 6. 
         FIG. 34  is a schematic diagram of the receiver of  FIG. 33 . 
         FIG. 35  illustrates a reception state of a radio frame in Embodiment 6. 
         FIG. 36  is a flow chart illustrating the operation of the wireless communication system of  FIG. 33 . 
         FIG. 37  is a schematic diagram of a wireless communication system according to Embodiment 7. 
         FIG. 38  is a schematic diagram of the transmitter of  FIG. 37 . 
         FIG. 39  is a schematic diagram of the receiver of  FIG. 37 . 
         FIG. 40  conceptually illustrates a radio frame according to Embodiment 7. 
         FIG. 41  is a flow chart illustrating the operation of the wireless communication system of  FIG. 37 . 
         FIG. 42  is a schematic diagram of a configuration of a wireless communication system according to Embodiment 8. 
         FIG. 43  is a schematic diagram of the transmitter of  FIG. 42 . 
         FIG. 44  is a schematic diagram of the receiver of  FIG. 42 . 
         FIG. 45  conceptually illustrates a radio frame according to Embodiment 8. 
         FIG. 46  is a correspondence table illustrating the relationship between the bit value of data, first frame length and second frame length. 
         FIG. 47  is a correspondence table illustrating the relationship between the number of transmissions, and frame length. 
         FIG. 48  is a flow chart illustrating the operation of the wireless communication system of  FIG. 42 . 
         FIG. 49  is a schematic diagram of constitution of another wireless communication system according to Embodiment 8. 
         FIG. 50  is a schematic diagram of the transmitter of  FIG. 49 . 
         FIG. 51  is a schematic diagram of the receiver of  FIG. 49 . 
         FIG. 52  is a flow chart illustrating the operation of the wireless communication system of  FIG. 49 . 
         FIG. 53  is a schematic diagram of constitution of a wireless communication system according to Embodiment 9. 
         FIG. 54  is a schematic diagram of the transmitter  801  of  FIG. 53 . 
         FIG. 55  is a schematic diagram of the receiver  802  of  FIG. 53 . 
         FIG. 56  conceptually illustrates a radio frame according to Embodiment 9. 
         FIG. 57  illustrates relationships between information and frames where one of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying the data frames DFR_ 1  to DFR_n for an error and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed thereon. 
         FIG. 58  illustrates relationships between information and frames where two of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying the data frames DFR_ 1  to DFR_n for an error and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed thereon. 
         FIG. 59  illustrates relationships between information and frames where two of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying the data frames DFR_ 1  to DFR_n for an error and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed thereon. 
         FIG. 60  illustrates relationships between information and frames where all of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying the data frames DFR_ 1  to DFR_n for an error and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed thereon. 
         FIG. 61  illustrates relationships between information and frames where all of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying the data frames DFR_ 1  to DFR_n for an error and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed thereon. 
         FIG. 62  illustrates relationships between information and frames where all of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying the data frames DFR_ 1  to DFR_n for an error and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed thereon. 
         FIG. 63  illustrates relationships between information and frames where all of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying the data frames DFR_ 1  to DFR_n for an error and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed thereon. 
         FIG. 64  is a correspondence table illustrating the correspondence between the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and frame length. 
         FIG. 65  illustrates a specific example of the radio frame WFR 8 - 1  of  FIG. 56( a ) . 
         FIG. 66  illustrates a specific example of the radio frame WFR 8 - 2  of  FIG. 56( b ) . 
         FIG. 67  illustrates a specific example of the radio frame WFR 8 - 3  of  FIG. 56( c ) . 
         FIG. 68  illustrates a specific example of the radio frame WFR 8 - 4  of  FIG. 56( d ) . 
         FIG. 69  is a correspondence table illustrating the correspondence between the number of the data frames DFR_ 1  to DFR_n and error verification information, and frame length. 
         FIG. 70  is a correspondence table illustrating the relationship between the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and frame length. 
         FIG. 71  is a correspondence table illustrating the correspondence between the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n, and frame length. 
         FIG. 72  is a flow chart illustrating the operation of the wireless communication system of  FIG. 53 . 
         FIG. 73  is a schematic diagram of a wireless communication system according to Embodiment 10. 
         FIG. 74  is a schematic diagram of the transmitter of  FIG. 73 . 
         FIG. 75  is a schematic diagram of the receiver of  FIG. 73 . 
         FIG. 76  schematically illustrates a radio frame according to Embodiment 10. 
         FIG. 77  illustrates a specific example of a radio frame according to Embodiment 10. 
         FIG. 78  is a flow chart illustrating the operation of the wireless communication system of  FIG. 73 . 
         FIG. 79  is a schematic diagram of a wireless communication system according to Embodiment 11. 
         FIG. 80  is a schematic diagram of the transmitter of  FIG. 79 . 
         FIG. 81  is a schematic diagram of the receiver of  FIG. 79 . 
         FIG. 82  schematically illustrates a radio frame according to Embodiment 11. 
         FIG. 83  is a correspondence table illustrating the correspondence between the bit value of header information and frame length. 
         FIG. 84  is a correspondence table illustrating the correspondence between the bit value of delimiter information and frame length. 
         FIG. 85  is a correspondence table illustrating the correspondence between the bit value of a check frame and frame length. 
         FIG. 86  illustrates a specific example of a radio frame according to Embodiment 11. 
         FIG. 87  is a flow chart illustrating the operation of the wireless communication system of  FIG. 79 . 
         FIG. 88  is a schematic diagram of a wireless communication system according to Embodiment 12. 
         FIG. 89  is a schematic diagram of the transmitter of  FIG. 88 . 
         FIG. 90  is a schematic diagram of the receiver of  FIG. 88 . 
         FIG. 91  schematically illustrates a radio frame according to Embodiment 12. 
         FIG. 92  conceptually illustrates the method of transmitting frames and the method of receiving frames according to Embodiment 12. 
         FIG. 93  illustrates a first specific example of a radio frame according to Embodiment 12. 
         FIG. 94  illustrates a second specific example of a radio frame according to Embodiment 12. 
         FIG. 95  is a flow chart illustrating the operation of the wireless communication system of  FIG. 88 . 
         FIG. 96  is a schematic view of the constitution of Application Example 1. 
         FIG. 97  is a schematic view of the constitution of Application Example 2. 
         FIG. 98  is a schematic view of the constitution of Application Example 3. 
         FIG. 99  is a schematic view of the constitution of Application Example 4. 
         FIG. 100  is a schematic view of the constitution of Application Example 5. 
         FIG. 101  is a schematic view of the constitution of Application Example 6. 
         FIG. 102  is a schematic view of the constitution of Application Example 7. 
         FIG. 103  is a schematic view of the constitution of Application Example 8. 
     
    
    
     BEST MODES FOR CARRYING OUT THE INVENTION 
     Embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding components in the drawings are labeled with the same characters, and their description will not be repeated. 
     Embodiment 1 
       FIG. 1  is a schematic diagram of a wireless communication system according to Embodiment 1 of the present invention. Referring to  FIG. 1 , the wireless communication system  10  according to Embodiment 1 of the present invention includes a transmitter  1  and a receiver  2 . 
     The transmitter  1  and receiver  2  are positioned in a wireless communication space. The transmitter  1  generates, in the manner described below, a header frame HFR having a frame length indicating the beginning of data to be transmitted, data frames DFR having a plurality of frame lengths representing the data to be transmitted, and an end frame FFR having a frame length indicating the end of the data to be transmitted. Then, the transmitter  1  transmits the header frame HFR, data frame DFR and end frame FFR one after another in accordance with a wireless communication scheme to transmit radio frames when the wireless communication space is available and to wait to transmit radio frames when the wireless communication space is not available (i.e. CSMA/CA scheme). 
     The receiver  2  receives the header frame HFR, data frames DFR and end frame FFR transmitted by the transmitter  1 , and, based on the received radio wave of the header frame HFR, data frames DFR and end frame FFR that have been received, detects the beginning of the data to be transmitted, decodes the receiving radio waves into bit sequences indicating the data to be transmitted, and detects the end of the data to be transmitted. 
       FIG. 2  is a schematic diagram of the transmitter  1  of  FIG. 1 . Referring to  FIG. 2 , the transmitter  1  includes an antenna  11 , a transmitting circuitry  12  and a generating circuitry  13 . 
     The generating circuitry  13  generates, in the manner described below, the header frame HFR, data frames DFR and end frame FFR described above. Then, the generating circuitry  13  outputs the header frame HFR, data frames DFR and end frame FFR that have been generated to the transmitting circuitry  12 . 
     The transmitting circuitry  12  receives the header frame HFR, data frames DFR and end frame FFR from the generating circuitry  13 . Then, the transmitting circuitry  12  transmits the header frame HFR, data frames DFR and end frame FFR one after another via the antenna  11  in accordance with the CSMA/CA scheme. In this case, the transmitting circuitry  12  transmits the header frame HFR, data frames DFR and end frame FFR at a frequency of 2.4 GHz, for example. 
       FIG. 3  is a schematic diagram of the receiver  2  of  FIG. 1 . Referring to  FIG. 3 , the receiver  2  includes an antenna  21 , a band pass filter (BPF)  22 , an envelope detection circuit  23 , a frame length detection circuit  24 , a determination circuit  25 , and a decoder  26 . 
     The BPF  22  receives a radio frame transmitted by the transmitter  1  via the antenna  21 , and outputs those portions of the received radio wave of the received radio frame that have the frequency of the radio frame to the envelope detection circuit  23 . 
     The envelope detection circuit  23  receives the received radio wave from the BPF  22 , detects the envelope of the received radio wave that has been received, and outputs the envelope to the frame length detection circuit  24 . 
     The frame length detection circuit  24  receives the envelope from the envelope detection circuit  23  and, based on the received envelope, detects the frame length in the manner described below. Then, the frame length detection circuit  24  outputs the detected frame length to the determination circuit  25 . 
     The determination circuit  25  receives the frame length from the frame length detection circuit  24  and determines whether the received frame length indicates the beginning of the data to be transmitted. If the determination circuit  25  determines that the frame length indicates the beginning of the data to be transmitted, it outputs the frame lengths that it subsequently receives from the frame length detection circuit  24  to the decoder  26 . On the other hand, if the determination circuit  25  determines that the frame length does not indicate the beginning of the data to be transmitted, it discards the frame lengths that it subsequently receives from the frame length detection circuit  24 . 
     When the decoder  26  receives a frame length from the determination circuit  25 , it converts the frame length to a bit sequence in the manner described below, and outputs the converted bit sequence to the host system (not shown). 
       FIG. 4  conceptually illustrates a radio frame according to Embodiment 1. Referring to  FIG. 4 , a radio frame WFR 1  according to Embodiment 1 includes a header frame HFR 1 , data frames DFR_ 1  to DFR_n (n is an integer not smaller than 1), and an end frame FFR 1 . 
     The header frame HFR 1  has a frame length indicating the beginning of data to be transmitted (i.e. 1190 μs). 
     Each of the data frames DFR_ 1  to DFR_n has a frame length representing the data to be transmitted. 
     The end frame FFR 1  has a frame length indicating the end of the data to be transmitted (i.e. 680 μs). 
     Then, the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  are transmitted one after another in accordance with the CSMA/CA scheme. 
       FIG. 5  is a correspondence table illustrating the relationship between the bit value of data and frame length. Referring to  FIG. 5 , the correspondence table TBL 1  contains bit values of data and frame lengths. The bit values of data are associated with the frame lengths. 
     A bit value of data is represented by 4 bits, for example. The frame length of 710 μs is associated with the bit value of “0000”, the frame length of 740 μs is associated with the bit value of “0001”, the frame length of 770 μs is associated with the bit value of “0010”, the frame length of 800 μs is associated with the bit value of “0011”, the frame length of 830 μs is associated with the bit value of “0100”, the frame length of 860 μs is associated with the bit value of “0101”, the frame length of 890 μs is associated with the bit value of “0110”, the frame length of 920 μs is associated with the bit value of “0111”, the frame length of 950 μs is associated with the bit value of “1000”, the frame length of 980 μs is associated with the bit value of “1001”, the frame length of 1010 μs is associated with the bit value of “1010”, the frame length of 1040 μs is associated with the bit value of “1011”, the frame length of 1070 μs is associated with the bit value of “1100”, the frame length of 1100 μs is associated with the bit value of “1101”, the frame length of 1130 μs is associated with the bit value of “1110”, and the frame length of 1160 μs is associated with the bit value of “1111”. 
     Thus, the data to be transmitted is represented by frame lengths different from the frame lengths of the header frame HFR 1  and end frame FFR 1 . In the correspondence table TBL 1 , the frame length increases by 30 μs as the bit value increases by “1”. 
     The generating circuitry  13  of the transmitter  1  holds the correspondence table TBL 1 . Then, the generating circuitry  13  divides the bit sequence representing data to be transmitted into 4-bit values, and refers to the correspondence table TBL 1  to convert the divided 4-bit values into frame lengths. Thereafter, the generating circuitry  13  generates data frames DFR_ 1  to DFR_n having the converted frame lengths. 
     For example, if the bit sequence representing data to be transmitted is “1101001010010001”, the generating circuitry  13  divides the bit sequence of “1101001010010001” into the bit values of “1101”, “0010”, “1001”, and “0001”. Then, the generating circuitry  13  refers to the correspondence table TBL 1  to convert the bit value of “1101” into the frame length of 1100 μs, convert the bit value of “0010” into the frame length of 770 μs, convert the bit value of “1001” into the frame length of 980 μs, and convert the bit value of “0001” into the frame length of 740 μs. Thereafter, the generating circuitry  13  generates the data frame DFR_ 1  having the frame length of 1100 μs, the data frame DFR_ 2  having the frame length of 770 μs, the data frame DFR_ 3  having the frame length of 980 μs, and the data frame DFR_ 4  having the frame length of 740 μs. 
     The decoder  26  of the receiver  2  holds the correspondence table TBL 1 . Then, the decoder  26  refers to the correspondence table TBL 1  to convert frame lengths received from the determination circuit  25  into bit values to decode the frame lengths into bit sequences indicating data to be transmitted. 
       FIG. 6  conceptually illustrates envelope detection and bit determination. Referring to  FIG. 6 , the envelope detection circuit  23  of the receiver  2  receives a received radio wave FR of a radio frame WFR from the BPF  22 . The radio frame WFR has a frame length L of 1010 (μs), for example (see (a)). 
     The envelope detection circuit  23  detects an envelope EVL of the radio frame WFR, and detects the detected envelope EVL at an interval of 10 μs to obtain the detected values I 1  to I 102  (see (b)). 
     Then, the envelope detection circuit  23  outputs the detected values I 1  to I 102  to the frame length detection circuit  24 . The frame length detection circuit  24  determines the bit values of the detected values I 1  to I 102  and obtains the bit sequence “111 . . . 1110”. The frame length detection circuit  24  then accumulates the bit value of “1” starting from the beginning of the bit sequence “111 . . . 1110” and obtains the cumulative value of “101”. Since the bit value of the 102nd is “0”, the frame length detection circuit  24  multiplies the cumulative value of “101” by the interval of 10 μs to obtain a frame length of 1010 μs, and resets the cumulative value of “101”. 
       FIG. 7  illustrates a specific example of a radio frame WFR 1  according to Embodiment 1.  FIG. 7  illustrates a method of transmitting data to be transmitted in connection with an example where the bit sequence representing data to be transmitted is “1101001010010001”. 
     Referring to  FIG. 7 , the generating circuitry  13  of the transmitter  1  generates a header frame HFR 1  having the frame length of 1190 μs indicating the beginning of the data to be transmitted. Then, as described above, based on the bit sequence of “1101001010010001”, the generating circuitry  13  generates the data frame DFR_ 1  having the frame length of 1100 μs, the data frame DFR_ 2  having the frame length of 770 μs, the data frame DFR_ 3  having the frame length of 980 μs, and the data frame DFR_ 4  having the frame length of 740 μs. Thereafter, the generating circuitry  13  generates the end frame FFR 1  having the frame length of 680 μs indicating the end of the data to be transmitted. 
     Then, the generating circuitry  13  outputs the radio frame WFR 1 - 1  including the header frame HFR 1 , four data frames DFR_ 1  to DFR_ 4  and end frame FFR 1  to the transmitting circuitry  12 . 
     The transmitting circuitry  12  receives from the generating circuitry  13  the radio frame WFR 1 - 1  (i.e. the header frame HFR 1 , four data frames DFR_ 1  to DFR_ 4  and end frame FFR 1 ). 
     Then, the transmitting circuitry  12  performs carrier sensing via the antenna  11  and, when the wireless communication space is available, transmits the header frame HFR 1  constituting a part of the radio frame WFR 1 - 1  via the antenna  11 . 
     Thereafter, the transmitting circuitry  12  performs carrier sensing via the antenna  11  and, when the wireless communication space is available, transmits the data frame DFR_ 1  constituting a part of the radio frame WFR 1 - 1  via the antenna  11 . 
     Subsequently, in a similar manner, the transmitting circuitry  12  sequentially transmits the data frames DFR_ 2  to DFR_ 4  constituting parts of the radio frame WFR 1 - 1  via the antenna  11  in accordance with the CSMA/CA scheme. 
     Finally, the transmitting circuitry  12  performs carrier sensing via the antenna  11  and, when the wireless communication space is available, transmits the end frame FFR 1  constituting a part of the radio frame WFR 1 - 1  via the antenna  11 . 
     On the other hand, if the carrier sensing indicates that the wireless communication space is not available, the transmitting circuitry  12  waits to transmit the header frame HFR 1 , four data frames DFR_ 1  to DFR_ 4  and end frame FFR 1 . 
     Thus, the four data frames DFR_ 1  to DFR_ 4  having frame lengths representing data to be transmitted are sandwiched between the header frame HFR 1  and end frame FFR 1  and are transmitted in accordance with the CSMA/CA scheme. 
     The BPF  22  of the receiver  2  receives radio waves via the antenna  21  and outputs the portions of the received radio wave that have the frequency of the radio frame WFR 1 - 1  to the envelope detection circuit  23 . 
     Then, for each of portions of a plurality of the received radio waves received from the BPF  22 , the envelope detection circuit  23  detects detection values in the manner described above, and outputs the plurality of detected values I 1  to I 120 , I 1  to I 111 , I 1  to I 78 , I 1  to I 99 , I 1  to I 75  and I 1  to I 69  that have been detected to the frame length detection circuit  24 . 
     The frame length detection circuit  24  receives the plurality of detected values I 1  to I 120 , I 1  to I 111 , I 1  to I 78 , I 1  to I 99 , I 1  to I 75  and I 1  to I 69  from the envelope detection circuit  23 . 
     Then, based on the detected values I 1  to I 120 , the frame length detection circuit  24  detects the cumulative value of “119”, multiplies the cumulative value of “119” by the interval of 10 μs to detect the frame length of 1190 μs, and, based on the detected value I 120 =“0”, resets the cumulative value of “119”. 
     Thereafter, based on the detected values I 1  to I 111 , the frame length detection circuit  24  detects the cumulative value of “110”, multiplies the cumulative value of “110” by the interval of 10 μs to detect the frame length of 1100 μs, and, based on the detected value I 111 =“0”, resets the cumulative value of “110”. 
     Subsequently, based on the detected values I 1  to I 78 , I 1  to I 99 , I 1  to I 75  and I 1  to I 69 , the frame length detection circuit  24  similarly detects the frame lengths of 770 μs, 980 μs, 740 μs and 680 μs, respectively. 
     Then, the frame length detection circuit  24  successively provides the frame lengths of 1190 μs, 1100 μs, 770 μs, 980 μs, 740 μs and 680 μs to the determination circuit  25 . 
     The determination circuit  25  sequentially receives from the frame length detection circuit  24  the frame lengths of 1190 μs, 1100 μs, 770 μs, 980 μs, 740 μs and 680 μs. When the determination circuit  25  has received the frame length of 1190 μs, senses the beginning of the data to be transmitted based on the frame length of 1190 μs, and sequentially outputs the received frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs to the decoder  26 . 
     Thereafter, the determination circuit  25  receives the frame length of 680 μs, and senses the end of the data to be transmitted based on the received frame length of 680 μs, and stops outputting frame lengths to the decoder  26 . 
     The decoder  26  sequentially receives from the determination circuit  25  the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs, and refers to the correspondence table TBL 1  to convert the received frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs to the bit values of “1101”, “0010”, “1001” and “0001”, respectively. Then, the decoder  26  outputs the data to be transmitted made of the bit sequence of “1101001010010001” to the host system. 
     Thus, the transmitter  1  sequentially transmits the header frame HFR 1 , four data frames DFR_ 1  to DFR_ 4  and end frame FFR 1  in accordance with the CSMA/CA scheme. When the receiver  2  detects the frame length of the header frame HFR 1  (i.e. 1190 μs) based on a received radio wave, it senses the beginning of the data to be transmitted and converts the four frame lengths of the four data frames DFR_ 1  to DFR_ 4  (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) into bit values (i.e. “1101”, “0010”, “1001” and “0001”), thereby receiving the data to be transmitted (i.e. “1101001010010001”). Then, when the receiver  2  detects the frame length of the end frame FFR 1  (i.e. 680 μs), it senses the end of the data to be transmitted and ends the reception process. 
     As such, it is only required that the transmitter  1  transmit the data frames DFR_ 1  to DFR_n having frame lengths representing data to be transmitted by sandwiching between the header frame HFR 1  and end frame FFR 1 , and that the number of the data frames DFR_ 1  to DFR_n be not smaller than 1. 
     Therefore, desired data may be represented by frame lengths and transmitted. Also, desired data represented by frame lengths may be received. 
       FIG. 8  is a flow chart illustrating the operation of the wireless communication system  10  of  FIG. 1 . Referring to  FIG. 8 , when the operation of the wireless communication system  10  is started, the transmitter  1  generates the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  in the manner described above (step S 1 ). 
     Then, the transmitter  1  sets K-total number of frames, i.e. header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  (step S 2 ), and sets k=1 (step S 3 ). 
     Thereafter, the transmitter  1  performs carrier sensing (step S 4 ), and, based on the results of the carrier sensing, determines whether the wireless communication space is available (step S 6 ). 
     If it is determined that the wireless communication space is available, the transmitter  1  transmits the kth frame (step S 6 ). 
     Thereafter, the transmitter  1  determines whether k=K (step S 7 ). If it is determined at step S 7  that k=K is not true, the transmitter  1  sets k=k+1 (step S 8 ). Thereafter, the operation returns to step S 4 , and steps S 4  to S 8  described above are repeated until it is determined at step S 7  that k=K. 
     Then, if it is determined at step S 7  that k=K, the transmitter  1  stops transmitting radio frames. 
     The receiver  2  sequentially receives the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  (step S 9 ). 
     Then, the receiver  2  detects the envelopes of a plurality of the received radio wave of the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  and detects a plurality of detected values (step S 10 ). 
     Thereafter, the receiver  2  detects the plurality of frame lengths based on the plurality of detected values in the manner described above (step S 11 ). 
     Then, the receiver  2  determines whether the first frame length is 1190 μs (step S 12 ). 
     If it is determined at step S 12  that the first frame length is 1190 μs, the receiver  2  senses the beginning of the data to be transmitted (step S 13 ), and converts the second to N−1th frame lengths into bit sequences in the manner described above, thereby receiving the data to be transmitted (step S 14 ). 
     Thereafter, based on the received radio wave of the end frame FFR 1 , the receiver  2  senses the end of the data to be transmitted (step S 15 ). 
     Then, if it is determined at step S 12  that the first frame length is not 1190 μs, or after step S 15 , the operation ends. 
     Thus, the transmitter  1  sequentially transmits the header frame HFR 1 , n data frames DFR_ 1  to DFR_n and the end frame FFR 1  in accordance with the CSMA/CA scheme. When the receiver  2  detects the frame length of the header frame HFR 1  based on a received radio wave, it senses the beginning of the data to be transmitted, and converts the n frame lengths of the n data frames DFR_ 1  to DFR_n into bit sequences, thereby receiving the data to be transmitted. Then, when the receiver  2  detects the frame length of the end frame FFR 1 , it senses the end of the data to be transmitted, and ends the reception process. 
     As a result, it is only required that the transmitter  1  transmit the data frames DFR_ 1  to DFR_n having frame lengths representing data to be transmitted by sandwiching between the header frame HFR 1  and end frame FFR 1 , and that the number of the data frames DFR_ 1  to DFR_n be not smaller than 1. 
     Thus, desired data may be represented by frame lengths and be transmitted. Further, desired data represented by frame lengths may be received. 
     In the above descriptions, the correspondence table TBL 1  associates frame lengths with bit values of data where the frame length increases by 30 μs as the bit value of data increases by “1”; however, Embodiment 1 is not limited to such an implementation, and the correspondence table TBL 1  associates frame lengths with bit values of data where the frame length increases by a described length as the bit value of data increases by “1”. 
     In the above descriptions, the header frame HFR 1  has the frame length of 1190 μs; alternatively, in Embodiment 1, the header frame HFR 1  may have any frame length that is different from the frame lengths associated with bit values of data. 
     Further, in the above descriptions, the end frame FFR 1  has the frame length of 680 μs; alternatively, in Embodiment 1, the end frame FFR 1  may have any frame length that is different from the frame lengths associated with bit values of data. 
     Thus, since the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  have different frame lengths each other, the receiver  2  can distinguish between the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  to receive these frames. 
     Further, in Embodiment 1, there may not be an end frame FFR 1  because the receiver  2  can sense the beginning of data to be transmitted even if there is no the end frame FFR 1 . 
     Further, in Embodiment 1, the operations of the transmitter  1  and receiver  2  may be executed by a program. In this case, each of the transmitter  1  and receiver  2  includes a central processing unit (CPU), a read on memory (ROM) and a random access memory (RAM). In the transmitter  1 , the ROM stores a program A including steps S 1  to S 8  shown in  FIG. 8 , and the CPU reads the program A from the ROM and executes it. Thus, the operation of the transmitter  1  is performed. In the receiver  2 , the ROM stores a program B including steps S 9  to S 15  shown in  FIG. 8 , and the CPU reads the program B from the ROM and executes it. Thus, the operation of the receiver  2  is performed. Further, each of the ROMs of the transmitter  1  and receiver  2  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Embodiment 2 
       FIG. 9  is a schematic diagram of a wireless communication system according to Embodiment 2. Referring to  FIG. 9 , a wireless communication system  100  according to Embodiment 2 includes a transmitter  101  and a receiver  102 . 
     The transmitter  101  and receiver  102  are positioned in a wireless communication space. The transmitter  101  generates a header frame HFR 2  having a frame length representing the beginning of data to be transmitted and the number of data frames in the manner described below. 
     The transmitter  101  generates the data frames DFR_ 1  to DFR_n and the end frame FFR 1  in the same manner as that in the transmitter  1 . 
     When the wireless communication space is available, the transmitter  101  transmits the header frame HFR 2 , data frames DFR_ 1  to DFR_n and end frame FFR 1  one after another in accordance with the CSMA/CA scheme. 
     The receiver  102  receives the header frame HFR 2 , data frames DFR_ 1  to DFR_n and end frame FFR 1  transmitted by the transmitter  101 . Then, based on the received radio wave of the header frame HFR 2  that has been received, the receiver  102  detects the frame length representing the beginning of the data to be transmitted and the number of data frames. Otherwise, the receiver  102  performs the same functions as the receiver  1 . 
       FIG. 10  is a schematic diagram of the transmitter  101  of  FIG. 9 . Referring to  FIG. 10 , the transmitter  101  is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  of  FIG. 2  is replaced by a generating circuitry  13 A. 
     The generating circuitry  13 A generates data frames DFR_ 1  to DFR_n in the same manner as that in the generating circuitry  13 . Then, the generating circuitry  13 A detects the number n of the generated data frames DFR_ 1  to DFR_n, and generates a header frame HFR 2  having a frame length indicating the beginning of the data to be transmitted and the number n of data frames in the manner described below. Otherwise, the generating circuitry  13 A performs the same functions as the generating circuitry  13 . 
     In the transmitter  101 , the transmitting circuitry  12  receives from the generating circuitry  13 A the header frame HFR 2 , data frames DFR_ 1  to DFR_n and end frame FFR 1 , and transmits the header frame HFR 2 , data frames DFR_ 1  to DFR_n and end frame FFR 1  that have been received one after another in accordance with the CSMA/CA scheme. 
       FIG. 11  is a schematic diagram of the receiver  102  of  FIG. 9 . Referring to  FIG. 11 , the receiver  102  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  of  FIG. 3  is replaced by a determination circuit  25 A. 
     When the determination circuit  25 A receives the first frame length from the frame length detection circuit  24 , it determines whether the first frame length that has been received is equal to the frame length of the header frame HFR 2 . 
     If it is determined that the first frame length is equal to the frame length of the header frame HFR 2 , the determination circuit  25 A senses the beginning of the data to be transmitted and detects the number n of the data frames DFR_ 1  to DFR_n. When the determination circuit  25 A has detected the number n of the data frames DFR_ 1  to DFR_n, the determination circuit  25 A outputs to the decoder  26  the number of frame lengths that matches the number n of the data frames DFR_ 1  to DFR_n that has been detected. Otherwise, the determination circuit  25 A performs the same functions as the determination circuit  25 . 
       FIG. 12  is a correspondence table illustrating the relationship between the number of data frames and the frame length of a header frame. 
     Referring to  FIG. 12 , the correspondence table TBL 2  contains numbers of data frames and frame lengths of header frames. The numbers of data frames are associated with the frame lengths of header frames. 
     The frame length of 1190 μs is associated with the number of data frames of 1, the frame length of 1220 μs is associated with the number of data frames of 2, the frame length of 1250 μs is associated with the number of data frames of 3, and so forth, and the frame length of 1190+(n−1)×30 μs is associated with the number of data frames of n. 
     The frame length of 1190 μs indicates the beginning of data to be transmitted and that the number of data frames is 1; the frame length of 1220 μs indicates the beginning of data to be transmitted and that the number of data frames is 2; the frame length of 1250 μs indicates the beginning of data to be transmitted and that the number of data frames is 3; and so forth; and the frame length of 1190+(n−1)×30 μs indicates the beginning of data to be transmitted and that the number of data frames is n. 
     The generating circuitry  13 A of the transmitter  101  holds the correspondence tables TBL 1  and TBL 2 . In the same manner as that in the generating circuitry  13 , the generating circuitry  13 A generates data frames DFR_ 1  to DFR_n, and detects the number n of the generated data frames DFR_ 1  to DFR_n. 
     Then, the generating circuitry  13 A refers to the correspondence table TBL 2  and detects the frame length corresponding to the detected number n, and generates a header frame HFR 2  having the detected frame length. 
     The determination circuit  25 A of the receiver  102  holds the correspondence table TBL 2 . The determination circuit  25 A refers to the correspondence table TBL 2  and detects the number n of data frames corresponding to the first frame length. Then, the determination circuit  25 A outputs the number of frame lengths that is equal to the detected number n to the decoder  26 . 
       FIG. 13  illustrates a specific example of a radio frame according to Embodiment 2.  FIG. 13  illustrates how data to be transmitted is transmitted in an example where the bit sequence representing the data to be transmitted is “101000111111”. 
     Referring to  FIG. 13 , the generating circuitry  13 A of the transmitter  101  divides the bit sequence of “101000111111” representing the data to be transmitted into the bit values of “1010”, “0011”, and “1111”. Then, the generating circuitry  13 A refers to the correspondence table TBL 1  to convert the bit value of “1010” into the frame length of 1010 μs, convert the bit value of “0011” into the frame length of 800 μs, and convert the bit value of “1111” into the frame length of 1160 μs. 
     Then, the generating circuitry  13 A generates a data frame DFR_ 1  having the frame length of 1010 μs, a data frame DFR_ 2  having the frame length of 800 μs, and a data frame DFR_ 3  having the frame length of 1160 μs. 
     Then, the generating circuitry  13 A detects the number of the generated data frames DFR_ 1  to DFR_ 3  (i.e. 3). 
     Thereafter, the generating circuitry  13 A refers to the correspondence table TBL 2  to detect the frame length of 1250 μs corresponding to that number (i.e. 3), and generates a header frame HFR 2  having the detected frame length of 1250 μs. 
     Finally, the generating circuitry  13 A generates the end frame FFR 1  having the frame length of 680 μs indicating the end of the data to be transmitted. 
     Then, the generating circuitry  13 A outputs the radio frame WFR 1 - 2  including the header frame HFR 2 , three data frames DFR_ 1  to DFR_ 3  and end frame FFR 1  to the transmitting circuitry  12 . 
     The transmitting circuitry  12  receives from the generating circuitry  13 A the radio frame WFR 1 - 2  (i.e. the header frame HFR 2 , three data frames DFR_ 1  to DFR_ 3  and end frame FFR 1 ). 
     Then, the transmitting circuitry  12  transmits the header frame HFR 2 , three data frames DFR_ 1  to DFR_ 3  and end frame FFR 1  constituting the radio frame WFR 1 - 2  via the antenna  11  in accordance with the CSMA/CA scheme. 
     The BPF  22  of the receiver  102  receives a radio wave via the antenna  21  and outputs a plurality of reception radio waves that have the frequency of the radio frame WFR 1 - 2  in the received radio waves to the envelope detection circuit  23 . 
     Then, the envelope detection circuit  23  detects detection values for each of the plurality of reception radio waves received from the BPF  22  in the manner described above and outputs the detected detection values I 1  to I 126 , I 1  to I 102 , I 1  to I 81 , I 1  to I 117  and I 1  to I 69  to the frame length detection circuit  24 . 
     The frame length detection circuit  24  receives the detection values I 1  to I 126 , I 1  to I 102 , I 1  to I 81 , I 1  to I 117  and I 1  to I 69  from the envelope detection circuit  23 . 
     Then, based on the detection d values I 1  to I 126 , I 1  to I 102 , I 1  to I 81 , I 1  to I 117  and I 1  to I 69 , the frame length detection circuit  24  detects the frame lengths of 1250 μs, 1010 μs, 800 μs, 1160 μs and 680 μs, respectively, in the manner described above. 
     Then, the frame length detection circuit  24  sequentially outputs the frame lengths of 1250 μs, 1010 μs, 800 μs, 1160 μs and 680 μs to the determination circuit  25 A. 
     The determination circuit  25 A sequentially receives the frame lengths of 1250 μs, 1010 μs, 800 μs, 1160 μs and 680 μs from the frame length detection circuit  24 . When the determination circuit  25 A has received the frame length of 1250 μs, it refers to the correspondence table TBL 2  and, based on the frame length of 1250 μs, detects the beginning of the data to be transmitted and detects the number of data frames, i.e. 3. Thereafter, the determination circuit  25 A sequentially outputs the three frame lengths, i.e. frame lengths of 1010 μs, 800 μs and 1160 μs that it subsequently receives to the decoder  26 . 
     Finally, the determination circuit  25 A receives the frame length of 680 μs and, based on the received frame length of 680 μs, detects the end of the data to be transmitted and stops outputting frame lengths to the decoder  26 . 
     The decoder  26  sequentially receives the three frame lengths of 1010 μs, 800 μs and 1160 μs from the determination circuit  25 A, and refers to the correspondence table TBL 1  to convert the received frame lengths of 1010 μs, 800 μs and 1160 μs to the bit values of “1010”, “0011” and “1111”, respectively. Then, the decoder  26  outputs the data to be transmitted composed of the bit sequence of “101000111111” to the host system. 
     Thus, the transmitter  101  sequentially transmits the header frame HFR 2 , three data frames DFR_ 1  to DFR_ 3  and end frame FFR 1  in accordance with the CSMA/CA scheme. When the receiver  102  detects the frame length of the header frame HFR 2  (i.e. 1250 μs) based on the received radio wave, it senses the beginning of the data to be transmitted based on the frame length of 1250 μs, and it detects the number of data frames, i.e. 3, and converts the three frame lengths of the three data frames DFR_ 1  to DFR_ 3  (i.e. 1010 μs, 800 μs and 1160 μs) to the bit values (i.e. “1010”, “0011” and “1111”) to receive the data to be transmitted (i.e. “101000111111”). When the receiver  102  detects the frame length of the end frame FFR 1  (i.e. 680 μs), it senses the end of the data to be transmitted and ends the reception process. 
     As a result, when the determination circuit  25 A of the receiver  102  has detected the beginning of the data to be transmitted and the number of data frames, it outputs the number of frame lengths that is equal to the detected number to the decoder  26 . When the determination circuit  25 A has received from the frame length detection circuit  24  a number of frame lengths that is different from the number of data frames, it discards the received frame lengths. 
     Therefore, it is possible to prevent a frame from being interrupted or prevent a frame from being omitted. 
       FIG. 14  is a flow chart illustrating the operation of the wireless communication system  100  of  FIG. 9 . The flow chart of  FIG. 14  is the same as the flow chart of  FIG. 8  except that steps S 12  and S 13  of the flow chart of  FIG. 8  are replaced by steps S 12 A and S 13 A, respectively, and step S 16  is added. 
     Referring to  FIG. 14 , when the operation of the wireless communication system  100  is started, the transmitter  101  sequentially performs steps S 1  to S 8  described above. At step S 1 , the transmitter  101  generates data frames DFR_ 1  to DFR_n and, after detecting the number n of the generated data frames DFR_ 1  to DFR_n, generates a header frame HFR 2  based on the detected number n and the correspondence table TBL 2 . 
     The receiver  102  sequentially executes steps S 9  to step S 11  described above. Then, after step S 11 , based on the first frame length, the receiver  102  detects the beginning of the data to be transmitted and the number n of data frames in the manner described above (step S 12 A). 
     Then, the receiver  102  determines whether the number of the frame lengths from the second one to the N−1th one is equal to the number n (step S 13 A). 
     If it is determined at step S 13 A that the number of the frame lengths from the second one to the N−1th one is equal to the number n, the receiver  102  sequentially executes steps S 14  and S 15  described above. 
     On the other hand, if it is determined at step S 13 A that the number of the frame lengths from the second one to the N−1th one is not equal to the number n, the receiver  102  discards the number of frame lengths that is different from the number n (step S 16 ). 
     After step S 15  or step S 16 , the operation ends. 
     Thus, in Embodiment 2, the transmitter  101  transmits the header frame HFR 2  that has a frame length that represents the number of data frames. The receiver  102  detects the number n of data frames and, if the number of frame lengths from the second one to the N−1th one is equal to the number n, converts the second to N−1th frame lengths to bit sequences, thereby receiving the data to be transmitted. If the number of frame lengths from the second one to the N−1th one is not equal to the number n, the receiver  102  discards the number of frame lengths that is different from the number n. 
     Therefore, it is possible to prevent a frame from being interrupted data or prevent a frame from being omitted. 
     In the correspondence table TBL 2 , the frame length of a header frame increases by 30 μs from 1190 μs to 1190+(n−1)×30 μs as the number of data frames increases; however, Embodiment 2 is not limited to such an implementation, and the frame length of a header frame may increase by any interval as the number of data frames increases as long as the frame length is different from the frame lengths of the data frames DFR_ 1  to DFR_n. 
     Further, in Embodiment 2, the operations of the transmitter  101  and receiver  102  may be carried out by a program. In this case, each of the transmitter  101  and receiver  102  includes a CPU, a ROM and a RAM. In the transmitter  101 , the ROM stores the program A including steps S 1  to S 8  shown in  FIG. 14 , and the CPU reads the program A from the ROM and executes it. Thus, the operation of the transmitter  101  is performed. In the receiver  102 , the ROM stores a program C including steps S 9  to S 11 , S 12 A, S 13 A and S 14  to S 16  shown in  FIG. 14 , and the CPU reads the program C from the ROM and executes it. Thus, the operation of the receiver  102  is performed. Further, each of the ROMs of the transmitter  101  and receiver  102  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 2 is the same as that of Embodiment 1. 
     Embodiment 3 
       FIG. 15  is a schematic diagram of a wireless communication system according to Embodiment 3. Referring to  FIG. 15 , the wireless communication system  200  according to Embodiment 3 includes a transmitter  201  and a receiver  202 . 
     The transmitter  201  and receiver  202  are positioned in a wireless communication space. The transmitter  201  generates, in the manner described below, sub-header frames SHFR_ 1  to SHFR_m (m is an integer not smaller than 1) that are located at a desired interval along the data frames DFR_ 1  to DFR_n and have a frame length that indicates a delimiter within the sequence of the data frames DFR_ 1  to DFR_n. Each of the sub-header frames SHFR_ 1  to SHFR_m is also referred to as “delimiter frame”. 
     The transmitter  201  generates a header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  in the same manner as that in the transmitter  1 . 
     Then, the transmitter  201  transmits the header frame HFR 1 , data frames DFR_ 1  and DFR_ 2 , sub-header frame SHFR_ 1 , data frames DFR_ 3  and DFR_4, . . . sub-header frame SHFR_m, data frames DFR_n−1 and DFR_n, and end frame FFR 1  one after another in accordance with the CSMA/CA scheme. 
     The receiver  202  receives the header frame HFR 1 , data frames DFR_ 1  and DFR_ 2 , sub-header frame SHFR_ 1 , data frames DFR_ 3  and DFR_4, . . . sub-header frame SHFR_m, data frames DFR_n−1 and DFR_n, and end frame FFR 1  transmitted by the transmitter  201 . Then, based on the received radio wave of the received sub-header frames SHFR_ 1  to SHFR_m, the receiver  202  detects the frame length that indicates the delimiter inserted into the sequence of the data frames DFR_ 1  to DFR_n. Otherwise, the receiver  202  performs the same functions as the receiver  1 . 
       FIG. 16  is a schematic diagram of the transmitter  201  of  FIG. 15 . Referring to  FIG. 16 , the transmitter  201  is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  of  FIG. 2  is replaced by the generating circuitry  13 B. 
     The generating circuitry  13 B generates the sub-header frames SHFR_ 1  to SHFR_m having the frame length that indicates the delimiter inserted into the sequence of the data frames DFR_ 1  to DFR_n in the manner described below. Otherwise, the generating circuitry  13 B performs the same functions as the generating circuitry  13 . 
     In the transmitter  201 , the transmitting circuitry  12  receives, from the generating circuitry  13 B, the header frame HFR 1 , data frames DFR_ 1  and DFR_ 2 , sub-header frame SHFR_ 1 , data frames DFR_ 3  and DFR_4, . . . sub-header frame SHFR_m, data frames DFR_n−1 and DFR_n, and end frame FFR 1 , and transmits the header frame HFR 1 , data frames DFR_ 1  and DFR_ 2 , sub-header frame SHFR_ 1 , data frames DFR_ 3  and DFR_4, . . . sub-header frame SHFR_m, data frames DFR_n−1 and DFR_n, and end frame FFR 1  that have been received one after another in accordance with the CSMA/CA scheme. 
       FIG. 17  is a schematic diagram of the receiver  202  of  FIG. 15 . Referring to  FIG. 17 , the receiver  202  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  of  FIG. 3  is replaced by a determination circuit  25 B. 
     The determination circuit  25 B holds the frame length of the header frame HFR 1 , the frame lengths of the sub-header frames SHFR_ 1  to SHFR_m and the frame length of the end frame FFR. 
     If the frame length received from the frame length detection circuit  24  matches the frame length of the header frame HFR 1 , the determination circuit  25 B outputs a predetermined number of frame lengths to the decoder  26 , and, if the frame length received from the frame length detection circuit  24  matches the frame length of any one of the sub-header frames SHFR_ 1  to SHFR_m, outputs a predetermined number of frame lengths to the decoder  26 . Otherwise, the determination circuit  25 B performs the same functions as the determination circuit  25 . 
       FIG. 18  conceptually illustrates a radio frame according to Embodiment 3. Referring to  FIG. 18 , the radio frame WFR 3  of Embodiment 3 includes a header frame HFR 1 , data frames DFR_ 1  to DFR_n, sub-header frames SHFR_ 1  to SHFR_m, and an end frame FFR 1 . 
     The two data frames DFR_ 1  and DFR_ 2  are positioned to follow the header frame HFR 1 . The sub-header frame SHFR_ 1  is positioned to follow the data frame DFR_ 2 . The two data frames DFR_ 3  and DFR_ 4  are positioned to follow the sub-header frame SHFR_ 1 . The sub-header frame SHFR_ 2  is positioned to follow the data frame DFR_ 4 . The two data frames DFR_ 5  and DFR_ 6  are positioned to follow the sub-header frame SHFR_ 2 . 
     Other frames are positioned in a similar manner, and the sub-header frame SHFR_m is positioned to follow the data frame DFR_n−2, and the two data frames DFR_n−1 and DFR_n are positioned to follow the sub-header frame SHFR_m. 
     Then, the end frame FFR 1  is positioned to follow the data frame DFR_n. 
     Each of the sub-header frames SHFR_ 1  to SHFR_m has the frame length of 1280 μs. The frame length of 1280 μs indicates a delimiter inserted into the sequence of the data frames DFR_ 1  to DFR_n. 
       FIG. 18  shows an implementation where the number of data frames DFR positioned to follow the header frame HFR 1  and each of the sub-header frames SHFR_ 1  to SHFR_m is two; however, Embodiment 3 is not limited to such an implementation, and the numbers of data frames DFR positioned to follow the header frame HFR 1  and each of the sub-header frames SHFR_ 1  to SHFR_m may be 1 or more. Further, the numbers of data frames DFR positioned to follow the header frame HFR 1  and the sub-header frames SHFR_ 1  to SHFR_m may be the same or different from each other. 
     The generating circuitry  13 B of the transmitter  201  generates sub-header frames SHFR_ 1  to SHFR_m having the frame length of 1280 μs. Further, the generating circuitry  13 B generates a header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  in the same manner as that in the generating circuitry  13 . 
     Then, the generating circuitry  13 B outputs the header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m, data frames DFR_ 1  to DFR_n and end frame FFR 1  to the transmitting circuitry  12  in the order shown in  FIG. 18 . 
     The transmitting circuitry  12  receives, from the generating circuitry  13 B, the header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m, data frames DFR_ 1  to DFR_n and end frame FFR 1  in the order shown in  FIG. 18  and transmits the header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m, data frames DFR_ 1  to DFR_n and end frame FFR 1  that have been received one after another in the order shown in  FIG. 18  in accordance with the CSMA/CA scheme. 
     The receiver  202  receives the header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m, data frames DFR_ 1  to DFR_n and end frame FFR 1  in the order shown in  FIG. 18 . 
     Then, based on a plurality of received radio waves, the receiver  202  detects a plurality of frame lengths in the manner described above. 
     If the first frame length received from the frame length detection circuit  24  is equal to 1190 μs, the determination circuit  25 B senses the beginning of the data to be transmitted, and outputs a predetermined number (i.e. 2) of frame lengths following the first frame to the decoder  26 . 
     Then, each time the determination circuit  25 B determines that the frame length received from the frame length detection circuit  24  is equal to 1280 μs, it repeatedly outputs a predetermined number (i.e. 2) of frame lengths following the frame length of 1280 μs to the decoder  26 . 
     Finally, if the frame length received from the frame length detection circuit  24  is equal to 680 μs, the determination circuit  25 B senses the end of the data to be transmitted and stops outputting frame lengths to the decoder  26 . 
     The decoder  26  refers to the correspondence table TBL 1  to convert the n frame lengths received from the determination circuit  25 B to bit values, thereby receiving the data to be transmitted. Then, the decoder  26  outputs the data to be transmitted to the host system. 
     Thus, in Embodiment 3, n data frames DFR_ 1  to DFR_n are transmitted in such a way that a predetermined number of them are sandwiched between the header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m and end frame FFR 1 , thereby allowing a desired length of data to be transmitted while enabling detection of interruption by an interference frame or omission of a desired frame. 
       FIG. 19  is a flow chart illustrating the operation of the wireless communication system  200  of  FIG. 15 . The flow chart of  FIG. 19  is the same as the flow chart of  FIG. 8  except that steps S 1 , S 2  and S 9  of the flow chart of  FIG. 8  are replaced by steps S 1 A, S 2 A and S 9 A, respectively, and steps S 17  to steps S 20  are added between steps S 13  and S 15 . 
     Referring to  FIG. 19 , when the operation of the wireless communication system  200  is started, the transmitter  201  generates a header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m, data frames DFR_ 1  to DFR_n and an end frame FFR 1  (step S 1 A). 
     Then, the transmitter  201  sets K-total number of frames, i.e. header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m, data frames DFR_ 1  to DFR_n and end frame FFR 1  (step S 2 A). 
     Thereafter, the transmitter  201  executes steps S 3  to S 8  described above. Thus, the transmitter  201  transmits the header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m, data frames DFR_ 1  to DFR_n and end frame FFR 1  one after another in the order shown in  FIG. 18  in accordance with the CSMA/CA scheme. 
     When it is determined at step S 7  that k=K, the transmitter  201  stops transmitting frames. 
     Then, the receiver  202  receives the header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m, data frames DFR_ 1  to DFR_n and end frame FFR 1  in the order shown in  FIG. 18  (step S 9 A). 
     Thereafter, the receiver  202  sequentially executes steps S 10  to S 13  discussed above. 
     After step S 13 , the receiver  202  refers to the correspondence table TBL 1  to convert the predetermined number of frame lengths to bit sequences (step S 17 ). 
     Then, the receiver  202  determines whether the frame length is equal to 1280 μs (step S 18 ). 
     If it is determined at step S 18  that the frame length is equal to 1280 μs, the receiver  202  converts the predetermined number of frame lengths to bit sequences (step S 19 ). 
     Thereafter, the receiver  202  determines whether all the frame lengths have been converted to bit sequences (step S 20 ). 
     If it is determined at step S 20  that at least one of all the frame lengths have not been converted to bit sequences, the operation returns to step S 18  and steps S 18  to S 20  described above are repeatedly performed. 
     Then, if it is determined at step S 20  that all the frame lengths have been converted to bit sequences, the receiver  202  performs step S 15  described above. 
     On the other hand, if it is determined at step S 12  that the first frame length is not 1190 μs, or if it is determined at step S 18  that the frame length is not 1280 μs, or after step S 15 , the operation ends. 
     Thus, the data frames DFR_ 1  to DFR_n are transmitted in such a way that a predetermined number of these frames are sandwiched between the header frame HFR 1 , sub-header frames SHFR_ 1  to SHFR_m and end frame FFR 1 , thereby allowing a desired length of data to be transmitted while enabling detection of interruption by an interference frame or omission of a desired frame. 
     In Embodiment 3, the operations of transmitter  201  and receiver  202  may be carried out by a program. In this case, each of the transmitter  201  and receiver  202  includes a CPU, a ROM and a RAM. In the transmitter  201 , the ROM stores a program D including steps S 1 A, S 2 A and S 3  to S 8  shown in  FIG. 19 , and the CPU reads the program D from the ROM and executes it. Thus, the operation of the transmitter  201  is performed. In the receiver  202 , the ROM stores a program E including steps S 9 A, S 10 , S 11 , S 12 , S 13 , S 17  to S 20  and S 15  shown in  FIG. 14 , and the CPU reads the program E from the ROM and executes it. Thus, the operation of the receiver  202  is performed. Further, each of the ROMs of the transmitter  201  and receiver  202  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 3 is the same as that of Embodiment 1. 
     Embodiment 4 
       FIG. 20  is a schematic diagram of a wireless communication system according to Embodiment 4. Referring to  FIG. 20 , the wireless communication system  300  accordance to Embodiment 4 includes a transmitter  301  and a receiver  302 . 
     The transmitter  301  and receiver  302  are positioned in a wireless communication space. The transmitter  301  divides a bit sequence representing header information into bit values with desired numbers of bits and converts the divided bit values to frame lengths in the manner described below to generate header frames HFR_ 1  to HFR_i (i is an integer not smaller than 1) having the converted frame lengths. 
     The transmitter  301  also divides a bit sequence of end information indicating the end of data to be transmitted into bit values with desired numbers of bits, and converts the divided bit values to frame lengths in the manner described below to generate end frames FFR_ 1  to FFRj (j is an integer not smaller than 1) having the converted frame lengths. 
     Further, the transmitter  301  generates data frames DFR_ 1  to DFR_n in the same manner as that in the transmitter  1 . 
     Then, the transmitter  301  transmits the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j one after another in accordance with the CSMA/CA scheme. 
     The receiver  302  receives the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j that have been transmitted by the transmitter  301 . Then, based on the received radio wave of the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j that has been received, the receiver  302  detects the plurality of frame lengths of the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j, and converts the detected plurality of frame lengths to bit sequences, thereby receiving the header information, data to be transmitted and end information. 
       FIG. 21  is a schematic diagram of the transmitter  301  of  FIG. 20 . Referring to  FIG. 21 , the transmitter  301  is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  of  FIG. 2  is replaced by a generating circuitry  13 C. 
     The generating circuitry  13 C generates header frames HFR_ 1  to HFR_i and end frames FFR_ 1  to FFR_j in the manner described below. Otherwise, the generating circuitry  13 C performs the same functions as the generating circuitry  13 . 
     In the transmitter  301 , the transmitting circuitry  12  receives, from the generating circuitry  13 C, the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j, and transmits the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j that have been received one after another in accordance with the CSMA/CA scheme. 
       FIG. 22  is a schematic diagram of the receiver  302  of  FIG. 20 . Referring to  FIG. 22 , the receiver  302  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  of  FIG. 3  is omitted. 
     Accordingly, in the receiver  302 , the frame length detection circuit  24  outputs all the frame lengths that have been detected to the decoder  26 . 
       FIG. 23  conceptually illustrates a radio frame according to Embodiment 4. Referring to  FIG. 23 , the radio frame WFR 4  includes header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j. 
     The data frames DFR_ 1  to DFR_n are positioned to follow the header frames HFR_ 1  to HFR_i, and the end frames FFR_ 1  to FFR_j are positioned to follow the data frames DFR_ 1  to DFR_n. 
     The header frames HFR_ 1  to HFR_i have frame lengths corresponding to the bit sequence of the header information. The end frames FFR_ 1  to FFR_j have frame lengths corresponding to the bit sequence of the end information. 
     Thus, in the radio frame WFR 4 , each of the header frame HFR and end frame FFR is composed of at least one frame. Accordingly, the radio frame WFR 4  may include one header frame HFR and one end frame FFR; a plurality of header frames HFR and one end frame FFR; one header frame HFR and a plurality of end frames FFR; or a plurality of header frames HFR and a plurality of end frames FFR. That is, at least one of the header frame HFR and end frame FFR may be composed of one or more radio frames having one or more frame lengths. 
       FIG. 24  is a correspondence table illustrating another relationship between the bit value of data and frame length. 
     Referring to  FIG. 24 , the correspondence table TBL 3  contains bit values of data and frame lengths. The bit values of data are associated with the frame lengths. 
     A bit value of data is represented by 4 bits, for example. The frame length of 725 μs is associated with the bit value of “0000”, the frame length of 755 μs is associated with the bit value of “0001”, the frame length of 785 μs is associated with the bit value of “0010”, the frame length of 815 μs is associated with the bit value of “0011”, the frame length of 845 μs is associated with the bit value of “0100”, the frame length of 875 μs is associated with the bit value of “0101”, the frame length of 905 μs is associated with the bit value of “0110”, the frame length of 935 μs is associated with the bit value of “0111”, the frame length of 965 μs is associated with the bit value of “1000”, the frame length of 995 μs is associated with the bit value of “1001”, the frame length of 1025 μs is associated with the bit value of “1010”, the frame length of 1055 μs is associated with the bit value of “1011”, the frame length of 1085 μs is associated with the bit value of “1100”, the frame length of 1115 μs is associated with the bit value of “1101”, the frame length of 1145 μs is associated with the bit value of “1110”, and the frame length of 1175 μs is associated with the bit value of “1111”. 
     Thus, in the correspondence table TBL 3 , the frame length increases by 30 μs as the bit value increases by “1”. 
       FIG. 25  is a correspondence table illustrating the relationship between the bit value of end information and frame length. Referring to  FIG. 25 , the correspondence table TBL 4  contains bit values of end information and frame lengths. The bit values of end information are associated with the frame lengths. 
     A bit value of end information is represented by 2 bits, for example. The frame length of 500 μs is associated with the bit value of “00”, the frame length of 530 μs is associated with the bit value of “01”, the frame length of 560 μs is associated with the bit value of “10”, and the frame length of 590 μs is associated with the bit value of “11”. 
     Thus, in the correspondence table TBL 4 , the frame length increases by 30 μs as the bit value increases by “1”. 
     In Embodiment 4, the correspondence table TBL 1  (see  FIG. 5 ) is used to convert the bit sequence of header information to frame lengths. 
     As a result, the frame lengths representing header information, the frame lengths representing data to be transmitted and the frame lengths representing end information are different from each other. 
     The generating circuitry  13 C of the transmitter  301  holds the correspondence table TBL 1  (see  FIG. 5 ), correspondence table TBL 3  and correspondence table TBL 4 . 
     Then, the generating circuitry  13 C divides the bit sequence representing the header information into bit values with 4 bits, and refers to the correspondence table TBL 1  to convert the divided bit values to frame lengths to generate header frames HFR_ 1  to HFR_i having the converted frame lengths. 
     Further, the generating circuitry  13 C divides the bit sequence representing the data to be transmitted into bit values with 4 bits, and refers to the correspondence table TBL 3  to convert the divided bit values to frame lengths to generate data frames DFR_ 1  to DFR_n having the converted frame lengths. 
     Furthermore, the generating circuitry  13 C divides the bit sequence representing the end information into bit values with 2 bits, and refers to the correspondence table TBL 4  to convert the divided bit values to frame lengths to generate end frames FFR_ 1  to FFR_j having the converted frame lengths. 
     Then, the generating circuitry  13 C outputs the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j to the transmitting circuitry  12 . 
     The transmitting circuitry  12  transmits the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and end frames FFR_ 1  to FFR_j one after another in accordance with the CSMA/CA scheme. 
     The decoder  26  of the receiver  302  holds the correspondence tables TBL 1 , TBL 3  and TBL 4 . The decoder  26  sequentially receives a plurality of frame lengths from the frame length detection circuit  24 . Then, the decoder  26  refers to the correspondence tables TBL 1 , TBL 3  and TBL 4  and sequentially converts the plurality of frame lengths to bit sequences and outputs the converted bit sequences to the host system. 
     In this case, the decoder  26  refers to all the correspondence tables TBL 1 , TBL 3  and TBL 4  and detects the correspondence table containing the frame length from the frame length detection circuit  24  (i.e. one of the correspondence tables TBL 1 , TBL 3  and TBL 4 ), and refers to the detected correspondence table (i.e. one of the correspondence tables TBL 1 , TBL 3  and TBL 4 ) to convert the frame length to a bit sequence. 
     In Embodiment 4, the host system receives, from the decoder  26 , the bit sequence representing header information, the bit sequence representing data to be transmitted and the bit sequence representing end information, and, based on the bit sequence representing header information and the bit sequence representing end information, detects the beginning and end of the data to be transmitted and receives the data to be transmitted. 
       FIG. 26  is a flow chart illustrating the operation of the wireless communication system  300  of  FIG. 20 . The flow chart of  FIG. 26  is the same as the flow chart of  FIG. 8  except that steps S 12  to S 15  of the flow chart of  FIG. 8  are replaced by steps S 21  and S 22 . 
     Referring to  FIG. 26 , when the operation of the wireless communication system  300  is started, the transmitter  301  sequentially performs steps S 1  to S 8  described above. In this case, at step S 1 , the transmitter  301  refers to the correspondence table TBL 1  to generate header frames HFR_ 1  to HFR_i representing header information, refers to the correspondence table TBL 3  to generate data frame DFR_ 1  to DFR_n, and refers to the correspondence table TBL 4  to generate end frames FFR_ 1  to FFR_j. 
     Then, the receiver  302  sequentially executes steps S 9  to S 11  described above. After step S 11 , the decoder  26  of the receiver  302  refers to the correspondence tables TBL 1 , TBL 3  and TBL 4  to convert a plurality of frame lengths received from the frame length detection circuit  24  to a plurality of bit sequences (step S 21 ), and outputs the converted plurality of bit sequences to the host system. 
     Based on the plurality of bit sequences, the host system senses the header information, data to be transmitted and end information (step S 22 ). Thus, the operation ends. 
     Thus, in Embodiment 4, the transmitter  301  converts not only the bit sequence representing data to be transmitted but also the bit sequence of header information and the bit sequence of end information to frame lengths and transmits them, and the receiver  302  acquires the bit sequence of the header information and the bit sequence of the end information. 
     Therefore, the header information is capable of representing information other than the beginning of data to be transmitted. The end information is capable of representing information other than the end of data to be transmitted. 
     In Embodiment 4, the correspondence tables TBL 1 , TBL 3  and TBL 4  may contain other sets of frame lengths being different from frame lengths described above as long as the frame length changes as the bit value increases. It should be noted that the sets of frame lengths contained in the tables TBL 1 , TBL 3  and TBL 4  are different from each other. 
     Further, in Embodiment 4, the operations of the transmitter  301  and receiver  302  may be carried out by a program. In this case, each of the transmitter  301  and receiver  302  includes a CPU, a ROM and a RAM. In the transmitter  301 , the ROM stores the program A including steps S 1  to S 8  shown in  FIG. 26 , and the CPU reads the program A from the ROM and executes it. Thus, the operation of the transmitter  301  is performed. In the receiver  302 , the ROM stores a program F including steps S 9  to S 11 , S 21  and S 22  shown in  FIG. 26 , and the CPU reads the program F from the ROM and executes it. Thus, the operation of the receiver  302  is performed. Further, each of the ROMs of the transmitter  301  and receiver  302  corresponds to the storage medium storing the computer- (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 4 is the same as that of Embodiment 1. 
     Embodiment 5 
       FIG. 27  is a schematic diagram of a wireless communication system according to Embodiment 5. Referring to  FIG. 27 , the wireless communication system  400  according to Embodiment 5 is the same as the wireless communication system  300  except that the receiver  302  of the wireless communication system  300  of  FIG. 20  is replaced by a receiver  402 . 
     In Embodiment 5, a radio frame WFR 5  transmitting data to be transmitted is analogous to the radio frame WFR 4  (see  FIG. 23 ) where the number of the header frames HFR_ 1  to HFR_i is 2 or more (i.e., i is an integer not smaller than 2) and the number of the end frames FFR_ 1  to FFR_j is 2 or more (i.e. j is an integer not smaller than 2). 
     The receiver  402  is positioned in a wireless communication space. The receiver  402  receives the radio frame WFR 5  transmitted by the transmitter  301  and senses the header frames HFR_ 1  to HFR_i and end frames FFR_ 1  to FFR_j of the radio frame WFR 5  that has been received in the state transition scheme, described below. 
     The receiver  402  decodes the data frames DFR_ 1  to DFR_n into bit sequences where the permitted number of interrupt frames that interrupt the sequence of the data frames DFR_ 1  to DFR_n of the radio frame WFR 5  is w (w=1 or 2), or decodes the data frames DFR_ 1  to DFR_n into bit sequences while preventing a data frame from being omitted. 
       FIG. 28  is a schematic diagram of the receiver  402  of  FIG. 27 . Referring to  FIG. 28 , the receiver  402  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  of  FIG. 3  is replaced by a determination circuit  25 C and an identification device  410  is added. 
     The determination circuit  25 C holds the correspondence tables TBL 1 , TBL 3  and TBL 4 . The determination circuit  25 C also holds the number of the data frames DFR_ 1  to DFR_n. 
     If frame lengths received from the frame length detection circuit  24  are contained in the correspondence table TBL 1  or TBL 4 , the determination circuit  25 C outputs the frame lengths to the identification device  410 . On the other hand, if the frame lengths received from the frame length detection circuit  24  are not contained in the correspondence tables TBL 1  or TBL 4 , the determination circuit  25   c  discards the frame lengths. 
     If frame lengths received from the frame length detection circuit  24  are contained in the correspondence table TBL 3 , the determination circuit  25 C determines whether the number of the frame lengths contained in the correspondence table TBL 3  matches the number n. If the number of the frame lengths contained in the correspondence table TBL 3  matches the number n, the determination circuit  25 C outputs the frame lengths to the decoder  26 . On the other hand, if the number of the frame lengths contained in the correspondence table TBL 3  does not match the number n, the determination circuit  25 C discards the frame lengths. 
     If frame lengths received from the frame length detection circuit  24  are not contained in the correspondence table TBL 3 , the determination circuit  25 C determines whether the number of the frame lengths that are not contained in the correspondence table TBL 3  is not greater than the permitted value w. If the number of the frame lengths not contained in the correspondence table TBL 3  is not greater than the permitted value w, the determination circuit  25 C outputs the frame lengths to the decoder  26 . On the other hand, if the number of the frame lengths not contained in the correspondence table TBL 3  is greater than the permitted value w, the determination circuit  25   c  discards the frame lengths. 
     The identification device  410  receives a plurality of frame lengths from the determination circuit  25 C and, if the plurality of frame lengths that have been received match a plurality of wait states of its own, it outputs to the decoder  26  a signal HDS indicating that header information has been received or a signal FS indicating that end information has been received. 
     On the other hand, if the plurality of frame lengths do not match the plurality of wait states of its own, the identification device  410  does not output the signal HDS or FS to the decoder  26 . 
     In the receiver  402 , the decoder  26  holds the correspondence table TBL 3 . When the decoder  26  receives the signal HDS from the identification device  410  and then receives a frame length from the determination circuit  25 C, it refers to the correspondence table TBL 3  and decodes the received frame length into bit values. 
       FIG. 29  is a state transition diagram of the identification device  410  of  FIG. 28 . Referring to  FIG. 29 , the identification device  410  includes transition circuits  411  and  412 . 
     The transition circuit  411  includes an wait state for-L 1   4111 , an wait state for-L 2   4112 , . . . , and an wait state for-L 1   411   i.    
     The wait state for-L 1   4111  to wait state for-L 1   411   i  are states of waiting for the frame lengths L 1 , L 2 , . . . and Li, respectively. 
     First, the transition circuit  411  is in the wait state for-L 1   4111 , and, when the frame length L 1  or a frame length close to L 1 , such as L 1 −10 μs or L 1 +10 μs, is input, transitions to the wait state for-L 2   4112 . Then, when the frame length L 2  or a frame length close to L 2  is input, the transition circuit  411  transitions to the wait state for-L 3   4113 . Similarly, when the frame length Li−1 or a frame length close to Li−1 is input, the transition circuit  411  transitions to the wait state for-L 1   411   i ; when the frame length L 1  or a frame length close to L 1  is input, the circuit determines that the plurality of frame lengths match the wait state for-L 1   4111  to wait state for-L 1   411   i , and outputs the signal HDS to the decoder  26 . 
     Thus, the transition circuit  411  detects the header frames HFR_ 1  to HFR_i by detecting i frame lengths L 1 , L 2 , . . . and Li. That is, the transition circuit  411  senses the beginning of data to be transmitted by detecting i frame lengths L 1 , L 2 , . . . and Li. 
     On the other hand, if, for example, in the wait state for-L 2   4112 , the frame length L 2  or a frame length close to L 2  is not input in a predetermined time period, or a frame length different from the frame length L 2  or a frame length close to L 2  is input two or more times, the transition circuit  411  returns to the wait state for-L 1   4111 , which is the initial state. That is, the transition circuit  411  returns to the wait state for-L 1   4111 , i.e. the initial state, if the i frame lengths L 1 , L 2  . . . , and L 1  are not successively input even if a frame that is not one of the header frames HFR_ 1  to HFR_i happens to match the frame length for which the device is waiting for. 
     Supposing, while the transmitter  301  is transmitting the header frames HFR_ 1  to HFR_i, a frame from another transmitter interrupts the sequence, for example, even if a frame length different from the frame length L 2  or a frame length close to L 2  is input in the wait state for-L 2   4112 , the transition circuit  411  transitions to the state of waiting for the next frame length L 3  if the frame length of L 2  is input in a predetermined time period or before two or more different frame lengths are input. 
     Thus, even when the header frames HFR_ 1  to HFR_i having a plurality of frame lengths are transmitted, the device is capable of properly receiving the header frames HFR_ 1  to HFR_i as the transition circuit  411  transitions in state as shown in  FIG. 29 . 
     The transition circuit  412  includes an wait state for-L 1   4121 , wait state for-L 2   4122 , . . . , and an wait state for-Lj  412   j.    
     In the same operation as that for the transition circuit  411  described above, the transition circuit  412  determines that j frame lengths of the end frames FFR_ 1  to FFR_j match j wait states, i.e. wait-for-L 1  state  4121  to wait-for-Lj state  412   j , and outputs a signal FS to the decoder  26 . 
     In the identification device  410 , the two transition circuits  411  and  412  transition in state in response to the same plurality of frame lengths from the determination circuit  25 C; however, when i frame lengths of the header frames HFR_ 1  to HFR_i, are input, the transition circuit  411  determines that the i frame lengths match the i wait states, i.e. i wait state for-L 1   4111  to wait state for-L 1   411   i  and outputs the signal HDS, while the transition circuit  412  does not output the signal HDS because it cannot detect the match. 
     Further, when j frame lengths of the end frame FFR_ 1  to FFR_j are input, the transition circuit  412  determines that the j frame lengths match the j wait states, i.e. wait state for-L 1   4121  to wait state for-Lj  412   j  and outputs the signal FS, while the transition circuit  411  does not output the signal FS because it cannot detect the match. 
     Thus, even when the same plurality of frame lengths are input to both the transition circuits  411  and  412 , the identification device  410  is capable of outputting the signal HDS or FS to the decoder  26 . 
       FIG. 30  illustrates a manner in which a radio frame WFR 5  is received according to Embodiment 5. Referring to  FIG. 30 , the radio frame WFR 5 - 1  includes two header frames HFR_ 1  and HFR_ 2 , three data frames DFR_ 1  to DFR_ 3  and three end frames FFR_ 1  to FFR_ 3 . 
     In addition,  FIG. 30  shows an interrupt frame ITR 1  that interrupts between the data frames DFR_ 2  and data frame DFR_ 3 . 
     The transmitter  301  transmits the header frames HFR_ 1  and HFR_ 2 , data frames DFR_ 1  to DFR_ 3  and end frames FFR_ 1  to FFR_ 3  one after another in accordance with the CSMA/CA scheme. 
     Then, the receiver  402  sequentially receives the header frames HFR_ 1  and HFR_ 2 , data frames DFR_ 1  and DFR_ 2 , interrupt frame ITR 1 , data frame DFR_ 3  and end frames FFR_ 1  to FFR_ 3 . 
     The frame length detection circuit  24  of the receiver  402  sequentially outputs the two frame lengths L H1  and L H2  of the header frames HFR_ 1  and HFR_ 2  to the determination circuit  25 C, sequentially outputs the four frame lengths L D1 , L D2 , L IT1  and L D3  of the data frame DFR_ 1 , data frame DFR_ 2 , interrupt frame ITR 1  and data frame DFR_ 3  to the determination circuit  25 C, and sequentially outputs the three frame lengths L F1  to L F3  of the end frames FFR_ 1  to FFR_ 3  to the determination circuit  25 C. 
     When the determination circuit  25 C receives the two frame lengths L H1  and L H2 , it refers to the correspondence tables TBL 1 , TBL 3  and TBL 4  and senses that the two frame lengths L H1  and L H2  are contained in the correspondence table TBL 1 , and sequentially outputs the two frame lengths L H1  and L H2  to the identification device  410 . 
     When the identification device  410  receives the two frame lengths L H1  and L H2 , the transition circuit  411  senses that the two frame lengths L H1  and L H2  match the wait state for-L 1   4111  and wait state for-L 2   4112  and outputs the signal HDS to the decoder  26 , 
     After the determination circuit  25 C has outputted the two frame lengths L H1  and L H2  to the identification device  410 , it sequentially receives the four frame lengths L D1 , L D2 , L IT1  and L D3 . Then, the determination circuit  25 C senses that the frame lengths L D1 , L D2 , and L D3  are contained in the correspondence table TBL 3 , and senses that the frame length L IT1  is not contained in any of the correspondence tables TBL 1 , TBL 3  and TBL 4 . Thereafter, the determination circuit  25 C determines that the number of the frame lengths that are not contained in the correspondence table TBL 3  (i.e. 1) is not greater than the permitted value w (i.e. 1 or 2), and ignores the frame length L IT1  and outputs the frame lengths L D1 , L D2  and L D3  to the decoder  26 . 
     After the determination circuit  25 C has outputted the frame lengths L D1 , L D2  and L D3  to the decoder  26 , it sequentially receives the three frame lengths L F1  to L F3 . Then, the determination circuit  25 C senses that the three frame lengths L F1  to L F3  are contained in the correspondence table TBL 4 , and outputs the three frame lengths L F1  to L F3  to the identification device  410 . 
     When the identification device  410  receives the three frame lengths L F1  to L F3 , the transition circuit  412  senses that the three frame lengths L F1  to L F3  match the wait state for-L 1   4121  to wait state for-L 3   4123 , and outputs the signal FS to the decoder  26 . 
     After the decoder  26  has received the signal HDS from the identification device  410 , it receives the frame lengths L D1 , L D2  and L D3  from the determination circuit  25 C, and, based on the signal HDS, senses the beginning of the data to be transmitted. Then, the decoder  26  refers to the correspondence table TBL 3  to convert the received frame lengths L D1 , L D2  and L D3  to three bit values. Thereafter, the decoder  26  receives the signal FS and senses the end of the data to be transmitted, and outputs the bit sequence with the three bit values being arranged properly to the host system. 
     Thus, the receiver  402  permits a number of interrupt frame lengths ITR that is not larger than the permitted value w and performs the receiving process of data to be transmitted. 
     If the number of interrupt frames is larger than the permitted value w, the determination circuit  25 C discards the frame lengths L D1 , L D2  and L D3 . That is, if the number of interrupt frames is larger than the permitted value w, the receiver  402  stops the receiving process of the data to be transmitted. 
       FIG. 31  illustrates another manner in which a radio frame WFR 5  is received according to Embodiment 5. 
     The transmitter  301  transmits the header frames HFR_ 1  and HFR_ 2 , data frames DFR_ 1  to DFR_ 3  and end frames FFR_ 1  to FFR_ 3  one after another in accordance with the CSMA/CA scheme. 
     Then, the receiver  402  sequentially receives the header frames HFR_ 1  and HFR_ 2 , data frames DFR_ 1  and DFR_ 2  and end frames FFR_ 1  to FFR_ 3 . 
     The frame length detection circuit  24  of the receiver  402  sequentially outputs the two frame lengths L H1  and L H2  of the header frames HFR_ 1  and HFR_ 2  to the determination circuit  25 C, sequentially outputs the two frame lengths L D1  and L D2  of the data frames DFR_ 1  and DFR_ 2  to the determination circuit  25 C, and sequentially outputs the three frame lengths L 1  to L F3  of the end frames FFR_ 1  to FFR_ 3  to the determination circuit  25 C. 
     When the determination circuit  25 C has received the two frame lengths L H1  and L H2 , it refers to the correspondence tables TBL 1 , TBL 3  and TBL 4  and senses that the two frame lengths L H1  and L H2  are contained in the correspondence table TBL 1 , and sequentially outputs the two frame lengths L H1  and L H2  to the identification device  410 . 
     When the identification device  410  has received the two frame lengths L H1  and L H2 , the transition circuit  411  senses that the two frame lengths L H1  and L H2  match the wait state for-L 1   4111  and wait state for-L 2   4112 , and outputs the signal HDS to the decoder  26 . 
     After the determination circuit  25 C has outputted the two frame lengths L H1  and L H2  to the identification device  410 , it sequentially receives the two frame lengths L D1  and L D2 . Then, the determination circuit  25 C senses that the frame lengths L D1  and L D2  are contained in the correspondence table TBL 3 , and senses that the number of frame lengths L D1  and L D2  contained in the correspondence table TBL 3  (i.e. 2) is smaller than the number n of the data frames DFR_ 1  to DFR_ 3  (i.e. 3). Then, the determination circuit  25 C discards the frame lengths L D1  and L D2 . 
     In this case, even if the determination circuit  25 C receives the three frame lengths L F1  to L F3  after it has discarded the frame lengths L D1  and L D2 , it does not determine whether the three frame lengths L F1  to L F3  are contained in any one of the correspondence tables TBL 1 , TBL 3  and TBL 4 . 
     Also, if the number of the frame lengths of the data frames DFR is larger than the predetermined number (i.e. 3), the determination circuit  25 C discards the frame lengths received from the frame length detection circuit  24 . 
     Thus, if a data frame DFR is omitted, the receiver  402  determines that it has failed to receive the data to be transmitted, and stops the receiving process of the data to be transmitted. 
     Therefore, it is possible to correctly receive data frames DFR while preventing a data frame DFR from being omitted. 
       FIG. 32  is a flow chart illustrating the operation of the wireless communication system  400  of  FIG. 27 . The flow chart of  FIG. 32  is the same as the flow chart of  FIG. 8  except that steps S 12  to S 15  of the flow chart of  FIG. 8  are replaced by steps S 23  to S 27 . 
     Referring to  FIG. 32 , when the operation of the wireless communication system  400  is started, the transmitter  301  sequentially executes steps S 1  to S 8  described above. 
     Then, the receiver  402  sequentially executes steps S 9  to S 11  described above. After step S 11 , if the plurality of frame lengths received from the frame length detection circuit  24  are contained in the correspondence table TBL 1 , the determination circuit  25 C of the receiver  402  outputs the plurality of frame lengths to the identification device  410 , and the identification device  410  senses that the plurality of frame lengths match the wait state for-L 1   4111  to wait state for-L 1   411   i . That is, the receiver  402  performs matching on a plurality of frame lengths for header information (step S 23 ). 
     Thereafter, the determination circuit  25 C determines whether the number of interrupt frames is not larger than the permitted value w (step S 24 ). 
     If it is determined at step S 24  that the number of interrupt frames is not larger than the permitted value w, the determination circuit  25 C further determines whether the number of the frame lengths for the data matches the number n (step S 25 ). 
     If it is determined at step S 25  that the number of the frame lengths for the data matches the number n, the determination circuit  25 C outputs the plurality of the frame lengths for the data to the decoder  26 , and the decoder  26  refers to the correspondence table TBL 3  to convert the plurality of frame lengths to a bit sequence (step S 26 ). 
     After the determination circuit  25 C has outputted the plurality of frame lengths for the data to the decoder  26 , if the plurality of frame lengths received from the frame length detection circuit  24  are contained in the correspondence table TBL 4 , it outputs the plurality of frame lengths to the identification device  410 , and the identification device  410  senses that the plurality of frame lengths match the wait state for-L 1   4121  to wait state for-Lj  412 J. That is, the receiver  402  performs matching on the plurality of frame lengths for end information (step  27 ). 
     Then, if it is determined at step S 24  that the number of interrupt frames is larger than the permitted value w, or if it is determined at step S 25  that the number of the frame lengths for the data does not match the number n, or after step S 27 , the operation ends. 
     Thus, if the number of interrupt frames is not larger than the permitted value w, the receiving process for the data to be transmitted is continued, and, if the number of data frames DFR is different from a predetermined number (i.e. n), the receiving process for the data to be transmitted is not performed. 
     Therefore, it is possible to correctly receive data frames DFR while permitting a number of interrupt frames that is not larger than the permitted value w and preventing a data frame DFR from being omitted. 
     In the above description, the number n of the data frames DFR_ 1  to DFR_n is held by the determination circuit  25 C; however, Embodiment 5 is not limited to such an arrangement, and the number n may be represented by the header frames HFR_ 1  to HFR_i or end frames FFR_ 1  to FFR_j. 
     If the number n is represented by the header frames HFR_ 1  to HFR_i, a desired one of the header frames HFR_ 1  to HFR_i has a frame length that represents the number n. 
     On the other hand, if the number n is represented by the end frames FFR_ 1  to FFR_j, a desired one of the end frames FFR_ 1  to FFR_j has a frame length that represents the number n. 
     If the transition circuit  411  does not sense that the plurality of frame lengths match the wait state for-L 1   4111  to wait state for-L 1   411   i , it does not output the signal HDS to the decoder  26 . Then, if the transition circuit  412  does not sense that the plurality of frame lengths match the wait state for L 1   4121  to wait state for-Lj  412   j , it does not output the signal FS to the decoder  26 . 
     Thus, if the interrupt frame ITR interrupts the sequence of the header frames HFR_ 1  to HFR_i or end frames FFR_ 1  to FFR_j, the decoder  26  does not receive the signal HDS or FS, and therefore the receiving process for the data frames DFR_ 1  to DFR_n is not performed. 
     In Embodiment 5, the operations of the transmitter  401  and receiver  402  may be carried out by a program. In this case, each of the transmitter  401  and receiver  402  includes a CPU, a ROM and a RAM. In the transmitter  401 , the ROM stores the program A including steps S 1  to S 8  shown in  FIG. 32 , and the CPU reads the program A from the ROM and executes it. Thus, the operation of the transmitter  401  is performed. In the receiver  402 , the ROM stores a program G including steps S 9  to S 11 , and S 23  to S 27  shown in  FIG. 32 , and the CPU reads the program G from the ROM and executes it. Thus, the operation of the receiver  402  is performed. Further, each of the ROMs of the transmitter  401  and receiver  402  corresponds to the storage medium storing a computer (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 5 is the same as those of Embodiments 1 and 4. 
     Embodiment 6 
       FIG. 33  is a schematic diagram of a wireless communication system according to Embodiment 6. Referring to  FIG. 33 , the wireless communication system  500  according to Embodiment 6 is the same as the wireless communication system  10  except that the receiver  2  of the wireless communication system  10  of  FIG. 1  is replaced by a receiver  502 . 
     The radio frame WFR 6  of Embodiment 6 is constituted by the radio frame WFR 1  of  FIG. 4 . 
     The receiver  502  is positioned in a wireless communication space. the receiver  502  receives the radio frame WFR 6  from the transmitter  1 . Then, the receiver  502  processes the header frame HFR 1  and end frame FFR 1  forming parts of the radio frame WFR 6  in the same manner as that in the receiver  2 . 
     The receiver  502  detects the received signal strengths RSSI 1  to RSSIn of the data frames DFR_ 1  to DFR_n forming parts of the radio frame WFR 6 . Then, when the receiver  502  performs the receiving process on the data frame DFR_ 2  to DFR_n, it performs the receiving process on the data frames DFR_ 1  to DFR_n in the manner described above if the strength differences ΔRSSI between the received signal strengths RSSI 2  to RSSIn of the data frames DFR_ 2  to DFR_n and the received signal strengths RSSI 1  to RSSIn−1 of the data frames DFR_ 1  to DFR_n−1 directly preceding the data frame DFR_ 2  to DFR_n are smaller than the threshold Δ_th. 
     The threshold Δ_th is decided such that, for example, the n variances, which are the differences between the average of n received signal strengths RSSI 1  to RSSIn and the n received signal strengths RSSI 1  to RSSIn, is within 90% of the average. 
     On the other hand, if the strength difference ΔRSSI is not smaller than the threshold Δ_th, the receiver  502  determines whether the number n RSSI  of the data frames DFR for which the strength difference ΔRSSI is not smaller than the threshold Δ_th is not larger than the permitted value w RSSI . The permitted value w RSSI  is 1 or 2. 
     If the number n RSSI  is not larger than the permitted value w RSSI , the receiver  502  discards the data frames DFR for which the strength difference ΔRSSI is not smaller than the threshold Δ_th, and performs the receiving process for the data frames DFR_ 1  to DFR_n in the manner described above. 
     On the other hand, if the number n RSSI  is larger than the permitted value w RSSI , the receiver  502  determines that it has failed to receive the data frames DFR_ 1  to DFR_n, and stops the receiving process for the data frames DFR_ 1  to DFR_n. 
       FIG. 34  is a schematic diagram of the receiver  502  of  FIG. 33 . Referring to  FIG. 34 , the receiver  502  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  of  FIG. 3  is replaced by a determination circuit  25 D and a strength detection circuit  510  is added. 
     In the receiver  502 , the envelope detection circuit  23  outputs a detected envelope to the frame length detection circuit  24  and strength detection circuit  510 . 
     The strength detection circuit  510  receives a plurality of envelopes from the envelope detection circuit  23 , detects the strengths of the plurality of envelopes that have been received as the received signal strengths RSSI 1  to RSSIn, and outputs the detected received signal strengths RSSI 1  to RSSIn to the determination circuit  25 D. 
     The determination circuit  25 D receives the plurality of frame lengths for the data frames DFR from the frame length detection circuit  24  and receives the received signal strengths RSSI 1  to RSSIn from the strength detection circuit  510 . 
     Then, the determination circuit  25 D detects the strength difference ΔRSSI between the received signal strengths RSSI 2  to RSSIn of the data frames DFR_ 2  to DFR_n and the received signal strengths RSSI 1  to RSSIn−1 of the data frame DFR_ 1  to DFR_n−1, and determines whether the strength difference ΔRSSI that has been detected is smaller than the threshold Δ_th. 
     If the strength difference ΔRSSI is smaller than the threshold Δ_th, the determination circuit  25 D outputs the plurality of frame lengths to the decoder  26 . 
     On the other hand, if the strength difference ΔRSSI is not smaller than the threshold Δ_th, the determination circuit  25 D determines whether the number n RSSI  of the data frames DFR for which the strength difference ΔRSSI is not smaller than the threshold Δ_th is not larger than the permitted value w RSSI . 
     If the number n RSSI  is not larger than the permitted value w RSSI , the determination circuit  25 D discards the data frames DFR for which the strength difference ΔRSSI is not smaller than the threshold Δ_th, and outputs the plurality of frame lengths to the decoder  26 . 
     On the other hand, if the number n RSSI  is larger than the permitted value w RSSI , the determination circuit  25 D determines that it has failed to receive the data frames DFR_ 1  to DFR_n, and discards the plurality of frame lengths. 
     Otherwise, the determination circuit  25 D performs the same functions as the determination circuit  25 . 
       FIG. 35  illustrates a manner in which a radio frame WFR 6  is received according to Embodiment 6. The transmitter  1  transmits a header frame HFR 1 , data frames DFR_ 1  to DFR_ 3  and an end frame FFR 1  one after another in accordance with the CSMA/CA scheme. 
     Then, the receiver  502  sequentially receives the header frame HFR 1 , the data frames DFR_ 1  and DFR_ 2 , an interrupt frame ITR 2 , the data frame DFR_ 3  and the end frame FFR 1 . 
     The strength detection circuit  510  of the receiver  502  receives, from the envelope detection circuit  23 , an envelope EVL 1  for the header frame HFR 1 , an envelope EVL 2  for the data frame DFR_ 1 , data frame DFR_ 2 , interrupt frame ITR 2  and data frame DFR_ 3 , and an envelope EVL 3  for the end frame FFR 1 . 
     The strength detection circuit  510  detects the strength of the envelope EVL 1  as a received signal strength RSSI_HFR, detects the strength of the envelope EVL 2  as a received signal strengths RSSI 1  to RSSI 4 , and detects the strength of the envelope EVL 3  as a received signal strength RSSI_FFR. 
     Then, the strength detection circuit  510  outputs the received signal strength RSSI_HFR, received signal strengths RSSI 1  to RSSI 4  and received signal strength RSSI_FFR to the determination circuit  25 D. 
     The determination circuit  25 D receives, from the frame length detection circuit  24 , the frame length of the header frame HFR 1 , the four frame lengths of the data frame DFR_ 1 , data frame DFR_ 2 , interrupt frame ITR 2  and data frame DFR_ 3 , and the frame length of the end frame FFR 1 . Further, the determination circuit  25 D receives the received signal strength RSSI_HFR, received signal strengths RSSI 1  to RSSI 3  and RSSI_ITR, and the received signal strength RSSI_FFR from the strength detection circuit  510 . 
     Then, if the frame length of the header frame HFR 1  is equal to 1190 μs, the determination circuit  25 D senses the beginning of the data to be transmitted. 
     When the determination circuit  25 D has sensed the beginning of the data to be transmitted, it detects the strength difference ΔRSSI 1-2  between the received signal strength RSSI 2  and received signal strength RSSI 1 , and determines that the detected ΔRSSI 1-2  is smaller than the threshold Δ_th. 
     Then, the determination circuit  25 D detects the strength difference ΔRSSI 2-ITR  between the received signal strength RSSI_ITR and received signal strength RSSI 2 , and determines that the strength difference ΔRSSI 2-ITR  is smaller than the threshold Δ_th. 
     Thereafter, the determination circuit  25 D ignores the interrupt frame ITR 2  and detects the strength difference ΔRSSI 2-3  between the received signal strength RSSI 3  and received signal strength RSSI 2 , and determines that the strength difference ΔRSSI 2-3  is smaller than the threshold Δ_th. 
     Then, the determination circuit  25 D sequentially outputs the three frame lengths of the data frames DFR_ 1  to DFR_ 3  to the decoder  26 . 
     On the other hand, if the determination circuit  25 D determines that the strength difference ΔRSSI 2-ITR  is not smaller than the threshold Δ_th, it counts the number n RSSI  of the interrupt frame ITR 2  for which the strength difference ΔRSSI 2-ITR  is not smaller than the threshold Δ_th, the number n RSSI  being 1. Then, the determination circuit  25 D ignores the interrupt frame ITR 2  and detects the strength difference ΔRSSI 2-3  between the received signal strength RSSI 3  and received signal strength RSSI 2 , and determines that the strength difference ΔRSSI 2-3  is smaller than the threshold Δ_th. 
     Thereafter, the determination circuit  25 D determines that the number n RSSI , i.e. 1, is not larger than the permitted value w RSSI  (i.e. 1 or 2), and sequentially outputs the three frame lengths of the data frames DFR_ 1  to DFR_ 3  to the decoder  26 . 
     If the number n RSSI , i.e. 1, is larger than the permitted value w RSSI  (i.e. 1 or 2), the determination circuit  25 D discards the three frame lengths of the data frames DFR_ 1  to DFR_ 3 . 
     After the determination circuit  25 D has outputted the three frame lengths of the data frames DFR_ 1  to DFR_ 3  to the decoder  26 , it senses the end of the data to be transmitted when the frame length of the end frame FFR 1  is equal to 680 μs. 
     The decoder  26  refers to the correspondence table TBL 1  to sequentially convert the three frame lengths received from the determination circuit  25 D to bit values. 
     Thus, Embodiment 6 uses the received signal strength RSSI of a data frame DFR to detect the interrupt frame ITR, and, if the strength difference ΔRSSI in received signal strength between the detected interrupt frame ITR and the data frame DFR is not smaller than a threshold Δ_th, permits a number n RSSI  of interrupt frames for which the strength difference ΔRSSI is not smaller than the threshold Δ_th that is not larger than a permitted value w RSSI , and ignores the frames for which the strength difference ΔRSSI is not smaller than the threshold Δ_th and continues the receiving process. If the number n RSSI  is larger than the permitted value w RSSI , it stops the receiving process. 
     This can prevents a number of interrupt frames ITR that is larger than the permitted value w RSSI  from interrupting the sequence of the data frames DFR_ 1  to DFR_n. 
       FIG. 36  is a flow chart illustrating the operation of the wireless communication system  500  of  FIG. 33 . 
     The flow chart of  FIG. 36  is the same as the flow chart of  FIG. 8  except that step S 14  of the flow chart of  FIG. 8  is replaced by steps S 28  to S 32 . 
     Referring to  FIG. 36 , when the operation of the wireless communication system  500  is started, the transmitter  1  sequentially executes steps S 1  to S 8  described above. 
     Then, the receiver  502  sequentially executes steps S 9  to S 13  described above. After step S 13 , the strength detection circuit  510  of the receiver  502  detects the received signal strengths of the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 1  (step S 28 ). 
     Thereafter, the determination circuit  25 D of the receiver  502  detects the strength difference ΔRSSI between the received signal strengths of adjacent data frames (step S 29 ). 
     Subsequently, the determination circuit  25 D determines whether the strength difference ΔRSSI is smaller than the threshold Δ_th (step S 30 ). 
     If it is determined at step S 30  that the strength difference ΔRSSI is not smaller than the threshold Δ_th, the determination circuit  25 D further determines whether the number n RSSI  of the interrupt frames for which the strength difference ΔRSSI is not smaller than the threshold Δ_th is not larger than the permitted value w RSSI  (step S 31 ). 
     If it is determined at step S 30  that the strength difference ΔRSSI is smaller than the threshold Δ_th, or if it is determined at step S 31  that the number n RSSI  is not larger than the permitted value w RSSI , the determination circuit  25 D outputs the plurality of frame lengths for the data frames DFR to the decoder  26 , and the decoder  26  refers to the correspondence table TBL 1  to convert the plurality of frame lengths to a bit sequence (step S 32 ). Thereafter, the receiver  502  performs step S 15  described above. 
     If it is determined at step S 12  that the first frame length is not equal to 1190 μs, or if it is determined at step S 31  that the number n RSSI  is larger than the permitted value w RSSI , or after step S 15 , the operation ends. 
     Thus, Embodiment 6 uses the received signal strength RSSI of a data frame DFR to detect the interrupt frame ITR, and, if the strength difference ΔRSSI in received signal strength between the detected interrupt frame ITR and the data frame DFR is not smaller than the threshold Δ_th, permits that a number n RSSI  of the interrupt frames for which the strength difference ΔRSSI is not smaller than the threshold Δ_th is not larger than the permitted value w RSSI , and ignores the frames for which the strength difference ΔRSSI is not smaller than the threshold Δ_th and continues the receiving process. If the number n RSSI  is larger than the permitted value w RSSI , it stops the receiving process. 
     This can prevents a number of interrupt frames ITR that is larger than the permitted value w RSSI  from interrupting the sequence of the data frames DFR_ 1  to DFR_n. 
     In the above description, the strength difference ΔRSSI is the strength difference between one of the received signal strengths RSSI 2  to RSSIn of the data frames DFR_ 2  to DFR_n and one of the received signal strengths RSSI 1  to RSSIn−1 of the data frames DFR_ 1  to DFR_n−1; however, Embodiment 6 is not limited to such an implementation, and, in connection with those of the received signal strengths RSSI 1  to RSSIn that are the third and following ones, i.e. the received signal strengths RSSI 3  to RSSIn, the strength difference ΔRSSI may be the strength difference between the average of a plurality of the received signal strengths before the received signal strengths RSSI 3  to RSSIn and the received signal strengths RSSI 3  to RSSIn. 
     In Embodiment 6, the operations of the transmitter  501  and receiver  502  may be carried out by a program. In this case, each of the transmitter  501  and receiver  502  includes a CPU, a ROM and a RAM. In the transmitter  501 , the ROM stores the program A including steps S 1  to S 8  shown in  FIG. 36 , and the CPU reads the program A from the ROM and executes it. Thus, the operation of the transmitter  501  is performed. In the receiver  502 , the ROM stores a program H including steps S 9  to S 13 , S 28  to S 32  and S 15  shown in  FIG. 36 , and the CPU reads the program H from the ROM and executes it. Thus, the operation of the receiver  502  is performed. Further, each of the ROMs of the transmitter  501  and receiver  502  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 6 is the same as that of Embodiment 1. 
     Embodiment 7 
       FIG. 37  is a schematic diagram of a wireless communication system according to Embodiment 7. Referring to  FIG. 37 , the wireless communication system  600  according to Embodiment 7 includes a transmitter  601  and a receiver  602 . 
     The transmitter  601  and receiver  602  are positioned in a wireless communication space. The transmitter  601  generates identifier frames DGFR_ 1  to DGFR_s (s is an integer not smaller than 1) having frame lengths representing an identifier of a destination of transmission in the manner described below, and generates the data frames DFR_ 1  to DFR_n and the end frame FFR 1  in the same manner as that in the transmitter  1 . 
     Then, the transmitter  601  transmits the identifier frames DGFR_ 1  to DGFR_s, data frames DFR_ 1  to DFR_n and end frame FFR 1  one after another in accordance with the CSMA/CA scheme. 
     The receiver  602  receives the identifier frames DGFR_ 1  to DGFR_s, data frames DFR_ 1  to DFR_n and end frame FFR 1 . Then, the receiver  602  decodes the received radio wave of the identifier frames DGFR_ 1  to DGFR_s to a bit sequence in the manner described below. 
     The receiver  602  decodes the received radio wave of the data frames DFR_ 1  to DFR_n into a bit sequence in the same manner as that in the receiver  2 . 
     Further, the receiver  602  senses the end of the data to be transmitted based on the received radio wave of the end frame FFR 1  in the same manner as that in the receiver  2 . 
     Then, if the bit sequence decoded based on the received radio wave of the identifier frames DGFR_ 1  to DGFR_s matches the identifier of its own, the receiver  602  receives the bit sequence decoded based on the received radio wave of the data frames DFR_ 1  to DFR_n as the data to be transmitted. 
       FIG. 38  is a schematic diagram of the transmitter  601  of  FIG. 37 . Referring to  FIG. 38 , the transmitter  601  is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  of  FIG. 2  is replaced by a generating circuitry  13 D. 
     The generating circuitry  13 D holds an identifier of a destination of transmission. Then, the generating circuitry  13 D generates identifier frames DGFR_ 1  to DGFR_s in the manner described below. Further, the generating circuitry  13 D generates the data frames DFR_ 1  to DFR_n and the end frame FFR 1  in the same manner as that in the generating circuitry  13 . 
     Then, the generating circuitry  13 D outputs the identifier frames DGFR_ 1  to DGFR_s, data frames DFR_ 1  to DFR_n and end frame FFR 1  to the transmitting circuitry  12 . 
     In the transmitter  601 , the transmitting circuitry  12  sequentially transmits the identifier frames DGFR_ 1  to DGFR_s, data frames DFR_ 1  to DFR_n and end frame FFR 1  in accordance with the CSMA/CA scheme. 
       FIG. 39  is a schematic diagram of the receiver  602  of  FIG. 37 . Referring to  FIG. 39 , the receiver  602  is the same as the receiver  2  except that the frame length detection circuit  24  of the receiver  2  of  FIG. 3  is replaced by a frame length detection circuit  24 A and the detection circuit  25  is replaced by a determination circuit  610 . 
     The frame length detection circuit  24 A detects the plurality of frame lengths in the same manner as that in the frame length detection circuit  24 , and outputs the plurality of frame lengths that have been detected except for the last frame length to the decoder  26 , and outputs the last frame length to the determination circuit  610 . 
     The determination circuit  610  holds an identifier of the receiver  602 . The determination circuit  610  receives a bit sequence from the decoder  26 . Then, the determination circuit  610  determines whether the bit sequence of the identifier frames DGFR_ 1  to DGFR_s matches the identifier of the receiver  602 . 
     If the bit sequence of the identifier frames DGFR_ 1  to DGFR_s matches the identifier of the receiver  602 , the determination circuit  610  senses the beginning of the data to be transmitted and determines that the bit sequence of the data frames DFR_ 1  to DFR_n is data addressed to the receiver  602 . 
     Then, when the determination circuit  610  senses the end of the data to be transmitted based on the last frame length received from the frame length detection circuit  24 A, it outputs the bit sequence of the data frames DFR_ 1  to DFR_n as the data to be transmitted to the host system. 
       FIG. 40  conceptually illustrates a radio frame according to Embodiment 7. Referring to  FIG. 40 , the radio frame WFR 7  in Embodiment 7 includes the identifier frames DGFR_ 1  to DGFR_s, data frames DFR_ 1  to DFR_n and end frame FFR 1 . 
     The identifier frames DGFR_ 1  to DGFR_s have frame lengths that represent an identifier of a destination of transmission. 
     The data frames DFR_ 1  to DFR_n are positioned to follow the identifier frames DGFR_ 1  to DGFR_s, and the end frame FFR 1  is positioned to follow the data frames DFR_ 1  to DFR_n. 
     The generating circuitry  13 D of the transmitter  610  holds the correspondence table TBL 1  (see  FIG. 5 ) and the correspondence table TBL 3  (see  FIG. 24 ). 
     Then, the generating circuitry  13 D divides the bit sequence representing the identifier of the destination of transmission into bit values with 4 bits, and refers to the correspondence table TBL 1  to convert the divided bit values to frame lengths, and generates identifier frames DGFR_ 1  to DGFR_s having the converted frame lengths. 
     The generating circuitry  13 D divides the bit sequence representing the data to be transmitted into bit values with 4 bits, and refers to the correspondence table TBL 3  to convert the divided bit values to frame lengths, and generates data frames DFR_ 1  to DFR_n having the converted frame lengths. 
     In Embodiment 7, the decoder  26  holds the correspondence tables TBL 1  and TBL 3 . If the frame length received from the frame length detection circuit  24 A is contained in the correspondence table TBL 1 , the decoder  26  refers to the correspondence table TBL 1  to convert the frame lengths to a bit sequence, and outputs the converted bit sequence to the determination circuit  610 . 
     If the frame length received from the frame length detection circuit  24 A is contained in the correspondence table TBL 3 , the decoder  26  refers to the correspondence table TBL 3  to convert the frame lengths to a bit sequence, and outputs the converted bit sequence to the determination circuit  610 . 
       FIG. 41  is a flow chart illustrating the operation of the wireless communication system  600  of  FIG. 37 . 
     The flow chart of  FIG. 41  is the same as the flow chart of  FIG. 8  except that steps S 1 , S 2 , S 9  and S 14  of the flow chart of  FIG. 8  are replaced by steps S 1 B, S 2 B, S 9 B and S 14 A, respectively, and step S 12  is replaced by steps S 33  and S 34 . 
     Referring to  FIG. 41 , when the operation of the wireless communication system  600  is started, the transmitter  601  generates the identifier frames DGFR_ 1  to DGFR_s, data frames DFR_ 1  to DFR_n and end frame FFR 1  in the manner described above (step S 1 B). 
     Then, the transmitter  601  sets K-total number of the identifier frames DGFR_ 1  to DGFR_s, data frames DFR_ 1  to DFR_n and end frame FFR 1  (step S 2 B). 
     Thereafter, the receiver  601  sequentially executes steps S 3  to S 8  described above. 
     If it is determined at step S 7  that k=K, the receiver  601  ends transmission of the radio frame WFR 7 . 
     Then, the receiver  602  sequentially receives the identifier frames DGFR_ 1  to DGFR_s, data frames DFR_ 1  to DFR_n and end frame FFR 1  (step S 9 B). 
     Thereafter, the receiver  602  sequentially executes steps S 10  and S 11  described above. After step S 11 , the receiver  602  converts the plurality of frame lengths except for the last frame length to a bit sequence (step S 33 ). 
     More specifically, if the frame length received from the frame length detection circuit  24 A is contained in the correspondence table TBL 1 , the decoder  26  of the receiver  602  refers to the correspondence table TBL 1  to convert the frame lengths to bit values. If the frame length received from the frame length detection circuit  24 A is contained in the correspondence table TBL 3 , the decoder  26  refers to the correspondence table TBL 3  to convert the frame lengths to bit values. 
     After step S 33 , the receiver  602  determines whether the bit sequence of the identifier frames (i.e. bit sequence into which frame lengths have been converted with reference to the correspondence table TBL 1 ) matches the identifier of the receiver  602  (step S 34 ). 
     If it is determined at step S 34  that the bit sequence of the identifier frames matches the identifier of the receiver  602 , step S 13  described above is performed. 
     The receiver  602  detects the bit sequence of the data frames (i.e. bit sequence into which data frames have been converted with reference to the correspondence table TBL 3 ) as the data to be transmitted (step S 14 A). 
     Thereafter, step S 15  described above is executed. 
     Then, if it is determined at step S 34  that the bit sequence of identifier frames does not match the identifier of the receiver  602 , or after step S 15 , the operation ends. 
     Thus, in Embodiment 7, the transmitter  601  transmits an identifier of a destination of transmission by the identifier frames DGFR_ 1  to DGFR_s, and, when the bit sequence decoded based on the received radio wave of the identifier frames DGFR_ 1  to DGFR_s matches the identifier of its own, the receiver  60  detects the bit sequence decoded based on the received radio wave of the data frames DFR_ 1  to DFR_n as the data to be transmitted. 
     Thus, a destination of transmission can be designated and data to be transmitted can be modulated with frame lengths and transmitted. 
     Also, the frame lengths of the identifier frames DGFR_ 1  to DGFR_s are different from the frame lengths of the data frames DFR_ 1  to DFR_n, thereby reducing errors in identifiers and data. 
     In Embodiment 7, the operations of the transmitter  601  and receiver  602  may be carried out by a program. In this case, each of the transmitter  601  and receiver  602  includes a CPU, a ROM and a RAM. In the transmitter  601 , the ROM stores a program I including steps S 1 B, S 2 B and S 3  to S 8  shown in  FIG. 41 , and the CPU reads the program I from the ROM and executes it. Thus, the operation of the transmitter  601  is performed. In the receiver  602 , the ROM stores a program J including steps S 9 B, S 10  to S 13 , S 34 , S 13 , S 14 A and S 15  shown in  FIG. 41 , and the CPU reads the program J from the ROM and executes it. Thus, the operation of the receiver  602  is performed. Further, each of the ROMs of the transmitter  601  and receiver  602  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 7 is the same as that of Embodiment 1. 
     Embodiment 8 
       FIG. 42  is a schematic diagram of a configuration of a wireless communication system according to Embodiment 8. Referring to  FIG. 42 , the wireless communication system  700  according to Embodiment 8 includes a transmitter  701  and a receiver  702 . 
     The transmitter  701  and receiver  702  are positioned in a wireless communication space. The transmitter  701  generates the header frame HFR 1  in the same manner as that in the transmitter  1 . The transmitter  701  generates data frames DFR_ 1  to DFR_n in the manner described below, generates an end frame FFR 2  having frame length that indicates the end of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n in the manner described below, and generates a verification frame VFR for verifying the data frames DFR_ 1  to DFR_n for an error in the manner described below. 
     Then, the transmitter  701  repeatedly performs, a predetermined number of transmissions, a transmitting process in which the header frame HFR 1 , data frames DFR_ 1  to DFR_n, verification frame VFR and end frame FFR 2  are transmitted in accordance with the CSMA/CA scheme. 
     The receiver  702  sequentially receives the header frame HFR 1 , data frames DFR_ 1  to DFR_n, verification frame VFR and end frame FFR 2 . Then, based on the frame length of the header frame HFR 1 , the receiver  702  senses the beginning of the data to be transmitted. 
     The receiver  702  repeatedly performs, the number of transmissions of the data frames DFR_ 1  to DFR_n, a decoding process in which the received radio wave of the data frames DFR_ 1  to DFR_n is decoded into a bit sequence in the manner described below, and, if the bit sequences for the number of transmissions match each other, receives the bit sequences as the data to be transmitted. 
     Further, based on the verification frame VFR, the receiver  702  detects an error in the data frames DFR_ 1  to DFR_n. 
     Further, based on the end frame FFR 2 , the receiver  702  senses the end of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
       FIG. 43  is a schematic diagram of the transmitter  701  of  FIG. 42 . Referring to  FIG. 43 , the transmitter  701  is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  of  FIG. 2  is replaced by a generating circuitry  13 E. 
     The generating circuitry  13 E holds a number of transmissions of the data frames DFR_ 1  to DFR_n. The generating circuitry  13 E generates a header frame HFR 1  in the same manner as that in the generating circuitry  13 . The generating circuitry  13 E generates data frames DFR_ 1  to DFR_n in the manner described below, generates an end frame FFR 2  having a frame length that indicates the end of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n in the manner described below, and generates a verification frame VFR for verifying the data frames DFR_ 1  to DFR_n for an error in the manner described below. 
     Then, the generating circuitry  13 E outputs the header frame HFR 1 , data frames DFR_ 1  to DFR_n, verification frame VFR, end frame FFR 2  and number of transmissions of the data frames DFR_ 1  to DFR_n to the transmitting circuitry  12 . 
     In the transmitter  701 , the transmitting circuitry  12  repeatedly transmits the header frame HFR 1 , data frames DFR_ 1  to DFR_n, verification frame VFR, and end frame FFR 2  in accordance with the CSMA/CA scheme the number of transmissions of the data frames DFR_ 1  to DFR_n. 
       FIG. 44  is a schematic diagram of the receiver  702  of  FIG. 42 . Referring to  FIG. 44 , the receiver  702  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  of  FIG. 3  is replaced by a determination circuit  25 E. 
     Based on the frame length of the header frame HFR 1 , the determination circuit  25 E senses the beginning of the data to be transmitted. 
     If the determination circuit  25 E detects an error in the data frames DFR_ 1  to DFR_n based on the frame length of the verification frame VFR, it discards the plurality of frame lengths. 
     On the other hand, if the determination circuit  25 E does not detect an error in the data frames DFR_ 1  to DFR_n, it senses the end of the data to be transmitted based on the frame length of the end frame FFR 2 , and senses the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     Then, the determination circuit  25 E receives, from the frame length detection circuit  24 , the plurality of frame lengths of the data frames DFR_ 1  to DFR_n the number of transmissions, and, if the plurality of frame lengths for the number of transmissions match each other, outputs the plurality of frame lengths to the decoder  26 . 
       FIG. 45  conceptually illustrates a radio frame according to Embodiment 8. Referring to  FIG. 45 , a radio frame WFR 8  of Embodiment 8 includes a header frame HFR 1 , data frames DFR_ 1  to DFR_n, verification frame VFR and end frame FFR 2 . 
     The data frames DFR_ 1  to DFR_n are positioned to follow the header frame HFR 1 , the verification frame VFR is positioned to follow the data frame DFR_n, and the end frame FFR 2  is positioned to follow the verification frame VFR. 
     The verification frame VFR has a frame length L V  for detecting the error in the data frames DFR_ 1  to DFR_n. Supposing that the frame lengths of the data frames DFR_ 1  to DFR_n are L 1  to Ln, respectively, the frame length L V  is represented as (L 1 +L 2 + . . . +Ln)/n or |L 1 −L 2 + . . . +Ln−1−Ln|. 
     The end frame FFR 2  has a frame length that indicates the end of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
       FIG. 46  is a correspondence table illustrating the relationship between the bit value of data and first and second frame lengths. 
     Referring to  FIG. 46 , the correspondence table TBL 5  contains bit values of data, first frame lengths and second frame lengths. The first frame lengths and second frame lengths are associated with the bit values of data. 
     The first frame length of 725 μs and the second frame length of 1175 μs are associated with the bit value of “0000”. The first frame length of 755 μs and the second frame length of 1145 μs are associated with the bit value of “0001”. The first frame length of 785 μs and the second frame length of 1115 μs are associated with the bit value of “0010”. The first frame length of 815 μs and the second frame length of 1085 μs are associated with the bit value of “0011”. The first frame length of 845 μs and the second frame length of 1055 μs are associated with the bit value of “0100”. The first frame length of 875 μs and the second frame length of 1025 μs are associated with the bit value of “0101”. The first frame length of 905 μs and the second frame length of 995 μs are associated with the bit value of “0110”. The first frame length of 935 μs and the second frame length of 965 μs are associated with the bit value of “0111”. The first frame length of 965 μs and the second frame length of 935 μs are associated with the bit value of “1000”. The first frame length of 995 μs and the second frame length of 905 μs are associated with the bit value of “1001”. The first frame length of 1025 μs and the second frame length of 875 μs are associated with the bit value of “1010”. The first frame length of 1055 μs and the second frame length of 845 μs are associated with the bit value of “1011”. The first frame length of 1085 μs and the second frame length of 815 μs are associated with the bit value of “1100”. The first frame length of 1115 μs and the second frame length of 785 μs are associated with the bit value of “1101”. The first frame length of 1145 μs and the second frame length of 755 μs are associated with the bit value of “1110”. The first frame length of 1175 μs and the second frame length of 725 μs are associated with the bit value of “1111”. 
     Thus, in Embodiment 8, each of the bit values of “0000” to “1111” is represented by two frame lengths. More specifically, each of the bit values “0000” to “1111” is represented by two frame lengths where, for two bit values A and B, one of the first frame length and second frame length of one bit value A is longer than one of the first frame length and second frame length of the other bit value B and the other one of the first frame length and second frame length of the one bit value A is shorter than the other one of the first frame length and second frame length of the other bit value B. 
     This allows each of the bit values “0000” to “1111” to be correctly received. The reason follows. Since frame lengths tend to fluctuate to be shorter in wireless communication, it is necessary that an error would occur in a bit value when the longer one of the first and second frame lengths described above becomes a longer frame length, and this fluctuation is unlikely to occur in wireless communication. 
     The generating circuitry  13 E of the transmitter  701  holds a correspondence table TBL 5 . Then, the generating circuitry  13 E divides a bit sequence representing data to be transmitted into bit values with 4 bits, and refers to the correspondence table TBL 5  to convert the divided bit values to first and second frame lengths, and generates a data frame DFR having the converted first and second frame lengths. 
     For example, if the data to be transmitted is represented by the bit sequence of “01100010”, the generating circuitry  13 E divides the bit sequence “01100010” into the bit values “0110” and “0010”, and refers to the correspondence table TBL 5  to convert the divided bit value “0110” to the frame lengths of [905 μs, 995 μs], and refers to the correspondence table TBL 5  to convert the bit value “0010” to the frame lengths of [785 μs, 1115 μs]. Then, the data frame DFR_ 1  is composed of a frame having the frame length of 905 μs and a frame having the frame length of 995 μs, while the data frame DFR_ 2  is composed of a frame having the frame length of 785 μs and a frame having the frame length of 1115 μs. 
     If two frame lengths are assigned to each of the bit values of “0000” to “1111”, each of the frame lengths L 1  to Ln of the data frames DFR_ 1  to DFR_n is constituted by the average of a first frame length and a second frame length. Thus, the generating circuitry  13 E calculates the average of first and second frame lengths to determine the frame lengths L 1  to Ln, and, based on the determined frame lengths L 1  to Ln, calculates (L 1 +L 2 + . . . +Ln)/n or |L 1 −L 2 + . . . +Ln−1−Ln|, thereby determining the frame length L V . 
     Further, the decoder  26  of the receiver  702  holds the correspondence table TBL 5 , and refers to the correspondence table TBL 5  to convert each pair of two frame lengths to a bit value for decoding to provide a bit sequence representing the data to be transmitted. 
       FIG. 47  is a correspondence table illustrating the relationship between the number of transmissions and frame length. Referring to  FIG. 47 , the correspondence table TBL 6  contains numbers of transmissions and frame lengths. The frame lengths are associated with the numbers of transmissions. 
     The frame length of 1200 μs is associated with the number of transmissions of 2; the frame length of 1230 μs is associated with the number of transmissions of 3; the frame length of 1260 μs is associated with the number of transmissions of 4; and the frame length of 1290 μs is associated with the number of transmissions of 5. 
     The generating circuitry  13 E of the transmitter  701  holds the correspondence table TBL 6 . Then, the generating circuitry  13 E refers to the correspondence table TBL 6  to detect the frame length associated with the number of transmissions that it holds, and generates an end frame FFR 2  having the detected frame length. 
     Further, the determination circuit  25 E of the receiver  702  holds the correspondence table TBL 6 . Then, the determination circuit  25 E refers to the correspondence table TBL 6  to detect the number of transmissions associated with the last frame length received from the frame length detection circuit  24 , thereby sensing the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     How the receiver  702  receives the radio frame WFR 8  will be described. It is supposed that the frame length L 1  of the data frame DFR_ 1  is represented by L 1 =(L 11 , L 22 ), the frame length L 2  of the data frame DFR_ 2  is represented by L 2 =(L 21 , L 22 ), and so forth, and the frame length Ln of the data frame DFR_n is represented by Ln=(L n1 , L n2 ). Here, L 11  to L n1  are the first frame lengths in the correspondence table TBL 5 , while L 12  to L n2  are the second frame lengths in the correspondence table TBL 5 . 
     When the receiver  702  has received the radio frame WFR 8 , based on the plurality of envelopes from the envelope detection circuit  23 , the frame length detection circuit  24  sequentially detects the plurality of frame lengths L H , L 1 =(L 11 , L 12 ) to Ln=(L n1 , L n2 ), L V  and L F , and sequentially outputs the plurality of frame lengths L H , L 1 =(L 11 , L 12 ) to Ln=(L n1 , L n2 ), L V  and L F  that have been detected to the determination circuit  25 E. Here, L H  is the frame length of the header frame HFR 1 , and L F  is the frame length of the end frame FFR 1 . 
     When the determination circuit  25 E has received the frame length L H , it determines whether the received frame length L H  is equal to 1190 μs, and, if the frame length L H  is equal to 1190 μs, it senses the beginning of the data to be transmitted. 
     Thereafter, the determination circuit  25 E sequentially receives the frame lengths L 1 =(L 11 , L 12 ) to Ln=(L n1 , L n2 ) and L V . Since the determination circuit  25 E holds the number n of the data frames DFR_ 1  to DFR_n, it senses that the 2n frame lengths are the frame lengths of the data frames DFR_ 1  to DFR_n, and detects that the frame length received after the 2n frame lengths is the frame length L V  of the verification frame VFR. 
     Thereafter, the determination circuit  25 E calculates the average of each of (L 11 , L 12 ) to (L n1 , L n2 ) to determine the frame lengths L 1  to Ln, and, based on the determined frame lengths L 1  to Ln, calculates (L 1 +L 2 + . . . +Ln)/n or |L 1 −L 2 + . . . +Ln−1−Ln|. Then, the determination circuit  25 E determines whether (L 1 +L 2 + . . . +Ln)/n or |L 1 −L 2 + . . . +Ln−1−Ln| that has been calculated matches the frame length L V . 
     If (L 1 +L 2 + . . . +Ln)/n or |L 1 −L 2 + . . . +Ln−1−Ln| matches the frame length L V , the determination circuit  25 E determines that there is no error in the data frames DFR_ 1  to DFR_n. On the other hand, if (L 1 +L 2 + . . . +Ln)/n or |L 1 −L 2 + . . . +Ln−1−Ln| does not match the frame length L V , the determination circuit  25 E senses that there is an error in the data frames DFR_ 1  to DFR_n, and discards the frame lengths (L 11 , L 12 ) to (L 1 , L 2 ). Thus, the determination circuit  25 E senses that the receiver has failed to receive the radio frame WFR 8 . 
     If determination circuit  25 E has determined that there is no error in the data frames DFR_ 1  to DFR_n, upon receiving the last frame length L F , it refers to the correspondence table TBL 6  to detect the number of transmissions corresponding to the frame length L F , and senses the end of the data to be transmitted. Then, the determination circuit  25 E waits for the plurality of frame lengths L H , L 1 =(L 11 , L 12 ) to Ln=(L n1 , L n2 ), L V  and L F  supplied from the frame length detection circuit  24 . 
     When the determination circuit  25 E has received the plurality of frame lengths L H , L 1 =(L 11 , L 12 ) to Ln=(L n1 , L n2 ), L V  and L F , it repeats the operations described above. 
     The determination circuit  25 E repeats the operations described above the number of transmissions, and, if there is no error in the data frames DFR_ 1  to DFR_n, it determines whether the values of L 1 =(L 11 , L 12 ) to Ln=(L n1 , L n2 ) for the number of transmissions match each other. 
     If the values of L 1 =(L 11 , L 12 ) to Ln=(L n1 , L n2 ) for the number of transmissions match each other, the determination circuit  25 E outputs (L 11 , L 12 ) to (L n1 , L n2 ) to the decoder  26 . On the other hand, if the values of L 1 =(L 11 , L 12 ) to Ln=(L n1 , L n2 ) for the number of transmissions do not match each other, the determination circuit  25 E discards (L 11 , L 12 ) to (L n1 , L n2 ) and senses that the receiver has failed to receive the radio frame WFR 8 . 
       FIG. 48  is a flow chart illustrating the operation of the wireless communication system  700  of  FIG. 42 . 
     The flow chart of  FIG. 42  is the same as the flow chart of  FIG. 8  except that steps S 1 , S 2  and S 9  of the flow chart of  FIG. 8  are replaced by steps S 1 C, S 2 C and S 9 C, respectively, and steps S 35  to S 44  are added. 
     Referring to  FIG. 48 , when the operation of the wireless communication system  700  is started, the transmitter  701  generates the header frame HFR 1 , data frames DFR_ 1  to DFR_n, verification frame VFR and end frame FFR 2  in the manner described above (step S 1 C). 
     Then, the transmitter  701  sets K-total number of the header frame HFR 1 , data frames DFR_ 1  to DFR_n, verification frame VFR and end frame FFR 2  (step S 2 C). 
     Thereafter, the transmitter  701  sets t=1 (step S 35 ), and sequentially executes steps S 3  to S 8  described above. 
     Then, if it is determined at step S 7  that k=K, the transmitter  701  further determines whether t=T (i.e. number of transmissions) (step S 36 ). 
     If it is determined at step S 36  that t=T is not true, the transmitter  701  sets t=t+1 (step S 37 ). Thereafter, the operation returns to step S 3 , and steps S 3  to S 8 , steps S 36  and S 37  described above are repeatedly executed until it is determined at step S 36  that t=T. 
     If it is determined at step S 36  that t=T, the transmitter  701  ends transmission of the radio frame WFR 8 . 
     Thereafter, the receiver  702  sets r=r+1 (step S 38 ), and receives the header frame HFR 1 , data frames DFR_ 1  to DFR_n, verification frame VFR and end frame FFR 2  (step S 9 C). Here, r is the number of reception processes. 
     Then, the receiver  702  sequentially executes steps S 10  to S 13  described above. 
     After step S 13 , the receiver  702  determines whether it has detected an error in the data frames DFR_ 1  to DFR_n in the manner described above (step S 39 ). 
     If it is determined at step S 39  that no error has been detected in the data frames DFR_ 1  to DFR_n, based on the last frame length, the receiver  702  senses the end of the data to be transmitted and the number T of transmissions in the manner described above (step S 40 ). 
     Then, the receiver  702  determines whether r=T (i.e. number of transmissions) (step S 41 ). 
     If it is determined at step S 41  that r=T is not true, the receiver  702  sets r=r+1 (step S 42 ). Thereafter, the operation returns to step S 9 C and steps S 9 C, S 10  to S 13  and S 39  to S 42  described above are repeatedly executed until it is determined at step S 41  that r=T. 
     If it is determined at step S 41  that r=T the receiver  702  further determines whether the plurality of frame lengths for the number of transmissions of the data frames DFR_ 1  to DFR_n match each other (step S 43 ). 
     If it is determined at step S 43  that the plurality of frame lengths for the number of transmissions of the data frames DFR_ 1  to DFR_n match each other, the receiver  702  decodes the plurality of frame lengths into a bit sequence (step S 44 ), thereby receiving the data to be transmitted. 
     Then, if it is determined at step S 12  that the first frame length is not equal to 1190 μs, or if it is determined at step S 39  that an error has been detected in the data frames DFR_ 1  to DFR_n, or if it is determined at step S 43  that the plurality of frame lengths for the number of transmissions of the data frames DFR_ 1  to DFR_n do not match each other, or after step S 44 , the operation ends. 
     Thus, according to Embodiment 8, if no error is detected in the data frames DFR_ 1  to DFR_n, the plurality of frame lengths of the data frames DFR_ 1  to DFR_n are decoded into a bit sequence and the data to be transmitted is received. Therefore, the data frames DFR_ 1  to DFR_n could be correctly received. 
     Further, if the plurality of frame lengths for the number of transmissions of the data frames DFR_ 1  to DFR_n match each other, the plurality of frame lengths of the data frames DFR_ 1  to DFR_n are decoded into a bit sequence and the data to be transmitted is received. Therefore, the data frames DFR_ 1  to DFR_n could be yet more correctly received. 
     Since the plurality of frame lengths of the data frames DFR_ 1  to DFR_n decoded into a bit sequence are the data to be transmitted, determining whether the plurality of frame lengths for the number of transmissions of the data frames DFR_ 1  to DFR_n match each other at steps S 43  corresponds to determining whether the data sets for the number of transmissions match each other. 
       FIG. 49  is a schematic diagram of a configuration of another wireless communication system according to Embodiment 8. The wireless communication system according to Embodiment 8 may be the wireless communication system  700 A of  FIG. 49 . 
     Referring to  FIG. 49 , the wireless communication system  700 A includes a transmitter  701 A and a receiver  702 A. 
     The transmitter  701 A and receiver  702 A are positioned in a wireless communication space. The transmitter  701 A generates a header frame HFR 1  and end frame FFR 2  in the same manner as that in the transmitter  701 . 
     Further, the transmitter  701 A generates the data to be transmitted where the bit sequence representing the data to be transmitted contains a checksum. Then, the transmitter  701 A divides the data to be transmitted that has been generated into bit values with 4 bits, and refers to the correspondence table TBL 5  to convert the divided bit values to frame lengths, and generates the data frames DFR_ 1  to DFR_n having the converted frame lengths. 
     Then, the transmitter  701 A transmits the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 2  one after another in accordance with the CSMA/CA scheme. 
     Thus, since the transmitter  701 A transmits the data frames DFR_ 1  to DFR_n where a checksum for detecting an error in the data frames DFR_ 1  to DFR_n is placed on the bit sequence representing the data to be transmitted, a radio frame for the wireless communication system  700 A has the structure of the radio frame WFR 8  (see  FIG. 45 ) where the verification frame VFR is omitted. 
     The receiver  702 A receives the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 2 . Then, the receiver  702  A processes the received radio wave of the header frame HFR 1  in the same manner as that in the receiver  702 . 
     Thereafter, the receiver  702 A detects the plurality of frame lengths based on the received radio wave of the data frames DFR_ 1  to DFR_n and decodes the plurality of frame lengths that have been detected into a bit sequence. Then, based on the decoded bit sequence, the receiver  702 A determines whether there is no error in the data. 
     If there is an error in the data, the receiver  702 A discards the decoded bit sequence and determines that the receiver has failed to receive data. 
     On the other hand, if there is no error in the data, the receiver  702 A detects the frame lengths based on the received radio wave of the end frame FFR 2 , and, based on the detected frame length, detects the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     Then, the receiver  702 A detects the plurality of frame lengths based on the received radio wave of the data frames DFR_ 1  to DFR_n, decodes the plurality of frame lengths that have been detected into a bit sequence, and, based on the decoded bit sequence, determines whether there is no error in the data. The receiver  702 A repeatedly executes this process the number of transmissions. 
     When the receiver  702 A has determined that there is no error in the data the number of transmissions, it determines whether the data sets for the number of transmissions match each other. Then, when the receiver  702 A determines that the data sets for the number of transmissions match each other, it determines that it has succeeded in receiving data, and accepts the data. 
     On the other hand, if the data sets for the number of transmissions do not match each other, the receiver  702 A determines that it has failed to receive data, and discards the data. 
       FIG. 50  is a schematic diagram of the transmitter  701 A of  FIG. 49 . Referring to  FIG. 50 , the transmitter  701 A is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  of  FIG. 1  is replaced by a generating circuitry  13 F. 
     The generating circuitry  13 F holds the correspondence tables TBL 5  and TBL 6 , and the number of transmissions of the data frames DFR_ 1  to DFR_n. The generating circuitry  13 F generates the header frame HFR 1  and end frame FFR 2  in the same manner as that in the generating circuitry  13 E. 
     Further, the generating circuitry  13 F generates the data to be transmitted where the bit sequence representing the data to be transmitted contains a checksum. Then, the generating circuitry  13 F divides the data to be transmitted that has been generated into bit values with 4 bits, and refers to the correspondence table TBL 5  to convert the divided bit values to frame lengths, and generates data frames DFR_ 1  to DFR_n having the converted frame lengths. 
     Then, the generating circuitry  13 F outputs the header frame HFR 1 , data frames DFR_ 1  to DFR_n, end frame FFR 2  and the number of transmissions to the transmitting circuitry  12 . 
     In the transmitter  701 A, the transmitting circuitry  12 , repeatedly, performs, the number of transmissions, the process in which the header frame HFR 1 , data frames DFR_ 1  to DFR_n and end frame FFR 2  are transmitted in accordance with the CSMA/CA scheme. 
       FIG. 51  is a schematic diagram of the receiver  702 A of  FIG. 49 . Referring to  FIG. 51 , the receiver  702 A is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  of  FIG. 3  is replaced by a determination circuit  25 F and a control circuit  710  is added. 
     The determination circuit  25 F holds the correspondence table TBL 6 . Based on the first frame length received from the frame length detection circuit  24 , the determination circuit  25 F detects the beginning of the data to be transmitted in the same manner as that in the determination circuit  25 . 
     When the determination circuit  25 F has sensed the beginning of the data to be transmitted, it sequentially outputs the plurality of frame lengths sequentially received from the frame length detection circuit  24  to the decoder  26 . 
     When the determination circuit  25 F has received the last frame length from the frame length detection circuit  24 , it refers to the correspondence table TBL 6  to detect the number of transmissions corresponding to the last frame length and sense the end of the data to be transmitted, and outputs the detected number of transmissions to the control circuit  710 . 
     The control circuit  710  receives the bit sequence from the decoder  26  and, based on how bits are arranged in the received bit sequence, determines whether there is an error in the data. 
     If there is an error in the data, the control circuit  710  discards the decoded bit sequence and determines that the receiver has failed to receive data. 
     If there is no error in the data, the control circuit  710  repeatedly performs the above operations the number of transmissions. 
     Then, the control circuit  710  determines whether the data sets for the number of transmissions match each other. If the data sets for the number of transmissions match each other, the control circuit  710  determines that the receiver has succeeded in receiving data, and outputs the data to the host system. 
     On the other hand, if the data sets for the number of transmissions do not match each other, the control circuit  710  determines that the receiver has failed to receive data, and discards the data. 
       FIG. 52  is a flow chart illustrating the operation of the wireless communication system  700 A of  FIG. 49 . 
     The flow chart of  FIG. 52  is the same as the flow chart of  FIG. 48  except that steps S 1 C,  2 C, S 9 C, S 39 , S 43  and S 44  of the flow chart of  FIG. 48  are replaced by steps S 1 , S 2 , S 9 , S 39 A, S 43 A and S 44 A, respectively and step S 45  is added. 
     Referring to  FIG. 52 , when the operation of the wireless communication system  700 A is started, the transmitter  701 A sequentially executes steps S 1  to S 8 , S 36  and S 37  described above. In this case, at step S 1 , the transmitter  701 A generates the data to be transmitted where the bit sequence of the data to be transmitted contains a checksum. Then, based on the generated data, the transmitter  701 A generates the data frames DFR_ 1  to DFR_n in the manner described above. Further, at step S 1 , the transmitter  701 A generates the end frame FFR 2  in the manner described above. 
     The receiver  702 A sequentially executes steps S 38 , S 9  to S 13  described above. Then, after step S 13 , the receiver  702 A decodes the plurality of frame lengths of the data frames DFR_ 1  to DFR_n into a bit sequence (step S 45 ). 
     Thereafter, based on how the bits are arranged in the decoded bit sequence, the receiver  702 A determines whether it has detected an error in the data (step S 39 A). 
     If it is determined at step S 39 A that no error has been detected in the data, steps S 40  to S 42  described above are sequentially executed. 
     Then, if it is determined at step S 41  that r=T, the receiver  702 A determines whether the data sets for the number of transmissions match each other (S 45 A). 
     If it is determined at step S 43 A that the data sets for the number of transmissions match each other, the receiver  702 A determines that it has succeeded in receiving data, and accepts the data (step S 44 A). 
     Then, if it is determined at step S 12  that the first frame length is not equal to 1190 μs, or if it is determined at step S 39 A that an error has been detected in the data, or if it is determined at step S 43 A that the data sets for the number of transmissions do not match each other, or after step S 44 A, the operation ends. 
     Thus, since it is determined that the receiver has succeeded in receiving data when the data sets for the number of transmissions match each other, data could be correctly received. 
     In the above description, in the correspondence table TBL 5 , the first frame length changes in ascending order and the second frame length changes in descending order as the bit value increases; however, Embodiment 8 is not limited to such an implementation, and the first frame length may change in descending order and the second frame length may change in ascending order as the bit value increases. 
     Further, in the above description, the first and second frame lengths change by 30 μs as the bit value increases by “1”; however, Embodiment 8 is not limited to such an implementation, and the first and second frame lengths may change by an amount other than 30 μs as the bit value increases by “1”. 
     Further, the verification frame VFR does not need to be located between the data frames DFR_ 1  to DFR_n and the end frame FFR 1 , and may be located between the header frame HFR 1  and the data frames DFR_ 1  to DFR_n. 
     Further, in Embodiment 8, the operations of the transmitter  701  and receiver  702  may be carried out by a program. In this case, each of the transmitter  701  and receiver  702  includes a CPU, a ROM and a RAM. In the transmitter  701 , the ROM stores a program K including steps S 1 C, S 2 C, S 35 , S 3  to S 8 , S 36  and S 37  shown in  FIG. 48 , and the CPU reads the program K from the ROM and executes it. Thus, the operation of the transmitter  701  is performed. In the receiver  702 , the ROM stores a program L including steps S 38 , S 9 C, S 10  to S 13  and S 39  to S 44  shown in  FIG. 48 , and the CPU reads the program L from the ROM and executes it. Thus, the operation of the receiver  702  is performed. Further, each of the ROMs of the transmitter  701  and receiver  702  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Further, in Embodiment 8, the operations of the transmitter  701 A and receiver  702 A may be carried out by a program. In this case, each of the transmitter  701 A and receiver  702 A includes a CPU, a ROM and a RAM. In the transmitter  701 A, the ROM stores a program M including steps S 1 , S 2 , S 35 , S 3  to S 8 , S 36  and S 37  shown in  FIG. 52 , and the CPU reads the program M from the ROM and executes it. Thus, the operation of the transmitter  701 A is performed. In the receiver  702 A, the ROM stores a program N including steps S 38 , S 9  to S 13 , S 45 , S 39 A, S 40  to S 42 , S 43 A and S 44 A shown in  FIG. 52 , and the CPU reads the program N from the ROM and executes it. Thus, the operation of the receiver  702 A is performed. Further, each of the ROMs of the transmitter  701 A and receiver  702 A corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 8 is the same as that of Embodiment 1. 
     Embodiment 9 
       FIG. 53  is a schematic diagram of a wireless communication system according to Embodiment 9. Referring to  FIG. 53 , the wireless communication system  800  according to Embodiment 9 includes a transmitter  801  and a receiver  802 . 
     The transmitter  801  and receiver  802  are positioned in a wireless communication space. The transmitter  801  generates a header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  in the manner described below. 
     Then, the transmitter  801  transmits the header frame HFR 3 , data frames DFR_ 1  to DFR_n and end frame FFR 3  one after another in accordance with the CSMA/CA scheme, or transmits the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3  and end frame FFR 3  one after another in accordance with the CSMA/CA scheme, or transmits the header frame HFR 3 , data frames DFR_ 1  to DFR_n, verification frame VFR 3  and end frame FFR 3  one after another in accordance with the CSMA/CA scheme, or transmits the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  one after another in accordance with the CSMA/CA scheme. 
     The header frame HFR 3  has a frame length indicating the beginning of the data to be transmitted, or a frame length representing at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n, and indicating the beginning of the data to be transmitted. 
     The end frame FFR 3  has a frame length indicating the end of the data to be transmitted, or a frame length representing at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n, and indicating the end of the data to be transmitted. 
     The verification frame VFR 3  has a frame length representing at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The sub-header frame SHFR 3  has a frame length indicating a delimiter for the data frames DFR_ 1  to DFR_n, or a frame length representing at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n, and indicating a delimiter for the data frames DFR_ 1  to DFR_n. 
     The receiver  802  sequentially receives the header frame HFR 3 , data frames DFR_ 1  to DFR_n and end frame FFR 3 , or sequentially receives the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3  and end frame FFR 3 , or sequentially receives the header frame HFR 3 , data frames DFR_ 1  to DFR_n, verification frame VFR 3  and end frame FFR 3 , or sequentially receives the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3 . 
     Then, based on the frame length of the header frame HFR 3 , the receiver  802  senses the beginning of the data to be transmitted, and, depending on the demands, detects at least one of the number of the data frames DFR_ 1  to DFR_n, an error in the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     Further, the receiver  802  decodes the received radio wave of the data frames DFR_ 1  to DFR_n into a bit sequence in the manner described below. 
     Furthermore, based on the frame length of the sub-header frame SHFR 3 , the receiver  802  senses a delimiter in the data frames DFR_ 1  to DFR_n and, depending on the demands, detects at least one of the number of the data frames DFR_ 1  to DFR_n, an error in the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     Moreover, based on the frame length of the verification frame VFR 3 , the receiver  802  detects at least one of the number of the data frames DFR_ 1  to DFR_n, an error in the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     Furthermore, based on the frame length of the end frame FFR 3 , the receiver  802  senses the end of the data to be transmitted, and, depending on the demands, detects at least one of the number of the data frames DFR_ 1  to DFR_n, an error in the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
       FIG. 54  is a schematic diagram of the transmitter  801  of  FIG. 53 . Referring to  FIG. 54 , the transmitter  801  is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  of  FIG. 2  is replaced by a generating circuitry  13 G. 
     If the radio frame WFR 8  of Embodiment 9 is composed of the header frame HFR 3 , data frames DFR_ 1  to DFR_n and end frame FFR 3 , the generating circuitry  13 G generates the header frame HFR 3 , data frames DFR_ 1  to DFR_n and end frame FFR 3  in the manner described below. Then, the generating circuitry  13 G outputs the header frame HFR 3 , data frames DFR_ 1  to DFR_n and end frame FFR 3  that have been generated to the transmitting circuitry  12 . 
     If the radio frame WFR 8  of Embodiment 9 is composed of the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3  and end frame FFR 3 , the generating circuitry  13 G generates the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3  and end frame FFR 3  in the manner described below. Then, the generating circuitry  13 G outputs the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3  and end frame FFR 3  that have been generated to the transmitting circuitry  12 . 
     If the radio frame WFR 8  of Embodiment 9 is composed of the header frame HFR 3 , data frames DFR_ 1  to DFR_n, verification frame VFR 3  and end frame FFR 3 , the generating circuitry  13 G generates the header frame HFR 3 , data frames DFR_ 1  to DFR_n, verification frame VFR 3  and end frame FFR 3  in the manner described below. Then, the generating circuitry  13 G outputs the header frame HFR 3 , data frames DFR_ 1  to DFR_n, verification frame VFR 3  and end frame FFR 3  that have been generated to the transmitting circuitry  12 . 
     If the radio frame WFR 8  of Embodiment 9 is composed of the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3 , the generating circuitry  13 G generates the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  in the manner described below. Then, the generating circuitry  13 G outputs the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  that have been generated to the transmitting circuitry  12 . 
     When the transmitting circuitry  12  has received the header frame HFR 3 , data frames DFR_ 1  to DFR_n and end frame FFR 3  from the generating circuitry  13 G, it transmits the header frame HFR 3 , data frames DFR_ 1  to DFR_n and end frame FFR 3  one after another in accordance with the CSMA/CA scheme. 
     When the transmitting circuitry  12  has received the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3  and end frame FFR 3  from the generating circuitry  13 G, it transmits the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3  and end frame FFR 3  one after another in accordance with the CSMA/CA scheme. 
     When the transmitting circuitry  12  has received the header frame HFR 3 , data frames DFR_ 1  to DFR_n, verification frame VFR 3  and end frame FFR 3  from the generating circuitry  13 G, it transmits the header frame HFR 3 , data frames DFR_ 1  to DFR_n, verification frame VFR 3  and end frame FFR 3  one after another in accordance with the CSMA/CA scheme. 
     When the transmitting circuitry  12  has received the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  from the generating circuitry  13 G, it transmits the header frame HFR 3 , data frames DFR_ 1  to DFR_n, sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  one after another in accordance with the CSMA/CA scheme. 
       FIG. 55  is a schematic diagram of the receiver  802  of  FIG. 53 . Referring to  FIG. 55 , the receiver  802  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  of  FIG. 3  is replaced by a determination circuit  25 G. 
     In Embodiment 9, at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on at least one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using a frame length. 
     If only the number of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  or other frames, the determination circuit  25 G receives, from the frame length detection circuit  24 , a plurality of frame lengths located between the first frame length and the last frame length, and, if the number of the received plurality of frame lengths matches the number of the data frames DFR_ 1  to DFR_n, outputs the plurality of frame lengths to the decoder  26 . On the other hand, if the number of the plurality frame lengths does not match the number of the data frames DFR_ 1  to DFR_n, the determination circuit  25 G discards the plurality of frame lengths. 
     If only the verification information for verifying an error of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  or other frames, the determination circuit  25 G receives, from the frame length detection circuit  24 , a plurality of frame lengths located between the first frame length and the last frame length, and, based on the received plurality of frame lengths and the verification information, determines whether an error has been detected in the data frames DFR_ 1  to DFR_n. If the determination circuit  25 G determines that no error has been detected in the data frames DFR_ 1  to DFR_n, it outputs the plurality of frame lengths to the decoder  26 . On the other hand, if the determination circuit  25 G determines that an error has been detected in the data frames DFR_ 1  to DFR_n, it discards the plurality of frame lengths. 
     If only the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  or other frames, the determination circuit  25 G receives, from the frame length detection circuit  24 , the plurality of frame lengths of the data frames DFR_ 1  to DFR_n the number of transmissions, and, if the plurality of frame lengths for the number of transmissions match each other, outputs the plurality of frame lengths to the decoder  26 . On the other hand, if the plurality of frame lengths for the number of transmissions do not match each other, the determination circuit  25 G discards the plurality of frame lengths. 
     If the number of the data frames DFR_ 1  to DFR_n and the verification information for verifying an error of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  or other frames, the determination circuit  25 G receives, from the frame length detection circuit  24 , a plurality of frame lengths located between the first frame length and the last frame length, and, if the number of the received plurality of frame lengths matches the number of the data frames DFR_ 1  to DFR_n and if, based on the plurality of frame lengths and verification information, it determines that no error has been detected in the data frames DFR_ 1  to DFR_n, outputs the plurality frame lengths to the decoder  26 . On the other hand, if the number of the plurality of frame lengths does not match the number of the data frames DFR_ 1  to DFR_n and/or if the determination circuit  25 G determines that an error has been detected in the data frames DFR_ 1  to DFR_n, it discards the plurality of frame lengths. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  or other frames, the determination circuit  25 G receives, from the frame length detection circuit  24 , a plurality of frame lengths located between the first frame length and the last frame length the number of transmissions, and, if the number of the plurality of frame lengths matches the number of the data frames DFR_ 1  to DFR_n and if the plurality of frame lengths for the number of transmissions match each other, outputs the plurality of frame lengths to the decoder  26 . On the other hand, if the number of the plurality of frame lengths does not match the number of the data frames DFR_ 1  to DFR_n, and/or if the plurality of frame lengths for the number of transmissions do not match each other, the determination circuit  25 G discards the plurality of frame lengths. 
     If the verification information for verifying an error of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  or other frames, the determination circuit  25 G receives, from the frame length detection circuit  24 , a plurality of frame lengths located between the first frame length and the last frame length the number of transmissions, and, if based on the plurality of frame lengths and verification information, it determines that no error has been detected in the data frames DFR_ 1  to DFR_n and if it determines that the plurality of frame lengths for the number of transmissions match each other, outputs the plurality of frame lengths to the decoder  26 . On the other hand, if the determination circuit  25 G determines that an error has been detected in the data frames DFR_ 1  to DFR_n and/or if it determines that the plurality of frame lengths for the number of transmissions do not match each other, it discards the plurality of frame lengths. 
     If the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying an error of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  or other frames, the determination circuit  25 G receives, from the frame length detection circuit  24 , a plurality of frame lengths located between the first frame length and the last frame length the number of transmissions, and, if the number of the plurality of frame lengths matches the number of the data frames DFR_ 1  to DFR_n, and if, based on the plurality of frame lengths and verification information, it determines that no error has been detected in the data frames DFR_ 1  to DFR_n, and if it determines that the plurality of frame lengths for the number of transmissions match each other, outputs the plurality of frame lengths to the decoder  26 . On the other hand, the determination circuit  25 G discards the plurality of frame lengths if at least one of the following is true: that the number of the plurality of frame lengths does not match the number of the data frames DFR_ 1  to DFR_n; that it determines that an error has been detected in the data frames DFR_ 1  to DFR_n; and that it determines that the plurality of frame lengths for the number of transmissions do not match each other. 
       FIG. 56  conceptually illustrates a radio frame according to Embodiment 9. Referring to  FIG. 56 , a radio frame WFR 8  of Embodiment 9 is constituted by any one of radio frames WFR 8 - 1  to WFR 8 - 4 . 
     The radio frame WFR 8 - 1  includes a header frame HFR 3 , data frames DFR_ 1  to DFR_n, and an end frame FFR 3  (see  FIG. 56( a ) ). The header frame HFR 3  has a frame length indicating the beginning of the data to be transmitted, or a frame length representing at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n, and indicating the beginning of the data to be transmitted. 
     The data frames DFR_ 1  to DFR_n are constituted by the data frames DFR_ 1  to DFR_n of one of Embodiments 1 to 8 described above. 
     The end frame FFR 3  has a frame length indicating the end of the data to be transmitted, or a frame length representing at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n, and indicating the end of the data to be transmitted. 
     The radio frame WFR 8 - 2  is the same as the radio frame WFR 8 - 1  except that a sub header frame SHFR 3  is added to the radio frame WFR 8 - 1  (see  FIG. 56( b ) ). 
     The sub-header frame SHFR 3  is inserted at any position in the sequence of the data frames DFR_ 1  to DFR_n. The sub-header frame SHFR 3  has a frame length indicating a delimiter for the data frames DFR_ 1  to DFR_n, or a frame length representing at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n, and a delimiter for the data frames DFR_ 1  to DFR_n. 
     The number of sub-header frames SHFR 3  is not limited to 1 and two or more sub-header frames may be present and, in general terms, one or more sub-header frames may be present. The one or more sub-header frames SHFR 3  are inserted at any position in the sequence of the data frames DFR_ 1  to DFR_n. 
     The radio frame WFR 8 - 3  is the same as the radio frame WFR 8 - 1  except that a verification frame VFR 3  is added to the radio frame WFR 8 - 1  (see  FIG. 56( c ) ). 
     The verification frame VFR 3  is located between the data frame DFR_n and the end frame FFR 3 . The verification frame VFR 3  has a frame length representing at least one of the number of the data frames DFR_ 1  to DFR_n, verification information for verifying an error of the data frames DFR_ 1  to DFR_n, and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     Alternatively, the verification frame VFR 3  may be located between the header frame HFR 3  and the data frame DFR_ 1 . 
     The radio frame  8 - 4  is the same as the radio frame  8 - 1  except that the sub-header frame SHFR 3  and the verification frame VFR 3  are added to the radio frame WFR 8 - 1  (see  FIG. 56( d ) ). 
     The sub-header frame SHFR 3  and verification frame VFR 3  are described above. 
       FIG. 57  illustrates relationships between information and frames in the case where one of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying an error of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed thereon. 
     In  FIG. 57 , the number of the data frames DFR_ 1  to DFR_n is denoted as “A”, the verification information for verifying an error of the data frames DFR_ 1  to DFR_n (also referred to as “error verification information”) is denoted as “B”, and the number of transmissions of the data frames DFR_ 1  to DFR_n is denoted as “C”. 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 1 , each of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) is placed on the header frame HFR 3  or end frame FFR 3  by using a frame length (see table TBL- 7  of  FIG. 57( a ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 2 , each of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) is placed on one of the header frame HFR 3 , end frame FFR 3  and sub-header frame SHFR 3  by using a frame length (see table TBL- 8  of  FIG. 57( b ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 3 , each of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) is placed on one of the header frame HFR 3 , end frame FFR 3  and verification frame VRF 3  by using a frame length (see table TBL- 9  of  FIG. 57( c ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 4 , each of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) is placed on one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VRF 3  by using a frame length (see table TBL- 10  of  FIG. 57( d ) ). 
       FIGS. 58 and 59  illustrate relationships between information and frames in the case where two of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying an error of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed thereon. 
     In  FIGS. 58 and 59 , too, the number of the data frames DFR_ 1  to DFR_n is denoted as “A”, the error verification information for verifying an error of the data frames DFR_ 1  to DFR_n is denoted as “B”, and the number of transmissions of the data frames DFR_ 1  to DFR_n is denoted as “C”. 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 1 , two of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) are placed on the header frame HFR 3  and/or end frame FFR 3  by using a frame length (see table TBL- 11  of  FIG. 58( a ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 2 , two of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) are placed on one or two of the header frame HFR 3 , end frame FFR 3  and sub-header frame SHFR 3  by using a frame length (see table TBL- 12  to TBL- 14  of  FIG. 58( b ) to ( d ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 3 , two of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) are placed on one or two of the header frame HFR 3 , end frame FFR 3  and verification frame VFR 3  by using a frame length (see table TBL- 15  of  FIG. 58( e )  and tables TBL- 16  and TBL- 17  of  FIGS. 59( f ) and ( g ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 4 , two of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) are placed on one or two of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using a frame length (see tables TBL- 18  to TBL- 20  of  FIG. 59( h ) to ( j ) ). 
       FIGS. 60 to 63  illustrate relationships between information and frames in the case where all of the number of the data frames DFR_ 1  to DFR_n, the verification information for verifying an error of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed thereon. 
     In  FIGS. 60 to 63 , too, the number of the data frames DFR_ 1  to DFR_n is denoted as “A”, the error verification information for verifying an error of the data frames DFR_ 1  to DFR_n is denoted as “B”, and the number of transmissions of the data frames DFR_ 1  to DFR_n is denoted as “C”. 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 1 , all of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) are placed on the header frame HFR 3  and/or end frame FFR 3  by using a frame length (see table TBL- 21  of  FIG. 60( a ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 2 , all of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) are placed on at least one of the header frame HFR 3 , end frame FFR 3  and sub-header frame SHFR 3  by using a frame length (see tables TBL- 22  to TBL- 26  of  FIG. 60( b ) to ( f ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 3 , all of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) are placed on at least one of the header frame HFR 3 , end frame FFR 3 , and verification frame VFR 3  by using a frame length (see tables TBL- 27  to TBL- 31  of  FIG. 61( g ) to ( k ) ). 
     If the radio frame WFR 8  is constituted by the radio frame WFR 8 - 4 , all of the number of the data frames DFR_ 1  to DFR_n (i.e. A), error verification information (i.e. B) and the number of transmissions of the data frames DFR_ 1  to DFR_n (i.e. C) are placed on one to three of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using a frame length (see tables TBL- 32  to TBL- 36  of  FIG. 62( l ) to ( p )  and tables TBL- 37  to TBL- 40  of  FIG. 63( q ) to ( t ) ). 
     How at least one of the number of the data frames DFR_ 1  to DFR_n, error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on at least one of the header frame HFR 3  or other frames by using a frame length will be described. 
     (9-1) The case where all of number of data frames DFR_ 1  to DFR_n, error verification information and number of transmissions of data frames DFR_ 1  to DFR_n are placed on one frame by using a frame length 
       FIG. 64  is a correspondence table illustrating the correspondence between the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and frame length. 
       FIG. 64  illustrates the relationship between the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and frame length in an example where each of the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n is in the range of 1 to 7. 
     Referring to  FIG. 64 , the correspondence table TBL- 41  contains frame lengths, numbers of data frames, error verification information, and numbers of transmissions of data frames. The frame lengths, numbers of data frames, error verification information, and numbers of transmissions of data frames are associated with each other. 
     If all of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using a frame length, all of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are represented by a bit value with 8 bits, i.e. b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 . In this case, the 3-bit value b 1 b 2 b 3  represents the number of the data frames DFR_ 1  to DFR_n, the 2-bit value b 4 b 5  represents the error verification information, and the 3-bit value b 6 b 7 b 8  represents the number of transmissions of the data frames DFR_ 1  to DFR_n. The bit value b 4 b 5  representing the error verification information are the two lowest-order bits of the bit sequence representing the sum of the n bit sequences of the data frames DFR_ 1  to DFR_n. Thus, the bit value b 4 b 5  are one of (00), (01), (10) and (11). 
     The frame length of 500 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is 1 (i.e. “001”), the error verification information is “00”, and the number of transmissions of the data frames DFR_ 1  to DFR_n is 1 (i.e. “001”). 
     The frame length of 520 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is 1 (i.e. “001”), the error verification information is “00”, and the number of transmissions of the data frames DFR_ 1  to DFR_n is 2 (i.e. “010”). 
     Other frame lengths are assigned to other cases as shown in the table, and the frame length of 4280 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is 7 (i.e. “111”), the error verification information is “11”, and the number of transmissions of the data frames DFR_ 1  to DFR_n is 7 (i.e. “111”). 
     Thus, in the correspondence table TBL- 41 , the frame length increases by 20 μs as the bit value representing one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n increases by “1”. 
     If the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  by using a frame length, the frame length represents the beginning of the data to be transmissions, the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the sub-header frame SHFR 3  by using a frame length, the frame length represents a delimiter for data frames, the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the end frame FFR 3  by using a frame length, the frame length represents the end of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the verification frame VFR 3  by using a frame length, this frame length represents the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n, i.e. b 1 b 2 b 3 , is “100” (i.e. 4 frames), the error verification information b 4 b 5  is “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n, i.e. b 6 b 7 b 8 , is “101” (i.e. 5 times), and when these three types of information are placed on one frame, the frame length is 2360 μs. 
       FIG. 65  illustrates a specific example of the radio frame WFR 8 - 1  of  FIG. 56( a ) .  FIG. 65  describes the specific example of the radio frame WFR 8 - 1  in the case where the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  by using a frame length. 
     Referring to  FIG. 65 , the radio frame WFR 8 - 1 - 1  includes a header frame HFR 3 , data frames DFR_ 1  to DFR_ 4  and an end frame FFR 3 . 
     The header frame HFR 3  has the frame length of 2360 μs, the data frame DFR_ 1  has the frame length of 1100 μs, the data frame DFR_ 2  has the frame length of 770 μs, the data frame DFR_ 3  has the frame length of 980 μs, the data frame DFR_ 4  has the frame length of 740 μs, and the end frame FFR 3  has the frame length of 680 μs. 
     The frame length of 2360 μs of the header frame HFR 3  represents the beginning of the data to be transmitted as well as the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times). The frame length of 680 μs of the end frame FFR 3  indicates only the end of the data to be transmitted 
     If the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the end frame FFR 3  by using a frame length, the end frame FFR 3  has the frame length of 2360 μs and the header frame HFR 3  has the frame length of 1190 μs. Then, the frame length of 2360 μs of the end frame FFR 3  represents the end of the data to be transmitted as well as the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times), and the frame length of 1190 μs of the header frame HFR 3  indicates only the beginning of the data to be transmitted. 
     If a number of the data frames DFR_ 1  to DFR_n other than “100” (i.e. 4 frames), error verification information other than “01” and a number of transmissions of the data frames DFR_ 1  to DFR_n other than “101” (i.e. 5 times) are placed on the header frame HFR 3  or end frame FFR 3  of the radio frame WFR 8 - 1  by using a frame length, too, the number of the data frames DFR_ 1  to DFR_n other than “100” (i.e. 4 frames), the error verification information other than “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n other than “101” (i.e. 5 times) are placed on the header frame HFR 3  or end frame FFR 3  of the radio frame WFR 8 - 1  in the same manner as that described above. 
       FIG. 66  illustrates a specific example of the radio frame WFR 8 - 2  of  FIG. 56( b ) .  FIG. 66  also illustrates the specific example of the radio frame WFR 8 - 2  in the case where the number of the data frames DFR_ 1  to DFR_n (“100”) (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) are placed on the header frame HFR 3  by using a frame length. 
     Referring to  FIG. 66 , the radio frame WFR 8 - 2 - 1  includes a header frame HFR 3 , data frames DFR_ 1  and DFR_ 2 , a sub-header frame SHFR 3 , data frames DFR_ 3  and DFR_ 4  and an end frame FFR 3 . 
     The header frame HFR 3  has the frame length of 2360 μs, the data frame DFR_ 1  has the frame length of 1100 μs, the data frame DFR_ 2  has the frame length of 770 μs, the sub-header frame SHFR 3  has the frame length of 1280 μs, the data frame DFR_ 3  has the frame length of 980 μs, the data frame DFR_ 4  has the frame length of 740 μs, and the end frame FFR 3  has the frame length of 680 μs. 
     The frame length of 1280 μs of the sub-header frame SHFR 3  indicates a delimiter inserted into the sequence of the data frames DFR_ 1  to DFR_ 4 . 
     The frame length of 2360 μs of the header frame HFR 3  and the frame length of 680 μs of the end frame FFR 3  are described above with reference to  FIG. 65 . 
     If the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the sub-header frame SHFR 3  by using a frame length, the sub-header frame SHFR 3  has the frame length of 2360 μs, the header frame HFR 3  has the frame length of 1190 μs and the end frame FFR 3  has the frame length of 680 μs. Then, the frame length of 2360 μs of the sub-header frame SHFR 3  represents a delimiter for the data frames DFR_ 1  to DFR_ 4  as well as the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times), and the frame length of 1190 μs of the header frame HFR 3  indicates only the beginning of the data to be transmitted and the frame length of 680 μs of the end frame FFR 3  indicates only the end of the data to be transmitted. 
     If the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the end frame FFR 3  by using a frame length, the end frame FFR 3  has the frame length of 2360 μs, the header frame HFR 3  has the frame length of 1190 μs and the sub-header frame SHFR 3  has the frame length of 1280 μs. Then, the frame length of 2360 μs of the end frame FFR 3  represents the end of the data to be transmitted as well as the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times), and the frame length of 1190 μs of the header frame HFR 3  indicates only the beginning of the data to be transmitted and the frame length of 1280 μs of the sub-header frame SHFR 3  indicates only a delimiter for the data frames DFR_ 1  to DFR_ 4 . 
     If a number of the data frames DFR_ 1  to DFR_n other than “100” (i.e. 4 frames), error verification information other than “01” and a number of transmissions of the data frames DFR_ 1  to DFR_n other than “101” (i.e. 5 times) are placed on one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  of the radio frame WFR 8 - 2  by using a frame length, too, the number of the data frames DFR_ 1  to DFR_n other than “100” (i.e. 4 frames), the error verification information other than “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n other than “101” (i.e. 5 times) are placed on one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  of the radio frame WFR 8 - 2  in the same manner as that described above. 
       FIG. 67  illustrates a specific example of the radio frame WFR 8 - 3  of  FIG. 56( c ) .  FIG. 67  also illustrates the specific example of the radio frame WFR 8 - 3  in the case where the number of the data frames DFR_ 1  to DFR_n (“100”) (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) are placed on the header frame HFR 3  by using a frame length. 
     Referring to  FIG. 67 , the radio frame WFR 8 - 3 - 1  includes a header frame HFR 3 , data frames DFR_ 1  to DFR_ 4 , a verification frame VFR 3 , and an end frame FFR 3 . 
     The header frame HFR 3  has the frame length of 2360 μs, the data frame DFR_ 1  has the frame length of 1100 μs, the data frame DFR_ 2  has the frame length of 770 μs, the data frame DFR_ 3  has the frame length of 980 μs, the data frame DFR_ 4  has the frame length of 740 μs, the verification frame VFR 3  has the frame length L V , and the end frame FFR 3  has the frame length of 680 μs. 
     The frame length L V  of the verification frame VFR 3  is a frame length to detect an error in the data frames DFR_ 1  to DFR_ 4 , as described in connection with Embodiment 8. The frame length of 2360 μs of the header frame HFR 3  and the frame length of 680 μs of the end frame FFR 3  are described above with reference to  FIG. 65 . 
     Since the frame length of 2360 μs of the header frame HFR 3  includes the error verification information “01” and the frame length L V  of the verification frame VFR 3  is a frame length to detect an error in the data frames DFR_ 1  to DFR_ 4 , the radio frame WFR 8 - 3 - 1  includes two pieces of error verification information. 
     If the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the verification frame VFR 3  by using a frame length, the verification frame VFR 3  has the frame length of 2360 μs, the header frame HFR 3  has the frame length of 1190 μs and the end frame FFR 3  has the frame length of 680 μs. Then, the frame length of 2360 μs of the verification frame VFR 3  represents the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times), and the frame length of 1190 μs of the header frame HFR 3  indicates only the beginning of the data to be transmitted and the frame length of 680 μs of the end frame FFR 3  indicates only the end of the data to be transmitted. In this case, the radio frame WFR 8 - 3  includes one piece of error verification information. 
     If the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the end frame FFR 3  by using a frame length, the end frame FFR 3  has the frame length of 2360 μs, the header frame HFR 3  has the frame length of 1190 μs and the verification frame VFR 3  has the frame length L V . Then, the frame length of 2360 μs of the end frame FFR 3  represents the end of the data frames DFR_ 1  to DFR_ 4  as well as the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times), and the frame length of 1190 μs of the header frame HFR 3  indicates only the beginning of the data to be transmitted and the frame length L V  of the verification frame VFR 3  represents error verification information for detecting an error in the data frames DFR_ 1  to DFR_ 4 . In this case, too, the radio frame  8 - 3  includes two pieces of error verification information. 
     If a number of the data frames DFR_ 1  to DFR_n other than “100” (i.e. 4 frames), error verification information other than “01” and a number of transmissions of the data frames DFR_ 1  to DFR_n other than “101” (i.e. 5 times) are placed on one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  of the radio frame WFR 8 - 3  by using a frame length, too, the number of the data frames DFR_ 1  to DFR_n other than “100” (i.e. 4 frames), the error verification information other than “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n other than “101” (i.e. 5 times) are placed on one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  of the radio frame WFR 8 - 3  in the same manner as that described above. 
     Thus, if the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the header frame HFR 3  or end frame FFR 3  other than the verification frame VFR 3  by using the frame length of 2360 μs, the radio frame WFR 8 - 3  includes two pieces of error verification information; if the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the verification frame VFR 3  by using the frame length of 2360 μs, the radio frame WFR 8 - 3  includes one piece of error verification information. 
       FIG. 68  illustrates a specific example of the radio frame WFR 8 - 4  of  FIG. 56( d ) .  FIG. 68  also illustrates the specific example of the radio frame WFR 8 - 4  in the case where the number of the data frames DFR_ 1  to DFR_n (“100”) (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) are placed on the header frame HFR 3  by using a frame length. 
     Referring to  FIG. 68 , the radio frame WFR 8 - 4 - 1  includes a header frame HFR 3 , data frames DFR_ 1  and DFR_ 2 , a sub-header frame SHFR 3 , data frames DFR_ 3  and DFR_ 4 , a verification frame VFR 3 , and an end frame FFR 3 . 
     The header frame HFR 3  has the frame length of 2360 μs, the data frame DFR_ 1  has the frame length of 1100 μs, the data frame DFR_ 2  has the frame length of 770 μs, the sub-header frame SHFR 3  has the frame length of 1280 μs, the data frame DFR_ 3  has the frame length of 980 μs, the data frame DFR_ 4  has the frame length of 740 μs, the verification frame VFR 3  has the frame length L V , and the end frame FFR 3  has the frame length of 680 μs. 
     The frame length L V  of the verification frame VFR 3  is a frame length to detect an error in the data frames DFR_ 1  to DFR_ 4 , as described in connection with Embodiment 8. The frame length of 2360 μs of the header frame HFR 3  and the frame length of 680 μs of the end frame FFR 3  are described above with reference to  FIG. 65 . Further, the frame length of 1280 μs of the sub-header frame SHFR 3  is described above with reference to  FIG. 66 . 
     Since the frame length of 2360 μs of the header frame HFR 3  includes the error verification information “01” and the frame length L V  of the verification frame VFR 3  is a frame length to detect an error in the data frames DFR_ 1  to DFR_ 4 , the radio frame WFR 8 - 4 - 1  includes two pieces of error verification information. 
     If the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the verification frame VFR 3  by using a frame length, the verification frame VFR 3  has the frame length of 2360 μs, the header frame HFR 3  has the frame length of 1190 μs, the sub-header frame SHFR 3  has the frame length of 1280 μs, and the end frame FFR 3  has the frame length of 680 μs. Then, the frame length of 2360 μs of the verification frame VFR 3  represents the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times), and the frame length of 1190 μs of the header frame HFR 3  indicates only the beginning of the data to be transmitted, the sub-header frame SHFR 3  indicates only a delimiter for the data frames DFR_ 1  to DFR_ 4 , and the frame length of 680 μs of the end frame FFR 3  indicates only the end of the data to be transmitted. In this case, the radio frame WFR 8 - 4  includes one piece of error verification information. 
     If the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the end frame FFR 3  by using a frame length, the end frame FFR 3  has the frame length of 2360 μs, the header frame HFR 3  has the frame length of 1190 μs, the sub-header frame SHFR 3  has the frame length of 1280 μs, and the verification frame VFR 3  has the frame length L V . Then, the frame length of 2360 μs of the end frame FFR 3  represents the end of the data frames DFR_ 1  to DFR_ 4  as well as the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times), and the frame length of 1190 μs of the header frame HFR 3  indicates only the beginning of the data to be transmitted, the sub-header frame SHFR 3  indicates only a delimiter for the data frames DFR_ 1  to DFR_ 4 , and the frame length L V  of the verification frame VFR 3  represents error verification information for detecting an error in the data frames DFR_ 1  to DFR_ 4 . In this case, too, the radio frame  8 - 4  includes two pieces of error verification information. 
     If the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the sub-header frame SHFR 3  by using a frame length, the sub-header frame SHFR 3  has the frame length of 2360 μs, the header frame HFR 3  has the frame length of 1190 μs, the verification frame VFR 3  has the frame length L V , and the end frame FFR 3  has the frame length of 680 μs. Then, the frame length of 2360 μs of the header frame HFR 3  represents a delimiter for the data frames DFR_ 1  to DFR_ 4  as well as the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times), and the frame length of 1190 μs of the header frame HFR 3  indicates only the beginning of the data to be transmitted, the frame length L V  of the verification frame VFR 3  represents error verification information for detecting an error in the data frames DFR_ 1  to DFR_ 4 , and the end frame FFR 3  indicates only the end of the data to be transmitted. In this case, too, the radio frame  8 - 4  includes two pieces of error verification information. 
     If a number of the data frames DFR_ 1  to DFR_n other than “100” (i.e. 4 frames), error verification information other than “01” and a number of transmissions of the data frames DFR_ 1  to DFR_n other than “101” (i.e. 5 times) are placed on one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  of the radio frame WFR 8 - 4  by using a frame length, too, the number of the data frames DFR_ 1  to DFR_n other than “100” (i.e. 4 frames), the error verification information other than “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n other than “101” (i.e. 5 times) are placed on one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  of the radio frame WFR 8 - 4  in the same manner as that described above. 
     Thus, if the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  other than the verification frame VFR 3  by using the frame length of 2360 μs, then, the radio frame WFR 8 - 4  includes two pieces of error verification information; if the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the verification frame VFR 3  by using the frame length of 2360 μs, the radio frame WFR 8 - 4  includes one piece of error verification information. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL- 41 , and refers to the correspondence table TBL 1  to generate data frames DFR_ 1  to DFR_ 4  having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL- 41  to determine a frame length representing the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the determined frame length. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that for the generating circuitry  13 , generating a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     (i) Receiving Operation for Radio Frame WFR 8 - 1 - 1   
     The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL- 41 . If the receiver  802  receives the radio frame WFR 8 - 1 - 1 , the frame length detection circuit  24  detects the frame lengths of 2360 μs, 1100 μs, 770 μs, 980 μs, 740 μs and 680 μs in the manner described above, and sequentially outputs the frame lengths of 2360 μs, 1100 μs, 770 μs, 980 μs, 740 μs and 680 μs that have been detected to the determination circuit  25 G. 
     When the determination circuit  25 G has received the first frame length (i.e. 2360 μs), it senses the beginning of the data to be transmitted based on the frame length of 2360 μs. Then, the determination circuit  25 G determines which of the correspondence tables TBL 1  and TBL- 41  contains the frame length of 2360 μs, and determines that the correspondence table TBL- 41  contains the frame length of 2360 μs. Then, the determination circuit  25 G refers to the correspondence table TBL- 41  to detect the number of the data frames DFR_ 1  to DFR_n “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) that are associated with the frame length of 2360 μs. 
     Thereafter, the determination circuit  25 G receives the frame lengths of 1100 μs, 770 μs, 980 μs, 740 μs and 680 μs from the frame length detection circuit  24 , and senses the end of the data to be transmitted based on the frame length of 680 which has been received last. Then, the determination circuit  25 G determines whether the number of frame lengths between the frame length of 2360 μs and the frame length of 680 μs (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) match the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames). Further, the determination circuit  25 G receives, from the frame length detection circuit  24 , the frame lengths of 2360 μs, 1100 μs, 770 μs, 980 μs, 740 μs and 680 μs for the number of transmissions “101” (i.e. 5 times), and extracts, from the frame lengths of 2360 μs, 1100 μs, 770 μs, 980 μs, 740 μs and 680 μs for the number of transmissions “101” (i.e. 5 times) that has been received, the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs of the data frames DFR_ 1  to DFR_ 4  the number of transmissions “101” (i.e. 5 times). Then, the determination circuit  25 G determines whether the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) match each other. 
     Then, if the determination circuit  25 G determines that the number of the frame lengths between the frame length of 2360 μs and the frame length of 680 μs (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) matches the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames) and determines that the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) match each other, then, it outputs the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and error verification information “01” to the decoder  26 . 
     When the decoder  26  has received the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and the error verification information “01” from the determination circuit  25 G, it refers to the correspondence table TBL 1  to convert the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs to four bit sequences “1101”, “0010”, “1001” and “0001” in the manner described above, and calculates the sum “1101” of the converted four bit sequences “1101”, “0010”, “1001” and “0001”. Then, from the bit sequence “11001” which represents the calculated sum, the decoder  26  detects the two lowest-order bits “01”, and determines whether the detected 2-bit value 01” matches the error verification information “01”. 
     In this case, since the detected 2-bit value “01” matches the error verification information “01”, the decoder  26  determines that no error has been detected in the data frames DFR_ 1  to DFR_ 4 , and outputs the bit sequence “1101001010010001”, which is obtained by arranging the four bit sequences “1101”, “0010”, “1001” and “0001” in order, as the data to be transmitted. 
     If the determination circuit  25 G determines that the number of the frame lengths between the frame length of 2360 μs and the frame length of 680 μs (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) does not match the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), or if it determines that the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) do not match each other, it discards the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and determines that the receiver failed to receive the data to be transmitted. Further, if the detected 2-bit value does not match the error verification information, the decoder  26  determines that an error has been detected in the data frames DFR_ 1  to DFR_n and discards the four bit sequences “1101”, “0010”, “1001” and “0001”. 
     If the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the end frame FFR 3  by using a frame length, the determination circuit  25 G of the receiver  802  sequentially receives, from the frame length detection circuit  24 , the frame lengths of 1190 μs, 1100 μs, 770 μs, 980 μs, 740 μs and 2360 μs. 
     Then, based on the first frame length (i.e. 1190 μs), the determination circuit  25 G senses the beginning of the data to be transmitted, and, based on the frame length of 2360 μs which has been received last, detects the end of the data to be transmitted as well as the number of the data frames DFR_ 1  to DFR_ 4  “100”, the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times). 
     Thereafter, the determination circuit  25 G performs the same operations as those described above, and the decoder  26  outputs the data to be transmitted in accordance with the operations described above. 
     (ii) Receiving Operation for Radio Frame WFR 8 - 2 - 1   
     If the receiver  802  receives the radio frame WFR 8 - 2 - 1 , the frame length detection circuit  24  detects the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs and 680 μs in the manner described above, and sequentially outputs the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs and 680 μs that have been detected to the determination circuit  25 G. 
     When the determination circuit  25 G has received the first frame length (i.e. 2360 μs), it senses the beginning of the data to be transmitted based on the frame length of 2360 μs. Then, the determination circuit  25 G determines which of the correspondence tables TBL 1  and TBL- 41  contains the frame length of 2360 μs, and determines that the corresponding table TBL- 41  contains the frame length of 2360 μs. Then, the determination circuit  25 G refers to the correspondence table TBL- 41  to detect the number of the data frames DFR_ 1  to DFR_n “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) that are associated with the frame length of 2360 μs. 
     Thereafter, the determination circuit  25 G recognizes a predetermined number (i.e. 2) of frame lengths (i.e. 1100 μs and 770 μs) following the first frame length (i.e. 2360 μs) as the frame lengths of the data frames, and, based on the frame length of 1280 μs, senses a delimiter for the data frames. Then, the determination circuit  25 G recognizes a predetermined number (i.e. 2) of frame lengths (i.e. 980 μs and 740 μs) following the frame length of 1280 μs as the frame lengths of the data frames, and, based on the frame length of 680 μs which has been received last, senses the end of the data to be transmitted. 
     Then, the determination circuit  25 G determines whether the number of the frame lengths sandwiched between the frame length of 2360 μs, the frame length of 1280 μs and the frame length of 680 μs (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) matches the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames). Further, the determination circuit  25 G receives, from the frame length detection circuit  24 , the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs and 680 μs for the number of transmissions “101” (i.e. 5 times), and extracts, from the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs and 680 μs for the number of transmissions “101” (i.e. 5 times) that has been received, the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs of the data frames DFR_ 1  to DFR_ 4  the number of transmissions “101” (i.e. 5 times). Then, the determination circuit  25 G determines whether the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) match each other. 
     Then, if the determination circuit  25 G determines that the number of the frame lengths sandwiched between the frame length of 2360 μs, the frame length of 1280 μs and the frame length of 680 μs (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) matches the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), and determines that the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) match each other, it outputs the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and the error verification information “01” to the decoder  26 . 
     Thereafter, the decoder  26  outputs the bit sequence “1101001010010001” as the data to be transmitted in accordance with the operations described above. 
     If the determination circuit  25 G determines that the number of the frame lengths sandwiched between the frame length of 2360 μs, the frame length of 1280 μs and the frame length of 680 μs (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) does not match the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), or if it determines that the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) do not match each other, then, it discards the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and determines that the receiver has failed to receive the data to be transmitted. 
     If the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the sub-header frame SHFR 3  by using a frame length, the determination circuit  25 G of the receiver  802  sequentially receives, from the frame length detection circuit  24 , the frame lengths of 1190 μs, 1100 μs, 770 μs, 2360 μs, 980 μs, 740 μs and 680 μs. 
     Then, based on the first frame length (i.e. 1190 μs), the determination circuit  25 G senses the beginning of the data to be transmitted, and recognizes a predetermined number (i.e. 2) of frame lengths (i.e. 1100 μs and 770 μs) following the first frame length (i.e. 1190 μs) as the frame lengths of the data frames. Thereafter, based on the frame length of 2360 μs, the determination circuit  25 G senses a delimiter for data frames and determines which of the correspondence table TBL 1  and TBL- 41  contains the frame length of 2360 μs. Then, if the determination circuit  25 G determines that the correspondence table TBL- 41  contains the frame length of 2360 μs, it refers to the correspondence table TBL- 41  and detects the number of the data frames DFR_ 1  to DFR_n “100” (i.e. 4), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) that are associated with the frame length of 2360 μs. 
     Thereafter, the determination circuit  25 G performs the same operations as those described above, and the decoder  26  outputs the data to be transmitted in accordance with the operations described above. 
     Otherwise, the description of the receiving operation for the radio frame WFR 8 - 2 - 1  is the same as that of the receiving operation for the radio frame WFR 8 - 1 - 1 . 
     (iii) Receiving Operation for Radio Frame WFR 8 - 3 - 1   
     If the receiver  802  receives the radio frame WFR 8 - 3 - 1 , the frame length detection circuit  24  detects the frame lengths of 2360 μs, 1100 μs, 770 μs, 980 μs, 740 μs, L V , and 680 μs in the manner described above, and sequentially outputs the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs, L V  and 680 μs that have been detected to the determination circuit  25 G. 
     When the determination circuit  25 G has received the first frame length (i.e. 2360 μs), it senses the beginning of the data to be transmitted based on the frame length of 2360 μs. Then, the determination circuit  25 G determines which of the correspondence tables TBL 1  and TBL- 41  contains the frame length of 2360 μs, and determines that the corresponding table TBL- 41  contains the frame length of 2360 μs. Then, the determination circuit  25 G refers to the correspondence table TBL- 41  to detect the number of the data frames DFR_ 1  to DFR_n “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) that are associated with the frame length of 2360 μs. 
     Thereafter, the determination circuit  25 G recognizes the frame lengths (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) following the first frame length (i.e. 2360 μs) as the frame lengths of the data frames, and, based on the frame length L V , senses the error verification information. Then, based on the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and frame length L V , the determination circuit  25 G determines whether an error has been detected in the data frames DFR_ 1  to DFR_n in the manner described in connection with Embodiment 8. Subsequently, based on the frame length of 680 μs which has been received last, the determination circuit  25 G senses the end of the data to be transmitted. 
     Then, the determination circuit  25 G determines whether the number of the frame lengths between the frame length of 2360 μs and the frame length L V  (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) matches the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames). Further, the determination circuit  25 G receives, from the frame length detection circuit  24 , the frame lengths of 2360 μs, 1100 μs, 770 μs, 980 μs, 740 μs, L V  and 680 μs for the number of transmissions “101” (i.e. 5 times), and extracts, from the frame lengths of 2360 μs, 1100 μs, 770 μs, 980 μs, 740 μs, L V  and 680 μs for the number of transmissions “101” (i.e. 5 times) that has been received, the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs of the data frames DFR_ 1  to DFR_ 4  the number of transmissions “101” (i.e. 5 times). Then, the determination circuit  25 G determines whether the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) match each other. 
     Then, if the determination circuit  25 G determines that the number of the frame lengths between the frame length of 2360 μs and the frame length L V  (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) matches the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), determines that no error has been detected in the data frames DFR_ 1  to DFR_ 4 , and determines that the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) match each other, it outputs the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and the error verification information “01” to the decoder  26 . 
     Thereafter, the decoder  26  outputs the bit sequence “1101001010010001” as the data to be transmitted in accordance with the operations described above. In this case, based on the error verification information “01” and the four bit sequences of the data frames DFR_ 1  to DFR_ 4 , the decoder  26  determines that no error has been detected in the data frames DFR_ 1  to DFR_ 4 . 
     Therefore, if the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the header frame HFR 3  by using a frame length, the receiver  802  uses the determination circuit  25 G and decoder  26  to determine that no error has been detected in the data frames DFR_ 1  to DFR_ 4  in different manners. As a result, the data to be transmitted could be received still more correctly. 
     If the determination circuit  25 G determines that the number of the frame lengths between the frame length of 2360 μs and the frame length L V  (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) does not match the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), or if it determines that an error has been detected in the data frames DFR_ 1  to DFR_ 4 , or if it determines that the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) do not match each other, it discards the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and determines that the receiver has failed to receive the data to be transmitted. 
     If the number of the data frames DFR_ 1  to DFR_ 4 , the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  are placed on the verification frame VFR 3  by using a frame length, the determination circuit  25 G of the receiver  802  sequentially receives, from the frame length detection circuit  24 , the frame lengths of 1190 μs, 1100 μs, 770 μs, 980 μs, 740 μs, 2360 μs and 680 μs. 
     Then, based on the first frame length (i.e. 1190 μs), the determination circuit  25 G senses the beginning of the data to be transmitted, and recognizes the frame lengths (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) following the first frame length (i.e. 1190 μs) as the frame lengths of the data frames. Thereafter, the determination circuit  25 G determines which of the correspondence tables TBL 1  and TBL- 41  contains the frame length of 2360 μs, and determines that the correspondence table TBL- 41  contains the frame length of 2360 μs. Then, the determination circuit  25 G refers to the correspondence table TBL- 41  to detect the number of the data frames DFR_ 1  to DFR_n “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) that are associated with the frame length of 2360 μs. 
     Thereafter, the determination circuit  25 G performs the same operations as those described above, and the decoder  26  outputs the data to be transmitted in accordance with the operations described above. In this case, the receiver  802  uses only the decoder  26  to determine whether an error has been detected in the data frames DFR_ 1  to DFR_ 4 . 
     If the number of the data frames DFR_ 1  to DFR_ 4 , the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  are placed on the end frame FFR 3  by using a frame length, the receiver  802  uses the determination circuit  25 G and decoder  26  to determine whether an error has been detected in the data frames DFR_ 1  to DFR_ 4  in different manners. 
     Otherwise, the description of the receiving operation for the radio frame WFR 8 - 3 - 1  is the same as that of the receiving operation for the radio frame WFR 8 - 1 - 1 . 
     (iv) Receiving Operation for Radio Frame WFR 8 - 4 - 1   
     If the receiver  802  receives the radio frame WFR 8 - 4 - 1 , the frame length detection circuit  24  detects the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs, L V , and 680 μs in the manner described above, and sequentially outputs the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs, L V  and 680 μs that have been detected to the determination circuit  25 G. 
     When the determination circuit  25 G has received the first frame length (i.e. 2360 μs), it senses the beginning of the data to be transmitted based on the frame length of 2360 μs. Then, the determination circuit  25 G determines which of the correspondence tables TBL 1  and TBL- 41  contains the frame length of 2360 μs, and determines that the corresponding table TBL- 41  contains the frame length of 2360 μs. Then, the determination circuit  25 G refers to the correspondence table TBL- 41  to detect the number of the data frames DFR_ 1  to DFR_n “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n “101” (i.e. 5 times) that are associated with the frame length of 2360 μs. 
     Thereafter, the determination circuit  25 G recognizes a predetermined number (i.e. 2) of frame lengths (i.e. 1100 μs and 770 μs) following the first frame length (i.e. 2360 μs) as the frame lengths of the data frames, and, based on the frame length of 1280 μs, senses a delimiter for the data frames. Then, the determination circuit  25 G recognizes a predetermined number (i.e. 2) of frame lengths (i.e. 980 μs and 740 μs) following the frame length of 1280 μs as the frame lengths of the data frames, and, based on the frame length L V , senses the error verification information. 
     Then, based on the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and the frame length L V , the determination circuit  25 G determines whether an error has been detected in the data frames DFR_ 1  to DFR_n in the manner described in connection with Embodiment 8. Subsequently, based on the frame length of 680 μs which has been received last, the determination circuit  25 G senses the end of the data to be transmitted. 
     Then, the determination circuit  25 G determines whether the number of the frame lengths sandwiched between the frame length of 2360 μs, the frame length of 1280 μs and the frame length L V  (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) matches the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames). Further, the determination circuit  25 G receives, from the frame length detection circuit  24 , the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs, L V  and 680 μs for the number of transmissions “101” (i.e. 5 times), and extracts, from the frame lengths of 2360 μs, 1100 μs, 770 μs, 1280 μs, 980 μs, 740 μs, L V  and 680 μs for the number of transmissions “101” (i.e. 5 times) that has been received, the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs of the data frames DFR_ 1  to DFR_ 4  the number of transmissions “101” (i.e. 5 times). Then, the determination circuit  25 G determines whether the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) match each other. 
     Then, if the determination circuit  25 G determines that the number of the frame lengths sandwiched between the frame length of 2360 μs, the frame length of 1280 μs and the frame length L V  (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) matches the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), determines that no error has been detected in the data frames DFR_ 1  to DFR_ 4 , and if it is determined that the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) match each other, the determination circuit  25 G outputs the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and error verification information “01” to the decoder  26 . 
     Thereafter, the decoder  26  outputs the bit sequence “1101001010010001” as the data to be transmitted in accordance with the operations described above. In this case, the decoder  26  determines that no error has been detected in the data frames DFR_ 1  to DFR_ 4  based on the error verification information “01” and the four bit sequences of the data frames DFR_ 1  to DFR_ 4 . 
     Therefore, if the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), the error verification information “01” and the number of transmissions of the data frames DFR_ 1  to DFR_ 4  “101” (i.e. 5 times) are placed on the header frame HFR 3  by using a frame length, the receiver  802  uses the determination circuit  25 G and decoder  26  to determine that no error has been detected in the data frames DFR_ 1  to DFR_ 4  in different manners. As a result, the data to be transmitted could be received still more correctly. 
     If the determination circuit  25 G determines that the number of the frame lengths sandwiched between the frame length of 2360 μs, the frame length of 1280 μs and the frame length L V  (i.e. 1100 μs, 770 μs, 980 μs and 740 μs) does not match the number of the data frames DFR_ 1  to DFR_ 4  “100” (i.e. 4 frames), or if it determines that an error has been detected in the data frames DFR_ 1  to DFR_ 4 , or it determines that the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs for the number of transmissions “101” (i.e. 5 times) do not match each other, it discards the frame lengths of 1100 μs, 770 μs, 980 μs and 740 μs and determines that the receiver has failed to receive the data to be transmitted. 
     The receiving operations performed when the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DRF_ 1  to DFR_n are placed on the end frame FFR 3  by using a frame length, when such information is placed on the sub-header frame SHFR 3 , and if such information is placed on the verification frame VFR 3  are the same as those for the radio frames WFR 8 - 1 - 1 , WFR 8 - 2 - 1  and WFR 8 - 3 - 1 , described above. 
     As described above, in the receiving operations for the radio frame WFR 8 - 4 - 1 , if the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using a frame length, the receiver  802  uses the determination circuit  25 G and decoder  26  to determine whether an error has been detected in the data frames DFR_ 1  to DFR_n in different manners; if the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the verification frame VFR 3  by using a frame length, the receiver  802  uses only the decoder  26  to determine whether an error has been detected in the data frames DFR_ 1  to DFR_n. 
     (9-2) The case where all of number of data frames DFR_ 1  to DFR_n, error verification information and number of transmissions of data frames DFR_ 1  to DFR_n are placed on a plurality of frames by using frame lengths 
     If all of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on a plurality of frames by using frame lengths, the following versions are possible: the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on one frame by using a frame length and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on another frame by using a frame length; the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one frame by using a frame length and the number of the data frames DFR_ 1  to DFR_n is placed on another frame by using a frame length; the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one frame by using a frame length and the error verification information is placed on another frame by using a frame length; and the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on different one frame, respectively, by using a frame length. 
     (9-2-1) The case where number of data frames DFR_ 1  to DFR_n and error verification information are placed on one frame by using frame length and number of transmissions of data frames DFR_ 1  to DFR_n are placed on another frame by using frame length 
       FIG. 69  is a correspondence table illustrating the relationship between the number of the data frames DFR_ 1  to DFR_n and error verification information, and frame length. 
       FIG. 69  illustrates the correspondence between the number of the data frames DFR_ 1  to DFR_n and error verification information, and frame length in an example where the number of the data frames DFR_ 1  to DFR_n is in the range of 1 to 7. 
     Referring to  FIG. 69 , the correspondence table TBL- 42  contains frame lengths, numbers of data frames, and error verification information. The frame lengths, numbers of data frames and error verification information are associated with each other. 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using a frame length, the number of the data frames DFR_ 1  to DFR_n and the error verification information are represented as a 5-bit value b 1 b 2 b 3 b 4 b 5 . In this case, the 3-bit value b 1 b 2 b 3  represents the number of the data frames DFR_ 1  to DFR_n, and the 2-bit value b 4 b 5  represents the error verification information. The details of the bit value b 4 b 5  representing the error verification information are described above. 
     The frame length of 505 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is 1 (i.e. “001”) and the error verification information is “00”. 
     The frame length of 525 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is 1 (i.e. “001”) and the error verification information is “01”. 
     In the same manner, the frame length of 1045 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is 7 (i.e. “111”) and the error verification information is “11”. 
     Thus, in the correspondence table TBL- 42 , the frame length increases by 20 μs as the bit value representing one of the number of the data frames DFR_ 1  to DFR_n and the error verification information increases by “1”. 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are to be placed on the header frame HFR 3  by using a frame length, this frame length represents the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are to be placed on the sub-header frame SHFR 3  by using a frame length, this frame length represents a delimiter for the data frames, the number of the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are to be placed on the end frame FFR 3  by using a frame length, this frame length represents the end of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are to be placed on the verification frame VFR 3  by using a frame length, this frame length represents the number of the data frames DFR_ 1  to DFR_n and the error verification information. 
     The number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using the frame length that corresponds to the number of the data frames DFR_ 1  to DFR_n and error verification information in the correspondence table TBL- 42 , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using the frame length that corresponds to the number of transmissions of the data frames DFR_ 1  to DFR_n in the correspondence table TBL 6  (see  FIG. 47 ). 
     If the radio frame is constituted by the radio frame WFR 8 - 1 , the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on the header frame HFR 3  or end frame FFR 3  by using a frame length on the correspondence table TBL- 42 , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  or header frame HFR 3  by using a frame length on the correspondence table TBL 6 . 
     If the radio frame is constituted by the radio frame WFR 8 - 2 , the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 42 , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 6 . For example, the number of the data frames DFR_ 1  to DFR_n and the error verification information may be placed on the header frame HFR 3 , and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the sub-header frame SHFR 3 . 
     If the radio frame is constituted by the radio frame WFR 8 - 3 , the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 42 , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 6 . For example, the number of the data frames DFR_ 1  to DFR_n and the error verification information may be placed on the header frame HFR 3 , and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the end frame FFR 3 . 
     If the radio frame is constituted by the radio frame WFR 8 - 4 , the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 42 , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 6 . For example, the number of the data frames DFR_ 1  to DFR_n and the error verification information may be placed on the sub-header frame SHFR 3 , and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the verification frame VFR 3 . 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1 , TBL 6  and TBL- 42 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL- 42  to determine a frame length that represents the number of the data frames DFR_ 1  to DFR_n and the error verification information, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Further, the generating circuitry  13 G refers to the correspondence table TBL 6  to generate an end frame FFR 3  (or sub-header frame SHFR 3  or verification frame VFR 3  or header frame HFR 3 ) having the frame length that corresponds to the number of transmissions of the data frames DFR_ 1  to DFR_n. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1 , TBL 6  and TBL- 42 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the received plurality of frame lengths, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the error verification information, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G detects the number of the data frames DFR_ 1  to DFR_n and the error verification information based on the frame length of one frame such as the header frame HFR 3 , and detects the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame length of the other one frame. 
     Thereafter, the determination circuit  25 G and decoder  26  performs the operations described in section (9-1), and outputs the data to be transmitted. 
     (9-2-2) The case where error verification information and number of transmissions of data frames DFR_ 1  to DFR_n are placed on one frame by using frame length and number of data frames DFR_ 1  to DFR_n is placed on another frame by using frame length 
       FIG. 70  is a correspondence table illustrating the correspondence between the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and frame length. 
       FIG. 70  illustrates the correspondence between the number of transmissions of the data frames DFR_ 1  to DFR_n and error verification information, and frame length in an example where the number of transmissions of the data frames DFR_ 1  to DFR_n is in the range of 1 to 7. 
     Referring to  FIG. 70 , the correspondence table TBL- 43  contains frame lengths, error verification information and number of transmissions of data frames. The frame lengths, error verification information and number of transmissions of data frames are associated with each other. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using a frame length, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are represented as a 5-bit value b 4 b 5 b 6 b 7 b 8 . In this case, the 2-bit value b 4 b 5  represents the error verification information and the 3-bit value b 6 b 7 b 8  represents the number of transmissions of the data frames DFR_ 1  to DFR_n. The details of the bit value b 4 b 5  representing the error verification information are described above. 
     The frame length of 510 μs is assigned to the case where the error verification information is “00” and the number of transmissions of the data frames DFR_ 1  to DFR_n is 1 (i.e. “001”). 
     The frame length of 530 μs is assigned to the case where the error verification information is “01” and the number of transmissions of the data frames DFR_ 1  to DFR_n is 1 (i.e. “001”). 
     In the same manner, the frame length of 1050 μs is assigned to the case where the error verification information is “11” and the number of transmissions of the data frames DFR_ 1  to DFR_n is 7 (i.e. “111”). 
     Thus, in the correspondence table TBL- 43 , the frame length increases by 20 μs as the bit value representing one of the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n increases by “1”. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  by using a frame length, this frame length represents the beginning of the data to be transmitted, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the sub-header frame SHFR 3  by using a frame length, this frame length represents a delimiter for the data frames, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the end frame FFR 3  by using a frame length, this frame length represents the end of the data to be transmitted, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the verification frame VFR 3  by using a frame length, this frame length represents the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using the frame length that corresponds to the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n in the correspondence table TBL- 43 , and the number of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using the frame length that corresponds to the number of the data frames DFR_ 1  to DFR_n in the correspondence table TBL 2  (see  FIG. 12 ). The correspondence table TBL 2  illustrates the relationship between the number of data frames and the frame length of a header frame, however, in Embodiment 9, the frame length of a header frame on the correspondence table  2  may be replaced by one of the frame length of the end frame FFR 3 , the frame length of the sub-header frame SHFR 3 , and the frame length of the verification frame VFR 3 . 
     If the radio frame is constituted by the radio frame WFR 8 - 1 , the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  or end frame FFR 3  by using a frame length on the correspondence table TBL- 43 , and the number of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  or header frame HFR 3  by using a frame length on the correspondence table TBL 2 . 
     If the radio frame is constituted by the radio frame WFR 8 - 2 , the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 43 , and the number of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 2 . For example, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 , and the number of the data frames DFR_ 1  to DFR_n may be placed on the sub-header frame SHFR 3 . 
     If the radio frame is constituted by the radio frame WFR 8 - 3 , the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 43 , and the number of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 2 . For example, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 , and the number of the data frames DFR_ 1  to DFR_n may be placed on the end frame FFR 3 . 
     If the radio frame is constituted by the radio frame WFR 8 - 4 , the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 43 , and the number the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 2 . For example, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the sub-header frame SHFR 3 , and the number of the data frames DFR_ 1  to DFR_n may be placed on the verification frame VFR 3 . 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1 , TBL 2  and TBL- 43 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL- 43  to determine a frame length that represents the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Further, the generating circuitry  13 G refers to the correspondence table TBL 2  to generate an end frame FFR 3  (or sub-header frame SHFR 3  or verification frame VFR 3  or header frame HFR 3 ) having the frame length that corresponds to the number of the data frames DFR_ 1  to DFR_n. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1 , TBL 2  and TBL- 43 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the error verification information, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G detects the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame length of one frame such as the header frame HFR 3 , and detects the number of the data frames DFR_ 1  to DFR_n based on the frame length of the other one frame. 
     Thereafter, the determination circuit  25 G and decoder  26  performs the operations described in section (9-1), and outputs the data to be transmitted. 
     (9-2-3) The case where number of data frames DFR_ 1  to DFR_n and number of transmissions of data frames DFR_ 1  to DFR_n are placed on one frame by using frame length and error verification information is placed on another one frame by using frame length 
       FIG. 71  is a correspondence table illustrating the correspondence between the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n, and frame length. 
       FIG. 71  illustrates the correspondence between the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n, and frame length in an example where each of the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n is in the range of 1 to 7. 
     Referring to  FIG. 71 , the correspondence table TBL- 43  contains frame lengths, numbers of data frames, and numbers of transmissions of data frames. The frame lengths, numbers of data frames and number of transmissions of data frames are associated with each other. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using a frame length, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are represented as a 6-bit value b 1 b 2 b 3 b 6 b 7 b 8 . In this case, the 3-bit value b 1 b 2 b 3  represents the number of the data frames DFR_ 1  to DFR_n, and the 3-bit value b 6 b 7 b 8  represents the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The frame length of 515 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is “001” (i.e. 1 frame) and the number of transmissions of the data frames DFR_ 1  to DFR_n is 1 “001”. 
     The frame length of 535 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is “001” and the number of transmissions of the data frames DFR_ 1  to DFR_n is 2 (i.e. “010”). 
     In the same manner, the frame length of 1475 μs is assigned to the case where the number of the data frames DFR_ 1  to DFR_n is “111” (7 frames) and the number of transmissions of the data frames DFR_ 1  to DFR_n is 7 (i.e. “111”). 
     Thus, in the correspondence table TBL- 44 , the frame length increases by 20 μs as the bit value representing one of the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n increases by “1”. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  by using a frame length, this frame length represents the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the sub-header frame SHFR 3  by using a frame length, this frame length represents a delimiter for the data frames, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the end frame FFR 3  by using a frame length, this frame length represents the end of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the verification frame VFR 3  by using a frame length, this frame length represents the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using the frame length that corresponds to the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n in the correspondence table TBL- 44 , and the error verification information is placed on another one of the header frame HFR 3 , end frame FFR 3 , sub-header frame SHFR 3  and verification frame VFR 3  by using the frame length L V  described in Embodiment 8. 
     If the radio frame is constituted by the radio frame WFR 8 - 1 , the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  or end frame FFR 3  by using a frame length on the correspondence table TBL- 44 , and the error verification information is placed on the end frame FFR 3  or header frame HFR 3  by using the frame length L V . 
     If the radio frame is constituted by the radio frame WFR 8 - 2 , the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 44 , and the error verification information is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using the frame length L V . For example, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 , and the error verification information may be placed on the sub-header frame SHFR 3 . 
     If the radio frame is constituted by the radio frame WFR 8 - 3 , the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 44 , and the error verification information is placed on another one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using the frame length L V . For example, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 , and the error verification information may be placed on the end frame FFR 3 . 
     If the radio frame is constituted by the radio frame WFR 8 - 4 , the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL- 44 , and the error verification information is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using the frame length L V . For example, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the sub-header frame SHFR 3 , and the error verification information may be placed on the verification frame VFR 3 . 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL- 44 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL- 44  to determine a frame length that represents the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Further, the generating circuitry  13 G generates an end frame FFR 3  (or sub-header frame SHFR 3  or verification frame VFR 3  or header frame HFR 3 ) having the frame length L V  that represents the error verification information. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL- 44 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the error verification information, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G detects the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame length of one frame such as the header frame HFR 3 , and detects the error verification information based on the frame length of the other one frame. 
     Thereafter, the determination circuit  25 G and decoder  26  performs the operations described in section (9-1), and outputs the data to be transmitted. 
     (9-2-4) The case where number of data frames DFR_ 1  to DFR_n, error verification information and number of transmissions of data frames DFR_ 1  to DFR_n are placed on different frames by using frame length 
     The number of the data frames DFR_ 1  to DFR_n is placed on one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using the frame length corresponding to the number of the data frames DFR_ 1  to DFR_n in the correspondence table TBL 2 , the error verification information is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using the frame length L V  in the same manner as that in Embodiment 8, and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using the frame length corresponding to the number of transmissions of the data frames DFR_ 1  to DFR_n in the correspondence table TBL 6 . For example, the number of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 , the error verification information may be placed on the sub-header frame SHFR 3 , and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the end frame FFR 3 . 
     If the number of the data frames DFR_ 1  to DFR_n is to be placed on the header frame HFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the beginning of the data to be transmitted and the number of the data frames DFR_ 1  to DFR_n. If the number of the data frames DFR_ 1  to DFR_n is to be placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n and the number of the data frames DFR_ 1  to DFR_n. If the number of the data frames DFR_ 1  to DFR_n is placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the number of the data frames DFR_ 1  to DFR_n. If the number of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the end of the data frames DFR_ 1  to DFR_n and the number of the data frames DFR_ 1  to DFR_n. 
     If the error verification information is placed on the header frame HFR 3  by using the frame length L V , the frame length L V  represents the beginning of the data to be transmitted and the error verification information. If the error verification information is placed on the sub-header frame SHFR 3  by using the frame length L V , the frame length L V  represents a delimiter for the data frames DFR_ 1  to DFR_n and the error verification information. If the error verification information is placed on the verification frame VFR 3  by using the frame length L V , the frame length L V  represents only the error verification information. If the error verification information is placed on the end frame FFR 3  by using the frame length L V , the frame length L V  represents the end of the data to be transmitted and the error verification information. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the beginning of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n. If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the verification frame FFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the number of transmissions of the data frames DFR_ 1  to DFR_n. If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the end of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     Since the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on different frames by using frame lengths, one of the radio frames WFR 8 - 2  to WFR 8 - 4  is used in section (9-2-4). 
     If the radio frame WFR 8 - 2  is used, the number of the data frames DFR_ 1  to DFR_n is placed on one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 2 , the error verification information is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using the frame length L V , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 6 . For example, the number of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 , the error verification information may be placed on the sub-header frame SHFR 3 , and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the end frame FFR 3 . 
     If the radio frame WFR 8 - 3  is used, the number of the data frames DFR_ 1  to DFR_n is placed on one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 2 , the error verification information is placed on another one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using the frame length L V , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , verification frame VFR 3  and end frame FFR 3  by using the frame length L V . For example, the number of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 , the error verification information may be placed on the end frame FFR 3 , and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the verification frame VFR 3 . 
     If the radio frame WFR 8 - 4  is used, the number of the data frames DFR_ 1  to DFR_n is placed on one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length on the correspondence table TBL 2 , the error verification information is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using the frame length L V , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3 . For example, the number of the data frames DFR_ 1  to DFR_n may be placed on the sub-header frame SHFR 3 , the error verification information may be placed on the verification frame VFR 3 , and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 . 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1 , TBL 2  and TBL 6 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL 2  to determine a frame length that represents the number of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Further, the generating circuitry  13 G generates an end frame FFR 3  (or sub-header frame SHFR 3  or verification frame VFR 3  or header frame HFR 3 ) having the frame length L V  that represents the error verification information. Further, the generating circuitry  13 G refers to the correspondence table TBL 6  to generate a sub-header frame SHFR 3  (or verification frame VFR 3  or header frame HFR 3  or end frame FFR 3 ) having the frame length corresponding to the number of transmissions of the data frames DFR_ 1  to DFR_n. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     The receiver  802  receives one of the radio frames WFR 8 - 2  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1 , TBL 2  and TBL 6 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the error verification information, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G detects the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame lengths of different frames, each for one frame. 
     Thereafter, the determination circuit  25 G and decoder  26  performs the operations described in section (9-1), and outputs the data to be transmitted. 
     (9-3) The case where two of number of data frames DFR_ 1  to DFR_n, error verification information and number of transmissions of data frames DFR_ 1  to DFR_n are placed on one frame by using frame length 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are to be placed on one frame by using a frame length, the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL- 42 . 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on the header frame HFR 3  by using a frame length on the correspondence table TBL- 42 , this frame length represents the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL- 42 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n, the number of the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL- 42 , this frame length represents the number of the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are placed on the end frame FFR 3  by using a frame length on the correspondence table TBL- 42 , this frame length represents the end of the data frames DFR_ 1  to DFR_n, the number of the data frames DFR_ 1  to DFR_n and the error verification information. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL 42 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL- 42  to determine a frame length that represents the number of the data frames DFR_ 1  to DFR_n and the error verification information, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL- 42 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the error verification information, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G refers to the correspondence table TBL- 42  to detect the number of the data frames DFR_ 1  to DFR_n and the error verification information based on the frame length of one frame. 
     Thereafter, if the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n matches the number of the data frames DFR_ 1  to DFR_n that have been detected, the determination circuit  25 G outputs the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) to the decoder  26 . Then, the decoder  26  receives the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) and, based on the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) that have been received, outputs the data to be transmitted in accordance with the operations described above. 
     If the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n does not match the number of the data frames DFR_ 1  to DFR_n that have been detected, the determination circuit  25 G discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one frame by using a frame length, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL- 43 . 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  by using a frame length on the correspondence table TBL- 43 , this frame length represents the beginning of the data to be transmitted, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL- 43 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL- 43 , this frame length represents the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the end frame FFR 3  by using a frame length on the correspondence table TBL- 43 , this frame length represents the end of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL- 43 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL- 43  to determine a frame length that represents the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL- 43 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the error verification information, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G refers to the correspondence table TBL- 43  to detect the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame length of one frame. 
     Thereafter, the determination circuit  25 G detects the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n the number of transmissions and, if the plurality of frame lengths for the number of transmissions that has been detected match each other, outputs the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) to the decoder  26 . Then, the decoder  26  receives the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) and, based on the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) that have been received, outputs the data to be transmitted in accordance with the operations described above. 
     If the plurality of frame lengths for the number of transmissions do not match each other, the determination circuit  25 G discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one frame by using a frame length, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL- 44 . 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the header frame HFR 3  by using a frame length on the correspondence table TBL- 44 , this frame length represents the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL- 44 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL- 44 , this frame length represents the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on the end frame FFR 3  by using a frame length on the correspondence table TBL- 44 , this frame length represents the end of the data frames DFR_ 1  to DFR_n, the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL- 44 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL- 44  to determine a frame length that represents the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , and generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL- 44 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G refers to the correspondence table TBL- 44  to detect the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame length of one frame. 
     Thereafter, the determination circuit  25 G detects the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n the number of transmissions. Then, if the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n matches the number of the data frames DFR_ 1  to DFR_n that has been detected and if the plurality of frame lengths for the number of transmissions match each other, the determination circuit  25 G outputs the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) to the decoder  26 . Then, the decoder  26  receives the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) and, based on the plurality of frame lengths and error verification information (i.e. one of “00”, “01”, “10” and “11”) that have been received, outputs the data to be transmitted in accordance with the operations described above. 
     If the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n does not match the number of the data frames DFR_ 1  to DFR_n that has been detected, or if the plurality of frame lengths for the number of transmissions do not match each other, the determination circuit  25 G discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     (9-4) The case where two of number of data frames DFR_ 1  to DFR_n, error verification information and number of transmissions of data frames DFR_ 1  to DFR_n are placed on two frames by using frame lengths 
     If the number of the data frames DFR_ 1  to DFR_n and the error verification information are to be placed on different frames, each for one frame, by using frame lengths, the number of the data frames DFR_ 1  to DFR_n is placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL 2 , and the error verification information is placed on another one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using the frame length L V . For example, the number of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 , and the error verification information may be placed on the sub-header frame SHFR 3 . 
     If the number of the data frames DFR_ 1  to DFR_n is to be placed on the header frame HFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the beginning of the data to be transmitted and the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is to be placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n and the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the end of the data frames DFR_ 1  to DFR_n and the number of the data frames DFR_ 1  to DFR_n. 
     If the error verification information is placed on the header frame HFR 3  by using the frame length L V , the frame length L V  represents the beginning of the data to be transmitted and the error verification information. 
     If the error verification information is placed on the sub-header frame SHFR 3  by using the frame length L V , the frame length L V  represents a delimiter for the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the error verification information is placed on the verification frame VFR 3  by using the frame length L V , the frame length L V  represents the error verification information. 
     If the error verification information is placed on the end frame FFR 3  by using the frame length L V , the frame length L V  represents the end of the data to be transmitted and the error verification information. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL 2 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL 2  to determine a frame length that represents the number of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Further, the generating circuitry  13 G generates an end frame FFR 3  (or sub-header frame SHFR 3  or verification frame VFR 3  or header frame HFR 3 ) having the frame length L V . Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL 2 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the error verification information, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G refers to the correspondence table TBL 2  to detect the number of the data frames DFR_ 1  to DFR_n based on the frame length of one frame and detect the error verification information based on the frame length L V . 
     Thereafter, if the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n matches the number of the data frames DFR_ 1  to DFR_n that have been detected, and if the determination circuit  25 G determines based on the frame length L V  that no error has been detected in the data frames DFR_ 1  to DFR_n, it outputs the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n to the decoder  26 . Then, the decoder  26  refers to the correspondence table TBL 1  to convert the plurality of frame lengths to bit sequences, and outputs the data to be transmitted. 
     If the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n does not match the number of the data frames DFR_ 1  to DFR_n that have been detected, or if the determination circuit  25 G detects an error in the data frames DFR_ 1  to DFR_n, it discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     If the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on different frames, each for one frame, by using frame lengths, the error verification information is placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using the frame length L V , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL 6 . For example, the error verification information may be placed on the sub-header frame SHFR 3  and the number of transmissions of the data frames DFR_ 1  to DFR_n may be placed on the header frame HFR 3 . 
     If the error verification information is placed on the header frame HFR 3  by using the frame length L V , the frame length L V  represents the beginning of the data to be transmitted and the error verification information. 
     If the error verification information is placed on the sub-header frame SHFR 3  by using the frame length L V , the frame length L V  represents a delimiter for the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the error verification information is placed on the verification frame VFR 3  by using the frame length L V , the frame length L V  represents the error verification information. 
     If the error verification information is placed on the end frame FFR 3  by using the frame length L V , the frame length L V  represents the end of the data to be transmitted and the error verification information. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the beginning of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the end of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL 6 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length L V . Further, the generating circuitry  13 G refers to the correspondence table TBL 6  to determine a frame length that represents the number of transmissions of the data frames DFR_ 1  to DFR_n, and generates an end frame FFR 3  (or sub-header frame SHFR 3  or verification frame VFR 3  or header frame HFR 3 ) having the frame length that has been determined. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B, and generates a verification frame VFR 3  having the frame length L V  in the same manner as that in the generating circuitry  13 E. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL 6 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the error verification information, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G refers to the correspondence table TBL 6  to detect the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame length of one frame, and detects the error verification information based on the frame length L V . 
     Thereafter, the determination circuit  25 G detects the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n the number of transmissions. Then, if the plurality of frame lengths for the number of transmissions match each other, and if it determines based on the frame length L V  that no error has been detected in the data frames DFR_ 1  to DFR_n, it outputs the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n to the decoder  26 . Then, the decoder  26  refers to the correspondence table TBL 1  to convert the plurality of frame lengths to bit sequences and outputs the data to be transmitted. 
     If the plurality of frame lengths for the number of transmissions do not match each other, or if the determination circuit  25 G detects an error in the data frames DFR_ 1  to DFR_n, it discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n are placed on different frames, each for one frame, by using frame lengths, the number of the data frames DFR_ 1  to DFR_n is placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL 2 , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on another one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL 6 . For example, the number of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3 , and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3 . 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the beginning of the data to be transmitted and the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n and the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the end of the data frames DFR_ 1  to DFR_n and the number of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the beginning of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the end of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1 , TBL 2  and TBL 6 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL 2  to determine a frame length that represents the number of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Further, the generating circuitry  13 G refers to the correspondence table TBL 6  to determine a frame length that represents the number of transmissions of the data frames DFR_ 1  to DFR_n, and generates an end frame FFR 3  (or sub-header frame SHFR 3  or verification frame VFR 3  or header frame HFR 3 ) having the frame length that has been determined. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , and generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1 , TBL 2  and TBL 6 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G refers to the correspondence table TBL 2  to detect the number of the data frames DFR_ 1  to DFR_n based on the frame length of one frame, and refers to the correspondence table TBL 6  to detect the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame length of one frame. 
     Thereafter, the determination circuit  25 G detects the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n the number of transmissions. Then, if the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n matches the number of data frames that has been detected and if the plurality of frame lengths for the number of transmissions match each other, the determination circuit  25 G outputs the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n to the decoder  26 . Then, the decoder  26  refers to the correspondence table TBL 1  to convert the plurality of frame lengths to bit sequences, and outputs the data to be transmitted. 
     If the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n does not match the number of the data frames that has been detected, or if the plurality of frame lengths for the number of transmissions do not match each other, the determination circuit  25 G discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     (9-5) The case where one of number of data frames DFR_ 1  to DFR_n, error verification information and number of transmissions of data frames DFR_ 1  to DFR_n is placed on one frame by using frame length 
     If the number of the data frames DFR_ 1  to DFR_n is placed on one frame by using a frame length, the number of the data frames DFR_ 1  to DFR_n is placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL 2 . 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the beginning of the data to be transmitted and the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n and the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the number of the data frames DFR_ 1  to DFR_n. 
     If the number of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length on the correspondence table TBL 2 , this frame length represents the end of the data frames DFR_ 1  to DFR_n and the number of the data frames DFR_ 1  to DFR_n. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL 2 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL 2  to determine a frame length that represents the number of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , and generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL 2 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G refers to the correspondence table TBL 2  to detect the number of the data frames DFR_ 1  to DFR_n based on the frame length of one frame. 
     Thereafter, if the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n matches the number of data frames that has been detected, the determination circuit  25 G outputs the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n to the decoder  26 . Then, the decoder  26  refers to the correspondence table TBL 1  to convert the plurality of frame lengths to bit sequences, and outputs the data to be transmitted. 
     If the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n does not match the number of data frames that has been detected, the determination circuit  25 G discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     If the error verification information is placed on one frame by using the frame length L V , the error verification information is placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using the frame length L V . 
     If the error verification information is placed on the header frame HFR 3  by using the frame length L V , the frame length L V  represents the beginning of the data to be transmitted and the error verification information. 
     If the error verification information is placed on the sub-header frame SHFR 3  by using the frame length L V , the frame length L V  represents a delimiter for the data frames DFR_ 1  to DFR_n and the error verification information. 
     If the error verification information is placed on the verification frame VFR 3  by using the frame length L V , the frame length L V  represents the error verification information. 
     If the error verification information is placed on the end frame FFR 3  by using the frame length L V , the frame length L V  represents the end of the data frames DFR_ 1  to DFR_n and the error verification information. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence table TBL 1 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length L V  in accordance with the method in Embodiment 8. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , and generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence table TBL 1 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the error verification information, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G detects the error verification information based on the frame length of one frame. 
     Thereafter, if no error has been detected in the frames DFR_ 1  to DFR_n, the determination circuit  25 G outputs the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n to the decoder  26 . Then, the decoder  26  refers to the correspondence table TBL 1  to convert the plurality of frame lengths to bit sequences and outputs the data to be transmitted. 
     If an error has been detected in the data frames DFR_ 1  to DFR_n, the determination circuit  25 G discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on one frame by using a frame length, the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on one of the header frame HFR 3 , the sub-header frame SHFR 3 , the verification frame VFR 3  and the end frame FFR 3  by using a frame length on the correspondence table TBL 6 . 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the beginning of the data to be transmitted and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents a delimiter for the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the verification frame VFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     If the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length on the correspondence table TBL 6 , this frame length represents the end of the data frames DFR_ 1  to DFR_n and the number of transmissions of the data frames DFR_ 1  to DFR_n. 
     The generating circuitry  13 G of the transmitter  801  holds the correspondence tables TBL 1  and TBL 6 . Then, the generating circuitry  13 G refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values of the data to be transmitted. Further, the generating circuitry  13 G refers to the correspondence table TBL 6  to determine a frame length that represents the number of transmissions of the data frames DFR_ 1  to DFR_n, and generates a header frame HFR 3  (or end frame FFR 3  or sub-header frame SHFR 3  or verification frame VFR 3 ) having the frame length that has been determined. Otherwise, the generating circuitry  13 G generates an end frame FFR 3  having the frame length of 680 μs or a header frame HFR 3  having the frame length of 1190 μs in the same manner as that in the generating circuitry  13 , and generates a sub-header frame SHFR 3  having the frame length of 1280 μs in the same manner as that in the generating circuitry  13 B. 
     The receiver  802  receives one of the radio frames WFR 8 - 1  to WFR 8 - 4 . The determination circuit  25 G of the receiver  802  holds the correspondence tables TBL 1  and TBL 6 . Then, the determination circuit  25 G receives a plurality of frame lengths from the frame length detection circuit  24  and, based on the plurality of frame lengths that have been received, detects the beginning of the data to be transmitted, the number of transmissions of the data frames DFR_ 1  to DFR_n, and the end of the data to be transmitted in the manner described above. In this case, the determination circuit  25 G refers to the correspondence table TBL 6  to detect the number of transmissions of the data frames DFR_ 1  to DFR_n based on the frame length of one frame. 
     Thereafter, the determination circuit  25 G detects the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n the number of transmissions. Then, if the plurality of frame lengths for the number of transmissions that has been detected match each other, the determination circuit  25 G outputs the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n to the decoder  26 . Then, the decoder  26  refers to the correspondence table TBL 1  to convert the plurality of frame lengths to bit sequences, outputs the data to be transmitted. 
     If the plurality of frame lengths for the number of transmissions do not match each other, the determination circuit  25 G discards the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n. 
     As described above, in Embodiment 9, at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on at least one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using a frame length. 
       FIG. 72  is a flow chart illustrating the operation of the wireless communication system  800  of  FIG. 53 . The flow chart of  FIG. 72  is the same as the flow chart of  FIG. 52  except that steps S 1  and S 2  of the flow chart of  FIG. 52  are replaced by steps S 1 D and S 2 D, respectively, step S 38  is deleted, step S 9  is replaced by step S 9 D, and steps S 12 , S 13 , S 45 , S 39 A, S 40  to S 42  and S 43 A are replaced by steps S 60  to S 62 . 
     Referring to  FIG. 72 , when the operation is started, the generating circuitry  13 G of the transmitter  801  generates at least one frame having a frame length that represents at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and the data frames DFR_ 1  to DFR_n in the manner described above (step S 1 D). 
     In this case, at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on at least one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3  by using at least one frame length. 
     Then, the transmitter  801  sets K=total number of the frames generated at step S 1 D (step S 2 D). 
     Thereafter, steps S 35 , S 3  to S 8 , S 36  and S 37  described above are sequentially executed. 
     Then, the receiver  802  sequentially receives at least one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3 , and the data frames DFR_ 1  to DFR_n in the order in which they were transmitted (step S 9 D). 
     Thereafter, steps S 10  and S 11  described above are sequentially executed. 
     After step S 11 , the determination circuit  25 G of the receiver  802  determines whether it has detected the beginning of the data to be transmitted by determining whether the first frame length is 1190 μs or matches a frame length contained in one of the correspondence tables TBL 2 , TBL 6  and TBL- 41  to TBL- 44  (step S 50 ). 
     In this case, if none of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  by using a frame length, the determination circuit  25  determines whether it has detected the beginning of the data to be transmitted by determining whether the first frame length is equal to 1190 μs. On the other hand, if at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the header frame HFR 3  by using a frame length, the determination circuit  25 G determines whether it has detected the beginning of the data to be transmitted by determining whether the first frame length matches a frame length contained in one of the correspondence tables TBL 2 , TBL 6  and TBL- 41  to TBL- 44 . 
     If it is determined at step S 50  that the beginning of the data to be transmitted has not detected, the operation ends. 
     On the other hand, if it is determined at step S 50  that the beginning of the data to be transmitted has been detected, the determination circuit  25 G, or the determination circuit  25 G and decoder  26  in the receiver  802 , perform(s) a verification procedure (step S 51 ). 
     This verification procedure includes the following: 
     (I) verifying that the number of the plurality of frame lengths corresponding to the data frames DFR_ 1  to DFR_n matches the number of the data frames DFR_ 1  to DFR_n that has been detected; 
     (II) based on the error verification information, verifying that no error has been detected in the data frames DFR_ 1  to DFR_n; and 
     (III) verifying that the plurality of frame lengths for the number of transmissions corresponding to the data frames DFR_ 1  to DFR_n match each other. 
     If the verification of (II) above is performed based on the frame length L V , the determination circuit  25 G performs the verification of (II) above; if the verification of (II) is performed based on the 2-bit value b 4  and b 5 , the decoder  26  performs the verification of (II) above. 
     The determination circuit  25 G, or the determination circuit  25 G and decoder  26  detect(s) at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n in the manner described above, and, depending on the at least one information that has been detected, performs at least one of the verification of (I) to (III) above to perform the verification procedure. 
     After step S 51 , the determination circuit  25 G, or the determination circuit  25 G and decoder  26 , determine(s) whether it/they has/have succeeded in the verification procedure (step S 52 ). 
     If all of the at least one of verification of (I) to (III) above performed depending on the at least one information type that has been detected are satisfied, the determination circuit  25 G or the determination circuit  25 G and decoder  26  determine(s) that it/they has/have succeeded in the verification procedure. On the other hand, if even some of the at least one of the verifications of (I) to (III) above performed depending on the at least one information that has been detected is not satisfied, the determination circuit  25 G or the determination circuit  25 G and decoder  26  determine(s) that it/they has/have not succeeded in the verification procedure. 
     The end of the data to be transmitted is detected based on the frame length of the end frame FFR 3  during the verification procedure of step S 51 . Then, if none of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length, the determination circuit  25 G determines whether the end of the data to be transmitted has been detected by determining whether the last frame length is equal to 680 μs. On the other hand, if at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the end frame FFR 3  by using a frame length, the determination circuit  25 G determines whether the end of the data to be transmitted has been detected by determining whether the last frame length matches a frame length contained in one of the correspondence tables TBL 2 , TBL 6  and TBL- 41  to TBL- 44 . 
     Further, a delimiter for the data frames DFR_ 1  to DFR_n is detected based on the frame length of the sub-header frame SHFR 3  during the verification procedure of step S 51 . Then, if none of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3  by using a frame length, the determination circuit  25 G determines whether a delimiter for the data frames DFR_ 1  to DFR_n has been detected by determining whether a frame length different from the frame lengths of the data frames DFR_ 1  to DFR_n is equal to 1280 μs. On the other hand, if at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is placed on the sub-header frame SHFR 3  by using a frame length, the determination circuit  25 G determines whether a delimiter for the data frames DFR_ 1  to DFR_n has been detected by determining whether a frame length different from the frame lengths of the data frames DFR_ 1  to DFR_n matches a frame length contained in one of the correspondence tables TBL 2 , TBL 6  and TBL- 41  to TBL- 44 . 
     If it is determined at step S 52  that the verification procedure is not succeeded, the operation ends. 
     On the other hand, if it is determined at step S 52  that the verification procedure is succeeded, the receiver  802  determines that it has succeeded in receiving the data (step S 44 A), and the operation ends. 
     As described above, in Embodiment 9, the transmitter  801  transmits at least one frame (i.e. at least one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3 ) having at least one frame length that represents at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n, and the receiver  802  receives at least one frame (i.e. at least one of the header frame HFR 3 , sub-header frame SHFR 3 , verification frame VFR 3  and end frame FFR 3 ) and performs at least one of the verification of (I) to (III) above. This significantly improves the freedom with which the at least one of the number of the data frames DFR_ 1  to DFR_n, the error verification information and the number of transmissions of the data frames DFR_ 1  to DFR_n is transmitted and received, thereby allowing the data frames DFR_ 1  to DFR_n to be correctly received. 
     In Embodiment 9, the operations of the transmitter  801  and receiver  802  may be carried out by a program. In this case, each of the transmitter  801  and receiver  802  includes a CPU, a ROM and a RAM. In the transmitter  801 , the ROM stores a program O including steps S 1 D, S 2 D, S 35 , S 3  to S 8  and S 37  shown in  FIG. 72 , and the CPU reads the program O from the ROM and executes it. Thus, the operation of the transmitter  801  is performed. In the receiver  802 , the ROM stores a program P including steps S 9 D, S 10 , S 11 , S 60  to S 62  and S 44 A shown in  FIG. 72 , and the CPU reads the program P from the ROM and executes it. Thus, the operation of the receiver  802  is performed. Further, each of the ROMs of the transmitter  801  and receiver  802  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Furthermore, at least one of the header frame HFR 3 , sub-header frame SHFR 3  (also referred to as “delimiter frame”), verification frame VFR 3  and end frame FFR 3  constitutes the “auxiliary frame”. 
     Otherwise, the description of Embodiment 9 is the same as those of Embodiments 1 to 8. 
     Embodiment 10 
       FIG. 73  is a schematic diagram of a wireless communication system according to Embodiment 10. Referring to  FIG. 73 , the wireless communication system  900  according to Embodiment 10 includes a transmitter  901  and a receiver  902 . 
     The transmitter  901  and receiver  902  are positioned in a wireless communication space. The transmitter  901  generates a start frame STA in the manner described below. The transmitter  901  generates header frames HFR_ 1  to HFR_i in the same manner as that in the transmitter  301 , generates data frames DFR_ 1  to DFR_n in the same manner as that in the transmitter  1 , and generates check frames CHK_ 1  to CHK_n in the manner described below. 
     Then, the transmitter  801  transmits the start frame STA, header frames HFR_ 1  to HFR_i, data frame DFR_ 1 , check frame CHK_ 1 , data frame DFR_ 2 , check frame CHK_2, . . . , data frame DFR_n, and check frame CHK_n one after another in accordance with the CSMA/CA scheme. 
     The start frame STA is a frame for informing the receiver  902  of start of transmission of frames. Each of the check frames CHK_ 1  to CHK_n is a frame for checking the data frames DFR_ 1  to DFR_n. 
     The receiver  902  sequentially receives the start frame STA, header frames HFR_ 1  to HFR_i, data frame DFR_ 1 , check frame CHK_ 1 , data frame DFR_ 2 , check frame CHK_2, . . . , data frame DFR_n and check frame CHK_n. 
     Then, based on the frame length of the start frame STA, the receiver  802  senses start of transmission of frames, and, based on the bit sequence of the header frames HFR_ 1  to HFR_i, detects the beginning of the data to be transmitted and detects the header information. The receiver  902  checks whether the data frames DFR_ 1  to DFR_n are correct based on the frame lengths of the check frames CHK_ 1  to CHK_n. Then, if the data frames DFR_ 1  to DFR_n are correct, the receiver  902  converts the frame lengths of the data frames DFR_ 1  to DFR_n to bit sequences, thereby providing the data to be transmitted. 
       FIG. 74  is a schematic diagram of the transmitter of  FIG. 73 . Referring to  FIG. 74 , the transmitter  901  is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  is replaced by a generating circuitry  13 H. 
     The generating circuitry  13 H generates the start frame STA in the manner described below, generates the header frames HFR_ 1  to HFR_i in the same manner as that in the generating circuitry  13 C, generates the data frames DFR_ 1  to DFR_n in the same manner as that in the generating circuitry  13 , and generates the check frames CHK_ 1  to CHK_n in the manner described below. 
     Then, the generating circuitry  13 H outputs the start frame STA, header frames HFR_ 1  to HFR_i, data frame DFR_ 1 , check frame CHK_ 1 , data frame DFR_ 2 , check frame CHK_2, . . . , data frame DFR_n and check frame CHK_n that have been generated to the transmitting circuitry  12 . 
     The transmitting circuitry  12  transmits the start frame STA, header frames HFR_ 1  to HFR_i, data frame DFR_ 1 , check frame CHK_ 1 , data frame DFR_ 2 , check frame CHK_2, . . . , data frame DFR_n and check frame CHK_n one after another in accordance with the CSMA/CA scheme. 
       FIG. 75  is a schematic diagram of the receiver of  FIG. 73 . Referring to  FIG. 75 , the receiver  902  is the same as the receiver  2  except that the determination circuit  25  of the receive  2  is replaced by a determination circuit  25 H and the decoder  26  is replaced by a decoder  26 A. 
     The determination circuit  25 H receives a plurality of frame lengths from the frame length detection circuit  24 . Then, if the firstly received frame length matches the frame length of the start frame STA, the determination circuit  25 H senses start of transmission of frames. 
     If the determination circuit  25 H has sensed start of transmission of frames, it outputs the plurality of frame lengths including the second frame length and frame lengths following the second frame length to the decoder  26 A. 
     If the first frame length does not match the frame length of the start frame STA, the determination circuit  25 H discards the plurality of frame lengths that have been received in the second and subsequent. 
     When the decoder  26 A has received the plurality of frame lengths from the determination circuit  25 H, it converts the plurality of frame lengths that have been received to the bit sequences of the header frames HFR_ 1  to HFR_i, the bit sequences of the data frames DFR_ 1  to DFR_n and the bit sequences of the check frames CHK_ 1  to CHK_n in the manner described below. 
     Then, based on the bit sequences of the header frames HFR_ 1  to HFR_i, the bit sequences of the data frames DFR_ 1  to DFR_n and the bit sequences of the check frames CHK_ 1  to CHK_n, the decoder  26 A determines whether the data frames DFR_ 1  to DFR_n are correct in the manner described below. 
     If the decoder  26 A determines that the data frames DFR_ 1  to DFR_n are correct, it outputs a bit sequence obtained by arranging the bit sequences of the data frames DFR_ 1  to DFR_n in one series as the data to be transmitted. 
     On the other hand, if the decoder  26 A determines that the data frames DFR_ 1  to DFR_n are not correct, it discards the bit sequences of the data frames DFR_ 1  to DFR_n. 
       FIG. 76  schematically illustrates a radio frame according to Embodiment 10. Referring to  FIG. 76 , the radio frame WFR 9  of Embodiment 10 includes a start frame STA, header frames HFR 1  to HFR_i, data frames DFR_ 1  to DFR_n and check frames CHK_ 1  to CHK_n. 
     The header frames HFR_ 1  to HFR_i are positioned to follow the start frame STA, the data frame DFR_ 1  is positioned to follow the header frame HFR_i, the check frame CHK_ 1  is positioned to follow the data frame DFR_ 1 , the data frame DFR_ 2  is positioned to follow the check frame CHK_ 1 , the check frame CHK_ 2  is positioned to follow the data frame DFR_ 2 , and so forth, and the data frame DFR_n is positioned to follow the check frame CHK_n−1, and the check frame CHK_n is positioned to follow the data frame DFR_n. 
     The start frame STA has a frame length different from those of the data frames DFR_ 1  to DFR_n. 
     The check frame CHK_ 1  has the frame length corresponding to the bit sequence of the four lowest-order bits of the bit sequence that represents the sum of the i bit sequences of the header frames HFR_ 1  to HFR_i and the bit sequence of the data frame DFR_ 1 . 
     The check frame CHK_ 2  has the frame length corresponding to the bit sequence of the four lowest-order bits of the bit sequence that represents the sum of the bit sequence of the check frame CHK_ 1  and the bit sequence of the data frame DFR_ 2 . 
     The check frame CHK_ 3  has the frame length corresponding to the bit sequence of the four lowest-order bits of the bit sequence that represents the sum of the bit sequence of the check frame CHK_ 2  and the bit sequence of the data frame DFR_ 3 . 
     In the same manner, the check frame CHK_n has the frame length corresponding to the bit sequence of the four lowest-order bits of the bit sequence that represents the sum of the bit sequence of the check frame CHK_n−1 and the bit sequence of the data frame DFR_n. 
       FIG. 77  illustrates a specific example of a radio frame WFR 9  according to Embodiment 10. Referring to  FIG. 77 , the radio frame WFR 9 - 1  includes a start frame STA, header frames HFR_ 1  to HFR_ 3 , data frames DFR_ 1  to DFR_ 3 , and check frames CHK_ 1  to CHK_ 3 . 
     The start frame STA has the frame length of 300 μs, the header frames HFR_ 1  to HFR_ 3  have the frame lengths of 770 μs, 980 μs and 710 μs, respectively, the data frames DFR_ 1  to DFR_ 3  have the frame lengths of 800 μs, 1010 μs and 1160 μs, respectively. 
     The frame length of 770 μs of the header frame HFR_ 1  corresponding to the bit sequence of “0010”, the frame length of 980 μs of the header frame HFR_ 2  corresponding to the bit sequence of “1001”, the frame length of 710 μs of the header frame HFR_ 3  corresponding to the bit sequence of “0000”, the frame length of 800 μs of the data frame DFR_ 1  corresponding to the bit sequence of “0011”, the frame length of 1010 μs of the data frame DFR_ 2  corresponding to the bit sequence of “1010”, and the frame length of 1160 μs of the data frame DFR_ 3  corresponding to the bit sequence of “1111” (see correspondence table TBL 1 ). 
     As a result, the check frame CHK_ 1  has the frame length of 1130 μs, which corresponds to “1110”, i.e. the sum of “0010”, “1001”, “0000” and “0011”. 
     The check frame CHK_ 2  has the frame length of 950 μs, which corresponds to the bit sequence of “1000”, i.e. the four lowest-order bits of “11000”, which is the sum of the bit sequence “1110” of the check frame CHK_ 1  and the bit sequence “1010” of the data frame DFR_ 2 . 
     The check frame CHK_ 3  has the frame length of 920 μs, which corresponds to the bit sequence “0111”, i.e. the four lowest-order bits of “10111”, which is the sum of the bit sequence “1000” of the check frame CHK_ 2  and the bit sequence “1111” of the data frame DFR_ 3 . 
     The generating circuitry  13 H of the transmitter  901  holds the correspondence table TBL 1 . Then, the generating circuitry  13 H generates a start frame STA having the frame length of 300 μs. Then, the generating circuitry  13 H refers to the correspondence table TBL 1  and, based on the bit sequence “0010” of the header frame HFR_ 1 , the bit sequence “1001” of the header frame HFR_ 2  and the bit sequence “0000” of the header frame HFR_ 3 , generates the header frame HFR_ 1  having the frame length of 770 μs, the header frame HFR_ 2  having the frame length of 980 μs and the header frame HFR_ 3  having the frame length of 710 μs, respectively. Thereafter, the generating circuitry  13 H refers to the correspondence table TBL 1  and, based on the bit sequence “0011” of the data frame DFR_ 1 , the bit sequence “1010” of the data frame DFR_ 2  and the bit sequence “1111” of the data frame DFR_ 3 , generates the data frame DFR_ 1  having the frame length of 800 μs, the data frame DFR_ 2  having the frame length of 1010 μs, and the data frame DFR_ 3  having the frame length of 1160 μs, respectively. 
     Then, the generating circuitry  13 H generates the check frame CHK_ 1  having the frame length of 1130 μs, the check frame CHK_ 2  having the frame length of 950 μs and the check frame CHK_ 3  having the frame length of 920 μs in the manner described above. 
     Then, the generating circuitry  13 H sequentially outputs the start frame STA, header frames HFR_ 1  to HFR_ 3 , data frame DFR_ 1 , check frame CHK_ 1 , data frame DFR_ 2 , check frame CHK_ 2 , data frame DFR_ 3  and check frame CHK_ 3  to the transmitting circuitry  12 , and the transmitting circuitry  12  transmits the start frame STA, header frames HFR_ 1  to HFR_ 3 , data frame DFR_ 1 , check frame CHK_ 1 , data frame DFR_ 2 , check frame CHK_ 2 , data frame DFR_ 3  and check frame CHK_ 3  one after another in accordance with the CSMA/CA scheme. 
     The receiver  902  sequentially receives the start frame STA, header frames HFR_ 1  to HFR_ 3 , data frame DFR_ 1 , check frame CHK_ 1 , data frame DFR_ 2 , check frame CHK_ 2 , data frame DFR_ 3  and check frame CHK_ 3 . 
     Then, the frame length detection circuit  24  of the receiver  902  detects the frame lengths of 300 μs, 770 μs, 980 μs, 710 μs, 800 μs, 1130 μs, 1010 μs, 950 μs, 1160 μs and 920 μs and sequentially outputs the frame lengths of 300 μs, 770 μs, 980 μs, 710 μs, 800 μs, 1130 μs, 1010 μs, 950 μs, 1160 μs and 920 μs that have been detected to the determination circuit  25 H in the manner described above. 
     When the determination circuit  25 H has received the frame length of 300 μs, it senses that it has received the start frame STA since the received frame length is 300 μs, and senses start of transmission of frames. 
     Then, the determination circuit  25 H outputs the frame lengths of 770 μs, 980 μs, 710p, 800 μs, 1130 μs, 1010 μs, 950 μs, 1160 μs, and 920 μs following the frame length of 300 μs to the decoder  26 A. 
     The decoder  26 A holds the correspondence table TBL 1 . Then, the decoder  26 A refers to the correspondence table TBL 1  to convert the frame lengths of 770 μs, 980 μs, 710p, 800 μs, 1130 μs, 1010 μs, 950 μs, 1160 μs, and 920 μs to the bit sequences “0010”, “1001”, “0000”, “0011”, “1110”, “1010”, “1000”, “1111” and “0111”, respectively. 
     Then, the decoder  26  A calculates the sum “1110” of “0010”, “1001”, “0000” and “0011”, and detects that the calculated sum “1110” matches the bit sequence “1110” of the check frame CHK_ 1  and senses that the data frame DFR_ 1  is correct. 
     Thereafter, the decoder  26 A detects that bit sequence “1000” of four lowest-order bits of the sum “1100” of the bit sequence “1110” of the check frame CHK_ 1  and the bit sequence “1010” of the data frame DFR_ 2  matches the bit sequence “1000” of the check frame CHK_ 2  to sense that the data frame DFR_ 2  is correct. 
     Further, the decoder  26 A detects that the bit sequence “0111” of four lowest-order bits of the sum “1011” of the bit sequence “1000” of the check frame CHK_ 2  and the bit sequence “1111” of the data frame DFR_ 3  matches the bit sequence “0111” of the check frame CHK_ 3  to sense that the data frame DFR_ 3  is correct. 
     Then, the decoder  26 A arranges the bit sequences “0011”, “1010” and “1111” of the data frames DFR_ 1  to DFR_ 3  in one series to outputs “001110101111” as the data to be transmitted. 
     In the above description, the number of the check frames CHK_ 1  to CHK_n is equal to the number of the data frames DFR_ 1  to DFR_n; however, Embodiment 10 is not limited to such an implementation, and the number of the check frames CHK may be unequal to the number of the data frames DFR_ 1  to DFR_n and a check frame CHK may be inserted between the data frames DFR_ 1  to DFR_n at a desired interval along the data frames DFR_ 1  to DFR_n. 
     In the above description, the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and check frames CHK are represented by 4-bit sequences; however, Embodiment 10 is not limited to such an implementation, and the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and check frame CHK may be represented by bit sequences different from 4-bit sequences. 
     Further, in the above description, the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and check frames CHK are transmitted only once; however, Embodiment 10 is not limited to such an implementation, and it is only required that the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and check frames CHK be transmitted one or more times. In this case, when the receiver  902  has determined that the data frames DFR_ 1  to DFR_n are correct using check frames CHK the number of transmissions, it arranges the bit sequences of the data frames DFR_ 1  to DFR_n in one series to output the arranged bit sequence as the data to be transmitted. 
       FIG. 78  is a flow chart illustrating the operation of the wireless communication system  900  of  FIG. 73 . The flow chart of  FIG. 78  is the same as the flow chart of  FIG. 52  except that steps S 1 , S 2  and S 9  of the flow chart of  FIG. 52  are replaced by steps S 1 E, S 2 E and S 9 E, respectively, steps S 12 , S 13 , S 45 , S 39 A and S 40  are replaced by steps S 60  to S 65 , and step S 43  A is deleted. 
     Referring to  FIG. 78 , when the operation is started, the transmitter  901  generates the start frame STA, header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and check frames CHK_ 1  to CHK_P (P is a positive integer) in the manner described above (step S 1 E). 
     Then, the transmitter  901  sets K-total number of the frames generated at step S 1 E (step S 2 E). 
     Thereafter, steps S 35 , S 3  to S 8  and S 36  to S 38  described above are sequentially executed. 
     Then, the receiver  902  sequentially receives the start frame STA, header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and check frames CHK_ 1  to CHK_P (step S 9 E). 
     Then, steps S 10  and S 11  described above are sequentially executed. Then, after step S 11 , the determination circuit  25 H of the receiver  902  determines whether it has sensed start of transmission of frames by determining whether the first frame length is 300 μs (step S 60 ). In this case, if the first frame length is 300 μs, the determination circuit  25 H determines that it has sensed start of transmission of frames, and, if the first frame length is not 300 μs, determines that it has not sensed start of transmission of frames. 
     If it is determined at step S 60  that it has not sensed start of transmission of frames, the operation ends. 
     On the other hand, if it is determined at step S 60  that it has sensed start of transmission of frames, the determination circuit  25 H outputs the second and subsequent frame lengths to the decoder  26 A, and the decoder  26 A refers to the correspondence table TBL 1  to convert the second and subsequent frame lengths to bit sequences. That is, the decoder  26 A converts the frame lengths of the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and check frames CHK_ 1  to CHK_P to bit sequences (step S 61 ). 
     Then, the decoder  26 A sets p=1 (p is an integer that meets 1≤p≤P) (step S 62 ), and uses the bit sequence of the first check frame CHK_ 1  to determine, in the manner described above, whether the data frames are correct (step S 63 ). 
     If it is determined at step S 63  that the data frames are not correct, the operation ends. 
     If it is determined at step S 63  that the data frames are correct, the decoder  26 A determines whether p=P (step S 64 ). 
     If it is determined at step S 64  that p=P is not true, the decoder  26 A sets p=p+1 (step S 65 ). Thereafter, the operation returns to step S 63 . Then, steps S 63  to S 65  described above are repeatedly executed until it is determined at step S 64  that p=P. 
     If it is determined at step S 64  that p=P, steps S 9 E, S 10 , S 11 , S 60  to S 65 , S 41  and S 42  described above are repeatedly executed until it is determined at step S 41  that r=T. 
     If it is determined at step S 41  that r=T the receiver  902  has succeeded in receiving the data (step S 44 A), and the operation ends. 
     Thus, in Embodiment 10, it is determined for each check frame whether the data frames are correct (see step S 63 ). Then, if it is determined the number of transmissions that all of the data frames DFR_ 1  to DFR_n are correct, the receiver succeeds in receiving the data. 
     Therefore, the data frames DFR_ 1  to DFR_n could be received correctly. 
     Further, if the number P of the check frames CHK_ 1  to CHK_P is equal to the number n of the data frames DFR_ 1  to DFR_n, it is checked for each data frame whether the data frame is correct, thereby allowing the data frames DFR_ 1  to DFR_n to be received more correctly. 
     In Embodiment 10, the operations of the transmitter  901  and receiver  902  may be carried out by a program. In this case, each of the transmitter  901  and receiver  902  includes a CPU, a ROM and a RAM. In the transmitter  901 , the ROM stores a program Q including steps S 1 E, S 2 E, S 35 , S 3  to S 8 , S 36  and S 37  shown in  FIG. 78 , and the CPU reads the program Q from the ROM and executes it. Thus, the operation of the transmitter  901  is performed. In the receiver  902 , the ROM stores a program R including steps S 38 , S 9 E, S 10 , S 11 , S 60  to S 65 , S 41 , S 42  and S 44 A shown in  FIG. 78 , and the CPU reads the program R from the ROM and executes it. Thus, the operation of the receiver  902  is performed. Further, each of the ROMs of the transmitter  901  and receiver  902  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Further, in the above description, the start frame STA has the frame length of 300 μs; however, Embodiment 10 is not limited to such an implementation, and the start frame STA may have any frame length other than 300 μs if its frame length is different from the frame lengths of the data frames DFR_ 1  to DFR_n. 
     Otherwise, the description of Embodiment 10 is the same as those of Embodiment 1 to 8. 
     Embodiment 11 
       FIG. 79  is a schematic diagram of a wireless communication system according to Embodiment 11. Referring to  FIG. 79 , the wireless communication system  1000  according to Embodiment 11 includes a transmitter  1001  and receiver  1002 . 
     The transmitter  1001  and receiver  1002  are positioned in a wireless communication space. The transmitter  1001  generates header frames HFR_ 1  to HFR_i having the frame lengths corresponding to the bit sequence of header information in the manner described below. Further, the transmitter  1001  generates data frames DFR_ 1  to DFR_n in the manner described below. Furthermore, the transmitter  1001  generates delimiter frames KFR_ 1  to KFR_m having the frame lengths corresponding to the bit sequences that indicate delimiters for the data frames DFR_ 1  to DFR_n in the manner described below. Moreover, the transmitter  1001  generates a check frame CHK in the manner described above. 
     Then, the transmitter  1001  transmits the header frames HFR_ 1  to HFR_i, then consecutively transmits the delimiter frames KFR_ 1   q  times (q is a positive integer), then consecutively transmits the data frames DFR_ 1   q  times and consecutively transmits the delimiter frame KFR_ 2   q  times, then consecutively transmits the data frame DFR_ 2   q  times, and so forth, and consecutively transmits the delimiter frame KFR_m−1 q times, then consecutively transmits the data frames DFR_n−1 q times, then consecutively transmits the delimiter frame KFR_m q times, then consecutively transmits the data frame DFR_n q times, and then consecutively transmits the check frame CHK q times. 
     The receiver  1002  sequentially receives the header frames HFR_ 1  to HFR_i, q delimiter frames KFR_ 1 , q data frames DFR_ 1 , q delimiter frames KFR_ 2 , q data frames DFR_2, . . . q delimiter frames KFR_m, q data frames DFR_n and check frames CHK. 
     Then, when the receiver  1002  has detected the frame lengths of the header frames HFR_ 1  to HFR_i, it senses the beginning of the data to be transmitted. 
     Thereafter, when the receiver  1002  has received the q delimiter frames KFR_ 1 , it enters into a state of waiting for a data frame DFR_ 1 ; when it has received the q data frames DFR_ 1 , it enters into a state of waiting for a delimiter frame KFR_ 2 ; when it has received the q delimiter frames KFR_ 2 , it enters into a state of waiting for a data frame DFR_ 2 ; and so forth, and when it has received the q delimiter frames KFR_m, it enters into a state of waiting for a data frame DFR_n. Then, after the receiver  1002  has received the q data frames DFR_n, it receives the check frames CHK, and uses the received check frames CHK to determine whether the data frames DFR_ 1  to DFR_n are correct. When the receiver  1002  determines that the data frames DFR_ 1  to DFR_n are correct, it determines that the receiver has succeeded in receiving the data to be transmitted. 
       FIG. 80  is a schematic diagram of the transmitter of  FIG. 79 . Referring to  FIG. 80 , the transmitter  1001  is the same as the transmitter  1  except that the generating circuitry  13  of the transmitter  1  is replaced by a generating circuitry  13 I. 
     The generating circuitry  13 I generates the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n and delimiter frames KFR_ 1  to KFR_m in the manner described below. Further, the generating circuitry  13 I generates the check frames CHK in the manner described above. 
     Then, the generating circuitry  13 I outputs the header frames HFR_ 1  to HFR_i, data frames DFR_ 1  to DFR_n, delimiter frames KFR_ 1  to KFR_m and check frames CHK to the transmitting circuitry  12 . 
     In the transmitter  1001 , the transmitting circuitry  12  transmits the header frames HFR_ 1  to HFR_i, q delimiter frames KFR_ 1 , q data frames DFR_1, . . . , the q delimiter frames KFR_m, q data frames DFR_n and q check frames CHK one after another in accordance with the CSMA/CA scheme. 
       FIG. 81  is a schematic diagram of the receiver of  FIG. 79 . Referring to  FIG. 81 , the receiver  1002  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  is replaced by a determination circuit  25 I and the decoder  26  is replaced by a decoder  26 B. 
     When the decoder circuit  25 I has detected the frame lengths of the header frames HFR_ 1  to HFR_i, it senses the beginning of the data to be transmitted. 
     Thereafter, when the determination circuit  25 I has received the q frame lengths of the q delimiter frames KFR_ 1  from the frame length detection circuit  24 , it enters into a state of waiting for a data frame DFR_ 1 ; when it has received the q frame lengths of the q data frames DFR_ 1  from the frame length detection circuit  24 , it enters into a state of waiting for a delimiter frame KFR_ 2 ; when it has received the q frame lengths of the q delimiter frames KFR_ 2  from the frame length detection circuit  24 , it enters into a state of waiting for a data frame DFR_ 2 ; and so forth, and when it has received the q frame lengths of the q delimiter frames KFR_m from the frame length detection circuit  24 , it enters into a state of waiting for a data frame DFR_n. Then, after the determination circuit  25 I has received the q frame lengths of the q data frames DFR_n from the frame length detection circuit  24 , it receives the frame lengths of the check frames CHK. 
     Then, the determination circuit  25 I outputs the q frame lengths of the q data frames DFR_ 1  to the q frame lengths of the q data frames DFR_n, the q frame lengths of the q delimiter frames KFR_ 1  to the q frame lengths of the q delimiter frames KFR_n and the frame lengths of the check frames CHK to the decoder  26 B. 
     Then, the decoder  26 B converts the q frame lengths of the q data frames DFR_ 1  to the q frame lengths of the q data frames DFR_n, the q frame lengths of the q delimiter frames KFR_ 1  to the q frame lengths of the q delimiter frames KFR_n and the frame length of the check frame CHK to q×n bit sequences, q×m bit sequences and one bit sequence in the manner described below, and, based on the converted q×n bit sequences, q×m bit sequences and one bit sequence, determines whether the q data frames DFR_ 1  to q data frames DFR_n are correct. Then, if the decoder  26 B determines that the q data frames DFR_ 1  to q data frames DFR_n are correct, the receiver has succeeded in receiving the data to be transmitted. 
       FIG. 82  schematically illustrates a radio frame according to Embodiment 11. Referring to  FIG. 82 , the radio frame WFR 10  of Embodiment 11 includes header frames HFR_ 1  to HFR_i, q delimiter frames KFR_ 1  to q delimiter frames KFR_m, q data frames DFR_ 1  to q data frames DFR_n, and q check frames CHK. 
     The q delimiter frames KFR_ 1  are positioned to follow the header frame HFR_i, the q data frames DFR_ 1  are positioned to follow the q delimiter frames KFR_ 1 , the q delimiter frames KFR_ 2  are positioned to follow the q data frames DFR_ 1 , the q data frames DFR_ 2  are positioned to follow the q delimiter frames KFR_ 2 , and so forth, the q data frames DFR_n−1 are positioned to follow the q delimiter frames KFR_m- 1 , the q delimiter frames KFR_m are positioned to follow the q data frames DFR_n−1, the q data frames DFR_n are positioned to follow the q delimiter frames KFR_m, and the q check frames CHK are positioned to follow the q data frames DFR_n. 
       FIG. 83  is a correspondence table illustrating the correspondence between the bit value of header information and frame length. 
     Referring to  FIG. 83 , the correspondence table TBL- 45  contains bit values of header information and frame lengths. The bit values of header information are associated with the frame lengths. 
     In header information, the bit value of “0000” is associated with the frame length of 715 μs, the bit value of “0001” is associated with the frame length of 745 μs, and in the same manner, the bit value of “1111” is associated with the frame length of 1165 μs. 
     Thus, in the correspondence table TBL- 45 , the frame length increases by 30 μs as the bit value of header information increases by “1”. 
       FIG. 84  is a correspondence table illustrating the correspondence between the bit value of delimiter information and frame length. 
     Referring to  FIG. 84 , the correspondence table TBL- 46  contains bit values of delimiter information and frame lengths. The bit values of delimiter information are associated with the frame lengths. 
     In delimiter information, the bit value of “0000” is associated with the frame length of 720 μs, the bit value of “0001” is associated with the frame length of 750 μs, and in the same manner, the bit value of “1111” is associated with the frame length of 1170 μs. 
     Thus, in the correspondence table TBL- 46 , the frame length increases by 30 μs as the bit value of delimiter information increases by “1”. 
       FIG. 85  is a correspondence table illustrating the correspondence between the bit value of a check frame and frame length. 
     Referring to  FIG. 85 , the correspondence table TBL- 47  contains bit values of check frames and frame lengths. The bit values of check frames are associated with the frame lengths. 
     In check frames, the bit value of “0000” is associated with the frame length of 725 μs, the bit value of “0001” is associated with the frame length of 755 μs, in the same manner, the bit value of “1111” is associated with the frame length of 1175 μs. 
     Thus, in the correspondence table TBL- 47 , the frame length increases by 30 μs as the bit value of a check frame increases by “1”. 
     The generating circuitry  13 I of the transmitter  1001  holds the correspondence tables TBL 1 , TBL- 45 , TBL- 46  and TBL- 47 . Then, the generating circuitry  13 I refers to the correspondence table TBL- 45  to generate the header frames HFR_ 1  to HFR_i having the frame lengths corresponding to the bit value of the header information. Further, the generating circuitry  13 I refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit value of the data to be transmitted. Furthermore, the generating circuitry  13 I refers to the correspondence table TBL- 46  to generate the delimiter frames KFR_ 1  to KFR_m having the frame lengths corresponding to the bit value of the delimiter information. Moreover, based on the bit sequences of the header frames HFR_ 1  to HFR_i, and the bit sequences of the q data frames DFR_ 1  to q data frames DFR_n, the generating circuitry  13 I calculates the bit value of the check frame in the manner described above, and refers to the correspondence table TBL- 47  to generate the check frame CHK having the frame length corresponding to the calculated bit value. 
     The determination circuit  25 I and decoder  26 B of the receiver  1002  each hold the correspondence tables TBL 1 , TBL- 45 , TBL- 46  and TBL- 47 . 
     Then, the determination circuit  25 I determines whether the a frame length received from the frame length detection circuit  24  is contained in one of the correspondence tables TBl 1 , TBL- 45 , TBL- 46  and TBL- 47 . If the frame length is contained in the correspondence table TBl 1 , the determination circuit  25 I determines that the frame length is one of the frame lengths of the data frames DFR_ 1  to DFR_n. If the frame length is contained in the correspondence table TBL- 45 , the determination circuit  25 I determines that the frame length is one of the frame lengths of the header frames HFR_ 1  to HFR_i. If the frame length is contained in the correspondence table TBL- 46 , the determination circuit  25 I determines that the frame length is one of the frame lengths of the delimiter frames KFR_ 1  to KFR_m. If the frame length is contained in the correspondence table TBL- 47 , the determination circuit  25 I determines that the frame length is the frame length of the check frames CHK. 
     The decoder  26 B refers to the correspondence tables TBL 1 , TBL- 45 , TBL- 46  and TBL- 47  to convert the frame lengths of the data frames DFR_ 1  to DFR_n, the frame lengths of the header frames HFR_ 1  to HFR_i, the frame lengths of the delimiter frames KFR_ 1  to KFR_m and the frame length of the check frames CHK to bit sequences, respectively. 
     Then, based on the converted bit sequences, the decoder  26 B determines whether the data frames DFR_ 1  to DFR_n are correct in the manner described above. When the decoder  26 B has determined that the data frames DFR_ 1  to DFR_n are correct, it arranges the n bit sequences of the data frames DFR_ 1  to DFR_n in one series and outputs the arranged bit sequence as the data to be transmitted. On the other hand, if the decoder  26 B has determined that the data frames DFR_ 1  to DFR_n are not correct, it discards the n bit sequences of the data frames DFR_ 1  to DFR_n. 
       FIG. 86  illustrates a specific example of the radio frame WFR 10  according to Embodiment 11. Referring to  FIG. 86 , the radio frame WFR 10 - 1  contains the header frames HFR_ 1  to HFR_ 3 , delimiter frames KFR_ 1  to KFR_ 3 , data frames DFR_ 1  to DFR_ 3  and check frames CHK. 
     The header frames HFR_ 1  to HFR_ 3  have the frame lengths of 805 μs, 985 μs and 895 μs, respectively; the delimiter frames KFR_ 1  to KFR_ 3  have the frame lengths of 990 μs, 810 μs and 1080 μs, respectively; and the data frames DFR_ 1  to DFR_ 3  have the frame lengths of 920 μs, 1100 μs and 770 μs, respectively. As a result, the check frame CHK has the frame length of 725 μs. 
     Then, the delimiter frames KFR_ 1  to KFR_ 3  and data frames DFR_ 1  to DFR_ 3  are consecutively transmitted three times. 
     The generating circuitry  13 I of the transmitter  1001  divides the header information into the 4-bit values “0011”, “1001” and “0110”, and refers to the correspondence table TBL- 45  to convert the bit values “0011”, “1001” and “0110” to the frame lengths of 805 μs, 985 μs and 895 μs, respectively. Then, the generating circuitry  13 I generates the header frames HFR_ 1  to HFR_ 3  having the frame lengths of 805 μs, 985 μs and 895 μs, respectively. 
     Further, the generating circuitry  13 I divides the data to be transmitted into the 4-bit values “0111”, “1101” and “0010”, and refers to the correspondence table TBL 1  to convert the bit values “0111”, “1101” and “0010” to the frame lengths of 920 μs, 1100 μs and 770 μs, respectively. Then, the generating circuitry  13 I generates the data frames DFR_ 1  to DFR_ 3  having the frame lengths of 920 μs, 1100 μs and 770 μs, respectively. 
     Furthermore, the generating circuitry  13 I divides the delimiter information into the 4-bit values “1001”, “0011” and “1100”, and refers to the correspondence table TBL- 46  to convert the bit values “1001”, “0011” and “1100” to the frame lengths of 990 μs, 810 μs and 1080 μs, respectively. Then, the generating circuitry  13 I generates the delimiter frames KFR_ 1  to KFR_ 3  having the frame lengths of 990 μs, 810 μs and 1080 μs, respectively. 
     Then, generating circuitry  13 I sums the bit values “0011”, “1001” and “0110” of the header frames HFR_ 1  to HFR_ 3 , the bit values “1001”, “0011” and “1100” of the delimiter frames KFR_ 1  to KFR_ 3  and the bit values “0111”, “1101” and “0010” of the data frames DFR_ 1  to DFR_ 3  and detects the four lowest-order bits of the sum to detect the bit value “0000”. Then, the generating circuitry  13 I refers to the correspondence table TBL- 47  to detect the frame length of 725 μs corresponding to the bit value “0000”, and generates the check frame CHK having the detected frame length of 725 μs. 
     Thereafter, the generating circuitry  13 I sequentially outputs the header frame HFR_ 1 , header frame HFR_ 2 , header frame HFR_ 3 , delimiter frame KFR_ 1 , data frame DFR_ 1 , delimiter frame KFR_ 2 , data frame DFR_ 2 , delimiter frame KFR_ 3 , data frame DFR_ 3  and check frame CHK to the transmitting circuitry  12 . 
     The transmitting circuitry  12  transmits the header frame HFR_ 1 , header frame HFR_ 2  and header frame HFR_ 3  one after another in accordance with the CSMA/CA scheme, then consecutively transmits the delimiter frame KFR_ 1  three times in accordance with the CSMA/CA scheme, then, consecutively transmits the data frame DFR_ 1  three times in accordance with the CSMA/CA scheme, then consecutively transmits the delimiter frame KFR_ 2  three times in accordance with the CSMA/CA scheme, then consecutively transmits the data frame DFR_ 2  three times in accordance with the CSMA/CA scheme, then consecutively transmits the delimiter frame KFR_ 3  three times in accordance with the CSMA/CA scheme, then consecutively transmits the data frame DFR_ 3  three times in accordance with the CSMA/CA scheme, and then consecutively transmits the check frame CHK three times in accordance with the CSMA/CA scheme. 
     The receiver  1002  sequentially receives the header frames HFR_ 1  to HFR_ 3 , three delimiter frames KFR_ 1 , three data frames DFR_ 1 , three delimiter frames KFR_ 2 , three data frames DFR_ 2 , three delimiter frames KFR_ 3 , three data frames DFR_ 3  and check frames CHK. 
     Then, the frame length detection circuit  24  of the receiver  1002  detects the frame lengths of 805 μs, 985 μs, 895 μs, triple 990 μs, triple 920 μs, triple 810 μs, triple 1100 μs, triple 1080 μs, triple 770 μs and triple 725 μs in the manner described above, and sequentially outputs the frame lengths of 805 μs, 985 μs, 895 μs, triple 990 μs, triple 920 μs, triple 810 μs, triple 1100 μs, triple 1080 μs, triple 770 μs and triple 725 μs that have been detected to the determination circuit  25 I. 
     The determination circuit  25 I sequentially receives the frame lengths of 805 μs, 985 μs, 895 μs, triple 990 μs, triple 920 μs, triple 810 μs, triple 1100 μs, triple 1080 μs, triple 770 μs and triple 725 μs, and determines whether the frame lengths of 805 μs, 985 μs, 895 μs, triple 990 μs, triple 920 μs, triple 810 μs, triple 1100 μs, triple 1080 μs, triple 770 μs and triple 725 μs that have been received are contained in the correspondence tables TBL 1 , TBL- 45 , TBL- 46  and TBL- 47 . 
     As a result, the determination circuit  25 I determines that the frame lengths of 805 μs, 985 μs and 895 μs are contained in the correspondence table TBL- 45 , to sense that the frame lengths of 805 μs, 985 μs and 895 μs are the frame lengths of the header frames HFR_ 1  to HFR_ 3 . Thus, the determination circuit  25 I senses the beginning of the data to be transmitted. 
     Thereafter, the determination circuit  25 I receives the triple frame length of 990 μs, and determines that the received triple frame length of 990 μs is contained in the correspondence table TBL- 46  to sense that the triple frame length of 990 μs is the frame length of the delimiter frame KFR_ 1 . Then, the determination circuit  25 I enters into a state of waiting for the data frame DFR_ 1 . 
     Thereafter, the determination circuit  25 I receives the triple frame length of 920 μs and determines that the received triple frame length of 920 μs is contained in the correspondence table TBL 1  to sense that the triple frame length of 920 μs is the frame length of the data frame DFR_ 1 . Then, the determination circuit  25 I enters into a state of waiting for the delimiter frame KFR_ 2 . 
     In the same manner, when the determination circuit  25 I has received the triple frame length of 810 μs, it senses that it has received the three delimiter frames KFR_ 2  and enters into a state of waiting for a data frame DFR_ 2 ; when it has received the triple frame length of 1100 μs, it senses that it has received the three data frames DFR_ 2  and enters into a state of waiting for a delimiter frame DFR_ 3 ; and when it has received the triple frame length of 1080 μs, it senses that it has received the three delimiter frames KFR_ 3  and enters into a state of waiting for a data frame DFR_ 3 . Then, when the determination circuit  25 I has received the triple frame length of 770 μs, it senses that it has received the three data frames DFR_ 3 , and then, when it has received the triple frame length of 725 μs, it senses that it has received the three check frames CHK. 
     Thus, the determination circuit  25 I detects that it has received the data frames DFR_ 1  to DFR_ 3  and delimiter frames KFR_ 1  to KFR_ 3  while repeating the state of waiting for a data frame and the state of waiting for a delimiter frame. 
     Then, the determination circuit  25 I sequentially outputs the frame lengths of 805 μs, 985 μs, 895 μs, triple 990 μs, triple 920 μs, triple 810 μs, triple 1100 μs, triple 1080 μs, triple 770 μs, and triple 725 μs to the decoder  26 B. 
     The decoder  26 B sequentially receives the frame lengths of 805 μs, 985 μs, 895 μs, triple 990 μs, triple 920 μs, triple 810 μs, triple 1100 μs, triple 1080 μs, triple 770 μs, and triple 725 μs. Then, the decoder  26 B refers to the correspondence table TBL- 45  to convert the frame lengths of 805 μs, 985 μs and 895 μs to the bit values of “0011”, “1001” and “0110”, respectively, and refers to the correspondence table TBL- 46  to convert the triple frame length of 990 μs to the triple bit value of “1001”, and refers to the correspondence table TBL 1  to convert the triple frame length of 920 μs to the triple bit value of “0111”. 
     Thereafter, the decoder  26 B refers to the correspondence table TBL- 46  to convert the triple frame length of 810 μs to the triple bit value of “0011”, and refers to the correspondence table TBL 1  to convert the triple frame length of 1100 μs to the triple bit value of “1101”. 
     Subsequently, the decoder  26 B refers to the correspondence table TBL- 46  to convert the triple frame length of 1080 μs to the triple bit value of “1100”, and refers to the correspondence table TBL 1  to convert the triple frame length of 770 μs to the triple bit value of “0010”. 
     Finally, the decoder  26 B refers to the correspondence table TBL- 47  to convert the triple frame length of 725 μs to the triple bit value of “0000”. 
     Then, the decoder  26 B sums the bit values of “0011”, “1001” and “0110” of the header frames HFR_ 1  to HFR_ 3 , the bit value of “1001” of the delimiter frame KFR_ 1 , the bit value of “0111” of the data frame DFR_ 1 , the bit value of “0011” of the delimiter frame KFR_ 2 , the bit value of “1101” of the data frame DFR_ 2 , the bit value of “1100” of the delimiter frame KFR_ 3 , and the bit value of “0010” of the data frame DFR_ 3  and detects the four lowest-order bits of the sum to detect the bit value of “0000”. Then, the decoder  26 B senses that the detected bit value of “0000” is equal to the bit value of “0000” of the check frame CHK, and determines that the data frames DFR_ 1  to DFR_ 3  are correct. Thereafter, the decoder  26 B outputs the triple bit value of “0111”, triple bit value of “1101” and triple bit value of “0010” of the three data frames DFR_ 1 , three data frames DFR_ 2  and the three data frames DFR_ 3  as the data to be transmitted. 
     Thus, as the data frames DFR_ 1  to DFR_ 3  and delimiter frames KFR_ 1  to KFR_ 3  are transmitted alternately, the receiver  1002  enters into a state of waiting for a data frame when it has received a delimiter frame and enters into a state of waiting for a delimiter frame when it has received a data frame. As a result, the receiver  1002  correctly receives each of the data frames DFR_ 1  to DFR_ 3  three times. This allows the same data to be received correctly. 
       FIG. 87  is a flow chart illustrating the operation of the wireless communication system  1000  of  FIG. 79 . 
     Referring to  FIG. 87 , when the operation is started, the transmitter  1001  generates the header frames HFR_ 1  to HFR_i, delimiter frames KFR_ 1  to KFR_m, data frames DFR_ 1  to DFR_n and check frame CHK in the manner described above (step S 71 ). 
     Then, the transmitter  1001  sets K-total number of the delimiter frames KFR_ 1  to KFR_m, data frames DFR_ 1  to DFR_n and check frames CHK (step S 72 ). 
     Thereafter, the same steps as steps S 3  to S 5  of the flow chart of  FIG. 8  are sequentially executed (step S 73  to S 75 ). 
     If it is determined at step S 75  that the wireless communication space is available, the transmitter  1001  consecutively transmits the kth frame q times (step S 76 ). 
     Then, the transmitter  1001  determines whether k=K (step S 77 ). If it is determined at step S 77  that k=K is not true, the transmitter  1001  sets k=k+1 (step S 78 ). Thereafter, the operation returns to step S 74 . Then, steps S 74  to S 78  described above are repeatedly executed until it is determined at step S 77  that k=K. 
     If it is determined at step S 77  that k=K, this circuitry that each of the delimiter frames KFR_ 1  to KFR_m, data frames DFR_ 1  to DFR_n and check frame CHK was consecutively transmitted q times. 
     After it is determined at step S 77  that k=K, the receiver  1002  detects envelopes of a plurality of received radio waves to detect a plurality of detection values (step S 79 ). Then, based on the plurality of wave detection values, the receiver  1002  detects a plurality of frame lengths in the manner described above (step S 80 ). 
     Thereafter, the receiver  1002  determines whether it has sensed the beginning of the data to be transmitted by determining whether it has received the header frames HFR_ 1  to HFR_i (step S 81 ). 
     If it is determined at step S 81  that the beginning of the data to be transmitted has not been sensed, the operation ends. 
     On the other hand, if it is determined at step S 81  that the beginning of the data to be transmitted has been sensed, the receiver  1002  determines whether it has received a delimiter frame in the manner described above (step S 82 ). 
     If it is determined at step S 82  that no delimiter frame has been received, the operation ends. 
     On the other hand, if it is determined at step S 82  that a delimiter frame has been received, the receiver  1002  enters into a state of waiting for a data frame (step S 83 ). Then, the receiver  1002  determines whether a data frame has been received in the manner described above (step S 84 ). 
     If it is determined at step S 84  that no data frame has been received, the operation ends. 
     On the other hand, if it is determined at step S 84  that a data frame has been received, the receiver  1002  enters into a state of waiting for a delimiter frame (step S 85 ). Then, the receiver  1002  determines whether all of the delimiter frames and data frames have been received (step S 86 ). 
     If it is determined at step S 86  that not all of the delimiter frames and data frames have been not received, the operation returns to step S 82 . Then, steps S 82  to S 86  described above are repeatedly executed until it is determined at step S 86  that all of the delimiter frames and data frames have been received. 
     If it is determined at step S 86  that all of the delimiter frames and data frames have been received, the receiver  1002  receives the check frame in the manner described above (step S 87 ), and converts the frame lengths of the header frames HFR_ 1  to HFR_i, delimiter frames KFR_ 1  to KFR_m, data frames DFR_ 1  to DFR_n and check frame CHK to bit values in the manner described above. 
     Then, the receiver  1002  determines whether the data frames are correct in the manner described above (step S 88 ). 
     If it is determined at step S 88  that the data frames are not correct, the operation ends. 
     On the other hand, if it is determined at step S 88  that the data frames are correct, the receiver  1002  has succeeded in receiving the data (step S 89 ), and the operation ends. 
     Thus, as the data frames DFR_ 1  to DFR_ 3  and delimiter frames KFR_ 1  to KFR_ 3  are transmitted alternately, the receiver  1002  enters into a state of waiting for a data frame when it has received a delimiter frame and enters into a state of waiting for a delimiter frame when it has received a data frame (see steps S 82  to S 85 ). Therefore, the receiver can correctly receive each of the data frames DFR_ 1  to DFR_ 3  one or more times. Further, the same data can be received correctly. 
     In Embodiment 11, a delimiter frame may be inserted into the sequence of the header frames HFR_ 1  to HFR_i in the manner described above. In this case, the receiver enters into a state of waiting for a header frame or data frame when it has received a delimiter frame, and enters into a state of waiting for a delimiter frame when it has received a header frame or data frame. This allows the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n to be received correctly. 
     In Embodiment 11, the operations of the transmitter  1001  and receiver  1002  may be carried out by a program. In such implementations, each of the transmitter  1001  and receiver  1002  includes a CPU, a ROM and a RAM. In the transmitter  1001 , the ROM stores a program S including step S 71  to S 78  shown in  FIG. 87 , and the CPU reads the program S from the ROM and executes it. 
     Thus, the operation of the transmitter  1001  is performed. In the receiver  1002 , the ROM stores a program T including steps S 79  to S 89  shown in  FIG. 87 , and the CPU reads the program T from the ROM and executes it. Thus, the operation of the receiver  1002  is performed. Further, each of the ROMs of the transmitter  1001  and receiver  1002  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 11 is the same as those of Embodiments 1 to 8. 
     Embodiment 12 
     Embodiment 12 describes an implementation where a transmitter transmits data indicating a control action and a receiver receives the data indicating a control action to control a device. In this implementation, the control action includes an absolute control and a relative control. The absolute control is a control that is completed in one round, such as on and off. The relative control is a control that gradually changes the state of the device, such as up and down for sound volume. 
     If a relative control is to be performed, the control action may be transmitted a plurality of times in series, but even then, the receiver may fail to receive the control action transmitted in one of these transmission rounds, making it difficult to perform the desired control. 
     In view of this, the following describes a method for controlling correctly the device when a relative control is performed. 
       FIG. 88  is a schematic diagram of a wireless communication system according to Embodiment 12. Referring to  FIG. 88 , the wireless communication system  1100  according to Embodiment 12 includes a transmitter  1101  and receiver  1102 . 
     The transmitter  1101  and receiver  1102  are positioned in a wireless communication space. The transmitter  1101  generates the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n in the manner described above. In this case, the data frames DFR_ 1  to DFR_n have the frame lengths corresponding to the bit values indicating the control action of the device  1103 . 
     Then, the transmitter  1101  transmits the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n in the manner described below. 
     The receiver  1102  sequentially receives the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n in the manner described below. Then, the receiver  1102  decodes the data frames DFR_ 1  to DFR_n into data, and outputs this data as the control action to the device  1103 . 
       FIG. 89  is a schematic diagram of the transmitter of  FIG. 88 . Referring to  FIG. 89 , the transmitter  1101  is the same as the transmitter  1  except that the transmitting circuitry  12  of the transmitter  1  is replaced by a transmitting circuitry  12 A, the generating circuitry  13  is replaced by a generating circuitry  13 J, and a timer  14  is added. 
     The generating circuitry  13 J refers to the correspondence table TBL- 45  and generates the header frames HFR_ 1  to HFR_i having the frame lengths corresponding to the bit values representing header information, and refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_n having the frame lengths corresponding to the bit values representing data to be transmitted (i.e. control action for the device  1103 ). Then, the generating circuitry  13 J outputs the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n that have been generated to the transmitting circuitry  12 A. 
     The transmitting circuitry  12 A receives the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n. Then, when the timer  14  has measured the cycle Tt, the transmitting circuitry  122 A consecutively transmits the header frame HFR_ 1  a plurality of times in accordance with the CSMA/CA scheme within the cycle Tt. Thereafter, when the timer  14  has measured the cycle Tt, the transmitting circuitry  12 A consecutively transmits the header frame HFR_ 2  a plurality of times in accordance with the CSMA/CA scheme within the cycle Tt. In the same manner, each time the timer  14  measures the cycle Tt, the transmitting circuitry  12 A consecutively transmits one header frame or one data frame a plurality of times in accordance with the CSMA/CA scheme within the cycle Tt to consecutively transmit each of the header frames HFR_ 3  to HFR_i and data frames DFR_ 1  to DFR_n a plurality of times. 
     The timer  14  measures the cycle Tt and provides the start timing and end timing of an cycle Tt to the transmitting circuitry  12 A. 
       FIG. 90  is a schematic diagram of the receiver of  FIG. 88 . Referring to  FIG. 90 , the receiver  1102  is the same as the receiver  2  except that the determination circuit  25  of the receiver  2  is replaced by a determination circuit  25 J, and a switch  27 , a control circuit  28  and a timer  29  are added. 
     The switch  27  is connected between the antenna  21  and BPF  22 . The switch  27  is turned on and off depending on the control signal CTL from the control circuit  28 . That is, the switch  27  is turned on when the control signal CTL is at H (i.e. logical high) level, and is turned off when the control signal CTL is at L (i.e. logical low) level. 
     When the control circuit  28  has received a start timing for a cycle Tr from the timer  29 , it outputs a control signal CTL at L level to the switch  27 , and, when it has received an end timing for the cycle Tr from the timer  29 , it outputs a control signal CTL at H level to the switch  27 . 
     Each time the timer  29  receives, from the determination circuit  25 J, a completion signal CPL indicating that it has completed reception of frame lengths, it measures a cycle Tr, and outputs a start timing and end timing for the cycle Tr to the control circuit  28 . 
     The determination circuit  25 J holds the correspondence tables TBL 1  and TBL- 45 . Then, the determination circuit  25 J refers to the correspondence tables TBL 1  and TBL- 45  and, when it determines that a frame length received from the frame length detection circuit  24  is one of the frame lengths of the header frames HFR_ 1  to HFR_i or data frames DFR_ 1  to DFR_n, it outputs the completion signal CPL to the timer  29 . 
     Further, if the determination circuit  25 J has detected the beginning of the data to be transmitted based on the frame lengths of the header frames HFR_ 1  to HFR_i, it outputs the plurality of frame lengths of the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n to the decoder  26 . 
     The decoder  26  refers to the correspondence tables TBL 1  and TBL- 45  to convert the plurality of frame lengths received from the determination circuit  25 J to bit sequences, and outputs the bit sequences corresponding to the data frames DFR_ 1  to DFR_n as a control action to the device  1103 . 
       FIG. 91  schematically illustrates a radio frame according to Embodiment 12. Referring to  FIG. 91 , the radio frame WFR 11  of Embodiment 12 includes header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n. 
     The data frames DFR_ 1  to DFR_n are positioned to follow the header frames HFR_ 1  to HFR_i. 
       FIG. 92  conceptually illustrates the method of transmitting frames and the method of receiving frames according to Embodiment 12.  FIG. 92  illustrates a method of transmitting and receiving frames in an example where each of the header frames and data frames is consecutively transmitted three times. 
     Referring to  FIG. 92 , within a first cycle Tt, the transmitter  1101  consecutively transmits the header frame H 1  three times in accordance with the CSMA/CA scheme in synchronization with the start timing of the first cycle Tt. 
     Then, when the receiver  1102  has completed reception of the first header frames H 1 , it measures the first cycle Tr beginning at the timing at which it completed reception of the header frames H 1 , and stops receiving frames from the transmitter  1101  from the start timing to end timing for the first cycle Tr. 
     Thereafter, within a second cycle Tt, the transmitter  1101  consecutively transmits the data frame D 1  three times in accordance with the CSMA/CA scheme in synchronization with the start timing of the second cycle Tt. 
     Then, the receiver  1102  fails to receive the first data frame D 1  and succeeds in receiving the second data frame D 1 . Then, when the receiver  1102  has completed reception of the second data frame D 1 , it measures a second cycle Tr beginning at the timing at which it completed reception of the data frame D 1 , and stops receiving frames from the transmitter  1101  from the start timing to end timing for the second cycle Tr. 
     In the same manner, within a cycle Tt, the transmitter  1101  consecutively transmits each of the data frames D 2  to Dn three times in accordance with the CSMA/CA scheme in synchronization with the start timing of the cycle Tt. 
     Then, for each of the data frames D 2  to Dn, the receiver  1102  succeeds in receiving one of the first to third data frames (i.e. first to third data frames of one of the data frames D 2  to Dn), and stops receiving frames from the transmitter  1101  in the time period of the cycle Tr beginning at the timing at which it completed reception of data frames. 
     Here, the following X, Y and N are prescribed. 
     X: maximum valid frame length of the header frame, data frame, sub-header frame, verification frame, end frame and delimiter frame; 
     Y: maximum frame transmission interval (for example, the time interval between H 1  and H 1 ); and 
     N: number of frames for one communication sequence. N is an integer not smaller than 2. 
     As a result, the cycles Tt and Tr should meet the following conditions:
 
 N ( X+Y )≤ Tt   (1), and
 
( N− 1)( X+Y )≤ Tr≤Tt −(minimum frame length)  (2).
 
     Equation (1) represents the condition that needs to be met to allow all the frames in one communication sequence to be transmitted. 
     Further, the timing at which reception of one frame is completed is the earliest if the receiver succeeds in receiving the first frame, then, the receiver must stop receiving frames in a time period where there is a possibility that it receives the remaining N−1 frames, and therefore, (N−1)(X+Y)≤Tr is satisfied. 
     Then, the cycle Tr must end before transmission of the next frame is started, then, the cycle Tr is the longest when the first frame is received in one communication sequence, and therefore, Tr≤Tt−(minimum frame length) is satisfied. 
     Thus, Equation (2) above is the required condition. 
       FIG. 93  illustrates a first specific example of a radio frame WFR 11  according to Embodiment 12. Referring to  FIG. 93 , the radio frame WFR 11 - 1  includes the header frame HFR_ 1  and the data frame DFR_ 1 . The header frame HFR_ 1  has the frame length corresponding to a bit value representing header information. The data frame DFR_ 1  has the frame length corresponding to a bit value indicating the control action of“on”. 
     The generating circuitry  13 J of the transmitter  1101  refers to the correspondence table TBL- 45  to generate the header frame HFR_ 1  having the frame length corresponding to the bit value indicating the header information, and refers to the correspondence TBL 1  to generate the data frame DFR_ 1  having the frame length corresponding to the bit value indicating the control action of “on”. 
     Then, within the cycle Tt, the transmitting circuitry  12 A consecutively transmits the header frame HFR_ 1  a plurality of times in synchronization with the start timing of the cycle Tt from the timer  14  in accordance with the CSMA/CA scheme, and then, again, within the cycle Tt, consecutively transmits the data frame DFR_ 1  a plurality of times in synchronization with the start timing of the cycle Tt from the timer  14  in accordance with the CSMA/CA scheme. 
     In the receiver  1102 , the switch  27  is turned on, and the BPF  22  receives the received radio wave of one of the plurality of header frames HFR_ 1  transmitted within the first cycle Tt, and outputs those portions of the received radio wave received that have the frequency of the radio frame WFR 11  to the envelope detection circuit  23 . 
     Then, the envelope detection circuit  23  detects the envelope of the received radio wave portions from the BPF  22  and outputs the detection values to the frame length detection circuit  24 . Based on the detection values from the envelope detection circuit  23 , the frame length detection circuit  24  detects the frame length in the manner described above, and outputs the detected frame length to the determination circuit  25 J. 
     The determination circuit  25 J detects that the frame length received from the frame length detection circuit  24  is contained in the correspondence table TBL- 45 , and determines that the it has received the frame length of the header frame HFR_ 1 . Then, the determination circuit  25 J outputs the completion signal CPL to the timer  29  and outputs the frame length to the decoder  26 . 
     In response to the completion signal CPL, the timer  29  measures the cycle Tr, and outputs the start timing and end timing for the cycle Tr to the control circuit  28 . In response to the start timing for the cycle Tr, the control circuit  28  outputs the control signal CTL at L level to the switch  27 , and, in response to the control signal CTL at L level, the switch  27  is turned off. Thus, the receiver  1102  stops receiving frames. 
     Thereafter, in response to the end timing for the cycle Tr, the control circuit  28  outputs the control signal CTL at H level to the switch  27 , and, in response to the control signal CTL at H level, the switch  27  is turned on. Thus, the receiver  1102  enters into a state of being able to receive frame lengths. 
     Then, the BPF  22  receives the received radio wave of one of the plurality of data frames DFR_ 1  transmitted within the second cycle Tt, and outputs those portions of the received radio wave received that have the frequency of the radio frame WFR 11  to the envelope detection circuit  23 . 
     Then, the envelope detection circuit  23  detects the envelope of the received radio wave portions from the BPF  22  and outputs the detection values to the frame length detection circuit  24 . Based on the detection values from the envelope detection circuit  23 , the frame length detection circuit  24  detects the frame length in the manner described above, and outputs the detected frame length to the determination circuit  25 J. 
     The determination circuit  25 J detects that the frame length received from the frame length detection circuit  24  is contained in the correspondence table TBL 1 , and determines that it has received the frame length of the data frame DFR_ 1 . Then, the determination circuit  25 J outputs the completion signal CPL to the timer  29  and outputs the frame length to the decoder  26 . 
     In response to the completion signal CPL, the timer  29  measures the cycle Tr, and outputs the start timing and end timing for the cycle Tr to the control circuit  28 . In response to the start timing for the cycle Tr, the control circuit  28  outputs the control signal CTL at L level to the switch  27 , and, in response to the control signal CTL at L level, the switch  27  is turned off. Thus, the receiver  1102  stops receiving frame lengths. 
     The decoder  26  receives the frame length of the header frame HFR_ 1  and the frame length of the data frame DFR_ 1 , refers to the correspondence table TBL- 45  to convert the frame length of the header frame HFR_ 1  to a bit sequence, and senses the beginning of the data to be transmitted. Thereafter, the decoder  26  refers to the correspondence table TBL 1  to convert the frame length of the data frame DFR_ 1  to a bit sequence, and outputs the bit sequence that indicates the control action of “on” to the device  1103 . Thus, the device  1103  is turned “on”. 
     The device  1103  is turned “off” in the same manner. 
       FIG. 94  illustrates a second specific example of the radio frame WFR 11  according to Embodiment 12. 
     Referring to  FIG. 94 , the radio frame WFR 11 - 2  includes the header frame HFR_ 1  and data frames DFR_ 1  to DFR_ 3 . The header frame HFR_ 1  has the frame length corresponding to the bit value indicating the header information. The data frames DFR_ 1  to DFR_ 3  has the frame length corresponding to the bit value indicating the control action of “up”. 
     The generating circuitry  13 J of the transmitter  1101  refers to the correspondence table TBL- 45  to generate the header frame HFR_ 1  having the frame length corresponding to the bit value indicating the header information, and refers to the correspondence table TBL 1  to generate the data frames DFR_ 1  to DFR_ 3  having the frame length corresponding to the bit value indicating the control action of “up”. 
     Within the cycle Tt, the transmitting circuitry  12 A consecutively transmits each of the header frame HFR_ 1  and data frames DFR_ 1  to DFR_ 3  a plurality of times in the manner described above. 
     Within the cycle Tt, the receiver  1102  completes reception of the frame lengths of the header frame HFR_ 1  and data frames DFR_ 1  to DFR_ 3  in the manner described above, and converts the frame lengths of the header frame HFR_ 1  and data frames DFR_ 1  to DFR_ 3  to bit sequences. 
     Then, the receiver  1102  outputs the three bit sequences of the data frames DFR_ 1  to DFR_ 3  to the device  1103 . Thus, the device  1103  increases its sound volume by three steps, for example, or increases its brightness by three steps. 
     The device  1103  decreases its sound volume or brightness in the same manner. 
       FIG. 95  is a flow chart illustrating the operation of the wireless communication system of  FIG. 88 . Referring to  FIG. 95 , when the operation is started, the transmitter  1101  generates the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n in the manner described above (step S 91 ). Then, the transmitter  1101  sets K-total number of the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n (step S 92 ). 
     Thereafter, the transmitter  1101  sets k=1 (step S 93 ), and performs carrier sensing (step S 94 ). 
     Based on the result of carrier sensing, the transmitter  1101  determines whether the wireless communication space is available (step S 95 ), and, if it determines that the wireless communication space is available, it further determines whether the current timing is the start timing for the kth cycle Tt (step S 96 ). If it determines that the current timing is the start timing for the kth cycle Tt, the transmitter  1101  consecutively transmits the kth frame a plurality of times (step S 97 ). 
     Thereafter, the receiver  1102  receives the received radio wave of one of the plurality of the kth frames (step S 98 ). Then, the receiver  1102  detects the envelope of the received radio wave and detects the detection values (step S 99 ), and detects the frame length based on the detection value (step S 100 ). 
     The receiver  1102  determines whether it has detected a valid frame length in the manner described above (step S 101 ). If it is determined at step S 101  that no valid frame length has been detected, the operation ends. 
     On the other hand, if it is determined at step S 101  that a valid frame length has been detected, the receiver  1102  starts measuring the cycle Tr (step S 102 ), and stops reception (step S 103 ). 
     Thereafter, the receiver  1102  determines whether the current time is the end timing for the cycle Tr (step S 104 ), and, if it is determined that the current time is the end timing for the cycle Tr, it transitions to the state in which it is ready to receive (step S 105 ). 
     Then, the receiver  1102  determines whether it has received all of the header frames and data frames (step S 106 ). 
     If it is determined at step S 106  that all of the header frames and data frames have been not received, the transmitter  1101  determines whether the current time is the end timing for the kth cycle Tt (step S 107 ), and, if it determines that the current time is the end timing for the kth cycle Tt, it further determines whether k=K (step S 108 ). If it is determined at step S 108  that k=K is not true, the transmitter  1101  sets k=k+1 (step S 109 ). Thereafter, the operation returns to step S 94 , and steps S 94  to S 108  described above are repeatedly executed until it is determined at step S 108  that k=K. 
     If it is determined at step S 108  that k=K, the transmitter  1101  stops transmission (step S 110 ). 
     On the other hand, if the receiver  1102  determines at step S 106  that it has received all of the header frames and data frames, it converts the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n to bit sequences in the manner described above, and outputs the bit sequences of the data frames DFR_ 1  to DFR_n to the device  1103  to control the device  1103  (step S 111 ). Then, after steps S 110  and S 111 , the operation ends. 
     Thus, the following is performed for all of the header frames and data frames within one cycle Tt: the transmitter  1101  consecutively transmits one frame a plurality of times, and the receiver  1102  receives one of the plurality of frame lengths transmitted by the transmitter  1101 . 
     This ensures that each of the header frames and data frames is absolutely received and, even when the device  1103  is under relative control, the device  1103  can be correctly controlled. 
     In the above description, the radio frame WFR 11  includes the header frames HFR_ 1  to HFR_i and data frames DFR_ 1  to DFR_n, Embodiment 12 is not limited to such an implementation, and the radio frame WFR 11  may further include at least one of the sub-header frame SHFR, verification frame VFR, end frame FFR, delimiter frame KFR and check frame CHK, described above. 
     Now, application examples of the wireless communication system  1100  will be described. 
     Application Example 1 
       FIG. 96  is a schematic view of the constitution of Application Example 1. Referring to  FIG. 96 , a control system  1100 A according to Application Example 1 includes a smartphone  20  and a key  30 . 
     The smartphone  20  includes the constitution of the transmitter  1101  shown in  FIG. 88 . The key  30  is carried around by the user of the smartphone  20 . 
     The key  30  includes a key body  31 , a ring  32  and a tab  33 . The key body  31  is connected to the tab  33  via the ring  32 . 
     The tab  33  includes a receiver  330 , and the receiver  330  has the same constitution as the receiver  1102  shown in  FIG. 88 . 
     The smartphone  20  uses GPS, for example, to acquire a current position and a current time. Then, the smartphone  20  places the bit sequence indicating the current position and the bit sequence indicating the current time on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  330  of the key  30 . 
     The receiver  330  receives the radio frame WFR 11  from the smartphone  20 . Then, based on the received radio wave, the receiver  330  detects the bit sequences of the data frames DFR_ 1  to DFR_n in the manner described above, and stores in the storage unit the current position and current time in an associated manner. 
     In this way, in Application Example 1, the smartphone  20  acquires a current position and a current time at fixed intervals and transmits the acquired current position and current time to the receiver  330  of the key  30 , and the receiver  330  stores in the storage unit the current position of the smartphone  20  and current time in an associated manner. 
     As a result, if by any chance the user of the smartphone  20  loses the smartphone  20 , he will know where and when he lost the smartphone  20  if he acquires the current positions and current times stored in the receiver  330  of the key  30 . That is, the last current position and current time stored in the receiver  330  indicate where and when the smartphone  20  was lost since no current position of the smartphone  20  and current time may be stored in the receiver  330  without the smartphone  20 . 
     In Application Example 1, the key  30  may be replaced by a watch; in generally, any object that the user of the smartphone  20  carries may be used. 
     As described above, in Application Example 1, information that allows the user of the smartphone  20  to know where and when he lost the smartphone  20  is transmitted to the receiver  330  mounted on an object carried by the user, where the information stored by the receiver  330  may be any information that allows the user to know where and when he lost the smartphone  20 . 
     Thus, in generally, Application Example 1 may be employed in cases where it is desired to know where and when a smartphone  20  was lost. 
     Alternatively, in Application Example 1, the smartphone  20  may transmit, instead of both a current position and current time, only a current time to the key  30  and the receiver  330  may store only the current time received from the smartphone  20  in the storage unit. If the user of the smartphone  20  knows the time when the receiver  330  ceased to receive time information from the smartphone  20 , he may try to remember where he was at that time and look for the smartphone  20 . 
     Application Example 2 
       FIG. 97  is a schematic view of the constitution of Application Example 2. Referring to  FIG. 97 , the control system  1100 B of Application Example 2 includes a smartphone  40 , a base station  50 , a cloud server  60  and a rain item  70 . 
     The smartphone  40  includes the constitution of the transmitter  1101  described above. 
     The rain item  70  includes an umbrella  71 , a receiver  72  and a Light Emitting Device (LED)  73 . The receiver  72  has the same constitution as the receiver  1102  described above. The receiver  72  and LED  73  are mounted on the umbrella  71 . 
     The smartphone  40  uses an application program installed thereon to automatically access the cloud server  60  via a wireless access network (a 3G link) of the base station  50 , and acquires a weather forecast from the cloud server  60 . 
     Then, the smartphone  40  places a bit sequence indicating the weather forecast on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  72  of the rain item  70 . 
     The receiver  72  receives the radio frame WFR 11  from the smartphone  40 . Then, based on the received radio wave, the receiver  72  detects the bit sequence in the manner described above and determines the content of the weather forecast based on the detected bit sequence, and, if the weather forecast says that it will rain, controls the LED  73  to be turned on. Then, the LED  73  is turned on in accordance with control by the receiver  72 . 
     In this way, the smartphone  40  transmits another information acquired via a network (i.e. a weather forecast) to the rain item  70  being controlled. Thus, the user of the smartphone  40  can go out to have to not forget the rain item  70 . 
     In Application Example 2, if the weather forecast says that it will rain, the umbrella  71  may be opened instead of the LED  73  being turned on. 
     In generally, as described above, Application Example 2 may be employed in cases where the user of the smartphone  40  does not forget carrying an object that he must carry when he goes out. 
     Application Example 3 
       FIG. 98  is a schematic view of the constitution of Application Example 3. Referring to  FIG. 98 , a control system  1100 C of Application Example 3 includes a smartphone  80 , an access point  90 , a smart meter  100 - 1 , lights  110  and  120 , and a control line  130 . 
     The access point  90 , smart meter  100 - 1  and lights  110  and  120  are connected to the control line  130 . The control  130  may comply with any standards. 
     The smartphone  80  includes the constitution of the transmitter  1101  described above. The light  110  includes a receiver  111  and the light  120  includes a receiver  121 . Each of the receivers  111  and  121  has the same constitution as the receiver  1102  described above. 
     The smartphone  80  uses an usual method to establish a radio link with the access point  90 . Then, the smartphone  80  accesses the access point  90  to transmit its authentication information to the access point  90 , and inquires of the access point  90  whether the lights  110  and  120  are controllable. 
     In response to the inquiry by the smartphone  80 , the access point  90  requests the smart meter  100 - 1  so as to transmit to itself the value of power that can be supplied to the two lights  110  and  120 . In response to the request by the access point  90 , the smart meter  100 - 1  transmits to the access point  90  the value of power that can be supplied to the two lights  110  and  120 . 
     The access point  90  receives from the smart meter  100 - 1  the value of power that can be supplied to the two lights  110  and  120 . The access point  90  holds in advance the value of power that allows the two lights  110  and  120  to be turned on. The access point  90  determines whether the smartphone  80  is an authenticated one based on the authentication information received from the smartphone  80 . If the access point  90  determines that the smartphone  80  is an authenticated one, it determines whether the value of power that can be supplied to the two lights  110  and  120  is larger than the value of power that allows the two lights  110  and  120  to turn on. If the value of power that can be supplied is larger than the value of power that allows the two lights  110  and  120  to turn on, the access point  90  permits that the smartphone  80  controls the lights  110  and  120 . Then, the access point  90  transmits, to the lights  110  and  120  via the control line  130 , a signal that allows the lights  110  and  120  to be controlled by the smartphone  80 . Thus, controls are possible through the control line  130 . 
     If the smartphone  80  is permitted by the access point  90  to control the lights  110  and  120 , it places a bit sequence indicating control actions for controlling the lighting intensity of the lights  110  and  120  on the data frames DFR_ 1  to DFR_n and transmits them to the receivers  111  and  121 , respectively, in accordance with the same operations as the transmitter  1101 . 
     The receiver  111  receives a radio frame from the smartphone  80 . Then, based on the received radio wave, the receiver  111  detects the bit sequence in the manner described above, and controls the lighting intensity of the light  110  based on the detected bit sequence. 
     The receiver  121  receives a radio frame from the smartphone  80 . Then, based on the received radio wave, the receiver  121  detects the bit sequence in the manner described above, and controls the lighting intensity of the light  120  based on the detected bit sequence. 
     Thus, in Application Example 3, the smartphone  80  can control the lights  110  and  120  on the conditions that it is allocated to the access point  90  and it has obtained permission from the access point  90  to control the lights  110  and  120 . 
     Further, the controlling of the lights  110  and  120  by the smartphone  80  may be limited to the time period in which controls are possible through the control line  130 . 
     In generally, as described above, Application Example 3 may be employed in cases where the controlling of the controlled devices (i.e. lights  110  and  120 ) is to be restricted based on local information held by the smart meter  100 - 1  and the authentication information of the smartphone  80  held by the access point  90 . 
     Application Example 4 
       FIG. 99  is a schematic view of the constitution of Application Example 4. Referring to  FIG. 99 , a control system  1100 D according to Application Example 4 includes a smartphone  140  and printer  150 . 
     The smartphone  140  has the same constitution as the transmitter  1101  described above. The printer  150  includes a receiver  151 . The receiver  151  has the same constitution as the receiver  1102  described above. 
     The smartphone  140  and printer  150  are provided in the same room. That is, the printer  150  is located near the smartphone  140 . The printer  150  gets on standby at a low power consumption if it has not been used for a certain period of time (for example, 10 minutes). The low power consumption may be 10% to 30% of the power consumption found during normal operation, for example; in generally, any value smaller than the power consumption found during normal operation may be used. 
     The smartphone  140  places a bit sequence indicating a control action for the printer  150  on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  151  of the printer  150 . 
     The receiver  151  receives the radio frame from the smartphone  140 . Then, based on the received radio wave, the receiver  151  detects the bit sequence in the manner described above, and activates the printer  150  based on the detected bit sequence. 
     After the printer  150  is activated in accordance with control by the receiver  151 , it gets on standby at a low power consumption if a certain period of time goes by after the completion of use by the holder of the smartphone  140 . 
     In this way, in Application Example 4, the smartphone  140  activates the printer  150  located near itself. Thus, when the holder of the smartphone  140  desires to use the printer  150 , he may remotely activate the printer  150  to print various data. Also, the power consumption of the printer  150  may be saved. 
     Alternatively, in Application Example 4, the control system  1100 D may include a personal computer instead of the smartphone  140 . In this case, the personal computer activates the printer  150  in accordance with the same operations as the smartphone  140 . 
     The printer  150  may be in any position that can be associated with the positional information of the smartphone  140 . 
     Application Example 5 
       FIG. 100  is a schematic view of the constitution of Application Example 5. Referring to  FIG. 100 , a control system  1100 E according to Application Example 5 includes a smartphone  160 , a VTR  170 , a game machine  180  and a television  190 . 
     The smartphone  160 , VTR  170 , game machine  180  and television  190  are positioned in one house. 
     The smartphone  160  has the same constitution as the transmitter  1101  described above. The VTR  170  includes a receiver  171 . The game machine  180  includes a receiver  181 . The television  190  includes a receiver  191 . Each of the receivers  171 ,  181  and  191  has the same constitution as the receiver  1102  described above. 
     In a manner similar to that in the transmitter  1101 , the smartphone  160  places a bit sequence indicating one of the control action of turning on the VTR  170 , the control action of turning off the VTR  170 , the control action of increasing the sound volume of the VTR  170  and the control action of reducing the sound volume of the VTR  170  on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  171 . 
     In a manner similar to that in the transmitter  1101 , the smartphone  160  places a bit sequence indicating one of the control action of turning on the game machine  180 , the control action of turning off the game machine  180 , the control action of increasing the sound volume of the game machine  180  and the control action of reducing the sound volume of the game machine  180  on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  181 . 
     In a manner similar to that in the transmitter  1101 , the smartphone  160  places a bit sequence indicating one of the control action of turning on the television  190 , the control action of turning off the television  190 , the control action of increasing the sound volume of the television  190  and the control action of reducing the sound volume of the television  190  on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  191 . 
     The receiver  171  of the VTR  170  receives the radio frame from the smartphone  160 . Based on the received radio wave, the receiver  171  detects the bit sequence in the manner described above, and, based on the detected bit sequence, turns on the VTR  170 , turns off the VTR  170 , increases the sound volume of the VTR  170 , or reduces the sound volume of the VTR  170 . 
     The receiver  181  of the game machine  180  receives the radio frame from the smartphone  160 . Based on the received radio wave, the receiver  181  detects the bit sequence in the manner described above, and, based on the detected bit sequence, turns on the game machine  180 , turns off the game machine  180 , increases the sound volume of the game machine  180 , or reduces the sound volume of the game machine  180 . 
     The receiver  191  of the television  190  receives the radio frame from the smartphone  160 . Based on the received radio wave, the receiver  191  detects the bit sequence in the manner described above, and, based on the detected bit sequence, turns on the television  190 , turns off the television  190 , increases the sound volume of the television  190 , or reduces the sound volume of the television  190 . 
     In this way, in Application Example 5, the smartphone  160  controls home electronics in a home to turn on/off and to increase/decrease the sound volume. Thus, the smartphone  160  may be used as a remote controller for home electronics. 
     Application Example 6 
       FIG. 101  is a schematic view of the constitution of Application Example 6. Referring to  FIG. 101 , a control system  1100 F according to Application Example 6 includes a smartphone  230 , an air conditioner  240  and a light  250 . 
     The smartphone  230  is carried by a person working in an office or commercial facilities. The air conditioner  240  and light  250  are positioned in the office or commercial facilities. 
     The smartphone  230  has the same constitution as the transmitter  1101  described above. The air conditioner  240  includes a receiver  241 . The light  250  includes a receiver  251 . Each of the receivers  241  and  251  has the same constitution as the receiver  1102  described above. 
     In a manner similar to that in the transmitter  1101 , the smartphone  230  places a bit sequence indicating the control action of saving the electricity used by the air conditioner  240  or a control action that depends on the desire of the holder of the smartphone  230  on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  241 . Control actions that depend on the desire of the holder of the smartphone  230  include, for example, causing relatively strong ventilation, causing relatively week ventilation, setting the temperature to a relatively high level, setting the temperature to a relatively low level, and ensuring that the holder of the smartphone  230  is not exposed to direct airflow from the air conditioner. 
     In a manner similar to that in the transmitter  1101 , the smartphone  230  places a bit sequence indicating the control action of saving the electricity used by the light  250 , or a control action that depends on the desire of the holder of the smartphone  230  on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  251 . Controls actions that depend on the desire of the holder of the smartphone  230  include, for example, increasing the brightness and reducing the brightness. 
     The receiver  241  of the air conditioner  240  receives the radio frame from the smartphone  230 . Then, based on the received radio wave, the receiver  241  detects the bit sequence in the manner described above, and, based on the detected bit sequence, increases the ventilation of the air conditioner  240 , reduces the ventilation of the air conditioner  240 , sets the temperature to be achieved by the air conditioner  240  to a high level, or sets the temperature to be achieved by the air conditioner  240  to a low level. 
     The receiver  251  of the light  250  receives a radio frame from the smartphone  230 . Then, based on the received radio wave, the receiver  251  detects the bit sequence in the manner described above, and, based on the detected bit sequence, increases the brightness of the light  250  or reduces the brightness of the light  250 . 
     In this way, in Application Example 6, a person working in the office or commercial facilities may use his own smartphone  230  to save the electricity used by the air conditioner  240  and light  250  or control the air conditioner  240  and light  250  as he wishes, while staying at his own desk. 
     Thus, energy conservation can be achieved in an office or commercial facilities. Also, the interior of the office or commercial facilities may be made more comfortable. 
     Alternatively, in Application Example 6, the control system  1100 F may include an electric device other than the air conditioner  240  and light  250 , and may include any electric device that is positioned in an office or commercial facilities. 
     The receivers  241  and  251  may be any receivers that are positioned in a building, in facilities or above facilities and are capable of controlling the air conditioner  240  and light  250  (i.e. the controlled elements) depending on the desire of a person using the building or facilities. 
     Application Example 7 
       FIG. 102  is a schematic view of the constitution of Application Example 7. Referring to  FIG. 102 , a control system  1100 G according to Application Example 7 includes a smartphone  260 , a shutter  270  and a light  280 . 
     The smartphone  260  is held by a resident of a building (for example, an apartment) including a living space in which the resident lives and a space for common use. The shutter  270  and light  280  are positioned in the space for common use in this building. 
     The smartphone  260  has the same constitution as the transmitter  1101  described above. The shutter  270  includes a receiver  271 . The light  280  includes a receiver  281 . Each of the receivers  271  and  281  has the same constitution as the receiver  1102  described above. 
     In a manner similar to that in the transmitter  1101 , the smartphone  260  places a bit sequence indicating the control action of opening the shutter  270  or the control action of closing the shutter  270  on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  271 . 
     In a manner similar to that in the transmitter  1101 , the smartphone  260  places a bit sequence indicating the control action of turning on the light  280  or the control action of turning off the light  280  on the data frames DFR_ 1  to DFR_n and transmits them to the receiver  281 . 
     The receiver  271  of the shutter  270  receives the radio frame from the smartphone  260 . Then, based on the received radio wave, the receiver  271  detects the bit sequence in the manner described above, and, based on the detected bit sequence, opens the shutter  270  or closes the shutter  270 . 
     The receiver  281  of the light  280  receives the radio frame from the smartphone  260 . Then, based on the received radio wave, the receiver  281  detects the bit sequence in the manner described above, and, based on the detected bit sequence, turns on the light  280  or turns off the light  280 . 
     In this way, in Application Example 7, a resident of an apartment or the like may use his smartphone  260  to control the shutter  270  and light  280  positioned in the space for common use of the apartment or the like. 
     Thus, the electricity used by electric devices positioned in a space for common use of an apartment or the like may be saved. Further, an electric device positioned in a space for common use of an apartment or the like may be freely controlled, thereby making the life in the apartment or the like more comfortable. 
     Alternatively, in Application Example 7, the control system  1100 G may include an electric device other than the shutter  270  and light  280 ; in generally, the system may include any electric device that is positioned in a space for common use of an apartment or the like. 
     The electric device may be controlled by a plurality of smartphones  260  (i.e. a plurality of transmitters  1101 ) carried by a plurality of persons. 
     Application Example 8 
       FIG. 103  is a schematic view of the constitution of Application Example 8. Referring to  FIG. 103 , a control system  1100 H according to Application Example 8 includes a smartphone  290 , a lock  310  and a case  320 . 
     The smartphone  290  has the same constitution as the transmitter  1101  described above. The lock  310  and case  320  are objects carried by the user of the smartphone  290 . The lock  310  includes a receiver  311  and the case  320  includes a receiver  321 . Each of the receivers  311  and  321  has the same constitution as the receiver  1102  described above. In this case, the receiver  311  controls a display device. The receiver  321  controls a Light Emitting Device (LED) or speaker. 
     When the case  320  is controlled, the smartphone  290  places a bit sequence indicating a control action on the data frames DFR_ 1  to DFR_n in the same manner as that in the transmitter  1101 , and transmits them to the receiver  321 . 
     The receiver  321  of the case  300  receives the radio frame from the smartphone  290 . Then, based on the received radio wave, the receiver  321  detects the bit sequence in the manner described above, and, based on the detected bit sequence, turns on the LED which serves as the controlled element. 
     Thus, the user of the smartphone  290  can see that the LED is on to find out where the case  300 , which is an object that he carries, is located. 
     If the receiver  321  controls a speaker, the receiver  321  controls the speaker to produce a sound. Thus, the user of the smartphone  290  can hear the sound produced by the speaker to find out where the case  320 , which is an object that he carries, is located. 
     When the lock  310  is controlled, the smartphone  290  uses GPS, for example, to acquire a current position and a current time. Then, the smartphone  290  places a bit sequence indicating the current position and a bit sequence indicating the current time on the data frames DFR_ 1  to DFR_n in the same manner as that in the transmitter  1101  and transmits them to the receiver  311  of the lock  310 . 
     The receiver  311  of the lock  310  receives the radio frame from the smartphone  290 . Then, based on the received radio wave, the receiver  311  detects the current position and current time based on the bit sequence in the manner described above, and stores in the storage unit the detected current position and current time in an associated manner, and displays the current position and current time on the display device. 
     Thus, the user of the smartphone  290  can monitor the lock  310 , which is an object that he carries. 
     Thus, Application Example 8 allows the smartphone  290  to control a “called object” or allows the smartphone  290  to control a “monitored object”. 
     Alternatively, the control system  10 I may include an object other than the lock  310  or case  320 , as long as the object is an “object to be called” by the smartphone  290  or an “object to be monitored” by the smartphone  290 . 
     In Embodiment 12, the operations of the transmitter  1101  and receiver  1102  may be carried out by a program. In such implementations, each of the transmitter  1101  and receiver  1102  includes a CPU, a ROM and a RAM. In the transmitter  101 , the ROM stores a program U including steps S 91  to S 97  and S 107  to S 110  shown in  FIG. 95 , and the CPU reads the program U from the ROM and executes it. Thus, the operation of the transmitter  1101  is performed. In the receiver  1102 , the ROM stores a program V including steps S 98  to S 106  and S 111  shown in  FIG. 95 , and the CPU reads the program V from the ROM and executes it. Thus, the operation of the receiver  1102  is performed. Further, each of the ROMs of the transmitter  1101  and receiver  1102  corresponds to the storage medium storing a computer- (i.e. CPU-) readable program. 
     Otherwise, the description of Embodiment 12 is the same as those of Embodiments 1 to 11. 
     In the above description, the receivers  2 ,  102 ,  202 ,  302 ,  402 ,  502 ,  602 ,  702 ,  702 A,  802 ,  902 ,  1002  and  1102  detect an envelope of a received radio wave of a radio frame; however, embodiments of the present invention are not limited to such implementations, and the receivers  2 ,  102 ,  202 ,  302 ,  402 ,  502 ,  602 ,  702 ,  702 A,  802 ,  902 ,  1002  and  1102  may perform synchronous detection on a received radio wave of a radio frame or perform regenerative detection on a received radio wave of a radio frame, or, in generally, it is only required that they detect a received radio wave of a radio frame. 
     In Embodiments 1 to 12 described above, various transmitter and receivers are described. Thus, a transmitter according to an embodiment of the present invention may include: a generating circuitry that generates a first radio frame having a frame length representing header information for data to be transmitted and a second radio frame having a frame length representing the data to be transmitted; and a transmitting circuitry that transmits the first radio frame and the second radio frame one after another in accordance with a wireless communication scheme to transmit a radio frame when a wireless communication space is available and to wait to transmit a radio frame when the wireless communication space is not available. 
     Further, a receiver according to an embodiment of the present invention may include: a receiving circuitry that sequentially receives a first radio frame having a frame length representing header information for data to be transmitted and a second radio frame having a frame length representing the data to be transmitted; a first detecting circuitry that detects a beginning of the data to be transmitted based on a received radio wave of the first radio frame; a second detecting circuitry that, when the beginning of the data to be transmitted is detected, detects the frame length of the second radio frame based on a received radio wave of the second radio frame; and a decoding circuitry that decodes the detected frame length into a bit sequence representing the data to be transmitted. 
     Furthermore, a program for causing a computer to execute transmission of radio frames in a transmitter according to an embodiment of the present invention may include: a first step in which a generating circuitry generates a first radio frame having a frame length representing header information of data to be transmitted and a second radio frame having a frame length representing the data to be transmitted; and a second step in which a transmitting circuitry transmits the first radio frame and the second radio frame one after another in accordance with a wireless communication scheme to transmit a radio frame when a wireless communication space is available and to wait to transmit a radio frame when the wireless communication space is not available. 
     Moreover, a program for causing a computer to execute reception of radio frames in a receiver according to an embodiment of the present invention may include: a first step in which a receiving circuitry sequentially receives a first radio frame having a frame length representing header information of data to be transmitted and a second radio frame having a frame length representing the data to be transmitted; a second step in which a first detecting circuitry detects a beginning of the data to be transmitted based on a received radio wave of the first radio frame; a third step in which, when the beginning of the data to be transmitted is detected, a second detecting circuitry detects the frame length of the second radio frame based on a received radio wave of the second radio frame; and a fourth step in which a decoding circuitry decodes the detected frame length into a bit sequence representing the data to be transmitted. 
     It should be understood that the embodiments disclosed herein are exemplary in every respect and not limiting. It is contemplated that the scope of the present invention is defined by the Claims and not by the above description of the embodiments, and includes all modifications within the spirit and scope equivalent to those of the Claims. 
     INDUSTRIAL APPLICABILITY 
     The present invention is applied to a program executed in a transmitter, a receiver, and a program executed in a receiver.