Patent Publication Number: US-11037868-B2

Title: Semiconductor device package and method of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/156,991, filed Oct. 10, 2018, which claims the benefit of and priority to U.S. Provisional Application No. 62/575,143, filed Oct. 20, 2017, the contents of which are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including a power die and a manufacturing method thereof. 
     2. Description of the Related Art 
     In a semiconductor device package (e.g., system in package, SIP), a molding compound is used to protect active or passive devices, but the molding compound will hinder the heat dissipation for the active or passive devices. To enhance the heat dissipation for the active or passive devices, the active or passive devices can be embedded in a carrier (leadframe or substrate) with more efficient heat dissipation design. 
     To form electrical connections for the embedded active or passive devices, a portion of insulation material (e.g., prepreg) which covers the active or passive devices may be removed (by e.g., a laser drilling technique) to form a via hole. Conductive material(s) (e.g., copper (Cu), silver (Ag) or the like) may be filled into the via hole by, for example, plating technique. The conductive contacts/terminals of the passive element for external connection generally include tin (Sn) or solder material. However, to facilitate manufacturing a conductive via for an embedded passive device by plating technique, the conductive contacts/terminals may be changed from solder/Sn to a material having relatively greater conductivity (e.g., Cu, Ag or other suitable material(s)), and such customized structure may inevitably increase the manufacturing cost of semiconductor device packages. 
     SUMMARY 
     In some embodiments, a semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. Each of the first conductive pad and the second conductive pad has a top surface and a bottom surface. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on the top surface of first conductive pad and the second conductive pad. The passive device has a first conductive contact and a second conductive contact. The conductive adhesive material electrically connects the first conductive contact and the second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes the bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to at least one of the first conductive pad and the second conductive pad. 
     In some embodiments, according to another aspect, a semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material and a dielectric layer. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. Each of the first conductive pad and the second conductive pad has a top surface and a bottom surface. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on the top surface of first conductive pad and the second conductive pad. The passive device has a first conductive contact and a second conductive contact. The first conductive contact and the second conductive contact include tin. The conductive adhesive material electrically connects the first conductive contact and the second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes the bottom surface of the first conductive pad and the second conductive pad. 
     In some embodiments, a method for manufacturing a semiconductor device package includes (a) proving a metal carrier having a first conductive pad and a second conductive pad connected to the first conductive pad through a connection part; (b) connecting a passive device to the first conductive pad and the second conductive pad through a conductive adhesive material; (c) forming a dielectric layer covering the metal carrier and the passive device; and (d) removing the connection part to separate the first conductive pad from the second conductive pad to form a space therebetween. The space is exposed from the dielectric layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure. 
         FIG. 1B  illustrates an enlarged view of a portion of the die pad in  FIG. 1A  in accordance with some embodiments of the present disclosure. 
         FIG. 1C  illustrates an enlarged view of a portion of the die pad in  FIG. 1A  in accordance with some embodiments of the present disclosure. 
         FIG. 1D  illustrates an enlarged view of a portion of the die pad in  FIG. 1A  in accordance with some embodiments of the present disclosure. 
         FIG. 2  illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure. 
         FIG. 3  illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure. 
         FIG. 4  illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure. 
         FIG. 5A ,  FIG. 5B ,  FIG. 5C ,  FIG. 5D  and  FIG. 5E  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
         FIG. 6A ,  FIG. 6B ,  FIG. 6C  and  FIG. 6D  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
         FIG. 7A ,  FIG. 7B ,  FIG. 7C ,  FIG. 7D  and  FIG. 7E  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
         FIG. 8A ,  FIG. 8B  and  FIG. 8C  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
         FIG. 9A ,  FIG. 9B  and  FIG. 9C  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
         FIG. 10A ,  FIG. 10B  and  FIG. 10C  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
     
    
    
     Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. 
     DETAILED DESCRIPTION 
       FIG. 1A  illustrates a cross-sectional view of a semiconductor device package  1  in accordance with some embodiments of the present disclosure. The semiconductor device package  1  includes a metal carrier  10 , electronic components  11   a ,  11   b ,  11   c , a dielectric layer  12 , a conductive via  13  and a conductive layer  14 . 
     The metal carrier  10  may be a leadframe or a portion of a leadframe. For example, the metal carrier  10  is a leadframe including one or more die pads (or die paddles)  10   a ,  10   b  and  10   c . The die pads  10   a ,  10   b  and  10   c  are separated from each other. For example, there is a gap between any two adjacent die pads. In some embodiments, the metal carrier  10  is, or includes, copper or a copper alloy. In some embodiments, tin may be plated on the metal carrier  10 . In other embodiments, the metal carrier  10  includes one of, or a combination of, iron, an iron alloy, nickel, a nickel alloy, or another metal or metal alloy. In some embodiments, the metal carrier  10  is coated with a silver or copper layer. 
     In some embodiments, the die pad  10   a  includes a cavity  10   ar  for accommodating the electronic component  11   a . The die pad  10   a  includes two portions  10   a   1  and  10   a   2  physically spaced apart from each other. There is a gap  10   s  between the portion  10   a   1  of the die pad  10   a  and the portion  10   a   2  of the die pad  10   a . In some embodiments, the die pad  10   c  includes a cavity  10   cr  for accommodating the electronic component  11   c . In some embodiments, the top surfaces  10   a   3 ,  10   b   1  and  10   c   1  of the die pads  10   a ,  10   b  and  10   c  are substantially coplanar. Alternatively, the top surfaces  10   a   3 ,  10   b   1  and  10   c   1  of the die pads  10   a ,  10   b  and  10   c  may have different heights. In some embodiments, the bottom surfaces  10   a   4 ,  10   b   2  and  10   c   2  of the die pads  10   a ,  10   b  and  10   c  are substantially coplanar. 
       FIG. 1B  illustrates an enlarged view of a portion of the die pad  10   a  in  FIG. 1A  circled by a dotted-line rectangle A in accordance with some embodiments of the present disclosure. For the purpose of clarity, the conductive via  13  is omitted in  FIG. 1B . The portion  10   a   1  of the die pad  10   a  of the metal carrier  10  includes a conductive pad  10   p   1  and the portion  10   a   2  of the die pad  10   a  of the metal carrier  10  includes a conductive pad  10   p   2 . The conductive pad  10   p   1  includes a first lateral surface  10 L 11  and a second lateral surface  10 L 12 . The conductive pad  10   p   2  includes a first lateral surface  10 L 21  and a second lateral surface  10 L 22  which respectively facing toward the first lateral surface  10 L 11  and the second lateral surface  10 L 12  of the conductive pad  10   p   1 . In some embodiments, the first lateral surface  10 L 11  and the second lateral surface  10 L 12  are curved surfaces and connected to each other. The first lateral surface  10 L 21  and the second lateral surface  10 L 22  are curved surfaces and connected to each other. The first lateral surface  10 L 11  and the second lateral surface  10 L 12  of the conductive pad  10   p   1  are spaced apart from the first lateral surface  10 L 21  and the second lateral surface  10 L 22  of the conductive pad  10   p   2  to define the gap  10   s  therebetween. 
       FIG. 1C  illustrates an enlarged view of a portion of the die pad  10   a  in  FIG. 1A  circled by a dotted-line rectangle A in accordance with other embodiments of the present disclosure. For the purpose of clarity, the conductive via  13  is omitted in  FIG. 1C . The structure illustrated in  FIG. 1C  is similar to that in  FIG. 1B  except that in  FIG. 1C , the conductive pad  10   p   1  has one curved surface  10 L 13  and the conductive pad  10   p   2  has one curved surface  10 L 23 . The curved surface  10 L 13  is spaced apart from the curved surface  10 L 23  to define the gap  10   s  therebetween. 
     Referring back to  FIG. 1A , the electronic component  11   a  is disposed within the cavity  10   ar  of the die pad  10   a . In some embodiments, the electronic component  11   a  may include two conductive contacts, in which one conductive contact (which may be referred to as “the first conductive contact”) is electrically connected to the portion  10   a   1  of the die pad  10   a  (e.g., on the conductive pad  10   p   1  as shown in  FIG. 1B  or  FIG. 1C ) and the other conductive contact (which may be referred to as “the second conductive contact”) is electrically connected to the portion  10   a   2  of the die pad  10   a  (e.g., on the conductive pad  10   p   2  as shown in  FIG. 1B  or  FIG. 1C ). For example, the electronic component  11   a  is disposed across the gap  10   s . In some embodiments, the conductive contacts of the electronic component  11   a  include tin or its alloy. In some embodiments, the electronic component  11   a  is attached to the die pad  10   a  through a conductive adhesive layer  11   h  (e.g., a solder, a plating film or a metal film). In some embodiments, the electronic component  11   a  is a passive device such a resistor, a capacitor, an inductor, or a combination thereof. The electronic component  11   a  is electrically connected to the conductive via  13  through the die pad  10   a  of the metal carrier  10 . In some embodiments, the conductive via  13  includes tin or its alloy. 
     The electronic component  11   b  is disposed on the top surface  10   b   1  of the die pad  10   b  of the metal carrier  10 . In some embodiments, a backside surface of the electronic component  11   b  is attached to the die pad  10   b  of the metal carrier  10  through an adhesive layer (e.g., glue or tape). An active surface of the electronic component  11   b  is electrically connected to the conductive via  13 . The electronic component  11   b  may include a chip or a die including a semiconductor substrate, one or more integrated circuit devices and/or one or more overlying interconnection structures therein. The integrated circuit devices may include active devices such as transistors and/or passive devices such resistors, capacitors, inductors, or a combination thereof. In some embodiments, a thickness of the electronic component  11   b  is different from that of the electronic component  11   a . For example, the thickness of the electronic component  11   a  is greater than that of the electronic component  11   b.    
     The electronic component  11   c  is disposed within the cavity  10   cr  of the die pad  10   c . In some embodiments, a backside surface of the electronic component  11   c  is attached to the die pad  10   c  of the metal carrier  10  through an adhesive layer (e.g., glue or tape). An active surface of the electronic component  11   c  is electrically connected to the conductive via  13 . The electronic component  11   c  may include a chip or a die including a semiconductor substrate, one or more integrated circuit devices and/or one or more overlying interconnection structures therein. The integrated circuit devices may include active devices such as transistors and/or passive devices such resistors, capacitors, inductors, or a combination thereof. In some embodiments, a thickness of the electronic component  11   c  is different from that of the electronic component  11   b . For example, the thickness of the electronic component  11   c  is greater than that of the electronic component  11   b . In some embodiments, a top view of the conductive adhesive material  11   h , the adhesive layer between the electronic component  11   b  and the die pad  10   b  or the adhesive layer between the electronic component  11   c  and the die pad  10   c  can be any shapes depending on different design specifications. 
     The dielectric layer  12  is disposed on the die pads  10   a ,  10   b  and  10   c  to cover or encapsulate the electronic components  11   a ,  11   b  and  11   c . The dielectric layer  12  is disposed at the gap between any two adjacent die pads. For example, the dielectric layer  12  is disposed between the die pad  10   a  and the die pad  10   b  and the gap between the die pad  10   b  and the die pad  10   c . The dielectric layer  12  exposes the bottom surfaces  10   a   4 ,  10   b   2  and  10   c   2  of the die pads  10   a ,  10   b  and  10   c . In some embodiments, a bottom surface  122  of the dielectric layer  12  is substantially coplanar with the bottom surfaces  10   a   4 ,  10   b   2  and  10   c   2  of the die pads  10   a ,  10   b  and  10   c . In some embodiments, the dielectric layer  12  may include molding compounds, pre-impregnated composite fibers (e.g., pre-preg), Borophosphosilicate Glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, Undoped Silicate Glass (USG), any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, an epoxy resin including fillers dispersed therein. Examples of a pre-preg may include, but are not limited to, a multi-layer structure formed by stacking or laminating a number of pre-impregnated materials/sheets. 
     In some embodiments, the dielectric layer  12  exposes a least a portion of the gap  10   s  between the portion  10   a   1  of the die pad  10   a  and the portion  10   a   2  of the die pad  10   a . For example, as shown in  FIG. 1B , the dielectric layer  12  is disposed between the first lateral surface  10 L 11  of the conductive pad  10   p   1  and the first lateral surface  10 L 21  of the conductive pad  10   p   2 , and the dielectric layer  12  exposes a space between the second lateral surface  10 L 12  of the conductive pad  10   p   1  and the second lateral surface  10 L 22  of the conductive pad  10   p   2 . For example, as shown in  FIG. 1C , the dielectric layer  12  exposes the space between the curved surface  10 L 13  of the conductive pad  10   p   1  and the curved surface  10 L 23  of the conductive pad  10   p   2 . In some embodiments, the dielectric layer  12  is disposed between two conductive contacts of the electronic component  11   a  as shown in  FIG. 1B  and  FIG. 1C . Alternatively, the dielectric layer  12  may expose a portion of the conductive contacts of the electronic component  11   a  as shown in  FIG. 1D , which illustrates an enlarged view of a portion of the die pad  10   a  in  FIG. 1A  circled by a dotted-line rectangle A in accordance with some embodiments of the present disclosure. 
     The conductive layer  14  is disposed on a top surface  121  of the dielectric layer  12 . The conductive layer  14  is electrically connected to the electronic components  11   a ,  11   b  and  11   c  through the conductive vias  13 . In some embodiments, the conductive layer  14  and the conductive via  13  are formed of the same material. Alternatively, the conductive layer  14  and the conductive via  13  may include different materials. 
     In accordance with the embodiments as shown in  FIG. 1A , embedding both the active devices (e.g., the electronic components  11   b  and  11   c ) and the passive device (e.g., the electronic component  11   a ) within the dielectric layer  12  can improve the heat dissipation of the semiconductor device package  1 . Furthermore, in some embodiments, since the conductive contacts of the passive device (e.g., the electronic component  11   a ) and the conductive via  13  are formed of the same material (e.g., tin or its alloy), it is unnecessary to use a customized passive device, which would in turn reduce the manufacturing cost of semiconductor device package  1 . Moreover, placing the electronic components (e.g., the electronic components  11   a  and  11   c ) with relatively greater thickness into cavities (e.g.,  10   ar  and  10   cr ) can reduce the total thickness of the semiconductor device package  1 . 
       FIG. 2  illustrates a cross-sectional view of a semiconductor device package  2  in accordance with some embodiments of the present disclosure. The semiconductor device package  2  is similar to the semiconductor device package  1  shown in  FIG. 1A  and the differences therebetween are described below. As shown in  FIG. 2 , the die pad  20   a  does not have a gap. In addition, all the electronic components  11   a ,  11   b  and  11   c  are directly connected to the conductive vias  13 . 
       FIG. 3  illustrates a cross-sectional view of a semiconductor device package  3  in accordance with some embodiments of the present disclosure. The semiconductor device package  3  is similar to the semiconductor device package  2  shown in  FIG. 2  except that all the die pads of the metal carrier  30  have a cavity  30   c  to accommodate the electronic components  11   a ,  11   b  and  11   c.    
       FIG. 4  illustrates a cross-sectional view of a semiconductor device package  4  in accordance with some embodiments of the present disclosure. The semiconductor device package  4  is similar to the semiconductor device package  3  shown in  FIG. 3  except that the sidewall of the cavity of some die pads (e.g., the die pad  40   a ) of the metal carrier  40  is removed. In other words, unlike the die pad  30   a  in  FIG. 3  including a base portion  30   a   1  and an extension portion  30   a   2 , the die pad  40   a  in  FIG. 4  has a base portion  40   a   1  without an extension portion. 
       FIG. 5A ,  FIG. 5B ,  FIG. 5C ,  FIG. 5D  and  FIG. 5E  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. In some embodiments, the manufacturing process illustrated in  FIG. 5A ,  FIG. 5B ,  FIG. 5C ,  FIG. 5D  and  FIG. 5E  can be used to form the structure as shown in  FIG. 1B . 
     Referring to  FIG. 5A , a metal carrier  50  (e.g., a leadframe or a portion of a leadframe) is provided. The metal carrier  50  has a base portion  50   a  and an extension portion  50   b . The base portion  50   a  and the extension portion  50   b  define a cavity  50   c . The base portion  50   a  has a top surface  50   a   1  and a bottom surface  50   a   2  opposite to the top surface  50   a   1 . 
     Referring to  FIG. 5B , a recess  50   r   1  is formed on the top surface  50   a   1  of the base portion  50   a  of the metal carrier  50 . In some embodiments, the recess  50   r   1  can be formed by etching or other suitable operations. 
     Referring to  FIG. 5C , an electronic component  51  is disposed within the cavity  50   c  of the metal carrier  50 . The electronic component  51  is disposed on the base portion  50   a  of the metal carrier  50 . The electronic component  51  is disposed over the recess  50   r   1 . In some embodiments, the electronic component  51  may be a passive device (e.g., a resistor, a capacitor, an inductor or a combination thereof). The electronic component  51  includes two conductive contacts  51   a  and  51   b , in which the conductive contact  51   a  is disposed at one side of the recess  50   r   1  and the conductive contact  51   b  is disposed at an opposite side of the recess  50   r   1 . 
     Referring to  FIG. 5D , a dielectric layer  52  is formed to cover a portion of the metal carrier  50  and the electronic component  51 . The dielectric layer  52  exposes the bottom surface  50   a   2  of the metal carrier  50 . 
     Referring to  FIG. 5E , a portion of the dielectric layer  52  is removed to form an recess  50   r   2  on the bottom surface  50   a   2  of the metal carrier  50 . The recess  50   r   2  is formed corresponding to the recess  50   r   1 . The recess  50   r   2  is connected to the recess  50   r   1  to form a gap to divide the base portion  50   a  of the metal carrier  50  into two separated portions. 
       FIG. 6A ,  FIG. 6B ,  FIG. 6C  and  FIG. 6D  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. In some embodiments, the manufacturing process illustrated in  FIG. 6A ,  FIG. 6B ,  FIG. 6C  and  FIG. 6D  can be used to form the structure as shown in  FIG. 1C . The operation in  FIG. 6A  is carried out subsequent to the operation in  FIG. 5A . The manufacturing process illustrated in  FIG. 6A ,  FIG. 6B ,  FIG. 6C  and  FIG. 6D  is similar to that in  FIG. 5B ,  FIG. 5C ,  FIG. 5D  and  FIG. 5E  except that in  FIG. 6A , the recess  60   r   1  is formed on the bottom surface  50   a   2  of the base portion  50   a  of the metal carrier  50 . Therefore, as shown in  FIG. 6D , the sidewall of the gap has one curved surface while in  FIG. 5E , the sidewall of the gap has two curved surfaces connected to each other. 
       FIG. 7A ,  FIG. 7B ,  FIG. 7C ,  FIG. 7D  and  FIG. 7E  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
     Referring to  FIG. 7A , a metal carrier  70  (e.g., a leadframe or a portion of a leadframe) is provided. The metal carrier  70  includes a plurality die pads  70   a ,  70   b  and  70   c . In some embodiments, the die pad  70   a  is similar to the die pad illustrated in  FIG. 6A . Alternatively, the die pad  70   a  is similar to the die pad illustrated in  FIG. 5B . The die pads  70   b  and  70   c  are respectively similar to the die pads  10   b  and  10   c  illustrated in  FIG. 1A . Therefore, the descriptions for the die pads illustrated in  FIGS. 1A and 6A  are applicable herein. 
     Referring to  FIG. 7B , an electronic component  71   a  is disposed within the cavity  70   c  of the die pad  70   a , an electronic component  71   b  is disposed on the die pad  70   b , and an electronic component  71   c  is disposed within the cavity  70   r  of the die pad  70   c . In some embodiments, the electronic components  71   a ,  71   b  and  71   c  are similar to the electronic components  11   a ,  11   b  and  11   c  in  FIG. 1A , and thus the descriptions and properties of the electronic components  11   a ,  11   b  and  11   c  can be applicable to the electronic components  71   a ,  71   b  and  71   c . In some embodiments, the electronic component  71   a  is disposed before disposing the electronic components  71   b  and  71   c.    
     Referring to  FIG. 7C , a dielectric layer  72  is formed to cover or encapsulate the metal carrier  70  and the electronic components  71   a ,  71   b  and  71   c . In some embodiments, the dielectric layer  72  is similar to the dielectric layer  12  in  FIG. 1A , and thus the descriptions and properties of the dielectric layer  12  can be applicable to the dielectric layer  12 . In some embodiments, the dielectric layer  72  can be formed by lamination or other suitable operations. A conductive layer  74  is formed on the dielectric layer  72 . 
     Referring to  FIG. 7D , through vias  73  are formed to penetrate the dielectric layer  72  to electrically connect the die pads  70   a ,  70   b  and  70   c  with the conductive layer  72 . In some embodiments, the through vias  73  may be formed by the following operations: (i) forming through holes to penetrate the conductive layer  74  and the dielectric layer  72  to expose a portion of the die pads  70   a ,  70   b  and  70   c  (e.g., the conductive pads of the die pads  70   a ,  70   b  and  70   c ) by, for example, laser drilling; and (ii) filing conductive material (e.g., tin or its alloy) within the through holes by, for example, plating or other suitable operations. 
     A patterning operation is carried out on the conductive layer  74  to form the patterned conductive layer. A portion of the dielectric layer  72  below the electronic component  71   a  is removed to form a recess  70   s  (or gap) to divide the die pad  70   a  into two separated portions. In some embodiments, the structure illustrated in  FIG. 7D  is similar to the semiconductor device package  1  in  FIG. 1A , and thus the descriptions and properties of the semiconductor device package  1  can be applicable to the structure illustrated in  FIG. 7D . 
     Referring to  FIG. 7E , a solder mask (or solder resist)  75  is formed on the patterned conductive layer  74 . The solder mask  75  has one or more recesses to expose a portion of the patterned conductive layer  74 . Electrical contacts (e.g., solder balls)  76  are formed within the recesses to be electrically connected to the exposed portion of the patterned conductive layer  74 . In some embodiments, a singulation operation can be carried out by, for example, sawing or other suitable operations. 
       FIG. 8A ,  FIG. 8B  and  FIG. 8C  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
     Referring to  FIG. 8A , the metal carrier  20  (e.g., a leadframe or a portion of a leadframe) is provided. The metal carrier  20  is similar to the metal carrier  20  illustrated in  FIG. 2 . Then, the operations as shown in  FIGS. 7B, 7C and 7D  are carried out to form the structure as shown in  FIG. 8B  except that the operation for removing a portion of the dielectric layer  72  as shown in  FIG. 7D  can be omitted and that the through via  13  is electrically connected to the conductive contacts of the electronic component  11   a  rather than the die pad  20   a . In some embodiments, the structure illustrated in  FIG. 8B  is similar to the semiconductor device package  2  in  FIG. 2 , and thus the descriptions and properties of the semiconductor device package  2  can be applicable to the structure illustrated in  FIG. 8B . 
     Referring to  FIG. 8C , a solder mask (or solder resist)  85  is formed on the patterned conductive layer  14 . The solder mask  85  has one or more recesses to expose a portion of the patterned conductive layer  14 . Electrical contacts (e.g., solder balls)  86  are formed within the recesses to be electrically connected to the exposed portion of the patterned conductive layer  14 . In some embodiments, a singulation operation can be carried out by, for example, sawing or other suitable operations. 
       FIG. 9A ,  FIG. 9B  and  FIG. 9C  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
     Referring to  FIG. 9A , the metal carrier  30  (e.g., a leadframe or a portion of a leadframe) is provided. The metal carrier  30  is similar to the metal carrier  30  illustrated in  FIG. 3 . Then, the operations as shown in  FIGS. 7B, 7C and 7D  are carried out to form the structure as shown in  FIG. 9B  except that the operation for removing a portion of the dielectric layer  72  as shown in  FIG. 7D  can be omitted and that the through via  13  is electrically connected to the conductive contacts of the electronic component  11   a  rather than the die pad  30   a . In some embodiments, the structure illustrated in  FIG. 9B  is similar to the semiconductor device package  3  in  FIG. 3 , and thus the descriptions and properties of the semiconductor device package  3  can be applicable to the structure illustrated in  FIG. 9B . 
     Referring to  FIG. 9C , a solder mask (or solder resist)  95  is formed on the patterned conductive layer  14 . The solder mask  95  has one or more recesses to expose a portion of the patterned conductive layer  14 . Electrical contacts (e.g., solder balls)  96  are formed within the recesses to be electrically connected to the exposed portion of the patterned conductive layer  14 . In some embodiments, a singulation operation can be carried out by, for example, sawing or other suitable operations. 
       FIG. 10A ,  FIG. 10B  and  FIG. 10C  illustrate a manufacturing process in accordance with some embodiments of the present disclosure. 
     Referring to  FIG. 10A , the metal carrier  40  (e.g., a leadframe or a portion of a leadframe) is provided. The metal carrier  40  is similar to the metal carrier  40  illustrated in  FIG. 4 . In some embodiments, the extension portion of the die pad  40   a  can be removed by, for example, etching or other suitable operations. Then, the operations as shown in  FIGS. 7B, 7C and 7D  are carried out to form the structure as shown in  FIG. 10B  except that the operation for removing a portion of the dielectric layer  72  as shown in  FIG. 7D  can be omitted and that the through via  13  is electrically connected to the conductive contacts of the electronic component  11   a  rather than the die pad  40   a . In some embodiments, the structure illustrated in  FIG. 10B  is similar to the semiconductor device package  4  in  FIG. 4 , and thus the descriptions and properties of the semiconductor device package  4  can be applicable to the structure illustrated in  FIG. 4B . 
     Referring to  FIG. 10C , a solder mask (or solder resist)  105  is formed on the patterned conductive layer  14 . The solder mask  105  has one or more recesses to expose a portion of the patterned conductive layer  14 . Electrical contacts (e.g., solder balls)  106  are formed within the recesses to be electrically connected to the exposed portion of the patterned conductive layer  14 . In some embodiments, a singulation operation can be carried out by, for example, sawing or other suitable operations. 
     As used herein, the terms “substantially,” “substantial,” “approximately,” and “about” are used to denote small variations. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” or “substantially aligned” can refer to two surfaces within micrometers (μm) of lying along the same plane, such as within 100 μm, within 80 μm, within 60 μm, within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane. Two surfaces or components can be deemed to be “substantially perpendicular” if an angle therebetween is, for example, 90°±10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. When used in conjunction with an event or circumstance, the terms “substantially,” “substantial,” “approximately,” and “about” can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation. The term “substantially flat” can refer to a surface roughness (Ra) of about 20 μm or less, such as about 3 μm to about 20 μm, where a difference between a highest point and a lowest point of the surface is about 10 μm or less, such as about 5 μm to about 10 μm. As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component. 
     Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. 
     While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It can be clearly understood by those skilled in the art that various changes may be made, and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus, due to variables in manufacturing processes and such. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.