Patent Publication Number: US-2022231121-A1

Title: Isolation regions in integrated circuit structures

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of (and claims the benefit or priority under 35 U.S.C. § 120) U.S. application Ser. No. 16/829,590, filed Mar. 25, 2020 and entitled “ISOLATION REGIONS IN INTEGRATED CIRCUIT STRUCTURES”. The disclosure of the prior Application is considered part of and is incorporated by reference in the disclosure of this Application 
    
    
     BACKGROUND 
     Electronic components may include active electrical elements, such as transistors. The design of these elements may impact the size, performance, and reliability of the electronic component. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings. 
         FIGS. 1A-1D  are cross-sectional views of an integrated circuit (IC) structure, in accordance with various embodiments. 
         FIGS. 2A-2D, 3A-3D, 4A-4D, 5A-5D, 6A-6D, 7A-7D, 8A-8D, 9A-9D, 10A-10D, 11A-11D, 12A - 12 D,  13 A- 13 D,  14 A- 14 D,  15 A- 15 D,  16 A- 16 D,  17 A- 17 D,  18 A- 18 D,  19 A- 19 D,  20 A- 20 D,  21 A- 21 D,  22 A- 22 D,  23 A- 23 D,  24 A- 24 D,  25 A- 25 D,  26 A- 26 D,  27 A- 27 D,  28 A- 28 D,  29 A- 29 D,  30 A- 30 D,  31 A- 31 D,  32 A- 32 D,  33 A- 33 D,  34 A- 34 D,  35 A- 35 D,  36 A- 36 D,  37 A- 37 D,  38 A- 38 D,  39 A- 39 D,  40 A- 40 D, and  41 A- 41 D are cross-sectional views of stages in an example process of manufacturing the IC structure of  FIGS. 1A-1D , in accordance with various embodiments. 
         FIGS. 42A-42D  are cross-sectional views of another IC structure, in accordance with various embodiments. 
         FIG. 43  is a cross-sectional view of another IC structure, in accordance with various embodiments. 
         FIGS. 44-47  illustrate example IC structure layouts, in accordance with various embodiments. 
         FIG. 48  is a top view of a wafer and dies that may include an IC structure in accordance with any of the embodiments disclosed herein. 
         FIG. 49  is a side, cross-sectional view of an IC component that may include an IC structure in accordance with any of the embodiments disclosed herein. 
         FIG. 50  is a side, cross-sectional view of an IC package that may include an IC structure in accordance with any of the embodiments disclosed herein. 
         FIG. 51  is a side, cross-sectional view of an IC component assembly that may include an IC structure in accordance with any of the embodiments disclosed herein. 
         FIG. 52  is a block diagram of an example electrical device that may include an IC structure in accordance with any of the embodiments disclosed herein. 
     
    
    
     DETAILED DESCRIPTION 
     Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometer; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region. 
     Gate-all-around (GAA) transistors may include a vertically oriented stack of lateral semiconductor channels (e.g., wire channels) wrapped by gate material. During operation, current may flow through these semiconductor channels, modulated by electrical signals applied to the gate and proximate source/drain (S/D) regions. However, an undesirable parasitic channel may also form under the transistor (e.g., in the substrate or other underlying materials) during operation; such parasitic channels may degrade transistor performance (e.g., may cause elevated source-to-drain leakage current in the transistor&#39;s off state). Such parasitic channel problems may be aggravated in GAA transistors relative to fin-based transistor because the parasitic “sub-fin” region may be too wide to gain any short channel control to suppress the leakage. 
     Disclosed herein are novel IC structures that may provide improved isolation between device regions (e.g., S/D and channel regions) and the underlying materials to mitigate or eliminate source-to-drain leakage through parasitic channels. The manufacturing techniques disclosed herein may provide such isolation without requiring the use of expensive conventional silicon-on-insulator (SOI) substrates, and without adding significant manufacturing complexity (thus speeding adoption and reducing cost). 
     In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. 
     Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. 
     For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The phrase “A or B” means (A), (B), or (A and B). The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features. 
     The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. As used herein, the term “insulating” means “electrically insulating” unless otherwise specified. For convenience, the phrase “ FIG. 1 ” may be used to refer to the collection of drawings of  FIGS. 1A-1D , the phrase “ FIG. 2 ” may be used to refer to the collection of drawings of  FIGS. 2A-2D , etc. 
       FIG. 1  provides cross-sectional views of an IC structure  100 , in accordance with various embodiments. In particular,  FIG. 1A  is a cross-sectional view taken through the section A-A of  FIGS. 1C and 1D  (perpendicular to the longitudinal axis of a channel region  202 , and across the source/drain regions  128 / 130  of different channel regions  202 ),  FIG. 1B  is a cross-sectional view taken through the section B-B of  FIGS. 1C and 1D  (perpendicular to the longitudinal axis of a channel region  202 , and across a gate  204  spanning multiple channel regions  202 ),  FIG. 10  is a cross-sectional view taken through the section C-C of  FIGS. 1A and 1B  (along the longitudinal axis of a channel region  202 ), and  FIG. 1D  is a cross-sectional view taken through the section D-D of  FIGS. 1A and 1B  (between adjacent channel regions  202 , parallel to the longitudinal axis of the channel regions  202 ). The “A,” “B,” “C,” and “D” sub-figures of  FIGS. 2-41  share the same perspectives as those of the sub-figures “A,” “B,” “C,” and “D” of  FIG. 1 , respectively. Although various ones of the accompanying drawings depict a particular number of device regions  206  (e.g., three), channel regions  202  (e.g., three) in a device region  206 , and a particular arrangement of channel materials  106  (e.g., two wires) in a channel region  202 , this is simply for ease of illustration, and an IC structure  100  may include more or fewer device regions  206  and/or channel regions  202 , and/or other arrangements of channel materials  106 . 
     A device region  206  may be oriented vertically relative to an underlying base  102 , with multiple device regions  206  arrayed along the base  102 . The base  102  may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The base  102  may include, for example, a crystalline substrate formed using a bulk silicon. The base  102  may include a layer of silicon dioxide on a bulk silicon or gallium arsenide substrate. The base  102  may include a converted layer (e.g., a silicon layer that has been converted to silicon dioxide during an oxygen-based annealing process). In some embodiments, the base  102  may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the base  102 . Although a few examples of materials from which the base  102  may be formed are described here, any material or structure that may serve as a foundation for an IC structure  100  may be used. The base  102  may be part of a singulated die (e.g., the dies  1502  of  FIG. 48 ) or a wafer (e.g., the wafer  1500  of  FIG. 48 ). In some embodiments, the base  102  may itself include an interconnect layer, an insulation layer, a passivation layer, an etch stop layer, additional device layers, etc. As shown in  FIG. 1 , the base  102  may include pedestals  222 , around which a dielectric material  110  may be disposed; the dielectric material  110  may include any suitable material, such as a shallow trench isolation (STI) material (e.g., an oxide material, such as silicon oxide). 
     The IC structure  100  may include one or more device regions  206  having channel material  106  with a longitudinal axis (into the page from the perspective of  FIGS. 1A and 1B , and left-right from the perspective of  FIGS. 1C and 1D ). The channel material  106  of a device region  206  may be arranged in any of a number of ways. For example,  FIG. 1  illustrates the channel material  106  of the device regions  206  as including multiple semiconductor wires (e.g., nanowires or nanoribbons in GAA, forksheet, double-gate, or pseudo double-gate transistors). Although various ones of the accompanying drawings depict a particular number of wires in the channel material  106  of a device region  206 , this is simply for ease of illustration, and a device region  206  may include more or fewer wires as the channel material  106 . More generally, any of the IC structures  100  disclosed herein or substructures thereof (e.g., the insulating material regions  158 , discussed below) may be utilized in a transistor having any desired architecture, such as forksheet transistors, double-gate transistors, or pseudo double-gate transistors. In some embodiments, the channel material  106  may include silicon and/or germanium. In some embodiments, the channel material  106  may include indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, or further materials classified as group II-VI, III-V, or IV. In some embodiments, the channel material  106  may include a semiconducting oxide (e.g., indium gallium zinc oxide). In some embodiments, the material composition of the channel material  106  used in different ones of the wires in a particular device region  206  may be different, or may be the same. 
     Source/drain (S/D) regions  128 / 130  may be in electrical contact with the longitudinal ends of the channel material  106 , allowing current to flow from one S/D region  128 / 130  to another S/D region  128 / 130  through the channel material  106  (upon application of appropriate electrical potentials to the S/D regions  128 / 130  through S/D contacts  164 ) during operation. Although  FIG. 1A  (and others of the accompanying drawings) depicts a single S/D contact  164  spanning (“shorting”) multiple S/D regions  128 / 130 , this is simply illustrative, and the S/D contacts  164  may be arranged so as to isolate and connect various ones of the S/D regions  128 / 130  as desired. As discussed further below with reference to  FIGS. 2-41 , the S/D regions  128  may have a particular dopant type (i.e., n-type or p-type) while the S/D regions  130  may have the opposite dopant type (i.e., p-type or n-type, respectively); the particular arrangement of S/D regions  128 / 130  in the accompanying drawings is simply illustrative, and any desired arrangement may be used (e.g., by appropriate selective masking). The S/D regions  128 / 130  may be laterally confined by insulating material regions including dielectric material  112 , dielectric material  118 , and dielectric material  120 ; these insulating material regions may provide barriers between S/D regions  128 / 130  in adjacent device regions  206 . As shown in  FIG. 1A , in some embodiments, the dielectric material  112  may have a U-shaped cross-section, with “spacers” formed of the dielectric material  118  thereon, and the dielectric material  120  therebetween. 
     In some embodiments, the S/D regions  128 / 130  may include a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, S/D regions  128 / 130  may include dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions  128 / 130  may include one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. For p-type metal oxide semiconductor (PMOS) transistors, S/D regions  128 / 130  may include, for example, group IV semiconductor materials such as silicon, germanium, silicon germanium, germanium tin, or silicon germanium alloyed with carbon. Example p-type dopants in silicon, silicon germanium, and germanium include boron, gallium, indium, and aluminum. For n-type metal oxide semiconductor (NMOS) transistors, S/D regions  128 / 130  may include, for example, group III-V semiconductor materials such as indium, aluminum, arsenic, phosphorous, gallium, and antimony, with some example compounds including indium aluminum arsenide, indium arsenide phosphide, indium gallium arsenide, indium gallium arsenide phosphide, gallium antimonide, gallium aluminum antimonide, indium gallium antimonide, or indium gallium phosphide antimonide. 
     The channel material  106  may be in contact with a gate dielectric  136 . In some embodiments, the gate dielectric  136  may surround the channel material  106  (e.g., when the channel material  106  includes wires, as shown in  FIG. 1 ). The gate dielectric  136  may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric  136  include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric  136  to improve its quality when a high-k material is used. 
     The gate dielectric  136  may be disposed between the channel material  106  and a gate metal  138 . In some embodiments, the gate metal  138  may surround the channel material  106  (e.g., when the channel material  106  includes wires, as shown in  FIG. 1 ). Together, the gate metal  138  and the gate dielectric  136  may provide a gate  204  for the associated channel material  106  in an associated channel region  202 , with the electrical impedance of the channel material  106  modulated by the electrical potential applied to the associated gate  204  (through gate contacts  140 ). The gate metal  138  may include at least one p-type work function metal or n-type work function metal (or both), depending on whether the transistor of which it is a part is to be a PMOS or an NMOS transistor. In some implementations, the gate metal  138  may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer (e.g., tantalum, tantalum nitride, an aluminum-containing alloy, etc.). In some embodiments, a gate metal  138  may include a resistance-reducing cap layer (e.g., copper, gold, cobalt, or tungsten). For a PMOS transistor, metals that may be used for the gate metal  138  include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed herein with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate metal  138  include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning). In some embodiments, the gate metal  138  may include grading (increasing or decreasing) of the concentration of one or more materials therein. Dielectric material  118  may separate the gate metal  138 , the gate dielectric  136 , and the gate contact  140  from the proximate S/D contacts  164 , and dielectric material  124  may separate the gate dielectric  136  from the proximate S/D regions  128 / 130 . The dielectric materials  118  and  124  may include silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxide doped with carbon, silicon oxynitride, or silicon oxynitride doped with carbon, for example. Together, a channel material  106 , gate dielectric  136 , gate metal  138 , and associated S/D regions  128 / 130  may form a transistor. 
     In the IC structure  100  of  FIG. 1 , an insulating material region  158  may be present between the S/D regions  128 / 130  and the base  102 ; the presence of such an insulating material region  158  may help isolate the S/D regions  128 / 130  from the underlying material, and thus mitigate or eliminate the formation of an undesirable parasitic channel in the underlying material, as discussed above. The insulating material regions  158  may include an oxide of the channel material  106 ; for example, if the channel material  106  is silicon, the insulating material regions  158  may include silicon oxide. As discussed below with reference to  FIGS. 2-41 , the insulating material regions  158  may be formed during the “release” of the channel material  106  from adjacent layers of sacrificial material  104 , and thus may be formed in the IC structure  100  without increasing the manufacturing complexity of the IC structure  100 . 
     The dimensions of the elements of the IC structure of  FIG. 1  (and others of the embodiments disclosed herein) may take any suitable form. For example, in some embodiments, a gate length  208  of a gate  204  may be between 3 nanometers and 100 nanometers; different ones of the gates  204  in a device region  206  may have the same gate length  208 , or different gate lengths  208 , as desired. In some embodiments, the width  210  of the channel material  106  may be between 3 nanometers and 30 nanometers. In some embodiments, the thickness  212  of the channel material  106  may be between 1 nanometer and 500 nanometers (e.g., between 5 nanometers and 40 nanometers when the channel material  106  is a wire). In some embodiments in which a channel region  202  includes semiconductor wires, the spacing  214  between adjacent ones of the wires in a channel region  202  may be between 5 nanometers and 40 nanometers. 
     In some embodiments, the IC structure  100  may be part of a memory device, and transistors of the IC structure  100  may store information in the IC structure  100  or facilitate access to (e.g., read and/or write) storage elements of the memory device. In some embodiments, the IC structure  100  may be part of a processing device. In some embodiments, the IC structure  100  may be part of a device that includes memory and logic devices (e.g., in a single die  1502 , as discussed below), such as a processor and cache. More generally, the IC structures  100  disclosed herein may be part of memory devices, logic devices, or both. 
       FIGS. 2-41  illustrate stages in an example process for manufacturing the IC structure  100  of  FIG. 1 . Although the operations of the process may be illustrated with reference to particular embodiments of the IC structures  100  disclosed herein, the process of  FIGS. 2-41  and variants thereof may be used to form any suitable IC structure. Operations are illustrated a particular number of times and in a particular order in  FIGS. 2-41 , but the operations may be reordered and/or repeated as desired (e.g., with different operations performed in parallel when manufacturing multiple IC structures  100  simultaneously). 
       FIG. 2  illustrates an assembly including a base  102 , a stack  148  of material layers on the base  102 , and a stack  230  of material layers on the base  102 . The stack  148  of material layers may include one or more layers of a second material  152  spaced apart from each other (and from the base  102 ) by intervening layers of a first material  150 , while the stack  230  of material layers may include one or more layers of the channel material  106  spaced apart from each other (and from the stack  148 ) by intervening layers of sacrificial material  104 . The size and arrangement of the material layers in the stack  230  of the assembly of  FIG. 2  corresponds to the desired size and arrangement of the channel material  106  in the IC structure  100 , as will be discussed further below, and thus the material layers in the assembly of  FIG. 2  may vary from the particular embodiment illustrated in  FIG. 2 . For example, the thickness of a layer of channel material  106  may correspond to the channel thickness  212  discussed above (though the thickness of the layer of channel material  106  may differ from the final channel thickness  212  due to material lost during processing, etc.), and the thickness of a layer of sacrificial material  104  may correspond to the wire spacing  214  discussed above (though the thickness of the layer of sacrificial material  104  may differ from the final wire spacing  214  due to material lost during processing, etc.). The sacrificial material  104  may be any material that may be appropriately selectively removed in later processing operations (as discussed below with reference to  FIG. 30 ). For example, the sacrificial material  104  may be silicon germanium, and the channel material  106  may be silicon. In another example, the sacrificial material  104  may be silicon dioxide and the channel material  106  may be silicon or germanium. In another example, the sacrificial material  104  may be gallium arsenide and the channel material  106  may be indium gallium arsenide, germanium, or silicon germanium. The assembly of  FIG. 2  may be formed using any suitable deposition techniques, such as chemical vapor deposition (CVD), metalorganic vapor phase epitaxy (MOVPE), molecular-beam epitaxy (MBE), physical vapor deposition (PVD), atomic layer deposition (ALD), or a layer transfer process. 
     The dimensions and material composition of the first material  150  and the second material  152  may be selected so that the techniques used to facilitate the “release” of the channel material  106  from the sacrificial material  104  (e.g., as discussed below with reference to  FIG. 36 ) cause the material of the stack  148  to turn into a dielectric material (forming the insulating material region  158 , discussed above with reference to  FIG. 1 ). For example, in some conventional techniques, the channel material  106  may be “released” during fabrication by performing a clean operation that oxidizes and etches the channel material  106  at a relatively slow rate, but that oxidizes and etches the sacrificial material  104  at a much faster rate. In such an embodiment, the first material  150  may be selected to have a same material composition as the sacrificial material  104 , the second material  152  may be selected to have a same material composition as the channel material  106 , and the thicknesses of the layers of first material  150  and second material  152  may be less than the thicknesses of the layers of sacrificial material  104  and channel material  106 , respectively (i.e., less than the wire spacing  214  and the channel thickness  212 , respectively) so that, during the clean operation, the first material  150  may be substantially etched away while the second material  152  is oxidized, resulting in an insulating material region  158  (as discussed below with reference to  FIG. 36 ). 
     In some such embodiments, the sacrificial material  104  and the first material  150  may include silicon germanium (e.g., silicon germanium having a germanium content that is greater than  30  atomic-percent), and the channel material  106  and the second material  152  may include silicon. Further, in some such embodiments, the thicknesses of the layers of first material  150  and second material  152  may be less than 3 nanometers, and the thicknesses of the layers of sacrificial material  104  and channel material  106  (i.e., the wire spacing  214  and the channel thickness  212 , respectively) may be greater than 3 nanometers. Other material combinations and thicknesses may be used as appropriate in accordance with teachings disclosed herein. 
       FIG. 3  illustrates an assembly subsequent to forming a patterned hardmask  108  on the assembly of  FIG. 2 . Forming the patterned hardmask  108  may include depositing the hardmask (using any suitable method) and then selectively removing portions of the hardmask  108  (e.g., using lithographic techniques) to form the patterned hardmask  108 . In some embodiments, the pattern of the patterned hardmask  108  may first be formed in another material on the initially deposited hardmask, and then the pattern may be transferred from the other material into the hardmask  108 . The locations of the hardmask  108  may correspond to the device regions  206  in the IC structure  100 , as discussed further below. In the embodiment of  FIG. 3 , the hardmask  108  may be patterned into multiple parallel rectangular portions (corresponding to the fins  220  discussed below). 
       FIG. 4  illustrates an assembly subsequent to forming fins  220  in the material stack of the assembly of  FIG. 2 , in accordance with the pattern of the patterned hardmask  108 . Etch techniques may be used to form the fins  220 , including wet and/or dry etch schemes, as well as isotropic and/or anisotropic etch schemes. The fins  220  may include the sacrificial material  104  and the channel material  106 , as well as a portion of the base  102 ; the portion of the base  102  included in the fins  220  provides a pedestal  222 . The width of the fins  220  may be equal to the width  210  of the channel material  106 , as discussed above. Any suitable number of fins  220  may be included in the assembly of  FIG. 4  (e.g., more or fewer than 3). Although the fins  220  depicted in  FIG. 4  (and others of the accompanying drawings) are perfectly rectangular, this is simply for ease of illustration, and in practical manufacturing settings, the shape of the fins  220  may not be perfectly rectangular. For example, the fins  220  may be tapered, widening toward the base  102 . The top surface of the fins  220  may not be flat, but may be curved, rounding into the side surfaces of the fins  220 , and these non-idealities may carry over into subsequent processing operations. In some embodiments, the pitch  101  of the fins  220  may be between 20 nanometers and 50 nanometers (e.g., between 20 nanometers and 40 nanometers). 
       FIG. 5  illustrates an assembly subsequent to forming a dielectric material  110  on the base  102  of the assembly of  FIG. 4 , between the fins  220 . The dielectric material  110  may include any suitable material, such as an STI material (e.g., an oxide material, such as silicon oxide). The dielectric material  110  may be formed by blanket depositing the dielectric material  110  and then recessing the dielectric material  110  back to a desired thickness. In some embodiments, the thickness of the dielectric material  110  may be selected so that the top surface of the dielectric material  110  is above the top surface of the pedestals  222  (e.g., approximately coplanar with a top surface of the stack  148 ). In some embodiments, the height  103  of a fin  220  above the top surface of the dielectric material  110  may be between 40 nanometers and 100 nanometers (e.g., between 50 nanometers and 70 nanometers). 
       FIG. 6  illustrates an assembly subsequent to forming a conformal layer of a dielectric material  112  over the assembly of  FIG. 5 . The dielectric material  112  may may be formed using any suitable technique (e.g., ALD). The dielectric material  112  may include any suitable material (e.g., silicon oxide). 
       FIG. 7  illustrates an assembly subsequent to forming a dielectric material  114  over the assembly of  FIG. 6 . The dielectric material  114  may extend over the top surfaces of the fins  220 , as shown, and may serve as a “dummy gate. ” The dielectric material  114  may include any suitable material (e.g., polysilicon). 
       FIG. 8  illustrates an assembly subsequent to forming a patterned hardmask  116  on the assembly of  FIG. 7 . The hardmask  116  may include any suitable materials (e.g., silicon nitride, carbon-doped silicon oxide, or carbon-doped silicon oxynitride). The hardmask  116  may be patterned into strips that are oriented perpendicular to the longitudinal axis of the fins  220  (into and out of the page in accordance with the perspective of  FIGS. 8C and 8D ), corresponding to the locations of the gates  204  in the IC structure  100 , as discussed further below. 
       FIG. 9  illustrates an assembly subsequent to etching the dielectric material  114  (the “dummy gate”) of the assembly of  FIG. 8  using the patterned hardmask  116  as a mask. The locations of the remaining dielectric material  114  may correspond to the locations of the gates  204  in the IC structure  100 , as discussed further below. 
       FIG. 10  illustrates an assembly subsequent to depositing a conformal layer of dielectric material  118  on the assembly of  FIG. 9 , and then performing a directional “downward” etch to remove the dielectric material  118  on horizontal surfaces, leaving the dielectric material  118  as “spacers” on side faces of exposed surfaces, as shown. The dielectric material  118  may be deposited to any desired thickness using any suitable technique (e.g., ALD). The dielectric material  118  may include any suitable dielectric material (e.g., silicon oxycarbonitride). The dielectric material  118  may border the fins  220  in the volumes that will be replaced by the S/D regions  128 / 130 , as discussed below. 
       FIG. 11  illustrates an assembly subsequent to depositing a dielectric material  120  on the assembly of  FIG. 10 . The dielectric material  120  may be blanket deposited over the assembly of  FIG. 10  and then the dielectric material  120  may be polished (e.g., by chemical mechanical polishing (CMP)) or otherwise recessed back so that the top surface of the dielectric material  120  is coplanar with the top surface of the patterned hardmask  116 , as shown in  FIGS. 11D and 110 . The dielectric material  120  may include any suitable material (e.g., an oxide, such as silicon oxide). 
       FIG. 12  illustrates an assembly subsequent to depositing a hardmask  126  on the assembly of  FIG. 11 . The hardmask  126  may have any suitable material composition; for example, in some embodiments, the hardmask  126  may include titanium nitride. 
       FIG. 13  illustrates an assembly subsequent to patterning the hardmask  126  of the assembly of  FIG. 12  so as to selectively remove the hardmask  126  in areas that will correspond to the S/D regions  130 , while otherwise leaving the hardmask  126  in place. Any suitable patterning technique (e.g., a lithographic technique) may be used to pattern the hardmask  126 . The particular arrangement of the S/D regions  130  in an IC structure  100  (and thus the particular layout of the patterned hardmask  126 ) depicted in various ones of the accompanying figures is simply illustrative, and any desired arrangement may be used;  FIG. 42  depicts an IC structure  100  with a different arrangement of S/D regions  130 , for example. 
       FIG. 14  illustrates an assembly subsequent to recessing the exposed dielectric material  120  of the assembly of  FIG. 13  (i.e., the dielectric material  120  not protected by the hardmask  126 ). Any suitable selective etch technique may be used to recess the exposed dielectric material  120 , such as an isotropic etch. In the areas not protected by the hardmask  126 , the dielectric material  120  may remain. 
       FIG. 15  illustrates an assembly subsequent to removing some of the dielectric material  118  exposed in the assembly of  FIG. 14 . This operation may enlarge the “canyons” between adjacent portions of hardmask  116 /dielectric material  114 , facilitating subsequent operations. In some embodiments, the removal of some of the dielectric material  118  may be achieved by a partial isotropic etch (e.g., a nitride partial isotropic etch when the dielectric material  118  includes a nitride). 
       FIG. 16  illustrates an assembly subsequent to further recessing the exposed dielectric material  120  of the assembly of  FIG. 15  (i.e., the dielectric material  120  not protected by the hardmask  126 ). Any suitable selective etch technique may be used to recess the exposed dielectric material  120 , such as an isotropic etch. In the areas not protected by the hardmask  126 , the dielectric material  120  may remain. 
       FIG. 17  illustrates an assembly subsequent to conformally depositing additional dielectric material  118  on the assembly of  FIG. 16 , and then performing another directional “downward” etch to remove the dielectric material  118  on horizontal surfaces, “repairing” the dielectric material  118  as “spacers” on side faces of exposed surfaces, as shown. The etch of  FIG. 17  (e.g., a reactive ion etch (RIE)) may also remove the dielectric material  112  from the top faces of the sacrificial material  104 , as shown. 
       FIG. 18  illustrates an assembly subsequent to removing the portions of the sacrificial material  104  and the channel material  106  in the assembly of  FIG. 17  that are not covered by the hardmask  126  to form open volumes  224  (e.g., using any suitable etch techniques). These open volumes  224  may correspond to the locations of the S/D regions  130  in the IC structure  100 , as discussed further below, and are self-aligned to the dielectric material  112 , as shown. 
       FIG. 19  illustrates an assembly subsequent to recessing the exposed sacrificial material  104  of the assembly of  FIG. 18 , without simultaneously recessing the exposed channel material  106  (as shown in  FIG. 19C ). Any suitable selective etch technique may be used. Since this partial lateral recess of the exposed sacrificial material  104  is self-aligned to the exposed channel material  106 , the recess of the exposed sacrificial material  104  may be uniform across the width of the channel material  106  (i.e., left-right from the perspective of  FIG. 19A ). 
       FIG. 20  illustrates an assembly subsequent to conformally depositing a dielectric material  124  over the assembly of  FIG. 19 . The dielectric material  124  may include any suitable material (e.g., a low-k dielectric material) and may be deposited so as to fill the recesses formed by recessing the exposed sacrificial material  104  (as discussed above with reference to  FIG. 19 ). In some embodiments, conformally depositing the dielectric material  124  may include multiple rounds of deposition (e.g., three rounds) of one or more dielectric materials. 
       FIG. 21  illustrates an assembly subsequent to recessing the dielectric material  124  of the assembly of  FIG. 20 . Any suitable selective etch technique may be used to recess the exposed dielectric material  124 , such as an isotropic etch. The dielectric material  124  may remain on side surfaces of the sacrificial material  104  proximate to the open volumes  224 , as shown in  FIG. 21C . The amount of recess may be such that the recessed surface of the dielectric material  124  is flush with (not shown) or slightly beyond the side surface of the channel material  106 , as shown in  FIG. 21C . Excessive recess of the exposed dielectric material  124  beyond the side surface of the channel material  106  may result in device performance degradation (e.g., due to elevated parasitic contact-to-gate coupling capacitance) and/or device defect (e.g., due to contact-to-gate short). 
       FIG. 22  illustrates an assembly subsequent to forming the S/D regions  130  in the open volumes  224  of the assembly of  FIG. 21 . The S/D regions  130  may be formed by epitaxial growth that seeds from the exposed surfaces of the base  102  and the channel material  106 , and the lateral extent of the S/D regions  130  (e.g., in the left-right direction of  FIG. 22A ) may be limited by the dielectric material  112  bordering the open volumes  224 . In some embodiments, the S/D regions  130  may include an n-type epitaxial material (e.g., heavily in-situ phosphorous-doped material for use in an NMOS transistor). In some embodiments, the epitaxial growth of the S/D regions  130  may include an initial nucleation operation to provide a seed layer, followed by a primary epitaxy operation in which the remainder of the S/D regions  130  are formed on the seed layer. 
       FIG. 23  illustrates an assembly subsequent to depositing a conformal layer of a dielectric material  142  on the assembly of  FIG. 22 . The dielectric material  142  may be a contact etch stop layer (CESL), and may be formed of any suitable material (e.g., silicon nitride). 
       FIG. 24  illustrates an assembly subsequent to depositing a dielectric material  122  on the assembly of  FIG. 23 , and then polishing the dielectric material  122  and the dielectric material  142  to expose the hardmask  126 . In some embodiments, the dielectric material  122  may be a pre-metal dielectric (PMD), such as an oxide material (e.g., silicon oxide). 
       FIG. 25  illustrates an assembly subsequent to removing the hardmask  126  from the assembly of  FIG. 24 , then depositing and patterning a hardmask  127 . The hardmask  127  may have any suitable material composition; for example, in some embodiments, the hardmask  127  may include titanium nitride. The hardmask  127  may be patterned so as to selectively remove the hardmask  127  in areas that will correspond to the S/D regions  128 , while otherwise leaving the hardmask  127  in place. Any suitable patterning technique (e.g., a lithographic technique) may be used to pattern the hardmask  127 . As noted above, the particular arrangement of the S/D regions  128  in an IC structure  100  (and thus the particular layout of the patterned hardmask  127 ) depicted in various ones of the accompanying figures is simply illustrative, and any desired arrangement may be used;  FIG. 42  depicts an IC structure  100  with a different arrangement of S/D regions  128 , for example. 
       FIG. 26  illustrates an assembly subsequent to recessing the exposed dielectric material  120  (i.e., the dielectric material  120  not protected by the hardmask  127 ) of the assembly of  FIG. 25 . Any suitable selective etch technique may be used to recess the exposed dielectric material  120 , such as an isotropic etch. 
       FIG. 27  illustrates an assembly subsequent to removing some of the dielectric material  118  exposed in the assembly of  FIG. 26 . This operation may enlarge the “canyons” between adjacent portions of hardmask  116 /dielectric material  114 , facilitating subsequent operations. In some embodiments, the removal of some of the dielectric material  118  may be achieved by a partial isotropic etch (e.g., a nitride partial isotropic etch when the dielectric material  118  includes a nitride). 
       FIG. 28  illustrates an assembly subsequent to further recessing the exposed dielectric material  120  of the assembly of  FIG. 27  (i.e., the dielectric material  120  not protected by the hardmask  127 ). Any suitable selective etch technique may be used to recess the exposed dielectric material  120 , such as an isotropic etch. 
       FIG. 29  illustrates an assembly subsequent to conformally depositing additional dielectric material  118  on the assembly of  FIG. 28 , and then performing another directional “downward” etch to remove the dielectric material  118  on horizontal surfaces, “repairing” the dielectric material  118  as “spacers” on side faces of exposed surfaces, as shown. The etch of  FIG. 29  (e.g., an RIE) may also remove the dielectric material  112  from the top faces of the sacrificial material  104 , as shown. 
       FIG. 30  illustrates an assembly subsequent to removing the portions of the sacrificial material  104  and the channel material  106  in the assembly of  FIG. 29  that are not covered by the hardmask  127  to form open volumes  225  (e.g., using any suitable etch techniques). These open volumes  225  may correspond to the locations of the S/D regions  128  in the IC structure  100 , as discussed further below, and are self-aligned to the dielectric material  112 , as shown. 
       FIG. 31  illustrates an assembly subsequent to recessing the exposed sacrificial material  104  of the assembly of  FIG. 30 , without simultaneously recessing the exposed channel material  106 , conformally depositing a dielectric material  124 , and recessing the dielectric material  124 . These operations may take any of the forms discussed above with reference to  FIGS. 19-21 . The dielectric material  124  may remain on side surfaces of the sacrificial material  104  proximate to the open volumes  225 , as shown in  FIG. 31C . 
       FIG. 32  illustrates an assembly subsequent to forming the S/D regions  128  in the open volumes  225  of the assembly of  FIG. 31 , depositing a conformal layer of a dielectric material  154 , and depositing a dielectric material  156 . The S/D regions  128  may be formed by epitaxial growth that seeds from the exposed surfaces of the base  102  and the channel material  106 , and the lateral extent of the S/D regions  128  (e.g., in the left-right direction of  FIG. 32A ) may be limited by the dielectric material  112  bordering the open volumes  225 . In some embodiments, the S/D regions  130  may include a p-type epitaxial material (e.g., heavily in-situ boron-doped material for use in a PMOS transistor). In some embodiments, the epitaxial growth of the S/D regions  128  may include an initial nucleation operation to provide a seed layer, followed by a primary epitaxy operation in which the remainder of the S/D regions  128  are formed on the seed layer. In some implementations, the S/D regions  128  may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in-situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions  128  may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. The dielectric material  154  may be a CESL, and may be formed of any suitable material (e.g., silicon nitride). In some embodiments, the dielectric material  156  may be a PMD, such as an oxide material (e.g., silicon oxide). 
       FIG. 33  illustrates an assembly subsequent to polishing the hardmask  127 , the dielectric material  122 , the dielectric material  142 , the dielectric material  154 , and the dielectric material  156  of the assembly of  FIG. 32  (e.g., using a CMP technique) to expose the hardmask  116  above the channel regions  202 . 
       FIG. 34  illustrates an assembly subsequent to removing the hardmask  116 , the dielectric material  114  (the “dummy gate”), and the dielectric material  112  from the assembly of  FIG. 33  to form open volumes  226 . Any suitable etch techniques may be used. 
       FIG. 35  illustrates an assembly subsequent to recessing the dielectric material  110  of the assembly of  FIG. 34  so that the side faces of the stack  148  (including the layers of first material  150  and second material  152 ) are exposed. Any suitable etch techniques may be used. 
       FIG. 36  illustrates an assembly subsequent to “release” of the channel material  106  in the stack  230  of the assembly of  FIG. 35  by removal of the sacrificial material  104 . As noted above, in some embodiments, the etch technique used to remove the sacrificial material  104  may cause the simultaneous removal of the layers of first material  150  in the stack  148  and oxidation of the layers of second material  152 , resulting in an insulating material region  158 , as shown. The insulating material regions  158  may be in contact with pedestals  222  of the base  102 , and may be disposed between the channel material  106  and the base  102  (as well as between the S/D regions  128 / 130  and the base  102 ). Further, the release operations may cause a thin layer of oxide  157  (e.g., silicon oxide, when the channel material  106  includes silicon) on the exposed surfaces of the channel material  106 . 
       FIG. 37  illustrates an assembly subsequent to performing a clean operation that removes the oxide  157  from the assembly of  FIG. 36 , and then forming a conformal gate dielectric  136  over the resulting assembly. The gate dielectric  136  may be formed using any suitable technique (e.g., ALD), and may include any of the materials discussed herein with reference to the gate dielectric  136 . 
       FIG. 38  illustrates an assembly subsequent to forming a gate metal  138  over the assembly of  FIG. 37 . The gate metal  138  may include any one or more material layers, such as any of the materials discussed herein with reference to the gate metal  138 . 
       FIG. 39  illustrates an assembly subsequent to polishing the gate metal  138  and the gate dielectric  136  of the assembly of  FIG. 38  to remove the gate metal  138  and the gate dielectric  136  over the dielectric material  122  and the dielectric material  156 . Any suitable polishing technique, such as a CMP technique, may be used. 
       FIG. 40  illustrates an assembly subsequent to recessing the gate metal  138  and the gate dielectric  136  (e.g., using one or more etch techniques) to form recesses in the assembly of  FIG. 39 , and then forming gate contacts  140  in the recesses. The gate contacts  140  may include any one or more materials (e.g., an adhesion liner, a barrier liner, one or more fill metals, etc.). 
       FIG. 41  illustrates an assembly subsequent to patterning the dielectric material  134  and the dielectric material  132  of the assembly of  FIG. 40  to form recesses, and then forming S/D contacts  164  in the recesses. The S/D contacts  164  may include any one or more materials (e.g., an adhesion liner, a barrier liner, one or more fill metals, etc.). The assembly of  FIG. 41  may take the form of the IC structure  100  of  FIG. 1 . 
     As noted above, the particular arrangement of the S/D regions  128 / 130  in an IC structure  100  depicted in various ones of the accompanying figures is simply illustrative, and any desired arrangement may be used.  FIG. 42  depicts an IC structure  100  with a different arrangement of S/D regions  128 / 130 , for example. In particular, the IC structure  100  of  FIG. 42  may be fabricated by patterning the hardmasks  126 / 127  so that the boundary between S/D regions  128  and S/D regions  130  is between and parallel to adjacent channel regions  202 . Any other desired arrangement of S/D regions  128 / 130  may be implemented in accordance with the present disclosure. [ 75 ] In some embodiments, the repeated deposition and etching operations around the dielectric material  118  may be performed such that a “cap” of the dielectric material  118  extends over the insulating material  120 .  FIG. 43  is a side, cross-sectional view of such an IC structure  100 , sharing the perspective of the “A” sub-figures herein. The resulting dielectric material  118  may have the same of an upside down “U” and may be nested in the U-shaped dielectric material  112 . Any of the embodiments disclosed herein may include a dielectric material  118  having the structure of  FIG. 43 . 
     As discussed above, during fabrication of transistor devices of the IC structure  100 , the stack  148  of the assembly of  FIG. 2  (and other figures) may be transformed into the insulating material region  158 . Consequently, the distinct material layers of the stack  148  may not be readily identifiable in the device regions  206  of an IC structure  100 . However, in regions of the IC structure  100  in which such transistor devices are not formed, the distinct material layers of the stack  148  (including alternating layers of a first material  150  and a second material  152 , at thicknesses less than a channel thickness  212 ) may be present. For example,  FIG. 44  is a top view of an IC structure  100  (which may be, for example, a portion of a die, as discussed below with reference to  FIG. 48 ) including a guard ring  180  (e.g., a metallic ring used to provide electrical shielding) around an interior area  182 .  FIG. 45  is a side view of the IC structure  100  of  FIG. 44 , depicting that, in some embodiments, the insulating material regions  158  may be disposed under the interior area  182  (e.g., due to the presence of the transistors disclosed herein under the interior area  182 ), while the stack  148  (including alternating layers of a first material  150  and a second material  152 , at thicknesses less than a channel thickness  212 ) may remain under the guard ring  180  (e.g., due to there being no transistor devices present under the guard ring  180 ). In another example,  FIG. 46  is a top view of an IC structure  100  (which may be, for example, a portion of a die, as discussed below with reference to  FIG. 48 ) including a memory array area  186  surrounded by a perimeter area  184  around the memory array area  186 .  FIG. 47  is a side view of the IC structure  100  of  FIG. 46 , depicting that, in some embodiments, the insulating material regions  158  may be disposed under the memory array area  186  (e.g., due to the presence of the transistors disclosed herein under the memory array area  186 , as part of static random access memory (SRAM) cells, or memory cells with other architectures), while the stack  148  (including alternating layers of a first material  150  and a second material  152 , at thicknesses less than a channel thickness  212 ) may remain under the perimeter area  184  (e.g., due to there being no transistor devices present under the perimeter area  184 ). 
     The IC structures  100  disclosed herein may be included in any suitable electronic component.  FIGS. 48-52  illustrate various examples of apparatuses that may include any of the IC structures  100  disclosed herein. 
       FIG. 48  is a top view of a wafer  1500  and dies  1502  that may include one or more IC structures  100  in accordance with any of the embodiments disclosed herein. The wafer  1500  may be composed of semiconductor material and may include one or more dies  1502  having IC structures (e.g., the IC structures  100  disclosed herein) formed on a surface of the wafer  1500 . Each of the dies  1502  may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer  1500  may undergo a singulation process in which the dies  1502  are separated from one another to provide discrete “chips” of the semiconductor product. The die  1502  may include one or more IC structures  100  (e.g., as discussed below with reference to  FIG. 49 ), one or more transistors (e.g., some of the transistors discussed below with reference to  FIG. 49 ) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer  1500  or the die  1502  may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die  1502 . For example, a memory array formed by multiple memory devices may be formed on a same die  1502  as a processing device (e.g., the processing device  1802  of  FIG. 52 ) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. 
       FIG. 49  is a side, cross-sectional view of an IC component  1600  that may include one or more IC structures  100  in accordance with any of the embodiments disclosed herein. One or more of the IC components  1600  may be included in one or more dies  1502  ( FIG. 48 ). The IC component  1600  may be formed on a substrate  1602  (e.g., the wafer  1500  of  FIG. 48 ) and may be included in a die (e.g., the die  1502  of  FIG. 48 ). The substrate  1602  may take the form of any of the embodiments of the base  102  disclosed herein. 
     The IC component  1600  may include one or more device layers  1604  disposed on the substrate  1602 . The device layer  1604  may include features of one or more IC structures  100 , other transistors, diodes, or other devices formed on the substrate  1602 . The device layer  1604  may include, for example, source and/or drain (S/D) regions, gates to control current flow between the S/D regions, S/D contacts to route electrical signals to/from the S/D regions, and gate contacts to route electrical signals to/from the S/D regions (e.g., in accordance with any of the embodiments discussed above with reference to the IC structures  100 ). The transistors that may be included in a device layer  1604  are not limited to any particular type or configuration, and may include any one or more of, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), or high-electron-mobility transistors (HEMT). Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors (e.g., as discussed above with reference to the IC structures  100 ). 
     Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the IC structures  100 ) of the device layer  1604  through one or more interconnect layers disposed on the device layer  1604  (illustrated in  FIG. 49  as interconnect layers  1606 - 1610 ). For example, electrically conductive features of the device layer  1604  (e.g., the gate contacts and the S/D contacts) may be electrically coupled with the interconnect structures  1628  of the interconnect layers  1606 - 1610 . The one or more interconnect layers  1606 - 1610  may form a metallization stack (also referred to as an “ILD stack”)  1619  of the IC component  1600 . Although  FIG. 49  depicts an ILD stack  1619  at only one face of the device layer  1604 , in other embodiments, an IC component  1600  may include two ILD stacks  1619  such that the device layer  1604  is between the two ILD stacks  1619 . 
     The interconnect structures  1628  may be arranged within the interconnect layers  1606 - 1610  to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures  1628  depicted in  FIG. 49 ). Although a particular number of interconnect layers  1606 - 1610  is depicted in  FIG. 49 , embodiments of the present disclosure include IC components having more or fewer interconnect layers than depicted. 
     In some embodiments, the interconnect structures  1628  may include lines  1628   a  and/or vias  1628   b  filled with an electrically conductive material such as a metal. The lines  1628   a  may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate  1602  upon which the device layer  1604  is formed. For example, the lines  1628   a  may route electrical signals in a direction in and out of the page from the perspective of  FIG. 49 . The vias  1628   b  may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate  1602  upon which the device layer  1604  is formed. In some embodiments, the vias  1628   b  may electrically couple lines  1628   a  of different interconnect layers  1606 - 1610  together. 
     The interconnect layers  1606 - 1610  may include a dielectric material  1626  disposed between the interconnect structures  1628 , as shown in  FIG. 49 . In some embodiments, the dielectric material  1626  disposed between the interconnect structures  1628  in different ones of the interconnect layers  1606 - 1610  may have different compositions; in other embodiments, the composition of the dielectric material  1626  between different interconnect layers  1606 - 1610  may be the same. 
     A first interconnect layer  1606  may be formed above the device layer  1604 . In some embodiments, the first interconnect layer  1606  may include lines  1628   a  and/or vias  1628   b,  as shown. The lines  1628   a  of the first interconnect layer  1606  may be coupled with contacts (e.g., the S/D contacts or gate contacts) of the device layer  1604 . 
     A second interconnect layer  1608  may be formed above the first interconnect layer  1606 . In some embodiments, the second interconnect layer  1608  may include vias  1628   b  to couple the lines  1628   a  of the second interconnect layer  1608  with the lines  1628   a  of the first interconnect layer  1606 . Although the lines  1628   a  and the vias  1628   b  are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer  1608 ) for the sake of clarity, the lines  1628   a  and the vias  1628   b  may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments. 
     A third interconnect layer  1610  (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer  1608  according to similar techniques and configurations described in connection with the second interconnect layer  1608  or the first interconnect layer  1606 . In some embodiments, the interconnect layers that are “higher up” in the metallization stack  1619  in the IC component  1600  (i.e., farther away from the device layer  1604 ) may be thicker. 
     The IC component  1600  may include a solder resist material  1634  (e.g., polyimide or similar material) and one or more conductive contacts  1636  formed on the interconnect layers  1606 - 1610 . In  FIG. 49 , the conductive contacts  1636  are illustrated as taking the form of bond pads. The conductive contacts  1636  may be electrically coupled with the interconnect structures  1628  and configured to route the electrical signals of device layer  1604  to other external devices. For example, solder bonds may be formed on the one or more conductive contacts  1636  to mechanically and/or electrically couple a chip including the IC component  1600  with another component (e.g., a circuit board). The IC component  1600  may include additional or alternate structures to route the electrical signals from the interconnect layers  1606 - 1610 ; for example, the conductive contacts  1636  may include other analogous features (e.g., posts) that route the electrical signals to external components. In embodiments in which the IC component  1600  includes an ILD stack  1619  at each opposing face of the device layer  1604 , the IC component  1600  may include conductive contacts  1636  on each of the ILD stacks  1619  (allowing interconnections to the IC component  1600  to be made on two opposing faces of the IC component  1600 ). 
       FIG. 50  is a side, cross-sectional view of an example IC package  1650  that may include one or more IC structures  100  in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package  1650  may be a system-in-package (SiP). 
     The package substrate  1652  may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed of different materials, etc.), and may have conductive pathways extending through the dielectric material between the face  1672  and the face  1674 , or between different locations on the face  1672 , and/or between different locations on the face  1674 . These conductive pathways may take the form of any of the interconnects  1628  discussed above with reference to  FIG. 49 . 
     The package substrate  1652  may include conductive contacts  1663  that are coupled to conductive pathways (not shown) through the package substrate  1652 , allowing circuitry within the dies  1656  and/or the interposer  1657  to electrically couple to various ones of the conductive contacts  1664 . 
     The IC package  1650  may include an interposer  1657  coupled to the package substrate  1652  via conductive contacts  1661  of the interposer  1657 , first-level interconnects  1665 , and the conductive contacts  1663  of the package substrate  1652 . The first-level interconnects  1665  illustrated in  FIG. 50  are solder bumps, but any suitable first-level interconnects  1665  may be used. In some embodiments, no interposer  1657  may be included in the IC package  1650 ; instead, the dies  1656  may be coupled directly to the conductive contacts  1663  at the face  1672  by first-level interconnects  1665 . More generally, one or more dies  1656  may be coupled to the package substrate  1652  via any suitable structure (e.g., (e.g., a silicon bridge, an organic bridge, one or more waveguides, one or more interposers, wirebonds, etc.). 
     The IC package  1650  may include one or more dies  1656  coupled to the interposer  1657  via conductive contacts  1654  of the dies  1656 , first-level interconnects  1658 , and conductive contacts  1660  of the interposer  1657 . The conductive contacts  1660  may be coupled to conductive pathways (not shown) through the interposer  1657 , allowing circuitry within the dies  1656  to electrically couple to various ones of the conductive contacts  1661  (or to other devices included in the interposer  1657 , not shown). The first-level interconnects  1658  illustrated in  FIG. 50  are solder bumps, but any suitable first-level interconnects  1658  may be used. As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket). 
     In some embodiments, an underfill material  1666  may be disposed between the package substrate  1652  and the interposer  1657  around the first-level interconnects  1665 , and a mold compound  1668  may be disposed around the dies  1656  and the interposer  1657  and in contact with the package substrate  1652 . In some embodiments, the underfill material  1666  may be the same as the mold compound  1668 . Example materials that may be used for the underfill material  1666  and the mold compound  1668  are epoxy mold materials, as suitable. Second-level interconnects  1670  may be coupled to the conductive contacts  1664 . The second-level interconnects  1670  illustrated in  FIG. 50  are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects  16770  may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects  1670  may be used to couple the IC package  1650  to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to  FIG. 51 . 
     The dies  1656  may take the form of any of the embodiments of the die  1502  discussed herein (e.g., may include any of the embodiments of the IC component  1600 ). In embodiments in which the IC package  1650  includes multiple dies  1656 , the IC package  1650  may be referred to as a multi-chip package (MCP). The dies  1656  may include circuitry to perform any desired functionality. For example, or more of the dies  1656  may be logic dies (e.g., silicon-based dies), and one or more of the dies  1656  may be memory dies (e.g., high bandwidth memory). In some embodiments, the die  1656  may include one or more IC structures  100  (e.g., as discussed above with reference to  FIG. 48  and  FIG. 49 ). 
     Although the IC package  1650  illustrated in  FIG. 50  is a flip chip package, other package architectures may be used. For example, the IC package  1650  may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package  1650  may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although two dies  1656  are illustrated in the IC package  1650  of  FIG. 50 , an IC package  1650  may include any desired number of dies  1656 . An IC package  1650  may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face  1672  or the second face  1674  of the package substrate  1652 , or on either face of the interposer  1657 . More generally, an IC package  1650  may include any other active or passive components known in the art. 
       FIG. 51  is a side, cross-sectional view of an IC component assembly  1700  that may include one or more IC packages or other electronic components (e.g., a die) including one or more IC structures  100  in accordance with any of the embodiments disclosed herein. The IC component assembly  1700  includes a number of components disposed on a circuit board  1702  (which may be, e.g., a motherboard). The IC component assembly  1700  includes components disposed on a first face  1740  of the circuit board  1702  and an opposing second face  1742  of the circuit board  1702 ; generally, components may be disposed on one or both faces  1740  and  1742 . Any of the IC packages discussed below with reference to the IC component assembly  1700  may take the form of any of the embodiments of the IC package  1650  discussed above with reference to  FIG. 50  (e.g., may include one or more IC structures  100  in a die). 
     In some embodiments, the circuit board  1702  may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board  1702 . In other embodiments, the circuit board  1702  may be a non-PCB substrate. 
     The IC component assembly  1700  illustrated in  FIG. 51  includes a package-on-interposer structure  1736  coupled to the first face  1740  of the circuit board  1702  by coupling components  1716 . The coupling components  1716  may electrically and mechanically couple the package-on-interposer structure  1736  to the circuit board  1702 , and may include solder balls (as shown in  FIG. 51 ), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. 
     The package-on-interposer structure  1736  may include an IC package  1720  coupled to a package interposer  1704  by coupling components  1718 . The coupling components  1718  may take any suitable form for the application, such as the forms discussed above with reference to the coupling components  1716 . Although a single IC package  1720  is shown in  FIG. 51 , multiple IC packages may be coupled to the package interposer  1704 ; indeed, additional interposers may be coupled to the package interposer  1704 . The package interposer  1704  may provide an intervening substrate used to bridge the circuit board  1702  and the IC package  1720 . The IC package  1720  may be or include, for example, a die (the die  1502  of  FIG. 48 ), an IC component (e.g., the IC component  1600  of  FIG. 49 ), or any other suitable component. Generally, the package interposer  1704  may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the package interposer  1704  may couple the IC package  1720  (e.g., a die) to a set of BGA conductive contacts of the coupling components  1716  for coupling to the circuit board  1702 . In the embodiment illustrated in  FIG. 51 , the IC package  1720  and the circuit board  1702  are attached to opposing sides of the package interposer  1704 ; in other embodiments, the IC package  1720  and the circuit board  1702  may be attached to a same side of the package interposer  1704 . In some embodiments, three or more components may be interconnected by way of the package interposer  1704 . 
     In some embodiments, the package interposer  1704  may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer  1704  may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer  1704  may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The package interposer  1704  may include metal lines  1710  and vias  1708 , including but not limited to through-silicon vias (TSVs)  1706 . The package interposer  1704  may further include embedded devices  1714 , including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer  1704 . The package-on-interposer structure  1736  may take the form of any of the package-on-interposer structures known in the art. 
     The IC component assembly  1700  may include an IC package  1724  coupled to the first face  1740  of the circuit board  1702  by coupling components  1722 . The coupling components  1722  may take the form of any of the embodiments discussed above with reference to the coupling components  1716 , and the IC package  1724  may take the form of any of the embodiments discussed above with reference to the IC package  1720 . 
     The IC component assembly  1700  illustrated in  FIG. 51  includes a package-on-package structure  1734  coupled to the second face  1742  of the circuit board  1702  by coupling components  1728 . The package-on-package structure  1734  may include an IC package  1726  and an IC package  1732  coupled together by coupling components  1730  such that the IC package  1726  is disposed between the circuit board  1702  and the IC package  1732 . The coupling components  1728  and  1730  may take the form of any of the embodiments of the coupling components  1716  discussed above, and the IC packages  1726  and  1732  may take the form of any of the embodiments of the IC package  1720  discussed above. The package-on-package structure  1734  may be configured in accordance with any of the package-on-package structures known in the art. 
       FIG. 52  is a block diagram of an example electrical device  1800  that may include one or more IC structures  100  in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device  1800  may include one or more of the IC component assemblies  1700 , IC packages  1650 , IC components  1600 , or dies  1502  disclosed herein. A number of components are illustrated in  FIG. 52  as included in the electrical device  1800 , but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device  1800  may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. 
     Additionally, in various embodiments, the electrical device  1800  may not include one or more of the components illustrated in  FIG. 52 , but the electrical device  1800  may include interface circuitry for coupling to the one or more components. For example, the electrical device  1800  may not include a display device  1806 , but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device  1806  may be coupled. In another set of examples, the electrical device  1800  may not include an audio input device  1824  or an audio output device  1808 , but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device  1824  or audio output device  1808  may be coupled. 
     The electrical device  1800  may include a processing device  1802  (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device  1802  may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device  1800  may include a memory  1804 , which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory  1804  may include memory that shares a die with the processing device  1802 . This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM). 
     In some embodiments, the electrical device  1800  may include a communication chip  1812  (e.g., one or more communication chips). For example, the communication chip  1812  may be configured for managing wireless communications for the transfer of data to and from the electrical device  1800 . The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. 
     The communication chip  1812  may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP 2 ”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip  1812  may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip  1812  may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip  1812  may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip  1812  may operate in accordance with other wireless protocols in other embodiments. The electrical device  1800  may include an antenna  1822  to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). 
     In some embodiments, the communication chip  1812  may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip  1812  may include multiple communication chips. For instance, a first communication chip  1812  may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip  1812  may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip  1812  may be dedicated to wireless communications, and a second communication chip  1812  may be dedicated to wired communications. 
     The electrical device  1800  may include battery/power circuitry  1814 . The battery/power circuitry  1814  may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device  1800  to an energy source separate from the electrical device  1800  (e.g., AC line power). 
     The electrical device  1800  may include a display device  1806  (or corresponding interface circuitry, as discussed above). The display device  1806  may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display. 
     The electrical device  1800  may include an audio output device  1808  (or corresponding interface circuitry, as discussed above). The audio output device  1808  may include any device that generates an audible indicator, such as speakers, headsets, or earbuds. 
     The electrical device  1800  may include an audio input device  1824  (or corresponding interface circuitry, as discussed above). The audio input device  1824  may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). 
     The electrical device  1800  may include a GPS device  1818  (or corresponding interface circuitry, as discussed above). The GPS device  1818  may be in communication with a satellite-based system and may receive a location of the electrical device  1800 , as known in the art. 
     The electrical device  1800  may include an other output device  1810  (or corresponding interface circuitry, as discussed above). Examples of the other output device  1810  may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. 
     The electrical device  1800  may include an other input device  1820  (or corresponding interface circuitry, as discussed above). Examples of the other input device  1820  may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. 
     The electrical device  1800  may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device  1800  may be any other electronic device that processes data. 
     The following paragraphs provide various examples of the embodiments disclosed herein. 
     Example 1 is an integrated circuit (IC) component, including: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, and the third material includes silicon; and a third region including alternating layers of the second material and the third material, wherein the second region is between the first region and the third region, and individual ones of the layers in the second region have thicknesses that are less than thicknesses of individual ones of the layers in the third region. 
     Example 2 includes the subject matter of Example 1, and further specifies that the second region includes at least two layers of the second material. 
     Example 3 includes the subject matter of Example 1, and further specifies that the second region includes at least three layers of the second material. 
     Example 4 includes the subject matter of any of Examples 1-3, and further specifies that the first region includes crystalline silicon. 
     Example 5 includes the subject matter of any of Examples 1-4, and further specifies that the first region, the second region, and the third region are distributed along an axis that is perpendicular to planes of the layers of second material and third material. 
     Example 6 includes the subject matter of any of Examples 1-5, and further specifies that the third region includes at least three layers of the third material. 
     Example 7 includes the subject matter of any of Examples 1-6, and further specifies that the second region is laterally aligned with a fourth region, and the fourth region includes silicon and oxygen. 
     Example 8 includes the subject matter of Example 7, and further specifies that the first region, the second region, and the third region are under a guard ring of the IC component, and the fourth region is not under the guard ring. 
     Example 9 includes the subject matter of Example 7, and further specifies that the first region, the second region, and the third region are at a periphery of a memory array, and the fourth region is not at the periphery of the memory array. 
     Example 10 includes the subject matter of any of Examples 1-7, and further specifies that the IC component further includes gate-all-around (GAA) transistors in a fourth region, and the layers of the third material in the third region are individually laterally aligned with wire channels in at least some of the GAA transistors in the fourth region. 
     Example 11 includes the subject matter of Example 10, and further specifies that the first region, the second region, and the third region are under a guard ring of the IC component, and the fourth region is not under the guard ring. 
     Example 12 includes the subject matter of Example 10, and further specifies that the first region, the second region, and the third region are at a periphery of a memory array, and the fourth region is not at the periphery of the memory array. 
     Example 13 includes the subject matter of any of Examples 1-7, and further specifies that the first region, the second region, and the third region are under a guard ring of the IC component. 
     Example 14 includes the subject matter of any of Examples 1-7, and further specifies that the first region, the second region, and the third region are at a periphery of a memory array. 
     Example 15 includes the subject matter of any of Examples 1-14, and further specifies that the IC component further includes: an array of channel regions, including a first channel region and an adjacent second channel region, wherein axes of the first channel region and the second channel region are parallel and offset; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region. 
     Example 16 includes the subject matter of Example 15, and further specifies that the insulating material region includes a first insulating material and a second insulating material, wherein the first insulating material has a U-shaped cross-section, and the first insulating material is between the second insulating material and the first source/drain region. 
     Example 17 is an integrated circuit (IC) component, including: a substrate; a first region including alternating layers of a first material and a second material, wherein individual ones of the layers has a thickness that is less than 3 nanometers; and a second region including alternating layers of the first material and the second material, wherein individual ones of the layers has a thickness that is greater than 3 nanometers, and the first region is between the substrate and the second region. 
     Example 18 includes the subject matter of Example 17, and further specifies that the second region includes at least two layers of the second material. 
     Example 19 includes the subject matter of Example 17, and further specifies that the second region includes at least three layers of the second material. 
     Example 20 includes the subject matter of any of Examples 17-19, and further specifies that the substrate includes silicon. 
     Example 21 includes the subject matter of any of Examples 17-20, and further specifies that the second region includes at least three layers of the second material. 
     Example 22 includes the subject matter of any of Examples 17-21, and further specifies that the first material and the second material are semiconductor materials. 
     Example 23 includes the subject matter of any of Examples 17-22, and further specifies that the first material and the second material include silicon. 
     Example 24 includes the subject matter of any of Examples 17-23, and further specifies that the first region is laterally aligned with a third region, and the third region includes a dielectric material. 
     Example 25 includes the subject matter of Example 24, and further specifies that the dielectric material includes oxygen. 
     Example 26 includes the subject matter of any of Examples 24-25, and further specifies that the first region and the second region are under a guard ring of the IC component, and the third region is not under the guard ring. 
     Example 27 includes the subject matter of any of Examples 24-25, and further specifies that the first region and the second region are at a periphery of a memory array, and the third region is not at the periphery of the memory array. 
     Example 28 includes the subject matter of any of Examples 17-23, and further specifies that the IC component further includes gate-all-around (GAA) transistors in a third region, and the layers of the second material in the second region are individually laterally aligned with wire channels in at least some of the GAA transistors in the third region. 
     Example 29 includes the subject matter of Example 28, and further specifies that the first region and the second region are under a guard ring of the IC component, and the third region is not under the guard ring. 
     Example 30 includes the subject matter of Example 28, and further specifies that the first region and the second region are at a periphery of a memory array, and the third region is not at the periphery of the memory array. 
     Example 31 includes the subject matter of any of Examples 17-23, and further specifies that the first region and the second region are under a guard ring of the IC component. 
     Example 32 includes the subject matter of any of Examples 17-23, and further specifies that the first region and the second region are at a periphery of a memory array. 
     Example 33 includes the subject matter of any of Examples 17-32, and further specifies that the IC component further includes: an array of channel regions, including a first channel region and an adjacent second channel region, wherein axes of the first channel region and the second channel region are parallel and offset; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region. 
     Example 34 includes the subject matter of Example 33, and further specifies that the insulating material region includes a first insulating material and a second insulating material, wherein the first insulating material has a U-shaped cross-section, and the first insulating material is between the second insulating material and the first source/drain region. 
     Example 35 includes the subject matter of any of Examples 17-34, and further specifies that the IC component is a die. 
     Example 36 is an electronic assembly, including: the IC component of any of Examples 1-35; and a support electrically coupled to the IC component. 
     Example 37 includes the subject matter of Example 36, and further specifies that the support includes a package substrate. 
     Example 38 includes the subject matter of any of Examples 36-37, and further specifies that the support includes an interposer. 
     Example 39 includes the subject matter of any of Examples 36-37, and further specifies that the support includes a printed circuit board. 
     Example 40 includes the subject matter of any of Examples 36-39, and further includes: a housing around the IC component and the support. 
     Example 41 includes the subject matter of Example 40, and further specifies that the housing is a handheld computing device housing. 
     Example 42 includes the subject matter of Example 40, and further specifies that the housing is a server housing. 
     Example 43 includes the subject matter of any of Examples 40-42, and further includes: a display coupled to the housing. 
     Example 44 includes the subject matter of Example 43, and further specifies that the display is a touchscreen display.