Patent Publication Number: US-9852702-B2

Title: Digital driving circuits, methods and systems for display devices

Description:
This application is a continuation of U.S. patent application Ser. No. 13/755,709, filed Jan. 31, 2013, now U.S. Pat. No. 8,704,818, issued Apr. 22, 2014, which is a continuation of U.S. patent application Ser. No. 13/007,014, filed Jan. 14, 2011, which claims priority to U.S. Provisional Patent Application No. 61/294,977, filed Jan. 14, 2010, all of which are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates generally to display control devices, and more particularly to display control devices that enable/disable display segments according to a voltage applied across such segments. 
     BACKGROUND 
     Display technologies, such as liquid crystal display (LCDs), can activate segments of a display according to signals applied across the segments. Conventionally, technology for driving LCDs directly requires dedicated hardware to generate and sequence specific analog voltage levels in order to properly drive a display. Waveforms are generated using such multiple signal levels to either turn on or off each segment. Typically, such multiple signal levels include a high bias voltage, and multiple other intermediate voltage levels proportional to the high bias voltage. A high bias voltage is typically an analog value that may be varied to increase or decrease a contrast of display segments. The generation of a variable high bias voltage and multiple intermediate voltages can be costly in terms of integrated circuit die area, and in some cases power. 
     A typical LCD display may include multiple “commons”. Each common may be connected to a corresponding set of LCD segments. Commons may be driven to an analog selection voltage in a time division multiplexed fashion such that only one commons is driven to an analog selection voltage at a time. When not driven to a selection voltage, each common may be driven to one of many different analog de-selection voltage levels. 
     While LCDs segments may be activated by applying a voltage bias, in order to avoid damaging such segments, LCD controls signals must have an overall DC bias of zero. 
     For systems having N commons, voltages relative to the high bias value may include 1/(1+√N), 2/(1+√N). Further, to ensure a zero DC bias is maintained across each segment, additional values are needed that may be arrived at by “flipping” the previously voltage levels, which gives: √N/(1+√N) and (√N−1)/(1+√N). As but one example, for a system having eight commons, the different analog voltage levels would be 0%, 28%, 56% and 100%. As noted above, to preserve a DC bias across a segment, you must complement (1−x %) these values, and thus include voltage levels 100%, 72%, 44% and 0%. Hardware to generate these levels can require the generation of the high bias voltage (100%), and the ability to generate the four levels proportional to this high bias level. 
     Such levels can be expressed in terms of a value a as follows: 
     
       
         
           
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     If resistor ladders are employed to voltage divide a high bias voltage, there may be overlap in the resistor ranges (α=1 and α=3) and some values can be reused, but for the most part, there may be little overlap, with each a setting needing its own set of resistors in the divider. Thus, for any system which plans to support many commons, a divider with many resistors must be constructed to generate the voltages. This also requires a complicated analog multiplexer to select the different voltage levels. Once the device is made, there may not exist a way to add more commons since the architecture is fixed. 
     One example of a conventional LCD driving arrangement is shown in  FIGS. 16A and 16B .  FIGS. 16A and 16B  show an arrangement having three commons. 
     Referring to  FIG. 16A  a number of analog waveforms are shown, including a common waveform (COM 0 ), two segment selection waveforms (SEG 0 , SEG 1 ), and waveforms showing a resulting voltage difference between the common levels and segment selection levels (COM 0 −SEG 0 , COM 0 −SEG 1 ). The waveforms show three timeslots t 0 , t 1  and t 2 . Such three time slots may make up a frame. 
     As shown, common signal COM 0  varies between a high analog bias voltage (Van_HI), and two values proportional to this voltage (Van_HI*(⅔), Van_HI*(⅓)), and a low voltage (GND). Signal COM 0  is driven to a high selection level during timeslot t 0 . 
     Segment selection waveform SEG 0  is driven with a selection state with respect to the signal COM 0 . Accordingly, as shown by the hatched portion of waveform COM 0 −SEG 0 , a voltage across a segment may exceed a threshold (Vth, −Vth), resulting in a segment being activated at timeslot t 0 . In timeslots t 1  and t 2 , levels remain below Vth/−Vth, so the segment is not activated. 
     In contrast, segment selection waveform SEG 1  is driven with de-selection state with respect to the signal COM 0 . Accordingly, as shown by waveform COM 0 −SEG 0 , a voltage across a segment never exceeds a threshold (Vth, −Vth), resulting in a segment remaining de-activated. 
     It is understood that  FIGS. 16A and 16B  show a very limited number of commons, and that LCD assemblies may include substantially larger numbers of commons (i.e., twenty or more), in which additional analog levels may be required. 
     Generating such selection and de-selection analog voltage levels can be quite expensive. As noted above, such analog circuits may be implemented with resistors, however such resistors must typically have tight tolerances. This can be costly in device area and/or require special process steps. Further, the analog circuitry require to generate multiple analog voltage levels may also be costly. Conventional analog control circuits for an LCD are shown in  FIGS. 17A and 17B . 
       FIG. 17A  shows a first portion of a conventional system  1700  that generates a high bias voltage v 0  and four proportional intermediate voltages v 1 , v 2 , v 3  and v 4 . System  1700  includes a band gap reference circuit  1702  that provides a temperature independent voltage Vbg to operational amplifier (op amp)  1704 . Op amp  1704  may drive bias transistor P 170 . A drain of transistor P 170  may be fed back to op amp  1704  by an adjustable feedback bias circuit that includes adjustment switches  1706 , and resistances R 1  and R 2 . In response to contrast input values CONTRAST, adjustment switches  1706  may vary resistance values R 1 /R 2  to alter an op amp  1704  driving voltage to generate a desired high bias voltage v 0  (where v 0 =(1+R 1 /R 2 *Vbg)). 
     A high bias voltage v 0  may be provided to a resistance ladder network  1708  that may include high precision resistors for generating a large number of bias voltages to accommodate different display types, as well as varying numbers of commons. In response to bias select values (BIAS SELECT), a selection circuit  1710  may connect four generated analog output voltages from resistance ladder network  1708  as output voltage v 1 , v 2 , v 3  and v 4 . It is understood that selection circuit  1710  is an analog circuit that must be capable of passing the various different analog voltage levels. 
       FIG. 17B  shows a second portion of a conventional system  1700  that outputs one of many different analog voltages as a common signal or segment control signal. The various generated analog voltage v 0 , v 1 , v 2 , v 3 , v 4  and GND may be selectively output from a first analog multiplexer (MUX)  1712  in response to common/segment (COM_SEG) selection values. Values output form first analog MUX  1712  may be selectively output to a buffer circuit  1716  from second analog MUX  1714  in response to display and frame data (DISP_DATA, FRAME).  FIGS. 17A and 17B  show how a conventional approach may require considerable analog circuit resources. 
     It is noted that to accommodate a wide range of LCD voltage levels, a high supply voltage (e.g., Vpwr_Hi in  FIG. 17A ) may be generated by a voltage digital-to-analog converter (VDAC), which may further add to the size and complexity of the system. 
     It is also noted that other conventional approaches may utilize charge pumps in lieu of resistance ladder networks to arrive at various analog bias voltages. Such an approach also consumes considerable die area and power. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block schematic diagram of a display control system according to one embodiment. 
         FIG. 2  is a block schematic diagram of a display control system that applies digital signals to a frequency filter, which may be formed with a display device, according to one embodiment. 
         FIG. 3  is a side cross sectional view showing a portion of a liquid crystal display (LCD) that may be included in embodiments. 
         FIGS. 4A and 4B  are block schematic diagrams of a display control system according to one embodiment. 
         FIGS. 5A and 5B  are timing diagrams showing the operation of a display control system that utilizes digital signals and a filter, according to one embodiment. 
         FIG. 6  is a table showing pulse density stream values that may be included in embodiments. 
         FIG. 7  is a table showing other pulse density stream values that may be included in embodiments. 
         FIGS. 8A and 8B  are block diagrams of a display control system and method that may include programmable digital blocks, according to an embodiment. 
         FIGS. 9A and 9B  are block schematic diagrams of a display control system according to an embodiment. 
         FIG. 10  is a block schematic diagram of a display control system that may rely on signal correlation to activate segments, according to one embodiment. 
         FIG. 11  is a block schematic diagram of a signal generator circuit that may be included in embodiments. 
         FIG. 12  is a timing diagram showing display device control using signal correlation according to an embodiment. 
         FIG. 13  is a timing diagram showing segment selection and de-selection waveforms according to one embodiment. 
         FIG. 14  is a graph showing perceived LCD segment darkness relative to root mean square (RMS) voltage applied across the segment. 
         FIG. 15  is a graph showing a “dead time” effect on LCD segment control voltages according to an embodiment. 
         FIGS. 16A and 16B  are diagrams showing a conventional LCD control approach. 
         FIGS. 17A and 17B  are diagrams showing a conventional LCD control circuits. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments will now be described that show circuits, systems and methods that can control a segmented display, such as a liquid crystal display (LCD), with digital (e.g., binary level) signals, and thus avoid analog circuits like those included in conventional approaches. 
     Some may generate display driver signals that vary between only two levels and are applied to opposing electrodes of a display segment. Correlation of such opposing driver signals may be used to select or de-select the segment based on an average voltage magnitude across the segment over a time period (e.g., root mean square). 
     Other embodiments may provide one or more driving methods in addition to the signal correlation method noted above, and enable switching between such different operating modes. One such alternate mode may include generating display driver signals that vary between only two levels, but may change in pulse density. An inherent features (e.g., capacitance and/or resistance) of a display (e.g., LCD display) may be utilized as all or part of a filter to cause the varying pulse densities to generate different voltage levels at segments of the display. 
     Referring to  FIG. 1 , a system according to one embodiment is shown in a block diagram and designated by the general reference character  100 . A system  100  may include digital signal generator circuit  102 , a selection driver circuit  104 , and a display structure  106 . A digital signal generator circuit  102  may generate a number of signals, each of which varies between two levels. That is, such signals may have binary levels and thus a digital signal generator circuit  102  may be implemented with digital circuits, and hence not include specialized analog circuits, as in the conventional approaches noted above. 
     In the embodiment shown, digital signal generator circuit  102  may generate control signals CTRL- 0  to CTLR-L. Such signals may different pulse densities and/or waveform shapes (e.g., phase differences). Such different control signals may have varying degrees of correlation to one another. In addition, a selection driver circuit  104  may vary the types of control signals generated in response to a MODE signal. 
     A selection driver circuit  104  may selectively connect control signals (CTRL- 0  to -L) to display connection points  108  to generate driver signals. In the very particular embodiment shown, such driver signals include common driver signals (COM 1  to COMN) as well as segment driver signals (SEG 1  to SEGM). It is understood that a selection driver circuit  104  can connect different control signals (CTRL- 0  to -L) to display connection points  108  at different time periods (e.g., timeslots) to generate driver signals (COM 1  to -N, SEG 1  to -M) that are time division multiplexed (TDM). Selection operations of selection driver circuit  104  may be made in response to common control signals (COM_CTRL), display data (DISPLAY_DATA), and MODE data. COM_CTRL signals may control a timing of multiplexing, while DISPLAY_DATA signals may vary according to a desired output of display structure  106 . MODE data may indicate a type of operation. In one very particular embodiment, MODE data may indicate a higher power, higher performance node, as well as a lower power, power performance mode. Selection driver circuit  104  may have different signal sequencing operations depending upon MODE data. 
     It is noted that selection driver circuit  104  may also be a digital circuit, and thus may be implemented with digital logic. This is in sharp contrast to conventional analog circuit approaches that must be capable for passing multiple voltage levels. 
     Display structure  106  may include a display that may be controlled by signals received on display connection points  108 . In one embodiment, a display structure may be an LCD display having a number of segments, each having first and second electrodes. Groups of first electrodes may be commonly driven by different common driver signals (COM 1  to -N), while groups of second electrodes may be commonly driven by different segment driver signals (SEG 1  to -M). 
     Optionally, a system  100  may include an impedance network  110  between connection points  108  and display structure  106 . In some embodiments, an impedance network  110  in combination with inherent impedance values of display structure  106  may form a frequency filter for driver signals (COM 1  to -N, SEG 1  to -M). 
     In this way, a system may include a signal generator that generates multiple waveforms that vary between only two levels that may be selectively output as display driver signals, and vary according to two more different modes of operation. 
     As noted above, display properties, such as a capacitance of a display device may be leveraged to filter variable pulse density signals to generate different signal levels at segments of a display. In a very particular embodiment, capacitive properties of LCD glass in an LCD display may be leveraged to produce a low pass filter. Varying voltage levels can then be generated using a density modulation scheme rather than analog hardware. In some embodiments, display driver signals can be generated with pullup/pulldown mode output drivers with ˜5K ohms of output impedance, (or alternatively a relatively small drive field effect transistor) and a sufficient low pass filter is thus generated on the glass. 
     In a very particular embodiment, a rough number for a capacitance of an LCD pixel may be ˜15 pF/mm 2 . This is about the size of a standard decimal point on a typical LCD display. At such a capacitance, a −3 dB point (e.g., cut off frequency) for an extremely small pixel may be about ˜2 MHz. As noted above, in a typical LCD structure, there are multiple segments connected to a LCD display connection point. Thus, an overall capacitance at an LCD connection point may be much larger than 15 pF, and in some embodiment may be about ˜200 pF. At such a capacitance a −3 dB point may be at about ˜160 KHz. Thus, in an embodiment that may switch a driver signal between five states, a minimum clock speed at which a pulse density stream may be modulated may be about ˜1 MHz. 
     Referring now to  FIG. 2 , one example of a system in one mode of operation according to an embodiment is shown in block diagram and designated by the general reference character  200 . A system  200  may include a pulse density generator  212  that outputs a driver signal COM/SEG to display connection point  208 . Signal COM/SEG may a digital signal that varies between two levels. In very particular embodiments, a pulse density generator  212  may include a signal generator circuit and selection driver circuit like those shown as  102 / 104  in  FIG. 1 . As shown, a system  200  may include an output driver resistance R DRV . 
     A display structure  206  may be connected to display connection point  208  to receive driver signal COM/SEG. Display structure  206  may inherently include a display resistance R DIS  and a display capacitance C DIS . That is, the physical construction of the display structure  206  may create R DIS  and C DIS . In a particular embodiment, resistance R DRV  and R DIS  in combination with capacitance C DIS  may form a low pass filter with respect to a modulating frequency of signal COM/SEG. That is, a modulating frequency may be outside of the pass band of such a low pass filter. Consequently, an output voltage VSEG may vary in level as a pulse density varies. 
     Optionally, a system  200  may include an additional resistance R EXT  and/or additional capacitance C EXT  to arrive at a desired filtering response. 
     The mode of operation shown for system  200  may be a higher power, higher performance mode. 
     In this way, in one mode of operation, a system may drive a display structure with a binary level signal, and utilize the inherent capacitance and resistance of the display structure as a low pass filter that transforms variable pulse density into varying voltage levels. 
     Referring now to  FIG. 3 , a portion of a display structure may be included in the embodiments is shown in a partial side cross sectional view and designated by the general reference character  306 . A display structure  306  may be an LCD device that includes a number of common electrodes (one shown as  314 ) and segment electrodes (one shown as  316 ) separated by an LCD “goo”  318 . A common electrode (e.g.,  314 ) may have a capacitance C DIS   _   COM , while a segment electrode (e.g.,  316 ) may have a capacitance C DIS   _   SEG . Such capacitances may form all or part of a low pass filter as described above. 
     In this way, a system may utilize an LCD as all or part of a low pass filter. 
     Because signals generated to control a display device are digital (e.g., transition between binary levels), hardware to generate such signals may be considerably smaller than that utilized in conventional analog approaches, like those noted above, for any reasonable number of commons (i.e., 32 commons). 
     A more detailed embodiment will now be described with reference to  FIGS. 4A and 4B . 
     Referring now to  FIG. 4A , a signal generator circuit according to an embodiment is shown in a block schematic diagram and designated by the general reference character  402 . In one very particular embodiment, a signal generator circuit  402  may be one implementation of that shown as  102  in  FIG. 1 . In particular, signal generator  402  generate driver signals in a higher-power, higher-performance mode of operation. 
     A signal generator circuit  402  may include a control selection circuit  420  and an intensity control circuit  422 . A control selection circuit  420  may include a level density generator circuit  424 , frame logic circuits  426 , and an inverter  428 . A level density generator  424  may vary a density of a binary (i.e., two-level) signals to arrive at a desired level with respect to a low pass filter. In the embodiment shown, level density generator circuit  424  may generate intermediate signals, one corresponding to a level 1/(1+α) and one corresponding to a level 2/(1+α). Such signals may be output in conjunction with two static values, one corresponding to a FRAME signal, and the FRAME signal as inverted by inverter  428 . 
     Frame logic circuits  426  may invert intermediate signals in response to signal FRAME. Thus, frame logic circuits  426  may output either intermediate signals output from level density generator  424  (1/(1+α) and 2/(1+α)), or their inverses, which may be correspond to levels 1−1/(1+α) and 1−2/(1+α), which are corresponding DC balancing levels. 
     Intensity control circuit  422  may include an intensity density generator  430  and combining logic  432 . An intensity density generator  430  may generate a signal INT having a pulse density that varies in response to a value CONTRAST. In one embodiment, a signal INT is not correlated to signals output from control selection circuit  420 . Accordingly, signal INT may be conceptualized as modulating an intensity of signals output form control selection circuit  420 . Such a feature may provide for adjustable contrast of a display device. 
     In the very particular embodiment shown, signal generator circuit  402  may provide a common “on” control signal (COM_On), a common “off” control signal (COM_Off), a segment “off” control signal (SEG_Off), and a segment “on” control signal (SEG_On). To ensure zero bias DC values can be maintained, control signal COM_On may be a logic high in one frame section, and a logic low another frame section (as modulated by signal INT). Control signal COM_Off may be the 1/(1+α) pulse stream for the one frame section and the inverse pulse stream 1−1/(1+α) in the other frame section (as modulated by signal INT). Similarly, control signal SEG_Off may be the 2/(1+α) pulse stream for the one frame section and the inverse pulse stream 1−2/(1+α) in the other section (as modulated by signal INT). Control signal SEG_On may be a logic low in one frame section, and a logic high in another frame section (as modulated by signal INT). 
     Referring now to  FIG. 4B , a selection driver circuit according to an embodiment is shown in a block schematic diagram and designated by the general reference character  404 . In one very particular embodiment, a selection driver circuit  404  may be one particular example of that shown as  104  in  FIG. 1 . 
     A selection circuit  404  may include signal selection logic  434  and output logic  436 . In the very particular embodiment shown, a selection circuit  404  may provide the flexibility to output a common drive signal or a segment drive signal at a display device connection point  408 . Signal selection logic  434  may select any of the control signal types (COM_On, COM_Off, SEG_Off, SEG_On) in response to signal Common and signal On. The Common signal indicates if a particular signal is a Common drive signal (value 1) or a segment drive signal (value 0). The ‘On’ signal indicates if the segment should be illuminated for a corresponding common-segment signal combination. In  FIG. 4B , output logic may be an OR gate with an output that drives a display connection point  408 . As mentioned before, a driving power of output logic  436  may preferably be relatively weak to provide an output resistance suitable for a low pass filter formed with a display device, such as an LCD. 
     In this way, a binary level, pulse density modulated common drive signal or segment drive signal may be routed to a display connection point. 
     Referring to  FIGS. 5A and 5B , two graphs represent a low pass filtering of a variable pulse density signal according to one embodiment.  FIG. 5A  shows a driver signal (COM) having a variable pulse density according to an embodiment. A signal COM may be generated by time division multiplexing control signals of different pulse densities.  FIG. 5A  shows timeslots t 0 , t 1  and t 2 . Within each timeslot, signal COM varies between only two levels, V DRV   _   HI  and GND. Further, within each timeslot a signal may be driven in a complementary fashion to help ensure a zero DC bias across a driven display segment. 
     Referring to  FIG. 5A , in timeslot t 0 , signal COM may be driven to a highest level, followed by a complementary value, and can be conceptualized as a having a pulse density stream of “1,1,1”. In timeslots t 1  and t 2 , signal COM may be driven to a ⅓ proportional level (i.e., (i.e., 1/(1+α) and α=2), followed by a complementary value, and can have a pulse density stream of “0,1,0” (then 1,0,1). 
       FIG. 5B  shows one particular response of a low pass filter, at least a portion of which is formed by the physical structure of a display device.  FIG. 5B  shows a corresponding segment voltage response VSEG. Waveform VSEG includes timeslots t 0 ′, t 1 ′ and t 2 ′ that represent a response to signal COM timeslots t 0 , t 1  and t 2 , respectively. As shown, in response to the variations in pulse density, a voltage VSEG may vary between a levels VHI, ⅓*VHI, ⅔*VHI and GND. 
     It is understood that according to the number of commons, different pulse densities, and hence different pulse streams may be employed. As noted above, a number of levels may be arrived at by the relationships 1/(1+α) and 2/(1+α), where α=√N, and N=number of commons. 
       FIG. 6  shows one very particular example of density stream that may be generated according to an embodiment when rounding α to whole number values. It is understood that each bit in the given density stream corresponds to a signal level in a corresponding portion of a timeslot. 
       FIG. 7  shows one very particular example of density streams that may be generated according to an embodiment when rounding α to a nearest ½ value. Of course, various other density streams may be arrived at according to a pulse density modulation stream, allowable frequency range, and desired precision, to name but a few of many factors. 
     It is noted that the density streams may be modulated to generate highest frequencies when possible. Such an approach may enhance the performance of a system by moving the frequencies well into the stop band of filter created by all or a portion of a display device. 
     In this way, pulse density bit streams may be generated to modulate a binary level signal to generate a desired signal level at a filtered output. 
     Referring now to  FIGS. 8A and 8B , a method and system according to still further embodiments are shown in series a block diagrams.  FIGS. 8A and 8B  show system for generating LCD driver signals that may be implemented with programmable digital logic blocks. 
       FIG. 8A  shows a system  800  that includes a number of digital programmable logic blocks  834 . Such programmable logic blocks  834  may be programmed to provide particular digital logic functions and have particular digital signal interconnections in response to configuration data CFG. 
       FIG. 8B  show a system  800  after configuration data has configured the digital programmable logic blocks into a signal generator circuit  802  and a selection driver circuit  804 - 0 / 1 . In a very particular embodiment, system  800  may be one very particular implementation of that shown in  FIG. 1 . 
     A signal generator circuit  802  may generate signals having a particular density modulation as noted in embodiments above and equivalents. Such signals may be provided to selection driver circuits  804 - 0 / 1 . 
     In the embodiment of  FIG. 8B , the digital programmable logic blocks have been configured to provide a number of common drive signals (COMs) and segment drive signals (SEGs) to particular display connection points. More particularly, a selection driver circuit may include a common section  804 - 0  that generates common driver signals and segment section  804 - 1  that generates segment driver signals. 
     Common section  804 - 0  may generate common driver signals COMs in response to sequence control signals SEQ that vary between binary levels. In one particular embodiments, sequence control signals may generate common driver signals COMs that have repeating sequences. 
     In contrast, segment section  804 - 1  may generate selection driver signals SEGs in response to both sequence control signals SEQ and display data (DISPLAY_DATA). DISPLAY_DATA data may vary according to a desired display output. Consequently, segment driver signals (SEGs) may also vary in response to display data. 
     In this way, a system may include a common section that generates digital common driver signals having a pulse density that varies according to a sequence, and a segment section that generates digital segment driver signals having a pulse density that varies according to display data. 
     Referring now to  FIGS. 9A and 9B , a system according to another embodiment is shown in series block schematic diagrams and designated by the general reference character  900 . In particular embodiments, system  900  may be a portion of one very particular implementation of that shown in  FIG. 8B . A system  900  may generate driver signals that may be modulated to provide four different voltage levels (LvI 0 , LvI 1 , LvI 2 , LvI 3 ) when filtered by an LCD. 
     Referring to  FIG. 9A , a portion of system  900  is shown to include a signal generator circuit  902 , a common section  904 - 0 , an intensity control circuit  922 , and a state machine circuit  938 . A signal generator circuit  902  may include a pulse width modulation (PWM) circuit  936 - 0  and inverters  928 - 0  and - 1 . Pulse width modulation (PWM) circuit  936 - 0  may generate a binary signal Mod(LvI 2 ) according to a modulation clock (mod_clk) having a pulse density that generates a LvI 2  in a corresponding filter/LCD. Signal MOD(LvI 2 ) may be inverted by inverter  928 - 0  to generate a binary signal Mod(LvI 1 ) that generates a LvI 1  voltage in a corresponding filter/LCD. Signal generator circuit  902  may also provide a static low logic level signal “0”, corresponding to LvI 0 , and may invert such a signal to provide a static high logic level signal “1” that may correspond to LvI 3 . 
     A common section  904 - 0  may include logic for selectively connecting either of signals Mod(LvI 2 ) or LvI 0  as output signals to intensity control circuit  922 . Common section  904  may operate in response to state sequence signals STATE[ 0 ] to [ 3 ] provided state machine circuit  938 . 
     An intensity control circuit  922  may include an intensity PWM circuit  936 - 1  and combining logic  932 . Intensity PWM circuit  936 - 1  may generate a binary signal Mod(Contrast) having a pulse density that may modulate the outputs of common section  904 - 0  in the same manner as described for section  422  of  FIG. 4 . 
     A state machine circuit  938  may generate state sequence signals STATE[ 0 ] to [ 3 ] according to a time division multiplexing signal (clk_tdm). Such sequence signals (STATE[ 0 ] to [ 3 ]) may generate common driver signals COM 1  to COM 4  output signals that are time division multiplexed with frames of three timeslots. Only one common driver signal will be active (at LvI 0 ) in any given timeslot, each being at an inactive modulated state Mod(LvI 2 ) in the remaining timeslots. In the very particular embodiment shown, a state machine circuit  938  may include a look-up table (LUT) that sequences through states in synchronism with clk_tdm. 
     Common driver signals COM 1  to - 4  may be driven on corresponding display connection points  908 - 0 , which may be connected to common inputs of an LCD display. 
     Referring to  FIG. 9B , a second part of system  900  is shown to include a display data section  942 , a segment section  904 - 1 , and combining logic  932 ′. Display data section  942  may include display memories  940 - 0  and - 1 , and display data selection circuits  944 . Display memories ( 940 - 0 / 1 ) may store data values corresponding a desired display response. In the particular embodiment shown, each display memory ( 940 - 0 / 1 ) may provide eight output values (out 0  to out 7 ) at a time. Data selection circuits  944  may selectively output values from display memories ( 940 - 0 / 1 ) in response to state sequence signals (STATE[ 0 ] and [ 1 ]) as display data DISP 1  to DISP 4 . 
     Segment section  904 - 1  may include logic for selectively connecting either of signals Mod(LvI 1 ) or LvI 3  as output signals to combining logic  932 ′ in response to display data DISP 1  to - 4  and state sequence signal STATE[ 2 ]. 
     Combining logic  932 ′ may modulate the outputs of segment section  904 - 1  in the same manner as described for section  422  of  FIG. 4  according to signal Mod(Contrast). 
     Segment driver signals SEG 1  to - 4  may be driven on corresponding display connection points  908 - 1 , which may be connected to common inputs of an LCD display. 
     In the embodiment of  FIGS. 9A and 9B , the system shown was for an N=4 system, which only requires 4 bias levels (LvI 0 =0, LvI 1 =⅓, LvI 2 =⅔ and LvI 3 =1). As noted above, LvI 0  and LvI 3  represent 0 and 1 signal levels, while a ⅓ duty cycle PWM circuit  936 - 0  may generate LvI 1  and (by inverting) Lv 12 . A LUT within state machine circuit  938  may step through eight states necessary to generate a type B (i.e., zero bias in two frames) LCD waveform with 4 commons. 
     In one embodiment,  FIGS. 9A and 9B  represent the hardware to control a 16 segment LCD element. Display memories ( 940 - 0 / 1 ) may be display random access memory (RAM) which store the desired state for each segment of the LCD element. State machine circuit  938  may be used to step through each timeslot (i.e., sub-frame) and the display memories ( 940 - 0 / 1 ) may be accessed to determine which of the 4 bias levels are required in order to generate the desired LCD waveform. In some embodiments, a modulation clock (mod_clk) may have a frequency greater than 1 MHz, preferably greater than 3 MHz. The approach illustrated by  FIGS. 9A and 9B  may be applied to systems having any number of commons, and with a sufficiently fast mod_clk, substantially any known LCD may be useable with such embodiments. 
     Embodiments of the invention may use high frequency digital signals (generated either through delta sigma modulation, pulse width modulation or any other suitable density modulation scheme) and the inherent low pass characteristics of a display, (such as an LCD) to apply a different bias voltage levels to the display without requiring specific analog hardware. The density of a digital signal applied to a display may be varied according to the bias voltage desired, and a state machine can properly sequence the modulated signal in order to influence the LCD. The modulated signal can also be mixed with another uncorrelated signal to adjust the discrimination ratio. 
     Embodiments above may use pulse density modulation in combination with a low pass filter, as noted above, for one mode of operation. Other embodiments may utilize signal correlation to drive an average voltage across a display segment to an active level (e.g., opaque in the case of an LCD). Such a signal correlation approach may be employed individually, or in combination with one or more other modes of operation. As but one example, correlation approaches may be utilized in combination with signal density approaches to provide two different modes of operation. More detailed examples of signal correlation embodiments will now be described. 
     Referring now to  FIG. 10 , a system according to an alternate embodiment is shown in a block schematic diagram and designated by the general reference character  1000 . A system  1000  may show another mode of operation for a system like of of  FIG. 1 , and like sections are referred to by the same reference characters but with the leading digits being “10” instead of “1”. Alternatively,  FIG. 10  may be system that provides one mode of operation 
     Digital signal generator  1002  may generate control signals CTRL- 0  to CTRL-L that vary between two levels, some of which may correlate with one another, others of which may not correlate with one another. When signals correlate with one another, an average voltage difference between such signals, over a predetermined time period, may be large enough to activate a display segment. Conversely, when signals do not correlate with one another, such an average voltage difference may be insufficient to activate a display segment. In very particular examples, segments within display  1006  may be activated when a root mean square voltage (Vrms) exceeds a threshold value (Vrms_LCD_On), while non-correlated signals will not exceed Vrms_LCD_On. Thus, in the embodiment of  FIG. 10 , control signals (CTRL- 0  to -L) may not be pulse density modulated according to a level value, but rather may be waveforms created to correlate or not correlate with one another. 
     A selection driver circuit  1004  may selectively connect control signals (CTRL- 0  to -L) to display connection points  1008  to generate driver signals in the same manner as selection driver circuit  104  of  FIG. 1 . 
     However, unlike  FIG. 1  common driver signals (COM 1  to COMN) may be driven with various waveforms that may or may not correlate with corresponding segment driver signals (SEG 1  to SEGM). Since an LCD segment will be on if the root mean square (RMS) voltage is above some threshold voltage, and off if the RMS voltage is below the threshold voltage, driver signals (COM 1  to COMN, SEG 1  to SEGM) may be generated by multiplexing a waveforms that can selectively activate segments, while keeping other segments off, based on such signals correlating with one another. 
     A system  1000  may also include a dead time control circuit  1052 . A dead time control circuit  1052  may drive all driver signals (COM 1  to COMN, SEG 1  to SEGM) to a high level for a time period d, which may be established by timing circuit  1050 . A dead time “d” may be selected to increase perceived contrast, as will be described in more detail below. 
     One method of generating waveforms and corresponding driver signals according to an embodiment will now be described with reference to  FIGS. 11 and 12 . 
       FIG. 11  shows one particular example of a signal generator circuit  1102 , and may be one particular implementation of that shown as  1002  in  FIG. 10 . Signal generator circuit  1102  generates complementary signals CTRL 0 / 1  that follow a clock signal (CLOCK_IN), and generates complementary harmonic signals (CTRL 2 / 3 ) by frequency dividing signal CLOCK_IN by two and inverting the result. 
     It is understood that  FIG. 11  is provided as but one type of correlation between two signals. Alternate embodiments may include various other types of waveforms to arrive and correlating (i.e., average voltage over time adequate to activate display segment) and non-correlating signals (i.e., average voltage over time not adequate to activate display segment). 
       FIG. 12  shows examples of driver signals that may be generated by multiplexing control signals shown in  FIG. 11 . Thus, driver signal COM 0  may be generated by outputting signal CTRL 2  in timeslots t 0  to t 2 . Signal COM 1  may be generated by outputting signal CTRL 0  in timeslots t 0  and t 2 , and signal CTRL 2  in timeslot t 1 . The remaining signals COM 2 , SEG 0 , SEG 1  are generated in the same general fashion. Further, all signals (COM 0 / 1 / 2 , SEG 0 / 1 ) are driven high in the dead time period after timeslot t 2 . 
       FIG. 12  shows how signals may correlate with one another. In particular, in timeslot to, signals COM 0  and SEG 1  may correlate with one another by a sufficient amount so as to exceed the threshold (Vrms_LCD_On). Thus, display segment(s) connected between such signals would be activated. In timeslot t 1 , signals COM 1  and SEG 1  correlate with one another. In timeslot t 2 , signals COM 2  and SEG 1  correlate with one another. It is noted that signal SEG 0  never has sufficient correlation with any of the common signals (COM 0 / 1 / 2 ) to exceed Vrms_LCD_On. 
     As noted above, in particular embodiments a display (e.g., LCD) segment state may be understood by taking the difference between the common driver signal and the segment driver signal applied to the segment. If the RMS voltage is above the threshold, the segment is on, otherwise the segment is off. The waveforms of  FIG. 13  further illustrate that point. 
       FIG. 13  shows two waveforms which represent a voltage difference across two segments caused by a segment driver signal (SEG) and two different common driver signals (COM 0 , COM 1 ). Waveform SEG−COM 0  which in an “off” segment, while waveform SEG−COM 1  results in an “on” segment. An RMS voltage applied to such segments may be derived as follows. In the case of the “off” segment” 
     
       
         
           
             
               
                 
                   
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     It is noted that a dead time “d” can range from 0 to infinity, and “n” can also range from 1 to infinity. In the case that n=1 and d=0, Vrms(on)=sqrt(1)=1 and Vrms(off)=sqrt(0)=0. If a threshold voltage for a display segment is 0.5, then when n=1 and d=0, the segment will operate as desired (this is basically a static LCD drive). The RMS “on” voltage will be 1 volt, and the RMS “off” voltage will be 0 volts. Thus, such an arrangement may be acceptable when the segment turns “on” above 0.5, and “off” below 0.5 volts. 
     However, actual LCDs may have a less defined “on” and “off” voltage. An “on” and “off” may be defined as voltages that cause the segment to darken to within 90% of its maximum (“on”), and below 10% of the minimum (“off”). To better understand such actual LCD dynamics, an AC signal was applied to a real LCD, and the perceived darkness level was plotted for different RMS voltages applied (normalized to the maximum allowable LCD voltage). Results of such observations are shown in a graph in  FIG. 14 . 
       FIG. 14  shows that in order for the observed LCD display to have crisp “on” and “off” states, it was desirable to have a certain minimum separation between the “on” and “off” voltages. In particular, if the RMS on voltage is above 0.53, a segment has a desirable “on” appearance, and if the RMS voltage is below 0.45, the segment has a desirable “off” appearance. 
     Referring back to the RMS calculations, in the case that n=4 and d=0, Vrms(on) is sqrt((1+3/2)/4)=sqrt(5/8)=˜0.79, and Vrms(off)=sqrt((3/2)/4)=sqrt(3/8)=0.612. In such an arrangement, the LCD will have an undesirable appearance as both voltages exceed the turn-on target RMS voltage of 0.53. 
     To remedy this problem, the inventors noted that a dead time “d” could be adjusted. If d=3, Vrms(on) will become sqrt((5/2)/7)=0.59, and Vrms(off) will be sqrt((3/2)/7)=0.46. This means the “on” segment will be activated, but the “off” segment will be slightly darkened, causing the LCD to look less defined. 
     Increasing d to 4 causes Vrms(on) to be 0.55 and Vrms(off) to be 0.43, which results in a desirable contrast response. It is noted that continued increases to “d” cause the “off” segments to have less contrast, and causes a reduction in the “on” voltage below the ideal point, which can result in the entire display starting to look dim.  FIG. 15  illustrates this relationship. 
     As shown in  FIG. 15 , setting a dead time to four (d=4) can achieve a best response for the system. It is understood that different LCDs can have different responses. Further, arriving at a best response may also differ based on a number of commons and type of signal correlation used. Accordingly, the particular embodiment shown in  FIGS. 13 to 15  can be considered a guide to arrive at settings that would be applicable to other systems by one skilled in the art. 
     Referring still to  FIGS. 13 to 15 , another metric for an LCD display is a contrast ratio. A contrast ratio may be a ratio of Vrms(on) to Vrms(off), and may help in determining how much room there is between an “on” segment and an “off” segment. When there is more distance between the two, it can be easier to clearly define an “on” segment and an “off” segment without having to compromise on the clarity of the “on” segments. 
     For the particular drive scheme show previously, a contrast ratio can be given as: 
     
       
         
           
             
               
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     It is noted that the contrast ratio does not depend on dead time (d). For n=1, the contrast ratio is ∞, but for n=2, 
                 3   1       =   1.73         
and n=4,
 
                 5   3       =     1.29   .           
As n increases, the voltage “distance” between on and off states will become smaller and smaller, as shown by the contrast ratio getting smaller. The smaller the contrast ratio, the more a system will have to depend upon the LCD physical features (e.g., the LCD goo properties) to have a sharply defined “off” to “on” transition, since the difference between the generated “on” and “off” voltages will be small. If the example with n=4 is revisited, we see that in all cases, the ratio of the on and off voltages was 1.29 (ignoring rounding error) (0.79/0.612=1.29, 0.59/0.46=1.29, 0.55/0.43=1.29).
 
     Referring to  FIG. 14 , it is shown that a contrast ratio of at least 1.25 (0.54/0.43) is desirable for a clear definition of the on and off segments. The above proposed method, arriving at a contrast ratio of 1.29, meets such a response. 
     In the embodiments above, the hardware utilized to implement display driver signals may be digital circuits (i.e., circuits that operate at binary levels). The hardware necessary to implement an analog LCD driver, such as the conventional approaches above, can be large in comparison to the proposed digital implementations. Accordingly, significant savings in silicon die area can be obtained by replacing a traditional analog LCD drive implementation with a digital topology like those of the embodiments, or equivalents. 
     The embodiments, and equivalents, have the ability to be scaled to any number of commons and segments with minimal hardware requirements. 
     Embodiments of the invention may also provide savings in power consumption as compared to conventional approaches. By utilizing digital (i.e., binary level) circuits, a corresponding display can be driven by a system “waking” from a low power sleep mode, driving display pins between logic high and low levels, then going back to the low power sleep mode. This can provide for a faster transition between sleep and wake states as compared to conventional analog circuit approaches, as time is not needed for analog DAC circuits to be stabilized since the driven display control signal levels are at logic levels. In the case of an LCD system, a drive mode can be left alone and it may not be necessary to rely on the LCD glass to store charge during a sleep interval. 
     It should be appreciated that reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, it is emphasized and should be appreciated that two or more references to “an embodiment” or “one embodiment” or “an alternative embodiment” in various portions of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined as suitable in one or more embodiments of the invention. 
     Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claims require more features than are expressly recited in each claim. Rather, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.