Patent Publication Number: US-9433099-B2

Title: Package carrier

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 102135527, filed on Oct. 1, 2013. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a carrier and more particularly, to a package carrier. 
     2. Description of Related Art 
     A chip package provides a chip with proper signal and heat transmission paths and protects the chip structure. A leadframe often serves as a carrier of the chip when a conventional wire bonding technique is applied. As contact density in the chip gradually increases, the leadframe is no longer able to further improve the contact density and thus can be replaced by a package carrier which can achieve favorable contact density. Besides, the chip is packaged onto the package carrier by conductive media, such as metal conductive wires or bumps. 
     Generally, in order to form the package carrier, a core dielectric layer often serves as a core material, and patterned circuit layers and patterned dielectric layers are alternately stacked on the core dielectric layer by performing a fully additive process, a semi-additive process, a subtractive process, or any other process. Consequently, the core dielectric layer accounts for a great proportion of the whole thickness of the package carrier. If the thickness of the core dielectric layer cannot be effectively reduced, it will be very difficult to reduce the thickness of the chip package. 
     SUMMARY OF THE INVENTION 
     The invention is directed to a package carrier adapted to carry at least one chip. 
     The package carrier of the invention includes a removable supporting plate and a circuit board. The removable supporting plate includes a dielectric layer, a copper foil layer and a releasing layer. The dielectric layer is disposed between the copper foil layer and the releasing layer. The circuit board is disposed on the removable supporting plate and directly contacts the releasing layer, and a thickness of the circuit board is between 30 μm to 100 μm. 
     In an embodiment of the invention, the circuit board includes a circuit layer, a first solder mask layer and a second solder mask layer. The circuit layer has an upper surface and a lower surface opposite to each other. The first solder mask layer is disposed on the upper surface of the circuit layer and exposes a portion of the upper surface. The second solder mask layer is disposed on the lower surface of the circuit layer and exposes a portion of the lower surface. The releasing layer and the second solder mask layer are conformally disposed, and the lower surface exposed by the second solder mask layer directly contacts the releasing layer. 
     In an embodiment of the invention, the circuit board includes a first patterned circuit layer, a second patterned circuit layer, an insulation layer, at least one conductive through hole, a first solder mask layer and a second solder mask layer. The insulation layer is disposed between the first patterned circuit layer and the second patterned circuit layer, and has a first surface and a second surface opposite to each other. The conductive through hole passes through the first surface and the second surface of the insulation layer, and is electrically connected to the first patterned circuit layer and the second patterned circuit layer. The first solder mask layer is disposed on the first surface of the insulation layer and covers a portion of the first patterned circuit layer. The second solder mask layer is disposed on the second surface of the insulation layer and covers a portion of the second patterned circuit layer. The releasing layer and the second solder mask layer are conformally disposed, and the second patterned circuit layer exposed by the second solder mask layer directly contacts the releasing layer. 
     In an embodiment of the invention, a thickness of the dielectric layer of the removable supporting plate is greater than a thickness of the insulation layer. 
     In an embodiment of the invention, the thickness of the insulation layer is less than or equal to 30 μm. 
     In an embodiment of the invention, the first patterned circuit layer is embedded in the insulation layer, and a top surface of the first patterned circuit layer is aligned to a first surface. 
     In an embodiment of the invention, the first patterned circuit layer is disposed on the first surface of the insulation layer. 
     In an embodiment of the invention, the second patterned circuit layer is embedded in the insulation layer, and a bottom surface of the second patterned circuit layer is aligned to the second surface. 
     In an embodiment of the invention, the second patterned circuit layer is disposed on the second surface of the insulation layer. 
     In an embodiment of the invention, a material of the releasing layer includes a metal material or a resin material. 
     Based on above, in the package carrier of the invention, the removable supporting plate is served as a supporting structure for supporting the circuit board, and the removable supporting plate may be removed after a chip is disposed on the circuit board of the package carrier and the packaging is completed. Therefore, in comparison with a package structure having a core dielectric layer in conventional art, a package structure composed of the package carrier of the invention can have a relatively small thickness. 
     Several exemplary embodiments accompanied with figures are described in detail below to further describe the invention in details. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the invention. 
         FIG. 1  is a schematic cross-sectional view of a package carrier according to an embodiment of the invention. 
         FIG. 1 ′ is a schematic cross-sectional view of a package carrier according to another embodiment of the invention. 
         FIG. 2  is a schematic cross-sectional view of a package carrier according to another embodiment of the invention. 
         FIG. 3  is a schematic cross-sectional view of a package carrier according to another embodiment of the invention. 
         FIG. 4  is a schematic cross-sectional view of the package carrier depicted in  FIG. 2  which carries a chip. 
         FIG. 5  is a schematic cross-sectional view of a package structure composed of the package carrier depicted in  FIG. 2 . 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
       FIG. 1  is a schematic cross-sectional view of a package carrier according to an embodiment of the invention. Referring to  FIG. 1 , in the present embodiment, a package carrier  100   a  includes a removable supporting plate  110  and a circuit board  120   a . The removable supporting plate  110  includes a dielectric layer  112 , a copper foil layer  114  and a releasing layer  116 . The dielectric layer  112  is disposed between the copper foil layer  114  and the releasing layer  116 . The circuit board  120   a  is disposed on the removable supporting plate  110  and directly contacts the releasing layer  116 . A thickness of the circuit board  120   a  is between 30 μm to 100 μm. 
     More specifically, in the present embodiment, the circuit board  120   a  includes a circuit layer  122   a , a first solder mask layer  125   a  and a second solder mask layer  127   a . Namely, the circuit board  120   a  of the present embodiment is particularly a single-layer circuit board, and the thickness of the circuit board  122   a  may be less than or equal to 30 μm. The circuit layer  122   a  has an upper surface  121   a  and a lower surface  123   a  opposite to each other. The first solder mask layer  125   a  is disposed on the upper surface  121   a  of the circuit layer  122   a  and exposes a portion of the upper surface  121   a . The second solder mask layer  127   a  is disposed on the lower surface  123   a  of the circuit layer  122   a  and exposes a portion of the lower surface  123   a . The releasing layer  116  and the second solder mask layer  127   a  are conformally disposed, and the lower surface  123   a  exposed by the second solder mask layer  127   a  directly contacts the releasing layer  116 . Herein, a material of the releasing layer  116  includes a metal material or a resin material. 
     Since the package carrier  100   a  of the present embodiment includes the removable supporting plate  110  which may serve as a supporting structure for supporting the circuit board  120   a  having the thickness being relatively thinner (e.g., the single-layer circuit board as depicted in  FIG. 1 ). Subsequently, after a chip (not illustrated) is disposed on the circuit board  120   a  of the package carrier  100   a  and a packaging thereof is completed, the removable supporting plate  110  may then be removed. In other words, before packaging the chip, the removable supporting plate  110  may serve as the supporting structure; and after packaging the chip, the removable supporting plate  110  may be removed to reduce a whole thickness of a package structure. Therefore, in comparison with a package structure having a core dielectric layer in conventional art, a package structure composed of the package carrier  100   a  of the present embodiment can have a relatively small thickness. 
     It should be noted that, in another embodiment, referring to  FIG. 1 ′, a circuit board  120   a ′ in a package carrier  100   a ′ may include a solder mask layer  127 ′ at a single side only, and a circuit board  122   a ′ may be disposed on the solder mask layer  127 ′. In this case, a whole thickness T″″ of the circuit board  120   a ′ is constituted by a thickness of the circuit layer  122   a ′ of single-layer plus a thickness of the solder mask layer  127 ′ of single-layer. 
     It should be noted that the reference numerals and a part of the contents in the previous embodiment are used in the following embodiments, in which identical reference numerals indicate identical or similar components, and repeated description of the same technical contents is omitted. For a detailed description of the omitted parts, reference can be found in the previous embodiment, and no repeated description is contained in the following embodiments. 
       FIG. 2  is a schematic cross-sectional view of a package carrier according to another embodiment of the invention. Referring to  FIG. 2 , a package carrier  100   b  of the present embodiment is similar to the package carrier  100   a  of  FIG. 1 , a difference of the two is that, a circuit board  120   b  of the present embodiment is particularly a double-layer circuit board. More specifically, in the present embodiment, the circuit board  120   b  includes a first patterned circuit layer  122   b , a second patterned circuit layer  124   b , an insulation layer  126   b , at least one conductive through hole  128   b , a first solder mask layer  125   b  and a second solder mask layer  127   b . The insulation layer  126   b  is disposed between the first patterned circuit layer  122   b  and the second patterned circuit layer  124   b , and includes a first surface  121   b  and a second surface  123   b  opposite to each other. As shown in  FIG. 2 , in the present embodiment, the first patterned circuit layer  122   b  is disposed on the first surface  121   b  of the insulation layer  126   b , and the second patterned circuit layer  124   b  is disposed on the second surface  123   b  of the insulation layer  126   b . Herein, a thickness T 1  of the dielectric layer  112  of the removable supporting plate  110  is greater than a thickness T 2  of the insulation layer  126   b . More preferably, the thickness of the insulation layer  126   b  of the circuit board  120   b  is less than or equal to 30 μm. 
     Furthermore, the conductive through hole  128   b  of the circuit board  120   b  passes through the first surface  121   b  and the second surface  123   b  of the insulation layer  126   b , and is electrically connected to the first patterned circuit layer  122   b  and the second patterned circuit layer  124   b . The first solder mask layer  125   b  is disposed on the first surface  121   b  of the insulation layer  126   b  and covers a portion of the first patterned circuit layer  122   b . The second solder mask layer  127   b  is disposed on the second surface  123   b  of the insulation layer  126   b  and covers a portion of the second patterned circuit layer  124   b . The releasing layer  116  and the second solder mask layer  127   b  are conformally disposed, and the second patterned circuit layer  124   b  exposed by the second solder mask layer  127   b  directly contacts the releasing layer  116 . More preferably, a thickness T′ of the circuit board  120   b  is between 30 μm and 100 μm. 
       FIG. 3  is a schematic cross-sectional view of a package carrier according to another embodiment of the invention. Referring to  FIG. 3 , a package carrier  100   c  of the present embodiment is similar to the package carrier  100   b  of  FIG. 2 , a difference of the two is that, a circuit board  120   c  of the present embodiment is particularly a double-layer circuit board and the circuit layer belongs to an embedded circuit. More specifically, in the present embodiment, a first patterned circuit layer  122   c  of the circuit board  120   c  is embedded in an insulation layer  126   c , and a top surface S 1  of the first patterned circuit layer  122   c  is aligned to a first surface  121   c . A second patterned circuit layer  124   c  of the circuit board  120   c  is embedded in the insulation layer  126   c , and a bottom surface S 2  of the second patterned circuit layer  124   c  is aligned to a second surface  123   c . A conductive through hole  128   c  is electrically connected to the first patterned circuit layer  122   c  and the second patterned circuit layer  124   c . A first solder mask layer  125   c  and a second solder mask layer  127   c  are disposed on the first surface  121   c  and the second surface  123   c  respectively, and expose a portion of the first patterned circuit layer  122   c  and a portion of the second patterned circuit layer  124   c  respectively. More preferably, a thickness T″ of the circuit board  120   c  is between 30 μm and 100 μm. 
     It should be noted that, the circuit boards ( 120   a ,  120   a ′,  120   b  and  120   c ) of the package carriers ( 100   a ,  100   a ′,  100   b ,  100   c ) in the embodiments are at most two-layer circuit layer, and the whole thicknesses (T, T′, T″ and T′″) of the circuit boards ( 120   a ,  120   a ′,  120   b  and  120   c ) of the package carriers ( 100   a ,  100   a ′,  100   b ,  100   c ) are all between 30 μm to 100 μm. In the circuit boards ( 120   a ,  120   a ′,  120   b  and  120   c ) within said thickness range, a supporting strength thereof is insufficient due to the thicknesses being relatively thinner. Therefore, the removable supporting plate  110  may serve as a supporting structure for reinforcing overall structural strengths of the package carriers ( 100   a ,  100   a ′,  100   b ,  100   c ). When the thickness range exceeds greater than 100 μm, or the circuit board has more than two-layer circuit layer, which indicates that a strength of the circuit board is sufficient to support the chip being disposed thereon in subsequent process, thus it is not adapted to the invention. 
       FIG. 4  is a schematic cross-sectional view of the package carrier depicted in  FIG. 2  which carries a chip. Referring to  FIG. 4 , when a chip  210  is disposed on a circuit board  100   d , the chip  210  may be electrically connected the first patterned circuit layer  122   b  (which can be deemed as pads) exposed by the first solder mask layer  125   b  through a plurality of wires  220 . In order to make the first patterned circuit layer  122   b  exposed by the first solder mask layer  125   b  to provide a more preferable contact reliability, the package carrier  100   d  of the present embodiment further includes a surface treatment layer  130  as compared to the package carrier  100   b  depicted in  FIG. 2 . The surface treatment layer  130  is disposed on the first patterned circuit layer  122   b  exposed by the first solder mask layer  125   b , so as prevent the pads from being oxidized or contaminated by the outside world. Thereafter, the chip  210 , the wires  220  and the package carrier  100   d  may be packaged through an encapsulation adhesive  230 . 
     Since the package carrier  100   d  of the present embodiment includes the removable supporting plate  110 , thus during processes of disposing the chip  210 , forming the wires  220  and performing the packaging, the removable supporting plate  110  may serve as a supporting structure for providing a sufficient supporting strength to reinforce a structural strength of the circuit board  120   b . Subsequently, in order to satisfy the development trend of the package structure towards light, thin, short, and small, after packaging, the removable supporting plate  110  of the package carrier  100   d  may be removed to expose the second patterned circuit layer  124   b  exposed by the second solder mask layer  127   b , as shown in  FIG. 5 . Thereafter, a plurality of solders  240  may be bonded on the second patterned circuit layer  124   b  exposed by the second solder mask layer  127   b  thereby forming a package structure  200  capable of electrically connecting to external circuits. In this case, since the removable supporting plate  110  in the package structure  200  is already removed, a whole thickness of the package structure  200  may be effectively reduced. 
     In summary, in the package carrier of the invention, the removable supporting plate is served as a supporting structure for supporting the circuit board, and the removable supporting plate may be removed after a chip is disposed on the circuit board of the package carrier and the packaging is completed. Therefore, in comparison with a package structure having a core dielectric layer in conventional art, a package structure composed of the package carrier of the invention can have a relatively small thickness. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.