Patent Publication Number: US-8524527-B2

Title: High-performance single-crystalline N-type dopant-doped metal oxide nanowires for transparent thin film transistors and active matrix organic light-emitting diode displays

Description:
CLAIM OF PRIORITY 
     This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/246,087 entitled: “High-Performance Single-Crystalline Arsenic-Doped Indium Oxide Nanowires for Transparent Thin Film Transistors” filed Sep. 25, 2009, the entire contents of which are incorporated by reference. 
    
    
     GOVERNMENT SUPPORT 
     This invention was made with government support under grant numbers CCF 0726815 and CCF 0702204 awarded by the National Science Foundation. The government has certain rights in the invention. 
    
    
     BACKGROUND 
     This application relates to transparent electronics. 
     Transparent electronics can be implemented in various applications, including displays, 2-5  solar cells, 6,7  charge-coupled devices (CCDS), 8  and UV detectors. 9,10  The core technology to realize the transparent electronics requires the development of high-performance transparent thin film transistors (TTFTs), with high device mobilities, moderate carrier concentrations, low threshold voltages, and steep subthreshold slopes. 11  Currently, TTFTs fabricated with amorphous or polycrystalline transparent conducting oxide (TCO) thin films have been widely studied, including ZnO, SnO 2 , CuAl0 2  and many other semiconductor oxides. 1,12-16  However, TTFTs made from these materials usually exhibit rather low mobilities (0.2-120 cm 2 V −1  sec −1 ) and high threshold voltages (Vth: 10-20 V). 14-17  For instance, TTFTs with amorphous indium gallium oxide (α-IGO) films display device mobility of 7 cm 2 V −1  sec −1 , a current on-off ratio of 10 4 , and an inverter gain of 1.5 on glass substrates. 18  These results clearly indicate that the performance of TCO thin film-based TTFTs may limit their operation in high frequency applications and has significant room for further improvement. 
     SUMMARY 
     Techniques, systems, apparatus materials are disclosed for implementing high-performance arsenic (As)-doped indium oxide (In 2 O 3 ) nanowires for transparent electronics, including their implementation in transparent thin-film transistors (TTFTs) and transparent active-matrix organic light-emitting diodes (AMOLED) displays. 
     The subject matter described in this specification potentially can provide one or more of the following advantages. With the aid of n-type dopants, such as arsenic, zinc and antimony, and a self-assembled gate nanodielectric, As-doped In 2 O 3  nanowire TTFTs with transparent ITO contacts show good transparency and excellent transistor performance such as high mobility, high on/off ratio, low operation voltage, and steep subthreshold slope. A saturation device mobility of 1,490 cm 2 V −1 s −1  can be achieved on glass substrates, which is the highest TTFT device mobility reported so far. We further examined the AC gain from a single As-doped In 2 O 3  nanowire TTFT, and the results indicate good frequency response and a unity-gain frequency of 18.8 GHz. In addition, the TTFTs were further utilized to construct a transparent circuit and used to control a variable-intensity OLED. Moreover, an AMOLED display with good transparency was also fabricated which generates numerical displays. Results suggest that As-doped In 2 O 3  nanowires have great potential to serve as building blocks for future transparent electronics. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1   a  shows an SEM image of As-doped indium oxide nanowires. 
         FIG. 1   b  shows EDS spectrum showing the chemical composition of the As-doped indium oxide nanowires. 
         FIG. 1   c  shows corresponding HR-TEM image of a single As-doped In 2 O 3  nanowire with a diameter of ˜16 nm. 
         FIG. 1   d  shows another HR-TEM image, where the (100) planes are clearly visible, and oriented perpendicular to the vertical axis. 
         FIG. 2   a  shows Schematic diagram of As-doped In 2 O 3  nanowire TTFT fabricated on an ITO glass substrate, with ALD-deposited Al 2 O 3  or SAND as the dielectric layer and IAD-deposited ITO as source and drain electrodes. 
         FIG. 2   b  shows Optical photograph of fully transparent As-doped In 2 O 3  nanowire transistors. 
         FIG. 2   c  exhibits Family of I ds -V DS  curves of a single As-doped In 2 O 3  nanowire TTFT with the channel length of 1.8 μm. 
         FIG. 2   d  shows Current versus gate voltage (I ds -V g ) plot in the linear regime (V DS =200 mV). 
         FIG. 2   e  shows the measurement setup showing As-doped In 2 O 3  nanowire transistor configured as a common-source amplifier. 
         FIG. 2   f  shows the frequency response of AC gain of As-doped In 2 O 3  nanowire TTFT. 
         FIG. 2   g  shows the bilateral small-signal model used in the patent. 
         FIG. 3   a  shows a plot of the output current through the loaded OLED (I OLED ) versus V in  with V dd  at 5.0 V in linear scale (red line) and log scale (blue line), respectively. 
         FIG. 3   b  shows OLED light intensity versus V in  with V dd =5.0 V. Inset: OLED spectrum. 
         FIG. 3   c  shows optical images of the OLED under V in =−3.0 V, 0.0 V, and 3.0 V. 
         FIGS. 4   a - c  show applications of As-doped In203 nanowire TTFT circuitry to drive a seven segment AMOLED display. 
         FIG. 5  is a process flow diagram showing a process of synthesizing As-doped In 2 O 3 . 
         FIG. 6  is a process flow diagram of a process for fabricating As-doped In 2 O 3  nanowire transistors with a SAND dielectric. 
         FIG. 7   a  represents the Family of I ds -V DS  curves for a single As-doped In 2 O 3  nanowire transistor using SAND as the dielectric layer with a channel length of 1.8 μm. 
         FIG. 7   b  shows the current versus gate voltage (I ds -V g ) curves in the linear region (V DS =200 mV). 
         FIG. 8  is a process flow diagram of a process for fabricating As-doped In 2 O 3  nanowire TTFTs with an Al 2 O 3  dielectric. 
         FIGS. 9   a ,  9   b  and  9   c  show device mobility, subthreshold voltage, and I on /I off  ratio of 10 single nanowire TTFTs, with the straight lines indicating average values for the respective parameters. 
         FIG. 10  is a process flow diagram of a process for OLED depositions for AMOLED display. 
         FIG. 11  shows optical transmission spectra of a typical As-doped In 2 O 3  nanowire TTFT, and an AMOLED display substrate after transparent OLED deposition. 
     
    
    
     Like reference symbols and designations in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     Transparent electronics or invisible circuits can provide optical transparency and low temperature processing. As such, transparent electronics can be used in various applications including displays, solar cells, charge-coupled devices (CCDS), and ultraviolet (UV) detectors. High-performance transparent thin film transistors (TTFTs) with high device mobilities, moderate carrier concentrations, low threshold voltages, and steep subthreshold slopes can be used to implement the transparent electronics. TTFTs can be fabricated with amorphous or polycrystalline transparent conducting oxide (TCO) thin films, including ZnO, SnO 2 , CuAlO 2  and many other semiconductor oxides. However, TTFTs made from these materials usually exhibit rather low mobilities (e.g., 0.2-120 cm 2 V −1  sec −1 ) and high threshold voltages (e.g., V th : 10-20 V). For instance, TTFTs with amorphous indium gallium oxide (α-IGO) films display device mobility of 7 cm 2 V −1  sec −1 , a current on-off ratio of 10 4 , and an inverter gain of 1.5 on glass substrates. Based on these results, TCO thin film-based TTFTs may have limited use in high frequency applications. 
     Additionally, one-dimensional (1-D) nanostructured materials, including single-walled carbon nanotubes (SWNTs) and semiconductor metal oxide nanowires can be used for TTFT fabrications. In comparison to conventional TCO-based TTFTs, nanomaterials synthesized through a simple chemical vapor deposition (CVD) method can easily provide high-quality single-crystalline nanostructures, which are highly desirable in most electronic and optoelectronic devices. In addition, nanostructured material-based TTFTs can provide added advantages, such as versatile compatibility with a variety of device substrates, which can extend their applicability to flexible electronics, due to the compatibility of nanostructured TTFTs with low temperature processing. Among these nanomaterials, In 2 O 3  nanowires having a wide energy gap (˜3.75 eV), a single crystalline nanostructure, and high device mobility may be one of the best candidates for high performance TTFTs. For example, 1n 2 O 3  nanowire TTFTs with a device mobility as high as 514 cm 2 V −1  sec −1  can be implemented. Further improvement in performance may be achieved through doping of the nanowires. 
     For display implementation, having good optical transparency and/or mechanical flexibility, high performance transparent and/or flexible TFTs can be useful. For example, the circuitry of an active matrix organic light-emitting diode (AMOLED) pixel usually contains one driving transistor and one switching transistor. The driving transistors need to carry sufficient current to the OLED pixels, and the switching transistors should be capable of operating at 60-120 Hz for the human eye to see an integrated image of successively presented patterns in a video display (so-called retinal persistence). Polycrystalline silicon (poly-Si) and amorphous silicon (α-Si) can be used as the “back-panel” electronics for AMOLED displays. However, these poly-Si and α-Si back-panels are generally optically opaque, not compatible with flexible substrates, and can have low mobilities, high threshold voltages, and in the case of α-Si, poor current-carrying capacity. 
     Described below are synthesis of arsenic (As)-doped In 2 O 3  nanowires on Si/SiO 2  substrates; fabrication of TTFTs by transferring the doped nanowires to glass substrates with pre-patterned indium-tin oxide (ITO) gate electrodes and an Al 2 O 3  or a self-assembled nanodielectric (SAND) gate insulator; and patterning of transparent ITO source and drain electrodes. The as-fabricated As-doped In 2 O 3  nanowire TTFTs perform as typical n-type FETs with a high device mobility (e.g., 1,490 cm 2 V −1  sec −1 ) and optical transparency of near 81% in the visible wavelength regime. Also described is the AC gain of these nanowire TTFTs. The results indicate good frequency response, ˜1.5 kHz with a unity-gain frequency of ˜18.8 GHz. Moreover, As-doped In 2 O 3  nanowire TTFTs can be used to drive organic light-emitting diodes (OLEDs) with tunable emitting intensities, including a seven-segment AMOLED display enabled by a nanowire TTFT “back-panel.” 
     Techniques, systems, apparatus and materials are described for implementing high-performance arsenic (As)-doped indium oxide (In 2 O 3 ) nanowires for transparent electronics, including their implementation in transparent thin-film transistors (TTFTs) and transparent active-matrix organic light-emitting diodes (AMOLED) displays. The As-doped In 2 O 3  nanowires can be synthesized using a laser ablation process, and then fabricated into TTFTs with indium-tin-oxide (ITO) as the source, drain and gate electrodes. The nanowire TTFTs on glass substrates exhibit very high device mobilities (e.g., ˜1,490 cm 2 V 1 s −1 ), current on/off ratios (e.g., 5.7×10 6 ), steep subthreshold slopes (e.g., 88 mY/dec), and a saturation current of 60 μA for a single nanowire. By using a self-assembled nanodielectric (SAND) as gate dielectric, the device mobilities and saturation current can be further improved up to 2,560 cm 2 V −1 s −1  and 160 μA, respectively. All devices exhibit good optical transparency (e.g., ˜81% on average) in the visible spectral range. In addition, the nanowire TTFTs can be utilized to control green OLEDs with varied intensities. Furthermore, a fully integrated seven-segment AMOLED display was fabricated with a good transparency of 40% and with each pixel controlled by two nanowire transistors. As described below, performance enhancement can be achieved by combining nanowire doping and self-assembled nanodielectrics to implement silicon-free electronic circuitry for low power consumption, optically transparent, high-frequency devices assembled near room temperature. 
     Characterizations of Arsenic-Doped Indium Oxide Nanowires 
     As-doped In 2 O 3  nanowires can be grown on a Si/SiO 2  substrate by a laser ablation process. Using argon mixed with oxygen as the carrier gas, hydrogen can be added to the carrying gas to suppress the oxidation processes and incorporate a small amount of As into the In 2 O 3  nanowires. The surface morphology and crystal structure of the As-doped In 2 O 3  nanowires can be further characterized by field-emission scanning electron microscopy (FESEM), high-resolution transmission electron microscopy (HRTEM), selected area electron diffraction pattern (SAED), and energy dispersion X-ray spectrometry (EDS). 
       FIG. 1   a  shows a typical SEM image  100  of as-grown As-doped In 2 O 3  nanowires which are ˜5-10 μm long with a diameter of 15-30 nm. In the inset  110  of the SEM image  100 , an Au/In alloy particle  112 , with a diameter of ˜16 nm, can be clearly observed at the very tip  114  of a nanowire  116 , supporting growth via a so-called vapor-liquid-solid (VLS) growth mechanism. In addition, the As-doped In 2 O 3  nanowires have perfectly smooth surfaces without any amorphous coating and have extremely uniform diameters. To further evaluate the composition of the As-doped In 2 O 3  nanowires, (EDS) can be performed during a (TEM) investigation.  FIG. 1   b  shows a typical EDS spectrum  120  of an individual As-doped In 2 O 3  nanowire, which indicates the presence of As elements  122  and  124  in In 2 O 3  nanowires. The atomic ratio of In:As can be estimated as 100:4. The atomic density of indium atoms in In 2 O 3  is about 3.12×10 22  atom/cm 3 , and the dopant density of 4% As dopants can be estimated to be 1.25×10 21  atom/cm 3 . 
     Also, the crystallography of these As-doped nanowires can be studied using HRTEM (SAED). HRTEM (see image  130 ) confirms that each As-doped In 2 O 3  nanowire has a perfect single crystalline structure without any noticeable dislocations or defects, and the corresponding SAED (see image  132  in the inset) reveals that the phase of As-doped nanowires is body-centered cubic (bcc), as shown in  FIG. 1   c . The interspacing between each plane is 0.506 nm, corresponding to the (200) plane in the bcc As-doped In 2 O 3  nanowire crystal structure as shown in the image  140  of  FIG. 1   d , with the lattice constant (α) of 1.012 nm slightly expanded versus that of un-doped In 2 O 3  nanowires (α=1.01 nm). The expanded lattice constant can be attributed to the incorporation of As into the In 2 O 3  nanowires. Taken together, these results indicate that these nanowires grown using the present laser ablation process exhibit high crystalline quality, with the In 2 O 3  nanowire structural integrity preserved after As dopant incorporation. 
     Electronic Transport Characteristics of As-doped In 2 O 3  Nanowire TTFTs 
     Doping processes can substantially enhance the electrical properties of nanowire materials in a controlled fashion, and zinc, antimony and arsenic are all effective n-type dopants which increase the carrier concentration in In 2 O 3  thin films. For illustrative purposes, described below are As-doped In 2 O 3  nanowires used as the semiconductor in TTFT devices. After the nanowire synthesis, the as-grown nanowires are removed from the Si/SiO 2  substrates by ultra-sonication to yield a suspension in isopropyl alcohol (IPA), and are dispersed onto an ITO substrate with 50 nm Al 2 O 3  dielectric. The process can be performed repeatedly until the desired nanowire density is achieved and then ITO can be deposited as source and drain electrodes. The nanowire orientation can be random, but the desired density and a yield of at least 80% can be achieved for the transistors.  FIG. 2   a  shows a schematic  200  of an As-doped In 2 O 3  nanowire TTFT  201  on an ITO glass substrate  202 , with an atomic layer deposition (ALD)-derived high-k Al 2 O 3  (thickness of 50 nm, k eff ˜9.0) dielectric layer  204 , and ion-assisted deposition-derived (IAD) ITO (thickness of 100 nm, sheet resistance ˜60Ω/□) source  206  and drain  208  electrodes, with the semiconductor-doped metal oxide nanowires  210  as the active channel. Details can be found below. 
       FIG. 2   b  displays an optical image of  220  an As-doped In 2 O 3  nanowire TTFT substrate, with the background photograph  222  visible through the transistor regions. The transmittance spectrum in  FIG. 7  below reveals ˜81% optical transmission, essentially identical to that of bare glass or glass/ITO substrates. 
     Detailed electronic transport measurements can be carried out to characterize the electronic properties of single As-doped In 2 O 3  nanowire TTFTs.  FIG. 2   c  is a chart  230  of the measured drain current (I ds ) versus source-drain voltage (V DS ) characteristics of a representative single nanowire TTFT. The channel length of the as-fabricated TTFTs is ˜1.8 μm, shown in the inset SEM image  242  of  FIG. 2   d  (scale bar=1 μm). The device exhibits typical enhancement-mode n-type semiconductor transistor behavior with an on-current (I on ) of ˜60 μA. while V g =4.5 V and V DS =3V. Note that doping helps to reduce the contact resistance in In 2 O 3  nanowire FETs, shown by the absence of a Schottky barrier in  FIG. 2   c.    
       FIG. 2   d  is a chart  240  that shows the drain current (I ds ) versus gate voltage (V g ) characteristics for a single transparent As-doped In 2 O 3  nanowire transistor. The doped In 2 O 3  nanowire devices display I on /T off =5.7×10 6 , a peak subthreshold slope (S)=88 mV/dec, and threshold voltage (V T )=0.5 V, while V DS =200 mV. The mobility (μ) can be calculated from the maximum transconductance by applying the equations 1 and 2. 
                     device   ⁢           ⁢     mobility   ⁡     (   μ   )         =         L   2         V   DS     ⁢     C   i         ·       ⅆ     I   DS         ⅆ     V   g                   (   1   )               
where L is the channel length and C i  is the specific capacitance of single doped nanowire calculated as follows,
 
 C   i =2π∈ 0 ∈ s   L /ln(2 h/r)  (2)
 
where, r is the radius of doped In 2 O 3  nanowires, h is the thickness of the dielectric layer, and ∈ s  is the dielectric constant of ALD deposited Al 2 O 3 . The device mobility can vary from ˜1,080-1,490 cm 2 V −1  sec −1  as the gate bias is increased from 1.0 V to 3.0 V. In comparisons to other nanowire TFTs, the present mobilities are substantially greater, with ZnO=20 cm 2 V −1  sec −1 , In 2 O 3 =35 cm 2 V −1  sec −1 , and SnO 2 =15 cm 2 V −1  sec −1 . This can be understood from the single-crystal nature of the As-doped In 2 O 3  nanowires and the formation of relatively high-quality interfaces. Note that the present device performance rivals or exceeds that of previously reported doped and un-doped metal oxide nanowire TTFTs. Table 1 summarizes the relevant data which suggest that the As doping should significantly enhance overall nanowire device performance.
 
                                     TABLE 1                   On-Current   Mobility   On/off    Subthreshold       Material   (μA)   (cm 2 /VS)   ratio   Slope (mV/dec)                                                    In 2 O 3  NW   &lt;1   98.1   2 × 10 4     N/A       In 2 O 3  NW   10   514   10 6     160       In 2 O 3  Thin film   800   120   10 5     80       ZnO   2   96   10 6     300       Ta-SnO 2  NW   20   120   10 5     270       Sb-SnO 2  NW   22   550   10 5     170       Zn-In 2 O 3  NW   8.5   80   10 6     700       As-In 2 O 3  NW   60   1,490   5.7 × 10 6     88                    
Detailed statistical study of ten single nanowire TTFTs (see  FIGS. 6   a ,  6   b  and  6   c  below) reveals that the device mobility is 1,200 cm 2 V −1  sec −1  in average with a standard deviation of 210 cm 2 V −1  sec −1  the subthreshold voltage is 170 mV/dec with a standard deviation of 90 mV/dec, and the I on /I off  ratio is from 10 5  to 10 7 .
 
     To further modify device performance, the 50 nm Al 2 O 3  gate dielectric can be replaced with an organic self-assembled nanodielectric (SAND), layer (thickness ˜16 nm, k eff ˜5; see below for details). The mobility of a single As-doped In 2 O 3  nanowire TFT is enhanced to ˜2,560 cm 2 V −1  sec −1 , for V g  and V DS =4.4 V and 200 mV, respectively. In addition, I on  is increased to 160 μA at Vg=3.0 V and V DS =1.5 V, and S increased to 149 mV/dec (see  FIGS. 5   a  and  5   b  below). These SAND effects can be attributed to: the advantageous characteristics of the high-capacitance dipolar organic nanoscopic dielectrics. Similar I on /I off  ratio (˜10 4 ) was previously reported for ZnO/SAND nanowire TFTs, and may result from the gate leakage current. The gate leakage current was measured between the source/drain pads and the back gate electrode (with overlapping area of ˜2×10 5  μm 2 ) to be about 1 nA for the 16 nm SAND dielectric and 20 pA for the 50 nm Al 2 O 3  dielectric at V g =3 V. This gate leakage current for SAND dielectric sets a lower limit for the off current that can be reliably measured, and may be a reason for the observed I on /I off  ratio of 10 4  for the SAND-gated devices. Much of the measured leakage current may be conduction between the source/drain pads and the back gate electrode underneath, and thus the leakage current could be greatly reduced by using a patterned gate electrode with minimized overlap with the source and drain electrodes. 
     The present devices exhibit high mobilities and steep subthreshold slopes, which are desired properties for fast device operation, such as switching transistors in AMOLED displays. The unity-gain frequency of the nanowire TTFTs can be estimated using equation 3, where (V g -V T ) is the gate overvoltage (the applied gate voltage in excess of the threshold voltage). 
     
       
         
           
             
               
                 
                   
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     In this approximation, the unity-gain frequency of the described TTFTs can reach 18.8 GHz. In addition, the AC gain and radio-frequency response (RFR) can be described from the As-doped In 2 O 3  nanowire TTFTs.  FIG. 2   e  is a diagram  250  that shows an experimental set-up for AC measurements. The nanowire TTFT is configured as common-source amplifier, and DC offsets are applied to the gate and drain electrodes to bias it in saturation, near the maximum g m  (˜1.8 μS). 
       FIG. 2   f  is a plot  260  that shows the RFR of the device measured by applying digital signal processing (DSP) to the time domain signals ( 262 —open circles), simulated data for the as-fabricated TTFT ( 264 —closed circles), and simulated data for an optimized device structure ( 266 —open boxes). A gain of ˜6 dB can be observed at low frequency with a roll-off around 500 Hz and a cut-off frequency (f −3 dB ) of ˜1.5 kHz, which is comparable to earlier work. To understand the frequency response of the described As-doped In 2 O 3  nanowire TTFTs, a bilateral small-signal model  270  (shown in  FIG. 2   g ) can be applied to model the AC characteristics of the present TTFTs. The simulated result ( 264 —closed circles in  FIG. 2   f ) agrees well with the measured data, suggesting that the operation frequency is strongly influenced by the parasitic capacitance associated with the source and drain contact electrodes (˜157 pF) and the probes (˜100 pF). By optimizing the device dimensions and structure (i.e., use short channel widths and reduce overlaps between source and drain contact electrodes), and adopting an active probe (˜1 MΩ) for the measurements, the cut-off frequency (f −3 dB ) can be increased to 400 MHz, shown in the  FIG. 2   f  ( 266 —open boxes). The simulated results therefore suggest that As-doped In 2 O 3  nanowire TTFTs can offer great potential in high frequency device applications. 
     Fully Transparent OLED Driving Circuitry 
     The ability to fabricate high performance As-doped In 2 O 3  nanowire TTFTs enables further exploration of transparent circuit applications. Controlling a variable-intensity OLED can be also implemented. For example,  FIG. 3   a  shows a plot  300  of an output current through the loaded OLED (I OLED ) versus V in  with V dd  at 5.0 V in linear scale  302  and log scale  304 , respectively.  FIG. 3   a  shows that a monochrome OLED can be wire-bonded on a breadboard together with an As-doped In 2 O 3  nanowire TTFT chip. The inset  306  of  FIG. 3   a  shows a circuit diagram of the experimental setup, where one TTFT is connected to an external OLED, and V dd  is applied to drain of the transistor. By controlling V in  that provides a gate voltage for the transistor with fixed V dd , the voltage drop across the OLED can be controlled. In  FIG. 3   a , the current flowing through the OLED is successfully modulated via V in  by a factor of ˜300, thus controlling the OLED light intensity, as shown in  FIG. 3   b .  FIG. 3   b  is a plot  310  that shows the OLED light intensity versus V in  ( 312 ) with V dd =5.0 V. The inset  314  of  FIG. 3   b  shows the OLED spectrum  316 . OLED light intensity below 1 Cd/m 2  is usually defined as the off-state and above 1 Cd/m 2  as the on-state. Although the present off-state:on-state light intensity ratio is −5, the effect is clearly visible in  FIG. 3   c  where the OLED is operated with V in =−3 ( 320 ),  0  ( 322 ), and  3  ( 324 ) V, respectively. 
     AMOLED Display and Drive Circuitry 
     The discussion above demonstrates the high-performance characteristics of As-doped In 2 O 3  nanowire/SAND TTFTs, including high device mobility and fast device operation, can be employed as switching and driving transistors in an AMOLED display circuitry. In addition, described below is fabrication of an AMOLED display using high-performance As-doped In 2 O 3  TTFTs.  FIG. 4   a  shows an equivalent circuit diagram  400  of seven segment AMOLED display circuitry. Note that the driving circuit of each OLED pixel can consist of one switching transistor (T 1 ), one driving transistor (T 2 ), and one storage capacitor (C st ). T 1  is employed to select a specified pixel and transfer data through the data line to the OLED. T 2  is employed to control the current supplied to the OLED pixel, which is adjusted by controlling the V g  of T 2 , equal to the voltage difference between the ends of C st . The storage capacitor is employed to store data during one period for time-varying operations. The EL opening area of each segment is −0.18 mm 2 . In some implementations, the driving circuit of each OLED pixel can include additional components. 
     AMOLED display fabrication begins by patterning the OLED ITO anode and individually addressed bottom gate electrodes by photolithography and wet etching. Next, 50 nm ALD Al 2 O 3  is deposited on the patterned ITO gate and OLED anodes. Following Al 2 O 3  deposition, contact holes above the OLED anodes, as bottom gate electrode contacts for each pixel, are fabricated through a wet etching process. After that, a suspension of As-doped In 2 O 3  nanowires in 2-propanol alcohol is dispersed on the device substrate. A thin layer of source and drain electrodes (20 nm Al) are then deposited bye-beam evaporation and patterned by lift-off. Following source and drain electrode patterning, a 200 nm thick SiO 2  layer is deposited by e-beam evaporation to passivate the device and planarize the nanowire transistors for OLED fabrication. The detail of OLED deposition can be found below. 
       FIG. 4   b  shows an optical image  410  of a 1″×1″ inch AMOLED display substrate before OLED deposition, with a background image  412  visible through the display region. The optical transmittance spectrum (see  FIG. 7  below) reveals that the optical transmittance values of the AMOLED display before and after OLED layer deposition are ˜81% and ˜35% in the visible region, respectively. The optical transmittance should be readily increased using a more transparent OLED design. The display can consist of 12 seven-segment OLED pixels, 84 OLED unit pixels, and 156 nanowire TTFTs. In some implementations, additional components can be included. For each seven-segment OLED pixel, the scan lines for all unit pixels are individually controlled, as are the data lines.  FIG. 4   c  shows optical images  420 ,  422  and  424  of the seven segment pixels with different numerical digits at different data line voltages (V data =−5 to 5 V) with different scan line voltages (V scan =−5 to 5 V) and fixed V dd  (=3 V). This may be the first demonstration of a seven-segment AMOLED display driven entirely by TTFT circuits. 
     The great potential of As-doped In 2 O 3  nanowires for high-performance transparent electronics has been described. With the aid of arsenic dopants and a self-assembled gate nanodielectric, As-doped In 2 O 3  nanowire TTFTs with transparent ITO contacts show good transparency and excellent transistor performance such as high mobility, high on/off ratio, low operation voltage, and steep subthreshold slope. A saturation device mobility of 1,490 cm 2 V −1 s −1  is achieved on glass substrates, which is the highest TTFT device mobility reported so far. Additionally, the AC gain from a single As-doped In 2 O 3  nanowire TTFT has been examined, and the results indicate good frequency response and a unity-gain frequency of 18.8 GHz. In addition, the TTFTs can be utilized to construct a transparent circuit and used to control a variable-intensity OLED. Moreover, an AMOLED display with good transparency can be also fabricated which generates numerical displays. Our results suggest that As-doped In 2 O 3  nanowires have great potential to serve as building blocks for future transparent electronics. 
     As-doped In 2 O 3  Nanowire Synthesis 
       FIG. 5  is a process flow diagram showing a process  500  of synthesizing As-doped In 2 O 3 . 10 nm gold nanoparticles can be dispersed on a Si/SiO 2  substrate and utilized as catalysts in the nanowire synthesis ( 510 ). n-type dopant-doped metal oxide nanowires can be grown on the substrate using a laser ablation process ( 520 ). The laser ablation process can include: placing the nanoparticles dispersed substrate into a quartz tube at the down stream end of a furnace ( 522 ); placing an InAs target at the upper stream of the furnace ( 524 ). During the laser ablation process, the chamber of the furnace is heated ( 526 ). For example, the chamber can be maintained at 760 Torr, 700° C. To a carrier gas that includes argon (Ar) and oxygen (O 2 ), H 2  can be added (e.g., 10% H 2 ) ( 528 ), and the H 2  added carrier gas can be flowed over the substrate to suppress oxidation processes and incorporate the n-type dopant into the metal oxide nanowires ( 529 ). For example, a constant flow of 150 standard cubic centimeters (sccm) of the carrier gas can be flowed over the substrate. The typical reaction time is about 50 minutes. After cooling down ( 530 ), the samples can be characterized using FESEM, TEM, XRD and EDS. 
     The Fabrication of As-doped In 2 O 3  Nanowire Transistors with a SAND Dielectric 
       FIG. 6  is a process flow diagram of a process  600  for fabricating As-doped In 2 O 3  nanowire transistors with a SAND dielectric. After the n-type dopant-doped metal oxide nanowire synthesis ( 610 ), the as-grown nanowires can be removed from the Si/SiO 2  substrates by ultra-sonication to yield a suspension in isopropyl alcohol (IPA) ( 620 ), and can be then dispersed onto a silicon substrate coated with dielectric layer (e.g., SAND or ALD Al 2 O 3 ) ( 630 ). The process can be performed repeatedly until the desired nanowire density is achieved ( 640 ). The nanowire orientation can be random, but the desired density can be achieved. A yield of at least 80% can be achieved for the transistors. The SAND dielectric films used can consist of layer-by-layer self-assembled multilayers deposited using procedures described in the Yoon et al. paper (see Yoon, M. Y.; Facchetti, A.; Marks, T. J., σ-π molecular dielectric multilayers for low low-voltage organic thin-film transistors.  Proceedings of the National Academy of Sciences  2005, 102, (13), 4678-4682.) The SAND dielectric can be composed of self-assembled multilayers that include the following layer building blocks: (i) α,ω-difunctionalized hydrocarbon chains that block charge transport due to their saturated structures, (ii) highly polarizable stilbazolium π-electron layers that stabilize charge carriers in the channel with oriented dipoles, and (iii) glassy siloxane polymer layers that planarize the surface and enhance structural robustness by cross-linking and filling pinholes. Next, photolithography can be applied to pattern both source and drain electrodes to bridge the nanowires ( 650 ), followed by metal deposition of 5 nm Ti/45 nm Au using an e-beam evaporation ( 660 ). The degenerately doped silicon substrate can serve as the back gate. The mobility of a single As-doped In 2 O 3  nanowire TFT is enhanced to ˜2,560 cm 2 V −1  sec −1 , for V g =4.4 V and V DS =200 mV. In addition, I on  can be increased to 160 μA at V g =3.0 V and V DS =1.5 V, and S increased to 149 mV/dec. 
       FIG. 7   a  ( 5   a ) is a plot  700 ( 500 ) that shows a family of I ds -V DS  curves  702 ,  703 ,  704 ,  705 ,  706 ,  707  and  708  for a single As-doped In 2 O 3  nanowire transistor using SAND as the dielectric layer with a channel length of 1.8 μm. The gate voltage is varied from −2.0 V to 4.0 V in steps of 1.0 V from the bottom to top ( 702 ,  703 ,  704 ,  705 ,  706 ,  707  and  708 ).  FIG. 7   b  is a plot  710  that shows the current versus gate voltage (I ds -V g ) curves in the linear region (V DS =200 mV). Curves  712 ,  714  and  716  correspond to a linear-scale I ds -V g , log scale I ds -V g , and μ, respectively. 
     The Fabrication of As-doped In 2 O 3  Nanowire TTFTs with an Al 2 O 3  Dielectric 
       FIG. 8  is a process flow diagram of a process  800  for fabricating As-doped In 2 O 3  nanowire TTFTs with an Al 2 O 3  dielectric. For transparent nanowire transistors, fabrication can be started with the deposition of a 50 nm Al 2 O 3  dielectric layer by atomic layer deposition (ALD) on a commercial ITO glass (Sheet Resistance=20Ω/□) at 250° C. ( 810 ). The ITO glass can serve as the back gate of the transparent transistors. The As-doped In 2 O 3  nanowires can be then dispersed on the substrates as described above ( 820 ). After forming (e.g., patterning) source and drain electrodes by photolithography ( 830 ), a transparent conductor layer (e.g., ITO) can be deposited by ion-assisted deposition (IAD) at room temperature (R sheet =60Ω/□) with an ITO (In 2 O 3 :SnO 2 =9:1) target purchased from William Advanced Materials, for example ( 840 ). The schematic diagram is shown in  FIG. 2   a  above, inset. Next, the electronic parameters of as-fabricated nanowire TTFTs can be examined by using Agilent 4156B instrumentation, for example. 
       FIGS. 9   a  ( 6   a ),  9   b  and  9   c  show the device mobility  900 , subthreshold voltage  910 , and I on /I off  ratio  920  of 10 single As-doped In 2 O 3  nanowire TTFTs. The straight lines  902  and  904  indicate corresponding average values. The device mobility is 1,200 cm 2 V −1  sec −1  in average with a standard deviation of 210 cm 2 V −1  sec −1 , the subthreshold voltage is 170 m/dec with a standard deviation of 90 mV/dec, and the I on /I off  ratio is from 10 5  to 10 7 . 
     OLED Depositions for the AMOLED Display 
       FIG. 10  is a process flow diagram of a process  1000  for OLED depositions for AMOLED display. After the fabrication of the As-doped In 2 O 3  nanowire TTFT back-panel ( 1010 ), the back-panel or chip can be cleaned with UV/ozone for 10 minutes, for example ( 1020 ). The cleaned back-panel can be then placed in the vacuum chamber of an evaporator ( 1030 ). All compounds can be purified using temperature gradient vacuum sublimation prior to deposition ( 1040 ). A shadow mask can be placed on the nanowire TTFT back-panel ( 1050 ), after which organic layers (20 nm of NPD, 25 nm of 8% Irppy/CBP, and 400 {acute over (Å)} of BCP) can be deposited by thermal evaporation from resistively heated tantalum boats at a rate of about 2 {acute over (Å)}/s ( 1060 ), followed by the cathode consisting 10 {acute over (Å)} of LiF ( 1070 ) and 150 {acute over (Å)} of aluminum ( 1080 ). The AMOLED devices can be then connected with a home-made electrical measurement jig to drive the AMOLED displays ( 1090 ). The transmittance spectrum reveals ˜81% optical transmission of As-doped In 2 O 3  nanowire TTFT, essentially identical to that of bare glass or glass/ITO substrates. After OLED layer deposition, the transmittance spectrum of AMOLED display is about 35% optical transmission. FIG.  11 ( 7 ) is a plot  1100  showing an optical transmission spectra of a typical As-doped In 2 O 3  nanowire TTFT (curve  1102 ), and a AMOLED display substrates after transparent OLED deposition (curve  1104 ). 
     While this specification contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. 
     Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments. 
     Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this application.