Patent Publication Number: US-2023136778-A1

Title: Semiconductor substrate structure and manufacturing method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of the U.S. provisional application Ser. No. 63/275,914, filed on Nov. 4, 2021, and the priority benefit of Taiwan application serial no. 111140307, filed on Oct. 24, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     Technical Field 
     The disclosure relates to a semiconductor substrate structure and a manufacturing method thereof. 
     Description of Related Art 
     In applications of integrated circuit, the redistribution circuit layer (RDL) is a multilayer structure formed by conductive material and dielectric material. The redistribution circuit layer is often manufactured on a temporary carrier. However, the material used in the aforementioned multilayer structure and the material used in the temporary carrier may have a coefficient of thermal expansion (CTE) mismatch. Thus, warpage is likely to occur in the process of continuously forming the aforementioned multilayer structure (at least four layers continuously) on the temporary carrier. The more the layers, the more obvious the warpage. As a result, the yield and electrical performance of the semiconductor substrate structure will be adversely affected. 
     SUMMARY 
     The disclosure provides a semiconductor substrate structure and a manufacturing method thereof, which maintains better yield and electrical performance while having a multilayer redistribution structure. 
     The semiconductor substrate structure of the disclosure includes a first group of circuit structure and a second group of circuit structure. The first group of circuit structure includes multiple first circuit layers and a first bonding layer. The second group of circuit structure includes multiple second circuit layers and a second bonding layer. The second group of circuit structure is disposed on the first group of circuit structure and is electrically connected to the first group of circuit structure. The first bonding layer is bonded to the second bonding layer to form a multilayer redistribution structure. 
     The semiconductor substrate structure of the disclosure includes a first group of circuit structure, a second group of circuit structure, and a third group of circuit structure. The first group of circuit structure includes multiple first circuit layers and a first bonding layer. The second group of circuit structure includes multiple second circuit layers and a second bonding layer. The second group of circuit structure is disposed on the first group of circuit structure and is electrically connected to the first group of circuit structure. The first bonding layer is bonded to the second bonding layer. The third group of circuit structure includes multiple third circuit layers and a third bonding layer. The second group of circuit structure is disposed between the first group of circuit structure and the third group of circuit structure and are electrically connected with each other. The second group of circuit structure includes another bonding layer relative to the first group of circuit structure, and the another bonding layer is bonded to the third bonding layer to form a multilayer redistribution structure. 
     The manufacturing method of a semiconductor substrate structure of the disclosure includes at least the following process. A first group of circuit structure is formed on a first temporary carrier. The first group of circuit structure includes multiple first circuit layers and a first bonding layer. A second group of circuit structure is formed on a second temporary carrier. The second group of circuit structure includes multiple second circuit layers and a second bonding layer. The first group of circuit structure and the second group of circuit structure are directly bonded, so that the first bonding layer is bonded to the second bonding layer. 
     The manufacturing method of a semiconductor substrate structure of the disclosure includes at least the following process. A first group of circuit structure is formed on a first temporary carrier. The first group of circuit structure includes multiple first circuit layers and a first bonding layer. A second group of circuit structure is formed on a second temporary carrier. The second group of circuit structure includes multiple second circuit layers and a second bonding layer. The first group of circuit structure and the second group of circuit structure are directly bonded, so that the first bonding layer is bonded to the second bonding layer. A third group of circuit structure is formed on the second group of circuit structure. The third group of circuit structure includes multiple third circuit layers and a third bonding layer. The second group of circuit structure and the third group of circuit structure are bonded. The second group of circuit structure includes another bonding layer relative to the first group of circuit structure, and the another bonding layer is bonded to the third bonding layer to form a multilayer redistribution structure. 
     The manufacturing method of a semiconductor substrate structure of the disclosure includes at least the following process. A second group of circuit structure is formed on a second temporary carrier. A third group of circuit structure is formed on the second group of circuit structure. The second group of circuit structure and the third group of circuit structure are bonded. The second temporary carrier is removed. A first group of circuit structure is formed on a first temporary carrier. The first group of circuit structure and the second group of circuit structure are directly bonded. The first temporary carrier is removed. A conductive pillar and a conductive cap are formed on a surface of the first group of circuit structure, and an external terminal is formed on a surface of the third group of circuit structure. 
     The semiconductor substrate structure of the disclosure includes a first group of circuit structure and a second group of circuit structure. The second group of circuit structure is disposed on the first group of circuit structure and is electrically connected to the first group of circuit structure to form a multilayer redistribution structure. A dielectric layer in the first group of circuit structure and a dielectric layer in the second group of circuit structure are organic thin-films. 
     Based on the above, the disclosure first separately manufactures multiple groups of circuit structure on the temporary carrier, and then directly bonds and assembles the aforementioned multiple groups of circuit structure into a multilayer redistribution structure. In this way, compared with the multilayer redistribution structure produced continuously at one time, the warpage may be effectively reduced. Thus, the semiconductor substrate structure maintains better yield and electrical performance while having a multilayer redistribution structure. 
     In order to make the above-mentioned features and advantages of the disclosure comprehensible, embodiments accompanied with drawings are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  to  FIG.  1 I  are partial schematic cross-sectional views illustrating a manufacturing method of a semiconductor substrate structure according to some embodiments of the disclosure. 
         FIG.  1 J ,  FIG.  1 K  and  FIG.  1 L  are partial schematic cross-sectional views illustrating a manufacturing method of the first group of circuit structure of  FIG.  1 D  according to an alternative embodiment of the disclosure. 
         FIG.  1 M ,  FIG.  1 N , and  FIG.  1 O  are partial schematic cross-sectional views illustrating a semiconductor substrate structure according to another embodiments of the disclosure. 
         FIG.  1 P  is a schematic view illustrating a bonding of a semiconductor substrate structure according to some embodiments of the disclosure. 
         FIG.  1 Q  is a schematic view illustrating a semiconductor substrate structure after bonding according to some embodiments of the disclosure. 
         FIG.  1 R  is a schematic view illustrating a semiconductor substrate structure after bonding of a prior art. 
         FIG.  2 A  to  FIG.  2 D  are partial schematic cross-sectional views illustrating a manufacturing method of a semiconductor structure according to some other embodiments of the disclosure. 
         FIG.  2 E  is a partial manufacturing flowchart of a semiconductor structure according to some embodiments of the disclosure. 
         FIG.  2 F  is a partial schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the disclosure. 
         FIG.  3 A  is a partial schematic cross-sectional view illustrating a semiconductor structure according to some other embodiments of the disclosure. 
         FIG.  3 B  and  FIG.  3 C  are partial schematic cross-sectional views illustrating some specific embodiments of the connecting layer of  FIG.  3 A . 
         FIG.  4 A  is a partial schematic cross-sectional view illustrating a pitch of a circuit structure. 
         FIG.  4 B  is a partial schematic top view corresponding to  FIG.  4 A . 
         FIG.  5 A  is a partial manufacturing flowchart of a semiconductor substrate structure according to some embodiments of the disclosure. 
         FIG.  5 B  is a partial schematic cross-sectional view illustrating a semiconductor substrate structure according to some embodiments of the disclosure. 
     
    
    
     It should be noted that,  FIG.  3 B  and  FIG.  3 C  may be enlarged parts of the dotted frame in  FIG.  3 A . 
     DESCRIPTION OF THE EMBODIMENTS 
     Exemplary embodiments of the disclosure are described below comprehensively with reference to the figures, but the disclosure may also be implemented in different ways and should not be construed as limited to the embodiments described herein. In the drawings, for the sake of clarity, the size and thickness of various regions, parts, and layers may not be drawn to actual scale. In order to facilitate understanding, the same elements in the following description are described with the same symbols. 
     The disclosure is more comprehensively described with reference to the figures of this embodiment. However, the disclosure may also be implemented in various different forms, and is not limited to the embodiments in the present specification. Thicknesses, dimensions, and sizes of layers or regions in the drawings are exaggerated for clarity. The same reference numbers are used in the drawings and the description to indicate the same or like parts, which are not repeated in the following embodiments. 
     Directional terms (for example, upper, lower, right, left, front, back, top, and bottom) used herein only refer to the graphical use, and are not intended to imply absolute orientation. 
     It should be understood that, although the terms “first”, “second”, “third”, or the like may be used herein to describe various elements, components, regions, layers, and/or portions, these elements, components, regions, and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as that commonly understood by one of ordinary skill in the art to which this disclosure belongs. 
       FIG.  1 A  to  FIG.  1 I  are partial schematic cross-sectional views illustrating a manufacturing method of a semiconductor substrate structure according to some embodiments of the disclosure.  FIG.  1 J ,  FIG.  1 K  and  FIG.  1 L  are partial schematic cross-sectional views illustrating a manufacturing method of the first group of circuit structure of  FIG.  1 D  according to an alternative embodiment of the disclosure.  FIG.  1 M ,  FIG.  1 N , and  FIG.  1 O  are partial schematic cross-sectional views illustrating a semiconductor substrate structure according to another embodiments of the disclosure.  FIG.  1 P  is a schematic view illustrating a bonding of a semiconductor substrate structure according to some embodiments of the disclosure.  FIG.  1 Q  is a schematic view illustrating a semiconductor substrate structure after bonding according to some embodiments of the disclosure.  FIG.  1 R  is a schematic view illustrating a semiconductor substrate structure after bonding of a prior art. Referring to  FIG.  1 A , multiple first circuit layers  111  are formed on a first temporary carrier  10 . The first temporary carrier  10  may be made of glass, plastic, silicon, metal, or other suitable materials, as long as the material may withstand the subsequent process and simultaneously support the structure formed thereon. 
     In some embodiments, a first releasing layer  12  (e.g. a light-to-heat conversion film or other suitable releasing layer) may optionally be coated between the first temporary carrier  10  and a first group of circuit structure  110  for enhancing the peelability between the first temporary carrier  10  and the first group of circuit structure  110  in the subsequent process and improving the flatness of the first group of circuit structure  110 , but the disclosure is not limited thereto. 
     In this embodiment, multiple first circuit layers  111  (six layers are schematically depicted in  FIG.  1 A ) and a first micro bump  12   a  (subsequently used to form a first bonding member  112   a  as shown in  FIG.  1 D ) on the first circuit layer  111  may be formed on the first temporary carrier  10 . Each of the first circuit layers  111  may include a first conductive pattern  111   a , a first dielectric layer  111   b , and/or a first conductive through hole  111   c . The first conductive pattern  111   a  and the first conductive through hole  111   c  may be embedded in the first dielectric layer  111   b , and the first micro bump  12   a  may be electrically connected to the first circuit layer  111 , but the disclosure is not limited thereto. 
     In some embodiments, the first conductive pattern  111   a  may be formed on the first temporary carrier  10  using a deposition process, a lithography process, and an etching process or other suitable processes. Next, the first dielectric layer  111   b  including multiple openings may be formed on the first temporary carrier  10  using, for example, a coating process, a lithography etching process, or other suitable processes. The opening exposes at least a part of the first conductive pattern  111   a  for electrical connection. Then, a conductive material may be formed within the opening of the first dielectric layer  111   b  to form the first conductive through hole  111   c  using a suitable deposition process. Then, the above steps are performed multiple times to form multiple first circuit layers  111 . Thereafter, the first micro bump  12   a  may be formed using a suitable deposition process. It should be noted that the first group of circuit structure  110  shown in  FIG.  1 A  is merely an exemplary illustration, and more or fewer layers of the first circuit layers  111  may be formed according to circuit design requirements. As long as the first circuit layer  111  includes at least two layers, then the first circuit layer  111  belongs to the protection scope of the disclosure. 
     In some embodiments, the material of the first conductive pattern  111   a  and the first conductive through hole  111   c  may include copper, gold, nickel, aluminum, platinum, tin, combinations thereof, alloys thereof, or other suitable conductive materials. The material of the first dielectric layer  111   b  may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), inorganic dielectric materials (e.g., silicon oxide, silicon nitride) or other suitable electrical insulating materials, but the disclosure is not limited thereto. 
     Referring to  FIG.  1 B , a first connecting bump  12   b  is formed on the first micro bump  12   a . in the case of the material of the first micro bump  12   a  being substantially the same as the material of the first connecting bump  12   b , the first micro bump  12   a  and the first connecting bump  12   b  may not have a substantial interface, but the disclosure is not limited thereto. The material of the first micro bump  12   a  and the first connecting bump  12   b  may also be different. In addition, other film layers (e.g., seed crystal layer, not shown) may also be included between the first micro bump  12   a  and the first circuit layer  111 . 
     Referring to  FIG.  1 C  and  FIG.  1 D , a first bonding dielectric material layer  12   c  is formed to cover the first micro bump  12   a  and the first connecting bump  12   b . That is, a height of the first bonding dielectric material layer  12   c  is higher than a stacking height of the first micro bump  12   a  and the first connecting bump  12   b . Next, a planarization process (e.g., a grinding process, a chemical mechanical polishing process, or a combination thereof) is performed to form the first bonding member  112   a  and a first bonding dielectric layer  112   b . The first bonding member  112   a  and the first bonding dielectric layer  112   b  may be regarded as the first bonding layer  112 . Furthermore, the planarization process (grinding and polishing) may be performed with a grinding wheel  101  until a top surface of the first connecting bump  12   b  is exposed, so that top surfaces of the first bonding member  112   a  and the first bonding dielectric layer  112   b  form a coplanar. The first circuit layers  111  and the first bonding layer  112  may be regarded as the first group of circuit structure  110 . 
     In some embodiments, the first bonding member  112   a  may be formed by sequentially stacking a seed crystal layer of materials such as titanium/copper (Ti/Cu) and an electroplating layer of materials such as copper, but the disclosure is not limited thereto. In some other embodiments, the first bonding member  112   a  may include other suitable conductive materials such as silver, gold, nickel, or alloys thereof, for example, Cu, Cu/Ni/Au, Cu/Ti, Cu/Ag, or the like. A second layer of material such as titanium may be formed on a first layer of material such as copper, and then a third layer of material such as silver is formed on the second layer by electroplating, sputtering, or other suitable deposition methods. A thickness of the second layer may be smaller than a thickness of the third layer, but the disclosure is not limited thereto. In addition, the first bonding member  112   a  may be in a form of a pad or a conductive pillar. 
     In some embodiments, the first bonding dielectric layer  112   b  may be a two-stage curing material (e.g., polyimide). Thus, in this stage, the aforementioned material may be in a half-cured state by controlling the curing temperature and/or the process parameters. In this way, the first bonding dielectric layer  112   b  may have a certain extent of elasticity and softness at this stage, but the disclosure is not limited thereto, and the first bonding dielectric layer  112   b  may also be directly cured. 
     In this embodiment, the first group of circuit structure  110  includes a first surface  110   t  and a second surface  110   b  opposite to each other. The second surface  110   b  is close to the first temporary carrier  10 , and the first conductive pattern  111   a  and the first dielectric layer  111   b  on the second surface  110   b  may be substantially flush. In addition, the first conductive through hole  111   c  is gradually thicker toward a direction of the first bonding layers  112  (e.g., thicker in width or diameter). In other words, the first conductive through hole  111   c  is tapered toward a direction of the first temporary carrier  10  (e.g., tapered in width or diameter), but the disclosure is not limited thereto. 
     In some embodiments, distribution density of the first conductive pattern  111   a  on the second surface  110   b  of the first group of circuit structure  110  must be sufficient for subsequent mounting of semiconductor chips, but the disclosure is not limited thereto. 
     Referring to  FIG.  1 E , multiple second circuit layers  121  are formed on a second temporary carrier  20 . In this embodiment, multiple second circuit layers  121  (six layers are schematically depicted in  FIG.  1 E ) and a second micro bump  22   a  (subsequently used to form a second bonding member  122   a  as shown in  FIG.  1 H ) on the second circuit layer  121  may be formed on the second temporary carrier  20 . Each of the second circuit layers  121  may include a second conductive pattern  121   a , a second dielectric layer  121   b , and/or a second conductive through hole  121   c . The second conductive pattern  121   a  and the second conductive through hole  121   c  may be embedded in the second dielectric layer  121   b , and the second micro bump  22   a  may be electrically connected to the second circuit layer  121 , but the disclosure is not limited thereto. 
     Referring to  FIG.  1 F , a second connecting bump  22   b  is formed on the second micro bump  22   a . Other film layers (e.g., seed crystal layer, not shown) may also be included between the second micro bump  22   a  and the second circuit layer  121 . The material of the second micro bump  22   a  and the second connecting bump  22   b  are similar to the material of the first micro bump  12   a  and the first connecting bump  12   b , and details are not repeated herein. 
     Referring to  FIG.  1 G  and  FIG.  1 H , a second bonding dielectric material layer  22   c  is formed to cover the second micro bump  22   a  and the second connecting bump  22   b . That is, a height of the second bonding dielectric material layer  22   c  is higher than a stacking height of the second micro bump  22   a  and the second connecting bump  22   b . Next, a planarization process (e.g., a grinding process, a chemical mechanical polishing process, or a combination thereof) is performed to form the second bonding member  122   a  and a second bonding dielectric layer  122   b . The second bonding member  122   a  and the second bonding dielectric layer  122   b  may be regarded as the second bonding layer  122 . Furthermore, the planarization process (grinding and polishing) may be performed by the grinding wheel  101  until a top surface of the second connecting bump  22   b  is exposed, so that top surfaces of the second bonding member  122   a  and the second bonding dielectric layer  122   b  form a coplanar. The second circuit layers  121  and the second bonding layer may be regarded as a second group of circuit structure  120 . 
     In this embodiment, the second group of circuit structure  120  includes a third surface  120   t  and a fourth surface  120   b  opposite to each other. The fourth surface  120   b  is close to the second temporary carrier  20 , and the second conductive pattern  121   a  and the second dielectric layer  121   b  on the fourth surface  120   b  may be substantially flush. In addition, the second conductive through hole  121   c  is gradually thicker toward a direction of the second bonding layers  122  (e.g., thicker in width or diameter). In other words, the second conductive through hole  121   c  is tapered toward a direction of the second temporary carrier  20  (e.g., tapered in width or diameter), but the disclosure is not limited thereto. 
     In some embodiments, the first conductive pattern  121   a  of the fourth surface  120   b  of the second group of circuit structure  120  may be used for subsequent installation of a substrate or an external terminal, but the disclosure is not limited thereto. 
     In some embodiments, a dielectric layer in the first group of circuit structure  110  (e.g., the first dielectric layer  111   b  and the first bonding dielectric layer  112   b ) and a dielectric layer in the second group of circuit structure  120  (e.g., the second dielectric layer  121   b  and the second bonding dielectric layer  122   b ) are organic thin-films, but the disclosure is not limited thereto. 
     In some embodiments, a material of a dielectric layer in the first group of circuit structure  110  (e.g., the first dielectric layer  111   b  and the first bonding dielectric layer  112   b ) and a material of a dielectric layer in the second group of circuit structure  120  (e.g., the second dielectric layer  121   b  and the second bonding dielectric layer  122   b ) are the same (e.g., the dielectric (material) coefficients of thermal expansion are the same), but the disclosure is not limited thereto. In some other embodiments, the material of the dielectric layer in the first group of circuit structure  110  (e.g., the first dielectric layer  111   b  and the first bonding dielectric layer  112   b ) and the material of the dielectric layer in the second group of circuit structure  120  (e.g., the second dielectric layer  121   b  and the second bonding dielectric layer  122   b ) are different (e.g., the dielectric coefficients of thermal expansion are different), “different” may include similar but not identical. 
     In some embodiments, a difference between a dielectric coefficient of thermal expansion of the dielectric layer of the first group of circuit structure  110  (e.g., the first dielectric layer  111   b  and the first bonding dielectric layer  112   b ) and a dielectric coefficient of thermal expansion of the dielectric layer of the second group of circuit structure  120  (e.g., the second dielectric layer  121   b  and the second bonding dielectric layer  122   b ) may be less than 10%, but the disclosure is not limited thereto. 
     It should be noted that other specific details of forming the second group of circuit structure  120  (e.g., material, forming method, and setting of a second releasing layer  22 ) are similar to forming the first group of circuit structure  110 , and details are not repeated herein. 
     Referring to  FIG.  1 I , the structure shown in  FIG.  1 D  is flipped upside down. The first group of circuit structure  110  and the second group of circuit structure  120  are directly bonded, so that the first bonding layer  112  is bonded to the second bonding layer  122  to form a multilayer redistribution structure RDL. Through the above manufacturing process, a semiconductor substrate structure  100  of this embodiment has been substantially completed. The semiconductor substrate structure  100  of this embodiment includes a first group of circuit structure  110  and a second group of circuit structure  120 . The first group of circuit structure  110  includes multiple first circuit layers  111  and a first bonding layer  112 . The second group of circuit structure  120  includes multiple second circuit layers  121  and a second bonding layer  122 . The second group of circuit structure  120  is disposed on the first group of circuit structure  110  and is electrically connected to the first group of circuit structure  110 . The first bonding layer  112  is bonded to the second bonding layer  122  to form a multilayer redistribution structure RDL. Accordingly, in this embodiment, multiple groups of circuit structure (the first group of circuit structure  110  and the second group of circuit structure  120 ) are separately manufactured on temporary carriers (the first temporary carrier  10  and the second temporary carrier  20 ) respectively. Then, multiple groups of circuit structure are directly assembled into the multilayer redistribution structure RDL. In this way, compared with the multilayer redistribution structure produced continuously at one time, the warpage may be effectively reduced. Thus, the semiconductor substrate structure  100  maintains better yield and electrical performance while having multilayer redistribution structure RDL. 
     Furthermore, due to the limitations of the process, the difficulty is positively related to the number of layers to be produced. Therefore, the more layers to be made, the higher the chance that the entire multilayer redistribution structure is be damaged during the manufacturing process, resulting in ineffective control of yield and cost. In this embodiment, the multilayer redistribution structure RDL is divided into multiple groups of circuit structure with a smaller number of layers, which are produced separately. Thus, the problem of continuous stacking of multiple layers that cannot effectively control the yield and cost may be avoided, but the disclosure is not limited thereto. 
     In some embodiments, due to a difference between the coefficient of thermal expansion (CTE), warpage occurs, and the more layers are stacked, the more serious the situation is going to be. Therefore, in the case of the multilayer redistribution structure being made continuously at one time, the warpage accumulates and becomes larger, such as the multilayer redistribution structure  2  formed on the temporary carrier  1  as shown in  FIG.  1 R . In this embodiment, the multilayer redistribution structure RDL is divided into multiple groups of circuit structure (the first group of circuit structure  110  and the second group of circuit structure  120 ) and then manufactured separately. Thereafter, one of the groups is flipped upside down for bonding (afterwards, a bonding surface may be leveled by applying upward and downward pressure). In this way, stress may be effectively offset due to different warpage directions of upper and lower sides, thereby relieving the warpage, as shown in  FIG.  1 P  and  FIG.  1 Q . It should be noted that, in  FIG.  1 Q , the first temporary carrier  10  is not pressurized and is omitted for brevity. The warpage in  FIG.  1 P  to  FIG.  1 R  is merely an exemplary illustration and is not intended to limit the disclosure, and the actual warpage is subject to actual process conditions. 
     In some embodiments, direct bonding may be performed by Cu to Cu hybrid bonding or Cu to Cu direct bonding, so that the first bonding members  112   a  is in direct contact with the second bonding members  122   a , and the first bonding dielectric layer  112   b  is in direct contact with the second bonding dielectric layer  122   b . The first bonding member  112   a  and the second bonding member  122   a  may be bonded in a one-to-one manner, for example, the first bonding member  112   a  is substantially aligned with the second bonding member  122   a . However, due to the design of the process conditions, the first bonding member  112   a  may also be substantially partially staggered with the second bonding member  122   a . Since no welding material is used for bonding between the first bonding layer  112  and the second bonding layer  122 , the connection of the multilayer redistribution structure RDL may be regarded as a solderless connection. 
     In some embodiments, the finer the line distance/pitch (L/S) (e.g., line width), the more demanding the process requirements are and the more difficulties are encountered in forming a multilayer redistribution structure. However, compared with the continuously formed structures, the method of bonding and assembling multiple groups of circuit structure to make fine line distance/pitch structures in this embodiment has greater advantages in yield and electrical performance. For example, the first group of circuit structure  110  and the second group of circuit structure  120  may both have a fine line distance/pitch of at least less than 10 micrometers. Thus, after the first group of circuit structure  110  and the second group of circuit structure  120  are directly bonded and assembled, a multilayer redistribution structure RDL with fine line distance/pitch is formed, but the disclosure is not limited thereto. 
     In some embodiments, as shown in  FIG.  1 I , each of the first circuit layers  111  includes two adjacent first circuits, and a first pitch  111   s  is provided between center points of the two adjacent first circuits, each of the second circuit layers  121  includes two adjacent second circuits, and a second pitch  121   s  is provided between center points of the two adjacent second circuits, the first pitch  111   s  of each of the first circuit layers  111  is smaller than the second pitch  121   s  of each of the second circuit layers  121 , and the pitch of each layer gradually increases from the first group of circuit structure  110  to the second group of circuit structure  120 . For example, a direction from the second surface  110   b  of the first group of circuit structure  110  to the fourth surface  120   b  of the second group of circuit structure  120  which passes through the first surface  110   t  of the first group of circuit structure  110  and the third surface  120   t  of the second group of circuit structure  120 . The first surface  110   t  is bonded to the third surface  120   t . The first pitch  111   s  and the second pitch  121   s  are minimum pitches of each layer, but the disclosure is not limited thereto. In other embodiments, the first pitch  111   s  and the second pitch  121   s  may be an average pitch of each layer. 
       FIG.  4 A  is a partial schematic cross-sectional view illustrating a pitch of a circuit structure.  FIG.  4 B  is a partial schematic top view corresponding to  FIG.  4 A . Furthermore, as shown in  FIG.  4 A  and  FIG.  4 B , a fine pitch F and a thick pitch C may be provided in the circuit layer, and the pitch may be, for example, a distance between center points of two adjacent circuits. For example, the distance between the center points of two adjacent circuits L 1  is the fine pitch F, and the distance between the center points of two adjacent circuits L 2  is the thick pitch C. Alternatively, the pitch may be a distance between two adjacent pads. For example, the distance between center points of two adjacent pad P 1  is the fine pitch F, and the distance between center points of two adjacent pad P 2  is the thick pitch C. Thus, the aforementioned first pitch  111   s  and second pitch  121   s  may apply these designs according to actual design requirements, which is not limited in the disclosure. 
     In some embodiments, in the case that the first bonding dielectric layer  112   b  and the second bonding dielectric layer  122   b  are two-stage curing materials (e.g., polyimide), in the aforementioned bonding process, heat and/or force is applied to the first bonding layer  112  and the second bonding layer  122 . For example, a temperature greater than a glass transition temperature (Tg) of the first bonding layer  112  and the second bonding layer  122  may be applied to the bonding interface of the first bonding layer  112  and the second bonding layer  122 . Thus, the first bonding dielectric layer  112   b  and the second bonding dielectric layer  122   b  change from a half-cured state to a cured state at this stage, so that the bonding force between the first bonding layer  112  and the second bonding layer  122  is enhanced, but the disclosure is not limited thereto. 
     In some embodiments, a material of the first bonding dielectric layer  112   b  and a material of the second bonding dielectric layer  122   b  may be the same, so substantially no interface is be observed between the first bonding dielectric layer  112   b  and the second bonding dielectric layer  122   b , but the disclosure is not limited thereto. 
     In some embodiments, the first conductive through hole  111   c  is gradually thicker toward a direction of the first bonding layer  112  (e.g., thicker in width or diameter), and the second conductive through hole  112   c  is gradually thicker toward a direction of the second bonding layer  122  (e.g., thicker in width or diameter). In other words, the first conductive through hole  111   c  is tapered toward the direction of the first temporary carrier  10  (e.g., tapered in width or diameter), and the second conductive through hole  112   c  is tapered toward the direction of the second temporary carrier  20  (e.g., tapered in width or diameter). That is, after the bonding process, a tapered direction of the first conductive through hole  111   c  is opposite to a tapered direction of the second conductive through hole  112   c.    
     It should be noted that, according to actual application requirements, the first temporary carrier  10  and/or the second temporary carrier  20  may be optionally removed to expose the first conductive pattern  111   a  and/or the second conductive pattern  121   a  and electrically connect with other elements. The releasing layer may be peeled off by applying external energy between a bottom surface of the circuit structure and the temporary carrier. 
     Referring to  FIG.  1 J  to  FIG.  1 L , in the alternative embodiment, the first bonding layer  112  may use other manufacturing methods. First, a first photosensitive dielectric layer  12   d  may be formed on the first circuit layers  111 . Next, the first photosensitive dielectric layer  12   d  is patterned by a lithographic tool such as a stepper and the first photosensitive dielectric layer  12   d  is cured to form multiple openings  12   e  exposing the first circuit layer  111  below, as shown in  FIG.  1 J . Next, a first seed crystal layer  12   f  is formed to cover the first photosensitive dielectric layer  12   d  patterned, and the openings  12   e  are filled by a part of the first seed crystal layer  12   f , as shown in  FIG.  1 K . Thereafter, a first metal layer  12   g  is formed by performing an electroplating process. Top surfaces of a first bonding member  112   a  and a first bonding dielectric layer  112   b  are a coplanar formed by performing a planarization process with a grinding wheel  101 . It should be noted that, for the sake of brevity, the second bonding layer  122  may be formed using a manufacturing method similar to the above, which is not shown here. For example, a second photosensitive dielectric layer is formed on the second circuit layers  122 . The second photosensitive dielectric layer is patterned and the second photosensitive dielectric layer is cured to form the openings exposing the second circuit layer  122  below. A second seed crystal layer is formed to cover the second photosensitive dielectric layer patterned, and the openings are filled by a part of the second seed crystal layer. A second metal layer is formed by performing an electroplating process. Top surfaces of a second bonding member  122   a  and a second bonding dielectric layer  122   b  are a coplanar formed by performing a planarization process with a grinding wheel  101 . 
     In some embodiments, a material of the first seed crystal layer  12   f  is, for example, Ti (which a thickness of, for example, 0.1 micrometer)/Cu (with a thickness of, for example, 0.3 micrometer). A material of the first metal layer  12   g  is, for example, Cu, but the disclosure is not limited thereto. 
     In some embodiments, a number of groups of circuit structure may not be limited to two groups. For example, the multilayer redistribution structure RDL 1  of the semiconductor substrate structure  100 A shown in  FIG.  1 M  may further include a third group of circuit structure  130 , the third group of circuit structure  130  includes multiple third circuit layers  131  and a third bonding layer  132 . Furthermore, the second group of circuit structure  120  is disposed between the first group of circuit structure  110  and the third group of circuit structure  130  and are electrically connected with each other. The second group of circuit structure  120  includes another bonding layer  123  relative to the first group of circuit structure, and the another bonding layer  123  is bonded to the third bonding layer  132  to form a multilayer redistribution structure. In addition, the third group of circuit structure  130  includes a fifth surface  130   t  and a sixth surface  130   b  opposite to each other. 
     In addition, the semiconductor substrate structure  100 A may be a continuation of  FIG.  1 H , with the second temporary carrier  20  and the second releasing layer  22  removed, the third group of circuit structure  130  on the third temporary carrier  30  and the third releasing layer  32  are bonded to the second group of circuit structure  110  to form a multilayer redistribution structure RDL 1 , but the disclosure is not limited thereto. 
     In some embodiments, a number of the first circuit layer  111  of the first group of circuit structure  110  (six-layer structure) is the same as a number of the second circuit layer  121  of the second group of circuit structure  120  (six-layer structure), but different embodiments may also be provided. For example, in the semiconductor substrate structure  100 A shown in  FIG.  1 M , the number of the first circuit layer  111  of the first group of circuit structure  110  and the number of the second circuit layer  121  of the second group of circuit structure  120  are different from a number of the third group of circuit structure  130  (five-layer structure), the aforementioned difference in number may be one layer or two layers, but the disclosure is not limited thereto. 
     In some embodiments, a thickness of the first circuit layer  111  of the first group of circuit structure  110  (six-layer structure) is the same as a thickness of the second circuit layer  121  of the second group of circuit structure  120  (six-layer structure), but different embodiments may also be provided. For example, in the semiconductor substrate structure  100 B shown in  FIG.  1 N , the thickness of the first circuit layer  111  of the first group of circuit structure  110  and the thickness of the second circuit layer  121  of the second group of circuit structure  120  are different from a thickness of a third group of circuit structure  130 B. The thickness of the third group of circuit structure  130 B may be twice the thickness of the first circuit layer  111  or the thickness of the second circuit layer  121  of the second group of circuit structure  120  to form a multilayer redistribution structure RDL 2 . In addition, in this embodiment, the second group of circuit structure  120  and the third group of circuit structure  130 B are bonded using Cu to Cu hybrid bonding or Cu to Cu direct bonding, but the disclosure is not limited thereto. In other embodiments, such as the semiconductor substrate structure  100 C shown in  FIG.  1 O , solder  124  and solder  134  may be used for bonding between the second group of circuit structure  120  and the third group of circuit structure  130 B to form a multilayer redistribution structure RDL 3 , but the disclosure is not limited thereto. 
     In some embodiments, as shown in  FIG.  1 M  and  FIG.  1 N , each of the third circuit layers  131  of the third group of circuit structure includes two adjacent second circuits, and a third pitch  131   s  is provided between center points of the two adjacent third circuits, the third pitch  131   s  is greater than the first pitch  111   s  and the second pitch  121   s , and the pitch of each layer gradually increases from the first group of circuit structure  110  to the third group of circuit structure  130 . For example, a direction from the second surface  110   b  of the first group of circuit structure  110  to the sixth surface  130   b  of the third group of circuit structure  130  which passes through the first surface  110   t  of the first group of circuit structure  110 , the third surface  120   t  of the second group of circuit structure  120 , the fourth surface  120   b  of the second group of circuit structure  120 , and the fifth surface  130   t  of the third group of circuit structure  130 . The fourth surface  120   b  is bonded to the fifth surface  130   t . In addition, a dielectric coefficient of thermal expansion (CTE) of the third bonding layer  132  is smaller than a dielectric coefficient of thermal expansion of the first bonding layer  112  and a dielectric coefficient of thermal expansion of the second bonding layer  122 , but the disclosure is not limited thereto. 
     It is to be noted that the following embodiments use the reference numerals and a part of the contents of the above embodiment, and the same or similar reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the above embodiments, and details are not described in the following embodiments. 
       FIG.  2 A  to  FIG.  2 D  are partial schematic cross-sectional views illustrating a manufacturing method of a semiconductor structure according to some other embodiments of the disclosure.  FIG.  2 E  is a partial manufacturing flowchart of a semiconductor structure according to some embodiments of the disclosure.  FIG.  2 F  is a partial schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the disclosure. Referring to  FIG.  2 A  and  FIG.  2 E , as a continuation of  FIG.  1 E , after the first group of circuit structure and the second group of circuit structure are assembled (step S 110 ), the first temporary carrier is removed by a first releasing layer (step S 120 ). For example, the manufacturing method of the semiconductor substrate structure may further remove the first releasing layer  12  and the first temporary carrier  10  (e.g., by a laser process, and the remaining first releasing layer  12  may be removed by plasma process) to expose the first conductive pattern  111   a  and the first dielectric layer  111   b  (which may be regarded as a chip end of the multilayer redistribution structure RDL) of the second surface  110   b  of the first group of circuit structure  110 . Next, after removing the first temporary carrier  10 , multiple conductive connecting members are formed on the first group of circuit structure (step S 130 ). For example, multiple conductive connecting members  240  may be formed on the first conductive pattern  111   a  of the second surface  110   b  of the first group of circuit structure  110 . The conductive connecting members  240  includes a conductive pillar  241  and a conductive cap  242  formed thereon. The conductive pillar  241  may be made of copper, and the conductive cap  242  may be made of solder, but the disclosure is not limited thereto. The conductive pillar  241  and the conductive cap  242  may also be made of other suitable materials. For example, the conductive cap  242  may be a Sn/Ag lead-free solder. Through the above manufacturing process, another semiconductor substrate structure for electrically connecting the semiconductor chip and the external terminal may be completed, but the disclosure is not limited thereto. 
     In some embodiments, adjacent conductive connecting members  240  may have fine pitches to correspond to chips to be mounted later, but the disclosure is not limited thereto. 
     Referring to  FIG.  2 B  and  FIG.  2 E , the semiconductor chip is bonded to the semiconductor substrate structure (step S 140 ). For example, a semiconductor chip  301  may be connected to the second surface  110   b  of the first group of circuit structure  110  using, for example, flip chip bonding. For example, a conductive bump  302  of the semiconductor chip  301  (which may further include solder) may be bonded to the conductive cap  242  of the conductive connecting member  240 . In other words, the conductive bump  302  of the semiconductor chip  301  may be in direct contact with the conductive cap  242  of the conductive connecting member  240  to form a heterogeneous integration module or system. Furthermore, the semiconductor chip  301  may be bonded to the second group of circuit structure  120  by thermal compression bonding. 
     In some embodiments, the semiconductor chip  301  is, for example, a logic chip, a memory chip, a three-dimensional integrated circuit (3DIC) chip (e.g., a high bandwidth memory chip), and/or the like. The 3DIC chip includes multiple layers stacked on each other, and silicon vias (TSVs) are formed to provide vertical electrical connection between the layers, but the disclosure is not limited thereto. 
     In some embodiments, a height  302   h  of the conductive bump  302  may be greater than a height  240   h  of the corresponding conductive connecting member  240 , but the disclosure is not limited thereto. The height  302   h  of the conductive bump  302  and the height  240   h  of the conductive connecting member  240  may be determined according to actual design requirements. 
     In some embodiments, an underfill is formed on the semiconductor substrate structure (step S 150 ). For example, an underfill  40  may be formed on the second surface  110   b  of the first group of circuit structure  110  to fill the gap between the second surface  110   b  and the semiconductor chip  301 , thereby enhancing the reliability of the flip chip bonding. In some embodiments, more than one semiconductor chip  301  performing the same or different functions may be provided on the first group of circuit structure  110 . In this case, the semiconductor chips  301  may be electrically connected to the first group of circuit structure  110  and to each other through the first group of circuit structure  110 . The number of semiconductor chips  301  disposed on the first group of circuit structure  110  does not constitute limitation to the disclosure. 
     Referring to  FIG.  2 C  and  FIG.  2 E , the semiconductor substrate structure and the semiconductor chip are encapsulated (step S 160 ). For example, a sealing body  250  is formed on the second surface  110   b  of the first group of circuit structure  110  to encapsulate the semiconductor chip  301  and the underfill  40 . The sealing body  250  may be a molding compound formed by a molding process. The sealing body  250  may be formed of an insulating material such as epoxy resin or other suitable resins, but the disclosure is not limited thereto. 
     Referring to  FIG.  2 D  and  FIG.  2 E , the second releasing layer and the second temporary carrier are removed (step S 170 ). For example, the second releasing layer  22  and the second temporary carrier  20  are removed to expose the second conductive pattern  121   a  and the second dielectric layer  121   b  of the fourth surface  120   b  of the second group of circuit structure  120  (which may be regarded as a terminal end of the multilayer redistribution structure RDL). Thereafter, the external terminal is formed on the second group of circuit structure (step S 180 ). For example, a bottom connection pad may be formed by metallization on the second conductive pattern  121   a , and solder may be formed on the bottom connection pad, so as to form multiple external terminals  260  on the terminal end of the multilayer redistribution structure RDL. The second group of circuit structure  120  is disposed between the external terminal  260  and the first group of circuit structure  110 , and the external terminal  260  is electrically connected to the second group of circuit structure  120 . Through the above manufacturing process, a semiconductor structure  200  of this embodiment has been substantially completed. 
     In some embodiments, as shown in  FIG.  2 F , after removing the second releasing layer  22  and the second temporary carrier  20 , a third group of circuit structure  130  may be further formed, and then the external terminal is formed on the third group of circuit structure  130  to complete the semiconductor structure  200 A. Details of material and formation method of the third group of circuit structure  130  are similar to those described in  FIG.  1 M  and  FIG.  2 D , and details are not repeated herein. 
     In some embodiments, the external terminal  260  may be a solder ball, and may be formed using a balling process to be placed on the second conductive pattern  121   a  of the second group of circuit structure  120 . A soldering process and a reflow process may be selectively performed to enhance the adhesion between the external terminal  260  and the second conductive pattern  121   a , but the disclosure is not limited thereto. 
     In a not-shown embodiment, the semiconductor structure  200  may be further disposed on a circuit carrier (e.g., a printed circuit board (PCB), a system board, a motherboard), a package and/or other elements to form an electronic device. For example, the external terminal  260  is disposed on the circuit carrier, and the semiconductor chip  301  is electrically connected to the circuit carrier or other elements in the circuit carrier through the multilayer redistribution structure RDL, but the disclosure is not limited thereto. 
     In some embodiments, the semiconductor structure  200  is a wafer level semiconductor packaging structure, but the disclosure is not limited thereto. 
       FIG.  3 A  is a partial schematic cross-sectional view illustrating a semiconductor structure according to some other embodiments of the disclosure.  FIG.  3 B  and  FIG.  3 C  are partial schematic cross-sectional views illustrating some specific embodiments of the connecting layer of  FIG.  3 A . Referring to  FIG.  3 A , compared with the semiconductor structure  200  of  FIG.  2 D , the semiconductor structure  300  of this embodiment further includes a connecting layer  370  and a substrate  380  between the multilayer redistribution structure RDL and the external terminal  260 . The multilayer redistribution structure RDL is coupled to the substrate  380  through the connecting layer  370  (the multilayer redistribution structure RDL and the substrate  380  may be collectively referred to as a 2.2D integrated substrate). The substrate  380  may be a ceramic substrate, a laminated organic substrate, a packaged substrate, an integrated substrate, or the like. 
     In some embodiments, the connecting layer  370  may connect with other elements by using solder. For example, as shown in  FIG.  3 B , the connecting layer  370  may include a copper pad  371  (which may also be a copper pillar) in direct contact with the multilayer redistribution structure RDL, a copper pad  372  in direct contact with the substrate  380 , and a solder  373  disposed between the copper pad  371  and the copper pad  372 . A surface of the copper pad  372  may be composed of Cu/Ni/Au and may also be surrounded by a solder mask  374  to improve electrical performance, but the disclosure is not limited thereto. Solderless connections may also be used between the connecting layer  370  and other elements. For example, as shown in  FIG.  3 C , a connection method of the connecting layer  370  is, for example, hybrid bonding or Cu to Cu direct bonding. The connecting layer  370  may include the copper pad  371  in direct contact with the multilayer redistribution structure RDL and the copper pad  372  in direct contact with the substrate  380 . The copper pad  371  and the copper pad  372  may be in direct contact with and bonded together, but the disclosure is not limited thereto. 
     In some embodiments, the substrate  380  includes a core layer  381 , a build-up structure  382 , and multiple vias  381   a . The build-up structure  382  is respectively formed on two sides of the core layer  381 , and the vias  381   a  penetrate through the core layer  381  to electrically connect the build-up structure  382  on both sides. The build-up structure  382  includes a conductive pattern  382   a  embedded in the dielectric layer, but the disclosure is not limited thereto. In a not-shown embodiment, the substrate  380  may not have the core layer  381 . 
       FIG.  5 A  is a partial manufacturing flowchart of a semiconductor substrate structure according to some embodiments of the disclosure.  FIG.  5 B  is a partial schematic cross-sectional view illustrating a semiconductor substrate structure according to some embodiments of the disclosure. Referring to  FIG.  2 A ,  FIG.  2 F ,  FIG.  5 A , and  FIG.  5 B , the semiconductor substrate structure  100 D of this embodiment may have different manufacturing method which includes the following steps. A second group of circuit structure disposed on the second temporary carrier is provided, and the third group of circuit structure and the second group of circuit structure are bonded (step S 210 ). The second temporary carrier is removed (step S 220 ). A first group of circuit structure disposed on the first temporary carrier is bonded to the second group of circuit structure (step S 230 ). The first temporary carrier is removed (step S 240 ). A conductive pillar and a conductive cap are formed on a surface of the first group of circuit structure, and an external terminal is formed on a surface of the third group of circuit structure (step S 250 ). Through the above manufacturing process, a semiconductor structure  100 D of this embodiment has been substantially completed. 
     In this embodiment, the manufacturing method of the semiconductor structure  100 D may also correspond to the following steps. A second group of circuit structure is formed on a second temporary carrier. A third group of circuit structure is formed on the second group of circuit structure. The second group of circuit structure and the third group of circuit structure are bonded. The second temporary carrier is removed. A first group of circuit structure is formed on a first temporary carrier. The first group of circuit structure and the second group of circuit structure are directly bonded. The first temporary carrier is removed. A conductive pillar and a conductive cap are formed on a surface of the first group of circuit structure, and an external terminal is formed on a surface of the third group of circuit structure. 
     In this embodiment, the semiconductor structure  100 D includes a multilayer redistribution structure RDL 1  formed by a first group of circuit structure  110 , a second group of circuit structure  120 , and a third group of circuit structure  130 . The conductive pillar  241  and the conductive cap  242  are formed on the second surface  110   b  of the first group of circuit structure  110 . The external terminal  260  is formed on the sixth surface  130   b  of the third group of circuit structure  130 . The third group of circuit structure  130  is not disposed on a temporary carrier during manufacturing process and is a plate-like structure with support, but the disclosure is not limited thereto. The same or similar reference numerals are used to denote the same or similar elements, so details may be referred to the foregoing embodiments and are not repeated herein. 
     It should be noted that the different embodiment described above may be combined in different ways, and it is not a limitation of this case. As long as multiple groups of circuit structure are individually manufactured and then assembled into a multilayer redistribution structure, they all belong to the protection scope of the disclosure. In addition, temporary carriers (e.g., the first temporary carrier, the second temporary carrier, the third temporary carrier, or other temporary carriers used in the process) form no part of the final structure. 
     To sum up, the disclosure first separately manufactures multiple groups of circuit structure on the temporary carrier, and then bonds and assembles the aforementioned multiple groups of circuit structure into a multilayer redistribution structure. In this way, compared with the multilayer redistribution structure produced continuously at one time, the warpage may be effectively reduced. Thus, the semiconductor substrate structure maintains better yield and electrical performance while having multilayer redistribution structure. 
     Although the disclosure has been described in detail with reference to the above embodiments, they are not intended to limit the disclosure. Those skilled in the art should understand that it is possible to make changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the disclosure shall be defined by the following claims.