Patent Publication Number: US-8995596-B1

Title: Techniques for calibrating a clock signal

Description:
BACKGROUND 
     Integrated circuits usually include circuitry and multiple logic blocks that may be configured to perform any of a variety of functions. Programmable integrated circuit devices such as field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., may include logic blocks or elements that can be configured to perform desired functions based on different user designs. 
     Apart from internal logic blocks that may be used to implement or perform different user functions, a programmable logic device generally includes input-output blocks or high-speed transceiver channel blocks that may be used to communicate with other components coupled to the programmable logic device through various input-output protocols. 
     As an example, the programmable logic device and any external components coupled to it may be part of a passive optical network (PON) structure. In general, a PON structure is a point-to-multipoint network architecture that allows a single provider node, commonly known as an optical line terminal (OLT), to serve multiple user nodes, commonly known as optical network terminals (ONUs). As such, the programmable device may be configured to implement a high speed communication protocol such as a Gigabit Passive Optical Network (GPON) protocol to communicate with any of the external components coupled to it. 
     However, several limitations need to be addressed when implementing a high speed communication protocol, such as the GPON protocol, in a programmable logic device. Some of the common challenges when implementing high speed communication protocols include, among others, long dead time, multiple phase shifts, and short recovery time. These problems arise partly because a clock data recovery circuit is generally used to recover a clock signal from an incoming data stream and the clock data recovery circuit in the programmable device may not be able to lock to the incoming clock signal within a relatively short period of time. 
     Incoming data may be lost if the clock data recovery circuit is not able to lock to the incoming clock signal within a single data frame. Moreover, different components or devices coupled to the programmable device may send data to the programmable device at different phases even though they may all operate at the same frequency. Therefore, information may be lost as incoming data may not be accurately sampled by the device. 
     SUMMARY 
     In order to fully support a high speed communication protocol, such as the GPON protocol, a programmable device may need to be able to lock to the clock signal of an incoming data stream in a relatively short period of time. Embodiments of the present invention include techniques to calibrate a clock signal in an integrated circuit in response to an incoming data stream. 
     It is appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method on a computer readable medium. Several inventive embodiments of the present invention are described below. 
     In one embodiment, a method is disclosed. The method includes receiving a data packet with a first operating frequency rate using first and second receiver circuits. The data packet includes a plurality of preamble bits. The first and second receiver circuits may operate at second and third operating frequency rates, respectively. A portion of the data packet received at the first receiver circuit is transmitted to a control circuit. The plurality of preamble bits within the portion of the data packet is identified with the control circuit. A clock circuit is calibrated based on the identified preamble bits. The first and second receiver circuits may be clocked with first and second clock outputs from the clock circuit. 
     In another embodiment, another method is disclosed. The method includes receiving a data stream from an external component and checking the data stream with an error checking circuit for a plurality of valid preamble bits. At least one edge of a data window associated with a first bit of the plurality of valid preamble bits is identified. An edge of a first clock output of a clock circuit is adjusted to a center of the data window associated with the first bit of the plurality of preamble bits. An edge of a second clock output of the clock circuit is adjusted to a center of a data window associated with a second bit of the plurality of preamble bits. 
     In yet another embodiment, an integrated circuit is disclosed. The integrated circuit includes a first receiver circuit operable to receive a data stream with a plurality of preamble bits at a first operating frequency rate. The integrated circuit also includes a clock circuit with first and second clock outputs. The first clock output of a clock circuit is coupled to the first receiver circuit. An output of a calibration circuit is coupled to an input terminal of the clock circuit. The calibration circuit is coupled to receive the data stream from the first receiver circuit. The calibration circuit may be operable to tune the first and second clock outputs from the clock circuit based on the plurality of preamble bits. 
     Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified block diagram of an illustrative integrated circuit receiving a data stream from an external component in accordance with an embodiment of the present invention. 
         FIG. 2  is a schematic diagram of an illustrative integrated circuit with receiver circuits, a calibration control circuit, and a clock switching and assembler circuit in accordance with an embodiment of the present invention. 
         FIG. 3  is a simplified method flow chart of illustrative steps involved in operating an integrated circuit in accordance with an embodiment of the present invention. 
         FIG. 4  is a simplified method flow chart of illustrative steps involved in calibrating a clock circuit in accordance with an embodiment of the present invention. 
         FIG. 5  is a simplified block diagram of an illustrative integrated circuit in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments provided herein include circuitry and techniques to calibrate a clock signal in an integrated circuit. 
     It will be obvious, however, to one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments. 
     Generally, an integrated circuit device may be connected to other external circuitry such as other integrated circuit devices, memory modules, etc. and signals may travel from the integrated circuit to the external circuitry coupled to it and vice versa. For instance, an integrated circuit device may be placed on a printed circuit board with other components coupled to the integrated circuit through conductive pathways. 
     High speed signals with different phases may travel between the integrated circuit device and other components. In order to receive incoming data from different components, the integrated circuit device may need to be properly calibrated. It is therefore desirable to have a technique to properly calibrate the integrated circuit device and align clock signals in the integrated circuit device to incoming data streams when receiving high speed data streams from multiple external components, each operating at a different clock phase or frequency. 
     One of the embodiments describes a method to implement a high speed input-output protocol such as a Gigabit Passive Optical Network (GPON) protocol with multiple input-output circuits on an integrated circuit device. It should be appreciated that even though a GPON protocol is used herein as an exemplary embodiment, the techniques described herein may be applicable to other input-output protocols. 
     Instead of using a clock data recovery circuit, which may not be able to appropriately recover a clock signal from an incoming data stream within a specific amount of time, a calibrated phase-locked loop circuit is used to clock the incoming data stream, according to one embodiment. A calibration control circuit may be used to align the phases of clock outputs from the phase-locked loop circuit to the incoming data stream. 
       FIG. 1 , meant to be illustrative and not limiting, shows block diagram of integrated circuit  100  receiving data stream  101  from an external component in accordance with one embodiment of the present invention. It should be appreciated that the integrated circuit may be placed on a printed circuit board and may be coupled to other components on the printed circuit board. 
     In the embodiment of  FIG. 1 , data stream  101  from an external component may be split into two separate channels,  101 A and  101 B. In an exemplary embodiment, the two separate channels,  101 A and  101 B, may be two separate traces coupled together. The two channels  101 A and  101 B may be coupled to two receiver circuits  102 A and  102 B, respectively, in the peripheral region of integrated circuit  100 . 
     In one embodiment, each of receiver circuits  102 A and  102 B may be a differential receiver circuit such as a low voltage differential signal (LVDS) circuit. It should be appreciated that the frequency rate of data streams from the external component may be different than the operating frequency rates of receiver circuits  102 A and  102 B. For instance, the data stream from the printed circuit board may be a high-speed data stream, such as a Gigabit Passive Optical Network (GPON) data stream, operating at 2.5 gigabit per second (Gbps) while each of receiver circuits  102 A and  120 B may be a differential input circuit operating at 1.25 gigahertz (GHz). It should be appreciated that even though only two receiver circuits  102 A and  102 B are shown in the embodiment of  FIG. 1 , data streams from the printed circuit board may be split into any number of channels and more receiver circuits may be used in this context. 
     Receiver circuit  102 A may transmit the received data stream to calibration control circuit  110  while both receiver circuits,  102 A and  102 B, may transmit the received data stream to clock switching and assembler circuit  120 . It should be appreciated that receiver circuits  102 A and  102 B may include input buffers on the peripheral region of the integrated circuit that may be used to receive signals from external components coupled to the integrated circuit and transmit the signals to circuit blocks in the core region of the integrated circuit (e.g., calibration circuit  110 , and clock switching and assembler circuit  120 ). A more detailed description of the calibration circuit  110  and the clock switching and assembler circuit  120  will be described later with reference to circuit  200  of  FIG. 2 , in the core region of the integrated circuit. In one embodiment, calibration control circuit  110  may calibrate clock circuit  150  on the integrated circuit to match a clock phase of the data stream received by receiver circuits  102 A and  102 B. In an exemplary embodiment, clock circuit  150  may be a phase-locked loop (PLL) circuit operable to provide clock signals at different phases to receiver circuits  102 A and  102 B. 
     Accordingly, clock circuit  150  may also provide clock switching and assembler circuit  120  with a clock signal that matches the phase of the data streams from receiver circuits  102 A and  102 B. Clock switching and assembler circuit  120  may then merge the two data streams from  102 A and  102 B as a single data stream before transmitting it to user logic block  130 . It should be appreciated that user logic block  130  may represent circuitry in the integrated circuit that may be used to implement desired user functions. 
       FIG. 2 , meant to be illustrative and not limiting, shows circuit  200  with a more detailed representation of receiver circuits  102 A and  102 B, calibration control circuit  110 , and clock switching and assembler circuit  120  in accordance with one embodiment of the present invention. Each of receiver circuits  102 A and  102 B may include a buffer circuit coupled to a deserializer circuit. For instance, in the embodiment of  FIG. 2 , buffer circuits  103 A and  103 B are coupled to deserializer circuits  106 A and  106 B, respectively. Signals received by deserializer circuits  106 A and  106 B may be clocked by phase-locked loop (PLL) circuit  150 . 
     Outputs from receiver circuits  102 A and  102 B are clock switching and assembler circuit  120 . Output from receiver circuit  102 A may be further coupled to calibration control circuit  110 . In one embodiment, calibration control circuit  110  may include error checker block  112 , pattern checker block  114 , and PLL reconfiguration block  116  coupled to status monitor and control block  118 . Clock switching and assembler circuit  120  may include assembler circuit  125  and may include storage circuits  123 A and  123 B, which may be coupled to receive outputs from receiver circuits  102 A and  102 B respectively. 
     In the embodiment of  FIG. 2 , receiver circuits  102 A and  102   b , and PLL circuit  150  may be “hard” circuit elements on a periphery region of an integrated circuit device while calibration control circuit  110  and clock switching and assembler circuit  120  may be “soft” logic blocks on a core region of the integrated circuit device. It should be appreciated that “hard” circuit elements may be actual circuit elements on the integrated circuit device that may be used to perform specific functions while “soft” logic blocks may be formed by clusters of logic elements (e.g., look-up tables, etc.) to implement any of a variety of functions. 
     In one embodiment, as the integrated circuit device is powered up, status monitor and control block  118  may be used to activate a calibration process within the integrated circuit device. In an exemplary embodiment, status monitor and control block  118  may include a state machine configured to initiate and control a calibration operation within the integrated circuit device. In the embodiment of  FIG. 2 , status monitor and control block  118  and PLL reconfiguration block  116  may be clocked by calibration clock signal  105 . It should be appreciated that calibration clock signal  105  may be slower than or similar to system reference clock signal  151 . In one embodiment, the clock rate of calibration clock signal  105  depends on the speed of status monitor and control block  118  and PLL reconfiguration block  116 . 
     Data stream  101 , received at receiver circuits  102 A and  102 B, may be transmitted to error checker circuit  112 . In one embodiment, data stream  101  may include a preamble signal or a training pattern transmitted from an external component to the integrated circuit. In the embodiment of  FIG. 2 , data stream  101  may be received by buffers  103 A and  103 B and transmitted, respectively, to deserializer circuits  106 A and  106 B. Data stream  101  may be a serial data stream and deserializer circuits  106 A and  106 B may be operable to convert data stream  101  to parallel data streams  108 A and  108 B, respectively. 
     A clock terminal of each of deserializer circuits  106 A and  106 B may be coupled to receive clock signals  152 S and  154 S, respectively, from PLL circuit  150 . PLL circuit  150 , in turn, may be coupled to system reference clock signal  151 . In an exemplary embodiment, data stream  101  may have a data transfer rate of 2.5 Gbps and PLL circuit  150  may operate at a clock rate of 1.25 GHz. Accordingly, for every clock cycle, i.e., from one rising edge to a next rising edge or from one falling edge to a next falling edge, each of receiver circuits  102 A and  102 B may receive two data bits from data stream  101 . 
     However, as deserializer circuits  106 A and  106 B may only capture one bit of data either at every rising edge or falling edge, one of the two data bits received from data stream  101  may be lost, by each deserializer circuit, at every clock cycle. As such, in an exemplary embodiment, clock signal  154 S, coupled to deserializer circuit  106 B, may be phase shifted by 180 degrees relative to clock signal  152 S that is coupled to deserializer circuit  106 A, such that deserializer circuit  106 A captures the data bit lost in each clock cycle by deserializer circuit  106 B and that deserializer circuit  106 B captures the data bit lost in each clock cycle by deserializer circuit  106 A (e.g., so that no data bits in incoming data stream  101  are lost). 
     Accordingly, deserializer circuit  106 A may be used to capture the first of the two data bits received at every clock cycle and deserializer circuit  106 B may be used to capture the remaining data bit. As such, even though each of receiver circuits  102 A and  102 B may operate at a lower speed compared to the data transfer rate of data stream  101 , data stream  101  may still be fully captured by using two receiver circuits,  102 A and  102 B, operating in parallel and phase shifted from each other. It should be appreciated that even though two receiver circuits  102 A and  102 B are shown in the embodiment of  FIG. 2 , depending on the data transfer rate of data stream  101  and the speed of system reference clock signal  151 , fewer or more receiver circuits that are appropriately phase shifted from each other may be used. 
     In one embodiment, once a calibration operation has been initiated, error checker circuit  112  may begin checking parallel data stream  108 A received from deserializer circuit  106 A for valid data (e.g., for valid preamble bits). In the embodiment of  FIG. 2 , error checker circuit  112 , which may sometimes be referred to herein as a bit error rate tester, may be coupled to receive parallel clock signal  152 P from PLL circuit  150 . It should be appreciated that parallel clock signals  152 P and  154 P may be substantially slower than their respective serial clock signals,  152 S and  154 S. For instance, serial clock signal  152 S may be at 1.25 GHz and parallel clock signal  152 P may be at 125 MHz. 
     If error checker circuit  112  does not detect valid data in the sampled parallel data stream  108 A (e.g., if circuit  112  detects random noise, which indicates either than no data is being received or that the phases of the clocks output by PLL circuit  150  are not aligned with the phase of incoming data signals), error checker circuit  112  may output error flag signal  113  and, in response, control circuitry  118  may provide control signals  119  to PLL reconfiguration block  116  that directs PLL reconfiguration block  116  to reconfigure PLL circuit  150  to adjust the phases of its clock outputs to another phase (e.g., to the next phase). These processes (e.g., which cycle the phases of PLL circuit  150  through the available phases) may continue until error checker circuit  112  detects valid data (e.g., until the phases of the clocks output by PLL circuit  150  may the phase of incoming data and the incoming data is valid data, rather than random noise). 
     Status monitor and control block  118  may receive error flag signal  113  through a status input terminal that is coupled to an output terminal of error checker circuit  112 . Status monitor and control block  118  may then transmit appropriate control signals, control signals  119 , to PLL reconfiguration block  116 . PLL reconfiguration block  116  may accordingly transmit PLL reconfiguration control signals  117  to configure PLL circuit  150 . It should be appreciated that PLL reconfiguration block  116  may be an interface that receives control signals  119  from status monitor and control block  118  and transmits appropriate PLL reconfiguration control signals  117  to PLL circuit  150 . Once error checker circuit  112  detects valid data, error checker circuit  112  may provide a flag signal  113  to control block  118  indicating that valid data is being received. 
     In one embodiment, status monitor and control block  118  may be a user-design dependent block while PLL reconfiguration block  117  may be a generic or design independent interface block that may be operable to transmit PLL reconfiguration signals  117  to PLL circuit  150  based on control signals  119 . In another embodiment, status monitor and control block  118  may be configured with a PLL reconfiguration interface block. In such an embodiment, a separate or generic PLL reconfiguration block (e.g., PLL reconfiguration block  117 ) may not be required as control signals  119  may be transferred directly to PLL circuit  150  through the PLL reconfiguration interface block within status monitor and control block  118 . 
     In an exemplary embodiment, PLL circuit  150  may be operable to generate clock signals with multiple phases. For instance, PLL circuit  150  may be operable to generate clock signals with eight different phases and PLL reconfiguration block  116  may be operable to control PLL circuit  150  such that error checker block  112  may sample parallel data stream  108 A using every clock phase generated by PLL circuit  150 . 
     PLL reconfiguration block  116  may further be operable to track all of the clock phases in which valid data streams are detected by error checker block  112 . Once a valid data stream is detected by error checker block  112  and an appropriate clock phase is selected by PLL reconfiguration block  116 , PLL circuit  150  may output clocks signals  152 S,  152 P,  154 S, and  154 P at the appropriate phases. 
     In one embodiment, data stream  101  may be a data packet from an external component that includes a plurality of preamble bits, actual data bits, and an end-of-file marker. In one embodiment, PLL reconfiguration block  116  selects a clock phase that corresponds relatively closely with a phase of the plurality of preamble bits. For instance, the rising (or falling) edges of clock signal  152 S may correspond to the center of the data windows of a first portion of the plurality of preamble bits, and the rising edges of clock signal  154 S may correspond to the center of the data windows of a second portion of the plurality of preamble bits. It should be appreciated that the preamble bits may be a training pattern that may include a plurality of predetermined data bits for calibrating a clock circuit such as PLL circuit  150  according to a phase of an incoming data stream. 
     Once PLL circuit  150  has been calibrated, receiver circuits  102 A and  102 B may begin to receive actual data bits from data stream  101 . As mentioned above, deserializer circuits  106 A and  106 B may be clocked respectively by clock signals  152 S and  154 S that are phase shifted by 180 degrees from each other. As such, deserializer circuit  106 A may sample and convert a first portion of serial data stream  101  to first parallel data stream  108 A and deserializer circuit  106 B may sample and convert a second portion of serial data stream  101  to second parallel data stream  108 B. In one embodiment, deserializer circuit  106 A may sample and convert all the odd bits in serial data stream  101  while deserializer circuit  106 B may sample and convert all the even bits in serial data stream  101 . 
     First parallel data stream  108 A may be transmitted to storage circuit  123 A and second parallel data stream  108 B may be transmitted to storage circuit  123 B. Storage circuits  123 A and  123 B are clocked by parallel clock signals  152 P and  154 P, respectively. In the embodiment of  FIG. 2 , each of storage circuits  123 A and  123 B may be controlled by two different clock signals, namely a “write clock” signal and a “read clock” signal. Accordingly, data may be written to and stored in storage circuits  123 A and  123 B according to their “write clock” signals, and the stored data may be read from storage circuits  123 A and  123 B according to their “read clock” signals. 
     In one embodiment, parallel clocks signals  152 P and  154 P, coupled respectively to the “write clock” input terminals of storage circuits  123 A and  123 B, are phase shifted from each other by 180 degrees. It should be appreciated that parallel clock signal  152 P is a corresponding parallel clock signal for serial clock signal  152 S and parallel clock signal  154 P is a corresponding parallel clocks signal for serial clock signal  154 S. 
     First parallel data stream  108 A, may be stored in storage circuit  123 A and second parallel data stream  108 B may be stored in storage circuit  123 B before being transmitted to data assembler circuit  125 . Data assembler circuit  125  may be coupled to receive first and second parallel data streams,  124 A and  124 B, from storage circuits  123 A and  123 B, respectively. In the embodiment of  FIG. 2 , the clock input terminal of assembler circuit  125  and the “read clock” input terminals of storage circuits  123 A and  123 B are coupled to receive parallel clock signal  154 P. 
     It should be appreciated that first and second parallel data streams  108 A and  108 B—due to the fact that even bits in a data stream generally come after the odd bits—may not be received simultaneously by storage circuits  123 A and  123 B. As such, the later clock signal, in this embodiment, parallel clock signal  154 P, may be used as the “read clock” signal for both storage circuits  123 A and  123 B as well as data assembler circuit  125  to ensure that storage circuits  123 A and  123 B contain valid data bits before a read attempt is initiated. 
     First parallel data stream  124 A and second parallel data stream  124 B from storage circuits  123 A and  123 B, respectively, may be merged by assembler circuit  125 . In an exemplary embodiment, first and second parallel data streams  124 A and  124 B are merged by assembler circuit  125  to produce a single parallel data stream  127  having sequentially ordered data bits. The combined parallel data stream  127  may then be transmitted to user design logic block  130 . User design logic block  130  may be clocked with parallel clock signal  154 P. 
     In one embodiment, combined parallel data stream  127  may only be transmitted to user design logic block  130  after the calibration operation has been performed. In another embodiment, a ready signal may be transmitted to user design logic block  130  after the calibration operation has been performed to enable the transmission of combined parallel data stream  127  to user design logic block  130 . It should be appreciated that user logic block  130  may include circuitry or logic elements, details of which are not shown in order not to unnecessarily obscure the present invention, that may be used to implement desired user functions. 
     The combined parallel data stream  127  may also be transmitted to pattern checker block  114 . As pattern checker block  114  is coupled to receive the combined parallel data stream  127  from data assembler circuit  125 , pattern checker block  114  may also be clocked with parallel clock signal  154 P. As mentioned above, data stream  101  may include an end-of-file marker to indicate the end of the data stream and pattern checker block  114  may be operable to check parallel data stream  127  for the end-of-file marker, according to one embodiment. Accordingly, pattern checker block  114  may output a signal, status signal  115 , to indicate if an end-of-file marker has been detected. 
     Once status monitor and control block  118  receives status signal  115  from pattern checker block  114  indicating that an end-of-file marker has been detected, status monitor and control block  118  may initiate a new calibration operation that is similar to the calibration process described above. In an exemplary embodiment, the calibration operation may be repeated for every new data stream received by the integrated circuit. 
       FIG. 3 , meant to be illustrative and not limiting, shows simplified method  300  for operating an integrated circuit in accordance with an embodiment of the present invention. At step  310 , first and second receivers receive a data packet having a first operating frequency rate. In one embodiment, the data packet may include a plurality of preamble bits, a data stream and an end-of-frame marker. The first and second receiver circuits may operate at a different operating frequency rate than the first operating frequency rate of the received data packet. 
     In one embodiment, the first and second receiver circuits may have a slower operating rate compared to the operating rate of the data packet. As an example, the data packet may be a data stream with a data transfer rate of 2.5 Gbps while the first and second receiver circuits may operate at 1.25 GHz. 
     At step  320 , a portion of the data packet received is transmitted to a control circuit. In the embodiment of  FIG. 1 , data stream  101  received at receiver circuit  102 A may be transferred to calibration control circuit  110 . At step  330 , a plurality of preamble bits within the portion of the data packet is identified with the calibration control circuit. 
     A clock circuit is calibrated based on the plurality of preamble bits at step  340 . In one embodiment, the clock circuit may be a PLL circuit and the calibration control circuit may configure the PLL circuit to output clock signals at specific phases according to the plurality of preamble bits in the data packet received. 
       FIG. 4 , meant to be illustrative and not limiting, shows simplified method flow  400  for calibrating a clock circuit in accordance with an embodiment of the present invention. At step  410 , a data stream from an external component is received. In an exemplary embodiment, the clock circuit may be a clock circuit in an integrated circuit device and the external component may be another circuit or device that is coupled to the integrated circuit device through an input-output interface. 
     At step  420 , the data stream is checked for a plurality of valid preamble bits. In one embodiment, the data stream may be transmitted to a checker circuit, such as error checker circuit  112  of  FIG. 2 , that may be operable to sample a plurality of preamble bits multiple times to determine a validity of the preamble bits in the received data stream. 
     An edge of a data window of a first bit of the plurality of valid preamble bits is identified at step  430 . A first clock output of a clock circuit is adjusted to a center of the data window of the first bit of the plurality of preamble bits at step  440 . Accordingly, at step  450 , a second clock output of the clock circuit is adjusted to a center of the data window of a second bit of the plurality of preamble bits. 
     In one embodiment, the plurality of preamble bits may be clocked with a PLL circuit that is operable to output clock signals at a common frequency but with different phases. Therefore, the plurality of preamble bits may be sampled numerous times using multiple clock signals with different phases to identify an operating phase of the plurality of preamble bits. 
     In one embodiment, the clock signal from the PLL circuit with a rising edge (or a falling edge) that corresponds relatively closely to the center of the data window of the first bit of the plurality of preamble bits is selected as the first clock output of the PLL circuit. The PLL circuit may be operable to output two clock signals with different phases at any one time. In an exemplary embodiment, the first and second clock outputs may be clock signals with a 180 degree phase difference. Accordingly, a rising edge (or a falling edge) of the second clock output of the PLL circuit may be adjusted to the center of the data window of the second bit of the plurality of preamble bits. 
       FIG. 5 , meant to be illustrative and not limiting, shows a simplified block diagram of integrated circuit  500  in accordance with an embodiment of the present invention. Integrated circuit  500  includes core logic region  515  and input-output elements  510 . Other auxiliary circuits such as phase-locked loops (PLLs)  525  for clock generation and timing, can be located outside the core logic region  515  (e.g., at corners of integrated circuit  500  and adjacent to input-output elements  510 ). 
     Core logic region  515  may be populated with logic cells that may include “logic elements” (LEs), among other circuits. LEs may include look-up table-based logic regions and may be grouped into “Logic Array Blocks” (LABs). The LEs and groups of LEs or LABs can be configured to perform user functions. Configuration data loaded into configuration memory can be used to produce control signals that configure the LEs and groups of LEs and LABs to perform the desired user functions. Core logic region  515  may also include a plurality of embedded memory blocks  550  that can be used to perform a variety of functions. 
     Input-output elements  510  may also include input-output buffers that connect integrated circuit  500  to other external components. Signals from core region  515  are transmitted through input-output elements  510  to external components that may be connected to integrated circuit  500 . A single device like integrated circuit  500  can potentially support a variety of different interfaces and each individual input-output bank  510  can support a different input-output standard with a different interface. 
     Integrated circuit  500  receives signals from external circuitry at input-output elements  510 . Signals may be routed from input-output elements  510  to core logic region  515  and other logic blocks on integrated circuit  500 . For instance, integrated circuit  500  may be placed on a printed circuit board and may receive signals or data streams from other circuitry. In an exemplary embodiment, input-output elements  510  may include buffer circuits  103 A and  103 B of  FIG. 2 . 
     Core logic region  515  and other logic blocks on integrated circuit  500  may perform functions based on the signals received. In one embodiment, core logic region  515  may include calibration control circuit  110 , clock switching and assembler circuit  120 , and user logic block  130  of  FIG. 1 . Signals may be sent from core logic region  515  and other relevant logic blocks of integrated circuit  500  to other external circuitry or components that may be connected to integrated circuit  500  through input-output elements  510 . 
     The embodiments, thus far, were described with respect to programmable logic circuits. The method and apparatus described herein may be incorporated into any suitable circuit. For example, the method and apparatus may also be incorporated into numerous types of devices such as microprocessors or other integrated circuits. Exemplary integrated circuits include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), just to name a few. 
     The programmable logic device described herein may be part of a data processing system that includes one or more of the following components; a processor; memory; I/O circuitry; and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. The programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable logic device may be one of the family of devices owned by the assignee. 
     Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way. 
     The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.