Patent Publication Number: US-9837032-B2

Title: Method of driving display panel and display apparatus for performing the same

Description:
CLAIM OF PRIORITY 
     Priority is claimed under 35 U.S.C. §119 with respect to Korean Patent Application No. 10-2014-0063006, filed on May 26, 2014 in the Korean Intellectual Property Office KIPO, the contents of which are herein incorporated by reference in their entireties. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a method of driving a display panel and a display apparatus for performing the method. More particularly, the present invention relates to a method of driving a display panel so as to improve driving reliability and decrease a width of a bezel, and a display apparatus for performing the method. 
     Description of the Related Art 
     Generally, a liquid crystal display (LCD) apparatus comprises a first substrate including a pixel electrode, a second substrate including a common electrode, and a liquid crystal layer disposed between the first and second substrates. An electric field is generated by voltages applied to the pixel electrode and the common electrode. By adjusting an intensity of the electric field, transmittance of a light passing through the liquid crystal layer may be adjusted so that a desired image may be displayed. 
     Generally, a display apparatus includes a display panel and a panel driver. The display panel includes a plurality of gate lines and a plurality of data lines. The panel driver includes a gate driver providing gate signals to the gate lines and a data driver providing data voltages to the data lines. 
     To decrease the width of the bezel, a chip on glass (COG) method has been employed. In the COG method, a portion of the panel driver or an entire panel driver is mounted on a substrate of the display panel. As a resolution of the display panel increases, a level of an output current of the data driver increases. However, a positive power voltage of a logic voltage of the data driver tends to decrease. 
     When the data voltage is outputted from the data driver, a negative power voltage may momentarily increase. When a difference between the positive power voltage of the logic voltage and the negative power voltage of the data driver decreases, a level shifter in the data driver may be operated abnormally. Thus, driving reliability of the display apparatus may decrease. 
     In addition, when widths of wirings increase to prevent momentary increase of the negative power voltage when the data voltage is outputted, the width of the bezel may increase. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method of driving a display panel so as to improve driving reliability while decreasing a width of a bezel. 
     The present invention also provides a display apparatus for performing the method of driving the display panel. 
     In an exemplary embodiment of the method of driving a display panel according to the present invention, the method includes outputting a gate signal to a gate line of the display panel in response to a first control signal and outputting a data voltage to a data line of the display panel in response to a second control signal using a plurality of data output blocks having driving timings different from one another. A single driving chip includes the plurality of data output blocks. 
     In an exemplary embodiment, when a distance of the data output block from a signal wiring transmitting a power voltage to the driving chip is relatively far, driving timing of the data output block may be relatively early. 
     In an exemplary embodiment, the driving chip may further include a control block configured to control the driving timings of the data output blocks. 
     In an exemplary embodiment, the outputting the voltage to the data line may use a plurality of driving chips. Each of the driving chips may include the plurality of data output blocks. All of the data output blocks of the driving chips may have driving timings different from one another. 
     In an exemplary embodiment, the outputting the voltage to the data line may use a plurality of driving chips. Each of the driving chips may include the plurality of data output blocks. First data output blocks of the driving chips may have a first driving timing and second data output blocks of the driving chips may have a second driving timing different from the first driving timing. 
     In an exemplary embodiment, the outputting the voltage to the data line may use a plurality of driving chips. When a resistance of a signal wiring transmitting a power voltage to the driving chip is relatively high, driving timing of the driving chip may be relatively early. 
     In an exemplary embodiment, the signal wiring may be sequentially connected to a first driving chip, a second driving chip adjacent to the first driving chip, a third driving chip adjacent to the second driving chip, and a fourth driving chip adjacent to the third driving chip. 
     In an exemplary embodiment, the fourth driving chip, the third driving chip, the second driving chip and the first driving chip may sequentially output the data voltage. 
     In an exemplary embodiment, a first signal wiring may be connected to a first driving chip, a second signal wiring is connected to a second driving chip, a third signal wiring is connected to a third driving chip, and a fourth signal wiring is connected to a fourth driving chip. 
     In an exemplary embodiment, the first and fourth driving chips corresponding to an edge portion of the display panel may output the data voltage earlier than the second and third driving chips corresponding to a central portion of the display panel. 
     In an exemplary embodiment, the driving chip may be mounted on a substrate on which the gate line and the data line are disposed. 
     In an exemplary embodiment of a display apparatus according to the present invention, the display apparatus includes a display panel, a timing controller, a gate driver and a data driver. The display panel includes a gate line and a data line. The display panel is configured to display an image. The timing controller is configured to generate a first control signal and a second control signal. The gate driver is configured to output a gate signal to the gate line in response to the first control signal. The data driver includes a driving chip mounted on a substrate on which the gate line and the data line are disposed, and including a plurality of data output blocks. The data output blocks have driving timings different from one another. The data driver is configured to output a data voltage to the data line using the data output blocks. 
     In an exemplary embodiment, when a distance of the data output block from a signal wiring transmitting a power voltage to the driving chip is relatively far, driving timing of the data output block may be relatively early. 
     In an exemplary embodiment, the driving chip may further include a control block configured to control the driving timings of the data output blocks. 
     In an exemplary embodiment, the data driver may include a plurality of driving chips. Each of the driving chips may include the plurality of data output blocks. All of the data output blocks of the driving chips may have driving timings different from one another. 
     In an exemplary embodiment, the data driver may include a plurality of driving chips. Each of the driving chips may include the plurality of data output blocks. First data output blocks of the driving chips may have a first driving timing and second data output blocks of the driving chips may have a second driving timing different from the first driving timing. 
     In an exemplary embodiment, the data driver may include a plurality of driving chips. The data driver may further include a signal wiring transmitting a power voltage to the driving chip and disposed on the substrate. When a resistance of the signal wiring connected to the driving chip is relatively high, driving timing of the driving chip may be relatively early. 
     According to the method of driving the display panel and the display apparatus for performing the method, the driving chip of the data driver includes a plurality of data output blocks and output timings of the data output blocks are adjusted so that an increase in a negative power source in the data driver is prevented. Thus, driving reliability of the display apparatus may be improved. 
     In addition, the negative power source in the data driver does not momentarily increase so that a thin and long wiring may be employed. Thus, the width of the bezel may decrease. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which like reference symbols indicate the same or similar components, wherein: 
         FIG. 1  is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present invention; 
         FIG. 2  is a block diagram illustrating a data driver of  FIG. 1 ; 
         FIG. 3  is a circuit diagram illustrating a level shifter of  FIG. 2 ; 
         FIG. 4  is a plan view illustrating a driving chip and a wiring of the data driver of  FIG. 1 ; 
         FIG. 5A  is a block diagram illustrating a first driving chip of  FIG. 4 ; 
         FIG. 5B  is a block diagram illustrating a second driving chip of  FIG. 4 ; 
         FIG. 5C  is a block diagram illustrating a third driving chip of  FIG. 4 ; 
         FIG. 5D  is a block diagram illustrating a fourth driving chip of  FIG. 4 ; 
         FIG. 6  is a waveform diagram illustrating signals in the data driver of  FIG. 1 ; 
         FIG. 7  is a waveform diagram illustrating signals in a data driver according to an exemplary embodiment of the present invention; 
         FIG. 8  is a plan view illustrating a driving chip and a wiring of a data driver according to an exemplary embodiment of the present invention; 
         FIG. 9A  is a block diagram illustrating a first driving chip of  FIG. 8 ; 
         FIG. 9B  is a block diagram illustrating a second driving chip of  FIG. 8 ; 
         FIG. 9C  is a block diagram illustrating a third driving chip of  FIG. 8 ; 
         FIG. 9D  is a block diagram illustrating a fourth driving chip of  FIG. 8 ; 
         FIG. 10  is a waveform diagram illustrating signals in the data driver of  FIG. 8 ; 
         FIG. 11  is a waveform diagram illustrating signals in a data driver according to an exemplary embodiment of the present invention; 
         FIG. 12  is a plan view illustrating a driving chip and a wiring of a data driver according to an exemplary embodiment of the present invention; 
         FIG. 13  is a waveform diagram illustrating signals in the data driver of  FIG. 12 ; 
         FIG. 14  is a plan view illustrating a driving chip and a wiring of a data driver according to an exemplary embodiment of the present invention; and 
         FIG. 15  is a waveform diagram illustrating signals in the data driver of  FIG. 14 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings. 
       FIG. 1  is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present invention. 
     Referring to  FIG. 1 , the display apparatus includes a display panel  100  and a panel driver. The panel driver includes a timing controller  200 , a gate driver  300 , a gamma reference voltage generator  400  and a data driver  500 . 
     The display panel  100  displays an image. The display panel  100  has a display region on which an image is displayed and a peripheral region adjacent to the display region. 
     The display panel  100  includes a plurality of gate lines GL, a plurality of data lines DL and a plurality of unit pixels connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D 1  and the data lines DL extend in a second direction D 2  crossing the first direction D 1 . 
     Each unit pixel includes a switching element (not shown), a liquid crystal capacitor (not shown) and a storage capacitor (not shown). The liquid crystal capacitor and the storage capacitor are electrically connected to the switching element. The unit pixels may be disposed in a matrix form. 
     The timing controller  200  receives input image data RGB and an input control signal CONT from an external apparatus (not shown). The input image data RGB may include red image data R, green image data G and blue image data B. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronizing signal and a horizontal synchronizing signal. 
     The timing controller  200  generates a first control signal CONT 1 , a second control signal CONT 2 , a third control signal CONT 3  and a data signal DATA based on the input image data RGB and the input control signal CONT. 
     The timing controller  200  generates the first control signal CONT 1  for controlling an operation of the gate driver  300  based on the input control signal CONT, and outputs the first control signal CONT 1  to the gate driver  300 . The first control signal CONT 1  may further include a vertical start signal and a gate clock signal. 
     The timing controller  200  generates the second control signal CONT 2  for controlling an operation of the data driver  500  based on the input control signal CONT, and outputs the second control signal CONT 2  to the data driver  500 . The second control signal CONT 2  may include a horizontal start signal and a load signal. 
     The timing controller  200  generates the data signal DATA based on the input image data RGB 1 . The timing controller  200  outputs the data signal DATA to the data driver  500 . 
     The timing controller  200  generates the third control signal CONT 3  for controlling an operation of the gamma reference voltage generator  400  based on the input control signal CONT, and outputs the third control signal CONT 3  to the gamma reference voltage generator  400 . 
     The gate driver  300  generates gate signals driving the gate lines GL in response to the first control signal CONT 1  received from the timing controller  200 . The gate driver  300  sequentially outputs the gate signals to the gate lines GL. 
     The gate driver  300  may be directly mounted on the display panel  100 , or it may be connected to the display panel  100  as a tape carrier package (TCP) type. Alternatively, the gate driver  300  may be integrated on the peripheral region of the display panel  100 . 
     The gamma reference voltage generator  400  generates a gamma reference voltage VGREF in response to the third control signal CONT 3  received from the timing controller  200 . The gamma reference voltage generator  400  provides the gamma reference voltage VGREF to the data driver  500 . The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA. 
     In an exemplary embodiment, the gamma reference voltage generator  400  may be disposed in the timing controller  200  or in the data driver  500 . 
     The data driver  500  receives the second control signal CONT 2  and the data signal DATA from the timing controller  200 , and receives the gamma reference voltages VGREF from the gamma reference voltage generator  400 . The data driver  500  converts the data signal DATA into data voltages having an analog type using the gamma reference voltages VGREF. The data driver  500  outputs the data voltages to the data lines DL. 
     In the present exemplary embodiment, the data driver  500  includes a plurality of driving chips. The driving chips are mounted on the display panel  100 . For example, the driving chips may be mounted on a substrate on which the gate line GL and the data line DL are disposed. 
     Alternatively, the data driver  500  may be directly mounted on the display panel  100 , or it may be connected to the display panel  100  as a TCP type. Alternatively, the data driver  500  may be integrated on the peripheral region of the display panel  100 . 
       FIG. 2  is a block diagram illustrating the data driver  500  of  FIG. 1 .  FIG. 3  is a circuit diagram illustrating a level shifter of  FIG. 2 . 
     Referring to  FIGS. 1 to 3 , the data driver  500  includes a level shifter  510 , a shift register  520 , a latch  530 , a signal processing part  540  and a buffer  550 . 
     The level shifter  510  increases a level of an input voltage inputted to an input terminal IN so as to generate an output voltage. The level shifter  510  outputs the output voltage through an output terminal OUT. 
     For example, the input voltage has a value between a first positive power voltage VDD 1  and a first negative power voltage VSS 1 . The output voltage has a value between a second positive power voltage VDD 2  higher than the first positive power voltage VDD 1  and a second negative power voltage VSS 2 . 
     The first positive power voltage VDD 1  and the first negative power voltage VSS 1  are mainly used with respect to a digital operation. For example, the first positive power voltage VDD 1  may be called to a logic power, and the first negative power voltage VSS 1  may be called to a logic ground. The second positive power voltage VDD 2  and the second negative power voltage VSS 2  may be used in the shift register  520  and the analog output buffer  550 . For example, the first positive power voltage VDD 1  may be between about 1V and about 2V, and the second positive power voltage VDD 2  may be between about 7V and about 10V. For example, the first negative power voltage VSS 1  may be a ground voltage, and the second negative power voltage VSS 2  may be a ground voltage. 
     For example, a waveform of the output voltage may be inverted from the input voltage. As a further example, when the input voltage has a low level, the output voltage may have a high level and, when the input voltage has a high level, the output voltage may have a low level. 
     The level shifter  510  includes an inverter INV and first to fourth switching elements T 1 , T 2 , T 3  and T 4 . A first end portion or input of the inverter INV is connected to the input terminal IN of the level shifter  510  and to a control electrode of the first switching element T 1 . A second end portion or output of the inverter INV is connected to a control electrode of the second switching element T 2 . An input electrode of the first switching element T 1  is connected to a control electrode of the fourth switching element T 4 . The second negative power voltage VSS 2  is applied to an output electrode of the first switching element T 1 . An input electrode of the second switching element T 2  is connected to a control electrode of the third switching element T 3 . The second negative power voltage VSS 2  is applied to an output electrode of the second switching element T 2 . The second positive power voltage VDD 2  is applied to an input electrode of the third switching element T 3 . An output electrode of the third switching element T 3  is connected to the input electrode of the first switching element T 1 . The second positive power voltage VDD 2  is applied to an input electrode of the fourth switching element T 4 . An output electrode of the fourth switching element T 4  is connected to the input electrode of the second switching element T 2 . The output terminal OUT of the level shifter  510  is connected to the output electrode of the fourth switching element T 4 . 
     The shift register  520  is a group of process registers of a linear type in a digital circuit. The shift register  520  outputs a latch pulse to the latch  530 . 
     The latch  530  temporarily stores the data signal DATA and outputs the data signal DATA. 
     The signal processing part  540  converts the data signal DATA having a digital type to a data voltage having an analog type based on the gamma reference voltage VGREF and outputs the data voltage. The signal processing part  540  may include a digital to analog converter. 
     The buffer  550  buffers the data voltage outputted from the signal processing part  540  and outputs the data voltage to the data line DL. The buffer  550  may include an amplifier connected to the data line DL. 
       FIG. 4  is a plan view illustrating a driving chip and a wiring of the data driver  500  of  FIG. 1 .  FIG. 5A  is a block diagram illustrating a first driving chip of  FIG. 4 .  FIG. 5B  is a block diagram illustrating a second driving chip of  FIG. 4 .  FIG. 5C  is a block diagram illustrating a third driving chip of  FIG. 4 .  FIG. 5D  is a block diagram illustrating a fourth driving chip of  FIG. 4 .  FIG. 6  is a waveform diagram illustrating signals in the data driver  500  of  FIG. 1 . 
     Referring to  FIGS. 1 to 6 , the data driver  500  includes a driving chip. For example, the data driver  500  may include a plurality of driving chips, and the data driver  500  may include four driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . The data driver  500  includes a first driving chip SIC 1 , a second driving chip SIC 2  adjacent to the first driving chip SIC 1 , a third driving chip SIC 3  adjacent to the second driving chip SIC 2  and a fourth driving chip SIC 4  adjacent to the third driving chip SIC 3 . 
     Each driving chip includes a plurality of data output blocks. The first driving chip SIC 1  includes a first data output block DB 11  and a second data output block DB 12 . The second driving chip SIC 2  includes a first data output block DB 21  and a second data output block DB 22 . The third driving chip SIC 3  includes a first data output block DB 31  and a second data output block DB 32 . The fourth driving chip SIC 4  includes a first data output block DB 41  and a second data output block DB 42 . 
     Each driving chip may further include a control block. The first driving chip SIC 1  may further include a first control block CB 1 . The second driving chip SIC 2  may further include a second control block CB 2 . The third driving chip SIC 3  may further include a third control block CB 3 . The fourth driving chip SIC 4  may further include a fourth control block CB 4 . The control block receives the second control signal CONT 2  from the timing controller  200  so as to control an operation of the driving chip. For example, the control block may control output timings of the data output blocks. 
     Although the data driver  500  includes four driving chips in the present exemplary embodiment, the present invention is not limited to the number of driving chips. Alternatively, the data driver  500  may include a single driving chip. 
     Although each driving chip includes two data output blocks in the present exemplary embodiment, the present invention is not limited to the number of data output blocks. However, in the present exemplary embodiment, the data driver  500  includes at least one driving chip, which includes a plurality of data output blocks. 
     The data driver  500  includes signal wirings L 1 , L 2 , L 3  and L 4  for transmitting a power voltage to the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 , respectively. In the present exemplary embodiment, the signal wirings L 1 , L 2 , L 3  and L 4  may be sequentially connected to the first driving chip SIC 1 , the second driving chip SIC 2 , the third driving chip SIC 3  and the fourth driving chip SIC 4 . 
     For example, a first signal wiring L 1  may transmit the second positive power voltage VDD 2  to the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . A second signal wiring L 2  may transmit the first positive power voltage VDD 1  to the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . A third signal wiring L 3  may transmit the first negative power voltage VSS 1  to the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . A fourth signal wiring L 4  may transmit the second negative power voltage VSS 2  to the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . 
     The first driving chip SIC 1  is relatively close to a power providing part (not shown). The fourth driving chip SIC 4  is relatively far from the power providing part (not shown). Thus, the resistance of a portion of the signal wiring connected to the fourth driving chip SIC 4  is higher than the resistance of a portion of the signal wiring connected to the first driving chip SIC 1 . 
     In  FIG. 6 , EN 1 - 1  is an enable signal of the first data output block DB 11  of the first driving chip SIC 1  representing driving timing of the first data output block DB 11  of the first driving chip SIC 1  which outputs the data voltage. EN 1 - 2  is an enable signal of the second data output block DB 12  of the first driving chip SIC 1  representing driving timing of the second data output block DB 12  of the first driving chip SIC 1  which outputs the data voltage. EN 2 - 1  is an enable signal of the first data output block DB 21  of the second driving chip SIC 2  representing driving timing of the first data output block DB 21  of the second driving chip SIC 2  which outputs the data voltage. EN 2 - 2  is an enable signal of the second data output block DB 22  of the second driving chip SIC 2  representing driving timing of the second data output block DB 22  of the second driving chip SIC 2  which outputs the data voltage. EN 3 - 1  is an enable signal of the first data output block DB 31  of the third driving chip SIC 3  representing driving timing of the first data output block DB 31  of the third driving chip SIC 3  which outputs the data voltage. EN 3 - 2  is an enable signal of the second data output block DB 32  of the third driving chip SIC 3  representing driving timing of the second data output block DB 32  of the third driving chip SIC 3  which outputs the data voltage. EN 4 - 1  is an enable signal of the first data output block DB 41  of the fourth driving chip SIC 4  representing driving timing of the first data output block DB 41  of the fourth driving chip SIC 4  which outputs the data voltage. EN 4 - 2  is an enable signal of the second data output block DB 42  of the fourth driving chip SIC 4  representing driving timing of the second data output block DB 42  of the fourth driving chip SIC 4  which outputs the data voltage. 
     In the present exemplary embodiment, the first data output block DB 11  and the second data output block DB 12  of the first driving chip SIC 1  have driving timings different from each other. The first data output block DB 21  and the second data output block DB 22  of the second driving chip SIC 2  have driving timings different from each other. The first data output block DB 31  and the second data output block DB 32  of the third driving chip SIC 3  have driving timings different from each other. The first data output block DB 41  and the second data output block DB 42  of the fourth driving chip SIC 4  have driving timings different from each other. In addition, the first to fourth driving chips SIC 1  to SIC 4  have driving timings different from one another. Therefore, all of the eight data output blocks DB 11  to DB 42  of the first to fourth driving chips SIC 1  to SIC 4  may have driving timings different from one another. 
     In the present exemplary embodiment, when a distance of the driving chip from the signal wiring L 1  to L 4  transmitting the power voltage to the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively far, driving timing of the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is designed to be relatively early. For example, when the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  are far from the signal wirings L 1  to L 4  compared to the first data output blocks DB 11 , DB 21 , DB 31  and DB 41 , driving timing of the second output block DB 12 , DB 22 , DB 32  and DB 42  is earlier than driving timing of the first output block DB 11 , DB 21 , DB 31  and DB 41  respectively in the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4 . 
     In the present exemplary embodiment, when a resistance of the signal wiring (e.g. L 1 ) transmitting the power voltage to the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively high, driving timing of the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively early. For example, the fourth driving chip SIC 4 , the third driving chip SIC 3 , the second driving chip SIC 2  and the first driving chip SIC 1  sequentially output the data voltage. 
     The CR curve in  FIG. 6  represents a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4  in a conventional driving method in which the driving chip is not divided into the plurality of data output blocks and the driving chips concurrently output the data voltage. In the conventional driving method, the first to fourth driving chips SIC 1  to SIC 4  concurrently output the data voltage so that a noise is generated due to a resistance of the signal wiring. Accordingly, the second negative power voltage VSS 2  of the fourth driving chip SIC 4  momentarily increases. The fourth driving chip SIC 4  is the farthest from the power providing part so that a resistance of a portion of the signal wiring connected to the fourth driving chip SIC 4  is the highest and the second negative power voltage VSS 2  of the fourth driving chip SIC 4  increases the most. 
     In  FIG. 6 , Ver is an error reference voltage of abnormal operation of the level shifter  510  and the shift register  520  due to the second negative power voltage VSS 2 . When the second negative power voltage VSS 2  exceeds the error reference voltage Ver, the level shifter  510  and the shift register  520  may operate abnormally. 
     Referring again to  FIG. 3 , when the second negative power voltage VSS 2  exceeds the error reference voltage Ver, the level of the second power voltage VSS 2  connected to the output electrodes of the first and second switching elements T 1  and T 2 , respectively, the first and second switching elements T 1  and T 2 , respectively, may not be normally turned on. Thus, the level shifter  510  operates abnormally and the shift register  520  and the buffer  550  may operate abnormally. 
     According to the principles of the present invention, the first and second data output blocks DB 11  to DB 42 , respectively, of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 , respectively, of the present exemplary embodiment are controlled to have driving timings different from one another. In  FIG. 6 , the C curve represents a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4  according to the present invention. 
     For example, a first rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4  when the second data output block DB 42  of the fourth driving chip SIC 4  outputs the data voltage. A second rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4  when the first data output block DB 41  of the fourth driving chip SIC 4  outputs the data voltage. A third rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the third driving chip SIC 3  when the second data output block DB 32  of the third driving chip SIC 3  outputs the data voltage. A fourth rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the third driving chip SIC 3  when the first data output block DB 31  of the third driving chip SIC 3  outputs the data voltage. A fifth rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the second driving chip SIC 2  when the second data output block DB 22  of the second driving chip SIC 2  outputs the data voltage. A sixth rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the second driving chip SIC 2  when the first data output block DB 21  of the second driving chip SIC 2  outputs the data voltage. A seventh rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the first driving chip SIC 1  when the second data output block DB 12  of the first driving chip SIC 1  outputs the data voltage. An eighth rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the first driving chip SIC 1  when the first data output block DB 11  of the first driving chip SIC 1  outputs the data voltage. 
     As shown in  FIG. 6 , the first and second data output blocks DB 11  to DB 42  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timings different from one another so that the second negative power voltage VSS 2  does not exceed the error reference voltage Ver. Thus, the level shifter  510  and the shift register  520  operate normally. 
     In an exemplary embodiment, the control blocks CB 1  to CB 4  of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  may control their own driving timings so as to be different from one another. The driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  may store their own addresses. According to the addresses, the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  may set the driving timings of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . The driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  receive a driving chip control signal from the timing controller  200 . The driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  generate the first to eighth driving enable signals EN 1 - 1  to EN 4 - 2  based on the driving chip control signal. 
     Alternatively, the timing controller  200  may generate a plurality of driving chip control signals and outputs the driving chip control signals to the data driver  500  so that the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have different driving timings. The timing controller  200  may output the driving chip control signals having timings different from one another to the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . 
     In an exemplary embodiment, when the driving timing of the driving chip is relatively late, a bias current of the driving chip may be relatively high. When the driving timing of the driving chip is relatively late, a charging time of a pixel connected to the driving chip may be relatively short. The bias current of the driving chip having a relatively short charging time increases so that driving ability of the driving chip may be improved and a decrease in the charging time of the driving chip may be compensated. 
     For example, a bias current of a buffer of the first driving chip SIC 1  may be the highest. A bias current of a buffer of the fourth driving chip SIC 4  may be the lowest. 
     According to the present exemplary embodiment, the plurality of the data output blocks DB 11  to DB 42  of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timings different from one another so that the second negative power voltage VSS 2  in the signal wiring is prevented from exceeding the error reference voltage Ver. Thus, driving reliability may be improved. 
     In addition, when the plurality of the data output blocks of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timings different from one another, the second negative power voltage VSS 2  in the signal wiring does not momentarily increase, allowing one to design the signal wiring to have a higher resistance. For example, when a thin and long signal wiring is employed, a width of a bezel of the display apparatus may decrease. 
       FIG. 7  is a waveform diagram illustrating signals in the data driver  500  according to an exemplary embodiment of the present invention. 
     The method of driving the display panel and the display apparatus for performing the method are substantially the same as the method of driving the display panel and the display apparatus for performing the method of the previous exemplary embodiment explained referring to  FIGS. 1 to 6  except for the driving timing of the data output blocks of the driving chips. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment of  FIGS. 1 to 6  and any repetitive explanation concerning the above elements will be omitted. 
     Referring to  FIGS. 1 to 5D and 7 , the display apparatus includes a display panel  100  and a panel driver. The panel driver includes a timing controller  200 , a gate driver  300 , a gamma reference voltage generator  400  and a data driver  500 . 
     The data driver  500  includes a driving chip. For example, the data driver  500  may include a plurality of driving chips, and the data driver may include four driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . The data driver  500  includes a first driving chip SIC 1 , a second driving chip SIC 2  adjacent to the first driving chip SIC 1 , a third driving chip SIC 3  adjacent to the second driving chip SIC 2  and a fourth driving chip SIC 4  adjacent to the third driving chip SIC 3 . 
     The driving chip includes a plurality of data output blocks. The first driving chip SIC 1  includes a first data output block DB 11  and a second data output block DB 12 . The second driving chip SIC 2  includes a first data output block DB 21  and a second data output block DB 22 . The third driving chip SIC 3  includes a first data output block DB 31  and a second data output block DB 32 . The fourth driving chip SIC 4  includes a first data output block DB 41  and a second data output block DB 42 . 
     The driving chip may further include a control block. The first driving chip SIC 1  may further include a first control block CB 1 . The second driving chip SIC 2  may further include a second control block CB 2 . The third driving chip SIC 3  may further include a third control block CB 3 . The fourth driving chip SIC 4  may further include a fourth control block CB 4 . Each control block receives the second control signal CONT 2  from the timing controller  200  so as to control an operation of the driving chip. For example, the control block may control output timings of the data output blocks. 
     The data driver  500  includes signal wirings L 1 , L 2 , L 3  and L 4  for transmitting a power voltage to the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . In the present exemplary embodiment, the signal wirings L 1 , L 2 , L 3  and L 4  may be sequentially connected to the first driving chip SIC 1 , the second driving chip SIC 2 , the third driving chip SIC 3  and the fourth driving chip SIC 4 . 
     In  FIG. 7 , EN 1  is an enable signal of the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1  to SIC 4  representing driving timing of the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1  to SIC 4  which output the data voltage. EN 2  is an enable signal of the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1  to SIC 4  representing driving timing of the second data output block DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1  to SIC 4  which output the data voltage. 
     In the present exemplary embodiment, the first data output block DB 11  and the second data output block DB 12  of the first driving chip SIC 1  have driving timings different from each other. The first data output block DB 21  and the second data output block DB 22  of the second driving chip SIC 2  have driving timings different from each other. The first data output block DB 31  and the second data output block DB 32  of the third driving chip SIC 3  have driving timings different from each other. The first data output block DB 41  and the second data output block DB 42  of the fourth driving chip SIC 4  have driving timings different from each other. The first to fourth driving chips SIC 1  to SIC 4  have the same driving timings as one another. Therefore, the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the driving chips SIC 1  to SIC 4  commonly have a first driving timing. The second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the driving chips SIC 1  to SIC 4  commonly have a second driving timing. 
     In the present exemplary embodiment, when a distance of the driving chip from the signal wiring L 1  to L 4  transmitting the power voltage to the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively far, driving timing of the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively early. For example, when the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  are far from the signal wirings L 1  to L 4  compared to the first data output blocks DB 11 , DB 21 , DB 31  and DB 41 , driving timing of the second output block DB 12 , DB 22 , DB 32  and DB 42  is earlier than driving timing of the first output block DB 11 , DB 21 , DB 31  and DB 41  in the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4 . 
     In the present exemplary embodiment, the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  and the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  are controlled so as to have driving timings different from each other. In  FIG. 6 , the C curve represents a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4 . 
     For example, a first rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4  when the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1  to SIC 4  output the data voltage. A second rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4  when the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1  to SIC 4  output the data voltage. 
     As shown in  FIG. 7 , the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have a driving timing different from the driving timing of the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  so that the second negative power voltage VSS 2  does not exceed the error reference voltage Ver. Thus, the level shifter  510  and the shift register  520  operate normally. 
     According to the present exemplary embodiment, the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the driving chips have driving timing different from driving timing of the second data output blocks DB 12 , DB 22 , DB 32  and DB 41  of the driving chips so that the second negative power voltage VSS 2  in the signal wiring is prevented from exceeding the error reference voltage Ver. Thus, driving reliability may be improved. 
     In addition, when the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  and the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timings different from each other, the second negative power voltage VSS 2  in the signal wiring does not momentarily increase so that a relatively high resistance of the signal wiring is allowed. For example, when a thin and long signal wiring is employed, the width of a bezel of the display apparatus may decrease. 
       FIG. 8  is a plan view illustrating a driving chip and a wiring of a data driver according to an exemplary embodiment of the present invention.  FIG. 9A  is a block diagram illustrating a first driving chip of  FIG. 8 .  FIG. 9B  is a block diagram illustrating a second driving chip of  FIG. 8 .  FIG. 9C  is a block diagram illustrating a third driving chip of  FIG. 8 .  FIG. 9D  is a block diagram illustrating a fourth driving chip of  FIG. 8 .  FIG. 10  is a waveform diagram illustrating signals in the data driver of  FIG. 8 . 
     The method of driving the display panel and the display apparatus for performing the method are substantially the same as the method of driving the display panel and the display apparatus for performing the method of the previous exemplary embodiment explained referring to  FIGS. 1 to 6  except for a wiring structure connecting the driving chips. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment of  FIGS. 1 to 6  and any repetitive explanation concerning the above elements will be omitted. 
     Referring to  FIGS. 1 to 3 and 8 to 10 , the display apparatus includes a display panel  100  and a panel driver. The panel driver includes a timing controller  200 , a gate driver  300 , a gamma reference voltage generator  400  and a data driver  500 . 
     The data driver  500  includes a driving chip. For example, the data driver  500  may include a plurality of driving chips, and the data driver may include four driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . The data driver  500  includes a first driving chip SIC 1 , a second driving chip SIC 2  adjacent to the first driving chip SIC 1 , a third driving chip SIC 3  adjacent to the second driving chip SIC 2 , and a fourth driving chip SIC 4  adjacent to the third driving chip SIC 3 . 
     Each driving chip includes a plurality of data output blocks. The first driving chip SIC 1  includes a first data output block DB 11  and a second data output block DB 12 . The second driving chip SIC 2  includes a first data output block DB 21  and a second data output block DB 22 . The third driving chip SIC 3  includes a first data output block DB 31  and a second data output block DB 32 . The fourth driving chip SIC 4  includes a first data output block DB 41  and a second data output block DB 42 . 
     Each driving chip may further include a control block. The first driving chip SIC 1  may further include a first control block CB 1 . The second driving chip SIC 2  may further include a second control block CB 2 . The third driving chip SIC 3  may further include a third control block CB 3 . The fourth driving chip SIC 4  may further include a fourth control block CB 4 . The control block receives the second control signal CONT 2  from the timing controller  200  so as to control an operation of the driving chip. For example, the control block may control output timings of the data output blocks. 
     The data driver  500  includes signal wirings L 11  to L 44  for transmitting a power voltage to the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 , respectively. In the present exemplary embodiment, a first group of the signal wirings L 11  to L 14  may be connected to the first driving chip SIC 1 . A second group of the signal wirings L 21  to L 24  may be connected to the second driving chip SIC 2 . A third group of the signal wirings L 31  to L 34  may be connected to the third driving chip SIC 3 . A fourth group of the signal wirings L 41  to L 44  may be connected to the fourth driving chip SIC 4 . 
     For example, first signal wirings L 11 , L 21 , L 31  and L 41  in each group may transmit a second positive power voltage VDD 2  to the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . Second signal wirings L 12 , L 22 , L 32  and L 42  may transmit a first positive power voltage VDD 1  to the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . Third signal wirings L 13 , L 23 , L 33  and L 43  may transmit a first negative power voltage VSS 1  to the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . Fourth signal wirings L 14 , L 24 , L 34  and L 44  may transmit a second negative power voltage VSS 2  to the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . 
     The first driving chip SIC 1  and the fourth driving chip SIC 4  corresponding to an edge portion of the display panel  100  are relatively far from a power providing part (not shown). The second driving chip SIC 2  and the third driving chip SIC 3  corresponding to a central portion of the display panel  100  are relatively close to the power providing part (not shown). Thus, resistances of portions of the signal wirings connected to the first and fourth driving chips SIC 1  and SIC 4 , respectively, are higher than resistances of portions of the signal wirings connected to the second and third driving chips SIC 2  and SIC 3 , respectively. For example, the signal wirings in the present exemplary embodiment extend to a left portion of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . A resistance of a portion of the signal wiring connected to the first driving chip SIC 1  is higher than a resistance of a portion of the signal wiring connected to the fourth driving chip SIC 4 . A resistance of a portion of the signal wiring connected to the second driving chip SIC 2  is higher than a resistance of a portion of the signal wiring connected to the third driving chip SIC 3 . 
     In  FIG. 10 , EN 1 - 1  is an enable signal of the first data output block DB 11  of the first driving chip SIC 1  representing driving timing of the first data output block DB 11  of the first driving chip SIC 1  which outputs the data voltage. EN 1 - 2  is an enable signal of the second data output block DB 12  of the first driving chip SIC 1  representing driving timing of the second data output block DB 12  of the first driving chip SIC 1  which outputs the data voltage. EN 2 - 1  is an enable signal of the first data output block DB 21  of the second driving chip SIC 2  representing driving timing of the first data output block DB 21  of the second driving chip SIC 2  which outputs the data voltage. EN 2 - 2  is an enable signal of the second data output block DB 22  of the second driving chip SIC 2  representing driving timing of the second data output block DB 22  of the second driving chip SIC 2  which outputs the data voltage. EN 3 - 1  is an enable signal of the first data output block DB 31  of the third driving chip SIC 3  representing driving timing of the first data output block DB 31  of the third driving chip SIC 3  which outputs the data voltage. EN 3 - 2  is an enable signal of the second data output block DB 32  of the third driving chip SIC 3  representing driving timing of the second data output block DB 32  of the third driving chip SIC 3  which outputs the data voltage. EN 4 - 1  is an enable signal of the first data output block DB 41  of the fourth driving chip SIC 4  representing driving timing of the first data output block DB 41  of the fourth driving chip SIC 4  which outputs the data voltage. EN 4 - 2  is an enable signal of the second data output block DB 42  of the fourth driving chip SIC 4  representing driving timing of the second data output block DB 42  of the fourth driving chip SIC 4  which outputs the data voltage. 
     In the present exemplary embodiment, the first data output block DB 11  and the second data output block DB 12  of the first driving chip SIC 1  have driving timings different from each other. The first data output block DB 21  and the second data output block DB 22  of the second driving chip SIC 2  have driving timings different from each other. The first data output block DB 31  and the second data output block DB 32  of the third driving chip SIC 3  have driving timings different from each other. The first data output block DB 41  and the second data output block DB 42  of the fourth driving chip SIC 4  have driving timings different from each other. In addition, the first to fourth driving chips SIC 1  to SIC 4  have driving timings different from one another. Therefore, all of the eight data output blocks DB 11  to DB 42  of the first to fourth driving chips SIC 1  to SIC 4  may have driving timings different from one another. 
     In the present exemplary embodiment, when a distance of the driving chip from the power providing part signal wiring L 1  to L 4  transmitting the power voltage to the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively far, the driving timing of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively early. For example, when the second data output blocks DB 32  and DB 42  are far from the signal wirings L 31  to L 44  compared to the first data output blocks DB 31  and DB 41  in the third and fourth driving chips SIC 3  and SIC 4 , driving timings of the second output blocks DB 32  and DB 42  are respectively earlier than driving timings of the first output blocks DB 31  and DB 41 . For example, when the first data output blocks DB 11  and DB 21  are far from the signal wirings L 11  to L 24  compared to the second data output blocks DB 12  and DB 22  in the first and second driving chips SIC 1  and SIC 2 , driving timings of the first output blocks DB 11  and DB 21  are respectively earlier than driving timings of the second output blocks DB 12  and DB 22 . 
     In the present exemplary embodiment, when a resistance of the signal wiring transmitting the power voltage to the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively high, driving timing of the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively early. For example, the first driving chip SIC 1 , the fourth driving chip SIC 4 , the second driving chip SIC 2  and the third driving chip SIC 3  sequentially output the data voltage. 
     Alternatively, the first driving chip SIC 1  and the fourth driving chip SIC 4  output the data voltage with a first timing and the second driving chip SIC 2  and the third driving chip SIC 3  output the data voltage with a second timing. 
     In  FIG. 10 , the CR curve represents a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4  in a conventional driving method in which the driving chip is not divided into the plurality of the data output blocks, and the driving chips concurrently output the data voltage. In the conventional driving method, the first to fourth driving chips SIC 1  to SIC 4 , respectively, concurrently output the data voltage so that a noise is generated due to a resistance of the signal wiring. 
     Referring again to  FIG. 3 , when the second negative power voltage VSS 2  exceeds an error reference voltage Ver, the level of the second power voltage VSS 2  connected to the output electrodes of the first and second switching elements T 1  and T 2 , the first and second switching elements T 1  and T 2  may not be normally turned on. Thus, the level shifter  510  operates abnormally and the shift register  520  and the buffer  550  may operate abnormally. 
     The first and second data output blocks DB 11  to DB 42  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  of the present exemplary embodiment are controlled to have driving timings different from one another. In  FIG. 10 , the C1 curve represents a waveform of the second negative power voltage VSS 2  of the first driving chip SIC 1  when the first driving chip SIC 1  outputs the data voltage, the C2 curve represents a waveform of the second negative power voltage VSS 2  of the second driving chip SIC 2  when the second driving chip SIC 2  outputs the data voltage, the C3 curve represents a waveform of the second negative power voltage VSS 2  of the third driving chip SIC 3  when the third driving chip SIC 3  outputs the data voltage, and the C4 curve represents a waveform of the second negative power voltage VSS 2  of the fourth driving chip SIC 4  when the fourth driving chip SIC 4  outputs the data voltage. 
     As shown in  FIG. 10 , the first and second data output blocks DB 11  to DB 42  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timings different from one another so that the second negative power voltage VSS 2  does not exceed the error reference voltage Ver. Thus, the level shifter  510  and the shift register  520  operate normally. 
     According to the present exemplary embodiment, the plurality of data output blocks DB 11  to DB 42  of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timings different from one another so that the second negative power voltage VSS 2  in the signal wiring is prevented from exceeding the error reference voltage Ver. Thus, driving reliability may be improved. 
     In addition, when the plurality of data output blocks DB 11  to DB 42  of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timings different from one another, the second negative power voltage VSS 2  in the signal wiring does not momentarily increase so that a relatively high resistance of the signal wiring is allowed. For example, when a thin and long signal wiring is employed, the width of a bezel of the display apparatus may decrease. 
       FIG. 11  is a waveform diagram illustrating signals in a data driver according to an exemplary embodiment of the present invention. 
     The method of driving the display panel and the display apparatus for performing the method are substantially the same as the method of driving the display panel and the display apparatus for performing the method of the previous exemplary embodiment explained with reference to  FIGS. 8 to 10  except for the driving timing of the data output blocks of the driving chips. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment of  FIGS. 1 to 6 , and any repetitive explanation concerning the above elements will be omitted. 
     Referring to  FIGS. 1 to 3, 8 to 9D and 11 , the display apparatus includes a display panel  100  and a panel driver. The panel driver includes a timing controller  200 , a gate driver  300 , a gamma reference voltage generator  400  and a data driver  500 . 
     The data driver  500  includes a driving chip. For example, the data driver  500  may include a plurality of driving chips, and the data driver may include four driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . The data driver  500  includes a first driving chip SIC 1 , a second driving chip SIC 2  adjacent to the first driving chip SIC 1 , a third driving chip SIC 3  adjacent to the second driving chip SIC 2  and a fourth driving chip SIC 4  adjacent to the third driving chip SIC 3 . 
     The driving chip includes a plurality of data output blocks. The first driving chip SIC 1  includes a first data output block DB 11  and a second data output block DB 12 . The second driving chip SIC 2  includes a first data output block DB 21  and a second data output block DB 22 . The third driving chip SIC 3  includes a first data output block DB 31  and a second data output block DB 32 . The fourth driving chip SIC 4  includes a first data output block DB 41  and a second data output block DB 42 . 
     The driving chip may further include a control block. The first driving chip SIC 1  may further include a first control block CB 1 . The second driving chip SIC 2  may further include a second control block CB 2 . The third driving chip SIC 3  may further include a third control block CB 3 . The fourth driving chip SIC 4  may further include a fourth control block CB 4 . Each control block receives the second control signal CONT 2  from the timing controller  200  so as to control an operation of the driving chip. For example, the control block may control output timings of the data output blocks. 
     The data driver  500  includes signal wirings L 11  to L 44  for transmitting a power voltage to the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4 . In the present exemplary embodiment, a first group of the signal wirings L 11  to L 14  may be connected to the first driving chip SIC 1 . A second group of the signal wirings L 21  to L 24  may be connected to the second driving chip SIC 2 . A third group of the signal wirings L 31  to L 34  may be connected to the third driving chip SIC 3 . A fourth group of the signal wirings L 41  to L 44  may be connected to the fourth driving chip SIC 4 . 
     In  FIG. 11 , EN 1  is an enable signal of the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1  to SIC 4  representing driving timing of the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1  to SIC 4  which output the data voltage. EN 2  is an enable signal of the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1  to SIC 4  representing driving timing of the second data output block DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1  to SIC 4  which output the data voltage. 
     In the present exemplary embodiment, the first data output block DB 11  and the second data output block DB 12  of the first driving chip SIC 1  have driving timings different from each other. The first data output block DB 21  and the second data output block DB 22  of the second driving chip SIC 2  have driving timings different from each other. The first data output block DB 31  and the second data output block DB 32  of the third driving chip SIC 3  have driving timings different from each other. The first data output block DB 41  and the second data output block DB 42  of the fourth driving chip SIC 4  have driving timings different from each other. The first to fourth driving chips SIC 1  to SIC 4  have the same driving timings as one another. Therefore, the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the driving chips SIC 1  to SIC 4  commonly have a first driving timing. The second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the driving chips SIC 1  to SIC 4  commonly have a second driving timing. 
     In the present exemplary embodiment, when a distance of the driving chip from the signal wiring L 11  to L 44  transmitting the power voltage to the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively far, driving timing of the driving chip SIC 1 , SIC 2 , SIC 3  and SIC 4  is relatively early. 
     In the present exemplary embodiment, the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  and the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  are controlled to have driving timings different from each other. In  FIG. 11 , the C curve represents a waveform of the second negative power voltage VSS 2  of the first driving chip SIC 1 . 
     For example, a first rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the first driving chip SIC 1  when the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1  to SIC 4  output the data voltage. A second rising waveform of the C curve is a waveform of the second negative power voltage VSS 2  of the first driving chip SIC 1  when the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1  to SIC 4  output the data voltage. 
     As shown in  FIG. 11 , the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timing different from the driving timing of the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the first to fourth driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  so that the second negative power voltage VSS 2  does not exceed the error reference voltage Ver. Thus, the level shifter  510  and the shift register  520  operate normally. 
     According to the present exemplary embodiment, the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the driving chips have driving timing different from driving timing of the second data output blocks DB 12 , DB 22 , DB 32  and DB 41  of the driving chips so that the second negative power voltage VSS 2  in the signal wiring is prevented from exceeding the error reference voltage Ver. Thus, driving reliability may be improved. 
     In addition, when the first data output blocks DB 11 , DB 21 , DB 31  and DB 41  of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  and the second data output blocks DB 12 , DB 22 , DB 32  and DB 42  of the driving chips SIC 1 , SIC 2 , SIC 3  and SIC 4  have driving timings different from each other, the second negative power voltage VSS 2  in the signal wiring does not momentarily increase so that a relatively high resistance of the signal wiring is allowed. For example, when a thin and long signal wiring is employed, the width of a bezel of the display apparatus may decrease. 
       FIG. 12  is a plan view illustrating a driving chip and a wiring of a data driver according to an exemplary embodiment of the present invention.  FIG. 13  is a waveform diagram illustrating signals in the data driver of  FIG. 12 . 
     The method of driving the display panel and the display apparatus for performing the method are substantially the same as the method of driving the display panel and the display apparatus for performing the method of the previous exemplary embodiment explained referring to  FIGS. 1 to 6  except that the data driver includes a single driving chip and the driving chip includes four data output blocks. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment of  FIGS. 1 to 6  and any repetitive explanation concerning the above elements will be omitted. 
     Referring to  FIGS. 1 to 3, 12 and 13 , the data driver  500  includes a single driving chip SIC. The driving chip SIC includes a plurality of data output blocks. For example, the driving chip SIC includes a plurality of data output blocks, and the driving chip SIC includes first to fourth data output blocks DB 1 , DB 2 , DB 3  and DB 4 . 
     The driving chip SIC may further include a control block CB. For example, the control block CB may control output timings of the data output blocks DB 1 , DB 2 , DB 3  and DB 4 . The control block CB may be disposed at a side portion of the driving chip SIC. The control block CB may be disposed adjacent to the first data output block DB 1 . 
     Although the driving chip SIC includes four data output blocks in the present exemplary embodiment, the present invention is not limited to the number of data output blocks. 
     The data driver  500  includes signal wirings L 1 , L 2 , L 3  and L 4  for transmitting a power voltage to the driving chip SIC. In the present exemplary embodiment, the signal wirings L 1 , L 2 , L 3  and L 4  may be connected to the control block CB of the driving chip SIC. 
     For example, a first signal wiring L 1  may transmit the second positive power voltage VDD 2  to the driving chip SIC. A second signal wiring L 2  may transmit the first positive power voltage VDD 1  to the driving chip SIC. A third signal wiring L 3  may transmit the first negative power voltage VSS 1  to the driving chip SIC. A fourth signal wiring L 4  may transmit the second negative power voltage VSS 2  to the driving chip SIC. 
     In  FIG. 13 , EN 1  is an enable signal of the first data output block DB 1  representing driving timing of the first data output block DB 1  which outputs the data voltage. EN 2  is an enable signal of the second data output block DB 2  representing driving timing of the second data output block DB 2  which outputs the data voltage. EN 3  is an enable signal of the third data output block DB 3  representing driving timing of the third data output block DB 3  which outputs the data voltage. EN 4  is an enable signal of the fourth data output block DB 4  representing driving timing of the fourth data output block DB 4  which outputs the data voltage. 
     In the present exemplary embodiment, the first to fourth data output blocks DB 1  to DB 4  have driving timings different from one another. 
     In the present exemplary embodiment, when a distance of the data output block from the signal wiring L 1  to L 4  transmitting the power voltage to the driving chip SIC is relatively far, the driving timing of the data output block is relatively early. For example, the driving timing of the fourth data output block DB 4  may be earlier than the driving timing of the first output block DB 1  in the driving chip SIC. 
     Referring again to  FIG. 3 , when the second negative power voltage VSS 2  exceeds the error reference voltage Ver, the level of the second power voltage VSS 2  connected to the output electrodes of the first and second switching elements T 1  and T 2 , the first and second switching elements T 1  and T 2  may not be normally turned on. Thus, the level shifter  510  operates abnormally and the shift register  520  and the buffer  550  may operate abnormally. 
     The first to fourth data output blocks DB 1  to DB 4  of the driving chip SIC of the present exemplary embodiment are controlled to have driving timings different from one another. In  FIG. 13 , the C curve represents a waveform of the second negative power voltage VSS 2  of the driving chip SIC. 
     As shown in  FIG. 13 , the first to fourth data output blocks DB 1  to DB 4  of the driving chip SIC have driving timings different from one another so that the second negative power voltage VSS 2  does not exceed the error reference voltage Ver. Thus, the level shifter  510  and the shift register  520  operate normally. 
     According to the present exemplary embodiment, the plurality of the data output blocks DB 1  to DB 4  of the driving chip SIC have driving timings different from one another so that the second negative power voltage VSS 2  in the signal wiring is prevented from exceeding the error reference voltage Ver. Thus, driving reliability may be improved. 
     In addition, when the plurality of data output blocks DB 1  to DB 4  of the driving chip SIC have driving timings different from one another, the second negative power voltage VSS 2  in the signal wiring does not momentarily increase so that a relatively high resistance of the signal wiring is allowed. For example, when a thin and long signal wiring is employed, the width of a bezel of the display apparatus may decrease. 
       FIG. 14  is a plan view illustrating a driving chip and a wiring of a data driver according to an exemplary embodiment of the present invention.  FIG. 15  is a waveform diagram illustrating signals in the data driver of  FIG. 14 . 
     The method of driving the display panel and the display apparatus for performing the method are substantially the same as the method of driving the display panel and the display apparatus for performing the method of the previous exemplary embodiment explained with reference to  FIGS. 12 and 13  except that the signal wiring is connected to a central portion of the driving chip. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment of  FIGS. 12 and 13  and any repetitive explanation concerning the above elements will be omitted. 
     Referring to  FIGS. 1 to 3, 14 and 15 , the data driver  500  includes a single driving chip SIC. The driving chip SIC includes a plurality of data output blocks. For example, the driving chip SIC includes a plurality of data output blocks, and the driving chip SIC includes first to fourth data output blocks DB 1 , DB 2 , DB 3  and DB 4 . 
     The driving chip SIC may further include a control block CB. For example, the control block CB may control output timings of the data output blocks DB 1 , DB 2 , DB 3  and DB 4 . The control block CB may be disposed at a central portion of the driving chip SIC. The control block CB may be disposed between the second data output block DB 2  and the third data output block DB 3 . 
     Although the driving chip SIC includes four data output blocks in the present exemplary embodiment, the present invention is not limited to the number of data output blocks. 
     The data driver  500  includes signal wirings L 1 , L 2 , L 3  and L 4  for transmitting a power voltage to the driving chip SIC. In the present exemplary embodiment, the signal wiring L 1 , L 2 , L 3  and L 4  may be connected to the control block CB of the driving chip SIC. 
     For example, a first signal wiring L 1  may transmit the second positive power voltage VDD 2  to the driving chip SIC, a second signal wiring L 2  may transmit the first positive power voltage VDD 1  to the driving chip SIC, a third signal wiring L 3  may transmit the first negative power voltage VSS 1  to the driving chip SIC, and a fourth signal wiring L 4  may transmit the second negative power voltage VSS 2  to the driving chip SIC. 
     In  FIG. 15 , EN 1  is an enable signal of the first data output block DB 1  representing driving timing of the first data output block DB 1  which outputs the data voltage. EN 2  is an enable signal of the second data output block DB 2  representing driving timing of the second data output block DB 2  which outputs the data voltage. EN 3  is an enable signal of the third data output block DB 3  representing driving timing of the third data output block DB 3  which outputs the data voltage. EN 4  is an enable signal of the fourth data output block DB 4  representing driving timing of the fourth data output block DB 4  which outputs the data voltage. 
     In the present exemplary embodiment, the first to fourth data output blocks DB 1  to DB 4  have driving timings different from one another. 
     In the present exemplary embodiment, when a distance of the data output block from the signal wiring L 1  to L 4  transmitting the power voltage to the driving chip SIC is relatively far, the driving timing of the data output block is relatively early. For example, driving timings of the first and fourth data output blocks DB 1  and DB 4  may be earlier than driving timings of the second and third data output blocks DB 2  and DB 3  in the driving chip SIC. When a distance of the first data output block DB 1  from the signal wiring L 1  to L 4  is far compared to a distance of the fourth data output block DB 4  from the signal wiring L 1  to L 4 , the driving timing of the first data output block DB 1  is earlier than the driving timing of the fourth data output block DB 4 . When a distance of the first data output block DB 1  from the signal wiring L 1  to L 4  is substantially the same as a distance of the fourth data output block DB 4  from the signal wiring L 1  to L 4 , the driving timing of the first data output block DB 1  or the driving timing of the fourth data output block DB 4  may be set to be earlier than the other. Alternatively, when a distance of the first data output block DB 1  from the signal wiring L 1  to L 4  is substantially the same as a distance of the fourth data output block DB 4  from the signal wiring L 1  to L 4 , the driving timing of the first data output block DB 1  and the driving timing of the fourth data output block DB 4  may be set to be the same. 
     Referring again to  FIG. 3 , when the second negative power voltage VSS 2  exceeds the error reference voltage Ver, the level of the second power voltage VSS 2  connected to the output electrodes of the first and second switching elements T 1  and T 2 , the first and second switching elements T 1  and T 2  may not be normally turned on. Thus, the level shifter  510  operates abnormally and the shift register  520  and the buffer  550  may operate abnormally. 
     The first to fourth data output blocks DB 1  to DB 4 , respectively, of the driving chip SIC of the present exemplary embodiment are controlled to have driving timings different from one another. In  FIG. 15 , the C curve represents a waveform of the second negative power voltage VSS 2  of the driving chip SIC. 
     As shown in  FIG. 15 , the first to fourth data output blocks DB 1  to DB 4  of the driving chip SIC have driving timings different from one another so that the second negative power voltage VSS 2  does not exceed the error reference voltage Ver. Thus, the level shifter  510  and the shift register  520  operate normally. 
     According to the present exemplary embodiment, the plurality of data output blocks DB 1  to DB 4  of the driving chip SIC have driving timings different from one another so that the second negative power voltage VSS 2  in the signal wiring is prevented from exceeding the error reference voltage Ver. Thus, driving reliability may be improved. 
     In addition, when the plurality of data output blocks DB 1  to DB 4  of the driving chip SIC have driving timings different from one another, the second negative power voltage VSS 2  in the signal wiring does not momentarily increase so that a relatively high resistance of the signal wiring is allowed. For example, when a thin and long signal wiring is employed, the width of a bezel of the display apparatus may decrease. 
     According to the present invention as explained above, the data driver includes the plurality of data output blocks having driving timings different from one another so that driving reliability of the display apparatus may be improved and the width of the bezel may decrease. 
     The foregoing is illustrative of the present invention and is not to be construed as limiting thereof. Although exemplary embodiments of the present invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims. The present invention is defined by the following claims, with equivalents of the claims to be included therein.