Patent Publication Number: US-2023136392-A1

Title: Front-End Module Providing Enhanced Switching Speed

Description:
TECHNICAL FIELD 
     The present invention relates to a radio frequency circuit, and in particular, to a front-end module providing an enhanced switching speed in a radio frequency circuit. 
     BACKGROUND 
     A front-end module is a radio frequency circuit arranged between an antenna and a baseband circuit for transmitting or receiving RF signals. The front-end module typically includes radio frequency switches, filters, and power amplifiers. Front-end modules are used in various communication devices, such as mobile communications, wireless networks (Wi-Fi), Bluetooth, global positioning system (GPS), and so on. 
     With the continuous development in communication technology, the power demand for RF signals has increased significantly for expanding the radio coverage. As a consequence, the circuit area and insertion loss of the front-end module increase with the increase in the power of the RF signals to enhance isolation during transmitting and receiving the RF signals, resulting in an increase in manufacturing cost and a decrease in circuit performance. 
     SUMMARY 
     According to an embodiment of the invention, a front-end module includes a first radio frequency (RF) terminal, a second RF terminal, a third RF terminal, a transmission path, and a reception path. The transmission path is formed between the first RF terminal and the third RF terminal. The reception path is formed between the first RF terminal and the second RF terminal. The reception path includes a first set of switches, a first path, and a second path. The first set of switches includes a first terminal coupled to the first RF terminal, a second terminal, and a control terminal configured to receive a first control signal. The first set of switches is controlled to be on or off according to the first control signal. The first path includes a second set of switches and an amplifier. The second set of switches includes a first terminal coupled to the second terminal of the first set of switches, a second terminal, and a control terminal configured to receive a second control signal. The second set of switches is controlled to be on or off according to the second control signal. The amplifier includes an input terminal coupled to the second terminal of the second set of switches and configured to receive a receive signal, and an output terminal coupled to the second RF terminal and configured to output an amplified signal. The first path and the second path are coupled in parallel between the second terminal of the first set of switches and the second RF terminal. The second path includes a third set of switches, and the third set of switches include a first terminal coupled to the second terminal of the first set of switches, a second terminal coupled to the second RF terminal, and a control terminal configured to receive a third control signal. The third set of switches is controlled to be on or off according to the third control signal. When a transmission signal is transmitted to the first RF terminal via the transmission path, the first set of switches, the second set of switches, and the third set of switches are all turned off. 
     According to another embodiment of the invention, a front-end module includes a first RF terminal, a second RF terminal, a first set of switches, a second set of switches, and a third set of switches. The first set of switches includes a first terminal coupled to the first RF terminal, a second terminal, a control terminal configured to receive a first control signal, and at least one first transistor. The first set of switches is controlled to be on or off according to the first control signal. The second set of switches includes a first terminal coupled to the second terminal of the first set of switches, a second terminal, a control terminal configured to receive a second control signal, and at least one second transistor. The second set of switches is controlled to be on or off according to the second control signal. The third set of switches includes a first terminal coupled to the second terminal of the first set of switches, a second terminal coupled to the second RF terminal, and a control terminal configured to receive a third control signal, and at least one third transistor. The third set of switches is controlled to be on or off according to the third control signal. A size of each of the at least one second transistor and a size of each of the at least one third transistor are each less than a size of each of the at least one first transistor. 
     According to another embodiment of the invention, a front-end module includes a first RF terminal, a second RF terminal, a first set of switches, a second set of switches, a third set of switches, a first shunt path, and a second shunt path. The first set of switches includes a first terminal coupled to the first RF terminal, a second terminal, a control terminal configured to receive a first control signal, and at least one first transistor. The first set of switches is controlled to be on or off according to the first control signal. The second set of switches includes a first terminal coupled to the second terminal of the first set of switches, a second terminal, a control terminal configured to receive a second control signal, and at least one second transistor. The second set of switches is controlled to be on or off according to the second control signal. The third set of switches includes a first terminal coupled to the second terminal of the first set of switches, a second terminal coupled to the second RF terminal, and a control terminal configured to receive a third control signal, and at least one third transistor. The third set of switches is controlled to be on or off according to the third control signal. The first shunt path includes a first terminal coupled to the second terminal of the second set of switches, and a second terminal coupled to a reference voltage terminal. The second shunt path includes a first terminal coupled to the second terminal of the third set of switches, and a second terminal coupled to the reference voltage terminal. A quantity of the at least one second transistor is equal to a quantity of the at least one third transistor. When the first set of switches, the second set of switches, and the third set of switches are all turned off, a voltage across each of the at least one first transistor is substantially equal to a voltage across each of the at least one second transistor, and is substantially equal to a voltage across each of the at least one third transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram of a front-end module according to an embodiment of the invention. 
         FIG.  2    is a circuit diagram of a front-end module according to an embodiment of the invention. 
         FIG.  3    is an equivalent circuit diagram of the front-end module in  FIG.  2    when the reception path is not conductive. 
         FIG.  4    is a circuit diagram of a front-end module according to another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Below, exemplary embodiments will be described in detail with reference to accompanying drawings so as to be easily realized by a person having ordinary knowledge in the art. The inventive concept may be embodied in various forms without being limited to the embodiments set forth herein. Descriptions of well-known parts are omitted for clarity, and like reference numerals refer to like elements throughout. 
       FIG.  1    is a block diagram of a front-end module  1  according to an embodiment of the invention. The front-end module  1  may perform a transmission of a radio frequency (RF) signal Stx or an RF signal Srx. 
     As shown in  FIG.  1   , the front-end module  1  includes an antenna  10 , an RF terminal RF 1 , an RF terminal RF 2 , an RF terminal RF 3 , a transmission path Ptx, and a reception path Prx. The antenna  10  is coupled to the RF terminal RF 1 . The transmission path Ptx is formed between the RF terminal RF 1  and the RF terminal RF 3 , and the reception path Prx is formed between the RF terminal RF 1  and the RF terminal RF 2 . When transmitting the RF signal Stx, the transmission path Ptx is conductive and the reception path Prx is non-conductive. When receiving the RF signal Srx , the reception path Prx is conductive and the transmission path Ptx is non-conductive. The reception path Prx includes a first set of switches SW 1 , an amplification path Prx 1 , and a bypass path Prx 2 . In this embodiment, the RF signals Stx and Srx may be a transmit signal and a receive signal, respectively. 
       FIG.  2    is a circuit diagram of a front-end module according to an embodiment of the invention. 
     As shown in  FIG.  2   , the first set of switches SW 1  includes a first terminal, a second terminal, and a control terminal. The first terminal of the first set of switches SW 1  is coupled to the RF terminal RF 1 , and the control terminal of the first set of switches SW 1  is configured to receive the control signal Sc 1 . The first set of switches SW 1  is controlled to be on or off according to the control signal Sc 1 . The first set of switches SW 1  may include N cascoded transistors T 1 , where N is a positive integer and is determined by circuit requirements. In one embodiment, sizes of the multiple transistors T 1  may be equal. 
     Similar to the reception path Prx, the transmission path Ptx may include a fourth set of switches SW 4 . The fourth set of switches SW 4  includes a first terminal, a second terminal, and a control terminal. The first terminal of the fourth set of switches SW 4  is coupled to the RF terminal RF 1 , the second terminal of the fourth set of switches SW 4  is coupled to the RF terminal RF 3 , and the control terminal of the first set of switches SW 4  is configured to receive the control signal Sc 4 . The fourth set of switches SW 4  is controlled to be on or off according to the control signal Sc 4 . The fourth set of switches SW 4  may include at least one cascoded transistor T 4 , such as M cascoded transistors T 4 , where M is a positive integer and is determined by circuit requirements. In one embodiment, sizes of the multiple transistors T 4  may be equal. In some embodiments, the quantity M of the transistors T 4  in the fourth set of switches SW 4  is positively correlated to the maximum power of the RF signal Srx. Since breakdown voltages of respective transistors T 4  are substantially equal, e.g., between 2.5V and 3V, the larger the maximum power of the RF signal Srx is, the larger the quantity M of the cascoded transistors T 4  in the fourth set of switches SW 4  may be, so as to avoid break-down of the transmission path Ptx when receiving a high-power RF signal Srx. Similarly, the larger the maximum power of the RF signal Stx is, the larger the quantity N of the cascoded transistors T 1  in the first set of switches SW 1  may be, so as to avoid break-down of the reception path Prx when transmitting a high-power RF signal Stx. In some embodiments, N may be less than M, for example, N may be  6 , and M may be 8, but the invention is not limited thereto. In other embodiments, N may be equal to or greater than M, wherein the quantity N of the transistors T 1  in the reception path Prx may be selected according to the maximum power of the RF signal Stx, and the quantity M of the transistors T 4  in the transmission path Ptx may be selected according to the maximum power of the RF signal Srx. In further embodiments, the size of each transistor T 1  may be equal to the size of each transistor T 4 . 
     As shown in  FIGS.  1  and  2   , in the reception path Prx, the amplification path Prx 1  and the bypass path Prx 2  are coupled in parallel between the second terminal of the first set of switches SW 1  and the RF terminal RF 2 . The amplification path Prx 1  may be used to amplify the RF signal Srx to generate an amplified signal Samp, and transmit the amplified signal Samp to the RF terminal RF 2 . The bypass path Prx 2  may be a different signal path from the amplification path Prx 1 , and the bypass path Prx 2  may allow the RF signal Srx to pass to the RF terminal RF 2 . In an embodiment, the amplification path Prx 1  includes a second set of switches SW 2  and an amplifier AMP. The second set of switches SW 2  includes a first terminal coupled to the second terminal of the first set of switches SW 1 , and a control terminal configured to receive the control signal Sc 2 . The second set of switches SW 2  is controlled to be on or off according to the control signal Sc 2 . The amplifier AMP includes an input terminal and an output terminal. The input terminal of the amplifier AMP is coupled to the second terminal of the second set of switches SW 2  and is configured to receive the RF signal Srx. The output terminal of the amplifier AMP is coupled to the RF terminal RF 2  and is configured to output the amplified signal Samp. The bypass path Prx 2  includes a third set of switches SW 3 . The third set of switches SW 3  includes a first terminal, a second terminal, and a control terminal. The first terminal of the third set of switches SW 3  may be coupled to the second terminal of the first set of switches SW 1 , the second terminal of the third set of switches SW 3  may be coupled to the RF terminal RF 2 , and the control terminal of the third set of switches SW 3  may be configured to receive a control signal Sc 3 . The third set of switches SW 3  may be controlled to be on or off according to the control signal Sc 3 . In some embodiments, the second set of switches SW 2  may include at least one cascoded transistor T 2 , and the third set of switches SW 3  may include at least one cascoded transistor T 3 . As shown in  FIG.  2   , for example, the second set of switches SW 2  may include, but is not limited to, two transistors T 2 , and the third set of switches SW 3  may include, but is not limited to, two transistors T 3 . 
     In  FIG.  2   , the front-end module  1  may further include a shunt path SH 1 , a shunt path SH 2 , a shunt path SH 3 , and a shunt path SH 4 . 
     For example, when the RF signals Stx is being transmitted via the transmission path Ptx to the RF terminals RF 1 , the first set of switches SW 1 , the second set of switches SW 2 , and the third set of switches SW 3  may be all turned off, and the shunt path SH 1  and the shunt path SH 2  may be turned on. In such a case, sum of the quantity N of the transistors T 1  in switches SW 1  and the quantity P of the transistors T 2  in switches SW 2  (i.e., N+P) may be selected according to the maximum power of the RF signal Stx. 
     When the RF terminal RF 1  receives the RF signal Srx, the fourth set of switches SW 4  may be turned off In such a case, the first set of switches SW 1  and the second set of switches SW 2  may be used to control the conduction state of the amplification path Prx 1 , and the first set of switches SW 1  and the third set of switches SW 3  may be used to control the conduction state of the bypass path Prx 2 . As described further below, by arranging the parallel amplification path Prx 1  and the bypass path Prx 2 , and by further setting the sizes of the transistors in the second set of switches SW 2  and the third set of switches SW 3 , the front-end module  1  in the embodiment of the present invention may operate at a faster switching speed. 
     In some embodiments, the shunt path SH 1  includes a first terminal, a second terminal, and a control terminal. The first terminal of the shunt path SH 1  is coupled to the second terminal of the second set of switches SW 2 , the second terminal of the shunt path SH 1  is coupled to a reference voltage terminal GND, and the control terminal of the shunt path SH 1  is configured to receive a control signal Ss 1 . The shunt path SH 2  includes a first terminal, a second terminal, and a control terminal. The first terminal of the shunt path SH 2  is coupled to the second terminal of the third set of switches SW 3 , the second terminal of the shunt path SH 2  is coupled to the reference voltage terminal GND, and the control terminal of the shunt path SH 2  is configured to receive a control signal Ss 2 . The shunt path SH 1  may serve as a grounding path for the amplification path Prx 1 , and the shunt path SH 2  may serve as a grounding path for the bypass path Prx 2 . The shunt path SH 1  includes at least one transistor Ts 1 , and the shunt path SH 2  includes at least one transistor Ts 2 . In some embodiments, the control signal Sc 2  and the control signal Ss 1  may be complementary signals to each other, and the control signal Sc 3  and the control signal Ss 2  may be complementary signals to each other. For example, when the RF signal Stx is transmitted from the RF terminal RF 3  to the RF terminal RF 1  via the transmission path Ptx, the first set of switches SW 1  may be turned off according to the control signal Sc 1  at a low level, and the fourth set of switches SW 4  may be turned on according the control signal Sc 4  at a high level. In such a case, the second set of switches SW 2  and the third set of switches SW 3  may be turned off (e.g., each transistor T 2  and each transistor T 3  are turned off) according to the control signals Sc 2  and Sc 3  at the low level (e.g., 0V, or −3V) respectively, and the shunt path SH 1  and the shunt path SH 2  may be turned on according to the control signals Ss 1  and Ss 2  at the high level respectively. In the embodiment, various low levels of the control signals Sc 1 , Sc 2 , and Sc 3  are identical, for example, 0V or −3V. In other embodiments, various high levels of the control signals Sc 1 , Sc 2 , and Sc 3  are also identical. The specific voltage levels are examples and are not intended to limit the present invention. 
     When the RF signal Srx is transmitted from the RF terminal RF 1  to the RF terminal RF 2  via the reception path Prx, the first set of switches SW 1  is turned on according to the control signal Sc 1 , and the fourth set of switches SW 4  is turned off according to the control signal Sc 4 . In such a case, if the power of the RF signal Srx is insufficient, e.g., less than a predetermined power, signal amplification may be required, and the RF signal Srx may be transmitted via the amplification path Prx 1  where the second set of switches SW 2  is ON and the third set of switches SW 3  is OFF. In the embodiment, in order to reduce signal loss and/or power consumption, the shunt path SH 1  is OFF (e.g., non-conductive), and the shunt path SH 2  is ON (e.g., conductive). If the power of the RF signal Srx is sufficient, e.g., equal to or exceeding the predetermined power, signal amplification may be not required, and the RF signal Srx may be transmitted via the bypass path Prx 2  where the second set of switches SW 2  is OFF and the third set of switches SW 3  is ON. In the embodiment, in order to reduce signal loss and/or power consumption, the shunt path SH 1  is ON (e.g., conductive) , and the shunt path SH 2  is OFF (e.g., non-conductive). 
     In some embodiments, the shunt path SH 4  includes a first terminal, a second terminal, and a control terminal. The first terminal of the shunt path SH 4  is coupled to the second terminal of the fourth set of switches SW 4 , the second terminal of the shunt path SH 4  is coupled to the reference voltage terminal GND, and the control terminal of the shunt path SH 4  is configured to receive a control signal Ss 4 . The shunt path SH 4  may include at least one transistor Ts 4 . The shunt path SH 4  may serve as a grounding path for the transmission path Ptx. The control signal Sc 4  and the control signal Ss 4  may be complementary signals to each other. For example, when the fourth set of switches SW 4  in the transmission path Ptx is turned on according to the control signal Sc 4  at a high level, the shunt path SH 4  is turned off according to the control signal Ss 4  at a low level. When the fourth set of switches SW 4  in the transmission path Ptx is turned off according to the control signal Sc 4  at a low level, the shunt path SH 4  is turned on according to the control signal Ss 4  at a high level. In some embodiments, the reference voltage terminal GND may provide a reference voltage such as 0V. 
     As shown in  FIG.  2   , the quantity of the transistors T 2  in the second set of switches SW 2  is equal to the quantity of the transistors T 3  in the third set of switches SW 3 , and equal to P. In some embodiments, sum N+P=M, where N is the quantity of the transistors T 1 , P is the quantity of the transistors T 2  or T 3 , and M is the quantity of the transistors T 4 . For example, the quantity M of the transistors T 4  may be 8, and the quantity N of the transistors T 1  may be 6, and P=M−N may be 2. In another example, the quantity M of the transistors T 4  may be 8, the quantity N of the transistors T 1  may be 7, the quantity P of the transistors T 2  and the quantity of the transistors T 3  may each be 1 (=8−7). In another example, the quantity M of the transistors T 4  may be 8, the quantity N of the transistors T 1  may be 5, the quantity P of the transistors T 2  and the quantity of the transistors T 3  may each be 3 (=8−5). 
     However, the present disclosure may not be such limited. In other embodiments, sum N+P may be selected according to the maximum power of the RF signal Stx, and quantity M of the transistors T 4  may be selected according to the maximum power of the RF signal Srx. In the embodiments, the sum N+P may be greater than quantity M of the transistors T 4 , that is N+P&gt;M. 
     As described above, the size of each transistor T 2  may be equal, and the size of each transistor T 3  may be equal. In some embodiments, the size of each transistor T 2  and the size of each transistor T 3  may each be smaller than the size of each transistor T 1 . In another embodiment, a sum of the size of a transistor T 2  and the size of a transistor T 3  may be substantially equal to the size of a transistor T 1 . For example, the sum of the size of transistor T 2  and the size of transistor T 3  may be equal to the size of transistor T 1 +/−5%, +/−10%, or +/−50%. 
     In the embodiments, with lager-sized transistors arranged, the insertion loss and/or the noise figure may be reduced, but larger area may be taken up by the larger-sized transistors. Accordingly, the amplification path Prx 1  may be used to transmit the RF signal Srx having a lower power, and the bypass path Prx 2  may be used to transmit the RF signal Srx having a higher power. Therefore, taking account of the insertion loss/noise figure and the area of the amplification path Prx 1 , it may be configured that the transistors T 2  is larger-sized than the transistors T 3 . For example, when the size of the transistor T 1  is A, the size of the transistor T 2  may be 9A/10, and the size of the transistor T 3  may be A/10, but the present invention is not limited thereto. In other embodiments, the size of the transistor T 2  may be 8A/10, and the size of the transistor T 3  may be 2A/10. Alternatively, the size of the transistor T 2  may be 7A/10, and the size of the transistor T 3  may be 3A/10. Alternatively, the size of the transistor T 2  may be 6A/10, and the size of the transistor T 3  may be 4A/10. 
     In some embodiments, sizes of the transistors T 1 , T 2 , and T 3  may be positively correlated with finger widths thereof, respectively. For example, in an embodiment of the size of the transistor T 1  being A, the size of the transistor T 2  being 9A/10, and the size of the transistor T 3  being A/10, the transistor T 1  may occupy  100  fingers and the finger width may be 10 microns, the transistor T 2  may occupy 100 fingers and the finger width may be 9 microns, and transistor T 3  may occupy  100  fingers and the finger width may be 1 micron. Therefore, the size of T 1  may be 10 microns*100 fingers, the size of transistor T 2  may be 9 microns*100 fingers, and the size of transistor T 3  may be 1 micron*100 fingers. In other embodiments, the size of the transistors T 1 , T 2 , and T 3  may be positively correlated with the quantities of fingers thereof, respectively. For example, the transistors T 1  may occupy 100 fingers and the finger width may be 10 microns, the transistor T 2  may occupy 90 fingers and the finger width may be 10 microns, and the transistor T 3  may occupy 10 fingers and the finger width may be 10 micron. Therefore, the size of the transistors T 1  may be 10 microns*100 fingers, the size of the transistors T 2  may be 10 microns* 90  fingers, and the size of the transistors T 3  may be 10 microns*10 fingers. 
       FIG.  3    is an equivalent circuit diagram when the reception path Prx is non-conductive. In  FIG.  3   , M is equal to 8 and N is equal to 6. When the reception path Prx is non-conductive (e.g., OFF), the first set of switches SW 1 , the second set of switches SW 2 , and the third set of switches SW 3  are turned off, and the shunt paths SH 1 , SH 2  are turned on. The first set of switches SW 1  may be equivalent to 6 serially connected capacitors C 1 . Each capacitor C 1  corresponds to a turn-off transistor T 1  having a size of A. The second set of switches SW 2  may be equivalent to  2  serially connected capacitors C 2 . Each capacitor C 2  corresponds to a turn-off transistor T 2  having a size of 9A/10. The third set of switches SW 3  may be equivalent to 2 serially connected capacitors C 3 . Each capacitor C 3  corresponds to a turn-off transistor T 3  having a size of A/10. For the reception path Prx in  FIG.  3   , an equivalent capacitance thereof is equal to that of 8 serially connected capacitors having the size of A. In this embodiment, the voltages across respective capacitors C 1  are substantially equal. Similarly, the voltages across respective capacitors C 2  are substantially equal, and the voltages across respective capacitors C 3  are substantially equal. In another embodiment, the voltage across each capacitor C 1  is substantially equal to the voltage across each capacitor C 2 , and is substantially equal to the voltage across each capacitor C 3 . In some embodiments, the difference in voltages across any two of the capacitor C 1 , the capacitor C 2 , and the capacitor C 3  is within 1%. 
     Referring to  FIG.  2   , the amplification path Prx 1  may include a capacitor C and an inductor L coupled in series thereto. The capacitor C includes a first terminal and a second terminal. The first terminal of the capacitor C is coupled to the second terminal of the second set of switches SW 2 . The inductor L includes a first terminal and a second terminal. The first terminal of the inductor L is coupled to the second terminal of the capacitor C, and the second terminal of the inductor L is coupled to the input terminal of the amplifier AMP. There may or may not be other components present between the capacitor C and the inductor L. 
     The front-end module  1  may include a fifth set of switches SW 5  and a sixth set of switches SW 6  to enhance isolation between the bypass path Prx 2  and the amplification path Prx 1 . The sixth set of switches SW 6  includes a first terminal, a second terminal, and a control terminal. The first terminal of the sixth set of switches SW 6  is coupled to the output terminal of the amplifier AMP, the second terminal of the sixth set of switches SW 6  is coupled to the RF terminal RF 2 , and the control terminal of the sixth set of switches SW 6  is configured to receive a control signal Sc 6 . The sixth set of switches SW 6  is controlled to be on or off according to the control signal Sc 6 . The sixth set of switches SW 6  may include one or more transistors T 6 , e.g., 1 transistor T 6 . The fifth set of switches SW 5  includes a first terminal, a second terminal, and a control terminal. The first terminal of the fifth set of switches SW 5  may be coupled to the second terminal of the third set of switches SW 3 , the second terminal of the fifth set of switches SW 5  may be coupled to the RF terminal RF 2 , and the control terminal of the fifth set of switches SW 5  may be configured to receive a control signal Sc 5 . The fifth set of switches SW 5  may be controlled to be on or off according to the control signal Sc 5 . The fifth set of switches SW 5  may include one or more transistors T 5 , e.g., 2 cascoded transistors T 5 . When the RF signal Srx is transmitted to the RF terminal RF 2  via the amplification path Prx 1 , the sixth set of switches SW 6  is turned on, and the fifth set of switches SW 5  is turned off to prevent the signal from being transmitted via the bypass path Prx 2 . When the RF signal Srx is transmitted to the RF terminal RF 2  via the bypass path Prx 2 , the fifth set of switches SW 5  is turned on, and the sixth set of switches SW 6  is turned off to prevent the signal from being transmitted via the amplification path Prx 1 . 
     The front-end module  1  may further include a shunt path SH 3  including a first terminal, a second terminal, and a control terminal. The first terminal of the shunt path SH 3  is coupled to the RF terminal RF 2 , the second terminal of the shunt path SH 3  is coupled to the reference voltage terminal GND, and the control terminal of the shunt path SH 3  is configured to receive a control signal Ss 3 . When transmitting the RF signal Stx, the shunt path SH 3  may be turned on. The shunt path SH 3  includes at least one transistor Ts 3 . 
     Compared to the reception path including M transistors T 1 , the reception path Prx in the present invention includes a smaller quantity of N transistors T 1 . In some embodiments, during transmission of the RF signal Stx, the transmission path Ptx is conductive and reception path Prx is non-conductive, wherein the first set of switches SW 1 , the second set of switches SW 2  and the third set of switches SW 3  in the reception path Prx are all turned off, so that the power handling capability of the front-end module  1  at the time is determined by the first set of switches SW 1 , the second set of switches SW 2 , and the third set of switches SW 3 . It may be seen from the equivalent circuit in  FIG.  3    that, by configuring the M-N transistors T 2  and the M−N transistors T 3  each smaller than the size of the transistor T 1 , the switching speed may be increased without significantly affecting the power handling capability. 
       FIG.  4    is a schematic circuit diagram of another front-end module  3  according to an embodiment of the present invention. The front-end module  3  is similar to the front-end module  1 , except that the front-end module  3  further includes a filter  30  and a seventh set of switches SW 7 . The differences between the front-end module  3  and the front-end module  1  will be explained as follows. 
     The filter  30  is coupled between the second terminal of the first set of switches SW 1  and the first terminal of the second set of switches SW 2 . The seventh set of switches SW 7  is coupled in parallel to the filter  30 . The seventh set of switches SW 7  may include one or more transistors T 7 , e.g.,  1  transistor T 7 . 
     The filter  30  may be a low-pass filter to filter out noise from the RF signal Srx. When the power of the noise in the RF signal Srx exceeds a noise threshold, the seventh set of switches SW 7  may be turned off, so as to transmit the RF signal Srx via the filter  30  to the amplification path Prx 1  or the bypass path Prx 2 , reducing the noise while enhancing the signal quality. When the power of the noise in the RF signal Srx is less than the noise threshold, the seventh set of switches SW 7  may be turned on, so as to transmit the RF signal Srx to the amplification path Prx 1  or the bypass path Prx 2  without passing through the filter  30 , reducing the insertion loss resulted from the filter  30 . The filter  30  may be controlled to filter out the noise from the RF signal Srx or not according to the signal Sc 7 , so as to achieve a better signal quality or a reduced the insertion loss. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.