Patent Publication Number: US-10311964-B2

Title: Memory control circuit and memory test method

Description:
This application claims the benefit of Taiwan application Serial No. 105143402, filed Dec. 27, 2016, the disclosure of which is incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     The disclosure relates in general to a memory control circuit and a memory test method. 
     BACKGROUND 
     In personal computers or common hand-held smart mobile devices, the memory is an essential element. As the semiconductor technology is improved on manufacturing process and product yield rate, the memory efficiency is also advanced. 
     In the hand-held smart mobile device and the computer, multi-channel memory technology is used to improve the memory efficiency. In the multi-channel memory technology, a plurality of parallel memory channels are between the dynamic random access memory (DRAM) and the memory control circuit to improve data throughput. 
     Each channel of the multi-channel memory is independent. However, the access latency between the channels may be different due to manufacture process variations. Or, even for the same channel, the access latency may be varied because of the usage time, the temperature or the interface between the memory and the memory control circuit. 
     Built-in self-test (BIST) circuit is widely used in many memory products for memory test. BIST circuit can improve test quality with low test cost. 
     How to test the multi-channel memory in a low-cost, fast and accurate way is an important issue. 
     SUMMARY 
     According to one embodiment, a memory control circuit coupled to a multi-channel memory is provided. The memory control circuit includes: a plurality of channel controllers, coupled to a respective one of a plurality of channel memories of the multi-channel memory; and a built-in self-test (BIST) circuit, coupled to the channel controllers, the BIST circuit including a BIST controller and a plurality of command index registers, the BIST controller being coupled to the channel controllers, the command index registers being coupled to the BIST controller, the command index registers storing respective command indexes of the channel controllers. The BIST controller receives inform from at least two of the channel controllers which indicates that the informing at least two channel controllers already complete respective current test commands. When the BIST controller arbitrates, the BIST controller selects at least one channel controller from the informing at least two channel controllers, and based on the respective command index(es) of the selected at least one channel controller, the BIST controller sends respective next test command(s) to the selected at least one channel controller. 
     According to another embodiment, a multi-channel test method applied to a multi-channel memory is provided. The multi-channel memory is coupled to a plurality of channel controllers. The multi-channel test method includes: receiving inform from at least two of the channel controllers which indicates that the informing at least two channel controllers already complete respective current test commands; and arbitrating and selecting at least one channel controller from the informing at least two channel controllers, and based on respective command index(es) of the selected at least one channel controller, sending respective next test command(s) to the selected at least one channel controller. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a functional block diagram of a memory control circuit according to an embodiment of the disclosure. 
         FIG. 2  shows a flow chart of a multi-channel memory test method according to an embodiment of the disclosure. 
         FIG. 3  shows a flow chart of a multi-channel memory test method according to another embodiment of the disclosure. 
         FIG. 4  shows a test efficiency diagram for the multi-channel memory test method according to an embodiment of the disclosure. 
     
    
    
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
     DETAILED DESCRIPTION 
     Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the disclosure. Each of the disclosed embodiments has one or more technical features. In possible implementation, one skilled person in the art would selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure. 
       FIG. 1  shows a functional block diagram of a memory control circuit according to an embodiment of the disclosure. The memory control circuit  100  is coupled to and control a multi-channel memory  190 . The multi-channel memory  190  includes N channel memories  190 _ 1 - 190 _N (N being a natural number). 
     The memory control circuit  100  includes a built-in self-test (BIST) circuit  110  and N channel controllers  131 _ 1 - 131 _N. The BIST circuit  110  includes a receiving interface  111 , a BIST controller  113 , N command index registers  115 _ 1 - 115 _N, m data background generators  117 _ 1 - 117 _ m  and m comparators  119 _ 1 - 119 _ m  (m being a natural number and m being smaller or equal to N). 
     The first channel controller  131 _ 1  includes a first command buffer  133 _ 1 , a first read data buffer  135 _ 1 , a first write data buffer  137 _ 1  and a first finite state machine (FSM)  139 _ 1 . Similarly, the N-th channel controller  131 _N includes a N-th command buffer  133 _N, a N-th read data buffer  135 _N, a N-th write data buffer  137 _N and a N-th FSM  139 _N. Other channel controllers have the same or similar circuit configuration. 
     The receiving interface  111  is coupled to the BIST controller  113 . The receiving interface  111  receives a BIST command BIST_CMD. For example but not limited by, the receiving interface  111  serially receives the BIST command BIST_CMD. The BIST command BIST_CMD includes, for example, a test algorithm indication parameter. In an embodiment of the disclosure, there are many default test algorithms in the BIST controller  113 . Each test algorithm may include different number of test commands and different test command sequence from each other. For example but not limited by, in three default test algorithms of the BIST controller  113 , a first test algorithm includes R0R0R1R1W1W1W0W0 . . . , wherein “R0” refers to read 0 from the channel memory while “W1” refer to write 1 into the channel memory, and so on. A second test algorithm includes R1R1R0R0W1W1W0W0 . . . and a third test algorithm includes W1W1W0W0R1R1R0R0. The above description is for example and the disclosure is not limited. After the receiving interface  111  receives the BIST command BIST_CMD which includes a complete test algorithm indication parameter, the receiving interface  111  sends the BIST command BIST_CMD to the BIST controller  113 . Thus, the BIST controller  113  will determine which one of the default test algorithm is to be used in this test (for example, the second test algorithm is used), and the BIST controller  113  generates corresponding test commands to the channel controllers  131 _ 1 - 131 _N. In an embodiment of the disclosure, based on the BIST command BIST_CMD, the BIST controller  113  selects a default test algorithm and generates a plurality of sequential test commands until the test is complete. 
     The BIST controller  113  decodes based on the BIST command BIST_CMD which for example includes the test algorithm indication parameter, and the BIST controller  113  generates corresponding test commands to the channel controllers  131 _ 1 - 131 _N. When the BIST controller  113  sends the corresponding test commands to the channel controllers  131 _ 1 - 131 _N, the BIST controller  113  updates the command index registers  115 _ 1 - 115 _N. When the channel controllers  131 _ 1 - 131 _N complete the respective current test command, the channel controller informs the BIST controller  113 . If there is conflict between the channel controllers  131 _ 1 - 131 _N, the BIST controller  113  arbitrates. 
     The N command index registers  115 _ 1 - 115 _N are coupled to the BIST controller  113 . The N command index registers  115 _ 1 - 115 _N store the respective next test command indexes of the channel controllers  131 _ 1 - 131 _N. In an embodiment of the disclosure, because the access latency of each channel memory may be different from each other, the respective current test command perform by the channel memories may be different and thus the timing at which the channel memory completes the respective current test command may be different. 
     In the following, the second test algorithm is used as an example. In initialization of the test, the BIST controller  113  sets the respective current test command index of the N command index registers  115 _ 1 - 115 _N as “1”, which refers that the channel controllers  131 _ 1 - 131 _N will perform the first test command. For example but not limited by, the BIST controller  113  sends the first test command to the channel controllers  131 _ 1 - 131 _N and then the BIST controller  113  updates the respective current test command index of the N command index registers  115 _ 1 - 115 _N as “2”. Then, for example but not limited by, the first channel controller  131 _ 1  completes the first test command earliest among the channel controllers  131 _ 1 - 131 _N. The first channel controller  131 _ 1  returns and informs the BIST controller  113  (the channel controller which informs the BIST controller  113  may also be referred as “the informing channel controller”). The BIST controller  113  sends the second test command to the first channel controller  131 _ 1  and updates the current test command index of the command index register  115 _ 1  as “3” (while at this moment, the respective current test command indexes of the command index register  115 _ 2 - 115 _N are still “2”). When the third channel controller  131 _ 3  completes the first test command, the third channel controller  131 _ 3  returns and informs the BIST controller  113 . The BIST controller  113  sends the second test command to the third channel controller  131 _ 3  and updates the current test command index of the command index register  115 _ 3  as “3” (while at this moment, the respective current test command indexes of the command index register  115 _ 2 ,  115 _ 4 - 115 _N are still “2”), and so on. 
     In other words, in an embodiment of the disclosure, when the channel controller completes the current test command and informs the BIST controller  113 , the BIST controller  113  sends the respective next test command to the (informing) channel controller and updates the test command index of the corresponding command index register. 
     The m data background generators  117 _ 1 - 117 _ m  are coupled to the BIST controller  113 , and are for generating the write data or the expectation data. In an embodiment of the disclosure, them data background generators  117 _ 1 - 117 _ m  generate m different write data or m different expectation data. The m comparators  119 _ 1 - 119 _ m  are coupled to the BIST controller  113  and the m data background generators  117 _ 1 - 117 _ m . In executing the write test command, one or more or all of the m data background generators  117 _ 1 - 117 _ m  generate the write data (e.g. at most m different write data) and send the write data to one or more of the N channel controllers  131 _ 1 - 131 _N under control of the BIST controller  113 . In executing the read test command, one or more or all of the m data background generators  117 _ 1 - 117 _ m  generate the expectation data (e.g. at most m different expectation data) and the comparators  119 _ 1 - 119 _ m  compare the read data returned from one or more of the channel controllers  131 _ 1 - 131 _N with the expectation data to decide whether the read test is passed or failed. In an embodiment of the disclosure, the channel controllers  131 _ 1 - 131 _N may compare m different expectation data. 
     The command buffers  133 _ 1 - 133 _N are coupled to the BIST controller  113 . The command buffers  133 _ 1 - 133 _N are for buffering the test commands received from the channel controllers  131 _ 1 - 131 _N and for sending the test commands to the FSM  139 _ 1 - 139 _N. The read data buffers  135 _ 1 - 135 _N are coupled to the BIST controller  113  and are configured to buffer the data read from the channel memories  190 _ 1 - 190 _N. In executing the write test command, the write data is buffered in the write data buffers  137 _ 1 - 137 _N (which are coupled to the BIST controller  113 ) and written into the channel memories  190 _ 1 - 190 _N by the FSMs  139 _ 1 - 139 _N. 
     The FSMs  139 _ 1 - 139 _N are coupled to the command buffers  133 _ 1 - 133 _N, the read data buffers  135 _ 1 - 135 _N, the write data buffers  137 _ 1 - 137 _N and the channel memories  190 _ 1 - 190 _N. The FSMs  139 _ 1 - 139 _N perform read and/or write operations on the channel memories  190 _ 1 - 190 _N based on the test commands buffered in the command buffers  133 _ 1 - 133 _N. 
     In read test, based on the read test command, the FSMs  139 _ 1 - 139 _N buffer data read from the channel memories  190 _ 1 - 190 _N into the read data buffers  135 _ 1 - 135 _N. The FSMs  139 _ 1 - 139 _N inform the BIST controller  113  and return the read data back to the BIST controller  113 . 
     In write test, based on the write test command, the FSMs  139 _ 1 - 139 _N inform the BIST controller  113  and the BIST controller  113  sends the write data to the write data buffers  137 _ 1 - 137 _N. The FSMs  139 _ 1 - 139 _N further write the data buffered in the write data buffers  137 _ 1 - 137 _N to the channel memories  190 _ 1 - 190 _N. 
     Now refer to  FIG. 2 .  FIG. 2  shows a flow chart of a multi-channel memory test method according to an embodiment of the disclosure. In step  210 , the BIST controller  113  sends the first test command to all the channel controllers  131 _ 1 - 131 _N. 
     In step  220 , the BIST controller  113  is informed that at least one (or at least two) of the channel controllers  131 _ 1 - 131 _N already complete(s) the respective current test command. 
     In step  230 , the BIST controller  113  determines that whether the channel controller(s) which inform the BIST controller  113  have already completed all the test commands. 
     If yes in the step  230 , then the flow proceeds to the step  240 . If no in the step  230 , then the flow proceeds to the step  250 . 
     In step  240 , the BIST controller  113  determines that whether all the channel controllers  131 _ 1 - 131 _N have already completed all the test commands. If yes in step  240 , then the test flow ends. If no in step  240 , then the flow returns to the step  220 . 
     In step  250 , when arbitration by the BIST controller  113  is necessary (which means that there are more than one channel controllers concurrently inform the BIST controller  113 ), the BIST controller  113  selects at least one channel controller from the informing channel controller(s) (which inform the BIST controller  113 ). The BIST controller  113  further sends the respective next test command to the selected at least one channel controller based on the respective command index of the selected at least one channel controller. 
     In details, in step  250 , the BIST controller  113  determines whether conflict occurs. In other words, the BIST controller  113  determines that whether there are more than one channel controllers inform the BIST controller  113  about the complete of the respective current test command. If conflict between the channel controllers occurs, the BIST controller  113  arbitrates. In an embodiment of the disclosure, the arbitration mechanism of the BIST controller  113  is not specially defined. After the BIST controller  113  arbitrates, the BIST controller  113  sends the respective next test command to the selected channel controller(s). 
     For example, but not limited by, the BIST controller  113  is informed by the three channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5 . After arbitration, the BIST controller  113  selects the channel controller  131 _ 1 . Based on the command index of the command index register  115 _ 1 , the BIST controller  113  sends the next test command to the channel controller  131 _ 1 . 
     Now refer to  FIG. 3 .  FIG. 3  shows a flow chart of a multi-channel memory test method according to another embodiment of the disclosure. In step  310 , the BIST controller  113  sends the first test command to all the channel controllers  131 _ 1 - 131 _N. 
     In step  320 , the BIST controller  113  is informed that at least one (or at least two) of the channel controllers  131 _ 1 - 131 _N already complete(s) the respective current test command. In different cycles, the number of the informing channel controllers which concurrently complete the respective current test command may be different. For example, but not limited by, in a cycle, there are two channel controllers which concurrently complete the respective current test command and inform the BIST controller  113 . But in another cycle, there may be four channel controllers which concurrently complete the respective current test command and inform the BIST controller  113 . 
     In step  330 , the BIST controller  113  determines that whether the at least one (or the at least two) channel controller(s) which inform the BIST controller  113  have already completed all the test commands. 
     If yes in the step  330 , then the flow proceeds to the step  340 . If no in the step  330 , then the flow proceeds to the step  350 . 
     In step  340 , the BIST controller  113  determines that whether all the channel controller(s)  131 _ 1 - 131 _N have already completed all the test commands. If yes in step  340 , then the test flow ends. If no in step  340 , then the flow returns to the step  320 . 
     In step  350 , the BIST controller  113  determines whether the arbitration is necessary. In other words, the BIST controller  113  determines whether a parameter “k” is larger than a parameter “m”. The parameter “k” is a natural number which is smaller than or equal to N. The parameter “k” refers to the number of the different types of the current test commands completed by the informing channel controllers which concurrently inform the BIST controller  113  during the same cycle. The parameter “k” is variable. That is, the parameter “k” is the type number of the test commands completed by the channel controllers. The parameter “m” refers to that the BIST controller  113  is capable of concurrently sending “m” respective next test commands to the informing channel controllers. That is, the parameter “m” is a maximum type number of the test commands that the BIST controller may concurrently send (also referred as a maximum support command type number). In principle, the parameter “m” is fixed and is related to the hardware design of the memory control circuit. If the parameter “nn” is larger, the test efficiency of the memory control circuit  100  is better but the cost is also higher, and vice versa. Besides, in the step  310 , the BIST controller  113  sends the first test command to all the channel controllers, which means that all the channel controllers receive the same first test command. Thus, the step  310  meets the requirement of the parameter “m”. 
     If no in the step  350  (which means the BIST controller  113  determines that the number of the types of the completed test commands is not larger than the maximum type number of the test commands that the BIST controller  113  may concurrently send, or means the arbitration is not necessary), the flow proceeds to the step  360 . If yes in the step  350  (which means the BIST controller  113  determines that the number of the types of the completed test commands is larger than the maximum type number of the test commands that the BIST controller may concurrently send, or means the arbitration is necessary), the flow proceeds to the step  370 . 
     In step  360 , based on the respective command register of the at least one or at least two informing channel controllers, the BIST controller  113  sends “k” types of respective next test commands to the at least one or at least two informing channel controller(s). That is, in the step  360 , the BIST controller  113  determines that the BIST controller  113  is capable of sending the respective next test commands to all the at least one or at least two informing channel controller(s) of step  320 . In other words, the type number of the respective next test commands sent from the BIST controller  113  to the informing channel controller(s) is equal to the type number of the test commands completed by the informing channel controller(s). In one embodiment, there may be two or more channel controllers which concurrently complete the same test command. Thus, the channel controllers which concurrently complete the same test command may receive the same type of the respective next test command and accordingly, the number of the channel controllers which concurrently complete the test commands may be larger or equal to the number of the test command types which are concurrently completed by the channel controllers. 
     In step  370 , based on the respective command register of the selected channel controllers, the BIST controller  113  sends “m” respective next test commands to the selected channel controllers. In other words, in step  370 , the BIST controller  113  determines that the BIST controller  113  is not capable of concurrently sending “k” types of the respective next test commands (for example, due to the hardware limitation) to the informing channel controllers (because “k” is larger than “m”). Thus, the BIST controller  113  arbitrates, and based on the respective command register of the selected channel controllers, the BIST controller  113  sends “m” respective next test commands to the selected channel controllers. In other words, the BIST controller  113  sends to the selected channel controllers the respective next test commands whose type number matches the maximum support command type number. In one embodiment, there may be two or more channel controllers which concurrently complete the same test command. Thus, the selected channel controllers may receive the same type of the respective test commands. The number of the selected channel controllers may be larger than or equal to the maximum support command type number. 
     In another possible embodiment, in step  350 , it is determined that whether the BIST controller  113  is capable of concurrently sending the respective next test commands to the informing channel controller(s). If it is determined that the BIST controller  113  is capable of concurrently sending the respective next test commands to the informing channel controller(s), then based on the respective command indexes of the informing channel controllers, the BIST controller  113  sends the respective test commands to the informing channel controllers and updates the respective command indexes of the informing channel controllers. On the contrary, if it is determined that the BIST controller  113  is not capable of concurrently sending the respective next test commands to the informing channel controller(s), then the BIST controller  113  selects among the informing channel controllers, sends the respective test commands to the selected channel controllers based on the respective command indexes of the selected channel controllers, and updates the respective command indexes of the selected channel controllers. 
     Several examples are described in the following description for explanation. Example One: m=3, k=2. 
     In the step  320 , the BIST controller  113  is informed that the three channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5  concurrently complete their respective current test commands. For example, but not limited by, the respective current command indexes of the three channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5  are 5, 5 and 8. Based on this, the BIST controller  113  determines that the channel controllers  131 _ 1  and  131 _ 3  complete the fourth test command and the channel controller  131 _ 5  completes the seventh test command. The test commands (the fourth test command) completed by the channel controllers  131 _ 1  and  131 _ 3  are the same, which are different from the test command (the seventh test command) completed by the channel controller  131 _ 5 . Thus, the BIST controller  113  determines that the three channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5  which concurrently inform the BIST controller  113  have already completed two types of the test commands (i.e. the fourth test command and the seventh test command), i.e. k=2. If the three channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5  have not completed all the test commands yet, in the step  350 , the BIST controller determines that the arbitration is unnecessary because the parameter “k” (k=2) is smaller than the parameter “m” (m=3). 
     In the step  360 , based on the respective command indexes of the informing channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5 , the BIST controller  113  sends the respective next test commands to the channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5 . For example, the respective current command indexes of the three channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5  are 5, 5 and 8. Then, the BIST controller  113  sends the fifth test command to the channel controllers  131 _ 1  and  131 _ 3 , and sends the eighth test command to the channel controller  131 _ 5 . The BIST controller  113  further updates the respective command indexes of the informing channel controllers  131 _ 1 ,  131 _ 3  and  131 _ 5  as 6, 6 and 9. 
     Example Two: m=3, k=4. 
     In the step  320 , the BIST controller  113  is informed that the four channel controllers  131 _ 2 ,  131 _ 4 ,  131 _ 6  and  131 _ 8  concurrently complete their respective current test commands. The BIST controller  113  determines that the test commands completed by the four channel controllers  131 _ 2 ,  131 _ 4 ,  131 _ 6  and  131 _ 8  are different from each other (i.e. k=4). For example but not limited by, the respective current command indexes of the channel controllers  131 _ 2 ,  131 _ 4 ,  131 _ 6  and  131 _ 8  are 3, 5, 7 and 9. Based on this, the BIST controller  113  determines that the channel controllers  131 _ 2 ,  131 _ 4 ,  131 _ 6  and  131 _ 8  complete the second, the fourth, the sixth and the eight test commands, respectively. If the channel controllers  131 _ 2 ,  131 _ 4 ,  131 _ 6  and  131 _ 8  have not completed all the test commands yet, in the step  350 , the BIST controller  113  determines that the arbitration is necessary (because the parameter “k” (k=4) is larger than the parameter “m” (m=3)). That is, the BIST controller  113  is not capable of concurrently sending four different types of the next test commands to the channel controllers  131 _ 2 ,  131 _ 4 ,  131 _ 6  and  131 _ 8  (for example, this is beyond the hardware limitation). In the step  370 , the BIST controller  113  arbitrates that, for example but not limited by, the BIST controller  113  selects the channel controllers  131 _ 2 ,  131 _ 4  and  131 _ 6  from the channel controllers  131 _ 2 ,  131 _ 4 ,  131 _ 6  and  131 _ 8 . Based on the respective command indexes of the selected channel controllers  131 _ 2 ,  131 _ 4  and  131 _ 6 , the BIST controller  113  sends the respective next test commands to the channel controllers  131 _ 2 ,  131 _ 4  and  131 _ 6 . For example, the respective current command indexes of the selected channel controllers  131 _ 2 ,  131 _ 4  and  131 _ 6  are 3, 5 and 7. Then, the BIST controller  113  sends the third test command to the channel controller  131 _ 2 , and sends the fifth test command to the channel controller  131 _ 4 , and sends the seventh test command to the channel controller  131 _ 6 . The BIST controller  113  further updates the respective command indexes of the selected channel controllers  131 _ 2 ,  131 _ 4  and  131 _ 6  as 4, 6 and 8. The command index of the unselected channel controller  131 _ 8  is still “9” because the BIST controller  113  does not send the next test command to the unselected channel controller  131 _ 8 . 
     From the above description, in an embodiment of the disclosure, the BIST controller  113  may dynamically send the respective next test commands to the informing channel controllers in response to the inform from the one or more channel controllers. 
     Now, the test efficiency of the multi-channel memory test method according to an embodiment of the disclosure is described.  FIG. 4  shows a test efficiency diagram for the multi-channel memory test method according to an embodiment of the disclosure. 
     In here, taken as an example, “read 0 (R0)”, “write 1 (W1)” and “read 1 (R1)” test operations are performed on the first to the third channel memories and m=1. The latency tRTW of the read-to-write operation is one cycle. The latency tWTR of the write-to-read operation is one cycle. The latency tDQ of the data output is one cycle. Thus, the read/write latency of the first to the third channel memories are as table 1: 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 R0 
                 W1 
                 R1 
               
               
                   
                 RAL 
                 WAL 
                 RAL 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
            
               
                   
                 The first channel memory 
                 1 
                 2 
                 4 
               
               
                   
                 The second channel memory 
                 3 
                 2 
                 1 
               
               
                   
                 The third channel memory 
                 2 
                 1 
                 3 
               
               
                   
                   
               
            
           
         
       
     
     In table 1, “RAL” refers to the read access latency and “WAL” refers to the write access latency. 
     In  FIG. 4 , TEST_CMD_ 1 -TEST_CMD_ 3  is the test commands for the first to the third channel memories, respectively. DQ 1  refers to the signal on the data transmission line of the first channel controller  131 _ 1  and so are DQ 2  and DQ 3 . 
     The test time for the first channel memory is expressed as: (RAL+tDQ)+tRTW+WAL+tWTR+(RAL+tDQ)=(1+1)+1+2+1+(4+1)=11 (cycles). Similarly, the test time for the second channel memory is expressed as: (RAL+tDQ)+tRTW+WAL+tWTR+(RAL+tDQ)=(3+1)+1+2+1+(1+1)=10 (cycles). The test time for the third channel memory is expressed as: (RAL+tDQ)+tRTW+WAL+tWTR+tARB+(RAL+tDQ)=(2+1)+1+1+1+1+(3+1)=11 (cycles). 
     In the test time for the third channel memory, “tARB” refers to the arbitration latency time. In here, it is assumed that the first channel is given the high priority in the arbitration by the BIST controller and thus the third channel memory has to wait for one cycle for receiving the next test command (R1). 
     Table 2 shows the test efficiency between an embodiment of the disclosure and the test methods without applying the disclosure: 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Dedicated 
                 Shared 
                 Shared 
                   
               
               
                   
                 BIST 
                 BIST-serial 
                 BIST-parallel 
               
               
                   
                 (without 
                 (without 
                 (without 
               
               
                   
                 applying 
                 applying 
                 applying 
                 an 
               
               
                   
                 embodiment 
                 embodiment 
                 embodiment 
                 embodiment 
               
               
                   
                 of the 
                 of the 
                 of the 
                 of the 
               
               
                   
                 disclosure) 
                 disclosure) 
                 disclosure) 
                 disclosure 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 Test time 
                 11 cycles 
                 31 cycles 
                 13 cycles 
                 11 cycles 
               
               
                 The number 
                 3 
                 1   
                 1   
                 1 
               
               
                 of the BIST 
               
               
                 circuit 
               
               
                 The number 
                     3 times 
                 1 time  
                 1 time  
                 1 time  
               
               
                 of the total 
               
               
                 pins 
               
               
                 The test cost 
                 3 
                 2.8 
                 1.2 
                 1 
               
               
                   
               
            
           
         
       
     
     In table 2, in the “dedicated BIST” test method, each channel memory is allocated with a dedicated BIST circuit. In the “shared BIST-serial” test method, all the channel memories share the same BIST circuit and the test is performed in serial. The serial test refers to that, after all test commands on the current channel memory are completed, then the next channel memory is tested. In the “shared BIST-parallel” test method, all the channel memories share the same BIST circuit and the test is performed in parallel. The parallel test refers to that, after the current test command on all the channel memories is completed, then the next test command on all the channel memories is tested. 
     In general, the test cost is expressed as: (the number of the pins)*(the test time)*(the cost of the test machine per second). Thus, if the test cost of an embodiment of the disclosure is taken as a base, then the test cost for the other three test methods are 3 (times), 2.8 (times) and 1.2 (times), respectively. Thus, an embodiment of the disclosure may improve the test efficiency. 
     From the above description, the BIST method on the multi-channel memory is disclosed in embodiments of the disclosure. In the case that a single BIST circuit is used, no matter whether the access latency time for the different channel memories are the same or not, or no matter whether the access latency for the same channel memory is fixed or varied, the test method of an embodiment of the disclosure may be used to improve the test efficiency. Thus, the test method of an embodiment of the disclosure may improve the test speed and the test quality in low test cost and reduced test time. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.