Patent Publication Number: US-2021167018-A1

Title: 3DIC Architecture with Interposer or Bonding Dies

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/417,282, filed on May 20, 2019, and entitled “3DIC Architecture with Interposer for Bonding Dies,” which is a divisional of U.S. patent application Ser. No. 12/774,558, filed on May 5, 2010 (now U.S. Pat. No. 10,297,550, issued May 21, 2019), and entitled “3DIC Architecture with Interposer for Bonding Dies,” which application claims the benefit of U.S. Provisional Application No. 61/301,855 filed on Feb. 5, 2010, entitled “Logic Last 3DIC,” which applications are hereby incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to integrated circuits, and more particularly to the formation of three-dimensional integrated circuits (3DICs) comprising interposers and the method of forming the same. 
     BACKGROUND 
     Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area. 
     These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required. An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase. 
     Three-dimensional integrated circuits (3DICs) were thus formed, wherein two dies may be stacked, with through-silicon vias (TSVs) formed in one of the dies to connect the other die to a package substrate. The TSVs are often formed after the front-end-of-line (FEOL) process, in which devices, such as transistors, are formed, and possibly after the back-end-of-line (BEOL) process, in which the interconnect structures are formed. This may cause yield loss of the already formed dies. Further, since the TSVs are formed after the formation of integrated circuits, the cycle time for manufacturing is also prolonged. 
     SUMMARY 
     In accordance with one aspect, a device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure. 
     Other embodiments are also disclosed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIGS. 1A through 1I  are cross-sectional views of intermediate stages in the manufacturing of a three-dimensional integrated circuit (3DIC) in accordance with various embodiments, wherein dies are bonded onto both sides of an interposer; 
         FIGS. 2A through 2D  are cross-sectional views of intermediate stages in the manufacturing of a 3DIC in accordance with various embodiments, wherein a molding compound is used to form a planar surface for forming more large bumps; 
         FIGS. 3A through 3C  are cross-sectional views of intermediate stages in the manufacturing of a 3DIC in accordance with various embodiments, wherein a dummy silicon wafer is used to form a planar surface for forming more large bumps; 
         FIGS. 4A through 4E  are cross-sectional views of intermediate stages in the manufacturing of a 3DIC in accordance with various embodiments, wherein a die is located in an opening in an interposer; and 
         FIGS. 5A through 5D  are cross-sectional views of intermediate stages in the manufacturing of a 3DIC in accordance with various embodiments, wherein through-substrate vias in an interposer have different lengths. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure. 
     A novel three-dimensional integrated circuit (3DIC) and the method of forming the same are provided. The intermediate stages of manufacturing an embodiment are illustrated. The variations of the embodiment are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. 
     Referring to  FIG. 1A , substrate  10  is provided. Throughout the description, substrate  10  and the corresponding interconnect structures  12  and  32  (not shown in  FIG. 1A , please refer to  FIG. 1D  in combination are referred to as interposer wafer  100 . Substrate  10  may be formed of a semiconductor material, such as silicon, silicon germanium, silicon carbide, gallium arsenide, or other commonly used semiconductor materials. Alternatively, substrate  10  is formed of a dielectric material. Interposer wafer  100  is substantially free from integrated circuit devices, including active devices, such as transistors and diodes. Furthermore, interposer wafer  100  may include, or may be free from, passive devices, such as capacitors, resistors, inductors, varactors, and/or the like. 
     Front-side interconnect structure  12  is formed over substrate  10 . Interconnect structure  12  includes one or more dielectric layer  18 , and metal lines  14  and vias  16  in dielectric layer(s)  18 . Throughout the description, the side of interposer wafer  100  facing up in  FIG. 1A  is referred to as a front side and the side facing down is referred to as a backside. Metal lines  14  and vias  16  are referred to as front-side redistribution lines (RDLs). Further, through-substrate vias (TSVs)  20  are formed in substrate  10  to a predetermined depth, and may possibly penetrate some or all of dielectric layer(s)  18 . TSVs  20  are electrically coupled to front-side RDLs  14 / 16 . 
     Next, front-side (metal) bumps (or bond pads)  24  are formed on the front-side of interposer wafer  100  and are electrically coupled to TSVs  20  and RDLs  14 / 16 . In an embodiment, front-side metal bumps  24  are solder bumps, such as eutectic solder bumps. In alternative embodiments, front-side bumps  24  are copper bumps or other metal bumps formed of gold, silver, nickel, tungsten, aluminum, and alloys thereof. Front-side bumps  24  may protrude the surface of interconnect structure  12 . 
     Referring to  FIG. 1B , dies  22  are bonded to front-side bumps  24 . Dies  22  may be device dies comprising integrated circuit devices, such as transistors, capacitors, inductors, resistors (not shown), and the like, therein. Further, dies  22  may be logic dies comprising core circuits, and may be, for example, center processing unit (CPU) dies. The bonding between dies  22  and bumps  24  may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper) bonding. In alternative embodiments, dies  22  are not bonded at this time. Instead, dies  22  are bonded after the backside interconnect structure  32  ( FIG. 1D ) is formed, as will be discussed in detail hereinafter. Underfill  23  is dispensed into the gaps between dies  22  and interposer wafer  100  and is cured. 
     Referring to  FIG. 1C , carrier  26 , which may be a glass wafer, is bonded onto the front side of interposer wafer  100  through adhesive  28 . Adhesive  28  may be an ultra-violet (UV) glue, or formed of other known adhesive materials. A wafer backside grinding is performed to thin substrate  10  from the backside, until TSVs  20  are exposed. An etch may be performed to further reduce the surface of substrate  10  so that TSVs  20  protrude out of the back surface of the remaining portion of substrate  10 . 
     Next, as shown in  FIGS. 1D and 1E , backside interconnect structure  32  is formed to connect to TSVs  20 . In various embodiments, backside interconnect structure  32  may have a similar structure as front-side interconnect structure  12 , and may include metal bumps and one or more layer of RDLs. For example, backside interconnect structure  32  may include dielectric layer  34  on substrate  10 , wherein dielectric layer  34  may be a low-temperature polyimide layer, or may be formed of commonly known dielectric materials, such as spin-on glass, silicon oxide, silicon oxynitride, or the like. Dielectric layer  34  may also be formed using chemical vapor deposition (CVD). When the low-temperature polyimide is used, dielectric layer  34  also acts as a stress buffer layer. As shown in  FIG. 1E , under-bump metallurgy (UBM)  36  and backside metal bumps  38 A are then formed. Similarly, backside bumps  38 A may be solder bumps such as eutectic solder bumps, copper bumps, or other metal bumps formed of gold, silver, nickel, tungsten, aluminum, and/or alloys thereof. In an exemplary embodiment, the formation of UBM  36  and bumps  38 A may include blanket forming a UBM layer, forming a mask over the UBM layer with openings formed in the mask, plating bumps  38 A in the openings, removing the mask, and performing a flash etching to remove the portions of the blanket UBM layer previously covered by the mask. 
     Referring to  FIG. 1F , dies  50  are bonded to the backside of interposer wafer  100 . Dies  50  may be electrically coupled to dies  22  through front-side interconnect structure  12 , backside interconnect structure  32 , and TSVs  20 . Dies  22  and dies  50  may be different types of dies. For example, dies  22  may be logic dies, such as CPU dies, while dies  50  may be memory dies. 
     Next, as shown in  FIG. 1H , large bumps  38 B are formed on the backside of interposer wafer  100 , and are electrically coupled to backside interconnect structure  32 , TSVs  20  (not shown), and possibly dies  22  and  50 . Large bumps  38 B may be solder bumps formed of, for example, eutectic solder, although they may also be other types of bumps such as metal bonds. In alternative embodiments, the order for bonding dies  50  and forming large bumps  38 B may be reversed.  FIG. 1G  illustrates an alternative embodiment, wherein large bumps  38 B are formed first, followed by the bonding of dies  50  to form the structure shown in  FIG. 1H . In these embodiments, bumps  38 A (referred to as small bumps hereinafter) and large bumps  38 B may be formed simultaneously using a one-step bump formation process. 
     In  FIG. 1I , carrier  26  as shown in  FIG. 1H  is de-bonded, for example, by exposing UV glue  28  to a UV light, causing it to lose its adhesive property. Dicing tape  60  is then adhered to the front side of the resulting structure. Next, a dicing is performed along lines  62  to separate interposer wafer  100  and dies  22  and  50  bonded on interposer wafer  100  into a plurality of dies. Each of the resulting dies includes one of interposer die  100 ′, dies  22 , and dies  50 . 
     In  FIG. 1I , due to the existence of dies  50 , portions of the backside of interposer wafer  100  are not available for forming large bumps  38 B. In alternative embodiments shown in  FIGS. 2A through 2D , however, more large bumps  38 B may be formed since some of large bumps  38 B (denoted as  38 B′ as in  FIG. 2D ) may be formed vertically aligned to, and overlapping, dies  50 . A brief process flow is shown in  FIGS. 2A through 2D . The initial process steps of this embodiment may be essentially the same as shown in  FIGS. 1A  through  1 F, wherein small bumps  38 A for bonding dies  50  are formed, while large bumps  38 B are not formed at this time. Next, as shown in  FIG. 2A , dies  50  are bonded to the backside of interposer wafer  100 . Underfill  52  is filled into the gaps between dies  50  and interposer wafer  100 , and is then cured. 
     Referring to  FIG. 2B , molding compound  54  (alternatively referred to as an encapsulating material) is molded onto dies  50  and interposer wafer  100 . The top surface of molding compound  54  may be higher than, or level with, top surfaces of dies  50 . Referring to  FIG. 2C , deep vias  56  are formed to penetrate molding compound  54  and are electrically coupled to backside interconnect structure  32 . Next, interconnect structure  58 , which includes RDLs  49  electrically coupled to deep vias  56 , is formed, followed by the formation of UBMs (not marked) and large bumps  38 B. Again, a stress buffer layer, which may be formed of polyimide or solder resist, may be formed under the UBMs. It is observed that some of the large bumps  38 B (marked as  38 B′) may be formed directly over, and vertically overlapping, portions of dies  50 , and hence the number of large bumps  38 B is increased over that of the structure shown in  FIG. 1I . 
     In  FIG. 2D , carrier  26  is de-bonded. Dicing tape  60  is then adhered to the front side of the resulting structure. Next, a dicing is performed to separate interposer wafer  100  and dies  22  and  50  that are bonded onto interposer wafer  100  into a plurality of dies. 
       FIGS. 3A through 3C  illustrate yet another embodiment, the initial process steps of this embodiment may be essentially the same as shown in  FIGS. 1A-1F  and  FIG. 2A , wherein dies  50  are bonded onto interposer wafer  100 . Next, as shown in  FIG. 3A , dummy wafer  66  (wherein the material of dummy wafer  66  is also referred to as an encapsulating material) is bonded onto interposer wafer  100 . In an embodiment, dummy wafer  66  is a dummy silicon wafer. In alternative embodiments, dummy wafer  66  is formed of other semiconductor materials, such as silicon carbide, GaAs, or the like. Dummy wafer  66  may not have integrated circuit devices, such as capacitors, resistors, varactors, inductors, and/or transistors therein. In yet other embodiments, dummy wafer  66  is a dielectric wafer. Cavities  68  are formed in dummy wafer  66 . The size of cavities  68  is great enough to hold dies  50  therein. The bonding of dummy wafer  66  onto interposer wafer  100  may include oxide-to-oxide bonding. In an exemplary embodiment, before dummy wafer  66  is bonded onto interposer wafer  100 , oxide layer  69 , which may be formed of silicon oxide (such as a thermal oxide) is pre-formed on dummy wafer  66 , and oxide layer  70  is pre-formed on interposer wafer  100 . Oxide layer  69  is then bonded onto oxide layer  70  through oxide-to-oxide bonding. As a result, dies  50  are embedded in cavities  68 , and surface  72  of the resulting structure is flat. 
     Next, as shown in  FIG. 3B , TSVs  56  are formed to penetrate dummy wafer  66  and oxide layers  69  and  70 , and are electrically coupled to backside interconnect structure  32 . Next, interconnect structure  58 , which includes RDLs  49  electrically coupled to TSVs  56 , is formed, followed by the formation of UBMs (not marked) and large bumps  38 B. Again, large bumps  38 B include bumps  38 B′ formed directly over, and vertically overlapping, dies  50 . 
     In  FIG. 3C , carrier  26  is de-bonded. Dicing tape  60  is then adhered to a side of the resulting structure. Next, a dicing is performed to separate interposer wafer  100  and dies  22  and  50  bonded onto interposer wafer  100  into a plurality of dies. 
       FIGS. 4A through 4D  illustrate yet another embodiment, wherein dies  50  are located in the cavities in interposer wafer  100 . First, the structure shown in  FIG. 4A  is formed, wherein the formation process may be essentially the same as shown in  FIGS. 1A through 1E . Therefore, the formation details are not discussed herein. Next, as shown in  FIG. 4B , openings  74  are formed in interposer wafer  100 , for example, using wet etch or dry etch. This may be performed by forming and patterning photo resist  76  and then etching interposer wafer  100  through the openings in photo resist  76 . The etch may stop when front-side interconnect structure  12  is reached, or the portions of metal features in front-side interconnect structure  12  are exposed. The exposed metal structures in front-side interconnect structure  12  may act as bond pads. 
     In  FIG. 4C , dies  50  are inserted into openings  74  and bonded onto the metal features in front-side interconnect structure  12 . The bonding may be solder bonding, metal-to-metal bonding, or the like. Accordingly, dies  50  may be electrically coupled to dies  22  and TSVs  20 . Next, underfill  80  is filled into the remaining spaces in openings  74 . 
     Referring to  FIG. 4D , large bumps  38 B are formed. In alternative embodiments, large bumps  38 B are formed before the formation of openings  74  ( FIG. 4B ) and the bonding of dies  50 . In  FIG. 4E , dicing tape  60  is attached, and the 3DIC shown in  FIG. 4E  may be diced into individual dies. 
     In alternative embodiments, after the formation of the structure shown in  FIG. 4C , molding compound  54  ( FIGS. 2B-2D ) or dummy wafer  66  ( FIGS. 3A-3C ) is formed/bonded onto the structure shown in  FIG. 4C  and on the opposite side of interposer wafer  100  than dies  22 . The remaining process steps may be similar to what are shown in  FIGS. 2B-2D  and  FIGS. 3A-3C , and hence are not discussed herein. Further, in each of the above-discussed embodiments, dies  22  may be bonded onto interposer wafer  100  either before or after the bonding of dies  50 , and may be bonded after the formation of large bumps  38 B. 
     In above-discussed embodiments, TSVs  20  (for example, referring to  FIG. 1C ) in interposer wafer  100  may have a same length. In alternative embodiments, TSVs  20  may have different lengths.  FIGS. 5A through 5D  illustrate an exemplary embodiment for forming TSVs  20  with different lengths. Referring to  FIG. 5A , substrate  10  of interposer wafer  100  is provided, and interconnect structure  12  is formed over substrate  10 . Interconnect structure  12  includes UBMs and bumps (not marked). Next, as shown in  FIG. 5B , dies  22  are bonded onto interposer wafer  100 , and underfill  23  is also injected into the gaps between dies  22  and interposer wafer  100  and is cured. 
     Referring to  FIG. 5C , carrier  26 , which may be a glass wafer, is bonded onto the front side of interposer wafer  100  through adhesive  28 . A wafer backside grinding is performed to thin substrate  10  from the backside to a desirable thickness. Next, TSV openings (occupied by the illustrated TSVs  20 ) are formed to penetrate substrate  10 . Further, the TSV openings extend into dielectric layers  18  that are used for forming interconnect structure  12 . The TSV openings are then filled with a metallic material to form TSVs  20  and dielectric layer  25  for electrically insulating TSVs  20  from substrate  10 . In the resulting structure, metal features  88  (of interconnect structure  12 ) include metal features  88 A and  88 B, with metal features  88 A buried deeper inside dielectric layers  18  than metal features  88 B. In the formation of the TSV openings, metal features  88 A and  88 B may be used as etch stop layers, so that the etching of dielectric layers  18  stops at different depths. Accordingly, length L 1  ( FIG. 5D ) of TSVs  20 A is greater than length L 2  of TSVs  20 B. The subsequent process steps may be essentially the same as shown in  FIGS. 1E through 1I , or as shown in other embodiments, when applicable. 
     It is observed that in the embodiments (for example,  FIGS. 1I, 2D, 3C, and 4E ), no TSVs are needed, although they can be formed, in any of dies  22  and  50 . However, the devices in both dies  22  and  50  may be electrically coupled to large bumps  38 B and electrically coupled to each other. In conventional 3DICs, TSVs are formed after the formation of the integrated circuit devices in device dies. This results in the increase in the yield loss and the cycle time for packaging. In the embodiments, however, no TSVs are needed in any of device dies  22  and  50 , and the possible yield loss resulting from the formation of TSVs in device dies  22  and  50  is avoided. Further, the cycle time is reduced since interposer wafer  100  and the corresponding TSVs may be formed at the time dies  22  and  50  are formed. 
     Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.