Patent Publication Number: US-2022223548-A1

Title: Semiconductor Device and Method

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application claims the benefit of U.S. Provisional Application No. 63/137,362, filed on Jan. 14, 2021, entitled “An Asymmetric Cu Structure to Enable Better Coplanarity for Hybrid Bonding Process Applications,” which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS. 1 through 14  are cross-sectional views of intermediate stages in the manufacturing of semiconductor devices, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Various embodiments provide methods for forming different sized under-bump metallizations (UBMs) and conductive bumps, which have improved coplanarity, and semiconductor devices formed by the same. UBMs and conductive bumps having different widths may be used to provide different types of connections between semiconductor devices. However, forming UBMs and conductive bumps with different widths may result in upper extents of top surfaces of the conductive bumps being disposed at different levels. For example, if a conductive material for forming conductive bumps having a same thickness is deposited over two UBMs having the same height and different widths, a top surface of the conductive bump formed over the wider UBM may be disposed above a top surface of the conductive bump formed over the narrower UBM after the conductive material is reflowed. 
     In order to improve a coplanarity of top surfaces of the conductive bumps, first UBMs having relatively greater widths may be formed with concave upper surfaces, while second UBMs having relatively smaller widths may be formed with flat surfaces or convex upper surfaces. The conductive connectors formed over the first UBMs have a greater volume to fill relative to the conductive connectors formed over the second UBMs, thus the level of upper extents of top surfaces of the conductive connectors formed over the first UBMs is lowered with respect to the conductive connectors formed over the second UBMs. The first UBMs and the second UBMs may be formed using a plating process and the shapes of the top surfaces of the first UBMs and the second UBMs may be controlled based on a concentration of a leveling agent used in a plating solution and a current density applied during the plating process. The method for improving the coplanarity of the conductive bumps reduces yield loss caused by cold joints, solder bridges, and the like. This reduces device defects and increases throughput. Moreover, the first UBMs and the second UBMs may be formed simultaneously and the conductive connectors formed thereover are formed simultaneously, which reduces production time and costs. 
       FIGS. 1 through 14  illustrate cross-sectional views of intermediate stages in the formation of a device in accordance with some embodiments of the present disclosure. It is appreciated that although a device wafer and a device die are used as examples, the embodiments of the present disclosure may also be applied to form conductive features in other devices (e.g., package components) including, and not limited to, package substrates, interposers, packages, and the like. 
       FIG. 1  illustrates a cross-sectional view of a semiconductor device  100 . In some embodiments, the semiconductor device  100  is a device wafer including active devices and/or passive devices, which are represented as integrated circuit devices  104 . The semiconductor device  100  may be singulated to form a plurality of chips/dies  106  therefrom. In  FIG. 1 , a single die  106  is illustrated. In some embodiments, the semiconductor device  100  is an interposer wafer, which is free from active devices and may include passive devices. In some embodiments, the semiconductor device  100  is a package substrate strip, which includes a core-less package substrate or a cored package substrate with a core therein. In subsequent discussion, a device wafer is used as an example of the semiconductor device  100 , and the semiconductor device  100  may be referred to as a wafer. The embodiments of the present disclosure may also be applied to interposer wafers, package substrates, packages, or the like. 
     In some embodiments, the dies  106  are logic dies (e.g., central processing units (CPUs), graphics processing units (GPUs), system-on-chips (SoCs), application processors (APs), microcontrollers, application-specific integrated circuit (ASIC) dies, or the like), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, high bandwidth memory (HBM) dies, or the like), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies or the like), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof. 
     In some embodiments, the semiconductor device  100  includes a semiconductor substrate  102  and features formed at a top surface of the semiconductor substrate  102 . The semiconductor substrate  102  may be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The semiconductor substrate  102  may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or a glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the semiconductor substrate  102  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Shallow trench isolation (STI) regions (not separately illustrated) may be formed in the semiconductor substrate  102  to isolate active regions in the semiconductor substrate  102 . Vias (not separately illustrated) may be formed extending into the semiconductor substrate  102  or through the semiconductor substrate  102  (e.g., through-vias) and may be used to electrically inter-couple features on opposite sides of the semiconductor device  100 . 
     In some embodiments, the semiconductor device  100  includes integrated circuit devices  104 , which are formed on the top surface of semiconductor substrate  102 . The integrated circuit devices  104  may include complementary metal-oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and the like. The details of the integrated circuit devices  104  are not illustrated herein. In some embodiments, the semiconductor device  100  is used for forming interposers (which are free from active devices), and the semiconductor substrate  102  may be a semiconductor substrate or a dielectric substrate. 
     An inter-layer dielectric (ILD)  108  is formed over the semiconductor substrate  102  and fills spaces between gate stacks of transistors (not separately illustrated) in the integrated circuit devices  104 . In some embodiments, the ILD  108  is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, combinations or multiple layers thereof, or the like. The ILD  108  may be formed using spin coating, flowable chemical vapor deposition (FCVD), or the like. In some embodiments, the ILD  108  is formed using a deposition method such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like. 
     Contact plugs  110  are formed in the ILD  108  and electrically couple the integrated circuit devices  104  to overlying metal lines and/or vias. In some embodiments, the contact plugs  110  are formed of conductive materials, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), alloys or multiple layers thereof, or the like. The formation of the contact plugs  110  may include forming contact openings in the ILD  108 , filling the conductive materials into the contact openings, and performing a planarization process (such as a chemical mechanical polish (CMP) process, a mechanical grinding process, an etch-back process, or the like) to level top surfaces of the contact plugs  110  with top surfaces of the ILD  108 . 
     An interconnect structure  112  is formed over the ILD  108  and the contact plugs  110 . The interconnect structure  112  includes metal lines  114  and metal vias  116 , which are formed in dielectric layers  118  (also referred to as inter-metal dielectrics (IMDs)). The metal lines  114  that are formed at a same level are collectively referred to as a metal layer. In some embodiments, the interconnect structure  112  includes a plurality of metal layers including the metal lines  114  that are interconnected through the metal vias  116 . The metal lines  114  and the metal vias  116  may be formed of copper, copper alloys, other metals, or the like. 
     In some embodiments, the dielectric layers  118  are formed of low-k dielectric materials. The dielectric constants (k-values) of the low-k dielectric materials may be lower than about 3.0. The dielectric layers  118  may comprise carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), combinations or multiple layers thereof, or the like. In some embodiments, the dielectric layers  118  may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the dielectric layers  118  may comprise oxides (e.g., silicon oxide or the like), nitrides (e.g., silicon nitride or the like), combinations thereof, or the like. The dielectric layers  118  may be formed by FCVD, PECVD, LPCVD, or the like. In some embodiments, the formation of the dielectric layers  118  includes depositing a porogen-containing dielectric material in the dielectric layers  118  and then performing a curing process to drive out the porogen. As such, the dielectric layers  118  may be porous. 
     The formation of the metal lines  114  and the metal vias  116  in the dielectric layers  118  may include single damascene processes and/or dual damascene processes. In a single damascene process, a trench or a via opening is formed in one of the dielectric layers  118  and the trench or the via opening is filled with a conductive material. A planarization process, such as a CMP process, is then performed to remove excess portions of the conductive material, which may be higher than top surfaces of the dielectric layer  118 , leaving a metal line  114  or a metal via  116  in the corresponding trench or via opening. In a dual damascene process, a trench and a via opening are both formed in a dielectric layer  118 , with the via opening underlying and being connected to the trench. Conductive materials are filled into the trench and the via opening to form a metal line  114  and a metal via  116 , respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. 
     Top metal features  120  may be formed in a top dielectric layer  121 . The top metal features  120  may be formed of the same or similar materials and by the same or similar processes to the metal lines  114  and the metal vias  116  and the top dielectric layer  121  may be formed of the same or similar materials and by the same or similar processes to the dielectric layers  118 . The top metal features  120  may refer to a topmost layer of metallization in the interconnect structure  112 . Although  FIG. 1  illustrates the interconnect structure  112  as having a particular number of metallization layers, any number of metal layers may be included in other embodiments. The top dielectric layer  121  and the underlying dielectric layer  118  that is immediately underlying the top dielectric layer  121  may be formed as a single continuous dielectric layer, or may be formed as different dielectric layers using different processes, and/or formed of materials different from each other. 
     A first passivation layer  122  and a second passivation layer  124  may be formed over the interconnect structure  112 . The first passivation layer  122  and the second passivation layer  124  may be collectively referred to as the first passivation structure. In some embodiments, the first passivation layer  122  and the second passivation layer  124  may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the first passivation layer  122  and the second passivation layer  124  may include an inorganic dielectric material, which may include a material selected from silicon nitride (SiN x ), silicon oxide (SiO 2 ), silicon oxy-nitride (SiON x ), silicon oxy-carbide (SiOC x ), silicon carbide (SiC), combinations or multiple layers thereof, or the like. The first passivation layer  122  and the second passivation layer  124  may be formed of different materials. For example, the first passivation layer  122  may comprise silicon nitride (SiN) and the second passivation layer  124  may comprise undoped silicate glass (USG). In some embodiments, the first passivation layer  122  may comprise a single layer and the second passivation layer  124  may be omitted. In some embodiments, top surfaces of the top dielectric layer  121  and the top metal features  120  are coplanar (e.g., level with one another). Accordingly, the first passivation layer  122  and the second passivation layer  124  may be planar layers. In some embodiments, the top metal features  120  protrude higher than top surfaces of the top dielectric layer  121 , and the first passivation layer  122  and the second passivation layer  124  are non-planar. The first passivation layer  122  and the second passivation layer  124  may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. 
     In  FIG. 2 , openings  126  are formed in the first passivation layer  122  and the second passivation layer  124 . The openings  126  may be formed using an etching process, which may include a dry etching process. The etching process may include forming a patterned etching mask (not separately illustrated), such as a patterned photoresist, and then etching the first passivation layer  122  and the second passivation layer  124  using the patterned photoresist as a mask. The patterned etching mask is then removed. The openings  126  may be patterned through the first passivation layer  122  and the second passivation layer  124  and may expose the top metal features  120 . 
     In  FIG. 3 , a seed layer  128  is formed over the second passivation layer  124 , the first passivation layer  122 , and the top metal features  120  and in the openings  126 . The seed layer  128  may comprise a titanium layer and a copper layer over the titanium layer. In some embodiments, the seed layer  128  comprises a copper layer in contact with the second passivation layer  124 , the first passivation layer  122 , and the top metal features  120 . The seed layer  128  may be formed by a deposition process such as PVD, or the like. 
     In  FIG. 4 , a patterned photoresist  130  is formed over the seed layer  128 . The patterned photoresist  130  may be formed by depositing a photosensitive layer over the seed layer  128  using spin-on coating or the like. The photosensitive layer may then be patterned by exposing the photosensitive layer to a patterned energy source (e.g., a patterned light source) and developing the photosensitive layer to remove an exposed or unexposed portion of the photosensitive layer, thereby forming the patterned photoresist  130 . Openings  132 , which expose the seed layer  128 , are formed extending through the patterned photoresist  130 . The pattern of the patterned photoresist  130  corresponds to redistribution layers (RDLs) to be formed in the patterned photoresist  130 , as will be discussed below with respect to  FIG. 5 . 
     In  FIG. 5 , a conductive material  134  is formed over exposed portions of the seed layer  128  and filling the openings  126  and the openings  132 . The conductive material  134  may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material  134  may comprise a metal, such as copper, titanium, tungsten, aluminum, a combination or alloy thereof, or the like. The combination of the conductive material  134  and underlying portions of the seed layer  128  form an RDL  136 A and an RDL  136 B (collectively referred to as RDLs  136 ). Each of the RDLs  136  may include a via portion extending through the second passivation layer  124  and the first passivation layer  122  and a trace/line portion over the second passivation layer  124 . Although only two of the RDLs  136  are illustrated in  FIG. 5 , any number of the RDLs  136  may be formed over each of the dies  106 . 
     In  FIG. 6 , the patterned photoresist  130  and portions of the seed layer  128  on which the conductive material  134  is not formed are removed. The patterned photoresist  130  may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the patterned photoresist  130  is removed, exposed portions of the seed layer  128  are removed using an acceptable etching process, such as wet or dry etching. One or more optional cleaning processes may also be performed. 
     In  FIG. 7 , a third passivation layer  138 , a fourth passivation layer  140 , and a protection layer  142  are formed over the second passivation layer  124  and over and along sidewalls and top surfaces of the RDLs  136 . The third passivation layer  138  and the fourth passivation layer  140  may be collectively referred to as the second passivation structure. The third passivation layer  138  and the fourth passivation layer  140  may be formed of materials the same as or different from the materials of the first passivation layer  122  and the second passivation layer  124 . In some embodiments, the third passivation layer  138  and the fourth passivation layer  140  may be formed of inorganic dielectric materials, such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbide, combinations or multiple layers thereof, or the like. In some embodiments, the third passivation layer  138  may comprise silicon oxide and the fourth passivation layer  140  may comprise silicon nitride. The third passivation layer  138  may be made of materials that have a high etching selectivity from the material of the fourth passivation layer  140 , such that the third passivation layer  138  may act as an etch stop layer for a process used to etch the fourth passivation layer  140 . In some embodiments, the third passivation layer  138  may be a single layer, and the fourth passivation layer  140  may be omitted. The third passivation layer  138  and the fourth passivation layer  140  may be deposited by CVD, ALD, or the like. The third passivation layer  138  and the fourth passivation layer  140  may have a combined thickness T 1  ranging from about 0.5 μm to about 5.0 μm or from about 1.0 μm to about 2.5 μm. 
     The protection layer  142  is then formed over the fourth passivation layer  140 . In some embodiments, the protection layer  142  is formed of a polymer material (which may be photosensitive) such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), an epoxy, or the like. The protection layer  142  may be formed by CVD, PECVD, a spin-coating process, or the like. In some embodiments, the formation of the protection layer  142  includes coating the protection layer  142  in a flowable form, and then baking to harden the protection layer  142 . A planarization process, such as a CMP or a mechanical grinding process may be performed to level the top surface of the protection layer  142 . The protection layer  142  may have a height H 1  over the RDLs  136  ranging from about 1.0 μm to about 10 μm. The protection layer  142  may further have a height H 2  over the second passivation layer  124  between the RDLs  136  ranging from about 2 μm to about 40 μm or from about 4.5 μm to about 20 μm. 
     In  FIG. 8 , a first opening  144  and a second opening  146  are formed through the protection layer  142 , the fourth passivation layer  140 , and the third passivation layer  138  over the RDL  136 A and the RDL  136 B, respectively. In embodiments in which the protection layer  142  comprises a photosensitive material, the protection layer  142  may be patterned by exposing the protection layer  142  to a patterned energy source (e.g., a patterned light source) and developing the protection layer  142  to remove an exposed or unexposed portion of the protection layer  142 , thereby forming the first opening  144  and the second opening  146 . The first opening  144  and the second opening  146  may then be extended through the fourth passivation layer  140  and the third passivation layer  138  to expose the RDL  136 A and the RDL  136 B, respectively, using the protection layer  142  as a mask. The fourth passivation layer  140  and the third passivation layer  138  may be etched using any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch process may be anisotropic. 
     As illustrated in  FIG. 8 , the first opening  144  and the second opening  146  may have tapered sidewalls, which narrow in a direction toward the semiconductor substrate  102 . In some embodiments, the sidewalls of the first opening  144  and the second opening  146  may be substantially vertical or may be tapered and may widen in a direction toward the semiconductor substrate  102 . The first opening  144  may have a width W 1  level with a top surface of the protection layer  142  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm and a width W 2  level with a bottom surface of the third passivation layer  138  over the RDL  136 A ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The second opening  146  may have a width W 3  level with a top surface of the protection layer  142  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm and a width W 4  level with a bottom surface of the third passivation layer  138  over the RDL  136 B ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. Ratios of the width W 3  to the width W 1  and the width W 4  to the width W 2  may range from about 1.0 to about 8.0. The first opening  144  and the second opening  146  may have heights H 3  ranging from about 2 μm to about 40 μm or from about 4.5 μm to about 20 μm. In some embodiments, the first opening  144  is larger (e.g., wider) than the second opening  146 . For example, the width W 1  of the first opening  144  may be greater than the width W 3  of the second opening  146 , and the width W 2  of the first opening  144  may also be greater than the width W 4  of the second opening  146 . 
     The protection layer  142  may then be cured using a curing process. The curing process may comprise heating the protection layer  142  to a predetermined temperature for a predetermined period of time using an anneal process or other heating process. The curing process may also comprise an ultra-violet (UV) light exposure process, an infrared (IR) energy exposure process, combinations thereof, or a combination thereof with a heating process. Alternatively, the protection layer  142  may be cured using other methods. In some embodiments, the curing process is not included, or is performed before forming the first opening  144  and the second opening  146 . 
     In  FIG. 9 , a seed layer  148  is formed over the RDLs  136 , the third passivation layer  138 , the fourth passivation layer  140 , and the protection layer  142  and in the first openings  144  and the second openings  146 . The seed layer  148  may comprise a titanium layer and a copper layer over the titanium layer. In some embodiments, the seed layer  148  comprises a copper layer in contact with the RDLs  136 , the third passivation layer  138 , the fourth passivation layer  140 , and the protection layer  142 . The seed layer  148  may be formed by a deposition process such as PVD, or the like. As illustrated in  FIG. 9 , a bottom surface of the seed layer  148  in the first opening  144  may be level with a bottom surface of the seed layer  148  in the second opening  146 . The seed layer  148  includes horizontal portions extending along a top surface of the protection layer  142 , diagonal portions extending along sidewalls of the third passivation layer  138 , the fourth passivation layer  140 , and the protection layer  142 , and horizontal portions extending along top surfaces of the RDLs  136 . 
     In  FIG. 10 , a patterned photoresist  150  is formed over the seed layer  148 . The patterned photoresist  150  may be formed by depositing a photosensitive layer over the seed layer  148  using spin-on coating or the like. The photosensitive layer may then be patterned by exposing the photosensitive layer to a patterned energy source (e.g., a patterned light source) and developing the photosensitive layer to remove an exposed or unexposed portion of the photosensitive layer, thereby forming the patterned photoresist  150 . A first opening  152 A exposing the seed layer  148  over the RDL  136 A and a second opening  152 B exposing the seed layer  148  over the RDL  136 B are formed extending through the patterned photoresist  150 . The first opening  152 A and the second opening  152 B may be collectively referred to as openings  152 . The pattern of the patterned photoresist  150  corresponds to under-bump metallizations (UBMs) to be formed in the patterned photoresist  150 , as will be discussed below with respect to  FIG. 11 . 
     The first opening  152 A may have a width W 5  ranging from about 10 μm to about 90 μm and the second opening  152 B may have a width W 6  ranging from about 5 μm to about 80 μm. A ratio of the width W 5  of the first opening  152 A to the width W 6  of the second opening  152 B may range from about 1.5 to about 10 or from about 2 to about 5. In some embodiments, the first opening  152 A is larger (e.g., wider) than the second opening  152 B. For example, the width W 5  of the first opening  152 A may be greater than the width W 6  of the second opening  152 B. A ratio of an area of the first opening  152 A to an area of the second opening  152 B in a top-down view (not separately illustrated) may range from about 2.5 to about 16. Different types of UBMs may be subsequently formed in the first opening  152 A and the second opening  152 B and the dimensions of the first opening  152 A and the second opening  152 B may be based on the types of UBMs to be formed therein. In some embodiments, controlled collapse chip connection (C4) bumps may be formed in the first opening  152 A and micro bumps (μbumps) may be formed in the second openings  152 B. Forming the first opening  152 A and the second opening  152 B simultaneously, and subsequently forming the UBMs and the conductive contacts simultaneously, reduces the masks required to form the UBMs and the conductive contacts and reduces costs. 
     In  FIGS. 11A and 11B , a conductive material  154  is deposited in the first opening  152 A and the second opening  152 B. The conductive material  154  may be deposited by plating, such as electroplating or the like. The conductive material  154  may comprise a metal, such as copper (Cu), nickel (Ni), silver (Ag), combinations thereof, or the like. The combination of the conductive material  154  and underlying portions of the seed layer  148  form a first UBM  156 A in the first opening  152 A and a second UBM  156 B in the second opening  152 B (collectively referred to as UBMs  156 ). Conductive connectors (such as the conductive connectors  160 , discussed below with respect to  FIG. 13 ) may be subsequently formed on the UBMs  156  to provide external connection to the semiconductor device  100 . The UBMs  156  may include bump portions extending along a top surface of the protection layer  142 . The UBMs  156  may also include via portions in the first opening  144  and the second opening  146  (e.g., extending through the protection layer  142 , the fourth passivation layer  140 , and the third passivation layer  138 ) that are physically and electrically coupled to the RDLs  136 . As a result, the UBMs  156  are electrically coupled to devices (e.g., the integrated circuit devices  104  of the semiconductor substrate  102 ). 
     In embodiments in which the conductive material  154  is formed by a plating process, the dies  106  may be submerged in a plating solution. A direct current may be applied to the semiconductor substrate  102 . In embodiments in which the conductive material  154  comprises copper, the plating solution may comprise copper sulfate (CuSO 4 ), sulfuric acid (H 2 SO 4 ), and hydrochloric acid (HCl). The plating solution may further include additives, such as an accelerator agent, a suppressor agent, a leveling agent, combinations thereof, or the like. In some embodiments, the plating solution may comprise copper sulfate having a concentration ranging from about 20 g/L to about 175 g/L, sulfuric acid having a concentration ranging from about 50 g/L to about 300 g/L, hydrochloric acid having a concentration ranging from about 10 ppm to about 100 ppm, a leveling agent having a concentration ranging from about 5 cc/L to about 30 cc/L, an accelerator agent having a concentration ranging from about 5 cc/L to about 30 cc/L, and a suppressor agent having a concentration ranging from about 5 cc/L to about 30 cc/L. 
     The leveling agent may be adsorbed on surfaces of the conductive material  154  as the conductive material  154  is deposited. The leveling agent may prevent the conductive material  154  from being deposited with a top surface having a convex profile, with greater concentrations of the leveling agent resulting in the conductive material  154  being deposited with a less convex profile. For example, if the conductive material  154  is deposited with a plating solution that does not include the leveling agent, the conductive material  154  may have a convex top surface. As the concentration of the leveling agent present in the openings  152  increases, the conductive material  154  may be deposited with a less convex top surface such as a flat top surface or a concave top surface. 
     In some embodiments, the leveling agent may comprise polar molecules. For example, the leveling agent may include one or more halo-groups, such as a chloro-group or the like. Because the leveling agent includes polar molecules, the leveling agent may be attracted to the first opening  152 A and the second opening  152 B based on an electric field applied through the RDL  136 A and the RDL  136 B, respectively. The electric field applied through the RDL  136 A and the RDL  136 B is a result of the direct current being applied to the semiconductor substrate  102  during the electroplating. The magnitude of the electric field applied through the RDL  136 A and the RDL  136 B depends on the areas of the RDL  136 A and the RDL  136 B and the applied current density. The first opening  152 A has an area larger than the second opening  152 B, resulting in the electric field applied in the first opening  152 A being greater than the electric field applied in the second opening  152 B. This causes a greater concentration of the leveling agent to be present in the first opening  152 A than the second opening  152 B. As a result, more of the leveling agent is adsorbed on the conductive material  154  in the first opening  152 A than the second opening  152 B and the first UBM  156 A is formed with a less convex surface than the second UBM  156 B. This is illustrated by the first UBM  156 A being formed with a concave surface in the embodiments illustrated in  FIGS. 11A and 11B , and the second UBM  156 B being formed with a more convex surface (e.g., a flat surface in the embodiment illustrated in  FIG. 11A  and a convex surface in the embodiment illustrated in  FIG. 11B ). The conductive material  154  may be plated using a current density ranging from about 1 amp/dm 2  (ASD) to about 15 ASD. The area of the first opening  152 A is from about 5 to about 16 times greater than the area of the second opening  152 B (e.g., in a top-down view) such that the current applied in the first opening  152 A may be from about 5 to about 16 times greater than the current applied in the second opening  152 B. 
     The surface profiles of the UBMs  156  illustrated in  FIGS. 11A and 11B  may be the result of including different concentrations of the leveling agent in the plating solution, applying different current densities, combinations thereof, or the like. For example, the surface profiles illustrated in  FIG. 11A  may be achieved by including higher concentrations of the leveling agent and/or using higher current densities with respect to the embodiment illustrated in  FIG. 11B . For the embodiment illustrated in  FIG. 11A , a concentration of the leveling agent in the plating solution may range from about 5 cc/L to about 30 cc/L and a current density ranging from about 1 ASD to about 15 ASD may be applied to the dies  106 . For the embodiment illustrated in  FIG. 11B , a concentration of the leveling agent in the plating solution may range from about 5 cc/L to about 30 cc/L and a current density ranging from about 1 ASD to about 15 ASD may be applied to the dies  106 . The current density may be adjusted by altering the direct current applied to the semiconductor substrate  102 . 
     In the embodiment illustrated in  FIG. 11A , the first UBM  156 A has the width W 5  over the protection layer  142  ranging from about 10 μm to about 90 μm, the width W 1  level with a top surface of the protection layer  142  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm, and a bottom surface of the first UBM  156 A has the width W 2  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The first UBM  156 A has a height H 4  over the protection layer  142  ranging from about 5 μm to about 18 μm. The top surface of the first UBM  156 A is concave such that a distance D 1  between an upper extent of the first UBM  156 A and a lower extent of the top surface of the first UBM  156 A ranges from about 0.1 μm to about 10 μm or from about 0.5 μm to about 6 μm. The second UBM  156 B has the width W 6  over the protection layer  142  ranging from about 5 μm to about 50 μm, the width W 3  level with a top surface of the protection layer  142  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm, and a bottom surface of the first UBM  156 A has the width W 4  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The second UBM  156 B has a height H 5  over the protection layer  142  ranging from about 5 μm to about 18 μm. The top surface of the second UBM  156 B may be substantially planar. In some embodiments, the height H 5  of the second UBM  156 B may be equal to the height H 4  of the first UBM  156 A. In some embodiments, the height H 5  of the second UBM  156 B is greater than the height H 4  of the first UBM  156 A, with the height H 4  of the first UBM  156 A being within about 3 μm or about 6 μm of the height H 5  of the second UBM  156 B. In the embodiment illustrated in  FIG. 11A , the top surface of the second UBM  156 B may be level with or above the upper extent of the top surface of the first UBM  156 A and above the lower extent of the top surface of the first UBM  156 A. Providing the first UBM  156 A and the second UBM  156 B with heights within the prescribed ranges helps to ensure that upper extents of subsequently deposited conductive connectors (such as the conductive connectors  160 , discussed below with respect to  FIG. 13 ) are within a desired range of one another, which helps to improve coplanarity of the conductive connectors; reduces the risk of cold joints, solder bridges, and the like; and reduces device defects and yield losses. 
     In the embodiment illustrated in  FIG. 11B , the first UBM  156 A has the width W 5  over the protection layer  142  ranging from about 10 μm to about 90 μm, the width W 1  level with a top surface of the protection layer  142  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm, and a bottom surface of the first UBM  156 A has the width W 2  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The first UBM  156 A has a height H 6  over the protection layer  142  ranging from about 5 μm to about 18 μm. The top surface of the first UBM  156 A is concave such that a distance D 2  between an upper extent of the first UBM  156 A and a lower extent of the top surface of the first UBM  156 A ranges from about 0.1 μm to about 10 μm or from about 0.5 μm to about 6 μm. The second UBM  156 B has the width W 6  over the protection layer  142  ranging from about 5 μm to about 80 μm, the width W 3  level with a top surface of the protection layer  142  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm, and a bottom surface of the first UBM  156 A has the width W 4  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. The second UBM  156 B has a height H 7  over the protection layer  142  ranging from about 5 μm to about 18 μm. The top surface of the second UBM  156 B may be convex. The top surface of the second UBM  156 B is convex such that a distance D 4  between an upper extent of the second UBM  156 B and a lower extent of the top surface of the second UBM  156 B is less than about 0.1 μm. The height H 7  of the second UBM  156 B may be greater than the height H 6  of the first UBM  156 A. In some embodiments, the top surface of the second UBM  156 B may extend above the top surface of the first UBM  156 A a distance D 3  ranging from about 0.01 μm to about 3 μm. In the embodiment illustrated in  FIG. 11B , the upper extent of the top surface of the second UBM  156 B may be above the upper extent of the top surface of the first UBM  156 A, the lower extent of the top surface of the second UBM  156 B may be level with or above the upper extent of the top surface of the first UBM  156 A, and the lower extent of the top surface of the second UBM  156 B may be above the lower extent of the top surface of the first UBM  156 A. Although the first UBM  156 A is illustrated as having angular surfaces and transitions between surfaces, the top surface of the first UBM  156 A may have a rounded profile in the cross-sectional view of  FIGS. 11A and 11B . 
     Conductive materials (e.g., a solder material) may be subsequently deposited over the UBMs  156  and reflowed to form conductive connectors. Because of the greater width of the first UBM  156 A with respect to the second UBM  156 B, reflowing the conductive materials to form the conductive connectors may result in the conductive connector formed over the first UBM  156 A having a tendency to have a greater height than the conductive connector formed over the second UBM  156 B. However, by forming the first UBM  156 A with a concave top surface and the second UBM  156 B with a flat or a convex top surface, this height difference is corrected for and the conductive connectors may be subsequently formed with top surfaces having upper extents at the same level or closer to the same level. Specifically, the more concave profile of the first UBM  156 A provides a greater volume for the conductive connector formed over the first UBM  156 A to fill relative to the conductive connector formed over the second UBM  156 B, which lowers the top surface of the conductive connector formed over the first UBM  156 A relative to the conductive connector formed over the second UBM  156 B. This results in the top surfaces of the conductive connectors being closer to coplanar, reduces yield losses due to cold joints and solder bridges, and reduces device defects. Moreover, because the first UBM  156 A and the second UBM  156 B are formed simultaneously, less masks are required compared to other methods for improve the coplanarity of the conductive connectors, which reduces production time and costs. 
     In  FIG. 12 , a first conductive material  158 A and a second conductive material  158 B (collectively referred to as a conductive material  158 ) are deposited over the first UBM  156 A in the first opening  152 A and the second UBM  156 B in the second opening  152 B, respectively. In some embodiments, the conductive material  158  is formed by evaporation, electroplating, printing, solder transfer, ball placement, or the like. The conductive material  158  may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, multiple layers or combinations thereof, or the like. The conductive material  158  may be deposited in the first opening  152 A and the second opening  152 B simultaneously and may be deposited to a thickness ranging from about 3 μm to about 20 μm. 
     As illustrated in  FIG. 12 , the conductive material  158  may be deposited conformally, such that a top surface of the first conductive material  158 A has a similar profile to the top surface of the first UBM  156 A and a top surface of the second solder material  158 B has a similar profile to the top surface of the second UBM  156 B. As a result, the first conductive material  158 A may have a concave top surface and the second conductive material  158 B may have a flat top surface or a convex top surface. Because of the greater width of the first UBM  156 A with respect to the second UBM  156 B, reflowing the conductive material  158  may result in the first conductive material  158 A having a tendency to have a greater height than the second conductive material  158 B. However, by forming the first UBM  156 A with a concave top surface and the second UBM  156 B with a flat or a convex top surface, this height difference is corrected for and the conductive material  158  may be reflowed to form conductive connectors (such as the conductive connectors  160 , discussed below with respect to  FIG. 13 ) having upper extents of top surfaces at the same level or closer to the same level. Specifically, the more concave profile of the first UBM  156 A provides a greater volume for the first conductive material  158 A to fill during the reflow relative to the second conductive material  158 B, which lowers the upper extent top surface of the conductive connector formed over the first UBM  156 A relative to the conductive connector formed over the second UBM  156 B. This results in the upper extents of the top surfaces of the conductive connectors being closer to coplanar, reduces yield losses due to cold joints and solder bridges, and reduces device defects. Moreover, the first conductive material  158 A and the second conductive material  158 B are formed simultaneously, reducing production time and costs. 
     In  FIG. 13 , the patterned photoresist  150  and portions of the seed layer  148  on which the conductive material  154  is not formed are removed and a reflow is performed on the first conductive material  158 A and the second conductive material  158 B (illustrated in  FIG. 12 ). The patterned photoresist  150  may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the patterned photoresist  150  is removed, exposed portions of the seed layer  148  are removed using an acceptable etching process, such as wet or dry etching. 
     The reflow may be used to shape the first conductive material  158 A and the second conductive material  158 B into a first conductive connector  160 A and a second conductive connector  160 B, respectively (collectively referred to as conductive connectors  160 ). As illustrated in  FIG. 13 , the conductive connectors  160  may have a spherical shape. The conductive connectors  160  may be ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, micro bumps, or the like. In some embodiments, first conductive connector  160 A may be a C4 bump and the second conductive connector  160 B may be a micro bump. 
     Because of the greater width of the first UBM  156 A with respect to the second UBM  156 B, reflowing the conductive material  158  may result in the first conductive connector  160 A having a tendency to have a greater height than the second conductive connector  160 B. However, by forming the first UBM  156 A with a concave top surface and the second UBM  156 B with a flat or a convex top surface, this height difference is corrected for and the conductive material  158  may be reflowed to form the first conductive connector  160 A and the second conductive connector  160 B having top surfaces with upper extents at the same level or close to the same level. Although the upper extents of the top surfaces of the first conductive connector  160 A and the second conductive connector  160 B are illustrated as being level in  FIG. 13 , a difference in levels of the upper extents of the top surfaces of the first conductive connector  160 A and the second conductive connector  160 B may range from the first conductive connector  160 A being disposed above the second conductive connector  160 B by about 3 μm to the second conductive connector  160 B being disposed above the first conductive connector  160 A by about 3 μm or from the first conductive connector  160 A being disposed above the second conductive connector  160 B by about 8 μm to the second conductive connector  160 B being disposed above the first conductive connector  160 A by about 5 μm. Maintaining the upper extents of the top surfaces of the first conductive connector  160 A and the second conductive connector  160 B within this range of one another may sufficiently improve the coplanarity of the first conductive connector  160 A and the second conductive connector  160 B, which reduces solder bridging, cold joints, and the like. This reduces device defects, reduces device yield loss, and improves device performance. Moreover, the first conductive material  158 A and the second conductive material  158 B are formed simultaneously, reducing production time and costs. 
       FIG. 14  illustrates an embodiment in which the protection layer  142  is omitted. As illustrated in  FIG. 14 , the seed layer  148  of the UBMs  156  may be formed directly on a top surface of the fourth passivation layer  140 . The UBMs  156  may include horizontal portions extending along the top surface of the fourth passivation layer  140 . The steps for forming the UBMs  156  and the conductive connectors  160  may be the same as those discussed above, with only the steps of depositing and patterning the protection layer  142  being omitted. Omitting the protection layer  142  may provide better contact resistance between the UBMs  156  and the underlying RDLs  136 , and reduces costs associated with forming the protection layer  142 . 
       FIG. 15  illustrates an embodiment in which via portions of the UBMs  156  have the same widths. The UBMs  156  illustrated in  FIG. 15  may be formed by forming the first opening  144  and the second opening  146  illustrated in  FIG. 8  with the same widths, then proceeding with the steps illustrated in  FIGS. 9 through 13 . As illustrated in  FIG. 15 , the via portions of the UBMs  156  may have widths W 7  level with a top surface of the protection layer  142  ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm and widths W 8  level with a bottom surface of the third passivation layer  138  over the RDL  136 A ranging from about 5 μm to about 80 μm or from about 10 μm to about 50 μm. 
     As discussed previously, the shape and profile of a concave portion of the first UBM  156 A is caused by the width W 5  of the first opening  152 A (illustrated in  FIG. 10 ), the concentration of the leveling agent present when forming the first UBM  156 A, and the current applied when forming the first UBM  156 A. As such, the shape and profile of the concave portion of the first UBM  156 A may be controlled independent from the shape and profile of the via portion of the first UBM  156 A. As illustrated in  FIG. 15 , a centerline of a via portion C 1  of the first UBM  156 A may be offset or misaligned from a centerline of a bump portion C 2  of the first UBM  156 A. A centerline of a concave portion C 3  of the first UBM  156 A may be aligned with the centerline of the bump portion C 2  of the first UBM  156 A and offset or misaligned with the centerline of the via portion C 1  of the first UBM  156 A. Further, in the embodiment illustrated in  FIG. 15 , the concave portion of the first UBM  156 A may have a width that is greater than a width of the via portion of the first UBM  156 A. Forming the first UBM  156 A according to the above-described embodiments allows for the shape and profile of the concave portion of the first UBM  156 A to be set independently of the shape and profile of the underlying via portion of the first UBM  156 A, which provides for greater flexibility in forming the first UBM  156 A. 
     Embodiments may achieve various advantages. For example, forming different UBMs having different widths with different surface profiles improves the coplanarity of conductive connectors subsequently formed over the UBMs. This helps to prevent solder bridges, cold joints, and the like, increases throughput, and reduces device defects. Moreover, the UBMs as well as the conductive connectors may be formed simultaneously, which reduces production time and costs. 
     In accordance with an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex. In an embodiment, the first UBM structure has a first width greater than a second width of the second UBM structure. In an embodiment, the first UBM includes a via portion extending through the first passivation layer, and a centerline of the via portion is misaligned with a centerline of a concave portion of the top surface of the first UBM structure. In an embodiment, the first UBM includes a via portion extending through the first passivation layer, and a width of the via portion is less than a width of a concave portion of the top surface of the first UBM structure. In an embodiment, the semiconductor device further includes a polymer layer over the first passivation layer, the first UBM structure and the second UBM structure extending through the polymer layer, the UBM structure having a first height over the polymer layer, the second UBM structure having a second height over the polymer layer, and a difference between the first height and the second height being less than 3 μm. In an embodiment, the semiconductor device further includes a first conductive connector over the first UBM structure, an upper extent of a top surface of the first UBM structure being disposed a first distance over a top surface of the first passivation layer; and a second conductive connector over the second UBM structure, an upper extent of a top surface of the second UBM structure being disposed a second distance over the top surface of the first passivation layer, and a difference between the first distance and the second distance being less than 4 μm. In an embodiment, an upper extent of the top surface of the first UBM structure is level with an upper extent of the top surface of the second UBM structure. 
     In accordance with another embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, a top surface of the first UBM structure being concave, and the first UBM structure having a first width; and a second UBM structure over and electrically coupled to the second redistribution line, a bottom surface of the second UBM structure being level with a bottom surface of the first UBM structure, the second UBM structure having a second width less than the first width, and a top surface of the second UBM structure being less concave than the top surface of the first UBM structure. In an embodiment, the top surface of the second UBM structure is flat. In an embodiment, the top surface of the second UBM structure is convex. In an embodiment, the semiconductor device further includes a first passivation layer over the first redistribution line and the second redistribution line, the first UBM structure and the second UBM structure extending through the first passivation layer, the first UBM structure and the second UBM structure including horizontal portions extending along a top surface of the first passivation layer. In an embodiment, the semiconductor device further includes a first passivation layer over the first redistribution line and the second redistribution line; and a polymer layer over the first passivation layer, the first UBM structure and the second UBM structure extending through the polymer layer and the first passivation layer, and the first UBM structure and the second UBM structure including horizontal portions extending along a top surface of the polymer layer. In an embodiment, an upper extent of the top surface of the first UBM structure is level with an upper extent of the top surface of the second UBM structure. 
     In accordance with yet another embodiment, a method includes forming a first conductive feature and a second conductive feature over a semiconductor substrate; depositing a passivation structure over the first conductive feature and the second conductive feature; forming a patterned photoresist over the passivation structure, the patterned photoresist including a first opening over the first conductive feature and a second opening over the second conductive feature; and simultaneously electroplating a first under-bump metallurgy (UBM) structure in the first opening and a second UBM structure in the second opening, the first UBM structure being electrically coupled to the first conductive feature, the second UBM structure being electrically coupled to the second conductive feature, and a surface profile of the first UBM structure being different from a surface profile of the second UBM structure. In an embodiment, the first UBM structure is electroplated with a concave surface profile, and the second UBM structure is electroplated with a flat or convex surface profile. In an embodiment, the first opening has a first area greater than a second area of the second opening in a top-down view. In an embodiment, electroplating the first UBM structure and the second UBM structure includes applying a current with a density from  1  ASD to  15  ASD. In an embodiment, electroplating the first UBM structure and the second UBM structure includes applying an electroplating solution in the first opening and the second opening, the electroplating solution including a leveling agent, a greater concentration of the leveling agent being adsorbed on a surface of the first UBM structure than a surface of the second UBM structure. In an embodiment, the method further includes simultaneously depositing a conductive material over the first UBM structure and the second UBM structure; and reflowing the conductive material to form a first conductive connector over the first UBM structure and a second conductive connector over the second UBM structure. In an embodiment, electroplating the first UBM structure and the second UBM structure includes applying an electroplating solution in the first opening and the second opening, the electroplating solution including a leveling agent, the leveling agent including chlorine, the leveling agent having a concentration in the electroplating solution ranging from 5 cc/L to 30 cc/L. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.