Patent Publication Number: US-9431252-B2

Title: Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same

Description:
This application is a continuation application of U.S. patent application Ser. No. 13/718,992, filed on Dec. 18, 2012, entitled “Tunneling Field Effect Transistor (TFET) Formed By Asymmetric Ion Implantation and Method of Making Same,” which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Advances in the semiconductor industry have reduced the size of transistors in integrated circuits (ICs) to 32 nanometers and smaller. The decrease in transistor sizes leads to decreases in power supply voltage to the transistors. As the power supply voltage has decreased, the threshold voltage of the transistors in the ICs has also decreased. 
     Lower threshold voltages are difficult to obtain in a conventional metal-oxide-semiconductor field-effect transistor (MOSFET). Indeed, as the threshold voltage is reduced the ratio of on current to off current (I on /I off ) also decreases. The on current refers to the current through the MOSFET when an applied gate voltage is above the threshold voltage, and the off current refers to current through the MOSFET when the applied gate voltage is below the threshold voltage. 
     The on current to off current ratio may be improved by using a tunneling field-effect transistor (TFET). The TFET takes advantage of band-to-band tunneling (BTBT) to increase the achievable on current (I on ), which permits further reductions in threshold voltage, power supply voltage, and transistor size. Unfortunately, forming the source, which has one doping type, and the drain, which has another doping type, in the TFET such that the source and drain are both suitably self-aligned with the gate stack is challenging. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which: 
         FIG. 1  is a cross section of an embodiment TFET having a drain and a source that are both self-aligned with a gate stack; 
         FIGS. 2 a -2 i    collectively illustrate a method of forming the embodiment TFET of  FIG. 1 ; 
         FIG. 3  illustrates an embodiment method of forming the TFET of  FIG. 1 ; and 
         FIG. 4  illustrates another embodiment method of forming the TFET of  FIG. 1 . 
     
    
    
     Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. 
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The making and using of embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure. 
     The present disclosure will be described with respect to embodiments in a specific context, namely a tunneling field effect transistor (TFET). The concept may also be applied, however, to other integrated circuits (e.g., a fin field effect transistor (FinFET), a planar metal-oxide-semiconductor field-effect transistor (MOSFET), a double-gate MOSFET, a tri-gate MOSFET, etc.) and electronic structures. 
     Referring now to  FIG. 1 , an embodiment TFET  10  is illustrated. As shown, the TFET  10  includes a substrate  12  supporting a source  14  with a first doping type (e.g., p-type) and a drain  16  with a second doping type (e.g., n-type) on opposing sides of a channel region  18  in the substrate  12 . In an embodiment, the channel region  18  is disposed in a fin of a FinFET device as opposed to the TFET  10  of  FIG. 1 . In an embodiment, the source  14  is disposed in a first source/drain region  20  of the substrate  12  and the drain  16  is disposed in a second source/drain region  22  of the substrate  12 . In an embodiment, the substrate  12  is formed from silicon, a silicon-containing material, an intrinsic silicon, and so on. 
     Still referring to  FIG. 1 , the TFET  10  also includes a gate stack  24 . In an embodiment, the gate stack  24  is a metal gate/high-k (MG/HK) gate stack. As shown, the source  14  is disposed on a first side  26  of the gate stack  24  while the drain  16  is disposed on a second side  28  of the gate stack  24 . In addition, and as will be more fully explained below, each of the source  14  and the drain  16  is self-aligned with the gate stack  24 . In other words, a periphery of the source  14  closest to the channel  18  is generally vertically-aligned with a first sidewall  30  of the gate stack  24 . Likewise, a periphery of the drain  16  closest to the channel  18  is generally vertically-aligned with a second sidewall  32  of the gate stack  24 . 
     In an embodiment, the gate stack  24  includes a gate dielectric layer  34  (e.g., a gate oxide layer), a gate polysilicon  36 , and an oxide mask  38 . As shown, in an embodiment the gate dielectric layer  34  extends over the source  14 , the channel region  18  of the substrate  12 , and the drain  16 . In addition, the gate polysilicon  36  is disposed over the gate dielectric layer  34  while the oxide mask  38  is disposed over and/or around the gate polysilicon  36 . 
     Referring now to  FIGS. 2 a -2 i   , an embodiment method of forming the TFET  10  of  FIG. 1  is collectively illustrated. As shown in  FIG. 2 a   , the method begins by forming the gate stack  24  over the substrate  12 . In an embodiment, the gate stack  24  is a metal gate/high-k (MG/HK) gate stack. In an embodiment, the gate stack  24  is formed using a gate first integration flow. In an embodiment, the gate stack  24  is formed using a gate last integration flow. In an embodiment, the gate stack  24  is employed in a multi-gate transistor having a plurality of sources, drains, and channels. In other words, the gate stack  24  extends over a plurality of channels supported. In another embodiment, the gate stack  24  is a polysilicon gate as described above. 
     Still referring to  FIG. 2 a   , a nitride layer  40  is formed over the gate stack  24 . In an embodiment, the nitride layer  40  is a low-temperature nitride film. Moving now to  FIG. 2 b   , germanium ions (Ge+) are implanted in the nitride layer  40  (as indicated by the arrows). As shown, in an embodiment the germanium ions are implanted in a direction that forms an acute angle with a top surface  42  of the substrate  12 . 
     Referring now to  FIG. 2 c   , the germanium-implanted portions  44  of the nitride layer  40  ( FIG. 2 b   ) are removed to form an asymmetric nitride spacer  46 , which may be formed from the low-temperature nitride. In an embodiment, the germanium-implanted portions  44  of the nitride layer  40  are removed by a plasma etching process. In an embodiment, the germanium-implanted portions  44  of the nitride layer  40  are selectively removed using fluoride (F), carbon (C), and/or hydrogen (H) containing plasmas such as, for example, mixtures of CF 4 /CHF 3 , CH 2 F 2 , CH 3 F, Argon (Ar), and so on. The selectivity of ion implanted nitride film versus deposited nitride film may be 3:1 or higher due to the reactivity of F-bonding with more dangling bonds of SiNx, i.e., amorphized nitride film. In an embodiment, the germanium-implanted portions  44  of the nitride layer  40  are removed by a plasma etching process. The geranium-implanted portions  44  etch away faster than the portions of the nitride layer  40  that are not exposed to the germanium implantation. In an embodiment, the asymmetric nitride spacer  46  is supported by the gate dielectric layer  34  and abuts the second sidewall  32  of the gate stack  24 . 
     As shown in  FIG. 2 c   , the asymmetric nitride spacer  46  is confined to the second side  28  of the gate stack  24 . In this configuration, the asymmetric nitride spacer  46  protects or covers the second source/drain region  22  of the substrate  12  from an ion implantation. However, the asymmetric nitride spacer  46  does not overlap a top surface  48  of the gate stack  24 . In other words, the asymmetric nitride spacer  46  does not cover or protect the top surface  48  of the gate stack  24 . In addition, the asymmetric nitride spacer  46  also leaves the first source/drain region  20  of the substrate  12  on the first side  26  of the gate stack  24  unprotected or uncovered. 
     Referring now to  FIG. 2 d   , p-type impurities (as indicated by the arrows) are implanted in the first source/drain region  20  of the substrate  12  on the first side  26  of the gate stack  24 , which is unprotected by the asymmetric nitride spacer  46 , to form the source  14 . In an embodiment, the p-type impurities may be boron, boron-based molecules (e.g., FxBy molecules or molecular clusters), indium, and so on. After the source  14  has been formed, the asymmetric nitride spacer  46  is removed as shown in  FIG. 2 e   . In an embodiment, the asymmetric nitride spacer  46  is removed using a wet etching process. 
     Referring now to  FIGS. 2 f -2 i   , the process flow generally repeats with a different doping in order to form the drain  16 . Indeed, as shown in  FIG. 2 f   , another nitride layer  40  is formed over the gate stack  24 . As before, the nitride layer  40  may be a low-temperature nitride film. Moving now to  FIG. 2 g   , germanium ions (Ge+) are implanted in the nitride layer  40  (as indicated by the arrows). As shown, in an embodiment the germanium ions are implanted in a direction that forms an acute angle with the top surface  48  of the substrate  12 . Notably, the acute angle of implantation in  FIG. 2 g    may be the same or different than the acute angle of implantation in  FIG. 2   b.    
     Referring now to  FIG. 2 h   , the germanium-implanted portions  44  of the nitride layer  40  ( FIG. 2 g   ) are removed to form an asymmetric nitride spacer  46 , which may be formed from the low-temperature nitride. In an embodiment, the germanium-implanted portions  44  of the nitride layer  40  are removed by a plasma etching process. The geranium-implanted portions  44  etch away faster than the portions of the nitride layer  40  that are not exposed to the germanium implantation. In an embodiment, the asymmetric nitride spacer  46  is supported by the gate dielectric layer  34  and abuts the first sidewall  30  of the gate stack  24 . 
     As shown in  FIG. 2 h   , the asymmetric nitride spacer  46  is confined to the first side  26  of the gate stack  24 . In this configuration, the asymmetric nitride spacer  46  protects or covers the first source/drain region  20  of the substrate  12  and the source  14  from an ion implantation. However, the asymmetric nitride spacer  46  does not overlap the top surface  48  of the gate stack  24 . In other words, the asymmetric nitride spacer  46  does not cover or protect the top surface  48  of the gate stack  24 . In addition, the asymmetric nitride spacer  46  also leaves the second source/drain region  22  of the substrate  12  on the second side  28  of the gate stack  24  unprotected or uncovered. 
     Referring now to  FIG. 2 i   , n-type impurities (as indicated by the arrows) are implanted in the first source/drain region  20  of the substrate  12  on the first side  26  of the gate stack  24 , which is unprotected by the asymmetric nitride spacer  46 , to form the drain  16 . In an embodiment, the n-type impurities may be phosphorus, arsenic, antimony, and so on. After the drain  16  has been formed, the asymmetric nitride spacer  46  is removed as shown in  FIG. 1 . In an embodiment, the asymmetric nitride spacer  46  is removed using a wet etching process. 
     Referring now to  FIG. 3 , an embodiment method  50  of forming an integrated circuit (e.g., the TFET  10  of  FIG. 1 ) is provided. In block  52 , a first nitride layer is formed over a gate stack supported by a substrate. In block  54 , germanium ions are implanted in the first nitride layer in a direction forming an acute angle with a top surface of the substrate. In block  56 , germanium-implanted portions of the first nitride layer are etched away to form a first asymmetric nitride spacer confined to a first side of the gate stack. The first asymmetric nitride spacer protects a first source/drain region of the substrate from a first ion implantation. In block  58 , ions are implanted in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain. 
     Referring now to  FIG. 4 , another embodiment method  60  of forming an integrated circuit (e.g., the TFET  10  of  FIG. 1 ) is provided. In block  62 , a first nitride layer is formed over a gate stack supported by a substrate. In block  64 , germanium ions are implanted in the first nitride layer in a direction forming an acute angle with a top surface of the substrate. In block  66 , germanium-implanted portions of the first nitride layer are selectively removed using a fluoride/carbon/hydrogen containing plasma to form a first asymmetric nitride spacer confined to a first side of the gate stack. The first asymmetric nitride spacer protects a first source/drain region of the substrate from a first ion implantation. In block  68 , ions are implanted in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain. 
     The TFET  10  of  FIG. 1  has several advantages relative to a conventional TFET. For example, the source  14  and the drain  16  of the TFET  10  are self-aligned relative to the gate stack  24  due to the formation process. Therefore, the TFET  10  has a consistent threshold voltage. 
     An embodiment method of forming an integrated circuit includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain. 
     An embodiment method of forming an integrated circuit including forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, selectively removing germanium-implanted portions of the first nitride layer using a fluoride/carbon/hydrogen containing plasma to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain. 
     An embodiment method of forming an integrated circuit includes implanting germanium ions in a first nitride layer in a direction forming an acute angle with a top surface of a substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of a gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain, and removing the first asymmetric nitride spacer using an etching process. 
     In an embodiment, a method of forming an integrated circuit is provided. The method includes forming a first masking layer over a gate stack, a first source/drain region, and a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposing sides of the gate stack. An etch rate of a portion of the first masking layer is modified such that an etch rate of the first masking layer over the first source/drain region is different than an etch rate of the first masking layer over the second source/drain region, and the first masking layer over the first source/drain region is removed to form a first exposed source/drain region. The first exposed source/drain region is doped with first dopants. The first masking layer is removed and a second masking layer is formed over the gate stack, the first source/drain region, and the second source/drain region. An etch rate of a portion of the second masking layer is modified such that an etch rate of the second masking layer over the first source/drain region is different than an etch rate of the second masking layer over the second source/drain region. The second masking layer is removed over the second source/drain region to form a second exposed source/drain region. The second exposed source/drain region is doped with second dopants. 
     In another embodiment, a method of forming an integrated circuit is provided. The method includes forming a first masking layer over a gate feature, a first source/drain region, and a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposing sides of the gate feature. An etch rate of the first masking layer over the first source/drain region is increased such that a first etch rate of the first masking layer over the first source/drain region is different than a second etch rate of the first masking layer over the second source/drain region, and the first masking layer over the first source/drain region is removed. The first source/drain region is doped with dopants of a first conductivity type. A second masking layer is formed over the gate feature, the first source/drain region, and the second source/drain region, and an etch rate of the second masking layer over the second source/drain region is increased such that a third etch rate of the second masking layer over the second source/drain region is different than a fourth etch rate of the second masking layer over the first source/drain region. The second masking layer over the second source/drain region is removed, and the second source/drain region is doped with dopants of a second conductivity type. 
     In yet another embodiment, a method of forming an integrated circuit is provided. The method includes forming a first masking layer over a gate feature, a first source/drain region, and a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposing sides of the gate feature, and implanting ions in the first masking layer over the first source/drain region such that the first masking layer over the second source/drain region being substantially free of the ions. The first masking layer over the first source/drain region is removed such that the first masking layer remains over the second source/drain region. The first source/drain region is doped with dopants having a first conductivity type. A second masking layer is formed over the gate feature, the first source/drain region, and the second source/drain region, and ions are implanted in the second masking layer over the second source/drain region such that the second masking layer over the first source/drain region being substantially free of the ions. The second masking layer over the second source/drain region is removed such that the second masking layer remains over the first source/drain region, and the second source/drain region is doped with dopants having a second conductivity type. 
     While the disclosure provides illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.