Patent Publication Number: US-9900003-B2

Title: High voltage current switch circuit

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a National Phase filing under 35 U.S.C. § 371 of PCT/EP2013/052672 filed on Feb. 11, 2013; and this application claims priority to Application No. TV2012A000026 filed in Italy on Feb. 22, 2012; the entire contents of each application is hereby incorporated by reference. 
     The present invention relates to an electronic circuit of analog type, which can be of integrated type or realized with discrete components. 
     In particular, the present invention relates to a high voltage switch circuit for switching current signals, namely pulse type current signals, between an input port and a selectable output port. 
     In many applications, for example in the biomedical sector, multiplexers are used when it is necessary to supply a desired current signal to an output port, which can be activated selectively. 
     Italian patent application nr. MI2007A000595 describes a high voltage pulsed current generation circuit for a neuromuscular electrical stimulator. This document shows the use of a multiplexer having an input port adapted to receive a pulse type current signal, generated by a stimulation circuit, and a plurality of output ports, each of which can be selected to provide said current signal to a corresponding pair of stimulation electrodes. 
     Multiplexers, substantially of a type similar to the one described above, can also be used in biomedical applications of different type, such as in ultrasonic scanning apparatus. 
     Often, these devices do not have satisfactory galvanic isolation to ground of the output ports. 
     In many devices, even if intended for use, for example, in biomedical applications, in which the presence of effective galvanic isolation is a very important design requirement, it is possible to encounter the presence of non-negligible leakage currents to ground. The intensity of said leakage currents increases, generally not linearly, with the voltage at the terminals of the input/output port. 
     Many prior art multiplexers have high power consumption, both in stand-by mode and during operation, which increases significantly if high voltages are present at the terminals of the input/output ports. 
     Another example of electronic stimulation device is disclosed in U.S. Pat. No. 5,052,391. 
     In this document, an electronic circuit to provide high voltage, high rise-time, and charge balanced current pulses is disclosed. 
     This electronic circuit does not actually have current multiplexing functionalities but it basically provides for the splitting of one output for a parallel connection with a plurality of output channels. 
     Moreover, such a circuit shows relevant drawbacks in terms of weight and size, since multiple transformers have to be used to transfer the energy of a stimulation pulse to the corresponding output channels. The overall bulkness of such a system makes it difficult to use in portable stimulators. 
     Further, the output current supplied to each output port is often subject to relevant waveform distortions due to the currents adsorbed by the adopted switching devices. 
     The main object of the present invention is to provide a switch circuit, which is capable of overcoming the drawbacks described above. 
     A further object of the present invention is to provide a switch circuit that can be controlled by logic type signals to switch an input current towards a selectable output port. 
     A further object of the present invention is to provide a switch circuit, in which input and output terminals have high impedance to ground for voltages within the specification ranges. 
     A further object of the present invention is to provide a switch circuit having low quiescent and active power consumption for voltages within the specification ranges. 
     A further object of the present invention is to provide a switch circuit that can be supplied by high voltage power supplies. 
     A further object of the present invention is to provide a switch circuit that is easy to produce at industrial level, as an integrated circuit or as a discrete component circuit, at competitive costs with respect to prior art devices. 
     These objects, together with other objects that will be more apparent from the subsequent description and from the accompanying drawings, are achieved, according to the invention, by a high voltage switch circuit according to claim  1 , proposed hereafter, and the related dependent claims which refer to preferred embodiments of the present invention. 
    
    
     
       Further characteristics and advantages of the present invention will be more apparent with reference to the description given below and to the accompanying figures, provided purely for explanatory and non-limiting purposes, wherein: 
         FIG. 1A, 1B  illustrate block diagrams showing the general operation and structure of the high voltage switch circuit, according to the present invention; 
         FIG. 2  illustrates a block diagram of a multiplexer comprising the high voltage switch circuit, according to the present invention; 
         FIG. 3  illustrates a block diagram of the output stage included in an embodiment the high voltage switch circuit, according to the invention; 
         FIG. 4  schematically illustrates the buffer stage included in the high voltage switch circuit, according to the invention; 
         FIG. 5-6  illustrate in more details the circuit structure of the output stage of the high voltage switch circuit, in the embodiment shown in  FIG. 3 . 
     
    
    
     With reference to the aforesaid figures, the present invention relates to a high voltage switch circuit  1 . 
     The high voltage switch circuit  1  is particularly adapted for use in a muscular or neuromuscular electrical stimulator and it will now be described with reference to such an implementation for simplicity of exposition. 
     However, this is not intended to limit in any way the scope of the present invention. 
     In fact, the switch circuit  1  can be used in different biomedical applications, for example in an ultrasonic devices, or in other types of devices in which it is necessary to selectively activate a plurality of current controlled ports, such as micro-electromechanical devices or systems (MEMS). 
     Referring to  FIGS. 1A-1B , the switch circuit  1  comprises an input port IN adapted to receive an input current I IN . 
     The input current I IN  is predefined and is generated by a current generator circuit  500 , electrically connected with a pair of terminals (positive and negative) IN +  and IN −  of the input port IN. 
     The input current I IN  has a pulse type waveform, preferably of unipolar type. 
     The switch circuit  1  comprises an output port O I  that can receive the input current I IN  and conduct an output current I LI  to a corresponding electrical load L I . 
     The switch circuit  1  is capable of directing the input current I IN  to the output port O I , when this latter is selected to conduct the output current I LI  to the load L I . 
     An input voltage V IN  is present between the terminals IN +  and IN −  of the input port IN, which is a function of the input current I IN  and of the downstream equivalent impedance seen from the terminals of the input port IN. 
     The input voltage V IN  can assume high values, for example values of a few hundreds of volts in an electrical stimulator. 
     The switch circuit  1  comprises an electronic buffer stage BUF that is electrically connected to the input port IN. 
     The buffer stage BUF is adapted to sense the input voltage V IN , at the terminals IN + , IN −  of the input port IN, and to supply, at a buffer output BF, a buffered voltage V BUF , which follows the sensed input voltage V IN . 
     The switch circuit  1  comprises complementary switches T 1 , T 2  that operate as current switches and are electrically connected between the input port IN and the output port O I . 
     The switch circuit  1  comprises a first control terminal K 1  for providing a first control signal C 1  of logic type (for example at 0V and 3.3V). 
     Preferably, the switch circuit  1  is operatively associated with an electronic control stage COM adapted to generate the control signal C 1  and send it to the control terminal K 1 , connected thereto. 
     In some embodiments of the present invention, the control stage COM may be physically included in the switch circuit  1 . 
     Preferably, the control stage COM may comprise a digital processing device, for example a microprocessor, or a shift register or another circuit of similar type. 
     The switch circuit  1  comprises a first voltage level translator A 1  that is electrically connected with the buffer stage BUF, with the switches T 1 , T 2  and with the control terminal K 1 . 
     The voltage level translator A 1  is adapted to provide a first and second gate voltage V P1 , V P2  respectively at a first and second gate terminal G 1 , G 2  of the first and second switch T 1 , T 2  to control said switches through the control signal C 1 . 
     Depending on the control signal C 1 , the switches T 1 , T 2  enable or disable the flow of the input current I IN  from the input port IN to the output port O I , thus providing or blocking a current path from the input port I IN  to the output port O I  for the input current I IN . 
     The connectivity between the input port IN and each output port O 1  is determined by the control signal C 1  that selects the output port O 1  to receive the input current I IN . 
     The output current provided by the switches T 1 , T 2  is thus equal to (I IN *C 1 ) where C 1  is a logic signal having logic values equal to 0 or 1. 
     The adoption of the voltage level translator A 1  for providing the gate voltages V P1 , V P2  is quite advantageous since it allows to properly set the voltage across the gate-source junctions of the switches T 1 , T 2  in order to make it possible to control (in particular to turn on) said switches through the control signal C 1 . The switches T 1 , T 2  are in fact transistors in which the voltage across the gate-source junction may vary, since they have the source terminals electrically connected with the terminals of the input port IN. 
     As shown in  FIGS. 1B and 3 , the switches T 1 , T 2 , the voltage level translator A 1  and the input terminal K 1  form an output circuit NET 1  that is comprised in an electronic output stage M I  of the switch circuit  1 . 
     The output stage M I  is electrically connected to the input port IN, the buffer stage BUF, the output port O I  and preferably to the control stage COM. 
     According to a preferred embodiment of the present invention ( FIG. 4 ), the buffer stage BUF comprises a circuit structure divided into two sections, substantially symmetrical with respect to ground. 
     Each of the aforesaid sections comprises a sensing circuit B 1 , B 2  arranged in such a manner as to sense the voltage of a corresponding terminal IN + , IN −  of the input port IN, and a voltage follower circuit F 1 , F 2 , arranged in such a manner that the voltage of the positive and negative terminals BF + , BF −  of the buffer output BF follow the sensed voltage. 
     This solution makes it possible to maintain a high impedance to ground for the input port IN and the buffer output BF, the voltages at the terminals of which are floating with respect to ground. 
     The buffer output BF provides, between the terminals BF + , BF − , the buffered voltage V BUF  that follows the variations of the voltage V IN  at the terminals IN + , IN −  of the input port IN. 
     This makes it possible to power the voltage level translator A 1  with high voltages (V PP  and V NN ) that are different from V IN , thereby without introducing significant distortions (for example due to unwanted current absorptions) in the input current I IN , when this latter flows toward the output port O I . 
     In a first section, the buffer stage BUF preferably comprises a first sensing circuit B 1  and a first follower circuit F 1 . 
     Preferably, the sensing circuit B 1  is electrically connected with the positive terminal IN +  of the input port IN, with the sensing node S 1  and with a first power supply V CC . 
     The sensing circuit B 1  senses the voltage of the positive terminal IN +  of the input port IN and establishes an offset with respect to this voltage to compensate the threshold gate-source voltage of a transistor T 9  of the voltage follower circuit F 1  and prevent an unwanted conduction of the switch T 1 . 
     Preferably, the sensing circuit B 1  comprises a Zener diode D 21  and a capacitor Z 21 , connected in parallel between the positive terminal IN +  and the sensing node S 1 . 
     The diode D 21  advantageously prevents from over-voltages at the sensing node S 1  while the capacitor Z 21  maintains the voltage offset with respect to the voltage of the positive terminal IN + . 
     Preferably, the sensing circuit B 1  comprises a resistor R 21  and a diode D 24  electrically connected in series between the power supply V CC  and the sensing node S 1 . 
     The voltage follower circuit F 1  is electrically connected with the sensing node S 1 , with the positive terminal BF +  of the buffer output BF and with a second power supply V PP , which is a high voltage power supply. 
     In the voltage follower circuit F 1 , the voltage of the positive terminal BF +  substantially follows the voltage of the positive terminal IN + . 
     Preferably, the voltage follower circuit F 1  comprises the transistor T 9 , for example an n-type enhancement mode MOSFET, connected between the power supply V PP  and ground through the resistor R 23 . 
     The transistor T 9  has the gate terminal connected with the sensing node S 1 , the drain terminal connected with the power supply V PP  and the source terminal connected with the terminal BF +  and to a resistor R 23 , in turn connected with ground. 
     Operation of the first section of the stage BUF is now described in greater detail. 
     When there is no current flow towards the load L I  (e.g. the input current I IN  has no current pulses) the sensing node S 1  is at a voltage approximately equal to V CC . 
     The voltage of the terminal BF +  is therefore approximately equal to V IN  minus the voltage drop on the network composed of the circuit elements D 21 , Z 21 , D 24  and R 21  and the voltage V GSth (T9), i.e. the threshold gate-source voltage of the transistor T 9 . 
     The voltage of the sensing node S 1  follows the voltage of the terminal IN + , so that the voltage of the terminal BF +  follows the voltage of the terminal IN +  and the switch T 1  is in an OFF state. 
     If there is a current flowing toward the load L I  (i.e. the switch T 1  is in an ON state), the voltage of the terminal IN +  depends substantially on the voltage drop across said load. In this case, the voltage variations at the terminal IN +  are sensed by the sensing circuit B 1  and followed by the voltage at the terminal BF + . 
     A second section of the buffer stage BUF preferably has a circuit structure substantially symmetrical to that of the first section described above, which comprises a second sensing circuit B 2  and a second follower circuit F 2 . 
     Preferably, the sensing circuit B 2  is electrically connected with the negative terminal IN −  of the input port IN, with a second sensing node S 2  and with a third power supply V DD . 
     The sensing circuit B 2  senses the voltage of the negative terminal IN −  of the input port IN and establishes a voltage offset with respect thereto to compensate the threshold gate-source voltage of a transistor T 10  of the voltage follower circuit F 2  and prevent an unwanted conduction of the switch T 2 . 
     Preferably, the sensing circuit B 2  comprises a Zener diode D 22  and a capacitor Z 22 , connected in parallel between the negative terminal IN −  and the sensing node S 2 . 
     The diode D 22  advantageously prevents from over-voltages at the sensing node S 2  while the capacitor Z 22  maintains the voltage offset with respect to the voltage of the negative terminal IN − . 
     Preferably, the sensing circuit B 2  comprises a resistor R 26 , and a diode D 23  electrically connected in series between the power supply V DD  and the sensing node S 2 . 
     The follower circuit F 2  is electrically connected with the sensing node S 2  and with the negative terminal BF −  of the buffer output BF. 
     In the follower circuit F 2 , the voltage of the negative terminal BF −  substantially follows the voltage of the negative terminal IN − . 
     Preferably, the follower circuit F 2  comprises the transistor T 10 , for example a p-type enhancement mode MOSFET, connected between a fourth power supply V NN , which is a high voltage power supply, and ground through the resistor R 24 . 
     In the transistor T 10 , the gate terminal is connected with the sensing node S 2 , the drain terminal is connected with the power supply voltage V NN  and the source terminal of the transistor T 10  is electrically connected with the terminal BF −  and to a resistor R 24 , in turn connected with ground. 
     Operation of the second section of the stage BUF is substantially similar to that of the first section. 
     When there is no current flow toward the load L I  (e.g. the input current I IN  does not have current pulses), the sensing node S 2  is at a voltage approximately equal to V DD . 
     The voltage of the terminal BF −  is therefore approximately equal to V IN  minus the voltage drop on the network composed of the circuit elements D 22 , Z 22 , D 23  and R 26  and the voltage V GSth (T10), i.e. the threshold gate-source voltage of the transistor T 10 . 
     The voltage of the sensing node S 2  follows the voltage of the terminal IN − , so that the voltage of the terminal BF −  follows the voltage of the terminal IN −  and the switch T 2  is in OFF state. 
     If there is current flow toward the load L I  (i.e. the switch T 2  is in ON state), the voltage of the terminal IN −  depends substantially on the voltage drop across said load. 
     In this case, the voltage variations at the terminal IN −  are sensed by the sensing circuit B 2  and followed by the voltage at the terminal BF − . 
     The buffer stage BUF is thus capable to supply a buffered voltage V BUF  that follows the input voltage V IN  with a small power consumption and negligible distortions of the input current I IN . 
     The structure of the first output circuit NET T , in a preferred embodiment of the switch circuit  1  of the present invention ( FIGS. 3 and 5 ), is now described in greater detail. 
     As mentioned above, the output circuit NET T  comprises the switches T 1 , T 2 , the voltage level translator A 1  and the control terminal K 1 . 
     Preferably, the output circuit NET T  comprises a first output Y 1  electrically connected with the output port O I . 
     The first output Y 1  comprises a pair of terminals (positive and negative) Y 1   + , Y 1   −  electrically connected with a pair of terminals (positive and negative) O I   + , O I   −  the output port O I . 
     As shown in  FIG. 3 , the output Y 1  is electrically connected with the output port O I  in such a manner that the output current I LI , which is supplied by the output port O I  to the corresponding electrical load L I , has a waveform with the same polarity as the input current I IN . 
     In this case, the terminals Y 1   + , Y 1   −  of the output Y 1  are electrically connected with the terminals O I   + , O I   −  the output port O I  with direct polarity, i.e. with the positive terminal Y 1   +  electrically connected with the positive terminal O I   +  and the negative terminal Y 1   −  electrically connected with the negative terminal O I   +  the output port O I . 
     Of course, the output Y 1  may be electrically connected with the output port O I  in such a manner that the output current I LI  has a waveform with reversed polarity with respect to the input current I IN . 
     The switch T 1  is electrically connected between the positive terminal IN +  of the input port I IN  and the positive terminal Y 1   +  of the output Y 1  and the switch T 2  is electrically connected between the negative terminal IN −  of the input port I IN  and the negative terminal Y 1   −  of the output Y 1 . 
     The switches T 1  and T 2  are complementary and are preferably field effect transistors (J-FETs or MOSFET), respectively of p- and n-enhancement mode type. 
     Advantageously, the transistors T 1  and T 2  are arranged to have the drain terminals electrically connected with the terminals Y 1   +  and Y 1   −  and the source terminals electrically connected with the terminals IN +  and IN − , respectively. 
     In this way, when the transistors T 1  and T 2  are in conduction state (switches T 1  and T 2  in ON state), the input current I IN  can flow from the terminals of the input port IN to the terminals of the output Y 1 . 
     Instead, when the two transistors T 1  and T 2  are in cut-off state (switches T 1  and T 2  in OFF state), the passing of the input current I IN  toward the output Y 1  is prevented. 
     As mentioned above, the voltage level translator A 1  is advantageously adapted to control the switches T 1  and T 2  through the control signal C 1 . 
     The voltage level translator A 1  is electrically connected between the terminals (positive and negative) BF + , BF −  of the buffer output BF and with the gate terminals G 1 , G 2  of the switches T 1  and T 2 . 
     The voltage level translator A 1  comprises a first polarization circuit including the circuit series of the resistor R 1 , the third transistor T 3 , the resistor R 2 , the fourth transistor T 4  and the resistor R 3 . 
     The transistors T 3 , T 4  are preferably bipolar junction transistors (BJT), respectively of npn and pnp type, and are adapted to enable/prevent flow of a first polarization current I P1  along said first polarization circuit. 
     The transistors T 3 , T 4  are arranged in such a manner to be controlled by the terminal K 1 , according to the state of the control signal C 1 . 
     Preferably, the transistor T 3  has its collector terminal electrically connected with the resistor R 1 , which is in turn connected in series with the positive terminal BF +  of the buffer output BF, and is connected with the control terminal K 1 , at the base terminal thereof. 
     Instead, the transistor T 4  has the base terminal connected to ground and the collector terminal electrically connected with the resistor R 3 , which is in turn connected in series with the negative terminal BF −  of the buffer output BF. 
     The transistors T 3  and T 4  have their emitter terminals connected with the terminals of the resistor R 2 . 
     As an alternative, the transistors T 3 , T 4  may have their base terminals connected to the ground and to the terminal K 1 , respectively. 
     Preferably, the voltage level translator A 1  comprises a first circuit network to protect the switches T 1  and T 2  (in particular their gate terminals G 1 , G 2 ) against over-voltages. 
     This protective network advantageously comprises first and second over-voltage protection elements D 1  and D 2  (preferably Zener diodes) that are respectively connected between the gate terminals G 1 , G 2  of the transistors T 1  and T 2  and the terminals IN +  and IN −  of the input port IN. 
     Preferably, the voltage level translator A 1  also comprises some stabilizing circuit elements, such as the resistor R 5  and the capacitor Z 1 , connected in parallel with the resistor R 2 , and the protection resistor R 4  and R 6 , connected in series with the base terminals of the transistor T 3  and T 4 , respectively. 
     Operation of the output circuit NET 1  is now described in greater detail. 
     Let us assume that the output circuit NET 1  is initially in a deactivated or stand-by state and the terminal K 1  receives a control signal C 1  at “low” logic level. 
     The transistors T 3  and T 4  are in the cut-off state and there is no flow of the polarization current I P1 . 
     If the input current I IN  does not have any current pulses, the voltage at the terminal BF +  is approximately V CC −V GS (T 9 ) while the voltage at the terminal BF −  is approximately V DD −V GS (T 10 ), where V GS (T 9 ) and V GS (T 10 ) are the gate-source voltages of the transistors T 9  and T 10 , respectively. 
     If the input current I IN  has a current pulse, the voltage at the terminals BF +  and BF −  increases up to V PP  and V NN  respectively. 
     In both cases, as there is no flow of the polarization current I P1 , the voltage level translator A 1  provides gate voltages V P1 , V P2  to the gate terminals G 1 , G 2 , such as to maintain the switches T 1  and T 2  in the cut-off state. 
     From the above, it is evident how, with a control signal C 1  at a “low” logic level, whatever the voltage V IN  and the input current I IN  (within the specification range of the circuit), the switches T 1  and T 2  remain in the OFF state and the input current I IN  cannot flow toward the output Y 1 . 
     The output circuit NET 1  is therefore maintained in deactivated or stand-by state. 
     When the terminal K 1  receives a control signal C 1  at “high” logic level, the transistors T 3  and T 4  are taken to conduction state and the polarization current I P1  can flow. 
     In this situation, before the switching of the transistors T 3 , T 4  is completed, the voltage at the terminals BF +  and BF −  initially tends to increase up to V PP  and V NN  respectively. 
     Due to the voltage drop across the resistors R 1  and R 3 , which is determined by flow of the current I P1 , the voltage level translator A 1  provides gate voltages V P1 , V P2  to the gate terminals G 1 , G 2 , such as to take the switches T 1  and T 2  to the conduction state (ON state). 
     The switches T 1  and T 2  are taken to the ON state and the input current I IN  is free to flow toward the output Y 1 . 
     At this point, the voltage at the terminals BF +  and BF −  depends substantially on the voltage across the load L I  but the voltage drop across the resistors R 1  and R 3 , due to flow of the current I P1 , ensures that the gate terminals G 1 , G 2  are always at voltages such as to maintain the switches T 1  and T 2  in conduction state. 
     Therefore, with a control signal C 1  at a high logic level, whatever the voltage V IN  and the input current I IN  (within the specification range of the circuit), the switches T 1  and T 2  are always in ON state and the input current I IN  can flow toward the output Y 1 . 
     From the above, it is apparent that the voltage level translator A 1  provides a voltage level shifting of the control signal C 1  to safely control the switches T 1 , T 2 , despite of the variations of the input voltage V IN , since these latter are constantly followed by the buffered voltage V BUF . 
     Given that the terminals of the output Y 1  are preferably connected with direct polarity to the terminals of the output port O I , the output current I IL  supplied to the electrical load L I , has a waveform with the same polarity as the input current I IN . 
     In other words, the condition IL I =I IN  is obtained. 
     In this way, when the output circuit NET 1  is enabled by the control signal C 1  to transmit an input current I IN  of pulse type toward the output port O I , the output current I IL  has pulses with the same polarity and amplitude as the pulses of the input current I IN . 
     When the terminal K 1  again receives a control signal C 1  at “low” logic level, the transistors T 3  and T 4  return to the cutoff state and ideally there should be no flow of the polarization current I P1 . 
     In this situation, in fact, the voltage level translator A 1  supplies, respectively to the gate terminals G 1 , G 2  voltages V P1 , V P2  such as to take the transistors T 1  and T 2  to cut-off state (OFF state). 
     Regardless of this, due to the presence of stray capacitances between the gate terminals G 1 , G 2  and the terminal IN +  of the input port IN, the transistors T 1 , T 2  do not switch immediately but are taken to OFF state only when the input current I IN  reaches zero, i.e. at the end of the input current pulse. 
     Based on the above, it can be observed that:
         activation of the output circuit NET 1  is determined simply by the transition of the control signal C 1  from a “low” logic level to a “high” logic level;   deactivation of the output circuit NET 1  is instead determined by transition of the control signal C 1  to “low” logic level and by passage of the input current I IN  through zero.       

     It is therefore evident how the output circuit NET 1  behaves, from a functional viewpoint, in a manner substantially similar to that of a DIAC electronic device. 
     In an embodiment of the present invention, particularly suitable for use in a muscular or neuromuscular electrical stimulator, the switch circuit  1  comprises the fifth and sixth complementary switches T 5 , T 6  that operate as current switches and that are electrically connected between the input port IN and the output port O I , in parallel with the switches T 1 , T 2 . 
     The switch circuit  1  comprises a second control terminal K 2  for providing a second control signal C 2  of logic type. 
     Preferably, the second control signal C 2  is received from the control stage COM. 
     The switch circuit  1  comprises a second voltage level translator A 3  that is electrically connected with the buffer stage BUF, with the switches T 5 , T 6  and with the control terminal K 2 . 
     The voltage level translator A 2  is adapted to provide a third and fourth gate voltage V P3 , V P4  respectively at a third and fourth gate terminal G 3 , G 4  of the switches T 5 , T 6  in order to control these latter through the control signal C 2 . 
     Depending on the control signal C 2 , the switches T 5 , T 6  can enable or disable the flow of the input current I IN  from the input port IN to the output port O I , thereby providing or blocking a current path from the input port I IN  towards the output port O I  for the input current I IN . 
     The connectivity between the input port IN and each output port O I  is determined by the control signal C 2  and the output current provided by the switches T 5 , T 6  is thus equal to (I IN *C 2 ), where C 2  is a logic signal having logic values equal to 0 or 1. 
     The adoption of the voltage level translator A 3  for providing the gate voltages V P3 , V P4  is quite advantageous since it allows to properly set the voltage across the gate-source junction of the switches T 5 , T 6  in order to make it possible to control (in particular to turn on) them through the control signal C 2 . 
     As shown in  FIGS. 3 and 6 , the switches T 5 , T 6 , the voltage level translator A 3  and the control terminal K 2  form an output circuit NET 2 , which is comprised in an output stage M I  of the switch circuit  1  and which is connected between the input port IN and the output port O I , as the output circuit NET 1 . 
     Referring to  FIG. 6 , the output circuit NET 2  has a circuit structure similar to that of the circuit NET 1 , described above. 
     The output circuit NET 2  comprises a second output Y 2  electrically connected with the output port O I . 
     The second output Y 2  comprises a pair of terminals (positive and negative) Y 2   + , Y 2   −  electrically connected with the terminals O I   + , O I   −  the output port O I . 
     Preferably, the output circuit NET 2  is electrically connected with the output port O I  in such a manner that the output current I LI , which is supplied by the output port O I  to the corresponding electrical load L I , has a waveform with reverse polarity with respect to that of the input current I IN . 
     In this case, the terminals Y 2   + , Y 2   −  of the output Y 2  are electrically connected with the terminals O I   + , O I   −  the output port O I  with reverse polarity, i.e. with the positive terminal Y 2   +  electrically connected with the negative terminal O I   −  and the negative terminal Y 2   −  electrically connected with the positive terminal O I   +  of the output port O I . 
     Of course, the output circuit NET 2  may be electrically connected with the output port O I  in such a manner that the output current I LI  has a waveform with direct polarity with respect to the input current I IN . 
     The switch T 5  is electrically connected between the positive terminal IN +  of the input port I IN  and the positive terminal Y 2   +  of the output Y 2  and the switch T 6  is electrically connected between the negative terminal IN −  of the input port I IN  and the negative terminal Y 2   −  of the output Y 2 . 
     The switches T 5  and T 6  are complementary and preferably field effect transistors (FET or MOSFET), respectively of p- and n-port enhancement mode type. 
     Advantageously, the switches T 5  and T 6  are arranged in such a manner as to have the drain terminals electrically connected with the terminals Y 2   +  and Y 2   −  and the source terminals electrically connected with the terminals IN +  and IN − , respectively. 
     In this way, when the transistors T 5  and T 6  are in conduction state (switches T 5  and T 6  in ON state), the input current I IN  can flow from the terminals of the input port IN to the terminals of the output Y 2 . 
     Instead, when the transistors T 5  and T 6  are in the cut-off state (switches T 5  and T 6  in OFF state), the passage of the input current I IN  toward the output Y 2  is prevented. 
     Preferably, the voltage level translator A 3 , adapted to control the transistors T 5  and T 6 , is electrically connected between the terminals (positive and negative) BF +  and BF −  of the buffer output BF and with the gate terminals G 3 , G 4  of the switches T 5  and T 6 . 
     The voltage level translator A 3  advantageously comprises a second polarization circuit formed by the circuit series consisting of the resistor R 11 , the seventh transistor T 7 , the resistor R 12 , the eighth transistor T 8  and the resistor R 13 . 
     The transistors T 7  and T 8  are preferably bipolar junction transistors (BJT), respectively of npn and pnp type, and are adapted to enable/prevent flow of a second polarization current I P2  along said second polarization circuit. 
     Preferably, the transistor T 7  has its collector terminal electrically connected with the resistor R 11 , in turn connected in series with the positive terminal BF +  of the buffer output BF, and is connected with the terminal K 2 , at the base terminal thereof. 
     The transistor T 8  has the base terminal connected with ground and the collector terminal electrically connected with the resistor R 13 , in turn connected in series with the negative terminal BF −  of the buffer output BF. 
     The transistors T 7  and T 8  have their emitter terminals connected to the terminals of the resistor R 12 . 
     As an alternative, the transistors T 7 , T 8  may have their base terminals connected to the ground and to the terminal K 2 , respectively. 
     Preferably, the voltage level translator A 3  comprises a second circuit network to protect the gate terminals of the transistors T 5  and T 6  against over-voltages. 
     This protective network advantageously comprises third and fourth over-voltage protection elements D 10  and D 11  (preferably Zener diodes) that are respectively connected between the gate terminals G 3 , G 4  of the transistors T 5  and T 6  and the terminals IN +  and IN −  of the input port IN. 
     Preferably, the voltage level translator A 3  also comprises some stabilizing circuit elements, such as the resistor R 15  and the capacitor Z 10 , connected in parallel with the resistor R 12 , and the protection resistor R 14  and R 16  connected in series with the base terminals of the transistors T 7  and T 8 , respectively. 
     Operation of the output circuit NET 2  is similar to that of the output circuit NET 1 . 
     Let us assume that the output circuit NET 2  is initially in a deactivated state and the terminal K 2  receives a logic control signal C 2  at “low” level. The transistors T 7  and T 8  are in the cut-off state and there is no flow of the polarization current I P2 . 
     In this situation, in the presence or absence of pulses of the input current I IN , the gate terminals of the switches T 5  and T 6  are always at gate voltages V P3 , V P4  such as to maintain them in a cut-off state. 
     Therefore, with a control signal C 2 , at a low logic level, the switches T 5  and T 6  remain in the OFF state and the input current I IN  cannot in any case flow toward the output Y 2 . 
     The output circuit NET 2  is therefore maintained in a deactivated or stand-by state. 
     When the terminal K 2  receives a logic control signal C 2  at “high” level, the transistors T 7  and T 8  switch to conduction state and the polarization current I P2  can flow. 
     In this situation, due to the voltage drop across the resistors R 11  and R 13 , determined by the flow of the current I P2 , the gate terminals G 3 , G 4  of the transistors T 5  and T 6  are polarized at gate voltages V P3 , V P4  such as to take the transistors T 5  and T 6  to conduction state. 
     The switches T 5  and T 6  are then taken to the ON state and the input current I IN  is free to flow toward the output Y 2 . 
     At this point, the voltage at the terminals BF +  and BF −  depends substantially on the voltage across the load L I  but the voltage drop across the resistors R 11  and R 13 , due to circulation of the current I P2 , ensures that the gate terminals G 3 , G 4  are always at gate voltages V P3 , V P4  such as to maintain the transistors T 5  and T 6  in conduction state. 
     Therefore, with a control signal C 2  at high logic level, whatever the voltage V IN  and the input current I IN  (within the specification range of the circuit), the switches T 5  and T 6  are always in the ON state and the input current I IN  can in any case flow toward the output Y 2 . 
     From the above, it is apparent that the voltage level translator A 3  provides a voltage level shifting of the control signal C 3  to safely control the switches T 5 , T 6 , despite of the variations of the input voltage V IN , since these latter are constantly followed by the buffered voltage V BUF . 
     Given that the terminals of the output Y 2  are preferably connected with reverse polarity to the terminals of the output port O I , the output current I IL  supplied to the electrical load L I , will have a waveform with reverse polarity with respect to the input current I IN . 
     In other words, the condition IL I =−I IN  is obtained. 
     In this way, when the output circuit NET 2  is enabled by the control signal C 2  to transmit a pulse type input current I IN  toward the output port O I , the output current I IL  has pulses with the same amplitude but with reverse polarity with respect to the pulses of the input current I IN . 
     When the terminal K 2  once again receives a control signal C 2  at “low” logic level, the transistors T 7  and T 8  are again taken to the cutoff state and ideally there should be no flow of the polarization current I P2 . 
     In this situation, the voltage level translator A 3  supplies, respectively to the gate terminals of the transistors T 5  and T 6 , gate voltages V P3 , V P4  such as to take the same transistors T 5  and T 6  to the cut-off state. 
     Regardless of this, due to the presence of stray capacitances between the gate terminals of the transistors T 5 , T 6  and the terminal IN −  of the input port, the transistors T 5 , T 6  do not switch immediately but are taken to the cut-off state only when the input current I IN  reaches zero, i.e. at the end of the input current pulse. 
     On the basis of the above, it can be observed that:
         activation of the output circuit NET 2  is determined simply by transition of the control signal C 2  from a “low” logic level to a “high” logic level;   deactivation of the output circuit NET 2  is determined by transition of the control signal C 2  at “low” logic level and by passage of the input current I IN  through zero.       

     Therefore, also the output circuit NET 2  behaves, from a functional viewpoint, in a manner substantially similar to that of a DIAC electronic device. 
     Referring to  FIG. 2 , the high voltage switch circuit  1 , which does not have multiplexing functionalities per se, is particularly suitable for implementation in a multiplexer  100 . 
     The multiplexer  100  comprises a common input port IN and a plurality of output ports O I , each of which can be selected by logic control signals. 
     The multiplexer  100  receives an input current I IN  at the input port IN and it directs it towards the selected output ports O I . 
     The multiplexer  100  thus implements a multiplexing function of the type 1→N, with N&gt;1, for the current signals received at the input port IN. 
     The adoption of the high voltage switch circuit  1  in a multiplexer  100  is particularly advantageous for use in an electrical stimulator. 
     In this case, each of the mentioned output ports can be electrically connected with a pair of stimulation electrodes and the output current, supplied by each output port, is the current effectively injected by the electrodes during stimulation, while the electrical load connected to each output port typically consists of the impedance offered by the stimulation electrodes and by the portion of the patient&#39;s body affected by the stimulation current. 
     The multiplexer  100  comprises a common buffer stage BUF (as described above), which senses the voltage V IN  between the terminals of the input port IN and provides, at the buffer output BF, a buffered voltage V BUF  that substantially follows the input voltage V IN . 
     The multiplexer  100  comprises a plurality of output stages M I , each of which is electrically connected with the input port IN, the common buffer stage BUF and a corresponding output port O I . 
     Each of the output stages M I  comprises the output circuit NET 1  and preferably also the output circuit NET 2 , as described above. 
     Preferably, the control terminals K 1  (and possibly K 2 ) of each output stage M I  are electrically connected with a common control stage COM that may be physically included in the multiplexer  1 . 
     It is apparent that the common buffer stage BUF and each of the output stages M I  form a switch circuit  1 , according to the invention, which is electrically connected between the input port IN and the corresponding output port O I  ( FIG. 2 ). 
     The operation of the multiplexer  100  is now briefly described. 
     Normally, the output stages M I  are maintained in a deactivated state. 
     Therefore, the control signals sent by the control stage COM are normally maintained at a “low” logic level. 
     To direct the input current I IN  toward any desired output port O I , the control stage COM must activate the output circuit NET 1  (or optionally the output circuit NET 2 ) of the output stage M I , which is operatively associated with the chosen output port O I . 
     The control signal C 1  (or possibly C 2 ) sent to the output circuit NET 1  (or possibly NET 2 ) of the output stage M I , is therefore taken to “high” logic level, enabling the input current I IN  to flow toward the output port O I . 
     If the output Y 1  (or possibly Y 2 ) of the output circuit NET 1  (or NET 2 ) is connected with direct polarity to the output port O I , the output current I IL  has the same waveform as the input current I IN . 
     If the output Y 1  (or possibly Y 2 ) of the output circuit NET 1  (or NET 2 ) is connected with reverse polarity to the output port O I , the output current I IL  has a waveform with pulses of opposite polarity with respect to the input current I IN . 
     It can be noted how by suitably managing the output circuit NET 1  (or NET), one or more pulses of the input current I IN  can be “neutralized”, simply by maintaining the control signals C 1  (or C 2 ) in the “low” logic state. The pulses of the input current I IN  thus “neutralized”, do not appear, with direct or reverse polarity, in the output current I IL . 
     In this case, the output current I IL  has a different time distribution of the pulses, with respect to the input current I IN . 
     Operation of the output stage M I , as adjusted by the control signals C 1 , C 2 , can be summarized in the following exemplificative table: 
     
       
         
           
               
               
               
               
               
             
               
                   
                   
               
               
                   
                 C 1   
                 C 2   
                 M I   
                 I LI   
               
               
                   
                   
               
             
            
               
                   
                 0 
                 0 
                 OFF 
                 0 
               
               
                   
                 0 
                 1 
                 Circuit NET 2  ON (reversing) 
                 −I IN   
               
               
                   
                 1 
                 0 
                 Circuit NET 1  ON (not reversing) 
                 I IN   
               
               
                   
                 1 
                 1 
                 Short circuit 
                 0 
               
               
                   
                   
                   
                   
                 (V IN=0 ) 
               
               
                   
                   
               
            
           
         
       
     
     From the table above it is evident how the output current from each output stage M I  is equal to (I IN *C 1 ) or (I IN *C 2 ), where C 1 , C 2  are logic signals that assume the logic values 0 or 1. 
     The multiplexer  1  is therefore not only capable of reversing the polarity of the pulses of the input current I IN  (for example, by alternately activating the switching circuits NET 1  and NET 25  where both are present) but also of modifying the waveform of this latter. 
     The use of the switching circuits NET 1  and (optionally) NET 2  in each output stage M I , with the functionalities described above, is particularly useful in the case in which the multiplexer is used in a muscular or neuromuscular electrical stimulator. 
     For different biomedical applications or for other scopes of use of the multiplexer  1 , the output stages M I  may however have different structure and functionality and comprise only the output circuit NET 1 . 
     It has been seen in practice how the high voltage switch circuit  1 , according to the present invention, allows the set objects to be achieved. 
     With respect to prior art devices, the switch circuit  1  has improved functionalities, in terms of reduction of dissipated power and high impedance of inputs/outputs. 
     The switch circuit  1  ensures effective high impedance of inputs and outputs. It is arranged in such a manner that the voltages present between the terminals of the input port IN, of any output port O I  and of the buffer output BF are virtually floating with respect to ground. 
     An advantage of the switch circuit  1  is the absence of working point bias currents for the active elements (transistors). This substantially reduces the power consumption to what is caused by leakage currents in the transistors. 
     Additional power consumption in active state is caused by charging/discharging of the parasitic capacitances trough the polarization currents I P1 , I P2 . This can be minimized through reducing the time periods during which the control signals C 1 , C 2  are at a logic level commanding the ON state for the switches T 1 , T 2 , T 5 , T 6 . This is basically a design factor that depends on the parasitic capacitances, mainly in said switches. 
     The switch circuit  1  is particularly suitable for operating in the presence of high voltages to the terminals of the input port IN or of the output port. 
     For this purpose, it is sufficient to select in the most appropriate manner the type of transistor of each output stage. 
     The switch circuit  1  is characterized by considerable flexibility of use. 
     It is particularly suitable for use in biomedical applications, such as in a muscular or neuromuscular electrical stimulator. 
     In this application, the use of the output circuits NET 1  and NET 2  for the output stage M I , according to the description above, enables simple and effective adjustment of the polarity and time distribution of the output current I LI , at each output port O I . 
     However, the switch circuit  1  can be easily integrated in other biomedical applications, for example in ultrasonic devices or micro-electromechanical devices or systems (MEMS). 
     The switch circuit  1  has a simple structure and is easy and inexpensive to produce at industrial level, with manufacturing techniques using discrete or integrated components.