Patent Publication Number: US-7715222-B2

Title: Configurable SRAM system and method

Description:
RELATED APPLICATION DATA 
   This application is a continuation of U.S. patent application Ser. No. 11/463,917, filed Aug. 11, 2006 now U.S. Pat. No. 7,450,413, entitled “Configurable SRAM System and Method,” which is incorporated herein by reference in its entirety. 
   This application is related to commonly-owned and co-pending U.S. patent application Ser. No. 11/947,092, filed Nov. 29, 2007, entitled “Design Structure for a Configurable SRAM System and Method.” 

   FIELD OF THE INVENTION 
   The present invention generally relates to the field of static random access memory (SRAM) cells. In particular, the present invention is directed to a configurable SRAM system and method. 
   BACKGROUND 
   Static random access memory (SRAM) cells are susceptible to process and environmental variation. Such variation has become a greater concern as cell dimensions have become smaller. One example variation includes asymmetry in the cell, which may impact the ability to properly write or read an SRAM cell. Device asymmetry can be an even larger problem as the voltages provided to a cell are lowered. 
   SUMMARY OF THE DISCLOSURE 
   In one embodiment, a method of switching performance modes of a static random access memory (SRAM) circuit. The method includes sharing a first memory node of a first SRAM cell with a second memory node of a second SRAM cell during a first mode of operation of the SRAM circuit; sharing a third memory node of the first SRAM cell with a fourth memory node of the second SRAM cell during the first mode of operation; isolating the first memory node from the second memory node during a second mode of operation of the SRAM circuit; isolating the third memory node from the fourth memory node during the second mode of operation; and caching data stored in the memory nodes prior to switching from the first mode of operation to the second mode of operation and/or from the second mode of operation to the first mode of operation. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein: 
       FIG. 1  shows one embodiment of an SRAM system; 
       FIG. 2  shows one example of a grid arrangement of SRAM cells; 
       FIG. 3  shows one example of an SRAM cell; 
       FIG. 4  shows one example of a cell control module; and 
       FIG. 5  shows another embodiment of an SRAM system. 
   

   DETAILED DESCRIPTION 
     FIG. 1  illustrates one embodiment of an SRAM system  100 . SRAM system  100  includes an SRAM cell  105  and an SRAM cell  110 . SRAM cell  105  includes a first memory node  115  (i.e., a memory storage node) and a second memory node  120 . SRAM cell  110  includes a first memory node  125  and a second memory node  130 . 
   SRAM system  100  may be included in a memory array of a number of SRAM cells arranged in one of many well known arrangements. In one example, SRAM cells (e.g., SRAM cells  105 ,  110 ) may be arranged in a grid pattern having columns and rows. Examples of such a grid pattern are well known to those of ordinary skill.  FIG. 2  illustrates one example of a grid pattern arrangement  200  of SRAM cells. Grid pattern arrangement  200  includes columns  205  and rows  210 . Each column  205  includes a plurality of SRAM cells  215  connected with each other by bitlines  220 . Each row  210  includes at least one wordline  225  connected with at least a portion of each of the plurality of SRAM cells  215  in the corresponding row. In one example, to read and/or write data to/from SRAM cells in a given row, a wordline  225  corresponding to a particular row will be utilized to allow electrical communication between memory cells of each SRAM cell  215  in the row with corresponding bitlines  220 . Various activation sequences for wordlines, such as wordlines  225 , are known to those of ordinary skill. A data collection unit  240  (e.g., a multiplexer) may be utilized to process information to and/or from bitlines  220 . Typically, only one prior art SRAM cell from each column could be read and/or written to at a time utilizing the same bitlines. It should also be noted that although grid pattern arrangement  200  depicts four columns and six rows, one of ordinary skill will recognize that many configurations of rows and/or columns may be utilized in a grid pattern arrangement of SRAM cells. 
   Each of SRAM cells  105 ,  110  of  FIG. 1  may include any well known SRAM cell. One example of an SRAM cell is a cross-coupled six transistor SRAM cell.  FIG. 3  illustrates another example of an SRAM cell  300 . SRAM cell  300  includes a memory node  305  and a memory node  310  separated by a feedback loop  315  (e.g., a cross-coupled inverter pair). Feedback loop  315  may include any number and/or combination of circuit elements as is known to those of ordinary skill. In one example, feedback loop  315  may include inverters  320  and  325  in parallel. 
   Memory node  305  is separated from a bitline  330  by an access transistor  335 . Memory node  310  is separated from a bitline  340  by an access transistor  345 . In one example, an access transistor (e.g., access transistor  335 , access transistor  345 ) may include any number and/or combination of transistors. An example access transistor may include, but is not limited to, a p-type field effect transistor (FET), a n-type FET, a pass gate arrangement of two or more FET&#39;s, and any combinations thereof. 
   A wordline  350  is connected to access transistors  335 ,  345 . In one example, a signal (e.g., a voltage drop, a voltage increase) on wordline  350  may operate to allow current to flow across access transistors  335 ,  345  to bring memory node  305  into electrical communication with bitline  330  and memory node  310  into electrical communication with bitline  340 . In another example, wordline  350  may be activated during a read and/or write operation of SRAM cell  300 . 
   Referring again to  FIG. 1 , SRAM cells  105  and  110  are illustrated in a column. SRAM cells  105  and  110  are in electrical communication with a bitline  160  and a bitline  165 . In one example, bitlines  160  and  165  may be utilized to read and/or write information to and/or from a memory node (e.g., memory nodes  115 ,  120 ,  125 ,  130 ) of one or more of SRAM cells  105 ,  115 . In another example, bitline  160  may be a “true” bitline and bitline  165  may be a “compliment” bitline. 
   First memory node  115  and first memory node  125  are connected with a cell control module  135 . Second memory node  120  and second memory node  130  are connected with cell control module  140 . In one example, a cell control module, such as cell control modules  135 ,  140 , includes one or more circuit elements that are configured to switch between a logically inactive state and a logically active state upon receiving appropriate instruction (e.g., an activation signal, a deactivation signal) via a cell control switch mechanism. A cell control switch mechanism may include any mechanism (e.g., a signal from a controller or other processor) for switching a cell control module from one state to another, such as from a logically inactive state to a logically active state. In one example, cell control modules  135 ,  140  switch substantially simultaneously from one state to another. In another example, cell control modules  135 ,  140  are in electrical communication (e.g., the gates of cell control modules  135 ,  140  are connected to) a single cell control switch mechanism that switches cell control modules  135 ,  140  from a logically inactive state to a logically active state and/or from a logically active state to a logically inactive state. In yet another example, cell control modules  135 ,  140  each may be in electrical communication with a separate cell control switch mechanism where each of the separate cell control switch mechanisms work in concert to switch cell control modules  135 ,  140  between states. 
     FIG. 4  illustrates one example of a cell control module  400 . Cell control module  400  includes an access transistor  405 . In one example, access transistor  405  may include any number and/or combination of transistors. An example access transistor may include, but is not limited to, a p-type field effect transistor (FET), a n-type FET, a pass gate arrangement of two or more FET&#39;s, and any combinations thereof. In one example, a first node  410  of access transistor  405  (e.g., a source, a drain) is connected to a memory node of a first SRAM cell (e.g., memory node  115  of  FIG. 1 ) and a second node  415  of access transistor  405  (e.g., a source, a drain) is connected to a memory node of a second SRAM cell (e.g., memory node  125  of  FIG. 1 ). A gate  420  of access transistor  405  is connected to a cell control switch mechanism  425 . In one example, access transistor  405  includes an n-type FET with a gate  420  connected to cell control switch mechanism  425 , which drives a voltage at gate  420  high in order to switch access transistor  405  to a logically active state. In another example, access transistor  405  includes a p-type FET with a gate  420  connected to cell control switch mechanism  425 , which drives a voltage at gate  420  low in order to switch access transistor  405  to a logically active state. In yet another example, access transistor  405  includes a p-type FET and an n-type FET in parallel, each having a gate  420  connected to cell control switch mechanism  425 . Cell control switch mechanism  425  drives a voltage at gate  420  of the n-type FET high to switch the n-type FET to a logically active state and drives a voltage at gate  420  of the p-type FET low to switch the p-type FET to a logically active state. Such an example takes advantage of an n-type FET&#39;s ability to share a logical “1” between memory nodes (e.g., memory nodes  115  and  125 , memory nodes  120  and  130 ) well, and a p-type FET&#39;s ability to share a logical “0” between memory nodes well. 
   Referring again to  FIG. 1 , cell control modules  135 ,  140 , when in a logically inactive state, separate the memory nodes of SRAM cell  105  and SRAM cell  110 . SRAM cell  105  and SRAM cell  110  act independently in the logically inactive state. In a logically active state, a cell control module (e.g., cell control modules  135 ,  140 ) allows current to pass across the cell control module. When cell control module  135  is in a logically active state, memory node  115  and memory node  125  are shared. When cell control module  140  is in a logically active state, memory node  120  and memory node  130  are shared. 
   Various mechanisms for controlling an activation/deactivation signal to a cell control module (e.g., cell control modules  135 ,  140 ) will be clear to those of ordinary skill. An example mechanism includes, but is not limited to, detection of system lowering voltage. The timing of switching a cell control module from a logically active to a logically inactive mode and/or from a logically inactive to a logically active mode will vary depending on device and/or application, as will the mechanism utilized to control the switching. Example mechanisms include, but are not limited to, a static logic circuit, a dynamic logic circuit, and any combinations thereof. In one example, cell control module  135  and cell control module  140  are switched to and/or from a logically active state substantially simultaneously. In another example, cell control modules  135 ,  140  may be switched to and/or from a logically active state at different times. 
   SRAM system  100  shows two SRAM cells ( 105 ,  110 ) being connected with cell control modules  135 ,  140 . In another embodiment, three or more SRAM cells may be connected with one or more cell control modules. SRAM cells  105 ,  110  are shown in  FIG. 1  as parallel to each other in a single column. In yet another embodiment, two or more SRAM cells (e.g., SRAM cells  105 ,  110 ) may be in separate columns. 
     FIG. 5  illustrates another embodiment of a SRAM system  500 . SRAM system  500  includes an SRAM cell  502  and an SRAM cell  504 . SRAM cell  502  includes memory nodes  506 ,  508  separated by a feedback loop  510 . Feedback loop  510  includes inverters  512 ,  514 . SRAM cell  504  includes memory nodes  516 ,  518  separated by a feedback loop  520 . Feedback loop  520  includes inverters  522 ,  524 . SRAM system  500  also includes a cell control module  526  connected between memory nodes  506  and  516  and a cell control module  528  connected between memory nodes  508  and  518 . Each of cell control modules  526 ,  528  may include any number and any combination of transistors or other circuit elements that allow the cell control modules to be in a logically active state and a logically inactive state. In one example, cell control modules  526 ,  528  may be in a logically active state and allow sharing of logical values stored in the memory nodes (e.g., memory nodes  506 / 516  and  508 / 518 ). In such an example, SRAM cell  502  and SRAM cell  504  may combine to form one effective SRAM cell. In another example, cell control modules  526 ,  528  may be in a logically inactive state acting as isolation devices and not allow sharing of logical values stored in the memory nodes (e.g., memory nodes  506 / 516  and  508 / 518 ). In such an example, SRAM cell  502  and SRAM cell  504  act separately. The active and inactive states of cell control modules  526 ,  528  may be controlled by a cell control switch mechanism (not shown) connected via gates  530 ,  532  of cell control modules  526 ,  528 . 
   SRAM cells  502  and  504  may be read from and/or written to simultaneously or separately depending on the active/inactive state of cell control modules  526 ,  528 . SRAM cell  502  includes an access transistor  540  between memory node  506  and a bitline  542 . Access transistor  540  is controlled by a wordline  544  connected to a gate of access transistor  540 . SRAM cell  502  also includes an access transistor  546  between memory node  508  and a bitline  548 . Access transistor  546  is also controlled by wordline  544  connected to a gate of access transistor  546 . SRAM cell  504  includes an access transistor  550  between memory node  516  and bitline  542 . Access transistor  550  is controlled by a wordline  554  connected to a gate of access transistor  550 . SRAM cell  504  also includes an access transistor  556  between memory node  518  and bitline  548 . Access transistor  556  is also controlled by wordline  554  connected to a gate of access transistor  556 . 
   Each of access transistors  540 ,  546 ,  550 ,  556  may include any one or more transistors including, but is not limited to, a p-type field effect transistor (FET), a n-type FET, a pass gate arrangement of two or more FET&#39;s, and any combinations thereof. 
   A configurable SRAM system of the present disclosure (e.g., SRAM system  100 ,  500 ) may be included in a variety of devices. Example devices that may include a configurable SRAM system include, but are not limited to, a stand-alone SRAM (e.g., a 512 megabyte chip), a microprocessor, a microcontroller, any other integrated circuit capable of handling an embedded SRAM element and/or array, and any combinations thereof. In one example, SRAM system  100 ,  500  may be included in a grid arrangement similar to that of  FIG. 2 . In another example, SRAM system  100 ,  500  may be included in an array of SRAM systems  100 ,  500 . 
   In one embodiment, a configurable SRAM system (e.g., SRAM system  100 ,  500 ) may be operated in one of two different operating modes: a shared mode (i.e., a process tolerant mode) and an independent mode (i.e., a high performance mode). In a shared mode, two or more SRAM cells are shared by switching corresponding cell control modules to a logically active state. In an independent mode, two or more SRAM cells are allowed to operate independently by switching corresponding cell control modules to a logically inactive state. In one example, a process tolerant mode that allows sharing of two or more SRAM cells may be instigated by low voltage operation of a device including an SRAM system according to the present disclosure. Upon return to a high voltage operation of the device, the SRAM system may switch to a high performance mode in which the cell control modules switch to a logically inactive state and allow the SRAM cells to operate independently. In one example, a memory device may have a maximum operating voltage and one or more lesser voltages at which it may operate (e.g., to save power) in different modes. The actual values of these voltages vary depending on device and application. In one example, a memory device having a maximum operating voltage of 1.2 volts (V) may also have a lower operating voltage of 0.8 V that is utilized in a power-saving mode. 
   One embodiment of a method of switching performance modes of an SRAM system will be described with reference to  FIG. 5 . One of ordinary skill will recognize that the method may be implemented with any configurable SRAM system according to the present disclosure. In one example, SRAM system  500  may begin operation in an independent mode with SRAM cell  502  and SRAM cell  504  working independently from each other and cell control modules  530 ,  532  in a logically inactive state. A read and/or write operation may be implemented on SRAM cell  502  independently from SRAM cell  504  by activating wordlines  544  and  554  independently. SRAM system  500  may be switched to a shared mode by sending a cell control signal to cell control modules  530 ,  532  to switch cell control modules to a logically active state. In the logically active state, memory node  506  shares with memory node  516  and memory node  508  shares with memory node  518 . In a shared mode, a read and/or write operation may be implemented on a combined SRAM cell that includes SRAM cell  502  and SRAM cell  504 . In one example, wordlines  544  and  554  may be activated together to allow logical values to pass between memory nodes  506 ,  508 ,  516 ,  518  and bitlines  542 ,  548 . In one example, all SRAM cells in an array of SRAM system  500  SRAM cells may be switched from one mode to another simultaneously. 
   In another embodiment, logical values stored in memory nodes  506 ,  508 ,  516 ,  518  may be required to be saved for later use and/or invalidated when SRAM system  500  switches from one mode to another. In one example, one or more logical values stored in memory nodes  506 ,  508 ,  516 ,  518  may be cached in a system separate from SRAM system  500  according to well known memory caching mechanisms. In another example, a device including SRAM system  500  may be instructed to invalidate the memory cache of SRAM system  500  at or near the time of switching SRAM system  500  from one mode to another. 
   In one embodiment, an SRAM system according to the present disclosure allows two or more SRAM cells to switch between a process tolerant mode in which the memory nodes of the SRAM cells are shared to form an effective single larger SRAM cell from the two or more SRAM cells and a high performance mode in which the two or more SRAM cells operate independently. In one example, a process tolerant mode increases the size of the effective SRAM cell and reduces the impact of any sensitivities and/or variations (e.g., process and/or environmental variations) of the SRAM cells. In one example, a process tolerant mode may be utilized at a low voltage operation of a device including an SRAM system of the present disclosure. In another example, a high performance mode maximizes the memory capacity of an SRAM system of the present disclosure. Such maximization may occur during a high voltage operation of a device including an SRAM system of the present disclosure. 
   In one aspect, the present disclosure may provide an SRAM device including any number of SRAM cells (e.g., in an array) that operate in either a process tolerant mode (e.g., two or more SRAM cells shared) or in a high performance mode (e.g., each SRAM cell operating independently) depending on a predetermined condition of the SRAM device. In one example, where an SRAM circuit operates in a process tolerant mode, an amount of memory capacity of an SRAM device is reduced in trade-off for stability (e.g., at low voltage operation). 
   Exemplary embodiments have been disclosed above and illustrated in the accompanying drawings. It will be understood by those skilled in the art that various changes, omissions and additions may be made to that which is specifically disclosed herein without departing from the spirit and scope of the present invention.