Patent Publication Number: US-2013242631-A1

Title: Power converter apparatus

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a power converter apparatus that includes a first substrate and a second substrate, which are closely arranged to face each other, and switching elements mounted on the substrates. 
     A power converter apparatus of this type is disclosed in Japanese Laid-Open Patent Publication No. 2004-311685, for example. As shown in  FIG. 6 , a power semiconductor device  80  of the publication has a pair of insulating substrates  81   a  and  81   b,  which face each other. An insulated gate bipolar transistor (IGBT)  82   a  (upper arm) and an IGBT  82   b  (lower arm) are mounted on circuit traces of the insulating substrates  81   a  and  81   b,  respectively. The IGBTs  82   a  and  82   b  are connected in series. A positive input terminal  83   a  is connected to the insulating substrate  81   a,  and a negative input terminal  83   b  is connected to the insulating substrate  81   b.  The channel-shaped output terminal  84  is arranged between the insulating substrates  81   a  and  81   b,  and the output terminal  84  connects the circuit traces of the insulating substrates  81   a  and  81   b  in series. 
     In the power semiconductor device  80 , the pair of insulating substrates  81   a  and  81   b  are arranged to face each other, and the output terminal  84  connects the circuit traces of the insulating substrates  81   a  and  81   b  with each other. Accordingly, in the power semiconductor device  80 , the direction of current that flows from the positive input terminal  83   a  into the output terminal  84  through the insulating substrate  81   a  is opposite to the direction of current that flows from the output terminal  84  into the negative input terminal  83   b  through the insulating substrate  81   b.  As a result, the inductance of the whole power semiconductor device  80  may be reduced by mutual induction effect. Accordingly, surge voltage accompanying switching operations of the IGBTs  82   a  and  82   b  is reduced. 
     In the power semiconductor device  80 , since the IGBTs  82   a  and  82   b  are arranged to face each other between the pair of insulating substrates  81   a  and  81   b,  heat generated from both of the IGBTs  82   a  and  82   b  remains in the space between the insulating substrates  81   a  and  81   b.  However, measures for heat dissipation are not enough. 
     Accordingly, it is an object of the present invention to provide a power converter apparatus, which can regulate inductance of the whole apparatus low and improve heat dissipation property of the switching elements. 
     SUMMARY OF THE INVENTION 
     To achieve the foregoing object and in accordance with one aspect of the present invention, a power converter apparatus including a first substrate and a second substrate closely arranged to face with each other, switching elements mounted on a mounting surface of the first substrate and a mounting surface of the second substrate, a primary bus bar extending between the first substrate and the second substrate, an output terminal electrically connected to the primary bus bar, two input terminals provided on the second substrate and a secondary bus bar arranged close to the primary bus bar with the switching elements intervened therebetween is provided. The switching elements on the first substrate and the switching elements on the second substrate are connected to each other in series. The secondary bus bar extends between the first substrate and the second substrate. One of the two input terminals is electrically connected to the secondary bus bar. Current flows into the first and the second substrates and the primary and the secondary bus bars via the input terminals and the output terminal. The direction of the current that flows into the first substrate and the direction of the current that flows into the second substrate are opposite to each other and the direction of the current that flows into the primary bus bar and the direction of the current that flows into the secondary bus bar are opposite to each other. The first substrate and the second substrate each include a heat dissipating member provided on a surface thereof opposite to the mounting surface. 
     According to the above configuration, the direction of the current that flows into the first substrate and the direction of the current that flows into the second substrate are opposite to each other, in which the first substrate and the second substrate are arranged close to each other. Accordingly, magnetic flux generated by the current that flows into the first substrate is balanced out by mutual induction effect by magnetic flux generated by the current that flows into the second substrate. Also, the direction of the current that flows into the primary bus bar and the direction of the current that flows into the secondary bus bar are opposite to each other, in which the primary bus bar and the secondary bus bar are arranged close to each other. Accordingly, magnetic flux generated by the current that flows into the primary bus bar is balanced out by mutual induction effect by magnetic flux generated by the current that flows into the secondary bus bar. Therefore, in the power converter apparatus, inductance in whole current paths may be regulated to be low by the mutual induction effect at a plurality of portions in the current paths. Also, in each of the first substrate and the second substrate, a heat dissipating member is provided on a surface thereof opposite to the mounting surface for the switching elements. Accordingly, since heat generated by the switching elements on each of the substrates is emitted by the corresponding heat dissipating member, the switching elements are efficiently cooled. 
     Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
         FIG. 1  is a perspective view illustrating a power converter apparatus according to an embodiment; 
         FIG. 2  is a side view showing the power converter apparatus of  FIG. 1 ; 
         FIG. 3  is a circuit configuration diagram of the power converter apparatus of  FIG. 1 ; 
         FIG. 4  is a side view showing a power converter apparatus according to another embodiment; 
         FIG. 5  is a side view showing a power converter apparatus according to another embodiment; and 
         FIG. 6  is a side view showing a conventional semiconductor device for electric power. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A power converter apparatus according to an embodiment of the present invention will now be described with reference to  FIGS. 1 to 3 . 
     As shown in  FIGS. 1 and 2 , a power converter apparatus  10  configures an inverter circuit of a three-phase output, for example. A first heat sink  11  provided in a lower part of the power converter apparatus  10  is formed in a rectangular plate shape from metal such as aluminum-based metal and copper. The first heat sink  11  has a rectangular plate base  11   a  and a plurality of fins  11   b  arranged side by side on the lower surface of the base  11   a.  A first substrate  21 , which is shaped as a rectangular plate, is arranged on the upper surface of the base  11   a  of the first heat sink  11 . The first heat sink  11  (base  11   a ) is thermally coupled with the first substrate  21 . The direction in which the long sides of the first substrate  21  extend is defined as a longitudinal direction of the first substrate  21 , and the direction in which the short sides extend is defined as a transverse direction of the first substrate  21 . 
     An insulating substrate such as an insulating metal substrate is used as the first substrate  21 . On conductive traces of the first substrate  21 , a plurality of lower arm switching elements Q 2 , Q 4  and Q 6  are mounted side by side in the longitudinal direction of the first substrate  21 . Power semiconductor devices such as power MOS transistors and IGBTs are used as the lower arm switching elements Q 2 , Q 4  and Q 6 . Further, the lower arm switching elements Q 2 , Q 4  and Q 6  correspond to a lower arm switching element for a U-phase, a lower arm switching element for a V-phase, and a lower arm switching element for a W-phase from one of the short sides to the other one of the short sides of the first substrate  21  in this order. 
     Accordingly, in the present embodiment, the upper surface of the first substrate  21  is a mounting surface for the lower arm switching elements Q 2 , Q 4  and Q 6 . Also, the lower surface of the first substrate  21  is a surface opposite to the mounting surface for the lower arm switching elements Q 2 , Q 4  and Q 6 . The first heat sink  11  is mounted on the lower surface. Heat from the lower arm switching elements Q 2 , Q 4  and Q 6  is emitted from the first heat sink  11  via the first substrate  21 . The first heat sink  11  configures a heat dissipating member. 
     In the vicinity of one of the long sides of the first substrate  21 , a plurality of primary bus bars  23 U,  23 V and  23 W are arranged. Specifically, the primary bus bar  23 U for the U-phase, the primary bus bar  23 V for the V-phase and the primary bus bar  23 W for the W-phase are arranged from one of the short sides to the other one of the short sides of the first substrate  21  in this order. The primary bus bars  23 U,  23 V and  23 W are joined onto the first substrate  21 . Each of the primary bus bars  23 U,  23 V and  23 W has a rectangular base  23   a,  which extends in the longitudinal direction of the first substrate  21 , and a bar connection electrode portion  23   c , which stands from a central portion in a longitudinal direction of the base  23   a.    
     Further, each of the primary bus bars  23 U,  23 V and  23 W has an output terminal  23   b  provided on a second substrate  25  and the connection electrode portion  23   c  connected to the output terminal  23   b.  According to the present embodiment, each of the primary bus bars  23 U,  23 V and  23 W and the corresponding output terminal  23   b  are integrally formed with each other. In each of the primary bus bars  23 U, and  23 V and  23 W, the connection electrode portion  23   c  located under the second substrate  25  is formed broader than the output terminal  23   b  located on top of the second substrate  25 . Steps  23   d  are formed in a connection section between the connection electrode portion  23   c  and the output terminal  23   b.  Also, loads (not shown) such as a motor are connected to the output terminals  23   b,  which are respectively electrically connected to the corresponding primary bus bars  23 U,  23 V and  23 W. 
     A secondary bus bar  24  is arranged in the vicinity of a long side of the first substrate  21  that is opposite to the long side in the vicinity of which the primary bus bars  23 U,  23 V and  23 W are provided. This secondary bus bar  24  is joined onto the first substrate  21  and has a rectangular base  24   a , which extends in the longitudinal direction of the first substrate  21 , and a bar connection electrode portion  24   c , which stands from a central portion in the longitudinal direction of this base  24   a.  Further, in the secondary bus bar  24 , a negative input terminal  24   b  provided on the second substrate  25  is connected to the connection electrode portion  24   c.  According to the present embodiment, the secondary bus bar  24  and the negative input terminal  24   b  are integrally formed with each other. In the secondary bus bar  24 , the connection electrode portion  24   c  located under the second substrate  25  is formed broader than the negative input terminal  24   b  located on top of the second substrate  25 . Steps  24   d  are formed in a connection section between the connection electrode portion  24   c  and the negative input terminal  24   b.    
     The second substrate  25 , which is shaped as a rectangular plate, is supported by the steps  23   d  of the three primary bus bars  23 U,  23 V and  23 W and the steps  24   d  of the secondary bus bar  24 . The first substrate  21  and the second substrate  25  are closely arranged to face each other. That is, the primary bus bars  23 U,  23 V and  23 W and the secondary bus bar  24  also function as spacer portions for maintaining a space between the first substrate  21  and the second substrate  25 . Further, the primary bus bars  23 U,  23 V and  23 W, more specifically, the bases  23   a  and the connection electrode portions  23   c  extend between surfaces of the first substrate  21  and the second substrate  25 , which face each other. The secondary bus bar  24 , more specifically, the base  24   a  and the connection electrode portion  24   c  extend between the surfaces of the first substrate  21  and the second substrate  25 , which face each other. The direction in which the long sides of the second substrate  25  extend is defined as a longitudinal direction of the second substrate  25  and the direction in which the short sides extend is defined as a transverse direction of the second substrate  25 . 
     An insulating substrate such as an insulating metal substrate is used as the second substrate  25 . In the vicinity of one of the long sides of the second substrate  25 , the output terminals  23   b  for the respective phases are arranged on the second substrate  25 . Specifically, the output terminal  23   b  for the U-phase, the output terminal  23   b  for the V-phase, and the output terminal  23   b  for the W-phase are arranged from one of the short sides to the other one of the short sides of the second substrate  25  in this order. Further, in the vicinity of a long side of the second substrate  25  that is opposite to the long side on which the output terminals  23   b  are provided, the negative input terminal  24   b  is arranged on the upper surface of the second substrate  25 . The negative input terminal  24   b  is located in a central portion in the longitudinal direction of the second substrate  25 . 
     Moreover, in the second substrate  25 , a positive input terminal  26  is arranged in a region sandwiched by the three output terminals  23   b  and the negative input terminal  24   b.  The positive input terminal  26  is joined onto the second substrate  25 . The positive input terminal  26  has a rectangular base  26   a,  which extends in the longitudinal direction of the second substrate  25 , and a bar positive input terminal  26   b,  which stands from a central portion in a longitudinal direction of this base  26   a.  A power supply (not shown) is connected to the positive input terminal  26  and the negative input terminal  24   b.    
     On conductive traces of the second substrate  25 , a plurality of upper arm switching elements Q 1 , Q 3  and Q 5  are mounted side by side in the longitudinal direction of the second substrate  25 . Power semiconductor devices such as power MOS transistors and IGBTs are used as these upper arm switching elements Q 1 , Q 3  and Q 5 . Further, the respective upper arm switching elements Q 1 , Q 3  and Q 5  correspond to an upper arm switching element for the U-phase, an upper arm switching element for the V-phase and an upper arm switching element for the W-phase from one of the short sides to the other one of the short sides of the second substrate  25  in this order. The primary bus bars  23 U,  23 V and  23 W and the secondary bus bar  24  are closely arranged with each other with the respective switching elements Q 1  to Q 6  arranged therebetween. 
     Also, on the upper surface of the second substrate  25 , namely on a surface opposite to the switching elements Q 1 , Q 3  and Q 5 , a second heat sink  30  is mounted to be thermally coupled with the second substrate  25 . The second heat sink  30  is formed in a rectangular plate shape from metal such as aluminum-based metal and copper. The second heat sink  30  has a rectangular plate base  30   a  and a plurality of fins  30   b  arranged on an upper surface of the base  30   a  side by side. 
     Accordingly, in the present embodiment, the lower surface of the second substrate  25  is a mounting surface for the upper arm switching elements Q 1 , Q 3  and Q 5 . Also, the upper surface of the second substrate  25  is a surface opposite to the mounting surface for the upper arm switching elements Q 1 , Q 3  and Q 5 , and the second heat sink  30  is mounted on the upper surface. Heat from the upper arm switching elements Q 1 , Q 3  and Q 5  is emitted from the second heat sink  30  via the second substrate  25 . The second heat sink  30  configures a heat dissipating member. 
     Capacitors  31  are mounted on the second substrate  25 . For the capacitors  31 , for example, film capacitors with high capacitance or electrolytic capacitors with low capacitance that are connected in parallel, are used. In the second substrate  25 , conductive traces for drains of the upper arm switching elements Q 1 , Q 3  and Q 5  for the respective phases are electrically connected to the base  26   a  of the positive input terminal  26 . Further, in the first substrate  21 , conductive traces for sources of the lower arm switching elements Q 2 , Q 4  and Q 6  for the respective phases are electrically connected to the base  24   a  of the secondary bus bar  24 . Moreover, the positive terminals of the capacitors  31  are connected to the positive input terminal  26  via positive conductive traces, and negative terminals of the capacitors  31  are connected to the secondary bus bar  24  via negative conductive traces. 
     The second substrate  25  and first substrate  21  are electrically connected with each other by the primary bus bars  23 U,  23 V and  23 W and the secondary bus bar  24 . Specifically, between two input terminals, namely, the positive input terminal  26  and the negative input terminal  24   b  mounted on the second substrate  25 , the upper arm switching element Q 1  and the lower arm switching element Q 2  for the U-phase are connected in series by the primary bus bar  23 U for the U-phase and the secondary bus bar  24 . Further, the upper arm switching element Q 3  and the lower arm switching element Q 4  for the V-phase are connected in series by the primary bus bar  23 V for the V-phase and the secondary bus bar  24 . Moreover, the upper arm switching element Q 5  and the lower arm switching element Q 6  for the W-phase are connected in series by the primary bus bar  23 W for the W-phase and the secondary bus bar  24 . 
     In the power converter apparatus  10 , current from a power supply flows from the positive input terminal  26  to the capacitors  31  through the conductive traces of the second substrate  25  and to the upper arm switching elements Q 1 , Q 3  and Q 5  to be supplied to loads such as a motor via the output terminals  23   b  for the respective phases. Accordingly, in the second substrate  25 , as shown by a top arrow Y in  FIG. 2 , the current flows from right to left, namely from the positive input terminal  26  to the primary bus bars  23 U,  23 V and  23 W. 
     Then, the current returned from the loads flows from the output terminals  23   b  for the respective phases to the primary bus bars  23 U,  23 V and  23 W for the corresponding phases, namely, from top to bottom and to the lower arm switching elements Q 2 , Q 4  and Q 6  via the conductive traces of the first substrate  21 . Thereafter, the current flows through the secondary bus bar  24  from the bottom to the top via the conductive traces of the first substrate  21  into the negative input terminal  24   b.  Accordingly, in the first substrate  21 , as shown by a bottom arrow Y in  FIG. 2 , the current flows from left to right, namely, from the primary bus bars  23 U,  23 V and  23 W to the negative input terminal  24   b.  Therefore, as shown by the arrows Y in  FIG. 2 , the direction of the current that flows into the second substrate  25 , and the direction of the current that flows into the first substrate  21  are opposite to each other. Also, the direction of the current that flows through each of the primary bus bars  23 U,  23 V and  23 W and the direction of the current that flows into the secondary bus bar  24  are opposite to each other. 
     Next, a circuit configuration of the power converter apparatus  10  will be described. As shown in  FIG. 3 , an inverter circuit has six switching elements Q 1  to Q 6 . In the inverter circuit, the upper arm switching element Q 1  for the U-phase and the lower arm switching element Q 2  for the U-phase are connected in series, the upper arm switching element Q 3  for the V-phase and the lower arm switching element Q 4  for the V-phase are connected in series, and the upper arm switching element Q 5  for the W-phase and the lower arm switching element Q 6  for the W-phase are connected in series. 
     In the inverter circuit, the conductive traces for the drains of the upper arm switching elements Q 1 , Q 3  and Q 5  for the U-phase, the V-phase and the W-phase are electrically connected to the positive input terminal  26 . Further, the conductive traces for the sources of the lower arm switching elements Q 2 , Q 4  and Q 6  for the U-phase, the V-phase and the W-phase are electrically connected to the secondary bus bar  24 . 
     Moreover, the capacitors  31  are connected between the positive input terminal  26  and the secondary bus bar  24 . In order to simplify the description of the inverter circuit, 
       FIG. 3  shows the capacitors  31 . As current from the power supply flows from the positive input terminal  26  into the capacitors  31 , the capacitors  31  are charged. If the capacitors  31  are charged, current is supplied from the capacitors  31  to the loads via the respective switching elements Q 1  to Q 6 . 
     A connection point between the upper arm switching element Q 1  for the U-phase and the lower arm switching element Q 2  for the U-phase is connected to an output terminal U for the U-phase via the output terminal  23   b  of the primary bus bar  23 U for the U-phase. A connection point between the upper arm switching element Q 3  for the V-phase and the lower arm switching element Q 4  for the V-phase is connected to an output terminal V for the V-phase via the output terminal  23   b  of the primary bus bar  23 V for the V-phase. A connection point between the upper arm switching element Q 5  for the W-phase and the lower arm switching element Q 6  for the W-phase is connected to an output terminal W for the W-phase via the output terminal  23   b  of the primary bus bar  23 W for the W-phase. Loads such as a motor are connected to the output terminal U for the U-phase, the output terminal V for the V-phase and the output terminal W for the W-phase. 
     Next, the operation of the power converter apparatus  10  with the above described configuration will now be described. 
     As direct current from the power supply flows from the positive input terminal  26  to the capacitors  31  and into the upper arm switching elements Q 1 , Q 3  and Q 5  and the lower arm switching elements Q 2 , Q 4  and Q 6 , the switching elements Q 1  to Q 6  are respectively controlled to be turned on and off at predetermined intervals. Then, alternating current is supplied to the loads such as a motor via the output terminal U for the U-phase, the output terminal V for the V-phase and the output terminal W for the W-phase. The current flows from the secondary bus bar  24  into the power supply. Alternatively, regenerative current from the loads such as a motor flows into the upper arm switching elements Q 1 , Q 3  and Q 5  and the lower arm switching elements Q 2 , Q 4  and Q 6  and the switching elements Q 1  to Q 6  are respectively controlled to be turned on and off at predetermined intervals. The regeneration current flows into the capacitors  31  and from the positive input terminal  26  into the secondary bus bar  24  via the power supply. 
     Further, the first substrate  21  and second substrate  25 , which are arranged to face each other, are connected by the primary bus bars  23 U,  23 V and  23 W and the secondary bus bar  24 . Thereby, the direction of the current that flows into the first substrate  21  and the direction of the current that flows into the second substrate  25  are opposite to each other. Also, the direction of the current that flows into the primary bus bars  23 U,  23 V and  23 W and the direction of the current that flows through the secondary bus bar  24  are opposite to each other. In the power converter apparatus  10 , as the upper arm switching elements Q 1 , Q 3  and Q 5  are heated by switching operations, the heat is emitted from the second heat sink  30  via the second substrate  25 . Also, as the lower arm switching elements Q 2 , Q 4  and Q 6  are heated by switching operations, the heat is emitted from the first heat sink  11  via the first substrate  21 . 
     According to the above described embodiments, the following advantages are obtained. 
     (1) The first substrate  21  and the second substrate  25  are closely arranged to face each other. Also, the primary bus bars  23 U,  23 V and  23 W and the secondary bus bar  24  are arranged close to each other. Also, the direction of the current that flows into the first substrate  21  and the direction of the current that flows into the second substrate  25  are opposite to each other, and the direction of the current that flows into the primary bus bars  23 U,  23 V and  23 W and the direction of the current that flows into the secondary bus bar  24  are opposite to each other. Accordingly, magnetic flux generated by the currents that flow in the directions opposite to each other is balanced out by mutual induction effect so that the inductance in the whole current paths is regulated to be low. As a result, even if the switching operations of the respective switching elements Q 1  to Q 6  are performed rapidly, surge voltage is regulated to be low. Accordingly, it is not necessary to increase the breakdown voltage of the respective switching elements Q 1  to Q 6 . Therefore, switching elements at a low cost can be adopted as the respective switching elements Q 1  to Q 6 . Since the switching loss of the respective switching elements Q 1  to Q 6  is reduced, generation of heat by the respective switching elements Q 1  to Q 6  is also be suppressed. 
     (2) In the first substrate  21  and second substrate  25 , the heat sinks  11  and  30  are provided on a side opposite to the mounting surface for the respective switching elements Q 1  to Q 6 . Accordingly, the upper arm switching elements Q 1 , Q 3  and Q 5  can be individually cooled by the second heat sink  30 , and the lower arm switching elements Q 2 , Q 4  and Q 6  can be individually cooled by the first heat sink  11 . 
     (3) The upper arm switching elements Q 1 , Q 3  and Q 5  and the lower arm switching elements Q 2 , Q 4  and Q 6  are arranged on the surfaces of the first and the second substrates  21 ,  25 , which face each other. The first heat sink  11  is provided on an outer surface of the first substrate  21  and is exposed to an outside of the power converter apparatus  10 . The second heat sink  30  is provided on an outer surface of the second substrate  25  and is exposed to the outside of the power converter apparatus  10 . Therefore, even if the upper arm switching elements Q 1 , Q 3  and Q 5  and the lower arm switching elements Q 2 , Q 4  and Q 6  are arranged in a space between the surfaces of the first and the second substrates  21 ,  25  to face each other, heat generated by the respective switching elements Q 1  to Q 6  is efficiently emitted to the outside of the power converter apparatus  10  by the corresponding heat sinks  11  and  30 . As a result, the heat sinks  11  and  30 , which are provided on both of the substrates  21  and  25 , prevent the heat from being retained in the space between the first substrate  21  and the second substrate  25 , thereby efficiently cooling the respective switching elements Q 1  to Q 6 . 
     (4) The output terminals  23   b  for the respective phases, the negative input terminal  24   b  and the positive input terminal  26  are arranged on the second substrate  25 . That is, three of the terminals are collectively arranged on the single second substrate  25 . Accordingly, for example, compared with a case where the output terminals  23   b,  the negative input terminal  24   b  and the positive input terminal  26  are separately arranged on the first substrate  21  and the second substrate  25 , operations for connecting wires such as wire harness to the respective terminals can be easily performed. 
     (5) In the power converter apparatus  10 , the first substrate  21  and the second substrate  25  are closely arranged to face each other and the upper arm switching elements Q 1 , Q 3  and Q 5  and the lower arm switching elements Q 2 , Q 4  and Q 6  are connected by the primary bus bars  23 U,  23 V and  23 W in series. Accordingly, compared with a case where the upper arm switching elements Q 1 , Q 3  and Q 5  and the lower arm switching elements Q 2 , Q 4  and Q 6  are arranged on a single substrate to be respectively connected in series, a current path is shortened to suppress self-inductance. Therefore, the current path is shortened to suppress the self-inductance, and the directions of the flowing current are inversed to utilize mutual induction effect so that the inductance of the whole power converter apparatus  10  is suppressed to be low. 
     (6) The output terminals  23   b  are integrally formed with the corresponding primary bus bars  23 U,  23 V and  23 W. Accordingly, for example, compared with a case where the primary bus bars  23 U,  23 V and  23 W are separate from the output terminals  23   b,  the number of parts of the power converter apparatus  10  is reduced. 
     The above described embodiments may be modified as follows. 
     According to the above described embodiment, the upper arm switching elements Q 1 , Q 3  and Q 5  are provided on the lower surface (mounting surface) of the second substrate  25  and the second heat sink  30  is provided on the upper surface of the second substrate  25 . Also, the upper arm switching elements Q 2 , Q 4  and Q 6  are provided on the upper surface (mounting surface) of the first substrate  21  and the first heat sink  11  is provided on the lower surface of the first substrate  21 . Such an arrangement is not limited to the above described embodiment, however. The mounting surfaces of the substrates  21 ,  25  for the respective switching elements Q 1  to Q 6  and the surfaces on which the respective heat sinks  11  and  30  are provided may be changed. 
     As shown in  FIG. 4 , in a manner similar to that of the above described embodiment, the upper arm switching elements Q 1 , Q 3  and Q 5  may be mounted on the lower surface (mounting surface) of the second substrate  25  and the second heat sink  30  may be provided on the upper surface of the second substrate  25 . In the upper arm switching elements Q 1 , Q 3  and Q 5 , a heat dissipating member  43  may be thermally coupled with surfaces (lower surfaces) opposite to joining surfaces (upper surfaces) of the switching elements Q 1 , Q 3  and Q 5  to be joined with the second substrate  25 . 
     Also, in the first substrate  21 , in a manner similar to that of the above described embodiment, the lower arm switching elements Q 2 , Q 4  and Q 6  may be mounted on the upper surface (mounting surface) of the first substrate  21  and the first heat sink  11  may be provided on the lower surface of the first substrate  21 . In the lower arm switching elements Q 2 , Q 4  and Q 6 , a heat dissipating member  44  may be thermally coupled with surfaces (upper surfaces) opposite to joining surfaces (lower surfaces) of the switching elements Q 2 , Q 4  and Q 6  to be joined with the first substrate  21 . 
     As configured in this manner, the upper arm switching elements Q 1 , Q 3  and Q 5  are sandwiched by the second heat sink  30  and the heat dissipating member  43  to improve heat dissipating property. Also, the lower arm switching elements Q 2 , Q 4  and Q 6  are sandwiched by the first heat sink  11  and the heat dissipating member  44  to improve heat dissipating property. 
     Further, as shown in  FIG. 5 , the upper arm switching elements Q 1 , Q 3  and Q 5  may be mounted on the upper surface (mounting surface) of the second substrate  25 , and a heat dissipating member  40  may be thermally coupled with the surfaces opposite to the joining surfaces of the upper arm switching elements Q 1 , Q 3  and Q 5  to be joined with the second substrate  25 . Upon this, the second heat sink  30  is provided on the lower surface (the surface opposite to the mounting surface) of the second substrate  25 . 
     Also, the lower arm switching elements Q 2 , Q 4  and Q 6  may be mounted on the lower surface (mounting surface) of the first substrate  21 , and a heat dissipating member  41  may be thermally coupled with the surfaces opposite to the joining surfaces of the lower arm switching elements Q 2 , Q 4  and Q 6  to be joined with the first substrate  21 . Upon this, the first heat sink  11  is provided on the upper surface (the surface opposite to the mounting surface) of the first substrate  21 . In this case, in order to prevent heat from being retained between the first heat sink  11  and the second heat sink  30 , it is preferable to provide a fan  42  or a cooler (not shown) in place of the first heat sink  11  and the second heat sink  30 . 
     As configured above, in addition to the heat sinks  11  and  30  provided on the substrates  21  and  25 , respectively, the heat generated by the respective switching elements Q 1  to Q 6  may be emitted by the heat dissipating members  40  and  41  provided on the switching elements Q 1  to Q 6 . Accordingly, since the two heat dissipating members are thermally coupled with the single switching element, the respective switching elements Q 1  to Q 6  may be efficiently cooled. 
     In the above embodiment, although the output terminals  23   b,  the negative input terminal  24   b  and the positive input terminal  26  are arranged on the second substrate  25 , the output terminals  23   b,  the negative input terminal  24   b  and positive input terminal  26  may be distributed to the first substrate  21  and the second substrate  25 , respectively or collectively arranged on the first substrate  21  as long as electrical connection is maintained. 
     According to the above described embodiment, the capacitors  31  are mounted on the second substrate  25 . The capacitors, however, may be distributed to the first substrate  21  and second substrate  25  separately corresponding to the upper arm and the lower arm switching elements or may be mounted on the first substrate  21  only. 
     In the above embodiment, the lower arm switching elements Q 2 , Q 4  and Q 6  are mounted on the first substrate  21  and the upper arm switching elements Q 1 , Q 3  and Q 5  are mounted on the second substrate  25 . The mounting configuration, however, is not limited to this. The upper arm switching elements Q 1 , Q 3  and Q 5  may be mounted on the first substrate  21  and the lower arm switching elements Q 2 , Q 4  and Q 6  may be mounted on the second substrate  25 . 
     In the above described embodiment, the output terminals  23   b  are integrally formed with the corresponding primary bus bars  23 U,  23 V and  23 W. The output terminals  23   b,  however, may be separate from the primary bus bars  23 U,  23 V and  23 W. That is, the primary bus bars  23 U,  23 V and  23 W respectively connect the upper arm switching elements Q 1 , Q 3  and Q 5  and the lower arm switching elements Q 2 , Q 4  and Q 6  in series. As long as the output terminals  23   b  are electrically connected to the primary bus bars  23 U,  23 V and  23 W, positions or forms of the output terminals  23   b  may be modified as necessary. 
     In the above described embodiment, the negative input terminal  24   b  is integrally formed with the secondary bus bar  24 . The negative input terminal  24   b,  however, may be separate from the secondary bus bar  24 . 
     In the above described embodiment, the negative input terminal  24   b  is electrically connected to the secondary bus bar  24 . The positive input terminal  26 , however, may be electrically connected to the secondary bus bar  24  in place of the negative input terminal  24   b.    
     Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.