Patent Publication Number: US-11644920-B2

Title: Capacitance detection circuit and input device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present invention claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2020-057686 filed on Mar. 27, 2020, the entire content of which is incorporated herein by reference. 
     BACKGROUND FIELD 
     The field relates to a capacitance detection circuit for an electrostatic capacitance. 
     DESCRIPTION OF THE PRIOR ART 
     In recent years, touch type input devices are provided in electronic apparatuses such as computers, smartphones, tablet terminals and portable audio devices to serve as user interfaces. Known touch type input devices include touchpads and pointing device that perform various inputs by contacting or approaching of a finger or a stylus. 
     Touch type input devices are substantially divided into resistive film type and electrostatic capacitance type. In the electrostatic capacitance type, a plurality of sensor electrodes convert electrostatic capacitances (referred to as a capacitance below) generated by a user input to electrical signals so as to detect the presence or absence of a user input and coordinate position thereof. 
     Methods for detecting the electrostatic capacitance are substantially divided into self-capacitance type and mutual capacitance type. The self-capacitance type has extremely high sensitivity, and is capable of detecting touch operation as well as finger approach. However, the self-capacitance type suffers issues of being incapable of distinguishing waterdrops from touching or detecting a two-point touch. On the other hand, the mutual capacitance type features advantages of capabilities for detecting a two-point touch (or a multi-point touch of more than two points), and is less likely affected by waterdrops. Thus, either one or both of the self-capacitance type and the mutual capacitance type can be selected according to an intended purpose. 
       FIG.  1    shows a block diagram of a comparative embodiment of touch type input device  10  of the self-capacitance type. The touch type input device  10  includes a touch panel  12  and a capacitance detection circuit  20 . The touch panel  12  includes a sensor electrode SE, and the sensor electrode SE is connected to a sense pin SNS of the capacitance detection circuit  20 . The capacitance detection circuit  20  detects an electrostatic capacitance Cs generated between the sensor electrode SE and a finger  2  of a user or a stylus. 
     The capacitance detection circuit  20  includes multiple switches SW 81  to SW 90 , four reference capacitors Cr 1  to Cr 4 , and an analog-to-digital converter (ADC)  22 . The electrostatic capacitance Cs is converted to differential voltage signals Vs_p and Vs_n by the multiple switches SW 81  to SW 90  and the four reference capacitors Cr 1  to Cr 4 , and then converted to a digital signal by the ADC  22 . 
     PRIOR ART DOCUMENTS 
     Patent Documents 
     [Patent document 1] Japan Patent Publication No. 2015-132506 
     [Patent document 2] Japan Patent Publication No. 2014-45475 
     SUMMARY 
     Each of the reference capacitors Cr 1  to Cr 4  has a capacitance equivalent to the electrostatic capacitance Cs formed by the sensor electrode SE. In recent years, the capacitance of the electrostatic capacitance Cs increases along with the continuous trend of thinning the touch panel  12 . Thus, when the reference capacitors Cr 1  to Cr 4  are integrated on a semiconductor chip, the area occupied thereof is increased, incurring to higher production costs. 
     The present disclosure is implemented in view of the above issues, and an exemplary object of an embodiment thereof is to provide a capacitance detection circuit for reducing a chip area. 
     A capacitance detection circuit according to an embodiment includes: a sense pin connected to a sensor electrode; a reference capacitor; a first driving unit configured to apply a high voltage or a low voltage to the sense pin; a second driving unit configured to apply the high voltage or the low voltage to a first terminal of the reference capacitor; a third driving unit configured to apply the high voltage or the low voltage to a second terminal of the reference capacitor; a first switch disposed between the sense pin and the first terminal of the reference capacitor; and a second switch disposed between an input of a post-stage circuit block and the first terminal of the reference capacitor. 
     A capacitance detection circuit according to an embodiment includes: a sense pin connected to a sensor electrode; a first reference capacitor; a second reference capacitor; a first driving unit configured to apply a high voltage or a low voltage to the sense pin; a second driving unit configured to apply the high voltage or the low voltage to a first terminal of the first reference capacitor; a third driving unit configured to apply the high voltage or the low voltage to a second terminal of the first reference capacitor; a fourth driving unit configured to apply the high voltage or the low voltage to a first terminal of the second reference capacitor; a fifth driving unit configured to apply the high voltage or the low voltage to a second terminal of the second reference capacitor; a first switch disposed between the sense pin and the first terminal of the first reference capacitor; a second switch disposed between a first input of a post-stage circuit block including differential inputs and the first terminal of the first reference capacitor; a third switch disposed between the sense pin and the first terminal of the second reference capacitor; and a fourth switch disposed between a second input of the post-stage circuit block and the first terminal of the second reference capacitor. 
     Moreover, any combination from the constituents above or any expression of the present disclosure as a conversion between methods and devices is also effective as a form of the present disclosure. 
     According to the present disclosure, the chip area can be reduced. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    shows a block diagram of a touch type input device of the self-capacitance type according to a comparative embodiment. 
         FIG.  2    is a block diagram of a touch type input device including a capacitance detection circuit according to a first embodiment of the present disclosure; 
         FIG.  3 A  to  FIG.  3 F  are equivalent circuit diagrams of a capacitance/voltage (C/V) conversion circuit in a first phase ϕ 1 , a second phase ϕ 2 , . . . to a sixth phase ϕ 6 ; 
         FIG.  4    is a waveform diagram illustrating the operation of the C/V conversion circuit in  FIG.  2   ; 
         FIG.  5    is a diagram showing an example of a specific configuration example of a capacitance detection circuit; 
         FIG.  6    is a circuit diagram illustrating a capacitance detection circuit according to a second embodiment; 
         FIG.  7 A  to  FIG.  7 E  are equivalent circuit diagrams illustrating a C/V conversion circuit in a first phase ϕ 1 , a second phase ϕ 2 , . . . to a fifth phase ϕ 5 ; 
         FIGS.  8 A - FIG.  8 E  are equivalent circuit diagrams illustrating a C/V conversion circuit in a sixth phase ϕ 6  to a tenth phase ϕ 10 ; 
         FIG.  9    is a circuit diagram illustrating a C/V conversion circuit; 
         FIG.  10    is a circuit diagram illustrating a reference capacitor Cr and a third driving unit according to the first embodiment; 
         FIGS.  11 A  TO  FIG.  11 B  are diagrams for illustrating a layout of a capacitance detection circuit; 
         FIG.  12 A  is a circuit diagram illustrating a reference capacitor and a third driving unit according to the second embodiment of the present disclosure, and  FIG.  12 B  is a circuit diagram illustrating a reference capacitor and a third driving unit according to a third embodiment of the present disclosure; and 
         FIG.  13    is a circuit diagram illustrating a capacitance detection circuit according an alternative embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     One or more aspects of the present invention are described with reference to the following description and the accompanying drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are shown in block diagram or not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Further, not all illustrated acts or events are required to implement a methodology in accordance with the present invention. 
     In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the present invention. It may be evident, however, to one skilled in the art that one or more aspects of the present invention may be practiced with a lesser degree of these specific details. While a particular feature of the invention may have been disclosed with respect to only one of several aspects of the implementations, such feature may be combined with one or more other features of other implementations as may be desired and advantageous for any given or particular application. 
     An embodiment disclosed in the detailed description relates to a capacitance detection circuit for detecting a capacitance of a sensor electrode. The capacitance detection circuit includes: a sense pin connected to a sensor electrode; a reference capacitor; a first driving unit configured to apply a high voltage or a low voltage to the sense pin; a second driving unit configured to apply the high voltage or the low voltage to a first terminal of the reference capacitor; a third driving unit configured to apply the high voltage or the low voltage to a second terminal of the reference capacitor; a first switch disposed between the sense pin and the first terminal of the reference capacitor; and a second switch disposed between an input of a post-stage circuit block and the first terminal of the reference capacitor. 
     According to the configuration above, the number of the reference capacitor can be reduced to one, and the circuit area can be reduced. 
     In the capacitance detection circuit, in a first phase, the first driving unit applies the high voltage to the sense pin, the second driving unit applies the low voltage to the first terminal of the reference capacitor, and the third driving unit applies the high voltage to the second terminal of the reference capacitor; in a second phase, the first switch is closed, and the third driving unit applies the low voltage to the second terminal of the reference capacitor; and in a third phase, the second switch is closed, and the third driving unit applies the low voltage to the second terminal of the reference capacitor. 
     Furthermore, in the capacitance detection circuit, in a fourth phase, the first driving unit applies the low voltage to the sense pin, the second driving unit applies the high voltage to the first terminal of the reference capacitor, and the third driving unit applies the high voltage to the second terminal of the reference capacitor; in a fifth phase, the first switch is closed, and the third driving unit applies the high voltage to the second terminal of the reference capacitor; and in a sixth phase, the second switch is closed, the third driving unit applies the high voltage to the second terminal of the reference capacitor. 
     The post-stage circuit block can include a sigma-delta (As) modulator. 
     The post-stage circuit block can include an integrator, and an analog-to-digital converter (ADC) configured to convert an output of the integrator to a digital value. 
     The reference capacitor can be a variable capacitor, and includes a plurality of capacitive elements and multiple switches disposed between a first side of the plurality of capacitive elements and the first terminal. 
     The second driving unit can independently apply the high voltage and the low voltage to a second side of each of the plurality of capacitive elements. 
     The plurality of capacitive elements in the reference capacitor can be Metal-Insulator-Metal (MIM) capacitors, and at least one portion of the plurality of capacitive elements is disposed at a region overlapping with an integrated region of a transistor element. Accordingly, the chip area can be further reduced. 
     An embodiment disclosed in the detailed description further relates to a capacitance detection circuit. The capacitance detection circuit includes: a sense pin connected to a sensor electrode; a first reference capacitor; a second reference capacitor; a first driving unit configured to apply a high voltage or a low voltage to the sense pin; a second driving unit configured to apply the high voltage or the low voltage to a first terminal of the first reference capacitor; a third driving unit configured to apply the high voltage or the low voltage to a second terminal of the first reference capacitor; a fourth driving unit configured to apply the high voltage or the low voltage to a first terminal of the second reference capacitor; a fifth driving unit configured to apply the high voltage or the low voltage to a second terminal of the second reference capacitor; a first switch disposed between the sense pin and the first terminal of the first reference capacitor; a second switch disposed between a first input of a post-stage circuit block including differential inputs and the first terminal of the first reference capacitor; a third switch disposed between the sense pin and the first terminal of the second reference capacitor; and a fourth switch disposed between a second input of the post-stage circuit block and the first terminal of the second reference capacitor. 
     According to the configuration above, the number of the reference capacitor can be reduced to two, and the circuit area can be reduced. 
     The capacitance detection circuit can be integrated on a semiconductor integrated circuit. The so-called “integrated” includes a situation where all components of the circuit are formed on a semiconductor substrate, or including a situation where main components of the circuit are integrated, while having a portion of resistors or capacitors configured on the outside of the semiconductor substrate for adjusting a circuit constant. By integrating the circuit on one chip, the circuit area can be reduced, and characteristics of the circuit elements can be kept in uniform. 
     EMBODIMENTS 
     The present disclosure is described by way of appropriate embodiments with the accompanying drawings below. The same symbols and denotations are assigned to the same or equivalent constituents, components and processes in the drawings, and repeated description is appropriately omitted. Furthermore, the embodiments are merely illustrative and exemplary, and are not to be construed as limitations to the present disclosure. Further, not all features and combinations thereof stated in the embodiments are necessarily essentials of the present disclosure. 
     In the detailed description, as used herein, the term “connected” as used to describe the situation of “a state in which component A is connected to component B” is defined to include a situation where component A is physically and directly connected to component B, and includes a situation where component A is indirectly connected to component B via other components without producing substantive influences on the electrical connection state of said components, or without damaging functions or effects achieved by the combinations of said components. 
     Similarly, as used herein, the term “disposed” as used to describe the situation of “a state in which component C is disposed between component A and component B” is defined to include, a situation where component A and component C, or component B and component C are directly connected, and a situation of indirect connection via other components without producing substantive influences on the electrical connection state of said components, or without damaging functions or effects achieved by the combinations of said components. 
       FIG.  2    shows a block diagram of a touch type input device  100  including a capacitance detection circuit  200  according to a first embodiment. The touch type input device  100  includes a panel  110  and the capacitance detection circuit  200 . The touch type input device  100  is a user interface for detecting a touch operation performed by a finger  2  (or a stylus) of a user. 
     The panel  110  is a touch panel or a switch panel, and includes one or more sensor electrodes SE. In this embodiment, only the part corresponding to one sensor electrode SE is depicted. 
     A host processor  120  integrally controls machines, apparatuses and systems disposed with the touch type input device  100 . The capacitance detection circuit  200  detects an electrostatic capacitance of each sensor electrode SE, and transmits them to the host processor  120 . Furthermore, the capacitance detection circuit  200  can compare a detected electrostatic capacitance Cs with a threshold to value detect the presence or absence of a touch and transmit an indication of the presence or absence of touch operation to the host processor  120 . 
     The capacitance detection circuit  200  includes a sense pin SNS, a capacitance/voltage (C/V) conversion circuit  210 , an analog-to-digital converter (ADC)  220  and an interface circuit  230 . 
     The sensor electrode SE is connected to the sense pin SNS. The C/V conversion circuit  210  converts the electrostatic capacitance Cs generated by the sensor electrode SE to a voltage signal Vs. The ADC  220  is coupled to the output of the analog circuit  210  and converts the voltage signal Vs to a digital signal Ds. The interface circuit  230  is coupled to the ADC  220  and transmits the digital signal Ds to the host processor  120 . 
     The C/V conversion circuit  210  is a front end circuit that converts the electrostatic capacitance Cs to a voltage signal, and includes a first driving unit  212 , a second driving unit  214 , a third driving unit  216 , a first switch SW 11 , a second switch SW 12 , a reference capacitor Cr and a controller  218 . 
     The first driving unit  212  applies a high voltage V H  or a low voltage V L  to the sense pin SNS. For example, the high voltage V H  is a power voltage V DD  of a power line AVDD, and the low voltage V L  is a ground voltage V GND  (=0 V) of a ground line GND. 
     The second driving unit  214  applies the high voltage V H  or the low voltage V L  to a first terminal e 1  of the reference capacitor Cr. 
     The third driving unit  216  applies the high voltage V H  or the low voltage V L  to a second terminal e 2  of the reference capacitor Cr. 
     Each of the first driving unit  212 , the second driving unit  214  and the third driving unit  216  includes a high-side switch MH and a low-side switch ML. 
     The first switch SW 11  is disposed between the sense pin SNS and the first terminal e 1  of the reference capacitor Cr. The second switch SW 12  is disposed between an input of the post-stage ADC  220  and the first terminal e 1  of the reference capacitor Cr. 
     The controller  218  is configured to control the first driving unit  212 , the second driving unit  214 , the third driving unit  216 , the first switch SW 11  and the second switch SW 12 . In this embodiment, the controller  218  switches the state of the C/V conversion circuit  210  between a first phase ϕ 1 , a second phase ϕ 2 , . . . and a sixth phase ϕ 6 .  FIGS.  3 ( a ) to  3 ( f )  show equivalent circuit diagrams of the C/V conversion circuit  210  in the first phase ϕ 1 , the second phase ϕ 2 , . . . to the sixth phase ϕ 6 . The first phase ϕ 1 , the second phase ϕ 2  and the third phase ϕ 3  are the unit for one round of sensing, and the fourth phase ϕ 4 , the fifth phase ϕ 5 , . . . to the sixth phase ϕ 6  are the unit for one round of sensing. 
     As shown in  FIG.  3 A , in the first phase ϕ 1 , the first driving unit  212  applies the high voltage V H  to the sense pin SNS, the second driving unit  214  applies the low voltage V L  to the first terminal e 1  of the reference capacitor Cr, and the third driving unit  216  applies the high voltage V H  to the second terminal e 2  of the reference capacitor Cr. At this point in time, a charge amount Qr of the reference capacitor Cr becomes 0, and a charge amount Qs of the electrostatic capacitance Cs becomes V H ×Cs. 
     As shown in  FIG.  3 B , in the second phase ϕ 2 , the first switch SW 11  is closed, and the third driving unit  216  applies the low voltage V L  to the second terminal e 2  of the reference capacitor Cr. As used in this specification, when a switch is described as “closed,” it means that current may flow across the switch; a switch may include a transistor switch, mechanical switch, or other switch. In this state, transmission between the electrostatic capacitance Cs and the reference capacitor Cr is formed, thereby smoothing the charge amounts Qs and Qr.
 
 Cs×V   H =( Cs+Cr )× Vs  
 
     At this point in time, the internal voltage Vs is represented by equation (1):
 
 Vs=Cs /( Cs+Cr )× V   H   (1)
 
     As shown in  FIG.  3 C , in the third phase ϕ 3 , the second switch SW 12  is closed, and the third driving unit  216  applies the low voltage V L  to the second terminal e 2  of the reference capacitor Cr. Thereby, the sensing voltage Vs is supplied to the ADC  220  in the post-stage. 
     As shown in  FIG.  3 D , in the fourth phase ϕ 4 , the first driving unit  212  applies the low voltage V L  to the sense pin SNS, the second driving unit  214  applies the high voltage V H  to the first terminal e 1  of the reference capacitor Cr, and the third driving unit  216  applies the high voltage V H  to the second terminal e 2  of the reference capacitor Cr. At this point in time, the charge amount Qr of the reference capacitor Cr becomes 0, and the charge amount Qs of the electrostatic capacitance Cs becomes 0. 
     As shown in  FIG.  3 E , in the fifth phase ϕ 5 , the first switch SW 11  is closed, and the third driving unit  216  applies the high voltage V H  to the second terminal e 2  of the reference capacitor Cr. In this state, the internal voltage Vs is represented by equation (2):
 
 Vs=Cr /( Cs+Cr )× V   H   =V   H   −Cs /( Cs+Cr )× V   H   (2)
 
     As shown in  FIG.  3 F , in the sixth phase ϕ 6 , the second switch SW 12  is closed, and the third driving unit  216  applies the high voltage V H  to the second terminal e 2  of the reference capacitor Cr. Thereby, the sensing voltage Vs is supplied to the ADC  220  in post-stage. 
     An example of a configuration of the touch type input device  100  is as described above, and the operation thereof is subsequently described.  FIG.  4    shows a waveform diagram of the operation of the C/V conversion circuit  210  in  FIG.  2   . In the first phase ϕ 1 , the switch MH 1  is closed, and the voltage V SNS  of the sense pin SNS becomes the high voltage V H =V DD . Furthermore, the switches ML 2  and ML 3  are closed, and the internal voltage Vs becomes the low voltage V L =0 V. In the following second phase ϕ 2 , the first switch SW 11  is closed, electric charges are transmitted between the electrostatic capacitance Cs and the reference capacitor Cr, and the internal voltage Vs is stable at the voltage level represented by equation (1). Then, in the third phase ϕ 3 , the second switch SW 12  is closed, and the internal voltage Vs is supplied to the post stage. 
     In the fourth phase ϕ 4 , the switch ML 1  is closed, and the voltage V SNS  of the sense pin SNS becomes the low voltage V L =0 V. Furthermore, the switches MH 2  and MH 3  are closed, and the internal voltage Vs becomes the high voltage V H =V DD . In the following fifth phase ϕ 5 , the first switch SW 11  is closed, and electric charges are transmitted between the electrostatic capacitance Cs and the reference capacitor Cr, and the internal voltage Vs is stable at the voltage level represented by equation (2). Then, in the sixth phase ϕ 6 , the second switch SW 12  is closed, and the internal voltage Vs is supplied to the post stage. 
     The operation of the capacitance detection circuit  200  is as described above. The capacitance detection circuit  200  is capable of reducing the number of the reference capacitor Cr to one, hence reducing the circuit area. 
       FIG.  5    illustrates an example of a diagram of a specific configuration of the capacitance detection circuit  200 . The ADC  220  is a delta-sigma (ΔΣ) modulator, and the digital signal Ds is a bitstream obtained by oversampling. 
     The ΔΣ modulator usually includes a subtractor  221 , an integrator  222 , a comparator  223  and a digital-to-analog converter (DAC)  224 . In this configuration, a capacitor Cfb serves the functions of the subtractor  221  and the DAC  224 . By using the capacitor Cfb, a high voltage or a low voltage corresponding to the bitstream Ds is feed backed to the input of the ADC  220 , and a signal component equivalent to a difference to the sensing voltage Vs from the C/V conversion circuit  210  is inputted to the integrator  222 . The integrator  222  accumulates the difference. The comparator  226  compares an output of the integrator  222  with the reference voltage, and converts the same to a bitstream. Four switches are provided on two terminals of a capacitor C INT  of the integrator  222 , and the polarity of the capacitor C INT  is inverted during the periods of processing the voltage Vs obtained in the third phase ϕ 3  and the voltage Vs obtained in the sixth phase ϕ 6 . 
     Furthermore, the configuration of the ADC  220  is not limited to that in  FIG.  5   , and ADCs in various forms and approaches can be utilized. 
     Second Embodiment 
       FIG.  6    shows a circuit diagram of a capacitance detection circuit  300  according to a second embodiment. The capacitance detection circuit  300  includes a C/V conversion circuit  310  and an ADC  330 . The ADC  330  has differential inputs. 
     The sensor electrode SE is connected to the sense pin SNS. The C/V conversion circuit  310  includes a first driving unit  312 , a second driving unit  314 , a third driving unit  316 , a fourth driving unit  318 , a fifth driving unit  320 , a controller  322 , a first switch SW 21 , a second switch SW 22 , a third switch SW 23 , and a fourth switch SW 24 . 
     The first driving unit  312  applies the high voltage V H  or the low voltage V L  to the sense pin SNS. The second driving unit  314  applies the high voltage V H  or the low voltage V L  to a first terminal e 1  of a first reference capacitor Cr 1 . The third driving unit  316  applies the high voltage V H  or the low voltage V L  to a second terminal e 2  of the first reference capacitor Cr 1 . The fourth driving unit  318  applies the high voltage V H  or the low voltage V L  to a first terminal e 1  of a second reference capacitor Cr 2 . The fifth driving unit  320  applies the high voltage V H  or the low voltage V L  to a second terminal e 2  of the second reference capacitor Cr 2 . 
     Each of the first driving unit  312 , the second driving unit  314  . . . and the fifth driving unit  320  includes a high-side switch MH and a low-side switch ML. The first switch SW 21  is disposed between the sense pin SNS and the first terminal e 1  of the first reference capacitor Cr 1 . The second switch SW 22  is disposed between a first input of the differential inputs of the ADC  220  and the first terminal e 1  of the first reference capacitor Cr 1 . 
     The third switch SW 23  is disposed between the sense pin SNS and the first terminal e 1  of the second reference capacitor Cr 2 . The fourth switch SW 24  is disposed between the second input of the ADC  220  and the first terminal e 1  of the second reference capacitor Cr 2 . 
     The controller  322  controls the first driving unit  312 , the second driving unit  314  . . . and the fifth driving unit  320 , and the first switch SW 21 , the second switch SW 22  . . . and the fourth switch SW 24 . 
       FIGS.  7 ( a ) to  7 ( f )  are equivalent circuit diagrams of the C/V conversion circuit  310  in the first phase ϕ 1  to the fifth phase ϕ 5 . The first phase ϕ 1  and the second phase ϕ 2  in  FIGS.  7 ( a ) and  7 ( b )  correspond to the first phase ϕ 1  and the second phase ϕ 2  in  FIGS.  3 ( a ) and  3 ( b ) , respectively. In the second phase ϕ 2 , an internal voltage Vs 1  of equation (1a) is generated:
 
 Vs 1= Cs /( Cs+Cr 1)× V   H   (1a)
 
     The third phase ϕ 3  and the fourth phase ϕ 4  in  FIGS.  7 ( c ) and  7 ( d )  correspond to the fourth phase ϕ 4  and the fifth phase ϕ 5  in  FIGS.  3 ( d ) and  3 ( e ) , respectively. In the fourth phase ϕ 4 , an internal voltage Vs 2  of equation (2a) is generated:
 
 Vs 2= V   H   −Cs /( Cs+Cr 2)× V   H   (2a)
 
     In the fifth phase ϕ 5  of  FIG.  7 E , the second switch SW 22  and the fourth switch SW 24  are closed, and the differential signals Vs 1  and Vs 2  are supplied to the ADC  330  in post-stage. 
       FIGS.  8 ( a ) to  8 ( f )  are equivalent circuit diagrams of the C/V conversion circuit  310  in a sixth phase ϕ 6 , a seventh phase ϕ 7  . . . to a tenth phase ϕ 10 .  FIGS.  8 ( a ) and  8 ( b )  depict processes performed after polarity inversion in the processes of  FIGS.  7 ( a ) and  7 ( b ) , respectively, and the internal voltage Vs 1  of equation (1b) is generated:
 
 Vs 1= V   H   −Cs /( Cs+Cr 1)× V   H   (1b)
 
       FIGS.  8 ( c ) and  8 ( d )  depict processes performed after polarity inversion in the processes of  FIGS.  7 ( c ) and  7 ( d ) , respectively, and an internal voltage Vs 2  of equation (2b) is generated:
 
 Vs 2= Cs /( Cs+Cr 2)× V   H   (2b)
 
     In the tenth phase ϕ 10  in  FIG.  8 E , the second switch SW 22  and the fourth switch SW 24  are closed, and the differential signals Vs 1  and Vs 2  are supplied to the ADC  330  in post-stage. 
     In addition, it should be understood that a person skilled in the art can switch the orders of the phases in  FIGS.  7 A - FIG.  7 E  and  FIG.  8 A - FIG.  8 E . 
     The operation of the capacitance detection circuit  300  is described as above. The capacitance detection circuit  300  is capable of reducing the number of the reference capacitor from four to two, hence reducing the circuit area. 
     An example of a specific configuration of the reference capacitor Cr is subsequently discussed. The C/V conversion circuit  210  of the first embodiment is taken as an example; however, the same description applies to the C/V conversion circuit  310  of the second embodiment. 
       FIG.  9    shows a circuit diagram of the C/V conversion circuit  210 . The capacitance of the reference capacitor Cr is preferably equivalent to the electrostatic capacitance Cs, which is the detection target. For the capacitance detection circuit  200 , versatility of application in combination with panels  110  having various sizes or thicknesses is required. Therefore, it is advisable that the reference capacitor Cr can include a variable capacitor. Moreover, the capacitance value of the reference capacitor Cr can be adjusted with respect to each product so as to become substantially equivalent to that of the electrostatic capacitance Cs. 
       FIG.  10    shows a circuit diagram of the reference capacitor Cr and the third driving unit  216  of the first embodiment. The reference capacitor Cr includes multiple (four in this example) capacitive elements Ce 1  to Ce 4 . The multiple capacitive elements Ce 1  to Ce 4  are commonly connected on the same side of the first terminal e 1 . 
     The third driving unit  216  includes individual driving parts DU 1 , DU 2 , DU 3  and DU 4  respectively corresponding to the multiple capacitive elements Ce 1 , Ce 2 , Ce 3 , and Ce 4 . By applying the case of having some of the driving parts DU 1 , DU 2 , DU 3 , and/or DU 4  being in use while some remaining are not in use, the capacitance of the reference capacitor Cr can be switched. In the driving part DU that is not used, both of the high-side switch and the low-side switch are set as off. 
       FIG.  11 A  and  FIG.  11 B  show diagrams of a layout of the capacitance detection circuit  200 . The reference capacitor Cr is formed by a metal-insulator-metal (MIM) capacitor. In the layout of  FIG.  11 A , the reference capacitor Cr is formed in a passive region  402  different from the active region  400  formed with transistors. 
     In  FIG.  11 B , a portion or all of the reference capacitor Cr is configured to be overlapping with the active area  400  formed with transistors. With the configuration of  FIG.  10   , the following issues can be caused if the layout of  FIG.  11 B  is used. When there is/are capacitive element Ce not in use, high impedance may occur at the side of the second terminal e 2 . Thus, the capacitive element Ce acts as a parasitic capacitance and is coupled to circuits in the active area. The coupling leads to problems such as increased noise and degraded precision for the electrostatic capacitance detection. 
       FIG.  12 A  shows a circuit diagram of the reference capacitor Cr and the third driving unit  216  of the second embodiment. The reference capacitor Cr includes multiple capacitive elements Ce 1 , Ce 2 , Ce 3 , and Ce 4 , and switches SWe 1 , SWe 2 , SWe 3  and SWe 4  inserted to the side of the first terminals e 1  of the multiple capacitive elements Ce 1 , Ce 2 , Ce 3 , and Ce 4 . The configuration of the third driving unit  216  is the same as that in  FIG.  10   . 
     By adding the switches SWe 1 , SWe 2 , SWe 3  SWe 4 , coupling between the capacitive element Ce that is not in use and circuits in the active area can be disconnected by the switch SWe. The capacitive element Ce that is not in use can be fixed at the high voltage or the low voltage at the side of the second terminal e 2  by the driving part DU in advance. As a result, as shown in  FIG.  11 B , with an overlapping configuration of the MIM capacitor and the active area, surrounding environmental noise can be reduced, and degradation of detection precision can be alleviated. Thereby, the chip area can be reduced. 
       FIG.  12 B  shows a circuit diagram of the reference capacitor Cr and the third driving unit  216  of a third embodiment. The reference capacitor Cr includes multiple capacitive elements Ce 1 , Ce 2 , Ce 3 , and Ce 4 , and switches SWe 1 , SWe 2 , SWe 3  and SWe 4  inserted to the side of the first terminal e 1  of the multiple capacitive elements Ce 1 , Ce 2 , Ce 3 , and Ce 4 . The third driving unit  216  is not divided into individual components corresponding to the individual capacitive elements Ce 1 , Ce 2 , Ce 3 , and Ce 4 , but is configured as one component to collectively connect thereto. 
     In the embodiments, a situation where a post-stage circuit block of the C/V conversion circuit  210  being an ADC is given as an example; however, the present disclosure is not limited thereto.  FIG.  13    shows a circuit diagram of a capacitance detection circuit  200 A of an alternative embodiment. In this alternative embodiment, the post-stage circuit block of the C/V conversion circuit  210  includes an integrator  240  and an ADC  220 . An output signal of the C/V conversion circuit  210  is accumulated by the integrator  240  and hence amplified, and then converted to a digital value by the ADC  220 .