Patent Publication Number: US-10763785-B2

Title: Fast startup time for crystal oscillator

Description:
CROSS-REFERENCE APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 15/853,942, filed on Dec. 25, 2017, entitled “CIRCUIT AND METHOD FOR FACILITATING STARTUP TIME OF CRYSTAL OSCILLATOR,” the disclosure of which is hereby incorporated by reference in its entirety for all purposes. 
    
    
     TECHNICAL FIELD 
     The embodiments herein generally relate to facilitating a startup of a crystal oscillator in a circuit. 
     BACKGROUND 
     Various types of oscillators are commonly used to provide a reference signal for use within electronic circuits. Their piezoelectric properties allow them to be a frequency—determining element in electronic circuits. A crystal oscillator, particularly one made of quartz crystal, works by being distorted by an electric field when voltage is applied to an electrode near or on the crystal. This property is known as electrostriction or inverse piezoelectricity. When the field is removed, the quartz—which oscillates in a precise frequency—generates an electric field as it returns to its previous shape, and this can generate a voltage. 
     Typically, a crystal oscillation circuit includes a crystal oscillator, an inverter coupled in parallel with the crystal oscillator, and capacitors coupled to the input and output of the inverter and to ground. To conserve power, the crystal oscillation circuit includes an enable/disable mechanism. The crystal oscillator can be started by injecting energy composed of noise and/or transient power supply response. The startup time of a crystal oscillator is typically determined by the noise or transient conditions at turn-on; small-signal envelope expansion due to negative resistance; and large-signal amplitude limiting. 
     It is known that crystal resistance is not constant, typically being higher at start-up than when oscillating in steady state. The crystal resistance is related to the Q factor of the oscillator, which dictates the amount of power applied to the crystal to keep it oscillating at the same amplitude. As the resistance decreases, the amount of power consumed decreases. The variation in the crystal resistance causes more power to be used at start-up than is desired to achieve the best noise performance in steady state operation. However, decreasing the power such that optimal noise performance is achieved in steady state increases the amount of time for the crystal 
     A common approach to startup the crystal oscillator is to inject high energy at the beginning, and then making the expansion even faster to reach the desired frequency. With this approach, a lot of energy is used to startup the crystal oscillator. Under this approach, the startup time for the crystal oscillator can be between 500-600 us for crystals that oscillate around 26 MHz. However, this approach does not work well in the context when power supply is limited. 
     Another common approach is to inject noise at the startup time into the oscillation of the crystal element. In general, certain amount of phase noise is preferred during the oscillation of the crystal element. Various techniques have been proposed to inject noises at the startup time of the crystal element. 
     SUMMARY 
     Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. Since individual crystal elements are different in terms of their physical characteristics such as capacitance, aging, etc., startup time for different crystal oscillators can be different. In some embodiments, a simple learning block can be placed in parallel to a crystal oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. 
     In some implementations, the learning block can comprise a counter, a buffer, a determinator, and/or any other component. The determinator can be configured to determine whether the crystal oscillator has reached the desired frequency (stabilize) for a given startup cycle. The counter can be configured to count the number of clock cycles taken for the crystal oscillator to reach the desired frequency and the buffer can be used to store a count indicating a counted number of clock cycles, which can be read by a disable mechanism for deactivating noise injection. 
     In some implementations, an adjustment block may be employed to adjust the count determined by the learning block based on one or more characteristics of the crystal oscillator during a startup of the crystal oscillator. The adjustment block can comprise an adjustment determinator, an adjuster, and/or any other components. The adjustment determinator can be configured to determine an adjustment for the clock cycles to stabilize the crystal element  102 . The adjuster can be configured to adjust the count based on the adjustment determined by the adjustment determinator. 
     In some embodiments, a simple block that creates a negative capacitance (Cneg) can be configured in parallel to the crystal oscillator. The Cneg may be a float negative resistance and can be used to cancel the shunt resistance of the crystal oscillator. In those embodiments, the Cneg circuit may be only used during the startup time for the crystal oscillator such that the Cneg circuit is disconnect once the crystal oscillator stabilizes to avoid frequency shifting. In some implementations, the Cneg circuit can be configured to generate negative impedance comprising a combination of negative resistance and capacitance to cancel the impedance of the crystal element. 
     Other objects and advantages of the invention will be apparent to those skilled in the art based on the following drawings and detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an example oscillator circuit in accordance with the disclosure. 
         FIG. 2A  illustrates a learning block that can be connected to the example oscillator circuit shown in  FIG. 1 . 
         FIG. 2B  illustrates one example of a learning block shown in  FIG. 2A . 
         FIG. 3A  illustrates an adjustment block that can be connected with the oscillation circuit shown in  FIG. 1  and the learning block shown in  FIG. 2A . 
         FIG. 3B  illustrates one example of the adjustment block shown in  FIG. 3A . 
         FIG. 4  illustrates an example of a circuit that can generate negative resistance and/or negative impedance to cancel Cshunt capacitance and/or impedence for the oscillator circuit shown in  FIG. 1 . 
         FIG. 5  illustrates an exemplary method for controlling a startup for an oscillator circuit in accordance with the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, various embodiments will be described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the embodiments. However, it will also be apparent to one skilled in the art that the embodiments may be practiced without the specific details. Furthermore, well-known features may be omitted or simplified in order not to obscure the embodiments being described. 
     A crystal oscillator is typically formed in an oscillator circuit  100  such as the one illustrated in  FIG. 1 . As shown, the oscillator circuit  100  can comprise a crystal element  102 , a CMOS inverter  104 , a stabilizing capacitor  106 , another stabilizing capacitor  108 , a transistor  114  and/or any other components. In this example, the crystal element  102  is connected in parallel to the high gain CMOS inverter  104 . Stabilizing capacitors  106  and  108  are connected to ground and respectively to the input  110  and the output  112  of the inverter  104 . In operation, when the circuit supply voltage Vcc is turned on, the transistor  114  will be on, generating a voltage Vout at the inverter output  112 . Vout then charges up the capacitor  108  and develops a voltage at the crystal element  102 , causing it to begin oscillating at a low amplitude. This generates a voltage Vin at the input  110  of the inverter and charges capacitor  106 . The increasing voltage Vin slowly causes the inverter  104  to move to its high gain region, thereby allowing the amplitude of the oscillations of the crystal element  102  to increase. The noise generator  116  can be configured to generate a certain amount of noises and inject the noises into the oscillation of the crystal element  102  during the startup. 
       FIG. 2A  illustrates a learning block  200  can be connected to the oscillator circuit  100 . The learning block  200  can be used to count a number of clock cycles for the crystal element  102  to stabilize during a given startup. This count can then be used to control noise injection for the crystal element  102  during a next startup after the given startup. One insight provided by the inventor(s) is that every crystal element  102  can have a unique set of physical characteristics such as capacitance, aging, temperature and etc. These characteristics may affect the startup time for the crystal element  102 . That is, different crystal element  102  can have different startup time to stabilize. Traditionally, noise injection for the crystal element  102  during the startup time is controlled according to a worse case among a number of crystal elements. For example, a manufacturer may measure startup time for different crystal oscillators manufactured by the manufacturer in a lab. The noise injection to the oscillator circuit  100  is then controlled according to the longest measured startup time for those crystal oscillators. Although, in some cases, startup time variations among different crystal oscillators may not be very significant, this can still lead to inefficiency since some crystal oscillators do not take the longest measured startup time to stabilize. 
     As an improvement, the learning block  200  can be placed in parallel to the oscillator circuit  100  for controlling the noise injection by the noise generator  202  on a per-chip basis. As shown, the learning block  200  can be configured to receive a signal from the oscillator circuit  100  as an input. The received signal can include information indicating a level of oscillation the crystal element  102  is currently having. Based on such a signal, the learning block  200  can determine whether the crystal element  102  has reached a predetermined oscillation level (e.g., stabilized). For example, when the received signal indicates that crystal element is just being started, the learning block  200  may be configured to reset the count to 0, and to start incrementing an internal counter. When the received signal indicates that the oscillation level of the crystal element  102  has reached the predetermined oscillation level, the learning block  200  can be configured to stop the counter and to store the counted number of clock cycles for this startup in a buffer. This count can be used by the oscillation circuit  100  to control the noise injection for the next startup(s) of the crystal element  102 . 
       FIG. 2B  illustrates one example of a learning block  200  in accordance with the disclosure. As shown, the learning block  200  can comprise a determinator  206 , a counter  208 , a buffer  210 , and/or any other components. The determinator  204  can be configured to receive a signal from the oscillator circuit  100 . As mentioned above, this signal can indicate a current oscillation level of the crystal element  102 . The determinator  206  can be configured to read a predetermined oscillation level for the crystal element  102 , for example from the buffer  210 . The determinator  206  can be configured to compare the current oscillation level of the crystal element  102  and the predetermined oscillation level to determine whether crystal element  102  has reached the predetermined oscillation level. The determinator  206  can be configured to generate an instruction to have the counter  208  to reset a count to 0 and start incrementing the count (in clock cycles) when the received signal indicates the current oscillation level of the crystal element  102  is 0 or slightly above 0. The determinator  206  can be configured to generate an instruction to have the count stop counting the clock cycles when it is determined that crystal element  102  has reached the predetermined oscillation level. 
     The counter  208  can be configured to start and stop counting clock cycle by clock cycle based on the above-described instructions from the determinator  206 . Once stopped, the counter  208  can be configured to store the counted number of clock cycles in the buffer  210 . As shown, the buffer  210  can be connected to a disable mechanism  204 , which in some examples may comprise a tristate buffer. The disable mechanism  204  can be configured to control the deactivation of the noise injection by the noise generator  202 . For example, as illustration, if the count is 200 clock cycles as determined by the determinator  206 , the disable mechanism  204  can be configured to read this count and deactivate the noise injection by the noise generator  202  after the 200 clock cycles have reached during the current startup of the crystal element  102 . 
     In some implementations, the determinator  206  can be configured to account for a lead time that may be needed for disabling noise injection by the disable mechanism  204 . For example, as illustration, the determinator  206  may determine that it takes 150 clock cycles for the crystal element  102  to stabilize during the current startup for the crystal element  102 . The determinator  206  may be configured with a lead time factor (e.g., 5 clock cycles) such that the counted number of clock cycles for the crystal element  102  to stabilize is reduced based on the lead time factor (e.g., 150−5=145 clock cycles) when stored in the buffer  210 . In this way, when the disable mechanism  204  reads the count stored in the buffer  210 , the stored count is already adjusted according to the lead time factor. 
     In some implementations, an adjustment block  300  may be employed to adjust the count read from the buffer  210  by the disable mechanism  204 . As mentioned above, the count stored in the buffer  210  can indicate a counted number of clock cycles for crystal element  102  to stabilize during a previous startup from the disable mechanism  204 &#39;s point of view. This count is then used by the disable mechanism  204  to control the deactivation of the noise injection during the current startup of the crystal element  102 . In those implementations, the adjustment block  300  can be used to adjust (e.g., fine-tune) the count based on certain factor(s) such as temperature, aging, etc., that may affect the duration for the crystal element  102  to stabilize between different startups. 
       FIG. 3A  illustrates one example of an adjustment block  300  that can be connected with the oscillation circuit  100  and the learning block  200 . The adjustment block  300  can be configured to read the count from learning block  200 . The adjustment block  300  can be configured to receive a signal from the oscillation circuit  100 , such as a signal indicating a temperature of the crystal element  102 . The adjustment block  300  can be configured to determine an adjustment for the count based on the signal received from the oscillation circuit  100  and to obtain an adjusted count. The adjusted count can be stored in the buffer  210  of the learning block  200  for use in a next startup. The adjusted count can be sent to the disable mechanism  204  for control the deactivation of the noise injection for the current startup. 
       FIG. 3B  illustrates one example of adjustment block  300  in accordance with the disclosure. As shown, the adjustment block  300  can comprise an adjustment determinator  302 , an adjuster  304 , and/or any other components. The adjustment determinator  302  can be configured to receive a signal from the learning block  200 . The signal can indicate a characteristic about the crystal element  102  such as its temperature at the current startup. The adjustment determinator  302  can be configured to determine an adjustment for the clock cycles to stabilize the crystal element  102 . For example, the adjustment determinator  302  can be configured to determine a 5 clock cycle adjustment is needed for the current startup based on a temperature of the crystal element  102  measured during the current startup. This adjustment can account for factors that may affect the stabilizing duration for the crystal element  102  during the current startup. In some implementations, the adjustment determinator  302  can be configured to store historical characteristics of the crystal element  102 , such as its temperature over time. In those implementations, the adjustment determinator  302  can compare the stored historical characteristics and determine the adjustment to the count based on the comparison. 
     The adjuster  304  can be configured to read the count stored in the buffer  210  and adjust the count based on the adjustment determined by the adjustment determinator  302 . For example, as illustration, the adjustment determinator  302  may determine the adjustment for the count is −5 clock cycles based on the measured temperature of the crystal element  102 ; and the count is 120 clock cycles. In that case, the adjustment determinator  302  may adjust the count to 115 clock cycles. As also shown, the adjusted count can be fetched to the disable mechanism  204  for controlling the deactivation of the noise injection. The adjusted count can also be stored in the buffer  210  for next use in some implementations. 
       FIG. 4  illustrates a simple block  400  showing the crystal element  102  may be connected in parallel to a Cneg circuit  406  in some embodiments. As shown, the crystal element  102  can be modeled as Cshunt  402  and motional arm  404 . Cshunt capacitance is the passive resistance that can affect the startup time of the crystal element  102 ; and is a main factor for reducing the negative resistance from the oscillator core. The Cneg circuit  406  can be configured to generate a negative capacitance to cancel the Cshunt capacitance of the crystal element  102 . In those implementations, the negative capacitance generated by the Cneg circuit  406  may be a float negative resistance around 4 pF. In some embodiments, the Cneg circuit  402  may be only used during the startup time for the crystal oscillator such that the Cneg circuit  402  is disconnected once the crystal oscillator stabilizes to avoid frequency shifting. In some implementations, the Cneg circuit  402  can be configured to generate negative impedance comprising a combination of negative resistance and capacitance to cancel the impedance of the crystal element  102 . 
     Attention is now is directed to  FIG. 5  where an exemplary method  500  for controlling a startup for an oscillator circuit in accordance with the disclosure. The particular series of processing steps depicted in  FIG. 5  is not intended to be limiting. It is appreciated that the processing steps may be performed in an order different from that depicted in  FIG. 5  and that not all the steps depicted in  FIG. 5  need be performed. In certain implementations, the method  500  may be implemented by a video processing center, such as the video processing center shown in  FIG. 5 . 
     In some embodiments, the method depicted in method  500  may be implemented in one or more processing devices (e.g., a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and/or other mechanisms for electronically processing information). The one or more processing devices may include one or more devices executing some or all of the operations of method  500  in response to instructions stored electronically on an electronic storage medium. The one or more processing devices may include one or more devices configured through hardware, firmware, and/or software to be specifically designed for execution of one or more of the operations of method  500 . 
     At  502 , a signal can be received from an oscillation circuit. The signal can indicate an oscillation level of a crystal element of the oscillation circuit. In some implementations, operations involved in  502  can be implemented by a learning block the same as or substantially similar to the learning block  200  described and illustrated herein. 
     At  504 , it can be determined from the signal received at  502  whether a current oscillation level of the crystal element is 0 or slightly above 0. When it is determined that the current oscillation level of the crystal element is 0 or slightly above 0, a count can be started. In some implementations, operations involved in  504  can be implemented by a learning block the same as or substantially similar to the learning block  200  described and illustrated herein. 
     At  506 , it can be determined from the signal received at  502  whether the current oscillation level of the crystal element determined at  504  has reached a target oscillation level. When it is determined that the current oscillation level of the crystal element has reached the target oscillation level, the count can be stopped and the value of the count can be stored in a bu. In some implementations, operations involved in  506  can be implemented by a learning block the same as or substantially similar to the learning block  200  described and illustrated herein. 
     At  506 , the count stored in the buffer can be fetched to a disable mechanism for controlling deactivation of noise injection to the oscillation circuit. In some implementations, operations involved in  504  can be implemented by a learning block the same as or substantially similar to the learning block  200  described and illustrated herein. 
     The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the disclosure as set forth in the claims. 
     Other variations are within the spirit of the present disclosure. Thus, while the disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are illustrated in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure, as defined in the appended claims. 
     The use of the terms “a” and “an” and “the” and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. The term “connected” is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure. 
     Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is intended to be understood within the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present. 
     Various embodiments of this disclosure are described herein, including the best mode known to the inventors for carrying out the disclosure. Variations of those embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate and the inventors intend for the disclosure to be practiced otherwise than as specifically described herein. Accordingly, this disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the disclosure unless otherwise indicated herein or otherwise clearly contradicted by context.