Patent Publication Number: US-2004047224-A1

Title: Memory architecture with vertical and horizontal row decoding

Description:
BACKGROUND OF THE INVENTION  
       [0001] In the stand-alone and embedded semiconductor memory areas, as the memory density increases, the silicon area consumed by the memory needs to be reduced in order to remain cost-effective. Memory cell size is continuously being reduced to achieve such silicon area reduction. If the continued efforts in reducing the cell size is not accompanied with similar efforts in reducing the size of those periphery circuits which interface with the memory array, the silicon area consumed by the periphery circuit becomes the bottleneck in achieving smaller silicon area.  
       [0002] Row decoder circuit is one of the circuit blocks which interfaces with the memory array. Conventionally, the wordline (row) path of a memory includes address buffers driving row predecoding circuits which in turn drive the row decoder. The address buffer and row predecoding circuits are generally located in the periphery area of a memory and do not physically interface with the memory array. However, the row decoder usually extends along one side or through the center of the memory array. With a reduction in the cell size, the memory cell pitch within which the row decoder needs to be formed is equally reduced. Thus, to achieve an effective overall area reduction, the row decoder needs to be reduced in size.  
       [0003] Conventional row decoders include multi-decoding stages. In, for example, a three-stage row decoding scheme, a first decoding stage receives a first group of predecoded row address signals and in response selects a group of the decode logic in the second decoding stage. The second decoding stage, in addition to the signal(s) from the first decoding stage, receives a second set of predecoded row address signals and in response selects one of a group of wordline drivers which form the third decoding stage. This third decoding stage, in addition to the signal(s) from the second decoding stage, may receive a third set of predecoded row address signals and in response selects a wordline in one or more memory arrays.  
       [0004] Many row decoding schemes for minimizing the size of the row decoder, for example by reducing the number of transistors in one or more of the three decoding stages of the row decoder, have been proposed and used. Although such reduction in the number of transistors results in a smaller row decoder, no technique has been proposed which yields a substantial reduction in the silicon are consumed by the row decoder.  
       [0005] Thus, there is a need for a circuit technique and array configuration which yield a significant reduction in the silicon area consumed by the row decoder.  
       BRIEF SUMMARY OF THE INVENTION  
       [0006] In accordance with an embodiment of the present invention, a semiconductor memory includes a memory array having a plurality of rows and columns of sectors, a horizontal global row decoder, a vertical global row decoder, and a plurality of horizontal local row decoders. Each of the sectors has a plurality of rows and columns of memory cells. The horizontal global row decoder is configured to select one of the rows of sectors in response to a first set of row address signals. The vertical global row decoder is configured to select one or two adjacent columns of the columns of sectors in response to a second set of row address signals. The plurality of horizontal local row decoders are coupled to the vertical global row decoder and the horizontal global row decoder to select one or two adjacent sectors located at the intersection of the selected row of sectors and the selected one or two adjacent columns of sectors.  
       [0007] In another embodiment, the semiconductor memory also includes a plurality of vertical local row decoders coupled to the plurality of horizontal local row decoders to select a row of memory cells in the selected one or two adjacent sectors in response to a third plurality of row address signals.  
       [0008] In accordance with another embodiment of the present invention, a semiconductor memory includes a memory array having a plurality of sectors each having a plurality of rows and columns of memory cells, a horizontal global row decoder, a vertical global row decoder, and a plurality of horizontal local row decoders. The horizontal global row decoder is configured to provide a first plurality of predecoded row address signals on a first plurality of lines extending across the memory array in a direction parallel to the rows of memory cells. The vertical global row decoder is configured to provide a second plurality of predecoded row address signals on a second plurality of lines extending across the memory array in a direction parallel to the columns of memory cells. The plurality of horizontal local row decoders are configured so that one of the plurality of horizontal local row decoders selects one or both of two sectors located adjacent to the one of the plurality of horizontal local row decoders in response to a unique combination of the first and second plurality of predecoded row address signals.  
       [0009] In another embodiment, the semiconductor memory further includes a plurality of vertical local row decoders configured to provide a third plurality of predecoded row address signals on a third plurality of lines extending across the memory array in a direction parallel to the columns of memory cells. The one of the plurality of horizontal local row decoders selecting one or both of two sectors located adjacent to the one of the plurality of horizontal local row decoders further selects a row of memory cells in the selected one or both of two sectors in response to the third plurality of predecoded row address signals.  
       [0010] In another embodiment, the vertical local row decoders are located along at least one side of the memory array, the vertical local row decoders being equal in number to the plurality of columns of horizontal local row decoders.  
       [0011] In another embodiment, each of the plurality of horizontal local row decoders includes a logic gate coupled to a decode circuit. The logic gate is configured to provide an output signal in response to a subset of the first plurality of signals and a subset of the second plurality of signals. The decode circuit is configured to provide a plurality of output signals in response to the output signal of the logic gate and the third plurality of predecoded row address signals.  
       [0012] In another embodiment, of the plurality of rows and columns of sectors, the logic gate in the one of the plurality of horizontal local row decoders operates to select the one or both of two sectors located adjacent to the one of the plurality of horizontal local row decoders in response to a preselected subset of each of the first and second plurality of predecoded row address signals. The decode circuit in the one of the plurality of horizontal local row decoders operates to select one of the rows of memory cells in the selected one or both of two sectors in response to the output signal of the logic gate and the third plurality of predecoded row address signals.  
       [0013] In another embodiment, the plurality of sectors are arranged along rows and columns, and the plurality of horizontal local row decoders are arranged along a plurality of rows and columns. Each column of the horizontal local row decoders separates two columns of sectors.  
       [0014] The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.  
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0015]FIG. 1 is a simplified block diagram of a non-volatile semiconductor memory  100  illustrating a memory architecture and row decoding technique in accordance with an embodiment of the present invention;  
     [0016]FIG. 2 shows a row of sectors and the corresponding row decode blocks in accordance with another embodiment of the present invention; and  
     [0017]FIG. 3 shows one circuit implementation of the horizontal local row decoder. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0018]FIG. 1 is a simplified block diagram of a 32 Mb semiconductor memory  100  illustrating a memory architecture and row decoding technique in accordance with an embodiment of the present invention. The 32 Mb density is only illustrative and not intended to be limiting. The memory architecture and row decoding technique shown in FIG. 1 can be modified by one skilled in this art to implement any density and type of memory in view of the present disclosure.  
     [0019] Memory  100  includes a memory array having  64  memory sectors  102 -i of 512 rows by 1024 columns of cells each (64 Kb per sector). The sectors are arranged along eight rows and eight columns. A horizontal global row decoder  104  is shown along the left side of the memory array. This row decoder receives two sets of row addresses A&lt;14:12&gt; and A&lt;17:15&gt;, and provides predecoded row address signals on eight groups of global lines  105 -i extending horizontally across the memory array. Each group of global lines  105 -i includes eight lines. Addresses A&lt;17:15&gt; are decoded to select one of the eight groups of global lines  105 -i, and addresses A&lt;14:12&gt; are decoded to select one of the eight signal lines in the selected group of global lines. Although horizontal global row decoder  104  is shown as directly receiving addresses A&lt;17:12&gt;, these addresses may be predecoded via predecode circuits and then the predecoded signals be provided to horizontal global row decoder  104 .  
     [0020] A vertical global row decoder  106  is shown extending along the top of the memory array. This row decoder receives two sets of row addresses A&lt;11:9&gt; and A&lt;20:18&gt; and provides predecoded row address signals on eight groups of global lines  107 -i extending vertically across the memory array. Addresses A&lt;20:18&gt; are decoded to select one of the eight groups of global lines  107 -i, and addresses A&lt;11:9&gt; are decoded to select one of the eight signal lines in the selected group of global lines. Although vertical global row decoder  106  is shown as directly receiving addresses A&lt;11:9&gt; and A&lt;20: 18&gt;, these addresses may be predecoded via predecode circuits and then the predecoded signals are provided to vertical global row decoder  106 .  
     [0021] Eight vertical local row decoders  108 -i are shown between vertical global row decoder  106  and the array. Each vertical local row decoder  108 -i receives row addresses A&lt;8:6&gt;, and decodes these addresses to select one of the eight signal lines  110 -i extending vertically across the memory array.  
     [0022] Eight horizontal local row decoders  112 -i are shown between every two adjacent columns of sectors. As shown, each of eight groups of signal lines  110 -i driven by vertical local row decoders  108 -i is paired with a corresponding one of eight groups of lines  107 -i driven by vertical global row decoder  106 , each pair extending through one of the eight columns of horizontal local row decoders  112 -i. Each of the eight groups of signal lines  105 -i driven by horizontal global row decoder  104  extends horizontally over a corresponding one of the eight rows of sectors and horizontal local row decoders.  
     [0023] The horizontally-extending groups of signal lines  105 -i and the vertically extending groups of signal lines  107 -i form a grid. Each horizontal local row decoder  112 -i includes a first decode circuit (not shown in FIG. 1) which receives a unique combination of signal lines  105 -i and  107 -i to select a corresponding sector for a read, write or erase operation. Each horizontal local row decoder  112 -i further includes a second decode circuit (not shown in FIG. 1) which receives signal lines  110 -i and an output signal of the first decode circuit, and in response selects a row of memory cells in the selected sector.  
     [0024] Although horizontal global row decoder  104  is shown along the left side of the memory array, it may also be placed along the right side of the array. Alternatively, it may be placed along both left and right sides of the array. This may be desirable for high-speed applications where the area penalty due to two horizontal global row decoders is not a concern. In another embodiment, horizontal global row decoder  104  is placed along the center of the memory array, thus dividing array to a right-half array and a left-half array.  
     [0025] Similarly, vertical global row decoder  106  may be located along the bottom side of the array rather than top as shown in FIG. 1. Alternatively, vertical global row decoder  106  may be placed along both top and bottom sides of the array. In another embodiment, vertical global row decoder  106  is placed along the center of the memory array, thus dividing the array to an upper-half array and a lower-half array. These possible variations for the location of vertical global row decoder  106  also apply to vertical local row decoders  108 -i.  
     [0026] As can be seen, many combinations of locations are possible for the vertical and horizontal global row decoders and the vertical local row decoders. Depending on the design targets, modifying the configuration of these blocks from that shown in FIG. 1 would be obvious to one skilled in this art in view of this disclosure.  
     [0027] The cross-hatched sector  102 -i and a corresponding wordline in sector  102 -i are selected as follows. In response to row addresses A&lt;17:12&gt;, horizontal global row decoder  104  selects signal line group  105 -i from the eight groups of signal lines, as well as one of the eight signal lines in the selected signal line group  105 -i. In response to row addresses A&lt;20:18&gt; and A&lt;11:9&gt;, vertical global row decoder  106  selects signal line group  107 -i from the eight groups of signal lines, as well as one of the eight signal lines in the selected signal line group  107 -i. The first decode circuit (not shown) in horizontal local row decoder  112 -i receives the selected one of the eight signal lines in each of signal line groups  105 -i and  107 -i, and in response selects one of a number of groups of decoded wordline drivers (not shown) in horizontal local wordline driver  102 -i. Each of the groups of the decoded wordline drivers receives the eight predecoded signals  110 -i generated by vertical local wordline driver  108 -i. In response to row addresses A&lt;8:6&gt;, vertical local wordline decoder  108 -i selects one of the eight predecoded signals  110 -i. In response to the selected one of predecoded signals  110 -i, the decoded wordline drivers in horizontal local driver  112 -i select one wordline in sector  102 -i.  
     [0028] Column decoder  114  along the bottom of the array selects one or more column(s) from the selected sector  102 -i in response to column addresses (not shown) in accordance with conventional methods. Accordingly, the cell(s) located at the intersection of the selected row and column(s) in sector  112 -i is accessed for read, program, or erase operations. More than one sector may be selected in a given operation depending on the design goals.  
     [0029] Using a multi-layer metal process, in one embodiment, a first layer metal is used for the vertically-extending bitlines, a second layer metal is used for portions of the eight groups of lines  105 -i extending over the horizontal local row decoders  112 -i, and a third layer metal is used for each of: (i) the portions of the eight groups of signal lines  105 -i extending over the sectors, (ii) the eight groups of signal lines  107 -i extending through the columns of horizontal local row decoders  112 -i, and (iii) the eight groups of signal lines  110 -i generated by the local vertical row decoders  108 -i. In another embodiment, the use of the second and third layers metal is reversed.  
     [0030]FIG. 2 shows one row of sectors and the corresponding row decode blocks in accordance with another embodiment of the present invention. As shown, two columns of horizontal local row decoders  212 -i are included for every four adjacent columns of sectors (FIG. 1 shows one column of horizontal local row decoders  112 -i for each column of sectors). Each horizontal local row decoder  212 -i includes a first decoder portion  212 -i 1  and two decoded wordline driver portions  212 -i 2 , and  212 -i 3 . First decoder portion  212 -i 1  decodes the signal lines from vertical global row decoder  206 -i to select one of a group of decoded word-line drivers (not shown) in each of wordline driver portions  212 -i 2  and  212 -i 3 . The selected group of wordline drivers in each of wordline driver portions  212 -i 2  and  212 -i 3  then deocdes the signal lines from corresponding vertical local row decoders  208 -i 1  and  208 -i 2  to select a wordline from corresponding array sectors  202 -i 1  and  202 -i 2 .  
     [0031] In one embodiment, decoded wordline driver portion  212 -i 2  drives the wordlines in sector  202 -i 1 , and decoded wordline driver portion  212 -i 3  drives wordlines in sector  202 -i 2 . Alternatively, each wordline driver portion  212 -i 2  and  212 -i 3  drives wordlines in both sectors  202 -i 1  and  202 -i 2 , as shown in FIG. 3.  
     [0032]FIG. 3 shows one circuit implementation of the horizontal local row decoder  212 -i in FIG. 2. One horizontal local row decoder  312 -i and its two adjacent sectors  302 -i 1  and  302 -i 2  are shown. A first decode portion  312 -i 1  of each horizontal local row decoder  312 -i includes one logic gate  316 -i for every four wordlines (each sector  302 -i 1 ,  302 -i 2  has 512 wordlines). These logic gates receive vertically-extending signal lines  307 -i generated by vertical global row decoder  306 -i and horizontally-extending signal lines  305 -i generated by the horizontal global row decoder (not shown). Logic gates  316 -i perform decode function on the signals they receive. A two-input NAND gate is shown for logic gate  316 -i. A four-transistor CMOS NAND implementation may be used for logic gate  316 -i, however, other logic gates and transistor implementations may be used as would be obvious to one skilled in the art.  
     [0033] Each of decoded wordline driver portions  312 -i 2 ,  312 -i 3  includes one decoded wordline driver  317 -i per wordline. Wordline driver  317 -i drives one wordline (e.g., WL&lt;0&gt;) in each of sectors  302 -i 1 ,  302 -i 2 . The wordline drivers are arranged in groups of four, with two groups of four wordline drivers (e.g., groups  318 -i 1  and  318 -i 2 ) having a common input terminal coupled to an output terminal of one logic gate  316 -i.  
     [0034] Decoded wordline driver portions  312 -i 2 ,  312 -i 3  receive vertically-extending signal lines  310 -i 1 ,  310 -i 2  generated by vertical local row decoders  308 -i 1 ,  308 -i 2 . Signal lines  310 -i 1 ,  310 -i 2  carry true and complement of each signal generated by the corresponding vertical local row decoder  308 -i 1 ,  308 -i 2 . Each wordline driver  317 -i performs a decode function on the output signal received from the corresponding logic gate  316 -i and the set of true and complement signals received from the corresponding vertical local row decoder  308 -i 1 ,  308 -i 2 . Wordline driver  317 -i is a three-transistor NOR gate, however, other logic gates and transistor implementations may be used as would be obvious to one skilled in the art.  
     [0035] As shown, logic gate  316 -i is coupled between supply voltage VPX and ground potential. Supply voltage VPX represents a multiplexed supply line which is biased to the supply voltage VCC (e.g., 1.8V supply or 3V supply) or to a boosted voltage (e.g., to 3V from a 1.8V supply, or to 5V from a 3V supply) during read operation, and to supply voltage VPP (e.g., +9V) during programming operation. VPP is generally greater than VCC, since higher array voltages are required during programming.  
     [0036] Each wordline driver  317 -i includes a decoded-supply CMOS inverter along with a decoded NMOS transistor. The decoded-supply CMOS inverter is coupled between one of predecoded signals  310 -i 1 ,  31   0 -i 2  and supply voltage VNNX. Supply voltage VNNX represents a multiplexed supply line which can be biased to provide the necessary supply voltage during each of read, programming, and erase operations. The input terminal of the CMOS inverter is coupled to an output terminal of a corresponding logic gate  316 -i, and the output terminal of the inverter is coupled to a wordline in each of sectors  302 -i 1  and  302 -i 2 . The decoded NMOS transistor of each wordline driver is coupled between the corresponding wordline and the supply voltage VNNX, and receives at its gate the complement of the same decode signal coupled to the supply terminal of the CMOS inverter.  
     [0037] Supply voltages VPX and VNNX, or variations thereof, are commonly used in EPROMs, EEPROMs, and flash EPROMs/EEPROMs to supply the requisite voltages to the array. However, the row decoding technique, in accordance with the present invention, is not limited to any particular type of memory, and can be modified by one of skilled in this art, in view of this disclosure, to be included in other types of semiconductor memories such as DRAMs and SRAMs.  
     [0038] While the above is a complete description of the embodiments of the present invention, it is possible to use various alternatives, modifications and equivalents. For example, memory  100  (FIG. 1) may be a flash non-volatile memory, and during an erase operation one or more sectors are selected for simultaneous sector erase. Further, the circuit diagrams are for depiction of the various circuit elements and do not necessarily limit the layout or other architectural aspects of the array. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claim, along with their full scope of equivalents.