Patent Publication Number: US-9404951-B2

Title: Method of discrimination of a device as powerable through a LAN line and device for estimating electric parameters of a LAN line

Description:
FIELD OF THE INVENTION 
     This invention relates in general to “Power over Ethernet” techniques, and, more particularly, to a method of recognizing a device as powerable through a LAN line that is based on the assessment of certain electrical parameters of the LAN line, and to a related device for estimating these electrical parameters. 
     BACKGROUND OF THE INVENTION 
     Power over Ethernet (PoE) is a technology that permits the powering of appliances through the same cable that connects them to a LAN. In a PoE network there is essentially a Power Sourcing Equipment (PSE) that is capable of supplying a Powered Device (PD), that may be, for instance, a phone, a webcam, or any other device that is connectable to the LAN. The PSE supplies power to the PD devices connected to respective sockets through a dedicated pair of insulating wires of the connecting cable. In particular, the PSE verifies whether a PD is connected to a LAN line, and monitors the current delivered to the LAN line of the PD continuously. If the PD is disconnected, the PSEs stop the application of the DC supply voltage to the LAN line. 
     The standard specifications that rule this technique of powering devices contemplate the possibility for the PDs connected to the LAN of communicating to the PSE the power that should be supplied to them for a correct functioning. 
     In order to verify whether a valid PD is connected or not to an output port of the PSE, the PoE transmission standard that at present is the IEEE 802.3af, contemplates that any connectable PD be provided with a “signature element,” that may be a dedicated circuit with a certain impedance connected between the power supply terminals of the PD. When a new PD is connected to a respective point of the PSE, the PSE carries out an interrogation routine for reading the signature element. At the end of the interrogation routine, if validly identified, the newly connected PD is powered by the PSE. 
     The standard proposes that the PSE monitor the connection to a PoE supplied PD for verifying whether or not it has been disconnected, and when so, the PSE stops the provision of a supply voltage to the respective line of the LAN, in order to prevent application of a relatively large DC voltage to an open pair of insulated wires of the LAN line. 
     The procedures for recognizing a valid PD are normally carried out by measuring the resistance seen across the terminals through which the PSE supplies the LAN line, for example by applying a voltage across the pair of power supply conductors of the LAN line and measuring the current absorbed, or by forcing a current and sensing the voltage. 
     Unfortunately, by using these known recognition procedures, it happens sometimes that a valid PD may be incorrectly recognized as invalid, or vice versa. 
     SUMMARY OF THE INVENTION 
     Investigations carried out by the applicants have revealed that such erroneous recognitions may be due to the fact that it is simply not sufficient to measure the resistance of the power supply line at the PSE outlet for correctly identifying a valid PD, by evaluating two points of the voltage-current characteristic. Often, nonlinear elements may be connected to the line that may cause errors in the determination of the line resistance such to impede a correct identification of a PD as valid or not. 
     According to a first embodiment of the method of this disclosure, PDs that may be supplied through the LAN line are discriminated from PDs that may not be so supplied as a function of the resistance of the supply line and the voltage drop (Vdrop) caused by nonlinear elements in series therewith. The values of these two parameters are estimated by applying two distinct voltages to the supply terminals of the LAN line and sensing the relative steady-state currents absorbed by the power supply line, and by processing voltage and current values for estimating the resistance (Rdet) of the line and the voltage drop caused by nonlinear elements connected in series therewith. 
     According to an alternative embodiment of this disclosure, a third voltage is applied to the line and a third steady-state current absorbed by the line is sensed and from these voltage and current values an error term that represents the linearity of the voltage-current characteristic of the electric line is obtained. The result of the test for deciding whether the PD is powerable through the LAN line is made to depend also from this error term. 
     According to a further embodiment, the capacitance of the line is also estimated and a decision of whether or not the PD is powerable through the LAN line is also based upon the estimated capacitance value. 
     The disclosure further provides a device for estimating the above-mentioned electrical parameters of a LAN line, that are used according to the discrimination method of this disclosure for reliably recognizing PD that can be powered through the LAN line. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an embodiment of the device of this disclosure for estimating electrical parameters of a LAN line. 
         FIGS. 2 and 3  depict waveforms of the supply voltage of the LAN line and of the absorbed current for the device of  FIG. 1  according to an embodiment of a method of this disclosure, for a LAN line with a capacitance smaller than and larger than 1.5 μF, respectively. 
         FIG. 4  depicts waveforms of the current absorbed by the LAN line obtained by switching the supply voltage from 8V to 6V with the device of  FIG. 1 . 
         FIG. 5  depicts waveforms of the current absorbed by the LAN line and output waveforms of the comparator of the device of  FIG. 1  obtained by switching the supply voltage from 4V to 8V. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of a device for estimating values of electrical parameters of a supply line of a LAN network for implementing the method of this disclosure is depicted in  FIG. 1 . 
     A PD connected to a LAN line is recognized as powerable or not by a PSE, according to a PoE technique, by measuring the resistance Rdet seen from the supply terminals VLp, VLm of the LAN line. This is performed by driving the two supply conducting wires of the LAN line with a first voltage V 1 , and sensing a first steady-state current IL 1  absorbed by the supply line, then powering the line with a second voltage V 2 , and sensing a second steady-state current IL 2  absorbed by the line. Thus, the resistance Rdet seen from the terminals is estimated through the following formula: 
               R   ⁢           ⁢   det     =         V   ⁢           ⁢   1     -     V   ⁢           ⁢   2           IL   ⁢           ⁢   1     -     IL   ⁢           ⁢   2               
and the voltage drop Vdrop eventually due to nonlinear elements connected in series with the power supply line is given by one of the following equations:
 
 V drop= V 1 −Rdet*IL 1 or  V drop= V 2 −Rdet*IL 2.
 
     The calculated parameters Vdrop and Rdet are compared with pre-established reference intervals defined by specifications for establishing whether the connected PD is powerable through the LAN network or not. The specifications IEEE 803.af set a validity range for Rdet, but it would be desirable and is likely that, in the future, the specifications may set a validity range also for Vdrop, such to reduce the probability that the PSE is wrongly recognized as powerable to a PD that is non compliant with the specifications, or vice versa. At present, specifications set a threshold current that may be absorbed by the power supply lines of the LAN. 
     According to another embodiment of the method of this disclosure, the current that circulates in a LAN line, when the largest of the voltages V 1  and V 2  is applied, is compared with the threshold value. If this threshold value is exceeded, the PD is recognized as not compliant with the PoE specifications and may not be powered through the LAN line. 
     In order to make the discrimination between PD powerable and not powerable by the PSE more reliable according to another embodiment of the method of this disclosure, a third supply voltage V 3  is applied and the steady-state current IL 3  absorbed by the line is measured. An error term ε is estimated according to the following formula: 
     
       
         
           
             
               
                 IL 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 3 
               
               ± 
               ɛ 
             
             = 
             
               
                 
                   
                     V 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   - 
                   
                     V 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     drop 
                   
                 
                 
                   R 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   det 
                 
               
               . 
             
           
         
       
     
     Any skilled person will immediately notice that if the voltage-current characteristic of the supply line of a LAN line were linear, the error term ε would be null. In general, if the line has a nonlinear characteristic, thus this error term is nonnull. Therefore, its value indicates how much the voltage-current characteristic of the line is nonlinear. 
     This implies that the estimated value of the resistance Rdet may depend on the supply voltages used for carrying out the estimation. In practice, relatively large values of ε may mean that the value of Rdet calculated for a certain PD may fit in the specifications range because of the voltages that have been used for carrying out the estimation, and different voltages used for the assessment may result in obtainment of a value of Rdet not compliant with specifications. 
     Even if present specifications do not contemplate the evaluation of this error term for deciding whether a PD is powerable or not using the PoE technology, it is highly desirable and probable that the standard specifications will be updated for making the identification of PDs powerable with the PoE technique more reliable. 
     The device of  FIG. 1  provides to a control system of the power that may be supplied to a LAN line ( 2 ) and to a PD Host ( 1 ) connected thereto that may utilize more information than known systems provide during the so-called “detection phase”. More precisely, according to this embodiment, the device of  FIG. 1  provides the values of the resistance component of the line Rdet seen from the terminals VLp and VLm, and the voltage drop Vdrop due to nonlinear elements that may be connected to the line, such as, for example, rectifying diodes that are commonly included in PDs. 
     According to another and preferred embodiment, the device also provides an error term ε and/or the capacitance of a connected PD, that may be sensed over a wide range. 
     The system carries out these estimations of electrical parameters of the power supply line respecting the constraints of the international specifications IEEE 803.af (that set a threshold voltage Vmax=10V and a threshold current Imax=5 mA). 
     According to an alternative embodiment, during a “detection phase”, the LAN line is supplied at three different voltages over three consecutive steps. As shown in  FIGS. 2 and 3 , on the nodes VLp and VLm a first voltage of 4V is supplied for 50 ms, then a second voltage of 8V is supplied for 50 ms, and finally a third voltage, smaller than the second voltage but larger than the first voltage, of 6V is supplied for 50 ms, is applied. 
     Of course, these voltages may have different values provided they comply with the constraints of the standard specifications, that contemplate supply voltages of between 2.8V and 10V and voltage steps of at least 1V. 
     The voltage step switchings generate high frequency harmonics that may disturb the normal transmission of data over the LAN line. For this reason, the device of  FIG. 1  should preferably be provided with a circuit (not shown) that limits the slope of the switching edges to the different supply voltages. 
     The sequence of different supply voltages applied to the LAN line on which a detection routine is performed, is controlled by the digital block  9 , L OGIC  DSP &amp; C ONTROL , that acts on the block V OUT SET  by sequentially enabling constant current generators that produce on the resistor R 1  the desired voltages of 4V, 8V and 6V. In practice, the block V OUT SET  forms with the resistor R 1  a controlled voltage generator  8  of one of three pre-established supply voltages. 
     The node VI is connected to the non inverting input of the operational amplifier OA of the block  5 . The inverting input of the amplifier is connected to the terminal VLm, that is to the “low side” terminal of the line, for replicating the voltage VI on the node VLm. 
     The output of the operational amplifier controls the MOS M 1  that drives the current absorbed by the line. The block Ilim is a current limiter, that limits the current that may be absorbed by the line up to a pre-established threshold value, compatible with specifications. For example, such a current threshold may be fixed at 3 mA, that is compatible with specifications of the standard IEEE 803.af. 
     The “high” side VLp of the line is connected to the positive supply terminal Vbatt. The 20 μA current generator  4  establishes the working point of the system in case of an open line (absence of the PD H OST ). The block L OGIC  DSP &amp; C ONTROL  subtracts this current from the value of the current Il sensed by the block  6 . 
     The block  5  replicates on the node VLm the voltage on the node VI, thus it behaves as a voltage generator when the line current is below the maximum current Ilim. For larger currents, the circuit elements  5  act as a current generator of a current Ilim=3 mA. The current absorbed by the line is forced through the resistor R 2  by way of the transistor M 1  and the block Ilim. The voltage drop on the resistor R 2  is therefore proportional to the current absorbed by the line. 
     The circuit elements  6 , that is the sense resistor R 2  and the analog-to-digital converter A  TO  D C ONV , provide a digital signal representative of the current absorbed by the line to the processing block  9  L OGIC  DSP &amp; C ONTROL . The activation of the monitoring/measurement of the current by the converter is managed by the same block L OGIC  DSP &amp; C ONTROL.    
     Between the input terminal VI and the output terminal VLm, there is a comparator  7  that provides to the block L OGIC  DSP &amp; C ONTROL  a flag signal for discriminating when the block  5  is functioning as a voltage generator rather than as a current generator. When it functions as a voltage generator, the two nodes VI and VLm are practically at the same potential, and the output of the comparator presents a logically null flag  0 , while when it functions as a current generator the two nodes are at sensibly different potentials and the comparator outputs an active flag  1 . 
     The digital block L OGIC  DSP &amp; C ONTROL  that controls the state of the above described analog blocks, receives from them the information when activated, implements the assessment method, and produces on the output bus D ATA  O UT  at least the values of the resistance Rdet and of the voltage drop Vdrop accountable to nonlinear loads coupled to the power supply line of the LAN connection. 
     Preferably, it also produces on the output bus D ATA  O UT  information on the degree of nonlinearity of the supply line load and the value of the capacitance Cdet over a relatively wide variability range. This information may be stored and used by a controller of the powering of the LAN lines coupled to respective ports of the PSE. 
     The present standard IEEE 803.af sets discrimination resistance values of Rdet and of capacitance Cdet of PD:
         Rdet is valid if within the interval from 19 kΩ to 29.5 kΩ and invalid if smaller than 15 kΩ or larger than 33 kΩ;   Cdet is valid if smaller than 150 nF and invalid if larger than 10 μF. For intermediate capacitance values, other criteria are used to decide whether or not the PD should be supplied. However, there are PDs produced before the introduction of the standard specifications that can be supplied through a LAN line though having a Cdet value larger than the maximum value established by the standard.       

       FIGS. 2 and 3  are waveforms that illustrate the functioning of the device of  FIG. 1  with two different kinds of PDs: the PD used for obtaining the diagrams of  FIG. 2  is compatible with the IEEE specifications 802.3af, with Rdet=25 kΩ and Cdet=150 nF; the PD used for the diagrams of  FIG. 3  is a pre-standard device with Rdet=25 kΩ and Cd=5 μF. 
       FIG. 2  shows waveforms obtained with a standard compliant PD having a capacitance Cdet smaller than 1.5 μF. The system supplies the power supply line at a first voltage, for example 4V, determining a steady-state current absorption IL 4  that depends on the electrical characteristics of the connected PD. The current IL 4  flows through the sensing resistor R 2 , producing a voltage drop proportional to the current itself. 
     The analog-to-digital converter A  TO  D C ONV  converts the voltage on the sensing resistor into a digital signal and provides it to the control logic L OGIC  DSP &amp; C ONTROL , that digitally filters and stores it. 
     Preferably, the measure of the value of IL 4  starts with a delay of about 3 ms from the beginning of the voltage step for avoiding transient disturbances. 
     After 50 ms, that is a time interval long enough to allow the analog-to-digital converter to convert the steady-state current value, a second supply voltage of 8V is applied and the steady-state current level IL 8  is measured anew and stored. 
     From the applied voltages and the sensed steady-state current, the block L OGIC  DSP &amp; C ONTROL  determines and stores the resistance value Rdet of the line and the voltage drop Vdrop due to nonlinear load components that may be present. 
     According to a preferred embodiment, the control logic supplies the line at a third voltage of 6V and, similarly, stores the respective steady-state current value IL 6 . 
     As already described above, the control logic calculates an error term ε that gives an indication of the degree of nonlinearity of the voltage-current characteristic, according to the following equation: 
     
       
         
           
             
               
                 IL 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 6 
               
               ± 
               ɛ 
             
             = 
             
               
                 
                   
                     6 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                   - 
                   
                     V 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     drop 
                   
                 
                 
                   R 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   det 
                 
               
               . 
             
           
         
       
     
     As will be apparent to any skilled person, the supply voltages that are stepwise applied during the test routine may differ from those of the above described example, provided that they are within the ranges set by the standard specifications of the PoE technology. At present the standard specifications contemplate voltages comprised between 2.8V and 10V with a difference of 1V between different voltage levels. 
     Any skilled person will recognize that it is not mandatory that the optionally applied third voltage be comprised between the first and the second voltages; for example, it is possible to use a second voltage of 6V and a third voltage of 8V. Another parameter that is useful for identifying a valid PD is the capacitance Cdet of the PD connected in parallel to the line resistance Rdet. 
     According to a further embodiment, the capacitance Cdet of the PD is calculated using two different formulas depending on whether the current limiter Ilim is limiting or not the current absorbed by the line. 
     Let us consider first the case in which the current absorbed by the line is smaller than Ilim when a voltage of 8V is applied. When the device supplies the line at 8V, the capacitance Cdet of the PD, that is in parallel with the resistance Rdet seen from the terminal VLm and VLp, is rapidly charged at the voltage 8V-Vdrop (having neglected the resistance of the LAN line). Switching the applied supply voltage from 8V to 6V, the current absorbed by the line is null as long as the capacitance Cdet discharges on the resistance Rdet from the voltage 8V−Vdrop to the voltage 6V−Vdrop. Thereafter, the current may increase up to the value (6V−Vdrop)/Rdet. 
     In order to estimate the capacitance Cdet, the time interval tcd 1  from the beginning of the step at 6V to the instant in which the current absorbed by the line reaches the steady-state level IL 4 , when the line is supplied at 4V, is measured. 
     The control logic estimates the capacitance value Cdet as a function of this time interval, of the resistance Rdet, of the voltage drop Vdrop, and of the second (8V) and third voltage (6V) using the following formula: 
     
       
         
           
             
               C 
               ⁢ 
               
                   
               
               ⁢ 
               det 
             
             = 
             
               
                 - 
                 
                   
                     tcd 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     det 
                   
                 
               
               · 
               
                 1 
                 
                   ln 
                   ⁢ 
                   
                     
                       
                         6 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         V 
                       
                       - 
                       
                         V 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         drop 
                       
                     
                     
                       
                         8 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         V 
                       
                       - 
                       
                         V 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         drop 
                       
                     
                   
                 
               
             
           
         
       
     
       FIG. 2  depicts graphs of the supply voltage and of the current absorbed by the line for a capacitance value smaller than 1.5 μF. 
       FIG. 4  depicts various waveforms of the current absorbed by the line based upon the voltage step from 8V to 6V with a line resistance Rdet of 25 kΩ and for different values of capacitance Cdet. 
     If the capacitance Cdet is relatively large (larger than 1.5 μF, as often in the case in a pre-standard) and a voltage of 8V is applied, the current absorbed by the line exceeds the threshold value imposed by specifications, therefore the current limiter Ilim limits the current absorbed by the line up to this threshold value. In this case, the operational amplifier OA with the driver M 1  and the current limiter Ilim, during transitions from 0V to 4V and during the transition from the step 4V to 8V, acts for a certain time (that is a function of the value of Ilim and of Cdet) as a current generator that draws a constant current from the line. As depicted in  FIG. 3 , the voltage on the node VLm may not instantaneously follow the voltage VI generated by the block V OUT SET  on the resistor R 1 . 
     The comparator  7  senses when the voltage applied on the line is larger than that generated on the resistor R 1  and provides to the digital block  9  an active flag. The signal output by the comparator  7  delays the beginning of the 3 ms interval that starts if the flag is logically low, in order to prevent significant errors in measuring the steady-state values of IL 4  and IL 8 , in the presence of longer lasting transients. 
     According to an embodiment, the time tdc 2  in which the output of the comparator  7  remains at a high logic level, because of the switching from the first supply voltage (4V) to the second voltage (8V), is measured, and the capacitance Cdet of the PD as a function of tcd 2 , Rdet, Vdrop and of the two voltage levels (4V and 8V) is calculated with the following formula: 
     
       
         
           
             
               C 
               ⁢ 
               
                   
               
               ⁢ 
               det 
             
             = 
             
               
                 - 
                 
                   
                     tcd 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     det 
                   
                 
               
               · 
               
                 1 
                 
                   ln 
                   ⁢ 
                   
                     
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           det 
                           · 
                           I 
                         
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         lim 
                       
                       - 
                       
                         ( 
                         
                           
                             4 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             V 
                           
                           - 
                           
                             V 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             drop 
                           
                         
                         ) 
                       
                     
                     
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           det 
                           · 
                           I 
                         
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         lim 
                       
                       - 
                       
                         ( 
                         
                           
                             8 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             V 
                           
                           - 
                           
                             V 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             drop 
                           
                         
                         ) 
                       
                     
                   
                 
               
             
           
         
       
     
     If the steady-state current flowing through the resistance Rdet (that is IL 8 ) is negligible in respect to the current Ilim, then the previous formula may be simplified as follows: 
     
       
         
           
             
               C 
               ⁢ 
               
                   
               
               ⁢ 
               det 
             
             = 
             
               - 
               
                 
                   tcd 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     2 
                     · 
                     I 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   lim 
                 
                 
                   
                     8 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                   - 
                   
                     4 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                 
               
             
           
         
       
     
       FIG. 5  depicts different waveforms of absorbed currents and the relative flags output by the comparator  7  for voltage switchings from 4V to 8V, obtained with different capacitance values Cdet and with a resistance Rdet of 25 kΩ (and thus for different values of tdc 2 ). 
     The novel system of this disclosure is capable of providing during a “detection phase” and exhaustive amount of significant data for recognizing the state of the line and of a PD eventually connected to it. The electrical data obtained allows the control system of the power supplied to the LAN line to decide correctly, even with desirably overhauled standard specifications requiring more details of the electrical characteristics of the line to be powered (for example the new international specifications IEEE803.at that is being discussed and that contemplates powerable devices of up to 30 W rating and a full compatibility with pre-standard PDs). It is evident that the supply voltages may be immediately adapted for being compliant with future PoE specifications. 
     This provides for a practically absolute reliability of the assessment of the presence of a valid PD connected to the line by virtue of the different verifications that are carried out. 
     Systems realized according to a preferred embodiment are also capable of communicating the value of the capacitive component of the line, in addition to an accurate value of the resistive components. This allows the system to recognize and validate pre-standard PDs, and could allow discrimination in a detection phase PDs that require different approaches from the controller of the powering of the LAN line (i.e. PD that require powers larger than the threshold permitted by the present standard, PD that require 2 or 4 twisted wires and so on). 
     Verifying the voltage drop of the nonlinear elements of the PD enhances the reliability of the decision on whether to power a valid remote PD or not.