Patent Publication Number: US-2022231591-A1

Title: Control method of switching circuit, control circuit of switching circuit, and switching circuit

Description:
CROSS REFERENCE TO THE RELATED APPLICATIONS 
     This application is based upon and claims priority to Chinese Patent Application No. 202110061952.4, filed on Jan. 18, 2021, the entire contents of which are incorporated herein by reference. 
     TECHNICAL FIELD 
     The present disclosure relates to the technical field of power electronics, and more particularly to a control method of a switching circuit, a control circuit of the switching circuit, and the switching circuit. 
     BACKGROUND 
     In the switched-mode power supply (SMPS), especially the power supply for the Intel® processor, the SMPS needs to receive instructions from the processor and adjust the output voltage in real time to optimize processor performance and power consumption. In order to achieve this function, after a specific instruction is received, the reference voltage needs to follow the output voltage. In the prior art, the output voltage is sampled, and the reference voltage that follows the output voltage is generated through an analog-to-digital conversion circuit and a digital-to-analog conversion circuit. Due to the fast rate of change of the output voltage, a fast analog-to-digital conversion circuit and a fast digital-to-analog conversion circuit are required. The present disclosure directly uses an analog circuit to realize that a voltage reference follows the output voltage, which is convenient and low in cost. 
     SUMMARY 
     In view of the above, a purpose of the present disclosure is to provide a control method of a switching circuit, a control circuit of the switching circuit, and the switching circuit to solve the problems that fast analog-to-digital conversion circuit and digital-to-analog conversion circuit are required to make a voltage reference follow the output voltage in the prior art. 
     A technical solution of the present disclosure is to provide a control method of a switching circuit. The control method includes the following steps: generating a first voltage reference, and controlling slopes of a rising edge and a falling edge to generate a second voltage reference; and performing an operational amplification on an output feedback voltage and a reference voltage to obtain a compensation voltage. When the first voltage reference has the falling edge, the reference voltage is coupled to the first voltage reference through a first switch, and the second voltage reference is coupled to an output voltage through a second switch. When the first voltage reference has the rising edge, the reference voltage is coupled to the second voltage reference through a third switch. 
     Optionally, the slopes of the rising edge and the falling edge of the first voltage reference may be controlled according to set slopes to generate the second voltage reference. 
     Optionally, a central processing unit (CPU) may set the slopes. 
     Another technical solution of the present disclosure is to provide a control circuit of a switching circuit. The control circuit includes a slope buffer and a first operational amplifier. The slope buffer receives a first voltage reference, and controls slopes of a rising edge and a falling edge to generate a second voltage reference. The first operational amplifier receives an output feedback voltage and a reference voltage, and performs an operational amplification to obtain a compensation voltage. 
     When the first voltage reference has the falling edge, the reference voltage is coupled to the first voltage reference through a first switch, and the second voltage reference is coupled to an output voltage through a second switch. When the first voltage reference has the rising edge, the reference voltage is coupled to the second voltage reference through a third switch. 
     Optionally, the slopes of the rising edge and the falling edge of the first voltage reference may be controlled according to set slopes to generate the second voltage reference. 
     Optionally, a central processing unit (CPU) may set the slopes. 
     Optionally, the control circuit may further include a digital-to-analog conversion circuit, and the digital-to-analog conversion circuit may generate the first voltage reference. 
     Optionally, when the first voltage reference has the falling edge, a first signal may change from being invalid to being valid. When the first voltage reference has the rising edge, the first signal may change from being valid to being invalid. When the first signal is valid, the reference voltage may be coupled to the first voltage reference through the first switch, and the second voltage reference may be coupled to the output voltage through the second switch. When the first signal is invalid, the reference voltage may be coupled to the second voltage reference through the third switch. 
     Optionally, when a first enable signal is valid, and when the first voltage reference has the falling edge, the first signal may change from being invalid to being valid. When the first voltage reference has the rising edge, the first signal may change from being valid to being invalid. 
     When the first enable signal is invalid, the first signal may be invalid. 
     Optionally, the first enable signal may be SetVID_Decay. 
     Optionally, the slope buffer may include a second operational amplifier and a first capacitor. A first terminal of the second operational amplifier may receive the first voltage reference, and a second terminal of the second operational amplifier may be coupled to an output terminal of the second operational amplifier, and may be coupled to a negative voltage output terminal of the switching circuit through the first capacitor. 
     Optionally, the first operational amplifier may include a first current-type operational amplifier, a first compensation capacitor, a proportion amplification circuit and a first voltage follower. The first current-type operational amplifier may receive the output feedback voltage and the reference voltage. The proportion amplification circuit may receive the output voltage and the reference voltage. The proportion amplification circuit may be coupled to a common-mode voltage. An output of the first current-type operational amplifier may be coupled to an output of the proportion amplification circuit through the first compensation capacitor. The output of the first current-type operational amplifier may generate the compensation voltage through the first voltage follower. 
     Another technical solution of the present disclosure is to provide an operational amplification circuit. The operational amplification circuit includes a first current-type operational amplifier, a first compensation capacitor and a proportion amplification circuit. The first current-type operational amplifier receives a first feedback voltage and a reference voltage. The proportion amplification circuit receives a first voltage and the reference voltage, and is coupled to a common-mode voltage, and performs a proportional amplification on the first voltage and the reference voltage. An output of the first current-type operational amplifier is coupled to an output of the proportion amplification circuit through the first compensation capacitor. The output of the first current-type operational amplifier generates a compensation voltage. 
     Optionally, the proportion amplification circuit may include a second current-type operational amplifier and a first resistor. The second current-type operational amplifier may receive the first voltage and the reference voltage. An output of the second current-type operational amplifier may be coupled to the common-mode voltage through the first resistor. The output of the second current-type operational amplifier may be an output of the proportion amplification circuit. 
     Optionally, the operational amplification circuit may further include a first voltage follower. The output of the first current-type operational amplifier may generate the compensation voltage through the first voltage follower. 
     Optionally, a gain of the second current-type operational amplifier may be k times that of the first current-type operational amplifier. k may be greater than 1. 
     Optionally, the first voltage may be an output voltage. The first feedback voltage may be an output feedback voltage. The output voltage may be coupled to the output feedback voltage through a second resistor. An output sampling current may be coupled to the output feedback voltage. 
     Optionally, the first voltage may be coupled to the first feedback voltage through a voltage-dividing circuit. The voltage-dividing circuit may divide the first voltage. 
     Optionally, the voltage-dividing circuit may include a first control switch, a second control switch, a voltage-dividing resistor and a second voltage follower. The first voltage may be coupled to an input terminal of the second voltage follower through the first control switch. The first voltage may be coupled to the second control switch through the voltage-dividing resistor. The second control switch may be coupled to the input terminal of the second voltage follower. An output terminal of the second voltage follower may be coupled to the first feedback voltage. The operational amplification circuit may receive the reference voltage and a voltage of the input terminal of the second voltage follower. 
     Another technical solution of the present disclosure is to provide a switching circuit. 
     Compared with the prior art, the structure and method of the circuit according to the present disclosure have advantages as follows: an analog circuit is used to realize that the voltage reference follows the output voltage, which is convenient and low in cost. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a control circuit according to the present disclosure; 
         FIG. 2  is a schematic waveform diagram of a first signal, a first voltage reference, a second voltage reference and a reference voltage of the control circuit according to the present disclosure; 
         FIG. 3  is a schematic circuit diagram of an embodiment of a digital-to-analog conversion circuit  100  of the control circuit according to the present disclosure; 
         FIG. 4  is a schematic circuit diagram of an embodiment of an operational amplifier  300  according to the present disclosure; 
         FIG. 5  is a schematic circuit diagram of another embodiment of the operational amplifier  300  according to the present disclosure; 
         FIG. 6  is a schematic circuit diagram of an embodiment of the operational amplifier  300  according to the present disclosure added with DROOP; 
         FIG. 7  is a schematic circuit diagram of an embodiment of the operational amplifier  300  according to the present disclosure added with a voltage-dividing circuit; and 
         FIG. 8  is a schematic circuit diagram of an embodiment of the operational amplifier  300  according to the present disclosure added with both DROOP and the voltage-dividing circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The preferred embodiments of the present disclosure are described in detail below with reference to the drawings, but the present disclosure is not limited to these embodiments. The present disclosure covers any substitution, modification, equivalent method and solution made within the spirit and scope of the present disclosure. 
     For a better understanding of the present disclosure, the specific details of the following preferred embodiments of the present disclosure are explained herein after in detail, while the present disclosure can also be fully understood by those skilled in the art without the description of these details. 
     The present disclosure is described in detail by giving examples with reference to the drawings. It should be noted that the drawings are simplified and do not use an accurate proportion, that is, the drawings are merely for the objectives of conveniently and clearly assisting in illustrating embodiments of the present disclosure. 
     The present disclosure provides a control circuit of a switching circuit. As shown in  FIG. 1 , the control circuit includes a slope buffer  200  and a first operational amplifier  300 . The slope buffer  200  receives a first voltage reference VA, and controls slopes of a rising edge and a falling edge to generate a second voltage reference VB. The first operational amplifier  300  receives an output feedback voltage VFB and a reference voltage VBR, and performs an operational amplification to obtain a compensation voltage COMP. When the first voltage reference VA has the falling edge, the reference voltage VBR is coupled to the first voltage reference VA through a first switch K 410 , and the second voltage reference VB is coupled to an output voltage VO+ through a second switch K 420 . When the first voltage reference VA has the rising edge, the reference voltage VBR is coupled to the second voltage reference VB through a third switch K 430 .  FIG. 2  is a schematic waveform diagram of the first voltage reference VA, the second voltage reference VB and the reference voltage VBR of the control circuit according to the present disclosure. At moment t 01 , the first voltage reference VA has the falling edge. After passing through the slope buffer  200 , the slope of the falling edge of the second voltage reference VB becomes lower. The reference voltage VBR at this time is approximately equal to the first voltage reference VA. At moment t 02 , the first voltage reference VA has the rising edge, and at this time, the second voltage reference VB starts to rise slowly before it drops to a voltage between moment t 01  and moment t 02  of the first voltage reference VA, and the reference voltage VBR steps to the value of the second voltage reference VB and starts to rise slowly like the second voltage reference VB. In the present disclosure, an analog circuit is used to realize that the voltage reference follows the output voltage, which is convenient and the cost is low. 
     In an embodiment, the slopes of the rising edge and the falling edge of the first voltage reference VA are controlled according to set slopes. The set slopes are not limited to linear slopes shown in  FIG. 2 , and may be any type of slopes. In an embodiment, a CPU is used to set the slopes. 
     As shown in  FIG. 1 , the control circuit further includes a digital-to-analog conversion circuit  100 , and the digital-to-analog conversion circuit generates the first voltage reference VA. 
       FIG. 3  shows an embodiment of the digital-to-analog conversion circuit  100 . The digital-to-analog conversion circuit  100  includes an operational amplifier  110 , a current mirror composed of switching tubes M 120  and M 130 , a switching tube M 110 , a resistor R 110 , and a resistor R 120 . The operational amplifier  110  receives an internal voltage reference VBG and a voltage on the resistor R 110 . The output of the operational amplifier  110  is coupled to the gate of the switching tube M 110 . The source of the switching tube M 110  is coupled to the resistor R 110 . The other terminal of the resistor R 110  is coupled to the reference ground. The drain of the switching tube M 110  is coupled to the input terminal of the current mirror. The digital signal controls the number of the actually coupled current mirrors. The output terminal of the current mirror is coupled to the resistor R 120 . A voltage on the resistor R 120  is the output voltage of the digital-to-analog conversion circuit  100 . 
     In an embodiment, a first signal is used to control the first switch K 410 , the second switch K 420  and the third switch K 430 . When the first voltage reference VA has the falling edge, the first signal TRACK changes from being invalid to being valid. When the first voltage reference has the rising edge, the first signal TRACK changes from being valid to being invalid. When the first signal is valid, the reference voltage VBR is coupled to the first voltage reference VA through the first switch K 410 , and the second voltage reference VB is coupled to the output voltage VO+ through the second switch K 420 . When the first signal TRACK is invalid, the reference voltage is coupled to the second voltage reference VB through the third switch K 430 . TRACKB and TRACK shown in  FIG. 1  are logically complementary. In an embodiment, being valid may correspond to a high level, and being invalid may correspond to a low level. In another embodiment, in contrast, being valid may correspond to a low level, and being invalid may correspond to a high level. 
     In an embodiment, when a first enable signal is valid, and when the first voltage reference has the falling edge, the first signal changes from being invalid to being valid, and when the first voltage reference has the rising edge, the first signal changes from being valid to being invalid. When the first enable signal is invalid, the first signal is invalid. The first enable signal is SetVID_Decay. SetVID_Decay is an instruction in the SVID protocol for communication between the Intel processor and its power supply, and is used to reduce the output voltage of the power supply to a new target value with a slope determined by the load, so as to save power consumption. 
     In an embodiment, as shown in  FIG. 1 , the slope buffer  200  includes a second operational amplifier  210  and a first capacitor C 210 . A first terminal of the second operational amplifier  210  receives the first voltage reference VA, and a second terminal of the second operational amplifier  210  is coupled to an output terminal VB of the second operational amplifier  210 , and is coupled to a negative voltage output terminal VO− of the switching circuit through the first capacitor C 210 . 
     As shown in  FIG. 4 , the first operational amplifier  300  includes a first current-type operational amplifier  310 , a first compensation capacitor C 310 , a proportion amplification circuit  320  and a first voltage follower  330 . The first current-type operational amplifier  310  receives the output feedback voltage VFB and the reference voltage VBR. The proportion amplification circuit  320  receives the output voltage VO+ and the reference voltage VBR. The proportion amplification circuit  320  is coupled to a common-mode voltage VDC. An output of the first current-type operational amplifier  310  is coupled to an output of the proportion amplification circuit  320  through the first compensation capacitor C 310 . The output of the first current-type operational amplifier  310  generates the compensation voltage COMP through the first voltage follower  330 . 
     A technical solution of the present disclosure is to provide a control method of a switching circuit. The control method includes the following steps: generating a first voltage reference, and controlling slopes of a rising edge and a falling edge to generate a second voltage reference; and performing an operational amplification on an output feedback voltage and a reference voltage to obtain a compensation voltage; when the first voltage reference has the falling edge, the reference voltage is coupled to the first voltage reference through a first switch, and the second voltage reference is coupled to an output voltage through a second switch; when the first voltage reference has the rising edge, the reference voltage is coupled to the second voltage reference through a third switch. 
     As an optional solution, the slopes of the rising edge and the falling edge of the first voltage reference are controlled according to set slopes. 
     As an optional solution, a central processing unit (CPU) may set the slopes. 
     A yet another technical solution of the present disclosure is to provide an operational amplification circuit. As shown in  FIG. 4 , the operational amplification circuit includes a first current-type operational amplifier  310 , a first compensation capacitor C 310  and a proportion amplification circuit  320 . The first current-type operational amplifier  310  receives a first feedback voltage VFB and a reference voltage VBR. The proportion amplification circuit  320  receives a first voltage and the reference voltage VBR, and is coupled to a common-mode voltage VDC, and performs a proportional amplification on the first voltage and the reference voltage VBR. An output of the first current-type operational amplifier  310  is coupled to an output of the proportion amplification circuit  320  through the first compensation capacitor C 310 . A compensation voltage COMP is generated by the output of the first current-type operational amplifier  310 . In an embodiment, the operational amplification circuit further includes a first voltage follower  330 . The output of the first current-type operational amplifier  310  generates a compensation voltage through the first voltage follower  330 . In  FIG. 4 , the output of the first current-type operational amplifier  310  generates the compensation voltage COMP through the voltage follower  330 , and the voltage follower  330  is used to prevent the circuit coupled post the compensation voltage COMP from affecting the operational amplification circuit. Therefore, the voltage follower  330  may be optional. 
       FIG. 5  shows an embodiment with reference to a proportion amplification circuit  320 . The proportion amplification circuit includes a second current-type operational amplifier  321  and a first resistor R 310 . The second current-type operational amplifier  321  receives the first voltage and the reference voltage VBR. An output of the second current-type operational amplifier  321  is coupled to the common-mode voltage VDC through the first resistor R 310 . The output of the second current-type operational amplifier  321  is an output of the proportion amplification circuit  320 . 
     In an embodiment, a gain of the second current-type operational amplifier  321  is k times that of the first current-type operational amplifier  310 . k may be greater than 1. 
     As shown in  FIG. 6 , in an embodiment, a DROOP function is added, that is, when the output current is high, the voltage at the output terminal drops due to the voltage drop on the output wire, and the voltage sampled by the output voltage feedback does not contain the voltage drop on the wire. Therefore, the voltage drop on the wire also needs to be taken into account. The first voltage is an output voltage VO+. The first feedback voltage VFB is an output feedback voltage. The output voltage VO+ is coupled to the output feedback voltage through a second resistor R 340 . An output sampling current Itotal is coupled to the output feedback voltage. By sampling the output current and generating a voltage drop on the second resistor R 340 , the voltage drop on the output wire may be equivalent to. 
     As shown in  FIG. 7 , in an embodiment, an output voltage divider function is added. The first voltage is coupled to the first feedback voltage through a voltage-dividing circuit. The voltage-dividing circuit divides the first voltage. The voltage-dividing circuit includes a first control switch K 310 , a second control switch K 320 , voltage-dividing resistors R 320  and R 330  and a second voltage follower  340 . The first voltage is coupled to an input terminal of the second voltage follower  340  through the first control switch K 310 . The first voltage is coupled to the second control switch K 320  through the voltage-dividing resistor R 320 . The second control switch K 320  is coupled to the input terminal of the second voltage follower  340 . An output terminal of the second voltage follower  340  is coupled to the first feedback voltage VFB. The operational amplification circuit receives the reference voltage VBR and an input terminal voltage VOS+ of the second voltage follower. When the first control switch K 310  is on and the second control switch K 320  is off, the first voltage is coupled to the first feedback voltage through the voltage follower, and the value of the first feedback voltage is equal to the first voltage. When the second control switch K 320  is on and the first control switch K 310  is off, the first voltage is divided by the resistor, then coupled to the first feedback voltage through the voltage follower, and the value of the first feedback voltage is equal to the voltage value after the first voltage is divided. In the switching circuit, the first voltage is an output voltage, the first feedback voltage is an output feedback voltage. 
     In an embodiment, both output voltage divider function and DROOP function may be added. As shown in  FIG. 8 , the output voltage is coupled to the feedback voltage VFB through a voltage-dividing circuit and then through a circuit with DROOP function composed of a resistor R 340  and the output sampling current Itotal. 
     A yet another technical solution of the present disclosure is to provide a switching circuit. 
     Although the embodiments are separately illustrated and described above, the embodiments contain some common technologies. Those skilled in the art can replace and integrate the embodiments. Any content not clearly recorded in one of the embodiments may be determined based on another embodiment where the content is recorded. 
     The embodiments described above do not constitute a limitation on the scope of protection of the technical solution of the present disclosure. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-mentioned embodiments shall fall within the scope of protection of the technical solution of the present disclosure.