Patent Publication Number: US-6703883-B2

Title: Low current clock sensor

Description:
BACKGROUND OF THE INVENTION 
     The invention generally relates to electronic circuits, and more particularly to clock sensors. 
     Clock sensors are used to detect clock signals in many applications. Conventional clock sensors are configured with standard CMOS inverters. However, these CMOS inverters cannot detect signals with small swings and they draw a significant amount of power. Differential amplifiers having differential pair inputs are also used as clock sensors to detect small signals, but they also consume too much power. In a typical application, a clock sensor is used with a PLL (phase locked loop) in portable devices (e.g., laptop and handheld computers) for detecting incoming clock signals to “wake up” the circuits in the device to let the circuits be ready for operations. In these devices, low power consumption by clock sensors is especially important. These conventional clock sensors, however, typically consume a large amount of current and power while waiting for incoming clock signals, resulting in very inefficient use of power in the portable devices. 
     Therefore, there is a need for a clock sensor that requires low current and low power to operate on. 
     SUMMARY OF THE INVENTION 
     The invention provides a clock sensor that can be operated at very low current and power. This sensor can also detect an input clock signal with a very small amplitude to detect the presence of clock inputs. 
     According to one embodiment of the invention, a clock sensor comprises an input circuit configured to receive an input clock signal; a biasing circuit, connected to the input circuit, that is configured to receive the input clock signal and to provide biasing voltages; and a switching circuit, connected to the biasing circuit, that is configured to receive the biasing voltage and in response to the input clock signal, to provide a switching signal for switching an output circuit to generate an output clock signal. 
     According to another embodiment of the invention, the clock sensor further comprises an output circuit, connected to the biasing circuit, that is configured to receive the switching signal and to generate the output clock signal in response to the switching signal. In this embodiment, the input clock signal has a small amplitude and the output clock signal has a full amplitude. 
    
    
     Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein: 
     FIG. 1 shows a low current clock sensor according to one embodiment of the present invention; 
     FIGS. 2A-2C illustrate various voltage signals in the embodiment in FIG. 1; 
     FIG. 3 shows a schematic implementation of the embodiment in FIG. 1; and 
     FIG. 4 illustrates an application of the invention in a computer system. 
    
    
     Throughout the drawings, the same reference numerals indicate similar or corresponding features or functions. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a low current clock sensor  10  according to one embodiment of the present invention. In FIG. 1, clock sensor  10  comprises an input circuit  16 , a biasing circuit  20 , a switching circuit  26  and an output circuit  30 . The input circuit includes a pair of capacitors,  42  and  44 , which are connected to biasing circuit  20  via signal lines  48  and  49 , respectively. Biasing circuit  20  includes two transistors,  52  and  56 , configured so that each functions as a diode. Transistors  52  and  56  are connected to each other via a biasing resistor  50 . These transistors are also connected to biasing resistors  62  and  66 , respectively, which are connected to signal lines  48  and  49 , respectively. Biasing circuit  20  is connected to switching circuit  26  via signal lines  58  and  59 . Switching circuit  26  includes transistors  82  and  86  and has its output connected to an output circuit  30  via signal line  68 . Output circuit  30  includes an inverter  31  that provides an output clock signal V o  to a clock detection circuit, such as a low pass filter (not shown), via signal line  78 . 
     In operation, biasing circuit  20  provides biasing voltages to the gates of transistors  82  and  86 . More specifically, when no input voltage is supplied, biasing circuit  20  supplies a first biasing voltage of Vdd-V T  to the gate of transistor  82  via signal line  58  and a second biasing voltage of V T  to the gate of transistor  86  via signal line  59 . V T  is the threshold voltage of a transistor and is typically about 0.7 V. By biasing the gate voltages of transistors  82  and  86  in switching circuit  26 , these two transistors are kept in a near ON state. Thus, an input signal with a very small amplitude will activate transistors  82  and  86 . Since the devices are kept very small, clock sensor  10  operates at very low power and consumes little current. When there is an input clock signal v i , as illustrated in FIG. 2A, that is supplied to input circuit  16 , transistors  62  and  66  are turned on/off, depending on the voltage value of the input clock signal. Switching circuit  26  outputs a switching voltage v s  to inverter  31  via signal line  68 . The value of v s  fluctuates above and below the biasing voltages, as illustrated in FIG.  2 B. Switching voltage v s  switches inverter  31  on/off to cause the output clock signal v o  to be high or low, as illustrated in FIG.  2 C. The output clock signal v o  is then sent to a clock detection circuit via signal line  78 . The output clock signal v o  is a stronger signal compared to the input signal v s , and has the full amplitude of approximately Vdd. In this embodiment, even if the input clock signal v i  has a small amplitude (e.g., down to a value of about 200 mV) it can still be detected by clock sensor  10 . 
     In a specific embodiment of the invention, the ratio of the gate widths of transistors  52  and  56  is 2:2; the ratio of the gate widths of transistors  62  and  66  is 2:1; and the ratio of the gate widths of the transistors in inverter  31  is 4:2. 
     FIG. 3 shows a schematic implementation of the embodiment in FIG.  1 . As illustrated in FIG. 3, capacitors  42  and  46  are implemented with two MOS transistors with their source and drain electrodes connected together. This is convenient for the process used for the prototype, but is not the only way to realize a capacitor. 
     FIG. 4 illustrates an application of the present invention in a computer system  100 , which includes a processor  110 , a memory module  114  and a clock generating circuit  118 . Memory module includes memory chips  124  and a clock buffer, e.g., a zero-delay buffer  128 , which includes a clock sensor  10  of the invention. Clock generating circuit  118  supplies a clock signal to processor  110  and memory module  114  via buffer  128 . Buffer  128  replicates the clock signal and distributes it to the memory cells in memory chips  124 . In this application, the clock sensor in buffer  128  is used to detect whether a clock signal is coming so as to “wake up” memory chips  124  in the computer system in order to allow the system to return to active operation after a time in low power mode. Thus, while the system is in an inactive mode waiting for clock signals, the clock sensor requires little current to detect clock signals of small amplitudes and consumes very low power, which is especially important for portable systems. 
     While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. For example, although CMOS transistors are used in the above embodiments of the invention, other types of transistors, such as bipolar transistors, or a combination of bipolar and MOS transistors can also be used. Accordingly, it is intended to embrace all such alternatives, modifications and variations as falling within the spirit and scope of the appended claims.