Patent Publication Number: US-8120936-B2

Title: DC-to-AC power converting device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a power converting device, more particularly to a DC-to-AC power converting device. 
     2. Description of the Related Art 
       FIG. 1  illustrates a conventional solar power converting system that includes a solar cell array  1  for converting solar energy into electrical energy, a power conditioner  2  for receiving the electrical energy from the solar cell array  1  and for outputting an AC voltage output to a load or a power network, and a rechargeable battery  6 . The power conditioner  2  includes a charge/discharge controller  21  coupled to the solar cell array  1  and the rechargeable battery  6 , a DC-to-DC converter  22  coupled to the charge/discharge controller  21 , and a DC-to-AC inverter  23 . 
       FIG. 2  illustrates a conventional boost device that can be applied to the aforesaid DC-to-DC converter  22  of  FIG. 1 . The conventional boost device includes an inductor  11 , a switch  12 , a diode  13 , and a capacitor  14 . The inductor  11  has a first end coupled to an external power source  10 , and a second end. The switch  12 , such as a semiconductor power switch, has a first terminal coupled to a common node between the second end of the inductor  11  and an anode of the diode  13 , a second terminal coupled to ground, and a control terminal for receiving an external control signal such that the switch  12  is operable between an ON-state and an OFF-state in response to the external control signal. The capacitor  14  is coupled between a cathode of the diode  13  and ground. 
     When the switch  12  is operated in the ON-state, a current (i L ) from the external power source  10  flows through the inductor  11  to store electric power. When the switch  12  is operated in the OFF-state, the capacitor  14  is charged with a current from the inductor  11  through the diode  13  such that the conventional boost device outputs an output voltage, i.e., a voltage across the capacitor  14 , to a load. 
     The following are some of the drawbacks of the conventional boost device: 
     1. When the switch  12  is in the OFF-state, a voltage across the switch  12  is substantially equal to the output voltage. Therefore, if the switch  12  is implemented as a MOSFET device, a relatively large conducting impedance is exhibited by the MOSFET device, thereby resulting in a relatively large conduction loss. 
     2. When the switch  12  is switched from the OFF-state to the ON-state, a reverse bias surge current is generated to flow through the switch  12  that causes serious switching loss, thereby reducing power transformation efficiency. 
       FIG. 3  illustrates another conventional boost device that can be applied to the aforesaid DC-to-DC converter  22  of  FIG. 1 . The conventional boost device includes a coupling inductor  15 , a switch  16 , a diode  17 , and an output capacitor  18 . The coupling inductor  15  has first and second windings  151 ,  152 , each of which has a polarity end and a non-polarity end. The polarity end of the first winding  151  is coupled to an external power source  10 . The switch  16  has a first terminal coupled to a common node between the non-polarity end of the first winding  151  and the polarity end of the second winding  152 , a second terminal coupled to ground, and a control terminal for receiving an external control signal such that the switch  16  is operable between an ON-state and an OFF-state in response to the external control signal. The diode  17  has an anode coupled to the non-polarity end of the second winding  152 , and a cathode. The capacitor  18  is coupled between the cathode of the diode  17  and ground. 
     When the switch  16  is operated in the ON-state, a current from the external power source  10  flows through the first winding  151  such that the first winding  151  is excited to store electric power. When the switch  16  is operated in the OFF-state, energy stored in the coupling inductor  15  charges the output capacitor  18  through the second winding  152  and the diode  17  such that the conventional boost device outputs an output voltage, i.e., a voltage across the output capacitor  18 , to a load. 
     When the switch  16  is switched from the ON-state to the OFF-state, a voltage is generated as a result of a leakage inductance of the coupling inductor  15  and can cause damage to the switch  16 . As such, an additional snubber circuit is required to absorb energy attributed to the leakage inductance. 
     Since the operation of the conventional boost device is described in detail in the aforesaid patent, further discussion of the same is omitted herein for the sake of brevity. 
     However, such a conventional boost device cannot provide electrical isolation. Thus, for an outdoor power supplying appliance including the conventional boost device, lightning strike may result in damage to the conventional boost device. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a boost device that can attain high power transformation efficiency and that can provide electrical isolation. 
     According to the present invention, there is provided a power converting device for converting a DC voltage input from an external power source into an AC voltage output. The power converting device comprises: 
     a transformer having first and second windings each having opposite first and second ends, the first end of the first winding being adapted to be coupled to the external power source; 
     a clamp unit coupled to the transformer and adapted to be coupled to the external power source, the clamp unit including
         a first switch coupled between a reference node and the second end of the first winding of the transformer, and operable between an ON-state and an OFF-state, and   a series connection of a clamp capacitor and a second switch coupled across the first winding of the transformer, the second switch being operable between an ON-state and an OFF-state; and       

     an inverting unit coupled to the first end of the second winding of the transformer, and operable so as to output the AC voltage output based on an induced voltage across the second winding of the transformer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment with reference to the accompanying drawings, of which: 
         FIG. 1  is a schematic circuit block diagram illustrating a conventional solar power converting system; 
         FIG. 2  is a schematic electrical circuit diagram illustrating a conventional boost device; 
         FIG. 3  is a schematic electrical circuit diagram illustrating another conventional boost device; 
         FIG. 4  is a schematic electrical circuit diagram illustrating the preferred embodiment of a power converting device according to the present invention; 
         FIGS. 5   a  and  5   b  illustrate waveforms of external control signals (v gS1 , v gS2 ) for first and second switches of a clamp unit of the preferred embodiment, respectively; 
         FIG. 5   c  illustrates waveforms of currents (i LP , i LS ) flowing respectively through first and second windings of a transformer of the preferred embodiment; 
         FIG. 5   d  illustrates a waveform of an exciting current (i LM ) of the transformer of the preferred embodiment; 
         FIG. 5   e  illustrates waveforms of a current (i S1 ) flowing through the first switch, and a voltage (v S1 ) across the first switch; 
         FIG. 5   f  illustrates waveforms of a current (i S2 ) flowing through the second switch, and a voltage (v S2 ) across the second switch; 
         FIG. 5   g  illustrates waveforms of a current (i 1 ) flowing through a diode of a first switch unit of the preferred embodiment, and a voltage (v D1 ) across the diode of the first switch unit; 
         FIG. 5   h  illustrates waveforms of a current (i DW ) flowing through a first diode of a boost unit of the preferred embodiment, and a voltage (v DW ) across the first diode; 
         FIG. 5   i  illustrates waveforms of a current (i DY ) flowing through a second diode of the boost unit of the preferred embodiment, and a voltage (v DY ) across the second diode; 
         FIG. 6  is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a first mode; 
         FIG. 7  is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a second mode; 
         FIG. 8  is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a third mode; 
         FIG. 9  is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a fourth mode; 
         FIG. 10  is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a fifth mode; 
         FIG. 11  is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a sixth mode; 
         FIG. 12  is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a seventh mode; 
         FIGS. 13   a  and  13   b  illustrate respectively waveforms of the current (i LP ) flowing through the first winding (L P ) and a control signal (v gS1 ) for the first switch when in a step-down operation; and 
         FIG. 14  is a plot illustrating experimental results of power transformation efficiency of the preferred embodiment for a DC voltage input of 18 Volts. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to  FIG. 4 , the preferred embodiment of a power converting device according to the present invention is shown to be adapted for converting a DC voltage input (V IN ) from an external power source into an AC voltage output, such as a sinusoidal signal. The power converting device includes a transformer (T r ), a clamp unit  3 , an inverting unit  5 , and a boost unit  4 . 
     The transformer (T r ) includes first and second windings (L P , L S ) wound around an iron core. A winding ratio of the first and second windings (L P , L S ) is equal to 1:N. Each of the first and second windings (L P , L S ) has a polarity end serving as a first end, and a non-polarity end serving as a second end. The polarity end of the first winding (L P ) is adapted to be coupled to the external power source for receiving the input voltage (V IN ). It is noted that the transformer (T r ) can accommodate high leakage inductance component. The first and second windings (L P , L S ) can be separately wound in a known manner, which is much easier compared to a conventional sandwich winding manner. 
     The clamp unit  3  is coupled to the transformer (T r ) and is adapted to be coupled to the external power source. The clamp unit  3  includes a first switch (S 1 ), and a series connection of a clamp capacitor (C X ) and a second switch (S 2 ). The first switch (S 1 ) is coupled between a reference node, such as ground, and the non-polarity end of the first winding (L P ) of the transformer (T r ). The first switch (S 1 ) has a control end for receiving an external control signal (v gS1 ), and is operable to switch between an ON-state and an OFF-state in response to the external control signal (v gS1 ). The series connection of the clamp capacitor (C X ) and the second switch (S 2 ) is adapted to be coupled to the external power source, and is coupled in parallel to the first winding (L P ) of the transformer (T r ). The second switch (S 2 ) has a control end for receiving an external control signal (v gS2 ), and is operable to switch between an ON-state and an OFF-state in response to the external control signal (v gS2 ). 
     It is noted that, based on the external control signals (v gS1 , v gS2 ) shown in  FIGS. 5   a  and  5   b , the first and second switches (S 1 , S 2 ) are operated alternately in the ON-state, and duration of the ON-state of one of the first and second switches (S 1 , S 2 ) does not overlap duration of the ON-state of the other one of the first and second switches (S 1 , S 2 ). In this embodiment, the first and second switches (S 1 , S 2 ) are switched at a frequency of 100 KHz. 
     The inverting unit  5  is coupled to the polarity end of the second winding (L S ) of the transformer (T r ), and is operable so as to output the AC voltage output (v O ) based on an induced voltage across the second winding (L S ) of the transformer (T r ). The inverting unit  5  includes a full-bridge circuit and an output capacitor (C O ). 
     The full-bridge circuit has a configuration similar to that disclosed in U.S. patent application Ser. No. 12/470,246. The full-bridge circuit includes a first series connection of first and second switch units  51 ,  52 , and a second connection of third and fourth switch units  53 ,  54 . The first and second series connections are coupled in parallel between the polarity end of the second winding (L S ) of the transformer (T r ) and the reference node. Each of the first, second, third and fourth switch units  51 ,  52 ,  53 ,  54  includes a diode (D 1 , D 2 , D 3 , D 4 ) and a switch (T 1 , T 2 , T 3 , T 4 ) coupled in series to each other. The switch (T 1 , T 2 , T 3 , T 4 ) of each of the first, second, third and fourth switch units  51 ,  52 ,  53 ,  54  is operable between an ON-state and an OFF-state. In this embodiment, the first switch unit  51  is coupled to the third switch unit  53 , and the second switch unit  52  is coupled to the fourth switch unit  54 . The diode (D 1 , D 3 ) of each of the first and third switch units  51 ,  53  has an anode coupled to the polarity end of the second winding (L S ) of the transformer (T r ), and a cathode coupled to the switch (T 1 , T 3 ) thereof. The diode (D 2 ) of the second switch unit  52  has an anode coupled to the switch (T 1 ) of the first switch unit  51 , and a cathode coupled to the switch (T 2 ). The diode (D 4 ) of the fourth switch unit  54  has an anode coupled to the switch (T 3 ) of the third switch unit  53 , and a cathode coupled to the switch (T 4 ). The switches (T 1 , T 4 ) of the first and fourth switch units  51 ,  54  are simultaneously in the ON-state, and the switches (T 2 , T 3 ) of the second and third switch units  52 ,  53  are simultaneously in the ON-state. When the switch (T 1 ) of the first switch unit  51  is in the ON-state, the switch (T 2 ) of the second switch unit  52  is in the OFF-state. It is noted that the diodes (D 1 , D 2 /D 3 , D 4 ) are used to prevent short circuit. In this embodiment, the switches (T 1 , T 2 , T 3 , T 4 ) are switched at a frequency of 60 Hz. 
     The output capacitor (C O ) is coupled between a first common node (n 1 ) between the first and second switch units  51 ,  52 , and a second common node (n 2 ) between the third and fourth switch units  53 ,  54 . The AC voltage output (v O ) is a voltage across the output capacitor (C O ). The output capacitor (C O ) is capable of being charged through the full-bridge circuit with an induced voltage across the second winding (L S ) of the transformer (T r ). When the switches (T 1 , T 4 ) of the first and fourth switch units  51 ,  54  are in the ON-state, the output capacitor (C O ) is charged so that the AC voltage output (v O ) is a positive half of a sinusoidal signal. When the switches (T 2 , T 3 ) of the second and third switch units  52 ,  53  are in the ON-state, the output capacitor (C O ) is charged so that the AC voltage output (v O ) is a negative half of the sinusoidal signal. 
     The boost unit  4  is coupled across the second winding (L S ) of the transformer (T r ). The boost unit  4  is capable of being charged with the induced voltage across the second winding (L S ) of the transformer (T r ), and of charging the output capacitor (C O ) through the full-bridge circuit so as to boost the voltage across the output capacitor (C O ). The boost unit  4  has a configuration similar to a boost circuit disclosed in U.S. patent application Ser. No. 12/433,039, and includes a first capacitor (C Y ), a series connection of a first diode (D W ) and a second capacitor (C W ), and a second diode (D Y ). The first capacitor (C Y ) is coupled between the non-polarity end of the second winding (L S ) of the transformer (T r ) and the reference node. It is noted that the output capacitor (C O ) is further charged through the full-bridge circuit with a voltage across the first capacitor (C Y ) when the output capacitor (C O ) is charged with the induced voltage across the second winding (L S ) of the transformer (T r ), as best shown in  FIGS. 6 and 7 . The series connection of the first diode (D W ) and the second capacitor (C W ) is coupled in parallel to the second winding (L S ) of the transformer (T r ). The first diode (D W ) has an anode coupled to the second capacitor (C W ), and a cathode coupled to the non-polarity end of the second winding (L S ) of the transformer (T r ). When the output capacitor (C O ) is charged through the full-bridge circuit with the induced voltage across the second winding (L S ) of the transformer (T r ), the second capacitor (C W ) is charged through the first diode (D W ) with the induced voltage across the second winding (L S ) of the transformer (T r ), as best shown in  FIGS. 6 and 7 . The second diode (D Y ) has an anode coupled to the reference node, and a cathode coupled to a common node (p) between the anode of the first diode (D W ) and the second capacitor (C W ). The first capacitor (C Y ) is capable of being charged through the second diode (D Y ) with a voltage (V CW ) across the second capacitor (C W ), as best shown in  FIGS. 9 ,  10  and  11 . It is noted that the first diode (D W ) and the second diode (D Y ) do not conduct simultaneously. 
     The boost unit  4  of the preferred embodiment is operable among first to seventh modes based on the external control signals (v gsi , v gs2 ) for the first and second switches (S 1 , S 2 ) of the clamp unit  4  shown in  FIGS. 5   a  and  5   b .  FIG. 5   d  illustrates a waveform of an exciting current (i LM ) of the transformer (T r ).  FIG. 5   c  illustrates waveforms of currents (i LP , i LS ) flowing respectively through the first and second windings (L p , L s ) of the transformer (T r ).  FIG. 5   e  illustrates waveforms of a current (i s1 ) flowing through the first switch (S i ), and a voltage (v s1 ) across the first switch (S 1 ).  FIG. 5   f  illustrates waveforms of a current (i s2 ) flowing through the second switch (S 2 ), and a voltage (v s2 ) across the second switch (S 2 ).  FIG. 5   g  illustrates waveforms of a current (i 1 ) flowing through the diode (D 1 ) of the first switch unit  51 , and a voltage (v D1 ) across the diode (D 1 ).  FIG. 5   h  illustrates waveforms of a current (i Dw ) flowing through the first diode (D w ) of the boost unit  4 , and a voltage (v DW ) across the first diode (D w ).  FIG. 5   i  illustrates waveforms of a current (i DY ) flowing through the second diode (D y ) of the boost unit  4 , and a voltage (v DY ) across the second diode (D y ). 
     Referring further to  FIGS. 5   a  to  5   i , and  6 , the boost unit  4  is operated in the first mode during a period from t 0  to t 1 . In  FIG. 6 , L M  represents an exciting inductance of the transformer (T r ), L k1  represents a leakage inductance of the first winding (L P ), and L k2  represents a leakage inductance of the second winding (L S ). Therefore, a coupling coefficient (k) is represented as follows:
 
 k=L   M /( L   k1   +L   M )= L   M   /L   1   (Equation 1)
 
where L 1  is an inductance of the first winding (L P ). In the first mode, the first switch (S 1 ) is in the ON-state, the second switch (S 2 ) is in the OFF-state, and the diodes (D 1 , D 4 ) and the first diode (D W ) conduct. The first winding (L P ) is excited by a current (i IN ) from the external power source to generate an induced voltage equal to V IN  across the first winding (L P ). Thus, the induced voltage (v LS ) across the second winding (L S ) is represented as follows:
 
ν LS   =N ( V   IN −ν k1 )  (Equation 2)
 
where v k1  is a voltage across the leakage inductance (L k1 ). At the same time, the second capacitor (C W ) is charged through the first diode (D W ) with the induced voltage (v LS ) across the second winding (L S ) to N(V IN −ν k1 ) so as to clamp a voltage across the second diode (D Y ). Thus, the voltage (v CW ) across the second capacitor (C W ) is represented as follows:
 
ν CW =ν LS −ν k2   =NV   IN −2 Nν   k1   (Equation 3)
 
where v k2  is a voltage across the leakage inductance (L k2 ). In this case, the output capacitor (C O ) is charged through the first and fourth switch units  51 ,  54  with the induced voltage (v LS ) across the second winding (L S ), and the voltage (v CY ) across the first capacitor (C Y ). Therefore, the AC voltage output (v O ) is represented as follows:
 
ν O =ν CY +ν LS   (Equation 4)
 
(v CY  is equal to NV IN /(1−d)−2Nv k1  which will be described in detail later, where d is a duty cycle of the first switch (S 1 )). In the first mode, the current (i LP ) flowing through the first winding (L P ) includes the exciting current (i LM ) and an induced current. When the waveform of the current (i s1 ) flowing through the first switch (S 1 ) is close to being a square shape through appropriate configuration of the exciting inductance (L M ) and the coupling coefficient (k), the first switch (S 1 ) has relatively low conduction loss and switching loss.
 
     Referring to  FIGS. 5   a  to  5   i , and  7 , the boost unit  4  is operated in the second mode during a period from t 1  to t 2 . In the second mode, the first and second switches (S 1 , S 2 ) are in the OFF-state, and the diodes (D 1 , D 4 ) and the first diode (D W ) conduct. Energy attributed to the leakage inductance (L k1 ) of the first winding (L P ) is released to the transformer (T r ) such that the second winding (L S ) is operated as in the first mode. In this case, the current (i LP ) flowing through the first winding (L P ) begins to charge a parasitic capacitance of the first switch (S 1 ) such that the voltage (v S1 ) across the first switch (S 1 ) rises (see  FIG. 5   e ). On the other hand, a parasitic capacitance of the second switch (S 2 ) discharges such that the voltage (v S2 ) across the second switch (S 2 ) reduces to zero (see  FIG. 5   f ). Thus, a sum of the voltage (v S1 ) across the first switch (S 1 ) and the voltage (v S2 ) across the second switch (S 2 ) is equal to a sum of a voltage (v CX ) across the clamp capacitor (C X ) and the DC voltage input (V IN ). That is,
 
ν S1 +ν S2   =V   IN +ν CX   (Equation 5)
 
     Referring to  FIGS. 5   a  to  5   i , and  8 , the boost unit  4  is operated in the third mode during a period from t 2  to t 3 . In the third mode, the first switch (S 1 ) is in the OFF-state, and the second switch (S 2 ) is in the ON-state. When the voltage (v S2 ) across the second switch (S 2 ) is zero, a substrate diode (D S2 ) of the second switch (S 2 ) conducts such that the current (i LX ) flowing through the inductor (L X ) and the current (i LP ) flowing through the first winding (L P ) flow to the clamp capacitor (C X ). Thus, the voltage (v S1 ) across the first switch (S 1 ) is clamped. When the duty cycle of the first switch (S 1 ) is represented by “d”, based on the voltage-second theorem, the voltage (v CX ) across the clamp capacitor (C X ) is determined according to the following Equation 2:
 
ν CX   =V   IN   d /(1 −d )  (Equation 6)
 
According to the Equations 5 and 6, a maximum value of the voltage (v S1 ) across the first switch (S 1 ) is represented as follows:
 
ν S1   =V   IN +ν CX   =V   IN /(1 −d )  (Equation 7)
 
     Since energy attributed to the leakage inductance (L K1 ) of the first winding (L P ) is released, the current (i LS ) flowing through the first winding (L P ) decreases to zero at t 3  (see  FIG. 5   c ). The voltage (v LS ) across the second winding (L S ) is represented as follows:
 
ν LS   =NV   IN   d /(1 −d )  (Equation 8)
 
     The current (i LS ) flowing through the second winding (S 2 ) is reversed and gradually increases such that a parasitic capacitance of the second diode (D Y ) of the boost unit  4  discharges and that a parasitic capacitance of the first diode (D W ) is charged. Therefore, the relationship among the voltage (v DW ) across the first diode (D W ), the voltage (v DY ) across the second diode (D Y ) and the voltage (v CY ) across the first capacitor (C Y ) is determined according to the following equation  9 :
 
ν DW +ν DY =ν CY   (Equation 9)
 
According to the Equation 3, the voltages (v DW , v DY ) across the first and second diodes (D W , D Y ) clamp each other, and each of the voltages (v DW , v DY ) across the first and second diodes (D W , D Y ) has a maximum value equal to v CY . In this case, a part of the current (i LS ) flowing through the second winding (L S ) flows through the output capacitor (C O ) and substrate diodes (D T4′ , D T1′ ) of the switches (T 4 , T 1 ) such that parasitic capacitances of the diodes (D 4 , D 1 ) are charged with a small amount of current. Thus, the diodes (D 4 , D 1 ) become cut off. During the third mode, the first and second diodes (D Y , D W ) and the diodes (D 1 , D 2 , D 3 , D 4 ) have a very small reversed recovery current as a result of the leakage inductance (L k2 ).
 
     Referring to  FIGS. 5   a  to  5   i , and  9 , the boost unit  4  is operated in the fourth mode during a period from t 3  to t 4 . In the fourth mode, the first switch (S 1 ) is in the OFF-state, the second switch (S 2 ) is in the ON-state, and the second diode (D Y ) conducts. The current (i LP ) flowing through the first winding (L P ) decreases to zero at t 3 , and then reversely increases. In this case, the clamp capacitor (C X ) discharges through the second switch (S 2 ). The current (i CX ) flowing through the clamp capacitor (C X ) and the exciting current (i LM ) reversely flow to the first winding (L P ). Thus, the induced voltage (v LS ) across the second winding (L S ) is equal to N times the voltage (v CX ) across the clamp capacitor (C X ), and the first capacitor (C Y ) is charged through the second diode (D Y ) with the induced voltage (v LS ) across the second winding (L S ) and the voltage (v CW ) across the second capacitor (C W ). Referring to the Equations 2 and 5, the voltage (v CY ) across the first capacitor (C Y ) is determined according to the following Equation 10:
 
ν CY =ν LS +ν CW   =NV   IN /(1 −d )−2 NV   k1   (Equation 10)
 
According to the Equation 3, the voltages (v D1 , v D4 ) across the diodes (D 1 , D 4 ) are determined according to the following Equation 11:
 
ν D1 +ν D4 =ν O −ν CW   −NV   IN   (Equation 11)
 
     Referring to  FIGS. 5   a  to  5   i , and  10 , the boost unit  4  is operated in the fifth mode during a period from t 4  to t 5 . In the fifth mode, the first and second switches (S 1 , S 2 ) are in the OFF-state, and the second diode (D Y ) conducts. The parasitic capacitance of the second switch (S 2 ) is charged and the parasitic capacitance of the first switch (S 1 ) discharges. When the parasitic capacitance of the first switch (S 1 ) discharges to zero, the substrate diode (D S1 ) of the first switch (S 1 ) conducts such that the voltage (v S2 ) across the second switch (S 2 ) is clamped to V IN +v CX . Therefore, the second switch (S 2 ) has the same clamp voltage as that of the first switch (S 1 ). 
     Referring to  FIGS. 5   a  to  5   i , and  11 , the boost unit  4  is operated in the sixth mode during a period from t 5  to t 6 . In the sixth mode, the first switch (S 1 ) is switched from the OFF-state to the ON-state, the second switch (S 2 ) is in the OFF-state, and the second diode (D Y ) conducts. When the first switch (S 1 ) is switched from the OFF-state to the ON-state, due to the leakage inductance (L k1 ), an inrush current can be avoided. Therefore, the current (i LP ) flowing through the first winding (L P ) cannot become positive at once such that the second winding (L S ) is operated as in the fifth mode. Energy attributed to the exciting inductance (L M ) decreases and is released to the second winding (L S ). Since the substrate diode (D S1 ) of the first switch (S 1 ) still conducts, as shown in  FIG. 5   e , the first switch (S 1 ) has zero-voltage switching characteristics during transformation from the OFF-state to the ON-state. 
     Referring to  FIGS. 5   a  to  5   i , and  12 , the boost unit  4  is operated in the seventh mode during a period from t 6  to t 7 . In the seventh mode, the first switch (S 1 ) is in the ON-state and the second switch (S 2 ) is in the OFF-state. When the current (i LP ) flowing through the first winding (L P ) has an amplitude equal to that of the exciting current (i LM ) of the transformer (T r ), the first winding (L P ) receives energy again such that the current (i LS ) flowing through the second winding (L S ) linearly increases. At the same time, the voltage across the exciting inductance (L M ) is induced to the second winding (L S ) through the first winding (L P ) such that the current flowing through the second winding (L S ) reversely increases again. In this case, the parasitic capacitances of the first diode (D W ) and the diodes (D 1 , D 4 ) discharge, and the parasitic capacitance of the second diode (D Y ) is charged. 
     When the parasitic capacitances of the first diode (D W ) and the diodes (D 1 , D 4 ) discharge to zero, the first diode (D W ) and the diodes (D 1 , D 4 ) conduct such that the output capacitor (C O ) and the second capacitor (C W ) are charged through the diodes (D 1 , D 4 ) with the current flowing through the second winding (L S ). Charging paths are the same as that of the first mode. When the exciting current of the transformer (T r ) gradually increases, the induced current flowing through the second winding (L S ) gradually decreases, and then, the boost unit  4  returns to the first mode. 
     According to the Equations 3 and 10, the output voltage (v O ) is represented as follows: 
                     v   O     =         v   CW     +     v   CY       =         NV   IN     ⁢       (     2   -   d     )       (     1   -   d     )         -     4   ⁢     Nv     k   ⁢           ⁢   1                     (     Equation   ⁢           ⁢   12     )               
Thus, a voltage gain (G V ) of the power converting device is represented as follows:
 
                     G   V     =              v   O            V   IN       =       N   ⁢       (     2   -   d     )       (     1   -   d     )         -       4   ⁢     Nv     k   ⁢           ⁢   1           V   IN                   (     Equation   ⁢           ⁢   13     )               
where 0≦d&lt;1 such that
 
             N   ⁢       (     2   -   d     )       (     1   -   d     )             
is greater than 2N.
 
     According to the Equation 13, by appropriately selecting d and v k1 , the voltage gain (G V ) of less than one can be obtained. Therefore, the power converting device of the present invention can further provide step-down function. 
     When the power converting device is in a step-down operation, referring to  FIGS. 13   a  and  13   b , if the external power source, such as a solar cell unit, provides the current (i IN ) during the ON-state of the first switch (S 1 ), i AVG  represents an average current during one cycle. V O  and I O  represent effective values of the voltage across the output capacitor (C O ) and the current flowing through the output capacitor (C O ), respectively. R represents an impedance of a load (not shown). P IN  and P O  represent input and output powers, respectively. η represents a power transformation efficiency of the power converting device. As a result, P IN ·η=P O . To simplify analysis, assuming η=1, the relationship between the input and output powers (P IN , P O ) is represented as follows:
 
P IN =P O   (Equation 14)
 
 V   IN   ·i   AVG   =V   O   ·I   O   =V   O   2   /R   (Equation 15)
 
Since the second switch (S 2 ) is in the OFF-state, i AVG =i LP . Therefore, the Equation 15 can be represented as follows:
 
                       V   IN     ·       d   ·     i   P       2       =       V   O   2     R             (     Equation   ⁢           ⁢   16     )               
where i P  is a maximum value of i LP . Thus, i P  can be represented as follows:
 
                     i   P     =       2   ·     V   O   2         R   ·     V   IN     ·   d               (     Equation   ⁢           ⁢   17     )               
Referring to the Equation 4, v k1  can be represented as follows:
 
                     v     k   ⁢           ⁢   1       =         L     k   ⁢           ⁢   1       ⁢       Δ   ⁢           ⁢     i   P         d   ⁢           ⁢   t         =       2   ·       L   1     ⁡     (     1   -   k     )       ·     V   O   2         R   ·     V   IN     ·     d   2     ·   T                 (     Equation   ⁢           ⁢   18     )               
where T is a period of one cycle of v GS1 , i.e., a reciprocal of the switching frequency (f S ) of the first switch (S 1 ). The Equation 18 is introduced into the Equation 13, the voltage gain (G V ) of the power converting device can be represented as follows:
 
                     G   V     =         v   O       V   IN       =       N   ⁢       (     2   -   d     )       (     1   -   d     )         -     8   ⁢   N   ⁢           L   1     ⁡     (     1   -   k     )       ·     V   O   2     ·     f   S         R   ·     V   IN   2     ·     d   2                       (     Equation   ⁢           ⁢   19     )               
Then, the Equation 20 can be determined as follows:
 
                           8   ⁢     N   ·       L   1     ⁡     (     1   -   k     )       ·     f   S           R   ·     d   2         ·     G   V   2       +     G   V     -       N   ⁡     (     2   -   d     )         (     1   -   d     )         =   0           (     Equation   ⁢           ⁢   20     )               
In the Equation 20, assuming that
 
             a   =       8   ⁢     N   ·       L   1     ⁡     (     1   -   k     )       ·     f   S           R   ·     d   2                     b   =   1                 c   =     -       N   ⁡     (     2   -   d     )         (     1   -   d     )           ,         
since G V &gt;0, the Equation 20 has a solution of G V  as follows:
 
     
       
         
           
             
                 
             
             ⁢ 
             
               
                 
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                           32 
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       FIG. 14  illustrates experimental results of power transformation efficiency (η) of the power converting device of the preferred embodiment operated under a condition, where the DC voltage input (V IN ) is 18 volts. As shown in  FIG. 14 , the power converting device has maximum power transformation efficiency (η) over 92%. 
     The following are some of the advantages attributed to the power converting device of the present invention: 
     1. The first and second switches (S 1 , S 2 ), the first and second diodes (D W , D Y ), and the diodes (D 1 , D 2 , D 3 , D 4 ) have soft switching characteristics. 
     2. Due to the presence of the transformer (T r ), the power converting device of the present invention has electrical isolation capability. 
     3. The power converting device of the present invention has relatively high power transformation efficiency. 
     While the present invention has been described in connection with what is considered the most practical and preferred embodiment, it is understood that this invention is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.