Patent Publication Number: US-11641162-B2

Title: Circuits and methods for generating a supply voltage for a switching regulator

Description:
BACKGROUND 
     In some integrated circuits, such as pulse width modulation controllers, internal power supplies are preferred. The internal power supply is sometimes referred to as a self-supply. The internal power supply generates power to operate the circuits and components within the integrated circuits and may be a voltage converter or a plurality of voltage converters that convert a voltage to at least one voltage used by the integrated circuit. 
     Some integrated circuits are used to control a flyback converters or the like. For example, the integrated circuits may control flyback converters used in pulse width modulation controllers. The flyback converters are not presently suitable as a source for an internal power supply. Flyback converters and similar circuits have a high voltage component, such as a switch supplying a current source that is connected either to a DC bulk high voltage node or to a high voltage drain switching node. The high voltage component has to source an average current equal to the power consumption in the integrated circuit and has a voltage drop almost equal to the DC bulk high voltage. 
     The amount of power dissipation for the high voltage component is a problem when it is internal to the integrated circuit. In some embodiments, the power dissipation is the sum of the power dissipation of the high voltage component and a high voltage MOSFET that may be used for power generation within the integrated circuit. In order to reduce the power dissipated by the MOSFET, the on resistance of the MOSFET could be reduced. Alternatively, a larger integrated circuit package with a low thermal resistance could be used. Both solutions increase the cost of the integrated circuit. 
     SUMMARY 
     Circuits and methods for converting a current to an output voltage are disclosed herein. An embodiment of the circuit includes a first switch connected between a source of current and a first node and a second switch connected between the first node and a common voltage. The circuit also includes a first controller for controlling the state of the first switch and a second controller for controlling the state of the second switch. A capacitor is coupled to the first node; the voltage on the capacitor is the output voltage. When the second switch is open, the capacitor charges, and when the second switch is closed, the capacitor does not charge. The current flows through the primary inductance of a transformer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic diagram of a circuit for providing internal power for an integrated circuit. 
         FIGS.  2 A- 2 F  are graphs showing voltages and currents at different locations in the circuit of  FIG.  1   . 
         FIG.  3    is an alternate embodiment of the circuit of  FIG.  1   . 
         FIG.  4    is an alternate embodiment of the circuit of  FIG.  1   . 
         FIG.  5    is an alternate embodiment of the circuit of  FIG.  1   . 
         FIG.  6    is an alternate embodiment of the circuit of  FIG.  1   . 
         FIG.  7    is a flow chart describing an embodiment of the operation of the circuit of  FIG.  1   . 
     
    
    
     DETAILED DESCRIPTION 
     Circuits and methods for providing an internal power supply or self-supply are described herein. The circuits and methods described herein are related to pulse width modulation (PWM) control circuits and are used herein for illustration purposes. It is to be noted that the circuits and methods described herein may be applied to circuits other than pulse width modulation circuits. 
     Reference is made to  FIG.  1   , which is a schematic illustration of a circuit  10  for generating an output voltage, VCC. The voltage VCC is used as a self-supply voltage for the circuit  10 . The circuit  10  may be located within an integrated circuit  102 , wherein the voltage VCC is used to power the integrated circuit  102 . The integrated circuit  102  may include a pulse width modulation (PWM) controller, not shown, that controls a flyback transformer T 1 . The transformer T 1  may be external to the integrated circuit  102 . The transformer T 1  has a primary side  106  and a secondary side  107 . The primary side  106  of the transformer T 1  is connected to a voltage source V 1 , which may be a high voltage source. The primary side  106  of the transformer T 1  is sometimes referred to as the primary winding magnetization inductance or the primary inductance. The secondary side  107  of the transformer T 1  may be connected to components, such as light-emitting diodes or generic loads that are controlled by use of PWM. The integrated circuit  102  controls the PWM, which controls the power delivered to the loads connected to the secondary side  107  of the transformer T 1 . 
     The circuit  10  includes a first switch Q 1  and a second switch Q 2  that are connected in series at a node N 1 . In the embodiment of  FIG.  1   , the switches Q 1 , Q 2  are metal oxide semiconductor field effect transistors (MOSFETs) and may be referred to as the FET Q 1  and the FET Q 2 . It is noted devices other than the MOSFETs, such as other types of transistors, may be used for the switches Q 1  and Q 2 . The drain of the FET Q 1  is connected to the primary side  106  of the transformer T 1 . The source of the FET Q 1  is connected to the drain of the FET Q 2  at the node N 1 . The source of the FET Q 2  is connected to ground. The configuration of the FET Q 1  is used as a switched bootstrap cascode with the FET Q 2 . The current flow in the FET Q 1  is sometimes referred to as the drain current I D . 
     The node N 1  is also connected to a switch SW 1 . The circuit  10  uses the switch SW 1  to allow current to flow in one direction as described below. The other side of the switch SW 1  is connected to a capacitor C 1 , which is connected to ground. The voltage across the capacitor C 1  is the output voltage VCC. The switch SW 1 , which is at the potential of the output voltage, is connected to control logic  130 , which can monitor the voltage VCC. The circuit  10  also includes two drivers, which are referred to as a first driver  12  and a second driver  14 . Both drivers  12 ,  14  receive input signals from the control logic  130 . The output of the first driver  12  is connected to the gate of the FET Q 1  and the output of the second driver  14  is connected to the gate of the FET Q 2 . The control logic  130  controls the gate voltages and currents through the FETs Q 1  and Q 2  in addition to the state of the switch SW 1 . Therefore, the control logic  130  can monitor and set the output voltage VCC by switching the states of the FETs Q 1  and Q 2 . 
     Having described the circuit  10 , its operation will now be described. In summary, the FET Q 1  is used to charge the capacitor C 1 , wherein the voltage on the capacitor C 1  is the output voltage VCC. The FET Q 1  is used as a switched bootstrap cascode with the FET Q 2 . By selectively turning on and turning off the FETs Q 1  and Q 2  the primary winding magnetization inductance of the transformer T 1  can be charged along with the capacitor C 1 . The drivers  12  and  14  control the current flow through the FETs Q 1  and Q 2  so as to control the charging of the capacitor C 1 . 
     The operation of the circuit  10  will now be described in more detail. The FETs Q 1  and Q 2  have internal capacitance between their gates and sources. When the FETs Q 1  and Q 2  are on, their gate-to-source capacitances are charged to the VCC voltage. In addition, the current in the FET Q 1 , referred to as the drain current I D , charges the primary side  106  of the transformer T 1 , which is also referred to as the primary inductance. As the drain current I D  reaches a peak threshold established by the control law of the circuit  10  as a function of a load connected to secondary side  107  of the transformer T 1 , the FET Q 2  is turned off while the FET Q 1  is on. In this configuration, the gate-to-source capacitance, which was previously charged to VCC voltage, is shifted upwards. Therefore, the source voltage of the FET Q 1  is clamped to VCC and the drain current I D  is switched to charge the capacitor C 1  by way of closing the switch SW 1 . 
     Because the FET Q 1  is still on, the drain voltage is low, so the voltage from the source V 1  drops across the primary side  106  of the transformer T 1 . Therefore, the capacitor C 1  is charged without any additional power dissipation from the source V 1 , which significantly improves the efficiency for generating the voltage VCC. The drain current I D  charges the capacitor C 1  for a time window when the FET Q 2  is turned off. Then, the FET Q 2  is turned on again and the source voltage of the FET Q 1  goes low again. At this point the FET Q 1  is turned off to control the slope of the drain voltage through the gate current by means of the first driver  12 , or the current output by the first driver  12 , which improves the electromagnetic interference (EMI) performance of the circuit  100 . Therefore, the circuit  10  provides for drain slope control to reduce EMI in addition to providing self supply for the integrated circuit  102 . 
     A more detailed operation of the circuit  10  is provided below with reference to  FIGS.  2 A- 2 F , which are graphs showing voltages at different nodes within the circuit  10 . Three modes of operation of the circuit  10  will be described, a turn-on transient mode, a self-supply mode, and a turn-off transient mode. The three modes are part of a cycle that the circuit  10  uses during its operation. The graphs  2 A- 2 F have three times noted, t1, t2, and t3. The time t1 is the beginning of the turn-on transient mode, t2 is the beginning of the self-supply mode, and t3 is the beginning of the turn-off transient mode.  FIG.  2 A  shows the voltage on the gate of the FET Q 1 .  FIG.  2 B  shows the voltage on the source of the FET Q 1 .  FIG.  2 C  shows the drain voltage on the FET Q 1 ,  FIG.  2 D  shows the voltage on the gate of the FET Q 2 .  FIG.  2 E  shows the drain current I D .  FIG.  2 F  shows the current through the capacitor C 1 . 
     During the turn-on transient mode (sometimes referred to as the first mode), which occurs at time t1, the FET Q 2  is on and the FET Q 1  is turned on as shown by the graphs of  FIGS.  2 A and  2 D . More specifically, the high voltage on the gates indicates that the FETs Q 1  and Q 2  are on. Therefore, the drain voltage slope, as shown by the graph of  FIG.  2 C , is controlled by the first driver  12 . Controlling the drain voltage slope reduces the EMI of the circuit  10  by attenuating transients. The first driver  12  forces a current through the gate and to the source of the FET Q 1 . The current continues through the FET Q 2  to ground. During on the turn-on transient mode, from time t1 to time t2, the slope of the drain current depends on the voltage output by the voltage source V 1  and the primary inductance of the transformer T 1 . The slope of the drain current may be equal or proportional to the ratio of the voltage of the source V 1  and the inductance of the primary side  106  of the transformer T 1 . 
     During the self-supply mode (sometimes referred to as the second mode), which occurs at time t2, the FET Q 2  is turned off, as shown in  FIG.  2 D . The gate-source capacitance in the FET Q 1  acts as a bootstrap that allows the gate voltage on the FET Q 1  to reach a value that is greater than the voltage VCC. The voltage between t2 and t3 on  FIG.  2 A  is greater than VCC. For example, the gate voltage may rise to twice the voltage VCC. Because the FET Q 2  is off, the drain current I D  passes through the capacitor C 1 , which charges the capacitor C 1  as shown in  FIG.  2 F . The source voltage on the FET Q 1  is clamped to VCC. It follows that the gate-source voltage of the FET Q 1  is equal to VCC. 
     During the turn-off transient mode (sometimes referred to as the third mode), which occurs at t3, the FET Q 2  is turned on as shown in  FIG.  2 D . This causes the gate-source capacitance voltage on the FET Q 1  to be shifted toward ground as shown in  FIG.  2 B . Then the FET Q 1  is turned off, and in this situation, the slope of the drain voltage across the FET Q 1  is controlled by the first driver  12 . The result is the decreasing drain current I D  shown in  FIG.  2 E . 
     The circuit  10  provides the voltage VCC and power for the integrated circuit  102  by using the current driving the primary side  106  of the transformer T 1 . By using the driving current, no bias winding is required from the transformer T 1 . It is noted that while the primary side  106  of the transformer T 1  has been described as the source of current or part of the source of current for the circuit  10 , other sources of current could be used. In addition, the generation of the voltage VCC does not require any additional power dissipation from the voltage source V 1  that supplies the transformer T 1 . A further advantage to the circuit  10  is that the drain slope can be controlled during the switching transients as shown by the graph in  FIG.  2 E . Therefore, EMI can be attenuated during the switching between operating modes of the circuit  10 . 
     The circuit  10  of  FIG.  1    shows the use of the first and second drivers  12  and  14  to control the drain current I D  and the charging of the capacitor C 1 . The charge on the capacitor C 1  is the output voltage VCC. A more discrete version of the circuit  10  is shown by the circuit  100  of  FIG.  3   . The circuit  100  includes the FET Q 1  and the FET Q 2 . The node N 1  is connected to the anode of a diode D 1 . The circuit  100  uses the diode D 1  as a switch, similar to the manner in which the switch SW 1  of  FIG.  1    is used, to enable current to flow in one direction. The cathode of the diode D 1  is connected to the capacitor C 1 . The cathode of the diode D 1  is connected to a first current source I 1 , which, as described below, is used to control the slope of the drain voltage of the FET Q 1  during the turn on and turn off transients. The first current source I 1  is connected to a switch SW 3 , which is connected to a node N 2 . The node N 2  connects to the gate of the FET Q 1  and to a switch SW 4 . The switch SW 4  is connected to a second current source I 2 , which is connected to ground. 
     The gate of the FET Q 2  is connected to the control logic  130  by way of the second driver  14 . The control logic  130  may also control the state of the switches SW 3  and SW 4 . The combination of the current sources I 1  and I 2  and the combination of the switches SW 3  and SW 4  constitute one possible embodiment of the first driver  12 ,  FIG.  1   , in discrete form. In addition to the components described above, the circuit  100  may include voltage measuring devices to measure voltages at specific locations in the circuit  100 , including the voltage VCC. 
     Having described an embodiment of the circuit  100 , other embodiments using discrete or integrated components will now be described. Reference is made to  FIG.  4   , which shows an alternative embodiment of the circuit  100  of  FIG.  3   . The diode D 1  of  FIG.  3    has been replaced by the switch SW 1  that is controlled by the control logic  130 . During the self-supply mode, the control logic  130  closes the switch SW 1  so that the capacitor C 1  can charge. In some embodiments, the switch SW 1  is closed when the source voltage of the FET Q 2  reaches the VCC voltage. During the turn-off transient mode, the switch SW 1  is opened in order to prevent the capacitor C 1  from discharging within the circuit  100 . 
       FIG.  5    is an embodiment of the circuit  100  of  FIG.  3    wherein the current sources I 1  and I 2  have been replaced by a resistor R 1 . The resistor R 1  is located between the node N 2  and the gate of the FET Q 1 . During the turn-on transient mode, the switch SW 3  is closed, so the drain slope is controlled by the value of the resistor R 1 . More specifically, the current through the gate of the FET Q 1  is controlled by the value of the resistor R 1 , which controls the slope of the drain voltage during switching transients. Accordingly, the resistor R 1  acts as a current control or source. During the turn-off transient mode, the switch SW 4  is closed, so the drain slope is again controlled by the value of the resistor R 1 . It is noted that resistors could be placed in series with the switches SW 3  and SW 4  in order to provide more flexibility in controlling the drain slope during the transient modes. 
     Another embodiment of the circuit  100  of  FIG.  3    is shown in  FIG.  6   . The circuit  100  of  FIG.  6    has the current sources I 1  and I 2  removed. Therefore, the FET Q 1  is turned off and on directly by the status of the switches SW 3  and SW 4 . 
     The operation of the circuit  10  is summarily described by the flow chart  200  of  FIG.  7   . The operation commences at step  202  with operating the circuit  10  in the first mode wherein the current I D  passes through the first switch Q 1  and the second switch Q 2  that are connected in series. The switches Q 1 , Q 2  are connected at a node N 1 . The current I D  increases during the first mode. The operation continues at step  204  with operating the circuit  10  in the second mode, wherein the second switch Q 2  is turned off and current flows through the first switch Q 1  and into the capacitor C 1 . The voltage on the capacitor C 1  is the output voltage. The operation continues at step  206  with operating the circuit  10  in a third mode, wherein the current is regulated by the first switch Q 1 , and wherein the current decreases during the third mode. 
     While illustrative and presently preferred embodiments of the invention have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed and that the appended claims are intended to be construed to include such variations except insofar as limited by the prior art.