Patent Publication Number: US-7215164-B2

Title: Capacitance multiplier with enhanced gain and low power consumption

Description:
BACKGROUND OF THE INVENTION 
   This application claims priority to Korean Patent Application No. 2004-43670 filed on Jun. 14, 2004 in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. 
   1. Field of the Invention 
   The present invention relates generally to a capacitance multiplier, and in particular to a capacitance multiplier with cascaded current amplifiers for enhanced capacitance gain and low power consumption. 
   2. Description of the Related Art 
   A PLL (Phase Locked Loop) is commonly used for communication, multimedia, and other applications.  FIG. 1  is a block diagram of a conventional PLL (Phase Locked Loop). Referring to  FIG. 1 , the PLL includes a PFD (Phase Frequency Detector)  100 , a charge pump  200 , a loop filter  300 , a VCO (voltage controlled oscillator)  400 , and a frequency divider  500 . 
   The PFD  100  generates an up signal SUP and/or a down signal SDN based on a phase (and frequency) difference between a reference signal SIN and a feedback signal SFEED. The charge pump  200  outputs an output signal having a level corresponding to a state of the up signal SUP and/or the down signal SDN. 
   After high frequency components of the output signal of the charge pump  200  are removed by the loop filter  300 , the filtered output signal VFILT is sent to the VCO  400 . The VCO  400  outputs a high frequency signal SO having a frequency corresponding to a direct current (DC) level of the signal VFILT. 
   The divider  500  generates a low frequency feedback signal SFEED based on the output signal SO from the VCO  400 . The feedback signal SFEED is fed back to the PFD  100 . When the PLL is locked, the output signal SO of the VCO  400  is used for synchronizing the phase of signals in various parts of a circuit. 
     FIG. 2  shows a circuit diagram of the charge pump  200  and the loop filter  300  in the PLL of  FIG. 1 . Referring to  FIG. 2 , the charge pump  200  includes an inverter  210  for inverting the up signal SUP, a PMOSFET (P-channel metal oxide semiconductor field effect transistor) MP 1  having a source coupled to a high power supply VDD, a gate coupled to an output of the inverter  210 , and a drain having the signal VFILT generated thereon. The charge pump  200  also includes an NMOSFET (N-channel metal oxide semiconductor field effect transistor) MN 1  having a drain coupled to the drain of the PMOSFET MP 1 , a gate having the down signal SDN applied thereon, and a source coupled to a low power supply VSS. The low power supply VSS may have a negative voltage or a ground voltage. 
   The loop filter  300  includes a resistor RLF 1  having one end coupled to the drain of the NMOSFET MN 1 , a first capacitor CLF 1  coupled between the other end of the resistor RLF 1  and the low power supply VSS, and a second capacitor CLF 2  coupled between the drain of the NMOSFET MN 1  and the low power supply VSS. When the loop filter  300  is implemented within a semiconductor chip, the first capacitor CLF 1  disadvantageously occupies a large area. Thus, it is desired to reduce the size of the first capacitor CLF 1 . 
     FIG. 3  shows a circuit diagram illustrating a basic principle of a capacitance multiplier. Referring to  FIG. 3 , (a) is a circuit diagram of a capacitance multiplier, and (b) is an AC equivalent circuit of the circuit of (a) seen from a node A. 
   In the circuit of (a), NMOSFETs MN 2  and MN 3  form a current mirror with a ratio of sizes (Width/Length) of the NMOSFETs MN 2  and MN 3  being 1:M. A current flowing through the capacitor C 1  is substantially the current I flowing through the NMOSFET MN 2 , and a current flowing through a drain of the NMOSFET MN 3  is M times the current I flowing through the NMOSFET MN 2 . 
   An input impedance at the node A is represented by the following expression 1: 
                 Z   =         υ   ⁢           ⁢   in       i   ⁢           ⁢   in       =     1     sC1   ⁡     (     1   +   M     )                   〈     Expression   ⁢           ⁢   1     〉               
Accordingly, an input capacitance at the node A is (1+M)C 1  that is scaled up by a scale factor of M.
 
     FIG. 4  is a circuit diagram of a conventional capacitance multiplier as disclosed in IEEE Journal of Solid-State Circuits, titled “A 2.4 GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase Switching Prescaler and Loop Capacitance Multiplier”. An input admittance of the circuit of  FIG. 4  is represented by the following expression 2: 
   
     
       
         
           
             
               
                 Y 
                 = 
                 
                   
                     
                       i 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       in 
                     
                     
                       υ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       in 
                     
                   
                   = 
                   
                     
                       g 
                       OA 
                     
                     + 
                     
                       s 
                       ⁡ 
                       
                         ( 
                         
                           Cp2 
                           + 
                           
                             
                               ( 
                               
                                 M 
                                 + 
                                 1 
                               
                               ) 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             Ci 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               
                                 1 
                                 + 
                                 
                                   s 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     Cp1 
                                     
                                       
                                         ( 
                                         
                                           M 
                                           + 
                                           1 
                                         
                                         ) 
                                       
                                       ⁢ 
                                       gm1 
                                     
                                   
                                 
                               
                               
                                 1 
                                 + 
                                 
                                   s 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     
                                       Ci 
                                       + 
                                       Cp1 
                                     
                                     gm1 
                                   
                                 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
             
             
               
                 〈 
                 
                   Expression 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
                 〉 
               
             
           
         
       
     
   
   In the expression 2, Cp 1  and Cp 2  are the capacitances of parasitic capacitors at the nodes A and B, respectively, and gm 1  denotes a transconductance of the NMOSFET MN 13 . g OA  denotes a total conductance at the node A, and M denotes a current gain of a current mirror. 
     FIGS. 5A and 5B  are graphs showing a frequency response of the input impedance of the circuit of  FIG. 4 .  FIG. 5A  shows a magnitude of the input impedance of the circuit of  FIG. 4 , and  FIG. 5B  shows a phase of the input impedance of the circuit of  FIG. 4 . Dotted lines in  FIGS. 5A and 5B  represent graphs illustrating an ideal frequency response. 
   Referring to  FIGS. 5A and 5B , the circuit of  FIG. 4  may be used as a capacitance multiplier in the range of a frequency greater than fc 1  and a frequency less than fc 2 . The fc 1  and fc 2  are represented by the following expression 3: 
                         fc1   =       g   OA       2   ⁢           ⁢     π   ⁡     (     M   +   1     )       ⁢           ⁢   Ci         ,           fc2   =     gm1     2   ⁢           ⁢   π   ⁢           ⁢   Ci                     〈     Expression   ⁢           ⁢   3     〉               
fc 1  is designed to be as small as possible for preventing a decrease in the DC gain of the PLL. In particular, g OA  is desired to be small.
 
   In order to maintain a phase margin of the PLL, fc 2  is desired to be larger than a zero frequency of the loop filter. Therefore, the value of gm 1  and thus the level of current flowing through the NMOSFET MN 13  are determined depending on an operating frequency of the loop filter. 
   For obtaining a large capacitance gain in the circuit of  FIG. 4  with a large scale factor (M), the NMOSFET MN 14  has current that is M times a current flowing through the NMOSFET MN 13 . Accordingly, the power consumption of the capacitance multiplier of  FIG. 4  increases with the scale factor M. Thus, the scale factor (M) is limited to about 20 in an actual application for acceptable power consumption. 
   Thus, a capacitance multiplier is desired with higher capacitance gain but with low power consumption. 
   SUMMARY OF THE INVENTION 
   Accordingly, a capacitance multiplier of the present invention occupies a smaller area with higher capacitance gain but with low power consumption. 
   In a general aspect of the present invention, a capacitance multiplier includes a cascade of a plurality of current amplifiers with each current amplifier having a respective current gain Ki. In addition, the capacitance multiplier includes a capacitor coupled in parallel across the cascade of current amplifiers. 
   In one embodiment of the present invention, each current amplifier is comprised of at least one current mirror transistor pair having a size ratio of 1:Ki. In another embodiment of the present invention, each current amplifier is comprised of transistors coupled as a plurality of inverters. 
   In an example embodiment of the present invention, each current amplifier includes a first PMOSFET (P-channel metal oxide semiconductor field effect transistor) having a source coupled to a high power supply, and a gate and a drain coupled together to a first node. In addition, a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) has a source coupled to a low power supply, and a gate and a drain coupled together to the first node. Furthermore, a second PMOSFET has a source coupled to the high power supply and a gate coupled to the first node. Additionally, a second NMOSFET has a drain coupled to a drain of the second PMOSFET, a gate coupled to the first node, and a source coupled to the low power supply. In that case, a size of the second PMOSFET is Ki times a size of the first PMOSFET, and a size of the second NMOSFET is Ki times a size of the first NMOSFET. 
   In another embodiment of the present invention, each current amplifier is comprised of a plurality of cascoded transistors. In an example embodiment of the present invention, each current amplifier includes a first PMOSFET having a source coupled to a high power supply, a gate coupled to a first node, and a drain coupled to a second node. In addition, a second PMOSFET has a source coupled to the high power supply and a gate coupled to the first node. Furthermore, a third PMOSFET has a source coupled to the second node and a gate coupled to a third node. Additionally, a fourth PMOSFET has a source coupled to a drain of the second PMOSFET and a gate coupled to the third node. 
   Also, a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) has a drain coupled to a drain of the third PMOSFET, a gate coupled to the second node, and a source coupled to the third node. Furthermore, a second NMOSFET has a drain coupled to a drain of the fourth PMOSFET and a gate coupled to the second node. In addition, a third NMOSFET has a drain coupled to the third node, a gate coupled to the first node, and a source coupled to a low power supply. Furthermore, a fourth NMOSFET has a drain coupled to a source of the second NMOSFET, a gate coupled to the first node, and a source coupled to the low power supply. 
   In that case, a size of the second PMOSFET is Ki times a size of the first PMOSFET, a size of the fourth PMOSFET is Ki times a size of the third PMOSFET, a size of the second NMOSFET is Ki times a size of the first NMOSFET, and a size of the fourth NMOSFET is Ki times a size of the third NMOSFET. 
   In this manner, a capacitance gain of the capacitance multiplier is substantially a product of the respective current gains of the current amplifiers. Additionally, a total current dissipation of the capacitance multiplier is substantially a sum of currents flowing through each branch in the current amplifiers. Thus, the capacitance gain of the capacitance multiplier is increased with low power consumption. With such increased capacitance gain, the capacitance of the capacitor used in the capacitance multiplier may be reduced for decreased area. 
   The capacitance multiplier of the present invention is used to particular advantage within a loop filter of a phase locked loop. In that case, the capacitor has a node coupled to a charge pump of the phase locked loop. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features and advantages of the present invention will become more apparent when described in detailed exemplary embodiments thereof with reference to the attached drawings in which: 
       FIG. 1  shows a block diagram of a conventional PLL (Phase Locked Loop) of the prior art; 
       FIG. 2  shows a circuit diagram of a charge pump and a loop filter in the PLL of  FIG. 1 , according to the prior art; 
       FIG. 3  shows a circuit diagram illustrating a basic principle of a capacitance multiplier; according to the prior art; 
       FIG. 4  shows a circuit diagram of a conventional capacitance multiplier of the prior art; 
       FIGS. 5A and 5B  show graphs of a frequency response of an input impedance for the circuit of  FIG. 4 ; 
       FIG. 6  shows a block diagram of a capacitance multiplier, according to an embodiment of the present invention; 
       FIG. 7  shows a circuit diagram of a current amplifier included in the capacitance multiplier of  FIG. 6 , according to an embodiment of the present invention; 
       FIG. 8  shows a circuit diagram of a current amplifier included in the capacitance multiplier of  FIG. 6 , according to another embodiment of the present invention; 
       FIG. 9  shows a simulation graph of a frequency response of an input impedance of the capacitance multiplier of  FIG. 10 ; and 
       FIG. 10  shows a circuit diagram of an example capacitance multiplier of  FIG. 6  with a cascade of three current amplifiers, according to an example embodiment of the present invention. 
   

   The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number in  FIGS. 1 ,  2 ,  3 ,  4 ,  5 ,  6 ,  7 ,  8 ,  9 , and  10  refer to elements having similar structure and/or function. 
   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 6  shows a block diagram of a capacitance multiplier according to an embodiment of the present invention. Referring to  FIG. 6 , the capacitance multiplier includes a current amplifying circuit  600  and a capacitor Ci. The current amplifying circuit  600  includes a plurality of current amplifiers such as first, second, and nth current amplifiers  610 ,  620 , . . . , and  630 . 
   The current amplifiers  610 ,  620 , . . . , and  630  are cascaded in series, and each of the current amplifiers  610 ,  620 , . . . , and  630  has a respective current gain K 1 , K 2 , . . . , Kn. In addition, the capacitor Ci is coupled in parallel across the cascade of the current amplifiers  610 ,  620 , . . . , and  630 . 
     FIG. 7  shows a circuit diagram of a current amplifier included in the capacitance multiplier of  FIG. 6  according to an exemplary embodiment of the present invention. Referring to  FIG. 7 , the current amplifier includes PMOSFETs (P-channel metal oxide semiconductor field effect transistors) MP 21  and MP 22 , and NMOSFETs (N-channel metal oxide semiconductor field effect transistors) MN 21  and MN 22 . 
   The PMOSFET MP 21  has a source coupled to a high power supply VDD, and a gate and a drain coupled together at a node N 1 . The NMOSFET MN 21  has a gate and a drain coupled together at the node N 1 , and a source coupled to a low power supply VSS. For example, the low power supply VSS has a ground voltage or a negative voltage. 
   The PMOSFET MP 22  has a source coupled to the high power supply VDD and a gate coupled to the node N 1 . The NMOSFET MN 22  has a drain coupled to the drain of the PMOSFET MP 22 , a gate coupled to the node N 1 , and a source coupled to the low power supply VSS. 
   The operation of the capacitance multiplier is now explained with reference to the embodiments of  FIGS. 6 ,  7 , and  10 .  FIG. 10  shows an example implementation of the capacitance multiplier of  FIG. 6  with each of three current amplifiers  610 ,  620  and  630  being implemented similarly to the current amplifier of  FIG. 7 . Referring to  FIG. 10 , each of the current amplifiers  610 ,  620  and  630  has a respective current gain K 1 , K 2 , and K 3 . 
   For example in  FIG. 7 , NMOSFETs MN 21  and MN 22  form a current mirror, and PMOSFETs MP 21  and MP 22  form a current mirror. Additionally, transistors MP 21  and MN 21  are configured as an inverter, and transistors MP 22  and MN 22  are configured as another inverter. For a current gain of Ki in  FIG. 7 , a size (Width/Length) of the PMOSFET MP 22  is Ki times a size of the PMOSFET MP 21 . In addition, a size of the NMOSFET MN 22  is Ki times a size of the NMOSFET MN 21 . 
   The capacitance multiplier of  FIGS. 6 and 10  is suitable for lower voltage applications since each of the amplifiers  610 ,  620 , and  630  is configured as inverters. Each of the amplifiers  610 ,  620 , and  630  includes two inverters since an AC amplified current having an inverted phase may be fed-back when only one inverter is used in each of the amplifiers  610 ,  620 , and  630 . 
   In the capacitance multiplier of  FIG. 10  with three amplifiers, the input admittance is represented by the following expression 4 with reference to the expression 2: 
   
     
       
         
           
             
               
                 Y 
                 = 
                 
                   
                     
                       i 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       in 
                     
                     
                       υ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       in 
                     
                   
                   = 
                   
                     
                       g 
                       OA 
                     
                     + 
                     
                       s 
                       ⁡ 
                       
                         ( 
                         
                           Cp2 
                           + 
                           
                             
                               ( 
                               
                                 
                                   K1 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   K2 
                                   ⁢ 
                                   
                                       
                                   
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                                   K3 
                                 
                                 + 
                                 1 
                               
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                             ⁢ 
                             
                                 
                             
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                             Ci 
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                                 1 
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                                   ⁢ 
                                   
                                     Cp1 
                                     
                                       
                                         ( 
                                         
                                           
                                             K1 
                                             ⁢ 
                                             
                                                 
                                             
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                                             K2 
                                             ⁢ 
                                             
                                                 
                                             
                                             ⁢ 
                                             K3 
                                           
                                           + 
                                           1 
                                         
                                         ) 
                                       
                                       ⁢ 
                                       gm1 
                                     
                                   
                                 
                               
                               
                                 1 
                                 + 
                                 
                                   s 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     
                                       Ci 
                                       + 
                                       Cp1 
                                     
                                     gm1 
                                   
                                 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
             
             
               
                 〈 
                 
                   Expression 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   4 
                 
                 〉 
               
             
           
         
       
     
   
   In the expression 4, Cp 1  and Cp 2  denote capacitances of parasitic capacitors at nodes A and B, respectively (as illustrated in  FIG. 10 ) 
   gm 1  denotes a sum of the transconductance of the transistor MN 21  and the transconductance of the transistor MP 21 . g OA  denotes a total conductance at the node A. K 1 , K 2 , and K 3  denote gains of each of the current amplifiers  610 ,  620 , and  630 , respectively. Each current gain is determined by a ratio of transistor sizes within the current amplifier. 
   Referring to the frequency response of  FIGS. 5A and 5B , fc 1  and fc 2  of the capacitance multiplier in  FIG. 10  are represented by the following expression 5: 
   
     
       
         
           
             
               
                 
                   
                     
                       
                         fc1 
                         = 
                         
                           
                             g 
                             OA 
                           
                           
                             2 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               π 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     K1 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     K2 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     K3 
                                   
                                   + 
                                   1 
                                 
                                 ) 
                               
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             Ci 
                           
                         
                       
                       , 
                     
                   
                   
                     
                       fc2 
                       = 
                       
                         gm1 
                         
                           2 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           π 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           Ci 
                         
                       
                     
                   
                 
               
             
             
               
                 〈 
                 
                   Expression 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   5 
                 
                 〉 
               
             
           
         
       
     
   
   An operable frequency range of the frequency multiplier according to an exemplary embodiment shown in  FIG. 10  has a similar range compared with that of a conventional circuit of  FIG. 4 . 
   In this manner, the frequency multiplier of  FIG. 10  has a capacitance gain with a scale factor that is a product of the gains of the current amplifiers (i.e., K 1 K 2 K 3 ). Thus, a relatively large capacitance is obtained by cascading the plurality of current amplifiers  610 ,  620 , and  630 . With such a large capacitance gain, the capacitance of the capacitor Ci may be reduced for smaller area of the capacitance multiplier. For example, the capacitor Ci is easily scaled up by 100 times. 
   On the other hand, the current dissipation in the capacitance multiplier of  FIGS. 6 and 10  is relatively low. For example, in the conventional capacitance multiplier of  FIG. 4 , the circuit has an entire current of (M+1)×I=101×I with the scale factor M being 100 and with a current I flowing through the MNOSMFET MN 13  in  FIG. 4 . 
   In contrast, in the capacitance multiplier of  FIG. 10 , when the current gains of the current amplifiers  610 ,  620 , and  630  are K 1 =2, K 2 =5, and K 3 =10, the capacitance multiplier has a scale factor K 1 ×K 2 ×K 3 =100. However, the current consumed in the capacitance multiplier of  FIG. 10  is (K 1 +K 2 +K 3 +3)×I=20×I, which is about ⅕ of the current consumed in the conventional circuit of  FIG. 4 . Alternatively, when K 1 =4, K 2 =5, and K 3 =5, the scale factor K 1 ×K 2 ×K 3  is 100, and the current consumption is just 17×I. 
     FIG. 8  shows a circuit diagram of a current amplifier included in the capacitance multiplier of  FIG. 6  according to another exemplary embodiment of the present invention. The current amplifier of  FIG. 8  includes a plurality of cascoded transistors for improved DC characteristic of the PLL having the capacitance multiplier. 
   Referring to  FIG. 8 , the current amplifier includes PMOSFETs MP 31 , MP 32 , MP 33  and MP 34 , and NMOSFETs MN 31 , MN 32 , MN 33  and MN 34 . The PMOSFETs MP 31  and MP 33  form a cascode of transistors, and the PMOSFETs MP 32  and MP 34  form a cascode of transistors. The NMOSFETs MN 31  and MN 33  form a cascode of transistors, and the NMOSFETs MN 32  and MN 34  form a cascode of transistors. 
   The PMOSFET MP 31  has a source coupled to a high power supply VDD, a gate coupled to a node N 2 , and a drain coupled to a node N 3 . The PMOSFET MP 33  has a source coupled to a node N 3 , a drain coupled a node N 2 , and a gate coupled to a node N 4 . 
   The NMOSFET MN 31  has a drain coupled to the node N 2 , a gate coupled to the node N 3 , and a source coupled to the node N 4 . The NMOSFET MN 33  has a drain coupled to the node N 4 , a gate coupled to the node N 2 , and a source coupled to a low power supply VSS. 
   The PMOSFET MP 32  has a source coupled to the high power supply VDD and a gate coupled to the node N 2 . The PMOSFET MP 34  has a source coupled to the drain of the PMOSFET MP 32  and a gate coupled to the node N 4 . The NMOSFET MN 32  has a drain coupled to the drain of the PMOSFET MP 34  and a gate coupled to the node N 3 . The NMOSFET MN 34  has a drain coupled to the source of the NMOSFET MN 32 , a gate coupled to the node N 2 , and a source coupled to the low power supply VSS. 
   For a current gain of Ki in  FIG. 8 , a size of the PMOSFET MP 33  is Ki times a size of the PMOSFET MP 31 , a size of the PMOSFET MP 34  is Ki times a size of the PMOSFET MP 32 . In addition, a size of the NMOSFET MN 33  is Ki times a size of the NMOSFET MN 31 , and a size of the NMOSFET MN 34  is Ki times a size of the NMOSFET MN 32 . The circuit of  FIG. 8  is self-biasing and does not need a bias circuit. Operation of the circuit in  FIG. 8  is similar to the operation of the current amplifier in  FIG. 7 , and thus a description of the operation of the circuit in  FIG. 8  is omitted. 
     FIG. 9  is a simulation graph illustrating a frequency response of the input impedance of the capacitance multiplier of  FIG. 10 . In order to implement a capacitance of 4.7 nF during simulation, Ci is set to 33.57 pF, K 1 =2, K 2 =5, and K 3 =14. The dotted line of  FIG. 9  represents an ideal frequency characteristic of the input impedance of the capacitance multiplier of  FIG. 10 , and the solid line represents the frequency characteristic of the input impedance for the capacitance multiplier of  FIG. 10 . 
   While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. For example, any numbers of elements or any circuit topologies as illustrated and described herein are by way of example only. 
   The capacitance multiplier of  FIG. 6  may be advantageously used within a loop filter of a phase locked loop. In that case, one node of the capacitor Ci is coupled to a charge pump of the phase locked loop. However, the capacitance multiplier of the present invention may also be used in any other applications requiring a large capacitance with reduced area and low power consumption.