Patent Publication Number: US-10325816-B2

Title: Structure and method for FinFET device

Description:
PRIORITY DATA 
     The present application is a continuation application of U.S. patent application Ser. No. 14/924,422, filed Oct. 27, 2015, which is a divisional application of U.S. patent application Ser. No. 14/458,484, filed Aug. 13, 2014, which claims priority to U.S. provisional patent application No. 61/984,475, filed on Apr. 25, 2014, each of which is hereby incorporated by reference in its entirety. 
    
    
     RELATED APPLICATION 
     This application is related to patent applications U.S. Ser. No. 13/740,373 filed on Jan. 14, 2013, as “Semiconductor Device and Fabricating the Same;” U.S. Ser. No. 13/902,322 filed on May 24, 2013, as “FinFET Device and Method of Fabricating Same;” U.S. Ser. No. 13/934,992 filed on Jul. 3, 2013, as “Fin Structure of Semiconductor Device;” and U.S. Ser. No. 14/155,793 filed on Jan. 15, 2014, as “Semiconductor Device and Formation Thereof,” the entire disclosures of which are hereby incorporated by reference. 
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. 
     Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor. Although existing FinFET devices and methods of fabricating FinFET devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read in association with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features in drawings are not drawn to scale. In fact, the dimensions of illustrated features may be arbitrarily increased or decreased for clarity of discussion. 
         FIG. 1  is a flow chart of an example method for fabricating a FinFET device in accordance with some embodiments. 
         FIG. 2A  is a diagrammatic perspective view of an example FinFET device undergoing processes in accordance with some embodiments. 
         FIG. 2B  is a cross-sectional view of an example FinFET device along the line A-A in  FIG. 2A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 3A  is a diagrammatic perspective view of an example FinFET device undergoing processes in accordance with some embodiments. 
         FIG. 3B  is a cross-sectional view of an example FinFET device alone the line A-A in  FIG. 3A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIGS. 4A and 4B  are diagrammatic perspective views of a FinFET device undergoing processes in accordance with some embodiments. 
         FIG. 5  is a cross-sectional view of an example FinFET device along the line A-A in  FIG. 4A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIGS. 6A and 6B  are diagrammatic perspective views of a FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 7A and 7B  are diagrammatic perspective views of a FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 8A-8B and 9  are cross-sectional views of an example FinFET device along the line B-B in  FIG. 7B  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIGS. 10A and 10B  are diagrammatic perspective views of a FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 10C and 10D  are cross-sectional views of an example FinFET device along the line A-A in  FIG. 10A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 10E  is a cross-sectional view of an example FinFET device along the line B-B in  FIG. 10B  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIGS. 11A and 11B  are diagrammatic perspective views of a FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 12A and 12B  are diagrammatic perspective views of a FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 13A and 13B  are diagrammatic perspective views of a FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 13C, 13D and 13G  are cross-sectional views of an example FinFET device along the line A-A in  FIG. 13A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIGS. 13E and 13F  are cross-sectional views of an example FinFET device along the line B-B in  FIG. 13B  at fabrication stages constructed according to the method of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     The present disclosure is directed to, but not otherwise limited to, a fin-like field-effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metaloxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with a FinFET example to illustrate various embodiments of the present invention. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed. 
       FIG. 1  is a flowchart of a method  100  for fabricating a FinFET device  200  in accordance with some embodiments. It is understood that additional steps may be implemented before, during, and after the method, and some of the steps described may be replaced or eliminated for other embodiments of the method. The FinFET device  200  and the method  100  making the same are collectively described with reference to various figures. 
     Referring to  FIGS. 1 and 2A-2B , the method  100  begins at step  102  by providing a substrate  210 . The substrate  210  may include a bulk silicon substrate. Alternatively, the substrate  210  may include an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. 
     In another embodiment, the substrate  210  has a silicon-on-insulator (SOI) structure with an insulator layer in the substrate. An exemplary insulator layer may be a buried oxide layer (BOX). The SOI substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. 
     In the present embodiment, the substrate  210  includes a first semiconductor material layer  212 , a second semiconductor material layer  214  disposed over the first semiconductor material layer  212  and a third semiconductor material layer  216  disposed over the second semiconductor material layer  214 . The second and third semiconductor material layers,  214  and  216 , are different from each other. The second semiconductor material layer  214  has a first lattice constant and the third semiconductor material layer  416  has a second lattice constant different from the first lattice constant. In the present embodiment, the second semiconductor material layer  214  includes silicon germanium (SiGe), and both of the first and the third semiconductor material layers,  212  and  216 , include silicon. In various examples, the first, the second and the third semiconductor material layers,  212 ,  214  and  216 , may include germanium (Ge), silicon (Si), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), or other suitable materials. In the present embodiment, the second and the third semiconductor material layers,  214  and  216 , are deposited by epitaxial growth, referred to as a blanket channel epi. In various examples, the epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. 
     The substrate  210  may include various doped features depending on design requirements as known in the art. In some embodiment, the substrate  210  may include various doped regions depending on design requirements (e. g., p-type substrate or n-type substrate). In some embodiment, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF 2 ; n-type dopants, such as phosphorus or arsenic, and/or combination thereof. The doped regions may be configured for an n-type FinFET (NFET), or alternatively configured for a p-type FinFET (PFET). 
     Referring to  FIGS. 1 and 3A-3B , the method  100  proceeds to step  104  by forming first fins  220  and trenches  230  in the substrate  210 . The first fin  220  has a first width w 1  in a range of about 4 nm to about 10 nm. In one embodiment, a patterned fin hard mask (FHM) layer  222  is formed over the substrate  210 . The patterned FHM layer  222  includes silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material. The patterned hard mask layer  222  may include a single material layer or multiple material layers. The patterned FHM layer  222  may be formed by depositing a material layer by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other appropriate method, forming a patterned photoresist (resist) layer by a lithography process, and etching the material layer through the openings of the patterned photoresist layer to form the patterned FHM layer  222 . 
     An exemplary photolithography process may include forming a photoresist layer, exposing the resist by a lithography exposure process, performing a post-exposure bake process, and developing the photoresist layer to form the patterned photoresist layer. The lithography process may be alternatively replaced by other technique, such as e-beam writing, ion-beam writing, maskless patterning or molecular printing. 
     The substrate  210  is then etched through the patterned FHM layer  222  to form the first fins  220  and the trenches  230  in the substrate  210 . In another embodiment, the patterned photoresist layer is directly used the patterned FHM layer  222  as an etch mask of the etch process to form the first fins  220  and the trenches  230  in the substrate  210 . The etching process may include a wet etch or a dry etch. In one embodiment, the wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. The respective etch process may be tuned with various etching parameters, such as etchant used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and/or other suitable parameters. For example, a wet etching solution may include NH 4 OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF 4 , NF 3 , SF 6 , and He. Dry etching may also be performed anisotropically using such mechanism as DRIE (deep reactive-ion etching). 
     In the present embodiment, the etching depth is controlled such that the third and the second semiconductor material layers,  216  and  214  are fully exposed but the first semiconductor material layer  212  is partially exposed in the trench  230 . Thus the first fin structure  220  is formed to have the third semiconductor material layer  216  as an upper portion, the second semiconductor material layer  214  as a middle portion and the first semiconductor material layer  212  as a bottom portion. 
     In some embodiment, the FinFET device  200  includes an NFET device, designated with the reference numeral  200 A and referred to as the NFET device  200 A. The FinFET device  200  also includes a PFET device, designated with the reference numeral  200 B and referred to as the PFET device  200 B. 
     Referring to  FIGS. 1 and 4A-4B , the method  100  proceeds to step  106  by forming a patterned oxidation-hard-mask (OHM)  310  over the substrate  210 , including wrapping a portion of the first fins  220 . In the present embodiment, in the NFET  200 A, the patterned OHM  310  covers a first region  312  and exposes a second region  314  in the substrate  210 . In the PFET  200 B, the patterned OHM  310  wraps the whole first fins  220 . The patterned OHM layer  310  may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material. The patterned OHM layer  310  may be formed by depositing a material layer by thermal oxidation, chemical CVD, ALD, or any other appropriate method, forming a patterned photoresist (resist) layer by a lithography process, and etching the material layer through the openings of the patterned photoresist layer to form the patterned OHM layer  310 . 
     Referring also to  FIGS. 1, 4A and 5 , the method  100  proceeds to step  108  by performing a thermal oxidation process to the FinFET device  200 . In one embodiment, the thermal oxidation process is conducted in oxygen ambient. In another embodiment, the thermal oxidation process is conducted in a combination of steam ambient and oxygen ambient. In the second region  314  of the NFET  200 A, during the thermal oxidation process, at least outer layers of the first, the second and the third semiconductor material layers,  212 ,  214  and  216 , convert to a first, second and a third semiconductor oxide features  322 ,  324  and  326 , respectively. While in the first region  312  of the NFET  200 A, as well as entire the PFET  200 B, the patterned OHM  310  prevents the first fin structure  220 , to be oxidized. Therefore, the thermal oxidation process is referred to as a selective oxidation. 
     After the thermal oxidation process, the first fin structure  220  in the second region  324  has a different structure than those in the first region  312 . For the sake of clarity to better description, the first fin structure  220  in the second region  214  (having the second semiconductor oxide feature  324 ) is referred to as a second fin structure  320 . Thus the second fin structure  320  has the third semiconductor material layer  216  as its upper portion, the second semiconductor material layer  214 , with the second semiconductor oxide feature  324  at its outer layer, as its middle portion and the first semiconductor material layer as its bottom portion. 
     In the present embodiment, the thermal oxidation process is controlled such that the second semiconductor material layer  214  oxidizes much faster that the first and third semiconductor material layers,  212  and  216 . In another words, comparing to the second semiconductor oxide feature  324 , the first and third semiconductor oxide features,  322  and  326 , are quite thin. As an example, the thermal oxidation process to the FinFET device  200  is performed in a H 2 O reaction gas with a temperature ranging from about 400° C. to about 600° C. and under a pressure ranging from about 1 atm. to about 20 atm. After the oxidation process, a cleaning process is performed to remove the first and the third semiconductor oxide features,  322  and  326 . The cleaning process may be performed using diluted hydrofluoric (DHF) acid. 
     In the present example, the second semiconductor oxide features  324  extends in the vertical direction with a horizontal dimension varying from the top surface to the bottom surface of the second semiconductor material layer  214 . In furtherance of the present example, the horizontal dimension of the second semiconductor oxide features  324  reaches its maximum, referred to as a first width w 1 , and decreases to close to zero when approaches to the top and bottom surfaces of the second semiconductor oxide features  324 , resulting in an olive shape in a cross-sectional view. By tuning of the thermal oxidation process, selecting a composition and thickness of the second semiconductor material layer  214  and tuning the oxidation temperature, it achieves a target second width w 2  of the second semiconductor oxide feature  324 , which applies an adequate stress to the third semiconductor material layer  216  in the first fin  220 , where a gate channel is to be defined underlying a gate region, which will be described later. 
     In one embodiment, the second semiconductor material layer  214  includes silicon germanium (SiGex 1 ) and both of the first and the third semiconductor material layers,  212  and  216 , include silicon (Si). The subscript x 1  is a first Ge composition in atomic percent and it may be adjusted to meet a predetermined volume expansion target. In one embodiment, x 1  is selected in a range from about 20% to about 80%. An outer layer of the SiGex 1  layer  214  is oxidized by the thermal oxidation process, thereby forming the silicon germanium oxide (SiGeO) feature  324 . The second width w 2  of the SiGeO feature  324  is in a range of about 3 nm to 10 nm. A center portion of the SiGex 1  layer  214  changes to a second Ge composition x 2 , which is much higher than x 1 . A size and shape of the center portion of SiGex 2  vary with process conditions, such as thermal oxidation temperature and time. Also the second Ge composition x 2  in the center portion is higher than other portions, such as a top portion, a bottom portion, a left side portion and a right side portion. 
     Referring to  FIGS. 1 and 6A-6B , the method  100  proceeds to step  110  by depositing a liner  405  to conformably wrap over the first fin structure  220 , as well as the second fin structure  320 , in both of the NFET device  200 A and the PFET device  200 B. First, the patterned OHM layer  310  is removed by an etching process, such as a selective wet etch. In the present embodiment, the liner  405  includes silicon nitride, silicon oxynitride, aluminum oxide, or other suitable materials. The liner  405  has a first thickness in a range of about 20 Å to about 60 Å. In the present embodiment, the liner  405  is deposited by ALD to achieve adequate film coverage of wrapping over the first fin structure  220 . Alternatively, the liner  405  may be deposited by CVD, physical vapor deposition (PVD), or other suitable techniques. In one embodiment, the liner  405  is formed by two layers, a first layer  404  and a second layer  404  deposited over the first layer  404 , not shown. The first layer  402  may include Si and silicon oxynitride and the second layer  404  may include silicon nitride and aluminum oxide. The first layer  402  has a second thickness in a range of about 10 Å to about 30 Å and the second layer  404  has a third thickness in a range of about 20 Å to about 60 Å. In the present embodiment, the liner  405  is designed to be a buffer layer to prevent the second semiconductor material layer  214  be oxidized further in the downstream or later processed and a barrier of out-diffusion of the second semiconductor material layer  214 , which will be described in detail below. 
     Referring to  FIGS. 1 and 7A-7B , the method  100  proceeds to step  112  by depositing a dielectric layer  410  over the substrate  210 , including filling in the trench  230 , in both of the NFET  200 A and the PFET  200 B. The dielectric layer  410  may include silicon oxide, silicon nitride, silicon oxynitride, spin-on-glass, spin-on-polymer, or other suitable materials, or combinations thereof. The dielectric layer  410  may be deposited by CVD, physical vapor deposition (PVD), ALD, thermal oxidation, spin-on coating, or other suitable techniques, or a combination thereof. As has been mentioned previously, having the liner  405  cover the first fin structure  220  and the second fin structure  320 , it provides a buffer to adverse impacts induced during the formation of the dielectric layer  410 , such as in thermal curing process for the dielectric layer  410 . 
     Referring also to  FIGS. 1 and 7A-7B , the method  100  proceeds to step  114  by forming a patterned HM layer  415  over the substrate  210  to cover the NFET  200 A and leave the PFET  200 B be un-covered. The patterned HM layer  415  may include silicon nitride, silicon oxynitride, silicon carbide, or any other suitable dielectric material. The patterned HM layer  415  may be formed similarly to forming of the patterned OHM layer  310  in step  106 . 
     Referring to  FIGS. 1 and 8A , the method  100  proceeds to step  116  by recessing the liner  405  and the third semiconductor material layer  216  in the first fin structure  220  in the PFET  200 B, while the NFET  200 A is protected by the patterned HM layer  415 . The liner  405  and the third semiconductor material layer  216  are recessed by proper etching processes, such as a selective wet etch, a selective dry etch, or a combination thereof. Alternatively, the liner  405  and the third semiconductor material layer  216  are recessed through a patterned photoresist layer formed over the PFET  200 B. In present embodiment, the recessing processes are controlled to have a top surface of the remaining liner  405  below the remaining third semiconductor material layer  216  but above the second semiconductor material layer  214  with a first distance d 1 . As has been mentioned previously, the first distance d 1  is designed to be adequate to retard an upwards-out-diffusion of the second semiconductor material  214 , along an interface  412  of the dielectric layer  410  and the third semiconductor material layer  216 , into the upper portion of the first fin structures, where a gate channel will be formed later. For example, the first distance d 1  is adequate to retard the upwards out-diffusion of Ge in the SiGe layer  214  along the interface  412  of the dielectric layer  410  and the Si layer  216 . In one embodiment, the first distance d 1  is in a range of about 2 nm to about 10 nm. 
     In another embodiment, as shown in  FIG. 8B , where the liner is formed by the first layer  402  and the second layer  404 , the first layer  402  is recessed to have a top surface of the remaining first layer  402  above the second semiconductor material layer  214  with a second distance d 2  and the second layer  404  is recessed to have a top surface of the remaining second layer  404  above the second semiconductor material layer  214  with the first distance d 1 . The second distance d 2  is larger than the first distance d 1 . In one embodiment, the second distance d 2  is in a range of about 5 nm to about 20 nm. The double layers of the liner will enhance to retard an out-diffusion of the second semiconductor material  214  along the interface  412  of the dielectric layer  410  and the third semiconductor material layer  216 . 
     Referring to  FIGS. 1, 7A and 9 , the method  100  proceeds to step  118  by depositing a fourth semiconductor material layer  430  over the recessed third semiconductor material layer  216  to form a third fin structure  440  in the PFET device  200 B, while the NFET  200 A is protected by the patterned HM layer  415 . The fourth semiconductor material layer  430  may be deposited by epitaxial growth. The epitaxial process may include CVD deposition techniques, molecular beam epitaxy, and/or other suitable processes. The fourth semiconductor material layer  430  may include germanium (Ge), silicon (Si), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), or other suitable materials. In the present embodiment, the fourth semiconductor material layer  430  is SiGe. Thus the third fin structure  440  is formed to have the fourth semiconductor material layer  430  as its upper portion, the third semiconductor material layer  216  as its upper middle portion, the second semiconductor material layer  214  as its lower middle portion and the first semiconductor material layer  212  as its bottom portion. 
     A CMP process may be performed thereafter to remove excessive the fourth semiconductor material layer  430  and planarize the top surface of the PFET device  200 B. The HM layer  415  in the NFET device  200 A is removed by a proper etching process, such as a wet etch, a dry etch, or a combination thereof. 
     Referring to  FIGS. 1 and 10A-10E , the method  100  proceeds to step  120  by recessing the liner  405  in the NFET device  200 A and recessing the dielectric layer in both of the NFET device  200 A and the PFET device  200 B. First, the patterned HM layer  415  is removed from the NFET device  200 A by a proper etching process, such as a selective wet etch, or a selective dry etch. The liner  405  is then be recessed by a proper etching process, such as a selective wet etch, a selective dry etch, or a combination thereof. In present embodiment, the recessing processes are controlled to have a top surface of the remaining liner  405  below the remaining third semiconductor material layer  216  but above the second semiconductor material layer  214  with the first distance d 1 . In another embodiment, where the liner is formed by the first layer  402  and the second layer  404 , the first layer  402  is recessed to have a top surface of the remaining second layer  402  above the second semiconductor material layer  214  with the second distance d 2 . 
     The dielectric layer  410  is then recessed in both of the NFET device  200 A and the PFET device  200 B to expose the upper portion of the first fin structure  220  (in the NFET device  200 A) and the upper portion of the third fin structure  440  (in the PFET device  200 B). In the present embodiment, the recessing processes are controlled to have a top surface of the recessed dielectric layer  410  above the top surface of the liner  405  with a third distance d 3 . In the present embodiment, the third distance d 3  is designed to be adequate to keep the liner  405  away from an upper portion of the first, the second and the third fin structures, where a gate region will be formed later, to avoid adverse impacts of the liner  405  to the gate region, such as fixed charges in the liner  405 . In one embodiment, the third distance d 3  is in a range of about 3 nm to about 10 nm. Alternatively, where the liner is formed by the first liner  402  and the second liner  404 , the top surface of the recessed dielectric layer  410  is above the top surface of the second layer  404  with the third distance d 3 . The top surface of the first layer  402  is at same level or below the top surface of the recessed dielectric layer  410 . 
     In one embodiment, the recessed dielectric layer  410  in the trench  230  forms shallow trench isolation (STI) features. 
     Referring also to  FIGS. 10A and 10B , in some embodiments, the first, the second and the third fin structures,  220 ,  320  and  440 , include source/drain (S/D) regions  450  and gate regions  460 . In furtherance of the embodiment, one of the S/D regions  450  is a source region, and another of the S/D regions  450  is a drain region. The S/D regions  450  are separated by the gate region  460 . For the sake of clarity to better description, the S/D regions and the gate regions in the NFET device  200 A are referred to as a first S/D regions  450 A and a first gate regions  460 A; the S/D regions and the gate regions in the PFET device  200 B are referred to as a second S/D regions  450 B and a second gate regions  460 B. 
     In one embodiment, the first S/D regions  450 A locates in a portion of the first fin structure  220 , separated by the first gate region  460  locating in a portion of the second fin structure  320 . In the PFET device  200 B, the third fin structure  440  includes the second S/D regions  450 B, separated by the second gate region  460 B. 
     Referring to  FIGS. 1 and 11A-11B , the method  100  proceeds to step  122  by forming a gate stack  510  and sidewall spacers  520  on sidewalls of the gate stack  510 , in the first and second gate regions,  460 A and  460 B. In one embodiment using a gate-last process, the gate stack  510  is a dummy gate and will be replaced by the final gate stack at a subsequent stage. Particularly, the dummy gate stacks  510  are to be replaced later by a high-k dielectric layer (HK) and metal gate electrode (MG) after high thermal temperature processes, such as thermal annealing for S/D activation during the sources/drains formation. The dummy gate stack  510  is formed on the substrate  210  and is partially disposed over the second fin structure  320  in the first gate region  460 A and the third fin structure  440  in the second gate region  460 B. In one embodiment, the dummy gate stack  510  includes a dielectric layer  512 , an electrode layer  514  and a gate hard mask (GHM)  516 . The dummy gate stack  510  is formed by a suitable procedure including deposition and patterning. The patterning process further includes lithography and etching. In various examples, the deposition includes CVD, physical vapor deposition (PVD), ALD, thermal oxidation, other suitable techniques, or a combination thereof. The lithography process includes photoresist (or resist) coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof. The etching process includes dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching). 
     The dielectric layer  512  includes silicon oxide. Alternatively or additionally, the dielectric layer  512  may include silicon nitride, a high-k dielectric material or other suitable material. The electrode layer  514  may include polycrystalline silicon (polysilicon). The GHM  516  includes a suitable dielectric material, such as silicon nitride, silicon oxynitride or silicon carbide. The sidewall spacers  520  may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. The sidewall spacers  520  may include a multiple layers. Typical formation methods for the sidewall spacers  520  include depositing a dielectric material over the gate stack  510  and then anisotropically etching back the dielectric material. The etching back process may include a multiple-step etching to gain etch selectivity, flexibility and desired overetch control. 
     Referring again to  FIGS. 1 and 11A-11B , the method  100  proceeds to step  124  by forming a first S/D features  610 A in the first S/D regions  450  A and a second S/D features  610 B in the second S/D regions  450 B. In one embodiment, the first S/D features  610 A is formed by recessing a portion of the upper portion of the first fin  220  in the first S/D region  450 A and the second S/D features  610 B is formed by recessing a portion of the upper portion of the third fin  440  in the second S/D region  450 B. In one embodiment, the first fin structure  220  and the third fin structure  440  are recessed in one etching process. In another embodiment, the first fin structure  220  and the third fin structure  440  are recessed in two different etching processes. In present embodiment, for gaining process integration flexibility. the recessing process is controlled to have a portion of the third semiconductor material layer  216  remain in the first fin structure  220  and have a portion of the fourth semiconductor material layer  430  remain in the third fin structure  440 . 
     The first S/D features  610 A and the second S/D features  610 B are then epitaxially grow on the recessed first fin structure  220  in the first S/D region  450 A and the recessed third fin structure  440  in the second S/D region  450 B. The first and the second S/D features,  610 A and  610 B, include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, or other suitable material. The first and the second S/D features,  610 A and  610 B, may be formed by one or more epitaxy or epitaxial (epi) processes. The first and the second S/D features,  610 A and  610 B, may also be doped, such as being in-situ doped during the epi processes. Alternatively, the first and the second S/D features,  610 A and  610 B, are not in-situ doped and implantation processes (i.e., a junction implant process) are performed to dope the first and the second S/D features,  610 A and  610 B. 
     In one embodiment, the first S/D features  610 A is formed by the epitaxially grown Si layer doped with carbon to form Si:C z  as a lower portion of the first S/D features  610 A and the epitaxial grown Si layer doped with phosphorous to form Si:P as an upper portion of the first S/D features  610 A, where z is carbon composition in atomic percent. In one embodiment, z is in a range of about 0.5% to about 1.5%. The Si:C z  has a thickness, which is in a range of about 5 nm to about 15 nm. The Si:P has a thickness, which is in a range of about 20 nm to 35 nm. 
     In another embodiment, the second S/D features  610 B is formed by the epitaxially grown SiGe layer doped with boron to form SiGe α B where α is germanium composition in atomic percent. In one embodiment, α is in a range of about 60% to about 100%. 
     Referring to  FIGS. 1 and 12A-12B , the method  100  proceeds to step  126  by forming an interlayer dielectric (ILD) layer  720  on the substrate  210  between the gaps of the dummy gate stacks  510 . The ILD layer  720  includes silicon oxide, silicon oxynitride, low k dielectric material or other suitable dielectric materials. The ILD layer  720  may include a single layer or alternative multiple layers. The ILD layer  720  is formed by a suitable technique, such as CVD, ALD and spin-on (SOG). A chemical mechanical polishing (CMP) process may be performed thereafter to remove excessive ILD layer  720  and planarize the top surface of the FinFET device  200 . 
     Referring also to  FIGS. 1 and 12A-12B , the method  100  proceeds to step  128  by removing the dummy gate stacks  510  in the first gate region  460 A to form one or more first gate trench  810 A and in the second gate region  460 B to form one or more second gate trench  810 B. The upper portion of the second fin structure  320  is exposed in the first gate trench  810 A and the upper portion of the third fin structure  440  is exposed in the second gate trench  810 B. The dummy gate stacks  510  are removed by an etch process (such as selective wet etch or selective dry etch) designed to have an adequate etch selectivity with respect to the third semiconductor material layer  216  in the first gate trench  810 A and the fourth semiconductor material layer  430  in the second gate trench  810 B. The etch process may include one or more etch steps with respective etchants. The gate hard mask layer  516  and the spacers  520  are removed as well. Alternatively, the dummy gate stack  510  may be removed by a series of processes including photolithography patterning and etching process. 
     Referring to  FIGS. 1 and 13A-13G , the method  100  proceeds to step  130  by forming a first and a second high-k/metal gate (HK/MG) stacks,  910 A and  910 B, over the substrate  210 , including wrapping over a portion of the second fins  320  in the first gate trench  810 A and a portion of the third fin structure  440  in the second gate trench  810 B, respectively. The first and the second HK/MG stacks,  910 A and  910 B, include gate dielectric layer  912  and gate electrode  914  on the gate dielectric  912 . In one embodiment, the gate dielectric layer  912  includes a dielectric material layer having a high dielectric constant (HK dielectric layer-greater than that of the thermal silicon oxide in the present embodiment) and the gate electrode  914  includes metal, metal alloy or metal silicide. The formation of the first and the second HK/MG stacks,  910 A and  910 B, includes depositions to form various gate materials and a CMP process to remove the excessive gate materials and planarize the top surface of the NFET device  200 A and the PFET device  200 B. 
     In one embodiment, the gate dielectric layer  912  includes an interfacial layer (IL) deposited by a suitable method, such as atomic layer deposition (ALD), CVD, thermal oxidation or ozone oxidation. The IL includes oxide, HfSiO and oxynitride. A HK dielectric layer is deposited on the IL by a suitable technique, such as ALD, CVD, metal-organic CVD (MOCVD), physical vapor deposition (PVD), other suitable technique, or a combination thereof. The HK dielectric layer may include LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y2O 3 , SrTiO 3  (STO), BaTiO 3  (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3  (BST), Al 2 O 3 , Si 3 N 4 , oxynitride (SiON), or other suitable materials. The gate dielectric layers  912  wrap over the upper portion of the second fin structures  320  in the first gate region  460 A and the upper portion of the third fin structures  440  in the second gate region  460 B. 
     A metal gate (MG) electrode may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer and a conductive layer of metal, metal alloy or metal silicide). The MG electrode may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, any suitable materials or a combination thereof. The MG electrode may be formed by ALD, PVD, CVD, or other suitable process. The MG electrode may be formed separately for the NFET  200 A and the PFET  200 B with different metal layers. A CMP process may be performed to remove excessive MG electrode. 
     Referring again to  FIGS. 13C and 13D , in the NFET device  200 A, the first HK/MG gate  910 A wraps over the upper portion of the second fin  320 , where the second fin structure  320  includes the semiconductor material layer  216  as its upper portion, the second semiconductor material layer  214 , with a semiconductor oxide feature  324  at its outer layer, as its middle portion and the first semiconductor material layer  212  as its bottom portion. The liner  405  is formed along sidewalls of the second fin structure such that along a lower portion of the third semiconductor material layer  216 ; along the semiconductor oxide feature  324  and along the first semiconductor material layer  212 . The top surface of the liner  405  is above a top surface of the second semiconductor material layer  214  with the first distance d 1 . The recessed dielectric layer  410  is formed between each of second fin structures  320 . The top surface of the recessed dielectric layer  410  is above the top surface of the liner  405  with the third distance d 3 . 
     Referring again to  FIGS. 13E and 13F , in the PFET device  200   b , the second HK/MG gate  910 B wraps over the upper portion of the third fin structure  440 , where the includes the fourth semiconductor material layer  430  as its upper portion, the third semiconductor material layer  216  as its upper middle portion, the second semiconductor material layer  214  as its lower middle portion and the first semiconductor material layer  212  as its bottom portion. The liner  405  is formed along sidewalls of the third fin structure  440  such that, it wraps along a lower portion of the third semiconductor material layer  216 ; along the second semiconductor material layer  214  and along the first semiconductor material layer  212 . The top surface of the liner  405  is above the top surface of the second semiconductor material layer  214  with the first distance d 1 . The recessed dielectric layer  410  is formed between each of third fin structures  440  and the top surface of the recessed dielectric layer  410  is above the top surface of the liner  405  with the third distance d 3 . 
     When the liner includes the first layer  402  and the second layer  404 , the top surface of the first layer  402  is above the second semiconductor material layer  214  with a second distance d 2 , which is larger than the first distance d 1  but it is at same or below the top surface of the recessed dielectric layer  410 . 
     The FinFET device  200  may undergo further CMOS or MOS technology processing to form various features and regions known in the art. For example, subsequent processing may form various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate  210 , configured to connect the various features to form a functional circuit that includes one or more FinFET field-effect transistors. In furtherance of the example, a multilayer interconnection includes vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. 
     Additional operations may be implemented before, during, and after the method  100 , and some operations described above may be replaced or eliminated for other embodiments of the method. 
     Based on the above, the present disclosure offers structures of a FinFET. The structures employ a liner wrapping over the fin structures to retard out-diffusion in a gate region and provide a buffer for the fin structure in the gate region. The structured demonstrate device performance improvement. 
     The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner. 
     The present disclosure also provides another embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a second fin structure over the substrate, in a second gate region. The second fin structure includes an upper semiconductor material member, a middle semiconductor material member and a lower semiconductor material member, the liner wrapping around the lower semiconductor material member and the middle semiconductor member and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes the dielectric layer laterally proximate to an upper portion of the middle semiconductor material member. The middle semiconductor material member includes an upper portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner and a second high-k/metal gate stack over the substrate, including wrapping over the upper semiconductor material member and the upper portion of the middle semiconductor material member in the second gate region. 
     The present disclosure also provides a method for fabricating a FinFET. The method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region, forming first fin structures in the NFET region and the PFEN region. The first fin structure includes a first epitaxial semiconductor material layer as its upper portion; a second epitaxial semiconductor material layer, with a semiconductor oxide feature at its outer layer, as its middle portion and a third semiconductor material layer as its bottom portion. The method also includes forming a patterned oxidation-hard-mask (OHM) over the NFET region and PFEN region to expose the first fin structure in a first gate region of the NFET region. The method also includes applying annealing to form a semiconductor oxide feature at out layer of the second semiconductor material layer in the first fin structure in the first gate region. The method also includes forming a liner wrapping over the first fins in both of the NFET region and the PFET region, depositing a dielectric layer between the first fins, recessing the liner and forming a second fin structure in the PFET region after covering the NFET region with a hard mask layer. The method also includes recessing the liner in the NFET region after removing the hard mask layer and recessing the dielectric layer in both of the NFET region and the PFET region. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.