Patent Publication Number: US-10790216-B2

Title: Thermally enhanced semiconductor package and process for making the same

Description:
RELATED APPLICATIONS 
     This application is a divisional of U.S. patent application Ser. No. 15/491,064, filed on Apr. 19, 2017, now U.S. Pat. No. 10,068,831, which claims the benefit of provisional patent application Ser. No. 62/431,914 filed Dec. 9, 2016, the disclosures of which are hereby incorporated herein by reference in their entirety. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure relates to a semiconductor package and a process for making the same, and more particularly to a thermally enhanced semiconductor package, and a process to apply a thermally conductive film to the semiconductor package for enhanced thermal performance. 
     BACKGROUND 
     With the current popularity of portable communication devices and developed semiconductor fabrication technology, high speed and high performance transistors are more densely integrated on semiconductor dies. Consequently, the amount of heat generated by the semiconductor dies increases significantly due to the large number of transistors integrated on the semiconductor dies, the large amount of power passing through the transistors, and the high operation speed of the transistors. Accordingly, it is desirable to package the semiconductor dies in a configuration for better heat dissipation. 
     Flip chip assembly technology is widely utilized in semiconductor packaging due to its preferable solder interconnection between flip chip dies and the laminate, on which the flip chip dies are mounted. The flip chip assembly technology eliminates the space needed for wire bonding and the die surface areas of a package, and essentially reduces the overall size of the package. In addition, the elimination of the wire bonding and implementation of a shorter electrical path from the flip chip dies to the laminate reduces undesired inductance and capacitance. 
     Further, semiconductor dies formed from silicon on insulator (SOI) structures are trending due to the low cost of silicon materials, a large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques. However, harmonic generations and low resistivity values of the SOI structures severely limit the SOI&#39;s usage in radio-frequency (RF) applications. By using SOI structures in RF fabrications, an interface between the silicon handle layer and an adjacent dielectric layer will generate unwanted harmonic and intermodulation products. Such spectrum degradation causes a number of significant system issues, such as unwanted generation of signals in other RF bands, which the system is attempting to avoid. 
     To accommodate the increased heat generation of high performance dies and to utilize the advantages of flip chip assembly, it is therefore an object of the present disclosure to provide an improved semiconductor package design with flip chip dies in a configuration for better heat dissipation. In addition, there is also a need to eliminate the deleterious effects of harmonic generations and intermodulation distortions. 
     SUMMARY 
     The present disclosure relates to a thermally enhanced semiconductor package, and a process for making the same. According to one embodiment, a thermally enhanced semiconductor package includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The thinned flip chip die includes a device layer, a number of interconnects extending from a lower surface of the device layer and coupled to an upper surface of the module substrate, and a dielectric layer over an upper surface of the device layer. The mold compound component resides over the upper surface of the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip die at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity. 
     In one embodiment of the semiconductor package, the thinned flip chip die is formed from a silicon on insulator (SOI) structure. Herein, the device layer of the thinned flip chip die is formed from a silicon epitaxy layer of the SOI structure and the dielectric layer of the thinned flip chip die is a buried oxide layer of the SOI structure. 
     In one embodiment of the semiconductor package, the thermally conductive film has a higher thermal conductivity than the thermally enhanced mold compound component. 
     In one embodiment of the semiconductor package, the thermally conductive film has a thermal conductivity between 5 w/m·k and 5000 w/m·k. 
     In one embodiment of the semiconductor package, the thermally conductive film has a thickness between 0.1 μm to 100 μm. 
     In one embodiment of the semiconductor package, the thermally conductive film resides over exposed surfaces of the cavity and over the mold compound component to thermally connect the module substrate. 
     In one embodiment of the semiconductor package, the thermally enhanced mold compound component has a thermal conductivity between 2 w/m·k and 20 w/m·k. 
     According to an exemplary process, a precursor package including a module substrate, a thinned flip chip die attached to an upper surface of the module substrate, and a mold compound component is provided. Herein, the mold compound component resides over the upper surface of the module substrate, surrounds the thinned flip chip die, and extends above the upper surface of the thinned flip chip die to form a cavity, which is above the upper surface of the thinned flip chip die. Next, a thermally conductive film is deposited over at least the upper surface of the thinned flip chip at the bottom of the cavity. A thermally enhanced mold compound component is then applied over at least a portion of the thermally conductive film to fill the cavity. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1  shows an exemplary thermally enhanced semiconductor package according to one embodiment of the present disclosure. 
         FIG. 2  shows an alternative thermally enhanced semiconductor package according to one embodiment of the present disclosure. 
         FIG. 3  shows an alternative thermally enhanced semiconductor package according to one embodiment of the present disclosure. 
         FIGS. 4-9  provide exemplary steps that illustrate a process to fabricate the exemplary thermally enhanced semiconductor package shown in  FIG. 1 . 
     
    
    
     It will be understood that for clear illustrations,  FIGS. 1-9  may not be drawn to scale. 
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     The present disclosure relates to a thermally enhanced semiconductor package, and a process for making the same.  FIG. 1  shows an exemplary thermally enhanced semiconductor package  10  according to one embodiment of the present disclosure. For the purpose of this illustration, the exemplary thermally enhanced semiconductor package  10  includes a module substrate  12 , two thinned flip chip dies  14 , an underfilling layer  16 , a mold compound component  18 , a thermally conductive film  20 , and a thermally enhanced mold compound component  22 . In different applications, the thermally enhanced semiconductor package  10  may include fewer or more thinned flip-chip dies. 
     In detail, the module substrate  12  may be formed from a laminate, a wafer level fan out (WLFO) carrier, a lead frame, a ceramic carrier, or the like. Each thinned flip chip die  14  includes a device layer  24 , a number of interconnects  26  extending from a lower surface of the device layer  24  and coupled to an upper surface of the module substrate  12 , a dielectric layer  28  over an upper surface of the device layer  24 , and essentially no silicon handle layer (not shown) over the dielectric layer  28 . Herein, essentially no silicon handle layer over the dielectric layer  28  refers to at most 2 μm silicon handle layer over the dielectric layer  28 . In some cases, the thinned flip chip dies  14  do not include any silicon handle layer such that an upper surface of each thinned flip chip die  14  is an upper surface of the dielectric layer  28 . The device layer  24  with a thickness between 10 nm and 20000 nm may be formed of silicon oxide, gallium arsenide, gallium nitride, silicon germanium, or the like, and the dielectric layer  28  with a thickness between 10 nm and 20000 nm may be formed of silicon oxide, silicon nitride, or aluminum nitride. The interconnects  26  with a height between 5 μm and 200 μm may be copper pillar bumps, solder ball bumps, or the like. 
     In one embodiment, each thinned flip chip die  14  may be formed from a silicon on insulator (SOI) structure, which refers to a structure including a silicon handle layer, a silicon epitaxy layer, and a buried oxide layer sandwiched between the silicon handle layer and the silicon epitaxy layer. Herein, the device layer  24  of each thinned flip chip die  14  is formed by integrating electronic components in or on the silicon epitaxy layer of a SOI structure. The dielectric layer  28  of each thinned flip chip die  14  is the buried oxide layer of the SOI structure. In addition, the silicon handle layer of the SOI structure is removed substantially to complete each thinned flip chip die  14  (more details in the following discussion). 
     The underfilling layer  16  resides over the upper surface of the module substrate  12 , such that the underfilling layer  16  encapsulates the interconnects  26  and underfills each thinned flip chip die  14  between the lower surface of the device layer  24  and the upper surface of the module substrate  12 . The underfilling layer  16  may be formed from conventional polymeric compounds, which serve to mitigate the stress effects caused by Coefficient of Thermal Expansion (CTE) mismatch between the thinned flip chip dies  14  and the module substrate  12 . 
     The mold compound component  18  resides over the underfilling layer  16 , surrounds each thinned flip chip die  14 , and extends above the upper surface of each thinned flip chip die  14  to form a cavity  30  over the upper surface of each thinned flip chip die  14 . Herein, the upper surface of each thinned flip chip die  14  is exposed at the bottom of the cavity  30 . The mold compound component  18  may be formed from a same or different material as the underfilling layer  16 . When the mold compound  18  and the underfilling layer  16  are formed from a same material, the mold compound  18  and the underfilling layer  16  may be formed simultaneously. One exemplary material used to form the mold compound component  18  is an organic epoxy resin system. 
     The thermally conductive film  20  is continuously deposited over exposed surfaces of each cavity  30  and over the mold compound component  18 . In some applications, the thermally conductive film  20  may also extend to thermally connect the module substrate  12 . Within each cavity  30 , the thermally conductive film  20  is immediately above the upper surface of each thinned flip chip die  14  with no significant voids or defects. Herein, no significant voids or defects refers to no voids or defects larger than 0.1 μm between the thermally conductive film  20  and the upper surface of each thinned flip chip die  14 . The thermally conductive film  20  has a high thermal conductivity between 5 w/m·k and 5000 w/m·k and a high electrical resistivity greater than 1E6 Ohm-cm. The thermally conductive film  20  may be formed from chemical vapor deposition (CVD) diamond, aluminum nitride, boron nitride, alumina, beryllium oxide, and the like. 
     Heat generated by the electronic components in each device layer  24  will travel upward to an area above the upper surface of each thinned flip chip die  14  and then pass laterally in the area above the upper surface of each thinned flip chip die  14  until it is extracted via the interconnects  26  to the module substrate  12 . It is therefore highly desirable to have a high thermal conductivity region immediately adjacent to the upper surface of each thinned flip chip die  14  to conduct most of the heat generated by the thinned flip chip dies  14 . Consequently, the higher the thermal conductivity in the adjacent region above the upper surface of each thinned flip chip die  14 , the better the heat dissipation performance of the thinned flip chip dies  14 . Depending on different deposition stresses, different deposited materials, and different applications of the thinned flip chip dies  14 , the thermally conductive film  20  has different thicknesses varying from 0.1 μm to 100 μm. For a CVD diamond material, which has an extremely high conductivity greater than 2000 w/m·k, a 1 μm or greater thickness of the thermally conductive film  20  is extremely effective for the heat dissipation management of the thinned flip chip dies  14 . For a boron nitride material, which has a high conductivity between 50 w/m·k-100 w/m·k, a 5 μm-10 μm thickness of the thermally conductive film  20  is desirable. 
     Besides the bottom region of each cavity  30 , which is adjacent to the upper surface of each thinned flip chip die  14 , the thermally conductive film  20  may also be deposited over the mold compound component  18  and in contact with the module substrate  12 . Consequently, the heat generated by the thinned flip chip dies  14  may also dissipate through the thermally conductive film  20  and over the mold compound component  18  to the module substrate  12 . 
     The thermally enhanced mold compound component  22  resides over at least a portion of the thermally conductive film  20  to substantially fill each cavity  30 . Although the thermally enhanced mold compound component  22  is not immediately above the thinned flip chip dies  14 , the thermally enhanced mold compound component  22  is still close to the thinned flip chip dies  14 . Consequently, the thermally enhanced mold compound component  22  is also desired to have a high thermal conductivity and a high electrical resistivity. In this embodiment, the thermally enhanced mold compound component  22  has a lower conductivity than the thermally conductive film  20 . The thermally enhanced mold compound component  22  has a thermal conductivity between 2 w/m·k and 20 w/m·k and an electrical resistivity greater than 1E14 Ohm-cm. One exemplary material used to form the thermally enhanced mold compound component  22  is poly phenyl sulfides (PPS) impregnated with boron nitride additives. In addition, the thermally enhanced mold compound component  22  may be formed from a same or different material as the mold compound component  18 . However, unlike the thermally enhanced mold compound component  22 , the mold compound  18  does not have a thermal conductivity requirement in higher performing embodiments. In some applications, the thermally enhanced mold compound component  22  may further reside over the mold compound component  18 . 
     It will be clear to those skilled in the art that the thermally conductive film  20  may only be deposited at the bottom region of each cavity  30 , which is adjacent to the upper surface of each thinned flip chip die  14 . Herein, the thermally conductive film  20  includes two discrete sections as illustrated in  FIG. 2 , each of which is immediately above the upper surface of a corresponding thinned flip chip die  14 . The thermally enhanced mold compound component  22  resides over each section of the thermally conductive film  20  and fills each cavity  30 . In this embodiment, the thermally enhanced mold compound component  22  is in contact with the mold compound component  18 . 
     In another embodiment, the thermally enhanced semiconductor package  10  further includes a shielding structure  32  encapsulating the thermally enhanced mold compound component  22  and in contact with the module substrate  12  as illustrated in  FIG. 3 . Herein, the thermally enhanced mold compound component  22  resides over an entirety of the thermally conductive film  20  so as to provide a planarized surface of the thermally enhanced semiconductor package  10 . The shielding structure  32  helps to reduce the electromagnetic interference caused by the thinned flip chip dies  14 . 
       FIGS. 4-9  provide exemplary steps that illustrate a process to fabricate the exemplary thermally enhanced semiconductor package  10  shown in  FIG. 1 . Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 4-9 . 
     Initially, a semiconductor package  34  is provided as depicted in  FIG. 4 . For the purpose of this illustration, the semiconductor package  34  includes the module substrate  12 , two flip chip die  14 F, the underfilling layer  16 , and the mold compound component  18 . In different applications, the semiconductor package  34  may include fewer or more flip chip dies. In detail, each flip chip die  14 F includes the device layer  24 , the interconnects  26  extending from the lower surface of the device layer  24  and coupled to the upper surface of the module substrate  12 , the dielectric layer  28  over the upper surface of the device layer  24 , and a silicon handle layer  36  over the dielectric layer  28 . As such, the backside of the silicon handle layer  36  is a top surface of each flip chip die  14 F. 
     In one embodiment, each flip chip die  14 F may be formed from a SOI structure, which refers to a structure including a silicon handle layer, a silicon epitaxy layer, and a buried oxide layer sandwiched between the silicon handle layer and the silicon epitaxy layer. Herein, the device layer  24  of each flip chip die  14 F is formed by integrating electronic components in or on the silicon epitaxy layer of a SOI structure. The dielectric layer  28  of each flip chip die  14 F is the buried oxide layer of the SOI structure. The silicon handle layer  36  of each flip chip die  14 F is the silicon handle layer of the SOI structure. 
     In addition, the underfilling layer  16  resides over the upper surface of the module substrate  12 , such that the underfilling layer  16  encapsulates the interconnects  24  and underfills each flip chip die  14 F between the lower surface of the device layer  22  and the upper surface of the module substrate  12 . The mold compound component  18  resides over the underfilling layer  16  and encapsulates the flip chip dies  14 F. The mold compound component  18  may be used as an etchant barrier to protect the flip chip dies  14 F against etching chemistries such as Tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH) in the following steps. 
     Next, the mold compound component  18  is thinned down to expose the backside of the silicon handle layer  36  of each flip chip die  14 F, as shown in  FIG. 5 . The thinning procedure may be done with a mechanical grinding process. The following step is to remove substantially the entire silicon handle layer  36  of each flip chip die  14 F to create the cavity  30  and provide the thinned flip chip die  14  with the upper surface exposed to the cavity  30 , as shown in  FIG. 6 . Herein, removing substantially the entire silicon handle layer  36  refers to removing at least 95% of the entire silicon handle layer  36 , and perhaps a portion of the dielectric layer  28 . Because the silicon handle layer  36  is removed substantially, deleterious harmonic generations and intermodulation distortions at an interface between the silicon handle layer  36  and the dielectric layer  28  may be eliminated. Removing substantially the entire silicon handle layer  36  may be provided by an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, ACH, NaOH, or the like. 
     The thermally conductive film  20  is then deposited over the exposed surfaces of each cavity  30  and over the mold compound component  18  as illustrated in  FIG. 7 . The thermally conductive film  20  may also extend to thermally connect the module substrate  12 . In each cavity  30 , the thermally conductive film  20  is immediately above the upper surface of each thinned flip chip die  14  with no significant voids or defects. Depositing the thermally conductive film  20  may be provided by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) with a temperature between 150° C. and 300° C. According to different depositing processes with different materials, a protecting procedure to a lower surface of the module substrate  12 , which contains the electrical input/output contact regions, may be applied before the deposition (not shown). 
     After the thermally conductive film  20  is deposited over the exposed surfaces of each cavity  30  and over the mold compound component  18 , a thermally enhanced mold compound  22 M is applied over at least a portion of the thermally conductive film  20  to substantially fill each cavity  30  as depicted in  FIG. 8 . Notice that the thermally enhanced mold compound  22 M does not directly reside over the upper surface of the thinned flip chip dies  14 . In some cases, the thermally enhanced mold compound  22 M may further reside over the mold compound component  18 . A curing process (not shown) is followed to harden the thermally enhanced mold compound  22 M in order to form the thermally enhanced mold compound component  22 . The curing temperature is between 100° C. and 320° C. depending on which material is used as the thermally enhanced mold compound  22 M. Normally, the thermally conductive film  20  has a higher thermal conductivity than the thermally enhanced mold compound component  22 , such that the bottom region of each cavity  30  (adjacent to the upper surface of each thinned flip chip die  14 ) has better heat dissipation performance than the rest of the cavity  30 . 
     An upper surface of the thermally enhanced mold compound component  22  is then planarized to form the thermally enhanced semiconductor package  10  as depicted in  FIG. 9 . A mechanical grinding process may be used for planarization. The thermally enhanced mold compound component  20  may reside over the mold compound component  18 . Finally, the thermally enhanced semiconductor package  10  may be marked, diced, and singulated into individual components. 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.