Patent Publication Number: US-4654854-A

Title: Method and apparatus for decoding threshold-decodable forward-error correcting codes

Description:
This application is a continuation of application Ser. No. 426,421, filed Sept. 29, 1982, now abandoned. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to an improved method and apparatus for decoding threshold-decodable forward-error-correcting codes. 
     DESCRIPTION OF RELATED ART INCLUDING 
     Information disclosed under 37 CFR Sections 1.97-1.99. 
     In the design of any digital communication system, one constraint is to maintain the integrity of transmitted information within acceptable limits. Information integrity is degraded by noise and other channel impairments, which cause channel errors. A typical measure of information integrity is bit-error-rate (BER). When the information BER is high, the information contains many errors at the receiving side of a communication system and the information integrity is low. 
     Many methods have been proposed and implemented to maintain acceptable information integrity. Forward-error-correcting (FEC) codes are one such method, and threshold-decodable codes are a subclass of FEC codes. 
     Forward-error-correcting codes operate by generating redundant check digits, also called parity digits, in a device called an &#34;encoder&#34;. The parity digits are transmitted to the receiving site either multiplexed with the information or on another channel. When received, the detected information and parity digits will be found to contain errors due to noise and other impairments. If the frequency and pattern of channel errors is not too severe, the redundant data added by the encoder can be used to identify and correct the improperly-received digits. This correction procedure is implemented in a device called a &#34;decoder&#34;, which outputs an estimate of the original information stream without redundant check digits. If the frequency and pattern of channel errors is too serve, the decoder&#39;s estimate of the original information stream will be incorrect. A &#34;decoder error event&#34; occurs when the decoder&#39;s estimate of an information symbol differs from the symbol actually transmitted. Decoder error events may be classified as being of Type 1 or Type 2 according to the definitions given above. These errors are not to be confused with the underlying channel errors. 
     Threshold-decodable codes, a subclass of FEC codes, were pioneered by Massey (U.S. Pat. Nos. 3,303,333; 3,402,393; 3,566,352). With a threshold-decodable FEC code, the decoder forms a stream of error indicators called subsolution signals or syndromes. These syndromes are based on the received information and redundant check digits. Each syndrome checks several information digits, and each information digit is checked by several syndromes. 
     With error-free transmission from transmitter to receiver, all syndromes will be identically zero. When errors occur, certain syndromes will be set HIGH (=1). 
     The decoder forms a set of subsolution signals {S k  } x .sbsb.1.sub.(j) for each information digit x i .sup.(j) to be decoded. These syndromes are said to be &#34;orthogonal&#34; on the information digit being decoded, in the sense that each syndrome of the said set checks the said information digit, but no other information digit is checked by more than one syndrome of the said set. Thus, an error on some other information digit can affect at most one of the syndromes contained in said set. 
     The values of all syndromes contained in {S k  } x .sbsb.i.sub.(j) are summed (possibly with unequal weightings, although a simple arithmetic sum is generally preferred), and the resultant sum is called the decision statistic D s . D s  is compared to a decision threshold T 1 . If the threshold is equalled or exceeded, an error is declared and said information digit is corrected. 1  When the decision statistic D s  is less than decision threshold T 1 , said information digit is declared to be correct and it is passed out of the decoder as initially received. 
    
     This prior-art decoding technique, relying solely on the orthogonal set of subsolution signals, may be described as &#34;algebraic decoding&#34;, since it relies only on the algebraic properties of the code. 
     Improvements and extensions to Massey&#39;s original work were added by Kohlenberg (U.S. Pat. No. 3,447,132), Tong (U.S. Pat. Nos. 3,593,282; 2,718,905), Cain (U.S. Pat. No. 3,662,338) and En (U.S. Pat. No. 4,193,062). In particular, Kohlenberg extended the Massey system to include a capability for burst-error correction. Kohlenberg also proposed a decoder structure incorporating information on channel reliability, to disable certain syndromes from affecting the decision statistic D s  (typically, those syndromes likely to be affected by a burst of errors). Cain has elaborated the so-called guard means developed by Kohlenberg, whereby syndrome signals are disabled from affecting the decision statistic under certain conditions. 
     The invention disclosed herein differs from the work of Kohlenberg and Cain in its use of reliability information. Kohlenberg and Cain reduce the quantity of syndrome data entering certain decoder decisions, based on reliability information. The invention disclosed herein uses all relevant syndrome data in all decisions, and incorporates reliability information as additional data. Decoder performance is improved by increasing the quantity of information entering each decoder decision, rather than decreasing said quantity. 
     Tong refined the work of Massey and Kohlenberg, and proposed another use for reliability information in the decoder (U.S. Pat. No. 3,588,819). With Tong&#39;s formulation, reliability information is used to identify the probable location of channel errors. Once these locations are known, the entire power of the FEC code is applied to correcting the information digits in these locations. A so-called &#34;hard&#34; error, where an error has occurred but the measured reliability appears high, would not be corrected by this scheme. The invention disclosed herein allows correction of information digits with high measured reliability, and therefore differs from the work of Tong. 
     En, in U.S. Pat. No. 4,193,062, discloses a rate=1/2, triple-error-correcting code. 
     SUMMARY OF THE INVENTION 
     This invention embodies improved methods for decoding threshold-decodable forward-error-correcting (FEC) codes. 
     It is shown in this disclosure that decoder error events (errors in the decoded information stream generated by the decoder) are of two types: (1) Type 1 error. An information digit is received and demodulated incorrectly, but the decoder fails to correct it. (2) Type 2 error. An information digit is received and demodulated correctly, but the decoder inverts it (thereby inserting an error). 
     This invention embodies three methods for reducing the incidence of Type 1 and Type 2 errors: 
     1. Method 1 reduces the incidence of Type 1 errors. When a threshold decoder&#39;s decision sttatistic approaches the algebraic correction threshold, but fails to cross it, there is a chance that a Type 1 error is incipient. (i.e. the information digit was truly in error, but other errors on the channel degraded the decision statistic to a point below the threshold). Under this condition, a limited search is initiated for an information digit with low reliability. If such an information digit is found, it is corrected. With some codes, reliability information on the received parity digits is used as an additional signal to enable or disable this search. 
     2. Method 2 reduces the incidence of Type 2 errors. Occasionally the decoder&#39;s decision statistic will exceed the correction threshold even when the information digit being decoded is correct. This typically occurs while many error indications (syndromes) are passing through the decoder&#39;s decision circuit, which leads to ambiguity. Method 2 operates by examining an extended stream of syndrome digits for correlated error indications. This method also examines the reliability of the information digit subject to correction. If the syndrome pattern indicates an error pattern beyond the error correcting capability of the code, and the reliability of the information digit is high, the correction signal generated by the decoder is disabled. 
     3. Method 3 reduces the incidence of Type 2 errors, and may be substituted for Method 2 with the use of certain codes. This method controls decoder activity based only on the decision statistic and the measured information bit reliability. Examination of correlated syndromes, as in Method 2, is not implemented. 
     When the decoder&#39;s correction decision appears unambiguous (i.e., the correction threshold is met or exceeded, and the syndrome pattern indicates a correctable error pattern), the improved decoder emulates prior art. 
     A principle object of this invention is to increase the accuracy of threshold-decodable FEC codes. 
     Another object of this invention is to achieve the desired improvement without significant increase in decoder complexity--thereby preserving the threshold decoder&#39;s primary advantage of simplicity. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, advantages and features of the invention will become clear when considered with the following specification and accompanying drawings wherein: 
     FIG. 1 is a block diagram for an encoder known in the prior art, for producing a forward-error-correcting, threshold-decodable code, 
     FIG. 2 is a block diagram for a decoder known in the prior art, for decoding the code produced by the encoder of FIG. 1, 
     FIG. 3 is a block diagram for a decoder incorporating this invention that decodes the code produced by the encoder of FIG. 1, 
     FIG. 4 is a detail of one part of the decision means disclosed in FIG. 3, illustrating a means for detecting most partially-masked channel errors, and generating correction signals to be applied thereto, and 
     FIG. 5 is a detail of the second part of the decision means disclosed in FIG. 3, illustrating a means for detecting most channel errors correctable by the prior art decoder of FIG. 2, but further incorporating a guard means to disable corrective action in most cases where the prior art decoder of FIG. 2 would erroneously invert an information bit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As an example of threshold decoding that will prove useful below, FIG. 1 and FIG. 2 illustrate the encoder and decoder for a rate=2/3 single-error-correcting threshold-decodable FEC coding system known in the prior art. This system conforms to the work of Massey and Kohlenberg. A binary communication channel is assumed. The system will correct any isolated burst of errors less than or equal to 3.increment. channel bits in length. In addition, it will correct isolated random errors. 
     Following the practice of previous investigators, notation is adopted wherein subscripts indicate time intervals and superscripts indicate information streams into the encoder or out of the decoder. 
     The encoder forms parity bits by the modulo-2 addition of selected information bits: 
     
         p.sub.i =x.sub.i-5.increment.-3.sup.(1) ⊕x.sub.i-4.increment.-2.sup.(1) ⊕x.sub.i-3.increment.-2.sup.(2) ⊕x.sub.i-2.increment.-2.sup.(2) (Eq. 1) 
    
     This is achieved through the combination of delay means 101, 102, 103, and 104, and modulo-2 adders 105, 106, and 107. The original information plus parity is transmitted over one or more imperfect channels, detected by a receiver, and passed to the decoder (FIG. 2). The decoder attempts to correct errors in received streams r i .sup.(j), thereby improving the estimate, x i .sup.(j), of the originally encoded data x i .sup.(j). 
     Errors are represented in the notation as: 
     e i .sup.(j) =1 if an only if r i .sup.(j) ≠x i .sup.(j) 
     ε i  =1 if and only if ρ i  ≠p i   
     Thus, ##EQU1## 
     The decoder forms a syndrome S i  composed of error components: 
     
         S.sub.i =e.sub.i-5.increment.-3.sup.(1) ⊕e.sub.i-4.increment.-2.sup.(1) ⊕e.sub.i-3.increment.-2.sup.(2) ⊕e.sub.i-2.increment.-2.sup.(2) ⊕ε.sub.i                                      (Eq. 3) 
    
     These syndromes propogate through the syndrome register composed of delay elements 206, 207, and feedback correction elements 211, 212, 213. Selected syndromes are processed by AND gates 214, 215, to form correction signals C 1  and C 2 . ##EQU2## Where   represents a logical AND. The primed syndromes indicate potential prior feedback corrections. The effective decision threshold in this case is T 1  =2. 
     The syndromes composing C 1  are orthogonal on x i-5 .increment.-3.sup.(1), in the sense that e i-5 .increment.-3.sup.(1) is the only common error component in S i  and S i- .increment.-1 &#39;. When e i-5 .increment.-3.sup.(1) =1 (i.e., r i-5 .increment.-3.sup.(1) is in error), but no other error component of S i  or S i- .increment.-1 &#39; has value equal to 1, both inputs to AND gate 215 have value=1. This drives C 1  high, causing r i-5 .increment.-3.sup.(1) to be inverted and corrected. S i  is also inverted, removing the error indication. When a single error component exists in S i  and S i-5 .increment.-3 &#39;, but the error is not on r i-5 .increment.-3.sup.(1), only one of the syndromes will have value=1. The operation AND gate 215 thereby sets C i  =0, and r i-5 .increment.-3.sup.(1) will be accepted as being correct. 
     Similar arguments apply to C 2  and r i-3 .increment.-2.sup.(2). 
     When more than one error affects the syndromes forming C k , k=1,2, the decoder may still respond correctly. If both errors occur on bits within the same syndrome, and neither error is on the information bit subject to correction signal C k , then the syndrome remains zero, and no bit inversion takes place. This is the desired effect, since the information bit was received correctly. 
     On the other hand, the decoder will sometimes respond incorrectly in the presence of two or more channel errors when those errors affect the syndromes forming C k . 
     Using the symbolism of statistical theory, consider the decoder to form the null hypothesis H 0  : the bit subject to correction was received incorrectly. Then, with two channel errors embedded in the syndromes forming C k , Type 1 and Type 2 errors occur as follows: 
     Type 1 Error (H 0  is rejected when it is true). 
     The information bit was received incorrectly, but the decoder fails to invert it. A secondary error &#34;cancels out&#34; an error indication in one of the syndromes (only one syndrome is affected due to orthogonality). Since only one syndrome remains with value=1, C k  =0 and the information bit is not inverted. 
     Type 2 Error (H 0  is accepted when it is false). 
     The information bit was received correctly, but the decoder inverts it. This occurs when the two errors affect different syndromes. Both syndromes have value=1, and this condition is indistinguishable from a single error on the information bit being checked. As a result, C k  =1 and the decoder inverts the received information bit. 
     The error processes leading to Type 1 and Type 2 errors occur in other threshold decoding systems, with only slight differences based on the number of syndromes entering a decision, and the guaranteed error-correcting capability of the code. 
     DESCRIPTION OF THE INVENTION 
     Three methods are disclosed. Method 1 reduces the incidence of Type 1 errors. Methods 2 and 3 reduce the incidence of Type 2 errors. The three methods can be used independently or in various combinations. 
     The invention can be specifically applied, with desirable effect, to decoding the following codes: 
     (1) The generalized Rate=(n-1)/n, single-error-correcting code developed by Massey in U.S. Pat. No. 3,566,352. 
     (2) The Rate=1/2, double-error-correcting code developed by Massey. 
     (3) The Rate=1/2 triple-error-correcting code developed by En in U.S. Pat. No. 4,193,062. 
     (4) All of the above codes, modified according by Kohlenberg&#39;s scheme, disclosed in U.S. Pat. No. 3,477,132, to correct isolated bursts of errors as well as scattered random errors. 
     In addition, it is assumed that the invention may be applied to decoding all members of the general class of threshold decodable forward-error-correcting codes. 
     METHOD FOR REDUCING THE INCIDENCE OF TYPE 1 ERRORS 
     In most error patterns that would normally result in a Type 1 Error, two conditions exist simultaneously: 
     A. Of all syndromes that check the information digit r i .sup.(j) being decoded, the number of syndromes with value=1 is greater than or equal to a threshold T 2  defined below, but less than the algebraic decision threshold T 1  : ##EQU3## 
     Where the {S k  } is the set of syndromes checking said information digit, and only the syndromes with value=1 contribute to the sum. 
     B. A reliability measurement R i .sup.(j) made on said information digit indicates low reliability. 
     Condition A is just the condition for a Type 1 error in a state-of-the-art hard decision threshold decoder employing a single threshold T 1 . Condition B recognizes that most errors are associated with characteristics and observable qualities in the received analog waveform. These qualities can be used to test the reliability of received channel digits. 
     The invention defines a threshold T 2 , such that 
     
         0&lt;T.sub.2 &lt;T.sub.1 
    
     T 1  is the algebraic decision threshold (without resort to the methods disclosed herein). T 2  is another threshold, an integral part of this invention. If the decision statistic equals or exceeds T 2  but is less than T 1 , and the reliability R i .sup.(j) of the information digit being decoded is low, said digit is corrected. Let Y A  be a logical variable with value=1 when ##EQU4## and value=0 otherwise. Let Y B  be a logical variable with value=1 when R i .sup.(j) is HIGH, and value=0 otherwise. The invention defines a new correction signal C y  to be applied to r i .sup.(j) : 
     
         C.sub.y =Y.sub.A Y.sub.B                                   (Eq. 5) 
    
     where implied multiplication is a logical AND, and the overbar indicates logical negation. When C y  =1, correction of r i .sup.(j) is ENABLED despite the failure of D s  to meet or exceed T 1 . 
     Optimum selection of T 2 , and the reliability test yielding R i .sup.(j), depends on the code being employed and the expected channel conditions. For example, a typical reliability test for a channel characterized by additive white Gaussian noise (AWGN) would be so-called alpha-flunk or null-zone test. In such a test, a channel digit with anomolously small signal amplitude would be assigned a low reliability. Alternatively, a typical reliability test in a jamming environment would test for an anomolously large signal amplitude. Such a condition would indicate the probable action of a jammer, and therefore imply low reliability. 
     A single reliability test may be applied uniformly to all received digits. Alternatively, reliability tests may be designed separately for each stream of channel digits entering the decoder (e.g., in the R=2/3 code illustrated in this disclosure, {ρ i  }, {r i .sup.(1) } and {r i .sup.(2) } represent the three streams of channel digits into the decoder). 
     When T 2  is large, a syndrome pattern {S k  } x .sbsb.i.sub.(j) with ##EQU5## will point toward r i .sup.(j) without significant ambiguity. When T 2  is small--in particular when T 2  =1 as in the generalized rate=(n-1)/n code developed by Massey--it frequently will be equalled or exceeded due to random errors even when r i .sup.(j) was received correctly. This would lead to false alarms, and induced Type 2 errors due to operation with the lower threshold. Decoders employing a small T 2  must therefore include a guard means to disable attempted correction based solely on T 2  and R i .sup.(j). This guard means may employ a combination of methods, including examination of parity digit reliability R i .sup.ρ and correlated correction decisions based on T 1 . Specific methods depend on the code being implemented, but the general concepts are: 
     (1) Discount, wholly or partially, syndromes based on parity digits with low measured reliability. 
     (2) Since a correction based on decision threshold T 1  is inherently more reliable than a correction based on T 2 , the decoder should first attempt to assign syndromes to decision sets {S k  } such that D s  ≧T 1 . Corrective action based on threshold T 2  should only be attempted with syndromes excluded from such decision sets. 
     Such a guard means is described and illustrated below in the particular case of Massey&#39;s rate=2/3, single-error-correcting code. 
     In all embodiments of the invention, correction signals C y  are fed back into the syndrome register (in addition to enabling correction of information digits). This feedback removes the effects of detected errors from future correction decisions. 
     METHODS FOR REDUCING THE INCIDENCE OF TYPE 2 ERRORS 
     In most error patterns that would normally result in a Type 2 error, three conditions exist simultaneously: 
     A. ##EQU6## 
     B. R i .sup.(j) is high 
     C. Some syndromes that are not members of the decision set {S k  }, but that contain error components in common with the members of {S k  }, have value=1. 
     Condition A enables corrective action by a state-of-the-art hard decision threshold decoder employing a threshold T 1 . In most cases, this will be the appropriate response to an information digit that was received incorrectly. But it is also the condition for a Type 2 error when said information digit was received correctly. Condition B recognizes the fact that most digits received correctly will have a high mesasured reliability, whereas most digits received incorrectly will have a low measured reliability. Condition C recognizes the fact that, when a Type 2 error exists, the underlying channel errors will usually be associated with their own patterns of syndromes. This becomes more likely as the code rate increases, thereby increasing the proportion of information digits to parity digits. 
     The invenion, in using method 2, tests for the existence of conditions B and C, in addition to the threshold test defined by prior art (condition A). Let Z A  be a logical variable with value=1 when condition A is satisfied, and value=0 otherwise. Similarly, let Z B  and Z C  be logical variables defined on conditions B and C respectively. The invention combines these logical variables to yield a correction signal C i  &#39;: 
     
         C.sub.i &#39;=Z.sub.A (Z.sub.C +Z.sub.B Z.sub.C)               (Eq. 6) 
    
     where implied multiplication is a logical AND, addition is a logical OR, and the overbar indicates logical negation. Thus, an isolated channel error will yield Z C  =1 and the correction signal follows Z A  as in prior art. When the information digit subject to correction by C i  &#39; is correct, but Z A  =1 due to the influence of other channel errors, Z B  =Z C  =1 with high probability. Thus, the influence of Z B  will DISABLE Z A  in most cases that would normally result in a Type 2 decoder error. In other words, when Z C  =1, (implying an ambiguous syndrome pattern) Z A  is only ENABLED when Z B  =0 (implying low reliability on the information digit subject to correction). An example of this method for reducing the incidence of Type 2 errors is given below, for the Massey rate=2/3 single-error-correction code. 
     With some codes, particularly codes where the number of syndrome digits in the decision set D s  is larger than T 1 , a third method may be employed in lieu of method 2, to reduce the incidence of Type 2 errors. In this third disclosed method, a new decision threshold T 3  is defined such that T 1  &lt;T 3  ≦n. 
     With this method, reliability of the information digit is used in the correction decision when T 1  ≦D s  &lt;T 3 . 
     In this range, the information digit checked by {S k  } will be corrected by the decoder if it has low reliability, but will be passed out of the decoder as initially received if it has high reliability. 
     When T 3  ≦D s , the improved decoder emulates prior art and the information digit checked by {S k  } is corrected regardless of its measured reliability. 
     Defining Z A  and Z B  as above, ##EQU7## In all embodiments of the invention, correction signals C i  &#39; generated by method 2 or 3 are fed back into the syndrome register (in addition to ENABLING correction of r i .sup.(j). This feedback removes the effects of detected errors from future correction decisions. 
     SPECIFIC IMPLEMENTATON OF THE INVENTION AS IT RELATES TO THE RATE=2/3 SINGLE-ERROR-CORRECTING AND BURST-ERROR-CORRECTING THRESHOLD DECODABLE CODE OF MASSEY AND KOHLENBERG 
     FIG. 3 illustrates a decoder for binary data incorporating the disclosed invention. The decoder is designed for the Rate=2/3 Massey coding system, as adapted after Kohlenberg to correct bursts of errors as well as single errors. Not shown, but implicitly present, are: (1) a receiver capable of generating an estimate of the transmitted channel bit, plus a one-bit measure of reliability; and (2) a device for presenting said receiver output to the decoder along the input lines shown. 
     Following the notation defined previously, r i .sup.(1), r i .sup.(2) and ρ i  are the estimates of transmitted information and parity bits generated by the receiver. R i .sup.(1), R i .sup.(2) and R i .sup.ρ are the one-bit reliability measures relating to r i .sup.(1), r i .sup.(2), and ρ i , respectively. The reliability test should be selected and designed to optimize the performance of the decoder. 
     As illustrated in FIG. 3, the improved decoder adopts certain elements of prior art. These are indicated by device numbers 201-213, as initially defined in FIG. 2. However, the correction signals applied to correction means 209, 210, 211, 212, 213 differ from the correction signals of prior art. The invention is implemented through the use of new circuit elements 301-313. New correction signals C 11 , C 12 , C 21 , C 22 , and C.sub.Σ are defined. In addition, the correction signals C 1 , C 2  illustrated in FIG. 2 are replaced by correction signals C.sub.Σ &#39;, C 1  &#39;, C 2  &#39;. 
     Syndrome digits S i  are generated according to prior art. 
     After participating in syndrome generation, information digits are passed to the new correction means consisting of delay means 302, 304, 306 and inversion means 301, 303, 305, 307. These elements are exercised to reduce the incidence of Type 1 decoder errors (relative to prior art). 
     At time t i  when r i .sup.(1), r i .sup.(2), ρ i  are presented to the syndrome generator, information bits r i-5 .increment.-3.sup.(1) and r i-3 .increment.-2.sup.(2) are passed to said correction means. 
     Said correction means corrects most channel errors that would have appeared as Type 1 decoder errors in prior art. Correction signals C 11 , C 12 , C 21 , and C 22  indicate the probable presence of an incorrect r i .sup.(j) where an additional error acts to degrade one of the two syndromes checking said r i .sup.(j). 
     Said correction signals are generated in decision means 313, described below. 
     After exiting said correction means consisting of 301-307, information bits pass through a further correction stage where correction signals C 1  &#39; and C 2  &#39; are applied. Said correction signals indicate the presence of all single isolated errors (as in prior art). Furthermore, said correction signals are disabled in the presence of most channel errors that would have appeared as Type 2 decoder errors in prior art. Said correction signals are generated in decision means 313, described below. 
     After undergoing possible corrective action by signals C 1  &#39;, C 2  &#39;, the processed bit streams are realigned by delay element 205 and offered as estimates {x i-6 .increment.-4.sup.(1), x i-6 .increment.-4.sup.(2) } of the transmitted information {x i-6 .increment.-4.sup.(1), x i-6 .increment.-4.sup.(2) }. 
     As illustrated in FIG. 3, the syndrome register is augmented relative to prior art by additional delay elements 309, 311, 312 and correction stages 308, 310. All correction stages act to remove the effects of previously detected errors from current and future decisions. The syndrome register is tapped along its length to generate signals A 1 , A 2 , A 3 , A 4 , A 4  &#39;, A 5 , A 6 . These signals are inputs to decision means 313. 
     The decision means 313 takes as input said syndrome signals A 1 , A 2 , A 3 , A 4 , A 4  &#39;, A 5 , and A 6  and the reliability measurements R i .sup.(1), R i .sup.(2), R i .sup.ρ. Said decision means outputs correction signals C 11 , C 12 , C 21 , C 22 , C.sub.Σ, C 1  &#39;, C 2  &#39;, C.sub.Σ 40 . Said correction signals are applied to the information streams and syndrome stream to correct probable errors and remove the effects of said errors from future decisions. 
     Decision means 313 is detailed in FIGS. 4 and 5. FIG. 4 illustrates an embodiment of the Type 1 error reduction means. FIG. 5 illustrates an embodiment of the Type 2 error reduction means, combined with a means to detect almost all channel errors correctable with the prior art decoder of FIG. 2. 
     The Type 1 error reduction means of FIG. 4 generates correction signals C 11 , C 12 , C 21 , C 22 , C.sub.Σ. A correction signal has value=1, thereby inverting an information bit and one or two syndrome bits, when: 
     A. Said information bit had low measured reliability, and 
     B. Only one of the syndromes checking said information bit had value=1, and 
     C. The parity bit entering into the syndrome with value=1 had high reliability. Note that, since T 2  is small (T 2  =1 for this decoder), a guard means is incorporated to avoid excessive occurrence of induced Type 2 errors. The guard means is incorporated in condition C. 
     Consider the stream of syndrome bits propogating through the syndrome register illustrated in FIG. 3. With the code illustrated here, error indications usually occur in pairs. These paired indicators are separated by .increment. or (.increment.+1) positions, and identify probable errors on particular information bits. When a syndrome is not paired in this manner, it is either due to: (1) a channel error on the parity bit affecting said syndrome; or (2) a combination of two channel errors that would result in a Type 1 decoder error with a prior art decoder of FIG. 2. These two cases are differentiated by the Type 1 error reduction means, which is implemented to correct received bits r i .sup.(j) as they come under the influence of correction signals C 11 , C 12 , C 21 , C 22 . The four correction stages are illustrated in FIG. 3 as correction means 301, 303, 305, 307. Most errors on parity bits are ignored. 
     Information bit reliability is presented to the circuit by R i .sup.(1) and R i .sup.(2). These are combined with delay means 410, 411, 412, 413, and inversion means 414, 415, 416, 417 to present signals to AND gates 418, 419, 420, 421. A particular signal has value=1 if the information bit correctable by the AND gate had low measured reliability. The signal is zero otherwise. This supports implementation of condition A stated above. 
     Condition B is implemented by the unpaired syndrome detection means 401-407. When syndromes are paired to indicate an error on a particular information bit, they will appear simultaneously on input lines A 1  and A 3 , or A 1  and A 4 . This will cause a HIGH input to OR gate 403. Operation of 403, in combination with delay means 404, 405, and NOR gate 406, causes u 0  =0 when each of said syndromes appear at A 4 . Likewise, the operation of AND gate 407 causes the output of the unpaired syndrome detection means u 1  =0.  This drives u 3  LOW, thereby disabling correction signals C 11 , C 12 , C 21 , and C 22 . In these cases, involving paired syndromes, corrective action is implemented by decision means illustrated in FIG. 5, and described below. Alternatively, in most cases involving an unpaired syndrome, said syndrome will appear at A 4  while u 0  =1. This causes u 1  =1, thereby supporting condition B above. 
     Condition C is implemented by reliability input R i .sup.ρ, in combination with delay means 409. U 2  =1 when the parity bit affecting the syndrome bit appearing at A 4  has high reliability. U 2  =0 otherwise. 
     When conditions A, B, and C are satisfied for a particular received information bit, the correction signal affecting said bit will be HIGH. This signal is modulo-2 added to said bit in the new correction means illustrated in FIG. 3. It is further employed to invert the syndrome giving rise to corrective action. It is even further used to invert the syndrome with value=0, which checks the said information bit. With the embodiment of FIG. 4, this last inversion is carried out when said syndrome with value=0 is trailing the syndrome that triggered corrective action. With addition delay elements and slight redesign, however, inversion could be applied regardless of relative syndrome positions. 
     Correction signals C 11 , C 12 , C 21 , C 22  are calculated simultaneously. This is required by the common use of certain input signals. As a consequence of simultaneous decision-making, C.sub.Σ is generated and applied to 211 (in FIG. 3). The syndrome at this position enters all decisions leading to correction signals C 11 , C 12 , C 21 , C 22 . The syndrome feedback correction means 211 (of prior art) is in the correct position to apply C.sub.Σ. Its function is therefore redefined by the disclosed invention. Rather than apply a feedback correction signal C 1 , it is used to apply a common feedback correction signal C.sub.Σ due to the new Type 1 Error Reduction Means. (The function of C 1  is supported by C.sub.Σ &#39; described below). 
     The error detector means of FIG. 5 supports two goals: 
     A. It detects almost all channel errors that would have been detected by the prior art decoder of FIG. 2; and 
     B. It further detects almost all syndrome patterns that would result in a Type 2 decoder error, if said syndrome pattern were to be applied to the prior art decoder of FIG. 2. 
     While a small fraction of algebraically-correctible errors remain uncorrected with the means of FIG. 5, this shortfall is compensated and overshadowed by the large number of potential Type 2 decoder errors that are avoided. 
     The error detector for channel 1 will be described. Operation of the detector for channel 2 may be understood by analogy. 
     The goal of this error detector (for channel 1) is to set correction signals C 1  &#39; and C.sub.Σ &#39; HIGH (=1) when A 4  &#39;=A 6  &#39;=1--but to avoid this setting action when the information bit subject to correction is actually correct. 
     The single error detector means 501, representing prior art, identifies (1) all channel error events correctible by prior art, and (2) all syndrome patterns that would result in a Type 2 decoder error using prior art. It is the purpose of the remaining circuit elements to separate these two conditions, and only ENABLE the correction signals under condition 1. Circuit elements 502-508 (and 520) represent new elements of the invention disclosed herein. 
     In a potential Type 2 decoder error event, (condition (2) above), an underlying channel error acting on an information bit will cause two syndromes with value=1. One of said syndromes is an element of {A 4  &#39;, A 6  }, thereby contributing to the potential Type 2 error event. The other said syndrome is an element of {A 1 , A 2 , A 5  }. This latter set includes all syndromes that cross-check the error components found at {A 4  &#39;, A 6  }. If any of {A 1 , A 2 , A 5  } have value=1, it is an indication of a potential Type 2 error event. This test is implemented by OR gate 503 which outputs signal u 5 . 
     When all of {A 1 , A 2 , A 5  } have value=0, the improved decoder declares low probability of a Type 2 error, and the algebraic correction signal u 4  (of prior art) is ENABLED. This is achieved through the logic chain 504, 505 which sets u 9  HIGH thereby ENABLING u 4 . 
     u 4  is similarly ENABLED if u 5  =1, but the reliability of the information bit subject to correction is LOW. In this case, u 7  =0 but u 6  =u 8  =u 9  =1 thereby ENABLING u 4 . 
     When u 5  =1 and the information bit reliability is HIGH, u 6  =u 8  =u 9  =0 thereby DISABLING u 4 . In this case, the probability that the information bit is correct outweighs the probability that it is incorrect. 
     The correction signals generated by this error detector are applied to the information and syndrome streams as illustrated in FIG. 3. 
     In the prior art decoder of FIG. 2, correction signal C 1  is implicitly calculated prior to C 2 . In the disclosed invention, C 1  &#39; and C 2  &#39; are calculated simultaneously. Since a subset of the decision inputs are common to C 1  &#39; and C 2  &#39;, this yields improved performance. A consequence of simultaneous decision-making is the generation of C.sub.Σ &#39;. This is applied at syndrome feedback correction means 212, implementing the joint functions of correction means 211, 212 illustrated in FIG. 2.