Patent Publication Number: US-6667653-B2

Title: Threshold voltage-independent MOS current reference

Description:
This is a division of patent application Ser. No. 10/002,982, filing date Nov. 11, 2001, now U.S. Pat. No. 6,570,436, Threshold Voltage-Independent Mos Current Reference, assigned to the same assignee as the present invention. 
    
    
     BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The invention relates to a current reference circuit, and more particularly, to a threshold voltage-independent MOS current reference circuit. 
     (2) Description of the Prior Art 
     Current and voltage reference circuits are widely used in analog designs. A particularly difficult problem encountered in MOS reference circuit designs is caused by the large variation in threshold voltage (V th ) that often occurs in CMOS processing. Since the voltage-to-current transfer response of the MOS transistor depends on the value of V th , large variations in V th  can cause large variation in the actual current or voltage output of the reference circuit. It is desirable, therefore to eliminate V th  dependence in the reference output. 
     However, prior art attempts to eliminate the V th  component typically rely on complicated voltage addition techniques to create a V x +V th . These techniques create several problems due to the use of differing operation points, or modes, for different MOS devices. Therefore, mismatch problems are a major drawback. 
     Several prior art inventions describe voltage or current reference circuits. U. S. Pat. No. 5,739,682 to Kay describes a reference substantially independent of the threshold voltage of the transistor providing the reference. A pair of MOS transistors has gate voltages made equal. The current through the first transistor is very small. The current through the second transistor is equal to the first current multiplied by a scaling factor. Since the first current is so small, the second current through the second transistor is essentially not dependent upon the threshold voltage. U.S. Pat. No. 5,910,749 to Kimura teaches a current reference with no temperature dependence. Both bipolar and MOS embodiments are disclosed. U.S. Pat. No. 4,723,108 to Murphy et al describes a circuit to compensate for MOS transistor performance changing over temperature and manufacturing variation. Changing Vth, caused by temperature, is compensated by changing the mobility in the opposite direction. The gate drive of a MOS device is thereby compensated. U.S. Pat. No. 5,315,230 to Cordoba et al teaches a reference voltage generator circuit that compensates for temperature and VCC variation. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide an effective and very manufacturable current reference circuit. 
     A further object of the present invention is to provide a current reference circuit comprising MOS devices. 
     A still further object of the present invention is to provide an MOS current reference circuit that is independent of the threshold voltage to thereby reduce reference current variation due to processing variation. 
     Another still further object of the present invention is to provide a nearly zero temperature coefficient current reference using this novel MOS current reference circuit. 
     In accordance with the objects of this invention, a new current reference circuit is achieved. This current reference circuit uses MOS transistors. However, the reference value does not depend upon the threshold voltage. The circuit comprises, first, a first MOS transistor having gate, drain, and source. A gate voltage value is coupled from the gate to the source. A second MOS transistor has gate, drain, and source. The second MOS transistor is of the same size and type as the first MOS transistor. The source is coupled to the first MOS transistor source. The gate voltage value plus a delta voltage value is coupled from the gate to the source. A means is provided for forcing a drain voltage value from the drain to the source of the first MOS transistor and from the drain to the source of the second MOS transistor. The first MOS transistor and the second MOS transistor conduct drain currents in the linear mode. Finally, a means is provided for subtracting the first MOS transistor drain current from the second MOS transistor drain current to thereby create a current reference value. The current reference value does not depend upon the threshold voltage of the first and second MOS transistors. The circuit may be further applied to create a nearly zero temperature coefficient current reference. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings forming a material part of this description, there is shown: 
     FIG. 1 illustrates a first preferred embodiment of the present invention. 
     FIG. 2 illustrates a first preferred embodiment of the present invention, using NMOS transistors, including a means of forcing a drain voltage and a means of subtracting the drain currents to thereby create the current reference. 
     FIG. 3 illustrates the second preferred embodiment of the present invention, using PMOS transistors, including a means of forcing a drain voltage and a means of subtracting the drain currents to thereby create the current reference. 
     FIG. 4 illustrates the application of the present invention in a nearly zero temperature coefficient current reference circuit. 
     FIG. 5 illustrates the current versus temperature performance of the nearly zero temperature coefficient current reference circuit. 
     FIG. 6 illustrates an exemplary circuit for creating a positive voltage coefficient voltage depending upon the thermal voltage (V T ). 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiments disclose the novel current reference circuit of the present invention. In the first embodiment, a matched pair of AMOS transistors is used to create the threshold voltage-independent current reference. In the second preferred embodiment, a matched pair of PMOS transistors is used in an inverted version of the present invention. Finally, the invention is applied to a near zero temperature coefficient (TC) current reference. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention. 
     Referring now to FIG. 1, a first preferred embodiment of the present invention is illustrated. Several important features of the invention are shown. The circuit comprises a matching pair of MOS transistors, N 1   10  and N 2   14 . Each transistor, N 1   10  and N 2   14 , is of the same type and size, and more preferably, is oriented in the same layout direction. Even though the novel technique of the invention eliminates V th  from the current reference final value, other parameters, such as mobility, or μ o , and gate capacitance, C ox , should still be made to match as closely a possible between the two transistors. A significant advantage of the present invention is the elimination of the V th  dependence in the current reference. By comparison, μ o  and C ox  process variance is found to be much less than that of V th . 
     The first MOS transistor, N 1   10 , has a gate voltage value, V 1    26 , coupled from the gate to the source. The second MOS transistor, N 2   14 , has the source coupled to the first MOS transistor source at the V SS  node  42 . A second gate voltage value, V 2    30 , is coupled from tho gate to the source of N 2   14 . The second gate voltage value, V 2    30 , comprises the first gate voltage value, V 1    26 , plus a delta voltage value, ΔV. 
     A means is provided for forcing a drain voltage value, V D    34  and  38 , from the drain to the source of the first MOS transistor, N 1   10 , and from the drain to the source of the second MOS transistor, N 2   14 . Most importantly, both transistors,  10  and  14 , are biased to operate in the linear mode. To insure that both devices are in the linear mode, the gate voltages, V 1    26  and V 2    30 , are much larger than a the drain voltage, V D    34  and  38 . In the linear mode, a direct relationship exists between the gate voltage and the drain current as given by: 
     
       
           I   D =(μ o   C   ox   W/L ) ( V   G   −V   th   −V   D /2) V   D , 
       
     
     where W/L is the width to length ratio. In this mode, the gate voltages must be larger than the threshold voltage to insure that both transistors are in strong inversion. The first MOS transistor, N 1   10 , generates a current, I 1 . The second MOS transistor, N 2   14 , generates a current, I 2 . 
     Finally, a means,  18 , is provided for subtracting the first MOS transistor N 1   10  drain current I 1  from the second MOS transistor N 2   14  drain current I 2  to thereby create a current reference value, I REf . The subtracting means  18  creates the current reference output, I REF , where I REF =I 2 −I 1 . 
     Substituting the gate and drain voltage values into the linear mode drain current equation, we find: 
     
       
           I   1 =(μ o   C   ox   W/L ) ( V   1   −V   th   −V   D /2) V   D , 
       
     
     and 
     
       
           I   2 =(μ o   C   ox   W/L ) ( V   1   +ΔV−V   th   −V   D /2) V   D . 
       
     
     Since, I REF =I 2 −I 1 , we can solve the drain equations for I REF , yielding: 
     
       
           I   REF =(μ o   C   ox   W/L ) (Δ V ) V   D . 
       
     
     We note from this result that the V th  term has been canceled. Therefore, the resulting current reference value does not depend on the threshold voltage. Since the resulting reference does still depend upon both mobility and gate capacitance, I REF  is also called I μCox . 
     Referring now to FIG. 2, the first preferred embodiment is illustrated in greater detail to show a realized circuit implementation of the invention concept. The matched NMOS transistor pair comprises N 1   50  and N 2   54 . Once again, the sources of N 1  and N 2  are coupled together while the gates are coupled to V 1  and V 1 +ΔV such that the gate drive differs by the delta voltage, ΔV. The gate voltages, V 1  and V 1 +ΔV, are biased much higher than the drain voltage, V D , so that the MOS devices are operating in the linear mode. 
     The means to force the drain voltage value, V D    34  and  38 , from the drain to the source of both N 1  and N 2   14  is provided by two voltage followers comprising the operation amplifiers  74  and  78  and the output transistors, N 3   66  and N 4   0 . Due to the large input impedance and the high gain of the operation amplifiers  74  and  78 , the drain voltages, V D1  and V D2  are guaranteed to be driven to the reference drain voltage value, V D    82 . Further, the voltage follower arrangement isolates the drain reference voltage, V D , from the actual drains of the first and second MOS transistors, N 1   50  and N 2   54 . 
     The means for subtracting the drain currents, I 1  and I 2 , is provided by the PMOS transistors, P 1   90 , P 2   94 , P 3   98 , and P 4   102 . The gate and drain of P 1   90  are coupled together and further coupled to the gate of P 2   94  at the node A  106 . P 1   90  and P 2   94  are the same type of device and are the same size. Further, the sources of P 1   90  and P 2   94  are coupled together at V CC    118 . Therefore, P 1   90  and P 2   94  form a current mirror. Since P 1   90  must conduct I 1 , the mirror configuration causes P 2   94  to likewise conduct a drain current of I 1 . 
     MOS transistors P 3   98  and P 4   102  form a second current mirror. Once again, the gate and drain of P 3   98  are coupled together and further coupled to the gate of P 4   102 . P 3   98  and P 4   102  are another matched pair. Therefore, the drain current of P 3   98  is mirrored by the drain current of P 4   102 . 
     As an important feature, the drain of P 3   98  is coupled to the drain of P 2   94  at node B  110 . As discussed above, the greater gate drive (V 1 +ΔV) on N 2   54  creates a drain current, I 2 , which is larger than the drain current I 1  of N 1   50 . Because P 2   94  is biased to conduct only I 1 , P 3   98  will conduct the difference between I 1  and I 2 . Therefore, the P 3   98  current is given by I 2 −I 1 . Finally, the P 3  current is simply mirrored to the output current reference as I 2 −I 1 . As shown above, the subtraction of I 2  from I 1  effectively eliminates the V th  term from the output current, I μCox . 
     Referring now to FIG. 3, the second preferred embodiment of the present invention is illustrated. In this case, the circuit is inverted such that the main mirroring devices comprise the PMOS transistors P 1   216  and P 2   220 . The analysis of operation of the circuit is the same as for the first embodiment of FIG.  2 . In this second embodiment case of FIG. 3, the output current reference, I μCox , is a sinking current rather than a sourcing current as in FIG.  2 . 
     Referring now to FIG. 4, an important application of the voltage-threshold independent current reference of the present invention is illustrate. In this application, the novel circuit is used to create a nearly zero temperature coefficient (TC) current source. 
     First, a first voltage-threshold independent current reference  304  is used to form a positive temperature coefficient current reference circuit  304 . The gate voltage for the voltage-threshold independent current reference  304 l comprises a positive temperature coefficient value. The delta voltage value, ΔV  328 , comprises a positive temperature coefficient value, mV T  where V T  is the thermal voltage and m is a constant. The drain voltage value, V D    324 , comprises another positive temperature coefficient value, kV T , where k is another constant. 
     Once again, the output of the current reference  304  is given by: 
       I   REF =(μ o C ox   W/L ) (Δ V ) V   D . 
     Since ΔV=mV T  and V D =mV T , the reference current becomes: 
     
       
           I   REF =(μ o   C   x   W/L )mk( V   T ) 2 . 
       
     
     It is known that the mobility, μ o , of the transistor varies as (T) −{fraction (3/2)} , where T is temperature. It is also known that V T  varies as (T) 1 . Therefore, the reference current, I PTC , for the positive current reference  304  varies as (T) ½ . 
     Second, a second voltage-threshold independent current reference  300  is used to form a negative temperature coefficient current reference circuit  300 . The gate voltage for the voltage-threshold independent current reference  300  comprises a negative temperature coefficient value. The delta voltage value, ΔV  320 , comprises a negative temperature coefficient value, V BG /n, where V BG  is a bandgap voltage and n is a constant. The drain voltage value, V D    324 , again comprises a positive temperature coefficient value, kV T , where k is a constant. The current reference value output by the circuit  300  comprises a negative temperature coefficient current reference value, I ZTC . 
     Referring again to the current relation, the output of the current reference  300  is given by: 
     
       
           I   REF =(μ o   C   ox   W/L ) (ΔV) V   D . 
       
     
     Since ΔV=(V BG )/n and V D =mV T , the reference current becomes: 
     
       
           E   REF =(μ o   C   ox   W/L ) ( V   BG )/ n ) ( V   T ). 
       
     
     Once again, the mobility, μ o , of the transistor varies as (T) −{fraction (3/2)} , and V T  varies as (T) 1 . However, the bandgap voltage, V BG )/n does not significantly vary with T. Therefore, the reference current, I NTC , for the negative current reference  300  varies as (T) −½ . 
     A means is provided for adding the positive temperature coefficient current reference value, I PTC , and the negative temperature coefficient current reference value, I NTC , to thereby obtain a nearly zero temperature coefficient current reference, I ZTC . The adding means preferably comprises the current mirror circuit comprising the matching devices, N 5   308  and N 6   312 . The gate and drain of N 5   308  are coupled together and further coupled to the gate of N 6   312  at the node C  332 . The sources of N 5   308  and N 6   312  are coupled together such that a common gate-to-source voltage is obtained. The drain of N 5   308  is further coupled to the current reference outputs of the current reference circuits  300  and  304 . The positive temperature coefficient current reference value, I PTC , and the negative temperature coefficient current reference value, I NTC , are added together to create the zero TC reference, I ZTC , as the drain current of N 5 . This current, I ZTC , is mirrored to the output, OUT  336 , by N 6 . 
     Referring now to FIG. 5, the temperature performance of the nearly zero TC current reference of FIG. 4 is illustrated. Note that the combined current, I ZTC , is given by: 
     
       
           I   ZTC   =I   PTC   +I   NTC . 
       
     
     Further, substituting into the reference equation once again, the zero TC current is given by: 
     
       
           I   REF =(μ o   C   ox   W/L ) [ mV   T +( V   BG )/ n )] ( V   T ). 
       
     
     Differentiating this equation with respect to temperature and setting the result to zero results in: 
       V   BG   /n=mV   T , 
     where temperature is T o  at the zero slope point. 
     Referring again to FIG. 5, the response graph  350  shows how the output current source varies over temperature. The derivative zero indicates the point of zero slope at T o . This is the desired operating point for the nearly zero TC circuit of FIG.  4 . Further, this operating point can be selected at any fixed by setting the current and geometry of the MOS devices. 
     Referring now to FIG. 6, an exemplary circuit for deriving the mV T  and kV T  voltages is illustrated. This circuit is well known in the art. The current mirror created by P 1   400  and P 2   404  is matched such that I 1  is the drain current of both P 1  and P 2 . N 1   412  and N 2   416  are operated in weak inversion such that the drain current is exponentially proportional to the drain voltage. Note that N 2  is scaled from N 1  at a ratio given by the constant C. The voltage drop across the first resistor, R 1 , is given by: 
     
       
           V   R1   −ln ( C ) V   T . 
       
     
     Therefore, since P 3   408  is scaled from P 2   404  by the ratio given by the constant A, then the current flowing through the second resistor, R 2 , is given by: 
     
       
           I   2 =( Aln ( C ) V   T )/ R   1 . 
       
     
     Finally, since R 2  is scaled from R 1  by the constant B, then the voltage drop across the second resistor, R 2  is given by: 
     
       
           V   R2   =ABln ( C ) V   T . 
       
     
     Therefore, V R1  and V R2  may be used for kV T  and mkV T . 
     The present invention provides a unique and advantageous current reference circuit. The unique configuration eliminates dependence on the threshold voltage to improve performance. Further, the simplicity of the scheme means that the circuits are stable, effective at low power levels, and space efficient. An effective and very manufacturable current reference circuit is achieved. The current reference circuit comprises all MOS devices. The MOS current reference circuit is not dependent upon the threshold voltage, and this reduces reference current variation due to processing variation. Finally, a nearly zero temperature coefficient current reference is achieved using this novel MOS current reference circuit. 
     As shown in the preferred embodiments, the novel current reference circuit provides an effective and manufacturable alternative to the prior art. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.