Patent Publication Number: US-2023138767-A1

Title: Control circuit of power converter and control method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of China application serial no. 202111264103.5, filed on Oct. 28, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND 
     Technical Field 
     The disclosure relates to a power converter, and in particular to a control circuit of the power converter and a control method thereof. 
     Description of Related Art 
     For the conventional power converter employing digital filter, it is necessary to make filter parameter changes when the output power requirements change. However, when the filter parameters are directly replaced, it leads to significant difference in filter output value. This further results in output control signal level variation and power converter failing to maintain stable output voltage. 
     SUMMARY 
     The disclosure provides a control circuit of a power converter and a control method thereof, which can control the power converter to maintain a stable power signal output. 
     According to an embodiment of the disclosure, a control circuit of a power converter of the disclosure includes an error amplifying circuit, a controller, a digital filter, and a digital pulse width signal modulator. The error amplifying circuit is coupled to an output terminal of the power converter and provides a digital error signal. The controller stores multiple working parameters. When the controller receives a first external control command, the controller provides a first working parameter corresponding to the first external control command. The digital filter is coupled to the controller and the error amplifying circuit, and generates a current digital compensation value according to the first working parameter and the digital error signal. The digital pulse width signal modulator is coupled to the digital filter and generates a pulse width modulation signal according to the current digital compensation value. When the controller receives a second external control command, the controller provides a second working parameter corresponding to the second external control command. The controller calculates a transition value according to the second working parameter and the current digital compensation value, and the controller then provides the second working parameter and the transition value to the digital filter. 
     In an embodiment, when the controller provides the second working parameter and the transition value to the digital filter, the digital filter outputs the current digital compensation value. 
     In an embodiment, the error amplifying circuit includes an error amplifier and an analog-to-digital converter. The error amplifier is coupled to a reference voltage and the output terminal of the power converter, and the analog-to-digital converter is coupled between the error amplifier and the digital filter. 
     In an embodiment, the controller includes a decoder, a memory, and a computing unit. The decoder receives the second external control command and generates an indication signal according to the second external control command. The memory is coupled to the decoder and the digital filter, and stores the working parameters. The memory outputs one of the working parameters as the second working parameter according to the indication signal. The computing unit is coupled to the memory and the digital filter, and calculates the transition value according to the second working parameter and the current digital compensation value. 
     In an embodiment, the digital filter includes a register and a computing circuit. The register is coupled to the controller and stores the transition value. The computing circuit is coupled to the register and the controller, and generates the current digital compensation value according to the second working parameter and the transition value. 
     According to an embodiment of the disclosure, a control method of a power converter of the disclosure includes the following steps. A digital error signal is provided by an error amplifying circuit. When a controller receives a first external control command, a first working parameter corresponding to the first external control command is provided by the controller among the multiple working parameters it stores. A current digital compensation value is generated by a digital filter according to the first working parameter and the digital error signal. A pulse width modulation signal is generated by a digital pulse width signal modulator according to the current digital compensation value. When the controller receives a second external control command, a second working parameter corresponding to the second external control command is provided by the controller. A transition value is calculated by the controller based on the second working parameter and the current digital compensation value. The second working parameter and the transition value are provided by the controller to the digital filter. 
     In an embodiment, when the controller provides the second working parameter and the transition value to the digital filter for computation, the digital filter outputs the current digital compensation value. 
     In an embodiment, the error amplifying circuit includes an error amplifier and an analog-to-digital converter. The error amplifier is coupled to a reference voltage and an output terminal of the power converter, and the analog-to-digital converter is coupled between the error amplifier and the digital filter. 
     In an embodiment, the controller includes a decoder, a memory, and a computing unit. The steps for providing the second working parameter corresponding to the second external control command include the following. The second external control command is received by the decoder, and an indication signal is generated according to the second external control command. One of the working parameters is chosen to be output from the memory as the second working parameter according to the indication signal. The step of calculating the transition value includes the following. The transition value is calculated by the computing unit according to the second working parameter and the current digital compensation value. 
     In an embodiment, the digital filter includes a register and a computing circuit, and the register stores the transition value. The control method further includes the following. The current digital compensation value is being generated by the computing circuit according to the second working parameter and the transition value. 
     Based on the above, the control circuit of the power converter and the control method thereof of the disclosure can automatically generate the matching transition value according to the working parameters corresponding to the external control commands. The digital filter can therefore keep outputting the same digital compensation value, which is based on the transition value, to the digital pulse width signal modulator, and the digital pulse width signal modulator keep outputting the same pulse width modulation signal. 
     In order for the features and advantages of the disclosure to be more comprehensible, the following specific embodiments are described in detail in conjunction with the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic circuit diagram of a control circuit of a power converter according to an embodiment of the disclosure. 
         FIG.  2    is a flowchart of a control method of a power converter according to an embodiment of the disclosure. 
         FIG.  3    is a schematic diagram of an equivalent digital circuit of a digital filter according to an embodiment of the disclosure. 
         FIG.  4    is a schematic diagram of changes in signal and value switching according to an embodiment of the disclosure. 
         FIG.  5    is a schematic diagram of a simulation of signal and value switching according to an embodiment of the disclosure. 
         FIG.  6    is a schematic diagram of a simulation of conventional signal and value switching. 
     
    
    
     DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS 
     Reference will now be made in detail to the exemplary embodiments of the disclosure, examples of which are illustrated in the drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or similar parts. 
       FIG.  1    is a schematic circuit diagram of a control circuit of a power converter according to an embodiment of the disclosure. Referring to  FIG.  1   , a power converter  100  includes a control circuit  110 , a driver  120 , an output circuit  130 , and an output terminal  101 . The output circuit  130  includes transistors  131  and  132 , an inductor  133 , and a capacitor  134 . The control circuit  110  includes a controller  111 , a digital filter  112 , a digital pulse width signal modulator  113 , and an error amplifying circuit  114 . 
     In the embodiment, the error amplifying circuit  114  is coupled to the output terminal  101  of the power converter  100 . The digital filter  112  is coupled to the controller  111 , the digital pulse width signal modulator  113 , and the error amplifying circuit  114 . The digital pulse width signal modulator  113  is coupled to the driver  120 . The driver  120  is coupled to control terminals of the transistor  131  and the transistor  132 . 
     A first terminal of the transistor  131  is coupled to a first voltage V 1 . The first voltage V 1 , for example, has a high voltage level. A second terminal of the transistor  131  is coupled to a first terminal of the transistor  132  and a first terminal of the inductor  133 . The first terminal of the transistor  132  is coupled to a second terminal of the transistor  131  and the first terminal of the inductor  133 . A second terminal of the transistor  132  is coupled to a second voltage V 2 . The second voltage V 2 , for example, has a low voltage level or is grounded. 
     In the embodiment, the transistor  131  may be an NMOS transistor, and the transistor  132  may be a PMOS transistor. A second terminal of the inductor  133  is coupled to the output terminal  101  of the power converter  100 . A first terminal of the capacitor  134  is coupled to the second terminal of the inductor  133  and the output terminal  101 , and a second terminal of the capacitor  134  is coupled to a third voltage V 3 . The third voltage V 3 , for example, has a low voltage level or is grounded. 
     In the embodiment, the controller  111  includes a decoder  1111 , a memory  1112 , and a computing unit  1113 . The digital filter  112  includes a computing circuit  1121  and a register  1122 . The error amplifying circuit  114  includes an error amplifier  1141  and an analog-to-digital converter  1142 . The decoder  1111  is coupled to an external computing processor  200  and the memory  1112 . The computing processor  200  may be a central processing unit (CPU), a graphics processing unit (GPU), or a current level comparator that may be fabricated with or external to control circuit  110 . 
     The decoder  1111  may receive an external control command C 1 /C 2  provided by the computing processor  200 , and generate a corresponding indication signal to the memory  1112  according to the external control command C 1 /C 2 . The memory  1112  is further coupled to the computing unit  1113  and the computing circuit  1121  of the digital filter  112 , and stores multiple working parameters. The computing unit  1113  is further coupled to the register  1122  of the digital filter  112 . In the embodiment, the computing circuit  1121  is further coupled to the register  1122  and the digital pulse width signal modulator  113 . 
     In the embodiment, a first input terminal of the error amplifier  1141  is coupled to the output terminal  101  of the power converter  100 , and a second input terminal of the error amplifier  1141  is coupled to a reference voltage Vf. An output terminal of the error amplifier  1141  is coupled to the analog-to-digital converter  1142 . The analog-to-digital converter  1142  is further coupled to the computing circuit  1121 . 
     In the embodiment, the error amplifier  1141  may generate an analog error signal Vr according to an output voltage Vout and the reference voltage Vf, so that the output terminal of the error amplifier  1141  may provide the analog error signal Vr to the analog-to-digital converter  1142 . The analog-to-digital converter  1142  may convert the analog error signal to output a digital error signal X[n] to the computing circuit  1121 . 
     When the computing processor  200  outputs the first external control command C 1  to the decoder  1111 , the decoder  1111  generates a first indication signal D 1  to the memory  1112  according to the first external control command C 1 . The memory  1112  outputs a first working parameter Pa to the computing unit  1113  and the computing circuit  1121  according to the first indication signal D 1 . The computing circuit  1121  outputs a current digital compensation value Y[n] to the digital pulse width signal modulator  113  and the register  1122  according to the first working parameter Pa and the digital error signal X[n]. The digital pulse width signal modulator  113  outputs a pulse width modulation signal PS to the driver  120  according to the current digital compensation value Y[n]. For this, the driver  120  may control the output circuit  130  according to the pulse width modulation signal PS to generate the output voltage Vout to the output terminal  101  of the power converter  100 . 
     Next, when the power requirement of a load device coupled to the output terminal  101  of the power converter  100  changes, the load state changes, or a power signal output by the power converter  100  changes, the computing processor  200  may respond by outputting the second external control command C 2  to the decoder  1111 . The decoder  1111  then generates a second indication signal D 2  to the memory  1112  according to the second external control command C 2 . 
     The memory  1112  outputs a second working parameter Pb to the computing unit  1113  and the computing circuit  1121  according to the second indication signal D 2 . The computing unit  1113  calculates a transition value Pc according to the second working parameter Pb and the current digital compensation value Y[n] provided by the register  1122 , and provides the transition value Pc to the register  1122  for storage. For this, the computing circuit  1121  may keep generating identical digital compensation value Y[n] according to the digital error signal X[n], the second working parameter Pb, and the transition value Pc. 
     Therefore, the control circuit  110  of the power converter  100  can effectively maintain the output voltage Vout of the power converter  100  when the working parameter of the digital  185  filter  112  changes, resulting in a stable power output. 
       FIG.  2    is a flowchart of a control method of a power converter according to an embodiment of the disclosure. Referring to  FIG.  1    and  FIG.  2   , the control circuit  110  may execute Steps S 210  to S 270  to implement a control function thereof. 
     In Step S 210 , the error amplifying circuit  114  provides the digital error signal X[n]. In Step S 220 , when the controller  111  receives the first external control command Cl, the controller  111  provides the first working parameter Pa corresponding to the first external control command C 1 . In Step S 230 , the digital filter  112  generates the current digital compensation value Y[n] according to the first working parameter and the digital error signal X[n]. In Step S 240 , the digital pulse width signal modulator  113  generates the pulse width modulation signal PS according to the current digital compensation value Y[n]. In Step S 250 , when the controller  111  receives the second external control command C 2 , the controller  111  provides the second working parameter Pb corresponding to the second external control command C 2 . In Step S 260 , the controller  111  calculates the transition value Pc according to the second working parameter Pb and the current digital compensation value. In Step S 270 , the controller  111  provides the second working parameter Pb and the transition value Pc to the digital filter  112 . 
     For this, the digital filter  112  may keep generating the current digital compensation value Y[n] according to the second working parameter and the transition value Pc. That is, when the controller  111  provides the second working parameter and the transition value Pc to the digital filter  112  for computation, the digital filter  112  still outputs the identical digital compensation value Y[n]. 
     Therefore, when the power requirement of the load device coupled to the output terminal  101  of the power converter  100  changes, the load state changes, or the power signal output by the power converter  100  changes (for example, the number of output phases changes such that an equivalent output inductance value changes), it is necessary to switch the working parameters in the digital filter  112  to respond to the changes. When the changes occur, the controller  111  changes from receiving the first external control command C 1  to receiving the second external control command C 2 , so that the control circuit  110  of the power converter  100  can maintain the output voltage Vout of the power converter  100  steadily. 
       FIG.  3    is a schematic diagram of an equivalent digital circuit of a digital filter according to an embodiment of the disclosure. Referring to  FIG.  1    and  FIG.  3   , the digital filter  112  may be a multi-order filter with a cascade architecture, and the computing circuit  1121  may be implemented in a Type I series cascade architecture, which is shown as digital circuit  300  in  FIG.  3   . The digital circuit  300  of the computing circuit  1121  may include three sub-computing blocks  300 A,  300 B, and  300 C, but the disclosure is not limited thereto. 
     In an embodiment, the computing circuit  1121  may further be embodied in other equivalent circuit forms. In the embodiment, the sub-computing block  300 A may include an input node  300 _input, register nodes N 1 , N 2 , N 3 , tx 1 , tx 2 , and ty 1 , and operands  301  to  310 . The sub-computing block  300 B may include register nodes N 4 , N 5 , ty 2 , and tx 3 , and operands  311  to  315 . The sub-computing block  300 C may include an output node  300  output, a register node ty 3 , and operands  316  to  318 . 
     It should be noted first that the register nodes N 1  to N 5 , tx 1  to tx 3 , and ty 1  to ty 3  may indicate that computing values thereof are respectively stored by corresponding register units, and the operands  301  to  318  may indicate that computing functions thereof are respectively implemented by a corresponding unit time delay, multiplier, adder, or subtractor. 
     As shown in  FIG.  3   , in the sub-computing block  300 A (the first stage), the operand  301  is coupled to the input node  300 _input to receive an input value Din of the digital error signal X[n], and the operand  301  is a multiplier (with a multiplier value of K 1 ). The operand  302  is coupled between an output of the operand  301  and the register node tx 1  (storing a transition value CX 1 ), and the operand  302  is a unit time delay. The operand  303  is coupled between the register node tx 1  and an input of the operand  304 , the operand  303  is a multiplier (with a multiplier value of K 2 ), and the operand  304  is an adder. 
     The operand  304  is coupled to the output of the operand  301  and an output of the operand  303 , and outputs a computing result to the register node N 1  (storing a node value Al). The operand  305  is coupled to the register node N 1 , and the operand  305  is a subtractor. The operand  305  is coupled to the register node N 1  and an output of the operand  306 , and outputs a computing result to the register node N 2  (storing a node value A 2 ). The operand  306  is coupled between the operand  305  and the register node ty 1  (storing a transition value CY 1 ), and the operand  306  is a multiplier (with a multiplier value of K 3 ). The operand  307  is coupled between the register node ty 1  and an output of the operand  305 , and the operand  307  is a unit time delay. 
     The register node N 2  is coupled to the output of the operand  305 . The operand  308  is coupled between the register node N 2  and the register node tx 2  (storing a transition value CX 2 ), and the operand  308  is a unit time delay. The operand  309  is coupled between the register node tx 2  and the operand  310 , the operand  309  is a multiplier (with a multiplier value of K 4 ), and the operand  310  is an adder. The operand  310  is coupled to the register node N 2  and an output of the  250  operand  309 , and outputs a computing result to the register node N 3  (storing a node value A 3 ). 
     Therefore, based on the above equivalent digital circuit architecture, in the case where the system is in a stable state (the influence of the unit time delay may be ignored), algorithms of Equation (1) to Equation (6) below may be implemented. 
         A 1= CX 1* K 2+ Din*K 1   Equation (1)
 
         A 2= A 1− CY 1* K 3   Equation (2)
 
         A 3= A 2+ CX 2* K 4   Equation (3)
 
         A 1= CX 1* K 2+ Din*K 1   Equation (4)
 
       CX2=A2   Equation (5)
 
       CY1=A2   Equation (6)
 
     In the sub-computing block  300 B (the second stage), the operand  311  is coupled to the register node N 3 , and the operand  311  is a subtractor. The operand  311  is coupled to the register node N 3  and an output of the operand  312 , and outputs a computing result to the register node N 4  (storing a node value A 4 ). The operand  312  is coupled between the operand  311  and the register node ty 2  (storing a transition value CY 2 ), and the operand  312  is a multiplier (with a multiplier  265  value of K 5 ). 
     The operand  313  is coupled between the register node ty 2  and an output of the operand  311 , and the operand  313  is a unit time delay. The register node N 4  is coupled to the output of the operand  311 . The operand  314  is coupled between the register node N 4  and the register node tx 3  (storing a transition value CX 3 ), and the operand  314  is a unit time delay. The operand  315  is coupled to the register node N 4  and the register node tx 3 , and outputs a computing result to the register node N 5  (storing a node value A 5 ), and the operand  315  is an adder. 
     Therefore, based on the above equivalent digital circuit architecture, in the case where the system is in the stable state (the influence of the unit time delay may be ignored), algorithms of Equation (7) to Equation (10) below may be implemented. 
         A 4= A 3− CY 2* K 5   Equation (7)
 
         A 5= A 4− CX 3   Equation (8)
 
       CX3=A4   Equation (9)
 
       CY2=A4   Equation (10)
 
     In the sub-computing block  300 C (the third stage), the operand  316  is coupled to the register node N 5 , and the operand  316  is a subtractor. The operand  316  is coupled to the register node N 5  and the output node  300 _output to output a value Dout as the current digital compensation value Y[n]. The operand  317  is coupled between the operand  316  and the register node ty 3  (storing a transition value CY 3 ), and the operand  317  is a multiplier (with a multiplier value of K 6 ). The operand  318  is coupled between the register node ty 3  and the output of the operand  316 , and the operand  318  is a unit time delay. 
     Therefore, based on the above equivalent digital circuit architecture, in the case where the system is in the stable state (the influence of the unit time delay may be ignored), algorithms of Equation (11) and Equation (12) may be implemented. 
         Dout=A 5− CY 3* K 6   Equation (11)
 
       CY3=Dout   Equation (12)
 
     When the controller  111  is switching coefficients (for example, switching the multiplier values K 3  to K 6  to new multiplier values K 3 ′ to K 6 ′) in response to changes in the control command, it is necessary for the controller to make following calculation to maintain the same output value Dout as the current digital compensation value Y[n]. For the sub-computing block  300 C, the controller  111  may execute algorithms of Equation (13) and Equation (14) below to obtain the new transition value CY 3 ′ and a new node value A 5 ′. 
         CY 3′=Dout   Equation (13)
 
         A 5′= Dout+CY 3′* K 6′  Equation (14)
 
     For the sub-computing block  300 B, the controller  111  may execute algorithms of Equation (15) to Equation (18) below to obtain the new transition values CX 3 ′ and CY 2 ′ and new node values A 4 ′ and A 3 ′. 
         A 4′= A 5′/2   Equation (15)
 
         CX 3′= A 4′=( Dout+CY 3′* K 6′)/2= Dout *(1+ k 6′)/2   Equation (16)
 
       CY 2 ′=A 4 ′  Equation (17)
 
         A 3′= A 4′+ CY 2′* K 5′  Equation (18)
 
     For the sub-computing block  300 A, the controller  111  may execute algorithms of Equation (19) to Equation (22) to obtain the new transition values CX 2 ′ and CY 1 ′ and new node values A 2 ′ and A 1 ′. 
         A 2′= A 3′/(1+ K 4′)   Equation (19)
 
         CX 2′= A 2′= Dout *(1+ K 6′)*(1+ K 5′)/(2*(1+ K 4′))   Equation (20)
 
       CY 1 ′=A 2 ′  Equation (21)
 
         A 1′0= A 2′+ CY 1′* K 3′  Equation (22)
 
     In other words, when the decoder  1111  of the controller  111  receives the second external control command C 2 , the decoder  1111  may output the corresponding second indication signal D 2  to the memory  1112 . The memory  1112  may output the second working parameter Pb to the computing unit  1113  according to the second indication signal D 2 , and the second working parameter Pb includes the new multiplier values K 3 ′ to K 6 ′. The computing unit  1113  may then execute Equation (13) to Equation ( 22 ) above with the current digital compensation value Y[n] to generate a new transition value Pc to the digital filter  112 . The new transition value Pc includes the new transition values CX 2 ′, CX 3 ′, CY 1 ′, CY 2 ′, and CY 3 ′. In this way, the computing circuit  1121  may keep generating the same digital compensation value Y[n]. 
       FIG.  4    is a schematic diagram of changes in signal and value switching according to an embodiment of the disclosure. Referring to  FIG.  1    and  FIG.  4   , for example, it is assumed that the power converter  100  may output a power signal with a three-phase configuration. In this regard, between times t 0  and t 15 , the controller  111  receives the first external control command C 1 , and the memory  1112  continuously outputs the first working parameter Pa to the digital filter  112 . 
     The computing circuit  1121  of the digital filter  112  may respectively perform computations during periods TA 1  to TA 8  of times t 0  to t 1 , t 2  to t 3 , t 4  to t 5 , t 6  to t 7 , t 8  to t 9 , t 10  to t 11 , t 12  to t 13 , and t 14  to t 16  to continuously output the digital compensation value Y[n], and the analog-to-digital converter  1142  may continuously generate the digital error signal X[n]. Therefore, the digital pulse width signal modulator  113  of the control circuit  110  may output a pulse width modulation signal PWM 1  as shown in  FIG.  4   , and two other digital pulse width signal modulator  113  of the control circuit  110  may further output pulse width modulation signals PWM 2   335  and PWM 3  as shown in  FIG.  4   . 
     It is assumed that the power converter  100  intends to switch to outputting a power signal with a single-phase configuration at a time t 17 . That is, the pulse width modulation signals PWM 2  and PWM 3  output by the two digital pulse width signal modulator  113  of the control circuit  110  stop changing, and the digital pulse width signal modulator  113  of the control circuit  110  keeps outputting the same switching pulse width modulation signal PWM 1 . In this regard, at a time t 15 , the controller  111  receives the second external control command C 2 , and the memory  1112  switches to outputting the second working parameter Pb to the digital filter  112 . The computing unit  1113  may perform computations during the times t 15  to t 17  to generate the transition value Pc to the digital filter  112 . 
     In this way, the computing circuit  1121  of the digital filter  112  may perform computations during a period TC 1  of times t 17  to t 18  to keep outputting the digital compensation value Y[n], and the analog-to-digital converter  1142  may continuously generate the digital error signal X[n]. In addition, the computing circuit  1121  of the digital filter  112  may perform computations during periods TC 2  and TC 3  of times t 19  to t 20  and t 21  to t 22  to keep outputting the digital compensation value Y[n]. 
     Referring to  FIG.  5    and  FIG.  6    together,  FIG.  5    is a schematic diagram of a simulation of signal and value switching according to an embodiment of the disclosure.  FIG.  6    is a schematic diagram of a simulation of conventional signal and value switching. Referring to  FIG.  5    first, assuming that the controller  111  switches from receiving the first external control command C 1  to receiving the second external control command C 2  at a time of 0.007 seconds, a command flag FP of the controller  111  is switched, for example, from a value of 0 to a value of 0.8. 
     In this regard, the computing unit  1113  can quickly perform computations to generate the transition value Pc to the digital filter  112 , so that the computing circuit  1121  may keep outputting the digital compensation value Y[n] according to the transition value Pc before and after the time of 0.007 seconds. Therefore, the power converter  100  may stably generate the output voltage Vout before and after the time of 0.007 seconds, and the analog error signal Vr generated by the error amplifier  1141  may be stably maintained at a fixed voltage level. 
     In contrast, referring to  FIG.  6   , assuming that a controller of a conventional power converter also switches from receiving the first external control command C 1  to receiving the second external control command C 2  at the time of 0.007 seconds, the command flag FP of the controller of the conventional power converter is also switched, for example, from the value of 0 to the value of 0.8. Without a compensation control mechanism for generating the transition value Pc by the computing unit  1113  of the disclosure, a digital compensation value Y[n]&#39; received by a digital pulse width signal modulator of the conventional power converter will have level variation after the time of 0.007 seconds and will gradually return to stability after a period of time. 
     In this way, a voltage level of the output voltage Vout&#39; of the conventional power converter will drop sharply corresponding to changes in the digital compensation value Y[n]′ and will gradually return to stability after a period of time, so that a power signal output by the power converter has the issue of signal level variation. In addition, the analog error signal Vr generated by the error amplifier  1141  is also affected to generate a level variation of 0.2 volts, thereby affecting the stability of the control circuit of the power converter. In other words, the control circuit  110  of the power converter  100  of the disclosure can effectively control the power converter  100  to output the power signal stably. 
     In summary, the control circuit of the power converter and the control method thereof of the disclosure can automatically generate the corresponding transition value according to changes in the external control command, which is provided by the external computing processor. In the case where a power requirement of the system changes, the digital filter can automatically correct a calculation result with the transition value, so the power converter of the disclosure can maintain the stable digital compensation value and output voltage, which can effectively avoid or reduce the case of signal level variation. 
     Finally, it should be noted that the above embodiments are only used to illustrate, but not to limit, the technical solutions of the disclosure. Although the disclosure has been described in detail with reference to the above embodiments, persons skilled in the art should understand that the technical solutions described in the above embodiments may still be modified or some or all of the technical features thereof may be equivalently replaced. However, the modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the disclosure.