Patent Publication Number: US-2004042272-A1

Title: Novolatile semiconductor memory having multilayer gate structure

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-254126, filed Aug. 30, 2002, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002] 1. Field of the Invention  
       [0003] The present invention relates to a nonvolatile semiconductor memory. More specifically, the invention relates to the structure of a memory cell array and a method of writing and reading data.  
       [0004] 2. Description of the Related Art  
       [0005] EEPROMs (electrically erasable and programmable read only memories) are known as nonvolatile semiconductor memories that can write and erase data electrically. Of the EEPROMs, there is a flash memory that can electrically erase a set of data at once.  
       [0006] The structure of a prior art NOR EEPROM will now be described with reference to FIG. 1A. FIG. 1A is a circuit diagram of a memory cell array of the prior art NOR EEPROM.  
       [0007] Referring to FIG. 1A, the memory cell array includes a plurality of memory cells MC arranged in matrix. The control gates of the memory cells MC in the same row are connected to their common one of control gate lines CG 1  to CGn (n is a natural number and only CG 1  to CG 3  are shown in FIG. 1A). Adjacent memory cells in the same column have source and drain regions in common. The drains of the memory cells MC in the same column are connected to their common one of drain lines DL 1  to DLm (m is a natural number and only DL 1  to DL 5  are shown in FIG. 1A). The sources of the memory cells MC in the same row are connected to their common one of source lines SL 1  to SLk (k is a natural number and only SL 1  is shown in FIG. 1).  
       [0008]FIG. 1B is a plan pattern view of the memory cell array shown in FIG. 1A. As shown in FIG. 1B, the memory cells MC are formed in each of strip-shaped element regions AA electrically isolated by strip-shaped element isolation regions STI. The control gate lines CG 1  to CGn extend in a direction perpendicular to the longitudinal direction of the element isolation regions STI. Each of the element regions AA includes a source contact plug SP and a drain contact plug DP that are connected to their respective source and drain of each of the memory cells MC. Drain lines DL 1  to DLm (not shown), each of which connects the drain contact plugs DP in each column, extend in the same direction as the longitudinal direction of the element isolation regions STI. The source lines SL 1  to SLk (only SL 1  is shown in FIG. 1B), each of which connect the source contact plugs SP in each row, extend in a direction parallel to the control gate lines CG 1  to CGn.  
       [0009] The following operations of the prior art NOR EEPROM will now be described.  
       [0010] [Erase Operation] 
       [0011] In erase mode, a positive potential Ve of about 10 V is applied to all drain and source lines and a well (semiconductor substrate). A negative potential Vge of about −8 V is applied to all control gate lines. Consequently, electrons are extracted from a floating gate toward a channel. In other words, electrons decrease in the floating gate and positive charges increase seemingly; therefore, the threshold voltage of the memory cells lowers and data is erased from the memory cells.  
       [0012] [Write Operation] 
       [0013] In write mode, the source lines and well are set at a ground potential GND. A potential Vgp of about 8 V and a potential Vdp of about 5 V are applied to their respective control gate line and drain line connected to a selected memory cell. The control gate line and drain line connected to a non-selected memory cell are set at the ground potential GND. Thus, current flows through only the channel of the selected memory cell. Hot electrons generated by the flow of current are injected into the floating gate of the selected memory cell. In other words, electrons increase in the floating gate; therefore, the threshold voltage of the memory cells heightens and data is written to the memory cells.  
       [0014] [Read Operation] 
       [0015] In read mode, the source lines and well are set at the ground potential GND. A potential Vgr of about 5 V and a potential Vdr of about 1 V are applied to their respective control gate line and drain line connected to a selected memory cell. The control gate line and drain line connected to a non-selected memory cell are set at the ground potential GND. In a memory cell in an erase state, current flows into the source from the drain because the threshold voltage of the memory cell is lower than the gate voltage Vgr. In a memory cell in a write state, no current flows because the threshold voltage is higher than the gate voltage Vgr. In other words, data in the memory cells is discriminated depending upon the presence and absence of current.  
       [0016] In the prior art nonvolatile semiconductor memory described above, adjacent memory cells in the same column have a source contact plug and a drain contact plug in common. In other words, one contact plug is formed for each of the memory cells. The area of the occupied memory cells is therefore decreased. Further, the rate of decrease in the area of the memory cell array depends upon not the size of memory cells but the design rule of contact plugs.  
       [0017] However, the prior art nonvolatile semiconductor memory has a large number of contact plugs that restrict the rate of decrease in the area of the memory cell array. The memory cell array is therefore becoming difficult to decrease in size. Furthermore, the contact resistance of the contact plugs is high and the electrical characteristics of the nonvolatile semiconductor memory are likely to deteriorate.  
       BRIEF SUMMARY OF THE INVENTION  
       [0018] A semiconductor memory device according to an aspect of the present invention comprises:  
       [0019] memory cells arranged in matrix, adjacent memory cells in a column direction having one of a source and a drain in common;  
       [0020] source lines to each of which sources of memory cells of adjacent two columns are connected;  
       [0021] drain lines to each of which drains of memory cells of adjacent two columns are connected, drains of memory cells of two columns connected to the source line being connected to different drain lines, respectively; and  
       [0022] control gate lines to each of which gates of adjacent memory cells in a row direction are connected. 
     
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
     [0023]FIG. 1A is a circuit diagram of a prior art NOR EEPROM;  
     [0024]FIG. 1B is a plan view of the prior art NOR EEPROM;  
     [0025]FIG. 2A is a circuit diagram of a NOR EEPROM according to a first embodiment of the present invention;  
     [0026]FIG. 2B is a plan view of the NOR EEPROM according to the first embodiment of the present invention;  
     [0027]FIG. 2C is a circuit diagram of the NOR EEPROM according to the first embodiment of the present invention;  
     [0028]FIG. 2D is a cross-sectional view taken along line  2 D- 2 D of FIG. 2B;  
     [0029]FIG. 2E is a cross-sectional view taken along line  2 E- 2 E of FIG. 2B;  
     [0030]FIG. 2F is a cross-sectional view taken along line  2 F- 2 F of FIG. 2B;  
     [0031]FIG. 3A is a table showing voltages applied in write mode of the NOR EEPROM according to the first embodiment of the present invention;  
     [0032]FIG. 3B is a table showing voltages applied in read mode of the NOR EEPROM according to the first embodiment of the present invention;  
     [0033]FIG. 4 is a circuit diagram of a NOR EEPROM according to a second embodiment of the present invention;  
     [0034]FIG. 5 is a table showing voltages applied in write mode of the NOR EEPROM according to the second embodiment of the present invention;  
     [0035]FIG. 6A and FIG. 6B are circuit diagrams of part of a memory cell array of the NOR EEPROM according to the second embodiment of the present invention, which is shown to describe a write operation of the EEPROM;  
     [0036]FIG. 7 is a table showing voltages applied in read mode of the NOR EEPROM according to the second embodiment of the present invention;  
     [0037]FIG. 8A and FIG. 8B are circuit diagrams of part of a memory cell array of the NOR EEPROM according to the second embodiment of the present invention, which is shown to describe a read operation of the EEPROM;  
     [0038]FIG. 9A is a plan view of a NOR EEPROM according to a first modification to the first and second embodiments of the present invention;  
     [0039]FIG. 9B is a cross-sectional view taken along line  9 B- 9 B of FIG. 9A;  
     [0040]FIG. 10A is a plan view of a NOR EEPROM according to a second modification to the first and second embodiments of the present invention;  
     [0041]FIG. 10B is a cross-sectional view taken along line  10 B- 10 B of FIG. 10A; and  
     [0042]FIG. 11 is a plan view of a NOR EEPROM according to a third modification to the first and second embodiments of the present invention.  
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0043] A nonvolatile semiconductor memory according to a first embodiment of the present invention will now be described with reference to FIG. 2A, taking an EEPROM as an example. FIG. 2A is a circuit diagram of a NOR EEPROM according to the first embodiment.  
     [0044] As shown in FIG. 2A, the NOR EEPROM comprises a memory cell array  10 , a row decoder  20 , column decoders  30   a  and  30   b , column selectors  40   a  and  40   b , a sense amplifier  50 , and a voltage generation circuit  60 .  
     [0045] The memory cell array  10  includes a plurality of memory cells MC arranged in matrix. The memory cells MC are each configured by a MOS transistor including a multilayer gate having, e.g., a control gate and a floating gate. The control gates of memory cells MC arranged in the same row are connected to a common control gate line CGj (j=1 to n, j and n are each natural number). Adjacent memory cells MC in the same column have one of source and drain regions in common. The drains of memory cells MC of adjacent two columns are connected to a common drain line DLi (i=1 to m, i and m are each natural number). The sources of memory cells MC of adjacent two columns are connected to a common source line SLi. However, the memory cells MC of adjacent two columns have only one of source and drain lines in common.  
     [0046] The row decoder  20  decodes an externally input row address signal. In response to the row address signal, the row decoder applies a given voltage to the control gate lines CG 1  to CGn.  
     [0047] The column decoders  30   a  and  30   b  decode an externally input column address signal. In response to the column address signal, the column decoders  30   a  and  30   b  control column selectors  40   a  and  40   b , respectively.  
     [0048] The column selector  40   a  selects one from among the drain lines DL 1  to DLm in response to the decoded column address signal. The column selector  40   b  selects one from among the source lines SL 1  to SLm in response to the decoded column address signal.  
     [0049] In write mode, the sense amplifier  50  latches write data. In read mode, the sense amplifier  50  latches data read out of a memory cell MC.  
     [0050] The voltage generation circuit generates a voltage and applies it to any one of the source lines SL 1  to SLm selected by the column selector  40   b.    
     [0051] The configuration of the memory cell array described above will now be described in detail. FIG. 2B is a plan pattern view of part of the memory cell array shown in FIG. 2A. In this pattern view, first and second directions are defined as indicated by arrows in FIG. 2B.  
     [0052] Referring to FIG. 2B, a plurality of element isolation regions STI in strip-shape along the first direction is formed in a semiconductor substrate at regular intervals along the second direction perpendicular to the first direction. An element region AA is formed between adjacent element isolation regions STI and memory cells are formed in the element region AA. A plurality of control lines CG 1  to CGn in strip-shape along the second direction is formed at regular intervals along the first direction. A source region and a drain region are formed in the element region AA so as to sandwich a control gate line, thus forming a memory cell MC. As described above, adjacent memory cells in the same column have one of the source and drain regions in common. The element isolation regions STI are each partly removed. In other words, each of the element isolation regions STI is separated into regions in the first direction with a space between adjacent regions. The regions are each located directly under two control gate lines and between the two control gates. The space is located between the control gates on one and another region respectively. The space is an element region AA′. An impurity diffusion layer is formed in the element region AA′. Sources or drains of the memory cells MC of adjacent two columns in the second direction are connected to each other by the element region AA′. Consequently, the element regions AA′ are used as source and drain regions alternately in the second direction. In other words, the element regions AA′ are arranged in a staggered format, as are the element isolation regions STI.  
     [0053] The configuration of the memory cell array can be rephrased as follows. The element isolation regions STI whose longitudinal direction is equal to the first direction are arranged in a staggered format. The control gate lines CG 1  to CGn are formed in the second direction. Two control gate lines pass across each of the element isolation regions STI. The control gate line CGj alternately passes across the same element isolation regions STI as those across which the control gate lines CGj+1 and CGj−1 pass. The element region AA′ is interposed between adjacent element isolation regions STI in the first direction. This element region AA′ is also interposed between adjacent control gate lines.  
     [0054] Either a source contact plug SP or a drain contact plug DP is formed in the element region AA′. The source contact plugs SP in the same column are connected to their common one of the source lines SL 1  to SLm. The drain contact plugs DP in the same column are connected to their common one of the drain lines DL 1  to DLm. The source lines SL 1  to SLm and drain lines DL 1  to DLm are formed in the first direction and shaped like a strip. These source and drain lines overlap the element isolation regions STI. The source contact plugs SP and drain contact plugs DP are arranged alternately in the second direction as described above, as are the source lines SL 1  to SLm and drain lines DL 1  to DLm.  
     [0055] The configuration of the above memory cell array can be described with reference to FIG. 2C. FIG. 2C is a circuit diagram of the memory cell array of the NOR EEPROM shown in FIGS. 2A and 2B.  
     [0056] Referring to FIG. 2C, the memory cell array includes a plurality of first memory cell units UNIT 1  arranged in matrix. Each of the first memory cell units UNIT 1  includes four memory cells MC arranged in matrix. Ends (sources) of current paths of the four memory cells are connected to one another. The closest four memory cells MC of adjacent four first memory cell units UNIT 1  compose a second memory cell unit UNIT 2 . The memory cells MC belong to one of the second memory cell units UNIT 2  as well as one of the first memory cell units UNIT 1 . The four memory cells MC of each of the first memory cell units UNIT 1  belong to their respective second memory cell units UNIT 2 . Needless to say, the four memory cells MC of each of the second memory cell units UNIT 2  belong to their respective first memory cell units UNIT 1 . The other ends (drains) of the current paths of the four memory cells MC of the second memory cell unit UNIT 2  are connected to one another. The ends (sources) of the current paths of the first memory cell units UNIT 1  in the same column are connected to a common first wire (source line). The other ends (drains) of the current paths of the second memory cell units UNIT 2  in the same column are connected to a common second wire (drain line). Furthermore, the gates of the memory cells in the same row are connected to a common control gate line.  
     [0057] A first element isolation region STI 1  is formed between adjacent first memory cell units UNIT 1  in the row direction to electrically isolate these units UNIT 1  from each other. A second element isolation region STI 2  is formed between adjacent second memory cell units UNIT 2  in the row direction to electrically isolate these units UNIT 2  from each other. A region AA 1  is formed between adjacent second element isolation regions STI 2  in the column direction, and a contact plug (source contact plug SP) that connects a common end of the current paths in the first memory cell unit UNIT 1  to the first wire is formed in the region AA 1 . On the other hand, a region AA 2  is formed between adjacent first element isolation regions STI 1  in the column direction, and a contact plug (drain contact plug DP) that connects the other common end of the current paths in the second memory cell unit UNIT 2  to the second wire is formed in the region AA 2 . These regions AA 1  and AA 2  correspond to the region AA′ shown in FIG. 2B.  
     [0058] The section of the memory cell array will now be described with reference to FIGS. 2D to  2 F. FIGS. 2D to  2 F are cross-sectional views taken along lines  2 D- 2 D,  2 E- 2 E and  2 F- 2 F of FIG. 2B, respectively.  
     [0059] First, the configuration of the memory cell array will be described with reference to FIG. 2D showing the cross-sectional view taken along line  2 D- 2 D in the element region AA. As shown in FIG. 2D, a plurality of impurity diffusion layers  13   a  and  13   b  is formed in a surface area of a semiconductor substrate (silicon substrate)  11 . The impurity diffusion layer  13   a  serves as a drain region and the impurity diffusion layer  13   b  serves as a source region. A floating gate electrode  14  is formed on the semiconductor substrate  11  with a gate insulation film interposed therebetween. The gate insulation film  12  is made of, for example, silicon oxide and oxynitride. The floating gate electrode  14  is made of, for example, polysilicon. A control gate electrode  16  is formed on the floating gate electrode  14  with a gate-to-gate insulation film  15  interposed therebetween such that the electrode  16  covers the electrode  14 . The gate-to-gate insulation film  15  is formed of a three-layer ONO film of silicon oxide, silicon nitride and silicon oxide, a single-layer film of silicon oxide, a two-layer ON film of silicon oxide and silicon nitride, a two-layer NO film or the like. A multilayer gate containing the floating gate electrode  14  and control gate electrode  16  and the source and drain regions  13   b  and  13   a  make up a memory cell (flash cell) MC. Furthermore, an interlayer insulation film  17  is formed on the semiconductor substrate  11  so as to coat the memory cell MC.  
     [0060] Then, the configuration of the memory cell array will be described with reference to FIG. 2E showing the cross-sectional view taken along line  2 E- 2 E. As shown in FIG. 2E, the semiconductor substrate includes a plurality of element isolation regions STI. Not the floating gates  14  but the control gate electrodes  16  are formed on each of the element isolation regions STI. Each of the element isolation regions STI is formed across a region directly under two control gate electrodes  16 . The element isolation regions STI are arranged so as to sandwich a region (element region AA′) formed between adjacent two control gate electrodes  16 . The drain region  13   a  is formed in the element region AA′ and connected to the drain region  13   a  in the element region AA. The interlayer insulation film  17  is formed on the semiconductor substrate  11  so as to coat the control gate electrode  16 . Moreover, drain contact plugs  18   a  are formed in the interlayer insulation film  17  so as to be connected to their corresponding drain regions  13   a . A metal wiring layer  19   a  is formed on the interlayer insulation film  17  to connect the drain contact plugs  18   a  in common. The metal wiring layer  19   a  functions as a drain line DLi.  
     [0061] Then, the configuration of the memory cell array will be described with reference to FIG. 2F showing the cross-sectional view taken along line  2 F- 2 F. As is apparent from FIG. 2F, the configuration is basically the same as that of the memory cell array shown in FIG. 2E. The positions of element regions AA′ are each shifted by half cycle from those of element regions AA′ in the configuration shown in FIG. 2E. More specifically, the element region AA′ is formed adjacent to a region in which the source region  13   b  is to be formed in the configuration shown in FIG. 2D. The source region  13   b  is formed in the element region AA′ and connected to the source region  13   b  in the element region AA. Source contact plugs  18   b  are formed in the interlayer insulation film  17  so as to be connected to their corresponding source regions  13   b . A metal wiring layer  19   b  is formed on the interlayer insulation film  17  to connect the source contact plugs  18   b  in common. The metal wiring layer  19   b  functions as a source line SLi.  
     [0062] An operation of the NOR EEPROM according to the first embodiment will now be described with reference to FIGS. 2A, 3A and  3 B. FIG. 3A is a table showing voltages applied in write mode of the NOR EEPROM and FIG. 3B is a table showing voltages applied in read mode thereof. In FIGS. 3A and 3B, cell A 1  corresponds to a memory cell MC whose gate is connected to the control gate line CGj, drain is connected to the drain line DLi, and source is connected to the source line SLi, as shown in FIG. 2A. Cell A 2  corresponds to a memory cell MC whose gate is connected to the control gate line CGj, drain is connected to the drain line DLi, and source is connected to the source line SLi−1. Cell B 1  corresponds to a memory cell MC whose gate is connected to the control gate line CGj+1, drain is connected to the drain line DLi, and source is connected to the source line SLi. Cell B 2  corresponds to a memory cell MC whose gate is connected to the control gate line CGj+1, drain is connected to the drain line DLi, and source is connected to the source line SLi−1.  
     [0063] [Write Operation] 
     [0064] The write operation of the NOR EEPROM will be described with reference to FIGS. 2A and 3A, taking an operation of writing data to cell A 1  as an example.  
     [0065] First, the semiconductor substrate (well region)  11  is set at a ground potential GND. The voltage generation circuit  60  applies a potential Vdp to the source lines SL 1  to SLi−1 and sets the source lines SLi to SLm at the ground potential GND. The drain lines DL 1  to DLi are set at the potential Vdp through the sense amplifier  50  and drain lines DLi+1 to DLm are set at the ground potential GND. The potential Vdp is, for example, about 5 V. The row decoder  20  applies a potential Vgp to the control gate line CGj and sets the other control gate lines CG 1  to CGj−1 and CGj+1 to CGn at the ground potential GND. The potential Vgp is, for example, about 8 V. In the cell A 1 , therefore, the potential Vgp is applied to the control gate and the potential difference Vdp is applied between the source and drain. Consequently, current flows through a channel region between the source and drain to generate hot electrons. The hot electrons are injected into the floating gate of the cell A 1 . Thus, the number of electrons in the floating gate of the cell A 1  increase and so does the threshold voltage of the cell A 1 . In other words, data is written to the cell A 1 .  
     [0066] The status of the cell A 2  appearing when data is written to the cell A 1  will now be described. Since the control gate of the cell A 2  is connected to the same control gate line CGj as that of the cell A 1 , its potential is Vgp. However, the potentials of the source line SLi−1 and drain line DLi connected to the source and drain of the cell A 2  are both Vdp. In other words, there is no difference in potential between the source and drain of the cell A 2 . No current flows between the source and drain or no hot electrons are generated. Consequently, no electrons are injected into the floating gate of the cell A 2  and, in other words, no data is written to the cell A 2 .  
     [0067] Then, the status of the cell B 1  will be described. The source and drain of the cell B 1  are connected to the source line SLi and drain line DLi, respectively, like the source and drain of the cell A 1 . There is a potential difference Vdp between the source and drain of the cell B 1 . However, the control gate of the cell B 1  is connected to the control gate line CGj+1 other than the control gate line CGj to which the control gate of the cell A 1  is connected. The control gate line CGj+1 is set at the ground potential GND. Therefore, no electrons are injected into the floating gate and, in other words, no data is written to the cell B 1 .  
     [0068] As for the cell B 2 , there is no difference in potential between the source and drain and the control gate is set at the ground potential GND. Thus, no data is written to the cell B 2 , either.  
     [0069] As described above, data is written to only the cell A 1 .  
     [0070] An operation of writing data to the cell A 2  will now be described. First, the semiconductor substrate (well region)  11  is set at the ground potential GND. The voltage generation circuit  60  sets the source lines SL 1  to SLi−1 at the ground potential GND and applies the potential Vdp to the source lines SLi to SLm. The drain lines DL 1  to DLi−1 are set at the ground potential GND and the potential Vdp is applied to the drain lines DLi to DLm through the sense amplifier  50 . The row decoder  20  applies the potential Vgp to the control gate line CGj and sets the other control gate lines CG 1  to CGj−1 and CGj+1 to CGn at the ground potential GND. In the cell A 2 , therefore, the potential Vgp is applied to the control gate and the potential difference Vdp is applied between the source and drain. Thus, data is written to the cell A 2 .  
     [0071] The status of the cell A 1  appearing when data is written to the cell A 2  will now be described. The potential Vgp is applied to the control gate of the cell A 1  like the control gate of the cell A 2 . However, the potentials of the source line SLi and drain line DLi connected to the source and drain of the cell A 1  are both Vdp. In other words, there is no difference in potential between the source and drain of the cell A 1 . No data is therefore written to the cell A 1 .  
     [0072] As for the cell B 1 , there is no difference in potential between the source and drain and the control gate is set at the ground potential GND. Thus, no data is written to the cell B 1 , either.  
     [0073] The status of the cell B 2  will be described. There is a difference in potential between the source and drain of the cell B 2 . However, the control gate of the cell B 2  is connected to the control gate line CGj+1 set at the ground potential GND. Data is not therefore written to the cell B 2 .  
     [0074] As described above, data is written to only the cell A 2 .  
     [0075] In order to write data to the cell B 1 , the potential Vgp has only to be applied to only the control gate line CGj+1 and the other control gate lines CG 1  to CGj and CGj+2 to CGn have only to be set at the ground potential GND when data is written to the cell A 1 . Thus, data is written to only the cell B 1  as described above with respect to the write of data to the cell A 1 .  
     [0076] In order to write data to the cell B 2 , the potential Vgp has only to be applied to only the control gate line CGj+1 and the other control gate lines CG 1  to CGj and CGj+2 to CGn have only to be set at the ground potential GND when data is written to the cell A 2 . Thus, data is written to only the cell B 2  as described above with respect to the write of data to the cell A 2 .  
     [0077] [Read Operation] 
     [0078] The read operation of the NOR EEPROM will be described with reference to FIGS. 2A and 3B, taking an operation of reading data from cell A 1  as an example.  
     [0079] First, the semiconductor substrate (well region)  11  is set at a ground potential GND. The voltage generation circuit  60  applies a potential Vdr to the source lines SL 1  to SLi−1 and sets the source lines SLi to SLm at the ground potential GND. The potential Vdr is applied to the drain lines DL 1  to DLi through the sense amplifier and the drain lines DLi+1 to DLm are set at the ground potential GND. The potential Vdr is, for example, about IV. The row decoder  20  applies a potential Vgr to the control gate line CGj and sets the other control gate lines CG 1  to CGj−1 and CGj+1 to CGn at the ground potential GND. The potential Vgr is, for example, about 5 V. In the cell A 1 , therefore, the potential Vgr is applied to the control gate and the potential difference Vdr is applied between the source and drain. If data is written to the cell A 1 , the threshold voltage of the cell A 1  is higher than the gate voltage Vgr; therefore, the cell A 1  turns off to prevent current from flowing between the source and drain of the cell A 1 . If the cell A 1  is in an erase state, the threshold voltage of the cell A 1  is lower than the gate voltage Vgr; therefore, the cell A 1  turns on to cause current to flow between the source and drain of the cell A 1 . Data can thus be read out of the cell A 1  according to whether current is present or absent in the drain line DLi of the cell A 1  (whether the potential of the drain line DLi varies or not).  
     [0080] The descriptions of the status of the other cells when data is read out of the cell A 1  are omitted. As in the write operation, no data is read out of the other cells (non-selected memory cells), because there is no difference in potential between the source and drain or the control gate is set at the ground potential.  
     [0081] An operation of reading data from the cell A 2  will now be described. First, the semiconductor substrate (well region)  11  is set at the ground potential GND. The voltage generation circuit  60  sets the source lines SL 1  to SLi−1 at the ground potential GND and applies the potential Vdr to the source lines SLi to SLm. The drain lines DL 1  to Dli−1 are set at the ground potential GND and the potential Vdr is applied to the drain lines DLi to DLm through the sense amplifier  50 . The row decoder  20  applies the potential Vgr to the control gate line CGj and sets the other control gate lines CG 1  to CGj−1 and CGj+1 to CGn at the ground potential GND. In the cell A 2 , therefore, the potential Vgr is applied to the control gate and the potential difference Vdr is applied between the source and drain. Thus, data is read out of the cell A 2 .  
     [0082] In order to read data from the cell B 1 , the potential Vgr has only to be applied to only the control gate line CGj+1 and the other control gate lines CG 1  to CGj and CGj+2 to CGn have only to be set at the ground potential GND when data is read out of the cell A 1 . Thus, data is read from only the cell B 1  as in the operation of reading data from the cell A 1 .  
     [0083] In order to read data from the cell B 2 , the potential Vgr has only to be applied to only the control gate line CGj+1 and the other control gate lines CG 1  to CGj and CGj+2 to CGn have only to be set at the ground potential GND when data is read out of the cell A 2 . Thus, data is read from only the cell B 2  as in the operation of reading data from the cell A 2 .  
     [0084] [Erase Operation] 
     [0085] The erase operation of the NOR EEPROM according to the first embodiment is similar to that of the prior art EEPROM. A positive potential of about 10 V is applied to all the drain lines DL 1  to DLm and all the source lines SL 1  to SLm. A negative potential of about −8 V is applied to all the control gate lines CG 1  to CGn. Consequently, electrons are extracted from the floating gates of all the memory cells MC toward the semiconductor substrate and data is erased from the memory cells MC.  
     [0086] In the foregoing NOR EEPROM according to the first embodiment of the present invention, the drains of memory cells in adjacent two columns are connected to a common drain line and the sources of memory cells in adjacent two columns are connected to a common source line. The sources of memory cells of two columns, whose drains are connected to a common drain line DLi, are connected to source lines SLi and SLi−1. The drains of memory cells of two columns, whose sources are connected to a common source line SLi, are connected to drain lines DLi and DLi+1. Thus, the sources or drains of adjacent four memory cells are connected to each other. The number of source contact plugs and that of drain contact plugs each can be reduced by half, though conventionally two memory cells required one source contact plug and one drain contact plug. The contact plugs, which interfered with microfabrication, can be reduced in number and thus the NOR EEPROM can be increased in packing density further. If the contact plugs are decreased in number, the cross-sectional area of the contact plug can be made larger than that of the prior art EEPROM. Consequently, the contact resistance at the contact plug can be lowered and accordingly the electrical characteristics of the NOR EEPROM can be improved.  
     [0087] A nonvolatile semiconductor memory according to a second embodiment of the present invention will now be described with reference to FIG. 4, taking an EEPROM as an example. FIG. 4 is a circuit diagram of a NOR EEPROM according to the second embodiment.  
     [0088] As shown in FIG. 4, the source and drain lines of the first embodiment are replaced with bit lines BL 1  to BLk. Furthermore, the column decoders  30   a  and  30   b  of the first embodiment are replaced with one column decoder  30  and the column selectors  40   a  and  40   b  thereof are replaced with one column selector  40 .  
     [0089] A memory cell array  10  includes a plurality of memory cells MC arranged in matrix. The control gates of memory cells MC arranged in the same row are connected to a common control gate line CGj (j=1 to n, j and n are each natural number). Adjacent memory cells MC in the same column have one of impurity diffusion layers, which serve as source and drain regions, in common. One impurity diffusion layer of the memory cells MC in one column and that of memory cells MC in one adjacent column are connected to a common bit line BLi (i=1 to k, i and k are each natural number). The other impurity diffusion layer of the memory cells MC in the one column and that of memory cells MC in the other adjacent column are connected to a common bit line BLi+1 (or BLi−1).  
     [0090] The row decoder  20  decodes an externally input row address signal. In response to the row address signal, the row decoder applies a given voltage to the control gate lines CG 1  to CGn.  
     [0091] The column decoder  30  decodes an externally input column address signal. In response to the column address signal, the column decoder  30  controls the column selector  40 .  
     [0092] The column selector  40  selects one from among the bit lines BL 1  to BLk in response to the decoded column address signal.  
     [0093] In write mode, a sense amplifier  50  latches write data. In read mode, the sense amplifier  50  latches data read out of a memory cell MC.  
     [0094] Since the plan and sectional views of the memory cell array  10  are the same as those shown in FIGS. 2B to  2 F, the descriptions of the configuration of the memory cell array are omitted. In the second embodiment, however, each of the impurity diffusion layers  13   a  and  13   b  serves as either of source and drain. Accordingly, the drain contact plug  18   a  and source contact plug  18   b  both serve as bit line contact plugs connected to the bit lines BL 1  to BLk.  
     [0095] An operation of the NOR EEPROM according to the second embodiment will now be described. As shown in FIG. 4, a memory cell MC whose gate is connected to the control gate line CGj and source-to-drain current path is connected between the bit lines BLi−1 and BLi is defined as cell A 1 . A memory cell MC whose gate is connected to the control gate line CGj and source-to-drain current path is connected between the bit lines BLi and BLi+1 is defined as cell A 2 . A memory cell MC whose gate is connected to the control gate line CGj+1 and source-to-drain current path is connected between the bit lines BLi−1 and BLi is defined as cell B 1 . A memory cell MC whose gate is connected to the control gate line CGj+1 and source-to-drain current path is connected between the bit lines BLi and BLi+1 is defined as cell B 2 .  
     [0096] [Write Operation] 
     [0097] The write operation of the NOR EEPROM according to the second embodiment will be described with reference to FIGS. 5 and 6A, taking an operation of writing data to the cell A 1  as an example. FIG. 5 is a table showing voltages applied in the write operation of the NOR EEPROM. FIG. 6A is an enlarged circuit diagram of part of the NOR EEPROM shown in FIG. 4.  
     [0098] First, the semiconductor substrate (well region) is set at a ground potential GND. The bit lines BL 1  to BLi−1 are set at the ground potential GND and a potential Vdp is applied to the bit lines BLi to BLk through the sense amplifier. The row decoder  20  applies a potential Vgp to the control gate line CGj and sets the other control gate lines CG 1  to CGj−1 and CGj+1 to CGn at the ground potential GND. As shown in FIG. 6A, the bit line BLi−1 functions as a source line and the bit line BLi functions as a drain line. Paying attention to the cell A 1 , the impurity diffusion layer connected to the bit line BLi−1 serves as a source region and the impurity diffusion layer connected to the bit line BLi serves as a drain region. A potential difference Vdp is applied between the source and drain of the cell A 1 . Current (indicated by the arrow in FIG. 6A) flows through a channel region between the source and drain of the cell A 1  and consequently data is written to the cell A 1 .  
     [0099] As for the other memory cells MC, there is no difference in potential between the source and drain, or no potential is applied to the control gate line CG; therefore, no data is written to the other memory cells MC.  
     [0100] An operation of writing data to the cell A 2  will now be described with reference to FIGS. 5 and 6B. FIG. 6B is an enlarged circuit diagram of part of the NOR EEPROM shown in FIG. 4.  
     [0101] First, the semiconductor substrate (well region) is set at a ground potential GND. The bit lines BL 1  to BLi−1 are set at the ground potential GND and a potential Vdp is applied to the bit lines BLi+1 to BLk through the sense amplifier. The row decoder  20  applies a potential Vgp to the control gate line CGj and sets the other control gate lines CG 1  to CGj−1 and CGj+1 to CGn at the ground potential GND. As shown in FIG. 6B, the bit line BLi functions as a source line and the bit line BLi+1 functions as a drain line. Paying attention to the cell A 2 , the impurity diffusion layer connected to the bit line BLi serves as a source region and the impurity diffusion layer connected to the bit line BLi+1 serves as a drain region. A potential difference Vdp is applied between the source and drain of the cell A 2 . Current (indicated by the arrow in FIG. 6B) flows through a channel region between the source and drain of the cell A 2  and consequently data is written to the cell A 2 .  
     [0102] As for the other memory cells MC, there is no difference in potential between the source and drain, or no potential is applied to the control gate line CG; therefore, no data is written to the other memory cells MC.  
     [0103] In order to write data to the cell B 1 , the potential Vgp has only to be applied to only the control gate line CGj+1 and the other control gate lines CG 1  to CGj and CGj+2 to CGn have only to be set at the ground potential GND when data is written to the cell A 1 . Thus, data is written to only the cell B 1  as described above with respect to the write of data to the cell A 1 . In this case, the bit line BLi−1 serves as a source line and the bit line BLi serves as a drain line as in the operation of writing data to the cell A 1 .  
     [0104] In order to write data to the cell B 2 , the potential Vgp has only to be applied to only the control gate line CGj+1 and the other control gate lines CG 1  to CGj and CGj+2 to CGn have only to be set at the ground potential GND when data is written to the cell A 2 . Thus, data is written to only the cell B 2  as described above with respect to the write of data to the cell A 2 . In this case, the bit line BLi−1 serves as a source line and the bit line BLi serves as a drain line as in the operation of writing data to the cell A 2 .  
     [0105] [Read Operation] 
     [0106] The read operation of the NOR EEPROM according to the second embodiment will be described with reference to FIGS. 7 and 8A, taking an operation of reading data from the cell A 1  as an example. FIG. 7 is a table showing voltages applied in the read operation of the NOR EEPROM. FIG. 8A is an enlarged circuit diagram of part of the NOR EEPROM shown in FIG. 4.  
     [0107] First, the semiconductor substrate (well region) is set at a ground potential GND. The bit lines BL 1  to BLi−1 are set at the ground potential GND and a potential Vdr is applied to the bit lines BLi to BLk through the sense amplifier. The row decoder  20  applies a potential Vgr to the control gate line CGj and sets the other control gate lines CG 1  to CGj−1 and CGj+1 to CGn at the ground potential GND. As shown in FIG. 8A, the bit line BLi−1 functions as a source line and the bit line BLi functions as a drain line. Paying attention to the cell A 1 , the impurity diffusion layer connected to the bit line BLi−1 serves as a source region and the impurity diffusion layer connected to the bit line BLi serves as a drain region. A potential difference Vdr is applied between the source and drain of the cell A 1 . If data is written to the cell A 1 , the cell A 1  turns off and no current flows between the source and drain of the cell A 1 . If the cell A 1  is in an erase state, it turns on and current flows between the source and drain of the cell A 1 . The sense amplifier senses whether current is present or absent in the bit line BLi (whether the potential of the bit line BLi varies or not), thereby reading data from the cell A 1 .  
     [0108] An operation of reading data from the cell A 2  will now be described with reference to FIGS. 7 and 8B. FIG. 8B is an enlarged circuit diagram of part of the NOR EEPROM shown in FIG. 4.  
     [0109] First, the semiconductor substrate (well region)  11  is set at a ground potential GND. The bit lines BL 1  to BLi are set at the ground potential GND and a potential Vdr is applied to the bit lines BLi+1 to BLk through the sense amplifier. The row decoder  20  applies a potential Vgr to the control gate line CGj and sets the other control gate lines CG 1  to CGj−1 and CGj+1 to CGn at the ground potential GND. As shown in FIG. 8B, the bit line BLi functions as a source line and the bit line BLi+1 functions as a drain line. Paying attention to the cell A 2 , the impurity diffusion layer connected to the bit line BLi serves as a source region and the impurity diffusion layer connected to the bit line BLi+1 serves as a drain region. The potential difference Vdr is applied between the source and drain of the cell A 2 . If data is written to the cell A 2 , no current flows between the source and drain of the cell A 2 . If the cell A 2  is in an erase state, current flows between the source and drain of the cell A 2 . The sense amplifier senses whether current is present or absent in the bit line BLi+1 (whether the potential of the bit line BLi+1 varies or not), thereby reading data from the cell A 2 .  
     [0110] In order to read data from the cell B 1 , the potential Vgr has only to be applied to only the control gate line CGj+1 and the other control gate lines CG 1  to CGj and CGj+2 to CGn have only to be set at the ground potential GND when data is read out of the cell A 1 . Thus, data is read from the cell B 1  as described above with respect to the read of data from the cell A 1 . In this case, the bit line BLi−1 serves as a source line and the bit line BLi serves as a drain line as in the operation of reading data from the cell A 1 .  
     [0111] In order to read data from the cell B 2 , the potential Vgr has only to be applied to only the control gate line CGj+1 and the other control gate lines CG 1  to CGj and CGj+2 to CGn have only to be set at the ground potential GND when data is read out of the cell A 2 . Thus, data is read from the cell B 2  as described above with respect to the read of data from the cell A 2 . In this case, the bit line BLi−1 serves as a source line and the bit line BLi+1 serves as a drain line as in the operation of reading data from the cell A 2 .  
     [0112] [Erase Operation] 
     [0113] The erase operation of the NOR EEPROM according to the second embodiment is similar to that of the prior art EEPROM.  
     [0114] In the foregoing NOR EEPROM according to the second embodiment, one of source and drain of memory cells in adjacent two columns is connected to a common bit line and the other is connected to a different bit line. The memory cells of two columns, which are connected to a common bit line BLi, are connected to bit lines BLi−1 and BLi+1. The memory cells of two columns, which are connected to a common bit line BLi−1, are connected to bit lines BLi and BLi−2. Further, the memory cells of two columns, which are connected to a common bit line BLi+1, are connected to bit lines BLi and BLi+2. As in the first embodiment, therefore, four memory cells have one bit line contact plug in common. The number of contact plugs can be reduced by half. The NOR EEPROM can thus be increased in packing density further. Furthermore, the cross-sectional area of the contact plug can be made larger than that of the prior art EEPROM. Consequently, the contact resistance at the contact plug can be lowered and accordingly the electrical characteristics of the NOR EEPROM can be improved.  
     [0115] The impurity diffusion layers of the memory cells MC included in the NOR EEPROM according to the second embodiment are connected to the bit lines BL, not the source or drain lines. In other words, the impurity diffusion layers of the memory cells MC are not divided into source and drain regions. The bit line BL alternately serves as a source line and a drain line in accordance with a selected memory cell MC. As has been described with reference to FIGS. 6A and 6B and FIGS. 8A and 8B, the bit line BLi serves as a drain line if the bit line BLi−1 serves as a source line when a memory cell connected to the bit lines BLi−1 and BLi is selected. In contrast, the bit line BLi serves as a source line if a memory cell connected to the bit lines BLi and BLi+1 is selected. Needless to say, when a memory cell connected to the bit lines BLi−1 and BLi is selected, the bit line BL can serves as a source line if the bit line BLi−1 can serves as a drain line.  
     [0116] Since both source and drain lines need not be used as described above, one column selector is sufficient for the second embodiment though two column selectors are required in the first embodiment. In other words, the source line SL and drain line DL can have one column selector in common. Furthermore, the voltage generation circuit  60  of the first embodiment exclusively for the source line SL becomes unnecessary. Thus, the circuit arrangement of the second embodiment can be simplified more greatly than that of the first embodiment, and the NOR EEPROM can be downsized.  
     [0117] As described above, according to the first and second embodiments of the present invention, adjacent four memory cells in the row and column directions have one of impurity diffusion layers in common. The number of contact plugs can thus be reduced by half. Therefore, the NOR EEPROM can be increased in packing density further. Furthermore, the cross-sectional area of the contact plug can be made larger than that of the prior art EEPROM. Consequently, the contact resistance at the contact plug can be lowered and accordingly the electrical characteristics of the NOR EEPROM can be improved.  
     [0118]FIG. 9A is a plan view of a NOR EEPROM according to a first modification to the first and second embodiments of the present invention. FIG. 9B is a cross-sectional view taken along line  9 B- 9 B of FIG. 9A. Neither source line SL nor drain line DL is shown.  
     [0119] Referring to FIG. 9A, a source contact plug SP and a drain contact plug DP are formed so as to reach the source and drain regions not only in an element region AA′ but also in one of its adjacent element regions AA. The cross-sectional area of the source contact plug SP and drain contact plug DP is larger than that in the first and second embodiments. In the first modification shown in FIG. 9A, the cross-sectional area is about twice as large as that in the first and second embodiments. Consequently, the source contact plug SP and drain contact plug DP can be decreased in resistance. Moreover, the contact area of the source contact plug SP and drain contact plug DP and the source and drain regions increases, with the result that the contact resistance can be lowered. The electrical characteristics of the NOR EEPROM can be improved.  
     [0120]FIG. 10A is a plan view of a NOR EEPROM according to a second modification to the first and second embodiments of the present invention. FIG. 10B is a cross-sectional view taken along line  10 B- 10 B of FIG. 10A. Neither source line SL nor drain line DL is shown.  
     [0121] Referring to FIG. 10A, a source contact plug SP and a drain contact plug DP are formed so as to reach the source and drain regions not only in an element region AA′ but also in its adjacent two element regions AA. The same advantage as that of the above first modification can be obtained from the second modification.  
     [0122] In the second modification, each of the contact plugs SP and DP can be provided in contact with its adjacent element isolation region ST 1  in the row direction. In other words, each of the contact plugs can be expanded in the lateral direction as much as possible. In this case, the cross-sectional area of each of the contact plugs is about three times as large as that in the first and second embodiment and thus the contact resistance can be lowered further.  
     [0123]FIG. 11 is a plan view of a NOR EEPROM according to a third modification to the first and second embodiments of the present invention. No element isolation regions ST 1  are shown. FIG. 11 shows a plane pattern of source and drain lines SL and DL of the first and second modifications. As shown, a portion with a contact plug and a portion without a contact plug are alternated with each other in the row direction in adjacent control gate lines. Therefore, the source and drain lines SL and DL can be broadened in regions where they are connected to the contact plugs and narrowed in the other regions. Using such a pattern, the top surfaces of the contact plugs can completely be covered with a metal wiring layer and the drain and source lines DL and SL can be formed by a metal wiring layer of the same level. Needless to say, the source and drain lines SL and DL can be formed by a metal wiring layer of a different level.  
     [0124] In the foregoing first to third modifications, too, both source and drain regions need not be formed. In other words, the bit lines can be used in place of the source and drain lines.  
     [0125] The embodiments of the present invention have been described, taking a NOR EEPROM as an example throughout the first and second embodiments and the first to third modifications thereto; however, it is not limited to the NOR EEPROM. For example, the embodiment of the present invention can be applied to a NAND EEPROM or a semiconductor memory other than the EEPROM.  
     [0126] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.