Patent Publication Number: US-6906357-B1

Title: Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to semiconductor circuit structures, and in particular, to semiconductor circuit structures providing electrostatic discharge (ESD) protection for integrated circuits. 
   2. Description of the Related Art 
   Electrostatic discharge (ESD) protection devices are widely used in an integrated circuit (IC) to protect the electronic devices within the IC, e.g., bipolar junction transistors (BJTs) and metal oxide semiconductor field effect transistors (MOSFETs), from spurious voltage pulses caused by various sources of electrostatic energy. Numerous conventional ESD protection structures and devices are well known in the art, and include the use of BJTs, MOSFETs, grounded gate metal oxide semiconductor (GGMOS) structures, low voltage triggered silicon controlled rectifiers (LVTSCRs), triacs and diacs. 
   Electrostatic discharge events produce voltages that typically have large magnitudes and can be either positive or negative in polarity (i.e., with respect to the reference, or ground, potential of the circuit to be protected). Most conventional ESD protection structures can only protect against ESD events of a single polarity. Accordingly, for protection against both positive and negative ESD voltages, at least two distinct ESD protection structures are normally required. 
   For some applications, as a practical matter, only one dedicated ESD protection structure need be provided for protecting against positive ESD event voltages. Negative ESD event voltages can be clamped at a safe voltage by the inherent body diode present in most circuits (discussed in more detail below). 
   Referring to  FIG. 1 , one common device used for an ESD protection structure is a diac  10 , which is well known in the art. Between the two electrical terminals  11   a  (T 1 ),  11   b  (T 2 ) multiple semiconductor layers  12   p ,  12   n ,  14 ,  16   n ,  16   p . As is well known, the diac  10  is a bi-directional device that becomes conductive when the voltage at one terminal T 1  (T 2 ) becomes more positive than the voltage at the other terminal T 2  (T 1 ) by an amount greater than the predetermined trigger voltage, and remains conductive, i.e., continues to conduct current from the more positive to the less positive terminal, until such inter-terminal voltage becomes less than a predetermined holding voltage. 
   Referring to  FIG. 2 , the implementation of a diac  10   a  as an ESD protection structure within an IC environment typically appears as shown. The P-type substrate  14 , which is typically connected to a circuit reference, or ground, electrode  18 , has two N-type wells  12   n ,  16   n  diffused or implanted into its surface, separated by a gap region  14   g . Within the first well  12   n  are a similarly diffused or implanted N-type contact region  12   na  and P-type contact region  12   p  both of which are connected to one of the diac terminals  11   a . Within the second well  16   n  are another similarly diffused or implanted N-type contact region  16   na  and P-type contact region  16   p , both of which are connected to the other diac terminal  11   b . As noted above, this diac structure  10   a  will provide protection for a positive voltage appearing across the terminals  11   a ,  11   b  (one of which is typically connected to the circuit reference electrode  18 ), but will not provide the primary protection against negative ESD voltages due to the so-called “body diode” which exists by nature of the PN junction between the P-type substrate  14  and the N-type well  12   n / 16   n.    
   For many circuits or applications, such asymmetrical ESD protection can be acceptable. However, some circuits or systems must be tolerant of negative voltages appearing at the terminals to be protected from ESD events without being clamped at the typically low voltages associated with the body diode. One example of such a circuit would be a circuit used for measuring current in the operation of a circuit or system with a heavy inductive load (e.g., for driving a motor). For proper accuracy, influences created by the chip during operation of the host circuit or system must be minimized, including avoidance of premature voltage clamping caused by voltage spikes which may at first appear, albeit incorrectly, to be an ESD event. 
   SUMMARY OF THE INVENTION 
   In accordance with the presently claimed invention, an electrostatic discharge (ESD) protection structure is provided with a diac in which substantially similar ESD protection is provided for both positive and negative ESD voltages appearing at the circuit electrode sought to be protected. 
   In accordance with one embodiment of the presently claimed invention, an electrostatic discharge (ESD) protection structure with a diac includes one or more reference electrodes, a circuit electrode, a semiconductor material, semiconductor regions and semiconductor wells. The semiconductor material is of a first conductivity type and in electrical communication with one or more of the one or more reference electrodes. A first semiconductor region of the first conductivity type is disposed on the semiconductor material and in electrical communication with at least one of the one or more reference electrodes. A second semiconductor region of a second conductivity type is disposed on the semiconductor material proximate the first semiconductor region and in electrical communication with the at least one of the one or more reference electrodes. A first semiconductor well of the second conductivity type is disposed in the semiconductor material. A second semiconductor well of the first conductivity type is disposed in the first semiconductor well. A third semiconductor region of the first conductivity type is disposed on the second semiconductor well and in electrical communication with the circuit electrode. A fourth semiconductor region of the second conductivity type is disposed on the second semiconductor well and in electrical communication with the circuit electrode. 
   In accordance with another embodiment of the presently claimed invention, an electrostatic discharge (ESD) protection structure with a diac includes one or more reference electrodes, a circuit electrode, a semiconductor material, semiconductor regions and semiconductor wells. The semiconductor material is of a first conductivity type and in electrical communication with one or more of the one or more reference electrodes. A first semiconductor region of the first conductivity type is disposed on the semiconductor material and in electrical communication with at least one of the one or more reference electrodes. A second semiconductor region of the second conductivity type is disposed on the semiconductor material proximate the first semiconductor region and in electrical communication with the at least one of the one or more reference electrodes. A first semiconductor well of a second conductivity type is disposed in the semiconductor material. A second semiconductor well of the second conductivity type is disposed in the first semiconductor well. A third semiconductor well of the first conductivity type is disposed in the second semiconductor well. A third semiconductor region of the first conductivity type is disposed on the third semiconductor well and in electrical communication with the circuit electrode. A fourth semiconductor region of the second conductivity type is disposed on the third semiconductor well and in electrical communication with the circuit electrode. 
   In accordance with still another embodiment of the presently claimed invention, an electrostatic discharge (ESD) protection structure with a diac includes one or more reference electrodes, a circuit electrode, a semiconductor material, a semiconductor layer, semiconductor regions and semiconductor wells. The semiconductor material is of a first conductivity type and in electrical communication with one or more of the one or more reference electrodes. A first semiconductor region of the first conductivity type is disposed on the semiconductor material and in electrical communication with at least one of the one or more reference electrodes. A second semiconductor region of the second conductivity type is disposed on the semiconductor material proximate the first semiconductor region and in electrical communication with the at least one of the one or more reference electrodes. The semiconductor layer is of a second conductivity type and disposed in the semiconductor material. A first semiconductor well of the second conductivity type is disposed on the semiconductor layer. A second semiconductor well of the first conductivity type is disposed in the first semiconductor well. A third semiconductor region of the first conductivity type is disposed on the second semiconductor well and in electrical communication with the circuit electrode. A fourth semiconductor region of the second conductivity type is disposed on the second semiconductor well and in electrical communication with the circuit electrode. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  depicts the structure of a conventional diac. 
       FIG. 2  is a cross-sectional view of a conventional implementation of a diac in an IC. 
       FIG. 3A  is a cross-sectional view of an implementation of a diac structure for ESD protection in accordance with one embodiment of the presently claimed invention. 
       FIG. 3B  is a cross-sectional view of an implementation of a diac structure for ESD protection in accordance with another embodiment of the presently claimed invention. 
       FIG. 4  is a graph of the current-versus-voltage characteristic for one example implementation of a diac structure for ESD protection in accordance with the presently claimed invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
   Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
   Referring to  FIG. 3A , in accordance with one embodiment of the presently claimed invention, an ESD protection structure  100   a  includes a diac and can be described as follows. (It should be understood that while the following discussion is in terms of specific orders or sequences of P-type and N-type semiconductor materials, substrates, layers, wells, diffusions or implants, such orders or sequences can be reversed, i.e., P-types and N-types can be interchanged, in accordance with well known IC design and fabrication techniques without departing from the spirit and scope of the presently claimed invention. Further, it should also be understood that the semiconductor layers, wells, and regions discussed herein can be implemented using well known diffusion and implantation techniques as appropriate.) 
   A P-type substrate  114  includes an N-type region  112  which can be implemented as an N-type well, or alternatively as an N-type isolation layer  112   ni  on top of which is an N-type well  112   nw . (It should be understood that the substrate  114  can include all of the P-type semiconductor material as shown, or alternatively, can be a P-type substrate area  114   s  on top of which the remaining semiconductor layers and regions are deposited or otherwise added.) Within this well  112 / 112   nw  is a P-type well  112   pw . In turn, within this well  112   pw  are an N-type contact region  112   na  and a P-type contact region  112   pa , both of which are connected to a circuit electrode  111   a  for the circuit sought to be protected against ESD events. As a result, two blocking junctions are provided between the circuit electrode  111   a  and the reference electrode  118  to which the substrate  114  is connected: the PN junction between wells  112   pw  and  112 / 112   nw ; and the PN junction between well  112 / 112   nw  and substrate  114 / 114   s.    
   The substrate  114 / 114   s  includes at least one additional set of contact regions, including one or more of: an N-type contact region  116   na  and a P-type contact region  116   pa  connected to a circuit reference electrode  111   ba ; and another N-type contact region  116   nb  and P-type contact region  116   pb  connected to another circuit reference terminal  111   bb . These N-type contact regions  116   na ,  116   nb  and P-type contact regions  116   pa ,  116   pb  can be distinct contact regions, or alternatively, can form common N-type and P-type semiconductor rings within an annular region about the N-type well  112 / 112   nw . Additionally, the reference electrodes  111   ba ,  111   bb  can be separate electrodes or one common electrode connected or available for connection to the reference electrode  118  to which the substrate  114 / 114   s  is connected. Additionally, these contact regions  116   na ,  116   pa ,  116   nb ,  116   pb  can, in turn, be disposed within respective P-type wells  114   wa ,  114   wb  within the substrate  114 / 114   s , with such wells  114   wa ,  114   wb  being either distinct wells or portions of a common annular well (e.g., a latch-up guard ring) about N-type well  112 / 112   nw.    
   Referring to  FIG. 3B , an alternative embodiment  100   b  of an ESD protection structure with a diac in accordance with the presently claimed invention includes a structure similar to that shown in and described in connection with FIG.  3 A. In this embodiment  100   b , the contact regions  116   n ,  116   p  for the reference electrode  111   b  are disposed between wells  112   a / 1112   nwa ,  112   pwa ,  112   b / 112   nwb ,  112   pwb  and contact regions  112   naa ,  112   paa ,  112   nab ,  112   pab  for the circuit electrodes  111   aa ,  111   ab . Similar to the embodiment  100   a  of  FIG. 3A , these outer semiconductor wells  112   a / 112   nwa ,  112   pwa ,  112   b / 112   nwb ,  112   pwb  and contact regions  112   naa ,  112   paa ,  112   nab ,  112   pab  can be separate or portions of an annular region surrounding the contact regions  116   n ,  116   p  for the reference electrode  111   b.    
   As is well known in the art, the various semiconductor layers, wells and contact regions discussed above will have various concentrations of dopants introduced to change or otherwise control the charge carrier concentrations. Further, also in accordance with well known semiconductor circuit fabrication techniques, the dopant concentrations of the P-type contact regions  112   pa ,  116   pa ,  116   pb ,  112   paa ,  112   pab ,  116   p  will generally be greater than the dopant concentrations for the P-type wells  112   pw ,  114   wa ,  114   wb ,  112   pwa ,  112   pwb ,  114   w  and substrate  114 / 114   s . Similarly, the dopant concentrations for the N-type contact regions  112   na ,  116   na ,  116   nb ,  112   naa ,  112   nab ,  116   n  will be greater than the dopant concentrations of the N-type wells  112 / 112   nw  and isolation layer  112   ni.    
   Operations of these ESD protection structures  100   a ,  100   b  during ESD events are in accordance with well-known operating principles for such diac structures and need not be discussed here. (For example, for discussions about general principles of operation of these types of ESD protection structures, including current avalanche breakdown mechanisms and “double injection” of holes and electrons during ESD events, see U.S. Pat. Nos. 6,355,959, 6,433,368 and 6,541,801, the disclosures of which are incorporated herein by reference.) 
   Referring to  FIG. 4 , by eliminating the normal body diode effect through the introduction of the dual blocking junctions (discussed above), the ESD protection provided by the above-described ESD protection structures  100   a ,  100   b  becomes substantially symmetrical with respect to positive and negative polarity ESD voltages. As can be seen, for both positive and negative voltage biases at the circuit electrodes  111   a ,  111   aa ,  111   ab , voltage breakdown pursuant to the desired ESD protection occurs at approximately 30 volts in both cases. Accordingly, an ESD protection structure with a diac in accordance with the presently claimed invention provides substantially similar ESD protection for both positive and negative ESD voltages appearing at the circuit electrode sought to be protected. 
   Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and equivalents be covered thereby.