Patent Publication Number: US-2016233163-A1

Title: Semiconductor device and method of manufacturing semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from U.S. Provisional Application No. 62/114,415, filed on Feb. 10, 2015; the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     Embodiments described herein relates generally to a semiconductor device and a method of manufacturing the semiconductor device. 
     BACKGROUND 
     Among MOS (Metal Oxide Semiconductor) transistors as an example of a semiconductor device, there is a high breakdown voltage transistor for which a high breakdown voltage is required in a drain or the like. Such a high breakdown voltage transistor is configured to have a wide element area in order to increase the breakdown voltage of the drain. 
     However, when the element area is widened, the semiconductor device is increased in area. Therefore, it is desirable that the high breakdown voltage transistor be formed while suppressing the increase of a circuit area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating an exemplary configuration of a transistor according to a first embodiment; 
         FIG. 2  is a diagram for describing a resistance value in a drain of the transistor according to the first embodiment; 
         FIG. 3  is a diagram for describing the resistance value in the drain in a case where a plug portion connected to the drain is made of metal; 
         FIG. 4  is a diagram for describing a breakdown voltage of the drain in a case where the resistance of a wiring plug is low; 
         FIG. 5  is a diagram illustrating a relation between a sheet resistance of an n-type diffusion layer and a breakdown voltage of the drain; 
         FIG. 6  is a diagram illustrating an exemplary configuration of a transistor which is manufactured to have a long distance between a gate and a second n +  layer; 
         FIG. 7  is a flowchart illustrating a procedure of forming the transistor according to the first embodiment; 
         FIG. 8  is a diagram illustrating an exemplary configuration of a transistor according to a second embodiment; and 
         FIG. 9  is a diagram illustrating an exemplary configuration of a transistor according to a third embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     According to the embodiments, there is provided a semiconductor device. The semiconductor device includes a first transistor and a second transistor. The first transistor is connected to a first wiring through a wiring plug made of a material having a first resistance value smaller than a predetermined value. In addition, at least one of a drain and a source of the second transistor is connected to a second wiring through a polysilicon plug made of a material having a second resistance value larger than the first resistance value. 
     A semiconductor device and a method of manufacturing the semiconductor device according to embodiments will be described in detail with reference to the accompanying drawings below. Further, the invention is not limited to these embodiments. 
     First Embodiment 
       FIG. 1  is a diagram illustrating an exemplary configuration of a transistor according to a first embodiment.  FIG. 1  illustrates a cross-sectional configuration of a MOS (Metal Oxide Semiconductor) transistor (a transistor  10 HA). The transistor  10 HA is a transistor (a semiconductor device) which is required for a high breakdown voltage. Further, the transistor  10 HA may be an nMOS transistor, or may be a pMOS transistor. In the following, the description will be made about a case where the transistor  10 HA is the nMOS transistor (an HV nMOS). 
     In a transistor circuit of the embodiment, a low breakdown voltage transistor is connected to a first wiring through a wiring plug (a contact plug) made of a material having a first resistance value smaller than a predetermined value. Then, the transistor  10 HA having a high breakdown voltage is connected to a second wiring through a polysilicon plug (a polysilicon layer) made of a material having a second resistance value larger than the first resistance value. With this configuration, the breakdown voltage of the drain of the transistor  10 HA is improved using a small area. 
     The transistor  10 HA includes a source  20 S, a gate  20 G, and a drain  20 D. Then, the source  20 S, the gate  20 G, and the drain  20 D are connected to a contact plug or a wiring layer (an interconnect layer) on an upper layer side of the transistor  10 HA. The source  20 S includes an n-type diffusion layer  1 Sn, and the drain  20 D includes an n-type diffusion layer  1 Dn. In the transistor  10 HA, the gate  200  is formed between the source  20 S and the drain  20 D. 
     The n-type diffusion layers  1 Sn and  1 Dn is formed by a first n −  layer (a silicon layer) having an impurity concentration lower than a predetermined value. The n-type diffusion layers  1 Sn and  1 Dn, for example, are simultaneously formed in the same process to have the same impurity concentration. Further, the impurity concentration of the n-type diffusion layer  1 Sn and the impurity concentration of the n-type diffusion layer  1 Dn may be different from each other. 
     The contact plug (the polysilicon plug) connected to a wiring layer  11   s  is provided on the upper layer side of the n-type diffusion layer  1 Sn. Therefore, the source  20 S and the wiring layer  11   s  are connected through the contact plug. The wiring layer  11   s , for example, is a metal wiring layer. 
     The contact plug connected to the source  20 S includes a plug portion  12   sn  and a plug portion  13   sn . The plug portion  12   sn  is formed on the upper portion side of the plug portion  13   sn . Therefore, the plug portion  13   sn  is formed on the upper layer side of the n-type diffusion layer  1 Sn, and the plug portion  12   sn  is formed in the upper portion of the plug portion  13   sn.    
     The plug portion  12   sn  is formed by a first n +  layer (the polysilicon layer) having an impurity concentration higher than a predetermined value, and the plug portion  13   sn  is formed by a second n layer (the polysilicon layer) having an impurity concentration lower than a predetermined value. The first n +  layer may have an impurity concentration at which the wiring layer  11   s  and the plug portion  12   sn  come into ohmic contact with each other. Therefore, in a case where the wiring layer  11   s  is a polysilicon, the plug portion  12   sn  may be formed by the first or second n −  layer. In addition, in a case where the breakdown voltage required for the source  20 S is lower than a predetermined value, the plug portions  12   sn  and  13   sn  may be formed using a metal layer. 
     The contact plug (the polysilicon plug) connected to a wiring layer lid is provided on the upper layer side of the n-type diffusion layer  1 Dn. Therefore, the drain  20 D and the wiring layer lid are connected through the contact plug. The wiring layer  11   d , for example, a metal wiring layer. 
     The contact plug connected to the drain  20 D includes a plug portion  12   dn  and a plug portion  13   dn . The plug portion  12   dn  is formed on the upper portion side of the plug portion  13   dn . Therefore, the plug portion  13   dn  is formed on the upper layer side of the n-type diffusion layer  1 Dn, and the plug portion  12   dn  is formed on the upper portion side of the plug portion  13   dn.    
     The plug portion  12   dn  is formed by the first n +  layer (the polysilicon layer) having an impurity concentration higher than a predetermined value. In other words, the plug portion  12   dn  is formed using a material having a resistance value lower than a predetermined value. 
     In addition, the plug portion  13   dn  is formed by the second n −  layer (the polysilicon layer) having an impurity concentration lower than a predetermined value. In other words, the plug portion  13   dn  is formed using a material having a resistance value higher than a predetermined value. 
     The first n +  layer may have an impurity concentration at which the wiring layer lid and the plug portion  12   dn  come into ohmic contact with each other. Therefore, in a case where the wiring layer lid is polysilicon, the plug portion  12   dn  may be formed by the first or second n −  layer. 
     Further, the impurity concentration of the plug portion  12   dn  and the impurity concentration of the plug portion  12   sn  may be different from each other. In addition, the impurity concentration of the plug portion  13   dn  and the impurity concentration of the plug portion  13   sn  may be different from each other. The plug portions  12   dn  and  12   sn  are simultaneously formed in the same process to have the same impurity concentration. In addition, the plug portions  13   dn  and  13   sn  are simultaneously formed in the same process to have the same impurity concentration. 
     The gate  20 G is connected to a wiring layer (a wiring plug)  11   g.  The wiring layers  11   s ,  11   d,  and  11   g  are formed using a material having a resistance value lower than a predetermined value. The wiring layers  11   s ,  11   d , and  11   g,  for example, are metal wiring layers. Further, the wiring layers  11   s ,  11   d , and  11   g  may be made of polysilicon having an even impurity concentration. 
     In the transistor  10 HA, the gate  20 G is connected to the first wiring layer through the wiring layer  11   g.  In addition, in the transistor  10 HA, the drain  20 D (the n-type diffusion layer  1 Dn) is connected to the second wiring layer through the wiring layer  11   d.    
     Next, the resistance value of the drain  20 D of the transistor  10 HA will be described.  FIG. 2  is a diagram for describing the resistance value of the drain of the transistor according to the first embodiment.  FIG. 2  illustrates a cross-sectional configuration of the transistor circuit which includes the transistor  10 HA. 
     The transistor circuit includes the transistors  10 HA and  10 L. The transistor  10 L is an nMOS transistor having a low breakdown voltage (LV nMOS) compared to the transistor  10 HA. The thickness of a gate oxide film of the transistor  10 HA is thicker than that of the transistor  10 L. 
     The transistor  10 L includes a source  35 S, a gate  35 G, a drain  35 D, and a substrate connecting portion  1 Y. The source  35 S includes an n-type diffusion layer  2 Sn, and the drain  35 D includes an n-type diffusion layer  2 Dn. In the transistor  10 L, the gate  35 G is formed between the source  35 S and the drain  35 D. The n-type diffusion layers  2 Sn and  2 Dn is formed by the first n −  layer similarly to the n-type diffusion layers  1 Sn and  1 Dn. 
     An n-type diffusion layer  22   sn  having an impurity concentration higher than a predetermined value is formed on the upper layer side of the n-type diffusion layer  2 Sn. The n-type diffusion layer  22   sn  is formed by a second n +  layer (the polysilicon layer) having an impurity concentration higher than a predetermined value. The second n +  layer is a layer having an impurity concentration higher than that of the first n −  layer. A wiring plug  21   s  is provided on the upper layer side of the n-type diffusion layer  22   sn.    
     An n-type diffusion layer  22   dn  having an impurity concentration higher than a predetermined value is formed on the upper layer side of the n-type diffusion layer  2 Dn. The n-type diffusion layer  22   dn  is formed by the second n +  layer. A wiring plug  21   d  is provided on the upper layer side of the n-type diffusion layer  22   dn.    
     The gate  35 G is connected to a wiring layer  21   g . The wiring layer  21   g  is a metal wiring layer similarly to the wiring layer  11   g.  The wiring plugs  21   s  and  21   d  and the wiring layer  21   g,  for example, are formed simultaneously with the wiring layers  11   s,    11   d,  and  11   g  in the same process as that of the wiring layers  11   s ,  11   d,  and  11   g . Further, the wiring plugs  21   s  and  21   d  and the wiring layer  21   g  may be made of polysilicon having an even impurity concentration. 
     A substrate connecting portion (a well connecting portion in a case where a well is configured)  1 X includes a p-type diffusion layer  12   xp  and a wiring plug  11   x.  The substrate connecting portion  1 X is connected to the substrate (or the well) through the p-type diffusion layer  12   xp . In addition, the substrate connecting portion (a well connecting portion in a case where a well is configured)  1 Y includes a p-type diffusion layer  12   yp  and a wiring plug  11   y . The substrate connecting portion  1 Y is connected to the substrate (or the well) through the p-type diffusion layer  12   yp . The p-type diffusion layers  12   xp  and  12   yp  are formed a first p +  layer (a silicon layer) having an impurity concentration higher than a predetermined value. 
     The wiring plug  11   x  is provided on the upper layer side of the p-type diffusion layer  12   xp . The wiring plug  11   y  is provided on the upper layer side of the p-type diffusion layer  12   yp . The wiring plugs  11   x  and fly, for example, are formed simultaneously with the wiring layers  11   s,    11   d,  and  11   g  in the same process as that of the wiring layers  11   s,    11   d,  and  11   g.    
     Resistance caused by the n-type diffusion layer  1 Dn and resistance caused by the plug portions  12   dn  and  13   dn  are generated between the wiring layer  11   d  and the gate  20 G of the transistor  10 HA. Therefore, in the transistor  10 HA, since having the plug portion  13   dn  a large resistance value is connected to the drain  20 D, a large resistance value appears in the drain  20 D. With this configuration, the breakdown voltage of the drain  20 D is improved. 
       FIG. 3  is a diagram for describing the resistance value of the drain in a case where the plug portion connected to the drain is made of metal.  FIG. 3  illustrates the cross-sectional configuration of the transistor circuit. In the transistor circuit illustrated in  FIG. 3 , the transistor  10 L (including the ground connecting portion  1 Y) and the ground connecting portion  1 X of a transistor  10 HX have the same configuration as that of the CMOS transistor illustrated in  FIG. 2 . The transistor circuit herein includes the transistors  10 HX and  10 L. 
     The transistor  10 HX includes a source  70 S, a gate  70 G, a drain  70 D, and the substrate connecting portion  1 X. The source  70 S includes an n-type diffusion layer  7 Sn, and the drain  70 D includes an n-type diffusion layer  7 Dn. In the transistor  10 HX, the gate  70 G is formed between the source  70 S and the drain  70 D. The n-type diffusion layers  7 Sn and  7 Dn, for example, are formed by the first n −  layer similarly to the n-type diffusion layers  2 Sn and  2 Dn. 
     An n-type diffusion layer  72   sn  having an impurity concentration higher than a predetermined value is formed on the upper layer side of the n-type diffusion layer  7 Sn. The n-type diffusion layer  72   sn  is formed by the second n +  layer (a silicon layer) similarly to the n-type diffusion layer  22   sn . A wiring plug  71   s  is provided on the upper layer side of the n-type diffusion layer  72   sn.    
     An n-type diffusion layer  72   dn  having an impurity concentration higher than a predetermined value is formed on the upper layer side of the n-type diffusion layer  7 Dn. The n-type diffusion layer  72   dn  is formed by the second n +  layer similarly to the n-type diffusion layer  72   sn . A wiring plug  71   d  is provided on the upper layer side of the n-type diffusion layer  72   dn.    
     The gate  70 G is connected to a wiring layer  71   g . The wiring layer  71   g  is a metal wiring layer similarly to the wiring layer  11   g.  The wiring plugs  71   s  and  71   d  and the wiring layer  71   g,  for example, are formed simultaneously with the wiring plugs  21   s  and  21   d  and the wiring layer  21   g  in the same process as that of the wiring plugs  21   s  and  21   d  and the wiring layer  21   g.  Further, the wiring plugs  71   s  and  71   d  and the wiring layer  71   g  may be made of polysilicon having an even impurity concentration. 
     The transistor  10 HX is configured to have the wiring plug  71   d  of a low resistance, so that the breakdown voltage of the drain  70 D becomes lower. In other words, the breakdown voltage of the drain  70 D becomes lower than that of the drain  20 D. 
       FIG. 4  is a diagram for describing the breakdown voltage of the drain in a case where the resistance of the wiring plug is low. The breakdown voltage of the drain  70 D depends on a sheet resistance (a region except the n-type diffusion layer  72   dn ) of the n-type diffusion layer  7 Dn. For example, in a case where the impurity concentration of the n-type diffusion layer  7 Dn is lower than a predetermined value, the breakdown voltage depends on an electric field focusing on a boundary surface (bottom)  91  of the n-type diffusion layer  72   dn . Therefore, in a case where the impurity concentration of the n-type diffusion layer  7 Dn is lower than the predetermined value, the breakdown voltage of the drain  70 D depends on the impurity concentration of the n-type diffusion layer  72   dn . The breakdown voltage of the drain  70 D in this case is improved by alleviating the electric field under the n-type diffusion layer  72   dn.    
     On the other hand, in a case where the impurity concentration of the n-type diffusion layer  7 Dn is higher than the predetermined value, the electric field is focused on the boundary surface (the end of the gate)  92  between the n-type diffusion layer  7 Dn and the gate  70 G. Therefore, in a case where the impurity concentration of the n-type diffusion layer  7 Dn is higher than the predetermined value, the breakdown voltage of the drain  70 D depends on the impurity concentration of the n-type diffusion layer  7 Dn. The breakdown voltage of the drain  70 D in this case is improved by alleviating the electric field between the gate  70 G and the n-type diffusion layer  7 Dn. 
       FIG. 5  is a diagram illustrating a relation between a sheet resistance of the n-type diffusion layer and the breakdown voltage of the drain. The horizontal axis of  FIG. 5  represents the sheet resistance of the n-type diffusion layer  7 Dn (the first n −  layer), and the vertical axis represents the breakdown voltage of the drain  70 D. 
     In a case where the impurity concentration of the n-type diffusion layer  7 Dn is lower than the predetermined value, the sheet resistance of the n-type diffusion layer  7 Dn and the breakdown voltage of the drain  70 D show a relation denoted by the characteristic  101 . In addition, in a case where the impurity concentration of the n-type diffusion layer  7 Dn is higher than the predetermined value, the sheet resistance of the n-type diffusion layer  7 Dn and the breakdown voltage of the drain  70 D show a relation denoted by the characteristic  102 . Therefore, in general, “n-Rs” is set such that the breakdown voltage is maximized in the boundary between the characteristic  102  and the characteristic  101 . 
     As one of the methods of improving the breakdown voltage of the drain  70 D, there is a method of lengthening a length between the gate  70 G and the n-type diffusion layer  72   dn  (the wiring plug  71   d ). In this method, the length of the n-type diffusion layer  7 Dn disposed from the distance of the gate  70 G to the n-type diffusion layer  72   dn  becomes lengthy. As a result, the area of the n-type diffusion layer  7 Dn becomes larger. 
       FIG. 6  is a diagram illustrating an exemplary configuration of a transistor of which the length between the gate and the second n +  layer is set to be lengthy.  FIG. 6  illustrates a cross-sectional configuration of a transistor  10 HY in a case where the length between the gate  70 G and the n-type diffusion layer  72   dn  is set to be lengthy. 
     In a case where the length between the gate  70 G and the n-type diffusion layer  72   dn  is set to be lengthy, an n-type diffusion layer  7 Dn′ is used instead of the n-type diffusion layer  7 Dn. The n-type diffusion layer  7 Dn′ is a diffusion layer which is formed to have a length between the gate  70 G and the n-type diffusion layer  72   dn  longer than that of the n-type diffusion layer  7 Dn. With this configuration, it is possible to make the resistance large between the n-type diffusion layer  72   dn  and the gate  70 G, and the breakdown voltage of the area of the characteristic  102  of  FIG. 5  can be increased. Therefore, it is possible to increase a maximum breakdown voltage determined at an intersection between the characteristic  102  and the characteristic  101 . 
     However, in the case of the transistor  10 HY illustrated in  FIG. 6 , the area of the transistor  10 HY becomes larger. Herein, in this embodiment, as illustrated in  FIG. 1 , the plug portion  12   sn  of the drain  20 D is formed by the first n +  layer, and the plug portion  13   sn  is formed by the second n layer. With this configuration, the transistor  10 HA can be formed in a small area and make the resistance large in a portion between the plug portion  12   dn  and the gate  20 G, and the breakdown voltage of the characteristic  102  can be increased. In addition, since the plug portion  12   dn  of a high impurity layer is separated from a pn junction place between the diffusion layer and the substrate, the electric field of the pn junction is weakened and the breakdown voltage of the characteristic  101  is also improved. With both effects described above, a maximum breakdown voltage of the drain  20 D becomes larger than that of the transistor  10 HY. 
     In other words, a procedure of forming a transistor device having the transistor  10 HA will be described.  FIG. 7  is a flowchart illustrating a procedure of forming the transistor according to the first embodiment. In this embodiment, a first contact hole group is formed in the transistor, and then a second contact hole group is formed. 
     Among the contact holes connected to the transistor, the contact holes of the source  20 S and the drain  20 D of the transistor  10 HA are the first contact hole group. In addition, among the contact holes connected to the transistor, the contact holes other than the first contact hole group are the second contact hole group. Therefore, the second contact hole group are the contact holes of the gate  20 G, the transistor  10 L, and the substrate connecting portions  1 X and  1 Y of the transistor  10 HA. 
     On the substrate of the well, the gate (the gate  20 G), a drain diffusion layer, a source diffusion layer, a diffusion layer for the connection of the substrate of the transistor (the transistors  10 HA and  10 L) are formed (Step S 10 ). 
     Thereafter, an inter-layer film is formed on the layers (Step S 20 ). Thereafter, the first contact hole group is formed on the upper portion side of the source diffusion layer  20 S and the drain diffusion layer  20 D of the transistor  10 HA (an HV nMOS). At this time, a lithography process or an imprint process is performed, and thus the first contact hole group using a resist pattern is formed. Then, RIE (Reactive Ion Etching) or the like is performed on the resist pattern to form the first contact hole group in the inter-layer film (Step S 30 ). 
     Furthermore, polysilicon is deposited in the first contact hole group (Step S 40 ). The polysilicon contains n-type impurities such as As and P. Therefore, the plug portions  12   sn ,  12   sn ,  12   dn , and  13   dn  are formed on the transistor  10 HA. Thereafter, planarization is performed (Step S 50 ). 
     Furthermore, other contact holes (the second contact hole group) except the HV nMOS are formed. At this time, the lithography process or the imprint process is performed, and thus the second contact hole group using the resist pattern is formed. Then, the RIE is formed on the resist pattern, so that the second contact hole group is formed in the inter-layer film (Step S 60 ). Furthermore, metal wirings are buried in the second contact hole group (Step S 70 ). Therefore, the wiring layers  11   g  and  21   g  and the wiring plugs  21   s,    21   d,    11   x , and  11   y  are formed. Thereafter, the planarization is performed (Step S 80 ). 
     Further, regarding the contact holes connected to the CMOS transistor, the second contact hole group is first formed and then the first contact hole group may be formed. In this case, after the second contact hole group is formed, the metal wiring is buried in the second contact hole group. Thereafter, the first contact hole group is formed, and the polysilicon is deposited in the first contact hole group. 
     In addition, the plug portions  12   sn  and  12   sn  of the source  20 S may be included in the second contact hole group. In this case, the first contact hole group becomes the plug portions  12   dn  and  13   dn.    
     When the semiconductor device (a semiconductor integrated circuit) is manufactured, the transistor device having the transistor  10 HA, the plug portions  12   sn ,  12   sn ,  12   dn , and  13   dn , the wiring layers  11   g  and  21   g,  and the wiring plugs  21   s,    21   d,    11   x , and  11   y  are formed through the procedure described in  FIG. 7 . 
     Thereafter, a film forming process, an exposure process, a develop process, and an etching process are performed on each layer of a wafer process. Specifically, the substrate deposited with the resist pattern is exposed to light using a mask, and then the substrate is developed to form the resist pattern on the substrate. Then, the lower layer of the resist pattern is etched using the resist pattern as the mask. Therefore, an actual pattern corresponding to the resist pattern is formed on the substrate. When the semiconductor device is manufactured, the film forming process, the exposure process, the develop process, and the etching process described above are repeatedly performed on each layer. 
     Next, the impurity concentration such as the plug portions  12   sn  and  12   sn  will be described. The impurity concentration of the plug portions  12   sn  and  13   dn , for example, is less than 1×10 19 /cm 3 . In addition, the impurity concentration of the n-type diffusion layers  1 Sn and  1 Dn, for example, is less than 1×10 19 /cm 3 . In addition, the impurity concentration of the plug portions  12   sn  and  12   dn , for example, is equal to or more than 1×10 19 /cm 3 . In other words, the impurity concentrations of the first n −  layer and the second n −  layer, for example, are less than 1×10 19 /cm 3 . In addition, the impurity concentration of the first n +  layer, for example, is equal to or more than 1×10 19 /cm 3 . Further, the boundary of the impurity concentration of the first and second n layers and the impurity concentration of the first n +  layer may be arbitrarily set within a range of 1×10 17  to 1×10 21 /cm 3 . 
     Further, in a case where the transistor  10 HA is a pMOS transistor, the plug formed on the upper portion side of the source or the drain is formed by a polysilicon layer having a resistance value higher than a predetermined value. The polysilicon contains p-type impurities such as B. In this case, the impurity concentration of the lower layer of the plug formed on the upper portion side of the source or the drain, for example, is less than a first value. For example, the impurity concentration of the lower layer of the plug formed on the upper portion side of the source is equal to the impurity concentration of the p-type diffusion layer which forms the source. In addition, the impurity concentration of the upper portion side of the plug on the upper portion side of the source, for example, equal to or more than the first value. 
     In this way, according to the first embodiment, the transistor circuit includes the transistor  10 HA and the transistor  10 L. Then, the transistor  10 L is connected to the first wiring through the wiring plug made of a material having the first resistance value smaller than a predetermined value. In addition, the drain  20 D of the transistor  10 HA is connected to the second wiring through the polysilicon plug made of a material having the second resistance value larger than the first resistance value. 
     With this configuration, in the drain  20 D, the resistance in a portion between the high impurity layer and the gate  20 G can be made large and the electric field of the pn junction between the diffusion layer and the substrate can be weakened. As a result, a high breakdown voltage transistor can be effectively formed while suppressing the increase of the circuit area. 
     Second Embodiment 
     Next, a second embodiment will be described using  FIG. 8 . In the second embodiment, a concentration gradient is given to the plug portions  12   dn  and  13   dn . Specifically, the polysilicon plug on the drain is formed such that the impurity concentration becomes lower as it goes from the wiring layer  11   d  toward the drain  20 D. 
       FIG. 8  is a diagram illustrating an exemplary configuration of a transistor according to the second embodiment. Among the respective components of  FIG. 8 , the components achieving the same functions as those of the transistor  10 HA of the first embodiment illustrated in  FIG. 1  will be denoted with the same symbols, and the redundant description will not be repeated. 
     A transistor  10 HB includes a plug portion  14   dn  instead of the plug portions  12   dn  and  13   dn  of the transistor  10 HA. The upper portion side (the side near the wiring layer  11   d ) of the plug portion  14   dn  is formed to have an impurity concentration higher than that on the lower portion side (the side near the n-type diffusion layer  1 Dn). Then, the plug portion  14   dn  is formed to have a lower impurity concentration as it goes from the upper portion side toward the lower portion side. 
     The plug portion  14   dn , for example, is formed to have a higher carbon concentration as it goes from the upper portion side to the lower portion side. Therefore, in the plug portion  14   dn , the concentration gradient is formed from the upper portion side toward the lower portion side. As a result, the plug portion  14   dn  comes into ohmic contact with the wiring layer  11   d,  and the resistance value of the plug portion  14   dn  becomes lower than a predetermined value. 
     In addition, the transistor  10 HB includes a plug portion  14   sn instead of the plug portions  12   sn  and  12   sn  of the transistor  10 HA. The upper portion side (the side near the wiring layer  11   s ) of the plug portion  14   sn  is formed to have an impurity concentration higher than that on the lower portion side (the side near the n-type diffusion layer  1 Sn). Then, the plug portion  14   sn is formed to have a lower impurity concentration as it goes from the upper portion side toward the lower portion side. 
     The plug portion  14   sn , for example, is formed to have a higher carbon concentration as it goes from the upper portion side to the lower portion side. Therefore, in the plug portion  14   sn , the concentration gradient is formed from the upper portion side toward the lower portion side. As a result, the plug portion  14   sn  comes into ohmic contact with the wiring layer  11   s , and the resistance value of the plug portion  14   sn  becomes lower than a predetermined value. 
     Further, the CMOS transistor of this embodiment has the same configuration as that of the CMOS transistor of the first embodiment in the places other than the transistor  10 HB. 
     In this way, in the second embodiment, the plug portion  14   dn  is formed to have a lower impurity concentration as it goes from the wiring layer  11   d  toward the drain  20 D. With this configuration, in the drain  20 D, the resistance in a portion between the high impurity layer and the gate  20 G can be made large and the electric field of the pn junction between the diffusion layer and the substrate can be weakened. As a result, a high breakdown voltage transistor can be effectively formed while suppressing the increase of the circuit area. 
     Third Embodiment 
     Next, a third embodiment will be described using  FIG. 9 . In the third embodiment, a concentration gradient is formed between the plug portions  12   dn  and  13   dn . Therefore, the impurities of the plug portion  12   dn  are prevented from being diffused into the plug portion  13   dn , and the impurities of the plug portion  13   dn  are prevented from being diffused into the plug portion  12   dn.    
       FIG. 9  is a diagram illustrating an exemplary configuration of a transistor according to the third embodiment. Among the respective components of  FIG. 9 , the components achieving the same functions as those of the transistor  10 HA of the first embodiment illustrated in  FIG. 1  will be denoted with the same symbols, and the redundant description will not be repeated. 
     A transistor  10 HC includes the plug portions  12   dn ,  13   dn,  and  15   dn  instead of the plug portions  12   dn  and  13   dn  of the transistor  10 HA. The plug portion  15   dn  is disposed between the plug portions  12   dn  and  13   dn.    
     Therefore, the plug portion  13   dn  is formed on the upper portion side of the n-type diffusion layer  1 Dn, and the plug portion  15   dn  is formed on the upper portion side of the plug portion  13   dn . Then, the plug portion  12   dn  is formed on the upper portion side of the plug portion  15   dn . Therefore, the plug portion  12   dn  comes into ohmic contact with the wiring layer  11   d , and the resistance values of the plug portions  13   dn  and  15   dn  become higher than a predetermined value. 
     In addition, the transistor  10 HC includes the plug portions  12   sn ,  12   sn , and  15   sn  instead of the plug portions  12   sn  and  12   sn  of the transistor  10 HA. The plug portion  15   sn  is disposed between the plug portions  12   sn  and  12   sn.    
     Therefore, the plug portion  12   sn  is formed on the upper layer side of the n-type diffusion layer  1 Sn, and the plug portion  12   sn  is formed in the upper portion side of the plug portion  15   sn . Then, the plug portion  12   sn  is formed on the upper portion side of the plug portion  15   sn . Therefore, the plug portion  12   sn  comes into ohmic contact with the wiring layer  11   s , and the resistance values of the plug portions  12   sn  and  15   sn  become higher than a predetermined value. 
     Further, the CMOS transistor of this embodiment has the same configuration as that of the CMOS transistor of the first embodiment in the places other than the transistor  10 HC. 
     In this way, in the third embodiment, the plug portion  15   dn  formed of an oxide film is formed between the plug portions  12   dn  and  13   dn . With this configuration, in the drain  20 D, the resistance in a portion between the high impurity layer and the gate  20 G can be made large and the electric field of the pn junction between the diffusion layer and the substrate can be weakened. As a result, a high breakdown voltage transistor can be effectively formed while suppressing the increase of the circuit area. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.