Patent Publication Number: US-8120431-B2

Title: Variable loop bandwidth phase locked loop

Description:
This is a continuation of U.S. Ser. No. 11/260,442, filed Oct. 27, 2005 now U.S. Pat. No. 7,589,594, which is incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to phase locked loops generally and, more particularly, to a method and/or apparatus for implementing a variable loop bandwidth phase locked loop. 
     BACKGROUND OF THE INVENTION 
     Conventional phase locked loops (PLLs) are widely used in frequency synthesis, clock and data recovery, and other communications circuits. Conventional PLLs need to vary the loop bandwidth within the PLL. For example, an input clock is often noisy. If a clean clock is needed at the output of the PLL, a narrow bandwidth filter can be implemented to filter out the input noise. A different situation arises when the lock time is important. In such cases, a wide bandwidth PLL is needed to achieve fast locking. In some systems, a PLL is needed to switch between a narrow bandwidth mode and a wide bandwidth mode. 
     Referring to  FIG. 1 , a diagram of a system  10  is shown illustrating a conventional PLL. The system includes a charge pump  12 , a phase frequency detector  14  and a loop filter  16 . The charge pump  12  receives signals from the phase frequency detector  14 . The loop filter  16  is shown implemented as a second order loop filter that converts the charge pump current ICP into a control voltage. The loop bandwidth of the PLL may be approximated by the following equation: 
                     ϖ   u     =         ICPR   z     ⁢     K   vco         2   ⁢           ⁢   π   ⁢           ⁢   N               EQ   .           ⁢     (   1   )                 
where ICP is the charge pump current, R z  is the loop filter resistor, K VCO  is the VCO gain, and N is the feedback frequency divider ratio. A stabilizing zero is formed by the resistor R z  and the capacitor C z , with the frequency defined as  ω   z =1/(R Z C Z ). The loop filter  16  has two poles, a first pole at w=0 and a second pole at  ω   p =1/(R z C 1 ).
 
     To maintain stability, the loop may be designed to have a damping factor close to 1. The damping factor is given by the following equation: 
                   ξ   =           ICPK   vco       2   ⁢           ⁢   π   ⁢           ⁢     N   ⁡     (       C   1     +     C   z       )             ⁢     (       1   2     ⁢     R   z     ⁢     C   z       )               EQ   .           ⁢     (   2   )                 
The second pole  ω   p  is chosen 3-10 times higher than  ω   u . In a scheme aimed at varying the loop bandwidth  ω   u , a guarantee that stability is not sacrificed is important.
 
     It would be desirable to implement a variable loop bandwidth phase locked loop circuit that may accommodate a variety of applications. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a voltage controlled oscillator, a first charge pump, a second charge pump, a switch circuit and a comparator circuit. The voltage controlled oscillator may be configured to generate an output signal oscillating at a first frequency in response to a control signal. The charge pump circuit may be configured to generate a first component of the control signal in response to a first adjustment signal and a second adjustment signal. The second charge pump may be configured to generate a second component of the control signal in response to a first intermediate signal and a second intermediate signal. The switch circuit may be configured to generate the first intermediate signal and the second intermediate signal in response to the first adjustment signal and the second adjustment signal. The comparator circuit may be configured to generate the first and second adjustment signals in response to a comparison between (i) an input signal having a second frequency and (ii) the output signal. 
     The objects, features and advantages of the present invention include providing a phase locked loop that may (i) provide a variable loop bandwidth, (ii) increase or decrease the bandwidth while maintaining stability, and/or (iii) be easy to implement while providing loop stability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a diagram illustrating a conventional PLL; 
         FIG. 2  is a block diagram illustrating an embodiment of the present invention; 
         FIG. 3  is a detailed diagram illustrating an embodiment of the present invention; 
         FIG. 4  is a diagram illustrating a simulated bandwidth and phase margin versus alpha; and 
         FIG. 5  is a diagram illustrating an alternate implementation of the switch array. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to  FIG. 2 , a block diagram of a system  100  in accordance with a preferred embodiment of the present invention is shown. The system  100  may be implemented as a variable loop bandwidth phase locked loop. The system  100  generally comprises a block (or circuit)  102 , a block (or circuit)  104 , a block (or circuit)  106 , a block (or circuit)  108 , a block (or circuit)  110  and a block (or circuit)  112 . The circuit  102  may be implemented as a switching array. The circuit  104  may be implemented as a charge pump circuit. The circuit  106  may be implemented as a voltage controlled oscillator. The circuit  108  may be implemented as a control circuit. The circuit  110  may be implemented as a feedback divider. The circuit  112  may be implemented as a phase frequency detector (or comparator circuit). The switch array  102  may receive a signal (e.g., UP) and a signal (e.g., DN) that may be generated by the phase frequency detector  112 . The charge pump  104  may also receive the signal UP and the signal DN. The switch array  102  generally presents a signal (e.g., A) and a signal (e.g., B) to the circuit  108 . The signal UP and the signal DN may be adjustment signals. 
     Various combinations of the signal UP and the signal DN may be presented to the switch array  102 . In the example shown, the switch array  102  receives two versions of the signal DN and two versions of the signal UP, shown in a generally sequential order presented to the switch array  102  (e.g., DN, DN, UP, UP). However, other orders may be implemented to meet the design criteria of a particular implementation. Additionally, more than two versions of the signal DN and the signal UP may be implemented in certain design applications. 
     The charge pump circuit  104  may present a first component of a signal (e.g., CTR) to the voltage controlled oscillator  106 . The signal CTR may be a control signal configured to control a frequency of oscillation of a signal (e.g., OUT) presented by the voltage control oscillator  106 . The control circuit  108  may present a second component of the control signal CTR. For example, the charge pump  104  and the control circuit  108  each contribute to the signal CTR. The charge pump  104  and the control circuit  108  both contribute to the frequency of oscillation of the signal OUT by contributing to the signal CTR. The feedback divider  110  may be used to divide the frequency of the signal OUT before being presented to the phase frequency detector  112 . The divided version of the signal OUT is shown as a signal (e.g., FEEDBACK_CLOCK) presented to the phase frequency detector  112 . The particular amount of division provided by the circuit  112  may be varied to meet the design criteria of a particular implementation. In certain implementations, a divide by one may be implemented, which leaves the frequency of the signal FEEDBACK_CLOCK unchanged from the frequency of the signal OUT. In other implementations, various divide factors may be implemented. 
     The control circuit  108  generally comprises a block (or circuit)  130 , a block (or circuit)  132 , and a block (or circuit)  134 . The circuit  130  may be implemented as a charge pump. The circuit  132  may be implemented as a stabilizer circuit. The circuit  134  may be implemented as a capacitor switch array. The charge pump  130  is shown contributing to the signal CTR through the stabilizer circuit  132 . However, in certain implementations, the charge pump  130  may directly contribute to the signal CTR (e.g., through a connection that does not pass through the stabilizer circuit  132 ). In such an implementation, the stabilizer circuit  132  may need to be connected to the charge pump  104 . 
     Referring to  FIG. 3 , a more detailed block diagram of a system  100  is shown. In general, the system  100  may be used to vary the loop bandwidth of the system  100  while maintaining loop stability. The bandwidth of the system  100  may be varied in response to one or more control signals (e.g., L and H). The signal L may be used to lower the loop bandwidth. For example, if the signal L is high (or true) the bandwidth of the system  100  may be reduced. Similarly, if the signal H is high (or true) the bandwidth of the system  100  may be increased. The control signals L and H may be used to control the charge pump  130 . In general, the charge pump  130  either adds or subtracts from the effect of the charge pump  104 , in response to the control signals L and H. 
     The switch array  102  generally comprises a switch  154 , a switch  156 , a switch  158 , and a switch  160 . The particular number of switches in the switch array  102  may be varied to meet the design criteria of a particular implementation. The charge pump circuit  104  generally comprises a current source  162 , a switch  164 , a switch  166  and a current source  168 . A connection between the switch  164  and the switch  166  may be connected to the voltage controlled oscillator  114 . The charge pump  104  uses a current ICP 1   a  and a current ICP 1   b  to generate a portion of the signal CTR. In general, the current ICP 1   a  and the current ICP 1   b  are equal. However, due to process and/or design variations, the current ICP 1   a  and the current ICP 1   b  may not always be equal. 
     The charge pump circuit  130  generally comprises a current source  170 , a switch  172 , a switch  174 , and a current source  176 . The stabilizer circuit  132  generally comprises a resistor RZ and a capacitor CZ. The capacitor switch array  134  generally comprises a number of capacitors C 0 -Cn and a number of switches D 0 -Dn. The particular number of capacitors Ca-Cn and the particular number of switches D 0 -Dn may be varied to meet the design criteria of a particular implementation. In general, each of the capacitors C 0 -Cn has a similar capacitance. However, due to process variations, the particular capacitances of the capacitors C 0 -Cn may vary. 
     In general, the switches  154  and  160  receive the signal L. The switches  156  and  158  may receive the signal H. In one example, the control signals L and H may be generated internally within the system  100 . In another example, the control signals L and H may be generated externally to the system  100 . In one example, the control signals L and H may be generated by a circuit. In another example, the control signals L and H may be received as user inputs. In general, the switches  154 - 160  may be turned on or off to control the bandwidth of the system  100 . The current source  162  may generate the current ICP 1   a  in response to activating the switch  164 . The switch  164  may be activated when the signal L presented to the switch  150  is high (or true). The current source  168  may generate the current ICP 1   b  in response to activating the switch  166 . The switch  166  may be activated when the signal L presented to the switch  152  is high (or true). The following table illustrates examples of the various signals: 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Signal 
                 H = high, L = low 
                 H = low, L = high 
               
               
                   
               
             
            
               
                 A 
                 Up 
                 Dn 
               
               
                 B 
                 Dn 
                 Up 
               
               
                   
               
            
           
         
       
     
     The current source  170  and the current source  176  may generate the second component of the control signal CTR. The current source  170  may generate the signal ICP 2   a  in response to activating the switch  172 . The switch  172  may be activated when the (i) signal L presented to the switch  154  is low or (ii) the signal H presented to the switch  158  is high. The current source  176  may generate the current ICP 2   b  in response to activating the switch  174 . The switch  174  may be activated when the (i) signal H presented to the switch  156  is low or (ii) signal L presented to the switch  160  is high. In general, the current ICP 2   a  and the current ICP 2   b  are equal. However, due to process and/or design variations, the current ICP 2   a  and the current ICP 2   b  may not always be equal. 
     The system  100  may adjust the bandwidth while maintaining a generally consistent damping factor. The currents ICP 1   a , ICP 1   b , ICP 2   a  and ICP 2   b  control the damping factor. The signals UP and DN presented to the charge pump  104  and the switch array  102  may be implemented (i) in opposite polarities (e.g., UP/DN versus DN/UP) or (ii) with the same polarity (e.g., UP/DN versus UP/DN). The reversal of the second charge pump  130  (which reduces the loop bandwidth) is normally controlled by the control signals H and L for the switch  154 , the switch  156 , the switch  158  and the switch  160 . The signals UP and DN presented to the charge pump circuit  104  and the switch array circuit  102  may have similar polarities. The loop bandwidth may be shown by the following equation: 
                       ω   _     u   ′     =           I   t     ⁢     R   z     ⁢     K   vco         2   ⁢           ⁢   π   ⁢           ⁢   N       =     α   ⁢           ⁢       ω   _     u                 EQ   .           ⁢     (   3   )                 
The current I t  may be shown by the following equation:
 
 I   t   =I CP1 ±I CP2  EQ. (4)
 
The zero formed by the stabilizer circuit  132  may be defined as  ω   z ′=  ω   z α. The parameter α may be determined by the ratio of the signal ICP 2  and the signal ICP 1 . The parameter α may be given by the following equation:
 
α=1 ±I CP2 /I CP1  EQ. (5)
 
     The sign in EQ. 4 and EQ. 5 may be determined as follows: 
     (i) if the signal L is set to low and the signal H is set to high, then α=1+ICP 2 /ICP 1  and I t =ICP 1 +ICP 2 ; or 
     (ii) if the signal L is set to high, then α=1−ICP 2 /ICP 1  and I t =ICP 1 −ICP 2 . 
     The damping factor may be shown by the following equation: 
                     ξ   ′     =     ξ   ⁢         I   t       I     t   ⁢           ⁢   0           ⁢     1   α               EQ   .           ⁢     (   6   )                 
where I t0  may be the initial value of the current I t .
 
     The bandwidth may be varied by changing the current I t . For example, if I t0 =ICP 1  or α=1, and a decrease in the bandwidth is needed, the signal H may be set to low and the signal L may be set to high. The bandwidth of the system  100  may be decreased when the difference between the current ICP 1  and the current ICP 2  (e.g., I t ), is decreased. If an increase to the bandwidth is needed, the signal H may be set to high and the signal L may be set to low. The bandwidth may be increased when the sum (I t ) of the current ICP 1  and the current ICP 2  is increased. 
     Stability in the system  100  may be maintained provided the current ICP 1  and the current ICP 2  meet the following conditions: 
                   α   =       I   t       ICP   ⁢           ⁢   1               EQ   .           ⁢     (   7   )                 
Following EQ. (6), to maintain a constant damping factor
 
                     α   2     =       I   t       I     t   ⁢           ⁢   0                 EQ   .           ⁢     (   8   )                 
By solving for the current ICP 1  and the current ICP 2  from EQS. (7) and (8), the following equations may be produced:
 
 I CP1 =αI   t0  
 
 I CP2=±(α−α 2 ) I   t0   EQ. (9)
 
Given I t0  and α (e.g., the bandwidth multiplying factor), the signal ICP 1  and the signal ICP 2  may be uniquely determined from EQ. (9).
 
     The +/− notation in EQ. (9) indicates two conditions. A first condition (e.g., the +condition) occurs when the signal L is high (or true). A second condition (e.g., the − condition) occurs when the signal H is high (or true). 
     The pole formed by the system  100  may be defined by the following equation: 
                             ω   _     p   ′     =     1   /     (     RC   eq     )                     C   eq     =       C   0     ⁢       ∑       i   =   1     ,   N       ⁢     D   i                       EQ   .           ⁢     (   10   )                 
C eq  may be an effective capacitance and equal to αC 1  by selecting the capacitor C 0  and activating the number of switches D 0 -Dn. By selecting one or more of the capacitors C 0 -Cn by selecting the corresponding switches D 0 -Dn, the system  100  ensures that a second pole does not impact the phase margin when the bandwidth is varied. In general, since each of the capacitors C 0 -Cn are similar, the above equation is valid for the particular capacitance selected.
 
     Referring to  FIG. 4 , a diagram illustrating a simulated bandwidth and phase margin versus alpha is shown. In  FIG. 4  the simulated loop bandwidth of the PLL is plotted versus α. While the bandwidth is varied by an order of magnitude, the phase margin is almost flat which indicates that the stability of the system  100  is maintained. 
     The system  100  may also function when the loop bandwidth is needed to remain constant while the feedback divider ratio generated from the feedback divider  110  is varied. In such a case, one can choose α=N′/N, where N′ may be defined as the varied divider ratio. The currents ICP 1  and ICP 2  may be determined by EQ. (9). In one example, the switches D 0 -Dn may be omitted and a single capacitor C 1  may be implemented if the desired bandwidth change is small (e.g., around two times) to ensure that  ω   p  is adequately separated from  ω   u ′. 
     Referring to  FIG. 5 , an alternate implementation of the switch array is shown implemented as a switch array  102 ′. The switch array  102 ′ generally comprises a multiplexer  150  and a multiplexer  152 . In one example, the multiplexer  150  and the multiplexer  152  may be implemented as 2:1 multiplexers. The multiplexer  150  is shown having an input (e.g., D 0 ) that may receive the signal DN and an input (e.g., D 1 ) that may receive the signal UP. A select input (e.g., S) may receive the signal H. The multiplexer  150  may have an output (e.g., O) that may present the signal A in response to the signal DN, the signal UP and the signal H. The multiplexer  152  may have a similar implementation. For example, the multiplexer  152  may have an input D 0  that may receive the signal UP, an input D 1  that may receive the signal DN, an input S that may receive the signal H and an output O that may present the signal B. In the example shown, the input D 0  of the multiplexer  150  may receive the signal DN, while the input D 0  of the multiplexer  152  may receive the signal UP. Similarly, the input D 1  of the multiplexer  150  may receive the signal UP, while the input D 1  of the multiplexer  152  may receive the signal DN. By alternating the D 0  and D 1  inputs between the multiplexer  150  and the multiplexer  152 , a single signal H may be used to generate the signals A and B. While specific examples of the switch array  102  and the switch array  102 ′ have been shown, other examples may be implemented to meet the design criteria of a particular implementation. 
     The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.