Patent Publication Number: US-6667843-B2

Title: Integrated programmable error amplifier

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a disk drive actuator system, and more particularly to an integrated programmable error amplifier for controlling a current signal used to drive an actuator to position a transducing head. 
     Disk drive systems conventionally use an actuator arm to move a transducing head to a radial position on a magnetic disk. A position control loop is used to read the actual radial position of the head and compare it to the desired position, which generates a position error signal. This position error signal is used to generate a command to move the head to the correct position. 
     In order to move the head, a servo controller is provided to convert the position error signal generated by a position control loop into a current command for controlling a current control loop to drive the disk drive actuator motor to move the head. The current control loop includes an error amplifier which compares a desired actuator motor current to an actual actuator motor current, and controls the current delivered to the actuator motor accordingly. The error amplifier is typically configured with a single ended operational amplifier as part of an actuator motor controller on an integrated circuit, with three discrete resistors and two discrete capacitors. The error amplifier is implemented to have a pole in its response at a frequency of zero, and also to have a zero in its response. The zero in the response of the error amplifier is created by one of the resistors and one of the capacitors. Often a second pole is also desirable in the response of the amplifier/controller, to improve the rise time of the response and to improve noise performance. The second pole is created by the same resistor that creates the zero in the response, and by the two capacitors. 
     While the error amplifier configured with a single ended operational amplifier has provided effective response characteristics for controlling the position of the head, the necessity for discrete components requires extra pins in the integrated circuit package, which can increase packaging costs, and requires additional printed circuit board space to implement the discrete components externally, which is undesirable since space is at a premium for the increasingly small disk drives currently in production. These problems would be magnified even further if the circuit were to be built differentially, which could improve the power supply rejection ratio (PSRR) of the circuit. There is a need in the art for an error amplifier and compensation circuit that may be realized in an integrated circuit while providing the high performance response characteristics needed to effectively control the current provided to the actuator motor to position the head in the disk drive system. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is an error amplifier for use in a disk drive actuator system having an actuator motor for radially positioning a transducing head with respect to a rotatable disk. The error amplifier includes a switched-capacitor proportional-integral controller for comparing first and second differential input signals representing a respective actual current and commanded current for driving the actuator motor, and providing a differential output signal. A transconductor-capacitor filter is connected to filter the differential output signal of the switched-capacitor proportional-integral controller, and provides a motor control signal to control the actuator motor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a typical disk drive actuator control system. 
     FIG. 2 is a block diagram of a typical motor control circuit of a disk drive actuator control system. 
     FIG. 3 is a circuit schematic diagram of a typical discrete component proportional-integral controller. 
     FIG. 4 is a block diagram of motor controller employing an error amplifier according to the present invention. 
     FIG. 5 is a circuit schematic diagram of a proportional-integral controller of the error amplifier of the present invention. 
     FIG. 6 is a circuit schematic diagram of a transconductor-capacitor filter of the error amplifier of the present invention. 
     FIG. 7 is a circuit schematic diagram of a transconductance and capacitance cell of the transconductor-capacitor filter of the present invention. 
     FIG. 8 is a circuit schematic diagram of a transconductor reference biasing circuit of the transconductor-capacitor filter of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 is a block diagram of a typical disk drive actuator system  10 . Disk drive actuator system  10  includes a servo controller  11 , a position control circuit  12 , a digital-to-analog converter (DAC)  13 , a transconductance motor control circuit  14 , a motor  16 , an actuator arm  18 , a transducing head  20 , a disk  22 , a preamplifier  24  and a signal conditioning and decoder circuit  25 . Disk drive actuator system  10  is operable to move transducing head  20  to a radial position on disk  22 . A position control loop is used to read the actual radial position of the head and compare it to a desired position, which produces a position error signal. The position error signal is used to produce a current to drive actuator motor  16  to move head  20  supported by actuator arm  18  to the desired position. 
     Disk  22  includes a plurality of concentric tracks on which data and position information is recorded. Head  20  is operable to read the data and position information from the tracks of disk  22  and generate an input signal representative of the data and position information. The input signal is amplified by preamplifier  24  and filtered and decoded by signal conditioning and decoder circuit  25  to produce a digital signal that indicates the actual position of head  20  with respect to the tracks of disk  22 . 
     Servo controller  11  receives a digital signal Commanded Position identifying the desired track location of head  20 , and also receives a digital signal Actual Position from signal conditioning and decoder circuit  25  identifying the actual track location of head  20 . Servo controller  11  compares digital signal Commanded Position to digital signal Actual Position, and generates Position Error Signal, which is operated on by position control circuit  12  to create digital signal Current Command for controlling the movement of head  20  to the desired track location. Digital signal Current Command is converted to an analog control signal by DAC  13 , which is input to transconductance motor control circuit  14 . 
     Transconductance motor control circuit  14  controls the current that drives motor  16  to move head  20  to the desired track location. Transconductance motor control circuit  14  receives an analog current command signal in the form of a voltage from DAC  13 , and provides a current Imotor corresponding to the current command to motor  16  to move head  20  to the desired track location. 
     FIG. 2 is a block diagram of typical transconductance motor control circuit  14  of disk drive actuator system  10 . A transconductance control loop is used to measure the current to actuator motor  16  as a voltage and compare it to an analog voltage representing the current command signal. Transconductance motor control circuit  14  includes an error amplifier  32 , an output amplifier  34 , a current sense amplifier  36 , and a resistor Ris. 
     Error amplifier  32  receives a voltage Vdac from digital-to-analog converter  13  (FIG.  1 ), and also receives a voltage Vis from current sense amplifier  36 . Current sense amplifier  36  measures the current to motor  16  by measuring the voltage drop across a small resistor Ris, which is connected in series with motor  16 . Current sense amplifier  36  then amplifies the voltage drop across resistor Ris and provides a voltage Vis to error amplifier  32 . Error amplifier  32  compares voltage Vis to voltage Vdac, and provides a voltage Verroramp which represents the voltage that will cause the difference between voltages Vdac and Vis to be zero. 
     Output amplifier  34  receives voltage Verroramp from error amplifier  32 , and then amplifies voltage Verroramp to yield Vmotor which produces current motor in actuator motor  16  and resistor Ris. 
     Error amplifier  32  functions as a proportional-integral controller where voltage Verroramp is a linear combination of the difference between voltages Vdac and Vis and the integral of the difference between voltages Vdac and Vis. A proportional-integral controller has a zero and a pole in its frequency response. The zero is generally used to cancel the electrical pole of the motor conductance in the open-loop response. A second pole can be added to the frequency response of a proportional-integral controller, which has the advantage of giving the transconductance control loop a two-pole closed-loop frequency response. With the second pole in the closed-loop frequency response, the rise time of the step response can be increased, and the noise performance can be improved because the noise equivalent bandwidth for a given cutoff frequency can be improved. An example of a proportional-integral controller with a two-pole frequency response is shown in FIG.  3 . 
     FIG. 3 is a circuit schematic diagram of a typical discrete component error amplifier  32 , implemented as a proportional-integral controller. Although the present invention does not use discrete components, the proportional-integral controller shown in FIG. 3 serves as a model for explaining the theory underlying the present invention. Error amplifier (proportional-integral controller)  32  includes operational amplifier A 1 , capacitors Ca and Cc, resistors Rdac, Ris, and Rc, input signal nodes Vdac, Vis, and Vref, and output signal node Verroramp. Operational amplifier A 1  has first (+) and second (−) input nodes, and an output node connected to output signal node Verroramp. Input signal node Vref functions as a virtual ground and is connected to the first input node of operational amplifier A 1 . Input signal node Vdac is connected to the second input node of operational amplifier A 1  through resistor Rdac, and input signal node Vis is connected to the second input node of operational amplifier A 1  through resistor Ris. Capacitor Ca is connected between the second input node and the output node of operational amplifier A 1 . Resistor Rc and capacitor Cc are connected in series between the second input node and the output node of operational amplifier A 1 . 
     The proportional-integral controller operates in a manner generally known in the art, operating on an input signal and an integral component of the input signal to provide an output signal for controlling the operation of the disk drive motor in a manner that will cause the current through the actuator motor to correspond to the commanded current. The frequency response of the proportional-integral controller includes a second pole, due to the configuration of Ca, Rc, and Cc. 
     The proportional-integral controller shown in FIG. 3, however, has several disadvantages. Using integrated resistors and capacitors to build a proportional-integral controller makes its production in integrated circuit form extremely difficult, if not practically impossible. This is because of the need for large-valued capacitors and/or large-valued resistors to meet the requirement of accurate RC time constants. Using external components requires extra pins for the integrated circuit package, which increases packaging costs. External discrete components also require additional printed circuit board space, and if the same motor controller is to be used in different types of disk drive actuator systems, then different discrete parts may be required to achieve the necessary closed-loop response adding further expense. Furthermore, implementing external discrete components as a differential circuit would require twice as many pins and discrete components as a single-ended solution. 
     Error amplifier (proportional-integral controller)  32  has the transfer function:                    V   erroramp          (   s   )       =       [         -     1     R   is                V   is          (   s   )         -       1     R   dac              V   dac          (   s   )           ]                     {       (         sC   c          R   c       +   1     )     /     [     s        (       s                       C   a          C   c           C   a     +     C   c              R   c       +   1     )       ]       }              
        Generally   ,       C   a          &lt;&lt;     C   c         ,       so                       C   a          C   c           C   a     +     C   c              R   c       ≈       C   a          R   c                 (     Eq   .              1     )                         
     Therefore, the transfer function can be rewritten as:                  V   erroramp          (   s   )       ≈       {       [         -     1     R   is                V   is          (   s   )         -       1     R   dac              V   dac          (   s   )           ]          [       (         sC   c          R   c       +   1     )     s     ]       }          {     1     (         sC   a          R   c       +   1     )       }               (     Eq   .              2     )                         
     This new transfer function shows that an error amplifier can be split into two circuits, with each circuit providing a pole in the frequency response and one of the circuits also providing a zero. A first circuit can represent the first term:              {       [         -     1     R   is                V   is          (   s   )         -       1     R   dac              V   dac          (   s   )           ]          [       (         sC   c          R   c       +   1     )     s     ]       }           (     Eq   .              3     )                         
     And a second circuit can represent the second term:              {     1     (         sC   a          R   c       +   1     )       }           (     Eq   .              4     )                         
     The first circuit can be realized in integrated circuit form with a switched-capacitor proportional-integral controller. The switched-capacitor technique is based on the realization that a capacitor switched between two circuit nodes at a sufficiently high rate is equivalent to a resistor connecting these two nodes. The second circuit can also be realized in integrated circuit form with a transconductor-capacitor low-pass filter. However, instead of using capacitors in the second circuit, the gate oxide capacitances of NMOS transistors can be used. Therefore, it is possible for a newly designed error amplifier to include both circuits in an integrated circuit design. 
     FIG. 4 is a block diagram of a transconductance motor control circuit  14 ′ employing error amplifier  48  according to the present invention. Transconductance motor control circuit  14 ′ includes a proportional-integral controller  50  and a transconductor-capacitor filter  52  making up error amplifier  48 , an output amplifier  54 , a current-sense amplifier  56  and a resistor Ris. 
     Proportional-integral controller  50  is a fully differential proportional-integral controller with one pole and one zero in its frequency response. A fully differential proportional-integral controller with common mode feedback provides better power supply rejection than a single-ended proportional-integral controller. Proportional-integral controller  50  receives a differential voltage Vdac representing the current command signal, receives a differential voltage Vis from current sense amplifier  56 , and provides a differential voltage Vo to transconductor-capacitor filter  52 . 
     Transconductor-capacitor filter  52  is a differential transconductor-capacitor low-pass filter with one pole in its frequency response. Transconductor-capacitor filter  52  may be constructed as is generally known in the art, and is operable to receive differential voltage Vo from proportional-integral controller  50  and provide a differential motor control signal Verroramp according to the following equation:                  V   erroramp       V   o       =       (       sC   Gm     +   1     )       -   1               (     Eq   .              5     )                         
     where C is the value of the capacitor in the filter and Gm is the gain of the transconductor in the filter. 
     FIG. 5 is a circuit schematic diagram of proportional-integral controller  50  of error amplifier  48  of the present invention. Proportional-integral controller  50  includes input signal nodes Vis+, Vis−, Vdac+, and Vdac−, switches Sis 1 -Sis 4 , Sdac 1 -Sdac 4 , Scom 1 -Scom 4 , Sx 1 -Sx 4 , and Src 1 -Src 4 , capacitors Cis 1 , Cis 2 , Cdac 1 , Cdac 2 , Cx 1 , Cx 2 , Crc 1 , Crc 2 , Cc 1 , and Cc 2 , differential operational amplifier U 1 , output signal nodes Vo+ and Vo−, and fixed potential Vssg, which is the small-signal ground reference voltage of the circuit. Differential operational amplifier U 1  has first and second input nodes and first and second output nodes. 
     Switch Sis 2  is connected between input signal node Vis+ and capacitor Cis 1 , and switch Sis 4  is connected between input signal node Vis− and capacitor Cis 2 . Switch Sdac 2  is connected between input signal node Vdac+ and capacitor Cdac 1 , where capacitor Cdac 1  is connected to capacitor Cis 1 . Switch Sdac 4  is connected between input signal node Vdac− and capacitor Cdac 2 , where capacitor Cdac 2  is connected to capacitor Cis 2 . Switch Sis 1  is connected between switch Sis 2  and fixed potential Vssg, switch Sis 3  is connected between switch Sis 4  and fixed potential Vssg, switch Sdac 1  is connected between switch Sdac 2  and fixed potential Vssg, and switch Sdac 3  is connected between switch Sdac 4  and fixed potential Vssg. Switch Scom 2  is connected between capacitor Cis 1  and the second input node of differential operational amplifier U 1 , and switch Scom 4  is connected between capacitor Cis 2  and the first input node of differential operational amplifier U 1 . Switch Scom 1  is connected between capacitor Cis 1  and fixed potential Vssg, and switch Scom 3  is connected between capacitor Cis 2  and fixed potential Vssg. Switch Sx 1  is connected between the second input node of differential operational amplifier U 1  and capacitor Cx 1 , where capacitor Cx 1  is connected to the first output node of differential operational amplifier U 1 . Switch Sx 3  is connected between the first input node of differential operational amplifier U 1  and capacitor Cx 2 , where capacitor Cx 2  is connected to the second output node of differential operational amplifier U 1 . Switch Sx 2  is connected between switch Sx 1  and fixed potential Vssg, and switch Sx 4  is connected between switch Sx 3  and fixed potential Vssg. Switch Src 2  is connected between capacitors Crc 1  and Cc 1 , where capacitors Crc 1  and Cc 1  are connected respectively to capacitor Cis 1  and the first output node of differential operational amplifier U 1 . Switch Src 4  is connected between capacitors Crc 2  and Cc 2 , where capacitors Crc 2  and Cc 2  are connected respectively to capacitor Cdac 2  and the second output node of differential operational amplifier U 1 . Switch Src 1  is connected between capacitor Crc 1  and fixed potential Vssg, and switch Src 3  is connected between capacitor Crc 2  and fixed potential Vssg. The first and second output nodes of differential operational amplifier U 1  are connected respectively to output signal nodes Vo+ and Vo−. 
     In operation, two non-overlapping clock phases Φ 1  and Φ 2  exist for proportional-integral controller  50 . During clock phase Φ 1 , switches Sis 1 , Sis 3 , Sdac 1 , Sdac 3 , Scom 1 , Scom 3 , Sx 1 , Sx 3 , Src 1 , and Src 3  are turned on, and switches Sis 2 , Sis 4 , Sdac 2 , Sdac 4 , Scom 2 , Scom 4 , Sx 2 , Sx 4 , Src 2 , and Src 4  are turned off. Switches Sis 1  and Scom 1  function to discharge capacitor Cis 1 , and switches Sis 3  and Scom 3  discharge capacitor Cis 2 . Similarly, switches Sdac 1  and Scom 1  discharge capacitor Cdac 1 , and switches Sdac 3  and Scom 3  discharge capacitor Cdac 2 . In addition, switches Src 1  and Scom 1  discharge capacitor Crc 1 , and switches Src 3  and Scom 3  discharge capacitor Crc 2 . Also during clock phase Φ 1 , switch Sx 1  connects capacitor Cx 1  to the second input node of differential operational amplifier U 1 , and switch Sx 3  connects capacitor Cx 2  to the first input node of differential operational amplifier U 1 . Because capacitors Cx 1  and Cx 2  are connected between the output nodes and input nodes of differential operational amplifier U 1 , the first and second output nodes of differential operational amplifier U 1  are held respectively to the voltages that were stored in capacitors Cx 1  and Cx 2  during the previous clock phase Φ 2 . 
     During clock phase Φ 2 , switches Sis 2 , Sis 4 , Sdac 2 , Sdac 4 , Scom 2 , Scom 4 , Sx 2 , Sx 4 , Src 2 , and Src 4  are turned on, and switches Sis 1 , Sis 3 , Sdac 1 , Sdac 3 , Scom 1 , Scom 3 , Sx 1 , Sx 3 , Src 1 , and Src 3  are turned off. Switches Sis 2  and Sis 4  connect input signal nodes Vis+ and Vis− to capacitors Cis 1  and Cis 2  respectively. The voltages at input signal nodes Vis+ and Vis− cause currents to flow to and charge capacitors Cis 1  and Cis 2 . Switches Sdac 2  and Sdac 4  connect input signal nodes Vdac+ and Vdac− to capacitors Cdac 1  and Cdac 2  respectively. The voltages at input signal nodes Vdac+ and Vdac− cause currents to flow to and charge capacitors Cdac 1  and Cdac 2 . The currents through capacitors Cis 1  and Cdac 1  are summed, and connected to the second input node of differential operational amplifier U 1  through switch Scom 2 . The currents through capacitors Cis 2  and Cdac 2  are summed, and connected to the first input node of differential operational amplifier U 1  though switch Scom 4 . Ideally, differential operational amplifier U 1  has infinite input impedance, so the sum of the currents that flow through capacitors Cis 1  and Cdac 1  also flows through capacitors Crc 1  and Cc 1 . Therefore, the sum of the charges in capacitors Cis 1  and Cdac 1  is added to capacitors Crc 1  and Cc 1 . Similarly, the sum of the currents that flow through capacitors Cis 2  and Cdac 2  also flows through capacitors Crc 2  and Cc 2 . Therefore, the sum of the charges in capacitors Cis 2  and Cdac 2  is added to capacitors Crc 2  and Cc 2 . 
     The output taken at output signal nodes Vo+ and Vo− is a function of the charges stored in capacitors Crc 1 , Crc 2 , Cc 1 , and Cc 2 . Because capacitors Crc 1  and Crc 2  are discharged every Φ 1  clock phase, their contributions to the output are related to the inputs at input signal nodes Vis+, Vis−, Vdac+, and Vdac− for a given Φ 2  clock phase period. These contributions provide the proportional term. Capacitors Cc 1  and Cc 2  are not discharged, therefore their contributions provide the integral term by integrating (summing) the previous charges during the Φ 2  clock phase. The output at output signal nodes Vo+ and Vo− is discrete in time because of the switching nature of the circuit. Therefore, the transfer function of proportional-integral controller  50  can be accurately defined in the z-domain:                  V   o          (   z   )       =     -       [         C   dac            V   dac          (   z   )         +       C   is            V   is          (   z   )           ]          [       (             C   rc     +     C   c           C   rc          C   c            z     -     1     C   rc         )     /     (     z   -   1     )       ]                 (     Eq   .              6     )                         
     where: 
     Cis=Cis 1 =Cis 2 , 
     Cdac=Cdac 1 =Cdac 2 , 
     Crc=Crc 1 =Crc 2 , and 
     Cc=Cc 1 =Cc 2 . 
     Because proportional-integral controller  50  is intended for use in different disk drive actuator systems, proportional-integral controller  50  is programmable to provide a variety of responses. The periods of clock phases Φ 1  and Φ 2  are programmable, as well as the value of capacitors Cis 1 , Cis 2 , Cdac 1 , Cdac 2 , Cc 1 , and Cc 2 , by techniques generally known in the art. 
     FIG. 6 is a circuit schematic diagram of transconductor-capacitor filter  52  of error amplifier  48  of the present invention. Transconductor-capacitor filter  52  includes input signal nodes Vi+ and Vi−, transconductance cells G 1  and G 2 , capacitors C 1  and C 2 , buffers B 1 , B 2 , B 3  and B 4 , output signal nodes Vo+ and Vo−, and fixed potential GND. Transconductance cells G 1  and G 2  are each transconductors having first and second input nodes and an output node. Bias currents for transconductance cells G 1  and G 2  are generated by a transconductor reference circuit G 3  described later and shown in FIG.  8 . Input signal nodes Vi+ and Vi− are connected respectively to the first input nodes of transconductance cells G 1  and G 2 . The output nodes of transconductance cells G 1  and G 2  are connected through buffers B 1  and B 3 , respectively, to output signal nodes Vo+ and Vo−. The output node of transconductance cell G 1  is connected through buffer B 2  to the second input node of transconductance cell G 1 , and the output node of transconductance cell G 2  is connected through buffer B 4  to the second input node of transconductance cell G 2 . The output node of transconductance cell G 1  is connected through capacitor C 1  to fixed potential GND and the output node of transconductance cell G 2  is connected through capacitor C 2  to fixed potential GND. In the configuration shown in FIG. 6, transconductor-capacitor filter  52  is a pseudo-differential realization of a low-pass filter. 
     In order to keep the capacitor area of transconductor-capacitor filter  52  to a minimum, the transconductance of transconductance cells G 1  and G 2  need to be low. To attain a low transconductance, a differential pair with floating voltage sources can be used, where the floating voltage sources are implemented with source followers. These floating voltage sources reduce the overall transconductance for a given bias current. Furthermore, the floating voltage sources give the transconductance a linear response over a large dynamic range. Such a transconductance cell is shown in FIG.  7 . 
     FIG. 7 is a circuit schematic diagram of transconductance cell G 1  (which is identical to transconductance cell G 2 ) and capacitance C 1  (which is identical to capacitance C 2 ) of transconductor-capacitor filter  52 . Transconductance cell G 1  includes transistors M 1 -M 9 , current source transistors MI 1 -MI 7 , a capacitor realized by transistor MC 1 , input signal nodes Vgi+ and Vgi−, input bias nodes Vref 1  and Vref 2 , output signal node Vgo, and fixed potentials VPOS and GND. Transistors M 1 -M 7  and current mirror transistors MI 1 , MI 2 , and MI 5 -MI 7  are PMOS transistors each having a gate, a source, and a drain. Transistors M 8  and M 9  and current mirror transistors MI 3  and MI 4  are NMOS transistors each having a gate, a source, and a drain. The gates of current source transistors MI 1 , MI 2 , and MI 5 -MI 7  are each biased by a signal provided at node Vpbias by transconductance cell G 3  (shown in FIG. 8) of transconductor-capacitor filter  52 . The gates of current source transistors MI 3  and MI 4  are biased by a signal provided at node Vnbias by transconductance cell G 3  (FIG. 8) of transconductor-capacitor filter  52 . Input signal node Vgi+ is connected to the gates of transistors M 1  and M 2 , and input signal node Vgi− is connected to the gates of transistors M 3  and M 4  and the source of transistor M 6 . Current mirror transistor MI 1  has its source connected to fixed potential VPOS, and its drain connected to the sources of transistors M 1  and M 3 . Current mirror transistor MI 2  has its source connected to fixed potential VPOS, and its drain connected to the sources of transistors M 2  and M 4 . Current mirror transistor MI 3  has its drain connected to the drain of transistor M 1 , and its source connected to fixed potential GND. Current mirror transistor MI 4  has its drain connected to the drain of transistor M 4 , and its source connected to fixed potential GND. The drains of transistors M 2  and M 3  are each connected to fixed potential GND. Input bias node Vref 1  is connected to the gates of transistors M 8  and M 9 , and input bias node Vref 2  is connected to the gate of transistor M 5  and the drain of transistor M 8 . Current mirror transistor MI 5  has its source connected to fixed potential VPOS, and its drain connected to the source of transistor M 5 . The drain of transistor M 5  is connected to the drain of transistor M 9 . The sources of transistors M 8  and M 9  are connected respectively to the drains of transistors M 1  and M 4 . The gates of transistors M 6  and M 7  are connected to the drain of transistor M 9 , and transistor MC 1  is connected between the gate of transistor M 7  and fixed potential GND to realize capacitor C 1 . Transistor MC 1  is an NMOS transistor having a gate, a source, a body and a drain, with the gate connected to the gate of transistor M 7  and the source, body and drain all connected to fixed potential GND. Transistor MC 1  is used instead of a discrete capacitors because when NMOS transistors are biased far above a threshold voltage so that their channels are fully depleted, they provide a nearly constant capacitance over the input voltage range. In addition, NMOS transistors may also provide a larger capacitance per unit area than a discrete capacitor, and the dependence of capacitance on oxide thickness can be removed through proper implementation of a reference cell. Therefore, capacitor C 1  can be realized by transistor MC 1  as shown in FIG. 7, which is more suitable for fabrication in an integrated circuit. Current mirror transistor MI 6  has its source connected to fixed potential VPOS, and its drain connected to the source of transistor M 6 . Current mirror transistor MI 7  has its source connected to fixed potential VPOS, and its drain connected to the source of transistor M 7 . The drains of transistors M 6  and M 7  are each connected to fixed potential GND. Output signal node Vgo is connected to the source of transistor M 7 . 
     Transistors M 1  and M 4  form a differential pair and have identical widths and lengths. Transistors M 2  and M 3  are floating voltage sources and also have identical widths and lengths. The ratios of width to length for transistors M 1 -M 4  are nW 1 /L 1 =W 2 /L 2 =W 3 /L 3 =nW 4 /L 4 , where a larger constant n helps reduce the transconductance of differential pair M 1  and M 4 . To further reduce transconductance, transistors M 1 -M 4  are PMOS transistors instead of NMOS transistors because the hole mobility of PMOS transistors is less than the electron mobility of NMOS transistors. 
     Transistors M 8  and M 9  are folded cascode devices that are used to increase signal dynamic range, increase output impedance and reduce loading of the output. Current mirror transistor MI 5  has transistor M 5  as a cascode device to reduce the capacitive loading of the transconductance output of transistor M 9 . The current of transistor M 8  is not used, which farther reduces the effective transconductance. Because the output current of transistor M 8  is not used, a pseudo-differential structure utilizing dual transconductors and capacitors as shown in FIG. 6 is needed to realize the desired linear response over the differential range. The transconductance output of transistor M 9  is connected to transistor MC 1  to give the desired frequency response. 
     Transistors M 6  and M 7  are source followers that function as buffers at the transconductance output of transistor M 9 . The source of transistor M 6  is an output connected to input signal node Vgi−. Transistor M 6  improves the frequency response because without transistor M 6 , the capacitances of transistors M 3  and M 4  would load capacitor C 1  (realized by transistor MC 1 ). The source of transistor M 7  is connected to output signal node Vgo. Transistor M 7  reduces capacitive feed through from input signal node Vgi+ to output signal node Vgo through the large gate-to-source capacitances of transistors M 1 -M 4 . 
     The gate oxide capacitances in transconductance cell G 1  are a function of oxide thickness. Therefore the performance (cutoff frequency) of transconductance cell G 1  is a function of oxide thickness. It is generally undesirable for manufacturing variances to dictate the performance of transconductance cells G 1  and G 2 . To solve this potential problem, transconductance cell G 3  is configured not only to provide bias currents to transconductance cells G 1  and G 2 , but also to eliminate their sensitivity to oxide thickness. 
     FIG. 8 is a circuit schematic diagram of transconductance cell G 3  of transconductor-capacitor filter  52 . Transconductance cell G 3  includes transistors M 11 -M 15  and M 18 -M 20 , current mirror transistors MI 11 -MI 14 , bias transistors Mpref and Mnref, a zero temperature coefficient voltage Vtref, a current source Itref, an input bias node Vref 3 , an output signal node Vbo, and fixed potentials VPOS and GND. Transistors M 11 -M 15  and M 20 , current mirror transistors MI 11  and MI 12 , and bias transistor Mpref are PMOS transistors each having a gate, a source, and a drain. Transistors M 18  and M 19 , current mirror transistors MI 13  and MI 14 , and bias transistor Mnref are NMOS transistors each having a gate, a source, and a drain. Current source Itref is a reference current source that is a function of oxide thickness. Zero temperature coefficient voltage Vtref has a positive node connected to the gates of transistors M 11  and M 12 , and a negative node connected to the gates of transistors M 13  and M 14 . Current mirror transistor MI 11  has its source connected to fixed potential VPOS, and its drain connected to the sources of transistors M 11  and M 13 . Current mirror transistor MI 12  has its source connected to fixed potential VPOS, and its drain connected to the sources of transistors M 12  and M 14 . Current mirror transistor MI 13  has its drain connected to the drain of transistor M 11 , and its source connected to fixed potential GND. Current mirror transistor MI 14  has its drain connected to the drain of transistor M 14 , and its source connected to fixed potential GND. The drains of transistors M 12  and M 13  are each connected to fixed potential GND. Input bias node Vref 3  is connected to the gates of transistors M 18  and M 19 , and the sources of transistors M 18  and M 19  are connected respectively to the drains of current mirror transistors MI 13  and MI 14 . Transistor M 20  has its source connected to fixed potential VPOS, its gate connected to its drain, and its drain connected to the drain of transistor M 18 . Transistor M 15  has its source connected to fixed potential VPOS, its gate connected to the gate of transistor M 20 , and its drain connected to the drain of transistor M 19  and output signal node Vbo. Output signal node Vbo is connected to the gates of current mirror transistors MI 11  and MI 12 , as well as the gate of bias transistor Mpref. Bias transistor Mpref has its source connected to fixed potential VPOS, and its drain connected to the drain of bias transistor Mnref. Bias transistor Mnref has its drain connected to its gate, its gate connected to the gates of current mirror transistors MI 13  and MI 14 , and its source connected to fixed potential GND. Current source Itref is connected between output signal node Vbo and fixed potential GND. The gate of transistor Mpref is connected to biasing output node Vpbias, and the gate of transistor Mnref is connected to biasing output node Vnbias. 
     Transistors M 11 -M 14  in transconductance cell G 3  are identical in width and length to transistors M 1 -M 4  in transconductance cell G 1 . Similar to the configuration described above with respect to FIG. 7, transistors M 18  and M 19  are folded cascode devices. The output drain current from transistor M 18  is input into the mirror formed by transistors M 20  and M 15 . The output drain current of transistor M 19  is subtracted from the output drain current of transistor M 15 , and this difference is the output current Ibo of transconductance circuit G 3 . Negative feedback is employed from output signal Vbo to bias the gates of transistors MI 11 , MI 12  and Mpref. Mpref in turn feeds current into the mirror formed by transistors MI 13 , MI 14  and Mnref. The circuit is properly biased when output current Ibo is equal to the current of reference current source Itref. The gate voltages of transistors Mpref and Mnref are used to bias the gates of current mirror transistors MI 1 -MI 7  of transconductance cell G 1  shown in FIG. 7 (which is identical to transconductance cell G 2  also shown in block diagram form in FIG.  6 ). Also, when output current Ibo of transconductance cell G 3  is equal to the current of reference current source Itref, then the transconductance of transconductance cell G 3  is a linear function of oxide thickness, since:                  G   m          (     T   ox     )       =         I   tref          (     T   ox     )         V   tref               (     Eq   .              7     )                         
     Because the gate voltages of transistors Mpref and Mnref are shared between transconductance reference cell G 3  and transconductance filter cells G 1  and G 2 , the transconductances of all three transconductance cells G 1 -G 3  are a function of oxide thickness. Since the capacitors of the filter circuit are also MOS devices, they have properties that are also a linear function of the same oxide thickness. The cutoff frequency of transconductance cells G 1  and G 2  is defined by:              ω   =         G   m          (     T   ox     )         C        (     T   ox     )                 (     Eq   .              8     )                         
     Since the dependence of both transconductance and capacitance on the oxide thickness is linear, the dependence on oxide thickness cancels out of the equation, so that the cutoff frequency of the circuit is relatively insensitive to oxide thickness, as well as to temperature and other process parameters. 
     The present invention therefore provides a newly designed error amplifier for use in a disk drive actuation system that may be realized in an integrated circuit while providing the high performance response characteristics needed to effectively control the current that drives the actuator motor to position the head in the disk drive. The error amplifier and compensation circuit of the present invention eliminates the need for large-valued integrated resistors and/or capacitors which have traditionally made implementation in an integrated circuit prohibitive and which have typically been implemented as discrete components, which was problematic due to the necessity for extra pins and the inefficient usage of printed circuit board space, which is at a premium in such systems. The circuit of the present invention achieves this with two main circuit portions. A switched-capacitor proportional-integral controller compares differential input signals representing the actual current through the actuator motor and the commanded current, and generates a control signal for driving the actuator motor with the proper current. The control signal is input to a transconductor-capacitor filter which filters the discrete time proportional-integral controller output, provides a second pole in the overall transconductance response, and provides a motor control signal to control the actuator motor. Both the switched-capacitor proportional-integral controller and the transconductor-capacitor filter are readily fabricated in an integrated circuit, which is desirable to save space and expense in the disk drive system. 
     Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.