Patent Publication Number: US-8116148-B2

Title: Low power shift register and semiconductor memory device including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 12/164,384 filed on Jun. 30, 2008 now U.S. Pat. No. 7,852,687, which claims priority of Korean patent application number 10-2008-0033674 filed on Apr. 11, 2008. The disclosure of each of the foregoing applications is incorporated herein reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a shift register used in a variety of integrated circuits and the like, and more particularly, to a shift register consuming less current. 
     A shift register is a device for shifting an input signal in synchronization with a clock when transferring the input signal. The shift register is used in an integrated circuit, a semiconductor device and the like. 
     Hereinafter, the shift register used in a semiconductor memory device will be exemplarily described. 
     A semiconductor memory device satisfying DDR2/DDR3 specification secures a write recovery time (tWR) to ensure a complete data storage operation in a memory cell enabled by an active command. That is, a precharge operation of the cell is prohibited during the write recovery time (tWR). 
     In an auto precharge mode, even if a separate precharge command is not given, the precharge operation is performed at a timing defined in the specification if a column address &lt;10&gt; has a logic high level when a write or read command is applied. As a result of the precharge operation, an activated word line is deactivated and a bit line is precharged. 
     In the auto precharge mode, if a write with auto precharge command is applied, a start point of the precharge operation is determined by the write recovery time (tWR) based on the clock, which is set in a mode register set. 
     That is, the precharge operation is started internally after the write recovery time (tWR) from an input of the write with auto precharge command. 
     The shift register is used to allow the precharge operation to be performed after the write recovery time (tWR), which is based on the clock, from the input of the write command. 
       FIG. 1  is a circuit diagram of a conventional shift register used in a semiconductor memory device to secure a write recovery time (tWR). 
     Referring to  FIG. 1 , the conventional shift register includes a plurality of shift units  110 ,  120 ,  130 ,  140 ,  150  and  160 . Each of the shift units  110  to  160  shifts an input signal by one clock pulse in synchronization with a clock CLOCK. 
     The input signal is a write with precharge signal INPUT that is activated when a write command is input when a column address &lt;10&gt; has a logic high level. The plurality of shift units  110  to  160  each shifts the write with precharge signal INPUT by one clock pulse in synchronization with the clock CLOCK. 
     One of output signals A, B, C, D, E and F of the plurality of shift units  110 ,  120 ,  130 ,  140 ,  150  and  160  is output as an auto precharge signal APCG. For example, when the write recovery time tWR is 3, the write with precharge signal INPUT is delayed by the three shift units  110 ,  120  and  130  before being output as the auto precharge signal APCG. When the write recovery time tWR is 6, the write with precharge signal INPUT is delayed by the six shift units  110 ,  120 ,  130 ,  140 ,  150  and  160  before being output as the auto precharge signal APCG. The write recovery time tWR is set at a value between 1 and 6 by signals TWR 1 , TWR 2 , TWR 3 , TWR 4 , TWR 5  and TWR 6  respectively. 
     That is, the shift register delays the write with precharge signal INPUT by the write recovery time tWR based on the clock CLOCK to output the auto precharge signal APCG. 
       FIG. 2  is a circuit diagram of the shift unit  110  in the conventional shift register of  FIG. 1 . 
     Referring to  FIG. 2 , the shift unit  110  includes two pass gates PG 1  and PG 2 , and two latches  111  and  112 . This is because the shift unit  110  is designed to shift the write with precharge signal INPUT by one clock pulse. In a case where the shift unit  110  is designed to shift the write with precharge signal INPUT by half a clock pulse, the shift unit  110  may include only one pass gate and one latch. 
     In operation, when the clock CLOCK has a logic low level, the first gate PG 1  is turned on, and when the clock CLOCK has a logic high level, the second pass gate PG 2  is turned on. Then, the write with precharge signal INPUT is sequentially shifted to the latch unit  111  and then to the next latch unit  112  every half clock pulse. Consequently, the shift unit  110  including the two pass gates PG 1  and PG 2  and the two latches  111  and  112  shifts the write with precharge signal INPUT by one clock pulse. 
     The shift unit  110  further includes a transistor  113  configured to reset the signal in the latch  111  in response to an initialization signal INITIAL. 
       FIG. 3  is a timing diagram illustrating an operation of the conventional shift register of  FIG. 1 . 
     For simplicity,  FIG. 3  illustrates a case where the write recovery time tWR is 6. When the write with precharge signal INPUT is received, the shift register shifts the write with precharge signal INPUT by six clock pulses to output the auto precharge signal APCG. As such, the memory device can perform an auto precharge operation after the write recovery time tWR from a write operation. 
     As the operation speed of a memory device, semiconductor device or an integrated circuit including the shift register is increased, frequency of a clock for the shift register is also increased accordingly. 
     Then, the current consumption of the shift register is also increased accordingly. This is because the shift register is operated based on the clock, and thus the shift register consumes current every toggling of the clock. Therefore, there is a demand for a low power shift register consuming less current. 
     SUMMARY OF THE INVENTION 
     Embodiments of the present invention are directed to providing a low power shift register consuming less current and a semiconductor memory device including the low power shift register. 
     In accordance with an aspect of the invention, there is provided a shift register, comprising a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register. 
     As such, the shift register does not always toggle the shift clock, but instead, toggles the shift clock only while the input signal is shifted. Accordingly, it is possible to reduce current consumption of the shift register. 
     In accordance with another aspect of the invention, there is provided a semiconductor memory device, comprising, a shift circuit configured to shift a write with precharge signal in synchronization with a shift clock to output an auto precharge signal, and a clock control circuit configured to enable the shift clock in response to the write with precharge signal and disable the shift clock in response to the auto precharge signal. 
     As such, when the write with precharge signal is activated, the semiconductor memory device toggles the shift clock to shift the write with precharge signal. On the contrary, when the shifting is completed and thus the auto precharge signal is activated, the semiconductor memory device disables the shift clock, i.e., stops the toggling of the shift clock. Accordingly, it is possible to reduce current consumption of the semiconductor memory device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a conventional shift register used in a semiconductor memory device to secure a write recovery time. 
         FIG. 2  is a circuit diagram of a shift unit in the conventional shift register of  FIG. 1 . 
         FIG. 3  is a timing diagram illustrating an operation of the conventional shift register of  FIG. 1 . 
         FIG. 4  is a circuit diagram of a shift register in a semiconductor memory device, in accordance with an embodiment of the present invention. 
         FIG. 5  is a circuit diagram of a clock control circuit of the shift register of  FIG. 4 . 
         FIG. 6  is a timing diagram illustrating an overall operation of the shift register of  FIG. 4 . 
     
    
    
     DESCRIPTION OF SPECIFIC EMBODIMENTS 
     Hereinafter, a low power shift register and a semiconductor memory device including the low power shift register in accordance with the present invention will be described in detail with reference to the accompanying drawings. 
       FIG. 4  is a circuit diagram of a shift register in a semiconductor memory device, in accordance with an embodiment of the invention. 
     Referring to  FIG. 4 , the shift register includes a clock control circuit  410  and a shift circuit  420 . The clock control circuit  410  enables a shift clock ICLOCK in response to a write with precharge signal INPUT and disables the shift clock ICLOCK in response to an auto precharge signal APCG. The shift circuit  420  shifts the write with precharge signal INPUT in synchronization with the shift clock ICLOCK to generate the auto precharge signal APCG. 
     In more detail, the clock control circuit  410  enables the shift clock ICLOCK when the write with precharge signal INPUT is activated. The enabling of the shift clock ICLOCK refers to toggling the shift clock ICLOCK. Before the write with precharge signal INPUT is activated, there is no signal to shift, and thus there is no need to toggle the shift clock ICLOCK. The clock control circuit  410  disables the shift clock ICLOCK when the auto precharge signal APCG is activated. The disabling of the shift clock ICLOCK refers to stopping the toggling of the shift clock ICLOCK, i.e., fixing the logic level of the shift clock ICLOCK to a logic high level or a logic low level. 
     The shift clock ICLOCK is disabled when the auto precharge signal APCG is activated. However, it does not mean that the shift clock ICLOCK is disabled immediately when the auto precharge signal APCG is activated. This is because the auto precharge signal APCG needs a certain margin to be deactivated after being activated. Surely, in a case where the auto precharge signal APCG does not need to be deactivated after it is activated, the shift clock ICLOCK may be disabled immediately when the auto precharge signal APCG is activated. The clock control circuit  410  will be described in more detail later with reference to  FIG. 5 . 
     The shift circuit  420  shifts the write with precharge signal INPUT in synchronization with the shift clock ICLOCK. The shift circuit  420  includes a plurality of shift units  421  to  426 . Each of the shift units  421  to  426  shifts a signal input thereto by one clock pulse. The shift time of each of the shift units  421  to  426  may be appropriately selected. For example, each of the shift units  421  to  426  may also be designed to shift the signal input thereto by half clock or by two clock pulses or longer. Each of the shift units may be the conventional shift unit of  FIG. 2 . 
       FIG. 4  illustrates a shift register used in a semiconductor memory device, which receives a write with auto precharge signal INPUT to generate an auto precharge signal APCG. The shift time applied to the write with auto precharge signal INPUT for outputting the auto precharge signal APCG is determined by the write recovery time tWR. Accordingly, the shift register of  FIG. 4  outputs one of the output signals A, B, C, D, E and F of the respective shift units  421 ,  422 ,  423 ,  424 ,  425  and  426 , which is selected according to the write recovery time tWR, as the auto precharge signal APCG. 
     In a case that the shift time (number of clock pulses) needs to be varied, the shift register may further include a selection circuit  430  configured to select one of the output signals A, B, C, D, E and F of the respective shift units  421 ,  422 ,  423 ,  424 ,  425  and  426  to output the selected output signal as the auto precharge signal APCG. 
     The selection circuit  430  is configured to perform an OR operation on an initialization signal INITIAL and the auto precharge signal APCG to generate a reset signal RESET. The reset signal RESET is used to reset the signal in each of the shift units  421  to  426 . Therefore, whichever of the initialization signal INITIAL and the auto precharge signal APCG is activated, the reset signal RESET is activated to reset the signal in each of the shift units  421  to  426 . That is, the shift circuit  420  is reset when the auto precharge signal APCG is activated because the activation of the auto precharge signal APCG indicates the termination of the operation of the shift circuit  420 . The selection circuit  430  is optional, and it is also possible that each of the shift units  421  to  426  directly receives the initialization signal INITIAL. 
       FIG. 5  is a circuit diagram of a clock control unit of the shift register of  FIG. 4 . 
     The clock control circuit  410  includes a signal receiving unit  510 , a latch unit  520  and a control unit  530 . The signal receiving unit  510  activates a clock enable signal CKE in response to the write with precharge signal INPUT and deactivates the clock enable signal CKE in response to the auto precharge signal APCG. The latch unit  520  allows the clock enable signal CKE to be fixed at a constant logic level. The control unit  530  enables or disables the shift clock ICLOCK according to the clock enable signal CKE. 
     The signal receiving unit  510  includes an activation unit  511 , a delay unit  512  and a deactivation unit  513 . The activation unit  511  activates the clock enable signal CKE when the write with precharge signal INPUT is activated. The delay unit  512  delays the auto precharge signal APCG. The deactivation unit  513  deactivates the clock enable signal CKE when an output signal of the delay unit  512  is activated. 
     Referring to  FIG. 5 , the activation unit  511  may be configured with an NMOS transistor. The delay unit  512  may be configured with a typical delay unit or a shift unit, e.g., the shift unit  421  of  FIG. 4 , which delays a signal input thereto by one clock pulse. As described above, the delay unit  512  is configured to secure a margin, i.e., a time required to deactivate the auto precharge signal APCG after activating it. The delay time of the delay unit  512  may be appropriately selected. Typically, approximately one clock pulse is sufficient for the delay time. The deactivation unit  513  may be configured with an inverter for inverting an output signal of the delay unit  512 , and a PMOS transistor receiving an output signal of the inverter at a gate. 
     The latch unit  520  may have a simple configuration of a pair of inverters. An output terminal of the one inverter is connected to an input terminal of the other inverter, and vice versa. The control unit  530  may be configured with an AND gate (or a NAND gate and an inverter) for receiving the clock CLOCK and the clock enable signal CKE to generate the shift clock ICLOCK. 
     In operation, when the write with precharge signal INPUT has a logic high level, the activation unit  511  is turned on. Then, the clock enable signal CKE is activated to a logic high level and latched in the latch unit  520 . As the clock enable signal CKE is activated to a logic high level, the control unit  530  transfers the clock CLOCK directly as the shift clock ICLOCK. That is, the shift clock ICLOCK toggles so that the shift circuit  420  performs shift operations. 
     When the auto precharge signal is activated to a logic high level, the deactivation unit  513  is turned on after a certain margin which is determined by the delay unit  512 . Then, the clock enable signal CKE is deactivated to a logic low level and latched in the latch unit  520 . As the clock enable signal CKE is deactivated to a logic low level, the control unit  530  fixes the shift clock ICLOCK to a logic low level regardless of the toggling of the clock CLOCK. That is, the shift clock ICLOCK stops the toggling so that the shift circuit  420  does not perform the shift operation and thus does not consume current. 
       FIG. 6  is a timing diagram illustrating an overall operation of the shift register of  FIG. 4 . 
     For simplicity,  FIG. 6  illustrates the case where the write recovery time tWR is 6, i.e., where an output signal of the shift unit  426  is selected as the auto precharge signal APCG. 
     When the write with precharge signal INPUT is activated, the shift clock ICLOCK immediately starts toggling. Then, the write with precharge signal INPUT is shifted by six clock pulses by the shift circuit  420  to activate the auto precharge signal APCG. After a certain margin from the activation of the auto precharge signal APCG, the shift clock ICLOCK stops toggling. 
     As a result, the shift clock ICLOCK toggles only while the write with precharge signal INPUT is shifted and output as the auto precharge signal APCG. Accordingly, at other times, the shift clock ICLOCK does not toggle, and thus unnecessary current is not consumed. 
     As described above, the shift register in accordance with the embodiments of the invention enables the shift clock only while the input signal is actually shifted. As such, an unnecessary toggling of the shift clock can be prevented, and thus the current consumption due to the toggling of the shift clock can be reduced. 
     While the invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. 
     Particularly, although the shift register used in the semiconductor memory device is described above, the invention is not limited thereto. That is, the shift register in accordance with the invention may also be applied to any integrated circuit, semiconductor memory device and the like that need to delay an input signal based on a clock.