Patent Publication Number: US-7218333-B2

Title: Gray scale display apparatus using pulse width modulation

Description:
FIELD OF INVENTION 
     The present invention relates to a circuit for driving multi channels for use in a gray scale display apparatus; and, more particularly, to a pulse width modulation (PWM) selector in the circuit of the gray scale display apparatus using pulse width modulation (PWM). 
     DESCRIPTION OF PRIOR ART 
     In a liquid crystal display (hereinafter, referred to a LCD), which is generally used as a display device, each pixel basically includes a scanning electrode for controlling a scanning line included in the liquid crystal display and a data electrode for adjustably showing data on each pixel when each scanning line is selected. In addition, each pixel is coupled to each other in a matrix structure. 
     For driving a conventional LCD having the matrix structure, there is generally used a voltage averaging method employing a sequential scanning technique by multiplexing a pixel data. This method may be used without losing any contrast of an image if the LCD device is slowly operated, e.g., an operation speed of the LCD device is about 400 msec. 
     Meanwhile, in a display, which can reproduce a fast moving image or present a fast moving mouse point, like a super twisted nematic (hereinafter, referred as STN) LCD, a multi-line scanning (MLS) technique is generally used. A gray scale of an image in the STN LCD is adjusted by a pulse width modulation (PWM) method. 
     In addition, there is a frame rate control (FRC) method for adjusting the gray scale of the image. In the FRC method generally used as a kind of driving method for use in the LCD device, a frame has a plurality of sub-frames. The FRC method has an advantage of implementation cost. However, in the FRC method, the more the gray scale is segmented minutely, the more the frame should have sub-frames. As a result, the operation speed of the LCD device using the FRC method is decreased. Namely, the LCD device using the FRC method is not proper for reproducing the fast moving image. 
       FIG. 1  is a block diagram describing a conventional driver having a PWM selector using the PWM method for adjusting the gray scale of the image. 
     As shown, the PWM selector is coupled to a PWM signal generator  100  and a plurality of decoders  110 _ 1  to  110 _n. The PWM signal generator  100  generates 16 gray scale pulses, wherein each of the 16 gray scale pulses has a different pulse width from each other. Each of the plurality of decoders  110 _ 1  to  110 _n receives a 4-bit data code, e.g., DIN 1 &lt;3:0&gt;. Each decoder converts an inputted 4-bit data code into a 16-bit scale code. The PWM selector outputs a selected gray scale pulse among the 16 gray scale pulses in response to the 16-bit scale code outputted from each decoder, e.g.,  110 _ 1 . In addition, a buffer  130  is used for delivering the 16 gray scale pulses to the PWM selector. 
     There are N number of channels CH 1  to CHn. Herein, N is a positive integer. Each channel, e.g, CH 1  is coupled to 16 number of selecting units  120   a  to  120   p  included in the PWM selector. Each channel is driven by a gray scale pulse selected by the 16-bit gray scale. Each channel is corresponding to each pixel column of panel in the LCD device. 
     Herein, the PWM selector is used in the case that an image data code is 4-bit; however, the PWM selector can be modified in response to the bit number of the image data code. 
       FIG. 2  is waveforms describing the plurality of gray scale pulses and an operation of the PWM selector shown in  FIG. 1 . 
     As illustrated, there are 16 gray scale pulses P&lt;0&gt; to P&lt;15&gt; each having a different pulse width. If a first image data code DIN 1  is “0011,” the PWM selector outputs a third gray scale pulse P&lt;2&gt; matched with “0011” to a first channel CH 1 . Likewise, if a (n−1) th  image data code DIN (n−1)  is “0110,” the PWM selector outputs a sixth gray scale pulse P&lt;5&gt; and, if a n th  image data code DIN n  is “1111,” the PWM selector outputs a 16 th  gray scale pulse P&lt;15&gt;, where n is the number of channels. 
     As described above, in the PWM method for adjusting the gray scale of the image, there should be the number of PWM gray scale pulses in response to the bit number of the image data code. Namely, the number of PWM gray scale pulses is 2 N  if the bit number of the image data code is N. For example, if the image data code is 4-bit, the number of PWM gray scale pulses is 2 4  and, if the image data code is 12-bit, the number of PWM gray scale pulses is 2 12 . 
       FIG. 3  is a block diagram depicting a conventional RGB interface applied with a PWM selector using the PWM method. 
     As shown, the PWM selector for outputting each color gray scale code to each channel is coupled to a plurality of decoders  310 _ 1  to  310 _n and three PWM generators  300   a  to  300   c , where n is the number of channels. In the conventional RGB interface, each channel, e.g., CH 1  is constituted with three color sub-channels, e.g, R&lt;1&gt;, G&lt;1&gt; and B&lt;1&gt;. Also, each decoder, e.g.,  310 _ 1  includes three sub-decoders  310 _ 1 A,  310 _ 1 B and  310 _ 1 C. Each sub-decoder, e.g.,  310 _ 1 A serves as each 4-bit color data, e.g., RI&lt;1&gt; of an image data, e.g., DATA 1 . Three PWM generators  300   a  to  300   c  respectively generate three color gray scale pulses PR&lt;0:15&gt;, PG&lt;0:15&gt; and PB&lt;0:15&gt;, wherein each color gray scale pulse, e.g., PR&lt;0:15&gt; includes 16 gray scale pulses PR&lt;0&gt; to PR&lt;15&gt; each having a different pulse width in response to the 4-bit color data, e.g., RI&lt;1&gt; of the image data, e.g., DATA 1 . Each color gray scale pulse is transmitted through each buffer, e.g.,  330   a.    
     Herein, each channel also corresponds to each pixel column in the LCD device. Each channel, e.g., CH 1  includes three color sub-channels, R&lt;1&gt;, G&lt;1&gt; and B&lt;1&gt;. In addition, each color data of the image data is 4-bit. 
     Hereinafter, an operation of the PWM selector is described in detail. The decoder, e.g.,  310 _ 1  converts each 4-bit color data of the image data code into each 16-bit color scale code. In response to each 16-bit color scale code outputted from each decoder, the PWM selector outputs a selected gray scale pulse among the 16 gray scale pulses of each color gray scale pulse to each channel. 
     As described above, in the PWM method for adjusting the gray scale of the image, there should be the number of PWM gray scale pulses in response to the bit number of the image data code, e.g., there should be 16 PWM gray scale pulses if the bit number of the image data code is 4. In addition, if each channel has three color sub-channels R, G and B, the number of PWM gray scale pulses is increased three times. As a result, in case the bit number of the image data code is N and each channel has K color sub-channels, there should be K×2 N  number of PWM gray scale pulses. 
     Therefore, the higher quality image is reproduced, i.e., the more bits of the image data code is needed, the more wires are needed for transmitting a plurality of PWM gray scale pulses in response to the bit number of the image data code. In addition, it is difficult to integrate an apparatus using the PWM method, and current consumption is greatly increased due to a large number of wires. 
     SUMMARY OF INVENTION 
     It is, therefore, an object of the present invention to provide a multi-gradation display apparatus using pulse width modulation (PWM) which can enhance integration of the same and reduce current consumption by preventing an increase in the number of PWM gray scale pulses corresponding to an increase in the bit number of an image data code. 
     In accordance with an aspect of the present invention, there is provided a multi-gradation display apparatus using a pulse width modulation (PWM) method including a plurality of channels; a plurality of input blocks for outputting a plurality of N-bit image code in response to a gray scale of an image, wherein N is a positive integer; a pulse width modulation generator for outputting first and second gray scale pulses, each having 2 N  edges in response to the bit number of N-bit image code; and a plurality of count controllers, each selecting an edge of the first or second gray scale pulse in response to the N-bit image code to output a driving pulse having a pulse width from an initial point to the edge of the first or second gray scale pulse to the plurality of channels, wherein the second gray scale pulse is complementary with the first gray scale pulse. 
     In accordance with another aspect of the present invention, there is provided a plurality of channels; a plurality of input means for outputting a plurality of N-bit image code in response to a gray scale of an image, wherein N is a positive integer; a pulse width modulation generator for outputting a gray scale pulse having 2 N  edges in response to the bit number of N-bit image code; and a plurality of count controllers, each selecting an edge of the gray scale pulse in response to the N-bit image code to output a driving pulse having a pulse width from an initial point to the edge of the first or second gray scale pulse to the plurality of channels. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram describing a conventional pulse width modulation (hereinafter, referred as a PWM) selector using the PWM method for adjusting the gray scale of the image; 
         FIG. 2  shows waveforms describing the plurality of gray scale pulses and an operation of the PWM selector shown in  FIG. 1 ; 
         FIG. 3  is a block diagram depicting a conventional RGB interface applied with a PWM selector using the PWM method; 
         FIG. 4  is a block diagram of a driver using the PWM method for adjusting a gray scale of an image in accordance with an embodiment of the present invention; 
         FIG. 5  shows waveforms describing an operation of the count counter shown in  FIG. 4 ; and 
         FIG. 6  is a block diagram depicting an RGB interface applied with the driver using the PWM method in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF INVENTION 
     Hereinafter, a multi-gradation display apparatus using a pulse width modulation (hereinafter, referred as a PWM) method will be described in detail with reference to the accompanying drawings. 
       FIG. 4  is a block diagram of a driver using the PWM method for adjusting a gray scale of an image in accordance with the present invention. 
     As shown, the driver is provided with a PWM signal generator  400 , first and second buffers  430   a  and  430   b  and a plurality of counter controllers  420 _ 1  to  420 _n. 
     The PWM signal generator  400  generates first and second gray scale pulses P&lt;a&gt; and P&lt;b&gt;, wherein the first gray scale pulse P&lt;a&gt; is complementary with the second gray scale pulse P&lt;b&gt;. Also, the first gray scale pulse P&lt;a&gt; is a signal resulting from the logical XOR operation of a plurality of PWM gray scale pulses. Herein, the number of PWM gray scale pulses is based on the bit number of an image data code. If the bit number of an image data code is K, the number of PWM gray scale pulses is 2 K . As a result, if the number of PWM gray scale pulses is 2 K , the number of rising and falling edges in the first gray scale pulse P&lt;a&gt; is 2 K . 
     The first and second buffers  430   a  and  430   b  deliver the first and second gray scale pulses P&lt;a&gt; and P&lt;b&gt; to the plurality of count controllers  420 _ 1  to  420 _n. Herein, the number of count controllers is based on the number of channels, i.e., the number of pixel columns in the display. 
     The count controller selects a rising edge of the first or second gray scale pulse P&lt;a&gt; and P&lt;b&gt; in response to the image data code and outputs a gray scale pulse which has a pulse width from an initial point to the selected rising edge to the channel. 
     Herein, in  FIG. 4 , the image data code is 4-bit, i.e., K is 4; however, the driver using the PWM method can be applied in the case when the bit number of the image data code is K′, i.e., another positive integer. 
       FIG. 5  shows waveforms describing an operation of the count counter in accordance with an embodiment of the present invention. 
     As shown, because of the complementary first and second gray scale pulses P&lt;a&gt; and P&lt;b&gt;, the count controller, e.g.,  420 _ 1  counts a rising edge of the first gray scale pulse P&lt;a&gt; if the last bit, e.g., DIN 1 &lt;0&gt; of the image data code is. “1”. Otherwise, the count controller, e.g.,  420 _ 1  counts a rising edge of the second gray scale pulse P&lt;b&gt; if the last bit, e.g., DIN (n−l) &lt;0&gt; of the image data code is “0”. Namely, a least significant bit (LSB) of the image data code determines which of the gray scale pulses is counted by the count controller. Herein, the LSB is the last bit of the image data code. 
     In detail, if a first image data code DIN 1 &lt;3:0&gt; is inputted as “0011”, its LSB is “1”. As a result, a first count controller  420 _ 1  counts a second rising edge {circle around ( 2 )} of the second gray scale pulse P&lt;b&gt;. Then, the first count controller  420 _ 1  outputs a first gray scale pulse which has a pulse width from an initial point to the second rising edge {circle around ( 2 )} of the second gray scale pulse P&lt;b&gt; to a first channel CH 1 . 
     In the case where a (n−1) th  image data code DIN (n−1) &lt;3:0&gt; is inputted as “0110”, its LSB is “0”. As a result, a (n−1) th  count controller  420 _(n−1) counts a third rising edge {circle around ( 3 )} of the first gray scale pulse P&lt;b&gt;. Then, the (n−1) th  count controller  420 _(n−1) outputs a (n−1) th  gray scale pulse which has a pulse width from an initial point to the third rising edge {circle around ( 3 )} of the first gray scale pulse P&lt;a&gt; to a (n−1) th  channel CH(n−1). 
     In the case of an n th  image data code DIN n &lt;3:0&gt; inputted as “1111”, an nth gray scale pulse is determined by n th  count controller  420 _n operating in a similar manner of above first count controller  420 _ 1 . 
     As described above, a display apparatus using the PWM method for adjusting a gray scale of an image in accordance with the present invention needs only two gray scale pulses, e.g., P&lt;a&gt; and P&lt;b&gt;, not a plurality of gray scale pulses in response to the bit number of the image data code. If the display apparatus uses a 4-bit image data code, there should be 2 4 , i.e., 16 gray scale pulses. However, in the present invention, there are only two gray scale pulses. 
     In addition, for determining a gray scale pulse, the count controller can count not only a rising edge of the two gray scale pulses but also a falling edge of the two gray scale pulses. Moreover, if there is one gray scale pulse outputted from a PWM signal generator, the count controller can count the rising and falling edges of the gray scale pulse. 
       FIG. 6  is a block diagram depicting an RGB interface applied with the driver using the PWM method in accordance with the present invention. 
     As shown, in the driver, there are a plurality of PMW color signal generators  600   a  to  600   c , a plurality of 2-bit buffers  630   a  to  630   c  and a plurality of unit count controllers  620 _ 1 A to  620 _ 1 C, . . . ,  620 _nA to  620   n C. Herein, the number of PMW signal generators or buffers is based on the number of colors provided to each channel for reproducing the inputted image. Generally, three colors R, G and B are used. Also, the number of count controllers is based on the number of channels, i.e., the number of pixel columns in the display apparatus. 
     The plurality of PWM color signal generators  600   a  to  600   c  outputs two color gray scale pulses respectively. One of the two color gray scale pulses is complementary with the other. Also, each color gray scale pulse is a signal resulted from the logical XOR operation of a plurality of PWM gray scale pulses. Herein, the number of PWM gray scale pulses is based on the bit number of an image data code. As a result, each color gray scale pulse has the number of rising and falling edge in response to the bit number of the image data code. Each color gray scale pulse is transmitted through each 2-bit buffer, e.g.,  630   a . In addition, each color data, e.g., RI&lt;1&gt; of each image data, e.g.,  610 _ 1  is 4-bit. 
     Each channel corresponds to each pixel column in the display apparatus. Also, each channel, e.g., CH 1  includes three color sub-channels, R&lt;1&gt;, G&lt;1&gt; and B&lt;1&gt;. 
     Herein, since an operation of each unit count controller, e.g.,  620 _ 1 A is the same to that of the count controller, e.g.,  420 _ 1  shown in  FIG. 4 , there is omitted a description of the operation of each unit count controller. 
     As described above, in the RGB interface applied with the driver using the PWM method in accordance with the present invention, each PWM color signal generator outputs each complementary color gray scale pulse to each unit count controller. As a result, the RGB interface can prevent an increase of the number of PWM gray scale pulses corresponding to increasing the bit number of an image data code. 
     Therefore, though the higher quality image is reproduced, i.e., the more bits of the image data code are needed, the number of wires can be reduced in the present invention. As a result, it is enhanced to integrate the display apparatus using the PWM method, and current consumption is rapidly reduced by decreasing the number of wires. 
     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.