Patent Publication Number: US-2015085144-A1

Title: Dual video graphics array connectors testing system

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to testing systems, and particularly to a dual Video Graphics Array (VGA) connectors testing system. 
     2. Description of Related Art 
     More and more electronic devices have two VGA connectors connecting to other video devices, such as televisions. In quality tests, in order to improve testing efficiency, two displays are required to connect the two VGA connectors respectively at same time, which increases the testing cost. 
     Therefore, it is desirable to provide a dual VGA connectors testing system that can overcome the limitations described. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a functional block diagram of a dual VGA connectors testing system in accordance with an exemplary embodiment. 
         FIGS. 2-4  are a circuit diagram of the dual VGA connectors testing system of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the disclosure will be described with reference to the drawings. 
       FIGS. 1-4  show a dual VGA connectors testing system  100 , according to an exemplary embodiment. The dual VGA connectors testing system  100  is connected between two first VGA female connectors  201  mounted on a main board  200  and a second VGA female connector  301  of a video device  300 . The VGA connector is a three-row 15-pin D-sub connector, each row has five pins. The VGA connector has three RGB color signal terminals, two scan synchronizing signal terminals, two address signal terminals, two bus signal terminals, and five GND signal terminals. 
     The dual VGA connectors testing system  100  includes an exchanging module  10  and a controlling module  20  connected to the exchanging module  10 . 
     The exchanging module  10  includes a RGB signal unit  11 , a scanning and controlling signal unit  12 , and an address signal unit  13 . 
     The RGB signal unit  11  includes a first group of RGB signal inputting terminals  111 , a second group of RGB signal inputting terminals  112 , a group of RGB signal outputting terminals  113 , and a first controlling terminal  114 . The RGB signal unit  11  is an exchanging chip U1. The first group of RGB signal inputting terminals  111  are three pins 1B1, 2B1, and 3B1 of the exchanging chip U1. The second group of RGB signal inputting terminals  112  are three pins 1B2, 2B2, and 3B2 of the exchanging chip U1. The RGB signal outputting terminals  113  are three pins 1A, 2A, and 3A of the exchanging chip U1. The first controlling terminal  114  is a pin S of the exchanging chip U1. The pins 1A, 2A, and 3A are connected with the pins 1B1, 2B1, and 3B1 respectively and disconnected with the pins 1B2, 2B2, and 3B2 respectively when the pin S is input a first signal, such as +5 V (volt). The pins 1A, 2A, and 3A are connected with the pins 1B2, 2B2, and 3B2 respectively and disconnected with the pins 1B1, 2B1, and 3B1 respectively when the pin S is input a second signal, such as 0 V (volt). 
     The scanning and controlling signal unit  12  includes a first group of scanning and controlling signal inputting terminals  121 , a second group of scanning and controlling signal inputting terminals  122 , a group of scanning and controlling signal outputting terminals  123 , and a second controlling terminal  124 . The scanning and controlling signal unit  12  is an exchanging chip U2. The first group of scanning and controlling signal inputting terminals  121  are pins 1B1, 2B1, 3B1, and 4B1 of the exchanging chip U2. The second group of scanning and controlling signal inputting terminals  122  are pins 1B2, 2B2, 3B2, and 4B2 of the exchanging chip U2. The scanning and controlling signal outputting terminals  123  are pins 1A, 2A, 3A, and 4A of the exchanging chip U2. The second controlling terminal  124  is a pin S of the exchanging chip U2. The pins 1A, 2A, 3A, and 4A are connected with the pins 1B1, 2B1, 3B1, and 4B1 respectively and disconnected with the pins 1B2, 2B2, 3B2, and 4B2 respectively when the pin S is input a first signal, such as +5 V (volt). The pins 1A, 2A, 3A, and 4A are connected with the pins 1B2, 2B2, 3B2, and 4B2 respectively and disconnected with the pins 1B1, 2B1, 3B1, and 4B1 respectively when the pin S is input a second signal, such as 0 V (volt). 
     In the embodiment, the pins 1A, 2A, 1B1, 2B1, 1B2, and 2B2 of the exchanging chip U2 are used for transmitting scanning signals, the pins 3A, 4A, 3B1, 4B1, 3B2, and 4B2 are used for transmitting controlling signals. 
     The address signal unit  13  includes a first group of address signal inputting terminals  131 , a second group of address signal inputting terminals  132 , a group of address signal outputting terminals  133 , and a third controlling terminal  134 . The address signal unit  13  is an exchanging chip U3. The first group of address signal inputting terminals  131  are pins 1B1 and 2B1 of the exchanging chip U3. The second group of address signal inputting terminals  132  are pins 1B2 and 2B2 of the exchanging chip U3. The address signal outputting terminals  133  are pins 1A and 2A of the exchanging chip U3. The third controlling terminal  134  is a pin S of the exchanging chip U3. The pins 1A and 2A are connected with the pins 1B1 and 2B1 respectively and disconnected with the pins 1B2 and 2B2 respectively when the pin S is input a first signal, such as +5 V (volt). The pins 1A and 2A are connected with the pins 1B2 and 2B2 respectively and disconnected with the pins 1B1 and 2B1 respectively when the pin S is input a second signal, such as 0 V (volt). 
     In the embodiment, types of the exchanging chips U1, U2, and U3 are same, and the exchanging chips U1, U2, and U3 are arrayed on a circuit board (not shown). 
     The first group of RGB signal inputting terminals  111 , the first group of scanning and controlling signal inputting terminals  121 , and the first group of address signal inputting terminals  131  are connected to a first VGA male connector (not shown) coupled to the first VGA female connectors  201 . The second group of RGB signal inputting terminals  112 , the second group of scanning and controlling signal inputting terminals  122 , and the second group of address signal inputting terminals  132  are connected to a second VGA male connector (not shown) coupled to the other first VGA female connectors  201 . The RGB signal outputting terminals  113 , the scanning and controlling signal outputting terminals  123 , and the address signal outputting terminals  133  are connected to a third VGA male connector (not shown) coupled to the second VGA female connector  301 . 
     In the embodiment, the pins 1B1, 2B1, and 3B1 of the exchanging chip U1, the pins 1B1, 2B1, 3B1, and 4B1 of the exchanging chip U2, and the pins 1B1 and 2B1 of the exchanging chip U3 are connected to the first VGA male connector. The pins 1B2, 2B2, and 3B2 of the exchanging chip U1, the pins 1B2, 2B2, 3B2, and 4B2 of the exchanging chip U2, and the pins 1B2 and 2B2 of the exchanging chip U3 are connected to the second VGA male connector. The pins 1A, 2A, and 3A of the exchanging chip U1, the pins 1A, 2A, 3A, and 4A of the exchanging chip U2, and the pins 1A and 2A of the exchanging chip U3 are connected to the third VGA male connector. 
     The controlling module  20  is connected to the first controlling terminal  114 , the second controlling terminal  124 , and the third controlling terminal  134 . The controlling module  20  outputs the first signal or the second signal to the first controlling terminal  114 , the second controlling terminal  124 , and the third controlling terminal  134 . 
     In the embodiment, the controlling module  20  includes a transistor T 1 , a switch SW 1 , a resistor R 1 . The transistor T 1  includes a collator C 1 , an emitter E 1 , and a base B 1  configured for controlling connection or disconnection between the collator C 1  and the emitter E 1 . The collator C 1  is connected to a power source Vcc via the resistor R 1 . The base B 1  is connected to another power source Vcc via the switch SW 1 . The emitter E 1  is grounded. The collator C 1  is directly connected to the first controlling terminal  114 , the second controlling terminal  124 , and the third controlling terminal  134 . 
     Before testing, the first VGA male connector, the second VGA male connector, and the third VGA male connector are connected to the two first VGA female connectors  201  and the second VGA female connector  301  respectively. The three RGB color signal terminals of two first VGA female connectors  201  are connected to the first group of RGB signal inputting terminals  111  and the second group of RGB signal inputting terminals  112  respectively. The two scan synchronizing signal terminals and the two bus signal terminals of two first VGA female connectors  201  are connected to the first group of scanning and controlling signal inputting terminals  121  and the second group of scanning and controlling signal inputting terminals  122 . The two address signal terminals of two first VGA female connectors  201  are connected to the first group of address signal inputting terminals  131  and the second group of address signal inputting terminals  132 . The RGB signal outputting terminals  113 , the scanning and controlling signal outputting terminals  123 , and the address signal outputting terminals  133  are connected to the second VGA female connector  301 . 
     During test, the controlling module  20  outputs the first signal to the first controlling terminal  114 , the second controlling terminal  124 , and the third controlling terminal  134 . The first VGA female connector  201  connected to the first group of RGB signal inputting terminals  111 , the first group of scanning and controlling signal inputting terminals  121 , and the first group of address signal inputting terminals  131  is connected to the second VGA female connector  301 . Therefore, this first VGA female connector  201  is testing. The controlling module  20  outputs the second signal to the first controlling terminal  114 , the second controlling terminal  124 , and the third controlling terminal  134 . The first VGA female connector  201  connected to the second group of RGB signal inputting terminals  112 , the second group of scanning and controlling signal inputting terminals  122 , and the second group of address signal inputting terminals  132  is connected to the second VGA female connector  301 . Therefore, another first VGA female connector  201  is tested. 
     Particular embodiments are shown and described by way of illustration only. The principles and the features of the present disclosure may be employed in various and numerous embodiments thereof without departing from the scope of the disclosure as claimed. The above-described embodiments illustrate the scope of the disclosure but do not restrict the scope of the disclosure.