Patent Publication Number: US-8988255-B2

Title: Apparatus and method for coding data based on phasor disparity

Description:
FIELD 
     One or more embodiments described herein relate to processing data. 
     BACKGROUND 
     Data terminals are continuously evolving to handle greater market demand. The input/output (IO) units in these terminals generate interference which reduces receiver/transmitter performance. One attempt to reduce interference involves the use of conductive shielding. This approach has proven unsatisfactory for increasing costs, weight, physical size, manufacturing time and complexity. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an example of an electronic terminal. 
         FIG. 2  shows one embodiment of a method for processing data in the terminal. 
         FIGS. 3(   a )- 3 ( c ) show examples of spectral components of pulses representing data bits. 
         FIG. 4  shows an example of reference bit positions for a 4-bit codeword. 
         FIG. 5  shows an example of a plot of phasors generated at the different bit positions. 
         FIG. 6  shows an example of a plot of phasors generated for different codewords. 
         FIG. 7  shows a block coding technique for generating codewords. 
         FIG. 8  shows a phasor diagram produced by block coding. 
         FIG. 9  shows a phasor diagram produced by zero-sum block pair coding. 
         FIG. 10  shows a spectral diagram generated using zero-sum block pair coding. 
         FIG. 11  shows a phasor diagram produced by running sum block coding. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows an example of an electronic terminal  10  for transmitting and receiving data. The terminal may be any one of a variety of portable devices including but not limited to a smart or other type of mobile phone, a media terminal, a media player, a laptop or notebook computer, a personal digital assistant, a camera or camcorder with enhanced capability, a television or monitor, a navigation system, or any one of a number of other portable devices that are capable of transmitting and receiving data. Alternatively, the terminal may be a stationary device such as but not limited to a desktop computer or an audio or speaker system. 
     As shown in  FIG. 1 , the terminal includes a processor  1  for receiving a bit stream from a signal line  6 , a codeword buffer  2  for generating codewords of one or more predetermined bit lengths from the bit stream, and one or more interface units. The bit stream may come from any one of a plurality of applications, functions, or operations to be performed on the terminal. For example, the bit stream may correspond to information transmitted in connection with a voice or video call, a message such as a text or e-mail message, or data generated by an application executed on the terminal. 
     The processor generates codewords from the bits in the bit stream. The processor may be one or more processing or controller chips which performs control functions for the entire terminal, or may perform one or more specially dedicated functions for the terminal such as call, message, or media transmission and management. The processor is controlled by programs stored in a terminal memory, and transmits the codewords to one or more of the interface circuits along an N-bit IO bus, where, for example, N may include or correspond to the number of bits in each codeword. 
     The one or more interface circuits may include a wired interface  3 , a wireless interface  4 , or both, equipped with respective transmitter (Tx) and/or receiver (R) circuits. The codewords transmitted from these circuits may be contained in packets and transmitted according to any one of a variety of communications standards and or protocols. In one application, the wired interface may be a Universal Serial Bus, Ethernet, or other protocol interface used for data transmissions. 
       FIG. 2  shows operations included in one embodiment of a method for processing data in a terminal The terminal may the one shown in  FIG. 1  or another type of terminal. An initial operation includes receiving a bit stream (Block  100 ), which may include bits generated in any of the aforementioned ways. In one illustrative application, the bits correspond to a call or message to be transmitted from a smart phone over the wireless interface. 
     A second operation includes determining a phasor for each bit in the bit stream within a predetermined spectral frequency range that is less than an entire spectral frequency spectrum over which data communications takes place for the terminal. According to one embodiment, the phasor for each bit is determined at only a single spectral frequency. (Block  110 ). 
     Moreover, the phasor for each bit may be determined in a variety of ways. One way begins with the understanding that a single data bit on an IO bus may be spectrally represented by a pulse at a single frequency over time. Each pulse (bit) in a bit stream contributes to the net spectrum of the bit stream waveform, and may be represented by the following Equation (1):
 
 H ( f )= A  sinc( f/BR )× e   −j2πb f/BR    (1)
 
     This meaning of this equation may be explained with reference to  FIGS. 3(   a ) to ( c ). In these figures, A is the pulse amplitude, BR is the bus bit rate, BT is the bit time (inverse of bit rate), and b is the bit location (measured in bit times from zero). 
     In  FIG. 3(   a ), the pulse position is located at an initial time (t=0), the spectral magnitude takes the form of a descending waveform from a peak position at time, t=0, and establishing a minimum at a frequency between BR and 2BR, and the spectral phase is substantially 0°. 
     In  FIG. 3(   b ), the pulse position is located at time, t=BT, the spectral magnitude has essentially the same descending waveform, and the spectral phase is a series of connected descending ramp waveforms (e.g., sawtooth), each ramp waveform spanning a phase range of 360° over a frequency range of one BR. 
     In  FIG. 3(   c ), the pulse position is located at time, t=2BT, the spectral magnitude has the same descending waveform, and the spectral phase is a series of connected descending ramp waveforms, each ramp waveform spanning a phase range of 360° over a frequency range of ½ BR. 
     From these figures and Equation (1), the phasor of a data bit may be defined as the complex vector (a vector in the complex plane) given by the spectral magnitude and phase angle of the bit taken at a single frequency of interest. To assist in the understanding of these phasors, consider the case where a codeword is formed from four bits, where each bit is expressed by a phasor that occupies one of four bit positions (b=0, 1, 2, and 3) as shown in  FIG. 4 . These bit positions may have a spectral magnitude and phase defined by Equations (2) and (3) for a bit rate BR=¼.
 
 H ( f )= A  sinc( f/ 4)× e   −jφ(f)    (2)
 
φ( f )=−π b/ 2   (3)
 
     Given these equations, the phasor at a frequency of one quarter the bit rate for a pulse at time t=0 is shown by arrow X in  FIG. 5 . As shown, this arrow has a magnitude and phase, with the phase lying on the real axis of the plot. For a pulse period of 0 to 3Bt, the phase for the bit at time t=0 corresponds to a bit location b=0 and repeating at this location at bit locations 4, 8, and so on. 
     The phasor of a data bit located at time delayed by one bit time (t=BT) would have an arrow of the same magnitude pointing downward along the imaginary axis of (moving clockwise on) the plot at bit location b=1, 5, and so on. The phasor of a data bit located at a time delayed by two bit times (t=2BT) would have an arrow of the same magnitude pointing along the real axis of the plot at a bit location of b=2, 6, and so on. And, the phasor of a data bit located at a time delayed by three bit times (t=3BT) would have an arrow of a same magnitude pointing upwardly along the imaginary axis of the plot at a bit location of b=3, 7, and so on. 
     The aforementioned phasors are generated based on an illustrative set of parameters for use in generating a 4-bit codeword. In other embodiments, the parameters may change from bit-to-bit, or codeword-to-codeword, to generate phasors of different spectral magnitudes, phases, and/or bit positions. (A 10-bit codeword example will be discussed in greater detail in subsequent figures). 
     Using phasors defined based on the spectral characteristics, pulse positions, and bit positions shown in  FIGS. 3-5 , codewords may be generated from the bits in the bit stream. (Block  120 ). The codewords may be generated in a variety of ways in accordance with embodiments to be described. The manner in which the codewords are generated may either reduce spectral energy and/or achieve some predetermined level of spectral energy for data transmission. 
     When codewords are generated in a way which reduces spectral energy (e.g., compared with other techniques which, for example, use different bases for combining bits to generate codewords), the amount of interference in the terminal may be proportionally reduced, thereby alleviating the need to use conductive shielding. In other embodiments, spectral energy may be adjusted to achieve a different effect. Moreover, the methods described herein may be combined with a conductive shielding technique as previously described. 
     Once the codewords are formed, a phasor may be generated for the codeword at a single frequency in the bit-stream spectrum based on a sum of the phasors of the individual bits comprising the codeword at that frequency. (Block  130 ). The phasors of each bit in the codeword may be summed, for example, in the manner shown by Equation (4). 
                     H   ⁡     (   f   )       =       ∑     b   =   1     n     ⁢           ⁢       x   bk     ⁢     ⅇ       -   ⅈ     ⁢           ⁢   2   ⁢   π   ⁢           ⁢     bf   /   BR                     (   4   )               
wherein x b  represents each bit having a logical value of 0 or 1.
 
       FIG. 6  shows an example of how phasors may be formed for a 4-bit codeword based on a sum of bit phasors defined based on the spectral characteristics, pulse positions, and bit positions shown in  FIGS. 3-5 . As shown in  FIG. 6 , the phasor for each codeword may be represented on a plot having real and imaginary axes. When summing the phasors for each bit, a logical value of 0 for the bit is considered not to have a phasor and a logical value of 1 is considered to have a phasor. Thus, the phasor generated for each code word, in effect, is generated taking only the phasors of the 1-value bits into consideration. 
     The following examples are shown on the plot of  FIG. 6 . The phasors for codewords comprised of the following bits have a zero value for both the real and imaginary components: 0000, 0101, 1010, 1111. This is because the sum of the phasors of these bit values cancel each other out, assuming that the phasor for each 1-value bit has the same magnitude. 
     Consider, for example, the codeword 0101 having 1-bit values at b=1 and b=3 positions. The phasors for these 1-value bits have spectral phase angles at 270° and 90°, respectively, taking the angles for the b values in  FIG. 5  as a reference. When added, the sum of the phase angles equal 360° (or equivalently 0°) and the sum of their spectral magnitudes (being equal but opposite in sign) also equals zero. As a result, the phasor of the codeword 0101 lies at the origin of the plot indicated by circle A, which corresponds to zero spectral energy. The same phasors are generated for codewords 0000, 1010, and 111. 
     The phasors for other codewords are not located at the origin of the plot. For example, the phasors for codewords 0001 and 1011 corresponds to a value in circle B. This phasor has a magnitude corresponding to the length of the arrow pointing to circle B (which represents the magnitude of the phasor for an individual 1-value bit) and a phase angle generated based on the sum of the phase angles for the 1-value bits in these codewords. The phasor for the codeword 0011 is shown within circle C and has a magnitude equal to √2 times the magnitude of the phasor for a 1-value bit and a phase angle of 135°. The phasors for other codewords may be plotted using these principles. 
     In the illustrative embodiment of  FIG. 6 , the phasors for each bit are assumed to have essentially the same spectral magnitude. However, in other embodiments, the phasors for each bit value may have different values, which will be reflected in the phasors of the codewords generated from a sum of the phasors for these bits. Generating codewords based on phasor summation of the bits comprising the codeword provides a computationally efficient way of controlling the spectral energy of the data to be transmitted. According to one embodiment, this method may be used to control the amount of interference that is ultimately generated in the terminal. 
     Once the phasors for the codewords generated at one frequency are determined, the codewords may be transmitted through an interface, such as either interface shown in  FIG. 1 . Examples of how the codewords may be generated in Block  120  in  FIG. 2  will now be discussed. 
     Block Coding 
     Block coding may be performed in a variety of ways. One way, referred to as Minimum-Magnitude Block Coding, involves performing a one-to-one mapping of data words of a predetermined length to codewords. Referring to  FIG. 7 , this coding technique includes calculating the angle of the phasor for each bit based on Equation 5. (Block  210 ).
 
θ k= 2 πkf′  for  k= 1 to  n  and  f′=f   r   /f   b    (5)
 
where n is the number of bits that comprise each codeword, f r  is the single radio frequency, and f b  is the data bit rate. Next, the coordinates of the phasor for each bit is calculated using Equation 6. (Block  220 ).
 
R k =Cos θ k  and I k =Sin θ k  for k=1 to n   (6)
 
     The codeword power spectral densities (PSDs) are computed from Equation 7. (Block  230 ). 
     
       
         
           
             
               
                 
                   
                     
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     Data words are then mapped in one-to-one correspondence with codewords having one or more of a predetermined number of the lowest PSDs taken from the Pc values computed by Equation 7. (Block  240 ). This one-to-one mapping may be performed based on one of a variety of criteria. 
     One criteria involves mapping codewords having the smallest phasor magnitude at a predetermined mitigation frequency out of all possible codewords to data words. This approach creates a spectral notch which can be used as a basis for achieving a certain level of performance, which, for example, may be to transmit the data at a minimum or reduced spectral energy as a way of limiting interference. 
     Another criteria involves mapping the codewords that have an equal values (or which are nearly equal to within a predetermined tolerance) in all bit positions, or where a sum of codewords have an equal or near equal value in all bit positions. This may minimize or in some cases even eliminate spikes in the spectral waveform. 
     Another criteria involves mapping codewords having a sum of phasor bit amplitudes that are lower than a predetermined threshold or which are otherwise minimized. 
       FIG. 8  shows a plot of phasors (shown as points) generated for codewords according to the block coding technique performed based on the first criteria. In this plot, the codewords that appear within the circle are selected to be mapped to the data words. 
     Zero-Sum Pair Block Coding 
     Another type of block coding is referred to as zero-sum pair block coding. This type of coding involves performing a one-to-two mapping, where each data word is associated with a unique code pair and mapped to the codewords of that pair in an alternating manner. Also, in this approach, some data words may be mapped in one-to-one correspondence to zero-magnitude codewords. This approach may also be performed so that no codeword belongs to more than one code pair. 
     In accordance with one embodiment, the members of each pair may be chosen from minimum magnitude codewords such that a phasor sum of each pair is reduced by some predetermined amount or minimized such that the sum is near or exactly zero, if possible. Moreover, codewords may be optionally selected to minimize the phasor sum over all codewords, in a case where the sum over every pair is not zero. 
       FIG. 9  shows an example of a phasor diagram that may be generated according to this method. In this example, a number of individual codewords (which are not paired) have and therefore will be mapped to phasors with zero or near-zero magnitude. Phasors of this type are shown within circle R in the phasor diagram. 
     Other and/or remaining codewords are selected in pairs so that the phasors corresponding to each of the pairs will have a net-zero magnitude. This may be accomplished, for example, by locating phasors for individual codewords that have opposing magnitudes and phase angles, pairing them, and then generating data words based on those pairs. Each data word is based on two codewords to form a one-to-two mapping. Examples of phasor pairs are shown in circles S 1 , S 2 , and S 3  in the phasor diagram. Additionally, or alternatively, the method may be implemented so that each time a data word mapped to one of these pairs of circles, the choice of which codeword is used may alternate so that the phasor contribution for that codeword cancels to zero on average. 
       FIG. 10  shows an example of a spectral waveform diagram that may be generated using zero-sum block pair coding for a 3-bit to 4-bit codeword mapping for at a single radio frequency of one quarter the bit rate (or which equivalently may be produced for any odd multiple of this frequency). As shown in this diagram, two notches are generated at normalized frequencies of approximately 0.25 and 0.75. The notches generated by phasor cancellation in this type of coding indicates that the IO bus energy may be reduced by more than 10 dB or more in this example. 
     Running Sum Block Coding 
     Another type of block coding is referred to as running sum block coding. The type of coding involves performing a one-to-p mapping (p&gt;1), where each data word is associated with a unique code group having p codewords and mapped to a codeword in the group which reduces or minimizes a running signal phasor (within the receiver&#39;s bandwidth). In implementing this method, no codeword may belong to more than one code group. 
     Also, the codewords in each group may be chose from minimum magnitude codewords, such that their phasor sum in reduced or minimized (and made to be zero, if possible). 
     In performing this type of coding, some data words may optionally be mapped in one-to-one correspondence to zero magnitude codewords. Also, the codewords may be selected to that their corresponding phasors are spaced at predetermined intervals (or even equally spaced) on a common circle in the phasor diagram. In an equal spacing application, this would require the selected phasors in each group to have the same or similar magnitude with 2π/p radians between each codeword and an adjacent or nearest codeword in either direction on or near the circle). 
       FIG. 11  shows an example of a phasor diagram that may be generating using this type of coding. In this example, one data word may be mapped to four possible codewords (p=4). The phasors for these four codewords are shown in circles T 1  to T 4  in the diagram. If the running phasor of the data stream up to the point when the data word corresponding to the phasors in these circles lies in a given quadrant, then the codeword having a phasor in the opposite quadrant is chosen along with another pair of opposing phasors that lie along or substantially along the circle, to thereby generate a phasor for the 4-codeword group that is reduced or effectively canceled out. This group is then mapped to a data word to be transmitted. 
     Other types of coding may be used for purposes of mapping data words to codewords. One example includes bit stuffing, where stuff or dummy bits are chosen to minimize a running phasor sum within the bandwidth of a receiver or transmitter. In one embodiment, the stuff bits (e.g., non-information bits) may be inserted onto the IO bus during existing gaps in the data stream, which may include one or more of during a bus idle state or where inter-packet gaps take place. 
     Another type of coding is referred to as running phase disparity. According to this approach, data is encoded as a running stream in a manner, for example, similar to a data scrambler but based on rules which generate one or more notches in the spectrum at a predetermined radio frequency where the codewords/phasors are generated. This approach is different from an approach taken to so-called “whiten” the data spectrum. 
     Another type of coding is referred to as parallel-serial coding. According to this approach, data is encoded across the IO bus width, as well as in time, to improve coding performance. An example of parallel radio frequency interference (RFI) encoding involves encoding single-ended lines to fully differential lines. 
     The aforementioned embodiments may be implemented in software, hardware, or a combination thereof. When implemented at least partially in software, a program may be stored in the terminal to control operation of the processor, which, for example, may considered to encompass one or more terminal chips. The program may be stored on a computer-readable medium such as but not limited to a storage device or memory located within or coupled to the terminal, and may include code for performing the operations included in various embodiments of the method described herein. 
     In accordance with one or more of the aforementioned embodiments, the spectral energy may represent the spectral energy of the codewords (and/or data words formed from the codewords) transmitted on an IO bus. In other embodiments, the codewords or data words may be transmitted on another type of bus or signal line. While an IO bus may be considered to be an internal feature of a terminal or apparatus including or which perform the embodiments described herein, in other embodiments the bus or signal lines carrying the codewords for which spectral energy and interference are to be reduced may be coupled to and located externally from the apparatus or terminal. One non-limiting example contemplates the bus as being a Universal Serial Bus (USB) or other type of external interface. 
     Moreover, the codewords generated in accordance with one or more embodiments described herein may be formed independently from a waveform shape of the bits included in the codeword. Thus, in the case where different bits in the stream have different pulse or waveform shapes, the differences in these shapes will not adversely affect or complicate codeword formation. 
     Moreover, different bit pulse or waveform shapes may have different spectral characteristics, but one or more embodiments described herein may generate codewords irrespective and independent of these differing spectral characteristics because the spectral magnitude of the phasors generated for the codeword bits at any single frequency within a transmission spectrum may be independent of the pulse location in time, and the spectral phase shift at any single frequency of the spectrum may be linearly related to the pulse location in time. 
     One or more embodiments described herein may specifically be applied within a smart phone which operates based on multiple (e.g., 10) separate radio bands with hundreds of possible radio channels. The embodiments described herein may be separately applied to control the transmission of data within respective ones of these bands and channels. Moreover, the criteria (e.g., spectral frequency ranges of the phasors (e.g., the circles in the phasor diagrams)) may be different from band-to-band or even from channel-to-channel based on predetermined information stored in the terminal or apparatus. 
     Any reference in this specification to an “embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments. The features of any one embodiment may be combined with features of one or more other embodiments to form new embodiments. 
     Furthermore, for ease of understanding, certain functional blocks may have been delineated as separate blocks; however, these separately delineated blocks should not necessarily be construed as being in the order in which they are discussed or otherwise presented herein. For example, some blocks may be able to be performed in an alternative ordering, simultaneously, etc. 
     Although the present invention has been described herein with reference to a number of illustrative embodiments, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without departing from the spirit of the invention. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.