Patent Publication Number: US-4731761-A

Title: Semiconductor memory

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an address decoder of a semiconductor memory, and particularly to a structure of an address decoder for a CMOS type dynamic RAM having static column function. 
     2. Description of the Prior Art 
     An address decoder for selecting one memory cell from a memory cell array included in a semiconductor memory is formed of a plurality of transistors, which are connected in series or in parallel and are switch-controlled by address signals. 
     Recently, a semiconductor memory has come to be implemented in a large capacity, increasing the number of bits required for address signals, so that the number of transistors forming an address decoder must be increased correspondingly. This increases the load capacitance of an address signal line, so that the speed of operation of an address decoder is greatly limited. On the other hand, this increases the area of device region required for forming an address decoder on a semiconductor chip. 
     In order to solve the above described problems, an address.predecoding method such as shown in, e.g. Japanese Patent Laying-Open Gazette No. 3289/1982 has been proposed. 
     FIG. 1 shows one example of a structure of a conventional address decoder according to the address predecoding method. In FIG. 1, a conventional address decoder comprises an address buffer circuit 1 for receiving an externally applied address input signals Ext. Ai (i=0,1,...,5) to output the complementary address signal Ai, Ai a predecoder circuit 2 composed of four 2-input NAND gates for receiving and predecoding address signals A 2j , A 2j , A 2j+1 , and A 2j+1 , from corresponding two address buffer circuits 1 to output intermediate signals Z 4j , Z 4j+1 , Z 4j+2  and Z 4j+3  and, an NAND type unit decoder 3 composed of three parallel-connected p channel MOS transistors P 11  ˜P 13  and three series-connected n channel MOS transistors N 11  ˜N 13  for receiving and decoding a part of the intermediate signals from all of the predecoder circuits 2 to output a selection signal S k  (k=0,...,63). V CC  denotes the positive supply potential and V SS  denotes the negative supply potential. 
     The operation will now be described with reference to FIG. 1. The address buffer circuit 1 receives an external address input signal Ext.Ai and applies complementary address signals Ai, Ai to the predecoder circuit 2. The predecoder circuit 2 receives the address signals A 2j , A 2j , A 2j+1  and A 2j+1  and outputs the intermediate signals Z 4j , Z 4j+1 , Z 4j+2 , and Z 4j+3  which satisfy the following equations (1)˜(4). 
     
         Z.sub.4j =A.sub.2j ·A.sub.2j+1                    ( 1) 
    
     
         Z.sub.4j+1 =A.sub.2j ·A.sub.2j+1                  ( 2) 
    
     
         Z.sub.4j+2 =A.sub.2j ·A.sub.2j+1                  ( 3) 
    
     
         Z.sub.4j+3 =A.sub.2j ·A.sub.2j+1                  ( 4) 
    
     where, j =0, 1, 2. 
     The unit decoder 3 receives a predetermined part of the intermediate signals Z 0  ˜Z 11  from the predecoder circuit 2 (one from each of the predecoder circuits, i.e.; three signals in total) evaluates the negative logical product thereof and outputs a selection signal S k  (k=0, ...63). For example, a unit decoder receiving the intermediate signals Z 0 , Z 4  and Z 8  outputs a selection signal S 0  through the operation shown by the following equation (5). ##EQU1## 
     Accordingly, when the address signals A 0  ˜A 5  are all &#34;L&#34;, the selection signal S 0  becomes &#34;L&#34; and a signal line connected to the unit decoder output is selected. 
     FIG. 2 shows another structure of a conventional address decoder according to the predecoding method. 
     Different from the structure of FIG. 1, the predecoder circuit 4 for receiving and predecoding the address signals A 2j , A 2j , a 2j+1  and A 2j+1  (j=0,1,2) to output an intermediate signal is composed of four 2-input NAND gates in the structure of FIG. 2. The unit decoder 5 for receiving and decoding a predetermined set of three intermediate signals from all intermediate signals to output a selection signal is composed of a 3-inputs and 1-output NOR circuit comprising three series-connected p channel MOS transistors and three parallel-connected n channel MOS transistors. Namely, in this structure, the predecoder circuit 4 outputs active low intermediate signals Z 4j , Z 4j+1 , Z 4j+2 , and Z 4j+3 . On the other hand, the NOR type unit decoder 5 outputs an active high selection signal S k  (k=0,...63) in response to the applied intermediate signal. 
     The operation will now be described with reference to FIG. 2. 
     The predecoder circuit 4 receives the address signals A j , A j , A j+1  and A j+1  from the address buffer circuit 1, evaluates respective negative logical products and outputs intermediate signals Z 4j , Z 4j+1 , Z 4j+2  and Z 4j+3  which satisfy the following equations (6)˜(9). 
     
         Z.sub.4j =A.sub.2j ·A.sub.2j+1 =A.sub.2j +A.sub.2j+1 ( 6) 
    
     
         Z.sub.4j+1 =A.sub.2j ·A.sub.2j+1 =A.sub.2j +A.sub.2j+1 ( 7) 
    
     
         Z.sub.4j+2 =A.sub.2j ·A.sub.2j+1 =A.sub.2j +A.sub.2j+1 ( 8) 
    
     
         Z.sub.4j+3 =A.sub.2j ·A.sub.2j+1 =A.sub.2j +A.sub.2j+1 ( 9) 
    
     where, j=0, 1, 2. 
     The unit decoder 5 receives one predetermined intermediate signal from each of the predecoder circuits 4 (three intermediate signals in total), evaluates negative logic sum thereof and outputs a selection signal S k  (k=0, . . . 63). For example, a unit decoder receiving intermediate signals Z 0 , Z 4 , and Z 8  outputs a selection signal S 0  which satisfies the following equation (10). ##EQU2## Therefore, when address signals A 1  ˜A 5  are all &#34;L&#34;, this unit decoder only is selected and the selection signal S 0  becomes &#34;H&#34;. Accordingly, only the signal line for receiving the selection signal S 0  is selected. 
     As described above with reference to FIGS. 1 and 2, in an address decoder using the predecoding method, a unit decoder for decoding 6-bit address information A 0  ˜A 6  is composed of a 3-input NAND circuit or 3-input NOR circuit. If the predecoding method is not used, a unit decoder for decoding the 6-bit address informtion must be composed of 6-input NAND or NOR circuit. Accordingly, by employing the predecoding mehtod, the number of elements required for composing a unit decoder can be decreased to 1/2. Consequently, the number of element connected to the address information line becomes a half, so that the load capacitance on the address information line is greatly decreased, enabling the rapid operation of address decoding. In addition, due to the decrease of the number of elements the areas of element region forming the address decoder can be reduced. 
     However, in the conventional predecoding method, if the unit decoder is composed of a NAND circuit, the predecoder must output NOR outputs (i.e., active-high signal) and if the unit decoder is an NOR circuit, the predecoder must output NAND outputs (i.e., active-low signal) due to the above described circuit structure. 
     Recently, a DRAM (dynamic random access memory) having static column function has becn developed in order to improve the access time of a semiconductor memory. Details of the static column function is disclosed in F. Baba et al., &#34;A 35 ms 64k Static Column DRAM&#34;, ISSCC Digest of Technical Papers, Feb. 1983, pp.64-65 and F. Baba et al., Nikkei Electronics 1983, vol. 9-12, pp. 153-174. Therefore, the description is omitted. 
     In the CMOS type DRAM having static column function, the column decoder and not the row decoder requires the static operation. Therefore, in view of the rapidity of the decoder and the number of elements forming the decoder, a combination of a row decoder formed of nMOS dynamic NOR circuits and column decoder composed of CMOS static NAND circuits is most preferable. However, as described above, in order to form a decoder employing the combination of an NOR type row decoder and an NAND type column decoder, a predecoder must be provided for each of the row address and the column address. Alternatively, in order to use the predecoder both for the row address and the column address, the row decoder and the column decoder must be composed of circuits of the same type. Therefore, in either case, a decoder cannot be constructed in its most suitable way in view of its performance or the number of elements for composing the circuit. 
     An address decoder using the predecoding method with an address decoder for one axis composed of an NAND circuit and an address decoder for the other axis composed of an NOR circuit is disclosed in U.S. Pat. No. 4,429,374 &#34;Memory Array Addressing&#34; by Tanimura. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to eliminate the above described problems of the prior arts and to apply the predecoding method to a DRAM, specifically to a DRAM with static column function in the most suitable way, thereby to provide a high speed and highly area-effective DRAM, specifically a DRAM with static column function. 
     A semiconductor memory employing the predecoding method according to the present invention comprises a predecoder used both for the row address and column address, a row decoder composed of NOR circuits, a column decoder composed of NAND circuits and a logic inversion circuit for matching the address information logic between the row decoder and the column decoder. 
     In the above described structure, the predecoder outputs an intermediate signal of a logic matching either with the row decoder or the column decoder and, the intermediate signal from the predecoder is applied to the decoder of which logic is not matching with the output logic of the predecoder through the logic inversion circuit. 
     Accordingly, the predecoding method can be applied to the DRAM with a static column function in the most suitable way, providing a DRAM with a static column function with high speed and high area-effectiveness. 
     These and other objects and features of the present invention will be more apparent from the following detailed description with reference to the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Fig. 1 is a schematic diagram showing one structure of a conventional address decoder employing the predecoding method. 
     FIG. 2 is a schematic diagram showing another structure of a conventional address decoder employing the predecoding method. 
     FIG. 3 is a block diagram showing the structure of a semiconductor memory according to one embodiment of the present invention. 
     FIG. 4 shows one example of a structure of an address buffer circuit and a predecoder circuit according to the present invention. 
     FIG. 5 shows one example of a structure of a unit row decoder forming the row decoder according to the present invention. 
     FIG. 6 shows one example of a structure of a logic inversion circuit according to the present invention. 
     FIG. 7 shows the structure of a unit column decoder and a unit word driver circuit according to the present invention. 
     FIG. 8 shows one example of a structure of a circuit for decoding a word line drive clock φ x . 
     FIG. 9 is a diagram of signal wave forms showing the address.decode operation of the semiconductor memory according to the present invention. 
     FIG. 10 shows a structure of a predecoder according to another embodiment of the present invention. 
     FIG. 11 shows a structure of a logic inversion circuit according to another embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 is a block diagram showing the structure of a semiconductor memory according to one embodiment of the present invention. 
     In FIG. 3, the semiconductor memory comprises a memory cell array 11 composed of a plurality of memory cells arranged in a matrix form of rows and columns, an address buffer circuit 10 used for both row and column addresses for receiving an external address signal which specifies a single memory cell included in the memory cell array 11 to arrange the waveform thereof, a predecoder circuit 60 for predecoding an address signal from the address buffer circuit 10 and for outputting an intermediate signal, a column decoder 12 for outputting a column selection signal in response to the intermediate signal from the predecoder 60, a row decoder 14 for outputting a row selection signal in response to the intermediate signal from the predecoder 60 and, a logic inversion circuit 16 provided between the predecoder 60 and the column decoder 12 and the row decoder 14, for establishing logic matching of the row decoder 14 and the column decoder 12 with respect to the intermediate signal from the predecoder 60. A word driver 14 for activating one row (word line) selected by the row decoder 14 is provided between the memory cell array 11 and the row decoder 14. 
     A sense amplifier and I/0 gate 13 for supplying and receiving input data D IN  and output data D OUT  to and from the memory cell array 11 is provided between the memory cell array 11 and the data input buffer 22 and data output buffer 21. 
     On the other hand, in order to control the operation timing of the semiconductor memory, provided are an RAS clock buffer 17 for receiving an external row address strobe signal Ext.RAS for providing the timing of strobing the row address and for outputting an internal RAS signal, a CS clock buffer 18 for receiving an external chip select signal Ext.CS for providing the timing for data input and output and for outputting an internal CS signal, a WE clock buffer 19 for receiving an external write enable signal Ext.WE for applying an instruction for data writing operation and for outputting an internal WE signal, and a timing control circuit 20 for controlling the operation timing of the semiconductor memory in response to the clock signals from the buffers 17, 18 and 19. 
     In a DRAM with static column function, CS is used instead of the signal CAS (column address strobe) for controlling the timing of the column selection. 
     The structure of circuits in each block will now be described with reference to the drawings with regard to the case where the semiconductor memory has a memory capacity of 65,536 bits (256 rows by 256 columns). 
     FIG. 4 shows one example of the structure of the address buffer circuit and the predecoder shown in FIG. 3. 
     In FIG. 4, the address buffer circuit 10 comprises address buffer circuits 1 each of which receives an external address input signal Ext.A1 (1=0, 1, . . . ,7) and outputs address signals A1, A1 which are complementary with each other. The predecoder 60 comprises four predecoders 6 composed of four 2-input AND gate and four 2-input NOR gates, each of which receives address signals A 2m , A 2m , A 2m+1  and A 2m+1  (m=0,1,2,3) from the address buffer circuit 10 and a predecoder enable signal PREDECODER ENABLE for providing the operation timing of the predecoder 60 and performs the logic operation represented by the following equations (11)˜(14) to output intermediate signals Z 4m , Z 4m+1 , Z 4m+2  and A 4m+3 . 
     
         Z.sub.4m =(A.sub.2m ·A.sub.2m +1)+(PREDECODER ENABLE) (11) 
    
     
         Z.sub.4m+1 =(A.sub.2m ·A.sub.2m+1)+(PREDECODER ENABLE) (12) 
    
     
         Z.sub.4m+2 =(A.sub.2m ·A.sub.2m+1)+(PREDECODER ENABLE) (13) 
    
     
         Z.sub.4m+3 =(A.sub.2m ·A.sub.2m+1)+(PREDECODER ENABLE) (14) 
    
     where m=0, 1, 2, 3. 
     In this structure, the output from the predecoder 60 is an active-high signal. The intermediate signals from the predecoder 60 are applied to the column decoder 12. 
     FIG. 5 shows one example of a structure of a unit column decoder forming the column decoder shown in FIG. 4. 
     In FIG. 5, the unit column decoder comprises a CMOS type static NAND circuit which receives a column decoder control signal COLUMN DECODER ENABLE for activating the column decoder and a predetermined set of three intermediate signals from the predecoder 60 for outputting the negative logical product thereof, and a CMOS logic gate for evaluating the logical product of the inverted signal of the NAND circuit output and each of the intermediate signals Z 0 , Z 1 , Z 2  and Z 3  for outputting selection signals Y 4n , Y 4n+1 , Y 4n+2  and Y 4n+3 . 
     A CMOS static NAND circuit is composed of four parallel-connected p channel MOS transistors P 20  ˜P 23  and four series-connected n channel MOS transistors N 20  ˜N 23 . Namely, the pMOS transistor P 20  and the nMOS transistor N 20  receive a signal COLUMN DECODER ENABLE at their gates, the pMOS transistor P 21  and the nMOS transistor N 21  receive one of the intermediate signals Z 4  ˜Z 7  at their gates, the pMOS transistor P 22  and the nMOS transistor N 22   receive one of the intermediate signals Z 8  ˜Z 11  at their gates and the pMOS transistor P 22  and the nMOS transistor N 22  receive one of the intermediate signals Z 12  ˜Z 15  at their gates. One conduction terminal of each of the pMOS transistors P 20  ˜P 23  is connected to the supply potential V CC , while the other conduction terminal is connected in common to the NAND circuit output signal line. The nMOS transistors N 20  ˜N 23  are connected in series with each other, one conduction terminal of the nMOS transistor N 20  is connected to the NAND circuit output signal line and the other conduction terminal of the nMOS transistor N 23  is connected to the ground potential V SS . 
     The logic gate portion for outputting a selection signal is composed of two portions. One selection signal output portion is formed of four pMOS transistors P 24  ˜P 27  and four nMOS transistors N 24  ˜N 27 . An NAND circuit output signal is applied to all gates of the pMOS transistors P 24  ˜P 27  and the nMOS transistors N 24  ˜N 27 . 
     One conduction terminal of the pMOS transistor P 24  receives the intermediate signal Z 0 , while the other conduction terminal is connected to one conduction terminal of the nMOS transistor N 24  and at the same time outputs a selection signal Y 4N . 
     Similarly, the pMOS transistor P 25  and the nMOS transistor N 25  are provided for an intermediate signal Z 1   for outputting a selection signal Y 4n+1  responsive to the NAND circuit output and the intermediate signal Z 1 . The pMOS transistor P 26  and the nMOS transistor N 26  are provided for an intermediate signal Z 2  for outputting a selection signal Y 4N+2  responsive to the NAND circuit output and the intermediate signal Z 2 . The pMOS transistor P 27  and the nMOS transistor N 27  are provided for an intermediate signal Z 3  for outputting a selection signal Y 4N+3  responsive to the intermediate signal Z 3  and the NAND circuit output. 
     The other part of the logic gate for selection signal generation is of the same structure as the logic gate described above, comprising pMOS transistors P 28  ˜P 31  and nMOS transistors N 28  ˜N 31 . The pMOS transistor P 28  and the nMOS transistor N 28  are provided for an intermediate signal Z 0  for outputting a selection signal Y 4N . The pMOS transistor P 29  and the nMOS transistor N 29  are provided for an intermediate signal Z 1  the pMOS transistor P 30  and the nMOS transistor N 30  are provided for an intermediate signal Z 2 , and the pMOS transistor P 31  and the nMOS transistor N 31  are provided for an intermediate signal Z 3 , respectively, for outputting selection signals Y 4N+1 , Y 4N+2  and Y 4N+3 , respectively. 
     When a control signal COLUMN DECODER ENABLE becomes &#34;H&#34;, the NAND circuit is activated to decode a supplied intermediate signal. The logic gate portion outputs selection signals Y 4N , Y 4N+1 , Y 4N+2  and Y 4N+3  which satisfy the following equation (15) in response to the NAND circuit output and the intermediate signals Z 0  ˜Z 3 . 
     
         Y.sub.4N+t 32 Z.sub.t ·X                          (15) 
    
     t=0, 1, 2, 3, , 
     n=0, 1, 2, ...63 
     X: NAND circuit output 
     For example, the unit decoder circuit constructed so as to receive the intermediate signals Z 4 , Z 8  and Z 12  provides decoded signals Y 0  -Y 3  satisfying the following equations (15a)-(15d): ##EQU3## where, PDE represents a precharge decoder enable signal and CDE represents a column decoder enable signal. 
     Therefore, when all the column signals A 0  -A 7  are low and when both PDE and CDE are high, this unit decoder responds with providing Y 0  of high level. 
     FIG. 6 shows a structure of the logic inversion circuit shown in FIG. 3. In FIG. 6, the logic inversion circuit 16 is formed of a clocked CMOS inverter comprising p channel MOS transistors P 32  ˜P 34  and n channel MOS transistors N 52  and N 53 . The p channel MOS transistor P 32  receives at its gate an intermediate signal Z i  (i=4, 5,...15) applied through a column decoder 12, one conduction terminal thereof is connected to the supply potential V CC , and the other conduction terminal is connected to a signal line Z i  in the upper side and the lower side (in the figure) through p channel MOS transistors P 33 , P 34 . Namely, the pMOS transistor P 32  inverts the signal Z i  to output the same. 
     p channel MOS transistors P 33  and P 34  both receive at their gates a signal φ XD  through the inverter to be on/off controlled and transmit the output of the p channel MOS transistor P 32  to the row decoder 14 through a signal line Z i . 
     n channel MOS transistors N 52  and N 53  both receive a control signal PRECHARGE at their gates to be on/off controlled and, when they are rendered conductive, they connect the signal line Z i  to the ground potential V SS . The signal φ XD  is a logic inverted signal of a signal obtained by delaying a word line drive clock φ X  for activating the word line by a predetermined time period. 
     A control signal PRECHARGE is a signal for providing the timing of the precharge operation of the semiconductor memory generated synchronously with the signal RAS. While the signal PRECHARGE is &#34;H&#34;, the word line and bit line of the semiconductor memory are precharged. During precharging, the predecoder control signal PREDECODER ENABLE (FIG. 4) is &#34;L&#34; and the intermediate signal Z i  (i=4, 5,...15) is &#34;H&#34;, so that all Z i  applied to the row decoder 14 are &#34;L&#34;. 
     When the memory operation of the semiconductor memory begins and the signal PRECHARGE ENABLE becomes &#34;L&#34; and the predecoder control signal PREDECODER ENABLE becomes &#34;H&#34;, then the intermediate signal Z i  changes in response to the external address signal applied at that time, and the signal Z i  corresponding to the intermediate signal Z i   which has changed into &#34;L&#34; becomes &#34;H&#34;. After the generation of a word line drive clock φ X , when the signal φ XD  becomes &#34;L&#34;, p channel MOS transistors P×and P 34  are both turned off and the Z i  signal is cut off from the Z i  signal line. 
     FIG. 7 shows the structure of an unit row decoder and an unit word driver circuit forming the row decoder and the word driver circuit shown in FIG. 3. In FIG. 7, the unit decoder is composed of an NMOS dynamic NOR circuit comprising n channel MOS transistors N 32  ˜N 35 . The nMOS transistor N 33  receives one of the intermediate signals Z 4  ˜Z 7  at its gate, one conduction terminal thereof being connected to the output signal line of the NOR circuit and the other conduction terminal being connected to the ground potential V SS . The nMOS transistor N 34  receives at its gate one of the intermediate signals Z 8  ˜Z 11  its one conduction terminal being connected to the output signal line and the other conduction terminal being connected to the ground potential V SS . The nMOS transistor N 35  receives at its gate one of the intermedicate signals Z 12  ˜Z 15 , its one conduction terminal being connected to the output signal line and the other conduction terminal being connected to the ground potential V SS  nMOS transistor N 32  receives a control signal PRECHARGE at its gate, its one conduction terminal being connected to the supply potential V CC  and the other conduction terminal connected to the output signal line. 
     While the time when the signal PRECHARGE is &#34;H&#34;, the intermediate signals Z i  (i=4,...,15) are all &#34;L&#34; and the output signal line is precharged through the nMOS transistor N 32 . When the signal PRECHARGE is &#34;L&#34;, the NOR circuit decodes the supplied intermediate signal to transmit the same onto the output signal line. One unit word.driver circuit is composed of n channel MOS transistors N 36  ˜N 42  while the other unit word driver circuit is composed of n channel MOS transistors N 44  ˜N 51 . N channel MOS transistors N 36 , N 38 , N 40  and N 42  receive the control signal φ XD  at their gates, and supply the NOR circuit output to the gates of n channel MOS transistors N 37 , N 39 , N 41  and N 43 , respectively. n channel MOS transistors N 37 , N 39 , N 41  and N 43  transmit decoded clocks φ X0 , φ X1 , φ X2  and φ X3  (the generation of φ  X0  ˜φ X3  will be described later) on the word line, respectively, in response to the signal applied to their gates and activate (select) the corresponding word line. Similarly, in the other word.driver circuit, n channel MOS transistors N 44 , N 46 , N 48  and N 50  are turned on and off in response to the control signal φ XD  to transmit the NOR circuit output. n channel MOS transistors N 45 , N 47 , N 49  and N 51  are turned on and off in response to the signals transmitted from the n channel MOS transistors N 44 , N 46 , N 48  and N 50 , respectively, and transmit the decoded clocks φ X0 , φ X1 , φ X2  and φ X3  to the word lines. A clamp circuit 50 is provided on each of the word lines in order to prevent the word line potential from floating to cause erroneous selection condition at the time when it is not selected. The aforementioned row decoder and the word driver circuit are structured in such a manner that the intermediate signals Z 4  ˜Z 15  are decoded in the nMOS dynamic NOR circuit portion and the word driver circuit activates one word line by the NOR circuit output and the clocks φ X0  ˜φ X3  obtained by decoding the word line drive clock φ X . The circuit structure shown in FIG. 7 has been conventionally employed, so that a detailed description of its operation is omitted. 
     FIG. 8 shows one example of the structure of a decoder of the word line drive clock φ X . 
     In FIG. 8, the clock decoder is composed of n channel MOS transistors N 54 , N 56 , N 58  and N 60  which turn on and off in response to the signal φ XD  and transmit intermediate signals Z 0  ˜Z 3 , respectively, and n channel MOS transistors N 55 , N 57 , N 59  and N 61  which turn on and off in response to the signals transmitted from the n channel MOS transistors N 54 , N 56 , N 58  and N 60 , respectively, and output the decoded clocks φ X0 , φ X1 , φ X2   and φ X3 , respectively, by transmitting/not transmitting the clock φ X . A clamp circuit 55 is provided on each of the output signal lines of the nMOS transistors N 55 , N 57 , N 59  and N 61  in order to prevent the potential of the output signal line from floating which causes the erroneous decoded clock to be outputted. In this clock decoder, one of the singals φ X0  ˜φ X3  is activated in response to the value of the intermediate signals Z 0  ˜Z 3 . This is because one of the intermediate signals Z 0  ˜Z 3  becomes &#34;H&#34; as is apparent from the equations (11)˜(14). 
     FIG. 9 is a diagram of waveforms showing the operation timing of each part of the circuit shown in FIGS. 3 to 8. The address decode operation according to the present invention will be described with reference to FIG. 9. 
     While the external control signal Ext.RAS is &#34;H&#34;, the semiconductor memory performs the precharging operation. Namely, during this period, the signal PREDECODER ENABLE is &#34;L&#34;, the signal PRECHARGE is &#34;H&#34;, the intermediate signal Z j  (j=0,...15) is &#34;H&#34;, the intermediate signal Z k  (k=4, 5,...15) is &#34;L&#34;, the clock φ X  is &#34;L&#34;, the delay clock φ Xd  is &#34;H&#34; and the signal COLUMN DECODER ENABLE is &#34;L&#34;, so that all rows (word lines) and all columns are in the non-selection state and all dynamic NOR circuits forming the row decoder 14 are precharged. 
     After the row address information is set to be as the external address input signal Ext.A i  (i=1, 2,...7), when the signal Ext.RAS becomes &#34;L&#34; at the time t1, the signal PRECHARGE becomes &#34;L&#34; while the signal PREDECODER ENABLE becomes &#34;H&#34;. Accordingly, the predecoder 60 is activated and predecodes the row address supplied through the address buffer circuit 10 to output the intermediate signals Z 0  ˜Z 15 . At this time, the signal COLUMN DECODER ENABLE is &#34;L&#34; and column decoders 12 are all in the non-selection state. On the other hand, the row decoder 4 receives the logic-inverted intermediate signal Z k  (k=4,...15) through the logic inversion circuit 16 to start decoding. After the completion of the decoding operation of the row decoder 14, when the word line drive clock φ X  becomes &#34;H&#34;, either one of the decoded clocks φ X0  ˜φ X3  becomes &#34;H&#34; in response to the value of the intermediate signal Z 0  ˜Z 3  at the time. Consequently, one word line is selected through a word driver circuit connected to the unit row decoder which is in the selection state. Then, when the delay clock φ XD  becomes &#34;L&#34;, the address information line Z i  in the row decoder 14 is disconnected from the address information line Z i  in the column decoder 12 by the logic inversion circuit 16 (see FIG. 6). At the same time, the row decoder 14 is disconnected from the word driver circuit 15 (see FIG. 7). When the signal COLUMN DECODER ENABLE becomes &#34;H&#34;, the column decoder 12 is activated and it decodes the intermediate signal Z j  supplied from the predecoder 60 to output the corresponding column selection signal (see FIG. 5). Namely, when the column decoder 12 is activated, it selects the column corresponding to the address information at that time in response to the change of the external address input Ext.A i . In the static column mode, after the selection of one row, the memory cells connected to the row are successively selected in response to the column address. When the external control signal Ext.RAS becomes &#34;H&#34; again, all internal signals return to the precharge state. Although only the address.decode operation is described above, other operations are similar to that of a conventional semiconductor memory, so that the description is omitted. 
     Although in the above embodiment a structure is shown in which the intermediate signal from the predecoder is directly supplied to the row decoder and the intermediate signal is supplied to the column decoder through the logic inversion circuit, another structure may be applied to obtain the same effect as the above embodiment in which the intermediate signal from the predecoder is directly supplied to the column decoder and the intermediate signal is supplied to the row decoder through the logic inversion circuit. 
     FIG. 10 shows a structure of a predecoder according to another embodiment of the present invention. In FIG. 10, a unit predecoder is composed of eight 2-input NAND gates. NAND gates 71˜74 are activated when the signal PREDECODER ENABLE is &#34;H&#34;, to output the logic inversion signal of the address input A 2N , A 2N , A 2N+1 , A 2N+1  (N=0, 1, 2, 3), respectively. The NAND gate 75 receives the outputs from NAND gates 71 and 73, and evaluates the negative logical product thereof to output the intermediate signal Z 4N . The NAND gate 76 receives the output from the NAND gates 72 and 73, and evaluates the negative logic product thereof to output the intermediate signal Z 4N+1 . The NAND gate 77 evaluates the negative logical product of the outputs from the NAND gates 71 and 74 to output the intermediate signal Z 4N+2 . The NAND gate 78 evaluates the negative logic product of the outputs of the NAND gates 72 and 74 to output the intermediate signal Z 4N+3 . In the above desceibed structure, the intermediate signals Z 4N , Z 4N+1 , Z 4N+2  and Z 4N+3  satisfy the following equations (16)˜(19). 
     
         Z.sub.4N =(A.sub.2N +A.sub.2N+1)·(PREDECODER ENABLE) (16) 
    
     
         Z.sub.4N+1 =(A.sub.2N +A.sub.2N+1)·(PREDECODER ENABLE) (17) 
    
     
         Z.sub.4N+2 =(A.sub.2N +A.sub.2N+1)·(PREDECODER ENABLE) (18) 
    
     
         Z.sub.4N+3 =(A.sub.2N +A.sub.2N+1)·(PREDECODER ENABLE) (19) 
    
     FIG. 11 shows the structure of a logic inversion circuit according to another embodiment of the present invention. 
     In FIG. 11, the logic inversion circuit 16 is composed of a CMOS type inverter which receives the intermediate signal Z i  (i=0,...15) from the predecoder shown in FIG. 10 and outputs the inverted intermediate signal Z i . Namely, the logic inversion circuit is composed of complementary connected pMOS transistor P 62  and nMOS transistor N 62 , the input thereto being the intermediate signal Z i . The output Z i  from this inverter is applied to the column decoder. 
     As described above, according to the present invention, the row decoder and the column decoder are composed of the NOR circuit and the NAND circuit, respectively, the predecoder is used for both the row address and the column address, and a logic inversion circuit is provided for matching the logics between the row decoder and the column decoder, so that a semiconductor memory of high speed and high area-effectiveness can be implemented. 
     Although the present invention has been described with reference to specific embodiments, it should be understood that these embodiments are exemplary preferred embodiments and that modifications may be made without departing from the scope of the invention as defined in the appended claims.