Patent Publication Number: US-7592976-B2

Title: Flat display panel having internal power supply circuit for reducing power consumption

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a Continuation of application Ser. No. 09/974,806, filed Oct. 12, 2001, now U.S. Pat. No. 7,068, 264 which is a Continuation of Ser. No. 09/013,538 filed Jan. 26, 1998 now U.S. Pat. No. 6,522,314, which is a Continuation application of application Ser. No. 08/351,655 filed Dec. 7, 1994 now abandoned, which, in turn, is a Continuation-in-Part application of Ser. No. 08/188,760 filed on Jan. 31, 1994 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to flat displays, and particularly, to flat displays employing a plasma display panel, an electroluminescence panel, a liquid crystal panel, a fluorescent display tube, or light emitting diodes. 
     2. Description of the Related Art 
     The sizes and capacities of flat displays are increasing, due to the requirement for full-color displays, and the power consumption of the flat displays is increasing accordingly. The power consumption must be minimized. 
     For example, in the plasma display panel, to erase the whole screen of the flat display, non-display data may be entered to the display, or a signal DISPENA may be supplied to turn OFF the output of an address driver of the display. Once the screen is wholly erased, no address pulse is applied to form wall charges. Sustain pulses, however, are applied even thereafter, although they do nothing on the display. These sustain pulses waste electric power in the conventional flat displays. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to reduce the power consumption of a flat display by eliminating useless charging currents, as well as eliminating reactive currents caused by useless switching, from a display panel. 
     According to the present invention, there is provided a flat display employing at least one high voltage, different from logic voltages, wherein the flat display comprises a voltage detection unit for detecting the high voltage; and a drive control signal control unit for controlling drive control signals of the flat display in response to the detected high voltage. 
     The flat display may further comprise an internal power supply controlling unit for controlling an operation of an internal power supply circuit. The internal power supply controlling unit may control an operation of the internal power supply circuit by changing power supply control signals in response to the detected high voltage and the other drive voltages which are produced by the high voltage. The drive control signal control unit may control an operation of a display panel driving unit by changing the drive control signals in response to the detected high voltage and the other drive voltages which are produced by the high voltage. 
     The drive control signal control unit and the internal power supply controlling unit may stop circuit operation through a control circuit if the detected high voltage is below a specific value set in the flat display, and start the circuit operation through the control circuit if the detected high voltage reaches the specific value, and thereby the drive control signals may be controlled in response to changes in the detected high voltage. The drive control signal control unit and the internal power supply controlling unit may store at least first and second specific values to be compared with the detected high voltage, the first specific value being used at a rise of the high voltage and the second specific value being used at a fall of the high voltage. 
     Further, according to the present invention, there is provided a flat display employing at least one high voltage different from logic voltages, wherein the flat display comprises an external signal detection unit for detecting a specific signal input from the external of the flat display; and a drive control signal control unit for controlling drive control signals of the flat display in response to the detected specific signal. 
     The flat display may further comprise an internal power supply controlling unit for controlling an operation of an internal power supply circuit. The internal power supply controlling unit may control an operation of the internal power supply circuit by changing power supply control signals in response to the detected specific signal. The drive control signal control unit may control an operation of a display panel driving unit by changing the drive control signals in response to the detected specific signal. The drive control signal control unit and the internal power supply controlling unit may stop circuit operation through a control circuit if the specific signal is at a first level, and start the circuit operation through the control circuit if the detected specific signal is at a second level, and thereby the drive control signals may be controlled in response to a level of the specific signal. 
     According to the present invention, there is also provided a flat display employing at least one high voltage different from logic voltages, wherein the flat display comprises a display data checking unit for checking display data input to the flat display from the external; and a drive control signal control unit for controlling drive control signals of the flat display in accordance with the checked display data. 
     The flat display may further comprise an internal power supply controlling unit for controlling an operation of an internal power supply circuit. The internal power supply controlling unit may control an operation of the internal power supply circuit by changing power supply control signals in response to the checked result of the display data. The drive control signal control unit may control an operation of a display panel driving unit by changing the drive control signals in response to the checked result of the display data. The drive control signal control unit and the internal power supply controlling unit may stop circuit operation through a control circuit if the display data is not input to the flat display during a specific period, and start the circuit operation through the control circuit if the display data is input to the flat display, and thereby the drive control signals may be controlled in response to the checked result of the display data. 
     In addition, according to the present invention, there is provided a flat display for displaying data with a high voltage and drive voltages produced from the high voltage, wherein the flat display comprises a first high voltage decision unit for determining whether or not the high voltage is at a specific value or a specific range after a power supply is turned on and initialization is carried out; a first drive voltage decision unit for determining whether or not the drive voltages are at specific values or specific ranges; a second high voltage decision unit for determining whether or not the high voltage is kept at the specific value or the specific range after the start of protective operation of an internal power supply circuit that generates the drive voltages; a second drive voltage decision unit for determining whether or not the drive voltages are kept at the specific values or the specific ranges; and a drive control signal control unit for controlling drive control signals of the flat display in response to the decided results of the decision units. 
     The control of the internal power supply circuit may be carried out together with the control of the drive control signals in response to the decided results of the second drive voltage decision unit. 
     The flat display may be initialized when the second high voltage decision unit determines that the high voltage is not kept at the specific value or the specific range, and an internal power of the internal power supply circuit and the drive voltages may be cut OFF when the second drive voltage decision unit determines that the drive voltages are not kept at the specific values or the specific ranges. 
     The flat display may further comprise a time compensation unit for compensating for the time between the instant that the high voltage is applied until the drive voltages reach the specific values. The specific value compared with the high voltage in the first high voltage decision unit may differ from the specific value compared with the high voltage in the second high voltage decision unit. 
     The flat display may be a three-electrode surface discharge AC plasma display. The three-electrode surface discharge AC plasma display may comprise first and second electrodes arranged in parallel with each other; and third electrodes orthogonal to the first and second electrodes, the first electrode being commonly connected together, and the second electrodes being arranged for display lines, respectively, wherein the display has a surface discharge structure employing wall charges as memory. 
     The three-electrode surface discharge AC plasma display may further comprise a first substrate, and the first and second electrodes being arranged in parallel with each other on the first substrate and paired for respective display lines; a second substrate spaced apart from and facing the first substrate, and the third electrodes being arranged on the second substrate away from and orthogonal to the first and second electrodes; a wall charge accumulating dielectric layer covering the surfaces of the first and second electrodes; a phosphor formed over the second substrate; a discharge gas sealed in a cavity defined between the first and second substrates; and cells formed at intersections where the first and second electrodes cross the third electrodes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein: 
         FIG. 1  is a model view showing a 3-electrode surface discharge AC plasma display panel according to a prior art; 
         FIG. 2  is a section showing one discharge cell in the plasma display panel of  FIG. 1 ; 
         FIG. 3  is a block diagram showing a 3-electrode surface discharge AC plasma display system employing the panel of  FIG. 1 ; 
         FIG. 4  is a diagram showing waveforms for driving the plasma display of  FIG. 3 ; 
         FIG. 5  is a block diagram showing a 3-electrode surface discharge AC plasma display system according to an embodiment of the present invention; 
         FIG. 6A  is a block diagram showing essential part of the display system of  FIG. 5 ; 
         FIG. 6B  is a circuit diagram showing a voltage detector of  FIG. 6A ; 
         FIGS. 7 and 8  are block diagrams showing internal power supply circuits of  FIG. 6A ; 
         FIG. 9  is a diagram showing control waveforms at various parts of the internal power supply circuit of  FIGS. 7 and 8 ; 
         FIG. 10  is a circuit diagram showing an essential part of a display data controller of the display of  FIG. 5 ; 
         FIG. 11  is a circuit diagram showing an essential part of a panel driver controller of the flat display of  FIG. 5 ; 
         FIG. 12  is a flowchart showing processes carried out in the display according to the present invention; 
         FIG. 13  is a diagram for explaining the operation of a timer mentioned in the flowchart of  FIG. 12 ; 
         FIG. 14  is a diagram showing a waveform corresponding to the processes of the flowchart of  FIG. 12 ; 
         FIG. 15  is a block diagram showing a 2-electrode surface discharge AC plasma display system according to another embodiment of the present invention; and 
         FIG. 16  is a diagram showing waveforms for driving the plasma display system of  FIG. 15 . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     For a better understanding of the preferred embodiments, the problems of the prior art will be explained with reference to  FIGS. 1 to 4 . 
     Flat displays usually employ a PDP (plasma display panel), EL (electroluminescence) elements, an LCD (liquid crystal display), a VFD (fluorescent display), or LEDs (light emitting diodes). The present invention is applicable to these various types of flat displays. In the following descriptions, however, the present invention is explained with reference to a 3-electrode surface discharge AC plasma display system (AC PDP). 
       FIG. 1  is a model view showing a 3-electrode surface discharge AC plasma display panel according to the prior art, and  FIG. 2  is a section showing the structure of one discharge cell in the panel of  FIG. 1 . The panel is made of M×N dots. 
     The panel has a front glass substrate  1 , a rear glass substrate  2 , address electrodes  3 , separators (walls)  4 , phosphor  5  surrounded by the separators  5 , a dielectric layer  6 , X-electrodes  7 , and Y-electrodes  8 . Discharge is mainly carried out between a pair of the X- and Y-electrodes  7  and  8  arranged on the rear glass substrate  2 . These electrodes  7  and  8  are called sustain discharge electrodes. 
     To select cells in a selected display line involving a corresponding one of the Y-electrodes  8 , according to display data, discharge is carried out between the corresponding Y-electrode  8  and the address electrodes  3 . 
     The insulation dielectric layer  6  is formed over the sustain discharge electrodes  7  and  8 . A protective MgO film is formed over the dielectric layer  6 . The front glass substrate  1  is positioned opposite to the rear glass substrate  2 , and the address electrodes- 3  and phosphor  5  are formed on the front glass substrate  1 . In response to discharge, the phosphor  5  emits a corresponding one of red, green, and blue light. The phosphor  5  is formed over the address electrodes  3 . 
     The separators or barriers  4  are formed on one or both of the glass substrates, to define discharge cavities for the cells, respectively. Discharge is discretely carried out in the cells. The discharge produces ultraviolet rays that cause the phosphor to emit light. The cells are arranged in a matrix of M×N dots to form the display panel of  FIG. 1 . In  FIG. 1 , reference marks A 1  to A M  represent the address electrodes  3 , and Y 1  to Y N  the Y-electrodes  8 . The X electrodes  7  are connected together. 
       FIG. 3  is a block diagram showing a 3-electrode surface discharge AC plasma display system employing the panel of  FIG. 1 . This display involves peripheral circuits for driving the panel. 
     The display system has a control circuit  100 , a display data controller  101 , a frame memory  102 , a panel driver controller  103 , a scan driver controller  104 , and a common driver controller  105 . The display further has an address driver  21 , an X-driver  22 , a Y-scan driver  23 , a Y-driver  24 , and the plasma display panel (PDP)  30 . 
     The display employs a dot clock (CLOCK) indicating display data, display data (DATA) of 3×8 bits, i.e., 8 bits for each color to display colors with 256 shades of gray, a vertical synchronous signal (VSYNC) indicating the start of a frame (a field), and a horizontal synchronous signal (HSYNC) indicating the start of a line. 
     The control circuit  100  has a display data controller  101  and a panel driver controller  103 . The display data controller  101  stores display data in the frame memory  102  and transfers the data to the address driver  21  according to panel drive timing. A reference mark A-DATA indicates the display data, and A-CLOCK is a transfer clock. 
     The panel driver controller  103  has a scan driver controller  104  and a common driver controller  105 , to determine the timing of applying a high voltage waveform to the panel  30 . The reference mark Y-DATA is scan data for turning ON the Y-scan driver 23 bit by bit, Y-CLOCK is a transfer clock for turning ON the Y-scan driver 23 bit by bit, Y-STB 1  is a Y-strobe  1  for determining the timing of turning ON the Y-scan driver  23 , and Y-STB 2  is a Y-strobe  2 . Further, X-UD is a signal (VS/VW) to turn ON/OFF the X-common driver  22 , X-DD is a signal (GND) to turn ON/OFF the X-common driver  22 , Y-UD is a control signal (VS/VW) to turn ON/OFF the Y-common driver  24 , and Y-DD is a control signal (GND) to turn ON/OFF the Y-common driver  24 . 
     The address electrodes  3  (A 1  to A M ) are discretely connected to the address driver  21 , which applies address pulses to the electrodes  3  to cause address discharge. The Y-electrodes  8  (Y 1  to Y N ) are discretely connected to the Y-scan driver  23 . The Yscan driver  23  is connected to the Y-common driver (Y-driver)  24 . The Y-scan driver  23  produces pulses to cause corresponding address discharge  8 . The Y-driver  24  produces sustain pulses, etc., which are applied to the Y-electrodes  8  through the Y-scan driver  23 . 
     All of the X-electrodes  7  on the panel  30  are connected together. The X-common driver (X-driver)  22  produces write pulses, sustain pulses, etc. 
     These drivers are controlled by the control circuit  100 , which is controlled by the external synchronous signals and display data signals. 
       FIG. 4  shows examples of waveforms for driving the plasma display of  FIG. 3 . These waveforms are produced within a sub-frame or a sub-field according to a write addressing method with separate address and sustain discharge. This method is effective to display full colors with multiple shades of gray and stably drive and address the display with low voltages. 
     In  FIG. 4 , the sub-frame is divided into an address period and a sustain discharge period. During the address period, full-screen write, full-screen erase, and line-by-line write (address) processes are carried out. During the sustain discharge period, sustain pulses are simultaneously applied to all display lines, to cause sustain discharge in cells where wall charges have been accumulated during the write (address) process. 
     When an interlace method is employed to divide a frame into two sub-frames, the sub-frame of  FIG. 4  will correspond to a sub-field contained in each of the divided sub-frames. 
     The driving method of  FIG. 4  is characterized in that the full-screen write and erase processes are carried out at the start of the address period, to equalize the conditions of all cells, and that the full-screen erase process leaves wall charges, which advantageously act on the next line-by-line write discharge (address discharge). 
     At first, the Y-electrodes are set to GND level, and a write pulse of voltage VW is applied to the X-electrodes, to carry out the full-screen write process. At this time, ions, i.e., positive charges are accumulated on the phosphor on the address electrodes. Then, an erase pulse of voltage VE is applied to carry out the full-screen erase process. This process erases wall charges on the insulation MgO film on the X- and Y-electrodes. It is preferred, however, to leave negative charges, i.e., electrons, on the MgO film on the Y-electrodes, so that the negative charges advantageously work on the next address discharge. At this time, the voltage of the remaining wall charges must not cause sustain discharge when sustain discharge pulses are applied to the X- and Y-electrodes. 
     In this way, the full-screen write and erase processes are carried out to equalize the conditions of the cells and to lower an addressing voltage. Thereafter, the write discharge (address discharge) process is carried out on the lines one by one. The Y-electrode of a line to be written is set to GND level, and an address pulse of voltage VA is applied to the address electrodes corresponding to cells to be written in the line. At this time, ions are on the phosphor on the address electrodes, and electrons are on the MgO film on the Y-electrodes. Accordingly, the address discharge occurs at a very low voltage. After all display lines are sequentially subjected to the address discharge, a sustain pulse of voltage VS is alternately applied to the X- and Y-electrodes to carry out sustain discharge. 
     To entirely erase the screen of the plasma display panel according to the prior art of  FIGS. 1 to 4 , non-display data may be entered to the display, or a signal DISPENA may be applied to turn OFF the outputs of the address driver. After the screen is entirely erased accordingly, no address pulse is applied to accumulate wall charges. Sustain pulses, however, are applied during the sustain discharge period that follows the address period as shown in  FIG. 4 . Namely, the conventional flat display generates sustain pulses that do nothing on the display and waste electric power. 
     Next, preferred embodiment of a flat display according to the present invention will be explained with reference to the accompanying drawings. 
       FIG. 5  is a 3-electrode surface discharge AC plasma display according to the embodiment of the present invention. The display includes peripheral circuits for driving a typical 3-electrode AC PDP. 
     As shown in  FIG. 5 , the display has a control circuit  10 , a display data controller  11 , a frame memory  12 , a panel driver controller  13 , a scan driver controller  14 , and a common driver controller  15 . The display has an address driver  21 , an X-driver  22 , a Y-scan driver  23 , a Y-driver  24 , and the plasma display panel (PDP)  30 . The display has a CPU  40  which generates a control signal ADENA for the display data controller  11 , and an internal power supply circuit  50  which generates drive voltages VA, VW, and VE. Note that, references MCRST and MCPSD denote control signals (drive control signals) for the display panel driver controller  13 , DERS denotes a signal indicating that display data DATA is not supplied (or indicating a display erasing state), and PWSC 1  and PWSC 2  denote control signals (power supply control signals). 
     What is different from the plasma display of  FIG. 3  is that the plasma display of  FIG. 5  is provided with the CPU  40  that supplies the control circuit  10  with the drive control signals MCRST, MCPSD, and ADENA, and also provides an internal power supply circuit  50  with the power supply control signals PWSC 1  and PWSC 2 . Further, the CPU  40  receives the signal DERS indicating the display erasing state from the control circuit  10 . 
     The control circuit  10  and internal power supply circuit  50  are modified to receive the control signals MCRST, MCPSD, ADENA, PWSC 1 , and PWSC 2  from the CPU  40 , and the CPU  40  is modified to receive the signals DERS from the control circuit  10 . The details of the modifications will be explained later. Other arrangements of the plasma display according to the embodiment of  FIG. 5  are basically the same as those of  FIG. 3 . 
     In  FIG. 5 , the display employs a dot clock CLOCK for indicating display data, display data DATA involving 3×8 bits, i.e., 8 bits for each color to display colors with 256 shades of gray, a vertical synchronous signal VSYNC indicating the start of a frame (a field), and a horizontal synchronous signal HSYNC indicating the start of a line. A reference mark A-DATA denotes the display data, and A-CLOCK is a transfer clock. 
     The control circuit  10  has the display data controller  11  and panel driver controller  13 . The display data controller  11  stores display data DATA in the frame memory  12  and transfers the data to the address driver  21  according to panel drive timing. Note that, in the display data controller  11 , the display data DATA is checked, and when the display data DATA is not supplied during a specific period (display erasing state), the signal DERS is output to the CPU  40  from the control circuit  10  (display data controller  11 ). Namely, the input display data DATA is checked in the display data controller  11 , and the checked result is supplied to the CPU by the signal DERS. 
     The panel driver controller  13  has a scan driver controller  14  and a common driver controller  15  to determine the timing of applying a high voltage waveform to the panel  30 . A reference mark Y-DATA is scan data for turning ON the Y-scan driver 23 bit by bit, Y-CLOCK is a transfer clock for turning ON the Y-scan driver 23 bit by bit, Y-STB 1  is a Y-strobe  1  for determining the timing of turning ON the Y-scan driver  23 , and Y-STB 2  is a Y-strobe  2 . Further, X-UD is a signal (VSNW) to turn ON/OFF the X-common driver  22 , X-DD is a signal (GND) to turn ON/OFF the X-common driver  22 , Y-UD is a control signal (VS/VW) to turn ON/OFF the Y-common driver  24 , and Y-DD is a control signal (GND) to turn ON/OFF the Y-common driver  24 . 
     The address electrodes  3  are connected to the address driver  21 , which applies address pulses to the electrodes  3  to cause address discharge. The Y-electrodes  8  are connected to the Y-scan driver  23 . The Y-scan driver  23  is connected to the Y-common driver (Y-driver)  24 . The Y-scan driver  23  produces pulses to cause address discharge. The Y-driver  24  produces sustain pulses, etc., which are applied to the Y-electrodes  8  through the Y-scan driver  23 . All of the x-electrodes  7  on the panel  30  are connected together. The X-common driver (X-driver)  22  produces write pulses, sustain pulses, etc. These drivers are controlled by the control circuit  10 , which is controlled according to the external synchronous signals, display data signals, and the control signals MCRST, MCPSD, and ADENA provided by the CPU  40 . 
     In the embodiment of the present invention, a high voltage VS for displaying, a signal DISPENA, and a signal DERS are internally detected. Note that the signal DISPENA indicates erase or waiting (stand by) state and is input from the external of the display, and the signal DERS indicates no display data (or indicates that display data DATA is not supplied during a specific period). When the detected high voltage (VS) is below a specific value set in the flat display (for example, at a rise of the high voltage of a power ON state or a fall of the high voltage of a power OFF state), the display is stopped and a display operation of an abnormal (inferior) image can be avoided. 
     Further, when the signal DISPENA, input from the external, is at a specific level (low level L) or when the signal DERS is at a specific level (low level L) indicating that the display data DATA is not supplied during a specific period, the display is brought to a non-display state. Namely, in the above embodiment, as shown in  FIG. 5 , the CPU  40  receives the signal (specific signal) DISPENA from the external of the display, and when the signal DISPENA is at a specific level (low level (L)), the drive signals for the panel are stopped by the control signals (drive control signals) MCRST, MCPSD, and ADENA. Note that, when the specific signal DISPENA is at the specific level, the outputs of the address driver are turned OFF, and, further, the sustain pulses are also cut OFF. 
     Note that, in the above embodiment, the display can be stopped when the user (operator) intentionally cuts OFF, or decreases, the high voltage (VS) without employing an exclusive signal. When the operator intentionally cuts OFF the high voltage (VS) or decreases the high voltage (VS) below a specific value, which is previously set in the display, the drive signals (waveforms) for the panel are stopped by the control signals MCRST, MCPSD, and ADENA without using an exclusive signal and without providing an exclusive signal line. Namely, the flat display according to the embodiment internally detects the high voltage VS, to minimize a reactive current in a non-display state, i.e., an OFF state. If the detected high voltage VS is lower than a predetermined value (specific value), the control signals MCRST, MCPSD, and ADENA are provided to stop drive waveforms to the panel, to achieve a display OFF state. Note that the high voltage Vs is applied from outside the flat display, and is controlled by the user (operator). 
     Therefore, in the above embodiment, when the operator intentionally controls the high voltage (VS) or the signal DISPENA, the display can be brought to the non-display state and the consumption power of the display can be reduced. 
     As described above, according to the present embodiment, (1) when the display data DATA is not supplied during a specific period, (2) when the high voltage (VS) is below a specific value set in the flat display, or (3) when the specific signal DISPENA input from the external is at a specific level, charging currents that are irrelevant to an actual display operation and reactive currents due to useless switching operations are eliminated, so that power consumption can be reduced. 
       FIG. 6A  is a block diagram showing an essential part of the flat display of  FIG. 5 , and  FIG. 6B  is a circuit diagram showing a voltage detector of  FIG. 6A . The part shown in  FIG. 6A  involves the CPU  40 , internal power supply circuit  50 , high-voltage detectors  61  to  64 , a clock generator  65 , and a power-on-reset circuit  66 . 
     The internal power supply circuit  50  receives a power supply voltage Vcc and the high voltage VS and provides, according to PWM control, a voltage VA for an address discharge pulse, a voltage VW for a write discharge pulse, and a voltage VE for an erase pulse. The high voltage VS is detected by the high-voltage detector  61 , the address discharge pulse voltage VA by the high-voltage detector  62 , the write discharge pulse voltage VW by the high-voltage detector  63 , and the erase pulse voltage VE by the high-voltage detector  64 . Note that the high voltage Vs is applied from outside the flat display, and is controlled by the user (operator). Namely, when the user selects a non-display state, the high voltage Vs is lowered. 
     In  FIG. 6B , the high-voltage detector  61  ( 62 ,  63 ,  64 ) is made of resistors R 61  to R 63  and a capacitor C 61 , to provide a detection signal VSK (VAK, VWK, VEK). 
     The detection signals VSK, VAK, VWK, and VEK are supplied to an 8-bit analog-to-digital (A/D) converter incorporated in the CPU  40 . The converted data is stored by an internal register in the CPU  40  so that the CPU  40  identifies each voltage value as 8-bit data representing 256 points. The CPU  40  also receives a clock signal CLK from the clock generator  65  and a power ON reset signal RST from the power-on-reset circuit  66 . The CPU  40  provides the internal power supply circuit  50  with the power supply control signals PWSC 1  and PWSC 2  and the control circuit  10  with the drive control signals MCRST, MCPSD, and ADENA. 
       FIGS. 7 and 8  are block diagrams showing the internal power supply circuit  50  of  FIG. 6A , and  FIG. 9  shows control waveforms at various parts of the internal power supply circuit  50 .  FIG. 7  shows the general arrangement of the internal power supply circuit  50 , and  FIG. 8  shows a circuit for processing the control signals PWSC 1  and PWSC 2  provided by the CPU  40 , as well as a DTC voltage circuit  55  of  FIG. 7 . The details of the internal power supply circuit  50  of  FIGS. 7 to 9  are disclosed in Japanese Patent Application No. 5-135952 filed by this applicant. 
     The internal power supply circuit  50  of  FIG. 7  has a switching waveform voltage/current converter  51 , a reference voltage circuit  52  for providing a reference voltage Vr, a PWM controller  53 , a reference triangular wave oscillator  54 , the DTC voltage circuit  55 , and a protection circuit  56 . These circuits are integrated in an IC chip. The internal power supply circuit  50  further has a FET Tr 50 , resistors R 51  to R 53 , capacitors C 51  to C 54 , a diode D 50 , and a choke coil L 50 . The capacitors C 52  and C 54  are electrolytic capacitors. 
     In  FIG. 8 , the internal power supply circuit  50  further has a latch circuit  71 , a comparator  72 , transistors Tr 71  to Tr 73 , resistors R 71  to R 75 , and capacitors C 71  and C 72 . The capacitors C 71  and C 72  are externally arranged, and the capacitor C 71  is an electrolytic capacitor. 
     An input of the comparator  72  receives the voltage VS(VS/m) derived from the high voltages), and the other input of the comparator  72  receives a voltage Vr(Vr/n) derived from the reference voltage Vr. 
     The control signals PWSC 1  and PWSC 2  are used to connect voltages obtained by dividing the high voltage VS through the resistors to the panel  30  as well as connecting output signals of the circuits for monitoring the voltage and current of the high voltage VS to the CPU  40 . 
     In  FIG. 8 , potential Vsc is controllable in response to not only the switching status of the transistor Tr 71  but also the switching statuses of the transistors Tr 72  and Tr 73  that are controlled by the control signals PWSC 1  and PWSC 2 . This enables the high voltage VS to control the protection circuit  56 . 
     The internal power supply circuit  50  of  FIGS. 7 to 9  has the reference power supply for the protection circuit in the circuit  50 . If one of the divided output voltages is higher than a corresponding reference voltage, internal switching operations are stopped to provide no output. 
     The protective operation and outputs of the internal power supply circuit  50  are controlled according to the control signals PWSC 1  and PWSC 2  provided by the CPU  40 . The logic of the control signals PWSC 1  and PWSC 2  are as shown in Table 1. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 PWSC1 
                 PWSCI 
                 Circuit operation 
               
               
                   
                   
               
             
            
               
                   
                 H 
                 H 
                 Disable internal protection circuit 
               
               
                   
                 H 
                 L 
                 Start internal protection circuit 
               
               
                   
                 L 
                 L 
                 Stop outputs of internal power supply 
               
               
                   
                   
               
            
           
         
       
     
     The signals PWSC 1  and PWSC 2  at a high level (H) disable the internal protection circuit. In this case, no protective operation is carried out. When the signal PWSC 1  is H and the signal PWSC 2  is low level (L), the internal protection circuit is started to enable the protective operation. When the signals PWSC 1  and PWSC 2  are each L, the outputs of the internal power supply circuit  50  are stopped. 
       FIG. 10  is a circuit diagram showing an essential part of the display data controller  11  of  FIG. 5 , and  FIG. 11  is a circuit diagram showing an essential part of the panel driver controller  13  of  FIG. 5 . In  FIG. 5 , the CPU  40  provides the control circuit  10  with the control signals MCRST, MCPSD, and ADENA. The control signal ADENA is supplied to the display data controller  11 , and the control signals MCRST and MCPSD are supplied to the panel driver controller  13 . 
     In  FIG. 10 , the display data controller  11  has AND gates  110  to  117  and one input of each gate receives display data D 0  to D 7 , respectively. The other input of each AND gate  110  to  117  receives the control signal ADENA. When the control signal ADENA is H, address data A-DATA (DOA to D 7 A) is supplied to the address driver  21 . When the signal ADENA is L, no address data A-DATA (DOA to D 7 A) is supplied to the address driver  21 . In this way, the address data A-DATA from the display data controller  11  of the control circuit  10  to the address driver  21  is controlled in response to the control signal ADENA. 
     In  FIG. 11 , the panel driver controller  13  (common driver controller  15 ) has AND gates  131  and  132 , an OR gate  133 , and a flip-flop  134 . An inverting input of the AND gate  131  and an input of the AND gate  132  receive the control signal MCPSD. Outputs of the AND gates  131  and  132  are passed through the OR gate  133  and supplied to a data input of the flip-flop  134 . The AND gate  132  receives the signals Y-UD, Y-DD, X-UD, and X-DD as well as the control signal MCPSD. Namely, the signals Y-UD, Y-DD, X-UD, and X-DD supplied from the common driver controller  15  of the control circuit  10  to the X- and Y-drivers  22  and  24  are controlled in response to the control signal MCPSD. 
     The control signal MCRST is applied to direct clear terminals of all of the latch circuits and flip-flops, and these latch circuits and flip-flops are initialized by the control signal MCRST of a specific level (low level (L)). 
     The levels of the control signals MCRST, MCPSD, and ADENA are as shown in Table 2. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Initial 
                 Normal 
                 Abnormal 
                 Non-Data 
                 Present 
                   
               
               
                   
                 Setting 
                 Operation 
                 Operation 
                 DERS = “L” 
                 Date DERS = “H” 
                 DISPENA = “L” 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                 MCRST 
                 L 
                 H 
                 L 
                 L 
                 H 
                 L 
               
               
                 MCPSD 
                 H 
                 L 
                 H 
                 H 
                 L 
                 H 
               
               
                 ADENA 
                 L 
                 H 
                 L 
                 L 
                 H 
                 L 
               
               
                   
               
            
           
         
       
     
     As shown in the above table 2, initially, the signals MCRST and ADENA are each L (low level), and the signal MCPSD is H (high level). During normal operation, the signals MCRST and ADENA are H, and the signal MCPSD is L. During an abnormal process (abnormal operation), the signals MCRST and ADENA are each L, and the signal MCPSD is H. 
     Further, in the case that the signal DERS is L, that is, when the display data DATA is not supplied during a specific period, the signals MCRST and ADENA are L, and the signal MCPSD is H. On the other hand, in the case that the signal DERS is H, that is, when the display data DATA is supplied from the external, the signals MCRST and ADENA are H, and the signal MCPSD is L. 
     Further, in the case that the signal DISPENA is L, that is, when the apparatus having (controlling) the display panel changes the signal DISPENA to a low level (L) or the user (operator) intentionally changes the signal DISPENA to L, so as to bring the display to a non-display state, the signals MCRST and ADENA are L, and the signal MCPSD is H. 
       FIG. 12  is a flowchart showing processes carried out in the flat display according to the present invention,  FIG. 13  explains the operation of a timer shown in the flowchart, and  FIG. 14  is a waveform corresponding to the processes shown in the flowchart. 
     In  FIG. 12 , the power supply Vcc is turned ON. The CPU  40  receives a reset signal RST of high level (H) from the power-on-reset circuit  66  and starts a program. 
     Step S 1  carries out initialization in which driving waveforms are stopped in response to the drive control signals MCRST, MCPSD, and ADENA, and the operation of the internal protection circuit is disabled in response to the control signals PWSC 1  and PWSC 2 . 
     Step S 2  checks the high voltage VS. This step loops until the high voltage VS reaches a specified value, which is 170 V in  FIG. 14 . This value is set in advance in the CPU  40 . Once the high voltage VS reaches the specified value, the loop ends and step S 3  starts. 
     Step S 3  compensates for a delay time according to a timer. The output voltage VA (VW, VE) shown in  FIG. 13(   c ) of the internal power supply circuit  50  needs about 350 msec to reach a predetermined value after the high voltage VS ( FIG. 13(   a )) reaches the specified value. Step S 3  secures this duration according to a timer. As shown in  FIGS. 13(   d ) and  13 ( e ) and Table 1, the signals PWSC 1  and PWSC 2  of each H disable the internal protection circuit. When the signal PWSC 1  is H and the signal PWSC 2  is L, the internal protection circuit is started. When the signals PWSC 1  and PWSC 2  are each L, the outputs of the internal power supply circuit  50  are stopped. 
     Step S 4  starts the internal protection circuit in response to the control signals PWSC 1  and PWSC 2 . 
     Step S 5  checks the internal power supply to see whether or not the output voltages VA, VW, and VE of the internal power supply circuit  50  meet values stored in the CPU  40 . If any one of the voltage values is abnormal, the flow branches to an abnormality process routine of step S 10 . 
     The abnormality process routine of step S 10  provides the control signals PWSC 1  and PWSC 2  to stop the internal power supply circuit  50  and supplies the control signals MCRST, MCPSD, and ADENA to stop the control circuit  10 . As a result, none of the drive waveforms of  FIG. 4  is generated. Note that, this state is not cleared until a power-on-reset circuit is available by applying power supply voltage Vcc. 
     If step S 5  determines that all of the drive voltages VA, VW, and VE are normal, step S 6  starts the control circuit  10  including the display data controller  11  and panel driver controller  13  in response to the control signals MCRST, MCPSD, and ADENA. The signal MCRST is a reset signal for controlling the direct clear operation of all of the latch circuits and flip-flops provided in the display (driving circuit). The signal MCPSD is a reset signal for a synchronously resetting the high-voltage drivers. The signal ADENA is an enable signal for the address driver  21 . 
     Step S 7  checks the signal DISPENA (specific signal) applied from the external and the signal DERS applied from the control circuit  10 , when at least one signal DISPENA and DERS is at a low level L, the flow returns to the initialization of step S 1 . Namely, when the apparatus having the display panel changes the signal DISPENA to a low level L or the user (operator) intentionally changes the signal DISPENA to a low level L, and/or when the display data DATA is not supplied during a specific period and the signal DERS is at a low level L, the flow returns to the initialization of step S 1 . In this case, the display is not only brought to the non-display state, but also unnecessary currents (reactive currents) for switching operations and charging/discharging operations which are only used for displaying are cut down, so that the consumption power of the display can be reduced. 
     On the other hand, when both signal DISPENA and DERS are at a high levels H, that is, when the apparatus having the display panel or the operator does not change the signal DISPENA to a low level L, and when the display data DATA is supplied from the external, the flow proceeds to Step  8 . 
     Step S 8  again checks the high voltage VS. If the high-voltage VS is at a specified value, step S 9  checks the internal power supply voltages VA, VW, and VE. If step S 8  determines that the high voltage VS is below the specified value, the flow returns to the initialization of step S 1 , and further, the flow proceeds to abnormality process routine of step S 10 . The specified value for checking the high voltage VS in step S 8  is 165 V in  FIG. 14 , i.e., lower than the specified value of 170 V when checking the high voltage VS in step S 2 . This prevents abnormal operation in the program due to voltage fluctuations. 
     If the high voltage VS exceeds 195 V, the voltage is determined to be abnormal, and the flow branches to the abnormal process routine of step S 10 , which stops the internal power supply circuit  50  in response to the control signals PWSC 1  and PWSC 2 , and the control circuit  10  in response to the control signals MCRST, MCPSD, and ADENA, as shown in  FIG. 14 . 
     When the high voltage VS reaches 175 V in  FIG. 14 , the internal power supply voltages VA, VW, and VE are checked to start displaying data. If the high voltage VS drops below 165 V, the initialization is again carried out, and the control circuit  10  is reset in response to the control signals MCRST, MCPSD, and ADENA, to erase the whole screen. 
     As described above, according to the present embodiment, when the display data DATA is not supplied during a specific period, when the high voltage (VS) is below a specific value set in the flat display, or when the specific signal DISPENA input from the external is at a specific level, charging currents that are irrelevant to an actual display operation and reactive currents due to useless switching operations are eliminated, so that power consumption can be reduced. 
       FIG. 15  is a block diagram showing a 2-electrode surface discharge AC plasma display according to another embodiment of the present invention, and  FIG. 16  is a diagram showing waveforms for driving the plasma display of  FIG. 15 . In  FIG. 15 , reference  7 A denotes X-electrodes (X 1  to X M ), and  21 A denotes X-address driver. 
     By comparing  FIG. 15  with  FIG. 5 , in the 2-electrode surface discharge AC plasma display of this embodiment, the X-electrodes  7  in the 3-electrode surface discharge AC plasma display are omitted, and the X-address driver  21 A is provided instead of the address driver  21  in the 3-electrode surface discharge AC plasma display of  FIG. 5 . Further, in this 2-electrode surface discharge AC plasma display, the X-electrodes  7 A are provided as the address electrodes (A 1  to A M )  3  in the 3-electrode surface discharge AC plasma display of  FIG. 5 . Note, the driving waveforms of the 2-electrode surface discharge AC plasma display of this embodiment are described in  FIG. 16 . 
     In the 2-electrode surface discharge AC plasma display of this second embodiment, the other configurations or special characteristics of the present invention are the same as that of the 3-electrode surface discharge AC plasma display of the above first embodiment. Further, the flat display of the present invention are not only applied to 2-electrode or 3-electrode surface discharge AC plasma display, but also can be applied to various types of flat displays, e.g., flat displays employing a plasma display panel, an electroluminescence panel, a liquid crystal panel, a fluorescent display tube, light emitting diodes, and the like. 
     As explained above in detail, the flat display according to the present invention eliminates charging currents that are irrelevant to an actual display operation and reactive currents due to useless switching operations, thereby reducing power consumption. 
     Many different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention, and it should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.