Patent Publication Number: US-9847331-B2

Title: Semiconductor integrated circuit

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a division of U.S. application Ser. No. 14/681,081 filed Apr. 7, 2015, which is a division of U.S. application Ser. No. 13/875,291 filed May 2, 2013, now U.S. Pat. No. 9,035,425, and incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having multi-gate transistor device integrated with other devices such as resistor and/or lateral double-diffused metal-oxide-semiconductor (hereinafter abbreviated as LDMOS) device. 
     2. Description of the Prior Art 
     Conventional planar metal-oxide-semiconductor (hereinafter abbreviated as MOS) transistor has difficulty when scaling down to 65 nm and below. Therefore the non-planar transistor technology such as Fin Field effect transistor (FinFET) technology that allows smaller size and higher performance is developed to replace the planar MOS transistor. 
     Since the manufacturing processes of the FinFET device are easily integrated into the traditional logic device processes, it provides superior process compatibility. More important, since the FinFET device increases the overlapping area between the gate and the substrate, the channel region is more effectively controlled. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. In addition, the channel region is longer under the same gate length, and thus the current between the source and the drain is increased. 
     However, the FinFET device still faces many problems. For example, semiconductor structures of different sizes and isolation structures of different sizes are often formed on one semiconductor integrated circuit, and it is always difficult to construct and integrate those semiconductor structures and the isolation structures of different sizes on the same substrate. Furthermore, it is difficult for the circuit designer to construct above mentioned semiconductor integrated circuit without increasing process cost. 
     SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, a semiconductor integrated circuit is provided. The semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an n-well resistor positioned in the substrate. The substrate includes a plurality of first isolation structures and at least one second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor is electrically isolated from the multi-gate transistor device by the second isolation structure. 
     According to another aspect of the present invention, a semiconductor integrated circuit is provided. The semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and at least one second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode formed on the substrate. The first fin structures are parallel with each other and spaced apart from each of by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode positioned on the substrate. The second gate electrode covers a portion of one first isolation structure. The LDMOS device is electrically isolated from the multi-gate transistor device by the second isolation structure. 
     According to still another aspect of the present invention, a semiconductor integrated circuit is provided. The semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode positioned on the substrate. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode positioned on the substrate. The second gate electrode covers a portion of one second isolation structure. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure. 
     According to the semiconductor integrated circuit provided by the present invention, the multi-gate transistor device having the fin structures is integrated with the n-well resistor and/or the LDMOS device, which complies with high voltage requirement. Those different devices are electrically isolated by the first isolation structures and the second isolation structures of which the sizes are different. In other words, the semiconductor integrated circuit provided by the present invention renders superior flexibility to those circuit designers. In other words, the semiconductor integrated circuit having devices of different sized can be integrated without increasing process cost due to the flexibility rendered by the semiconductor integrated circuit of the present invention. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-3B  are schematic drawings illustrating a method for manufacturing isolation structures provided by a preferred embodiment of the present invention, wherein  FIGS. 1B, 2B, and 3B  are cross-sectional views taken along Line A-A′ of  FIGS. 1A, 2A, and 3A , respectively. 
         FIG. 4  is a plane view of a semiconductor integrated circuit provided by a preferred embodiment of the present invention. 
         FIG. 5  is a cross-sectional view taken along a Line B-B′ of  FIG. 4 . 
         FIG. 6  is a cross-sectional view of a modification to the semiconductor integrated circuit provided by the present invention. 
         FIG. 7  is a cross-sectional view of another modification to the semiconductor integrated circuit provided by the present invention. 
         FIG. 8  is a cross-sectional view taken along a Line C-C′ of  FIG. 4 . 
         FIG. 9  is a cross-sectional view taken along a Line D-D′ of  FIG. 4 . 
         FIG. 10  is another modification to the semiconductor integrated circuit provided by the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIGS. 1A-3B , which are schematic drawings illustrating a method for manufacturing isolation structures provided by a preferred embodiment of the present invention.  FIGS. 1B, 2B , and  3 B respectively are cross-sectional view taken along Line A-A′ of  FIGS. 1A, 2A, and 3A . It is noteworthy that the method for manufacturing isolation structures provided by the preferred embodiment adopts an approach for manufacturing fin structures for multi-gate transistor device, namely, the spacer image transfer (SIT) approach. Therefore the isolation structures can be integrated with the fin structures for multi-gate transistor device according to the preferred embodiment. As shown in  FIG. 1A  and  FIG. 1B , a substrate  10  is provided. The substrate  10  includes at least a silicon material layer. A pad layer (not shown) can be formed on a surface of the substrate  10  if required, and the pad layer can include oxides, nitride, or any other suitable materials. Next, a mandrel layer  12   a ,  12   b , and  12   c  are formed on the substrate  10  and/or the pad layer. It is noteworthy that a width of the mandrel layer  12   a ,  12   b ,  12   c  can be different depending on different process or product requirements. For instance, the mandrel layer  12   a  includes a width W A , the mandrel layer  12   b  includes a width W B , and the mandrel layer  12   c  includes a width W C , and the width W A , the width W B  and the width W C  are different from each other in the preferred embodiment. Additionally, the mandrel layer  12   a ,  12   b ,  12   c  can include an identical or different shapes. Furthermore, a spacing distance D 1  between the mandrel layer  12   a  and the mandrel layer  12   b  can be different from a spacing distance D 2  between the mandrel layer  12   b  and the mandrel layer  12   c  as mentioned in the preferred embodiment, but the spacing distance D 1  and D 2  can be the same if required. Then, a spacer layer  14  is respectively formed on sidewalls of the mandrel layers  12   a ,  12   b , and  12   c . According to the preferred embodiment, widths of the spacer layers  14  are all the same. However, it is well-known to those skilled in the art that the spacer layers  14  of different widths can be formed if required. 
     Please refer to  FIGS. 2A and 2B . Next, the mandrel layers  12   a ,  12   b , and  12   c  are removed and followed by an etching process with the spacer layers  14  serving as an etching mask. Accordingly, the substrate  10  is etched and thus a plurality of fin structures  16  are formed. Those fin structures  16  are spaced apart from each other by a plurality of first trenches  18 . It is well-known to those skilled in the art that portions of the fin structures  16  serve as locations where the source/drain for the multi-gate transistor device are to be formed, another portions of the fin structures  16  serve as the dummy fin structures for mitigating micro-loading effect. 
     Please refer to  FIGS. 3A and 3B . It is noteworthy that the preferred embodiment adopts not only the SIT approach, but also a dual shallow trench isolation (dual STI) approach. Accordingly, unnecessary spacer layers  14  are removed after forming the first trenches  18  by etching the substrate  10 , and followed by etching portions of the first trenches  18 . Consequently, at least a second trench  20  is formed in the bottom of the first trench  18 . Then, the first trenches  18  and the second trench  20  are filled up with an insulating material and an etching back process is subsequently performed to recess top surface of the insulating material and thus a plurality of first isolation structures  22  and at least a second isolation structure  24  are formed. In this approach, a top surface of the first isolation structures  22  and a top surface of the second isolation structure  24  are coplanar (shown in  FIGS. 5 and 6 ) while in the substrate-thickness direction, a depth of the first isolation structures  22  is different from a depth of the second isolation structure  24 . Additionally, in another approach provided by the preferred embodiment, the insulating material filling up the first trenches  18  and the second trench  20  is recessed only in certain regions. Therefore, a top surface of the first isolation structures  22  in the same region and a top surface of the second isolation structure  24  in the same region are coplanar (shown in  FIG. 9 ), but top surfaces of the first isolation structures  22  indifferent regions are non-coplanar and/or top surfaces of the second isolation structures  24  in different regions are non-coplanar (shown in  FIG. 10 ). 
     Avert to another approach provided by the preferred embodiment, the first trenches  18  are filled up with an insulating material and followed by an etching back process, and thus a top surface of the insulating material in the first trenches  18  is lower than a top surface of the fin structures  16 . Then, a protecting layer is formed on the insulating material and another etching process is subsequently performed to etch portions of the spacer layers  14  and the first trench  18  not protected by the protecting layer. Therefore, a deeper second trench  20  is formed in the first trench  18 . Next, another insulating layer is provided to fill up the second trench  20 . The protecting layer is then removed, and the first isolation structures  22  and the second isolation structure  24  as shown in  FIGS. 3A and 3B  are obtained. As shown in  FIGS. 3A and 3B , a depth of the first isolation structures  22  is different from a depth of the second isolation structure  24 , and top surfaces of the first isolation structures  22  and a top of the second isolation structure  24  are non-coplanar. However, it should be easily realized by those skilled in the art that steps for forming the first isolation structures  22  and the second isolation structures  24  are never limited to the abovementioned approaches, and top surfaces of the isolation structures  22 / 24  in different regions or in the same regions can be coplanar or non-coplanar depending on different product of process requirements. 
     It is noteworthy that the depth of the second isolation structures  24  is sufficient to provide effective electrical isolation between devices or between active regions. The first isolation structures  22  are able to provide electrical isolation between the fin structures of a multi-gate transistor device. It is noteworthy that the depth of the first isolation structures  22  is smaller than the depth of the second isolation structure  24  as shown in  FIG. 3 , therefore degrees-of-freedom of the production process is improved. It is well-known to those skilled in the art that improved degrees-of-freedom of the production process means process window is improved. Accordingly, the present invention provides a method for manufacturing isolation structures adopting both the SIT approach and the dual STI approach, therefore the fin structures  16 , the first isolation structures  22 , and the second isolation structures  24  are provided with the first isolation structures  22  and the second isolation structures  24 , which include different depths, are able to render different electrical isolation required by different devices/structures. Briefly speaking, the degrees-of-freedom of the production process and design flexibility are all improved. 
     Please refer to  FIG. 4 , which is a plane view of a semiconductor integrated circuit provided by a preferred embodiment of the present invention. As shown in  FIG. 4 , the semiconductor integrated circuit  100  provided by the preferred embodiment is formed on substrate  10 , and the substrate  10  includes a multi-gate transistor device region  110 , an n-well resistor region  120 , and a LDMOS device region  130  defined thereon. It should be noted that for clarifying the spatial relationships between the fin structures and the gate structures in the multi-gate transistor device region  110 , the n-well resistor region  120 , and the LDMOS device region  130 , only the fin structures and the gate structures are shown in  FIG. 4 , while the other elements are omitted. However, those skilled in the art would easily realize that the spatial relationships between the omitted elements and the fin structures according to the following description and figures. Furthermore, it should be understood that the spatial relationship and sizes of the multi-gate transistor device region  110 , the n-well resistor region  120 , and the LDMOS device region  130  are only exemplarily provided. Those skilled in the art would easily realize that the sizes and the arrangements of the multi-gate transistor device region  110 , then-well resistor region  120 , and the LDMOS device region  130  shown in  FIG. 4  are not limited thereto. In the same concept, the amounts and arrangements of the fin structures located in the multi-gate transistor device region  110 , the n-well resistor region  120 , and the LDMOS device region  130  are only exemplarily disclosed and not limited to this. 
     Please refer to  FIG. 4  and  FIG. 5 , wherein  FIG. 5  is a cross-sectional view taken along a Line B-B′ of  FIG. 4 . As shown in  FIG. 4  and  FIG. 5 , the integrated circuit  100  provided by the preferred embodiment includes at least a multi-gate transistor device  112  positioned in the multi-gate transistor device region  110  and at least an n-well resistor  122  positioned in the n-well resistor region  120 . The multi-gate transistor device  112  and the n-well resistor  122  are electrically isolated from each other by one second isolation structure  24 . As mentioned above, since the depth of the second isolation structure  24  is deep enough, the second isolation structures  24  renders effective electrical isolation between the two devices and avoids unwanted electrical contact between the two devices. 
     As shown in  FIG. 4  and  FIG. 5 , the multi-gate transistor device  112  includes a plurality of fin structures  16 . The fin structures  16  are parallel with each other and spaced apart from each other by the first isolation structures  22 . As mentioned above, since the depth of the first isolation structures  22  is smaller than the depth of the second isolation structure  24 , the degrees-of-freedom of the fin fabrication process is improved. The multi-gate transistor device  112  further includes a gate electrode  114  positioned on the substrate  10 , and intersectionally arranged with the fin structures  16 . The electrode  114  covers a portion of each fin structure  16 , as shown in  FIG. 4  and  FIG. 5 . The gate electrode  114  includes a gate dielectric layer  114   a  and a gate conductive layer  114   b . The gate dielectric layer  114   a  includes the conventional dielectric material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). In the preferred embodiment, the gate dielectric layer  114   a  can further include high-K dielectric material such as hafnium oxide (HfO), hafnium silicate (HfSiO), or metal oxide or metal silicate exemplarily of aluminum (Al), zirconium (Zr), lanthanum (La), but not limited to this. In addition, when the gate dielectric layer  114   a  of the preferred embodiment adopts the high-K dielectric material, the present invention can be further integrated with the metal gate process. Therefore a control gate compatible to the high-K gate dielectric layer is obtained. 
     A source/drain extension region  116   a  (shown in  FIG. 8 ) can be formed in the fin structures  16  of the multi-gate transistor device  112 , a spacer  118  (shown in  FIG. 8 ) can be subsequently formed on sidewalls of the gate electrode  114 , and a source/drain  116   b  (shown in  FIG. 8 ) can be subsequently formed in the fin structures  16  at respective two sides of the gate electrode  114 . Additionally, a selective epitaxial growth (SEG) process can be performed to form an epitaxial layer (not shown) on the fin structures  116  at respective two sides of the gate electrode  114 . Since the elements such as the gate dielectric layer  114   a , the gate conductive layer  114   b , the source/drain extension regions  116   a , the spacer  118 , and the epitaxial source/drain  116   b  are well known to those skilled in the art, those details are omitted in the interest of brevity. 
     Please still refer to  FIG. 4  and  FIG. 5 . The n-well resistor  122  of the semiconductor integrated circuit  100  provided by the preferred embodiment includes an n-well  124  and at least a pair of fin structures  16 . The two fin structures  16  serve as two terminals for the n-well resistor  122 . More important, the n-well resistor  122  includes at least one first isolation structure  22  with the two fin structures  16  positioned at respective two ends of the first isolation structure  22  as shown in  FIG. 5 . Therefore, current passing from one terminal toward another terminal is forced to travel through the n-well region  124  under the first isolation structure  22  as illustrated by the solid-line arrow shown in  FIG. 5 . It is noteworthy that though the first isolation structure  22  in the n-well resistor  122  and the first isolation structures  22  in the multi-gate transistor device  112  share the identical depth, an area of the first isolation structure  22  in the n-well resistor  122  is preferably larger than an area of the first isolation structures  22  in the multi-gate transistor device  112 . The larger area of the first isolation structure  22  in the n-well resistor  122  provides longer current path and thus improves the electrical performance of the n-well resistor  122 . 
     Please refer to  FIG. 6 , which is a cross-sectional view of a modification to the semiconductor integrated circuit provided by the present invention. It should be noted that a plane view of the instant modification is identical to the plane view shown in  FIG. 4 , therefore  FIG. 4  and  FIG. 6  should be referred together. Furthermore, elements the same in the both of the modification and the aforementioned embodiment are designated by the same numerals. The difference between the modification and the aforementioned embodiment is: the n-well resistor  122  further includes at least one second isolation structure  24 , and the first isolation structure  22  and the second isolation structure  24  of the n-well resistor  122  are coplanar as shown in  FIG. 6 . As mentioned above, the depth of the second isolation structure  24  is larger than the depth of the first isolation structure  22 , therefore an even longer current path is obtained as shown  FIG. 6 . Consequently, resistance of the n-well resistor  122  is further increased. 
     Please refer to  FIG. 7 , which is a cross-sectional view of another modification to the semiconductor integrated circuit provided by the present invention. It should be noted that a plane view of the instant modification is identical to the plane view shown in  FIG. 4 , therefore  FIG. 4  and  FIG. 7  should be referred together. Furthermore, elements the same in the both of the modification and the aforementioned embodiment are designated by the same numerals. The difference between the modification and the aforementioned embodiment is: the n-well resistor  122  further includes at least one second isolation structure  24 , and the first isolation structures  22  and the second isolation structure  24  of the n-well resistor  122  are non-coplanar. As shown in  FIG. 7 , a top surface of the second isolation structure  24  is higher than a top surface of the first isolation structure  22 . On the other hand, the depth of the second isolation structure  24  is still larger than the depth of the first isolation structure  22 , therefore a longer current path is obtained as shown  FIG. 7 . Consequently, resistance of the n-well resistor  122  is further increased. 
     Please refer to  FIG. 4  and  FIGS. 8-9 , wherein  FIG. 8  is a cross-sectional view taken along a Line C-C′ of  FIG. 4  and  FIG. 9  is a cross-sectional view taken along a Line D-D′ of  FIG. 4 . As shown in  FIG. 4  and  FIG. 8 , the semiconductor integrated circuit  100  provided by the preferred embodiment includes at least the multi-gate transistor device  112  positioned in the multi-gate transistor device region  110  and at least a LDMOS device  132  positioned in the LDMOS device region  130 . The multi-gate transistor device  112  and the LDMOS device  132  are electrically isolated from each other by one second isolation structure  24 . As mentioned above, since the depth of the second isolation structure  24  is deep enough, the second isolation structure  24  renders effective electrical isolation between the two devices and avoids unwanted electrical contact between the two devices. 
     As mentioned above, the multi-gate transistor device  112  includes the plurality of fin structures  16 . The fin structures  16  are parallel with each other and spaced apart from each other by the first isolation structures  22 . As mentioned above, since the depth of the first isolation structures  22  is smaller than the depth of the second isolation structure  24 , the degrees-of-freedom of the fin fabrication process is improved. The multi-gate transistor device  112  further includes a gate electrode  114  positioned on the substrate  10 , and intersectionally arranged with the fin structures  16 . The electrode  114  covers a portion of each fin structure  16  as shown in  FIG. 8 . The gate electrode  114  includes a gate dielectric layer  114   a  and a gate conductive layer  114   b . A source/drain extension region  116   a  can be formed in the fin structures  16  of the multi-gate transistor device  112 , a spacer  118  can be subsequently formed on sidewalls of the gate electrode  114 , and a source/drain  116   b  can be subsequently formed in the fin structures  16  at respective two sides of the gate electrode  114 . 
     Please still refer to  FIG. 4  and  FIGS. 8-9 . The LDMOS device  132  provided by the preferred embodiment includes a gate electrode  134  and at least one fin structure  16 . The gate electrode  134  is intersectionally arranged with the fin structure  16 . As shown in  FIGS. 8-9 , the gate electrode  134  covers a portion of the fin structure  16 . Furthermore, the gate electrode  134  includes a gate dielectric layer  134   a  and a gate conductive layer  134   b . A spacer  138  is formed at sidewalls of the gate electrode  134 . As mentioned above, during performing the SIT process, the shapes and the widths of the fin structures  16  can be adjusted to comply different product requirements. Therefore, the width of the fin structure  16  in the LDMOS device  132  can be larger than the width of the fin structures  16  in the multi-gate transistor device  112 , but not limited to this. It should be easily realized by those skilled in the art that the shapes, the amounts, and the widths of the fin structures  16  in the LDMOS device  132  and in the multi-gate transistor device  112  can be the same if required. 
     Please refer to  FIGS. 1-3  again and simultaneously refer to  FIGS. 8-9 . According to the preferred embodiment, after forming the first trenches  22 , an insulating material can be provided to fill up the first trench  22  and then etched back. It is noteworthy that a protecting layer (not shown) can be formed in the LDMOS region  130  and thus a top surface of the insulating material in the first trench  22  in the LDMOS device region  130  is not lowered while the top surface of the insulating material in other region is lowered. Meanwhile, the first isolation structure  22  in the LDMOS region  130  is obtained as shown in  FIGS. 3 and 8 . Then, steps for forming the second trench and filling the second trench with an insulating material are subsequently performed, and thus the first isolation structures  22  in the other regions and the second isolation structure  24  are obtained as shown in  FIGS. 3 and 9 . Accordingly, though the first isolation structures  22  in the LDMOS device region  130  and the first isolation structures  22  in the other regions share the identical depth, a top surface of the first isolation structure  22  in the LDMOS device region  130  and the top surface of the first isolation structures  22  in the other regions are non-coplanar as shown in  FIGS. 8-9 . In addition, the first isolation structure  22  in the LDMOS device region  130  is taken as encompassed by and formed in the fin structure  16 . 
     Please refer to  FIGS. 8-9  again. In the preferred embodiment, the gate electrode  134  covers a portion of the first isolation structure  22 . The LDMOS device  132  includes a source region  136   a  and a drain region  136   b . Furthermore, the first isolation structure  22  is not only encompassed by the fin structures  16 , but also formed in the fin structure  16  near the drain region  136   b . Additionally, other elements such as body region or n-drift region, which are required by HV device, can be formed in the fin structure  16  of the LDMOS device  132 . Since the aforementioned elements are well known to those skilled in the art, those details are omitted in the interest of brevity. 
     Please refer to  FIG. 10 , which is another modification to the semiconductor integrated circuit provided by the present invention. It should be noted that a plane view of the instant modification is identical to the plane view shown in  FIG. 4 , therefore  FIG. 4  and  FIG. 10  should be referred together. Furthermore, elements the same in the both of the modification and the aforementioned embodiment are designated by the same numerals. The difference between the modification and the aforementioned embodiment is: The LDMOS device  132  of the modification includes one second isolation structure  24 . As mentioned above, since the depth of the second isolation structure  24  is larger than the depth of the first isolation structures  22 , a longer current path is obtained when the high-voltage current passing the second isolation structure  24 . Consequently, voltage endurance capability of the LDMOS device  132  is further improved. 
     According to the semiconductor integrated circuit provided by the present invention, the multi-gate transistor device having the fin structures is integrated with the n-well resistor and/or the LDMOS device, which complies with high voltage requirement. Those different devices are electrically isolated by the first isolation structures and the second isolation structures of which the sizes are different. In other words, the semiconductor integrated circuit provided by the present invention renders superior flexibility to those circuit designers. In other words, the semiconductor integrated circuit having devices of different sized can be integrated without increasing process cost due to the flexibility rendered by the semiconductor integrated circuit of the present invention. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.