Patent Publication Number: US-8111090-B2

Title: Voltage comparator having improved kickback and jitter characteristics

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 11/464,672, filed Aug. 15, 2006, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     STATEMENT OF GOVERNMENT INTEREST 
     This invention was made with U.S. Government support under Contract No. NBCH 3039004 awarded by the Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention. 
    
    
     BACKGROUND 
     The present invention relates generally to voltage comparator circuits in integrated circuits and, more particularly, to a voltage comparator apparatus and method having improved kickback and jitter characteristics. 
     Comparators are widely used in integrated circuits that include, for example, analog-to-digital converters and voltage signal receivers on interconnections and clock distribution lines. A voltage comparator circuit provides an indication of which of two input voltages is larger or smaller. Since a voltage comparator often senses small differences between the input voltages and generates a digital output, a large amplification may be needed. The large amplification necessary for sensing small differences may be constructed using a differential amplifier operating in a non-linear region. The differential amplifier has two transistors connected as a source-coupled pair with one of the transistors turned off and the other transistor turned on. Therefore, the amplifier has one transistor turned on even under a static condition when the transistors are in a stable non-switching state. 
     As amplification circuits, comparators are susceptible to influence of noise on the input voltages. The noise on the input voltages causes erratic switching and false triggering of the comparator output. Thus, positive feedback can be applied to decrease the decision time limiting the effects of the noise on the inputs. 
     In one type of conventional CMOS voltage comparator, cross-coupled inverters are used to latch the state of a pair of input voltages applied to opposing legs of the latch. During a reset phase of the comparator, both the output voltage nodes are biased through control switching to a stable state (e.g., at the supply voltage), and are also isolated from the ground terminal of the device so as to prevent static power dissipation. When the input voltages are to be compared during the compare phase, a strobe (clock) signal deactivates the bias control circuitry, and couples the inverters/output nodes to the input voltages. The input voltage having the higher value will cause the transistor associated therewith to conduct more strongly, thus pulling the corresponding output node down more quickly, and in turn latching the output voltages to the complementary rail values. 
     However, one disadvantage associated with CMOS comparators that have their inputs active during the compare phase is coupling of the output voltages to the input nodes. In particular, the kickback caused by the output voltage nodes when transitioning from the metastable state can in turn cause jitter on the input voltages. Unfortunately, when attempting to amplify a small input voltage differential, it is possible that the resulting jitter on the input signals can actually cause the comparator to latch the incorrect state. As result, the overall performance of the comparator is diminished, in terms of resolution (i.e., the accuracy of the comparator, in bits, given a regeneration time) and in terms of offset (i.e., the magnitude of applied input voltage differential, below which results in an indeterminate output decision). 
     Accordingly, it would be desirable to be able to provide a voltage comparator with improved immunity to output kickback and jitter on the input voltage signals. 
     SUMMARY 
     The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a comparator apparatus for comparing a first and a second voltage input. In an exemplary embodiment, the apparatus includes a pair of cross-coupled inverter devices, each of which includes a pull up device and a pull down device, with corresponding output nodes defined between the pull up and pull down devices of each inverter. A first switching device is coupled to the first voltage input and a second switching device is coupled to the second voltage input, with control circuitry configured for selective switching between a reset mode and a compare mode of operation. In the reset mode of operation, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal across the output nodes, and the pull down devices in each inverter are isolated from the respective pull up devices. In the compare mode of operation, the first and second voltage inputs are isolated from respective output nodes, and the pull down devices in each inverter are coupled to the respective pull up devices so as to allow latching of the output nodes to a corresponding full rail value. 
     In another embodiment, a method for comparing a first voltage input and a second voltage input includes coupling, during a reset mode, the first and second voltage inputs to a corresponding pair of output nodes of a comparator device, the output nodes defined between corresponding pull up and pull down devices of a pair of cross-coupled inverter devices; isolating, during the reset mode, the pull down devices of the inverter devices from the pull up devices so as to develop a differential signal across the output nodes; isolating, during a compare mode, the first and second voltage inputs from the output nodes; and recoupling, during the compare mode, the pull down devices of the inverter devices to the pull up devices so as to allow latching of the output nodes to a corresponding full rail value. 
     TECHNICAL EFFECTS 
     As a result of the summarized invention, a solution is technically achieved in which a voltage comparator is configured so as to isolate the voltage input signals from the output stage during a compare phase of the circuit, thereby improving the kickback and jitter characteristics of the device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures: 
         FIG. 1  is a schematic diagram of an existing dynamic voltage comparator circuit; 
         FIG. 2(   a ) is a schematic diagram of the equivalent circuit of the voltage comparator of  FIG. 1  while operating in a reset mode; 
         FIG. 2(   b ) is a schematic diagram of the equivalent circuit of the voltage comparator of  FIG. 1  while operating in a compare mode; 
         FIG. 3  a schematic diagram of a voltage comparator circuit in accordance with an embodiment of the invention; 
         FIG. 4(   a ) is a schematic diagram of the equivalent circuit of the voltage comparator of  FIG. 3  while operating in a reset mode; 
         FIG. 4(   b ) is a schematic diagram of the equivalent circuit of the voltage comparator of  FIG. 3  while operating in a compare mode. 
     
    
    
     DETAILED DESCRIPTION 
     Disclosed herein is a voltage apparatus and method having improved kickback and jitter characteristics. Briefly stated, the present invention embodiments are configured so as to isolate the voltage input signals from the output stage during the compare phase of the circuit. Instead, the control circuitry couples the voltage input signals to the output stage so as to generate a small differential thereon during the reset phase of the circuit. Simultaneously during the reset phase, the NFET devices of the cross-coupled inverters are isolated from the associated PFET devices, thus isolating the NFET devices from the output nodes. Such as configuration, as described more fully below, substantially improves kickback and jitter for a voltage comparator device. 
     Referring initially to  FIG. 1 , there is shown a schematic diagram of an existing dynamic voltage comparator circuit  100 . The circuit  100  features a pair of cross-coupled inverters, including PFETs P 1  and P 2 , along with NFETs N 1  and N 2 . A first output node OUT_N is defined between P 1  and P 2 , while a second output node OUT_P is defined between P 2  and N 2 , on opposing legs of the inverters. The input voltages (IN_N, IN_P) to be compared with one another are respectively coupled to the gates of NFETs N 3  and N 4 . A small differential between the voltages on IN_N and IN_P is (during a compare phase) latched by the cross-coupled inverters to a full rail voltage at the output nodes OUT_N and OUT_P. 
     As further shown in  FIG. 1 , control devices for the comparator circuit  100  include PFETs P 3 , P 4 , P 5 , P 6  and P 7 , in addition to NFET N 5 . The control devices are operated by a uniphase clock signal CLK (i.e., uniphase in that the logical complement signal is not needed for operation of the comparator). 
       FIGS. 2(   a ) and  2 ( b ) illustrate the operation of comparator circuit  100  in further detail. In the reset mode of operation, the control signal CLK is logical low, thereby resulting in the equivalent circuit depicted in  FIG. 2(   a ). That is, PFETs P 3 , P 4 , P 5 , P 6  and P 7  are active low to effectively set each point within the cross-coupled inverters to a stable state corresponding to the supply rail voltage (V DD ). Since NFET N 5  is non-conducting when CLK is low ( FIG. 1) , the output nodes are also isolated from ground. This also prevents power from being dissipated in the static mode, as current is prevented from flowing through either of the legs of the comparator circuit. 
     Then, during a desired compare operation of the voltages at IN_N and IN_P, the clock signal CLK is strobed high to result in the equivalent circuit shown in  FIG. 2(   b ). As shown, each of the control PFET devices P 3  through P 7  are deactivated by the logic high value of CLK, while control NFET device N 5  is activated to provide a ground path for the output nodes OUT_N, OUT_P. Whichever of the input voltages IN_N, IN_P is higher with respect to the other will result in the corresponding NFET (N 3 , N 4 ) to conduct more strongly than the other. In turn, one of the output nodes OUT_N. OUT_P will begin to discharge faster than the other, ultimately causing one of the output node to latch to ground and the other to latch at the rail voltage V DD . 
     As indicated above, however, the input voltages IN_N and IN_P (applied to the gates of NFETs N 3  and N 4 ) are capacitively coupled to the output nodes during the compare operation in  FIG. 2(   b ). Where the difference between the voltages at IN_N and IN_P is relatively small, the kickback of the changing voltages of OUT_N and OUT_P can possibly affect the values IN_N and IN_P to the extent that an incorrect state is ultimately latched at the output nodes. 
     Therefore, in accordance with an embodiment of the invention,  FIG. 3  is a schematic diagram of a voltage comparator circuit  300  having improved kickback and jitter characteristics. As is shown, the circuit includes a cross-coupled inverter configuration defined by PFETs P 1 , P 2  and NFETs N 1 , N 2 . However, in comparison to the conventional comparator  100  of  FIG. 1 , the control circuitry of comparator  300  is significantly different. First, it will be noted that PFETs P 3  and P 4  are respectively configured within the current path of the output nodes OUT_P, OUT_N, selectively isolating the pull up device (e.g., P 1 ) from the corresponding pull down device (e.g., N 1 ) in each inverter. In addition, an NFET N 6  (as opposed to a PFET) is configured between the output nodes, and is activated during the reset phase described below. NFETs N 7  and N 8  are connected in parallel with pull down devices N 1  and N 2  respectively. 
     As will also be noted from  FIG. 3 , the NFETs N 3 , N 4  coupled to comparator input voltages IN_N. IN_P are connected in parallel with respect to inverter NFETs N 1  and N 2 , as is the case with control NFET N 5 . PFETs P 3 , P 4  and NFETs N 5 , N 6 , N 7  and N 8  are each controlled by a uniphase clock signal CLK. 
       FIG. 4(   a ) schematically illustrates the comparator  300  in the reset mode of operation, during which time the clock signal CLK is at logic high. In this case, it will be noted that because PFETs P 3  and P 4  are switched off during reset, the NFET portions (N 1 , N 2 ) of each inverter are isolated from the corresponding PFET portions (P 1 , P 2 ). Any residual voltage appearing across isolated NFETs N 1  and N 2  are also cleared out by being shorted to ground through activation of N 7  and N 8  ( FIG. 3) . Moreover, since control NFET N 5  is conductive, the input voltages IN_N and IN_P are actually coupled to the comparator output nodes OUT_P, OUT_N during the reset phase. Furthermore, since control NFET N 6  is conductive, output nodes OUT_P and OUT_N are coupled to one another through a small resistance, r, which represents the slight resistance of N 6  when conducting. 
     In other words, the combination of N 3 , N 4 , P 1 , P 2  and r effectively creates a low gain amplifier during the reset phase of operation. Thus, a differential signal between IN_N and IN_P is actually stored in the output nodes OUT_P and OUT_N during the reset phase of operation. Subsequently, during the compare phase of operation, the developed differential seen at the output nodes OUT_P and OUT_N is immediately latched by the cross-coupled inverters, which are once again “fully connected.” Moreover, the latching takes place while the inputs IN_N and IN_P are decoupled from the output nodes, thereby providing significant protection of the inputs IN_N and IN_P from kickback generated at the output nodes OUT_P and OUT_N during latching to the full rail voltages. 
     The equivalent circuit diagram of the comparator  300  during the compare phase is shown in  FIG. 4(   b ). In the compare phase, CLK is low, thus deactivating NFETs N 3 , N 4  and N 5  so as to isolate the inputs IN_N and IN_P from the output nodes. In addition, N 6  is deactivated while PFETs P 3  and P 4  are activated by the low clock signal, thereby recoupling the pull up and pull down devices of the inverters. So long as a differential signal was established at OUT_P and OUT_N during the reset phase, the inverters would not be at a metastable state (strictly speaking) upon activation of the compare phase. Thus, for example, if the voltage at OUT_P were to be slightly less than the voltage at OUT_N during reset, then OUT_P would be pulled down to ground and OUT_N would be pulled up to the rail voltage upon a transition to the compare phase shown in  FIG. 4(   b ). 
     Thus configured, comparator circuit  300  offers significantly less jitter due to kickback on the output nodes, as well as improved offset characteristics. Although comparator  300  uses bias current during the static reset phase to store the input voltage differential on the output nodes (representing a tradeoff in terms of static power dissipated), the peak power dissipated is actually lower than the conventional dynamic comparator  100  of  FIG. 1 . 
     While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.