Patent Publication Number: US-2002009004-A1

Title: Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The present invention relates to a semiconductor memory device and a semiconductor memory device testing method and, more particularly, to a double data rate synchronous dynamic random access memory (DDR SDRAM) and a testing method thereof.  
       [0003] 2. Description of the Background Art  
       [0004] Semiconductor memory devices have their performance verified by a testing device called tester at a final stage of their production process.  
       [0005]FIG. 15 is a diagram for use in explaining performance verification by a conventional tester.  
       [0006] With reference to FIG. 15, a tester  202  applies, to a memory device  204  to be tested, control signals /RAS, /CAS, /WE, an address signal ADD and a data input signal DIN to observe a data output signal DOUT output by the memory device  204 .  
       [0007] The tester  202  includes a timing generator  206  for generating a timing reference signal for the test, a signal generator  208  for outputting the control signals, the address signal and the data input signal in response to the output of the timing generator  206 , and a determination  210  for observing the data output signal DOUT output by the memory device  204  with the output of the timing generator  206  as a reference of time to determine whether the memory device  204  operates normally.  
       [0008]FIG. 16 is an operation waveform diagram for use in explaining a conventional performance verification test of a semiconductor memory device.  
       [0009] With reference to FIGS. 15 and 16, at time t 1 , the tester  202  causes the control signal /RAS to fall, so that the memory device  204  accepts a row address signal X. Then, The control signal /WE is set at a logical low or “L” level by the tester  202  and the memory device  204  is supplied with data DATA to be written by the data input signal DIN.  
       [0010] At time t 2 , the control signal /CAS is caused to fall and the memory device  204  responsively accepts a column address Y. Then, the memory device  204  writes the write data DATA in a memory cell designated by the row address and the column address.  
       [0011] Such writing cycle will be repeated as many times as the number corresponding to the memory capacity.  
       [0012] Next, a reading cycle for reading data will be described. When data writing ends, the control signal /RAS is caused to fall at time t 3 , so that the row address X is accepted into the memory device  204 . Subsequently, the control signal /WE is set at a logical high or “H” level to designate data reading of the memory device  204 .  
       [0013] At time t 4 , the control signal /CAS is caused to fall, so that the column address Y is accepted into the memory device  204 .  
       [0014] Responsively, at time t 5 , from the memory cell designated by the row address X and the column address Y, the read data DATA is transmitted as a data output signal from the memory device  204  to the tester  202 . Determination is made by the determination unit  210  whether the output data coincides with the written data. Thus, determination is made whether the memory device  204  is defective or not.  
       [0015] In recent years, with the speed-up of semiconductor memory devices, there has appeared a synchronous semiconductor memory device whose data input/output is controlled in synchronization with a clock signal, that is, a synchronous dynamic random access memory (SDRAM) and further, a higher-speed DDR SDRAM has appeared which transmits data at a data rate equivalent to both of leading and trailing edges of a clock signal.  
       [0016]FIG. 17 is a waveform diagram for use in explaining one of standards for a DDR SDRAM.  
       [0017] With reference to FIG. 17, the DDR SDRAM outputs a data signal DQ, as well as outputting a strobe signal DQS in synchronization with the data signal DQ. The strobe signal DQS is used as a reference signal for accepting the data signal DQ by a controller or the like, which receives data output by a memory device.  
       [0018] The strobe signal DQS is a signal for use as a solution of a skew between a clock signal and a data signal. Since the data signal DQ and the strobe signal DQS have the same signal transmission direction, skew is reduced. To enhance the effect, a transmission path of the data signal DQ and that of the strobe signal DQS on a printed-circuit board are formed to be approximately equal in length.  
       [0019] With the timing of a rise and a fall of the strobe signal DQS output from the DDR SDRAM as an origin, timing of output of the data signal DQ output similarly by the DDR SDRAM is defined. One of the standards for the timing is called tDQSQ standard.  
       [0020] For example, FIG. 17 shows a case where four data D 1  to D 4  is successively output from the DDR SDRAM. A time difference between a time of a transition from the data D 1  to the data D 2  when the data is successively output and a time of the strobe signal DQS is defined by the tDQSQ standard. A time tDQSQmax denotes a maximum allowed time of delay in the data D 1  determination behind a time of a rise of the strobe signal DQS. In other words, the data D 1  should be defined within a time denoted by tDQSQmax after the time of a rise of the strobe signal DQS and similarly the data D 2  should be defined within the tDQSQmax after a time of a fall of the strobe signal DQS.  
       [0021] On the other hand, there is a case where output of the data signal DQ is earlier in time than an edge of the strobe signal DQS. In this case, a time of output of the data D 3  should not be earlier by a time denoted by a tDQSQ min than an edge of the strobe signal DQS.  
       [0022] The tDQSQ standard should be satisfied in all the output cycles of data from the memory device. In a case of a 256-Mbit 8-bit-basis DDR SDRAM, the standard needs to be satisfied at each of 32 mega cycles (more precisely 33,554,432 cycles) equivalent to the number of memory cells corresponding to the respective terminals.  
       [0023] It is necessary to examine whether a manufactured device meets this standard or not. In a case of a DDR SDRAM, however, a relative time difference between a strobe signal DQS output and a data signal DQ output should be verified. The strobe signal DQS providing a reference time for the verification has a jitter component with respect to a clock signal applied to the DDR SDRAM. Therefore, the strobe signal DQS is not always output at fixed timing for a clock signal. Tester accordingly needs to simultaneously measure a time of a rise or a fall of the strobe signal DQS and a time when the data signal DQ changes and obtain a difference between the two times to examine the tDQSQ standard.  
       [0024] However, as described with reference to FIG. 14, in a conventional tester, it is a common practice to set a determination reference time according to a timing generator  126  to examine whether the data signal DQ is desired data, that is, a “H” level or a “L” level is output, from the memory device at the determination reference time. The tester then indicates the result as PASS/FAIL. Thus structured tester has a difficulty in measuring a data signal change point, with such a signal having a jitter component changing every cycle as the strobe signal DQS described in the foregoing as an origin.  
       [0025] Speed and data rate of semiconductor memory devices have been increased year by year. In recent years, higher and higher precision is required of a standard for timing between a strobe signal and data for the purpose of transferring data at a high speed. For example, while demanded precision has been conventionally on the order of nanosecond (ns), recent DDR SDRAM is required to have a precision on the order of picoseconds (ps). In the above-described tDQSQ standard, a precision within 750 ps, for example, is demanded. Under these circumstances, semiconductor manufacturers need to ensure the standard by stringent examination taking a test margin into consideration.  
       [0026] In other words, for an ordinary tester to measure the tDQSQ standard of DDR SDRAMs, the tester should have an extremely high level of performance. As long as a device is defined by the standard, it is necessary to observe whether the device has performance meeting the standard or not.  
       SUMMARY OF THE INVENTION  
       [0027] An object of the present invention is to provide a semiconductor memory device capable of executing a performance test related to a timing standard for a data signal and a strobe signal with ease and a method of testing a semiconductor memory device.  
       [0028] In summary, the present invention relates to a semiconductor memory device having a storage unit and a test circuit. The storage unit includes a plurality of memory cells and successively outputs data held in the plurality of memory cells and outputs a strobe signal whose signal waveform has a leading edge and a trailing edge synchronizing with the data output successively. The test circuit accepts data in response to the strobe signal.  
       [0029] The test circuit includes a first transmission gate unit responsive to a strobe signal to become conductive to transmit data and a first holding unit for holding data transmitted by the first transmission gate unit.  
       [0030] According to another aspect, the present invention relates to a subsidiary device for connecting, to a testing device, a semiconductor memory device which includes a plurality of memory cells and successively outputs data held in the plurality of memory cells and outputs a strobe signal whose signal waveform has a leading edge and a trailing edge synchronizing with data output successively, which subsidiary device includes first, second and third terminals and a test circuit.  
       [0031] The first and the second terminals receive data and a strobe signal from the semiconductor memory device, respectively.  
       [0032] The test circuit accepts data applied through the first terminal in response to the strobe signal applied through the second terminal. The test circuit includes a first transmission gate unit responsive to the strobe signal to become conductive to transmit data and a first holding unit for holding data transmitted by the first transmission gate unit. The third terminal transmits the output of the first holding unit to the testing device.  
       [0033] According to a further aspect of the present invention, the present invention relates to a testing device for testing a semiconductor memory device which includes a plurality of memory cells and successively outputs data held in the plurality of memory cells and outputs a strobe signal whose signal waveform has a leading edge and a trailing edge synchronizing with data output successively, which testing device includes a timing generator, a signal generator, a test circuit and a determination unit.  
       [0034] The timing generator outputs a timing reference for a test. The signal generator outputs a control signal to be applied to the semiconductor memory device and data to be stored therein in response to the output of the timing generator.  
       [0035] The test circuit accepts data in response to the strobe signal. The test circuit includes a first transmission gate unit responsive to the strobe signal to become conductive to transmit data and a first holding unit for holding data transmitted by the first transmission gate unit. The determination unit determines whether the output of the first holding unit coincides with an expected value.  
       [0036] Accordingly, a main advantage of the present invention is to facilitate verification by a testing device that a strobe signal and data have a predetermined relative time relation by latching data at a test circuit in practice.  
       [0037] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0038]FIG. 1 is a schematic block diagram for use in explaining a structure of a semiconductor memory device  1  according to a first embodiment of the present invention.  
     [0039]FIG. 2 is a schematic block diagram showing a structure of a memory circuit  2  illustrated in FIG. 1.  
     [0040]FIG. 3 is a block diagram for use in explaining a structure of a test circuit  3  in FIG. 1.  
     [0041]FIG. 4 is a circuit diagram showing a structure of a switch circuit SW 2  in FIG. 3.  
     [0042]FIG. 5 is a circuit diagram showing a structure of a data latch circuit  32  in FIG. 3.  
     [0043]FIG. 6 is a circuit diagram for use in explaining a structure of a delay circuit  44  illustrated in FIG. 5.  
     [0044]FIG. 7 is a diagram for use in explaining basic operation of the data latch circuit  32 .  
     [0045]FIG. 8 is a waveform diagram for use in explaining operation conducted when output of a data signal DQ delays behind a strobe signal DQS.  
     [0046]FIG. 9 is a waveform diagram for use in explaining a test for determining whether a device meets a tDQSQmin standard.  
     [0047]FIG. 10 is a flow chart for use in explaining a performance verification test of a test circuit.  
     [0048]FIG. 11 is a waveform diagram for use in explaining operation at Steps S 3  to S 6  in FIG. 10.  
     [0049]FIG. 12 is a conceptual diagram for use in explaining a connection between a memory device and a tester.  
     [0050]FIG. 13 is a diagram showing a structure of a tester jig  104 .  
     [0051]FIG. 14 is a block diagram for use in explaining a third embodiment of the present invention.  
     [0052]FIG. 15 is a diagram for use in explaining performance verification by a conventional tester.  
     [0053]FIG. 16 is a waveform diagram of operation for use in explaining a performance verification test of a conventional semiconductor memory device.  
     [0054]FIG. 17 is a waveform diagram for use in explaining one of standards for DDR SDRAM. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
     [0055] In the following, embodiments of the present invention will be described in detail with reference to the drawings. Like numerals in the drawings represent the same or corresponding parts.  
     [0056] [First Embodiment] 
     [0057]FIG. 1 is a schematic block diagram for use in explaining a structure of a semiconductor memory device  1  according to a first embodiment of the presents invention.  
     [0058] With reference to FIG. 1, the semiconductor memory device  1  includes a memory circuit  2  which conducts storage operation as a semiconductor memory device and a test circuit  3  for facilitating a test. The test circuit  3  receives external control signals TD 1  and TD 2 , sends and receives a strobe signal DQS, data signals DQ 0  to DQ 3  and an address signal TAn to and from external sources and sends and receives a strobe signal IDQS and data signals IDQ 0  to IDQ 3  to and from the memory circuit  2 . In addition, the test circuit  3  applies an address signal An to the memory circuit  2 . The memory circuit  2  receives internal address signals A 0  to An−1, control signals /CS, /RAS, /CAS and /WE, a clock signal CLK and a clock enable signal CKE.  
     [0059]FIG. 2 is a schematic block diagram showing the structure of the memory circuit  2  illustrated in FIG. 1.  
     [0060] With reference to FIG. 2, the memory circuit  2  includes memory array banks  14 # 0  to  14 # 3  each having a plurality of memory cells arrayed in matrix, an address buffer  5  for accepting the address signals A 0  to An in synchronization with a clock signal CLKI and outputting an internal row address X and an internal column address Y, a clock buffer  4  for receiving the external clock signal CLK and clock enable signal CKE to output clock signals CLKI and CKLQ for use in the memory circuit  2 , and a control signal input buffer  6  for accepting the control signals /CS, /RAS, /CAS and /WE in synchronization with the clock signal CLKI.  
     [0061] Each of the memory array banks  14 # 0  to  14 # 3  includes memory cells MC arranged in a matrix, a plurality of word lines WL provided corresponding to the rows of the memory cells MC and a plurality of bit line pairs BLP provided corresponding to the columns of the memory cells MC. In FIG. 2, each one of the memory cells MC, the word lines WL and the bit line pairs BLP are illustrated as a representative.  
     [0062] The memory circuit  2  further includes a control circuit for receiving an internal address signal from the address buffer  5  and receiving control signals int.RAS, int.CAS and int.WE synchronized with a clock signal from the control signal input buffer  6  to output a control signal to each block in synchronization with the clock signal CKLI, and a mode register for holding an operation mode recognized by the control circuit. In FIG. 2, the control circuit and the mode register are illustrated as one block denoted as block  8 .  
     [0063] The control circuit includes a bank decoder for designating a bank based on an address signal and a command decoder for conducting decoding in response to the control signals int.RAS, int.CAS and int.WE.  
     [0064] The memory circuit  2  further includes row decoders provided corresponding to the memory array banks  14 # 0  to  14 # 3  for decoding the row address signal x applied from the address buffer  5 , and word drivers for driving a row (word line) in the memory array banks  14 # 0  to  14 # 3  whose address is designated to enter a selected state in response to an output signal of the row decoder. In FIG. 2, each one of row decoders and one of word drivers are paired and illustrated as one of the blocks denoted as blocks  10 # 0  to  10 # 3 .  
     [0065] The memory circuit  2  further includes column decoders  12 # 0  to  12 # 3  for decoding the internal column address signal Y applied from the address buffer  5  to generate a column selecting signal, and sense amplifiers  16 # 0  to  16 # 3  for sensing and amplifying data of the memory cells connected to a selected row of the memory array banks  14 # 0  to  14 # 3 .  
     [0066] The memory circuit  2  further includes an input buffer  22  for receiving external write data to generate internal write data, a write driver for amplifying internal write data from the input buffer  22  to transmit the amplified data to a selected memory cell, a preamplifier for amplifying data read from a selected memory cell, and an output buffer  20  for conducting buffering processing with respect to data from the preamplifier and externally outputting the processed data.  
     [0067] The preamplifiers and write drivers are provided corresponding to the memory array banks  14 # 0  to  14 # 3 . In FIG. 2, one of the preamplifiers and the write drivers are paired and illustrated as one of the blocks denoted as blocks  18 # 0  to  18 # 3 .  
     [0068] The input buffer  22  accepts data DQ 0  to DQ 15  externally applied through the terminal in response to strobe signal STRB 1  and STRB 2  complementary to each other. The strobe signals STRB 1  and STRB 2  are signals as a reference for a data acceptance time which are output in synchronization with data by other semiconductor device or the like to the memory circuit  2 . The memory circuit  2  receives the strobe signals STRB 1  and STRB 2  which are transmitted from the external source in parallel to the data and applied to the two terminals, respectively, and takes the signals as a data signal acceptance reference.  
     [0069] The output buffer  20  outputs the data DQ 0  to DQ 15  in synchronization with the clock signal CLKQ when the memory circuit  2  externally outputs data, as well as externally outputting the strobe signals STRB 1  and STRB 2  for use in acceptance of the data signals by other semiconductor device.  
     [0070]FIG. 3 is a block diagram for use in explaining the structure of the test circuit  3  illustrated in FIG. 1.  
     [0071] With reference to FIG. 3, the test circuit  3  includes a data latch circuit  32  for latching data at the time of a test and switch circuits SW 1  to SW 4 .  
     [0072] The data latch circuit  32  accepts a data signal IND in response to a strobe signal INS, latches the result and outputs the same as an output signal DOUT. In addition, the data latch circuit  32  receives input of control signals TD 1  and TD 2  for controlling a delay time amount of the strobe signal and the data signal which will be described later and outputs a degenerated determination result signal TDOUT for use in examining the data latch circuit.  
     [0073] The switch circuit SW 2  is connected to three signal lines which transmit the strobe signals IDQS, DQS and INS, respectively. The switch circuit SW 3  is connected to a signal line L 12  on which the data signals IDQ 0  to IDQ 3  are transmitted, a signal line L 13  on which the data signal IND is transmitted and a signal line L 11 . The switch circuit SW 1  is connected to the signal line L 11 , a signal line L 23  for transmitting the data output signal DOUT and a signal line L 22  for transmitting the data signals DQ 0  to DQ 3 . The switch circuit SW 4  is connected to a signal line L 33  on which the determination result signal TDOUT is transmitted, a signal line L 31  on which the address signal TAn is transmitted and a signal line L 32  on which the address signal An is transmitted.  
     [0074]FIG. 4 is a circuit diagram showing the structure of the switch circuit SW 2  in FIG. 3.  
     [0075] With reference to FIG. 4, the switch circuit SW 2  includes a MOS transistor  34  connected between a signal line L 1  and a signal line L 2  and having a gate which receives a signal T 12 , a MOS transistor  36  connected between the signal line L 2  and a signal line L 3  and having a gate which receives a signal T 23 , and a MOS transistor  38  connected between the signal line L 1  and the signal line L 3  and having a gate which receives a signal T 13 .  
     [0076] Although FIG. 4 illustrates an example of a switch circuit composed of three MOS transistors, the circuit may have other structure as long as it enables two of the signal lines L 1 , L 2  and L 3  to be selectively connected.  
     [0077] In addition, since the switch circuits SW 1 , SW 3  and SW 4  shown in FIG. 3 have the same structure as that of the switch circuit SW 2  illustrated in FIG. 4 or have a structure in which a plurality of bits of the switch circuits SW 2  are provided in parallel, description thereof will not be repeated.  
     [0078]FIG. 5 is a circuit diagram showing the structure of the data latch circuit  32  in FIG. 3.  
     [0079] With reference to FIG. 5, the data latch circuit  32  includes a delay circuit  42  whose delay amount is set by the control signal TD 2  and which delays the data signal IND and outputs the delayed signal, and a delay circuit  44  whose delay amount is set by the control signal TD 1  and which delays the strobe signal INS and outputs the delayed signal.  
     [0080] The data latch circuit  32  further includes latch circuits  46 # 0  to  46 # 3  for internally latching the output of the delay circuit  42  in response to the output of the delay circuit  44  and transmission gates  48 # 0  to  48 # 3  for outputting the outputs of the latch circuits  46 # 0  to  46 # 3  as the data output signal DOUT in response to the output of the delay circuit  44 .  
     [0081] The data latch circuit  32  further includes latch circuits  50 # 0  to  50 # 3  for latching the output of the delay circuit  42  in response to the output of the delay circuit  44 , transmission gates  52 # 0  to  52 # 3  for outputting the outputs of the latch circuits  50 # 0  to  50 # 3  as the data output signal DOUT in response to the output of the delay circuit  44 , and a gate circuit  54  for regenerating four bits included in the data output signal DOUT and outputting the regenerated signal as the determination result signal TDOUT.  
     [0082] The transmission gates  48 # 0  to  48 # 3  are composed of P channel MOS transistors which become conductive when the output of the delay circuit  44  is at a “L” level. The transmission gates  52 # 0  to  52 # 3  are composed of N channel MOS transistors which become conductive when the output of the delay circuit  44  is at a “H” level.  
     [0083] The latch circuit  46 # 0  includes an N channel MOS transistor  62  which becomes conductive in response to the output of the delay circuit  44  to transmit the output of the delay circuit  42  to a node N 1 , a buffer circuit  66  having an input connected to the node N 1  and an output connected to a node N 2 , and a buffer circuit  64  having an input connected to the node N 2  and an output connected to the node N 1 . The latch circuits  46 # 1  to  46 # 3  have the same structure as that of the latch circuit  46 # 0  and description thereof will not be repeated.  
     [0084] The latch circuit  50 # 0  includes a transmission gate  68  which becomes conductive in response to the output of the delay circuit  44  to transmit the output of the delay circuit  42  to a node N 3 , a buffer circuit  70  having an input connected to the node N 3  and an output connected to a node N 4 , and a buffer circuit  72  having an input connected to the node N 4  and an output connected to the node N 3 . The latch circuits  50 # 1  to  50 # 3  have the same structure as that of the latch circuit  50 # 0  and description thereof will not be repeated.  
     [0085] In the data latch circuit  32 , output from the node N 2  is the output signal of the latch circuit  46 # 0 . The output signal of the latch circuit  50 # 0  is output from the node N 4 .  
     [0086] The data latch circuit  32  is an example of a circuit adapted to a DDR SDRAM having a 4-bit output, and other components than the delay circuit  44  and the gate circuit  54  are provided four each corresponding to the output bits of the DDR SDRAM. The latch circuits  46  and  50  and the transmission gates  48  and  52  are provided as many as a number n each when the DDR SDAM has an n-bit output.  
     [0087]FIG. 6 is a circuit diagram for use in explaining the structure of the delay circuit  44  illustrated in FIG. 5.  
     [0088] With reference to FIG. 6, the delay circuit  44  includes delay elements  82  to  86  connected in series for receiving an input signal IN applied to a node N 5 , a switch  88  connected between the node N 5  and a node N 9  from which an output signal OUT is output and responsive to a control signal SO to become conductive, a switch  90  connected between a node N 6  to which the output of the delay element  82  is applied and the node N 9  and responsive to a control signal S 1  to become conductive, a switch  92  connected between a node N 7  to which the output of the delay element  84  is applied and the node N 9  and responsive to a control signal S 2  to become conductive, and a switch  94  connected between a node N 8  to which the output of the delay element  86  is applied and the node N 9  and responsive to a control signal Sn to become conductive.  
     [0089] Each of the delay elements  82  to  86  includes an even-number of stages of inverters connected in series. The control signals S 0  to Sn are control signals included in the control signal TD 1 .  
     [0090]FIG. 7 is a diagram for use in explaining basic operation of the data latch circuit  32 .  
     [0091]FIG. 8 is a waveform diagram for use in explaining a test for verifying a tDQSQmax among tDQSQ standards.  
     [0092] With reference to FIGS. 7 and 8, from the DDR SDRAM, data D 1  to D 4  is successively output and the strobe signal DQS in synchronization with the data is output.  
     [0093] Description will be made of a case where at time t 1 , the strobe signal DQS rises from a “L” level to a “H” level and later at time t 2 , the data D 3  synchronized with the rise of the strobe signal is output.  
     [0094]FIG. 8 shows a case where a switching point where a transition is made from the data D 2  to the data D 3  falls on a limiting point of tDQSQmax. Therefore, for satisfying the tDQSQmax, a switching point where the transition from the data D 2  to the data D 3  is made should exist between the time t 1  when the leading edge of the strobe signal DQS is input and the time t 2  after a lapse of the time tDQSQmax from the time t 1 . In other words, when “H” is output as the data D 2  and “L” is output as the data D 3 , the tDQSQmax standard is satisfied if the data signal DQ is at a “H” level at the time t 1  and the data signal DQ is at a “L” level at the time t 2 . Conversely, if at the time t 2 , the data signal DQ is at a “H” level, the device fails to satisfy the standard for the time tDQSQmax. Accordingly, with the delay circuit  42  having no delay, setting the delay circuit  44  to have a delay of tDQSQmax by the control signal TD 1  which designates a delay amount results in rendering the transmission gate  68  non-conductive at the time t 3 , so that data of the latch circuit  50  is defined and output to the tester. The output to the tester is in practice selectively applied to the tester when the output of the delay circuit  44  is at a “H” level because of the transmission gate  52  provided at the output part of the latch circuit  50  in FIG. 5.  
     [0095] As a result, with the strobe signal DQS delayed by tDQSQmax, making the latch circuit  50  to hold data to enable the tester to determine whether the latch circuit holds the expected “L” of the data D 3  or whether the latch circuit  50  holds “H” as the contents of the data D 2  when the standard is not satisfied leads to determination whether the standard for tDQSQmax is satisfied or not.  
     [0096] In the foregoing description, timing is all defined at a point where the amplitude is 50%.  
     [0097] Next, description will be made of tDQSQmin among the tDQSQ standards.  
     [0098]FIG. 9 is a waveform diagram for use in explaining a test for determining whether a standard for tDQSQmin is satisfied or not.  
     [0099] With reference to FIGS. 7 and 9, consideration will be given to a case where the data signal DQ is output before the strobe signal DQS as indicated by a solid line. The figure illustrates a case where a transition point from the data D 2  to the data D 3  falls on the position limit satisfying tDQSQmin.  
     [0100] In other words, assuming a time earlier by the time of tDQSQmin than the time t 1  when the strobe signal DQS rises to be t 2 , for satisfying the standard for tDQSQmin, the transition point from the data D 2  to the data D 3  should exist between the time t 2  and t 1 .  
     [0101] In a case, for example, where “H” is output as the data D 2  and “L” is output as the data D 3 , the device is considered to satisfy the standard for tDQSQmin when the data signal DQ is at a “L” level at the time t 1  and the data signal DQ is at a “H” level at the time t 2 . Conversely, when at the time t 2  the data signal DQ is already at a “L” level, the device fails to meet the standard for the time tDQSQmin.  
     [0102] For verifying the foregoing, for example, data held by the latch circuit  50  may be observed, with the delay amount of the delay circuit  44  of FIG. 7 set to zero and the data signal DQ delayed by the time tDQSQmin by the delay circuit  42 . As a result, if it is determined that when the transmission gate  68  becomes non-conductive at a leading edge of the strobe signal DQS at the time t 1  to define the data of the latch circuit  50 , “H” as the contents of the data D 2  is held, the standard for tDQSQmin is satisfied.  
     [0103] Although the foregoing description has been made of a case where “H” and “L” are output as the data D 2  and D 3 , respectively, in order to realize this state, it is necessary to write data in the memory array in advance to conduct reading control such that “H” is output as an expected value of the data D 2  and “L” is output as an expected value of the data D 3 .  
     [0104] In addition, although the verification test has been described for the determination by the latch circuit whether the tDQSQ standard is satisfied or not, in a case where a test circuit including the latch circuit in question is provided in the semiconductor memory device, performance verification of the latch circuit part should be conducted in advance.  
     [0105]FIG. 10 is a flow chart for use in explaining a performance verification test of the test circuit.  
     [0106] With reference to FIGS. 3 and 10, the test is started as Step S 1 . At Step S 2 , an internal switch is switched for checking the test circuit. More specifically, in the switch circuit SW 2 , the signal line L 1  and the signal line L 3  are connected and the signal line L 2  is disconnected. In the switch circuit SW 1 , the signal line L 11  and the signal L 22  are connected and the signal line L 23  is disconnected. In the switch circuit SW 3 , the signal line L 11  and the signal line L 13  are connected and the signal line L 12  is disconnected. In the switch circuit SW 4 , the signal line L 33  and the signal line L 31  are connected and the signal line L 32  is disconnected. Then, the control signals TD 1  and TD 2  are set at an initial value.  
     [0107] Subsequently, at Step S 3 , a signal is applied for checking the test circuit. More specifically, the strobe signal DQS applied from the tester is supplied to the data latch circuit  32  as a strobe signal INS. In addition, the data signals DQ 0  to DQ 3  applied from the tester are supplied to the data latch circuit as the data signal IND. Then, the data latch circuit  32  outputs the determination result signal TDOUT which will be output as the output signal TAn from one of address pins. Then, at Step S 4 , determination is made whether an expected value and the signal TAn coincide with each other or not by the tester to proceed to Step S 5 . At Step S 5 , if verification of the test circuit performance is yet to be finished, the routine proceeds to Step S 6  where change of a delay amount is instructed by the control signals TD 1  and TD 2 . Then, Steps S 3 , S 4  and S 5  will be repeated.  
     [0108] When at Step S 5  the test circuit performance verification is finished, the routine proceeds to Step S 7  to conduct switching of the internal switch for checking the memory circuit. More specifically, in the switch circuit SW 2 , the signal line L 2  and the signal line L 3  are connected. As a result, the strobe signal IDQS output from the memory circuit is applied to the data latch circuit  32  as the strobe signal INS. In the switch circuit SW 3 , the signal line L 12  and the signal line L 13  are connected and the signal line L 11  is disconnected. As a result, the data signals IDQ 0  to IDQ 3  output from the memory circuit are applied to the data latch circuit  32  as the data signal IND.  
     [0109] In the switch circuit SW 1 , the signal line L 23  and the signal line L 22  are connected, so that the data output signal DOUT output from the data latch circuit is output to the tester as the data signals DQ 0  to DQ 3 . In the switch circuit SW 4 , the signal line L 32  and the signal line L 31  are connected and the signal line L 33  is disconnected. As a result, the address signal TAn applied from the tester is supplied to the memory circuit as the address signal An.  
     [0110] Subsequently at Step S 8 , the latch test of the DQ signal by the test circuit as described in FIGS. 8 and 9 is conducted. The device is considered to meet the tDQSQ standard when a right expected value is obtained by the latch test in either case of tDQSQmax and tDQSQmin. It is preferable to verify that the latch circuit holds an expected value properly when the delay circuit has no delay and then to conduct a test for tDQSQmax and tDQSQmin with corresponding delays applied.  
     [0111]FIG. 11 is a waveform diagram for use in explaining operation at Steps S 3  to S 6  of FIG. 10.  
     [0112] First, at the part A, delay the strobe signal DQS applied from the tester by the internal delay circuit from time t 1  to the time t 2 . Then, at the time t 2 , in the latch circuit, the transmission gate  68  of FIG. 7 is closed to define the latch circuit, so that “H” is output as the output signal DOUT to the tester. Then, change the delay amount to provide a waveform which is obtained when both of the delay circuits of the strobe signal and the data signal applied to the latch circuit are set to have no delay as shown in the part B, and further change the delay amount to then control such that the data signal DQ is delayed behind the strobe signal by the delay circuit  42  as shown in the part C. Then, at time t 4 , the data signal DQ applied so as to change in synchronization with the strobe signal DQS will be applied to the latch circuit with its transition point changed from the time t 4  to time t 5 . Then, at the latch circuit, data is defined in response to a rise of the strobe signal DQS at time t 4  and “L” is output as the output signal DOUT of the data. Thus, normal operation of the test circuit is verified when after a gradual change of a data delay amount, the output signal DOUT is inverted before and after the state shown as the part B.  
     [0113] As described in the foregoing, provision of the test circuit in a semiconductor memory device which latches the data signal DQ with the strobe signal DQS of the memory device as a trigger and transmits the latched signal to the tester for determination enables examination whether the device satisfies the tDQSQ standard or not.  
     [0114] [Second Embodiment] 
     [0115] In the first embodiment, the semiconductor memory device is designed to contain a test circuit, the device may be designed differently.  
     [0116]FIG. 12 is a conceptual diagram for use in explaining a connection between a memory device and a tester.  
     [0117] With reference to FIG. 12, a tester  106  and a memory device  102  are in general connected by a tester jig  104 . The tester jig  104  is in many cases manufactured for each kind of semiconductor memory device. For example, since a semiconductor memory device varies in the number of pins and package configuration, socket and the like corresponding to its configuration are mounted on the tester jig. The tester jig may be mounted with such a test circuit  108  as described in the first embodiment.  
     [0118]FIG. 13 is a diagram showing the structure of the tester jig  104 .  
     [0119] With reference to FIG. 13, the tester jig  104  includes a socket  110  and a test circuit  108  corresponding to the configuration of the memory device  102 . The socket  110  is provided with connection terminals  112  corresponding to the terminals of the memory device  102 . Between the socket  110  and the test circuit  108 , data signals DQ 0  to DQ 3  and a strobe signal DQS are sent and received. The socket  110  is provided with a terminal group P 1  to which control signals /RAS, /CAS and the like are applied, a terminal group P 2  to which the data signals DQ 0  to DQ 3  and the strobe signal DQS are applied and a terminal group P 3  to which control signals TD 1  and TD 2  for designating a delay amount of the test circuit  108  are applied. The structure of the test circuit  108  is the same as that of the test circuit  3  illustrated in FIG. 3 and description thereof will not be repeated. In a case where the test circuit is provided on the tester jig, since there is no need of examining the data latch circuit each time, no structure is necessary for outputting a determination result signal TDOUT indicative of an examination result of the data latch circuit as a part of an address signal.  
     [0120] As described in the foregoing, provision of the test circuit in the tester jig to enable the tester to determine a latching result of the test circuit results in attaining the same effect as that obtained by the first embodiment.  
     [0121] [Third Embodiment] 
     [0122] While the first embodiment shows a case where the test circuit is provided in the semiconductor memory device and the second embodiment shows a case where the test circuit is provided on the tester jig, the test circuit may be provided in other parts.  
     [0123]FIG. 14 is a block diagram for use in explaining a third embodiment of the present invention.  
     [0124] With reference to FIG. 14, a test circuit is provided inside a tester  122  in the third embodiment. The tester  122  includes a timing generator  126  for generating a timing reference such as a clock signal, a signal generator  128  for generating address signals A 0  to An, control signals /CS, /RAS, /CAS and /WE, a clock signal CLK and a clock enable signal CKE in response to the output of the timing generator  126 , a test circuit  132  which receives a data signal DQ and a strobe signal DQS from a memory device  124 , and a determination unit  130  for determining a latching result output by the test circuit  132 .  
     [0125] Thus providing the test circuit inside the tester  122  attains the same effects as those obtained by the first and the second embodiment.  
     [0126] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.