Patent Publication Number: US-11023160-B2

Title: Controller and operating method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2018-0080050 filed on Jul. 10, 2018, the disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Various embodiments of the present invention generally relate to a controller, and more particularly, to a controller capable of efficiently processing data, and an operating method thereof. 
     2. Description of the Related Art 
     The computer environment paradigm has shifted towards ubiquitous computing, which enables computing systems to be used anytime and anywhere. As a result, the demand for portable electronic devices, such as mobile phones, digital cameras, and laptop computers have increased rapidly. Those electronic devices generally include a memory system using a memory device as a data storage device. The data storage device may be used as a main memory unit or an auxiliary memory unit of a portable electronic device. 
     Since there is no mechanical driving part, a data storage device using a memory device provides advantages such as excellent stability and durability, high information access speed, and low power consumption. Also, the data storage device can have a higher data access rate and lower power consumption than a hard disk device. Non-limiting examples of the data storage device having such advantages include Universal Serial Bus (USB) memory devices, memory cards of diverse interfaces, Solid-State Drives (SSD) and the like. 
     SUMMARY 
     Various embodiments of the present invention are directed to a memory system capable of efficiently using a cache memory by compressing unmap data. 
     In accordance with an embodiment of the present invention, a controller may include: a memory suitable for storing map data and unmap data; a counter suitable for counting a number of the unmap data stored in the memory; a setter suitable for setting offset values to each of the unmap data when the number of the unmap data is equal to or greater than a predetermined threshold value; and a compressor suitable for compressing the unmap data to have a predetermined compression length based on the offset values. 
     In accordance with an embodiment of the present invention, an operating method of a controller may include: storing map data and unmap data; counting a number of the unmap data; setting offset values to each of the unmap data; and compressing the unmap data to have a predetermined compression length based on the offset values. 
     In accordance with an embodiment of the present invention, an operating method of a controller may include: detecting unmap data in a map table; attaching offset values to each of the unmap data; and compressing the unmap data based on the attached offset values. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout the several views, and wherein: 
         FIG. 1  is a block diagram illustrating a data processing system including a memory system in accordance with an embodiment of the present disclosure; 
         FIG. 2  is a schematic diagram illustrating a configuration of a memory device of the memory system shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram illustrating a configuration of a memory cell array of a memory block in the memory device shown in  FIG. 2 ; 
         FIG. 4  is a schematic diagram illustrating a three-dimensional (3D) structure of the memory device shown in  FIG. 2 ; 
         FIG. 5  is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure; 
         FIGS. 6A to 6C  are diagrams for describing an operation of setting offset values corresponding to the unmap data in accordance with an embodiment of the present disclosure; 
         FIG. 7  is a flowchart for describing an operation of the controller in accordance with an embodiment of the present disclosure; 
         FIGS. 8 to 16  are diagrams schematically illustrating application examples of a data processing system, in accordance with various embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Various examples of the disclosure are described below in more detail with reference to the accompanying drawings. The disclosure may be embodied in different other embodiments, forms and variations thereof and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosure to those skilled in the art to which this invention pertains. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and examples of the disclosure. It is noted that reference to “an embodiment,” “another embodiment” or the like does not necessarily mean only one embodiment, and different references to any such phrases are not necessarily to the same embodiment(s). 
     It will be understood that, although the terms “first”, “second”, “third”, and so on may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element described below could also be termed as a second or third element without departing from the spirit and scope of the present invention. 
     The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former can be directly connected or coupled to the latter, or electrically connected or coupled to the latter via an intervening element therebetween. 
     It will be further understood that when an element is referred to as being “connected to”, or “coupled to” another element, it may be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. 
     As used herein, singular forms are intended to include the plural forms and vice versa, unless the context clearly indicates otherwise. The articles ‘a’ and ‘an’ as used in this application and the appended claims should generally be construed to mean ‘one or more’ unless specified otherwise or clear from context to be directed to a singular form. 
     It will be further understood that the terms “comprises,” “comprising,” “includes,” and “including” when used in this specification, specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs in view of the present disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well-known process structures and/or processes have not been described in detail in order not to unnecessarily obscure the present invention. 
     It is also noted, that in some instances, as would be apparent to those skilled in the relevant art, a feature or element described in connection with one embodiment may be used singly or in combination with other features or elements of another embodiment, unless otherwise specifically indicated. 
       FIG. 1  is a block diagram illustrating a data processing system  100  in accordance with an embodiment of the present invention. 
     Referring to  FIG. 1 , the data processing system  100  may include a host  102  operatively coupled to a memory system  110 . 
     The host  102  may include, for example, a portable electronic device such as a mobile phone, an MP3 player and a laptop computer or an electronic device such as a desktop computer, a game player, a television (TV), a projector and the like. 
     The memory system  110  may operate or perform a specific function or operation in response to a request from the host  102  and, particularly, may store data to be accessed by the host  102 . The memory system  110  may be used as a main memory system or an auxiliary memory system of the host  102 . The memory system  110  may be implemented with any one of various types of storage devices, which may be electrically coupled to the host  102 , according to a protocol of a host interface. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC) and a micro-MMC, a secure digital (SD) card, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and the like. 
     The storage devices for the memory system  110  may be implemented with a volatile memory device such, for example, as a dynamic random access memory (DRAM) and a static RAM (SRAM) and/or a nonvolatile memory device such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (RRAM or ReRAM) and a flash memory. 
     The memory system  110  may include a controller  130  and a memory device  150 . The memory device  150  may store data to be accessed by the host  102 , and the controller  130  may control storage of data in the memory device  150 . 
     The controller  130  and the memory device  150  may be integrated into a single semiconductor device, which may be included in the various types of memory systems as exemplified above. 
     The memory system  110  may be configured as a part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game player, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage configuring a data center, a device capable of transmitting and receiving information under a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, a radio frequency identification (RFID) device, or one of various components configuring a computing system. 
     The memory device  150  may be a nonvolatile memory device and may retain data stored therein even while an electrical power is not supplied. The memory device  150  may store data provided from the host  102  through a write operation, and provide data stored therein to the host  102  through a read operation. The memory device  150  may include a plurality of memory blocks  152  to  156 , each of the memory blocks  152  to  156  may include a plurality of pages. Each of the plurality of pages may include a plurality of memory cells to which a plurality of word lines (WL) are electrically coupled. 
     The controller  130  may control overall operations of the memory device  150 , such as read, write, program and erase operations. For example, the controller  130  may control the memory device  150  in response to a request from the host  102 . The controller  130  may provide the data, read from the memory device  150 , with the host  102 , and/or may store the data, provided by the host  102 , into the memory device  150 . 
     The controller  130  may include a host interface (I/F)  132 , a processor  134 , an error correction code (ECC) component  138 , a power management unit (PMU)  140 , a memory interface (I/F)  142 , and a memory  144  all operatively coupled via an internal bus. 
     The host interface  132  may process commands and data provided from the host  102 , and may communicate with the host  102  through at least one of various interface protocols such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect-express (PCI-e or PCIe), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI) and integrated drive electronics (IDE). 
     The ECC component  138  may detect and correct errors in the data read from the memory device  150  during the read operation. When the number of the error bits is greater than or equal to a threshold number of correctable error bits, the ECC component  138  may not correct error bits but may output an error correction fail signal indicating failure in correcting the error bits. 
     The ECC component  138  may perform an error correction operation based on a coded modulation such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), and so on. The ECC component  138  may include all or some of circuits, modules, systems or devices for performing the error correction operation based on at least one of the above described codes. 
     The PMU  140  may provide and manage power of the controller  130 . 
     The memory interface  142  may serve as an interface for handling commands and data transferred between the controller  130  and the memory device  150 , to allow the controller  130  to control the memory device  150  in response to a request delivered from the host  102 . The memory interface  142  may generate a control signal for the memory device  150  and may process data entered into or outputted from the memory device  150  under the control of the processor  134 , in a case when the memory device  150  is a flash memory and, in particular, when the memory device  150  is a NAND flash memory. 
     The memory  144  may serve as a working memory for the memory system  110  and the controller  130 , and may store temporary or transactional data for operating or driving the memory system  110  and the controller  130 . The controller  130  may control the memory device  150  in response to a request from the host  102 . The controller  130  may deliver data read from the memory device  150  into the host  102 , may store data entered through the host  102  within the memory device  150 . The memory  144  may be used to store data required for the controller  130  and the memory device  150  in order to perform these operations. 
     The memory  144  may be implemented with a volatile memory. The memory  144  may be implemented with a static random access memory (SRAM) or a dynamic random access memory (DRAM). Although  FIG. 1  exemplifies the memory  144  disposed within the controller  130 , the disclosure is not limited thereto. That is, the memory  144  may be located inside or outside the controller  130 . For instance, the memory  144  may be embodied by an external volatile memory having a memory interface transferring data and/or signals transferred between the memory  144  and the controller  130 . 
     The processor  134  may control the overall operations of the memory system  110 . The processor  134  may drive or execute a firmware to control the overall operations of the memory system  110 . The firmware may be referred to as a flash translation layer (FTL). 
     The FTL may perform an operation such as interfacing between the host  102  and the memory device  150 . The host  102  may transmit requests for write and read operations to the memory device  150  through the FTL. 
     The FTL may manage operations of address mapping, garbage collection, wear-leveling and so forth. Particularly, the FTL may store map data. Therefore, the controller  130  may map a logical address, which is provided from the host  102 , to a physical address of the memory device  150  through the map data. The memory device  150  may perform an operation like a general device because of the address mapping operation. Also, through the address mapping operation based on the map data, when the controller  130  updates data of a particular page, the controller  130  may program new data on another empty page and may invalidate old data of the particular page due to a characteristic of a flash memory device. Further, the controller  130  may store map data of the new data into the FTL. 
     The processor  134  may be implemented with a microprocessor or a central processing unit (CPU). The memory system  110  may include one or more processors  134 . 
     A management unit (not shown) may be included in the processor  134 . The management unit may perform bad block management of the memory device  150 . The management unit may find bad memory blocks included in the memory device  150 , which are in unsatisfactory condition for further use, as well as perform bad block management on the bad memory blocks. When the memory device  150  is a flash memory, for example, a NAND flash memory, a program failure may occur during the write operation, for example, during the program operation, due to characteristics of a NAND logic function. During the bad block management, the data of the program-failed memory block or the bad memory block may be programmed into a new memory block. The bad blocks may seriously aggravate the utilization efficiency of the memory device  150  having a 3D stack structure and the reliability of the memory system  100 , and thus reliable bad block management is required. 
       FIG. 2  is a schematic diagram illustrating the memory device  150 . 
     Referring to  FIG. 2 , the memory device  150  may include the plurality of memory blocks BLOCK 0  to BLOCKN−1, and each of the blocks BLOCK 0  to BLOCKN−1 may include a plurality of pages, for example, 2 M  pages, the number of which may vary according to circuit design. The memory device  150  may include a plurality of memory blocks, as single level cell (SLC) memory blocks and multi-level cell (MLC) memory blocks, according to the number of bits which may be stored or expressed in each memory cell. The SLC memory block may include a plurality of pages which are implemented with memory cells each capable of storing 1-bit data. The MLC memory block may include a plurality of pages which are implemented with memory cells each capable of storing multi-bit data, for example, two or more-bit data. An MLC memory block including a plurality of pages which are implemented with memory cells that are each capable of storing 3-bit data may be defined as a triple level cell (TLC) memory block. 
       FIG. 3  is a circuit diagram illustrating a memory block  330  in the memory device  150 . 
     Referring to  FIG. 3 , the memory block  330  may correspond to any of the plurality of memory blocks  152  to  156  included in the memory device  150  of the memory system  110 . 
     Referring to  FIG. 3 , the memory block  330  of the memory device  150  may include a plurality of cell strings  340  which are electrically coupled to bit lines BL 0  to BLm−1, respectively. The cell string  340  of each column may include at least one drain select transistor DST and at least one source select transistor SST. A plurality of memory cells or a plurality of memory cell transistors MC 0  to MCn−1 may be electrically coupled in series between the select transistors DST and SST. The respective memory cells MC 0  to MCn−1 may be configured by single level cells (SLC) each of which may store 1 bit of information, or by multi-level cells (MLC) each of which may store data information of a plurality of bits. However, the present invention is not limited to just the SLC or MLC. The strings  340  may be electrically coupled to the corresponding bit lines BL 0  to BLm−1, respectively. For reference, in  FIG. 3 , ‘DSL’ denotes a drain select line, ‘SSL’ denotes a source select line, and ‘CSL’ denotes a common source line. 
     While  FIG. 3  only shows, as an example, that the memory block  330  is constituted with NAND flash memory cells, it is to be noted that the memory block  330  of the memory device  150  according to the embodiment is not limited to a NAND flash memory. The memory block  330  may be realized by a NOR flash memory, a hybrid flash memory in which at least two kinds of memory cells are combined, or one-NAND flash memory in which a controller is built in a memory chip. The operational characteristics of a semiconductor device may be applied to not only a flash memory device in which a charge storing layer is configured by conductive floating gates but also a charge trap flash (CTF) in which a charge storing layer is configured by a dielectric layer. 
     A power supply circuit  310  of the memory device  150  may provide word line voltages, for example, a program voltage, a read voltage and a pass voltage, to be supplied to respective word lines according to an operation mode and voltages to be supplied to bulks, for example, well regions in which the memory cells are formed. The power supply circuit  310  may perform a voltage generating operation under the control of a control circuit (not shown). The power supply circuit  310  may generate a plurality of variable read voltages to generate a plurality of read data, select one of the memory blocks or sectors of a memory cell array under the control of the control circuit, select one of the word lines of the selected memory block, and provide the word line voltages to the selected word line and unselected word lines. 
     A read and write (read/write) circuit  320  of the memory device  150  may be controlled by the control circuit, and may serve as a sense amplifier or a write driver according to an operation mode. During a verification operation or a normal read operation, the read/write circuit  320  may operate as a sense amplifier for reading data from the memory cell array. During a program operation, the read/write circuit  320  may operate as a write driver for driving bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuit  320  may receive from a buffer (not illustrated) data to be stored into the memory cell array, and drive bit lines according to the received data. The read/write circuit  320  may include a plurality of page buffers  322  to  326  respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs), and each of the page buffers  322  to  326  may include a plurality of latches (not illustrated). 
       FIG. 4  is a schematic diagram illustrating a 3D structure of the memory device  150 . 
     Although  FIG. 4  shows a 3D structure, the memory device  150  may be embodied by a two-dimensional (2D) or three-dimensional (3D) memory device. Specifically, as illustrated in  FIG. 4 , the memory device  150  may be embodied in a nonvolatile memory device having a 3D stack structure. When the memory device  150  has a 3D structure, the memory device  150  may include a plurality of memory blocks BLK 0  to BLKN−1 each having a 3D structure (or a vertical structure). 
     As described with reference to  FIG. 1 , the memory  144  may include a map cache. The map cache may store map data therein. The map data may represent relationship between logical block address (LBA) and physical block address (PBA). The logical block address may be provided along with data from the host  102  and may correspond to the data. The physical block address may indicate storage location of the data within the memory device  150 . For example, the controller  130  may receive a logical block address corresponding to write data from the host  102  and may assign physical block address for storing the write data into the memory device  150  through the FTL. The memory  144  may store map data representing the relationship between the logical block address and the physical block address corresponding to the write data into the map cache. The memory  144  may further include a map table in which the map data is an entry. In the map table, the map data may be recorded by a unit of a map segment. For example, when a size of a single map segment is 1024 KB and a size of a single map data is 1 KB, 1024 number of map data may be recorded within a single map table. The memory  144  may store a plurality of map tables. However, this is merely an example which will not limit the scope of the present invention. The structure of the map table will be described with reference to  FIGS. 6A to 6C . 
     The controller  130  may read, based on the map data recorded in the map table, data in response to a read request provided from the host  102 . Particularly, in response to a read request provided from the host  102 , the controller  130  may detect a logical address corresponding to the read request in the map table, may detect a physical address that indicates substantial storage location of a target data based on the map data including the detected logical address, and may read the target data stored in the storage location indicated by the detected physical address. The controller  130  may improve the performance of the read operation through the map table. However, the map cache for storing the map data configuring the map table has a limited capacity, and therefore the capacity of the map cache needs to be used efficiently. 
     In accordance with an embodiment of the present disclosure, an operating method of the controller  130  for efficiently using the map cache is provided. 
       FIG. 5  is a diagram illustrating a memory system  110  in accordance with an embodiment of the present disclosure. 
       FIG. 5  merely illustrates, differently from the memory system  110  illustrated in  FIG. 1 , elements relevant to an embodiment of the present disclosure. Thus, the memory system  110  of the present disclosure is not limited to the elements shown in the embodiment of  FIG. 5 . As described with reference to  FIGS. 1 to 4 , the memory system  110  may include the controller  130  and the memory device  150 . The controller  130  may control the memory device  150 . The controller  130  may include the processor  134 , the memory interface  142  and the memory  144 . 
     In addition, the controller  130  may include a counter  510 , a setter  530  and a compressor  550 . 
     The memory  144  may store map data into a map cache. The memory  144  may store unmap data which is a kind of map data unmapped in response to an unmap command provided from the host  102 , into the map cache. As described above, the map data may represent the relationship between the logical addresses and the physical addresses. However, the unmap data can no longer represent the relationship between the logical addresses and the physical addresses. Thus, the unmap data is data that may not be needed on memory  144 , and may be deleted at a later time. 
     The memory  144  may store a map table  570  in which the map data and the unmap data are recorded. The map table  570  may include a flag field and an address field. In the flag field, a flag may be recorded to discriminate the map data from the unmap data. In the address field, the logical addresses and the physical addresses (e.g., a block number and a page number) may be recorded. The value of the address field may represent mapping relationship between the logical addresses and the physical addresses (“L2P”). Both of the map data and the unmap data may be recorded into the map table  570 . In the memory  144 , map/unmap bit may be used to discriminate the map data from the unmap data. For example, when the map/unmap bit has a value of ‘0’ to indicate the unmap data, a value of the most significant bit (MSB) may be set as ‘0’ to indicate the unmap data and may be stored into the memory  144 . The unmap data having the most significant bit of a value ‘0’ may correspond to a value of ‘U’ in the flag field of the map table  570 . In contrast, when the map/unmap bit has a value of ‘1’ to indicate the map data, a value of the most significant bit may be set as ‘1’ to indicate the map data and may be stored into the memory  144 . The map data having the most significant bit of a value ‘1’ may correspond to a value of ‘M’ in the flag field of the map table  570 . However, this is merely an example which will not limit the scope of the present invention. 
     The processor  134  may control the memory device  150  to store therein the map data, which is recoded in the map table  570  stored in the map cache of the memory  144 , through the memory interface  142  in response to the flush command provided from the host  102 . 
     In accordance with an embodiment of the present invention, the counter  510  may count a number of the unmap data recorded in the whole map table  570  stored in the memory  144 . In accordance with an embodiment of the present invention, the counter  510  may count, by a unit of a map segment, a number of the unmap data recorded in the map table  570 . The counter  510  may compare the counted number of the unmap data with a predetermined threshold value. The counter  510  may provide the result of the comparison to the setter  530 . 
     The setter  530  may set offset values to each of the unmap data when the number of the unmap data is equal to or greater than the predetermined threshold value. 
     In accordance with an embodiment of the present invention, the setter  530  may set (or attach) offset values to the logical addresses corresponding to the unmap data. The setter  530  may arrange, based on the map table  570 , the unmap data such that the offset values for the unmap data increase as the offset values increase (i.e., as the logical addresses increase). 
     In accordance with an embodiment of the present invention, the setter  530  may set (or attach) offset values to physical addresses within a read map segment or a write map segment. It is assumed that 1024 number of map data is included in the write map segment and 512 number of map data is included in the read map segment when a size of the read map segment is 512 KB, a size of the write map segment is 1024 KB and a size of a single map data is 1 KB. However, this is merely an example which will not limit the scope of the present invention. As described above, the counter  510  may count the number of the unmap data included in each map segment. When the number of the unmap data included in a single map segment is equal to or greater than the predetermined threshold value, the setter  530  may arrange the unmap data such that the offset values for the unmap data increase as the physical addresses increase. For example, when there are a first unmap data corresponding to a memory block ‘100’ and a page ‘5’ and a second unmap data corresponding to a memory block ‘100’ and a page ‘1’, the setter  530  may arrange the first unmap data and the second unmap data into an order of the second unmap data and the first unmap data. For example, when there are a third unmap data corresponding to a memory block ‘50’ and a page ‘5’ and a fourth unmap data corresponding to a memory block ‘70’ and a page ‘5’, the setter  530  may arrange the third unmap data and the fourth unmap data into an order of the third unmap data and the fourth unmap data. 
     In accordance with an embodiment of the present disclosure, the setter  530  may set offset values by performing a modulo operation on the logical addresses such that the unmap data is compressed to have a predetermined compression length. For example, when the compressor  550  compresses the unmap data to have a compression length of ‘100’, the setter  530  sets the offset values from ‘1’ to ‘100’ as the logical addresses increase. That is, when there are unmap data respectively corresponding to logical addresses LBA 1  to LBA 100 , the setter  530  may set the offset values of ‘1’ to ‘100’ respectively for the unmap data corresponding to the logical addresses LBA 1  to LBA 100 . Further, when there are unmap data respectively corresponding to logical addresses LBA 101  to LBA 200 , the setter  530  may set the offset values of ‘1’ to ‘100’ respectively for the unmap data corresponding to the logical addresses LBA 101  to LBA 200 . 
     The setter  530  may provide the set offset values to the compressor  550 . 
     The compressor  550  may compress the unmap data to have a predetermined compression length based on the provided offset values. For example, when the predetermined compression length is ‘50’, the compressor  550  may compress, based on the offset values from ‘1’ to ‘100’, the unmap data corresponding to the offset values from ‘1’ to ‘50’ and the unmap data corresponding to the offset values from ‘51’ to ‘100’ to generate two pieces of compressed unmap data. The compressed unmap data may include a start logical address or a start physical address, a start offset value corresponding to a start logical address or a start physical address and a number of pieces of the unmap data. For example, when ‘100’ pieces of the unmap data having the offset values from ‘5’ to ‘104’ are compressed into the compressed unmap data, that compressed unmap data may include a value of ‘5’ as the start offset value corresponding to a start logical address or a start physical address and a value of ‘100’ as the number of pieces of the unmap data. 
     The compressor  550  may provide the compressed unmap data to the memory  144 . The memory  144  may store the compressed unmap data into the map cache. 
     As describe above, in accordance with an embodiment of the present disclosure, the controller  130  may compress the unmap data, and thus the map cache may be effectively utilized within the memory  144  having the limited capacity. 
       FIGS. 6A to 6C  are diagrams for describing an operation of setting the offset values corresponding to the unmap data in accordance with an embodiment of the present disclosure. 
       FIGS. 6A to 6C  illustrate a first map table  610  and a second map table  650 . For clarity of description, the first map table  610  and the second map table  650  are separately illustrated but the first map table  610  and the second map table  650  are substantially the same map table. In the embodiment shown in  FIGS. 6A to 6C , it is assumed that 6 pieces of map data are recorded in the first map table  610  and 6 pieces of unmap data are recorded in the second map table  650 . It is also assumed that a unmap command for all map data recorded in the first map table  610  is provided, thus all map data of the first map table  610  become the unmap data and the unmap data are recorded into the second map table  650 . 
     Each of the first map table  610  and the second map table  650  may have fields of a flag (“Flag”), a logical address (“LBA”), a memory block number (“Block”) and a page number (“Page”) to record the map data and the unmap data. As illustrated in  FIGS. 6A to 6C , all data recorded in the first map table  610  are map data since all the flag field corresponding to the data are recorded as a value of ‘M’. In contrast, all data recorded in the second map table  650  are unmap data since all the flag field corresponding to the data are recorded as a value of ‘U’. 
     As illustrated in  FIGS. 6A to 6C , the setter  530  may set the offset values (“offset”) corresponding to the unmap data recorded in the second map table  650 . 
     Referring to  FIG. 6A , the setter  530  may set offset values to the logical addresses (LBA) corresponding to the unmap data. 
     For example, the setter  530  may set an offset value of ‘1’ for the unmap data corresponding to the logical address (LBA) ‘1’; The setter  530  may set an offset value of ‘2’ for the unmap data corresponding to the logical address ‘2’; and the setter  530  may set an offset value of ‘3’ for the unmap data corresponding to the logical address ‘3’. In similar manner, the setter  530  may set offset values for the unmap data such that the offset values for the unmap data increase as the logical addresses corresponding to the unmap data increase. 
     Referring to  FIG. 6B , the setter  530  may set offset values to the physical addresses within the read map segment or the write map segment. It is assumed that plural pieces of map data recorded in the first map table  610  configure a single write map segment. 
     For example, as illustrated in  FIG. 6B , the setter  530  may set the offset values from a smallest memory block number among the plural pieces of unmap data recorded in the second map table  650 . For example, the setter  530  may set an offset value of ‘1’ for the unmap data having the smallest memory block number of ‘10’ among the plural pieces of unmap data recorded in the second map table  650 ; the setter  530  may set an offset value of ‘2’ for the unmap data having the second smallest memory block number of ‘20’ among the plural pieces of unmap data recorded in the second map table  650 ; and the setter  530  may set an offset value of ‘3’ for the unmap data having a memory block number of ‘40’ (i.e., third smallest memory block) among the plural pieces of unmap data recorded in the second map table  650 . When there are plural pieces of the unmap data corresponding to the same memory block number among the plural pieces of unmap data recorded in the second map table  650 , the setter  530  may set offset values for the plural pieces of the unmap data corresponding to the same memory block number based on the page number. For example, the setter  530  may set an offset value of ‘4’ for the unmap data having the smallest page number of ‘1’ among the plural pieces of unmap data corresponding to the same memory block number of ‘100’ in the second map table  650 ; the setter  530  may set an offset value of ‘5’ for the unmap data having the second smallest page number of ‘2’ among the plural pieces of unmap data corresponding to the same memory block number of ‘100’ in the second map table  650 ; and the setter  530  may set an offset value of ‘6’ for the unmap data having a page number of ‘5’ among the plural pieces of unmap data corresponding to the same memory block number of ‘100’ in the second map table  650 . However, this is merely an example which will not limit the scope of the present invention. 
     Referring to  FIG. 6C , the setter  530  may set offset values by performing a modulo operation on the logical addresses (LBA) such that the unmap data is compressed to have a predetermined compression length. It is assumed that the predetermined compression length is ‘3’. That is, it is assumed that 3 pieces of the unmap data are compressed into the compressed unmap data. 
     As illustrated in  FIG. 6C , the setter  530  may set offset values for the unmap data basically according to the logical addresses (LBA) corresponding to the unmap data. However, the maximum of the offset value may be limited to a value of ‘3’ because the predetermined compression length is ‘3’. Therefore, as described with reference to  FIG. 3 , the setter  530  may set the offset values from ‘1’ to ‘3’ for the unmap data corresponding to the logical addresses (LBA) from ‘1’ to ‘3’. Then, the setter  530  may set the offset values not from ‘4’ to ‘6’ but from ‘1’ to ‘3’ for the unmap data corresponding to the logical addresses from ‘4’ to ‘6’. When the offset values are set as described with reference to  FIG. 6A , a single piece of compressed unmap data may be generated. However, when the offset values are set as described with reference to  FIG. 6C , 2 pieces of compressed unmap data may be generated. However, this is merely an example which will not limit the scope of present invention. 
       FIG. 7  is a flowchart for describing an operation of the controller  130  in accordance with an embodiment of the present disclosure. Described with reference to  FIGS. 6A to 7  will be the operation of the controller  130 . 
     It is assumed that an unmap command is provided from the host  102  to the controller  130  for all map data recorded in the first map table  610 . 
     At step S 701 , the memory  144  may update the first map table  610  into the second map table  650  in response to the unmap command provided from the host  102 . 
     At step S 703 , the counter  510  may count a number of pieces of the unmap data recorded in the second map table  650 . 
     At step S 705 , the counter  510  may compare the counted number of pieces of the unmap data with the predetermined threshold value. The counter  510  may provide the setter  530  with the result of the comparison. 
     When the counted number of pieces of the unmap data is less than the predetermined threshold value (° No′ at step S 705 ), the process may be repeated from step S 701 . 
     When the counted number of pieces of the unmap data is equal to or greater than the predetermined threshold value (‘Yes’ at step S 705 ), the setter  530  may set the offset values respectively for the unmap data at step S 707 . For example, the setter  530  may set the logical addresses corresponding to the unmap data as the offset values for the unmap data, as described with reference to  FIGS. 6A to 6C . The setter  530  may provide the offset values to the compressor  550 . 
     At step S 709 , the compressor  550  may compress the unmap data to have the predetermined compression length based on the offset values. The compressor  550  may provide the compressed unmap data to the memory  144 . 
     At step S 711 , the memory  144  may store the compressed unmap data into the map cache. 
     In other words, the operation of the controller  130  in accordance with an embodiment of the present disclosure may include detecting unmap data in a map table (e.g., S 703  and S 705 ); attaching offset values to each of the unmap data (e.g., S 707 ); and compressing the unmap data based on the attached offset values (e.g., S 709 ). 
     Hereinafter, a data processing system and electronic devices which may be implemented with the memory system  110  including the memory device  150  and the controller  130 , which have been described with reference to  FIGS. 1 to 7 , will be described in detail with reference to  FIGS. 8 to 16 . 
       FIGS. 8 to 16  are diagrams schematically illustrating application examples of the data processing system of  FIGS. 1 to 7  according to various embodiments. 
       FIG. 8  is a diagram schematically illustrating an example of the data processing system including the memory system in accordance with an embodiment.  FIG. 8  schematically illustrates a memory card system  6100  including the memory system in accordance with an embodiment. 
     Referring to  FIG. 8 , the memory card system  6100  may include a memory controller  6120 , a memory device  6130  and a connector  6110 . 
     More specifically, the memory controller  6120  may be connected to the memory device  6130 , and may be configured to access the memory device  6130 . The memory device  6130  may be embodied by a nonvolatile memory (NVM). By the way of example but not limitation, the memory controller  6120  may be configured to control read, write, erase and background operations onto the memory device  6130 . The memory controller  6120  may be configured to provide an interface between the memory device  6130  and a host (not shown) and/or a drive firmware for controlling the memory device  6130 . That is, the memory controller  6120  may correspond to the controller  130  in the memory system  110  described with reference to  FIGS. 1 to 7 , while the memory device  6130  may correspond to the memory device  150  described with reference to  FIGS. 1 to 7 . 
     Thus, as shown in  FIG. 1 , the memory controller  6120  may include a random access memory (RAM), a processor, a host interface, a memory interface and an error correction code component. The memory controller  130  may further include the elements described in  FIG. 1 . 
     The memory controller  6120  may communicate with an external device, for example, the host  102  of  FIG. 1  through the connector  6110 . For example, as described with reference to  FIG. 1 , the memory controller  6120  may be configured to communicate with an external device through one or more of various communication protocols such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI express (PCIe), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (EDSI), Integrated Drive Electronics (IDE), Firewire, universal flash storage (UFS), wireless fidelity (Wi-Fi or WiFi) and Bluetooth. Thus, the memory system and the data processing system in accordance with an embodiment may be applied to wired and/or wireless electronic devices or particularly mobile electronic devices. 
     The memory device  6130  may be implemented by a nonvolatile memory. For example, the memory device  6130  may be implemented by various nonvolatile memory devices such as an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfer magnetic RAM (SU-RAM). The memory device  6130  may include a plurality of dies as in the memory device  150  of  FIG. 1 . 
     The memory controller  6120  and the memory device  6130  may be integrated into a single semiconductor device. For example, the memory controller  6120  and the memory device  6130  may construct a solid state driver (SSD) by being integrated into a single semiconductor device. Also, the memory controller  6120  and the memory device  6130  may construct a memory card such as a PC card (e.g., Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro and eMMC), a secured digital (SD) card (e.g., SD, miniSD, microSD and SDHC) and a universal flash storage (UFS). 
       FIG. 9  is a diagram schematically illustrating another example of a data processing system  6200  including a memory system, in accordance with an embodiment. 
     Referring to  FIG. 9 , the data processing system  6200  may include a memory device  6230  having one or more nonvolatile memories (NVMs) and a memory controller  6220  for controlling the memory device  6230 . The data processing system  6200  may serve as a storage medium such as a memory card (CF, SD, micro-SD or the like) or USB device, as described with reference to  FIG. 1 . The memory device  6230  may correspond to the memory device  150  in the memory system  110  described in  FIGS. 1 to 7 , and the memory controller  6220  may correspond to the controller  130  in the memory system  110  described in  FIGS. 1 to 7 . 
     The memory controller  6220  may control a read, write, or erase operation on the memory device  6230  in response to a request of the host  6210 , and the memory controller  6220  may include one or more central processing units (CPUs)  6221 , a buffer memory such as a random access memory (RAM)  6222 , an error correction code (ECC) circuit  6223 , a host interface  6224  and a memory interface such as an NVM interface  6225 . 
     The CPU  6221  may control the operations on the memory device  6230 , for example, read, write, file system management and bad page management operations. The RAM  6222  may be operated according to control of the CPU  6221 , and used as a work memory, buffer memory or cache memory. When the RAM  6222  is used as a work memory, data processed by the CPU  6221  may be temporarily stored in the RAM  6222 . When the RAM  6222  is used as a buffer memory, the RAM  6222  may be used for buffering data transmitted to the memory device  6230  from the host  6210  or transmitted to the host  6210  from the memory device  6230 . When the RAM  6222  is used as a cache memory, the RAM  6222  may assist the memory device  6230  to operate at high speed. 
     The ECC circuit  6223  may correspond to the ECC component  138  of the controller  130  illustrated in  FIG. 1 . As described with reference to  FIG. 1 , the ECC circuit  6223  may generate an error correction code (ECC) for correcting a fail bit or error bit of data provided from the memory device  6230 . The ECC circuit  6223  may perform error correction encoding on data provided to the memory device  6230 , thereby forming data with a parity bit. The parity bit may be stored in the memory device  6230 . The ECC circuit  6223  may perform error correction decoding on data outputted from the memory device  6230 . in this case, the ECC circuit  6223  may correct an error using the parity bit. For example, as described with reference to  FIG. 1 , the ECC circuit  6223  may correct an error using Low Density Parity Check (LDPC) code, Bose-Chaudhri-Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolution code, Recursive Systematic Code (RSC) or coded modulation such as Trellis-Coded Modulation (TCM) or Block coded modulation (BCM). 
     The memory controller  6220  may transmit to, and/or receive from, the host  6210  data or signals through the host interface  6224 , and may transmit to, and/or receive from, the memory device  6230  data or signals through the NVM interface  6225 . The host interface  6224  may be connected to the host  6210  through a parallel advanced technology attachment (DATA) bus, a serial advanced technology attachment (SATA) bus, a small computer system interface (SCSI), a universal serial bus (USB), a peripheral component interconnect-express (PCIe), or a NAND interface. The memory controller  6220  may have a wireless communication function with a mobile communication protocol such as wireless fidelity (WiFi) or Long Term Evolution (LTE). The memory controller  6220  may be connected to an external device, e.g., the host  6210 , or another external device, and then transmit and/or receive data to and/or from the external device. As the memory controller  6220  is configured to communicate with the external device through one or more of various communication protocols, the memory system and the data processing system in accordance with an embodiment may be applied to wired and/or wireless electronic devices or particularly a mobile electronic device. 
       FIG. 10  is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.  FIG. 10  schematically illustrates a solid state drive (SSD) to which the memory system in accordance with an embodiment is applied. 
     Referring to  FIG. 10 , the SSD  6300  may include a controller  6320  and a memory device  6340  including a plurality of nonvolatile memories (NVMs). The controller  6320  may correspond to the controller  130  in the memory system  110  of  FIG. 1 , and the memory device  6340  may correspond to the memory device  150  in the memory system of  FIG. 1 . 
     More specifically, the controller  6320  may be connected to the memory device  6340  through a plurality of channels CH 1  to CHi. The controller  6320  may include one or more processors  6321 , an error correction code (ECC) circuit  6322 , a host interface  6324 , a buffer memory  6325  and a memory interface, for example, a nonvolatile memory interface  6326 . 
     The buffer memory  6325  may temporarily store data provided from the host  6310  or data provided from a plurality of flash memories NVM included in the memory device  6340 , or temporarily store meta data of the plurality of flash memories NVM, for example, map data including a mapping table. The buffer memory  6325  may be embodied by volatile memories such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, a low power DDR (LPDDR) SDRAM and a graphics RAM (GRAM) or nonvolatile memories such as a ferroelectric RAM (FRAM), a resistive RAM (RRAM or ReRAM), a spin-transfer torque magnetic RAM (STT-MRAM) and a phase-change RAM (PRAM). For the purpose of description,  FIG. 10  illustrates that the buffer memory  6325  exists in the controller  6320 , but the buffer memory  6325  may be located or arranged outside the controller  6320 . 
     The ECC circuit  6322  may calculate an error correction code (ECC) value of data to be programmed to the memory device  6340  during a program operation, perform an error correction operation on data read from the memory device  6340  based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device  6340  during a failed data recovery operation. 
     The host interface  6324  may provide an interface function with an external device, for example, the host  6310 , and the nonvolatile memory interface  6326  may provide an interface function with the memory device  6340  connected through the plurality of channels. 
     Furthermore, a plurality of SSDs  6300  to which the memory system  110  of  FIG. 1  is applied may be provided to embody a data processing system, for example, a redundant array of independent disks (RAID) system. The RAID system may include the plurality of SSDs  6300  and a RAID controller for controlling the plurality of SSDs  6300 . When the RAID controller performs a program operation in response to a write command provided from the host  6310 , the RAID controller may select one or more memory systems or SSDs  6300  according to a plurality of RAID levels, i.e., RAID level information of the write command provided from the host  6310  in the SSDs  6300 , and may output data corresponding to the write command to the selected SSDs  6300 . Furthermore, when the RAID controller performs a read operation in response to a read command provided from the host  6310 , the RAID controller may select one or more memory systems or SSDs  6300  according to a plurality of RAID levels, that is, RAID level information of the read command provided from the host  6310  in the SSDs  6300 , and provide data read from the selected SSDs  6300  to the host  6310 . 
       FIG. 11  is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.  FIG. 11  schematically illustrates an embedded Multi-Media Card (eMMC)  6400  to which the memory system in accordance with an embodiment is applied. 
     Referring to  FIG. 11 , the eMMC  6400  may include a controller  6430  and a memory device  6440  embodied by one or more NAND flash memories. The controller  6430  may correspond to the controller  130  in the memory system  110  of  FIG. 1 , and the memory device  6440  may correspond to the memory device  150  in the memory system  110  of  FIG. 1 . 
     More specifically, the controller  6430  may be connected to the memory device  6440  through a plurality of channels. The controller  6430  may include one or more cores  6432 , a host interface (I/F)  6431  and a memory interface, for example, a NAND interface (I/F)  6433 . 
     The core  6432  may control the operations of the eMMC  6400 , the host interface  6431  may provide an interface function between the controller  6430  and the host  6410 . The NAND interface  6433  may provide an interface function between the memory device  6440  and the controller  6430 . For example, the host interface  6431  may serve as a parallel interface, for example, MMC interface as described with reference to  FIG. 1 . Furthermore, the host interface  6431  may serve as a serial interface, for example, Ultra High Speed (UHS)-I and UHS-II interface. 
       FIGS. 12 to 15  are diagrams schematically illustrating other examples of the data processing system including the memory system in accordance with an embodiment.  FIGS. 12 to 15  schematically illustrate universal flash storage (UFS) systems to which the memory system in accordance with an embodiment is applied. 
     Referring to  FIGS. 12 to 15 , the UFS systems  6500 ,  6600 ,  6700  and  6800  may include hosts  6510 ,  6610 ,  6710 ,  6810 , UFS devices  6520 ,  6620 ,  6720 ,  6820  and UFS cards  6530 ,  6630 ,  6730 ,  6830 , respectively. The hosts  6510 ,  6610 ,  6710 ,  6810  may serve as application processors of wired and/or wireless electronic devices or particularly mobile electronic devices, the UFS devices  6520 ,  6620 ,  6720 ,  6820  may serve as embedded UFS devices. The UFS cards  6530 ,  6630 ,  6730 ,  6830  may serve as external embedded UFS devices or removable UFS cards. 
     The hosts  6510 ,  6610 ,  6710 ,  6810 , the UFS devices  6520 ,  6620 ,  6720 ,  6820  and the UFS cards  6530 ,  6630 ,  6730 ,  6830  in the respective UFS systems  6500 ,  6600 ,  6700  and  6800  may communicate with external devices, e.g., wired and/or wireless electronic devices or particularly mobile electronic devices through UFS protocols. The UFS devices  6520 ,  6620 ,  6720 ,  6820  and the UFS cards  6530 ,  6630 ,  6730 ,  6830  may be embodied by the memory system  110  illustrated in  FIG. 1 . For example, in the UFS systems  6500 ,  6600 ,  6700 ,  6800 , the UFS devices  6520 ,  6620 ,  6720 ,  6820  may be embodied in the form of the data processing system  6200 , the SSD  6300  or the eMMC  6400  described with reference to  FIGS. 9 to 11 , and the UFS cards  6530 ,  6630 ,  6730 ,  6830  may be embodied in the form of the memory card system  6100  described with reference to  FIG. 8 . 
     Furthermore, in the UFS systems  6500 ,  6600 ,  6700  and  6800 , the hosts  6510 ,  6610 ,  6710 ,  6810 , the UFS devices  6520 ,  6620 ,  6720 ,  6820  and the UFS cards  6530 ,  6630 ,  6730 ,  6830  may communicate with each other through an UFS interface, for example, MIPI M-PHY and MIPI UniPro (Unified Protocol) in MIPI (Mobile Industry Processor Interface). Furthermore, the UFS devices  6520 ,  6620 ,  6720 ,  6820  and the UFS cards  6530 ,  6630 ,  6730 ,  6830  may communicate with each other through various protocols other than the UFS protocol, e.g., universal storage bus (USB) Flash Drives (UFDs), multi-media card (MMC), secure digital (SD), mini-SD, and micro-SD. 
     In the UFS system  6500  illustrated in  FIG. 12 , each of the host  6510 , the UFS device  6520  and the UFS card  6530  may include UniPro. The host  6510  may perform a switching operation to communicate with at least one of the UFS device  6520  and the UFS card  6530 . The host  6510  may communicate with the UFS device  6520  or the UFS card  6530  through link layer switching, e.g., L3 switching at the UniPro. In this case, the UFS device  6520  and the UFS card  6530  may communicate with each other through a link layer switching at the UniPro of the host  6510 . In an example, the configuration in which one UFS device  6520  and one UFS card  6530  are connected to the host  6510  has been exemplified for convenience of description. However, a plurality of UFS devices and UFS cards may be connected in parallel or in the form of a star to the host  6510 , and a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device  6520  or connected in series or in the form of a chain to the UFS device  6520 . Herein, the form of a star means an arrangement that a single device is coupled with plural other devices or cards for centralized control. 
     In the UFS system  6600  illustrated in  FIG. 13 , each of the host  6610 , the UFS device  6620  and the UFS card  6630  may include UniPro, and the host  6610  may communicate with the UFS device  6620  or the UFS card  6630  through a switching module  6640  performing a switching operation, for example, through the switching module  6640  which performs link layer switching at the UniPro, for example, L3 switching. The UFS device  6620  and the UFS card  6630  may communicate with each other through link layer switching of the switching module  6640  at UniPro. In an example, the configuration in which one UFS device  6620  and one UFS card  6630  are connected to the switching module  6640  has been exemplified for convenience of description. However, a plurality of UFS devices and UFS cards may be connected in parallel or in the form of a star to the switching module  6640 , and a plurality of UFS cards may be connected in series or in the form of a chain to the UFS device  6620 . 
     In the UFS system  6700  illustrated in  FIG. 14 , each of the host  6710 , the UFS device  6720  and the UFS card  6730  may include UniPro. The host  6710  may communicate with the UFS device  6720  or the UFS card  6730  through a switching module  6740  performing a switching operation, for example, the switching module  6740  which performs link layer switching at the UniPro, for example, L3 switching. In this case, the UFS device  6720  and the UFS card  6730  may communicate with each other through link layer switching of the switching module  6740  at the UniPro, and the switching module  6740  may be integrated as one module with the UFS device  6720  inside or outside the UFS device  6720 . In an example, the configuration in which one UFS device  6720  and one UFS card  6730  are connected to the switching module  6740  has been exemplified for convenience of description. However, a plurality of modules each including the switching module  6740  and the UFS device  6720  may be connected in parallel or in the form of a star to the host  6710  or connected in series or in the form of a chain to each other. Furthermore, a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device  6720 . 
     In the UFS system  6800  illustrated in  FIG. 15 , each of the host  6810 , the UFS device  6820  and the UFS card  6830  may include M-PHY and UniPro. The UFS device  6820  may perform a switching operation to communicate with the host  6810  and the UFS card  6830 . The UFS device  6820  may communicate with the host  6810  or the UFS card  6830  through a switching operation between the M-PHY and UniPro module for communication with the host  6810  and the M-PHY and UniPro module for communication with the UFS card  6830 , for example, through a target Identifier (ID) switching operation. Here, the host  6810  and the UFS card  6830  may communicate with each other through target ID switching between the M-PHY and UniPro modules of the UFS device  6820 . In an embodiment, the configuration in which one UFS device  6820  is connected to the host  6810  and one UFS card  6830  is connected to the UFS device  6820  has been exemplified for convenience of description. However, a plurality of UFS devices may be connected in parallel or in the form of a star to the host  6810 , or connected in series or in the form of a chain to the host  6810 , and a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device  6820 , or connected in series or in the form of a chain to the UFS device  6820 . 
       FIG. 16  is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.  FIG. 16  is a diagram schematically illustrating a user system  6900  to which the memory system in accordance with an embodiment is applied. 
     Referring to  FIG. 16 , the user system  6900  may include a user interface  6910 , a memory module  6920 , an application processor  6930 , a network module  6940 , and a storage module  6950 . 
     More specifically, the application processor  6930  may drive components included in the user system  6900 , for example, an operating system (OS), and include controllers, interfaces and a graphic engine which control the components included in the user system  6900 . The application processor  6930  may be provided as a System-on-Chip (SoC). 
     The memory module  6920  may be used as a main memory, work memory, buffer memory or cache memory of the user system  6900 . The memory module  6920  may include a volatile random access memory (RAM) such as a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM or LPDDR3 SDRAM or a nonvolatile RAM such as a phase-change RAM (PRAM), a resistive RAM (ReRAM), a magneto-resistive RAM (MRAM) or a ferroelectric RAM (FRAM). For example, the application processor  6930  and the memory module  6920  may be packaged and mounted, based on Package on Package (PoP). 
     The network module  6940  may communicate with external devices. For example, the network module  6940  may not only support wired communication, but may also support various wireless communication protocols such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (Wimax), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, wireless display (WI-DI), thereby communicating with wired/wireless electronic devices or particularly mobile electronic devices. Therefore, the memory system and the data processing system, in accordance with an embodiment of the present invention, can be applied to wired/wireless electronic devices. The network module  6940  may be included in the application processor  6930 . 
     The storage module  6950  may store data, for example, data received from the application processor  6930 , and then may transmit the stored data to the application processor  6930 . The storage module  6950  may be embodied by a nonvolatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash, NOR flash and 3D NAND flash, and provided as a removable storage medium such as a memory card or external drive of the user system  6900 . The storage module  6950  may correspond to the memory system  110  described with reference to  FIG. 1 . Furthermore, the storage module  6950  may be embodied as an SSD, eMMC and UFS as described above with reference to  FIGS. 10 to 15 . 
     The user interface  6910  may include interfaces for inputting data or commands to the application processor  6930  or outputting data to an external device. For example, the user interface  6910  may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor and a piezoelectric element, and user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker and a motor. 
     Furthermore, when the memory system  110  of  FIG. 1  is applied to a mobile electronic device of the user system  6900 , the application processor  6930  may control the operations of the mobile electronic device, and the network module  6940  may serve as a communication module for controlling wired and/or wireless communication with an external device. The user interface  6910  may display data processed by the processor  6930  on a display and touch module of the mobile electronic device, or support a function of receiving data from the touch panel. 
     While the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as determined in the following claims.