Patent Publication Number: US-2011063270-A1

Title: Source driver of display device, and method of controlling the same

Description:
INCORPORATION BY REFERENCE 
     This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-210478, filed on Sep. 11, 2009, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to a source driver of a display device and a method of controlling the same. 
     2. Description of Related Art 
     Recently, plane display devices such as a liquid crystal display have been increased in size. A large-scale plane display device drives signal lines by using an IC (Integrated Circuit) that is called a source driver. The number of signal lines that can be driven by each source driver has the limit. The plane display device that is enlarged and is highly miniaturized has plural source drivers that have a cascade connection configuration as shown in  FIG. 6 . The plane display device sequentially operates plural source drivers, and drives all signal lines for one horizontal line. 
     As shown in  FIG. 6 , a plane display device  1  of a related art includes a controller  10 , source drivers IC 1  to IC 4 , and a display  12 . The controller  10  transmits a clock signal CLK, a loading signal LOAD, and data signals DD 0  to DD 5  to each of source drivers. The clock signal CLK is a signal to generate the operation clock of source drivers IC 1  to IC 4 . Data signals DD 0  to DD 5  are pixel data. Each of source drivers IC 1  to IC 4  outputs a pixel drive signal corresponding to data signals DD 0  to DD 5  to the display  12 . The loading signal LOAD is a strobe signal to sequentially take data signals DD 0  to DD 5  into each of source drivers IC 1  to IC 4 . This loading signal LOAD is output to source drivers IC 1  to IC 4  from the controller  10  for every horizontal period. In the example of  FIG. 6 , the number of source drivers is limited to four for the simplification of the drawing. However, a further number of source drivers may be used. 
     Each of source drivers receives the clock signal CLK, the loading signal LOAD, and data signals DD 0  to DD 5 . Each of source drivers sequentially latches data signals DD 0  to DD 5  that are pixel data. The latch operation of each of source drivers is done according to a cascade signal DOI from a preceding stage. The source driver IC 1  receives a logical signal of high level from a power-supply voltage terminal VDD as the cascade signal DOI of the preceding stage. 
     As mentioned above, the plane display device has been enlarged and highly miniaturized, and then the number of pixels of one horizontal line has been increasing. Therefore, a high-speed forwarding of the data signal and the like that is transmitted between the controller and each source driver is needed. In a liquid crystal display, mini-LVDS is generally used as an interface for a high-speed forwarding between this controller and each source driver. The interface standard of this mini-LVDS exchanges data and clock signals between a transmitting circuit and a reception circuit with LVDS (Low voltage differential signaling) shown in  FIG. 7 . 
     As shown in  FIG. 7 , the controller  10  includes a transmitting circuit Tx, and each of source drivers IC 1  to IC 4  includes a reception circuit Rx.  FIG. 7  only shows the controller  10  and the source driver IC 1 . The transmitting circuit Tx and the reception circuit Rx are connected with signal buses LVDS+ and LVDS−. A differential signal is transmitted to the signal buses LVDS+ and LVDS−. The transmitting circuit Tx allows current to flow between the signal bus LVDS+, a terminator resistor R 1 , and the signal bus LVDS−. Then, the reception circuit Rx decides a logical value of the reception signal according to a polarity of potential difference caused at both ends of the terminator resistor R 1 . In such circuit configuration, noise reduction such as EMI (Electro Magnetic Interference) is possible with a coupling between the signal buses LVDS+ and LVDS−. 
       FIG. 8  shows a block diagram of each of source drivers IC 1  to IC 4 . The source drivers IC 1  to IC 4  have basically similar the configuration, and thus only the configuration of the source driver IC 1  will be explained below. The source driver IC 1  includes reception circuits RxDD 0  to RxDD 5 , RxCLK, an enable control circuit  21 , a divide-by-4 frequency divider  22 , a DOI signal generation circuit  23  and a data register  24 . 
     Each of reception circuits RxDD 0  to RxDD 5 , and RxCLK receives VLDS signal from the controller  10  similarly to the reception circuit Rx of  FIG. 7 . Reception circuits RxDD 0  to RxDD 5  and RxCLK receive data signals DD 0  to DD 5  and the clock signal CLK that are VLDS signals, respectively. Signals received by reception circuits RxDD 0  to RxDD 5  and RxCLK are converted to CMOS signal level and are output to circuits provided at the subsequent stage. 
     The enable control circuit  21  controls reception circuits RxDD 0  to RxDD 5  and RxCLK to be in an active state or a standby state according to an enable signal REC_EN. The configuration of the enable control circuit  21  is described later. 
     The divide-by-4 frequency divider  22  divides frequency of a clock signal of CMOS signal level output by the reception circuit RxCLK by four. The clock signal CLK whose frequency is divided by four is used as an internal operation clock of the source driver IC 1 . Thus the source driver IC 1  decreases power consumption. Hereinafter, the clock signal whose frequency is divided by four is called an internal operation clock signal. The active state or the standby state of the divide-by-4 frequency divider  22  is controlled according to the enable signal REC_EN of the enable control circuit  21 . 
     Upon receiving a cascade signal DIO of high level, the DOI signal generation circuit  23  outputs the cascade signal DOI of high level for a predetermined period after a predetermined number of clocks. The DOI signal generation circuit  23  includes a shift register  30 . The shift register  30  counts the clock signal CLK that is output by the reception circuit RxCLK for predetermined number of clocks. One example of the operation of the DOI signal generation circuit  23  will be briefly explained below. 
     When the cascade signal DIO of high level is received, the DOI signal generation circuit  23  makes the shift register  30  start to count the number of clocks of the clock signal CLK. Then, when the shift register  30  counts the predetermined number of clocks, the DOI signal generation circuit  23  outputs the cascade signal DOI of high level for a predetermined period. The predetermined period in which this cascade signal DOI keeps the high level corresponds to, for instance, one cycle of the operation clock. 
     Here, the configuration of the enable control circuit  21  is shown in  FIG. 9 . As shown in  FIG. 9 , the enable control circuit  21  includes delay circuits DLY 1 , DLY 2 , a NAND circuit NAND 1 , a NOR circuit NOR 1 , an inverter circuit IV 1 , and an RS latching circuit RS 1 . 
     The delay circuit DLY 1  includes inverter circuits IV 11  to IV 13 . The inverter circuits IV 11  to IV 13  that are sequentially connected with series constitute an inverter chain. The inverter circuit IV 11  of the first stage receives the loading signal LOAD. Then, the inverter circuit IV 13  of the final stage outputs the loading signal LOAD delayed for a predetermined period. 
     The NAND circuit NAND 1  has one input terminal to which the loading signal LOAD is input, and the other input terminal to which the loading signal LOAD delayed for the predetermined period output by the inverter circuit IV 13  is input. The NAND circuit NAND 1  outputs an operation result to the inverter circuit IV 1 . The inverter circuit IV 1  inverts the output signal of the NAND circuit NAND 1 , and outputs the inverted signal as a REC_SET signal. Therefore, the REC_SET signal is a pulse signal that is in the high level by an amount of delay generated in the delay circuit DLY 1  from the rising edge of the loading signal LOAD. 
     The delay circuit DLY 2  includes inverter circuits IV 21  to IV 23 . The inverter circuits IV 21  to IV 23  that are sequentially connected with series constitute an inverter chain. The inverter circuit IV 21  of the first stage receives the cascade signal DOI. Then, the inverter circuit IV 23  of the final stage outputs the cascade signal DOI delayed for a predetermined period. 
     The NOR circuit NOR 1  has one terminal to which the cascade signal DOI is input, and the other input terminal to which the cascade signal DOI delayed for the predetermined period output by the inverter circuit IV 23  is input. The NOR circuit NOR 1  outputs an operation result as a REC_RSET signal. Therefore, the REC_RSET signal is a pulse signal that is in the high level by an amount of delay generated in the delay circuit DLY 2  from the falling edge of the cascade signal DOI. 
     The RS latching circuit RS 1  has a set terminal S to which the REC_SET signal is input, and has a reset terminal R to which the REC_RSET signal is input. Then, the RS latching circuit RS 1  outputs an enable signal REC_EN according to the REC_SET signal and the REC_RSET signal. In detail, when receiving the REC_SET signal of high level, the RS latching circuit RS 1  outputs the enable signal REC_EN of high level from an output terminal Q. Alternatively, when receiving the REC_RSET signal of high level, the RS latching circuit RS 1  outputs the enable signal REC_EN of low level from the output terminal Q. 
       FIG. 10  shows a circuit configuration of reception circuits RxDD 0  to RxDD 5  and RxCLK. The reception circuits RxDD 0  to RxDD 5  and RxCLK have basically the similar configuration, and thus only the configuration of the reception circuit RxDD 0  will be explained below. As shown in  FIG. 10 , the reception circuit RxDD 0  includes PMOS transistors MP 1  to MP 6 , NMOS transistors MN 1  to MN 8 , a NAND circuit NAND 31 , an inverter circuit IV 31 , and a current supply CC 31 . 
     A differential stage is composed of the current supply CC 31  and PMOS transistors MP 1  and MP 2 , and the NMOS transistor MN 1 . The differential stage receives the LVDS signal. An amplifying stage is composed of PMOS transistors MP 3  to MP 6  and NMOS transistors MN 5  to MN 8 . The amplifying stage amplifies the signal that is output from the above-mentioned differential stage. 
     When the enable signal REC_EN is in the high level, the LVDS signal becomes a signal at CMOS level and it is output from the reception circuit RxDD 0 . On the other hand, when the enable signal REC_EN is in the low level, NMOS transistors MN 1  to MN 4  interrupt current pathways between a power-supply voltage terminal VDD and a voltage terminal VSS. Further, an output of the NAND circuit NAND 31  is fixed to the high level by the enable signal REC_EN of low level. Therefore, an output of the inverter circuit IV 31 , which is the output of the reception circuit RxDD 0  is fixed to the low level and the reception circuit RxDD 0  is in the standby state. Accordingly, the active state or the standby state of the reception circuit RxDD 0  is controlled according to the enable signal REC_EN. 
       FIGS. 11 to 13  show timing charts that show operation of source drivers IC 1  to IC 4 . Note that the same reference symbols of time in  FIGS. 11 to 13  indicate the same time. In addition, it is assumed that reception circuits RxCLK and RxDD 0  to RxDD 5  of all source drivers are in the standby state before time t 1 . 
     The loading signal LOAD of high level is received by source drivers IC 1  to IC 4  at time t 1 . In the enable control circuit  21  of each of source drivers, the REC_SET signal of a pulse signal is generated according to the rising edge of this loading signal LOAD. The enable signal REC_EN of high level is output from the RS latching circuit RS 1  according to this REC_SET signal. Then, reception circuits RxCLK and RxDD 0  to RxDD 5  of each of source drivers enter the active state according to this enable signal REC_EN. 
     All source drivers receive data signal DD 0  of high level as reset data RST at time t 2 . In a mini-LVDS interface, after the reception circuit Rx enters active state, the data signal DD 0  that is in the high level is set to the reset data RST for four cycles of the clock signal CLK (period T 1 ). 
     After receiving the reset data RST, the divide-by-4 frequency divider  22  outputs the internal operation clock signal at time t 3  in each of all source drivers. Each source driver operates according to this internal operation clock signal. Because the cascade signal DIO is in the high level, the source driver IC 1  starts taking data of data signals DD 0  to DD 5  at timings of rising and falling edges of the clock signal CLK. Here, because the data is taken according to timings of rising and falling edges of the clock signal CLK as mentioned above, the data of eight bits is taken into the source driver IC 1  in each one cycle of the internal operation clock for each data signal line. 
     Here, when (m×6)/8 pixel signal lines (m is a multiple of four) are driven for each one source driver, data taking of this one source driver is completed at the m-th edge timing of the clock signal CLK. Therefore, the source driver IC 1  takes data of data signals DD 0  to DD 5  at each edge of the clock signal CLK between the edge of the clock signal CLK at time t 3  (the first edge) and the edge of the clock signal CLK at time t 5  (the m-th edge). 
     The shift register  30  of the source driver IC 1  counts the (m−3)-th edge of the clock signal CLK at time t 4 . Then, the shift register  30  informs the DOI signal generation circuit  23  that the count reaches the predetermined number. Then, at this timing the DOI signal generation circuit  23  of the source driver IC 1  raises the cascade signal DOI to the high level. Note that the cascade signal DOI of this source driver IC 1  is the cascade signal DIO of the source driver IC 2 . 
     At time t 7  after one cycle of the internal operation clock from time t 4 , the DOI signal generation circuit  23  of the source driver IC 1  lowers the cascade signal DOI to the low level. In addition, the REC_RSET signal of a pulse signal is generated by the enable control circuit  21  of the source driver IC 1  according to this falling edge. The enable signal REC_EN of low level is output from the RS latching circuit RS 1  according to this REC_RSET signal. Then, reception circuits RxCLK and RxDD 0  to RxDD 5  of the source driver IC 1  enter the standby state according to this enable signal REC_EN of low level. Moreover, the divide-by-4 frequency divider  22  that generates the internal operation clock enters the standby state, too. Therefore, the source driver IC 1  enters the standby state. 
     On the other hand, the source driver IC 2  that receives the cascade signal DIO of high level starts to take data of data signals DD 0  to DD 5  at each edge of the clock signal CLK from the rising edge of the internal operation clock at time t 6 . Note that the edge of the clock signal CLK at time t 6  is (m+1)-th edge. Therefore, the source driver IC 2  takes data of data signals DD 0  to DD 5  at each edge of the clock signal CLK between the edge of the clock signal CLK at time t 6  (the (m+1)-th edge) and the edge of the clock signal CLK at time t 9  (the 2 m-th edge). At the same time, the shift register  30  of the source driver IC 2  starts to count the edge of the clock signal CLK at time t 6 . 
     The shift register  30  of the source driver IC 2  counts the (m−3)-th edge of the clock signal CLK at time t 8 . Then, the shift register  30  informs the DOI signal generation circuit  23  that the count reaches the predetermined number. Then, at this timing the DOI signal generation circuit  23  of the source driver IC 2  raises the cascade signal DOI to the high level. The cascade signal DOI of this source driver IC 2  is the cascade signal DIO of the source driver IC 3 . 
     At time t 11  after one cycle of the internal operation clock from time t 8 , the DOI signal generation circuit  23  of the source driver IC 2  lowers the cascade signal DOI to the low level. In addition, the REC_RSET signal of a pulse signal is generated by the enable control circuit  21  of the source driver IC 2  according to this falling edge. The enable signal REC_EN of low level is output from the RS latching circuit RS 1  according to this REC_RSET signal. Then, reception circuits RxCLK and RxDD 0  to RxDD 5  of the source driver IC 2  enter the standby state according to this enable signal REC_EN of low level. Moreover, the divide-by-4 frequency divider  22  that generates the internal operation clock enters the standby state, too. Therefore, the source driver IC 2  enters the standby state. 
     After this, source drivers IC 3  and IC 4  perform the similar operation as described above. More specifically, the source driver IC 3  that receives the cascade signal DIO of high level starts to take data of data signals DD 0  to DD 5  at each edge of the clock signal CLK from the rising edge of the internal operation clock at time t 10 . Note that the edge of the clock signal CLK at time t 10  is (2 m+1)-th edge. Therefore, the source driver IC 3  takes data of data signals DD 0  to DD 5  at each edge of the clock signal CLK between the edge of the clock signal CLK at time t 10  (the (2 m+1)-th edge) and the edge of the clock signal CLK at time t 13  (the 3m-th edge). At the same time, the shift register  30  of the source driver IC 3  starts to count the edge of the clock signal CLK at time t 10 . 
     The shift register  30  of the source driver IC 3  counts the (m−3)-th edge of the clock signal CLK at time t 12 . Then, the shift register  30  informs the DOI signal generation circuit  23  that the count reaches the predetermined number. Then, at this timing the DOI signal generation circuit  23  of the source driver IC 3  raises the cascade signal DOI to the high level. The cascade signal DOI of this source driver IC 3  is the cascade signal DIO of the source driver IC 4 . 
     At time t 15  after one cycle of the internal operation clock from time t 12 , the DOI signal generation circuit  23  of the source driver IC 3  lowers the cascade signal DOI to the low level. In addition, the REC_RSET signal of a pulse signal is generated by the enable control circuit  21  of the source driver IC 3  according to this falling edge. The enable signal REC_EN of low level is output from the RS latching circuit RS 1  according to this REC_RSET signal. Then, reception circuits RxCLK and RxDD 0  to RxDD 5  of the source driver IC 3  enter the standby state according to this enable signal REC_EN of low level. Moreover, the divide-by-4 frequency divider  22  that generates the internal operation clock enters the standby state, too. Therefore, the source driver IC 3  enters the standby state. 
     The source driver IC 4  that receives the cascade signal DIO of high level starts to take data of data signals DD 0  to DD 5  at each edge of the clock signal CLK from the rising edge of the internal operation clock at time t 14 . Note that the edge of the clock signal CLK at time t 14  is (3 m+1)-th edge. Therefore, the source driver IC 4  takes data of data signals DD 0  to DD 5  at each edge of the clock signal CLK between the edge of the clock signal CLK at time t 14  (the (3 m+1)-th edge) and the edge of the clock signal CLK at time t 17  (the 4m-th edge). At the same time, the shift register  30  of the source driver IC 4  starts to count the edge of the clock signal CLK at time t 14 . 
     The shift register  30  of the source driver IC 4  counts the (m −3 )-th edge of the clock signal CLK at time t 16 . Then, the shift register  30  informs the DOI signal generation circuit  23  that the count reaches the predetermined number. Then, at this timing the DOI signal generation circuit  23  of the source driver IC 4  raises the cascade signal DOI to the high level. The cascade signal DOI of this source driver IC 4  is the cascade signal DIO of a source driver of the subsequent stage. 
     At time t 19  after one cycle of the internal operation clock from time t 16 , the DOI signal generation circuit  23  of the source driver IC 4  lowers the cascade signal DOI to the low level. In addition, the REC_RSET signal of a pulse signal is generated by the enable control circuit  21  of the source driver IC 4  according to this falling edge. The enable signal REC_EN of low level is output from the RS latching circuit RS 1  according to this REC_RSET signal. Then, reception circuits RxCLK and RxDD 0  to RxDD 5  of the source driver IC 4  enter the standby state according to this enable signal REC_EN of low level. Moreover, the divide-by-4 frequency divider  22  that generates the internal operation clock enters the standby state, too. Therefore, the source driver IC 4  enters the standby state. 
     A technology of a liquid crystal display device that includes source drivers having a cascade connection configuration is disclosed in Japanese Unexamined Patent Application Publication No. 2005-284217. 
     SUMMARY 
     The present inventor has found a problem as described below. In the plane display device  1  of the related art, the reception circuits RxCLK and RxDD 0  to RxDD 5  of source drivers IC 1  to IC 4  are in the active state from time t 1  as shown in  FIG. 11  to  FIG. 13 . This is due to the fact that reception circuits RxDD 0  and RxCLK which receive the clock signal CLK and the reset data RST of each of source drivers enter the active state at time t 1  in the mini-LVDS interface standard. 
     However, source drivers IC 1  to IC 4  that are connected with cascade connection need not make reception circuits RxDD 1  to RxDD 5  active other than reception circuits RxDD 0  and RxCLK until the cascade signal DIO of high level is received. Therefore, in reception circuits RxDD 1  to RxDD 5 , unnecessary power is consumed. Moreover, even if a source driver is in the standby state, power consumption of the source driver keeps increasing in a liquid crystal display device or the like that is enlarged and highly miniaturized. Therefore, it is necessary to reduce wasting power consumption as mentioned above for the decrease of power consumption of source drivers. 
     A first exemplary aspect of an embodiment of the invention is a source driver having a cascade connection configuration that drives signal lines of a display device according to a plurality of signals transmitted by a mini-LVDS interface from a controller during a predetermined period corresponding to a cascade signal received from a preceding stage, the source driver including: a first reception circuit that receives a first signal of the plurality of signals; a second reception circuit that receives a second signal of the plurality of signals; and an enable control circuit that controls each of the first reception circuit and the second reception circuit to one of an active state and a standby state; in which the enable control circuit sets the second reception circuit to the active state according to the cascade signal received from the preceding stage, and sets the first and second reception circuits to the standby state according to a cascade signal output by the source driver to a subsequent stage. 
     The source driver in accordance with an exemplary aspect of the present invention sets the second reception circuit to the active state according to the cascade signal received from the preceding stage. Then the source driver sets the second reception circuit to the standby state according to the cascade signal output by the source driver to the subsequent stage. Therefore, the second reception circuit can enter the standby state during a period in which the second reception circuit needs not enter the active state in the source driver that has a cascade connection configuration. Then, power consumption in the source driver can be reduced during the period in which the second reception circuit needs not enter the active state. 
     The power consumption can be reduced according to the source driver in accordance with the exemplary aspect of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other exemplary aspects, advantages and features will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is an example of a configuration of a source driver in accordance with an exemplary embodiment of the present invention; 
         FIG. 2  is an example of a configuration of an enable control circuit of the source driver in accordance with the exemplary embodiment of the present invention; 
         FIG. 3  is a timing chart for explaining operations of a display device in accordance with the exemplary embodiment of the present invention; 
         FIG. 4  is a timing chart for explaining operations of the display device in accordance with the exemplary embodiment of the present invention; 
         FIG. 5  is a timing chart for explaining operations of the display device in accordance with the exemplary embodiment of the present invention; 
         FIG. 6  is a configuration of a general display device; 
         FIG. 7  is a schematic diagram to explain an LVDS interface. 
         FIG. 8  is a configuration of a source driver of a related art; 
         FIG. 9  is a configuration of an enable control circuit of the source driver of the related art; 
         FIG. 10  is a circuit configuration of a reception circuit. 
         FIG. 11  is a timing chart for explaining operations of a display device of a related art; 
         FIG. 12  is a timing chart for explaining operations of the display device of the related art; and 
         FIG. 13  is a timing chart for explaining operations of the display device of the related art; 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     Exemplary Embodiment 
     A specific exemplary embodiment of the present invention is explained hereinafter with reference to the drawings. In this exemplary embodiment, the present invention is applied to source drivers IC 1  to IC 4  of a liquid crystal display device. Note that a block configuration of the liquid crystal display device of this exemplary embodiment is similar to that shown in  FIG. 6 , and therefore explanation of the configuration thereof is omitted here. Therefore, source drivers IC 1  to IC 4  in  FIG. 6  are replaced by source drivers IC 1  to IC 4  in this exemplary embodiment. 
       FIG. 1  shows a block diagram of source drivers IC 1  to IC 4 . Note that the source drivers IC 1  to IC 4  have the similar configuration. Therefore, only a configuration of the source driver IC 1  will be explained in the following description. 
     As shown in  FIG. 1 , the source driver IC 1  includes reception circuits RxDD 0  to RxDD 5 , and RxCLK, an enable control circuit  100 , a divide-by-4 frequency divider  22 , a DOI signal generation circuit  23  and a data register  24 . In  FIG. 1 , the configurations denoted by the same reference symbols as in  FIG. 8  indicate the same or similar configurations as those therein. The enable control circuit  100  is different between the source driver IC 1  of  FIG. 1  and the source driver IC 1  of  FIG. 8 . Thus the above different point is mainly described in this exemplary embodiment. 
     As shown in  FIG. 1 , enable signals REC_EN 1  and REC_EN 3  described later are output from the enable control circuit  100 . The enable signal REC_EN 1  is supplied to reception circuits RxCLK and RxDD 0 . The enable signal REC_EN 3  is supplied to reception circuits RxDD 1  to RxDD 5 . Hereinafter, the enable control circuit  100 , which is a feature part of this invention, is mainly described in this exemplary embodiment. 
       FIG. 2  shows the configuration of the enable control circuit  100 . As shown in  FIG. 2 , the enable control circuit  100  includes delay circuits DLY 101 , DLY 111  and DLY 121 , NAND circuits NAND 101  and  102 , a NOR circuit NOR 101 , inverter circuits IV 101  and IV 102 , RS latching circuits RS 101  and RS 102 , a D flip-flop DFF 101 , and a selector SEL 101 . 
     The delay circuit DLY 101  includes inverter circuits IV 101  to IV 103 . The inverter circuits IV 101  to IV 103  that are sequentially connected with series constitute an inverter chain. The inverter circuit IV 101  of the first stage receives a loading signal LOAD. Then, the inverter circuit IV 103  of the final stage outputs the loading signal LOAD delayed for a predetermined period. 
     The NAND circuit NAND has one input terminal to which the loading signal LOAD is input, and the other input terminal to which the loading signal LOAD delayed for the predetermined period output by the inverter circuit IV 103  is input. The NAND circuit NAND outputs an operation result to the inverter circuit IV 101 . The inverter circuit IV 101  inverts the output signal of the NAND circuit NAND 101 , and outputs the inverted signal as a REC_SET 1  signal. Therefore, the REC_SET 1  signal is a pulse signal that is in high level by an amount of delay generated in the delay circuit DLY 101  from the rising edge of the loading signal LOAD. 
     The delay circuit DLY 111  includes inverter circuits IV 111  to IV 113 . The inverter circuits IV 111  to IV 113  that are sequentially connected with series constitute an inverter chain. The inverter circuit IV 111  of the first stage receives a cascade signal DOI. Then, the inverter circuit IV 113  of the final stage outputs the cascade signal DOI delayed for a predetermined period. 
     The NOR circuit NOR 101  has one input terminal to which the cascade signal DOI is input, and the other input terminal to which the cascade signal DOI delayed for the predetermined period output by the inverter circuit IV 113  is input. The NOR circuit NOR 101  outputs an operation result as a REC_RSET signal. Therefore, the REC_RSET signal is a pulse signal that is in the high level by an amount of delay generated in the delay circuit DLY 111  from the falling edge of the cascade signal DOI. 
     The delay circuit DLY 121  includes inverter circuits IV 121  to IV 123 . The inverter circuits IV 121  to IV 123  that are sequentially connected with series constitute an inverter chain. The inverter circuit IV 121  of the first stage receives a cascade signal DIO. Then, the inverter circuit IV 123  of the final stage outputs the cascade signal DIO delayed for a predetermined period. 
     The NAND circuit NAND 102  has one input terminal to which the cascade signal DIO is input, and the other input terminal to which the cascade signal DIO delayed for the predetermined period output by the inverter circuit IV 123  is input. The NAND circuit NAND 102  outputs an operation result to the inverter circuit IV 102 . The inverter circuit IV 102  inverts the output signal of the NAND circuit NAND 102 , and outputs the inverted signal as a REC_SET 2  signal. Therefore, the REC_SET 2  signal is a pulse signal that is in the high level by an amount of delay generated in the delay circuit DLY 121  from the rising edge of the cascade signal DIO. 
     The RS latching circuit RS 101  has a set terminal S to which the REC_SET 1  signal is input, and has a reset terminal R to which the REC_RSET signal is input. Then, the RS latching circuit RS 101  outputs an enable signal REC_EN 1  according to the REC_SET 1  signal and the REC_RSET signal. In detail, when receiving the REC_SET 1  signal of high level, the RS latching circuit RS 101  outputs the enable signal REC_EN 1  of high level from an output terminal Q. When receiving the REC_RSET signal of high level, the RS latching circuit RS 101  outputs the enable signal REC_EN 1  of low level from the output terminal Q. 
     The RS latching circuit RS 102  has a set terminal S to which the REC_SET 2  signal is input, and has a reset terminal R to which the REC_RSET signal is input. Then, the RS latching circuit RS 102  outputs an enable signal REC_EN 2  according to the REC_SET 2  signal and the REC_RSET signal. In detail, when receiving the REC_SET 2  signal of high level, the RS latching circuit RS 102  outputs the enable signal REC_EN 2  of high level from the output terminal Q. When receiving the REC_RSET signal of high level, the RS latching circuit RS 102  outputs the enable signal REC_EN 2  of low level from the output terminal Q. 
     The D flip-flop DFF 101  has a data input terminal D to which the cascade signal DIO is input, and a clock input terminal to which the loading signal LOAD is input. The D flip-flop DFF 101  latches the cascade signal DIO according to the rising edge of the loading signal LOAD. Then, the value that the D flip-flop DFF 101  latches is output from a data output terminal Q as a CHIP — 1 signal. 
     Because the cascade signal DIO is always in the high level (power-supply voltage VDD), the D flip-flop DFF 101  of the source driver IC 1  outputs a CHIP — 1 signal of high level according to a timing that the loading signal LOAD is raised up to high level. The D flip-flop DFF 101  of each of source drivers IC 2  to IC 4  outputs a CHIP — 1 signal of low level at a timing that the loading signal LOAD is raised up to high level because the cascade signal DIO is in the low level. 
     The selector SEL 101  has one input terminal to which the enable signal REC_EN 1  is input, and the other input terminal to which the enable signal REC_EN 2  is input. Then, the selector SEL 101  selects one of enable signals REC_EN 1  and REC_EN 2 , and outputs the select signal as the enable signal REC_EN 3 . In detail, when the CHIP — 1 signal is in the high level (the value is “1”), the enable signal REC_EN 1  is output as the enable signal REC_EN 3 . Alternatively, when the CHIP — 1 signal is in the low level (the value is “0”), the enable signal REC_EN 2  is output as the enable signal REC_EN 3 . As described above, it is only the source driver IC 1  that the CHIP — 1 signal is in the high level. Therefore, only the source driver IC 1  outputs the enable signal REC_EN 1  as the enable signal REC_EN 3 . In the other source drivers IC 2  to IC 4 , the enable signal REC_EN 2  is outputs as the enable signal REC_EN 3 . 
     As mentioned above, the enable control circuit  100  outputs enable signals REC_EN 1  and REC_EN 3 . Reception circuits RxCLK and RxDD 0  receive the enable signal REC_EN 1 , and reception circuits RxDD 1  to RxDD 5  receive the enable signal REC_EN 3 . Therefore, an active state and a standby state of reception circuits RxCLK and RxDD 0  are controlled according to the enable signal REC_EN 1 . Further, an active state and a standby state of reception circuits RxDD 1  to RxDD 5  are controlled according to the enable signal REC_EN 3 . 
       FIG. 3  to  FIG. 5  show timing charts that show the operation of source drivers IC 1  to IC 4  that include the enable control circuit  100  in this exemplary embodiment. Note that the same reference symbols of time in  FIGS. 3 to 5  indicate the same time. In addition, it is assumed that reception circuits RxCLK and RxDD 0  to RxDD 5  of all source drivers are in the standby state before time t 1 . 
     The loading signal LOAD of high level is received by source drivers IC 1  to IC 4  at time t 1 . In the enable control circuit  100  of each of source drivers, the REC_SET 1  signal of a pulse signal is generated according to the rising edge of this loading signal LOAD. The enable signal REC_EN 1  of high level is output from the RS latching circuit RS 101  according to the REC_SET 1  signal. Then, reception circuits RxCLK and RxDD 0  of each of all source drivers enter the active state according to this enable signal REC_EN 1 . 
     Moreover, the CHIP — 1 of the source driver IC 1  is in the high level at this time t 1 . The selector SEL 101  selects the enable signal REC_EN 1 . Therefore, the enable signal REC_EN 3  of the source driver IC 1  becomes the enable signal REC_EN 1  of high level as mentioned above. Therefore, reception circuits RxDD 1  to RxDD 5  of the source driver IC 1  enter the active state. On the other hand, the CHIP — 1 of source drivers IC 2  to IC 4  are in the low level. Therefore, the enable signal REC_EN 3  of the source drivers IC 2  to IC 4  becomes the enable signal REC_EN 2  of low level as mentioned above. Therefore, reception circuits RxDD 1  to RxDD 5  of the source drivers IC 2  to IC 4  are in the standby state. 
     The reception circuits RxDD 0  of all source drivers receive a data signal DD 0  of high level as a reset data RST at time t 2 . In a mini-LVDS interface, after the reception circuit Rx enters the active state, the data signal DD 0  that is in the high level is set to the reset data RST for four cycles of the clock signal CLK (period T 1 ). After receiving the reset data RST, the divide-by-4 frequency divider  22  outputs an internal operation clock signal at time t 3  in each of all source drivers. Each source driver operates according to this internal operation clock signal. 
     Because the cascade signal DIO is in the high level, the source driver IC 1  starts taking data of data signals DD 0  to DD 5  at timings of rising and falling edges of the clock signal CLK. Here, because the data is taken according to timings of rising and falling edges of the clock signal CLK as mentioned above, the data of eight bits is taken into the source driver in each one cycle of the internal operation clock for each data signal line. 
     Here, when (m×6)/8 pixel signal lines (m is a multiple of four) are driven for each one source driver, data taking of this one source driver is completed at the m-th edge timing of the clock signal CLK. Therefore, as shown in  FIG. 3 , the source driver IC 1  takes data of data signals DD 0  to DD 5  at each edge of the clock signal CLK between the edge of the clock signal CLK at time t 3  (the first edge) and the edge of the clock signal CLK at time t 5  (the m-th edge). 
     The shift register  30  of the source driver IC 1  counts the (m−3)-th edge of the clock signal CLK at time t 4 . Then, the shift register  30  informs the DOI signal generation circuit  23  that the count reaches the predetermined number. Then, the DOI signal generation circuit  23  of the source driver IC 1  raises the cascade signal DOI to the high level at this timing. Note that the cascade signal DOI of this source driver IC 1  is the cascade signal DIO of the source driver IC 2 . 
     At time t 7  after one cycle of the internal operation clock from time t 4 , the DOI signal generation circuit  23  of the source driver IC 1  lowers the cascade signal DOI to the low level. In addition, the REC_RSET signal of a pulse signal is generated by the enable control circuit  100  of the source driver IC 1  according to this falling edge. The enable signal REC_EN 1  of low level is output from the RS latching circuit RS 101  according to this REC_RSET signal. Then, reception circuits RxCLK and RxDD 0  of the source driver IC 1  enter the standby state according to this enable signal REC_EN 1  of low level. In addition, the enable signal REC_EN 1  of low level is output from the selector SEL 101  as the enable signal REC_EN 3 . Therefore, reception circuits RxDD 1  to RxDD 5  enter the standby state as well as the reception circuits RxCLK and RxDD 0  mentioned above. Moreover, the divide-by-4 frequency divider  22  that generates the internal operation clock enters the standby state, too. Therefore, the source driver IC 1  enters the standby state. 
     On the other hand, the source driver IC 2  receives the cascade signal DIO of high level at time t 4 . In the enable control circuit  100  of the source driver IC 2 , the REC_SET 2  signal of a pulse signal is generated according to the rising edge of this cascade signal DIO. The enable signal REC_EN 2  of high level is output from the RS latching circuit RS 102  according to this REC_SET 2  signal. Here, the CHIP — 1 signal of the source driver IC 2  is in the low level as state above. Therefore, the selector SEL 101  selects the enable signal REC_EN 2 . In other words, REC_EN 2 =REC_EN 3 . Therefore, the enable signal REC_EN 3  of the source driver IC 2  also rises to the high level, and the reception circuits RxDD 1  to RxDD 5  of the source driver IC 2  enter the active state. 
     After that, the source driver IC 2  that receives the cascade signal DIO of high level starts to take data of data signals DD 0  to DD 5  at each edge of the clock signal CLK from the rising edge of the internal operation clock at time t 6 . Note that the edge of the clock signal CLK at time t 6  is (m+1)-th edge. Therefore, the source driver IC 2  takes data of data signals DD 0  to DD 5  at each edge of the clock signal CLK between the edge of the clock signal CLK at time t 6  (the (m+1)-th edge) and the edge of the clock signal CLK at time t 9  (the 2 m-th edge). At the same time, the shift register  30  of the source driver IC 2  starts to count the edge of the clock signal CLK at time t 6 . 
     The shift register  30  of the source driver IC 2  counts the (m −3 )-th edge of the clock signal CLK at time t 8 . Then, the shift register  30  informs the DOI signal generation circuit  23  that the count reaches the predetermined number. Then, at this timing the DOI signal generation circuit  23  of the source driver IC 2  raises the cascade signal DOI to the high level. Note that the cascade signal DOI of this source driver IC 2  is the cascade signal DIO of the source driver IC 3 . 
     At time t 11  after one cycle of the internal operation clock from time t 8 , the DOI signal generation circuit  23  of the source driver IC 2  lowers the cascade signal DOI to the low level. In addition, the REC_RSET signal of a pulse signal is generated by the enable control circuit  100  of the source driver IC 2  according to this falling edge. The enable signal REC_EN 1  of low level is output from the RS latching circuit RS 101  according to this REC_RSET signal. Moreover, the enable signal REC_EN 2  of low level is output from the RS latching circuit RS 102  with the REC_RSET signal. Then, reception circuits RxCLK and RxDD 0  of the source driver IC 2  enter the standby state according to this enable signal REC_EN 1  of low level. Moreover, the enable signal REC_EN 2  of low level is output from the selector SEL 101  as the enable signal REC_EN 3 . Therefore, reception circuits RxDD 1  to RxDD 5  enter the standby state as well as the reception circuits RxCLK and RxDD 0  mentioned above. Moreover, the divide-by-4 frequency divider  22  that generates the internal operation clock enters the standby state, too. Therefore, the source driver IC 2  enters the standby state. 
     After this, source drivers IC 3  and IC 4  perform the similar operation as the source driver IC 2 . More specifically, as shown in  FIG. 4  (and  FIG. 3 ), the source driver IC 3  receives the cascade signal DIO of high level at time t 8 . Then, in the enable control circuit  100  of the source driver IC 3 , the REC_SET 2  signal of a pulse signal is generated according to the rising edge of this cascade signal DIO. The enable signal REC_EN 2  of high level is output from the RS latching circuit RS 102  according to this REC_SET 2  signal. Because the CHIP — 1 signal of the source driver IC 3  is in the low level, the selector SEL 101  selects the enable signal REC_EN 2 . Therefore, REC_EN 2 =REC_EN 3 . Accordingly, the enable signal REC_EN 3  of the source driver IC 3  also rises to the high level, and the reception circuits RxDD 1  to RxDD 5  of the source driver IC 3  enter the active state. 
     Further, in the source driver IC 3  that receives the cascade signal DIO of high level starts to take data of data signals DD 0  to DD 5  at each edge of the clock signal CLK from the rising edge of the internal operation clock at time t 10 . Note that the edge of the clock signal CLK at time t 10  is (2 m+1)-th edge. Therefore, the source driver IC 3  takes data of data signals DD 0  to DD 5  at each edge of the clock signal CLK between the edge of the clock signal CLK at time t 10  (the (2 m+1)-th edge) and the edge of the clock signal CLK at time t 13  (the 3m-th edge). At the same time, the shift register  30  of the source driver IC 3  starts to count the edge of the clock signal CLK at time t 10 . 
     The shift register  30  of the source driver IC 3  counts the (m −3 )-th edge of the clock signal CLK at time t 12 . Then, the shift register  30  informs the DOI signal generation circuit  23  that the count reaches the predetermined number. Then, at this timing the DOI signal generation circuit  23  of the source driver IC 3  raises the cascade signal DOI to the high level. Note that the cascade signal DOI of this source driver IC 3  is the cascade signal DIO of the source driver IC 4 . 
     At time t 15  after one cycle of the internal operation clock from time t 12 , the DOI signal generation circuit  23  of the source driver IC 3  raises the cascade signal DOI fall to the low level. In addition, the REC_RSET signal of a pulse signal is generated by the enable control circuit  100  of the source driver IC 3  according to this falling edge. The enable signal REC_EN 1  of low level is output from the RS latching circuit RS 101  according to this REC_RSET signal. Moreover, the enable signal REC_EN 2  of low level is output from the RS latching circuit RS 102  with the REC_RSET signal. Then, reception circuits RxCLK and RxDD 0  of the source driver IC 3  enter the standby state according to this enable signal REC_EN 1  of low level. Moreover, the enable signal REC_EN 2  of low level is output from the selector SEL 101  as the enable signal REC_EN 3 . Therefore, reception circuits RxDD 1  to RxDD 5  enter the standby state as well as the reception circuits RxCLK and RxDD 0  mentioned above. Moreover, the divide-by-4 frequency divider  22  that generates the internal operation clock enters the standby state, too. Therefore, the source driver IC 3  enters the standby state. 
     Further, as shown in  FIG. 5  (and  FIG. 4 ), the source driver IC 4  receives the cascade signal DIO of high level at time t 12 . Then, in the enable control circuit  100  of the source driver IC 4 , the REC_SET 2  signal of a pulse signal is generated according to the rising edge of this cascade signal DIO. The enable signal REC_EN 2  of high level is output from the RS latching circuit RS 102  according to this REC_SET 2  signal. Because the CHIP — 1 signal of the source driver IC 4  is in the low level, the selector SEL 101  selects the enable signal REC_EN 2 . Therefore, REC_EN 2 =REC_EN 3 . Accordingly, the enable signal REC_EN 3  of the source driver IC 4  also rises to the high level, and the reception circuits RxDD 1  to RxDD 5  of the source driver IC 4  enter the active state. 
     Further, in the source driver IC 4  that receives the cascade signal DIO of high level starts to take data of data signals DD 0  to DD 5  at each edge of the clock signal CLK from the rising edge of the internal operation clock at time t 14 . Note that the edge of the clock signal CLK at time t 14  is (3 m+1)-th edge. Therefore, the source driver IC 4  takes data of data signals DD 0  to DD 5  at each edge of the clock signal CLK between the edge of the clock signal CLK at time t 14  (the (3 m+1)-th edge) and the edge of the clock signal CLK at time t 17  (the 4 m-th edge). At the same time, the shift register  30  of the source driver IC 4  starts to count the edge of the clock signal CLK at time t 14 . 
     The shift register  30  of the source driver IC 4  counts the (m−3)-th edge of the clock signal CLK at time t 16 . Then, the shift register  30  informs the DOI signal generation circuit  23  that the count reaches the predetermined number. Then, at this timing the DOI signal generation circuit  23  of the source driver IC 4  raises the cascade signal DOI to the high level. Note that the cascade signal DOI of this source driver IC 4  is the cascade signal DIO of a source driver of the subsequent stage. 
     At time t 19  after one cycle of the internal operation clock from time t 16 , the DOI signal generation circuit  23  of the source driver IC 4  lowers the cascade signal DOI to the low level. In addition, the REC_RSET signal of a pulse signal is generated by the enable control circuit  100  of the source driver IC 4  according to this falling edge. The enable signal REC_EN 1  of low level is output from the RS latching circuit RS 101  according to this REC_RSET signal. Moreover, the enable signal REC_EN 2  of low level is output from the RS latching circuit RS 102  with the REC_RSET signal. Then, reception circuits RxCLK and RxDD 0  of the source driver IC 4  enter the standby state according to this enable signal REC_EN 1  of low level. Moreover, the enable signal REC_EN 2  of low level is output from the selector SEL 101  as the enable signal REC_EN 3 . Therefore, reception circuits RxDD 1  to RxDD 5  enter the standby state as well as the reception circuits RxCLK and RxDD 0  mentioned above. Moreover, the divide-by-4 frequency divider  22  that generates the internal operation clock enters the standby state, too. Therefore, the source driver IC 4  enters the standby state. 
     Here, as shown in  FIG. 11  to  FIG. 13 , in the plane display device  1  of a related art, reception circuits RxCLK and RxDD 0  to RxDD 5  of the source drivers IC 1  to IC 4  are in the active state from time t 1 . This is due to the fact that reception circuits RxDD 0  and RxCLK which receive the clock signal CLK and the reset data RST of each of source drivers enter the active state at time t 1  in the mini-LVDS interface standard. 
     However, source drivers IC 1  to IC 4  need not make reception circuits RxDD 1  to RxDD 5  active other than reception circuits RxDD 0  and RxCLK until the cascade signal DIO of high level is received. Nevertheless, in the plane display device  1  of the related art, reception circuits RxDD 1  to RxDD 5  are continuously set to the active state from time t 1 . Therefore, in reception circuits RxDD 1  to RxDD 5 , unnecessary electric power is consumed. 
     However, in source drivers of the plane display device in this exemplary embodiment, reception circuits RxDD 1  to RxDD 5  can be set to the standby state until the cascade signal DIO of high level is received by each of source drivers because each of source drivers has the enable control circuit  100  that has the configuration as described above. Therefore, the power consumption of the source driver in this exemplary embodiment can be decreased compared with that of the related art. 
     Note that the present invention is not limited to the above exemplary embodiment but can be modified as appropriate within the scope of the present invention. For example, the interface between the transmitting circuit and the reception circuit is not limited to the mini-LVDS. For example, in the above-mentioned exemplary embodiment, the reception circuit RxDD 0  is in the active state from time t 1  in all source drivers since the reception circuit RxDD 0  receives the reset data RST. However, the reception circuit RxDD 0  may enter the standby state until the cascade signal DIO of high level is received as is similar to reception circuits RxDD 1  to RxDD 5  when it is not required to comply with such protocol. 
     While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above. 
     Further, the scope of the claims is not limited by the exemplary embodiments described above. 
     Furthermore, it is noted that, Applicant&#39;s intent is to encompass equivalents of all claim elements, even if amended later during prosecution.