Patent Publication Number: US-2023147226-A1

Title: Size setting method for power switch transistor and system thereof

Description:
RELATED APPLICATIONS 
     This application claims priority to Taiwan Application Serial Number 110141558, filed Nov. 8, 2021, which is herein incorporated by reference. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates o a size setting method for at least one power switch transistor and a system thereof. More particularly, the present disclosure relates to use a load current of a logic circuit to set a size of at least one power switch transistor, and the logic circuit configured with the at least one power switch transistor still maintains high-speed transmission. 
     Description of Related Art 
     In recent years, due to the increasing of electronic circuit devices integrated with semiconductor materials, the demand for low power consumption technologies has also gradually increased. One of the low power consumption technologies is to configure Multi-Threshold CMOS (MTCMOS) in a logic circuit. MTCMOS is an effective power switch control technology, which reduces the leakage current and the power consumption of the logic circuit and maintains the speed performance required by the logic circuit through appropriately alternating high-threshold voltage transistors and low-threshold voltage transistors. 
     However, many MTCMOSs as logic gates are often overloaded, which greatly affects the speed of the logic circuit. The main reason why the speed of the logic gate having been overloaded will slow down is that the large voltage drop at the source-drain terminals causes the gate-source voltage (Vgs) to become smaller. An effective method to solve the aforementioned situation is to configure the minimum size of MTCMOS according to a load (i.e., the logic circuit) of MTCMOS. 
     In view of this, how to establish a size setting method for at least one power switch transistor and a system thereof that can meet the speed required by the logic circuit are indeed highly anticipated by the public and become the goal and the direction of relevant industry efforts. 
     SUMMARY 
     According to one aspect of the present disclosure, a size setting method for at least one power switch transistor includes performing a first load current extracting step, a second load current extracting step, a limited voltage drop calculating step, a standard supply current calculating step, a simulated supply current calculating step and a size setting step. The first load current extracting step is performed to drive a processing unit to extract a first load current of a first logic circuit. The first logic circuit is connected to a power supply voltage via the at least one power switch transistor and at least one power line to generate the first load current, and the at least one power line has at least one line voltage. The second load current extracting step is performed to drive the processing unit to extract a second load current of a second logic circuit. The second logic circuit is connected to the power supply voltage to generate the second load current. The limited voltage drop calculating step is performed to drive the processing unit to set a speed proportional value and store the speed proportional value to a storage unit. The processing unit performs a voltage calculating procedure on the speed proportional value, the first load current and the second load current to calculate a limited voltage drop between the at least one power switch transistor and the first logic circuit. The standard supply current calculating step is performed to drive the processing unit to calculate a standard supply current of the at least one power switch transistor according to the limited voltage drop. The simulated supply current calculating step is performed to drive the processing unit to perform a current calculating procedure on the standard supply current, the limited voltage drop and the at least one line voltage to calculate a simulated supply current of the at least one power switch transistor. The size setting step is performed to drive the processing unit to compare the first load current with the simulated supply current to calculate a size parameter, and then set a size of the at least one power switch transistor according to the size parameter. 
     According to another aspect of the present disclosure, a size setting system for at least one power switch transistor includes a power supply voltage, the at least one power switch transistor, at least one power line, a first logic circuit, a second logic circuit, a storage unit and a processing unit. The at least one power switch transistor is connected to the power supply voltage. The at least one power line is connected to the at least one power switch transistor, and has at least one line voltage. The first logic circuit is connected to the at least one power line, and generates a first load current. The second logic circuit is connected to the power supply voltage, and generates a second load current. The storage unit is configured to access the at least one line voltage, a voltage calculating procedure and a current calculating procedure. The processing unit is signally connected to the storage unit and configured to implement a size setting method for the at least one power switch transistor including performing a first load current extracting step, a second load current extracting step, a limited voltage drop calculating step, a standard supply current calculating step, a simulated supply current calculating step and a size setting step. In particular, the first load current extracting step is performed to extract the first load current. The second load current extracting step is performed to extract the second load current. The limited voltage drop calculating step is performed to set a speed proportional value and store the speed proportional value to the storage unit, and then perform the voltage calculating procedure on the speed proportional value, the first load current and the second load current to calculate a limited voltage drop between the at least one power switch transistor and the first logic circuit. The standard supply current calculating step is performed to calculate a standard supply current of the at least one power switch transistor according to the limited voltage drop. The simulated supply current calculating step is performed to perform the current calculating procedure on the standard supply current, the limited voltage drop and the at least one line voltage to calculate a simulated supply current of the at least one power switch transistor. The size setting step is performed to compare the first load current with the simulated supply current to calculate a size parameter, and then set a size of the at least one power switch transistor according to the size parameter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
         FIG.  1    shows a flow chart of a size setting method for at least one power switch transistor according to a first embodiment of the present disclosure. 
         FIG.  2    shows a schematic circuit diagrams of a first logic circuit, two power switch transistors and two power lines in a first load current extracting step of the size setting method for the at least one power switch transistor of  FIG.  1   . 
         FIG.  3    shows a schematic circuit diagram of a second logic circuit in a second load current extracting step of the size setting method for the at least one power switch transistor of  FIG.  1   . 
         FIG.  4    shows a block diagram of a size setting system for at least one power switch transistor according to a second embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiment will be described with the drawings. For clarity, some practical details will be described below. However, it should be noted that the present disclosure should not be limited by the practical details, that is, in some embodiment, the practical details is unnecessary. In addition, for simplifying the drawings, some conventional structures and elements will be simply illustrated, and repeated elements may be represented by the same labels. 
     It will be understood that when an element (or device) is referred to as be “connected to” another element, it can be directly connected to the other element, or it can be indirectly connected to the other element, that is, intervening elements may be present. In contrast, when an element is referred to as be “directly connected to” another element, there are no intervening elements present. in addition, the terms first, second, third, etc. are used herein to describe various elements or components, these elements or components should not be limited by these terms. Consequently, a first element or component discussed below could be termed a second element or component. 
     Please refer to  FIG.  1   .  FIG.  1    shows a flow chart of a size setting method  100  for at least one power switch transistor according to a first embodiment of the present disclosure. As shown in  FIG.  1   , the size setting method  100  for the at least one power switch transistor includes performing a first load current extracting step S 02 , a second load current extracting step S 04 , a limited voltage drop calculating step S 06 , a standard supply current calculating step S 08 , a simulated supply current calculating step S 10  and a size setting step S 12 . 
     The first load current extracting step S 02  is performed to drive a processing unit to extract a first load current  110  of a first logic circuit. The first logic circuit is connected to a power supply voltage via the at least one power switch transistor and at least one power line to generate the first load current  110 . In addition, the at least one power line has at least one line voltage, which is stored in a storage unit. 
     The second load current extracting step S 04  is performed to drive the processing unit to extract a second load current  120  of a second logic circuit. The second logic circuit is connected to the power supply voltage to generate the second load current  120 . 
     The limited voltage drop calculating step S 06  is performed to drive the processing unit to set a speed proportional value  130  and store the speed proportional value  130  to a storage unit. The processing unit performs a voltage calculating procedure on the speed proportional value  130 , the first load current  110  and the second load current  120  to calculate a limited voltage drop  140  between the at least one power switch transistor and the first logic circuit. 
     The standard supply current calculating step S 08  is performed to drive the processing unit to calculate a standard supply current  150  of the at least one power switch transistor according to the limited voltage drop  140 . 
     The simulated supply current calculating step S 10  is performed to drive the processing unit to perform a current calculating procedure on the standard supply current  150 , the limited voltage drop  140  and the at least one line voltage to calculate a simulated supply current  160  of the at least one power switch transistor. 
     The size setting step S 12  is performed to drive the processing unit to compare the first load current  110  with the simulated supply current  160  to calculate a size parameter  170 , and then set a size of the at least one power switch transistor according to the size parameter  170 . 
     Therefore, the user an request the speed requirements of the pluralities of the first logic circuits corresponding to the different specifications to set the speed proportional value  130 , and calculate the size parameter  170  by using the size setting method  100  for the at least one power switch transistor of the present disclosure. The user can configure the power switch transistor having the appropriate size to the first logic circuit so as to minimize area loss and standby power consumption. The size setting method  100  for the at least one power switch transistor of the present disclosure is described in more detail with the drawings and the embodiments below. 
     Please refer to  FIGS.  1 ,  2  and  3   .  FIG.  2    shows a schematic circuit diagram of a first logic circuit LC 1 , two power switch transistors Q 1 , Q 2  and two power lines M 1 , M 2  in the first load current extracting step S 02  of the size setting method  100  for the at least one power switch transistor of  FIG.  1   .  FIG.  3    shows a schematic circuit diagram of a second logic circuit LC 2  in the second load current extracting step S 04  of the size setting method  100  for the at least one power switch transistor of  FIG.  1   . It should be noted that a structure of the first logic circuit LC 1  in the first embodiment is the same as the second logic circuit LC 2 , that is, the first logic circuit LC 1  and the second logic circuit LC 2  are the same logic circuit; in other words, the second logic circuit LC 2  in  FIG.  3    is an internal circuit diagram of the first logic circuit LC 1  in  FIG.  2   . 
     As shown in  FIG.  2   , the first load current extracting step S 02  can be performed to connect a power supply voltage VDD to a first power domain VMTHz 0  of the first logic circuit LC 1  via the power switch transistor Q 1  and the power line M 1 , so that a plurality of transistors in the first logic circuit LC 1  (i.e., corresponding to a plurality of transistors in the second logic circuit LC 2  in  FIG.  3   ) are operated in a saturation region and generate the first load current  110 . In addition, the first load current extracting step S 02  can also be performed to connect another power supply voltage VSS to a second power supply domain VMTLz 0  of the first logic circuit LC 1  via the power switch transistor Q 2  and the power line M 2 , so that the aforementioned transistors are operated in the saturation region and generate another first load current (not shown). In general, a power supply in a logic circuit can be divided into multiple independent blocks, which are called power domains. The first power domain VMTHz 0  of the present disclosure is a high-voltage power domain in the first logic circuit LC 1 ; on the contrary, the second power domain VMTLz 0  is a low-voltage power domain in the first logic circuit LC 1 . 
     Further, both of the power switch transistors Q 1 , Q 2  of the first embodiment can be a Multi-Threshold CMOS (MTCMOS). Specifically, the power switch transistor Q 1  is a PMOS transistor, and the power switch transistor Q 2  is an NMOS transistor. A gate terminal of the power switch transistor Q 1  is electrically connected to an inverted enable signal ENb, which is configured to control the opening and closing of the power switch transistor Q 1 . A source terminal of the power switch transistor Q 1  is electrically connected to the power supply voltage VDD. A terminal voltage between a drain terminal of the power switch transistor Q 1  and the power line M 1  is represented as VMTH. Similarly, a gate terminal of the power switch transistor Q 2  is electrically connected to an enable signal EN, which is configured to control the opening and closing of the power switch transistor Q 2 . A source terminal of the power switch transistor Q 2  is electrically connected to the power supply voltage VSS. A terminal voltage between a drain terminal of the power switch transistor Q 2  and the power line M 2  is represented as VMTL, and the power line M 1  and the power line M 2  are the same line having the same line voltage. 
     As shown in  FIG.  3   , the second logic circuit LC 2  is a 23-stage ring oscillator, which is composed of 23 sets of inverters connected in series. In the first embodiment, the second logic circuit LC 2  includes a NAND gate and 22 sets of inverters. A fan out of the second logic circuit LC 2  is 3, and each of the inverters in the second logic circuit LC 2  can include a plurality of transistors (not shown). In detail, the second load current extracting step S 04  can be performed to connect the power supply voltage VDD to a first power supply domain (i.e., a high-voltage power supply domain connected to each of the inverters) and a second power supply domain (i.e., a low-voltage power domain connected to each of the inverters) of the second logic circuit LC 2 , so that the transistors in the second logic circuit LC 2  are operated in a saturation region and generate the second load current  120 . 
     A response speed of the first logic circuit LC 1  connected to the power switch transistor Q 1  is lower than a response speed of the second logic circuit LC 2  not connected to any power switch. In response to determining that the first load current  110  is greater than a supply current Isupply flowing through the power switch transistor Q 1  (as shown in  FIG.  2   ), a charging time of the first logic circuit LC 1  increases. If the power supply range is farther (i.e., the power line M 1  is longer), a resistance value of the power line M 1  must be considered. In detail, the present disclosure wants to ensure that the response speed of the first logic circuit LC 1  can only be slightly lower than the response speed of the second logic circuit LC 2 , so the speed proportional value  130  can be set by the processing unit, and the voltage drop caused by the power line M 1  is limited via the speed proportional value  130 , so that the high response speed of the first logic circuit LC 1  connected to the power switch transistor Q 1  is maintained. 
     In the limited voltage drop calculating step S 06 , the voltage calculating procedure can include the speed proportional value  130 , the first load current  110 , the second load current  120 , the power supply voltage VDD, a threshold voltage of the power switch transistor Q 1  and a terminal voltage between the power line M 1  and the first logic circuit LC 1  (i.e., the voltage value supplied to the first power domain VMTHz 0 ). The speed proportional value  130  is represented as S, the first load current  110  is represented as I MTCOMS , the second load current  120  is represented as I non_MTCOMS , the power supply voltage VDD is represented as V DD , the threshold voltage of the power switch transistor Q 1  is represented as V th , the terminal voltage is represented as V QL , and the speed proportional value  130  conforms to an equation (1): 
     
       
         
           
             
               
                 
                   
                     1 
                     - 
                     
                       
                         I 
                         
                           non 
                           ⁢ 
                           _ 
                           ⁢ 
                           MTCOMS 
                         
                       
                       
                         I 
                         MTCOMS 
                       
                     
                   
                   = 
                   
                     
                       1 
                       - 
                       
                         
                           
                             ( 
                             
                               
                                 V 
                                 DD 
                               
                               - 
                               
                                 V 
                                 
                                   t 
                                   ⁢ 
                                   h 
                                 
                               
                             
                             ) 
                           
                           2 
                         
                         
                           
                             ( 
                             
                               
                                 V 
                                 
                                   Q 
                                   ⁢ 
                                   L 
                                 
                               
                               - 
                               
                                 V 
                                 th 
                               
                             
                             ) 
                           
                           2 
                         
                       
                     
                     ≤ 
                     
                       S 
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     In detail, since both of the transistors in the first logic circuit LC 1  and the transistors in the second logic circuit LC 2  are operated in the saturation region, both of the first load current  110  and the second load current  120  belong to a saturation region current. The first load current  110  conforms to an equation (2) according to the conventional saturation region equation, and the second load current  120  conforms to an equation (3) according to the conventional saturation region equation: 
         I   MTCOMS   =K (V QL −V th ) 2   (2);
 
         I   non_MTCOMS   =K (V DD −V th ) 2   (3).
 
     K is a process transconductance parameter, which cancels out in the equation (1). In addition, the terminal voltage between the power line M 1  and the first logic circuit LC 1  conforms to an equation (4): 
     
       
         
           
             
               
                 
                   { 
                   
                     
                       
                         
                           
                             
                               V 
                               DD 
                             
                             = 
                             
                               
                                 
                                   I 
                                   MTCOMS 
                                 
                                 * 
                                 
                                   R 
                                   
                                     M 
                                     ⁢ 
                                     1 
                                   
                                 
                               
                               + 
                               
                                 V 
                                 
                                   Q 
                                   ⁢ 
                                   L 
                                 
                               
                             
                           
                         
                       
                       
                         
                           
                             
                               V 
                               
                                 Q 
                                 ⁢ 
                                 L 
                               
                             
                             - 
                             
                               V 
                               DD 
                             
                             - 
                             
                               
                                 I 
                                 MTCOMS 
                               
                               * 
                               
                                 R 
                                 
                                   M 
                                   ⁢ 
                                   1 
                                 
                               
                             
                           
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     R M1  is the resistance value of the power line M 1 . Generally speaking, in response to determining that the loads (not shown) connected to a rear end of the first logic circuit LC 1  are the same, the first load current  110  of the first logic circuit LC 1  is inversely proportional to the charging times corresponding to the loads. The present disclosure defines a speed parameter corresponding to the first logic circuit LC 1  to be proportional to the charging time, so the aforementioned speed parameter is inversely proportional to the first load current  110 . Then, the processing unit limits a difference generated from the terminal voltage between the power line M 1  and the first logic circuit LC 1  and the power supply voltage VDD to be the limited voltage drop  140  according to the speed proportional value  130  in the equation (1). 
     For example, the power supply voltage VDD of the first embodiment is equal to 1.1 volts (V DD =1.1 V), the threshold voltage of the power switch transistor Q 1  is equal to 0.25 volts (V th =0.25 V), and the speed proportional value  130  is set to 5% (S=0.05). The processing unit substitutes the above parameters into the equation (1), the equation (1) can be deduced that the terminal voltage between the power line M 1  and the first logic circuit LC 1  can only be smaller than the power supply voltage VDD by 21 mV, and the 21 mV is the limited voltage drop  140 . In other embodiments, the user can request the speed requirements of the pluralities of first logic circuits corresponding to the different specifications to set the speed proportional value, and the present disclosure is not limited thereto. 
     Moreover, the standard supply current calculating step  308  of the present disclosure can include a presetting sub-step S 081  and an estimating sub-step S 082 . The presetting sub-step S 081  is performed to drive the processing unit to preset the limited voltage drop  140  as a drain-source voltage of the power switch transistor Q 1 , so that the power switch transistor Q 1  is operated in a linear region. The estimating sub-step S 082  is performed to drive the processing unit to estimate the standard supply current  150  according to the drain-source voltage of the power switch transistor Q 1 . Furthermore, the supply current Isupply of the power switch transistor Q 1  is in the linear region, because the power supply voltage VDD minus the terminal voltage VMTH between the source terminal of the power switch transistor Q 1  and the power line M 1  is less than the power supply voltage VDD minus the threshold voltage of the power switch transistor Q 1 . If the length of the power line M 1  is very short and the resistance value of the power line M 1  is ignored, the processing unit sets the limited voltage drop  140  (i.e., 21 mV) as the drain-source voltage of the power switch transistor Q 1  and substitutes the limited voltage drop  140  into the conventional linear region equation, and the standard supply current  150  conforms to an equation (5): 
     
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     
                       - 
                       
                         μ 
                         p 
                       
                     
                     ⁢ 
                     
                       C 
                       
                         o 
                         ⁢ 
                         x 
                       
                     
                     ⁢ 
                     
                       W 
                       L 
                     
                     ⁢ 
                     
                       
                         ( 
                         
                           
                             
                               ( 
                               
                                 
                                   V 
                                   GS 
                                 
                                 - 
                                 
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                                     t 
                                     ⁢ 
                                     h 
                                   
                                 
                               
                               ) 
                             
                             ⁢ 
                             
                               V 
                               
                                 D 
                                 ⁢ 
                                 S 
                               
                             
                           
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                               DS 
                               2 
                             
                             2 
                           
                         
                         ) 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     I D  is the standard supply current  150 , V DS  is the limited voltage drop  140  (V DS =21 my), V GS  is a gate-source voltage of the power switch transistor Q 1  (V GS =VDD−VSS=1.1−0=1.1 V), μ p  is a carrier mobility in the linear region, W is a channel width of the power switch transistor Q 1  (W=3.6 μm), L is a channel length of the power switch transistor Q 1  (L=0.08 μm), C ox  is an unit capacity of a gate oxide layer, V th  is the threshold voltage of the power switch transistor Q 1  (V th =0.25 V). Both of the carrier mobility μ p  in the linear region and the unit capacity C ox  of the gate oxide layer are parameters determined by the process of the transistor. The processing unit can calculate a result that the standard supply current  150  is equal to 20 microamps (I D =20 μA) by substituting the above parameters into the equation (5). The standard supply current  150  represents that when a drain current of the power switch transistor Q 1  is 20 microamps, the response speed of the first logic circuit LC 1  is only less than 5% relative to the response speed of the second logic circuit LC 2 . 
     On the other hand, if the power supply range between the power switch transistor Q 1  and the first logic circuit LC 1  is far, the resistance value of the power line M 1  needs to be considered, and a voltage across the power line M 1  needs to be calculated. In the simulated supply current calculating step S 10 , the processing unit performs the current calculating procedure on the standard supply current  150 , the limited voltage drop  140  and the line voltage across the power line M 1  to calculate the simulated supply current  160  of the power switch transistor Q 1 . 
     Furthermore, the current calculating procedure can include the simulated supply current  160 , the standard supply current  150 , the limited voltage drop  140  and the line voltage across the power line M 1 . The simulated supply current  160  is represented as I supplyR_unit , the standard supply current  150  is represented as I supply_unit , the limited voltage drop  140  is represented as V drop , the line voltage across the power line M 1  is represented as V line , and the simulated supply current  160  conforms to an equation (6): 
     
       
         
           
             
               
                 
                   
                     I 
                     
                       supplyR 
                       ⁢ 
                       _ 
                       ⁢ 
                       unit 
                     
                   
                   = 
                   
                     
                       I 
                       
                         supply 
                         ⁢ 
                         _ 
                         ⁢ 
                         unit 
                       
                     
                     * 
                     
                       
                         [ 
                         
                           
                             ( 
                             
                               
                                 V 
                                 drop 
                               
                               - 
                               
                                 V 
                                 line 
                               
                             
                             ) 
                           
                           
                             V 
                             drop 
                           
                         
                         ] 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     Wherein V line =I MTCOMS *R M1 , I MTCOMS =0.5 mA, R M1  is the resistance value of the power line M 1 , R M1 =20 ohm (a line length of the power line M 1  is 100 μm), V drop =21 mV, and I supply_unit =20 μA. The processing unit can calculate the simulated supply current  160  (I supplyR_unit =20*0.52381) by substituting the above parameters into the equation (6). 
     Then, the size setting step S 12  is performed. The processing unit compares the first load current  110  with the simulated supply current  160  to calculate the size parameter  170 , and then sets the size of the power switch transistor Q 1  according to the size parameter  170 . In detail, the processing unit divides the first load current  110  by the simulated supply current  160  to generate the size parameter  170 , and then multiplies the size parameter  170  by the channel length and the channel width of the power switch transistor Q 1  to calculate the size of the power switch transistor Q 1 , which conforms to two following equations (7) and (8): 
     
       
         
           
             
               
                 
                   
                     Multi 
                     = 
                     
                       
                         I 
                         MTOCMS 
                       
                       
                         I 
                         
                           supplyR 
                           ⁢ 
                           _ 
                           ⁢ 
                           unit 
                         
                       
                     
                   
                   ; 
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
       
         
           
             
               
                 
                   { 
                   
                     
                       
                         
                           
                             
                               S 
                               L 
                             
                             = 
                             
                               Multi 
                               * 
                               L 
                             
                           
                         
                       
                       
                         
                           
                             
                               S 
                               W 
                             
                             = 
                             
                               Multi 
                               * 
                               W 
                             
                           
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     Multi is the size parameter  170 , I MTCOMS  is the first load current  110 , I supplyR_unit  is the simulated supply current  160 , a length dimension of the power switch transistor Q 1  is represented as S L , and a width dimension of the power switching transistor Q 1  is represented as S W , L is the channel length of the power switch transistor Q 1 , and W is the channel width of the power switch transistor Q 1 . 
     Table 1 lists the size parameters  170  of the present disclosure in different specifications, which correspond to the line lengths and the resistance values of the power lines M 1  (i.e., different power supply ranges) and the first load currents  110  of the first logic circuits LC 1  in different specifications. It should be noted that Table 1 is mainly for the case where the speed proportional value  130  is 5%, and the present disclosure is not limited thereto. 
     
       
         
           
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 the size parameters 170 (Multi) 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
            
               
                 I MTCOMS   
                 69 
                 140 
                 228 
                 283 
                 422 
                 562 
                 840 
               
               
                 (μA) 
               
               
                 1 μm 
                 4 
                 7 
                 12 
                 15 
                 22 
                 30 
                 44 
               
               
                 (0.2 ohm) 
               
               
                 10 μm 
                 4 
                 7 
                 13 
                 15 
                 23 
                 33 
                 48 
               
               
                 (2 ohm) 
               
               
                 50 μm 
                 4 
                 8 
                 13 
                 17 
                 28 
                 42 
                 74 
               
               
                 (10 ohm) 
               
               
                 100 μm 
                 4 
                 9 
                 15 
                 20 
                 36 
               
               
                 (20 ohm) 
               
               
                   
               
            
           
         
       
     
     In Table 1, in response to determining that the length of the power line M 1  is 10 μm and the first load current  110  is 840 μA, the user can configure the size parameter  170  (Multi=48) to set the size of the power switch transistor Q 1 , and so on. Therefore, the user can set the size of the power switch transistor Q 1  to meet the speed proportional value  130  by using the size setting method  100  for the at least one power switch transistor of the present disclosure, and ensure that various logic circuits still maintain high-speed transmission. 
     Please refer to  FIGS.  1  to  4   .  FIG.  4    shows a block diagram of a size setting system  200  for at least one power switch transistor according to a second embodiment of the present disclosure. As shown in  FIG.  4   , the size setting system  200  for at least one power switch transistor includes a power supply voltage  210 , a power switch transistor  220 , a power line  230 , a first logic circuit  240 , a second logic circuit  250 , a storage unit  260  and a processing unit  270 . The power switch transistor  220  is electrically connected to the power supply voltage  210 . The power line  230  is electrically connected to the power switch transistor  220 , and has a line voltage  261 . The first logic circuit  240  is electrically connected to the power line  230 , and generates a first load current  110 . The second logic circuit  250  is electrically connected to the power supply voltage  210 , and generates a second load current  120 . The structure of the first logic circuit  240  is the same as the second logic circuit  250 . The storage unit  260  is configured to access the line voltage  261 , a voltage calculating procedure  262 , a current calculating procedure  263  and a transistor parameter  264  of the power switch transistor  220 . The processing unit  270  is signally connected to the storage unit  260 . In addition, the processing unit  270  extracts a peak current of the first load current  110  and a peak current of the second load current  120 , and is configured to implement the size setting method  100  for the at least one power switch transistor. The processing unit  270  can be a Digital Signal Processor (DSP), a Micro Processing Unit (MPU), a Central Processing Unit (CPU) or other electronic processors, but the present disclosure is not limited thereto. 
     Therefore, the size setting system  200  for at least one power switch transistor of the present disclosure utilizes the processing unit  270  to calculate the limited voltage drop  140  according to the first load current  110  and the second load current  120 , and set the size of the power switch transistor  220  that can satisfy the speed proportional value  130 . The size setting system  200  for at least one power switch transistor of the present can ensure that the first logic circuit  240  connected to the power switch transistor  220  still maintains high-speed transmission. 
     In summary, the present disclosure has the following advantages. First, it is favorable to avoid configuring oversized power switch transistors in the logic circuits, thereby reducing circuit costs. Second, it is favorable to ensure that the logic circuits with the power switch transistors still have high-speed transmission. Third, it can reduce the user&#39;s layout time for the size configuration of the power switch transistor in the product development, thereby speeding up the development process. 
     Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.