Patent Publication Number: US-6906566-B2

Title: Dual-phase delay-locked loop circuit and method

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is a divisional of pending U.S. patent application Ser. No. 09/974,386, filed Oct. 9, 2001. 

   TECHNICAL FIELD 
   The present invention relates generally to integrated circuits, and more specifically to synchronizing an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal. 
   BACKGROUND OF THE INVENTION 
   In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits. 
   Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches. 
   To synchronize external and internal clock signals in modem synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another.  FIG. 1  is a functional block diagram illustrating a conventional delay-locked loop  100  including a variable delay line  102  that receives a clock buffer signal CLKBUF and generates a delayed clock signal CLKDEL in response to the clock buffer signal. The variable delay line  102  controls a variable delay VD of the CLKDEL signal relative to the CLKBUF signal in response to a delay adjustment signal DADJ. A feedback delay line  104  generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D 1 +D 2  relative to the CLKDEL signal. The D 1  component of the model delay D 1 +D 2  corresponds to a delay introduced by an input buffer  106  that generates the CLKBUF signal in response to an external clock signal CLK, while the D 2  component of the model delay corresponds to a delay introduced by an output buffer  108  that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer  106  and output buffer  108  are illustrated as single components, each represents all components and the associated delay between the input and output of the delay-locked loop  100 . The input buffer  106  thus represents the delay D 1  of all components between an input that receives the CLK signal and the input to the variable delay line  102 , and the output buffer  108  represents the delay D 2  of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed. 
   The delay-locked loop  100  further includes a phase detector  110  that receives the CLKFB and CLKBUF signals and generates a delay control signal DCONT having a value indicating the phase difference between the CLKBUF and CLKFB signals. One implementation of a phase detector is described in U.S. Pat. No. 5,946,244 to Manning (Manning), which is assigned to the assignee of the present patent application and which is incorporated herein by reference. A delay controller  112  generates the DADJ signal in response to the DCONT signal from the phase detector  110 , and applies the DADJ signal to the variable delay line  102  to adjust the variable delay VD. The phase detector  110  and delay controller  112  operate in combination to adjust the variable delay VD of the variable delay line  102  as a function of the detected phase between the CLKBUF and CLKFB signals. 
   In operation, the phase detector  110  detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller  112  operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted the phase of the CLKFB signal from the feedback delay line  104  is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop  100  has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be “locked.” When the delay-locked loop  100  is locked, the CLK and CLKSYNC signals are synchronized. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop  100  is locked), the variable delay VD has a value of NTCK−(D 1 +D 2 ) as indicated in  FIG. 1 , where N is an integer and TCK is the period of the CLK signal. When VD equals NTCK−(D 1 +D 2 ), the total delay of the CLK signal through the input buffer  106 , variable delay line  102 , and output buffer  108  is D 1 +NTCK−(D 1 +D 2 )+D 2 , which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKSYNC signal corresponds to the internal clock signal. 
     FIG. 2  is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop  100  of FIG.  1 . In response to a rising-edge of the CLK signal at a time T 0 , the CLKBUF signal goes high the delay D 1  later at a time T 1 . Initially, the variable delay VD as a value VD 1 , causing the CLKDEL signal to go high at a time T 3  and the CLKSYNC signal to go high at a time T 4 . At this point, note that the positive-edge of the CLKSYNC signal at the time T 4  is not synchronized with the CLK signal, which transitions high at a time T 5 . In response to the rising-edge of the CLKDEL signal at the time T 3 , the CLKFB goes high at a time T 6 , which occurs before a positive-edge of the CLKBUF signal occurring at a time T 7 . Thus, the positive-edge of the CLKFB signal occurs at the time T 6  while the positive-edge of the CLKBUF occurs at the time T 7 , indicating there is a phase shift between the two signals. The phase detector  110  ( FIG. 1 ) detects this phase difference, and generates the DCONT signal just after the time T 7  at a time T 8  which, in turn, causes the delay controller  112  ( FIG. 1 ) to generate the DADJ signal to adjust the value of the variable delay VD to a new value VD 2 . 
   In response to the new variable delay VD 2 , the next rising-edge of the CLKDEL signal occurs at a time T 9 . The CLKSYNC signal transitions high the delay D 2  later at a time T 10  and in synchronism with a rising-edge of the CLK signal. At this point, the delay-locked loop  100  is locked. In response to the positive-edge transition of the CLKDEL signal at the time T 9 , the CLKFB signal transitions high at a time T 11  in synchronism with the CLKBUF signal. Once again, the phase detector  110  ( FIG. 1 ) detects the phase difference between the CLKBUF and CLKFB signals, which in this case is approximately zero, and generates the DCONT signal just after the time T 11  in response to the detected phase difference. In this situation, the generated DCONT signal would not cause the variable delay VD 2  to be adjusted since the delay-locked loop  100  is locked. Moreover, although the relative phases of the CLKBUF and CLKFB signals is detected in response to each rising-edge of these signals, the variable delay VD may not be adjusted immediately even where such a phase difference is detected. For example, the variable delay VD may be adjusted only when a phase difference between the CLKFB and CLKBUF signals exists for a predetermined time or exceeds a predetermined magnitude. In this way, the phase detector  110  and delay controller  112  can provide a sort of “filtering” of jitter or variations in the CLK signal, as will be understood in the art. 
   In the delay-locked loop  100 , each cycle of the CLK signal the phase detector  110  compares rising-edges of the CLKBUF and CLKFB signals and generates the appropriate DCONT signal to incrementally adjust the variable delay VD until the delay-locked loop  100  is locked. The phase detector  110  could also compare falling-edges of the CLKBUF and CLKFB signals, as in the previously mentioned Manning patent. In this way, the delay-locked loop  100  incrementally adjusts the variable delay VD once each cycle of the CLK signal. Although the example of  FIG. 2  illustrates the delay-locked loop  100  as locking and therefore synchronizing the CLK and CLKSYNC signals after only two cycles of the CLK signal, the delay-locked loop typically takes as many as 200 cycles of the CLK signal to lock. Before the delay-locked loop  100  is locked, the CLKSYNC signal cannot be used to latch signals being applied to the synchronous memory device containing the delay-locked loop. As a result, the time it takes to lock the delay-locked loop  100  may slow the operation of the associated synchronous memory device. For example, in a conventional double data rate (DDR) SDRAM, the delay-locked loop is automatically disabled when the SDRAM enters a self-refresh mode of operation. Upon exiting the self-refresh mode, 200 cycles of the applied CLK signal must then occur before read or write data transfer commands can be applied to the SDRAM. 
   In the delay-locked loop  100 , the variable delay line  102  typically is formed from a number of serially-connected individual delay stages, with individual delay stages being added or removed to adjust the variable delay VD, as will be understood by those skilled in the art. For example, a plurality of serially-connected inverters could be used to form the variable delay line  102 , with the output from different inverters being selected in response to the DADJ to control the variable delay VD. A large number of stages in the variable delay line  102  is desirable with each stage having an incremental delay to provide better resolution in controlling the value of the variable delay VD. In addition, the variable delay line  102  must be able to provide the maximum variable delay VD corresponding to the CLK signal having the lowest frequency in the frequency range over which the delay-locked loop is designed to operate. This is true because the variable delay line  102  must provide a variable delay VD of NTCK−(D 1 +D 2 ), which will have its largest value when the period of the CLK signal is greatest, which occurs at the lowest frequency of the CLK signal. The desired fine resolution and maximum variable delay VD that the variable delay line  102  must provide can result in the delay line consisting of a large number of individual delay stages that consume a relatively large amount of space on a semiconductor substrate in which the delay-locked loop  100  and other components of the synchronous memory device are formed. Moreover, such a large number of individual delay stages can result in significant power consumption by the delay-locked loop  100 , which may be undesirable particularly in applications where synchronous memory device is contained in a portable battery-powered device. 
   There is a need for a delay-locked loop that occupies less space on a semiconductor substrate, consumes less power, and more quickly locks on an applied clock signal. 
   SUMMARY OF THE INVENTION 
   According to one aspect of the present invention, a delay-locked loop, includes a clock multiplier that generates a multiplied clock signal responsive to an input clock signal. The multiplied clock signal has a frequency that is a multiple of a frequency of the input clock signal. A variable delay circuit is coupled to the clock multiplier and generates a delayed clock signal responsive to the multiplied clock signal. The delayed clock signal has a delay relative to the multiplied clock signal and the variable delay circuit controls the value of the delay responsive to a delay control signal. A comparison circuit is coupled to the clock multiplier and to the variable delay circuit to generate the delay control signal in response to the relative phases of the delayed clock signal and the multiplied clock signal. 
   According to another aspect of the present invention, a delay-locked loop includes a variable delay circuit that receives an input clock signal and generates a delayed clock signal responsive to the input clock signal. The delayed clock signal has a delay relative to the input clock signal and the variable delay circuit controls the value of the delay responsive to a delay control signal. A comparison circuit is coupled to the variable delay circuit and generates the delay control signal in response to the relative phases of the rising-edge transitions of the delayed and input clock signals and in response to the relative phases of the falling-edge transitions of the delayed and input clock signals. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a functional block diagram of a conventional delay-locked loop. 
       FIG. 2  is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop of FIG.  1 . 
       FIG. 3  is a functional block diagram of a delay-locked loop according to one embodiment of the present invention. 
       FIG. 4  is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop of FIG.  3 . 
       FIG. 5  is a functional block diagram illustrating a delay-locked loop according to another embodiment of the present invention. 
       FIG. 6  is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop of FIG.  5 . 
       FIG. 7  is a diagram illustrating one embodiment of the clock multiplier of FIG.  3  and various signals generated during operation of the clock multiplier. 
       FIG. 8  is a functional block diagram illustrating a synchronous memory device including the delay-locked loop of FIG.  3  and/or the delay-locked loop of FIG.  5 . 
       FIG. 9  is a functional block diagram illustrating a computer system including a synchronous memory device of FIG.  8 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3  is a functional block diagram of a delay-locked loop  300  including a clock multiplier  302  that multiplies a frequency of an applied external clock signal CLK, allowing a variable delay VD of a delayed clock signal CLKDEL to be adjusted multiple times during each cycle of the applied clock signal and thereby enabling the applied clock signal to be more quickly locked, as will be explained in more detail below. In addition to locking more quickly on the CLK signal, the delay-locked loop  300  also enables a smaller variable delay line  304  to be utilized over a given operating frequency range due to the increased frequency of the signal being locked, as will also be explained below in more detail. In the following description, certain details are set forth to provide a sufficient understanding of the invention. It will be clear to one skilled in the art, however, that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail or omitted entirely in order to avoid unnecessarily obscuring the invention. 
   The delay-locked loop  300  includes the variable delay line  304 , a feedback delay line  306 , a phase detector  308 , and a delay controller  310 , all of which operate individually and in combination as previously described for the corresponding components in the conventional delay-locked loop  100  of FIG.  1 . Thus, for the sake of brevity, the operation of these components will not again be described in detail. In the delay-locked loop  300 , the clock multiplier  302  generates a multiplied clock signal MCLK in response to the CLK signal. The MCLK signal has a frequency FMCLK equal to a frequency FCLK of the CLK signal times 2^N, where N is an integer (i.e., FMCLK=FCLK×2^N). In the embodiment of  FIG. 3 , N=1 so that the frequency FMCLK of the MCLK signal is twice the frequency FCLK of the CLK signal. 
   An input buffer  310  develops a clock buffer signal CLKBUF in response to the MCLK signal. The input buffer  310  introduces an input buffer delay DIB, causing the CLKBUF signal to be delayed by the input buffer delay relative to the MCLK signal. The clock multiplier  302  also introduces a delay to the MCLK signal relative to the CLK signal. The delay introduced by the clock multiplier  302  plus the input buffer delay DIB introduced by the input buffer  310  together form the model delay component D 1  in the feedback delay line  306 . Although the clock multiplier  302  is shown connected before the input buffer  310  in the embodiment of  FIG. 3 , one skilled in the art will realize the input buffer and clock multiplier would typically be reversed, with the input buffer receiving the CLK signal and supplying the CLKBUF signal to the clock multiplier which, in turn, applies the MCLK signal to the variable delay line  304 . 
   In the delay-locked loop  300 , a clock divider  312  receives the CLKDEL signal and generates a divided clock signal DVCLK having the frequency FCLK of the CLKDEL signal. Thus, in the embodiment of  FIG. 3 , the clock divider  312  divides the multiplied frequency FMCLK of the MCLK signal by two to generate the DVCLK signal having the same frequency as the CLK. The clock divider  312  could also divide the frequency of the CLKDEL signal by other factors to generate the DVCLK signal having a frequency that is equal to the FMCLK signal divided by 2^N. A phase detection and correction circuit  314  receives the DVCLK and CLK signals, detects whether these two signals are approximately 180 degrees out of phase, and generates a corrected divided clock signal CDVCLK in response to the detected phase. More specifically, when the phase detection and correction circuit  314  determines the DVCLK and CLK signals are not approximately 180 degrees out of phase, the circuit outputs the DVCLK as the CDVCLK signal. In contrast, when the phase detection and correction circuit  314  detects the phase between the DVCLK and CLK signals is approximately 180 degrees, the phase detection and correction circuit inverts the DVCLK signal to generate the CDVCLK signal. The phase detection and correction circuit  314  prevents the delay-locked loop  300  from generating an output signal that is 180 degrees out of phase with the CLK signal, which can occur when the total delay introduced by the delay-locked loop equals one-half the period TCK of the CLK signal, as will be appreciated by those skilled in the art. 
   An output buffer  316  generates a synchronized clock signal CLKSYNC signal in response to the CDVCLK signal, the CLKSYNC being synchronized with the CLK signal. The output buffer  316  introduces an output buffer delay DOB, causing the CLKSYNC signal to be delayed by this amount relative to the CDVCLK signal. The output buffer delay DOB, along with delays introduced by the clock divider  312  and phase detection and correction circuit  314 , form the D 2  component of the model delay D 1 +D 2  generated by the feedback delay line  306 . As illustrated by a dotted line in  FIG. 3 , the output buffer  316  may correspond to a data driver that receives a data signal DQX and outputs the data signal in response to being clocked by the CDVCLK signal, as will be appreciated by those skilled in the art. One skilled in the art will understand various circuits that may be utilized to form the components  302 - 316  of the delay-locked loop  300 . 
   The operation of the delay-locked loop  300  will now be briefly described with reference to the signal timing diagram of  FIG. 4  that illustrates various signals generated in the delay-locked loop during operation. The detailed operation of the delay-locked locked loop  300  is similar to that previously described for the delay-locked loop  100  of  FIG. 1 , and thus, for the sake of brevity, a detailed description will not again be provided. In the delay-locked loop  300 , the MCLK, CLKBUF, CLKDEL, and CLKFB signals are all twice the frequency of the CLK signal. Note that each rising-edge and falling-edge transition of the CLK signal generates a corresponding rising-edge of the MCLK signal, as shown at times T 1 , T 2  and at times T 3 , T 4 , and that each rising-edge of the MCLK signal generates a corresponding rising-edge of the CLKBUF signal, as shown at times T 5 , T 6 . As previously described, the phase detector  308  ( FIG. 3 ) compares each rising-edge of the CLKBUF signal to a corresponding rising-edge of the CLKFB signal, as illustrated at times T 7 , T 8 , and T 9 . Because the frequency of the CLKBUF and CLKFB signals is twice the frequency of the CLK signal, these comparisons occur twice during each period of the CLK signal. For example, for the period TCK of the CLK signal extending from a time T 10  to a time T 11 , the phase detector  308  asserts the delay control signal DCONT signal twice at the times T 7  and the T 8 . 
   The delay-locked loop  300  adjusts the delay of the CLKDEL signal in response to both rising- and falling-edges of the CLK signal, enabling the delay-locked to more quickly lock the CLK and CLKSYNC signals. This is true because the delay-locked loop  300  adjusts the phase of CLKDEL signal more frequently (twice per period TCK of the CLK signal) to thereby lock the CLK and CLKSYNC signals. Moreover, since the frequency of the CLKBUF, CLKDEL, and CLKFB signals is twice the frequency FCLK of the CLK signal, the variable delay line  304  ( FIG. 3 ) may be smaller than a conventional variable delay line. The maximum variable delay VD the variable delay line  304  must provide is given by N×TCK−(D 1 +D 2 ) for the maximum period TCK of the CLK signal to be locked, and in the delay-locked loop  300  the maximum period TCK is one-half the maximum period of the corresponding CLK signal due to the frequency of the CLKBUF, CLKDEL, and CLKFB signals being doubled. 
     FIG. 5  is a functional block diagram of a delay-locked loop  500  that adjusts a delay of a synchronized clock signal CLKSYNC relative to an applied clock signal CLK in response to both rising- and falling-edges of the applied clock signal according to another embodiment of the present invention. The delay-locked loop  500  includes a variable delay line  502 , a feedback delay line  504 , an input buffer  506 , and an output buffer  508 , all of which operate as previously described for the corresponding components in the delay-locked loop  300  of  FIG. 3 , and thus, for the sake of brevity, the operation of these components will not again be described in detail. The delay-locked loop  500  further includes a rising-edge phase detector  510  that receives the CLKFB and CLKBUF signals and generates a rising-edge delay control signal RDCONT having a value indicating the phase difference between rising-edges of the CLKBUF and CLKFB signals. A falling-edge phase detector  512  receives the CLKFB and CLKBUF signals and generates a falling-edge delay control signal FDCONT having a value indicating the phase difference between falling-edges of the CLKFB and CLKBUF signals. A delay controller  514  generates a delay adjustment signal DADJ in response to the RDCONT and FDCONT signals from the phase detectors  510 ,  512 , and applies the DADJ signal to the variable delay line  102  to adjust the variable delay VD. The phase detectors  510 ,  512  and delay controller  514  operate in combination to adjust the variable delay VD of the variable delay line  502  as a function of the detected phase between rising-edges and falling-edges of the CLKBUF and CLKFB signals. 
   In operation, the phase detector  510  detects the phase difference between rising-edges of the CLKBUF and CLKFB signals and applies the corresponding RDCONT signal to the delay controller  514  which, in turn, generates the DADJ signal to adjust the variable delay VD of the CLKDEL signal. The phase detector  512  operates in the same way to detect the phase difference between falling-edges of the CLKBUF and CLKFB signals and applied the corresponding FDCONT signal to the delay controller  514  which, in turn, generates the DADJ signal to adjust the variable delay VD of the CLKDEL signal. The phase detectors  510 ,  512  and delay controller  514  operate in combination to adjust the delay of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. 
   The operation of the delay-locked loop  500  will now be briefly described with reference to the signal timing diagram of  FIG. 6 , which illustrates various signals generated in the delay-locked loop during operation. The detailed operation of the delay-locked loop  500  is similar to that previously described for the delay-locked loop  300  of  FIG. 3 , and thus, for the sake of brevity, a detailed description will not again be provided. In the delay-locked loop  500 , the rising-edge phase detector  510  compares rising-edges of the CLKFB and CLKBUF signals at times T 1  and T 2 , and generates the RDCONT signal at just after the time T 2  to adjust the variable delay VD of the CLKDEL signal in response to the detected phase difference. Similarly, at times T 3  and T 4 , the falling-edge phase detector  512  compares falling-edges of the CLKFB and CLKBUF signals, and generates the FDCONT signal at just after the time T 4  to adjust the variable delay VD of the CLKDEL signal in response to the detected phase difference. Thus, the delay-locked loop  500  adjusts the variable delay VD of the variable delay line  502  ( FIG. 5 ) twice during each period TCK of the CLK signal, once in response to the rising-edge of the CLK signal and once in response to the falling-edge of the CLK signal. In this way, the delay-locked loop  500  more quickly synchronizes the CLK and CLKSYNC signals, reducing the number of cycles of the CLK signal required for the delay-locked loop to lock. 
     FIG. 7  is a diagram illustrating one embodiment of the clock multiplier  302  of FIG.  3  and various signals generated during operation of the clock multiplier. An XOR gate  700  receives the CLK signal on a first input, and a delay circuit  702  receives the CLK signal and applies a delayed signal DO to a second input of the XOR gate in response to the CLK signal. As the timing diagram of  FIG. 7  illustrates, the delay circuit  702  generates the delayed signal DO having a delay TD relative to the either a rising- or falling-edge of the CLK signal. In operation, when the CLK transitions high or low, the XOR gate  700  receives the high or low CLK signal on one input and the complement of the CLK signal on the other input for the delay TD. In response to these signals, the XOR gate  700  drives the MCLK signal high for the delay TD, at which point both inputs of the XOR gate  700  receive either high or low signals, causing the XOR gate to drive the MCLK signal low. 
     FIG. 8  is a functional block diagram of a memory device  800  including the delay-locked loop  300  of FIG.  3  and/or the delay-locked loop  500  of FIG.  5 . The memory device  800  in  FIG. 8  is a double-data rate (DDR) synchronous dynamic random access memory (“SDRAM”), although the principles described herein are applicable to any memory device that may include a delay-locked loop for synchronizing internal and external signals, such as conventional synchronous DRAMs (SDRAMs), as well as packetized memory devices like SLDRAMs and RDRAMs, and are equally applicable to any integrated circuit that must synchronize internal and external clocking signals. 
   The memory device  800  includes an address register  802  that receives row, column, and bank addresses over an address bus ADDR, with a memory controller (not shown) typically supplying the addresses. The address register  802  receives a row address and a bank address that are applied to a row address multiplexer  804  and bank control logic circuit  806 , respectively. The row address multiplexer  804  applies either the row address received from the address register  802  or a refresh row address from a refresh counter  808  to a plurality of row address latch and decoders  810 A-D. The bank control logic  806  activates the row address latch and decoder  810 A-D corresponding to either the bank address received from the address register  802  or a refresh bank address from the refresh counter  808 , and the activated row address latch and decoder latches and decodes the received row address. In response to the decoded row address, the activated row address latch and decoder  810 A-D applies various signals to a corresponding memory bank  812 A-D to thereby activate a row of memory cells corresponding to the decoded row address. Each memory bank  812 A-D includes a memory-cell array having a plurality of memory cells arranged in rows and columns, and the data stored in the memory cells in the activated row is stored in sense amplifiers in the corresponding memory bank. The row address multiplexer  804  applies the refresh row address from the refresh counter  808  to the decoders  810 A-D and the bank control logic circuit  806  uses the refresh bank address from the refresh counter when the memory device  800  operates in an auto-refresh or self-refresh mode of operation in response to an auto- or self-refresh command being applied to the memory device  800 , as will be appreciated by those skilled in the art. 
   A column address is applied on the ADDR bus after the row and bank addresses, and the address register  802  applies the column address to a column address counter and latch  814  which, in turn, latches the column address and applies the latched column address to a plurality of column decoders  816 A-D. The bank control logic  806  activates the column decoder  816 A-D corresponding to the received bank address, and the activated column decoder decodes the applied column address. Depending on the operating mode of the memory device  800 , the column address counter and latch  814  either directly applies the latched column address to the decoders  816 A-D, or applies a sequence of column addresses to the decoders starting at the column address provided by the address register  802 . In response to the column address from the counter and latch  814 , the activated column decoder  816 A-D applies decode and control signals to an I/O gating and data masking circuit  818  which, in turn, accesses memory cells corresponding to the decoded column address in the activated row of memory cells in the memory bank  812 A-D being accessed. 
   During data read operations, data being read from the addressed memory cells is coupled through the I/O gating and data masking circuit  818  to a read latch  820 . The I/O gating and data masking circuit  818  supplies N bits of data to the read latch  820 , which then applies two N/2 bit words to a multiplexer  822 . In the embodiment of  FIG. 3 , the circuit  818  provides 64 bits to the read latch  820  which, in turn, provides two 32 bits words to the multiplexer  822 . A data driver  824  sequentially receives the N/2 bit words from the multiplexer  822  and also receives a data strobe signal DQS from a strobe signal generator  826  and a delayed clock signal CLKDEL from the delay-locked loop  300 / 500 . The DQS signal is used by an external circuit such as a memory controller (not shown) in latching data from the memory device  800  during read operations. In response to the delayed clock signal CLKDEL, the data driver  824  sequentially outputs the received N/2 bits words as a corresponding data word DQ, each data word being output in synchronism with a rising or falling edge of a CLK signal that is applied to clock the memory device  800 . The data driver  824  also outputs the data strobe signal DQS having rising and falling edges in synchronism with rising and falling edges of the CLK signal, respectively. Each data word DQ and the data strobe signal DQS collectively define a data bus DATA. As will be appreciated by those skilled in the art, the CLKDEL signal from the DLL is a delayed version of the CLK signal, and the delay-locked loop  300 / 500  adjusts the delay of the CLKDEL signal relative to the CLK signal to ensure that the DQS signal and the DQ words are placed on the DATA bus in synchronism with the CLK signal, as previously described with reference to  FIGS. 3-6 . The DATA bus also includes masking signals DM 0 -M, which will be described in more detail below with reference to data write operations. 
   During data write operations, an external circuit such as a memory controller (not shown) applies N/2 bit data words DQ, the strobe signal DQS, and corresponding data masking signals DM 0 -X on the data bus DATA. A data receiver  828  receives each DQ word and the associated DM 0 -X signals, and applies these signals to input registers  830  that are clocked by the DQS signal. In response to a rising edge of the DQS signal, the input registers  830  latch a first N/2 bit DQ word and the associated DM 0 -X signals, and in response to a falling edge of the DQS signal the input registers latch the second N/2 bit DQ word and associated DM 0 -X signals. The input register  830  provides the two latched N/2 bit DQ words as an N-bit word to a write FIFO and driver  832 , which clocks the applied DQ word and DM 0 -X signals into the write FIFO and driver in response to the DQS signal. The DQ word is clocked out of the write FIFO and driver  832  in response to the CLK signal, and is applied to the I/O gating and masking circuit  818 . The I/O gating and masking circuit  818  transfers the DQ word to the addressed memory cells in the accessed bank  812 A-D subject to the DM 0 -X signals, which may be used to selectively mask bits or groups of bits in the DQ words (i.e., in the write data) being written to the addressed memory cells. 
   A control logic and command decoder  834  receives a plurality of command and clocking signals over a control bus CONT, typically from an external circuit such as a memory controller (not shown). The command signals include a chip select signal CS*, a write enable signal WE*, a column address strobe signal CAS*, and a row address strobe signal RAS*, while the clocking signals include a clock enable signal CKE* and complementary clock signals CLK, CLK*, with the “*” designating a signal as being active low. The command signals CS*, WE*, CAS*, and RAS* are driven to values corresponding to a particular command, such as a read, write, or auto-refresh command. In response to the clock signals CLK, CLK*, the command decoder  834  latches and decodes an applied command, and generates a sequence of clocking and control signals that control the components  802 - 832  to execute the function of the applied command. The clock enable signal CKE enables clocking of the command decoder  834  by the clock signals CLK, CLK*. The command decoder  834  latches command and address signals at positive edges of the CLK, CLK* signals (i.e., the crossing point of CLK going high and CLK* going low), while the input registers  830  and data drivers  824  transfer data into and from, respectively, the memory device  800  in response to both edges of the data strobe signal DQS and thus at double the frequency of the clock signals CLK, CLK*. This is true because the DQS signal has the same frequency as the CLK, CLK* signals. The memory device  800  is referred to as a double-data-rate device because the data words DQ being transferred to and from the device are transferred at double the rate of a conventional SDRAM, which transfers data at a rate corresponding to the frequency of the applied clock signal. The detailed operation of the control logic and command decoder  834  in generating the control and timing signals is conventional, and thus, for the sake of brevity, will not be described in more detail. 
     FIG. 9  is a block diagram of a computer system  900  including computer circuitry  902  including the memory device  800  of FIG.  8 . Typically, the computer circuitry  902  is coupled through address, data, and control buses to the memory device  800  to provide for writing data to and reading data from the memory device. The computer circuitry  902  includes circuitry for performing various computing functions, such as executing specific software to perform specific calculations or tasks. In addition, the computer system  900  includes one or more input devices  904 , such as a keyboard or a mouse, coupled to the computer circuitry  902  to allow an operator to interface with the computer system. Typically, the computer system  900  also includes one or more output devices  906  coupled to the computer circuitry  902 , such as output devices typically including a printer and a video terminal. One or more data storage devices  908  are also typically coupled to the computer circuitry  902  to store data or retrieve data from external storage media (not shown). Examples of typical storage devices  908  include hard and floppy disks, tape cassettes, compact disk read-only (CD-ROMs) and compact disk read-write (CD-RW) memories, and digital video disks (DVDs). 
   It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. For example, many of the components described above may be implemented using either digital or analog circuitry, or a combination of both, and also, where appropriate, may be realized through software executing on suitable processing circuitry. Therefore, the present invention is to be limited only by the appended claims.