Patent Publication Number: US-6665802-B1

Title: Power management and control for a microcontroller

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a power management system for a microcontroller that provides decentralized power management of the microcontroller subsystems while providing a modular architecture that can be used for microcontrollers having different numbers of subsystems and more particularly to a modular power management architecture for a microcontroller which includes a power management state machine for controlling the power modes of the various microcontroller subsystems as well as a programmable peripheral interface for each of the subsystems which allows the response of the various subsystems to the various power modes to be preconfigured, thereby providing optimal power management of the subsystems. 
     2. Description of the Related Art 
     Various microcontrollers are used in numerous portable battery powered devices, such as portable personal computers and cellular phones. An important concern in any portable battery powered device is extending the amount of time the device can be used before the battery requires recharging. It is known to provide power management of the various subsystems within such portable devices in order to conserve battery power. Computer systems, for example, as disclosed in U.S. Pat. No. 4,980,836, utilize centralized power management control of various peripheral devices, such as the floppy disk drive and hard disk drive in order to conserve battery power. More particularly, in the system disclosed in the &#39;836 patent, accesses to the various peripheral devices, such as the floppy disk drive and the hard disk drive are monitored. If the peripheral devices have not been accessed for a predetermined amount of time, the computer system including the peripherals are placed in a low power state by way the centralized power management control logic. In such a low power state, the system clock frequency may be either stopped or reduced in order to reduce the power consumption of the device. By stopping the system clock, the power consumption is significantly reduced since CMOS devices, typically used in such applications, utilize extremely low power at zero frequency. Other known computer power management systems are disclosed in U.S. Pat. Nos. 4,611,289; 4,041,964; 5,218,704; 5,396,635; and 5,504,907. 
     The drawbacks of centralized power management control for peripheral devices are recognized by peripheral device manufacturers. In particular, it is recognized that the power management of a particular peripheral for a computer system may be best optimized at the peripheral device itself. Thus, various peripheral manufacturers have developed decentralized power management systems for various peripheral devices in order to optimize battery power conservation. For example, U.S. Pat. No. 4,151,611 discloses a power management system for memory systems. U.S. Pat. No. 4,951,309 discloses a power management system for a modem. U.S. Pat. No. 5,345,347 discloses a power management system for a disk drive. U.S. Pat. Nos. 5,546,590 and 5,606,704 disclose power management system for PC MCIA cards. 
     As mentioned above, microcontrollers are used in various applications for portable devices, such as cellular phones and automotive systems. In all such applications, there is an ever increasing trend to reduce the size of the device. For example, in newer cellular phone systems, unlike the “bag” phones in which the battery is carried in a bag separate from the phone, the newer portable cellular telephone include an integral battery and are becoming smaller and smaller. As such, reduction of the size of the cellular phone typically results in a reduction of the battery size. In general, for a given battery chemistry, for example, nickel cadmium or nickel metal hydride, reducing the size of the battery results in a reduced battery capacity. As such, reduced cellular phone size and increased battery capacity have become competing design tradeoffs in such devices. In order to optimize the tradeoff, power management techniques, utilized on a system level, for example, for computer systems, as discussed above, have been implemented on a microcontroller level in order to minimize battery power consumption. In general, power management techniques at the microcontroller level are known to utilize centralized control to control the power to the central processing unit (CPU) by reducing the speed or stopping the system clock. 
     There are several disadvantages in utilizing such centralized control at the microcontroller level. First, such centralized systems do not optimize the power usage of the various subsystems of the microcontroller. In general, the microcontroller subsystems are treated equally with the CPU from a power management standpoint and are thus not optimized. Secondly, the architecture of the power management system in known microcontrollers varies as a function of the number of subsystems included in the microcontroller for a given microcontroller family. For example, lower cost microcontrollers are normally provided without analog and digital converters (ADC) and corresponding ADC ports requiring one power management architecture, while higher level microcontrollers within the same family may include an ADC as well as other subsystems which require a different power management architecture. Thus, for a given family of microcontrollers, multiple power management architectures may be required, which increases the cost and complexity of the microcontrollers. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to solve various problems in the prior art. 
     It is yet a further object of the present invention to provide a power management system for a microcontroller which enables the microcontroller subsystems to be independently controlled. 
     It is yet a further object of the present invention to provide a modular architecture for a power management system for a microcontroller which enables the power management of the microcontroller subsystems to be controlled independently of the central processing unit (CPU). 
     Briefly, the present invention relates to a power management architecture for a microcontroller. The power management architecture includes a power management state machine for controlling the power mode of the central processing unit (CPU) and each of the subsystems within the microcontroller. The power management state machine includes a software configurable register (SFR) to enable the state machine to be configured for device and application specific applications. Each of the microcontroller subsystems is connected to the system by way of a flexible peripheral interface (FPI)(the system bus). The FPI is a 32 bit de-multiplexed, pipelined bus. Each FPI device includes a software configuration register, special function register (SFR) which can be configured by an operating system or application program. The SFR for the various FPI devices enables the response to each of the power modes of each microcontroller subsystem to be pre-configured; thus enabling each subsystem to be independently controlled by the power management state machine in order to optimize the power management of the various subsystems. Each of the FPI interfaces as well as the power management state SFR are connected to an FPI bus which interconnects the FPI interfaces with the central processing unit (CPU) and power management state machine SFR. The FPI bus enables reads and writes of the power management state machine SFR and peripheral interface SFRs. Such a configuration allows subsystems to be added or deleted without changing the basic architecture of the power management system, thus forming a modular power management architecture which reduces the cost and complexity of the microcontrollers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     These and other objects of the present invention are readily understood with reference to the following specification and attached drawings. 
     FIG. 1 is a block diagram of a power management architecture for a microcontroller or system on chip (SoC) in accordance with the present invention, shown with only those subsystems necessary for a complete understanding of the invention for clarity. 
     FIG. 2 is an expanded block diagram of the power management subsystem of the microcontroller illustrated in FIG.  1 . 
     FIG. 3 is a block diagram of the clock subsystem in accordance with present invention which forms a part of the invention. 
     FIG. 4 is a bit diagram of a peripheral interface power control special function register (SFR) in accordance with the present invention. 
     FIG. 5 is a bit diagram of an SFR for a power management state machine in accordance with the present invention. 
     FIG. 6 is a state diagram for the state machine according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention relates to a modular power management architecture for a microcontroller or System on Chip (SoC) which can be utilized for microcontrollers or SoC&#39;s with different numbers of subsystems and which allows an operating system or application program to independently control the subsystems within the microcontroller to optimize power management of the subsystems. In particular, the microcontroller architecture includes a power management subsystem which includes a configurable power management state machine for controlling the power modes of the central processing unit (CPU) and the various microcontroller subsystems. Each microcontroller subsystem is interconnected to the power management subsystem and the CPU by way of a flexible peripheral interface (FPI) and an FPI bus. The power management state machine and the FPI devices each contain a special function register SFR. The power management state machine SFR allows the power management subsystem to be configured for specific applications. The FPI SFRs enable the response of the peripheral to the various power modes of the power management subsystem to be pre-configured by the operating system or application program to provide increased flexibility and optimal power management of the subsystems. Such an architecture allows the power management subsystem to control the various subsystems from a power management standpoint with a few global commands. The use of the FPI bus and FPI peripheral interfaces for each of the subsystems provides for a modular architecture which can be used with virtually any number of subsystems; thus decreasing the complexity and the cost of the microcontrollers. As such, such systems can be added to the microcontroller without the need to design an entirely new integrated circuit. In addition, it should be understood that the modular architecture in accordance with the present invention can be used in applications other than power management to provide optimal control of the microcontroller subsystems. It is noted that, the term “microcontroller” is deemed interchangeable with any System-on-Chip (SoC). 
     As will be discussed in more detail below, the power management subsystem in accordance with the present invention may provide up to four power modes or states: RUN; IDLE; SLEEP; and DEEP SLEEP. Each of these power modes may be optimized through software by way of the SFR registers located in the FPI peripheral interfaces for each of the subsystems for more or less power consumption depending on the instantaneous requirements of the particular subsystem. The IDLE mode affects only the CPU core. The SLEEP and DEEP SLEEP modes affect the complete device and can help control power modes of external devices as well. Each of these modes is discussed in more detail below. 
     As discussed above, the response of each of the subsystems in the states can be preconfigured by the operating system or application program to provide optimum subsystem performance. These states or modes can be used to allow for gradual reduction of power consumption by reduction of the clock speed for any one of the subsystems; stop or complete subsystem power down as well as overall system stop and power down. In all of the modes or states, the power management system continues to operate so that it can wake the subsystems on command. As such, the microcontroller with the power management architecture in accordance with the present invention is able to provide increased battery life for portable microcontrolled devices, such as cellular phones, as well as power loss in a recoverable fashion. In addition, the system can be used to limit peak power during turn-on and reset of the portable device which can cause battery power fault condition, resulting in shut down of the device. During such conditions, the power, oscillator and phase lock loop (PLL) functions may be ramped in order to lower the peak power (Icc MAX ) and startup surge which allows a more efficient low-power power supply to be used thus lowering the cost while dramatically lowering the average power Icc TYP  of the microcontroller. Other advantages of the system in accordance with the present invention include: the ability of the system to maintain its state without data loss during battery discharge conditions such that, for example, the system can enter a static mode at the first sign of a power failure, the power supply can maintain regulation, and the device&#39;s state is maintained until a new battery is inserted or recharged; the ability to shut off entire subsystems during the SLEEP mode in order to minimize power supply losses at low power; and a soft RESET that does not disturb external devices or memory, which allows reset of only those components of the system which were powered down, leaving the external system unaware of the reset. fashion. In addition, the system can be used to limit peak power during turn-on and reset of the portable device which can cause battery power fault condition, resulting in shut down of the device. During such conditions, the power, oscillator and phase lock loop (PLL) functions may be ramped in order to lower the peak power (Icc MAX ) and startup surge which allows a more efficient low-power power supply to be used thus lowering the cost while dramatically lowering the average power Icc TYP  of the microcontroller. Other advantages of the system in accordance with the present invention include: the ability of the system to maintain its state without data loss during battery discharge conditions such that, for example, the system can enter a static mode at the first sign of a power failure, the power supply can maintain regulation, and the device&#39;s state is maintained until a new battery is inserted or recharged; the ability to shut off entire subsystems during the SLEEP mode in order to minimize power supply losses at low power; and a soft RESET that does not disturb external devices or memory, which allows reset of only those components of the system which were powered down, leaving the external system unaware of the reset. 
     SYSTEM BLOCK DIAGRAMS 
     A block diagram for the microcontroller power management architecture in accordance with the present invention is illustrated in FIG.  1  and generally identified with the reference numeral  20 . The power management architecture can be implemented on virtually any microcontroller. For clarity, only those elements and subsystems of the microcontroller necessary for a complete understanding of the invention are shown. As shown, the microcontroller includes a CPU core  22 , which may be any of a variety of CPU cores, such as a 32-bit RISC-like core, a digital signal processor core, or a 16-bit microcontroller core. The CPU core  22  is coupled to a system bus, for example, a multiplexed address/data FPI bus  24 , for example, 32 bit, to enable the operating system or application program to read and write the SFR register in the power management state machine as well as the SFRs in each of the FPI peripheral interfaces for each of the subsystems. A management subsystem  26  is also provided and coupled to the FPI bus. The management subsystem  26  includes a power manager  28  which controls the power modes of the CPU core  22  as well as other subsystems to be controlled as will be discussed in more detail below. Also attached to the FPI bus  24  are various microcontroller subsystems including input/output (I/O) ports  30 , direct memory access (DMA)  32 , system timers  34 , and external bus controller (EBC)  36 . Other standard subsystems are identified with the reference numeral  38 , while applications specific subsystems are identified with the reference numeral  40 . Each of the major subsystems  30 - 40  are connected to the FPI bus  24  by way of a FPI peripheral interface  42 - 52 , respectively. The microcontroller may also include memory banks  54  and  56 , which may be dynamic random access memory (DRAM) and include refresh circuitry  58  and  60 , respectively. As will be discussed in more detail below, an interrupt control unit (ICU)  62  is kept active (i.e. powered up) during all power modes. An Interrupt control signal from the ICU  62  is tied to both the power management subsystem  28  as well as the CPU core  22 . 
     An expanded block diagram of the management subsystem  26  is illustrated in FIG.  2 . As shown, the power management subsystem  26  includes the power manager  28  which includes a power management state machine, a programmable special function register (SFR)  62 , a clock subsystem  64  for generating a system clock signal CLOCK and a reset subsystem  66 . The reset subsystem  66  may be a conventional reset circuit which is responsive to an external hardware reset HDRST!  68  and a power on reset PORST!  70 . (As used herein the symbol ! is used to designate a logical complement of a signal or in other words that the signal is active low.) The reset PORST!  70  resets the complete chip; the complete system is held in reset until the PLL  85  indicates a lock to an external crystal. The reset HDRST! is constantly sampled by the power manager  28  at the power clock frequency to detect the external hardware reset request. The power manager  28  will reset the chip and hold it in reset until it detects an inactive HRDST!. Each of these resets HDRST! and PORST! may be pulled up by pull up resistors  72  and  74 , respectively. The management subsystem  26  may also include a watchdog timer  76  as well as the ability for external signals, such as non-maskable interrupt (NMI) and battery fault, identified as special pins with the reference numeral  78 , shown connected to an external pin  80  to interface with the power system state machine  28 . According to one embodiment, the FPI bus is a demultiplexed 32-bit address/data bus. It is noted, however, that any system bus could be employed. Thus, the figures are exemplary only. 
     SYSTEM I/O PINS 
     Table 1 illustrates the dedicated I/O pins for the power management subsystem  26 . The pins for main crystal, identified with the reference numeral  84 , provide the main clock source. The pins for the 32 KHz crystal, identified with the reference numeral  86 , are optional and are used for those microcontrollers which include a real time clock (RTC). The hard reset HDRST! and power on PORST! reset pins  88  and  90  are used in conjunction with the reset subsystem  66 . As discussed above, special interrupt pins, generally identified with the reference numeral  78 , enable the management subsystem  26  to interface with external interrupts, such as a non-maskable interrupt (NMI) and a battery power fault. The management subsystem  26  may also be provided with output pins, identified in FIG. 2 as boot configuration pins  82 , for core power enable and sleep. These pins are discussed in Table 1 and are configured during boot up and read from the SFR register to control external devices. 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Signal 
                 I/O 
                 Optional 
                 When Unused 
                 Function  
               
               
                   
               
             
            
               
                 Main Crystal 
                 I/O 
                   
                   
                 Main Oscillator 
               
               
                   
                   
                   
                   
                 Source 
               
               
                 PORST! 
                 Input 
                   
                   
                 Power on 
               
               
                   
                   
                   
                   
                 Reset Pin 
               
               
                 HDRST! 
                 I/O 
                   
                   
                 External Hard 
               
               
                   
                   
                   
                   
                 Reset 
               
               
                 Power Fault 
                 Input 
                 Yes 
                 Negated 
                 Pending Battery 
               
               
                   
                   
                   
                   
                 or Power Fault 
               
               
                   
                   
                   
                   
                 (Signal must go 
               
               
                   
                   
                   
                   
                 to ICU as well) 
               
               
                 NMI 
                 Input 
                 Yes 
                 Negated 
                 Non-Maskable 
               
               
                   
                   
                   
                   
                 Interrupt (Signal 
               
               
                   
                   
                   
                   
                 must go to ICU 
               
               
                   
                   
                   
                   
                 as well) 
               
               
                 Core Power 
                 Output 
                 Yes 
                 — 
                 Asserted = 
               
               
                 Enable 
                   
                   
                   
                 Supply Power 
               
               
                   
                   
                   
                   
                 to Device Core, 
               
               
                   
                   
                   
                   
                 Negated = 
               
               
                   
                   
                   
                   
                 Remove Core 
               
               
                   
                   
                   
                   
                 Power 
               
               
                 Sleep 
                 Output 
                 Yes 
                 — 
                 Assert SLEEP 
               
               
                   
                   
                   
                   
                 signal to 
               
               
                   
                   
                   
                   
                 external devices 
               
               
                 32 KHz Crystal 
                 I/O 
                 Yes 
                 — 
                 32 KHz 
               
               
                   
                   
                   
                   
                 oscillator 
               
               
                   
                   
                   
                   
                 Source 
               
               
                   
               
            
           
         
       
     
     SYSTEM CONTROL SIGNALS 
     Table 2 is a list of the signals generated by the power management subsystem  26  used in the overall power management system. These signals are discussed below. 
     
       
         
           
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 SIGNAL 
                 SOURCE 
                 FUNCTION  
               
               
                   
               
             
            
               
                 FPI RESET_N 
                 Management subsystem 26 
                 Hard reset to all 
               
               
                 [1:0] 
                   
                 FPI subsystems 
               
               
                 RESET 
                 Management subsystem 26 
                 software reset to 
               
               
                 [n:0] 
                   
                 individual subsystems 
               
               
                 CPU RESET 
                 Management subsystem 26 
                 reset CPU core 
               
               
                 SYSTEM 
                 Management subsystem 26 
                 Full system clock 
               
               
                 CLOCK 
                   
                 (distribution) 
               
               
                 IDLE 
                 Management subsystem 26 
                 asserting during IDLE 
               
               
                   
                   
                 mode to CPU 
               
               
                 IDLE Ack 
                 CPU 22 
                 asserting when pipe 
               
               
                   
                   
                 line is flushed 
               
               
                 SLEEP 
                 Management subsystem 26 
                 asserting during SLEEP 
               
               
                   
                   
                 mode to system 
               
               
                 FPI_SVN 
                 Bus masters 
                 CPU supervisory 
               
               
                   
                 (Debug included) 
                 mode instruction. 
               
               
                   
               
            
           
         
       
     
     The FPI_SVN signal is a supervisory signal that is asserted by a bus master (i.e. CPU core). More particularly, as mentioned above, each of the subsystems  30 - 40  include a FPI peripheral interface  42 - 52 , respectively, which, in turn, include an SFR register which enables the individual subsystems  30 - 40  to be configured by the operating system on how to respond to the power management commands from the power manager  28 . The management subsystem  26  also includes an SFR register  62  that allows the management subsystem to be configured during boot up by way the operating system for a specific application. The signal FPI_SVN is asserted during a supervisory mode to enable the SFRs to be configured. 
     The reset signal [n: 0 ] RESET is used for resetting the individual subsystems  30 - 40 . One bit per subsystem is provided to enable individual software reset control of each of the subsystems independent of the other systems. The software reset signal RESET [n: 0 ] is connected to a reset bus  92  as well as a hardware reset signal FPI_RESET_N [ 1 : 0 ]. The reset bus  92 , is an n bit bus, for example, a 8 bit bus. One bit is connected to each of the major subsystems  30 - 40 . For example, the Reset on Wake Up bit of the state machine SFR is used to configure the software reset signal for a global reset when persistent memories are not possible. In addition to the software reset signal, RESET [n: 0 ], a hard reset signal FPI_RESET_N [ 1 : 0 ] is also applied to each of the major subsystems  30 - 40  by way of the reset bus  92  to provide a hardware reset to all subsystems  30 - 40 . The hard reset signal FPI_RESET_N [ 1 : 0 ] is available at the output of the OR gate  98  and generated by various sources as indicated in Table 3 below including the power management state machine. The power management state machine generates this signal, for example, as the output of various states, as seen in FIG.  6  and is explained in greater detail below. In particular, this signal may be an output from states SLEEP  140 , POWER UP  142 , Wait PLL  144 , and RESET  148 . 
     Various software entities may request a reset by writing to the SFR  62 . The Reset Unit reset unit  66  reads the soft reset signal and issues a reset control signal to the OR gates  98 ,  100 . 
     The power management state machine  28  can also generate a CPU reset by way of a CPU reset signal, available at the output of an OR gate  100 . from the reset unit  66 . 
     Several signals can be used to reset the complete system or individual subsystems  30 - 40  including: a power on reset PORST!; a hardware reset HDRST!; a watchdog timer reset; and a wakeup reset from a SLEEP mode. Table 3 indicates the reset sources and the results. 
     
       
         
           
               
             
               
                 TABLE 3 
               
             
            
               
                   
               
               
                 RESET RESULTS 
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                   
                 FPI_Reset_n 
                 HDRST! 
                 CPU 
                 Memory 
                 PLL 
                 Boot 
                   
                 Manager 
               
               
                 Reset Source 
                 (1:0) 
                 Out 
                 Reset 
                 Reset 
                 Reset 
                 Config 
                 Debug 
                 Block 
               
               
                   
               
               
                 PORST! 
                 00 
                 X 
                 X 
                 X 
                 X 
                 X 
                 X 
                 X 
               
               
                 HDRST! 
                 00 
                 X 
                 X 
                 X 
                 X 
                   
                 X 
                 X 
               
               
                 Watchdog 
                 00 
                 X 
                 X 
                 X 
                 X 
                   
                 X 
                 X 
               
               
                 PMSM 
                 00 
                   
                 X 
                 X 
                 X 
               
               
                 Soft Reset 
                 RS FPI 
                 RS OUT 
                 X 
                 selectable 
                 RS CLK 
                   
                 RS DBG 
               
               
                 RSTREQ 
               
               
                   
               
            
           
         
       
     
     As illustrated in Table 2, the management subsystem  26  also generates a system clock signal, an IDLE signal, and a SLEEP signal. The IDLE signal is asserted by the power management state machine only to the CPU core  22  to hold its internal clocks. More particularly, when the IDLE signal is asserted, the CPU flushes its pipeline and shuts down its internal clocks until the IDLE signal is removed. The IDLE signal is asserted in the IDLE, SLEEP and DEEP SLEEP modes. Once the IDLE signal is asserted, the CPU core  22  asserts the IDLE acknowledge signal when the pipeline is flushed and halts or disables the internal CPU clock. During the time the IDLE time is asserted, all interrupts from the interrupt controller unit  62  are ignored. The SLEEP signal is an assertion from a power management state machine to all subsystems to switch to their respective SLEEP mode configurations as will be discussed in more detail below. 
     CLOCK SUBSYSTEM 
     The clock subsystem  64  is used to generate a system clock signal as well as a management clock signal. An exemplary clock subsystem  64  is illustrated in FIG.  3  and includes: a system oscillator  104 ; a phase lock loop (PLL)  106 ; and a clock  108 , which are used to generate a system clock signal SYSTEM CLOCK. The main crystal  84  (FIG.  2 ), for example, 15 MHz, depending on the clock speed of the CPU core  22 , is connected to the system oscillator  104  to generate an oscillation frequency of 150 MHz. The PLL  106  locks in the oscillation frequency, while the clock circuit  108  divides the oscillation frequency to provide the system clock frequency, for example 75 MHz. 
     The clock subsystem  64  also includes a management clock  110 . The management clock  110  can be derived from one of three sources such as a real time clock (RTC) oscillator  114 , connected to the 32 KHz crystal  86 ; the system clock oscillator  104 ; or the system clock signal SYSTEM CLOCK. A known multiplexer may be used to switch between the clock sources. The clock subsystem  64  may be configured by the SFR register  62  within management subsystem  26 . Depending on the configuration of the SFR register  62 , the system clock signal may be generated by the main oscillator  84 /PLL  86  or shut down. The management clock is used to run the power management system, a reset clock, and the watchdog timer. 
     During normal operations, the management clock may be sourced by the system clock signal SYSTEM CLOCK. During low power operation, START-UP and DEEP SLEEP mode of operation, the management clock  110  may be driven by the main oscillator  104 . Alternatively, if a 32 KHz oscillator is used for the real time clock, the management clock signal can be generated from the 32 KHz source while the main oscillator remains shut off. 
     SOFTWARE CONFIGURATION REGISTERS (SFR) 
     Software configuration registers (SFR) are provided in each of the subsystems to  30 - 40  in order to control the response of each subsystem  30 - 40  during the different power modes of operation. In particular, each subsystem  30 - 40  is provided with a peripheral interface power control SFR register  116  as illustrated in FIG.  4 . The register  116  may be a 32 bit register as shown with bit definitions as indicated in Table 4 below: 
     
       
         
           
               
               
               
               
               
               
             
               
                 TABLE 4 
               
               
                   
               
               
                   
                   
                   
                   
                 Req/ 
                   
               
               
                 Name 
                 Bits 
                 Value 
                 R/W 
                 O/Rec 
                 Purpose  
               
               
                   
               
             
            
               
                 SME 
                 0 
                 0 
                 r/w 
                 Required 
                 No SLEEP Mode 
               
               
                 (Sleep 
                   
                 1 
                   
                   
                 (Default) Enable 
               
               
                 Mode 
                   
                   
                   
                   
                 SLEEP Mode when 
               
               
                 Enable) 
                   
                   
                   
                   
                 “SLEEP” signal 
               
               
                   
                   
                   
                   
                   
                 assert 
               
               
                 DPC 
                 1 
                 0 
                 r/w 
                 Required 
                 Disable Peripheral 
               
               
                 (Disable 
                   
                 1 
                   
                   
                 during RUN Mode 
               
               
                 Peripheral 
                   
                   
                   
                   
                 (Default) RUN, 
               
               
                 Clock) 
                   
                   
                   
                   
                 Clock enabled 
               
               
                 SDClk 
                 15:8 
                 0000000 
                 r/w 
                 Optional 
                 Disable During 
               
               
                 (Sleep 
                   
                 0 
                   
                   
                 SLEEP (Default) 
               
               
                 Divide 
                   
                 0000000 
                   
                   
                 Divided Clock 
               
               
                 Clock) 
                   
                 1: 
                   
                   
                 During SLEEP as 
               
               
                   
                   
                 1111111 
                   
                   
                 defined by 
               
               
                   
                   
                 1 
                   
                   
                 Peripheral 
               
               
                   
               
            
           
         
       
     
     These peripheral interface power control SFR registers  116  allow the operating system to control each of the subsystems  116  independently. Subsystems  30 - 40  that are not used may be either powered down or have their clock forced into a static state. As mentioned above, the peripheral interface power control SFR register  116  is only accessible in the supervisory mode of the CPU core  22  or other privileged modes. These registers  116  may be reset to a default value when the reset signal FPI RESET_N [ 1 : 0 ]=00 or 01 or during a soft reset. 
     As noted from Table 4, the register  116  includes a SLEEP mode enable bit SME, which allows the subsystem  30 - 40  either to ignore the SLEEP mode or enable the sleep mode when the SLEEP signal is asserted by the power management state machine. A disable peripheral clock (DPC) bit allows the subsystem or peripheral to either be disabled during a RUN mode or enabled. A sleep divide clock (SDCLK) bit and a divide clock (DIVCLK) bit either disables or provides divided clock signals to the subsystem during a SLEEP mode and also may provide a divided clock signal to the subsystem during a normal mode. The peripheral interface control SFR register  116  may also provide for a peripheral specific configuration of a peripheral specific sleep mode which would be active when the sleep mode enable signal SME is set. 
     As mentioned above, the power management state machine also includes an SFR register  62  which allows the power management system to be configured for specific applications. The register  62  is illustrated in FIG. 5. A definition of the bits in the register  62  is provided in table 5 below. 
     
       
         
           
               
               
               
               
               
               
             
               
                 TABLE 5 
               
               
                   
               
               
                   
                   
                 VAL- 
                 R/ 
                 REQ/O/ 
                   
               
               
                 NAME 
                 BITS 
                 UE 
                 W 
                 REC 
                 PURPOSE  
               
               
                   
               
             
            
               
                 ReqSlp 
                 1:0 
                 00 
                 r/w 
                 Required 
                 No Sleep Request 
               
               
                 (Request 
                   
                   
                   
                   
                 (Default) 
               
               
                 Sleep) 
                   
                   
                   
                   
                 Idle Request 
               
               
                   
                   
                   
                   
                   
                 Sleep Request 
               
               
                   
                   
                   
                   
                   
                 Deep Sleep Request 
               
               
                   
                   
                   
                   
                   
                 (DEEP SLEEP bit) a   
               
               
                   
                   
                   
                   
                   
                 Note: this field is 
               
               
                   
                   
                   
                   
                   
                 cleared upon return 
               
               
                   
                   
                   
                   
                   
                 to RUN state 
               
               
                 RW 
                 4 
                 0 
                 r/w 
                 Required 
                 No Reset on Wake 
               
               
                 (Reset on 
                   
                   
                   
                   
                 Up(Default) 
               
               
                 Wake-Up) 
                   
                 1 
                   
                   
                 Reset on Wake Up b   
               
               
                 CPO (Core 
                 5 
                 0 
                 r/w 
                 Optional 
                 Core Powered during 
               
               
                 Power Off) 
                   
                   
                   
                   
                 DEEP SLEEP (De- 
               
               
                   
                   
                   
                   
                   
                 fault) Core Powered 
               
               
                   
                   
                 1 
                   
                   
                 Off in DEEP SLEEP 
               
               
                 PMSt (Power 
                 15:8 
                   
                 r 
                 Required 
                 As defined in the 
               
               
                 Management 
                   
                   
                   
                   
                 implementation 
               
               
                 State) 
               
               
                 ClkSrc (Clock 
                 19:16 
                 0000 
                 r/w 
                 Required 
                 Normal PLL (Default) 
               
               
                 Source during 
                   
                 0010 
                   
                 Recom- 
                 Oscillator Pass 
               
               
                 Sleep) 
                   
                 0011 
                   
                 mended 
                 Through/PLL on 
               
               
                   
                   
                 0100 
                   
                 Recom- 
                 Oscillator Pass 
               
               
                   
                   
                 0101 
                   
                 mended 
                 Through/PLL off 
               
               
                   
                   
                 1000 
                   
                 Optional 
                 32 KHz/Osc &amp; PLL on 
               
               
                   
                   
                 1010 
                   
                 Optional 
                 32 KHz/Osc &amp; PLL 
               
               
                   
                   
                   
                   
                   
                 off 
               
               
                   
                   
                 1011 
                   
                 Required 
                 Normal PLL/No Sys 
               
               
                   
                   
                 1100 
                   
                 Recom- 
                 Clk 
               
               
                   
                   
                 1101 
                   
                 mended 
                 Oscillator Pass 
               
               
                   
                   
                   
                   
                   
                 Through/PLL 
               
               
                   
                   
                 all 
                   
                 Recom- 
                 on/No Sys Clk 
               
               
                   
                   
                 oth- 
                   
                 mended 
                 Oscillator Pass 
               
               
                   
                   
                 ers 
                   
                   
                 Through/PLL off/No 
               
               
                   
                   
                   
                   
                 Optional 
                 Sys Clk 
               
               
                   
                   
                   
                   
                   
                 32 KHz/Osc &amp; PLL 
               
               
                   
                   
                   
                   
                 Optional 
                 on/No Sys Clk 
               
               
                   
                   
                   
                   
                   
                 32 KHz/Osc &amp; PLL 
               
               
                   
                   
                   
                   
                   
                 off/No Sys Clk 
               
               
                   
                   
                   
                   
                   
                 Reserved 
               
               
                 WOPSL (Watch 
                 21:20 
                 00 
                 r/w 
                 Recom- 
                 Watchdog operates 
               
               
                 dog Operation 
                   
                   
                   
                 mended 
                 during Sleep and Idle 
               
               
                 in Sleep) 
                   
                   
                   
                   
                 and overflow can 
               
               
                   
                   
                   
                   
                   
                 cause reset (Default) 
               
               
                   
                   
                 01 
                   
                   
                 Watchdog operates 
               
               
                   
                   
                   
                   
                   
                 during Sleep and Idle 
               
               
                   
                   
                   
                   
                   
                 and causes wake-up 
               
               
                   
                   
                 10 
                   
                   
                 Watchdog Timer clock 
               
               
                   
                   
                   
                   
                   
                 stopped during Sleep. 
               
               
                   
                   
                   
                   
                   
                 Note: The Watchdog 
               
               
                   
                   
                   
                   
                   
                 timer will be unable to 
               
               
                   
                   
                   
                   
                   
                 cause a reset or wake 
               
               
                   
                   
                   
                   
                   
                 up from Sleep in this 
               
               
                   
                   
                   
                   
                   
                 mode. 
               
               
                   
                   
                 11 
                   
                   
                 Reserved 
               
               
                 SlpClk 
                 26:24 
                 000 
                 r/w 
                 Recom- 
                 No Division of System 
               
               
                 (Sleep 
                   
                   
                   
                 mended 
                 Clock during 
               
               
                 Clock) 
                   
                   
                   
                   
                 Sleep (Default) 
               
               
                   
                   
                 001 
                   
                   
                 Divide System Clock 
               
               
                   
                   
                   
                   
                   
                 by 2 during Sleep 
               
               
                   
                   
                   
                   
                   
                 Divide System Clock 
               
               
                   
                   
                 010 
                   
                   
                 by 4 during Sleep 
               
               
                   
                   
                 to 
                   
                   
                 Divide System Clock 
               
               
                   
                   
                 111 
                   
                   
                 by 128 during Sleep 
               
               
                   
               
            
           
         
       
     
     Referring to Table 5, a request sleep signal REQSLP allows the power management state machine to be configured for different reduced power modes of operation; IDLE, SLEEP and DEEP SLEEP. Alternatively, the request sleep signal REQSLP can be set to 00 which disables the power management function altogether (a nominal configuration until some managed state is desired). A reset on wakeup signal RW is used to configure the reset state on wakeup. A core power off signal CPO is used to define whether the CPU core  22  is powered in the DEEP SLEEP mode. The state of power management state machine signal PMST are read only bits and enables the power management state to be read by the system for debug and development. A clock source signal CLKSRC enables the clock source to be configured for different power states. A watchdog operation in sleep mode (WOPSL) signal defines the operation of the watchdog timer during SLEEP and IDLE modes. A sleep clock signal SLPCLK is used to program the frequency of the system clock during a sleep mode of operation. 
     Table 6 illustrates the resulting actions from the watchdog timer in alternative states. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 6 
               
               
                   
                   
               
               
                   
                 Watchdog 
                   
                   
               
               
                   
                 Overflow State 
                 WOPSL! = 01 
                 WOPSL = 01  
               
               
                   
                   
               
             
            
               
                   
                 RUN 
                 Cause System Reset 
                 Force System Reset 
               
               
                   
                 IDLE 
                 Cause System Reset 
                 Transition to RUN 
               
               
                   
                 SLEEP 
                 Cause System Reset 
                 Wake-up 
               
               
                   
                 POWER UP 
                 Cause System Reset 
                 Continue Wake-up 
               
               
                   
                 OSC/PLL 
                 Cause System Reset 
                 Continue Wake-up 
               
               
                   
                 All Others 
                 Cause System Reset 
                 Ignore 
               
               
                   
                   
               
            
           
         
       
     
     The clock source as set by the system clock bits CLKSRC is illustrated in Table 7: 
     
       
         
           
               
               
               
               
               
               
             
               
                 TABLE 7 
               
               
                   
               
               
                   
                   
                   
                   
                 Management 
                 System 
               
               
                   
                 Deep 
                   
                 Sip- 
                 Clock 
                 Clock 
               
               
                 State 
                 Sleep 
                 ClkSrc 
                 Clk 
                 Source 
                 Source  
               
               
                   
               
             
            
               
                 RUN 
                 — 
                 — 
                 — 
                 Divided PLL 
                 Divided PLL 
               
               
                   
                   
                   
                   
                 Output 
                 Output 
               
               
                 IDLE 
                 — 
                 — 
                 — 
                 Divided PLL 
                 Divided PLL 
               
               
                   
                   
                   
                   
                 Output 
                 Output 
               
               
                 START 
                 — 
                 — 
                 — 
                 Divided PLL 
                 Divided PLL 
               
               
                 SHUTDOWN 
                   
                   
                   
                 Output 
                 Output 
               
               
                 SHUTDOWN/ 
                 0 
                 0000 
                 n 
                 PLL/2 n   
                 PLL/2 n   
               
               
                 SLEEP/POWER 
               
               
                 UP/Wait 
               
               
                 PLL/FAULT 
               
               
                   
                 0 
                 001X 
                 n 
                 Osc/2 n   
                 Osc/2 n   
               
               
                   
                 0 
                 010X* 
                 n 
                 32 KHz/2 n   
                 32 KHz/2 n   
               
               
                   
                 0 
                 1000 
                 n 
                 PLL/2 n   
                 None 
               
               
                   
                 0 
                 101X 
                 n 
                 Osc/2 n   
                 None 
               
               
                   
                 0 
                 110X* 
                 n 
                 32 KHz/2 n   
                 None 
               
               
                   
                 1 
                 X000 
                 n 
                 PLL/2 n   
                 None 
               
               
                   
                 1 
                 X01X 
                 n 
                 Osc/2 n   
                 None 
               
               
                   
                 1 
                 X01X* 
                 n 
                 32 KHz/2 n   
                 None 
               
               
                   
               
            
           
         
       
     
     It should be noted that if there is no 32 KHz clock/oscillator in the system, the source will default to the internal main oscillator equivalent to inverting PMSM [ 18 : 17 ], i.e. clock source=X10X!=X10X. 
     POWER MANAGEMENT MODES 
     The configuration of the system during the RUN, IDLE and SLEEP modes is illustrated in Table 8. 
     
       
         
           
               
               
               
               
               
               
             
               
                 TABLE 8 
               
               
                   
               
               
                 Mode 
                 Clock 
                 Units Powered 
                 Units Clocked 
                 State 
                 Wake Up 
               
               
                   
               
             
            
               
                 RUN 
                 Oscillators 
                 CPU Memory 
                 CPU 
                 System 
                 Not 
               
               
                   
                 Pll Clock 
                 ICU RTC 
                 Memory 
                 Fully 
                 Applicable 
               
               
                   
                 Distribution 
                 Watchdog 
                 ICU 
                 Operational 
               
               
                   
                 of PLL Clock 
                 power 
                 RTC 
               
               
                   
                   
                 Management 
                 Watchdog 
               
               
                   
                   
                 Reset 
                 Power 
               
               
                   
                   
                 Pins 
                 Management 
               
               
                   
                   
                 FPI Bus 
                 Reset 
               
               
                   
                   
                 Per 
                 Pins 
               
               
                   
                   
                 SFR 
                 FPI Bus 
               
               
                   
                   
                 System Timers 
                 Per 
               
               
                   
                   
                 EBC 
                 SFR and 
               
               
                   
                   
                 DMA 
                 Power 
               
               
                   
                   
                 Ports 
                 System Timers 
               
               
                   
                   
                 Peripherals 
                 EBC 
               
               
                   
                   
                   
                 DMA 
               
               
                   
                   
                   
                 Ports 
               
               
                   
                   
                   
                 Peripherals 
               
               
                 IDLE 
                 Oscillators 
                 CPU 
                 Memory 
                 CPU Core 
                 Any 
               
               
                   
                 PLL 
                 Memory 
                 ICU 
                 stopped 
                 enabled 
               
               
                   
                 Clock 
                 ICU 
                 RTC 
                 Local 
                 interrupt in 
               
               
                   
                 Distribution 
                 RTC 
                 Watchdog 
                 Memory 
                 ICU 
               
               
                   
                 of PLL Clock 
                 Watchdog 
                 Power 
                 accessible 
               
               
                   
                   
                 Power 
                 Management 
                 to DMA 
                 NMI, 
               
               
                   
                   
                 Management 
                 Reset 
                 and 
                 Special 
               
               
                   
                   
                 Reset 
                 Pins 
                 peripherals 
                 Pins 
               
               
                   
                   
                 Pins 
                 FPI Bus 
               
               
                   
                   
                 FPI Bus 
                 Per 
                   
                 Reset 
               
               
                   
                   
                 Per 
                 SFR and 
               
               
                   
                   
                 SFR 
                 Power 
               
               
                   
                   
                 System Timers 
                 System Timers 
               
               
                   
                   
                 EBC 
                 EBC 
               
               
                   
                   
                 DMA 
                 DMA 
               
               
                   
                   
                 Ports 
                 Ports 
               
               
                   
                   
                 Peripherals 
                 Peripherals 
               
               
                 SLEEP 
                 Oscillator 
                 Memory 
                 Memory 
                 CPU Core 
                 Any 
               
               
                   
                 Clock 
                 ICU 
                 ICU 
                 Stopped 
                 enabled 
               
               
                   
                 Distribution 
                 RTC 
                 RTC 
                 and may 
                 interrupt in 
               
               
                   
                 of PLL or 
                 Watchdog 
                 Watchdog 
                 be 
                 ICU 
               
               
                   
                 Oscillator as 
                 Power 
                 Power 
                 unpowered. 
               
               
                   
                 configured 
                 Management 
                 Management 
                   
                 NMI, 
               
               
                   
                 in SFR 
                 Reset 
                 Reset 
                 Local 
                 Special 
               
               
                   
                   
                 Pins 
                 Pins 
                 memory 
                 Pins 
               
               
                   
                   
                 FPI Bus 
                 FPI Bus 
                 accessible 
               
               
                   
                   
                   
                   
                 to enabled 
               
               
                   
                   
                 Per SFR 
                 Per SFR and 
                 devices 
                 Reset 
               
               
                   
                   
                 System Timers 
                 Power 
               
               
                   
                   
                 EBC 
                 System Timers 
                 PLL may 
               
               
                   
                   
                 DMA 
                 EBC 
                 be disabled 
               
               
                   
                   
                 Ports 
                 DMA 
               
               
                   
                   
                 Peripherals 
                 Ports 
               
               
                   
                   
                   
                 Peripherals 
               
               
                   
                 No Clock 
                 ICU 
                 ICU 
                 CPU Core 
                 Any 
               
               
                   
                 Distrusted 
                 RTC 
                 RTC 
                 stopped 
                 enabled 
               
               
                   
                 per SFRs 
                 Watchdog 
                 Watchdog (per 
                 and may 
                 EXTERNAL 
               
               
                   
                   
                 Power 
                 SFR) 
                 be 
                 interrupt in 
               
               
                   
                   
                 management 
                 Power 
                 unpowered. 
                 ICU 
               
               
                   
                   
                 Reset 
                 Management 
               
               
                   
                   
                 Pins 
                 Reset 
                 Local 
                 NMI, 
               
               
                   
                   
                   
                   
                 memory 
                 Special 
               
               
                   
                   
                   
                   
                 inaccessible 
                 Pins, 
               
               
                   
                   
                   
                   
                 PLL 
                 Watchdog 
               
               
                   
                   
                   
                   
                 is 
                 Reset 
               
               
                   
                   
                   
                   
                 disabled 
               
               
                   
               
            
           
         
       
     
     Each of the power modes is summarized in Table 9 and described in detail below: 
     
       
         
           
               
               
             
               
                 TABLE 9 
               
               
                   
               
               
                 MODE 
                 OPERATION  
               
               
                   
               
             
            
               
                 RUN 
                 In this mode the system is fully operational. 
               
               
                   
                 All power supply are enabled as controlled by 
               
               
                   
                 software and all clocks and all subsystems are 
               
               
                   
                 enabled as controlled by software. 
               
               
                 IDLE 
                 In this mode the system is semi-operation. 
               
               
                   
                 As mentioned above, only the CPU core is affected. 
               
               
                   
                 During this mode, the CPU core and awaiting 
               
               
                   
                 an interrupt. The CPU core clock is disabled. 
               
               
                   
                 This state is active entered by the operating 
               
               
                   
                 system when no outstanding actions are 
               
               
                   
                 pending. During this mode, all subsystems 
               
               
                   
                 remain powered up and fully clogged. The CPU 
               
               
                   
                 memory remains accessible to the subsystems 
               
               
                   
                 during this mode. A watchdog reset or any 
               
               
                   
                 enabled interim event can be used to wake the CPU. 
               
               
                 SLEEP 
                 The CPU core, is IDLE. In this mode, the phase 
               
               
                 (distributed 
                 lock loop (PLL) or oscillator (OSC) clock is 
               
               
                 clock) 
                 distributed to the subsystems which have been 
               
               
                   
                 preconfigured to operate in the SLEEP mode. 
               
               
                   
                 Interrupts from operating subsystems, a watchdog 
               
               
                   
                 reset or external signal can be used to wake 
               
               
                   
                 the system. Exact state of all of the subsystems 
               
               
                   
                 in the device is configured by the operating 
               
               
                   
                 system or application program prior to this 
               
               
                   
                 state being entered. Options include clock 
               
               
                   
                 source, operation and power modes of different 
               
               
                   
                 subsystems. Varying this state requires a shutdown 
               
               
                   
                 controlled by the power management systems 
               
               
                 SLEEP (no 
                 In this state the CPU core is IDLE and the clock 
               
               
                 distributed 
                 is distributed only to the power management system. 
               
               
                 clock) 
                 Exact state of this device is configured by 
               
               
                   
                 the operating system or application program before 
               
               
                   
                 the state is entered. Options include PLL 
               
               
                   
                 on/off, clock source or power management 
               
               
                   
                 system watchdog operation in power to subsystems. 
               
               
                   
                 Entering this state requires an orderly shutdown 
               
               
                   
                 controlled by the power management system. A 
               
               
                   
                 watchdog overflow, external signal or enabled 
               
               
                   
                 interrupt event can be used to wake the system. 
               
               
                   
                 In this state, any interrupt control unit (ICU) 
               
               
                   
                 is clocked with the power management circuitry. 
               
               
                 DEEP 
                 This state is a subset of the SLEEP mode state. 
               
               
                 SLEEP 
                 In this state, core power may be shut off PLL 
               
               
                   
                 off and only one oscillator is enabled. In 
               
               
                   
                 this state only a hard reset, non-maskable 
               
               
                   
                 interrupt (NMI) or an external signal can 
               
               
                   
                 be used to restart the device. Entering this 
               
               
                   
                 state requires an orderly shutdown by the 
               
               
                   
                 power management system. 
               
               
                   
               
            
           
         
       
     
     IDLE MODE 
     The IDLE mode allows the operating system or application software to stop the core CPU clocks in order to reduce power consumption. During this mode, the CPU awaits any internal or external interrupt events. When interrupt is detected, the system begins clocking immediately and execution starts where the CPU program counter was left. The interrupt is then taken. During this IDLE mode, all other on-chip clocks, PLL and devices function normally. The IDLE mode is entered when the CPU core sets the power management state machine register request sleep bit to IDLE. The power management state machine then asserts the IDLE signal to the CPU core which causes the CPU to clear its pipeline and halt while asserting an IDLE acknowledge. Three actions cause the system to switch from an IDLE mode to a RUN mode. First, any enabled interrupt can cause a transition from the IDLE mode to the RUN mode. Secondly, an assertion of a reset or watchdog timeout (if WOPSL!=01) may also cause transition form the IDLE mode to RUN mode after completing a reset operation. Third, an assertion of a watchdog timeout will cause a transition of the IDLE to RUN mode if the power management state machine bit WOPSL is set to [0:1]. 
     SLEEP MODE (Clock Distributed) 
     The sleep mode (clock distributed mode) is a subset of the sleep mode and it can include sleep with clocks, no clocks and deep sleep where power may be disabled. In this mode, the PLL and oscillator are not stopped and the clock is distributed to the system. The sleep mode may be entered under program control when substantial power saving is desired and a quick response to interrupt events is required or background functionality is required. This mode allows the operating system to stop the clock for CPU  22  and selected peripheral clocks to reduce power consumption while waiting for internal or external interrupt events. This mode also allows the option of operating only those peripherals having a reduced clock frequency. When an interrupt is detected, all systems begin clocking and execution starts. During this sleep mode with clock distributed, all other on-chip clocks, PLL&#39;s and devices not explicitly stopped by program control function normally. As mentioned above, the response to the subsystems  30  through  40  to the various power modes are configured under program control. Thus, the peripheral interface control register may be set during a supervisory mode of the CPU core  22  which will enable seep ES and divide clock bits. The CPU core may configure any reduced speed through the power management state machine configuration register bits  19 : 16  by configuring the clock source CLKSRC bits and the sleep clock bits  26 : 24 . 
     Any enabled interrupt event (except fault) to the CPU core  22  cause a transition to the sleep mode to the RUN mode. An assertion of reset will also cause the transition through the reset state to the RUN mode. If a watchdog overflow is detected, it will either cause a reset or transition to RUN mode depending on the configuration of the WOPSL and the power management state machine software configuration register  62 . Alternately, the assertion of a fault condition will cause the system to transition from a sleep mode to a deep sleep/fault mode. 
     SLEEP MODE (Clock Not Distributed) 
     The sleep mode (clock not distributed) mode is entered under program control when high power saving is required and immediate response to interrupt events is not required. This mode allows the operating system or application software to stop the CPU core  22 , optionally remove the CPU power and remove power and clocks from most or all of the subsystems. Also, the PLL  106  may be shutdown to minimize power consumption. The system will wait for a limited set of internal or external interrupt events to the CPU core  22 . When an enabled interrupt event is detected, a powerup sequence begins. In the transition from the RUN or IDLE mode to sleep mode, the power management state machine performs an orderly shutdown of on-chip activity to CPU core to be turned off. For example, the CPU core  22 , then the peripherals, and then clocks (if configured) are shut down in sequence. During a deep sleep mode, only a few functional units are powered and clocked including a clock source for the management block and ICU-special interrupt inputs and the I/O pins are powered. 
     The sleep mode (clock not distributed) mode is entered when the CPU core  22  sets the power management state machine software configuration register SFR  62  Request Sleep REQSLP bit to SLEEP and the clock source bits and no distribution of clock as indicated in Table 5. Any enabled interrupt, event, except a fault condition (battery or voltage), will cause a transition from a sleep mode through a wake-up sequence to a RUN mode, for examples, in response to a timer expiring or an external interrupt. The assertion of the fault mode will cause a CPU to transition from the power-up or OSC/PLL state to a deep sleep/fault mode state. The assertion of a hard reset will also force the system to perform a reset sequence which may cause loss of external and internal memory contents. On exit from the sleep mode, the CPU core  22  checks the status to identify if and why it came out of reset (i.e. cold boot, soft boot, watchdog reset or sleep mode wakeup). 
     DEEP SLEEP AND FAULT MODE 
     The DEEP SLEEP mode is entered under program control when the system must be placed on a maximum power saving mode or there has been a catastrophic failure that requires the system to shutdown completely. This mode can also be entered automatically if the power management state machine senses a fault condition as it tries to exit a sleep or deep sleep mode. Only an external hardware reset or special pins like the NMI can force the system to power on again. In order to enter the deep sleep mode, the CPU core sets the power management state machine software configuration register Request Sleep signal REQSLP to deep sleep. Alternatively, the assertion of a fault condition while the power management is in a sleep, power up or wake PLL state will cause the system to transition into a deep sleep/fault mode. Any enabled interrupt event except a fault condition (battery or voltage) to a CPU will cause the start of a wakeup process. On exiting the deep sleep mode, the CPU must check the status o identify why it came out of a PMSM SFR RW bit. These reasons include cold boot, soft boot, watchdog reset or sleep mode wakeup, deep sleep is considered a soft reset. 
     POWER MANAGEMENT STATE MACHINE 
     As mentioned above, the heart of the power management control system is a power management state machine. A state diagram for the power management state machine is illustrated in FIG.  6 . As indicated in the state diagram (FIG.  6 ), generally identified with the reference numeral,  130 , the state machine includes 8 states: a RUN state  132 ; an IDLE state  134 ; a START/SHUTDOWN state  136 ; a SHUTDOWN state  138 ; a SLEEP (DEEPSLEEP) state  140 ; a POWER UP state  142 ; a WAIT PLL state  144 ; a FAULT transition state  146 ; and a RESET state  148 . 
     The status of each of the state variables in each of the states is provided below: 
     POWER STATES 
     In the RUN State, the following system state variables are: 
     Core Power=True 
     Oscillator=True 
     PLL=True 
     Low Speed Clocks=False 
     Core Reset=False 
     IDLE=False 
     Sleep=False 
     IDLE STATE 
     In the IDLE State, the following system state variables are: 
     Core Power=True 
     Oscillator=True 
     PLL=True 
     Low Speed Clocks=False 
     Core Reset=False 
     IDLE=True 
     Sleep=False 
     Wait for Interrupt, Watchdog, Reset to exit State. 
     On transition to Run Clear SIpReq Register field. 
     START SHUTDOWN STATE 
     In the START SHUTDOWN State, the following system state variables are: 
     Core Power=True 
     Oscillator=True 
     PLL=True 
     Low Speed Clocks=False 
     Core Reset=False 
     IDLE=True 
     Sleep=True 
     SHUTDOWN STATE 
     In the SHUTDOWN State, the following system state variables are: 
     Core Power=True 
     Oscillator=True 
     PLL=True 
     Core Reset=False 
     IDLE=True 
     Sleep=True 
     If (ClkSrc!=0000) Low Speed Clocks=True 
     SLEEP (DEEP SLEEP) STATE 
     In the SLEEP State, the following system state variables are: 
     IDLE=True 
     Sleep=True 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 If (ClkSrc = 1XXX) 
                 Sys Clocks = False 
               
               
                   
                 If (ClkSrc = 1XX1) 
                 PLL = False 
               
               
                   
                 If (ClkSrc = 1101) 
                 Oscillator = False 
               
               
                   
                 If (ClkSrc ! = 0000) 
                 Low Speed Clocks = True 
               
               
                   
                 IF (DEEP SLEEP) 
                 Sys Clocks = False 
               
               
                   
                   
                 PLL = False 
               
               
                   
                 If (CPO = 1) 
                 Power = False 
               
               
                   
                   
                 Core Reset = True 
               
               
                   
                   
               
            
           
         
       
     
     Wait for interrupt, Watchdog, Reset etc. to exit Sleep State 
     POWER UP STATE 
     In the POWER UP State, the following system state variable are 
     IDLE=True 
     Sleep=True 
     Power=True 
     Oscillator=True 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 If (ClkSrc = 1XXX) 
                 Sys Clocks = False 
               
               
                   
                 If (ClkSrc = 1XX1) 
                 PLL = False 
               
               
                   
                 If (ClkSrc ! = 0000) 
                 Low Speed Clocks = True 
               
               
                   
                 If (RW = 1) 
                 Sys Clocks = False 
               
               
                   
                 If (DEEP SLEEP) 
                 PLL = False 
               
               
                   
                 If (CPO = 1) 
                 Core Reset = True 
               
               
                   
                   
                 Wait for (Fault ! Power OK ! Osc OK ! 
               
               
                   
                   
               
            
           
         
       
     
     Timer time-out) ! (!DEEP SLEEP &amp; ClkSrc=X0XX). If a Fault is asserted, the State Machine will transition to a Fault State. 
     WAIT PLL STATE 
     In the Wait PLL State, the following system state variables are: 
     IDLE=True 
     Sleep=True 
     Power=True 
     Oscillator=True 
     PLL=True 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 If (ClkSrc = 1XXX) 
                 Sys clocks = False 
               
               
                   
                 If (ClkSrc ! = 0000) 
                 Low Speed Clocks = True 
               
               
                   
                 If (RW = 1) 
                 Core Reset = True 
               
               
                   
                 If (DEEP SLEEP) 
                 Sys Clocks = False 
               
               
                   
                 If (CPO = 1) 
                 Core Reset = True 
               
               
                   
                   
               
            
           
         
       
     
     Wait for (Fault ! PLL Lock ! Timer time-out) ! (!DEEP SLEEP &amp; ClkSrc=XXX0). If a Fault is asserted the State Machine will transition to the Fault State. On transition to Run Clear SlpReq Register field. 
     FAULT TRANSITION STATE 
     This is a transient state that forces the system into a Fault Mode from certain Power Management States (Sleep, exiting Sleep). 
     If Fault is asserted while exiting Sleep Mode, the state machine state causes: 
     IDLE=True 
     Sleep=True 
     Set ReqSlp=DEEP SLEEP 
     Set RW=True if a DRAM system 
     Set MSB of ClkSrc= 1  ( 1 XXX) 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 If (ClkSrc = 1XX1) 
                 PLL = False 
               
               
                   
                 If (ClkSrc = 1101) 
                 Oscillator = False 
               
               
                   
                 If (ClkSrc ! = 0000) 
                 Low Speed Clocks = True 
               
               
                   
                 IF (DEEP SLEEP) 
                 Sys Clocks = False 
               
               
                   
                   
                 PLL = False 
               
               
                   
                 If (CPO = 1) 
                 Power = False 
               
               
                   
                   
                 Core Reset = True 
               
               
                   
                   
               
            
           
         
       
     
     RESET STATE 
     In the Reset state, the following system state variables are: 
     IDLE=True 
     Sleep=True 
     Power=True 
     Oscillator=True 
     PLL=False 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 If (ClkSrc = 1101), 
                 Oscillator = False 
               
               
                   
                 If (ClkSrc ! = 0000) 
                 Low Speed Clocks = True 
               
               
                   
                 IF (DEEP SLEEP) 
                 Sys Clocks = False 
               
               
                   
                   
                 PLL = False 
               
               
                   
                 If (CPo = 1) 
                 Power = False 
               
               
                   
                   
                 Core Reset = True 
               
               
                   
                   
               
            
           
         
       
     
     Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.