Patent Publication Number: US-9852953-B2

Title: CMOS fabrication

Description:
PRIORITY APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 14/470,526 (filed 27 Aug. 2014), which is a divisional of U.S. patent application Ser. No. 11/408,112 (filed 20 Apr. 2006), issued 2 Sep. 2014 as U.S. Pat. No. 8,823,108, which is a divisional of U.S. patent application Ser. No. 11/152,988 (filed 14 Jun. 2005), issued 28 Dec. 2010 as U.S. Pat. No. 7,858,458, the entire disclosures of which are hereby incorporated by reference herein in their entireties. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates generally to integrated circuit design and, more particularly, to a process for defining complementary metal oxide semiconductor (“CMOS”) transistors. 
     Description of the Related Art 
     Integrated circuits are typically produced according to a series of complex fabrication steps including deposition, masking, etching and doping steps. The complexity of the fabrication greatly increases the cost of the integrated circuits, and often results in relatively low manufacturing efficiency. 
     For example, for memory circuits or devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs) and ferroelectric (FE) memories, the fabrication of the CMOS logic around the periphery traditionally comprises a number of relatively time-consuming and expensive masking steps. 
     First, a mask is used to define the active areas of the transistors in the CMOS by shallow trench isolation (STI). According to some manufacturing methods, this same masking stage may be used to simultaneously define active areas in the array by STI. Next, a gate oxide is defined, typically in both the periphery and array. Using one mask for the n-channel metal oxide semiconductors (nMOS) and another mask for the p-channel metal oxide semiconductors (pMOS), the well, n-channel enhancement implants and polysilicon workfunction implants are defined in the next step. 
     The polysilicon for forming the gates in the CMOS may then be formed using another mask. The lightly doped drain (LDD) implant and Halo implant (or pocket implant, as it is sometimes referred to) may then be formed around the CMOS gates using one mask for the nMOS, one mask for the pMOS, and yet another mask for the array. 
     Spacers are then typically formed along the vertical sidewalls of gate electrodes of both the periphery and array. The source and drain regions for the transistors may then be doped using a mask for each of the nMOS and pMOS regions. Finally, a low k gap fill oxide is deposited along the top of the memory device, and the device undergoes rapid thermal processing (RTP) for dopant activation. The transistors and other circuit elements of the array and periphery are thereby defined, and lines may then be connected thereto according to other steps well known to those of skill in the art. 
     As is clear from the description above, a typical CMOS fabrication process necessitates the use of many masks, and is a complex, time-consuming process. An exemplary CMOS fabrication process flow as described above, for example, employs eight (8) masks from definition of field isolation until transistor source/drain doping for each of the nMOS and pMOS regions. There is a need, therefore, for a less complex manufacturing technique that would use fewer masks, and that would also have an improved yield in comparison to traditional techniques. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the invention, a process is provided for forming a memory device. The method includes patterning gates in nMOS and pMOS regions for CMOS circuits. The pMOS regions are masked with a first mask. Source/drain doping and supplemental doping between source/drain regions and the gates are conducted in the nMOS regions while the pMOS regions remain masked with the first mask. The nMOS regions are masked with a second mask. Source/drain doping and supplemental doping between source drain regions and the gates are conducted in the pMOS regions while the nMOS regions remain masked with the second mask. Exemplary supplemental doping includes lightly doped drain (LDD) and pocket or Halo implants. 
     According to another aspect of the invention, a method of manufacturing a memory device is disclosed. The method includes providing a substrate and defining a pMOS region and an nMOS region in the substrate. A first gate is defined in the nMOS region, and a second gate is defined in the pMOS region. First and second spacers are formed over the first and second gates, respectively. The nMOS and pMOS regions are selectively masked, and at least a portion of the first spacers is etched back from the first gate while the pMOS region is masked. 
     According to another aspect of the invention, a method is provided for manufacturing a memory device. The method includes providing a substrate and defining at least two active areas within the substrate, where at least one of said active areas comprises an nMOS region, and at least another of said active areas comprising a pMOS region. A first gate is patterned within the nMOS region and a second gate is patterned within the pMOS region. First disposable spacers are formed on the first gate and second disposable spacers are simultaneously formed on the second gate. The first disposable spacers are trimmed to be smaller than a width of the second disposable spacer. 
     According to another aspect of the invention, a method of fabricating CMOS circuits includes defining field isolation, patterning CMOS gates and conducting complete CMOS transistor doping using six or fewer masks. 
     According to another aspect of the invention, an integrated circuit is provided. The integrated circuit comprises a substrate, an nMOS gate over an n-channel in the substrate, and a pMOS gate over a p-channel in the substrate. The nMOS and pMOS gates have approximately the same widths while the n-channel is shorter than the pMOS channel. 
     According to another embodiment of the invention, a system comprising a CMOS circuit is provided. The CMOS circuit comprises a substrate and a CMOS transistor gate formed integrally with the substrate. Source/drain regions are formed within the substrate near the gate, and lightly doped drain (LDD) regions are formed at least partially between the source/drain regions and the gate. A gap-fill oxide, with a dielectric constant of less than about 3.5 directly contacts sidewalls of the gate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other aspects of the invention will be better understood from the detailed description of the preferred embodiments and from the appended drawings, which are meant to illustrate and not to limit the invention, and in which: 
         FIG. 1  is a flow chart illustrating one process for fabricating CMOS circuits according to a preferred embodiment of the present invention. 
         FIG. 2  illustrates a cross-sectional view of a portion of a memory device within which nMOS and pMOS transistors may be formed according to a preferred embodiment of the present invention. 
         FIG. 3  illustrates a cross-sectional view of the device of  FIG. 2  after a mask step, optional spacer trim in n-channel areas, n+ implant and n-channel enhancements implant. 
         FIG. 4  illustrates a cross-sectional view of the device of  FIG. 3  after spacer removal in n-channel areas, LDD implant and Halo implant. 
         FIG. 5  illustrates a schematic cross-sectional view of the nMOS region of the device of  FIG. 4  after LDD implant and Halo implant. 
         FIG. 6  illustrates a cross-sectional view of the device of  FIG. 4  after a second mask step, optional spacer trim in p-channel areas, p+ implant and p-channel enhancements implant. 
         FIG. 7  illustrates a cross-sectional view of the device of  FIG. 6  after spacer removal in p-channel areas, LDD implant and Halo implant. 
         FIG. 8  illustrates a cross-sectional view of the device of  FIG. 7  after mask removal, low k gap-fill oxide and RTP. 
         FIG. 9  illustrates a schematic cross-sectional view of the nMOS region of the device of  FIG. 8  after dopant activation and consequent diffusion. 
         FIG. 10  is a flow chart illustrating a process for fabricating CMOS circuits in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiments of the present invention are described in a DRAM environment. While the circuit design of these preferred embodiments may be incorporated into any integrated circuit that includes CMOS, such as processors, specialty chips or volatile or non-volatile memory devices, such as DRAM, SRAM, and flash memory, they have particular utility in the integrated circuit memory device context. Of course, larger circuits, computers, devices and systems incorporating the integrated circuits described herein are also contemplated. 
     A process for fabricating one CMOS region, in a memory device and particularly in DRAM according to one embodiment of the present invention, is illustrated in  FIG. 1 , and described in greater detail below.  FIG. 1  shows a flow chart illustrating one preferred process for fabricating a CMOS region. The steps illustrated in this flow chart are preferably performed in the illustrated order; however, as will be understood by those skilled in the art, they may also be performed in other sequences and various substitutions and replacements may be made. In the discussion below, some of the possible substitutions and replacements will be discussed in further detail. The description below simultaneously makes reference to the process flow of  FIG. 1  and the structures shown in  FIGS. 2-8 . 
     A substrate is first provided  100  ( FIG. 1 ). The provided substrate  11  is illustrated in  FIG. 2  after some initial processing (steps  100 - 108  of  FIG. 1 ).  FIG. 2  shows a cross-sectional view of a portion of the periphery of a memory device  10 , wherein the logic of the memory device is generally located. This graphical layout illustrates one pMOS active area and one nMOS active area of logic in the periphery. It will be understood that the integrated circuit includes many such pMOS and nMOS active areas, simultaneously processed on a wafer that will later be diced into chips or dies. Of course, many of these components would be indistinguishable in a purely visual representation, and some of the components shown in  FIG. 2  and subsequent figures are artificially distinguished from other materials in order to highlight their functionality. The memory device  10  is preferably built on and in the substrate  11 , which forms the lowest level of semiconductor material in which electrical devices are formed. The substrate  11  typically comprises silicon, e.g., epitaxial silicon or the upper surface of a silicon wafer. Of course, other suitable materials (e.g., other group III-V elements) may also be used, as is well-known to those skilled in the art. 
     In one embodiment, active areas may then be defined  102  ( FIG. 1 ) in the substrate  11  by field isolation, in the form of shallow trench isolation (STI) in the illustrated embodiment. Preferably, the active areas in both the array and periphery are defined by STI. Typically, a hard mask material (e.g., silicon nitride) is first laid down over the substrate  11 , and a photoresist layer is deposited over the hard mask. Standard photolithographic techniques may then be used to form a pattern of trenches through the photoresist layer, and the hard mask layer may then be anisotropically etched through the patterned photoresist to obtain a plurality of trenches through these top two layers. The photoresist layer may then be removed by conventional techniques, such as by using an oxygen-based plasma. The trenches may then be extended by a selective etch that removes the exposed silicon forming the substrate  11 , thereby forming trenches within the memory device  10 . These trenches are then filled with an insulator, such as an oxide. The insulator may be blanket deposited over the entire memory device  10 , and then the device may be planarized by any of a number of methods, including, for example, chemical-mechanical polishing (“CMP”) stopping on the hard mask. The resulting isolation trenches  12  may be seen in  FIG. 2 , separating the n-channel regions  13   a  from the p-channel regions  13   b . As will be understood by those skilled in the art, step  102  thereby comprehends the use of a first mask (not shown) to define the active areas. 
     As shown in  FIG. 2 , a thin gate dielectric layer  14  may then be formed  103  ( FIG. 1 ) over the active regions of the memory device  10 . This dielectric layer  14  comprises silicon oxide in a preferred embodiment, although other dielectric materials (e.g., high k layers such as Ta 2 O 5 , HfO 2  or ZrO 2 ) may be used. In one embodiment, the dielectric layer  14  is formed by thermal oxidation of the exposed silicon substrate  11 . 
     In a preferred embodiment, the nMOS and pMOS regions in the periphery may then be doped, defining the transistor wells within these regions. As will be well understood by those skilled in the art, in the nMOS regions, a p-well is formed by doping  104  ( FIG. 1 ) the silicon substrate  11  in that region to form a relatively lightly doped p-type semiconductor. In one preferred embodiment, the nMOS regions are doped with boron. Meanwhile, the pMOS regions are doped to form an n-type semiconductor or n-wells. In a preferred embodiment, the pMOS regions are doped with phosphorous. In one preferred process implementation, each of these steps uses one mask, and so two more masks (not shown) are used in step  104  to define the wells. The process of masking may be performed in a number of ways but is preferably performed as described above, using a photoresist layer patterned according to conventional photolithographic techniques. This lithographic pattern can optionally be transferred to a hard mask to expose the surface of the device  10 , thereby opening selected areas of the device  10  for further processing steps, such that the wells may be doped through the masks. After each masking step, the photoresist and any hard mask layers are preferably removed. In addition to doping the wells, these masks can be used for channel enhancement and polysilicon workfunction implants. 
     In another embodiment, (see  FIG. 10  and related description below) the second and third masks can be omitted and well implants can instead be performed at the same time as other doping steps using the fifth and sixth masks (which become the third and fourth masks) described below. 
     Returning to the embodiment of  FIG. 1 , the gates  16  may then be patterned or defined  106  in the periphery using a fourth mask. These gates  16  are formed of a conductive material and initially comprise undoped polysilicon in one preferred embodiment. Preferably the gates in the array (not shown) of the memory device  10  are patterned at a subsequent processing step. In further detail, polysilicon may first be blanket deposited over at least the periphery. Then, by a series of photolithographic steps, the polysilicon may be etched back to the gate dielectric layer  14  except in certain lithographically defined regions, where the polysilicon forms gates  16 . Preferably the polysilicon is blanket deposited over periphery and array (not shown) regions, but is patterned at this stage  106  only over the periphery. This is because the CMOS gates for the illustrated process employ a bare, uncovered polysilicon, whereas memory array gates preferably include strapping metal or silicide and protective capping layers. A separate mask is used at a later stage to pattern gates in the memory array regions after optional metal or silicide and cap layer formation. In other embodiments, the gates  16   a ,  16   b  may be metallic, as will be well understood by those skilled in the art. As will be better understood from the discussion below, the thickness of the polysilicon layer is selected to be greater than or equal to the desired source/drain junction depth. 
     Preferably, the gates  16  in both nMOS and pMOS regions  13   a ,  13   b  have the same width. Preferably, the gate length is less than 0.5 μm, and more preferably 0.1 μm. As will be seen below, despite the fact that the gate widths are the same for both nMOS and pMOS regions, the process described herein can produce effectively different channel lengths by modulating the spacer width rather than the gate width. As illustrated, the gates  16  are patterned without any capping layer, such that the polysilicon remains exposed on top. 
     Disposable spacers  18  ( FIG. 2 ) are then formed  108  ( FIG. 1 ) along the vertical surfaces of the gates  16 . First, a conformal layer of spacer material is deposited to cover the top surface of the memory device  10 . Preferably, the spacer material can be selectively etched with respect to the substrate  11  and the insulator layer  14 , and the substrate  11  and the insulator layer  14  can each be selectively etched with respect to the spacer material. In the illustrated embodiment, the spacer material comprises a relatively low density material, such as a TEOS oxide, such that it can be readily stripped (selectively) at a later stage. Of course, in other embodiments, the spacer material may comprise other well-known spacer materials, such as silicon nitride; however, such materials are less desirable for the disposable spacer function. The spacer material may be deposited using any suitable deposition process, such as, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). 
     After laying the spacer material over the vertical and horizontal surfaces of the memory device  10 , an anisotropic etch is used to preferentially remove the spacer material from the horizontal surfaces in a directional spacer etch. Thus, the spacer material is formed into the disposable spacers  18 , i.e., material extending from the sidewalls of another material. As shown in  FIG. 2 , the spacers  18  are formed along the vertical surfaces of the CMOS gates  16 . In a preferred embodiment, the width of the spacers  18  to which they are initially etched back is approximately the same for what will become both the nMOS and pMOS gates. Thus, no masking step is employed at this stage and the spacers  18  are initially uniformly thick in nMOS and pMOS regions. 
     In one embodiment, a fifth mask is then used to cover  110  ( FIG. 1 ) the pMOS, while exposing the nMOS regions for subsequent processing. This mask  20  is illustrated in  FIG. 3 . Optionally, the spacers  18   a  surrounding the nMOS gates  16   a  may then be partially etched back or trimmed  112  ( FIG. 1 ), narrowing their width W S  as illustrated in  FIG. 3 . As is well understood by those of skill in the art, the spacers for n-channel gates  16   a  are preferably smaller than those for p-channel gates  16   b  because p-channel should be separated from their respective sources and drains by a greater distance, since n-channel implants are less prone to diffusion. The p-channel has an effective channel length that is defined by the width of the gate  16   b  plus approximately two times the width of the spacers  18   b . The n-channel length L C  is more narrow, since it is defined in the illustrated embodiment by an identical gate width plus two times the width of the spacers  18   a , which are trimmed relative to spacers  18   b . Thus the p-channel is preferably between more than 10% greater than the n-channel length. More preferably, the effective p-channel length is 10-30% and most preferably 15-20% longer than the n-channel. 
     For example, in one embodiment, the effective channel length under the p-channel gate  16   b  may be between 600 Å and 800 Å, while the effective channel length under the n-channel gate  16   a  may be between 400 Å and 800 Å. In such an embodiment, the width of the spacers W S , as initially formed, should preferably be sufficient to generate an effective channel length of the nMOS and pMOS gates  16  of at least 800 Å. In a subsequent processing step, the spacers  18   a  surrounding the n-channel gates  16   a  may be etched back to achieve the desired effective channel length of the n-channel. This etch back may be performed by any of a number of conventional methods. 
     At step  114  ( FIG. 1 ), once the spacers  18   a  and n-channel gate  16   a  form an appropriate effective channel length, the source and drain regions  22   a  are implanted using the same mask  20 , as shown in  FIG. 3 . As is known in the art, the source and drain regions in the nMOS will preferably be doped (e.g., with phosphorous) to form an n-type semiconducting region in the p-well. In another embodiment, other elements may be used to dope the substrate  11  in order to form an n-type semiconductor. 
     In the preferred embodiment, because of the location of the spacers  18   a  along the sides of the n-channel gate  16   a , the source and drain regions  22   a  may be created a distance W S  away from the n-channel gate  16   a.    
     The same doping step  114  ( FIG. 1 ) dopes the illustrated exposed nMOS gates  16   a  during this stage of CMOS processing, thus setting the workfunction and differentiating the nMOS gates  16   a  from the pMOS gates  16   b . Thus, with the spacers  18  and mask  20  in place, the entire exposed (unmasked) surface of the periphery of the device  10  may be doped with an n-type semiconductor dopant, thereby defining the nMOS gates  16   a , sources and drains  22   a  in one step. The lack of a capping layer on the gates  16   a  facilitates this simultaneous doping of the gate  16   a  with the source/drain regions  22   a . As noted above, the thickness of the polysilicon layer as deposited is selected to be greater than or equal to the desired junction depth, such that the doping  114  does not penetrate into the channel region, but rather remains within the gate above the gate dielectric. In another embodiment (not shown), the gate can include a barrier layer above the gate dielectric to prevent diffusion or implantation of the gate from reaching the underlying channel. 
     With the same mask  20  in place, the n-channel may also be enhanced during this stage of CMOS processing, step  116 . The n-channel is enhanced with p-type doping, (e.g., boron). This enhancement doping is also commonly called a Taylor implant, and need not be performed for some applications. This step, while performed in the illustrated embodiment with the trimmed spacers  18   a  along the gates  16   a , may instead be performed with the spacers  18  in place, or after complete removal of the spacers  18 / 18   a.    
     With the same mask  20  in place, after completion of the above steps (or before, as discussed above), the spacers  18   a  adjacent the walls of the n-channel gates  16   a  are preferably removed  118  ( FIG. 1 ), as shown in  FIG. 4 . In a preferred embodiment, this removal may be performed by a buffered oxide etch or dip, preferentially removing TEOS without harm to the mask or other exposed structures. Choice of the spacer material relative to surrounding materials facilitates the removal. By this removal, access is achieved to those portions of the substrate  11  previously covered by the width, W S , of the spacers  18   a . Exposed gate oxide may also be removed, though the gate dielectric  14  remains protected under the nMOS gates  16   a  and under the mask  20 . 
     After removal of the disposable spacers  18   a , and with the same mask  20  in place, various doping steps may then be performed in the region between the n-channel gate  16   a  and its source and drain regions  22   a  in supplemental doping steps  120  ( FIG. 1 ), which can also be referred to as source/drain extension or transistor tailoring implants. With reference to  FIG. 5 , in one embodiment, as will be well understood in the art, a lightly doped drain (LDD)  23   a  may be implanted between these structures, on either side of the n-channel gate  16   a . As illustrated in the schematic cross-section of  FIG. 5 , the LDD  23   a  preferably abuts the source and drain regions  22   a  and extends substantially adjacent a top surface of the substrate  11 . In a preferred embodiment, a Halo implant  25   a , or pocket implant, may also be implanted substantially underneath the LDD  23   a  and the n-channel gate  16   a , as illustrated in  FIG. 5 . The Halo implant  25   a  is formed on either side of the gate  16   a  and is more deeply submerged within the substrate  11 . 
     The LDD  23   a  and Halo implants  25   a  may be provided over the entire exposed surface of the periphery of the memory device  10 , but, since these implants are created using much lower doping levels than those used to form the transistor elements, they are “washed out” by the higher doping of previously doped regions, and thus do not change the semiconductor characteristics of these elements. 
     In another preferred embodiment, the spacers  18   a  may not be completely removed in a single step, as disclosed in step  118 . Instead, the spacers  18   a  may be removed in multiple steps. This preferred embodiment enables a grading of the LDD implants  23   a , with lower levels of doping in later steps, as the regions closer to the n-channel gates  16   a  are revealed. In other words, a first portion of the spacers  18   a  may be removed, and a first level of doping may be used to form the LDD implant  23   a . A second portion of the spacers  18   a  may then be removed, and a second level of doping may be used to form the LDD implant  23   a . Preferably, this second level of doping is at a lower level than the first level of doping, such that the doping trails off as the LDD implant  23   a  approaches the gate  16   a . This process may be iterated until the spacers  18   a  are entirely removed, or until the LDD implant  23   a  is completely defined. This may improve the overall performance of the device  10 . 
     Thus, source/drain, enhancement and supplemental (e.g., LDD and Halo) doping for the nMOS regions are all performed using a single mask due to employment of disposable spacers. This is indicated in  FIG. 1  by the dotted box  140 . 
     In step  122  ( FIG. 1 ), the pMOS mask  20  is then removed, and a new, nMOS mask  24  ( FIG. 6 ) created, opening access to the pMOS regions  13   b  of the periphery. This is the sixth mask used in the process described herein. The remaining steps disclosed in  FIG. 1  (steps  124 - 132 ) are illustrated generally in  FIGS. 6 and 7 . As illustrated, these steps are very similar to steps  112 - 120 , discussed above. The major differences are as follows. First, the dopant types are opposite. For example, instead of using dopants to create n-type source/drain regions, p-type semiconductor doping is performed, preferably using boron. Second, as discussed above, the partial etch back or trim of the spacers  18   b  over the p-channel gates  16   b  (step  124 ) will preferably be eliminated or reduced, relative to the pull back described above with respect to the n-channel gates  16   a . In one particular embodiment, the spacers  18  ( FIG. 1 ) may initially be deposited to match the desired effective channel length for the p-channel gates  16   b , and a spacer trim need only be performed on the n-channel gates  16   a . In another embodiment, the spacers  18   b  surrounding the p-channel gates  16   b  will simply be trimmed less than the spacers  18   a  surrounding the n-channel gates  16   a , thereby creating an effective channel length differential between the pMOS and nMOS regions of the device  10 . 
     Thus, gate, source/drain, enhancement and supplemental (e.g., LDD and Halo) doping for the pMOS regions are all performed using a single mask due to employment of disposable spacers. This is indicated in  FIG. 1  by the dotted box  150 . 
     In  FIG. 8 , it may be seen that, after the processing of the respective pMOS and nMOS regions has been completed and after removal of the nMOS mask  24 , traditional processing steps may be performed. In one embodiment, new spacers may be formed, around the various circuit elements in the periphery in order to facilitate the formation of self-aligned contacts. Because of the sequence employed, the spacers can be oxide rather than traditional silicon nitride spacers, which exhibit high parasitic capacitance due to higher permittivity and also introduce stress. 
     More preferably, as illustrated, spacers can be omitted in the final product. Instead, as shown, a low k gap fill oxide  26 , with a permittivity preferably less than about 3.5 and more preferably less than about 3.2, is deposited along the top of the memory device  10  directly over conductive sidewalls of the gates  16 . Preferably the gates  16  comprise silicon, but it is also contemplated that the gates may be formed of other materials or may have a thin conductive coating. 
     With reference now to  FIG. 9 , thereafter the device  10  may undergo annealing (e.g., rapid thermal processing) for dopant activation. This is preferably conducted after forming the gap-fill oxide  26  and can serve to simultaneously densify the oxide  26 . As illustrated, dopant activation also drives the dopants from their original locations. In  FIG. 9 , the original implanted locations of  FIG. 5  are illustrated by dotted lines, and the post-activation positions are indicated by solid lines. It will be understood that the pMOS transistors likewise experience the same activation/dopant diffusion during the anneal. The transistors and other circuit elements of the periphery are thereby defined, and lines may be connected thereto according to other steps well known to those of skill in the art. At this or at earlier stages of wafer processing, the array of the memory device  10  may be defined according to various conventional techniques. 
     Referring again to  FIG. 8 , the resultant CMOS circuit can have one or more of the following distinguishing features. While the CMOS gates  16   a ,  16   b  of the illustrated embodiment have the same width, the channel defined between source and drain regions  22   a ,  22   b  are different, with the p-channel being longer than the n-channel, preferably more than 10% longer, particularly 10-30% and more particularly 15-20% longer on the pMOS side as compared to the nMOS side. A low k gap-fill material directly contacts gate sidewalls, reducing gate-to-drain Miller capacitance. Furthermore, despite the lack of spacers in the illustrated final product, distinct LDD regions are initially formed between source/drain regions and the gate corners (rather than under the gate corners), and later dopant activation (see  FIG. 9 ) cause the LDD to diffuse to the desired location under the gate corners. The resultant device accordingly has a longer life expectancy than LDD formations exclusively formed under the gate. 
     As is evident from the steps described above, the mask count for the preferred process is less than that for conventional CMOS processing, thereby simplifying the process. In particular, six masks are employed in the above-described preferred embodiment for the definition of the CMOS in the periphery. Gate, source/drain and LDD/Halo doping can be performed at the same stage with one mask for each of the nMOS and pMOS regions, rather than two for each region, thus saving two masks. In exchange, one mask is lost by using separate masks to pattern the transistor gates in the periphery and in the memory arrays. 
     With reference now to  FIG. 10 , the well implants can also be performed with the same masks, thus saving another two masks. Thus, from STI definition through completion of CMOS transistor definition in the periphery, the process of  FIG. 1  employs six (6) masks, while the process of  FIG. 9  employs four (4) masks. In  FIG. 10 , similar steps to those of  FIG. 1  are referenced by similar numbers in the 200 range, rather than the 100 range. 
     As will be appreciated by a comparison of  FIG. 1  with  FIG. 10 , the processes are very similar, except that the well doping steps  204   a ,  204   b  are now performed using the same masks used for gate, source/drain, enhancement and supplemental (LDD and Halo) doping. Traditionally, doping of the wells is conducted early in the fabrication process, such that subsequent heat steps can be used to help drive dopants to their ultimately desired depth. However, two factors have recently facilitated doping the wells with the same masks used for source/drain and other doping. The junction depths have become more shallow, and the background doping level (indeed, all doping levels) have increased relatively. Thus, with higher background (well) doping levels, greater crystal faults can be tolerated. Accordingly, state-of-the-art transistor standards enable joinder of well doping with the remaining doping steps for the transistors. Thus, a single mask can be employed for all transistor doping steps for nMOS (see box  240  in  FIG. 10 ) and a single mask for all transistor doping steps for pMOS (see box  250  in  FIG. 10 ). 
     Significantly, the spacers in place during source/drain doping, which define channel length, can be tailored for nMOS versus pMOS regions without additional masks. 
     In addition, the manufacturing efficiency for the above process is improved over conventional techniques because higher dose implants may be used. The performance of the CMOS devices may also be improved, with increased mobility and decreased body-effect, or reduced doping can attain the same device performance, as a result of postponing the enhancement and Halo implants until near the end of the process flow, such that reduced dopant diffusion occurs. The gate-to-drain Miller capacitance is also preferably lowered (resulting in faster circuits) because a densified high k dielectric, such as silicon nitride, need not be used for a spacer. Instead an oxide can be used as a spacer, or only the planarized oxide  26  can insulate, as illustrated. Because logic regions of memory devices are not as crowded as the array regions, contacts formed to source and drain regions need not be self-aligned; rather, the contacts vias can be opened in the planarized oxide  26  in a manner spaced from the conductive gate sidewalls, such that only the low k, gap-fill oxide  26  intervenes between the contact and the sidewalls of the gates  16   a ,  16   b.    
     Of course, the devices may also be made more reliable because of the independent spacer tailoring, and thus tailoring the location of doping, in pMOS versus nMOS devices. The process flow also facilitates subsequent siliciding (or silicidation) of the top of the CMOS gates, indeed all along the silicon line that forms the gates, without opening contacts through cap layers. Silicidation of the source and drain regions of these transistors is also facilitated. 
     While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the novel process for forming the CMOS may be modified a great deal, may have various omissions, substitutions and changes, and many of the steps may be performed in a different order without departing from the spirit of the invention. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.