Patent Publication Number: US-3970828-A

Title: System for precision time measurement

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to time measurement, and more particularly to apparatus for producing signals at the beginning and end of a second time interval larger than, but directly proportional to a first time interval. 
     In the past it has been the practice to develop a digital number proportional to a time interval by counting a clock during a period of interest between a pulse pair. However, when the period of interest approaches the pulse period of the clock, a measurement can be made with little or no accuracy in the first, second and/or third or other significant digits. 
     SUMMARY OF THE INVENTION 
     In accordance with the system of the present invention, the abovedescribed and other disadvantages of the prior art are overcome by &#34;stretching&#34; a first period of time between two successive occurrences so that the &#34;stretched&#34; second period of time is directly proportional to the first period. 
     The above-described and other advantages of the present invention will be better understood from the following detailed description when considered in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings which are to be regarded as merely illustrative: 
     FIG. 1 is a block diagram of a precision time measurement system constructed in accordance with the present invention; and 
     FIG. 2 is a more detailed diagram of a portion of the system shown in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIG. 1, the system of the present invention is illustrated at 10 having input terminals 11 and 12 connected to a control gate 13. 
     The purpose of the invention is to measure, with substantial precision, the time between the occurrences of two pulses P 1  and P 2 . A rectangular wave of a mark-to-space ratio equal to 1:1 is impressed upon input terminal 12. This rectangular wave is illustrated at 14 in FIG. 1. 
     If desired, pulse P 1  may occur during the high level portion 15 of rectangular wave 14, whereas the pulse P 2  may occur somewhere during the low level portion 16 of rectangular wave 14. 
     Responsive to the inputs on terminals 11 and 12, gate 13 produces a rectangular wave output and impresses the same on a ramp generator 17 over a lead 18. this produces an output ramp voltage illustrated at 19 on an output lead 20 of ramp generator 17. The ramp 19 is impressed upon the input of an amplifier 21, the output of which is illustrated at 22. 
     Control gate 13 produces an output pulse on an output lead 22 which is connected to an input lead 23 of a storage circuit 24. Storage circuit 24 is a conventional sample-and-hold circuit which samples the output of amplifier 21 when pulse P 2  occurs. 
     If, as shown in FIG. 1, ramp 19 reaches a voltage v when the pulse P 2  occurs, ramp 22 reaches an amplitude of Kv when pulse P 2  occurs, where K is the gain of amplifier 21. 
     The output of amplifier 21 is impressed upon storage circuit 24 over a lead 25. Storage circuit 24 is reset over a lead 26 connected from an output lead 59 of a one shot multivibrator 32 via a junction 60. 
     Storage circuit 24 supplies a voltage to a coincidence circuit 27 over a lead 28 which thus remains constant at Kv at and after the occurrence of pulse P 2 . The output of ramp generator 17 is also impressed upon coincidence circuit 27 over a lead 29 connected to a junction 30 with lead 20 that is connected from the output of ramp generator 17 to the input of amplifier 21. Ramp 19 thus continues to rise until it becomes equal to the voltage on lead 28, at which point coincidence circuit 27 produces a pulse on an output lead 30 that is connected to an AND gate 31 shown in control gate 13 in FIG. 2. In FIG. 1, one shot multivibrator 32 is then connected from a junction 31 in control gate 13 in FIG. 2 to a reset input lead 33 of ramp generator 17 via junction 60 to reset ramp generator 17 in FIG. 1. A lead 34 is also connected from lead 30 and provides a reset input to control gate 13. 
     Control gate 13 has an output lead 35 which is connected to a counter 36 to reset the same immediately prior to the beginning of the count. 
     Control gate 13 has another output lead 37 connected to counter 36 to supply clock pulses thereto over an appropriate interval. 
     control gate 13 has still another output lead 38 connected to a gating circuit 39 to sample the output of counter 36 when a pulse is impressed upon gating circuit 39 via lead 38. This sample is stored in a storage register 40. The number stored in storage register 40 is then indicated in an indicator 41. 
     Gating circuit 39, storage register 40 and indicator 41 are connected in succession from counter 36, gating circuit 39 receiving the additional actuating input pulse over lead 38. A clock 42 provides an additional input to control gate 13. 
     The output of one shot 32 is also connected to control gate 13 via lead 59, junction 60 and a lead 60&#39;. 
     In FIG. 2, a flip flop 43 is employed in control gate 13. AND gates are provided at 44, 45, 46 and 47 in control gate 13. Each of the AND gates 44, 45, 46 and 47 is provided with two inputs and one output. 
     One of the inputs to AND gate 44 is connected from input terminal 11. The other input to AND gate 44 is connected from input terminal 12 through an inverter 48. 
     AND gate 45 has first and second inputs 49 and 50 connected from terminals 11 and 12, respectively. 
     AND gate 46 has one input connected from junction 31&#39;, and another input connected from a junction 51. 
     The outputs of AND gates 45 and 46 are respectively connected to the set and reset inputs of flip flop 43. 
     Flip flop 43 has an output 52 connected to a junction 53. Junctions 51 and 53 are connected together. Lead 18 is connected from junction 53 to the input of ramp generator 17. 
     AND gate 47 has one input connected from junction 51 and a second input connected from the output of clock 42. 
     The output of AND gate 47 is connected to lead 37. 
     A more detailed construction of storage circuit 24 and coincidence circuit 27 are shown in FIG. 2. In storage circuit 24, an electronic sampling switch 54 is provided that is connected from lead 25 to a junction 55 and operated over lead 26 connected from the output of AND gate 44. A capacitor 56 is connected from junction 55 to ground. A junction 57 is also provided in storage circuit 24. Another electronic switch is provided at 58 and connected from junction 57 to ground. Switch 58 is operated by a pulse appearing at the output of one shot 32. 
     Coincidence circuit 27 includes a differential amplifier 61, an inverter 62 and a differentiator 63 connected in succession in that order from leads 25 and 29 to lead 30. 
     Lead 25 is connected to the noninverting input of differential amplifier 61. The output of ramp generator 17 over lead 29 is connected to the inverting input of differential amplifier 61. 
     Differentiator 63 includes a capacitor 64, a resistor 65 and a diode 66. Differentiator 63 also has junctions 67, 68 and 69. Capacitor 64 is connected from the output of inverter 62 to junction 67. Junctions 67 and 68 are both connected to output lead 30. Resistor 65 is connected between junctions 67 and 69. Diode 66 is connected between junctions 68 and 69, and is poled to be conductive in a direction toward junction 68, junction 69 being grounded. 
     In FIG. 2, lead 35 is connected from a junction 70 with the output lead of AND gate 45. 
     Indicator 41 may be calibrated in units of time. Indicator 41 may be a binary or decimal indicator. Counter 36 with gating circuit 39, storage register 40 and indicator 41 each may be entirely conventional. Moreover, the combination thereof may also be entirely conventional and may be considered to be an updated counter. 
     Although the combination thereof is new, each block shown in FIG. 1, except control gate 13, may be, by itself, entirely conventional. 
     Each of the AND gates 44, 45, 46 and 47 may be entirely conventional. All flip flops and AND gates may be entirely conventional. However, the combination of the AND gates and the flip flops is new. 
     Each component part of storage circuit 24 shown in FIG. 2 may be entirely conventional. Any conventional storage circuit may be employed for storage circuit 24. The storage circuit 24 shown in FIG. 2 is in fact conventional; however, the combination of the storage circuit 24 in FIGS. 1 and 2 with the other components shown therein is new. 
     Any conventional coincidence circuit may be employed for coincidence circuit 27 shown in FIGS. 1 and 2. The combination of coincidence circuit 27 with the other components is new; however, each of the component parts and the combination thereof shown in the dotted block 27 in FIG. 2 may be old in the art. Differential amplifier 61 may be entirely conventional. The same is true of inverter 62 and differentiator 63. 
     OPERATION 
     In the operation of the system of the present invention illustrated in FIGS. 1 and 2, when a pulse P 1  is impressed upon terminal 11, AND gate 45 sets flip flop 43, and the 1 output of flip flop 43 is raised to a high level and impressed over lead 18 on ramp generator 17. Ramp 19 in FIG. 1 is then generated during the rectangular wave on lead 18 and started on the occurrence of pulse P 1 . The same thing is true of ramp 22. However, the output of AND gate 44 causes the output of amplifier 21 to be sampled and held by capacitor 56 on the occurrence of pulse P 2 . This sampled voltage is then applied to the noninverting input of amplifier 61 in coincidence circuit 27. After sampling, the voltage upon the input lead 25 to coincidence circuit 27 therefore remains constant for a certain time interval during which the output amplitude of ramp generator 17 on lead 20 increases as at 19 and is impressed upon coincidence circuit 27 over lead 29. 
     When the amplitude on ramp 19 becomes equal to the sampled amplitude (constant) on input lead 25 of coincidence circuit 27, coincidence circuit 27 produces an output pulse on lead 30 which transfers the count in counter 36 to storage register 40 and via AND gates 31 and 46 resets flip flop 43. AND gate 31 is disabled by a flip flop 13&#39; from reset by one shot 32 to the occurrence of P 2 . AND gate 31 is enabled by flip flop 13&#39; from the occurrence of P 2  to an output from one shot 32. 
     As shown in FIG. 2, junction 31&#39; is connected from the output of AND gate 31 to leads 38, 39&#39;  and 40&#39; connected to gating circuit 39, one shot 32, and AND gate 46, respectively. 
     During the time that the 1 output of flip flop 43 is high, AND gate 47 passes the output pulses of clock 42 to counter 36. The count in counter 36, upon the production of the reset pulse on output lead 30 of coincidence circuit 27, is thus directly proportional to the time during which the 1 output of flip flop 43 is high. This is also directly proportional to the time interval between the occurrences of pulses P 1  and P 2 . 
     Indicator 41 thus can indicate, by calibration or without, in many conventional ways, a time directly proportional to the time interval between pulses P 1  and P 2  or equal to such time in seconds or in a fraction of a second. 
     A typical value for K would be K = 1,000. 
     The present invention may be used in a great many ways. For example, P 1  may be the transmitted pulse and P 2  may be the reflected pulse in a monopulse radar. The time measurement described hereinbefore may thus be directly proportional to slant range, and indicator 41 may be calibrated in miles or other linear measure. 
     The system of the present invention may also be employed in automatic or other ground controlled approach radar systems, in a process controller or otherwise.