Patent Publication Number: US-2023133322-A1

Title: Semiconductor package and method of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2021-0148489, filed on Nov. 2, 2021 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety. 
     TECHNICAL FIELD 
     Embodiments of the present inventive concept are directed to a semiconductor package and a method of manufacturing the same. 
     DISCUSSION OF THE RELATED ART 
     A semiconductor package mounted on an electronic device is miniaturized to have high performance and high capacity. To accomplish these aims, semiconductor packages in which semiconductor chips that include a through-silicon-via (TSV) are vertically stacked are being studied. 
     SUMMARY 
     An embodiment of the present inventive concept provides a semiconductor package that has a simplified manufacturing process and an increased yield, and a method of manufacturing the same. 
     According to an embodiment of the present inventive concept, a semiconductor package includes a first semiconductor chip that includes a first front surface on which first front surface pads of first and second groups are disposed; a second semiconductor chip that includes a second front surface that faces the first front surface and on which are disposed second front surface pads that are electrically connected to the first front surface pads of the second group, and a second rear surface opposite to the second front surface and on which are disposed second rear surface pads of first and second groups, and a through-electrode that electrically connects the second front surface pads and at least a portion of the second rear surface pads to each other; first bump structures that include a stud portion disposed below the second rear surface pads of the first group, and a bonding wire portion that extends from the stud portion and is connected to the first front surface pads of the first group; second bump structures disposed below the second rear surface pads of the second group; an encapsulant that encapsulates the second semiconductor chip and the first and second bump structures; and a redistribution structure disposed below the encapsulant, where the redistribution structure includes an insulating layer, redistribution layers disposed below the insulating layer, and redistribution vias that penetrate through the insulating layer and connect the redistribution layers to the first bump structures or the second bump structures. At least a portion of the redistribution vias connected to the first bump structures is in contact with the stud portion. 
     According to an embodiment of the present inventive concept, a semiconductor package includes a first semiconductor chip that includes first front surface pads of first and second groups; a second semiconductor chip that includes second front surface pads disposed below the first semiconductor chip and that are electrically connected to the first front surface pads of the second group, and second rear surface pads of first and second groups located opposite to the second front surface pads; first bump structures that include a stud portion disposed below the second rear surface pads of the first group, and a bonding wire portion that extends from the stud portion and is connected to the first front surface pads of the first group; and a redistribution structure disposed below the second semiconductor chip, where the redistribution structure includes redistribution layers that are electrically connected to the first and second semiconductor chips. The first front surface pads of the first group are electrically connected to the redistribution layers through the first bump structures. 
     According to an embodiment of the present inventive concept, a semiconductor package includes a first semiconductor chip that includes first pads of first and second groups; a chip structure that includes second upper pads disposed below the first semiconductor chip and that are electrically connected to the first pads of the second group, and second lower pads of first and second groups located opposite to the second upper pads; first bump structures that include a stud portion disposed below the second lower pads of the first group, and a bonding wire portion that extends from the stud portion and is connected to the first pads of the first group; second bump structures disposed below the second lower pads of the second group; and a redistribution structure disposed below the chip structure, where the redistribution structure includes redistribution layers that are electrically connected to the first and second bump structures. 
     According to an embodiment of the present inventive concept, a method of manufacturing a semiconductor package, includes forming a first semiconductor wafer that includes a first front surface and a first rear surface that are opposite to each other, and first front surface pads of first and second groups that are disposed on the first front surface; forming at least one second semiconductor chip that includes a second front surface and a second rear surface that are opposite to each other, second rear surface pads of first and second groups that are disposed on the second rear surface, and conductive posts that are disposed on the second rear surface pads of the second group; attaching the at least one second semiconductor chip onto the first semiconductor wafer such that the second front surface faces the first front surface; forming a bonding wire that electrically connects the first front surface pads of the first group and the second rear surface pads of the first group, and forming a stud bump on the second rear surface pads of the first group; forming a preliminary encapsulant that encapsulates the at least one second semiconductor chip, the bonding wire, and the stud bump, on the first semiconductor wafer; performing a polishing process that forms an encapsulant from which a portion of the preliminary encapsulant is removed, forms first bump structures that includes a stud portion from which a portion of the stud bump is removed, and forms second bump structures from which a portion of the conductive posts is removed, where the first and second bump structures are exposed through an upper surface of the encapsulant; and forming a redistribution structure on the upper surface of the encapsulant, where the redistribution structure comprises redistribution layers that are electrically connected to the first bump structures or the second bump structures. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1 A  is a cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept,  FIG.  1 B  is a plan view of  FIG.  1 A , taken along line I-I′, and  FIG.  1 C  is a partially enlarged view of portion ‘A’ of  FIG.  1 A . 
         FIG.  2 A  is a partially enlarged view of portion ‘B’ of  FIG.  1 A , and  FIG.  2 B  is a partially enlarged view illustrating a modified example of portion ‘B’ of  FIG.  1 A . 
         FIG.  3    is a partially enlarged view of a region of a semiconductor package according to an embodiment of the present inventive concept. 
         FIG.  4 A  is a cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept, and  FIG.  4 B  is a partially enlarged view of portion ‘C’ of  FIG.  4 A . 
         FIG.  5    is a cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept. 
         FIG.  6    is a cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept. 
         FIGS.  7 A to  7 C  are cross-sectional views that schematically illustrate a process of manufacturing a second semiconductor chip of  FIG.  1 A . 
         FIGS.  8 A to  8 D  are cross-sectional views that schematically illustrate a process of manufacturing a semiconductor package of  FIG.  1 A . 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, embodiments of the present inventive concept will be described with reference to the accompanying drawings. 
       FIG.  1 A  is a cross-sectional view of a semiconductor package  1  according to an embodiment of the present inventive concept,  FIG.  1 B  is a plan view of  FIG.  1 A , taken along line I-I′, and  FIG.  1 C  is a partially enlarged view of portion ‘A’ of  FIG.  1 A . 
     Referring to  FIGS.  1 A to  1 C , a semiconductor package  1  according to an embodiment includes a first semiconductor chip  100 , at least one second semiconductor chip  200 A or  200 B, first and second bump structures  310  and  320 , an encapsulant  410 , and a redistribution structure  510 . According to an embodiment of the present inventive concept, the first semiconductor chip  100  has a first width, the at least one second semiconductor chip  200 A or  200 B has a second width, narrower than the first width, and the redistribution structure  510  is stacked in a vertical or thickness direction (a Z-axis direction), and the first semiconductor chip  100  and the redistribution structure  510  are connected using a bonding wire and a stud bump to reduce process challenges and manufacturing cost. When a metal post is formed between the first semiconductor chip  100  and the redistribution structure  510 , a yield may decrease, and a manufacturing cost may increase. For example, since forming a metal post to a certain height, such as 100 µm, or more is challenging, and the possibility of generating defects, such as misalignment increases in a high-temperature process, such as about 300° C. or higher, due to deformation of the metal post , when the first semiconductor chip  100  and the redistribution structure  510  are connected using a metal post, a manufacturing cost may increase and a yield may decrease. In an embodiment of the present inventive concept, by introducing the first bump structure  310  that replaces the metal post, a connection state between the first semiconductor chip  100  and the redistribution structure  510  can be stably maintained and a yield can be increased even in a high-temperature process. 
     Hereinafter, each component of the semiconductor package  1  according to an embodiment will be described. 
     The first semiconductor chip  100  includes a first rear surface BS1 and a first front surface FS 1 , opposite to each other, and further includes a first substrate  110 , a first circuit layer  120 , and first connection pads  131  and  132 . Although the drawings show that the first front surface FS 1  is provided by the first circuit layer  120 , embodiments are not necessarily limited thereto, and in an embodiment, the first front surface FS 1  may be provided by a separate insulating material layer stacked below the first circuit layer  120 , such as an embodiment shown in  FIG.  4 A . 
     The first substrate  110  is a semiconductor wafer that may include a semiconductor element such as silicon or germanium, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first substrate  110  includes an active surface, such as a surface that faces the first circuit layer  120 , that includes an active region doped with impurities, and an inactive surface opposite to the active surface. Although  FIG.  1 A  shows an upper surface of the first substrate  110  as being the first rear surface BS1 of the first semiconductor chip  100 , embodiments are not necessarily limited thereto, an in an embodiment, a protective layer that provides the first rear surface BS1 of the first semiconductor chip  100  is formed on the first substrate  110 . The protective layer is made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, but, according to an embodiment, is also made of an insulating polymer. 
     The first circuit layer  120  is disposed on a lower surface of the first substrate  110 , and includes an interlayer insulating layer  121  and a wiring structure  125 . The interlayer insulating layer  121  includes at least one of flowable oxide (FOX), tonen silazen (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilaca glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PETEOS), fluoride silicate glass (FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX), or flowable CVD (FCVD) oxide, or a combination thereof. At least a portion of the interlayer insulating layer  121  that surrounds the wiring structure  125  is a low dielectric layer. The interlayer insulating layer  121  may be formed using a chemical vapor deposition (CVD) process, a flowable-CVD process, or a spin coating process. The wiring structure  125  is a multi-layer structure that includes a via and a wiring pattern that includes, for example, one of aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), or tungsten (W), or a combination thereof. A barrier layer that includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the wiring pattern and/or the via and the interlayer insulating layer  121 . Individual devices  115  that constitute an integrated circuit are disposed on the lower surface of the first substrate  110 , or an active surface thereof. The wiring structure  125  is electrically connected to the individual devices  115  by an interconnection portion  113 , such as a contact plug. The individual devices  115  may include an FET such as a planar FET or a FinFET, a memory device such as a flash memory, a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, an FeRAM, or an RRAM, a logic device such as an AND, an OR, or a NOT, etc., or various active and/or passive components such as a system LSI, a CIS, or an MEMS. 
     The first connection pads  131  and  132  are disposed on the first front surface FS 1  of the first semiconductor chip  100  and include first front surface pads  131  of a first group and first front surface pads  132  of a second group,. Since having the first circuit layer  120  and a second circuit layer  220  face each other shortens a signal transmission path, although the first connection pads  131  and  132  are illustrated as front surface pads disposed below the first front surface FS 1 , embodiments of the present inventive concept are not necessarily limited thereto. According to an embodiment, the first semiconductor chip  100  is disposed such that the first rear surface BS1 faces the second semiconductor chips  200 A and  200 B, and the first connection pads  131  and  132  are rear surface pads disposed below the first rear surface BS1. 
     The first front surface pads  131  of the first group and the first front surface pads  132  of the second group are connection terminals that are each electrically connected to the wiring structure  125  of the first circuit layer  120 . The first front surface pads  131  of the first group and the first front surface pads  132  of the second group include any one of copper (Cu), nickel (Ni), titanium (Ti), aluminum (Al), gold (Au), or silver (Ag), or an alloy thereof. The first front surface pads  131  of the first group do not overlap the second semiconductor chips  200 A and  200 B in (the Z-axis direction, perpendicular to the first front surface FS 1 . The first front surface pads  132  of the second group overlap the second semiconductor chips  200 A and  200 B in the Z-axis direction. For example, the first front surface pads  132  of the second group face second front surface pads  231  of the second semiconductor chips  200 A and  200 B, and are electrically connected to the second front surface pads  231  through a separate electrical connection member, such as a conductive bump, or may be in direct contact with and connected to the second front surface pads  231 , as shown in an embodiment of  FIG.  4 A . The first front surface pads  131  of the first group are electrically connected through a first bump structure  310  to portions of second rear surface pads, hereinafter, second rear surface pads  251  of a first group, located on a lower level from the second front surface pads  231 . The first bump structure  310  includes a stud portion  312  and a bonding wire portion  311 . 
     The second semiconductor chip  200 A or  200 B has a second rear surface BS 2  and a second front surface FS 2 , opposite to each other, and includes a second substrate  210 , a second circuit layer  220 , second front surface pads  231 , a through-electrode  240 , a second wiring layer  250 , and second rear surface pads  251  and  252 . The second semiconductor chips  200 A and  200 B are horizontally separated and disposed below the first semiconductor chip  100 . According to an embodiment, the number of second semiconductor chips may be less than or greater than those illustrated in the drawings. In addition, according to an embodiment, a plurality of second semiconductor chips that are stacked in the Z-axis direction are disposed below the first semiconductor chip  100 , as shown in an embodiment of  FIG.  5   . For example, in an embodiment, the first semiconductor chip  100  and the second semiconductor chips  200 A and  200 B are a chiplet that constitutes a multi-chip module (MCM). For example, in an embodiment, the first semiconductor chip  100  and the second semiconductor chips  200 A and  200 B may include a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an I/O chip, or a memory chip such as a DRAM, an SRAM, a PRAM, an MRAM, an FeRAM, or an RRAM, or the like, respectively. The second substrate  210  and the second circuit layer  220  have the same or similar characteristics as the first substrate  110  and the first circuit layer  120  described above, components corresponding to each other may be denoted by similar reference numerals, and repeated descriptions thereof may be omitted. Although the drawings show the second circuit layer  220  of the second semiconductor chips  200 A and  200 B as facing the first semiconductor chip  100 , embodiments are not necessarily limited thereto, and in an embodiment, the second wiring layer  250  faces the first semiconductor chip  100 . 
     The second front surface pads  231  are connection terminals disposed on the second front surface FS 2  that faces the first front surface FS 1  of the first semiconductor chip  100 , and are electrically connected to a second wiring structure  225  of the second circuit layer  220 . Although the drawings show the second front surface pads  231  as being disposed on the second front surface FS 2 , embodiments are not necessarily limited thereto, and in an embodiment, the second front surface pads  231  provide the flat second front surface FS 2 , together with the insulating material layer on the second circuit layer  220 , as shown in  FIG.  4 A . 
     The second front surface pads  231  are electrically connected to first front surface pads  132  of the second group, which face each other, through third bump structures  330 . The third bump structures  330  are disposed between the first front surface FS 1  of the first semiconductor chip  100  and the second front surface FS 2  of the second semiconductor chips  200 A and  200 B. In addition, an adhesive film  335  that surrounds the third bump structures  330  is interposed between the first front surface FS 1  of the first semiconductor chip  100  and the second front surfaces FS 2  of the second semiconductor chips  200 A and  200 B. The third bump structure  330  may be a solder ball, or may be a structure in which a conductive post and a solder ball are combined. The adhesive film  335  may be a non-conductive film (NCF), but is not necessarily limited thereto, and may include, for example, one of various types of polymer films that can survive a thermal compression process. 
     The second front surface pads  231  are electrically connected to at least a portion of the second rear surface pads  251  and  252  through the through-electrode  240 . The through-electrode  240  penetrates through the second substrate  210  and electrically connects the second front surface pads  231  to at least a portion of the second rear surface pads  251  and  252 , located opposite thereto. The through-electrode  240  includes a via plug  245  and a side insulating layer  241  that surrounds the side surfaces of the via plug  245 . The side insulating layer  241  electrically separates the via plug  245  from the second substrate  210 . The via plug  245  includes, for example, at least one of tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed by a plating process, a PVD process, or a CVD process. The side insulating layer  241  includes a metal compound such as tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN), and may be formed by a PVD process or a CVD process. 
     The second wiring layer  250  is disposed on a lower surface of the second substrate  210  and provides the second rear surface BS 2 . The second wiring layer  250  includes a rear surface interlayer insulating layer  253 , shown in  FIG.  2 A , and a rear surface wiring structure  255 , also shown in  FIG.  2 A . This has the same or similar characteristics to the interlayer insulating layer  121  and the wiring structure  125  of the first circuit layer  120  described above, and a repeated description thereof may be omitted. 
     The second rear surface pads  251  and  252  include second rear surface pads  251  of a first group and second rear surface pads  252  of a second group that are disposed on the second rear surface BS 2 . The second rear surface pads  251  of the first group are disposed adjacent to an edge  200   ed , shown in  FIG.  1 B , of the second semiconductor chips  200 A and  200 B, and are electrically isolated from the second rear surface pads  252  of the second group. The second rear surface pads  251  of the first group are electrically connected to redistribution layers  512  of the redistribution structure  510  through the first bump structure  310 . The second rear surface pads  252  of the second group are electrically connected to the redistribution layers  512  of the redistribution structure  510  through the second bump structures  320 . According to an embodiment of the present inventive concept, the stud portion  312  is formed on the second rear surface pads  251  of the first group, and the stud portion  312  is connected to a redistribution via  513  of the redistribution structure  510 , that shortens a signal transmission distance between the first semiconductor chip  100  and the redistribution layers  512 . For example, the signal of the first semiconductor chip  100  that reaches the stud portion  312  through the bonding wire portion  311  is transmitted to an external connection terminal  520  through the redistribution layer  512 , without going through the rear surface wiring structure  255 , shown in  FIG.  5 A , of the second wiring layer  250  and the second bump structure  320 . 
     The first bump structures  310  includes a stud portion  312  disposed below the second rear surface pads  251  of the first group, and a bonding wire portion  311  that extends from the stud portion  312  and is connected to the first front surface pads  131  of the first group. The stud portion  312  and the bonding wire portion  311  may be integrally formed, and may be made of the same material. The stud portion  312  and the bonding wire portion  311  include at least one of gold (Au), silver (Ag), lead (Pb), aluminum (Al), or copper (Cu), or an alloy thereof, but embodiments of the present inventive concept are not necessarily limited thereto. The stud portion  312  includes an exposed surface that is not covered by the encapsulant  410  and that contacts the redistribution via  513 . For example, the stud portion  312  includes a lower surface  310 BS, shown in  FIG.  2 A , or an exposed surface that is exposed through the encapsulant  410 . A diameter ‘D1, shown in  FIG.  1 B , of the exposed or lower surface of the stud portion  312  is substantially equal to a diameter D 2 , shown in  FIG.  1 B , of an exposed or lower surface of the second bump structure  320  exposed through the encapsulant  410 . In this case, “substantially equal” means that a diameter is not intentionally designed differently and that a process error may have occurred. The diameter D 1  of the exposed or lower surface of the stud portion  312  is about 20 µm or more or about 30 µm or more. For example, the diameter D 1  of the exposed or lower surface of the stud portion  312  may range from about 20 µm to about 80 µm, from about 30 µm to about 70 µm, or from about 40 µm to about 60 µm, etc.. When the diameter D 1  of the exposed or lower surface of the stud portion  312  is less than about 20 µm, forming the redistribution via  513  may be challenging. The diameter D 1  of the exposed or lower surface of the stud portion  312  is determined according to a condition of process, such as photolithography process, that forms the redistribution via  513 , and is not necessarily limited to the above-mentioned numerical values. 
     The second bump structures  320  are disposed below the second rear surface pads  252  of the second group, and are directly connected to the redistribution via  513 . The second bump structures  320  include a different type of metal from the first bump structures  310 . For example, the second bump structures  320  include copper (Cu) or an alloy of copper (Cu), but embodiments of the present inventive concept are not necessarily limited thereto. A shape of the second bump structures  320  differs from that of the first bump structures  310 , which will be described below with reference to  FIG.  2 A . 
     The encapsulant  410  is disposed below the first semiconductor chip  100 , and encapsulates the second semiconductor chips  200 A and  200 B, and the first and second bump structures  310  and  320 . The encapsulant  410  surrounds a side surface of the stud portion  312  of the first bump structures  310  and side surfaces of the second bump structures  320 , and a lower surface of the encapsulant  410  is coplanar with a lower surface of the stud portion  312  and lower surfaces of the second bump structures  320 . The encapsulant  410  includes, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a prepreg that includes an inorganic filler and/or glass fiber, ABF, FR-4, BT, or EMC, etc. 
     The redistribution structure  510  is disposed below the encapsulant  410  and the second semiconductor chips  200 A and  200 B, and includes an insulating layer  511 , redistribution layers  512 , and redistribution vias  513 . The insulating layer  511  includes an insulating resin. The insulating resin includes at least one of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with inorganic fillers and/or glass fibers in these resins, such as prepreg, ABF, FR-4, BT, or a photosensitive resin such as a photo-imageable dielectric (PID). The insulating layer  511  may include a plurality of insulating layers  511  stacked in a vertical direction. Depending on a process, a boundary between the plurality of insulating layers  511  may be unclear. 
     The redistribution layers  512  are disposed below the insulating layer  511 , and are electrically connected to the first semiconductor chip  100  and the second semiconductor chips  200 A and  200 B. The redistribution layers  512  include, for example, a metal that includes at least one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or titanium (Ti), or an alloy thereof. The redistribution layers  512  include, for example, a ground pattern, a power pattern, and a signal pattern. For example, the lowermost layers of redistribution layers  512  are thicker than redistribution layers  512  disposed thereon to form a reliable connection with an external connection terminal  520 . The external connection terminal  520  includes a low-melting-point metal, such as tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), or lead (Pb), or an alloy containing them, such as Sn—Ag—Cu, etc., and may have a spherical or ball-like shape. 
     The redistribution vias  513  penetrate through the insulating layer  511  and electrically connect the redistribution layers  512  to the first bump structure  310  or the second bump structure  320 . In particular, at least a portion of the redistribution vias  513  connected to the first bump structure  310  is in direct contact with the stud portion  312 . Therefore, a connection path between the first front surface pads  131  of the first group and the redistribution layer  512  is minimized. The redistribution vias  513  include a metal similar to that of the redistribution layers  512 . The redistribution vias  513  have a filled via shape into which a metal is filled or a conformal via shape into which a metal material is formed along an inner wall of a via hole. The redistribution vias  513  may be integrally formed with the redistribution layers  512 , but embodiments of the present inventive concept are not necessarily limited thereto. 
     Hereinafter, structures of the first bump structures  310  and the second bump structures  320  will be described in more detail with reference to  FIGS.  2 A and  2 B . 
       FIG.  2 A  is a partially enlarged view of portion ‘B’ of  FIG.  1 A , and  FIG.  2 B  is a partially enlarged view of a modified example of portion ‘B’ of  FIG.  1 A . 
     Referring to  FIG.  2 A , in a semiconductor package  1  according to an embodiment, the stud portions  312  of the first bump structures  310  have a height H 1  in a Z-axis direction perpendicular to the second rear surface BS 2  that is substantially equal to a height H 2  of the second bump structures  320 . For example, the second rear surface pads  251  of the first group and the second rear surface pads  252  of the second group are formed in the same process and have substantially the same height, and the stud portion  312  and the second bump structures  320  respectively disposed therebelow are also formed by a polishing process, described with reference to  FIG.  8 C , to have substantially the same height. In addition, a lower surface  310 BS of the stud portion  312 , a lower surface  320 BS of the second bump structures  320 , and a lower surface  410 BS of the encapsulant  410 , formed by the polishing process, are substantially coplanar. 
     The first bump structures  310  and the second bump structures  320  are formed by different manufacturing processes. For example, the first bump structures  310  are integrally formed with the bonding wire portion  311  by a wire bonding process using a capillary  30 , shown in  FIG.  8 B , and the second bump structures  320  are formed by a plating process that uses a photoresist. Therefore, the stud portion  312  of the first bump structures  310  has a post shape or a coin-shape, in which a side surface is convexly rounded in a horizontal direction, such as an X-direction, and the second bump structures  320  has a post shape with flat side surfaces, for example, surfaces that are not convexly rounded in a horizontal direction. For example, the second bump structures  320  include a conductive post. For example, the stud portion  312  have a maximum width W 1  in a horizontal direction, such as the X-axis and Y-axis directions that are parallel to the second rear surface BS 2 , that is greater than a maximum width W 2  of the second bump structures  320 . 
     As described above, due to the stud portion  312  that is integrally formed with the bonding wire portion  311 , an electrical path that connects the first front surface pads  131  of the first group of the first semiconductor chip  100  to the redistribution layers  512  or the redistribution vias  513  of the redistribution structure  510  can be secured without passing through a rear surface wiring structure  255  of the second semiconductor chips  200 A and  200 B. The second rear surface pads  251  of the first group on which the stud portion  312  is disposed are electrically connected to the through-electrode  240  through the rear surface wiring structure  255 . Signals from the second semiconductor chips  200 A and  200 B can be transmitted to the redistribution layers  512  through the through-electrode  240  and the stud portion  312 . 
     Referring to  FIG.  2 B , in an embodiment, in a semiconductor package 1a of a modified example, second rear surface pads  251  of a first group on which a stud portion  312  is disposed are electrically insulated from a rear surface wiring structure  255  and a through-electrode  240 . Regardless of the second semiconductor chips  200 A and  200 B, an electrical path connected from first front surface pads  131  of a first group of a first semiconductor chip  100  to redistribution layers  512  or redistribution vias  513  of a redistribution structure  510  can be secured by the stud portion  312 . 
       FIG.  3    is a partially enlarged view of a region of a semiconductor package  1 A according to an embodiment of the present inventive concept.  FIG.  3    illustrates a region in which a first bump structure  310  is illustrated, in portion ‘B’ of  FIG.  1 A . 
     Referring to  FIG.  3   , a semiconductor package  1 A of an embodiment has the same or similar characteristics as those described with reference to  FIGS.  1 A to  2 B , except that a stud portion  312  is formed of a plurality of stud layers. For example, first bump structures  310  according to a present embodiment includes a first stud layer  312   a  and a second stud layer  312   b  that are stacked between second rear surface pads  251  of a first group and redistribution vias  513 . One of the first stud layer  312   a  or the second stud layer  312   b  is integrally formed with a bonding wire portion  311 . The first stud layer  312   a  has a coined shape, and the second stud layer  312   b  has a coined shape, or may have a polished surface that faces the redistribution vias  513 . The coin-shape is created, for example, by compressing a stud layer using a flat piece of silicon. The first stud layer  312   a  and the second stud layer  312   b  are separated by an interface therebetween. According to a present embodiment, since a contact area between the first stud layer  312   a  and the second rear surface pads  251  of the first group increases, connection reliability and structural stability of the stud portion  312  is secured. Depending on an embodiment, the stud portion  312  includes a greater number of stud layers than those illustrated in the drawings. 
       FIG.  4 A  is a cross-sectional view of a semiconductor package  1 B according to an embodiment of the present inventive concept, and  FIG.  4 B  is a partially enlarged view of portion ‘C’ of  FIG.  4 A . 
     Referring to  FIGS.  4 A and  4 B , a semiconductor package  1 B according to an embodiment further includes a first insulating layer  133  that provides a first front surface FS 1  of a first semiconductor chip  100 , and a second insulating layer  233  that provides a second front surface FS 2  of second semiconductor chips  200 A and  200 B. The first insulating layer  133  is disposed below a lower surface  120 BS of a first circuit layer  120  and surrounds first front surface pads  131  and  132 , and the second insulating layer  233  is disposed on an upper surface  220 US of a second circuit layer  220  and surrounds second front surface pads  231 . In a present embodiment, the first front surface FS 1  is a flat surface provided by the first insulating layer  133  and the first front surface pads  131  and  132 , and the second front surface FS 2  is a flat surface provided by the second insulating layer  233  and the second front surface pads  231 . The first front surface FS 1  and the second front surface FS 2  are in contact with and coupled to each other and form a so-called direct bonding or hybrid bonding structure. The semiconductor package  1 B of a present embodiment has the same or similar characteristics as those described with reference to  FIG.  1 A  to 3, except that the first semiconductor chip  100  and the second semiconductor chips  200 A and  200 B are directly bonded to each other. The first insulating layer  133  and the second insulating layer  233  each include a material that can be bonded to the other, such as silicon oxide (SiO) or silicon carbonitride (SiCN). According to a present embodiment, a connection path between the first semiconductor chip  100  and the second semiconductor chip  200 A and  200 B is shortened, and a thickness of the semiconductor package  1 B is reduced. 
       FIG.  5    is a cross-sectional view of a semiconductor package  1 C according to an embodiment of the present inventive concept. 
     Referring to  FIG.  5   , a semiconductor package  1 C according to an embodiment has the same or similar characteristics as those described with reference to  FIGS.  1 A to  4 B , except that the semiconductor package  1 C includes at least one chip structure  200  disposed below a first semiconductor chip  100  that includes a plurality of second semiconductor chips  200 A,  200 B, and  200 C. For example, the first semiconductor chip  100  may be a logic chip that includes at least one of a CPU, a GPU, an FPGA, an application process (AP), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, or an application-specific integrated circuit (ASIC), etc., and the plurality of second semiconductor chips  200 A,  200 B, and  200 C may be memory chips such as a DRAM, an SRAM, a PRAM, an MRAM, an FeRAM, or an RRAM. 
     The first semiconductor chip  100  has a first surface S 1  and a second surface S 2  that are opposite to each other, and includes first pads  130 P 1  of a first group and first pads  130 P 2  of a second group disposed below the second surface S 2 . 
     The chip structure  200  has a third surface S 3  and a fourth surface S 4  that are opposite to each other, and includes second upper pads  230 P a  disposed on the third surface S 3  that faces the first semiconductor chip  100 , and second lower pads  230 P b   1  of a first group and second lower pads  230 P b   2  of a second group that are disposed below the fourth surface S 4  opposite to the second upper pads  230 P a . 
     The second upper pads  230 P a  are electrically connected to the first pads  130 P 2  of the second group through a separate electrical connection member, such as a conductive bump, or are in direct contact with and connected to the first pads  130 P 2  of the second group, as shown in an embodiment of  FIG.  4 A . 
     The second lower pads  230 P b   1  of the first group are electrically connected to the first pads  130 P 1  of the first group and redistribution vias  513  or redistribution layers  512  of a redistribution structure  510  through first bump structures  310 . The second lower pads  230 P b   2  of the second group are electrically connected to the redistribution vias  513  or redistribution layers  512  of the redistribution structure  510  through second bump structures  320 . 
     The second upper pads  230 P a  are provided by second front surface pads  231  of an uppermost second semiconductor chip  200 C of the plurality of second semiconductor chips  200 A,  200 B, and  200 C, and the second lower pads  230 P b   1  of the first group and the second lower pads  230 P b   2  of the second group are provided by second rear surfaces pads  251  and  252  of a lowermost second semiconductor chip  200 A of the plurality of second semiconductor chips  200 A,  200 B, and  200 C, respectively. 
     The chip structure  200  of a present embodiment has a height in a vertical direction at which a metal post that connects the first pads  130 P 1  of the first group and the redistribution layers  512  might not be formed. For example, a height from the first surface S 1  to the second surface S 2  of the first semiconductor chip  100  is less than a height from the third surface S 3  to the fourth surface S 4  of the chip structure  200 . In addition, a height H 3  from the second surface S 2  of the first semiconductor chip  100  to the fourth surface S 4  of the chip structure  200  is about 100 µm or more. For example, the height H 3  from the second surface S 2  to the fourth surface S 4  may range from about 100 µm to about 1 mm, from about 200 µm to about 1 mm, from about 300 µm to about 1 mm, or from about 300 µm to about 900 µm. As described above, according to a present embodiment, an electrical connection path of about 100 µm or more can be formed using the first bump structures  310  to increase process reliability and yield. 
       FIG.  6    is a cross-sectional view of a semiconductor package  1 D according to an embodiment of the present inventive concept. 
     Referring to  FIG.  6   , a semiconductor package  1 D according to an embodiment has the same or similar characteristics as those described with reference to  FIG.  1 A  to 5, except that a wiring substrate  600  and a heat dissipation structure  630  are further included. 
     A wiring substrate  600  is a support substrate on which a package structure that includes a first semiconductor chip  100 , second semiconductor chips  200 A and  200 B, a first bump structure  310 , a second bump structure  320 , a redistribution structure  510 , etc., is mounted, and is a substrate for a semiconductor package such as a printed circuit board (PCB), a ceramic substrate, or a tape wiring substrate, etc. The wiring substrate  600  includes a lower pad  612  disposed on a lower surface of a body of the wiring substrate  600 , an upper pad  611  disposed on an upper surface of the body, and a wiring circuit  613  that electrically connects the lower pad  612  and the upper pad  611 . The body of the wiring substrate  600  may include different materials, depending on a type of the substrate. For example, when the wiring substrate  600  is a printed circuit board, the body may be a thin copper stack plate, or have a form in which a wiring layer is additionally stacked on one or both sides of a thin copper stack plate. The lower and upper pads  612  and  611  and the wiring circuit  613  form an electrical path that connects the lower surface and the upper surface of the wiring substrate  600 . An external connection bump  620  connected to the lower pad  612  is disposed on the lower surface of the wiring substrate  600 . The external connection bump  620  includes at least one of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), or lead (Pb) and/or alloys thereof. 
     The heat dissipation structure  630  is disposed on an upper surface of the wiring substrate  600 , and covers an upper portion of the first semiconductor chip  100 . The heat dissipation structure  630  is attached to the wiring substrate  600  by an adhesive. The adhesive may be one of a thermally conductive adhesive tape, a thermally conductive grease, or a thermally conductive adhesive, etc. The heat dissipation structure  630  is in close contact with the first semiconductor chip  100  by an adhesive member  631  on the upper surface of the first semiconductor chip  100 . The heat dissipation structure  630  includes a thermally conductive material. For example, the heat dissipation structure  630  includes a metal or a metal alloy that includes at least one of gold (Au), silver (Ag), copper (Cu), or iron (Fe), etc., or a conductive material such as graphite or graphene, etc. The heat dissipation structure  630  may have a shape that differs from that illustrated in the drawings. For example, the heat dissipation structure  630  may cover only the upper surface of the first semiconductor chip  100 . 
       FIGS.  7 A to  7 C  are cross-sectional views that schematically illustrate a process of manufacturing the second semiconductor chip  200 A of  FIG.  1 A . 
     Referring to  FIG.  7 A , in an embodiment, a semiconductor wafer W 2  from which a plurality of second semiconductor chips are formed, which may be referred to as a “second semiconductor wafer” is prepared that has an upper surface US’ and a lower surface LS opposite to each other . The second semiconductor wafer W 2  is temporarily bonded to a carrier substrate  11  using a bonding material layer  12 . The bonding material layer  12  is made of an adhesive polymer material that can stably support the second semiconductor wafer W 2  during a subsequent process. The second semiconductor wafer W 2  is in a state in which some components of the second semiconductor chips are formed. For example, the second semiconductor wafer W 2  includes a second circuit layer  220  disposed on one surface of a second substrate  210 , second front surface pads  231  disposed below the second circuit layer  220 , and through-electrodes  240  that extend through the second substrate  210 . Expressions relating to directions such as “on,” “up,” “upward,” “below,” “down,” “downward,” etc., are based on those illustrated in  FIGS.  7 A to  7 C .) 
     Referring to  FIG.  7 B , in an embodiment, a second wiring layer  250 , second rear surface pads  251  of a first group, and second rear surface pads  252  of a second group are formed on an upper surface US of the second semiconductor wafer W 2  that has been planarized by a polishing process. As a portion of the second semiconductor wafer W 2  is removed by a polishing process, upper ends of the through-electrodes  240  are exposed. 
     The polishing process may be one of a grinding process such as a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. For example, the grinding process is performed to reduce a thickness of the second semiconductor wafer W 2  to a predetermined thickness, and the etch-back process having an appropriate condition is applied to expose the through-electrodes  240 . 
     The second wiring layer  250  includes a rear surface interlayer insulating layer  253 , shown in  FIG.  2 A , and a rear surface wiring structure  255 , also shown in  FIG.  2 A . The rear surface interlayer insulating layer  253  may be formed using a chemical vapor deposition (CVD) process, a flowable-CVD process, or a spin coating process. The rear surface wiring structure  255  may be formed using an etching process or a plating process, etc. 
     The second rear surface pads  251  of the first group and the second rear surface pads  252  of the second group may be formed using a photolithography process or a plating process, etc. Conductive posts  320   p  are formed on the second rear surface pads  252  of the second group. The conductive posts  320   p  are formed by a photoresist pattern on the second circuit layer  220  that has an etched region that exposes the second rear surface pads  252  of the second group, and by a plating process that fills the etched region of the photoresist with a metal such as copper (Cu) or the like. 
     Referring to  FIG.  7 C , in an embodiment, the second semiconductor wafer W 2  of  FIG.  7 B  is supported on a dicing tape  13  and is cut and separated into a plurality of second semiconductor chips  200 A. The second semiconductor wafer W 2  may be separated using, for example, a laser dicing process. , The plurality of second semiconductor chips  200 A are respectively attached to a first semiconductor chip  100  of a first semiconductor wafer W 1 , shown in  FIG.  8 A , using a pick-and-place device. 
       FIGS.  8 A to  8 D  are cross-sectional views that schematically illustrate a process of manufacturing the semiconductor package  1  of  FIG.  1 A . 
     Referring to  FIG.  8 A , in an embodiment, a first semiconductor wafer W 1  is prepared that includes a first front surface FS 1  and a first rear surface BS1 that are opposite to each other, and first front surface pads  131  of a first group and first front surface pads  132  of a second group that are disposed on the first front surface FS 1 . The first semiconductor wafer W 1  is supported by a second carrier substrate  20 . 
     In addition, at least one second semiconductor chip  200 A or  200 B prepared by the manufacturing process of  FIGS.  7 A to  7 C . The at least one second semiconductor chip  200 A or  200 B includes a second front surface FS 2  and a second rear surface BS 2  that are opposite to each other, second rear surface pads  251  of a first group and second rear surface pads  252  of a second group that are disposed on the second rear surface BS 2 , and conductive posts  320   p  disposed on the second rear surface pads  252  of the second group. 
     The at least one second semiconductor chip  200 A or  200 B is attached onto the first semiconductor wafer W 1  such that the second front surface FS 2  faces the first front surface FS 1 . A preliminary adhesive film layer  335   p  that surrounding third bump structures  330  is disposed below the second front surface FS 2  of the at least one second semiconductor chip  200 A or  200 B. The preliminary adhesive film layer  335   p  is a non-conductive film (NCF). 
     Referring to  FIG.  8 B , in an embodiment, after attaching the at least one second semiconductor chip  200 A or  200 B onto the first semiconductor wafer W 1 , a bonding wire  311   p  that electrically connects the first front surface pads  131  of the first group and the first rear surface pads  251  of the first group, and a stud bump  312   p  on the second rear surface pads  251  of the first group are formed. The bonding wire  311   p  and the stud bump  312   p  are formed by a wire bonding process that uses a capillary  30 . For example, the stud bump  312   p  is integrally formed with the bonding wire  311   p . The at least one second semiconductor chip  200 A or  200 B is fixed by a thermal compression process. In the thermal compression process, the preliminary adhesive film layer  335  preflows to form an adhesive film  335 . 
     Referring to  FIG.  8 C , in an embodiment, a preliminary encapsulant  410 ′ that covers the at least one second semiconductor chip  200 A or  200 B, the bonding wire  311   p , the stud bump  312   p , and the conductive posts  320   p , is formed on the first semiconductor wafer W 1 . A polishing process is applied to the preliminary encapsulant  410 ′ to form first bump structures  310 , second bump structures  320 , and an encapsulant  410 . For example, a polishing process forms a stud portion  312  in which a portion of the stud bump  312   p  of  FIG.  8 B  is removed, and forms second bump structures  320  in which portions of the conductive posts  320   p  of  FIG.  8 B  are removed. The first bump structures  310  include a stud portion  312  on the second rear surface pads  251  of the first group, and a bonding wire portion  311  that extends from the stud portion  312 . 
     An upper surface  312 US of each of the first bump structures  310  and an upper surface  320 US of each of the second bump structures  320  is exposed through an upper surface  410 US of the encapsulant  410 . The upper surface  410 US of the encapsulant  410 , the upper surface of the first bump structures  310  or the upper surface  312 US of the stud portion  312 , and the upper surface  320 US of the second bump structures  320  are coplanar. In addition, the upper surface  312 US of the stud portion  312  exposed through the upper surface  410 US of the encapsulant  410  has a predetermined size. For example, a diameter of the upper surface  312 US of the stud portion  312  is about 50 µm. 
     Referring to  FIG.  8 D , in an embodiment, a redistribution structure  510  is formed on the upper surface  410 US of the encapsulant  410 . The redistribution structure  510  includes redistribution layers  512  that are electrically connected to the first bump structures  310  or the second bump structures  320 . The redistribution structure  510  includes an insulating layer  511 , redistribution layers  512 , and redistribution vias  513 . The insulating layer  511  is formed by coating and curing a photosensitive resin such as PID on the upper surface  410 US of the encapsulant  410 . The redistribution layers  512  and the redistribution vias  513  are formed using one of a photolithography process, an etching process, or a plating process, etc. 
     According to embodiments of the present inventive concept, by introducing a bump structure that includes a bonding wire, a semiconductor package and a method of manufacturing the same are provided that have reduced manufacturing costs and increased yield. 
     While embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of embodiments of the present inventive concept as defined by the appended claims.