Patent Publication Number: US-11379187-B2

Title: Semiconductor device performing a multiplication and accumulation operation

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2019-0115719, filed on Sep. 20, 2019, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     Various embodiments relate to a semiconductor device performing a multiplication and accumulation (MAC) operation. 
     2. Related Art 
     Neural networks are widely used in artificial intelligence applications, such as image recognition and technologies used in autonomous vehicles. 
     In an example, a neural network includes an input layer, an output layer, and one or more inner layers between the input layer and the output layer. 
     Each of the output layer, the input layer, and the inner layers includes one or more neurons. Neurons contained in adjacent layers are connected in various ways through synapses. For example, synapses point from neurons in a given layer to neurons in a next layer. Alternately or additionally, synapses point to neurons in a given layer from neurons in a previous layer. 
     Each of the neurons stores a value. The values of the neurons included in the input layer are determined according to an input signal, for example, an image to be recognized. The values of the neurons contained in the inner and output layers are based on the neurons and synapses contained in corresponding previous layers. For example, the values of the neurons in each of the inner layers are based on the values of the neurons in a preceding layer in the neural network. 
     Each of the synapses has a weight. The weight of each of the synapses is based on a training operation of the neural network. 
     After the neural network is trained, the neural network can be used to perform an inference operation. In the inference operation, the values of the neurons in the input layer are set based on an input, and the values of the neurons in the next layers (e.g., the inner layers and the output layer) are set based on the values of the neurons in the input layer and the trained synapses connecting the layers. The values of the neurons in the output layer represent a result of the inference operation. 
     For example, in an inference operation, in which image recognition is performed by the neural network after the neural network has been trained, the values of the neurons in the input layer are set based on an input image, a plurality of operations are performed at the inner layers based on the values of the neurons in the input layer, and a result of the image recognition is output at the output layer from the inner layers. 
     In such an inference operation, a large number of Multiply-Accumulate (MAC) operations must be performed by the neurons in the convolutional neural network. As a result, a semiconductor device that can efficiently perform a large number of MAC operations is desired. 
     SUMMARY 
     In accordance with an embodiment of the present disclosure, a semiconductor device may include a cell array including a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation; a computation circuit including a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation; and a control circuit configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation. 
     In accordance with an embodiment of the present disclosure, a method of performing a computation operation may include storing a first plurality of analog voltage values respectively corresponding to a first plurality of input values in a first row of a cell array; and performing a first computation by: performing a first multiplication operation by: configuring capacitances of a plurality of unit computation circuits according to a plurality of weight values, respectively, and charging the configured capacitances of the plurality of unit computation circuits according to the first plurality of analog voltage values; and after performing the first multiplication operation, performing a first accumulation operation by: configuring the respective capacitances of the plurality of unit computation circuits to have a same value, connecting the capacitances of the plurality of unit computation circuits together in parallel, and outputting a first computation result according to a voltage of the connected capacitances. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying figures, wherein like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments that include various features, and explain various principles and beneficial aspects of those embodiments. 
         FIG. 1  illustrates a semiconductor device according to an embodiment of the present disclosure. 
         FIG. 2  illustrates a computation circuit according to an embodiment of the present disclosure. 
         FIGS. 3, 4, and 5  respectively illustrates operations of a semiconductor device according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments will be described below with reference to the accompanying figures. Embodiments are provided for illustrative purposes and other embodiments that are not explicitly illustrated or described are possible. Further, modifications can be made to embodiments of the present disclosure that will be described below in detail. 
       FIG. 1  illustrates a semiconductor device  1  according to an embodiment of the present disclosure. 
     The semiconductor device  1  includes a cell array  100 , a computation circuit  200 , and a control circuit  300 . 
     The cell array  100  includes a plurality of unit cells capable of storing analog signals. The plurality of unit cells may be arranged in a grid form. 
     The computation circuit  200  performs an operation corresponding to an inner product of an input vector and a weight vector and outputs a result thereof. 
     The structure and operation of the cell array  100  and the computation circuit  200  will be described in detail with reference to  FIG. 2 . 
     The control circuit  300  controls the cell array  100  and the computation circuit  200  according to a command CMD, an address ADDR, an input signal IN, and a weight signal W. The address can include a row address and a column address. 
     In the present embodiment, the input signal and the weight signal may be referred to as an input vector and a weight vector, and each includes a plurality of elements. Each element of the input vector and weight vector in the illustrated embodiment is a multi-bit digital signal. 
     The present embodiment is disclosed assuming that a signal corresponding to an input signal IN is stored in the cell array  100  and a weight signal W is provided to the computation circuit  200 . 
     In another embodiment, a signal corresponding to the weight signal may be stored in the cell array  100 , and a signal corresponding to the input signal may be provided to the computation circuit  200 . 
     The signal provided to the cell array  100  may be referred to as a first signal, and the signal provided to the computation circuit  200  may be referred to as a second signal. 
     Accordingly, a signal stored in the cell array  100  corresponding to the first signal may be referred to as a first analog signal. 
     The control circuit  300  controls the operation of storing an analog signal corresponding to the input signal in the cell array  100  and the operation of reading the stored analog signal from the cell array  100 . 
     Hereinafter, an operation of storing an analog signal corresponding to an input signal in the cell array  100  is referred to as a write operation, and an operation of reading the stored analog signal and outputting the stored analog signals to the bitlines BL 1  to BLn is referred to as a read operation. 
     The control circuit  300  provides row write signals WR 1 , . . . , WRm, column write signals WBL 1 , . . . , WBLn, row reset signals RST 1 , . . . , RSTm, row read signals RD 1 , . . . , RDm, and a global read signal GRD to the cell array  100  in order to control read or write operations. 
     A read operation, a write operation, and characteristics of signals required for each operation will be described in detail with reference to  FIG. 2 . 
     The control circuit  300  controls the operation of the computation circuit  200 . 
     In the present embodiment, the operation performed by the computation circuit  200  includes a MAC operation including a plurality of multiplication operations and a plurality of accumulation operations performed using results of the multiplication operations to calculate an inner product between an input vector and a weight vector. 
     In order to perform a multiplication operation, a read operation is performed to read a row of the cell array  100  corresponding to a row address. 
     As a result of the accumulation operations, a computation signal V mac  corresponding to the inner product between the input vector and the weight vector is output. 
     The control circuit  300  may provide switch control signals W 1 , . . . , Wn, an accumulation signal ACC, and a discharge signal RSTa to the computation circuit  200  for a computation operation. 
     A computation operation and characteristics of a signal required for the computation operation will be described in detail with reference to  FIG. 2 . 
       FIG. 2  illustrates a cell array  100  and a computation circuit  200  according to an embodiment of the present disclosure. 
     The cell array  100  includes a plurality of unit cells  110  arranged in a grid form. 
     The plurality of unit cells  110  are arranged in a grid having m rows and n columns, where each of m and n is a natural number greater than 1. Each of the plurality of unit cells  110  have the same internal configuration. 
     Hereinafter, a unit cell  110  located at an intersection of a first row and a first column will be described. 
     The cell array  100  includes a plurality of write wordlines  120  arranged in a row direction, a plurality of read wordlines  130  arranged in the row direction, and a plurality of bitlines  140  arranged in a column direction. 
     The cell array  100  includes a plurality of write bitlines  150  and a plurality of read bitlines  160  arranged in the column direction. 
     The cell array  100  includes a plurality of input current sources  170  each provides an input current I in  to a corresponding write bitline  150 . 
     The cell array  100  includes a plurality of bias current sources  180  each provides a bias current I bias  to a corresponding read bitline  160 . 
     The cell array  100  includes a column write switch M GW1  connecting the input current source  170  and the write bitline  150  according to the column write signal WBL 1 . 
     The cell array  100  includes a column read switch M GR1  connecting the bias current source  180  and the read bitline  160  according to the global read signal GRD. 
     The cell array  100  may further include a plurality of reset lines  190  arranged in a row direction. 
     The analog signal stored in the unit cell  110  may be initialized according to a row reset signal RST 1  applied to the reset line  190 . 
     The unit cell  110  includes a cell capacitor C 11  that stores an analog signal. A first terminal of the cell capacitor C 11  is grounded. 
     The unit cell  110  includes a write circuit that stores an analog signal in the cell capacitor C 11  and a read circuit that reads the analog signal stored in the cell capacitor C 11 . 
     The write circuit includes a write transistor M W11  having a source connected to the a second terminal of the cell capacitor C 11 , a gate connected to the write wordline  120 , and a drain connected to the write bitline  150 . 
     The read circuit includes a first read transistor MB 11  having a gate connected to the second terminal of the cell capacitor C 11  and a drain connected to the read bitline  160  and a second read transistor M R11  having a gate connected to a read wordline  130 , a drain connected to a source of the first read transistor MB 11 , and a source connected to the bitline  140 . 
     The unit cell  110  further includes a cell reset switch RS 11  connected between the first and second terminals of the cell capacitor C 11  and discharging the cell capacitor C 11  according to the row reset signal RST 1  transmitted through the reset line  190 . 
     When the write operation is performed, the row write signal WR 1  and the column write signal WBL 1  are activated. 
     In this embodiment, the row write signal WR 1  is activated while a write operation on the corresponding row is in progress. 
     The column write signal WBL 1  is a pulse signal having a width corresponding to the value of the corresponding element of the input vector. 
     In the period when both the row write signal WR 1  and the column write signal WBL 1  are at a high level, the cell capacitor C 11  is charged by the input current I in  provided through the write transistor M W11 . 
     Accordingly, the cell voltage V 11  charged in the cell capacitor C 11  by the write operation is, at the end of the pulse on the column write signal WBL 1 , an analog signal having a voltage value corresponding to the value of the corresponding element of the input vector. 
     At this time, the cell voltage V 11  should be set to a value high enough that the first read transistor M B11  can operate in the saturation region, and thus the cell voltage V 11  should be higher than the threshold voltage V th11  of the first read transistor M B11 . 
     In the present embodiment, the row reset signal RST 1  may be activated to discharge and initialize the cell capacitors C 11 , . . . , C 1n  included in the corresponding row before the write operation is performed. 
     When the read operation is performed, the global read signal GRD and the row read signal RD 1  are activated. 
     The global read signal GRD has a high level while a read operation is performed on any of the rows. 
     The row read signal RD 1  has a high level while performing a read operation on the corresponding row. 
     During the read operation, the bias current I bias  is provided to the drain of the first read transistor M B11 . 
     In this case, the bias current I bias  corresponds to a value at which the first read transistor M B11  can operate in a saturation region so that the source voltage of the first read transistor M B11  can follow the cell voltage V 11  provided to the gate thereof. 
     The second read transistor M R11  is turned on by the row read signal RD 1 , but the magnitude of the row read signal RD 1  is set such that the source voltage of the second read transistor M R11  substantially follows the drain voltage thereof. 
     Accordingly, in the read operation, an output voltage V O1  having substantially the same magnitude as the cell voltage V 11  is produced on the bitline BL 1 . 
     The read operation is performed on the plurality of columns included in the row, thereby a plurality of output voltages V O1 , . . . , V On  are provided from the plurality of bitlines BL 1 , . . . , BLn. 
     The computation circuit  200  includes a plurality of unit computation circuits  210  respectively corresponding to the plurality of bitlines in the cell array  100 . Each of the plurality of unit computation circuits  210  have substantially the same internal configuration. 
     Hereinafter, the internal configuration of the unit computation circuit  210  connected to the first bitline BL 1  is disclosed. 
     A first terminal of the unit computation circuit  210  is connected to the corresponding bitline BL 1  and a second terminal is grounded. The first terminal of the unit computation circuit  210  may be referred to as an output terminal of the unit computation circuit  210 . 
     Each of the plurality of unit computation circuits  210  performs a multiplication operation. For example, the unit computation circuit  210  charges an amount of charge corresponding to a product of an element of the input vector and an element of the weight vector. 
     That is, information stored in the unit computation circuit  210  corresponding to an element of the weight vector may be represented as a capacitance of the unit computation circuit  210 . 
     The output terminal of the unit computation circuit  210  is connected to the output terminal of the adjacent unit computation circuit through the connection switch M S1 . 
     The plurality of connection switches M S1  are turned on or off according to the accumulation signal ACC, and when the accumulation signal ACC is activated, the plurality of unit computation circuits are all connected in parallel so that the computation signal V mac  is output at the output terminal of the unit computation circuit  210 . 
     The unit computation circuit  210  includes k switch-capacitor pairs, where k is a natural number greater than 1, connected in parallel between the first terminal and the second terminal of the unit computation circuit  210 . 
     In an embodiment, the number k of switch-capacitor pairs corresponds to the number of bits of an element of the weight vector, which corresponds to a number of bits of the switch control signal W 1 . 
     Each switch-capacitor pair includes a switch SW; and a computation capacitor C j  for j in 1 . . . k, connected in series between the first terminal and the second terminal of the unit computation circuit  210 . 
     In the present embodiment, capacitance of a computation capacitor C j  included in the j-th switch-capacitor pair may be represented by 2 j-1 C P , where C p  is a unit capacitance having a predetermined capacitance. In another embodiment, each bit W 1j  of the switch control signal W 1  may control 2 j-1  switch-capacitor pairs, each capacitor in the switch-capacitor pairs having the unit capacitance C p . 
     The control circuit  300  controls the operation of the computation circuit  200 . 
     In order to perform a computation operation, the switch control signal W 1  is used to control the plurality of switch-capacitor pairs of the unit computation circuit  210  coupled to the first bit line BL 1 , the switch control signal W 2  is used to control the plurality of switch-capacitor pairs of the unit computation circuit  210  coupled to the second bit line BL 2 , and so on, with the switch control signal W n  used to control the plurality of switch-capacitor pairs of the unit computation circuit  210  coupled to the second bit line BLn, and so on, with. 
     As described above, the computation operation includes multiplication operations and accumulation operations. 
     The switch control signals W 1  to W n  are generated from the corresponding elements of the weight vector and respectively applied to the plurality of unit computation circuits  210  coupled to the plurality of bitlines BL 1  to BLn for the multiplication operation. 
     After the read operation is performed in the cell array  100 , the plurality of unit computation circuits are charged using the voltages V O1 , . . . , V On  produced on the plurality of bitlines BL 1  to BLn. 
     As a result, each of the plurality of unit computation circuits stores charges whose amount corresponds to multiplication between an element of the input vector (corresponding to a voltage on a bitline) and an element of the weight vector (corresponding to a configured capacitance of a unit computation circuit). 
     In order to perform the accumulation operation, the cell array  100  terminates the read operation. 
     In addition, for the accumulation operation, the switch control signals W 1 , . . . , W n  are controlled to set all of the capacitance of the plurality of unit computation circuits to be the same. 
     For example, the switch control signals W 1  . . . , W n  are each set to turn on all switches in the respective unit computation circuit  210 . As a result, all unit computation circuits come to have the same capacitance C t . 
     Thereafter, the accumulation signal ACC provided to the computation circuit  200  is activated to connect the plurality of unit computation circuits  210  in parallel. 
     When the addition signal ACC is activated, the charges stored in the plurality of unit computation circuits are redistributed, and as a result, the computation signal V mac  provided at the output of the unit computation circuit  210  corresponds to the inner product of the input vector and the weight vector. 
     The computation circuit  200  may include a discharge switch RSa connected in parallel to the unit computation circuit  210 . 
     The control circuit  300  may control the discharge operation with respect to the computation circuit  200  before starting the computation operation of the computation circuit  200 . 
     In the discharge operation, all the switches of the plurality of unit computation circuits  210  may be turned on, the accumulation operation signal ACC may be activated, and the discharge signal RSTa may be activated. 
       FIG. 3  is a timing diagram illustrating a write operation and a read operation with respect to the cell array  100 . 
     Write operations are sequentially performed from the first row to the m-th row of the cell array  100  during T 10  to T 1   m.    
     For example, the row write signal WR 1  is activated during T 10  to T 11  to perform a write operation on the first row to store the cell voltage V 11 , the row write signal WR 2  is activated during T 11  to T 12  to perform a write operation on the second row to store the cell voltage V 21 , and the row write signal WRm is activated during the period T 1 ( m −1) to T 1   m  to perform a write operation on the m-th row to store the cell voltage V m1 . 
     The cell voltage is only displayed for the first column, but the write operation may be performed on other columns to store the cell voltage. That is, in an embodiment, cell voltages V 11  to V 1n  may be respectively stored into cell capacitors C 11  to C 1n  when the row write signal WR 1  is activated, cell voltages V 21  to V 2n  may be respectively stored into cell capacitors C 21  to C 2n  when the row write signal WR 2  is activated, and so on. 
     The global read signal GRD is activated during the period between T 20  and T 2   m  so that read operations are sequentially performed from the first row to the m-th row of the cell array  100 . 
     For example, the row read signal RD 1  is activated during T 20  to T 21  to perform a read operation on the first row, so that the output voltage V O1  of the bitline BL 1  becomes the cell voltage V 11 . 
     The row read signal RD 2  is activated during T 21  to T 22  to perform a read operation on the second row, so that the output voltage V O1  of the bitline BL 1  becomes the cell voltage V 21 . 
     The row read signal RDm is activated during T 2 ( m −1) to T 2   m  to perform a read operation on the m-th row, so that the output voltage V O1  of the bitline BL 1  becomes the cell voltage V m1 . 
     Though only the output voltage V O1  for the first column is shown, output voltages for other columns are also output. That is, when the global read signal GRD and the row read signal RDy are both activated, output voltages V O1  to V On  of the bitlines BL 1  to BLn become the cell voltages V y1  to V yn , respectively, for y in 1 . . . m. 
       FIG. 4  is a timing diagram illustrating a write operation for each column during T 10  to T 11 . 
     A write operation is performed for each column of the first row during T 10  to T 11 . 
     As described above, each of the column write signals WBL 1 , . . . , WBLn has a pulse width corresponding to the value of the corresponding element of the input vector. 
     For example, the column write signal WBL 1  has a pulse width t 1  and has a high level between T 10  and T 10 +t 1 , and the column write signal WBL 2  has a pulse width of t 2  and has a high level between T 10  and T 10 +t 2 . The column write signal WBLn has a pulse width of tn and has a high level between T 10  and T 10 +tn. 
     Accordingly, the cell voltage V 11  gradually increases between T 10  and T 10 +t 1 , the cell voltage V 12  gradually increases between T 10  and T 10 +t 2 , and the cell voltage V 1n  gradually increases between T 10  and T 10 +tn. 
     As described above, the cell voltage V 11  should be set to a value at which the first read transistor M B11  can operate in the saturation region, so that the cell voltage V 11  should be higher than the threshold voltage V th11  of the first read transistor M B11 . 
     The minimum length of the time when each of the column write signals WBL 1  to WBLn is activated may be set accordingly. That is, the pulse width of each of the column write signals WBL 1  to WBLn may correspond to the value of the corresponding element of the input vector plus an offset value corresponding to the threshold voltage of a read transistor. 
       FIG. 5  is a timing diagram illustrating a computation operation for the first row. 
     The multiplication operation is performed between T 20  and T 30 , and the accumulation operation is performed between T 30  and T 40 . 
     In order to perform the multiplication operation, the computation circuit  200  provides switch control signals W 1  to Wn corresponding to respective elements of the weight vector to set the respective capacitances of the plurality of unit computation circuit  210  to have values corresponding to the respective elements of the weight vector. 
     Thereafter, when the global read signal GRD and the row read signal RD 1  are activated and the read operation for the first row is performed, the output voltages V O1  to V On  provided from the plurality of bitlines BL 1  to BLn are respectively applied to the unit computation circuits. 
     The charge amount Q j  charged in the j th  unit computation circuit, j in 1 . . . n, may be represented by the following equation 1. 
     
       
         
           
             
               
                 
                   
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             wherein k is the number of bits in the switch control signal W j , and W ji  is the value of the i th  bit of switch control signal W j . 
           
         
       
    
     In T 30 , the accumulation signal ACC is activated to connect the plurality of unit computation circuits  210  in parallel. 
     At this time, the switches included in the plurality of unit computation circuit are all turned on, and all the plurality of unit computation circuits come to have the same capacitance. 
     Accordingly, charges are redistributed among the plurality of unit computation circuits and a computation signal V mac  corresponding to the inner product of the input vector and the weight vector is generated. 
     When the capacitance of the unit computation circuit  210  is C t  during the accumulation operation, the computation signal V mac  may be expressed as Equation 2 below. 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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     As described above, the computation signal V mac  output during the accumulation operation is a signal having a value corresponding to the inner product of the input vector and the weight vector. 
     The computation circuit  200  may further include an amplifier  202  for adjusting and outputting the magnitude of the computation signal V mac . 
     The computation circuit  200  may further include an analog-to-digital converter (ADC)  204  for converting the computation signal V mac  into a digital signal D mac . 
     Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and scope of the disclosure as defined by the following claims.