Patent Publication Number: US-8981527-B2

Title: Resistor and manufacturing method thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a resistor and a manufacturing method thereof, and more particularly, to a resistor and a manufacturing method for a resistor integrated with a transistor having metal gate. 
     2. Description of the Prior Art 
     To increase the performance of transistors, metal gates are popularly used in the semiconductor field: the metal gates competent to the high-K gate dielectric layer replace the traditional polysilicon gates to be the control electrode. The metal gate approach can be categorized to the gate first process and the gate last process. And the gate last process gradually replaces the gate first process because it provides more material choices for the high-k gate dielectric layer and the metal gate. 
     Additionally, resistors are elements which are often used for providing regulated voltage and for filtering noise in a circuit. The resistors generally include polysilicon and silicide layers. 
     In the current semiconductor field, though the fabricating processes are improved with the aim of reaching high yields, it is found that integration of the manufacturing methods of those different kinds of semiconductor devices is very complicated and difficult. Therefore, a method for fabricating a resistor integrated with a transistor having metal gate is still in need. 
     SUMMARY OF THE INVENTION 
     According to a first aspect of the present invention, a method for forming a resistor integrated with a transistor having metal gate is provided. The method includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor. 
     According to a second aspect of the present invention, a resistor is provided. The resistor includes a substrate, a polysilicon main portion formed on the substrate, two metal portions respectively positioned at two opposite ends of the polysilicon main portion on the substrate, and two doped regions respectively formed between the metal portions and the polysilicon main portion on the substrate. 
     According to the resistor and the method for forming a resistor integrated with a transistor having metal gate, the doped regions protects the polysilicon main portion of the resistor during the etching process, therefore the over etching problem is solved. Furthermore, a length of the doped region can be defined or decided depending on a required resistance. In other words, by adjusting a length of the doped region, a resistance of the resistor can be easily modified. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-6  are schematic drawings illustrating a method for forming a resistor integrated with a transistor having metal gate provided by a first preferred embodiment of the present invention, wherein 
         FIG. 2  is a schematic drawing in a step subsequent to  FIG. 1 , 
         FIG. 3  is a schematic drawing in a step subsequent to  FIG. 2 , 
         FIG. 4  is a schematic drawing in a step subsequent to  FIG. 3 , 
         FIG. 5  is a schematic drawing in a step subsequent to  FIG. 4 , and 
         FIG. 6  is a schematic drawing in a step subsequent to  FIG. 5 . 
         FIGS. 7-8  are schematic drawings illustrating a method for forming a resistor integrated with a transistor having metal gate provided by a second preferred embodiment of the present invention, wherein 
         FIG. 8  is a schematic drawing in a step subsequent to  FIG. 7 . 
         FIGS. 9-12  are schematic drawings illustrating a method for forming a resistor integrated with a transistor having metal gate provided by a third preferred embodiment of the present invention, wherein 
         FIG. 10  is a schematic drawing in a step subsequent to  FIG. 9 , 
         FIG. 11  is a schematic drawing in a step subsequent to  FIG. 10 , and 
         FIG. 12  is a schematic drawing in a step subsequent to  FIG. 11 . 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIGS. 1-6 , which are schematic drawings illustrating a method for forming a resistor integrated with a transistor having metal gate provided by a first preferred embodiment of the present invention. As shown in  FIG. 1 , a substrate  100  having a transistor region  102  and a resistor region  104  defined thereon is provided. The substrate  100  also includes a plurality of shallow trench isolations (STIs)  106  positioned in between devices for providing electrical isolation. It is noteworthy that a STI  106  is formed in the resistor region  104 . A dielectric layer  108 , a bottom barrier layer  110 , and a semiconductor layer such as a polysilicon layer  112  are sequentially formed on the substrate  100 . As shown in  FIG. 1 , the dielectric layer  108  and the bottom barrier layer  110  are formed between the polysilicon layer  112  and the substrate  100 . In the preferred embodiment, method for forming a resistor integrated with a transistor having metal gate is integrated with the high-k first process, therefore the dielectric layer  108  includes a high dielectric constant (high-k) materials such as rare earth metal oxide. The high-k gate dielectric layer  108  can include material selected from the group consisting of hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate, (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), and barium strontium titanate (Ba x Sr 1-x TiO 3 , BST). Additionally, an interfacial layer (not shown) can be formed in between the high-k gate dielectric layer  108  and the substrate  100 . The bottom barrier layer  110  includes titanium nitride (TiN), but not limited to this. Then, a patterned mask  114  is formed on the polysilicon layer  112 . The patterned mask  114  can include photoresist, but not limited to this. The patterned mask  114  has two openings  114   a , and the openings  114   a  have a width W 1 . After forming the patterned mask  114 , an ion implantation  116  is performed to form two doped regions  118  in the polysilicon layer  112  in the resistor region  104  through the openings  114   a . Accordingly, the doped regions  118  include p-type dopants, but not limited to this. Furthermore, the doped regions  118  include the width W 1  inherited from the openings  114   a.    
     Please refer to  FIG. 2 . After forming the doped regions  118 , the patterned mask  114  is removed and followed by patterning the polysilicon layer  112 , the bottom barrier layer  110 , and the dielectric layer  108 . Consequently, a polysilicon dummy gate  120  for a transistor is formed in the transistor region  102  and a polysilicon main portion  130  for a resistor (shown in  FIG. 5 ) is formed in the resistor region  104 . As shown in  FIG. 2 , the polysilicon main portion  130  is formed to have the two doped regions  118  respectively positioned its two opposite ends. In other words, the two doped regions  118  are separated from each other by the polysilicon main portion  130 . Then, lightly-doped drains (LDDs)  122  for the transistor are formed in the substrate  100  at two sides of the polysilicon dummy gate  120  in the transistor region  102 , spacers  124  and  132  are respectively formed on sidewalls of the polysilicon dummy gate  120  and the doped regions  118 , and a source/drain  126  is formed in the substrate  100  at two sides of the spacer  124  in the transistor region  102 . Accordingly, a transistor  140  having the polysilicon dummy gate  120  is obtained in the transistor region  102 . Additionally, salicides  128  are formed on the source/drain  126 . After forming the transistor  140  having the polysilicon dummy gate  120 , a contact etch stop layer (CESL)  160  and an inter-layer dielectric (ILD) layer  162  are sequentially formed. Since the steps and material choices for the abovementioned elements are well-known to those skilled in the art, those details are omitted herein in the interest of brevity. Furthermore, selective strain scheme (SSS) can be used in the preferred embodiment. For example, a selective epitaxial growth (SEG) method can be used to form the source/drain  126 . 
     Please still refer to  FIG. 2 . After forming the CESL  160  and the ILD layer  162 , a planarization process is performed to remove a portion of the CESL  160  and a portion of the ILD layer  162  to expose the polysilicon dummy gate  120  of the transistor  140 , the doped regions  118 , and the polysilicon main portion  130 . Then, a patterned hard mask  164  is formed on the substrate  100 . The patterned hard mask  164  can include silicon nitride (SiN), but not limited to this. As shown in  FIG. 2 , the patterned hard mask  164  exposes the polysilicon dummy gate  120  and a portion of the doped regions  118 . 
     Please refer to  FIG. 3 . Next, a suitable etching process such as a dry etching process is performed. It is noteworthy that since an etching rate of the doped regions  118  and the polysilicon dummy gate  120  which include the polysilicon is different from that of the CESL  160 , the ILD layer  162  and the patterned hard mask  164  which include dielectric material, only the polysilicon dummy gate  120  and the exposed doped regions  118  are removed. Consequently, a first trench  166  is formed in the transistor  140  and two second trenches  168  are formed in resistor region  104 , simultaneously. It is noteworthy that the second trench  168  defined by the patterned hard mask  164 , the ILD layer  162  and the CESL  160  includes a width W 2 , and the width W 2  is always smaller than the width W 1  of the original doped regions  118 . Since the width W 2  of the second trenches  168  is smaller than the width W 1  of the doped regions  118 , it is ensured that the polysilicon main portion  130  is protected from the etching process, and thus damages to the polysilicon main portion  130  due to over etching is avoided. 
     As shown in  FIG. 3 , the bottom barrier layer  110  is exposed in the first trench  166  and the second trenches  168  by the etching process. After forming the first gate trench  166  and the second gate trench  168 , an etch stop layer (not shown) can be formed on the bottom barrier layer  110  in both of the first gate trench  166  and the second gate trench  168 . The etch stop layer can include tantalum nitride (TaN), but not limited to this. 
     Please refer to  FIG. 4 . After forming the first trench  166  and the second trenches  168 , a work function metal layer  170  required by the metal gate process is formed in both of the first trench  166  and the second trenches  168 . According to the preferred embodiment, the work function metal layer  170  can include suitable materials providing an appropriate work function for p-type transistor or n-type transistor. Therefore, the work function metal layer  170  has a work function, and the work function can be between 4.8 eV and 5.2 eV, or alternatively between 3.9 eV and 4.3 eV. Thereafter, a filling metal layer  172  filling up the first trench  166  and the second trenches  168  is formed on the substrate  100 . In the preferred embodiment, the filling metal layer  172  includes materials with low resistance and superior gap-filling characteristic, such as aluminum (Al), titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO), but not limited to this. Additionally, a top barrier layer (not shown) can be formed between the work function metal layer  170  and the filling metal layer  172  if required. 
     Please still refer to  FIG. 5 . After forming the work function metal layer  170  and the filling metal layer  172 , a planarization process such as a CMP process is performed to remove the unnecessary filling metal layer  172  and work function metal layer  170 . Consequently, a metal gate  180  for the transistor  140  is formed in the first trench  166  and two metal structures  182  are formed in the second trenches  168 . As shown in  FIG. 5 , the metal gate  180  and the metal structure  182  are multilayered structure. Furthermore, a resistor  150  having the polysilicon main portion  130 , the doped regions  118  and two metal structures  182  serving as metal portions for the resistor  150  is formed in the resistor region  104 . It is noteworthy that each doped region  118  is sandwiched by the polysilicon main portion  130  and the metal portion  182 . 
     Please refer to  FIG. 6 . After forming the metal gate  180  and the resistor  150 , a multilayered dielectric layer  190  is formed on the substrate  100 , and a first contact  192  electrically connected to the metal gate  180  of the transistor  140 , second contacts  194  electrically connected to the metal portions  182  of the resistor  150 , and third contacts  196  electrically connected to the salicides  128  on the source/drain  126  of the transistor  140  are formed in the multilayered dielectric layer  190 . It is noteworthy that because the contacts  192 ,  194 , and  196  are landing on two different materials (the metal materials of the metal gate  180  and the metal portion  182 , and the salicides  128 ), the contact process is simplified when comparing with the conventional contact process, of which the contacts are landing on three different materials (the metal material of the metal gate, the polysilicon of the resistor, and the salicide formed on the source/drain). 
     Please refer to  FIG. 5  again. More important, the resistor  150  provided by the preferred embodiment has a resistance that can be adjusted. Please refer to the following Formula (1): 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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     According to Formula (1), it is concluded that the resistance of the resistor  150  is in relationship with the length L p-poly  of the remained doped region  118  and the length L u-poly  of the polysilicon main portion  130 . Therefore, by modifying the L p-poly  of the remained doped region  118  and the length L u-poly  of the polysilicon main portion  130 , different resistance can be obtained. In other words, the preferred embodiment provides a resistor  150  have resistance that is adjustable as required by modifying the length L p-poly  of the doped region  118 . 
     According to the resistor  150  and the method for forming a resistor integrated with a transistor  140  having metal gate  180  provided by the preferred embodiment, the method is easily integrated with the gate-last process and the high-k first process. The doped regions  118  includes an etching rate different from the polysilicon main portion  130 , therefore the doped regions  118  are resistible to the etchant and sufficient to protect the polysilicon main portion  130  of the resistor  150  from the etching process, particularly the lateral over etching. Briefly speaking, the over etching problem, which used to encroach on the polysilicon main portion  130  in the prior art, is solved. Secondly, the contact process is simplified since the contacts  192 ,  194   196  are landing on two different materials (the metal materials of the metal gate  180  and the metal portion  182 , and the salicides  128 ). Furthermore, the length L p-poly  of the doped regions  118  can be defined or decided depending on a required resistance. In other words, by adjusting the length L p-poly  of the doped regions  118 , the resistance of the resistor  150  can be easily modified. 
     Please refer to  FIG. 7-8 , which are schematic drawings illustrating a method for forming a resistor integrated with a transistor having metal gate provided by a second preferred embodiment of the present invention. Please note that elements the same in both first and second preferred embodiment are designated by the same numerals, thus the material choices and steps for forming those elements are all omitted in the interest of brevity. According to the second preferred embodiment, the method provided by the present invention can be integrated with the high-k last process; therefore a dielectric layer  108   a  includes a conventional SiO 2  layer is formed between the substrate  100  and the polysilicon layer  112 . After removing the polysilicon layer  112  to form the first gate trench  166  and the second gate trenches  168 , the dielectric layer  108   a  exposed in the bottoms of the first gate trench  166  and the second gate trenches  168  serves as an interfacial layer. Next, a high-k gate dielectric layer  108  including abovementioned materials and a bottom barrier layer  110  as mentioned above are formed in the first gate trench  166  and the second gate trenches  168 . Then, an etch stop layer (not shown) can be formed on the bottom barrier layer  110 . 
     Please refer to  FIG. 7  again. After forming the etch stop layer, a work function metal layer  170  is formed in the first gate trench  166  and the second gate trenches  168 . The work function metal layer  170  can include suitable materials providing an appropriate work function for p-type transistor or n-type transistor. Therefore, the work function metal layer  170  has a work function, and the work function can be between 4.8 eV and 5.2 eV, or alternatively between 3.9 eV and 4.3 eV. 
     Please refer to  FIG. 7 . Thereafter, a filling metal layer  172  filling up the first trench  166  and the second trenches  168  is formed on the substrate  100 . In the preferred embodiment, the filling metal layer  172  includes materials with low resistance and superior gap-filling characteristic. Additionally, a top barrier layer (not shown) can be formed between the work function metal layer  170  and the filling metal layer  172  if required. It is noteworthy that for improving the gap-filling result of the following formed metal materials, another patterned mask (not shown) can be formed in the first trench  166  and the second trenches  168  and a surface of the patterned mask is lower than the opening of the first trench  166  and the second trenches  168 . Accordingly, the work function metal layer  170 , the bottom barrier layer  110 , and the high-k dielectric layer  108  not covered by the patterned mask are removed and the remained work function metal layer  170 , the remained bottom barrier layer  110 , and the remained high-k dielectric layer  108  are left only in the first gate trench  166  and the second trenches  168 , particularly on the bottom and sidewalls of the first gate trench  166  and the second trenches  168 . That means a topmost portion of the high-k dielectric layer  108 , the bottom barrier layer  110 , and the work function metal layer  170  are lower than the opening of first trench  166  and the second trenches  168 , and consequently the gap-filling result of the following formed metal materials can be improved. 
     Please refer to  FIG. 8 . After forming the filling metal layer  172 , a CMP process is performed to remove the unnecessary filling metal layer  172  and work function metal layer  170 . Consequently, a metal gate  180  for the transistor  140  is formed in the first trench  166  and two metal structures  182  are formed in the second trench  168 . As shown in  FIG. 8 , the metal gate  180  and the metal structures  182  are multilayered structure. Furthermore, a resistor  150  having the polysilicon main portion  130 , the doped regions  118  and two metal structures  182  serving as a metal portion for the resistor  150  is formed in the resistor region  104 . It is noteworthy that each doped region  118  is sandwiched by the polysilicon main portion  130  and the metal portion  182 . Furthermore, a multilayered dielectric layer  190  and contacts  192 ,  194 , and  196  are sequentially formed as mentioned above and those details are omitted for simplicity. 
     According to the second preferred embodiment, the resistor  150  and the method for forming a resistor integrated with a transistor  140  having metal gate  180  not only benefits by the advantages described in the first preferred embodiment but also is easily integrated with the high-k last process. 
     Please refer to  FIGS. 9-12 , which are schematic drawings illustrating a method for forming a resistor integrated with a transistor having metal gate provided by a third preferred embodiment of the present invention. Please note that the third preferred embodiment is exemplarily described with the method integrated with the high-k first process, but those skilled in the art would easily realize that the method provided by the third preferred embodiment can be integrated with the high-k last process as mentioned in the second preferred embodiment. Furthermore, though only the resistor are illustrated in  FIGS. 9-12 , the steps for forming the transistor having metal gate can be easily realized by the description mentioned in the first and second preferred embodiment. And therefore elements the same in the first, second, and third preferred embodiments are designated by the same numerals. 
     Please refer to  FIG. 9 . A substrate  100  having a transistor region (as shown in  FIGS. 1-8 ) and a resistor region  104  defined thereon is provided. The substrate  100  also includes a plurality of STIs  106  for providing electrical isolation between devices. It is noteworthy that a STI  106  is formed in the resistor region  104 . A dielectric layer  108 , a bottom barrier layer  110 , and a semiconductor layer such as a polysilicon layer  112  are sequentially formed on the substrate  100 . Because the preferred embodiment is exemplarily integrated with the high-k first process, the dielectric layer  108  includes a high-k material as mentioned above and the bottom barrier layer  110  includes TiN, but not limited to this. Then, a patterned mask  114  is formed on the polysilicon layer  112 . The patterned mask  114  has two openings  114   a  and the openings  114   a  have a width W 1 . After forming the patterned mask  114 , an ion implantation  116  is performed to form two doped regions  118  in the polysilicon layer  112  in the resistor region  104 . Accordingly, the doped regions  118  include p-type dopants, but not limited to this. Furthermore, the doped regions  118  include the width W 1  inherited from the openings  114   a.    
     Please refer to  FIG. 10 . After forming the doped region  118 , the patterned mask  114  is removed and followed by patterning the polysilicon layer  112 , the bottom barrier layer  110 , and the dielectric layer  108 . Consequently, a polysilicon dummy gate (not shown) for a transistor is formed in the transistor region  102  and a polysilicon main portion  130  for a resistor (shown in  FIG. 12 ) is formed in the resistor region  104 . As shown in  FIG. 10 , the polysilicon main portion  130  is formed to have the two doped regions  118  respectively positioned its two opposite ends. In other words, the two doped regions  118  are separated from each other by the polysilicon main portion  130 . Then, elements of the transistor are sequentially formed as mentioned above. And a spacer  132  is formed on sidewalls of the doped regions  118 . Next, a CESL  160  and an ILD layer  162  are sequentially formed. Since the steps and material choices for the abovementioned elements are well-known to those skilled in the art, those details are omitted herein in the interest of brevity. 
     Please still refer to  FIG. 10 . After forming the CESL  160  and the ILD layer  162 , a planarization process is performed to remove a portion of the CESL  160  and a portion of the ILD layer  162  to expose the polysilicon dummy gate of the transistor and the polysilicon main portion  130 : Then, a patterned hard mask  164  is formed on the substrate  100 . As shown in  FIG. 10 , the patterned hard mask  164  exposes a portion of the doped regions  118  on the substrate  100 . 
     Please refer to  FIG. 11 . Next, a suitable etching process such as a dry etching process is performed. It is noteworthy that since an etching rate of the doped regions  118  which includes the polysilicon is different from that of the CESL  160 , the ILD layer  162  and the patterned hard mask  164  which include dielectric material, only the exposed doped regions  118  are removed. Consequently, two second trenches  168  are formed in resistor region  104 . It is noteworthy that the second trench  168  defined by the patterned hard mask  164 , the ILD layer  162  and the CESL  160  includes a width W 2 , and the width W 2  is always smaller than the width W 1  of the original doped regions  118 . Since the width W 2  of the second trenches  168  is smaller than the width W 1  of the doped region, it is ensured that the polysilicon main portion  130  is protected from the etching process, and thus damages to the polysilicon main portion  130  due to over etching is avoided. 
     It is further noteworthy that in the preferred embodiment, the doped regions  118  exposed to the dry etching are not entirely removed. As shown in  FIG. 11 , the doped regions  118  are remained on the sidewalls and bottoms of the second trenches  168 . Consequently, the doped regions  118  include an L shape after the dry etching process. 
     Please refer to  FIG. 12 . After forming the second trenches  168 , the patterned hard mask  164  is removed, and an etch stop layer (not shown) as mentioned above can be formed on the substrate  100 . Next, a work function metal layer  170  is formed in the first gate trench  166  and the second gate trenches  168 . The work function metal layer  170  can include suitable materials providing an appropriate work function for p-type transistor or n-type transistor. Therefore, the work function metal layer  170  has a work function, and the work function can be between 4.8 eV and 5.2 eV, or alternatively between 3.9 eV and 4.3 eV. 
     Please refer to  FIG. 12  again. Thereafter, a filling metal layer  172  filling up the second trenches  168  is formed on the substrate  100 . In the preferred embodiment, the filling metal layer  172  includes materials with low resistance and superior gap-filling characteristic. Additionally, a top barrier layer (not shown) can be formed between the work function metal layer  170  and the filling metal layer  172  if required. After forming the filling metal layer  172 , a CMP process is performed to remove the unnecessary filling metal layer  172  and work function metal layer  170 . Consequently, a metal gate for the transistor is formed and two metal structures  182  are formed in the second trench  168 . As shown in  FIG. 12 , the metal structures  182  are multilayered structure. Furthermore, a resistor  150  having the polysilicon main portion  130 , the doped regions  118  and two metal structures  182  serving as metal portions for the resistor  150  is formed in the resistor region  104 . It is noteworthy that each doped region  118  is sandwiched by the polysilicon main portion  130  and the metal portion  182 . Furthermore, a multilayered dielectric layer  190  and contacts  192 ,  194 , and  196  are sequentially formed as mentioned above and those details are omitted for simplicity. 
     According to the third preferred embodiment, the resistor  150  provided by the preferred embodiment includes the L-shaped doped region  118  horizontally in between the polysilicon main portion  130  and the metal portion  182 , and vertically in between the metal portion  182  and the bottom barrier layer  110 . It is concluded that the doped regions  118  render superior protection to the polysilicon main portion  130  and the bottom barrier layer  110 . 
     Accordingly, the present invention provides a method for forming a resistor integrated with a transistor having metal gate that is easily integrate with the gate last process, the high-k first process, and the high-k last process. In other words, the method provided by the present invention can easily integrate the resistor and the transistor having metal gate without increasing process complexity. Furthermore, according to the resistor and the method for forming a resistor integrated with a transistor having metal gate, the doped regions protect the polysilicon main portion of the resistor during the etching process, therefore the over etching problem is solved. Furthermore, a length of the doped region can be defined or decided depending on a required resistance. In other words, by adjusting the width of the doped region, a resistance of the resistor can be easily modified. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.