Patent Publication Number: US-10312273-B2

Title: Low temperature poly-silicon TFT substrate structure and manufacture method thereof

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a divisional application of co-pending patent application Ser. No. 14/758,964, filed on Jul. 2, 2015, which is a national stage of PCT application number PCT/CN2015/077159, filed on Apr. 22, 2015, claiming foreign priority of Chinese patent application number 201510139978.0, filed on Mar. 27, 2015. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a display technology field, and more particularly to a low temperature poly-silicon thin film transistor (TFT) substrate structure and a manufacture method thereof. 
     BACKGROUND OF THE INVENTION 
     The low temperature poly-silicon (LTPS) technology is the manufacture technology of the new generation TFT substrate. The most significant difference from the traditional amorphous silicon (a-Si) is that the response speed of the LTPS display is faster and possesses advantages of high brightness, high resolution and low electrical power consumption. The poly-silicon (poly-Si) possesses excellent electrical property, and better drive ability to the active matrix organic light emitting diode (AMOLED). Thus, the AMOLED display back plate based on the low temperature poly-silicon technology has been widely utilized at present. 
     The present manufacture method of the LTPS TFT substrate mainly comprises the following steps: 
     Step 1, as shown in  FIG. 1 , providing a substrate  100 , wherein the substrate  100  comprises a drive TFT area and a display TFT area, and depositing a buffer layer  110  on the substrate  100 ; 
     Step 2, as shown in  FIG. 2 , depositing an amorphous silicon layer on the buffer layer  110  and implementing an excimer laser annealing process to the amorphous silicon layer to make the amorphous silicon layer crystallized and converted to be a poly-silicon layer  130  after excimer laser annealing pretreatment; 
     Step 3, as shown in  FIG. 3 , patterning the poly-silicon layer  130  to obtain a first poly-silicon section  140  in the drive TFT area and a second poly-silicon section  150  in the display TFT area which are alternately spaced; 
     Step 4, depositing a gate isolation layer  160  on the first poly-silicon section  140 , the second poly-silicon section  150  and the buffer layer  110 ; 
     Step 5, depositing and patterning a first metal layer on the gate isolation layer  160 , and forming a first gate  170  and a second gate  180  respectively above the first poly-silicon section  140  and the second poly-silicon section  150  and corresponding thereto; 
     Step 6, depositing an interlayer insulation layer  190  on the gate isolation layer  160 , the first gate  170  and the second gate  180 , and forming a first via  200  and a second via  200 ′ in the interlayer insulation layer  190  and the gate isolation layer  160  respectively above the first poly-silicon section  140  and the second poly-silicon section  150  and corresponding thereto; and 
     Step 7, as shown in  FIG. 4 , depositing and patterning a second metal layer on the interlayer insulation layer  190 , and respectively forming a first source/drain  210  in the drive TFT area and a second source/drain  220  in the display TFT area, and the first source/drain  210  contacts with the first poly-silicon section  140  through the first via  200 , and the second source/drain  220  contacts with the second poly-silicon section  150  through the second via  200 ′. 
     In the above process, the excimer laser annealing (ELA) technology utilizes transient pulses of laser to irradiate on the surface of the amorphous silicon layer to be melted and recrystallized. The AMOLED driving requires a drive TFT and a display TFT. The drive TFT demands larger lattice and thus higher electron mobility is required. The display TFT needs efficient electron mobility and uniformity of the electrical current. Accordingly, the OLED element can uniformly illuminate. 
     However, the ELA crystallization technology according to prior art cannot achieve effective control to the uniformity of the lattices and the crystallization direction of the lattices. The distribution of crystallization condition in the entire substrate is extremely non-uniform and results in that the long distance of the display effect is not uniform. 
     SUMMARY OF THE INVENTION 
     An objective of the present invention is to provide a manufacture method of a low temperature poly-silicon TFT substrate structure, capable of controlling the crystallization process of the poly-silicon to make that the larger lattice dimension of the poly-silicon layer is formed in the drive TFT area in the crystallization process and raise the electron mobility. The fractured crystals of poly-silicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for different TFTs can be satisfied to raise the light uniformity of the OLED. 
     Another objective of the present invention is to provide a low temperature poly-silicon TFT substrate structure, of which the lattice dimension of the poly-silicon layer in the drive TFT area is larger and higher electron mobility is provided. The uniformity of the grain boundary is well and the uniformity of the current is higher. 
     For realizing the aforesaid objectives, the present invention provides a manufacture method of a low temperature poly-silicon TFT substrate structure, which comprises the following steps: 
     Step 1, providing a substrate, wherein the substrate comprises a drive TFT area and a display TFT area, and depositing a buffer layer on the substrate, and patterning the buffer layer to make a thickness of the buffer layer in the drive TFT area be larger than a thickness of the buffer layer in the display TFT area; 
     Step 2, depositing an amorphous silicon layer on the buffer layer, implementing an excimer laser annealing process to the amorphous silicon layer to make the amorphous silicon layer crystallized and converted to a poly-silicon layer after an excimer laser annealing pretreatment, and patterning the poly-silicon layer to obtain a first poly-silicon section in the drive TFT area and a second poly-silicon section in the display TFT area; 
     Step 3, depositing a gate isolation layer on the first poly-silicon section, the second poly-silicon section and the buffer layer; 
     Step 4, depositing and patterning a first metal layer on the gate isolation layer to form a first gate and a second gate respectively above the first poly-silicon section and the second poly-silicon section and corresponding thereto; 
     Step 5, depositing an interlayer insulation layer on the gate isolation layer, the first gate and the second gate and forming a first via and a second via in the interlayer insulation layer and the gate isolation layer to be respectively above the first poly-silicon section and the second poly-silicon section and corresponding thereto; and 
     Step 6, depositing and patterning a second metal layer on the interlayer insulation layer to respectively form a first source/drain in the drive TFT area and a second source/drain in the display TFT area, wherein the first source/drain contacts with the first poly-silicon section through the first via, and the second source/drain contacts with the second poly-silicon section through the second via. 
     A lattice dimension of the first poly-silicon section is larger than a lattice dimension of the second poly-silicon section. Fractured crystals in the second poly-silicon section outnumber fractured crystals in the first poly-silicon section. 
     The substrate comprises a glass substrate, and a material of the buffer layer comprises one of silicon oxide, silicon nitride, and a combination thereof. 
     The interlayer insulation layer is formed of a material comprising one of silicon oxide, silicon nitride, and a combination thereof. 
     A thickness difference between the buffer layers of the drive TFT area and the display TFT area is larger than 500 Å. 
     The present invention further provides a low temperature poly-silicon TFT substrate structure, which comprises a drive TFT area and a display TFT area, wherein the drive TFT area comprises a substrate, a buffer layer on the substrate, a first poly-silicon section on the buffer layer, a gate isolation layer on the buffer layer and the first poly-silicon section, a first gate on the gate isolation layer and above the first poly-silicon section and corresponding thereto, an interlayer insulation layer on the gate isolation layer and the first gate and a first source/drain on the interlayer insulation layer; 
     wherein the display TFT area comprises a substrate, a buffer layer on the substrate, a second poly-silicon section on the buffer layer, a gate isolation layer on the buffer layer and the second poly-silicon section, a second gate on the gate isolation layer and above the second poly-silicon section and corresponding thereto, an interlayer insulation layer on the gate isolation layer and the second gate and a second source/drain on the interlayer insulation layer; and 
     wherein a thickness of the buffer layer in the drive TFT area is larger than a thickness of the buffer layer in the display TFT area. 
     A lattice dimension of the first poly-silicon section is larger than a lattice dimension of the second poly-silicon section. Fractured crystals in the second poly-silicon section outnumber fractured crystals in the first poly-silicon section. 
     The substrate comprises a glass substrate, and a material of the buffer layer comprises one of silicon nitride, silicon oxide, and a combination thereof. A material of the interlayer insulation layer comprises one of silicon oxide, silicon nitride, and a combination thereof. 
     A first via is formed in the interlayer insulation layer and the gate isolation layer in the drive TFT area and above the first poly-silicon section and corresponding thereto, and the first source/drain contacts with the first poly-silicon section through the first via; and 
     a second via is formed in the interlayer insulation layer and the gate isolation layer in the display TFT area and above the second poly-silicon section and corresponding thereto, and the second source/drain contacts with the second poly-silicon section through the second via. 
     A thickness difference between the buffer layers of the drive TFT area and the display TFT area is larger than 500 Å. 
     The present invention further provides a low temperature poly-silicon TFT substrate structure, which comprises a drive TFT area and a display TFT area, wherein the drive TFT area comprises a substrate, a buffer layer on the substrate, a first poly-silicon section on the buffer layer, a gate isolation layer on the buffer layer and the first poly-silicon section, a first gate on the gate isolation layer and above the first poly-silicon section and corresponding thereto, an interlayer insulation layer on the gate isolation layer and the first gate and a first source/drain on the interlayer insulation layer; 
     wherein the display TFT area comprises a substrate, a buffer layer on the substrate, a second poly-silicon section on the buffer layer, a gate isolation layer on the buffer layer and the second poly-silicon section, a second gate on the gate isolation layer and above the second poly-silicon section and corresponding thereto, an interlayer insulation layer on the gate isolation layer and the second gate and a second source/drain on the interlayer insulation layer; 
     wherein a thickness of the buffer layer in the drive TFT area is larger than a thickness of the buffer layer in the display TFT area; 
     wherein a lattice dimension of the first poly-silicon section is larger than a lattice dimension of the second poly-silicon section; and fractured crystals in the second poly-silicon section outnumber fractured crystals in the first poly-silicon section; 
     wherein the substrate comprises a glass substrate; a material of the buffer layer comprises one of silicon nitride, silicon oxide, and a combination thereof; and a material of the interlayer insulation layer comprises one of silicon oxide, silicon nitride, and a combination thereof. 
     The benefits of the present invention are that the present invention provides a low temperature poly-silicon TFT substrate structure and a manufacture method thereof. By providing the buffer layers in the drive TFT area and the display TFT area with different thicknesses, wherein the thickness of the buffer layer in the drive TFT area is larger and the thickness of the buffer layer in the display TFT area is smaller, different temperature grades are formed in a crystallization process of poly-silicon to achieve control of the grain diameters of crystals. The poly-silicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of poly-silicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for different TFTs can be satisfied to raise the light uniformity of the OLED. 
     In order to better understand the characteristics and technical aspect of the invention, please refer to the following detailed description of the present invention is concerned with the diagrams, however, provide reference to the accompanying drawings and description only and is not intended to be limiting of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The technical solution and the beneficial effects of the present invention are best understood from the following detailed description with reference to the accompanying figures and embodiments. 
       In drawings, 
         FIG. 1  is a diagram of Step 1 of a known manufacture method of a low temperature poly-silicon TFT substrate structure; 
         FIG. 2  is a diagram of Step 2 of the known manufacture method of a low temperature poly-silicon TFT substrate structure; 
         FIG. 3  is a diagram of Step 3 of the known manufacture method of a low temperature poly-silicon TFT substrate structure; 
         FIG. 4  is a diagram of Step 7 of the known manufacture method of a low temperature poly-silicon TFT substrate structure; 
         FIG. 5  is a flowchart of a manufacture method of a low temperature poly-silicon TFT substrate structure according to the present invention; 
         FIGS. 6-7  are diagrams of Step 1 of the manufacture method of a low temperature poly-silicon TFT substrate structure according to the present invention; 
         FIGS. 8-9  are diagrams of Step 2 of the manufacture method of a low temperature poly-silicon TFT substrate structure according to the present invention; 
         FIG. 10  is a diagram of Step 3 of the manufacture method of a low temperature poly-silicon TFT substrate structure according to the present invention; 
         FIG. 11  is a diagram of Step 4 of the manufacture method of a low temperature poly-silicon TFT substrate structure according to the present invention; 
         FIG. 12  is a diagram of Step 5 of the manufacture method of a low temperature poly-silicon TFT substrate structure according to the present invention; and 
         FIG. 13  is a diagram of Step 6 of the manufacture method of a low temperature poly-silicon TFT substrate structure according to the present invention and is also a sectional diagram of a low temperature poly-silicon TFT substrate structure according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings and the specific embodiments. 
     Referring to  FIG. 5 , the present invention first provides a manufacture method of a low temperature poly-silicon TFT substrate structure, which comprises the following steps: 
     Step 1, as shown in  FIGS. 6-7 , providing a substrate  1 , wherein the substrate  1  comprises a drive TFT area and a display TFT area, depositing a buffer layer  11  on the substrate  1 , and patterning the buffer layer  11  to make a thickness of the buffer layer  11  in the drive TFT area larger than a thickness of the buffer layer  11  in the display TFT area. 
     Specifically, the substrate  1  is a glass substrate, and a material of the buffer layer  11  is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. 
     By providing the buffer layers  11  in the drive TFT area and the display TFT area with different thicknesses, different temperature grades are formed in a crystallization process of the poly-silicon so as to achieve control of the grain diameters of crystals. 
     Preferably, a thickness difference between the buffer layer  11  of the drive TFT area and the buffer layer  11  of the display TFT area is larger than 500 Å. 
     Step 2, as shown in  FIGS. 8-9 , depositing an amorphous silicon layer on the buffer layer  11   p ; implementing an excimer laser annealing process to the amorphous silicon layer to make the amorphous silicon layer crystallized and converted to a poly-silicon layer  12  after excimer laser annealing pretreatment, and patterning the poly-silicon layer  12  to obtain a first poly-silicon section  14  in the drive TFT area and a second poly-silicon section  15  in the display TFT area. 
     In the excimer laser annealing process, the thicker buffer layer  11  in the drive TFT area can form a better insulating course. The temperature of the poly-silicon is higher, and the fusion is complete. The insulating effect of the thinner buffer layer  11  in the display area is next. The temperature of the poly-silicon is lower, and the fusion is incomplete. Thus, different temperature grades are formed in the crystallization process of the poly-silicon to achieve the control to the grain diameters of the crystals. The poly-silicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of poly-silicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for different TFTs can be satisfied to raise the light uniformity of the OLED. 
     Therefore, in this embodiment, a lattice dimension of the first poly-silicon section  14  is larger than a lattice dimension of the second poly-silicon section  15 ; fractured crystals in the second poly-silicon section  15  are more than fractured crystals in the first poly-silicon section  14 . 
     Step 3, as shown in  FIG. 10 , depositing a gate isolation layer  16  on the first poly-silicon section  14 , the second poly-silicon section  15  and the buffer layer  11 . 
     Step 4, as shown in  FIG. 11 , depositing and patterning a first metal layer on the gate isolation layer  16 , and forming a first gate  17  and a second gate  18  respectively above the first poly-silicon section  14  and the second poly-silicon section  15  and corresponding thereto. 
     Step 5, as shown in  FIG. 12 , depositing an interlayer insulation layer  19  on the gate isolation layer  16 , the first gate  17  and the second gate  18 , and forming a first via  20  and a second via  20 ′ in the interlayer insulation layer  19  and the gate isolation layer  16  respectively above the first poly-silicon section  14  and the second poly-silicon section  15  and corresponding thereto. 
     Specifically, a material of the interlayer insulation layer  19  is silicon oxide, silicon nitride, or a combination thereof. 
     Step 6, as shown in  FIG. 13 , depositing and patterning a second metal layer on the interlayer insulation layer  19  to respectively form a first source/drain  21  in the drive TFT area and a second source/drain  22  in the display TFT area, wherein the first source/drain  21  contacts with the first poly-silicon section  14  through the first via  20  and the second source/drain  22  contacts with the second poly-silicon section  15  through the second via  20 ′. 
     The aforesaid manufacture method of the low temperature poly-silicon TFT substrate structure provides the buffer layers in the drive TFT area and the display TFT area with different thicknesses, wherein the thickness of the buffer layer in the drive TFT area is larger and the thickness of the buffer layer in the display TFT area is smaller. Thus, different temperature grades are formed in the crystallization process of the poly-silicon to achieve control of the grain diameters of crystals. The poly-silicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of poly-silicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for different TFTs can be satisfied to raise the light uniformity of the OLED. 
     Referring to  FIG. 13 , the present invention further provides a low temperature poly-silicon TFT substrate structure, which comprises a drive TFT area and a display TFT area. The drive TFT area comprises a substrate  1 , a buffer layer  11  on the substrate  1 , a first poly-silicon section  14  on the buffer layer  11 , a gate isolation layer  16  on the buffer layer  11  and the first poly-silicon section  14 , a first gate  17  on the gate isolation layer  16  and above the first poly-silicon section  14  and corresponding thereto, an interlayer insulation layer  19  on the gate isolation layer  16  and the first gate  17  and a first source/drain  21  on the interlayer insulation layer  19 . 
     The display TFT area comprises a substrate  1 , a buffer layer  11  on the substrate  1 , a second poly-silicon section  15  on the buffer layer  11 , a gate isolation layer  16  on the buffer layer  11  and the second poly-silicon section  15 , a second gate  18  on the gate isolation layer  16  and above the second poly-silicon section  15  and corresponding thereto, an interlayer insulation layer  19  on the gate isolation layer  16  and the second gate  18  and a second source/drain  22  on the interlayer insulation layer  19 . 
     A thickness of the buffer layer  11  in the drive TFT area is larger than a thickness of the buffer layer  11  in the display TFT area. 
     A lattice dimension of the first poly-silicon section  14  is larger than a lattice dimension of the second poly-silicon section  15 ; fractured crystals in the second poly-silicon section  15  are more than fractured crystals in the first poly-silicon section  14 . 
     Specifically, a first via  20  is formed in the interlayer insulation layer  19  and the gate isolation layer  16  in the drive TFT area and above the first poly-silicon section  14  and corresponding thereto, and the first source/drain  21  contacts with the first poly-silicon section  14  through the first via  20 . 
     A second via  20 ′ is formed in the interlayer insulation layer  19  and the gate isolation layer  16  in the display TFT area and above the second poly-silicon section  15  and corresponding thereto, and the second source/drain  22  contacts with the second poly-silicon section  15  through the second via  20 ′. 
     Specifically, the substrate  1  is a glass substrate. 
     Specifically, a material of the buffer layer  11  is silicon nitride, silicon oxide, or a combination thereof; and a material of the interlayer insulation layer  19  is silicon oxide, silicon nitride or a combination thereof. 
     Preferably, a thickness difference between the buffer layer  11  of the drive TFT area and the buffer layer  11  of the display TFT area is larger than 500 Å. 
     In the aforesaid low temperature poly-silicon TFT substrate structure, the buffer layers in the drive TFT area and the display TFT area have different thicknesses, wherein the thickness of the buffer layer in the drive TFT area is larger and the thickness of the buffer layer in the display TFT area is smaller. Different temperature grades are formed in the crystallization process of the poly-silicon. The poly-silicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The uniformity of the grain boundary of the poly-silicon layer in the display TFT area is better in the crystallization process. The uniformity of the current is better. The electrical property demands for different TFTs can be satisfied to raise the light uniformity of the OLED. 
     In summary, the low temperature poly-silicon TFT substrate structure and the manufacture method thereof according to the present invention provides the buffer layers in the drive TFT area and the display TFT area with different thicknesses, wherein the thickness of the buffer layer in the drive TFT area is larger and the thickness of the buffer layer in the display TFT area is smaller. Different temperature grades are formed in the crystallization process of the poly-silicon to achieve control of the grain diameters of crystals. The poly-silicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of poly-silicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for different TFTs can be satisfied to raise the light uniformity of the OLED. 
     The above provide only specific embodiments of the present invention. The scope of the present invention is not limited to these embodiments. For those skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.