Patent Publication Number: US-2021167743-A1

Title: Fast amplitude detector and automatic gain control

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of priority to U.S. Patent Application Ser. No. 62/275,040, filed Jan. 5, 2016, which is incorporated herein by reference in its entirety. 
    
    
     FEDERAL FUNDING 
     This invention was made with government support under grant IIS-1418497 awarded by the National Science Foundation. The government has certain rights in the invention. 
    
    
     BACKGROUND 
     Amplitude detectors are ubiquitous in radio and other systems; however most such detectors require many cycles of an alternating current (AC) input signal to determine a level of the input signal. Automatic Gain Control (AGC) circuits, circuits that adjust gain of an amplifier according to an amplitude of an incoming AC input signal, are also ubiquitous in radio and other systems, and require at least one amplitude detector to determine a level of the AC signal; again, most such circuits require many cycles of the incoming signal to determine changes in level of the signal and adjust gain of the amplifier to compensate for those changes. 
     SUMMARY 
     An amplitude detector has a 90-degree phase shifter, such as one using an analog differentiator and an adjustable gain stage or one using a determinable delay. The phase shifter is coupled to shift phase of an input signal to the amplitude detection apparatus. The detector also has a first analog multiplier coupled to square the input signal, a second analog multiplier coupled to square output of the phase shifter, and an analog adder coupled to sum outputs of the first and second analog multiplier. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an automatic gain control circuit (AGC) of the present invention 
         FIG. 2  is a phase versus magnitude plot for a differentiator-based phase shifter of the present design. 
         FIG. 3  is a schematic diagram of a fast amplitude detector circuit, as implemented in a CMOS integrated circuit process. 
         FIG. 4A  and  FIG. 4B  illustrate block diagrams of alternative phase-shift networks for use in the fast amplitude detector or AGC circuit. 
         FIG. 5  is a schematic diagram of a power conditioning system using the present fast amplitude detector circuit. 
         FIG. 6  is a block diagram of an electrical impedance tomography unit using the present AGC circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hardware 
     A fast amplitude detection circuit  102  forming part of gain controller  103 , and a fast-responding automatic gain control circuit  100  using the gain controller  103  and fast amplitude detection circuit  102 , operates on a sinusoidal input signal  104 . 
     The gain controller  103  may in some embodiments filter an input signal  104 , the fast amplitude detection circuit  102  then phase-shifts the input signal  104  by 90 degrees in a phase-shift network  105 . In an embodiment, phase-shift network  105  has a differentiator  106  and a gain stage  108  to perform the phase shift and adjust gain for frequency-dependent amplitude response of the differentiator, the phase-shifted and gain adjusted signal is then squared in an analog multiplier  110 . In an alternative embodiment, phase-shift network  105  delays the input signal by one-quarter period to achieve a 90-degree phase shift, and the phase-shifted signal is squared in analog multiplier  110 . The circuit also squares the un-phase-shifted input signal  104  in an analog multiplier  112 . The squared input and squared phase-shifted signal are then summed in an analog adder  114  to provide a signal  116  representing a square of amplitude of the incoming signal  104 . In some embodiments, a square root  117  of signal  116  is taken to provide a signal  118  directly proportional to amplitude of the input signal  104 . 
     In some embodiments, where controllable amplifier  120  is digitally controlled or analog-to-digital conversion is used with the amplitude detection circuit in an automatic gain control circuit, an analog-to-digital converter  119 , which may be a fast converter of the “Flash” type, is used to digitize the sum from adder  114  and provide a gain control signal  122  to controllable amplifier  120  in feed-forward configuration; in embodiments having analog gain control inputs, output of the adder  114  may provide gain control of a voltage controlled controllable amplifier  120  directly. In alternative embodiments, the input to amplitude detector  102  is taken from amplifier  120 , and gain of the amplifier  120  is controlled in feedback configuration. Amplifier  120  provides an output  124  of the automatic gain controlled amplifier system. 
     The differentiator  106  of the phase shift network  105  has gain that is dependent on values of resistors and capacitors of the differentiator, as well as frequency of the input signal  104 ; a trim circuit  130  is provided to allow for adjustment of gain stage  108  of the phase-shift network to allow compensation for this variation. In a particular embodiment, where the amplitude detector  102  is fabricated on a monolithic integrated circuit for operation at fixed frequency, trim circuit  130  is adapted to be laser-trimmed, and when trimmed provides appropriate feedback resistances and reference current to current sources in gain stage  108  so gain stage  108  has to compensate for fabrication variations and to adjust gain stage  108  of the phase shift network to tune the phase shift network for a predetermined target frequency, such as an intermediate frequency (IF) of a communications receiver. In an alternative embodiment where the amplitude detector  102  is part of a system incorporating a processor (not shown) having a memory, the memory of the processor stores a calibration constant determined during a calibration procedure such as may be done during manufacture of the system. When the system starts operation, the processor writes the calibration constant to a register in trim circuit  130 , trim circuit  130  then provides appropriate feedback resistances and reference current to current sources in gain stage  108  so the gain stage properly compensates the phase shift network for the predetermined target frequency, 
     In a particular embodiment, where it is desired to adjust gain of a system rapidly for signal acquisition, but where amplitude of the input signal is not expected to change rapidly or at all, the amplitude detector  102  receives power from an on-chip power-enabling circuit and is turned off after gain settings have been assigned to the amplifier  120 . 
     In another embodiment, in order to prevent response to high-voltage noise spikes, a noise-blanking or median filter  132  is provided and configured to suppress such noise spikes. 
     Alternative 90-degree phase-shift networks for use in the fast amplitude detector are illustrated in  FIG. 4A and 4B ; since squaring is performed by the circuitry of squaring block  110  ( FIG. 1 ) or the squaring-sum-and-root unit illustrated in  FIG. 3  either the +90-degree phase shift of  FIG. 4A  or the −90-degree phase shift of  FIG. 4B  will function in the circuit. 
     Since a first derivative of a sine wave represents a frequency-dependent constant times a 90-degree phase-shifted derivative of the sine wave, the +90-degree phase shift of  FIG. 4A  uses a differentiator  402  such as often implemented by passing an input signal IN through a capacitor into an inverting input of an amplifier, with feedback taken through a resistor to the inverting input. To adjust for the frequency-dependent gain of differentiator  402 , input signal IN is provided to a frequency detector  404 ; in fixed frequency embodiments or those where frequency is known, frequency detector  404  may be omitted or frequency identification provided from another source. Detected or externally-provided frequency  405  is provided through in some embodiments a ROM-based table  408  and DAC to control gain of a controllable-gain amplifier  410 . Controllable-gain amplifier  410  amplifies differentiator  402  output, or an output of a noise filter  412  coupled to differentiator  402  output, by a factor determined to compensate for the frequency-dependent gain of differentiator  402  to provide phase-shifted output  418 . 
     In the alternative embodiment  430  of the phase-shift network illustrated in in  FIG. 4B , an all-pass filter  432  having a controllable delay delays input IN to provide output  436 . In variable-frequency embodiments, a frequency detector  434  is provided to compensate gain of filter  432 . 
     Theory 
     The present device performs an operation according to 
         M=k (cosine(Ø) 2 +sine(Ø) 2 )
 
     Where M is a square of amplitude of the incoming signal, Ø is an instantaneous phase of the incoming signal, and k is a constant. By the Pythagorean theorem, an amplitude of the incoming signal is given as m=Square-Root(M). 
     In an alternative embodiment, an analog square-root circuit  117  is inserted into the amplitude detector immediately after analog adder  114  so that an output of the square-root circuit is linearly proportional to amplitude of the incoming signal. 
     Results Achieved 
     (1) We designed, simulated, fabricated, and tested a fast amplitude detection circuit using data from a semiconductor foundry. A schematic diagram of squaring, summing, and square-rooting circuits of this circuit are shown in  FIG. 3 , where INA, INAx are a differential mode input corresponding to output of phase shifter  105  ( FIG. 1 ), and INC, INCx is a differential mode input corresponding to output of median filter  132 ( FIG. 1 ). On  FIG. 3 , AVSS is an analog ground, AVDD is an analog power supply, and VOUT is a summed and square-rooted magnitude signal corresponding to signal  118 , signal directly proportional to amplitude of the input signal  104 . Associated bias circuits are omitted for clarity. 
     (2) We designed an electronic readout front end system that uses the proposed fast amplitude detector. 
     The readout front end can process input signals within the amplitude range 1 mV to 1 V, and at frequencies of 100 Hz to 10 MHz, resolving amplitude within about one tenth of a cycle at low frequencies. 
     (3) Our results show that this read-out system is able to estimate the input amplitude and determine corresponding gain settings within a fraction of the input period, regardless of the input phase at time of amplitude change on the input. 
     (4) All of our circuits can be implemented by most analog or mixed-signal semiconductor processes and the design could easily adapt to become part of a larger “system on a chip.” 
     A particular embodiment of the system tuned for operation at 100 Hz has phase-shift  150  and amplitude  152  versus frequency response as illustrated in  FIG. 2 . 
     Applications 
     The fast amplitude detector and AGC system herein described can be used in many applications including controlling an intermediate frequency amplifier of a single or multiple-conversion superheterodyne receiver. It may also be used in a fast-response uninterruptable power supply, as illustrated in  FIG. 5 , or in an electrical-impedance imaging tomography system, as illustrated in  FIG. 6 . 
     In a fast-response uninterruptible power supply  550 , a powerline-frequency (typically 50 or 60 Hz), AC  552  is received, typically through a mains connector  552 . In normal operation, AC  552  couples through a fast solid-state transfer switch  554  to output  556 , where it may be used to power computers and other sensitive electronic devices (not shown). AC  552  also couples to a fast amplitude detector  558 , as herein described with reference to  102  on  FIG. 1  to provide an amplitude signal  560 , which is digitized by an ADC  562  or alternatively compared to limits (not shown), and digitized amplitude or out-of-tolerance signals provided to a processor  564 . When processor  564  determines that a voltage drop-out occurs, such as when amplitude of AC  552  fails to meet requirements of the sensitive electronic devices, processor  564  trips transfer switch  554  to couple output  556  to a high-power DC-AC conversion amplifier  566  coupled to draw power from battery  568 , and configures waveform synthesizer  570  to begin providing a reference waveform for amplifier  566  that begins in phase with AC  552 ; thereby providing power to a load connected to output  556 . Using our fast amplitude detector, we expect uninterruptable power supply  550  output  556  to recover within a tenth of a cycle upon voltage dropouts on AC  152 . 
     The AGC unit herein described is also of use in an electrical impedance imaging system  500  as illustrated in  FIG. 6 . Each electrode or probe  526  of system  500  couples through voltage and current sensing circuit  501  to provide sensed voltage or current  503  to a signal conditioning with AGC block  502 . Within signal conditioning with AGC block  502 , sensed voltage or current  503  feeds an amplitude detector  507  having a 90-degree phase shifter  505  where it couples into differentiator  504 . Differentiator  504  provides a first derivative signal to a gain block  506 . Since frequency must be adjustable to match stimulus frequency, gain block  506  has an adjustable gain controlled by a processor  509  to a gain that compensates for frequency dependences of phase shifter  505 . Phase shifter  505  gain block  506  provides output to a squaring circuit  508 . 
     A second squaring circuit  510  is fed by sensed voltage or current  503 , and outputs of both squaring circuits  508 ,  510  are summed and a square root extracted by sum &amp; root unit  512 . The extracted square root is processed by ADC  514  and table  516  to control gain of gain amplifier  518  that provides a multichannel ADC  520  with a conditioned signal derived from sensed voltage or current  503 . 
     In system  500 , processor  509  also controls frequency synthesizer  522  to provide a particular frequency of the multiple frequencies at which impedance is measured in sequence by system  500  to probe driver  524  for driving stimulus probes of probes  526 . As there are multiple probes, additional copies  530 ,  532  of Signal Conditioning with AGC block  502  are provided to condition current and voltage signals for each probe of system  500 . Processor  509  uses outputs of multichannel ADC, and knowledge of probe layout, to reconstruct a three-dimensional image of impedances within tissue of a patient. 
     Combinations 
     The various features herein described can be combined in several ways. For example, either phase shifter can be used for various applications with or without the A/D or table, and with the frequency detector or with other ways to identify frequency such as fixed frequency IF or programmable synthesizer devices. Particular anticipated combinations include: 
     An amplitude detection apparatus designated A including a phase shifter coupled to phase shift an input signal and an adjustable gain stage; a first analog multiplier coupled to square the input signal; a second analog multiplier coupled to square an output of the phase shifter; and an analog adder coupled to sum outputs of the first and second analog multiplier. 
     An amplitude detection apparatus designated AA including the amplitude detection apparatus designated A further comprising an analog square root circuit coupled to receive an output of the analog adder. 
     An amplitude detection apparatus designated AB including the amplitude detection apparatus designated A or AA wherein the amplitude detector is fabricated upon a monolithic integrated circuit, and further comprising trim circuitry adapted to compensate for manufacturing variation by adjusting gain of the gain stage of the phase shifter. 
     An automatic gain control circuit designated B including the amplitude detection apparatus designated A, AA, or AB coupled to control gain of a controllable amplifier. 
     An automatic gain control circuit designated BA including the automatic gain control circuit designated B wherein the controllable amplifier is digitally controlled, and further including: an analog-to-digital converter coupled to convert an analog output of the analog adder into a digital signal, the digital signal coupled to control the controllable amplifier. 
     An automatic gain control circuit designated BB including the automatic gain control circuit designated B or BA wherein the phase shifter comprises an all-pass filter delay unit. 
     An amplitude detection apparatus designated AC including the amplitude detection apparatus designated A, AA, or AB, wherein the phase shifter comprises an analog differentiator and an adjustable gain stage, the analog differentiator coupled to differentiate an input signal to the amplitude detection apparatus, the adjustable gain stage being configured to compensate for frequency dependent gain of the analog differentiator. 
     An amplitude detection apparatus designated AD including the amplitude detection apparatus designated A, AA, AB, or C further including an analog square root circuit coupled to receive an output of the analog adder. 
     An amplitude detection apparatus designated AE including the amplitude detection apparatus designated A, AA, AB, AC, or AD, wherein the amplitude detector is fabricated upon a monolithic integrated circuit, and further comprising trim circuitry adapted to compensate for manufacturing variation by adjusting gain of the gain stage of the phase shifter. 
     An automatic gain control circuit designated ABA including the amplitude detection apparatus designated A, AA, AB, AC, AD, or AE coupled to control gain of a controllable amplifier. 
     An uninterruptable power supply designated ACA including the amplitude detection apparatus designated A, AA, AB, AC, AD, or AE, wherein the uninterruptable power supply is configured to provide power from a battery to its output when the amplitude detection apparatus detects a dropout of an alternating-current power. 
     An electrical impedance imaging apparatus designated ADA including the automatic gain control circuit designated ABA coupled to condition voltage or current signals from electrodes of the electrical impedance imaging apparatus. 
     A method designated C of providing fast-response automatic gain control of an amplifier coupled to receive an input signal including phase-shifting the input signal to generate a phase-shifted input signal; squaring the phase-shifted input signal to provide a squared phase-shifted input signal; squaring the input signal to provide a squared input signal; summing the squared phase-shifted input signal and the squared input signal, and performing a square root to produce a magnitude signal; and using the magnitude signal to control gain of an amplifier coupled to amplify the input signal. 
     A method designated CA including the method designated C, further including compensating for frequency dependence of gain of the circuitry used to perform the phase shift. 
     A method designated CB including the method designated CA, wherein a frequency detection circuit is used to control the compensating for frequency dependence of gain of the circuitry used to perform the phase shift. 
     CONCLUSION 
     Changes may be made in the above methods and systems without departing from the scope hereof. It should thus be noted that the matter contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween.