Patent Publication Number: US-5422316-A

Title: Semiconductor wafer polisher and method

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to semiconductor wafer shaping, and more particularly to semiconductor wafer polishers for polishing the faces of semiconductor wafers. 
     The final step in a conventional semiconductor wafer shaping process is a polishing step to produce a highly reflective and damage-free surface on one face, and sometimes both faces, of the semiconductor wafer. Polishing of the wafer is accomplished by a mechanochemical process in which a rotating polishing pad rubs a polishing slurry against the wafer. The slurry includes fine silica particles (mechanical action) suspended in an alkali solution (chemical action). 
     Semiconductor electronic devices are fabricated from polished semiconductor wafers. The requirement for geometrical tolerance of the polished wafer has become more stringent as the complexity of device design has increased. Microscopic device geometries require each wafer to have a predetermined uniform thickness and to have at least one face which deviates less than one micrometer from the highest point to the lowest point when the wafer is held on a flat vacuum chuck. 
     SUMMARY OF THE INVENTION 
     Among the several objects of this invention may be noted the provision of improved semiconductor wafer polisher and method for polishing wafers to a predetermined thickness; the provision of such a polisher and method utilizing a polishing limiter for preventing wafers from being reduced beyond the predetermined thickness. 
     In general, a semiconductor wafer polisher of the present invention is adapted for polishing at least one semiconductor wafer having first and second opposite faces. The polisher is adapted to polish the first face of the semiconductor wafer to flatten the first face and reduce the thickness of the wafer from an initial thickness t 1  to a predetermined final thickness t 2 . The final thickness t 2  is thinner than the initial thickness t 1 . The polisher comprises a first table having a first plate and a first surface on the first plate. The first surface includes a planar first surface portion adapted to abut the first face of the semiconductor wafer. The polisher also has a second surface including a planar second surface portion adapted to abut the second face of the semiconductor wafer. At least one of the first and second surfaces is rotatable about an axis to effectuate relative rotation between the planar first and second surface portions. The first and second surface portions lie in respective parallel planes. The first surface portion comprises a planar polishing surface. The relative rotation between the first and second surfaces effectuates relative rotation between the polishing surface and the first face of the semiconductor wafer for polishing the first face. The planar polishing surface and the second surface portion are urged toward each other to press the first face of the semiconductor wafer and the polishing surface against each other such that the planar polishing surface rubs against the first face of the semiconductor wafer upon rotation of the polishing surface relative to the semiconductor wafer to wear against the first face of the semiconductor wafer. The polishing surface and the second surface portion move axially toward each other as the semiconductor wafer is reduced in thickness. The polisher further includes a wafer carrier for holding the semiconductor wafer between the polishing surface and the second surface portion. A polishing limiter is between the first and second surfaces for limiting the reduction in thickness of the wafer and is integrally formed with the wafer carrier such that the polishing limiter and wafer carrier constitute a single unitary piece. The polishing limiter has at least one rubbing surface adapted for rubbing against one of the first and second surfaces. The polishing limiter is sized and configured such that the rubbing surface is spaced axially from the one of the first and second surfaces when the semiconductor wafer has the thickness t 1  and such that the rubbing surface rubs against the one of the first and second surfaces and the polishing limiter extends from the second surface to the first surface when the semiconductor wafer has the thickness t 2 . The polishing limiter has a greater resistance to polishing than that of the semiconductor wafer such that the polishing limiter prevents the polishing surface and the second surface portion from further moving axially toward each other when the polishing limiter extends from the second surface to the first surface to prevent the wafer from being reduced in thickness beyond the thickness t 2 . 
     In another aspect of the present invention, a method of polishing a semiconductor wafer comprises supporting the semiconductor wafer with a wafer carrier having a support plate and a generally planar wafer holding surface on the support plate. The second face of the wafer is held against the holding surface. A polishing table is positioned against the first face of the semiconductor wafer. The polishing table has a polishing plate and a planar polishing surface on the polishing plate lying in a plane parallel to the planar wafer holding surface. The planar polishing surface abuts the first face of the semiconductor wafer. At least one of the wafer carrier and polishing table is rotatable about an axis to effectuate relative rotation between the wafer carrier and polishing table. Reduction in thickness of the semiconductor wafer is limited with a polishing limiter. The polishing limiter is integrally formed with one of the support plate and polishing plate such that the polishing limiter and the one of the support plate and polishing plate constitute a single unitary piece. The polishing limiter extends axially from the one of the support plate and polishing plate toward the other of the support plate and polishing plate and has a plate rubbing surface adapted for rubbing against the other of the support plate and polishing plate. The polishing limiter is sized and configured such that the plate rubbing surface is axially spaced from the other of the support plate and polishing plate when the semiconductor wafer has the thickness t 1  and such that the plate rubbing surface rubs against the other of the support plate and polishing plate when the semiconductor wafer has been reduced to the thickness t 2 . The plate rubbing surface has a greater resistance to polishing than that of the semiconductor wafer such that the polishing limiter prevents the wafer holding surface and the polishing surface from moving axially toward each other when the plate rubbing surface rubs against the other of the support plate and polishing plate to prevent the wafer from being reduced in thickness beyond the thickness t 2 . At least one of the wafer carrier and the polishing table are rotated about the axis to effectuate relative rotation between the polishing surface and the first face of the semiconductor wafer. The planar wafer holding surface and the planar polishing surface are urged toward each other during relative rotation between the polishing surface and the first face of the semiconductor wafer to press the first face of the semiconductor wafer and the polishing surface against each other such that the planar polishing surface rubs against the first face of the semiconductor wafer to wear against the first face of the semiconductor wafer. The wafer holding surface and the polishing surface move axially toward each other as the semiconductor wafer is reduced in thickness and until the semiconductor wafer has been reduced to the thickness t 2 . The plate rubbing surface rubs against the other of the support plate and polishing plate when the semiconductor wafer has been reduced to the thickness t 2  to prevent the wafer holding surface and the polishing surface from further moving axially toward each other thereby to prevent the wafer from being reduced in thickness beyond the thickness t 2 . 
     Other objects and features will be in part apparent and in part pointed out hereinafter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a top plan view of a semiconductor polisher of the present invention with portions broken away to show detail; 
     FIG. 2 is a section view taken along the plane of line 2--2 of FIG. 1 showing semiconductor wafers held by a wafer carrier; 
     FIG. 3 is a vertical section view similar to FIG. 2 but with the semiconductor wafers having been reduced in thickness equal to the thickness of the wafer carrier; 
     FIG. 4 is a vertical section view of another preferred embodiment of the present invention showing dummy wafers and semiconductor wafers in a staggered configuration; 
     FIG. 5 is a vertical section view of the polisher of FIG. 4 but with the semiconductor wafers having been reduced in thickness equal to the thickness of the dummy wafers; 
     FIG. 6 is a top plan view of a further embodiment of a semiconductor wafer polisher of the present invention with portions broken away to show detail; 
     FIG. 7 is a section view taken along the plane of line 7--7 of FIG. 6 showing semiconductor wafers bonded to a wafer carrier; and 
     FIG. 8 is a vertical section view similar to FIG. 7 but with the semiconductor wafers having been reduced in thickness equal to the thickness of the wafer carrier. 
     Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings, and first more particularly to FIGS. 1-3, a semiconductor wafer polisher of the present invention, indicated in its entirety by the reference numeral 20, is adapted for polishing a plurality of semiconductor wafers 22. Each semiconductor wafer 22 has an upper face 24 and a lower face 26. The polisher 20 is a double sided polisher adapted to polish both faces of each semiconductor wafer 22 to flatten each face and reduce the thickness of the wafer from an initial thickness t 1  (FIG. 2) to a predetermined final thickness t 2 . Although the initial thickness of each semiconductor wafer shown in FIG. 2 is the same, it is to be understood that the initial thickness may vary from wafer to wafer. However, the final thickness t 2  is thinner than the initial thickness t 1  of any semiconductor wafer to be polished. 
     The polisher 20 comprises upper (or first) and lower (or second) polishing tables 28, 30, respectively, and a wafer carrier 32. The upper polishing table 28 has an upper (or first) plate 34 and an upper polishing pad 36 on the upper plate. The upper polishing pad 36 includes a downwardly facing surface 38 having a planar first surface portion 40 adapted to abut and rub against the upper face 24 of each semiconductor wafer 22. The lower polishing table 30 has a lower (or second) plate 42 and a lower polishing pad 44 on the lower plate. The lower polishing pad 44 includes an upwardly facing surface 46 having a planar second surface portion 48 adapted to abut and rub against the lower face 26 of each semiconductor wafer 22. Preferably, the upper and lower polishing pads 36, 44 are of a polyurethane impregnated polyester felt or other suitable material. The first and second surface portions 40, 48 of the upper and lower polishing pads 36, 44 comprise upper and lower planar polishing surfaces 50, 52, respectively. The upper and lower polishing surfaces lie in respective parallel planes so that the upper and lower faces 24, 26 of the semiconductor wafers 22 (when polished) will lie in parallel planes and the thickness of the wafers 22 will be uniform. The upper and lower tables 28, 30 are both rotatable about an axis X (FIG. 1) which is perpendicular to the planes of the first and second surface portions 40, 48. The tables 28, 30 are adapted to counter-rotate during polishing of the semiconductor wafers 22 with the upper table 28 rotating counterclockwise as viewed in FIG. 1 and the lower table 30 rotating clockwise. 
     The wafer carrier 32 holds the semiconductor wafers 22 between the upper and lower polishing surfaces 50, 52 during polishing and comprises a generally circular plate 54 with a plurality of openings 56 for receiving the semiconductor wafers 22. Preferably, the openings 56 are sized and shaped for limiting lateral movement of the wafers 22 relative to the carrier 32 while allowing free rotation of the wafers within the openings. The wafer carrier is positioned axially between the upper and lower polishing surfaces 50, 52 and laterally between a sun gear 58 and a ring gear 60 (FIG. 1). A plurality of gear teeth 62 extend radially outwardly at the periphery of the circular plate 54 and intermesh with gear teeth of the sun and ring gears. The sun and ring gears rotate about the axis X and turn the carrier 32. Preferably, the sun and ring gears 58 and 60 rotate in the same direction (e.g., clockwise as viewed in FIG. 1) but at different rotational speeds (i.e., different rpms) to cause the carrier 32 to rotate about its center point and also revolve around the axis X. 
     Rotation of the upper table 28, lower table 30, sun gear 58 and ring gear 60 causes relative rotation between the upper polishing surface 50 and the upper faces 24 of the wafers 22 and relative rotation between the lower polishing surface 52 and the lower faces 26 of the wafers. The upper and lower tables 28, 30 are urged toward each other by the weight of the upper table and/or by other conventional means to press the upper polishing surface 50 against the upper faces 24 and press the lower polishing surface 52 against the lower faces 26 so that the upper polishing surface rubs against the upper faces and the lower polishing surface rubs against the lower faces upon rotation of the polishing surfaces to wear against the faces of the wafers. As the upper and lower faces 24, 26 of the semiconductor wafers are polished, the thickness of the wafers decreases and the polishing surfaces move axially toward each other. Preferably, the respective speeds of the upper table 28, lower table 30, sun gear 58 and ring gear 60 are selected to provide substantially uniform polishing rates of the upper face 24 and lower face 26 of each wafer 22. 
     The circular plate 54 of the wafer carrier 32 constitutes a polishing limiter 64 for limiting the reduction in thickness of the wafers 22. The polishing limiter 64 has planar upper and lower rubbing surfaces 66, 68. The upper rubbing surface 66 is adapted for being rubbed by the upper polishing surface 50, and the lower rubbing surface 68 is adapted for being rubbed by the lower polishing surface 52. Preferably, the thickness of the polishing limiter 64 (i.e., the axial distance between the upper and lower rubbing surfaces) is equal to the predetermined final thickness t 2 . Since the thickness of the polishing limiter 64 is less than the initial thickness t 1  of the wafers 22, not more than one of the upper and lower rubbing surfaces of the polishing limiter is rubbed by one of the polishing surfaces when the wafers are at their initial thickness. In other words, before the wafers have been polished to their predetermined final thickness, the upper rubbing surface 66 is axially spaced from the upper polishing surface 50 and/or the lower rubbing surface 68 is axially spaced from the lower polishing surface 52. The polishing limiter has a greater resistance to polishing than that of the semiconductor wafers 22 so that the polishing limiter prevents the polishing surfaces from further moving axially toward each other when the rubbing surfaces 66, 68 of the polishing limiter are simultaneously rubbed by the polishing surfaces. Thus, the polishing limiter 64 prevents the semiconductor wafers 22 from being reduced beyond the thickness t 2 . The polishing limiter is integrally formed with the wafer carrier such that the polishing limiter and carrier comprises a single unitary piece. Preferably, the wafer carrier/polishing limiter is stamped from a sheet of stainless steel and then coated with a suitable inert coating for preventing the stainless steel from contaminating the semiconductor wafers. 
     Although the circular plate 54 of the carrier 32 constitutes the polishing limiter in the preferred embodiment, it is to be understood that the polishing limiter may have other shapes or configurations. For example, the polishing limiter may comprise a plurality of fingers extending axially from the circular plate or a pair of raised annular beads extending axially from opposite faces of the circular plate. 
     To polish the semiconductor wafers 22, the wafers are placed in the openings of the carrier 32 which is placed axially between the upper and lower polishing surfaces 50, 52 of the polishing tables 28, 30. The initial thickness t 1  of the semiconductor wafers 22 is greater than the thickness t 2  of the polishing limiter 64 of the carrier 32 so that the wafers axially extend beyond the polishing limiter. The upper and lower polishing tables 28, 30 are axially moved toward each other so that the upper polishing surface 50 contacts the upper face 24 of the wafers 22 and the lower polishing surface 52 contacts the lower face 26 of the wafers. The upper and lower polishing surfaces then rotate relative to the wafers to polish the upper and lower faces 24, 26 of the wafers. As the wafers are polished the thickness of each decreases until the thickness is equal to the thickness t 2  of the polishing limiter 64. At that point, the upper rubbing surface 66 of the polishing limiter 64 is rubbed by the upper polishing surface and the lower rubbing surface 68 is rubbed by the lower polishing surface 52. Since the polishing limiter is resistant to polishing, it prevents the polishing tables from moving closer together than the distance t 2 . Thus, even if the polishing surfaces are rotated beyond the duration needed to polish the wafers to the final thickness t 2 , the wafers will not be over-polished. 
     Referring now to FIGS. 4 and 5, another embodiment of a semiconductor wafer polisher of the present invention is indicated in its entirety by the reference numeral 120. To simplify the description of this embodiment, corresponding parts are numbered the same as those parts shown in FIGS. 1-3 except the prefix &#34;1&#34; has been added to the reference numbers. 
     Like the polisher 20 of FIGS. 1-3, the polisher 120 is a double sided polisher adapted to polish both faces of each semiconductor wafer 122. The polisher 120 comprises upper and lower polishing tables 128, 130, respectively, and a wafer carrier 132. The polisher 120 is similar to the polisher 20 of FIGS. 1-3 except the wafer carrier 132 does not act as a polishing limiter. The wafer carrier 132 is thinner than the predetermined final thickness t 2  of the wafers 122. Instead dummy wafers 133 are used as polishing limiters to limit polishing of the semiconductor wafers 122. 
     The wafer carrier 132 holds both the semiconductor wafers 122 and the dummy wafers 133 between the upper and lower polishing surfaces 150, 152 of the upper and lower polishing tables 128, 130 during polishing. The wafer carrier 132 comprises a generally circular plate 154 with a plurality of openings 156 for receiving the semiconductor wafers 122 and the dummy wafers 133. Preferably, the semiconductor wafers 122 and dummy wafers 133 are arranged in a staggered configuration within the openings. The thickness of the dummy wafers is equal to the predetermined final thickness t 2  of the semiconductor wafers 122. The dummy wafers 133 have a greater resistance to polishing than that of the semiconductor wafers 122 and may be of sapphire, quartz, silicon-carbine, boron-nitrite coated silicon, or other suitable material. 
     To polish the semiconductor wafers 122, the semiconductor wafers and dummy wafers are placed in the openings of the carrier 132 and the carrier is placed axially between the upper and lower polishing surfaces 150, 152 of the polishing tables 128, 130. As shown in FIG. 4, the initial thickness t 1  of the semiconductor wafers 122 is greater than the thickness t 2  of the dummy wafers 133 so that the semiconductor wafers axially extend beyond the dummy wafers. The upper and lower polishing tables 128, 130 are axially moved toward each other so that the upper polishing surface 150 contacts the upper faces 124 of the semiconductor wafers and the lower polishing surface 152 contacts the lower faces 126 of the semiconductor wafers. The upper and lower polishing surfaces are then rotated relative to the wafers to polish the upper and lower faces 124, 126 of the semiconductor wafers. As the semiconductor wafers are polished, the thickness of each decreases until the thickness is equal to the thickness t 2  of the dummy wafers 133. At that point (shown in FIG. 5), the upper faces (upper rubbing surfaces) of the dummy wafers 133 are rubbed by the upper polishing surface 150 and the lower faces (lower rubbing surfaces) of the dummy wafers 133 are rubbed by the lower polishing surface 152. Since the dummy wafers are resistant to polishing, they prevent the polishing tables from moving closer together than the distance t 2 . Thus, even if the polishing surfaces are rotated beyond the duration needed to polish the semiconductor wafers to the final thickness t 2 , the semiconductor wafers will not be over-polished. 
     Referring now to FIGS. 6-8, another embodiment of a semiconductor wafer polisher of the present invention is indicated in its entirety by the reference numeral 220. To simplify the description of this embodiment, corresponding parts are numbered the same as those parts shown in FIGS. 1-3 except the prefix &#34;2&#34; has been added to the reference numbers. 
     The polisher 220 is a single sided polisher adapted to polish one face of each semiconductor wafer 222. The polisher 220 comprises a polishing table 228 and a wafer carrier 232. The polishing table 228 has a polishing plate 234 and a polishing pad 236 on the plate. The polishing pad 236 includes a planar polishing surface 250 adapted to abut and rub against the upper face 224 of each semiconductor wafer 222. The wafer carrier 232 comprises a support plate 270 having a plurality of circular recesses 272, each dimensioned for receiving a semiconductor wafer 222. Each recess 272 defines a generally planar wafer holding surface 274 for holding the lower face of the corresponding semiconductor wafer 222. The wafer holding surfaces 274 are coplanar and generally parallel to the polishing surface 250. The semiconductor wafers 222 are bonded with wax to the wafer holding surfaces 274. The wafer carrier is rotatable about a first axis X 1  and the polishing table 228 is rotatable about a second axis X 2  to effectuate relative rotation between the wafer carrier and the polishing table. The wafer carrier and polishing table are urged toward each other by conventional means to press the polishing surface 250 against the upper faces 224 of the semiconductor wafers 222 so that the polishing surface rubs against the upper faces upon relative rotation thereof to wear against the upper faces of the wafers. 
     The portion of the support plate 270 extending above the wafer holding surfaces 274 constitutes a polishing limiter 264 for limiting the reduction in thickness of the wafers 222. Preferably, the wafer carrier 232 is a single unitary member made of ceramic or other suitable material resistant to polishing. The polishing limiter 264 has a planar rubbing surface 266 adapted for being rubbed by the polishing surface 250. Preferably, the thickness of the polishing limiter 264 (i.e., the axial distance between the rubbing surface 266 and the wafer holding surfaces 274) is equal to the predetermined final thickness t 2 . Since the thickness of the polishing limiter 264 is less than the initial thickness t 1  of the wafers 222, the rubbing surface 266 is spaced from the polishing surface 250 until the wafers 222 are reduced to the final thickness t 2 . 
     To polish the semiconductor wafers 222, the lower faces 226 of the wafers are bonded to the wafer holding surfaces 274 and the wafers are placed below the polishing surface 250 of the polishing table 228. As shown in FIG. 7, the initial thickness t 1  of the semiconductor wafers 222 is greater than the thickness t 2  of the polishing limiter 264 of the support plate 270 so that the wafers axially extend upward beyond the polishing limiter. The polishing table 228 and wafer carrier 232 are axially moved toward each other so that the polishing surface 250 contacts the upper face 224 of the wafers. The polishing table 228 and wafer carrier 232 then counter-rotate about their respective axes so that the upper faces 224 of the wafers 222 are polished by the polishing surface 250. As the wafers are polished, the thickness of each decreases until the thickness is equal to the thickness t 2  of the polishing limiter 264, as shown in FIG. 8. At that point, the rubbing surface 266 of the polishing limiter 264 is rubbed by the polishing surface. Since the polishing limiter is resistant to polishing, it prevents the polishing table and carrier from moving closer together than the distance t 2 . Thus, even if the polishing surface is rotated beyond the duration needed to polish the wafers to the final thickness t 2 , the wafers will not be over-polished. 
     In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results attained. 
     As various changes could be made in the above constructions without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.