Patent Publication Number: US-2023163604-A1

Title: Series-parallel battery system

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims the priority of the patent application No. 202021046380.X, filed with State Intellectual Property Office of P.R.China on Jun. 9, 2020, the entirety of which is incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present disclosure relates to, but is not limited to, the technical field of batteries. 
     BACKGROUND 
     Terminals, such as mobile phones and the like, have become important living tools in the scenarios, such as communication interaction, digital entertainment and the like, and a large-capacity battery is a major measure to enhance the endurance of the terminals. The large-capacity battery and frequent usage of a terminal result in that quick charge has become an important aspect for improving user experience. Due to current limit of 5A (amperes) transmitted in a cable, and in order to enhance charging efficiency and to reduce losses of power transmission and power conversion, high-voltage charging has become a mainstream option. The transmission method for increasing a voltage and decreasing a current can effectively reduce the transmission loss of a line, but the high voltage does not match with the voltage of the battery and cannot be used to directly charge the battery. Even when a power supply of 5V (volts) is used for charging the battery, a power conversion chip is required to convert the voltage from the power supply of 5V into a voltage suitable for charging the battery. 
     SUMMARY 
     Embodiments of the present disclosure provide a series-parallel battery system including: a switch, a series-parallel battery and a charge and discharge management circuit. The series-parallel battery includes a battery combination management circuit and at least two batteries connected to each other. The battery combination management circuit is connected to the batteries. One battery in the series-parallel battery includes a second battery cell and a third protection circuit. Other batteries in the series-parallel battery include a first battery cell, a first protection circuit and a second protection circuit. The switch is connected to the batteries. The charge and discharge management circuit is connected to the battery combination management circuit and configured to control the states of the switch, of the first protection circuit and of the second protection circuit, so as to adjust a connection mode of the batteries in the series-parallel battery. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1   a    is a schematic diagram of a structure of a series-parallel battery in a series-parallel battery system provided in the present disclosure; 
         FIG.  1   b    is a schematic diagram of a structure of a series-parallel battery system including the series-parallel battery in  FIG.  1     a;    
         FIG.  1   c    is a schematic diagram of an exemplary circuit of the series-parallel battery in  FIG.  1     a;    
         FIG.  2   a    is a schematic diagram of a structure of a series-parallel battery in a series-parallel battery system provided in the present disclosure; 
         FIG.  2   b    is a schematic diagram of a structure of a series-parallel battery system including the series-parallel battery in  FIG.  2   a   ; and 
         FIG.  2   c    is a schematic diagram of an exemplary circuit of the series-parallel battery in  FIG.  2     a.    
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the exemplary embodiments may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure. 
     As used herein, the term “and/or” includes any or all combinations of one or more of the associated listed items. 
     The terms used herein are used only to describe particular embodiments and are not intended to limit the present disclosure. As used herein, the singular forms of “a” and “the” are also intended to include plural forms, unless the context clearly indicates otherwise. It is also to be understood that when the terms “include” and/or “constituted of . . . ” are used in this specification, it means that the features, wholes, steps, operations, components, and/or assemblies are present, but the presence or addition of one or more other features, wholes, steps, operations, components, assemblies, and/or groups thereof is not excluded. 
     The embodiments described herein may be described with reference to plane views and/or sectional views with the aid of ideal schematic diagrams of the present disclosure. Thus, example illustrations may be modified according to manufacturing techniques and/or tolerances. Thus, embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations based on manufacturing processes. Thus, the areas illustrated in the accompanying drawings have schematic properties and the shapes of the areas shown illustrates the specific shapes of the areas of the components, but are not intended for limiting. 
     Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those of ordinary skill in the art. It is also to be understood that terms such as those defined in frequently-used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present disclosure, and will not be construed as having idealized or over-formal meanings, unless expressly limited in such a manner herein. 
     Currently, a solution for adapting a high voltage to a battery voltage is to connect batteries in series. The power loss due to power conversion may be reduced by adapting the batteries in series to an input of a high voltage, which still has the following defects (1) to (3). (1) Supply of power from a single battery is merely supported in a circuit system, and thus a power supply chip is required to convert the batteries in series into a corresponding power supply for outputting, which also results in a certain loss. (2) As for conventional charging of 5V to the batteries in series, an additional boost circuit is required to adapt to charging the batteries in series, which has a low boost conversion efficiency. (3) Fixed batteries in series result to discharge loss while reducing charge loss, and with the popularity of 5G, the overall power of a system increases and the endurance may also be significantly reduced due to the discharge loss. 
     Thus, the present disclosure particularly provides a series-parallel battery system, which substantially avoids one or more of the problems due to the disadvantages and limitations in the related art. 
     The present disclosure provides a series-parallel battery system. As shown in  FIG.  1   a   ,  FIG.  1   b   ,  FIG.  2   a    and  FIG.  2   b   , the series-parallel battery system includes a switch  1 , a series-parallel battery  2  and a charge and discharge management circuit  3 . The series-parallel battery  2  includes a battery combination management circuit  23  and at least two batteries connected to each other. The battery combination management circuit  23  is connected to the batteries. One battery in the series-parallel battery includes a second battery cell  22  and a third protection circuit  26 . Other batteries in the series-parallel battery  2  include a first battery cell  21 , a first protection circuit  24  and a second protection circuit  25 . The switch  1  is connected to the batteries. The charge and discharge management circuit  3  is connected to the battery combination management circuit  23  and configured to control the states of the switch  1 , of the first protection circuit  24  and of the second protection circuit  25 , so as to adjust the connection mode of the batteries in the series-parallel battery. 
     The states of the switch  1 , of the first protection circuit  24  and of the second protection circuit  25  include an on state and an off state. The combination of the different states of the switch  1 , of the first protection circuit  24  and of the second protection circuit  25  may form the connection modes, i.e., series connection or parallel connection of the batteries in the series-parallel battery  2 . It should be noted that in an implementation of the present disclosure, the third protection circuit  26  is always in an on state. 
     In one battery, a battery cell is used for electric quantity storage, and a protection circuit is used to detect a voltage and a current across two ends of the battery cell, so as to prevent the battery cell from overcharge and over-discharge. The first protection circuit  24  or the second protection circuit  25  cooperates with the first battery cell  21  to implement the charge or discharge of one battery. The second battery cell  22  cooperates with the third protection circuit  26  to implement the charge and discharge of another battery. The battery combination management circuit  23  controls the switch  1  and the protection circuits of the batteries to be on or off according to an adjusting instruction from the charge and discharge management circuit  3 , so as to achieve combination of the series or parallel connection of the batteries. Or, the charge and discharge management circuit  3  controls the switch  1  to be on or off to achieve the combination of the series or parallel connection of the batteries. 
     The series-parallel battery system in the present disclosure includes a switch  1 , a series-parallel battery  2  and a charge and discharge management circuit  3 . The series-parallel battery  2  includes a battery combination management circuit  23  and at least two batteries connected to each other. The battery combination management circuit  23  is connected to the batteries. One battery in the series-parallel battery includes a second battery cell  22  and a third protection circuit  26 . Other batteries in the series-parallel battery  2  include a first battery cell  21 , a first protection circuit  24  and a second protection circuit  25 . The switch  1  is connected to the batteries. The charge and discharge management circuit  3  is connected to the battery combination management circuit  23  and configured to control the states of the switch  1 , of the first protection circuit  24  and of the second protection circuit  25 , so as to adjust the connection mode of the batteries. In the implementation of the present disclosure, the battery cells of the batteries in the series-parallel battery may be connected in a series or parallel connection mode, and the connection mode may be freely switched. Compared with an existing single battery power supply system, a voltage of the batteries in series may be converted into a voltage of a single battery, without a power supply chip, thereby effectively improving the discharge efficiency. Compared with existing charging to fixed batteries in series, a power supply of 5V may adapt to charging to the batteries in series, without an additional boost circuit, thereby effectively enhancing the charge efficiency. 
     In some implementations, the charge and discharge management circuit  3  may be arranged on a main board. 
     An existing solution of series charging and parallel discharging is to arrange a combination of four switches between two batteries in series to meet different charge and discharge demands. However, the solution has the following defects (1) and (2). (1) In both a charging series and a discharging stage, two switches in the circuit will work, which will increase the impedance loss of the switches. For example, as for charging of 65 W (watts), when a current entering the batteries is greater than 5 A, a switch impedance loss of 10 milliohms will also result in a switch conduction loss of greater than 0.25 W. (2) Multiple electronic switches are used to implement the circuit, and may occupy a large area of the circuit, especially a circuit in a mobile terminal, resulting in difficulty of implementation of the circuit. 
     In order to solve the above problems, in the series-parallel battery system in the present disclosure, one switch  1  is used to achieve switching between the series connection and the parallel connection of the batteries in the series-parallel battery  2 . 
     In some implementations, as shown in  FIG.  1   a    and  FIG.  1   b   , the switch  1  is arranged in the series-parallel battery  2 , and the battery combination management circuit  23  is connected to the switch  1  and configured to control the state of the switch  1  according to the instruction from the charge and discharge management circuit  3 . That is, the charge and discharge management circuit  3  determines the connection mode of the batteries and sends the adjusting instruction to the battery combination management circuit  23 , and the battery combination management circuit  23  controls the state of the switch  1  according to the adjusting instruction. 
     In some implementations, as shown in  FIG.  2   b   , the switch  1  is arranged on the main board, and the charge and discharge management circuit  3  is connected to the switch  1 . That is, the charge and discharge management circuit  3  directly controls the switch  1 , without through the battery combination management circuit  23 . 
     In the implementation of the present disclosure, the number of the switch  1  is reduced. Only one switch  1  is used to achieve switch between the battery connection mode in a charging state and the battery connection mode in a discharging state, such that the impedance loss on a charge and discharge loop is reduced, the charge and discharge efficiency is further enhanced, the circuit layout can also be optimized, the terminal equipment is advantageously lighter and thinner, and the cost is reduced. 
     As shown in  FIG.  1   a    and  FIG.  1   b   , a first terminal of the first battery cell  21  is connected to a first positive terminal of the series-parallel battery  2 , a third terminal of the first protection circuit  24 , a third terminal of the second protection circuit  25  and a third terminal of the battery combination management circuit  23 . A second terminal of the first battery cell  21  is connected to a first terminal of the first protection circuit  24  and a first terminal of the second protection circuit  25 . 
     A first terminal of the second battery cell  22  is connected to a second terminal of the first protection circuit  24 , a third terminal of the third protection circuit  26 , a second positive terminal of the series-parallel battery  2  and a seventh terminal of the battery combination management circuit  23 . A second terminal of the second battery cell  22  is connected to a first terminal of the third protection circuit  26 . A first terminal of the battery combination management circuit  23  is connected to a fourth terminal of the first protection circuit  24 . A second terminal of the battery combination management circuit  23  is connected to a fourth terminal of the second protection circuit  25 . A sixth terminal of the battery combination management circuit  23  is connected to a communication terminal of the series-parallel battery  2 . A second terminal of the third protection circuit  26  is connected to a second terminal of the second protection circuit  2  and a negative terminal of the series-parallel battery  2 . 
     In some implementations, as shown in  FIG.  1   a   , the switch  1  is arranged in the series-parallel battery  2 . A first terminal of the switch  1  is connected to the first positive terminal of the series-parallel battery  2 . A second terminal of the switch  1  is connected to the second positive terminal of the series-parallel battery  2 . A third terminal of the switch  1  is connected to a fourth terminal of the battery combination management circuit  23 . The charge and discharge management circuit  3  is connected to the sixth terminal of the battery combination management circuit  23  through the communication terminal of the series-parallel battery  2 . 
     In some implementations, as shown in  FIG.  2   a    and  FIG.  2   b   , the switch  1  is arranged on the main board. A first terminal of the switch  1  is connected to the first positive terminal of the series-parallel battery  2 . A second terminal of the switch  1  is connected to the second positive terminal of the series-parallel battery  2 . A third terminal of the switch  1  is connected to a first terminal of the charge and discharge management circuit  3 . A second terminal of the charge and discharge management circuit  3  is connected to the sixth terminal of the battery combination management circuit  23  through the communication terminal of the series-parallel battery  2 . 
     Compared with the solution shown in  FIG.  1   a    to  FIG.  1   c   , in the solution shown in  FIG.  2   a    to  FIG.  2   c   , internal circuits of the series-parallel battery  2  can be simplified by moving the switch  1  from the inside of the series-parallel battery  2  to the main board and by controlling the switch  1  to be on and off by means of the charge and discharge management circuit  3 . 
     In some implementations, as shown in  FIG.  1   a   ,  FIG.  1   c   ,  FIG.  2   a    and  FIG.  2   c   , the battery combination management circuit  23  includes a micro-processing circuit (e.g., a micro-processing chip, a microprocessor or a microcontroller), a second transistor Q 2 , a sixth transistor Q 6  and an eighth transistor Q 8 . A second electrode of the second transistor Q 2  is the fourth terminal of the battery combination management circuit  23 . A control electrode of the second transistor Q 2  is connected to the micro-processing circuit. A second electrode of the sixth transistor Q 6  is the first terminal of the battery combination management circuit  23 . A control electrode of the sixth transistor Q 6  is connected to the micro-processing circuit. A second electrode of the eighth transistor Q 8  is the second terminal of the battery combination management circuit  23 . A control electrode of the eighth transistor Q 8  is connected to the micro-processing circuit. A first electrode of the second transistor Q 2 , a first electrode of the sixth transistor Q 6  and a first electrode of the eighth transistor Q 8  are respectively connected to the positive terminal of the series-parallel battery  2 . The third terminal, the sixth terminal and the seventh terminal of the battery combination management circuit  23  are ports of the micro-processing circuit. 
     In some implementations, as shown in  FIG.  1   c    and  FIG.  2   c   , the switch  1  includes a first transistor Q 1  a first resistor R 1  and a second resistor R 2 . A control electrode of the first transistor Q 1  is connected to a second terminal of the first resistor R 1  and a first terminal of the second resistor R 2 . A first electrode of the first transistor Q 1  is the first terminal of the switch  1  and is connected to a first terminal of the first resistor R 1  A second electrode of the first transistor Q 1  is the second terminal of the switch  1 . A second terminal of the second resistor R 2  is the third terminal of the switch  1 . 
     The first transistor Q 1  implements an on-off action. The micro-processing circuit turns the first transistor Q 1  on or off by controlling the second transistor Q 2 . When the second transistor Q 2  is turned on, resistor voltage division is achieved by the first resistor R 1  and the second resistor R 2 , such that the first transistor Q 1  is also turned on. At this time, the switch  1  is turned on, and the first positive terminal is connected to the second positive terminal, thereby realizing parallel connection of the first battery cell  21  to the second battery cell  22 . When the second transistor Q 2  is turned off, the first transistor Q 1  is also turned off. At this time, the switch  1  is turned off, and the first positive terminal is disconnected to the second positive terminal, thereby realizing series connection of the first battery cell  21  to the second battery cell  22 . 
     In the solution of  FIG.  1   a    to  FIG.  1   c   , the micro-processing circuit communicates with the charge and discharge management circuit  3  through the communication terminal, so as to determine and control the first battery cell  21  and the second battery cell  22  being in a series or parallel connection state. In the whole battery charging and discharging process, voltage sampling is performed at point A and point B by the micro-processing circuit, so as to determine voltages of the first battery cell  21  and of the second battery cell  22 . In the solution of  FIG.  2   a    to  FIG.  2   b   , the charge and discharge management circuit  3  directly controls the second transistor Q 2  to be on or off by controlling the level of the control electrode of the second transistor Q 2 . 
     In some implementations, as shown in  FIG.  1   c    and  FIG.  2   c   , the first protection circuit  24  includes a first protection chip, a third transistor Q 3 , a fourth transistor Q 4 , a fifth transistor Q 5 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a first capacitor C 1  and a second capacitor C 2 . A first terminal of the second capacitor C 2  is the first terminal of the first protection circuit  24  and is connected to the first protection chip. A second electrode of the third transistor Q 3  is the second terminal of the first protection circuit and is connected to a second terminal of the first capacitor C 1 . A second terminal of the fourth resistor R 4  is the third terminal of the first protection circuit and is connected to a first terminal of the first capacitor C 1 . A control electrode of the fifth transistor Q 5  is connected to a second terminal of the fifth resistor R 5  and a first terminal of the sixth resistor R 6 . A second terminal of the sixth resistor R 6  is the fourth terminal of the first protection circuit  24 . A first electrode of the fifth transistor Q 5  is connected to a first terminal of the fifth resistor R 5  and a first terminal of the fourth resistor R 4 . A second electrode of the fifth transistor Q 5  is connected to the first protection chip and a second terminal of the second capacitor C 2 . A control electrode of the third transistor Q 3  and a control electrode of the fourth transistor Q 4  are respectively connected to the first protection chip. A first electrode of the third transistor Q 3  is connected to a second electrode of the fourth transistor Q 4 . A first electrode of the fourth transistor Q 4  is connected to the first terminal of the second capacitor C 2 . The third transistor Q 3 , the fourth transistor Q 4  and the first protection chip are implemented to prevent the first battery cell  21  under a series architecture from overcurrent of a discharge current and overvoltage of a charge voltage. 
     The sixth transistor Q 6  is used for controlling whether the first protection chip is enabled or not (i.e., whether the first protection circuit  24  is enabled or not). The fifth transistor Q 5  is turned on by the level of the control electrode of the sixth transistor Q 6  controlled by the micro-processing circuit, such that the first protection chip is controlled to be in a working state and thus the first battery cell  21  is connected in series to the second battery cell  22 . The fifth resistor R 5  and the sixth resistor R 6  are used for cooperating with the turn-on or turn-off state of the fifth transistor Q 5  and the sixth transistor Q 6 , and the fourth resistor R 4  and the second capacitor C 2  are used for cooperating with the working of the first protection chip and voltage sampling of the first battery cell  21 , so as to cooperatively realize overvoltage protection. 
     The first protection chip is used to control the turn-on and turn-off of the third transistor Q 3  and the fourth transistor Q 4 . The micro-processing circuit is used to control the turn-on and turn-off of the sixth transistor Q 6 . The first electrode of the fifth transistor Q 5  is connected to the first terminal of the first battery cell  21  (i.e., the positive terminal of the battery cell) and the first positive terminal of the series-parallel battery  2  through the fourth resistor R 4 . The second electrode of the fifth transistor Q 5  is connected to power supply pins of the first protection chip to supply power to the first protection chip, while the first protection chip monitors the voltage of the first battery cell  21 . When the sixth transistor is turned on, resistor voltage division is implemented by the fifth resistor R 5  and the sixth resistor R 6 , such that the fifth transistor Q 5  is turned on. After the fifth transistor Q 5  is turned on, the first protection chip controls the on state and off state of the third transistor Q 3  and the fourth transistor Q 4  according to the state of the first battery cell  21 . During charging, if a charge voltage or current exceeds a charging curve range of the first battery cell, the first protection chip controls the third transistor Q 3  to be off. During discharging, if a discharge voltage or current exceeds a discharging curve range of the first battery cell, the first protection chip controls the fourth transistor Q 4  to be off. If charging and discharging are normal and within the curve range, the first protection chip controls the third transistor Q 3  and the fourth transistor Q 4  to be on, and the second terminal of the first battery cell  21  (i.e., the negative terminal of the battery cell) is connected to the first terminal of the second battery cell  22 , thereby realizing series connection of the first battery cell  21  to the second battery cell  22 . When the sixth transistor Q 6  is turned off, the fifth transistor Q 5  is also turned off. The first protection chip is not supplied with power and then stops working, while the third transistor Q 3  and the fourth transistor Q 4  cannot be provided with a level for driving and then are in an off state, and thus the second terminal of the first battery cell  21  is disconnected to the first terminal of the second battery cell  22 . When the first protection chip is in a working state, the first transistor Q 1  is in an off state, that is, the micro-processing circuit controls the second transistor Q 2  to be in an off state. 
     In some implementations, as shown in  FIG.  1   c    and  FIG.  2   c   , the second protection circuit  25  includes a second protection chip, a seventh transistor Q 7 , a ninth transistor Q 9 , a tenth transistor Q 10 , an eighth resistor R 8 , a ninth resistor R 9 , a tenth resistor R 10 , a third capacitor C 3  and a fourth capacitor C 4 . A first terminal of the fourth capacitor C 4  is the first terminal of the second protection circuit  25  and is connected to the second protection chip. A second electrode of the ninth transistor Q 9  is the second terminal of the second protection circuit and is connected to a second terminal of the third capacitor C 3 . A second terminal of the eighth resistor R 8  is the third terminal of the second protection circuit  25  and is connected to a first terminal of the third capacitor C 3 . A control electrode of the seventh transistor Q 7  is connected to a second terminal of the ninth resistor R 9  and a first terminal of the tenth resistor R 10 . A second terminal of the tenth resistor R 10  is the fourth terminal of the second protection circuit  25 . A first electrode of the seventh transistor Q 7  is connected to a first terminal of the ninth resistor R 9  and a first terminal of the eighth resistor R 8 . A second electrode of the seventh transistor Q 7  is connected to the second protection chip and a second terminal of the fourth capacitor C 4 . A control electrode of the ninth transistor Q 9  and a control electrode of the tenth transistor Q 10  are respectively connected to the second protection chip. A first electrode of the ninth transistor Q 9  is connected to a second electrode of the tenth transistor Q 10 . A first electrode of the tenth transistor Q 10  is connected to a first terminal of the fourth capacitor C 4 . The ninth transistor Q 9 , the tenth transistor Q 10  and the second protection chip are implemented to prevent the first battery cell  21  under a parallel architecture from overcurrent of a discharge current and overvoltage of a charge voltage. 
     The eighth transistor Q 8  is used for controlling whether the second protection chip is enabled or not (i.e., whether the second protection circuit  25  is enabled or not). The seventh transistor Q 7  is turned on by the level of the control electrode of the eighth transistor Q 8  controlled by the micro-processing circuit, such that the second protection chip is controlled to be in a working state, and thus the first battery cell  21  is connected in parallel to the second battery cell  22 . The ninth resistor R 9  and the tenth resistor R 10  are used for cooperating with the turn-on or turn-off state of the seventh transistor Q 7  and the eighth transistor Q 8 , and the eighth resistor R 8  and the fourth capacitor C 4  are used for cooperating with the working of the second protection chip and voltage sampling of the first battery cell  21 , so as to cooperatively realize overvoltage protection. It should be noted that the first protection chip and the second protection chip cannot be enabled at the same time. 
     The second protection circuit  25  has the same working process as the first protection circuit  24 , which will not be described in detail herein. 
     In some implementations, as shown in  FIG.  1   c    and  FIG.  2   c   , the third protection circuit  26  includes a third protection chip, an eleventh transistor Q 11 , a twelfth transistor Q 12 , a fourteenth resistor R 14 , a fifth capacitor C 5  and a sixth capacitor C 6 . A first terminal of the sixth capacitor C 6  is the first terminal of the third protection circuit  26  and is connected to the third protection chip. A second electrode of the eleventh transistor Q 11  is the second terminal of the third protection circuit  26  and is connected to a second terminal of the fifth capacitor C 5 . A first terminal of the fourteenth resistor R 14  is the third terminal of the third protection circuit  26  and is connected to a first terminal of the fifth capacitor C 5 . A second terminal of the fourteenth resistor R 14  is connected to the third protection chip and a second terminal of the sixth capacitor C 6 . A control electrode of the eleventh transistor Q 11  and a control electrode of the twelfth transistor Q 12  are respectively connected to the third protection chip. A first electrode of the eleventh transistor Q 11  is connected to a second electrode of the twelfth transistor Q 12 . A first electrode of the twelfth transistor Q 12  is connected to a first terminal of the sixth capacitor C 6 . The eleventh transistor Q 11 , the twelfth transistor Q 12  and the third protection chip are implemented to prevent the second battery cell  22  from overcurrent of a discharge current and overvoltage of a charge voltage. 
     The third protection chip is used to control the eleventh transistor Q 11  and the twelfth transistor Q 12  to be on and off. The first terminal of the second battery cell  22  is connected to power supply pins of the third protection chip through the fourteenth resistor R 14  to supply power to the third protection chip, while the third protection chip is used to monitor the voltage of the second battery cell  22 . The third protection chip controls the eleventh transistor Q 11  and the twelfth transistor Q 12  to be on and off according to the state of the second battery cell  22 . During charging, if a charge voltage or current exceeds a charging curve range of the second battery cell  22 , the third protection chip controls the eleventh transistor Q 11  to be off. During discharging, if a discharge voltage or current exceeds a discharging curve range of the second battery cell, the third protection chip controls the twelfth transistor Q 12  to be off. If charging and discharging are normal and within the curve range, the third protection chip controls the eleventh transistor Q 11  and the twelfth transistor Q 12  to be on and connects the second terminal of the second battery cell  22  to the negative terminal of the series-parallel battery  2 . 
     In some implementations, as shown in  FIG.  1   c    and  FIG.  2   c   , the first protection circuit  24  may further include a first current sampling resistor R 7 . A first terminal of the first current sampling resistor R 7  is connected to the first terminal of the fourth transistor Q 4  and the first protection chip. A second terminal of the first current sampling resistor R 7  is connected to the first terminal of the second capacitor C 2  and the first protection chip. And/or, the second protection circuit  25  may further include a second current sampling resistor R 12 . A first terminal of the second current sampling resistor R 12  is connected to the first electrode of the tenth transistor Q 10  and the second protection chip. A second terminal of the second current sampling resistor R 12  is connected to the first terminal of the fourth capacitor C 4  and the second protection chip. And/or, the third protection circuit  26  may further include a third current sampling resistor R 15 . A first terminal of the third current sampling resistor R 15  is connected to the first electrode of the twelfth transistor Q 12  and the third protection chip. A second terminal of the third current sampling resistor R 15  is connected to the first terminal of the sixth capacitor C 6  and the third protection chip. 
     A current that passes through the first current sampling resistor R 7  may be obtained by the first protection chip according to I=U/R by detecting voltages across the two ends of the first current sampling resistor R 7 . A current that passes through the second current sampling resistor R 12  may be obtained by the second protection chip according to I=U/R by detecting voltages across the two ends of the second current sampling resistor R 12 . A current that passes through the third current sampling resistor R 15  may be obtained by the third protection chip according to I=U/R by detecting voltages across the two ends of the second current sampling resistor R 15 . It should be noted that the currents may be measured by other methods, and in this case, the current sampling resistors may be omitted. 
     In some implementations, as shown in  FIG.  1   c    and  FIG.  2   c   , the first protection circuit  24  may further include a first voltage sampling resistor R 3 . A first terminal of the first voltage sampling resistor R 3  is connected to the first protection chip. A second terminal of the first voltage sampling resistor R 3  is connected to the second electrode of the third transistor Q 3 . And/or, the second protection circuit  25  may further include a second voltage sampling resistor R 11 . A first terminal of the second voltage sampling resistor R 11  is connected to the second protection chip. A second terminal of the second voltage sampling resistor R 11  is connected to the second electrode of the ninth transistor Q 9 . And/or, the third protection circuit  26  may further include a third voltage sampling resistor R 13 . A first terminal of the third voltage sampling resistor R 13  is connected to the third protection chip. A second terminal of the third voltage sampling resistor R 13  is connected to the second electrode of the eleventh transistor Q 11 . 
     The first protection chip performs voltage sampling on the voltage at the negative terminal of the first battery cell  21  through the first voltage sampling resistor R 3 . The second protection chip performs voltage sampling on the voltage at the negative terminal of the first battery cell  21  through the second voltage sampling resistor R 11 . The third protection chip performs voltage sampling on the voltage at the negative terminal of the second battery cell  22  through the third voltage sampling resistor R 13 . 
     In some implementations, as shown in  FIG.  1   c    and  FIG.  2   c   , the first protection circuit  24  may further include a first thermistor F 1 . A second terminal of the first thermistor F 1  is connected to the first terminal of the second capacitor C 2 . A first terminal of the first thermistor F 1  is the first terminal of the first protection circuit  24 . And/or, the second protection circuit  25  may further include a second thermistor F 2 . A second terminal of the second thermistor F 2  is connected to the first terminal of the fourth capacitor C 4 . A first terminal of the second thermistor F 2  is the first terminal of the second protection circuit  25 . And/or, the third protection circuit  26  may further include a third thermistor F 3 . A second terminal of the third thermistor F 3  is connected to the first terminal of the sixth capacitor C 6 . A first terminal of the third thermistor F 3  is the first terminal of the third protection circuit  26 . 
     When the temperature of the battery cell exceeds a certain range, the thermistor has a high resistance value which increases the internal resistance of the battery, such that the circuit in a system is unable to obtain a corresponding voltage and a corresponding current, and is unable to work normally. It should be noted that if there are other temperature monitoring and response controls, the first thermistor F 1 , the second thermistor F 2  and the third thermistor F 3  may be replaced. 
     It should be noted that, in the implementation of the present disclosure, as an example, the first transistor Q 1 , the fifth transistor Q 5  and the seventh transistor Q 7  are PMOS transistors, and the second transistor Q 2 , the third transistor Q 3 , the fourth transistor Q 4 , the sixth transistor Q 6 , and the eighth transistor Q 8  to the twelfth transistor Q 12  are NMOS transistors. 
     The solution shown in  FIG.  2   a    to  FIG.  2   c    differs from the solution shown in  FIG.  1   a    to  FIG.  1   c    in that the switch  1  is arranged on the main board, and the charge and discharge management circuit  3  controls the first transistor Q 1  to be on or off, that is, the first transistor Q 1  is controlled to be on or off by the level of the control electrode of the second transistor Q 2  controlled by the charge and discharge management circuit  3 . The solution shown in  FIG.  2   a    to  FIG.  2   c    is the same as the solution shown in  FIG.  1   a    to  FIG.  1   c    in terms of the structure of the series-parallel battery  2  and the connection relation of the devices. 
     Exemplary implementations have been disclosed herein, and although specific terms are adopted, they are used and should be construed only as a general illustrative meaning and not for purpose of limitation. In some instances, it is apparent to those skilled in the art that features, characteristics and/or elements described in combination with a specific implementation can be used alone, or can be used in combination with features, characteristics and/or elements described in combination with other implementations, unless otherwise stated expressly. Accordingly, it will be understood by those skilled in the art that various changes in form and detail can be made without departing from the scope of the present disclosure as set forth in the appended claims.