Patent Publication Number: US-11394172-B2

Title: Laser driver with high-speed and high-current and integrated circuit thereof

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of optoelectronic integrated circuit (OEIC), in particular to a laser driver integrated circuit that simultaneously supports high-speed and high-current operation, and more particularly to a an integrated circuit. 
     BACKGROUND OF THE INVENTION 
     With the rapid development of communication networks, there is a high demand for optical fiber communication networks with high bandwidth and low loss. A laser driver is one of the key components in an optical communication system as it controls the quality of the transmitted optical signal. The driver circuit bandwidth and modulation current have significant impacts on the quality of the output optical signal. In order to work at high-speeds without inter-symbol interference (ISI), the laser driver must have sufficient bandwidth. In long-haul communication, the driver circuit must deliver high modulation current to the laser diode for a large extinction ratio. Due to the mismatch between the laser&#39;s input impedance and the (printed circuit board) PCB&#39;s transmission line impedance, a termination network (such as passive on-chip passive resistors) is usually required to absorb signal reflections from the laser side. If the terminal resistors and the input resistance of the laser are perfectly matched with the characteristic impedance of the transmission line, the reflected signal can be completely absorbed. But half of the output current will be wasted through the terminal resistors, resulting in a large power waste. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a high-speed high current laser driver integrated circuit to solve the problem of large power consumption waste caused by using passive terminal resistors. This design does not use any passive back termination resistor, so the power consumption of the circuit is much lower compared to the traditional circuit. Another object of the present invention provides an integrated circuit encapsulated by the laser driver with high-speed and high-current to avoid the large consumption waste. 
     The present invention provides a laser driver with high-speed and high-current, includes: 
     an input stage circuit; 
     a pre-drive circuit, being electrically connected to the out put ends of the input stage circuit; 
     a fully differential negative capacitance circuit, being electrically connected to the output ends of the pre-drive circuit; 
     a output stage circuit being electrically connected to the out put ends of the pre-drive circuit; and 
     an active reverse termination circuit; the input ends of the active reverse termination circuit being electrically connected to the input ends of the output stage circuit, and the output ends of the active reverse termination circuit being electrically connected to the output ends of the output stage circuit. 
     In the laser driver of the present invention, the active reverse termination circuit includes: 
     a pair of transistors M 5A , M 5B ; the gate of the transistor M 5A  is electrically connected to the positive output end of the pre-drive circuit, the gate of the transistor M 5B  is electrically connected to the negative output end of the pre-drive circuit; the sources of the transistors M 5A , M 5B  are electrically connected to a tail current source I M1 /k; 
     a pair of transistors M 6A , M 6B ; the gate of the transistor M 6A  is electrically connected to the positive output end of the pre-drive circuit, the gate of the transistor M 6B  is electrically connected to the negative output end of the pre-drive circuit; the sources of the transistors M 6A , M 6B  are electrically connected to a tail current source I M2 /k; 
     a pair of transistors M 7A , M 7B ; the gate of the transistor M 7A  is electrically connected to the positive output end of the pre-drive circuit, the gate of the transistor M 7B  is electrically connected to the negative output end of the pre-drive circuit; the sources of the transistors M 7A , M 7B  are electrically connected to a tail current source I M3 /k; 
     a pair of transistors M S1 , M S2 ; the drains of the transistors M 5A , M 6A , M 7A  are electrically connected to the gate of the transistor M S2 , the drains of the transistors M 5B , M 6B , M 7B  are electrically connected to the gate of the transistor M S1 ; the source of the transistor M S1  is electrically connected to a tail current source I B1 , the source of the transistor M S2  is electrically connected to a tail current source I B2 ; 
     a pair of resistors R 3A , R 3B ; one end of these resistors is connected with the drains of the transistors M S1 , M S2  to a supply voltage V DD ; the other ends of the resistors R 3A  and R 3b  are connected to the gates of the M S2  and M S1 , respectively; and 
     a pair of capacitors C 1 , C 2 ; one end of the capacitor C 1  is electrically connected to the source of the transistor M S2 , the other end of capacitor C 1  is directly connected to a output current terminal I OP ; one end of the capacitor C 2  is electrically connected to the source of the transistor M S1 , the other end of capacitor C 2  is directly connected to a output terminal I ON . 
     In the laser driver of the present invention, the input stage circuit includes: 
     a transistor M D ; the gate and drain of the transistor M D  are electrically connected to the voltage source V DD ; 
     a pair of transistors M 1A , M 1B ; the gates of the transistors M 1A , M 1B  respectively are used as the input ends of the input stage circuit, the drains of transistors M 1A , M 1B  are electrically connected to input ends of the pre-drive circuit, the sources of the M 1A  and M 1B  are connected to a tail current source I 1 ; and 
     a plurality of resistors R INA , R INB , R 1A , and R 1B ; one end of the resistor R INA  is electrically connected to a voltage source V CM , the other end of the resistor R INA  is electrically connected to the gate of the transistor M 1A ; one end of the resistor R INB  is electrically connected to the voltage source V CM , the other end of the resistor R INB  is electrically connected to the gate of the transistor M 1B ; one end of the resistor R 1A  is electrically connected to the drain of the transistors M 1A , the other end of the resistor R 1A  is electrically connected to the source of the transistor M D ; one end of the resistor R 1B  is electrically connected to the drain of the transistors M 1B , the other end of the resistor R 1B  is electrically connected to the source of the transistor M D . 
     In the laser driver of the present invention, both resistors R INA  and R INB  are 50 ohms. 
     In the laser driver of the present invention, the pre-drive circuit includes: 
     a pair of transistors M 2A , M 2B ; the gates of the transistors M 2A , M 2B  are electrically connected to the drains of transistors M 1A , M 1B  respectively, the drains of the transistors M 2A , M 2B  are electrically connected to input ends of the output stage circuit, the sources of the transistors M 2A , M 2B  are connected to a tail current source I 2 ; and 
     a pair of resistors R 2A , R 2B ; one end of the resistors R 2A  is connected to the drain of the transistors M 2A , one end of the resistors R 2B  is connected to the drain of the transistors M 2B , the other ends of the resistors R 2A , R 2B  are connected to the voltage source V DD . 
     In the laser driver of the present invention, the negative capacitance circuit includes: 
     a pair of transistors M 3A , M 3B ; the gate of the transistors M 3A  and the drain of the transistors M 3B  are electrically connected together to the positive output end of the pre-drive circuit, the gate of the transistors M 3B  and the drain of the transistors M 3A  are electrically connected together to the negative output end of the pre-drive circuit, the sources of the transistors M 3A , M 3B  are connected to a pair of tail current sources I 3A , I 3B  respectively; and 
     a capacitor C c ; two ends of the capacitor C c  are connected to the tail current sources I 3A , I 3B . 
     In the laser driver of the present invention, the output stage circuit includes: 
     a pair of transistors M 4A , M 4B ; the sources of the transistors M 4A , M 4B  are electrically connected together to a tail current source I M1 , the drains of the transistors M 4A , M 4B  represent the output ends of output current terminals I OP , I ON ; the gate of the transistor M 4A  is electrically connected to the positive output end of the pre-drive circuit, and the gate of the transistor M 4B  is electrically connected to the negative output end of the pre-drive circuit; and 
     a pair of transistors M CA , M CB ; the source and drain of the transistor M CA  are connected together to the output end of the output current terminal I ON , and the source and drain of the transistor M CB  are connected together to the output end of the output current terminal I OP ; the gate of the transistor M CA  is electrically connected to the positive output end of the pre-drive circuit, and the gate of the transistor M CB  is electrically connected to the negative output end of the pre-drive circuit. 
     In the laser driver of the present invention, the output stage circuit is a three parallel connected output stages circuit. 
     In the laser driver of the present invention, the first output stage is directly connected to the output of the pre-drive circuit while the second and the third output stages are connected to the output of pre-drive using switching circuits. 
     In the laser driver of the present invention, each switching circuit includes: 
     a pair of transistors M S3 , M S4 ; the gates of the transistors M S3 , M S4  receive a switch control signal V s , the sources of the transistors M S3 , M S4  respectively electrically are connected to the inputs of the second output stage via two input ends of the corresponding switching circuit, the drains of the transistors M S3 , M S4  are electrically connected to the output ends of the pre-drive circuit respectively. 
     In the laser driver of the present invention, one of the witching circuits is controlled by a switch control signal V s1 , and the other of the switching circuits is controlled by a switch control signal V s2 . 
     In the laser driver of the present invention, when the switch control signals V s1 , V s2  are 0, the output modulation current can be adjusted from 10 mA to 50 mA; when the switch control signal V s1  is 1 and the switch control signal V s2  is 0, the output modulation current can reach 100 mA; when the switch control signals V s1 , V s2  are 1, the output modulation current is as high as 150 mA. 
     The present invention provides a laser driver with high-speed and high-current, includes: 
     an input stage circuit which receives a pair of fully differential input voltage signals, V IP , V IN , then, adjusting the common-mode output voltage of signals V 1IP , V 1IN , such that they could be applied to the subsequent stage; 
     a pre-drive circuit, for amplifying the voltage signals V 1IP , V 1IN  to a pair of voltage signals V + , V − ; 
     a fully differential negative capacitance circuit that is directly connected to the output terminals of the pre-drive circuit, V + , V − ; the negative capacitance circuit generates a negative capacitor to reduce the input capacitance of the output stage circuit; 
     an output stage circuit, for receiving the voltage signals V + , V − , then outputting a pair of modulated current signals I OP , I ON ; and 
     an active reverse termination circuit, for absorbing the reflected wave caused by the output mismatch of the output stage circuit. 
     In the laser driver of the present invention, the active reverse termination circuit includes: 
     a pair of transistors M 5A , M 5B ; the gate of the transistor M 5A  receives the voltage signal V + , the gate of the transistors M 5B  receives the voltage signal V − ; the sources of the transistors M 5A , M 5B  are electrically connected to a tail current source I M1 /k; 
     a pair of transistors M 6A , M 6B ; the gate of the transistor M 6A  receives the voltage signal V + , the gate of the transistors M 6B  receives the voltage signal V − ; the sources of the transistors M 6A , M 6B  are electrically connected to a tail current source I M2 /k; 
     a pair of transistors M 7A , M 7B ; the gate of the transistor M 7A  receives the voltage signal V + , the gate of the transistors M 7B  receives the voltage signal V − ; the sources of the transistors M 7A , M 7B  are electrically connected to a tail current source I M3 /k; 
     a pair of transistors M S1 , M S2 ; the drains of the transistors M 5A , M 6A , M 7A  are electrically connected to the gate of the transistor M S2 , the drains of the transistors M 5B , M 6B , M 7B  are electrically connected to the gate of the transistor M S1 ; the source of the transistor M S1  is electrically connected to a tail current source I B1 , the source of the transistor M S2  is electrically connected to a tail current source I B2 ; 
     a pair of resistors R 3A , R 3B ; one end of these resistors is connected with the drains of the transistors M S1 , M S2  to a supply voltage V DD ; the other ends of the resistors R 3A  and R 3b  are connected to the gates of the M S2  and M S1  respectively; and 
     a pair of capacitors C 1 , C 2 ; one end of the capacitor C 1  is electrically connected to the source of the transistor M S2 , the other end of capacitor C 1  is directly connected to the output current terminal I OP ; one end of the capacitor C 2  is electrically connected to the source of the transistor M S1 , the other end of capacitor C 2  is directly connected to the output terminal I ON . 
     In the laser driver of the present invention, the input stage circuit includes: 
     a transistor M D ; the gate and drain of the transistor M D  are electrically connected to the voltage source V DD ; 
     a pair of transistors M 1A , M 1B ; the gates of the transistors M 1A , M 1 , respectively receive the voltage signals V IP , V IN , the output voltage signals V 1IP  and V 1IN  are taken at the drains of M 1A , M 1B  respectively, the sources of the M 1A  and M 1B  are connected to a tail current source I 1 ; and 
     a plurality of resistors R INA , R INB , R 1A , and R 1B ; one end of the resistor R INA  is connected to a voltage source V CM , the other end of the resistor R INA  is connected to the gate of the transistor M 1A ; one end of the resistor R INB  is connected to the voltage source V CM , the other end of the resistor R INB  is connected to the gate of the transistor M 1B ; one end of the resistor R 1A  is connected to the drain of the transistors M 1A , the other end of the resistor R 1A  is connected to the source of the transistor M D ; one end of the resistor R 1B  is connected to the drain of the transistors M 1B , the other end of the resistor R 1B  is connected to the source of the transistor M D . 
     In the laser driver of the present invention, the pre-drive circuit includes: 
     a pair of transistors M 2A , M 2B ; the gates of the transistors M 2A , M 2B  receive the voltage signals V 1IP , V 1IN  respectively, the drains of the transistors M 2A , M 2B  represent the output voltage signals V + , V −  respectively, the sources of the transistors M 2A , M 2B  are connected to a tail current source I 2 ; and 
     a pair of resistors R 2A , R 2B ; one end of the resistors R 2A  is connected to the drain of the transistors M 2A , one end of the resistors R 2B  is connected to the drain of the transistors M 2B , the other ends of the resistors R 2A , R 2B  are electrically connected to the voltage source V DD . 
     In the laser driver of the present invention, the negative capacitance circuit includes: 
     a pair of transistors M 3A , M 3B ; the gates of the transistors M 3A , M 3B  receive the voltage signals V + , V − , the drains of M 3A  and M 3B  receive the voltage signals V − , V +  respectively, the sources of the transistors M 3A , M 3B  are electrically connected to a pair of tail current sources I 3A , I 3B  respectively; and 
     a capacitor C c ; two ends of the capacitor C c  are electrically connected to the tail current sources I 3A , I 3B . 
     In the laser driver of the present invention, the output stage circuit includes: 
     a pair of transistors M 4A , M 4B ; the sources of the transistors M 4A , M 4B  are connected together to a tail current source I M1 , the drains of the transistors M 4A , M 4B  represent the output ends of the current signals I OP , I ON ; the gate of the transistor M 4A  receives the voltage signal V + , and the gate of the transistor M 4B  receives the voltage signal V − ; and 
     a pair of transistors M CA , M CB ; the source and drain of the transistor M CA  are connected together to the output end of the current signal I ON , and the source and drain of the transistor M CB  are connected together to the output end of the current signal I OP ; the gate of the transistor M CA  receives the voltage signal V + , and the gate of the transistor M CB  receives the voltage signal V − . 
     The present invention also provides an integrated circuit, which is encapsulated by a laser driver with high-speed and high-current; the laser driver includes: 
     an input stage circuit which receives a pair of fully differential input voltage signals, V IP , V IN , then, adjusting the common-mode output voltage of signals V 1IP , V 1IN , such that they could be applied to the subsequent stage; 
     a pre-drive circuit, for amplifying the voltage signals V 1IP , V 1IN  to a pair of voltage signals V + , V − ; 
     a fully differential negative capacitance circuit that is directly connected to the output terminals of the pre-drive circuit, V + , V − ; the negative capacitance circuit generates a negative capacitor to reduce the input capacitance of the output stage circuit; 
     an output stage circuit, for receiving the voltage signals V + , V − , then outputting a pair of modulated current signals I OP , I ON ; and 
     an active reverse termination circuit, for absorbing the reflected wave caused by the output mismatch of the output stage circuit; wherein the active reverse termination circuit comprises:
         a pair of transistors M 5A , M 5B ; the gate of the transistor M 5A  receives the voltage signal V + , the gate of the transistors M 5B  receives the voltage signal V − ; the sources of the transistors M 5A , M 5B  are electrically connected to a tail current source I M1 /k;   a pair of transistors M 6A , M 6B ; the gate of the transistor M 6A  receives the voltage signal V + , the gate of the transistors M 6B  receives the voltage signal V − ; the sources of the transistors M 6A , M 6B  are electrically connected to a tail current source I M2 /k;   a pair of transistors M 7A , M 7B ; the gate of the transistor M 7A  receives the voltage signal V + , the gate of the transistors M 7B  receives the voltage signal V − ; the sources of the transistors M 7A , M 7B  are electrically connected to a tail current source I M3 /k;   a pair of transistors M S1 , M S2 ; the drains of the transistors M 5A , M 6A , M 7A  are electrically connected to the gate of the transistor M S2 , the drains of the transistors M 5B , M 6B , M 7B  are electrically connected to the gate of the transistor M S1 ; the source of the transistor M S1  is electrically connected to a tail current source I B1 , the source of the transistor M S2  is electrically connected to a tail current source I B2 ;   a pair of resistors R 3A , R 3B ; one end of these resistors is connected with the drains of the transistors M S1 , M S2  to a supply voltage V DD ; the other ends of the resistors R 3A  and R 3b  are connected to the gates of the M S2  and M S1  respectively; and   a pair of capacitors C 1 , C 2 ; one end of the capacitor C 1  is electrically connected to the source of the transistor M S2 , the other end of capacitor C 1  is directly connected to the output current terminal I OP ; one end of the capacitor C 2  is electrically connected to the source of the transistor M S1 , the other end of capacitor C 2  is directly connected to the output terminal I ON .       

     In the integrated circuit of the present invention, the output stage circuit is a three parallel connected output stages circuit; the first output stage is directly connected to the output of the pre-drive circuit while the second and the third output stages are connected to the output of pre-drive using switching circuits; the pins of the integrated circuit include: 
     a pair of input pins, for transmitting the voltage signals V IP , V IN  to the input stage circuit; 
     a pair of output pins, which represent the output modulation current to the laser diode; 
     a plurality of tail current source pins, for accessing the tail current sources required by the driving circuit of the laser driver; 
     a plurality of voltage source pins, for accessing the voltage sources required by the driving circuit of the laser driver; and 
     two control signals pins, are used to activate the switching circuits designated for the second and the third output driver stages. 
     A solution of the present invention, for solving the above problem, is that the voltage signals V 1IP , V 1IN  are matched and adjusted by the input stage circuit, and then amplified by the pre-drive circuit to the output stage circuits. Finally, the output modulated current signals I OP , I ON  are generated. The negative capacitance circuit is used for reducing the input capacitance of the output stage circuits. The active reverse termination circuit absorbs the reflected wave caused by the output mismatch. There is no terminal resistance in the output stage circuit, so the power consumption of the circuit is much lower than that of the traditional circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  is a module diagram of the laser driver with high-speed and high-current when the number of the output stage circuit is only one, according to the embodiment of the present invention. 
         FIG. 2  is a circuit diagram of the laser driver with high-speed and high-current when the number of the output stage circuit is only one, and the active reverse termination circuit is not shown, according to the embodiment of the present invention. 
         FIG. 3  is a circuit diagram of the active reverse termination circuit of the laser driver, according to the embodiment of the present invention. 
         FIG. 4  is a module diagram of the laser driver with high-speed and high-current when the output stage circuit is a three parallel connected output stages circuit, according to the embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for the purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise disclosed form. 
     First Embodiment 
     Referring to  FIG. 1 , a laser driver with high-speed and high-current is shown. The laser driver with high-speed and high-current of the present invention includes an input stage circuit, a pre-drive circuit, a fully differential negative capacitance circuit, an output stage circuit and an active reverse termination circuit. The pre-drive circuit is electrically connected to the out put ends of the input stage circuit. The negative capacitance circuit is electrically connected to the output ends of the pre-drive circuit. The output stage circuit is electrically connected to the out put ends of the pre-drive circuit. The input ends of the active reverse termination circuit are electrically connected to the input ends of the output stage circuit, and the output ends of the active reverse termination circuit are electrically connected to the output ends of the output stage circuit. 
     A pair of voltage signals V IP , V IN  are applied to the input stage circuit which amplifies these input signals to a pair of output voltage signals V 1IP , V 1IN . Then the voltage signals V 1IP , V 1IN  are amplified by the pre-drive circuit to a pair of voltage signals V + , V −  to the output stage circuit, and finally, a pair of modulated current signals I OP , I ON  are generated by the output stage circuit. In addition, the negative capacitance circuit generates a negative capacitor to reduce the input capacitance of the output stage circuit. 
     Referring to  FIG. 2 , the input stage circuit is used for inputting the voltage signals V IP , V IN , then matching and adjusting the voltage signals V IP , V IN  into a pair of voltage signals V 1IP , V 1IN . The input stage circuit includes a transistor M D , a pair of transistors M 1A , M 1B , and a plurality of resistors R INA , R INB , R 1A , R 1B . The gate and drain of the transistor M D  is connected to the voltage source V DD . The gates of the transistors M 1A , M 1B  respectively are used as the input ends of the input stage circuit, the drains of transistors M 1A , M 1B  are electrically connected to input ends of the pre-drive circuit. The gates of the transistors M 1A , M 1B  receive the voltage signals V IP , V IN , respectively, the output voltage signals V 1IP  and V 1IN  are taken at the drains of the transistors M 1A , M 1B , respectively. The sources of these transistors are connected to a tail current source I 1 . 
     One end of the resistor R INA  is connected to a voltage source V CM , the other end of the resistor R INA  is connected to the gate of the transistor M 1A , one end of the resistor R INB  is connected to the voltage source V CM , the other end of the resistor R INB  is connected to the gate of the transistor M 1B ; one end of the resistor R 1A  is connected to the drain of the transistors M 1A , the other end of the resistor R 1A  is connected to the source of the transistor M D ; one end of the resistor R 1B  is connected to the drain of the transistors M 1B , the other end of the resistor R 1B  is connected to the source of the transistor M D . 
     In this embodiment, both of the resistors, R INA  and R INB , are 50 ohms. The diode-connected transistor M D  is used to adjust the common-mode output voltage to be suitable for the subsequent stage. The pre-drive circuit is used for amplifying the voltage signals V 1IP , V 1IN  to output the voltage signals V + , V − . 
     The pre-drive circuit includes a pair of transistors M 2A , M 2B  and a pair of resistors R 2A , R 2B . The gates of the transistors M 2A , M 2B  receive the voltage signals V 1IP , V 1IN , respectively, the drains of the transistors M 2A , M 2B  represent the output voltage signals V + , V − , respectively. The sources of the transistors M 2A , M 2B  are connected together to a tail current source I 2 . One end of the resistors R 2A  is connected to the drain of the transistors M 2A , one end of the resistors R 2B  is connected to the drain of the transistors M 2B , the other ends of the resistors R 2A , R 2B  are connected to the voltage source V DD . The diode-connected transistor M D  is used to adjust the output common-mode voltage of the input stage circuit, such that the transistors M 2A , M 2B  operate in the saturation region during switching. 
     Both ends of the negative capacitance circuit are connected to the two output terminals of the pre-drive circuit V + , V − . The negative capacitance circuit includes a pair of transistors M 3A , M 3B  and a capacitor C c . The gates of the transistors M 3A , M 3B  receive the voltage signals V + , V −  respectively, the drains of transistors M 3A  and M 3B  are connected to the voltage signals V − , V + , respectively, and the sources of the transistors M 3A , M 3B  are connected to a pair of tail current sources I 3A , I 3B . The gate of the transistors M 3A  and the drain of the transistors M 3B  are electrically connected together to the positive output end of the pre-drive circuit, the gate of the transistors M 3B  and the drain of the transistors M 3A  are electrically connected together to the negative output end of the pre-drive circuit. Two ends of the capacitor C c  are connected to the tail current sources I 3A , I 3B . The cross-coupled transistors M 3A , M 3B  and the capacitor C c  can generate a negative capacitance at the output end of the pre-drive circuit, which can reduce the capacitance at the interface between the pre-driver and output driver, increasing the circuit bandwidth and speed. 
     The output stage circuit is used for receiving the voltage signals V + , V − , then outputting the modulated current signals I OP , I ON . The negative capacitance circuit generates a negative capacitor to reduce the input capacitance of the output stage circuit. The output stage circuit includes a pair of transistors M 4A , M 4B , and a pair of transistors M CA , M CB . The sources of the transistors M 4A , M 4B  are connected together to a tail current source I M1 , the drains of the transistors M 4A , M 4B  are connected to the output ends of the current signals I OP , I ON , respectively. The gate of the transistor M 4A  receives the voltage signal V + , and the gate of the transistor M 4B  receives the voltage signal V − . The source and drain of the transistor M CA  are connected together to the output end of the current signal I ON , and the source and drain of the transistor M CB  are connected together to the output end of the current signal I OP . The gate of the transistor M CA  receives the voltage signal V + , and the gate of the transistor M CB  receives the voltage signal V − . The transistors M CA , M CB  can form an NMOS capacitor, reducing the Miller effect of transistors M 4A , M 4B . 
     Referring to  FIG. 3 , the active reverse termination circuit includes a pair of transistors M 5A , M 5B , a pair of transistors M 6A , M 6B , a pair of transistors M 7A , M 7B , a pair of transistors M S1 , M S2 , a pair of resistors R 3A , R 3B , and a pair of capacitors C 1 , C 2 . The gate of the transistor M 5A  is electrically connected to the positive output end of the pre-drive circuit, the gate of the transistor M 5B  is electrically connected to the negative output end of the pre-drive circuit. In this embodiment, the gate of the transistor M 5A  receives the voltage signal V + , the gate of the transistors M 5B  receives the voltage signal V − . The sources of the transistors M 5A , M 5B  are connected to a tail current source I M1 /k. The gate of the transistor M 6A  is electrically connected to the positive output end of the pre-drive circuit, the gate of the transistor M 6B  is electrically connected to the negative output end of the pre-drive circuit. The gate of the transistor M 6A  receives the voltage signal V + , the gate of the transistors M 6B  receives the voltage signal V − . The sources of the transistors M 6A , M 6B  are connected to a tail current source I M2 /k. The gate of the transistor M 7A  is electrically connected to the positive output end of the pre-drive circuit, the gate of the transistor M 7B  is electrically connected to the negative output end of the pre-drive circuit. The gate of the transistor M 7A  receives the voltage signal V + , the gate of the transistors M 7B  receives the voltage signal V − . The sources of the transistors M 7A , M 7B  are connected to a tail current source I M3 /k. 
     The drains of the transistors M 5A , M 6A , M 7A  are connected to the gate of the transistor M S2 , the drains of the transistors M 5B , M 6B , M 7B  are connected to the gate of the transistor M S1 . The source of the transistor M S1  is connected to a tail current source I B1 , the source of the transistor M S2  is connected to a tail current source I B2 . One end of the resistors R 3A , R 3B  is connected with the drains of the transistors M S1 , M S2  to a supply voltage V DD . The other ends of the resistors R 3A  and R 3b  are connected to the gates of the M S2  and M S1 , respectively. One end of the capacitor C 1  is electrically connected to the source of the transistor M S2 , the other end of capacitor C 1  is directly connected to the output current terminal I OP ; one end of the capacitor C 2  is electrically connected to the source of the transistor M S1 , the other end of capacitor C 2  is directly connected to the output terminal I ON . 
     In this embodiment, the transistors M S1 , M S2  form source follower stages with low output impedance, about 20Ω, which helps to absorb reflected waves from the laser side. The active reverse back termination circuit is AC coupled to the output terminals of the driver circuit using C 1  and C 2 . The AC coupling technique isolates the DC voltage of the active reverse circuit and the driver circuit. Therefore, the active reverse termination circuit will not sink or source any excess DC current from or to the output driver. There is no need to use an additional dc offset cancellation circuit to save power and area. Meanwhile, the output stage circuit does not need to use terminal resistors to absorb reflected waves, thus greatly reducing power consumption. 
     As described above, the voltage signals V 1IP , V 1IN  are matched and adjusted by the input stage circuit, and then amplified by the pre-drive circuit to the output stage circuits. Finally, the output modulated current signals I OP , I ON  are generated. The negative capacitance circuit is used for reducing the input capacitance of the output stage circuit. The active reverse termination circuit absorbs the reflected wave caused by the output mismatch. There is no terminal resistance in the output stage circuit, so the power consumption of the circuit is much lower than that of the traditional circuit. 
     Second Embodiment 
     Referring to  FIG. 1 , a laser driver with high-speed and high-current is shown. The laser driver with high-speed and high-current of the present invention includes an input stage circuit, a pre-drive circuit, a negative capacitance circuit, a three parallel-connected output stages circuit and an active reverse termination circuit. A pair of voltage signals V IP , V IN  are applied to the input stage circuit which amplifies these input signals to a pair of output voltage signals V 1IP , V 1IN . Then the voltage signals V 1IP , V 1IN  are amplified by the pre-drive circuit to a pair of voltage signals V + , V −  to the output stage circuit, and finally, a pair of modulated current signals I OP , I ON  are generated by the output stage circuit. In addition, the negative capacitance circuit generates a negative capacitor to reduce the input capacitance of the output stage circuit. 
     Referring to  FIG. 2  again, the input stage circuit is used for inputting the voltage signals V IP , V IN , then matching and adjusting the voltage signals V IP , V IN  into a pair of voltage signals V 1IP , V 1IN . The input stage circuit includes a transistor M D , a pair of transistors M 1A , M 1B , and a plurality of resistors R INA , R INB , R 1A , R 1B . The gate and drain of the transistor M D  is connected to the voltage source V DD . The gates of the transistors M 1A , M 1B  receive the voltage signals V IP , V IN , respectively, the output voltage signals V 1IP  and V 1IN  are taken at the drains of the transistors M 1A , M 1B , respectively. The sources of these transistors are connected to a tail current source I 1 . One end of the resistor R INA  is connected to a voltage source V CM , the other end of the resistor R INA  is connected to the gate of the transistor M 1A ; one end of the resistor R INB  is connected to the voltage source V CM , the other end of the resistor R INB  is connected to the gate of the transistor M 1B ; one end of the resistor R 1A  is connected to the drain of the transistors M 1A , the other end of the resistor R 1A  is connected to the source of the transistor M D ; one end of the resistor R 1B  is connected to the drain of the transistors M 1B , the other end of the resistor R 1B  is connected to the source of the transistor M D . 
     In this embodiment, both of the resistors, R INA  and R INB , are 50 ohms. The diode-connected transistor M D  is used to adjust the common-mode output voltage to be suitable for the subsequent stage. The pre-drive circuit is used for amplifying the voltage signals V 1IP , V 1IN  to output the voltage signals V + , V − . The pre-drive circuit includes a pair of transistors M 2A , M 2B  and a pair of resistors R 2A , R 2B . The gates of the transistors M 2A , M 2B  receive the voltage signals V 1IP , V 1IN , respectively, the drains of the transistors M 2A , M 2B  represent the output voltage signals V + , V − , respectively. The sources of the transistors M 2A , M 2B  are connected together to a tail current source I 2 . One end of the resistors R 2A  is connected to the drain of the transistors M 2A , one end of the resistors R 2B  is connected to the drain of the transistors M 2B , the other ends of the resistors R 2A , R 2B  are connected to the voltage source V DD . The diode-connected transistor M D  is used to adjust the output common-mode voltage of the input stage circuit, such that the transistors M 2A , M 2B  operate in the saturation region during switching. Both ends of the negative capacitance circuit are connected to the two output terminals of the pre-drive circuit V + , V − . The negative capacitance circuit includes a pair of transistors M 3A , M 3B  and a capacitor C c . The gates of the transistors M 3A , M 3B  receive the voltage signals V + , V − , respectively, the drains of M 3A  and M 3B  are connected to the voltage signals V − , V + , respectively, and the sources of the transistors M 3A , M 3B  are connected to a pair of tail current sources I 3A , I 3B . Two ends of the capacitor C c  are connected to the tail current sources I 3A , I 3B . The cross-coupled transistors M 3A , M 3B  and the capacitor C c  can generate a negative capacitance at the output end of the pre-drive circuit, which can reduce the capacitance at the interface between the pre-driver and output driver, increasing the circuit bandwidth and speed. 
     The output stage circuits are used for receiving the voltage signals V + , V − , then outputting the modulated current signals I OP , I ON . The negative capacitance circuit generates a negative capacitor to reduce the input capacitance of the output stage circuit. The output stage circuit includes a pair of transistors M 4A , M 4B , and a pair of transistors M CA , M CB . The sources of the transistors M 4A , M 4B  are connected together to a tail current source I M1 , the drains of the transistors M 4A , M 4B  are connected to the output ends of the current signals I OP , I ON , respectively. The gate of the transistor M 4A  receives the voltage signal V + , and the gate of the transistor M 4B  receives the voltage signal V − . The source and drain of the transistor M CA  are connected together to the output end of the current signal I ON , and the source and drain of the transistor M CB  are connected together to the output end of the current signal I OP . The gate of the transistor M CA  receives the voltage signal V + , and the gate of the transistor M CB  receives the voltage signal V − . The transistors M CA , M CB  can form an NMOS capacitor, reducing the Miller effect of transistors M 4A , M 4B . 
     In this embodiment, the first output stage is directly connected to the output of the pre-drive circuit while the second and the third output stages are connected to the output of the pre-driver using switching circuits. Each switching circuit includes a pair of transistors M S3 , M S4 ; the gates of the transistors M S3 , M S4  receive a control signal V s , the sources of the transistors M S3 , M S4  are connected to the inputs of the second output stage, the drains of the transistors M S3 , M S4  receive the voltage signals V + , V − , respectively. 
     In addition, the number of the output stage circuits is three, and the number of the switching circuits is two. The internal structures of these output stage circuits are the same, and the internal structures of the two switching circuits are the same. One of the witching circuits is controlled by a control signal V s1 , and the other switching circuit is controlled by a control signal V s2 . When the control signals V s1 , V s2  are 0, the output modulation current can be adjusted from 10 mA to 50 mA; when the switch control signal V s1  is 1 and the switch control signal V s2  is 0, the output modulation current can reach 100 mA; when the switch control signals V s1 , V s2  are 1, the output modulation current is as high as 150 mA. 
     Referring to  FIG. 3  again, the active reverse termination circuit includes a pair of transistors M 5A , M 5B , a pair of transistors M 6A , M 6B , a pair of transistors M 7A , M 7B , a pair of transistors M S1 , M S2 , a pair of resistors R 3A , R 3B  and a pair of capacitors C 1 , C 2 . The gate of the transistor M 5A  receives the voltage signal V + , the gate of the transistors M 5B  receives the voltage signal V − . The sources of the transistors M 5A , M 5B  are connected to a tail current source I M1 /k. The gate of the transistor M 6A  receives the voltage signal V + , the gate of the transistors M 6B  receives the voltage signal V − . The sources of the transistors M 6A , M 6B  are connected to a tail current source I M2 /k. The gate of the transistor M 7A  receives the voltage signal V + , the gate of the transistors M 7B  receives the voltage signal V − . The sources of the transistors M 7A , M 7B  are connected to a tail current source I M3 /k. 
     The drains of the transistors M 5A , M 6A , M 7A  are connected to the gate of the transistor M S2 , the drains of the transistors M 5B , M 6B , M 7B  are connected to the gate of the transistor M S1 . The source of the transistor M S1  is connected to a tail current source I B1 , the source of the transistor M S2  is connected to a tail current source I B2 . One end of the resistors R 3A , R 3B  is connected with the drains of the transistors M S1 , M S2  to a supply voltage V DD . The other ends of the resistors R 3A  and R 3b  are connected to the gates of the M S2  and M S1 , respectively. One end of the capacitor C 1  is electrically connected to the source of the transistor M S2 , the other end of capacitor C 1  is directly connected to the output current terminal I OP ; one end of the capacitor C 2  is electrically connected to the source of the transistor M S1 , the other end of capacitor C 2  is directly connected to the output terminal I ON . The active reverse termination circuit absorbs reflection waves due to output mismatch through the capacitors C 1 , C 2 . 
     In this embodiment, the transistors M S1 , M S2  form source follower stages with low output impedance, about 20Ω, which helps to absorb reflected waves from the laser side. The active reverse back termination circuit is AC coupled to the output terminals of the driver circuit using C 1  and C 2 . The AC coupling technique isolates the DC voltage of the active reverse circuit and the driver circuit. Therefore, the active reverse termination circuit will not sink or source any excess DC current from or to the output driver. There is no need to use an additional dc offset cancellation circuit which helps to save power and area. Meanwhile, the output stage circuit does not need to use terminal resistors to absorb reflected waves, thus greatly reducing power consumption. 
     As described above, the voltage signals V 1IP , V 1IN  are matched and adjusted by the input stage circuit, and then amplified by the pre-drive circuit to the output stage circuits. Finally, the output modulated current signals I OP , I ON  are generated. The negative capacitance circuit is used for reducing the input capacitance of the output stage circuits. The active reverse termination circuit absorbs the reflected wave caused by the output mismatch. There is no terminal resistance in the output stage circuit, so the power consumption of the circuit is much lower than that of the traditional circuit. 
     Third Embodiment 
     An integrated circuit is shown as an embodiment, and the integrated circuit is encapsulated by a laser driver with high-speed and high-current. The pins of the integrated circuit include a pair of input pins, a pair of output pins, a plurality of tail current source pins and a plurality of voltage source pins. 
     The input pins are used for transmitting the voltage signals V IP , V IN  to the input stage circuit. The output pins represent the output modulation current to the laser diode I OP , I ON . The tail current source pins are used for accessing the tail current sources required by the driving circuit. The tail current sources include the sources I 1 , I 2 , I 3A , I 3B , I M1 /k, I M2 /k, I M3 /k, I B1 , I B2  and three I M1 . The voltage source pins are used for accessing the voltage sources (such as V DD  and V CM ) required by the driving circuit. 
     Fourth Embodiment 
     An integrated circuit is shown as an embodiment, and the integrated circuit is encapsulated by a laser driver with high-speed and high-current. The pins of the integrated circuit include a pair of input pins, a pair of output pins, a plurality of tail current source pins, a plurality of voltage source pins, and at least one control signal pin. 
     The input pins are used for transmitting the voltage signals V IP , V IN  to the input stage circuit. The output pins represent the output modulation current to the laser diode I OP , I ON . The tail current source pins are used for accessing the tail current sources required by the driving circuit. The tail current sources include the sources I 1 , I 2 , I 3A , I 3B , I M1 /k, I M2 /k, I M3 /k, I B1 , I B2  and three I M1 . The voltage source pins are used for accessing the voltage sources (such as V DD  and V CM ) required by the driving circuit. While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not to be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.