Patent Publication Number: US-6905891-B2

Title: Method for processing multiple semiconductor devices for test

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor device processing, and more specifically, to processing multiple semiconductor devices for test. 
     RELATED ART 
     As the semiconductor industry evolves, devices continually become smaller. This continuing evolution leads to very small packages which become increasingly difficult to handle and time consuming to test. Device package technologies have progressed from discrete packaging for individual devices to packaging many devices at one time in a single format. However, in order to perform testing of individual devices packaged together, they must be electrically isolated. 
     One prior art method of testing devices packaged together involves molding an array of devices. The molded arrays are then electrically isolated using a half saw method. However, the half saw method results in a brittle array for testing since the molding material is the only material holding the array of devices in place. Furthermore, the half saw method may remove any periphery material surrounding the molded array which may have contained alignment and identification information, thus increasing process time and overall cost. 
     Accordingly, a need exists for a method for handling and testing smaller packages which maintains physical integrity while reducing process time and cost. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which: 
         FIG. 1  illustrates a bottom view of an encapsulated packaged array in accordance with one embodiment of the present invention; 
         FIG. 2  illustrates a bottom view of a encapsulated packaged array having a temporary adhesive substrate in accordance with one embodiment of the present invention; 
         FIG. 3  illustrates a cross sectional view of the encapsulated packaged array of  FIG. 2 , taken along line  3 — 3 , after performing a half saw process in accordance with one embodiment of the present invention; 
         FIG. 4  illustrates a cross sectional view of the encapsulated packaged array of  FIG. 2 , taken along line  3 — 3 , after performing a full saw process in accordance with an alternate embodiment of the present invention; and 
         FIG. 5  illustrates a process flow in accordance with an embodiment of the present invention. 
       Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     Embodiments of the present invention allow for the electrical isolation of encapsulated packaged arrays while maintaining physical integrity of the packaged arrays for testing and transport. These encapsulated package arrays may refer to MAPBGAs (molded array package ball grid arrays), QFNs (quad flat package no leads), MLPs (molded leadless packages), other leadless packages, or the like. A temporary adhesive substrate may be used to maintain the physical integrity of electrically isolated devices that are either physically isolated or physically connected via an encapsulation layer. A support structure in addition to the temporary adhesive substrate may also be used to provide further support and to provide an area for markings, as will be discussed below. The temporary adhesive substrate therefore allows for the transport and testing of multiple devices in parallel. 
       FIG. 1  illustrates a bottom view of an encapsulated packaged array  10  in accordance with one embodiment of the present invention. Packaged array  10  includes a package substrate  12  and a plurality of semiconductor devices  14  (whose outlines are indicated by dotted lines since they are on the opposite side of package substrate  12  and cannot be seen from the bottom view). Package substrate  12  can be any type of substrate, such as, for example, a metal substrate (e.g. a lead frame), an organic substrate (e.g. fiber glass), or any other type of substrate. Packaged array  10  includes arrays  16 ,  6 , and  8 , wherein each array includes a same number of devices  14 . (The arrays  16 ,  6 , and  8 , are indicated by dashed lines in  FIGS. 1 and 2 .) However, in alternate embodiments, each array may include a different number of devices, or packaged array  10  may include a single array, such as a panel array. That is, packaged array  10  may refer to any configuration having at least two semiconductor devices (such as semiconductor devices  14 ). The outer periphery of substrate  12  (such as the area surrounding arrays  16 ,  6 , and  8  in  FIG. 1 ) may include markings such as indexing, alignment fiducials, electrical contacts that may need to be preserved for testing, or any other type of markings, such as identification markings, etc. The identification markings may include a bar code, a two dimension matrix, radio frequency circuitry, etc. Package substrate  12  also includes a variety of interconnects or traces that provide for electrical connections between devices, such as devices  14 , or within devices. Therefore, the devices  14  of  FIG. 1  may be electrically connected to other devices (e.g. neighboring devices) within an array or across arrays. 
     Semiconductor devices  14  each include at least one semiconductor die (not shown) electrically connected to package substrate  12  and an encapsulation layer. (Note that the die within semiconductor devices  14  may include any type of circuitry that perform any type of function.) In one embodiment, each array  16 ,  6 , and  8  is encapsulated individually (where, in this embodiment, the dashed lines defining arrays  16 ,  6 , and  8  may also correspond to the outer edge of each array&#39;s encapsulation layer). Alternatively, a single encapsulation layer may be used for all devices  14  on package substrate  12  (such as, for example, in the case of a single panel array). The encapsulation can be performed by a variety of difference processes, such as, for example, plastic overmolding, conformal coating (e.g. epoxy coating), or any other encapsulation process.  FIGS. 2-4  will be discussed below in combination with FIG.  5 . 
       FIG. 5  illustrates a process flow  24  for processing multiple devices for test. In block  26 , a semiconductor wafer is provided. In block  28 , singulation of the semiconductor wafer is performed. The singulated die are then attached to a package substrate (in block  30 ) using, for example, an adhesive. As discussed in reference to  FIG. 1 , the package substrate can include any type of material, such as metal, organic, etc. In block  32 , electrical connections are provided for the die. For example, in one embodiment, the die are wire bonded to leads on the package substrate. Alternatively, other methods may be used to provide electrical connections for the die, such as, for example, bump methods. Flow then proceeds to block  34  where the package substrate and the attached die are encapsulated, thus resulting in an encapsulated packaged array, such as packaged array  10  of FIG.  1 . 
     Flow proceeds to block  36  where a temporary adhesive substrate and support structure are added.  FIG. 2  illustrates the packaged array  10  of  FIG. 1  with an additional temporary adhesive substrate  20  and support structure  18 . In one embodiment, temporary adhesive substrate  20  includes an adhesive tape and support structure  18  includes a metallic frame at the periphery of the tape. The encapsulated side of the array is attached to the adhesive side of the tape such that the metallic frame provides support and positional integrity for the array. Note that the side opposite the encapsulated side is left exposed to allow for electrical contacts for test. (However, note that in alternate embodiments, a temporary adhesive substrate may be used on either side of the packaged array, or alternatively, on both sides, where the temporary adhesive substrate may cover all or portions of the packaged array.) The metallic frame may also be marked with information that may be provided to a data base for identification or other testing purposes.  FIG. 2  illustrates a bottom view of packaged array  10  having a temporary adhesive substrate  20  and support structure  18  surrounding an outer edge  21  of package substrate  12 . (Note that outer edge  21  may also be referred to as perimeter  21 .) In this embodiment, a gap exists between outer edge  21  and support structure  18  such that temporary adhesive substrate  20  is visible. However, in alternate embodiments, outer edge  21  may be adjacent to support structure  18 , or may overlap support structure  18 . 
     Alternate embodiments may use any type of temporary adhesive substrates other than tape, and any type of support structure (such as metal, plastic, ceramic, etc.) that provides the necessary degree of support. Alternatively, temporary adhesive substrate  20  may not require a separate support structure at all. That is, support structure  18  may be optional or may be within temporary adhesive substrate  20 . For example, temporary adhesive substrate  20  can be a less flexible material than tape which is still capable of providing sufficient support to packaged array  10 . Also, temporary adhesive substrate  20  may include any necessary markings if no support structure is necessary. Furthermore, temporary adhesive substrate  20  can be any type of temporary substrate that can later be removed, and can be attached or fastened to the encapsulation portion of packaged array  10  using any variety of methods, such as mechanical forces, electrostatic forces, magnetic forces, etc. 
     Flow then proceeds to block  40  of  FIG. 5  where electrical isolation of semiconductor devices  14  is performed.  FIG. 3  illustrates one embodiment for electrically isolating devices  14 .  FIG. 3  illustrates a cross sectional view along line  3 - 3  of packaged array  10  after a half saw process. The half saw process electrically isolates devices  14  by severing package substrate  12  surrounding each device  14  and thus severing any electrical connections that existed within package substrate  12  between devices  14 . The half saw process leaves at least a portion of the encapsulation layer  17  between devices  14  thus maintaining a physical connection between devices  14 . This helps to provide positional integrity for test. If the encapsulation layer sufficiently overlaps the outer periphery of an array (such as arrays  16 ,  6 , and  8 ), portions  19  of the encapsulation layer  17  may remain after the half saw process. However, in alternate embodiments, the half saw process may remove these portions  19 .  FIG. 4  illustrates a cross sectional view also along line  3 — 3  of an alternate embodiment for electrically isolating devices  14  where a full saw process is used. The full saw process eliminates any electrical and physical connections between devices  14  such that only temporary adhesive structure  20  maintains the positional integrity of devices  14 . That is, package substrate  12  as well as encapsulation layer  17  are physically separated via the full saw process. If the encapsulation layer sufficiently overlaps the outer periphery of an array, portions  22  of the encapsulation layer may remain after the full saw process. Alternatively, the full saw process may remove these portions  22  as well.  FIGS. 3 and 4  illustrate all electrical connections between each device  14  being severed since each device  14  is now attached to a physically isolated portion of package substrate  12 . However, in alternate embodiments, only selected electrical connections may be severed. Furthermore, all or selected electrical connections may be severed between only selected devices  14 . That is, any degree of electrical isolation between devices may be implemented. Also, processes other than sawing may be used to isolate the devices. For example, a laser may used to electrically isolate devices  14 . 
     Flow proceeds to block  42  of  FIG. 5  where devices  14  are tested using a testing platform. That is, the devices  14  attached to temporary adhesive structure  20  are generally placed on a testing platform, support platform, or chuck for testing. (Therefore, temporary adhesive structure  20  is generally a separate portion or substrate from the testing platform; however, in an alternate embodiment, temporary adhesive structure  20  may be an integrated portion of the testing platform.) The tests performed on devices  14  may include thermal tests (e.g. thermal conditioning), environmental tests, electrical tests, functional tests, physical tests, etc. The positional integrity of the electrically isolated devices  14  provided by temporary adhesive substrate  20  allows the testing of devices  14  to be performed in parallel. Temporary adhesive substrate  20  also allows for the transport of multiple electrically isolated devices simultaneously while maintaining positional integrity of devices  14 . Furthermore, test results or any other information may be correlated to the corresponding semiconductor device or array through the use of markings on the temporary adhesive substrate  20  or support structure  18 . 
     Flow then proceeds to an optional singulation step  44 . For example, if a full saw process was used in step  40 , singulation step  44  would not be necessary because the die are already physically separate from each other. However, if a half saw process was used in step  40 , singulation step  44  is performed to fully singulate the semiconductor devices. Therefore, if further singulation is necessary, step  44  can be included in the flow. 
     After testing and optional singulation, flow proceeds to block  46  where temporary adhesive substrate  20  and support structure  18  are removed. After removal of temporary adhesive substrate  20 , semiconductor devices  14  may optionally be sorted based on test results. Alternatively, temporary adhesive substrate  20  and support structure  18  (if any) may be removed during sorting. Note that after the temporary adhesive substrate (and support structure, if any) are removed, the temporary adhesive substrate and support structure can be reused for further packaged array processing. 
     In an alternate embodiment to the flow of  FIG. 5 , the package substrate may be optional. That is, after wafer singulation in step  28 , the singulated die may be encapsulated without the use of a package substrate. For example, the singulated die may be placed in a holder or carrier structure for positional integrity during encapsulation. The resulting array, held together by the encapsulation, would then proceed to step  36  where a temporary adhesive substrate and support structure are added. (In this embodiment, the resulting array may be transported with or without the holder or carrier structure.) Also, note that, as discussed above, the support structure may not be needed depending on the type of temporary adhesive substrate used. Since no package substrate exists in this embodiment, step  40  would no longer be necessary and flow would proceed to test block  42 . After test  42 , flow proceeds to singulate step  44  in order to fully singulate the semiconductor devices, and subsequently, to temporary adhesive substrate removal step  46 . 
     Alternatively, after wafer singulation step  28 , the singulated die may be individually encapsulated and placed within a holder or carrier structure for maintaining positional integrity. Flow would then proceed to step  36  where a temporary adhesive substrate (and, if necessary, a support structure) would be added. In yet another embodiment, the individually encapsulated singulated die may be attached directly to a temporary adhesive substrate. In these embodiments, after the addition of the temporary adhesive substrate, flow would proceed to test  42  and temporary adhesive substrate removal  46 . Note that singulation step  44  would not be necessary since the devices are already physically isolated. 
     In an alternate embodiment, the temporary adhesive substrate may be used to perform Known Good Die testing. For example, in this embodiment, after wafer singulation  28 , flow proceeds to step  36  where the singulated die are attached to the temporary adhesive substrate. That is, the semiconductor die are not packaged (i.e. encapsulated) prior to testing (at step  40 ). Therefore, the testing at step  40  may be used to identify which semiconductor die have circuitry that properly perform predetermined operations (as may be defined by a predetermined specification). In this embodiment, after wafer singulation, a “pick and place” tool may be used to place the semiconductor die onto the temporary adhesive substrate. (Note that in alternate embodiments, the wafer prior to singulation may be placed on the temporary adhesive substrate for testing.) 
     In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. 
     Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.