Patent Publication Number: US-6982732-B2

Title: Display panel driving method with selectable driving pattern

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to a method for driving a display panel in which are arranged light emission (hereinafter, simply referred to as “emission”) elements having only two states, emitting and non-emitting. 
   2. Description of the Related Art 
   With the rend toward display device with larger screens in recent years, displays with thinner shapes have been sought. AC-discharge type plasma display panels have attracted attention as one thin-type display device. 
     FIG. 1  shows in summary the configuration of a plasma display device equipped with such a plasma display panel. 
   In  FIG. 1 , the plasma display panel PDP  10  comprises m column electrodes D 1  to D m , as data electrodes, and n row electrodes X 1  to X n  and Y 1  to Y n , arranged to intersect each of the column electrodes. Each of the pairs X and Y of row electrodes corresponds to a row of the screen. These column electrodes D and row electrodes X and Y are formed on two glass substrate s, arranged in opposition and enclosing a discharge space into which is injected a discharge gas. At the portions of intersection of each of the row electrodes and column electrodes, discharge cells serving as display elements corresponding to individual pixels are formed. 
   Because the discharge cells utilize a discharge phenomenon, they have only two states, “emitting” and “non-emitting”. That is, discharge cells are capable of representing only the brightnesses of two grayscales, at the minimum brightness (the non-emitting state) and at the maximum brightness (the emitting state). The driving device  100  executes grayscale driving of the above PDP  10 , in which such discharge cells are arranged in a matrix shape, using a subfield method in which intermediate grayscale brightnesses corresponding to input image signals are represented. 
   In the subfield method, the display interval for one subfield is divided into, for example, eight subfields SF 1  to SF 8 , as shown in  FIG. 2 . To each of these subfields SF 1  to SF 8  is allocate d a number of times emission is to be executed within that subfield. Hence by changing the combination of the subfields during which emission is executed and the subfields during which emission is not executed based on the input image signal, emission is executed, within the display interval of one field, a number of times corresponding to the brightness level of the input image signal. As a result, an intermediate brightness is perceived corresponding to the total number of emissions executed within the field display interval in question. 
     FIG. 3  is a figure showing one example of emission driving pattern is, indicating combinations of subfields for which emission is executed and subfields for which emission is not executed. 
   The driving device  100  selects one emission driving pattern from among the nine types shown in  FIG. 3 , according to the input image signal. The different driving pulses are applied to the column electrodes D and row electrodes X and Y of the PDP  10  so as to execute emission for the number of times shown in  FIG. 2  only in those subfields indicated by white circles in the selected emission driving pattern. 
   Through the nine types of emission driving patterns shown in  FIG. 3 , images can be displayed having nine intermediate brightnesses, with emission brightness ratios of 0, 1, 7, 23, 47, 82, 128, 185, and 255. 
   Here, by means of the emission driving patterns shown in  FIG. 3 , after first putting a discharge cell in the non-emitting state in one subfield within a field interval, emission is not executed again in subsequent subfields. That is, as indicated by the white circles, emission driving patterns wherein subfields in which emission is executed continuously (hereafter called the “continuous emission state”) and subfields in which the extinguished state is continuous (hereafter called the “continuous extinguished state”) alternate within a single field interval are excluded. As a result, so-called false contours, occurring on the boundaries of two image regions in which the above continuous emission state and the above continuous extinguished state alternate, is suppressed. 
   In an emission driving pattern like that shown in  FIG. 3 , the frequency of switching between the above continuous emission state and the above continuous extinguished state is equal to the vertical sync frequency which determines the display interval for a single field. Hence there is concern that when a PAL television signal, which has only a 50 Hz vertical sync frequency, may be supplied as the input image signal, and when the brightness levels represented by this image signal are comparatively high, flicker may occur. 
   SUMMARY OF THE INVENTION 
   The present invention was devised in consideration of this problem, and has as an object the provision of a display panel driving method which is capable of image display with false contours suppressed, without the occurrence of flicker even when the vertical sync frequency of the input image signal is low. 
   The display panel driving method of this invention is a method for driving a display panel in which, in a display panel which forms a display screen by means of a plurality of emission elements, each of the above emission elements is driven to emit light in each of N subfields constituting one field interval of an input image signal. In this method, depending on the vertical sync frequency of the above input image signal and the mean image brightness represented by the above input image signal, either a first emission driving sequence is executed, in which intermediate brightnesses are represented for each of N+1 gradations, from the first grayscale to the (N+1)th grayscale, by causing the above emission elements to emit in n (where n is an integer from 0 to N) of the above subfields which are continuous within the above one field interval, corresponding to the brightness level represented by the above input image signal; or, a second emission driving sequence is executed, in which intermediate brightnesses are represented for each of N+1 gradations, from the first grayscale to the (N+1)th grayscale, by using the above emission elements to emit during the first half of the above field period in each of the above subfields which are continuous, corresponding to the brightness level represented by the above input image signal, and then, in the second half of the field period, causing the above emission elements to emit in each of the above subfields which are continuous, corresponding to the brightness level represented by the above input image signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a figure showing in summary the configuration of a plasma display device; 
       FIG. 2  is a figure showing one example of an emission driving format, based on the subfield method; 
       FIG. 3  is a figure showing one example of an emission driving pattern; 
       FIG. 4  is a figure showing the configuration of a plasma display device which drives a plasma display panel according to a driving method of this invention; 
       FIG. 5  is a figure showing the internal configuration of the data conversion circuit  30 ; 
       FIG. 6  is a figure showing the data conversion characteristic in the first data conversion circuit  32 ; 
       FIG. 7  is a figure showing one example of a data conversion table, based on the data conversion characteristic shown in  FIG. 6 ; 
       FIG. 8  is a figure showing one example of a data conversion table, based on the data conversion characteristic shown in  FIG. 6 ; 
       FIG. 9  is a figure showing the internal configuration of the multi-graycale processing circuit  33 ; 
       FIG. 10  is a figure used to explain the operation of the error diffusion processing circuit  330 ; 
       FIG. 11  is a figure showing the internal configuration of the dither Processing circuit  350 ; 
       FIG. 12  is a figure used to explain the operation of the dither processing circuit  350 ; 
       FIG. 13  is a figure showing a data conversion table used in the second data conversion circuit  34 , and an emission driving pattern; 
       FIG. 14  is a figure showing a data conversion table used in the second data conversion circuit  35 , and an emission driving pattern; 
       FIG. 15  is a figure showing one example of an emission driving format (based on the selective erasing address method) during first emission driving, adopted when the vertical sync frequency of the input image signal is equal to or higher than a prescribed frequency, or when the brightness level of the input image signal is comparatively low; 
       FIG. 16  is a figure showing on example of an emission driving format (based on the selective erasing address method) during second emission driving, adopted when the vertical sync frequency of the input image signal is lower than a prescribed frequency, and the brightness level of the input image signal is comparatively high; 
       FIG. 17  is a figure showing the various driving pulses applied to the PDP  10 , and the application timing; 
       FIG. 18  is a figure showing the data conversion table used in the second data conversion circuit  35 , and another example of an emission driving pattern; 
       FIG. 19  is a figure showing another example of an emission driving format (based on the selective erasing address method) during the second emission driving; 
       FIG. 20  is a figure showing the data conversion table used in the second data conversion circuit  35 , and another example of an emission driving pattern; 
       FIG. 21  is a figure showing an example of an emission driving format (based on the selected writing address method) during the first emission driving; 
       FIG. 22  is a figure showing another example of an emission driving format (based on the selected writing address method) during the second emission driving; 
       FIG. 23  is a figure showing the data conversion table used in the second data conversion circuit  34  when performing the first emission driving based on the emission driving format shown in  FIG. 21 , and the emission driving pattern; 
       FIG. 24  is a figure showing the data conversion table used in the second data conversion circuit  35  when performing the second emission driving based on the emission driving format shown in  FIG. 22 , and the emission driving pattern; 
       FIG. 25  is a figure showing a modified example of the emission driving format shown in  FIG. 16 ; 
       FIG. 26  is a figure showing the data conversion table used in the second data conversion circuit  35  when performing driving based on the emission driving format shown in  FIG. 25 , and the emission driving pattern; 
       FIG. 27  is a figure showing a modified example of the emission driving format shown in  FIG. 22 ; 
       FIG. 28  is a figure showing the data conversion table used by the second data conversion circuit  35  when performing driving based on the emission driving format shown in  FIG. 27 , and the emission driving pattern; 
       FIG. 29  is a figure showing an example of the emission driving pattern adopted when one field is divided into  13  subfields, and grayscale driving is executed based on the selective erasing address method; and, 
       FIG. 30  is a figure showing an example of the emission driving pattern adopted when one field is divided into  13  subfields, and grayscale driving is executed based on the selected writing address method. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Below, embodiments of this invention are explained, referring to the drawings. 
     FIG. 4  is a figure showing the configuration of a plasma display device which drives a plasma display panel according to a driving method of this invention. 
   As shown in  FIG. 4 , this plasma display device comprises a plasma display panel PDP  10 , and driving circuitry, comprising functional modules as described below. As shown in  FIG. 4 , the driving circuitry comprises a synchronization detection circuit  1 ; driving control circuit  2 ; vertical sync frequency detection circuit  3 ; A/D converter  4 ; memory  5 ; address driver  6 ; first sustaining driver  7 ; second sustaining driver  8 ; data conversion circuit  30 ; and mean brightness detection circuit  40 . 
   The PDP  10  comprises m column electrodes D 1  to D m  as address electrodes, and n each row electrodes X 1  to X n  and Y 1  to Y n  arranged to intersect each of the column electrodes. Here, row electrodes corresponding to one row in the PDP  10  are formed by one pair of the row electrodes X and Y. The column electrodes D and the row electrodes X and Y are formed on two glass substrates, arranged in opposition and enclosing a discharge space into which is injected a discharge gas. Discharge cells, serving as display elements corresponding to individual pixels, are formed at the portions of intersection of each of the row electrode pairs with the column electrodes. 
   When the synchronization detection circuit  1  detects a vertical sync signal in the input image signal, it generates a vertical synchronization detection signal V and supplies this signal to the driving control circuit  2  and the vertical sync frequency detection circuit  3 . Also, when the synchronization detection circuit  1  detects a horizontal sync signal in the above input image signal, it generates a horizontal synchronization detection signal H and supplies this signal to the driving control circuit  2 . The vertical sync frequency detection circuit  3  measures the period of the above vertical synchronization detection signal V, and by this means determines the vertical sync frequency in the above input image signal, and supplies to the driving control circuit  2  and data conversion circuit  30  a vertical sync frequency signal VG which indicates this frequency value. The A/D converter  4  samples the above input image signal, according to a clock signal provided by the driving control circuit  2 , and converts this into pixel data D with, for example, 8 bits per pixel; this is supplied to the data conversion circuit  30  and the mean brightness detection circuit  40 . 
   The mean brightness detection circuit  40  determines the mean brightness level of the input image signal based on the above pixel data D, supplied in order by the A/D converter  4 , and supplies a mean brightness signal AB indicating this mean brightness level to the driving control circuit  2 . 
   The data conversion circuit  30  executes multi-grayscale processing on the above pixel data D, and within one field interval, converts the results into pixel driving data GD to drive the emission of individual discharge cells. 
     FIG. 5  is a figure showing the internal configuration of the data conversion circuit  30 . 
   In  FIG. 5 , the first data conversion circuit  32  provides the results of conversion of the above pixel data D into (14×16)/255, based on conversion characteristics as shown in  FIG. 6 , to the multi-grayscale processing circuit  33  as converted pixel data D H . That is, the first data conversion circuit  32  converts pixel data D, capable of representing the brightnesses of 256 grayscales from 0 to 255 in 8 bits, into converted pixel data D H  capable of representing the brightnesses of 225 grayscales from 0 to 224 in 8 bits. Specifically, the first data conversion circuit  32  converts the above pixel data D into converted pixel data D H , based on the conversion tables in  FIG. 7  and  FIG. 8 , which conform to the conversion characteristic shown in  FIG. 6 . The conversion characteristic is set according to the number of bits of the pixel data, the number of compressed bits resulting from conversion to multiple grayscales, described below, and the number of display grayscales. In this way, before executing the multi-grayscale processing described below, conversion is performed by the first data conversion circuit  32 , taking into account the number of display grayscales and the number of compressed bits resulting from multi-grayscale processing. As a result of this data conversion, the occurrence of brightness saturation in the multi-grayscale processing described below, and the occurrence of flat portions in the display characteristic (that is, the occurrence of grayscale distortion) arising when there are no display grayscales at bit boundaries, are prevented. 
     FIG. 9  is a figure showing the internal configuration of the multi-graycale processing circuit  33 , which executes multi-grayscale processing. 
   As shown in  FIG. 9 , the multi-grayscale processing circuit  33  comprises an error diffusion processing circuit  330  and dither processing circuit  350 . 
   The data separation circuit  331  in the error diffusion processing circuit  330  separates the lower 2 bits of the 8 bits of converted pixel data D H  provided by the above first data conversion circuit  32  as error data, and the upper 6 bits as display data. The adder  332  adds this error data, delay output from the delay circuit  334 , and multiplication output from the coefficient multiplier  335 , and provides the result of addition to the delay circuit  336 . The delay circuit  336  supplies the addition result from the adder  332 , delayed by the time duration of one clock period of pixel data (hereafter called delay time D), to the above coefficient multiplier  335  and delay circuit  337  as the delayed addition signal AD 1 . The coefficient multiplier  335  supplies to the above adder  332  the result of multiplying the above delayed addition signal AD 1  by a prescribed coefficient K 1  (for example “ 7/16”). The delay circuit  337  supplies to the delay circuit  338  the above delayed addition signal AD 1 , further delayed by an amount of time (1 horizontal scan interval−above delay time D×4), as the delayed addition signal AD 2 . The delay circuit  338  supplies to the coefficient multiplier  339  this delayed addition signal AD 2 , further delayed by the above delay time D, as the delayed addition signal AD 3 . The delay circuit  338  also supplies to the coefficient multiplier  340  the above delayed addition signal AD 2 , delayed by an amount of time (delay time D×2), as the delayed addition signal AD 4 . Besides, the delay circuit  338  supplies to the coefficient multiplier  341  the above delayed addition signal AD 2 , delayed by an amount of time (delay time D×3), as the delayed addition signal AD 5 . The coefficient multiplier  339  supplies to the adder  342  the result of multi plying the above delayed addition signal AD 3  by a prescribed coefficient K 2  (for example, “ 3/16”). The coefficient multiplier  340  supplies to the adder  342  the result of multiplying the above delayed addition signal AD 4  by a prescribed coefficient K 3  (for example, “ 5/16”). The coefficient multiplier  341  supplies to the adder  342  the result of multiplying the above delayed addition signal AD 5  by a prescribed coefficient K 4  (for example, “ 1/16”). The adder  342  supplies to the above delay circuit  334  the addition signal obtained by adding the multiplication results supplied by the above coefficient multipliers  339 ,  340  and  341 . The delay circuit  334  supplies the addition signal, delayed by an amount of time equal to the above delay time D, to the above adder  332 . The adder  332  supplies to the adder  333  the above error data, the delayed output from the delay circuit  334 , and a carry-out signal C o  which is at logical level “0” if there is no carry digit when adding with the multiplication output of the coefficient multiplier  335 , and is at logical level “1” if there is a carry digit. The adder  333  outputs the result of addition of the above carryout signal C o  to the display data which is the upper 6 bits of the above converted pixel data D H  as 6 bits of error diffusion processed pixel data ED. 
   Below, operation of an error diffusion processing circuit  330  with the configuration described is explained. 
   For example, when determining the error diffusion processed pixel data ED corresponding to the pixel G(j,k) of the PDP  10 , as shown in  FIG. 10 , first, prescribed coefficients K 1  to K 4  as described above are used to weight by addition the error data corresponding to the pixel G(j,k−1) on the left of the pixel G(j,k) in question; the pixel G(j−1,k−1) on the upper left; the pixel G(j−1,k) directly above; and the pixel G(j−1,k+1) on the upper right, as follows: 
   Error data corresponding to pixel G(j,k−1): Delayed addition signal AD 1    
   Error data corresponding to pixel G(j−1,k+1): Delayed addition signal AD 3    
   Error data corresponding to pixel G(j−1,k): Delayed addition signal AD 4    
   Error data corresponding to pixel G(j−1,k−1): Delayed addition signal AD 5    
   Next, to these addition results are added the lower 2 bits of the converted pixel data HD P , that is, the error data corresponding to the pixel G(j,k); the 1-bit carry-out signal C o  obtained in this operation added to the upper 6 bits of converted pixel data D H  that is, the display data corresponding to the pixel G(j,k), is then taken to be the error diffusion processed pixel data ED. 
   By means of this configuration, in the error diffusion processing circuit  330 , the upper 6 bits of the converted pixel data D H  is taken to be the display data and the remaining lower 2 bits to be the error data, and the weighted error data for each of the peripheral pixels {G(j,k−1), G(j−1,k+1), G(j−1,k), G(j−1,k−1)} is reflected in the above display data. Through this operation, the brightness of the lower 2 bits at the origin pixel {G(j,k)} is approximately represented by the above peripheral pixels, and consequently, 6 bits&#39; worth of display data, fewer than 8 bits&#39; worth, can be used to represent brightness grayscales equivalent to 8 bits&#39; worth of pixel data. 
   If the coefficients of this error diffusion are added uniformly for each pixel, in some cases noise due to error diffusion patterns may be perceived visually, so that image quality will be degraded. Hence the error diffusion coefficients K 1  to K 4  to be allocated to each of the four peripheral pixels may be changed for each field. 
   The dither processing circuit  350  performs dither processing of error diffusion processed pixel data ED supplied by the error diffusion processing circuit  330 . In this dither processing, one intermediate display level is represented by a plurality of neighboring pixels. For example, when the upper 6 bits of pixel data among 8 bits of pixel data are used for grayscale representation equivalent to 8 bits, the four pixels adjacent on the left and right, and above and below, are taken to be one set, and four dither coefficients a to d, which are different coefficient values, are allocated and added to each of the pixel data values corresponding to each of the pixels of this set. Through this dither processing, four pixels can produce combinations of four different intermediate display levels. Hence even if there are only 6 bits of pixel data, the number of levels of brightness grayscales which can be represented is increased fourfold, that is, intermediate grayscales equivalent to 8 bits can be displayed. 
   However, if a dither pattern with dither coefficients a through d is added uniformly to each pixel, there are cases in which noise due to this dither pattern is perceived visually, and the image quality is degraded. 
   Hence in the dither processing circuit  350 , the dither coefficients a to d to be allocated to each of the four pixels are changed for each field. 
     FIG. 11  is a figure showing the internal configuration of the dither processing circuit  350 . 
   In  FIG. 11 , the dither coefficient generation circuit  352  generates four dither coefficients a, b, c, d for each of four adjacent pixels [G(j,k), G(j,k+1), G(j+1,k), G(j+1,k+1)] as shown in  FIG. 12 , and supplies these in order to the adder  351 . Further, the dither coefficient generation circuit  352  changes, for each field, the allocation of the dither coefficients a through d generated corresponding to each of the four pixels, as shown in  FIG. 12 . 
   In other words, dither coefficients a through d are generated in cyclic repetition and supplied to the adder  351 , with the following allocations. 
   In the first field, 
   pixel G(j,k): dither coefficient a 
   pixel G(j,k+1): dither coefficient b 
   pixel G(j+1,k): dither coefficient c 
   pixel G(j+1,k+1): dither coefficient d 
   In the second field, 
   pixel G(j,k): dither coefficient b 
   pixel G(j,k+1): dither coefficient a 
   pixel G(j+1,k): dither coefficient d 
   pixel G(j+1,k+1): dither coefficient c 
   In the third field, 
   pixel G(j,k): dither coefficient d 
   pixel G(j,k+1): dither coefficient c 
   pixel G(j+1,k): dither coefficient b 
   pixel G(j+b  1 ,k+1): dither coefficient a 
   And in the fourth field, 
   pixel G(j,k): dither coefficient c 
   pixel G(j,k+1): dither coefficient d 
   pixel G(j+1,k): dither coefficient a 
   pixel G(j+1,k+1): dither coefficient b 
   The dither coefficient generation circuit  352  repeatedly executes the operation for the first through fourth fields as described above. That is, after completing the operation to generate dither coefficients in the fourth field, the circuit returns to the operation for the above first field, and repeats the operation described above. 
   The adder  351  adds the dither coefficients a through d allocated for each field as described above to the error diffusion processed pixel data ED corresponding to the above pixel G(j,k), pixel G(j,k+1), pixel G(j+1,k), and pixel G(j+1,k+1), su plied from the above error diffusion processing circuit  330 . The dither added pixel data obtained is supplied to the upper bit extraction circuit  353 . 
   For example, in the first field shown in  FIG. 12 , the following are supplied in order as dither added pixel data to the upper bit extraction circuit  353 : 
   Error diffusion processed pixel data ED corresponding to the pixel G(j,k)+dither coefficient a, 
   Error diffusion processed pixel data ED corresponding to the pixel G( j,k+1)+dither coefficient b, 
   Error diffusion processed pixel data ED corresponding to the pixel G(j+1,k)+dither coefficient c, and Error diffusion processed pixel data ED corresponding to the pixel G(j+1,k+1)+dither coefficient d. 
   In this process, when a plurality of pixels are viewed as a single pixel unit, as shown in  FIG. 10 , through addition of the above dither coefficients, brightness equivalent to 8 bits can be rep resented even with only the upper 4 bits of the above dither added pixel data. Hence the upper bit extraction circuit  353  of the next stage extracts the upper 4 bits of the dither added pixel data, and these are supplied to the second data conversion circuits  34  and  35  shown in  FIG. 5  as multi-grayscale pixel data D S . 
   The second data conversion circuit  34  converts the multi-grayscale pixel data D S  into 14-bit pixel driving data GD a  according to the data conversion table shown in  FIG. 13 , and supplies this to the selector  36 . 
   On the other hand, the second data conversion circuit  35  converts the above multi-grayscale pixel data D S  into 14-bit pixel driving data GD b  according to the data conversion table shown in  FIG. 14 , and supplies the result to the selector  36 . When a flicker suppression signal FS at logical level “0” is supplied from the driving control circuit  2 , the selector  36  selects GD a  from among the above pixel driving data GD a  and GD b  for use as pixel driving data GD, and supplies this to the memory  5  shown in  FIG. 4 . On the other hand, when a flicker suppression signal FS with logical level “1” is supplied, the selector  36  selects the above pixel driving data GD b , and supplies this to the memory  5  as pixel driving data GD. 
   The memory  5  writes in order this pixel driving data GD, according to write signals supplied from the driving control circuit  2 . When, by means of this write operation, one screen&#39;s worth (n rows, m columns) of writing is completed, the memory  5  reads out the written data according to read signals supplied from the driving control circuit  2 . That is, in the memory  5 , one screen&#39;s worth of the written pixel driving data GD 11  to GD nm  is taken to be pixel driving data bit groups DB 1  to DB 14 , grouped by the bit digit (from the first to the 14th bit). 
   The pixel driving data bit groups DB 1  to DB 14  are as follows. 
   DB 1 : 1st bit of each of GD 11  to GD nm    
   DB 2 : 2nd bit of each of GD 11  to GD nm    
   DB 3 : 3rd bit of each of GD 11  to GD nm    
   DB 4 : 4th bit of each of GD 11  to GD nm    
   DB 5 : 5th it of each of GD 11  to GD nm    
   DB 6 : 6th bit of each of GD 11  to GD nm    
   DB 7 : 7th bit of each of GD 11  to GD nm    
   DB 8 : 8th bit of each of GD 11  to GD nm    
   DB 9 : 9th bit of each of GD 11  to GD nm    
   DB 10 : 10th bit of each of GD 11  to GD nm    
   DB 11 : 11th bit of each of GD 11  to GD nm    
   DB 12 : 12th bit of each of GD 11  to GD nm    
   DB 13 : 13th bit of each of GD 11  to GD nm    
   DB 14 : 14th bit of each of GD 11  to GD nm    
   The memory  5  reads out in order, one display line at a time, each of these pixel driving data bit groups DB 1  to DB 14 , corresponding to each of the subfields SF 1  to SF 14  described below. 
   The driving control circuit  2  executes emission driving control as follows, according to the above vertical sync frequency signal VF and mean brightness signal AB. 
   When the vertical sync frequency indicated by the above vertical sync frequency signal VF is equal to or greater than, for example, 60 Hz, or when the mean brightness level indicated by the mean brightness signal AB is lower than a prescribed level, the driving control circuit  2  first supplies a logical level “0” flicker suppression signal FS to the data conversion circuit  30 . In this process, the selector  36  of the data conversion circuit  30  supplies pixel driving data GD a , converted by the second data conversion circuit  34 , to memory  5  in response to this logical level “0”. flicker suppression signal FS. The driving control circuit  2  then supplies, to the address driver  6 , first sustaining driver  7  and second sustaining driver  8 , various timing signals so as to cause emission driving of the PDP  10  according to the emission driving format shown in  FIG. 15 . 
   That is, w hen the brightness level of the input image signal is low, or when for example an NTSC format television signal or other signal with vertical sync frequency at 60 Hz or higher is supplied as the input image signal, emission driving is executed as shown in  FIG. 13  and  FIG. 15 . 
   On the other hand, when the vertical sync frequency indicated by the above vertical sync frequency signal VF is less than 60 Hz, and in addition the mean brightness level indicated by the mean brightness signal AB is higher than a prescribed level, the driving control circuit  2  first supplies a logical level “1” flicker suppression signal FS to the data conversion circuit  30 . In this process, the selector  36  of the data conversion circuit  30  supplies to the memory  5  pixel driving data GD b  converted by the second data conversion circuit  35  in response to this logical level “1” flicker suppression signal FS. The driving control circuit  2  then supplies, to the address driver  6 , first sustaining driver  7  and second sustaining driver  8 , various timing signals so as to cause emission driving of the PDP  10 , according to the emission driving format shown in  FIG. 16 . 
   In other words, if as the input image signal a PAL format television signal or other signal with a vertical sync frequency less than 60 Hz is supplied, and in addition the mean brightness is high, then emission driving is executed as shown in  FIG. 14  and  FIG. 16 . 
   In the emission driving format shown in  FIG. 15  and  FIG. 16 , the display interval of one field (hereafter this expression also refers to one frame) is divided into 14 subfields SF 1  to SF 14 . Within each subfield, executed are an address sequence Wc, in which each of the discharge cells of the PDP  10  is set to either the “lit discharge cell state” or the “extinguish discharge cell state”, and an emission sustain sequence Ic which causes only discharge cells in the above “lit discharge cell state” to emit repeatedly the number of times indicated in  FIG. 15  (or in  FIG. 16 ). Also, in the leading subfield SF 1 , a simultaneous reset sequence Rc is executed which initializes the wall charge within all the discharge cells of the PDP  10 ; and in the final subfield SF 14 , an erasing sequence E is executed which simultaneously eliminates the wall charge within all the discharge cells. 
   In the emission driving format shown in  FIG. 16 , the emission driving in the subfields SF 1 , SF 3 , SF 5 , SF 7 , SF 9 , SF 11 , SF 13  in the emission driving format of  FIG. 15  is executed in the first half of the one-field display interval, and the emission driving in the subfields SF 2 , SF 4 , SF 6 , SF 8 , SF 10 , SF 12 , SF 14  is executed in the second half. Here, the above erasing sequence E is executed in the final subfield SF 13  of the first half, and the above simultaneous reset sequence Rc is executed in the leading subfield SF 2  of the second half. 
   The address driver  6 , first sustaining driver  7  and second sustaining driver  8  apply various driving pulses in order to realize the operations of each of the above sequences to the electrodes of the PDP  10 , with timing determined by the timing signals supplied by the driving control circuit  2 . 
     FIG. 17  shows the timing of the application of various driving pulses applied to the column electrodes D and the row electrodes X and Y of the PDP  10  by the above drivers, during the above simultaneous reset sequence Rc, address sequence Wc, emission sustain sequence Ic, and erasing sequence E. 
   First, in the above simultaneous reset sequence Rc, the first sustaining driver  7  and second sustaining driver  8  each simultaneously apply reset pulses RP X  and RP Y  to the row electrodes X 1  to X n  and Y 1  to Y n , as shown in  FIG. 17 . In response to the application of these reset pulses RP X  and RP Y , all the discharge cells in the PDP  10  undergo reset discharge, and a prescribed uniform wall charge is formed within each of the discharge cells. By this means, all the discharge cells are set to the initial “lit discharge cell state”. 
   Next, in the address sequence Wc, the address driver  6  generates pixel data pulses having voltages corresponding to the logical levels of each pixel driving data bit in the pixel driving data bit group DB read from the above memory  5 . For example, the address driver  6  generates a high-voltage pixel data pulse when the logical level of the pixel driving data bit is “1”, and generates a low-voltage (0 volt) pixel data pulse when it is “0”. The address driver  6  applies these pixel data pulses, one display line (m pulses) at a time, to the column electrodes D 1  to D m . For example, in the address sequence Wc of the subfield SF 1 , the pixel driving data bit group DB 1  is read from memory  5 , as described above. In this process, the address driver  6  first converts m pixel driving data bits corresponding to the first display line in the pixel driving data bit group DB 1  into m pixel data pulses having pulse voltages corresponding to the respective logical levels, and applies these to the column electrodes D 1  to D m  as the pixel data pulses group DP 1 . Next, the address driver  6  converts the m pixel driving data bits corresponding to the second display line in the pixel driving data bit group DB 1  into m pixel data pulses having pulse voltages which correspond to the respective logical levels, and apply these to the column electrodes D 1  to D m  as the pixel data pulse group DP 2 . Subsequently, similar operations are performed in the address sequence Wc of the subfield SF 1  to apply pixel data pulse groups DP 3  to DPn, corresponding to the 3rd through nth display lines of the pixel data pulse group DP 1 , in order to the column electrodes D 1  to D m , In the address sequence Wc of the subfield SF 2 , the pixel driving data bit group DB 2  is read from memory  5 , as described above. Here, the address driver  6  converts the m pixel driving data bits corresponding to the first display line in the pixel driving data bt group DB 2  into m pixel data pulses having pulse voltages corresponding to the respective logical levels, and applies these to the column electrodes D 1  to D m  as the pixel data pulse group DP 1 . Then the address driver  6  converts the m pixel driving data bits corresponding to the second display line in the pixel driving data bit group DB 2  into m pixel data pulses having pulse voltages which correspond to the respective logical levels, and applies these to the column electrodes D 1  to D m  as the pixel data pulse group DP 2 . Subsequently, similar operations are performed in the address sequence Wc of the subfield SF 2  to apply pixel data pulse groups DP 3  to DPn, corresponding to the 3rd through nth display lines of the pixel data pulse group DP 2 , in order to the column electrodes D 1  to D m . 
   Further, in each address sequence Wc the second sustaining driver  8  generates negative-polarity scan pulses SP as shown in  FIG. 17 , with the same timing as the timing of application of the above-described pixel data pulse groups DP, and applies these in order to the row electrodes Y 1  to Y n . In this process, discharge (selective erasing discharge) occurs only in discharge cells at the intersections of row electrodes Y to which a scan pulse SP is applied, and column electrodes D to which a high-voltage pixel data pulse is applied; the wall charge which had remained within the discharge cells is then selectively eliminated. Discharge cells which have been initialized by this selective erasing discharge to the “lit discharge cell state” in the above simultaneous reset sequence Rc are set to the “extinguished discharge cell state”. On the other hand, discharge is not induced in discharge cells belonging to column electrodes D to which a low-voltage pixel data pulse is applied, and the current state is maintained. That is, discharge cells in the “extinguished discharge cell state” remain in the “extinguished discharge cell state”, and discharge cells in the “lit discharge cell state” are maintained in the “lit discharge cell state”. 
   Next, in the emission sustain sequence Ic for each subfield, positive-polarity sustain pulses IP X  and IP Y  are applied repeatedly in alternation to the row electrodes X 1  to X n  and Y 1  to Y n  by the first sustaining driver  7  and second sustaining driver  8 , as shown in  FIG. 17 . As shown in  FIGS. 15 and 16 , in the emission sustain sequence Ic for each of the subfields SF 1  to SF 14 , the number of times that the above sustain pulse IP is applied repeatedly is, if the number of times in SF 1  is “1”: 
   SF 1 : 1 
   SF 2 : 3 
   SF 3 : 5 
   SF 4 : 8 
   SF 5 : 10 
   SF 6 : 13 
   SF 7 : 16 
   SF 8 : 19 
   SF 9 : 22 
   SF 10 : 25 
   SF 11 : 28 
   SF 12 : 32 
   SF 13 : 35 
   SF 14 : 39 
   Here, only discharge cells in which wall charge is formed, that is, only discharge cells in the “lit discharge cell state”, undergo discharge each time these sustain pulses IP X  and IP Y  are applied (sustaining discharge), and sustain the emission state accompanying this discharge. The longer the time over which the emission state is sustained, the brighter the emitted light as perceived by the human eye. 
   In the era sing sequence E, the second sustaining driver  8  generates negative-polarity erasing pulses EP and applies them to the row electrodes Y 1  through Y n , as shown in  FIG. 17 . Through application of these erasing pulses EP, an erasing discharge is induced within all the discharge cells of the PDP  10 , and the wall charge remaining within all the discharge cells is annihilated. That is, by means of this erasing discharge, all the discharge cells in the PDP  10  are forcibly set to the “extinguished discharge cell state”. 
   Through the driving described above, only those discharge cells set in the “lit discharge cell state” during the address sequence Wc within each subfield undergo emission a number of times corresponding to subfield weighting for each subfield, as described above. 
   In this process, whether each discharge cell is set to the “lit discharge cell state” or to the “extinguished discharge cell state” is determined by the pixel driving data GD a  or GD b  shown in  FIG. 13  or  FIG. 14 . That is, if a bit in the pixel driving data GD is at logical level “1”, selective erasing discharge is induced in the address sequence Wc of the subfield corresponding to the bit digit, and the discharge cell is put into the “extinguished discharge cell state”. On the other hand, if a bit in the pixel driving data GD is at logical level “0”, then the above selective erasing discharge is not induced in the address sequence Wc of the subfield corresponding to the bit digit. Hence discharge cells in the “extinguished discharge cell state” remain in the “extinguished discharge cell state”, and discharge cells in the “lit discharge cell state” are maintained in the “lit discharge cell state”. 
   In the pixel driving data GD a  shown in  FIG. 13 , each of the first through 14th bits determines whether or not selective erasing discharge is induced in the address sequence Wc for the respective subfields SF 1  to SF 14  in  FIG. 15 . Hence when the pixel driving data GD a  shown in  FIG. 13  is used to perform driving according to the emission driving format of  FIG. 15 , first all the discharge cells are initialized to the “lit discharge cell state” in subfield SF 1 . The “lit discharge cell state” of discharge cells is maintained until a selective erasing discharge is induced by the address sequence Wc in the subfields indicated by black circles in  FIG. 13 . Hence in the emission sustain sequences Ic in each of the subfields (indicated by white circles) existing while the above “lit discharge cell state” is maintained, sustaining discharge emission is executed a number of times corresponding to the weighting for that subfield. As a result, an intermediate brightness is perceived according to the total number of sustaining discharge emissions induced in the emission sustain sequence Ic for each subfield during the interval for one field. 
   Consequently if the pixel driving data GD a  having the 15 patterns shown in  FIG. 13  is used to perform driving according to the emission driving format shown in  FIG. 15 , then intermediate-level brightnesses in 15 stages can be expressed, as follows:
 
{0:1:4:9:17:27:40:56:75:97:122:150:182:217:255}
 
   By means of grayscale driving in these 15 stages, and multi-grayscale processing by the multi-grayscale processing circuit  33  as described above, intermediate brightnesses which are visually equivalent to 256 grayscales can be expressed. 
   On the other hand, in the pixel driving data GD b  shown in  FIG. 14 , the first through 14th bits correspond to the subfields SF 1  to SF 14  in  FIG. 16  as follows. 
   GD b  1st bit: SF 1   
   GD b  2nd bit: SF 3   
   GD b  3rd bit: SF 5   
   GD b  4th bit: SF 7   
   GD b  5th bit: SF 9   
   GD b  6th bit: SF 11   
   GD b  7th bit: SF 13   
   GD b  8th bit: SF 2   
   GD b  9th bit: SF 4   
   GD b  10th bit: SF 6   
   GD b  11th bit: SF 8   
   GD b  12th bit: SF 10   
   GD b  13th bit: SF 12   
   GD b  14th bit: SF 14   
   Further, in the emission driving format shown in  FIG. 16 , the simultaneous reset sequence Rc is executed in subfield SF 2  as well as in subfield SF 1 . 
   Hence if driving is performed using the pixel driving data GD shown i  FIG. 14  according to the emission driving format of  FIG. 16 , all discharge cells are initialized to the “lit discharge cell state” in the subfields SF 1  and SF 2 . This “lit discharge cell state” is maintained until selective erasing discharge is induced in the address sequence Wc for subfields, indicated by the black circles in  FIG. 14 . In this process, sustaining discharge emission is executed repeatedly a number of times corresponding to the weighting for the subfield during the emission sustain sequences Ic for subfields (indicated by white circles) while the above “lit discharge cell state” is maintained. When selective erasing discharge is induced in the address sequence Wc for a subfield indicated by a black circle in  FIG. 14 , each of the discharge cell makes a transition to the “extinguished discharge cell state”. In this process, an intermediate brightness is perceived corresponding to the total number of sustaining discharge emissions induced in the emission sustain sequence Ic for each subfield within one field interval. 
   Hence if, as shown in  FIG. 14 , the  15  patterns of pixel driving data GD b  are used to perform driving according to the emission driving format shown in  FIG. 16 , similarly to the driving shown in  FIGS. 13 and 15  and described above, it is possible to express intermediate-level brightnesses in 15 stages:
 
{0:1:4:9:17:27:40:56:75:97:122:150:182:217:255}
 
   In the driving shown in  FIGS. 13 and 15  (hereafter called the first emission driving), reset discharge is induced to form wall charge within all discharge cells only in the leading subfield of one field. Then, selective erasing discharge is induced one time at most within the display interval for one field, to selectively eliminate the wall charge formed within each discharge cell. By this means, the number of times there is a switch from the continuous emission state, in which subfields in which sustaining discharge emission is performed are continuous (shown by white circles in  FIG. 13 ), to the continuous extinguished state, in which subfields in the extinguished state are continuous, is at most one time. Hence as shown in  FIG. 13 , there are no emission driving patterns among the 15 emission driving patterns in which intervals of the continuous emission state and intervals of the continuous extinguished state are inverted within one field display interval. Consequently within one screen, when there are two adjacent screen regions in which the continuous emission state interval and the continuous extinguished state interval are inverted, the occurrence of the false contours which are thought to occur at such boundaries is suppressed. Also, in the above first emission driving, reset discharge, which requires a comparatively large amount of power, is executed only once at the beginning of a field, so that power consumption is suppressed. 
   On the other hand, in driving as shown in  FIGS. 14 and 16  (hereafter called the second emission driving), grayscale driving is adopted in which the display interval for one field is divided into first-half driving intervals (SF 1 , SF 3 , SF 5 , SF 7 , SF 9 , SF 11 , SF 13 ) and second-half driving intervals (SF 2 , SF 4 , SF 6 , SF 8 , SF 10 , SF 12 , SF 14 ). As indicated by the white circles in  FIG. 14 , in the driving intervals of the first half, emission is executed continuously from the beginning over a time period corresponding to the brightness level of the input image signal. In driving intervals of the second half, emission is executed continuously from the beginning over a time period corresponding to the brightness level of the input image signal. Thus as shown in  FIG. 14 , among the 15 emission driving patterns, there exist no emission driving patterns in which the interval of the continuous emission state and the interval of the continued extinguished state are inverted within one field display interval. Consequently within one screen, when two screen regions in which the continuous emission state interval and the continuous extinguished state interval are mutually inverted, the false contours which are said to occur at the boundary are suppressed. Also, by means of the above second emission driving, switching from the continuous emission state wherein subfields in which sustaining discharge emission is induced are continuous, to the continuous extinguished state wherein subfields in the extinguished state are continuous, occurs at most two times within one field interval. That is, the time between the moment of initiation of emission in the above first-half driving interval, and the moment of initiation of emission in the second-half driving interval, is approximately ½ the display interval for one field, and the frequency of switching between the above continuous emission state and the above continuous extinguished state is approximately 2 times the vertical sync frequency which determines the display interval for one field. As a result, even if a PAL format television signal with a vertical sync frequency of 50 Hz is supplied as the input image signal, and the mean brightness expressed by the PAL format television signal is comparatively high, a good-quality image without flicker is displayed. 
   As explained above, in this invention, when an image signal with a low mean brightness level is input, or when an image signal with a high vertical sync frequency is input, the first emission driving ( FIG. 13  and  FIG. 15 ), in which discharge cell are caused to emit in each of a number of continuous subfields corresponding to the brightness level of the input image signal within one field. By means of this first emission driving, there exist no emission driving patterns in which continuous emission intervals and continuous extinguished intervals are inverted within one field display interval, so that the occurrence of false contours is suppressed. Further, reset discharge, which incurs comparatively large power consumption, is executed only once, at the beginning of the field, so that power consumption can be suppressed. 
   On the other hand, when an image signal is input which has a high mean brightness level and also has a low vertical sync frequency, the second emission driving ( FIG. 14  and  FIG. 16 ) is executed, in which, in each of the first and second halves of one field, discharge cells are caused to emit in a number of continuous subfields corresponding to the brightness level of the input image signal. By means of this second emission discharge, there exist no emission discharge patterns within one field display interval such that continuous emission intervals and continuous extinguished intervals are inverted, so that the occurrence of false contours is suppressed. Further, by means of the second emission discharge, the number of times within one field display interval that there is switching from the continuous emission state to the continuous extinguished state is at most 2 times. Hence even when the input image signal is an image signal with a comparatively low vertical sync frequency, as in the case of PAL television signals, and moreover the brightness of the image signal is high, a good-quality image is displayed with flicker suppressed. 
   In the emission driving patterns corresponding to the first through 13th grayscales during second emission driving as shown in  FIG. 14 , selective erasing discharge is induced only one time each in the first half and in the second half of a field. However, when the amount of wall charge remaining within a discharge cell is small, even if a scan pulse SP and a high-voltage pixel data pulse are applied simultaneously, selective erasing discharge may not be induced normally. 
   Hence as the conversion table used by the second data conversion circuit  35 , that shown in  FIG. 18  may be adopted in place of the table of  FIG. 14 , in order to reliably induce this selective erasing discharge. By means of pixel driving data GD b  converted using this conversion table, selective erasing discharge is induced in each of two continuous subfields, as indicated by the black circles in  FIG. 18 . Consequently, even if the wall charge within a discharge cell cannot be properly annihilated by the first selective erasing discharge, the wall charge can be annihilated normally through the second selective erasing discharge. 
   In the emission discharge format shown in  FIG. 16 , the subfields SF 1 , SF 3 , SF 5 , SF 7 , SF 9 , SF 11 , SF 13  are executed in the first half of a field, and the subfields SF 2 , SF 4 , SF 6 , SF 8 , SF 10 , SF 12 , SF 14  are executed in the second half; but other methods are possible. 
     FIG. 19  is a figure showing a modified example of the emission driving format shown in  FIG. 16 , in consideration of this point. 
   In the emission driving format shown in  FIG. 19 , the subfields SF 1 , SF 4 , SF 5 , SF 8 , SF 9 , SF 12 , SF 13  are executed in order in the first half of a field, and in the second half, SF 2 , SF 3 , SF 6 , SF 7 , SF 10 , SF 11 , SF 14  are executed in order. 
     FIG. 20  is a figure showing the data conversion table used in the second data conversion circuit  34  when executing emission driving control adopting the emission driving format shown in  FIG. 19 , and an emission driving pattern. 
   Here, the first through 14th bits of the pixel driving data GD b  shown in  FIG. 20  are associated with the subfields SF 1  to SF 14  shown in  FIG. 19  as follows. 
   GD b  1st bit: SF 1   
   GD b  2nd bit: SF 4   
   GD b  3rd bit: SF 5   
   GD b  4th bit: SF 8   
   GD b  5th bit: SF 9   
   GD b  6th bit: SF 12   
   GD b  7th bit: SF 13   
   GD b  8th bit: SF 2   
   GD b  9th bit: SF 3   
   GD b  10th bit: SF 6   
   GD b  11th bit: SF 7   
   GD b  12th bit: SF 10   
   GD b  13th bit: SF 11   
   GD b  14th bit: SF 14   
   In the above embodiment, as the pixel data writing method, the so-called selective erasing address method was adopted in which all the discharge cells are initialized to the “lit discharge cell state” in advance, and the wall charge is eliminated selectively according to the pixel data to set the “extinguished discharge cell state”. 
   However, it is possible to similarly apply this invention to the case in which the so-called selected writing address method is adopted as the pixel data writing method, in which the wall charge remaining in each discharge cell is annihilated, so that all discharge cells are initialized to the “extinguished discharge cell state”, and wall charge is then formed selectively according to the pixel data. 
     FIG. 21  is a figure showing an emission driving format during the first emission driving, used when adopting this selected writing address method, and  FIG. 22  shows an emission driving format during the second emission driving.  FIG. 23  is a figure showing the data conversion table used in the second date conversion circuit  34  when adopting the emission driving format shown in  FIG. 21 , and the emission driving pattern. Further,  FIG. 24  shows the data conversion table used by the second data conversion circuit  35  when adopting the emission driving format shown in  FIG. 22 , and the emission driving pattern. 
   In the emission driving format used in the first emission driving shown in  FIG. 21 , as opposed to the emission driving format shown in  FIG. 15 , grayscale driving is executed in order from subfield SF 14  to SF 1 . A simultaneous reset sequence Rc′, in which the wall charge remaining in all discharge cells is eliminated simultaneously to initialize all discharge cells to the “extinguished discharge cell state”, is executed only in the leading subfield SF 14 . Further, in each subfield an address sequence Wc′ and an emission sustain sequence Ic are executed. Here, selected write discharge to form wall charge is induced only in the address sequences Wc′ of subfields (indicated by black circles) corresponding to the digits of bits with a logical level “1” in the pixel driving data GD shown in  FIG. 23 . Discharge cells in which this selected writing discharge is induced are set to the “lit discharge cell state”. Hence emission is executed in the emission sustain sequences Ic for subfields indicated by black or white circles in  FIG. 23  only a number of times corresponding to the weighting of each subfield. In the first emission driving shown in  FIG. 21  and  FIG. 23 , the number of switches from the continuous emission state, in which subfields of sustaining discharge emission (indicated by black or white circles in  FIG. 23 ) are continuous, to the continuous extinguished state in which subfields in the extinguished state are continuous, is at most one. Hence among the 15 different emission driving patterns shown in  FIG. 23 , there exist no emission driving patterns in which the continuous emission state interval and the continuous extinguished state interval are inverted within the display interval for one field. Therefore when there are two adjacent screen regions within a screen such that the continuous emission state interval and the continuous extinguished state interval are mutually inverted, the occurrence of so-called false contours at the boundary between the regions is suppressed. Further, reset discharge, which has comparatively high power consumption, is executed only once at the beginning of the field even in the first emission driving shown in  FIGS. 21 and 23 , so that power consumption is suppressed. 
   On the other hand, in the emission driving format during second emission driving shown in  FIG. 22 , the subfields SF 13 , SF 11 , SF 9 , SF 7 , SF 5 , SF 3 , SF 1  are executed in order in the first half of one field, and SF 14 , SF 12 , SF 10 , SF 8 , SF 6 , SF 4 , SF 2  are executed in order in the second half. Here the simultaneous reset sequence Rc is executed, similarly to the case described above, in the leading subfield of the first half SF 13  and in the leading subfield of the second half SF 14 . Also, within each subfield the above-described address sequence Wc′ and emission sustain sequence Ic are executed. In this process, the first through 14th bits of the pixel driving data GD b  shown in  FIG. 24  correspond to the subfields SF 1  to SF 14  in  FIG. 22  as follows. 
   GD b  1st bit: SF 13   
   GD b  2nd bit: SF 11   
   GD b  3rd bit: SF 9   
   GD b  4th bit: SF 7   
   GD b  5th bit: SF 5   
   GD b  6th bit: SF 3   
   GD b  7th bit: SF 1   
   GD b  8th bit: SF 14   
   GD b  9th bit: SF 12   
   GD b  10th bit: SF 10   
   GD b  11th bit: SF 8   
   GD b  12th bit: SF 6   
   GD b  13th bit: SF 4   
   GD b  14th bit: SF 2   
   Hence emission is performed the number of times corresponding to the weighting of subfields indicated by black and white circles in  FIG. 24  only in the emission sustain sequence Ic. In this driving, switching from the continuous extinguished state to the continuous emission state is performed at most two times during the display interval for one field, similarly to the emission driving shown in  FIG. 14 . 
   When there is no cause for concern regarding flicker, because the vertical sync frequency of the input image signal is equal to or greater than a prescribed frequency (60 Hz), or because the mean brightness expressed by the input image signal is low, the driving control circuit  2  executes the first emission driving, shown in  FIGS. 21 and 23 . On the other hand, if the vertical sync frequency of the input image signal is lower than the prescribed frequency, and in addition the mean brightness is high, so that there is cause for concern regarding flicker, the second emission driving shown in  FIGS. 22 and 24  is executed, so that switching during the display interval of one field from the continuous extinguished state to the continuous emission state occurs at most two times. 
   Also, in the second emission driving of the above embodiment, odd-numbered subfields are executed in the first half of the field, and even-numbered subfields are executed in the second half; but the two may be interposed. 
     FIG. 25  is a figure showing an emission driving format in second emission driving, taking this point into consideration. 
   In the emission driving format shown in  FIG. 25 , the subfields SF 2 , SF 4 , SF 6 , SF 8 , SF 10 , SF 12 , SF 14 , having ratios of the number of emissions to be performed in each emission sustain sequence Ic equal to [3:8:13:19:25:32:39], are executed in order in the first half of the field. In the second half of the field, the subfields SF 1 , SF 3 , SF 5 , SF 7 , SF 9 , SF 11 , SF 13 , having ratios of the number of emissions to be performed in each emission sustain sequence Ic equal to [1:5:10:16:22:28:35], are executed in order. 
     FIG. 26  is a figure showing the data conversion table used in the second data conversion circuit  35  when adopting the emission driving format shown in  FIG. 25 , and the emission driving pattern. 
   Here, the first through 14th bits of the pixel driving data GD b  shown in  FIG. 26  are associated with the subfields SF 1  to SF 14  shown in  FIG. 25  as follows. 
   GD b  1st bit: SF 2   
   GD b  2nd bit: SF 4   
   GD b  3rd bit: SF 6   
   GD b  4th bit: SF 8   
   GD b  5th bit: SF 10   
   GD b  6th bit: SF 12   
   GD b  7th bit: SF 14   
   GD b  8th bit: SF 1   
   GD b  9th bit: SF 3   
   GD b  10th bit: SF 5   
   GD b  11th bit: SF 7   
   GD b  12th bit: SF 9   
   GD b  13th bit: SF 11   
   GD b  14th bit: SF 13   
   That is, in the second emission driving shown in  FIGS. 25 and 26 , the subfield series of the first half of the field in the second emission driving shown in  FIGS. 14 and 16  (SF 1 , SF 3 , SF 5 , SF 7 , SF 9 , SF 11 , SF 13 ) and the subfield series of the second half (SF 2 , SF 4 , SF 6 , SF 8 , SF 10 , SF 12 , SF 14 ) are inverted. 
   Similarly, in the second emission driving shown in  FIGS. 27 and 28 , the subfield series of the first half of the field in the second emission driving shown in  FIGS. 22 and 24  (SF 13 , SF 11 , SF 9 , SF 7 , SF 5 , SF 3 , SF 1 ) and the subfield series of the second half (SF 14 , SF 12 , SF 10 , SF 8 , SF 6 , SF 4 , SF 2 ) are inverted. 
   In the above embodiment, one field is divided into an even number (14) of subfields to perform grayscale driving of the PDP  10 ; but the number of subfields into which the field is divided is not limited to an even number. 
     FIG. 29  an d  FIG. 30  are figures showing an example of the emission driving pattern in second emission driving adopted when one field is divided into an odd number (13) of subfields to drive the PDP  10 .  FIG. 29  and  FIG. 30  show the emission driving patterns in second emission driving when adopting the selective erasing address method and the selected writing address method, respectively. 
   In the emission driving pattern shown in  FIG. 29 , subfields SF 1 , SF 3 , SF 5 , SF 7 , SF 9 , SF 11 , SF 13 , having a ratio of the number of times emission is to be executed in each emission sustain sequence Ic equal to [1:5:10:16:22:28:35], are executed in order in the first half of the field. In the second half of the field, subfields SF 2 , SF 4 , SF 6 , SF 8 , SF 10 , SF 12 , having a ratio of the number of times emission is to be executed in each emission sustain sequence Ic equal to [3:8:13:19:25:32], are executed in order. 
   In the emission driving pattern shown in  FIG. 30 , subfields SF 13  SF 11 , SF 9 , SF 7 , SF 5 , SF 3 , SF 1 , having a ratio of the number of times emission is to be executed in each emission sustain sequence Ic equal to [35:28:22:16:10:5:1], are executed in order in the first half of the field. In the second half of the field, subfields SF 12 , SF 10 , SF 8 , SF 6 , SF 4 , SF 2 , having a ratio of the number of times emission is to be executed in each emission sustain sequence Ic equal to [32:25:19:13:8:3], are executed in order. 
   As explained in detail above, in this invention, when an image signal with low mean brightness is input, or when an image signal with a high vertical sync frequency is input, emission elements comprised by pixels are caused to emit in a number of continuous subfields within one field corresponding to the brightness level expressed by the input image signal. By means of this driving, there exist no emission driving patterns in which a continuous emission interval and a continuous extinguished interval within one field are inverted, so that the occurrence of false contours is suppressed. On the other hand, when an image signal with a high mean brightness, and which has a low vertical sync frequency, is input, emission elements are caused to emit in each of a number of continuous subfields, in the first half and in the second half of a field, according to the brightness level expressed by the image signal. By means of this driving, the number of times there is switching from the continuous emission state to the continuous extinguished state within the display interval for one field is two times. Hence even if an image signal is input with a low vertical sync frequency, such as a PAL television signal, and in addition the mean brightness is high, a good-quality image is displayed, with false contours as well as flicker suppressed. 
   This application is based on Japanese Patent Application No. 2001-181109 which is herein incorporated by reference.