Patent Publication Number: US-11646704-B2

Title: Power amplifier circuit

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of U.S. patent application Ser. No. 16/382,324, filed on Apr. 12, 2019, which claims priority from Japanese Patent Application No. 2018-097267 filed on May 21, 2018. The contents of these applications are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND OF THE DISCLOSURE 
     Field of the Disclosure 
     The present disclosure relates to a power amplifier circuit. 
     Description of the Related Art 
     In mobile communication terminals, such as cellular phones, a power amplifier circuit is used that amplifies a radio frequency (RF) signal to be transmitted to a base station. The power amplifier circuit includes a transistor that amplifies the RF signal, and a bias circuit that supplies a bias current to the transistor. For example, Japanese Unexamined Patent Application Publication No. 2017-92526 discloses a bipolar transistor TrRF 1  that amplifies an input signal RFin, a bipolar transistor TrRF 2  that amplifies the amplified signal RFout 1  amplified by the bipolar transistor TrRF 1 , and a bias circuit  200 D that supplies a bias current to a base of the bipolar transistor TrRF 2 . 
     However, when the output power of a power amplifier circuit increases, a phase of an output signal varies in accordance with the transistor characteristics, and the linearity of the phase deteriorates in some cases. 
     BRIEF SUMMARY OF THE DISCLOSURE 
     The present disclosure has been made in view of such circumstances and provides a power amplifier circuit that improves the linearity of a phase of an output signal. 
     One preferred embodiment of the present disclosure is directed to a power amplifier circuit that includes a first transistor configured to amplify a first signal and output a second signal; a second transistor configured to amplify the second signal and output a third signal; a bias circuit configured to supply a bias current to a base of the second transistor; and a bias adjustment circuit configured to adjust the bias current to be supplied by the bias circuit by subjecting the first signal to detection. The bias adjustment circuit controls the bias current to be supplied to the base of the second transistor by drawing, from the bias circuit, a current of a magnitude corresponding to a magnitude of the first signal. The current increases as the magnitude of the first signal increases. 
     Preferred embodiments of the present disclosure can provide the power amplifier circuit that improves the linearity of a phase of an output signal. 
     Other features, elements, characteristics and advantages of the present disclosure will become more apparent from the following detailed description of preferred embodiments of the present disclosure with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG.  1    illustrates an overview of a configuration of a power amplifier circuit according to a first embodiment of the present disclosure; 
         FIG.  2    illustrates an example of a configuration of a power amplifier circuit according to the first embodiment of the present disclosure; 
         FIG.  3    illustrates a relationship between, in the power amplifier circuit according to the first embodiment, output power, and base voltage of a third transistor; 
         FIG.  4    illustrates a relationship between power and phase of an output signal of the power amplifier circuit according to the first embodiment; 
         FIG.  5    illustrates an example of a configuration of a modification of the power amplifier circuit according to the first embodiment of the present disclosure; 
         FIG.  6    illustrates an example of a configuration of another modification of the power amplifier circuit according to the first embodiment of the present disclosure; and 
         FIG.  7    illustrates an example of a configuration of still another modification of the power amplifier circuit according to the first embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE DISCLOSURE 
     An embodiment of the present disclosure will be described in detail below with reference to the drawings. The same elements are designated by the same reference numerals, and the repeated descriptions thereof are omitted. 
     (1) Entire Configuration 
       FIG.  1    illustrates an overview of a configuration of a power amplifier circuit according to a first embodiment of the present disclosure. A power amplifier circuit  100  illustrated in  FIG.  1    is a circuit that is installed in, for example, a mobile communication device, such as a cellular phone, and that amplifies the power of a radio frequency (RF) signal to a level necessary to transmit the signal to a base station. The power amplifier circuit  100  amplifies a transmission signal of a communication standard, such as the second generation mobile communication system (2G), the third generation mobile communication system (3G), the fourth generation mobile communication system (4G), the fifth generation mobile communication system (5G), long term evolution (LTE)-frequency division duplex (FDD), LTE-time division duplex (TDD), LTE-Advanced, or LTE-Advanced Pro. The frequency of an RF signal ranges from about several hundred MHz to several tens of GHz, for example. The communication standard and frequency of a signal to be amplified by the power amplifier circuit  100  are not limited to these. 
     Specifically, the power amplifier circuit  100  includes, for example, amplifiers  110  and  111 , bias circuits  120  and  121 , matching networks  130  and  131 , a bias adjustment circuit  140 , and capacitors C 1  and C 2 . 
     Each of the amplifiers  110  and  111  amplifies an input RF signal and outputs the amplified RF signal. That is, the power amplifier circuit  100  amplifies power in two stages. Specifically, the first-stage (driver-stage) amplifier  110  amplifies an RF signal RF 1  (first signal) inputted from an input terminal through the matching network  130  and outputs an RF signal RF 2  (second signal). The subsequent-stage (power-stage) amplifier  111  amplifies the RF signal RF 2  (second signal) supplied from the amplifier  110  and outputs an RF signal RF 3  (third signal). Each of the amplifiers  110  and  111  is constituted by, for example, a bipolar transistor, such as a heterojunction bipolar transistor (HBT), made of a compound semiconductor of gallium arsenide (GaAs) or the like. As each of the amplifiers  110  and  111  and the bias circuit  121  to be described, a field-effect transistor (FET) may be used instead of the bipolar transistor. 
     The bias circuits  120  and  121  supply a bias current or a bias voltage to the respective amplifiers  110  and  111 . The bias circuits  120  and  121  may adjust a bias current or a bias voltage to thereby control the gains of the amplifiers  110  and  111 . 
     The matching network (MN)  130  matches the impedance of a circuit (not illustrated) provided at a previous stage to that of the amplifier  110 . The matching network  131  matches the impedance of the amplifier  111  to that of a circuit (not illustrated) provided at a subsequent stage. Although omitted in  FIG.  1   , the power amplifier circuit  100  may include an interstage matching network between the amplifier  110  and the amplifier  111 . 
     The bias adjustment circuit  140  is a circuit that adjusts a bias current or a bias voltage to be supplied to the amplifier  111  by the bias circuit  121  by subjecting an RF input separated from the RF signal RF 1  to detection. The bias adjustment circuit  140  is used to improve the linearity of a phase of an output signal of the power amplifier circuit  100  when the output power of the power amplifier circuit  100  is relatively high. That is, in a typical power amplifier circuit, when the output power exceeds a certain level, a phase of an output signal can vary widely in accordance with the performance of a transistor. To deal with this issue, in the power amplifier circuit  100 , a current corresponding to the magnitude of the RF signal RF 1  is drawn from the bias circuit  121 , and a bias current to be supplied from the bias circuit  121  to the amplifier  111  is controlled, and the phase of the output signal is thereby controlled. 
     The capacitors C 1  and C 2  are provided at inputs of the respective amplifiers  110  and  111 . Each of the capacitors C 1  and C 2  is a direct current (DC) cut capacitor that blocks a direct-current component included in an RF signal and allows an alternating-current component to pass. 
     (2) Configuration of Each Element 
       FIG.  2    illustrates an example of a configuration of a power amplifier circuit  100 A according to the first embodiment of the present disclosure. In the power amplifier circuit  100 A illustrated in  FIG.  2   , the specific configurations of the bias circuit  121  and the bias adjustment circuit  140  in particular of the power amplifier circuit  100  illustrated in  FIG.  1    are illustrated. 
     (2-1) Amplifier 
     The amplifiers  110  and  111  include respective transistors Q 1  and Q 2 . With respect to the transistor Q 1  (first transistor), a power-supply voltage Vcc is supplied to a collector through an inductor L 1 , the RF signal RF 1  and a bias current are supplied to a base, and an emitter is connected to the ground. Thus, the transistor Q 1  outputs, from the collector, the RF signal RF 2  obtained by amplifying the RF signal RF 1 . With respect to the transistor Q 2  (second transistor), the power-supply voltage Vcc is supplied to a collector through an inductor L 2 , the RF signal RF 2  and a bias current are supplied to a base, and an emitter is connected to the ground. Thus, the transistor Q 2  outputs, from the collector, the RF signal RF 3  obtained by amplifying the RF signal RF 2 . 
     With respect to the inductors L 1  and L 2 , the power-supply voltage Vcc is supplied to one ends, and the other ends are connected to the collectors of the respective transistors Q 1  and Q 2 . Each of the inductors L 1  and L 2  is a choke inductor for inhibiting an alternating-current component from leaking to a power-supply voltage Vcc side. 
     (2-2) Bias Circuit 
     The bias circuit  121  includes, for example, transistors Q 3  to Q 5 , and resistance elements R 1  to R 3 . The configuration of the first-stage bias circuit  120  can be regarded as similar to the configuration of the subsequent-stage bias circuit  121 , and thus a detailed description thereof is omitted. The configurations of the bias circuits  120  and  121  are examples, and thus each of the bias circuits  120  and  121  may be a bias circuit having a current mirror configuration or another configuration. 
     With respect to the transistor Q 3  (third transistor), a battery voltage Vbatt is supplied to a collector, a base is connected to a base of the transistor Q 4 , and an emitter is connected to the base of the transistor Q 2  through the resistance element R 1 . Furthermore, as described later, the base of the transistor Q 3  is connected to the bias adjustment circuit  140 . Incidentally, a voltage to be supplied to the collector of the transistor Q 3  is not limited to the battery voltage Vbatt, and a desired voltage only has to be supplied. 
     With respect to the transistor Q 4 , a collector and the base are connected (hereinafter this type of connection is referred to as “diode connected”), a bias control voltage VB is supplied to the collector through the resistance element R 2  (first resistance element), and an emitter is connected to a collector of the transistor Q 5 . With respect to the transistor Q 5 , the transistor Q 5  is diode connected, the collector is connected to the emitter of the transistor Q 4 , and an emitter is connected to the ground through the resistance element R 3 . Thus, a voltage of a predetermined level (for example, about 2.7 V) is generated at the collector of the transistor Q 4 . Each of the transistors Q 4  and Q 5  may be constituted by a diode in place of a transistor. In this case, the collector (or base) and the emitter are to be regarded as an anode and a cathode, respectively. The same is true for a diode-connected transistor to be described. 
     With respect to the resistance element R 1 , one end is connected to the emitter of the transistor Q 3 , and the other end is connected to the base of the transistor Q 2 . The resistance element R 1  suppresses an increase in bias current accompanying an increase in local temperature in particular of the transistor Q 2 . With respect to the resistance element R 2 , the bias control voltage VB is supplied to one end, and the other end is connected to the collector of the transistor Q 4 . With respect to the resistance element R 3 , one end is connected to the emitter of the transistor Q 5 , and the other end is connected to the ground. 
     In the above-described configuration, the transistor Q 3  supplies a bias current from the emitter to the base of the transistor Q 2 . The bias circuit  121  does not have to include the resistance elements R 1  to R 3 . 
     (2-3) Bias Adjustment Circuit 
     The bias adjustment circuit  140  includes transistors Q 6  and Q 7 , and a capacitor C 3 . 
     The transistor Q 6  (fourth transistor) is diode connected and constitutes a first diode. With respect to the transistor Q 6 , a collector is connected, through the capacitor C 3 , to a side on which a supply path of the RF signal RF 1  to the transistor Q 1  is disposed, a base is connected to an emitter of the transistor Q 7 , and an emitter is connected to the ground. 
     With respect to the capacitor C 3 , one end is connected to the supply path of the RF signal RF 1  to the transistor Q 1 , and the other end is connected to the collector of the transistor Q 6 . The capacitor C 3  inhibits a direct-current component at the collector of the transistor Q 6  from being supplied to the supply path of the RF signal RF 1  to the transistor Q 1 . 
     The transistor Q 7  (fifth transistor) is diode connected and constitutes a second diode. A collector of the transistor Q 7  is connected to the bases of the transistors Q 3  and Q 4  of the bias circuit  121 . The emitter of the transistor Q 7  is connected to the base and the collector of the transistor Q 6 . The transistor Q 7  is provided to inhibit the backflow of a current flowing from the bias circuit  121  to the transistor Q 6 . Hence, the transistor Q 7  does not have to be a transistor and may be a diode. 
     The transistors Q 6  and Q 7  may be formed on the same semiconductor substrate. Here, the effect of improving the linearity of a phase of an output signal achieved by the power amplifier circuit  100 A to be described increases as the sizes of emitters of transistors in which the respective transistors Q 6  and Q 7  are formed decrease. The sizes of the emitters of the transistors in which the respective transistors Q 6  and Q 7  are formed may be about 2×2 m or may be smaller than about 2×2 m, for example. 
     (3) Operating Principle 
     Next, an operating principle of the power amplifier circuit  100 A will be described with reference to  FIGS.  2  to  5   . 
     An average current that flows into the collector of the transistor Q 6  from the side on which the supply path of the RF signal RF 1  to the transistor Q 1  is disposed is denoted by I 1 . An average current that flows into the collector of the transistor Q 6  from the emitter of the transistor Q 7  is denoted by I 2 . Of a current that flows from a power supply of the bias control voltage VB through the resistance element R 2  and flows from the collector of the transistor Q 4  to the base of the transistor Q 4 , part serves as a base current of the transistor Q 3 , and the other part flows to the bias adjustment circuit  140 . The other part of the current serves as the average current I 2  described above. Furthermore, an average current that flows out of the emitter of the transistor Q 6  is denoted by I 3 . At this time, the equation I 3 =I 1 +I 2  holds. 
     When a voltage value of the RF signal RF 1  is not less than a predetermined threshold value, the transistor Q 6  serving as the first diode is turned on, and a collector-emitter current flows. A current value of the collector-emitter current increases as the voltage value of the RF signal RF 1  increases. As a result, when a power level of the RF signal RF 1  increases, the average current I 3  that flows out of the emitter of the transistor Q 6  (a cathode of the first diode) increases. At this time, the average current I 1  increases in response to an increase in the average current I 3 . Of an amount by which the average current I 3  increases, an amount not covered by an amount by which the average current I 1  increases is covered by the average current I 2  drawn from the bias circuit  121 . Hence, when the power level of the RF signal RF 1  increases, the average current I 2  drawn from the bias circuit  121  increases. Thus, as the average current I 2  increases, an average current that flows from the bias control voltage VB to the base of the transistor Q 4  increases. As a result, when the output power increases, a voltage drop across the resistance element R 2  increases, and a base voltage Vef of the transistor Q 3  decreases. 
       FIG.  3    illustrates a relationship between, in the power amplifier circuit according to the first embodiment, the output power, and the base voltage of the third transistor. In  FIG.  3   , the horizontal axis represents output power (dBm) of the power amplifier circuit  100 A, and the vertical axis represents base voltage Vef (V) of the transistor Q 3 . In  FIG.  3   , a reference numeral  100 A denotes the power amplifier circuit  100 A, and a reference numeral  1000  denotes a power amplifier circuit  1000  in a comparative example. Here, the power amplifier circuit  1000  in the comparative example does not include the bias adjustment circuit  140 , and the supply path of the RF signal RF 1  to the amplifier  110  and the bias circuit  121  are not connected to each other. Other configurations of the power amplifier circuit  1000  in the comparative example are similar to those of the power amplifier circuit  100 A. 
     As illustrated in  FIG.  3   , in the power amplifier circuit  1000  in the comparative example, the base voltage Vef of the transistor Q 3  is almost constant at about 2.6 V regardless of the magnitude of the output power. On the other hand, in the power amplifier circuit  100 A according to the first embodiment, although the base voltage Vef in a region where the output power is low is on the order of about 2.6 V, the base voltage Vef decreases as the output power increases, and the rate of decrease in the base voltage Vef accompanying an increase in the output power increases in a region where the output power is high. Thus, in the power amplifier circuit  100 A, when a level of the output power increases, the average current I 2  that the bias adjustment circuit  140  draws from the bias circuit  121  increases, and the base voltage Vef of the transistor Q 3  therefore decreases. 
       FIG.  4    illustrates a relationship between power and phase of an output signal of the power amplifier circuit according to the first embodiment. In  FIG.  4   , the horizontal axis represents power (dBm) of an output signal of the power amplifier circuit  100 A, and the vertical axis represents phase (degrees) of the output signal (an absolute value of the phase of the RF signal RF 3  at an output node). In  FIG.  4   , a reference numeral  100 A denotes the power amplifier circuit  100 A, and a reference numeral  1000  denotes the power amplifier circuit  1000  in the comparative example. 
     As illustrated in  FIG.  4   , in the power amplifier circuit  1000  in the comparative example, the phase of the output signal decreases gradually as the output power increases, and the phase of the output signal decreases rapidly in a region where the output power is not less than about 28 dBm in particular. On the other hand, in the power amplifier circuit  100 A according to the first embodiment, although the phase of the output signal increases gradually as the output power increases, the phase of the output signal reaches a maximum value in the vicinity of an output power of about 28 dBm, and the phase of the output signal decreases gradually when the output power further increases. Subsequently, the phase of the output signal in the vicinity of an output power of about 32 dBm is approximately equal to the phase of the output signal in a region where the output power is low (an output power range of from about 10 to about 20 dBm). Hence, it can be said that, in the power amplifier circuit  100 A, the linearity of the phase of the output signal has been improved. 
     (4) Modifications 
       FIG.  5    illustrates an example of a configuration of a modification of the power amplifier circuit according to the first embodiment of the present disclosure. Hereinafter, a point in which the configuration of a power amplifier circuit  100 B serving as a modification differs from the configuration of the power amplifier circuit  100 A described above will be described, and a description of a point in which the configuration of the power amplifier circuit  100 B is similar to the configuration of the power amplifier circuit  100 A is appropriately omitted. 
     As illustrated in  FIG.  5   , the bias adjustment circuit  140  included in the power amplifier circuit  100 B includes a filter circuit  141 . The filter circuit  141  includes a capacitor C 4  (first capacitor) and a resistance element R 4  (second resistance element). One end of the capacitor C 4  is connected to the base of the transistor Q 6 , and the other end is connected to the ground. One end of the resistance element R 4  is connected to the base of the transistor Q 6  and to the one end of the capacitor C 4 , and the other end of the resistance element R 4  is connected to the emitter of the transistor Q 7 . 
     In the power amplifier circuit  100 B, the noise contained in the RF signal RF 1  is reduced by the filter circuit  141 , and the noise transferred to the bias circuit  121  decreases. In particular, in the case where the first diode is constituted by a diode-connected transistor (for example, the transistor Q 6 ), the effect of reducing the noise is increased. 
       FIG.  6    illustrates an example of a configuration of another modification of the power amplifier circuit according to the first embodiment of the present disclosure. Hereinafter, a point in which the configuration of a power amplifier circuit  100 C serving as a modification differs from the configuration of the power amplifier circuit  100 A described above will be described, and a description of a point in which the configuration of the power amplifier circuit  100 C is similar to the configuration of the power amplifier circuit  100 A is appropriately omitted. 
     As illustrated in  FIG.  6   , a bias circuit  122  of the power amplifier circuit  100 C includes transistors Q 3 , Q 8 , and Q 9 , resistance elements R 1 , R 2 , R 5 , R 6 , and R 7 , capacitors C 5  and C 6 , and a diode D 1 . In the bias circuit  122 , as in the bias circuit  121 , a current supply line to the bias adjustment circuit  140  is connected to a base terminal of the emitter follower transistor Q 3  that provides a bias current or a bias voltage to the base of the amplification-stage transistor Q 2 . In the bias circuit  122 , however, the number of transistor stages connected to the resistance element R 2  of a bias VB terminal is changed from two to one. 
       FIG.  7    illustrates an example of a configuration of still another modification of the power amplifier circuit according to the first embodiment of the present disclosure. Hereinafter, a point in which the configuration of a power amplifier circuit  100 D serving as a further modification differs from the configuration of the power amplifier circuit  100 A described above will be described, and a description of a point in which the configuration of the power amplifier circuit  100 D is similar to the configuration of the power amplifier circuit  100 A is appropriately omitted. 
     As illustrated in  FIG.  7   , a bias circuit  123  of the power amplifier circuit  100 D includes transistors Q 3  and Q 10 , resistance elements R 1 , R 2 , and R 10 , capacitors C 5 , C 6 , C 7 , and C 8 , and an inductor L 3 . In the bias circuit  123 , as in the bias circuit  121 , the current supply line to the bias adjustment circuit  140  is connected to the base terminal of the emitter follower transistor Q 3  that provides a bias current or a bias voltage to the base of the amplification-stage transistor Q 2 . However, the bias circuit  123  differs from the bias circuit  121  in that, for example, a parallel capacitor is connected and an LC filter (capacitor C 8  and inductor L 3 ) is employed as a supply bias line to the resistance element R 1 . 
     The embodiment according to the present disclosure has been described above. A power amplifier circuit according to the first embodiment includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current to be supplied by the bias circuit by subjecting the first signal to detection. The bias adjustment circuit controls the bias current to be supplied to the base of the second transistor by drawing, from the bias circuit, a current of a magnitude corresponding to a magnitude of the first signal. The current increases as the magnitude of the first signal increases. 
     Thus, when the output power of the power amplifier circuit increases, a current corresponding to the magnitude of the output power is drawn from the bias circuit. As a result, the linearity of a phase of an output signal of the power amplifier circuit is improved. 
     Furthermore, in the power amplifier circuit according to the first embodiment, the bias circuit may include a third transistor having an emitter from which the bias current is outputted. 
     Thus, the linearity of a phase of an output signal is improved. 
     Furthermore, in the power amplifier circuit according to the first embodiment, the bias adjustment circuit may include a first diode having an anode connected to a side on which a supply path of the first signal to the first transistor is disposed and to a base side of the third transistor, and having a cathode connected to a ground side. 
     Thus, the linearity of a phase of an output signal is improved. 
     Furthermore, in the power amplifier circuit according to the first embodiment, the first diode may be a fourth transistor that has a collector connected to the side on which the supply path of the first signal to the first transistor is disposed, a base connected to the base side of the third transistor, and an emitter connected to the ground side, and that is diode connected. 
     Thus, the linearity of a phase of an output signal is improved. 
     Furthermore, in the power amplifier circuit according to the first embodiment, the bias adjustment circuit may further include a second diode having an anode connected to a base of the third transistor and a cathode connected to the anode of the first diode. 
     Thus, the linearity of a phase of an output signal is improved. 
     Furthermore, in the power amplifier circuit according to the first embodiment, the second diode may be a fifth transistor that has a collector connected to the base of the third transistor and an emitter connected to the anode of the first diode, and that is diode connected. 
     Thus, the linearity of a phase of an output signal is improved. 
     Furthermore, in the power amplifier circuit according to the first embodiment, the bias adjustment circuit may further include a filter circuit having one end connected to the anode of the first diode and another end connected to the base side of the third transistor. 
     Thus, of an input signal to the power amplifier circuit, the noise transferred to the bias circuit through the bias adjustment circuit is reduced. Hence, the linearity of a phase of an output signal is improved with high accuracy. 
     Furthermore, in the power amplifier circuit according to the first embodiment, the filter circuit may include a first capacitor having one end connected to the anode of the first diode and another end grounded, and a second resistance element having one end connected to the anode of the first diode and to the one end of the first capacitor, and having another end connected to the base side of the third transistor. 
     Thus, the linearity of a phase of an output signal is improved with high accuracy. 
     Furthermore, in the power amplifier circuit according to the first embodiment, the current may increase as the magnitude of the first signal increases. 
     Thus, the linearity of a phase of an output signal is improved. 
     The above-described embodiment is intended to facilitate understanding of the present disclosure, but is not intended for a limited interpretation of the present disclosure. The present disclosure can be changed or improved without departing from the gist thereof and includes equivalents thereof. That is, appropriate design changes made to the embodiment by those skilled in the art are also included in the scope of the present disclosure as long as the changes have features of the present disclosure. For example, the elements included in the embodiment, and the arrangements, materials, conditions, shapes, sizes, and so forth of the elements are not limited to those exemplified in the embodiment, and can be appropriately changed. Furthermore, the elements included in the embodiment can be combined with each other so long as it is technically possible to do so, and such combined elements are also included in the scope of the present disclosure as long as the combined elements have the features of the present disclosure. 
     While preferred embodiments of the disclosure have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The scope of the disclosure, therefore, is to be determined solely by the following claims.