Patent Publication Number: US-2023154759-A1

Title: Semiconductor structures and method for manufacturing the same

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application claims priority to U.S. Provisional Application No. 63/280,296 filed Nov. 17, 2021, the disclosures of which are hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     The semiconductor industry has continually improved the speed and power of integrated circuits (ICs) by reducing the size of components (e.g., transistor devices) within the ICs. The ability to reduce the size of components within an integrated chip is usually determined by the lithographic resolution. For example, double patterning lithography (DPL) has become one of the most promising lithography technologies for printing critical design layers in sub-28 nm technology nodes. In recent years, self-aligned double patterning (SADP) has emerged as a double patterning technology that is able to avoid such misalignment and overlay errors. In the SADP technology, mandrels are formed, followed by the formation of spacers along sidewalls of the mandrels. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. Specifically, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a flow diagram showing a method of fabricating a semiconductor structure, in accordance with some embodiments of the present disclosure. 
         FIGS.  2 A,  7 D,  7 E,  8 D,  8 E,  9 E and  9 F  are schematic perspective views of a stacked structure in different stages of some operations of the method shown in  FIG.  1   , in accordance with some embodiments of the present disclosure. 
         FIGS.  2 B,  3 B,  4 B,  5 B,  5 C,  6 B,  6 C,  7 B,  8 B,  9 C,  9 D,  9 G,  10 B,  11 B,  12 B,  13 B and  14 B  are schematic cross-sectional views illustrating different stages of sequential operations of the method shown in  FIG.  1   , in accordance with some embodiments of the present disclosure. 
         FIGS.  3 A,  4 A,  5 A,  6 A,  7 A,  7 C,  8 A,  8 C,  9 A,  9 B,  10 A,  11 A,  12 A,  13 A and  14 A  are schematic top views illustrating different stages of sequential operations of the method shown in  FIG.  1   , in accordance with some embodiments of the present disclosure. 
         FIGS.  15 A and  15 B  are schematic top views illustrating various applications of a directional etching operation, in accordance with some embodiments of the present disclosure. 
         FIGS.  16 A,  16 B,  17 A,  17 B,  18 A and  18 B  are schematic top views illustrating multiple directional etching operations applied in the method shown in  FIG.  1   , in accordance with some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     The advanced lithography process, method, and materials described in the current disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs can be processed according to the above disclosure. 
     The present disclosure is directed to a patterning process for semiconductor structure. Specifically, the SADP technology is introduced in which mandrels are patterned, followed by the formation of spacers along sidewalls of the mandrels. The mandrels are removed while the spacers remain and are used to define a pattern at about half a pitch of the mandrels. The abovementioned patterning process may be performed to pattern lines in a semiconductor structure. The lines patterned in this way may attain a pitch that is difficult to achieve using existing lithographic equipment alone. 
       FIG.  1    is a flow diagram showing a method  200  of fabricating a semiconductor structure  300  shown in  FIGS.  14 A and  14 B .  FIGS.  2 A,  7 D,  7 E,  8 D,  8 E,  9 E and  9 F  are schematic perspective of the semiconductor structure views illustrating different stages of the method  200 .  FIGS.  2 B,  3 B,  4 B,  5 B,  5 C,  6 B,  6 C,  7 B,  8 B,  9 C,  9 D,  9 G,  10 B,  11 B,  12 B,  13 B and  14 B  are schematic cross-sectional views illustrating different stages of sequential operations of the method  200 .  FIGS.  3 A,  4 A,  5 A,  6 A,  7 A,  7 C,  8 A,  8 C,  9 A,  10 A,  11 A,  12 A,  13 A and  14 A  are schematic top views illustrating different stages of sequential operations of the method  200 . 
     In operation  201 , a stacked structure  101  is formed on a substrate  100 , as shown in  FIGS.  2 A and  2 B . The stacked structure  101  includes a mask layer  110  over the substrate  100  and a resist layer over the mask layer  110 . In some embodiments, the substrate  100  is a semiconductor substrate including doped or undoped silicon (Si), a bulk semiconductor substrate, a crystalline semiconductor substrate or an active region of a semiconductor-on-insulator (SOI) substrate. The substrate  100  may include other semiconductor materials such as germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb) or alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP or combinations thereof. 
     In other embodiments, the substrate  100  can be replaced with a dielectric layer which includes, but not limited to, silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), fluorinated SiO 2  (FSG), boro-phospho-silicate glass (BPSG), other low dielectric constant (&lt;3.9) materials, or combinations thereof. In some embodiments, the dielectric layer is an interlayer dielectric layer or an inter-metal dielectric (IMD) layer. In some embodiments, the substrate  100  includes conductive lines or vias (i.e., metal lines) that provide electrical connections to subsequently formed components. 
     The mask layer  110  is formed on a top surface S 1  of the substrate  100 . In some embodiments, the mask layer  110  is formed of a metal or a metallic compound such as titanium (Ti), tantalum (Ta), titanium nitride (TiN) or tantalum nitride (TaN). The mask layer  110  may be formed of metal-doped carbide (e.g., tungsten carbide) or a metalloid (e.g., silicon nitride, boron nitride or silicon carbide). In other embodiments, the mask layer  110  includes silicon oxynitride (SiON), nitride, oxide, low-k or high-k dielectrics. These materials are usually considered to be a “hard mask.” The mask layer  110  may include a single-layer structure or a multilayer structure. The mask layer  110  may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. 
     The resist layer  120  is formed on a top surface S 2  of the mask layer  110 . In some embodiments, the resist layer  120  is formed of a photoresist. The photoresist may be a single layer or include multiple layers. The resist layer  120  may be formed using spin coating or other suitable methods. In some embodiments, the resist layer  120  and the mask layer  110  are stacked over the substrate  100  along a thickness direction D 1  substantially orthogonal to the top surface S 1  of the substrate  100 . Each of the resist layer  120  and the mask layer  110  has a uniform thickness along a length direction D 2  and a width direction D 3  over the substrate  100 . The length direction D 2  and the width direction D 3  are respectively orthogonal to the thickness direction D 1 . 
     In operation  203 , the resist layer  120  of the stacked structure  101  is patterned, as shown in  FIGS.  3 A and  3 B . In some embodiments, the patterning process at least includes a lithography operation, such as exposure and developing steps. After the patterning process, portions of the resist layer  120  are removed and the remaining portions of the resist layer  120  form a mandrel pattern  122  on the mask layer  110 . In some embodiments, multiple parallel trenches T 1  are formed in the mandrel pattern  122  and portions of a top surface S 2  of the mask layer  110  are exposed through the trenches T 1 . As illustrated in  FIG.  3 B , in some embodiments, the trench T 1  extends along the length direction D 2 . 
     In operation  205 , a spacer layer  130  is formed on the stacked structure  101 , as shown in  FIGS.  4 A and  4 B . The spacer layer  130  may be deposited over the mandrel pattern  122  and the mask layer  110 . In some embodiments, the material of the spacer layer  130  is selected to have a high etching selectivity between the mask layer  110  and mandrel pattern  122 . For example, the etching selectivity between the mandrel pattern  122  and the mask layer  110  is between about 2.0 and about 8.0. In some embodiments, the spacer layer  130  is formed of aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), silicon oxide (SiO 2 ), hafnium oxide (HfO 2 ) or the like. The spacer layer  130  may be formed using a deposition process such as ALD, CVD, or the like. 
     As illustrated in  FIG.  4 B , the spacer layer  130  covers sidewalls of the mandrel pattern  122  and portions of the top surface S 2  of the mask layer  110 . In some embodiments, the spacer layer  130  is conformally formed such that the spacer layer  130  has substantially equal thicknesses across sidewalk and top surfaces of the mandrel pattern  122 . 
     In operation  207 , an etching operation is performed on the spacer layer  130 , as shown in  FIGS.  5 A,  5 B and  5 C .  FIGS.  5 B and  5 C  are schematic cross-sectional views respectively taken along line A-A′ and line B-B′ shown in  FIG.  5 A . In some embodiments, the etching process for removing portions of the spacer layer  130  is achieved by reactive ion etching (RIE). During the etching operation, the spacer layer  130  over the mandrel pattern  122  is completely removed and the spacer layer  130  over the mask layer  110  is partially removed. In such embodiments, the remaining portion of the spacer layer  130  forms multiple spacer patterns  132  left on sidewalk of the mandrel pattern  122 . The spacer pattern  132  may have a closed contour, e.g., the spacer pattern  132  includes an opening O 1  from a top-view perspective. 
     As illustrated in  FIGS.  5 B and  5 C , in some embodiments, the opening O 1  extends along the length direction D 2 . Multiple openings O 1  may be formed over the mask layer  110  and parallel to each other. Portions of the mask layer  110  are exposed through the openings O 1 . 
     In operation  209 , the mandrel pattern  122  is removed, as shown in  FIGS.  6 A,  6 B and  6 C .  FIGS.  6 B and  6 C  are schematic cross-sectional views respectively taken along line A-A′ and line B-B′ shown in  FIG.  6 A . An etching operation may be used to remove the mandrel pattern  122  and leave the spacer patterns  132  on the mask layer  110 . In some embodiments, the mandrel pattern  122  is differentiated from the spacer patterns  132  and the mask layer  110  in terms of an etching selectivity of the same etchant. The etching process may be selective to the mandrel pattern  122  and do not remove (or remove insignificantly) the spacer patterns  132  and the mask layer  110 . Therefore, the mandrel pattern  122  can be completely removed while the spacer patterns  132  and the mask layer  110  are kept substantially intact after the etching process. In some embodiments, the underlying mask layer  110  acts as an etch stop layer during the removal of the mandrel pattern  122 . After the mandrel pattern  122  is removed, each of the spacer patterns  132  is formed on the mask layer  110  along with the respective opening O 1 . The opening O 1  may be defined by the spacer pattern  132  as a closed contour. In some embodiments, at least one of the spacer patterns  132  has a ring shape when viewed from above. The ring-shaped spacer pattern  132  may have rounded corners around their top portions. In some embodiments, each of the spacer patterns  132  has a pair of length portions L 1  extending along the length direction D 2 , a pair of width portions R 1  extending along the width direction D 3 , and corner portions C 1  connecting the length portions L 1  and the width portions R 1 . 
     In operation  211 , at least one directional etching operation is performed on the spacer patterns  132 , as shown in  FIGS.  7 A to  7 E and  8 A to  8 E . In some embodiments, the directional etching operation includes a slanted plasma etching. The tilt angle of the plasma may be controlled based on a desired etching profile so as to adjust the etching direction. 
     Referring to  FIG.  7 A , in some embodiments, a directional etching operation E 11  is applied to the spacer patterns  132  along the length direction D 2  from a top-view perspective. The directional etching operation E 11  may be selective to the spacer patterns  132  and do not remove (or substantially do not remove) the mask layer  110 . As shown in  FIG.  7 A , the width portions R 1  and the corner portion C 1  of the spacer patterns  132  are orthogonal to an incident direction of the directional etching operation E 11 , as shown in  FIG.  7 A , and therefore the width portions R 1  and the corner portions C 1  of the spacer patterns  132  may encounter more plasma than the length portions L 1 . In such embodiments, the width portions R 1  and the corner portions C 1  receive more ion treatments or plasma bombardment during the directional etching operation E 11 . In some embodiments, the directional etching operation E 11  is used to trim the width portions R 1  while substantially preserving the length portions L 1  from trimming. 
       FIG.  7 B  is a schematic cross-sectional view taken along line B-B′ shown in  FIG.  7 A . In the directional etching operation E 11 , a plasma with a first tilt angle θ 1  is used to bombard the width portions R 1  along one side of the length direction D 2  (i.e., the left side of the length direction D 2  in the cross-sectional view). The first tilt angle θ 1  refers to an angle between the incident direction of the directional etching operation E 11  and a normal axis Z 1  that extends along the thickness direction D 1 . 
       FIG.  7 C  illustrates one of the spacer patterns  132  shown in  FIG.  7 A  being etched during the directional etching operation E 11  from a top-view perspective. The width portion R 1  may include a first width portion R 11  and a second width portion R 12  opposite to each other. In some embodiments, the width portion R 11  is bombarded from an exterior side of the spacer pattern  132 , and the width portion R 12  is bombarded from an interior side of the spacer pattern  132 . In such embodiments, the two opposing width portions R 11  and R 12  are simultaneously bombarded by the plasma in the directional etching operation E 11 . As the plasma continuously bombards the first and second width portions R 11 , R 12 , the opening O 1  is gradually elongated along the length direction D 2 . After the two opposing width portions R 11  and R 12  are etched through, the closed contour of the spacer pattern  132  is broken or cut open. Corner portions C 1  of the spacer pattern  132  may be partially trimmed during the removal of the width portion R 1 . 
       FIGS.  7 D and  7 E  are respectively schematic perspective views of the first and second width portions R 11  and R 12  in  FIG.  7 C . In some embodiments, the first width portion R 11  is directionally etched from the exterior side of the spacer pattern  132 , as shown in  FIG.  7 D . In some embodiments, the second width portion R 12  is directionally etched from the interior side of the spacer pattern  132 , as shown in  FIG.  7 E . In such embodiments, the exterior and interior sides of the spacer pattern  132  are simultaneously etched. 
     Referring to  FIG.  8 A , in some embodiments, a directional etching operation E 12  is applied to the spacer patterns  132  along the length direction D 2  from a top-view perspective. In some embodiments, the directional etching operation E 12  is applied along an opposite direction to the directional etching operation E 11  from a top-view perspective. The directional etching operation E 12  may be similar to the directional etching operation E 11  in many aspects except for the incident direction. 
       FIG.  8 B  is a schematic cross-sectional view taken along line B-B′ shown in  FIG.  8 A . In the directional etching operation E 12 , a plasma with a second tilt angle θ 2  is used to bombard the width portions R 1  along the other side of the length direction D 2  (i.e., the right side of the length direction D 2  in the cross-sectional view). The definition of the second tilt angle θ 2  may be the same as the first tilt angle θ 1  but symmetrical to the first tilt angle θ 1  with respect to the normal axis Z 1 . In some embodiments, the second tilt angle θ 2  is substantially equal to the first tilt angle θ 1  in value. In other embodiments, the first tilt angle θ 1  and the second tilt angle θ 2  are different. 
       FIG.  8 C  illustrates one of the spacer patterns  132  shown in  FIG.  8 A  being etched during the directional etching operation E 12  from a top-view perspective. In some embodiments, the width portion R 11  is bombarded from the interior side of the spacer pattern  132 , and the width portion R 12  is bombarded from the exterior side of the spacer pattern  132 . In such embodiments, the two opposing width portions R 11  and R 12  are simultaneously bombarded by the plasma in the directional etching operation E 12 . 
       FIGS.  8 D and  8 E  are respectively schematic perspective views of the first and second width portions R 11  and R 12  in  FIG.  8 C . In some embodiments, the first width portion R 11  is directionally etched from the interior side of the spacer pattern  132 , as shown in  FIG.  8 D . In some embodiments, the second width portion R 12  is directionally etched from the exterior side of the spacer pattern  132 , as shown in  FIG.  8 E . In such embodiments, the exterior and interior sides of the spacer pattern  132  are simultaneously etched. 
     In some embodiments, the directional etching operation E 11  and the directional etching operation E 12  together etch through the first and second width portions R 11 , R 12  and break the closed contour of the spacer pattern  132 . In such embodiments, the two directional etching operations E 11  and E 12  are alternatively performed with more than one cycle, such as 2 to 4 cycles, until the width portions R 1  of the spacer patterns  132  are completely removed. In other embodiments, the directional etching operation E 11  alone etches through the first and second width portions R 11 , R 12  and breaks the closed contour of the spacer pattern  132 . 
       FIG.  9 A  is a schematic top view illustrating multiple spacer features  134  generated from the spacer patterns  132  after operation  211 . After applying the directional etching operation E 11  and/or the directional etching operation E 12 , the spacer features  134  are formed on the mask layer  110 . In some embodiments, the spacer features  134  extend along the length direction D 2 . In some embodiments, the spacer features  134  are arranged in parallel along the width direction D 3 . 
       FIG.  9 B  is a schematic top view continued from  FIG.  7 C or  8 C  and shows a pair of spacer features  134 . Since the directional etching operations E 11  and E 12  are symmetrical to each other, two adjacent spacer features  134  may be formed in a pair when a single spacer pattern  132  is etched to remove its opposite width portions R 11  and R 12 . In some embodiments, each of the spacer patterns  132  is cut into two spacer features  134 A and  134 B. The two spacer features  134 A and  134 B may be symmetrical with respect to a central line M 1  extending in the length direction D 2  between the two spacer features  134 A and  134 B from a top-view perspective. That is, the two spacer features  134 A and  134 B may mirror images to each other. The spacer features  134  may have rounded or sharp corners from a top-view perspective. In some embodiments, each of the spacer features  134 A and  134 B has two trimmed ends  136 , The trimmed end  136  may have a sharp corner  137  connected to the inner sides of the length portion L 1  and a round corner  138  connected to the outer sides of the length portion L 1 . 
       FIG.  9 C  is a schematic cross-sectional view taken along line A-A′ shown in  FIG.  9 A . In some embodiments, any two adjacent spacer features  134  have a fixed pitch P 1 , which is a feature of an SADP process. The pitch P 1  is substantially equals to a total width of one opening O 1  (as shown in  FIG.  6 B ) and one spacer feature  134 . 
       FIG.  9 D  is a schematic cross-sectional view taken along line B-B′ shown in  FIG.  9 A . Since the spacer features  134  are formed along the length direction D 2 , there may be no spacer feature  134  shown in the cross-sectional view along line B-B′. 
       FIGS.  9 E and  9 F  illustrate schematic perspective views of spacer features  134 . Each of the spacer features  134  may have an inner sidewall W 1  and an outer sidewall W 2 . The inner sidewall W 1  may be connected to the outer sidewall W 2  via a boundary line B 1 . In some embodiments, the inner sidewall W 1  is substantially a flat surface. The inner sidewall W 1  may face the width direction D 3 , and the pair of inner sidewalls W 1  may face each other. In some embodiments, the outer sidewall W 2  is substantially a curved surface. The outer sidewall W 2  at least includes a round portion near the boundary line B 1  and may include a flat portion connected to the length portion L 1 . 
     Referring to  FIG.  9 E , in some embodiments, the boundary line B 1  is upright and parallel to the normal axis Z 1 . That is, the angle between the boundary line B 1  and the normal axis Z 1  is substantially 0 degrees. In such embodiments, the inner sidewall W 1  has a rectangular shape, and the outer sidewall W 2  is substantially upright. 
     Referring to  FIG.  9 F , in some embodiments, the boundary line B 1  is slanted and apart from the normal axis Z 1 , That is, an inclination angle α greater than 0 degrees may exist between the boundary line B 1  and the normal axis Z 1 . In such embodiments, the inner sidewall W 1  has a trapezoid shape and the outer sidewall W 2  is at least partially inclined. In some embodiments, the outer sidewall W 2  includes a bevel portion around the boundary line B 1 . 
       FIGS.  9 G  is a schematic cross-sectional view taken along line C-C′ shown in  FIG.  9 A . The spacer feature  134  may have a pair of boundary lines B 1  at two ends of the inner sidewall W 1 . In some embodiments, the inclination angle α between the boundary line B 1  and the normal axis Z 1  is between about −60 to about +60 degrees. The minus sign of the “−60 degrees” may refer to the inclination angle α measured in a counterclockwise direction from the normal axis Z 1 , and the plus sign of the “+60 degrees” refers to the inclination angle α measured in a clockwise direction from the normal axis Z 1 . In some other embodiments, the minus sign of the “−60 degrees” may refer to the inclination angle α measured in a clockwise direction from the normal axis Z 1 , and the plus sign of the “+60 degrees” refers to the inclination angle α measure in a counterclockwise direction from the normal axis Z 1 . In some embodiments, when one end of the inner sidewall W 1  corresponds to an inclination angle of +α, the other end of the inner sidewall W 1  corresponds to an inclination angle of −α, and vice versa. 
     The present disclosure uses an SADP technology in accompany with a directional etching operation to cut spacer patterns into a pair of spacer features, which can save a lithographic process. With the use of the directional etching operation, a photomask and lithography operations used to form a photoresist pattern that protect the length portions L 1  and expose the width portions R 1  of the spacer patterns  132  are saved. As a result, the manufacturing process can be simplified and the process cost can be reduced. 
     In operation  213 , the mask layer  110  of the stacked structure  101  is patterned, as shown in  FIGS.  10 A and  10 B . In some embodiments, the mask layer  110  is etched using the spacer features  134  as an etch mask. In some embodiments, the underlying substrate  100  acts as an etch stop layer during the patterning of the mask layer  110 . After the patterning process, portions of the mask layer  110  are removed and portions of the top surface S 1  are exposed. The remaining portion of the mask layer  110  forms multiple mask patterns  112  over the substrate  100 . 
     In operation  215 , the spacer features  134  are removed, as shown in  FIGS.  11 A and  11 B . An etching process may be used to remove the spacer features  134  and leave the mask patterns  112  on the substrate  100 . In some embodiments, the spacer features  134  are differentiated from the mask patterns  112  and the substrate  100  in terms of an etching selectivity of the same etchant. The etching process may be selective to the spacer features  134  and do not remove (or substantially do not remove) the mask patterns  112  and the substrate  100 . Therefore, the spacer features  134  can be completely removed while the mask patterns  112  and the substrate  100  are kept substantially intact after the etching process. 
     As illustrated in  FIG.  11 B , after the spacer features  134  are removed, each of the mask patterns  112  is formed on the substrate  100  and extend along the length direction D 2 . In some embodiments, the mask patterns  112  are parallel arranged along the width direction D 3 . Referring to  FIGS.  9 C and  11 B , the pitch P 1  of the spacer features  134  may be provided as the pitch of the mask patterns  112 . 
     In operation  217 , the substrate  100  is patterned, as shown in  FIGS.  12 A and  12 B , In some embodiments, the substrate  100  is etched using the mask patterns  112  as an etch mask. After the patterning process, portions of the substrate  100  are removed and the remaining substrate  100  forms a substrate  102 . As illustrated in  FIG.  12 B , in some embodiments, the substrate  102  includes multiple protruding fin patterns  104 . The fin patterns  104  are respectively covered by the mask patterns  112 . 
     In operation  219 , the mask patterns  112  are removed, as shown in  FIGS.  13 A and  13 B . An etching process may be used to remove the mask patterns  112  and leave the substrate  102 . In some embodiments, the mask patterns  112  are differentiated from the substrate  102  in terms of an etching selectivity of the same etchant. The etching process may be selective to the mask patterns  112  and do not remove (or substantially do not remove) the substrate  102 . Therefore, the mask patterns  112  can be completely removed while the substrate  102  are kept substantially intact after the etching process. As illustrated in  FIG.  13 B , in some embodiments, the fin patterns  104  extend along the length direction D 2  and are arranged in parallel along the width direction D 3 . In some embodiments, a trench H 1  is formed between two adjacent fin patterns  104  from a cross-sectional view. Multiple trenches H 1  may be arranged between the fin patterns  104 . 
     In operation  221 , a dielectric layer  140  is deposited onto the substrate  102 , as shown in  FIGS.  14 A and  14 B . In some embodiments, the material of the dielectric layer  140  includes oxide, nitride, oxynitride, carbide, a combination thereof, or the like. The dielectric layer  140  may be formed using a deposition process such as CVD. 
     In some embodiments, the trench H 1  is not completely filled with the dielectric layer  140 . The fin patterns  104  may protrude from the dielectric layer  140 . In other embodiments, the trench H 1  is completely filled with the dielectric layer  140 . As a result, the semiconductor structure  300  formed using the method  200  has been fabricated. 
     In some embodiments, multiple directional etching operations are used in the method  200 . One or more of these directional etching operations may be used to trim a target pattern or remove a sacrificial pattern that is otherwise removed by another operation.  FIGS.  15 A and  15 B  are schematic top views illustrating various applications of the directional etching operation. Referring to  FIG.  15 A , multiple target patterns  150  may be arranged in parallel along the width direction D 3  and over a substrate (not shown). Each of the target patterns  150  extends along the length direction D 2 . In some embodiments, the target patterns  150  are spacer patterns, mask patterns, fins of FinFETs or the like. The target patterns  150  may have a first length L 10 . Multiple sacrificial patterns  160  may be disposed near end portions of the target patterns  150 . Each of the sacrificial patterns  160  extends along the width direction D 3 . 
     In some embodiments, a directional etching operation E 10  is applied to the target patterns  150  along the length direction D 2 . The directional etching operation E 10  may at least include two single etching operations with respective etching directions. Either etching operation can be applied downwards or upwards to the target patterns  150  from a top-view perspective. As illustrated in  FIG.  15 A , all of the sacrificial patterns  160  may receive most of the ion bombardments of the directional etching operation E 10  since each sacrificial patterns  160  is substantially orthogonal to an incident direction the directional etching E 10 . After receiving a significant amount of ion treatments or plasma bombardment of the directional etching operation E 10 , all of the sacrificial patterns  160  may be removed, as shown in  FIG.  15 B . The removal of the sacrificial patterns  160  does not require any additional lithographic process. Since there is no need to use any photomask or photoresist, the processing cost can be greatly reduced. 
     Further, two ends  152  of each target patterns  150  may receive part of the directional etching operation E 10 . The two ends  152  may be partially or completely removed at the same time as the sacrificial patterns  160  are removed. Therefore, the target patterns  150  can be trimmed. Referring to  FIG.  14 B , after the directional etching operation E 10 , the remaining portion of the target pattern  150  may have a second length L 20  substantially less the first length L 10 . In some embodiments, the trimmed ends of the target patterns  150  have a sharp corner or a round corner from a top-view perspective. 
       FIGS.  16 A,  16 B,  17 A,  17 B,  18 A and  18 B  are schematic top views illustrating multiple directional etching operations applied in the method  200 . 
     Continued from  FIG.  9 A  and referring to  FIG.  16 A , in some embodiments, the method  200  further includes a second directional etching operation E 2  performed on the spacer features  134  between operation  211  and operation  213 . The second directional etching operation E 2  may at least include two single etching operations with respective etching directions. Either etching operation can be applied downwards or upwards to the spacer features  134  from a top-view perspective. In some embodiments, the second directional etching operation E 2  includes a slanted plasma etching. The tilt angle of the plasma may be controlled based on a desired etching profile so as to adjust the etching direction. In some embodiments, the second directional etching operation E 2  is applied to the spacer features  134  along the length direction D 2 . Two ends (marked as dashed boxes) of each spacer features  134  may be at least partially removed. Therefore, the spacer features  134  can be trimmed to have a desired length, as shown in  FIG.  16 B , prior to subsequent operations. In some embodiments, the trimmed ends of the spacer feature  134  have a sharp corner or a round corner from a top-view perspective. 
     Continued from  FIG.  11 A  and referring to  FIG.  17 A , in some embodiments, the method  200  further includes a third directional etching operation E 3  performed on the mask patterns  112  between operation  215  and operation  217 . The third directional etching operation E 3  may at least include two single etching operations with respective etching directions. Either operation can be applied downwards or upwards to the mask patterns  112  from a top-view perspective. In some embodiments, the third directional etching operation E 3  includes a slanted plasma etching. The tilt angle of the plasma may be controlled based on a desired etching profile so as to adjust the etching direction. In some embodiments, the third directional etching operation E 3  is applied to the mask patterns  112  along the length direction D 2 . Two ends (marked as dashed boxed) of each mask patterns  112  may be at least partially removed. Therefore, the mask patterns  112  can be trimmed to have a desired length, as shown in  FIG.  17 B , prior to subsequent operations. In some embodiments, trimmed ends of the mask patterns  112  have a sharp corner or a round corner from a top-view perspective. 
     Continued from  FIG.  13 A  and referring to  FIG.  18 A , in some embodiments, the method  200  further includes a fourth directional etching operation E 4  performed on the fin patterns  104  between operation  219  and operation  221 . The fourth directional etching operation E 4  may at least include two etching operations with respective etching directions. Either operation can be applied downwards or upwards to the fin patterns  104  from a top-view perspective. In some embodiments, the fourth directional etching operation E 4  includes a slanted plasma etching. The tilt angle of the plasma may be controlled based on a desired etching profile so as to adjust the etching direction. In some embodiments, the fourth directional etching operation E 4  is applied to the fin patterns  104  along the length direction D 2 . Two ends (marked as dashed boxes) of each fin patterns  104  may be at least partially removed. Therefore, the fin patterns  104  can be trimmed to have a desired length, as shown in  FIG.  18 B , prior to subsequent operations. In some embodiments, the trimmed ends of the fin patterns  104  have a sharp corner or a round corner from a top-view perspective. 
     The directional etching operations E 2 , E 3  and E 4  do not require any lithographic process. As a result, the trimming of spacer features  134 , mask patterns  112  or fin patterns  104  does not need any photomask or photoresist, and thus the processing cost can be greatly reduced. It is noted that one or more of the directional etching operations E 2 , E 3  and E 4  may be optional. Therefore, each of the directional etching operations E 2 , E 3  and E 4  may be used in accompany with the use of the directional etching operation E 1 . 
     One aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other. 
     One aspect of the present disclosure provides another method of manufacturing a semiconductor structure. The method includes providing a substrate; forming a mask layer over the substrate; forming a mandrel pattern over the mask layer, wherein the mandrel pattern extends along a first direction; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern to form an opening defined by the spacer pattern, wherein the spacer pattern has a closed contour; and applying a directional etching operation along the first direction to etch two opposing sidewalls of the spacer pattern. 
     One aspect of the present disclosure provides another method of manufacturing a semiconductor structure. The method includes providing a substrate; forming at least one target pattern on the substrate, wherein the at least one target pattern extends along a first direction; forming at least one sacrificial pattern adjacent to the at least one target pattern, wherein the at least one sacrificial pattern extends along a second direction perpendicular to the first direction; and applying a directional etching operation along the first direction to trim two ends of the at least one target pattern. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.