Patent Publication Number: US-7724097-B2

Title: Direct digital synthesizer for reference frequency generation

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention provides frequency synthesizer circuit architectures that are particularly adapted for use in computation, control and communication applications. 
   2. Description of Related Art 
   Low frequency (32 KHz-300 MHz) clock or timing signals are employed in electronic devices for many different applications. A typical reference oscillator may use a quartz resonator or another resonator which may operate on a fundamental frequency (less than about 40 MHz) or an overtone mode of oscillation (about 30 to 300 MHz). However, certain electronic devices (e.g., mobile communication devices) require higher frequency (500 MHz-3 GHz) timing signals which either cannot be generated directly by quartz resonators or other electro-acoustic resonators, or are prohibitively expensive to generate using such resonators. Also, high-frequency oscillators that use non-acoustic resonator technology (e.g., an inductor/capacitor resonant tank) cannot achieve the low phase noise or low power consumption required by many applications. Furthermore, conventional oscillator solutions may be too costly or too bulky for certain product applications and/or fail to provide a sufficient variety of output frequencies with sufficiently low noise. 
   An alternate approach to generating a reference signal is frequency synthesis, which can be performed either indirectly, by employing a phase lock loop (“PLL”), or directly, by employing a direct digital synthesizer (“DDS”). 
   In PLL frequency synthesis, a reference oscillator operating at a relatively low frequency (f REF ) is employed to generate a higher output frequency (f out &gt;f REF ) with a desired accuracy. To accomplish this synthesis, the frequency of a voltage controlled oscillator (“VCO”) is adjusted until the phase error between the reference oscillator and the VCO is minimized. The VCO is adjusted by a feedback loop that compares the frequency and phase of the VCO to that of the reference oscillator. When the loop settles, the VCO frequency closely tracks both the frequency and phase of the reference signal according to a predetermined harmonic relationship defined by the division ratios of the dividers used in the PLL circuit, e.g. f VCO /N=f REF /M. Non-harmonic scaling may be obtained by rapidly switching the divider between adjacent ratios P and P+1 with the aid of a controller often employing a delta-sigma modulator loop. The instantaneous output frequency alternates between f REF *P/M and f REF *(P+1)/M, and the average frequency equals f REF *(P+N)/M where N is a non-integer value between 0 and 1. Simultaneously with the divider modulus control, a phase correction is also applied to the divider output signal before it is compared with the reference signal to produce an error signal that is low-pass-filtered and applied to the VCO input. This implementation is also known as a fractional-N synthesizer. 
   The output signal of a fractional-N PLL may be degraded by the presence of spurious signals and noise that result from the constant switching of the P divider. These undesired signals must be minimized to meet the requirements of practical applications, which results in increased power consumption and loop settling time. 
   In typical DDS architectures, a higher reference frequency generator is used with a numerically controlled oscillator (“NCO”) to produce an output signal having controlled frequency and phase. The DDS output frequency range and resolution is mainly determined by the reference frequency and the length of the NCO word. As a result, DDS circuits that deliver a higher synthesized output frequency tend to have higher power consumption. 
   While existing phase interpolating DDS architectures may provide generation of a wide range of output frequencies from a single reference oscillator, improved DDS architectures are desired. 
   SUMMARY OF THE INVENTION 
   In accordance with aspects of the present invention, DDS synthesizer architecture derive a signal with selectable output frequency (“f OUT .”) from an oscillator signal with higher fixed frequency (“f osc ”) using a combination of a multi-modulus divider providing at least two possible modulii for reducing the frequency of an input signal to achieve the desired frequency for f our  and a variable delay to achieve a desired instantaneous phase for f OUT . The resultant f out  signal may then be used to clock or drive circuitry in a user device that requires a lower reference frequency. 
   In one embodiment the frequency synthesizer has an input for receiving a clock reference signal at a first frequency f osc . The direct digital synthesizer (DDS) architecture has a multi-modulus divider for dividing the frequency of the input signal to provide an intermediate signal. Multi-modulus, as used herein, refers to the multiple programmable division ratios used to divide the frequency of the input signal into a lower frequency. The embodiment also has a numerically controlled oscillator (NCO) having an accumulator receiving an accumulator increment value. The NCO provides a phase value to a latch circuit. The latch circuit receives and is clocked by the intermediate signal wherein the numerically controlled oscillator outputs a delay value comprised of one or more bits and an overflow signal comprised of one or more bits wherein said overflow signal is provided to the multi-modulus divider to select between at least a first divider ratio and a second divider ratio. The DDS also has a programmable delay generator. In one embodiment, the delay generator receives the delay signal having one or more bits and the overflow signal containing one bit. In preferred embodiments the delay generator receives one or more reference clock signals (e.g. the clock input signal to the multi-modulus divider and or the signal with the intermediate adjusted frequency output from the multi-modulus divider. From the inputs, the delay generator calculates a delay time for application to each pulse in the signal with an intermediate adjusted frequency to provide an output signal which achieves improved phase noise and timing jitter performance (f out ). 
   In certain preferred embodiments discussed herein, the multi-modulus divider selects between first and second divider ratios, while in other preferred embodiments the multi-modulus divider selects between a first divider ratio, a second divider ratio and a third divider ratio. In some instances selected embodiments also have one or more programmable dividers. In these embodiments, the programmable divider operates on the signal input into the multi-modulus divider or on the intermediate signal output from the programmable divider. If the former, the programmable pre-multi-modulus divider reduces the overall power consumption by providing a lower frequency signal to the multi-modulus divider. If the latter, the programmable post-multi-modulus divider provides a wide range of division ratios by which the frequency of the signal input to the multi-modulus divider is divided. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects and advantages of the invention will be appreciated more fully from the following further description thereof, with reference to the accompanying drawings, wherein: 
       FIG. 1  illustrates a functional block diagram of a DDS architecture in accordance with aspects of the invention. 
       FIG. 2  illustrates a delay generator that can be employed with aspects of the present invention. 
       FIG. 3  shows the waveform timing relationships for the circuit of  FIG. 2 . 
       FIG. 4  is an exemplary timing diagram for the direct digital synthesis block diagram of  FIG. 1 . 
       FIGS. 5   a  and  5   b  are tables illustrating the behavior of a 3 and 4-bit NCO DDS systems in accordance with aspects of the present invention. 
       FIG. 6  illustrates an alternative embodiment of the invention. 
       FIGS. 7   a  and  7   b  show details of an exemplary frequency plan of a preferred embodiment of the present invention. 
       FIG. 8   a  shows the role of the f OSC OFFSET setting of the reference oscillator in the frequency planning of a preferred embodiment. 
       FIG. 8   b  illustrates the functionality of a MCpolarity setting in accordance with aspects of the present invention. 
       FIG. 9  illustrates an alternate embodiment of the invention that employs a digitally generated randomization signal to create a controlled spread-spectrum reference frequency output. 
       FIG. 10  illustrates yet another embodiment of the invention. 
       FIG. 11  illustrates another alternate embodiment of the invention that utilizes a triple-modulus divider. 
       FIGS. 12   a - c  illustrates the operation of one embodiment of  FIG. 11 . 
       FIG. 13  illustrates the architecture of a further embodiment of the present invention. 
       FIG. 14  illustrates a variation of the embodiment shown in  FIG. 13 . 
   

   DETAILED DESCRIPTION 
   The present invention is described in terms of several embodiments. In describing these embodiments, including the drawings, specific terminology will be used for the sake of clarity. Also, in the discussion of certain mathematical relationships, certain variable values are discussed by way of illustration. However, the invention is not intended to be limited to the specific embodiments described below. 
     FIG. 1  is a schematic illustration of a multi-modulus divider direct digital synthesizer (“DDS”) architecture  10  in accordance with aspects of the present invention. This exemplary DDS architecture  10  includes a reference oscillator  12 , a multi-modulus divider  14 , an NCO  16  and a delay generator  18 , which is also referred to herein as a “phase interpolator.” 
   Reference oscillator  12  produces a periodic waveform with a frequency f osc . As shown in the figure, f OSC  is provided to the multi-modulus divider  14  and the delay generator  18 . The reference oscillator  12  may, by way of example, utilize a bulk acoustic wave resonator (e.g., FBAR-type or SMR-type), a micromechanical or nanomechanical resonator, a dielectric resonator, an LC tank or a quartz resonator. 
   The multi-modulus divider  14  is illustrated as a dual modulus divider which is operable to switch between division ratios P and P+1 to modify the received f OSC  signal. As will be discussed in detail below, the division ratio is controlled by the overflow output of the NCO. This overflow output is also referred to as modulus control (“MC”). The multi-modulus divider  14  is preferably synchronous with the oscillator frequency f OSC . 
   The NCO  16  includes an adder or accumulator  20  and a holding circuit/register  22 . The holding circuit  22  may be, for example, a bank of delay flip-flops or latches. The NCO  16  may also include a look-up table and other phase control circuits (not shown). 
   The delay generator  18  generally has a programmable delay circuit  24  whose function is to delay individual pulse edges based on a control word. The delay generator  18  also includes a delay control circuit  26  that receives various timing signals along with the NCO output word and provides the control word to the delay circuit  24 . The delay generator  18  is used to delay the phase of a resultant output signal relative to the phase the signal input to the delay generator  18 . 
   As shown in  FIG. 1 , in response to the input signal f OSC , the multi-modulus programmable divider  14  provides a clocking signal V P  to the NCO  16  and the phase interpolator  18 . The frequency f DIV  of signal V P  is related to f OSC  as follows: f Vp =f OSC /P set  where P set  can be P or P+1 as determined by the modulus control signal MC output from the NCO  16 . 
   The NCO  16 , in particular holding circuit  22 , is clocked by the output V P  of the multi-modulus divider  14 . As further shown in  FIG. 1 , a digital tuning word K is provided as an input to the accumulator  20  of the NCO  16 . The holding circuit  22  of NCO  16  outputs an overflow value (“OVF”) or MC as well as an output word N A . The input word K sets the value by which the accumulator output value (“A”) of word length N A  is incremented for each V P  pulse generated by the multi-modulus programmable divider  14 . The value D is the portion of the accumulator output value A that is output from the NCO  16 . D is used to set the delay of the delay generator/phase interpolator  18 . The word length of D is N D . As described in further detail N D ≦N A  (N A  is the word length of value A). 
   In particular, the NCO  16 , clocked at f Vp , computes the phase value of the synthesized signal. Tuning word K, provided to accumulator  20  of the NCO  16 , specifies how many V P  periods are counted by the accumulator  20  for each f OUT  period. The holding circuit  22  in the NCO  16  updates the phase value calculated by the accumulator  20  at intervals of 1/f Vp . The delay value (as represented by D and which, in certain embodiments, is a truncated word of that output from the holding circuit) and the overflow signal OVF are provided to the delay generator  18  to generate a residual phase correction via delay control  26 . 
   The instantaneous frequency of signal V P  oscillates between f OSC /P and f OSC /(P+1), where P is the multi-modulus programmable divider base value, depending on the value of the modulus control signal MC. It can be shown that for N A =N D , the average value of the output frequency f OUT  is as follows:
 
 f   OUTideal   =f   OSC /( P+K/ 2 N     A   )  (2)
 
where P is the multi-modulus programmable divider base value, K is the programmed NCO accumulator increment value as described above and N A  is the NCO word length. The ratio K/2 N     A    can range from 0 to 1−(2 −N     A   ). As a result, the instantaneous frequency deviation of signal V P  at the n th  pulse instant is:
 
Δ f   Vp ( n )= f   OUTideal   −f   Vp ( n )= f   OSC *[1/( P+K/ 2 N     A   )−1/ P   n   ]=f   OSC   /P   n   *[P   n −( P+K/ 2 N     A   )]/( P+K/ 2 N     A   ).  (3)
 
It is easy to prove that the maximum error occurs for K=2 (N   A   −1) . An example of this is illustrated in  FIG. 5B  discussed below. For large N A  values, this is −f OSC /(2P 2 +P) for P n =P, or f OSC /(2P 2 +3P+1) for P n =P+1.
 
   Holding circuit  22  in NCO  16  latches at least the N A  bits of the accumulator output word A. It is advantageous if the holding circuit  22  also latches the overflow signal bit of the accumulator  20 . The holding circuit  22  is latched by the signal V P . A portion of the accumulator output word, which is referred to herein as delay value D (n−1) , is provided to the delay control circuit  26  of the delay generator  18  along with the overflow value OVF, with a delay of one V P  pulse period. The NCO phase value at each overflow instant represents the residual phase portion of the accumulator output word A and is used to provide a phase correction to the delay control circuit  26  while the overflow pulse OVF (MC) controls the modulus of multi-modulus divider  14 . It should be noted that the edges of the V P  pulse train are delayed by the programmable delay generator  18  based on the phase value originating from the NCO  16 . 
   The delay generator  18  may be implemented in different ways. Examples of delay generator implementations are described in U.S. Pat. No. 6,188,261 entitled “Programmable Delay Generator and Application Circuits Having Said Delay Generator” which issued on Feb. 13, 2001 and is incorporated by reference herein. One exemplary implementation of such circuits is shown in  FIG. 2 .  FIG. 2  shows a specific implementation of a delay generator employing an integrator  50  that starts a programmable-slope ramping voltage  52  V Ramp  (e.g. by charging a capacitor with a constant current) after it receives a start pulse (Pulse In). The ramp slope is programmable via a slope control word  54  that determines the delay control range. Signals V P  and Reset are fed to an integrator  56  in addition to the slope control word  54 . Signal V P  starts the integrator ramp and signal reset forces it to assume its initial value. 
   Before the input pulse is applied, a Delay-Set word (derived from delay word D) is input to D/A converter  58  which in turn provides a threshold voltage (V Threshold ). The voltage ramp V Ramp    52  is compared with the threshold voltage V Threshold  by comparator  60 . An output of the comparator  60  is provided to a one-shot multivibrator  62 . The resultant output of one-shot multivibrator  62  (V D ) gets triggered each time there is a crossover of V D  below V Threshold . This crossover determines the delay (t D ) of the output pulse referenced to the input edge. The corresponding waveforms are shown in  FIG. 3 . 
   Returning to the embodiment of  FIG. 1 , for the DDS to operate as desired, the applied delay should be a fraction of the f OSC  period. At the n th  V P  pulse, the applied delay should ideally be D n−1 /2 N     A   *1/f OSC , where D n−1  was the value of the NCO output word at the previous overflow (n−1 th  V P  pulse). Depending on the actual implementation of the DDS, N D  can equal N A  or just be a fraction of it (i.e. N A ≧N D ). In any case, the words D and A are related as follows:
 
 D=A/ 2 (N     A     −N     D     )   (4)
 
Therefore, the correction delay added to the n th  V P  pulse edge is T c(n) =D (n−1) /2 N     D   *1/f OSC . If N A &gt;N D , the residual error ΔT corr =[D (n−1) /2 N     D   −A (n−1) /2 N     A   ]*1/f OSC  results in deterministic quantization noise, and therefore deterministic frequency jitter on the DDS output signal. Note, one skilled in the art would realize that the operation of the overall embodiment of  FIG. 1  remains unchanged if the delay has one or more but generally less than P- 2  f OSC  periods added to all of the delay values.
 
   In addition to the selected portion of the accumulated phase value A and OVF, the delay control circuit also could receive signal f OSC  from the reference oscillator  12  as this could enhance the delay accuracy. V P  is also optionally provided to the delay generator circuit  18 . Since the more timing information that is provided to the delay generator, the better it will perform,  FIG. 1  illustrates the delay control with inputs of V P  and f OSC . The delay control  26  uses the truncated accumulator output value D, the value OVF and optionally, V P  and f OSC  to perform delay correction on V P  that essentially shifts the V P  pulses by a fraction of the f OSC  period according to the previous NCO output word. The resultant signal V D  is a phase corrected signal. 
   The output frequency is given by the following relationship: f OUT =f OSC /(P+K/2 N     A   ) where f OSC  is the reference oscillator frequency, P is the dual modulus divider base ratio, K is the NCO accumulator increment, and N A  is the NCO word length. 
   The frequency synthesis resolution is given as:
 
Δ f=f   OSC *(1 /P− 1/( P+ 1/2 N     A   ))  (5)
 
   The average frequency deviation over M V D  output pulses is defined as:
 
Δ f= 1 /M*Σ (| f   inst(n)   −f   OUTideal |)  (6)
 
where f inst(n)  is the instantaneous frequency of the corrected pulses after the phase correction has been applied. This is given as:
 
 f   OUT =1 /T   D(n) =1 /[t   D(n+1)   −t   D(n) ]=1 /[T   P(n)   +T   OSC /2 N     D   *( D   (n)   −D   (n−1) )]  (7)
 
Where t D(n+1)  and t D(n)  are the delay-corrected output pulse edges at instances n+1 and n, corresponding to delay correction words D (n)  and D (n−1)  and T P(n)  is the period of the P divider output at the n th  instance.
 
   It can be seen in  FIG. 1  that NCO  16  is clocked by the dual modulus divider output signal V P  to provide a delay correction value to the delay generator circuit  18 . As will be discussed in more detail below, an optional binary frequency divider  104  shown in  FIG. 6  may provide a fixed binary frequency division while it will also correct the duty cycle of the output waveform (f OUT ). As the reference oscillator signal at frequency f OSC  in  FIG. 1  is operated on by programmable divider  60 , the frequency of V P  is necessarily lower than f OSC . 
   In fact, the higher the f OSC /f OUT  ratio, the finer the f OUT  frequency synthesis resolution for a given NCO word length as shown above. The advantage of a high f OSC /f OUT  ratio is that the delay generator and the NCO now operate at a much lower rate than in conventional phase-interpolating DDS architectures and therefore the circuit architecture of  FIG. 1  features reduced power consumption over these DDS implementations. Furthermore, in  FIG. 1 , interpolation by the delay generator circuit (phase interpolator)  18  occurs at lower speeds, which offers a significant improvement over the prior art as the lower clocking speed results in a lower power dissipation. 
   The output pulse V D  has a duty cycle that depends on the synthesized frequency f OUT . Optionally, a toggle Flip-Flop (T-FF) with an output of half the frequency (f OUT /2) or other latching mechanism can be used to produce a duty-cycle corrected version of the synthesized output frequency signal. 
     FIG. 4  is a timing diagram showing an example of operation of the circuit architecture of  FIG. 1 .  FIG. 5A  is a table that illustrates the behavior of the system described in  FIG. 4 . A number of signals are shown in the plots illustrated in  FIG. 4 . Before addressing the various plots, it is important to understand that certain parameters associated with the architectures have been selected in this example for illustrative purposes. For instance, the divider modulus base value (P) has been set to 4. This means that unless there is an overflow, four f OSC  pulses are typically passed before a V P  pulse comes from the programmable divider  18 . When an overflow occurs, the divider counts 5 f OSC  pulses before a V P  is produced. A larger value of P results in a lower output frequency. While P has been set to a value of 4 in this example, it should be understood that P may be any integer value. P may be set at manufacture to a specific value or range of values depending upon operating conditions. 
   By way of example only, P may be any integer from 3 to 30. Said another way, the larger the value of P, the better control and finer resolution there is over the synthesized output signal V P . 
   In the example of  FIG. 4 , the word length N A  of the NCO accumulator  16  is selected to be 3 bits. This provides a maximum value of A to be 7. A larger word length N A  will result in a finer f OUT  resolution as described above. The resolution of the accumulator output value determines the resolution of the phase correction word. In other words, the precision of the ratio of the accumulator increment to the full-scale range determines the time-scale granularity of the f OUT  pulse edges. Another value set in this example is the word length of the delay being applied, which here is shown to be equal to N D . 
   As mentioned above, in general N A ≧N D . The value of N A  determines the granularity of the average frequency programming as shown above through the ratio K/2 N     A   . As the instantaneous frequency of signal V P  will vary between f OSC /P and f OSC /P+1, the value of N D  determines the effectiveness of the phase interpolation which ultimately determines the phase jitter (or Phase Noise) of the synthesizer. 
   Obviously, the larger the NCO word length the finer the output frequency synthesis resolution. For example, in a practical frequency synthesis application with a f OSC  frequency in the neighborhood of 2 GHz, if one wants to generate any arbitrary frequency with an accuracy of 1 PPM in the range of 400 to 500 MHz the P divider should be set up for division-by 4 or 5, while a word length N A  greater than 18 bits should be used. In this particular application, given that the instantaneous value of the frequency f Vp  will be switching between 400 and 500 MHz and given the current state of the art of delay generator designs, and given that implementations of digital to delay converters with larger N D  values become exponentially more complex and consume exponentially more power (i.e. the more bits, the more complicated, with, for example, 6 bits being more complicated than 4 bits and 9 bits more complicated than 6 bits, etc.), N D  would be chosen considerably smaller than N A  in this case. In particular, the value of N D  will generally be set as small as possible while still achieving sufficient cycle-to-cycle jitter performance and sufficient high frequency phase noise performance for the target application. 
   The rate of overflow is dependent on the accumulator increment value K. The rate of overflow affects how the delay value applied to the phase interpolator varies (note that it can only be greater than zero). In this example, the increment value, K, is set at 3. The ratio of K to 2 N     A    determines the effective divide ratio of the synthesizer (i.e. fractional division). As K assumes values in the range of 0 to 2 N     A     −1  the output frequency f OUT  ranges from f OSC /(P+2 −N     A   ) to f OSC /(P+1−2 −N     A   ). 
   In the timing diagram of  FIG. 4 , the topmost plot shows the waveform output by the reference oscillator. The frequency of the reference oscillator output is f OSC  as shown. 
   The second plot from the top shows the waveform of signal V P  output by multi-modulus divider  14 . As discussed above, V P  is provided to the delay generator  18 , as well as to D-FF  22  of the NCO  16 . The timing of the pulses V P  depends upon the multi-modulus divider  14  toggling between P and P+1. Signal V P  sets the NCO operational frequency. 
   In  FIG. 4 , the third plot from the top presents the value of the accumulator output word (D), which produces the delay control word to be applied to V P . A delayed version of this value is applied to the delay generator as described below. 
   The fourth plot from the top shows the overflow signal OVF which issues from holding or latching circuit  22 . The OVF signal controls the division ratio (modulus control) of multi-modulus divider  14 . It is also input into delay control circuit  26  of the delay generator  18 . As shown in  FIG. 4 , OVF lasts for one V P  cycle every time it is triggered. The accumulator values that cause the overflow are set forth in the table in  FIG. 7A . Note, in this example, the overflow value causes the P value to change from P to P+1 which causes the T osc  count to increase from 4 to 5. The increment of t p  and the value of T P  also increase in duration during overflow. 
   The fifth plot from the top shows a signal representing the delay value (D (n) ), which is output by the accumulator  20 . In the present example, this signal may range from a value of zero to a value of 7. Other values may be selected depending upon a design choice for various operating conditions. For K=3, the leftmost delay value is zero, while the next delay value is 3, the third delay is 6, the fourth delay is 1, the fifth delay is 4, the sixth delay is 7, the seventh delay is 2, the eighth delay is 5 and the ninth delay is 0. 
   The sixth plot from the top presents delay value (D (n−1) ) applied to delay generator/phase interpolator  18  via signal D output from holding/latching circuit  22  of NCO  16 . It can be easily observed that the D (n−1)  are staggered by one V P  cycle relative to D (n) . 
   Finally, the seventh plot from the top presents a pulse train showing the delay-compensated output pulse signal V D  of  FIG. 1 , in relation to signal V P . Referring to  FIG. 5A  it is observed that the increments of t D  are uniform, and the effect of the uniform values of t D  results in a uniform value for f out . As noted from  FIG. 3  t D  is the time delay applied to the pulse V D  relative to the pulse edge for V P .  FIG. 5B  illustrates the effect of a change in the value of N A  and K from 3 (in  FIG. 5A ) to 4 and 7, respectively, in  FIG. 5B . In addition to a change in the increments for an overflow to occur,  FIG. 5B  illustrates that T D  and therefore f out  oscillates between two values.  FIG. 5B  illustrates a system operation where the input increment K≈2 N     A     −1 . In this example, the K increment (7) is approximately equal to 2 4−1  (i.e. 8). As stated below, it is preferred if K does not assume values at or near the limits of its range of values. 
   As explained above with regard to  FIGS. 1 and 4 , the edge-corrected V D  pulses can be duty-cycle corrected by passing them through a device such as a toggle flip-flop or a binary frequency divider, as will be described in more detail below with regard to  FIG. 6 . 
     FIG. 6  is a schematic illustration of an alternative embodiment of the invention. It illustrates a multi-modulus divider direct digital synthesizer architecture  100  in accordance with aspects of the present invention. The architecture  100  includes many of the same components as the architecture of  FIG. 1 , which operates in the manner discussed above. For instance, the reference oscillator  12  produces a waveform with a frequency f OSC . In the present embodiment the reference oscillator  12  also includes a frequency offset control function f osc  Offset that causes the frequency f OSC  of its output signal to be shifted by a given amount (e.g. 2%). The architecture  100  also includes the multi-modulus programmable divider  14 , programmable NCO  16 , and delay generator circuit  18 . 
   As shown in  FIG. 6 , the architecture  100  preferably also includes two programmable binary dividers  102  and  104 , a programmable modulus control inverter  106 , and a temperature sensing unit such as digital thermometer  108 . The digital thermometer  108  may receive a signal Tmeas.enable as shown in the figure. This signal may enable/disable measurement by the thermometer  108 . 
   The reference oscillator frequency f OSC  can be optionally divided using the binary divider  102  to a lower master clock frequency f CLK  to enable lower power consumption but provides cruder delay resolution (i.e. introduces more jitter). The binary divider  102  receives signal f OSC  from the reference oscillator  12  and outputs a signal of frequency f CLK , which is provided to the multi-modulus programmable divider  14  as well as the delay control circuit  26  of delay generator  18 . The binary divider  102  divides down the oscillator frequency f OSC , e.g., by a selectable but fixed integer value (B 1 ) to generate f CLK . This provides reduced power dissipation, as the DDS operates now at a reduced speed, while it also increases the total delay range that must be covered by the phase interpolator. This typically degrades the absolute jitter performance of the phase interpolator because digital-to-time converters, like digital-to-analog data converters tend to have a fixed ratio between the magnitude of the absolute errors and the full scale range doubling the maximum delay which the phase interpolator must provide will, to first order, double the absolute value of the maximum errors in the delay. Note that, in this embodiment, the input into the multi-modulus divider  14  is f clk  and not f osc  (as in  FIG. 1 ). In this embodiment f clk  is optionally input into delay control  26 . 
   The multi-modulus divider  14  is preferably synchronous with the reference oscillator  12 . As discussed above with regard to  FIG. 1 , the output of the multi-modulus divider  14  is signal V P . The parameters B 1  of the binary divider  102  and P set  of the multi-modulus divider  14  are used to set a coarse frequency range for V P , which also is the operational frequency of the delay generator  18 . The frequency of V P  is related to f OSC  as follows:
 
 F   Vp   =f   OSC /(2 B1   P   set )= f   CLK   /P   set   (8)
 
where P set  can be P or P+1 as determined by the modulus control signal MC. The setting of B 1  effectively enables a trade-off between noise performance (i.e. jitter) and power consumption.
 
   As shown in  FIG. 6 , input signal K is provided to the accumulator  20  of NCO  16 . K is composed of a K Fset  word along with an additional correction value K FC  originating from the digital thermometer. As explained above, the resulting increment K is used to determine the rate of overflows and subsequently defines how many V P  pulses are counted by the programmable divider  18 . The output A of accumulator  20  is a delay value D (n)  and an overflow signal. A latching circuit such as a bank of N A +1 data flip-flops (“D-FF”)  22  in the NCO  16  updates the output value of the accumulator  20 , shown as signal A at specified intervals. The accumulator output values A (i.e. the phase delay values) are optionally truncated into values D which are provided to delay control circuit  26  of the delay generator  18  along with an overflow signal OVF, the master clock signal f CLK  and optionally the signal V P . As previously noted, it is advantageous, but not required, to provide V P  and the signal input into the multi-modulus divider (f CLK  in  FIG. 6 ) to synchronize the delay generator to the V P  pulse. 
   As shown, V P  is also provided to the delay generator circuit  18 . The delay control  26  uses the accumulated value D and OVF f CLK  to perform delay generation on V P  and to output a resultant signal V D , which is a corrected V P  signal. Delay control  26  uses optional inputs f clk  and V P  to synchronize the delay generator with V P . V D  is provided to the binary divider  104 . As with the binary divider  102 , an input to the binary divider  104 , B 2 , may be a user-specified or predetermined input that sets the binary division ratio at the output of the delay generator  18 . The binary division ratio is controlled through a B 2  programming word supplied to the binary divider  104 . A buffer  110  may be employed to isolate the operation of the DDS from a variety of external loads (not shown). The resultant output is a signal f OUT . 
   As discussed above, coarse adjustments of the output frequency can be primarily determined through programming words to the binary frequency dividers  102  and  104 . This range of frequencies is also governed by the range of values for P set  in the multi-modulus P/(P+1) divider  14 . To those skilled in the art it is obvious that if the selected range of possible P/(P+1) values spans an octave, i.e., max(P set )&gt;2*min(P set ), in combination with a programmable binary divider such as B 2 , the system can yield a multi-octave output frequency (f OUT ) coverage. While programmable dividers  102  (B 1 ) and  104  (B 2 ) are not required to be binary, the use of other integer dividers require more power consumption and do not provide for duty cycle correction. 
   Additional frequency control can be had through the configuration of the divider modulus control polarity MCpolarity applied to the programmable modulus control inverter  106 . In the previous embodiments (MC p =0) it has been assumed that an overflow OVF condition causes the dual modulus divider to divide by P+1. In this case, the output frequency in the architecture of  FIG. 6  is given by the following relationship:
 
 f   OUT   =f   OSC /2 B1 *1( P+K/ 2 N     A   )/2 B2   (9)
 
If MCpolarity is set so that during regular NCO increments the multi-modulus divider  14  divides by P+1 and during overflows it divides by P (MC p =1) then the output frequency is:
 
 f   OUT   =f   OSC /2 B1 *1/( P+ 1 −K/ 2 N     A   )/2 B2 .  (10)
 
This configuration also requires that the delay compensation word is bit inverted (i.e. D MCp=1 =1−D MCp=0 ) So that maximum delay settings correspond to pulses resulting from division by P+1. The frequency coverage dependence on the MCpolarity signal is illustrated in  FIG. 8B .
 
   Fine adjustment of the output frequency is controlled by K as explained above. The increment word K of word length N K  is input to the NCO accumulator  20  and determines how fast the accumulator output A advances for each clock pulse V P  generated by the programmable multi-modulus divider  14 . Depending on the application, the increment K can be fixed at K Fset  producing a fixed output frequency or can be dynamically adjusted producing phase or frequency deviations of the output signal. 
     FIG. 6  shows the increment K as a sum of the programming words K Fset  and K FC  with word lengths N Fset  and N FC , respectively. While K Fset  is one-time programmed during the manufacturing process to determine the nominal output frequency f OUT,nom , the frequency correction word K FC  is updated periodically to correct the output frequency for possible drifts of f OSC  due to temperature fluctuations as measured by the thermometer  108 . The intermittently-operated thermometer  108  may include an accurate temperature sensor, an analog-to-digital converter and a numerical circuit that produces a supplementary correction value that modifies the effective synthesizer division ratio as follows:
   f   OSC   /f   OUT =2 B1+B2 *( P+[K   FSet   +K   FC ]2 N     A   )  (11) 
If f OSC  drifts due to a difference in temperature by an amount Δf OSC  then the output frequency will also drift as follows:
   f   OUT   +Δf   OUT =( f   OSC   +Δf   osc )*2 −(B1+B2) /( P+[K   Fset   +K   FC ]/2 N     A   )  (12) 
To eliminate the output drift the correction increment should be:
   K   FC   =Δf   OSC   /f   OSC *( P* 2 N     A     +K   Fset )  (13) 
A variety of temperature-to-increment converters and drift correction mechanisms can be implemented in this block.
 
   Alternatively, K Fset  can be dynamically adjusted according to a phase modulation word (not shown) to produce an output signal featuring continuously variable phase and/or frequency. In this case, a separate phase modulation controller would be inserted at the K Fset  input of the adder before the NCO  16 . 
     FIG. 7   a  shows an exemplary frequency plot for a preferred embodiment with B 1 =1, B 2 =1, and P having values of 2, 3 and 4. Also f OSC =2000 MHz and N A =10. It can be easily seen that no gaps in f our  coverage (a range of about 500 MHz to 1000 MHz) exist as P transitions through various values. It should also be understood that these values for B 1 , B 2 , P, f OSC  and N A  are merely illustrative and do not limit the scope of the invention. 
     FIG. 7   b  shows another exemplary frequency plan for a preferred embodiment with B 1 =1, B 2 =1 and 2, and P=2, 3 and 4. And as with  FIG. 7   a , f OSC =2000 MHz and N A =10. It can be easily seen that the output coverage (a range of about 250 MHz to 1000 MHz) is expanded by an additional factor of 2 by setting the output divider to divide by 2 (i.e., when B 2 =2). 
     FIG. 8   a  illustrates the use of the oscillator offset function f OSC Offset. This setting shifts the frequency of the reference oscillator f OSC  by a small amount (e.g. less than ˜2%) and may be programmed during the manufacturing of the product. It can be easily seen that this option can enable alternative output frequency coverage around the boundary frequencies for different P divider settings. 
     FIG. 8   b  illustrates the effects of the MCpolarity setting in the frequency selection. The output frequency is plotted against the normalized K value for both configurations of the MC polarity. It can be easily seen that one curve is the inverse of the other. As the two MC polarity settings configure both the programmable divider and the delay generator in complementary ways, they provide diversity in selecting the output frequency. 
     FIG. 9  is a schematic illustration of an alternate embodiment of the invention. It illustrates a multi-modulus divider direct digital synthesizer architecture  200 , which incorporates many of the elements shown and described with regard to  FIGS. 1 and 8 .  FIG. 11  further includes a Pseudo-Random Noise (“PRN”) generator  202  that produces a dynamically variable (dithering) accumulator increment. This in turn results in a phase-dithered output delay word that applies a controlled noise-like phase correction to the VP signal. This noise-like phase addition “frequency-spreads” any discrete spurious signals and thus reduces their amplitude. The coherence of the f OUT  instantaneous frequency fluctuations is reduced by this random jitter process that also features a zero-mean. The PRN generator is clocked by the VP signal and has a word length N PRN  of a few least significant bits of the word length N A . One skilled in the art is aware of different approaches for the construction of PRN generators. One example is a linear code sequence generator that can be made up of any set of delay elements in conjunction with linear combining elements in a feedback path such that the number of states the generator can assume is a function of the length (in time) of the delay elements and the particular combination of feedback. These structures are referred to as Linear Feedback Shift Registers (LFSR). One skilled in the art can readily integrate such structures into a circuit. The resulting pseudo-random instantaneous output frequency jumps are as shown below:
   f   OUT ( n )= f   OSC *2 −(B1+B2) /( P+[K   Fset   +K   PRN ( n )]/2 N     A   )  (14) 
where f OUT  (n) is the output frequency at the n th  V P  instant and K PRN (n) is the dithering PRN increment issued by the PRN generator  202 .
 
     FIG. 10  depicts an alternate embodiment of the circuit of  FIG. 9 , in which the PRN phase increment is added at the output of the NCO  16 . The adder  203  sums delay value Di and KPRN to supply the output D O  along with the summation overflow bit OVF D  to the delay control block  26 . 
   Other dithering schemes are well known to one skilled in the art. One such example is described in U.S. Pat. No. 4,410,954 entitled “Digital frequency synthesizer with random jittering for reducing discrete spectral spurs,” which issued on Oct. 18, 1983 and is hereby incorporated by reference. 
   Another application where the increment K is also modulated in a controlled fashion is in “spread-spectrum” clocks to enable the suppression of Electro-Magnetic Interference (“EMI”) products in noise sensitive applications. The difference with the PRN increment dithering described above is that spread spectrum clock oscillators spread out the concentrated clock energy on their nominal output frequency to a broader bandwidth and controlled frequency range (e.g. ˜1% of the output frequency). The total energy remains the same but the peak energy is spread out to near-by frequencies. It can be easily seen that spurious-randomization application dithers the K increment by small amounts (e.g. within a few LSB&#39;s of A), while reduced-EMI spread spectrum applications vary the K increment by much larger amounts (e.g. to result in ˜0.5% to ˜5% f OUT  variations). The embodiments illustrate in  FIGS. 9 and 10  can also implement spread-spectrum PRN functions but it is advantageous if frequency deviations do not exceed the allowed range of values of the K/2 N     A    ratio. 
   Thus, it can be seen that the output frequency f OUT  for architectures implementing aspects of the present invention is dependent upon a number of parameters, including the reference oscillator frequency, the two binary divider ratios B 1  and B 2 , the dual modulus divider ratio P, the increment associated with the accumulator, and the settings for the P modulus control polarity configuration and the f OSC  offset setting. 
     FIG. 10  is a schematic illustration of another alternate embodiment  300  of the invention. It illustrates a multi-modulus divider direct digital synthesizer architecture in accordance with aspects of the present invention also shown in  FIGS. 1 and 6  and  9 . The only difference between the embodiments of  FIG. 9  and  FIG. 10  is the point where the dithering from the PRN generator  202  is inserted. The PRN  202  output is now added to the holding circuit  22  input, instead of the accumulator  20  input. The PRN word length N PRN  is much smaller than the accumulator input/NCO output word length N A . It should be noted that after the PRN addition, the word length is truncated back to N A . Embodiment  300  also includes a Pseudo-Random-Generator  202  output added to the accumulator output. This embodiment can be more suitable for the purposes of further reduction in spurious signals than the embodiment illustrated in  FIG. 9 . 
     FIG. 10  is a schematic illustration of another alternate embodiment  300  of the invention. This embodiment addresses the use of the invention when temperature, spread spectrum frequency modulation, and external modulation inputs added together could cause the value of normalized K to move above its maximum value (1) or below its minimum value (0). In such applications a problem is created when the nominal value of K must be selected near its maximum or minimum value in order to set the output frequency to its desired value. To understand this problem, consider that the maximum output frequency for the architecture in  FIG. 1  is f osc /P min  (the oscillator frequency over the minimum value of P) and the highest frequency of the output is f osc /(P max +1) (the oscillator frequency over 1+the maximum value of P). By selecting the appropriate value of P and K, any arbitrary frequency between these two limits can be selected. However, the value of P and K that give a frequency are unique since K can only represent a fraction (less than 1) of an oscillator period, T osc . Therefore, some possible output frequencies will require the normalized value of K to be near 0 or near 1. If temperature correction terms, external modulation terms, or spread spectrum modulation terms are added to K, the ratio K/2 N     A    would need to exceed the limits of 0 or 1 and the loop would fail to operate correctly. The discussion of  FIG. 8   a  describes a method to keep the normalized value of K from being too close to either end of the (0, 1) range by pulling the oscillator frequency when K Fset  falls too close to a limit moving the nominal value of K further from the limit. 
     FIG. 11  illustrates an improved structure and method for achieving this result. Instead of requiring a change in the oscillator frequency, which may compromise the oscillator&#39;s performance as a frequency reference,  FIG. 11  extends the allowed normalized range of K to be from 0-2 oscillator periods instead of the 0-1 oscillator period range provided by the architecture in  FIG. 1 . 
   The embodiment in  FIG. 11  operates in a way that is similar to the embodiment in  FIG. 1  except that the division modulus of the multi-modulus divider  14 ′ is now controlled by both the overflow signal OVF (MC 1 ) (which is like the OVF from  FIG. 1 ) and the MSB (MC 0 ) instead of just using the OVF pulse as in the embodiment illustrated in  FIG. 1 . Also, only the N A −1 lower bits from the NCO output word are used for delay compensation and feedback to the accumulator input. For example, for the embodiment in  FIG. 1 , when the phase accumulator  20  output is 16 bits, 1 bit (OVF) is fed to the multi-modulus divider  14 ′ and retired and the remaining 15 bits are added to K in the accumulator  20  to form the next accumulator  20  output. In  FIG. 1 , K is also a 15 bit binary word (i.e., it ranges from 1 up to 32,767); therefore, the sum of K and the 15 bit fed back remainder is a 16 bit word that can take on all possible 16-bit values, 0-65,535. In the embodiment in  FIG. 11 , the range of allowed increments is increased 2-fold compared to the fed-back remainder (i.e. N K =N A ). The sum of a 15 bit remainder and a 16 bit K is a 17 bit word that ranges from 0-98,303. By increasing to a triple modulus divider P, (e.g., P, P+1, P+2), the two-bit overflow signal (MC 1  and MC 0 ) pulses are used to select the modulus while the same 15 bit remainder is returned for accumulation in the next period. As in the embodiments described above, a portion of this word is also used for the (n+1) th  instance delay compensation of the multi-modulus divider output pulse. It should be obvious that this concept can be extended to higher order modulus dividers (e.g., P, P+1, P+2, P+3 etc.) in a straightforward manner by simply using more of the MSBs of the accumulator output as part of the OVF signal to control the multi-modulus divider and returning only the remaining accumulator output bits to form the remainder to be accumulated in the next period. 
   Operationally, the formula for the output frequency of the embodiment in  FIG. 13  is:
 
 f   OUT   =f   OSC /( P+ 2 *K/ 2 N     A   )  (15)
 
where f OSC  is the reference oscillator frequency, P is the base value of the P/P+1/P+2 multi-modulus programmable divider, K is the increment and N A =N K  is the increment word length. Since K can range from 0 to 2 N   A   −1 , f OUT  can range from (f OSC /2 B1+B2 )/P to (f OSC /2 B1+B2 )/(P+2−1/2 N     A   ). At the nominal center frequency, the ratio 2K/2 N     A    would be centered around 1 and set to range from 0.5 to 1.5 in order to select any desired frequency in the range around f osc /(P+1). Note, the advantage of  FIG. 11  over  FIG. 1  is the added redundancy. There are now two values of P and K that can be used to create any specific frequency. The added degree of freedom is what makes it possible to avoid selecting a nominal value of K near either end of its allowed range. In the specific case of a triple modulus programmable divider DDS, having the normalized 2K/2 N     A    range from 0.5-1.5 allows the selection of all possible frequencies with the appropriate selection of P. And, this allows any dynamic components (e.g., temperature compensation, external modulation, spread spectrum modulation, etc.) to vary the overall output period by up to +/−0.5 of a reference oscillator period before the minimum or maximum value of K is exceeded. If larger dynamic components need to be accommodated, a higher modulus programmable divider can be employed and the range of K can be further increased.
 
     FIG. 12   a  illustrates the operation of the triple modulus DDS with P=4, f OSC =2 GHz, N A =N K =4, K=11 and N D =3.  FIG. 12   b  shows the Modulus control truth table of the multi-modulus divider for values of MC 0  and MC 1  and  FIG. 12   c  shows the P division cycle count and the output pulse period for all possible increments of a 4 bit word. 
     FIG. 13  shows an embodiment using the circuit architecture of  FIG. 11  with elements of the embodiment of  FIG. 9 . For instance, it includes a P, P+1, P+2 multi-modulus divider  14 ′ controlled by both the overflow OVF and the MSB as well as a spreading generator  202 . The output frequency four is given by the following relationship:
   f   OUT =( f   OSC /2 B1+B2 )*(1/ P+[KF   set   +K   SS ( n )]/2 N     A   ))  (16) 
where f OUT(n)  is the output frequency at the nth V P  instant and KSS(n) is the spreading fractional increment issued by the spreading generator ( 202 ). One skilled in the art is aware of several different approaches for the effective spreading sequence that is provided by the spread generator ( 202 ). Examples include a predetermined noise generation pattern as described above, a linear deterministic function or other deterministic function (e.g. a “Hershey Kiss” function).
 
     FIG. 14  shows a variation of the embodiments of  FIGS. 11 and 13  in which the spreading word K SS  is added at the output of the accumulator, in a fashion similar to the embodiment of  FIG. 10 .