Patent Publication Number: US-9432022-B2

Title: Wide-range level-shifter

Description:
TECHNICAL FIELD 
     This application relates to level-shifters, and more particularly to a wide-range level-shifter. 
     BACKGROUND 
     As semiconductor technology has advanced into the deep submicron regime, the power supply, voltage is scaled down in concert with the scaling down of transistor dimensions. For example, microprocessors are now manufactured with transistors powered by a sub-one volt power supply voltage. But these modern systems may need to interface with peripheral devices such as memories that operate on higher supply voltages. The signal flow from the low-voltage domain to the high-voltage domain requires a shift up in voltage. Conversely, the signal flow from the high-voltage domain to the low-voltage domain requires a shift down in voltage. A conventional level-shifter  100  is shown in  FIG. 1  that may perform such voltage level shifts between an input signal (IN) and an output signal (OUT). In this embodiment, the input signal is a low-voltage-domain (VDDL) signal whereas the output signal is a high-voltage-domain (VDDH) signal. However, level-shifter  100  is readily modified to instead shift down in voltage. 
     The input signal drives a gate of an NMOS transistor MN 1 . If the input signal is low (ground or VSS), transistor MN 1  switches off, allowing a node N 1  to float. The input signal also drives an inverter INV that produces an inverted input signal that in turn drives a gate of an NMOS transistor MN 2 . Inverter INV is powered by a power supply node providing the low-voltage-domain power supply voltage VDDL. Thus, inverter INV will charge the gate of transistor MN 2  to VDDL when the input signal is low, which switches on transistor MN 2  to pull node N 2  to ground. 
     Node N 2  couples to a gate of a PMOS transistor MP 1  that has its drain coupled to node N 1 . Transistor MP 1  is cross-coupled with a PMOS transistor MP 2 . The input signal also drives a gate of a PMOS transistor MP 3  in series with transistor MP 1 . When the input signal is low, both transistors MP 3  and MP 1  will be on, which charges node N 1  to a high-voltage-domain power supply voltage VDDH. Node N 1  drives the gate of transistor MP 2  coupled to node N 2 . Transistor MP 2  will thus be off when the input signal is low. Another PMOS transistor MP 4  that has its gate driven by the inverted input signal is in series with transistor MP 3 . 
     In response to the input signal switching high to VDDL, transistor MN 1  will switch on and transistor MN 2  will switch off. Output node N 2 , which had been discharged while the input signal was low, must then float until transistor MP 2  can be switched on. In turn, transistor MP 2  can&#39;t switch on until transistor MN 1  can discharge node N 1 . However, transistor MP 1  is still momentarily on and attempting to keep node N 1  charged, which thus fights with transistor MN 1  discharging node N 1 . Transistor MP 3  is only weakly on because VDDL is effectively a weak zero with regard to VDDH. Transistor MP 3  thus assists transistor MN 1  in terms of discharging node N 1  by restricting the flow of charge to transistor MP 1 . Once node N 1  is discharged, transistor MP 2  will switch on. Since transistor MP 4  will already be on due to the inverted input signal being driven low, the switching on of transistor MP 2  will charge the output signal to VDDH. An analogous struggle occurs between transistors MN 2  and MP 2  when the inverted signal is driven to VDDL in response to the input signal transitioning low. 
     This fight between the NMOS and PMOS transistors in level-shifter  100  may be alleviated by weakening PMOS transistors MP 3  and MP 1  (as well as transistors MP 4  and MP 2 ). But such a weakening adversely affects timing as each PMOS stack MP 3 /MP 1  and MP 4 /MP 2  must also pull up its corresponding node (N 1  or N 2 , respectively) depending upon whether the input signal is high or low. There is thus a minimum amount of strength necessary for the PMOS stacks to meet desired timing requirements. Since the PMOS stacks must be left relatively strong, there is a limit to the voltage range for level-shifter  100 . In that regard, as VDDL drops ever lower at the modern process nodes, transistor MP 3  turns on ever stronger with regard to VDDL functioning as an effective zero in keeping transistor MP 3  on despite the input signal transitioning high to VDDL. This input range for level-shifter  100  is also affected by the process corner. Should level-shifter  100  be manufactured in a process corner that makes NMOS transistors relatively weak compared to the corresponding PMOS transistors, the PMOS/NMOS struggle with regard to discharging node N 1  is aggravated. 
     Accordingly, there is a need in the art for level-shifters with improved input voltage range and operating speed. 
     SUMMARY 
     A level-shifter is provided that includes a pair of cross-coupled PMOS transistors. The level-shifter also includes two PMOS transistor stacks. A first PMOS stack includes a first one of the cross-coupled PMOS transistors and a second one of the stacks includes a second one of the cross-coupled PMOS transistors. 
     The first PMOS stack includes a first weak PMOS keeper transistor that has its gate driven by an input signal and is coupled in parallel with a first PMOS pull-up transistor that is relatively strong in comparison to the first weak keeper transistor. The level-shifter includes a control circuit that controls whether the first pull-up transistor is switched on or off. The second PMOS stack is analogous to the first PMOS stack. In that regard, the second PMOS stack includes a second weak keeper PMOS transistor that has its gate driven by an inverted version of the input signal and is coupled in parallel with a second pull-up PMOS transistor that is relatively strong with respect to the second weak keeper transistor. The control circuit also controls whether the second pull-up transistor is switched on or off. 
     The control circuit controls the first pull-up transistor to be switched on when the first PMOS stack functions to charge a first node to a first power supply voltage in response to the input signal transitioning from a second power supply voltage to ground. Conversely, the control circuit controls the first pull-up transistor to be switched off when the first node is discharged in response to the input signal transitioning from ground to the second power supply voltage. In this fashion, the level-shifter has the advantage of a weak first PMOS stack with regard to discharging the first node yet has the advantage of a strong first PMOS stack with regard to charging the first node to the first power supply voltage. The second power supply voltage may be less than or greater than the first power supply voltage. 
     The control circuit also controls the second pull-up transistor to be switched on when the second PMOS stack functions to charge a second node to the first power supply voltage in response to the input signal transitioning from ground to the second power supply voltage. Conversely, the control circuit controls the second pull-up transistor to be switched off when the second node is discharged in response to the input signal transitioning from the second power supply voltage to ground. In this fashion, the level-shifter has the advantage of a weak second PMOS stack with regard to discharging the second node yet has the advantage of a strong second PMOS stack with regard to charging the second node to the first power supply voltage. These advantageous features may be better appreciated with reference to the following detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a conventional level-shifter. 
         FIG. 2  is a high-level circuit diagram of a wide-range level-shifter in accordance with an embodiment of the disclosure. 
         FIG. 3  is a circuit diagram of a wide-range level-shifter in accordance with an embodiment of the disclosure. 
         FIG. 4  is a timing diagram for various signals within the level-shifter of  FIG. 3  in response to the input signal transitioning from ground to a power supply voltage. 
         FIG. 5  is a timing diagram for various signals within the level-shifter of  FIG. 3  in response to the input signal transitioning from a power supply voltage to ground. 
         FIG. 6  is a flowchart for a method of operation for the level-shifter of  FIG. 2 . 
     
    
    
     Embodiments of the disclosed level-shifter and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. 
     DETAILED DESCRIPTION 
     A level-shifter is provided that offers a PMOS stack that is selectively weakened with regard to an NMOS transistor pulling an internal node low with regard to a first binary transition in the input signal. The PMOS stack is also selectively strengthened when the PMOS stack must charge the internal node high with regard to a complementary second binary transition of the input signal. 
     This selective weakening and strengthening of the PMOS stacks may be better understood with reference to the level-shifter  200  shown in  FIG. 2 . Transistors MN 1 , MN 2 , MP 1 , and MP 2  as well as inverter INV operate as discussed with regard to level-shifter  100 . Their operation will be reviewed again for additional clarity. 
     The input signal (IN) supplied on an input signal node that drives the gate of NMOS transistor MN 1 , which has its source coupled to ground and its drain coupled to node N 1 . If the input signal is low (ground or VSS), transistor MN 1  switches off, allowing node N 1  to float. The input signal also drives an inverter INV that in turn drives a gate of an NMOS transistor MN 2  with an inverted version of the input signal. Transistor MN 2  has its source coupled to ground and its drain coupled to node N 2  that supplies the output signal. Inverter INV is powered by a power supply node providing the low-voltage-domain power supply voltage VDDL. Thus, inverter INV will charge the gate of transistor MN 2  to VDDL when the input signal is low, which switches on transistor MN 2  to pull node N 2  to ground. Conversely, when the input signal is high (VDDL), transistor MN 1  will switch on to pull node N 1  to ground and transistor MN 2  will switch off, allowing node N 2  to float. 
     PMOS transistors MP 1  and MP 2  are cross-coupled with regard to their drains and gates. The drain of transistor MP 1  couples to node N 1  that also couples to the gate of transistor MP 2 . Similarly, the drain of transistor MP 2  couples to node N 2  that also couples to the gate of transistor MP 1 . When node N 1  is discharged, transistor MP 2  will thus switch on. Conversely, transistor MP 1  switches on responsive to node N 2  discharging to ground. Transistors MP 1  and MP 2  are each part of a corresponding PMOS stack. In level-shifter  100 , transistor MP 1  was part of a PMOS stack that also included transistor MP 3 . However, transistor MP 3  of level-shifter  100  is replaced by PMOS transistors MP 3 ′, MP 3 ″, and MP 3 ′″ in level-shifter  200 . Similarly, transistor MP 2  was part of a PMOS stack that also included transistor MP 4 . This transistor MP 4  of level-shifter  100  is replaced by transistors MP 4 ′, MP 4 ″, and MP 4 ′″ in level-shifter  200 . 
     With regard to the transistor MP 1  PMOS stack, transistors MP 3 ′ and MP 3 ″ are in series between a power supply node providing VDDH and a source for transistor MP 1 . The source of transistor MP 3 ′ couples to a power supply node providing VDDH and its drain couples to a source for transistor MP 3 ″. The drain of transistor MP 3 ″ couples to a source of transistor MP 1 . The input signal drives the gates of transistors MP 3 ′ and MP 3 ″ analogously to how the input signal drives the gate of transistor MP 3  in level-shifter  100 . Both transistors MP 3 ′ and MP 3 ″ are relatively weak in comparison to transistor MP 1 , which is relatively strong in comparison to transistors MP 3 ′ and MP 3 ″. By being coupled in series, transistors MP 3 ′ and MP 3 ″ are the equivalent of a single, even weaker PMOS transistor. Recall that one solution to extending the voltage range of level-shifter  100  was to weaken transistor MP 3 . Transistors MP 3 ′ and MP 3 ″ thus function as this desirable weakening of transistor MP 3  to prevent the node N 1  discharge struggle discussed with regard to level-shifter  100 . Despite this PMOS stack weakening, level-shifter  200  does not suffer the delays that would vex operation of level-shifter  100  if its transistor MP 3  were weakened to increase its input voltage range as will be explained further herein with regard to the operation of transistor MP 3 ′. 
     Given the weakness of transistors MP 3 ′ and MP 3 ″, transistor MN 1  in level-shiner  200  may thus discharge node N 1  relatively quickly in response to the input signal transitioning high to VDDL—despite transistors MP 3 ′ and MP 3 ″ being switched weakly on. But level-shifter  200  does not suffer from timing delays due to the weakness of transistors MP 3 ′ and MP 3 ″ because of the relative strength of transistor MP 3 ′″, which is coupled in parallel to the series stack of transistors MP 3 ′ and MP 3 ″. The source of transistor MP 3 ′″ couples to a power supply node providing VDDH and its drain couples to the source of transistor MP 1 . A control signal C 1  drives the gate of transistor MP 3 ′″. A control circuit  205  discussed further below generates control signal C 1  responsive to binary transitions of the input signal such as sensed on nodes N 1  and N 2 . Because transistor MP 3 ′″ functions to charge node N 1 , it is also denoted herein as a pull-up transistor. In contrast, transistors MN 1  and MN 2  may be denoted as pull-down transistors since they function to discharge nodes N 1  and N 2 , respectively. 
     Because pull-up transistor MP 3 ′″ is relatively strong, control signal C 1  is generated by control circuit  205  so that pull-up transistor MP 3 ′″ is off when the input signal transitions high to VDDL. In that regard, control signal C 1  is a VDDH-domain signal such that pull-up transistor MP 3 ′ is fully off when control signal C 1  is driven high to VDDH. In this fashion, pull-up transistor MP 3 ′″ does not struggle with transistor MN 1  when transistor MN 1  functions to pull node N 1  to ground. Note that transistors MP 3 ′ and MP 3 ″ are weakly on when the input signal is high and transistor MP 3 ′″ is off Transistors MP 3 ′ and MP 3 ″ function as weak keeper transistors that keep the drain of pull-up transistor MP 3 ′ charged to VDDH. In this fashion, there is no leakage current through pull-up transistor MP 3 ′″ when transistor MP 3 ′″ is off. 
     As will be explained further herein, control circuit  205  drives control signal C 1  low in response to the input signal transitioning high to VDDL. Pull-up transistor MP 3 ′″ then switches on so that it may then quickly charge node N 1  to VDDH when cross-coupled transistor MP 1  is switched on responsive to a subsequent transition of the input signal low to ground. Cross-coupled transistor MP 1  is also relatively strong so that the serial combination or stack of pull-up transistor MP 3 ′″ and cross-coupled transistor MP 1  can quickly charge node N 1  to VDDH. Control circuit  205  also drives control signal C 1  high to VDDH responsive to the input signal transitioning low. In this fashion, pull-up transistor MP 3 ′″ will be fully off and will not struggle with pull-down transistor MN 1  at a subsequent high transition of the input signal. 
     Transistors MP 4 ′, MP 4 ″, and MP 4 ′″ function analogously. Transistor MP 4 ′″ may thus be denoted as a pull-up transistor whereas transistors MP 4 ′ and MP 4 ″ function as weak keeper transistors. The source of transistor MP 4 ′ couples to a power supply node for providing VDDH and its drain couples to a source of transistor MP 4 ″. The drain of transistor MP 4 ″ couples to a source for cross-coupled transistor MP 2 . The inverted version of the input signal from the inverter INV drives the gates of keeper transistors MP 4 ′ and MP 4 ″. When the input signal transitions low such that its inverted version transitions high to VDDL, keeper transistors MP 4 ′ and MP 4 ″ will be only weakly switched on. The serial combination of keeper transistors MP 4 ′ and MP 4 ″ is even weaker such that pull-down transistor MN 2  can thus quickly discharge node N 2  despite relatively-strong cross-coupled transistor MP 2  being initially on at the transition of the input signal low since cross-coupled transistor MP 2  is starved of charge due to the weakness of keeper transistors MP 4 ′ and MP 4 ″. Pull-up transistor MP 4 ′″ couples in parallel with the serial combination of keeper transistors MP 4 ′ and MP 4 ″. The source of pull-up transistor MP 4 ′″ thus couples to a power supply node providing VDDH whereas its drain couples to the source of cross-coupled transistor MP 2 . Control circuit  205  generates a control signal C 2  that drives the gate of pull-up transistor MP 4 ′″ responsive to binary transitions of the input signal such as sensed on nodes N 1  and N 2 . 
     Pull-up transistor MP 4 ′″ is relatively strong in comparison to keeper transistors MP 4 ′ and MP 4 ″. Thus, control circuit  205  drives control signal C 2  high to VDDH responsive to the input signal transitioning high to VDDL to prevent pull-up transistor MP 4 ′″ from struggling with pull-down transistor MN 2  with regard to an eventual discharge of node N 2  in response to a subsequent low transition of the input signal (which charges the inverted input signal to VDDL). While pull-up transistor MP 4 ′″ is off, keeper transistors MP 4 ′ and MP 4 ″ function as a weak keeper device that keeps the drain of pull-up transistor MP 4 ′″ charged to VDDH so as to eliminate leakage current across pull-up transistor MP 4 ′″ while it is off. Control circuit  205  drives control signal C 2  low to switch on pull-up transistor MP 4 ′″ in response to the input signal transitioning low so that pull-up transistor MP 4 ′″ may assist in rapidly charging node N 2  to VDDH when cross-coupled transistor MP 2  is switched on at a subsequent high transition of the input signal. Cross-coupled transistor MP 2  is also relatively strong so that the serial combination of cross-coupled transistor MP 2  and pull-up transistor MP 4 ′″ may quickly charge node N 2  to VDDH. In this fashion, level-shifter  200  has the advantage of weak PMOS stacks when discharging either of nodes N 1  and N 2  yet has strong PMOS stacks with regard to charging these nodes. 
     A level-shifter  300  of  FIG. 3  shows an example embodiment for control circuit  205 . In particular, control circuit  205  comprises PMOS transistors MP 5 , MP 6 , MP 7 , and MP 8  as well as NMOS transistors MN 3  and MN 4 . The following discussion will also reference  FIGS. 4 and 5 .  FIG. 4  diagrams the response of node N 1 , node N 2 , control signal C 1 , and control signal C 2  in level-shifter  300  for a transition of the input signal from low (VSS) to high (VDDL). Conversely,  FIG. 5  illustrates the same signals for level-shifter  300  in response to a transition of the input signal from high to low. The structure of control circuit  205  will first be described followed by a discussion of its function with regard to these binary transitions of the input signal. 
     Node N 1  couples to the gate of transistors MN 4  and MP 8 . The source of transistor MN 4  couples to ground and its drain couples to the drain of transistor MP 8 . The source of transistor MP 8  couples to the drain of transistor MP 5 , which in turn has its source coupled to a power supply node providing VDDH and has its gate driven by control signal C 1 . The voltage at the drain of transistor MN 4  (as well as the drain of transistor MP 8 ) functions as control signal C 2  that drives the gates of pull-up transistor MP 4 ′″ and transistor MP 6 . As will be explained further herein, transistor MN 4  functions to discharge control signal C 2  and thus is also designated herein as a pull-down transistor. Conversely, transistor MP 8  functions to charge control signal C 2  to VDDH and thus is designated herein as a pull-up transistor. 
     Transistors MP 7  and MN 3  have their gates driven by node N 2 . The source of transistor MN 3  couples to ground and its drain couples to the drain of transistor MP 7 . In turn, the source of transistor MP 7  couples to the drain of transistor MP 6 . The drain voltage for transistors MP 7  and MN 3  functions as control signal C 1 , which not only drives the gate of transistor MP 5  but also drives the gate of pull-up transistor MP 3 ′″. Analogous to transistor MN 4 , transistor MN 3  is also designated herein as a pull-down transistor in that it functions to discharge control signal C 1 . Similarly, transistor MP 7  is also designated herein as a pull-up transistor in that it functions to charge control signal C 1  to VDDH. Transistor MP 6  is analogous to transistor MP 5  in that transistor MP 6  has its source tied to the VDDH power supply node and its gate is driven by control signal C 2 . Both transistors MP 5  and MP 6  function as switches that are controlled by control signals C 1  and C 2 , respectively. Node N 1  couples to the gate of cross-coupled transistor MP 2 . Similarly, node N 2  couples to the gate of cross-coupled transistor MP 1 . 
     Given this structure for control circuit  205 , the transition of the input signal from low to VDDL will first be discussed as diagrammed in  FIG. 4 . Prior to the high transition of the input signal, node N 1  would have been charged high to VDDH. This high voltage on node N 1  thus switches on pull-down transistor MN 4  such that its drain and control signal C 2  are grounded prior to the high transition of the input signal. The output signal (which is the same as the node N 2  voltage) was low prior to the high transition of the input signal. Thus, pull-up transistor MP 7  is on at that time. Since control signal C 2  is also low prior to the high transition of the input signal, pull-up transistor MP 7  and transistor MP 6  are both on while the input signal is low, which charges control signal C 1  high. Thus, pull-up transistor MP 3 ′″ is off prior to the input signal transitioning to VDDL. Conversely, pull-up transistor MP 4 ′″ is on prior to the high transition of the input signal. 
     When the input signal transitions high, the switching on of pull-down transistor MN 1  readily discharges node N 1  since pull-up transistor MP 3 ′″ is off. Cross-coupled transistor MP 2  is then switched on and pull-down transistor MN 2  switched off. Since cross-coupled transistor MP 2  and pull-up transistor MP 4 ′″ are then both switched on, node N 2  and the output signal are quickly charged to VDDH as node N 1  is discharged. In turn, the charging of node N 2  switches on pull-down transistor MN 3  and switches off pull-up transistor MP 7 . Control signal C 1  is then discharged in anticipation of a subsequent transition of the input signal low as discussed below with regard to  FIG. 5 . The discharge of node N 1  switches on pull-up transistor MP 8  and switches off pull-down transistor MN 4 . Pull-up transistor MP 8  and transistor MP 5  are then both conducting such that control signal C 2  is driven high to VDDH, which shuts off pull-up transistor MP 4 ′″. In this fashion, pull-up transistor MP 4 ′″ won&#39;t struggle with pull-down transistor MN 2  for a subsequent low transition of the input signal. 
     When the input signal transitions low as diagrammed in  FIG. 5 , pull-down transistor MN 2  is switched on and pull-down transistor MN 1  switched off. Since pull-up transistor MP 4 ′″ is off at this time, node N 2  is quickly discharged to ground. Cross-coupled transistor MP 1  then switches on. Since pull-up transistor MP 3 ′″ was on prior to the discharge of node N 2 , switched-on pull-up transistor MP 3 ′″ and cross-coupled transistor MP 1  quickly charge node N 1  to VDDH. The charging of node N 1  switches on pull-down transistor MN 4  and switches off pull-up transistor MP 8  so that control signal C 2  is discharged. Conversely, the discharge of node N 2  switches on pull-up transistor MP 7  and switches off pull-down transistor MN 3 . Transistor MP 6  is switched on responsive to the discharge of control signal C 2  so that the combination of transistor MP 6  and pull-up MP 7  then charge control signal C 1  high to VDDH. The high state of control signal C 1  then shuts off pull-up transistor MP 3 ′″. 
     When the input signal subsequently switches high to VDDL, pull-down transistor MN 1  can thus quickly discharge node N 1  since this discharge is countered only by the weakly-switched-on combination of keeper transistors MP 3 ′ and MP 3 ″. In that regard, transistors MN 3 , MN 4 , MP 5 , MP 6 , MP 7 , and MP 8  that comprise control circuit  205  are all relatively strong. The discharge of node N 1  causes transistors MP 2  and MP 8  to switch on and also causes transistor MN 4  to switch off. Transistors MP 5  and MP 8  then charge control signal C 2  high to VDDH, which shuts off transistors MP 4 ′″ and MP 6 . 
     After the low transition of the input signal, control circuit  205  thus operates to keep control signals C 1  and C 2  in their previous state until node N 1  is charged and node N 2  discharged. Control circuit  205  then responds to the binary transitions of the node N 1  and N 2  voltages to flip the binary state of the control signals C 1  and C 2 . Control signal C 2  is thus discharged so that node N 2  can be quickly charged at the subsequent high transition of the input signal. Conversely, control signal C 1  is charged to VDDH so that pull-up transistor MP 3 ′″ will not struggle with pull-down transistor MN 1  when pull-down transistor MN 1  discharges node N 1  at the subsequent transition of the input signal to VDDH. 
     Control circuit  205  operates in an analogous fashion during the high transition of the input signal. Control signals C 1  and C 2  thus are momentarily maintained in their previous state until node N 1  is discharged and node N 2  is charged. After the discharge of node N 1 , control circuit  205  charges control signal C 2  so that pull-down transistor MP 4 ′″ is then turned off. But transistor MP 4 ′″ was on long enough after the high transition of the input signal to quickly charge node N 2  to VDDH. Control circuit  205  then responds to the charging of node N 2  by discharging control signal C 1  so that pull-up transistor MP 3 ′″ is then turned on so that it may assist in a charging of node N 1  responsive to a subsequent low transition of the input signal. But this switching on of pull-up transistor MP 3 ′″ occurs after node N 1  is already discharged so that there is no struggle with regard to the discharge of node N 1 . The net result is that level-shifter  300  of  FIG. 3  achieves the conflicting goals of having weak PMOS stacks with regard to the discharging of nodes N 1  and N 2  yet also having strong PMOS stacks with regard to the charging of nodes N 1  and N 2 . In this fashion, level-shifter  300  may have a wide input signal voltage range such that the VDDL may be dropped to low levels (for example, 0.6 V or less) yet high-speed and accurate operation is achieved. Moreover, this performance may be guaranteed across all expected process corners. 
     A method of operation for level-shifter  300  will now be discussed.  FIG. 6  is a flowchart of an example method of operation. A step  600  comprises discharging an output signal responsive to an input signal transitioning from a first power supply voltage to ground. The discharging of the output signal as discussed with regard to  FIG. 5  is an example of such an act. A step  605  comprises switching on a first pull-up transistor responsive to the input signal transitioning from the first power supply voltage to ground. The switching on of pull-up transistor MP 4 ′″ after the input signal transitions low is an example of such an act. A step  610  comprises using the switched-on first pull-up transistor to charge the output signal to a second power supply voltage responsive to the input signal transitioning from ground to the first power supply voltage. The discussion above with regard to pull-up transistor MP 4 ′″ charging the output signal to VDDH (in conjunction with cross-coupled transistor MP 2 ) is an example of such an act. Finally, the method includes a step  615  of after the charging of the output signal, switching off the first pull-up transistor such that the discharging of the output signal responsive to the input signal transitioning to ground is not opposed by the first pull-up transistor. The charging of control signal C 2  through pull-up transistor MP 8  in response to the discharging of node N 1  so as to switch off pull-up transistor MP 4 ′″ as discussed with regard to level-shifter  300  is an example of such an act. 
     As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the spirit and scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.