Patent Publication Number: US-6658015-B1

Title: Multiport switch with plurality of logic engines for simultaneously processing different respective data frames

Description:
TECHNICAL FIELD 
     The present invention relates to network communications and more particularly, to generating data forwarding decisions in a network switch. 
     BACKGROUND ART 
     In computer networks, a plurality of network stations are interconnected via a communications medium. For example, Ethernet is a commonly used local area network scheme in which multiple stations are connected to a single shared serial data path. These stations often communicate with a switch located between the shared data path and the stations connected to that path. Typically, the switch controls the communication of data packets on the network. 
     The network switch includes switching logic for receiving and forwarding frames to the appropriate destinations. One arrangement for generating a frame forwarding decision uses a direct addressing scheme, where the network switch includes a fixed address table storing switching logic for the destination addresses. 
     For example, a frame may be received by the network switch with header information indicating the source address and destination address of the frame. The switching logic accesses the fixed address table using the source address and destination address as lookups to find the appropriate frame forwarding information. The switch then uses this information and sends the frame to the appropriate port(s). 
     When all of the stations connected to the network are simultaneously operating, packet traffic on the shared serial path can be heavy with little time between packets. Additionally, due to increased network throughput requirements, increasing the data throughput is crucial to the overall operation of the switch. 
     One drawback with typical prior art systems employing address tables is that the decision making logic processes data frames one frame at a time. That is, when multiple frames are received by the switch, the decision making logic processes the header information from the first frame and generates the frame forwarding information. The decision making logic then starts the process over again for the second frame. Such a processing arrangement often results in low data throughput. Additionally, prior art arrangements employing address tables typically include a single decision making device that performs all of the processing tasks necessary to generate a frame forwarding decision. A drawback with utilizing a single decision making device is the difficulty in implementing changes in any one part of the decision making process without affecting other parts of the decision making process. Another drawback with typical prior art systems is that the decision making logic is included within a logic device that performs other functions on the switch. Such an arrangement makes changes to the decision making logic difficult to implement without affecting other logic functions on the switch. 
     SUMMARY OF THE INVENTION 
     There exists a need for a switching device that includes a decision making engine designed to support networks requiring a high data throughput. 
     There is also a need for a switching device that employs a modular decision making engine that facilitates changes to the decision making logic. 
     These and other needs are met by the present invention, where a multiport switch includes a decision making engine used to make frame forwarding decisions. The decision making engine is designed in pipelined, modular fashion so that multiple frames may be processed simultaneously. 
     According to one aspect of the invention, a multiport switch is configured to control the communication of data frames between stations. The switch includes a programmable address table for storing address information and data forwarding information. The switch also includes a decision making engine configured to search the programmable address table and generate data forwarding information for a data frame. The decision making engine comprises a plurality of logic engines where each of the logic engines is configured to process a data frame simultaneously with each other logic engine. 
     Another aspect of the present invention provides a method for generating data forwarding information in a multiport switch that controls communication of data frames between stations. The method includes receiving a data frame and processing the data frame in a pipelined manner through a decision making engine. The decision making engine comprises a plurality of logic engines with each of the logic engines configured to process a data frame simultaneously with each other logic engine. The method also includes generating the data forwarding information. 
    
    
     Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a packet switched network including a multiple port switch according to an embodiment of the present invention. 
     FIG. 2 is a block diagram of the multiple port switch of FIG.  1 . 
     FIG. 3 is a detailed block diagram illustrating the switching subsystem of FIG.  2 . 
     FIG. 4 is a block diagram of a system including the internal rules checker of FIG. 2 in accordance with an embodiment of the present invention. 
     FIG. 5 illustrates the composition of the IRC address table of FIG.  4 . 
     FIG. 6 illustrates the format of an IRC address table entry of the IRC address table of FIG.  5 . 
     FIG. 7 illustrates linked list chains for identifying table entries relative to a selected bin. FIG. 8 illustrates a hash function circuit used with the internal rules checker of FIG.  2 . 
     FIG. 9 illustrates the composition of the forwarding descriptor in accordance with an embodiment of the present invention. 
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     The present invention will be described with the example of a switch in a packet switched network, such as an Ethernet (IEEE 802.3) network. It will become apparent, however, that the present invention is also applicable to other packet switched systems, as described in detail below, as well as to other types of systems in general. 
     Switch Architecture Overview 
     FIG. 1 is a block diagram of an exemplary system in which the present invention may be advantageously employed. The exemplary system  10  is a packet switched network, such as an Ethernet (IEEE 802.3) network. The packet switched network includes integrated multiport switches (IMS)  12  that enable communication of data packets between network stations. The network may include network stations having different configurations, for example twelve ( 12 ) 10 megabit per second (Mb/s) or 100 Mb/s network stations  14  (hereinafter 10/100 Mb/s) that send and receive data at a network data rate of 10 Mb/s or 100 Mb/s, and a 1000 Mb/s (i.e., 1 Gb/s) network node  22  that sends and receives data packets at a network speed of 1 Gb/s. The gigabit node  22  may be a server, or a gateway to a high-speed backbone network. Hence, the multiport switches  12  selectively forward data packets received from the network nodes  14  or  22  to the appropriate destination based upon Ethernet protocol. 
     Each multiport switch  12  includes a media access control (MAC) module  20  that transmits and receives data packets to and from 10/100 Mb/s physical layer (PHY) transceivers  16  via respective shared media independent interfaces (MII)  18  according to IEEE 802.3u protocol. Each multiport switch  12  also includes a gigabit MAC  24  for sending and receiving data packets to and from a gigabit PHY  26  for transmission to the gigabit node  22  via a high speed network medium  28 . 
     Each 10/100 Mb/s network station  14  sends and receives data packets to and from the corresponding multiport switch  12  via a media  17  and according to either half-duplex or full duplex Ethernet protocol. The Ethernet protocol ISO/IEC 8802-3 (ANSI/IEEE Std. 802.3, 1993 Ed.) defines a half-duplex media access mechanism that permits all stations  14  to access the network channel with equality. Traffic in a half-duplex environment is not distinguished or prioritized over the medium  17 . Rather, each half-duplex station  14  includes an Ethernet interface card that uses carrier-sense multiple access with collision detection (CSMA/CD) to listen for traffic on the media. The absence of network traffic is detected by sensing deassertion of a receive carrier on the media. Any station  14  having data to send will attempt to access the channel by waiting a predetermined time, known as the interpacket gap interval (IPG), after deassertion of the receive carrier on the media. If a plurality of stations  14  have data to send on the network, each of the stations will attempt to transmit in response to the sensed deassertion of the receive carrier on the media and after the IPG interval, possibly resulting in a collision. Hence, the transmitting station will monitor the media to determine if there has been a collision due to another station sending data at the same time. If a collision is detected, both stations stop, wait a random amount of time, and retry transmission. 
     The 10/100 Mb/s network stations  14  that operate in full duplex mode send and receive data packets according to the Ethernet standard IEEE 802.3u. The full-duplex environment provides a two-way, point-to-point communication link enabling simultaneous transmission and reception of data packets between each link partner, i.e., the 10/100 Mb/s network station  14  and the corresponding multiport switch  12 . 
     Each multiport switch  12  is coupled to 10/100 physical layer (PHY) transceivers  16  configured for sending and receiving data packets to and from the corresponding multiport switch  12  across a corresponding shared media independent interface (MII)  18 . In particular, each 10/100 PHY transceiver  16  is configured for sending and receiving data packets between the multiport switch  12  and up to four (4) network stations  14  via the shared MII  18 . A magnetic transformer  19  provides AC coupling between the PHY transceiver  16  and the corresponding network medium  17 . Hence, the shared MII  18  operates at a data rate sufficient to enable simultaneous transmission and reception of data packets by each of the network stations  14  to the corresponding PHY transceiver  16 . 
     Each multiport switch  12  also includes an expansion port  30  for transferring data between other switches according to a prescribed protocol. For example, each expansion port  30  can be implemented as a second gigabit MAC port similar to port  24 , thereby enabling multiple multiport switches  12  to be cascaded together as a separate backbone network. 
     FIG. 2 is a block diagram of the multiport switch  12 . The multiport switch  12  contains a decision making engine  40  that performs frame forwarding decisions, a switching subsystem  42  for transferring frame data according to the frame forwarding decisions, an external memory interface  44 , management information base (MIB) counters  48   a  and  48   b  (collectively  48 ), and MAC (media access control) protocol interfaces  20  and  24  to support the routing of data packets between the Ethernet (IEEE 802.3) ports serving the network stations  14  and the gigabit node  22 . The MIB counters  48  provide statistical network information in the form of management information base (MIB) objects, to an external management entity controlled by a host CPU  32 , described below. 
     The external memory interface  44  enables external storage of packet data in an external memory  36  such as, for example, a synchronous static random access memory (SSRAM), in order to minimize the chip size of the multiport switch  12 . In particular, the multiport switch  12  uses the external memory  36  for storage of received frame data, memory structures, and MIB counter information. The external memory  36  is preferably either a Joint Electron Device Engineering Council (JEDEC) pipelined burst or Zero Bus Tumaround™ (ZBT)-SSRAM having a 64-bit wide data path and a 17-bit wide address path. The external memory  36  is addressable as upper and lower banks of 128K in 64-bit words. The size of the external memory  36  is preferably at least 1 Mbytes, with data transfers possible on every clock cycle through pipelining. Additionally the external memory interface clock operates at clock frequencies of at least 66 MHz, and, preferably, 100 MHz and above. 
     The multiport switch  12  also includes a processing interface  50  that enables an external management entity such as a host CPU  32  to control overall operations of the multiport switch  12 . In particular, the processing interface  50  decodes CPU accesses within a prescribed register access space, and reads and writes configuration and status values to and from configuration and status registers  52 . 
     The internal decision making engine  40 , referred to as an internal rules checker (IRC), makes frame forwarding decisions for data packets received from one source to at least one destination station. 
     The multiport switch  12  also includes an LED interface  54  that clocks out the status of conditions per port and drives an external LED logic. The external LED logic drives LED display elements that are human readable. 
     The switching subsystem  42 , configured for implementing the frame forwarding decisions of the IRC  40 , includes a port vector first in first out (FIFO) buffer  56 , a plurality of output queues  58 , a multicopy queue  60 , a multicopy cache  62 , a free buffer queue  64 , and a reclaim queue  66 . 
     The MAC unit  20  includes modules for each port, each module including a MAC receive portion, a receive FIFO buffer, a transmit FIFO buffer, and a MAC transmit portion. Data packets from a network station  14  are received by the corresponding MAC port and stored in the corresponding receive FIFO. The MAC unit  20  obtains a free buffer location (i.e., a frame pointer) from the free buffer queue  64 , and outputs the received data packet from the corresponding receive FIFO to the external memory interface  44  for storage in the external memory  36  at the location specified by the frame pointer. 
     The IRC  40  monitors (i.e., “snoops”) the data bus to determine the frame pointer value and the header information of the received packet (including source, destination, and VLAN address information). The IRC  40  uses the header information to determine which MAC ports will output the data frame stored at the location specified by the frame pointer. The decision making engine (i.e., the IRC  40 ) may thus determine that a given data frame should be output by either a single port, multiple ports, or all ports (i.e., broadcast). For example, each data frame includes a header having source and destination address, where the decision making engine  40  may identify the appropriate output MAC port based upon the destination address. Alternatively, the destination address may correspond to a virtual address that the appropriate decision making engine identifies as corresponding to a plurality of network stations. In addition, the frame may include a VLAN tag header that identifies the frame as information destined to one or more members of a prescribed group of stations. The IRC  40  may also determine that the received data packet should be transferred to another multiport switch  12  via the expansion port  30 . Hence, the internal rules checker  40  will decide whether a frame temporarily stored in the external memory  36  should be output to a single MAC port or multiple MAC ports. 
     The internal rules checker  40  outputs a forwarding decision to the switch subsystem  42  in the form of a forwarding descriptor. The forwarding descriptor includes a priority class identifying whether the frame is high priority or low priority, a port vector identifying each MAC port that should receive the data frame, Rx port number, an untagged set field, VLAN information, opcode, and frame pointer. The format of the forwarding descriptor will discussed further with respect to FIG.  9 . The port vector identifies the MAC ports to receive the data frame for transmission (e.g., 10/100 MAC ports 1-12, Gigabit MAC port, and/or Expansion port). The port vector FIFO  56  decodes the forwarding descriptor including the port vector, and supplies the frame pointer to the appropriate output queues  58  that correspond to the output MAC ports to receive the data frame transmission. In other words, the port vector FIFO  56  supplies the frame pointer on a per-port basis. The output queues  58  fetch the data frame identified in the port vector from the external memory  36  via the external memory interface  44 , and supply the retrieved data frame to the appropriate transmit FIFO of the identified ports. If a data frame is to be supplied to a management agent, the frame pointer is also supplied to a management queue  68 , which can be processed by the host CPU  32  via the CPU interface  50 . 
     The multicopy queue  60  and the multicopy cache  62  keep track of the number of copies of the data frame that are fetched from the respective output queues  58 , ensuring that the data frame is not overwritten in the external memory  36  until the appropriate number of copies of the data frame have been output from the external memory  36 . Once the number of copies output corresponds to the number of ports specified in the port vector FIFO  56 , the frame pointer is forwarded to the reclaim queue  66 . The reclaim queue  66  stores frame pointers that can be reclaimed by the free buffer queue  64  as free pointers. After being returned to the free buffer queue  64 , the frame pointer is available for reuse by the MAC unit  20  or the gigabit MAC unit  24 . 
     FIG. 3 depicts the switch subsystem  42  of FIG. 2 in more detail according to an exemplary embodiment of the present invention. Other elements of the multiport switch  12  of FIG. 2 are reproduced in FIG. 3 to illustrate the connections of the switch subsystem  42  to these other elements. 
     As shown in FIG. 3, the MAC module  20  includes a receive portion  20   a  and a transmit portion  24   b . The receive portion  20   a  and the transmit portion  24   b  each include  12  MAC modules (only two of each shown and referenced by numerals  70   a ,  70   b ,  70   c , and  70   d ) configured for performing the corresponding receive or transmit function according to IEEE 802.3 protocol. The MAC modules  70   c  and  70   d  perform the transmit MAC operations for the 10/100 Mb/s switch ports complementary to modules  70   a  and  70   b , respectively. 
     The gigabit MAC port  24  also includes a receive portion  24   a  and a transmit portion  24   b , while the expansion port  30  similarly includes a receive portion  30   a  and a transmit portion  30   b . The gigabit MAC port  24  and the expansion port  30  also have receive MAC modules  72   a  and  72   b  optimized for the respective ports. The transmit portions  24   b  and  30   b  of the gigabit MAC port  24  and the expansion port  30   a  also have transmit MAC modules  72   c  and  72   d , respectively. The MAC modules are configured for full-duplex operation on the corresponding port, and the gigabit MAC modules  72   a  and  72   c  are configured in accordance with the Gigabit Proposed Standard IEEE Draft P802.3z. 
     Each of the receive MAC modules  70   a ,  70   b ,  72   a , and  72   b  include queuing logic  74  for transfer of received data from the corresponding internal receive FIFO to the external memory  36  and the rules checker  40 . Each of the transmit MAC modules  70   c ,  70   d ,  72   c , and  72   d  includes a dequeuing logic  76  for transferring data from the external memory  36  to the corresponding internal transmit FIFO, and a queuing logic  74  for fetching frame pointers from the free buffer queue  64 . The queuing logic  74  uses the fetched frame pointers to store receive data to the external memory  36  via the external memory interface controller  44 . The frame buffer pointer specifies the location in the external memory  36  where the received data frame will be stored by the receive FIFO. 
     The external memory interface  44  includes a scheduler  80  for controlling memory access by the queuing logic  74  or dequeuing logic  76  of any switch port to the external memory  36 , and an SSRAM interface  78  for performing the read and write operations with the external memory  36 . In particular, the multiport switch  12  is configured to operate as a non-blocking switch, where network data is received and output from the switch ports at the respective wire rates of 10, 100, or 1000 Mb/s. Hence, the scheduler  80  controls the access by different ports to optimize usage of the bandwidth of the external memory  36 . 
     Each receive MAC stores a portion of a frame in an internal FIFO upon reception from the corresponding switch port; the size of the FIFO is sufficient to store the frame data that arrives between scheduler time slots. The corresponding queuing logic  74  obtains a frame pointer and sends a write request to the external memory interface  44 . The scheduler  80  schedules the write request with other write requests from the queuing logic  74  or any read requests from the dequeuing logic  76 , and generates a grant for the requesting queuing logic  74  (or the dequeuing logic  76 ) to initiate a transfer at the scheduled event (i.e., slot). Sixty-four bits of frame data is then transferred over a write data bus  69   a  from the receive FIFO to the external memory  36  in a direct memory access (DMA) transaction during the assigned slot based on the retrieved frame pointer. The frame data is stored in the location pointed to by the free buffer pointer obtained from the free buffer pool  64 , although a number of other buffers may be used to store data frames, as will be described. 
     The rules checker  40  also receives the frame pointer and the header information (including source address, destination address, VLAN tag information, etc.) by monitoring (i.e., snooping) the DMA write transfer on the write data bus  69   a . The rules checker  40  uses the header information to make the forwarding decision and generate a forwarding instruction in the form of a forwarding descriptor that includes a port vector. The port vector has a bit set for each output port to which the frame should be forwarded. If the received frame is a unicopy frame, only one bit is set in the port vector generated by the rules checker  40 . The single bit that is set in the port vector corresponds to a particular one of the ports. 
     The rules checker  40  outputs the forwarding descriptor including the port vector and the frame pointer into the port vector FIFO  56 . The port vector is examined by the port vector FIFO  56  to determine which particular output queue should receive the associated frame pointer. The port vector FIFO  56  places the frame pointer into the top of the appropriate queue  58  and/or  68 . This queues the transmission of the frame. 
     As shown in FIG. 3, each of the transmit MAC units  70   c ,  70   d ,  72   d , and  72   c  has an associated output queue  58   a ,  58   b ,  58   c , and  58   d , respectively. In preferred embodiments, each of the output queues  58  has a high priority queue for high priority frame pointers, and a low priority queue for low priority frame pointers. The high priority frame pointers are used for data frames that require a guaranteed access latency, e.g., frames for multimedia applications or management MAC frames. The frame pointers stored in the FIFO-type output queues  58  are processed by the dequeuing logic  76  for the respective transmit MAC units. At some point in time, the frame pointer reaches the bottom of an output queue  58 , for example, output queue  58   d  for the gigabit transmit MAC  72   c . The dequeuing logic  76  for the transmit gigabit port  24   b  takes the frame pointer from the corresponding gigabit port output queue  58   d , and issues a request to the scheduler  80  to read the frame data from the external memory  36  at the memory location specified by the frame pointer. The scheduler  80  schedules the request, and issues a grant for the dequeuirig logic  76  of the transmit gigabit port  24   b  to initiate a DMA read. In response to the grant, the dequeuing logic  76  reads the frame data (along the read bus  69   b ) in a DMA transaction from the location in external memory  36  pointed to by the frame pointer, and stores the frame data in the internal transmit FIFO for transmission by the transmit gigabit MAC  72   c . If the frame pointer specifies a unicopy transmission, the frame pointer is returned to the free buffer queue  64  following writing the frame data into the transmit FIFO. 
     A multicopy transmission is similar to the unicopy transmission, except that the port vector has multiple bits set, designating the multiple ports from which the data frame will be transmitted. The frame pointer is placed into each of the appropriate output queues  58  and transmitted by the appropriate transmit MAC units  20   b ,  24   b , and/or  30   b.    
     The free buffer pool  64 , the multicopy queue  60 , the reclaim queue  66 , and the multicopy ache  62  are used to manage use of frame pointers and re-use of frame pointers once the data frame has been transmitted to its designated output port(s). In particular, the dequeuing logic  76  passes frame pointers for unicopy frames to the free buffer queue  64  after the buffer contents have been copied to the appropriate transmit FIFO. 
     For multicopy frames, the port vector FIFO  56  supplies multiple copies of the same frame pointer to more than one output queue  58 , each frame pointer having a unicopy bit set to zero. The port vector FIFO  56  also copies the frame pointer and the copy count to the multicopy queue  60 . The multicopy queue  60  writes the copy count to the multicopy cache  62 . The multicopy cache  62  is a random access memory having a single copy count for each buffer in external memory  36  (i.e., each frame pointer). 
     Once the dequeuing logic  76  retrieves the frame data for a particular output port based on a fetched frame pointer and stores the frame data in the transmit FIFO, the dequeuing logic  76  checks if the unicopy bit is set to 1. If the unicopy bit is set to 1, the frame pointer is returned to the free buffer queue  64 . If the unicopy bit is set to zero indicating a multicopy frame pointer, the dequeuing logic  76  writes the frame pointer with a copy count of minus one (−1) to the multicopy queue  60 . The multicopy queue  60  adds the copy count to the entry stored in the multicopy cache  62 . 
     When the copy count in multicopy cache  62  for the frame pointer reaches zero, the frame pointer is passed to the reclaim queue  66 . Since a plurality of frame pointers may be used to store a single data frame in multiple buffer memory locations, the frame pointers are referenced to each other to form a linked-list (i.e., chain) of frame pointers to identify the stored data frame in its entirety. The reclaim queue  66  traverses the chain of buffer locations identified by the frame pointers, and passes the frame pointers to the free buffer queue  64 . 
     The foregoing description of the switch architecture provides an overview of the switch operations in a packet switched network. A more detailed description of the features of the present invention as embodied in the multiport switch  12  will now be provided. 
     INTERNAL RULES CHECKER 
     The present invention is directed to the internal rules checker  40  (IRC) and the use of the IRC  40  to provide high data throughput. As described previously, the switch subsystem  42  provides the switching logic for receiving and forwarding frames to the appropriate output port(s). The forwarding decisions, however, are made by the IRC  40  located on the multiport switch  12 . 
     According to the exemplary embodiment of the invention illustrated in FIG. 4, the IRC  40  includes four functional logic blocks, an ingress rules engine  200 , a source address (SA) lookup engine  210 , a destination address (DA) lookup engine  220  and an egress rules engine  230 . In the exemplary embodiment, the four engines  200 ,  210 ,  220  and  230  are employed as separate logic devices. In other words, each engine is designed in a modular fashion to receive input from other devices and to perform its particular functions without relying on processing logic from another logic engine. Advantageously, this modular architecture allows changes to be made to any of the particular logic engines without affecting other parts of the decision making process. However, in alternative configurations, the individual functions performed by each logic engine, discussed in detail below, as well as the particular fnumber of logic engines may be modified, based on the particular network requirements. Additionally, in the exemplary embodiment, the entire IRC  40  is designed in a modular fashion, including a memory for storing frame headers and a scheduler for facilitating processing of the frame headers. Advantageously, storing the frame headers within the IRC  40  enables the IRC  40  to process the frames in an efficient manner without having to transmit handshaking signals to the respective MAC devices for forwarding the frame headers to the IRC  40 . 
     The IRC  40  also includes address table  82 . However, in alternative embodiments, the address table  82  may be located outside the IRC  40  within another part of the multiport switch  12  or even external to the multiport switch  12 . According to the exemplary embodiment, the address table  82  supports  4096  user addresses and capabilities for  64  unique virtual local area networks (VLANs). However, the number of addresses and VLANs supported may be increased by expanding the table size. VLANs provide “broadcast domains” whereby broadcast traffic is kept “inside” the VLAN. For example, a specific VLAN may contain a group of users at a high level of an organization. When sending data to this group of users, the data may include a specific VLAN identifier associated with this particular group to ensure that only these users receive the data. These VLAN groupings can be thought of as “sub-networks” within a larger network. 
     FIG. 5 illustrates the organization of the IRC address table  82 . The IRC address table  82  contains an array of  4096  entries. The first “n” entries  92  are referred to as “bin entries” and have addresses from “0” to “n−1”. The remaining entries  94  are referred to as “heap entries” and have addresses from “n” to “ 4095 ”. Each of the table entries includes a 72-bit address entry field and a 12-bit “next pointer” field. 
     FIG. 6 illustrates the composition of each 84-bit table entry shown in FIG.  5 . The hit bit is used for address entry “aging” to delete entries from the address table  82  that have not been used in a predetermined amount of time. The static bit is used to prevent deletion of an address entry. 
     The traffic capture bit identifies traffic capture source and destination MAC addresses for mirroring MAC conversations to the management queue  68 . 
     The VLAN index field is a 6-bit field used to reference a 12-bit VLAN identifier (ID). The VLAN index-to-VLAN ID table  86 , shown in FIG. 4, contains the mapping associations. The switch  12  receives both tagged and untagged frames. When the switch  12  receives untagged data frames, i.e., without VLAN tag information, the IRC  40  assigns a VLAN index from the VLAN port-to-index table  88 , shown in FIG. 4, based on the receive port on which the frame is received. The VLAN index-to-ID table  86  and the VLAN port-to-index table  88  are located with the configuration and status registers  52 . However, in alternative configurations, the tables  86  and  88  may be located within the IRC  40 . 
     The port vector is a 15-bit field that provides a forwarding descriptor with a vector identifying the port(s) to which the frame should be forwarded. The MAC address field is a 48-bit field that includes addresses for both source addresses and destination addresses. The addresses can be unicast, multicast or broadcast. An individual/group (I/G) bit is also included in the MAC address field. 
     In the exemplary embodiment of the present invention, the host CPU  32  functions as the management entity and is connected to the IRC  40  via the CPU IF  50 . Alternatively, a management MAC may be connected to the CPU IF  50  to function as the management entity. 
     The IRC  40  uses the specific fields of the address table  82  to make frame forwarding decisions when frames are received in the switch  12 . More specifically, the IRC  40  uses engines  200 - 230  to generate frame forwarding information and to create a forwarding descriptor for output to the port vector FIFO  56 . 
     As discussed previously, the multiport switch  12  stores incoming data frames in external memory  36 . According to the exemplary embodiment illustrated in FIG. 4, the IRC  40  also includes a logically separate 4-deep rules queue  120  allocated for each receive port, i.e., the queue corresponding to each receive port holds four frame headers. However, in alternative configurations, the rules queue  120  may be configured to store other numbers of frame headers for each port, based on the particular network requirements. 
     The rules queue  120  “snoops” on the write bus  69  to external memory  36  to capture a predetermined portion of the data frames, including the destination and source addresses, transferred by queuing logic  74  to the buffers in external memory  36 . For example, the rules queue  120  may store the first 40 bytes of the frame. When a frame has been completely transferred to external memory  36 , the queuing logic  74  signals the end of the transfer and provides frame status information indicating whether the frame was received at the switch  12  without errors. The IRC  40  also includes IRC scheduler  122 , illustrated in FIG. 4, which monitors the signaling from queuing logic  74  and stores the frame status information in the rules queue  120  along with the corresponding frame header. 
     The rules queue  120  monitors the number of entries present at each port. When a queue for a receive port has three entries, the IRC  40  signals flow-control/back-pressure logic associated with that receive port in order to regulate network activity, the details of which are not disclosed herein in order not to unduly obscure the thrust of the present invention. 
     When the end of frame (EOF) transfer has been signaled by the queuing logic  74 , the IRC scheduler  122  enables the processing of the frame header through the ingress rules engine  200 . Logic engines  200 - 230 , as discussed previously, are separate logic devices and are able to process data frames in parallel, thereby increasing data throughput as compared to systems which employ a single decision making device. In other words, each logic engine is able to perform its respective processing on a different data frame simultaneously with the other respective logic engines. Advantageously, the data throughput of the multiport switch  12  including engines  200 - 230  may increase up to fourfold, as compared to a network switch that employs a single decision making device, since four data frames may be processed simultaneously. The operation of each logic engine, according to the exemplary embodiment, will be described below. 
     The ingress rules engine  200  performs a variety of pre-processing functions for each frame header. For example, ingress rules engine  200  checks to see if a data frame was received with errors by reading the frame status information stored with the respective frame headers in rules queue  120 . When the ingress rules engine  200  determines that a receive error has occurred, the ingress rules engine  200  constructs a forwarding descriptor with a null port vector, e.g., a port vector with all zeros or some other predetermined value, that will cause the frame to be discarded. Optionally, frames with errors may be forwarded to the host CPU  32  for diagnostic purposes. 
     The ingress rules engine  200  also checks the source address of the received frame to determine whether the Individual/Group (I/G) bit is set. If the I/G bit is set, indicating a multicast source address, the ingress rules engine  200  handles the frame as if the frame was received with errors. That is, the ingress rules engine  200  creates a forwarding descriptor with a null port vector. 
     The ingress rules engine  200  also checks the destination address (DA) of the frame to determine if the frame should be sent to the management entity, e.g., host CPU  32 . Specifically, the ingress rules engine  200  looks for Bridge Protocol Data Units (BPDUs), Generic Attribute Registrations Protocol (GARP) frames, MAC Control Frames and frames with certain Physical MAC addresses. The ingress rules engine  200  identifies these types of frames based on their specific destination address information. When the ingress rules engine  200  detects a match with one of the above DAs, the ingress rules engine  200  constructs a forwarding descriptor identifying the management port as the forwarding port. 
     The ingress rules engine  200  also determines whether SA and DA lookups will be performed by engines  210  and  220 , respectively, based on whether learning and forwarding are set in the respective port IRC control registers  114   a-m , illustrated in FIG. 4, in addition to whether the data frame was received with errors or is one of the specific types of frames to be transmitted to the management port, discussed above. According to the exemplary embodiment of the invention, the multiport switch  12  includes one port IRC control register  114  for each of the twelve 10/100 Mb/s ports and for the 1 Gb/s port. In alternative configurations, a single register could be used to store the appropriate control information for the respective ports. 
     Referring to FIG. 4, each port IRC control register  114  includes a learn bit and a forward (frwrd) bit. A set learn bit allows the IRC to “learn” unknown MAC source addresses received by the corresponding port, i.e., add new entries not stored in address table  82 . A set frwrd bit allows frames received by the corresponding port to be forwarded to other ports and allows frames received by other ports to be transmitted from this port. When learning is set and forwarding is not set in the port IRC control register  114  corresponding to the port on which the frame was received, only the SA lookup is performed. That is, the SA lookup is performed so that a new entry may be added to the address table  82  and the SA lookup engine  210  generates a forwarding descriptor with a null port vector. When learning and forwarding are both set in the port IRC control register  114  corresponding to the receive port, both SA and DA lookups are performed, as discussed in more detail below. When learning and forwarding are both clear in the port IRC control register  114  corresponding to the receive port, neither the SA nor DA lookups is performed. In this case, the ingress rules engine  200  generates a forwarding descriptor with a null port vector. 
     Optionally, the ingress rules engine  200  performs VLAN ingress filtering to prevent the multiport switch  12  from forwarding a frame that does not belong to a VLAN associated with the receiving port. The port IRC control registers  114  each include an ingress bit which, when set, indicates that ingress filtering is enabled. Ingress filtering according to the exemplary embodiment of the present invention proceeds as follows. 
     Initially, the ingress rules engine  200  determines whether a received frame has no VLAN tag header or if the VLAN tag header has a VLAN ID equal to “0”. When the frame has no VLAN tag header or the VLAN ID is “0”, the ingress rules engine  200  does not perform ingress filtering regardless of the state of the ingress bit. Otherwise, the ingress rules engine  200  retrieves the VLAN index corresponding to the frame&#39;s VLAN ID from the VLAN index-to-ID table  86 . If the frame&#39;s VLAN ID is not found in this table, the ingress rules engine  200  forwards the frame to the management port only. 
     After processing by ingress rules engine  200 , the IRC  40  performs SA and DA searches of address table  82 , based on whether learning and forwarding are enabled as discussed above. The multiport switch  12  needs to make frame forwarding decisions relatively quickly, since multiple data frames may be received by the multiport switch  12  simultaneously. Hence, in the exemplary embodiment of the present invention, a hashing scheme is used to search only a subset of the address entries, as described below. The memory structure of FIG. 5 provides an indexed arrangement, where a given network address will be assigned to a corresponding bin. In other words, each bin entry  96  is configured to reference a plurality of table entries (i.e., heap entries)  98 . Hence, the SA lookup engine  210  performs a search of the address table  82  by first accessing a specific bin  96  pointed to by a hash key, and then searching the entries within (i.e., referenced by) the corresponding bin to locate the appropriate match. 
     Each bin entry  96  is the starting point for the search by the SA lookup engine  210  for a particular address within the address table  82 . A bin entry may reference no addresses (i.e., be empty), may reference only one address within the bin entry location, or may reference a plurality of addresses using a linked list chain structure. 
     FIG. 7 is a diagram illustrating bin entries referencing a different number of table entries. Each of the bin entries  96  and heap entries  98  includes the 72-bit address entry and a 12-bit “next pointer” field. The “next pointer” field associated with the bin entry  96  identifies the location of the next entry in the chain of linked list addresses. For example, Bin  3 ,  96   d , of FIG. 7 does not have any associated table entries. In such a case, the 72-bit address entry equals zero (or another null value), and the bin&#39;s corresponding “next pointer” field will have a value of “1”, indicating no entries for the corresponding bin. If a bin such as Bin  1 ,  96   b , contains a single table entry, the bin entry will store the switching logic data for that single address in its address entry field, and store the value “zero” in the “next pointer” field, indicating there are no further address entries in the chain. Bin  0 ,  96   a , however, references four addresses by using the “next pointer” field to identify the location of the next entry in the chain. The additional entries  96   b - 96   d  in the bin are linked in a linear list, as shown in FIG.  7 . Thus, the first entry of Bin  0  is stored in the address entry field of the bin entry  96   a  and the next entry (heap entry  98   a ) is referenced by address entry “a” in the next pointer field of the bin entry  96   a.    
     The SA lookup engine  210  performs hash searches of the IRC address table  82  to find entries associated with the source address and VLAN index of a received data frame. FIG. 8 is a block diagram illustrating an exemplary hash function circuit  100  used in conjunction with the SA lookup engine  210  in accordance with an embodiment of the present invention. The hash function circuit  100  includes a series of AND gates  102 , a series of exclusive OR (XOR) gates  104 , and a shift register  106 . A user-specified hash function, stored in a user-programmable register (HASHPOLY)  108 , includes a 12-bit value defining the hash polynomial used by the hash function circuit  100 . Exemplary hash polynomials for the hashing function of the present invention are x 12 +x 10 +x 7 +x 3 +x 2 +1, which has a HASHPOLY of 0100 1000 1101, and x 12 +x 10 +x 5 +x 3 +1, which has a HASHPOLY of 0100 0010 1001. The x 12  term is assumed to always equal “1”, and therefore is not stored in the HASHPOLY register  108 . Other polynomials may also be used for HASHPOLY based on the particular design requirements. 
     The hash function circuit  100  generates the hash key using the source address of the data packet according to a user-specified hash function. Initially, the IRC controller  82  concatenates the 16 least significant bits of the source address of the data packet with the VLAN index to create a search key. After the entire search key has been processed, the hash function circuit  100  outputs a 12-bit has key. 
     From the 12-bit hash key, the SA lookup engine  210  calculates a bin number for searching the appropriate bin list in address table  82 . More particularly, the SA lookup engine  210  uses the lower POLYEN bits of the hash key to generate the bin number. The bin number falls in the range of [0, n−1] where n=2 POLYEN  and the value of POLYEN is programmed by the host CPU  32  and stored in register  110 . The hash key output by the hash function circuit  100  is provided to a logic circuit, for example a 12-bit parallel AND gate  111 , that selectively outputs the lower significant bits of the hash key based upon a polynomial enable value (POLYEN) stored in register  210 . The field “POLYEN” defines how many bits of the hash key are used to create the bin number. For example, if POLYEN=5, then the SA lookup engine  210  uses the lower five bits of the hash key. Hence, the hash key output by the logic circuit  100  is based upon masking the 12-bit hash key using the stored register value POLYEN in register  110 . 
     After the bin number is calculated, the SA lookup engine  210  searches the bin list of the particular bin for an address entry whose address and VLAN index and fields match the source address (SA) and VLAN index of the received frame. 
     If the SA lookup engine  210  finds an address entry whose address and VLAN index match the SA and VLAN index of the frame, the SA lookup engine  210  sets the hit bit for that address entry. Optionally, the hit bit may be used for address entry aging. If the SA lookup engine  210  does not find a match and learning is enabled, the SA lookup engine  210  constructs a new entry in the IRC address table  82  using the information from the received frame. 
     After the SA lookup engine  210  completes the search and adds a new entry, if necessary, the DA lookup engine  220  performs a search of the address table  82 , assuming that forwarding is set in the corresponding port IRC control register  114 . Specifically, the DA lookup engine  220  searches the address table  82  for an address entry whose address and VLAN index match the destination address (DA) and VLAN index of the frame. The DA lookup engine  220  uses the 12-bit hash function circuit  100 , illustrated in FIG. 8, to generate a 12-bit hash key for the DA/AVLAN index search. The DA lookup engine  220  uses the lower POLYEN bits of the hash key to calculate the bin number in the address table  82 . The DA lookup engine  220  then searches the appropriate bin list for a DA/VLAN index match in the address table  82 . If a match is found, the DA lookup engine  220  uses the port vector field of the address entry and passes the port vector field information to the egress rules engine  230 . When the DA lookup engine  220  cannot find a DA/VLAN index match, the frame must be “flooded” to all members of the VLAN. In this case, the DA lookup engine  220  sets the port vector to indicate that all member ports are to transmit the frame. 
     After, the DA lookup engine  220  generates the port vector, the egress rules engine  230  receives the port vector information along with the receive port number and VLAN ID information. The egress rules engine  230  then creates a forwarding descriptor for the frame, as discussed in detail below. 
     FIG. 9 illustrates the composition of the forwarding descriptor according to an embodiment of the present invention. Referring to FIG. 9, the priority class field is a one-bit field that indicates the output priority queue in which the frame pointer should be placed, e.g., high priority or low priority. 
     The port vector field is a 15-bit field that identifies each port(s) that should receive the data frame for transmission to its destination address. Bit  0  of the port vector field corresponds to Port  0  (the management port), bits  1 - 12  correspond to MAC ports  1 - 12  respectively (the 10/100 Mb/s ports), bit  13  corresponds to the gigabit port  24  and bit  14  corresponds to the expansion port  30 . 
     The untagged set field is a 13-bit field that indicates which ports should remove VLAN tag headers before transmitting frames. The untagged set is obtained from an untagged set table. The Rx port is a four-bit field that indicates the port from which the frame was received. 
     The VLAN ID field is a 12-bit field that includes the VLAN identifier associated with the frame. The opcode is an 11-bit field that contains instructions about how the frame should be modified before transmission and information that the host CPU  32  can use for processing frames from the management queue. The frame pointer is a 13-bit field that contains the location of the frame stored in external memory  36 . 
     When VLAN ingress filtering is set, the egress rules engine  230  performs VLAN member set checking. The egress rules engine  230  performs this check by examining the bit that corresponds to the frame&#39;s VLAN index in the VLAN member set table entry that corresponds to the output port. If this bit is not set, the egress rules engine  230  masks that port from the port vector. The egress rules engine  230  also performs a trunk mapping function when an output port is part of a “trunk”, i.e., a predetermined set of ports that are used to transmit data to the same destination. When a port is part of a trunk, the egress rules engine  230  determines which port in the trunk on which to transmit the data frame. 
     After the egress rules engine  230  generates the forwarding descriptor, the egress rules engine  230  outputs the forwarding descriptor to the port vector FIFO  56  for queuing, as shown in FIG.  3 . As discussed above, the IRC  40  processes data frames in a pipelined manner to increase data throughput. Additionally, the pipeline is asynchronous so that the SA and DA lookup engines  210  and  220  are able to search the address table  82  for the desired information. In other words, the SA and DA lookup engines  210  and  220  have a variable amount of time to search the address table  82  and are not limited to a fixed search time. Advantageously, this enables the SA and DA lookup engines  210  and  220  to search the address table  82  in an efficient manner to locate the desired information. 
     Described has been a system and method for generating a forwarding descriptor in a network interface device. An advantage of the invention is that logic engines  200 - 230  are designed as separate logic devices and are able to process data frames independently. For example, the egress rules engine  230  may process a first frame while the DA lookup engine  220  is processing a second frame, the SA lookup engine  210  is processing a third frame and the ingress rules engine is processing a fourth frame. Advantageously, the throughput of the switch increases data throughput as much as fourfold, as compared to a switch that processes frames one frame at a time. Another advantage of the invention is that the modular architecture of the IRC  40  enables changes to be made to one of the logic engines without affecting the other logic engines. For example, when changes to the ingress rules engine  200  are desired, the changes may be made without causing corresponding changes to any of the engines  210 ,  220  or  230 . Accordingly, the desired changes may be made in an efficient manner while minimizing the complexity of the changes. A further advantage of the invention is that the entire IRC  40  is designed in a modular fashion including rules queue  120  for storing frame headers. The use of the rules queue  120  within the IRC  40  reduces flow control/back pressure problems associated with processing frames received by the MAC devices. The snooping function of rules queue  120  also reduces the need for additional handshaking signals between the receive MACs and the IRC  40  when storing frame headers in the rules queue  120 . Accordingly, the modularity of the entire IRC  40  enables changes to be made to any part of the IRC  40  while minimizing the effects to other parts of the switch  12 . 
     In this disclosure, there is shown and described only the preferred embodiments of the invention, but, as aforementioned, it is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.