Patent Publication Number: US-2023137190-A1

Title: Power control device

Description:
This application is a continuation of U.S. application Ser. No. 17/542,695, filed on Dec. 6, 2021 which is a continuation of U.S. application Ser. No. 17/142,866, filed Jan. 6, 2021, now U.S. Pat. No. 11,228,170, which is a continuation of U.S. application Ser. No. 16/900,495, filed Jun. 12, 2020 now U.S. Pat. No. 10,916,933 issued on Feb. 9, 2021, which is a continuation of U.S. patent application Ser. No. 16/287,713, filed Feb. 27, 2019, now U.S. Pat. No. 10,714,929, issued on Jul. 14, 2020, which is a continuation of U.S. patent application Ser. No. 16/034,497, filed Jul. 13, 2018, now U.S. Pat. No. 10,256,623, issued on Apr. 9, 2019, which claims priority to Japanese Patent Application No. 2017-158846 filed on Aug. 21, 2017 and Japanese Patent Application No. 2018-049584 filed on Mar. 16, 2018, the contents of both of which are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     This invention relates to a power control device. 
     Description of the Related Art 
     Conventionally, there are known power supply circuits that include an overvoltage protection circuit to perform protection against an overvoltage in an output voltage. 
       FIG.  11    shows one exemplary configuration of a power supply circuit having an overvoltage protection circuit as mentioned above. The power supply circuit  100 A shown in  FIG.  11    is what is called a linear regulator, which is a kind of DC-DC converter. The power supply circuit  100 A includes an output transistor  101 , an error amplifier  102 , an overvoltage protection circuit  103 A, and resistors R 1  and R 2 . 
     To the drain of the output transistor  101 , which is an n-channel MOSFET, an input voltage Vin is applied. To the source of the output transistor  101 , an output terminal Tout, from which an output voltage Vout is output, is connected. The source of the output transistor  101  is connected to a ground potential via a serially connected arrangement of the resistors R 1  and R 2 . The resistors R 1  and R 2  divide the output voltage Vout. 
     The connection node at which the resistors R 1  and R 2  are connected together is connected to the inverting input terminal of the error amplifier  102 . To the non-inverting input terminal of the error amplifier  102 , a reference voltage Vref is applied. The output terminal of the error amplifier  102  is connected to the gate of the output transistor  101 . 
     In this configuration, the error amplifier  102  drives the gate of the output transistor  101  so that a feedback voltage FB, which is generated by dividing the output voltage Vout with the resistors R 1  and R 2 , equals the reference voltage Vref. Thus, the output voltage Vout is controlled to the voltage value given by Formula (1) below. 
         V out=(( R 1 +R 2)/ R 2)× V ref  (1)
 
     The overvoltage protection circuit  103 A monitors the feedback voltage FB, and when the feedback voltage FB exceeds the threshold voltage value set as an overvoltage, the overvoltage protection circuit  103 A stops an output operation of the error amplifier  102 . With this, when the output voltage Vout rises to reach the overvoltage, the feedback voltage FB also rises to exceed the threshold voltage value; thus, the output operation of the error amplifier  102  is stopped, and accordingly the output voltage Vout lowers. In this way, overvoltage protection in the output voltage Vout is performed. 
       FIG.  12    shows another exemplary configuration of a power supply circuit having an overvoltage protection circuit. The power supply circuit  100 B shown in  FIG.  12    is a linear regulator like the power supply circuit  100 A shown in  FIG.  11   , but differs from this in configuration in that the power supply circuit  100 B has an overvoltage protection circuit  103 B. 
     The overvoltage protection circuit  103 B directly monitors the output voltage Vout, and when the output voltage Vout exceeds a set overvoltage value, it stops the output operation of the error amplifier  102 . 
     For another example, Japanese Patent Application published as No. 2010-220454 also discloses a power supply circuit that performs overvoltage protection. 
     However, the power supply circuit  100 A shown in  FIG.  11    and the power supply circuit  100 B shown in  FIG.  12    described above have the following problems respectively. In the power supply circuit  100 A, when the resistor R 1  becomes open or the resistor R 2  is short-circuited, an abnormal drop in the feedback voltage causes the error amplifier  102  to increase the output voltage Vout up to an overvoltage, but the feedback voltage FB lowers, so the overvoltage protection circuit  103 A cannot detect the overvoltage and the overvoltage protection function does not come into effect. 
     On the other hand, in the power supply circuit  100 B, when the resistor R 1  is open or the resistor R 2  is short-circuited as above and the output voltage Vout rises, since the overvoltage protection circuit  103 B directly monitors the output voltage Vout, overvoltage protection can be performed. 
     However, when the output transistor  101 , the error amplifier  102  and the overvoltage protection circuit  103 B are configured so as to be included in one IC, and the resistors R 1  and R 2  are provided externally to the IC, the output voltage Vout can be set with the resistance values of the resistors R 1  and R 2  as seen from Formula (1). In that case, it is difficult to do overvoltage setting properly for all possible output voltages Vout with a common IC, that is, with the overvoltage protection circuit  103 B. 
     Against the background discussed above, the present invention intends to provide a power control device that can perform overvoltage protection in the output voltage even if the feedback voltage is abnormal and that facilitates proper overvoltage setting. 
     SUMMARY OF THE INVENTION 
     A power control device according to one aspect of the present invention includes: an output voltage controller configured to control an output voltage based on a feedback voltage corresponding to the output voltage; and an overvoltage protector configured to continue or stop the operation of the output voltage controller based on a first detection result of whether the output voltage has exceeded an output voltage threshold value and a second detection result of whether the feedback voltage has fallen to or below a feedback voltage threshold value. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a diagram showing a configuration of a power supply circuit according to a first embodiment of the present invention. 
         FIG.  2    is a timing chart showing one example of operation of an overvoltage protection circuit according to the first embodiment. 
         FIG.  3    is a timing chart showing one example of operation of an overvoltage protection circuit according to the first embodiment. 
         FIG.  4    is a diagram showing a configuration of a power supply circuit according to a second embodiment of the present invention. 
         FIG.  5    is a timing chart showing one example of operation of an overvoltage protection circuit according to the second embodiment. 
         FIG.  6    is a timing chart showing one example of operation of an overvoltage protection circuit according to the second embodiment. 
         FIG.  7    is a diagram showing a configuration of a power supply circuit according to a third embodiment of the present invention. 
         FIG.  8    is a diagram showing a configuration of a power supply circuit according to a fourth embodiment of the present invention. 
         FIG.  9    is a plan view showing one example of pin arrangement in a power supply IC according to the fourth embodiment of the present invention. 
         FIG.  10    is a diagram showing an external appearance of one example of vehicle incorporating various electronic appliances. 
         FIG.  11    is a diagram showing one example of a power supply circuit having an overvoltage protection circuit. 
         FIG.  12    is a diagram showing one example of a power supply circuit having an overvoltage protection circuit. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings. 
     First Embodiment:  FIG.  1    is a diagram showing the configuration of a power supply circuit  10  according to a first embodiment of the present invention. The power supply circuit  10  is configured as a DC-DC converter, or more specifically, a linear regulator. The power supply circuit  10  converts an input voltage Vin to an output voltage Vout. 
     The power supply circuit  10  includes a power supply IC  10 A and external resistors R 1  and R 2 . The power supply IC  10 A is a power control device that controls, so as to keep constant, the output voltage Vout of the power supply circuit  10 . The power supply IC  10 A is a semiconductor integrated circuit having integrated in it an output transistor  1 , an error amplifier  2 , a first overvoltage protection circuit  3 , and a second overvoltage protection circuit  4 . The power supply IC  10 A has terminals T 1  to T 4  via which to establish electrical connection with the outside. The output transistor  1  and the error amplifier  2  constitute an output voltage controller  5 , which controls the output voltage Vout. 
     To the drain of the output transistor  1 , which is configured as an n-channel MOSFET, an input voltage Vin is applied via the terminal T 1 . To the source of the output transistor  1 , an output terminal Tout is connected via the terminal T 2 . At the output terminal Tout, the output voltage Vout appears. The terminal T 2  is connected to a ground potential via a serially connected arrangement of the resistors R 1  and R 2 . The resistors R 1  and R 2  divide the output voltage Vout. 
     The connection node at which the resistors R 1  and R 2  are connected together is connected to the inverting input terminal of the error amplifier  2  via the terminal T 3 . To the non-inverting input terminal of the error amplifier  2 , a reference voltage Vref is applied. The output terminal of the error amplifier  2  is connected to the gate of the output transistor  1 . 
     In this configuration, the error amplifier  2  drives the gate of the output transistor  1  so that a feedback voltage FB, which is generated by dividing the output voltage Vout with the resistors R 1  and R 2 , equals the reference voltage Vref. Thus, the output voltage Vout is controlled at a voltage value calculated by Formula (1) above. 
     The first overvoltage protection circuit  3  includes an output voltage detector  31 , a feedback voltage detector  32  (FB voltage detector), and an AND circuit  33 , and performs protection against an overvoltage in the output voltage Vout. 
     The FB voltage detector  32  detects whether the feedback voltage FB that appears at the terminal T 3  has fallen to or below a predetermined feedback voltage threshold value (FB voltage threshold value). The output voltage detector  31  detects whether the output voltage Vout which is input via the terminal T 4  has risen above a predetermined output voltage threshold value. The detection outputs from the output voltage detector  31  and the FB voltage detector  32  are input to the AND circuit  33 . The error amplifier  2  continues or stops the output operation in accordance with the output from the AND circuit  33 . 
     Now, the operation of the first voltage protection circuit  3  will be described with reference to a timing chart shown in  FIG.  2   .  FIG.  2    shows, from top down, the output voltage Vout, the feedback voltage FB, a detection output V 1  from the output voltage detector  31 , a detection output V 2  from the FB voltage detector  32 , and an output AND from the AND circuit  33 .  FIG.  2    shows a case where, through the setting of the resistors R 1  and R 2 , the output voltage Vout is set at a voltage Vout 1  (for example 1V). 
       FIG.  2    also shows an output voltage threshold value Vth 1  set in the output voltage detector  31 , and a FB voltage threshold value Vth 2  set in the FB voltage detector  32 . The output voltage threshold value Vth 1  is a voltage (for example, 1.2V) slightly higher than the voltage Vout 1 , and the FB voltage threshold value Vth 2  is a voltage (for example, 0.2V) close to zero. 
     At time point t 1  shown in  FIG.  2   , the error amplifier  2  starts up, and the output voltage Vout and the feedback voltage FB begin to rise. Here, the output voltage Vout equals zero, and is thus equal to or lower than the output voltage threshold value Vth 1 , so the detection output V 1  is Low. The feedback voltage FB equals zero, and thus the feedback voltage FB is equal to or lower than the FB voltage threshold value Vth 2 , so the detection output V 2  is High. Accordingly, the output AND is Low. When the output AND is Low, the error amplifier  2  continues the output operation. 
     At time point t 2 , when the feedback voltage FB rises to or above the FB voltage threshold value Vth 2 , the detection output V 2  becomes Low. Thus, the output AND is Low. 
     At time point t 3 , when the feedback voltage FB reaches the reference voltage Vref, and the output voltage Vout reaches the voltage Vout 1 , both the feedback voltage FB and the output voltage Vout become constant. When the feedback voltage FB and the output voltage Vout are constant, both the detection outputs V 1  and V 2  are Low, so the output AND is Low. 
     At time point t 4 , if the resistor R 1  becomes open, or the resistor R 2  is short-circuited, the feedback voltage FB rapidly falls to or below the FB voltage threshold value Vth 2 , and the FB voltage detector  32  turns the detection output V 2  High. Here, the detection output V 1  is Low, so the output AND is Low. 
     Then, due to an abnormal drop in the feedback voltage FB, the output voltage Vout rises to exceed the output voltage threshold value Vth 1  at time point t 5 . Here, the output voltage detector  32  turns the detection output V 1  High, so the output AND becomes High. With this, the error amplifier  2  stops the output operation, and the output voltage Vout goes down. In this way, protection can be performed against an overvoltage in the output voltage Vout caused by an open circuit in the resistor R 1  or a short circuit in the resistor R 2 . 
     As described above, if the feedback voltage FB is equal to or lower than the FB voltage threshold value Vth 2  but the output voltage Vout is equal to or lower than the output voltage threshold value Vth 1 , it is judged that the circuit is starting up, so the output operation of the output voltage Vout is continued (time point t 1  to t 2 ). If the feedback voltage FB is above the FB voltage threshold value Vth 2 , it is judged that the circuit is in a normal state, so the output operation of the output voltage Vout is continued (time point t 2  to t 4 ). If the feedback voltage FB falls to or below the FB voltage threshold value Vth 2 , and in addition the output voltage Vout rises above the output voltage threshold value Vth 1 , it is judged that an overvoltage has occurred due to an open circuit in the resistor R 1  or a short circuit in the resistor R 2 , and the output operation of the output voltage Vout is stopped for overvoltage protection (after time point t 5 ). 
       FIG.  3    is a timing chart corresponding to  FIG.  2   , and it shows a case where, through the setting of the resistors R 1  and R 2 , the output voltage Vout is set at a voltage Vout 2  (for example, 5V) higher than the voltage Vout 1 . 
     At time point t 11  shown in  FIG.  3   , the error amplifier  2  starts up, and the output voltage Vout and the feedback voltage FB begin to rise. Here, the detection output V 1  is Low, and the detection output V 2  is High, so the output AND is Low. 
     At time point t 12 , when the feedback voltage FB rises to exceed the FB voltage threshold value Vth 2 , the detection output V 2  becomes Low. Thus, the output AND is Low. 
     Thereafter, the output voltage Vout rises, and when it exceeds the output voltage threshold value Vth 1  at time point t 13 , the detection output V 1  turns High, but the detection output V 2  is Low, so the output AND is Low, resulting in the continued output operation of the error amplifier  2 . 
     At time point t 14 , when the feedback voltage FB reaches the reference voltage Vref, and the output voltage Vout reaches the voltage Vout 2 , both the feedback voltage FB and the output voltage Vout become constant. When the feedback voltage FB and the output voltage Vout are constant, the detection output V 1  is High, and the detection output V 2  is low, so the output AND is Low. 
     At time point t 15 , if the resistor R 1  becomes open, or the resistor R 2  is short-circuited, the feedback voltage FB rapidly falls to or below the FB voltage threshold value Vth 2 , and the FB voltage detector  32  turns the detection output V 2  High. Here, the detection voltage V 1  is High, so the output AND turns High. With this, the error amplifier  2  stops the output operation, and the output voltage Vout goes down. Thus, the output voltage Vout 2  drops without rising up to an overvoltage, and overvoltage protection is performed. 
     As described above, if the feedback voltage FB is equal to or lower than the FB voltage threshold value Vth 2 , and the output voltage Vout is equal to or lower than the output voltage threshold value Vth 1 , it is judged that the circuit is starting up, so the output operation of the output voltage Vout is continued (time point t 11  to t 12 ). If the feedback voltage FB is above the FB voltage threshold value Vth 2 , it is judged that the circuit is in a normal state, so the output operation of the output voltage Vout is continued (time point t 12  to t 15 ). If the feedback voltage FB falls to or below the FB voltage threshold value Vth 2 , and in addition the output voltage Vout rises above the output voltage threshold value Vth 1 , it is judged that an overvoltage has occurred due to an open circuit in the resistor R 1  or a short circuit in the resistor R 2 , and the output operation of the output voltage Vout is stopped for overvoltage protection (after time point t 15 ). 
     As described with reference to  FIG.  2    and  FIG.  3   , even in a case where, through the setting of the external resistors R 1  and R 2 , the output voltage Vout (Vout 1 , Vout 2 ) is variably set with respect to a common power supply IC  10 A, by allowing overvoltage setting in the overvoltage protection circuit  3  based on the output voltage threshold value Vth 1  and the FB voltage threshold value Vth 2 , it is possible to perform overvoltage protection for the output voltage Vout in either setting. This makes proper overvoltage setting easy. 
     The second overvoltage protection circuit  4  monitors the feedback voltage FB, and if the feedback voltage FB exceeds a predetermined overvoltage set value, it stops the output operation of the error amplifier  2 . With this, even if an overvoltage occurs in the output voltage Vout with the resistors R 1  and R 2  in a normal state, overvoltage protection can still be performed. In other words, by providing not only the first overvoltage protection circuit  3  but also the second overvoltage protection circuit  4 , it becomes possible to handle overvoltages due to various causes. 
     Second Embodiment:  FIG.  4    is a diagram showing the configuration of a power supply circuit  15  according to a second embodiment of the present invention. A power supply circuit  15  shown in  FIG.  4    is configured as a linear regulator just like the power supply circuit  10  according to the first embodiment described above. The power supply circuit  15  has a power supply IC  15 A. A difference from the first embodiment in configuration is that the power supply IC  15 A has a first overvoltage protection circuit  301 . 
     The first overvoltage protection circuit  301  has an output voltage detector  301 A and a FB voltage detector  301 B. The output voltage detector  301 A continues or stops the detection operation according to a detection output V 2  from the FB voltage detector  301 B. The output voltage detector  301 A outputs a detection output V 1  to an error amplifier  2 . The error amplifier  2  continues or stops the output operation according to the detection output V 1 . 
     Now, the operation of the first voltage protection circuit  301  will be described with reference to a timing chart shown in  FIG.  5   .  FIG.  5    shows, from top down, the output voltage Vout, the feedback voltage FB, the detection output V 1  from the output voltage detector  301 A, and the detection output V 2  from the FB voltage detector  301 B.  FIG.  5    shows a case where, through the setting of resistors R 1  and R 2 , the output voltage Vout is set at a voltage Vout 1 . 
       FIG.  5    also shows an output voltage threshold value Vth 1  set in the output voltage detector  301 A, and a FB voltage threshold value Vth 2  set in the FB voltage detector  301 B. The output voltage threshold value Vth 1  is a voltage slightly higher than the voltage Vout 1 , and the FB voltage threshold value Vth 2  is a voltage close to zero. 
     At time point t 21  shown in  FIG.  5   , the error amplifier  2  starts up, and the output voltage Vout and the feedback voltage FB begin to rise. The feedback voltage FB equals zero, and thus the feedback voltage FB is equal to or lower than the FB voltage threshold value Vth 2 , so the detection output V 2  is High. With this, the output voltage detector  301 A performs a detection operation. Here, the output voltage Vout equals zero, and is thus equal to or lower than the output voltage threshold value Vth 1 , so the detection output V 1  is Low. When the detection output V 1  is Low, the error amplifier  2  continues the output operation. 
     At time point t 22 , when the feedback voltage FB rises to exceed the FB voltage threshold value Vth 2 , the detection output V 2  becomes Low. With this, the output voltage detector  301 A stops the detection operation, so the detection output V 1  becomes Low. 
     At time point t 23 , when the feedback voltage FB reaches a reference voltage Vref, and the output voltage Vout reaches the voltage Vout 1 , the feedback voltage FB and the output voltage Vout become constant. When the feedback voltage FB and the output voltage Vout are constant, both the detection outputs V 1  and V 2  are Low. 
     At time point t 24 , if the resistor R 1  becomes open, or the resistor R 2  is short-circuited, the feedback voltage FB rapidly falls to or below the FB voltage threshold value Vth 2 , and the FB voltage detector  301 B turns the detection output V 2  High. With this, the output voltage detector  301 A starts up. Here, the output voltage Vout is equal to or lower than the output voltage threshold value Vth 1 , so the detection output V 1  is Low. 
     Then, due to an abnormal drop in the feedback voltage FB, the output voltage Vout rises and at time point t 25 , it exceeds the output voltage threshold value Vth 1 . Here, the output voltage detector  301 A turns the detection output V 1  High. With this, the error amplifier  2  stops the output operation, and the output voltage Vout goes down. In this way, protection can be performed against an overvoltage in the output voltage Vout caused by an open circuit in the resistor R 1  or a short circuit in the resistor R 2 . 
       FIG.  6    is a timing chart corresponding to  FIG.  5   , and it shows a case where, through the setting of the resistors R 1  and R 2 , the output voltage Vout is set at a voltage Vout 2  higher than the voltage Vout 1 . 
     At time point t 31  shown in  FIG.  6   , the error amplifier  2  starts up, and the output voltage Vout and the feedback voltage FB begin to rise. Here, since the detection output V 2  is High, the output voltage detector  301 A is performing a detection operation, so the detection output V 1  is Low. 
     At time point t 32 , when the feedback voltage FB rises to exceed the FB voltage threshold value Vth 2 , the detection output V 2  becomes Low. With this, the output voltage detector  301 A stops the detection operation, so the detection output V 1  is Low. 
     Thereafter, the output voltage Vout rises and at time point  33 , it exceeds the output voltage threshold value Vth 1 , but since the detection output V 2  is Low and thus the output voltage detector  301 A is inactive, the detection output V 1  is Low. 
     At time point t 34 , when the feedback voltage FB reaches the reference voltage Vref, and the output voltage Vout reaches the voltage Vout 2 , both the feedback voltage FB and the output voltage Vout become constant. When the feedback voltage FB and the output voltage Vout are constant, both the detection outputs V 1  and V 2  are Low. 
     At time point t 35 , if the resistor R 1  becomes open, or the resistor R 2  is short-circuited, the feedback voltage FB rapidly falls to or below the FB voltage threshold value Vth 2 , and the FB voltage detector  301 B turns the detection output V 2  High. With this, the output voltage detector  301 A starts up. Since the output voltage Vout exceeds the output voltage threshold value Vth 1 , the detection output V 1  becomes High. Thus, the error amplifier  2  stops the output operation, and the output voltage Vout goes down. In this way, the output voltage Vout drops without rising up to an overvoltage, and overvoltage protection is performed. 
     With this second embodiment, effects similar to those with the first embodiment can be obtained. However, in the second embodiment, the output voltage detector  301 A remains inactive until it is started up by the FB voltage detector  301 B, and this helps reduce power consumption. 
     Third Embodiment:  FIG.  7    is a diagram showing the configuration of a power supply circuit  20  according to a third embodiment of the present invention. The power supply circuit  20  shown in  FIG.  7    is a DC-DC converter, or more specifically, a synchronous rectification switching regulator. The power supply circuit  20  converts an input voltage Vin to an output voltage Vout. The power supply circuit  20  includes a power supply IC  20 A, a coil L 1 , a capacitor C 1 , and resistors R 1  and R 2 . The power supply IC  20 A is a power control device that controls, so as to keep constant, the output voltage Vout of the power supply circuit  20 . The coil L 1 , the capacitor C 1 , and the resistors R 1  and R 2  are provided as components external to the power supply IC  20 A. 
     The power supply IC  20 A is a semiconductor integrated circuit having integrated in it a first switching element  11 , a second switching element  12 , an error amplifier  13 , a driver  14 , a first overvoltage protection circuit  16 , and a second overvoltage protection circuit  17 . The error amplifier  13 , the driver  14 , the first switching element  11 , and the second switching element  12  constitute an output voltage controller  18  which controls the output voltage Vout. The power supply IC  20 A has terminals T 11  to T 14  via which to establish electrical connection with the outside. 
     To the source of the first switching element  11 , which is configured as a p-channel MOSFET, the input voltage Vin is applied via the terminal T 11 . The drain of the first switching element  11  is connected to the drain of the second switching element  12 , which is configured as an n-channel MOSFET. The source of the second switching element  12  is connected to an application terminal for a ground potential. That is, the first switching element  11  and the second switching element  12  are connected in series between the input voltage and the ground potential. 
     To the connection node at which the first switching element  11  and the second switching element  12  are connected together, one end of the coil L 1  is connected via the terminal T 12 . The other end of the coil L 1  is connected to one end of the capacitor C 1 . The other end of the capacitor C 1  is connected to the application terminal for the ground potential. To the connection node at which the coil L 1  and the capacitor C 1  are connected together, the output terminal Tout is connected. At the output terminal Tout, the output voltage Vout appears. 
     To a line on which the output voltage Vout appears, an application terminal for the ground potential is connected via a serially connected arrangement of the resistors R 1  and R 2 . The connection node at which the resistors R 1  and R 2  are connected together is connected to the inverting input terminal of the error amplifier  13 . To the non-inverting input terminal of the error amplifier  13 , a reference voltage Vref is applied. The driver  14  drives the respective gates of the first switching element  11  and the second switching element  12  based on the output of the error amplifier  13 . By the driver  14 , the first switching element  11  and the second switching element  12  are switched complementarily. 
     The feedback voltage FB is generated by dividing the output voltage Vout with the resistors R 1  and R 2 . The generated feedback voltage FB is input to the error amplifier  13 , and the driver  14  drives the first switching element  11  and the second switching element  12 . With this, the feedback voltage FB is controlled so as to be equal to the reference voltage Vref, and the output voltage Vout is controlled so as to be constant. Through the setting of the external resistors R 1  and R 2 , the output voltage Vout can be set variably. 
     The first overvoltage protection circuit  16  has an output voltage detector  161 , a FB voltage detector  162 , and an AND circuit  163 . Thus, the configuration of the first overvoltage protection circuit  16  is similar to that of the first overvoltage protection circuit  3  in the first embodiment. The driver  14  continues or stops the switching operation according to the output from the AND circuit  163 . When performing overvoltage protection, the driver  14  turns off both the first switching element  11  and the second switching element  12 . 
     The operation of the first overvoltage protection circuit  16  is similar to that in the above embodiment. Briefly described, even in a case where the output voltage Vout is variably set with the resistors R 1  and R 2 , if the resistor R 1  becomes open or the resistor R 2  is short-circuited, the switching operation of the driver  14  is stopped by the first overvoltage protection circuit  16 , and protection against an overvoltage in the output voltage Vout is performed. Also, proper overvoltage setting in the respective output voltage detector  161  and the FB voltage detector  162  can be easily done. 
     The second overvoltage protection circuit  17  has a function similar to that of the second overvoltage protection circuit  4  in the first embodiment. 
     In the power supply IC  20 A according to this embodiment, usable instead of the first overvoltage protection circuit  16  is an overvoltage protection circuit with a configuration similar to that of the first overvoltage protection circuit  301  in the second embodiment. 
     Fourth Embodiment:  FIG.  8    is a diagram showing the configuration of a power supply circuit  40  according to a fourth embodiment of the present invention. The power supply circuit  40  shown in  FIG.  8    is a DC-DC converter, or more specifically, a synchronous rectification switching regulator. The power supply circuit  40  converts an input voltage Vin to an output voltage Vout. The power supply circuit  40  includes a power supply IC  40 A, a coil L 1 , a capacitor C 1 , and resistors R 1  and R 2 . The power supply IC  40 A is a power control device which controls the output voltage Vout of the power supply circuit  40  so as to keep it constant using a fixed on-time control method. The coil L 1 , the capacitor C 1 , and the resistors R 1  and R 2  are provided as components external to the power supply IC  40 A. 
     The power supply IC  40 A is a semiconductor integrated circuit having integrated in it a first switching element  21 , a second switching element  22 , a comparator  23 , an on-time generator  24 , a driver  25 , a first overvoltage protection circuit  26 , a second overvoltage protection circuit  27 , a power good portion  28 , an internal power supply portion  29 , a UVLO portion  30 , an enable controller  34 , and a soft starter  35 . The comparator  23 , the on-time generator  24 , the driver  25 , the first switching element  21 , and the second switching element  22  constitute an output voltage controller  36  which controls an output voltage Vout. The power supply IC  40 A has terminals, such as a terminal PVIN, via which to establish electrical connection with the outside. 
     To the source of the first switching element  21 , which is configured as a p-channel MOSFET, the input voltage Vin is applied via the terminal PVIN. The drain of the first switching element  21  is connected to the drain of the second switching element  22 , which is configured as an n-channel MOSFET. To the source of the second switching element  22 , an application terminal for a ground potential is connected via a terminal PGND. That is, the first switching element  21  and the second switching element  22  are connected in series between the input voltage Vin and the ground potential. 
     To the connection node at which the first switching element  21  and the second switching element  22  are connected together, one end of the coil L 1  is connected via a terminal SW. The other end of the coil L 1  is connected to one end of the capacitor C 1 . The other end of the capacitor C 1  is connected to the application terminal for the ground potential. To the connection node at which the coil L 1  and the capacitor C 1  are connected together, the output terminal Tout is connected. At the output terminal Tout, the output voltage Vout appears. 
     To a line on which the output voltage Vout appears, the application terminal for the ground potential is connected via a serially connected arrangement of the resistors R 1  and R 2 . The connection node at which the resistors R 1  and R 2  are connected together is connected to the inverting input terminal of the comparator  23  via a terminal FBS. To one non-inverting input terminal of the comparator  23 , a reference voltage Vref is applied. 
     The on-time generator  24  has the output of the comparator  23  input to it, and generates an on-time. The driver  25  drives the respective gates of the first switching element  21  and the second switching element  22  based on the output of the on-time generator  24 . By the driver  25 , the first switching element  21  and the second switching element  22  are switched complementarily. 
     A feedback voltage FB is generated by dividing the output voltage Vout with the resistors R 1  and R 2 . The generated feedback voltage FB is input to the comparator  23 . The on-time generator  24  generates a desired on-time when the output of the comparator  23  turns High. Here, the on-time generator suppresses frequency fluctuation by adjusting the on-time based on the input and output voltages. 
     The driver  25  keeps, only during the generated on-time period, the first switching element  21  on and the second switching element  22  off. When the on-time period expires, the driver  25  turns the first switching element  21  off and turns the second switching element  22  on. With this, the output voltage Vout is controlled so as to be constant. Through the setting of the external resistors R 1  and R 2 , the output voltage Vout can be set variably. 
     The first overvoltage protection circuit  26  has an output voltage detector  261 , a FB voltage detector  262 , and an AND circuit  263 . Thus, the configuration of the first overvoltage protection circuit  26  is similar to that of the first overvoltage protection circuit  3  in the first embodiment. To the output voltage detector  261 , the output voltage Vout is input via a terminal VOUTS. To the FB voltage detector  262 , the feedback voltage FB is input via the terminal FBS. The driver  25  continues or stops the switching operation according to the output from the AND circuit  263 . 
     The operation of the first overvoltage protection circuit  26  is similar to that in the above embodiments. Briefly described, even in a case where the output voltage Vout is variably set with the resistors R 1  and R 2 , if the resistor R 1  becomes open or the resistor R 2  is short-circuited, the switching operation of the driver  25  is stopped by the first overvoltage protection circuit  26 , and protection against an overvoltage in the output voltage Vout is performed. Also, proper overvoltage setting in the respective output voltage detector  261  and the FB voltage detector  262  can be easily done. 
     The second overvoltage protection circuit  27  has a function similar to that of the second overvoltage protection circuit  4  in the first embodiment. To the second overvoltage protection circuit  27  and the after-mentioned power good portion  28 , the feedback voltage FB is input via the terminal FBS. 
     In the power supply IC  40 A according to this embodiment, usable instead of the first overvoltage protection circuit  26  is an overvoltage protection circuit with a configuration similar to that of the first overvoltage protection circuit  301  in the second embodiment. 
     The power good portion  28  is a block to realize a power good function. The power good portion  28  controls a transistor Tr 1  to turn it on and off based on the feedback voltage FB. The drain of the transistor Tr 1 , which is an n-channel MOSFET, is connected to the terminal PGD, and the source of the transistor Tr 1  is connected to the application terminal for the ground potential. The terminal PGD is pulled up to the output terminal Tout by a resistor (unillustrated). When the feedback voltage reaches a predetermined voltage, the power good portion  28  turns off the transistor Tr 1  and outputs a High flag from the terminal PGD. 
     The terminal AVIN is a power terminal for the driver  25 , and is connected to the terminal PVIN. The internal power supply portion  29  is a circuit block that generates an internal power supply. The UVLO portion  30  is a block for preventing a low-voltage malfunction. The UVLO portion  30  shuts down the device when the voltage at the terminal AVIN becomes equal to or lower than a predetermined voltage. 
     The enable controller  34  shuts down the device when the terminal EN is Low, and enables the device when the terminal EN is High. 
     The terminal SS is a terminal for setting the soft start time, and is connected to the input terminal of the soft start portion  35 . The output terminal of the soft starter  35  is connected to another non-inverted input terminal of the comparator  23 . According to the capacitance value of a capacitor (unillustrated) connected to the terminal SS, the start-up time of the output voltage Vout can be variably set. 
     To the terminal VOUTS, one end of a resistor Rd is connected. To the other end of the resistor Rd, the drain of the transistor Tr 2 , which is an n-channel MOSFET, is connected. The source of the transistor Tr 2  is connected to the application terminal for the ground potential. When the device is shut down, the transistor Tr 2  turns on, and this discharges the output capacitor C 1 . Thus, the terminal VOUTS is a terminal for output voltage detection and output discharge. 
     A terminal MODE is a terminal for setting the switching control mode. According to the level of the signal applied to the terminal MODE, whether the device operates in a fixed-frequency mode forcibly or shifts between Deep-SLLM control and the fixed-frequency mode is switched. 
     A terminal RESERVE is a reserve terminal, and is connected to ground. A terminal AGND is a ground terminal for the driver  25 . 
       FIG.  9    is a plan view showing one example of the pin arrangement in the power supply IC  40 A as a semiconductor integrated circuit device (packaged product). The function of each terminal is as described above. 
     The power supply IC  40 A is in a rectangular shape as seen in a plan view, and has a first side  401  which extends laterally. Arranged in a lateral row along the first side  401  are the terminal PGND, the terminal PGND, the terminal VOUTS, and the terminal EN in the order named. The aim of providing a plurality of terminals PGND is to allow the plurality of wires to be connected together inside the package to reduce the ON-resistance of the second switching element  22 , thereby to improve efficiency. 
     A second side  402  extends longitudinally from one end of the first side  401 . Arranged in a longitudinal row along the second side  402  are the terminal SW, the terminal SW, the terminal SW, and the terminal PGND in the order named. The aim of providing a plurality of terminal SW is to allow the plurality of wires to be connected together inside the package to reduce the ON-resistances of the first switching element  21  and the second switching element  22 , thereby to improve efficiency. 
     A third side  403  extends laterally from an end part of the second side  402  opposite from the first side  401 . Thus, the third side  403  faces the first side  401  longitudinally. Arranged in a lateral row on the third side  403  are the terminal FBS, the terminal AGND, the terminal RESERVE, and the terminal MODE in the order named. 
     A fourth side  404  extends longitudinally from an end part of the third side  403  opposite from the second side  402 , and connects to an end part of the first side  401 . Thus, the fourth side  404  faces the second side  402  laterally. Arranged in a longitudinal row along the fourth side  404  are the terminal SS, the terminal AVIN, the terminal PVIN, and the terminal PVIN in the order named. The aim of providing a plurality of terminal PVIN is to allow the plurality of wires to be connected together inside the package to reduce the ON-resistance of the first switching element  21 , thereby to improve efficiency. 
     The rated voltages for all the terminals arranged on the fourth side  404  are high voltages. The rated voltages for all the terminals arranged on the third side  403  are low voltages. Thus, a group of high-voltage terminals and a group of low-voltage terminals are separated from each other. Of the terminals arranged on the first side  401 , the terminal EN, which is arranged on its end part near the fourth side  404 , has a high rated voltage, and the other terminals have low rated voltages. Thus, the terminal EN and the terminals arranged on the fourth side  404  make a high-voltage terminal group, which is thus separated from the low voltage group arranged on the first side  401 . 
     Of the terminals arranged on the second side  402 , the terminal PGD arranged on its end part near the third side  403  has a low rated voltage, and the other terminals have high rated voltages. Thus, the terminal PGD and the terminals arranged on the third side  403  makes a low-voltage terminal group, which is thus separated from the high-voltage terminal group arranged on the second side  402 . 
     A pad EXP-PAD is a bottom-side heatsink pad, and it is, when the IC is mounted on a board, connected to the ground plane inside the board with a plurality of vias. With this, satisfactory heat dissipation characteristics can be obtained. 
     Appliances incorporating the power supply circuits: The power supply circuits according to the embodiments described above are particularly suitable for devices that are required to be reliable, and can be incorporated into not only consumer products (such as mobile devices, game machines, and cameras) but also vehicle-mounted appliances, industrial equipment, medical equipment, and the like. 
       FIG.  10    is an exterior view showing an exemplary configuration of a vehicle incorporating various electronic appliances. The vehicle X of this exemplary configuration incorporates a battery X 10  and various electronic appliances X 11  to X 18  that operate by being supplied with an input voltage from the battery X 10 . It should be noted that, for the sake of convenient illustration, any of the battery X 10  and the electronic appliances X 11  to X 18  shown in  FIG.  10    may be elsewhere than they are actually located. 
     The electronic appliance X 11  is a traveling motor controller that controls the driving of a traveling motor. 
     The electronic appliance X 12  is a lamp control unit that controls the turning on/off of HID (high intensity discharged) lamps, DRLs (daytime running lamps), or the like. 
     The electronic appliance X 13  is a transmission control unit which performs control related to transmission. 
     The electronic appliance X 14  is a body control unit that performs control with respect to the movement of the vehicle X (such as the control of an ABS (anti-lock brake system), an EPS (electric power steering), an electronic suspension, and the like). 
     The electronic appliance X 15  is a security control unit which drives and controls door locks, burglar alarms, and the like. 
     The electronic appliance X 16  comprises electronic appliances incorporated in the vehicle X as standard or manufacturer-fitted equipment at the stage of factory shipment, such as wipers, power side mirrors, power windows, dampers (shock absorbers), a power sun roof, and power seats. 
     The electronic appliance X 17  comprises electronic appliances fitted to the vehicle X optionally as user-fitted equipment, such as vehicle mounted A/V (audio/visual) equipment, a car navigation system, and an ETC (electronic toll collection system). 
     The electronic appliance X 18  is electronic appliance provided with a high-withstand-voltage motor such as a vehicle-mounted blower, an oil pump, an water pump, and a battery cooling fan. 
     The power supply circuits according to the respective embodiments described above can be incorporated into any of the appliances X 11  to X 18 . 
     Modifications: The embodiments of the present invention described above allow for many modifications made without departing from the spirit of the present invention. 
     For example, the switching regulator to which the present invention is applied is not limited to the synchronous rectification type described above; it may instead be of a non-synchronous rectification type, a step-up/-down type, an isolated/non-isolated type, or the like.