Patent Publication Number: US-6223246-B1

Title: Computer system having an interrupt handler

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a computer system having an interrupt processing capability and more particularly to a computer system having an interrupt process capability therein independent of an operating system (hereinafter may be referred to as OS). 
     2. Description of Related Art 
     When the application system executed by microprocessors or the like becomes very large-scaled, there may be necessitated an exceptional process therefor. However, the performance of an OS and tasks managed by the OS is statically determined by the specifications of the real-time OS, thus it is rather difficult to change the predetermined performance. Moreover, it may become necessitated that some additional features be added to the application program. For example, a message in the midst of a message queue managed by the OS need be transferred to a task under a certain specific condition without contents of the task being altered. In such a case, the OS according to the related art does not allow for the message to be transferred to the task ignoring the order of transfer stored in the queue. 
     FIG. 1 is a block diagram showing a configuration example of related-art computer system. Referring to FIG. 1, a control unit  22  performing various processes is connected to a communication medium  21 . The control unit  22  executes a real-time OS  3  and thus executes application programs such as a task  4   1  through  4   n.  Data  51 , data  52 , data  53  and so on are stored in the message queue  23  in the control unit  22 . Task  41  receives data transmitted from a task which is being executed in another control unit (not shown), by way of the communication medium  21 . The real-time OS  3  is managed in such a manner that the data transferred is stored to the message queue  23 . How to manage the messages varies depending on the specifications of the real-time OS  3  in question. For example, the messages are managed and ordered in a first-in first-out (FIFO) fashion. 
     Referring to FIG.1, the FIFO method is carried out as follows: The real-time OS  3  receives a message request from among tasks  4   1  through  4   n . Assume now for convenience that the task  4   1  requests a message. Then, the real-time OS  3  hands over data to the requesting task  4   1  in the order in which the message is received by the real-time OS  3 . If there exists undefined data which requires an interrupt process, the real time OS  3  and task  4   1  perform as follows (see FIG.  2 ). 
     FIG. 2 is a flow chart showing processes of the real-time OS  3  and task when there exists, among messages requested by the task, an undefined datum which requires the interrupt process. Referring to FIG. 2, the task  4   1  requests the real-time OS  3  to re-send a message to the effect that the message received from the real-time OS  3  is not what the task  4   1  requested, that is, an undefined datum. Then, the real-time OS  3  performs a message re-sending process (STEP S 901 ). Next, the real-time OS  3  adds a message obtained as a result thereof to the tail of a message queue  23  (STEP S 902 ). Next, the real-time OS  3  removes a message in the head of the message queue  22  (STEP S 903 ). Next, the task  4   1  determines whether or not the removed message is the one requested to be re-sent (STEP S 904 ). When the removed message is found to be the one requested to be re-sent, the real-time OS  3  transfers the re-sent message to the task  4   1  (STEP S 905 ). When the STEP S 904  determines that the removed message is not the one requested to be re-sent, the process returns to STEP S 902  for another processing. 
     If there are many messages stored in the message queue  23 , performing such a process mentioned above takes time such that the processing time increases proportional to the number of messages stored. It takes time until the task receives the message which is requested to be re-sent, thus deteriorating the responsibility of computer system. 
     Moreover, it is not possible for the task to predict in advance how many messages are put in the message queue  23 . It is also not possible to predict the degree to which the responsibility is deteriorated thereby. 
     Accordingly, in the computer system according to the related art, the development of another extra operating system is needed in order that an exceptional procedure can be achieved to change the OS and task. On the other hand, the task related thereto need be changed if the task is to be changed without implementing the extra operating system. Thus, the amount of tasks to be changed becomes enormous, thus deteriorating productivity of software therefor. 
     Moreover, various events occur as the application program becomes huge. Thereby, it becomes necessary to carry out a process responsive to each condition due to combination of the events, so that the event management becomes complicated. 
     Moreover, the increased processing time is required to recognize such conditions. Consider a case where limited is the time required for carrying out the process responsive to certain condition after the event such as a message re-sending request occurs. In this case, the increase in processing time not only results in deterioration of responsibility but also may cause a fatal outcome, for example, in terms of safety in an application system where a system need be stopped to secure safety in the event that a certain condition occurs. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing drawbacks, it is therefore an object of the present invention to provide a computer system as wells as a control method therefor capable of handling exceptional procedures by performing interrupt processes with desirable responsibility so that making changes in the operating system and tasks are avoided and a simple configuration is achieved. 
     According to one preferred embodiment of the present invention, there is provided a control method for the computer system having interrupt capability therein, comprising the steps of: referring to at least one flag pattern in an interrupt activation condition flag storing unit which stores an event as an interrupt activation condition flag; thereafter determining whether or not the flag pattern exists in an operational key description storing unit which stores the position for the operation corresponding to the flag pattern in the interrupt activation condition flag storing unit; performing the interrupt process based on an operational description storing unit which stores a process corresponding to the flag pattern, in the event that there exists such the flag pattern as a result of the determining step; and thereafter resetting a bit of the flag corresponding to the process executed. 
     According to the configuration realizing such a control method, a flag operation is carried out in accordance with an event that occurs such that the interrupt process is performed responsive to this flag pattern. Thereby, making undue changes in the operating system as well as in tasks such as an application program are avoided so as to achieve a simple configuration. Thus, exceptional procedures can be handled by the interrupt processes with desirable responsibility. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The objects, features and advantages of the present invention will become more apparent from the following description of the preferred embodiment taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram for an example of the computer system configuration according to the related art. 
     FIG. 2 is a flowchart showing processes of a real-time OS  3  and task in the related art. 
     FIG. 3 is a block diagram showing the schematic configuration of a computer system according to the present invention. 
     FIG. 4 shows an interrupt activation condition flag storing unit  11 . 
     FIG. 5 shows an interrupt activation condition flag  11  according to an embodiment of the present invention. 
     FIG. 6 is an example of an operational key description storing unit a unit  16 . 
     FIG. 7 is an example of an operational description storing unit  17 . 
     FIG. 8 is a flowchart showing a process for an interrupt activation unit  12  in the event that a flag is written to the interrupt activation condition flag storing unit  11 . 
     FIG. 9 is a flowchart showing STEP S 403  (shown in FIG. 8) in detail. 
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. 
     FIG. 3 is a block diagram showing the schematic configuration of a computer system according to the present invention. Referring to FIG. 3, an interrupt activation condition flag storing unit  11  is a region for storing an interrupt activation condition flag, and the interrupt activation condition flag storing unit  11  includes a memory unit such as a register. The interrupt activation condition flag storing unit  11  is a region for storing an event occurrence due to an external interrupt factor and for storing the completion of a specific condition in a real-time OS  13 . 
     A single event occurrence can be managed by at least one bit in the storing unit. The real-time OS  13  performs the flag operation on the interrupt activation condition flag storing unit  11 . In other words, the real-time OS  13  writes data to the interrupt activation condition flag storing unit  11 . For example, the real-time OS  13  is notified of the event from an application program  14 . Upon being notified of the event, the real-time OS  13  performs the flag operation on a flag in the interrupt activation condition flag storing unit  11  when a specific condition is satisfied. Moreover, in the event that there occurs an interrupt factor such as an external equipment (not shown), a unit  15  equipped in this external equipment for detecting external interrupt factor performs the flag operation on the interrupt activation condition flag storing unit  11 . The interrupt activation condition flag storing unit  11  notifies an interrupt activation unit  12  of occurrence of interrupt when the flag operation was performed. 
     When notified of the occurrence of an interrupt, the interrupt activation unit  12  refers to an operational key description storing unit  16 . A key corresponding to the flag pattern in the interrupt activation condition flag storing unit  11  is being stored in the operational key description storing unit  16 . The operational key description storing unit  16  stores data by which the operation described in an operational description storing unit  17  performs efficiently. For example, an address or label corresponding to the flag pattern of the interrupt activation condition flag storing unit  11  is described. An interrupt processing program corresponding to each specific pattern indicated by the interrupt activation condition flag storing unit  11  is described in the operational description storing unit  17 . An address for each interrupt processing program is stored in the operational key description storing unit  16 . The operational key description storing unit  16  as well as the operational description storing unit  17  are stored in memory means such as a memory or the like. 
     Next, an operation for a computer system according to an embodiment of the present invention is described. The computer system according to the embodiment is managed by a flag written in the interrupt activation condition flag storing unit  11 . Thereby, the interrupt processes responsive to the combination of a plurality of events are executed independent of the real-time OS. In this embodiment, the event is meant to be the interrupt due to an undefined datum detected as well as external event. 
     FIG. 4 shows an interrupt activation condition flag storing unit  11 . Considered in the embodiment is a computer system which is equipped with a port for use with interrupt activation as shown in FIG.  4 . This port for use with interrupt activation is considered as an interrupt activation condition flag storing unit. For example, that the interrupt activation condition flag storing unit  11  is of 16 bit means that the manageable events are  16 . When the bit for the port is set due to a certain external factor, an interrupt corresponding to that position of the bit occurs. Moreover, this port can be written and read by a software, and the interrupt corresponding to the bit can occur also if the bit for the port is set by the software. 
     FIG. 5 shows an interrupt activation condition flag storing unit  11  explained hereinbelow. Referring to FIG. 5, the interrupt activation condition flag storing unit  11  is taken as 3 bits for convenience. As shown in FIG. 5, let the flag storing unit be labeled A, B, and C in this order from the left to the right. “A” bit is a flag indicating whether or not an undefined data is detected . “B” bit is a flag indicating whether or not there is an external interrupt factor which occurred in a specific external equipment. First of all, the application program  14  requests a message from the real-time OS  13 . When the message transferred from the real-time OS  13  is detected as being an undefined datum, the real-time OS  13  is notified accordingly. In this case, the real-time OS  13  writes a flag “1” to the “A” bit portion in the interrupt activation condition flag storing unit  11  shown in FIG.  5 . When an external interrupt factor which occurred in the external equipment controlled by the application program  14  is detected by an external interrupt factor detecting unit  15 , the external interrupt factor detecting unit  15  writes a flag “1” to the “B” bit portion in the interrupt activation condition flag storing unit  11  shown in FIG.  5 . 
     In this embodiment, the messages need be replaced only when both the undefined data is detected and the external interrupt factor occurred . In other words, the messages are replacement-processed at the time the flag pattern in the interrupt activation condition flag storing unit  11  shown in FIG. 5 becomes “110” ( at the time both the undefined data is detected and the external interrupt factor occurred). See FIG. 9 where the replacement process is described in detail in STEP S 703  in FIG.  9 . In the event of the flag operation, the interrupt activation unit  12  refers to a key corresponding to the current flag pattern from the operational key description storing unit  16 . 
     FIG. 6 is an example for an operational key description storing unit  16 . Referring to FIG. 6, a label corresponding to a flag pattern in the interrupt activation condition flag storing unit  11  is described in the operational key description storing unit  16 . For example, when the flag pattern is “001”, a label indicating the location of the interrupt processing program corresponding to the pattern is described therein. Hence, if the assumed flag pattern was “110”, an operation therefor is described in the position of the label flg 110 . Next, the interrupt activation unit  12  executes a program described in a label flg 110 . 
     FIG. 7 is an example of the operational description storing unit  17 . Referring to FIG. 7, a program corresponding to the label flg 110  is described in this operational description storing unit  17 . Thus, the interrupt activation unit  12  executes this program as an interrupt process. 
     FIG. 8 is a flowchart showing a process for the interrupt activation unit  12  in the event that a flag is written to the interrupt activation condition flag storing unit  11 . Referring to FIG. 8, first of all, the current flag pattern is examined (STEP S 401 ). Thereafter, it is determined whether or not the current flag pattern is the assumed flag pattern (STEP S 402 ). Determination therefor is based upon whether or not the flag pattern is described in the operational description storing unit  16 . Thereafter, if the current flag pattern is the assumed flag pattern, an operation responsive to the flag is executed (STEP S 403 ). Thereafter, the bit for the flag in the interrupt activation condition flag storing unit  11  responsive to the executed process is reset (STEP S 404 ) so as to return from the interrupt process. If the current flag pattern is not the assumed flag pattern in STEP S 402 , then an original process is resumed and returns from the interrupt process. 
     FIG. 9 is a flowchart showing STEP S 403  (shown in FIG. 8) in detail. Referring to FIG. 9, first of all, the request to re-send a message is carried out (STEP S 701 ). After receiving the resent message as a result thereof, the head of a message in the message queue is removed (STEP S 702 ). Thereafter, the resent message is inserted to the head in the message queue (STEP S 703 ). 
     Hence, the interrupt process shown in the flowchart in FIG. 8 changed the performance of the real-time OS  13  without being restricted by the operation of the real-time OS  13 , so that resent message is immediately transferred to the application program  14 . The application program  14  performs the process by utilizing this resent message. 
     Accordingly, by employing the embodiment for the present invention where the resent message is inserted to the head of message in the message queue, there is no need for a search process in which messages are repeatedly replaced. Thereby, it becomes possible to estimate time for processing. Moreover, in spite of exceptional processes, desirable responsibility can be achieved. Thereby, the process is facilitated to be completed within a predetermined time period even if the process in question has a severe time constraint. 
     Moreover, by implementing the present invention where the events are administered and managed by the internal event of the real-time OS  13  and the external interrupt factors and the like, the processes independent of the real-time OS  13  can be performed regardless of internal condition within the real-time OS  13 . Thereby, new features can be added without making changes in the real-time OS  13  and application program  14 , moreover, the interrupt process due to combination of the events can be carried out with ease. 
     Though the external equipment is controlled by the application program  14  in the above-mentioned embodiment, it may be implemented independently of the application program  14 . 
     The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiment is therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.