Patent Publication Number: US-2013232455-A1

Title: Error diffusion and grid shift in lithography

Description:
BACKGROUND 
     The semiconductor industry has experienced exponential growth. Continuous advancements in lithographic resolution have been made to support critical dimensions (CDs) of 90 nm to 65 nm, 45 nm, 32 nm, 22 nm, 16 nm and beyond. New techniques in lithography have been developed, such as immersion lithography, multiple patterning, extreme ultraviolet (EUV) lithography and e-beam lithography. The challenges being raised by new lithography techniques are not only in resolution but also in economy (e.g. cost of upgrading and loss of throughput). Much development has focused on improving resolution without significant reduction in process throughput. However, current methods have not been satisfactory in all respects. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a flowchart of an example method of a data preparation in lithography processes at stages constructed according to various aspects of the present disclosure. 
         FIG. 2  is a simplified schematic diagram of an IC layout design GDS grip of an example embodiment of a method of data preparation in lithography processes at stages constructed according to various aspects of the present disclosure. 
         FIG. 3  is a simplified schematic diagram of a first exposure grid of an example embodiment of a method of data preparation in lithography processes at stages constructed according to various aspects of the present disclosure. 
         FIG. 4  is a simplified schematic diagram of generation of a second exposure grid of an example embodiment of a method of data preparation in lithography processes at stages constructed according to various aspects of the present disclosure 
         FIG. 5  is a simplified schematic diagram of grey level spectrums of an example embodiment of method of data preparation in lithography process at stages constructed according to various aspects of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. 
     According to an embodiment of the present disclosure, a method  100  of data preparation in lithography processes is illustrated as a flowchart in  FIG. 1 . The method  100  includes blocks  102 - 110 , each of which is discussed below in more detail and with reference to examples in various additional figures. 
     Referring to  FIGS. 1 and 2 , the method  100  begins at step  102  by providing an IC layout design in a GDS grid  200 . The IC layout design may contain a plurality of semiconductor features. The IC layout design may be generated as a computer file, for example as a GDS type file or as an open artwork system interchange standard (OASIS) type file. The GDS or OASIS files are database files used for data exchange of IC layout artwork. For example, these files may have binary file formats for representing planar geometric shapes, text labels, as well as other layout information of the IC layout. The GDS or OASIS files may each contain multiple layers. The GDS or OASIS files may be used to reconstruct the IC layout artwork, and as such can be transferred or shared between various fabrication tools. 
     A proximity correction process may also apply to the GDS grid  200 . The proximity correction process is a lithography enhancement technique that can be used to compensate for image errors due to process defects. For example, electron scattering during the performance of a maskless lithography process may adversely impact regions of the substrate near the region that is being exposed by the electron beams. Consequently, these nearby regions may become inadvertently exposed, thereby causing variations of the desired exposure pattern. To compensate for these image errors, proximity correction techniques such as dose modification, shape modification, or background correction exposure may be employed in a maskless lithography process. The performance of the proximity correction process in the GDS grid  200  makes the fabricated semiconductor feature patterns resemble the desired patterns more accurately. 
     For the sake of providing an example, a simplified IC layout design GDS grid  200  is illustrated in  FIG. 2 . The IC layout design GDS grid  200  includes a plurality of circuit sections  210 - 230 , represented by a plurality of polygons. In the illustrated embodiment, the circuit sections  210 - 230  may include different logic sections and varying sizes. The sizes may refer to physical dimensions of the circuit sections  210 - 230  or the amount of data that is contained within each section. The IC layout design GDS grid  200  includes a two-dimensional array of pixels. Pixels are often represented using dots or squares in a coordinate system. Each pixel has an exposure intensity value (represented by a digital number) and a location address (corresponding to its coordinates). 
     Continuing with  FIG. 2 , a pixel size of the GDS grid  200  is selected typically to make boundaries of layout design pattern (such as polygons) fairly align with boundaries of pixels in the IC layout design GDS grid  200 , as shown in  FIG. 2 . Pixels in the IC layout design GDS grid  200  are divided into two types: either interior or exterior of the polygon of the IC layout design. For an interior pixel (or an exterior pixel), a lithography exposure does is set at maximum intensity (or at minimum intensity), which is referred to as a black color or a white color, respectively. 
     The method  100  proceeds to step  104  by converting the IC layout design GDS grid  200  to a sub-pixel exposure grid  300 , a machine-specific form, as shown in  FIG. 3 . In order to implement the IC layout design GDS  200  by a lithography machine, a data preparation process is carried out to form a machine-specific data format. The data preparation process starts with converting the IC layout design GDS grid  200  to a machine-specific exposure grid, referred to as a sub-pixel exposure grid  300 . The sub-pixel exposure grid  300  may include a two-dimensional array of pixels in a coordinate system. A lithography exposure process sweeps across the entire surface of a substrate to be patterned, pixel by pixel (or pixels by pixels). The pixel size of the sub-pixel exposure grid  300  impacts not only computing data volume in the data preparation process but also on the throughput in the downstream or later processing. 
     The pixel size of the sub-pixel exposure grid  300  is selected to be typically larger than the pixel size of the IC layout design GDS  200  for gaining process throughput. For example, a pixel size in the IC layout design GDS  200  is 0.1 nm and a pixel size in the sub-pixel exposure grid  300  is 3 nm, which is 30 times larger. In the present embodiment, the pixel size of the sub-pixel exposure grid  300  is set as from 0.5 nm to 8.0 nm. When the pixel size of the sub-pixel exposure grid  300  is larger than the IC layout design GDS grid  200 , the boundaries of polygons (of the IC layout design) may not match with the boundaries of pixels in some locations in the sub-pixel exposure grid  300 , such as in  310 A,  310 B,  320 A and  320 B, as shown in  FIG. 3 . This mismatching generates partial filled pixels in the sub-pixel exposure grid  300 , referred to as pixel size truncations. The larger pixel size may result in less amount of computation required in the downstream or later processing, but induces more image errors. 
     The method  100  proceeds to step  106  by applying an error-diffusion to the sub-pixel exposure grid  300 , as shown in  FIG. 4 . After receiving the error-diffusion, the sub-pixel exposure grid  300  is referred to as the sub-pixel exposure grid  300   a.  An error diffusion is a computer graphics technique. As an example, an error diffusion algorithm scans a pixel grid from left to right, top to bottom, quantizing pixel values one by one. A data of an exposure intensity level (referred as to a grey level) is assigned to each pixel. In the error diffusion algorithm, the grey level of a pixel (referred to as a source pixel) is compared to a predetermined grey-level scale, such as the discrete grey-level scales. When the source pixel is completely inside (or outside) of a polygon (the IC layout design feature), the grey level of the source pixel is set to be the maximum (or minimum) of grey-level in the predetermined grey-level scale. When a source pixel is on the polygon edge (hence not completely inside nor completely outside a polygon), the grey level of the source pixel is set to be the closest grey level in the predetermined grey-level scale, now the pixel is referred to as a output pixel. After outputting the pixel, the error diffusion algorithm calculates the difference between the source pixel and the output pixel (a simple subtraction), and then it spreads this difference (referred to as an “error”) over neighboring pixels. 
     For example, in a simple two dimensional error diffusion algorithm, half of the error is added to the next right pixel, one quarter of the error is added to the pixel on the next line below, and another quarter of the error is added to the pixel on the next line below and one pixel forward. 
     A further refined error diffusion algorithm can disperse the error further away from the current pixel. In the depicted embodiment, a Floyd-Steinberg error diffusion algorithm is applied to the sub-pixel exposure grid  300 . In the Floyd-Steinberg error diffusion algorithm, the pixel immediately to the right of the pixel being quantized gets 7/16 of the error (the divisor is 16 because the weights add to 16), the pixel directly below the pixel of being quantized gets 5/16 of the error, and the diagonally adjacent pixels of the pixel being quantized get 3/16 and 1/16. 
     Alternately, the error diffusion algorithm may includes a modified Floyd-Steinberg error diffusion algorithm, referred to as Fan error diffusion. In the Fan error diffusion, the pixel immediately to the right of the pixel being quantized gets 7/16 of the error, the pixel directly below the pixel being quantized gets 5/16 of the error, the pixel immediately to the left and directly below the pixel being quantized gets 3/16 of the error and the pixel two to the left and directly below the pixel being quantized gets 1/16 of the error (the divisor is 16 because the weights add to 16). 
     By using error diffusion technique, each time the quantization error is transferred to neighboring pixels, while not affecting the pixels that have already been quantized. An error diffusion technique can successfully make a digitization system be a more analog-like system. Error diffusion is able to increase the filling resolution without reducing the pixel size. Error diffusion results in such a way that the more pixels being rounded downwards, the more likely that the next pixel will be rounded upward. As an average, the quantization error is close to zero. 
     During the error diffusion process, the lithography exposure intensity is quantized. Referring to  FIG. 5 , from a continuous grey-level spectrum to a discrete grey-level scales  500 B. A maximum exposure dose of the discrete grey-level scales  500 B is usually set to be the same as the dose used for the black color pixel and the minimum exposure dose of the discrete grey-level scales  500 B is usually set to be the same as the one used for the white color pixel, or vice versa. A grey level error is induced when converting from a grey-level spectrum to a discrete grey-level scale. For example, in the grey-level spectrum  500 A, all different grey-levels between the level  510 A and the level  510 B are converted to one grey-level  510 C in the discrete grey-level scales  500 B. In another words, one grey-level  510 C represents all different levels between the level  510 A and  510 B. An error induced by quantization of grey level is referred to as grey-level truncation. 
     The exposure dose intensity (grey level) delivered to each pixel is controlled by a quantization state of data bits stored in the sub-pixel exposure grid  300   a.  For example, if 6 bits are used, a total of 64 grey levels are established in the discrete grey-level scales  500 B, from a grey level zero (white color) to a grey level 63 (black color). The more divided the levels of discrete grey-level scales  500 B, the closer to the spectrum  500 A, the more accurate the grey-level, the more bits are used, and the larger the data volume to be stored and to be computed in data preparation, in the downstream or later processing. 
     The pixel size truncation and grey-level truncation may induce errors in critical dimension (CD) control and CD uniformity (CDU). The conventional methods to solve pixel size truncation and grey-level truncation are reducing pixel and using more data bit for grey-level scales with a cost of a larger data volume and a longer cycle time in data preparation. 
     A normalized data volume (NDV) is introduced here to evaluate and compare data volume among different data preparation algorithms. The NDV is defined as data volume per unit area of pixel. The NDV can be calculated from: 
       NDV=GreyLevel (bit)/(Pixel Size) 2  (nm 2 ) 
     For example, if the amount of bit used for grey level is k, the GreyLevel (bit) is GreyLevel (k). Under this condition, each pixel&#39;s exposure intensity (referred to as grey level) is coded by using a k-bit-digital number. The NDV represents a normalized data volume by a density of allowed grey levels per unit area. As an example, when pixel size of the sub-pixel exposure grid 300 is p nm and the grey level uses k bit (which allows different grey levels of 2 to (bit) th  power), the NDV of the sub-pixel exposure grid  300  equals to GreyLevel (k)/p 2 . 
     In the depicted embodiment, the grey level of the sub-pixel exposure grid  300   a  (after receiving the error-diffusion) may be selected to be less than the sub-pixel exposure grid  300 . For example, if the grey level of the sub-pixel exposure grid  300  uses k bit (which allows grey levels of 2 to (bit) th  power), the grey level of the sub-pixel exposure grid  300   a  uses (k−1) [which allows half of grey levels of 2 to (bit) th  power]. 
     The method  100  proceeds to steps  108   a  and  108   b  in parallel. In the step  108   a,  the sub-pixel exposure grid  300   a  (after receiving the error-diffusion) coverts to an exposure grid  400 , as shown in  FIG. 4 . In the present embodiment, the pixel size of the exposure grid  400  is set as two times of the pixel size in the sub-pixel exposure grid  300 . The grey-level of the exposure grid  400  is set to use (k−1) bits, same as the sub-pixel exposure grid  300   a.  Thus the NDV of the exposure grid  400  equals to ¼ of the sub-pixel exposure grid  300 . 
     Referring also to  FIG. 4 , in the step  108   b,  a grid-shift technique is applied to the sub-pixel exposure grid  300   a  to create a grid-shifted exposure grid  410 . For a two-dimension coordinate system of the sub-pixel exposure grid  300   a,  a grid shift may include shifting the coordinate system along a first direction, or along a second direction, or along both the first and the second directions. In the present embodiment, the coordinate system of the sub-pixel exposure grid  300   a  shifts one pixel size of the sub-pixel exposure grid  300   a  in both of the first and the second directions The grid-shifted exposure grid  410  may use a pixel size larger than the pixel size as the sub-pixel exposure grid  300 . The grid-shifted exposure grid  410  also may use less bits for the grey level than the sub-pixel exposure grid  300 . In the present embodiment, the grid-shifted exposure grid  410  uses pixel size of two times of the pixel size of the sub-pixel exposure grid  300  and uses (k−1) bits for the grey level. Here the grid shifting for the grid-shifted exposure grid  410  is referred to as a ½ grid shift due to the grid shifting in each direction is half of pixel size of the grid-shifted exposure grid  410 . The NDV of the grid-shifted exposure grid  410  equals to ¼ of the NDV of the sub-pixel exposure grid  300 . 
     Another of the broader forms of the present disclosure involves applying multiple grid shifts to the sub-pixel exposure grid  300   a.  The grid shift direction can be independent of each other. The displacement of the grid shift can be independent of each other also. 
     The method  100  proceeds to step  110  by adding the exposure grid  400  (from the step  108   a ) to the grid-shifted exposure grid  410  (from the step  108   b ) to form a second exposure grid  450 , as shown in  FIG. 4 . In the present embodiment, the pixel size and the grey-level of the second exposure grid  450  are same as the exposure grid  400  and the grid-shifted exposure grid  410 . Thus the second exposure grid  450  has a pixel size of 2p nm and uses a grey level of (k−1) bits. The NDV of the second exposure grid  450  is the sum of the NDV of the exposure grid  400  and the NDV of the grid-shifted exposure grid  410 , shown below: 
     
       
         
           
             
               
                 
                   
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     Where NDV 450  is the NDV of the second exposure grid  450 , k is the amount of bits being used for the grey level, and NDV 300  is the NDV of the sub-pixel exposure grid  300 . It is shown that the data volume (represent by NDV) of the second exposure grid  450  is half of the sub-pixel exposure grid  300 . It has been demonstrated that, with fairly reduced data volume, the second exposure grid  450  achieves a lower critical dimension (CD) error, a better CD uniformity and a lower center mass error than the sub-pixel exposure grid  300 . 
     Base on the discussions above, it can be seen that the present disclosure offers a new data preparation algorithm for lithography process by applying a combination of error diffusion and multiple-grid (MG) shift techniques and a approaching of a sub-pixel size grid. The new data preparation algorithm showed reductions of center mass error and truncation error and improvements of CD control and uniformity without increasing data volume. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.