Patent Publication Number: US-7715484-B2

Title: Orthogonal frequency division multiplexing with PN-sequence

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an orthogonal frequency division multiplexing system, and particularly, to an orthogonal frequency division multiplexing system with PN-sequence. 
   2. Description of the Related Art 
   A large number of references related to the orthogonal frequency division multiplexing (OFDM) synchronization algorithm exist, and can be divided into the time domain and the frequency domain according to the types of solution, i.e. before and after the Inverse Fast Fourier Transform (IFFT), or into the Non-Data-Aided (also known as blind estimation) and Data-Aided according to data mode, both of which usually use training symbols or cyclic prefixes, pilot symbols and so on. 
   The concept of using the cyclic prefix is mainly that every OFDM symbol has periodicity after being added with a cyclic prefix, so we only need to use a correlator to estimate the correlation of the cyclic prefixes in the OFDM symbols, and through the Maximum Likelihood Estimation Algorithm, easily calculate the starting point of each OFDM symbol and the offset of carrier frequency as described in the prior related art reference (1) J. J. van de Beek, M. Sandel, and P. O. Borjesson, “ML estimation of timing and frequency offset in OFDM systems,” IEEE Trans. Signal Processings, vol. 45, pp. 1800-1805, July 1997 and U.S. Pat. No. 5,889,759. 
   The concept of using the training symbol to perform synchronization is that the two PN-sequences in the frequency domain may become periodic time domain signals after passing the IFFT at a transmitting terminal, and the synchronization of timing offset can be accomplished by acquiring the timing metric for estimating time through the operation of the correlation and calculating the maximum of the timing metric though the Maximum Likelihood Estimation Algorithm. In addition, the concept of using the timing metric to estimate the frequency offset is mainly that the first training symbol is the equal data of N/2 length in the timing domain, and thus the frequency offset can make the two equal data have a phase shift expressed by φ=π{circumflex over (ε)}, in which {circumflex over (ε)} is the frequency offset to be estimated. Therefore, the estimation of frequency offset can be accomplished by just calculating the angle of timing metric and dividing the angle by π as described in the prior related art references (2) Schmidl, T. M. and Cox, D. C., “Robust frequency and timing synchronization for OFDM”, IEEE Transactions on Communications, vol. 45, pp. 1613-1621, December 1977.; (3) P. H. Moose, “A technique for orthogonal frequency division multiplexing frequency offset correction,” IEEE Trans. Commun., vol. 42, pp. 2908-2914, October 1994 and Republic of China Patent Nos. 567689 and No. 560148. 
   In addition, in the prior related art reference (4) Landstrom, D., Wilson, S. K., van de Beek, J.-J., Odling, P., Borjesson, P. O., “Symbol time offset estimation in coherent OFDM systems,” IEEE Transactions on Communications, vol. 50, pp. 545-549, April 2002, the methods of the pilot symbol and the cyclic prefix are combined. Though the synchronization method just based on the cyclic prefix can be improved, the position of the pilot symbol must be arranged properly, thereby achieving a better performance. 
   The methods mentioned above are all data-aided methods. Though the method is of less complexity, due to the addition of extra data, the bandwidth utilization is lowered consequently, which is the biggest disadvantage of using the conventional data-aided method. 
   Therefore, it is necessary to provide an orthogonal frequency division multiplexing system to solve the above problems. 
   SUMMARY OF THE INVENTION 
   The invention relates to an orthogonal frequency division multiplexing system with PN-sequence. The orthogonal frequency division multiplexing system comprises a modulate circuit, an Inverse Fast Fourier Transformer, a PN-sequence generating circuit, a cyclic prefix inserter, a first adder, a time and frequency synchronization device, a cyclic prefix remover, a Fast Fourier Transformer and a demodulate circuit. 
   The modulate circuit is used to modulate a signal to be transmitted to a complex number frequency domain signal at a transmitting terminal. The Inverse Fast Fourier Transformer is used to transform the complex number frequency domain signal at the transmitting terminal to a complex number time domain signal at the transmitting terminal. The PN-sequence generating circuit is used to generate a PN-sequence signal. The cyclic prefix inserter is used to add cyclic prefixes to the complex number time domain signal at the transmitting terminal and the PN-sequence signal respectively. The first adder is used to sum up the complex number time domain signal at the transmitting terminal and the PN-sequence signal, both of which have cyclic prefixes, to form a transmitting signal. The time and frequency synchronization device is used to receive a receiving signal formed by the transmitting signal though a channel, and for calculating and compensating the timing offset and frequency offset of the receiving signal. The cyclic prefix remover is used for removing the cyclic prefix of the receiving signal after compensated by the time and frequency synchronization device. The Fast Fourier Transformer is used for transforming the receiving signal with the cyclic prefix removed to a complex number frequency domain signal at a receiving terminal. The demodulate circuit is used for demodulating the complex number frequency domain signal at the receiving terminal to a receiving terminal signal. 
   The orthogonal frequency division multiplexing system of the invention is to add a PN-sequence with cyclic prefix to each OFDM symbol before transmitting. The time and frequency synchronization device of the invention comprises two synchronization circuits from the cyclic prefix and PN-sequence during calculating the timing offset and frequency offset of receiving signal. As a result, the OFDM system of the invention not only has better performance in fading channel, but also has better bandwidth utilization without extra bandwidth for transmitting the PN-sequence. Therefore, the architecture of the orthogonal frequency division multiplexing system of the invention may be better than that of the conventional synchronization system, which just utilizes the cyclic prefix. Moreover, to add PN-sequence to each OFDM signal will not decrease the bandwidth utilization but will optimize the performance of synchronization at the receiving terminal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of the orthogonal frequency division multiplexing system of the invention; 
       FIG. 2  is a schematic diagram of the OFDM symbols of the invention; 
       FIG. 3  is a schematic diagram of the timing offset synchronization device of the invention; 
       FIG. 4  is a schematic diagram of the first timing offset synchronization circuit of the invention; 
       FIG. 5  is a schematic diagram of the second timing offset synchronization circuit of the invention; 
       FIG. 6  is a schematic diagram of the frequency offset synchronization device of the invention; 
       FIG. 7  is a schematic diagram of the first frequency offset synchronization circuit of the invention; and 
       FIG. 8  is a schematic diagram of the second frequency offset synchronization circuit of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Referring to  FIG. 1 , it shows a schematic diagram of the orthogonal frequency division multiplexing system of the invention. The orthogonal frequency division multiplexing system  10  of the invention includes a modulate circuit  11 , an Inverse Fast Fourier Transformer  12 , a PN-sequence generating circuit  13 , a first cyclic prefix inserter  14 , a second cyclic prefix inserter  15 , a first adder  16 , a time and frequency synchronization device  20 , a cyclic prefix remover  17 , a Fast Fourier Transformer  18  and a demodulate circuit  19 . 
   The modulate circuit  11  is used to modulate a signal to be transmitted to a complex number frequency domain signal at a transmitting terminal. The Inverse Fast Fourier Transformer  12  is used to transform the complex number frequency domain signal at the transmitting terminal to a complex number time domain signal at a transmitting terminal. The PN-sequence generating circuit  13  is used to generate a PN-sequence signal. The first cyclic prefix inserter  14  is used to add cyclic prefixes to the complex number time domain signal at the transmitting terminal. The second cyclic prefix inserter  15  is used to add the cyclic prefix to the PN-sequence signal. The first adder  16  is used to sum up the complex number time domain signal at the transmitting terminal and the PN-sequence signal, both of which have cyclic prefixes, to form a transmitting signal. 
   Referring to  FIG. 2 , it shows the orthogonal frequency division multiplexing system of the invention, in which a PN-sequence with cyclic prefix is added to each OFDM symbol before transmitting, and the transmitted signal is shown in  FIG. 2 . The length of the cyclic prefix is L. The length of IFFT is N. The start point of the OFDM symbol is θ. Under this architecture, the orthogonal frequency division multiplexing system of the invention observes the 2N+L sampling point of the receiving signal by using the Maximum Likelihood Estimation Algorithm. 
   Referring to  FIG. 1  again, the transmitting signal forms a receiving signal though a channel (timing offset) and frequency offset. The time and frequency synchronization device  20  is used for receiving the receiving signal and for calculating and compensating the timing offset and frequency offset of the receiving signal. It includes a timing offset synchronization device  30 , a frequency offset synchronization device  60  and a compensation device  90 . The timing offset synchronization device  30  is used for calculating the timing offset of the receiving signal, and the frequency offset synchronization device  60  is used for calculating the frequency offset of the receiving signal and the compensation device  90  is for compensating the receiving signal according to the timing offset and the frequency offset. 
   Referring to  FIG. 3 , it shows a schematic diagram of the timing offset synchronization device  30  of the invention. The timing offset synchronization device  30  includes a first timing offset synchronization circuit  40 , a second timing offset synchronization circuit  50 , a first multiplier  31 , a second multiplier  32 , a second adder  33  and a first maximum value circuit  34 . The timing offset synchronization device  30  calculates the timing offset according to the following equation (1) which is derived from MLE criterion: 
                   θ   ^     =       arg   ⁢           ⁢       max   θ     ⁢     {     Λ   θ     }         =     arg   ⁢           ⁢       max   θ     ⁢       {       ρΛ   θ   CP     +       α   ⁡     (     1   -   ρ     )       ⁢     Λ   θ   PN         }     .                   (   1   )               
where α is the channel amplitude response, ρ=β 2 SNR/(β 2 SNR+1) and SNR is the signal to noise ratio. According to equation (1), the proposed timing synchronization method is based on the SNR level. For a large signal to noise ratio, the estimation chiefly relies on the cyclic prefix (Λ θ   CP ), whereas for a low SNR, the estimator depends on the information of the PN sequence (Λ θ   PN ).
 
   The first timing offset synchronization circuit  40  is for generating a first timing metric (Λ θ   CP ) formed by the cyclic prefix. The second timing offset synchronization circuit  50  is used for generating a second timing metric (Λ θ   PN ) formed by the PN-sequence. The first multiplier  31  is used for multiplying the first timing metric by a first coefficient ρ to get ρΛ θ   CP . The second multiplier  32  is used for multiplying the second timing metric by a second coefficient α(1−ρ) to get α(1−ρ)Λ θ   PN . The second adder  33  is used for adding the first timing metric multiplied by the first coefficient ρ and the second timing metric multiplied by the second α(1−ρ). The first maximum value circuit  34  is used for obtaining the maximum, i.e. 
           arg   ⁢           ⁢       max   θ     ⁢     {           }             
in the equation (1) representing obtaining the maximum for the parameter in the bracket, for the output of the second adder  33  to calculate the timing offset of the receiving signal. In addition, the first timing offset synchronization circuit  40  and the second timing offset synchronization circuit  50  are described in detail respectively as follows.
 
   Referring to  FIG. 4 , it shows a schematic diagram of the first timing offset synchronization circuit  40  of the invention. The first timing offset synchronization circuit  40  includes a first delay circuit  41 , a first conjugate circuit  42 , a third multiplier  43 , a first real-part circuit  44  and a first accumulator  45 . The first timing offset synchronization circuit  40  calculates the first timing metric (Λ θ   CP ) according to the following equation (2): 
                   Λ   θ   CP     =       ∑     k   =   θ       θ   +   L   -   1       ⁢           ⁢       Re   ⁡     (       r   k     ⁢     r     k   +   N     *       )       .               (   2   )               
The equation (2) is obtained by neglecting all the constant terms of the equation (1) because they are not relevant to the maximization of the log-likelihood function.
 
   From the equation (2), it will be known that the signal r k  must be multiplied by the conjugate signal r k+N * delayed time N, and then the real-part is taken after multiplying and accumulated by length L. Therefore, the first delay circuit  41  is used for delaying the receiving signal r k  for a first predetermined time (N). The first conjugate circuit  42  is used for obtaining the complex conjugate r k+N * of the delayed receiving signal. The third multiplier  43  is used for multiplying the receiving signal r k  without being delayed and the output signal r k+N * of the first conjugate circuit to obtain r k r k+N *. The first real-part circuit  44  is used for obtaining the real-part Re (r k r k+N *) of the complex number output signal of the third multiplier  43 . The first accumulator  45  is used for accumulating the output signal of the first real-part circuit  44  and a plurality of time points to calculate the first timing metric, in which the number accumulated is the length (L) of the cyclic prefix. 
   Referring to  FIG. 5 , it shows a schematic diagram of the second timing offset synchronization circuit  50  of the invention. The second timing offset synchronization circuit  50  includes a second real-part circuit  501 , a second delay circuit  502 , a third delay circuit  503 , a fourth multiplier  504 , a second conjugate circuit  505 , a third real-part circuit  506 , a third adder  507 , a second accumulator  508 , a fifth multiplier  509 , a third accumulator  510 , a sixth multiplier  511 , a seventh multiplier  512  and a fourth adder  513 . The second timing offset synchronization circuit  50  calculates the second timing metric (Λ θ   PN ) according to the following equation (3): 
   
     
       
         
           
             
               
                 
                   Λ 
                   θ 
                   PN 
                 
                 = 
                 
                   
                     
                       ( 
                       
                         1 
                         + 
                         ρ 
                       
                       ) 
                     
                     ⁢ 
                     
                       
                         ∑ 
                         
                           k 
                           = 
                           θ 
                         
                         
                           θ 
                           + 
                           N 
                           + 
                           L 
                           - 
                           1 
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         
                           p 
                           
                             k 
                             - 
                             θ 
                           
                         
                         ⁢ 
                         
                           Re 
                           ⁡ 
                           
                             ( 
                             
                               r 
                               k 
                             
                             ) 
                           
                         
                       
                     
                   
                   - 
                   
                     ρ 
                     ⁢ 
                     
                       
                         ∑ 
                         
                           k 
                           = 
                           θ 
                         
                         
                           θ 
                           + 
                           L 
                           - 
                           1 
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         
                           
                             p 
                             
                               k 
                               - 
                               θ 
                             
                           
                           ⁡ 
                           
                             [ 
                             
                               
                                 
                                   
                                     
                                       Re 
                                       ⁡ 
                                       
                                         ( 
                                         
                                           r 
                                           k 
                                         
                                         ) 
                                       
                                     
                                     + 
                                   
                                 
                               
                               
                                 
                                   
                                     Re 
                                     ⁡ 
                                     
                                       ( 
                                       
                                         r 
                                         
                                           k 
                                           + 
                                           N 
                                         
                                         * 
                                       
                                       ) 
                                     
                                   
                                 
                               
                             
                             ] 
                           
                         
                         . 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 3 
                 ) 
               
             
           
         
       
     
   
   The second real-part circuit  501  is used for obtaining the real-part Re (r k ) of the complex number receiving signal. The second delay circuit  502  is used for delaying the complex number receiving signal r k  for a first predetermined time (N), and obtaining the complex conjugate r k+N * of the output complex signals of the second delay circuit  502  through the second conjugate circuit  505 . The third delay circuit  503  is used for delaying the PN-sequence receiving signal p k  of the receiving signal for a second predetermined time (θ) to obtain p k−θ . The fourth multiplier  504  is used for multiplying the output signal of the second real-part circuit  501  and the output signal of the third delay circuit  503  to obtain p k−θ  Re (r k ). 
   The second accumulator  508  is used for accumulating the output of the fourth multiplier  504  by a plurality of lengths, in which the number accumulated (L+N) is the length (L) of the cyclic prefix plus the first predetermined time (N). The sixth multiplier  511  is used for multiplying the output signal of the second accumulator  508  by a third coefficient (1+ρ) to obtain the former half part 
             (     1   +   ρ     )     ⁢       ∑     k   =   θ       θ   +   N   +   L   -   1       ⁢           ⁢       p     k   -   θ       ⁢     Re   ⁡     (     r   k     )                 
of the above equation (3).
 
   The third real-part circuit  506  is used for obtaining the real-part Re (r k+N *) of the complex number output signal of the second conjugate circuit  505 . The third adder  507  is used for adding the output signal of the second real-part circuit  501  and the output signal of the third real-part circuit  506  to obtain Re (r k )+Re (r k+N *). The fifth multiplier  509  is used for multiplying the output signal of the third adder  507  and the output signal of the third delay circuit  503  to obtain p k−θ  [Re (r k )+Re (r k+N *)]. The third accumulator  510  is used for accumulating the output signal of the fifth multiplier  509  by a plurality of lengths, in which the number accumulated is the length (L) of the cyclic prefix. The seventh multiplier  512  is used for multiplying the output signal of the third accumulator  510  by the first coefficient ρ to obtain the latter half part 
           ρ   ⁢       ∑     k   =   θ       θ   +   L   -   1       ⁢           ⁢       p     k   -   θ       ⁡     [       Re   ⁡     (     r   k     )       +     Re   ⁡     (     r     k   +   N     *     )         ]               
of the equation (3). The fourth adder  513  is used for adding the output signal of the sixth multiplier  511  and the output signal of the seventh multiplier  512  to calculate the second timing metric (Λ θ   PN ).
 
   Referring to  FIG. 6 , it shows a schematic diagram of the frequency offset synchronization device  60  of the invention. The frequency offset synchronization device  60  includes a first frequency offset synchronization circuit  70 , a second frequency offset synchronization circuit  80 , an eighth multiplier  61 , a ninth multiplier  62 , a fifth adder  63 , a second maximum value circuit  64 . The frequency offset synchronization circuit  60  calculates the frequency offset according to the following equation (4) which is derived from MLE criterion: 
                   ɛ   ^     =       arg   ⁢           ⁢       max   ɛ     ⁢     {     Λ   ɛ     }         =     arg   ⁢           ⁢       max   ɛ     ⁢       {       ρΛ   ɛ   CP     +       α   ⁡     (     1   -   ρ     )       ⁢     Λ   ɛ   PN         }     .                   (   4   )               
where ρ and α are defined in equation (1). From equation (4), it is obvious that the performance of the derived frequency offset estimator is highly dependent on SNR. For a large signal to noise ratio, the estimation chiefly relies on the cyclic prefix (Λ ε   CP ), whereas for a low SNR, the estimator depends on the information of the PN sequence (Λ ε   PN ).
 
   The first frequency offset synchronization circuit  70  is used for generating a first frequency offset metric (Λ ε   CP ) formed by the cyclic prefix. The second frequency offset synchronization circuit  80  is used for generating a second frequency offset metric (Λ ε   PN ) formed by the PN-sequence. The eighth multiplier  61  is used for multiplying the first frequency offset metric by a first coefficient ρ to obtain ρΛ ε   CP . The ninth multiplier  62  is used for multiplying the second frequency offset metric by a second coefficient α(1−ρ) to obtain α(1−ρ)Λ ε   PN . The fifth adder  63  is used for adding the first frequency offset metric multiplied by the first coefficient ρ and the second frequency offset metric multiplied by the second coefficient α(1−ρ) . The second maximum value circuit  64  is used for obtaining the maximum, i.e. 
           arg   ⁢           ⁢       max   θ     ⁢     {           }             
in the equation (4) representing obtaining the maximum for the parameter within the bracket, of the output of the fifth adder  63  to calculate the frequency offset of the receiving signal. In addition, the first frequency offset synchronization circuit  70  and the second frequency offset synchronization circuit  80  are described in detail respectively as follows.
 
   Referring to  FIG. 7 , it shows a schematic diagram of the first frequency offset synchronization circuit  70  of the invention. The first frequency offset synchronization circuit  70  includes a fourth delay circuit  71 , a third conjugate circuit  72 , a tenth multiplier  73 , a fourth real-part circuit  74  and a fourth accumulator  75 . The first frequency offset synchronization circuit  70  calculates the first frequency offset metric (Λ ε   CP ) according to the following equation (5): 
   
     
       
         
           
             
               
                 
                   Λ 
                   ɛ 
                   CP 
                 
                 = 
                 
                   
                     ∑ 
                     
                       k 
                       = 
                       θ 
                     
                     
                       θ 
                       + 
                       L 
                       - 
                       1 
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       Re 
                       ⁡ 
                       
                         ( 
                         
                           
                             r 
                             k 
                           
                           ⁢ 
                           
                             r 
                             
                               k 
                               + 
                               N 
                             
                             * 
                           
                           ⁢ 
                           
                             ⅇ 
                             
                               j2π 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               ɛ 
                             
                           
                         
                         ) 
                       
                     
                     . 
                   
                 
               
             
             
               
                 ( 
                 5 
                 ) 
               
             
           
         
       
     
   
   The fourth delay circuit  71  is used for delaying the receiving signal r k  for a first predetermined time (N). The third conjugate circuit  72  is used for obtaining complex conjugate r k+N * of the delayed receiving signal. The tenth multiplier  73  is used for multiplying the receiving signal r k  without being delayed, the output signal r k+N * of the third conjugate circuit  72  and a first frequency offset item e j2πε . The fourth real-part circuit  74  is used for obtaining the real-part of the complex number output signal of the tenth multiplier  73 . The fourth accumulator  75  is used for accumulating the output signal of the fourth real-part circuit  74  by a plurality of time points to calculate the first frequency offset metric (Λ ε   CP ), in which the number accumulated is the length (L) of the cyclic prefix. 
   Referring to  FIG. 8 , it shows a schematic diagram of the second frequency offset synchronization circuit  80  of the invention. The second frequency offset synchronization circuit  80  includes an eleventh multiplier  801 , a fifth real-part circuit  802 , a fifth delay circuit  803 , a fourth conjugate circuit  804 , a twelfth multiplier  805 , a sixth real-part circuit  806 , a sixth adder  807 , a thirteenth multiplier  808 , a fourteenth multiplier  809 , a sixth accumulator  810 , a seventh accumulator  811 , a fifteenth multiplier  812 , a sixteenth multiplier  813  and a seventh adder  814 . The second frequency offset synchronization circuit  80  calculates the second frequency offset metric (Λ ε   PN ) according to the following equation (6): 
   
     
       
         
           
             
               
                 
                   Λ 
                   ɛ 
                   PN 
                 
                 = 
                 
                   
                     
                       ( 
                       
                         1 
                         + 
                         ρ 
                       
                       ) 
                     
                     ⁢ 
                     
                       
                         ∑ 
                         
                           k 
                           = 
                           θ 
                         
                         
                           θ 
                           + 
                           N 
                           + 
                           L 
                           - 
                           1 
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         
                           p 
                           k 
                         
                         ⁢ 
                         
                           Re 
                           ( 
                           
                             
                               r 
                               k 
                             
                             ⁢ 
                             
                               ⅇ 
                               
                                 
                                   
                                     - 
                                     j2πɛ 
                                   
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   k 
                                 
                                 N 
                               
                             
                           
                           ) 
                         
                       
                     
                   
                   - 
                   
                     ρ 
                     ⁢ 
                     
                       
                         ∑ 
                         
                           k 
                           = 
                           θ 
                         
                         
                           θ 
                           + 
                           L 
                           - 
                           1 
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         
                           
                             p 
                             k 
                           
                           ⁡ 
                           
                             [ 
                             
                               
                                 
                                   
                                     
                                       Re 
                                       ( 
                                       
                                         
                                           r 
                                           k 
                                         
                                         ⁢ 
                                         
                                           ⅇ 
                                           
                                             
                                               
                                                 - 
                                                 j2πɛ 
                                               
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               k 
                                             
                                             N 
                                           
                                         
                                       
                                       ) 
                                     
                                     + 
                                   
                                 
                               
                               
                                 
                                   
                                     Re 
                                     ( 
                                     
                                       
                                         r 
                                         
                                           k 
                                           + 
                                           N 
                                         
                                         * 
                                       
                                       ⁢ 
                                       
                                         ⅇ 
                                         
                                           
                                             j2πɛ 
                                             ⁡ 
                                             
                                               ( 
                                               
                                                 k 
                                                 + 
                                                 N 
                                               
                                               ) 
                                             
                                           
                                           N 
                                         
                                       
                                     
                                     ) 
                                   
                                 
                               
                             
                             ] 
                           
                         
                         . 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 6 
                 ) 
               
             
           
         
       
     
   
   The eleventh multiplier  801  is used for multiplying the receiving signal r k  by a second frequency offset item e −j2πεk/N . The fifth real-part circuit  802  is used for obtaining the real-part for the complex number signal output by the eleventh multiplier  801 . The fifth delay circuit  803  is used for delaying the receiving signal r k  for a first predetermined time (N). The fourth conjugate circuit  804  is used for obtaining the complex conjugate as r k+N * of the output signal of the fifth delay circuit  803 . The twelfth multiplier  805  is used for multiplying the output signal of the fourth conjugate circuit  804  by a third frequency offset item e −j2πε(k+N)/N . The sixth real-part circuit  806  is used for obtaining the real-part 
           Re   (       r     k   +   N     *     ⁢     ⅇ       j2πɛ   ⁡     (     k   +   N     )       N         )         
of the complex number signal output by the twelfth multiplier  805 . The sixth adder  807  is used for adding the output signal of the fifth real-part circuit  802  and the output signal of the sixth real-part circuit  806  to obtain
 
   
     
       
         
           
             Re 
             ( 
             
               
                 r 
                 k 
               
               ⁢ 
               
                 ⅇ 
                 
                   
                     
                       - 
                       j2πɛ 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                   N 
                 
               
             
             ) 
           
           + 
           
             
               Re 
               ( 
               
                 
                   r 
                   
                     k 
                     + 
                     N 
                   
                   * 
                 
                 ⁢ 
                 
                   ⅇ 
                   
                     
                       j2πɛ 
                       ⁡ 
                       
                         ( 
                         
                           k 
                           + 
                           N 
                         
                         ) 
                       
                     
                     N 
                   
                 
               
               ) 
             
             . 
           
         
       
     
   
   The thirteenth multiplier  808  is used for multiplying the PN-sequence receiving signal p k  of receiving signal and the output signal of the fifth real-part circuit  802  to obtain 
             p   k     ⁢       Re   (       r   k     ⁢     ⅇ         -   j2πɛ     ⁢           ⁢   k     N         )     .           
The sixth accumulator  810  is used for accumulating the output signal of the thirteenth multiplier  808  by a plurality of lengths, in which the numbers (L+N) accumulated is the length (L) of the cyclic prefix plus the first predetermined time (N). The sixteenth multiplier  813  is used for multiplying the output of the sixth accumulator  810  by a third coefficient
 
   
     
       
         
           
             ( 
             
               1 
               + 
               ρ 
             
             ) 
           
           ⁢ 
           
               
           
           ⁢ 
           to 
           ⁢ 
           
               
           
           ⁢ 
           get 
           ⁢ 
           
               
           
           ⁢ 
           
             ( 
             
               1 
               + 
               ρ 
             
             ) 
           
           ⁢ 
           
             
               ∑ 
               
                 k 
                 = 
                 θ 
               
               
                 θ 
                 + 
                 N 
                 + 
                 L 
                 - 
                 1 
               
             
             ⁢ 
             
                 
             
             ⁢ 
             
               
                 p 
                 k 
               
               ⁢ 
               
                 
                   Re 
                   ( 
                   
                     
                       r 
                       k 
                     
                     ⁢ 
                     
                       ⅇ 
                       
                         
                           
                             - 
                             j2πɛ 
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           k 
                         
                         N 
                       
                     
                   
                   ) 
                 
                 . 
               
             
           
         
       
     
   
   The fourteenth multiplier  809  is used for multiplying the PN-sequence receiving signal p k  of the receiving signal and the output signal of the sixth adder  807 . The seventh accumulator  811  is used for accumulating the output signal of the fourteenth multiplier  809  by a plurality of lengths, in which the number accumulated is the length (L) of the cyclic prefix. The fifteenth multiplier  812  is used for multiplying the output signal of the seventh accumulator  811  by the first coefficient ρ to obtain 
           ρ   ⁢       ∑     k   =   θ       θ   +   L   -   1       ⁢         p   k     ⁡     [       Re   ⁡     (       r   k     ⁢     ⅇ         -   j2πɛ     ⁢           ⁢   k     N         )       +     Re   ⁡     (       r     k   +   N     *     ⁢     ⅇ       j2πɛ   ⁢           ⁢     (     k   +   N     )       N         )         ]       .             
The seventh adder  814  is used for adding the output signal of the fifteenth multiplier  812  by the output signal of the sixteenth multiplier  813  to calculate the second frequency offset metric (Λ ε   PN ).
 
   Referring to  FIG. 1  again, the cyclic prefix remover  17  is used for removing the cyclic prefix of the receiving signal compensated by the time and frequency synchronization device after the time and frequency synchronization device  20  calculates and compensates the timing offset and frequency offset of the receiving signal. The Fast Fourier Transformer  18  is used for transforming the receiving signal with the cyclic prefix removed to a complex number frequency domain signal at a receiving terminal. The demodulate circuit  19  is used for demodulating the complex number frequency domain signals at the receiving terminal to a receiving terminal signal. 
   The orthogonal frequency division multiplexing system  10  of the invention is to add a PN-sequence with cyclic prefix to each OFDM symbol before transmitting. The time and frequency synchronization device  20  comprises two synchronization circuits from the cyclic prefix and PN-sequence during calculating the timing offset and frequency offset of receiving signal. As a result, the OFDM system  10  of the invention not only has better performance in fading channel, but also has the better bandwidth utilization without extra bandwidth for transmitting the PN-sequence. Therefore, the architecture of the orthogonal frequency division multiplexing system  10  of the invention may be better than that of the conventional synchronization system, which just utilizes the cyclic prefix. Moreover, to add PN-sequence to each OFDM signal will not decrease the bandwidth utilization, but will optimize the performance of synchronization at the receiving terminal. 
   While an embodiment of the present invention has been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiment of the present invention is therefore described in an illustrative, but not restrictive, sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope as defined in the appended claims.