Patent Publication Number: US-2019190469-A1

Title: Circuits for power-combined power amplifier arrays

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 14/639,700, filed Mar. 5, 2018, which claims the benefit of U.S. Provisional Patent Application No. 61/948,198, filed Mar. 5, 2014, each of which is hereby incorporated by reference herein in its entirety. 
    
    
     STATEMENT REGARDING GOVERNMENT FUNDED RESEARCH 
     This invention was made with government support under grant FA8650-10-1-7042 awarded by the Defense Advanced Research Projects Agency. The government has certain rights in the invention. 
    
    
     BACKGROUND 
     Burgeoning long-range communications applications, such as satellite communication in the 45 GHz band and high data-rate wireless backhaul in the 71-76 GHz and 81-86 GHz bands, have driven the need for the development of high-power, energy-efficient long-range communication circuitry, such as power amplifiers. 
     However, existing power amplifier and combiner architectures do not provide a means for compact large-scale power combining in a linear manner to achieve watt-class output powers at mmWave frequencies. 
     Accordingly, new circuits for power-combined power amplifier arrays are desirable. 
     SUMMARY 
     Circuits for power-combined power amplifier arrays are provided. In some embodiments, the circuits for power combined-power amplifier arrays comprise: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an example of a block diagram of a circuit for a power-combined power amplifier array including selectable power amplifier unit cells in accordance with some embodiments. 
         FIG. 2  is an example of a block diagram of a circuit for a power-combined power amplifier array including non-selectable power amplifier unit cells in accordance with some embodiments. 
         FIG. 3  is an example of a schematic diagram of a non-isolating power combiner in accordance with some embodiments. 
         FIG. 4  is a graph showing peak efficiency of a non-isolating power combiner based on various parameters in accordance with some embodiments. 
         FIG. 5  is an example of a schematic diagram of a circuit for a power-combined power amplifier array including selectable power amplifier unit cells in accordance with some embodiments. 
         FIG. 6  is an example of a schematic diagram of a power amplifier unit cell and driver that can be used in the circuit of  FIG. 5  in accordance with some embodiments. 
         FIG. 7  is an example of a schematic diagram of a circuit for a power-combined power amplifier array including non-selectable power amplifier unit cells in accordance with some embodiments. 
         FIG. 8  is an example of a schematic diagram of a power amplifier unit cell and driver that can be used in the circuit of  FIG. 7  in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Circuits for power-combined power amplifier arrays are provided. In some embodiments, these circuits include an input splitter that splits an input signal, an array of power amplifier unit cells that each receive the split input signal and provide an output signal, and a non-isolating power combiner that receive the output signals from the power amplifier unit cells and combines these signals so that a single combined output can be provided. In some embodiments, the power amplifier unit cells are selectable so that only m of the total available unit cells are powered on at a given point in time. In some embodiments, the power combiner can include an array of spiral inductors that are each connected to an output of a corresponding power amplifier unit cell on one side the inductor and to an output of the power combiner on the other side of the inductor. 
     Turning to  FIG. 1 , an example  100  of a block diagram of a circuit for a power-combined power amplifier array including selectable power amplifier unit cells in accordance with some embodiments is shown. This circuit can be used for any suitable application. For example, in some embodiments, this circuit can be used for a digital-mmWave power amplifier array. 
     As illustrated, circuit  100  includes an input splitter  102 , an array of power amplifier unit cells  104 ,  106 , and  108 , a non-isolating power combiner  110 , switches  112 ,  114 , and  116 , a digital signal processor (DSP)  120 , and a load resistor  122 . 
     As described above, input splitter  102  splits an input signal so that the input signal can be provided from a single point to the power amplifier unit cells. Input splitter  102  can be implemented in any suitable manner. For example, as described below in connection with  FIGS. 5 and 7 , the input splitter can be implemented as a tree of transmission lines. 
     Each of power amplifier unit cells  104 ,  106 , and  108  amplify the signal from the input splitter when the unit cell is turned ON. Whether a unit cells is turned ON or OFF may be controlled by a signal from DSP  120  which controls switches  112 ,  114 , and  116 . Any suitable unit cells, any suitable switches, and any suitable DSP can be used. In some embodiments, DSP  120  can also be omitted when not needed and any other suitable mechanism for controlling the switches can be provided. 
     Power combiner  110  receives the outputs of the ON unit cells, combines the outputs into a single signal, and drives load R load    122 . As described below, in some embodiments, power combiner may be implemented using a set of spiral inductors. Load R load    122  can be any suitable load in some embodiments. 
     Turning to  FIG. 2 , an example  200  of a block diagram of a circuit for a power-combined power amplifier array including non-selectable power amplifier unit cells in accordance with some embodiments is shown. This circuit can be used for any suitable application. For example, in some embodiments, this circuit can be used for a watt-class power amplifier array. 
     As illustrated, circuit  200  includes an input splitter  202 , an array of power amplifier unit cells  204 ,  206 , and  208 , a non-isolating power combiner  210 , and a load resistor  122 . 
     Input splitter  202  splits an input signal so that the input signal can be provided from a single point to the power amplifier unit cells. Input splitter  202  can be implemented in any suitable manner. For example, as described below in connection with  FIGS. 5 and 7 , the input splitter can be implemented as a tree of transmission lines. 
     Each of power amplifier unit cells  204 ,  206 , and  208  amplify the signal from the input splitter. 
     Power combiner  210  receives the outputs of the unit cells, combines the outputs into a single signal, and drives load R load    222 . As described below, in some embodiments, power combiner may be implemented using a set of spiral inductors. Load R load    222  can be any suitable load in some embodiments. 
     Any suitable number of input splitter outputs, power amplifier unit cells, and power combiner inputs can be used in the examples of  FIGS. 1 and 2  in some embodiments. For example, in some embodiments, the number of these components can be an even number, such as eight, twelve, or sixteen. In some embodiments, for each of its inputs, the power combiner can include a single spiral conductor connected to the input and to a single output of the power combiner. 
     As discussed above, in some embodiments and instances, it may be desirable to turn OFF one or more of the power amplifier unit cells, while leaving other of the power amplifier unit cells ON. In order to achieve an output amplitude that is proportional to the number of power amplifier unit cells that are ON (m) (i.e., to achieve A out  α m), the following should be true:
         the total output power of the power amplifier array (P out (m)) should be equal to m·P unit (m) (where P unit (m) is the output power of each of the ON power amplifier unit cells);   P unit (m) should be proportional to 1/R in (m) (where R in (m) is the input resistance at the input to the combiner (assuming that the combiner presents a purely resistive impedance to the power amplifier unit-cells)); and   P out (m) should be proportional to m 2 .       

     Based, on this, it follows that m·P unit (m) should be proportional to m 2 , 
     
       
         
           
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     should be proportional to m 2 , and R in (m) should be proportional to 
     
       
         
           
             
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             . 
           
         
       
     
     In order to address these and other requirements, as shown in the example of  FIG. 3 , a combiner  310  in accordance with some embodiments can contain a set of lumped C-L-C-section equivalents  324 ,  326 ,  328 , and  330  (at the desired frequency of operation ω 0 ) which each receive the output of a corresponding power amplifier unit cell. These C-L-C-section equivalents can be implemented in any suitable manner. For example, in some embodiments, as shown in  FIG. 3 , each C-L-C-section equivalent can be realized as a single spiral inductor which behaves equivalently to a C-L-C-section  332  at the desired frequency of operation. 
     To achieve an equivalent characteristic impedance Z 0  necessary for the combiner to be implemented in CMOS back end of line (BEOL) and to achieve the behavior of a quarter-wave transmission line at the desired frequency ω 0 , the spiral inductor can be configured to achieve an inductance of L=Z 0 /ω 0  and a parasitic capacitance of C p =1/(Z 0 ω 0 ) on either side as seen in box  334  of  FIG. 3 . If Road is the load impedance seen by the combiner and R in  is the desired input impedance, then L=√{square root over (nR load R in )}/ω 0  and C p =1/ω 0 √{square root over (nR load R in )}. For instance, an eight-way combiner designed to operate at 45 GHz, to drive a 50Ω load, and to present a 50Ω input impedance at each of its inputs requires L=500 pH with C p =25 fF on either side, giving an effective Z 0  of 141.42Ω. 
     The maximum number of elements that can be combined in a single step using the quarter-wave lumped combiner, with given values for R load  and R in , is limited by the achievable self-resonant frequency (SRF) of spirals in the BEOL and layout considerations for maintaining symmetry. For example, in some embodiments, the maximum number of elements that can be combined can be found to be sixteen when the combiner is implemented in 45 nm SOI CMOS BEOL for R load =R in =50Ω for which Z 0 =200Ω at 45 GHz Although sixteen elements may be found to be the maximum number of elements that can be combined, in some embodiments, fewer elements than that number of elements can be combined. For example, in some embodiments, eight elements can be combined for which the spirals have a Z 0 =141.42Ω at 45 GHz. In another example, in some embodiments, twelve elements can be combined, which requires a Z 0 =173.2Ω at 45 GHz. 
     The efficiency η comb  of the n-way lumped quarter-wave combiner driving R load  may be expressed as: 
     
       
         
           
             
               
                 
                   
                     
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     where Q L  is the inductive quality factor of the spiral, Q C  is the quality factor of the parasitic capacitances of the spiral at ω 0 , and ρ comb  (the ideal impedance transformation performed by the combiner) may be expressed as: 
     
       
         
           
             
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     Equation (1) can also be written as follows: 
     
       
         
           
             
               
                 
                   
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     where ρ sec  equals n·ρ comb  and is the impedance transformation performed by each spiral section in the combiner. 
     Equations (1) and (2) assume that the currents and voltages in an ideal lossless combiner are unaffected by the resistance of the spiral being in series with the inductance of the spiral, and by the resistance of the spiral being in parallel with the capacitances of the spiral. 
     Based on equation (2), it can be seen that the efficiency of the combiner only depends on Q L , Q C  and ρ sec . 
     An example of the simulated and theoretical efficiencies of two eight-way combiners with Q L =12, Q C =50 and Q L =25, Q C =20 at 45 GHz in accordance with some embodiments are shown in  FIG. 4 . As can be seen, the peak efficiency in this example occurs at ρ sec =1. Based on this graph, an eight-way combiner with Q L =12, Q C =50, and ρ sec =16 (based on a ρ comb =2) has an efficiency of 65%. Likewise, based on this graph, an eight-way combiner with Q L =25, Q C =20, and ρ sec =8 (based on a ρ comb =1) has an efficiency of 75%. 
     Any suitable arrangement of the lumped quarter-wave sections can be used in some embodiments. For example, as shown in  FIGS. 5 and 7 , in some embodiments, the sections of a combiner can be joined pairwise and then each pair can be connected to an output of the combiner (e.g., an output pad) by means of an intermediary microstrip. Thus, in this example, four microstrips can be used. In some embodiments, it may be beneficial to ensure that the pairwise connections and intermediary microstrips are as short as possible. 
     As described above, in accordance with some embodiments, one or more of the power amplifier unit cells in an array of such cells may be able to be switched OFF. In some of such embodiments, an OFF unit-cell may be configure to present a short-circuit (or near short-circuit) impedance to the corresponding combiner input. This short-circuit can then be transformed by the corresponding lumped quarter-wave section of the combiner to an open at the output of the combiner thus ensuring that no (or minimal) power is dissipated by the section of the combiner corresponding to the OFF cell. Furthermore, each ON unit-cell may see an impedance 
     
       
         
           
             
               
                 
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                   load 
                 
               
             
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     which has the desired load modulation effect (R in (m) α 1/m). 
     Turning to  FIG. 5 , an example  500  of a three-bit digital to mmWave power amplifier array in accordance with some embodiments is shown. As illustrated, eight supply switched stacked-FET power amplifier unit-cells PA 1    502 , PA 2    504 , PA 3    506 , PA 4    508 , PA 5    510 , PA 6    512 , PA 7    514 , and PA 8    516  are power combined using an eight-way lumped quarter-wave combiner  518 . 
     The combiner is designed to have R in (8)=25Ω for R load =50Ω (ρ comb =2, L=353 pH, C p =35.4 fF, Z 0 =100Ω at 45 GHz). 
     Eight digital control lines (b 1    520 , b 2    522 , b 3    524 , b 4    526 , b 5    528 , b 6    530 , b 7    532 , and b 8    534 ) determine the ON/OFF state of the unit-cells and thereby determine the power amplifier array&#39;s output modulation. The lengths of these digital control lines can be equalized to minimize skew in the digital control word input to the power amplifier array during modulation in some embodiments. As shown in  FIG. 5 , inverter chains connected to the control lines drive switches in the unit cells and drivers at the inputs of the unit cells to turn the unit cells and drivers ON and OFF. 
     The eight power amplifier unit-cells receive their input power via two eight-way input power splitters formed from transmission lines  536 ,  538 ,  540 ,  542 ,  544 ,  544 ,  546 , and  548 , and  550 ,  552 ,  554 ,  556 ,  558 ,  560 , and  562 . As shown, a three-stage design is implemented in which the two stages closest to each power amplifier unit-cell inputs (formed from transmission lines:  542 ,  544 ,  546 ,  548 , and  538 ,  540 ; and  556 ,  558 ,  560 ,  562 , and  552 ,  554 ) are designed in a current-splitting fashion and the stage furthest from the unit cell (formed from transmission lines  536  and  550 ) performs the necessary impedance transformation using a 3λ/4 transmission line. Transmission lines  536  and  550  should be equal in length. 
       FIG. 6  shows an example of a power amplifier unit cell and driver circuit  600  that can be used in circuit  500  in accordance with some embodiments. As shown circuit  600 , includes a two-stacked Class-E-like driver stage  602  followed by a two-stacked class-E-like main amplifier stage  604 . When the unit cells and drivers are OFF, these components consume minimal power, preserve input match with respect to the input splitter as a whole and the transmission lines in the third stage of the input splitter, and present a short-circuit (or near short circuit) impedance to the combiner. 
     In some embodiments, the OFF resistance of a unit cell (R off ) can be configured to match the equivalent source resistance of the ON power amplifier unit cells (e.g., 15Ω). For example, in some embodiments, this can be done by configuring the bias voltage applied at the drain of transistor M 5  (which bias voltage is illustrated in  FIG. 6  as being 1.1V). 
     Turning to  FIG. 7 , an example  700  of a 33-46 GHz watt-class power amplifier array in accordance with some embodiments is shown. As illustrated, eight supply switched stacked-FET power amplifier unit-cells PA 1    702 , PA 2    704 , PA 3    706 , PA 4    708 , PA 5    710 , PA 6    712 , PA 7    714 , and PA 8    716  are power combined using an eight-way lumped quarter-wave combiner  718 . 
     The combiner is designed to have R in (8)=50Ω for R load =50Ω (ρ comb =1, L=500 pH, C p =25 fF, Z 0 =141.42Ω at 45 GHz). In the combiner of  FIG. 7 , each spiral&#39;s outer dimensions are 86 μm×86 μm, and the distance between adjacent spirals was chosen to be greater than 45 μm, which can significantly reduce the coupling and the maximum difference in |Γ in | 
     Unlike circuit  500  of  FIG. 5 , no mechanism for individually turning the power amplifier unit cells ON and OFF is implemented in the embodiment illustrated in  FIG. 7 . 
     Like in circuit  500 , in circuit  700  the eight power amplifier unit-cells receive their input power via two four-way input power splitters (which together act as one eight-way input power splitter) formed from transmission lines  736 ,  737 ,  738 ,  740 ,  742 ,  744 ,  744 ,  746 , and  748 , and  750 ,  751 ,  752 ,  754 ,  756 ,  758 ,  760 , and  762 . As shown in  FIG. 7 , the 3V4 transmission line of  FIG. 5  can be split into two transmission lines  736 ,  737  and  750 ,  751 , in some embodiments. Transmission line pairs  736 ,  737  and  750 ,  751  should be equal lengths. 
       FIG. 8  shows an example of a power amplifier unit cell and driver circuit  800  that can be used in circuit  700  in accordance with some embodiments. As shown circuit  800 , includes a two-stacked Class-E-like driver stage  802  followed by a four-stacked class-E-like power amplifier stage  804 . For long-term reliability, the maximum voltage swing across any two device terminals is limited to a peak value of 2×V dd =2.4V. 
     The provision of the examples described herein (as well as clauses phrased as “such as,” “e.g.,” “including,” and the like) should not be interpreted as limiting the subject matter to the specific examples; rather, the examples are intended to illustrate only some of many possible aspects. 
     Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and the numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is only limited by the claims that follow. Features of the disclosed embodiments can be combined and rearranged in various ways.