Patent Publication Number: US-2023140988-A1

Title: Power management circuit in low-power double data rate memory and management method thereof

Description:
RELATED APPLICATIONS 
     This application claims priority to Taiwan Application Serial Number 110141428, filed Nov. 5, 2021, which is herein incorporated by reference. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates to a power management circuit in a memory and a management method thereof. More particularly, the present disclosure relates to a power management circuit in a low-power double data rate memory and a management method thereof. 
     Description of Related Art 
     In the specifications of a low-power double data rate 4 (LPDDR4) memory, a specific voltage (e.g., VDD 1 ) is used as an external power supply to generate another specific voltage (e.g., VCSA). The voltage VCSA is smaller than the voltage VDD 1 . In the conventional technique, the line width of the power supply requires 22 um when the voltage VDD 1  is used as the external power supply to generate the voltage VCSA (the position of the voltage VCSA and the position of the voltage VDD 1  are separated by more than 5000 um), so that the resistance of the line of the power supply is smaller than or equal to 10 ohms. However, due to the excessively large line width of the power supply in the conventional technology, the circuit area is increased, and the speed is slowed down. In addition, when the LPDDR4 memory enters a standby mode, using the voltage VDD 1  will still consume a certain amount of power and generate a certain amount of leakage current. Accordingly, a power management circuit in a low-power double data rate memory and a management method thereof having the features of reducing the line width of the power supply, saving the power consumption and reducing the leakage current are commercially desirable. 
     SUMMARY 
     According to one aspect of the present disclosure, a power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies of the low-power double data rate memory according to a reference voltage. The power management circuit in the low-power double data rate memory includes a low dropout regulator and a power network structure. The low dropout regulator has a first transmitting terminal and a second transmitting terminal. The first transmitting terminal is configured to transmit a first voltage of the power supplies. The second transmitting terminal is configured to transmit a second voltage of the power supplies, and the low dropout regulator adjusts a voltage difference between the first voltage and the second voltage according to the reference voltage. The power network structure is electrically connected to the low dropout regulator and includes a first power network circuit and a second power network circuit. The first power network circuit has a first connecting point electrically connected to the first transmitting terminal. The first power network circuit has a grid shape and a first unit network space. The second power network circuit has a second connecting point electrically connected to the second transmitting terminal. The second power network circuit has another grid shape and a second unit network space, and the second connecting point is separated from the first connecting point by a distance. The distance is smaller than or equal to one of the first unit network space and the second unit network space. 
     According to another aspect of the present disclosure, a power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies of the low-power double data rate memory according to a first reference voltage, a second reference voltage and a control signal. The power management circuit in the low-power double data rate memory includes a first low dropout regulator, a second low dropout regulator and a power network structure. The first low dropout regulator has a first transmitting terminal and a second transmitting terminal. The first transmitting terminal is configured to transmit a first voltage of the power supplies. The second transmitting terminal is configured to transmit a second voltage of the power supplies, and the first low dropout regulator adjusts a first voltage difference between the first voltage and the second voltage according to the first reference voltage. The second low dropout regulator has a third transmitting terminal, a fourth transmitting terminal and a fifth transmitting terminal. The third transmitting terminal is configured to transmit a third voltage of the power supplies. The fourth transmitting terminal is configured to transmit the first voltage of the power supplies. The fifth transmitting terminal is configured to transmit a fourth voltage of the power supplies. The second low dropout regulator adjusts a second voltage difference between the third voltage and the first voltage according to the second reference voltage and the control signal, and adjusts a third voltage difference between the fourth voltage and the first voltage according to the control signal. The power network structure is electrically connected to the first low dropout regulator and the second low dropout regulator and has a unit network space. The power network structure is electrically connected to the first transmitting terminal and the second transmitting terminal through a first connecting point and a second connecting point. The second connecting point is separated from the first connecting point by a distance, and the distance is smaller than or equal to the unit network space. 
     According to further another aspect of the present disclosure, a management method of a power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies of the low-power double data rate memory according to a reference voltage. The management method of the power management circuit in the low-power double data rate memory includes performing a voltage supplying step and a voltage regulating step. The voltage supplying step includes supplying a first voltage to a first power network circuit of a power network structure and a low dropout regulator. The voltage regulating step includes configuring the low dropout regulator to generate a second voltage according to the first voltage and adjust a first voltage difference between the first voltage of a first transmitting terminal and the second voltage of a second transmitting terminal according to the reference voltage. The low dropout regulator has the first transmitting terminal and the second transmitting terminal. The first transmitting terminal is configured to transmit the first voltage of the power supplies. The second transmitting terminal is configured to transmit the second voltage of the power supplies. The power network structure is electrically connected to the low dropout regulator and includes the first power network circuit and a second power network circuit. The first power network circuit has a first connecting point electrically connected to the first transmitting terminal. The first power network circuit has a grid shape and a first unit network space. The second power network circuit has a second connecting point electrically connected to the second transmitting terminal. The second power network circuit has another grid shape and a second unit network space. The second connecting point is separated from the first connecting point by a distance, and the distance is smaller than or equal to one of the first unit network space and the second unit network space. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
         FIG.  1    shows a schematic view of a power management circuit in a low-power double data rate memory according to a first embodiment of the present disclosure. 
         FIG.  2    shows a schematic view of a low dropout regulator of the power management circuit in the low-power double data rate memory of  FIG.  1   . 
         FIG.  3    shows a schematic view of a power network structure of the power management circuit in the low-power double data rate memory of  FIG.  1   . 
         FIG.  4    shows a circuit diagram of the low dropout regulator of  FIG.  2   . 
         FIG.  5    shows a schematic view of a memory unit of the power management circuit in the low-power double data rate memory of  FIG.  1   . 
         FIG.  6    shows a schematic view of a power management circuit in a low-power double data rate memory according to a second embodiment of the present disclosure. 
         FIG.  7    shows a schematic view of a first low dropout regulator and a second low dropout regulator of the power management circuit in the low-power double data rate memory of  FIG.  6   . 
         FIG.  8    shows a circuit diagram of the second low dropout regulator of  FIG.  7   . 
         FIG.  9    shows a flow chart of a management method of a power management circuit in a low-power double data rate memory according to a third embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiment will be described with the drawings. For clarity, some practical details will be described below. However, it should be noted that the present disclosure should not be limited by the practical details, that is, in some embodiment, the practical details is unnecessary. In addition, for simplifying the drawings, some conventional structures and elements will be simply illustrated, and repeated elements may be represented by the same labels. 
     It will be understood that when an element (or device) is referred to as be “connected to” another element, it can be directly connected to the other element, or it can be indirectly connected to the other element, that is, intervening elements may be present. In contrast, when an element is referred to as be “directly connected to” another element, there are no intervening elements present. In addition, the terms first, second, third, etc. are used herein to describe various elements or components, these elements or components should not be limited by these terms. Consequently, a first element or component discussed below could be termed a second element or component. 
     Please refer to  FIGS.  1 ,  2  and  3   .  FIG.  1    shows a schematic view of a power management circuit  100  in a low-power double data rate memory according to a first embodiment of the present disclosure.  FIG.  2    shows a schematic view of a low dropout (LDO) regulator  200  of the power management circuit  100  in the low-power double data rate memory of  FIG.  1   .  FIG.  3    shows a schematic view of a power network structure  300  of the power management circuit  100  in the low-power double data rate memory of  FIG.  1   . The power management circuit  100  in the low-power double data rate memory is configured to manage a plurality of power supplies of the low-power double data rate memory according to a reference voltage VREF. The power management circuit  100  in the low-power double data rate memory includes a low dropout regulator  200  and a power network structure  300 . The low dropout regulator  200  has a first transmitting terminal T 1  and a second transmitting terminal T 2 . The first transmitting terminal T 1  is configured to transmit a first voltage VDDA of the power supplies. The second transmitting terminal T 2  is configured to transmit a second voltage VCSA of the power supplies, and the low dropout regulator  200  adjusts a voltage difference between the first voltage VDDA and the second voltage VCSA according to the reference voltage VREF. In addition, the power network structure  300  is electrically connected to the low dropout regulator  200  and includes a first power network circuit  310  and a second power network circuit  320 . The first power network circuit  310  has a first connecting point CP 1  electrically connected to the first transmitting terminal T 1 . The first power network circuit  310  has a grid shape and a first unit network space D 1 . The second power network circuit  320  has a second connecting point CP 2  electrically connected to the second transmitting terminal T 2 . The second power network circuit  320  has another grid shape and a second unit network space D 2 , and the second connecting point CP 2  is separated from the first connecting point CP 1  by a distance D 3 . The distance D 3  is smaller than or equal to one of the first unit network space D 1  and the second unit network space D 2 . Therefore, the power management circuit  100  in the low-power double data rate memory of the present disclosure utilizes the low dropout regulator  200  combined with the power network structure  300  and uses the first voltage VDDA as an external power supply to generate the second voltage VCSA, so that the line width of the power supply only requires 4 um to solve the problem of the conventional technology (e.g., using a third voltage VDD 1  (as shown in  FIG.  7   ) as the external power supply to generate the second voltage VCSA) that the line width of the power supply requires 22 um and is too large. 
     Please refer to  FIGS.  1 ,  2 ,  3 ,  4  and  5   .  FIG.  4    shows a circuit diagram of the low dropout regulator  200  of  FIG.  2   .  FIG.  5    shows a schematic view of a memory unit Mb_T of the power management circuit  100  in the low-power double data rate memory of  FIG.  1   . The low-power double data rate memory may be a low-power double data rate 4 (LPDDR4) memory. The power management circuit  100  in the low-power double data rate memory includes a plurality of pads PAD_T, PAD_B, the low dropout regulator  200 , the power network structure  300  and a plurality of memory units Mb_T, Mb_B. 
     The pads PAD_T, PAD_B are electrically connected to the power network structure  300  and supply the first voltage VDDA to the low dropout regulator  200 , the power network structure  300  and the memory units Mb_T, Mb_B. The pad PAD_T supplies the first voltage VDDA to the memory unit Mb_T. The pad PAD_B supplies the first voltage VDDA to the memory unit Mb_B. 
     The low dropout regulator  200  includes a transistor  210  and a comparator  220 . The transistor  210  is electrically connected between the first transmitting terminal T 1  and the second transmitting terminal T 2 . The comparator  220  is electrically connected to the first transmitting terminal T 1 , the second transmitting terminal T 2  and the transistor  210 . The comparator  220  is configured to compare the reference voltage VREF and the second voltage VCSA to generate a comparison signal, and the comparison signal is electrically connected to the transistor  210  to adjust the voltage difference between the first voltage VDDA and the second voltage VCSA. The transistor  210  is a PMOS transistor and has a source electrode, a gate electrode and a drain electrode, and the source electrode, the gate electrode and the drain electrode are electrically connected to the first voltage VDDA, the comparison signal and the second voltage VCSA, respectively. In one embodiment, the first voltage is equal to 1.35 V, and the second voltage is equal to 0.94 V, but the present disclosure is not limited thereto. In addition, the low dropout regulator  200  further includes a resistor R 1  and a capacitor C 1 . The resistor R 1  and the capacitor C 1  are electrically connected between the gate electrode and the drain electrode of the transistor  210 . The comparator  220  includes a plurality of transistors P 11 , P 12 , N 11 , N 12 , N 13 . The transistor N 11  is electrically connected between the transistor P 11  and the transistor N 13 . The transistor N 12  is electrically connected between the transistor P 12  and the transistor N 13 , and the transistors P 11 , P 12  are connected to each other. The transistors N 11 , N 12 , N 13  are controlled by the reference voltage VREF, the second voltage VCSA and a bias voltage VN, respectively. Each of the transistors P 11 , P 12  is the PMOS transistor, and each of the transistors N 11 , N 12 , N 13  is an NMOS transistor. 
     The power network structure  300  includes the first power network circuit  310  and the second power network circuit  320 . The first power network circuit  310  includes a plurality of first horizontal power lines  312  and a plurality of first vertical power lines  314 . The first horizontal power lines  312  are arranged parallel to each other and extend in a first direction DX. The first vertical power lines  314  are arranged parallel to each other and extend in a second direction DY. Each of the first vertical power lines  314  is connected to each of the first horizontal power lines  312 , and the second direction DY is perpendicular to the first direction DX. In addition, the second power network circuit  320  includes a plurality of second horizontal power lines  322  and a plurality of second vertical power lines  324 . The second horizontal power lines  322  are arranged parallel to each other and extend in the first direction DX. The second vertical power lines  324  are arranged parallel to each other and extend in the second direction DY. Each of the second vertical power lines  324  is connected to each of the second horizontal power lines  322 . The second connecting point CP 2  is separated from the first connecting point CP 1  by the distance D 3  along one of the first direction DX and the second direction DY. In  FIG.  3   , the second connecting point CP 2  is separated from the first connecting point CP 1  by the distance D 3  along the first direction DX. 
     The low dropout regulator  200  and the power network structure  300  are both disposed in a chip. The chip is made of complementary metal oxide semiconductor (CMOS) and includes a first metal layer and a second metal layer. The first power network circuit  310  and the second power network circuit  320  are located in the first metal layer and the second metal layer, respectively. 
     The memory unit Mb_T includes a storage unit  400 , a voltage equalization circuit  500  and a sensing circuit  600 . The storage unit  400  includes a bit line BL, a bit line bar BLB, at least one storage capacitor SC and at least one word line WL. The at least one storage capacitor SC is connected to the at least one word line WL and one of the bit line BL and the bit line bar BLB. The at least one storage capacitor SC is configured to store a storage message. The voltage equalization circuit  500  is electrically connected to the bit line BL, the bit line bar BLB, the first voltage VDDA and an equalization reference voltage (i.e., VCSA/2). The voltage equalization circuit  500  is configured to equalize the bit line BL and the bit line bar BLB according to the first voltage VDDA. The sensing circuit  600  is electrically connected to the bit line BL, the bit line bar BLB, the second voltage VCSA and an inverted voltage SAN. The sensing circuit  600  is configured to sense a storage message of the storage capacitor SC according to the second voltage VCSA and transmit the storage message to one of the bit line BL and the bit line bar BLB. The voltage equalization circuit  500  is adjacent to the sensing circuit  600 , i.e., a load terminal of the first voltage VDDA is adjacent to a load terminal of the second voltage VCSA. The detail of internal structures and read-write operations of the storage unit  400 , the voltage equalization circuit  500  and the sensing circuit  600  is known in the prior art. The structure of the memory unit Mb_B is the same as the structure of the memory unit Mb_T, and will not be described again herein. 
     Therefore, the power management circuit  100  in the low-power double data rate memory of the present disclosure utilizes the low dropout regulator  200  combined with the power network structure  300  and uses the first voltage VDDA as an external power supply to generate the second voltage VCSA, so that the line width of the power supply only requires 4 um to solve the problem of the conventional technology (e.g., using a third voltage VDD 1  (as shown in  FIG.  7   ) as the external power supply to generate the second voltage VCSA) that the line width of the power supply requires 22 um and is too large. In the LPDDR4 memory, the external power supply is inputted from the pads PAD_T, PAD_B. Take the pad PAD_T for example, because the line transmitting the third voltage VDD 1  does not have the grid shape, the line transmitting the third voltage VDD 1  (corresponding to the position of the first voltage VDDA in  FIG.  1   ) is separated from the low dropout regulator  200  by a distance D. The distance D is equal to 5000 um, and the line width of the power supply requires 22 um. However, in the present disclosure, the first voltage VDDA is used as the external power supply instead of the third voltage VDD 1 , and the line transmitting the first voltage VDDA (i.e., the first power network circuit  310 ) has the grid shape, so that the distance between the first power network circuit  310  and the low dropout regulator  200  can be greatly shortened, and the line width of the power supply only requires 4 um. In addition, the load terminal of the first voltage VDDA (e.g., the voltage equalization circuit  500 ) is adjacent to the load terminal of the second voltage VCSA (e.g., the sensing circuit  600 ). The structure of the first power network circuit  310  and the second power network circuit  320  can greatly shorten the distance between the first connecting point CP 1  and the second connecting point CP 2 , thereby saving the line width of the power supply by 81%. 
     Please refer to  FIGS.  3 ,  6  and  7   .  FIG.  6    shows a schematic view of a power management circuit  100   a  in a low-power double data rate memory according to a second embodiment of the present disclosure.  FIG.  7    shows a schematic view of a first low dropout regulator  200   a  and a second low dropout regulator  700   a  of the power management circuit  100   a  in the low-power double data rate memory of  FIG.  6   . The power management circuit  100   a  in the low-power double data rate memory is configured to manage a plurality of power supplies of the low-power double data rate memory according to a first reference voltage VREF 1 , a second reference voltage VREF 2  and a control signal EN. The power management circuit  100   a  in the low-power double data rate memory includes the first low dropout regulator  200   a , the second low dropout regulator  700   a  and a power network structure  300 . The first low dropout regulator  200   a  has a first transmitting terminal T 1  and a second transmitting terminal T 2 . The first transmitting terminal T 1  is configured to transmit a first voltage VDDA of the power supplies. The second transmitting terminal T 2  is configured to transmit a second voltage VCSA of the power supplies, and the first low dropout regulator  200   a  adjusts a first voltage difference between the first voltage VDDA and the second voltage VCSA according to the first reference voltage VREF 1 . Moreover, the second low dropout regulator  700   a  has a third transmitting terminal T 3 , a fourth transmitting terminal T 4  and a fifth transmitting terminal T 5 . The third transmitting terminal T 3  is configured to transmit a third voltage VDD 1  of the power supplies. The fourth transmitting terminal T 4  is configured to transmit the first voltage VDDA of the power supplies. The fifth transmitting terminal T 5  is configured to transmit a fourth voltage VDD 2  of the power supplies. The second low dropout regulator  700   a  adjusts a second voltage difference between the third voltage VDD 1  and the first voltage VDDA according to the second reference voltage VREF 2  and the control signal EN, and adjusts a third voltage difference between the fourth voltage VDD 2  and the first voltage VDDA according to the control signal EN. The power network structure  300  is electrically connected to the first low dropout regulator  200   a  and the second low dropout regulator  700   a  and has a unit network space. The power network structure  300  is electrically connected to the first transmitting terminal T 1  and the second transmitting terminal T 2  through a first connecting point CP 1  and a second connecting point CP 2 . The second connecting point CP 2  is separated from the first connecting point CP 1  by a distance D 3 , and the distance D 3  is smaller than or equal to the unit network space. The unit network space is equal to one of the first unit network space D 1  and the second unit network space D 2  of  FIG.  3   . Therefore, the power management circuit  100   a  in the low-power double data rate memory of the present disclosure can utilize the control signal EN to switch the operation of the second low dropout regulator  700   a  in the standby mode and short circuit the first voltage VDDA and the fourth voltage VDD 2 , thus reducing the first voltage VDDA and the second voltage VCSA. In other words, the present disclosure can not only greatly save the power consumption of the third voltage VDD 1 , but also effectively reduce the leakage current of the circuit. 
     Please refer to  FIGS.  2 ,  6 ,  7  and  8   .  FIG.  8    shows a circuit diagram of the second low dropout regulator  700   a  of  FIG.  7   . The low-power double data rate memory may be a LPDDR4 memory. The first low dropout regulator  200   a  includes a first transistor  210   a  and a first comparator  220   a . The first transistor  210   a  and the first comparator  220   a  are the same as the transistor  210  and the comparator  220  of the low dropout regulator  200  in  FIG.  2   , respectively. The second low dropout regulator  700   a  includes a second transistor  710 , a third transistor  720 , a second comparator  730  and a fourth transistor  740 . The second transistor  710  is electrically connected between the third transmitting terminal T 3  and the fourth transmitting terminal T 4 . The third transistor  720  is electrically connected between the fourth transmitting terminal T 4  and the fifth transmitting terminal T 5  and controlled by the control signal EN. The second comparator  730  is electrically connected to the third transmitting terminal T 3 , the fourth transmitting terminal T 4  and the second transistor  710 . The second comparator  730  is configured to compare the second reference voltage VREF 2  and the first voltage VDDA to generate a second comparison signal, and the second comparison signal is electrically connected to the second transistor  710  to adjust the second voltage difference between the third voltage VDD 1  and the first voltage VDDA. The fourth transistor  740  is electrically connected to the second comparator  730  and controlled by the control signal EN. Each of the second transistor  710  and the third transistor  720  is a PMOS transistor, and the fourth transistor  740  is an NMOS transistor. In the specifications of the LPDDR4 memory, the range of the third voltage VDD 1  is from 1.70 V to 1.95 V, and the range of the fourth voltage VDD 2  is from 1.06 V to 1.17 V. In one embodiment of the present disclosure, the first voltage VDDA is equal to 1.35 V, and the second voltage VCSA is equal to 0.94 V. The third voltage VDD 1  is equal to 1.80 V, and the fourth voltage VDD 2  is equal to 1.10 V, but the present disclosure is not limited thereto. In addition, the second low dropout regulator  700   a  further includes a resistor R 2  and a capacitor C 2 . The resistor R 2  and the capacitor C 2  are electrically connected between the gate electrode and the drain electrode of the second transistor  710 . The second comparator  730  includes a plurality of transistors P 21 , P 22 , N 21 , N 22 , N 23 . The transistor N 21  is electrically connected between the transistor P 21  and the transistor N 23 . The transistor N 22  is electrically connected between the transistor P 22  and the transistor N 23 , and the transistors P 21 , P 22  are connected to each other. The transistors N 21 , N 22 , N 23  are controlled by the second reference voltage VREF 2 , the first voltage VDDA and a bias voltage VN, respectively. Each of the transistors P 21 , P 22  is the PMOS transistor, and each of the transistors N 21 , N 22 , N 23  is the NMOS transistor. 
     The first low dropout regulator  200   a , the second low dropout regulator  700   a  and the power network structure  300  are all disposed in a chip. The chip is made of CMOS and includes a first metal layer and a second metal layer. The first power network circuit  310  and the second power network circuit  320  are located in the first metal layer and the second metal layer, respectively. The power network structure  300  and the memory units Mb_T, Mb_B are the same as the power network structure  300  and the memory units Mb_T, Mb_B of the power management circuit  100  in the low-power double data rate memory of  FIGS.  3  and  1   , respectively. Therefore, the power management circuit  100   a  in the low-power double data rate memory of the present disclosure can utilize the control signal EN to switch the operation of the second low dropout regulator  700   a  in the standby mode and short circuit the first voltage VDDA and the fourth voltage VDD 2 , thus reducing the first voltage VDDA and the second voltage VCSA. In other words, the present disclosure can not only greatly save the power consumption of the third voltage VDD 1 , but also effectively reduce the leakage current of the circuit. 
     Please refer to  FIGS.  1 ,  2 ,  3  and  9   .  FIG.  9    shows a flow chart of a management method  800  of a power management circuit  100  in a low-power double data rate memory according to a third embodiment of the present disclosure. The management method  800  may be applied to the power management circuit  100  in the low-power double data rate memory of  FIG.  1   . The management method  800  of the power management circuit  100  in the low-power double data rate memory is configured to manage a plurality of power supplies of the low-power double data rate memory according to a reference voltage VREF. The management method  800  of the power management circuit  100  in the low-power double data rate memory includes performing a voltage supplying step S 2  and a voltage regulating step S 4 . The voltage supplying step S 2  includes supplying a first voltage VDDA to a first power network circuit  310  of a power network structure  300  and a low dropout regulator  200 . The voltage regulating step S 4  includes configuring the low dropout regulator  200  to generate a second voltage VCSA according to the first voltage VDDA and adjust a first voltage difference between the first voltage VDDA of a first transmitting terminal T 1  and the second voltage VCSA of a second transmitting terminal T 2  according to the reference voltage VREF. Therefore, the management method  800  of the power management circuit  100  in the low-power double data rate memory of the present disclosure utilizes the low dropout regulator  200  combined with the power network structure  300  and uses the first voltage VDDA as an external power supply to generate the second voltage VCSA, so that the line width of the power supply only requires 4 um to solve the problem of the conventional technology (e.g., using a third voltage VDD 1  as the external power supply to generate the second voltage VCSA) that the line width of the power supply requires 22 um and is too large. 
     Please refer to  FIGS.  3 ,  6 ,  7  and  9   . The management method  800  of  FIG.  9    may be applied to the power management circuit  100   a  in the low-power double data rate memory of  FIG.  6   . The management method  800  of the power management circuit  100   a  in the low-power double data rate memory is configured to manage a plurality of power supplies of the low-power double data rate memory according to a first reference voltage VREF 1 , a second reference voltage VREF 2  and a control signal EN. The management method  800  of the power management circuit  100   a  in the low-power double data rate memory includes performing a voltage supplying step S 2  and a voltage regulating step S 4 . 
     The voltage supplying step S 2  includes supplying a third voltage VDD 1  and a fourth voltage VDD 2  to a second low dropout regulator  700   a  and supplying a first voltage VDDA to a first power network circuit  310  of a power network structure  300  and a first low dropout regulator  200   a  via the second low dropout regulator  700   a.    
     The voltage regulating step S 4  includes configuring the first low dropout regulator  200   a  to generate a second voltage VCSA according to the first voltage VDDA and adjust a first voltage difference between the first voltage VDDA of a first transmitting terminal T 1  and the second voltage VCSA of a second transmitting terminal T 2  according to the first reference voltage VREF 1 . In addition, the voltage regulating step S 4  further includes configuring the second low dropout regulator  700   a  to adjust a second voltage difference between the third voltage VDD 1  of a third transmitting terminal T 3  and the first voltage VDDA of a fourth transmitting terminal T 4  according to the second reference voltage VREF 2  and the control signal EN, and adjust a third voltage difference between the fourth voltage VDD 2  of a fifth transmitting terminal T 5  and the first voltage VDDA of the fourth transmitting terminal T 4  according to the control signal EN. In the voltage regulating step S 4 , the control signal EN is configured to turn on and off the second low dropout regulator  700   a . In response to determining that the control signal EN is at a high voltage level, the second low dropout regulator  700   a  is turned on to enter a normal mode and adjusts the second voltage difference between the third voltage VDD 1  of the third transmitting terminal T 3  and the first voltage VDDA of the fourth transmitting terminal T 4  according to the second reference voltage VREF 2 . On the contrary, in response to determining that the control signal EN is at a low voltage level, the second low dropout regulator  700   a  is turned off to enter a standby mode, and reduces the third voltage difference between the fourth voltage VDD 2  of the fifth transmitting terminal T 5  and the first voltage VDDA of the fourth transmitting terminal T 4 . In the specifications of the LPDDR4 memory, the standby mode includes a first standby mode IDD 2 P and a second standby mode IDD 6 S. Therefore, the management method  800  of the power management circuit  100   a  in the low-power double data rate memory of the present disclosure can utilize the control signal EN to switch the operation of the second low dropout regulator  700   a  in the standby mode and short circuit the first voltage VDDA and the fourth voltage VDD 2 , thus reducing the first voltage VDDA and the second voltage VCSA. In other words, the present disclosure can not only greatly save the power consumption of the third voltage VDD 1 , but also effectively reduce the leakage current of the circuit. 
     In other embodiments, the distance between the first connecting point and the second connecting point may be a straight line distance between the first connecting point and the second connecting point. The first unit network space may be a diagonal distance of a first unit grid of the first power network circuit. The second unit network space may be a diagonal distance of a second unit grid of the second power network circuit. The distance between the first connecting point and the second connecting point is smaller than or equal to one of the first unit network space and the second unit network space, but the present disclosure is not limited thereto. 
     According to the aforementioned embodiments and examples, the advantages of the present disclosure are described as follows. 
     1. The power management circuit in the low-power double data rate memory and the management method thereof of the present disclosure utilize the low dropout regulator combined with the power network structure and use the first voltage as an external power supply to generate the second voltage, so that the line width of the power supply only requires 4 um to solve the problem of the conventional technology (e.g., using the third voltage as the external power supply to generate the second voltage) that the line width of the power supply requires 22 um and is too large. In other words, the line width of the power supply can be saved by 81%. 
     2. The power management circuit in the low-power double data rate memory and the management method thereof of the present disclosure can utilize the control signal to switch the operation of the second low dropout regulator in the standby mode and short circuit the first voltage and the fourth voltage, thus reducing the first voltage and the second voltage. In other words, the present disclosure can not only greatly save the power consumption of the third voltage, but also effectively reduce the leakage current of the circuit. 
     Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.