Patent Publication Number: US-9893714-B2

Title: Configurable FIR filter with segmented cells

Description:
BACKGROUND 
     The present invention generally relates to integrated circuits, and, more particularly, to a finite impulse response filter. 
     Finite impulse response (FIR) filters are commonly used in digital signal processing applications such as image processing, audio processing, and video processing applications. FIR filters include decimation filters, interpolation filters, symmetric filters, and asymmetric filters. Decimation and interpolation filters change a sampling rate of input samples and hence, are multi-rate filters. Symmetric and asymmetric filters perform filtering without changing the sampling rate of the input samples and hence, are single-rate filters. 
     A decimation filter removes M−1 samples out of every M samples of an input signal, thereby down-sampling the input signal by a factor of M. An interpolation filter inserts L−1 samples between adjacent samples of an input signal, thereby up-sampling the input signal by a factor of L. In order to reduce the hardware required for interpolation and decimation, polyphase filters are used for achieving interpolation and decimation. A conventional interpolation filter cannot be used as decimation filter and a conventional decimation filter cannot be used as an interpolation filter. This leads to an increase in circuit area and power dissipation. 
     Techniques for overcoming the aforementioned problem involve configuring a programmable logic device (PLD) as an FIR filter. The PLD can be operated in either interpolation or decimation mode as required. However, this technique does not support run-time configurability for changing the number of filter taps. The technique also does not support use of polyphase filters, so still there is additional circuit area and power consumption. The technique also does not support cascading of two or more FIR filters and hence, cannot achieve quadrature error compensation. 
     It would be advantageous to have a FIR filter that supports run-time configurability, yet does not consume unnecessary power and area, and supports quadrature error compensation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements. 
         FIG. 1  is a schematic block diagram of a FIR filter circuit that includes first and second segment cells in accordance with an embodiment of the present invention; 
         FIG. 2  is a schematic block diagram of the first segment cell of  FIG. 1  in accordance with an embodiment of the present invention; 
         FIG. 3  is a schematic block diagram of the second segment cell of  FIG. 1  in accordance with an embodiment of the present invention; 
         FIG. 4  is a timing diagram illustrating control signals when the first segment cell is configured as an interpolation filter in accordance with an embodiment of the present invention; 
         FIG. 5  is a timing diagram illustrating the control signals when the first segment cell is configured as a decimation filter in accordance with an embodiment of the present invention; 
         FIG. 6  is a timing diagram illustrating the control signals when the first segment cell is configured as a symmetric filter in accordance with an embodiment of the present invention; 
         FIG. 7  is a timing diagram illustrating the control signals when the first segment cell is configured as an asymmetric filter in accordance with an embodiment of the present invention; 
         FIG. 8  is a schematic block diagram of a cascaded unit formed by cascading the first and second segment cells in accordance with an embodiment of the present invention; 
         FIGS. 9A and 9B  are a timing diagram illustrating the control signals when the cascaded unit is configured as an interpolation filter in accordance with an embodiment of the present invention; 
         FIGS. 10A and 10B  are a timing diagram illustrating the control signals when the cascaded unit is configured as a decimation filter in accordance with an embodiment of the present invention; 
         FIGS. 11A and 11B  are a timing diagram illustrating the control signals when the cascaded unit is configured as a symmetric filter in accordance with an embodiment of the present invention; 
         FIGS. 12A and 12B  are a timing diagram illustrating the control signals when the cascaded unit is configured as an asymmetric filter in accordance with an embodiment of the present invention; 
         FIGS. 13A and 13B  are a timing diagram illustrating the control signals when the cascaded unit is configured as a complex symmetric filter in accordance with an embodiment of the present invention; and 
         FIGS. 14A and 14B  are a timing diagram illustrating the control signals when the cascaded unit is configured as a complex asymmetric filter in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present invention, and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention. As used herein, the term multiplexer has been abbreviated as a mux. 
     In an embodiment of the present invention, a finite impulse response (FIR) filter circuit is provided. The FIR filter circuit includes a plurality of segment cells. Each segment cell of the plurality of segment cells is configurable as at least one of an interpolation filter, a decimation filter, a symmetric filter, and an asymmetric filter. Two or more segment cells are configurable to be connected in cascade to form at least one of an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, and a complex asymmetric filter. A first segment cell of the plurality of segment cells outputs first, second, third, and fourth output signals. The first segment cell includes first through thirteenth multiplexers, first through fourth adders, first and second multipliers, an accumulator, and first and second tapped delay lines. The first multiplexer receives a first input signal and a second input signal. The first multiplexer outputs a first intermediate signal based on a first control signal. The second multiplexer receives a third input signal and the first intermediate signal. The second multiplexer outputs a second intermediate signal based on a second control signal. The first tapped delay line receives the second intermediate signal. The first tapped delay line includes first and second filter taps for generating first and second tapped signals based on a first enable signal, respectively. The first segment cell outputs the second tapped signal as the first output signal. The third multiplexer receives a fourth input signal and the first output signal. The third multiplexer outputs a third intermediate signal based on a third control signal. The fourth multiplexer receives a fifth input signal, the first intermediate signal, and the third intermediate signal. The fourth multiplexer outputs a fourth intermediate signal based on the second control signal and a fourth control signal. The second tapped delay line receives the fourth intermediate signal. The second tapped delay line includes third and fourth filter taps for generating third and fourth tapped signals based on a second enable signal, respectively. The first segment cell outputs the fourth tapped signal as the second output signal. The first adder receives the first and fourth tapped signals and generates a first adder signal. The second adder receives the second and third tapped signals and generates a second adder signal. The fifth multiplexer receives the first tapped signal and the first adder signal. The fifth multiplexer outputs a fifth intermediate signal based on the fourth control signal. The sixth multiplexer receives the second tapped signal and the second adder signal. The sixth multiplexer outputs a sixth intermediate signal based on the fourth control signal. The seventh multiplexer receives the fifth intermediate signal and the third tapped signal. The seventh multiplexer outputs a seventh intermediate signal based on a fifth control signal. The eighth multiplexer receives the sixth intermediate signal and the fourth tapped signal. The eighth multiplexer outputs an eighth intermediate signal based on the fifth control signal. The ninth multiplexer receives first and second signals indicative of first and second coefficient values, respectively. The ninth multiplexer outputs a ninth intermediate signal based on a sixth control signal. The ninth intermediate signal is indicative of a first value. The tenth multiplexer receives third and fourth signals indicative of third and fourth coefficient values, respectively. The tenth multiplexer outputs a tenth intermediate signal based on the sixth control signal. The tenth intermediate signal is indicative of a second value. The first multiplier receives the seventh and ninth intermediate signals. The first multiplier multiplies the seventh intermediate signal with the first value and generates a first multiplier output signal. The second multiplier receives the eighth and tenth intermediate signals. The second multiplier multiplies the eighth intermediate signal with the second value and generates a second multiplier output signal. The eleventh multiplexer receives the first input signal and a first logic low signal. The eleventh multiplexer outputs an eleventh intermediate signal based on a seventh control signal. The third adder receives the first multiplier output signal, the second multiplier output signal, and the eleventh intermediate signal. The third adder generates a third adder signal. The twelfth multiplexer receives the first and second input signals. The twelfth multiplexer outputs a twelfth intermediate signal based on an eighth control signal. The first segment cell outputs the twelfth intermediate signal as the third output signal. The first accumulator receives the third adder signal and generates a first accumulator signal. The fourth adder receives the twelfth intermediate signal and the third adder signal and generates a fourth adder signal. The thirteenth multiplexer receives the third adder signal, the first accumulator signal, and the fourth adder signal. The thirteenth multiplexer outputs the fourth output signal based on a ninth control signal. The ninth control signal is a multi-bit signal. 
     Various embodiments of the present invention provide a finite impulse response (FIR) filter circuit. The FIR filter circuit includes a plurality of segment cells. Each segment cell of the plurality of segment cells is configurable as at least one of an interpolation filter, a decimation filter, a symmetric filter, and an asymmetric filter. Two or more segment cells of the plurality of segment cells are configurable to be connected in cascade to form an at least one of an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, and a complex asymmetric filter. The FIR filter circuit includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter circuit further includes control circuits corresponding to the segment cells for generating control signals. 
     The FIR filter circuit provides flexibility to cascade two or more segment cells to form at least one of an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, and a complex asymmetric filter. The number of filter taps in delay lines of the segment cells can be varied as per requirement. Further, the FIR filter circuit can be designed to achieve any interpolation and decimation factors. The FIR filter circuit uses pre-adders for reducing the number of multipliers required when a segment cell or more than one segment cell are configured as a symmetric filter, thereby reducing area requirement. Further, the FIR filter circuit can be configured for various signal processing applications such as, but not limited to, image processing application, audio processing application, video processing application, and quadrature error compensation. 
     Referring now to  FIG. 1 , a schematic block diagram of a finite impulse response (FIR) filter circuit  100  in accordance with an embodiment of the present invention is shown. The FIR filter circuit  100  includes first and second segment cells  102   a  and  102   b  (collectively referred to as “segment cells  102 ”). The FIR filter circuit  100  further includes first and second control circuits  104   a  and  104   b  corresponding to the first and second segment cells  102   a  and  102   b . The FIR filter circuit  100  includes first and second registers  106   a  and  106   b  corresponding to the first and second segment cells  102   a  and  102   b.    
     Referring now to  FIG. 2 , a schematic block diagram of the first segment cell  102   a  in accordance with an embodiment of the present invention is shown. The first segment cell  102   a  includes first through thirteenth muxes  202   a - 202   m , first through fourth adders  204   a - 204   d , first and second multipliers  206   a  and  206   b , and a first accumulator  208 . The first segment cell  102   a  further includes first through fourth filter taps  210   a - 210   d . The first and second filter taps  210   a  and  210   b  are connected in cascade and form a first tapped delay line. The third and fourth filter taps  210   c  and  210   d  are connected in cascade and form a second tapped delay line. 
     The first register  106   a  stores first through fourth coefficient values (C 1 -C 4 ) and outputs first through fourth signals (V 1 -V 4 ), respectively. 
     The first control circuit  104   a  generates a first set of signals including first and second enable signals (V EN   _   1  and V EN   _   2 ) and first through ninth control signals (V CNT   _   1 -V CNT   _   9 ). In an example, the first control circuit  104   a  is connected to the first register  106   a  for receiving the first through fourth signals. 
     The first mux  202   a  has a first input terminal for receiving a first input signal (V IN   _   1 ) and a second input terminal for receiving a second input signal (V IN   _   2 ). The first mux  202   a  has a select terminal connected to the first control circuit  104   a  for receiving the first control signal and an output terminal for outputting a first intermediate signal (V INT   _   1 ). The first mux  202   a  outputs the first input signal as the first intermediate signal when the first control signal is at logic low state. The first mux  202   a  outputs the second input signal as the first intermediate signal when the first control signal is at logic high state. 
     The second mux  202   b  has a first input terminal for receiving a third input signal (V IN   _   3 ) and a second input terminal connected to the output terminal of the first mux  202   a  for receiving the first intermediate signal. The second mux  202   b  has a select terminal connected to the first control circuit  104   a  for receiving the second control signal and an output terminal for outputting a second intermediate signal (V INT   _   2 ). The second mux  202   b  outputs the third input signal as the second intermediate signal when the second control signal is at logic low state. The second mux  202   b  outputs the first intermediate signal as the second intermediate signal when the second control signal is at logic high state. 
     The first tapped delay line is connected to the output terminal of the second mux  202   b  for receiving the second intermediate signal. The first tapped delay line is further connected to the first control circuit  104   a  for receiving the first enable signal. The first and second filter taps  210   a  and  210   b  generate first and second tapped signals (V TAP   _   1  and V TAP   _   2 ), respectively, based on the first enable signal. The first and second filter taps  210   a  and  210   b  are enabled when the first control circuit  104   a  enables the first enable signal. The first segment cell  102   a  outputs the second tapped signal as a first output signal (V OUT   _   1 ). 
     The third mux  202   c  has a first input terminal for receiving a fourth input signal (V IN   _   4 ) and a second input terminal connected to the first tapped delay line for receiving the first output signal. The third mux  202   c  has a select terminal connected to the first control circuit  104   a  for receiving the third control signal and an output terminal for outputting a third intermediate signal (V INT   _   3 ). The third mux  202   c  outputs the fourth input signal as the third intermediate signal when the third control signal is at logic low state. The third mux  202   c  outputs the first output signal as the third intermediate signal when the third control signal is at logic high state. 
     The fourth mux  202   d  has a first input terminal for receiving a fifth input signal (V IN   _   5 ), a second input terminal connected to the output terminal of the first mux  202   a  for receiving the first intermediate signal, and a third input terminal connected to the output terminal of the third mux  202   c  for receiving the third intermediate signal. The fourth mux  202   d  has a two-bit select terminal connected to the first control circuit  104   a  for receiving the second and fourth control signals and an output terminal for outputting a fourth intermediate signal (V INT   _   4 ). The fourth mux  202   d  outputs the fifth input signal as the fourth intermediate signal when the second and fourth control signals are at logic low state. The fourth mux  202   d  outputs the first intermediate signal as the fourth intermediate signal when the second and fourth control signals are at logic high and logic low states, respectively. The fourth mux  202   d  outputs the third intermediate signal as the fourth intermediate signal when the second and fourth control signals are at logic low and logic high states, respectively. In an embodiment, the fourth mux  202   d  has a fourth input terminal connected to the output terminal of the third mux  202   c  for receiving the third intermediate signal. 
     The second tapped delay line is connected to the output terminal of the fourth mux  202   d  for receiving the fourth intermediate signal. The second tapped delay line is further connected to the first control circuit  104   a  for receiving the second enable signal. The third and fourth filter taps  210   c  and  210   d  generate third and fourth tapped signals (V TAP   _   3  and V TAP   _   4 ), respectively, based on the second enable signal. The third and fourth filter taps  210   c  and  210   d  are enabled when the first control circuit  104   a  enables the second enable signal. The first segment cell  102   a  outputs the fourth tapped signal as a second output signal (V OUT   _   2 ). 
     The first adder  204   a  has first and second input terminals connected to the first and fourth filter taps  210   a  and  210   d  for receiving the first and fourth tapped signals, respectively. The first adder  204   a  has an output terminal for generating a first adder signal (V ADD   _   1 ). 
     The second adder  204   b  has first and second input terminals connected to the second and third filter taps  210   b  and  210   c  for receiving the second and third tapped signals, respectively. The second adder  204   b  has an output terminal for generating a second adder signal (V ADD   _   2 ). 
     The fifth mux  202   e  has a first input terminal connected to the first filter tap  210   a  for receiving the first tapped signal and a second input terminal connected to the output terminal of the first adder  204   a  for receiving the first adder signal. The fifth mux  202   e  has a select terminal connected to the first control circuit  104   a  for receiving the fourth control signal and an output terminal for outputting a fifth intermediate signal (V INT   _   5 ). The fifth mux  202   e  outputs the first tapped signal as the fifth intermediate signal when the fourth control signal is at logic low state. The fifth mux  202   e  outputs the first adder signal as the fifth intermediate signal when the fourth control signal is at logic high state. 
     The sixth mux  202   f  has a first input terminal connected to the second filter tap  210   b  for receiving the second tapped signal and a second input terminal connected to the output terminal of the second adder  204   b  for receiving the second adder signal. The sixth mux  202   f  has a select terminal connected to the first control circuit  104   a  for receiving the fourth control signal and an output terminal for outputting a sixth intermediate signal (V INT   _   6 ). The sixth mux  202   f  outputs the second tapped signal as the sixth intermediate signal when the fourth control signal is at logic low state. The sixth mux  202   f  outputs the second adder signal as the sixth intermediate signal when the fourth control signal is at logic high state. 
     The seventh mux  202   g  has a first input terminal connected to the output terminal of the fifth mux  202   e  for receiving the fifth intermediate signal and a second input terminal connected to the third filter tap  210   c  for receiving the third tapped signal. The seventh mux  202   g  has a select terminal connected to the first control circuit  104   a  for receiving the fifth control signal and an output terminal for outputting a seventh intermediate signal (V INT   _   7 ). The seventh mux  202   g  outputs the fifth intermediate signal as the seventh intermediate signal when the fifth control signal is at logic low state. The seventh mux  202   g  outputs the third tapped signal as the seventh intermediate signal when the fifth control signal is at logic high state. 
     The eighth mux  202   h  has a first input terminal connected to the output terminal of the sixth mux  202   f  for receiving the sixth intermediate signal and a second input terminal connected to the fourth filter tap  210   d  for receiving the fourth tapped signal. The eighth mux  202   h  has a select terminal connected to the first control circuit  104   a  for receiving the fifth control signal and an output terminal for outputting an eighth intermediate signal (V INT   _   8 ). The eighth mux  202   h  outputs the sixth intermediate signal as the eighth intermediate signal when the fifth control signal is at logic low state. The eighth mux  202   h  outputs the fourth tapped signal as the eighth intermediate signal when the fifth control signal is at logic high state. 
     The ninth mux  202   i  has a first input terminal for receiving the first signal and a second input terminal for receiving the second signal. The ninth mux  202   i  has a select terminal connected to the first control circuit  104   a  for receiving the sixth control signal and an output terminal for outputting a ninth intermediate signal (V INT   _   9 ). The ninth intermediate signal is indicative of a first value. The ninth mux  202   i  outputs the first signal as the ninth intermediate signal when the sixth control signal is at logic low state. The ninth mux  202   i  outputs the second signal as the ninth intermediate signal when the sixth control signal is at logic high state. 
     The tenth mux  202   j  has a first input terminal for receiving the third signal and a second input terminal for receiving the fourth signal. The tenth mux  202   j  has a select terminal connected to the first control circuit  104   a  for receiving the sixth control signal and an output terminal for outputting a tenth intermediate signal (V INT   _   10 ). The tenth intermediate signal is indicative of a second value. The tenth mux  202   j  outputs the third signal as the tenth intermediate signal when the sixth control signal is at logic low state. The tenth mux  202   j  outputs the fourth signal as the tenth intermediate signal when the sixth control signal is at logic high state. 
     The first multiplier  206   a  is connected to the output terminals of the seventh and ninth muxes  202   g  and  202   i  for receiving the seventh and ninth intermediate signals, respectively. The first multiplier  206   a  multiplies the seventh intermediate signal with the first value and generates a first multiplier output signal (V MUL   _   OUT   _   1 ). 
     The second multiplier  206   b  is connected to the output terminals of the eighth and tenth muxes  202   h  and  202   j  for receiving the eighth and tenth intermediate signals, respectively. The second multiplier  206   b  multiplies the eighth intermediate signal with the second value and generates a second multiplier output signal (V MUL   _   OUT   _   2 ). 
     The eleventh mux  202   k  has a first input terminal for receiving the first input signal and a second input terminal for receiving a first logic low signal (V LOW   _   1 ). The eleventh mux  202   k  has a select terminal connected to the first control circuit  104   a  for receiving the seventh control signal and an output terminal for outputting an eleventh intermediate signal (V INT   _   11 ). The eleventh mux  202   k  outputs the first input signal as the eleventh intermediate signal when the seventh control signal is at logic low state. The eleventh mux  202   k  outputs the first logic low signal as the eleventh intermediate signal when the seventh control signal is at logic high state. 
     The third adder  204   c  has first, second, and third input terminals connected to the first multiplier  206   a , the second multiplier  206   b , and the output terminal of the eleventh mux  202   k  for receiving the first multiplier output signal, the second multiplier output signal, and the eleventh intermediate signal, respectively. The third adder  204   c  has an output terminal for generating a third adder signal (V ADD   _   3 ). 
     The twelfth mux  202   l  has first and second input terminals for receiving the first and second input signals, respectively. The twelfth mux  202   l  has a select terminal connected to the first control circuit  104   a  for receiving the eighth control signal and an output terminal for outputting a twelfth intermediate signal (V INT   _   12 ). The twelfth mux  202   l  outputs the first input signal as the twelfth intermediate signal when the eighth control signal is at logic low state. The twelfth mux  202   l  outputs the second input signal as the twelfth intermediate signal when the eighth control signal is at logic high state. The first segment cell  102   a  outputs the twelfth intermediate signal as a third output signal (V OUT   _   3 ). 
     The first accumulator  208  is connected to the output terminal of the third adder  204   c  for receiving the third adder signal. The first accumulator  208  generates a first accumulator signal (V ACC   _   1 ). 
     The fourth adder  204   d  has first and second input terminals connected to the output terminals of the twelfth mux  202   l  and the third adder  204   c  for receiving the twelfth intermediate signal and the third adder signal, respectively. The fourth adder  204   d  has an output terminal for generating a fourth adder signal (V ADD   _   4 ). 
     The thirteenth mux  202   m  has a first input terminal connected to the output terminal of the third adder  204   c  for receiving the third adder signal, a second input terminal connected to the first accumulator  208  for receiving the first accumulator signal, and a third input terminal connected to the output terminal of the fourth adder  204   d  for receiving the fourth adder signal. The thirteenth mux  202   m  has a two-bit select terminal for receiving the ninth control signal and an output terminal for outputting a fourth output signal (V OUT   _   4 ). The ninth control signal is a multi-bit signal. The thirteenth mux  202   m  outputs the third adder signal as the fourth output signal when a value corresponding to the ninth control signal is zero. The thirteenth mux  202   m  outputs the first accumulator signal as the fourth output signal when the value corresponding to the ninth control signal is one. The thirteenth mux  202   m  outputs the fourth adder signal as the fourth output signal when the value corresponding to the ninth control signal is two. 
     Referring now to  FIG. 3 , a schematic block diagram of the second segment cell  102   b  in accordance with an embodiment of the present invention is shown. The second segment cell  102   b  includes fourteenth through twenty-sixth muxes  302   a - 302   m , fifth through eighth adders  304   a - 304   d , third and fourth multipliers  306   a  and  306   b , and a second accumulator  308 . The second segment cell  102   b  further includes fifth through eighth filter taps  310   a - 310   d . The fifth and sixth filter taps  310   a  and  310   b  are connected in cascade and form a third tapped delay line. The seventh and eighth filter taps  310   c  and  310   d  are connected in cascade and form a fourth tapped delay line. 
     The second register  106   b  stores fifth through eighth coefficient values (C 5 -C 8 ) and outputs fifth through eighth signals (V 5 -V 8 ), respectively. 
     The second control circuit  104   b  generates a second set of signals including third and fourth enable signals (V EN   _   3  and V EN   _   4 ) and tenth through eighteenth control signals (V CNT   _   10 -V CNT   _   18 ). In an example, the second control circuit  104   b  is connected to the second register  106   b  for receiving the fifth through eighth signals. 
     The fourteenth mux  302   a  has a first input terminal for receiving a sixth input signal (V IN   _   6 ) and a second input terminal for receiving a seventh input signal (V IN   _   7 ). The fourteenth mux  302   a  has a select terminal connected to the second control circuit  104   b  for receiving the tenth control signal and an output terminal for outputting a thirteenth intermediate signal (V INT   _   13 ). The fourteenth mux  302   a  outputs the sixth input signal as the thirteenth intermediate signal when the tenth control signal is at logic low state. The fourteenth mux  302   a  outputs the seventh input signal as the thirteenth intermediate signal when the tenth control signal is at logic high state. 
     The fifteenth mux  302   b  has a first input terminal for receiving an eighth input signal (V IN   _   8 ) and a second input terminal connected to the output terminal of the fourteenth mux  302   a  for receiving the thirteenth intermediate signal. The fifteenth mux  302   b  has a select terminal connected to the second control circuit  104   b  for receiving the eleventh control signal and an output terminal for outputting a fourteenth intermediate signal (V INT   _   14 ). The fifteenth mux  302   b  outputs the eighth input signal as the fourteenth intermediate signal when the eleventh control signal is at logic low state. The fifteenth mux  302   b  outputs the thirteenth intermediate signal as the fourteenth intermediate signal when the eleventh control signal is at logic high state. 
     The third tapped delay line is connected to the output terminal of the fifteenth mux  302   b  for receiving the fourteenth intermediate signal. The third tapped delay line is further connected to the second control circuit  104   b  for receiving the third enable signal. The fifth and sixth filter taps  310   a  and  310   b  generate fifth and sixth tapped signals (V TAP   _   5  and V TAP   _   6 ), respectively, based on the third enable signal. The fifth and sixth filter taps  310   a  and  310   b  are enabled when the second control circuit  104   b  enables the third enable signal. The second segment cell  102   b  outputs the sixth tapped signal as a fifth output signal (V OUT   _   5 ). 
     The sixteenth mux  302   c  has a first input terminal for receiving a ninth input signal (V IN   _   9 ) and a second input terminal connected to the third tapped delay line for receiving the fifth output signal. The sixteenth mux  302   c  has a select terminal connected to the second control circuit  104   b  for receiving the twelfth control signal and an output terminal for outputting a fifteenth intermediate signal (V INT   _   15 ). The sixteenth mux  302   c  outputs the ninth input signal as the fifteenth intermediate signal when the twelfth control signal is at logic low state. The sixteenth mux  302   c  outputs the fifth output signal as the fifteenth intermediate signal when the twelfth control signal is at logic high state. 
     The seventeenth mux  302   d  has a first input terminal for receiving a tenth input signal (V IN   _   10 ), a second input terminal connected to the output terminal of the fourteenth mux  302   a  for receiving the thirteenth intermediate signal, and a third input terminal connected to the output terminal of the sixteenth mux  302   c  for receiving the fifteenth intermediate signal. The seventeenth mux  302   d  has a two-bit select terminal connected to the second control circuit  104   b  for receiving the eleventh and thirteenth control signals and an output terminal for outputting a sixteenth intermediate signal (V INT   _   16 ). The seventeenth mux  302   d  outputs the tenth input signal as the sixteenth intermediate signal when the eleventh and thirteenth control signals are at logic low state. The seventeenth mux  302   d  outputs the thirteenth intermediate signal as the sixteenth intermediate signal when the eleventh and thirteenth control signals are at logic high and logic low states, respectively. The seventeenth mux  302   d  outputs the fifteenth intermediate signal as the sixteenth intermediate signal when the eleventh and thirteenth control signals are at logic low and logic high states, respectively. In an embodiment, the seventeenth mux  302   d  has a fourth input terminal connected to the output terminal of the sixteenth mux  302   c  for receiving the fifteenth intermediate signal. 
     The fourth tapped delay line is connected to the output terminal of the seventeenth mux  302   d  for receiving the sixteenth intermediate signal. The fourth tapped delay line is further connected to the second control circuit  104   b  for receiving the fourth enable signal. The seventh and eighth filter taps  310   c  and  310   d  generate seventh and eighth tapped signals (V TAP   _   7  and V TAP   _   8 ), respectively, based on the fourth enable signal. The seventh and eighth filter taps  310   c  and  310   d  are enabled when the second control circuit  104   b  enables the fourth enable signal. The second segment cell  102   b  outputs the eighth tapped signal as a sixth output signal (V OUT   _   6 ). 
     The fifth adder  304   a  has first and second input terminals connected to the fifth and eighth filter taps  310   a  and  310   d  for receiving the fifth and eighth tapped signals, respectively. The fifth adder  304   a  has an output terminal for generating a fifth adder signal (V ADD   _   5 ). 
     The sixth adder  304   b  has first and second input terminals connected to the sixth and seventh filter taps  310   b  and  310   c  for receiving the sixth and seventh tapped signals, respectively. The sixth adder  304   b  has an output terminal for generating a sixth adder signal (V ADD   _   6 ). 
     The eighteenth mux  302   e  has a first input terminal connected to the fifth filter tap  310   a  for receiving the fifth tapped signal and a second input terminal connected to the output terminal of the fifth adder  304   a  for receiving the fifth adder signal. The eighteenth mux  302   e  has a select terminal connected to the second control circuit  104   b  for receiving the thirteenth control signal and an output terminal for outputting a seventeenth intermediate signal (V INT   _   17 ). The eighteenth mux  302   e  outputs the fifth tapped signal as the seventeenth intermediate signal when the thirteenth control signal is at logic low state. The eighteenth mux  302   e  outputs the fifth adder signal as the seventeenth intermediate signal when the thirteenth control signal is at logic high state. 
     The nineteenth mux  302   f  has a first input terminal connected to the sixth filter tap  310   b  for receiving the sixth tapped signal and a second input terminal connected to the output terminal of the sixth adder  304   b  for receiving the sixth adder signal. The nineteenth mux  302   f  has a select terminal connected to the second control circuit  104   b  for receiving the thirteenth control signal and an output terminal for outputting an eighteenth intermediate signal (V INT   _   18 ). The nineteenth mux  302   f  outputs the sixth tapped signal as the eighteenth intermediate signal when the thirteenth control signal is at logic low state. The nineteenth mux  302   f  outputs the sixth adder signal as the eighteenth intermediate signal when the thirteenth control signal is at logic high state. 
     The twentieth mux  302   g  has a first input terminal connected to the output terminal of the eighteenth mux  302   e  for receiving the seventeenth intermediate signal and a second input terminal connected to the seventh filter tap  310   c  for receiving the seventh tapped signal. The twentieth mux  302   g  has a select terminal connected to the second control circuit  104   b  for receiving the fourteenth control signal and an output terminal for outputting a nineteenth intermediate signal (V INT   _   19 ). The twentieth mux  302   g  outputs the seventeenth intermediate signal as the nineteenth intermediate signal when the fourteenth control signal is at logic low state. The twentieth mux  302   g  outputs the seventh tapped signal as the nineteenth intermediate signal when the fourteenth control signal is at logic high state. 
     The twenty-first mux  302   h  has a first input terminal connected to the output terminal of the nineteenth mux  302   f  for receiving the eighteenth intermediate signal and a second input terminal connected to the eighth filter tap  310   d  for receiving the eighth tapped signal. The twenty-first mux  302   h  has a select terminal connected to the second control circuit  104   b  for receiving the fourteenth control signal and an output terminal for outputting a twentieth intermediate signal (V INT   _   20 ). The twenty-first mux  302   h  outputs the eighteenth intermediate signal as the twentieth intermediate signal when the fourteenth control signal is at logic low state. The twenty-first mux  302   h  outputs the eighth tapped signal as the twentieth intermediate signal when the fourteenth control signal is at logic high state. 
     The twenty-second mux  302   i  has a first input terminal for receiving the fifth signal and a second input terminal for receiving the sixth signal. The twenty-second mux  302   i  has a select terminal connected to the second control circuit  104   b  for receiving the fifteenth control signal and an output terminal for outputting a twenty-first intermediate signal (V INT   _   21 ). The twenty-first intermediate signal is indicative of a third value. The twenty-second mux  302   i  outputs the fifth signal as the twenty-first intermediate signal when the fifteenth control signal is at logic low state. The twenty-second mux  302   i  outputs the sixth signal as the twenty-first intermediate signal when the fifteenth control signal is at logic high state. 
     The twenty-third mux  302   j  has a first input terminal for receiving the seventh signal and a second input terminal for receiving the eighth signal. The twenty-third mux  302   j  has a select terminal connected to the second control circuit  104   b  for receiving the fifteenth control signal and an output terminal for outputting a twenty-second intermediate signal (V INT   _   22 ). The twenty-second intermediate signal is indicative of a fourth value. The twenty-third mux  302   j  outputs the seventh signal as the twenty-second intermediate signal when the fifteenth control signal is at logic low state. The twenty-third mux  302   j  outputs the eighth signal as the twenty-second intermediate signal when the fifteenth control signal is at logic high state. 
     The third multiplier  306   a  is connected to the output terminals of the twentieth and twenty-second muxes  302   g  and  302   i  for receiving the nineteenth and twenty-first intermediate signals, respectively. The third multiplier  306   a  multiplies the nineteenth intermediate signal with the third value and generates a third multiplier output signal (V MUL   _   OUT   _   3 ). 
     The fourth multiplier  306   b  is connected to the output terminals of the twenty-first and twenty-third muxes  302   h  and  302   j  for receiving the twentieth and twenty-second intermediate signals, respectively. The fourth multiplier  306   b  multiplies the twentieth intermediate signal with the fourth value and generates a fourth multiplier output signal (V MUL   _   OUT   _   4 ). 
     The twenty-fourth mux  302   k  has a first input terminal for receiving the sixth input signal and a second input terminal for receiving a second logic low signal (V LOW   _   2 ). The twenty-fourth mux  302   k  has a select terminal connected to the second control circuit  104   b  for receiving the sixteenth control signal and an output terminal for outputting a twenty-third intermediate signal (V INT   _   23 ). The twenty-fourth mux  302   k  outputs the sixth input signal as the twenty-third intermediate signal when the sixteenth control signal is at logic low state. The twenty-fourth mux  302   k  outputs the second logic low signal as the twenty-third intermediate signal when the sixteenth control signal is at logic high state. 
     The seventh adder  304   c  has first, second, and third input terminals connected to the third multiplier  306   a , the fourth multiplier  306   b , and the output terminal of the twenty-fourth mux  302   k  for receiving the third multiplier output signal, the fourth multiplier output signal, and the twenty-third intermediate signal, respectively. The seventh adder  304   c  has an output terminal for generating a seventh adder signal (V ADD   _   7 ). 
     The twenty-fifth mux  302   l  has first and second input terminals for receiving the sixth and seventh input signals, respectively. The twenty-fifth mux  302   l  has a select terminal connected to the second control circuit  104   b  for receiving the seventeenth control signal and an output terminal for outputting a twenty-fourth intermediate signal (V INT   _   24 ). The twenty-fifth mux  302   l  outputs the sixth input signal as the twenty-fourth intermediate signal when the seventeenth control signal is at logic low state. The twenty-fifth mux  302   l  outputs the seventh input signal as the twenty-fourth intermediate signal when the seventeenth control signal is at logic high state. The second segment cell  102   b  outputs the twenty-fourth intermediate signal as a seventh output signal (V OUT   _   7 ). 
     The second accumulator  308  is connected to the output terminal of the seventh adder  304   c  for receiving the seventh adder signal. The second accumulator  308  generates a second accumulator signal (V ACC   _   2 ). 
     The eighth adder  304   d  has first and second input terminals connected to the output terminals of the twenty-fifth mux  302   l  and the seventh adder  304   c  for receiving the twenty-fourth intermediate signal and the seventh adder signal, respectively. The eighth adder  304   d  has an output terminal for generating an eighth adder signal (V ADD   _   8 ). 
     The twenty-sixth mux  302   m  has a first input terminal connected to the output terminal of the seventh adder  304   c  for receiving the seventh adder signal, a second input terminal connected to the second accumulator  308  for receiving the second accumulator signal, and a third input terminal connected to the output terminal of the eighth adder  304   d  for receiving the eighth adder signal. The twenty-sixth mux  302   m  has a two-bit select terminal for receiving the eighteenth control signal and an output terminal for outputting an eighth output signal (V OUT   _   8 ). The eighteenth control signal is a multi-bit signal. The twenty-sixth mux  302   m  outputs the seventh adder signal as the eighth output signal when a value corresponding to the eighteenth control signal is zero. The twenty-sixth mux  302   m  outputs the second accumulator signal as the eighth output signal when the value corresponding to the eighteenth control signal is one. The twenty-sixth mux  302   m  outputs the eighth adder signal as the eighth output signal when the value corresponding to the eighteenth control signal is two. 
     In an embodiment of the invention, the first control circuit  104   a  includes a third register (not shown) for storing a first set of values. The first set of values includes values that are indicative of the first control signal, the second control signal, the third control signal, the fourth control signal, the seventh control signal, and the eighth control signal. The first set of values further includes values that are indicative of the input and output operating frequencies of the first segment cell  102   a . The second control circuit  104   b  includes a fourth register (not shown) for storing a second set of values. The second set of values includes values that are indicative of the tenth control signal, the eleventh control signal, the twelfth control signal, the thirteenth control signal, the sixteenth control signal, and the seventeenth control signal. The second set of values further includes values that are indicative of the input and output operating frequencies of the second segment cell  102   b . In an example, the input and output operating frequencies of the first and second segment cells  102   a  and  102   b  are generated based on a clock frequency of a system that includes the FIR filter circuit  100 . 
     A user can configure each segment cell  102  as at least one of an interpolation filter, a decimation filter, a symmetric filter, and an asymmetric filter. In an example, the user can configure the first segment cell  102   a  as at least one of an interpolation filter, a decimation filter, a symmetric filter, and an asymmetric filter by providing the first set of values. Thus, the first control circuit  104   a  generates the first control signal, the second control signal, the third control signal, the fourth control signal, the seventh control signal, and the eighth control signal based on the first set of values. The user further provides first and second ratios. The first ratio is the ratio of the clock frequency of the system (hereinafter referred to as “system clock frequency”) to the input operating frequency of the first segment cell  102   a . The second ratio is the ratio of the system clock frequency to the output operating frequency of the first segment cell  102   a . The first control circuit  104   a  generates the first and second enable signals and the fifth and sixth control signals based on the first and second ratios. In an embodiment, the user provides a value indicative of the ninth control signal when the first segment cell  102   a  is configured as at least one of an interpolation filter, a symmetric filter, and an asymmetric filter. In another embodiment, the first control circuit  104   a  generates the ninth control signal based on at least one of the first set of values and the first and second ratios. 
     Referring now to  FIG. 4 , a timing diagram illustrating the control signals when the first segment cell  102   a  is configured as an interpolation filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the fourth control signal, the seventh control signal, and the ninth control signal in the first set of values are zero, one, zero, one, and zero, respectively. The first ratio is 2 and the second ratio is 1. Thus, the input operating frequency of the first segment cell  102   a  (V SEG1   _   IN   _   CLK ) is half times the system clock frequency (V SYS   _   CLK ). The output operating frequency of the first segment cell  102   a  is equal to the system clock frequency. Hence, the interpolation factor is 2. The first control circuit  104   a  generates the first, second, fourth, seventh, and ninth control signals at logic low state, logic high state, logic low state, logic high state, and logic low state, respectively. The first control circuit  104   a  generates the second enable signal and the fifth control signal at logic low state. 
     The first control circuit  104   a  generates the first enable signal at a frequency equal to the input operating frequency of the first segment cell  102   a . Thus, the first and second filter taps  210   a  and  210   b  latch values of corresponding input signals for a time period corresponding to the input operating frequency of the first segment cell  102   a  for generating the first and second tapped signals, respectively. As the interpolation factor is 2, the first control circuit  104   a  generates the sixth control signal at a frequency that is twice the input operating frequency of the first segment cell  102   a.    
     During time period T 0 -T 1 , the first control circuit  104   a  generates the sixth control signal at logic low state. Thus, the first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the first and third coefficient values, respectively, thereby generating a weighted first tapped signal and a weighted second tapped signal as the first and second multiplier output signals, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating a first intermediate adder signal as the third adder signal. The thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. 
     During time period T 1 -T 2 , as the first control circuit  104   a  generates the sixth control signal at logic high state, the first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the second and fourth coefficient values, respectively, thereby generating a weighted first tapped signal and a weighted second tapped signal as the first and second multiplier output signals, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating a second intermediate adder signal as the third adder signal. The thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. 
     Thus, the first segment cell  102   a  outputs at a frequency that is twice the input operating frequency thereof. 
     Referring now to  FIG. 5 , a timing diagram illustrating the control signals when the first segment cell  102   a  is configured as a decimation filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the fourth control signal, and the seventh control signal are zero, one, zero, and one, respectively. In the example, the first ratio is 2 and the second ratio is 4. Thus, the input operating frequency of the first segment cell  102   a  is half times the system clock frequency. The output operating frequency of the first segment cell  102   a  is one fourth times the system clock frequency. Hence, the decimation factor is 2. 
     The first control circuit  104   a  generates the first and second enable signals at a frequency that is half times the input operating frequency of the first segment cell  102   a . Thus, the first through fourth filters taps  210   a - 210   d  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the input operating frequency of the first segment cell  102   a . The first control circuit  104   a  generates the first control signal, the second control signal, the fourth control signal, and the seventh control signal at logic low state, logic high state, logic low state, and logic high state, respectively. 
     During time period T 0 -T 2 , the first control circuit  104   a  generates the first enable signal at logic high state and the fifth and sixth control signals at logic low state. Thus, the first and second filter taps  210   a  and  210   b  latch corresponding input signals and generate the first and second tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the first coefficient value and the third coefficient value, respectively, thereby generating a weighted first tapped signal and a weighted second tapped signal as the first and second multiplier output signals, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. 
     During time period T 2 -T 4 , the first control circuit  104   a  generates the first and second enable signals at logic low state. Hence, the first through fourth filter taps  210   a - 210   d  are disabled. 
     During time period T 4 -T 6 , the first control circuit  104   a  generates the second enable signal at logic high state and the fifth and sixth control signals at logic high state. Thus, the third and fourth filter taps  210   c  and  210   d  latch corresponding input signals and generate third and fourth tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the third and fourth tapped signals with the second coefficient value and the fourth coefficient value, respectively, thereby generating a weighted third tapped signal and a weighted fourth tapped signal as the first and second multiplier output signals, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. The first accumulator  208  accumulates the third adder signal generated by the third adder  204   c  during the time period T 0 -T 6 . As the first control circuit  104   a  generates the ninth control signal such that the value corresponding to the ninth control signal is one during the time period T 4 -T 6 , the thirteenth mux  202   m  outputs the second accumulator signal as the fourth output signal. 
     Thus, the first segment cell  102   a  outputs at a frequency that is half times the input operating frequency thereof. 
     Referring now to  FIG. 6 , a timing diagram illustrating the control signals when the first segment cell  102   a  is configured as a symmetric filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the third control signal, the fourth control signal, the seventh control signal, and the ninth control signal are zero, one, one, one, one, and zero, respectively. The first ratio is 2 and the second ratio is 2. Thus, the input and output operating frequencies of the first segment cell  102   a  are half times the system clock frequency. 
     The first control circuit  104   a  generates the first and second enable signals at a frequency that is half times the system clock frequency. Thus, the first through fourth filters taps  210   a - 210   d  latch values of corresponding input signals for a time period corresponding to the input operating frequency of the first segment cell  102   a . The first control circuit  104   a  generates the first, second, third, fourth, seventh, and ninth control signals at logic low state, logic high state, logic high state, logic high state, logic high state, and logic low state, respectively. The first control circuit  104   a  generates the fifth and sixth control signals at logic low state. 
     During time period T 0 -T 2 , the first control circuit  104   a  generates the first and second enable signals at logic high state. The first through fourth filter taps  210   a - 210   d  generate the first through fourth tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the first and second adder signals with the first and third coefficient values for generating a weighted first adder signal and a weighted second adder signal as the first multiplier output signal and the second multiplier output signal, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. As the value corresponding to the ninth control signal is zero, the thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. 
     During time period T 2 -T 4 , the first control circuit  104   a  generates the first and second enable signals at logic low state and hence, the first through fourth filter taps  210   a - 210   d  are disabled. 
     Referring now to  FIG. 7 , a timing diagram illustrating the control signals when the first segment cell  102   a  is configured as an asymmetric filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the fourth control signal, the seventh control signal, and the ninth control signal are zero, one, zero, one, and zero, respectively. The first ratio is 2 and the second ratio is 2. Thus, the input and output operating frequencies of the first segment cell  102   a  are half times the system clock frequency. 
     The first control circuit  104   a  generates the first enable signal at a frequency that is half times the system clock frequency. Thus, the first and second filters taps  210   a  and  210   b  latch values of corresponding input signals for a time period corresponding to the input operating frequency of the first segment cell  102   a . The first control circuit  104   a  the first, second, fourth, seventh, and ninth control signals at logic low state, logic high state, logic low state, logic high state, and logic low state, respectively. The first control circuit  104   a  generates the second enable signal and the fifth and sixth control signals at logic low state. 
     During time period T 0 -T 2 , the first control circuit  104   a  generates the first enable signal at logic high state. The first and second filter taps  210   a  and  210   b  generate the first and second tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the first and third coefficient values for generating a weighted first tapped signal and a weighted second tapped signal as the first multiplier output signal and the second multiplier output signal, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. As the value corresponding to the ninth control signal is zero, the thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. 
     During time period T 2 -T 4 , the first control circuit  104   a  generates the first enable signal at logic low state and hence, the first and second filter taps  210   a  and  210   b  are disabled. 
     Thus, the first and second adder  204   a  and  204   b  pre-add the respective input signals, thereby reducing the number of multipliers required when the first segment cell  102   a  is configured as a symmetric filter. 
     Referring now to  FIG. 8 , a schematic block diagram of a cascaded unit  802  in accordance with an embodiment of the present invention is shown. The cascaded unit  802  is formed by cascading the first and second segment cells  102   a  and  102   b . The second segment cell  102   b  receives the first, second, third, and fourth output signals as the eighth, tenth, seventh, and sixth input signals, respectively. 
     A user can configure the cascaded unit  802  as at least one of an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, and a complex asymmetric filter by providing the first and second sets of values. Thus, the first control circuit  104   a  generates the first control signal, the second control signal, the third control signal, the fourth control signal, the seventh control signal, and the eighth control signal based on the first set of values and the second control circuit  104   b  generates the tenth control signal, the eleventh control signal, the twelfth control signal, the thirteenth control signal, the sixteenth control signal, and the seventeenth control signal based on the second set of values. The user further provides the first ratio, the second ratio, a third ratio, and a fourth ratio. The third ratio is the ratio of the system clock frequency to the input operating frequency of the second segment cell  102   b . The fourth ratio is the ratio of the system clock frequency to the output operating frequency of the second segment cell  102   b . The first control circuit  104   a  generates the first and second enable signals and the fifth and sixth control signals based on the first and second ratios. The second control circuit  104   b  generates the third and fourth enable signals and the fourteenth and fifteenth control signals based on the third and fourth ratios. In an embodiment, the user provides values indicative of the ninth control signal and the eighteenth control signal when the cascaded unit  802  is configured as at least one of an interpolation filter, a symmetric filter, and an asymmetric filter. In another embodiment, the first control circuit  104   a  generates the ninth control signal based on at least one of the first set of values and the first and second ratios, and the second control circuit  104   b  generates the eighteenth control signal based on the second set of values and the third and fourth ratios. 
     Referring now to  FIGS. 9A and 9B , a timing diagram illustrating the control signals when the cascaded unit  802  is configured as an interpolation filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the fourth control signal, the seventh control signal, and the ninth control signal in the first set of values are zero, one, zero, one, and zero, respectively. The values corresponding to the eleventh control signal, the thirteenth control signal, the sixteenth control signal, and the eighteenth control signal in the second set of values are zero. The first and third ratios are 2 and the second and fourth ratios are 1. Thus, the input operating frequencies of the first and second segment cells  102   a  and  102   b  are half times the system clock frequency. The output operating frequencies of the first and second segment cells  102   a  and  102   b  are equal to the system clock frequency. Hence, the interpolation factor is 2. The first control circuit  104   a  generates the first, second, fourth, seventh, and ninth control signals at logic low state, logic high state, logic low state, logic high state, and logic low state, respectively. The first control circuit  104   a  generates the second enable signal and the fifth control signal at logic low state. The second control circuit  104   b  generates the eleventh, thirteenth, sixteenth, and eighteenth control signals at logic low state. The second control circuit  104   b  generates the fourth enable signal and the fourteenth control signal at logic low state. 
     The first and second control circuits  104   a  and  104   b  generate the first and third enable signals, respectively, at a frequency that is half times the system clock frequency. Thus, the first and second filter taps  210   a  and  210   b  and the fifth and sixth filter taps  310   a  and  310   b  latch values of corresponding input signals at the frequency that is half times the system clock frequency for generating the first, second, fifth, and sixth tapped signals, respectively. As the interpolation factor is 2, the first and second control circuits  104   a  and  104   b  generate the sixth and fifteenth control signals, respectively, at a frequency that is equal to the system clock frequency. 
     During time period T 0 -T 1 , the first and second control circuits  104   a  and  104   b  generate the sixth and fifteenth control signals at logic low state, respectively. Thus, the first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the first and third coefficient values, respectively, thereby generating a weighted first tapped signal and a weighted second tapped signal as the first and second multiplier output signals, respectively. The third and fourth multipliers  306   a  and  306   b  multiply the fifth and sixth tapped signals with the fifth and seventh coefficient values, respectively, thereby generating a weighted fifth tapped signal and a weighted sixth tapped signal as the third and fourth multiplier output signals, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. The thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. The seventh adder  304   c  adds the fourth output signal, the third and fourth multiplier output signals for generating the seventh adder signal. The twenty-sixth mux  302   m  outputs the seventh adder signal as the eighth output signal. 
     During time period T 1 -T 2 , as the first control circuit  104   a  generates the sixth control signal at logic high state, the first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the second and fourth coefficient values, respectively, thereby generating a weighted first tapped signal and a weighted second tapped signal as the first and second multiplier output signals, respectively. As the second control circuit  104   b  generates the fifteenth control signal at logic high state, the third and fourth multipliers  306   a  and  306   b  multiply the fifth and sixth tapped signals with the sixth and eighth coefficient values, respectively, thereby generating a weighted fifth tapped signal and a weighted sixth tapped signal as the third and fourth multiplier output signals, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. The thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. The seventh adder  304   c  adds the fourth output signal, the third and fourth multiplier output signals for generating the seventh adder signal. The twenty-sixth mux  302   m  outputs the seventh adder signal as the eighth output signal. 
     Thus, the cascaded unit  802  outputs at a frequency that is twice the input operating frequency of the first segment cell  102   a , i.e., at a frequency equal to the system clock frequency. 
     Referring now to  FIGS. 10A and 10B , a timing diagram illustrating the control signals when the cascaded unit  802  is configured as a decimation filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the fourth control signal, and the seventh control signal are zero, one, zero, and one, respectively. The values corresponding to the eleventh control signal, the thirteenth control signal, and the sixteenth control signal are zero. In the example, the first and third ratios are 2 and the second and fourth ratios are 4. Thus, the input operating frequencies of the first and second segment cells  102   a  and  102   b  are half times the system clock frequency. The output operating frequencies of the first and second segment cells  102   a  and  102   b  are one fourth times the system clock frequency. Hence, the decimation factor is 2. 
     The first control circuit  104   a  generates the first and second enable signals at a frequency that is half times the input operating frequency of the first segment cell  102   a . The second control circuit  104   b  generates the third and fourth enable signals at a frequency that is half times the input operating frequency of the second segment cell  102   b . Thus, the first through fourth filter taps  210   a - 210   d  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the input operating frequency of the first segment cell  102   a  and the fifth through eighth filter taps  310   a - 310   d  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the input operating frequency of the second segment cell  102   b . The first control circuit  104   a  generates the first control signal, the second control signal, the fourth control signal, and the seventh control signal at logic low state, logic high state, logic low state, and logic high state, respectively. The second control circuit  104   b  generates the eleventh control signal, the thirteenth control signal, and the sixteenth control signal at logic low state. 
     During time period T 0 -T 2 , the first control circuit  104   a  generates the first enable signal at logic high state and the fifth and sixth control signals at logic low state. Thus, the first and second filter taps  210   a  and  210   b  latch corresponding input signals and generate the first and second tapped signals, respectively. The second control circuit  104   b  generates the third enable signal at logic high state and the fourteenth and fifteenth control signals at logic low state. Thus, the fifth and sixth filter taps  310   a  and  310   b  latch corresponding input signals and generate the fifth and sixth tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the first coefficient value and the third coefficient value, respectively, thereby generating a weighted first tapped signal and a weighted second tapped signal as the first and second multiplier output signals, respectively. The third and fourth multipliers  306   a  and  306   b  multiply the fifth and sixth tapped signals with the fifth coefficient value and the seventh coefficient value, respectively, thereby generating a weighted fifth tapped signal and a weighted sixth tapped signal as the third and fourth multiplier output signals, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. The seventh adder  304   c  adds the fourth output signal, and the third and fourth multiplier output signals for generating the seventh adder signal. 
     During time period T 2 -T 4 , the first control circuit  104   a  generates the first and second enable signals at logic low state. Hence, the first through fourth filter taps  210   a - 210   d  are disabled. The second control circuit  104   b  generates the third and fourth enable signals at logic low state. Hence, the fifth through eighth filter taps  310   a - 310   d  are disabled. 
     During time period T 4 -T 6 , the first control circuit  104   a  generates the second enable signal at logic high state and the fifth and sixth control signals at logic high state. Thus, the third and fourth filter taps  210   c  and  210   d  latch corresponding input signals and generate the third and fourth tapped signals, respectively. The second control circuit  104   b  generates the fourth enable signal at logic high state and the fourteenth and fifteenth control signals at logic high state. Thus, the seventh and eighth filter taps  310   c  and  310   d  latch corresponding input signals and generate the seventh and eighth tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the third and fourth tapped signals with the second coefficient value and the fourth coefficient value, respectively, thereby generating a weighted third tapped signal and a weighted fourth tapped signal as the first and second multiplier output signals, respectively. The third and fourth multipliers  306   a  and  306   b  multiply the seventh and eighth tapped signals with the sixth coefficient value and the eighth coefficient value, respectively, thereby generating a weighted seventh tapped signal and a weighted eighth tapped signal as the third and fourth multiplier output signals, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. The seventh adder  304   c  adds the fourth output signal and the third and fourth multiplier output signals for generating the seventh adder signal. The first accumulator  208  accumulates the third adder signal generated by the third adder  204   c  during the time period T 0 -T 6 . The second accumulator  308  accumulates the seventh adder signal generated by the seventh adder  304   c  during the time period T 0 -T 6 . As the first control circuit  104   a  generates the ninth control signal such that the value of the ninth control signal is one during the time period T 4 -T 6 , the thirteenth mux  202   m  outputs the first accumulator signal as the fourth output signal. As the second control circuit  104   b  generates the eighteenth control signal such that the value of the eighteenth control signal is one during the time period T 4 -T 6 , the twenty-sixth mux  302   m  outputs the second accumulator signal as the eighth output signal. 
     Thus, the cascaded unit  802  outputs at a frequency that is half times the input operating frequency of the first segment cell  102   a.    
     Referring now to  FIGS. 11A and 11B , a timing diagram illustrating the control signals when the cascaded unit  802  is configured as a symmetric filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the third control signal, the fourth control signal, the seventh control signal, and the ninth control signal are zero, one, zero, one, one, and zero, respectively. The values corresponding to the eleventh, twelfth, thirteenth, sixteenth, and eighteenth control signals are zero, one, one, zero, and zero, respectively. The first, second, third, and fourth ratios are 2. Thus, the input and output operating frequencies of the first and second segment cells  102   a  and  102   b  are half times the system clock frequency. The first segment cell  104   a  receives the sixth output signal as the fourth input signal. 
     The first control circuit  104   a  generates the first and second enable signals at a frequency that is half times the system clock frequency. Thus, the first through fourth filters taps  210   a - 210   d  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the system clock frequency. The second control circuit  104   b  generates the third and fourth enable signals at a frequency that is half times the system clock frequency. Thus, the fifth through eighth filters taps  310   a - 310   d  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the system clock frequency. The first control circuit  104   a  generates the first, second, third, fourth, seventh, and ninth control signals at logic low state, logic high state, logic low state, logic high state, logic high state, and logic low state, respectively. The first control circuit  104   a  generates the fifth and sixth control signals at logic low state. The second control circuit  104   b  generates the eleventh, twelfth, thirteenth, sixteenth, and eighteenth control signals at logic low state, logic high state, logic high state, logic low state, and logic low state, respectively. The second control circuit  104   b  generates the fourteenth and fifteenth control signals at logic low state. 
     During time period T 0 -T 2 , the first control circuit  104   a  generates the first and second enable signals at logic high state. The first through fourth filter taps  210   a - 210   d  generate the first through fourth tapped signals, respectively. The second control circuit  104   b  generates the third and fourth enable signals at logic high state. The fifth through eighth filter taps  310   a - 310   d  generate the fifth through eighth tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the first and second adder signals with the first and third coefficient values for generating a weighted first adder signal and a weighted second adder signal as the first multiplier output signal and the second multiplier output signal, respectively. The third and fourth multipliers  306   a  and  306   b  multiply the fifth and sixth adder signals with the fifth and seventh coefficient values for generating a weighted fifth adder signal and a weighted sixth adder signal as the third multiplier output signal and the fourth multiplier output signal, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. As the value corresponding to the ninth control signal is zero, the thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. The seventh adder  304   c  adds the fourth output signal, the third and fourth multiplier output signals for generating the seventh adder signal. As the value corresponding to the eighteenth control signal is zero, the twenty-sixth mux  302   m  outputs the seventh adder signal as the eighth output signal. 
     During time period T 2 -T 4 , the first control circuit  104   a  generates the first and second enable signals at logic low state and hence, the first through fourth filter taps  210   a - 210   d  are disabled. The second control circuit  104   b  generates the third and fourth enable signals at logic low state and hence, the fifth through eighth filter taps  310   a - 310   d  are disabled. 
     Referring now to  FIGS. 12A and 12B , a timing diagram illustrating the control signals when the cascaded unit  802  is configured as an asymmetric filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the fourth control signal, the seventh control signal, and the ninth control signal are zero, one, zero, one, and zero, respectively. The values corresponding to the eleventh, thirteenth, sixteenth, and eighteenth control signals are zero. The first, second, third, and fourth ratios are 2. Thus, the input and output operating frequencies of the first and second segment cells  102   a  and  102   b  are half times the system clock frequency. 
     The first control circuit  104   a  generates the first enable signal at a frequency that is half times the system clock frequency. Thus, the first and second filters taps  210   a  and  210   b  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the system clock frequency. The second control circuit  104   b  generates the third enable signal at a frequency that is half times the system clock frequency. Thus, the fifth and sixth filters taps  310   a  and  310   b  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the system clock frequency. The first control circuit  104   a  the first, second, fourth, seventh, and ninth control signals at logic low state, logic high state, logic low state, logic high state, and logic low state, respectively. The second control circuit  104   b  generates the eleventh, thirteenth, sixteenth, and eighteenth control signals at logic low state. The first control circuit  104   a  generates the second enable signal and the fifth and sixth control signals at logic low state. The second control circuit  104   b  generates the fourth enable signal and the fourteenth and fifteenth control signals at logic low state. 
     During time period T 0 -T 2 , the first control circuit  104   a  generates the first enable signal at logic high state. The first and second filter taps  210   a  and  210   b  generate the first and second tapped signals, respectively. The second control circuit  104   b  generates the third enable signal at logic high state. The fifth and sixth filter taps  310   a  and  310   b  generate the fifth and sixth tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the first and third coefficient values for generating a weighted first tapped signal and a weighted second tapped signal as the first multiplier output signal and the second multiplier output signal, respectively. The third and fourth multipliers  306   a  and  306   b  multiply the fifth and sixth tapped signals with the fifth and seventh coefficient values for generating a weighted fifth tapped signal and a weighted sixth tapped signal as the third multiplier output signal and the fourth multiplier output signal, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. As the value corresponding to the ninth control signal is zero, the thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. The seventh adder  304   c  adds the fourth output signal and the third and fourth multiplier output signals for generating the seventh adder signal. As the value corresponding to the eighteenth control signal is zero, the twenty-sixth mux  302   m  outputs the seventh adder signal as the eighth output signal. 
     During time period T 2 -T 4 , the first control circuit  104   a  generates the first enable signal at logic low state and hence, the first and second filter taps  210   a  and  210   b  are disabled. The second control circuit  104   b  generates the third enable signal at logic low state and hence, the fifth and sixth filter taps  310   a  and  310   b  are disabled. 
     Referring now to  FIGS. 13A and 13B , a timing diagram illustrating the control signals when the cascaded unit  802  is configured as a complex symmetric filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the third control signal, the fourth control signal, the seventh control signal, the eighth control signal, and the ninth control signal are zero, one, one, one, one, zero, and zero, respectively. The values corresponding to the tenth, eleventh, twelfth, thirteenth, sixteenth, seventeenth, and eighteenth control signals are one, one, one, one, one, zero, and two, respectively. The first, second, third, and fourth ratios are 2. Thus, the input and output operating frequencies of the first and second segment cells  102   a  and  102   b  are half times the system clock frequency. 
     The first control circuit  104   a  generates the first and second enable signals at a frequency that is half times the system clock frequency. Thus, the first through fourth filters taps  210   a - 210   d  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the system clock frequency. The second control circuit  104   b  generates the third and fourth enable signals at a frequency that is half times the system clock frequency. Thus, the fifth through eighth filters taps  310   a - 310   d  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the system clock frequency. The first control circuit  104   a  generates the first, second, third, fourth, seventh, eighth, and ninth control signals at logic low state, logic high state, logic high state, logic high state, logic high state, logic low state, and logic low state, respectively. The first control circuit  104   a  generates the fifth and sixth control signals at logic low state. The second control circuit  104   b  generates the tenth, eleventh, twelfth, thirteenth, sixteenth, and seventeenth control signals at logic high state, logic high state, logic high state, logic high state, logic high state, and logic low state, respectively. The second control circuit  104   b  generates the eighteenth control signal such that the value corresponding to the eighteenth control signal is two. The second control circuit  104   b  generates the fourteenth and fifteenth control signals at logic low state. 
     From time T 0 -T 2 , the first control circuit  104   a  generates the first and second enable signals at logic high state. The first through fourth filter taps  210   a - 210   d  generate the first through fourth tapped signals, respectively. The second control circuit  104   b  generates the third and fourth enable signals at logic high state. The fifth through eighth filter taps  310   a - 310   d  generate the fifth through eighth tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the first and second adder signals with the first and third coefficient values for generating a weighted first adder signal and a weighted second adder signal as the first multiplier output signal and the second multiplier output signal, respectively. The third and fourth multipliers  306   a  and  306   b  multiply the fifth and sixth adder signals with the fifth and seventh coefficient values for generating a weighted fifth adder signal and a weighted sixth adder signal as the third multiplier output signal and the fourth multiplier output signal, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. As the value corresponding to the ninth control signal is zero, the thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. The seventh adder  304   c  adds the third and fourth multiplier output signals for generating the seventh adder signal. The twenty-fifth mux  302   l  outputs the sixth input signal (i.e., the fourth output signal) as the twenty-fourth intermediate signal. The eighth adder  304   d  adds the seventh adder signal and the twenty-fourth intermediate signal. As the value of the eighteenth control signal is two, the twenty-sixth mux  302   m  outputs the seventh adder signal as the eighth output signal. 
     From time T 2 -T 4 , the first control circuit  104   a  generates the first and second enable signals at logic low state and hence, the first through fourth filter taps  210   a - 210   d  are disabled. The second control circuit  104   b  generates the third and fourth enable signals at logic low state and hence, the fifth through eighth filter taps  310   a - 310   d  are disabled. 
     Referring now to  FIGS. 14A and 14B , a timing diagram illustrating the control signals when the cascaded unit  802  is configured as a complex asymmetric filter in accordance with an embodiment of the present invention is shown. In an example, the values corresponding to the first control signal, the second control signal, the fourth control signal, the seventh control signal, the eighth control signal, and the ninth control signal are zero, one, zero, one, zero, and zero, respectively. The values corresponding to the tenth, eleventh, thirteenth, sixteenth, seventeenth, and eighteenth control signals are one, one, zero, one, zero, and two, respectively. The first, second, third, and fourth ratios are 2. Thus, the input and output operating frequencies of the first and second segment cells  102   a  and  102   b  are half times the system clock frequency. 
     The first control circuit  104   a  generates the first enable signal at a frequency that is half times the system clock frequency. Thus, the first and second filter taps  210   a  and  210   b  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the system clock frequency. The second control circuit  104   b  generates the third enable signal at a frequency that is half times the system clock frequency. Thus, the fifth and sixth filters taps  310   a  and  310   b  latch values of corresponding input signals for a time period corresponding to a frequency that is half times the system clock frequency. The first control circuit  104   a  generates the first, second, fourth, seventh, eighth, and ninth control signals at logic low state, logic high state, logic low state, logic high state, logic low state, and logic low state, respectively. The first control circuit  104   a  generates the fifth and sixth control signals at logic low state. The second control circuit  104   b  generates the tenth, eleventh, thirteenth, sixteenth, and seventeenth control signals at logic high state, logic high state, logic low state, logic high state, and logic low state, respectively. The second control circuit  104   b  generates the eighteenth control signal such that the value corresponding to the eighteenth control signal is two. The second control circuit  104   b  generates the fourteenth and fifteenth control signals at logic low state. 
     From time T 0 -T 2 , the first control circuit  104   a  generates the first enable signal at logic high state. The first and second filter taps  210   a  and  210   b  generate the first and second tapped signals, respectively. The second control circuit  104   b  generates the third enable signal at logic high state. The fifth and sixth filter taps  310   a  and  310   b  generate the fifth and sixth tapped signals, respectively. The first and second multipliers  206   a  and  206   b  multiply the first and second tapped signals with the first and third coefficient values for generating a weighted first tapped signal and a weighted second tapped signal as the first multiplier output signal and the second multiplier output signal, respectively. The third and fourth multipliers  306   a  and  306   b  multiply the fifth and sixth tapped signals with the fifth and seventh coefficient values for generating a weighted fifth tapped signal and a weighted sixth tapped signal as the third multiplier output signal and the fourth multiplier output signal, respectively. The third adder  204   c  adds the first and second multiplier output signals for generating the third adder signal. As the value corresponding to the ninth control signal is zero, the thirteenth mux  202   m  outputs the third adder signal as the fourth output signal. The seventh adder  304   c  adds the third and fourth multiplier output signals for generating the seventh adder signal. The twenty-fifth mux  302   l  outputs the sixth input signal (i.e., the fourth output signal) as the twenty-fourth intermediate signal. The eighth adder  304   d  adds the seventh adder signal and the twenty-fourth intermediate signal. As the value of the eighteenth control signal is two, the twenty-sixth mux  302   m  outputs the seventh adder signal as the eighth output signal. 
     From time T 2 -T 4 , the first control circuit  104   a  generates the first enable signal at logic low state and hence, the first and second filter taps  210   a  and  210   b  are disabled. The second control circuit  104   b  generates the third enable signal at logic low state and hence, the fifth and sixth filter taps  310   a  and  310   b  are disabled. 
     Thus, the first adder  204   a , the second adder  204   b , the fifth adder  304   a , and the sixth adder  304   b  pre-add the respective input signals, thereby reducing the number of multipliers required when the cascaded unit  802  is configured as at least one of a symmetric filter and a complex symmetric filter. 
     The FIR filter circuit  100  can be designed to have any number of segment cells. Each delay line in the segment cells  102  can include any number of filter taps. The segment cells  102  can be designed to have any number of delay cells in the delay lines. The number of delay lines in the segment cells  102  can be varied based on the maximum decimation factor requirement. The FIR filter circuit  100  can be configured to achieve any interpolation factor. In an example, the ninth and tenth muxes  202   i  and  202   j  are 4:1 muxes for achieving an interpolation factor of 4. As the segment cells  102  make use of pre-adders, the number of multipliers required is decreased, thereby reducing area requirement. Further, the two or more segment cells among the segment cells  102  can be configured as at least one of an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, and a complex asymmetric filter. Thus, the FIR filter circuit  100  can be configured as a filter with real-valued coefficients. The FIR filter circuit  100  can even be configured as a filter with complex-valued coefficients. Further, the coefficient values and the first and second set of values can be changed during run-time, thereby providing run-time configurability. 
     It will be understood by those of skill in the art that a segment cell or more than one segment cell among the segment cells  102  can be configured to achieve a rational interpolation factor or a rational decimation factor. 
     It will be understood by those of skill in the art that the same logical function may be performed by different arrangements of logic gates, or that logic circuits operate using either positive or negative logic signals. Therefore, variations in the arrangement of some of the logic gates described above should not be considered to depart from the scope of the present invention. No element, act, or instruction used in the present application should be construed as critical or essential to the invention unless explicitly described as such. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. 
     While various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present invention, as described in the claims.