Patent Publication Number: US-2021166987-A1

Title: Semiconductor package structure and semiconductor manufacturing process

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 16/197,351 filed Nov. 20, 2018, the contents of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     1. Field of the Disclosure 
     The present disclosure relates to a semiconductor package structure and a semiconductor manufacturing process, and more particularly to a semiconductor package structure including thermal structure and a semiconductor manufacturing process. 
     2. Description of the Related Art 
     The trend for an electronic product is to highly integrate the elements so as to form a minimum size and obtain a best electrical performance. However, the multiple heat sources problem may occur due to multiple elements. If the heat from the elements is transmitted to a main element, a junction temperature of the main element may be too high to meet a maximum specified temperature. 
     SUMMARY 
     In some embodiments, according to an aspect, a semiconductor package structure includes a semiconductor die, at least one wiring structure, a metal support, a passive element, a plurality of signal vias, and a plurality of thermal structures. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The metal support is used for supporting the semiconductor die. The passive element is electrically connected to the semiconductor die. The signal vias are electrically connecting the passive element and the semiconductor die. The thermal structures are connected to the passive element, and the thermal structures are disposed on a periphery of the at least one wiring structure. 
     In some embodiments, according to an aspect, a semiconductor package structure includes a semiconductor die, at least one wiring structure, a passive element, a plurality of signal vias, and a plurality of thermal vias. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The passive element is electrically connected to the semiconductor die. The signal vias are electrically connecting the passive element and the semiconductor die. The thermal vias are connected to the passive element, and the thermal vias are disposed on a periphery of the at least one wiring structure. 
     In some embodiments, according to another aspect, a semiconductor manufacturing process includes: (a) providing a semiconductor package, wherein the semiconductor package includes a semiconductor die, at least one wiring structure, a plurality of signal vias and a plurality of thermal structures, the semiconductor die includes an active surface, the at least one wiring structure is electrically connected to the active surface of the semiconductor die, the signal vias are electrically connected to the semiconductor die, the thermal structures are disposed on a periphery of the at least one wiring structure; and (b) mounting a passive element on the semiconductor package, wherein the passive element is electrically connected to the signal vias and is connected to the thermal structures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 2  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 3  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 4  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 5  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 6  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 7  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 8  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 9  illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
         FIG. 10  illustrates one or more stages of an example of a semiconductor manufacturing process according to some embodiments of the present disclosure. 
         FIG. 11  illustrates one or more stages of an example of a semiconductor manufacturing process according to some embodiments of the present disclosure. 
         FIG. 12  illustrates a top view of an example of a semiconductor package structure according to some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     In the semiconductor-associated industry, according to the design specification of the semiconductor package product, the junction temperature of the semiconductor die in the semiconductor package product cannot exceed about 150° C. In a comparative example of semiconductor package structure, a passive element is electrically connected to a semiconductor die. For example, an inductor is disposed on a semiconductor die. By a simulation, before disposing the inductor, the junction temperature of the semiconductor die is about 136° C. After disposing the inductor, the junction temperature of the semiconductor die is higher than 154° C. Since the heat from the inductor is transmitted to the semiconductor die by the signal paths, the junction temperature of the semiconductor die may be above about 150° C. Thus, the semiconductor package structure product cannot meet the above design specification. 
     To address these issues, some comparative embodiments of this disclosure are directed to semiconductor package structures and methods of manufacturing semiconductor package structures that include an additional heat dissipating device such as a copper plate or a heat sink with a plurality of heat dissipating fins. However, such additional heat dissipating device will increase the total thickness or volume of the semiconductor package structure. In addition, some comparative embodiments of this disclosure are directed to semiconductor package structures and methods of manufacturing semiconductor package structures that include a thickened prepreg or a thickened die pad. However, the junction temperature of the semiconductor package structure with such thickened prepreg or thickened die pad may be about 154° C., which still can&#39;t meet the above specification. 
     To address at least the above concerns, an embodiment of the present disclosure provides a plurality of thermal structures connected to the passive element to form a plurality of thermal paths. And, the amount of the thermal structures is larger than the amount of the signal paths connecting the passive elements and the semiconductor die. The greater amount of heat from the passive element is transmitted to the thermal structures rather than to the semiconductor die. Therefore, the junction temperature of the semiconductor die may be less than about 150° C. The semiconductor package structure of the present disclosure can meet the above specification. 
       FIG. 1  illustrates a cross-sectional view of an example of a semiconductor package structure  1  according to some embodiments of the present disclosure. The semiconductor package structure  1  includes a semiconductor die  11 , at least one wiring structure  12 , a passive element  13 , a plurality of signal vias  14 , and a plurality of thermal structures  15 . The semiconductor die  11  has an active surface  111  and a back surface  112  opposite to the active surface  111 . In some embodiments, the semiconductor package structure  1  may further include a metal support  18 . The semiconductor die  11  is disposed on the metal support  18 . The metal support  18  is used for supporting the semiconductor die  11 . The metal support  18  may be a leadframe. 
     The at least one wiring structure  12  is electrically connected to the active surface  111  of the semiconductor die  11 . Thus, the active surface  111  faces the wiring structure  12 . The passive element  13  is electrically connected to the semiconductor die  11 . The signal vias  14  are electrically connecting the passive element  13  and the semiconductor die  11 . The thermal structures  15  are connected to the passive element  13 , and the thermal structures  15  are disposed on a periphery of the at least one wiring structure  12 . 
     In some embodiments, the at least one wiring structure  12  includes a first circuit layer  121  and a second circuit layer  122 . The first circuit layer  121  is electrically connected to the passive element  13 , and the second circuit layer  122  is electrically connected to the signal vias  14 . The wiring structure  12  may include a first dielectric layer  123  and a second dielectric layer  124 . The first circuit layer  121  may include a seed layer and a conductive layer. A material of the seed layer may be, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. A material of the conductive layer may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer may be omitted. The first circuit layer  121  may include the signal vias  14  disposed in the through hole of the first dielectric layer  123 , and at least one conductive pad. That is, the signal vias  14  may be a portion of the first circuit layer  121  and a portion of the wiring structure  12 . In some embodiments, the first circuit layer  121  may further include at least one trace. 
     In some embodiments, the first dielectric layer  123  covers the second circuit layer  122 , and the first dielectric layer  123  surrounds the first circuit layer  121  and the signal vias  14 . The first dielectric layer  123  may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the first dielectric layer  123  may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The first dielectric layer  123  defines at least one through hole extending through the first dielectric layer  123 . 
     In some embodiments, the second circuit layer  122  is disposed on the second dielectric layer  124 , and the second circuit layer  122  is electrically connected to the first circuit layer  121  by the signal vias  14 . The second circuit layer  122  may include a seed layer and a conductive layer. A material of the seed layer may be, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. A material of the conductive layer may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer may be omitted. The second circuit layer  122  may include at least one conductive via  125  disposed in the through hole of the second dielectric layer  124 , and at least one conductive pad. In some embodiments, the second circuit layer  122  may further include at least one trace. 
     In some embodiments, the second dielectric layer  124  surrounds the semiconductor die  11 , the conductive via  125  and the metal support  18 . The second dielectric layer  124  may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the second dielectric layer  124  may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The first dielectric layer  123  and the second dielectric layer  124  may be an isolation material. 
     In some embodiments, the passive element  13  (e.g., an inductor) includes two electrodes  131 ,  132  electrically connected to the signal vias  14  and connected to the thermal structures  15 . The two electrodes  131 ,  132  are formed as an L shape. In some embodiments, the two electrodes  131 ,  132  of the passive element  13  are disposed on the first circuit layer  121 , and are electrically connected to the first circuit layer  121 . The first circuit layer  121  is electrically connected to the signal vias  14  and is connected to the thermal structures  15 . 
     In some embodiments, the thermal structures  15  are thermal vias. The thermal structures  15  may include a plurality of first thermal vias  151 , a plurality of second thermal vias  152  and a plurality of first thermal pads  153 . The first thermal vias  151  are connected to the first circuit layer  121 . The first thermal pads  153  are disposed between the first thermal vias  151  and the second thermal vias  152 , and are connected to the first thermal vias  151  and the second thermal vias  152 . In some embodiments, the first thermal pads  153  and the second thermal vias  152  are formed at the same time as the second circuit layer  122  and the at least one conductive via  125 , respectively. The second dielectric layer  124  surrounds the second thermal vias  152 , and the first thermal pads  153  is disposed on the second dielectric layer  124 . 
     In some embodiments, an amount of the thermal structures  15  may be larger than ten times an amount of the signal vias  14 . That is, the amount of the first thermal vias  151  may be larger than ten times the amount of the signal vias  14 , or the amount of the second thermal vias  152  may be larger than ten times the amount of the signal vias  14 . In some embodiments, the amount of the thermal structures  15  may be larger than sixteen times the amount of the signal vias  14 . That is, the amount of the first thermal vias  151  may be larger than sixteen times the amount of the signal vias  14 , or the amount of the second thermal vias  152  may be larger than sixteen times the amount of the signal vias  14 . Therefore, the most heat from the passive element  13  is transmitted to the thermal structures  15  rather than to the semiconductor die  11 . The junction temperature of the semiconductor die  11  may be less than about 150° C. The semiconductor package structure  1  of the present disclosure can meet the design specifications. 
     In some embodiments, the metal support  18  includes a die pad  181 , a plurality of signal pins  182 , and a plurality of thermal pins  183 . The die pad  181 , the signal pins  182  and the thermal pins  183  are isolated from each other. The semiconductor die  11  is disposed on the die pad  181  of the metal support  18 . The back surface  112  of the semiconductor die  11  is attached to the die pad  181  of the metal support  18  by adhesion. The signal pins  182  are electrically connected to the signal vias  14 . The thermal pins  183  are connected to the thermal structures  15 . In some embodiments, the thermal pins  183  are connected to the second thermal vias  152  of the thermal structures  15 . The major part of the heat from the passive element  13  may be transmitted to the thermal structures  15  and the thermal pins  183 , and such heat may be dissipated to outside so as to reduce the temperature of the semiconductor package structure  1 . In some embodiments, the thermal pins  183  may be a portion of the thermal structures  15 . Thus, the thermal structures  15  penetrate through the isolation material including the first dielectric layer  123  and the second dielectric layer  124 . 
     In some embodiments, the semiconductor package structure  1  may further include a protection layer  19  disposed on the first dielectric layer  123 . The protection layer  19  may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators, or a solder resist layer. 
       FIG. 2  illustrates a cross-sectional view of an example of a semiconductor package structure  1   a  according to some embodiments of the present disclosure. The semiconductor package structure  1   a  shown in  FIG. 2  is similar to the semiconductor package structure  1  shown in  FIG. 1 , and the differences are described as follows. In some embodiments, the passive element  13  includes two electrodes  131   a ,  132   a  and two metal pins  133 ,  134 . The two electrodes  131   a ,  132   a  are electrically connected to the signal vias  14 , and the two metal pins  133 ,  134  are connected to the thermal structures  15 . The two electrodes  131   a ,  132   a  of the passive element  13  are disposed on the first circuit layer  121 , and are electrically connected to the first circuit layer  121 . The thermal structures  15  may further include a first thermal layer  154  that is separated from the first circuit layer  121 . The two metal pins  133 ,  134  are disposed on the first thermal layer  154 , and are connected to the first thermal layer  154 . The first thermal layer  154  is connected to the first thermal vias  151 . Because the two electrodes  131   a ,  132   a  and two metal pins  133 ,  134  are separated, the most heat from the passive element  13  is transmitted to the thermal structures  15  by the two metal pins  133 ,  134  so as to reduce the junction temperature of the semiconductor die  11 . 
       FIG. 3  illustrates a cross-sectional view of an example of a semiconductor package structure  1   b  according to some embodiments of the present disclosure. The semiconductor package structure  1   b  shown in  FIG. 3  is similar to the semiconductor package structure  1   a  shown in  FIG. 2 , and the differences are described as follows. In some embodiments, the thermal structures  15  may include a plurality of metal pillars  155  penetrating through the isolation material including the first dielectric layer  123  and the second dielectric layer  124 . The metal pillars  155  are connected to the two metal pins  133 ,  134  to transmit the most heat from the passive element  13  to outside. In some embodiments, the amount of the metal pillars  155  may be larger than ten times the amount of the signal vias  14 . In some embodiments, the amount of the metal pillars  155  may be larger than sixteen times the amount of the signal vias  14 . 
       FIG. 4  illustrates a cross-sectional view of an example of a semiconductor package structure  1   c  according to some embodiments of the present disclosure. The semiconductor package structure  1   c  shown in  FIG. 4  is similar to the semiconductor package structure  1   a  shown in  FIG. 2 , and the differences are described as follows. In some embodiments, the thermal structures  15  may include thermal plates  156 . The thermal plates  156  are connected to the two metal pins  133 ,  134 . In some embodiments, a total area of the thermal plates  156  may be larger than ten times a total area of the signal vias  14 . In some embodiments, a total area of the thermal plates  156  may be larger than sixteen times a total area of the signal vias  14 . In some embodiments, the thermal structures  15  may further include a plurality of thermal fins  157  extending from the thermal plates  156 . 
       FIG. 5  illustrates a cross-sectional view of an example of a semiconductor package structure  1   d  according to some embodiments of the present disclosure. The semiconductor package structure  1   d  includes a semiconductor die  11   a , at least one wiring structure  12   a , a passive element  13   a , a plurality of signal vias  14   a , and a plurality of thermal structures  15   a . The semiconductor die  11   a  has an active surface  111   a . The at least one wiring structure  12   a  is electrically connected to the active surface  111   a  of the semiconductor die  11   a . Thus, the active surface  111   a  faces the wiring structure  12   a . The passive element  13  is electrically connected to the semiconductor die  11   a . The passive element  13   a  includes two electrodes  131   a ,  132   a  electrically connected to the signal vias  14   a  and is connected to the thermal structures  15   a . The signal vias  14   a  are electrically connecting the passive element  13   a  and the semiconductor die  11   a . In some embodiments, the passive element  13   a  is electrically connected to the semiconductor die  11   a  by the signal path including the signal vias  14   a  and the first circuit layer  121   a  of the wiring structure  12   a . The signal path may further include the second circuit layer  122   a  and the conductive via  125   a  electrically connected to the external device. The thermal structures  15   a  are connected to the passive element  13   a , and the thermal structures  15   a  are disposed on a periphery of the at least one wiring structure  12   a . In some embodiments, the thermal structures  15   a  may include a second thermal layer  158  to transmit the most heat from the passive element  13   a  to outside. 
     In some embodiments, the semiconductor package structure  1   d  may further include a dielectric layer  16  surrounding the semiconductor die  11   a . That is, the semiconductor die  11   a  is embedded in the dielectric layer  16 . The material of the dielectric layer  16  may be a prepreg. In some embodiments, the semiconductor package structure  1   d  may further include a protection layer  19   a  disposed on the dielectric layer  16 . The dielectric layer  16  may be an isolation material. The thermal structures  15   a  include a plurality of thermal vias. The thermal vias penetrate through the dielectric layer  16 . 
     In some embodiments, an amount of the thermal structures  15   a  may be larger than ten times an amount of the signal vias  14   a . In some embodiments, the amount of the thermal structures  15   a  may be larger than sixteen times the amount of the signal vias  14   a.    
       FIG. 6  illustrates a cross-sectional view of an example of a semiconductor package structure  1   e  according to some embodiments of the present disclosure. The semiconductor package structure  1   e  shown in  FIG. 6  is similar to the semiconductor package structure  1   d  shown in  FIG. 5 , and the differences are described as follows. In some embodiments, the semiconductor package structure  1   e  may further include an encapsulant  17  (e.g., molding compound) surrounding the semiconductor die  11   a . That is, the semiconductor die  11   a  is embedded in the encapsulant  17 . The encapsulant  17  may be an isolation material. The thermal structures  15   a  include a plurality of thermal vias. The thermal vias penetrate through the encapsulant  17 . 
       FIG. 7  illustrates a cross-sectional view of an example of a semiconductor package structure if according to some embodiments of the present disclosure. The semiconductor package structure if includes a semiconductor die  11   b , at least one wiring structure  12   b , a passive element  13   a , a plurality of signal vias  14   b , and a plurality of thermal structures  15   b . The semiconductor die  11   b  has an active surface  111   b . The at least one wiring structure  12   b  is electrically connected to the active surface  111   b  of the semiconductor die  11   b . Thus, the active surface  111   b  faces the wiring structure  12   b . The passive element  13   a  is electrically connected to the semiconductor die  11   b . The passive element  13   a  includes two electrodes  131   a ,  132   a  electrically connected to the signal vias  14   b  and the thermal structures  15   b . In some embodiments, the passive element  13   a  is electrically connected to the semiconductor die  11   b  by the signal path including the signal vias  14   b  and the wiring structure  12   b . The signal vias  14   b  are electrically connecting the passive element  13   a  and the semiconductor die  11   b . The thermal structures  15   b  are connected to the passive element  13   a , and the thermal structures  15   b  are disposed on a periphery of the at least one wiring structure  12   b.    
     In some embodiments, the semiconductor package structure if may further include at least one antenna structure  21  electrically connected to the semiconductor die  11   b . In some embodiments, the semiconductor package structure if may further include a plurality of conductive elements  22  (e.g., solder balls) electrically connecting the at least one wiring structure  12   b  and connecting the thermal structures  15   b.    
     In some embodiments, an amount of the thermal structures  15   b  may be larger than ten times an amount of the signal vias  14   b . In some embodiments, the amount of the thermal structures  15   b  may be larger than sixteen times the amount of the signal vias  14   b.    
       FIG. 8  illustrates a cross-sectional view of an example of a semiconductor package structure  1   g  according to some embodiments of the present disclosure. The semiconductor package structure  1   g  includes a semiconductor die  11   c , at least one wiring structure  12   c , a passive element  13   a , a plurality of signal vias  14   c , and a plurality of thermal structures  15   c . The semiconductor die  11   c  has an active surface  111   c . The at least one wiring structure  12   c  is electrically connected to the active surface  111   c  of the semiconductor die  11   c . Thus, the active surface  111   c  faces the wiring structure  12   c . The passive element  13   a  is electrically connected to the semiconductor die  11   c . The signal vias  14   c  are electrically connecting the passive element  13   a  and the semiconductor die  11   c . The thermal structures  15   c  are connected to the passive element  13   a , and the thermal structures  15   c  are disposed on a periphery of the at least one wiring structure  12   c.    
     In some embodiments, the semiconductor package structure  1   g  may further include an encapsulant  17   a  (e.g., molding compound) surrounding the semiconductor die  11   c . In some embodiments, the semiconductor package structure  1   g  may further include a plurality of conductive elements  23  (e.g., solder balls) electrically connecting the passive element  13   a  and the at least one wiring structure  12   c . In some embodiments, conductive elements  23  may be a portion of the thermal structures  15   c . Thus, the thermal structures  15   c  penetrate through the encapsulant  17   a.    
     In some embodiments, an amount of the thermal structures  15   c  may be larger than ten times an amount of the signal vias  14   c . In some embodiments, the amount of the thermal structures  15   c  may be larger than sixteen times the amount of the signal vias  14   c.    
       FIG. 9  illustrates a cross-sectional view of an example of a semiconductor package structure  1   h  according to some embodiments of the present disclosure. The semiconductor package structure  1   h  shown in  FIG. 1  is similar to the semiconductor package structure  1  shown in  FIG. 1 , and the differences are described as follows. In some embodiments, the semiconductor package structure  1   h  further includes a plurality of first recess portions  184  are formed between the signal pins  182  and the thermal pins  183 , so that the signal pins  182  and the thermal pins  183  are isolated from each other. In some embodiments, the semiconductor package structure  1   h  further includes a plurality of second recess portions  185  are formed between the signal pins  182  and the die pad  181 , so that the signal pins  182  and the die pad  181  are isolated from each other. 
       FIGS. 10 to 11  illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure. In some embodiments, the semiconductor manufacturing process is for manufacturing a semiconductor package structure such as the semiconductor package structure  1   h  shown in  FIG. 9 . 
     Referring to  FIG. 10 , a semiconductor package  10  is provided. The semiconductor package  10  includes a semiconductor die  11 , at least one wiring structure  12 , a plurality of signal vias  14  and a plurality of thermal structures  15 . The semiconductor die  11  includes an active surface  111  and a back surface  112 . The at least one wiring structure  12  is electrically connected to the active surface  111  of the semiconductor die  11 . The signal vias  14  are electrically connected to the semiconductor die  11 . The thermal structures  15  are disposed on a periphery of the at least one wiring structure  12 . 
     In some embodiments, the at least one wiring structure  12  includes a first circuit layer  121  and a second circuit layer  122 . The first circuit layer  121  is electrically connected to the passive element  13 , and the second circuit layer  122  is electrically connected to the signal vias  14 . The wiring structure  12  may include a first dielectric layer  123  and a second dielectric layer  124 . The first circuit layer  121  may include a seed layer and a conductive layer. A material of the seed layer may be, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. A material of the conductive layer may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer may be omitted. The first circuit layer  121  may include the signal vias  14  disposed in the through hole of the first dielectric layer  123 , and at least one conductive pad. That is, the signal vias  14  may be a portion of the first circuit layer  121  and a portion of the wiring structure  12 . In some embodiments, the first circuit layer  121  may further include at least one trace. 
     In some embodiments, the first dielectric layer  123  covers the second circuit layer  122 , and the first dielectric layer  123  surrounds the first circuit layer  121  and the signal vias  14 . The first dielectric layer  123  may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the first dielectric layer  123  may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The first dielectric layer  122  defines at least one through hole extending through the first dielectric layer  122 . 
     In some embodiments, the second circuit layer  122  is disposed on the second dielectric layer  124 , and the second circuit layer  122  is electrically connected to the first circuit layer  121  by the signal vias  14 . The second circuit layer  122  may include a seed layer and a conductive layer. A material of the seed layer may be, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. A material of the conductive layer may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer may be omitted. The second circuit layer  122  may include at least one conductive via  125  disposed in the through hole of the second dielectric layer  124 , and at least one conductive pad. In some embodiments, the second circuit layer  122  may further include at least one trace. 
     In some embodiments, the second dielectric layer  124  surrounds the semiconductor die  11 , the conductive via  125  and the metal support  18 . The second dielectric layer  124  may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the second dielectric layer  124  may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. 
     In some embodiments, the thermal structures  15  are thermal vias. The thermal structures  15  may include a plurality of first thermal vias  151 , a plurality of second thermal vias  152  and a plurality of first thermal pads  153 . The first thermal vias  151  are connected to the first circuit layer  121 . The first thermal pads  153  are disposed between the first thermal vias  151  and the second thermal vias  152 , and are connected to the first thermal vias  151  and the second thermal vias  152 . In some embodiments, the first thermal pads  153  and the second thermal vias  152  are formed at the same time as the second circuit layer  122  and the at least one conductive via  125 . The second dielectric layer  124  surrounds the second thermal vias  152 , and the first thermal pads  153  is disposed on the second dielectric layer  124 . 
     In some embodiments, an amount of the thermal structures  15  may be larger than ten times an amount of the signal vias  14 . That is, the amount of the first thermal vias  151  may be larger than ten times the amount of the signal vias  14 , or the amount of the second thermal vias  152  may be larger than ten times the amount of the signal vias  14 . In some embodiments, the amount of the thermal structures  15  may be larger than sixteen times the amount of the signal vias  14 . That is, the amount of the first thermal vias  151  may be larger than sixteen times the amount of the signal vias  14 , or the amount of the second thermal vias  152  may be larger than sixteen times the amount of the signal vias  14 . 
     In some embodiments, the metal support  18  includes a die pad  181 , a plurality of signal pins  182 , and a plurality of thermal pins  183 . The semiconductor die  11  is mounted on the die pad  181  of the metal support  18 . The back surface  112  of the semiconductor die  11  is disposed on the die pad  181  of the metal support  18 . The signal pins  182  are electrically connected to the signal vias  14 . The thermal pins  183  are connected to the thermal structures  15 . In some embodiments, the thermal pins  183  are connected to the second thermal vias  152  of the thermal structures  15 . In some embodiments, the die pad  181  is connected to the signal pins  182 , and the signal pins  182  are connected to the thermal pins  183 . 
     In some embodiments, the semiconductor package structure  1  may further include a protection layer  19  disposed on the first dielectric layer  123 . The protection layer  19  may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators, or a solder resist layer. 
     Referring to  FIG. 11 , a plurality of first recess portions  184  and a plurality of second recess portions  185  are formed by etching. The first recess portions  184  are formed to expose portion of the second dielectric layer  124 , and the first recess portions  184  are formed between the signal pins  182  and the thermal pins  183 . The second recess portions  185  are formed to expose portion of the second dielectric layer  124 , and the second recess portions  185  are formed between the signal pins  182  and the die pad  181 . Therefore, the signal pins  182  and the thermal pins  183  are isolated from each other, and the signal pins  182  and the die pad  181  are isolated from each other. 
     Then, the passive element  13  is mounted on the semiconductor package  10  to form the semiconductor package structure  1   h  as shown in  FIG. 9 . The passive element  13  is electrically connected to the signal vias  14  and is connected to the thermal structures  15 . In some embodiments, the passive element  13  includes two electrodes  131 ,  132  electrically connected to the signal vias  14  and connected to the thermal structures  15 . The two electrodes  131 ,  132  are formed as an L shape. In some embodiments, the two electrodes  131 ,  132  of the passive element  13  are disposed on the first circuit layer  121 , and are electrically connected to the first circuit layer  121 . The first circuit layer  121  is electrically connected to the signal vias  14  and is connected to the thermal structures  15 . 
       FIG. 12  illustrates a top view of an example of a semiconductor package structure  1  from the second circuit layer  122  according to some embodiments of the present disclosure. That is,  FIG. 12  is a top view of an example of a semiconductor package structure  1  removing the passive element  13  ( FIG. 1 ), the protection layer  19  ( FIG. 1 ), the first dielectric layer  123  ( FIG. 1 ) and the first circuit layer  121  ( FIG. 1 ). In some embodiments, an amount of the second thermal vias  152  may be larger than ten times an amount of the signal vias  14  ( FIG. 1 ). In some embodiments, the amount of the second thermal vias  152  may be larger than sixteen times the amount of the signal vias  14  ( FIG. 1 ). Therefore, the most heat from the passive element  13  ( FIG. 1 ) is transmitted to the thermal structures  15  ( FIG. 1 ) rather than to the semiconductor die  11 . The junction temperature of the semiconductor die  11  may be less than about 150° C. The semiconductor package structure  1  ( FIG. 1 ) of the present disclosure can meet the design specifications. 
     Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement. 
     As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. 
     Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. 
     Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. 
     While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.