Patent Publication Number: US-7221135-B2

Title: Method for regulating the time constant matching in DC/DC converters

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method for regulating the time constant matching, for example, in DC/DC converters. 
   The invention particularly, but not exclusively, relates to a method to be used in DC/DC converters, for example in voltage regulator module (VRM) applications, and the following description is made with reference to this field of application for convenience of illustration only. 
   The invention further relates to a corresponding regulation device for regulating and controlling the time constant matching in DC/DC converters. 
   2. Description of the Related Art 
   As it is well known, the evolution of the electric characteristics of processors for PCs, WORKSTATIONS and SERVERS obliges manufacturers to search for new solutions meeting the CPU requirements that include: high precision in the supply voltage, for instance +/−0.8% under steady state conditions and +/−3% under transient conditions. 
   In order to ensure an accurate supply, which respects more and more restrictive specifications, it is desirable to precisely know the value of the current flowing in the coils of the DC/DC converter used as power supply unit. 
   In order to ensure such a precision degree, designers are induced to use a current estimate method exploiting the parasitic resistance of each coil of the DC/DC converter. 
   The use of this method however introduces a drawback due to the real value offset of the components employed by the respective nominal value, jeopardizing the reading precision and thus the current estimate. 
   By analyzing the DC/DC converter it is observed that the parasitic resistance of each coil is not directly accessible and this so as to be able to draw the current information it is necessary to use an added electric network or reading network, placed in parallel to the coil and formed by a resistance R D  and by a capacitance C D , as for example shown in  FIG. 1 . 
   By now analyzing the transfer function, reported in the formula (1.1), between the voltage V sense  developing across the capacitance C D  and the current I L  flowing in the coil, the presence of a term can be noted which depends on the frequency and which is also called doublet. 
   A variation of the doublet can alter the read current information. More precisely, an overestimate of the current which flows in the coil is performed, if the time constant of the reading network, C D  R D  is lower than the time constant L/R L  also called coil network. Whereas, in the opposite case there is a under-estimation of the read current. 
   
     
       
         
           
             
               
                 
                   
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                 ( 
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   In order to have a correct current estimate it is thus necessary that the time constants of the reading network and coil network are equal, such correlation is also called “time constant matching.” This condition does not normally occur due to the variation from the nominal value of the values of the components used as above hinted at, which negatively influences the time constant matching. 
   Let&#39;s remember that the components can depart from their nominal value due to a statistic variability, from a dependence on the temperature or simply from an ageing thereof. 
   Through tests carried out by the Applicant it has been observed how the use of standard components leads to differences between the two time constants which can also reach ±30%. 
   Thus, against a variation of the current required by the load, such difference can cause, on the DC/DC converter regulated output voltage, overelongations or subelongations which can jeopardize the tolerance band imposed by the specifications. 
   The effect of the overelongations and of the subelongations on the output voltage with respect to a constant ideal value is shown in  FIG. 2  and it is due to a wrong Time Constant Matching. 
   As far as it is known, no specific solutions exist in the literature for correcting a wrong time constant matching. 
   A possible solution for trying to solve and/or to limit the entity of the overelongations and subelongations effects, is the use of particularly precise components, both in the coil network and in the reading network, and an oversized output capacitance. 
   Such solution however implies extremely high component costs linked to the precision required and, moreover, the use of such components also implies high costs in terms of area occupied on the motherboard. 
   Let&#39;s now analytically analyze an equation for the calculation of the tolerance band (TOB) i.e. of a DC/DC converter tolerance band with reference to the output voltage. 
                   TOB   manuf     =                 (         VID   ·     k   VID       ︸     reference     )     2     +       V   AVP   2     ·     (             k   gm   2     ︸     Current     Sense     +           k   ESR   2       n   ph       sense     element       )         ︸     STATIC     +           V   AVPdyn   2     ·           (         k   L   2     +     k   C   2         n   ph       )     ︸     TimeConstant     Matching       ︸     DYNAMIC                 (   1.2   )               ±TOB=TOB manuf   +V   ripple   +V   TC   (1.3) 
   In particular, the equation (1.3) defines the calculation for the determination of the tolerance band, which however needs the value of the TOB manuf  defined by the equation (1.2). 
   As it can be observed, the equation (1.2) shows the dependence of the tolerance band on some characteristic parameters dependant on the typology of the used reading or sensing network. By introducing such parameters it is possible to understand which weight the single blocks, which compose a DC/DC converter, have in the global calculation of the TOB. 
   The equation (1.2) collects the static and dynamic variations relative to the DC/DC converter and, for obtaining the total contribution, they are quadratically summed. 
   The contribution of the time constant matching in the equation (1.2) is given by the third addend, wherein the terms K L  and K C  appear which are respectively the coil statistic variation and the capacitance C D  one. Whereas, the term n ph  indicates the number of the phases of each DC/DC converter and the term V AVPdyn  indicates the variation of the output voltage against a variation of the required current I dyn . 
   The terms V ripple  and V TC , reported in the equation (1.3), indicate the deterministic variations of the output voltage. 
   Let&#39;s now analyze the equation (1.4) which allows to highlight a residual difference between the two time constants equal to 4%. 
   
     
       
         
           
             
               
                 
                   
                     
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   As it can be observed, with current and known DC/DC converters a residual difference between the two time constants equal to 4% can be reached by using an eight-phase system so as to allow a greater mediation of the unbalance of each phase. 
   However, systems with such a high number of phases are out of the normal trend for DC/DC converters, which require reduced costs and minimal uses of areas in the motherboard. 
   Moreover, it is good to consider that the above indicated result of the equation (1.4) solution has been obtained by using particularly precise components and, in a particular way, as regards the output capacitance, a capacitor with COG dielectric has been used, which has a great precision, a lower dependence on the temperature and a lower aging effect with respect to the normal capacitors. However, such types of COG capacitors have a more than double cost with respect to the common capacitors. 
   BRIEF SUMMARY OF THE INVENTION 
   A first embodiment of the present invention provides a method for regulating the time constant matching in such a manner to equalize the time constant of the reading network with that of the coil network in a simple and quick way, with a lower dependence on the temperature and the aging of the components and which allows the use of common components and having such functional characteristics as to allow to overcome the limits still affecting the methods according to the prior art. 
   A further embodiment of the present invention is a controller device which allows to regulate the time constant matching of a DC/DC converter by employing low cost components and by occupying a reduced area on the motherboard which allows to make the device extremely compact and economic, overcoming the limits and the drawbacks of the solutions proposed by the known technique. 
   One embodiment of the present invention realizes a regulation method of the adaptive type on the time constant matching of each DC/DC converter phase allowing to analyze the phase response to a load variation by regulating in a corresponding way a resistance R D , of the variable type, progressively reaching the optimal condition wherein the time constant of the reading network is equal to the time constant of the coil network. 
   One embodiment of the invention relates to a method for regulating the time constant matching of a DC/DC converter phase following a variation of a load applied to an output of the phase, the phase being associated with a coil network having an LR circuit connected in series and being connected to a reading network having an RC circuit connected in parallel to the coil network. The method includes:
         an acquisition step that acquires a trend of a voltage V sense  detected across a capacitance of said RC circuit and for transforming the voltage trend into a current trend I sense ;   a detection step that identifies a variation over a threshold value in the trend of the current I sense  obtained from the acquisition step in response to a variation of the load;   an identification step, enabled by the detection step, for determining a slope of the current I sense  trend;   a regulation step that adapts the resistance value of the RC circuit according to the value of the slope determined by the identification step.       

   A further embodiment of the invention relates to a device for regulating the time constant matching of a DC/DC converter phase following a variation of a load applied to an output of the phase, the phase being associated to a coil network having an LR circuit connected in series and being connected to a reading network having an RC circuit connected in parallel to the coil network. The device includes:
         a reading circuit having a V/I switch suitable to switch the trend of a voltage V sense  detected across the capacitance of the RC circuit to obtain a corresponding current I sense  trend;   a load variation sensor structured to identify a variation over a threshold value in the trend of the current I sense  obtained from the reading circuit in response to a variation of the load;   a mismatch sensor enabled by the variation sensor structured to determine a slope of the current I sense  trend;   an up-down counter structured to regulate the resistance value of the RC circuit according to the slope determined by the mismatch sensor.       

   The features and advantages of the method and device according to the present invention will be apparent from the following detailed description given by way of non-limiting example with reference to the following drawings. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     In such drawings: 
       FIG. 1  shows a portion of a DC/DC converter represented according to the prior art; 
       FIG. 2  graphically shows the output voltage of  FIG. 1  with possible subelongations or overelongations 
       FIG. 3  is a block scheme of the method according to one embodiment of the present invention; 
       FIGS. 4 and 5  are respectively a graphic representation of a load current variation and a respective time constant variation in a under-estimation, i.e. when the time constant of the reading circuit is greater than that of the coil circuit; 
       FIGS. 6 and 7  are respectively a graphic representation of a load current variation and a respective variation of the time constant in an over-estimation, i.e. when the time constant of the reading circuit is lower than that of the coil circuit; 
       FIGS. 8 and 9  are time/amplitude representations of the Isense current in response to a load variation, respectively an increase or a decrease; 
       FIG. 10  is a representation of a part of the device realized in according to one embodiment of the present invention; 
       FIG. 11  is a schematic representation of a method step realized according to one embodiment of the present invention; 
       FIG. 12  shows a trend of the Isense current; 
       FIG. 13  shows the Isense current of  FIG. 12  filtered by means of a low-pass filter; 
       FIG. 14  shows the Isense current trend before a further load variation; 
       FIG. 15  shows a part of the device according to one embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   A regulation method, according to one embodiment of the present invention, is schematically shown by means of a block scheme reported in  FIG. 3  and applied to a DC/DC converter phase  50 . 
   The DC/DC converter phase  50  is associated, in a usual way, with a coil network  51  comprising a series LR circuit with an inductance L and a parasitic resistance R L . 
   The DC/DC converter phase  50  also provides a reading network  10  comprising an RC circuit with a capacitance C D  in series with a variable resistance R D , placed in parallel to the coil network  51 . 
   Advantageously, the capacitance C D  and the resistance R D  are controlled and regulated by a device which, in the block scheme, is indicated with number  1 . 
   The device  1 , allows to regulate, further to a variation of the load applied to the DC/DC converter, the time constant matching of the phase  50 . 
   Advantageously, the regulation method according to one embodiment of the present invention is of the adaptive type, i.e. it allows to regulate a time constant τ D  of the reading network  10 , of the phase  50 , adapting it to a variation of the time constant T L  of the coil network  51  due to the effective load variation, thus optimizing the time constant matching. 
   Obviously, the regulation method and the device  1  realization of the method should be applied to each DC/DC converter phase  50 . 
   In order to define the situation wherein a DC/DC converter phase  50  is, the trend of its output voltage V OUT  or, similarly, the trend of the voltage V sense  detected across the capacitance C D  of the reading network  10  can be observed. 
   Generally, at the output of the DC/DC converter a capacitance is placed, called output capacitance C OUT , as highlighted in  FIG. 15 , and interposed between the output voltage V OUT  of the phase  50  and a ground reference voltage. 
   Against a variation of the load applied to the DC/DC converter, also called load transient, a distinctive element which allows to establish the time constant matching, is advantageously an analysis of the slope with which the trend of the output voltage V OUT  or of the voltage V sense  lies down on a new speed value due to the load variation. 
   Thus, for example,  FIGS. 4 and 6  highlight possible trends of the output voltage V OUT  whereas  FIGS. 5 and 7  indicate the trends of the corresponding voltage V sense . 
   The arrows reported in such figures indicate the curve slopes in a section wherein the response to the load variation is, by now, denominated by the time constant L/R L  of the coil network  51 . 
   Entering into details, it is observed that if the time constant τ D =C D ·R D  of the reading network  10  is greater than the time constant τ L =L/R L  of the coil network  51 , the real value of the current flowing in the inductance L is being under-estimated. This means that the DC/DC converter phase  50  supplies more current than that required by the load, such current thus allows to load the output capacitance C OUT  determining an overelongation on the output voltage V OUT  as indicated in  FIG. 4  or similarly a positive slope in the voltage V sense  as indicated in  FIG. 5 . 
   In the opposite case, wherein τ D  is lower than T L , the correct value of the current flowing in the inductance L is overestimated. The inductance thus supplies a minor current with respect to that required by the load and this determines, against the output capacitance C OUT , a subelongation of the output voltage V OUT , as indicated in  FIG. 6  or similarly a negative slope of the voltage V sense , as indicated in  FIG. 7 . 
   This explains the need of providing, for each single DC/DC converter phase  50 , a time constant matching. 
   Advantageously, therefore, the adaptive regulation method provides an acquisition step wherein a reading circuit  15  acquires information in voltage V sense  which develops across the capacitance C D  and it transforms it into a current I sense  trend, as indicated in  FIG. 3 . 
   Obviously, the acquisition step can be realized in several ways for example by means of a switch V/I suitable to switch the trend of a voltage V sense , detected across said capacitance C D , in a current I sense  trend. 
   Suitably, the adaptive method further provides an identification step wherein the slope is determined with which the current I sense  varies, further to a load variation or load transient. 
   Advantageously, the identification step provides the determination of the slope on the basis of a current I sense  integration. 
   The use of the integration operation allows to obtain an optimal immunity to noises. In fact, possible spikes or noises overlapped to the current I sense  or useful signal undergo a dampening due exactly to the integration operation of the same. 
   In the case of the proposed solution, the integration operation and thus the identification of the current I sense  trend slope uses the principle according to which, in a time/amplitude configuration, the slope can be determined by means of a difference of areas subtended by the current I sense  trend in two equal and adjacent time sections T′ and T″. 
   Such areas, as highlighted in particular in  FIGS. 8 and 9 , are indicated with A 1  and A 2  and being the sampling times defined as T 0 , T 1  and T 2 , it follows that T′=(T 1 −T 0 ) and T″=(T 2 −T 1 ). The sign taken by such difference indicates the current I sense  slope which is particularly positive if A 1  is lower than A 2 , as indicated in  FIG. 8 , and negative in the opposite case, shown in  FIG. 9 . Whereas, in the case wherein the time constant matching is respected, the difference between areas A 1  and A 2  is equal to zero. 
   A possible realisation of the identification step can occur, as indicated in  FIG. 3 , by means of a mismatch sensor  18  obtained according to the embodiment indicated in  FIG. 10 . 
   The mismatch sensor  18  comprises two switches, such as for example two MOS transistors T 1  and T 2 , respectively connected between the input and a ground voltage reference (GND) by means of the interposition of two capacitances C 1  and C 2  in correspondence with two nodes A and B. 
   The mismatch sensor  18  also comprises a window comparator  19  which has two inputs connected to the nodes A and B, to detect the voltages developing across the capacitances C 1  and C 2  loaded by means of the switches T 1  and T 2  with the current or a current I sense  or a difference current (I sense −I 0 ) where I 0  is a constant current value as it will be better specified hereafter. 
   The window comparator  19  can be for example realized by means of a pair of comparators  19 A and  19 B both of them being input, in an inverted way the voltages present at the nodes A and B and they have an output respectively UP and DOWN. 
   Obviously, the voltages developing across the capacities C 1  and C 2  are proportional to the areas A 1  and A 2 , thus, the determination of their difference defines the current I sense  slope, positive or negative. 
   In particular, the outputs UP and DOWN of the pair of comparators  19 A and  19 B will activate themselves in an alternated way according to the slope being positive or negative. 
   Advantageously, during such identification step it is suitable to perform a minimization step by removing from the current I sense  a denominated constant component I 0 , i.e. the current sampled at the time T 0 . By removing, for each instant comprised between T 0  and T 2 , the constant component I 0 , as far as the area is concerned it is as if the light grey part indicated in the  FIGS. 8 and 9  were eliminated. 
   The difference current (I sense −I 0 ) still has all the information and the characteristics of the current I sense  it reduces the value of the current at the input of the mismatch sensor  18  and, moreover, the possible dynamic problems during the device designing step are reduced. 
   The current I sense  minimisation step can be realised in several ways, for example as highlighted in  FIG. 11 , a sampling of the current value I sense  can be provided an instant before the start of the integration operation, defining a constant component I 0 , a copy thereof is made and it is taken away from instantaneous value of the current I sense  the moment when the capacitances C 1  and C 2  are loaded. 
   As it can be analyzed from  FIG. 12 , the amplitude order of the current I sense  slope, originated by a wrong time constant matching is highlighted by the difference between the ordinates of two points indicated with the arrows and it is lower than 1 μA. 
   Such slope value, as it is known, is much lower than the value of a possible ripple in the current I sense . 
   Thus, if the integration operation is performed with a current I sense  signal comprising a possible ripple, besides a quick device saturation, the effective information would be masked. 
   Advantageously, the method provides, further to the detection step a filtering step of the current I sense  to reduce the possible ripple contribution. 
   It is good to note how the time constants which govern the time constant matching are in the order of some hundreds of hertz while the ripple typically has a frequency of some hundreds of kilohertz kilogram. 
   Advantageously, the filtering step will thus have to occur at low frequency by using a low-pass filter which, from the current I sense , allows to eliminate a good part of the ripple. Such low-pass filter can be for example placed in the reading circuit  15  indicated in  FIG. 3 . 
   The effect of the filtering step on the signal I sense  before ripple does not change the global current trend as highlighted in  FIG. 13  and this allows to reach the sensitivity degree required by the method still maintaining all the information of the time constant matching. 
   For acquiring the information of the time constant matching after a load variation or load transient it is necessary to determine, in each DC/DC converter phase  50 , a latency T. 
   In fact, being the information relative to the Time Constant Matching linked to the final part of the time constant of the coil network  51  τ L =L/R L , which, on the other hand, is the greatest time constant between those of the closed-loop system, it is necessary to wait until all the other time constants fade away. 
   The latency T is generally equal to a fraction equal to ⅘ of the greatest time constant after the value of τ L , of the closed-loop system. In the shown example, the latency T is fixed at 300 μs. 
   Advantageously, the latency T allows to time all the various method steps. 
   A necessary condition to perform a correct measure of the current I sense  trend slope is that no further load variations have to occur during a whole duration D of the detection step. 
   Such duration D is generally determined by the sensor structure and it is comprised between 0&lt;D&lt;4*τ L . 
   In the described embodiment the duration D is fixed at (66+66)μs, thus the latency T more the duration D is equal to (300+122)=422 μs. 
   An example of the I sense  current offset trend further to a load variation is shown in  FIG. 14 , where one can observe how the load variation leads to a wrong interpretation of the trend as indicated in the corresponding graph of  FIG. 14   a  and thus of a wrong time constant matching evaluation. 
   The detection step can be realized in several ways for example by means of a load variation sensor  16  and a protection circuit  17 . 
   The role played by the load variation sensor  16  is of fundamental importance in order not to make errors in the evaluation of the Time Constant Matching condition. For this reason the architecture chosen for the sensor  16  is based, once more, on the integration method. 
   The sensor  16  is connected to the reading circuit  15  and it receives therefrom the current I sense  or a difference current (I sense −I 0 ) by means of the interposition of the protection circuit  17  which comprises one or more comparators, not highlighted in the figures and of a known type, which allow, during the detection step, to highlight the presence of a further variation of the load itself. 
   The sensor  16  must be able to discriminate the different load variations, which occur during the detection step, in relation to the status wherein the recognition step occurs. 
   In fact, the load variations can generate a more or less marked error of the time constant matching according to the load variation amplitude. 
   This means that the subelongation or overelongation on the voltage output V OUT  of a DC/DC converter phase  50  is less evident during small load variations. 
   In this regard, the sensor  16  is calibrated for being able to detect load variations above a certain threshold value S r  which is set directly during the design step and it depends on the resolution of the acquisition system, more in general it can be comprised between I MAX /2 and I MAX , where I MAX  indicates the maximum current the converter DC/DC can supply. In the shown example, the threshold value S r  has been set at 40 A. 
   Once the detection step has been started, the protection circuit  17  comparators are enabled. Such comparators have in turn a threshold S r  which is however lower with respect to the threshold value S r  of the sensor  16 , thus allowing the recognition of much smaller load variations. 
   The number of comparators used in the protection circuit  17  influences the precision degree required by the device  1  and obviously each threshold S r  of each comparator. 
   The comparison step, by means of the sensor  16  and of the protection circuit  17 , enables the identification step and thus the mismatch sensor  18 , but it allows also to interrupt such comparison step by disabling the identification step before a load variation which would damage the slope detection of current I sense  or of a difference current. 
   Obviously, the identification step of the method generates, according to the detected slope, an output UP or DOWN. 
   Advantageously, the method provides a regulation step suitable to be input the output of the identification step regulating, in a corresponding way, the variable resistance R D  of the reading network  10 . 
   The regulation step can be realized in several ways, for example as highlighted in  FIG. 15 , by means of an up-down counter  23  which, supplied by the output UP or DOWN of the mismatch sensor  18 , allows to regulate the resistance R D  according to the current I sense  slope detected by the mismatch sensor  18 . 
   The resistance R D  is of the variable type, which can be obtained in several ways. A possible embodiment provides the use of a structure  25  made of a series of N resistances  20 , wherein the values range from R to R N , and N suitable switches  21  placed in parallel to each one of the N resistances  20 . 
   In such way, the counter up-down  23  on the basis of the signal received from the mismatch sensor  18  opens or closes the N switches  21  suitably regulating, increasing or decreasing the value of the resistance R D  in series to the capacitance C D , so as to obtain a correct time constant matching value. 
   The number of the N resistances  20  used in the structure  25  determines the precision degree with which the time constant τ D  of the reading network  10  can be regulated. 
   In the case shown in  FIG. 15 , by way of example, the counter UP-DOWN is of the 5 bit type and thus the switches  21  are five. 
   Obviously the present invention can undergo several modifications all within the same scope of protection. 
   In particular, a recognition step and/or a detection step can be provided, realized by means of a digital approach whereas the regulation step could be performed by means of a continuous solution, without however invalidating the goodness of the regulation method as described. 
   A main advantage of the regulation method is that of allowing a simple regulation of the resistance R D  of the reading network  10  by adapting it to the detected slope of the current I sense  trend or of a difference current (I sense −I 0 ) proportional thereto allowing to reach an exact at the time constant matching in a quick way. 
   A remarkable further advantage of the method is that of estimating the real current value flowing in the inductance L of the coil network  51  and of supplying the exact current required by the load variation thus avoiding the formation of overelongations or subelongations in the output voltage. 
   Another advantage of the present method is given by the integration operations required during the acquisition step and during the identification step, which allow to make the method particularly exempt form the presence of possible noises in the current I sense  or in a current proportional thereto. 
   Another advantage is that the proposed method allows to use, for the realization of the various steps it is made of, non particularly precise common components, thus making the method little expensive and suitable to be applied on a large scale to each DC/DC converter. 
   A further advantage is represented by the fact that the proposed method can be realized with a minimal employment of occupied area in the motherboard with a remarkable saving on the global cost. 
   Further, the proposed method allows to realize DC/DC converters which have such specifications as to remain within the currently required restrictive characteristics. 
   A further advantage of the proposed method lies in that, through tests carried out by the Applicant, it has been observed how the 4% parameter required for the above reported equation (1.4) resolution can be normally obtained without the demand for particular and expensive components. 
   From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.