Patent Publication Number: US-2015089113-A1

Title: Expansion card having two switchable connectors

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to expansion cards, and particularly to an expansion card able to selectively activate a peripheral component interface express (PCIe) connector or a non-PCIe connector. 
     2. Description of Related Art 
     Main boards of computers have at least one PCIe slot for connecting with an expansion card, such as a graphics card or a network card. However, if the expansion card has a connector not matching the PCIe slot, the expansion card needs to be connected to the main board through an adapter card, which is inconvenient and inefficient. Furthermore, if a suitable slot is mounted on the main board for connecting a non-PCIe connector of the expansion card, the expansion card only having the non-PCIe connector can not be connected to the PCIe slot. 
     Therefore, it is desirable to provide an expansion card that can overcome the limitations described. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a functional block diagram of an embodiment of an expansion card. 
         FIGS. 2-6  are circuit diagrams of the expansion card of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the disclosure will be described with reference to the drawings. 
     The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.” The references “a plurality of” and “a number of” mean “at least two.” 
       FIGS. 1-6  show an embodiment of an expansion card  100 . The expansion card  100  can be, but is not limited to, a graphics card or a network card. In one embodiment, the expansion card  100  includes a PCIe connector  10 , a non-PCIe connector  20 , a signal switching module  30 , and a signal processing module  40 . 
     The PCIe connector  10  is pluggable into a PCIe slot having a number of standard PCIe pins. The PCIe connector  10  includes a group of first receiving terminals  11  and a group of first transmitting terminals  12 . In one embodiment, the first receiving terminals  11  include sixteen pins A 16 , A 17 , A 21 , A 22 , A 25 , A 26 , A 29 , A 30 , A 35 , A 36 , A 39 , A 40 , A 43 , A 44 , A 47 , A 48 . The first transmitting terminals  12  include sixteen pins B 14 , B 15 , B 19 , B 20 , B 23 , B 24 , B 27 , B 28 , B 33 , B 34 , B 37 , B 38 , B 41 , B 42 , B 45 , B 46 . 
     The non-PCIe connector  20  is pluggable into a suitable slot, which is different from the PCIe slot. The non-PCIe connector  20  includes a group of second receiving terminals  21  and a group of second transmitting terminals  22 . In one embodiment, the second receiving terminals  21  include sixteen pins V 19 , V 21 , V 27 , V 29 , V 35 , V 37 , V 43 , V 45 , V 51 , V 53 , V 59 , V 61 , V 67 , V 69 , V 75 , V 77 . The second transmitting terminals  22  include sixteen pins V 14 , V 16 , V 22 , V 24 , V 30 , V 32 , V 38 , V 40 , V 46 , V 48 , V 54 , V 56 , V 62 , V 64 , V 70 , V 72 . 
     The signal switching module  30  includes a signal receiving unit  31 , a signal transmitting unit  32 , and a controlling unit  33 . The signal receiving unit  31  and the signal transmitting unit  32  are two same switching chips U 1 , U 2 . The signal receiving unit  31  is configured for selectively receiving signals from the PCIe connector  10  or the non-PCIe connector  20 . The signal transmitting unit  32  is configured for selectively transmitting signals to the non-PCIe connector  20 . 
     The signal receiving unit  31  includes a group of first inputting terminals  311 , a group of second inputting terminal  312 , and a group of first controlling terminals  313 . The first inputting terminals  311  include a group of first sub-inputting terminals  3111  and a group of second sub-inputting terminals  3112 . When the first controlling terminals  313  receive a low-level signal, such as 0 volts (V), the first sub-inputting terminals  3111  are connected to the second inputting terminals  312 , and the second sub-inputting terminals  3112  are disconnected from the second inputting terminals  312 . When the first controlling terminals  313  receive a high-level signal, such as +5 V, the second sub-inputting terminals  3112  are connected to the second inputting terminals  312 , and the first sub-inputting terminals  3111  are disconnected from the second inputting terminals  312 . In one embodiment, the first sub-inputting terminals  3111  include sixteen pins  1 B 1 ,  1 B 2 ,  1 B 3 ,  1 B 4 ,  1 B 5 ,  1 B 6 ,  1 B 7 ,  1 B 8 ,  1 B 9 ,  1 B 10 ,  1 B 11 ,  1 B 12 ,  1 B 13 ,  1 B 14 ,  1 B 15 ,  1 B 16 . The second sub-inputting terminals  3112  include sixteen pins  2 B 1 ,  2 B 2 ,  2 B 3 ,  2 B 4 ,  2 B 5 ,  2 B 6 ,  2 B 7 ,  2 B 8 ,  2 B 9 ,  2 B 10 ,  2 B 11 ,  2 B 12 ,  2 B 13 ,  2 B 14 ,  2 B 15 ,  2 B 16 . The second inputting terminals  312  include sixteen pins A 1 , A 2 , A 3 , A 4 , A 5 , A 6 , A 7 , A 8 , A 9 , A 10 , A 11 , A 12 , A 13 , A 14 , A 15 , A 16 . 
     The signal transmitting unit  32  includes a group of first outputting terminals  321 , a group of second outputting terminals  322 , and a group of second controlling terminals  323 . The first outputting terminals  321  include a group of first sub-outputting terminals  3211  and a group of second sub-outputting terminals  3212 . 
     When the second controlling terminals  323  receive a low-level signal, such as 0 V, the first sub-outputting terminals  3211  are connected to the second outputting terminals  322 , and the second sub-outputting terminals  3212  are disconnected from the second outputting terminals  322 . When the second controlling terminals  323  receive a high-level signal, such as +5 V, the second sub-outputting terminals  3212  are connected to the second outputting terminals  322 , and the first sub-outputting terminals  3211  are disconnected from the second outputting terminals  322 . In one embodiment, the first sub-outputting terminals  3211  include sixteen pins  1 B 1 ,  1 B 2 ,  1 B 3 ,  1 B 4 ,  1 B 5 ,  1 B 6 ,  1 B 7 ,  1 B 8 ,  1 B 9 ,  1 B 10 ,  1 B 11 ,  1 B 12 ,  1 B 13 ,  1 B 14 , IBIS,  1 B 16 . The second sub-outputting terminals  3212  include sixteen pins  2 B 1 ,  2 B 2 ,  2 B 3 ,  2 B 4 ,  2 B 5 ,  2 B 6 ,  2 B 7 ,  2 B 8 ,  2 B 9 ,  2 B 10 ,  2 B 11 ,  2 B 12 ,  2 B 13 ,  2 B 14 ,  2 B 15 ,  2 B 16 . The second outputting terminals  322  include sixteen pins A 1 , A 2 , A 3 , A 4 , A 5 , A 6 , A 7 , A 8 , A 9 , A 10 , A 11 , A 12 , A 13 , A 14 , A 15 , A 16 . 
     In one embodiment, the controlling unit  33  is a toggle switch, which is connected to the first controlling terminals  313  and the second controlling terminals  323 . The controlling unit  33  outputs either the low-level signal or the high-level signal to the first controlling terminals  313  and the second controlling terminals  323 . 
     The signal processing module  40  is connected to the second inputting terminals  312  and the second outputting terminals  322 . In one embodiment, the signal processing module  40  is a local area network circuit. 
     The first receiving terminals  11  of the PCIe connector  10  are connected to the second sub-inputting terminals  3112  of the signal receiving unit  31 . The second receiving terminals  21  of the non-PCIe connector  20  are connected to the first sub-inputting terminals  3111  of the signal receiving unit  31 . The first transmitting terminals  12  of the PCIe connector  10  are connected to the second sub-outputting terminals  3212  of the signal transmitting unit  32 . The second transmitting terminals  22  of the non-PCIe connector  20  are connected to the first sub-outputting terminals  3211  of the signal transmitting unit  32 . 
     In one embodiment, the pins A 16 , A 17 , A 21 , A 22 , A 25 , A 26 , A 29 , A 30 , A 35 , A 36 , A 39 , A 40 , A 43 , A 44 , A 47 , A 48  of the PCIe connector  10  are connected to the pins  2 B 1 ,  2 B 2 ,  2 B 3 ,  2 B 4 ,  2 B 5 ,  2 B 6 ,  2 B 7 ,  2 B 8 ,  2 B 9 ,  2 B 10 ,  2 B 11 ,  2 B 12 ,  2 B 13 ,  2 B 14 ,  2 B 15 ,  2 B 16  of the signal receiving unit  31 , respectively. The pins V 19 , V 21 , V 27 , V 29 , V 35 , V 37 , V 43 , V 45 , V 51 , V 53 , V 59 , V 61 , V 67 , V 69 , V 75 , V 77  of the non-PCIe connector  20  are connected to the pins  1 B 1 ,  1 B 2 ,  1 B 3 ,  1 B 4 ,  1 B 5 ,  1 B 6 ,  1 B 7 ,  1 B 8 ,  1 B 9 ,  1 B 10 ,  1 B 11 ,  1 B 12 ,  1 B 13 ,  1 B 14 ,  1 B 15 ,  1 B 16  of the signal receiving unit  31 , respectively. The pins B 14 , B 15 , B 19 , B 20 , B 23 , B 24 , B 27 , B 28 , B 33 , B 34 , B 37 , B 38 , B 41 , B 42 , B 45 , B 46  of the PCIe connector  10  are connected to the pins  2 B 1 ,  2 B 2 ,  2 B 3 ,  2 B 4 ,  2 B 5 ,  2 B 6 ,  2 B 7 ,  2 B 8 ,  2 B 9 ,  2 B 10 ,  2 B 11 ,  2 B 12 ,  2 B 13 ,  2 B 14 ,  2 B 15 ,  2 B 16  of the signal transmitting unit  32 , respectively. The pins V 14 , V 16 , V 22 , V 24 , V 30 , V 32 , V 38 , V 40 , V 46 , V 48 , V 54 , V 56 , V 62 , V 64 , V 70 , V 72  of the non-PCIe connector  20  are connected to the pins  1 B 1 ,  1 B 2 ,  1 B 3 ,  1 B 4 ,  1 B 5 ,  1 B 6 ,  1 B 7 ,  1 B 8 ,  1 B 9 ,  1 B 10 ,  1 B 11 ,  1 B 12 ,  1 B 13 ,  1 B 14 ,  1 B 15 ,  1 B 16  of the signal transmitting unit  32 , respectively. 
     In use, when the non-PCIe connector  20  of the expansion card  100  is plugged into a non-PCIe slot of a main board (not shown), the controlling unit  33  outputs the low-level signal, the first sub-inputting terminals  3111  are connected to the second inputting terminals  312 , and the first sub-outputting terminals  3211  are connected to the second outputting terminals  322 . Therefore, the non-PCIe connector  20  is connected to the signal processing module  40 . When the PCIe connector  10  of the expansion card  100  is plugged into a PCIe slot of the main board, the controlling unit  33  outputs a high-level signal, the second sub-inputting terminals  3112  are connected to the second inputting terminals  312 , and the second sub-outputting terminals  3212  are connected to the second outputting terminals  322 . Therefore, the PCIe connector  10  is connected to the signal processing module  40 . 
     Particular embodiments are shown and described by way of illustration only. The principles and the features of the present disclosure may be employed in various and numerous embodiments thereof without departing from the scope of the disclosure as claimed. The above-described embodiments illustrate the scope of the disclosure but do not restrict the scope of the disclosure.