Patent Publication Number: US-9431906-B2

Title: Voltage converter circuit and associated control method to improve transient performance

Description:
TECHNICAL FIELD 
     The present invention generally relates to power circuit, and more particularly but not exclusively relates to voltage converter circuit and associated control method. 
     BACKGROUND 
     Switch mode power supply is widely employed in modern electrical products. Traditional switch mode power supply may apply pulse width modulation (PWM) control method to regulate the output of the power supply, which usually involves in complicated structure and slow transient response. Therefore, its performance in high current applications is limited. 
     Compared with PWM control method, pulse frequency modulation (PFM) control method, which primarily comprises constant on-time control method, constant off-time control method and hysteresis control method, possesses advantages in transient response performance and circuit design.  FIG. 1  illustrates a prior art constant on-time converter circuit  10 . Constant on-time converter circuit  10  primarily comprises a direct current to direct current (DC-DC) buck converter  101 , and a controller  102 . In the controller  102 , an error signal VEAO is compared with a ramp signal VRAMP by a comparator  105 . Wherein, VEAO is generated by an operational transconductance amplifier  104  according to a difference between a reference signal VREF and an output voltage feedback signal VFB. When the ramp signal VRAMP falls lower than the error signal VEAO, a pulse is provided to an on-timer  103  so that on-timer  103  turns a primary switch M 1  on and turns a synchronous switch M 2  off. After a constant period T 1  passes, on-timer  103  turns off the primary switch M 1  and turns on the synchronous switch M 2 . With the complementary actions of switches M 1  and M 2 , an output voltage VOUT is generated from an input voltage VIN. 
     When a transient load step occurs, the error signal VEAO may react smoothly. To achieve fast transient response for the converter circuit  10 , the peak to peak amplitude of the ramp signal VRAMP should be very small. But the small ramp amplitude may cause two major problems. First, it means that the noise margin of the converter circuit  10  is relatively small. When the converter circuit  10  is operating in a noisy operation environment, this feature may lead to a big risk. Second, to cope with small amplitude signal, circuit elements such as comparators need draw more power to achieve desired speed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. The drawings are only for illustration purpose. These drawings are not necessarily drawn to scale. The relative sizes of elements illustrated by the drawings may differ from the relative size depicted. 
         FIG. 1  illustrates a schematic circuit diagram of a prior art converter circuit  10 . 
         FIG. 2  illustrates a schematic circuit diagram of a converter circuit  20  according to an embodiment of the present invention. 
         FIG. 3  illustrates an operational wave form diagram of converter circuit  20  according to one embodiment of the present invention. 
         FIG. 4  illustrates an operational wave form diagram of a transient response comparison between the converter circuit  20  and the prior art converter circuit  10  according to an embodiment of the present invention. 
         FIG. 5  illustrates a schematic circuit diagram of a converter circuit  50  according to another embodiment of the present invention. 
         FIG. 6  illustrates an operational waveform diagram of converter circuit  50  according to one embodiment of the present invention. 
         FIG. 7  illustrates a schematic circuit diagram of a converter circuit  70  according to yet another embodiment of the present invention. 
         FIG. 8  illustrates a schematic circuitry diagram of a converter circuit  80  according to yet another embodiment of the present invention. 
         FIG. 9  illustrates a process flow of a method for controlling a converter circuit according to one embodiment of the present invention. 
     
    
    
     The use of the same reference label in different drawings indicates the same or like components. 
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present technology may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. 
     The term “on time” hereby and in the following text indicates in a converter circuit, the duration of a primary switch (high side switch in certain embodiments) turning on within per operational cycle. The term “off-time” hereby and in the following text indicates the duration of the primary switch turning off within per single operational cycle. 
       FIG. 2  illustrates a schematic circuit diagram of a converter circuit  20  according to an embodiment of the present invention. As shown in  FIG. 2 , the converter circuit  20  primarily comprises a voltage converter  201  and a controller  202 . In certain embodiments, voltage converter  201  is a switch mode converter. For example, in the embodiment shown in  FIG. 2 , the voltage converter  201  is a DC-DC buck converter. Other types of converter, such as boost converter, buck-boost converter, fly-back converter, or any other suitable converter that is known by the ordinary artisan, may also be applied as the switch mode converter. The switch mode converter  201  at least comprises a high side switch M 1 , and in certain embodiments further comprises a low side switch M 2 . It is well-known by the ordinary artisan that the low side switch M 2  may also be replaced by a free-wheel diode in other embodiments. A driver circuit  208  is coupled to the switches M 1  and M 2 , configured to drive switches M 1  and M 2  according to the output of controller  202 . A conjunction node of switches M 1  and M 2  is defined as switch node SW. An output inductor L, a resistor RESR, and an output capacitor COUT together comprise a filter circuit of the switch-mode converter  201 , wherein RESR is the practical equivalent series resistor of the ideal output capacitor COUT. A feedback loop comprising resistors R 1  and R 2  detects an output voltage VOUT on an output node OUT, and configured to generate a feedback signal FB. 
     Continuing seen in  FIG. 2 , in one embodiment, controller  202  comprises a timer  203 , an error amplifier  204 , a proportional amplifier circuit  205 , and a first comparator  206 . In the illustrated embodiment, the error amplifier  204  is an operation transconductance amplifier (OTA). The OTA  204  comprises a non-inverting input end, an inverting input end and an output end, wherein the non-inverting input end is coupled to a reference signal VREF, and wherein the inverting input end is coupled to the feedback signal FB. A capacitor CF is coupled between the output end of the OTA  204  and a reference ground. Thus, an error signal VEAO is generated on the output end of OTA  204 . Proportional amplifier circuit  205  has two inputs and an output, wherein the two inputs respectively receive the output voltage VOUT and the error signal VEAO, and wherein the output generates a gain signal VGAIN accordingly. In one embodiment, the proportional amplifier circuit  205  comprises an operation amplifier AMP, a first resistor R 3  and a second resistor R 4 . The operation amplifier AMP has a first input, a second input and an output, wherein the first input is coupled to the output end of the OTA  204 , and wherein the output is coupled to the first comparator  206 . The first resistor R 3  is coupled to the output voltage VOUT with one terminal and coupled to the second input end of the operation amplifier with the other terminal. The second resistor R 4  is coupled between the second input of the operation amplifier AMP and the output of the operation amplifier AMP. Resistors R 3  and R 4  are configured to decide the magnification factor of proportional amplifier circuit  205 . One with ordinary skill in relevant art should note that in other embodiments, other well known circuit structures may also be utilized as proportional amplifier  205 . First comparator  206  has two inputs and an output, wherein the two inputs respectively receive the gain signal VGAIN and a comparison signal, and wherein the output generates a pulse signal Vpulse accordingly. When the comparison signal is smaller than the gain signal VGAIN, a pulse is generated on the pulse signal Vpulse. One feature of the illustrated embodiment is that at least either the gain signal VGAIN or the comparison signal comprises a ramp component. For example, in the embodiment illustrated in  FIG. 2 , the comparison signal is a ramp signal VRAMP generated by a ramp network  207 . In one embodiment, ramp network  207  is coupled with the output inductor L of the converter circuit in parallel. The ramp network  207  may comprise a resistor Rc and a capacitor Cc, wherein the resistor Rc and the capacitor Cc are in series coupled. The ramp signal VRAMP is generated on a conjunction node CON of the resistor Rc and the capacitor Cc. In other embodiments, ramp network  207  may alternatively comprise other suitable circuitry structures and connection relationships. For example, the ramp network  207  may be coupled to the node OUT to receive the output voltage VOUT only; or the ramp network  207  may further comprises a voltage divider to provide a divided output voltage VOUT to the capacitor Cc rather than to directly couple the output voltage VOUT to the capacitor Cc. Timer  203  has an input and an output, wherein the input is coupled to the output of the first comparator  206 , and wherein the output generates a timing signal VT to indicate the on-time and the off-time of the converter circuit. In one embodiment, the output of timer  203  serves as the output of controller  202  and the timing signal VT controls at least the high side switch M 1  via the driver circuit  208 . In the illustrated embodiment, the timing signal VT further controls the low side switch M 2 . The high switch M 1  and the low side switch M 2  are turned on complementarily. Once a pulse is generated on the pulse signal Vpulse, the timing signal VT steps up to turn on the primary switch M 1  and to turn off the synchronous switch M 2 . Meanwhile timer  203  begins timing. After a constant time TON, the timing signal VT flops to low level to turn off the high side switch M 1  and to turn on the low side switch M 2 . 
     In another embodiment, the controller  202  further comprises an optional OR gate  209  (depicted in area enclosed by the dash line). OR gate  209  has two inputs and an output, and wherein the two inputs respectively receive the timing signal VT and the pulse signal Vpulse, and wherein the output serves as the output of controller  202 , and is coupled to and controls at least the high side switch M 1  via the driver circuit  208 . The output of OR gate  209  may be further coupled to and controls the low side switch M 2  via the driver circuit  208  in certain embodiments. Once a pulse is generated on the Vpulse, the high side switch M 1  may be turned on immediately, which may avoid the propagation delay caused by the timer  203  and thus may obtain a better transient response performance. Also, as long as output of the comparator  206  is high, the high side switch M 1  will keep on, which may extend on time in case of heavy load step-up. 
       FIG. 3  illustrates an operational wave form diagram of converter circuit  20  according to one embodiment of the present invention. According to  FIG. 2  and  FIG. 3 , the operational principle of converter circuit  20  is described in the following text. 
     Seen in  FIG. 3 , converter circuit  20  is operating in steady state. The error signal VEAO generated by OTA  204  is a function of feedback signal FB and the reference signal VREF (e.g. 0.8V). Specifically, the error signal 
                   VEAO   =       (     VREF   -   VFB     )     ⁢     gm     ω   ⁢           ⁢   CF                 (   1   )               
Wherein, gm is the transconductance of OTA  204 , ω is the switching angular velocity, and wherein ω=2π×fsw, and fsw is the switching frequency of high side switch M 1 .
 
     Proportional amplifier circuit  205  receives the error signal VEAO and the output voltage VOUT. Due to the proportional amplifying effect of resistors R 3  and R 4 , 
                         VGAIN   -   VEAO       R   ⁢           ⁢   4       =       VEAO   -   VOUT       R   ⁢           ⁢   3         ⁢     
     ⁢     Therefore   ,             (   2   )               VGAIN   =         -       R   ⁢           ⁢   4       R   ⁢           ⁢   3         ⁢   VOUT     +           R   ⁢           ⁢   3     +     R   ⁢           ⁢   4         R   ⁢           ⁢   3       ⁢   VEAO               (   3   )               
In steady state, the error signal VEAO is nearly constant. The variation of gain signal VGAIN may be considered a function of the output voltage VOUT. Consequently, by properly setting the values of resistors R 3  and R 4 , the gain signal VGAIN may be very sensitive to the change on the output voltage VOUT.
 
     Meanwhile, in the illustrated embodiment, ramp network  207  is coupled in parallel with the output inductor L to obtain the ramp signal VRAMP. When the high side switch M 1  is turned on, the voltage level on node SW nearly equals VIN. For a buck converter, VIN&gt;VOUT. At this time, the capacitor Cc is charged and the voltage level of ramp signal VRAMP rises with a slope S 1 . After the constant on time TON, the ramp signal VRAMP reaches its peak value. The ramp amplitude of the ramp signal is: 
                   VRAMP   =       TON   RcCc     ⁢     (     VIN   -   VOUT     )               (   4   )               
Then, the timer  203  stops timing. The high side switch M 1  is turned off, and the low side switch M 2  is turned on. The voltage level on node SW falls down to near ground voltage. The capacitor Cc is discharged and the voltage level of the ramp signal VRAMP declines with a slope S 2 .
 
     Whenever the voltage level of the ramp signal VRAMP equals to the gain signal VGAIN, a pulse is generated on the pulse signal Vpulse. This pulse is delivered to the timer  203  to begin timing for a next round. The high side switch M 1  is turned on again and the low side switch M 2  is turn off. Consequently the converter circuit  20  enters the next operation cycle. 
       FIG. 4  illustrates an operational wave form diagram of a transient response comparison between the converter circuit  20  and the prior art converter circuit  10  according to an embodiment of the present invention. As shown in  FIG. 4 , a large amplitude ramp component is applied in the ramp signal VRAMP. At steady state (before moment K 1 ), the load current IOUT is maintained at I 1 . At moment K 1 , the load current IOUT steps down from I 1  to I 2 . The output voltage VOUT immediately responses from load current IOUT and drastically rises up. For the converter circuit  20 , in response of the rising of output voltage VOUT, the gain signal VGAIN proportionally declines down according to formula (3). Whereas, for the prior art converter circuit  10 , due to the limited conductance gm, and the delay effect of the capacitor CF, the response of error signal VEAO is relatively slow. At moment K 2 , the on-time of this operational cycle ends, and the ramp signal VRAMP drops down with the slope S 2 . Because of the quick and drastic response of VGAIN, the ramp signal VRAMP touches the gain signal VGAIN much later than the error signal VEAO. As a result, the prior art converter circuit  10  enters into the next operation cycle at moment K 3 , while the converter circuit  20  according to an embodiment of the present invention enters into the next operation cycle at moment K 4 , wherein the moment K 4  is much later than the moment K 3 , which means that the output voltage VOUT on converter circuit  20  may stop rising earlier than it on the prior art converter circuit  10 . Continuously seen in  FIG. 4 , at moment K 4 , the output voltage VOUT on converter circuit  20  has already declined from the peak value. While the output voltage VOUT on the prior art converter circuit  10  is still rising up. Moreover, after moment K 4 , by the effect of proportional amplifier circuit  205 , the gain signal VGAIN also rises up in proportional to the output voltage VOUT. When the ramp signal VRAMP declines with the slope S 2 , it quickly touches the gain signal VGAIN again, Thus more pulses may be generated on the pulse signal Vpulse within per unit time, so that it may take shorter time for the output voltage VOUT on converter circuit  20  to return to normal. Seen in  FIG. 4 , at moment K 5 , the output voltage VOUT of converter circuit  20  according to the present embodiment is completely recovered, and a total recovery time of load step-up for converter circuit  20  is defined as TR 1 . Whereas, until moment K 6 , the output voltage VOUT of prior art converter circuit  10  is completely recovered and the total recovery time of load step-up for converter circuit  10  is defined as TR 2 . Wherein, TR 1  is much shorter than TR 2 . 
     Continuing with  FIG. 4 , similarly with the load step-down transient response process described above, once the load current IOUT steps up from I 2  to I 1 , the output voltage VOUT on the converter circuit  20  may also stop declining earlier and quickly return to normal value inasmuch as the gain signal VGAIN declines down and rises up drastically. The recovery time of load step-up TR 3  for converter circuit  20  may be also much shorter than the recovery time of load step-up TR 4  for prior art converter circuit  10 . 
     Therefore, the above analysis indicates that compared with prior art converter circuit  10 , the converter circuit  20  according to an embodiment of the present invention may obtain a better transient response performance when a large amplitude ramp component is applied. 
       FIG. 5  illustrates a converter circuit  50  according to another embodiment of the present invention. Converter circuit  50  has elements similar to converter circuit  20  in  FIG. 2 . For ease of illustration, the detailed information of the similar elements will not be described. 
     In the embodiment shown in  FIG. 5 , the output voltage VOUT is applied as the comparison signal instead of the ramp signal VRAMP. Therefore, the ramp network  207  is omitted. First comparator  206  compares the output voltage VOUT with the gain signal VGAIN. Meanwhile, in proportional amplifier circuit  205 , a capacitor Cc 2  is coupled with the resistor R 3  in parallel, configured to generate a ramp component on the gain signal VGAIN. 
       FIG. 6  illustrates an operational waveform diagram of converter circuit  50  according to one embodiment of the present invention. Seen in  FIG. 6 , when converter circuit is operating in steady state, with the ramp component generated by the capacitor Cc 2 , the gain signal is: 
     
       
         
           
             
               
                 
                   
                     
                       
                         VGAIN 
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                                   R 
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                                 R 
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                                 3 
                               
                             
                             ⁢ 
                             VEAO 
                           
                           - 
                           
                             
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 4 
                               
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 3 
                               
                             
                             ⁢ 
                             VOUT 
                           
                           - 
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             4 
                             ⁢ 
                             Cc 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                             ⁢ 
                             
                               
                                 ⅆ 
                                 VOUT 
                               
                               
                                 ⅆ 
                                 t 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
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                               - 
                               
                                 
                                   R 
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                                   ⁢ 
                                   4 
                                 
                                 
                                   R 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   3 
                                 
                               
                             
                             ⁢ 
                             VOUT 
                           
                           - 
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             4 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             Cc 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
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                               IL 
                               COUT 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     Wherein, 
               -   R     ⁢           ⁢   4   ⁢   Cc   ⁢           ⁢   2   ⁢     IOUT   COUT           
is the ramp component of gain signal VGAIN, and
 
               -       R   ⁢           ⁢   4       R   ⁢           ⁢   3         ⁢   VOUT         
is defined as a steady component of gain signal VGAIN. IL is the inductor current of converter circuit  50 . According to formula (5), the amplitude of the ramp component of the gain signal VGAIN is proportional to the inductor current IL with a factor of
 
             -         R   ⁢           ⁢   4   ⁢           ⁢   Cc   ⁢           ⁢   2     COUT     .           
By properly setting the value of R 4 , Cc 2  and COUT, a large amplitude ramp component (e.g. 80 mV) may be applied on gain signal VGAIN. Meanwhile, compared with the output voltage VOUT, the ramp component of gain signal VGAIN is small enough to be ignored. Consequently, the gain signal VGAIN may still be considered proportional to the output voltage VOUT, which allows the gain signal VGAIN continuously being sensitive to the change on output voltage VOUT.
 
     During the off time of converter circuit  50 , the output voltage VOUT slightly declines due to its ripple, and inversely following the inductor current IL. The gain signal VGAIN rises up with a slope S 4 . If the gain signal VGAIN reaches the output voltage VOUT, the first comparator  206  will generate a pulse on the pulse signal Vpulse. The high side switch M 1  is turned on and the low side switch M 2  is turned off. The converter circuit  50  enters into on time. As the inductor current IL begins rising up, the output voltage VOUT also rises and the gain signal VGAIN declines down with a slope S 3 . After a constant on time TON, the high side switch M 1  is turned off and the low side switch M 2  is turned on. The converter circuit  50  enters into off time again. 
     Continuing in  FIG. 6 , when the load current IOUT of converter circuit  50  steps down, i.e. a load step-up happening on the converter circuit  50 , the output voltage VOUT responses from the load current IOUT to rises up drastically. Meanwhile, inversely following the inductor current IL, the gain signal VGAIN initially steps up. Then, since the output voltage VOUT drastically rises up, the gain signal VGAIN proportionally declines. As a result, the difference between the output voltage VOUT and the gain signal VGAIN increases rapidly. During the off time, it takes more time for the gain signal VGAIN reaching the output voltage VOUT again. The prolonged off time of converter circuit  50  may help to quickly stop the output voltage VOUT rising up. Later, similar with the converter circuit  20 , if the output voltage VOUT of converter circuit  50  declines, the gain signal VGAIN also rises up drastically, which may generate more pulses per unit time. It allows the output voltage VOUT to quickly return to the normal value. 
     When the load current of converter circuit  50  steps up, the output voltage VOUT on the converter circuit  50  may also stop declining and return to normal value due to the similar reason described above. Therefore, when applying a large amplitude ramp component in gain signal VGAIN, the converter circuit  50  may also obtain an excellent transient response performance by means of the short recovery time of the load step. 
       FIG. 7  illustrates a schematic circuit diagram of a converter circuit  70  according to yet another embodiment of the present invention. Converter circuit  70  has elements similar to converter circuit  20  in  FIG. 2 . For ease of illustration, the detailed information of the similar elements will not be described. 
     As shown in  FIG. 7 , converter circuit  70  further comprises a termination circuit  710 , configured to terminate the on time of converter circuit  70  when a load step-down is detected. In one embodiment, the termination circuit  710  comprises: an offset voltage source  711 , having a positive end and a negative end, wherein the positive end is coupled to the positive input of proportional amplifier circuit  205 ; a second comparator  712 , having a non-inverting input, an inverting input and an output, wherein the inverting input is coupled to the output of proportional amplifier  205 , and wherein the non-inverting input is coupled to the negative end of offset voltage source  711 ; a flip-flop  713 , having a set end, a reset end and a Q output, wherein the set end is coupled to the output of the second comparator  712 , and wherein the reset end is coupled to the output of the first comparator  206 , and further wherein the Q output provides a terminating signal to indicate the step-down of the load current IOUT; and a logic operation circuit  714 , having two inputs and an output, wherein the logic operation circuit is coupled to the Q output of the flip-flop  713  and the output of the timer  203  respectively with its two inputs, and wherein the logic operation circuit  714  is coupled to at least the high side switch M 1  with its output, and wherein the logic operation circuit  714  is configured to turn off at least the high side switch M 1  in the converter circuit  201  when the terminating signal indicates a load step-down. 
     In one embodiment, the logic operation circuit  714  comprises: an inverter  715 , having an input and an output, wherein the input is coupled to the output of the timer  203 ; a first NOR gate  716 , having two inputs and an output, wherein the two inputs are respectively coupled to output of the inverter  715  and the Q output of the flip-flop  713 , and the output is configured to generate a high side gate signal HSG to control the high side switch M 1  through the driver circuit  208 . 
     In one embodiment, a low side switch M 2  is applied in voltage converter  201 . The logic operation circuit  714  further comprises a second NOR gate  717 , having two inputs and an output, wherein the two inputs are respectively coupled to the output of the time  203  and the Q output of the flip-flop  713 , and the output is configured to generate a low side gate signal LSG to control the low side gate M 2  through the driver circuit  208 . 
     The offset voltage source  711  generates an offset voltage Voffset. When the converter circuit is operating normally, the voltage level on the non-inverting input of the second comparator  712  is VEAO-Voffset, which is always lower than the gain signal VGAIN at normal status. Thus the second comparator  712  continuously provides a low level output to the set end of the flip-flop  713 , and the voltage level on output Q of the flip-flop  713  is maintained at low level. The high side gate signal HSG and the low side gate signal LSW (if applied) then depend on the timing signal VT, or further on the pulse signal Vpulse. The converter circuit  70  shares the same operation principle with the convert circuit  20  at this occasion. 
     When a step-down occurs on the load current IOUT, the output voltage VOUT of converter circuit  70  is in response of this step-down and rises drastically. Following the output voltage VOUT, the gain signal VGAIN also declines down drastically. If the gain signal VGAIN touches VEAO-Voffset, the second comparator  712  generates a high level output to the set end of flip-flop  713 . Then the flip-flop  713  is set and the output Q of flip-flop  713  is turned to high. Both the first NOR gate  716  and the second NOR gate  717  respond from this high level Q output of flip-flop  713 , and therefore the high side gate signal HSG and the low side gate signal LSG (if applied) are turned to low. Whenever the converter circuit  70  is in on-time or off-time, it immediately enters into a “shut-time”, wherein during this shut-time, both the high side switch M 1  and the low side switch M 2  (if applied) are turned off. At this time, if the low switch M 2  is applied, the body diode of the low side switch M 2  is applied as a fly-wheel diode and comprises a current loop together with the inductor L and the output capacitor COUT. 
     During the on-time of converter circuit  70 , when the load current step-down occurs, the on-time ends immediately to prohibit the rising of the output voltage VOUT since the high side switch M 1  is turned off. Meanwhile as described above, the low side switch M 2  is also turned off, the body diode of the low side switch M 2  serves as a fly-wheel diode. With a relatively large on-state resistance, the voltage level on the conjunction SW of switches M 1  and M 2  is lower than normal, which speeds up the ramp down of the inductor current IL during the shut time of the converter circuit  70 . Therefore, the step-down transient response speed of converter circuit  70  may be further improved. 
       FIG. 8  illustrates a schematic circuitry diagram of a converter circuit  80  according to yet another embodiment of the present invention. Converter circuit  80  has elements similar to converter circuit  50  in  FIG. 5 . For ease of illustration, the detailed information of the similar elements will not be described. 
     Compared with converter circuit  50 , converter circuit  80  further comprises a termination circuit  810 , configured to make converter circuit  80  enter into a shut time when a load step-down is detected. In one embodiment, the termination circuit  810  comprises: an offset voltage source  811 , having a positive end and a negative end, wherein the positive end is coupled to the output voltage VOUT; a second comparator  812 , having a non-inverting input, an inverting input and an output, wherein the inverting input is coupled to the output of proportional amplifier  205 , and wherein the non-inverting input is coupled to the negative end of offset voltage source  811 ; a flip-flop  813 , having a set end, a reset end and a Q output, wherein the set end is coupled to the output of the second comparator  812 , and wherein the reset end is coupled to the output of the first comparator  206 , and further wherein the Q output provides a terminating signal to indicate the step-down of the load current IOUT; and a logic operation circuit  814 , receiving the terminating signal and the control signal VG, operable to turn the high side switch M 1  and the low side switch M 2  (if applied) off when the terminating signal indicates a step-down of the load current IOUT. 
     In one embodiment, the logic operation circuit  814  comprises: an inverter  815 , having an input and an output, wherein the input is coupled to the output of the timer  203 ; a first NOR gate  816 , having two inputs and an output, wherein the two inputs are respectively coupled to output of the inverter  815  and the Q output of the flip-flop  813 , and the output is configured to generate a high side gate signal HSG to control the high side switch M 1  through the driver circuit  208 . 
     In one embodiment, a low side switch M 2  is applied in voltage converter  201 . The logic operation circuit  814  further comprises a second NOR gate  817 , having two inputs and an output, wherein the two inputs are respectively coupled to the output of the timer  203  and the Q output of the flip-flop  813 , and the output is configured to generate a low side gate signal LSG to control the low side gate M 2  through the driver circuit  208 . 
     One with ordinary skill in relevant art may understand that the above described embodiment is illustrative without limitation. In other embodiments, other well-known circuit structures or their combinations may also be implemented into the logic operation circuit  814  to achieve similar function. 
     The offset voltage source  811  generates an offset voltage Voffset. When the converter circuit  80  is operating normally, the voltage level on the non-inverting input of the second comparator  812  is VOUT-Voffset, which is always lower than the ramp bottom of the gain signal VGAIN at normal. Thus the second comparator  812  continuously provides a low level output to the set end of the flip-flop  813 , and the voltage level on output Q of the flip-flop  813  is maintained at low level. The high side gate signal HSG and the low side gate signal LSG (if applied) then totally depend on the timing signal VT, and the pulse signal Vpulse (if applied). The converter circuit  80  shares the same operation principle with the convert circuit  50  at this occasion. 
     When a step-down occurs on the load current IOUT, the output voltage VOUT of converter circuit  80  is in response of this step-down and rises drastically, which makes VOUT-Voffset also rise drastically. And following the output voltage VOUT, the gain signal VGAIN also declines down drastically. The level difference between VGAIN and VOUT-Voffset is thus greatly narrowed. If the gain signal VGAIN touches VOUT-Voffset, the second comparator  812  generates a high level output to the set end of flip-flop  813 . Then the flip-flop  813  is set and the output Q of flip-flop  813  is turned to high. Both the first NOR gate  816  and the second NOR gate  817  respond from this high level Q output of flip-flop  813 , and therefore the high side gate signal HSG and the low side gate signal LSG (if applied) are turned low respectively, whenever the converter circuit  80  is in on-time or off-time, it immediately enters into the shut-time, wherein during this shut-time, both the high side switch M 1  and the low side switch M 2  (if applied) are turned off. As this time, if the low side switch M 2  is applied in switch-mode voltage converter  201 , the body diode of the low side switch M 2  is applied as a fly-wheel diode and comprises a current loop together with the inductor L and the output capacitor COUT. 
     With the same reason the converter circuit  70  as described above, since both the high side switch M 1  and the low side switch M 2  are turned off, the step-down transient response of converter circuit  80  may be further improved. 
       FIG. 9  illustrates a process flow of a method for controlling a converter circuit according to one embodiment of the present invention. Seen in  FIG. 9 , the method comprises: step  901 , generating an error signal VEAO according to a feedback signal and a reference signal; step  902 , sending the error signal VEAO and an output voltage VOUT to a first proportional amplifier, configured to obtain a gain signal VGAIN; step  903 , comparing the gain signal VGAIN with a comparison signal, configured to generate a pulse signal Vpulse; step  904 , generating a time signal VT according to the pulse signal Vpulse to decide the on time and the off time of the converter circuit, wherein the length of the on time is constant; wherein, either of the gain signal VGAIN or the comparison signal comprises a ramp component. 
     In certain embodiments, the method for controlling the converter circuit may further comprise a step  905 , controlling at least a high side switch M 1  according to the time signal VT. 
     In another embodiment, controlling at least a primary switch M 1  is further according to the pulse signal Vpulse. 
     In certain embodiments, the method for controlling the converter circuit may further comprise a step  906  of generating a ramp signal VRAMP as the comparison signal. The ramp signal VRAMP may be generated by a ramp network. In one embodiment, the amplitude of the ramp signal VRAMP may depends on the output voltage VOUT and an input voltage VIN of the converter circuit. In other embodiments, the amplitude of the ramp signal VRAMP may depends on the output voltage VOUT solely; or the output voltage VOUT may be divided first. 
     In another embodiment, the method for controlling the converter circuit may alternatively further comprise a step  907  instead of the step  906 . The step  907  comprises: generating the ramp component on the gain signal VGAIN. Wherein the output voltage VOUT serves as the comparison signal. 
     In yet another embodiment, the method for controlling the converter circuit may further comprise an optional step  908 . Step  908  comprises: comparing the gain signal with an offset signal to indicate a load current step-down, and shut down all power switches in the converter circuit when the load current step-down is detected. 
     In one embodiment, the step  905  may further comprise controlling a low side switch M 2  in the converter circuit on and off according to the timing signal and the pulse signal (if applied). And the step  908  may further comprise shutting down the low side switch M 2  in the converter circuit when a load current step-down is detected. 
     In one embodiment, the offset signal is the sum of the error signal and a negative offset voltage. In another embodiment, the offset signal is the sum of the output voltage and a negative offset voltage. 
     The above description and discussion about specific embodiments of the present invention is for purposes of illustration. However, one with ordinary skill in the relevant art should know that the invention is not limited by the specific examples disclosed herein. Variations and modifications can be made on the apparatus, methods and technical design described above. Accordingly, the invention should be viewed as limited solely by the scope and spirit of the appended claims.