Patent Publication Number: US-2023155062-A1

Title: Package structure and forming method thereof

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority of Taiwan Patent Application No. 110142699, filed on Nov. 17, 2021, the entirety of which is incorporated by reference herein. 
     BACKGROUND 
     Technical Field 
     The disclosure is related to a package structure and a forming method thereof, and in particular, it is related to a package structure including vertically stacked light-emitting diode (LED) chips and a forming method thereof. 
     Description of the Related Art 
     Continuous advances in display technology has seen RGB LEDs used as display pixels and a light source for some display panels, gradually replacing the more conventional liquid-crystal display panels. Since the energy consumption of LEDs is low, display panels using LEDs may run more efficiently and save energy compared with conventional liquid-crystal display panels, and they may also reduce carbon emissions, making them more environmentally friendly. Therefore, display panels using LEDs have drawn much attention in the display field. It is hard to realize small-pitch operation for the RGB display because of the process limit of the package technology of the surface mounted device. However, improvements have been sought to existing display devices to adopt chip-on-board (COB) technology. Both mini LEDs and micro LEDs would realize small-pitch operation. 
     Although existing package structures have been adequate for their intended purposes, they have not been entirely satisfactory in all respects. Accordingly, improvements in the package structures and a forming method thereof are still necessary to produce display devices that meet market demand. 
     BRIEF SUMMARY OF THE DISCLOSURE 
     In accordance with some embodiments of the disclosure, a package structure is provided. The package structure has a light-emitting region and a non-light-emitting region that is adjacent to the light-emitting region, and includes a substrate, a first light-emitting layer, a second light-emitting layer and a third light-emitting layer. The first light-emitting layer, the second light-emitting layer and the third light-emitting layer are sequentially stacked on the substrate. Each of the first light-emitting layer, the second light-emitting layer and the third light-emitting layer includes a transparent adhesive layer disposed in the light-emitting region, a light-emitting diode (LED) chip disposed on the transparent adhesive layer, a redistribution layer formed on the LED chip and extending from the light-emitting region to the non-light-emitting region, and a planarization layer disposed on the LED chip and the redistribution layer. 
     In accordance with some embodiments of the disclosure, a package structure is provided. The package structure has a light-emitting region and a non-light-emitting region that is adjacent to the light-emitting region. The package structure includes a substrate, a first light-emitting unit, a first planarization layer, a second light-emitting unit, a third light-emitting unit, and a second planarization layer. The first light-emitting unit is disposed on the substrate. The first planarization layer is disposed on the first light-emitting unit. The second light-emitting unit and the third light-emitting unit are disposed on the first planarization layer and laterally separated from each other. The second planarization layer is disposed on the second light-emitting unit and the third light-emitting unit. Each of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit includes a transparent adhesive layer, an LED chip, and a redistribution layer. The transparent adhesive layer is disposed in the light-emitting region. The LED chip is disposed on the transparent adhesive layer. The redistribution layer is formed on the LED chip, and extends from the light-emitting region to the non-light-emitting region. 
     In accordance with some embodiments of the disclosure, a method for forming a package structure is provided. The method includes providing a source wafer on which a plurality of LED chips is disposed. Each of the LED chips is connected to the source wafer through a tethered structure. The method further includes providing a target substrate having a pre-determined light-emitting region and a pre-determined non-light-emitting region adjacent to the pre-determined light-emitting region. A first electrode, a second electrode, a third electrode, and a common electrode are disposed in the pre-determined non-light-emitting region of the target substrate and are in physical contact with the target substrate. The method further includes sequentially forming a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer on the target substrate. Each of forming the first light-emitting layer, forming the second light-emitting layer, and forming the third light-emitting layer includes transferring one LED chip on the source wafer to the pre-determined light-emitting region of the target substrate using a pickup device and forming a redistribution layer on the LED chip. The redistribution layer extends from the pre-determined light-emitting region to the pre-determined non-light-emitting layer. Each of forming the first light-emitting layer, forming the second light-emitting layer, and forming the third light-emitting layer further includes forming a planarization layer on the LED chip and the redistribution layer. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure may be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG.  1    illustrates a cross-sectional view of a package structure at the intermediate stage of its forming process according to some embodiments. 
         FIG.  2 A  illustrates a cross-sectional view of a source wafer on which a plurality of LED chips is disposed according to some embodiments. 
         FIG.  2 B  illustrates an enlarged cross-sectional view of an LED chip according to some embodiments. 
         FIGS.  2 C and  2 D  illustrate the process of transferring LED chips from a source wafer according to some embodiments. 
         FIGS.  3 A and  3 B  illustrate attachment of a transparent adhesive layer to the bottom surface of the LED chip or formation of the transparent adhesive layer on a target substrate. 
         FIGS.  4  and  5 A  illustrate cross-sectional views of a package structure at the intermediate stages of its forming process according to some embodiments. 
         FIG.  5 B  illustrates a top view of a package structure at the intermediate stage of its forming process according to some embodiments. 
         FIGS.  6 - 13    illustrate cross-sectional views of a package structure at the intermediate stages of its forming process according to some embodiments. 
         FIG.  14    is a cross-sectional view of a package structure according to other embodiments. 
         FIGS.  15  and  16 A  are perspective views of package structures according to various embodiments. 
         FIGS.  16 B and  16 C  illustrate cross-sectional views of the package structure respectively taken along lines B-B′ and C-C′ in  FIG.  16 A  according to some embodiments. 
         FIG.  17    is a perspective view of a package structure according to other embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE DISCLOSURE 
     The package structure and a forming method thereof of the disclosure are described in detail in the following description. It should be appreciated that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of elements and arrangements are described below to clearly describe the disclosure in a simple manner. These are, of course, merely examples and are not intended to be limiting. In addition, different embodiments may use like and/or corresponding reference numerals to denote like and/or corresponding elements for clarity. However, like and/or corresponding reference numerals are used merely for the purpose of clarity and simplicity, and do not suggest any correlation between different embodiments. 
     According to some embodiments of the disclosure, the package structure includes a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer sequentially stacked above the substrate. Each of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer includes a transparent adhesive layer, an LED chip, a redistribution layer, and a planarization layer. The LED chips emitting light with different colors are disposed along the vertical direction in the package structure, and the electrodes used for transmitting signals to the LED chips are disposed on the substrate. Therefore, the package structure with stacked LED chips may reduce the area of a single pixel in a display device, and may enhance the integrated density of pixels and the resolution of the display device. Furthermore, according to some embodiments of the disclosure, the method for forming the package structure includes transferring a single LED chip or LED chips with a certain period from a source wafer to a target substrate. The non-transferred LED chips may remain for the next process. This way, space utilization of the source wafer may be increased, the process of the package structure may be simplified, and the yield of the package structure may be improved. 
       FIG.  1    illustrates a cross-sectional view of a package structure  10  at the intermediate stage of its forming process according to some embodiments. First, a target substrate  100  is provided. The target substrate  100  has a pre-determined light-emitting region  100   a  and a pre-determined non-light emitting region  100   b  that is adjacent to the pre-determined light-emitting region  100   a.  In some embodiments, the pre-determined light-emitting region  100   a  may surround the pre-determined non-light emitting region  100   b.  It should be understood that, after completing the package structure  10 , the target substrate  100  may be abbreviated as a substrate  100 , and the pre-determined light-emitting region  100   a  and the pre-determined non-light emitting region  100   b  may be respectively abbreviated as a light-emitting region  100   a  and a non-light-emitting region  100   b.    
     As shown in  FIG.  1   , electrodes  102 ,  104 ,  106 , and a common electrode  108  are disposed in the pre-determined non-light-emitting region  100   b  of the target substrate  100 . According to some embodiments, the electrodes  102 ,  104 ,  106 , and the common electrode  108  may be in physical contact with the target substrate  100 . 
     In some embodiments, the target substrate  100  may be a backplane of a display device. In particular, the backplane of the display device may include a circuit substrate, such as a thin film transistor substrate or a glass substrate, a quartz substrate, or a silicon substrate having conductive wires. In other embodiments, the target substrate  100  may be an interposer substrate. The interposer substrate may include multiple metal wire layers and a plurality of vias connecting the metal wire layers. In addition, in some embodiments, the target substrate  100  may be a transparent substrate. Specifically, the transparent substrate may have a light transmittance to light with a wavelength in a range from 200 nm to 1100 nm greater than 90%, or preferably greater than 95%. 
     In some embodiments, the material of the electrodes  102 ,  104 ,  106 , and the common electrode  108  disposed in the pre-determined non-light-emitting region  100   b  of the target substrate  100  may include any suitable conductive materials, such as Al, Cu, W, Ti, Cr, Pt, Au, Ta, Ni, TiN, TaN, NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, indium tin oxide (ITO), other suitable conductive materials, or a combination thereof. 
       FIG.  2 A  illustrates a cross-sectional view of a source wafer  200  on which a plurality of LED chips  300  is disposed according to some embodiments, and  FIG.  2 B  illustrates an enlarged cross-sectional view of an LED chip  300  according to some embodiments. Referring to  FIG.  2 A , the source wafer  200  is provided. A plurality of LED chips  300  is disposed on the source wafer  200 , and each of the LED chips  300  is connected to the source wafer  200  through a tethered structure  315 . According to some embodiments, as shown in  FIG.  2 A , each of the LED chips  300  is suspended above the source wafer  200  through the tethered structure  315 . In some embodiments, the source wafer  200  may be a silicon wafer. In some embodiments, the LED chips  300  disposed on the source wafer  200  may be LED chips emitting blue light, red light, or green light. 
     Referring to  FIG.  2 B , according to some embodiments, the LED chip  300  may include, from the bottom to the top, a base layer  302 , a n-type semiconductor layer  304 , a light-emitting layer  306 , a p-type semiconductor layer  308 , an ohmic contact layer  310 , and a protection layer  312 . In particular, the protection layer  312  may be formed on a portion of the top surfaces of the n-type semiconductor layer  304  and the ohmic contact layer  310 , and may conformally extend to sidewalls of the base layer  302 , n-type semiconductor layer  304 , the light-emitting layer  306 , the p-type semiconductor layer  308 , and the ohmic contact layer  310 . The LED chip  300  may further include a first electrode  314  and a second electrode  316 . The first electrode  314  and the second electrode  316  are formed on the protection layer  312  and further penetrates through a portion of the protection layer  312  to be in physical contact with the ohmic contact layer  310  and the n-type semiconductor layer  304 , respectively. 
     According to some embodiments, the base layer  302  of the LED chip  300  may be a sapphire substrate. According to some embodiments of the disclosure, the n-type semiconductor layer  304  may be a n-doped III-V semiconductor layer. For example, the III-V semiconductor layer may include GaAs, GaN, GaP, InAs, GaAsP, AlGaAs, InGaP, InGaN, AlInGaP, InGaAsP, suitable III-V semiconductor epitaxial materials, or a combination thereof. Furthermore, in some embodiments, the III-V semiconductor layer may be doped with group IVA elements (e.g., silicon) to form the n-doped III-V semiconductor layer. 
     According to some embodiments of the disclosure, the p-type semiconductor layer  308  may be a p-doped III-V semiconductor layer. The III-V semiconductor layer may include GaAs, GaN, GaP, InAs, AN, InN, InP, GaAsP, AlGaAs, InGaP, InGaN, AlInGaP, InGaAsP, suitable III-V semiconductor epitaxial materials, or a combination thereof. Furthermore, in some embodiments, the III-V semiconductor layer may be doped with group IIA elements (e.g., Be, Mg, Ca, or Sr) to form the p-doped semiconductor layer. 
     In some embodiments, the light-emitting layer  306  may include a multiple quantum well (MQW), a single quantum well (SQW), a homo-junction, a hetero-junction, or the like. In some embodiments, the ohmic contact layer  310  may include a transparent conductive material or an opaque conductive material. For example, the transparent conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), other transparent conductive materials, or a combination thereof. The opaque conductive material may include Ni, Ag, or a Ni/Au alloy. 
     In some embodiments, the protection layer  312  may include any suitable insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, epoxy, photoresist materials, other suitable materials, or a combination thereof. In some embodiments, the materials of the first electrode  314  and the second electrode  316  may include Al, Cu, Ni, Au, Pt, Ti, an alloy thereof, or other suitable conductive materials. 
     According to some embodiments, a sacrificial layer (not shown) may be formed on the source wafer  200  first, and the layers of the LED chip  300  (such as the base layer  302 , the n-type semiconductor layer  304 , the light-emitting layer  306 , the p-type semiconductor layer  308 , and the ohmic contact layer  310 ) may be formed on the sacrificial layer. Next, a portion of the sacrificial layer may be removed using suitable etching processes to form an opening around the LED chip  300  that exposes the source wafer  200 . The protection layer  312  is formed on the n-type semiconductor layer  304  and the ohmic contact layer  310 . The protection layer  312  may be further conformally formed on the sidewalls of the base layer  302 , the n-type semiconductor layer  304 , the light-emitting layer  306 , the p-type semiconductor layer  308 , and the ohmic contact layer  310 , on a portion of the sacrificial layer, and in the aforementioned opening. Subsequently, the sacrificial layer may be removed using suitable etching methods. As shown in  FIG.  2 B , after removing the sacrificial layer, a portion of the protection layer  312  may be formed as the tethered structure  315 , and the LED chip  300  may be suspended above the source wafer  200  through the tethered structure  315 . After removing the sacrificial layer, the overlying structure is supported only by the tethered structure  315 . Therefore, the tethered structure  315  may be easily broken to separate the LED chip  300  and the source wafer  200 . 
       FIGS.  2 C and  2 D  illustrate the process of transferring LED chips  300  from the source wafer  200  according to some embodiments. The LED chips  300  are picked up using a pickup device  401 . In some embodiments, as shown in  FIG.  2 C , the pickup device  401  may include a base  402 . The base  402  has protruding portions  402   a  formed with a specific period. For example, in some embodiments, as shown in  FIG.  2 C , the protruding portions  402  may be formed every two LED chips  300 , but the disclosure is not limited thereto. The protruding portions  402  may be formed with different periods according to actual process needs. For example, the protruding portions  402   a  may be formed every three, every four, every five or more LED chips. The base  402  has the protruding portions  402   a  formed with a specific period to transfer a single LED chip  300  or LED chips  300  with a certain period to the target substrate. The remaining non-transferred LED chips may be used for the next round of the process. This way, space utilization of the source wafer  200  may be increased, the process of the package structure may be simplified, and the yield of the package structure may be increased. 
     According to some embodiments, the base  402  may include a flexible adhesive polymeric material, such as a flexible polymer material, to attach to the LED chips  300  after the tethered structures  315  are broken. Specifically, the flexible polymer material may include a poly-siloxane-based material, such as polydimethylsiloxane (PDMS). However, in other embodiments, the base  402  may include a material without adhesiveness. For example, in some embodiments, the material without adhesiveness may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), or other suitable materials. 
     In the embodiments where the base  402  includes a material without adhesiveness, as shown in  FIG.  2 C , the pickup device  401  may further include an adhesive layer  404  disposed on the surface of the protruding portion  402   a  of the base  402 . In some embodiments, the adhesive layer  404  may include poly-carbonate, polycarbodiimide, epoxy resin, poly-vinyl acetal, acrylic resin, polyester, other suitable adhesive materials, or a combination thereof. 
     Referring again to  FIG.  2 C , a pickup process  500  is performed. During the pickup process  500 , the pickup device  401  applies pressure to the LED chips  300  to break the tethered structure  315  that connects the LED chips  300  and the source wafer  200 . After the tethered structure  315  is broken, the LED chips  300  are separated from the source wafer  200  at the tethered structure  315 . 
     Referring to  FIG.  2 D , the contact surfaces (such as the protruding portions  402   a  or the adhesive layer  404 ) between the pickup device  401  and the LED chips  300  are adhesive, and accordingly the LED chips  300  without support may be attached to the pickup device  401 . In addition, in some embodiments, after the tethered structure  315  is broken, a portion of the tethered structure  315  in  FIG.  2 C  (may be also referred to as a tethered structure  317 ) may remain on the outer edge of the LED chip  300 . It should be noted that the tethered structure  317  may not be shown in the following figures since the cross-sectional views may not be cross-sections of the package structure that include the tethered structure  317 . 
       FIGS.  3 A and  3 B  illustrate attachment of a transparent adhesive layer  318  to the bottom surface of the LED chip  300  or formation of the transparent adhesive layer  318  on a target substrate  100  and in the pre-determined light-emitting region  100   a  according to various embodiments. Referring to  FIG.  3 A , in some embodiments, during the transfer of the LED chips  300  to the target substrate  100 , the transparent adhesive layer  318  may be attached to the bottom surface of the LED chips  300 . Referring to  FIG.  3 B , in other embodiments, the transparent adhesive layer  318  may be also directly formed in the pre-determined light-emitting region  100   a  and on the target substrate  100  prior to the transfer of the LED chips  300  to the target substrate  100 . 
     In some embodiments, the material of the transparent adhesive layer  318  may include an organic material, such an organic polymer material. In some specific embodiments, the material of the transparent adhesive layer  318  may include a photoresist material. According to some embodiments, the transparent adhesive layer  318  may have a light transmittance to light with a wavelength in a range from 500 nm to 1100 nm greater than 90%, or preferably greater than 95%. In some embodiments, the thickness of the transparent adhesive layer  318  may be between about 2 μm and about 20 μm, such as about 10 μm. 
     Since the adhesion between the transparent adhesive layer  318 , the target substrate  100  and/or the LEDs chip  300  may be greater than the adhesion between the LED chip  300  and the pickup device  401 , the LED chips  300  may be detached from the pickup device  401  after the LED chips  300  are attached to the target substrate  100 . 
     Subsequently,  FIGS.  4  and  5 A  illustrate cross-sectional views of the package structure  10  at the intermediate stages of its forming process according to some embodiments. As shown in  FIG.  4   , the LED chip  300  is transferred into the pre-determined light-emitting region  100   a  of the target substrate  100 . In  FIG.  4   , the LED chip after the transfer may be also referred to as an LED chip  300   a.  In addition, as shown in  FIG.  4   , no matter which method is used to form the transparent adhesive layer  318 , the transparent adhesive layer  318  may be sandwiched between the target substrate  100  and the LED chip  300   a  after transferring the LED chip  300   a  to the pre-determined light-emitting region  100   a  of the target substrate  100 . In some embodiments, the projection planes of the LED chip  300   a  and the transparent adhesive layer  318  on the target substrate  100  may completely overlap. In addition, in  FIG.  4   , the projection area of the LED chip  300   a  on the target substrate  100  is illustrated to be the same as that of the transparent adhesive layer  318  on the target substrate  100 . However, in other embodiments, the projection area of the LED chip  300   a  on the target substrate  100  may be greater than or less than that of the transparent adhesive layer  318  on the target substrate  100 . 
     Next, referring to  FIG.  5 A , a redistribution layer  320   a  is formed on the LED chip  300   a.  The redistribution layer  320   a  extends from the pre-determined light-emitting region  100   a  of the target substrate  100  to the pre-determined non-light-emitting region  100   b  of the target substrate  100 . Furthermore, in some embodiment, in addition to forming on the LED chip  300   a,  the redistribution layer  320   a  may be conformally formed on the sidewall of the LED chips  300   a,  on the target substrate  100 , and on the electrodes  106  and the common electrode  108 . According to some embodiments, the redistribution layer  320   a  may electrically connect the LED chip  300   a  to the electrode  106  and the common electrode  108 . 
     The distribution layer in the package structure (and additional redistribution layers formed subsequently) may realize the formation of high-density stacked LED chips directly on the target substrate (such as the backplane of the interposer substrate of the display device). The electrical connection of the LED chip may extend from the pre-determined light-emitting region to the pre-determined non-light-emitting region in the package structure through the redistribution layer. Compared to the conventional package process that forms LED chips directly on a wafer, the process window and reliability of the resulting package structure may be increased. 
     According to some embodiments, the material of the redistribution layer  320   a  may include Al, Cu, W, Ti, Cr, Pt, Au, Ta, Ni, TiN, TaN, NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, indium tin oxide (ITO), other suitable conductive materials, or a combination thereof, but the present disclosure is not limited thereto. The material of the redistribution layer  320   a  may be deposited using electro-plating, physical vapor deposition (PVD), atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), other suitable deposition techniques, or a combination thereof. Next, a portion of the material of the redistribution layer  320   a  is removed using suitable etching processes to expose two electrodes of the LED chip  300   a.  Alternatively, in other embodiments, a patterned photoresist may be formed first to define a region in which the redistribution layer  320   a  is formed, and the material of the redistribution layer  320   a  may be deposited in this region to form a patterned redistribution layer  320   a.  Subsequently, the photoresist may be removed and further process steps may be performed. 
     Referring to  FIG.  5 B ,  FIG.  5 B  is a top view of the package structure  10  shown in  FIG.  5 A .  FIG.  5 A  is taken along a line A-A′ in  FIG.  5 B . It should be noted that although the LED chip  300  in the cross-sectional views of  FIGS.  2 D and  3 A  is illustrated to have only one tethered structure  317 , the disclosure is not limited thereto. Each LED chip  300  may have at least one tethered structure  317 . For example, as shown in  FIG.  5 B , in some other embodiments, the LED chip  300   a  (and other LED chips disposed later) may have more than one tethered structure  317 , such as two tethered structures  317 . In  FIG.  5 B , although the tethered structures  317  in the package structure  10  are illustrated to form on two ends of the LED chip  300   a,  the disclosure is not limited thereto. In other embodiments, the tethered structures  317  may be formed at any places on the outer edge of the LED chip  300   a  as long as the tethered structures  317  does not completely overlap the redistribution layer  320  from the top-view shown in  FIG.  5 B . 
       FIGS.  6 - 13    illustrate cross-sectional views of the package structure  10  at the intermediate stages of its forming process according to some embodiments. Referring to  FIG.  6   , after forming the redistribution layer  320   a,  a planarization layer  110   a  is formed on the LED chip  300   a  and the redistribution layer  320   a.  In particular, as shown in  FIG.  6   , the planarization layer  110   a  is formed on the target substrate  100 , the electrodes  102 ,  104 ,  106 , the common electrode  108 , the LED chip  300   a,  and the redistribution layer  320   a.  After forming the planarization layer  110   a,  the transparent adhesive layer  318 , the LED chip  300   a,  the redistribution layer  320   a  and the planarization layer  110  may be collectively referred to as a first light-emitting layer  400   a.    
     In accordance with some embodiments, the planarization layer  110   a  may be transparent. Specifically, the planarization layer  110   a  may have a light transmittance to light with a wavelength in a range from 200 nm to 1100 nm greater than 90%, or preferably greater than 95%. In some embodiments, the material of the planarization layer  110   a  may include an organic material or an inorganic material. In some specific embodiments, the material of the planarization layer  110   a  may include an organic material. In some embodiments, the organic material may include photoresist or benzocyclobutene (BCB). In some embodiments, the inorganic material may include silicate glass or phosphor-silicate glass. The planarization layer  110   a  may be formed using any suitable deposition processes, such as a spin-on coating process, a chemical vapor deposition (CVD) process, a PVD process, an ALD process, other applicable deposition methods, or a combination thereof. 
     Next, referring to  FIG.  7   , a portion of the planarization layer  110  in the first light-emitting layer  400   a  is removed to form openings  112 ,  114 , and  116  in the planarization layer  110   a.  The openings  112 ,  114 , and  116  respectively expose the electrodes  102  and  104  and the redistribution layer  320   a  on the common electrode  108 . The portion of the planarization layer  110   a  may be removed using any suitable methods. For example, in the embodiments where the planarization layer  110   a  includes an organic material such as photoresist, the portion of the planarization layer  110   a  may be removed using a photolithography process. In some embodiments, the photolithography process may include soft baking, hard baking, mask aligning, exposure, post-exposure baking (PEB), developing photoresist, rinsing, drying, and/or other suitable processes. 
     Referring to  FIG.  8   , an LED chip  300   b  is disposed on the planarization layer  110   a  of the first light-emitting layer  400   a  using the aforementioned method, and the transparent adhesive layer  318  is sandwiched between the planarization layer  110   a  and the LED chip  300   b.  It should be noted that the transparent adhesive layer  318  and the LED chip  300   b  are also disposed in the pre-determined light-emitting region  100   a  of the target substrate  100 . 
     Next, referring to  FIG.  9   , a redistribution layer  320   b  is formed on the LED chip  300   b.  The redistribution layer  320   b  extends from the pre-determined light-emitting region  100   a  of the target substrate  100  to the pre-determined non-light-emitting region  100   b  of the target substrate  100 . In addition, in some embodiments, in addition to forming on the LED chip  300   b,  the redistribution layer  320   b  may be conformally formed on the sidewall of the LED chip  300   b  and on the planarization layer  110   a,  and may further extend into the openings  114  and  116 . According to some embodiments, as shown in  FIG.  9   , the redistribution layer  320   b  that extends into the openings  114  and  116  may be conformally formed on sidewalls and bottom surfaces of the openings  114  and  116 . Moreover, the redistribution layer  320   b  that extends into the openings  114  and  116  may be respectively in physical contact with the electrode  104  and the redistribution layer  320   a  on the common electrode  108  so that the redistribution layer  320   b  may electrically connect the LED chip  300   b  to the electrode  104  and the common electrode  108 . It should be noted that the portion of the redistribution layer  320   b  that extends into the opening  114  may be referred to as a via  150  herein. In some embodiments, as shown in  FIG.  9   , the via  150  may extend through the planarization layer  110   a  of the first light-emitting layer  400   a.  The material and the method for the redistribution layer  320   b  are similar to or the same as those for the redistribution layer  320   a,  which are not repeated herein. 
     Next, referring to  FIG.  10   , after forming the redistribution layer  320   b,  a planarization layer  110   b  is formed on the LED chip  300   b  and the planarization layer  320   a.  In particular, as shown in  FIG.  10   , the planarization layer  110   b  is formed on the LED chip  300   b  and the redistribution layer  320   b,  and may further extend into and fill the space in the via  150  that is not filled with the redistribution layer  320   b.  In addition, the planarization layer  110   b  may further fill the openings  112  and  116 . However, after forming the planarization layer  110   b,  the openings  112  and  116  may be formed again using the aforementioned method to remain the space for the subsequent formation of an additional redistribution layer. After forming the planarization layer  110   b,  the transparent adhesive layer  318 , the LED chip  300   b,  the redistribution layer  320   b,  and the planarization layer  110   b  disposed on the first light-emitting layer  400   a  may be collectively referred to as a second light-emitting layer  400   b.    
     Next, referring to  FIG.  11   , similar steps to those shown in  FIG.  8    are repeated. An LED chip  300   c  is disposed on the planarization layer  110   b  of the second light-emitting layer  400   b,  and the transparent adhesive layer  318  is sandwiched between the planarization layer  110   b  and the LED chip  300   c.  Likewise, the transparent adhesive layer  318  and LED chip  300   c  on the second light-emitting layer  400   b  are also disposed in the pre-determined light-emitting region  100   a  of the target substrate  100 . 
     Referring to  FIG.  12   , similar steps to those shown in  FIG.  9    are repeated. A redistribution layer  320   c  is formed on the LED chip  300   c.  The redistribution layer  320   c  extends from the pre-determined light-emitting region  100   a  of the target substrate  100  to the pre-determined non-light-emitting region  100   b  of the target substrate  100 . In addition, in some embodiments, in addition to forming on the LED chip  300   c,  the redistribution layer  320   c  may be conformally formed on the sidewall of the LED chip  300   c  and on the planarization layer  110   b,  and may further extend into the openings  112  and  116 . According to some embodiments, as shown in  FIG.  12   , the redistribution layer  320   c  that extends into the openings  112  and  116  may be conformally formed on sidewalls and bottom surfaces of the openings  112  and  116 . Moreover, the redistribution layer  320   c  that extends into the openings  112  and  116  may be respectively in physical contact with the electrode  102  and the redistribution layer  320   b  in the opening  116  so that the redistribution layer  320   c  may electrically connect the LED chip  300   c  to the electrode  102  and the common electrode  108 . It should be noted that the portions of the redistribution layer  320   b  and  320   c  that extend into the opening  116  may be referred to as a via  152  herein, and the portion of the redistribution layer  320   c  that extends into the opening  112  may be referred to as a via  154  herein. In some embodiments, as shown in  FIG.  12   , the vias  152  and  154  may extend through the planarization layer  110   a  of the first light-emitting layer  400   a  and the planarization layer  110   b  of the second light-emitting layer  400   b.    
     Furthermore, according to some embodiments, the redistribution layer  320   b  may be electrically connected to the electrode  104  and the common electrode  108  through the vias  150  and  152 , respectively, and the redistribution layer  320   c  may be electrically connected to the electrode  102  and the common electrode  108  through the vias  154  and  152 , respectively. As shown in  FIG.  12   , the redistribution layer  320   b  of the second light-emitting layer  400   b  and the redistribution layer  320   c  may be electrically connected to the common electrode  108  through the same via  152 . Accordingly, the number of electrically connected contacts formed on the target substrate  100  may be reduced. 
     Referring to  FIG.  13   , in some embodiments, the ratio of a depth  154 D of the via  154  to a width  154 W (i.e., the minimal width) of the via  154  (aspect ratio) may be between about 2:1 and about 20:1. Similarly, in some embodiments, the via  152 , which electrically connects the redistribution layers  320   b  and  320   c  to the common electrode  108 , may have an aspect ratio (i.e., the ratio of the depth of the via  152  to the minimal width of the via  152 ) of about 2:1 to about 20:1. The vias  152  and  154  having the aspect ratio within the above range may reduce the space occupied by the vias in the package structure, thereby improving signal integrity of the LED chips in the package structure. 
     Next, referring again to  FIG.  13   , a planarization layer  110   c  is formed on the redistribution layer  320   c  and the LED chip  300   c.  In particular, the planarization layer  110   c  is formed on the redistribution layer  320   c,  the LED chip  300   c,  and the planarization layer  110   b  of the second light-emitting layer  400   b,  and may further extend into and fill the space in the vias  152  and  154  that is not filled by the redistribution layer  320   c.  After forming the planarization layer  110   c,  the transparent adhesive layer  318 , the LED chip  300   c,  the redistribution layer  320   c,  and the planarization layer  110   c  disposed on the second light-emitting layer  400   b  may be collectively referred to as a third light-emitting layer  400   c.    
     In some embodiments, the LED chip  300   a  of the first light-emitting layer  400   a  may emit light with a first wavelength, the LED chip  300   b  of the second light-emitting layer  400   b  may emit light with a second wavelength, and the LED chip  300   c  of the third light-emitting layer  400   c  may emit light with a third wavelength. The first wavelength, the second wavelength, and the third wavelength are different from one another. Moreover, as described above, in some embodiments, each of the LED chips  300   a,    300   b,  and  300   c  may be a blue light, green light, or red light LED chip. 
     In  FIG.  13   , in accordance with some embodiments, a first side  100 H of the target substrate  100  on which the first light-emitting layer  400   a,  the second light-emitting layer  400   b,  and the third light-emitting layer  400   c  are disposed may be defined as the light-emitting side of the package structure  10 . In these embodiments, the first wavelength of the light emitted by the LED chip  300   a  is greater than the second wavelength of the light emitted by the LED chip  300   b,  and the second wavelength of the light emitted by the LED chip  300   b  is greater than the third wavelength of the light emitted by the LED chip  300   c.  For example, in these embodiments, the LED chips  300   a,    300   b,  and  300   c  may be a red light LED chip, a green light LED chip, and a blue light LED chip, respectively. 
     When the first side  100 H shown in  FIG.  13    is the light-emitting side, the light emitted by the LED chip located at the lower layer (such as the LED chip  300   a  of the first light-emitting layer  400   a ) may have a longer wavelength, and the light emitted by the LED chip located at the upper layer (such as the LED chip  300   c  of the third light-emitting layer  400   c ) may have a shorter wavelength. This way, the light emitted by the LED chip in the upper light-emitting layer may be prevented from passing through the lower light-emitting layers, and the light emitted by the LED chips in the lower layers may not be affected accordingly. 
     However, in other embodiments, a second side  100 L of the target substrate  100  on which the first light-emitting layer  400   a,  the second light-emitting layer  400   b,  and the third light-emitting layer  400   c  are not disposed may be also defined as the light-emitting side of the package structure  10 . The second side  100 L is opposite to the first side  100 H. In these embodiments, the third wavelength of the light emitted by the LED chip  300   c  is greater than the second wavelength of the light emitted by the LED chip  300   b,  and the second wavelength of the light emitted by the LED chip  300   b  is greater than the first wavelength of the light emitted by the LED chip  300   a.  For example, in these embodiments, the LED chips  300   a,    300   b,  and  300   c  may be a blue light LED chip, a green light LED chip, and a red light LED chip, respectively. 
     When the second side  100 L shown in  FIG.  13    is the light-emitting side, the light emitted by the LED chip located at the upper layer (such as the LED chip  300   c  of the third light-emitting layer  400   c ) may have a longer wavelength, and the light emitted by the LED chip located at the lower layer (such as the LED chip  300   a  of the first light-emitting layer  400   a ) may have a shorter wavelength. This way, the light emitted by the LED chip in the lower light-emitting layer may be prevented from passing through the upper light-emitting layers, and the light emitted by the LED chips in the upper layers may not be affected accordingly. 
     As shown in  FIG.  13   , according to some embodiments of the disclosure, the package structure  10  has a light-emitting region  100   a  (i.e., the pre-determined light-emitting region  100   a  described above) and a non-light-emitting region  100   b  (i.e., the pre-determined non-light-emitting region  100   b  described above) that is adjacent to the light-emitting region  100   a.  The package structure  10  includes a substrate  100  (i.e., the target substrate  100  described above) and the first light-emitting layer  400 , the second light-emitting layer  400   b,  and the third light-emitting layer  400   c  that are sequentially stacked. Each of the first light-emitting layer  400 , the second light-emitting layer  400   b,  and the third light-emitting layer  400   c  includes the transparent adhesive layer  318 , the LED chip (the LED chip  300   a,    300   b,  or  300   c ) on the transparent adhesive layer  318 , the redistribution layer (the redistribution layer  320   a,    320   b,  or  320   c ) on the LED chip and extending from the light-emitting region  100   a  to the non-light-emitting region  100   b,  and the planarization layer (the planarization layer  110   a,    110   b,  or  110   c ) on the LED chip and the redistribution layer. 
     In the embodiments shown in  FIGS.  1 ,  2 A- 2 D,  3 A- 3 B,  4 ,  5 A- 5 B, and  6 - 13   , respective LED chips may be formed on the source wafer, and the LED chips may be stacked vertically on the target substrate. As such, LED chips emitting light with different colors may be disposed along the vertical direction in the package structure to reduce the area of a single pixel in the display device. Furthermore, the LED chip is attached to the target substrate and the planarization layer in the light-emitting layer through the transparent adhesive layer. It is unnecessary to bond an LED chip to another LED chip, and thus the process complexity of the package structure may be reduced. On the other hand, the method for forming the package structure provided by the disclosure includes transferring a single LED chip or LED chips with a certain period from a source wafer to a target substrate. The non-transferred LED chips may remain for the next process. This way, space utilization of the source wafer may be increased, the process of the package structure may be simplified, and the yield of the package structure may be improved. 
       FIG.  14    is a cross-sectional view of a package structure  20  according to other embodiments. The package structure  20  shown in  FIG.  14    is similar to the package structure  10  shown in  FIG.  13   , except that an interposer substrate (substrate  100 ) is used as a base structure for the package structure  20 . In this embodiment, apart from the substrate  100  that is used as the interposer substrate, the package structure  20  may further include a conductive structure  103  disposed below the substrate  100 . As described above, the substrate  100 , which is used as the interposer substrate, may include multiple metal wire layers and a plurality of vias that connect every metal wire layer although the vias are not shown in  FIG.  14   . The package structure  20  may be electrically connected to another target substrate (such as another backplane of a display device) through the substrate  100  and the conductive structure  103 . In some embodiments, the material of the conductive structure  103  may include any suitable conductive materials, such as Al, Cu, W, Ti, Cr, Pt, Au, Ta, Ni, TiN, TaN, NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, indium tin oxide (ITO), other suitable conductive materials, or a combination thereof. According to the embodiment shown in  FIG.  14   , the package structure  20  may be used as a minimal unit and transferred to another target substrate to adjust the pixel density and the resolution of the display device at any time, thereby enhancing process flexibility. 
       FIG.  15    is a perspective view of the package structure  10  according to some embodiments. In the package structure  10  shown in  FIG.  15   , although the redistribution layer  320   b  and  320   c  may be electrically connected to the common electrode  108  through the same via  152 , the disclosure is not limited thereto. In other embodiments, the redistribution layer  320   b  and  320   c  may be electrically connected to the common electrode  108  through respective vias. These vias are also disposed in the aforementioned non-light-emitting region of the substrate  100 , extending through the planarization layers  110   a  and  110   b.  The arrangement of the vias used for electrically connecting the redistribution layers  320   b  and  320   c  is not particularly limited as long as these vias are also disposed in the aforementioned non-light-emitting region of the substrate  100  and are electrically connected to the common electrode  108 . 
     In addition, in some embodiments, the projection planes of the LED chips  300   a,    300   b,  and  300   c  on the substrate  100  at least partially overlap. In some specific embodiments, as shown in  FIG.  15   , the projection planes of the LED chips  300   a,    300   b,  and  300   c  on the substrate  100  completely overlap. 
       FIG.  16 A  is a perspective view of the package structure  30  according to some embodiments. It should be understood that, in  FIG.  16 A , the elements and/or features with the same reference numerals as those in the aforementioned embodiments may include the same materials, and like processes may be used to form these elements and/or features, which are not repeated herein. The difference between the package structure  30  shown in  FIG.  16 A  and the package structure  10  shown in  FIG.  15    is that the package structure  30  includes two planarization layers (the planarization layers  110   a  and  110   b ). The LED chip  300   a  is disposed in the planarization layer  110   a,  and the LED chips  300   b  and  300   c  are disposed in the planarization layer  110   b.    
     In some embodiments, as shown in  FIG.  16 A , the LED chips  300   b  and  300   c  may be stacked above the LED chip  300   a.  In some embodiments, the size of the LED chip  300   a  may be greater than the size of the LED chip  300   b  or  300   c.  Specifically, according to some embodiments, the projection area of the LED chip  300   a  on the substrate  100  may be greater than the projection area of the LED chip  300   b  or  300   c  on the substrate  100 . Furthermore, the projection area of the LED chip  300   a  on the substrate  100  may be greater than the sum of the projection areas of the LED chips  300   b  and  300   c  on the substrate  100 . 
     In accordance with some embodiments, each projection plane of the LED chips  300   b  and  300   c  on the substrate  100  at least partially overlaps the projection plane of the LED chip  300   a  on the substrate  100 . In some specific embodiments, each projection plane of the LED chips  300   b  and  300   c  on the substrate  100  completely overlaps the projection plane of the LED chip  300   a  on the substrate  100 . 
       FIGS.  16 B and  16 C  illustrate cross-sectional views of the package structure  30  respectively taken along lines B-B′ and C-C′ in  FIG.  16 A  according to some embodiments. Referring to  FIGS.  16 B and  16 C , according to some embodiments of the disclosure, the transparent adhesive layer  318  on the substrate  100 , the LED chip  300   a,  and the redistribution layer  320   a  may be collectively referred to as a first light-emitting unit  350   a.  The transparent adhesive layer  318  on the planarization layer  110   a,  the LED chip  300   b,  and the redistribution layer  320   b  may be collectively referred to as a second light-emitting unit  350   b.  The transparent adhesive layer  318  on the planarization layer  110   a,  the LED chip  300   c,  and the redistribution layer  320   c  may be collectively referred to as a third light-emitting unit  350   c.    
     In particular, the package structure  30  includes the substrate  100 , the first light-emitting unit  350   a  on the substrate  100 , the planarization layer  110   a  on the first light-emitting unit  350   a,  the second light-emitting unit  350   b,  the third light-emitting unit  350   c,  and the planarization layer  110   b  disposed on the second light-emitting unit  350   b  and the third light-emitting unit  350   c.  As described above, the first light-emitting unit  350   a,  the second light-emitting unit  350   b,  and the third light-emitting unit  350   c  include the transparent adhesive layer  318  disposed in the light-emitting region  100   a  of the substrate  100 , the LED chips  300   a,    300   b,  and  300   c  disposed on the transparent adhesive layer  318 , and the redistribution layers  320   a,    320   b,  and  320   c.  The light-emitting unit  350   b  and the light-emitting unit  350   c  are disposed on the planarization layer  110   a  and laterally separated from each other. As shown in  FIGS.  16 A- 16 C , the redistribution layer  320   a,    320   b,  and  320   c  of the first light-emitting unit  350   a,  the second light-emitting unit  350   b,  and the third light-emitting unit  350   c  are respectively formed on the LED chips  300   a,    300   b,  and  300   c,  and extend from the light-emitting region  100   a  of the substrate  100  to non-light-emitting region  100   b  of the substrate  100 . 
     According to some embodiments, as shown in  FIGS.  16 A- 16 C , the package structure  30  may further include the electrode  102 ,  104 , and  106  and the common electrode  108 . The electrode  102 ,  104 , and  106  and the common electrode  108  are disposed in the non-light-emitting region  100   b  of the substrate  100 , and are in physical contact with the substrate  100 . In some embodiments, the redistribution layer  320   a  of the first light-emitting unit  350   a  may electrically connect the LED chip  300   a  to the electrode  106  and the common electrode  108 . In some embodiments, the redistribution layer  320   b  of the second light-emitting unit  350   b  may electrically connect the LED chip  300   b  to the electrode  102  and the common electrode  108 . In some embodiments, the redistribution layer  320   c  of the third light-emitting unit  350   c  may electrically connect the LED chip  300   c  to the electrode  104  and the common electrode  108 . 
     In addition, in some embodiments, as shown in  FIGS.  16 A- 16 C , the redistribution layer  320   b  of the second light-emitting unit  350   b  may be electrically connected to the common electrode  108  and the electrode  102  respectively through the vias  152  and  154 , and the redistribution layer  320   c  of the third light-emitting unit  350   c  may be electrically connected to the electrode  104  and the common electrode  108  respectively through the vias  150  and  156 . In some embodiments, all of the vias  150 ,  152 ,  154 , and  156  are disposed in the non-light-emitting region  100   b  of the substrate  100 , and extend through the planarization layer  110   a.  In accordance with some embodiments, the vias  150 ,  152 ,  154 , and  156  may have an aspect ratio of about  2 : 1  to about  20 : 1  (i.e., a ratio of the depth of the via  150 ,  152 ,  154 , or  156  to the minimal width of the via  150 ,  152 ,  154 , or  156 ). The vias  150 ,  152 ,  154 , and  156  having the aspect ratio within the above range may reduce the space occupied by the vias in the package structure, thereby improving signal integrity of the LED chips in the package structure. 
     In  FIGS.  16 A- 16 C , although the redistribution layer  320   b  of the second light-emitting unit  350   b  and the redistribution layer  320   c  of the third light-emitting unit  350   c  are electrically connected to the same common electrode  108  respectively through the vias  152  and  156 , the disclosure is not limited thereto. In other embodiments, the redistribution layer  320   b  of the second light-emitting unit  350   b  and the redistribution layer  320   c  of the third light-emitting unit  350   c  may extend to the same via (not shown), and may be electrically connected to the common electrode  108  through this via. Similarly, this via may be disposed in the non-light-emitting region  100   b  of the substrate  100 , and may extent through the planarization layer  110   a.    
     Moreover, in some embodiments, as shown in  FIG.  16 C , a first side  100 H of the substrate  100  on which the first light-emitting unit  350   a,  the second light-emitting unit  350   b,  and the third light-emitting unit  350   c  are disposed may be defined as the light-emitting side of the package structure  30 . In some embodiments, the LED chip  300   a  of the first light-emitting unit  350   a  may emit light with a first wavelength, the LED chip  300   b  of the second light-emitting unit  350   b  may emit light with a second wavelength, and the LED chip  300   c  of the light-emitting unit  350   c  may emit light with a third wavelength. The first wavelength, the second wavelength, and the third wavelength may be different from one another. 
     In the embodiments where the first side  100 H is the light-emitting side of the package structure  30 , the first wavelength of the light emitted by the LED chip  300   a  may be greater than the second wavelength of the light emitted by the LED chip  300   b  and the third wavelength of the light emitted by the LED chip  300   c.  The second wavelength and the third wavelength are different. For example, in some embodiments, the LED chips  300   a  may be a red light LED chip and the LED chips  300   b  and  300   c  may respectively be a green light LED chip and a blue light LED chip, or the LED chips  300   b  and  300   c  may respectively be a blue light LED chip and a green light LED chip. 
     When the first side  100 H is used as the light-emitting side of the package structure  30 , the light emitted by the LED chips  300   b  and  300   c  of the second light-emitting unit  350   b  and the third light-emitting unit  350   c  may have shorter wavelength than that emitted by the LED chip  300   a  of the first light-emitting unit  350   a.  This way, the light emitted by the LED chips  300   b  and  300   c  of the second light-emitting unit  350   b  and the third light-emitting unit  350   c  may be prevented from passing through the underlying planarization layer  110   a,  and the light emitted by the LED chip  300   a,  which is below the LED chips  300   b  and  300   c,  may not be affected accordingly. 
     According to the embodiments shown in  FIGS.  16 A- 16 C , the LED chips with a smaller size (such as the LED chips  300   b  and  300   c  of the second light-emitting unit  350   b  and the third light-emitting unit  350   c ) are vertically stacked above the LED chip with a bigger size (such as the LED chip  300   a  of the first light-emitting unit  350   a ), and the LED chips with a smaller size are laterally separated from each other. In addition to the advantages described in the aforementioned embodiments, the package structure with the stacked LED chips may have a smaller overall size (such as a smaller height), thereby reducing the thickness of the display device in which this package structure is disposed. 
       FIG.  17    is a perspective view of a package structure  40  according to other embodiments. The package structure  40  shown in  FIG.  17    is similar to the package structure  30  shown in  FIG.  16   , except that the LED chip  300   a  with a bigger size is disposed above the LED chips  300   b  and  300   c  with a smaller size. In particular, in these embodiments, the LED chips  300   b  and  300   c  are disposed in the planarization layer  110   b  and separated from each other, and the LED chip  300   a  is disposed in the planarization layer  110   a.  In some embodiments, the projection plane of the LED chip  300   a  on the substrate  100  may at least partially overlap the projection planes of the LED chip  300   b  and  300   c  on the substrate  100 . In some specific embodiments, the projection plane of the LED chip  300   a  on the substrate  100  may completely overlap the projection planes of the LED chip  300   b  and  300   c  on the substrate  100 . In accordance with some embodiments, the projection area of the LED chip  300   a  on the substrate  100  may be greater than the sum of the projection areas of the LED chip  300   b  and  300   c  on the substrate  100 . 
     In some embodiments, a second side  100 L of the substrate  100  on which the LED chips  300   a,    300   b,  and  300   c  are not disposed may be defined as the light-emitting side of the package structure  40 . In the embodiments where the second side  100 L is used as the light-emitting side of the package structure  40 , the first wavelength of the light emitted by the LED chip  300   a  may be greater than the second wavelength of the light emitted by the LED chip  300   b  and the third wavelength of the light emitted by the LED chip  300   c.  For example, in some embodiments, the LED chips  300   a  may be a red light LED chip and the LED chips  300   b  and  300   c  may respectively be a green light LED chip and a blue light LED chip, or the LED chips  300   b  and  300   c  may respectively be a blue light LED chip and a green light LED chip. 
     When the second side  100 L is used as the light-emitting side of the package structure  40 , the light emitted by the LED chips  300   b  and  300   c  may have a shorter wavelength than that emitted by the LED chip  300   a.  This way, the light emitted by the LED chips  300   b  and  300   c  in the planarization layer  110   a  may be prevented from passing through the above planarization layer  110   b,  and the light emitted by the LED chip  300   a,  which is above the LED chips  300   b  and  300   c,  may not be affected accordingly. 
     In addition, in the embodiments shown in  FIG.  17   , the LED chip  300   a  may be electrically connected to the electrode  106  and the common electrode  108  through the redistribution layer  320   a,  the LED chip  300   b  may be electrically connected to the electrode  102  and the common electrode  108  through the redistribution layer  320   b,  and the LED chip  300   c  may be electrically connected to the electrode  104  and the common electrode  108  through the redistribution layer  320   c.  In particular, in some embodiments, the redistribution layer  320   a  may be electrically connected to the common electrode  108  and the electrode  106  respectively through vias  158  and  160 . That is, the LED chip  300   a  may be electrically connected to the common electrode  108  and the electrode  106  through the redistribution layer  320   a  and the vias  158  and  160 . The material and the forming method for the vias  158  and  160  are similar to or the same as those for the vias  152 ,  154 , and  156  in the aforementioned embodiments, which are not repeated again. Furthermore, according to some embodiments, the vias  158  and  160  may extend through the planarization layer  110   a.  In addition, as described in the above embodiment with respect to  FIG.  16 A , the vias  158  and  160  in the embodiment shown in  FIG.  17    may also have an aspect ratio of about 2:1 to about 20:1 (i.e., a ratio of the depth of the vias  158  and  160  to the minimal width of the vias  158  and  160 ). 
     In summary, according to some embodiments of the disclosure, the package structure includes a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer sequentially stacked above the substrate. Each of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer includes a transparent adhesive layer, an LED chip, a redistribution layer, and a planarization layer. The LED chips emitting light with different colors are disposed along the vertical direction in the package structure, and the electrodes used for transmitting signals to the LED chips are disposed on the substrate. Therefore, the package structure with stacked LED chips may reduce the area of a single pixel in a display device, and may enhance the integrated density of pixels and the resolution of the display device. Furthermore, according to some embodiments of the disclosure, the method for forming the package structure includes transferring a single LED chip or LED chips with a certain period from a source wafer to a target substrate, forming the redistribution layer that extends from the light-emitting region to the non-light-emitting region, and forming the planarization layer. The above process may be repeated on the substrate to disposed vertically stacked LED chips. The non-transferred LED chips on the source wafer may remain for the next process. By using the forming method of the package structure provided by the embodiments of the disclosure, space utilization of the source wafer may be increased, the process of the package structure may be simplified, and the yield of the package structure may be improved. 
     Although some embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by one of ordinary skill in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.