Patent Publication Number: US-5838151-A

Title: Wireless load sharing for parallel power converters and method

Description:
FIELD OF THE INVENTION 
     This invention relates in general to the field of power supplies, in particular to pluralities of power supplies and more particularly to an improved, wireless technique for paralleling plural power supplies to provide increased power supply capacity. 
     BACKGROUND OF THE INVENTION 
     Load sharing is important for many electronic products which require multiple power supplies and/or which include a number of separate modules. It is desirable in such settings to avoid having unbalanced power supply current due to small differences in output voltage calibration. Use of a plurality of power supplies has advantages such as (i) use of a standardized module that may be combined as needed to meet a specific requirement, (ii) distribution of thermal loading/heat removal and (iii) enhanced reliability through redundancy. However, this requires some additional design in order to balance loading between paralleled supplies, without which some will &#34;hog&#34; more of the load and thus tend to dissipate more heat. Heating is, in turn, related to likelihood of failure. Load balancing is thus desirable in these settings. 
     Additionally, interconnections between power supplies typically suffer from lack of shielding and are susceptible to picking up and distributing electronic noise. Also, current loops may be established that contribute to both inefficiency and noise pickup. 
     Techniques for paralleling multiple power supplies generally utilize sensing circuitry that in turn requires additional wires between the multiple supplies, as described, for example, in &#34;Load Sharing with Paralleled Power Supplies&#34; by Bob Mammano and Mark Jordan, Sep. 1991, Unitrode Power Supply Design Seminar, SEM-800, pp. 2-1 to 2-4 (see, e.g., FIG. 1 and associated text). In some cases, a master unit having current controlling circuitry is coupled to other units that are controlled by the master unit. The advantages include lower cost for the controlled units, because they do not include current control circuitry, but this is achieved at the expense of the entire power supply system being dependent on operation of the master unit (see &#34;Paralleling Power Converters&#34; by A. Cioffi, Electrical Manufacturing, Jan. 1991, pp. 27-31). These concerns and others are discussed in U.S. Pat. No. 4,717,833, issued to K. Small and entitled &#34;Single Wire Current Share Paralleling of Power Supplies&#34; (Jan. 5, 1988). The above noted patents and articles are hereby incorporated herein by reference. 
     Thus, what is needed is a practical, economical method for paralleling a multiplicity of power supplies without incurring current hogging, without increasing susceptibility to power supply produced or system induced distributed noise, without adding complicated interconnections and preserving immunity to single point failures and no loss of efficiency. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram of a single power supply in accordance with the teachings of the instant invention; and 
     FIG. 2 is a graph of power supply output voltage versus output current in accordance with the teachings of the instant invention. 
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of power supply 10 in accordance with the teachings of the instant invention. Power supply 10 includes three major subassemblies: (i) power stage 11, (ii) power control circuit 15 and (iii) virtual resistance generator 25. 
     Power stage 11 comprises a multiplicity of functions operating to provide regulated output voltage on line 14 from unregulated supply voltage coupled via line 12. Power stage 11 is typically realized as an input filter, power switching transistors, power switching transistor drivers, power transformer, output power rectifiers, output filter, transient snubbers, house keeping power supply (internal power supply for circuits 17, 19), current sensing and generation of a signal on line 16 proportional to the output current. 
     Power control circuit 15 senses the output voltage, the outer control loop parameter, on line 14 via the inverting input to error amplifier 19. The reference signal non inverting input to error amplifier 19 is coupled via resistor 37 to the output of reference voltage generator 27 and via resistor 35 to the output of operational amplifier 29. Additionally, resistor 43 and capacitor 45 couple this node to ground, in effect dividing down and filtering the reference generator output. Resistors 37 and 43 are used to calibrate virtual resistance generator 25 by setting the initial level of the reference signal. Power control circuit 15 also includes comparator 17 having an inverting input coupled to the output of error amplifier 19 and a non inverting input coupled via line 16 to the effective output current sensing signal of power stage 11, the inner control loop parameter. The effective power supply output current sense signal on line 16 is equal to the output voltage from error amplifier 19. Error amplifier 19 then has an output signal with the same dynamics as the regulator control loop (i.e., is proportional to the power supply current) and this output signal is the input to the virtual output resistance generator 25, coupled via resistor 31. 
     Virtual resistance generator 25 usefully comprises resistors 31 and 33, which set the gain of operational amplifier 29. Resistors 39 and 41 divide the output of reference generator 27 to provide an offset level to the non inverting input of operational amplifier 29. These two functions calibrate the output voltage level and swing from amplifier 29 as a function of the power supply output current. Resistor 35 scales and adds output signal 29 to the portion of the output signal from reference generator 27 from the voltage divider comprising resistors 37 and 43, with the resulting combination reference signal being fed into the non inverting input of error amplifier 19 in power control circuit 15. This reference signal sets the nominal power supply output voltage and also sets the output voltage to sag as a function of the output current. The slope of the output voltage versus current curve is the virtual power supply output resistance as defined by the combination of the signals from reference generator 27, error amplifier 19 and operational amplifier 29. 
     When the output voltage on lead 14 is below a certain level defined by the combination of signals from virtual resistance generator 25 and error amplifier 19, a positive voltage swing is produced at the output of error amplifier 19. This larger error signal then requires a larger current sense signal on line 16 to operate comparator 17. The current sense signal on line 16 from power stage 11 is a ramp function of time, thus comparator 17 generates a wider output pulse at control input 13 of power stage 11 to provide more current to lead 14 and thereby increasing the voltage present on lead 14. Similarly, when the voltage on lead 14 exceeds a certain level, error amplifier 19 provides a negative voltage swing at the output of error amplifier 19, reducing the pulse width produced by comparator 17 and hence reducing the drive level to power stage 11. This results in less current being provided to lead 14 and reduces the output voltage accordingly. Thus, the voltage on lead 14 is tightly controlled as defined by virtual resistance generator 25 output and the feedback loop. 
     EXAMPLE 
     Table I below provides typical component values or art numbers for one realization of the circuit of FIG. 1. 
     
                       TABLE I                                                     
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TYPICAL COMPONENT VALUES AND                                              
PART NUMBERS FOR POWER SUPPLY CIRCUIT.                                    
Ref. No.       Value or Part Number &amp; Mfr.                                
______________________________________                                    
10             01-P36000U, Motorola,                                      
               Chandler, AZ                                               
17, 19         UC 1825, Unitrode, Merrimack,                              
               NH                                                         
               or MC 1825, Motorola, Austin                               
               TX                                                         
27             AD 586, Analog Devices,                                    
               Norwood, MA                                                
29             MC33072, Motorola, Austin TX                               
31             10 KΩ                                                
33             20 KΩ                                                
35             511 KΩ                                               
37             10 KΩ                                                
39             10 KΩ                                                
41             7.5 KΩ                                               
43             &#34;pen&#34;                                                      
45             1000 pF                                                    
46             10 KΩ                                                
47             24 KΩ (Selectable or trimmable)                      
______________________________________                                    
 
    
     A power supply built using the values and parts listed in Table I provided the measured results given below in FIG. 2, which is a graph of power supply output voltage versus output current in accordance with the teachings of the instant invention. This power supply provided between zero and ten amperes from an unregulated supply having a nominal voltage of 28 volts while maintaining an output voltage of 7.031+/-39 mV volts. 
     Circuit 10 advantageously uses existing error amplifiers 17, 19 to also sense output current magnitude. Circuit 10 also allows adjustment of V REF  to force the droop on the power supply output. 
     This concept has been implemented into a satellite payload panel approach which utilizes multiple parallel connected power converters connected to a 20 foot rectangular bus bar, with the physical locations of the power converter connections distributed over the length of the bar. The bus bar then feeds various loads which are also spread out over the length of the bar. For the case of seven parallel +5V power converters, with an output slope of -4 mV/A, all seven power converter load currents were within 0.45 A of one another. 
     Under heavy pulse loading conditions, the +5V secondary bus voltage remained within the specified +1 to -3% range, as it was designed for. In this case, the power converters incorporated remote voltage sensing to ensure that all power converters were reading the same output voltage, regardless of their physical location on the bus bar. Additionally, laser trimming was performed at the module level at heavy loading to eliminate all initial circuit component tolerances as well as to guarantee optimal load sharing at the heavy load currents, where it is needed most for reliability. 
     Thus, a power supply module for a distributed power supply system has been described which overcomes specific problems and accomplishes certain advantages relative to prior art methods and mechanisms. The improvements over known technology are significant. The expense, complexities, and high reliance on a single module are avoided. Similarly, current hogging and the attendant disequilibrium in load sharing and heating are avoided. 
     The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and therefore such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. 
     It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Accordingly, the invention is intended to embrace all such alternatives, modifications, equivalents and variations as fall within the spirit and broad scope of the appended claims.