Patent Publication Number: US-6699759-B2

Title: High density read only memory and fabrication method thereof

Description:
This application is a Division of nonprovisional application Ser. No. 09/894,002, filed Jun. 29, 2001, now U.S. Pat. No. 6,462,387. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to semiconductor manufacturing process and more particularly to a high density read only memory (HDROM) and fabrication method thereof. 
     BACKGROUND OF THE INVENTION 
     Semiconductor fabrication technology have known a rapid and a spectacular development leading from sub micron fabrication to deep-sub micron fabrication. The size of thus produced semiconductor device is even smaller. As a result, the size of chip is decreased and the number of chips formed on each wafer is increased. And in turn the fabrication cost of each chip is reduced as the number and operating speed of transistors on a chip are increased. The number of transistors is double every one and half year based on Morgan&#39;s theory. As such, memory size of an integrated circuit (IC) has increased from past several thousand bits per chip to current several ten million bits per chip. In the case of read only memory (ROM), there are ICs having 1 Giga-bit capacity available now. Currently, ROMs having 64 million-bit are the most popular one. 
     In view of this trend, ROM capacity and operating speed will be higher as time goes as required by electronic product manufacturers. Hence, it is obvious that high density high capacity ROMs are the main stream of development. It is also anticipated that high density ROMs will replace current semiconductor products as the dominant product in the near future. As such, most semiconductor manufacturers endeavor to develop such products. 
     Currently, a NAND gate based architecture is incorporated in each cell of existing HDROMs for decreasing the number of contacts. It is advantageous for decreasing the area of chip. It is disadvantageous, however that resistance of serially connected cells becomes large by incorporating such NAND gate architecture. As such, a RC delay is occurred due to increase of resistance value (R) of the serially connected cell. And in turn the speed of reading, writing, or erasing is slowed. Further, ROMs having such NAND gates are fabricated by utilizing Fowler-Nordheim tunneling or hot carrier writing principle. Hence, cells tend to over program, thus causing the number of electrons in floating gate to increase excessively. As a result, critical threshold voltage of the conventional ROM cell is increased beyond control which in turn causes the channel of cell to be cut off permanently. Hence, such conventional HDROMs are limited in electronic applications. Thus improvement exists. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a high density read only memory and fabrication method thereof. The method comprises the step of fabricating a plurality of spaced post transistors on a wafer by implanting and trench etching wherein each post transistor has four vertical surfaces with one of vertical surfaces as a short circuit junction between substrate and source and a read only memory (ROM) cell formed on each of the three remaining vertical surfaces. This can maintain a critical threshold voltage on transistors of ROM cells at the same level while there is a voltage drop between substrate and source thereof. Further, in the layout of ROM cells drains of ROM cells are alternately coupled together because a word line is shared by adjacent ROM cells. Therefore, the invention can fabricate three ROM cells in a single post transistor for storing three-bit data, thereby fabricating high density ROM cells. 
     The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross-sectional view of P+ and P− type semiconductor layers having different densities being epitaxially fabricated according to the invention; 
     FIGS. 2A and 2B are cross-sectional and top plan views of plurality of spaced post transistors formed on wafer by lithography and trench etching according to the invention, respectively. 
     FIG. 3 is a cross-sectional view of FIG. 2-1 post transistors after oxidized and CVD epitaxially processed according to the invention; 
     FIG. 4 is a cross-sectional view showing a first poly-silicon layer formed on FIG. 3 post transistors according to the invention; 
     FIG. 5 is a cross-sectional view showing two floating gates formed on two adjacent FIG. 4 post transistors according to the invention; 
     FIG. 6 is a cross-sectional view showing an ONO layer formed on FIG. 5 post transistors according to the invention; 
     FIG. 7 is a cross-sectional view along Y axis after control gate is defined in Y axis by performing a masking and lithography on ONO layer between FIG. 6 post transistors arranged in Y axis according to the invention; 
     FIG. 8 is a cross-sectional view along Y axis after control gate is formed in Y axis on remained ONO layer between FIG. 6 post transistors arranged in Y axis according to the invention; 
     FIG. 9 is a cross-sectional view along Y axis after a second oxide layer is formed on control gate arranged in Y axis by perfroming CVD epitaxy processing according to the invention; 
     FIG. 10 is a cross-sectional view along X axis after control gate is formed in X axis on ONO layer between post transistors arranged in X axis according to the invention; 
     FIG. 11 is a cross-sectional view along X axis after a first metal layer is defined by performing a masking and lithography on remained ONO layer between post transistors arranged in X axis according to the invention; 
     FIG. 12 is a cross-sectional view along X axis after control gate is formed on post transistors arranged in X axis according to the invention; 
     FIG. 13 is a cross-sectional view along X axis after drain contacts are formed by performing a masking and lithography on post transistors arranged in X axis according to the invention; 
     FIG. 14A is a cross-sectional view along X axis and FIG. 14B is a top plan view respectively for illustrating a layout with formed bit lines on drain of ROM cell and a second metal layer formed on post transistors arranged in X axis according to the invention. 
     FIG. 15A is a cross-sectional along X axis and FIG. 15B is a top plan view respectively for illustrating another layout with formed contacts on post transistors arranged in X axis by performing a masking an lithography according to the invention. 
     FIG. 16 is a cross-sectional view of ROM cell along X axis during the HDROM manufacturing process according to the invention; and 
     FIG. 17 is a circuit diagram incorporating three ROM cells formed on each post transistor according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A high density read only memory (HDROM) of the invention is fabricated by the following process: Fabricating a plurality of spaced post transistors on a wafer by implanting and trench etching wherein each post transistor has four vertical surfaces with one of vertical surfaces as a short circuit junction between substrate and source and a read only memory (ROM) cell formed on each of the three remaining vertical surfaces. That is, the invention can fabricate three ROM cells in a single post transistor for storing three-bit data. As described that read only memory cell having a high density feature will be called high density read only memory (HDROM) in a description of the specification thereafter. 
     Referring to the drawings and particularly to FIG. 1 where a preferred embodiment of the invention is shown wherein a high density arsenic (As) is implanted on a p type wafer. The p type wafer is doped by As ions to form a n+ type semiconductor layer  11  which is served as source  11  of HDROM of the invention. Then a chemical vapor deposition (CVD) (note that a physical vapor deposition (PVD) or a photon-induced chemical vapor deposition (PCVD) may be employed in other embodiments) or implanting is employed to epitaxially fabricate (or implant) a p type semiconductor layer  12  having a thickness of about 0.5 to 2 μm on the n+ type semiconductor layer  11 . In the invention after boron ions have been doped in the epitaxial process, doping density near n_type semiconductor layer  11  will be higher than that of other areas. The doping density will be decreased as the epitaxial thickness reaches about 0.2 to 0.4 μm. Hence, p+ and p− type semiconductor layers  121  and  122  are formed on the n+ type semiconductor layer  11 . Then p+ and p− type semiconductor layer  121  and  122  are formed as substrate  121  and channel  122  of ROM cell respectively. Then fabricates a plurality of spaced post transistors  13  on the p+ and p− type semiconductor layer  121  and  122  by lithography and trench etching wherein each post transistor  13  has four vertical surfaces (FIG.  2 A). Then high density phosphor (P) ions are implanted on post transistors  13  so as to dope P ions on the surface of p− type semiconductor layer  122  to form a n+ type semiconductor layer  14  on the top of each post transistor  13 . n+ type semiconductor layer  14  is served as drain of HDROM cell of the invention. In the plan view of FIG. 2B, such formed transistors  13  are arranged in a matrix shape with each post transistor  13  equally spaced apart from the adjacent post transistor  13  in either X axis or Y axis. 
     In the epitaxial process, doping density of boron ions near source (i.e. n+ type semiconductor layer)  11  in p type semiconductor layer  12  is higher than that of other areas due to the following reasons: 
     (1) In the ROM cell manufacturing process, if boron ions on some channels  122  and substrate  121  have higher density, after ROM cells are processed in an anti-punch-through process the punch-through between the drain  14  and source  11  may not occur when a lower punch-through voltage is applied on ROM cells. 
     (2) Since a high voltage will apply on drain  14  of ROM cell low density boron ions near channel of drain  14  ROM cells may have a higher junction breakdown voltage when drain  14  of ROM cell is being programmed or erased. 
     (3) Since boron ions of ROM cell have a higher density near channel of source  11  the threshold voltage on the channel will be high. To the contrary, since boron ions of ROM cell have a lower density near another channel of drain  14  the threshold voltage on the channel will be low. Hence, there are two different levels of threshold voltage on the same channel. When a predetermined voltage is applied on gate to turn on the channel, a source-side-injection will occur to generate many gate hot carriers. As a result, the program efficiency and speed of electrons will be much higher than that of conventional stacked ROM cells. 
     (4) Typically, a Fowler-Nordheim tunneling or hot carrier writing principle is utilized in the conventional stacked ROM cells. Hence, cells tend to over program, thus causing the number of electrons in floating gate to increase excessively. As a result, critical threshold voltage of the conventional ROM cell is increased beyond control which in turn causes the channel of cell to be cut off permanently. In contrast in the invention p type semiconductor device  12  has two different density portions after implanted, thus causing critical voltage near source  11  to be higher for turning off the channel. As a result, an over erasure effect is eliminated. 
     Also, lithography and trench etching utilized by the invention to form post transistors  13  on semiconductor devices may cause an over etching. Hence, a space  131  is defined by four adjacent post transistors  13  after etching (FIG.  2 A). The size of space  131  is suitable to fabricate floating gates, control gate, and insulated oxide of the invention therein. Hence, the width of space  131  is required to be equal to or larger than a minimum width for disposing two floating gates, a control gate, and insulated layers. 
     Moreover, an oxidation process is performed on above semiconductor devices at a temperature about 800 to 950° C. by the invention so as to grow a first oxide layer  15  thereon (FIG.  3 ). The thickness of oxide layer  15  is about 70 to 120 Å. Such first oxide layer  15  is used as tunnel oxide of ROM cell in the invention. The quality of first oxide layer  15  determines the cycling endurance of ROM cell, the date retention of electrons in floating gate, and efficiency of programming and erasing electrons. Further, the oxidation also has the following meanings: 
     (1) Poly-silicon may be crystallized again to from a single crystal in a high temperature manufacturing process; 
     (2) Defect occurred in implanting in above high temperature manufacturing process may be repaired and doping in the implanting may be made active. 
     Then the invention utilize CVD epitaxial technique to grow a first poly-silicon layer  16  on first oxide layer  15 . Referring to FIG. 3 again, the thickness of first poly-silicon layer  16  is about 200 to 300 Å. First poly-silicon layer  16  is served as floating gate  16  on ROM cell in the invention. Then etch away a portion of first poly-silicon layer  16  so that there is no first poly-silicon layer  16  remained on the top of post transistor  13 . Then a photoresist  80  is coated on post transistors  13  and first poly-silicon layer  16  (FIG.  4 ). A masking  81  and lithography are employed to define floating gates on first poly-silicon layer  16 . A trench etching is then performed to etch away undesired poly-silicon and photoresist  80 . Referring to FIG. 5, two floating gates  161  are formed between two adjacent post transistors  13 . Then CVD epitaxial technique is alternately employed to grow oxide-nitride-oxide (ONO) layers  17  on semiconductor devices. ONO layers  17  remained on post transistors  13  are etched away to form desired ONO layers  17  (FIG.  6 ). In subsequent processes, such ONO layers  17  may be used as an insulation layer between later formed second poly-silicon layer and floating gate  161 . In the invention a low temperature manufacturing process is employed to grow ONO layers  17  because doping density in ROM cells may be deformed in a high temperature manufacturing process. 
     Note that the whole surface of wafer is the object to be sequentially processed in previous processes by the invention. Hence, after ONO layers  17  have been formed the configuration of one side of post transistors  13  (e.g., viewed along X axis) is the same as that of the other side of post transistors  13  (e.g., viewed along Y axis). However, in the following manufacturing processes of the invention the configuration of one side of semiconductor devices (e.g., viewed along X axis) is not the same as that of the other side of semiconductor devices (e.g., viewed along Y axis). Hence, the difference between the configuration as viewed along X axis and that as viewed along Y axis will be described in the following specification. 
     Referring to FIG. 7, photoresist  80  is coated on semiconductor devices in the invention. Then a masking  81  and lithography are employed to define control gate in Y axis on ONO layers  17  which are located in post transistors  13  along Y axis. Referring to FIG. 8, a trench etching is then performed to etch away undesired ONO layers  17  and photoresist  80 . Hence, a space is formed in ONO layers  17  for fabricating control gate. Then CVD epitaxial technique is employed to grow a second poly-silicon layer  18  on semiconductor device and ONO layers. Referring to FIG. 8, the second poly-silicon layer  18  is served as control gate  18  in Y axis of ROM cells by the invention. Second poly-silicon layer  18  is extended along X axis to connect ROM cells in X axis together. As an end, a word line W is formed of ROM cells. Then etch away undesired second poly-silicon layer  18  on semiconductor devices. Then CVD epitaxial is employed to grow a second oxide layer  19  on the whole semiconductor device. The cross-section of such ROM cells along Y axis is shown in FIG.  9 . 
     Then a masking and a lithography are employed to alternately define control gate in X axis on ONO layers  17  which are located in post transistors  13  along X axis. Then trench etching is performed to etch away undesired ONO layers  17  and photoresist  80 . Hence, a space is alternately formed in ONO layers  17  for fabricating control gate. Then CVD epitaxial technique is employed to grow a second poly-silicon layer  18  on ONO layers  17  as control gate  18  in X axis of ROM cells. The cross-section thereof along X axis is shown in FIG.  10 . Referring to FIG. 11, etch away undesired second poly-silicon layer  18  on semiconductor devices. Then CVD epitaxial is employed to grow a third oxide layer  20  on the whole semiconductor device. In subsequent processes third oxide layer  20  may be used as an insulation layer between later formed first metal layer and control gate  18 . The cross-section of such ROM cells along X axis is shown in FIG.  11 . 
     Then a masking  81  and a lithography are employed by the invention to define a short circuit region between substrate  121  and source  11  of ROM cell in post transistors  13  along X axis. In other words, a trench etching is performed to over etch the short circuit region on portions of ONO layers  17  where control gate  18  is not formed in post transistors  13  along X axis. After, the short circuit region is over etched to source  11  as shown in FIG. 12, a first metal layer  21  is coated thereon. As such, a short circuit is formed between substrate  121  and source  11  of ROM cells along X axis. Finally, a trench etching is employed to etch away undesired metal layer  21 . The cross-section thereof along X axis is shown in FIG.  12 . 
     Thereafter a high density plasma (HDP) is employed by the invention to grow a fourth oxide layer  22  on the whole semiconductor device as shown in FIG.  13 . In subsequent processes fourth oxide layer  20  may be used as an insulation layer between later formed second metal layer and first metal layer  21 . Then coat a photoresist  80  on fourth oxide layer  20 . Further, a masking  81  and a lithography are employed to alternately define a drain  14  of ROM cell adjacent to a post transistor of first metal layer  21 . In FIG. 13, trench etching is employed to etch away undesired oxide layers  15 ,  19 ,  20 , and  22  on drain  14  and photoresist  80 . Then coat a second metal layer  23  on the portion left by above removed oxides. Referring to FIG. 14A, second metal layer  23  is coupled to drains  14  along Y axis so as to serve as a bit line B 1  of ROM cells.  14 A is a cross-sectional view along X axis and FIG. 14B is a top plan view for illustrating a layout of ROM cells respectively. It is important to note that bit line B 1  is extended along Y axis to be alternately formed on corresponding drain  14  of post transistor. As viewed by post transistors bit line B 1  are alternately coupled to corresponding drains  14  along Y axis. 
     Thereafter a CVD epitaxial technique is employed to grow a fifth oxide layer  24  on the whole semiconductor device as shown in FIG. 15-1. In subsequent processes fifth oxide layer  24  may be used as an insulation layer between later formed third metal layer and bit line. Then coat a photoresist  80  on fifth oxide layer  24 . Further, a masking  81  and a lithography are employed to alternately define the other drain  14  of ROM cell adjacent to the other post transistor of first metal layer  21 . In FIG. 15A, trench etching is employed to etch away undesired oxide layers  15 ,  19 ,  20 ,  22  and  24  on the other drain  14  and photoresist  80 . Then coat a third metal layer  25  on the portion left by above removed oxides. Third metal layer  25  is coupled to the other drains  14  along Y axis so as to serve as the other bit line B 2  of ROM cells. FIG. 15A is a cross-sectional view along X axis and FIG. 15B is a top plan view for illustrating a layout of ROM cells respectively. It is also important to note that bit line B 2  is extended along Y axis to be alternately formed on the corresponding other drain  14  of post transistor. As viewed by post transistors bit lines B 1  are alternately coupled to the corresponding other drains  14  along Y axis. 
     Finally, a protective layer  30  is coated on the whole semiconductor device for forming the HDROM of the invention. FIG. 16 is a cross-sectional view along X axis respect to ROM cells disposed in X axis wherein an insulation layer formed by oxides  19 ,  20 ,  22  and  24  is labeled by numeral  50 . 
     By utilizing above manufacturing process of the invention, it is possible to fabricate three ROM cells Q 1 , Q 2  and Q 3  in a single post transistor for storing three-bit data. An equivalent circuit of above ROM cells is shown in FIG.  17 . The operation of the ROM cells is as follows in conjunction with the layout of ROM cells shown in FIG.  15 B: 
     (1) In writing data into a ROM cell Q 1 , a high voltage (e.g., 10 volt) is applied to word line W to turn on ROM cell Q 1  and maintain word line W at the same high voltage (e.g., 10 volt). Then above source-side-injection may be employed to inject electrons into floating gates  161  of ROM cells for completing data writing. 
     (2) In erasing data from ROM cell Q 1 , a negative high voltage (e.g., −5 volt) is applied to word line W to maintain bit line B 1  at a high voltage (e.g., 10 volt). Then above Fowler-Nordheim tunneling may be employed to inject electrons of ROM cells into drains  14  of ROM cells for completing data erasing. Alternatively, apply a high voltage (e.g., 10 volt) to source  11 . Then above Fowler-Nordheim tunneling may be employed to inject electrons of floating gates  161  into sources  11  for completing data erasing. 
     (3) In reading data from a ROM cell Q 1 , a low voltage (e.g., 3 volt) is applied to word line W and bit line B 1  is maintained at the same voltage (e.g., 3 volt). Hence, it is possible to determine whether a logical “1” or “0” value represented by electrons is stored in floating gate  161  of ROM cell Q 1  by reading a current value from drain  14 . 
     In brief, each post transistor of the invention is shared by three ROM cells. Hence, the capacity of memory thus fabricated is three times larger than that of conventional memory. Further, post transistors are of high density, thus effectively reducing occupied area of source contacts. As a result, the size of ROMs is reduced significantly, resulting in an increase of the number of ROMs fabricated on a single wafer. 
     While the invention has been described by means of specific embodiments, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope and spirit of the invention set forth in the claims.