Patent Publication Number: US-6338157-B1

Title: Threshold element and method of designing the same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method of designing a threshold element, and to a threshold element designed using such a method. In particular, the invention is adapted to develop a threshold element based on an output wired CMOS (complementary metal oxide semiconductor) logic. 
     2. Description of the Prior Art 
     During the last 40 years, the tides of interest to threshold and majority logics rose and waned periodically. This was caused, on the one hand, by new circuit elements of threshold nature and, on the other hand, by the tasks which used threshold functions to specify functional blocks. There are a lot of such tasks, for example, those of reliability, threshold coding, AD/DA-conversion, filtration, etc. Of special note are neural networks, the behavior of formal neutrons in which is described by threshold functions, starting from the classic work by McCulloch and Pitts. 
     A threshold function is defined as              y   =       Sign        (         ∑     i   =   1     n            w   i          x   i         -   T     )       =     {         1               if                     ∑     i   =   1     n            w   i          x   i           -   T     ≥   0                          0             if                     ∑     i   =   1     n            w   i          x   i           -   T     &lt;   0                       (   1   )                         
     where w i  is the weight of the i-th input and T is the threshold. Thus, a threshold element should consist of an adder and a threshold comparator. 
     Recently, new circuits of CMOS threshold elements have been suggested and studied. A νCMOS is based on the CMOS-inverter with floating gate and capacity inputs. Another CMOS is based on output wired CMOS inverters. The latter are the subject of the present specification. 
     FIG. 1 illustrates the structure of a threshold element consisting of output wired CMOS inverters. The threshold element comprises inverters  1 ,  2 , . . . , n having inputs x 1 , x 2 , . . . , x n . Outputs of the inverters  1 ,  2 , . . . , n are wired. The output voltage Vout appears at the wired outputs. A decision inverter  10  converts the output voltage Vout into binary data which is the final result  y . The threshold value of the decision inverter  10  is determined in proper manner to truly binary-code the result of the majority. The inverters  1 ,  2 , . . . , n realize an adder, while the decision inverter  10  realizes a comparator, in this circuit. The threshold element allows outputs from the inverters  1 ,  2 , . . . , n to cause the tug of war, in which the final result  y  becomes “1” if more binary code “1” is in put and becomes “0” if more binary code “0” is input. Thus, the inverters as a whole establish a majority circuit. 
     Since threshold functions are a subset of Boolean functions, any threshold function can naturally be represented by a superposition of operations (circuit elements) of any functionally full basis. The question is whether circuits can be built that would implement threshold functions in a simpler way than the traditional circuits do. If the answer is positive, it would be possible to simplify the implementations of arbitrary logic functions having a bigger number of basic elements. In CMOS-implementation, every character entry corresponds to two (p- and n-) transistors. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a threshold element capable of providing the function blocks with transistors less than two for each of the inputs, and a method of designing the same. 
     According to the present invention, there is provided a method of designing a threshold element, comprising: converting to the form including a ratio related to p- and n-transistors a threshold function which outputs the result of comparison between a predetermined threshold value and the sum of weighted inputs; and allocating the inputs to the p- and n-transistors in accordance with the ratio, so as to design a threshold element corresponding to the threshold function. 
     The ratio could be a parameter to determine which of p- and n-transistors more affects on the output when the p- and n-transistors are turned on, since the ratio is related to the p- and n-transistors. In other words, the ratio could be a parameter to determine the condition of the above-mentioned tug of war. 
     A threshold element of the present invention can be designed using the above-mentioned designing method. When a threshold function is converted to the form including a ratio related to p- and n-transistors, respective inputs are ti allocated to the p- and n-transistors in accordance with the ratio. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiment in conjunction with the accompanying drawings, wherein: 
     FIG. 1 illustrates a threshold element comprising conventional output wired CMOS inverters; 
     FIG. 2 illustrates the background leading to a method of designing a threshold element in accordance with an embodiment of the present invention; 
     FIG. 3 illustrates a threshold element realizing a certain threshold function in accordance with the theorem which the present inventor has found; 
     FIG. 4 illustrates the structure of the threshold element corresponding to xyz arithmetic; 
     FIG. 5 illustrates the structure of the threshold element corresponding to x(y+z) arithmetic; 
     FIG. 6 illustrates the structure of the threshold element corresponding to x+y+z arithmetic; 
     FIG. 7 illustrates the structure of the threshold element corresponding to xy{overscore (z)} arithmetic; 
     FIG. 8 illustrates the structure of the threshold element corresponding to x{overscore (yz)} arithmetic; 
     FIG. 9 illustrates the structure of the threshold element corresponding to {overscore (xyz)} arithmetic; 
     FIG. 10 illustrates the structure of the threshold element corresponding to xyz+x{overscore (yz)} arithmetic; 
     FIG. 11 illustrates the structure of the threshold element corresponding to {overscore (x)}yz+{overscore (xyz)} arithmetic; 
     FIG. 12 illustrates the structure of the threshold element corresponding to xyz+{overscore (xyz)} arithmetic; 
     FIG. 13 illustrates the structure of the threshold element corresponding to a two-input C-element; 
     FIG. 14 illustrates the structure of the threshold element corresponding to a three-input C-element; 
     FIG. 15 illustrates the structure of the threshold element corresponding to an n-input C-element; and 
     FIG. 16 illustrates the structure of the threshold element corresponding to a full adder. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2 illustrates the background leading to a designing method of the present invention. A p-transistor or p-channel MOSFET  20  and an n-transistor or n-channel MOSFET  21  are serially connected between a power supply and a ground. The gate  22  of the p-transistor  20  is grounded, and the gate  23  of the n-transistor  21  is pulled up to the power supply. In the static mode where both transistors  20 ,  21  are completely open, the voltage V at the drains of the p- and n-transistors  20 ,  21  is determined by the ratio α=βn/βp where βp and βn are a drain current coefficient or a beta value of p- and n-transistors  20 ,  21  respectively. The voltage V drops when α increases and grows when α declines. Assuming that p- and n-transistors take the same characteristic in the respective inverters  1 ,  2 , . . . , n in the conventional circuit shown in FIG. 1,        α   =         ∑     i   =   1     n          x   i           ∑     i   =   1     n            x   _     i                         
     can be obtained. The threshold function of the majority circuit shown in FIG. 1 can simply be expressed by 
     
       
           y =Sign(α−1)  (2) 
       
     
     because                Sign        (     α   -   1     )       =     Sign        (         ∑     i   =   1     n          x   i       -       ∑     i   =   1     n            x   _     i         )                   =     Sign        (         ∑     i   =   1     n          x   i       -       ∑     i   =   1     n          (     1   -     x   i       )         )                   =     Sign        (         ∑     i   =   1     n          x   i       -     n   2       )                             
     can be established. The ratio α is the principle to a threshold element of the present invention. 
     We will explain below the theorem which the present inventor has found to reduce the number of transistors implementing a threshold circuit. 
     Theorem 
     Any threshold function of expression (1) can be represented as follows so as to include a ratio,                F        (   X   )       =     Sign        (           ∑     i   ∉   S              w   i          x   i             ∑     i   ∈   S                w   _     i          x   i           -   1     )               (   3   )                         
     where S is a certain subset of indexes  i , such that 
     
       
         Σ iεS   w   i   =T   (4) 
       
     
     Proof 
     Since x i  is either of “0” or “1”, the following expression                  ∑     i   =   1     n            w   i          x   i         -   T           (   5   )                         
     takes a discrete value in relation to variable combinations of x i . Taking a value  a  closest and larger than “0” among the discrete values, a threshold function never loses its function even if T is replaced with (T−a). This operation allows set  S  of the index  i  to meet the expression (4). 
     If a set  S  of the index  i  meets the expression (4), then the expression (5) may be transformed as follows:                    ∑     i   =   1     n            w   i          x   i         -   T     =         ∑     i   ∉   S              w   i          x   i         -     (     T   -       ∑     i   ∈   S              w   i          x   i           )                   =         ∑     i   ∉   S              w   i          x   i         -       ∑     i   ∈   S              w   i          (     1   -     x   i       )                       =         ∑     i   ∉   S              w   i          x   i         -       ∑     i   ∈   S              w   i            x   _     i                         F        (   X   )       =     Sign        (         ∑     i   =   1     n            w   i          x   i         -   T     )                   =     Sign   (         ∑     i   ∉   S              w   i          x   i         -       ∑     i   ∈   S              w   i            x   _     i           )                 =     Sign        (           ∑     i   ∉   S              w   i          x   i             ∑     i   ∈   S              w   i            x   _     i           -   1     )                             
     This is the end of the proof. However, the above expression can be rearranged to the following expression.          F        (   X   )       =     1   -     Sign        (           ∑     i   ∈   S              w   i            x   _     i             ∑     i   ∉   S              w   i          x   i           -   1     )                         
     where S is a certain subset of indexes  i , such that            ∑     i   ∈   S            w   i       =     T   -   1                     
     This rearrangement may be employed in designing a circuit of a three-input C-element as described later. 
     FIG. 3 illustrates a threshold element based on a certain threshold function of the expression (1). As shown in FIG. 3, the threshold element comprises p-transistors  30 ,  31 , . . . , 3k for receiving x i  for the index  i  included in the above-mentioned set  S  defined by the expression (4), and n-transistors  40 ,  41 , . . . , 4m for receiving x i  for the index  i  outside the set  S . All of the drains from the p- and n-transistors are commonly connected. A decision inverter  50  compares the voltage Vout at the connected drains with a threshold value T so as to output the final result  y . 
     Taking account of the ratio α in the expression (2), the numerator of the fractional component in the expression (3) is considered to correspond to the n-transistors, and the denominator of the fractional component is likewise to the p-transistors. This tells that a single transistor covers a single input. Accordingly, the threshold element of FIG. 3 can be constructed with a half of transistors employed in a conventional threshold element of output wired CMOS inverters shown in FIG. 1 if the decision inverter  50  is neglected. 
     The utilization of the above-mentioned designing method allows a threshold element of a three-input Boolean calculation such as xyz, x(y+z), xy+yz+zx, x+yz, and x+y+z to be realized with four transistor and a single inverter, namely, six transistors in total. 
     xyz Arithmetic 
     A Boolean calculation of xyz can be expressed by a threshold function, F=Sign(x+y+z−3), which may be rearranged to        F   =     Sign        (       ɛ       x   _     +     y   _     +     z   _         -   1     )                       
     where ε is a transistor of a smaller beta value, which is called a “weak transistor” hereinafter. It is adapted to prevent the floating of the output voltage Vout and brought in for convenient designing. It should be noted that transformation can be effected to the threshold function in variable manners. 
     FIG. 4 illustrates a threshold element corresponding to xyz implementation. The x-, y- and z-inputs are connected to the bases of p-transistors  100 ,  101 ,  102  of the same beta value. The drains of p-transistors  100 ,  101 ,  102  are commonly connected to the drain of an n-transistor  103  corresponding to a weak transistor ε which keeps open. Four transistors  100 - 103  form an NAND-gate  104 . The analog output voltage Vout appears at the connected drains of four transistors  100 - 103 . A decision inverter  105  is disposed at the stage subsequent to the NAND-gate  104  so as to binary-code the output voltage Vout. The whole circuit forms an AND-gate  106 . 
     x(y+z) Arithmetic 
     A Boolean calculation of x(y+z) can be expressed by a threshold function, F=Sign(2x+y+z−3), which may be rearranged to the following expression.        F   =     Sign        (         z   +   ɛ         2                   x   _       +     y   _         -   1     )                       
     FIG. 5 illustrates a threshold element corresponding to x(y+z) implementation. The x- and y-inputs are connected to the bases of p-transistors  110 ,  111 , while the z-input is connected to the base of an n-transistor  112 . The drains of p- and n-transistors  110 - 112  are commonly connected to the drain of an n-transistor  113  corresponding to the weak transistor ε which keeps open. The beta value of the p-transistor  110  which receives the x-input is set at twice the beta value of the other transistors  111 ,  112  so as to reflect the weight of the transistor  110 . The output voltage Vout appears at the connected drains of four transistors  110 - 113  and is supplied to a decision inverter  114 . 
     xy+yz+zx Arithmetic 
     This is a three-input majority circuit. A Boolean calculation of xy+yz+zx can be expressed by a threshold function, F=Sign(x+y+z−2), which may be rearranged to the following expression.        F   =     Sign        (         z   +   ɛ         x   _     +     y   _         -   1     )                       
     The structure of the corresponding threshold element is the same as of FIG.  5 . Here, the beta value of the n-transistor  110  which receives the x-input is set at the same level as the other transistors  111 ,  112 . 
     x+y+z Arithmetic 
     A Boolean calculation of x+y+z can be expressed by a threshold function, F=Sign(x+y+z−1), which may be rearranged to the following expression.        F   =     Sign        (         y   +   z   +   ɛ                    x   _         -   1     )                       
     FIG. 6 illustrates a threshold element corresponding to x+y+z implementation. The x-input is connected to the base of a p-transistor  120 , while the y- and z-inputs are connected to the bases of n-transistors  121 ,  122 . The drains of the p- and n-transistors  120 - 122  are commonly connected to the drain of an n-transistor  123  corresponding to the weak transistor ε which keeps open. Four transistors  120 - 123  form an NOR-gate  124  having analog output. The output voltage Vout appears at the connected drains of four transistors  120 - 123 . A decision inverter  125  is disposed at the stage subsequent to the NOR-gate  124  so as to binary-code the output voltage Vout. The whole circuit forms an OR-gate  126 . 
     x+yz Arithmetic 
     A Boolean calculation of x+yz can be expressed by a threshold function, F=Sign(2x+y+z−2), which may be rearranged to the following expression.        F   =     Sign        (         y   +   z   +   ɛ       2                   x   _         -   1     )                       
     The structure of the corresponding threshold element is the same as of FIG.  6 . Here, the beta value of the p-transistor  120  which receives the x-input is set at twice the beta value of the other transistors  121 ,  122 . 
     The description has been made to five examples of Boolean calculation circuits. According to the present invention, a three-input Boolean calculation circuit can be formed with a combination of transistors equal to or less than eleven and inverters equal to or less than two, namely, transistors equal to or less than fifteen in total. A three-input Boolean calculation may be established by a combination of any of four bases such as xyz, xy{overscore (z)}, x{overscore (yz)}, and {overscore (xyz)}, so that the following examples can be implemented. 
     xyz Arithmetic 
     As described above, the threshold element of FIG. 4 corresponds to xyz implementation. Six transistors are used in total. As of {overscore (xyz)}, the threshold function can be expressed by F=1−Sign(x+y+z−3), so that an inverter may be added to the later stage of the AND-gate  106  of FIG.  4 . 
     xy{overscore (z)} Arithmetic 
     FIG. 7 illustrates a threshold element corresponding to this logic. This can be implemented with the z-input of FIG. 4 inverted by an inverter  130 . Eight transistors are used in total. The AND-gate  106  in FIG. 4 is also used in FIG.  7 . The threshold function may be expressed by F=Sign(x+y+{overscore (z)}−3). 
     Since          xy                   z   _       _                   
     can be expressed by F=1−Sign(x+y+{overscore (z)}−3), the corresponding threshold element may be implemented by inserting an inverter after the AND-gate  106  in FIG.  7 . 
     x{overscore (yz)} Arithmetic 
     Since a Boolean calculation of x{overscore (yz)} is equal to              x   _     +   y   +   z     _     ,                   
     the corresponding threshold function may be expressed by F=Sign(x+{overscore (y)}+{overscore (z)}−3)=1−Sign({overscore (x)}+y+z−1). FIG. 8 illustrates a circuit utilizing the OR-gate  126  in FIG.  6 . When the OR-gate  126  is used, the x-input is inverted by an inverter  131  and the output from the OR-gate  126  is inverted by an inverter  132 . Ten transistors are used in total. 
     Since          x                   y   _                     z   _       _                   
     can be expressed by F=1−Sign(x+{overscore (y)}+{overscore (z)}−3), the corresponding threshold element maybe implemented by inserting an inverter after the inverter  132  in FIG.  8 . 
     {overscore (xyz)} Arithmetic 
     Since a Boolean calculation of {overscore (xyz)} is equal to            x   +   y   +   z     _     ,                   
     the corresponding threshold function may be expressed by F=Sign({overscore (x)}+{overscore (y)}+{overscore (z)}−3)=1−Sign(x+y+z−1). FIG. 9 illustrates a circuit utilizing the OR-gate  126  in FIG.  6 . When the OR-gate  126  is used, the output from the OR-gate  126  is inverted by an inverter  133 . Eight transistors are used in total. 
     Since            x   _                     y   _                     z   _       _                   
     can be expressed by F=1−Sign({overscore (x)}+{overscore (y)}+{overscore (z)}−3), the corresponding threshold element may be implemented by adding an inverter after the inverter  133  in FIG.  9 . 
     xyz+x{overscore (yz)} Arithmetic 
     FIG. 10 illustrates a circuit of xyz+x{overscore (yz)} implementation. First, A=x{overscore (yz)} is made. 
     Since          A   =         x   _     +   y   +   z     _       ,                   
     the x-input of the NOR-gate  124  is inverted by an inverter  139 . This is the first stage of the circuit. The threshold function would be: The x-, y- and z-inputs are respectively connected to the drains                    F   =     Sign        (     xyz   +   A   -   1     )                   =     Sign        (     x   +   y   +   z   +     3      A     -   3     )                   =     Sign        (           3      A     +   ɛ         x   _     +     y   _     +     z   _         -   1     )                     (   6   )                         
     of p-transistors  140 ,  141 ,  142  at the second stage. The logic A is connected to the drain of an n-transistor  143  in parallel with a weak n-transistor  144  which keep open. The beta value of the n-transistor  143  which receives the logic A is set at thrice the beta value of the other transistors  140 - 142 . The drains of five transistors  140 - 144  are commonly connected, and the output voltage Vout appears at the connected drains. A decision inverter  145  is disposed after the drains, so that the whole second stage forms a composite circuit  146  corresponding to the expression (6). 
     The input A to the composite circuit  146  is an analog signal. The proper operation of the circuit  146  has been confirmed by circuit simulation if the characteristic of transistors are appropriately managed. Thirteen transistors are used in total. 
     Since          xyz   +     x                   y   _          z   _         _                   
     can be expressed by F=1−Sign(x+y+z+3x{overscore (yz)}−3), the corresponding threshold element may be implemented by adding an inverter after the circuit in FIG.  10 . Fifteen transistors are required in total. 
     {overscore (x)}yz+{overscore (xyz)} Arithmetic 
     The corresponding threshold function may be expressed by F=Sign({overscore (x)}yz+{overscore (xyz)}−1), a circuit of which is illustrated in FIG.  11 . The circuit eliminates the inverter  140  of FIG. 10 for inverting the x-input at the first stage, while it includes an inverter  150  for inverting the x-input at the second stage. Thirteen transistors are used in total. 
     Since                x                _        yz     +       x   _                     y   _          z   _         _                   
     can be expressed by F=1−Sign({overscore (x)}+y+z+3{overscore (xyz)}−3), the corresponding threshold element may be implemented by adding an inverter after the circuit in FIG.  11 . 
     xyz+{overscore (xyz)} Arithmetic 
     The corresponding threshold function may be expressed by F=Sign(xyz+{overscore (xyz)}−1), a circuit of which is illustrated in FIG.  12 . The circuit simply eliminates the inverter  140  of FIG. 10 for inverting the x-input at the first stage. Eleven transistors are used in total. 
     Since            x                 yz     +       x   _                     y   _          z   _         _                   
     can be expressed by F=1−Sign(x+y+z+3{overscore (xyz)}−3), the corresponding threshold element may be implemented by adding an inverter after the circuit in FIG.  12 . 
     C-element 
     The present invention may be applied to the types of calculation other than simple Boolean calculations. FIG. 13 illustrates the structure of a circuit called a two-input C-element with x- and y-inputs. C-elements are widely used as synchronizing devices in asynchronous circuits. It is regarded as a majority circuit with hysteresis. When C=0 in a two-input C-element, the x- and y-inputs both reaching “1” allows C=1. On the other hand, when C=1, the x- and y-inputs both coming to “0” allows C=0. The behavior of a two-input C-element is specified by a threshold function:          C        (     x   ,   y     )       =       Sign        (     x   +   y   +   C   -   2     )       =     Sign        (         C   +   ɛ         x   _     +     y   _         -   1     )                         
     Accordingly, the x- and y-inputs are connected to the bases of p-transistors  200 ,  201 , respectively. The drains of a weak n-transistor  202  which keeps open and an n-transistor  203  which receives the output C at the base are commonly connected to the drains of the p-transistors  200 ,  201 . The output voltage Vout appears at the connected drains. The output voltage Vout is supplied to a decision inverter  204  so as to provide a target C. The two-input C-element can be implemented with six transistors, while the similar implementation of a two-input C-element in a CMOS circuitry requires eight transistors. 
     FIG. 14 illustrates the structure of a three-input C-element with x-, y- and z-inputs. When C=0 in this element, the x-, y- and z-inputs all reaching “1” allows C=1, while the x-, y- and z-inputs all coming to “0” allows C=0 when C=1. The behavior of a three-input C-element is specified by a threshold function:          C        (     x   ,   y   ,   z     )       =       Sign        (     x   +   y   +   z   +     2      C     -   3     )       =     1   -     Sign        (           x   _     +     C   _         y   +   z   +   C       -   1     )                           
     Accordingly, the x-input and output C are connected to the bases of p-transistors  210 ,  211 , respectively. The y- and x-inputs and output C are connected to the bases of n-transistors  212 ,  213 ,  214 , respectively. All drains of n- and p-transistors  210 - 214  are commonly connected to form the output voltage Vout. Since either of p-transistor  211  or n-transistor  214  should inevitably open, a weak transistor is not necessary to keep the level of the output voltage Vout. The output voltage Vout is supplied to a decision inverter  215  so as to give a target C. The three-input C-element can be implemented with seven transistors, while the similar implementation of a three-input C-element in a conventional CMOS circuitry requires ten transistors. 
     FIG. 15 illustrates the structure of an n-input C-element. The corresponding threshold function can be generalized as:          C        (   X   )       =     1   -     Sign        (             C   _            ∑     i   =   1       n   -   1              x   _     i         +     0.5                     x   _     n             C          ∑     i   =   1       n   -   1            x   i         +     0.5                   x   n           -   1     )                         
     Accordingly, the x 1 - to x n -inputs are connected to p-transistors  151 - 15   n  and n-transistors  161 - 16   n . The drains of all the p-transistors  151 - 15 (n−1) are commonly connected while the drains of all the n-transistors  161 - 16 (n−1) are commonly connected. 
     A p-transistor  170  and an n-transistor  171  are serially connected between the drains of the p- and n-transistors  15 (n−1),  16 (n−1) corresponding to the x n−1 -input. The drains of the p- and n-transistors  170 ,  171  are connected to the drains of the p- and n-transistors  15 n,  16 n corresponding to the x n -input, which in turn are connected to a decision inverter  180 . The feedback from the output of the decision inverter  180  is connected to the drains of the serially connected p- and n-transistors  170 ,  171 . When C=1 in the n-input C-element, all inputs assuming “0” allows C=0, while all inputs reaching “1” allows C=1 when C=0. 
     Full Adder 
     FIG. 16 illustrates a threshold element of a full adder as another example. The full adder receives a carrier C i−1  from the ahead stage, and sums x i - and y i -inputs, to give the sum σ i  and the carrier C i . Threshold representation of a full adder is:                        C   i     =     maj        (       x   i     ,     y   i     ,     C     i   -   1         )         ;                   C   _     i     =     Sign        (           C     i   -   1       +   ɛ         x   i     +     y   i         -   1     )                     (   7   )                         
     and 
     
       
         σ i =Sign( x   i   +y   i   +C   i−1 −2 C   i −1)=Sign( x   i   +y   i   C   i−1 +2 {overscore (C)}   i −3); 
       
     
     
       
         
           
             
               
                 
                   
                     
                       σ 
                       _ 
                     
                     i 
                   
                   = 
                   
                     Sign 
                      
                     
                       ( 
                       
                         
                           
                             
                               
                                 C 
                                 _ 
                               
                               
                                 i 
                                 - 
                                 1 
                               
                             
                             + 
                             
                               
                                 C 
                                 
                                   _ 
                                   _ 
                                 
                               
                               i 
                             
                           
                           
                             
                               x 
                               i 
                             
                             + 
                             
                               y 
                               i 
                             
                             + 
                             
                               
                                 C 
                                 _ 
                               
                               i 
                             
                           
                         
                         - 
                         1 
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
         
         
             
         
       
     
     According to the representation (7), a circuit  300  generating {overscore (C)} i  includes a p-transistor  301  receiving the carrier C i−1  at the gate. A weak p-transistor  302  is disposed in parallel to the p-transistor  301  for keeping open. The x i - and y i -inputs are respectively connected to the gates of n-transistors  303 ,  304 . The drains of these transistors  301 - 304  are commonly connected. The signal {overscore (C)} i  appears at the connected drains, to form C i  through an inverter  320 . 
     On the other hand, according to the expression (8), a circuit  310  generating {overscore (σ)} i  includes p-transistors  311 ,  312  receiving {overscore (C)} i , and C i−1  at the gate. The x i - and y i -inputs and {overscore (C)} i  are respectively connected to the gates of n-transistors  313 ,  314 ,  315 . The drains of these transistors  311 - 315  are commonly connected. The signal {overscore (σ)} i  appears at the connected drains, to form σ i  through an inverter  321 . 
     As described above, a full adder of the present invention employs nine transistors (with two inverters), while a similar implementation of a full adder in a conventional CMOS circuitry requires twenty transistors (plus two inverters). The scale of the circuitry can be reduced in the present invention.