Patent Publication Number: US-6903980-B2

Title: Nonvolatile semiconductor memory device capable of correcting over-erased memory cells

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-170149 filed on Jun. 11, 2002, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a nonvolatile semiconductor memory device that is programmable. 
     2. Description of the Related Art 
     In a nonvolatile semiconductor memory device that is programmable and performs erasure on a batch basis, all the data in a sector to be erased are first set to “0” by preprogramming, and, then, the sector is erased. After the erasure, over-erasure correction is performed to correct memory cells that were over-erased within the erased sector. In general, thresholds of memory cells are not identical to each other, but vary within some distribution. Memory cells after erasure may include memory cells that end up having negative thresholds because of over-erasure. 
     Such over-erased memory cells allow an electric current to run through all the time even when the word line is not activated, thereby disturbing read operations and causing malfunction. The over-erasure correction brings the thresholds of such memory cells back to the normal thresholds, thereby eliminating over-erased memory cells. 
     In the nonvolatile semiconductor memory device as described above, data stored in memory cells of an erased sector may have unknown data status if an erasure operation is halted by a power failure or the like. If there are no over-erased memory cells, an erasure command is entered again into the nonvolatile semiconductor memory device, thereby performing preprogramming, data erasure, and over-erasure correction so as to set the relevant sector in a properly erased state. Depending on the timing of a power failure or resetting during the erasure operation, however, the erasure operation may come to a halt while over-erased memory cells are present. 
     In such a case, an erasure command may be entered again into the nonvolatile semiconductor memory device, but a sufficient potential cannot be given to a data bus in respect of the over-erased memory cells. This results in a failure to properly write data during the preprogramming stage of the erasure operation. The time limit set for an erasure operation may thus come to an end, resulting in a device hang-up. If this is the case, an erasure operation will always result in a device hang-up no matter how many times erasure operations are performed. Such a nonvolatile semiconductor memory device cannot be used as a memory device any longer. 
     Accordingly, there is a need for a nonvolatile semiconductor memory device that allows over-erased memory cells to be recovered when the over-erased memory cells are created by the halt of an erasure operation. 
     SUMMARY OF THE INVENTION 
     It is a general object of the present invention to provide a nonvolatile semiconductor memory device that substantially obviates one or more problems caused by the limitations and disadvantages of the related art. 
     Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a nonvolatile semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention. 
     To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a nonvolatile semiconductor memory device, including a memory cell array which includes nonvolatile memory cells, and a control circuit which responds to a first command by performing a first batch erasure with respect to a selected group of the memory cells, and responds to a second command by performing a second batch erasure with respect to the selected group of the memory cells, the first batch erasure including preprogramming, erasure, and over-erasure correction in this sequence, and the second batch erasure including over-erasure correction, preprogramming, erasure, and over-erasure correction in this sequence. 
     The nonvolatile semiconductor memory device as described above responds to the first command by performing the first batch erasure that is an erasure process performed in a normal erasure mode, and responds to the second command by performing the second batch erasure that is an erasure process performed in an erasure-hang-up recovery mode. In the erasure operation with the erasure-hang-up recovery mode, over-erasure correction is performed first. That is, a check is made as to whether there are over-erased memory cells in the area that is subjected to erasure. If the check finds one or more over-erased memory cells, a write operation for over-erasure correction is repeated until the check passes an over-erasure correction verify. 
     Namely, a threshold of 0 V or a threshold larger than 0 V that sets aside some tolerance margin is used as the threshold for the over-erasure verify, thereby deciding whether there is an over-erased memory cell. If there is an over-erased memory cell, a write operation is performed to bring up the threshold to a verify range of properly erased memory cells. If all the relevant memory cells pass the over-erasure correction verify, there is no over-erased memory cell any longer. 
     Thereafter, preprogramming, erasure, and over-erasure correction are performed in this sequence in the same manner as in a normal erasure algorithm. This properly erases all the memory cells in the relevant area that include the over-erased memory cells created by a halt of an erasure operation. 
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing the construction of a nonvolatile semiconductor memory device according to the present invention; 
         FIG. 2  is a flowchart showing an erasure operation with an erasure-hang-up recovery mode according to the present invention; 
         FIG. 3  is an illustrative diagram showing the thresholds of memory cells in various data states; 
         FIG. 4  is a flowchart for explaining a case in which an erasure operation with the erasure-hang-up recovery mode is performed after a power-failure that occurred during an erasure operation; 
         FIG. 5  is a flowchart for explaining a case in which an erasure operation with a normal erasure mode is performed after a power-failure that occurred during an erasure operation; 
         FIG. 6  is a table that shows the examples of an erasure command for the erasure-hang-up recovery mode and an erasure command for the normal erasure mode; 
         FIG. 7  is a timing chart for explaining the verify operation of an erasure process in the erasure-hang-up recovery mode; and 
         FIG. 8  is a timing chart showing the way a nonvolatile semiconductor memory device behaves when an erasure operation with the normal erasure mode is performed in the presence of an over-erased memory cell. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, embodiments of the present invention will be described with reference to the accompanying drawings. 
       FIG. 1  is a block diagram showing the construction of a nonvolatile semiconductor memory device according to the present invention. 
     A nonvolatile semiconductor memory device  10  of  FIG. 1  includes a control-circuit-&amp;-command-register unit  11 , an input/output buffer  12 , an address latch  13 , a decoder  14 , a data latch  15 , a memory cell array  16 , an output circuit  17 , a write circuit  18 , and an erase circuit  19 . 
     The control-circuit-&amp;-command-register unit  11  receives control signals from the exterior of the device, and also receives a command from the exterior of the device where the command is represented by a combination of an address and data that are input through the input/output buffer  12  and the like. The control-circuit-&amp;-command-register unit  11  operates as a state machine based on the control signals and command, thereby controlling the operation of each part of the nonvolatile semiconductor memory device  10 . 
     The input/output buffer  12  receives data from the exterior of the device, and stores the data in the control-circuit-&amp;-command-register unit  11  and in the data latch  15 . The address latch  13  latches address signals supplied from the exterior of the device, and supplies these address signals to the decoder  14 . The decoder  14  decodes the address supplied from the address latch  13 , and activates a word line situated in the memory cell array  16  in response to the decoding results. Data that are retrieved to the bit lines of the memory cell array  16  are supplied to the data latch  15 . 
     The memory cell array  16  includes an array of memory cell transistors, word lines, bit lines, etc., and store data in each memory cell transistor. At the time of data reading, data are read from memory cells specified by the activated word line, and are supplied to the bit lines. At the time of programming and erasing, word lines and bit lines are set to potentials suitable for respective operations, thereby injecting or removing electric charge into or from memory cells. 
     At the time of data reading, the data latch  15  compares a reference current of a reference cell with a data current that is supplied from the memory cell array  16 . This provides the sensing of data as to whether it is 0 or 1. The sensed data is supplied as read data to the exterior of the device through the input/output buffer  12 . Further, a verify check for the program operation and the erase operation is performed by comparing a reference current for the program verify or the erase verify with a data current supplied from the memory cell array  16 . 
     The output circuit  17  drives the decoder  14  under the control of the control-circuit-&amp;-command-register unit  11 , and reads data from the memory cell array  16  in the case of a data read operation. The write circuit  18  drives the decoder  14  under the control of the control-circuit-&amp;-command-register unit  11 , and performs data writing in the memory cell array  16  based on the write data that is supplied to the data latch  15  from the input/output buffer  12 . 
     The erase circuit  19  generates potentials that are applied to the word lines and bit lines at the time of erase operations, thereby carrying out a sector-specific erasure operation with respect to the memory cell array  16 . 
     In the present invention, the control-circuit-&amp;-command-register unit  11  responds to a command that specifies an erasure operation with the erasure-hang-up recovery mode, and performs an erasure operation that recovers from the conditions that lead to a hang-up. A normal erasure mode that is the same as a conventional erasure mode is also available. If a command specifying an erasure operation with the normal erasure mode is entered, the control-circuit-&amp;-command-register unit  11  performs a normal, routine erasure operation. 
       FIG. 2  is a flowchart showing an erasure operation with the erasure-hang-up recovery mode according to the present invention. 
     At step ST 1  of  FIG. 2 , a verify operation is carried out for the purpose of over-erasure correction. Namely, a data current read from a memory cell is compared with a reference current for the over-erasure verify in order to determine whether there is an over-erased memory cell. If the memory cell subjected to data reading is determined to be an over-erased memory cell (FAIL), a write operation for over-erasure correction is performed at step ST 2 . 
       FIG. 3  is an illustrative diagram showing the thresholds of memory cells in various data states. 
     The vertical axis represents the threshold of memory cells, and the horizontal axis represents the number of memory cells. As shown in  FIG. 3 , memory cells in the data-written state have a threshold distribution that spreads within a “0” verify range. Further, memory cells in the data-erased state have a threshold distribution that spreads within a “1” verify range. These distributions are proper distributions. If an erasure operation comes to a halt due to a power failure or the like, memory cells may be placed in the over-erased state. Such over-erased memory cells have thresholds that are below 0 V as shown by hatches in FIG.  3 . 
     In the erasure operation with the erasure-hang-up recovery mode according to the present invention, a check is made at step ST 1  as to whether memory cells subjected to an erasure operation include an over-erased memory cell. If the check finds one or more over-erased memory cells, a write operation for over-erasure correction is repeated at step ST 2  until the check passes the over-erasure correction verify. 
     Namely, a threshold of 0 V on the vertical axis as shown in  FIG. 3  or a threshold larger than 0 V that sets aside some tolerance margin is used as the threshold for the over-erasure verify, thereby deciding whether there is an over-erased memory cell. If there is an over-erased memory cell, a write operation is performed to bring up the thresholds to the “1” verify range as shown in FIG.  3 . 
     If all the memory cells subjected to the erasure operation passes the over-erasure correction verify, there is no over-erased memory cell any longer. A normal erasure algorithm will commence thereafter. 
     At step ST 3 , a preprogramming verify is performed as part of the normal erasure algorithm. If the verify fails, such a failure means that the relevant memory cells are not programmed, and, thus, preprogramming is performed at step ST 4 . If all the relevant memory cells pass the preprogramming verify, the procedure goes to step ST 5 . 
     At step ST 5 , an erase verify is performed. If it fails, such a failure means that some memory cells are not erased, and, thus, an erasure operation is carried out at step ST 6  with respect to the relevant sector. At step ST 7 , an over-erasure correction verify is performed. At step ST 8 , an over-erasure correction operation is performed on the memory cells that failed the verify check at step ST 7 . When none of the memory cells in the relevant sector is over-erased, the check passes the verify at step ST 7 , so that the procedure goes back to step ST 5 , from where the erase verify and the following steps will be repeated. 
     If all the memory cells in the relevant sector pass the erase verify, the erasure operation comes to an end. 
     In the operations described above, processes performed after step ST 3  are an erasure operation with the normal erasure mode, which is the same as a conventional erasure operation. In the present invention, the entry of a command indicative of an erasure operation with the erasure-hang-up recovery mode lets the procedure start from step ST 1 , thereby performing an erasure operation that corrects an erasure hang-up. The entry of a command indicative of an erasure operation with the normal erasure mode lets the procedure start from step ST 3 , thereby performing a normal, routine erasure operation. 
       FIG. 4  is a flowchart for explaining a case in which an erasure operation with the erasure-hang-up recovery mode is performed after a power-failure that occurred during an erasure operation. 
     At step ST 4 - 1  of  FIG. 4 , an erasure operation comes to a halt because of a power-failure or the like that occurs during the erasure operation. At step ST 4 - 2 , power is turned on, which prompts the nonvolatile semiconductor memory device to start an operation. At step ST 4 - 3 , a command is entered from the exterior of the device, which starts an erasure operation with the erasure-hang-up recovery mode. The following procedure is the same as the procedure that was described in connection with FIG.  2 . That is, an over-erasure verify and over-erasure correction are performed at steps ST 1  and ST 2 , followed by an erasure operation that is the same as a normal erasure operation. As a result, all the memory cells in the relevant sector can properly be erased, including over-erased memory cells that are created by the halt of the erasure operation at step ST 4 - 1 . 
       FIG. 5  is a flowchart for explaining a case in which an erasure operation with the normal erasure mode is performed after a power-failure that occurred during an erasure operation. 
     At step ST 5 - 1  of  FIG. 5 , an erasure operation comes to a halt because of a power-failure or the like that occurs during the erasure operation. At step ST 5 - 2 , power is turned on, which prompts the nonvolatile semiconductor memory device to start an operation. At step ST 5 - 3 , a command is entered from the exterior of the device, which starts an erasure operation with the normal erasure mode. The erasure operation with the normal erasure mode corresponds to the procedure from step ST 3  to step ST 8  of the flowchart of FIG.  2 . 
     The erasure operation with the normal erasure mode does not take into account the presence of over-erased memory cells, and performs a preprogramming verify (step ST 3 ) and preprogramming (step ST 4 ). At the preprogramming verify and preprogramming, a check is made as shown at step ST 4 A of  FIG. 5  as to whether the end of a time limit has come. If the preprogramming is not completed within the time limit, the procedure comes to an end as being an erasure failure. That is, an erasure fails if the programming of an over-erased memory cell is not completed within the time limit. If the over-erased memory cell is not heavily over-erased, the procedure passes the preprogramming verify, and the following steps ST 5  through ST 8  will be properly carried out. In this case, the erasure operation comes to an end without any problem. 
     In FIG.  2  and  FIG. 4 , a check regarding the time limit of a preprogramming process is also made. By the time this preprogramming is performed, however, all the over-erased memory cells are already corrected, leaving no possibility of an erasure failure as in the case of FIG.  5 . For those reasons, the step of a preprogramming time limit check (corresponding to ST 4 A of  FIG. 5 ) is omitted from FIG.  2  and FIG.  4 . 
     When an erasure operation with the normal operation mode is performed as in  FIG. 5 , the procedure does not pass a preprogramming verify because of an over-erased memory cell, resulting in an erasure failure due to exceeding the end of a time limit. In some cases, a normal write operation cannot cope with a strongly over-erased memory cell, so that the procedure fails at the preprogramming stage no matter how many times the erasure operation of  FIG. 5  is repeated. 
     When an erasure operation with the normal erasure mode fails as in this case, an erasure operation with the erasure-hang-up recovery mode as shown in  FIG. 4  is performed by entering a relevant command, thereby correcting over-erased memory cells. When it is known that an erasure operation is halted due to a power-failure or the like, an erasure operation with the erasure-hang-up recovery mode may be performed from the beginning by entering a relevant command. 
       FIG. 6  is a table that shows the examples of an erasure command for the erasure-hang-up recovery mode and an erasure command for the normal erasure mode. 
     A sector erasure with the normal erasure mode is specified by a command by successively supplying predetermined address inputs Add and predetermined data inputs Data to a nonvolatile semiconductor memory device as shown in  FIG. 6  from the first bus write cycle to the sixth bus write cycle. Further, a chip erasure with the normal erasure mode is specified by a command by replacing Data “ 10 H” of the sector erasure with Data “ 30 H” at the sixth bus write cycle. 
     A sector erasure with the erasure-hang-up recovery mode is specified by a command by providing the data input Data “ 11 H” at the sixth bus write cycle. Other address inputs Add and data inputs Data are identical to those of the sector erasure or chip erasure with the normal erasure mode. Further, a chip erasure with the erasure-hang-up recovery mode is specified by a command by providing the data input Data “ 31 H” at the sixth bus write cycle. 
       FIG. 7  is a timing chart for explaining the verify operation of an erasure process in the erasure-hang-up recovery mode. 
     As shown in  FIG. 7 , an address input “ 555 H” and a data input “ 11 H” or “ 31 H” are entered at the sixth bus write cycle (see FIG.  6 ). This indicates an erasure operation (sector erasure or chip erasure) with the erasure-hang-up recovery mode. When an erasure operation starts inside the nonvolatile semiconductor memory device chip, a ready/busy signal that is output from a ready/busy terminal RY/BY is changed from HIGH to LOW. During the erasure operation, the ready/busy signal remains at LOW. After the completion of the erasure operation, the ready/busy signal changes to HIGH. 
       FIG. 8  is a timing chart showing the way a nonvolatile semiconductor memory device behaves when an erasure operation with the normal erasure mode is performed in the presence of an over-erased memory cell. 
     In order to perform an erasure operation with the normal erasure mode, an address input “ 555 H” and a data input “ 10 H” or “ 30 H” are entered at the sixth bus write cycle (see FIG.  6 ). When an erasure operation starts inside the chip, the ready/busy signal that is output from the ready/busy terminal RY/BY is changed from HIGH to LOW. During the erasure operation, the ready/busy signal remains at LOW. A change to HIGH in the ready/busy signal responsive to the completion of the erasure operation is then awaited. 
     The example of  FIG. 8  corresponds to a case in which an over-erased memory cell is present. Since the writing of the over-erased memory cell cannot properly be done during the preprogramming stage of the erasure operation, the ready/busy signal that is expected to signal the end of the erasure operation stays LOW without changing to HIGH. In such a case, an output of the fifth DQ terminal (DQ 5 ) can be monitored to detect the exceeding of a preprogramming time limit. Namely, a change to HIGH of the output of the fifth DQ terminal (DQ 5 ) indicates that the erasure operation has failed by exceeding the end of the preprogramming time limit. In this example, the output of the fifth DQ terminal indicates the exceeding of the preprogramming time limit. Alternatively, any other DQ terminal may be used for this purpose, or any currently unused terminal may be assigned a function to indicate the exceeding of a preprogramming time limit. 
     The outputting of a signal indicative of a device operation status as shown in FIG.  7  and  FIG. 8  may be implemented by the control of the control-circuit-&amp;-command-register unit  11 . 
     In this manner, an output signal indicative of a chip internal operation status can be monitored when an erasure operation with the normal erasure mode is performed. Such monitoring makes it possible to detect the proper completion of an erasure operation or to detect the exceeding of a time limit cased by an over-erased memory cell. In the case of an erasure failure by exceeding the time limit, an erasure command with the erasure-hang-up recovery mode may be entered to properly erase all the relevant memory cells including the over-erased memory cells. 
     Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.