Patent Publication Number: US-7911512-B2

Title: Image sensor with readout circuit

Description:
FIELD OF THE INVENTION 
     This invention relates to solid state active pixel image sensors, and more particularly to CMOS image sensors, e.g. having active pixels each including a photodiode and three transistors. 
     BACKGROUND OF THE INVENTION 
     An image sensor of the type having active pixels each including a photodiode and three transistors commonly uses the technique known as Correlated Double Sampling (CDS) in which two sampling steps are used whereby a reset voltage and a signal voltage for each pixel are stored on capacitors in the column, and the difference between these voltages is processed by the readout chain. CDS improves fixed pattern noise in the final image, but although the subtraction process removes low frequency pixel noise it increases high frequency noise. The requirement for two readout steps limits the maximum operating frequency of the camera, and the provision of the storage capacitors increases the column area and contributes kT/C sampling noise. 
     European Patent Application 0130543.6 filed Oct. 5, 2001 by the present Assignee discloses a 3-transistor pixel image sensor using a read-reset amplifier which operates in reset mode to apply a reset voltage and in read mode it operates as a comparator. 
     Also, European Patent Application 01310582.0 filed Dec. 19, 2001 to the present Assignee discloses an image sensor in which readout of reset and read values is effected one line at a time and interleaved, with a controllable amount of offset between resetting a line and reading that line, to control exposure. This requires a buffer which is capable of storing an entire frame of reset values, which in practice requires a relatively sizeable DRAM. 
     SUMMARY OF THE INVENTION 
     The present invention provides an image sensor and method. The image sensor has an array of pixels. Each column has a first and a second column line connected to a read-reset amplifier/comparator which acts in a first mode as a unity gain buffer amplifier to reset the pixels via the first lines, and in a second mode acts as a comparator and AD converter to produce digitized reset and signal values. The reset and signal values are read out a line at a time in interleaved fashion. Reset values are stored in a memory and subsequently subtracted from the corresponding signal values. The arrangement reduces both fixed pattern and kT/C noise. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the invention will now be described, by way of example only, with reference to the drawings, in which: 
         FIG. 1  is a schematic circuit diagram of one example of image sensor embodying the invention; 
         FIG. 2  is a schematic circuit diagram showing part of the circuit of  FIG. 1  in more detail; 
         FIGS. 3   a  and  3   b  are schematic diagrams illustrating alternative operating modes of the circuit of  FIG. 2 ; 
         FIG. 4  is a timing diagram for the circuit of  FIGS. 2 and 3 ; 
         FIG. 5  is a timing diagram showing the same timing as  FIG. 4  but in terms of picture lines and clock periods; and 
         FIG. 6  is a schematic diagram showing a modified form of analog to digital conversion for the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 1  shows, by way of example, a 3×3 active pixel array. Each pixel  10  includes a photodiode  12  and a transistor pair MN 2 , MR 1  which forms the upper half of a NMOS source follower structure. Each column contains a column line  16  and a second column line  20 . To minimize the capacitance of these two lines, they are best routed in layers of metal with the Vx metal (line  16 ) above the VRT metal (line  20 ). 
     The two column lines  16  and  20  are connected to a Read-Reset Amplifier (RRComp) circuit  22 . The RRComp circuit  22  has two modes controlled by signals ReadMode and ResetMode. When a row of pixels is to be reset to a reference voltage VRT, these signals are ReadMode=0 and ResetMode=1 and the RRComp  22  functions as a unity gain buffer amplifier. When a row of pixel voltages is to be read out and converted into digital form, ReadMode=1 and ResetMode=0 and the RRComp  22  functions as an open loop amplifier or comparator. By feeding a ramp voltage to the input of each RRComp  22  the system functions as a single slope A-D converter. 
       FIG. 2  shows the schematic of the RRComp circuit  22 . One such circuit is contained at the base of each column and serves a column of pixels  10 , one of which is seen in  FIG. 2 . The RRComp circuit  22  is essentially a single stage amplifier which uses transistors MR 1  and MN 2  in the pixel as one half of a differential pair, and the column current source MCS 1  and MCS 2  as the long tail pair bias current. Transistors MP 1  and MP 2  form a current source load which can be configured via transistors MPS 1  and MPS 2 . Other transistors MR 1 , MRS 1  are used to read and reset the pixel, respectively. MR 2  is present to match MR 1  but the gate is always held at VDDHI. MRS 2  is used in reset mode to configure the amplifier as a unity gain buffer. 
       FIG. 2  shows the RRComp  22  configured as a comparator. The output stage is only used when the circuit is configured as a comparator and provides rail-to-rail logic. When the pixel is to be reset, then ResetMode=1, ReadMode=0, ReadModeBar=1 and ResetModeBar=0, configuring the amplifier as a unity gain buffer with output Vpix and input Vout=VRT. While ResetMode=1, the pixel is reset by setting Reset=0. By virtue of resetting the pixel within the feedback loop of the amplifier, the kT/C reset noise is reduced over the gain and bandwidth of the amplifier. Unfortunately the bandwidth of the pixel is much larger than that of the RRComp  22  and so this noise reduction will be small; the situation can be improved by boosting the bias current to the RRComp during reset and increasing the reset switch resistance. Alternatively, the reset pulse fall-time can be increased to allow the amplifier more time to correct for charge injection. 
     Note that the amplifier resets the pixel to a voltage equivalent to VRT plus the offset of the amplifier Vpix=(VRT+Voff). After the pixel is released from reset, the pixel integrates the light-induced photocurrent and produces a decreasing voltage. When the pixel is to be read, then ReadMode=1, ResetMode=0, ResetModeBar=1 and ReadModeBar=0, configuring the amplifier as a comparator with logic output Vc and intermediate output node Vz. The output gain can be increased by making transistor M 1  larger than the pixel source follower transistor Mn 2 . This introduces a systematic offset into the amplifier but this is cancelled by the operation of the RRComp  22 . The achievable gain from this circuit is typically around 45 dB in a 0.35 μm CMOS technology. 
     The offset of the amplifier is now inverted with respect to the reset mode state. This causes the output Vout=Vpix−Voff, and since the pixel was originally reset to the voltage VRT+Voff the offset contribution is cancelled. The two modes of operation are summarized in  FIG. 3 . In this way, the circuit as thus far described cancels fixed pattern noise (FPN) arising from both pixel-to-pixel offset variations due to Vt mismatches of pixel transistors and also column offsets due to mismatches of column amplifiers. When operating as a comparator, the RRComp  22  has an increasing ramp voltage applied to the node Vref. If the voltage Vref exceeds Vpix the output node Vc=AVDD, otherwise Vc=0V. 
     Reverting to  FIG. 1 , the way in which the outputs of the RRComps  22  in each column are utilized will now be described. When the comparator changes state, a count value from counter  24  is latched in a corresponding column DRAM/SRAM register  26 . This memory is preferably operated in a ping-pong fashion to increase readout speed. The stored count is a digital representation of the pixel voltage for that pixel. The stored voltages for a given line can be read out sequentially by a horizontal shift register or decoder  28 . This arrangement is used in a “double read” technique similar to that shown in European Patent Application 01310582.0 filed by the present Assignee. Briefly, lines of reset and read data are read out alternately, with the read data of a given line being delayed or offset from that line&#39;s reset data by a given number of line periods selected to control the image exposure. 
       FIG. 4  illustrates the timing applied to the circuit of  FIGS. 1 and 2  to achieve this, in one embodiment.  FIG. 5  shows the same timing in terms of line information. It will be seen that the number of lines of offset between resetting a given row of pixels and reading out their signal data determines the exposure period, and by adjusting the number of lines of offset the exposure of the image can be adjusted. The memory  26  is used to provide this offset, and must be capable of storing an entire frame if the maximum offset is to be available. 
     The use of RRComps  22  with this technique is of particular advantage. The RRComp reduces the spread of voltages which must be converted in a reset frame and thus reduces the framestore memory requirements. Moreover when configured as an open loop high-gain amplifier or comparator, the RRComp has a very low input referred noise which reduces the remaining readout noise level. 
     As is also indicated in  FIG. 4 , the stored reset (Blk) signal is subtracted from the corresponding pixel signal by any suitable subtracting means to give an output signal. 
     
       
         
           
             
               
                 
                   Vout 
                   = 
                     
                   ⁢ 
                   
                     Vpix 
                     + 
                     
                       √ 
                       
                         ( 
                         
                           kT 
                           / 
                           C 
                         
                         ) 
                       
                     
                     + 
                     FPN 
                     - 
                     
                       ( 
                       
                         VRT 
                         + 
                         
                           √ 
                           
                             ( 
                             
                               kT 
                               / 
                               C 
                             
                             ) 
                           
                         
                         + 
                         FPN 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 
                   = 
                     
                   ⁢ 
                   
                     Vpix 
                     - 
                     VRT 
                   
                 
               
             
           
         
       
     
       FIG. 6  shows a modification in which the Read-Reset amplifier is used to provide a two step AD converter. A two-step ADC can reduce power consumption and increase the output conversion rate of a column-parallel single slope AD converter. A ramp generator  30  provides a coarse ramp waveform which comprises a series of steps, and a fine ramp waveform which is a single slope. The coarse ramp voltage drives the inputs of the array of column comparators and also a local capacitor Cx. When the coarse ramp voltage exceeds the voltage on the pixel, the output of the comparator  22  changes from a 1 to a 0, causing ramp switch  32  to close and store the current ramp voltage locally in the column. 
     In a second conversion phase, CoarseConvert=0 and FineConvert=1, and the fine ramp voltage is applied to the bottom plate of the column capacitors Cx. The column capacitors Cx can be efficiently implemented in NMOS as N-well structures, where the N-well forms the bottom plate and is shared between columns by virtue of always being at a common potential. During the coarse conversion phase, the node Vbot is at approximately a coarse LSB voltage above ground to create a positive system offset for fine ramping. During fine conversion the fine ramp voltage drives Vbot. The fine ramp voltage starts from ground and sweeps over the LSB range of the coarse conversion. Some overrange can be built in to take account of charge injection introduced by the Vtop sampling switch and avoid ramp transient non-linearity. 
     Note that the deltaV on the Vtop node at the beginning of fine conversion will be around a coarse LSB voltage below the pixel output voltage, by virtue of switching Vbot from a coarse LSB voltage to ground. This will reset all comparators into an output high state. The Cx capacitor size must be chosen for some desired kT/C noise level and charge injection offset. The sampling switch should be minimum geometry. 
     The coarse ramp must have a much higher drive strength then the fine ramp, since it is driving a set of parallel grounded capacitors Cx with a greater slew rate. However, since the coarse ramp is used for only a brief part of the overall conversion cycle, the coarse ramp can be shut down when it is not in use. The coarse ramp generator must settle to fine LSB level within a clock cycle. The SRAM bank  26  is divided into fine and coarse sub-banks  26   a  and  26   b . These banks receive a fine and a coarse count which is latched by the change of state of the comparator switch  32  during fine and coarse conversion phases. 
     The present invention thus provides an improved means of reducing fixed pattern noise and kT/C noise. The invention enables a “double read” method to be implemented with a reduced size of frame buffer, potentially allowing SRAM rather than DRAM storage to be used.