Patent Publication Number: US-2009224604-A1

Title: Semiconductor device having plural power source terminals coupled to function block and method of controlling the same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and a method of controlling it, and more specifically, to a semiconductor device suited to an electric connection test with respect to power supplying. 
     2. Description of Related Art 
     Usually, a functional block is built in the semiconductor device and the functional block is electrically connected with a plurality of external terminals of the semiconductor device. Moreover, some functional blocks use dedicated power supplies in order to make small influence of noises from a semiconductor chip, etc. and further there exists a functional block having a plurality of dedicated power supplies in order to strengthen a power supplying capability. 
     On the other hand, there are some semiconductor devices each of which is equipped with a power supply switch in its functional block in order to attain lower power consumption. That is, when operating the functional block, the power supply switch is set to a state of closing to create a state of being able to supply power from the power supply terminal. However, when not operating the functional block, the power supply switch is set to a state of opening to interrupt supplying power to the inside of the functional block, whereby power consumption in the functional block is suppressed. 
     Moreover, in the semiconductor device, as its evaluation test, a validation test of electric connection is being conducted to power supplying wires of the functional block. This test is conducted usually using an evaluation apparatus, such as a tester. For example, when testing a wafer, usually a prober is used. In this case, a probe needle is made to electrically connect an external power supply terminal (pad) of the semiconductor device and the validation test is conducted. 
       FIG. 9  and  FIG. 10  show schematic plan views schematically showing a semiconductor device according to a related art. A semiconductor device  51  has a functional block  52 , such as a macro, a power supply switch  53  exclusively used by the functional block  52 , a plurality of power supply terminals  54   a  to  54   d  exclusively used by the functional block  52 , and an internal power supply wire  56  that electrically connects the functional block  52  and the power supply terminals  54   a  to  54   d .  FIG. 9  shows the semiconductor device with the power supply switch  53  set to be “opened,” and  FIG. 10  shows the semiconductor device with the power supply switch  53  set to be “closed.” In the semiconductor device  51 , the power supply terminals  54   a  to  54   d  are electrically connected with one another via the internal power supply wire  56 . That is, the power supply terminals  54   a  to  54   d  are in a state of being short-circuited in the semiconductor device  51 . 
     Incidentally, any wires electrically connected with the power supply are shown by thick lines and wires not electrically connected with the power supply are shown by thin lines in each diagram. Moreover, the power supply terminals electrically connected with the power supply are given hatching of a check (grating) pattern, and the power supply terminals not electrically connected with the power supply are given hatching of a stripe (oblique line) pattern. The power supply terminals and signal terminals that do not participate in the explanation of the present invention are not given hatching. 
     Here, in the semiconductor device  51 , when operating the functional block  52 , the power supply switch  53  is set to be “closed,” so that the functional block can be supplied power from the power supply terminals  54   a  to  54   d . On the other hand, when not operating the functional block  52 , the power consumption in the functional block  52  is suppressed by setting the power supply switch  53  to be “opened,” as shown in  FIG. 9 , and thereby interrupting supplying power to the functional block  52  from the power supply terminals  54   a  to  54   d.    
     Patent Document 1 (Japanese Patent Application Laid open No. 2001-060653) discloses a test workable semiconductor integrated circuit for conducting the electric connection test between the power supply terminals of the semiconductor chip and the power supply terminals of a semiconductor package wire-bonded thereto. This test workable semiconductor integrated circuit builds therein a non-relay type testing switch that intervenes between the plurality of power supply terminals of the semiconductor package and the semiconductor chip and whose opening and closing are controllable by means of a terminal outside the semiconductor chip. By this incorporation, at the time of a normal operation, the functional blocks in the semiconductor chip are electrically connected with the plurality of power supply terminals of the semiconductor package, and at the time of the testing, the functional blocks are connected only with a predetermined power supply terminal of the semiconductor package. Moreover, as one form of the test workable semiconductor integrated circuit, a form in which the number of power supply terminals and the number of the functional blocks are different from each other and that has switches for electrically isolating the power supply terminals and switches for electrically isolating the functional blocks for every functional block is also disclosed. 
     SUMMARY 
     The following analysis is given from a viewpoint of the present invention. 
       FIG. 11  is a schematic plan view schematically showing a semiconductor device according to a background art, and shows a semiconductor device in which a tester  57  for evaluating the electric connection of power supplying wires to the functional block  52  is electrically connected with the power supply terminals  54   a  to  54   d  of the semiconductor device  51  according to the background art shown in  FIG. 9  and  FIG. 10 . 
     In the case of the semiconductor device  51  having a configuration as is shown in  FIG. 9  to  FIG. 11 , since the power supply terminals  54   a  to  54   d  are electrically connected with one another by the internal power supply wire  56 , if even one power supply terminal among the plurality of existing power supply terminals  54   a  to  54   d  is electrically connected with a probe needle of the tester  57 , the semiconductor device  51  will pass an electric connection test. For example, as shown in  FIG. 11 , even in the case where the probe needle of the tester  57  is not connected with the power supply terminal  54   c , or even in the case where the internal power supply wire  56  is not electrically connected with the power supply terminal  54   d , since the internal power supply wire  56  and the probe needle of the tester  57  are electrically connected with the power supply terminals  54   a ,  54   b  normally, the semiconductor device can pass the electric connection test. 
     In such a case, even if a comparison is made between semiconductor devices that passed the electric connection test, since the semiconductor device that is supplied power normally from all the power supply terminals  54   a  to  54   d  and the semiconductor device that is not normally supplied power at a part of power supply terminals, as shown in  FIG. 11 , have different numbers of power supply terminals that are electrically connected, a difference will occur in transient electric power serviceability, and consequently a difference will arise in the evaluation result. Therefore, high-reliability evaluation cannot be performed in the semiconductor device having a configuration as shown in  FIG. 9  to  FIG. 11 . 
     A test workable semiconductor integrated circuit described in Patent Document 1 is for conducting an electric test of the power supply terminals of a semiconductor package (power supply terminals wire-bonded to the power supply terminals of a semiconductor chip), and the power supply terminals of the semiconductor device are short-circuited in the semiconductor device. Therefore, the test workable semiconductor integrated circuit described in Patent Document 1 is not one that is capable of conducting the electric connection test of each power supply terminal of the semiconductor chip. Especially, it is impossible for the circuit to conduct the electric connection test of the each power supply terminal in the semiconductor chip whose functional block is connected with a plurality of power supply terminals. Moreover, even if the semiconductor device has a form having a switch for electrically isolating the power supply terminals disclosed in Patent Document 1, one functional block can electrically connects a specific power supply terminal (for example, the first power supply terminal) among a plurality of power supply terminals (for example, assuming that they are the first power supply terminal and the second power terminal) connected with the functional block; if it is intended to be connected with other power supply terminal (for example, the second power supply terminal), it has no alternative but to electrically connect also with the specific power supply terminal (for example, the first power supply terminal). 
     By a first exemplary aspect of the present invention, a semiconductor device that has at least one functional block, the plurality of power supply terminals for supplying power to the functional block, and a plurality of switches each for controlling opening and closing of the electric connection between each power supply terminal and the functional block individually is provided. In the semiconductor device, the plurality of power supply terminals are not electrically connected with one another unless being intermediated by the functional block. Each switch is electrically connected only with one power supply terminal among the plurality of power supply terminals. 
     According to a second exemplary aspect of the present invention, a method for controlling a semiconductor device equipped with a plurality of power supply terminals and a functional block electrically connected with the plurality of power supply terminals via switches is provided. When controlling an operation of the functional block, opening and closing of the electric connections between the plurality of power supply terminals and the functional block are controlled simultaneously. When checking the electric connection for each power supply terminal, a predetermined power supply terminal whose electric connection is to be checked and the functional block are electrically connected, and at the same time both electric connections between the predetermined power supply terminal and the other power supply terminals and electric connections between the other power supply terminals and the functional block are interrupted. 
     According to the exemplary aspects of the present invention, the electric connection test of each of the power supply terminals can be conducted without affecting a normal operation of the functional block. This capability can suppress occurrence of a situation in which a power supplying capability becomes different among the semiconductor devices that passed the electric connection test, and can better reliability of the test. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other exemplary aspects, advantages and features of the present invention will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a schematic plan view schematically showing a semiconductor device according to a first exemplary embodiment of the present invention; 
         FIG. 2  is a schematic plan view schematically showing the semiconductor device according to the first exemplary embodiment of the present invention; 
         FIG. 3  is a schematic plan view schematically showing the semiconductor device according to the first exemplary embodiment of the present invention; 
         FIG. 4  is a schematic plan view schematically showing the semiconductor device according to the first exemplary embodiment of the present invention; 
         FIG. 5  is a schematic plan view schematically showing the semiconductor device according to the first exemplary embodiment of the present invention; 
         FIG. 6  is a schematic plan view schematically showing the semiconductor device according to the first exemplary embodiment of the present invention; 
         FIG. 7  is a schematic plan view schematically showing a semiconductor device according to a second exemplary embodiment of the present invention; 
         FIG. 8  is a schematic plan view schematically showing the semiconductor device according to the second exemplary embodiment of the present invention; 
         FIG. 9  is a schematic plan view schematically showing a semiconductor device according to a related art; 
         FIG. 10  is a schematic plan view schematically showing the semiconductor device according to the related art; and 
         FIG. 11  is a schematic plan view schematically showing the semiconductor device according to the related art. 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     A semiconductor device according to a first exemplary embodiment of the present invention will be explained.  FIG. 1  shows a schematic plan view schematically showing the semiconductor device according to the first exemplary embodiment of the present invention. A semiconductor device (semiconductor chip or package)  1  has at least one functional block  2 , such as a macro, a plurality of power supply switches  3   a  to  3   d  exclusively used by the functional block  2 , a plurality of power supply terminals (pads)  4   a  to  4   d  for the functional block  2 , and internal power supply wires (in the circuit)  6   a  to  6   d  that connect at least one signal terminal (pad)  5   a  to  5   d , the functional block  2 , and at least one of the power supply terminals  4   a  to  4   d.    
     Incidentally, each diagram illustrates only what is necessary for explanation of the present invention, and illustrations of any elements that are not used for the explanation (for example, a signal wire etc.) are omitted. Moreover, illustration of a situation of electric connections is as explained above. 
     The semiconductor device  1  is equipped with at least the power supply switches  3   a  to  3   d  whose number corresponds to the number of the power supply terminals  4   a  to  4   d  electrically connected with the functional block  2 . The power supply switches  3   a  to  3   d  electrically connected with the functional block  2  are electrically connected with the power supply terminals  4   a  to  4   d  that correspond to the respective components via the internal power supply wires  6   a  to  6   d . For example, the power supply switch  3   a  is connected between the functional block  2  and the power supply terminal  4   a  via the internal power supply wire  6   a , the power supply switch  3   b  is connected between the functional block  2  and the power supply terminal  4   b  via the internal power supply wire  6   b , the power supply switch  3   c  is connected between the functional block  2  and the power supply terminal  4   c  via the internal power supply wire  6   c , and the power supply switch  3   d  is connected between the functional block  2  and the power supply terminal  4   d  via the internal power supply wire  6   d.    
     Moreover, in the semiconductor device  1 , the plurality of power supply terminals  4   a  to  4   d  are not electrically connected with one another unless being intermediated by the functional block  2 . Similarly, the plurality of power supply switches  3   a  to  3   d  and the plurality of internal power supply wires  6   a  to  6   d  are not electrically connected with one another, respectively, either in the semiconductor device  1 . That is, regarding electric connections between the power supply switches  3   a  to  3   d  and the power supply terminals  4   a  to  4   d , they are electrically independent in the semiconductor device  1 : the power supply switch  3   a  will be connected only with the power supply terminal  4   a ; the power supply switch  3   b  will be connected only with the power supply terminal  4   b ; the power supply switch  3   c  will be connected only with the power supply terminal  4   c ; and the power supply switch  3   d  will be connected only with the power supply terminal  4   d , respectively. 
     As the power supply switches  3   a  to  3   d , a switch made of transistors can be used, for example. Incidentally, it is natural that the numbers of the power supply switches and the terminals are not limited to the numbers shown in the figure and can be set up appropriately. 
     A selector  9  capable of individually controlling opening and closing of the power supply switches  3   a  to  3   d  from the outside is connected with the semiconductor device  1 . For example, the selector  9  is electrically connected with the signal terminals  5   a  to  5   d  via external wires  10   a  to  10   d.    
     Regarding the power supply switches  3   a  to  3   d , the power supply switches  3   a  to  3   d  can be simultaneously opened and closed collectively by using a selector connected with the semiconductor device  1  or the like, and opening and closing of at least one power supply switch among the power supply switches  3   a  to  3   d  can also be controlled. Therefore, supplying power to the functional block  2  can be controlled by controlling opening and closing of all the power supply switches  3   a  to  3   d , and the situation of electric connection of power supplying wires can also be checked by individually opening and closing the power supply switches  3   a  to  3   d.    
     Moreover, in the case where transistors are used as the power supply switches  3   a  to  3   d  in the semiconductor device  1  of the present invention, since a total size of the power supply switches is allowed to be equivalent to that of a case where the power supply switch  1  as shown in  FIG. 9  to  FIG. 11  is unity, there is almost no increase in the area as compared with a form shown in  FIG. 9  to  FIG. 11 . 
     Next, a method for controlling the semiconductor device  1  of the present invention will be explained.  FIG. 2  shows a schematic plan view schematically showing the semiconductor device according to the first exemplary embodiment of the present invention.  FIG. 1  is a diagram showing a state in which the power supply switches  3   a  to  3   d  are all “opened,” and  FIG. 2  is a diagram showing a state in which all the power supply switches  3   a  to  3   d  are “closed.” 
     First, a control method in controlling an operation of the functional block of the semiconductor device of the present invention will be explained. When operating the functional block  2  in the semiconductor device  1 , the power supply switches  3   a  to  3   d  are all set to be “closed” by the selector  9 , so that the functional block  2  and the power supply terminals  4   a  to  4   d  are all electrically connected together. On the other hand, when the functional block  2  is not operated, the power supply switches  3   a  to  3   d  are all set to be “opened,” so that the electric connections between the functional block  2  and the power supply terminals  4   a  to  4   d  are all interrupted. By this setting, supplying power to the functional block  2  can be controlled, and power consumption at the time of not using the functional block  2  can be suppressed. 
     Next, the control method in an electric connection test of the semiconductor device of the present invention will be explained.  FIG. 3  to  FIG. 6  show schematic plan views schematically showing the semiconductor device according to the first exemplary embodiment of the present invention. 
     A tester  7  for evaluating the electric connections in the semiconductor device  1  is electrically connected with the power supply terminals  4   a  to  4   d  of the semiconductor device  1  via external wires  8   a  to  8   d.    
       FIG. 3  shows a state in which only the power supply switch  3   a  among the power supply switches  3   a  to  3   d  is set to be “closed”.  FIG. 4  shows a state in which only the power supply switch  3   b  among the power supply switches  3   a  to  3   d  is set to be “closed”.  FIG. 5  shows a state in which only the power supply switch  3   c  among the power supply switches  3   a  to  3   d  is set to be “closed”.  FIG. 6  shows a state in which only the power supply switch  3   d  among the power supply switches  3   a  to  3   d  is set to be “closed.” Thus, the power supply switches  3   a  to  3   d  and the internal power supply wires  6   a  to  6   d  that are electrically independent in the semiconductor device  1  are used and, with respect to a predetermined power supply terminal that will be checked for the electric connection, only the power supply switch connected with the predetermined power supply terminal is set to be “closed,” whereby it becomes possible for the predetermined power supply terminal and the functional block  2  to be electrically connected, and it becomes possible for both electric connections between the other power supply terminals and the functional block  2  and the electric connections between the predetermined power supply terminal and the other power supply terminals to be interrupted. 
     By this, the situations of electric connection in the power supplying wires (the power supply terminals  4   a  to  4   d , the power supply switches  3   a  to  3   d , and the internal power supply wires  6   a  to  6   d ) can be checked individually. Therefore, if there is a defect of no electric connection in any one of the wires etc., it can be checked surely. Moreover, it can suppress occurrence of a difference in a power supplying capability among the semiconductor devices that passed the test and can better reliability of the test. 
     Next, a semiconductor device according to a second exemplary embodiment of the present invention will be explained.  FIG. 7  shows a schematic plan view schematically showing the semiconductor device according to the second exemplary embodiment of the present invention. Although the semiconductor device having one functional block was explained in the first exemplary embodiment, in this exemplary embodiment the semiconductor device having a plurality of functional blocks will be explained. Incidentally,  FIG. 7  shows a situation where a tester  31  for conducting the electric connection test is connected with a semiconductor device  21 . 
     The semiconductor device  21  has a first functional block  22  and a second functional block  23 . Moreover, the semiconductor device  21  has power supply switches  24   a  to  24   d ,  25   a  to  25   e  whose number corresponds to the number of first power supply terminals  26   a  to  26   d  electrically connected with the first functional block  22  and second power supply terminals  27   a  to  27   e  electrically connected with the second functional block  23 . The first power supply switches  24   a  to  24   d  electrically connected with the first functional block  22  are electrically connected with the first power supply terminals  26   a  to  26   d  that correspond to the respective switches individually via first internal power supply wires  29   a  to  29   d ; the second power supply switches  25   a  to  25   e  electrically connected with the second functional block  23  are electrically connected with the second power supply terminals  27   a  to  27   e  that correspond to the respective switches individually via second power supply terminals  30   a  to  30   e . Moreover, in this exemplary embodiment, the power supply wires are electrically independent in the semiconductor device  21 , like the first exemplary embodiment. 
     In the semiconductor device  21 , the selector  34  that enables opening and closing of the power supply switches  24   a  to  24   d ,  25   a  to  25   e  to be controlled individually from the outside is electrically connected with signal terminals  28   a  to  28   i  via external wires  35   a  to  35   i.    
     The power supply switches  24   a  to  24   d ,  25   a  to  25   e  can also be simultaneously set to be opened and closed collectively by using a selector  34 , and opening and closing of at least one arbitrary power supply switch among the power supply switches  24   a  to  24   d ,  25   a  to  25   e  can also be controlled. Therefore, supplying power to the first functional block  22  and the second functional block  23  can be controlled by controlling opening and closing of all of the first power supply switches  24   a  to  24   d  and the second power supply switches  25   a  to  25   e . Moreover, if opening and closing of the power supply switches  24   a  to  24   d  or the power supply switches  25   a  to  25   e  are controlled for each functional block, the functional blocks  22 ,  23  can also be operated individually. Further, the situations of electric connection of the power supply wires can be checked by individually opening and closing the respective power supply switches  24   a  to  24   d ,  25   a  to  25   e.    
     Next, a control method of the semiconductor device  21  according to the second exemplary embodiment of the present invention will be explained using  FIG. 7  and  FIG. 8 .  FIG. 7  is a diagram showing a state in which all the power supply switches  24   a  to  24   d ,  25   a  to  25   e  are set to be “closed.”  FIG. 8  is a diagram showing a state in which the first power supply switches  24   a  to  24   d  are set to be “closed” and the second power supply switches  25   a  to  25   e  are set to be “opened.” When operating the first functional block  22 , the first power supply switches  24   a  to  24   d  connected with the first functional block  22  are all set to be “closed” in the same manner as the first exemplary embodiment; when not operating the first functional block  22 , the first power supply switches  24   a  to  24   d  are all set to be “opened.” Similarly, when operating the second functional block  23 , the second power supply switches  25   a  to  25   e  are all set to be “closed”; when not operating the second functional block  23 , the second power supply switches  25   a  to  25   e  are all set to be “opened.” Therefore, when simultaneously operating the first functional block  22  and the second functional block  23 , the first power supply switches  24   a  to  24   d  and the second power supply switches  25   a  to  25   e  are all set to be “closed”; when not simultaneously operating the first functional block  22  and the second functional block  23 , the first power supply switches  24   a  to  24   d  and the second power supply switches  25   a  to  25   e  are all set to be “opened.” Moreover, when operating at least one functional block among the plurality of functional blocks, for example, when operating only the first functional block  22  among the first functional block  22  and the second functional block  23 , the first power supply switches  24   a  to  24   d  are set to be “closed” and the second power supply switches  25   a  to  25   e  are set to be “opened,” as shown in  FIG. 8 . 
     By doing this, supplying power to the first functional block  22  and the second functional block  23  can be controlled, and the power consumption when the first functional block  22  and the second functional block  23  are not used can be suppressed. 
     Next, a control method in the electric connection test of the semiconductor device according to the second exemplary embodiment of the present invention will be explained using  FIG. 7 . The tester  31  for evaluating the electric connections in the semiconductor device  21  is electrically connected with the first power supply terminals  26   a  to  26   d  and the second power supply terminals  27   a  to  27   e  of the semiconductor device  21  via first external wires  32   a  to  32   d  and second external wires  33   a  to  33   e.    
     When conducting an electric connection evaluation test, like the first exemplary embodiment, only the power supply switch connected with the predetermined power supply terminal that will become a subject of the test is set to be “closed” and the other power supply switches than it are set to be “opened,” as shown in  FIG. 3  to  FIG. 6 . By this, even in the case of the semiconductor device  21  equipped with a plurality of functional blocks  22 ,  23 , the situations of electric connections of the respective power supplying wires can be checked individually. 
     INDUSTRIAL APPLICABILITY 
     Although the semiconductor device of the present invention and a method for manufacturing it were explained based on the above-mentioned exemplary embodiments, it is natural that the above-mentioned exemplary embodiments may include various variants, alterations, and improvements within a range of the present invention and based on a basic technological thought of the present invention without being limited to the above-mentioned exemplary embodiments. Moreover, within a limit of the scope of claims of the present invention, versatile combinations, substitutions, or selections of the disclosed various elements are possible. 
     Further problems, objects, and developmental forms of the present invention will be made clear also from all disclosed matters of the present invention including the scope of claims. 
     Further, it is noted that Applicant&#39;s intent is to encompass equivalents of all claim elements, even if amended later during prosecution.