Patent Publication Number: US-2022231892-A1

Title: Receiving circuit of deserializer

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a signal transmission circuit, and, more particularly, to a circuit at the receiving end of a serializer/deserializer (SerDes). 
     2. Description of Related Art 
     Link equalizer circuits (LEQs) and out-of-band signaling (OOBS) circuits are commonly found at the receiving end of the SerDes. The LEQ equalizes the signals received at the receiving end to compensate for the high-frequency attenuation of the signals as much as possible. The OOBS circuit detects the amplitude of the signals and controls the power of the signals. The detailed circuits and operating principles of the LEQs and the OOBS circuits are well known to people having ordinary skill in the art; therefore, the details are omitted for brevity. 
     However, because the common mode voltage in the receiving end of the traditional SerDes is jointly established by resistor-based voltage division, the LEQ, and the OOBS circuit, load stacking that accounts for high speed data attenuation is a common issue. Therefore, the design of the receiving circuit of a high-efficiency SerDes is a big challenge in the design of high-speed circuits. 
     SUMMARY OF THE INVENTION 
     In view of the issues of the prior art, an object of the present invention is to provide a receiving circuit of a deserializer, so as to make an improvement to the prior art. 
     According to one aspect of the present invention, a receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes a signal receiving terminal, a link equalizer circuit, an out-of-band signaling (OOBS) circuit, a first resistor, a second resistor, and a buffer circuit. The signal receiving terminal is configured to receive the input signal. The link equalizer circuit has a first input terminal coupled to the signal receiving terminal. The OOBS circuit has a second input terminal coupled to the signal receiving terminal. The first resistor is coupled between the signal receiving terminal and a first reference voltage. The second resistor is coupled between the signal receiving terminal and a second reference voltage. The buffer circuit has a third input terminal and an output terminal. The third input terminal is configured to receive a voltage, and the output terminal is coupled to the link equalizer circuit or the OOBS circuit. The first input terminal of the link equalizer circuit and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable. 
     According to another aspect of the present invention, a receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes a signal receiving terminal, a link equalizer circuit, an out-of-band signaling (OOBS) circuit, a first capacitor, a second capacitor, a first resistor, a second resistor, and a buffer circuit. The signal receiving terminal is configured to receive the input signal. The link equalizer circuit has a first input terminal coupled to the signal receiving terminal. The OOBS circuit has a second input terminal coupled to the signal receiving terminal. The first capacitor has a first terminal and a second terminal. The first terminal is coupled to the signal receiving terminal, and the second terminal is coupled to the link equalizer circuit or the OOBS circuit. The second capacitor has a third terminal and a fourth terminal. The third terminal is coupled to the signal receiving terminal, and the fourth terminal is coupled to the link equalizer circuit or the OOBS circuit. The first resistor has a fifth terminal and a sixth terminal. The fifth terminal is coupled to a first reference voltage, and the sixth terminal is electrically coupled to the signal receiving terminal. The second resistor has a seventh terminal and an eighth terminal. The seventh terminal is coupled to a second reference voltage, and the eighth terminal is electrically coupled to the link equalizer circuit or the OOBS circuit. The buffer circuit has a third input terminal and an output terminal. The third input terminal is configured to receive a voltage, and the output terminal is coupled to the link equalizer circuit or the OOBS circuit. The first input terminal of the link equalizer circuit and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable. 
     These and other objectives of the present invention no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments with reference to the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of the receiving circuit of a deserializer according to an embodiment of the present invention. 
         FIG. 2  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
         FIG. 3  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
         FIG. 4  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
         FIG. 5  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
         FIG. 6  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
         FIG. 7  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
         FIG. 8  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
         FIG. 9  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
         FIG. 10  is a circuit diagram of the receiving circuit of a deserializer according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The following description is written by referring to terms of this technical field. If any term is defined in this specification, such term should be interpreted accordingly. In addition, the connection between objects or events in the below-described embodiments can be direct or indirect provided that these embodiments are practicable under such connection. Said “indirect” means that an intermediate object or a physical space exists between the objects, or an intermediate event or a time interval exists between the events. 
     The disclosure herein includes the receiving circuit of a deserializer. On account of that some or all elements of the receiving circuit of the deserializer could be known, the detail of such elements is omitted provided that such detail has little to do with the features of this disclosure, and that this omission nowhere dissatisfies the specification and enablement requirements. A person having ordinary skill in the art can choose components equivalent to those described in this specification to carry out the present invention, which means that the scope of this invention is not limited to the embodiments in the specification. 
       FIG. 1  is a circuit diagram of the receiving circuit of a deserializer according to an embodiment of the present invention. The receiving circuit  100  includes a signal receiving terminal  110 , a resistor  120 , a resistor  130 , a buffer circuit  140 , an LEQ  150 , and an OOBS circuit  160 . The receiving circuit  100  is a receiving circuit of the direct current (DC) coupling mode. 
     The input signal Vin is inputted into the receiving circuit  100  through the signal receiving terminal  110  (i.e., the signal receiving terminal  110  receives the input signal Vin). The resistor  120  is coupled between the first reference voltage (e.g., the power supply voltage VDD) and the signal receiving terminal  110 . The resistor  130  is a variable resistor, and is coupled between the signal receiving terminal  110  and the second reference voltage (e.g., ground). The LEQ  150  is electrically connected to the signal receiving terminal  110 ; in other words, the resistor  120  is coupled between the first reference voltage and the input terminal of the LEQ  150 , and the resistor  130  is coupled between the input terminal of the LEQ  150  and the second reference voltage. The buffer circuit  140  is coupled between the resistor  130  and the OOBS circuit  160 ; more specifically, the input terminal of the buffer circuit  140  is electrically connected to the resistor  130 , and the output terminal of the buffer circuit  140  is electrically connected to the input terminal of the OOBS circuit  160 . 
     The input terminal of the buffer circuit  140  receives the voltage Vb which is the divided voltage on the resistor  130 . In other words, the voltage Vb can be changed by adjusting the resistance of the resistor  130 . Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the OOBS circuit  160 . 
     In some embodiments, the voltage Vb is smaller than the voltage at the input terminal of the LEQ  150 . 
     In the embodiment of  FIG. 1 , the buffer circuit  140  is embodied by a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) (hereinafter referred to as a PMOS transistor) source follower circuit (which is also referred to as a common-drain amplifier). The buffer circuit  140  includes a current source  142  and a PMOS transistor  144 . The gate of the PMOS transistor  144  (i.e., the input terminal of the buffer circuit  140 ) receives the voltage Vb, the source of the PMOS transistor  144  (i.e., the output terminal of the buffer circuit  140 ) is coupled to the first reference voltage through the current source  142 , and the drain of the PMOS transistor  144  is electrically connected to the second reference voltage. The operating principle of the source follower circuit is well-known to people having ordinary skill in the art, and is thus omitted for brevity. 
     One of the purposes of the buffer circuit  140  is to separate the LEQ  150  and the OOBS circuit  160  in a way that the input terminal of the LEQ  150  and the input terminal of the OOBS circuit  160  are not electrically connected to each other. As a result, the common mode voltage of the LEQ  150  and the common mode voltage of the OOBS circuit  160  can be adjusted independently. 
     Another purpose of the buffer circuit  140  is to reduce the load observed by the OOBS circuit  160 ; therefore, the data transmission rate of the receiving circuit  100  can be improved. 
       FIG. 2  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  200  is similar to the receiving circuit  100 , except that the LEQ  150  and the OOBS circuit  160  are interchanged. The receiving circuit  200  is a receiving circuit of the DC coupling mode. In the embodiment of  FIG. 2 , the buffer circuit  140  can reduce the load observed by the LEQ  150 ; in addition, the common mode voltage of the LEQ  150  and the common mode voltage of the OOBS circuit  160  can be adjusted independently. Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the LEQ  150 . 
     In some embodiments, the voltage Vb is smaller than the voltage at the input terminal of the OOBS circuit  160 . 
       FIG. 3  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  300  includes a signal receiving terminal  110 , the resistor  120 , a resistor  330 , the buffer circuit  140 , the LEQ  150 , the OOBS circuit  160 , a capacitor  370 , and a resistor  380 . The receiving circuit  300  is a receiving circuit of the DC coupling mode. The receiving circuit  300  is similar to the receiving circuit  100 , except that the receiving circuit  300  further includes the capacitor  370  and the resistor  380 . The resistor  380  is a variable resistor. The function of the resistor  330  is the same as that of the resistor  130 , but the resistor  330  may not be a variable resistor. 
     The capacitor  370  is coupled between the signal receiving terminal  110  and the LEQ  150 . More specifically, one end of the capacitor  370  is electrically connected to the signal receiving terminal  110 , and the other end of the capacitor  370  is electrically connected to the input terminal of the LEQ  150 . The resistor  380  and the capacitor  370  are connected in parallel. The input terminal of the buffer circuit  140  is electrically connected to the resistor  380 . One of the purposes of the capacitor  370  and the resistor  380  is to generate a peak gain at the high-frequency part of the input signal Vin, so as to compensate for the high-frequency loss of the input signal Vin. 
     The input terminal of the buffer circuit  140  receives the voltage Vb which is the divided voltage on the resistor  380 . In other words, the voltage Vb can be changed by adjusting the resistance of the resistor  380 . 
     In some embodiments, the voltage Vb is smaller than the voltage at the input terminal of the LEQ  150 . 
       FIG. 4  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  400  is similar to the receiving circuit  300 , except that the LEQ  150  and the OOBS circuit  160  are interchanged. The receiving circuit  400  is a receiving circuit of the DC coupling mode. In the embodiment of  FIG. 4 , the buffer circuit  140  can reduce the load observed by the LEQ  150 ; in addition, the common mode voltage of the LEQ  150  and the common mode voltage of the OOBS circuit  160  can be adjusted independently. 
     In some embodiments, the voltage Vb is smaller than the voltage at the input terminal of the OOBS circuit  160 . 
       FIG. 5  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  500  includes a signal receiving terminal  510 , a resistor  520 , a resistor  530 , a buffer circuit  540 , the LEQ  150 , and the OOBS circuit  160 . The receiving circuit  500  is a receiving circuit of the DC coupling mode. 
     The input signal Vin is inputted into the receiving circuit  500  through the signal receiving terminal  510  (i.e., the signal receiving terminal  510  receives the input signal Vin). The resistor  520  is a variable resistor, and is coupled between the first reference voltage and the signal receiving terminal  510 . The resistor  530  is coupled between the signal receiving terminal  510  and the second reference voltage. The LEQ  150  is electrically connected to the signal receiving terminal  510 ; in other words, the resistor  520  is coupled between the first reference voltage and the input terminal of the LEQ  150 , and the resistor  530  is coupled between the input terminal of the LEQ  150  and the second reference voltage. The buffer circuit  540  is coupled between the resistor  520  and the OOBS circuit  160 ; more specifically, the input terminal of the buffer circuit  540  is electrically connected to the resistor  520 , and the output terminal of the buffer circuit  540  is electrically connected to the input terminal of the OOBS circuit  160 . 
     The input terminal of the buffer circuit  540  receives the voltage Vb which is the divided voltage on the resistor  520 . In other words, the voltage Vb can be changed by adjusting the resistance of the resistor  520 . Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the OOBS circuit  160 . 
     In some embodiments, the voltage Vb is greater than the voltage at the input terminal of the LEQ  150 . 
     In the embodiment of  FIG. 5 , the buffer circuit  540  is embodied by an N-channel MOSFET (hereinafter referred to as an NMOS transistor) source follower circuit. The buffer circuit  540  includes a current source  542  and an NMOS transistor  544 . The gate of the NMOS transistor  544  (i.e., the input terminal of the buffer circuit  540 ) receives the voltage Vb, the source of the NMOS transistor  544  (i.e., the output terminal of the buffer circuit  540 ) is coupled to the second reference voltage through the current source  542 , and the drain of the NMOS transistor  544  is electrically connected to the first reference voltage. The operating principle of the source follower circuit is well-known to people having ordinary skill in the art, and is thus omitted for brevity. 
     The purpose of the buffer circuit  540  is similar to that of the buffer circuit  140 , so the details are omitted for brevity. 
       FIG. 6  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  600  is similar to the receiving circuit  500 , except that the LEQ  150  and the OOBS circuit  160  are interchanged. The receiving circuit  600  is a receiving circuit of the DC coupling mode. In the embodiment of  FIG. 6 , the buffer circuit  540  can reduce the load observed by the LEQ  150 ; in addition, the common mode voltage of the LEQ  150  and the common mode voltage of the OOBS circuit  160  can be adjusted independently. Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the LEQ  150 . 
     In some embodiments, the voltage Vb is greater than the voltage at the input terminal of the OOBS circuit  160 . 
       FIG. 7  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  700  includes a signal receiving terminal  510 , a resistor  720 , the resistor  530 , the buffer circuit  540 , the LEQ  150 , the OOBS circuit  160 , a capacitor  770 , and a resistor  780 . The receiving circuit  700  is a receiving circuit of the DC coupling mode. The receiving circuit  700  is similar to the receiving circuit  500 , except that the receiving circuit  700  further includes the capacitor  770  and the resistor  780 . The resistor  780  is a variable resistor. The function of the resistor  720  is the same as that of the resistor  520 , but the resistor  720  may not be a variable resistor. 
     The capacitor  770  is coupled between the signal receiving terminal  510  and the LEQ  150 . More specifically, one end of the capacitor  770  is electrically connected to the signal receiving terminal  510 , and the other end of the capacitor  770  is electrically connected to the input terminal of the LEQ  150 . The resistor  780  is connected in parallel with the capacitor  770 . The input terminal of the buffer circuit  540  is electrically connected to the resistor  780 . One of the purposes of the capacitor  770  and the resistor  780  is to generate a peak gain at the high-frequency part of the input signal Vin, so as to compensate for the high-frequency loss of the input signal Vin. 
     The input terminal of the buffer circuit  540  receives the voltage Vb which is the divided voltage on the resistor  780 . In other words, the voltage Vb can be changed by adjusting the resistance of the resistor  780 . 
     In some embodiments, the voltage Vb is greater than the voltage at the input terminal of the LEQ  150 . 
       FIG. 8  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  800  is similar to the receiving circuit  700 , except that the LEQ  150  and the OOBS circuit  160  are interchanged. The receiving circuit  800  is a receiving circuit of the DC coupling mode. In the embodiment of  FIG. 8 , the buffer circuit  540  can reduce the load observed by the LEQ  150 ; in addition, the common mode voltage of the LEQ  150  and the common mode voltage of the OOBS circuit  160  can be adjusted independently. 
     In some embodiments, the voltage Vb is greater than the voltage at the input terminal of the OOBS circuit  160 . 
       FIG. 9  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  900  includes a signal receiving terminal  910 , a resistor  920 , a resistor  930 , the buffer circuit  140 , a capacitor  970 , a capacitor  980 , the LEQ  150 , and the OOBS circuit  160 . The receiving circuit  900  is a receiving circuit of the alternating current (AC) coupling mode. 
     The input signal Vin is inputted into the receiving circuit  900  through the signal receiving terminal  910  (i.e., the signal receiving terminal  910  receives the input signal Vin). The resistor  920  is coupled between the first reference voltage and the signal receiving terminal  910 . The resistor  930  is a variable resistor, and is coupled between the input terminal of the LEQ  150  and the bias voltage Vbias. The capacitor  970  is coupled between the signal receiving terminal  910  and the LEQ  150 ; more specifically, one end of the capacitor  970  is electrically connected to the signal receiving terminal  910 , and the other end of the capacitor  970  is electrically connected to the LEQ  150  and the resistor  930 . The capacitor  980  is coupled between the signal receiving terminal  910  and the buffer circuit  140 ; more specifically, one end of the capacitor  980  is electrically connected to the signal receiving terminal  910 , and the other end of the capacitor  980  is electrically connected to the input terminal of the buffer circuit  140 . The bias voltage Vbias can be a divided voltage of the power supply voltage VDD. The buffer circuit  140  is coupled between the resistor  930  and the OOBS circuit  160 ; more specifically, the input terminal of the buffer circuit  140  is electrically connected to the resistor  930 , and the output terminal of the buffer circuit  140  is electrically connected to the input terminal of the OOBS circuit  160 . 
     The input terminal of the buffer circuit  140  receives the voltage Vb which is the divided voltage on the resistor  930 . In other words, the voltage Vb can be changed by adjusting the resistance of the resistor  930 . Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the OOBS circuit  160 . 
     In some embodiments, the voltage Vb is greater than the voltage at the input terminal of the LEQ  150 . 
     One of the purposes of the buffer circuit  140  is to separate the LEQ  150  and the OOBS circuit  160  in a way that the input terminal of the LEQ  150  and the input terminal of the OOBS circuit  160  are not electrically connected to each other. As a result, the common mode voltage of the LEQ  150  and the common mode voltage of the OOBS circuit  160  can be adjusted independently. 
     Another purpose of the buffer circuit  140  is to reduce the load observed by the OOBS circuit  160 ; therefore, the data transmission rate of the receiving circuit  100  can be improved. 
       FIG. 10  is a circuit diagram of the receiving circuit of the deserializer according to another embodiment of the present invention. The receiving circuit  1000  is similar to the receiving circuit  900 , except that the LEQ  150  and the OOBS circuit  160  are interchanged. The receiving circuit  1000  is a receiving circuit of the AC coupling mode. In the embodiment of  FIG. 10 , the buffer circuit  140  can reduce the load observed by the LEQ  150 ; in addition, the common mode voltage of the LEQ  150  and the common mode voltage of the OOBS circuit  160  can be adjusted independently. Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the LEQ  150 . 
     In some embodiments, the voltage Vb is greater than the voltage at the input terminal of the OOBS circuit  160 . 
     In the embodiments discussed above the transistors are embodied by MOSFETs; however, this is for illustrative purposes only, and the present disclosure is not limited thereto. People having ordinary skill in the art know how to use the bipolar junction transistors (BJTs) to replace the MOSFETs. 
     The receiving circuit of the deserializer of the present invention includes a buffer circuit. One of the purposes of the buffer circuit is to separate the LEQ and the OOBS circuit in a way that the input terminals of the two components are not electrically connected. As a result, the input load of the LEQ or the OOBS circuit is reduced, and the common mode voltages of the two components can be adjusted independently. Therefore, the receiving circuit of the deserializer of the present invention does not have the load stacking issue and can thus achieve the effect of high-speed data transmission without attenuation. 
     The shape, size, and ratio of any element in the disclosed figures are exemplary for understanding, not for limiting the scope of this invention. 
     The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.