Patent Publication Number: US-8120287-B2

Title: High efficiency power system for a LED display system

Description:
FIELD OF THE INVENTION 
     The present invention is related generally to a Light Emitting Diode (LED) display system and, more particularly, to a high efficiency power system for a LED display system. 
     BACKGROUND OF THE INVENTION 
       FIG. 1  is a systematic diagram of a conventional LED display system  100  for advertising board applications, which includes an AC/DC converter  102  to provide 5V power for a display panel  104 . The display panel  104  includes LED light sources  106 ,  110  and  114  and drivers  108 ,  112  and  116  to drive the LED light sources  106 ,  110  and  114 , respectively. Each LED light source  106  includes multiple LEDs  118 , each LED light source  110  includes multiple LEDs  120 , and each LED light source  114  includes multiple LEDs  122 . Both of the LEDs  118  and  120  have a forward voltage of about 2.2V, the LED  122  has a forward voltage of about 3.6V, the AC/DC converter  102  provides a supply voltage of 5V, and therefore, to avoid the residue in the supply voltage makes the LEDs  118 ,  120  and  122  over heated to be damaged, each of the LEDs  118 ,  120  and  122  is serially connected with a respective resistor Rc serving a heat sinker to share heat that would be generated by the LEDs  118 ,  120  and  122 . 
     However, there is a distance between the AC/DC converter  102  and the display panel  104 , and thus the resistance Rp of the power lines and the resistance Rg of the ground lines between the AC/DC converter  102  and the display panel  104  will induce a lot of power consumption. In addition, the heat sinker resistors Rc also induce a lot of power consumption. That is, because of the resistances Rp, Rg and Rc, there will be low efficiency and large power consumption in the conventional LED display system  100 . Moreover, in the conventional LED display system  100 , too much heat induces the degradation of LED performance. 
     Therefore, it is desired a high efficiency power system for a LED display system. 
     SUMMARY OF THE INVENTION 
     According to the present invention, a LED display system includes a plurality of LEDs, a power converter, a plurality of drivers. The plurality of drivers are used to drive the plurality of LEDs, each of the drivers has a plurality of LED pins each of which is connected to a respective one of the plurality of LEDs, and each of the drivers provides a feedback signal at a feedback pin. The power converter is used to convert a DC high voltage to at least a DC low voltage for the plurality of LEDs, and regulate the at least a DC low voltage according to one of the feedback signal. 
     According to the present invention, a LED display system includes a plurality of LEDs, a power converter, and a plurality of drivers. The power converter converts a DC high voltage to at least a DC low voltage for the plurality of LEDs, the plurality of drivers are used to drive the plurality of LEDs. Each of the drivers has a plurality of LED pins each of which is connected to a respective one of the plurality of LEDs, and each of the drivers receives a first digital signal and provides a second digital signal as the first digital signal of the next driver, and the second digital signal of the last driver is used to regulate the at least a DC low voltage. 
     According to the present invention, a driver for a LED display system includes a plurality of LED pins, a feedback pin, a minimum voltage selector, and a gain stage. Each of the LED pins is connected to a LED. The minimum voltage selector selects the minimum one of the voltages at the plurality of LED pins, the gain stage generates a feedback signal according to the minimum voltage, and the feedback pin provides the feedback signal to regulate a supply voltages for the LEDs. 
     According to the present invention, a driver for a LED display system includes a plurality of LED pins, a feedback pin, a plurality of current sources, a maximum voltage selector, and a gain stage. Each of the LED pins is connected to a LED. Each of the plurality of current sources controls a respective one of the driving currents in the LEDs, and has a resistor and a transistor connected between the LED pin it is connected and the resistor, and an operational amplifier having a first input connected to a voltage node, a second input connected to the node between the resistor and transistor, and an output connected to the gate of the transistor. The maximum voltage selector selects the maximum one of the gate voltages of the transistors, the gain stage generates a feedback signal according to the maximum voltage, and the feedback pin provides the feedback signal to regulate a supply voltages for the LEDs. 
     According to the present invention, a driver for a LED display system includes a plurality of LED pins, a feedback pin to provide a feedback signal, a minimum voltage selector, a gain stage, a current source, a switch connected between the feedback pin and a ground node, and a DC-to-PWM converter. Each of the LED pins is connected to a LED. The minimum voltage selector selects the minimum one of the voltages at the plurality of LED pins, the gain stage generates a DC signal according to the minimum voltage, the current source is connected to the feedback pin, the DC-to-PWM converter converts the DC signal to a pulse width modulation (PWM) signal according to the signal at the feedback pin to switch the switch to modulate the signal at the feedback pin, the feedback signal is used to regulate a supply voltages for the LEDs. 
     According to the present invention, a driver for a LED display system includes a plurality of LED pins, a feedback pin, a minimum voltage sampler, and a gain stage. Each of the LED pins is connected to a LED. The minimum voltage sampler samples the minimum one of the voltages at the plurality of LED pins, the gain stage generates a feedback signal according to the minimum voltage, and the feedback pin provides the feedback signal to regulate a supply voltage for the LEDs. 
     According to the present invention, a driver for a LED display system includes a plurality of LED pins, a minimum voltage sampler, a gain stage, two hysteretic comparators, and a logic circuit. Each of the LED pins is connected to a LED. The minimum voltage sampler samples the minimum one of the voltages at the plurality of LED pins, the gain stage generates a first signal according to the minimum voltage, the first hysteretic comparator compares the first signal with a first reference voltage to generate a second signal, the second hysteretic comparator compares the first signal with a second reference voltage to generate a third signal, the logic circuit generates a digital output signal according to the second and third signals and a digital input signal to regulate a supply voltages for the LEDs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a systematic diagram of a conventional LED display system for advertising board applications; 
         FIG. 2  is a systematic diagram of a LED display system according to the present invention; 
         FIG. 3  is a circuit diagram of a first embodiment for the LED driver of  FIG. 2 ; 
         FIG. 4  is a circuit diagram of a first embodiment for the feedback mechanism of the LED driver shown in  FIG. 3 ; 
         FIG. 5  is a circuit diagram of an embodiment for the buffer shown in  FIG. 4 ; 
         FIG. 6  is a circuit diagram of a second embodiment for the feedback mechanism of the LED driver shown in  FIG. 3 ; 
         FIG. 7  is a circuit diagram of an embodiment for the buffer shown in  FIG. 6 ; 
         FIG. 8  is a circuit diagram of a third embodiment for the feedback mechanism of the LED driver shown in  FIG. 3 ; 
         FIG. 9  is a waveform diagram of the circuit of  FIG. 8 ; 
         FIG. 10  is a circuit diagram of a second embodiment for the LED driver of  FIG. 2 ; 
         FIG. 11  is a circuit diagram of a second embodiment for the feedback mechanism of the LED driver shown in  FIG. 10 ; 
         FIG. 12  is a systematic diagram of another LED display system according to the present invention; 
         FIG. 13  is a circuit diagram of a portion of the LED driver shown in  FIG. 12 ; and 
         FIG. 14  is a circuit diagram of another portion of the LED driver other than that of  FIG. 13 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  is a systematic diagram of a LED display system  200  according to the present invention, in which an AC/DC converter  202  converts an AC voltage to a DC high voltage of 20V for a display panel  204 . Since it is a DC high voltage of 20V provided by the AC/DC converter  202 , the currents flowing through the global power lines having the resistance Rs are so small that the power consumed by the line resistance Rs is significantly reduced, and the efficiency of the LED display system  200  is improved. On the display panel  204 , a DC/DC converter  206  converts the 20V DC high voltage to 2.4V DC low voltage VLED 1  for red and green LED light sources  208  and  212 , and 3.8V DC low voltage VLED 2  for blue LED light sources  216 . Each LED light source  208  includes multiple LEDs  220 , each LED light source  212  includes multiple LEDs  222 , and each LED light source  216  includes multiple LEDs  224 . Multiple LED drivers  210  are employed to drive the LED light sources  208  respectively, multiple LED drivers  214  are employed to drive the LED light sources  212  respectively, and multiple LED drivers  218  are employed to drive the LED light sources  216  respectively. In the LED display system  200 , the feedback pins FB of the LED drivers  210  and  214  are all connected to a feedback input pin FB 1  of the DC/DC converter  206 , and the feedback pins FB of the LED drivers  218  are all connected to a feedback input pin FB 2  of the DC/DC converter  206 , by which feedback signals FB 1  and FB 2  are provided for LED supply voltage control, i.e., the DC/DC converter  206  could regulate the supply voltages VLED 1  and VLED 2  slightly higher than the forward voltages of the LEDs  220 ,  222  and  224  to reduce heat generation on the LEDs  220 ,  222  and  224  and thus there is no need of heat sinker resistors. Therefore, the efficiency of the LED display system  200  is further improved, and the total component cost is reduced. Furthermore, with the LED supply voltage control, the LED display system  200  could provide lower supply voltages VLED 1  and VLED 2  for the LEDs  220 ,  222  and  224 , and thus minimize the impact of LED aging. 
       FIG. 3  is a circuit diagram of a first embodiment for the LED driver  210  of  FIG. 2 . Referring to  FIGS. 2 and 3 , in addition to the feedback pin FB, the LED driver  210  further includes a data clock pin CLK to receive a data clock, a data input pin SDI for data input, an output enable pin OE to receive an output enable signal, a data output pin SDO for data output, and LED pins PLED 1 , PLED 2 , . . . , PLEDM, each of which is connected to a respective LED  220 . In the LED driver  210 , multiple current sources  300  are connected to the LED pins PLED 1 -PLEDM to control the driving currents ILED 1 , ILED 2 , . . . , ILEDM flowing through the LEDs  220 , respectively. The output enable signal received from the output enable pin OE determines to turn on or turn off the current sources  300 . Each current source  300  includes a transistor  304  and a resistor Rx 1  serially connected between its LED pin PLEDj (j=1, 2, . . . , M) and a ground node GND, and an operational amplifier  302  having a non-inverting input connected to a node N 1 , an inverting input connected to a node N 2 , and an output connected to the gate of the transistor  304 . 
       FIG. 4  is a circuit diagram of a first embodiment for the feedback mechanism of the LED driver  210  shown in  FIG. 3 , which includes a minimum voltage selector  400  to monitor the voltages at the LED pins PLED 1 -PLEDM. Referring to  FIG. 3 , since a same supply voltage VLED is provided for all the LEDs  220 , for any LED pin PLEDj, the voltage thereon will be related to the forward voltage of the LED  220  connected thereto. In further detail, the lower the voltage at the LED pin PLEDj is, the greater the forward voltage of the LED  220  connected to the LED pin PLEDj is. Referring to  FIG. 4 , the minimum voltage selector  400  selects the minimum one from the voltages at the LED pins PLED 1 -PLEDM to provide for a gain stage  402  to generate a feedback signal VS 1 . After being amplified by the gain stage  402 , the feedback signal VS 1  will have higher noise margin and thereby avoid the influence caused by the line resistance of the power line. In the gain stage  402 , a buffer  404  has a non-inverting input connected to the output of the minimum voltage selector  400 , a variable resistor RG 2  is connected between an inverting input and an output of the buffer  404 , a resistor RG 1  is connected between the inverting input of the buffer  404  and a node N 3 , a gain controller  406  controls the resistance of the variable resistor RG 2  to control the gain of the gain stage  402 , a switch SW 1  is connected between a compensation circuit  408  and the node N 3 , and a switch SW 2  is connected between the node N 3  and the ground node GND. Referring to  FIGS. 3 and 4 , since the on-resistance of the transistor  304  in the current source  300  possibly varies with temperature, a temperature variation may induce error in the feedback signal VS 1 . Therefore, the compensation circuit  408  is preferably employed to eliminate the error.  FIG. 5  is a circuit diagram of an embodiment for the buffer  404  shown in  FIG. 4 . As shown in  FIG. 4 , all the LED drivers  210  have their feedback pins FB common connected to the feedback input pin FB 1  of the DC/DC converter  206 , and the buffer  404  has higher sinking capability than sourcing capability as shown in  FIG. 5 , so that the signal at the feedback input pin FB 1  of the DC/DC converter  206  will be the minimum one of the feedback signals VS 1  applied to the feedback pins FB and therefore, the DC/DC converter  206  can provide a lower and appropriate supply voltage VLED 1  for all the LED light sources  208 . Referring to  FIG. 4 , the DC/DC converter  206  includes an error amplifier  410  to compare the feedback signal received from the feedback input pin FB 1  with a reference voltage VREF to generate an error signal for the DC/DC converter  206  to regulate the supply voltage VLED 1 . 
       FIG. 6  is a circuit diagram of a second embodiment for the feedback mechanism of the LED driver  210  shown in  FIG. 3 , in which a maximum voltage selector  500  monitors the gate voltages Vg 1 , Vg 2 , . . . , VgM of all the transistors  304  shown in  FIG. 3  and selects the maximum one therefrom to provide for a gain stage  502  to generate a feedback signal VS 2 . After being amplified by the gain stage  502 , the feedback signal VS 2  will have higher noise margin and thereby avoid the influence caused by the line resistance of the power line. In the gain stage  502 , voltage divider resistors RG 1  and RG 2  divides the output of the maximum voltage selector  500  to generate a voltage VD, a buffer  506  buffers the voltage VD to generate the feedback signal VS 2 , and a gain controller  504  controls the resistance of the variable resistor RG 2  to control the gain of the gain stage  502 .  FIG. 7  is a circuit diagram of an embodiment for the buffer  506  shown in  FIG. 6 . As shown in  FIG. 6 , all the LED drivers  210  have their feedback pins FB common connected to the feedback input pin FB 1  of the DC/DC converter  206 , and the buffer  506  has higher sourcing capability than sinking capability as shown in  FIG. 7 , so that the signal at the feedback input pin FB 1  of the DC/DC converter  206  will be the maximum one of the feedback signals VS 2  applied to the feedback pins FB. Referring to  FIG. 6 , the DC/DC converter  206  includes an error amplifier  508  to compare the feedback signal received from the feedback input pin FB 1  with a reference voltage VREF to generate an error signal for the DC/DC converter  206  to regulate the supply voltage VLED 1 . 
       FIG. 8  is a circuit diagram of a third embodiment for the feedback mechanism of the LED driver  210  shown in  FIG. 3 , and  FIG. 9  is a waveform diagram of the circuit of  FIG. 8 . Referring to  FIGS. 3 and 8 , the LED driver  210  includes a minimum voltage selector  600  to monitor the voltages at the LED pins PLED 1 -PLEDM and select the minimum one therefrom for a gain stage  602  to generate a DC signal VDC, a DC-to-PWM converter  610  to convert the DC signal VDC to a constant on-time PWM signal Spwm as shown by the waveform  620  of  FIG. 9  according to the feedback signal VS 3  at the feedback pin FB, and a switch  612  connected between the feedback pin FB and a ground node GND. As shown in  FIG. 8 , all the LED drivers  210  have their feedback pins FB common connected to the feedback input pin FB 1  of the DC/DC converter  206 , and the switch  612  connected between the feedback pin FB and the ground node GND has higher sinking capability than sourcing capability, so that the signal at the feedback input pin FB 1  of the DC/DC converter  206  will be the minimum one of the feedback signals VS 3  applied to the feedback pins FB. Referring to  FIGS. 8 and 9 , during the on time of the PWM signal Spwm, for example, from time t 1  to time t 2 , the switch  612  is off and therefore, a current source  614  will charge the feedback pin FB so that the feedback signal VS 3  will rise as shown by the waveform  618  of  FIG. 9 . During the off time of the PWM signal Spwm, for example, from time t 2  to time t 3 , the switch  612  is on and therefore, the feedback pin FB is connected to the ground node GND through the switch  612  so that the feedback signal VS 3  will go down. 
     Referring to  FIG. 8 , in the gain stage  602 , a buffer  606  has a non-inverting input connected to the output of the minimum voltage selector  600 , a variable resistor RG 2  is connected between an inverting input and an output of the buffer  606 , a resistor RG 1  is connected between the inverting input of the buffer  606  and a node N 4 , a gain controller  608  controls the resistance of the variable resistor RG 2  to control the gain of the gain stage  602 , a switch SW 3  is connected between a compensation circuit  604  and the node N 4 , a switch SW 4  is connected between the node N 4  and the ground node GND, and the compensation circuit  604  eliminates the error caused by temperature variation. In the DC/DC converter  206 , an error amplifier  616  compares the feedback signal received from the feedback input pin FB 1  with a reference voltage VREF to generate an error signal for the DC/DC converter  206  to regulate the supply voltage VLED 1 . 
       FIG. 10  is a circuit diagram of a second embodiment for the LED driver  210  of  FIG. 2 , which also includes multiple current sources  300  to drive multiple LEDs  220  respectively, and an on/off controller  700  provides control signals EN 1 , EN 2 , . . . , ENM according to an output enable signal received from an output enable pin OE, to individually determine to enable each respective one of the current sources  300 .  FIG. 11  is a circuit diagram of an embodiment for the feedback mechanism of the LED driver  210  shown in  FIG. 10 , in which a minimum voltage sampler  702  samples the minimum one of the voltages at the LED pins PLED 1 -PLEDM to provide for a gain stage  704  to generate a feedback signal VS 4  applied to the feedback pin FB. After being amplified by the gain stage  704 , the feedback signal VS 4  will have higher noise margin and thereby avoid the influence caused by the line resistance of the power line. In the gain stage  704 , a buffer  708  has a non-inverting input connected to the output of the minimum voltage sampler  702 , a variable resistor RG 2  is connected between an inverting input and an output of the buffer  708 , a resistor RG 1  is connected between the inverting input of the buffer  708  and a node N 5 , a switch SW 5  is connected between a compensation circuit  706  and a node N 5 , a switch SW 6  is connected between the node N 5  and a ground node GND, and, a gain controller  710  controls the resistance of the variable resistor RG 2  to control the gain of the gain stage  704 . 
     As shown in  FIG. 11 , all the LED drivers  210  have their feedback pins FB common connected to the feedback input pin FB 1  of the DC/DC converter  206 , and the buffer  708  has higher sinking capability than sourcing capability, so that the signal at the feedback input pin FB 1  of the DC/DC converter  206  will be the minimum one of the feedback signals VS 4  applied to the feedback pins FB. The buffer  708  has the same circuit as that of  FIG. 5 . In the DC/DC converter  206 , a hysteretic comparator  712  compares the signal received from the feedback pin FB 1  with a reference voltage VR 1  to generate a comparison signal Sc 1 , a hysteretic comparator  714  compares the signal received from the feedback pin FB 1  with a reference voltage VR 2  to generate a comparison signal Sc 2 , a logic circuit  716  generates a digital signal SD according to the comparison signals Sc 1  and Sc 2 , a digital-to-analog converter (DAC)  718  converts the digital signal SD to an analog signal SA, and an error amplifier  720  compares the analog signal SA with a reference voltage VR 3  to generate an error signal for the DC/DC converter  206  to regulate the supply voltage VLED 1 . In another embodiment, the error amplifier  720  may directly compare the signal received from the feedback input pin FB 1  with the reference voltage VR 3  to generate the error signal for the DC/DC converter  206  to regulate the supply voltage VLED 1 . 
     Although the above embodiments only illustrate the LED driver  210  in detail, any one skilled in the art may implement the LED drivers  214  and  218  in the same manner. 
       FIG. 12  is a systematic diagram of another LED display system  800  according to the present invention, in which an AC/DC converter  801  converts an AC voltage to a DC high voltage of 20V, a host  802  provides a data clock, a data signal and an output enable signal to the data clock input pin CLK, data input pin SDI and output enable pin OE of a DC/DC converter  804 , the DC/DC converter  804  converts the DC high voltage to a DC low voltage VLED for multiple LED light sources  806 , each LED light source  806  includes multiple parallel connected LEDs  808 , and multiple LED drivers  810  drive the LED light sources  806  respectively. Among the LED drivers  810 , the first one provides a data signal according to the data clock, data signal and output enable signal from the host  802 , through a data output pin SDO to a data input pin SDI of the next LED driver  810 , each of the other LED drivers  810  provides a data signal according to the data clock and output enable signal from the host  802  and the data signal from the previous LED driver  810  for its next LED driver  810 , and the last LED driver  810  provides a data signal fed back to the host  802 . The host  802  signals the DC/DC converter  804  according to the feedback data signal to regulate the supply voltage VLED to be slightly higher than the forward voltages of the LEDs  808 . Therefore, there is no need of heat sinker resistors, the efficiency is improved and the total component cost is reduced. 
       FIG. 13  is a circuit diagram of a portion of the LED driver  810  shown in  FIG. 12 , in which each of LED pins PLED 1 , PLED 2 , . . . , PLEDM is connected to a respective LED  808 , each of current sources  812  is connected to a respective one of the LED pins PLED 1 -PLEDM to drive the LED  808  connected thereto, an on/off controller  814  generates control signals EN 1 , EN 2 , . . . , ENM according to the output enable signal received from the output enable pin OE, to individually determine to enable each respective one of the current sources  812 .  FIG. 14  is a circuit diagram of another portion of the LED driver  810  other than that of  FIG. 13 . Taking the first LED driver  810  for example, it includes a minimum voltage sampler  816  to sample the minimum one of the voltages at the LED pins PLED 1 -PLEDM for a gain stage  818  to generate a signal VS 5 , a hysteretic comparator  826  to compare the signal VS 5  with a reference voltage VR 1  to generate a comparison signal Sc 3 , a hysteretic comparator  828  to compare the signal VS 5  with a reference voltage VR 2  to generate a comparison signal Sc 4 , and a logic circuit  830  to generate a digital signal SD according to the signal received from the data input pin SDI and the comparison signals Sc 3  and Sc 4  to provide for the next LED driver  810  through the data output pin SDO. The signal SD is a digital signal and thus can avoid the influence of noise caused by the line resistance of the power line. 
     In the gain stage  818 , a buffer  822  has a non-inverting input connected to the output of the minimum voltage sampler  816 , a variable resistor RG 2  is connected between the output and an inverting input of the buffer  822 , a resistor RG 1  is connected between the inverting input of the buffer  822  and a node N 6 , a switch SW 5  is connected between a compensation circuit  820  and the node N 6 , a switch SW 6  is connected between the node N 6  and the ground node GND, and a gain controller  824  controls the resistance of the variable resistor RG 2  to control the gain of the gain stage  818 . 
     While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.