Patent Publication Number: US-7592847-B2

Title: Phase frequency detector and phase-locked loop

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of U.S. Provisional Application No. 60/896,285, filed at Mar. 22, 2007, incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a phase-locked loop device and more particularly to a phase-locked loop device with switched-delay phase frequency detector. 
   2. Description of the Related Art 
   A phase-locked loop (PLL) device, is a major component applied in frequency generators, wireless receivers, communication devices and so on. Referring to  FIG. 1 .  FIG. 1  is a schematic diagram of a conventional PLL device. PFD unit  11  receives a reference clock signal REF_CK and a feedback clock signal FBK_CK and measures the phase and frequency difference therebetween to output phase difference signals, UP and DN. Charge pump circuit  12  receives and transforms the phase difference signals UP and DN into a current to charge loop filter  13 . In  FIG. 1 , a circuit of a conventional loop filter  13  is provided. The loop filter  13  receives the current from charge pump circuit to limit the rate of change of a capacitor voltage, VCON, resulting in slow rising or falling voltage corresponding to the phase and frequency differences. The voltage-controlled oscillator (VCO)  14  generates an output clock signal according to the voltage VCON. Feedback divider  15  has a parameter N to generate the feedback clock signal FBK_CK, wherein the period of the feedback clock signal FBK_CK is N times the period of the output clock signal. In an ideal situation, when the PLL is in in-lock state, the phase difference signal UP synchronizes to the phase difference signal DN. 
     FIG. 2  is a schematic diagram of a phase frequency detector and charge pump circuit. The phase frequency detector  21  comprises a first D flip-flop  23 , a second D flip-flop  24 , an AND gate  26  and a delay unit  25  with a delay T d . The phase frequency detector  21  output two signals UP and DN to control the charge pump circuit  22 . When the phase frequency detector  21  and the charge pump circuit is locked in a PLL device, the timing diagram of a related signal of the phase frequency detector  21  is shown in  FIG. 3 , where the high-level pulse widths of signals UP or DN respectively are T pup  and T pdn . Assume the signals UP and DN are perfectly matched, in other words, I up =I dn =I and T pup =T pdn =T d . When a PLL device is locked, the voltage on the loop filter is fixed because the net charge provided by the charge pump circuit should be zero. To maintain the locked condition, the following equation is satisfied:
   I   up   ·T   pup   =I   dn   ·T   pdn   (1) 
   However, if the current I up  and I dn  are not matched, to satisfy the equation (1), the pulse widths T pup  and T pdn  need to be adjusted. Assume that the down current I dn  is only 80% of the up current I up , i.e. I dn =0.8·I up . To satisfy the equation (1), the pulse width T pdn  is 125% of the pulse width T pup . Because the phase frequency detector  21  aligns the falling edges of the signals UP and DN, the rising edge of the signal DN leads the rising edge of the signal UP due to the different pulse widths T pup  and T pdn . If the duration of the pulse width T pup  is 1 ns, it results in a static phase error of 0.25 ns. Similarly, if the down current I dn  is smaller than the up current I up , the rising edge of the signal UP therefore leads the rising edge of the signal DN due to the different pulse widths T pup  and T pdn . 
   BRIEF SUMMARY OF THE INVENTION 
   An embodiment of the invention provides a phase-locked loop comprising a switched-delay phase frequency detector, a charge pump circuit, a loop filter and a voltage-controlled oscillator. The phase frequency detector with switched-delay measures a reference signal and a clock signal of the PLL device to output an up signal and a down signal. The charge pump circuit receives and transforms the up signal and the down signal into a current. The loop filter receives and transforms the current into a voltage. The voltage-controlled oscillator receives the voltage and outputs the clock signal. Wherein when the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on a first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on a second delay. 
   Another embodiment of the invention provides a phase detector comprising a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay. 
   A detailed description is given in the following embodiments with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
       FIG. 1  is a schematic diagram of a conventional PLL device. 
       FIG. 2  is a block diagram of a conventional phase frequency detector and a conventional charge pump circuit. 
       FIG. 3  is a timing diagram of the phase frequency detector and the charge pump circuit in  FIG. 2 . 
       FIG. 4  is a block diagram of a PLL device with switched-delay phase frequency detector in accordance with an embodiment of the invention 
       FIG. 5  is a block diagram of a phase frequency detector and a charge pump circuit according to an embodiment of the invention. 
       FIG. 6  is a timing diagram of the phase frequency detector  41  and the charge pump circuit  44  in  FIG. 5 . 
       FIG. 7  is a schematic diagram of a lock detector according to an embodiment of the invention. 
       FIG. 8  is a schematic diagram of a BBPD according to an embodiment of the invention. 
       FIG. 9  is a schematic diagram of a SAR controller according to an embodiment of the invention. 
       FIG. 10  is a circuit diagram of a charge pump circuit with current calibration circuit according to an embodiment of the invention. 
       FIG. 11  is a schematic diagram of a SAR cell according to an embodiment of the invention. 
       FIG. 12  is a diagram showing the response of the phase error. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     FIG. 4  is a block diagram of a PLL device with switched-delay phase frequency detector in accordance with an embodiment of the invention. The PLL device comprises a switched-delay phase frequency detector  41 , a lock detector  42 , a bang bang phase detector (BBPD)  43 , a charge pump circuit  44 , a current calibration unit  45 , a SAR controller  46 , a loop filter  47 , a voltage-controlled oscillator  48  and a feedback divider  49 . The switched-delay phase frequency detector  41  receives a reference clock signal Ref and a feedback clock signal Clk and measures the phase and frequency difference therebetween to output an up signal (UP) and a down signal (DN). The switched-delay phase frequency detector  41  comprises at least two different delay times, the first delay T d  and the second delay T d     —     en . When the reference clock signal Ref does not synchronize with the feedback clock signal Clk and the charge pump currents are not calibrated, the switched-delay phase frequency detector selects the second delay T d     —     en , wherein the first delay T d  is smaller than the second delay T d     —     en . 
   The lock detector  42  detects the reference clock signal Ref and the feedback clock signal Clk, and outputs a control signal S 2  to the SAR controller  46 . When the SAR controller  46  receives the control signal S 2 , the SAR controller  46  is first initialized. Then, the SAR controller  46  controls the current calibration unit  45  according to the control signal S 3  from the BBPD  43 . The charge pump circuit  44  generates an up current to charge the loop filter  47  and a down current to discharge the loop filter. The current calibration unit  45  calibrates the up current or the down current according to the SAR controller  46 . When the SAR controller  46  finishes the current calibration, the SAR controller  46  outputs the control signal S 1  to control the switched-delay phase frequency detector  41  to select the first delay T d . The charge pump circuit  44  receives and transforms the signals UP and DN into a current to charge loop filter  47 . The loop filter  47  receives and transforms the current into a voltage corresponding to the signals UP and DN. The voltage-controlled oscillator  48  generates an output clock signal according to the voltage from the loop filter  47 . Feedback divider  49  has a parameter N to generate the feedback clock signal Clk, wherein the period of the feedback clock signal Clk is N times the frequency of the output clock signal. 
     FIG. 5  is a block diagram of a phase frequency detector and a charge pump circuit according to an embodiment of the invention. The phase frequency detector  41  comprises a first D flip-flop  51 , a second D flip-flop  52 , a multiplexer  53 , a first delay unit  54 , a second delay unit  55  and an AND gate  56 . The D inputs of the first D flip-flop  51  and the second D flip-flop  52  are connected to a high voltage V DD . The clock inputs of the first D flip-flop  51  and the second D flip-flop  52  respectively receive the reference clock signal Ref and feedback clock signal Clk and respectively output the signals UP and DN, wherein the falling edge of the signal UP synchronizes with the falling edge of the signal DN. The AND gate  56  receives the signals UP and DN and outputs an output signal to the first delay unit  54  or the second delay unit  55 . The first delay unit  54  delays the output signal from the AND gate  56  with a first delay and the second delay unit  55  delays the output signal from the AND gate  56  with a second delay, wherein the second delay is larger than the first delay. In some embodiment, the first delay is 1 nanosecond and the second delay is 20 nanoseconds. 
   The multiplexer  53  has two input terminals and an output terminal, wherein the two input terminals are respectively coupled to the output terminals of the first delay unit  54  and the second delay unit  55 , and the output terminal is coupled to the first D flip-flop  51  and the second D flip-flop  52 . The multiplexer  53  transmits the output data from the first delay unit  54  or the second delay unit  55  based on the control signal S 1 . In one embodiment, when the reference clock signal Ref synchronizes with the feedback clock signal Clk and the charge pump currents are calibrated, the phase frequency detector  41  selects the first delay unit, and when the reference clock signal Ref does not synchronize with the feedback clock signal Clk and the charge pump currents are not calibrated, the phase frequency detector  41  selects the second delay unit. 
   The charge pump circuit  44  comprises a first current source  57 , a first switch SW 1 , a second switch SW 2 , and a second current source  58 . The connections of the described elements are shown in  FIG. 5  and are not described for brevity. In an ideal condition, the signals UP and DN simultaneously turn on and turn off the switches SW 1  and SW 2 , however, if the currents generated by the first current source  57  an the second current source  58  are mismatched, such as described in paragraph [0005], the high-level pulse widths change to satisfy the equation (1). 
   Referring to  FIG. 6 , a timing diagram of the phase frequency detector  41  and the charge pump circuit  44  in  FIG. 5  is illustrated. In  FIG. 6 , assume that the down current I dn  is 80% of the up current I up , and the high-level pulse widths of the signal UP and DN respectively are 1 nanosecond and 1.25 nanoseconds. In  FIG. 6 , we can find that the rising edge of the signal DN leads the signal UP, and this causes static error generated during the time period T 1 . In an ideal situation, the voltage at the node N, Vc, should be constant. However, in the described condition, the voltage Vc shifts, and the shift voltage Vr causes the clock frequency of the output signal of the voltage-controlled oscillator shifts. This damages the performance of the PLL device. 
   Although we can adjust the high-level pulse widths of the signal UP and DN to satisfy the equation (1), it results in the static phase error. Therefore, the preferred method to calibrate the current mismatch is to directly calibrate the current in the charge pump circuit  44 . Furthermore, we can use a bang-bang phase detector (BBPD) to detect the static phase error. When the bang-bang phase detector detects the phase error, it indicates that the current mismatch has occurred in the charge pump circuit  44 . 
   In a conventional phase frequency detector, only one delay unit is applied. Taking the embodiment shown in  FIG. 6  as an example, the static phase error is only 0.25 ns. Since the phase error is larger than the minimum detectable timing error of traditional BBPD, Δt min , the calibration resolution is still not good enough. As for a conventional BBPD fabricated utilizing standard 0.18 μm CMOS technology, its minimum detectable timing error, Δt min , is normally 50 μs. Namely, the calibration resolution is only 5% for the reset delay, T d =1 ns. 
   To increase the calibration resolution, if one can multiply the normal reset delay, T d , by a factor of 20, the static phase error would also be multiplied by the same factor and the calibration resolution would also be enhanced by 20. The resolution enhancement factor A res  is defined as 
   
     
       
         
           
             
               
                 
                   A 
                   res 
                 
                 = 
                 
                   
                     T 
                     d_en 
                   
                   
                     T 
                     d 
                   
                 
               
             
             
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
   
   wherein T d     —     en  represents the delay generated by the second delay unit  55  in  FIG. 5  and the second delay T d     —     en  is 20 ns. However, the second delay T d     —     en  can not be increased indefinitely. The maximum reset delay for a PFD should be less than half of the period, T ref , of the reference clock Ref to maintain a phase-locked system. Hence, the maximum achievable enhance factor, A res     —     max , is determined as 
   
     
       
         
           
             
               
                 
                   A 
                   res_max 
                 
                 = 
                 
                   0.5 
                   · 
                   
                     
                       T 
                       ref 
                     
                     
                       T 
                       d 
                     
                   
                 
               
             
             
               
                 ( 
                 3 
                 ) 
               
             
           
         
       
     
   
   For a BBPD with a minimum detectable timing error, Δt min , the calibration resolution, R cal , is defined as 
   
     
       
         
           
             
               
                 
                   R 
                   cal 
                 
                 = 
                 
                   1 
                   - 
                   
                     
                       
                         A 
                         res 
                       
                       · 
                       
                         T 
                         d 
                       
                     
                     
                       
                         Δ 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           t 
                           min 
                         
                       
                       + 
                       
                         
                           A 
                           res 
                         
                         · 
                         
                           T 
                           d 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 4 
                 ) 
               
             
           
         
       
     
   
   For example, assuming a phase-locked system with a reference clock of 10 MHz and a BBPD with a minimum detectable timing error, Δt min =50 ps. According to equations. (2)-(4), the minimum calibration resolution is 0.05%. 
   However, if the phase frequency detector  41  continuously uses the second delay unit  55  with a longer delay time during the phase-locked period, it would reduce the performance of the PLL device. Thus, the inventions, ‘novel’ phase frequency detector  41  with two different delays is provided to solve the problem. When the PLL device is not locked and the charge pump currents are not calibrated, the control signal S 1  controls the multiplexer  53  to select the second delay unit  55  with longer delay time. When the PLL device is locked, the control signal S 1  controls the multiplexer  53  to select the first delay unit  53  with shorter delay time. 
     FIG. 7  is a schematic diagram of a lock detector according to an embodiment of the invention. The lock detector mainly comprises two parts, a conventional lock detector  71  and a deglitch unit  72 . In the conventional lock detector  71 , the output signal of the AND gate  73  may have glitches and cause faults. Therefore, the lock detector according to an embodiment of the invention adds the deglitch unit  72  to eliminate the glitches. The deglitch unit  72  comprises an AND gate  64  and two D flip-flops (DFF 3  and DFF 4 ). The DFF 3  and DFF 4  are triggered by a clock, which is divided by 32 from the reference clock signal Ref. In this embodiment, the number 32 is only taken as an example, and is not limited to the scope of the invention thereto. When the PLL is locked, in other words, the reference clock signal Ref synchronizes with the feedback clock signal Clk, the output of the AND gate  73  is high. The data terminal of DFF 3  receives the output of the AND gate  73 , wherein the output of DFF 3  is high when the divided-by-32 clock signal is also high. If the output of the AND gate  73  becomes low before the next rising edge of the divided-by-32 clock signal, DFF 3  will be reset, and the control signal S 2  remains low. On the other hand, if the output of the conventional lock detector remains high till the next rising edge of the divided-by-32 clock signal, both the outputs of DFF 3  and DFF 4  is high and the control signal S 2  becomes high to indicate a locked condition of the PLL device. 
     FIG. 8  is a schematic diagram of a BBPD according to an embodiment of the invention. The first D flip-flop (DFF  1 ) receives the signal UP via the D terminal and the signal DN via the clock terminal. The second D flip-flop receives signal DN via D terminal and the signal UP via the clock terminal. When a phase error is generated in the charge pump circuit, the output of the exclusive gate (XOR)  81  is logic “1”. When the signal UP leads the signal DN, the output of the NAND gate  82  is logic “0”, i.e. the signal S 3  is at the low voltage level. When the signal DN leads the signal UP, the output of the NAND gate  82  is logic “1”, i.e. the signal S 3  is at the high voltage level. In an ideal condition, only one D flip-flop can serve as a simple BBPD to determine the phase relation between the signals UP and signal DN. However, in the described design, there is a finite sampling offset and an unbalanced capacitive load for signals UP and DN. In this embodiment, the BBPD detects the phase relation between the signals UP and DN and outputs the control signal S 3  to the SAR controller  46  based on the detection result. 
     FIG. 10  is a circuit diagram of a charge pump circuit with current calibration circuit according to an embodiment of the invention. The charge pump circuit comprises the first reference current source  101  and the second reference current source  102 . The first reference current source  101  provides the up current I up  and the second reference current source  102  provides the down current I down . In this embodiment, the up current I up  is fixed to 200 μA and the down current I down  is within the range from 180 μA to 210 μA. When the BBPD  43  detects a static phase error in the charge pump circuit  44 , the BBPD  43  outputs the control signal S 3  to the SAR controller  46 , and the bit 0   b ˜bit 3   b  in the second reference current source  102  are set to logic “1”. The SAR controller  46  outputs the logic value of the bit 0   b ˜bit 3   b  based on the comparison result of the signals UP and DN. In this embodiment, the up current I up  is 200 μA, and to avoid the current mismatch, the second reference current source  102  should provide the down current I down  with 200 μA. To achieve that, the logic values of bit 0   b ˜bit 3   b  are [1, 0, 1, 0]. 
     FIG. 9  is a schematic diagram of a SAR controller according to an embodiment of the invention. When the lock detector  42  detects that the PLL device is not locked, the lock detector  42  outputs the control signal S 2  to enable the SAR controller illustrated in  FIG. 9 . When the SAR controller receives the control signal S 2 , i.e. the control signal S 2  is logic high, the bits  0  to  3  are reset to logic “0”. When the SAR controller receives the control signal S 3  from the BBPD  43 , the first SAR cell  91  is enabled and the bit 3  will be logic “1” or logic “0” based on the comparison result, i.e. the control signal S 3 . When the bit  3  is determined, the second SAR cell  92  is enabled. As to the operation of the SAR cells  92  to  94 , it is similar to the operation of the SAR cell  91  and will not be described below for brevity. When the SAR controller finishes a current calibration procedure, the D flip-flop  95  outputs the control signal S 3  to the switched-delay PFD  41  and the switched-delay PFD  41  selects the first delay unit  54  with shorter delay time. 
     FIG. 11  is a schematic diagram of a SAR cell according to an embodiment of the invention. The NOR gate  111  receives the output signal from the Q terminal of the D flip-flop  117  and the signal EN. The NOR gate  112  receives the output signal from the  Q  terminal of the D flip-flop  117  and the signal EN. The NAND gate  133  receives the output signal from the Q terminal of the D flip-flop  117  and the signal EN. The NAND gate  114  has two input terminals, wherein one terminal serves as the Shift terminal and the other terminal receives the output signal of the NOR gate  111 . If the SAR cell is used to output the most signal bit (MSB), such as the bit  3  in the  FIG. 9 , the Shift terminal is connected to a high voltage source. If the SAR cell is not used to output the most signal bit (MSB), the Shift terminal is connected to the D terminal of a previous SAR cell. The NAND gate  115  has two input terminals, wherein one terminal serves as the Comp terminal to receive the control signal S 3  and the other input terminal receives the output signal of the NOR gate  112 . The NAND gate  116  receives the output signals from the NAND gate  113 , NAND  114  and NAND  115  to output a signal to the D terminal  117 . The CLR terminal receives the control signal S 2 , and when the control signal S 2  is changed to high, the output signal output via the Q terminal is set to logic “0”. 
   The period of the clock in the 4-bit SAR controller is an important parameter. If the clock period is too short, the synthesizer remains unsteady and the BBPD may fail to provide the correct information. Conversely, if the clock period is too long, the total calibration time increases dramatically. As a result, it is necessary to choose an appropriate clock period for the calibration system. Since the CP is switched during the calibration transient, the synthesizer may experience the phase acquisition. As shown in  FIG. 10 , the largest current step in the down current is 16 μA. In the following analysis, the appropriate clock period for the calibration technique is derived. 
   Assuming the synthesizer is locked before the down current is switched and it is modeled as a linear system. A sudden current change, I incr , of the down current is modeled as a phase step, θ step , as 
                   θ   step     =         (             I   up       I   dn_min       ·     T   d_en       -         I   up         I   dn_min     +     I   incr         ·     T   d_en           T   ref       )     ·   2     ⁢           ⁢   π             (   6   )               
where I dn     —     min  means the smallest down current in the beginning of the calibration process. Let I up , I dn     —     min , I incr , T d     —     ehn , and T ref  be 200 μA, 180 μA, 16 μA, 20 ns, and 100 ns, respectively. According to eq. (6), the phase step is calculated as θ step =0.114 rad or 6.5°.
 
   The phase transfer function, H(s), of the frequency synthesizer on phase domain is shown as 
   
     
       
         
           
             
               
                 
                   
                     H 
                     ⁡ 
                     
                       ( 
                       s 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           θ 
                           out 
                         
                         ⁡ 
                         
                           ( 
                           s 
                           ) 
                         
                       
                       
                         
                           θ 
                           
                             i 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             n 
                           
                         
                         ⁡ 
                         
                           ( 
                           s 
                           ) 
                         
                       
                     
                     = 
                     
                       
                         N 
                         · 
                         
                           ω 
                           C 
                         
                         · 
                         
                           ( 
                           
                             s 
                             + 
                             
                               ω 
                               Z 
                             
                           
                           ) 
                         
                       
                       
                         
                           
                             s 
                             3 
                           
                           
                             ω 
                             P 
                           
                         
                         + 
                         
                           s 
                           2 
                         
                         + 
                         
                           
                             ω 
                             C 
                           
                           · 
                           s 
                         
                         + 
                         
                           
                             ω 
                             C 
                           
                           · 
                           
                             ω 
                             Z 
                           
                         
                       
                     
                   
                 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 where 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 
                   
                     
                       ω 
                       P 
                     
                     = 
                     
                       
                         
                           C 
                           1 
                         
                         + 
                         
                           C 
                           2 
                         
                       
                       
                         
                           C 
                           1 
                         
                         · 
                         
                           C 
                           2 
                         
                         · 
                         
                           R 
                           2 
                         
                       
                     
                   
                   ; 
                   
                       
                   
                   ⁢ 
                   
                     
                       ω 
                       Z 
                     
                     = 
                     
                       1 
                       
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           2 
                         
                       
                     
                   
                   ; 
                   
                       
                   
                   ⁢ 
                   
                     
                       ω 
                       C 
                     
                     = 
                     
                       
                         
                           I 
                           cp 
                         
                         · 
                         
                           K 
                           vco 
                         
                         · 
                         
                           R 
                           2 
                         
                         · 
                         
                           C 
                           2 
                         
                       
                       
                         N 
                         · 
                         
                           ( 
                           
                             
                               C 
                               1 
                             
                             + 
                             
                               C 
                               2 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 7 
                 ) 
               
             
           
         
       
     
   
   and I cp , K VCO , and N denote the nominal charge pump current, the VCO gain, and division ratio, respectively. To simplify the analysis, the system is designed with the maximum phase margin at the unity gain frequency, i.e., 
             γ   ≡       ω   C       ω   Z         =         ω   P       ω   C       .           
Then the phase error transfer function, H e (s), between the phase error and input phase is expressed as
 
   
     
       
         
           
             
               
                 
                   
                     H 
                     e 
                   
                   ⁡ 
                   
                     ( 
                     s 
                     ) 
                   
                 
                 = 
                 
                   
                     1 
                     - 
                     
                       
                         H 
                         ⁡ 
                         
                           ( 
                           s 
                           ) 
                         
                       
                       N 
                     
                   
                   = 
                   
                     
                       
                         s 
                         3 
                       
                       + 
                       
                         
                           ω 
                           C 
                         
                         · 
                         γ 
                         · 
                         
                           s 
                           2 
                         
                       
                     
                     
                       
                         s 
                         3 
                       
                       + 
                       
                         
                           ω 
                           C 
                         
                         · 
                         γ 
                         · 
                         
                           s 
                           2 
                         
                       
                       + 
                       
                         
                           ω 
                           C 
                           2 
                         
                         · 
                         γ 
                         · 
                         s 
                       
                       + 
                       
                         ω 
                         C 
                         3 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 8 
                 ) 
               
             
           
         
       
     
   
   Finally, the step response of the phase error, θ e     —     sr (s), can be derived as 
   
     
       
         
           
             
               
                 
                   
                     θ 
                     e_sr 
                   
                   ⁡ 
                   
                     ( 
                     s 
                     ) 
                   
                 
                 = 
                 
                   
                     
                       
                         θ 
                         step 
                       
                       s 
                     
                     · 
                     
                       
                         H 
                         e 
                       
                       ⁡ 
                       
                         ( 
                         s 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         θ 
                         step 
                       
                       · 
                       
                         ( 
                         
                           
                             s 
                             2 
                           
                           + 
                           
                             
                               ω 
                               c 
                             
                             · 
                             γ 
                             · 
                             s 
                           
                         
                         ) 
                       
                     
                     
                       
                         s 
                         3 
                       
                       + 
                       
                         
                           ω 
                           C 
                         
                         · 
                         γ 
                         · 
                         
                           s 
                           2 
                         
                       
                       + 
                       
                         
                           ω 
                           C 
                           2 
                         
                         · 
                         γ 
                         · 
                         s 
                       
                       + 
                       
                         ω 
                         C 
                         3 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 9 
                 ) 
               
             
           
         
       
     
   
   The stability of the system is heavily related to the value of γ. In order to have a well-controlled settling behavior, phase margin of 64° and γ of 4.5 are chosen. It ensures that there is no under-damping settling behavior. If γ&gt;3, eq. (9) can be further decomposed into eq. (10) as 
   
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           
                             θ 
                             e_sr 
                           
                           ⁡ 
                           
                             ( 
                             s 
                             ) 
                           
                         
                         = 
                           
                         ⁢ 
                         
                           
                             
                               
                                 θ 
                                 step 
                               
                               · 
                               
                                 
                                   ( 
                                   
                                     1 
                                     - 
                                     γ 
                                   
                                   ) 
                                 
                                 / 
                                 
                                   ( 
                                   
                                     3 
                                     - 
                                     γ 
                                   
                                   ) 
                                 
                               
                             
                             
                               s 
                               + 
                               
                                 α 
                                 1 
                               
                             
                           
                           + 
                           
                             
                               
                                 θ 
                                 step 
                               
                               / 
                               
                                 ( 
                                 
                                   3 
                                   - 
                                   γ 
                                 
                                 ) 
                               
                             
                             
                               s 
                               + 
                               
                                 α 
                                 2 
                               
                             
                           
                           + 
                         
                       
                     
                   
                   
                     
                       
                           
                         ⁢ 
                         
                           
                             
                               θ 
                               step 
                             
                             / 
                             
                               ( 
                               
                                 3 
                                 - 
                                 γ 
                               
                               ) 
                             
                           
                           
                             s 
                             + 
                             
                               α 
                               3 
                             
                           
                         
                       
                     
                   
                 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 where 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 
                   
                     
                       α 
                       1 
                     
                     = 
                     
                       ω 
                       C 
                     
                   
                   , 
                   
                     
                       α 
                       2 
                     
                     = 
                     
                       
                         
                           ( 
                           
                             γ 
                             - 
                             1 
                             - 
                             
                               
                                 
                                   γ 
                                   2 
                                 
                                 - 
                                 
                                   2 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   γ 
                                 
                                 - 
                                 3 
                               
                             
                           
                           ) 
                         
                         2 
                       
                       · 
                       
                         ω 
                         C 
                       
                     
                   
                   , 
                   
                       
                   
                   ⁢ 
                   and 
                 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 
                   
                     α 
                     3 
                   
                   = 
                   
                     
                       
                         ( 
                         
                           γ 
                           - 
                           1 
                           + 
                           
                             
                               
                                 γ 
                                 2 
                               
                               - 
                               
                                 2 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 γ 
                               
                               - 
                               3 
                             
                           
                         
                         ) 
                       
                       2 
                     
                     · 
                     
                       
                         ω 
                         C 
                       
                       . 
                     
                   
                 
               
             
             
               
                 ( 
                 10 
                 ) 
               
             
           
         
       
     
   
   We also know that α 1 , α 2 , and α 3  are positive real numbers for γ&gt;3. Now we can derive the step response of the phase error in the time domain: 
   
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           θ 
                           e_sr 
                         
                         ⁡ 
                         
                           ( 
                           t 
                           ) 
                         
                       
                       = 
                         
                       ⁢ 
                       
                         
                           
                             
                               
                                 θ 
                                 step 
                               
                               · 
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   γ 
                                 
                                 ) 
                               
                             
                             
                               ( 
                               
                                 3 
                                 - 
                                 γ 
                               
                               ) 
                             
                           
                           · 
                           
                             ⅇ 
                             
                               
                                 - 
                                 
                                   α 
                                   1 
                                 
                               
                               · 
                               t 
                             
                           
                         
                         + 
                       
                     
                   
                 
                 
                   
                     
                         
                       ⁢ 
                       
                         
                           
                             
                               θ 
                               step 
                             
                             
                               ( 
                               
                                 3 
                                 - 
                                 γ 
                               
                               ) 
                             
                           
                           · 
                           
                             ⅇ 
                             
                               
                                 - 
                                 
                                   α 
                                   2 
                                 
                               
                               · 
                               t 
                             
                           
                         
                         + 
                         
                           
                             
                               θ 
                               step 
                             
                             
                               ( 
                               
                                 3 
                                 - 
                                 γ 
                               
                               ) 
                             
                           
                           · 
                           
                             ⅇ 
                             
                               
                                 - 
                                 
                                   α 
                                   3 
                                 
                               
                               · 
                               t 
                             
                           
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 11 
                 ) 
               
             
           
         
       
     
   
   Substituting the corresponding values of this synthesizer into eq. (11), the step response of the phase error is shown in  FIG. 12 . Referring to  FIG. 10  and eq. (6), the smallest phase step, θ step     —     min , is 0.015 rad when the system experiences a 2 μA down current change in the CP. Referring to  FIG. 12 , a calibration period larger than 4 μs is good enough for a phase error smaller than θ step     —     min  to ensure the calibration resolution. Taking process and temperature variations into consideration as well, the reference clock is divided by 128 to have a calibration period of 12.8 μs. 
   While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.