Patent Publication Number: US-8531807-B2

Title: ESD clamp adjustment

Description:
REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 12/826,983 filed on Jun. 30, 2010. 
    
    
     BACKGROUND 
     Integrated circuits (ICs) include external pins that allow the ICs to be connected to other external circuit elements. Although these external pins are required as a practical matter so ICs can be included in electronic products, unfortunately these external pins also make semiconductor devices on the ICs susceptible to potentially damaging electrostatic discharge (ESD) pulses. An ESD pulse, which is a sudden and unexpected voltage and/or current discharge, can transfer energy to devices on the IC through the external pins from an outside body (e.g., a human body, which can be approximated in modeling by a human body model (HBM)). ESD pulses can also affect internal nodes of the IC, as well as discrete devices that are not associated with ICs. In any case, an ESD pulse can damage electronic devices, for example by “blowing out” a gate oxide of a transistor in cases of high voltage or by “melting” an active region area of a device in cases of high current, causing junction failure. If devices are damaged by an ESD pulse, the electronic product can be rendered less operable than desired, or can even be rendered inoperable altogether. 
     To protect devices from ESD pulses, engineers have developed ESD protection devices.  FIG. 1  shows an example of an integrated circuit  100  that includes one or more semiconductor devices  102  (e.g., transistors arranged as part of an application specific integrated circuit (ASIC)), which are coupled to an exterior circuit assembly via an external pin  104 . The external pin  104  can be a supply pin that supplies a DC supply voltage (e.g., VDD or VSS) to the devices  102 , or can be an input/output (I/O) pin that transfers input or output signals therefrom, for example. A conventional ESD protection device  106  is coupled between the semiconductor device(s)  102  and the external pin  104  to mitigate damage due to ESD pulses  108 . 
     As shown in  FIG. 2 , if an ESD pulse  108  occurs (e.g., starting at time  110 ), the ESD protection device  106  detects the ESD pulse  108  and shunts the power associated with it away from the semiconductor device(s)  102  (e.g., as shown by arrow P ESD ), thereby preventing damage to the semiconductor device(s)  102 . In addition to this shunting, which occurs during actual ESD events, this functionality can also be falsely triggered, for example, by supply switching noise, fast power up sequences having rise times comparable to ESD events, and other non-ESD events. 
     Although this conventional ESD protection functionality is well understood, the inventors have appreciated a shortcoming in that conventional ESD protection devices, when active, can undesirably reduce the desired voltage level of the signal expected to be delivered from the external pin  104  to the device(s)  102 . For example,  FIG. 2  shows an example where the external pin  104  is a supply pin that is expected to provide a DC voltage supply (VDD) of approximately 3.3 volts to the semiconductor device(s)  102 . However, upon a  100  volt ESD pulse triggering the ESD protection device  106 , the supply voltage that actually reaches the semiconductor device(s)  102  is reduced to about 1.5 V during the ESD pulse. See line  112 . Because 1.5 V is less than the expected VDD and may be less than required to operate the semiconductor device(s)  102  (e.g., transistors in an ASIC), this can cause instability in the integrated circuit  100  and systems associated therewith. Other sample ESD pulses are also illustrated in  FIG. 2 , along with their corresponding effect on VDD delivered to the devices on the IC. 
     The applicants note that  FIG. 2  is a simulation result in which transmission line pulsing (TLP) is used to approximate an ESD event. In FIG.  2 &#39;s simulation, a constant current is delivered to a convention ESD protection device over a 100 ns period. Thus, at the start of the ESD pulse, an artificial voltage overshoot is exhibited, which is due to “slow” transistors. In real ESD events, the current actually delivered often tends to be transient and not as constant as shown by the simulation results of  FIG. 2 . 
     In view of the above, the inventors have devised ESD protection techniques that provide adequate ESD protection while still ensuring that substantially the same voltage as expected to be delivered to device(s) via an external pin (or other circuit node) is, in fact, delivered to the device(s) via the external pin (or other circuit node). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an integrated circuit that makes use of a conventional ESD protection circuit. 
         FIG. 2  shows waveforms associated with FIG.  1 &#39;s conventional ESD protection circuit during an ESD pulse. 
         FIG. 3  shows functional block diagram of an ESD protection circuit in accordance with some embodiments. 
         FIG. 4  shows waveforms associated with one example of FIG.  3 &#39;s ESD protection circuit during an ESD pulse. 
         FIG. 5  shows one manner in which a gate voltage of a shunt transistor can be varied in accordance with some embodiments. 
         FIG. 6  shows a circuit schematic of an ESD protection circuit in accordance with some embodiments. 
         FIG. 7  shows an ESD protection method in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. The drawings are not necessarily drawn to scale. 
     Various embodiments described below relate to improved ESD protection techniques. In some embodiments, an ESD protection device includes a variable resistor (e.g., a transistor) that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device on the IC. When an ESD pulse is not present, the first circuit node supplies a signal within an expected voltage range to the semiconductor device. To help ensure that the first circuit node still delivers the signal within the expected voltage range during an incoming ESD pulse, a regulator within the ESD protection device provides feedback to adjust a control voltage on a control terminal of the variable resistor. In this way, the semiconductor device is protected from the incoming ESD pulse while still being provided with a signal having a voltage level that is equal to (or slightly greater than) its expected voltage range. For example, if the first circuit node is designed to supply a DC supply voltage (VDD) of approximately 3.3 volts to a semiconductor device on the IC, the regulator helps keeps the voltage supplied to the semiconductor device at substantially 3.3 volts (or slightly greater) during an ESD pulse, while at the same time keeping the supplied voltage low enough to prevent damage to the semiconductor device. 
     Referring to  FIG. 3 , one can see an ESD protection device  300  in accordance with some embodiments. Like the previously discussed implementation of  FIG. 1 , the ESD protection device  300  can be included on an integrated circuit  302  on which one or more semiconductor devices  304  are disposed, although it could also be used with discrete devices rather than an IC. To protect the semiconductor devices  304  from an incoming ESD pulse  306 , the protection device  300  includes variable resistor  308  that selectively shunts the power of the ESD pulse  306  from a first circuit node  310  to a second circuit node  312  and away from the semiconductor devices  304 . It will be appreciated that although  FIG. 3  shows the first and second circuit nodes  310 ,  312  as external pins of the IC  302 , in other embodiments the first and second circuit nodes  310 ,  312  can be located on internal nodes within the IC  302 . 
     More particularly, the ESD protection device  300  includes a trigger element  314 , a gate driver element  316 , and a regulator element  318 , which are operably coupled as shown. As will be appreciated in more detail further herein, the trigger element  314  monitors power on the first circuit node  310  and provides a trigger signal, S trigger , indicative of whether the monitored power is representative of an incoming ESD pulse (e.g., ESD pulse  306 ). When asserted, the trigger signal activates both the gate driver  316  and the regulator element  318 . Upon being activated, gate driver  316  provides a first control signal, S control1 , to a control terminal of the variable resistor  308  to adjust its resistance so an appropriate amount of power is shunted there over (e.g., as shown by arrow P ESD ). In this way, the gate driver  316  keeps the voltage and/or current delivered to the device  304  below an upper threshold (see e.g., line  402  in  FIG. 4 ) to prevent damage to the device  304  due to the ESD pulse  306 . 
     In addition, to prevent the variable resistor  308  from shunting too much power from the device(s)  304  (e.g., thereby unduly reducing a voltage supplied to the devices  304  as previously shown in  FIG. 2 ), the regulator element  318  monitors the actual voltage delivered to the device  304  via the first circuit node  310  and provides a feedback signal, S feedback , indicative thereof. If the actual voltage approaches a predetermined voltage threshold (see e.g., line  404  in  FIG. 4 ), the regulator element  318  provides a second control signal, S control2 , in a manner which causes the gate driver  316  to change the first control signal S control1  to limit the amount of current shunted through the variable resistor  308 . 
     As shown in  FIG. 4 , these techniques keep the voltage supplied to the device during an ESD pulse between an upper threshold  402  and a lower threshold  404 . For example,  FIG. 4  shows examples of ESD pulses where the semiconductor device(s)  304  include transistors designed to operate at a DC supply voltage (VDD) of approximately 3.3 volts. Thus, during a 100 V ESD pulse, the actual voltage supplied to the device  304  remains at approximately 4.0V or greater, as shown by line  406 . Thus, ESD protection device  300  helps ensure the first circuit node  310  delivers a supply voltage at substantially 3.3 volts (or greater) to supply the devices  304  with their expected supply voltage. 
     The variable resistor can take different forms depending on the implementation. For example, in some embodiments, variable resistor can be a thyristor. In other embodiments, the variable resistor  308  can be a transistor (e.g., an n-type MOSFET), and the first control signal, S control1 , consists of a gate voltage. Often, the gate voltage will operate this transistor in an analog manner to facilitate more precise shunting than previously achievable.  FIG. 5  shows an example of how such an analog control scheme can be carried out with regards to an n-type MOSFET. 
     As can be seen from FIG.  5 &#39;s chart, when no ESD pulse is present during  502  and the magnitude of the quantity (VDD actual  minus VDD expected ) is below a first threshold voltage (V Threshold1 ), the gate driver supplies a gate voltage, V gate , which is less than the threshold voltage (VT) of the n-type transistor. Consequently, during this state, the n-type transistor is in a sub-threshold state and substantially no current is shunted away from the on chip semiconductor devices (e.g., no current is shunted from  310  to  312  over  308  in  FIG. 3 ). 
     In contrast, when an ESD pulse is present during  506  and the magnitude of the quantity (VDD actual  minus VDD expected ) is greater than a second threshold voltage (V T2 ), the gate driver supplies a gate voltage, V gate , which is substantially equal to the expected supply voltage VDD. Consequently, during this state the n-type transistor is in a saturation mode that shunts the maximum current away from the on chip semiconductor devices (e.g., maximum current is shunted from  310  to  312  over  308  in  FIG. 3 ). 
     When the ESD pulse is present during  504  and the magnitude of (VDD actual  minus VDD expected ) is between the first and second threshold voltages (V Threshold1 , V Threshold2 ), the gate driver supplies a gate voltage, V gate , which is between the threshold voltage VT of the n-type transistor and the actual supply voltage VDD on node  310 . Consequently, during this state  504 , the n-type transistor is in saturation, but the amount of current it shunts away changes according to the precise gate voltage present. In this way, during state  504 , the n-type transistor acts in an analog manner to selectively shunt a suitable amount of current away from the semiconductor devices (e.g.,  304 ) to prevent ESD damage and concurrently help ensure adequate supply voltages/headroom for the semiconductor devices. Thus, unlike conventional ESD protection devices where the ESD protection device is either “fully-on” or “fully-off”, some embodiments disclosed herein provide for an analog mode of operation that facilitates more accurate shunting than previously achievable. 
       FIG. 6  shows another embodiment of an ESD protection device  600  in accordance with some embodiments. As with some previously discussed implementations, the ESD protection device  600  is included on an integrated circuit  602  on which one or more semiconductor devices  604  are disposed. To protect the semiconductor devices  604  from an incoming ESD pulse (not shown), the ESD protection device  600  includes a shunt transistor  606  that selectively shunts the power of the ESD pulse from a first circuit node  608  to a second circuit node  610  and away from the semiconductor devices  604 . It will be appreciated that although  FIG. 6  shows the first and second circuit nodes  608 ,  610  as external pins of the IC  602 , in other embodiments the first and second circuit nodes  608 ,  610  can be internal nodes within the IC  602  or could be nodes between discrete devices not on an IC. 
     Like FIG.  3 &#39;s embodiment, the ESD protection device  600  includes a trigger element  612 , a gate driver element  614 , and a regulator element  616 . In the illustrated embodiment, the trigger element  612  includes a resistor  618  and a capacitor  620  disposed on a current path  622  extending between the first circuit node  608  and second circuit node  610 . An output node  624  between the resistor and capacitor supplies a trigger signal thereat. It will be appreciated that although  FIG. 6  shows an RC trigger element, other trigger elements could also be used, including but not limited to: an output of supply noise detector (e.g., voltage detector), or a control signal provided from a neighboring voltage domain (e.g., neighboring sector on the circuit) in which an ESD event is detected. 
     The gate driver circuit  614  includes a series of driver elements (e.g.,  626 ,  628 ,  630 ) in series with one another. A first driver element  626  has an input coupled to the trigger element&#39;s output node  624 , and a last of these driver elements  630  has an output coupled to the gate of the shunt transistor  606 . The last driver element  630  includes a first p-type transistor  632 , a second p-type transistor  634 , an n-type transistor  636 , and a resistor  638 . The first p-type transistor  632  has a drain coupled to the first circuit node  608 , and the n-type transistor  636  has a source coupled to the second circuit node  610 . The second p-type transistor  634  has a drain coupled to a source of the first p-type transistor  632 . Further, a source of the second p-type transistor  634  and a drain of the n-type transistor  636  are coupled to the control gate of the shunt transistor  606 . Although  FIG. 6  shows three driver elements in series, it will be appreciated that any number of driver elements, including even and odd numbers of such elements, could be included in other embodiments. 
     The regulator element  616  includes a regulator current path  640  extending between the first circuit node  608  and second circuit node  610 . A resistive element  642 , a string of diodes  644 , and regulator switch  646  lie on the current path  640 . A control node arranged between the resistive element and the series of diodes provides a second control signal to the second p-type transistor  634  in the gate driver circuit. 
     During operation, the trigger element  612  provides a trigger signal from its output node to the gate driver circuit  614 , wherein a voltage level of the trigger signal indicates whether an ESD pulse has occurred. For example, an incoming ESD pulse will typically cause the capacitor  620  to discharge, thereby pulling the output node/trigger signal on  624  low for a brief time to indicate the ESD pulse. 
     While the trigger signal is low (e.g., indicating the presence of the incoming ESD pulse), a p-type transistor  648  in the gate driver asserts an enable signal that closes the regulator switch  646 , thereby initiating current flow through the regulator  640 . The trigger signal also propagates through the driver elements in the gate driver, ultimately causing the first p-type transistor  632  to enter saturation and putting the n-type transistor  636  in sub-threshold mode. This establishes a source-drain bias across the second p-type transistor  634 . 
     Because the enable signal causes current to flow through the regulator  616 , a voltage is established on the regulator&#39;s output node so a second control signal is supplied to the second p-type transistor  634 . When the ESD pulse is present, the voltage magnitude of the second control signal is greater than the threshold voltage of the second p-type transistor  634 . The voltage level of the second control signal varies in an analog manner to “tune” the current through the second p-type transistor  634 , thereby correspondingly “tuning” the first control signal or gate voltage supplied to the shunt transistor  606 . In this manner, the second p-type transistor  634  can vary between triode mode and saturation mode to better control of the gate voltage applied to the shunting transistor  606  than previously achievable. 
     Notably, because the regulator element  616  continuously monitors the voltage on the first circuit node  608  throughout the ESD pulse, the second control signal supplied to the gate of the second p-type transistor  634  can selectively adjust the gate voltage supplied to the shunt transistor  606  throughout the duration of the ESD pulse. This is believed to be an improvement over traditional schemes wherein ESD protection circuits typically clamp for a predetermined time after an ESD pulse occurs, rather than performing on-going monitoring throughout the ESD pulse. Consequently, this feature can provide for more precise power shunting than previously achievable. 
       FIG. 7  shows an illustrative ESD protection methodology  700 . While this method is illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the devices and systems illustrated and described herein as well as in association with other structures not illustrated. 
     The method  700  starts at  702  by determining a supply voltage difference, if any, between an actual supply voltage on a first circuit node and an expected supply voltage on the first circuit node. For example, in some embodiments an expected supply voltage can be approximately 3.3 V with an acceptable variance of +/−100 mV. If the actual supply voltage is 15 V, there is a supply voltage difference of 11.7 V, while if the actual supply voltage is 2 V, there is a supply voltage difference of 1.3 V, for example. 
     In  704 , the method determines whether the supply voltage difference is greater than a first voltage threshold VTthreshold 1 . If not (“N” at  704 ), an ESD pulse is not present (or is sufficiently small), so that the method proceeds to block  708  and applies a gate voltage of less than a threshold voltage of a shunt transistor to the shunt transistor (e.g., shunt transistor  606  in  FIG. 6 ). Thus, at this time, limited or no current is shunted over the shunt transistor. Thus, if the expected supply voltage is 3.3V with an acceptable variance of +/−100 mV, the first voltage threshold is 100 mV. Accordingly, so long as the actual supply voltage is 3.3 V+/−100 mV, the method does not activate the shunt transistor. 
     However, if the supply voltage difference is greater than a first voltage threshold (VThreshold 1 ) (“Y” at  704 ), an ESD pulse of sufficient magnitude is likely present as indicated by  710  and the method continues to  712 , where it determines whether the supply voltage difference is greater than a second voltage threshold (VThreshold 2 ). 
     If the supply voltage difference is greater than the second voltage threshold (“Y” at  712 ), a gate voltage approximately equal to the actual supply voltage is applied to the shunt transistor. At this time, a maximum current is shunted over the transistor. Thus, block  714  to correspond to, for example, a condition where the actual supply voltage briefly “spikes” up to 15 V. In this instance, the supply voltage difference of 11.7 V exceeds the second voltage threshold and the actual supply voltage of 15V is applied to the gate of the shunt transistor to prevent damage to the semiconductor device. 
     If the supply voltage difference is not greater than the second voltage threshold VThreshold 2  (“N” at  712 ), a gate voltage having a voltage magnitude between the threshold voltage of the shunt transistor and the actual supply voltage is applied to the shunt transistor. At this time, analog tuning of the gate voltage occurs. Thus, block  718  corresponds to, for example, a condition where the actual supply voltage falls slightly outside of the expected supply voltage range. For example, the actual supply voltage could be approximately 3.0 V (i.e., supply voltage difference is greater than 100 mV but less than Vthreshold 2 ), causing an analog voltage to be applied to the gate of the shunt transistor. 
     While the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.