Patent Publication Number: US-10312813-B2

Title: Multi-phase converter

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of U.S. application Ser. No. 15/675,285, filed Aug. 11, 2017, which is incorporated by reference. 
    
    
     BACKGROUND 
     Multi-phase voltage converters for converting a first DC voltage a second DC voltage are availing for a wide range of applications. Multi-phase buck converters are one example. A multi-phase buck converter outputs a lower voltage than the received input voltage. A conventional buck converter includes a switch and either a capacitor, inductor, or both. In some instances, a large step down voltage ratio makes the buck regulator inefficient. In addition, relatively high input voltages limits the switching frequency of the switches and thus sacrifices the power density as well as dynamic responses. 
     SUMMARY 
     In general, one innovative aspect of the subject matter described in this specification can be embodied in first and second parallel converter branches, each parallel converter branch includes: an input node that receives a direct current (DC) input voltage, N output nodes that each respectively output a DC output voltage, where the DC output voltage is less than the DC input voltage, and where N is two or more; a plurality of switches that each operate at a magnitude limit of substantially the DC input voltage divided by N, where each switch includes a first terminal, a second terminal, and a third terminal, and the third terminal of the first switch receives a control signal that places the first switch in either a closed state in which a conduction path is established between the first and second terminals, or an open state in which the conduction path is eliminated between the first and second terminals; a converter output node that is connected to each of the N output nodes of the first and second parallel converter branches and provides the DC output voltage; and control logic that generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes. 
     Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. By using multiple stacked capacitors in the multi-phase converter, the switching voltages for the MOSFETS (or other transistor types that may be used) in the circuit is reduced to a lower voltage (e.g., &lt;5 V) than would otherwise be required without the stacked capacitors. Lowering the MOSFET switching voltage enables the capacitor stacked multi-phase voltage converter to have a higher density and efficiency relative to a traditional multi-phase buck converter. The capacitor stacked multi-phase voltage converter enables dynamic fast responses and ease of use for point of load applications and allows the use of low voltage MOSFETS for increased switching frequency. 
     The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an example capacitor-stacked multi-phase voltage converter. 
         FIG. 2  is a block diagram of example parallel converter branches with cascade stages and a final stage for each converter branch. 
         FIG. 3  is an example implementation of a three level—six phase capacitively stacked voltage converter. 
         FIG. 4  is an example implementation of a two level—four phase capacitively stacked voltage converter. 
         FIG. 5  is a diagram of pulse width modulated control waveforms of the two level—four phase capacitively stacked voltage converter. 
         FIG. 6  is a diagram of switch node waveforms of the two level—four phase capacitively stacked voltage converter. 
         FIG. 7  is a diagram of an output voltage and stacked capacitor voltages for the circuit of  FIG. 4 . 
     
    
    
     Like reference numbers and designations in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     The subject matter of this written description relates to a capacitor stacked multi-phased voltage converters that utilizes capacitors to stack voltages such that the MOSFETS operate at a smaller switching voltage. The capacitor stacked multi-phase voltage converter incorporates the benefit from both a switched capacitor converter and a buck converter. Because the capacitors reduce the switching voltage of the MOSFETS, the converter has a relatively higher efficiency and density when compared to converters that have a higher switching voltage. 
     These features and additional features are described in more detail below. 
       FIG. 1  is a block diagram of an example capacitor-stacked multi-phase voltage converter (CSMPVC). The voltage CSMPVC includes a control unit  102 , at least two N-level capacitor stacked converter parallel branches  104   a ,  104   b . Each parallel converter branch has an input node that receives a direct current (DC) input voltage and has N output nodes that each respectively output a DC output voltage. In some implementations, the DC output voltage is less than the DC input voltage. Inductors  106   a  and inductors  106   b  may respectively connected to each of the N output nodes. Alternatively, one inductor  106   a  may be connected to each of the output nodes of the branch  104   a , and one inductor  106   b  may be connected to each output node of branch  104   b.    
     As will be discussed in greater detail in connection with  FIGS. 2, 3 and 4 , each converter parallel branch includes N levels or stages. Typically, N is equal to two or more. 
     Each parallel converter branch  106   a , and  106   b  also includes a plurality of switches, such as MOSFETS. Each switch includes a first terminal, a second terminal, and a third terminal, and the third terminal of the first switch receives a control signal that places the first switch in either a closed state in which a conduction path is established between the first and second terminals, or an open state in which the conduction path is eliminated between the first and second terminals. Each switch operates at a magnitude limit for the switching voltage of substantially the DC input voltage divided by N. For example, for a CSMPVC with two parallel converter branches with an input voltage of 12V, each switch operates at a switching voltage magnitude limit of no more than 6V. 
     In some implementations, each converter branch  104  includes N−1 cascade stages and a final stage. The N−1 cascade stages are each at an ordinal position relative to the DC input voltage and begin with a first cascade stage that is connected to the DC input voltage as a respective input voltage. Each subsequent cascade stage is connected to a previous cascade stage to receive a respective input voltage. The final stage is connected to a last cascade stage to receive a respective input voltage. Moreover, each of the N−1 cascade stages includes a stacking capacitor that is charged to approximately (N−Ord)/N of the DC input voltage, wherein the value of Ord is the ordinal position of the cascade stage relative to the DC input voltage. Accordingly, the converter may be referred to as being “capacitor stacked.” The stacked capacitors are described in more detail with reference to  FIGS. 2-4  below. 
     The CSMPVC includes a converter output node  108  that is connected to each of the N output nodes  110   a ,  110   b  of the first and second parallel converter branches and provides the DC output voltage (Vout) to a point of load. 
     In addition, the CSMPVC includes a controller  102  with control logic that generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch. The first set of switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes. The control logic can be implemented by any appropriate control circuitry that provides phased drive signals for switches. 
     The CSMPVC can also include N−1 current balancing branches. As will be described in greater detail in connection with  FIG. 2 , the N−1 current balancing branches can optionally include grounding coupling capacitors to reduce the deleterious effects of small current imbalances that may occur. 
       FIG. 2  is a block diagram of example parallel converter branches  104   a  and  104   b  with cascade stages  202 ,  204 , and a final stage  206  for each converter branch. Each parallel converter branch  104  includes N−1 cascade stages, of which two ( 202  and  204 ) are shown in each branch  104 . Each cascade stage is at an ordinal position relative to the DC input voltage at the input node Vin. The first cascade stage  202 , which is at ordinal position  1 , is connected to the DC input voltage. Each subsequent cascade stage is connected previous cascade stage to receive a respective input voltage. For example, the second cascade stage  204 , which is at ordinal position  2 , is connected to cascade stage  202  by connection  203  to receive a respective input voltage. In addition, each parallel converter branch includes a final stage that is connected to a last cascade stage by a respective connection  205  to receive a respective input voltage. 
     Each of the N−1 cascade stages includes a stacking capacitor C, e.g., C 1   a  for stage  202   a , C 2   a  for stage  204   a , etc., that is charged to approximately (N−Ord)/N of the DC input voltage, i.e.,
 
 Vc _ ord=V in*( N - Ord )/ N   (1)
 
     Where: 
     Vc_ord is the DC voltage across the stacked capacitor in a given cascade stage; 
     Vin is the input voltage; 
     Ord is the ordinal position of the cascade stage relative to Vin; and 
     N is the number of stages in the branch  104 , i.e., the number of cascade stages and the final stage. 
     The actual voltage of the stacking capacitor will vary about the value Vc_ord due to charging and discharging during switching states, but the approximate DC value will be Vc_ord. 
     The utility of the stacking capacitor in each cascade stage is described with reference to  FIG. 3 , which is an example implementation of three level—six phase capicitatively stacked voltage converter  300 . In this example, each converter branch  104  has two cascade stages  202  and  204 , and a final stage  206 , for three phase outputs. Because there are two branches, the circuit  300  is referred to as a three level—six phase capicitatively stacked voltage converter. 
     Each of the N−1 cascade stages has a similar topology. In the example circuit  300 , each cascade stage  202  and  204  includes an input switch (Q 1   a  for  202   a  and Q 4   a  for  202   b ) that has a first terminal connected to the respective input voltage of the cascade stage. Each stage also includes a cascade coupling switch (Q 3   a  for  202   a  and Q 6   a  for  202   b ). In each stage, the first terminal of the coupling switch is connected to a second terminal of the input switch, and the second terminal of the coupling switch connected to a first terminal of an input switch of a subsequent cascade stage or the final stage. For example, as shown in  FIG. 3 , in cascade stage  202   a , the cascade coupling switch Q 3   a  connects the second terminal of the input switch Q 1   a  of the cascade stage  201   a  to the first terminal of the input switch Q 4   a  of the cascade stage  204   a . Accordingly, the second terminal of the cascade coupling switch Q 3   a  of the cascade stage  202   a  provides the respective input voltage for the cascade stage  204   a . A similar arrangement is implemented in the cascade stages  202   b  and  204   b . Were there addition cascade stages, they would also be connected in a similar manner. 
     Each cascade stage also has a stacking capacitor that has a first terminal connected to the second terminal of the input switch and a second terminal connected to a node that includes a first terminal of a ground switch and a first terminal of an output inductor. For example, cascade stage  202   a  includes the stacking capacitor C 1   a  that is connected to the second terminal of the input switch Q 1   a  and to a node that connects to a first terminal of a ground switch Q 2   a  and a first terminal of an output inductor L 1   a . Cascade stages  204   a ,  202   b  and  206   b  are constructed in a like manner. 
     Finally, each branch  104  has a final stage  206 . The final stage includes an input switch with a first terminal connected to a second terminal of a cascade coupling switch, and an output inductor with a first terminal connected to a second terminal of the input switch, and a second terminal coupled to an output node. Additionally, a ground switch has a first terminal connected to the second terminal of the input switch, and a second terminal connected to the ground. For example, as shown in  FIG. 3 , the input switch is Q 7   a , the ground switch is Q 8   a , and the output inductor is L 3   a . The second terminal of each inductor L is connected to a common node to provide an output voltage Vout. 
     In some implementations, for a first converter branch, each first terminal of the input switch of each subsequent cascade stage and final stage is respectively connected to each first terminal of each input switch of each subsequent cascade stage and final stage of the second converter branch. This is to facilitate current balancing during switching. For example, the first terminal of Q 4   a  is connected to the first terminal of Q 4   b , and the first terminal of Q 7   a  is connected to the first terminal of Q 7   b . Coupling capacitors C 3  and C 4 , which are shown in phantom, are optional and may be used if the phase shift between voltages in the branches is such that the currents do not balance. 
     The stacking capacitors C 1   a  and C 2   a  allow a switching voltage for each input switch Q 1   a  and Q 4   a  of each stage to be reduced to a level of 1/N of the DC input voltage. Likewise, the stacking capacitors C 1 B and C 2   b  allow the switching voltage for each input switch Q 1   b  and Q 6   b  to be reduced to the level of 1/N of the DC input voltage. Moreover, because the input switches only switch up to 1/N of the input voltage Vin, each stacking capacitor in a subsequent stage has its respective input voltage load reduced by 1/N. This monotonically decreasing load on the capacitors thus results in the final stage only needing to switch 1/N of the input voltage Vin, and thus the final stage does not require a stacking capacitor. Such reduction of the switch voltage for the switches in each stage enables the switches to be implemented with higher switching frequencies and at higher a density than if the switches had to switch a larger portion of the input voltage. 
     The final stage  206  of each of the converter parallel branch  104  includes an input switch having a first terminal connected to a second terminal of a cascade coupling switch. The final stage also includes output inductor and a ground switch. The output inductor has a first terminal connected to a second terminal of the input switch and a second terminal coupled to the output node. The ground switch has a first terminal connected to the second terminal of the input switch and a second terminal connected to the ground. However, because the final stage does not couple to another subsequent stage, and does not need a stacking capacitor, the final stage  206  does not have a stacking capacitor nor a cascade coupling switch. 
     For example, as shown in  FIG. 3 , the final stage  206   a  has the input switch Q 7   a , the inductor L 3   a , and the ground switch Q 8   a . Likewise, the final stage  206   b  has the input switch Q 7   b , the inductor L 3   b , and the ground switch Q 8   b.    
     Operation of an example multi-phase converter is described with reference to  FIGS. 4, 5 and 6 . The operation and function of the elements components of  FIG. 4  are similar to the operation and function of the elements components as described with reference to  FIG. 3  above, except that  FIG. 4  is a two level-four phase capacitively stacked voltage converter  400  (i.e., N=2). Here there is only a single cascade stage  402  and a final stage  404  in each branch  404 . For each cascade branch  104 , the input switch is Q 1 , the ground switch is Q 2 , cascade coupling switch is Q 3 , the output inductor is L 1 , and the stacking capacitor is C 1 . For each final stage  404 , the input switch is Q 4 , the grounding switch is Q 5 , and the output inductor is L 2 . According to equation (1) above, each stacked capacitor C 1  will charge to a voltage of approximately Vin*(2−1)/2, or Vin/2. Accordingly, each transistor Q will switch at no more than Vin/2. 
       FIG. 5  is a diagram  500  of pulse width modulated control waveforms of the two level—four phase capacitively stacked voltage converter. In this example, Vin=8V, Vout=1V, the switching frequency is 1 MHz, I out=100 A, and the duty cycle is 0.25. In this implementation, the CSMPVC does not utilize any coupling capacitors. In addition, the control signals S 1 P and S 2 P are 180 degrees phase shifted, and the control signals  1 N and S 2 N are 180 degrees phase shifted. 
       FIG. 6  is a diagram  600  of switch node waveforms of the two level—four phase capacitively stacked voltage converter. Only the switched voltages for Q 1   a -Q 5   a  are illustrated. Because Vin=8V, all switches are switching at approximately no more than 4V. This enables the CSMPVC to leverage the use of MOSFET technology enabling high density and high efficiency. 
       FIG. 7  is a diagram  700  of an output voltage and stacked capacitor voltages for the circuit of  FIG. 4 . As described above, the actual voltage of the stacking capacitor will vary about the value Vc_ord (here, 4V) due to charging and discharging during switching states, but the approximate DC value will be approximately 4V. 
     Embodiments of the subject matter and the operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on computer storage medium for execution by, or to control the operation of, data processing apparatus. 
     While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any features or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. 
     Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.