Patent Publication Number: US-2023136827-A1

Title: Laterally difused metal-oxide semiconductor (ldmos) transistor with integrated back-gate

Description:
TECHNICAL FIELD 
     This relates generally to semiconductor transistors, and more particularly, but not exclusively, to laterally diffused metal-oxide semiconductor (LDMOS) transistors. 
     BACKGROUND 
     LDMOS transistors are designed for higher power applications as compared to other metal-oxide semiconductor (MOS) transistors. In LDMOS transistors, the drain and source have a large spacing between them and the transistor has lateral diffusions that are used to produce a well-controlled channel region under the gate. However, to provide the necessary power handling capability, LDMOS transistors must be much larger than MOS transistors. Some examples of LDMOS transistors are configured in large ovals or, as further explained hereinbelow, in long back-to-back strips. In some applications, LDMOS transistors consume the majority of the surface area of an integrated circuit. Therefore, any savings in the size of LDMOS transistors can result in a large savings of valuable integrated circuit area. 
     SUMMARY 
     In accordance with an example, an integrated circuit includes a semiconductor substrate having a first conductivity and a drain region having a second conductivity in the semiconductor substrate, the drain region extending in a first direction. The integrated circuit also includes a first gate insulating layer on the drain region extending in the first direction and a first gate on the first gate insulating layer, the first gate extending in the first direction. The integrated circuit also includes a second gate insulating layer extending in the first direction on the drain region, the second gate insulating layer separated from the first gate insulating layer by a gate gap and a second gate on the second gate insulating layer, the second gate extending in the first direction and separated from the first gate by the gate gap. The integrated circuit also includes a first drain having the second conductivity in the drain region extending in the first direction and on an opposite side of the first gate from the gate gap and a second drain having the second conductivity in the drain region extending in the first direction and on an opposite side of the second gate from the gate gap. The integrated circuit also includes a channel well having the first conductivity in the drain region at the gate gap, the channel well extending in the first direction and extending in a second direction perpendicular to the first direction under the first gate and the second gate and a first source having the first conductivity formed in the channel adjacent to an edge of the first gate, the first source extending in the first direction. The integrated circuit also includes a second source having the first conductivity formed in the channel adjacent to an edge of the second gate, the second source extending in the first direction and separated from the first source by a channel gap and at least one back-gate contact formed in the channel well between the first gate and the second gate, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap. The integrated circuit also includes a source contact formed in the channel well in the gate gap except at the at least one back-gate contact and a conductive layer formed in contact with the at least one back-gate contact and the source contact. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a plan view of an example baseline LDMOS configuration. 
         FIG.  2    is a cross sectional view of the LDMOS transistor of  FIG.  1    from the cut line indicated in  FIG.  1   . 
         FIG.  3    is a plan view of an example baseline LDMOS transistor. 
         FIG.  4    is a cross section of the example LDMOS transistor of  FIG.  4    through the cut line indicated in  FIG.  4   . 
         FIG.  5    is a cross section of the example LDMOS transistor of  FIG.  4    through the cut line indicated in  FIG.  4   . 
         FIG.  6    is a plan view of an example LDMOS transistor. 
         FIG.  7    is a cross section of an example LDMOS transistor through the cut line indicated in  FIG.  7   . 
         FIG.  8    is a cross section of an example LDMOS transistor through the cut line indicated in  FIG.  7   . 
         FIGS.  9 A-J  (collectively “ FIG.  9   ”) are cross sectional views illustrating an example process for fabricating the example of  FIGS.  6 - 8   .  FIGS.  10 A- 10 C  (collectively “ FIG.  10   ”) are computer simulations of cross sections showing the arsenic doping levels in example LDMOS transistors. 
     
    
    
     DETAILED DESCRIPTION 
     In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily drawn to scale. 
     In this description, the term “coupled” may include connections made with intervening elements, and additional elements and various connections may exist between any elements that are “coupled.” Also, as used herein, the terms “on” and “over” may include layers or other elements where intervening or additional elements are between an element and the element that it is “on” or “over.” 
     In example arrangements, the problem of providing a more compact LDMOS structure with high performance is solved by back-gate contact diffusions that extend across the gap between gates in a back-to-back LDMOS configuration where there is a defined space between the gates and back-gate diffusions. In an example, an integrated circuit includes a semiconductor substrate having a first conductivity and a drain region having a second conductivity in the semiconductor substrate, the drain region extending in a first direction. The integrated circuit also includes a first gate insulating layer on the drain region extending in the first direction and a first gate on the first gate insulating layer, the first gate extending in the first direction. The integrated circuit also includes a second gate insulating layer extending in the first direction on the drain region, the second gate insulating layer separated from the first gate insulating layer by a gate gap and a second gate on the second gate insulating layer, the second gate extending in the first direction and separated from the first gate by the gate gap. The integrated circuit also includes a first drain having the second conductivity in the drain region extending in the first direction and on an opposite side of the first gate from the gate gap and a second drain having the second conductivity in the drain region extending in the first direction and on an opposite side of the second gate from the gate gap. The integrated circuit also includes a channel well having the first conductivity in the drain region at the gate gap, the channel well extending in the first direction and extending in a second direction perpendicular to the first direction under the first gate and the second gate and a first source having the first conductivity formed in the channel adjacent to an edge of the first gate, the first source extending in the first direction. The integrated circuit also includes a second source having the first conductivity formed in the channel adjacent to an edge of the second gate, the second source extending in the first direction and separated from the first source by a channel gap and at least one back-gate contact formed in the channel well between the first gate and the second gate, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap. The integrated circuit also includes a source contact formed in the channel well in the gate gap except at the at least one back-gate contact and a conductive layer formed in contact with the at least one back-gate contact and the source contact. 
       FIG.  1    is a plan view of an example integrated circuit (IC)  100  including an LDMOS configuration that is representative of some baseline configurations. The IC includes two LDMOS transistors that are configured to operate together to provide a transistor function. As explained further hereinbelow with regard to  FIG.  2   , each LDMOS transistor includes corresponding gates  124  that are separated by a gate gap  123  that includes a back-gate contact between two source contacts  132 . One gate  124  is between one drain contact  130  and one source contact  132 , and another gate  124  is between a second drain contact  130  and a second source contact  132 . Each of these components extends laterally in a length direction over a substrate  102  ( FIG.  2   ), e.g. in the vertical direction relative to the page in  FIG.  1   . The transistors may be regarded as back-to-back LDMOS sections. In many configurations, the transistors extend much farther than shown in  FIG.  1    and include multiple back-to-back LDMOS sections. There may be dozens of sections to provide the necessary power handling capability for the intended application of the IC  100 . Example applications include RF transmitters and automotive controls. For example, an LDMOS transistor may control power applied to headlights in an automobile. The specific examples described herein do not limit the application of LDMOS transistors. LDMOS transistors may be useful in many applications. 
       FIG.  2    is a cross sectional view of the IC  100  from the cut line indicated in  FIG.  1   . As explained further hereinbelow with regard to  FIG.  3   , n-well  106  is formed in or over a semiconductor substrate including a lightly doped p-type epitaxial (“epi”) layer  104  over p-type substrate  102 . N-type drain regions  112  are formed in n-well  106  and each of two n-type drain contacts  130  is respectively formed in each of two drain regions  112 . Channel well  118  is a p-type region formed in n-well  106 . N-type source regions  120  are formed in channel well  118  and are spaced apart by the back-gate contact  136 . Source contacts  132  are n+ regions formed in source regions  120 . Gates  124  include patterned polysilicon layers (gate layers) formed into polysilicon gate electrodes over gate insulating layers such as gate oxide layers  125  and field oxide layers  122 . Silicide layers  138  are conductive layers that are formed in contact with the gates  124 , drain contacts  130 , source contacts  132  and back-gate contact  136 . Back-gate contact  136  is formed so as to be in contact with the channel well  118 . Silicide layers  138  provide ohmic contacts and high conductivity. Of note, the silicide layer  138  on source contacts  132  and back-gate contact  136  shorts these components together in this example. Thus, the sources and back-gate are conductively connected in this configuration. This is known as an integrated back-gate (IBG) configuration. Coupling the back-gate to the source is often used in circuits using LDMOS transistors. The conductivity of the LDMOS transistors between their respective sources and drains is controlled by gates  124 , which cause channels to form under the gates in channel wells  118  under the gate oxide layers  125 . Field oxide layers  122 , the extension of drain regions  112  under field oxide layers  122  and the gradation of doping from drain contacts  130  to drain regions  112  and n-well  106  distribute the electric fields applied to the LDMOS transistors to provide a high voltage handling capability. Higher voltage capability can be increased by increasing the width of field oxide layers  122  under gates  124  and beyond. 
     A key figure of merit for LDMOS transistors is the specific on resistance (Rsp). Rsp is defined as the source/drain resistance (RSD) times the width of the device (W) times the half pitch (HP), which is the distance from the center of the source contact to the center of the drain contact. In the example of  FIGS.  1 - 3   , the source and back-gate are coupled together, so the center of the “source contact” is at a distance halfway between the gates. The lower the Rsp, the lower the on resistance of the resistor, and thus the less power is consumed to drive the transistor and the greater the driving capability of the LDMOS for a given size of the LDMOS. Thus, for the same driving capability, an LDMOS transistor with a low Rsp can be smaller than an LDMOS transistor with a higher Rsp. To reduce Rsp, it is desirable to minimize the HP. However, the width of source contacts  132  ( FIG.  1   ) and back-gate contact  136  ( FIG.  1   ) are generally at or near the minimum line width for the manufacturing process or cannot be reduced because of other factors such as current handling requirements or spreading of the dopant. 
       FIG.  3    is a plan view of an LDMOS transistor  300  implemented in some baseline configurations with a source contact and back-gate contact configuration that helps to reduce the HP. Rather than a single back-gate contact that runs parallel to the transistor gates, e.g. back-gate contact  136 ,  FIG.  1   ), one or more back-gate contacts are provided by back-gate contacts  336  that extend across gate gap  323  between and sometimes partially under gates  324 . Rather than the single source contact  132  of  FIG.  1   , the transistor  300  has a plurality of segmented source contacts  332  each between an adjacent pair of back-gate contacts  336 . Gates  324  are analogous to the gates  124  ( FIG.  1   ). Drain contacts  330  are analogous to the drain contacts  130  ( FIG.  1   ). Otherwise, features referenced by  3 XX generally correspond to or analogous to similar features of  FIG.  1    referenced by  1 XX. 
       FIG.  4    is a cross section of the LDMOS transistor  300  through the cut line indicated in  FIG.  3   . Features referenced by  3 XX generally correspond to or analogous to similar features of  FIG.  1    referenced by  1 XX. Shown are substrate  302 , epi layer  304 , and N-well  306 ; N-type drain regions  312  and channel well  318  in the N-well  306 ; sources  320  in the channel well  318 ; the drain contacts  330  in the drain regions  312 ; field oxide layers  322  and gate oxide layers  325 ; gates  324  and silicide layers  338 . At the cut line of  FIG.  4   , source contact  332  extends across the gate gap  323 . As shown in  FIG.  4   , source contact  332  extends partially under gates  324 . Gates  324  may be used to block implantation of source contact dopants such that the source contacts  332  are self-aligned to the gates  324 . After drive-in, part of the dopant will be diffused under gates  324 . 
       FIG.  5    is a cross section of the LDMOS transistor  300  through the cut line indicated in  FIG.  4   . As for  FIG.  4   , features in  FIG.  5    referenced by  3 XX generally correspond to or are analogous to similar features of  FIG.  1    referenced by  1 XX. At the cut line of  FIG.  5   , back-gate contact  336  extends across the gate gap  323  between gates  324 . As shown in  FIG.  5   , back-gate contact  336  extends partially under gates  324 . Similar to the source contacts  332 , the back-gate contacts  336  are self-aligned to the gates  324 , and after drive-in, part of the dopant will be diffused under gates  324 . 
     Referring to  FIG.  4   , by reconfiguring the back-gate contacts  336  and the source contacts  332  relative to the implementation of  FIG.  1   , the gap between gates  324  may be shrunk to nearly the minimum dimension of the lithography used to fabricate LDMOS transistor  300 . In addition, the number of back-gate contacts  336  can be adjusted to allow for a larger proportion of the area between gates  324  being devoted to source contacts  332 , thus lowering the overall source resistance and improving the driving power of LDMOS transistor  300 . 
     However, as can be seen in  FIG.  5   , the ends of back-gate contact  336  are very close to the interface between sources  320  and channel well  318  under gates  324 . This can raise the resistance of sources  320  near channel well  318 , e.g. due to reduced source dopant concentration near the interface, thus increasing the overall source to drain resistance (RSD) and thus undesirably raising Rsp. 
       FIG.  6    is a plan view of an example LDMOS transistor  600  that may advantageously address the problem of excess Rsp of the transistor  300 . Like references in  FIG.  6    indicate like features in  FIGS.  7  and  8   . The transistor  600  includes a source contact and back-gate contact configuration that helps to reduce the transistor HP while also reducing the increased resistance that may result from the proximity of the source contacts to the channel region in the transistor  300 . Similar to in  FIG.  4   , the space between gates  624  includes multiple, noncontiguous back-gate contacts  636  (also called herein “back-gate contact region(s)”). Unlike the transistor  400 , however, the source contact  632  (also called herein “source contact region”) remains contiguous and includes portions located between respective ones of the back-gate contacts  636  and the gates  624 . Therefore, in examples of the disclosure back-gate contacts  636  do not extend all the way across gate gap  623  between gates  624 . In examples, first back-gate contact gap  637  and second back-gate contact gap  639  are in the rage of 0.05 μm to 0.5 μm. Without implied limitation, first back-gate contact gap  637  and second back-gate contact gap  639  are the same size, but this is not a requirement. Drain contacts  630  provide a similar function to drain contacts  330  ( FIG.  3   ). Features referenced by  6 XX generally correspond to or are analogous to similar features of  FIG.  1    referenced by  3 XX. 
       FIG.  7    is a cross section of the example LDMOS transistor  700  through the cut line indicated in  FIG.  6   , in which in which like references indicate like features in  FIGS.  6  and  8   . Shown are substrate  602 , epi layer  604 , and N-well  606 ; N-type drain regions  612  and channel well  618  in the N-well  606 ; sources  620  in the channel well  618 ; the drain contacts  630  in the drain regions  612 ; field oxide layers  622  and gate oxide layers  625 ; gates  624  and silicide layers  638 . In the section view of  FIG.  7   , source contact  632  extends completely across the gap between gates  624 . The source contact  632  may be self-aligned to the gate  624  (e.g., the gates  624  may block the source contact  632  implant). While not explicitly shown, after thermal drive-in, the source contact  632  will typically extend partially under the gates  624 . 
       FIG.  8    is a cross section of the example LDMOS transistor  600  through the cut line indicated in  FIG.  6   , in which in which like references indicate like features in  FIGS.  6  and  7   . In the view of  FIG.  8   , back-gate contact  636  extends across the gate gap  623 . As shown in  FIG.  8   , back-gate contact  636  is separated from gates  624  by first back-gate contact gap  637 , and second back-gate contact gap  639 . Unlike LDMOS transistor  300  ( FIG.  3   ), back-gate contact  636  is not self-aligned to the gates  624  and is spaced apart from the gates  624 . Therefore, little if any of the dopant from back-gate contact  636  will diffuse under gates  624 . As shown in  FIG.  8   , portions of the source contact  632  are located between the back-gate contact  636  and the gates  624 . 
     Referring to  FIG.  6   , LDMOS transistor  600  allows for the gate gap  623  to be shrunk to nearly the minimum dimension of the lithography used to fabricate LDMOS transistor  600  plus first back-gate contact gap  637  and second back-gate contact gap  639 . In addition, the number of back-gate contacts  636  can be adjusted to allow for a larger proportion of the area between gates  624  being devoted to source contacts  632 , thus lowering the overall source resistance and improving the driving power of LDMOS transistor  600 . However, as can be seen in  FIG.  8   , unlike LDMOS transistor  300  ( FIG.  4   ), the ends of back-gate contact  636  are spaced apart from the interface between sources  620  and channel well  618  under gates  624 . This mitigates the effect of back-gate contact  636  on sources  620  and channel well  618 . 
       FIGS.  9 A-J  (collectively “ FIG.  9   ”) are cross sectional views illustrating an example process for fabricating the LDMOS transistor  600 . Features referenced by  9 XX in  FIG.  9    generally correspond to or are analogous to similar features of  FIGS.  6 - 8    referenced by  6 XX. The cross sections of  FIG.  9    are along the  FIG.  8    cut line of  FIG.  6   . Referring to  FIG.  9 A , an epitaxial layer  904  is formed on a substrate  902  using epitaxial deposition. The epitaxial layer  904  has a top surface opposite to the substrate  902 . In this example, epitaxial layer  904  is p- and substrate  902  is a p+ substrate, which has a resistivity of about 0.015 Ω-cm. The example of  FIG.  9    is an n-channel LDMOS enhancement-type transistor  900 . In this example, a first conductivity type is p and a second conductivity type is n. In other examples, the first conductivity type is n and the second conductivity type is p. Therefore, these other examples would be p-channel transistors. In other examples, changes in the doping profile of the channel (forming the channel well is further described hereinbelow) can provide a depletion-type transistor. However, depletion-type LDMOS transistors are not commonly used in high-voltage switching applications. 
     A masked implantation of n-type dopant into epitaxial layer  904 , followed by a drive-in step, forms n-well  906  (also called herein “drain well”). An example implantation is n-type dopant, such as phosphorous with a dose of about 4.0×10 12  atoms/cm 2  at an energy of about 80 keV. N-well  906  is a low concentration (n−), deep diffusion well. 
     A first oxide layer  908  is then deposited or grown over the surface of epitaxial layer  904  as shown in  FIG.  9 B . A layer of first photoresist layer  910  is deposited over oxide layer  908  and patterned and etched. An implantation of n-type dopant, such as phosphorous with a dose of about 8.0×10 12  atoms/cm 2  at an energy of about 80 keV, is then implanted using first photoresist layer  910  to form drain regions  912  after drive-in of the implantation. 
     Referring to  FIG.  9 C , first photoresist layer  910  is removed using a wet cleaning or ashing, for example, and a second photoresist layer  914  is deposited and patterned over first oxide layer  908 . Implants of p-type and n-type dopants, with the n-type dopant having substantially less diffusivity than the p-type dopant, are performed resulting in implants  915  as shown in  FIG.  9 C . A suitable p-type dopant is boron with a dose of about 1.0×10 14  atoms/cm 2  at an energy of about 35 keV. A suitable n-type dopant is arsenic with a dose of about 1.0×10 15  atoms/cm 2  at an energy of about 35 keV. 
     Referring to  FIG.  9 D , second photoresist layer  914  is then removed using a wet cleaning or ashing, for example. Prior to further processing, a drive-in step, for example 80 minutes at 1100° C., is performed to diffuse the n-type and p-type implants in n-well  906  with the result that the deeper p-type implant forms the channel well  918 , while the shallower n-type implants form n-type sources  920 . Thus, channel well  918 , and sources  920  are formed using the same mask (second photoresist layer  914 ). First oxide layer  908  is then removed. A second oxide layer  909  having a thickness of about 400 Å is formed on epitaxial layer  904 . A silicon nitride layer  911  is formed on second oxide layer  909  using low pressure chemical vapor deposition (LPCVD) and having a thickness of about 1400 Å. A third photoresist layer  916  is deposited and patterned over silicon nitride layer  911 . Silicon nitride layer  911  is then removed where exposed by third photoresist layer  916 . Third photoresist layer  916  is then removed. The resulting structure is then subjected to an oxidation step to form field oxide regions  922 , as shown in  FIG.  9 E . In this example, field oxide layers  922  are thermally grown to a thickness of approximately 1000 Å. 
     Second oxide layer  909  and the remaining portions of silicon nitride layer  911  are then removed, for example by plasma etching. A gate oxide layer  925  is then thermally grown on exposed portions of epitaxial layer  904  to a thickness of about 150 Å, resulting in the oxide layers  922 ,  925  shown in  FIG.  9 E . An optional low voltage threshold adjust Vt implant may then be performed through gate oxide layers  925 , which will include the portion of channel well  918  near the surface of epitaxial layer  904 . 
     In an example, a gate layer, consisting of a polysilicon layer, for example, with a thickness of about 1500 Å is then deposited over gate oxide layers  925  and field oxide layers  922  and doped with an impurity, such as phosphorus, to render it conductive. Fourth photoresist layer  926  is deposited and patterned over the polysilicon layer. The gate layer is then etched using fourth photoresist layer  926  as a mask to form gates  924  as shown in  FIG.  9 F . Fourth photoresist layer  926  is then removed. 
     An implant of an n-type impurity, such as phosphorus with a dose of about 4.0×10 14  atoms/cm 2  at an energy of about 80 keV followed by arsenic with a dose of about 5.0×10 15  atoms/cm 2  at an energy of about 120 keV is then performed to form n+ source contacts  932  and n+ drain contacts  930 . In some examples a fifth photoresist layer (not shown) is used as a mask, while in others the implant is self-aligned to the gates  924  and the gate oxide layer  925 . Even when a mask is used, the implant may be self-aligned to the gates  924 . This implantation is sometimes called the n-type source/drain (NSD) implantation, and results in the structure shown in  FIG.  9 G . N+ source contacts  932  are formed in sources  920  and N+ drain contacts  930  are formed in drain regions  912  using one implantation. If used, the fifth photoresist layer (not shown) is then removed. N+ source contacts  932  and n+ drain contacts  930  are then annealed. 
     Sixth photoresist layer  934  is then formed and patterned as shown in  FIG.  9 H  to create openings over the areas corresponding to the  FIG.  8    cut line shown in  FIG.  6   . The photoresist is left unexposed in areas corresponding to the  FIG.  8    cut line in  FIG.  6   . A p-type dopant, for example boron with a dose of about 2.0×10 15  atoms cm 2  at an energy of about 25 keV, is then implanted to form p+ back-gate contact  936  to provide conductive contact to channel well  918 . Because this implant is also used to form p-type source and drain contacts in other parts of the integrated circuit, this implant is sometimes called the p-type source/drain implant (PSD). No implant occurs in portions of the source contact  932  between adjacent back-gate contacts  936 . The portions of the source contact  932  on either side of the back-gate contact  936  correspond to the channel gaps  937  and  939  (corresponding to channel gaps  637  and  639  in  FIG.  6   , respectively). Sixth photoresist layer  934  is then removed and back-gate contact  936  is annealed. 
     Optionally, a layer of silicon dioxide, silicon nitride or a combination of the two may (not shown) be deposited overall and then removed using anisotropic plasma etching to form sidewalls (not shown) on gates  924 . The portions of gate oxide layer  925  not covered by gates  924  (and the optional sidewalls) are then removed using plasma etching, for example. A layer of siliciding metal (not shown) is then deposited overall. Examples of a suitable siliciding metal are molybdenum and titanium. An annealing step then causes a portion of gates  924 , drain contacts  930 , source contacts  932  and back-gate contact  936  to react with the siliciding metal to form silicide layers  938 . The remaining portion of the siliciding metal layer is then removed. In this example, the silicide layers  938  on source contacts  932  and back-gate contact  936  are conductively coupled to source contacts  932  and back-gate contact  936 , thus providing an integrated back-gate (IBG) structure. The resulting structure is shown in  FIG.  9 I . 
     An interlevel oxide layer  940  is then deposited as shown in  FIG.  9 J . A seventh photoresist layer (not shown) is deposited and patterned on interlevel oxide layer  940 . The seventh photoresist layer is used to form openings in interlevel oxide layer  940  to expose silicide layers  938 . The openings are filled with via  942 , via  944 , via  946 , via  948  and via  950 , which include conductive materials, as titanium, tungsten, a combination of the two, or other conductive materials. Via  942 , via  944 , via  946 , via  948  and via  950  provide conductive connections to drain regions  912 , sources  920  and channel well  918 , respectively, to an interconnection metal layer (not shown) on interlevel oxide layer  940 . 
       FIGS.  10 A- 10 C  (collectively “ FIG.  10   ”) are computer simulations of cross sections of example LDMOS transistors showing the arsenic doping levels at the edge of gate  1024 , which is analogous to the gates  724  of the example LDMOS transistor  600  ( FIGS.  6 - 8   ). These simulations only show the effective arsenic doping after NSD implant and do not show other dopants in the devices. The cross sections of  FIG.  10    represent the section of  FIG.  6    taken through the back-gate contact  636 , shown in section view in  FIG.  8   .  FIG.  10 A  corresponds a first case in which the first and second channel gaps  637 ,  639  are 0 μm;  FIG.  10 B  corresponds a second case in which the first and second channel gaps  637 ,  639  are 0.10 μm; and  FIG.  10 C  corresponds a third case in which the first and second channel gaps  637 ,  639  are 0.15 μm. In the described examples, the NSD implant includes arsenic to form sources  920  ( FIG.  9   ) along with boron to form channel well  918  ( FIG.  9   ).  FIG.  10 A  shows that, for the example of first and second back-gate contact gaps  637 ,  639  of 0 μm, the arsenic doping of the source  620  ( FIG.  8   ) is heavily counter-doped.  FIG.  10 B  shows that for the example of first and second back-gate contact gaps  637 ,  639  of 0.10 μm, the arsenic doping of source  620  ( FIG.  8   ) is significantly less counter-doped.  FIG.  10 C  shows that for the example of first and second back-gate contact gaps  637 ,  639  of 0.15 μm, the arsenic doping of source  620  ( FIG.  8   ) has very little counter-doping. With the example of  FIG.  10 C , and to a lesser extent  FIG.  10 B , it can be expected that the portion of source  620  ( FIG.  6   ) will provide significant conductivity when LDMOS transistor  600  ( FIG.  6   ) is on, thus lowering RSD and thus Rsp. 
     Data were obtained on multiple devices on multiple substrates for baseline LDMOS transistors consistent with those in example integrated circuit  100 , and for example transistors consistent with the LDMOS transistor  600 . LDMOS transistors in the former set are sometimes referred to as “low DWELL arsenic” transistors due to the minimal concentration of arsenic in the DWELL between the back-gate contact  636  and the channel and counter-doping of a portion of source  620  by back-gate contact  636 . LDMOS transistors in the latter set are sometimes referred to as “high DWELL arsenic” transistors due to the elevated concentration of arsenic in the DWELL between the back-gate contact  636  and the channel resulting from the back-gate contact gaps  637 ,  639 . The high DWELL arsenic transistors were found to have a significantly lower Rsp than the low DWELL arsenic transistors, as summarized in Table 1. The reduction of Rsp was found to be the greater for those transistors configured to operate at a lower drain voltage. This is interpreted as being due to the extension of the drain in the higher voltage transistors. Thus, the source/channel well resistance is a smaller portion of the overall RSD. The reduction of Rsp represents a significant design advantage, e.g. for area reduction of such transistors, and is especially so for the 5 V transistor example. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Nominal Drain Voltage (V) 
                 Rsp Reduction 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                   
                 5 
                 7.0% 
               
               
                   
                 7 
                 5.2% 
               
               
                   
                 13 
                 4.3% 
               
               
                   
                 20 
                 3.8% 
               
               
                   
                   
               
            
           
         
       
     
     Table 2 presents results from characterizing the “snap back current” of variants of an LDMOS transistor consistent with the transistor  600 . The snap back current is the unit current through the transistor at which the voltage between the drain and the source reaches a maximum before the transistor breaks down and the voltage rapidly drops as the current increases. The snap back current I ds  (or voltage V ds ) is typically characterized at each of several values of the gate-to-source voltage V gs . The V ds  and I ds  at which breakdown occurs for a particular V gs  defines one point of a locus of points that define the extent of an envelope of V-I values in which the transistor may be safely operated. The V-I values within this envelope are sometimes referred to as the safe operating area, or SOA. 
     In Table 2, normalized values of the current at which breakdown occurs are shown for the case that V gs =1 V. An “N/P ratio” represents the ratio of total area occupied by the source contacts  632  in the gate gap  623  to the total areas occupied by the back-gate contact  636 . The “PSD pullback” represents the width of the back-gate contact gaps  637 ,  639 , shown for the example of zero (no pullback, or the back-gate contact gaps  637 ,  639  having nil width) and the example of 0.1 μm. 
     The values in Table 2 indicate that the snap back current generally increases with decreasing N:P ratio, and is greater for the 0.1 μm pullback than for no pullback for all N:P values. In the case of N:P=1:2 the snap back current is about twice the value for 0.1 μm pullback as compared to no pullback. This example is illustrative of the benefit that results from the non-zero PSD pullback, as the snap back V-I points taken at various values of V gs  will define a larger SOA. 
     
       
         
           
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                   
                   
                 Weakest Isnap 
               
               
                 N:P Ratio 
                 PSD Pullback 
                 (Normalized, Vgs = 1 V) 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 2:1 
                 0.0 
                 1.44 
               
               
                 1:1 
                 0.0 
                 1.00 
               
               
                 1:2 
                 0.0 
                 25.0 
               
               
                 2:1 
                 0.1 
                 2.79 
               
               
                 1:1 
                 0.1 
                 18.1 
               
               
                 1:2 
                 0.1 
                 55.6 
               
               
                   
               
            
           
         
       
     
     Thus, transistors consistent with the transistor  600  may provide lower transistor half-pitch, lower Rsp and greater SOA than otherwise similar baseline transistors, all three attributes providing valuable improvements for robust integrated circuit designs. 
     As is the case for MOS devices in general, the conductivity types of the structures described above with reference to  FIGS.  1 - 9    may be reversed. In general, reference can be made to a first conductivity type and second conductivity type, which may be n-type and p-type respectively, or p-type and n-type respectively. 
     Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.