Patent Publication Number: US-5841324-A

Title: Charge-based frequency locked loop and method

Description:
BACKGROUND OF THE INVENTION 
     The present invention is related to frequency locked loops and more specifically to a frequency locked loop and method which is based on switched-capacitor charge movement. 
     Frequency locked loops (FLL) are described in &#34;Designing Tracking Error-Free Varactor Tuners With Frequency Locked Loop Integrated Circuits&#34;, C. W. Malinowski and H. Rinderle, IEEE Transactions on Consumer Electronics, Vol. CE-26, February, 1980. FLLs are alternatives to phase locked loops which require less integrated circuit real estate, improve locking range, ease difficulties in obtaining fractional frequency multiplications, and reduce phase jitter and side locking. 
     The present invention improves on the prior art FLLs by using a switched-capacitor circuit with a simple topology and which comprises components whose values can be well controlled. As is known, a switched-capacitor circuit is a frequency-to-current converter. A capacitor holds a charge q in coulombs which is the product of its capacitance C and the voltage V. A switched capacitor operating at frequency ƒ moves a charge of ƒ·q coulombs per second, which is a current of ƒ·C·V amperes. 
     Accordingly, it is an object of the present invention to provide a novel charge-based FLL and method which obviates the problems of the prior art. 
     It is another object of the present invention to provide a novel FLL and method in which a feedback capacitor is switched at an oscillator output frequency to provide a current correction to the oscillator to control the frequency of the loop. 
     It is yet another object of the present invention to provide a novel method and charge-based FLL with an oscillator whose output frequency controls the amount of charge provided by a switched feedback capacitor to a charge integrator whose output voltage controls the frequency of the oscillator. 
     It is still another object of the present invention to provide a novel method and FLL with a switched-capacitor circuit for providing an input current to an integrating amplifier which is a function of a combination of a reference current related to a reference frequency and a feedback current related to an output frequency of an oscillator. 
     It is a further object of the present invention to provide a novel method and FLL with a switched-capacitor circuit for providing an input current to an integrating amplifier which controls a voltage controlled oscillator, in which plural reference capacitors each move a charge responsive to their respective reference frequencies so that the oscillator output frequency can be related to the sums or differences of the reference frequencies, the ratios of capacitors, the ratio of the reference voltages and/or a fixed multiplication factor. 
     These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a combination block and circuit diagram of an embodiment of the present invention. 
     FIG. 2 is a combination block and circuit diagram of a further embodiment of the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     With reference now to FIG. 1, an embodiment 10 of the charge-based FLL of the present invention may include an oscillator 12 whose output frequency ƒ OUT  controls the amount of charge provided by a switched feedback capacitor C FB  to a charge integrator 14 whose output voltage controls ƒ OUT . A divider 16 may be provided to divide ƒ OUT  by a factor N so that feedback frequency ƒ FB  =ƒ OUT  /N. Switched feedback capacitor C FB  operates at frequency ƒ FB  and moves a charge of ƒ FB  ·q coulombs per second, which is an effective DC current of ƒ FB  ·C FB  ·R REF2  amperes. Switches 18 for operating the switched capacitors may be responsive to the frequency indicated by the switch designation, where a bar indicates an opposite phase to that of no bar. 
     FLL 10 may also include a switched reference capacitor C REF  for providing a charge to charge integrator 14 which is a function of a reference frequency ƒ REF , so that oscillator 12 output frequency ƒ OUT  is a function of a product of reference frequency ƒ REF  times a ratio of the capacitance of reference capacitor C REF  to the capacitance of feedback capacitor C FB . Switched reference capacitor C REF  operates at frequency ƒ REF  and moves a charge of ƒ REF  ·q coulombs per second, which is an effective DC current of ƒ REF  ·C REF  ·V REF1  amperes. 
     In operation, a charge is moved from V REF1  by switched capacitor C REF  to node A and thus to integrator 14. The voltage output of integrator 14 moves in the negative direction in response to the added charge. If oscillator 12 has a negative gain, ƒ OUT  will increase. This increase causes feedback capacitor C FB  to remove charge from node A. 
     At a steady state condition, FLL 10 forces the currents provided by C REF  and C FB  to be equal (i.e., the direct current at node A is zero), and therefor: 
     
         ƒ.sub.REF ·C.sub.REF ·V.sub.REF1 =ƒ.sub.FB ·C.sub.FB ·V.sub.REF2(1) 
    
     Since ƒ FB  =ƒ OUT  /N, equation 1 may be rewritten: 
     
         ƒ.sub.OUT =N·ƒ.sub.REF ·(C.sub.REF /C.sub.FB)·(V.sub.REF1 /V.sub.REF2)              (2) 
    
     As is apparent, oscillator 12 output frequency ƒ OUT  may be a function of reference frequency ƒ REF , the ratio of the capacitances of the two switched capacitors C REF  and C FB , the ratio of the reference voltages V REF1  and R REF2 , and/or the factor from divider 16. The ratio of the reference voltages may be 1 (one) if the reference voltages are the same as would likely be normal, or may be set to offset or correct the ratio of the capacitances of the two switched capacitors. 
     In a preferred embodiment, FLL 10 is a single integrated circuit in which oscillator 12 is a voltage controlled oscillator (VCO) and charge integrator 14 is comprised of an accumulating capacitor and a high gain amplifier which provides the voltage for controlling the VCO. Switches 18 for operating the switched capacitors may be conventional integrated circuit switches suitable for the particular application, such as bipolar or field effect transistors. Switches 18 may also be discrete components which are switches of any type, albeit without the advantage of reduced real estate afforded by integrated circuit switches. The frequency divider factor N may be any number suitable for the particular application, including a number equal to or greater than one, or a fraction less than one (which implies a frequency multiplication). 
     With reference now to FIG. 2, a further embodiment 20 of the present invention may include a switched-capacitor circuit with plural reference capacitors, C REF1 ,2,3 in this embodiment although the invention is not limited to three reference capacitors. As will be apparent, other switched-capacitor circuits may also be used without departing from the scope of the present invention. Operation of the embodiment of FIG. 2 is the same as that of FIG. 1, but with greater flexibility. For example, capacitors C REF1  and C REF2  are both adding charge to the integrator (a charge integrating amplifier 22 in this embodiment) and capacitors C REF3  and C FB  are both removing charge from amplifier 22. The three reference capacitors may be clocked at respective reference frequencies ƒ REF1 , ƒ REF2  and ƒ REF3  which may be the same or different, and may be charged with respective reference voltages V REF1 , V REF2  and V REF3  which may be the same or different. 
     Under steady state conditions, the feedback of the scaled VCO output ƒ FB  to switches 18 which operate switched feedback capacitor C FB  forces the DC current entering node B to be zero, thereby setting the equality: 
     
         ƒ.sub.REF1 ·C.sub.REF1 ·V.sub.REF1 +ƒ.sub.REF2 ·C.sub.REF2 ·V.sub.REF2 -ƒ.sub.REF3 ·C.sub.REF3 ·V.sub.REF3 =ƒ.sub.OUT ·C.sub.FB ·V.sub.REF4 /N (3) 
    
     which may be rewritten as follows if the reference voltages are equal: 
     
         ƒ.sub.OUT =N· (ƒ.sub.REF1 ·C.sub.REF1)+(ƒ.sub.REF2 ·C.sub.REF2)-(ƒ.sub.REF3 ·C.sub.REF3)!/C.sub.FB(4) 
    
     Thus, oscillator output frequency ƒ OUT  may be a function of sums of frequencies, differences in frequencies, ratios of capacitors, the ratio of reference voltages and/or factor N. This simple circuit may be implemented in a single integrated circuit, and may include components whose values can be easily controlled in the manufacturing process. The output frequency may be made dependent only on relative matching of capacitors. 
     The loop bandwidth of the FLL can be adjusted independently of the oscillator output frequency by scaling all of the V REF  s by the same factor. The average current injected into the charge integrator by both the reference and feedback capacitors is related to their respective V REF  s. The loop bandwidth is directly related to how fast the charge integrator can be charged which is determined by the average current injected by each switched capacitor. Therefor a larger V REF  will have a higher loop bandwidth than will a smaller V REF . Loop bandwidth controls the rate at which the FLL operates, and one V REF  may be set to provide a wide bandwidth for fast initial acquisition, and then another V REF  may be used to provide a narrow bandwidth to slow down the loop and minimize jitter. 
     While preferred embodiments of the present invention have been described, it is to be understood that the embodiments described are illustrative only and the scope of the invention is to be defined solely by the appended claims when accorded a full range of equivalence, many variations and modifications naturally occurring to those of skill in the art from a perusal hereof.