Patent Publication Number: US-2023153017-A1

Title: Storage device, and host-storage system including the storage device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2021-0155301, filed on Nov. 12, 2021 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety. 
     TECHNICAL FIELD 
     Embodiments of the present disclosure are directed to a storage device, and to a host-storage system that includes the storage device. 
     DISCUSSION OF THE RELATED ART 
     When storing data, an erasure code stores not only an original data but also additional parity data, thereby enabling the original data to be restored when some of the original data is lost in a part of a storage device. 
     On the other hand, in many erasure codes used for existing RAID (Redundant Array of Independent Disk) and the like, a host generally performs a decoding computation, which may have several side effects. For example, the host may perform the computation by reading the remaining original data and parity data to restore the original data when a data is lost in a part of the storage device. However, excessive computational resources of the host may be used in this process. This can degrade bandwidth and latency of an overall system. 
     On the other hand, recently, due to computational storage devices that can perform computations, the storage device may autonomously perform the computation previously performed by the host as described above, thereby reducing the burden on the host. However, due to the characteristics of the erasure code, the computation might not be able to be performed only on the stored data by one storage device, and a data exchange between a plurality of storage devices may be needed. When the computed or stored data inside a computational storage device is exchanged between computational storage devices in a peer-to-peer (P2P) system, the overhead of the network may increase. 
     SUMMARY 
     Embodiments of the present disclosure provide a storage device that can perform a decoding method that utilizes computational resources inside a storage device, without using computational resources of the host. 
     Embodiments of the present disclosure also provide a host-storage system that can perform a decoding method that utilizes the computational resources inside the storage device, without using the computational resources of the host. 
     According to an embodiment of the present disclosure, there is a provided storage device that includes a non-volatile memory that stores a first original data and a first parity data, a storage controller that receives a second original data that differs from the first original data from an external storage device, and receives the first parity data from the non-volatile memory, and a computational engine that receives and computes the first parity data and the second original data from the storage controller, and restores a third original data that differs from the first original data and the second original data, wherein the storage controller receives the third original data from the computational engine and transmits the third original data to the host and the external storage device. 
     According to another embodiment of the present disclosure, there is a provided storage device that includes a first storage device that stores a first original data of an original data set that includes the first original data to a fourth original data and a first parity data, and a second storage device that stores the second original data and a second parity data that differs from the first parity data, wherein the first storage device computes the second original data received from the second storage device and the first parity data, and restores the third original data, and wherein the second storage device transmits the second original data simultaneously to the first storage device and a host. 
     According to another embodiment of the present disclosure, there is a provided host-storage system that includes a host, a storage device that includes a first storage device that stores a first data and a second storage device that stores a second data, and a host interface that connects the host and the storage device, wherein the host transmits a read command to the first storage device and the second storage device, wherein the first storage device transmits a third data that is at least a part of the first data simultaneously to the host and the second storage device in response to the read command, and wherein the second storage device executes a computation that uses the third data received from the first storage device and the second data. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a block diagram of a host-storage system according to some embodiments. 
         FIG.  2    illustrates a storage controller, a memory interface, and a non-volatile memory of  FIG.  1    that have been reconfigured. 
         FIG.  3    schematically shows an encoding method that uses an erasure code according to some embodiments. 
         FIG.  4    schematically illustrates a storage device that performs a decoding computation based on an erasure code according to some embodiments. 
         FIG.  5    schematically illustrates a host-storage system that performs a decoding computation based on an erasure code according to some embodiments. 
         FIG.  6    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
         FIG.  7    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
         FIG.  8    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
         FIG.  9    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
         FIG.  10    illustrates a method for performing a decoding computation by a computing engine based on an erasure code according to an embodiment. 
         FIG.  11    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
         FIG.  12    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
         FIG.  13    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
         FIG.  14    illustrates a method for performing a decoding computation by a computing engine based on an erasure code according to an embodiment. 
         FIG.  15    schematically illustrates an encoding method that uses an erasure code according to some embodiments. 
         FIG.  16    illustrates a method for performing a decoding computation by a host-storage system on the basis of an erasure code according to some embodiments. 
         FIG.  17    schematically illustrates an encoding method that uses an erasure code according to some other embodiment. 
         FIG.  18    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
         FIG.  19    is a flowchart of a data read and decoding computation of a host-storage system according to some embodiments. 
         FIG.  20    illustrates a data center that incorporates a storage device according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, embodiments according to a technical idea of the present disclosure will be described with reference to the accompanying drawings. 
       FIG.  1    is a block diagram of a host-storage system according to some embodiments. 
     In some embodiments, a host-storage system  10  includes a host  100  and a storage device  200 . The storage device  200  includes a storage controller  210 , a non-volatile memory (NVM)  220  and a computational engine (CE)  230 . Further, in some embodiments, the host  100  includes a host controller  110  and a host memory  120 . The host memory  120  functions as a buffer memory that temporarily stores data to be transmitted to the storage device  200  or data received from the storage device  200 . 
     The storage device  200  includes storage medium that stores data in response to a request from the host  100 . For example, the storage device  200  includes at least one of a Solid status Drive (SSD), an embedded memory, or a detachable external memory. When the storage device  200  is an SSD, the storage device  200  may be, for example, a device that complies with the non-volatility memory express (NVMe) standard. 
     When the storage device  200  is an embedded memory or an external memory, the storage device  200  complies with the UFS (universal flash storage) or the eMMC (embedded multi-media card) standards. The host  100  and the storage device  200  each generate and transmit packets according to the adopted standard protocol. 
     When the non-volatile memory  220  of the storage device  200  includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. For example, the storage device  200  may include various different types of non-volatile memories. For example, the storage device  200  may include a MRAM (Magnetic RAM), a spin-transfer torque MRAM, a conductive bridging RAM (CBRAM), a FeRAM (Ferroelectric RAM), a PRAM (Phase RAM), a resistive memory (Resistive RAM), and/or various other types of memories. 
     In some embodiments, the host controller  110  and the host memory  120  are implemented as separate semiconductor chips. Further, in some embodiments, the host controller  110  and the host memory  120  are integrated on the same semiconductor chip. For example, the host controller  110  may be one of a plurality of modules provided in an application processor, and the application processor may be implemented as a system on chip (SoC). Further, the host memory  120  may be an embedded memory provided inside the application processor, or a non-volatile memory or a memory module placed outside the application processor. 
     The host controller  110  manages an operation of storing data, such as write data, of a buffer region in the non-volatile memory  220  or storing data, such as read data, of the non-volatile memory  220  in the buffer region. 
     The storage controller  210  includes a host interface  211 , a memory interface  212 , and a central processing unit (CPU)  213 . In addition, the storage controller  210  furthers include a flash translation layer (FTL)  214 , a packet manager  215 , a buffer memory  216 , an error correction code (ECC) engine  217 , and an advanced encryption standard (AES) engine  218 . 
     The storage controller  210  further includes a working memory into which the flash translation layer (FTL)  214  is loaded, and when the CPU  213  executes the flash translation layer  214 , the data write and read operations of the non-volatile memory can be controlled. 
     The host interface  211  transmits and receives packets to and from the host  100 . The packets transmitted from the host  100  to the host interface  211  may include a command or data to be written to the non-volatile memory  220 , etc. The packets transmitted from the host interface  211  to the host  100  may include a response to the command or data that is read from the non-volatile memory  220 , etc. 
     The memory interface  212  transmits data to be written to the non-volatile memory  220  to the non-volatile memory  220  or receives data that is read from the non-volatile memory  220 . The memory interface  212  may be implemented to comply with standard protocols such as Toggle or ONFI. 
     The flash translation layer  214  performs various functions such as address mapping, wear-leveling, and/or garbage collection. Address mapping operation changes a logical address received from a host into a physical address that is used to actually store the data in the non-volatile memory  220 . Wear-leveling ensures that blocks in the non-volatile memory  220  are used uniformly to prevent excessive degradation of a particular block, and may be implemented, for example, through a firmware technique that balances erasure counts of the physical blocks. Garbage collection ensures the available capacity in the non-volatile memory  220  by copying valid data of an existing block to a new block and then erasing the existing block. 
     The packet manager  215  may generate a packet according to the protocol of the interface discussed with the host  100 , or may parse various types of information from the packet received from the host  100 . Further, the buffer memory  216  temporarily stores the data to be written to the non-volatile memory  220  or the data being read from the non-volatile memory  220 . The buffer memory  216  may be configured to be provided inside the storage controller  210 , or may be placed outside the storage controller  210 . 
     An ECC engine  217  performs error detection and correction functions on the read data that is read from the non-volatile memory  220 . More specifically, the ECC engine  217  generates parity bits for the write data to be written to the non-volatile memory  220 , and the generated parity bits are stored in the non-volatile memory  220  together with the write data. When reading the data from the non-volatile memory  220 , the ECC engine  217  corrects errors in the read data using the parity bits that are read from the non-volatile memory  220  together with the read data, and outputs the corrected read data. 
     An AES engine  218  performs at least one of an encryption and/or decryption operation on the data which is input to the storage controller  210  using a symmetric-key algorithm. 
     A computational engine  230  performs computations on the data that are read from the non-volatile memory  220 . For example, the computational engine  230  includes a field programmable gate array (FPGA). The computational engine  230  can perform an XOR computation to restore the whole original data when some original data are lost. The specific contents thereof will be described below. 
     On the other hand, although  FIG.  1    shows that the computational engine  230  is not included in the storage controller  210  and is shown as an independent configuration, embodiments of the present disclosure are not necessarily limited thereto, and in other embodiments, the computational engine  230  is included in the storage controller  210 . 
     Further, although  FIG.  1    shows that the computational engine  230  receives data stored in the non-volatile memory  220  from the storage controller  210 , embodiments of the present disclosure are not necessarily limited to thereto, and in other embodiment, the computational engine  230  receives the stored data from the non-volatile memory  220 . 
       FIG.  2    illustrates a storage controller, a memory interface, and a non-volatile memory of  FIG.  1    that have been reconfigured. 
     The memory interface  212  of  FIG.  1    has been reconfigured to include a controller interface circuit  212   a  and a memory interface circuit  212   b , as shown in  FIG.  2   . 
     The non-volatile memory  220  includes first to eighth pins P 11  to P 18 , a memory interface circuit  212   b , a control logic circuit  510 , and a memory cell array  520 . 
     The memory interface circuit  212   b  receives a chip enable signal nCE from the storage controller  210  through a first pin P 11 . The memory interface circuit  212   b  transmits and receives signals to and from the storage controller  210  through second to eighth pins P 12  to P 18  according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enable status, such as a low level, the memory interface circuit  212   b  transmits and receives signals to and from the storage controller  210  through second to eighth pins P 12  to P 18 . 
     The memory interface circuit  212   b  receives a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the storage controller  210  through the second to fourth pins P 12  to P 14 , respectively. The memory interface circuit  212   b  receives a data signal DQ from the storage controller  210  or transmits the data signal DQ to the storage controller  210  through a seventh pin P 17 . The command CMD, the address ADDR, and the data are transmitted through the data signal DQ. For example, the data signal DQ may be transmitted through a plurality of data signal lines. The seventh pin P 17  may include a plurality of pins that correspond to the plurality of data signals. 
     The memory interface circuit  212   b  acquires the command CMD from the data signal DQ received in an enable section, such as a high level status, of the command latch enable signal CLE on the basis of toggle timings of the write enable signal nWE. The memory interface circuit  212   b  acquires the address ADDR from the data signal DQ received in the enable section, such as the high level status, of the address latch enable signal ALE on the basis of the toggle timings of the write enable signal nWE. 
     In some embodiments, the write enable signal nWE holds a static status, such as a high level or a low level, and is then toggled between the high level and the low level. For example, the write enable signal nWE is toggled at a section in which the command CMD or the address ADDR is transmitted. Accordingly, the memory interface circuit  212   b  acquires the command CMD or the address ADDR on the basis of the toggle timings of the write enable signal nWE. 
     The memory interface circuit  212   b  receives a read enable signal nRE from the storage controller  210  through a fifth pin P 15 . The memory interface circuit  212   b  receives a data strobe signal DQS from the storage controller  210  or transmits the data strobe signal DQS to the storage controller  210 , through a sixth pin P 16 . 
     In a data DATA output operation of the non-volatile memory  220 , the memory interface circuit  212   b  receives the toggled read enable signal nRE through the fifth pin P 15  before outputting the data DATA. The memory interface circuit  212   b  generates the toggled data strobe signal DQS on the basis of toggling the read enable signal nRE. For example, the memory interface circuit  212   b  generates the data strobe signal DQS that starts to toggle after a predetermined delay, such as tDQSRE, on the basis of the toggling start time of the read enable signal nRE. The memory interface circuit  212   b  transmits a data signal DQ that includes the data DATA on the basis of the toggle timing of the data strobe signal DQS. Accordingly, the data DATA is arranged by the toggle timing of the data strobe signal DQS and transmitted to the storage controller  210 . 
     In a data DATA input operation of the non-volatile memory  220 , when the data signal DQ that includes the data DATA is received from the storage controller  210 , the memory interface circuit  212   b  receives the toggled data strobe signal DQS together with the data DATA from the storage controller  210 . The memory interface circuit  212   b  acquires the data DATA from the data signal DQ on the basis of the toggle timing of the data strobe signal DQS. For example, the memory interface circuit  212   b  acquires the data DATA by sampling the data signal DQ at a rising edge and a falling edge of the data strobe signal DQS. 
     The memory interface circuit  212   b  transmits a ready/busy output signal nR/B to the storage controller  210  through an eighth pin P 18 . The memory interface circuit  212   b  transmits the status information of the non-volatile memory  220  to the storage controller  210  through the ready/busy output signal nR/B. When the non-volatile memory  220  is in a busy status, for example, when the internal operations of the non-volatile memory  220  are being performed, the memory interface circuit  212   b  transmits the ready/busy output signal nR/B that indicates the busy status to the storage controller  210 . When the non-volatile memory  220  is in a ready status, for example, when the internal operations of the non-volatile memory  220  are not being performed or are completed, the memory interface circuit  212   b  transmits the ready/busy output signal nR/B that indicates the ready status to the storage controller  210 . 
     For example, when the non-volatile memory  220  reads the data DATA from the memory cell array  520  in response to a page read command, the memory interface circuit  212   b  transmits a ready/busy output signal nR/B that indicates busy status, such as a low level, to the storage controller  210 . For example, when the non-volatile memory  220  programs data DATA into the memory cell array  520  in response to a program instruction, the memory interface circuit  212   b  transmits a ready/busy output signal nR/B that indicates busy status to the storage controller  210 . 
     The control logic circuit  510  generally controls various operations of the non-volatile memory  220 . The control logic circuit  510  receives the command/address CMD/ADDR acquired from the memory interface circuit  212   b . The control logic circuit  510  generates control signals that control other constituent elements of the non-volatile memory  220  according to the received command/address CMD/ADDR. For example, the control logic circuit  510  generates various control signals that program data DATA to the memory cell array  520  or read data DATA from the memory cell array  520   
     The memory cell array  520  stores data DATA acquired from the memory interface circuit  212   b  according to the control of the control logic circuit  510 . The memory cell array  520  outputs stored data DATA to the memory interface circuit  212   b  according to the control of the control logic circuit  510 . 
     The memory cell array  520  includes a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, embodiments of the present disclosure are not necessarily limited thereto, and the memory cells may be a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, or a magnetic random access memory (MRAM) cell. Hereinafter, embodiments of the present disclosure will be described on the basis of an embodiment in which the memory cells are NAND flash memory cells. 
     The storage controller  210  include first to eighth pins P 21  to P 28 , and a controller interface circuit  212   a . The first to eighth pins P 21  to P 28  respectively correspond to the first to eighth pins P 11  to P 18  of the non-volatile memory  220 . 
     The controller interface circuit  212   a  transmits the chip enable signal nCE to the non-volatile memory  220  through a first pin P 21 . The controller interface circuit  212   a  transmits and receives signals to and from the non-volatile memory  220 , which are selected through the chip enable signal nCE, through the second to eighth pins P 22  to P 28 . 
     The controller interface circuit  212   a  transmits the command latch enable signal CL E, the address latch enable signal ALE, and the write enable signal nWE to the non-volatile memory  220  through the second to fourth pins P 22  to P 24 , respectively. The controller interface circuit  212   a  transmits the data signal DQ to the non-volatile memory  220  through a seventh pin P 27  or receives the data signal DQ from the non-volatile memory  220 . 
     The controller interface circuit  212   a  transmits the data signal DQ that includes the command CMD or the address ADDR, along with a toggled write enable signal, to the non-volatile memory  220 . The controller interface circuit  212   a  transmits the data signal DQ that includes the command CMD to the non-volatile memory  220  by transmitting an enable status command latch enable signal CLE, and transmits the data signal DQ that includes the address ADDR to the non-volatile memory  220  by transmitting an enable status address latch enable signal ALE. 
     The controller interface circuit  212   a  transmits the read enable signal nRE to the non-volatile memory  220  through a fifth pin P 25 . The controller interface circuit  212   a  receives the data strobe signal DQS from the non-volatile memory  220  or transmits the data strobe signal DQS to the non-volatile memory  220  through a sixth pin P 26 . 
     In a data DATA output operation of the non-volatile memory  220 , the controller interface circuit  212   a  generates a toggled read enable signal nRE and transmits the read enable signal nRE to the non-volatile memory  220 . For example, the controller interface circuit  212   a  generates a read enable signal nRE that changes from a static status, such as a high level or a low level, to toggle status, before the data DATA is output. Accordingly, the toggled data strobe signal DQS is generated in the non-volatile memory  220  on the basis of the read enable signal nRE. The controller interface circuit  212   a  receives the data signal DQ that includes the data DATA together with the toggled data strobe signal DQS from the non-volatile memory  220 . The controller interface circuit  212   a  acquires the data DATA from the data signal DQ on the basis of the toggle timing of the data strobe signal DQS. 
     In a data DATA input operation of the non-volatile memory  220 , the controller interface circuit  212   a  generates a toggled data strobe signal DQS. For example, the controller interface circuit  212   a  generates a data strobe signal DQS that changes from a static status, such as a high level or a low level) to toggle status before transmitting the data DATA. The controller interface circuit  212   a  transmits the data signal DQ that includes the data DATA to the non-volatile memory  220  on the basis of the toggle timings of the data strobe signal DQS. 
     The controller interface circuit  212   a  receives a ready/busy output signal nR/B from the non-volatile memory  220  through an eighth pin P 28 . The controller interface circuit  212   a  discriminates the status information of the non-volatile memory  220  on the basis of the ready/busy output signal nR/B. 
       FIG.  3    illustrates an encoding method that uses an erasure code according to some embodiments. 
     Referring to  FIG.  3   , in some embodiments, (A) shows a first storage device  200 _ 1  that stores two original data OD 1  and OD 2 , and a second storage device  2002  that also stores two original data OD 3  and OD 4 . Each of the original data OD 1  to OD 4  has a size of 1 bit, and the entire data stored in the single storage device may be defined as a data block. 
     In (A), the size of all original data is 4 bits because there are four original data. However, embodiments are not necessarily limited thereto, and in other embodiments, the size of the whole original data and the size of the data block stored in the single storage device may vary. 
     An encoding method according to some embodiments stores the generated parity data together with the original data in a plurality of storage devices, while maintaining the whole original data. 
     Specifically, in (B), additional storage devices are used to store the original data OD 1  to OD 4  and the additionally generated parity data PD 1  to PD 4 . That is, to store the existing original data OD 1  to OD 4  and the additionally generated parity data PD 1  to PD 4 , a third storage device  200 _ 3  and a fourth storage device  200 _ 4  are used. 
     In an encoding process, each of the plurality of storage devices  200 _ 1  to  200 _ 4  evenly distributes and stores the original data OD 1  to OD 4 . Further, each of the plurality of storage devices  200 _ 1  to  200 _ 4  evenly distributes and stores the parity data PD 1  to PD 4 . 
     Specifically, the first storage device  200 _ 1  stores one original data OD 1  and one parity data PD 1 . The second storage device  200 _ 2  stores one original data OD 2  and one parity data PD 2 . The third storage device  200 _ 3  stores one original data OD 3  and one parity data PD 3 . The fourth storage device  200 _ 4  stores one original data OD and one parity data PD 4 . 
     The parity data is data generated by performing an XOR computation on an original data of the whole original data and is used to restore the original data. Specifically, the parity data is generated by performing an XOR computation on two original datas of the entire four original datas so that all the four original datas can be restored even if only two of the four storage devices  200 _ 1  to  200 _ 4  are used. 
     The respective size of each parity data PD 1  to PD 4  is 1 bit, which is the same as the respective sizes of the original data OD 1  to OD 4 . Therefore, the size of the data block stored in the plurality of storage devices  200 _ 1  to  2004  is kept as 2 bits before and after encoding. 
     On the other hand, although  FIG.  3    shows that four original data OD 1  to OEM that are evenly distributed one by one to each of the four storage devices  200 _ 1  to  2004 , embodiments are not necessarily limited thereto. Specifically, when, for example, three original datas exist, new data can be generated through a process such as data padding and can be evenly distributed to the plurality of storage devices  200 _ 1  to  200 _ 4 . 
       FIG.  4    schematically illustrates a storage device that performs an decoding computation based on an erasure code according to some embodiments. 
     Referring to  FIG.  4   , in some embodiments, the storage device  200  includes a plurality of storage devices  2001  to  200 _ 4 . Each of the plurality of storage devices  2001  to  200 _ 4  include storage controllers  210 _ 1  to  210 _ 4 , non-volatile memories  220 _ 1  to  220 _ 4 , and computational engines  230 _ 1  to  230 _ 4  as described with reference to  FIG.  1   . 
     Although  FIG.  4    shows the computational engines  230 _ 1  to  230 _ 4  as independent entities, and the data stored in the non-volatile memories  220 _ 1  to  220 _ 4  as received from the storage controllers  210 _ 1  to  210 _ 4 , embodiments are not necessarily limited thereto. As illustrated in  FIG.  1   , the computational engines  230 _ 1  to  230 _ 4  may be included in the storage controllers  210 _ 1  to  210 _ 4  and may directly receive the data stored in the non-volatile memories  220 _ 1  to  220 _ 4 , depending on the internal configuration. 
       FIG.  5    schematically illustrates a host-storage system that performs a decoding computation based on an erasure code according to some embodiments. 
     Referring to  FIG.  5   , in some embodiments, the host-storage system  10  include a host  100 , a plurality of storage devices  200 _ 1  to  200 _ 4 , and a switch SW. 
     The host-storage system  10  shown in  FIG.  5    has substantially the same operation as the host-storage system  10  shown in  FIG.  1   , except that the former includes a plurality of storage devices  200 _ 1  to  200 _ 4 . 
     The switch SW may be configured to be included in the host interface  211  shown in  FIG.  1   . Although the switch SW may be implemented as an Ethernet or a PCIe switch, embodiments are not necessarily limited thereto. 
     The plurality of storage devices  200 _ 1  to  200 _ 4  and the host  100  are connected to the switch SW to share data. For example, the data stored in any one of the plurality of storage devices  200 _ 1  to  200 _ 4  can be transmitted to another of the plurality of storage devices  200 _ 1  to  200 _ 4 , or can be transmitted to the host  100 . 
     Specifically, as described with reference to  FIG.  3   , the data stored in the plurality of storage devices  200 _ 1  to  200 _ 4  includes the original data and the parity data. Of this data, only the original data is transmitted to the host  100  from the plurality of storage devices  200 _ 1  to  200 _ 4 . For example, a total amount of transmission to the host  100  is equal to a capacity of the whole original data. 
     More specifically, the original data stored in any of the plurality of storage devices  200 _ 1  to  200 _ 4  can be transmitted to one of the other storage devices  200 _ 1  to  200 _ 4  at the time of transmission to the host  100 . For example, the original data stored in one of the plurality of storage devices  200 _ 1  to  200 _ 4  is transmitted to another of the plurality of storage devices  200 _ 1  to  200 _ 4  through a multicast or broadcast method. 
     However, at the same time when the original data stored in one of the plurality of storage devices  200 _ 1  to  200 _ 4  is transmitted to the host  100 , the original data does not always need to be transmitted to the other storage devices  200 _ 1  to  200 _ 4 . Specifically, the stored original data can be transmitted at the time when it is transmitted to the multiple destinations to reduce the overhead of the entire network. 
     Through the aforementioned conditions, since the host  100  receives only the original data, to the host does not participate in a decoding computation, and thus the consumption of the host&#39;s  100  computational resources can be reduced. Further, since the data is shared between the plurality of storage devices  200 _ 1  to  200 _ 4  by a multicast or broadcast method, not a P2P (Peer to peer) method, the consumption of communication resources can be reduced. Accordingly, network overhead can be prevented. 
       FIG.  6    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
     Referring to  FIG.  6   , in some embodiments, a first non-volatile memory  220 _ 1  stores a first original data X 1  and first parity data X 2 +X 3 . That is, the first original data X 1  and the first parity data X 2 +X 3  correspond to OD 1  and PD 1  shown in  FIG.  3   , respectively. 
     A second non-volatile memory  2202  stores a second original data X 2  and second parity data X 3 +X 4 . That is, the second original data X 2  and the second parity data X 3 +X 4  correspond to OD 2  and PD 2  shown in  FIG.  3   , respectively. 
     A third non-volatile memory  220 _ 3  stores a third original data X 3  and third parity data X 1 +X 4 . That is, the third original data X 3  and the third parity data X 1 +X 4  correspond to the OD 3  and PD 3  shown in  FIG.  3   , respectively. 
     A fourth non-volatile memory  220 _ 4  stores a fourth original data X 4  and fourth parity data X 1 +X 2 . That is, the fourth original data X 4  and the fourth parity data X 1 +X 2  correspond to the OD 4  and PD 4  shown in  FIG.  3   , respectively. 
       FIGS.  7  to  9  and  11  to  13    illustrate a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments.  FIGS.  10  and  14    illustrate a method for performing a decoding computation by a computing engine based on an erasure code according to an embodiment. Hereinafter, description will be made referring to  FIGS.  7  to  14   . 
     First, referring to  FIG.  7   , in some embodiments, for example, assume that the third storage device  200 _ 3  and the fourth storage device  200 _ 4  are in a disabled status. In this case, the host  100  cannot read the third original data X 3  stored in the third storage device  200 _ 3  and the fourth original data X 4  stored in the fourth storage device  200 _ 4 . 
     When some of the plurality of storage devices are disabled, the storage device capable of performing a distributed decoding according to some embodiments of the present disclosure restores the original data by using the stored original data and parity data, and provides the whole original data in response to a read command of the host. 
     Referring to  FIG.  8   , in some embodiments, the second original data X 2  stored in the second non-volatile memory  2202  of the second storage device  200 _ 2  is transmitted to a first computational engine  230 _ 1  of the first storage device  200 _ 1  through a switch SW. Further, the second original data X 2  is also transmitted to the host  100  through a multicast transmission method. 
     On the other hand, as described with reference to  FIG.  5   , since only the original data can be moved to the plurality of storage devices  200 _ 1  to  200 _ 4  and the host  100 , the second parity data X 3 +X 4  stored in the second non-volatile memory  2202  is not transmitted through the switch SW in  FIG.  8   . 
     Referring to  FIG.  9   , in some embodiments, the first computational engine  230 _ 1  performs a computation based on the first parity data X 2 +X 3  stored in the first non-volatile memory  220 _ 1  and the second original data X 2  provided from the second storage device  200 _ 2  to restore the third original data X 3 . Specifically, the first computational engine  230 _ 1  performs an XOR computation on the first parity data X 2 +X 3  and the second original data X 2  to restore the third original data X 3 . 
     Referring to  FIG.  10   , in some embodiments, in Table 1, assume that, for example, the first original data X 1  has a value of 1, the second original data X 2  has a value of 0, the third original data X 3  has a value of 0, and the fourth original data X 4  has a value of 1. 
     The parity data is obtained by performing an XOR computation based on the original data as described with reference to  FIG.  3   . Therefore, in  FIG.  9   , the first parity data X 2 +X 3  has a value of 0, the second parity data X 3 +X 4  has a value of 1, the third parity data X 1 +X 4  has a value of 0, and the fourth parity data X 1 +X 2  has a value of 1. 
     Referring to Table II, the first computational engine  230 _ 1  of  FIG.  9    performs an XOR computation based on the first parity data X 2 +X 3  and the second original data X 2 , and the corresponding result value is 0. For example, the first computational engine  230 _ 1  restores the third original data X 3  through the XOR computation of the first parity data X 2 +X 3  and the second original data X 2 . 
     Referring to  FIG.  11   , in some embodiments, the third original data X 3  restored by the first computational engine  230 _ 1  is transmitted to a second computational engine  230 _ 2  of the second storage device  200 _ 2  through the switch SW. Similar to the second original data X 2 , the third original data X 3  is also transmitted to the host  100  through a multicast transmission method. 
     On the other hand, as described with reference to  FIG.  5   , since only the original data can be moved to the plurality of storage devices  200 _ 1  to  200 _ 4  and the host  100 , the first parity data X 2 +X 3  stored in the first non-volatile memory  220 _ 1  of the first storage device  200 _ 1  is not transmitted through the switch SW. 
     Referring to  FIG.  12   , in some embodiments, the second computational engine  230 _ 2  performs a computation on the basis of the second parity data X 3 +X 4  stored in the second non-volatile memory  220 _ 2  and the third original data X 3  provided from the first storage device  200 _ 1  to restore the fourth original data X 4 . Specifically, the second computational engine  230 _ 2  performs an XOR computation on the second parity data X 3 +X 4  and the third original data X 3  to restore the fourth original data X 4 . 
     Referring to  FIG.  10   , In some embodiments, in Table II, the third original data X 3  restored from the first storage device  200 _ 1  has a value of 0, and the second parity data X 3 +X 4  stored in the second non-volatile memory  220 . 2  has a value of 1. Therefore, the second computational engine  230 _ 2  of  FIG.  12    performs an XOR computation based on the second parity data X 3 +X 4  and the third original data X 3 , and the corresponding result value is 1. For example, the second computational engine  230 _ 2  restores the fourth original data X 4  through an XOR computation of the second parity data X 3 +X 4  and the third original data X 3 . 
     Referring to  FIG.  13   , in some embodiments, in response to a read command of the host  100 , the first storage device  200 _ 1  transmits the first original data X 1  to the host, and the second storage device  200 _ 2  transmits the restored fourth original data X 4  to the host. 
     The transmission of the original data between the plurality of storage devices is performed simultaneously when the original data is transmitted to the host. However, when the original data is transmitted from one of the plurality of storage devices to the host, the original data need not be transmitted to any of the plurality of storage devices. Therefore, the first original data X 1  stored in the first storage device  200 _ 1  is not transmitted to the second storage device  200 _ 2 , and the fourth original data X 4  restored from the second storage device  200 _ 2  is also not transmitted to the first storage device  200 _ 1 . 
     The second original data X 2  and the third original data X 3  present in the first computational engine  230 _ 1  are deleted from the first computational engine  230 _ 1  when an decoding operation that corresponds to a read command of the host is completed. Similarly, the third original data X 3  and the fourth original data X 4  present in the second computational engine  230 _ 2  are also deleted from the second computational engine  230 _ 2  when an decoding operation is completed. 
     Referring to  FIG.  14   , in some embodiments, unlike  FIG.  10   , in Table III, assume that, for example, the first original data X 1  has a value of 1, the second original data X 2  has a value of 1, the third original data X 3  has a value of 0, and the fourth original data X 4  has a value of 1. 
     Further, as shown in  FIGS.  6  to  9  and  10  to  13   , assume that the first to fourth original data and the first to fourth parity data are stored, and the third storage device  200 _ 3  and the fourth storage device  200 _ 4  are in a disabled status. 
     As described with reference to  FIGS.  6  to  13   , the first computational engine  230 _ 1  restores the third original data X 3  based on the first parity data X 2 +X 3  and the second original data X 2 , and the second computational engine  230 _ 3  restores the fourth original data X 4  based on the second parity data X 3 +X 4  and the restored third original data X 3 . 
     Specifically, referring to Table IV of  FIG.  14   , in some embodiments, the first computational engine  230 _ 1  restores the third original data X 3  of a value of 0 through an XOR computation of the first parity data X 2 +X 3 , which have a value of 1, and the second original data X 2 , which have a value of 1. Similarly, the second computational engine  230 _ 2  restores the fourth original data X 4  to a value of 1 through an XOR computation of the second parity data X 3 +X 4 , which has a value of 1, and the restored third original data X 3 , which has a value of 0. 
     For example, all the original data is restored through an erasure code according to some embodiments and a distributed decoding method that uses the storage device. 
     In addition, although  FIGS.  7  to  13    show that the third storage device  200 _ 3  and the fourth storage device  200 _ 4  are disabled, for example, now assume that the first storage device  200 _ 1  and the second storage device  200 _ 2  are disabled. 
     Similar to the method described with reference to  FIGS.  7  to  13   , first, the fourth storage device  200 _ 4  transmits the fourth original data X 4  to the host  100  and the third storage device  200 _ 3 . 
     A third computational engine  230 _ 3  performs a computation based on the third parity data X 1 +X 4  stored in the third non-volatile memory  220 _ 3  and the fourth original data X 4  received from the fourth storage device  200 _ 4  to restore the first original data X 1 . 
     Specifically, referring to Table IV of  FIG.  14   , the third computational engine  230 _ 3  restores the first original data X 1  to a value of 1 through an XOR computation of the third parity data X 1 +X 4 , which has a value of 0, and the fourth original data X 4 , which has a value of 1. 
     The third storage device  200 _ 3  transmits the restored first original data X 1  to the host  100  and the fourth storage device  200 _ 4 . 
     A fourth computational engine  2304  performs a computation based on the fourth parity data X 1 +X 2  stored in the fourth non-volatile memory  220 _ 4  and the restored first original data X 1  received from the third storage device  200 _ 3  to restore the second original data X 2 . 
     Specifically, referring to Table IV of  FIG.  14   , the fourth computational engine  230 _ 4  restores the second original data X 2  to a value of 1 through an XOR computation of the fourth parity data X 1 +X 2 , which has a value of 0 and the first original data X 1 , which has a value of 1. 
     The third storage device  200 _ 3  transmits the stored third original data X 3  to the host  100 , and the fourth storage device  200 _ 4  transmits the restored second original data X 2  to the host  100 , and the host  100  reads all of the original data. 
     For example, all of the original data can be restored through any two of the four storage devices  200 _ 1  to  200 _ 4  shown in  FIGS.  7  to  13   , through an erasure code according to some embodiments and a distributed decoding method of a storage device. Specifically, all the original data can be restored in all cases of  4 C 2 =6. 
     Further, parity data is generated and decoding is performed, unlike that shown in  FIGS.  7  to  13   . 
     For example, assume that the first parity data is X 2 +X 4 , the second parity data is X 1 +X 3 , the third parity data is X 1 +X 4 , and the fourth parity data is X 2 +X 3 . Further, assume that the second storage device  200 . 2  and the third storage device  200 _ 3  are disabled. 
     As in a method described with reference to  FIGS.  7  to  13   , first, the fourth storage device  200 _ 4  transmits the fourth original data X 4  to the host  100  and the first storage device  200 _ 1 . 
     The first computational engine  230 _ 1  performs a computation based on the first parity data X 2 +X 4  stored in the first non-volatile memory  220 _ 1  and the fourth original data X 4  received from the fourth storage device  200 _ 4  to restore the second original data X 2 . 
     Specifically, referring to Table IV of  FIG.  14   , the first computational engine  230 _ 1  restores the second original data X 2  to a value of 1 through an XOR computation of the first parity data X 2 +X 4 , which has a value of 0, and the fourth original data X 4 , which has a value of 1. 
     The first storage device  200 _ 1  transmits the restored second original data X 2  to the host  100  and the fourth storage device  200 _ 4 . 
     The fourth computational engine  2304  performs a computation based on the fourth parity data X 2 -+X 3  stored in the fourth non-volatile memory  220 _ 4  and the restored second original data X 2  received from the first storage device  200 _ 1  to restore the third original data X 3 . 
     Specifically, referring to Table IV of  FIG.  14   , the fourth computational engine  230 _ 4  restores the third original data X 3  to a value of 0 through an XOR computation of the fourth parity data X 2 +X 3 , which has a value of 1, and the second original data X 2 , which has a value of 1. 
     The first storage device  200 _ 1  transmits the stored first original data X 1  to the host  100 , and the fourth storage device  200 _ 4  transmits the restored third original data X 3  to the host  100 , and the host  100  reads all of the original data. 
     For example, there is not only a combination of the parity data shown in  FIGS.  7  to  13   , but also a combination of various parity data that enables all the original data to be restored by using the original data and the parity data stored in any two storage devices. 
       FIG.  15    schematically illustrates an encoding method that uses an erasure code according to some embodiments. Hereinafter, differences from embodiments described with reference to  FIG.  3    will be mainly described. 
     Referring to  FIG.  15   , in some embodiments, unlike  FIG.  3   , in (A), the first storage device  200 _ 1  stores five original data OD 1  to OD 5 , the second storage device  200 _ 1  similarly stores five original data OD 6  to OD 10 , and the third storage device  200 _ 3  also similarly stores five original data OD 11  to OD 15 . In (A), the size of the whole original data is 15 bits because there are fifteen original datas. 
     In (B), additional storage devices are used to store the original data OD 1  to OD 15  and the additionally generated parity data PD 1  to PD 10 . For example, the fourth storage device  200 _ 4  and the fifth storage device  200 _ 5  are used to store the existing original data OD 1  to OD 15  and the additionally generated parity data PD 1  to PD 10 . 
     In a encoding process, each of the plurality of storage devices  200 _ 1  to  200 _ 5  evenly distributes and stores the original data OD 1  to OD 15 . Further, each of the plurality of storage devices  200 _ 1  to  200 _ 5  evenly distributes and stores the parity data PD 1  to PD 10 . 
     Specifically, the first storage device  2001  stores three original data OD 1  to OD 3  and two parity data PD 1  and PD 2 . The second storage device  200 _ 2  stores three original data OD 4  to OD 6  and two parity data PD 3  and PD 4 . The third storage device  200 _ 3  stores three original data OD 7  to OD 9  and two parity data PD 5  and PD 6 . The fourth storage device  200 _ 4  stores three original data OD 10  to OD 12  and two parity data PD 7  and PD 8 . The fifth storage device  200 _ 5  stores three original data D 13  to OD 15  and two parity data PD 9  and PD 10 . 
     As described with reference to  FIG.  3   , in some embodiments, the parity data is generated by performing an XOR computation on original data of the whole original data to restore the original data. Specifically, the parity data is generated by performing an XOR computation on three original data of the fifteen whole original data so that all the fifteen original data can be restored even if only any three of the five storage devices  200 _ 1  to  200 _ 5  are used. 
     The sizes of each of the parity data PD 1  to PD 10  is 1 bit, which is the same as the sizes of each of the original data OD 1  to OD 15 . Therefore, the size of the data block stored in the plurality of storage devices  200 _ 1  to  200 _ 5  is 5 bits both before and after encoding. 
       FIG.  16    illustrates a method for performing a decoding computation by a host-storage system on the basis of an erasure code according to some embodiments. 
     Referring to  FIG.  16   , in some embodiments, all the original data X 1  to X 15  can be restored by using any three storage devices of the five storage devices  200 _ 1  to  200 _ 5 . Since a specific method is substantially the same as that described with reference to  FIGS.  7  to  13   , a repeated description is omitted below. 
     Further, as described with reference to  FIGS.  7  to  13   , in addition to parity data combinations shown in  FIG.  16   , there are also other combinations of parity data that enable all of the original data to be restored by the use of the original data and the parity data stored in the three any storage devices. 
       FIG.  17    schematically illustrates an encoding method using an erasure code according to some embodiments. 
     Referring to  FIG.  17   , in some embodiments, unlike  FIGS.  3  and  15   , in (A), the first storage device  200 _ 1  stores six original data OD 1  to OD 6 , the second storage device  200 _ 2  stores six original data OD 7  to OD 12 , the third storage device  200 _ 3  also stores six original data OD 13  to OD 18 , and the fourth storage device  200 _ 4  also stores six original data OD 19  to OD 24 . In (A), the size of the whole original data is 24 bits because there are twenty-four original datas. 
     In (B), additional storage devices are used to store the original data OD 1  to OD 24  and the additionally generated parity data PD 1  to PD 12 . That is, a fifth storage device  2005  and a sixth storage device  200 _ 6  are used to store the existing original data OD 1  to OD 24  and the additionally generated parity data PD 1  to PD 12 . 
     In an encoding process, each of the plurality of storage devices  200 _ 1  to  200 _ 6  evenly distributes and stores the original data OD 1  to OD 24 . Further, each of the plurality of storage devices  200 _ 1  to  200 _ 6  evenly distributes and stores the parity data PD 1  to PD 12 . 
     Specifically, the first storage device  200 _ 1  stores four original data OD 1  to OD 4  and two parity data PD 1  and PD 2 . The second storage device  200 _ 2  stores four original data OD 5  to OD 8  and two parity data PD 3  and PD 4 . The third storage device  200 _ 3  stores four original data OD 9  to OD 12  and two parity data PD 5  and PD 6 . The fourth storage device  200 _ 4  stores four original data OD 13  to OD 16  and two parity data PD 7  and PD 8 . The fifth storage device  200 _ 5  stores four original data OD 17  to OD 20  and two parity data PD 9  and PD 10 . The sixth storage device  200 _ 6  stores four original data OD 21  to OD 24  and two parity data PD 11  and PD 12 . 
     As described with reference to  FIGS.  3  and  15   , the parity data is generated by performing an XOR computation on any original data of the whole original data to restore the original data. Specifically, the parity data is generated by performing an XOR computation on four original data of twenty-four original data so that all of the twenty-four original data can be restored even if only four of the six storage devices  200 _ 1  to  200 _ 6  are used. 
     The respective sizes of each of the parity data PD 1  to PD 12  is 1 bit, which is the same as the respective sizes of each of the original data OD 1  to OD 4 . Therefore, the size of a data block stored in the plurality of storage devices  200 _ 1  to  200 _ 6  is 6 bits both before and after encoding. 
       FIG.  18    illustrates a method for performing a decoding computation by a host-storage system based on an erasure code according to some embodiments. 
     Referring to  FIG.  18   , in some embodiments, all of the original data X 1  to X 24  can be restored by using any four of the six storage devices  200 _ 1  to  200 _ 6 . Since a specific method is substantially the same as that described with reference to  FIGS.  7  to  13   , a repeated description thereof will omitted below. 
     Further, as described in  FIGS.  7  to  13   , in addition to combinations of parity data shown in  FIG.  18   , various other combinations of parity data also enable all of the original data to be restored by using the original data and the parity data stored in any four storage devices. 
     Assuming, for convenience of description, that the number of original data blocks is K and the number of encoded data blocks is N, (N, K)=(4, 2) is described as an example with reference to  FIGS.  7  to  13   , (N, K)=(5, 3) is described as an example with reference to  FIGS.  15  to  16   , and (N, K)=(6, 4) is described as an example with reference to  FIGS.  17  to  18   . However, embodiments are not necessarily limited thereto. 
     Further, although  FIGS.  7  to  18    illustrate as an example a host-storage system that has a relationship of (N, K)=(K+2, K) and can restore the original data by the data stored in any K storage devices, embodiments are not necessarily limited thereto. 
     For example, in some embodiments, a host-storage system may have a relationship of (N, K)=(4, 3) or may have a relationship of (N, K)=(10, 2). That is, according to an embodiment, a host-storage system can be configured by changing the relationship between N and K, and a distributed decoding can be performed on the storage device accordingly. Further, when a specific storage device of less than N−K is not available, a distributed decoding can be performed using the data stored in K+1 or more storage devices. 
     On the other hand, as the value of N/K approaches 1, a ratio of a parity block to be added as compared to the original data block is small. For example, as the value of N/K approaches 1, an above-described decoding method can be executed while efficiently using the storage space. 
       FIG.  19    illustrates a data read and decoding computation of a host-storage system according to some embodiments. 
     Referring to  FIG.  19   , in some embodiments, the host provides a read command to the first storage controller and the second storage device to read the original data (S 10 ). Specifically, the host provides a read command to the first storage controller in the first storage device and the second storage controller in the second storage device. 
     The second storage device reads the second original data stored in the second non-volatile memory (S 11 ). The second original data is transmitted to the host and the first storage controller (S 12 ). For example, as described above, the second original data is simultaneously transmitted to the first storage controller and the host through a multicast or broadcast method. 
     The first storage controller provides the received read command to the first non-volatile memory (S 13 ). In response, the first non-volatile memory reads the first parity data (S 14 ). Further, the first non-volatile memory provides the read first parity data to the first storage controller (S 15 ). 
     Although  FIG.  19    shows that the second original data read operation of the second storage device is performed before the first parity data read operation of the first non-volatile memory, this is for convenience of description, and embodiments are not necessarily limited thereto. For example, in other embodiments, the above two operations may be performed in a different order from each other, or may be performed at the same time. 
     The first storage controller provides the received second original data and first parity data to the first computational engine (S 16 ). The first computational engine performs an XOR computation on the received second original data and first parity data (S 17 ). The first computational engine generates the first original data and provides it to the first storage controller (S 18 ). Since the transmission of the original data and the restoration of the original data through an XOR computation of the computational engine are the same as those described with reference to  FIGS.  7  to  13   , a repeated description thereof will omitted below. 
     The first storage controller transmits the received first original data to the host (S 19 ). A decoding operation of the first storage device and the second storage device that corresponds to a read command of the host and a read request of the host is completed. 
       FIG.  20    illustrates a data center that incorporates a storage device according to some embodiments. 
     Referring to  FIG.  20   , in some embodiments, a data center  3000  is a facility that gathers various types of data and provides services, and may also be called a data storage center. The data center  3000  is a system for search engine and database operations, and is a computing system used by corporations such as banks or government agencies. The data center  3000  includes application servers  3100  to  3100   n  and storage servers  3200  to  3200   m . The number of application servers  3100  to  3100   n  and the number of storage servers  3200  to  3200   m  may be variously selected depending on embodiments, and the number of application servers  3100  to  3100   n  and the number of storage servers  3200  to  3200   m  may differ from each other. 
     The application server  3100  or the storage server  3200  includes at least one of processors  3110  and  3210  and memories  3120  and  3220 . The storage server  3200  will be described as an example. The processor  3210  controls the overall operation of the storage server  3200 , and accesses the memory  3220  to execute command and/or data loaded into the memory  3220 . The memory  3220  may be a DDR SDRAM (double data rate synchronous DRAM), an HBM (high bandwidth memory), an HMC (hybrid memory cube), a DIMM (dual in-line memory module), an Optane DIMM or a NVMDIMM (non-volatile DIMM). According to an embodiment, the number of processors  3210  and the number of memories  3220  in the storage server  3200  may be variously selected. 
     In an embodiment, the processor  3210  and the memory  3220  form a processor-memory pair. In an embodiment, the number of processors  3210  and memories  3220  may differ from each other. The processor  3210  may include a single core processor or a multi-core processor. 
     The aforementioned description of the storage server  3200  also applies to the application server  3100 . According to an embodiment, the application server  3100  does not include a storage device  3150 . The storage server  3200  includes at least one or more storage devices  3250 . The number of storage devices  3250  in the storage server  3200  may be variously selected depending on an embodiment. 
     The application servers  3100  to  3100   n  and the storage servers  3200  to  3200   m  communicate with each other through a network  3300 . The network  3300  may be implemented using a FC (fibre channel) or an Ethernet, etc. FC is a medium used for a relatively high-speed data transfer, and may use an optical switch that provides high performance/high availability. The storage servers  3200  to  3200   m  may be provided as a file storage, a block storage or an object storage, depending on the access type of the network  3300 . 
     In an embodiment, the network  3300  is a storage-only network such as a SAN (storage area network). For example, a SAN may be an FC-SAN that uses an FC network and is implemented according to FCP (FC protocol). For example, a SAN may be an IP-SAN that uses a TCP/IP network and is implemented according to an iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In an embodiment, the network  3300  is a general network such as a TCP/IP network. For example, the network  3300  may be implemented according to a protocol such as an FCoE (FC over Ethernet), an NAS (network attached storage), or an NVMe-oF (NVMe over fabrics). 
     Hereinafter, the application server  3100  and the storage server  3200  will be described. Descriptions of the application server  3100  also apply to another application server  3100   n , and descriptions of the storage server  3200  also apply to another storage server  3200   m.    
     The application server  3100  stores the data requested by a user or client to store in one of the storage servers  3200  to  3200   m  through the network  3300 . Further, the application server  3100  acquires read data requested by the user or client from one of the storage servers  3200  to  3200   m  through the network  3300 . For example, the application server  3100  may be implemented as a Web server, a DBMS (Database Management System), etc. 
     The application server  3100  accesses a memory  3120   n  or a storage device  3150   n  in another application server  3100   n  through the network  3300 , or accesses the memories  3220  to  3220   m  or the storage devices  3250  to  3250   m  in the storage servers  3200  to  3200   m  through the network  3300 . Accordingly, the application server  3100  can perform various operations on the data stored in the application servers  3100  to  3100   n  and/or the storage servers  3200  to  3200   m . For example, the application server  3100  can execute commands for moving or copying the data between the application servers  3100  to  3100   n  and/or the storage servers  3200  to  3200   m . The data may be moved from the storage devices  3250  to  3250   m  of the storage servers  3200  to  3200   m  via the memories  3220  to  3220   m  of the storage servers  3200  to  3200   m , or may be directly moved to the memories  3120  to  3120   n  of the application servers  3100  to  3100   n . Data which moves through the network  3300  may be encrypted for security and privacy. 
     The storage server  3200  will be described as example. An interface  3254  provides a physical connection between the processor  3210  and a controller  3251 , and a physical connection between a NIC  3240  and the controller  3251 . For example, the interface  3254  can be implemented as a DAS (Direct Attached Storage) in which the storage device  3250  is directly connected with a dedicated cable. Further, for example, the interface  3254  may be implemented as one of various interface types, such as an ATA (Advanced Technology Attachment), a SATA (Serial ATA), an e-SATA (external SATA), a SCSI (Small Computer Small Interface), a SAS (Serial Attached SCSI), a PCI (Peripheral Component Interconnection), a PCIe (PCI express), a NVMe (NVM express), an IEEE 1394, a USB (universal serial bus), an SD (secure digital) card, a MMC (multi-media card), an eMMC (embedded multi-media card), a UFS (Universal Flash Storage), an eUFS (embedded Universal Flash Storage), and/or a CF (compact flash) card interface. 
     The storage server  3200  further includes a switch  3230  and a NIC  3240 . The switch  3230  can selectively connect the processor  3210  and the storage device  3250  or can selectively connect the NIC  3240  and the storage device  3250 , according to the control of the processor  3210 . 
     In an embodiment, the NIC  3240  includes one of a network interface card or a network adapter, etc. The NIC  3240  is connected to the network  3300  by at least one of a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC  3240  includes an internal memory, a DSP, a host bus interface, etc., and is connected to the processor  3210  and/or the switch  3230 , etc., through the host bus interface. The host bus interface may also be implemented as one of the interface examples  3254  described above. In an embodiment, the NIC  3240  is also integrated with at least one of the processor  3210 , the switch  3230 , and the storage device  3250 . 
     In an embodiment, a switch  3130  and a NIC  3140  of the application server  3100  may be implemented similarly as the switch  3230  and the NIC  3240  of the storage server  3200 . 
     The processor of the storage serves  3200  to  3200   m  or the application servers  3100  to  3100   n  transmits commands to the storage devices  3150  to  3150   n  and  3250  to  3250   m  or the memories  3120  to  3120   n  and  3220  to  3220   m  to program and/or read the data. The data is error-corrected through an ECC (Error Correction Code) engine. The data is subjected to data bus inversion (DBI) or data masking (DM) process, and may include CRC (Cyclic Redundancy Code) information. The data may be encrypted for security and privacy. 
     The storage devices  3150  to  3150   m  and  3250  to  3250   m  transmit the control signals and command/address signals to the NAND flash memory devices  3252  to  3252   m  in response to read commands received from the processor. Accordingly, when data is read from the NAND flash memory devices  3252  to  3252   m , the RE (Read Enable) signal is input as a data output control signal, and serves to output the data to the DQ bus. A DQS (Data Strobe) is generated using the RE signal. Commands and address signals are latched to the page buffer depending on a rising edge or a falling edge of a WE (Write Enable) signal. 
     The controller  3251  generally control the operation of the storage device  3250 . In an embodiment, the controller  3251  includes a SRAM (Static Random Access Memory). The controller  3251  writes data to the NAND flash  3252  in response to a write command, or reads the data from the NAND flash  3252  in response to a read command. For example, the write command and/or the read command is provided from the processor  3210  in the storage server  3200 , a processor  3210   m  in another storage server  3200   m  or the processors  3110  and  3110   n  in the application servers  3100  and  3100   n . A DRAM  3253  temporarily stores or buffers the data to be written to the NAND flash  3252  or the data read from the NAND flash  3252 . In addition, the DRAM  3253  can store metadata. Metadata is user data or data generated by the controller  3251  to manage the NAND flash  3252 . The storage device  3250  may include an SE (Secure Element) for security and privacy. 
     In some embodiments, the above-mentioned storage device is used as the storage device  3250  of the storage server  3200  to the storage device  3250   m  of the storage server  3200   m.    
     Although embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that embodiments of the present disclosure can be manufactured in various forms without being limited to the above-described embodiments and can be embodied in other specific forms without departing from the spirit and essential characteristics of the specification. Thus, the above embodiments are to be considered in all respects as illustrative and not restrictive.