Patent Publication Number: US-7594058-B2

Title: Chipset supporting a peripheral component interconnection express (PCI-E) architecture

Description:
BACKGROUND OF THE INVENTION 
   (1) Field of the Invention 
   The present invention relates in general to the field of computers, and more particularly to a computing system and a method for fast accessing the peer-to-peer cycles in Peripheral Component Interconnection Express (PCI-Express). 
   (2) Description of the Prior Art 
   A computer, or a computing system, is a type of data processing system. Examples of the computer include a server, a workstation, a desktop computer, a notebook computer, a laptop computer, and a hand-held device. Typically, a computer system includes of a microprocessor and memory. 
   The computing system may also include peripheral devices, such as a keyboard, a mouse and disk drives that connect to the computer via input/output (I/O) ports. The I/O ports allow the peripheral devices to communicate with the processor through a bus such as peripheral component interconnection (PCI) bus. In general, the bus can be either a parallel or a serial interface for connecting the peripheral devices to the computer system. 
   As consumers demand faster data processing speed and performance, some innovative devices have exceeded the capabilities of current bus architectures such as the conventional PCI bus. The innovative devices include high performance graphics cards, high speed memory, high speed microprocessors, high bandwidth networking, and other high speed devices. These innovative devices have created a need for a high performance and greater bandwidth interconnections. In order to meet this need, a new interconnection architecture, commonly referred to as PCI Express (or PCI-E) architecture, has been developed to provide the high speed interconnection and peer-to-peer access capability. 
   PCI-Express is a general purpose input/output (I/O) serial interconnection that provides a high performance interconnection for attaching devices such as high performance graphic cards, universal serial bus (USB) ports, networking and other such devices. Because the PCI Express architecture may connect to several different types of devices, the architecture provides a standard for communications in order to consolidate these devices on a single interconnection. 
     FIG. 1  is a block diagram of a prior computing system  10  employing the PCI-Express architecture. The computing system  10  includes a microprocessor  12 , a chipset  14  and a plurality of PCI-E ports  16 . The chipset  14  includes a port arbiter  141  and a Downstream Address Range Decoding logic (DARD logic for short)  143 . No matter “onboard access” or “peer-to-peer access” of the prior art on  FIG. 1 , the upstream requests from the PCI-E ports  16  are sent to microprocessor  12 . Said “onboard access” means an access is processed by the microprocessor  12 ; and said “peer-to-peer access” means an access between two PCI-E ports  16 , which needs no process from microprocessor  12 . 
   The peer-to-peer access doesn&#39;t need any process directly from microprocessor  12 ; furthermore, the chipset  14  doesn&#39;t decode neither the onboard address range nor PCI-E root port memory range for upstream requests. The upstream requests of peer-to-peer access are sent to microprocessor  12  by the port arbiter  141 , then microprocessor  12  redirects the requests and issues the corresponding downstream cycles to the DARD logic  143 , and then to the designated PCI-E port  16 . As a result, the long peer-to-peer access path, PCI-E port  16 →chipset  14 →microprocessor  12  →chipset  14 →another PCI-E port  16 , will induce long access latency and thus make some isochronous applications, such as dual-engine graphic card, infeasible. 
     FIG. 2  is a block diagram of another prior computing system  20  employing PCI-Express architecture. The computing system  20  includes a microprocessor  22 , a chipset  24  and a plurality of PCI-E ports  26 . The chipset  24  includes a port arbiter  241 , a DARD logic  243 , a Upstream Onboard Range Decoding logic (UORD logic for short)  245  and a downstream arbiter  247 . In the design, the computing system  20  uses the UORD logic  245  to distinguish the onboard access from the peer-to-peer access. The peer-to-peer access will be arbitrated to the downstream arbiter  247  and then sent to a specified device (of the specified PCI-E port  16 ) according to the decoding result of the device range of DARD logic  243 . 
   The advantage of this design compared to the previous scheme shown on  FIG. 1  is that the peer-to-peer access path is shortened. As shown on  FIG. 2 , the peer-to-peer access path is not routed through the microprocessor  22 . 
   However, the peer-to-peer access scheme is mainly designed for legacy device, such as PCI  1  access PCI  2 . Therefore, the data buffer size and access length are usually small and limited, which increase access latency and may not meet the requirements of some graphic applications, such as dual-engine graphic card that requires isochronous access. 
   Besides, two address decoding logics, upstream onboard range decoding logic  245  and downstream address range decoding logic  243 , within the peer-to-peer access path will also worse the access latency. 
   SUMMARY OF THE INVENTION 
   In view of the foregoing drawbacks of the related prior arts, a more efficient computing system employing the PCI-E architecture is therefore needed. 
   One objective of the present invention is to solve the problem of long data access path length of peer-to-peer cycle in PCI-E architecture. 
   Another objective of the present invention is to solve the problem of data access latency of peer-to-peer cycle in PCI-E architecture. 
   The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port arbiter, a first URD (Upstream Range Decoding) logic, a microprocessor, a DARD (Downstream Address Range Decoding) logic and a device arbiter. 
   The first port arbiter receives a data from the first PCI-E port. The first URD logic is coupled with the first port arbiter. The first URD logic comprises an onboard range table and a PCI-E device range table for detecting the data belonging to an onboard access or a peer-to-peer access. First of all, the microprocessor receives and processes the data from the first URD logic for said onboard access. Next, the DARD logic receives the data from the microprocessor. Then, the DARD logic decodes a device range of a downstream request of the data. Finally, the device arbiter along with the DARD logic and the first URD logic sends the data to one of the PCI-E port. 
   According to the present invention, the path length of the peer-to-peer cycle between PCI-E ports is shortened, and the data buffer size is enlarged. As a result, some isochronous applications such as dual-engine PCI-E graphic card is able to transfer the data more efficiently according to the present computing system. 
   These objectives of the present invention will undoubtedly become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments which will be illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will now be explained with reference to the preferred embodiments illustrated in the following drawings: 
       FIG. 1  is the block diagram of a prior computing system employing PCI-Express architecture. 
       FIG. 2  is the block diagram of another prior computing system employing PCI-Express architecture. 
       FIG. 3  is the block diagram of one embodiment of the present computing system. 
       FIG. 4  is the block diagram of another embodiment of the present computing system. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Please refer to  FIG. 3 , which is the block diagram of one embodiment of the present computing system  30 . The computing system  30  employs the peripheral component interconnection Express (PCI-E) architecture which includes at least one PCI-E port  36 , a port arbiter  341 , a URD (Upstream Range Decoding) logic  345 , a microprocessor  32 , a downstream arbiter  347 , a DARD (Downstream Address Range Decoding) logic  343  and a device arbiter  349 . The port arbiter  341 , The first URD logic  345   a , the downstream arbiter  347 , the DARD logic  343  and the device arbiter  349  may belong to the chipset  34  of the computing system  30 . 
   The PCI-E port  36  is the general purpose input/output (I/O) serial interconnections that provide a high performance interconnection for attached devices such as high performance graphics cards, universal serial bus (USB) ports, networking and other such devices. 
   The port-arbiter  341 , receiving a data from PCI-E port  36 , is a device that ensures that only one port arbiter  341  is allowed to initiate data transfer at a given moment. That is a common switching device. 
   The URD logic  345  is coupled with the port-arbiter  341  for detecting the data of an onboard access, a peer-to-peer access or the other access for subsequent dispatch. The URD logic  345  comprises an onboard range table and a PCI-E device range table for detecting the data of the onboard access or the peer-to-peer access. The upstream request of the data is decoded by the URD logic  341 . If the decoded range hits the onboard range table, the data will be referred to the onboard access, in which the data is sent to the microprocessor  32 . In the situation that the decoded range does not hit the onboard range table but hits the PCI-E device range table, the data is referred to the peer-to-peer access. In the peer-to-peer access situation, the data is directly sent to another PCI-E port  36 , which is different from the original PCI-E port  26  from that the data comes through the device arbiter  349 . The device arbiter  349  is coupled with both the DARD logic  343  and the URD logic  345 . 
   As to the other access, on which the decoded range of the upstream request hits neither the onboard range table nor the PCI-E range table, the data is dispatched to the DARD logic  343  through the downstream arbiter  347 . In other words, “the other access” in the present invention means the traditional peer-to-peer access. 
   The microprocessor  32  receives and processes the data from the URD logic  345  for the onboard access. The processed data will be arbitrated with following downstream cycle toward a device specified by the microprocessor  32 . The DARD logic  343  receives the data from the microprocessor  32 , wherein the DARD logic  343  decodes a device range of a downstream request of the data, so as to dispatch the data to the specified device. 
   In one embodiment of the present invention, the data received by the DARD logic  343  from the microprocessor  32  is routed through the downstream arbiter  347 , which arbitrates the data of the onboard access (from the microprocessor  32 ) or the other access (from the URD logic  345 ). 
   To shorten the peer-to-peer access latency as much as possible, the device arbitration is executed before the downstream requests the specified PCI-E port  36 . The device arbiter  349  receives the data from the DARD logic  343 , which is the downstream cycle of the onboard access or the other access, or the data from the URD logic  345  of the peer-to-peer access, and dispatches the data to one of the plurality of PCI-E ports  36 . 
   For some isochronous applications, such as dual-engine graphic card, predetermined data FIFO (first in first out) may be applied to the peer-to-peer access. 
   As the mentioned peer-to-peer access of the present invention (one of PCI-E ports  36 →the port arbiter  341 →the URD logic  345 →the device arbiter  349 →another of PCI-E ports  36 ), the present invention has provided a dedicated path for the PCI-E peer-to-peer cycle in order to improve the latency of prior arts. 
   In the prior art described with  FIG. 1 , the latency is caused by the prior peer-to-peer access passing through the microprocessor  12 . 
   In the prior art described with  FIG. 2 , the latency is caused by two address decoding logics, upstream onboard range decoding logic  245  and downstream address range decoding logic  243 , within the prior peer-to-peer access path. Besides the long access length, the latency of the prior art of  FIG. 2  is also caused by the small and limited data buffer size. 
   Obviously, in the present invention, the dedicated path for the peer-to-peer access provides a much shorter access length than prior arts. The data of the peer-to-peer access is distinguishable in the URD logic  345  and is dispatched to the designated PCI-E port  36  directly. Compared to the prior art of  FIG. 1 , the present peer-to-peer access has a shorter access length and does not pass through the microprocessor  32 . Compared to the prior art of  FIG. 2 , the present peer-to-peer access only passes through one address decoding logic—the URD logic  345 , and employs adequate FIFO size for isochronous applications. Hence, not only the access length is shortened in the present invention, but also the prior drawback of small and limited buffer size is improved. 
   Please refer to  FIG. 4 , which is a block diagram of another embodiment of the present computing system  40  and employs the peripheral component interconnection Express (PCI-E) architecture. The computing system  40  includes at least one first PCI-E port  46   a , at least one second PCI-E port  46   b , a first port arbiter  441   a , a second port arbiter  441   b , a first URD logic  445   a , a second URD logic  445   b , a upstream arbiter  448 , a microprocessor  42 , a downstream arbiter  447 , a DARD logic  443  and a device arbiter  449 . The first port arbiter  441   a , the second port arbiter  441   b , the first URD logic  445   a , the second URD logic  445   b , the upstream arbiter  448 , the downstream arbiter  447 , the DARD logic  443  and the device arbiter  449  may belong to the chipset  44  of the computing system  40 . 
   As described previously in the embodiment on  FIG. 3 , the dedicated path for present peer-to-peer access may apply adequate FIFO size to isochronous applications. But in practice, not every first PCI-E port  46   a  needs this bandwidth and access speed. Considering to cost and efficiency, another embodiment as shown in  FIG. 4  is provided. In this embodiment, the first PCI-E port  46   a  are designed for said “peer-to-peer access”, “onboard access” and “the other access”. The first PCI-E port  46   a , the first port arbiter  441   a  and the first URD logic  445   a  have the same functions as the embodiment on  FIG. 3 . Hence, data transferred to the first PCI-E port  46   a  is able to be isochronous and is treated with highest priority. Therefore, the first PCI-E port  46   a  can meet the requirements of high speed devices such as dual-engine graphic card. 
   At least one second PCI-E port  46   b , which is also the general purpose input/output (I/O) serial interconnections, are designed for said “onboard access” and “the other access” only. In other words, the second PCI-E port  46   b  is a interconnection for devices that need smaller buffer size or less speed. 
   The second port arbiter  441   b , receiving a data from the second PCI-E port  46   b , is a switching device for these second PCI-E port  46   b . The second URD logic  445   b  is coupled with the second port-arbiter  441   b  for detecting the data of the onboard access or the other access for subsequent dispatch. The second URD logic  445   b  includes an onboard range table for detecting the data of the onboard access or the other access. The upstream request of the data from the second PCI-E port  46   b  is decoded by the second URD logic  445   b . If the decoded range hits the onboard range table, the data will be referred to the onboard access, in which the data is dispatched to the microprocessor  42 . If the decoded range does not hit the onboard range table, the data will be referred to the “the other access”, in which the data is dispatched to the DARD logic  443  through the downstream arbiter  447 . The DARD logic  443  is coupled with a plurality of second PCI-E ports  46   b . The down stream cycle of said the other access from the second PCI-E ports  46   b  is routed toward the second PCI-E port  46   b.    
   Because the data of the onboard access from the first PCI-E port  46   a  is also dispatched to the microprocessor  42 , the upstream arbiter  448  is therefore needed. The upstream arbiter  448  coordinates the microprocessor  42 , the first URD logic  441   a  and the second URD logic  441   b  for arbitrating the data to the microprocessor  42  to maintain data order as well. 
   In this embodiment, the computing system  40  has a dedicated path for the peer-to-peer access to the first PCI-E port  46   a . The second PCI-E port  46   b  is a port without peer-to-peer support feature. In practice, the chipset  44  needs to separate the PCI-E port arbitrations to reduce the redundant address decoding logic and cycle dispatch logic. Therefore, the first port arbiter  441   a  and the second port arbiter  441   b  are separated; and the first URD logic  445   a  and the second URD logic  445   b  are also separated. In this architecture, devices that needs high data transfer speed, large bandwidth and buffer size are satisfied with the first PCI-E port  46   a . The second PCI-E port  46   b  provide interconnections for other devices that have general PCI-E interface. 
   According to the present invention, the path length of the PCI-E port peer-to-peer cycle is shortened, and the data buffer size is enlarged. As a result, some isochronous applications such as dual-engine PCI-E graphic card are able to get more data transfer efficiency according to the present computing system  30  and  40 . In dual-engine PCI-E graphic card, each graphic engine is responsible for calculating half or interleaved frame data and then transfers the calculated frame data through PCI-E peer-to-peer request. Such application can use the present first PCI-E ports to get sufficient data transfer efficiency and priority. The problems of access latency and long access length are both solved in the present invention. 
   While the present invention has been particularly shown and described with reference to the preferred embodiments, it can be easily understood by those skilled in the art that various changes on appearances or details may be made without departing from the spirit and scope of the present invention.