Patent Publication Number: US-11652151-B2

Title: Semiconductor device structure with fine conductive contact and method for preparing the same

Description:
TECHNICAL FIELD 
     The present disclosure relates to a semiconductor device structure and a method for preparing the same, and more particularly, to a semiconductor device structure with a fine conductive contact and a method for preparing the same. 
     DISCUSSION OF THE BACKGROUND 
     Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while providing greater functionality and including greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, various types and dimensions of semiconductor devices providing different functionalities are integrated and packaged into a single module. Furthermore, numerous manufacturing operations are implemented for integration of various types of semiconductor devices. 
     However, the manufacturing and integration of semiconductor devices involve many complicated steps and operations. Integration in semiconductor devices becomes increasingly complicated. An increase in complexity of manufacturing and integration of the semiconductor device may cause deficiencies. Accordingly, there is a continuous need to improve the manufacturing process of semiconductor devices so that the problems can be addressed. 
     This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure. 
     SUMMARY 
     In one embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a first conductive contact penetrating through the dielectric layer. The first conductive contact includes a first metal filling layer and a first metal silicide structure surrounding the first metal filling layer. The semiconductor device structure also includes a second conductive contact penetrating through the dielectric layer. The second conductive contact includes a second metal filling layer and a second metal silicide structure surrounding the second metal filling layer, and a first width of the first conductive contact is different from a second width of the second conductive contact. 
     In some embodiments, the first metal filling layer is separated from the dielectric layer by the first metal silicide structure, and the second metal filling layer is separated from the dielectric layer by the second metal silicide structure. In some embodiments, the first metal filling layer is separated from the semiconductor substrate by the first metal silicide structure, and the second metal filling layer is separated from the semiconductor substrate by the second metal silicide structure. In some embodiments, a material of the first metal silicide structure is the same as a material of the second metal silicide structure. In some embodiments, a top surface of the first metal silicide structure is level with a top surface of the first metal filling layer, and a top surface of the second metal silicide structure is level with a top surface of the second metal filling layer. In some embodiments, the first metal silicide structure and the second metal silicide structure each comprise multiple sub-layers. 
     In another embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a conductive contact penetrating through the dielectric layer. The semiconductor device structure also includes a metal oxide layer separating the conductive contact from the dielectric layer. The conductive contact and the metal oxide layer include a same metal. 
     In some embodiments, the metal oxide layer is in direct contact with the conductive contact. In some embodiments, a bottom surface of the metal oxide layer is level with a bottom surface of the conductive contact. In some embodiments, a top surface of the metal oxide layer is level with a top surface of the conductive contact. 
     In one embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure comprises a dielectric layer disposed over a semiconductor substrate; a first conductive contact penetrating through the dielectric layer, wherein the first conductive contact comprises a first metal filling layer and a first metal silicide structure surrounding the first metal filling layer; a second conductive contact penetrating through the dielectric layer, wherein the second conductive contact comprises a second metal filling layer and a second metal silicide structure surrounding the second metal filling layer, and wherein a first width of the first conductive contact is different from a second width of the second conductive contact; a first metal oxide layer separating the first conductive contact from the dielectric layer, wherein the first conductive contact and the first metal oxide layer comprise a same metal; and a second metal oxide layer separating the second conductive contact from the dielectric layer, wherein the second conductive contact and the second metal oxide layer comprise a same metal. 
     In some embodiments, the first metal filling layer is separated from the dielectric layer by the first metal silicide structure, and the second metal filling layer is separated from the dielectric layer by the second metal silicide structure. 
     In some embodiments, the first metal filling layer is separated from the semiconductor substrate by the first metal silicide structure, and the second metal filling layer is separated from the semiconductor substrate by the second metal silicide structure. 
     In some embodiments, a material of the first metal silicide structure is the same as a material of the second metal silicide structure. 
     In some embodiments, a top surface of the first metal silicide structure is level with a top surface of the first metal filling layer, and a top surface of the second metal silicide structure is level with a top surface of the second metal filling layer. 
     In some embodiments, the first metal silicide structure and the second metal silicide structure each comprise multiple sub-layers. 
     In another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate, and forming a first opening and a second opening penetrating through the dielectric layer. A first width of the first opening is different from a second width of the second opening. The method also includes forming a first metal silicide structure and a second metal silicide structure in the first opening and the second opening, respectively. The forming the first metal silicide structure and the second metal silicide structure includes forming a first silicon-containing layer and a second silicon-containing layer lining the first opening and the second opening, respectively, and transforming the first silicon-containing layer and the second silicon-containing layer into a first metal silicide layer and a second metal silicide layer, respectively. The method further includes filling a remaining portion of the first opening with a first metal filling layer and filling a remaining portion of the second opening with a second metal filling layer. 
     In some embodiments, the first silicon-containing layer and the second silicon-containing layer are formed by soaking the first opening and the second opening in silane. In some embodiments, a bottom surface and sidewalls of the first opening are covered by the first silicon-containing layer, and a bottom surface and sidewalls of the second opening are covered by the second silicon-containing layer. In some embodiments, the forming the first metal silicide structure and the second metal silicide structure further includes forming a third silicon-containing layer and a fourth silicon-containing layer over the first metal silicide layer and the second metal silicide layer, respectively, and transforming the third silicon-containing layer and the fourth silicon-containing layer into a third metal silicide layer and a fourth metal silicide layer, respectively. In some embodiments, the first metal filling layer is separated from the dielectric layer by the first metal silicide structure, and the second metal filling layer is separated from the dielectric layer by the second metal silicide structure. 
     In yet another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method includes forming a sacrificial layer over a semiconductor substrate, and forming an opening penetrating through the sacrificial layer. The method also includes filling the opening with a metal pillar, and removing the sacrificial layer after the metal pillar is formed. The method further includes reducing a width of the metal pillar after the sacrificial layer is removed. 
     In some embodiments, the width of the metal pillar is reduced by performing an oxidation process, such that a portion of the metal pillar is transformed into a metal oxide layer. In some embodiments, the metal oxide layer covers a top surface and sidewalls of a remaining portion of the metal pillar. In some embodiments, the method further includes forming a dielectric layer covering the metal oxide layer, and performing a planarization process to expose the remaining portion of the metal pillar. In some embodiments, the method further includes removing the metal oxide layer to expose the remaining portion of the metal pillar, and forming a dielectric layer covering the remaining portion of the metal pillar. In addition, the method includes performing a planarization process to expose the remaining portion of the metal pillar. 
     Embodiments of a semiconductor device structure and method for preparing the same are provided in the disclosure. In some embodiments, the semiconductor device structure includes conductive contacts penetrating through a dielectric layer over a semiconductor substrate. Each of the conductive contacts includes a metal filling layer and a metal silicide structure surrounding the metal filling layer. In some embodiments, the conductive contacts have different widths. Since the conductive contacts with different widths may be formed in similar processing steps using similar materials, the method for preparing the semiconductor device structure is simple and the fabrication cost and time of the semiconductor device structure can be reduced. 
     The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a cross-sectional view illustrating a semiconductor device structure, in accordance with some embodiments. 
         FIG.  2    is a cross-sectional view illustrating a semiconductor device structure, in accordance with some embodiments. 
         FIG.  3    is a cross-sectional view illustrating a semiconductor device structure, in accordance with some embodiments. 
         FIG.  4    is a flow diagram illustrating a method for preparing a semiconductor device structure, in accordance with some embodiments. 
         FIG.  5    is a flow diagram illustrating a method for preparing a semiconductor device structure, in accordance with some embodiments. 
         FIG.  6    is a cross-sectional view illustrating an intermediate stage of forming a dielectric layer over a semiconductor substrate during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  7    is a cross-sectional view illustrating an intermediate stage of forming a patterned mask over the dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  8    is a cross-sectional view illustrating an intermediate stage of etching the dielectric layer to form openings during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  9    is a cross-sectional view illustrating an intermediate stage of removing the patterned mask during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  10    is a cross-sectional view illustrating an intermediate stage of forming silicon-containing layers lining the openings during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  11    is a cross-sectional view illustrating an intermediate stage of transforming the silicon-containing layers into metal silicide layers during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  12    is a cross-sectional view illustrating an intermediate stage of repeating the step of forming silicon-containing layers during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  13    is a cross-sectional view illustrating an intermediate stage of repeating the step of transforming the silicon-containing layers into metal silicide layers during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  14    is a cross-sectional view illustrating an intermediate stage of forming metal silicide structures during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  15    is a cross-sectional view illustrating an intermediate stage of forming openings in a sacrificial layer over a semiconductor substrate during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  16    is a cross-sectional view illustrating an intermediate stage of filling the openings with metal pillars during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  17    is a cross-sectional view illustrating an intermediate stage of removing the sacrificial layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  18    is a cross-sectional view illustrating an intermediate stage of performing an oxidation process to transform portions of the metal pillars into metal oxide layers during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  19    is a cross-sectional view illustrating an intermediate stage of forming a dielectric layer over the metal oxide layers during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG.  20    is a cross-sectional view illustrating an intermediate stage of removing the metal oxide layers during the formation of the semiconductor device structure, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
       FIG.  1    is a cross-sectional view illustrating a semiconductor device structure  100 , in accordance with some embodiments. In some embodiments, the semiconductor device structure  100  includes a dielectric layer  103  disposed over a semiconductor substrate  101 , and conductive contacts  149   a  and  149   b  disposed in the dielectric layer  103 . In some embodiments, the conductive contacts  149   a  and  149   b  penetrate through the dielectric layer  103  to contact the semiconductor substrate  101 . 
     In some embodiments, the conductive contact  149   a  includes a metal filling layer  147   a  and a metal silicide structure  145   a  surrounding the metal filling layer  147   a , and the conductive contact  149   b  includes a metal filling layer  147   b  and a metal silicide structure  145   b  surrounding the metal filling layer  147   b . In some embodiments, the metal filling layer  147   a  is separated from the dielectric layer  103  and the semiconductor substrate  101  by the metal silicide structure  145   a , and the metal filling layer  147   b  is separated from the dielectric layer  103  and the semiconductor substrate  101  by the metal silicide structure  145   b . In some embodiments, the metal filling layer  147   a  is in direct contact with the metal silicide structure  145   a , and the metal filling layer  147   b  is in direct contact with the metal silicide structure  145   b.    
     Moreover, in some embodiments, the top surface T 1  of the metal silicide structure  145   a  of the conductive contact  149   a  is substantially level with the top surface T 2  of the metal filling layer  147   a  of the conductive contact  149   a , and the top surface T 3  of the metal silicide structure  145   b  of the conductive contact  149   b  is substantially level with the top surface T 4  of the metal filling layer  147   b  of the conductive contact  149   b . Within the context of this disclosure, the word “substantially” means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%. In some embodiments, the conductive contact  149   a  has a width W 1 , the conductive contact  149   b  has a width W 2 , and the width W 2  is greater than the width W 1 . 
       FIG.  2    is a cross-sectional view illustrating a semiconductor device structure  200   a , in accordance with some embodiments. In some embodiments, the semiconductor device structure  200   a  includes a dielectric layer  217  disposed over a semiconductor substrate  201 , and conductive contacts  213 ′ disposed in the dielectric layer  217 . Although  FIG.  2    shows that the semiconductor device structure  200   a  includes two conductive contacts  213 ′, the present disclosure is not limited thereto. In some embodiments, the semiconductor device structure  200   a  can have more, or fewer conductive contacts  213 ′, depend on the functional requirements of the semiconductor device structure  200   a.    
     Moreover, in some embodiments, the semiconductor device structure  200   a  also includes metal oxide layers  215  disposed between the conductive contacts  213 ′ and the dielectric layer  217 . In some embodiments, the conductive contacts  213 ′ are separated from the dielectric layer  217  by the metal oxide layers  215 . In some embodiments, the conductive contacts  213 ′ and the metal oxide layers  215  include the same metal. 
     In some embodiments, the top surfaces T 5  of the metal oxide layers  215  are substantially level with the top surfaces T 6  of the conductive contacts  213 ′. In some embodiments, the bottom surfaces B 1  of the metal oxide layers  215  are substantially level with the bottom surfaces B 2  of the conductive contacts  213 ′. In some embodiments, conductive contacts  213 ′ and the metal oxide layers  215  are in direct contact with the semiconductor substrate  201 . 
     In some embodiments of the present disclosure, the semiconductor device structure  200   a  (shown in  FIG.  1   ) may also include metal oxide layers (shown in  FIG.  2   ) disposed between the conductive contacts and the dielectric layer, which is not repeated herein for clarity. 
       FIG.  3    is a cross-sectional view illustrating a semiconductor device structure  200   b , in accordance with some embodiments. The semiconductor device structure  200   b  in  FIG.  3    is similar to the semiconductor device structure  200   a  in  FIG.  2   . However, in  FIG.  3   , the metal oxide layers  215  are removed such that the conductive contacts  213 ′ are in direct contact with the dielectric layer  217 . 
       FIG.  4    is a flow diagram illustrating a method  10  for forming a semiconductor device structure, such as the semiconductor device structure  100  shown in  FIG.  1   , and the method  10  includes steps S 11 , S 13 , S 15 , S 17 , S 19  and S 21 , in accordance with some embodiments.  FIG.  5    is a flow diagram illustrating a method  30  for forming a semiconductor device structure, such as the semiconductor device structures  200   a  and  200   b  shown in  FIGS.  2  and  3   , and the method  30  includes steps S 31 , S 33 , S 35 , S 37 , S 39 , S 41 , S 43  and S 45 , in accordance with some embodiments. The steps S 11  to S 21  of  FIG.  4    and the steps S 31  to S 45  of  FIG.  5    are elaborated in connection with the following figures. 
       FIGS.  6 - 14    are cross-sectional views illustrating various stages of forming the semiconductor device structure  100  by the method  10  of  FIG.  4    according to various embodiments of the present disclosure. As shown in  FIG.  6   , a semiconductor substrate  101  is provided. The semiconductor substrate  101  may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the semiconductor substrate  101  may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. 
     In some embodiments, the semiconductor substrate  101  includes an epitaxial layer. For example, the semiconductor substrate  101  has an epitaxial layer overlying a bulk semiconductor. In some embodiments, the semiconductor substrate  101  is a semiconductor-on-insulator substrate which may include a substrate, a buried oxide layer over the substrate, and a semiconductor layer over the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. 
     A dielectric layer  103  is formed over the semiconductor substrate  101 , as shown in  FIG.  6    in accordance with some embodiments. The respective step is illustrated as the step S 11  in the method  10  shown in  FIG.  4   . In some embodiments, the dielectric layer  103  is made of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material or another suitable material. The dielectric layer  103  may be formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin-on coating process, or another suitable method. 
     Subsequently, a patterned mask  105  with openings  110   a  and  110   b  is formed over the dielectric layer  103 , as shown in  FIG.  7    in accordance with some embodiments. In some embodiments, the dielectric layer  103  is exposed by the openings  110   a  and  110   b . In some embodiments, the width W 1  of the opening  110   a  is substantially equal to the width W 1  of the conductive contact  149   a  (see  FIG.  1   ). Hence, the width W 1  of the opening  110   a  and the width W 1  of the conductive contact  149   a  are denoted by the same reference sign. Moreover, the width W 2  of the opening  110   b  is substantially equal to the width W 2  of the conductive contact  149   b  (see  FIG.  1   ). Hence, the width W 2  of the opening  110   b  and the width W 2  of the conductive contact  149   b  are denoted by the same reference sign. In some embodiments, the widths W 2  of the opening  110   b  in the patterned mask  105  is greater than the width W 1  of the opening  110   a  in the patterned mask  105 . 
     Then, an etching process is performed on the dielectric layer  103  using the patterned mask  105  as an etching mask, such that openings  120   a  and  120   b  are formed in the dielectric layer  103 , as shown in  FIG.  8    in accordance with some embodiments. The etching process may be a wet etching process, a dry etching process, and a combination thereof. In some embodiments, the width of the opening  120   a  is substantially equal to the width W 1  of the opening  110   a , and the width of the opening  120   b  is substantially equal to the width W 2  of the opening  110   b . Therefore, the width of the opening  120   b  is greater than the width of the opening  120   a . In addition, the openings  120   a  and  120   b  penetrate through the dielectric layer  103 , such that the semiconductor substrate  101  is exposed by the openings  120   a  and  120   b , in accordance with some embodiments. The respective step is illustrated as the step S 13  in the method  10  shown in  FIG.  4   . 
     After the openings  120   a  and  120   b  are formed in the dielectric layer  103 , the patterned mask  105  is removed, as shown in  FIG.  9    in accordance with some embodiments. In some embodiments, the patterned mask  105  is removed by a stripping process, an ashing process, an etching process, or another suitable process. 
     Next, silicon-containing layers  123   a  and  123   b  are formed lining the openings  120   a  and  120   b , respectively, as shown in  FIG.  10    in accordance with some embodiments. The respective step is illustrated as the step S 15  in the method  10  shown in  FIG.  4   . In some embodiments, the silicon containing layer  123   a  covers the sidewalls SW 1  and the bottom surface B 3  of the opening  120   a , and the silicon containing layer  123   b  covers the sidewalls SW 2  and the bottom surface B 4  of the opening  120   b.    
     In some embodiments, the silicon-containing layers  123   a  and  123   b  are formed by soaking the openings  120   a  and  120   b  in at least one silicon-containing precursor, such as silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), dichlorosilane (SiH 2 Cl 2 ), another silicon-containing precursor, or a combination thereof. It should be noted that the openings  120   a  and  120   b  are not fully filled by the silicon-containing layers  123   a  and  123   b , in accordance with some embodiments. 
     Subsequently, the silicon-containing layers  123   a  and  123   b  are transformed into metal silicide layers  125   a  and  125   b , as shown in  FIG.  11    in accordance with some embodiments. The respective step is illustrated as the step S 17  in the method  10  shown in  FIG.  4   . In some embodiments, the silicon-containing layers  123   a  and  123   b  are transformed into metal silicide layers  125   a  and  125   b  by forming a metal material (not shown) over the silicon-containing layers  123   a  and  123   b  and thereafter performing an annealing process to react the metal material with the silicon-containing layers  123   a  and  123   b.    
     In some embodiments, the metal material includes nickel (Ni), titanium (Ti), cobalt (Co), tantalum (Ta), platinum (Pt), ytterbium (Yb), molybdenum (Mo), erbium (Er), or a combination thereof. In some embodiments, the metal silicide layers  125   a  and  125   b  include nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), tantalum silicide (TaSi), or a silicide material of a suitable metal material. 
     In some embodiments, the metal silicide structures  145   a  and  145   b  shown in  FIG.  1    are obtained after the metal silicide layers  125   a  and  125   b  are formed. In these cases, the process may proceed directly from the step S 17  to the step S 21 . In some embodiments, the steps S 15  and S 17  are sequentially repeated to form the metal silicide structures  145   a  and  145   b , as indicated by the directional process arrow S 19 . In these cases, silicon-containing layers  133   a  and  133   b  are formed over the silicide layers  125   a  and  125   b , as shown in  FIG.  12    in accordance with some embodiments. Some processes used to form the silicon-containing layers  133   a  and  133   b  are similar to, or the same as those used to form the silicon-containing layers  123   a  and  123   b , and details thereof are not repeated herein. After the silicon-containing layers  133   a  and  133   b  are formed, the silicon-containing layers  133   a  and  133   b  are transformed into metal silicide layers  135   a  and  135   b , as shown in  FIG.  13    in accordance with some embodiments. Some materials and processes used to form the metal silicide layers  135   a  and  135   b  are similar to, or the same as those used to form the metal silicide layers  125   a  and  125   b , and details thereof are not repeated herein. 
     The steps S 15  and S 17  can be repeated multiple times, depend on the functional requirements of the semiconductor device structure  100 . In other words, each of the metal silicide structures  145   a  and  145   b  may include multiple sub-layers, such as the metal silicide layers  125   a ,  125   b ,  135   a  and  135   b , in accordance with some embodiments. The metal silicide structures  145   a  and  145   b  formed in the openings  120   a  and  120   b  are shown in  FIG.  14    in accordance with some embodiments. It should be noted that the openings  120   a  and  120   b  are not fully filled by the metal silicide structures  145   a  and  145   b , in accordance with some embodiments. 
     Then, the remaining portions of the openings  120   a  and  120   b  are filled with metal filling layers  147   a  and  147   b , respectively, as shown in  FIG.  1    in accordance with some embodiments. The respective step is illustrated as the step S 21  in the method  10  shown in  FIG.  4   . In some embodiments, the metal filling layers  147   a  and  147   b  may be formed simultaneously in the same process steps. For example, the metal filling layers  147   a  and  147   b  may be formed by a deposition process and a subsequent planarization process. The deposition process may include a CVD process, a PVD process, an ALD process, a spin-on coating process, another suitable method, or a combination thereof. The planarization process may include a chemical mechanical polishing (CMP) process. 
     In some embodiments, the metal filling layers  147   a  and  147   b  may be formed separately by different steps. For example, the metal filling layer  147   b  is formed after the metal filling layer  147   a . In addition, the metal filling layers  147   a  and  147   b  are made of a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), in accordance with some embodiments. After the metal filling layers  147   a  and  147   b  are formed, the semiconductor device structure  100  having conductive contacts  149   a  and  149   b  with different widths is obtained. 
       FIGS.  15 - 19    are cross-sectional views illustrating various stages of forming the semiconductor device structure  200   a  by the method  30  of  FIG.  5    according to various embodiments of the present disclosure. As shown in  FIG.  15   , a semiconductor substrate  201 , similar to the semiconductor substrate  101  of the semiconductor device structure  100 , is provided, and a sacrificial layer  203  is formed over the semiconductor substrate  201 , in accordance with some embodiments. In some embodiments, the sacrificial layer  203  has openings  210  exposing the semiconductor substrate  201 . 
     In some embodiments, the sacrificial layer  203  is made of a dielectric material. For example, the sacrificial layer  203  includes silicide oxide, silicide nitride, silicon oxynitride, a low-k dielectric material or another suitable material. The sacrificial layer  203  may be formed by a deposition process, such as a CVD process, a PVD process, an ALD process, a spin-on coating process, or another suitable method. In addition, each of the openings  210  penetrating through the sacrificial layer  203  has a width W 3 . The openings  210  in the sacrificial layer  203  may be formed by an etching process, such as a wet etching process, a dry etching process, and a combination thereof. The respective steps are illustrated as the steps S 31  and S 33  in the method  30  shown in  FIG.  5   . 
     Next, the openings  210  are filled with metal pillars  213 , as shown in  FIG.  16    in accordance with some embodiments. The respective step is illustrated as the step S 35  in the method  30  shown in  FIG.  5   . In some embodiments, the widths of the metal pillars  213  are substantially equal to the widths W 3  of the openings  210 . In some embodiments, the metal pillars  213  include a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof. In some embodiments, the metal pillars  213  are formed by a deposition process and a subsequent planarization process. The deposition process includes a CVD process, a PVD process, an ALD process, a sputtering process, a plating process, another suitable method, or a combination thereof. The planarization process includes a CMP process. 
     After the metal pillars  213  are formed, the sacrificial layer  203  is removed, as shown in  FIG.  17    in accordance with some embodiments. The respective step is illustrated as the step S 37  in the method  30  shown in  FIG.  5   . In some embodiments, the sacrificial layer  203  is removed by an etching process, a stripping process, an ashing process, or another suitable process. After the sacrificial layer  203  is removed, the metal pillars  213  are protruded from the top surface of the semiconductor substrate  201 . 
     Subsequently, the widths of the metal pillars  213  (i.e., the widths W 3 ) are reduced, as shown in  FIG.  18    in accordance with some embodiments. In some embodiments, the widths of the metal pillars  213  are reduced by performing an oxidation process, such that portions of the metal pillars  213  are transformed into metal oxide layers  215 , and the remaining portions of the metal pillars  213 ′ (also referred to as conductive contacts) are obtained. The respective step is illustrated as the step S 39  in the method  30  shown in  FIG.  5   . 
     In some embodiments, the resulting widths W 3 ′ of the remaining portions of the metal pillars  213 ′ are less than the original widths W 3  of the metal pillars  213 . In some embodiments, the outer portions of the metal pillars  213  (i.e., the top portions and the sidewall portions of the metal pillars  213 ) are transformed into the metal oxide layers  215 . As a result, the metal oxide layers  215  are formed over the sidewalls SW 3  and the top surface T 7  of the remaining portions of the metal pillars  213 ′, in accordance with some embodiments. 
     The step S 41  of removing the metal oxide layers  215  is optional. In the embodiments for forming the semiconductor device structure  200   a , the step S 41  is skipped after the metal oxide layers  215  are formed, and a dielectric layer  217  is formed covering the metal oxide layers  215  and the remaining portions of the metal pillars  213 ′, as shown in  FIG.  19    in accordance with some embodiments. The respective step is illustrated as the step S 43  in the method  30  shown in  FIG.  5   . In some embodiments, the dielectric layer  217  is made of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material or another suitable material. The dielectric layer  217  may be formed by a deposition process, such as a CVD process, a PVD process, an ALD process, a spin-on coating process, or another suitable method. 
     Then, a planarization process is performed to remove excess portions of the dielectric layer  217  and the metal oxide layers  215 , such that the remaining portions of the metal pillars  213 ′ are exposed, as shown in  FIG.  2    in accordance with some embodiments. The respective step is illustrated as the step S 45  in the method  30  shown in  FIG.  5   . The planarization process may include a CMP process. After the planarization process is performed, the semiconductor device structure  200   a  is obtained. 
       FIG.  20    is a cross-sectional view illustrating an intermediate stage of forming the semiconductor device structure  200   b  by the method  30  of  FIG.  5    according to various embodiments of the present disclosure. Some processes used to form the semiconductor device structure  200   b  are similar to, or the same as those used to form the semiconductor device structure  200   a , and details thereof are not repeated herein. In some embodiments, the step S 41  of removing the metal oxide layers  215  is performed on the structure of  FIG.  18   , such that the top surface and the sidewalls of the remaining portions of the metal pillars  213 ′ are exposed. Then, the dielectric layer  217  is formed covering the structure of  FIG.  20   , and the planarization process is performed to expose the remaining portions of the metal pillars  213 ′ (i.e., the steps S 43  and S 45 ), as shown in  FIG.  3    in accordance with some embodiments. After the planarization process is performed, the semiconductor device structure  200   b  is obtained. In some embodiments, the sidewalls of the remaining portions of the metal pillars  213 ′ are in direct contact with the dielectric layer  217 . 
     In some embodiments of the present disclosure, the fabrication processes shown in  FIGS.  15 - 19    can also be applied to prepare conductive contacts with different widths in the dielectric layer in a similar way, which is not repeated herein for clarity. 
     Embodiments of the semiconductor device structure  100 ,  200   a  and  200   b  and method for preparing the same are provided in the disclosure. In some embodiments, the semiconductor device structure  100  includes the conductive contacts  149   a  and  149   b  penetrating through the dielectric layer  103  over the semiconductor substrate  101 . The conductive contact  149   a  includes the metal filling layer  147   a  and the metal silicide structure  145   a  surrounding the metal filling layer  147   a , and the conductive contact  149   b  includes the metal filling layer  147   b  and the metal silicide structure  145   b  surrounding the metal filling layer  147   b . In some embodiments, the conductive contacts  149   a  and  149   b  have different widths (e.g., the widths W 1  and W 2  are different). The conductive contacts  149   a  and  149   b  with different widths may be formed in similar processing steps using similar materials. As a result, the method for preparing the semiconductor device structure  100  is simple and the fabrication cost and time of the semiconductor device structure  100  can be reduced. 
     In some embodiments, the semiconductor device structure  200   a  includes the conductive contacts  213 ′ formed in the dielectric layer  217  over the semiconductor substrate  201 . In some embodiments, the semiconductor device structure  200   a  also includes metal oxide layers  215  separating the conductive contacts  213 ′ from the dielectric layer  217 . The conductive contacts  213 ′ are formed by performing a treatment process (e.g., an oxidation process) on the metal pillars  213  to reduce the widths of the metal pillars  213 , and the remaining portions of the metal pillars  213  become the conductive contacts  213 ′. In some embodiments, the metal oxide layers  215  are also formed by the treatment process. As a result, the method for preparing the semiconductor device structure  200   a  is simple and the fabrication cost and time of the semiconductor device structure  200   a  can be reduced. 
     In one embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a first conductive contact penetrating through the dielectric layer. The first conductive contact includes a first metal filling layer and a first metal silicide structure surrounding the first metal filling layer. The semiconductor device structure also includes a second conductive contact penetrating through the dielectric layer. The second conductive contact includes a second metal filling layer and a second metal silicide structure surrounding the second metal filling layer, and a first width of the first conductive contact is different from a second width of the second conductive contact. 
     In another embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a conductive contact penetrating through the dielectric layer. The semiconductor device structure also includes a metal oxide layer separating the conductive contact from the dielectric layer. The conductive contact and the metal oxide layer include a same metal. 
     In another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate, and forming a first opening and a second opening penetrating through the dielectric layer. A first width of the first opening is different from a second width of the second opening. The method also includes forming a first metal silicide structure and a second metal silicide structure in the first opening and the second opening, respectively. The forming the first metal silicide structure and the second metal silicide structure includes forming a first silicon-containing layer and a second silicon-containing layer lining the first opening and the second opening, respectively, and transforming the first silicon-containing layer and the second silicon-containing layer into a first metal silicide layer and a second metal silicide layer, respectively. The method further includes filling a remaining portion of the first opening with a first metal filling layer and filling a remaining portion of the second opening with a second metal filling layer. 
     In yet another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method includes forming a sacrificial layer over a semiconductor substrate, and forming an opening penetrating through the sacrificial layer. The method also includes filling the opening with a metal pillar, and removing the sacrificial layer after the metal pillar is formed. The method further includes reducing a width of the metal pillar after the sacrificial layer is removed. 
     The embodiments of the present disclosure have some advantageous features. In some embodiments, the semiconductor device structure includes conductive contacts with different widths, and each of the conductive contacts includes a metal filling layer and a metal silicide structure surrounding the metal filling layer. The method for preparing the semiconductor device structure having conductive contacts with different widths may be simple and the fabrication cost and time of the semiconductor device structure may be reduced. 
     Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof. 
     Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.