Patent Publication Number: US-2023153125-A1

Title: Technologies for signal conditioning of signals for qubits

Description:
BACKGROUND 
     Quantum computers promise computational abilities not feasible with classical computing. One of many challenges in quantum computing is obtaining high-fidelity measurement of quantum bits (qubits). For spin qubits, one challenge is sending control signals to one spin qubit without affecting another spin qubit. If the resonant frequencies of the spin qubits are too close, a control signal sent to one qubit can affect another. If the resonant frequencies of the spin qubits are too far apart, many physical cables may be required to carry all of the control signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 A- 1 F  illustrate various views of an example quantum compute device, in accordance with one embodiment. 
         FIG.  2    is a simplified block diagram of at least one embodiment of a quantum compute device. 
         FIG.  3    illustrates an example signal generator of quantum/classical interface circuitry of  FIG.  2   . 
         FIG.  4    illustrates an example embodiment of a notch filter of the signal generator of  FIG.  3   . 
         FIG.  5    illustrates a plot showing a filter response for various embodiments of a notch filter. 
         FIG.  6    illustrates a plot showing a signal without a notch filter that can be created by the signal generator of  FIG.  2   . 
         FIG.  7    illustrates a plot showing a signal without a notch filter that can be created by the signal generator of  FIG.  2   . 
         FIG.  8    illustrates a plot showing a signal without a notch filter that can be created by the signal generator of  FIG.  2   . 
         FIG.  9    is a simplified flow diagram of at least one embodiment of a method for determining parameters for the signal generator of  FIG.  3   . 
         FIG.  10    is a top view of a wafer and dies, in accordance with any of the embodiments disclosed herein. 
         FIG.  11    is a cross-sectional side view of an integrated circuit, in accordance with any of the embodiments disclosed herein. 
         FIGS.  12 A- 12 D  are perspective views of example planar, gate-all-around, and stacked gate-all-around transistors. 
         FIG.  13    is a cross-sectional side view of an integrated circuit device assembly, in accordance with any of the embodiments disclosed herein. 
         FIG.  14    is a block diagram of an example electrical device, in accordance with any of the embodiments disclosed herein. 
     
    
    
     DETAILED DESCRIPTION 
     Aspects of the present disclosure may include a signal generator to prepare a pulse sent to qubits. The signal generator includes one or more notch filters to filter out frequencies that may impact qubits other than the target qubit. The illustrative notch filters include a finite impulse response (FIR) filter and an infinite impulse response (IIR) filter, which result in a relatively narrow-band notch filter that does not significantly attenuate nearby frequencies. 
     In the following description, specific details are set forth, but embodiments of the technologies described herein may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring an understanding of this description. Phrases such as “an embodiment,” “various embodiments,” “some embodiments,” and the like may include features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. 
     In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description thereof. The intention is to cover all modifications, equivalents, and alternatives within the scope of the claims. 
     Some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of like objects being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally or spatially, in ranking, or any other manner. “Connected” may indicate elements are in direct physical or electrical contact, and “coupled” may indicate elements co-operate or interact, but they may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. Terms modified by the word “substantially” include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified term. For example, a substrate assembly feature, such as a through width, that is described as having substantially a listed dimension can vary within a few percent of the listed dimension. 
     As used herein, the phrase “communicatively coupled” refers to the ability of a component to send a signal to or receive a signal from another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component can send or receive a signal to another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of components that are communicatively coupled include integrated circuit dies located in the same package that communicate via an embedded bridge in a package substrate and an integrated circuit component attached to a printed circuit board that send signals to or receives signals from other integrated circuit components or electronic devices attached to the printed circuit board. 
     It will be understood that in the examples shown and described further below, the figures may not be drawn to scale and may not include all possible layers and/or circuit components. In addition, it will be understood that although certain figures illustrate transistor designs with source/drain regions, electrodes, etc. having orthogonal (e.g., perpendicular) boundaries, embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within +/- 5 or 10 degrees of orthogonality) due to fabrication methods used to create such devices or for other reasons. 
     As used herein, the phrase “located on” in the context of a first layer or component located on a second layer or component refers to the first layer or component being directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components. 
     As used herein, the term “adjacent” refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y. 
     As used herein, the terms “upper” / “lower” or “above” / “below” may refer to relative locations of an object (e.g., the surfaces described above), especially in light of examples shown in the attached figures, rather than an absolute location of an object. For example, an upper surface of an apparatus may be on an opposite side of the apparatus from a lower surface of the object, and the upper surface may be facing upward generally only when viewed in a particular way. As another example, a first object above a second object may be on or near an “upper” surface of the second object rather than near a “lower” surface of the object, and the first object may be truly above the second object only when the two objects are viewed in a particular way. 
     The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device). 
     References are made to the drawings, which are not necessarily drawn to scale, wherein similar or same numbers may be used to designate the same or similar parts in different figures. The use of similar or same numbers in different figures does not mean all figures including similar or same numbers constitute a single or same embodiment. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. 
     A quantum computer uses quantum-mechanical phenomena such as superposition and entanglement to perform computations, simulations, or other functions. In contrast to digital computers, which store data in one of two definite states (0 or 1), quantum computation uses quantum bits (qubits), which can be in superpositions of states. Qubits may be implemented using physically distinguishable quantum states of elementary particles such as electrons and photons. For example, the polarization of a photon may be used where the two states are vertical polarization and horizontal polarization. Similarly, the spin of an electron may have distinguishable states such as “up spin” and “down spin.” Qubits in quantum mechanical systems can be in a superposition of both states at the same time, a trait that is unique and fundamental to quantum computing. 
     Quantum computing systems execute algorithms containing quantum logic operations performed on qubits. In some cases, the result of the algorithm is not deterministic. The quantum algorithm may be repeated many times in order to determine a statistical distribution of results or in order to have a high likelihood of finding the correct answer. In some cases, a classical algorithm may be used to check if the quantum computer determined the correct result. 
     Qubits have been implemented using a variety of different technologies which are capable of manipulating and reading quantum states. These include but are not limited to quantum dot devices (spin-based and spatial-based), trapped-ion devices, superconducting quantum computers, optical lattices, nuclear magnetic resonance computers, solid-state NMR Kane quantum devices, electrons-on-helium quantum computers, cavity quantum electrodynamics (CQED) devices, molecular magnet computers, and fullerene-based ESR quantum computers, to name a few. Thus, while a quantum dot device is described below in relation to certain embodiments of the invention, the underlying principles of the invention may be employed in combination with any type of quantum computer, including, but not limited to, those listed above. The particular physical implementation used for qubits is not necessarily required for the embodiments of the invention described herein. 
     Quantum dots are small semiconductor particles, typically a few nanometers in size. Because of this small size, quantum dots operate according to the rules of quantum mechanics, having optical and electronic properties which differ from macroscopic entities. Quantum dots are sometimes referred to as “artificial atoms” to connote the fact that a quantum dot is a single object with discrete, bound electronic states, as is the case with atoms or molecules. 
       FIGS.  1 A- 1 F  are various views of a quantum dot device  100 , which may be used with embodiments of the invention described below.  FIG.  1 A  is a top view of a portion of the quantum dot device  100  with some of the materials removed so that the first gate lines  102 , the second gate lines  104 , and the third gate lines  106  are visible. Although many of the drawings and description herein may refer to a particular set of lines or gates as “barrier” or “quantum dot” lines or gates, respectively, this is simply for ease of discussion, and in other embodiments, the role of “barrier” and “quantum dot” lines and gates may be switched (e.g., barrier gates may instead act as quantum dot gates, and vice versa).  FIGS.  1 B- 1 F  are side cross-sectional views of the quantum dot device  100  of  FIG.  1 A ; in particular,  FIG.  1 B  is a view through the section B-B of  FIG.  1 A ,  FIG.  1 C  is a view through the section C-C of  FIG.  1 A ,  FIG.  1 D  is a view through the section D-D of  FIG.  1 A ,  FIG.  1 E  is a view through the section E-E of  FIG.  1 A , and  FIG.  1 F  is a view through the section F—F of  FIG.  1 A . 
     The quantum dot device  100  of  FIG.  1    may be operated in any of a number of ways. For example, in some embodiments, electrical signals such as voltages, currents, radio frequency (RF), and/or microwave signals, may be provided to one or more first gate line  102 , second gate line  104 , and/or third gate line  106  to cause a quantum dot (e.g., an electron spin-based quantum dot or a hole spin-based quantum dot) to form in a quantum well stack  146  under a third gate  166  of a third gate line  106 . Electrical signals provided to a third gate line  106  may control the electrical potential of a quantum well under the third gates  166  of that third gate line  106 , while electrical signals provided to a first gate line  102  (and/or a second gate line  104 ) may control the potential energy barrier under the first gates  162  of that first gate line  102  (and/or the second gates  164  of that second gate line  104 ) between adjacent quantum wells. Quantum interactions between quantum dots in different quantum wells in the quantum well stack  146  (e.g., under different quantum dot gates) may be controlled in part by the potential energy barrier provided by the barrier potentials imposed between them (e.g., by intervening barrier gates). 
     Generally, the quantum dot devices  100  disclosed herein may further include a source of magnetic fields (not shown) that may be used to create an energy difference in the states of a quantum dot (e.g., the spin states of an electron spin-based quantum dot) that are normally degenerate, and the states of the quantum dots (e.g., the spin states) may be manipulated by applying electromagnetic energy to the gates lines to create quantum bits capable of computation. The source of magnetic fields may be one or more magnet lines. Thus, the quantum dot devices  100  disclosed herein may, through controlled application of electromagnetic energy, be able to manipulate the position, number, and quantum state (e.g., spin) of quantum dots in the quantum well stack  146 . 
     In the quantum dot device  100  of  FIG.  1   , a gate dielectric  114  may be disposed on a quantum well stack  146 . A quantum well stack  146  may include at least one quantum well layer (not shown in  FIG.  1   ) in which quantum dots may be localized during operation of the quantum dot device  100 . The gate dielectric  114  may be any suitable material, such as a high-k material. Multiple parallel first gate lines  102  may be disposed on the gate dielectric  114 , and spacer material  118  may be disposed on side faces of the first gate lines  102 . In some embodiments, a patterned hardmask  110  may be disposed on the first gate lines  102  (with the pattern corresponding to the pattern of the first gate lines  102 ), and the spacer material  118  may extend up the sides of the hardmask  110 , as shown. The first gate lines  102  may each be a first gate  162 . Different ones of the first gate lines  102  may be electrically controlled in any desired combination (e.g., each first gate line  102  may be separately electrically controlled, or some or all the first gate lines  102  may be shorted together in one or more groups, as desired). 
     Multiple parallel second gate lines  104  may be disposed over and between the first gate lines  102 . As illustrated in  FIG.  1   , the second gate lines  104  may be arranged perpendicular to the first gate lines  102 . The second gate lines  104  may extend over the hardmask  110 , and may include second gates  164  that extend down toward the quantum well stack  146  and contact the gate dielectric  114  between adjacent ones of the first gate lines  102 , as illustrated in  FIG.  1 D . In some embodiments, the second gates  164  may fill the area between adjacent ones of the first gate lines  102 /spacer material  118  structures; in other embodiments, an insulating material (not shown) may be present between the first gate lines  102 /spacer material  118  structures and the proximate second gates  164 . In some embodiments, spacer material  118  may be disposed on side faces of the second gate lines  104 ; in other embodiments, no spacer material  118  may be disposed on side faces of the second gate lines  104 . In some embodiments, a hardmask  115  may be disposed above the second gate lines  104 . Multiple ones of the second gates  164  of a second gate line  104  are electrically continuous (due to the shared conductive material of the second gate line  104  over the hardmask  110 ). Different ones of the second gate lines  104  may be electrically controlled in any desired combination (e.g., each second gate line  104  may be separately electrically controlled, or some or all the second gate lines  104  may be shorted together in one or more groups, as desired). Together, the first gate lines  102  and the second gate lines  104  may form a grid, as depicted in  FIG.  1   . 
     Multiple parallel third gate lines  106  may be disposed over and between the first gate lines  102  and the second gate lines  104 . As illustrated in  FIG.  1   , the third gate lines  106  may be arranged diagonal to the first gate lines  102 , and diagonal to the second gate lines  104 . In particular, the third gate lines  106  may be arranged diagonally over the openings in the grid formed by the first gate lines  102  and the second gate lines  104 . The third gate lines  106  may include third gates  166  that extend down to the gate dielectric  114  in the openings in the grid formed by the first gate lines  102  and the second gate lines  104 ; thus, each third gate  166  may be bordered by two different first gate lines  102  and two different second gate lines  104 . In some embodiments, the third gates  166  may be bordered by insulating material  128 ; in other embodiments, the third gates  166  may fill the openings in the grid (e.g., contacting the spacer material  118  disposed on side faces of the adjacent first gate lines  102  and the second gate lines  104 , not shown). Additional insulating material  117  may be disposed on and/or around the third gate lines  106 . Multiple ones of the third gates  166  of a third gate line  106  are electrically continuous (due to the shared conductive material of the third gate line  106  over the first gate lines  102  and the second gate lines  104 ). Different ones of the third gate lines  106  may be electrically controlled in any desired combination (e.g., each third gate line  106  may be separately electrically controlled, or some or all the third gate lines  106  may be shorted together in one or more groups, as desired). 
     Although  FIGS.  1 A-F  illustrate a particular number of first gate lines  102 , second gate lines  104 , and third gate lines  106 , this is simply for illustrative purposes, and any number of first gate lines  102 , second gate lines  104 , and third gate lines  106  may be included in a quantum dot device  100 . Other examples of arrangements of first gate lines  102 , second gate lines  104 , and third gate lines  106  are possible. Electrical interconnects (e.g., vias and conductive lines) may contact the first gate lines  102 , second gate lines  104 , and third gate lines  106  in any desired manner. 
     Not illustrated in  FIG.  1    are accumulation regions that may be electrically coupled to the quantum well layer of the quantum well stack  146  (e.g., laterally proximate to the quantum well layer). The accumulation regions may be spaced apart from the gate lines by a thin layer of an intervening dielectric material. The accumulation regions may be regions in which carriers accumulate (e.g., due to doping, or due to the presence of large electrodes that pull carriers into the quantum well layer), and may serve as reservoirs of carriers that can be selectively drawn into the areas of the quantum well layer under the third gates  166  (e.g., by controlling the voltages on the quantum dot gates, the first gates  162 , and the second gates  164 ) to form carrier-based quantum dots (e.g., electron or hole quantum dots, including a single charge carrier, multiple charge carriers, or no charge carriers). In other embodiments, a quantum dot device  100  may not include lateral accumulation regions, but may instead include doped layers within the quantum well stack  146 . These doped layers may provide the carriers to the quantum well layer. Any combination of accumulation regions (e.g., doped or non-doped) or doped layers in a quantum well stack  146  may be used in any of the embodiments of the quantum dot devices  100  disclosed herein. 
     Referring now to  FIG.  2   , a simplified block diagram of a quantum compute device  200  is shown. In some embodiments, the quantum compute device  200  may include the quantum dot devices  100  described above in regard to  FIGS.  1 A- 1 F . The quantum compute device  200  may be embodied as or included in any type of compute device. For example, the quantum compute device  200  may include or otherwise be included in, without limitation, a server computer, an embedded computing system, a System-on-a-Chip (SoC), a multiprocessor system, a processor-based system, a consumer electronic device, a desktop computer, a laptop computer, a network device, a networked computer, a distributed computing system, and/or any other computing device. The illustrative quantum compute device  200  includes a processor  202 , a memory  204 , an input/output (I/O) subsystem  206 , a quantum/classical interface circuitry  208 , and a quantum processor  210 . In some embodiments, one or more of the illustrative components of the quantum compute device  200  may be incorporated in, or otherwise form a portion of, another component. For example, the memory  204 , or portions thereof, may be incorporated in the processor  202  in some embodiments. In some embodiments, the quantum compute device  200  may be embodied as the electrical device  1400  described below in regard to  FIG.  14    or may include any suitable component of the electrical device  1400 . 
     In some embodiments, the quantum compute device  200  may be located in a data center with other compute devices, such as an enterprise data center (e.g., a data center owned and operated by a company and typically located on company premises), managed services data center (e.g., a data center managed by a third party on behalf of a company), a colocated data center (e.g., a data center in which data center infrastructure is provided by the data center host and a company provides and manages their own data center components (servers, etc.)), cloud data center (e.g., a data center operated by a cloud services provider that host companies applications and data), and an edge data center (e.g., a data center, typically having a smaller footprint than other data center types, located close to the geographic area that it serves), a micro data center, etc. In some embodiments, the quantum compute device  200  may receive jobs over a network (such as the Internet) to perform on the quantum processor  210 . The quantum compute device  200  may perform the jobs on the quantum processor  210  and send the results back to the requesting device. 
     The processor  202  may be embodied as any type of processor capable of performing the functions described herein. For example, the processor  202  may be embodied as a single or multi-core processor(s), a single or multi-socket processor, a digital signal processor, a graphics processor, a neural network compute engine, an image processor, a microcontroller, or other processor or processing/controlling circuit. The processor  202  may include multiple processor cores. In some embodiments, the processor  202  supports quantum extensions to an existing ISA of the processor/core  202 , allowing instructions that interface with the quantum/classical interface circuitry  208  and the quantum processor  210 . 
     The memory  204  may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the memory  204  may store various data and software used during operation of the quantum compute device  200 , such as operating systems, applications, programs, libraries, and drivers. The memory  204  is communicatively coupled to the processor  202  via the I/O subsystem  206 , which may be embodied as circuitry and/or components to facilitate input/output operations with the processor  202 , the memory  204 , and other components of the quantum compute device  200 . For example, the I/O subsystem  206  may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations. The I/O subsystem  206  may connect various internal and external components of the quantum compute device  200  to each other with use of any suitable connector, interconnect, bus, protocol, etc., such as an SoC fabric, PCIe®, USB2, USB3, USB4, NVMe®, Thunderbolt®, Compute Express Link (CXL), and/or the like. In some embodiments, the I/O subsystem  206  may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor  202  and the memory  204  and other components of the quantum compute device  200  on a single integrated circuit chip. 
     The quantum/classical interface circuitry  208  is configured to interface with both classical components of the quantum compute device  200 , such as the processor  202  and memory  204 , as well as the quantum processor  210 . The quantum/classical interface circuitry  208  may include a variety of analog or digital circuitry, such as analog-to-digital converters, digital-to-analog converters, high gain amplifiers, low noise amplifiers, cryogenic amplifiers, field programmable gate arrays (FPGAs), classical processors, application-specific integrated circuits (ASICs), signal generating circuitry, signal conditioning circuitry, etc. In some embodiments, some or all of the quantum/classical interface circuitry  208  may be inside of a refrigerator, such as a dilution refrigerator, a magnetic refrigerator, a helium-4 and/or helium-3 refrigerator, etc. Some or all of the components of the quantum/classical interface circuitry  208  may be at any suitable temperature, such as 10 millikelvin, 100 millikelvin, 4 Kelvin, 20 Kelvin, 77 Kelvin, room temperature or above, or anywhere in between. 
     The quantum/classical interface circuitry  208  includes a signal generator  209 . The signal generator  209  is configured to prepare and filter or otherwise condition signals sent to the qubits to control or otherwise interface with the qubits. For example, the signal generator  209  may prepare a pulse to flip the state of a qubit from |0&gt; to |1&gt;. The pulse may have a particular center frequency associated with a resonant frequency of the qubit. In order to prevent such a pulse from affecting qubits with a nearby resonant frequency, the pulse may be filtered to remove energy content at frequencies corresponding to those qubits, as discussed in more detail below. 
     The quantum processor  210  is configured to operate one or more qubits. The qubits may be any suitable type of qubit, such as a quantum dot spin qubit described above in regard to  FIGS.  1 A- 1 F . In other embodiments, the qubits may be, e.g., charge qubits, transmon qubits, microwave qubits, superconducting qubits, or any other suitable type of qubits. The quantum processor  210  may include any suitable number of physical or logical qubits, such as 1-10 6 . In the illustrative embodiment, some or all of the quantum processor  210  is in a cryogenic refrigerator such as a dilution refrigerator. In particular, in the illustrative embodiment, the qubits are held at a temperature of about 10 millikelvin. In other embodiments, the qubits may be held at any suitable temperature, such as 1-100 millikelvin or higher, depending on the temperature sensitivity of the particular qubit in use. 
     The quantum processor  210  may be able to control the various qubits in various ways, such as by performing two-qubit gates, three-qubit gates, error correction operations, transferring a state from one type of qubit to another, measuring some, any or, all of the qubits, initializing some, any, or all of the qubits, etc. 
     The quantum compute device  200  may include additional components not shown in  FIG.  2   , such as one or more data storage devices, a network interface controller, one or more peripheral devices, etc. 
     Referring now to  FIG.  3   , in one embodiment, various components of the signal generator  209  of  FIG.  2    are shown. In the illustrative embodiment, the signal generator  209  generates a digital signal, processes it, and then creates an analog signal using a digital-to-analog converter (DAC)  312 . The various functions of the signal generator  209  may be performed by separate components dedicated to performing a particular function and/or may be performed by a processor or other logic. For example, the notch filter  304  may be implemented by one or more discrete components that modify the signal in a particular manner (as shown in  FIG.  5   ), and the gain  306  may be performed by logic that amplifies an incoming signal. Additionally or alternatively, in some embodiments, some or all of the blocks of the filter may be performed by general logic, such as a processor. 
     In block  302 , the signal generator  209  generates an envelope for a signal. In the illustrative embodiment, the envelope is a Gaussian. In other embodiments, the envelope may be a different shape. The illustrative envelope has a duration (as measured at the full width at half of maximum value) of about 170 nanoseconds. In other embodiments, the envelope may have a different duration, such as 20-2,000 nanoseconds. In the illustrative embodiment, both an in-phase and quadrature signal is generated (e.g., a sine function and a cosine function). In the illustrative embodiment, the block  302  sends a bitstream to the next block, where each value of the bitstream represents an amplitude of a signal to be generated at the DAC  312 . In the illustrative embodiment, block  302  generates a signal with a 10-12 bit resolution. In other embodiments, a different resolution may be used, such as 8-32 bit resolution. In the illustrative embodiment, the frequency of the data points is 2 GHz. In other words, the block  302  generates a signal of 10-12 bits with a new value generated everyone 0.5 nanoseconds. In other embodiments, a different frequency may be used, such as 0.5-4 GHz. In the illustrative embodiment, the amplitude of the pulse corresponds to a pulse that will flip a state of a target qubit or perform another desired operation on a target qubit, which will depend on the particular parameters of the qubit in question. 
     After the envelope is created, the signal passes through one or more notch filters  304 , such as notch filter  304 A and notch filter  304 B. As described below in more detail, each notch filter  304  has little impact on the peak amplitude of the overall pulse. As a result, several notch filters  304  can be chained together with little cumulative impact on the peak amplitude of the overall pulse. 
     Referring now to  FIG.  4   , in one embodiment, a notch filter  304  can include both a finite impulse response filter  414  and an infinite impulse response filter  416 . In block  402 , in the finite impulse response filter, each sample of the signal is delayed one cycle, multiplied by e jθ , and subtracted from the next sample of the signal, where θ is 2πƒ n /ƒ s ,ƒ s  is the sampling frequency (i.e., 2 GHz, in the illustrative embodiment), and ƒ n  is the frequency shift that is being filtered out relative to the center frequency. For example, in the illustrative embodiment, a target qubit has a resonant frequency of 325 MHz, and a collateral qubit has a resonant frequency of 327 MHz. The difference between those frequencies, ƒ s , is 2 MHz. Block  402  filters out the resonant frequency of the collateral qubit. However, block  402  also attenuates nearby frequencies relatively strongly. 
     In the illustrative embodiment, the incoming signal has a resolution of, e.g., 10 bits. After block  402 , the resolution of the signal is higher, in order for the calculations at the infinite impulse response filter  416  to be at a higher precision. As such, the resolution after block  402  in the illustrative embodiment increases by 16 bits, from 10 bits to 26 bits. In other embodiments, the resolution after block  402  may be increased by, e.g., 1-20 bits. 
     In embodiments without an infinite impulse response filter  416 , the attenuation at the finite impulse response filter  414  of, e.g., 40 dB leads to a relatively low-precision signal, requiring a higher-precision input of the signal of, e.g., 16 bits. Such an approach then requires more memory to store the signals at a higher resolution. As a result, using an infinite impulse response filter  416  reduces the memory requirement for storing the signals. 
     In order to mitigate some of the attenuation caused by the finite impulse response filter  414 , an infinite impulse response filter  416  is also used. At block  404 , each sample of the signal has added to it a feed-forward term that is created in blocks  406  and  410 . In the illustrative embodiment, the resolution of the signal is increased by 1 bit after block  404 . In other embodiments, the resolution of the signal may not increase after block  404 . 
     Block  406  shifts the signal back one sample time. Block  408  truncates the signal to fewer bits. In the illustrative embodiment, block  408  truncates the signal by 11 bits, reducing the signal from 27 bits to 16 bits. In other embodiments, block  408  may truncate the signal by 1-20 bits. In the illustrative embodiment, block  408  simply drops the lowest n bits. In other embodiments, block  408  may consider whether the most significant bit is a one and, if it is, round the remaining bits up to the next highest number. 
     Block  410  multiplies the shifted signal by ke jθ , where k is a scaling term between 0 and 1. If k is zero, the infinite impulse response filter  416  does not do anything. If k is one, the infinite impulse response filter  416  nearly completely undoes the finite impulse response filter  414 . In use, in one embodiment, k is equal to 0.99. In other embodiments, k may be any suitable value between 0 and 1. A smaller value of k leads to a higher attenuation of frequencies near the filtered frequency and a faster response time, and a higher value of k leads to less attenuation of frequencies near the filtered frequency and a slower response time. After block  410 , the signal has a precision of 26 bits, in the illustrative embodiment. 
     After the infinite impulse response filter  416 , the signal is increased at a gain block  412 . The signal may be increased in order to offset any decrease in the amplitude at the center frequency caused by the filters  414 ,  416 . For example, the signal may be increased by a factor of, e.g., 1.5-4. 
     After the gain block  412 , the signal is truncated at block  413  back to the same number of bits as the incoming signal (i.e., 10 bits, in the illustrative embodiment). It should be appreciated that, while the finite impulse response filter  414  does not significantly change the shape or duration of the pulse, the infinite impulse response filter  416  may significantly change the shape or duration of the pulse. For example, the infinite impulse response filter  416  may increase a pulse length by more than a factor of two. A smaller value of k will generally lead to a shorter pulse length, and a larger value of k will generally lead to a longer pulse length. 
     Referring back to  FIG.  3   , after the notch filters  304 , the signal may be increased at a gain block  306 . For example, the signal may be increased by a factor of, e.g., 1.5-4. In some embodiments, the gain block  306  may not be included or may provide no gain. 
     The signal is then modulated using a numerically-controlled oscillator  308  at block  310 . In the illustrative, the signal is modulated to, e.g., 350 MHz. More generally, the signal may be modulated at a frequency of, e.g., 100-1,000 MHz. In the illustrative embodiment, the resonant frequency is higher than the numerically-controlled oscillator  308  and higher than the maximum frequency of the DAC  312 . Accordingly, the signal from the DAC  312  is upconverted to a higher frequency, such as 12-20 GHz. The signal can then be provided to the target qubit. It should be appreciated that quantum processor  210  can be configured to provide the signal from the DAC  312  to multiple qubits, allowing the signal generator  209  to control multiple qubits from one DAC  312 . As the notch filters  304  can filter out frequencies that would affect collateral qubits, a particular operation will only significantly affect the target qubit. 
     It should be appreciated that the signal generator  209  can generate a pulse to control a target qubit at a particular frequency without significantly impacting a collateral qubit with a nearby resonant frequency. As a result, the quantum processor  210  can have many qubits spaced relatively closely together that are controlled by the signal generator  209  driving a single cable between the signal generator  209  and the quantum processor  210 . For example, a bandwidth of a pulse may be, e.g., 10 MHz. Without filtering, qubits at the closest frequency would have to be spaced apart by, e.g., 20 MHz. In contrast, with the filtering shown, qubits may be spaced apart by, e.g., 2 MHz. As the total bandwidth of the DAC  312  is limited to, e.g., 1 GHz, spacing qubits closer together allows more qubits to be controlled by the signal created at the DAC  312 . 
     Additionally, the signal generator  209  can create signals to control qubits with a small memory requirement. Instead of, e.g., storing a digital waveform of a pulse to drive each qubit, the signal generator  209  can store a small number of parameters of what frequencies to filter out for particular collateral qubits with frequencies near the target qubit, reducing memory and power requirements in the signal generator  209 . As the attenuation of the signal at the center frequency is relatively small, an amount of memory needed to store a template of a waveform of a signal for a particular control pulse can be independent of the number of filters to be applied. As the signal generator  209  may be in a cryogenic environment held at, e.g., 4 Kelvin with limited cooling capability, reducing power requirements can be critical. 
     Additionally, the signal generator  209  does not result in any significant loss in the dynamic range of the signal being created, even at frequencies near those being filtered out. As a result, the signal does not need a large number of bits in order to retain the necessary precision of the signal. 
     It should be appreciated that, in some embodiments, the signal generator  209  may be arranged in a different manner than shown in  FIG.  3   . For example, in one embodiment, the gain block  306  and/or the modulation block  310  may be before the notch filters  304 . More generally, the signal generator  209  may not include some of the components shown in  FIG.  3    and/or may include additional components not shown in  FIG.  3   . 
     Referring now to  FIG.  5   , in one embodiment, a plot  500  shows filter response as a function of frequency for two different filters. Curve  502  shows a filter response for a finite impulse response filter  414 . The filtered frequency is offset from the target frequency of 10 MHz by about 2 MHz. As can be seen from the plot  500 , the finite impulse response filter  414  causes over 40 dB of attenuation at the target frequency of 10 MHz. In contrast, curve  504  shows a filter response for a combination of the finite impulse response filter  414  and the infinite impulse response filter  416 . The attenuation of such a filter at the target frequency is less than 5 dB, while maintaining high attenuation of the filtered frequency. 
     Referring now to  FIGS.  6 - 8   , in one embodiment, simulated plots  600 ,  700 ,  800  of the output of the DAC  312  with various filters are shown. The plots  600 ,  700 ,  800  show the output in dB as a function of frequency. Plot  600  shows a curve  602  with no notch filters  304 . Plot  700  shows a curve  702  with one notch filter  304  about 2 MHz about the target frequency. Plot  800  shows a curve  802  with two notch filters  304 , one at about 2 MHz above the target frequency and another at about 5 MHz below the target frequency. As shown in the plots  600 ,  700 ,  800 , the notch filters  304  do not significantly reduce the peak of the signal at the target frequency. 
     Referring now to  FIG.  9   , in one embodiment, a flowchart for a method  900  for determining parameters for the notch filters  304  and other components of the signal generator  209  are shown. In some embodiments, filtering out the exact frequency of the collateral qubits may not result in zero change to the state of those qubits, as small contributions from frequencies within the bandwidth of the sensitivity of the collateral qubits can cause significant shifts in the state of the collateral qubits. In order to reduce the impact on the collateral qubits, the parameters of the notch filters  304  and/or other components of the signal generator  209  can be tuned. 
     In the illustrative embodiment, the parameters can be determined ahead of time-based on simulations of the qubits in the quantum processor  210 . The parameters can be determined by the quantum compute device  200 , either by the processor  202 , the quantum/classical interface circuitry  208 , or by another component. In some embodiments, the parameters can be determined by a compute device other than the quantum compute device  200 . Thus, it should be appreciated that, although the method  900  is described as being performed by the quantum compute device  100 , it could be performed by any suitable compute device. 
     The method  900  begins in block  902  in which the quantum compute device  200  determines a frequency of a target qubit. The quantum compute device  200  may determine the frequency of the target qubit in any suitable manner, such as based on specifications of the quantum processor  210 , by measuring the frequency of the qubit, by controlling or configuring the frequency of the qubit, by accessing a previously-stored value of the frequency of the qubit, etc. 
     In block  904 , the quantum compute device  200  determines a pulse to be sent to the target qubit. The quantum compute device  200  may determine a pulse width, frequency, amplitude, etc. 
     In block  906 , the quantum compute device  200  determines a frequency for one or more collateral qubits. The collateral qubits are qubits that are controlled using the same cable, transmission line, and/or the like as the target qubit and that are within a frequency of a pulse that will be used to control the target qubit. 
     In block  908 , the quantum compute device  200  determines parameters of the digital filters  414 ,  416  to be applied to the signal to be sent to the target qubit. Additionally or alternatively, in some embodiments, the quantum compute device  200  may determine parameters for other components of the signal generator  209 , such as the gain  306 . In the illustrative embodiment, the quantum compute device  200  determines parameters to filter out a frequency corresponding to the collateral qubits. It should be appreciated that, in the illustrative embodiment, the frequencies filtered out at the filters  414 ,  416  are not the same as the resonance frequency for the collateral qubits because the signal generated at the DAC  312  is unconverted in block  314  before being sent to the qubits. As such, the frequencies filtered out at the filters  414 ,  416  correspond to the collateral qubits in the sense that the frequencies filtered out at the filters  414 ,  416  are upconverted to frequencies whose filtering will result in little impact on the state of the collateral qubits. 
     In block  910 , the quantum compute device  200  determines the effect of the filtered pulse on collateral qubits. In the illustrative embodiment, the quantum compute device  200  simulates the effect on the collateral qubits. Additionally or alternatively, in some embodiments, the quantum compute device  200  may send the pulse to the target and collateral qubits and characterize the resulting states of the qubits. In some embodiments, the quantum compute device  200  may also determine the effect of the filtered pulse on the target qubit. 
     In block  912 , the quantum compute device  200  determines whether to continue tuning parameters based on the determined effect of the filtered pulse on the collateral qubits. The quantum compute device  200  may, e.g., compare the resulting fidelity of the collateral and/or target qubits to a threshold, compare the increase in fidelity of the collateral and/or target qubits for the past iteration of the algorithm to a threshold, etc. Additionally or alternatively, the quantum compute device  200  may consider the fidelity of the desired operation on the target qubit. For example, in one embodiment, the quantum compute device may try to maximize the probability that the target qubit changes state plus the probability that the collateral qubit does not change state. 
     In block  914 , if the quantum compute device  200  is to continue tuning parameters, the method  900  proceeds to block  916 . In block  916 , the quantum compute device  200  adjusts parameters of the notch filters  304 . For example, the quantum compute device  200  may adjust the filtered frequency of the finite impulse response filter  414  and the infinite impulse response filter  416 . In the illustrative embodiment, the frequency for the finite impulse response filter  414  is set to be the same as the frequency for the infinite impulse response filter  416 . In other embodiments, the frequencies for the finite impulse response filter  414  and the infinite impulse response filter  416  may be independent. In some embodiments, the quantum compute device  200  may adjust the parameter k of the infinite impulse response filter  416 . The quantum compute device  200  may use any suitable algorithm to adjust the parameters, such as gradient descent, a genetic algorithm, a machine-learning-based algorithm etc. The method  900  then loops back to block  910  to determine the effect of the filtered pulse on the collateral qubits. 
     Referring back to block  914 , if the quantum compute device is not to continue tuning parameters, the method  900  proceeds to block  918 , in which the quantum compute device  200  stores the parameters of the filters  414 ,  416  in the signal generator  209 . It should be appreciated that the signal generator  209  can create control signals with relatively few parameters, such as parameters for the initial pulse and a small number of relatively low-precision parameters for the notch filters  304 . As such, the signal generator  209  can store parameters for a large number of control pulses corresponding to a large number of qubits in a relatively small amount of memory. 
     It should be appreciated that the method  900  may be repeated for each qubit in the quantum processor  210  and/or may be repeated for each of several pulses that may be applied to each qubit in the quantum processor  210 . In some embodiments, some or all of the method  900  may be repeated for each notch filter  304  to be used. In some embodiments, an amount of gain to add in block  306  of  FIG.  3    may be adjusted as other parameters are adjusted in blocks  910 - 916 . In other embodiments, an amount of gain to add in block  306  may be determined after other parameters of the notch filters  304  are determined. 
     It should be appreciated that the method  900  can determine filter parameters that will lead to high fidelity operations on the target qubit with performing no action on the collateral qubits with high fidelity. For example, in one embodiment, a simulation of a pulse can be determined that will perform a qubit flip operation on the target qubit with a fidelity of 0.994 and perform no action on a collateral qubit with a fidelity of 0.999. 
     In some cases, the frequency of the notch filter  304  may be moved somewhat far from the frequency of the collateral qubit in order to improve the fidelity of the collateral qubit. For example, in one embodiment, a collateral qubit may be offset from the target qubit by 2.11 MHz, and the notch filter  304  may be set at a frequency of 2.52 MHz to reduce the impact of the signal on the collateral qubit. More generally, the notch filter  304  may be set at a frequency that is 0-30% more or less than the actual frequency difference from the target qubit. The frequency of the notch filter  304  may be determined using simulations or other calculations similar to those discussed above in regard to blocks  910 - 916 , as the effect of the frequency of the notch filter  304  on factors such as qubit fidelity is a nonlinear function. During application of the pulse, the state of the collateral qubit in, e.g., a |0&gt; state may significantly change before returning to the |0&gt; state with high fidelity. It should be appreciated that such a state evolution may induce a phase change in the qubit, which can be tracked and corrected. 
       FIG.  10    is a top view of a wafer  1000  and dies  1002 . The wafer  1000  may be composed of semiconductor material and may include one or more dies  1002  having integrated circuit structures formed on a surface of the wafer  1000 . The individual dies  1002  may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer  1000  may undergo a singulation process in which the dies  1002  are separated from one another to provide discrete “chips” of the integrated circuit product. The die  1002  may include one or more transistors (e.g., some of the transistors  1140  of  FIG.  11   , discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other integrated circuit components. In some embodiments, the wafer  1000  or the die  1002  may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die  1002 . For example, a memory array formed by multiple memory devices may be formed on a same die  1002  as a processor unit (e.g., the processor unit  1402  of  FIG.  14   ) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. Various chips disclosed herein may be manufactured using a die-to-wafer assembly technique in which some chips are attached to a wafer  1000  that include others of the chips and the wafer  1000  is subsequently singulated. 
       FIG.  11    is a cross-sectional side view of an integrated circuit device  1100  that may be included in any of the chips disclosed herein. One or more of the integrated circuit devices  1100  may be included in one or more dies  1002  ( FIG.  10   ). The integrated circuit device  1100  may be formed on a die substrate  1102  (e.g., the wafer  1000  of  FIG.  10   ) and may be included in a die (e.g., the die  1002  of  FIG.  10   ). The die substrate  1102  may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate  1102  may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate  1102  may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate  1102 . Although a few examples of materials from which the die substrate  1102  may be formed are described here, any material that may serve as a foundation for an integrated circuit device  1100  may be used. The die substrate  1102  may be part of a singulated die (e.g., the dies  1002  of  FIG.  10   ) or a wafer (e.g., the wafer  1000  of  FIG.  10   ). 
     The integrated circuit device  1100  may include one or more device layers  1104  disposed on the die substrate  1102 . The device layer  1104  may include features of one or more transistors  1140  (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate  1102 . The transistors  1140  may include, for example, one or more source and/or drain (S/D) regions  1120 , a gate  1122  to control current flow between the S/D regions  1120 , and one or more S/D contacts  1124  to route electrical signals to/from the S/D regions  1120 . The transistors  1140  may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors  1140  are not limited to the type and configuration depicted in  FIG.  11    and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non- planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors. 
       FIGS.  12 A- 12 D  are simplified perspective views of example planar, FinFET, gate-all-around, and stacked gate-all-around transistors. The transistors illustrated in  FIGS.  12 A- 12 D  are formed on a substrate  1216  having a surface  1208 . Isolation regions  1214  separate the source and drain regions of the transistors from other transistors and from a bulk region  1218  of the substrate  1216 . 
       FIG.  12 A  is a perspective view of an example planar transistor  1200  comprising a gate  1202  that controls current flow between a source region  1204  and a drain region  1206 . The transistor  1200  is planar in that the source region  1204  and the drain region  1206  are planar with respect to the substrate surface  1208 . 
       FIG.  12 B  is a perspective view of an example FinFET transistor  1220  comprising a gate  1222  that controls current flow between a source region  1224  and a drain region  1226 . The transistor  1220  is non-planar in that the source region  1224  and the drain region  1226  comprise “fins” that extend upwards from the substrate surface  1228 . As the gate  1222  encompasses three sides of the semiconductor fin that extends from the source region  1224  to the drain region  1226 , the transistor  1220  can be considered a tri-gate transistor.  FIG.  12 B  illustrates one S/D fin extending through the gate  1222 , but multiple S/D fins can extend through the gate of a FinFET transistor. 
       FIG.  12 C  is a perspective view of a gate-all-around (GAA) transistor  1240  comprising a gate  1242  that controls current flow between a source region  1244  and a drain region  1246 . The transistor  1240  is non-planar in that the source region  1244  and the drain region  1246  are elevated from the substrate surface  1228 . 
       FIG.  12 D  is a perspective view of a GAA transistor  1260  comprising a gate  1262  that controls current flow between multiple elevated source regions  1264  and multiple elevated drain regions  1266 . The transistor  1260  is a stacked GAA transistor as the gate controls the flow of current between multiple elevated S/D regions stacked on top of each other. The transistors  1240  and  1260  are considered gate-all-around transistors as the gates encompass all sides of the semiconductor portions that extends from the source regions to the drain regions. The transistors  1240  and  1260  can alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors depending on the width (e.g., widths  1248  and  1268  of transistors  1240  and  1260 , respectively) of the semiconductor portions extending through the gate. 
     Returning to  FIG.  11   , a transistor  1140  may include a gate  1122  formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. 
     The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used. 
     The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor  1140  is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. 
     For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning). 
     In some embodiments, when viewed as a cross-section of the transistor  1140  along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate  1102  and two sidewall portions that are substantially perpendicular to the top surface of the die substrate  1102 . In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate  1102  and does not include sidewall portions substantially perpendicular to the top surface of the die substrate  1102 . In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. 
     In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack. 
     The S/D regions  1120  may be formed within the die substrate  1102  adjacent to the gate  1122  of individual transistors  1140 . The S/D regions  1120  may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate  1102  to form the S/D regions  1120 . An annealing process that activates the dopants and causes them to diffuse farther into the die substrate  1102  may follow the ion-implantation process. In the latter process, the die substrate  1102  may first be etched to form recesses at the locations of the S/D regions  1120 . An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions  1120 . In some implementations, the S/D regions  1120  may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions  1120  may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions  1120 . 
     Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors  1140 ) of the device layer  1104  through one or more interconnect layers disposed on the device layer  1104  (illustrated in  FIG.  11    as interconnect layers  1106 - 1110 ). For example, electrically conductive features of the device layer  1104  (e.g., the gate  1122  and the S/D contacts  1124 ) may be electrically coupled with the interconnect structures  1128  of the interconnect layers  1106 - 1110 . The one or more interconnect layers  1106 - 1110  may form a metallization stack (also referred to as an “ILD stack”)  1119  of the integrated circuit device  1100 . 
     The interconnect structures  1128  may be arranged within the interconnect layers  1106 - 1110  to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures  1128  depicted in  FIG.  11   . Although a particular number of interconnect layers  1106 - 1110  is depicted in  FIG.  11   , embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted. 
     In some embodiments, the interconnect structures  1128  may include lines  1128   a  and/or vias  1128   b  filled with an electrically conductive material such as a metal. The lines  1128   a  may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate  1102  upon which the device layer  1104  is formed. For example, the lines  1128   a  may route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias  1128   b  may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate  1102  upon which the device layer  1104  is formed. In some embodiments, the vias  1128   b  may electrically couple lines  1128   a  of different interconnect layers  1106 - 1110  together. 
     The interconnect layers  1106 - 1110  may include a dielectric material  1126  disposed between the interconnect structures  1128 , as shown in  FIG.  11   . In some embodiments, dielectric material  1126  disposed between the interconnect structures  1128  in different ones of the interconnect layers  1106 - 1110  may have different compositions; in other embodiments, the composition of the dielectric material  1126  between different interconnect layers  1106 - 1110  may be the same. The device layer  1104  may include a dielectric material  1126  disposed between the transistors  1140  and a bottom layer of the metallization stack as well. The dielectric material  1126  included in the device layer  1104  may have a different composition than the dielectric material  1126  included in the interconnect layers  1106 - 1110 ; in other embodiments, the composition of the dielectric material  1126  in the device layer  1104  may be the same as a dielectric material  1126  included in any one of the interconnect layers  1106 - 1110 . 
     A first interconnect layer  1106  (referred to as Metal 1 or “M1”) may be formed directly on the device layer  1104 . In some embodiments, the first interconnect layer  1106  may include lines  1128   a  and/or vias  1128   b , as shown. The lines  1128   a  of the first interconnect layer  1106  may be coupled with contacts (e.g., the S/D contacts  1124 ) of the device layer  1104 . The vias  1128   b  of the first interconnect layer  1106  may be coupled with the lines  1128   a  of a second interconnect layer  1108 . 
     The second interconnect layer  1108  (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer  1106 . In some embodiments, the second interconnect layer  1108  may include via  1128   b  to couple the lines  1128  of the second interconnect layer  1108  with the lines  1128   a  of a third interconnect layer  1110 . Although the lines  1128   a  and the vias  1128   b  are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines  1128   a  and the vias  1128   b  may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments. 
     The third interconnect layer  1110  (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer  1108  according to similar techniques and configurations described in connection with the second interconnect layer  1108  or the first interconnect layer  1106 . In some embodiments, the interconnect layers that are “higher up” in the metallization stack  1119  in the integrated circuit device  1100  (i.e., farther away from the device layer  1104 ) may be thicker than the interconnect layers that are lower in the metallization stack  1119 , with lines  1128   a  and vias  1128   b  in the higher interconnect layers being thicker than those in the lower interconnect layers. 
     The integrated circuit device  1100  may include a solder resist material  1134  (e.g., polyimide or similar material) and one or more conductive contacts  1136  formed on the interconnect layers  1106 - 1110 . In  FIG.  11   , the conductive contacts  1136  are illustrated as taking the form of bond pads. The conductive contacts  1136  may be electrically coupled with the interconnect structures  1128  and configured to route the electrical signals of the transistor(s)  1140  to external devices. For example, solder bonds may be formed on the one or more conductive contacts  1136  to mechanically and/or electrically couple an integrated circuit die including the integrated circuit device  1100  with another component (e.g., a printed circuit board). The integrated circuit device  1100  may include additional or alternate structures to route the electrical signals from the interconnect layers  1106 - 1110 ; for example, the conductive contacts  1136  may include other analogous features (e.g., posts) that route the electrical signals to external components. The conductive contacts  1136  may serve as the conductive pads  509 , as appropriate. 
     In some embodiments in which the integrated circuit device  1100  is a double-sided die, the integrated circuit device  1100  may include another metallization stack (not shown) on the opposite side of the device layer(s)  1104 . This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers  1106 - 1110 , to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s)  1104  and additional conductive contacts (not shown) on the opposite side of the integrated circuit device  1100  from the conductive contacts  1136 . These additional conductive contacts may serve as the conductive pads  509 , as appropriate. 
     In other embodiments in which the integrated circuit device  1100  is a double-sided die, the integrated circuit device  1100  may include one or more through silicon vias (TSVs) through the die substrate  1102 ; these TSVs may make contact with the device layer(s)  1104 , and may provide conductive pathways between the device layer(s)  1104  and additional conductive contacts (not shown) on the opposite side of the integrated circuit device  1100  from the conductive contacts  1136 . These additional conductive contacts may serve as the conductive pads  509 , as appropriate. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device  1100  from the conductive contacts  1136  to the transistors  1140  and any other components integrated into the die  1100 , and the metallization stack  1119  can be used to route I/O signals from the conductive contacts  1136  to transistors  1140  and any other components integrated into the die  1100 . 
     Multiple integrated circuit devices  1100  may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps). 
       FIG.  13    is a cross-sectional side view of an integrated circuit device assembly  1300 . The integrated circuit device assembly  1300  includes a number of components disposed on a circuit board  1302  (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly  1300  includes components disposed on a first face  1340  of the circuit board  1302  and an opposing second face  1342  of the circuit board  1302 ; generally, components may be disposed on one or both faces  1340  and  1342 . Any of the integrated circuit components discussed below with reference to the integrated circuit device assembly  1300  may include or be included in any suitable ones of the embodiments disclosed herein. 
     In some embodiments, the circuit board  1302  may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board  1302 . In other embodiments, the circuit board  1302  may be a non-PCB substrate. The integrated circuit device assembly  1300  illustrated in  FIG.  13    includes a package-on-interposer structure  1336  coupled to the first face  1340  of the circuit board  1302  by coupling components  1316 . The coupling components  1316  may electrically and mechanically couple the package-on-interposer structure  1336  to the circuit board  1302 , and may include solder balls (as shown in  FIG.  13   ), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. 
     The package-on-interposer structure  1336  may include an integrated circuit component  1320  coupled to an interposer  1304  by coupling components  1318 . The coupling components  1318  may take any suitable form for the application, such as the forms discussed above with reference to the coupling components  1316 . Although a single integrated circuit component  1320  is shown in  FIG.  13   , multiple integrated circuit components may be coupled to the interposer  1304 ; indeed, additional interposers may be coupled to the interposer  1304 . The interposer  1304  may provide an intervening substrate used to bridge the circuit board  1302  and the integrated circuit component  1320 . 
     The integrated circuit component  1320  may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die  1002  of  FIG.  10   , the integrated circuit device  1100  of  FIG.  11   ) and/or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component  1320 , a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer  1304 . The integrated circuit component  1320  can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller. In some embodiments, the integrated circuit component  1320  can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. 
     In embodiments where the integrated circuit component  1320  comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM). 
     In addition to comprising one or more processor units, the integrated circuit component  1320  can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof. 
     Generally, the interposer  1304  may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer  1304  may couple the integrated circuit component  1320  to a set of ball grid array (BGA) conductive contacts of the coupling components  1316  for coupling to the circuit board  1302 . In the embodiment illustrated in  FIG.  13   , the integrated circuit component  1320  and the circuit board  1302  are attached to opposing sides of the interposer  1304 ; in other embodiments, the integrated circuit component  1320  and the circuit board  1302  may be attached to a same side of the interposer  1304 . In some embodiments, three or more components may be interconnected by way of the interposer  1304 . 
     In some embodiments, the interposer  1304  may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer  1304  may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer  1304  may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer  1304  may include metal interconnects  1308  and vias  1310 , including but not limited to through hole vias  1310 - 1  (that extend from a first face  1350  of the interposer  1304  to a second face  1354  of the interposer  1304 ), blind vias  1310 - 2  (that extend from the first or second faces  1350  or  1354  of the interposer  1304  to an internal metal layer), and buried vias  1310 - 3  (that connect internal metal layers). 
     In some embodiments, the interposer  1304  can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer  1304  comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer  1304  to an opposing second face of the interposer  1304 . 
     The interposer  1304  may further include embedded devices  1314 , including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer  1304 . The package-on-interposer structure  1336  may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board 
     The integrated circuit device assembly  1300  may include an integrated circuit component  1324  coupled to the first face  1340  of the circuit board  1302  by coupling components  1322 . The coupling components  1322  may take the form of any of the embodiments discussed above with reference to the coupling components  1316 , and the integrated circuit component  1324  may take the form of any of the embodiments discussed above with reference to the integrated circuit component  1320 . 
     The integrated circuit device assembly  1300  illustrated in  FIG.  13    includes a package-on-package structure  1334  coupled to the second face  1342  of the circuit board  1302  by coupling components  1328 . The package-on-package structure  1334  may include an integrated circuit component  1326  and an integrated circuit component  1332  coupled together by coupling components  1330  such that the integrated circuit component  1326  is disposed between the circuit board  1302  and the integrated circuit component  1332 . The coupling components  1328  and  1330  may take the form of any of the embodiments of the coupling components  1316  discussed above, and the integrated circuit components  1326  and  1332  may take the form of any of the embodiments of the integrated circuit component  1320  discussed above. The package-on-package structure  1334  may be configured in accordance with any of the package-on-package structures known in the art. 
       FIG.  14    is a block diagram of an example electrical device  1400 . For example, any suitable ones of the components of the electrical device  1400  may include one or more of the integrated circuit device assemblies  1300 , integrated circuit components  1320 , integrated circuit devices  1100 , or integrated circuit dies  1002  disclosed. A number of components are illustrated in  FIG.  14    as included in the electrical device  1400 , but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device  1400  may be attached to one or more motherboards mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die. 
     Additionally, in various embodiments, the electrical device  1400  may not include one or more of the components illustrated in  FIG.  14   , but the electrical device  1400  may include interface circuitry for coupling to the one or more components. For example, the electrical device  1400  may not include a display device  1406 , but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device  1406  may be coupled. In another set of examples, the electrical device  1400  may not include an audio input device  1424  or an audio output device  1408 , but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device  1424  or audio output device  1408  may be coupled. 
     The electrical device  1400  may include one or more processor units  1402  (e.g., one or more processor units). As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit  1402  may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU). 
     The electrical device  1400  may include a memory  1404 , which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory  1404  may include memory that is located on the same integrated circuit die as the processor unit  1402 . This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM). 
     In some embodiments, the electrical device  1400  can comprise one or more processor units  1402  that are heterogeneous or asymmetric to another processor unit  1402  in the electrical device  1400 . There can be a variety of differences between the processing units  1402  in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units  1402  in the electrical device  1400 . 
     In some embodiments, the electrical device  1400  may include a communication component  1412  (e.g., one or more communication components). For example, the communication component  1412  can manage wireless communications for the transfer of data to and from the electrical device  1400 . The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not. 
     The communication component  1412  may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component  1412  may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component  1412  may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component  1412  may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component  1412  may operate in accordance with other wireless protocols in other embodiments. The electrical device  1400  may include an antenna  1422  to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). 
     In some embodiments, the communication component  1412  may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component  1412  may include multiple communication components. For instance, a first communication component  1412  may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component  1412  may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component  1412  may be dedicated to wireless communications, and a second communication component  1412  may be dedicated to wired communications. 
     The electrical device  1400  may include battery/power circuitry  1414 . The battery/power circuitry  1414  may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device  1400  to an energy source separate from the electrical device  1400  (e.g., AC line power). 
     The electrical device  1400  may include a display device  1406  (or corresponding interface circuitry, as discussed above). The display device  1406  may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display. 
     The electrical device  1400  may include an audio output device  1408  (or corresponding interface circuitry, as discussed above). The audio output device  1408  may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds. 
     The electrical device  1400  may include an audio input device  1424  (or corresponding interface circuitry, as discussed above). The audio input device  1424  may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device  1400  may include a Global Navigation Satellite System (GNSS) device  1418  (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device  1418  may be in communication with a satellite-based system and may determine a geolocation of the electrical device  1400  based on information received from one or more GNSS satellites, as known in the art. 
     The electrical device  1400  may include an other output device  1410  (or corresponding interface circuitry, as discussed above). Examples of the other output device  1410  may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. 
     The electrical device  1400  may include an other input device  1420  (or corresponding interface circuitry, as discussed above). Examples of the other input device  1420  may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader. 
     The electrical device  1400  may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device  1400  may be any other electronic device that processes data. In some embodiments, the electrical device  1400  may comprise multiple discrete physical components. Given the range of devices that the electrical device  1400  can be manifested as in various embodiments, in some embodiments, the electrical device  1400  can be referred to as a computing device or a computing system. 
     Some examples of embodiments are provided below. As used in the following examples, the term “connected” may refer to an electrical connection. In some instances, the connection may be a direct connection between two items/components. Further, as used in the following examples, the term “coupled” may refer to a connection that may be direct or indirect. For example, a first component coupled to a second component may include a third component connected between the first and second components. 
     Example 1 includes a system comprising quantum/classical interface circuitry to generate a signal for an operation on a target qubit, the signal including a first frequency corresponding to the target qubit; apply a finite impulse response filter to the signal to filter a second frequency corresponding to a collateral qubit; apply an infinite impulse response filter to the signal to amplify frequencies near the second frequency; and send the signal to the target qubit. 
     Example 2 includes the subject matter of Example 1, and wherein the quantum/classical interface circuitry is to operate in a cryogenic refrigerator at a temperature below 10 Kelvin, wherein the quantum/classical interface circuitry is to store parameters to create a control pulse for individual qubits of a plurality of qubits, wherein to create the control pulse for individual qubits of the plurality of qubits comprises to apply two or more infinite impulse response filter to filter frequencies corresponding to other qubits of the plurality of qubits. 
     Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the plurality of qubits comprises at least 50 qubits. 
     Example 4 includes the subject matter of any of Examples 1-3, and wherein an amount of storage to store a template of the control pulse for individual qubits of the plurality of qubits is independent of a number of infinite impulse response filters to be applied to the corresponding control pulse. 
     Example 5 includes the subject matter of any of Examples 1-4, and wherein a template of the control pulse for individual qubits of the plurality of qubits is stored at a precision of less than or equal to 12 bits. 
     Example 6 includes the subject matter of any of Examples 1-5, and wherein individual qubits of the plurality of qubits are spaced apart from each other by less than a bandwidth of the control pulse for individual qubits, wherein the quantum/classical interface circuitry is to transmit control pulses for any of the plurality of qubits on the same data cable. 
     Example 7 includes the subject matter of any of Examples 1-6, and wherein the quantum/classical interface circuitry is to receive the parameters to create the control pulse for individual qubits of the plurality of qubits from a compute device outside of the cryogenic refrigerator. 
     Example 8 includes the subject matter of any of Examples 1-7, and wherein to apply the infinite impulse response filter to the signal to amplify frequencies near the second frequency comprises to apply the infinite impulse response filter based on a parameter, wherein the parameter controls a depth of the filter and an inband attenuation of the filter. 
     Example 9 includes the subject matter of any of Examples 1-8, and wherein to apply the finite impulse response filter to the signal to filter the second frequency comprises to apply the finite impulse response filter to an in-phase and quadrature component of the signal, wherein to apply the infinite impulse response filter to the signal comprises to apply the infinite impulse response filter to the in-phase and quadrature component of the signal. 
     Example 10 includes the subject matter of any of Examples 1-9, and wherein to apply the infinite impulse response filter comprises to multiply a time sample of the signal by a real number less than one times a complex phase corresponding to the second frequency and add it to the next time sample of the signal. 
     Example 11 includes the subject matter of any of Examples 1-10, and wherein to apply the finite impulse response filter and the infinite impulse response filter comprises to increase a precision of time samples of the signal by at least 5 bits, wherein the quantum/classical interface circuitry is to truncate the signal after the finite impulse response filter and the infinite impulse response filter by at least 2 bits. 
     Example 12 includes the subject matter of any of Examples 1-11, and wherein to truncate the signal after the finite impulse response filter and the infinite impulse response filter comprises to truncate the signal to a precision of the signal before the finite impulse response filter and the infinite impulse response filter. 
     Example 13 includes the subject matter of any of Examples 1-12, and wherein the collateral qubit has a resonant frequency, wherein the second frequency corresponding to the collateral qubit corresponds to a frequency at least 10% higher or lower than the resonant frequency of the collateral qubit. 
     Example 14 includes the subject matter of any of Examples 1-13, and further including a cryogenic refrigerator, wherein the quantum/classical interface circuitry is in the cryogenic refrigerator; a plurality of qubits in the cryogenic refrigerator, the plurality of qubits comprising the target qubit and the collateral qubit, the plurality of qubits communicatively coupled to the quantum/classical interface circuitry; and a classical processor outside of the cryogenic refrigerator, the classical processor coupled to the quantum/classical interface circuitry. 
     Example 15 includes a system comprising quantum/classical interface circuitry; and a compute device to determine parameters of two or more infinite impulse response filters to be applied by the quantum/classical interface circuitry; and send the parameters of the two or more infinite impulse response filters to the quantum/classical interface circuitry, wherein the quantum/classical interface circuitry is to receive the parameters of the two or more infinite impulse response filters from the compute device; store the parameters of the two or more infinite impulse response filters; and generate a control signal for a target qubit with use of the parameters of the two or more infinite impulse response filters, wherein the quantum/classical interface circuitry is to operate in a cryogenic refrigerator at a temperature below 10 Kelvin, wherein the compute device is to operate outside of the cryogenic refrigerator. 
     Example 16 includes the subject matter of Example 15, and wherein to generate the control signal comprises generate a digital signal for an operation on the target qubit, the digital signal including a first frequency corresponding to the target qubit; apply a finite impulse response filter to the digital signal to filter a second frequency corresponding to a collateral qubit; and apply one of the two or more infinite impulse response filters to the digital signal to amplify frequencies near the second frequency. 
     Example 17 includes the subject matter of any of Examples 15 and 16, and wherein an amount of storage to store a template of the digital signal is independent of a number of infinite impulse response filters to be applied to the digital signal. 
     Example 18 includes the subject matter of any of Examples 15-17, and wherein a template of the digital signal is stored at a precision of less than or equal to 12 bits. 
     Example 19 includes the subject matter of any of Examples 15-18, and wherein the collateral qubit is spaced apart from the target qubit by less than a bandwidth of the control signal for the target qubit, wherein the quantum/classical interface circuitry is to transmit control signals for the target qubit and the collateral qubit on the same data cable. 
     Example 20 includes the subject matter of any of Examples 15-19, and wherein to apply the finite impulse response filter to the digital signal to filter the second frequency comprises to apply the finite impulse response filter to an in-phase and quadrature component of the digital signal, wherein to apply the one or the two or more infinite impulse response filters to the digital signal comprises to apply the one of the two or more infinite impulse response filters to the in-phase and quadrature component of the digital signal. 
     Example 21 includes the subject matter of any of Examples 15-20, and wherein to apply the one of the two or more infinite impulse response filters comprises to multiply a time sample of the digital signal by a real number less than one times a complex phase corresponding to the second frequency and add it to the next time sample of the digital signal. 
     Example 22 includes the subject matter of any of Examples 15-21, and wherein to apply the finite impulse response filter and the one of the two or more infinite impulse response filters comprises to increase a precision of time samples of the digital signal by at least 5 bits, wherein the quantum/classical interface circuitry is to truncate the digital signal after the finite impulse response filter and the one of the two or more infinite impulse response filters by at least 2 bits. 
     Example 23 includes the subject matter of any of Examples 15-22, and wherein to truncate the digital signal after the finite impulse response filter and the one of the two or more infinite impulse response filters comprises to truncate the digital signal to a precision of the digital signal before the finite impulse response filter and the one of the two or more infinite impulse response filters. 
     Example 24 includes the subject matter of any of Examples 15-23, and wherein the collateral qubit has a resonant frequency, wherein the second frequency corresponding to the collateral qubit corresponds to a frequency at least 10% higher or lower than the resonant frequency of the collateral qubit. 
     Example 25 includes the subject matter of any of Examples 15-24, and wherein the parameters of the two or more infinite impulse response filters control a depth of the corresponding filter and an inband attenuation of the corresponding filter. 
     Example 26 includes a compute device comprising a processor; a memory communicatively coupled to the processor; one or more computer-readable media comprising a plurality of instructions that, when executed by the processor, causes the compute device to determine a frequency of a target qubit; determine a frequency of a collateral qubit; determine a pulse to be sent to the target qubit; determine initial values for one or more parameters of a digital filter based on the frequency of the collateral qubit; and determine final values for the one or more parameters of the digital filter at least partly based on an effect on the collateral qubit of the pulse after application of the digital filter based on the initial values for the one or more parameters of the digital filter. 
     Example 27 includes the subject matter of Example 26, and wherein the initial values of the one or more parameters of the digital filter, in use, would result in a signal sent to the collateral qubit with the frequency of the collateral qubit filtered out, wherein the final values for the one or more parameters of the digital filter, in use, would result in a signal sent to the collateral qubit with a frequency at least 10% higher or lower than the frequency of the collateral qubit. 
     Example 28 includes the subject matter of any of Examples 26 and 27, and wherein the one or more parameters of the digital filter comprise one or more parameters of an infinite impulse response filter and one or more parameters of a finite impulse response filter. 
     Example 29 includes the subject matter of any of Examples 26-28, and wherein to determine the final values for the one or more parameters of the digital filter comprises to determine the final values for the one or more parameters of the digital filter based on a fidelity of a spin flip operation on the target qubit and a fidelity of no operation on the collateral qubit. 
     Example 30 includes a system comprising the compute device of claim 29, further comprising a quantum compute device comprising the target qubit and the collateral qubit, the quantum compute device to generate a signal with use of the final values for the one or more parameters of the digital filter; and transmit the signal to the target qubit and the collateral qubit. 
     Example 31 includes a method comprising determining a frequency of a target qubit; determining a frequency of a collateral qubit; determining a pulse to be sent to the target qubit; determining initial values for one or more parameters of a digital filter based on the frequency of the collateral qubit; and determining final values for the one or more parameters of the digital filter at least partly based on an effect on the collateral qubit of the pulse after application of the digital filter based on the initial values for the one or more parameters of the digital filter. 
     Example 32 includes the subject matter of Example 31, and wherein the initial values of the one or more parameters of the digital filter, in use, would result in a signal sent to the collateral qubit with the frequency of the collateral qubit filtered out, wherein the final values for the one or more parameters of the digital filter, in use, would result in a signal sent to the collateral qubit with a frequency at least 10% higher or lower than the frequency of the collateral qubit. 
     Example 33 includes the subject matter of any of Examples 31 and 32, and wherein the one or more parameters of the digital filter comprise one or more parameters of an infinite impulse response filter and one or more parameters of a finite impulse response filter. 
     Example 34 includes the subject matter of any of Examples 31-33, and wherein determining the final values for the one or more parameters of the digital filter comprises determining the final values for the one or more parameters of the digital filter based on a fidelity of a spin flip operation on the target qubit and a fidelity of no operation on the collateral qubit. 
     Example 35 includes the subject matter of any of Examples 31-34, and further including generating a signal with use of the final values for the one or more parameters of the digital filter; and transmitting the signal to the target qubit and the collateral qubit. 
     Example 36 includes a compute device comprising means for determining a frequency of a target qubit; means for determining a frequency of a collateral qubit; means for determining a pulse to be sent to the target qubit; means for determining initial values for one or more parameters of a digital filter based on the frequency of the collateral qubit; and means for determining final values for the one or more parameters of the digital filter at least partly based on an effect on the collateral qubit of the pulse after application of the digital filter based on the initial values for the one or more parameters of the digital filter. 
     Example 37 includes the subject matter of Example 36, and wherein the initial values of the one or more parameters of the digital filter, in use, would result in a signal sent to the collateral qubit with the frequency of the collateral qubit filtered out, wherein the final values for the one or more parameters of the digital filter, in use, would result in a signal sent to the collateral qubit with a frequency at least 10% higher or lower than the frequency of the collateral qubit. 
     Example 38 includes the subject matter of any of Examples 36 and 37, and wherein the one or more parameters of the digital filter comprise one or more parameters of an infinite impulse response filter and one or more parameters of a finite impulse response filter. 
     Example 39 includes the subject matter of any of Examples 36-38, and wherein the means for determining the final values for the one or more parameters of the digital filter comprises means for determining the final values for the one or more parameters of the digital filter based on a fidelity of a spin flip operation on the target qubit and a fidelity of no operation on the collateral qubit. 
     Example 40 includes the subject matter of any of Examples 36-39, and further including means for generating a signal with use of the final values for the one or more parameters of the digital filter; and means for transmitting the signal to the target qubit and the collateral qubit. 
     Example 41 includes a system comprising the compute device of claim 40, further comprising means for generating a signal with use of the final values for the one or more parameters of the digital filter; and means for transmitting the signal to the target qubit and the collateral qubit. 
     Example 42 includes one or more computer-readable media comprising a plurality of instructions stored thereon that, when executed, causes a compute device to determine a frequency of a target qubit; determine a frequency of a collateral qubit; determine a pulse to be sent to the target qubit; determine initial values for one or more parameters of a digital filter based on the frequency of the collateral qubit; and determine final values for the one or more parameters of the digital filter at least partly based on an effect on the collateral qubit of the pulse after application of the digital filter based on the initial values for the one or more parameters of the digital filter. 
     Example 43 includes the subject matter of Example 42, and wherein the initial values of the one or more parameters of the digital filter, in use, would result in a signal sent to the collateral qubit with the frequency of the collateral qubit filtered out, wherein the final values for the one or more parameters of the digital filter, in use, would result in a signal sent to the collateral qubit with a frequency at least 10% higher or lower than the frequency of the collateral qubit. 
     Example 44 includes the subject matter of any of Examples 42 and 43, and wherein the one or more parameters of the digital filter comprise one or more parameters of an infinite impulse response filter and one or more parameters of a finite impulse response filter. 
     Example 45 includes the subject matter of any of Examples 42-44, and wherein to determine the final values for the one or more parameters of the digital filter comprises to determine the final values for the one or more parameters of the digital filter based on a fidelity of a spin flip operation on the target qubit and a fidelity of no operation on the collateral qubit. 
     In the foregoing, a detailed description has been given with reference to specific example embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. Furthermore, the foregoing use of embodiment(s) and other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment.