Patent Publication Number: US-2010117880-A1

Title: Variable sized aperture window of an analog-to-digital converter

Description:
This application is a divisional of co-pending U.S. application Ser. No. 11/800,708, filed May 7, 2007 by the same inventors (issued Aug. 11, 2009 as U.S. Pat. No. 7,573,409), which claims priority to U.S. application Ser. No. 11/726,739, filed Mar. 22, 2007 by the same inventors (issued May 5, 2009 as U.S. Pat. No. 7,528,756), both of which are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of computers and computer processors, and more particularly to analog-to-digital converters (ADCs). 
     2. Description of the Background Art 
     An analog-to-digital converter (ADC) is an electronic circuit that converts continuous signals to discrete digital numbers. Typically, an ADC is an electronic device that converts an input analog voltage to a digital number. 
     The analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter, and is typically reported as the number of samples per second (sps). 
     A continuously varying bandlimited signal can be sampled at intervals of time T, the sampling time, and measured and stored. The original signal can then be exactly reproduced from the discrete-time values by an interpolation formula. However, this reproduction is only possible if the sampling rate is higher than twice the highest frequency of the signal. This is sometimes referred to as the Shannon-Nyquist sampling theorem. Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time, called the conversion time, within which the converter performs a conversion. 
     It is often desirable to be able to sample analog signals in an integrated circuit (IC) at very high frequencies, for example in the range of several gigahertz (GHz). However, certain types of ICs are made with older semiconductor manufacturing and material technology that is capable of sampling signals only at lower frequencies, for example in the range of &lt;1-2 GHz. 
       FIG. 1  is a diagrammatic representation of an example of an analog-to-digital (A-to-D) sampling system  100  as is currently known in the art. Embedded in chip  101  is the A-to-D block  102 . A-to-D block  102  has a data output  105 , typically, but not necessarily a parallel bus, and a sampling frequency control  104 , which is used to sample input signal  103 . The highest frequency component of the input component is f, and the sampling frequency f s  must be at least twice the frequency of f i , preferably 2.2 times the frequency of f i  for sampling that supports functions such as Fourier Transformations (FT) or Fast Fourier Transformations (FFT), etc. Therefore, if the desired input frequency f i  is in the 10 GHz range, the chip must be able to clock the sampling frequency f s  at approximately 20-22 GHz, based on the Nyquist Frequency. Building a chip with such a high sampling frequency is more costly, and the architecture of such chips does not permit embedding of large data functions such as CPUs, memory, etc. in such a chip. 
     Several analog-to-digital conversion methods are known.  FIG. 1A  is a schematic representation of a sample and hold circuit diagram for an ADC, which is also called a track and hold circuit. When the sample and hold switch  110  is open, the last instantaneous value of the input voltage is held on the sample and hold capacitor  111 . When the sample and hold switch  110  is closed, the circuit is in track mode. Buffers  112  on the input and output isolate the sample and hold capacitor  111 . A sample and hold ADC is simple and reliable, but is limited in its sampling frequency rate and it has a high error probability. 
     A second analog-to-digital conversion method is that which utilizes a phase detector ADC. A phase detector generates a voltage signal which represents the difference in phase between two signal inputs. When the two compared signals are completely in phase, the two equal inputs to an XOR gate will output a constant level of zero. With a one degree phase difference, the XOR gate will output a 1 for the duration of the signals being different ( 1/360 th  of the cycle). When the signals are 180 degrees apart, the XOR gate puts out a steady 1 signal. Integration of the output signal results in an analog voltage proportional to the phase difference. A phase detector contains a number of XOR gates that simultaneously measure a number of phase differences of the input signal. This has the advantage of being a fast acting device, but has the disadvantage of being a large power consumption device. 
     A third analog-to-digital conversion method is that which utilizes a flash ADC, which is also called a parallel ADC.  FIG. 1B  is a schematic representation of a flash ADC circuit diagram. A flash ADC is formed of a series of comparators  120 , where each comparator  120  compares the input signal to a unique reference voltage. The comparator  120  outputs connect to the inputs of a priority encoder circuit  121 , which then produces a binary output  122 . As the analog input voltage exceeds the reference voltage at each comparator  120 , the comparator  120  outputs will sequentially saturate to a high state. The priority encoder  121  generates a binary number based on the highest order active input, ignoring all other active inputs. The flash ADC is efficient in terms of speed, but contains a large number of components. For example, a three-bit flash ADC requires eight comparators, a four-bit version requires 16 comparators, and an eight-bit version requires 256 comparators. 
     A fourth analog-to-digital conversion method is a successive approximation ADC, schematically shown in  FIG. 1C . The successive approximation ADC uses a successive approximation register (SAR)  130  as a sequence counter. This SAR  130  counts by trying all values of bits starting with the most significant bit (MSB) and finishing at the least significant bit (LSB). Throughout the count process, the SAR  130  monitors the comparator&#39;s output to see if the binary count is less than or greater than the analog signal input, and then adjusts the bit values accordingly. Different values of bits are tried from MSB to LSB to get a binary number that equals the original decimal number. The digital-to-analog converter (DAC)  131  output converges on the analog signal input much faster than with a regular sequence counter. The stoichastic renormalization group (SRG)  132  acts as a decimal to binary converter. The successive approximation ADC is a faster device, but has the disadvantages of high power consumption and a large number of components. 
     Various approaches have been taken to find an economical system that can sample high frequency input rates. In an article entitled,  Design of a High - Performance Analog - to - Digital Converter , by Kevin Nary, published in CSD Magazine in October 1998, Nary discloses a folding and interpolating 8-bit 2-Gsps ADC. The number of comparators required for a 4-bit ADC is reduced from fifteen to six when switching from a flash to a folding architecture. This ADC increases the analog bandwidth and the maximum sample rate and consumes less power than a flash architecture ADC. One method of achieving a folding function uses cross-coupled, differential amplifiers, where a single fold is achieved with two cross-coupled, differential amplifiers. By adding more resistors and differential pairs, the number of folds may be increased. Nary reported results of a 2 GHz sampling frequency with 98 MHz input frequency. 
     Another approach has been disclosed in an article entitled,  Capturing Data from Gigasample Analog - to - Digital Converters , by Ian King, published in I/O Magazine in January 2006, which discloses a method of de-multiplexing the digital output. For a 1.5 GHz sample rate, the conversion data will be output synchronous to a 750 MHz clock, where the data is presented to the outputs on both the rising and falling edges of the clock. Two latches are then used, wherein one latch is clocked on the rising edge of the phase-locked data clock and a second latch is clocked using a signal that is 180 degrees out of phase. This reduces the output to 375 MHz. After latching the incoming data, the clock domain is shifted using an intermediate set of latches so that all of the data can be clocked into a memory array on the same clock edge, which de-multiplexes the data rate to 187.5 MHz. A single-channel device can be put into a dual-edge sampling mode to increase the sampling speed from 1.5 Gsps to 3.0 Gsps, which increases the number of output data bits from 8 to 16. A system and method are clearly needed in which much higher sampling frequencies than 2-3 GHz can be converted. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to adequately sample a very high frequency input analog signal using circuitry which, otherwise might not be able to sample at a sufficiently high rate. 
     An embodiment of the presently described invention includes a substrate with several ADCs and central processing units (CPUs), and a distributed sampling system. Each ADC works in conjunction with a designated CPU to form an ADC system. Each individual ADC system may contain conventional devices formed from 0.18 micron silicon, as an example. In this example, such individual systems are capable of sampling signals in the range of 1-2 GHz or less. 
     The description of the present invention illustrates how multiple conventional devices can be used to adequately sample a very high frequency input signal. A timing signal is passed through a distributed sampling system, also called a delay sampling system or a relay sampling system. When the timing signal reaches a first designated point along the distributed sampling system, a first ADC samples an input signal. When the timing signal reaches a second designated point along the distributed sampling system, a second ADC samples the input signal. The timing signal continues through the distributed sampling system until an established number of samplings have been taken by the same established number of ADC systems. 
     In the case when the devices are on a single chip, as in the present example, the timing signal is passed along the chip through the distributed sampling system. The occurrence of each subsequent sampling occurs at a clocked amount of time after the previous sampling. This is achieved by a plurality of sequential sampling prompts or taps originating from the distributed sampling system as the timing signal travels through the system. This results in cumulative samplings of the high frequency input signal by several ADCs, such that an adequate sampling necessary for optimum Nyquist-Shannon sampling is achieved. For example, if it is desired to adequately sample an input signal of 10 GHz using conventional systems capable of only 1 GHz sampling, then 20 ADC systems would be necessary in order to sequentially sample the input analog signal. In the present example, each ADC system obtains a sampling at a clocked 50 psec interval after the previous sampling. The sampling results of all 20 ADC systems are combined to obtain a result that produces essentially the same output as a single ADC system that is capable of sampling at 20 GHz. 
     Several distributed sampling systems are described. One such distributed sampling system includes several elongated trace patterns or additional lengths of wire, which are electrically interconnected in series. A timing signal travels through a first additional length of wire, after which a timing signal tap or prompt causes a sampling of the input signal to be taken by a first ADC system; this occurs at a specified period of time, given by Δt. The timing signal continues through a second additional length of wire, after which a timing signal tap or prompt causes a second sampling of the input signal to be taken by a second ADC system; this occurs after a second period of time, Δt. The timing signal continues through an established number of lengths of wire, which causes a cumulative sampling from the same established number of ADC systems. The results of the sequential samplings are a series of sequential digital output values from a plurality of ADCs. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. 
     Another example of a distributed sampling system includes a specified permittivity material device, such as a SAW device. The material of the device determines the rate at which a timing signal travels through it. Samples of an input analog signal are taken by a plurality of ADC systems when a timing signal reaches a plurality of equidistant points along the device. The results of the sequential samplings are a series of sequential digital output values from a plurality of ADCs. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. 
     Still another example of a distributed sampling system uses a sequencer or multiplier, such that a timing signal is multiplied a set number of times in order to produce an incremental period of time, Δt for each stage. The ADC systems sample an input analog signal after each period of time, Δt. The input signal sampling results from the multiplier sampling system are a series of sequential digital output values from a plurality of ADCs. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. 
     An example of an ADC differential op amp circuit, which provides large common mode rejection is also described. By sampling the input signal out of phase, the input signal is completely differentiated and set apart from the background noise. This provides a cleaner signal, and therefore more accurate sampling results. 
     Yet another example of an ADC circuit discloses an A-to-D cell, which is based on a voltage controlled oscillator (VCO) circuit connected to an input. The VCO output goes into a counter, where the output is then compared to, or timed with a reference frequency through a gate, such as an XOR gate. The output then connects to a CPU, which also controls resets of the counter. 
     An example of a variable sized aperture window sampling system is also described. This example is achieved through the utilization of a variable aperture clock, such as a resistor capacitor differentiator comprised of a voltage controlled resistor and a capacitor. This variable aperture clock can modify the pulse width of a sample pulse to form a narrower pulse width, and therefore a faster sampling rate. This variable sized aperture window sampling system can be used by itself for ADC sampling, or it can be combined with any of the previously described multiple ADC distributed sampling systems. 
     These and other objects and advantages of the present invention will become clear to those skilled in the art in view of the description of modes of carrying out the invention, and the industrial applicability thereof, as described herein and as illustrated in the several figures of the drawings. The objects and advantages listed are not an exhaustive list of all possible advantages of the invention. Moreover, it will be possible to practice the invention even where one or more of the intended objects and/or advantages might be absent or not required in the application. 
     Furthermore, those skilled in the art will recognize that various embodiments of the present invention may achieve one or more, but not necessarily all, of the described objects and/or advantages. Accordingly, the objects and/or advantages described herein are not essential elements of the present invention, and should not be construed as limitations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagrammatic view of a conventional ADC system; 
         FIG. 1A  is a circuit diagram of a sample and hold ADC; 
         FIG. 1B  is a circuit diagram of a flash ADC; 
         FIG. 1C  is a circuit diagram of a successive approximation ADC; 
         FIG. 2  is a block diagrammatic view of a general ADC system according to the present invention; 
         FIGS. 3   a - 3   b  are representations of the timing relationship between samplings taken of an input analog signal and taps made in a timing signal distributed line according to a first embodiment of the presently described invention; 
         FIG. 4  is a representation of the timing relationship between samplings taken of an input analog signal and taps made in a timing signal distributed line according to a second embodiment of the presently described invention; 
         FIGS. 5-6  are block diagrammatic views of a third embodiment of the presently described invention; 
         FIGS. 7   a - 7   b  are circuit diagrams for an ADC that could be used with the presently described invention; 
         FIG. 8  is a diagrammatic view of a computer array, according to the present invention; 
         FIG. 9  is a detailed diagram showing a subset of the computers of  FIG. 8  and a more detailed view of the interconnecting data buses of  FIG. 8 ; 
         FIG. 10  is a block diagram depicting a general layout of a stack computer; 
         FIGS. 11   a - 11   c  are diagrammatic views of an ADC and computer system array according to the present invention; 
         FIG. 12   a  is a circuit diagram of an ADC sampling system according to the present invention; 
         FIG. 12   b  shows input voltage vs. output frequency characteristics of a CMOS silicon process; and 
         FIG. 13  is a circuit diagram of an enhanced ADC sampling system according to the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     This invention is described with reference to the figures, in which like numbers represent the same or similar elements. While this invention is described in terms of modes for achieving this invention&#39;s objectives, it will be appreciated by those skilled in the art that variations may be accomplished in view of these teachings without deviating from the spirit or scope of the presently claimed invention. 
     The embodiments and variations of the invention described herein, and/or shown in the drawings, are presented by way of example only and are not limiting as to the scope of the invention. Unless otherwise specifically stated, individual aspects and components of the invention may be omitted or modified for a variety of applications while remaining within the spirit and scope of the claimed invention, since it is intended that the present invention is adaptable to many variations. 
       FIG. 2  shows an example of an ADC system  200  according to the present invention. An input signal  204  is passed into a number of analog-to-digital converter cells  202   a  through  202   n  of a chip  201 . An external sampling clock  205  is shown in this example, but an internal clock could have been utilized as well. The sampling clock  205  is run at a substantially lower frequency, for example, 10 or 20 times lower frequency, than the intended sampling rate. By providing sequential time periods from time distribution apparatus  206   a  through  206   n , it is possible to increase the net sampling rate by n number of times. In this example, the time periods are provided by an external source, although as discussed above, an internal timing source could also be utilized. If the input signal  204  with a frequency up to 10 GHz is to be accurately sampled, then a sampling clock  205  at 20 or 22 GHz would be necessary for optimum Nyquist-Shannon sampling. However, in the present inventive system, the sampling clock  205  can run at, for example, 1 GHz for n=20 or 22, respectively. The time periods, provided by the time distribution apparatus  206   a  through  206   n  would be in an increment of 1/20, 1/22, or similar increment of the sampling frequency, so that each ADC  202  would sample the input signal  204  at a slightly delayed point, resulting in a sampling that would be equivalent to using a single ADC, sampling at a rate of 20 or 22 GHz. The time periods, provided by the time distribution apparatus  206   a  through  206   n  occur as a result of tap line connections  207   a  through  207   n  between an individual distribution station (such as  206   a ) and a corresponding individual ADC (such as A/D  202   a ). When a timing signal (produced by sampling clock  205 ) travels through a plurality of serially connected distribution stations or distribution apparatus  206   a  through  206   n  a series of taps or sampling prompts are sent through tap line connections  207   a  through  207   n  to corresponding ADCs  202   a  through  202   n , respectively. 
     Such an approach would require a multitude of ADCs or A-to-D channels  202 , for example, in this case at least 20 or 22, but it would allow use of an older technology chip  201 , for example 0.18 micron silicon, and it would permit sampling of signals running in the 10 GHz range or thereabouts. By increasing the number of A-to-D channels  202  even more, the sampled signal frequency (or its highest Fourier Transform component) could be even further increased. 
     Names of items  202   a  through  202   n  as ADCs, converter cells, or channels have been used in this example interchangeably. Typically, to be able to process the amount of data without losing sample data during processing, each A-to-D channel  202  must have sufficient data transfer capabilities, for example its own CPU  203   a  through  203   n  corresponding to A-to-D channels  202   a  through  202   n . 
     The time period between each ADC sampling of the input signal could be achieved in various ways, as exemplified by the following embodiments.  FIG. 3   a  discloses a time relationship between samplings taken of an input signal  301  and taps in a trace pattern  303  of a time distributed sampling system in a first embodiment of the invention. The trace pattern  303  contains a plurality of elongated wires connected in series. This time distributed sampling system has a plurality of ADC systems, wherein each ADC system comprises an ADC  202  and an associated central processing unit (CPU)  203 , as discussed previously in relation to  FIG. 2 . When a timing signal  306  travels through a first length of wire  303   a  to a tap point of W 1 , a prompt to sample the input signal  301  after a measurable amount of time, given by Δt  304  is made. This timing is represented as ADC sampling point C 1 . As the timing signal  306  continues through a second length of wire  303   b  to a second tap point of W 2 , a prompt to sample the input signal  301  after a second period of time, Δt is made. This timing is represented by ADC sampling point C 2 . A separate ADC system samples the input signal  301  after the timing signal  306  reaches each trace pattern  303  at tap points, W 1  through W n  for each tap in the distribution line. The results of the sequential samplings are a series of sequential digital output values from a plurality of ADCs. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. 
     A more detailed explanation follows with reference to  FIG. 3   a . A timing signal  306  passes through a first length of wire,  303   a  to a tap point, W 1 . At that point in time, an input signal  301  is sampled by a first ADC system, represented in time by the ADC sampling point, C 1 . When the timing signal  306  travels through a second length of wire,  303   b  to a tap point represented by W 2 , the input signal  301  is sampled by a second ADC system, at the ADC sampling point, C 2 . The above described distributed sampling system continues to sample the input signal  301  at ADC sampling points  302 , designated in time by C 1 , C 2 , etc. The input signal  301  is sampled after each sequential time period, Δt  304  as the timing signal  306  travels through the plurality of lengths of wire  303 . A number of ADC systems are established on a chip in order to adequately sample an input signal  301  in order to meet the Nyquist-Shannon requirement. 
     Consider the following example, which is given to further clarify the present invention, wherein the given example is not to be construed as a limiting feature. If, for example, an input signal  301  of 10 GHz frequency was to be sampled, then the time difference  304  between ADC sampling points  302  would need to be at least 50 psec to meet the Nyquist-Shannon requirement for an adequate sampling rate of a 10 GHz input signal. Each successive ADC system would sample the input signal  301  at the sampling points C 1 , C 2 , etc., wherein each sampling would occur at 50 psec after the previous ADC sampling. The ADC sampling points  302  correspond in time to successive tap points of W 1 , W 2 , etc. along the trace pattern  303 . If each ADC system was capable of capturing or taking a sample every 1 nsec, then a total of 20 ADC systems would be necessary to adequately sample an incoming 10 GHz signal. In this example, the distributed sampling system using multiple lengths of interconnected wires of the presently described invention is equivalent to using a single ADC, which is capable of sampling an input signal of 10 GHz at a sampling rate of 20 gsps. 
       FIG. 3   b  discloses a time relationship between samplings taken of an input signal  301  and taps made in a connected series of inverter pairs  305  of a time distributed sampling system in a second embodiment of the invention. Each clocked trace pattern  303  of  FIG. 3   a  is replaced with a pair of inverters  305  in  FIG. 3   b . A timing signal  306  travels through a series of connected inverter pairs  305 . When the timing signal  306  travels through a first inverter pair  305   a , a prompt to sample the input signal  301  after a first time period, Δt  304  is made, which coincides with the ADC sampling point C 1 . As the timing signal  306  continues through a second inverter pair  305   b , a prompt to sample the input signal  301  after a second time period, Δt  304  is made, which coincides with the ADC sampling point, C 2 . A separate ADC system samples the input signal  301  at each of the ADC sampling points, C 1  through C n , which occurs when the timing signal  306  travels through each inverter pair at points designated by W 1  through W n , respectively. The results of the sequential samplings are a series of sequential digital output values from a plurality of ADCs. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. 
     A more detailed explanation follows with reference to  FIG. 3   b . When a timing signal  306  travels through a first inverter pair,  305   a  to a tap point represented by W 1 , an input signal  301  is sampled by a first ADC system at a first ADC sampling point, designated in time by C 1 . When the timing signal  306  travels through a second inverter pair,  305   b  to a tap point represented by W 2 , the input signal  301  is sampled by a second ADC system at a second ADC sampling point, C 2 . The above given distributed sampling system continues to sample the input signal  301  as the timing signal  306  travels through the plurality of inverter pairs  305 . As the timing signal  306  travels through each of the inverter pairs  305 , the input signal  301  is sampled after each sequential time period, Δt  304  at each ADC sampling point  302 . A number of ADC systems are established on a chip in order to adequately sample an input signal  301  in order to meet the Nyquist-Shannon requirement. 
       FIG. 4  discloses a time relationship between samplings taken of an input analog signal  405  and line taps made in a specific permittivity material device  401  in a third embodiment of the invention. The time distribution sampling is achieved through the use of a specific permittivity material device  401 , such as a surface acoustic wave (SAW) device. An input signal  405  is sampled after each measurable time period, Δt  403  as a timing signal  406  travels past each equi-distant point, given by S 1  through S n  along the device  401 . 
     The specific permittivity material device distributed sampling system represented by  FIG. 4  works similar to the trace distributed sampling system of  FIG. 3   a . A separate ADC system contains an ADC and a corresponding CPU, as previously described with reference to  FIG. 2 . Each sequential ADC system samples the input signal  405 , represented by ADC sampling points  402  when a timing signal  406  reaches each sequential equi-distant point along the device  401 , corresponding to points S 1  through S n . As the timing signal  406  travels through the device  401 , a prompt to sample the input signal  405  after each incremental time period, Δt  403  is made, wherein the value of Δt  403  is determined by the specific material of the device  401 . When the timing signal  406  reaches a first sampling point  402  given by S 1 , a prompt to sample the input signal  405  by a first ADC system at a first ADC sampling point, C 1  is made. When the timing signal  406  reaches a second sampling point, S 2  within the device  401  after a second time period, Δt  403  a second ADC system is prompted to sample the input signal  405  at the corresponding second ADC sampling point, C 2 . The above described distributed sampling system continues to sample the input signal  405  at ADC sampling points  402 , which correspond in time to points, S 1  through S n  of the device  401 . The results of the sequential samplings are a series of sequential digital output values from a plurality of ADCs. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. 
     In an example of using an input signal  405  of 10 GHz, a timing signal  406  travels to a first point, given by S 1  within the device  401 . At this point, a first ADC system is prompted to sample the input signal  405  at the first ADC sampling point C 1  after a first time period  403  of 50 psec. When the timing signal  406  travels to a second point S 2  within the device  401 , a second ADC system is prompted to sample the input signal  405  at a second sampling point, C 2  which will occur after a second time period  403  of 50 psec. If each ADC system sampled the input signal  405  at a rate of 1 nsec, then 20 ADC systems would be required to adequately sample an input signal  405  of 10 GHz. In this example, the distributed sampling system using a specific permittivity material device of the presently described invention is equivalent to using a single ADC, which is capable of sampling an input signal of 10 GHz at a sampling rate of 20 gsps. 
     A fourth embodiment discloses a sequencer or multiplier distributed sampling system  601 , and is described with reference to  FIG. 5 . An example of a sequencer distribution sampling system  601  could use an emitter coupled logic (ECL) as a sequencer  501 . The sequencer  501  comprises a group of triggers  508  which are represented by w 1  through w n . Each trigger  508  is connected to an ADC  502 , each of which is then connected to an associated CPU  506 . A timing signal  507  enters the sequencer  501 , then each stage sequences or multiplies the timing signal  507  by the same incremental amount, given by Δt  503 . Therefore, as a pulse  504  travels through a first ADC trigger, w 1  the input signal  505  is sampled by ADC 1 . After a second time period Δt  503 , a pulse  504  travels through a second ADC trigger, w 2  wherein the input signal  505  is sampled by ADC 2 . The above described distributed sampling system continues to sample the input signal  505  by utilizing n number of triggers, w 1  through w n  and using ADC 1  through ADC n  converters, respectively. The sampling results are processed by n number of associated CPUs  506 . The results of the sequential samplings are a series of sequential digital output values from a plurality of ADCs. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. An important feature of the sequencer  501  is that time between each trigger  508  can be varied. 
     In an example of a 10 GHz input signal  505 , the sequencer  501  comprises 20 triggers  508 , as represented by w 1  through w 20 . The input analog signal  505  will be sequentially sampled at intervals of 50 psec time periods, Δt  503 . For example, ADC, will sample the input analog signal  505  when a pulse  504  travels through a first ADC trigger, w 1  after a first time period, Δt  503  of 50 psec. Then ADC 2  will sample the input analog signal  505  when a pulse  504  travels through a second ADC trigger, w 2  after a second time period, Δt  503  of 50 psec. If each ADC  502  is capable of sampling an input analog signal  505  at a rate of 1 nsec, then 20 triggers  508  along with 20 associated ADCs  502  and 20 associated CPUs  506  would be necessary to adequately sample a 10 GHz input signal  505  at a sampling rate of 20 gsps. In this example, the distributed sampling system using multiple ADCs with a sequencer or multiplier of the presently described invention is equivalent to using a single ADC, which is capable of sampling an input signal of 10 GHz at a sampling rate of 20 gsps. 
       FIG. 6  is a block diagram of a sequencer or multiplier distributed sampling system  601  which was described with reference to  FIG. 5 , with the addition of a clock generating block  602 . The clock generating block  602  could be internal or external, and could include, but is not limited to a phase locked loop (PLL), a delay locked loop (DLL), a voltage controlled oscillator (VCO), a ring oscillator, a crystal oscillator, or other type of oscillator.  FIG. 6  also shows a timing signal  603 . 
       FIG. 7   a  is a circuit diagram  707  of an ADC that could be used with the previously described inventions, which utilizes differential op amps. The differential op amp system that is shown in  FIG. 7   a  has two input sources  701  which are utilized in conjunction with op amps  702   a  and  702   b , wherein the op amp  702   b  is a voltage to current driver with a selectable gain multiplier. This configuration provides large common mode rejection for a very accurate reproduction of the input signal. The system of  FIG. 7   a  further shows a counter  704 , a CPU  705 , and a digital output signal  706 . 
       FIG. 7   b  is a circuit diagram  707  of an ADC which comprises a single-ended voltage controlled oscillator  703 . The remaining elements are the same as for  FIG. 7   a . The inverter system of  FIG. 7   a  has the advantage of separating out the desired input signal  701  to be sampled from the undesirable background noise;  FIG. 7   b  has no noise immunity. However, the inverter system of  FIG. 7   b  requires only one pin connection, whereas the inverter system of  FIG. 7   a  requires two pin connections. 
     The ADC circuit diagrams of  FIGS. 7   a  and  7   b  could be used with any of the previously described ADC/CPU distributed sampling systems for sampling an input analog signal. 
     The above described ADC/CPU distributed sampling systems could also be integrated with any of various architectures well known to the inventor. One mode for carrying out the invention is through utilizing an array of individual computers. An array is depicted in a diagrammatic view in  FIG. 8  and is designated therein by the general reference character  10 . The computer array  10  has a plurality (twenty four in the example shown) of computers  12  (sometimes also referred to as “cores” or “nodes” in the example of an array). In the example shown, all of the computers  12  are located on a single die  14 . According to the present invention, each of the computers  12  is a generally independently functioning computer, as will be discussed in more detail hereinafter. The computers  12  are interconnected by a plurality (the quantities of which will be discussed in more detail hereinafter) of interconnecting data buses  16 . In this example, the data buses  16  are bidirectional asynchronous high speed parallel data buses, although it is within the scope of the invention that other interconnecting means might be employed for the purpose. In the present embodiment of the array  10 , not only can data communication between the computers  12  be asynchronous, but the individual computers  12  can also operate in an internally asynchronous mode. The individual computers  12  operate asynchronously, which saves a great deal of power since each computer  12  will use essentially no power when it is not executing instructions, and since there is no clock running therein. 
     One skilled in the art will recognize that there will be additional components on the die  14  that are omitted from the view of  FIG. 8  for the sake of clarity. Such additional components include power buses, external connection pads, and other such common aspects of a microprocessor chip. 
     Computer  12   e  is an example of one of the computers  12  that is not on the periphery of the array  10 . That is, computer  12   e  has four orthogonally adjacent computers  12   a ,  12   b ,  12   c  and  12   d . This grouping of computers  12   a  through  12   e  will be used, by way of example, hereinafter in relation to a more detailed discussion of the communications between the computers  12  of the array  10 . As can be seen in the view of  FIG. 8 , interior computers  12  such as computer  12   e  will have four other computers  12  with which they can directly communicate via the buses  16 . In the following discussion, the principles discussed will apply to all of the computers  12 , except that the computers  12  on the edge of the array  10  will be in direct communication with only three other computers  12 , and the corner computers  12  will be in direct communication with only two other computers  12 . 
       FIG. 9  is a more detailed view of a portion of  FIG. 8  showing only some of the computers  12  and, in particular, computers  12   a  through  12   e , inclusive. The view of  FIG. 9  also reveals that the data buses  16  each have a read line  18 , a write line  20  and a plurality (eighteen, in this example) of data lines  22 . The data lines  22  are capable of transferring all the bits of one eighteen-bit instruction word simultaneously in parallel. 
     According to the present inventive method, a computer  12 , such as the computer  12   e  can set high one, two, three or all four of its read lines  18  such that it is prepared to receive data from the respective one, two, three or all four adjacent computers  12 . Similarly, it is also possible for a computer  12  to set one, two, three or all four of its write lines  20  high. 
     When one of the adjacent computers  12   a ,  12   b ,  12   c  or  12   d  sets a write line  20  between itself and the computer  12   e  high, if the computer  12   e  has already set the corresponding read line  18  high, then a word is transferred from that computer  12   a ,  12   b ,  12   c  or  12   d  to the computer  12   e  on the associated data lines  22 . Then, the sending computer  12  will release the write line  20  and the receiving computer ( 12   e  in this example) pulls both the write line  20  and the read line  18  low. The latter action will acknowledge to the sending computer  12  that the data has been received. Note that the above description is not intended necessarily to denote the sequence of events in order. In actual practice, the receiving computer may try to set the write line  20  low slightly before the sending computer  12  releases (stops pulling high) its write line  20 . In such an instance, as soon as the sending computer  12  releases its write line  20 , the write line  20  will be pulled low by the receiving computer  12   e.    
     Whenever a computer  12  such as the computer  12   e  has set one of its write lines  20  high in anticipation of writing it will simply wait, using essentially no power, until the data is “requested”, as described above, from the appropriate adjacent computer  12 , unless the computer  12  to which the data is to be sent has already set its read line  18  high, in which case the data is transmitted immediately. Similarly, whenever a computer  12  has set one or more of its read lines  18  to high in anticipation of reading it will simply wait, using essentially no power, until the write line  20  connected to a selected computer  12  goes high to transfer an instruction word between the two computers  12 . 
     As discussed above, there may be several potential means and/or methods to cause the computers  12  to function as described. However, in this present example, the computers  12  so behave simply because they are operating generally asynchronously internally (in addition to transferring data there-between in the asynchronous manner described). That is, instructions are generally completed sequentially. When either a write or read instruction occurs, there can be no further action until that instruction is completed (or, perhaps alternatively, until it is aborted, as by a “reset” or the like). There is no regular clock pulse, in the prior art sense. Rather, a pulse is generated to accomplish a next instruction only when the instruction being executed either is not a read or write type instruction (given that a read or write type instruction would require completion, often by another entity) or else when the read or write type operation is, in fact, completed. 
       FIG. 10  is a block diagram depicting the general layout of an example of one of the computers  12  of  FIGS. 8 and 9 . As can be seen in the view of  FIG. 10 , each of the computers  12  is a generally self contained computer having its own RAM  24  and ROM  26 . As mentioned previously, the computers  12  are also sometimes referred to as individual “nodes”, given that they are, in the present example, combined on a single chip. 
     Other basic components of the computer  12  are a return stack  28  including an R register  29 , an instruction area  30 , an arithmetic logic unit (“ALU” or “processor”)  32 , a data stack  34  and a decode logic section  36  for decoding instructions. One skilled in the art will be generally familiar with the operation of stack based computers such as the computers  12  of this present example. The computers  12  are dual stack computers having the data stack  34  and the separate return stack  28 . 
     In this embodiment of the invention, the computer  12  has four communication ports  38  for communicating with adjacent computers  12 . The communication ports  38  are further defined by the up port  38   a , the right port  38   b , the left port  38   c , and the down port  38   d . The communication ports  38  are tri-state drivers, having an off status, a receive status (for driving signals into the computer  12 ) and a send status (for driving signals out of the computer  12 ). If the particular computer  12  is not on the interior of the array ( FIG. 8 ) such as the example of computer  12   e , then one or more of the communication ports  38  will not be used in that particular computer, at least for the purposes described above. However, those communication ports  38  that do abut the edge of the die  14  can have additional circuitry, either designed into such computer  12  or else external to the computer  12  but associated therewith, to cause such communication port  38  to act as an external I/O port  39  ( FIG. 8 ). Examples of such external I/O ports  39  include, but are not limited to, USB (universal serial bus) ports, RS232 serial bus ports, parallel communications ports, analog to digital and/or digital to analog conversion ports, and many other possible variations. No matter what type of additional or modified circuitry is employed for this purpose, according to the presently described embodiment of the invention, the method of operation of the “external” I/O ports  39  regarding the handling of instructions and/or data received there from will be alike to that described, herein, in relation to the “internal” communication ports  38 . In  FIG. 8  an “edge” computer  12   f  is depicted with associated interface circuitry  80  (shown in block diagrammatic form) for communicating through an external I/O port  39  with an external device  82 . 
     In the presently described embodiment, the instruction area  30  includes a number of registers  40  including, in this example, an A register  40   a , a B register  40   b  and a P register  40   c . In this example, the A register  40   a  is a full eighteen-bit register, while the B register  40   b  and the P register  40   c  are nine-bit registers. Also depicted in block diagrammatic form in the view of  FIG. 10  is a slot sequencer  42 . 
     The data stack  34  and the return stack  28  are not arrays in memory accessed by a stack pointer, as in many prior art computers. Rather, the stacks  34  and  28  are an array of registers. The top two registers in the data stack  34  are a T register  44  and an S register  46 . The remainder of the data stack  34  has a circular register array  34   a  having eight additional hardware registers therein numbered, in this example S 2  through S 9 . One of the eight registers in the circular register array  34   a  will be selected as the register below the S register  46  at any time. The value in the shift register that selects the stack register to be below S cannot be read or written by software. Similarly, the top position in the return stack  28  is the dedicated R register  29 , while the remainder of the return stack  28  has a circular register array  28   a  having eight additional hardware registers therein (not specifically shown in the drawing) that are numbered, in this example R 1  through R 8 . 
     In addition to the registers previously discussed herein, the instruction area  30  also has an 18 bit instruction register  30   a  for storing an instruction word that is presently being used, and an additional 5 bit opcode register  30   b  for the particular instruction word presently being executed. 
     The previously described ADC/CPU distributed sampling systems could be integrated with the above described computer array, resulting in numerous system combinations of different type, size, and purpose. In addition, such systems could be processed as individual discrete components integrated together onto a substrate, or processed completely on a single chip, or a combination of the two processes. 
     The following description will give two examples of different ADC array possibilities, which are given to further clarify the present invention and are not to be construed as limiting features.  FIG. 11   a  shows a chip or die  14  with several computers or nodes  12 . The interior computers  12  are designated as general purpose computers (G)  94 , which are interconnected and therefore, can share resources there between as previously described. The periphery of the die  14  contains several ADCs (A)  95 . Each ADC (A)  95  has a dedicated computer, referred to as an ADC computer (C)  96 . Each ADC computer (C)  96  has access to any or all of the general purpose computers (G)  94 . The connections between the ADC computers (C)  96  may or may not be utilized. 
       FIG. 11   b  shows another embodiment of a die  14  with several computers  12 . ADCs (A)  95  are formed at the periphery of the die  14 , but there are no dedicated ADC computers (C)  96  as in  FIG. 11   a . Each ADC (A)  95  would have direct access to any or all of the interconnected general purpose computers (G)  94 . 
       FIG. 11   c  shows a die  14  with a total of forty computers  12 , wherein 20 computers  12  are ADCs (A)  95  and 20 computers  12  are general purpose computers (G)  94 .  FIG. 11   c  is an example of a die  14  which could be utilized in the previous examples of sampling a 10 GHz input analog signal. Each individual ADC was capable of sampling at a rate of 1 gsps; therefore, 20 such ADCs (A)  95  and 20 associated general purpose computers (G)  94  would be necessary to sample a 10 GHz input analog signal. 
       FIG. 12   a  is a circuit diagram of an ADC system  1200  according to another embodiment of the current invention. A-to-D cell  202  is based on a voltage controlled oscillator (VCO) circuit using VCO  1201  connected to input  204 . The VCO output goes into a counter  1202 , where the output is then compared to, or timed with a reference frequency  1203  through a gate, such as XOR gate  1204 . The output then connects to a CPU  203 , which also controls resets of the counter  1202  through line  1205 . 
     The ADC circuit diagram of  FIG. 12   a  has combined the advantages of the prior art ADC conversion methods that were previously discussed above, and decreased or eliminated their disadvantages. The ADC circuit diagram of  FIG. 12   a  has the simplicity and reliability of the sample and hold circuit of  FIG. 1A , and the speed and accuracy of the phase detector, flash ( FIG. 1B ), and successive approximation ( FIG. 1C ) circuits. The present inventive circuit of  FIG. 12   a  has a small number of components, and uses very little power compared to the fast circuits. The input  204  of the present inventive ADC circuit is not limited to voltage sources, and it is not frequency dependent. There is no limitation on the range of the VCO  1201 , and the counter  1202  is open to any speed or rate. 
       FIG. 12   b  shows as diagram  1211  characteristics of a VCO  1201  in a CMOS silicon process, such as 0.18 micron silicon. The input voltage range is from 0 to 1.8 volts, where the frequency moves from 1 GHz to 2 GHz. However, there is a narrow dynamic or useful range  1212  approximately 1 or 1.2 volts wide. Transfer curve  1213  shows the input voltage on the x-axis and the output frequency in GHz on the y-axis. 
       FIG. 13  shows an enhanced sampling system  1300  according to another embodiment of the present invention. In A-to-D converter cell  202 , the input line  204  connects to an optional input buffer  1307 . It then continues to an input sampling switch  1301 , which connects to sample-and-hold capacitor  1302 , whose voltage controls the VCO  1201 . This approach allows the oscillator to run at a stable frequency between samplings. VCO  1201 , in turn is connected to counter  1202 , as described above which then has connections to CPU  203 . CPU  203  also controls, in this example a sample pulse, which it sends to buffer  1306 . A variable aperture clock system, such as a resistor capacitor differentiator made of a voltage-controlled resistor  1304  and a capacitor  1305  is utilized, where the resistor  1304  is voltage-adjustable. The CPU  203  causes a differentiated, shorter pulse which is buffered in buffer  1303 , and the CPU  203  also controls the input sampling switch  1301 . By controlling the resistor voltage, the CPU  203  can modify the pulse width of the sampling period and create a smaller aperture window, and thereby increase the sampling rate. 
     The voltage controlled resistor  1304  and capacitor  1305  create a resistor capacitor differentiator, which determines the aperture window size or the variable rate for the input sampling switch  1301 . The CPU  203  modifies the pulse width of the sampling period by controlling the resistor  1304  voltage. The CPU  203  creates a differentiated, shorter pulse, and thereby controls the input sampling sample and hold switch  1301 . A shorter sample aperture window, which provides a shorter VCO  1201  leads to the ability to sample higher frequency input signals. A variable sample aperture window also resynchronizes the sampling phases back together again, via a resynchronizing circuit. 
     Modifying the pulse width affects the settling time, etc. of the capacitor, and thus affects the accuracy of the sampling. There is a trade-off between speed and accuracy, where a higher speed leads to a less accurate measurement. Therefore, resistor  1304  allows the system to have a software control (not shown) for accuracy running as code in CPU  203 . 
     The presently described invention of a variable width aperture window, which provides a variable sampling rate, can be used by itself or in combination with any of the previously described time distributed ADC sampling systems. Therefore, each ADC of a multiple ADC distributed sampling system could also comprise a variable aperture clock, such as a resistor capacitor differentiator to provide a shorter pulse and therefore, a shorter aperture window and a faster sampling rate. Likewise, the ADC variable rate aperture window sampling system could be used with any of the previously described multiple ADC distributed sampling system embodiments, including but not limited to the trace pattern embodiment described with reference to  FIG. 3   a , the inverter pair embodiment described with reference to  FIG. 3   b , the specific permittivity material device embodiment described with reference to  FIG. 4 , and the sequencer embodiment described with reference to  FIGS. 5 and 6 . 
     All of the above examples are only some of the examples of available embodiments of the present invention. Those skilled in the art will readily observe that numerous other modifications and alterations may be made without departing from the spirit and scope of the invention. Accordingly, the disclosure herein is not intended as limiting and the appended claims are to be interpreted as encompassing the entire scope of the invention.