Patent Publication Number: US-7725758-B2

Title: Multifunctional timer/event counter device and method of using such a device

Description:
PRIORITY CLAIM 
   The present application claims the benefit French Patent Application No. FR0512818, filed Dec. 16, 2005, which application is incorporated herein by reference in its entirety. 
   TECHNICAL FIELD 
   Embodiments of the invention relate in general to the domain of multifunctional timer/event counter circuits, commonly called “timers” by those skilled in the art. 
   BACKGROUND 
   The multifunctional timer/event counter device is a programmable circuit usually including a binary counter associated with a control register and a counter register. 
   For simplification and clarity reasons, the word “timer” will be used in the remainder of the description to refer to the “multifunctional timer/event counter device”. 
   The control register includes a binary number used to define the behavior of the timer counter. For example, one behavior of the counter may be to activate counting up or counting down on a rising front of a synchronization signal sent on a timer input, initialization of the counter to a value or reinitialization of the counter. 
   The counter register includes a binary number representative of the state of the counter. For example, this binary number may indicate an overflow to the capacity of the counter, the result of the comparison between the value of the counter and another value, or the value of the counter. 
   The timer is usually installed in a microcontroller and is used for example in particular to count, measure events or to generate signals with a variable cyclic ratio that can be used as a time base. 
   For example, the timer can be used to set up time intervals for data transmission. The timer counter is controlled by a clock signal, for example output by an oscillator installed in the microcontroller. The frequency of this clock signal may have been firstly divided by a divider also called a “prescaler” by those skilled in the art. 
   When the timer is used to count a number of events, it is clocked by signals representative of events to be counted sent to a timer input. 
   When used as a periodic starter timer, the timer generates constant frequency pulses but with a variable cyclic ratio, more frequently known as PWM (Pulse Width Modulation) to those skilled in the art. 
   In order to perform these functions, it is sometimes necessary to synchronize two timers, for example arranged on the same microcontroller. A first timer called the master timer is chosen to operate in master mode, and a second timer called the slave timer is chosen to operate in slave mode. In this configuration, the state of the master timer counter can be used to control the behavior of the slave timer counter. 
   For this purpose, some timers according to the prior art include specific inputs predefined and fixed by the manufacturer. These specific inputs may for example be an external clock input, a start counter input, an initialize counter input, an input for capture of the counter value in a register, etc. 
   However, the architecture of internal connections in each timer is physically fixed by the manufacturer. Thus, a signal sent to the start counter input will have the sole function of starting the counter, and can under no circumstances be used for example to initialize the counter or to give the order to capture the value of the counter in a register. Therefore, two signals have to be used to control starting and initializing the counter. 
   Since the architecture of existing microcontrollers is also physically fixed by the manufacturer, it is usually impossible to choose the signal generated by the master timer to control starting the slave timer. For example, the slave timer counter cannot be started until after an overflow of the master timer counter. 
   Similarly, if it is required to control the slave timer clock with a signal external to the micro controller, and then a signal with an output from the master timer, it is necessary to use two clock inputs on the slave timer or to make additional wiring on the input side of the slave timer. 
   SUMMARY 
   In this context, one embodiment of the invention is a multifunctional timer/event counter device unaffected by at least one of the limitations mentioned above. 
   According to one embodiment of the present invention, a multifunctional timer/event counter device includes a function module including at least a synchronization signal reception input and a reception input for at least a function control signal, the function module being capable of modifying the binary number as a function of at least the synchronization signal and the function control signal. 
   Thus, due to this arrangement, the device offers flexibility of how the synchronization signal reception input is used. For example, the input is no longer limited only to starting the counter of the device, and the function control can be used to assign a role to the synchronization signal, during the same process. Thus, a single synchronization signal can be used for example to start the counter, to initialize the counter, to capture the value of the counter, to stop the counter depending on the state of the synchronization signal, to control the count direction of the counter, namely to count up or to count down. 
   In one embodiment of the invention, the device also includes a first selection module including at least one plurality of inputs, and a reception input of a first selection control signal. This first selection module can be used to connect one input among the plurality of inputs of the first selection module, to the synchronization signal reception input of the function module, according to the first selection control signal. 
   The addition of this first selection module enables the device to receive signals with different frequencies, for example. Thus, two signals may for example be used to control starting of the counter. Therefore each behavior of the counter is no longer related only to one input of the first selection module. 
   For example, the device could also be made to comprise a second selection module including at least a synchronization output, a plurality of reception inputs of signals representative, at least for some of the signals at least a state of the counter, and signals defining, at least for some, at least the behavior of the counter, and a reception input for at least a second selection control signal. This second selection module can be used to connect one input among the plurality of inputs of the second selection module to the synchronization output according to the second selection control signal. 
   Advantageously, the device also includes a timer means capable of generating a signal defining at least the behavior of the counter based on the binary number and an event of the clock signal. 
   This timer means may for example be a D type flip-flop active on the rising front of the clock signal. 
   The device may also include at least one first means of activating the function module. 
   The device may also include at least one second means of activating the first selection module. 
   A multifunctional timer/event counter device like that described above may be included in a microcontroller. 
   The synchronization signal may be internal or external to the microcontroller. 
   An embodiment of the invention also relates to a method of using a multifunctional timer/event counter device including at least a counter controlled by a clock signal, and a control register including at least a binary number that will at least define a behavior of the counter. According to a first operating mode and during at least a first clock cycle, a function module executes the steps of reception of a synchronization signal, reception of a function control signal, and modification of the binary number according to the synchronization signal and the function control signal. 
   According to the first operating mode and during at least the first clock cycle, a first selection module may execute the steps of reception of a plurality of synchronization signals, reception of a first selection control signal, selection of the synchronization signal among the plurality of synchronization signals, according to the first selection control signal, and sending the synchronization signal to the function module. 
   According to a second operating mode and during at least the first clock cycle, a second selection module may execute the steps of reception of a plurality of signals, representative, at least for some, of a state of the counter, and a plurality of signals defining, at least for some, the behavior of the counter, reception of a second selection control signal, selection of a signal among the plurality of signals, according to the second selection control signal, and send the selected signal to a synchronization output of the second selection module. 
   During at least a second clock cycle and starting from an event of the clock signal, the counter may execute the behavior defined by the binary number. 
   The method may also include a step to activate the first operating mode. 
   The method may also include a step to activate the second operating mode. 
   According to another embodiment of the invention, the synchronization signal is a signal representative of at least a state of a counter of a second multifunctional timer/event counter device or a signal defining at least a behavior of the counter of the second device. 
   The plurality of synchronization signals may include at least a signal representative of at least a state of a counter of a second multifunctional timer/event counter device or a signal defining at least a behavior of the counter of the second device. 
   During at least a second clock cycle and starting from an event of the clock signal, the counter of the first device executes the behavior defined by the first binary number, and the counter of the second device executes a behavior defined by a second binary number contained in a control register of the second device. 
   The method may include a step to activate the first operating mode. 
   The method may also include a step to activate the second operating mode. 
   A function module of the second device may receive a signal representative of the state of the counter of the first device or a signal defining the behavior of the counter of the first device. 
   A first selection module of the second device may receive a signal representative of a state of the counter of the first device or a signal defining the behavior of the counter of the first device. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other characteristics and advantages of the invention will become clearer from the following description of a preferred embodiment of the invention given below for guidance and that is in no way limiting, with reference to the appended figures, wherein: 
       FIG. 1  shows a timer/event counter device according to one embodiment of the invention in the form of a block diagram; 
       FIG. 2  shows two timer/event counter devices in a particular application in the form of a block diagram, one device being used in a first operating mode, and the other device being used in a second operating mode; 
       FIG. 3  shows a timing diagram for the signals from the devices in the embodiment of  FIG. 2 ; and 
       FIG. 4  shows four devices according to another embodiment of the invention arranged to form a network. 
   

   DETAILED DESCRIPTION 
   The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     FIG. 1  shows a timer/event counter device in the form of a block diagram according to a particular embodiment of the invention. 
   The multifunctional timer/event counter device (TIMER), for example placed on a microcontroller chip, comprises a counter (CNT) controlled by a clock signal (CLK), a control register (REG_CTRL) including a binary number that will define a behavior of the counter (CNT) and a counter register (REG_CNT) containing a binary number representative of the state of the counter. This device (TIMER) also includes a function module (MF), a first and a second selection module (MS 1 , MS 2 ) and a timer means (D). 
   The function module (MF) includes a reception input (TRG) for a logical synchronization signal and a reception input for at least one function control signal (TMS), and is capable of modifying the binary number taking account of the synchronization signal and the function control signal (TMS). 
   The function control signal (TMS) may for example consist of a set of function control bits defined for example as follows:
           000 : reinitialize the counter on a rising front of the synchronization signal;     001 : counter clocked by the synchronization signal;     010 : start the counter when the synchronization signal is at the high level, and stop the counter when the synchronization signal is at the low level;     011 : start the counter on a rising front of the synchronization signal, with no control over stopping the counter;     100 : count down by the counter when the synchronization signal is at high level and count up when the synchronization signal is at the low level;   and a set of activation bits of the function module (MF) defined as follows:     0 : the function module (MF) is deactivated;     1 : the function module (MF) is active and the behavior of the counter is controlled by the synchronization signal.       

   For example, function control bits and activation bits of the function module (MF) may be sent to the function module (MF) by programming. 
   Thus, when activation bits  1  and function control bits  000  are sent to the function module (MF), the function module modifies the binary number contained in the control register (REG_CTRL) taking account of the synchronization signal, so that the counter (CNT) is reinitialized on a rising front of this synchronization signal. 
   By sending the same synchronization signal and the function control bits  011  to the function module (MF), the function module once again modifies the binary number contained in the control register (REG_CTRL) according to the state of the synchronization signal so that the counter starts on a rising front of the synchronization signal. 
   The first selection module (MS 1 ) includes a plurality of inputs and a reception input of a first selection control signal (TS). This first selection module (MS 1 ) can connect one input chosen from among the plurality of inputs to this first selection module (MS 1 ), to the reception input (TRG) of a synchronization signal of the function module (MF) as a function of the first selection control signal (TS). 
   The plurality of inputs of the first selection module (MS 1 ) may for example consist of eight inputs (ITR_ 1 , ITR_ 2 , ITR_ 3 , ITR_ 4 , ITR_ 5 , ITR_ 6 , EXT_ 11 , EXT_ 2 ), the first six inputs provided to receive six signals internal to the micro controller and the remaining two inputs being provided to receive two signals external to the microcontroller. 
   For example, the first selection control signal (TS) may consist of a first set of selection control bits, for example defined as follows:
           000 : selection of the first input (ITR_ 1 );     001 : selection of the second input (ITR_ 2 );     010 : selection of the third input (ITR_ 3 );     011 : selection of the fourth input (ITR_ 4 );     100 : selection of the fifth input (ITR_ 5 );     101 : selection of the sixth input (ITR_ 6 );     110 : selection of the seventh input (EXT_ 1 );     111 : selection of the eighth input (EXT_ 2 );       

   For example, the selection control bits may be sent to the first selection module (MF) by programming. 
   The second selection module (MS 2 ) comprises a synchronization output (TRGO), several inputs for reception of signals representative of the states of the counter (CNT) and signals defining behaviors of the counter (CNT), and a reception input for at least a second selection control signal (MMS). 
   This second selection module (MS 2 ) can connect one input from among the plurality of inputs of this second selection module (MS 2 ), to the synchronization output (TRGO) according to the second selection control signal (MMS). 
   For example, the plurality of inputs receives an overflow signal (OVF) from the counter (CNT), a comparison signal (CMP) representative of the result of the comparison between the value of the counter (CNT) and another value recorded in the counter register (REG_CNT), a start signal (EN) of the counter and a reset counter signal (RST). 
   The second selection control signal (MMS) may for example consists of a second set of selection control bits, for example defined as follows:
           000 : activate the second selection module (MMS);     001 : send the reset signal (RST) to the synchronization output (TRGO);     010 : send the start signal (EN) from the counter to the synchronization output (TRGO);     011 : send the overflow signal (OVF) to the synchronization output (TRGO);     100  send the comparison signal (CMP) to the synchronization output (TRGO);       

   The second set of selection control bits may for example be sent to the second selection module (MS 2 ) by programming. 
   For example, the timeout means (D) may consist of a set of flip-flops, known to those skilled in the art, controlled by the clock signal (CLK) and active on a rising front of the clock signal (CLK). 
   If the binary number in the control register (REF_CTRL) is modified during a first clock cycle so that the counter (CNT) adopts a new behavior, for example to start counting, the counter (CNT) will not follow this new behavior until the next clock cycle. 
   The device can operate in two different operating modes (MASTER, SLAVE):
         the first operating mode (SLAVE) is activated by sending the second set of selection control bits  000  to the second selection module (MS 2 ), and   the second operating mode (MASTER) is activated by sending activation bits  1  to the function module (MF).       

     FIG. 2  contains a block diagram showing two timer/event counter devices (TIMER_ 1 , TIMER — 2) in a particular application, the first device (TIMER_ 1 ) operating according to the first operating mode (SLAVE), and the second device (TIMER_ 2 ) acting according to the second operating mode (MASTER). 
   For reasons of clarity, only elements necessary for understanding the first operating mode (SLAVE) are shown on the first device, and only the elements necessary for understanding the second operating mode (MASTER) are shown on the second device. 
   Similarly, for clarity and simplification reasons, we will call:
         the first counter (CNT_ 1 ), the counter for the first device (TIMER_ 1 ) and the second counter (CNT_ 2 ), the counter for the second device (TIMER_ 2 );   the first counter register (REG_CNT_ 1 ) is the counter register for the first device (TIMER_ 1 ) and the second counter register (REG_CNT_ 2 ) is the counter register for the second device (TIMER_ 2 );   the first timer means (D_ 1 ) is the timer means for the first device (TIMER_ 1 ) and the second timer means (D_ 2 ) is the timer means for the second device (TIMER_ 2 );   the first control register (REG_CTRL_ 1 ) is the control register for the first device (TIMER_ 1 ) and the second control register (REG_CTRL_ 2 ) is the control register for the second device (TIMER_ 2 );       

   In this particular application, the synchronization output (TRGO) from the second device (TIMER_ 2 ) is connected to the first input (ITR_ 1 ) of the first selection module (MS 1 ) of the first device (TIMER_ 1 ). For example, this configuration is used for starting the counters of the two devices (TIMER_ 1 , TIMER_ 2 ) during the same clock cycle. 
   To do this, simply:
         send the selection control signal (MMS) to the second selection module (MS 2 ) of the second device (TIMER_ 2 ), containing the second set of selection control bits defined by bits  010 , in order to send the start signal (EN) for the second counter (CNT_ 2 ) to the synchronization output (TRGO) of the second device (TIMER_ 2 );   send the first selection control signal (TS) for the first selection module (MS 1 ) of the first device (TIMER_ 1 ), containing the first set of selection control bits defined by bits  000 , so as to connect the first input (ITR_ 1 ) of the first selection module (MS 1 ) to the reception input (TRG) of a synchronization signal of the function module (MF) of the second device (TIMER_ 2 );   send the function control signal (TMS) to the function module (MF) of the second device (TIMER_ 2 ) containing activation bits  1  and function control bits  011 .       

   With the synchronization output (TRGO) connected to the first input of the first selection module (MS 1 ) of the first device (TIMER_ 1 ), the start signal (EN) will also be used to start the first counter (CNT_ 1 ). 
   Therefore, this start signal is the synchronization signal for the two devices (TIMER_ 1 , TIMER_ 2 ). 
   Modification of the binary number contained in the second control register (REG_CTRL_ 2 ) by direct programming, provides a means of starting the first and second counters (CNT_ 1 , CNT_ 2 ) during the same clock cycle. 
     FIG. 3  shows a timing diagram of signals illustrating the operation of devices in this particular application. 
   CLK is the clock signal controlling the counters. 
   RST_ 1  and RST_ 2  are the reset first counter (CNT_ 1 ) signal and the reset second counter CNT_ 2 ) signal, respectively. 
   EN_ 1  and EN_ 2  represent the start first counter signal (CNT_ 1 ) and the start second counter signal CNT_ 2 ) respectively, sent to the first control register (REG_CTRL_ 1 ) and to the second control register (REG_CTRL_ 2 ) respectively. 
   CNT 1  and CNT 2  represent the value of the first counter (CNT_ 1 ) and the value of the counter of the second device (TIMER_ 2 ) respectively. 
   INCR_COUNTER_ 1  and INCR_COUNTER_ 2  represent the signal giving the start count order for the first counter (CNT_ 1 ) and the signal giving the start count order for the second counter CNT_ 2 ) respectively, generated by the first timer means (D_ 1 ) and the second timer means (D_ 2 ) respectively. 
   TRGO_ 2  represents the signal at the synchronization output from the second selection module (MS 2 ) of the second device (TIMER_ 2 ). 
   WRITE_CNT_ 1  represents the signal setting the value of the first counter (CNT_ 1 ). 
   Firstly, the second counter CNT_ 2 ) is reset to zero when RST_ 2  is at the high level. 
   Similarly, the first counter (CNT_ 1 ) is reset to zero when RST_ 1  is at the high level. 
   The first counter (CNT_ 1 ) is then initialized with the value 32487, namely 7EE7 in hexadecimal notation, when WRITE_CNT_ 1  is at the high level. 
   During at least one first clock cycle (C 1 ), EN_ 2  is set to the high level and is sent through the second control register (REG_CTRL_ 2 ) to the second timeout means (D_ 2 ) controlled by the same clock signal (CLK). 
   During this same clock cycle (C 1 ), EN_ 2  is sent to the synchronization output (TRGO) from the second device (TIMER_ 2 ) 
   This synchronization output (TRGO) being connected to the first input (ITR_ 1 ) of the first selection module (MS 1 ) of the first device (TIMER_ 1 ), EN_ 2  is sent to the reception input (TRG) as a synchronization signal of the function module (MF) of the first device (TIMER_ 1 ). 
   Also during this same first clock cycle (C 1 ), the binary number of the first control register (REG_CTRL_ 1 ) is then modified. The first timer means (D_ 1 ) controlled by the same clock signal (CLK) receives the signal EN_ 2 . 
   During a second clock cycle (C 2 ) and on a rising front of the clock signal (CLK), the first timer means (D_ 1 ) and the second timer means (D_ 2 ) generate the INCR_COUNTER_ 1  and INCR_COUNTER_ 2  signals respectively, identical to the EN_ 2  signal. During this same second clock cycle (C 2 ), these INCR_COUNTER_ 1  and INCR_COUNTER_ 2  signals are sent to the first counter (CNT_ 1 ) and the second counter (CNT_ 2 ) respectively. Thus, the first and second counters are started during this second clock cycle (C 2 ). 
   For example, synchronization of the two devices (TIMER_ 1 , TIMER_ 2 ) enables the two counters to be set to the initial values, and the comparison values in the registers can be configured to build up two PWM type logical signals with different frequencies but with an integer ratio, or two PWM type logical signals with identical frequencies but different phases. 
   It is also possible to loop back the synchronization output (TRGO) from the function module (MF) of the first device (TIMER_ 1 ) onto an input of the first selection module (MS 1 ) of the second device (TIMER_ 2 ). 
   Thus, during the same process, each device can operate according to the first operating mode (SLAVE), then according to the second operating mode (MASTER). 
   Embodiments of the invention can also limit the number of connections between several devices, and enables flexible configuration of the devices. 
   It is thus possible to make a network of timers as shown in  FIG. 4 , each device can control the other devices and can be controlled by the other devices. Thus, it is possible to build up very large frequency dividers from this type of configuration. 
   The timer and networks of timers may be contained in microcontrollers and other types of electronic circuits as well. Such a microcontroller or other type of electric circuit may, in turn, be contained in many different types of electronic systems, such as embedded systems designed to perform a particular function and computer systems generally. 
   From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.