Patent Publication Number: US-8987093-B2

Title: Multigate finFETs with epitaxially-grown merged source/drains

Description:
BACKGROUND 
     The present invention generally relates to semiconductor devices, and particularly to the manufacture of epitaxially-grown source/drains of multi-fin finFETs. 
     Fin metal-oxide-semiconductor field effect transistor (Fin-MOSFET) is an emerging technology which provides solutions to metal-oxide-semiconductor field effect transistor (MOSFET) scaling problems at, and below, the 22 nm node. FinMOSFET structures include fin field effect transistors (finFETs) which include at least one narrow semiconductor fin gated on at least two opposing sides of each of the at least one semiconductor fin. FinFET structures may be formed on a semiconductor-on-insulator (SOI) substrate, because of the low source/drain diffusion, low substrate capacitance, and ease of electrical isolation by shallow trench isolation structures. 
     FinFET devices having multiple fins covered by a single gate (also known as multigate devices) have been developed to further maximize the surface area contact between the body region of the fins and the gate. The multiple fins of multigate devices may be merged on one end to form a single source/drain region. Merging the multiple fins may be accomplished by epitaxially grown source/drain material, such as silicon, on the fin surface. However, as semiconductor devices continue to decrease in size, the smaller spaces between the fins may lead to issues such as faceting when growing source/drain regions of multigate devices. Due to the nature of epitaxial growth and certain structural features of integrated circuit devices, faceting is the result of epitaxially grown regions exhibiting undesirably formed shapes that impact device performance and reliability. In the case of forming source/drain regions on SOI finFETs, epitaxial growth occurs primarily on the fin sidewalls. Sidewall growth can result in faceting, voids, and other defects where growths on opposing sidewalls meet. Therefore, a method of growing source/drain regions of multigate devices that may, among other things, avoid faceting is desirable. 
     BRIEF SUMMARY 
     The present invention relates to methods of forming multi-gate finFET devices with epitaxially-grown merged source/drains. According to at least one exemplary embodiment, the method may include first forming a plurality of semiconductor fins joined by a plurality of inter-fin semiconductor regions and depositing a sacrificial gate over a center portion of each of the plurality of fins The sacrificial gate may divide each of the plurality of fins into a body region covered by the sacrificial gate, a first end, and a second end separated from the first end by the body region and the sacrificial gate also divides each of the plurality of inter-fin semiconductor regions into a body region covered by the sacrificial gate, a first end, and a second end separated from the first end by the body region. 
     The method may then further include forming a first merge layer over the first end of each of the plurality of fins to form a first merged fin region, the first merged fin region comprising the first merge layer, the first end of each of the plurality of fins, and the inter-fin semiconductor regions between the first ends of the plurality of fins and forming a second merge layer over the second end of each of the plurality of fins to form a second merged fin region, the second merged fin region comprising the second merge layer, the second ends of the plurality of fins, and the inter-fin semiconductor regions between the second ends of the plurality of fins. 
     The method may then further include etching a portion of the first merged fin region to form a first source/drain base region, etching a portion of the second merged fin region to form a second source/drain base region, forming a first source/drain region on the first source/drain base region, and forming a second source/drain region on the second source/drain base region. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIGS. 1A-1E  depict various views of a silicon-on-insulator (SOI) substrate that may be used in one embodiment of the invention. 
         FIGS. 2A-2E  depict etching the semiconductor substrate layer of the SOI substrate of  FIGS. 1A-1E  to form a plurality of semiconductor fins joined by inter-fin semiconductor regions. 
         FIGS. 3A-3E  depict depositing a sacrificial gate over body regions of the fins formed in  FIGS. 2A-2E . 
         FIGS. 4A-4E  depict merging the portions of the fins not covered by the sacrificial gate formed in  FIGS. 3A-3E . 
         FIGS. 5A-5E  depict etching the merged ends of the fins as formed in  FIGS. 4A-4E  to form source/drain base regions with top flat surfaces to support source/drain regions. 
         FIGS. 6A-6E  depict forming source/drain regions on the flat surfaces of the source/drain base regions formed in  FIGS. 5A-5E . 
         FIGS. 7A-7E  depict forming protective layers over the source/drain regions formed in  FIGS. 6A-6E . 
         FIGS. 8A-8E  depict removing the sacrificial gate formed in  FIGS. 3A-3E  from the body regions of the fins. 
         FIGS. 9A-9E  depict separating the body regions of the fins by removing the inter-fin semiconductor regions. 
     
    
    
     Figures with the suffix “A” are top-down views of an exemplary structure. Figures with the suffix “B”, “C”, “D”, or “E” are vertical cross-sectional views of the exemplary structure along the plane indicated by dashed line B-B′, C-C′, D-D′, or E-E′, respectively, of the corresponding figure with the same numeric label and the suffix “A.” 
     Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, dimensions of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements. 
     DETAILED DESCRIPTION 
     Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments. 
     Referring to  FIGS. 1A-1E , a semiconductor-on insulator (SOI) substrate  100  is provided. The SOI substrate  100  may further include a handle substrate  101 , a buried insulator layer  102 , and a semiconductor substrate layer  103 . The handle substrate  101  may be made of any semiconductor material including, but not limited to: silicon, germanium, silicon-germanium alloy, carbon-doped silicon, carbon-doped silicon-germanium alloy (SiGe:C), and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. The buried insulator layer  102  may be formed from any of several dielectric materials. Non-limiting examples include, for example, oxides, nitrides, oxynitrides of silicon, and combinations thereof. Oxides, nitrides and oxynitrides of other elements are also envisioned. In addition, the buried insulator layer  102  may include crystalline or non-crystalline dielectric material. The buried insulator layer  102  may be 100-500 nm thick, preferably about 200 nm. The semiconductor substrate layer  103  may be made of any of the several semiconductor materials possible for the handle substrate  101 . In general, the handle substrate  101  and the semiconductor substrate layer  103  may include either identical or different semiconducting materials with respect to chemical composition, dopant concentration and crystallographic orientation. The semiconductor substrate layer  103  may be p-doped or n-doped with a dopant concentration in the range of 1×10 15 -1×10 18 /cm 3 , preferably about 1×10 15 . The semiconductor substrate layer  103  may be 50-300 nm thick, preferably about 100 nm. 
     Referring to  FIGS. 2A-2E , fins  201  are formed by removing material from the semiconductor substrate layer  103  ( FIGS. 1A-1E ), for example by a photolithography process followed by an anisotropic etching process such as reactive ion etching (RIE). The process used to remove material from semiconductor the substrate layer  103  should not penetrate the semiconductor substrate layer  103  completely (i.e., the etching process should not expose the buried insulator layer  102 ), so that the fins  201  remain joined by inter-fin semiconductor regions  202 . In some embodiments, the fins  201  may have a height of approximately 25-30 nm, and a width of approximately 10 nm, while the inter-fin semiconductor regions  202  may have a height of approximately 5 nm, or 15-20% of the height of the fins  201 , and a width of approximately 30 nm. In some embodiments, a hard mask layer (not shown) may be incorporated into the etching process to protect the fins  201  during their formation, and also during subsequent processing steps, such as the sacrificial gate removal process discussed below in conjunction with  FIGS. 8A-8E . While the depicted embodiment includes three fins, it will be understood that other embodiments may include two or more fins. 
     Referring to  FIGS. 3A-3E , a sacrificial gate  301  may be formed over a central portion of fins  201 . The sacrificial gate  301  may be made of, for example, a polysilicon material and formed using known deposition techniques known in the art. Formation of the sacrificial gate  301  divides the fins into three regions, a body region  305 , and end regions  310   a  and  310   b . The body region  305  includes fin bodies  306  and inter-fin bodies  307 . The end region  310   a  includes fin ends  311   a  and inter-fin ends  312   a . The end region  310   b  includes fin ends  311   b  and inter-fin ends  312   b . The sacrificial gate  301  may further include one or more spacers (not shown) formed around the sacrificial gate  301  to separate the sacrificial gate  301  from the source/drain regions formed in  FIGS. 4A-6E . If included, the spacers may be made of, for example, silicon nitride or silicon oxynitride. The spacer may be formed by depositing a conformal layer of dielectric material, such as oxides, nitrides or oxynitrides followed by etching. The spacer (not depicted) may have a width ranging from 1 nm to 10 nm, typically ranging from 1 nm to 5 nm. 
     Referring to  FIGS. 4A-4E , merge layers  401   a  and  401   b  may be formed over the end regions  310   a  and  310   b  ( FIGS. 3A-3E ). The merge layers  401   a  and  401   b  should be made of a material with substantially similar etch properties as those of the fins  201 . In embodiments where the fins  201  ( FIGS. 2A-2E ) are made of a silicon-containing semiconductor material, the merge layers  401   a  and  401   b  may be formed, for example, by epitaxial growth or deposition of silicon or silicon-germanium. After formation of the merge layers  401   a  and  401   b , merged fin regions  420   a  and  420   b  includes the merge layers  401   a  and  410   b , the fin ends  311   a  and  311   b , and the inter-fin ends  312   a  and  312   b.    
     Referring to  FIGS. 5A-5E , the merged fin regions  420   a  and  420   b  ( FIGS. 4A-4E ) are etched to form source/drain base regions  510   a  and  510   b  using an etching process such as, for example, RIE. In some embodiments, the sacrificial gate  301  may include a protective cap (not shown) made of, for example, silicon nitride, to protect the sacrificial gate  301  from damage while the merged fin regions  420   a  and  420   b  are etched. The source/drain base region  510   a  may include remaining portions  512   a  of the merge layer  401   a  ( FIGS. 4A-4E ), remaining portions  511   a  of the fins ends  311   a  ( FIG. 3A ), and the inter-fin ends  312   a . The source/drain base region  510   b  may include remaining portions  512   b  of the merge layer  401   b , remaining portions  511   b  of the fins  311   b  ( FIG. 3A ), and the inter-fin ends  312   b . In some embodiments, the etch process may remove all of the merge layers  401   a  and  401   b . In such embodiments (not shown), the source/drain base regions  510   a  and  510   b  include only the remaining portions  511   a  and  511   b  of the fins ends  311   a  and  311   b  ( FIG. 3A ), and the inter-fin ends  312   a  and  312   b , respectively. Further, the etching process may remove some portions of the inter-fin ends  312   a  and  312   b.    
     Referring particularly to  FIG. 5C , the source/drain base regions  510   a  and  510   b  may have a substantially flat top surface and may have a thickness of about less then approximately 5 nm, preferably 3-4 nm. In later fabrication steps, source/drain regions may be formed on the top surface of the source/drain base regions  510   a  and  510   b . By growing the source/drain regions on the substantially uniform surface of the source/drain base regions  510   a  and  510   b , rather than the fin ends  311   a  and  311   b  directly, it may be possible to form more uniform source/drain regions with a consistent crystallographic orientation and doping while also preventing the formation of defects such as voids and facets. For example, in some embodiments, the source/drain base regions  510   a  and  510   b  may have a uniform (001) plane capable of supporting even silicon growth from a single plane, whereas growing source/drain regions directly on the fin ends  311   a  and  311   b  ( FIG. 3A ) may result in voiding and faceting where growth fronts from multiple planes meet. Further, the uniformity of the source/drain regions  510   a  and  510   b  allows for easier introduction of stress or strain into the source/drain regions. 
     Referring to  FIGS. 6A-6E , source/drain regions  601   a  and  601   b  are formed on top of the source/drain base regions  510   a  and  510   b , respectively. The source/drain regions  601   a  and  601   b  may be formed by, for example, epitaxially growing silicon on the top surface of the source/drain base regions  510   a  and  510   b . For NMOS finFETs (i.e. finFETs with source/drains with n-type dopants), the source/drain regions  601   a  and  601   b  may be made of, for example, silicon or silicon carbide with a doping concentration of about 1×10 20  to about 8×10 20 /cm 3  of arsenic or phosphorus. For PMOS finFETs finFETs (i.e. finFETs with source/drains with p-type dopants), the source/drain regions  601   a  and  601   b  may be made of, for example, silicon or silicon germanium with a doping concentration of 1×10 20 -8×10 20 /cm 3  of boron. The source/drain regions  601   a  and  601   b  may have a thickness of about 40-70 nm, preferably 50-60 nm. 
     Referring to  FIGS. 7A-7E , protective layers  701   a  and  701   b  are formed above the source/drain regions  601   a  and  601   b , respectively. The protective layers  701   a  and  701   b  may be capable of preventing any substantial damage to the source/drain regions  601   a  and  601   b  during subsequent processing steps, such as the etching processes discussed below in conjunction with  FIGS. 8A-8E  and  9 A- 9 E. The protective layers  701   a  and  701   b  may be made of, for example, silicon dioxide, silicon nitride, SiCOH, SiLK, or porous dielectrics. Further, the protective layers  701   a  and  701   b  may be formed by any known method in the art including, for example, chemical vapor deposition or other known deposition techniques. 
     Referring to  FIGS. 8A-8E , sacrificial gate  301 ( FIG. 7A-7E ) is removed to form a gate recess region  801 . In embodiments where the sacrificial gate  301  includes at least one spacer (not shown), the gate removal technique and or spacer material may be such that the spacer remains and may define the outer boundary of the gate recess region  801 . The gate recess region  801  includes both the space between and the space above the fin bodies  306  and will be filled with metal gate after the fin bodies  306  are separated ( FIG. 9A-9E ). The sacrificial gate  301  may be removed by known etching techniques including, for example, RIE. 
     Referring to  FIGS. 9A-9E , the fin bodies  306  may be separated by removing the inter-fin bodies  307  ( FIG. 8B ). Inter-fin bodies may be removed by any known etching process, including for example, RIE. In some embodiments, a single etching process may be used to remove the sacrificial gate  301  and remove the inter-fin bodies  307 . While etching the inter-fin bodies  307 , some material may be removed from the fin bodies  306 . To account for this, the fins  201  may be initially formed taller than ultimately desired (See  FIGS. 2A-2E  for formation of the fins  201 ). In some embodiments, a hard mask (not shown) can be formed on top of the fin bodies  306  during fin formation (shown in  FIG. 2A-2E ) to prevent loss of fin height during inter-fin body removal. Alternatively, the inter-fin bodies  307  may be removed by a thermal agglomeration process. The thermal agglomeration process may remove the inter-fin bodies  307  by causing the inter-fin bodies  307  to evaporate at high temperature under an ultra-high vacuum. After removal of the inter-fin bodies  307 , the buried insulator layer  102  may be exposed between each fin body  306  and each fin body  306  may not be in contact with any other fin body  306  in the gate recess region  801 . 
     After the fin bodies  306  are separated, a metal gate may be formed in the gate recess region  801  using any known gate-last process. For example, the gate-last process may include depositing in the gate recess region  801  a gate dielectric layer, one or more work-function metals, and a metal gate electrode (not shown). The gate dielectric layer may be made of, for example, silicon dioxide, tantalum nitride, or any other known high-k dielectric. Potential work-function metals may include may be made of, for example, titanium nitride, tantalum, tantalum nitride, or titanium-aluminum and may be 1 nm to 50 nm thick, preferably 1 nm to 10 nm. The metal gate electrode may be made of, for example, copper, tungsten, or aluminum. Other embodiments may include more or less metal depending on the application and types of device being formed. The composition of each layer may also vary and the process of selecting the material for each layer is known in the art. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable other of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.