Patent Publication Number: US-2023154819-A1

Title: Semiconductor package and method of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 16/888,990, filed on Jun. 1, 2020, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0067575, filed on Jun. 7, 2019, in the Korean Intellectual Property Office, the disclosure of each of which is hereby incorporated by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     Example embodiments of the present disclosure relate to semiconductor packages and/or methods of manufacturing the same, and, more specifically, to semiconductor packages having an improved heat dissipation property and methods of manufacturing the same. 
     DISCUSSION OF RELATED ART 
     In general, a packaging process is performed on semiconductor chips formed by performing various semiconductor processes on a wafer. Recently, various types of semiconductor chips are packaged in a single package, and the semiconductor chips are electrically connected to each other to operate as a single system. However, during operation of the semiconductor chips, excessive heat is generated. The semiconductor package may be degraded due to the excessive heat. 
     SUMMARY 
     According to an example embodiment of the inventive concepts, a semiconductor package includes a first semiconductor chip, a first interposer on the first semiconductor chip, the first interposer including a first interposer substrate and a first heat dissipation pattern passing through the first interposer substrate and electrically insulated from the first semiconductor chip, and a molding layer covering at least a portion of the first semiconductor chip and at least a portion of the first interposer. The first heat dissipation pattern may include a first through electrode passing through the first interposer substrate, and a first upper pad on an upper surface of the first interposer substrate and connected to the first through electrode. The molding layer may cover at least a portion of a sidewall of the first upper pad and at least a portion of the upper surface of the first interposer substrate. At least a portion of an upper surface of the first upper pad may be not covered by the molding layer. 
     According to an example embodiment of the inventive concepts, a semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first interposer on the first semiconductor chip, the first interposer including a first interposer substrate and a first heat dissipation pattern passing through the first interposer substrate, and a second interposer on the second semiconductor chip, the second interposer including a second interposer substrate and a second heat dissipation pattern passing through the second interposer substrate. 
     According to an example embodiment of the inventive concepts, a semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the first semiconductor chip, a first interposer on the first semiconductor chip, the first interposer including a first interposer substrate and a plurality of first heat dissipation patterns electrically insulated from the first semiconductor chip, a second interposer on the second semiconductor chip, the second interposer including a second interposer substrate and a plurality of second heat dissipation patterns electrically insulated from the second semiconductor chip, a third interposer on the third semiconductor chip, the third interposer including a third interposer substrate and a plurality of third heat dissipation patterns electrically insulated from the third semiconductor chip, and a molding layer covering at least a portion of the first semiconductor chip, at least a portion of the first interposer, at least a portion of the second semiconductor chip, at least a portion of the second interposer, at least a portion of the third semiconductor chip, and at least a portion of the third interposer. Each of the plurality of first heat dissipation patterns may include a first through electrode passing through the first interposer substrate, and a first upper pad on an upper surface of the first interposer substrate and connected to the first through electrode. Each of the plurality of second heat dissipation patterns may include a second through electrode passing through the second interposer substrate, and a second upper pad on an upper surface of the second interposer substrate and connected to the second through electrode. Each of the plurality of third heat dissipation patterns may include a third through electrode passing through the third interposer substrate, and a third upper pad on an upper surface of the third interposer substrate and connected to the third through electrode. 
     According to an example embodiment of the inventive concepts, a method of manufacturing a semiconductor package includes preparing a first interposer including a first interposer substrate and a first heat dissipation pattern, the first heat dissipation pattern including a first through electrode passing through the first interposer substrate and a first upper pad on an upper surface of the first interposer substrate, stacking the first interposer on a first semiconductor chip, positioning a molding film on the first interposer to contact a portion of the first upper pad and to be spaced apart from the upper surface of the first interposer substrate, forming a molding layer covering the first interposer substrate while not covering the portion of the first upper pad that is in contact with the molding film, and removing the molding film. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a cross-sectional view illustrating an interposer according to an example embodiment of the inventive concepts. 
         FIGS.  2 A and  2 B  are plan views illustrating arrangements of heat dissipation patterns in the interposer of  FIG.  1    according to some example embodiments of the inventive concepts. 
         FIG.  3    is a cross-sectional view illustrating an interposer according to an example embodiment of the inventive concepts. 
         FIG.  4    is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. 
         FIG.  5    is an enlarged cross-sectional view of a portion of the semiconductor package of  FIG.  4   . 
         FIG.  6    is a flow chart illustrating a method of forming a molding layer of the semiconductor package of  FIG.  4    according to an example embodiment of the inventive concepts. 
         FIGS.  7 A and  7 B  are cross-sectional views illustrating methods of forming a molding layer of the semiconductor package of  FIG.  4    according to some example embodiments of the inventive concepts. 
         FIG.  8    is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. 
         FIG.  9    is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. 
         FIGS.  10 A,  10 B, and  10 C  are plan views illustrating a first interposer and a second interposer of the semiconductor package of  FIG.  9    according to some example embodiments of the inventive concepts. 
         FIGS.  11 ,  12 ,  13 ,  14 , and  15    are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts. 
         FIGS.  16 ,  17 ,  18 ,  19 , and  20    are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts. 
         FIGS.  21 A and  21 B  are cross-sectional views illustrating a method of manufacturing the semiconductor package of  FIG.  9    according to an example embodiment of the inventive concepts. 
         FIGS.  22 A,  22 B,  22 C, and  22 D  are cross-sectional views illustrating a method of manufacturing the semiconductor package of  FIG.  17    according to an example embodiment of the inventive concepts. 
     
    
    
     DETAILED DESCRIPTION 
     Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application. 
       FIG.  1    is a cross-sectional view illustrating an interposer according to an example embodiment of the inventive concepts. 
     Referring to  FIG.  1   , an interposer  100  may include an interposer substrate  110  and a heat dissipation pattern  120 . 
     The interposer substrate  110  may include an organic material. For example, the interposer substrate  110  may be formed of prepreg that is a material in which resin is infiltrated into a glass fiber or a carbon fiber and is hardened to a B-stage (semi-curable state of resin). In some embodiments, the interposer substrate  110  may be a silicon wafer including silicon, such as single crystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the interposer substrate  110  may include ceramic. The interposer substrate  110  may have a plate shape and may have an upper surface and a lower surface opposite to each other. 
     The heat dissipation pattern  120  may pass through the interposer substrate  110 . That is, the heat dissipation pattern  120  may extend from the upper surface of the interposer substrate  110  to the lower surface of the interposer substrate  110 . When the interposer  100  is attached to an object desiring heat dissipation, the heat dissipation pattern  120  may serve as a path for releasing heat to the outside. For example, when the interposer  100  is attached to the object desiring the heat dissipation, as a bottom of the heat dissipation pattern  120  contacts the object and a top of the heat dissipation pattern  120  is exposed to the outside, heat generated from the object may be released to the outside through the heat dissipation pattern  120 . 
     The heat dissipation pattern  120  may include a material having high thermal conductivity. For example, the heat dissipation pattern  120  may include a material having a thermal conductivity of  10  W/mK or more. For example, the heat dissipation pattern  120  may include at least one of copper (Cu), nickel (Ni), gold (Au), tungsten (W), and aluminum (Al). 
     The heat dissipation pattern  120  may include a through electrode  121  penetrating the interposer substrate  110 , an upper pad  122  on the upper surface of the interposer substrate  110 , and a lower pad  123  on the lower surface of the interposer substrate  110 . A top end of the through electrode  121  may be connected to the upper pad  122 . A bottom end of the through electrode  121  may be connected to the lower pad  123 . The upper pad  122  and the lower pad  123  may be thermally coupled by the through electrode  121 . When the interposer  100  is attached to the object desiring the heat dissipation, at least a portion of the upper pad  122  may be exposed to the outside and the lower pad  123  may contact the object. 
     In some example embodiments, a width of the through electrode  121  in a horizontal direction (i.e., an X direction or a Y direction) may be between 50 μm and 500 μm. A height of the through electrode  121  in a vertical direction (i.e., a Z direction) may be between 50 μm and 300 μm. 
     In some example embodiments, a width of the upper pad  122  in the horizontal direction may be greater than the width of the through electrode  121  in the horizontal direction. In other words, a planar area of the upper pad  122  may be greater than a planar area of the through electrode  121 , in an X-Y plane having the X direction and the Y direction. In this case, as a surface area of the upper pad  122  exposed to the outside increases, heat transfer from the upper pad  122  to the outside may be improved. 
     In some example embodiments, the width of the upper pad  122  in the horizontal direction may be greater than the width of the through electrode  121  in the horizontal direction by at least 10 μm. For example, difference between the width of the upper pad  122  and the width of the through electrode  121  may be between 10 μm and 70 μm. 
     In some example embodiments, a distance between adjacent upper pads  122  in the horizontal direction may be between 10 μm and 100 μm. 
     In some example embodiments, a height of the upper pad  122  in the vertical direction may be between 5 μm and 50 μm. 
     As shown in  FIG.  1   , one upper pad  122  may be connected to one through electrode  121 . However, in some embodiments, one upper pad  122  may be connected to a plurality of through electrodes  121 . For example, the upper pad  122  may have a plate shape covering at least a portion of the upper surface of the interposer substrate  110  and connected to the plurality of through electrodes  121 . 
     In some example embodiments, a width of the lower pad  123  in the horizontal direction may be greater than the width of the through electrode  121  in the horizontal direction. That is, a planar area of the lower pad  123  may be greater than the planar area of the through electrode  121 , in the X-Y plane. In this case, because a contact area of the lower pad  123  contacting the object desiring the heat dissipation increases, the heat transfer between the object and the lower pad  123  may be improved. 
     In some example embodiments, the width of the lower pad  123  in the horizontal direction may be greater than the width of the through electrode  121  in the horizontal direction by at least 10 μm. For example, difference between the width of the lower pad  123  and the width of the through electrode  121  may be between 10 μm and 70 μm. 
     In some example embodiments, a distance between adjacent lower pads  123  in the horizontal direction may be between 10 μm and 100 μm. 
     In some example embodiments, a height of the lower pad  123  in the vertical direction may be between 5 μm and 50 μm. 
     As shown in  FIG.  1   , one lower pad  123  may be connected to one through electrode  121 . However, in some example embodiments, one lower pad  123  may be connected to a plurality of through electrodes  121 . For example, the lower pad  123  may have a plate shape covering at least a portion of the lower surface of the interposer substrate  110  and connected to the plurality of through electrodes  121 . 
       FIGS.  2 A and  2 B  are plan views illustrating arrangements of heat dissipation patterns in the interposer of  FIG.  1    according to some example embodiments of the inventive concepts. 
     In  FIG.  2 A , a first arrangement of heat dissipation patterns  120  is shown. In  FIG.  2 B , a second arrangement of the heat dissipation patterns  120  is shown. The first arrangement of the heat dissipation patterns  120  may represent a case in which the number or a density of the heat dissipation patterns  120  is relatively large, and the second arrangement of the heat dissipation patterns  120  may represent a case in which the number or density of heat dissipation patterns  120  is relatively small. Here, the arrangement of the heat dissipation patterns  120  may mean the number, density, or array form of the heat dissipation patterns  120 . 
     Because the heat dissipation property of the interposer  100  is changed depending on the number or density of the heat dissipation patterns  120 , the arrangement of the heat dissipation patterns  120  may be changed according to the object desiring the heat dissipation. 
     For example, when the interposer  100  is used to release heat of a semiconductor chip, the arrangement of the heat dissipation patterns  120  may be changed depending on a type of the semiconductor chip. For example, when a heat generation amount of the semiconductor chip is relatively great or the semiconductor chip desires rapid heat dissipation in the case in which the semiconductor chip is vulnerable to heat, the number or density of the heat dissipation patterns  120  may be increased. 
     Further, the arrangement of the heat dissipation patterns  120  may vary from region to region of the interposer  100 . For example, the number or density of the heat dissipation patterns  120  in a first region of the interposer  100  may be larger than the number or density of the heat dissipation patterns  120  in a second region of the interposer  100 . For example, when the first region of the interposer  100  corresponds to a central region of the semiconductor chip at which the heat generation amount is relatively large and the second region of the interposer  100  corresponds to a peripheral region of the semiconductor chip at which the heat generation amount is relatively small, the number or density of the heat dissipation patterns  120  in the first region of the interposer  100  may be larger than that of the heat dissipation patterns  120  in the second region of the interposer  100 . 
       FIG.  3    is a cross-sectional view illustrating an interposer according to an example embodiment of the inventive concepts. An interposer of  FIG.  3    may be the same as or substantially similar to the interposer  100  shown in  FIG.  1    except further including an upper cover layer and a lower cover layer. 
     Referring to  FIG.  3   , a heat dissipation pattern  120   a  of an interposer  100   a  may include an upper cover layer  124  on the upper pad  122  and a lower cover layer  125  on the lower pad  123 . 
     The upper cover layer  124  may cover the upper pad  122  on the upper surface of the interposer substrate  110 . The upper cover layer  124  may serve as a oxidation barrier layer for preventing oxidation of the upper pad  122 . The upper cover layer  124  may include, for example, nickel (Ni) and/or gold (Au). For example, the upper cover layer  124  may be formed by a plating process. 
     The lower cover layer  125  may cover the lower pad  123  on the lower surface of the interposer substrate  110 . The lower cover layer  125  may serve as a oxidation barrier layer for preventing oxidation of the lower pad  123 . The lower cover layer  125  may include, for example, nickel (Ni) and/or gold (Au). For example, the lower cover layer  125  may be formed by a plating process. 
       FIG.  4    is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts.  FIG.  5    is an enlarged cross-sectional view of a portion of the semiconductor package of  FIG.  4   . 
     Referring to  FIGS.  4  and  5   , a semiconductor package  200  may include a package substrate  210 , a first semiconductor chip  220 , a first interposer  250 , and a molding layer  270 . 
     The package substrate  210  may be, for example, a printed circuit board. The package substrate  210  may include a substrate base made of at least one of phenol resin, epoxy resin, and polyimide. The package substrate  210  may include an upper substrate pad  215  and a lower substrate pad  213  on an upper surface and a lower surface, respectively, of the substrate base. The upper substrate pad  215  and the lower substrate pad  213  may include, for example, copper (Cu), nickel (Ni), and/or aluminum (Al). An internal wiring line may be disposed in the substrate base to connect the upper substrate pad  215  and the lower substrate pad  213 . 
     An external connection terminal  290  may be attached to a lower surface of the package substrate  210 . For example, the external connection terminal  290  may be attached to the lower substrate pad  213 . The external connection terminal  290  may be, for example, a solder ball or a bump. The external connection terminal  290  may electrically connect the semiconductor package  200  and an external device. 
     The first semiconductor chip  220  may be mounted on the package substrate  210 . The first semiconductor chip  220  may include a semiconductor substrate having opposite active and inactive surfaces and a semiconductor device layer on the active surface of the semiconductor substrate. The first semiconductor chip  220  may have opposite first and second surfaces  220   a  and  220   b . A first chip pad  221  may be disposed on the first surface  220   a  of the first semiconductor chip  220 . The first chip pad  221  may be electrically connected to the semiconductor device layer through a wiring structure. 
     The first semiconductor chip  220  may be a memory chip, for example, a volatile memory chip and/or a nonvolatile memory chip. The volatile memory chip may include, for example, dynamic random access memory (DRAM), static RAM (SRAM), thyristor RAM (TRAM), zero capacitor RAM (ZRAM), or twin transistor RAM (TTRAM). The nonvolatile memory chip may include, for example, flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM (STT-MRAM), ferroelectric RAM (FRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM, or insulator resistance change memory. 
     The first semiconductor chip  220  may be a non-memory chip. For example, the first semiconductor chip  220  may be a logic chip, such as an artificial intelligence semiconductor chip, microprocessor, graphic processor, signal processor, network processor, chipset, audio codec, video codec, application processor, or system on chip, but the inventive concepts are not limited thereto. 
     The first semiconductor chip  220  may be mounted on the package substrate  210  so that the first surface  220   a  of the first semiconductor chip  220  on which the first chip pad  221  is disposed faces upward. The first chip pad  221  may be arranged along a side of a first semiconductor chip  220 . The first chip pad  221  may be electrically connected to the upper substrate pad  215  of the package substrate  210  through a conductive wire  280 . The first chip pad  221  may be used as a terminal to transfer input/output data signals of the first semiconductor chip  220  or a terminal to provide power and/or ground for the first semiconductor chip  220 . 
     The first interposer  250  may be stacked on the first surface  220   a  of the first semiconductor chip  220 . The first interposer  250  may include a first interposer substrate  251  and a first heat dissipation pattern  253 . The first heat dissipation pattern  253  may include a first through electrode  2531 , a first upper pad  2532 , and a first lower pad  2533 . The first interposer  250  may include the interposer  100  or the interposer  100   a  described with reference to  FIGS.  1  to  3   . 
     The first heat dissipation pattern  253  may be used as a heat transfer path for releasing the heat of the first semiconductor chip  220  to the outside. For example, a bottom of the first heat dissipation pattern  253  may contact the first surface  220   a  of the first semiconductor chip  220 , and a top of the first heat dissipation pattern  253  may be exposed to the outside. In this case, the heat of the first semiconductor chip  220  may be emitted to the outside through the first heat dissipation pattern  253 . The first heat dissipation pattern  253  may be electrically insulated from the first semiconductor chip  220 . The first heat dissipation pattern  253  of the first interposer  250  may be spaced apart from and electrically insulated from the first chip pad  221  of the first semiconductor chip  220 . 
     In some example embodiments, a first thermal interface material (TIM)  240  may be interposed between the first interposer  250  and the first semiconductor chip  220 . The first TIM  240  may physically fix the first interposer  250  to the first semiconductor chip  220  and may strengthen thermal coupling between the first heat dissipation pattern  253  of the first interposer  250  and the first semiconductor chip  220 . For example, the first TIM  240  may be formed of an insulating material, for example, an insulating material capable of maintaining an electrical insulation. 
     The first interposer  250  may be stacked on the first semiconductor chip  220  not to overlap the first chip pad  221  of the first semiconductor chip  220 . For example, in the case in which a plurality of first chip pad  221  are disposed adjacent to a side edge of the first surface  220   a  of the first semiconductor chip  220 , the first interposer  250  may be spaced a desired (or alternatively, predetermined) distance apart from the side edge of the first surface  220   a  of the first semiconductor chip  220  so as not to cover the plurality of first chip pads  221 . 
     The molding layer  270  may cover at least a portion of the first semiconductor chip  220  and at least a portion of the first interposer  250 . Thus, the molding layer  270  may act to protect the first semiconductor chip  220  and the first interposer  250  from the external environment. 
     The molding layer  270  may be formed by injecting an appropriate amount of a molding material around the first semiconductor chip  220  and curing the molding material. The molding layer  270  may be a portion for forming an appearance of the semiconductor package  200 . In some example embodiments, the molding material for forming the molding layer  270  may include epoxy-group molding resin or polyimide-group molding resin. For example, the molding layer  270  may include an epoxy molding compound (EMC). 
     As shown in  FIG.  5   , the molding layer  270  may cover a portion of the first upper pad  2532  and the first interposer substrate  251  and may expose the other portion of the first upper pad  2532  to the outside. For example, the molding layer  270  may cover a portion of a sidewall of the first upper pad  2532 , and may expose an upper surface of the first upper pad  2532 . In this case, the molding layer  270  may protect the portion of the sidewall of the first upper pad  2532 . 
     The first TIM  240  may be interposed between a lower surface of the first interposer substrate  251  and the first semiconductor chip  220 . The first TIM  240  may fill a space between the lower surface of the first interposer substrate  251  and the first semiconductor chip  220 , and may cover the first lower pad  2533  on the lower surface of the first interposer substrate  251 . For example, the first TIM  240  may fill a space between adjacent first lower pads  2533 , and may cover at least a portion of the first lower pad  2533 . Although not specifically illustrated, according to some example embodiments, the first TIM  240  may further cover a lower surface of the first lower pad  2533  facing the first surface  220   a  of the first semiconductor chip  220 . 
     In some example embodiments, because the heat generated from the first semiconductor chip  220  is released using the first interposer  250  attached onto the first semiconductor chip  220 , the heat generation property of the semiconductor package  200  may be improved. 
       FIG.  6    is a flow chart illustrating a method of forming a molding layer of the semiconductor package of  FIG.  4    according to an example embodiment of the inventive concepts.  FIGS.  7 A and  7 B  are cross-sectional views illustrating methods of forming a molding layer of the semiconductor package of  FIG.  4    according to some example embodiments of the inventive concepts. 
     Referring to  FIGS.  4 ,  6 ,  7 A, and  7 B , to form the molding layer  270  of the semiconductor package  200 , step S 110  of positioning a molding film MF on the first interposer  250 , step S 120  of forming the molding layer  270  by injecting and curing the molding material  271 , and step S 130  of removing the molding film MF may be sequentially performed. 
     For example, in the step S 110  of positioning the molding film MF on the first interposer  250 , the molding film MF may cover (contact) a portion of a surface of the first upper pad  2532 , and may not cover (not contact) at least a portion of a sidewall of the first upper pad  2532 . The molding film MF may be spaced apart from an upper surface of the first interposer substrate  251  to a desired (or alternatively, predetermined) distance to form a space between the upper surface of the first interposer substrate  251  and the molding film MF. 
     In the step  5120  of forming the molding layer  270  by injecting and curing the molding material  271 , the molding material  271  may be provided below the molding film MF and may be formed to cover the first semiconductor chip  220  and the first interposer substrate  251 . The molding material  271  may fill the space between the molding film MF and the first interposer substrate  251 . At that time, the molding material  271  may not cover a portion of the first upper pad  2532  covered by (in contact with) the molding film MF. When a certain pressure and heat are applied to the molding material  271  so as to cure the molding material  271 , the molding layer  270  may be formed to cover at least a portion of the first upper pad  2532 . 
     For example, as shown in  FIG.  7 A , the molding layer  270  may be formed by a transfer molding method using the molding film MF. In some example embodiments, as shown in  FIG.  7 B , the molding layer  270  may be formed by a compression molding method using the molding film MF. 
     After the molding layer  270  is formed, the molding film MF may be removed (S 130 ). The molding film MF may be, for example, a release film. Because the molding film MF is removed, a portion of the first upper pad  2532  may be covered by the molding layer  270 , whereas the other portion of the first upper pad  2532  may be exposed to the outside. 
       FIG.  8    is a cross-sectional views illustrating a semiconductor package according to an example embodiment of the inventive concepts. A semiconductor package shown in  FIG.  8    may be the same as or substantially similar to the semiconductor package  200  shown in  FIG.  4    except that the first semiconductor chip is mounted on the package substrate by a flip-chip bonding method. 
     Referring to  FIG.  8   , a semiconductor package  200   a  may include the package substrate  210 , the first semiconductor chip  220 , the first interposer  250 , and the molding layer  270 . The first semiconductor chip  220  may be mounted on the package substrate  210  so that the first surface  220   a  of the first semiconductor chip  220  on which the first chip pad  221  is disposed faces toward an upper surface of the package substrate  210 . The first chip pad  221  of the first semiconductor chip  220  may be electrically connected to the upper substrate pad  211  of the package substrate  210  through a connection part  223 . 
     The first interposer  250  may be mounted on the second surface  220   b  of the first semiconductor chip  220 . Because the first interposer  250  is mounted on the second surface  220   b  of the first semiconductor chip  220  on which the first chip pad  221  of the first semiconductor chip  220  is not disposed, the first interposer  250  may cover the whole second surface  220   b  of the first semiconductor chip  220 . 
     An underfill material layer  225  may fill a space between the first semiconductor chip  220  and the package substrate  210 , and may cover the connection part  223 . For example, the underfill material layer  225  may include epoxy resin and may be formed by a capillary under-fill method. In some example embodiments, the underfill material layer  225  may be a non-conductive film. In some example embodiments, the molding layer  270  may directly fill the space between the first semiconductor chip  220  and the package substrate  210 . In this case, the underfill material layer  225  may be omitted. 
       FIG.  9    is a cross-sectional views illustrating a semiconductor package according to an example embodiment of the inventive concepts. A semiconductor package shown in  FIG.  9    may be the same as or substantially similar to the semiconductor package  200   a  shown in  FIG.  8    except further including a second semiconductor chip on the first semiconductor chip and a second interposer on the second semiconductor chip. 
     Referring to  FIG.  9   , a semiconductor package  200   b  may include the package substrate  210 , the first semiconductor chip  220  on the package substrate  210 , a second semiconductor chip  230  stacked on the first semiconductor chip  220 , the first interposer  250  on the first semiconductor chip  220 , a second interposer  260  on the second semiconductor chip  230 , and the molding layer  270 . 
     The second semiconductor chip  230  may be stacked in an offset relation on the first semiconductor chip  220 . That is, a portion of the second semiconductor chip  230  protrudes from the first semiconductor chip  220  in the horizontal direction (e.g., the X direction and/or the Y direction). The second semiconductor chip  230  may be stacked on the first semiconductor chip  220  so that a first surface  230   a  of the second semiconductor chip  230  on which a second chip pad  231  is disposed faces upward and a second surface  230   b  of the second semiconductor chip  230  opposite to the first surface  230   a  thereof faces toward the first semiconductor chip  220 . An adhesive layer  233  may be provided between the second semiconductor chip  230  and the first semiconductor chip  220  to attach the second semiconductor chip  230 . 
     The second chip pad  231  of the second semiconductor chip  230  may be arranged along a side of the second semiconductor chip  230 . The second chip pad  231  may be electrically connected to the upper substrate pad  215  of the package substrate  210  through a conductive wire  281 . 
     In some example embodiments, the first semiconductor chip  220  and the second semiconductor chip  230  may be different types of semiconductor chips. For example, when the first semiconductor chip  220  is a non-memory chip, the second semiconductor chip  230  may be a memory chip. In some example embodiments, the first semiconductor chip  220  and the second semiconductor chip  230  may be the same type of semiconductor chips. In some example embodiments, the semiconductor package  200   b  may be a system in package in which different types of semiconductor chips are electrically connected to each other to operate as one system. 
     The first interposer  250  may be disposed on the first semiconductor chip  220 . The first interposer  250  may include the first interposer substrate  251  and the first heat dissipation pattern  253 . The first interposer  250  may include the interposers  100  and  100   a  described with reference to  FIGS.  1  to  3   . 
     A bottom of the first heat dissipation pattern  253  may contact the first semiconductor chip  220 , and a top of the first heat dissipation pattern  253  may be exposed to the outside. The first heat dissipation pattern  253  may be electrically insulated from the first semiconductor chip  220 , and may include a material having a high thermal conductivity such that the first heat dissipation pattern  253  may be used to release the heat of the first semiconductor chip  220  to the outside. The first TIM  240  may be interposed between the first interposer  250  and the first semiconductor chip  220  to strengthen thermal coupling between the first heat dissipation pattern  253  and the first semiconductor chip  220 . 
     The second interposer  260  may be disposed on the second semiconductor chip  230 . The second interposer  260  may include a second interposer substrate  261  and a second heat dissipation pattern  263 . The second heat dissipation pattern  263  may include a second through electrode penetrating the second interposer substrate  261 , an upper pad on an upper surface of the second interposer substrate  261 , and a lower pad on a lower surface of the second interposer substrate  261 , similar to the first through electrode  2531 , the first upper pad  2532 , and the first lower pad  2533  of the first heat dissipation pattern  253  shown in  FIG.  5   . A top of the second heat dissipation pattern  263  may not be covered by or may protrude above the second interposer substrate  261 . The second interposer  260  may include the interposers  100  and  100   a  described with reference to  FIGS.  1  to  3   . 
     A bottom of the second heat dissipation pattern  263  may contact the second semiconductor chip  230 , and a top of the second heat dissipation pattern  263  may be exposed to the outside. The second heat dissipation pattern  263  may be electrically insulated from the second semiconductor chip  230  and may be include a material having a high thermal conductivity, such that the second heat dissipation pattern  263  may be used to release heat of the second semiconductor chip  230  to the outside. A second TIM  241  may be interposed between the second interposer  260  and the second semiconductor chip  230  to strengthen thermal coupling between the second heat dissipation pattern  263  and the second semiconductor chip  230 . 
     The second interposer  260  may be stacked on the second semiconductor chip  230  not to overlap the second chip pad  231  of the second semiconductor chip  230 . For example, when a plurality of second chip pads  231  of the second semiconductor chip  230  are disposed adjacent to a side edge of the first surface  230   a  of the second semiconductor chip  230 , the second interposer  260  may be spaced apart from the side edge of the first surface  230   a  of the second semiconductor chip  230  by a desired (or alternatively, predetermined) distance not to cover the plurality of second chip pads  231  of the second semiconductor chip  230 . 
       FIGS.  10 A,  10 B, and  10 C  are plan views illustrating a first interposer and a second interposer of the semiconductor package of  FIG.  9    according to some example embodiments of the inventive concepts. 
     Referring to  FIGS.  9  and  10 A , two second semiconductor chips  230  may be stacked on the first semiconductor chip  220 . The second interposer  260  may be stacked on each of the two second semiconductor chips  230 . The two second semiconductor chips  230  may be spaced apart from each other with the first interposer  250  therebetween. In this case, the first interposer  250  may cover the remainder of the second surface  220   b  of the first semiconductor chip  220  other than a portion of the second surface  220   b  of the first semiconductor chip  220  on which the second semiconductor chip  230  is disposed. 
     The first interposer  250  may include a protruded portion (e.g., a downwardly protruded portion along the Z direction) to at least partially surround sidewalls of the second semiconductor chip  230 . For example, when the second chip pad  231  of the second semiconductor chip  230  is disposed adjacent to a first sidewall of the second semiconductor chip  230 , the first interposer  250  may surround second, third, and fourth sidewalls of the second semiconductor chip  230 . 
     Referring to  FIGS.  9  and  10 B , the first interposer  250  may include a plurality of sections disposed on the first semiconductor chip  220 . For example, the first interposer  250  may include a first sub interposer  250   a  on a central region of the second surface  220   b  of the first semiconductor chip  220  and two second sub interposers  250   b  on an edge region of the second surface  220   b  of the first semiconductor chip  220 . The first sub interposer  250   a  may include a first sub interposer substrate  251   a  and a first sub heat dissipation pattern  253   a . Each of the second sub interposers  250   b  may include a second sub interposer substrate  251   b  and a second sub heat dissipation pattern  253   b.    
     The first sub interposer  250   a  and the second sub interposers  250   b  may at least partially surround sidewalls of the second semiconductor chip  230 . For example, when the second chip pad  231  of the second semiconductor chip  230  is disposed adjacent to a first sidewall of the second semiconductor chip  230 , the first sub interposer  250   a  may be disposed to face a second sidewall of the second semiconductor chip  230  that is opposite to the first sidewall of the second semiconductor chip  230 , and the second sub interposers  250   b  may disposed to face opposite third and fourth sidewalls, respectively, of the second semiconductor chip  230 . The third and fourth sidewalls of the second semiconductor chip  230  may be perpendicular to the first and second sidewalls of the second semiconductor chip  230 . 
     Referring to  FIGS.  9  and  10 C , a density of a plurality of first sub heat dissipation patterns  253   a  included in the first sub interposer  250   a  may be different from a density of a plurality of second heat dissipation patterns  263  included in the second interposer  260 . For example, when the heat generation amount of the first semiconductor chip  220  is larger than the heat generation amount of the second semiconductor chip  230 , the density of the plurality of first sub heat dissipation patterns  253   a  included in the first sub interposer  250   a  may increase to improve the heat dissipation of the first semiconductor chip  220 . 
     In some example embodiments, the density of the first heat dissipation patterns  253  (e.g.,  253   a  and  253   b ) of the first interposer  250  may be vary from region to region. For example, the density of the plurality of first sub heat dissipation patterns  253   a  of the first sub interposer  250   a  may be larger than the density of the plurality of second sub heat dissipation patterns  253   b  of each of the second sub interposers  250   b.    
       FIGS.  11 ,  12 ,  13 ,  14 , and  15    are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts. Description of the same contents as described above are briefly made or omitted, for convenience of explanation. 
     Referring to  FIG.  11   , a semiconductor package  200   c  may be substantially the same as or substantially similar to the semiconductor package  200   b  shown in  FIG.  9    except that the first interposer  250  and the second interposer  260  are stacked in the vertical direction (e.g., the Z direction). 
     For example, the semiconductor package  200   c  may include the first interposer  250  on the first semiconductor chip  220  and the second interposer  260  on the second semiconductor chip  230 . The first interposer  250  and the second interposer  260  may be stacked in the vertical direction. The second interposer  260  may cover the first surface  230   a  of the second semiconductor chip  230  and an upper surface of the first interposer  250 . 
     In this case, the second heat dissipation pattern  263  of the second interposer  260  may be aligned with the first heat dissipation pattern  253  of the first interposer  250  in the vertical direction. Thus, the heat of the first semiconductor chip  220  may be released to the outside through the first heat dissipation pattern  253  and the second heat dissipation pattern  263 . Further, a third TIM  243  may be interposed between the first interposer  250  and the second interposer  260  to strengthen thermal coupling between the first heat dissipation pattern  253  and the second heat dissipation pattern  263 . 
     Referring to  FIG.  12   , a semiconductor package  200 d may be substantially the same as or substantially similar to the semiconductor package  200   b  shown in  FIG.  9    except that the second semiconductor chip  230  is mounted on the first semiconductor chip  220  by a flip chip bonding method. 
     For example, the second semiconductor chip  230  may be mounted on the first semiconductor chip  220  through an inter-chip connection  235  and a through silicon via (TSV)  227  in the first semiconductor chip  220 . Further, the second semiconductor chip  230  may be electrically connected to the package substrate  210  through the inter-chip connection  235  and the TSV  227  of the first semiconductor chip  220 . An undefill material layer  237  may fill a space between the second semiconductor chip  230 , and the first semiconductor chip  220  and may enclose the inter-chip connection  235 . 
     The second semiconductor chip  230  may be disposed so that the first surface  230   a  of the second semiconductor chip  230  on which the second chip pad  231  is disposed faces the first semiconductor chip  220 . The second interposer  260  may be disposed on the second surface  230   b  of the second semiconductor chip  230 . Because the second chip pad  231  is not disposed on the second surface  230   b  of the second semiconductor chip  230  on which the second interposer  260  is disposed, the second interposer  260  may cover the whole second surface  230   b  of the second semiconductor chip  230 . A bottom of the first heat dissipation pattern  253  included in the first interposer  250  may contact the first semiconductor chip  220 . A top of the first heat dissipation pattern  253  included in the first interposer  250  may not be covered by or may protrude above the first interposer substrate  251 . A bottom of the second heat dissipation pattern  263  included in the second interposer  260  may contact the second semiconductor chip  230 . A top of the second heat dissipation pattern  263  included in the second interposer  260  may not be covered by or may protrude above the second interposer substrate  261 . 
     Referring to  FIG.  13   , a semiconductor package  200 e may be substantially the same or substantially similar to the semiconductor package  200 d shown in  FIG.  12    except that the first interposer  250  and the second interposer  260  are stacked in the vertical direction. 
     For example, the semiconductor package  200 e may include the first interposer  250  on the first semiconductor chip  220  and the second interposer  260  on the second semiconductor chip  230 . The first interposer  250  and the second interposer  260  may be stacked in the vertical direction. The second interposer  260  may cover the second surface  230   b  of the second semiconductor chip  230  and an upper surface of the first interposer  250 . 
     In this case, the second heat dissipation pattern  263  of the second interposer  260  and the first heat dissipation pattern  253  of the first interposer  250  may be aligned in the vertical direction. Thus, the heat of the first semiconductor chip  220  may be released to the outside through the first heat dissipation pattern  253  and the second heat dissipation pattern  263 . Further, the third TIM  243  may be interposed between the first interposer  250  and the second interposer  260  to strengthen the thermal coupling between the first heat dissipation pattern  253  and the second heat dissipation pattern  263 . 
     Referring to  FIG.  14   , a semiconductor package  200 f may be substantially the same as or substantially similar to the semiconductor package  200 d shown in  FIG.  12    except that the second surface  230   b  of the second semiconductor chip  230  is exposed to the outside. 
     For example, the molding layer  270  may cover sidewalls of the second semiconductor chip  230  and may expose the second surface  230   b  of the second semiconductor chip  230 . The heat of the second semiconductor chip  230  may be released to the outside through the exposed second surface  230   b  of the second semiconductor chip  230 . 
     Referring to  FIG.  15   , a semiconductor package  200 g may be substantially the same as or substantially similar to the semiconductor package  200   b  shown in  FIG.  9    except further including a heat sink  285 . 
     For example, the semiconductor package  200 g may include the heat sink  285  on the first interposer  250  and/or the second interposer  260 . The heat sink  285  may be thermally coupled to the first heat dissipation pattern  253  of the first interposer  250  and/or the second heat dissipation pattern  263  of the second interposer  260 . For example, the heat sink  285  may be connected to the upper pad of the first heat dissipation pattern  253  and/or the upper pad of the second heat dissipation pattern  263 . 
     In some example embodiments, a TIM  287  may be disposed between the first interposer  250  and the heat sink  285  and/or between the second interposer  260  and the heat sink  285 . The TIM  287  may physically fix the heat sink  285  to the first interposer  250  and/or the second interposer  260  and may strengthen thermal coupling between the heat sink  285  and the first heat dissipation pattern  253  of the first interposer  250  and/or between the heat sink  285  and the second heat dissipation pattern  263  of the second interposer  260 . 
       FIGS.  16 ,  17 ,  18 ,  19 , and  20    are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts. Description of the same contents as described above are briefly made or omitted, for convenience of explanation. 
     Referring to  FIG.  16   , a semiconductor package  300  may include the first semiconductor chip  220 , the first interposer  250  on the first semiconductor chip  220 , the molding layer  270  molding the first semiconductor chip  220  and the first interposer  250 , and a redistribution structure  400 . 
     The first semiconductor chip  220  may be disposed so that the first surface  220   a  of the first semiconductor chip  220  on which the first chip pad  221  is disposed faces downward. The redistribution structure  400  may be disposed on the first surface  220   a  of the first semiconductor chip  220 . The first interposer  250  may be disposed on the second surface  220   b  of the first semiconductor chip  220 . 
     The first interposer  250  may include the first interposer substrate  251  and the first heat dissipation pattern  253 . A bottom of the first heat dissipation pattern  253  may contact the first semiconductor chip  220 , and a top of the first heat dissipation pattern  253  may be exposed to the outside. The first TIM  240  may be disposed between the first interposer  250  and the first semiconductor chip  220  to strengthen the thermal coupling between the first heat dissipation pattern  253  and the first semiconductor chip  220 . 
     The redistribution structure  400  may include a first insulation layer  411 , a second insulation layer  413 , and a redistribution pattern  420 . 
     The first insulation layer  411  may be disposed on the first surface  220   a  of the first semiconductor chip  220  and a lower surface of the molding layer  270 . The first insulation layer  411  may include an insulating material (e.g., oxide and/or nitride). The first insulation layer  411  may include an opening to expose the first chip pad  221  of the first semiconductor chip  220 . 
     The redistribution pattern  420  may be disposed on the first insulation layer  411 . A portion of the redistribution pattern  420  may extend along a surface of the first insulation layer  411 , and the other portion of the redistribution pattern  420  may be electrically and physically connected to the first chip pad  221  of the first semiconductor chip  220  through the opening. 
     The second insulation layer  413  may be disposed on the first insulation layer  411  and the redistribution pattern  420 . The second insulation layer  413  may include an insulating material (e.g., oxide and/or nitride). The second insulation layer  413  may include an opening to expose a portion of the redistribution pattern  420 . The external connection terminal  290  may be disposed on a portion of the redistribution pattern  420  exposed through the opening. 
     Referring to  FIG.  17   , a semiconductor package  300   a  may be substantially the same as or substantially similar to the semiconductor package  300  shown in  FIG.  16    except further including the second semiconductor chip  230  on the first semiconductor chip  220  and the second interposer  260  on the second semiconductor chip  230 . 
     For example, the second semiconductor chip  230  may be mounted on the first semiconductor chip  220  through the inter-chip connection  235 . The second semiconductor chip  230  may be electrically connected to the first semiconductor chip  220  through the inter-chip connection  235  and the TSV  227  of the first semiconductor chip  220 . Further, the second semiconductor chip  230  may be electrically connected to the redistribution pattern  420  of the redistribution structure  400  through the inter-chip connection  235  and the TSV  227  of the first semiconductor chip  220 . 
     The second interposer  260  may be disposed on the second surface  230   b  of the second semiconductor chip  230 , and may include the second interposer substrate  261  and the second heat dissipation pattern  263 . The second TIM  241  may be disposed between the second interposer  260  and the second semiconductor chip  230  to strengthen the thermal coupling between the second heat dissipation pattern  263  and the second semiconductor chip  230 . 
     The second semiconductor chip  230  may be disposed so that the first surface  230   a  of the second semiconductor chip  230  on which the second chip pad  231  is disposed faces the first semiconductor chip  220 . The second interposer  260  may be disposed on the second surface  230   b  of the second semiconductor chip  230 . Because the second chip pad  231  is not disposed on the second surface  230   b  of the second semiconductor chip  230 , the second interposer  260  may cover the whole second surface  230   b  of the second semiconductor chip  230 . 
     Referring to  FIG.  18   , a semiconductor package  300   b  may be substantially the same as or substantially similar to the semiconductor package  300   a  shown in  FIG.  17    except that the first interposer  250  and the second interposer  260  are stacked in the vertical direction. 
     For example, the semiconductor package  300   b  may include the first interposer  250  on the first semiconductor chip  220  and the second interposer  260  on the second semiconductor chip  230 . The first interposer  250  and the second interposer  260  may be stacked in the vertical direction. The second interposer  260  may cover the second surface  230   b  of the second semiconductor chip  230  and an upper surface of the first interposer  250 . 
     In this case, the second heat dissipation pattern  263  of the second interposer  260  and the first heat dissipation pattern  253  of the first interposer  250  may be aligned in the vertical direction. Thus, the heat of the first semiconductor chip  220  may be released to the outside through the first heat dissipation pattern  253  of the first interposer  250  and the second heat dissipation pattern  263  of the second interposer  260 . Further, the third TIM  243  may be disposed between the first interposer  250  and the second interposer  260  to strengthen the thermal coupling between the first heat dissipation pattern  253  and the second heat dissipation pattern  263 . 
     Referring to  FIG.  19   , a semiconductor package  300   c  may be the same as or substantially similar to the semiconductor package  300   a  shown in  FIG.  17    except that the semiconductor package  300   c  does not include the second interposer (see  260  of  FIG.  17   ) and the second surface  230   b  of the second semiconductor chip  230  is exposed to the outside. 
     For example, the molding layer  270  may cover sidewalls of the second semiconductor chip  230 , and may expose the second surface  230   b  of the second semiconductor chip  230 . The heat of the second semiconductor chip  230  may be released to the outside through the exposed second surface  230   b  of the second semiconductor chip  230 . 
     Referring to  FIG.  20   , a semiconductor package  300 d may be substantially the same as or substantially similar to the semiconductor package  300   a  shown in  FIG.  17    except that second semiconductor chip  230  is directly connected to the redistribution pattern  420 . 
     Referring to  FIG.  20   , the second semiconductor chip  230  may be disposed in an offset relation on the first semiconductor chip  220 . That is, a portion of the second semiconductor chip  230  protrudes from the first semiconductor chip  220  in the horizontal direction. The first surface  230   a  of the second semiconductor chip  230  on which the second chip pad  231  is disposed may contact the first semiconductor chip  220 . The second chip pad  231  of the second semiconductor chip  230  may be laterally spaced apart from a sidewall of the first semiconductor chip  220 . In this case, a portion of the redistribution pattern  420  may extend in the vertical direction through an opening of the molding layer  270  and may be physically and electrically connected to the second chip pad  231  of the second semiconductor chip  230 . 
       FIGS.  21 A and  21 B  are cross-sectional views illustrating a method of manufacturing the semiconductor package of  FIG.  9    according to an example embodiment of the inventive concepts. Descriptions of the same contents as described above are briefly made or omitted, for convenience of explanation. 
     Referring to  FIG.  21 A , the first semiconductor chip  220  may be positioned on the package substrate  210 . The first semiconductor chip  220  may be mounted on the package substrate  210  by a flip chip bonding method. The first surface  220   a  of the first semiconductor chip  220  on which the first chip pad  221  is provided may face the package substrate  210 . The second semiconductor chip  230  may be stacked on the first semiconductor chip  220  subsequent to mounting the first semiconductor chip  220  on the package substrate  210 . The second semiconductor chip  230  may be offset from the first semiconductor chip  220 . A portion of the second semiconductor chip  230  may protrude from the first semiconductor chip  220  in the horizontal direction. The second semiconductor chip  230  may be fixed to the first semiconductor chip  220  by the adhesive layer  233 . 
     After the second semiconductor chip  230  is stacked, the conductive wire  281  may be formed to connect between the second chip pad  231  of the second semiconductor chip  230  and the upper substrate pad  215  of the package substrate  210  by a wire bonding process. 
     Thereafter, the first TIM  240  covering at least a portion of the first semiconductor chip  220  and the second TIM  241  covering at least a portion of the second semiconductor chip  230  may be formed. For example, the first TIM  240  and the second TIM  241  may be formed by applying a material having a high thermal conductivity onto the first semiconductor chip  220  and the second semiconductor chip  230  through a dispensing method (e.g., a spray coating method). 
     Referring to  FIG.  21 B , the first interposer  250  may be positioned on the first semiconductor chip  220 , and the second interposer  260  may be positioned on the second semiconductor chip  230 . In the state in which the first interposer  250  is positioned on the first TIM  240  and the second interposer  260  is positioned on the second TIM  241 , the first TIM  240  and the second TIM  241  may be cured to fix the first interposer  250  and the second interposer  260  to the first semiconductor chip  220  and the second semiconductor chip  230 , respectively. 
     Thereafter, the molding layer (see  270  of  FIG.  9   ) may be formed to mold the first semiconductor chip  220 , the second semiconductor chip  230 , the first interposer  250 , and the second interposer  260 . The molding layer (see  270  of  FIG.  9   ) may be formed to expose a top of the first heat dissipation pattern  253  of the first interposer  250  and a top of the second heat dissipation pattern  263  of the second interposer  260  to the outside. The molding layer (see  270  of  FIG.  9   ) may be formed by the method the same as or substantially similar to that described with reference to  FIGS.  6 ,  7 A and  7 B . 
     After the molding layer  270  is formed, the individualized semiconductor package  200   a  shown in  FIG.  9    may be completed by a singulation process. 
       FIGS.  22 A,  22 B,  22 C, and  22 D  are cross-sectional views illustrating a method of manufacturing the semiconductor package of  FIG.  17    according to an example embodiment of the inventive concepts. Descriptions of the same contents as described above are briefly made or omitted, for convenience of explanation. 
     Referring to  FIGS.  22 A , the first semiconductor chip  220  may be provided on a carrier CA so that the first surface  220   a  of the first semiconductor chip  220  on which the first chip pad  221  is formed contacts the carrier CA. 
     The second semiconductor chip  230  may be stacked on the first semiconductor chip  220  by a flip chip bonding method after the first semiconductor chip  220  is provided on the carrier CA. In this case, the first surface  230   a  of the second semiconductor chip  230  on which the second chip pad  231  is formed faces the first semiconductor chip  220 . 
     After stacking the second semiconductor chip  230 , the first TIM  240  covering at least a portion of the first semiconductor chip  220  and the second TIM  241  covering at least a portion of the second semiconductor chip  230  may be formed. For example, the first TIM  240  and the second TIM  241  may be formed by applying a material having a high thermal conductivity onto the first semiconductor chip  220  and the second semiconductor chip  230  through a dispensing method (e.g., a spray coating method). 
     Referring to  FIG.  22 B , the first interposer  250  may be positioned on the first semiconductor chip  220 , and the second interposer  260  may be positioned on the second semiconductor chip  230 . In the state in which the first interposer  250  is positioned on the first TIM  240  and the second interposer  260  is positioned on the second TIM  241 , the first TIM  240  and the second TIM  241  may be cured to fix the first interposer  250  and the second interposer  260  to the first semiconductor chip  220  and the second semiconductor chip  230 , respectively. 
     Referring to  FIG.  22 C , the molding layer  270  may be formed to mold the first semiconductor chip  220 , the second semiconductor chip  230 , the first interposer  250 , and the second interposer  260 . The molding layer  270  may be formed to expose a top of the first heat dissipation pattern  253  of the first interposer  250  and a top of the second heat dissipation pattern  263  of the second interposer  260  to the outside. The molding layer  270  may be formed by the method the same as or substantially similar to that described with reference to  FIGS.  6 ,  7 A and  7 B . 
     Referring to  FIG.  22 D , after the molding layer  270  is formed, the resulting structure of  FIG.  22 C  may be separated from the carrier CA of  FIG.  22 C . Thereafter, the redistribution structure  400  may be formed on a surface of the molding layer  270  and the first surface  220   a  of the first semiconductor chip  220  on which the first chip pad  221  is formed. 
     For example, the first insulation layer  411  may be formed on the surface of the molding layer  270  and the first surface  220   a  of the first semiconductor chip  220 . To form the first insulation layer  411 , an insulation layer may be formed to cover the surface of the molding layer  270  and the first surface  220   a  of the first semiconductor chip  220 , and then a portion of the insulation layer may be removed to form an opening to expose the first chip pad  221  of the first semiconductor chip  220 . 
     Thereafter, the redistribution pattern  420  may be formed on the first insulation layer  411 . A portion of the redistribution pattern  420  may be connected to the first chip pad  221  through the opening of the first insulation layer  411 . To form the redistribution pattern  420 , a conductive layer may be formed on the first insulation layer  411  and the first chip pad  221 , and then the conductive layer may be patterned. 
     The second insulation layer  413  may be formed on the first insulation layer  411  and the redistribution pattern  420 . To form the second insulation layer  413 , an insulation layer may be formed to cover the first insulation layer  411  and the redistribution pattern  420 , and then a portion of the insulation layer may be removed to form the opening to expose a portion of the redistribution pattern  420 . 
     The external connection terminal  290  may be formed on the portion of the redistribution pattern  420  exposed through the opening of the second insulation layer  413 . The external connection terminal  290  may be, for example, a solder ball or a bump. After the external connection terminal  290  is formed, the individualized semiconductor package  300   a  shown in  FIG.  17    may be completed by a singulation process. 
     While the present inventive concepts have been shown and described with reference to some example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the present inventive concepts as set forth by the following claims.