Patent Publication Number: US-7218160-B2

Title: Semiconductor integrated circuit

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor integrated circuit, more particularly to a technology for controlling unnecessary power consumption in a flip-flop circuit and further ensuring a high-speed operation when necessary. 
   2. Description of the Related Art 
   The range of a conventional D-flip-flop includes a dynamic type, static type, sense amplifier type and the like. FIG. 18 of IEEE Journal Of Solid-State Circuits, Vol. 34, No. 4, April, 1999, discloses a semi dynamic flip-flop, which represents a circuit example capable of realizing a high-speed operation therein. FIG. 13 of the present invention shows a D-flip-flop of the dynamic type as the circuit example thereof. The dynamic-type D-flip-flop consumes a large quantity of power even when an input data signal D and an output data signal NQ are in a same state, thereby resulting in a large mean current. 
   No. 2001-267889 of the Publication of the Unexamined Patent Applications discloses a circuit example achieving a reduced power consumption. The circuit example is a flip-flop of the static type attached by a clock signal control function. FIG. 14 shows an example of the static type D-flip-flop. In the static-type flip-flop circuit, an internal clock is halted when the input data signal D and output data signal Q are in a same state to thereby result in a reduced power consumption due to halting an internal operation. A problem in the static-type flip-flop circuit is that a setup time is large and an operation at a higher speed is difficult. 
   Abreast of an advancing miniaturization of semiconductor elements, a semiconductor substrate is provided with a sharow trench isolation region (Sharow Trench Isolation) in order to isolate respective transistors or circuit blocks. In forming the sharow trench isolation region, when a distortion is generated in a lattice constant of a molecular structure, which is a characteristic of a diffusion region constituting a source or drain of an MOS-type transistor, the diffusion region of the transistor formed in a neighboring area of the sharow trench isolation region is subject to a stress. The stress causes a mobility of an electric charge to be degraded, thereby resulting in a lower current capacity (Ids) and increased threshold voltage (Vth). 
   SUMMARY OF THE INVENTION 
   A semiconductor integrated circuit according to the present invention comprises: 
   a latch circuit, the latch circuit inputting therein an input data signal, clock signal, and feedback signal and outputting an output data signal; 
   a retaining circuit, the retaining circuit retaining the output data signal; and 
   a feedback circuit, the feedback circuit inputting therein the input data signal and the output data signal and generating a feedback signal based on logic combinations of the input data signal and output data signal, wherein the signal transmission inside the logic circuits is controlled by means of the feedback signal regardless of whether the clock signal is discontinued. 
   The operation of the semiconductor integrated circuit having the foregoing configuration is described below. When the logic combinations of the input data signal and output data signal before and after the clock signal is in an asserted state are not different to each other, if the internal operation of the latch circuit is activated, it results in an unnecessary operation. 
   When the logic combinations of the input data signal and output data signal before and after the clock signal is asserted are not different to each other, the feedback circuit generates the feedback signal for turning off the internal operation of the latch circuit based on the logic combination. 
   The latch circuit halts the internal operation thereof in response to the feedback signal, except the clock signal supplied to the latch circuit, which is not halted. The operation of the semiconductor integrated circuit according to the present invention has its main objective in halting the internal operation of the latch circuit without halting the clock signal. In that manner, the power consumption can be reduced. 
   When the logic combinations of the input data signal and output data signal before and after the clock signal is asserted are different, the feedback signal from the feedback circuit asserts the internal operation of the latch circuit. The latch circuit accordingly restarts its internal operation, to thereby lead a fluctuation of the input data signal into a fluctuation of the output data signal. At that point, the clock signal is continuously being oscillated, thereby enabling a better setup responsiveness and high-speed operation. In brief, the lower power consumption and higher-speed operation, which were so far judged to be incompatible, can be simultaneously achieved. 
   The output data signal is additionally described below. In the case of the D-flip-flop, for example, the output data signal includes, with respect to the input data signal D and clock signal CK, a output data signal Q, and an output data signal NQ which is an inversion logic of the output data signal Q. When the output data signal is referred to in the present invention, one or both of the output data signal Q and output data signal NQ are represented, which is consistent in the following description. 
   The earlier-mentioned case, wherein “the logic combinations of the input data signal and output data signal before and after the clock signal is in the asserted state are not different to each other”, includes, in terms of the first output data signal Q relative to the input data signal D, D=“H”, Q=“H”, and, D=“L”, Q=“L”, and in terms of the second output data signal NQ relative to the input data signal D, D=“H”, NQ=“L”, and, D=“L” and Q=“H”. 
   Preferably, the feedback circuit is supplied with the input data signal and output data signal, and thereby generates a first feedback signal generated based on the output data signal, and a second feedback signal resulting from synthesizing the signal generated based on the output data signal and the input data signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
       FIG. 1  is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to an embodiment 1 of the present invention. 
       FIG. 2  is a circuit diagram illustrating an example of a specific configuration of the semiconductor integrated circuit according to the embodiment 1. 
       FIG. 3  is a waveform chart illustrating an operation of the semiconductor integrated circuit according to the embodiment 1. 
       FIG. 4  is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to an embodiment 2 of the present invention. 
       FIG. 5  is a circuit diagram illustrating an example of a specific configuration of the semiconductor integrated circuit according to the embodiment 2. 
       FIG. 6  is a waveform chart illustrating an operation of the semiconductor integrated circuit according to the embodiment 2. 
       FIG. 7  is a plane view partially illustrating an example of a semiconductor integrated circuit according to an embodiment 3 of the present invention 
       FIG. 8  is a plane view partially illustrating anther example of the semiconductor integrated circuit according to the embodiment 3. 
       FIG. 9  is a circuit diagram illustrating an example of a specific configuration of a semiconductor integrated circuit according to an embodiment 4 of the present invention. 
       FIG. 10  is a block diagram illustrating a configuration of a peripheral circuit of a power supply control circuit in the semiconductor integrated circuit according to the embodiment 4. 
       FIG. 11  is a circuit diagram illustrating an example of a specific configuration of a semiconductor integrated circuit according to an embodiment 5 of the present invention. 
       FIG. 12  is a block diagram illustrating a configuration of a peripheral circuit of a substrate potential control circuit in the semiconductor integrated circuit according to the embodiment 5. 
       FIG. 13  is a circuit diagram illustrating a configuration of a semiconductor integrated circuit according to a conventional technology. 
       FIG. 14  is a circuit diagram illustrating a configuration of another semiconductor integrated circuit according to the conventional technology. 
       FIG. 15  is a circuit diagram illustrating an example of a specific configuration of a semiconductor integrated circuit according to an embodiment 6 of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION 
   A semiconductor integrated circuit according to preferred embodiments of the present invention are described in detail referring to the drawings. 
   Embodiment 1 
     FIGS. 1 through 3  show an embodiment 1 of the present invention. 
   Referring to  FIG. 1 , a reference symbol A 1  denotes a latch circuit inputting therein an input data signal D, clock signal CK and feedback signals S 01  and S 02  and outputting an output data signal NQ. A reference symbol A 2  denotes a retaining circuit retaining the output data signal NQ. A reference symbol A 3  denotes a feedback circuit inputting therein the input data signal D and output data signal NQ and generating the feedback signal S 02  based on logic combinations of the input data signal D and output data signal NQ. For input to the feedback circuit A 3 , a signal line L 2  from the retaining circuit A 2 , as shown in a double-dotted chain line, may be employed in place of a signal line L 1 . A reference symbol  102  denotes an inverter. 
     FIG. 2  is a circuit diagram illustrating a specific configuration of the semiconductor integrated circuit of  FIG. 1 . Reference symbols P 01 –P 10  denote P-type MOS transistors (Pch transistor), and N 01 –N 11  denote N-type MOS transistors (Nch transistor). Reference symbols I 01  and I 02  respectively denote an inverter. The present semiconductor integrated circuit inputs therein the input data signal D and clock signal CK, and outputs a output data Q, and an output data signal NQ, which is an inversion logic of the output data signal Q. Reference symbols C 01  and C 02  denote precharge nodes, and C 03  denotes a data retaining node. Reference symbols S 01  and S 02  denote feedback signals. The latch circuit A 1  comprises a NAND-type dynamic circuit al and a NAND-type dynamic circuit a 2 . 
   The NAND-type dynamic circuit al is comprised of the Pch transistor P 01 , Nch transistor N 02 , Nch transistor N 03 , and Nch transistor N 01 , which are serially connected. To the NAND-type dynamic circuit al are inputted the input data signal D, clock signal CK, and feedback signal S 01  from the feedback circuit A 3 , and the NAND-type dynamic circuit a 1  controls charging/discharging with respect to the precharge node C 01 . The NAND-type dynamic circuit a 1  charges the precharge node C 01  during the period from a fall to rise of the clock signal CK (when the clock signal becomes the “L” level), discharges the charge of the precharge node C 01  during the period from the rise to fall of the clock signal CK (when the clock signal becomes the “H” level) in the case in which the input data signal D and feedback signal S 01  are both at the “H” level, and retains the charge of the precharge node C 01  in the case in which one of the input data signal D and feedback signal S 01  is at the “L” level. 
   The NAND-type dynamic circuit a 2  is comprised of the Pch transistor P 02 , Nch transistor N 04 , Nch transistor N 05 , and Nch transistor N 01 , which are serially connected. To the NAND-type dynamic circuit a 2  are inputted the precharge node C 02 , clock signal CK, and feedback signal S 02  from the feedback circuit A 3 , and the NAND-type dynamic circuit a 2  controls charging/discharging with respect to the precharge node C 02 . The NAND-type dynamic circuit a 2  charges the precharge node C 02  during the period from the fall to rise of the clock signal CK (when the clock signal becomes the “L” level), discharges the charge of the precharge node C 02  during the period from the rise to fall of the clock signal CK (when the clock signal becomes the “H” level) in the case in which the precharge node C 01  and feedback signal S 02  are both at the “H” level, and retains the charge of the precharge node C 02  in the case in which at least one of the precharge node C 01  and feedback signal S 02  is at the “L” level. 
   In order to execute the foregoing operation, the latch circuit A 1  is comprised of a plurality of Pch transistors P 01 –P 07 , a plurality of Nch transistors N 01 –N 07 , and a single inverter I 01 . More specifics are as follows. 
   The latch circuit A 1  comprises: 
   the Pch transistor P 01 , wherein a gate is connected to the clock signal CK, a source is connected to a power supply, and a drain is connected to the precharge node C 01 ; 
   the Nch transistor N 01 , wherein a gate is connected to the clock signal CK and a source is grounded; 
   the Nch transistor N 02 , wherein a gate is connected to the input data signal D and a drain is connected to the precharge node C 01 ; 
   the Nch transistor N 03 , wherein a gate is connected to the feedback signal S 01 , a drain is connected to a source of the Nch transistor N 02 , and a source is connected to a drain of the Nch transistor N 01 ; 
   the Pch transistor P 02 , wherein a gate is connected to the clock signal CK, a source is connected to the power supply, and the drain is connected to the precharge node C 02 ; 
   the Nch transistor N 04 , wherein a a gate is connected to the precharge node C 01  and a drain is connected to the precharge node C 02 ; 
   the Nch transistor N 05 , wherein a gate is connected to the feedback signal S 02 , a drain is connected to a source of the Nch transistor N 04 , and a source is connected to the drain of the Nch transistor N 01 ; 
   the inverter I 01 , wherein an input terminal is connected to the precharge node C 02 ; 
   the Pch transistor P 03 , wherein a gate is connected to an output terminal of the inverter I 01  and a source is connected to the power supply; 
   the Pch transistor P 04 , wherein a gate is connected to the precharge node C 01  and a source is connected to a drain of the Pch transistor P 03 ; 
   the Nch transistor N 06 , wherein a gate is connected to the precharge node C 01 , a source is grounded, and a drain is connected to a drain of the Pch transistor P 04 ; 
   the Pch transistor P 05 , wherein a gate is connected to the precharge node C 02 , a source is connected to the power supply, and a drain is connected to the output data signal NQ; 
   the Nch transistor N 07 , wherein a gate is connected to the drain of the Nch transistor N 06 , a source is grounded, and a drain is connected to the output data signal NQ; 
   the Pch transistor P 06 , wherein a gate is connected to the output terminal of the inverter I 01 , a source is connected to the power supply, and a drain is connected to the precharge node C 02 ; and 
   the Pch transistor P 07 , wherein a gate is connected to the precharge node C 02 , a source is connected to the power supply, and a drain is connected to the precharge node C 01 . 
   Referring to the foregoing configuration, the latch circuit A 1  may be configured such that, in the case in which the feedback signal S 01  and feedback signal S 02  are the signals of the inversion logic, the Pch transistors are replaced by the Nch transistors, the Nch transistors are replaced by the Pch transistors, the power supplies are replaced by the grounds, and the grounds are replaced by the power supplies. 
   The retaining circuit A 2  comprises: 
   the Pch transistor P 08 , wherein a gate is connected to the output data signal NQ and a source is connected to a power supply; 
   the Nch transistor N 08 , wherein a gate is connected to the output data signal NQ, a source is grounded, and a drain is connected to a drain of the Pch transistor P 08 ; 
   the Pch transistor P 09 , wherein a gate is connected to the drain of the Nch transistor N 08 , a source is connected to the power supply, and a drain is connected to the feedback signal S 01 ; and 
   the Nch transistor N 09 , wherein a gate is connected to the drain of the Nch transistor N 08 , a source is grounded, and a drain is connected to the feedback signal S 01 . 
   To the feedback circuit A 3  are inputted the input data signal D and output data signal NQ. The feedback circuit A 3  generates the feedback signal S 02  by means of the signal generated based on the output data signal NQ and input data signal D. 
   The feedback circuit A 3  specifically comprises: 
   the Pch transistor P 10 , wherein a gate is connected to the input data signal D, a drain is connected to the feedback signal S 02  and a source is connected to the drain of the Pch transistor P 08 ; 
   the Nch transistor N 10 , wherein a gate is connected to the input data signal D, a drain is connected to the feedback signal S 02 , and a source is grounded; and 
   the 11th Nch transistor N 11 , wherein a gate is connected to the output data signal NQ, a drain is connected to the feedback signal S 02 , and a source is grounded. 
   The feedback signal S 01  internally generated and outputted by latch circuit A 1  is a signal of logic inversion resulting from the logic inversion of the output data signal NQ. The feedback signal S 01  serves to control permission/prohibition of the discharge with respect to the NAND-type dynamic circuit a 1 , and is connected to the gate of the Nch transistor N 03 . The feedback signal S 02  generated and outputted by the feedback circuit A 3  is generated based on the input data signal D and output data signal NQ. The feedback signal S 02  serves to control permission/prohibition of the discharge with respect to the NAND-type dynamic circuit a 2 , and is connected to the gate of the Nch transistor N 05 . The feedback signal S 02  is always at the “L” level when the output data signal Q is at the “L” level. The feedback signal S 02  is still at the “L” level when the output data signal Q is at the “H” level and the input data signal D is also at the “H” level, and changed to the “H” level when the input data signal D is at the “L” level. Though the output data signal Q and output data signal NQ are shown in  FIG. 2 , there is no problem in providing either the output data signal Q alone or output data signal NQ alone. 
     FIG. 3  is a waveform chart illustrating an operation of the semiconductor integrated circuit configured as in  FIG. 2 .
     1) At time T 0 , the clock signal CK is at the “L” level, and the Pch transistors P 01  and P 02  are turned on, while the Nch transistor N 01  is turned off. At that time, the input data signal D and output data signal Q are both at the “L” level. The output data signal NQ is at the “L” level, the data retaining node C 03  is at the “L” level, and the feedback signal S 01  is at the “H” level, therefore the Nch transistor N 03  is in the ON state. However, the Nch transistor N 02  is in the OFF state because the input data signal D is at the “L” level, and further, the Nch transistor N 01  is also in the OFF state because of the clock signal CK at the “L” level. Accordingly, the precharge node C 01  is precharged to the “H” level. The Nch transistor N 11  is in the ON state because of the output data signal NQ at the “H” level, while the Nch transistor N 05  is in the OFF state because of the feedback signal S 02  at the “L” level. The Nch transistor N 04  is in the ON state because of the precharge node C 01  at the “H” level, whereas the Nch transistor N 05  is in the OFF state, therefore the precharge node C 02  is precharged to the “H” level.   
   As describe above, the precharge node C 01  and precharge node C 02  are both precharged to the “H” level at the time T 0 . Below is described the state of the rest of the configuration at the time of the precharge. The output of the inverter I 01  is at the “L” level because of the precharge node C 02  at the “H” level, as a result of which the Pch transistors P 06  and P 03  are in the ON state. Further the Pch transistors P 07  and  05  are in the OFF state. The Nch transistor N 06  is in the ON state because the precharge node C 01  is at the “H” level, and the Pch transistor P 04  is OFF. The Nch transistor N 07  is OFF because the Nch transistor N 06  is in the ON state and connected to the ground. The Pch transistor P 08  is OFF because the output data signal NQ is at the “H” level, and the Nch transistor N 08  is in the ON state. The Pch transistor P 10  is ON because of the input data signal D at the “L” level, and the Nch transistor N 10  is in the ON state. The Pch transistor P 09  is ON because the Nch transistor N 08  is ON and connected to the ground, and the Nch transistor N 09  is OFF. The data retaining node C 03  in the data retaining circuit A 2  is at the “L” level.
     2) It is assumed that the clock signal CK rises at the “H” level at time T 1 . The input data signal D is then at the “L” level, and the output data signal Q is at the “L” level. To put it differently, the input data signal D and output data signal Q both serve as conditions for halting the internal operation of the latch circuit at the “L” level. The Pch transistors P 01  and P 02  are both inverted to OFF, while the Nch transistor N 01  is inverted to ON. The Nch transistor N 02  remains the OFF state because the input data signal D stays at the “L” level. Therefore, the precharge node C 01  is not discharged, and remains the “H” level retaining the charge. Meanwhile, the Nch transistor N 05  keeps its OFF state because the feedback signal S 02  stays at the “L” level. Therefore, the precharge node C 02  is not discharge, and remains the “H” level retaining the charge. The Pch transistor P 05  and Nch transistor N 07  in an output stage of the latch circuit A 1  both remain the OFF state. Therefore, the output data signal NQ and output data signal Q remain the same state, and the feedback signal S 01  and feedback signal S 02  stay the same.   

   When the output data signal Q is at the “L” level, and the input data signal D is at the “L” level, a result obtained by the rise of the clock signal CK is the “L” level, which is the same as the original state of the output data signal Q, meaning that the halt of the internal operation of the latch circuit leads to the same result. The halt of the internal operation of the latch circuit achieves the reduction of the power consumption. Importantly, the internal operation of the latch circuit is halted by means of, not the discontinued supply of the clock signal CK, but the control of the signal transmissions inside a logic circuit. This accelerates a response speed in 4) after the cancellation of the conditions for halting the internal operation of the latch circuit, which is described in 3) below.
     3) It is assumed that the input data signal D rises from the “L” level to the “H” level at Time T 2 . The logic combinations of the input data signal D and output data signal Q results in inconsistency, and the conditions for halting the internal operation of the latch circuit are thereby cancelled.   4) Then, it is assumed that the clock signal CK rises to the “H” level at time T 3 . When the input data signal D is inverted to the “H” level, the Nch transistor N 10  is turned on, while the feedback signal S 02  stays at the “L” level. Further, the Nch transistor N 02  is turned on in response to the inversion of the input data signal D to the “H” level. At that time, the Nch transistor N 03  is in the ON state because the feedback signal S 01  is already at the “H” level, and the Nch transistor N 01  is in the ON state in response to the rise of the clock signal CK. Accordingly, the precharge node C 01  is connected to the ground and thereby discharged.   

   When the precharge node C 01  goes to the “L” level as a result of the discharge, an influence therefrom is transmitted to the Nch transistors N 06  and N 04 . 
   The Nch transistor N 06  is inverted to the OFF state, while the Pch transistor P 04  is inverted to the ON state. Because of the Pch transistor P 03  in the ON state, the gate of the Nch transistor N 07  is inverted to the “H” level, thereby leaving the Nch transistor N 07  in the ON state. The output state of the latch circuit A 1  is accordingly switched over. More specifically, because the Nch transistor N 07  is connected to the ground, the output data signal NQ is inverted to the “L” level from the past “H” level. Correspondingly, the output data signal Q is inverted from the “L” level to the “H” level. The output data signal Q is consequently at the “H” level as well as the input data signal D. At the same time, the feedback signal S 01  is inverted to the “L” level. When the feedback signal S 01  goes to the “L” level, the Nch transistor N 03  returns to the OFF state, and the precharge node C 01  is in a charge-permission standby state. 
   The Nch transistor N 04  is OFF in accordance with the inversion of the precharge node C 01  to the “L” level. The precharge node C 02  is at the “H” level retaining the charge. 
   The inversion of the output data signal NQ to the “L” level is retained in the data retaining circuit A 2 . The output of the inverter (P 08  and N 08 ) is inverted, and the data retaining node C 03  is inverted to the “H” level. The output of the inverter (P 09  and N 09 ) is kept at the “L” level. 
   As described, when the input data signal D is inverted from the “L” level to the “H” level, in the state of which the clock signal CK rises, the output data signal Q is inverted from the “L” level to the “H” level. More specifically, the internal operation of the latch circuit is restarted at a high speed in response to the rise of the clock signal CK after the conditions for halting the internal operation of the latch circuit are cancelled, which is because of the continuous oscillation of the clock signal CK. 
   The operation during the foregoing period establishes the conditions for halting the internal operation of the latch circuit that the input data signal D and output data signal Q are both at the “H” level.
     5) When the clock signal CK falls to the “L” level at time T 4 , the Pch transistors P 01  and P 02  are tuned on, and the precharge node C 01 , which was at the “L” level immediately prior thereto, is precharged to the “H” level. At that time, the Nch transistor N 03  is in the OFF state because the feedback signal S 01  is at the “L” level, thereby compensating for the precharge. Further, the supplementary charge is supplied to the precharge node C 02 .   6) The clock signal CK rises to the “H” level at time T 5 . At that time, the input data signal D and output data signal Q are both at the “H” level, meaning that the conditions for halting the internal operation of the latch circuit are established. In response to the rise of the clock signal CK, the Pch transistors P 01  and P 02  are inverted to OFF, while the Nch transistor N 01  is inverted to ON. Further, the Nch transistor N 02  is in the ON state because the input data signal D is at the “H” level. The Nch transistor N 03  remains the OFF state because of the feedback signal S 01  staying at the “L” level. Therefore, there is no discharge with respect to the precharge node C 01 , which remains the “H” level retaining the charge. In contrast to that, the Nch transistor NOS is continuously in the OFF state because of the feedback signal S 02  at the “L” level. Therefore, there is no discharge with respect to the precharge node C 02 , which stays at the “H” level retaining the charge. Accordingly, the Pch transistor P 05  and Nch transistor N 07  in the output stage of the latch circuit A 1  are both continuously in the OFF state. Hence, the output data signal NQ and output signal Q are still in the same state, and the feedback signal S 01  and feedback signal S 02  stay the same.   

   Compared to 4), in 4), the precharge node C 01  is discharged in response to the rise of the clock signal CK, which results in the active operation of the latch circuit A 1  because of the cancellation of the conditions for halting the internal operation of the latch circuit that the input data signal D is at the “H” level and output data signal Q is at the “L” level immediately prior to the rise of the clock signal CK. 
   In the case of 6), neither the precharge node C 01  nor precharge node C 02  is discharged despite the rise of the clock signal CK, which results in the halt of the latch circuit because of the establishment of the conditions for halting the internal operation of the latch circuit that the input data signal D and output data signal Q are both at the “H” level immediately prior to the rise of the clock signal CK. 
   When the output data signal Q is at the “H” level, and the input data signal D is at the “H” level, the result obtained from the rise of the clock signal CK is the “H” level, which is the same as the original state of the output data signal Q, meaning that the halt of the internal operation of the latch circuit leads to the same result. The halt of the internal operation of the latch circuit can achieve the reduction of the power consumption. Importantly, the internal operation of the latch circuit is halted by means of, not the discontinued supply of the clock signal CK, but the control of the signal transmissions inside the logic circuit. This accelerates the response speed in 7) after the cancellation of the conditions for halting the internal operation of the latch circuit in 6), which is described below.
     7) It is assumed that the input data signal D falls from the “H” level to the “L” level at Time T 6 . The logic combinations of the input data signal D and output data signal Q results in inconsistency, and the conditions for halting the internal operation of the latch circuit are thereby cancelled. In that manner, the Nch transistor N 10  is inverted to the OFF state, while the Pch transistor P 10  is inverted to the ON state. The Pch transistor P 08  is already in the ON state, therefore the feedback signal S 02  is inverted from the “L” level to the “H” level. As a result, the Nch transistor N 05  is inverted to the ON state. Then, a discharge-permission standby state arrives. However, because the clock signal CK is at the “L” level, the Pch transistor P 02  is in the ON state, and the Pch transistor P 06  is also in the ON state, the precharge node C 02  is still continuously charged.   8) It is assumed that the clock signal CK rises to the “H” level at time T 7 . The Pch transistor P 01  is turned off, and charging the precharge node C 02  is discontinued. Though the Nch transistor N 01  is turned on, the Nch transistor N 03  maintains its ON state because the feedback signal S 01  is at the “L” level. The precharge node C 01  is at the “H” level retaining the charge. Meanwhile, the Pch transistor P 02  is turned off, charging the precharge node C 02  is also discontinued. At that time, the feedback signal S 02  is already inverted to the “H” level, and in conjunction with the inversion, the Nch transistor N 05  is switched over to the ON state. The Nch transistor N 04  is originally in the ON state, and the Nch transistor N 01  is already turned on in response to the rise of the clock signal CK, therefore the precharge node C 02  starts to discharge. When the potential of the precharge node C 02  descends, and the output of the inverter I 01  is inverted to the “H” level, the Pch transistor P 06  is turned off, resulting in a rapid drop of the potential of the precharge node C 02 .   

   When the precharge node C 02  goes to the “L” level as a result of the foregoing discharge, the Pch transistor P 05  is inverted to the ON state. The Nch transistor N 07  is still in the ON state. Hence, the output state of the latch circuit A 1  is switched over. More specifically, the output data signal NQ is inverted from the past “L” level to the “H” level since the Pch transistor P 05  is connected to a power supply potential VDD. Correspondingly, the output data signal Q is inverted from the “H” level to the “L” level. This results in the establishment of the conditions for halting the internal operation of the latch circuit that the input data signal D and output data signal Q are both at the “L” level. At the same time, the feedback signal S 01  is inverted to the “H” level. When the feedback signal S 01  goes to the “H” level, the Nch transistor N 03  is returned to the ON state, leaving the precharge node C 01  in the discharge-permission standby state. In response to the inversion of the precharge node C 02  to the “L” level, the Pch transistor P 07  is turned on, and the precharge node C 01  is thereby additionally charged. 
   The inversion of the output data signal NQ to the “H” level is retained in the data retaining circuit A 2 . The output of the inverter (P 08  and N 08 ) is inverted, thereby inverting the data retaining node C 03  to the “L” level. The output of the inverter (P 09  and N 09 ) is kept at the “H” level. 
   As described, when the input data signal D is inverted from the “H” level to the “L” level, in the state of which the clock signal CK rises, the output data signal Q is inverted from the “H” level to the “L” level. This is because the conditions for halting the internal operation of the latch circuit (input data signal D and output data signal Q are both at “H” level) are previously cancelled. 
   When the output data signal NQ is inverted to the “H” level, and the feedback signal S 01  goes to the “H” level, the Nch transistor N 03  is inverted to the ON state, leaving the precharge node C 01  in the discharge-permission standby state. 
   Further, in response to the inversion of the output data signal NQ to the “H” level, the Nch transistor N 11  in the feedback circuit A 3  is inverted to the ON state, and the feedback signal S 02  is inverted from the “H” level to the “L” level. Then, the Nch transistor N 05  is accordingly inverted to the OFF state, leaving the precharge node C 02  in the charge-permission standby state.
     9) It is assumed that the clock signal CK rises to the “L” level at time T 8 . The Pch transistors P 01  and P 02  are turned on, and the precharge node C 02 , which was at the “L” level immediately prior thereto, is precharged to the “H” level. At that time, the Nch transistor N 05  is in the OFF state because the feedback signal S 02  is at the “L” level, thereby compensating for the precharge. The precharge node C 01  is also supplied with the additional charge. At this point, the state of 1) at the time T 0  is regained.   

   The summary of the present embodiment described so far is as follows. 
   When the conditions for halting the internal operation of the latch circuit that the input data signal D and output data signal Q are both at the “L” level or “H” level are established, the internal operation of the latch circuit A 1  can be halted irrespective of the fluctuation of the clock signal CK to thereby achieve a low power consumption. Further, because the internal operation of the latch circuit A 1  is halted along with the continuous oscillation of the clock signal CK, the logic combination is either “H” and “L”, or “L” and “H”, thereby achieving the accelerated setup after the cancellation of the conditions for halting the internal operation of the latch circuit. 
   The high-speed operation of the semiconductor integrated circuit according to the present invention is verified using a circuit simulation data. 
   A limit value for the setup is defined as a delay by 5% compared to a delay value obtained by clock signal CK minus output data signal NQ when the value of the input data signal D is determined with a sufficient length of time prior to the rising edge of the clock signal CK. Then, the delay states of the input data signal D and output data signal NQ when the input data signal D is determined at the setup limit value is verified. 
   Conditions for the simulation are set as follows. 
   In  FIGS. 2 ,  13  and  14 , a saturation current per unit width in all the Nch transistors is set to 380 μA/μm, and a threshold voltage thereof is set to 300 mV. A saturation current per unit width in all the Pch transistors is set to 160 μA/μm, and a threshold voltage thereof is set to −300 mV. The power supply voltage VDD is set to 1.3V, and a channel length of all the transistors is set to 0.12 μm. 
   Further, the following assumption is provided for the configuration of  FIG. 2 . 
   The transistors having the channel width of 2 μm are the Nch transistors N 01 , N 02 , N 03 , N 04 , N 05  and N 07 , and Pch transistors P 08  and P 10 . The transistors having the channel width of 0.4 μm are the Nch transistors N 06 , N 08 , N 09 , N 10 , and N 11 , and Pch transistors P 01 , P 02 , P 06 , P 07  and P 09 . The transistors having the channel width of 1.6 μm are the Pch transistors P 03  and P 04 . The transistor having the channel width of 1.6 μm is the Pch transistor P 05 . 
   Regarding the inverters, the Pch transistors of the inverter I 01  have the channel width of 0.8 μm, the Nch transistors of the inverter I 01  have the channel width of 0.4 μm, the Pch transistors of the inverter I 02  have the channel width of 5.4 μm, and the Nch transistors of the inverter I 02  have the channel width of 3.2 μm. 
   The configuration shown in  FIG. 18  of IEEE Journal Of Solid-State Circuits, Vol. 34, No. 4, April, 1999 is shown in  FIG. 13  of the present invention for which the following assumption is provided. An Nch transistor N 201  has the channel width of 3.6 μm. An Nch transistor N 202  has the channel width of 4.9 μm. An Nch transistor N 203  has the channel width of 5.5 μm. An Nch transistor N 204  has the channel width of 1.7 μm. An Nch transistor N 205  has the channel width of 1.7 μm. A Pch transistor P 201  has the channel width of 0.8 μm. A Pch transistor P 202  has the channel width of 5.5 μm. A Pch transistor of an inverter  1201  has the channel width of 1.16 μm. An Nch transistor of the inverter I 201  has the channel width of 0.6 μm. A Pch transistor of an inverter I 202  has the channel width of 0.8 μm. An Nch transistor of the inverter I 202  has the channel width of 0.4 μm. A Pch transistor of an inverter I 203  has the channel width of 0.4 μm. An Nch transistor of the inverter I 203  has the channel width of 0.4 μm. A Pch transistor of an inverter I 204  has the channel width of 0.4 μm. An Nch transistor of the inverter I 204  has the channel width of 1.2 μm. Pch transistors of an inverter I 205  have the channel width of 5.4 μm. An Nch transistor of the inverter I 205  has the channel width of 3.1 μm. A Pch transistor of an inverter I 206  has the channel width of 0.6 μm. An Nch transistor of the inverter I 206  has the channel width of 0.4 μm. Two Pch transistors of an AND gate A 201  have the channel width of 0.5 μm. Two Nch transistors of the AND gate A 201  have the channel width of 1.9 μm. 
   In  FIG. 14 , A Pch transistor of an inverter  10   h  has the channel width of 0.8 μm. An Nch transistor of the inverter  10   h  has the channel width of 0.4 μm. A Pch transistor of a transmission gate  10   i  has the channel width of 1.0 μm. An Nch transistor of the transmission gate  10   i  has the channel width of 0.5 μm. A Pch transistor of an inverter  10   j  has the channel width of 1.6 μm. An Nch transistor of the inverter  10   j  has the channel width of 0.8 μm. A Pch transistor of a transmission gate  10   c  has the channel width of 2.0 μm. An Nch transistor of the transmission gate  10   c  has the channel width of 1.0 μm. A Pch transistor of an inverter  10   d  has the channel width of 1.6 μm. An Nch transistor of the inverter  10   d  has the channel width of 0.8 μm. A Pch transistor of an inverter  10   e  has the channel width of 5.2 μm. An NchS transistor of the inverter  10   e  has the channel width of 3.2 μm. A Pch transistor of an inverter  10   a  has the channel width of 5.2 μm. An Nch transistor of the inverter  10   a  has the channel width of 3.2 μm. Two Pch transistors of a clocked inverter  10   g  have the channel width of 0.4 μm. Two Nch transistors of the clocked inverter  10   g  have the channel width of 0.4 μm. A Pch transistor PM 1  has the channel width of 1.5 μm. A Pch transistor PM 2  has the channel width of 1.5 μm. An Nch transistor NM 1  has the channel width of 1.0 μm. An Nch transistor NM 2  has the channel width of 1.0 μm. A Pch transistor of an inverter  11  has the channel width of 0.4 μm. An Nch transistor of the inverter  11  has the channel width of 0.4 μm. Three Pch transistors of an AND gate  13  have the channel width of 0.4 μm. Three Nch transistors of the AND gate  13  have the channel width of 0.4 μm. Two Pch transistors of an NOR gate  15  have the channel width of 0.8 μm. Two Nch transistors of the NOR gate  15  have the channel width of 0.4 μm. Two Pch transistors of an NAND gate  17  have the channel width of 0.4 μm. Two Nch transistors of the NAND gate  17  have the channel width of 0.4 μm. Two Pch transistors of an inverter  19  have the channel width of 1.6 μm. Two Nch transistors of the inverter  19  have the channel width of 0.8 μm. 
   As a result of the circuit simulation based on the conditions set as above, the delay time from the time when the input data signal D rises until the time when the output data signal NQ rises in  FIG. 2  was 320 ps, while the delay time from the time when the input data signal D falls until the time when the output data signal NQ falls was 460 ps. 
   In contrast to the foregoing result, the delay time from the time when the input data signal D rises until the time when the output data signal NQ rises in  FIG. 13  was 720 ps, while the delay time from the time when the input data signal D falls until the time when the output data signal NQ falls was 500 ps. 
   Further, the delay time from the time when the input data signal D rises until the time when the output data signal NQ rises in  FIG. 14  was 890 ps, while the delay time from the time when the input data signal D falls until the time when the output data signal NQ falls was 890 ps. 
   As described, in the circuit configuration of the latch circuit according to the embodiment 1 of the present invention, the second stage of a dynamic D-flip-flop, which is originally of a static type, is replaced by the same of the dynamic NAND type, and the feedback circuit is serially provided with the Nch transistors in the data input units of the first and second stages. When the input data signal D and output data signal Q are in the same state, the internal operation of the latch circuit is halted based on the logics of the input data signal D and output data signal Q to thereby reduce the power consumption and further maintain the high-speed operation of the dynamic circuit itself. 
   The circuit configuration of the latch circuit according to the embodiment 1 of the present invention, in addition to the described effects, has the advantage that the latch circuit A 1  is still operable when the voltage level of the clock signal CK is lower than the operation voltage of the latch circuit A 1  with no flow of any stationary through current. The reason for that is described referring to  FIGS. 2 and 3 . 
   At time T 3 , in the case in which the voltage value of the clock signal CK at the logic “H” level is low, however only exceeds the threshold level of the Nch transistor N 01  when the capabilities of the precharging Pch transistors P 01  and P 02  are poor, the Nch transistors N 02  and N 03  are in the ON state. Accordingly, the precharge node C 01  is discharged. In the foregoing state, the Pch transistor P 01  is not completely turned off, allowing the Nch transistors N 02  and N 03  to be in the ON state, thereby generating the through current. However, the Nch transistor N 03  is immediately turned off to thereby stop the through current. 
   Further, at time T 7 , in the case in which the voltage value of the clock signal CK at the logic “H” level is low, however only exceeds the threshold level of the Nch transistor N 01  when the capabilities of the precharging Pch transistors P 01  and P 02  are poor, the Nch transistors N 04  and N 05  are in the ON state. Accordingly, the precharge node C 02  is discharged. In the foregoing state, the Pch transistor P 02  is not completely turned off, allowing the Nch transistors N 04  and N 05  to be in the ON state, thereby generating the through current. However, the Nch transistor N 05  is immediately turned off to thereby stop the through current. 
   As described, in the circuit configuration shown in  FIG. 2 , the oscillation width of the clock can be reduced to thereby cut down on the charge/discharge energy. Thus, the power consumption in the semiconductor integrated circuit can be further reduced. 
   Embodiment 2 
     FIG. 4  is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to an embodiment 2 of the present invention. Reference symbols A 11 , A 12  and A 13  respectively denote a latch circuit, data retaining circuit, and feedback circuit. A signal line L 12 , which is shown in a double-dotted chain line, may be used for input to the feedback circuit A 13  in place of a signal line L 11 . 
     FIG. 5  is a circuit diagram illustrating an example of a configuration of the semiconductor integrated circuit according to the embodiment 2. In  FIG. 5 , A 11 , A 12  and A 13  shown in  FIG. 4  are correspondingly represented. Reference symbols P 101 –P 113  denote Pch transistors, N 101 –N 117  denote Nch transistors, and I 101 –I 104  denote inverters. D 1  denotes an input data signal having a low transition probability. D 2  denotes an input data signal having a high transition probability. SEL denotes an input data signal selection signal. CK denotes a clock signal. Q and NQ denote output data signals. C 101  and C 102  denote the precharge nodes. C 103  denotes a data retaining node. S 101  and S 102  denote the feedback signals. 
   The semiconductor integrated circuit according to the embodiment 2 comprises: 
   the latch circuit A 11  inputting therein the input data signals D 1  and D 2 , input data signal selection signal SEL, clock signal CK, and feedback signals S 101  and S 102  and outputting the output data signal NQ; 
   the retaining circuit A 12  retaining the output data signal NQ; 
   the feedback circuit A 13  inputting therein the input data signals D 1 , input data signal selection signal SEL, and output data signal NQ, 
   the feedback circuit A 13  controlling the feedback signals S 101  and S 102  based on the logic combinations of the input data signal D 1  and output data signal NQ when the input data signal selection signal SEL selects the input data signal D 1 , 
   the feedback circuit A 13  always outputting a constant value as the feedback signals S 101  and S 102  when the input data signal selection signal SEL selects the input data signal D 2 , characterized in that 
   an internal operation of the latch circuit A 11  is turned on/off by means of the feedback signals S 101  and S 102  when the input data signal selection signal SEL selects the input data signal S 01 , and the internal operation of the latch circuit A 11  is constantly activated when the input data signal selection signal SEL selects the input data signal D 2 . 
   The operation according to the foregoing configuration is as follows. When the input data signal selection signal SEL selects the input data signal D 1 , the same function as in the embodiment 1 is exerted. More specifically, when the logic combinations of the input data signal D 1  and output data signal NQ are not different before and after the clock signal CK is asserted, the feedback circuit A 12  generates the feedback signals S 101  and S 102  serving to turn off the internal operation of the latch circuit A 11  based on the logic combination. The latch circuit A 11  accordingly halts the internal operation thereof based on the feedback signals S 101  and S 102 , though the clocks signal CK supplied to the latch circuit A 11  is not halted. An important factor in the embodiment 2 is that the internal operation of the latch circuit A 11  is not halted without halting the clock signal CK. This enables the power consumption to be reduced. Next, when the logic combinations of the input data signal D 1  and output data signal NQ are different before and after the clock signal CK is asserted, the feedback signals S 101  and S 102  from the feedback circuit A 13  assert the internal operation of the latch circuit A 11 , in response to which the latch circuit A 11  restarts its internal operation, leading the fluctuation of the input data signal into the fluctuation of the output data signal. At that time, the clock signal CK is being continuously oscillated, thereby achieving the setup with a better responsiveness and the operation at a higher speed. Thus, the low power consumption and high-speed operation, which were so far regarded as incompatible, can be simultaneously achieved. When the input data signal selection signal SEL selects the input data signal D 2 , the same operation as in a general dynamic-type semiconductor integrated circuit is obtained, in which the high-speed operation is guaranteed. 
   For the input data signal D 1  is set a signal having the low transition probability, and for the input data signal D 2  is set a signal having the high transition probability. In the case of a logic circuit comprised of a group of flip-flops, for example, an input data signal in normal operation corresponds to the input data signal D 1 , and an input data signal in a test operation as a scan chain corresponds to the input data signal D 2 . 
   The latch circuit Al 1  of the semiconductor integrated circuit according to the embodiment 2 comprises a dynamic circuit a 11  and a NAND-type dynamic circuit a 12 . The dynamic circuit a 11  is configured in the following manner. In the case in which the input data signal selection signal SEL selects the input data signal D 1 , the input data signal D 1  and the feedback signal S 101  outputted so as to have an inverted polarity relative to the input data signal D 1  based on the output data signal NQ is inputted. The precharge node C 101  is charged during the period from the fall to rise of the clock signal CK (when the clock signal becomes the “L” level). The charge is discharged from the precharge node C 101  during the period from the rise to fall of the clock signal CK (when the clock signal becomes the “H” level) when the input data signal D 1  and feedback signal S 101  are both at the “H” level. The charge of the precharge node C 101  is retained when one of the input data signal D 1  and feedback signal S 101  is at the “L” level. Further, in the case in which the input data signal selection signal SEL selects the input data signal D 2 , the charge of the precharge node C 101  is discharged when the input data signal D 2  is at the “H” level, and the charge of the precharge node C 101  is retained when the input data signal D 2  is at the “L” level. 
   The NAND-type dynamic circuit a 12  is configured in the following manner. In the case in which the input data signal selection signal SEL selects the input data signal D 1 , the input data signal D 1  and the feedback signal S 102  as a logical sum of a signal, which is outputted so as to have a same polarity as the input data signal D 1  based on the precharge node C 101  and output data signal NQ is inputted. The precharge node C 102  is charged during the period from the fall to rise of the clock signal CK (when the clock signal becomes the “L” level). The charge is discharged from the precharge node C 102  during the period from the rise to fall of the clock signal CK (when the clock signal becomes the “H” level) when the precharge node C 101  and feedback signal S 102  are both at the “H” level. The charge of the precharge node C 102  is retained when one of the precharge node C 101  and feedback signal S 102  is at the “L” level. Further, in the case in which the input data signal selection signal SEL selects the input data signal D 2 , the charge of the precharge node C 102  is discharged when the input data signal selection signal SEL is at the “H” level and the precharge node C 101  is at the “H” level, and the charge of the precharge node C 102  is retained when the precharge node C 101  is at the “L” level. 
   The latch circuit A 11  comprises a plurality of Pch transistors P 101 –P 107  and a plurality of Nch transistors N 101 –N 107 , N 117  and N 118  and a single inverter I 101 . More specifically, the latch circuit comprises: 
   the Pch transistor P 101 , wherein a gate is connected to the clocks signal CK, a source is connected to a power supply, and a drain is connected to the precharge node C 101 ; 
   the Nch transistor N 101 , wherein a gate is connected to the clock signal CK and a source is grounded; 
   the Nch transistor N 102 , wherein a gate is connected to the input data signal D 1  and a drain is connected to the precharge node C 101 ; 
   the Nch transistor N 103 , wherein a gate is connected to the feedback signal S 101 , a drain is connected to a source of the Nch transistor N 102 , and a source is connected to a drain of the Nch transistor N 101 ; 
   the Pch transistor P 102 , wherein a gate is connected to the clock signal CK, a source is connected to the power supply, and a drain is connected to the precharge node C 102 ; 
   the Nch transistor N 104 , wherein a gate is connected to the precharge node C 101  and a drain is connected to the precharge node C 102 ; 
   the Nch transistor N 105 , wherein a gate is connected to the feedback signal S 102 , a drain is connected to a source of the Nch transistor N 104 , and a source is connected to the drain of the Nch transistor N 101 ; 
   the inverter I 101 , wherein an input terminal is connected to the precharge node C 102 ; 
   the Pch transistor P 103 , wherein a gate is connected to an output terminal of the inverter I 101  and a source is connected to the power supply; 
   the Pch transistor P 104 , wherein a gate is connected to the precharge node C 101  and a source is connected to a drain of the Pch transistor P 103 ; 
   the Nch transistor P 106 , wherein a gate is connected to the precharge node C 101 , a source is grounded, and a drain is connected to a drain of the Pch transistor P 104 ; 
   the Pch transistor P 105 , wherein a gate is connected to the precharge node C 102 , a source is connected to the power supply, and a drain is connected to the output data signal NQ; 
   the Nch transistor N 107 , wherein a gate is connected to the drain of the Nch transistor N 106 , a source is grounded, and a drain is connected to the output data signal NQ; 
   the Pch transistor P 106 , wherein a gate is connected to the output terminal of the inverter I 101 , a source is connected to the power supply, and a drain is connected the precharge node C 102 ; 
   the Pch transistor P 107 , wherein a gate is connected to the precharge node C 102 , a source is connected to the power supply, and a drain is connected to the precharge node C 101 ; 
   the Nch transistor N 117 , wherein a gate is connected to the input data signal D 2  and a drain is connected to the precharge node C 101 ; and 
   the Nch transistor N 118 , wherein a gate is connected to the input data signal selection signal SEL, a drain is connected to a source of the Nch transistor N 117 , and a source is connected to the drain of the Nch transistor N 101 . 
   The dynamic circuit all comprises a combination of an NAND-type dynamic circuit including the Pch transistor P 101 , Nch transistor N 102 , Nch transistor N 103 , and Nch transistor N 101 , which are serially connected, and an NAND-type circuit including the Pch transistor P 101 , Nch transistor N 117 , Nch transistor N 118 , and Nch transistor N 101 , which are serially connected. The NAND-type dynamic circuit a 12  comprises the Pch transistor P 102 , Nch transistor N 104 , Nch transistor N 105 , and Nch transistor N 101 , which are serially connected. 
   The feedback circuit A 13  of the semiconductor integrated circuit according to the embodiment 2 comprises: 
   the Pch transistor P 108 , wherein a gate is connected to the output data signal NQ and a source is connected to a power supply; 
   the Pch transistor P 110 , wherein a gate is connected to the input data signal D 1 , a drain is connected to the feedback signal S 102 , and a source is connected to a drain of the Pch transistor P 108 ; 
   the Nch transistor N 110 , wherein a gate is connected to the input data signal D 1  and a drain is connected to the feedback signal S 102 ; 
   the Nch transistor N 111 , wherein a gate is connected to the output data signal NQ, a drain is connected to the feedback signal S 102 , and a source is connected to a source of the Nch transistor N 110 ; 
   the Pch transistor P 111 , wherein a gate is connected to the input data signal selection signal SEL and a source is connected to the power supply; 
   the Nch transistor N 112 , wherein a gate is connected to the input data signal selection signal SEL, a source is grounded, and a drain is connected to a drain of the Pch transistor P 111 ; 
   the Nch transistor N 113 , wherein a gate is connected to the drain of the Nch transistor N 112 , a source is grounded, and a drain is connected to the source of the Nch transistor N 110 ; 
   the Pch transistor P 112 , wherein a gate is connected to the drain of the transistor N 112 , a source is connected to the power supply, and a drain is connected to the feedback signal S 102 ; 
   the Pch transistor P 113 , wherein a gate is connected to the data retaining node C 103 , a source is connected to the drain of the Pch transistor P 111 , and a drain is connected to the feedback signal S 101 ; 
   the Nch transistor N 114 , wherein a gate is connected to the input data signal selection signal SEL, a drain is connected to the feedback signal S 101 , and a source is grounded; and 
   the Nch transistor N 115 , wherein a gate is connected to the data retaining node C 103 , a drain is connected to the feedback signal S 101 , and a source is grounded. 
   When the discharge operation with respect to the precharge node C 101  in its discharge path and the discharge operation with respect to the precharge node C 102  in its discharge path race with each other in the foregoing configuration, errors are possibly generated. In order to prevent the racing, the charge of the precharge node C 101  is released earlier, and the charge of the precharge node C 102  is discharged later. 
   Hereinafter, the improvement is described. 
   In the foregoing configuration, it is preferable for the latch circuit A 11  to be configured in the manner that, referring to a spatial distance in terms of physical layout, a distance between the Nch transistor N 101  and Nch transistor N 103  is set to be shorter than a distance between the Nch transistor N 101  and Nch transistor N 105 . The operation according to the foregoing configuration is as follows. The smaller the spatial distance is, the easier the operation is, thereby achieving a better responsiveness. Therefore, the discharge is implemented earlier in the discharge path of the precharge node C 101 , where the Nch transistor N 103  having the shorter distance is present, and the operation can be thereby more stable. 
   In the foregoing configuration, it is preferable for the latch circuit A 11  to be configured in the manner that, referring to the threshold voltages of the MOS transistors, the threshold voltages of the Nch transistor N 102  and Nch transistor N 103  are set to be lower than the threshold voltages of the Nch transistor N 104  and Nch transistor N 105 . The operation according to the foregoing configuration is as follows. The lower the threshold voltage is, the easier the operation is, thereby achieving a better responsiveness. Therefore, the discharge is implemented earlier in the discharge path of the precharge node C 101 , where the Nch transistors N 102  and N 103  having the lower threshold voltages are present, and the operation can be thereby more stable. 
     FIG. 6  is a waveform chart illustrating the operation of the semiconductor integrated circuit according to the configuration of  FIG. 5 . 
   The input data signal selection signal SEL is at the “L” level from time T 10  through time T 18 , therefore the Nch transistor N 118  maintains its OFF state. More specifically, because of the input data signal selection signal SEL at the “L” level, the Pch transistor P 111  is in the ON state, while the Nch transistors N 112  and N 114  are in the OFF state. Further, because the output data signal Q is at the “L” level and the data retaining node C 103  of the data retaining circuit A 12  is also at the “L” level, the Pch transistor P 113  is in the ON state, while the Nch transistor N 115  is in the OFF state. Because of this, the feedback signal S 101  with respect to the gate of the Nch transistor N 103  in the NAND-type dynamic circuit a 12  is at the “H” level, and the Nch transistor N 103  is in the ON state. In consequence of the above-mentioned, the operation during the period from the time T 10  through the time T 18  is substantially identical to the operation in the embodiment 1, as shown in the waveform chart of  FIG. 5 . 
   The state at the time T 18  is as follows. The clock signal CK is at the “L” level and to be precharged during the period. In the latch circuit A 11 , the precharge node C 101  and precharge node C 102  are at the “H” level. The output data signal Q is at the “L” level, and the output data signal NQ is at the “H” level. The data retaining node C 103  of the data retaining circuit A 12  is at the “L” level. The Pch transistors P 101 , P 102 , P 106  and P 103  are in the ON state. The Pch transistors P 107 , P 105  and P 104  are in the OFF state. The Nch transistors N 103 , N 104  and N 106  are in the ON state. The Nch transistors N 101 , N 102 , N 105 , N 107 , N 117  and N 118  are in the OFF state. Meanwhile, in the feedback circuit A 13 , the Pch transistors P 110 , P 111  and P 113  are in the ON state. The Pch transistors P 108  and P 112  are in the OFF state. The Nch transistors N 111  and N 113  are in the ON state. The Nch transistors N 110 , N 112 , N 114  and N 115  are in the OFF state.
     1) At time T 19 , it is assumed that the input data signal selection signal SEL rises to the “H” level. The Pch transistor P 111  is then lead to OFF, Nch transistor N 112  to ON, and Nch transistor N 114  also to ON. The feedback signal S 101  is inverted from the “H” level to the “L” level. As a result, the Nch transistor N 103  is inverted to the OFF state. Further, because the Pch transistor P 111  is OFF and the Nch transistor N 112  is ON, the Pch transistor P 112  is ON and the Nch transistor N 113  is OFF. The feedback signal S 102  is inverted from the “L” level to the “H” level. As a result, the Nch transistor N 105  is inverted to the ON state. However, the clock signal CK is at the “L” level, and the Nch transistor N 101  is in the OFF state, therefore the precharge node C 101  and precharge node C 102  maintain their “H” level.   2) It is assumed that the clock signal CK rises to the “H” level at time T 20 . The Nch transistor N 101  is accordingly inverted to the ON state. At that time, the Nch transistor N 118  is already in the ON state. The input data signal D 2  is inverted from the “L” level to the “H” level immediately before the time T 20 , and the Nch transistor N 117  is accordingly in the ON state. Therefore, the precharge node C 101  is discharged, resulting in the “L” level. In accordance with this, the Nch transistor N 104  is inverted to the OFF state, and the precharge node C 102  is not discharged. The precharge node C 102  therefore retains its charge maintaining its “H” level.   

   The inversion of the precharge node C 101  to the “L” level results in the inversion of the Pch transistor P 104  to the ON state and also the inversion of the Nch transistor N 106  to the OFF state. Because of the Pch transistor P 103  in the ON state, the Nch transistor N 107  is inverted to the ON state. As a result, the output data signal NQ is inverted to the “L” level, while the output data signal Q is inverted to the “H” level. The data retaining node C 103  is inverted to the “H” level.
     3) When the clock signal CK falls at time T 21 , the Pch transistor P 101  is inverted to be in the ON state, and the precharge node C 101  is charged.   4) When the clock signal CK rises at time T 22 , the Nch transistor N 101  is inverted to be in the ON state, and the discharge is implemented in a path involving the Nch transistors N 117 , N 118  and N 101 . The precharge node C 101  is thereby inverted to the “L” level.   

   Thereafter, the clock signal CK falls again by time T 23 , and the precharge node C 101  is thereby charged.
     5) At the time T 23 , the input data signal D 2  is inverted from the “H” level to the “L” level, and the Nch transistor N 117  is inverted to the OFF state.   6) It is assumed that the clocks signal CK rises to the “H” level at time T 24 . The Pch transistors P 101  and P 102  are inverted to the OFF state. At that time, the feedback signal S 101  is at the “L” level, and the Nch transistor N 103  is in the OFF state. Meanwhile, the feedback signal S 102  is at the “H” level, and the Nch transistor N 105  is in the ON state. The precharge node C 101  is at the “H” level, therefore the Nch transistor N 104  is in the ON state. Accordingly, when the Pch transistor P 102  is inverted to be in the OFF state, the precharge node C 102  is connected to the ground via the Nch transistors N 104 , N 105  and N 101  to thereby discharge. At that time, the output of the inverter I 01  is inverted to the “H” level, and the Pch transistor P 106  is inverted to the OFF state. As a result, the precharge node C 102  is inverted from the “H” level to the “L” level.   7) It is assumed that the clock signal CK falls to the “L” level at time T 25 . The Pch transistor P 102  is inverted to the ON state, while the Nch transistor N 101  is inverted to the OFF state. The precharge node C 012  is thereby charged, and inverted to the “H” level.   

   As described, when the input data signal selection signal SEL is at the “H” level, the precharge is implemented by means of the fall of the clock signal CK, and the discharge is implemented by means of the rise of the clock signal CK. The input data signal D 2  is then fetched. The discharge is implemented in the dynamic circuit all when the input data signal D 2  is at the “H” level, and in the NAND-type dynamic circuit a 12  when the input data signal D 2  is at the “L” level. 
   The features of the embodiment 2 are mentioned below. 
   In the case in which the input data signal D 1  having the low transition probability is selected, the internal operation of the latch circuit A 11  is halted by means of the logics of the input data signal D 1  and output data signal Q when the input data signal D 1  and output data signal Q are in the same state to thereby reduce the power consumption and maintain the high-speed operation of the dynamic circuit itself as in the embodiment 1. When the input data signal D 2  having the high transition probability is selected, the internal operation of the latch circuit A 11  remains active enabling the high-speed operation of the dynamic circuit itself. 
   Embodiment 3 
     FIG. 7  is a plane view partially illustrating an example of a semiconductor integrated circuit according to an embodiment 3 of the present invention. The embodiment 3 offers a technology for preventing a racing between the Nch transistors N 104 , N 105  and the Nch transistors N 117 , N 118  in the latch circuit A 11  shown in  FIG. 5 . The charge of the precharge node C 101  is discharged earlier, while the precharge node C 102  is discharged later. 
     FIG. 7  shows a circuit block  30  comprising the Nch transistors N 101 , N 117  and N 118  of  FIG. 5 , and a circuit block  31  comprising the Nch transistors N 104  and N 105  of  FIG. 5 , which are formed on the semiconductor substrate. 
   The circuit block  30  is formed from diffusion regions constituting the source and drain of the Nch transistor N 101  and gate electrodes thereof, diffusion regions constituting the source and drain of the Nch transistor N 118  and gate electrodes thereof, and diffusion regions constituting the source and drain of the Nch transistor N 117  and gate electrodes thereof, which are sequentially disposed in a transverse direction. The diffusion region constituting the source of the Nch transistor N 118  is in common with the diffusion region constituting the drain of the Nch transistor N 101 . The diffusion region constituting the source of the Nch transistor N 117  is in common with the diffusion region constituting the drain of the Nch transistor N 118 . 
   The circuit block  31  is formed from diffusion regions constituting the source and drain of the Nch transistor N 105  and gate electrodes thereof and diffusion regions constituting the source and drain of the Nch transistor N 104  and gate electrodes thereof, which are sequentially disposed in the transverse direction. The diffusion region constituting the source of the Nch transistor N 104  is in common with the diffusion region constituting the drain of the Nch transistor N 105 . 
   The source diffusion region of the Nch transistor N 101  is connected to the ground potential. Further, the drain of the Nch transistor N 101  and the source of the Nch transistor N 118  are connected to the source of the Nch transistor N 105 . 
   In the embodiment 2, the circuit blocks  30  and  31  are adjacently disposed in the transverse direction, however may be adjacently disposed lengthwise. 
   The operation of the semiconductor integrated circuit according to the embodiment 3 having the foregoing configuration is described below. 
   For example, before the clock signal CK rises at the time T 22  in  FIG. 6 , the Nch transistor N 118  is in the ON state because the input data signal selection signal SEL is at the “H” level. The Nch transistor N 117  is in the ON state because the input data signal D 2  is at the “H” level. The Nch transistor N 105  is in the ON state because the feedback signal S 102  is at the “H” level. The Nch transistor N 104  is in the ON state because the precharge node C 101  is at the “H” level. 
   Thereafter, as soon as the clock signal CK rises, the level of the precharge node C 102  descends to the “L” level direction in compliance with the capacities of the Nch transistors N 104  and N 105  until the precharge node C 101  changes to the “L” level. 
   For that reason, the diffusion region constituting the drain of the Nch transistor N 101  and the diffusion region constituting the source of the Nch transistor N 118  are disposed closer to the diffusion region constituting the source of the Nch transistor N 105 . In that manner, the charge of the precharge node C 101  is discharged earlier, and the charge of the precharge node C 102  is discharged later so that the Nch transistors N 104 , N 105  and the Nch transistors N 117 , N 118  are prevented from racing with each other. 
   Hereinafter is described another method of discharging the precharge node C 101  earlier and discharging the precharge node C 102  later. 
   The threshold voltages of the Nch transistors N 117  and N 118  are set to be lower than the threshold voltages of the Nch transistors N 104  and N 105  so that the charge of the precharge node C 101  is discharged earlier, and the charge of the precharge node C 102  is discharged later. In that manner, the Nch transistors N 104  nad N 105  and the Nch transistors N 117  and N 118  are prevented from racing with each other. 
   Further, when STI (sharow Trench isolation) formed between the adjacent circuit blocks deteriorates transistor characteristics, the diffusion region constituting the source of the Nch transistor N 103  and diffusion region constituting the drain of the Nch transistor N 104  are formed on the STI side so that the transistor characteristics of the drains of the Nch transistors N 103  and N 104  are more deteriorated (lower current capacity, increased threshold voltage, or the like) than the transistor characteristics of the Nch transistors N 101 , N 117  and N 118 . Then, the precharge node C 101  is discharged earlier, and the precharge node C 102  is discharged later so that the Nch transistors N 104 , N 105  and the Nch transistors N 117 , N 118  are prevented from racing with each other. 
   Further, in the embodiment 3, the STI sepraration is present outside the Nch transistor N 117 , which possibly causes the deterioration of the transistor characteristic of the Nch transistor N 117 . As a possible configuration, as shown in  FIG. 8 , a dummy transistor N 150  having a dummy source diffusion region and a dummy gate electrode can be formed outside the Nch transistor N 117 , and connected to the ground potential in the same manner to thereby further control the deterioration of the transistor characteristic of the Nch transistor N 117 . 
   The embodiment 3 was exemplified and described based on the fact that the transistor characteristics mostly deteriorate due to the STI formed between the adjacent circuit blocks. 
   However, from the aspect of a possible situation in the future, where the STI formed between the adjacent circuit blocks can improve the transistor characteristics, in the present embodiment, the source diffusion region of the Nch transistor N 117  and the drain diffusion region of the Nch transistor N 118  are disposed on the STI side to thereby improve the transistor characteristics of the Nch transistors N 117  and N 118 . Then, the dummy source diffusion region and dummy gate electrode are formed outside the source diffusion region of the Nch transistor N 103  and the drain diffusion region of the Nch transistor N 104 , and connected to the ground potential in the same manner, to thereby control the improvement of the transistor characteristics of the Nch transistors N 103  and N 104 . 
   In  FIGS. 7 and 8 , N 117  may be replaced by N 102 , and N 118  may be replaced by N 103  to understand the configuration. 
   Embodiment 4 
     FIGS. 9 and 10  are views each illustrating a configuration of a semiconductor integrated circuit according to an embodiment 4 of the present invention. In  FIG. 9 , reference symbols P 01 –P 10  denote P-type MOS transistors. N 01 –N 11  denote N-type MOS transistors. I 01  and I 02  denote inverters. 
   A reference numeral  200  denotes a latch circuit. In the latch circuit  200 , the Pch transistors P 01 –P 07  and inverter I 01  are connected to a power supply VDD 1 , and the Nch transistor N 01 –N 07  and inverter I 01  are connected to a ground potential VSS 1 . A reference numeral  201  denotes a feedback circuit/retaining circuit. In the feedback circuit/retaining circuit  201 , the Pch transistors P 08 –P 10  and inverter I 02  are connected to a power supply VDD, and the Nch transistors N 08 –N 11  and inverter I 02  are connected to a ground potential VSS. 
     FIG. 10  is a configuration diagram illustrating the supply of the power supply and ground potential to the feedback circuit/retaining circuit  201 . CLOCK denotes a clock, and STOP denotes a clock feedback signal. The clock feedback signal STOP outputs the “H” level in normal operation, while outputting the “L” level when the clock is halted. 
   A reference numeral  202  denotes an AND circuit. The AND circuit  202  supplies the latch circuit  200  with the clock in normal operation, while supplying “L” level when the clock is halted. 
   The configuration shows an example in which the “L” level is supplied when the clock is halted, however there is no problem in the circuit operation if the “H” level is supplied when the clock is halted. 
   A reference numeral  203  denotes a power supply control circuit. The power supply control circuit  203  inputs therein the power supply VDD and ground potential VSS. 
   The power supply control circuit  203  outputs the power supply VDD 1  of the same level as the power supply VDD and the ground potential VSS 1  of the same level as the ground potential VSS to the latch circuit  200  when the clock feedback signal STOP is normally actuated. The power supply control circuit  203  outputs the power supply VDD 1  of the same level as the power supply VDD and the ground potential VSS 1  of a potential higher than the ground potential VSS to the latch circuit  200  when the clock feedback signal STOP halts the clock. 
   The latch circuit  203  is controlled in the foregoing manner so as to increase the potential level of the ground potential VSS 1  when the clock is halted, thereby reducing a leak current from the latch circuit  200 . 
   Because the power supply control circuit  203  is controlled in the described manner, the power supply can be turned off when the clock is halted to thereby reduce the leak current from the latch circuit  200  while keeping information retained in the retaining circuit  201 . 
   Embodiment 5 
     FIGS. 11 and 12  are views each illustrating a configuration of a semiconductor integrated circuit according to an embodiment 5 of the present invention. 
   In  FIG. 11 , reference symbols P 01 –P 10  denote P-type MOS transistors, and reference symbols N 01 –N 11  denotes N-type MOS transistors. Reference symbols I 01  and I 02  respectively denote an inverter. 
   A reference numeral  300  denotes a latch circuit. In the latch circuit  300 , substrate potentials of the Nch transistors N 02  and N 03  are connected to a VBS 1 , and substrate potentials of the Nch transistors N 04  and N 05  are connected to a VBS 2 . 
     FIG. 12  is a configuration diagram illustrating the supply of a substrate potential to the latch circuit  300 . 
   To a substrate potential control circuit  301  are inputted the feedback signal S 01  and feedback signal S 02  from the latch circuit  300 , and also a power supply VDD and ground potential VSS. Further, from the substrate potential control circuit  301  are outputted a substrate potential VBS 1  and a substrate potential VBS 2  to the latch circuit  300 . The substrate potential VBS 1  is supplied to the Nch transistors N 02  and N 03  of a NAND-type dynamic circuit al in the latch circuit  300 . The substrate potential VBS 2  is supplied to the Nch transistors N 04  and N 05  of a NAND-type dynamic circuit a 2  in the latch circuit  300 . 
   The substrate potential VBS 1  outputs a potential lower than the ground potential when the feedback signal S 01  is at the “L” level, and outputs a potential higher than the ground potential when the feedback signal S 01  is at the “H” level. The substrate potential VBS 2  outputs a potential lower than the ground potential when the feedback signal S 02  is at the “L” level, and outputs a potential higher than the ground potential when the feedback signal S 02  is at the “H” level The substrate potential control circuit  301  is thus controlled so that, when the feedback signal S 01  is at the “H” level, and the Nch transistors N 02  and N 03  are operated, the substrate potential is controlled in a forward bias direction, and the threshold potentials of the Nch transistors N 02  and N 03  are lowered to thereby enable a high-speed operation. 
   On the contrary, when the feedback signal S 01  is at the “L” level, and the Nch transistors N 02  and N 03  come to a halt, the substrate potential is controlled in a back bias direction so that the threshold potentials of the Nch transistors N 02  and N 03  are raised to thereby reduce the leak current. 
   When the feedback signal S 02  is at the “H” level, and the Nch transistors N 04  and N 05  are operated, the substrate potential is controlled in the forward bias direction so that the threshold potentials of the Nch transistors N 04  and N 05  are lowered to thereby enable the high-speed operation. 
   On the contrary, when the feedback signal S 02  is at the “L” level, and the Nch transistors N 04  and N 05  come to a halt, the substrate potential is controlled in the back bias direction so that the threshold potentials of the Nch transistors N 04  and N 05  are raised to thereby reduce the leak current 
   Embodiment 6 
     FIG. 15  is a circuit diagram illustrating an example of a configuration of a semiconductor integrated circuit according to an embodiment 6 of the present invention. In  FIG. 15 , reference symbols P 501 –P 511  denote Pch transistors, and N 501 –N 512  denote Nch transistors. Reference symbols I 501 , I 502 , I 503 , I 504  and I 505  respectively denote a inverter. C 501  and C 502  denote precharge nodes and C 503  denotes a data retaining node. S 501  and S 502  respectively denote a feedback signal. A reference numeral  500  denotes a feedback circuit. In  FIG. 15 , the configuration of  FIG. 2  described in the embodiment 1 is further provided with a path gate circuit and a circuit for retaining an output of the path gate circuit. 
   Next, the operation of the semiconductor integrated circuit according to the embodiment 6 having the foregoing configuration is described below. 
   For example, in the case in which the input data signal D is at the “H” level, the output data signal Q is at the “H” level, the output data signal NQ is at the “L” level, and the clock signal CK is at the “L” level, the Pch transistor P 508  is turned on, the Pch transistor P 510  is turned off, the Nch transistor N 511  is turned off, and the Nch transistor N 510  is turned on. Further, because the clock signal CK is at the “L” level, the Nch transistor N 512  is ON. Because the inverter I 505  outputs the “H” level, the Pch transistor P 511  is ON, and the feedback signal S 502  is at the “L” level. 
   Next, when the clock signal rises to be at the “H” level, the Nch transistor N 512  is OFF because of the clock signal CK at the “H” level, the Pch transistor P 511  is OFF because the output level of the inverter I 505  is “L”, the Pch transistor P 511  is OFF. The feedback signal S 502  accordingly retains a previous value by means of the inverters I 503  and I 504 . 
   The value of the feedback signal S 502  is determined during the period when the clock signal CK is at the “L” level. Then, the Pch transistor P 511  and Nch transistor N 512  are turned off when the clock signal CK rises so that the value of the feedback signal S 502  is retained without depending on the values of the input data signal D, output data signal Q and output data signal NQ to thereby reduce a hold time with respect to the input data signal D. 
   The embodiment 6 was described by means of the circuit configuration based on the embodiment 1. Further, the embodiments 2 through 5 can also achieve a corresponding effect by further providing, in their configurations, the path gate circuit and the circuit for retaining the output of the path gate circuit. 
   While the invention has been described and illustrated in detail, it is to be clearly understood that this is intended be way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of this invention being limited only be the terms of the following claims.