Patent Publication Number: US-11393523-B1

Title: Memory unit with asymmetric group-modulated input scheme and current-to-voltage signal stacking scheme for non-volatile computing-in-memory applications and computing method thereof

Description:
BACKGROUND 
     Technical Field 
     The present disclosure relates to a memory unit for a plurality of non-volatile computing-in-memory applications and a computing method thereof. More particularly, the present disclosure relates to a memory unit with an asymmetric group-modulated input scheme and a current-to-voltage signal stacking scheme for a plurality of non-volatile computing-in-memory applications and a computing method thereof. 
     Description of Related Art 
     In these years, due to the industrial growth of mobile device, medical electrical equipment, portable storage, etc., requirement of memory with low power, high speed and high density is increased. Computation-in-Memory (CIM) is a promising solution to improve the energy efficiency of multiply-and-accumulate (MAC) operations for artificial intelligence (AI) chips, and multiple-bit convolutional neural network (CNN) is required for high inference accuracy in many applications. 
     For example, battery-powered tiny AI edge devices require high precision of MAC computing for non-volatile computing-in-memory (nvCIM) to support complex applications. However, achieving high precision involves various challenges. First, long input latency caused by conventional input schemes. Second, limited system-level inference accuracy due to small signal margin. Third, high power consumption in readout circuit due to large amount of DC current. 
     The memory unit with the conventional fully-decoded wordline pulse-count input scheme and the memory unit with the conventional fully-decoded wordline pulse-width input scheme suffer long latency due to a lower number of parallel inputs that need multiple cycles for applying inputs to nvCIM and corresponding computing operations. Therefore, a memory unit with an asymmetric group-modulated input (AGMI) scheme and a current-to-voltage signal stacking (CVSS) scheme for a plurality of nvCIM applications and a computing method thereof having the features of reducing the computing latency, achieving larger signal margin and decreasing the energy consumption are commercially desirable. 
     SUMMARY 
     According to one aspect of the present disclosure, a memory unit with an asymmetric group-modulated input (AGMI) scheme and a current-to-voltage signal stacking (CVSS) scheme for a plurality of non-volatile computing-in-memory (nvCIM) applications is configured to compute a plurality of multi-bit input signals and a plurality of weights. The memory unit with the AGMI scheme and the CVSS scheme for the nvCIM applications includes a plurality of non-volatile memory cells, a source line, a bit line, a controller and a CVSS converter. The non-volatile memory cells are controlled by a plurality of word lines to generate a plurality of memory cell currents and storing the weights. The word lines transmit the multi-bit input signals, respectively. The source line is electrically connected to one end of each of the non-volatile memory cells. The bit line is electrically connected to another end of each of the non-volatile memory cells and has a bit-line current. The bit-line current is equal to a sum of the memory cell currents. The controller is electrically connected to the non-volatile memory cells. The controller splits the multi-bit input signals into a plurality of input sub-groups and generates a plurality of switching signals according to the input sub-groups, and the input sub-groups are sequentially inputted to the word lines. The CVSS converter is electrically connected to the non-volatile memory cells via the bit line. The CVSS converter is electrically connected to the controller and converts the bit-line current into a plurality of converted voltages according to the input sub-groups and the switching signals, and the CVSS converter stacks the converted voltages to form an output voltage, and the output voltage is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals multiplied by the weights. 
     According to another aspect of the present disclosure, a computing method of the memory unit with the AGMI scheme and the CVSS scheme for the nvCIM applications includes performing a voltage level applying step and a computing step. The voltage level applying step includes applying a plurality of voltage levels to the multi-bit input signals and the switching signals. The computing step includes driving the controller to split the multi-bit input signals into the input sub-groups, and driving the controller to sequentially input the input sub-groups to the word lines, and driving the CVSS converter to convert the bit-line current into a plurality of converted voltages according to the input sub-groups and the switching signals, and driving the CVSS converter to stack the converted voltages to form an output voltage. The output voltage is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals multiplied by the weights. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
         FIG. 1  shows a block diagram of a memory unit with an asymmetric group-modulated input (AGMI) scheme and a current-to-voltage signal stacking (CVSS) scheme for a plurality of non-volatile computing-in-memory (nvCIM) applications according to one embodiment of the present disclosure. 
         FIG. 2  shows a schematic view of the AGMI scheme of the memory unit of  FIG. 1 . 
         FIG. 3  shows a circuit diagram of a non-volatile memory array, a column multiplexer and a CVSS converter of the memory unit of  FIG. 1 . 
         FIG. 4  shows timing diagrams of voltage levels of a plurality of 8-bit input signals, a plurality of switching signals and an output voltage and a current level of a dataline current, in accordance with an example of the 8-bit input signals of the present disclosure. 
         FIG. 5  shows a circuit diagram of each of a plurality of initial operations of the CVSS converter of the memory unit during each of a plurality of bit line developing time intervals of  FIG. 4 . 
         FIG. 6  shows a circuit diagram of each of a first converting operation and a second converting operation of the CVSS converter of the memory unit during each of a first input phase and a second input phase of  FIG. 4 . 
         FIG. 7  shows a circuit diagram of a third converting operation of the CVSS converter of the memory unit during a third input phase of  FIG. 4 . 
         FIG. 8  shows timing diagrams of voltage levels of a plurality of 8-bit input signals, a plurality of switching signals and an output voltage and a current level of a dataline current, in accordance with another example of the 8-bit input signals of the present disclosure. 
         FIG. 9  shows timing diagrams of a current level of a dataline current and voltage levels of a plurality of switching signals and an output voltage, in accordance with an example of a plurality of 4-bit input signals of the present disclosure. 
         FIG. 10  shows a flow chart of a computing method of a memory unit with an AGMI scheme and a CVSS scheme for a plurality of nvCIM applications according to another embodiment of the present disclosure. 
         FIG. 11  shows a comparison result of array energy consumption among the memory unit with the AGMI scheme of the present disclosure, a memory unit with a conventional fully-decoded wordline pulse-count input scheme and a memory unit with a conventional fully-decoded wordline pulse-width input scheme. 
         FIG. 12  shows a comparison result of most significant bit part (MSP) signal margin among the memory unit with the AGMI scheme of the present disclosure, the memory unit with the conventional fully-decoded wordline pulse-count input scheme and the memory unit with the conventional fully-decoded wordline pulse-width input scheme. 
         FIG. 13  shows a comparison result of energy consumption between the memory unit with the CVSS scheme of the present disclosure and a memory unit with a conventional fully current summation scheme. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiment will be described with the drawings. For clarity, some practical details will be described below. However, it should be noted that the present disclosure should not be limited by the practical details, that is, in some embodiment, the practical details is unnecessary. In addition, for simplifying the drawings, some conventional structures and elements will be simply illustrated, and repeated elements may be represented by the same labels. 
     It will be understood that when an element (or device) is referred to as be “connected to” another element, it can be directly connected to the other element, or it can be indirectly connected to the other element, that is, intervening elements may be present. In contrast, when an element is referred to as be “directly connected to” another element, there are no intervening elements present. In addition, the terms first, second, third, etc. are used herein to describe various elements or components, these elements or components should not be limited by these terms. Consequently, a first element or component discussed below could be termed a second element or component. 
     Before describing any embodiments in detail, some terms used in the following are described. A voltage level of “1” represents that the voltage is equal to a power supply voltage VDD. The voltage level of “0” represents that the voltage is equal to a ground voltage GND. A PMOS transistor and an NMOS transistor represent a P-type MOS transistor and an N-type MOS transistor, respectively. Each transistor has a source, a drain and a gate. 
       FIG. 1  shows a block diagram of a memory unit  100  with an asymmetric group-modulated input (AGMI) scheme and a current-to-voltage signal stacking (CVSS) scheme for a plurality of non-volatile computing-in-memory (nvCIM) applications according to one embodiment of the present disclosure.  FIG. 2  shows a schematic view of the AGMI scheme of the memory unit  100  of  FIG. 1 .  FIG. 3  shows a circuit diagram of a non-volatile memory array  200 , a column multiplexer  500  and a CVSS converter  600  of the memory unit  100  of  FIG. 1 . The memory unit  100  with the AGMI scheme and the CVSS scheme for the nvCIM applications is configured to compute a plurality of multi-bit input signals (e.g., IN 0 [7:0], IN 1 [7:0], IN 2 [7:0], IN 3 [7:0]) and a plurality of weights (e.g., W 0 [0], W 1 [0], W 2 [0], W 3 [0]). The AGMI scheme represents that each of four 8-bit input signals IN 0 [7:0]-IN 3 [7:0] may be split into three input sub-groups IN 76 , IN 543 , IN 210  (2 bit-3 bit-3 bit) with three corresponding input phases WLP 2 , WLP 1 , WLP 0  by a controller  400 . The CVSS scheme represents that the bit-line current I BL  may be converted into a plurality of converted voltages according to the input sub-groups IN 76 , IN 543 , IN 210  and a plurality of switching signals (e.g., SWS 0 , SWS 1 , SWS 2 , SWS 3 , EN 1 , EN 2 , S 0 , S 1 ), and the converted voltages are stacked to form an output voltage V SUM  by the CVSS converter  600 . In FIGS. 1-3, the memory unit  100  with the AGMI scheme and the CVSS scheme for the nvCIM applications includes the non-volatile memory array  200 , a word line driver  300 , a controller  400 , a column multiplexer  500  and a CVSS converter  600 . 
     The non-volatile memory array  200  includes a plurality of non-volatile memory cells  210 , a source line SL and a bit line BL. The non-volatile memory cells  210  are controlled by a plurality of word lines WL[0], WL[1], WL[2], WL[3] to generate a plurality of memory cell currents I MC[0] , I MC[1] , I MC[2] , I MC[3]  and stores the weights W 0 [0]-W 3 [0]. The word lines WL[0]-WL[3] transmit the multi-bit input signals IN 0 [7:0]-IN 3 [7:0], respectively. The source line SL is electrically connected to one end of each of the non-volatile memory cells  210 . The bit line BL is electrically connected to another end of each of the non-volatile memory cells  210  and has a bit-line current I BL . The bit-line current I BL  is equal to a sum of the memory cell currents I MC[0] -I MC[3] . Each of the non-volatile memory cells  210  includes a resistive element and a transistor. The resistive element is electrically connected to the bit line BL and stores one of the weights W 0 [0]-W 3 [0]. The transistor is electrically connected between the resistive element and the source line SL. The source line SL is coupled to the ground voltage. The resistive element is in one of a high resistance state (HRS) and a low resistance state (LRS). The transistor is the NMOS transistor. In one embodiment, each of the non-volatile memory cells  210  may be a 1-transistor 1-resistor (1T1R) ReRAM cell. 
     The word line driver  300  is connected to the non-volatile memory cells  210  via the word lines WL[0]-WL[3]. The word line driver  300  is represented by “Input Driver” and is located on a left side of the non-volatile memory cells  210 . The word line driver  300  generates the voltage levels of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] to control each of the non-volatile memory cells  210  via the word lines WL[0]-WL[3]. 
     The controller  400  is electrically connected to the non-volatile memory cells  210 . The controller  400  is represented by “Controller” and is located on a bottom side of the word line driver  300 . The controller  400  splits the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] into the input sub-groups IN 76 , IN 543 , IN 210  and generates a plurality of switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ) according to the input sub-groups IN 76 , IN 543 , IN 210 , and the input sub-groups IN 76 , IN 543 , IN 210  are sequentially inputted to the word lines WL[0]-WL[3]. In other words, the controller  400  is configured to perform the AGMI scheme. 
     The column multiplexer  500  is electrically connected between each of the non-volatile memory cells  210  and the CVSS converter  600 . The column multiplexer  500  is represented by “Column MUX” and is located on a bottom side of the non-volatile memory cells  210 . The column multiplexer  500  receives the bit-line current I BL  and generates a dataline current I DL [n] according to the bit-line current I BL . n represents an integer value, such as 0-63. 
     The CVSS converter  600  is electrically connected to the non-volatile memory cells  210  via the bit line BL. The CVSS converter  600  is represented by “CVSS” and is located on a bottom side of the column multiplexer  500 . The CVSS converter  600  is electrically connected to the controller  400  and converts the bit-line current I BL  into the converted voltages according to the input sub-groups IN 76 , IN 543 , IN 210  and the switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ). The CVSS converter  600  stacks the converted voltages to form the output voltage V SUM , and the output voltage V SUM  is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] multiplied by the weights W 0 [0]-W 3 [0]. In detail, the CVSS converter  600  receives the dataline current I DL [n] corresponding to the bit-line current I BL  from the column multiplexer  500  and converts the dataline current I DL [n] into the converted voltages according to the input sub-groups IN 76 , IN 543 , IN 210  and the switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ). The CVSS converter  600  is configured to perform the CVSS scheme and includes a first dataline transistor P 1 , a first sub-converter  610 , a second sub-converter  620 , a coupling capacitor C C , an output capacitor C O , a stacking capacitor C S , a first stacking transistor NO and a second stacking transistor N 1 . The first dataline transistor P 1  is electrically connected to the column multiplexer  500 . The dataline current I DL [n] flows through the first dataline transistor P 1 . The first sub-converter  610  and the second sub-converter  620  are electrically connected to the first dataline transistor P 1 . One end (i.e., a node SUM) of the coupling capacitor C C  is electrically connected to the first sub-converter  610 . The output capacitor C O  is electrically connected between the one end of the coupling capacitor C C  and the ground voltage. The output capacitor C O  is electrically connected to a 2-bit voltage sense amplifier 2b-VSA for sensing. A voltage difference across the output capacitor C O  is equal to the output voltage V SUM . The stacking capacitor C S  is electrically connected between another end (i.e., a node STACK) of the coupling capacitor C C  and the ground voltage. The first stacking transistor NO is electrically connected between the one end of the coupling capacitor C C  and the ground voltage. The second stacking transistor N 1  is electrically connected between the another end of the coupling capacitor C C  and the ground voltage. The first dataline transistor P 1  is the PMOS transistor. Each of the first stacking transistor NO and the second stacking transistor N 1  is the NMOS transistor. 
     The first sub-converter  610  includes a first two-terminal switching element SW 0 , a first switching transistor PS 1 , a second dataline transistor P 2 , a first bias transistor BP 0  and a second two-terminal switching element SW 1 . The first two-terminal switching element SW 0  is electrically connected to the first dataline transistor P 1 . The first switching transistor PS 1  is electrically connected between the first two-terminal switching element SW 0  and the power supply voltage. The second dataline transistor P 2  is electrically connected to the first two-terminal switching element SW 0  and the first switching transistor PS 1 . The first bias transistor BP 0  is electrically connected to the second dataline transistor P 2 . The second two-terminal switching element SW 1  is electrically connected to the first bias transistor BP 0 , the coupling capacitor C C , the output capacitor C O  and the first stacking transistor NO. The first dataline transistor P 1  has a first transistor width, and the second dataline transistor P 2  has a second transistor width. The second transistor width is equal to one-half of the first transistor width, so that a current flowed through the second dataline transistor P 2  may be equal to one-half of the dataline current I DL [n]. Each of the first switching transistor PS 1 , the second dataline transistor P 2  and the first bias transistor BP 0  is the PMOS transistor. 
     The second sub-converter  620  is electrically connected between the first dataline transistor P 1  and the another end of the coupling capacitor C C . The first sub-converter  610  and the second sub-converter  620  are operated at different time periods. The second sub-converter  620  includes a third two-terminal switching element SW 2 , a second switching transistor PS 2 , a third dataline transistor P 3 , a second bias transistor BP 1  and a fourth two-terminal switching element SW 3 . The third two-terminal switching element SW 2  is electrically connected to the first dataline transistor P 1 . The second switching transistor PS 2  is electrically connected between the third two-terminal switching element SW 2  and the power supply voltage. The third dataline transistor P 3  is electrically connected to the third two-terminal switching element SW 2  and the second switching transistor PS 2 . The second bias transistor BP 1  is electrically connected to the third dataline transistor P 3 . The fourth two-terminal switching element SW 3  is electrically connected to the second bias transistor BP 1 , the coupling capacitor C C , the stacking capacitor C S  and the second stacking transistor N 1 . The third dataline transistor P 3  has a third transistor width, and the third transistor width is equal to one-sixteenth of the first transistor width, so that a current flowed through the third dataline transistor P 3  may be equal to one-sixteenth of the dataline current I DL [n]. Each of the second switching transistor PS 2 , the third dataline transistor P 3  and the second bias transistor BP 1  is the PMOS transistor. 
     The CVSS converter  600  is controlled by the switching signals. The switching signals include a first switching signal SWS 0 , a second switching signal SWS 1 , a third switching signal SWS 2 , a fourth switching signal SWS 3 , a first enable signal EN 1 , a second enable signal EN 2 , a bias signal Sbias, a first stacking signal S 0  and a second stacking signal S 1 . The first switching signal SWS 0  is electrically connected to the first two-terminal switching element SW 0  to switch the first two-terminal switching element SW 0 . The second switching signal SWS 1  is electrically connected to the second two-terminal switching element SW 1  to switch the second two-terminal switching element SW 1 . The third switching signal SWS 2  is electrically connected to the third two-terminal switching element SW 2  to switch the third two-terminal switching element SW 2 . The fourth switching signal SWS 3  is electrically connected to the fourth two-terminal switching element SW 3  to switch the fourth two-terminal switching element SW 3 . The first enable signal EN 1  is electrically connected to the first switching transistor PS 1  to switch the first switching transistor PS 1 . The first enable signal EN 1  is equal to the first switching signal SWS 0 . The second enable signal EN 2  is electrically connected to the second switching transistor PS 2  to switch the second switching transistor PS 2 . The second enable signal EN 2  is equal to the third switching signal SWS 2 . The bias signal Sbias is electrically connected to the first bias transistor BP 0  and the second bias transistor BP 1  to control the first bias transistor BP 0  and the second bias transistor BP 1 . The first stacking signal S 0  is electrically connected to the first stacking transistor NO to control the first stacking transistor NO. The second stacking signal S 1  is electrically connected to the second stacking transistor N 1  to control the second stacking transistor N 1 . 
     In  FIG. 2 , the AGMI scheme of the memory unit  100  is operated in three bit line developing time intervals T BLD2 , T BLD1 , T BLD0  and three computing time intervals of the three input phases (e.g., WLP 2 , WLP 1 , WLP 0 ). The three input phases include a first input phase WLP 2 , a second input phase WLP 1  and a third input phase WLP 0 . The computing time interval of the first input phase WLP 2  follows the bit line developing time intervals T BLD2 . The computing time interval of the second input phase WLP 1  follows the bit line developing time intervals T BLD1 . The computing time interval of the third input phase WLP 0  follows the bit line developing time intervals T BLD0 . Each of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] has eight bits. The input sub-groups IN 76 , IN 543 , IN 210  include a first input sub-group IN 76 , a second input sub-group IN 543  and a third input sub-group IN 210 , and the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  have two bits, three bits and three bits, respectively. Therefore, the memory unit  100  with the AGMI scheme and the CVSS scheme for the nvCIM applications of the present disclosure not only utilizes the AGMI scheme to reduce the computing latency, decrease the array energy consumption and achieve larger signal margin of most significant bit part (MSB part, MSP), but also utilizes the CVSS scheme to decrease the energy consumption of place value computing, a sense amplifier and a reference generator. 
       FIG. 4  shows timing diagrams of voltage levels of a plurality of 8-bit input signals IN 0 [7:0]-IN 3 [7:0], a plurality of switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ) and an output voltage V SUM  and a current level of a dataline current I DL [n], in accordance with an example of the 8-bit input signals IN 0 [7:0]-IN 3 [7:0] of the present disclosure. In  FIG. 4 , the 8-bit input signals IN 0 [7:0]-IN 3 [7:0] are “10010100”, “01111000”, “11101001”, “00100111”, respectively. In the 8-bit input signal IN 0 [7:0], the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  are “10”, “010” and “100”, respectively. In the 8-bit input signal IN 1 [7:0], the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  are “01”, “111” and “000”, respectively. In the 8-bit input signal IN 2 [7:0], the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  are “11”, “101” and “001”, respectively. In the 8-bit input signal IN 3 [7:0], the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  are “00”, “100” and “111”, respectively. The input sub-groups IN 76 , IN 543 , IN 210  are sequentially inputted to the word lines WL[0]-WL[3]. It is assumed that the resistive element of each of the non-volatile memory cells  210  is in LRS. The memory cell currents I MC[0] , I MC[1] , I MC[2] , I MC[3]  may be generated according to a state of the resistive element of each of the non-volatile memory cells  210  and the multi-bit input signals IN 0 [7:0]-IN 3 [7:0], as shown in  FIG. 3 . The dataline current I DL [n] corresponding to the bit-line current I BL  may be generated according to the memory cell currents I MC[0] , I MC[1] , I MC[2] , I MC[3] . During the first input phase WLP 2 , there are three computing sub-time intervals (i.e., 3×T U-WCVSS1 ) for sampling according to the first input sub-group IN 76  of each of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0]. During the second input phase WLP 1 , there are seven computing sub-time intervals (i.e., 7×T U-WCVSS2 ) for sampling according to the second input sub-group IN 543  of each of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0]. During the third input phase WLP 0 , there are seven computing sub-time intervals (i.e., 7×T U-WCVSS2 ) for sampling according to the second input sub-group IN 210  of each of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0]. 
       FIG. 5  shows a circuit diagram of each of a plurality of initial operations of the CVSS converter  600  of the memory unit  100  during each of a plurality of bit line developing time intervals T BLD2 , T BLD1  of  FIG. 4 . In  FIGS. 4 and 5 , the dataline current I DL [n] flows through the first dataline transistor P 1 . The first sub-converter  610  and the second sub-converter  620  are turned off by setting the first switching signal SWS 0  and the third switching signal SWS 2  to 0. The first stacking transistor NO and the second stacking transistor N 1  are turned on by setting the first stacking signal S 0  and the second stacking signal S 1  to 1. The output voltage V SUM  is equal to the ground voltage during each of the bit line developing time intervals T BLD2 , T BLD1 . 
       FIG. 6  shows a circuit diagram of each of a first converting operation and a second converting operation of the CVSS converter  600  of the memory unit  100  during each of a first input phase WLP 2  and a second input phase WLP 1  of  FIG. 4 . In  FIGS. 4 and 6 , the dataline current I DL [n] flows through the first dataline transistor P 1 . The first sub-converter  610  is turned on by setting the first switching signal SWS 0  and the second switching signal SWS 1  to 1. The second sub-converter  620  is turned off by setting the third switching signal SWS 2  and the fourth switching signal SWS 3  to 0. The first stacking transistor NO is turned off by setting the first stacking signal S 0  to 0, and the second stacking transistor N 1  is turned on by setting the second stacking signal S 1  to 1. The output voltage V SUM  rises to a first sum voltage V SUM-P2  during the first input phase WLP 2 . The output voltage V SUM  rises to a second sum voltage V SUM-P1  during the second input phase WLP 1 . 
       FIG. 7  shows a circuit diagram of a third converting operation of the CVSS converter  600  of the memory unit  100  during a third input phase WLP 0  of  FIG. 4 . In  FIGS. 4 and 7 , the dataline current I DL [n] flows through the first dataline transistor P 1 . The first sub-converter  610  is turned off by setting the first switching signal SWS 0  and the second switching signal SWS 1  to 0, and the second sub-converter  620  is turned on by setting the third switching signal SWS 2  and the fourth switching signal SWS 3  to 1. The first stacking transistor NO and the second stacking transistor N 1  are turned off by setting the first stacking signal S 0  and the second stacking signal S 1  to 0. The output voltage V SUM  rises to a third sum voltage V SUM-P0  during the third input phase WLP 0 . The third sum voltage V SUM-P0  is greater than the second sum voltage V SUM-P1  and is equal to the second sum voltage V SUM-P1  plus a stacking voltage V STACK  because of the CVSS scheme. 
       FIG. 8  shows timing diagrams of voltage levels of a plurality of 8-bit input signals IN 0 [7:0]-IN 3 [7:0], a plurality of switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ) and an output voltage V SUM  and a current level of a dataline current I DL [n], in accordance with another example of the 8-bit input signals IN 0 [7:0]-IN 3 [7:0] of the present disclosure. In  FIG. 8 , the 8-bit input signals IN 0 [7:0]-IN 3 [7:0] are “10011101”, “10010000”, “01101010”, “01100000”, respectively. In the 8-bit input signal IN 0 [7:0], the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  are “10”, “011” and “101”, respectively. In the 8-bit input signal IN 1 [7:0], the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  are “10”, “010” and “000”, respectively. In the 8-bit input signal IN 2 [7:0], the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  are “01”, “101” and “010”, respectively. In the 8-bit input signal IN 3 [7:0], the first input sub-group IN 76 , the second input sub-group IN 543  and the third input sub-group IN 210  are “01”, “100” and “000”, respectively. The input sub-groups IN 76 , IN 543 , IN 210  are sequentially inputted to the word lines WL[0]-WL[3]. It is assumed that the resistive element of each of the non-volatile memory cells  210  is in LRS. The memory cell currents I MC[0] , I MC[1] , I MC[2] , I MC[3]  may be generated according to a state of the resistive element of each of the non-volatile memory cells  210  and the multi-bit input signals IN 0 [7:0]-IN 3 [7:0], as shown in  FIG. 3 . The dataline current I DL [n] corresponding to the bit-line current I BL  may be generated according to the memory cell currents I MC[0] , I MC[1] , I MC[2] , I MC[3] . During the first input phase WLP 2 , there are two computing sub-time intervals having two sampling time intervals T sample1  for sampling according to the first input sub-group IN 76  of each of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0]. During the second input phase WLP 1 , there are five computing sub-time intervals having five sampling time intervals T sample2  for sampling according to the second input sub-group IN 543  of each of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0]. During the third input phase WLP 0 , there are five computing sub-time intervals having five sampling time intervals T sample2  for sampling according to the second input sub-group IN 210  of each of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0]. 
       FIG. 9  shows timing diagrams of a current level of a dataline current I DL [n] and voltage levels of a plurality of switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ) and an output voltage V SUM , in accordance with an example of a plurality of 4-bit input signals of the present disclosure. In  FIGS. 6 and 9 , the first sub-converter  610  of the CVSS converter  600  is performed with the 4-bit input signals without the second sub-converter  620 . The output voltage V SUM  rises to the first sum voltage V SUM-P2  during the first input phase WLP 2 . The output voltage V SUM  rises to the second sum voltage V SUM-P1  during the second input phase WLP 1 . During the first input phase WLP 2 , there are three computing sub-time intervals having three sampling time intervals for sampling according to the first input sub-group IN 32  of each of the 4-bit input signals. During the second input phase WLP 1 , there are three computing sub-time intervals having three sampling time intervals for sampling according to the second input sub-group IN 10  of each of the 4-bit input signals. 
       FIG. 10  shows a flow chart of a computing method  700  of a memory unit  100  with an AGMI scheme and a CVSS scheme for a plurality of nvCIM applications according to another embodiment of the present disclosure. In  FIGS. 1, 3 and 10 , the computing method  700  includes performing a voltage level applying step S 02  and a computing step S 04 . The voltage level applying step S 02  includes applying a plurality of voltage levels to the multi-bit input signals (e.g., IN 0 [7:0]-IN 3 [7:0]) and the switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ). The computing step S 04  includes driving the controller  400  to split the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] into the input sub-groups IN 76 , IN 543 , IN 210 , driving the controller  400  to sequentially input the input sub-groups IN 76 , IN 543 , IN 210  to the word lines WL[0]-WL[3], driving the CVSS converter  600  to convert the bit-line current I BL  into a plurality of converted voltages according to the input sub-groups IN 76 , IN 543 , IN 210  and the switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ), and driving the CVSS converter  600  to stack the converted voltages to form an output voltage V SUM . The output voltage V SUM  is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] multiplied by the weights W 0 [0]-W 3 [0]. 
     In the voltage level applying step S 02 , the switching signals include a first switching signal SWS 0 , a second switching signal SWS 1 , a third switching signal SWS 2 , a fourth switching signal SWS 3 , a first enable signal EN 1 , a second enable signal EN 2 , a bias signal Sbias, a first stacking signal S 0  and a second stacking signal S 1 . The first switching signal SWS 0  is applied to the first two-terminal switching element SW 0  to switch the first two-terminal switching element SW 0 . The second switching signal SWS 1  is applied to the second two-terminal switching element SW 1  to switch the second two-terminal switching element SW 1 . The third switching signal SWS 2  is applied to the third two-terminal switching element SW 2  to switch the third two-terminal switching element SW 2 . The fourth switching signal SWS 3  is applied to the fourth two-terminal switching element SW 3  to switch the fourth two-terminal switching element SW 3 . The first enable signal EN 1  is applied to the first switching transistor PS 1  to switch the first switching transistor PS 1 . The second enable signal EN 2  is applied to the second switching transistor PS 2  to switch the second switching transistor PS 2 . The bias signal Sbias is applied to the first bias transistor BP 0  and the second bias transistor BP 1  to control the first bias transistor BP 0  and the second bias transistor BP 1 . The first stacking signal S 0  is applied to the first stacking transistor NO to control the first stacking transistor NO. The second stacking signal S 1  is applied to the second stacking transistor N 1  to control the second stacking transistor N 1 . The first switching signal SWS 0  is equal to the first enable signal EN 1 . The third switching signal SWS 2  is equal to the second enable signal EN 2 . The switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ) are applied by the controller  400 . 
     In the computing step S 04 , the AGMI scheme and the CVSS scheme are performed to generate the output voltage V SUM  by the non-volatile memory array  200 , the word line driver  300 , the controller  400 , the column multiplexer  500  and the CVSS converter  600 . In detail, the non-volatile memory array  200  is driven to generate the memory cell currents I MC[0] , I MC[1] , I MC[2] , I MC[3]  according to the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] and the weights W 0 [0]-W 3 [0]. The non-volatile memory array  200  generates a bit-line current I BL  according to the memory cell currents I MC[0] , I MC[1] , I MC[2] , I MC[3] . The word line driver  300  is driven to generate the voltage levels of the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] and transmit the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] to the non-volatile memory array  200  via the word lines WL[0]-WL[3]. The controller  400  is driven to split the multi-bit input signals IN 0 [7:0]-IN 3 [7:0] into the input sub-groups IN 76 , IN 543 , IN 210  and sequentially input the input sub-groups IN 76 , IN 543 , IN 210  to the word lines WL[0]-WL[3]. The column multiplexer  500  is driven to generate a dataline current I DL [n] according to the bit-line current I BL . The CVSS converter  600  is driven to convert the bit-line current I BL  into the converted voltages according to the input sub-groups IN 76 , IN 543 , IN 210  and the switching signals (e.g., SWS 0 -SWS 3 , EN 1 , EN 2 , S 0 , S 1 ) and stack the converted voltages to form the output voltage V SUM . 
       FIG. 11  shows a comparison result of array energy consumption among the memory unit  100  with the AGMI scheme of the present disclosure, a memory unit with a conventional fully-decoded wordline pulse-count input scheme and a memory unit with a conventional fully-decoded wordline pulse-width input scheme.  FIG. 12  shows a comparison result of most significant bit part (MSP) signal margin among the memory unit  100  with the AGMI scheme of the present disclosure, the memory unit with the conventional fully-decoded wordline pulse-count input scheme and the memory unit with the conventional fully-decoded wordline pulse-width input scheme. In  FIGS. 11 and 12 , the 8-bit input signals and 8-bit weights are used to generate the comparison results of array energy consumption and MSP signal margin. The memory unit with the conventional fully-decoded wordline pulse-count input scheme and the memory unit with the conventional fully-decoded wordline pulse-width input scheme suffer long latency due to a lower number of parallel inputs that need multiple cycles for applying inputs to nvCIM and corresponding computing operations. The AGMI scheme of the present disclosure can drastically decrease the energy consumption of the cell array (i.e., array energy consumption) by 38.93X-232.19X and achieve 13X larger signal margin of MSP compared to the conventional input schemes, respectively. 
       FIG. 13  shows a comparison result of energy consumption between the memory unit  100  with the CVSS scheme of the present disclosure and a memory unit with a conventional fully current summation scheme. In  FIG. 13 , the 4-bit input signals and 4-bit weights are used to generate the comparison result of energy consumption. The energy consumption composed of the sense amplifier and the reference generator can be decreased by 33% with the CVSS scheme of the present disclosure compared to the conventional fully current summation scheme. The energy consumption composed of place value computing can be decreased by 35% with the CVSS scheme of the present disclosure compared to the conventional fully current summation scheme. The energy consumption composed of place value computing, the sense amplifier and the reference generator can be decreased by 34% with the CVSS scheme of the present disclosure compared to the conventional fully current summation scheme. 
     According to the aforementioned embodiments and examples, the advantages of the present disclosure are described as follows. 
     1. The memory unit with the AGMI scheme and the CVSS scheme for the nvCIM applications and the computing method thereof of the present disclosure can be applied to nvCIM macro for high precision of MAC computing with short latency, high energy efficiency, and robust MAC readout operation. The waveform shows the MAC operation of four 8-bit input signals which are applied serially in three input phases with four word lines activated simultaneously. The output voltages in different phases are accumulated and stacked by the CVSS converter. 
     2. The memory unit with the AGMI scheme and the CVSS scheme for the nvCIM applications of the present disclosure not only utilizes the AGMI scheme to reduce the computing latency, decrease the array energy consumption and achieve larger signal margin of MSP, but also utilizes the CVSS scheme to decrease the energy consumption of place value computing, the sense amplifier and the reference generator. 
     3. The AGMI scheme of the present disclosure can drastically decrease the energy consumption of the cell array by 38.93X-232.19X and achieve 13X larger signal margin of MSP compared to the conventional input schemes, respectively. 
     4. The energy consumption composed of place value computing, the sense amplifier and the reference generator can be decreased by 34% with the CVSS scheme of the present disclosure compared to the conventional fully current summation scheme. 
     Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.