Patent Publication Number: US-5630170-A

Title: System and method for determining peripheral&#39;s communication mode over row of pins disposed in a socket connector

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an improvement in communication between a data processing apparatus and a peripheral device to be connected to the data processing apparatus, and more specifically, to a system for identifying communication modes of the peripheral devices connected to a game apparatus and connector configurations suitable to the peripheral devices with various types of communication modes. 
     2. Description of Related Art 
     An image processing system is known as a system which has a display such as a television set, (hereinafter, referred to as a &#34;monitor&#34;), on which images are time-dependently displayed. As is widely known for home use, a game apparatus is one representative of such image processing systems. 
     The game apparatus comprises a processing unit executing game programs and generating video and audio signals. To the apparatus are connected various types of peripheral devices (frequently, referred to as simply &#34;peripherals&#34;) such as manipulating switching assemblies called joy pad, controller, or key board. The processing unit mainly performs not only a predetermined image processing therein but also a variety of processings including control of the peripheral devices. The peripheral devices are used, for example, for inputting necessary information from an operator into the processing unit and for displaying image data such as graphic and character data supplied from the processing unit. The peripheral devices thus typically include an operator controller and a monitor having a screen and speaker. 
     When the processing unit to which the monitor and operator controller are connected is activated by a player or an operator, the monitor is able to display images on its screen and to produce sound from its speaker, depending on instructions of a given game software sent from the processing unit. The player can enjoy the game with the game apparatus. 
     The game apparatus is normally required to be able to carry out various games. This means that there is much possibility that various types of peripheral devices are connected to the processing unit. 
     Various interfaces are arranged between the processing unit and the peripheral devices in aid of communication therebetween. Further, because communication modes are often varied depending on the peripheral device, the processing unit is required to obtain information (peripheral identification data) representing the type of a connected peripheral device. For this requirement, it is proposed that the type of a connected peripheral device can be identified using logical values acquired through data lines of the peripheral device when the processing unit sends twice to the peripheral device a peripheral selection signal of logical values of &#34;1&#34; firstly, and then of &#34;0&#34;. Such prior art is disclosed in Japanese patent Laid-open No.2-62618, for example. 
     However, the above identification method identifies in fact only the type of a connected peripheral device on the basis of logical values acquired though data lines of the device. In other words, this identification method does not give attention to the communication mode of a connected peripheral device. This results in a drawback that, frequently, connected peripheral devices cannot send data to the processing unit and also the processing unit cannot control the peripheral devices with preferable communication modes for those peripheral devices. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to make it possible for a data processing apparatus to communicate for data transmission employing various types of communication modes with various peripheral devices. 
     Another object of the present invention is to provide a data processing apparatus adaptable to various types of communication modes. 
     Still another object of the present invention is to provide a connector plug configuration, which connects a peripheral device to a data processing apparatus adaptable to various types of peripheral devices. 
     Still another object of the present invention is to provide a peripheral device having a connector assembly suitable for transmission of control signals and data with a data processing apparatus. 
     Still another object of the present invention is to provide a data processing apparatus with a system for identifying various types of communication modes of peripheral devices connected to the apparatus. 
     Still another object of the present invention is to provide a data processing apparatus with a system for controlling various types of peripheral devices connected to the apparatus through a connector with an improved pin or terminal contact configuration. 
     According to one aspect of the invention, directed to one or more of the above objects, there is provided a peripheral device for use with a data processing apparatus having a peripheral port. The peripheral device includes a connector detachably connectable to the peripheral port, the connector having a set of terminal contacts including first to ninth contacts disposed in a row. The first contact is for connecting to one of a power source potential and ground potential; and the ninth contact is for connecting to the other of the power source potential and the ground potential. The second, third, seventh and eighth contacts are for transmitting data signals. The fourth to sixth contacts are for transmitting control signals. The apparatus further includes a cable including a plurality of wires connecting ones of the terminal contacts of the connector with a printed circuit board of the peripheral device and includes means for transmitting data signals including identification data representing a communication mode of the peripheral device to the data processing apparatus via at least one of the second, third, seventh and eighth contacts in synchronism with a clock signal supplied from the data processing apparatus when the connector is connected to the peripheral port. 
     According to one implementation of this aspect of the invention, there is provided a peripheral device for use with a data processing apparatus, the apparatus having a peripheral port with a set of terminal pins consisting of first to ninth pins disposed in a row. The first pin is for connecting to one of a power source and ground potential; and the ninth pin is for connecting to the other of the power source and the ground potential. The second, third, seventh and eighth pins are for conducting data signals and the fourth to sixth pins are for conducting control signals. The apparatus has means for determining a communication mode for communicating with a peripheral device connected to the peripheral port based on the data signals received on the second, third, seventh and eighth pins. 
     Further, the peripheral device includes a plug connector detachably connectable to the peripheral port, the plug connector having a set of terminal pins consisting of first to ninth pins disposed in a row correspondingly to the first to ninth pins of the peripheral port. The peripheral device further includes a cable including a plurality of wires connecting ones of the terminal pins of the plug connector with a printed circuit board of the peripheral device and means for transmitting data signals including identification data representing the communication mode of the peripheral device via at least one of the second, third, seventh and eighth pins in synchronism with a clock signal supplied from the apparatus when the plug connector is connected to the peripheral port. 
     According to another aspect of the invention, there is provided a game apparatus including a data processing apparatus having a peripheral port with a plurality of terminal pins disposed in a row. The terminal pins include a pair of first pins. One of the first pins is for connecting to one of a power source and ground potential and the other of the first pins is for connecting to the other of the power source and the ground potential. The terminal pins include at least one second pin for conducting data signals and a plurality of third pins for conducting control signals. The data processing apparatus further has means for determining a communication mode based on the data signals conducted by the at least one second pin, means for conducting a clock signal via one of the third pins, and means for communicating in the determined communication mode. 
     The game apparatus further includes a peripheral device having a plug connector detachably connected to the peripheral port, the plug connector having a plurality of contacts identical in number and disposed in a row in correspondence to the terminal pins of the peripheral port. The peripheral device further has a cable including a plurality of wires connecting the contacts of the plug connector with a printed circuit board of the peripheral device and means for transmitting data signals including identification data, representing the communication mode of the peripheral device via the at least one second pin to the data processing apparatus in synchronism with the clock signal when the plug connector is connected to peripheral port. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a perspective illustration of a game system embodying the present invention; 
     FIG. 2 is a basic block diagram showing the game system; 
     FIG. 3 is a block diagram showing the connection between a main CPU and a sub CPU functioning as a system for managing and controlling peripheral devices and showing the block diagram of the sub CPU; 
     FIG. 4 shows a connector configuration of peripheral ports; 
     FIGS. 5A to 5C are pin configurations of plug connectors employed to accommodate typical communication modes; 
     FIGS. 6A to 6D are functional block diagrams of typical controllers as peripheral devices; 
     FIG. 7 is a flowchart exemplifying a processing carried out by the sub CPU; 
     FIG. 8 is a flowchart of an access subroutine to peripheral devices; 
     FIG. 9 shows a flowchart of an access subroutine for a three-wire handshake type of communication mode; 
     FIG. 10 shows a flowchart of an access subroutine for a clocked parallel type of communication mode; 
     FIG. 11 is a flowchart of an access subroutine for a clocked serial type of communication mode; 
     FIG. 12 represents a timing chart of control signals and data for the three-wire handshake type of communication mode; 
     FIG. 13 represent a timing chart of control signals and data for the clocked parallel type of communication mode; and 
     FIG. 14 is a timing chart of control signals and data for the clocked serial type of communication mode. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention will now be explained with reference to FIGS. 1 to 14. 
     FIG. 1 shows a perspective view of a game system 1 to which the present invention is applied. The game system 1 comprises a game apparatus 2 functioning as the data processing apparatus for processing game programs and controlling various operations and control switch assemblies or controllers 3a and 3b as an example of peripheral devices to the game apparatus. As for the controllers, such control keys disclosed in U.S. patent application Ser. No. 08/245,446 may be used. The apparatus 2 is provided with connector ports 4a and 4b for connecting peripheral devices. As also seen in FIG. 4, each of the connector ports 4a and 4b has a socket or a socket connector 4as(4bs) to which a plug or a plug connector 4ap(4bp) can be connected and disconnected. 
     The plugs 4ap and 4bp are connected to the controllers 3a and 3b through cables 5a and 5b, respectively. The controllers 3a and 3b are electrically and functionally connected to internal circuits of the game apparatus 2 via the cables 5a and 5b when the plugs 4ap and 4bp are inserted into the sockets 4as and 4bs. 
     Each of the plugs 4ap and 4bp has a configuration of plug pins which ensures transmission of a communication mode employed for the controllers 3a and 3b to the game apparatus 2. Further, the apparatus 2 comprises a video output terminal and an audio output terminal not shown. 
     The video output terminal is connected to a video input terminal 7a of a monitor 6, such a television set, through a cable 8a. Also the audio output terminal is connected to an audio input terminal 7b of the monitor 6 through a cable 8b. 
     The game apparatus 2 has a CD-ROM drive block 14 positioned at the central portion thereof. The CD-ROM drive block 14 is installed with a CD-ROM drive 9 and an optical pickup to read game program data or audio/video software from CD-ROM discs mounted thereto. The apparatus is further provided with a cartridge port 10 positioned at the rear side of the CD-ROM drive block 9. The cartridge port portion 10 is installed therein with a socket connector to which are connected devices such as a ROM/RAM cassette or an optional adapter for providing additional functions (not shown). 
     The apparatus 2 carries out a wide variety of information processings and controls such as image processings, audio processings and control of peripheral devices as well as processing of game programs. The controllers 3a and 3b provide operating signals to the apparatus 2. Video and audio signals generated by the apparatus 2 are given to the monitor 6 through the cables 8a and 8b. 
     FIG. 2 exemplifies a block diagram of the game apparatus 2. The apparatus 2 shown therein comprises a processing block 11, video block 12, audio block 13, and auxiliary block or CD-ROM drive block 14. The cartridge port 10 includes a cartridge interface (I/F) 15 and the auxiliary block 14 includes a compact disk interface (I/F) 16. 
     The processing block 11 comprises a main processing unit (CPU) 21, RAM 22, ROM 23, system control unit 24, and sub CPU 25. The main CPU 21 is functionally connected, via a bus line 26, to the RAM 22, ROM 23, system control unit 24, and sub CPU 25. 
     Through the bus line 26, system control unit 24 and a bus line 17, the main CPU 21 is functionally connected with the video block 12, audio block 13, cartridge I/F 15, and CD I/F 16. The CD I/F 16 of the auxiliary block 14 is connected with the CD-ROM drive 9. 
     The main CPU 21 controls the entire processings of the system. In order to enhance control capability, the main CPU 21 consists of 32-bit RISC type high speed CPUs (two CPU chips called SH-2) and provides an improved, high speed calculating operation which may function similarly as a digital signal processor (DSP). 
     RAM 22 has, for example, a memory capacity of 32 megabits in all, a memory area of 16 megabits of which is assigned to the main CPU 21, for example. The remaining memory area of the RAM 22 is assigned to the video block 12 and audio block 13. ROM 23 stores initial programs or bootstrap programs for the hardware and for the cassette ROM and the CD-ROM. 
     The system control unit 24 functions as a co-processor to the main CPU 21 so that the unit 24 interfaces 16 bit bus 17 to which the video block 12, audio block 13 and auxiliary block 14 are connected with 32 bit bus 26 to which the main CPU 21 is connected. 
     When the electric power is on and/or a reset button is pushed down, the sub CPU 25 not only resets the entire system but also carries out data collection from the peripheral devices such as the controllers 3a and 3b to control the peripheral devices. Also the sub CPU 25 can change the clock frequency of the entire system. 
     The sub CPU 25 further includes a connection-exchanging means described below. The connection-exchanging means selectively connects the peripheral devices such as the controllers 3a and 3b connected to the connector ports 4a and 4b with either a CPU core 31 (refer to FIG. 3) in the sub CPU 25 or the main CPU 21. 
     The video block 12 forms video signals on the basis of video control signals given from the main CPU 21 through the system control unit 24 and provides the monitor 6 the video signals through the cable 8a. This permits the monitor 6 to display images on its screen. The details of the video block 12 may be referred to PCT/JP94/01068 (filed Feb. 24, 1995 in U.S.), PCT/JP94/01067 (filed Feb. 27, 1995 in U.S.), PCT/JP94/01066 (filed Feb. 27, 1995 in U.S.). 
     The audio block 13 generates digital audio signals on the basis of audio control signals given from the main CPU 21 through the system control unit 24, converts those digital audio signals into corresponding analog audio signals by a digital/analog (DA) converter incorporated therein, and provides the monitor 6 the converted analog audio signals through the cable 8b. Such processing permits an audio speaker of the monitor 6 to produce sound. 
     The sub CPU 25 will be explained with reference to FIG. 3. FIG. 3 represents in block diagram the configuration of the sub CPU 25 which acts as a unit for controlling and managing peripheral devices. As shown in the figure, the sub CPU 25 is coupled with the main CPU 21 by way of the bus line 26. The sub CPU 25 comprises a CPU core 31, ROM 32, RAM 33, register table 34, register group 35, multiplexer 36, and I/O interface 37. 
     The CPU core 31, for example, may be a 4-bit CPU. The CPU core 31 is coupled with the ROM 32 to receive required programs from the ROM 32. Coupled with the CPU core 31 through a bus line 38 are the RAM 33, register table 34, and the register group 35. Further, the register group 35 is coupled with the I/O interface 37 via the multiplexer 36. The register group 35 and multiplexer 36 compose the connection-exchanging means 40. 
     The register group 35 may be sub-grouped into a main-CPU register group 351, a sub-CPU register group 352, and an I/O section register 353. The main-CPU register group 351 has two terminals; one is connected with the main CPU 21 through a bus line 39 and the bus line 26, while the other is connected with one of the two exchanging terminals of the multiplexer 36. The sub-CPU register group 352 has also two terminals; one is connected with the CPU core 31 through a bus line 38, while the other is connected with the other of the exchanging terminals of the multiplexer 36. 
     The multiplexer 36 has a common terminal connected with the I/O interface 37. The interface I/O 37 is connected with the connector ports 4a and 4b. The connector ports 4a and 4b are connected, through cables 5a and 5b, with the controllers 3a and 3b, respectively. 
     In response to data specified in the I/O section register 353, the multiplexer 36 functionally connects the peripheral devices such as the controllers 3a and 3b selectively to either the CPU core 31 through the register group 352 and bus line 38 or the main CPU 21 through the register group 351 and bus lines 39 and 26. 
     The CPU core 31 is designed such that, when the CPU core 31 is electrically connected with the peripheral devices via the multiplexer 36, the CPU core 31 communicates with the peripheral devices in the order of &#34;peripheral ID-1&#34;, &#34;peripheral ID-2&#34;, &#34;data size&#34; and &#34;data&#34;, decides a communication mode from those IDs (identification data), and then performs collection, transmission and exchanges etc. of the data. 
     In this embodiment, the data &#34;peripheral ID-1&#34;, which consists of 4-bit data, represents a communication mode as well as the type of a peripheral device. The data &#34;peripheral ID-2&#34;, which also consists of 4-bit data, is a type of data representing the device model of a peripheral device and consists of a set of data showing a device model focusing on signal types showing whether the signal is, for example, analog or digital. The &#34;data size&#34; represents the total bite number of data from a peripheral device and will be shown by references &#34;DSIZE0 to DSIZE3&#34; in figures described below. The &#34;data&#34; represents data, which are supplied from a peripheral device, of the total bite number specified by the &#34;data size&#34;. The CPU core 31 reads the data having the above total number at every 4-bit, because the CPU core 31 is a 4-bit processor in this embodiment. 
     Although the register group 35, multiplexer 36 and I/O interface 37 have two-channel circuits, respectively, this embodiment shows only one-channel circuit for simplified explanation. 
     Details of sub CPU 25 may be referred to co-pending Japanese patent applications Nos. 6-246579 and 6-246580 (see U.S. application Ser. No. 08/656,226). 
     As shown in FIG. 4 the I/O interface has two channels connected to peripheral ports 4a and 4b. Each of the peripheral ports 4a and 4b has a set of socket pins 1 through 9. Pins 2 through 8 are connected to I/O interface and assigned to send and receive a set of specific signals. Names and functions of the signals are shown in Table 1. 
     As shown in FIG. 4, each of plugs 4ap and 4bp which are to be connected to the sockets 4as and 4bs respectively has a set of plug pins 1 through 9 corresponding to the socket pins 1 through 9. The plug 4ap and 4bp are connected to main circuits of peripheral devices via cables 5a and 5b. 
     
                       TABLE 1                                                     
______________________________________                                    
Signal Name                                                               
           Pin No.      Remarks                                           
______________________________________                                    
TH         4            Control signal from                               
                        game apparatus                                    
TR         5            Control signal from                               
                        game apparatus                                    
TL         6            Control signal to                                 
                        game apparatus(ack)                               
R          7            Data signal (third                                
                        bit)                                              
L          8            Data signal (second                               
                        bit)                                              
D          2            Data signal (first                                
                        bit)                                              
U          3            Data signal (0-th                                 
                        bit)                                              
Vcc        1            Power Source(+5V)                                 
GND        9            GND                                               
______________________________________                                    
 
    
     Pins nos. 4 to 6 are assigned for control signals. Pin no. 4 is the first control pin and assigned for transmitting a peripheral selection signal TH from the game apparatus 2 to the peripheral device (for example, controllers 3a, 3b). Pin no. 5 is the second control pin and assigned for transmitting a data request signal TR from the game apparatus to the peripheral device. Pin no. 6 is the third control pin and assigned for transmitting a peripheral acknowledgement signal TL from the peripheral device to the game apparatus. 
     Pins nos. 2, 3, 7 and 8 are assigned for data signals. Pin no. 2 (the first data pin) is assigned for transmitting a bit data D, pin no. 3 (the second data pin) for a bit data U, pin no. 7 (the third data pin) for a bit data R, and pin no. 8 (the fourth data pin) for a bit data L, respectively. The data R is mainly used for data transmission to the game apparatus 2. The input/output directions of data for these signals D, U, R and L can optionally be specified in accordance with the kind of the peripheral device connected to the apparatus 2. The signal R represents the third bit of the data, L the second bit, D the first bit and U the 0-th bit, respectively. 
     Pins 2 through 8 are connected to an electric power source Vcc by way of resistors 411, respectively, thereby to pull up the voltage levels of the signal lines (pins nos. 2 to 8) to the level of the power source Vcc. 
     When a peripheral device is not connected to the port 4a (4b) the voltage level on each of pins nos. 2 to 8 is equal to the voltage value of the power source Vcc (i.e. logical value=binary value &#34;1&#34;). Thus, the sub CPU 25 identifies that a peripheral device is not connected to the socket 4as (4bs) when it receives these data of the voltage state &#34;1&#34;, for example, for D, U, R and L. 
     Pins nos. 5 and 6 are mainly assigned for transmitting control signals between the game apparatus and the peripheral devices in the above description. However, pins 5 and 6 may be used for data signal transmission where a peripheral device employs either the clocked parallel communication mode or clocked serial communication mode which will be described below. 
     Pin no. 3 is assigned to the signal Vcc which represents the power source (voltage: +5 V). The pin no. 9 is assigned to the signal GND which represent the ground potential (voltage: zero). 
     FIGS. 5A to 5C explains a variety of pin configurations for plugs 4ap and 4bp which vary depending on communication modes employed by peripheral devices. FIG. 5A shows a pin configuration for standard communication modes including a TH/TR-selection communication mode and a three-wire handshake communication mode, FIG. 5B shows a pin configuration for a clocked parallel communication mode (clock-synchronized-type parallel communication mode), and FIG. 5C shows a pin configuration for a clocked serial communication mode (clock-synchronized-type serial communication mode), respectively. The clocked parallel and serial communication modes correspond to the non-standard type of modes. 
     These pin configurations are prepared to easily accommodate a large number of types of peripheral devices, such as a control PAD, mouse, key board, modem and memory unit, and different communication modes which may change according to peripheral devices. 
     Typical communication modes employed by a variety of peripheral devices are, for example, a TH/TR-selection communication mode, a three-wire handshake mode, a clocked parallel mode, and a clocked serial mode. A peripheral device employing the TH/TR-selection and three-wire handshake communication modes requires all of the socket/plug pins 1 through 9 of the connector port 4a (4b) to be used electrically independently. Accordingly, as shown in FIG. 5A, all the pins 1 through 9 of the plug 4ap (4bp) are not short-circuited to each other. 
     On the other hand, where a peripheral device employs the clocked parallel communication mode, pin no. 5 assigned for the data request signal TR and pin no. 6 assigned for peripheral acknowledgment signal TL can electrically be short-circuited as shown in FIG. 5B. Further, in case of a peripheral device employing the clocked serial communication mode, the data transmission lines in the connector port 4a (4b) can be reduced to one line in principle, and it is possible to transmit data through the one data line in cooperation with the two peripheral selection line (TH) and data request line (TR). Accordingly, as shown in FIG. 5C, pin no. 2 may be connected to Vcc and pins 6 to 8 may be connected to GND. 
     As is exemplified above, it is understood that each of the connector ports 4a and 4b have a certain requirement in the number of needed signal lines (i.e., pins), which is determined in accordance with the employed communication mode. The processing apparatus 2 can use logical values on specified signal lines (in other words, specified pins) at the connector ports 4a and 4b to decide communication modes. Namely the apparatus 2 can determine the communication modes according to the logical values on the signal lines (pins). 
     Thus, in order to identify the employed communication mode, it should be essential to know the numbers of pins required to transmit data and the logical values on each signal line (i.e., each specified pin). In the present embodiment, the pin configurations of the plugs are designed to be able to transmit effectively to the apparatus 2 the logical values required to decide the communication mode employed by a peripheral device. In consequence, the apparatus 2 can quickly decide the employed communication mode. 
     Where the communication mode of a peripheral device is clocked parallel mode, the pin configuration of each plug 4ap (4bp) of the connectors are shown in FIG. 5B. In this mode, the apparatus 2 transmits to the controllers 3a and 3b a specified logical value (&#34;1&#34; or &#34;0&#34;) as the peripheral selection signal TH and given clock signals as the data request signal TR. In response to this, signals of required logical values are then quickly provided through the data lines from the controllers 3a and 3b in synchronization with the clock signals. As shown in FIG. 5B, the pin 5 for the data request signal TR is short-circuited with the pin 6 for the peripheral acknowledgment signal TL in this clocked parallel communication mode, thereby the signals (voltages) on both the plug pins no. 5 and 6 being the same. Accordingly the signal TR transmitted from the apparatus 2 to pin no. 5 is sent back almost simultaneously from pin no. 6 to the apparatus 2 as the signal TL. Thus, the apparatus 2 identifies the clocked parallel mode by sensing signal TL equal to signal TR. 
     Further, in case of a peripheral device of the clocked serial communication mode, only one signal line (U) is required to transmit data. In addition, only the peripheral selection signal line (TH) and data request signal line (TR) transmitting clock signals are required as control lines. Logical values needed to identify this communication mode may be set as R=L=&#34;0&#34;, D=&#34;1&#34;, and U=&#34;0&#34;. These requirements may be realized by such pin configurations of the plugs 4ap and 4bp as shown in FIG. 5C in which plug pins which are not used for transmitting data and control signals are connected to fixed potentials (Vcc and GND). For example, pin no. 2 is connected to the power source Vcc and pins nos. 6 to 8 are connected to the ground GND, This plug-pin configuration will make it possible to produce required logical values representing the clocked serial communication mode at the pins of the plugs 4ap and 4bp, thus such logical values being supplied to the apparatus 2. 
     The short-circuit between the pins in FIGS. 5B and 5C may be achieved either by putting a short-circuit wire bridging connecting portions at which the plug pins are connected to the corresponding wires contained in the cable 5a (or 5b) in the plug or by providing a short-circuit pattern on a printed circuit board arranged in the plug 4ap (4bp). This reduces in number wires in the cable 5a (or 5b) connecting the plug 4ap (4bp) to the main circuit of a peripheral device. 
     The foregoing short-circuit can also be achieved within the main circuit of a peripheral device either by putting a short-circuit wire bridging wires of the cable 5a (or 5b) or by forming a specified short-circuit printing pattern on a printed circuit board in the peripheral device. 
     Particularly in the case of pin configuration of the plug 4ap (4bp) shown in FIG. 5C assigned to the clocked serial communication mode, the no. 2 pin is short-circuited and electrically connected to the no. 1 pin (signal Vcc; power source pin) and the pins nos. 6 to 8 are all short-circuited and electrically connected to the no. 9 pin (signal GND; ground pin), And accordingly wires in the cable connecting the plug 4ap (or 4bp) with the main circuit of a peripheral device can largely be decreased in number, because only the lines of the data signal U and the control signals TH and TL are required. 
     On one hand, when the pin configuration of FIG. 5C is effectively realized within a peripheral device, the lines of the cable, independent of signal transmission, are electrically connected to the power source and the ground potential, which leads to reduced noises which may fall onto the lines. 
     The functional schematic diagram of controllers as representatives of peripheral devices employing the foregoing various communication modes will now be explained with reference to FIGS. 6A to 6D which use, as relevant, the same reference numerals as ones described above. 
     FIG. 6A shows a controller 3a employing the TH/TR-selection type communication mode. &#34;TH/TR selection type communication mode&#34; used in this specification means a communication mode in which, as shown in Table 3, manipulation data which are generated in response to key switches on the peripheral device manipulated by an operator or a game player, as well as the identification data, are supplied to the data processing device in response to control signals. The control signals, as shown in Table 3 for example, are any of four combinations of two bit data TH and TR via the fourth and fifth pins. The controller 3a comprises the plug connector 4ap, the cable 5a having nine wires connected to the nine plug pin nos. 1 to 9 of the plug connector 4ap, and a main circuit 3M to which the wires of the cable 5a are connected. The nine plug pin nos. 1 to 9 are electrically independent from each other and individually connected to the nine wires of the cable 5a. The main circuit 3M has an operating portion 3Ma and a data generator 3Mb. The operating portion 3Ma, which is operated by a player, includes keys and/or switches. The data generator 3Mb is formed by circuits such as hardware logic circuits or a CPU system such that, as shown in Table 3, a specific group of 4-bit data R, L, D, U including data indicative of the TH/TR selection communication mode and data generated at the operating portion 3Ma by the player&#39;s operation are supplied through the plug pin nos. 2, 3, 7, 8 in response to, in Table 3, the 1st to 4th rows of bit patterns of both the peripheral selection signal TH and data request signal TR. 
     FIG. 6B shows a controller 3a employing the three-wire handshake communication mode. The controller 3a comprises the plug connector 4ap, the cable 5a having nine wires connected to the nine plug pin nos. 1 to 9 of the plug connector 4ap, and a main circuit 3M to which the wires of the cable 5a are connected. The nine plug pins 1 to 9 are electrically independent from each other and individually connected to the nine wires of the cable 5a. The main circuit 3M has an operating portion 3Ma and a CPU system 3Mb. The CPU system 3Mb has a CPU and functions as a data generator which is responsive to the switching operation of the operating portion 3Ma manipulated by the operator. The data generator formed by hardware logic circuits can be adopted as a substitute for the CPU system. The CPU system 3Mb communicates with the game apparatus 2 using the three signals TH, TR, and TL sequentially inputted or outputted through the plug connector 4ap and then supplies, as shown in FIG. 12 and Table 4, 4-bit parallel data R, L, D, U including data indicative of the three-wire handshake communication mode and data generated at the operating portion 3Ma by the player&#39;s operation of the game apparatus 2 through the plug connector 4ap. When output signals from an operating portion 3Ma are analog quantities, the operating portion 3Ma includes signal processing circuits such as an A/D convertor. 
     FIG. 6C shows a controller 3a employing the clocked parallel communication mode. The controller 3a also comprises the plug connector 4ap of nine pin nos. 1 to 9, the cable 5a, and a main circuit 3M. Among the nine plug pin nos. 1 to 9, the pins of nos. 5 and 6 are short-circuited at their pin portions to each other and the remaining pins are still electrically independent. The plug pins of Nos. 1 to 5 and 7 to 9 are coupled with the respective wires of the cable 5a. The main circuit 3M has an operating portion 3Ma and a data generator 3Mb which can be constructed using gate array circuits, for example. The main generator 3Mb, through the plug connector 4ap sequentially receives the peripheral selection signal TH and data request signal TR. In response to the reception of the signal TR, the data generator 3Mb supplies to the game apparatus 2, as shown in FIG. 13 and Table 4, 4-bit parallel data including data indicative of the clocked parallel communication mode and data generated at the operating portion 3Ma by the player&#39;s operation. As the pin No. 6 is short-circuited to the pin No. 5, the potential equal to the signal TR is conducted to the game apparatus in place of the peripheral acknowledgment signal TL. The plug pin configuration of this mode reduces the number of wires of the cable 5a by one, as shown in FIG. 6C. The clocked parallel communication mode permits the game apparatus 2 to communicate with the controller 3a in the same manner as, but with a faster response than, the three-wire handshake mode. 
     FIG. 6D shows a controller 3a employing the clocked serial communication mode. The controller 3a also comprises the plug connector 4ap of nine pins of nos. 1 to 9, the cable 5a, and a main circuit 3M. Among the nine plug pins of nos. 1 to 9, the pins of nos. 1 and 2 are short-circuited and the pins of nos. 6 to 9 are short-circuited, respectively, at their pin portions to each other and the remaining pins are still electrically independent. The plug pins of nos. 1, 3 to 5, and 9 are coupled with the respective wires of the cable 5a. The main circuit 3M has an operating portion 3Ma and a data generator 3Mb which can be constructed using gate array circuits, for example. The data generator 3Mb, through the plug connector 4ap, sequentially receives the peripheral selection signal TH and data request signal TR. The data generator 3Mb together with the pin configuration supplies to the game apparatus 2, as shown in FIG. 14 and Table 4, data indicative of a clocked serial communication mode and then, in response to clock pulse inversion, supplies to the game apparatus 2 serial data including data generated at the operating portion 3Ma. The plug pin configuration of this mode remarkably reduces the number of wires of the cable 5a by four, as shown in FIG. 6D. 
     In FIGS. 6C and 6D, such short-circuit configuration can be achieved in the side of the main circuit 3M. 
     In the present embodiment, when the plug 4ap (or 4bp) connected to the controller 3a (or 3b) is inserted into the socket 4as (or 4bs) arranged in the apparatus 2, the foregoing plug pin configurations permit the sub CPU 25 to communicate to process in the order of &#34;peripheral ID-1&#34;, &#34;peripheral ID-2&#34;, &#34;data size&#34;, and &#34;data&#34;, even though the controller 3a (or 3b) as the peripheral device adopts different communication modes or different device types. Also the foregoing plug pin configuration provides the communication of &#34;peripheral IDs&#34; and &#34;data&#34; in a proper state, although types and/or communication modes of peripheral devices are different. 
     The operation of the apparatus 2 functionally including the system for identifying communication modes of peripheral devices will now be explained with reference to FIGS. 3 to 14 and Table 2 to 6. 
     As shown in FIG. 7, after being activated, the sub CPU 25 first outputs the control signals TH=&#34;1&#34; and TR=&#34;1&#34; (refer to Step S101 in FIG. 7). The CPU core 31 of the sub CPU 25 reads logical values of the data signals R, L, D and U produced on pins 7, 8, 2 and 3 by each of the peripheral devices and stores the read logical values into a predetermined memory area of the RAM 33 (Step S102). The CPU core 31 again outputs the control signals TH=&#34;0&#34; and TR=&#34;1&#34; (Step S103). In response to this, the CPU core 31 again reads logical values of the data signal R, L, D and U produced by the peripheral devices and stores them into a predetermined memory area of the RAM 33 (Step S104: see the intervals T 10  in FIG. 12 and T 20  in FIG. 13). 
     The CPU core 31 then calculates the &#34;peripheral ID-1&#34; (Step S105). The &#34;peripheral ID-1&#34; can be calculated using the following formula. ##EQU1## where h represents suffix for hexadecimal number. Using the calculated results of [ID-1], the CPU core 31 identifies the types of peripheral devices (Steps S106 to S110). The following table 2 shows a relation between the types of peripheral devices and the calculated results of [ID-1]. 
     
         ______________________________________                                    
Peripheral Device   ID-1                                                  
______________________________________                                    
                    F                                                     
                    E                                                     
3/6 Button          D                                                     
                    C                                                     
Control PAD         B                                                     
                    A                                                     
                    9                                                     
                    8                                                     
Adaptor             7                                                     
                    6                                                     
Controller (Peripheral #1)                                                
                    5                                                     
                    4                                                     
Mouse               3                                                     
                    2                                                     
                    1                                                     
Modem               0                                                     
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     In detail, the CPU core 31 first determines whether or not the calculated result [ID-1] is Bh, for instance. When it is determined that the calculated result [ID-1] be Bh (YES at Step S106), it is decided that the peripheral device be a control PAD packed and supplied together with the game system as a standard peripheral device. According to the present embodiment, the hexadecimal value Bh or the binary number &#34;1011&#34; of [ID-1] is assigned to the standard control pad. The values of [ID-1] other than Bh may be assigned to other optional peripheral devices as shown in Table 2. Thus the CPU core 31 which has determined the value Bh of [ID-1] moves to the processing of a control PAD access subroutine (Step S111). When the calculated result [ID-1] is not Bh (NO at Step S106), the CPU core 31 then determines whether or not the calculated result [ID-1] is 5h, for example (Step S107). 
     When it is determined that the calculated result [ID-1] be 5h (YES at Step S107, also refer to Table 2), a controller access subroutine is processed (Step S112), which is shown in detail in FIG. 8. 
     When the calculated result [ID-1] is not 5h (NO at Step S107), the sub CPU 25 proceeds to the determination whether the calculated result [ID-1] is 7h, for example (Step S108). When the determination is YES at Step S108 (i.e., the calculated result [ID-1]=7h), the sub CPU 25 then performs an adapter access subroutine (Step S113). 
     When it is determined that the calculated result [ID-1] be not 7h (NO at Step S108), the sub CPU 25 continues to determine if the above calculated result [ID-1] is 3h or not, for example (Step S109). Where the calculated result [ID-1] is determined to be 3h (YES at Step S109, Table 2), a mouse access subroutine is processed (Step S114). 
     When the above result [ID-1] is not 3h (NO at Step S109), it is then determined whether or not the calculated result [ID-1] be Dh (Step S110). Where this determination shows that the calculated result [ID-1] is Dh (YES at Step S110, Table 2), a 3/6 button access subroutine is then performed (Step S115). When the determination is NO at Step 110, the processing is continued to Step S116, where a decision that the peripheral device is not connected is made for the calculated result [ID-1]=Fh and a decision to be unknown is made for values of the [ID-1] other than the above exemplified results (refer to Table 2). 
     As a representative, the control PAD access subroutine will be described. In this subroutine, an access to the control PAD is carried out under the TH/TR communication mode automatically designated. In the present embodiment, the TH/TR selection communication mode is preferably employed in the standard control pad supplied together with the game apparatus 2. In other words, the game apparatus is constructed so that, when the calculated result of [ID-1] is determined as Bh, it automatically determines that the peripheral device connected is a standard control pad with a TH/TR selection communication mode. 
     In this communication mode, a control signal of 2-bit data consisting of combined two signals of the peripheral selection signal TH and data request signal TR is transmitted from the game apparatus to the control pad (peripheral controller). Then, in response to the 2-bit data of the combined control signal of TH and TR, the control pad transmits four patterns of combined 4-bit data R, L, D and U in a sequence of antecedent first to fourth rows, for example, as shown in Table 3. 
     Table 3 is a truth table of values required for a TH/TR selection communication mode in which the &#34;RIGHT&#34;, &#34;LEFT&#34;, &#34;DOWN&#34;, &#34;UP&#34;, &#34;START&#34;, and &#34;TRG-A, B, C, X, Y, Z, L, R&#34; are names of the key switches of the control pad or signal names generated by the key switches, respectively. 
     In the first step of the sequence, as shown in Table 3, the control pad outputs a four bit data of &#34;TRG-L&#34;, &#34;1&#34;, &#34;0&#34; and &#34;0&#34; via terminal pins R, L, D and U to the game apparatus 2, which data corresponds to the first two lines of the formula of [ID-1] as explained hereinabove. With this data the game apparatus calculates the upper 2-bit of [ID-1]. The first line of the formula makes &#34;1&#34; irrelevant to the value of &#34;TRG-L&#34; when the values (data R=&#34;TRG-L&#34;) and (data L=&#34;1&#34;) in TH=&#34;1&#34; are applied to the formula. The second line of the formula yields &#34;0&#34; when the values are (data D=&#34;0&#34;) and (data U=&#34;0&#34;) in TH=&#34;1&#34;. 
     In the second step of the sequence, similarly, the control pad outputs a four bit data of (R=&#34;RIGHT&#34; in TH=&#34;0&#34;) , (L=&#34;LEFT&#34; in TH=&#34;0&#34;), (D=&#34;DOWN&#34; in TH=&#34;0&#34;) and (U=&#34;UP&#34; in TH=&#34;0&#34;) via terminal pins R, L, D and U to the game apparatus 2, which data correspond to the second two lines of the formula of [ID-1]. With this data the game apparatus calculates the lower 2-bit of [ID-1]. Both of the third and fourth lines of the formula yield &#34;1&#34; because there never occurs a case where both keys of &#34;RIGHT&#34; and &#34;LEFT&#34; generate ON simultaneously and a case where both keys of &#34;DOWN&#34; and &#34;UP&#34; generate ON simultaneously. 
     Thus a calculation result of [ID-1]=binary 1011 or hexadecimal Bh is obtained and based on the calculation result the game apparatus 2 determines that the connected peripheral device is a standard pad with a TH/TR selection communication mode. 
     The game apparatus 2 receives signal data indicative of switches TRG-A, B, C, X, Y, Z, L and R in the third and fourth rows of the bit sequences as shown in Table 3 via terminal pins R, L, D and U in response to the combined 2-bit control signal of TH and TR. Thus during one sequence cycle of 1st to 4th steps the game apparatus collects data necessary for determining the type of a peripheral device and the mode of communication as well as data indicative of all key switches. 
     Data of the peripheral acknowledgment signal TL are ignored in the TH/TR selection communication mode since a required voltage level at terminal pin TL (no. 6 pin) is always &#34;1&#34; in all four steps of the sequence as shown in Table 3, which is equivalent to a status that the voltage value of the power source Vcc is always applied to the pin. 
     
                                           TABLE 3                                 
__________________________________________________________________________
DATA                                                                      
    TH   TR   TL  R    L    D    U                                        
__________________________________________________________________________
    bit6 bit5 bit4                                                        
                  bit3 bit2 bit1 bit0                                     
    INPUT                                                                 
         INPUT                                                            
              OUT-                                                        
                  OUT- OUT- OUT- OUT-                                     
              PUT PUT  PUT  PUT  PUT                                      
1st 1    1    1   TRG- 1    0    0                                        
                  L                                                       
2nd 0    1    1   RIGHT                                                   
                       LEFT DOWN UP                                       
3rd 1    0    1   STA- TRG- TRG- TRG-                                     
                  RT   A    C    B                                        
4th 0    0    1   TRG- TRG- TRG- TRG-                                     
                  R    X    Y    Z                                        
__________________________________________________________________________
 
    
     As another representative, the foregoing controller access subroutine shown in FIG. 8 will now be described also with reference to Table 4 which represents the bit patterns of data R, L, D and U corresponding to typical communication modes used by controllers as peripheral devices. 
     
                       TABLE 4                                                     
______________________________________                                    
Communication                                                             
            TH=1 TR=1     TH=0 TR=1                                       
mode        R     L      D   U    R    L    D   U                         
______________________________________                                    
Three-wire  0     0      0   1    0    0    0   1                         
handshake                                                                 
Clocked serial                                                            
            0     0      1   0    0    0    1   0                         
Clocked parallel                                                          
            0     0      1   1    0    0    1   1                         
______________________________________                                    
 
    
     In this access subroutine, the CPU core 31 of the sub CPU 25 first determines communication modes by a series of Steps S201 to S203 on the basis of the logical values of the data D and U acquired before. When both the data D is &#34;0&#34; and U is &#34;1&#34; (YES at Step S201), the peripheral device is identified as in the three-wire handshake mode (refer to Table 4), and the processing by the sub CPU 25 proceeds to a three-wire handshake-type access subroutine (Step S204). 
     When the data D and U are not &#34;0&#34; and &#34;1&#34;, respectively (NO at Step S201), the CPU core 31 then determines whether both of the data D and U are &#34;1&#34; and &#34;0&#34;, respectively, for example (Step S202). When the determination is YES at Step S202 (i.e., D=&#34;1&#34; and U=&#34;0&#34;, refer to Table 3), the CPU core 31 continues to an access subroutine of the clocked serial communication mode (Step S205). 
     Furthermore, where the determination is NO at Step S202 (i.e., data D is not &#34;1&#34; and data U is not &#34;0&#34;), the CPU core 31 determines whether or not the data D is &#34;1&#34; and data U is &#34;1&#34; (Step S203). When being determined that D=&#34;1&#34; and U=&#34;1&#34; (YES at Step S203, refer to Table 4), the CPU core 31 performs an access subroutine of the clocked parallel communication mode (Step S206). 
     When the CPU core cannot find the positive answers at any of the above determination processes at Steps S201 to S203 (NO at Steps S201 to S203), it is then determined that no peripheral device is connected to the apparatus 2 (Step S207), and this subroutine is ended. 
     Each access subroutine shown at the above Steps S204 to S206 will now be explained in detail. 
     First, the access subroutine of the three-wire handshake communication mode, which is shown in FIG. 9, will be explained using the timing chart of each signal shown in FIG. 12 in which the reference t shows time. 
     During the interval T 11  in FIG. 12, the CPU core 31 reads the &#34;peripheral ID-2&#34; (Step S301 in FIG. 9). In other words, the data ID-2 3 , ID-2 2 , ID-2 1  and ID-2 0  of R, L, D and U are taken in by the CPU core 31 during the interval T 11  and it is determined whether each of those data ID-2 3  to ID-2 0  corresponds to any of &#34;0h&#34; to &#34;Fh&#34; (refer to IDs shown in Table 5). 
     
                       TABLE 5                                                     
______________________________________                                    
Peripheral Device                                                         
              ID-2       Remarks                                          
______________________________________                                    
Digital device                                                            
              0          Control PAD,                                     
                         joystick etc.                                    
Analog device 1          Analog joystick etc.                             
Pointing device                                                           
              2          Mouse, tablet etc.                               
Keyboard      3          Keyboard etc.                                    
Multitap      4          Multitap etc.                                    
              5                                                           
              6                                                           
              7                                                           
              8                                                           
              9                                                           
              A                                                           
              B                                                           
              C                                                           
              D                                                           
Peripheral #2 E          ID for conversion                                
              F          for non-connection                               
______________________________________                                    
 
    
     In addition to the reading, the CPU core 31 looks up Table 5 for each value of the read peripheral ID-2. For example, the CPU core 31 determines that the peripheral device be a digital device for &#34;peripheral ID-2&#34;=0h, an analog device for &#34;peripheral ID-2&#34;=1h, a pointing device for &#34;peripheral ID-2&#34;=2h, a key board for &#34;peripheral ID-2&#34;=3h, and so on. 
     After such determination, the CPU core 31 reads the data size during the next interval T 12  (Step S302). Namely, as shown in FIG. 12, data DSIZE0 to DSIZE3 of R, L, D and U are taken in for deciding the data size. 
     The CPU core 31 then reads the data during the following intervals starting from interval T 13  in FIG. 12 (Step S303). It is then determined whether the amount of the read data reaches the data size (Step S304). If the determination is NO, the processing returns to Step S303 to read the data again. However, the determination is YES at Step S304 (i.e., the data amount that has been read by then reaches the determined data size), this subroutine is ended. 
     Next, the access subroutine of the clocked parallel communication mode identified at Step S205 in FIG. 8 will now be explained using FIGS. 10 and 13. 
     FIG. 13 shows the timing chart of the clocked parallel communication mode, which is almost the same as that shown in FIG. 12. Only one difference is that both of the signals TR and TL always change at the same timing. 
     First, the CPU core 31 reads the &#34;peripheral ID-2&#34; during the interval T 21  in FIG. 13 (Step S401 in FIG. 10). 
     In detail, the data ID-2 3 , ID-2 2 , ID-2 1  and ID-2 0  of R, L, D and U are taken in by the CPU core 31 during the interval T 21  and it is determined whether each of the data ID-2 3  to ID-2 0  corresponds to any of &#34;0h&#34; to &#34;Fh&#34; (refer to IDs shown in Table 5). The CPU core 31 looks up Table 5 for each value of the read peripheral ID-2. For example, the CPU core 31 determines that the peripheral device is a digital device for &#34;peripheral ID-2&#34;=0h, an analog device for &#34;peripheral ID-2&#34;=1h, a pointing device for &#34;peripheral ID-2&#34;=2h, a key board for &#34;peripheral ID-2&#34;=3h, and so on. 
     After this, during the next interval T 22 , the CPU core 31 reads the data size by receiving data DSIZE0 to DSIZE3 of R, L, D, U as shown in FIG. 13 (Step S402 in FIG. 10). 
     The CPU core 31 then reads the data during the following intervals starting from interval T 23  in FIG. 13 (Step S403). It is then determined whether the amount of the read data reaches the data size (Step S404). If the determination is NO, the processing returns to Step S403 to read the data again. However, if the determination is YES at Step S404 (i.e., the data amount that has been read by then reaches the determined data size), this subroutine is ended. 
     Next, the access subroutine of the docked serial communication mode will be explained according to FIGS. 11 and 14 and Table 6. FIG. 14 exemplifies signal changes for the clocked serial mode, where the logical values of only the signals TH, TR and U are expressed along the elapsed time t. 
     This communication mode enables to obtain the data U only supplied from a peripheral device when the peripheral selection signal TH is &#34;0&#34; and at the same time, the data request signal TR is repeatedly &#34;1&#34; and &#34;0&#34;, both the signals TH and TR being given to the peripheral device from the CPU core 31. The obtained data are exemplified in Table 6. 
     
                                           TABLE 6                                 
__________________________________________________________________________
TH  TR  TL  R   L   D   U                                                 
(input)                                                                   
    (input)                                                               
        (GND)                                                             
            (GND)                                                         
                (GND)                                                     
                    (Vcc)                                                 
                        (DATA)                                            
                             Remarks                                      
__________________________________________________________________________
1   1   0   0   0   1   0    ID-1(1st)                                    
0   1   0   0   0   1   0    ID-2(2nd)                                    
0   ↓                                                              
      ↑                                                             
        0   0   0   1   SMD.sub.3                                         
0   ↓                                                              
      ↑                                                             
        0   0   0   1   SMD.sub.2                                         
0   ↓                                                              
      ↑                                                             
        0   0   0   1   SMD.sub.1                                         
0   ↓                                                              
      ↑                                                             
        0   0   0   1   SMD.sub.0                                         
0   ↓                                                              
      ↑                                                             
        0   0   0   1   ID-2.sub.3                                        
0   ↓                                                              
      ↑                                                             
        0   0   0   1   ID-2.sub.2                                        
0   ↓                                                              
      ↑                                                             
        0   0   0   1   ID-2.sub.1                                        
0   ↓                                                              
      ↑                                                             
        0   0   0   1   ID-2.sub.0                                        
0   ↓                                                              
      ↑                                                             
        0   0   0   1   DSIZE.sub.3                                       
0   ↓                                                              
      ↑                                                             
        0   0   0   1   DSIZE.sub.2                                       
0   ↓                                                              
      ↑                                                             
        0   0   0   1   DSIZE.sub.1                                       
0   ↓                                                              
      ↑                                                             
        0   0   0   1   DSIZE.sub.0                                       
0   ↓                                                              
      ↑                                                             
        0   0   0   1   DATA.sub.7                                        
.   . . .   .   .   .   .                                                 
.   . . .   .   .   .   .                                                 
.   . . .   .   .   .   .                                                 
.   . . .   .   .   .   .                                                 
.   . . .   .   .   .   .                                                 
.   . . .   .   .   .   .                                                 
0   ↓                                                              
      ↑                                                             
        0   0   0   1   DATA.sub.0                                        
0   ↓                                                              
      ↑                                                             
        0   0   0   1   CCB                                               
0   ↓                                                              
      ↑                                                             
        0   0   0   1   1                                                 
0   ↓                                                              
      ↑                                                             
        0   0   0   1   1                                                 
0   ↓                                                              
      ↑                                                             
        0   0   0   1   0                                                 
1   1   0   0   0   1   0    End M5lD-1st                                 
__________________________________________________________________________
 
    
     As shown in Table 6, only when the peripheral selection signal TH is &#34;0&#34;, the data request signal TR is repeated at cycles of &#34;1&#34; and &#34;0&#34; (expressed by upward and downward arrows in Table 6), the signal TL and data R and L are all &#34;0&#34;, and the data D is &#34;1&#34;, various data U including SMD 3  to SMD 0 , ID-2 3  to ID-2 0 , DSIZE 3  to DSIZE 0 , and DATA 7  to DATA 0  are provided in sequence from the line U through the pin 3. Those data are read by the CPU core 31. Among them, the bit pattern of the data ID-2 3  to ID-2 0  are referred to the table 5 to decide the type of a connected peripheral device (Step S501 in FIG. 11). 
     The CPU core 31 reads the data size expressed by DSIZE 0  to DSIZE 3  (Step S502), so that the data size can be determined. 
     The data are then received by the CPU core 31 during predetermined intervals in a time sequence shown in FIG. 14 (Step S503). The amount of the read data are compared to the determined data size to determine whether the amount reaches the data size (Step S504). If the determination is NO, the processing returns to Step S503 to repeat the foregoing data read. The determination of YES at Step S504 allows to end this subroutine. 
     As explained above, the CPU core 31 exchanges signals with peripheral devices such that data &#34;DATA&#34; are inputted after information of &#34;peripheral ID-1&#34;, &#34;peripheral ID-2&#34; and data size &#34;DSIZE&#34;. 
     When the data are inputted into the CPU core 31, the CPU core 31 exchanges data with the main CPU 21 through the register table 34. 
     In the above embodiment, although the sub CPU 25 controls the peripheral devices, the main CPU 21 can also perform the above-described processing instead of the sub CPU 25, if the main CPU 21 is directly connected to the peripheral devices. 
     Further, another Identifying method of a communication mode can be used in the present invention. As is described above, the control signals TR and TL are equal in logical values (TR=TL) in the docked parallel communication mode and the logical values on only specified pins (D, U, R, L) are changed in specific manners. In case of the three-wire handshake mode, the control signals TR and TL are changed differently. This enables to calculate identification data of peripheral devices based on the pin configurations of the connectors and decide communication modes using the identification data. 
     Although the present invention has been described with reference to particular embodiments, the description is only an example of the invention&#39;s application and should not be taken as a limitation. In particular, the connector, the communication mode identifying system, and the peripheral device controlling system of the present invention is not limited to use with the game apparatus and can also be applied to any other system which use a processing unit and at least one peripheral device thereof.