Patent Publication Number: US-2023135799-A1

Title: Light-emitting device

Description:
TECHNICAL FIELD 
     The application relates to a structure of a light-emitting device, and more particularly, to a light-emitting device emitting an ultraviolet light, including a first semiconductor layer and a plurality of semiconductor pillars on the first semiconductor layer. 
    
    
     REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of U.S. Pat. Application Serial No. 16/726,576, filed on Dec. 24, 2019, now pending, which is a continuation application of U.S. Pat. Application Serial No. 16/035,299, filed on Jul. 13, 2018, now issued, which claims the right of priority based on TW Application Serial No. 106123445, filed on Jul. 13, 2017, the right of priority based on TW Application Serial No. 107123088, filed on Jul. 4, 2018, and the content of which are hereby incorporated by references in its entirety. 
    
    
     DESCRIPTION OF BACKGROUND ART 
     Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting device, which has the advantages of low power consumption, low heat generation, long working lifetime, shockproof, small volume, fast reaction speed and good photoelectric property, such as stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicators, and optoelectronic products. 
     SUMMARY OF THE APPLICATION 
     A light-emitting device includes a substrate; an aluminum nitride (AlN) buffer layer formed on the substrate; a first semiconductor layer including AlxGa(1-x)N formed on the aluminum nitride (AlN) buffer layer, wherein x&gt;0; a semiconductor pillar formed on the first semiconductor layer, including a second semiconductor layer and an active layer, wherein the semiconductor pillar includes an outmost periphery; a first contact layer formed on the first semiconductor layer, wherein the first contact layer includes a first contact portion and a first extending portion, wherein the first extending portion continuously surrounds an entirety of the outmost periphery of the semiconductor pillar and the first contact portion in a top view of the light-emitting device; a second contact layer formed on the second semiconductor layer of the semiconductor pillar; a first insulating layer formed on the first contact layer and the second contact layer, wherein the first insulating layer includes one or multiple first openings exposing the first contact layer and one or multiple second openings exposing the second contact layer; a first electrode contact layer connected to the first contact portion through the one or multiple first openings of the first insulating layer, wherein the first electrode contact layer covers all of the first contact layer; a second electrode contact layer connected to the second contact layer through the one or multiple second openings of the first insulating layer; a second insulating layer formed on the first electrode contact layer and the second electrode contact layer, wherein the second insulating layer includes one or multiple first openings exposing the first electrode contact layer and one or multiple second openings exposing the second electrode contact layer; a first electrode formed on the second insulating layer, wherein the first electrode covers the one or multiple first openings of the second insulating layer and is in contact with the first electrode contact layer to electrically connect the first semiconductor layer by the first contact portion; and a second electrode formed on the second insulating layer, wherein the second electrode covers the one or multiple second openings of the second insulating layer and is in contact with the second electrode contact layer to electrically connect the second semiconductor layer by the second contact layer. 
     A light-emitting device includes a substrate; an aluminum nitride (AlN) buffer layer formed on the substrate; a first semiconductor layer including AlxGa(1-x)N formed on the aluminum nitride (AlN) buffer layer, wherein x&gt;0; a semiconductor pillar formed on the first semiconductor layer, including a second semiconductor layer and an active layer, wherein the semiconductor pillar includes an outmost periphery; a first contact layer formed on the first semiconductor layer, wherein the first contact layer includes a first contact portion and a first extending portion, wherein the first extending portion continuously surrounds an entirety of the outmost periphery of the semiconductor pillar and the first contact portion in a top view of the light-emitting device; a second contact layer formed on the second semiconductor layer of the semiconductor pillar; a first electrode contact layer connected to the first contact portion, wherein the first electrode contact layer includes an outmost periphery; a second electrode contact layer connected to the second contact layer, wherein the second electrode contact layer surrounds an entirety of the outmost periphery of the first electrode contact layer in the top view of the light-emitting device; an insulating layer formed on the first electrode contact layer and the second electrode contact layer, wherein the insulating layer includes one or multiple first openings formed on the first electrode contact layer and one or multiple second openings formed on the second electrode contact layer; a first electrode formed on the insulating layer, wherein the first electrode covers the one or multiple first openings of the insulating layer and is electrically connected to the first electrode contact layer and the first semiconductor layer; and a second electrode formed on the second insulating layer, wherein the second electrode covers the one or multiple second openings of the insulating layer and is electrically connected to the second electrode contact layer and the second semiconductor layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates a top view of a light-emitting device  1  in accordance with an embodiment of the present application; 
         FIG.  2    illustrates a cross-sectional view of the light-emitting device  1  in accordance with an embodiment of the present application; 
         FIG.  3 A  illustrates a partial cross-sectional view of a light-emitting device  2 A in accordance with an embodiment of the present application; 
         FIG.  3 B  illustrates a partial top view of the light-emitting device  2 A in accordance with an embodiment of the present application; 
         FIG.  4 A  illustrates a partial cross-sectional view of a light-emitting device  2 B in accordance with an embodiment of the present application; 
         FIG.  4 B  illustrates a partial top view of the light-emitting device  2 B in accordance with an embodiment of the present application; 
         FIG.  5    illustrates a schematic view of a light-emitting apparatus  3  in accordance with an embodiment of the present application; and 
         FIG.  6    illustrates a structure diagram of a light-emitting apparatus  4  in accordance with an embodiment of the present application. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The embodiment of the application is illustrated in detail, and is plotted in the drawings. The same or the similar part is illustrated in the drawings and the specification with the same number. 
       FIG.  1    illustrates a top view of a light-emitting device  1  in accordance with an embodiment of the present application.  FIG.  2    illustrates a cross-sectional view of  FIG.  1    along line A-A′. 
     As shown in  FIG.  1    and  FIG.  2   , a light-emitting device  1  includes a substrate  11 ; and a semiconductor stack formed on the substrate  11 , wherein the semiconductor stack includes a first semiconductor layer  111 , and a plurality of semiconductor pillars  12  separated from each other and formed on the first semiconductor layer  111 . The plurality of semiconductor pillars  12  each includes a second semiconductor layer  122  and an active layer  123 . In an embodiment of the present application, the semiconductor pillar  12  includes a part of the first semiconductor layer  111 , and the active layer  123  is formed between the first semiconductor layer  111  and the second semiconductor layer  122 . 
     In an embodiment of the present application, the substrate  11  can be a growth substrate, including gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or sapphire (Al 2 O 3 ) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer for growing gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). 
     In an embodiment of the present application, a plurality of semiconductor layers including optical characteristics and consisting of semiconductor materials is formed on the substrate  11  by organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating, wherein physical vapor deposition (PVD) including sputtering or evaporation. The plurality of semiconductor layers is patterned by lithography and etching to remove portions of the semiconductor layers and to form the semiconductor stack including the first semiconductor layer  111 , and the plurality of semiconductor pillars  12  consisting of the active layer  123  and the second semiconductor layer  122 . The first semiconductor layer  111  and the second semiconductor layer  122  can be cladding layers, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer  111  is an n-type semiconductor and the second semiconductor layer  122  is a p-type semiconductor. The active layer  123  is formed between the first semiconductor layer  111  and the second semiconductor layer  122 . The electrons and holes combine in the active layer  123  under a current driving to convert electric energy into light energy and then light is emitted from the active layer  123 . The wavelength of the light emitted from the light-emitting device  1  is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack. The material of the semiconductor stack includes a group III-V semiconductor material, such as Al x In y Ga (1-   x-y) N or Al x In y Ga (1-x-y) P, wherein 0≤x, y≤1; (x+y)≤1. According to the material of the active layer  123 , when the material of the semiconductor stack is AlInGaP series material, red light having a wavelength between 610 nm and 650 nm or yellow light having a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack is InGaN series material, blue or deep blue light having a wavelength between 400 nm and 490 nm or green light having a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack is AlGaN series material, UV light having a wavelength between 400 nm and 250 nm can be emitted. The active layer  123  can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure, MQW). The material of the active layer  123  can be i-type, p-type, or n-type semiconductor. 
     In an embodiment of the present application, a buffer layer (not shown) is formed between the semiconductor stack and the substrate  11  to improve the epitaxial quality of the semiconductor stack. In an embodiment, an aluminum nitride (AlN) layer can be used as the buffer layer. In an embodiment, the method for forming aluminum nitride (AlN) is PVD, and the target is made of aluminum nitride. In another embodiment, a target made of aluminum which reacts in a nitrogen source environment with a PVD method is used to form aluminum nitride. 
     In an embodiment of the present application, the substrate  11  includes a sapphire (Al 2 O 3 ) substrate, and the first semiconductor layer  111  includes an aluminum gallium nitride (AlGaN) layer. In order to reduce the epitaxial defects caused by the lattice difference between the AlGaN layer and the sapphire substrate, the AlN layer is formed as a buffer layer between the AlGaN layer and the sapphire substrate, wherein the AlN buffer layer includes a thickness greater than 300 nm, preferably greater than 1000 nm, and even greater than 2500 nm to fill the epitaxial defects. The aluminum nitride (AlN) buffer layer includes carbon (C), hydrogen (H), and/or oxygen (O) including a doping concentration lower than 2E+17. The aluminum (Al) composition percentage of the aluminum nitride (AlN) buffer layer is greater than that of aluminum gallium nitride (AlGaN) of the first semiconductor layer  111 . 
     As shown in the top view of  FIG.  1    and the cross-sectional view of  FIG.  2    taken along line A-A′ of  FIG.  1   , after the plurality of semiconductor layers is formed on the substrate  11 , the plurality of semiconductor layers is patterned by lithography and etching to remove portions of the semiconductor layers and to form the semiconductor stack including the first semiconductor layer  111  and the plurality of semiconductor pillars  12  separated from each other, wherein the plurality of semiconductor pillars  12  each includes the second semiconductor layer  122  and the active layer  123 . 
     In an embodiment of the present application, the semiconductor pillars  12  are separated from each other to expose a surface S 1  of the first semiconductor layer  111 . The substrate  11  includes a first sidewall  11   s , the first semiconductor layer  111  includes a second sidewall  111   s , and the plurality of semiconductor pillars  12  each includes a third sidewall  12   s . As shown in  FIG.  2   , the first sidewall  11   s  of the substrate  11  is aligned to the second sidewall  111   s  of the first semiconductor layer  111 . An inclined angle or a right angle is between the third sidewall  12   s  of the semiconductor pillar  12  and the surface S 1  of the first semiconductor layer  111 . 
     In an embodiment of the present application, the inclined angle between the third sidewall  12   s  of the semiconductor pillar  12  and the surface S 1  of the first semiconductor layer  111  includes an angle between 10 degrees and 80 degrees, preferably less than 60 degrees, and more preferably less than 40 degrees. 
     In an embodiment of the present application, the first sidewall  11   s  of the substrate  11  is separated from the second sidewall  111   s  of the first semiconductor layer  111  by a distance to expose a surface S 2  of the substrate  11 . An obtuse angle or a right angle is between the second sidewall  111   s  of the first semiconductor layer  111  and the surface S 2  of the substrate  11 . 
     In an embodiment of the present application, an inclined angle between the second sidewall  111   s  of the first semiconductor layer  111  and the surface S 2  of the substrate  11  includes an angle between 10 degrees and 80 degrees, preferably less than 60 degrees, and more preferably less than 40 degrees. A height between the surface S 1  of the first semiconductor layer  111  and the surface S 2  of the substrate  11  is greater than 4000 Å, preferably greater than 6000 Å, and more preferably greater than 8000 Å. 
     In an embodiment of the present application, the surface S 2  of the substrate  11  is a flat surface, wherein the flat surface includes a roughness (Root mean square roughness, Rq) less than 8 nm, preferably less than 5 nm, and more preferably less than 2 nm. 
     In an embodiment of the present application, the surface S 2  of the substrate  11  includes a patterned surface (not shown), wherein the patterned surface includes a plurality of recesses extending from the surface S 2  of the substrate  11  toward the interior of the substrate  11  or a plurality of protrusions extending from the surface S 2  of the substrate  11  toward the surface S 1  of the first semiconductor layer  111 . From the top view of the light-emitting device  1 , the plurality of recesses or the plurality of protrusions each includes a circle, an ellipse, a rectangle, a polygon, or any other shape. From the top view of the light-emitting device  1 , the plurality of recesses or the plurality of protrusions each includes a bottom portion that is flush with the surface S 2  of the substrate  11 , and a top portion that is opposite to the bottom portion. The top portion may be a flat surface or a point. The depth or the height between the top portion and the bottom portion is between 0.1 µm and 2 µm, preferably between 0.2 µm and 0.9 µm, and more preferably between 0.5 µm and 0.7 µm. The bottom portion includes a width or a diameter between 0.05 µm and 1 µm, preferably between 0.2 µm and 0.8 µm, and more preferably between 0.3 µm and 0.5 µm. 
     In an embodiment of the present application, viewing from the top view of the light-emitting device  1  shown in  FIG.  1   , the semiconductor pillars  12  each includes a circle, an ellipse, a rectangle, a polygon, or any other shape. 
     In an embodiment of the present application, reducing the diameter or the width of the semiconductor pillar  12  can reduce the forward voltage(Vf) of the light-emitting device  1 . From the top view of the light-emitting device  1 , the semiconductor pillar  12  includes a diameter or a width greater than 4 µm and/or less than 80 µm, preferably less than 50 µm, and more preferably less than 20 µm. 
     In an embodiment of the present application, the semiconductor pillars  12  are arranged in a plurality of columns, and the semiconductor pillars  12  arranged in any two adjacent columns or every two adjacent columns can be aligned with each other or staggered. 
     In an embodiment of the present application, the semiconductor pillars  12  can be arranged in a first column and a second column. A first shortest distance is between two adjacent semiconductor pillars  12  in the same column, and a second shortest distance is between one of the semiconductor pillars  12  in the first column and another adjacent one of the semiconductor pillars  12  in the second column, wherein the first shortest distance is greater than or less than the second shortest distance. When an external current is injected into the light-emitting device  1 , the dispersed disposition of the plurality of semiconductor columns  12  uniforms the light field distribution of the light-emitting device  1  and reduces the forward voltage of the light-emitting device  1 . 
     In an embodiment of the present application, the semiconductor pillars  12  can be arranged in a first column, a second column and a third column. A first shortest distance is between one of the semiconductor pillars  12  in the first column and another one of the semiconductor pillars  12  in the second column, and a second shortest distance is between one of the semiconductor pillars  12  in the second column and another one of the semiconductor pillars  12  in the third column, wherein the first shortest distance is less than the second shortest distance. When an external current is injected into the light-emitting device  1 , the dispersed disposition of the plurality of semiconductor columns  12  uniforms the light field distribution of the light-emitting device  1  and reduces the forward voltage of the light-emitting device  1 . 
     A first contact layer  131  is formed on the surface S 1  of the first semiconductor layer  111  by physical vapor deposition or chemical vapor deposition. The material of the first contact layer  131  includes metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), rhodium (Rh), or an alloy of the above materials. 
     In an embodiment of the present application, the light emitted from the light-emitting device  1  includes a wavelength longer than 370 nm, and the material of the first contact layer  131  includes a metal having high reflectivity, such as silver (Ag), aluminum (Al), platinum (Pt) or rhodium (Rh). In order to increase the reflectivity of the first contact layer  131 , the metal layer of silver (Ag), aluminum (Al), platinum (Pt), or rhodium (Rh) includes a thickness greater than 400 angstroms (Å), preferably greater than 800 angstroms (Å), and more preferably greater than 1200 angstroms (Å). 
     In an embodiment of the present application, the light emitted from the light-emitting device  1  includes a wavelength shorter than 370 nm, and the material of the first contact layer  131  does not include silver (Ag). 
     In an embodiment of the present application, one side of the first contact layer  131  contacting with the surface S 1  of the first semiconductor layer  111  includes chromium (Cr) or titanium (Ti) to increase the bonding strength between the first contact layer  131  and the first semiconductor layer  111 . In order to reduce the light loss, the thickness of chromium (Cr) or titanium (Ti) layer is lower than 1000 angstroms (Å), preferably lower than 600 angstroms (Å), and more preferably lower than 400 angstroms (Å).And, in order to maintain sufficient bonding strength, chromium (Cr) and/or titanium (Ti) layers include a thickness greater than 10 angstroms (Å), preferably greater than 50 angstroms (Å), and more preferably greater than100 angstroms (Å). 
     In an embodiment of the present application, the first semiconductor layer  111  includes Al x Ga (1-x) N, where 0.3&lt;x&lt;0.8, preferably 0.35&lt;x&lt;0.7, and more preferably 0.4&lt;x&lt;0.6. In order to form an ohmic contact between the first contact layer  131  and the surface S 1  of the first semiconductor layer  111 , and maintain a sufficient bonding strength therebetween, the first contact layer  131  includes titanium (Ti) and aluminum (Al), wherein a ratio of a titanium (Ti) layer to an aluminum (Al) layer is between 0.1 and 0.2. 
     In an embodiment of the present application, the first contact layer  131  includes a first contact portion P 1  and a first extending portion E 1 . The first contact portion P 1  includes a projected area on the first semiconductor layer  111  that is larger than a projected area of one of the plurality of semiconductor pillars  12  on the first semiconductor layer  111 , wherein the projected area refers to a surface area along a normal direction perpendicular to the surface S 2  of the substrate  11 . As shown in  FIG.  1   , the first extending portion E 1  extends from the first contact portion P 1  and surrounds the plurality of semiconductor pillars  12 . 
     In an embodiment of the present application, the first contact layer  131  includes a plurality of first contact portions P 1  and a plurality of first extending portions E 1 , wherein the plurality of first extending portions E 1  is extended from the plurality of first contact portions P 1  and are connected to each other, and the plurality of first contact portions P 1  is electrically connected by the plurality of first extending portions E 1 . 
     As shown in  FIG.  2   , in an embodiment of the present application, the first contact portion P 1  of the first contact layer  131  includes a width larger than a width of the first extending portion E 1 . 
     A second contact layer  132  is formed on the second semiconductor layer  122  of the semiconductor pillar  12  by physical vapor deposition or chemical vapor deposition. The material of the second contact layer  132  includes metal, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), rhodium (Rh), or an alloy of the above materials. 
     In an embodiment of the present application, the light emitted from the light-emitting device  1  includes a wavelength longer than 370 nm, and the material of the second contact layer  132  includes a metal having high reflectivity, such as silver (Ag), aluminum (Al), platinum (Pt) or rhodium (Rh). In order to increase the reflectivity of the second contact layer  132 , the metal layer of silver (Ag), aluminum (Al), platinum (Pt), or rhodium (Rh) includes a thickness greater than 400 angstroms (Å), preferably greater than 800 angstroms (Å), and more preferably greater than 1200 angstroms (Å). 
     In an embodiment of the present application, the light emitted from the light-emitting device  1  includes a wavelength shorter than 370 nm, and the material of the second contact layer  132  does not include silver (Ag). 
     In an embodiment of the present application, a plurality of second contact layers  132  are respectively formed on the second semiconductor layer  122  of the plurality of semiconductor pillars  12 , and the plurality of second contact layers  132  are separated from each other. 
     In an embodiment of the present application, the second semiconductor layer  122  includes GaN, AlGaN or BN, and the second semiconductor layer  122  includes a doping element such as magnesium (Mg) to form a p-type semiconductor, wherein the doping element includes a concentration greater than 9E+18, preferably greater than 4E+19, and more preferably greater than 1E+20. The second contact layer  132  includes a transparent conductive material that is transparent to the light emitted from the active layer  123  and capable of forming ohmic contact with the second semiconductor layer  122 . The transparent conductive material includes a non-metal material such as graphene, metal, or metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second contact layer  132  is substantially formed on the entire surface of the second semiconductor layer  122  and contacts the second semiconductor layer  122 . The electrical current is uniformly spread into the second semiconductor layer  122  through the second contact layer  132 .In an embodiment of the present application, the second contact layer  132  includes graphene, and the second contact layer  132  further includes a thin metal layer or a thin metal oxide layer with material such as nickel oxide (NiO), cobalt oxide (Co 3 O 4 ), or copper oxide (Cu 2 O) formed between the second semiconductor layer  122  and the graphene layer for forming ohmic contact with the second semiconductor layer  122 . The thin metal layer or thin metal oxide layer includes a thickness between 0.1 and 100 nm, preferably between 0.1 and 50 nm, more preferably between 0.1 and 20 nm.In an embodiment of the present application, the thickness of the second contact layer  132  is between 0.1 nm and 100 nm. If the thickness of the second contact layer  132  is less than 0.1 nm, an ohmic contact with the second semiconductor layer  122  cannot be formed therebetween because the thickness is too thin. Besides, if the thickness of the second contact layer  132  is greater than 100 nm, the second contact layer  132  is too thick to partially absorb light emitted from the active layer  123 , and the luminance of the light-emitting device  1  is reduced. 
     In an embodiment of the present application, The positions of the first contact layer  131  and the second contact layers  132  formed on the semiconductor stack are misaligned and do not overlap each other. 
     A first insulating layer  14  is formed by physical vapor deposition or chemical vapor deposition to depositing an insulating material layer on the first contact layer  131  and the second contact layer  132 . The first insulating layer  14  is formed by patterning a portion of the insulating material layer by lithography and etching, and a first opening  1401  of the first insulating layer  14  is formed on the first contact layer  131  to expose the first contact layer  131  and a second opening  1402  of the first insulating layer  14  is formed on the second contact layer  132  to expose the second contact layer  132 . 
     In an embodiment of the present application, the first contact layer  131  includes the plurality of first contact portions P 1  and the plurality of first extending portions E 1 . The first insulating layer  14  includes a plurality of first openings  1401  respectively formed on the plurality of first contacts P 1 , wherein the plurality of first extending portions E 1  is covered by the first insulating layer  14 . 
     In an embodiment of the present application, the first insulating layer  14  includes a plurality of second openings  1402  respectively formed on the plurality of semiconductor pillars  12 . In other words, an amount of the plurality of second openings  1402  is same as that of the plurality of semiconductor pillars  12 . 
     In an embodiment of the present application, an amount of the plurality of second openings  1402  of the first insulating layer  14  is larger than that of the plurality of first openings  1401 . 
     In an embodiment of the present application, the second opening  1402  of the first insulating layer  14  includes a width smaller than that of the first opening  1401 . 
     In an embodiment of the present application, the first insulating layer  14  covers the third sidewalls  12   s  of the plurality of semiconductor pillars  12 , covers the surface S 1  of the first semiconductor layer  111 , covers the second sidewall  111   s  of the first semiconductor layer  111 , and/or covers the surface S 2  of the substrate  11 . 
     In an embodiment of the present application, the first insulating layer  14  protects the semiconductor structure, and includes two or more layers having different refractive indexes alternately stacked to form a Distributed Bragg reflector (DBR). The DBR selectively reflects light of a specific wavelength. The first insulating layer  14  is formed of a non-conductive material including organic material, inorganic material or dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     A first electrode contact layer  151  and a second electrode contact layer  152  are respectively formed in the first opening  1401  and the second opening  1402  of the first insulating layer  14  by physical vapor deposition or chemical vapor deposition, and extend and cover portions of the surface of the first insulating layer  14 . The first electrode contact layer  151  is connected to the first contact portion P 1  of the first contact layer  131  through the first opening  1401  of the first insulating layer  14 . The second electrode contact layer  152  is connected to the plurality of second contact layers  132  through the second opening  1402  of the first insulating layer  14 . 
     In an embodiment of the present application, the second electrode contact layer  152  covers the plurality of semiconductor pillars  12  and portions of the first contact layer  131 , wherein the second electrode contact layer  152  is electrically isolated from the first contact layer  131  by the first insulating layer  14 . 
     In an embodiment of the present application, the first contact layer  131  includes the first contact portion P 1  including a width W1 larger than a width W2 of the semiconductor pillar  12 , the width W1 of the first contact portion P 1  of the first contact layer  131  is larger than the width W3 of the first electrode contact layer  151 , and the width W3 of the first electrode contact layer  151  is larger than the width W2 of the semiconductor pillar  12 . 
     In an embodiment of the present application, the first electrode contact layer  151  covers portions of the first contact layer  131 , the second electrode contact layer  152  covers all of the second contact layers  132 . 
     In an embodiment of the present application, the first electrode contact layer  151  covers portions of the first contact layer  131 , the second electrode contact layer  152  covers portions of the second contact layers  132 . 
     In an embodiment of the present application, the first electrode contact layer  151  covers all of the first contact layer  131 , the second electrode contact layer  152  covers portions of the second contact layers  132 . 
     In an embodiment of the present application, the first electrode contact layer  151  and the second electrode contact layer  152  are separated from each other by a distance. In the top view of the light-emitting device  1 , the second electrode contact layer  152   surrounds multiple sidewalls of the first electrode contact layer  151 . 
     In an embodiment of the present application, in the top view of the light-emitting device  1 , the second electrode contact layer  152  includes an area larger than an area of the first electrode contact layer  151 . 
     In an embodiment of the present application, when an external current is injected into the light-emitting device  1 , the electrical current is conducted to the first semiconductor layer  111  and the second semiconductor layer  122  by the first electrode contact layer  151  and the second electrode contact layer  152 . 
     As shown in  FIG.  1   , the first electrode contact layer  151  is close to one side of the substrate  11 , such as the left or right side of a centerline of the substrate  11 . 
     In an embodiment of the present application, the material of the first electrode contact layer  151  and the second electrode contact layer  152  include a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), rhodium (Rh), or an alloy of the above materials. 
     In an embodiment of the present application, the light emitted from the light-emitting device  1  includes a wavelength shorter than 370 nm, and the material of the first electrode contact layer  151  and the second electrode contact layer  152  do not include silver (Ag). The material of the first electrode contact layer  151  and the second electrode contact layer  152  includes a metal having a high reflectivity for the UV light, such as aluminum (Al), platinum (Pt) or rhodium (Rh). In order to increase the reflectivity of the first electrode contact layer  151  and the second electrode contact layer  152  for the UV light, the layer including aluminum (Al), platinum (Pt), or rhodium (Rh) includes a thickness greater than 4000 angstroms (Å), preferably greater than 8000 angstroms (Å), and more preferably greater than 10000 angstroms (Å). 
     In an embodiment of the present application, one side of the first electrode contact layer  151  contacting with the first contact layer  131  includes chromium (Cr) or titanium (Ti) to increase the bonding strength between the first electrode contact layer  151  and the first contact layer  131 . The second electrode contact layer  152  contacting with the second contact layer  132  includes chromium (Cr) or titanium (Ti) to increase the bonding strength between the second electrode contact layer  152  and the second contact layer  132 . In order to reduce the brightness loss caused by the ultraviolet light of chromium (Cr) or titanium (Ti) material, a thickness of the layer including chromium (Cr) or titanium (Ti) material is lower than 1000 angstroms (Å), preferably lower than 800 angstroms (Å), and more preferably lower than 500 angstroms (Å).And, in order to maintain sufficient bonding strength, the layer including chromium (Cr) and/or titanium (Ti) includes a thickness greater than 10 angstroms (Å), preferably greater than 50 angstroms (Å), and more preferably greater than 100 angstroms (Å). 
     A second insulating layer  16  is formed by physical vapor deposition or chemical vapor deposition to deposit an insulating material layer on the first electrode contact layer  151  and the second electrode contact layer  152 . Then, the insulating material layer is patterned by lithography and etching to form the second insulating layer  16 , and the first opening  1601  and the second opening  1602  of the second insulating layer  16  respectively exposing the first electrode contact layer  151  and the second electrode contact layer  152 . 
     In an embodiment of the present application, the second insulating layer  16  includes one or a plurality of first openings  1601  and one or a plurality of second openings  1602 , wherein an amount of the plurality of first openings  1601  and an amount of the plurality of second openings  1602  are the same or different. 
     In an embodiment of the present application, the plurality of first openings  1601  of the second insulating layer  16  are respectively formed on the plurality of first electrode contact layers  151 , wherein an amount of the plurality of first openings  1601  and an amount of the plurality of first electrode contact layers  151  are the same. 
     In the top view of  FIG.  1   , the first opening  1601  and the second opening  1602  of the second insulating layer  16  are respectively formed on two sides of the centerline of the substrate  11 . For example, the first opening  1601  of the second insulating layer  16  is formed on the right side of the centerline of the substrate  11 , and the second opening  1602  of the second insulating layer  16  is formed on the left side of the centerline of the substrate  11 . 
     In an embodiment of the present application, the first opening  1601  of the second insulating layer  16  includes a width smaller than a width of the first opening  1401  of the first insulating layer  14 . 
     In an embodiment of the present application, the first opening  1601  of the second insulating layer  16  overlaps the first opening  1401  of the first insulating layer  14 , and the first opening  1601  of the second insulating layer  16  and the first opening  1401  of the first insulating layer  14  are both formed on the first contact layer  131 . 
     In an embodiment of the present application, the second opening  1602  of the second insulating layer  16  and the second opening  1402  of the first insulating layer  14  are misaligned. Specifically, the second opening  1402  of the first insulating layer  14  is formed on the second contact layer  132 , and the second opening  1602  of the second insulating layer  16  is formed on the first contact layer  131 . 
     In an embodiment of the present application, when the second insulating layer  16  includes a stack structure, and the stack structure includes two or more sublayers; wherein the sublayers have two materials with different refractive indexes alternately stacked to form a Distributed Bragg reflector (DBR). The DBR selectively reflects light of a specific wavelength. The second insulating layer  16  is formed of a non-conductive material including organic material, inorganic material or dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     A first electrode  171  and a second electrode  172  are formed on the second insulating layer  16  by electroplating, physical vapor deposition or chemical vapor deposition. In the top view of  FIG.  1   , the first electrode  171  is close to one side of the substrate  11 , such as the right side of the centerline of the substrate  11 , and the second electrode  172  is close to the other side of the substrate  11 , such as the left side of the centerline of the substrate  11 . The first electrode  171  covers the first opening  1601  of the second insulating layer  16  to be in contact with the first electrode contact layer  151 , and is electrically connected with the first semiconductor layer  111  by the first contact layer  131 . The second electrode  172  covers the second opening  1602  of the second insulating layer  16  to be in contact with the second electrode contact layer  152 , and is electrically connected with the second semiconductor layer  122  by the second contact layer  132 . 
     In an embodiment of the present application, the plurality of semiconductor pillars  12  formed under a covering area of the first electrode  171  includes a first space D 1  to separate from each other. The plurality of semiconductor pillars  12  outside the covering area of the first electrode  171  includes a second space D 2  to separate from each other, and the first spacing D 1  is greater than the second spacing D 2 . 
     In an embodiment of the present application, the light emitting device  1  further includes a semiconductor mesa. The semiconductor mesa includes a first semiconductor layer, an active layer and a second semiconductor layer, and is formed under the first electrode  171 , wherein the plurality of semiconductor pillars  12  formed outside the covering area of the first electrode  171  includes a second space D 2  to separate from each other, and the second semiconductor layer of the semiconductor mesa includes a width larger than the second space D 2  between the plurality of semiconductor pillars  12 . 
     In an embodiment of the present application, the first contact portion P 1  of the first contact layer  131  is formed under the first electrode  171  and/or the second electrode  172 . The first extending portion E 1  of the first contact layer  131  is formed under the first electrode  171  and the second electrode  172 . 
     In an embodiment of the present application, the first electrode  171  includes a size equal to or different from a size of the second electrodes  172 . The size includes width or area. 
     In an embodiment of the present application, in the top view of the light-emitting device  1 , the shape of the first electrode  171  is the same as or similar to that of the second electrode  172 , for example, the shapes of the first electrode  171  and the second electrode  172  are rectangular, as shown in  FIG.  1   . 
     In an embodiment of the present application, the first electrode  171  and the second electrode  172  include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first electrode  171  and the second electrode  172  include a single layer or multiple layers. When the first electrode  171  and the second electrode  172  include multiple layers, the first electrode  171  includes a first upper pad and a first lower pad, and the second electrode  172  includes a second upper pad and a second lower pad. The upper pads and the lower pads have different functions. 
     In an embodiment of the present application, the function of the upper pad is mainly used for soldering and wire bonding. With the upper pad, the light-emitting device  1  can be mounted on a package substrate in a flip-chip form using solder or eutectic bonding, for example, an AuSn bonding. The metal material of the upper pad includes high-ductility material, such as tin (Sn), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru) osmium (Os), or alloys thereof. The upper pad can be a single layer or a laminated structure of the above materials. In an embodiment of the present application, the material of the upper pad includes nickel (Ni) and/or gold (Au), and the upper pad is a single layer or a laminated structure 
     In an embodiment of the present application, the function of the lower pad is to form a stable interface with the first electrode contact layer  151  and the second electrode contact layer  152 , for example, to increase the interface bonding strength between the first lower pad and the first electrode contact layer  151 , or to increase the interface bonding strength between the second lower pad and the second electrode contact layer  152 . Another function of the lower pad is to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the reflective structure that destroys the reflectivity of the reflective structure. Therefore, the lower pad includes metal materials other than gold (Au), copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr). molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os) or an alloy of the above materials. The lower pad can be a single layer or a laminated structure of the above materials. In an embodiment of the present application, the lower pad includes a laminated structure of titanium (Ti)/aluminum (Al) or a laminated structure of chromium (Cr)/aluminum (Al). 
     In an embodiment of the present application, in order to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the reflective structure that destroys the reflectivity of the reflective structure, one side of the first electrode contact layer  151  contacting with the first electrode  171  includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt). One side of the second electrode contact layer  152  contacting with the second electrode  172  includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt). 
       FIG.  3 A  illustrates a partial cross-sectional view of a light-emitting device  2 A in accordance with an embodiment of the present application.  FIG.  3 B  illustrates a partial top view of the light-emitting device  2 A in accordance with an embodiment of the present application. Since the light-emitting device  2 A and the light-emitting device  1  have substantially the same structure, the descriptions about the same structure of the light-emitting device  2 A and the light-emitting device  1  will be appropriately omitted or will not be repeated. 
     As shown in  FIG.  3 A  and  FIG.  3 B , the light-emitting device  2 A illustrates another example of the structural embodiment of the semiconductor pillar  12  of the light-emitting device  1  illustrated in  FIG.  1   . In an embodiment of the present application, the semiconductor stack includes a first semiconductor layer  221 , an active layer  223 , and a semiconductor pillar  22  on the active layer  223 . The active layer  223  includes one or more well layers and one or more barrier layer alternatively stacked, wherein the well layer includes Al x Ga 1-x N and 0.2&lt;x&lt;0.4, and the barrier layer includes Al y Ga 1-y N and 0.4&lt;y&lt;0.7. The semiconductor pillar  12  shown in the light-emitting device  1  of  FIG.  2    can be replaced by the semiconductor pillar  22  shown in  FIGS.  3 A and  3 B , the semiconductor pillar  22  includes a second semiconductor layer  222 . In an embodiment of the present application, the semiconductor pillar  22  further includes a portion of the active layer  223 . The active layer  223  is formed between the first semiconductor layer  221  and the second semiconductor layer  222 , and the active layer  223  emits a UV light. 
     In an embodiment of the present application, the substrate  11  includes a first sidewall  11   s , the first semiconductor layer  221  includes a second sidewall  221   s , the second semiconductor layer  222  includes a third sidewall  222   s , and the active layer  223  includes a sidewall  223   s . As shown in  FIG.  3 A , the third sidewall  222   s  of the second semiconductor layer  222  is separated from the sidewall  223   s  of the active layer  223  by a distance to expose a surface S 3  of the active layer  223 , wherein the exposed surface S 3  of the active layer  223  can be the well layer or the barrier layer, the well layer includes Al x Ga 1-x N and 0.2&lt;x&lt;0.4 , and the barrier layer includes Al y Ga 1-y N and 0.4&lt;y&lt;0.7. An obtuse angle or a right angle is between the third sidewall  222   s  of the second semiconductor layer  222  and the surfaces S 3  of the active layer  223 . 
     In an embodiment of the present application, in the top view of the light-emitting device  2 A shown in  FIG.  3 B , the second semiconductor layer  222  each includes a circle, an ellipse, a rectangle, a polygon, or any other shape. The second semiconductor layer  222  is surrounded by the active layer  223 , and part of the surface S 3  of the active layer  223  is exposed to be formed outside the covering area of the second semiconductor layer  222 . Part of the surface S 3  of the active layer  223  is not covered by the second semiconductor layer  222 , wherein the exposed surface S 3  of the active layer  223  can be the well layer or the barrier layer, the well layer includes Al x Ga 1-x N and 0.2&lt;x&lt;0.4 , and the barrier layer includes Al y Ga 1-y N and 0.4&lt;y&lt;0.7. 
     In an embodiment of the present application, the active layer  223  is surrounded by the first semiconductor layer  221 , and part of the surface S 1  of the first semiconductor layer  221  is exposed to be formed outside the covering area of the active layer  223 , wherein the first semiconductor layer  221  includes AlGaN. The part of the surface S 1  of the first semiconductor layer  221  is not covered by the active layer  223 . 
       FIG.  4 A  illustrates a partial cross-sectional view of a light-emitting device  2 B in accordance with an embodiment of the present application.  FIG.  4 B  illustrates a partial top view of the light-emitting device  2 B in accordance with an embodiment of the present application. Since the light-emitting device  2 B and the light-emitting device  1  have substantially the same structure, the descriptions about the same structure of the light-emitting device  2 B and the light-emitting device  1  will be appropriately omitted or will not be repeated. 
     As shown in  FIG.  4 A  and  FIG.  4 B , the light-emitting device  2 B illustrates another example of the structural embodiment of the semiconductor pillar  12  of the light-emitting device  1  illustrated in  FIG.  2   . In an embodiment of the present application, the semiconductor stack includes a first semiconductor layer  321 , an active layer  323 , and a plurality of semiconductor pillars  32  on the first semiconductor layer  321 . The semiconductor pillars  32  each includes a second semiconductor layer  322 , and the active layer  323  emits a UV light. 
     In an embodiment of the present application, the semiconductor pillar  32  further includes part of the active layer  323 . The active layer  323  is formed between the first semiconductor layer  321  and the second semiconductor layer  322 , and the active layer  323  emits UV light. 
     In an embodiment of the present application, in the top view of the light-emitting device  2 B shown in  FIG.  4 B , the second semiconductor layer  322  each includes a circle, an ellipse, a rectangle, a polygon, or any other shape. The second semiconductor layer  322  is surrounded by the active layer  323 , and part of the surface S 3  of the active layer  323  is exposed to be formed outside the covering area of the second semiconductor layer  322 . The part of the surface S 3  of the active layer  323  is not covered by the second semiconductor layer  323 . The active layer  323  is surrounded by the first semiconductor layer  321 , and part of the surface S 1  of the first semiconductor layer  321  is exposed outside the coverage area of the active layer  323 . The part of the surface S 1  of the first semiconductor layer  321  is not covered by the active layer  323 , wherein the first semiconductor layer  321  includes AlGaN. 
       FIG.  5    is a schematic view of a light-emitting apparatus  3  in accordance with an embodiment of the present application. The light-emitting device  1 ,  2 A, or  2 B in the foregoing embodiment is mounted on the first spacer  511  and the second spacer  512  of the package substrate  51  in the form of flip chip. The first spacer  511  and the second spacer  512  are electrically insulated from each other by an insulating portion  53  including an insulating material. The main light-extraction surface of the flip chip is one side of the growth substrate  11  opposite to the electrode-forming surface where the electrodes are formed on. A reflective structure  54  can be provided around the light-emitting device  1 ,  2 A, or  2 B to increase the light extraction efficiency of the light-emitting apparatus  3 . 
       FIG.  6    illustrates a structure diagram of a light-emitting apparatus  4  in accordance with an embodiment of the present application. A light bulb includes an envelope  602 , a lens  604 , a light-emitting module  610 , a base  612 , a heat sink  614 , a connector  616  and an electrical connecting device  618 . The light-emitting module  610  includes a submount  606  and a plurality of light-emitting devices  608  on the submount  606 , wherein the plurality of light-emitting devices  608  can be the light-emitting device  1 ,  2 A, or  2 B or the light-emitting apparatus  3  described in above embodiments. 
     The principle and the efficiency of the present application illustrated by the embodiments above are not the limitation of the application. Any person having ordinary skill in the art can modify or change the aforementioned embodiments. Therefore, the protection range of the rights in the application will be listed as the following claims.