Patent Publication Number: US-10331152-B2

Title: Quiescent current control in voltage regulators

Description:
TECHNICAL FIELD 
     This application relates to circuits and methods for generating an output voltage and regulating the output voltage to a target voltage, in particular to such circuits and methods that allow for reducing power consumption, e.g., power consumption resulting from a quiescent current flowing in the buffer stage of low-dropout regulators (LDOs). 
     BACKGROUND 
     Almost every modern power management integrated circuit (IC) incorporates a variety of different LDOs to provide stable and accurately regulated voltage supplies. The LDO drops the input voltage V in  by the pass device to the output voltage V out  to provide a regulated supply that is free of any noise. With steadily increasing demand for more regulated voltage supplies (e.g., a modern power management IC (PMIC) can include more than 20 LDOs), the current consumption (I q ) of the LDOs becomes the key parameter for power efficiency. 
     A class of LDOs may be very efficient in normal operation mode where the output voltage V out  is well below the input voltage V in , the quiescent current I q  at low load condition is well controlled to a low value (e.g., &lt;20 μA), and the current efficiency is very good. However, in a scenario where the input voltage V in  of the LDO is close to the desired regulated output voltage, i.e., in the so-called dropout operation region, the quiescent current I q  of the LDO increases (e.g., up to several mA) and is independent of the load current. This behavior heavily disrupts the power efficiency of the LDO. 
     SUMMARY 
     There is a need for improved quiescent current control in voltage regulators, specifically for a circuit for generating an output voltage and regulating the output voltage to a target voltage, and for an improved method of generating the output voltage and regulating the output voltage to a target voltage (or an improved method of controlling a circuit for generating the output voltage and regulating the output voltage to a target voltage). There further is a need for such a circuit and method to reduce power consumption, and to reduce a quiescent current flowing through a buffer stage of a low-dropout regulator (LDO). In particular, there is a need for such a circuit and method to guarantee substantially constant quiescent current I q  of the LDO, across the entire operation range for the input voltage, and to reduce the quiescent current I q  in the deep dropout case. 
     In view of some or all of these needs, the present disclosure proposes a circuit for generating an output voltage and regulating the output voltage to a target voltage and a method of operating a circuit for generating an output voltage and regulating the output voltage to a target voltage, having the features of the respective independent claims. 
     An aspect of the disclosure relates to a circuit (e.g., an LDO) for generating an output voltage and regulating the output voltage to a target voltage. The circuit may include a pass device (e.g., output pass device) coupled (e.g., connected) between an input voltage level and an output voltage level (e.g., between the input voltage level and the output node of the circuit). The pass device may be a pass transistor (e.g., output transistor). The circuit may further include an error amplifier stage configured to generate a first control voltage on the basis of (e.g., depending on) a reference voltage and the output voltage. The error amplifier stage may comprise an error amplifier. The first control voltage may be generated on the basis of (e.g., depending on) a fixed fraction of the output voltage. The circuit may further include a buffer stage configured to generate a drive signal for the pass device on the basis of (e.g., depending on) the first control voltage. The circuit may yet further include a tracking circuit (e.g., VDS tracking circuit) configured to track a voltage across the pass device and to generate a second control voltage on the basis of (e.g., depending on) the voltage across the pass device. The buffer stage may include a variable resistance element for limiting a current flowing through the buffer stage on the basis of (e.g., depending on) the second control voltage. Therein, a resistance value of the variable resistance element may depend on the second control voltage. The current may be a current flowing to ground from a supply voltage level. The pass device and all other transistors mentioned throughout this disclosure may be MOS transistors, e.g. MOSFETs. 
     Thus, the circuit comprises a current mode buffer stage and a (VDS) tracking circuit, and applies a so-called starved current mode buffer approach. Configured as such, the circuit guarantees almost constant quiescent current I q  (proportional to the load current) of the LDO across the entire input voltage operation range and reduces the quiescent current I q  in the deep dropout case. In particular, the quiescent current I q  is independent of the input voltage V in , the quiescent current Iq is proportional to the load current, which ensures best power efficiency, and the quiescent current I q  is fixed for deep dropout operation (the fixed value may or may not depend on the load current). 
     The proposed circuit may achieve the above advantages by adding only two additional transistors, one as acting as the variable resistance element, the other one being included in the tracking circuit, to realize the desired performance for a PMOS LDO structure. Further, the proposed solution is extendable to any LDO structure like a NMOS LDO or more complex LDO structures. 
     In embodiments, the buffer stage further includes a circuit branch comprising a first transistor and a second transistor coupled (e.g., connected) in series (not necessarily in this order) with the variable resistance element. The circuit branch (i.e., a series connection of the first transistor, the second transistor and the variable resistance element, not necessarily in this order) may be coupled (e.g., connected) between a supply voltage level and ground. The variable resistance element may limit a current flowing through the circuit branch. The first transistor may form a current mirror with the pass device. Further, a first voltage depending on the first control voltage may be supplied (e.g., fed, or provided) to a gate terminal of the second transistor. 
     Thereby, a particularly simple and efficient structure for implementing the buffer stage and for limiting the current flowing through the buffer stage can be provided. 
     In embodiments, the tracking circuit may include a third transistor and a current source that may be coupled (e.g., connected) in series (not necessarily in this order) between a drain terminal of the pass device and a predetermined voltage level. The third transistor may be referred to as a tracking transistor. The third transistor may be of the same type as the pass device. For a PMOS pass device, the predetermined voltage level may be ground. For an NMOS pass device, the predetermined voltage level may be a supply voltage level (e.g., Vdd). The current source may generate a bias current. A gate terminal and a drain terminal of the third transistor may be coupled (e.g., connected) to each other. Further, the second control voltage may be the voltage at the gate terminal of the third transistor. 
     Thereby, a particularly simple and efficient structure for tracking the voltage across the pass device and for controlling the variable resistance element via the second control voltage can be provided. 
     In embodiments, the variable resistance element may be a fourth transistor. Further, the second control voltage may be supplied to a gate terminal of the fourth transistor. For example, control terminals of the third and fourth transistors may be coupled (e.g., connected) to each other. 
     Thereby, the variable resistance element can be implemented in a simple manner, and efficient control of the variable resistance element is enabled. 
     In embodiments, the pass device, the first transistor, the third transistor, and the fourth transistor may be PMOS transistors and the second transistor may be an NMOS transistor. Further, the first, second, and fourth transistors may be coupled (e.g., connected) in series (not necessarily in this order) between a supply voltage level (e.g., the input voltage level) and ground. Yet further, the third transistor and the current source may be coupled (e.g., connected) in series (not necessarily in this order) between the drain terminal of the pass device and ground. Accordingly, the proposed solution can be readily applied to a PMOS LDO structure. 
     In embodiments, the fourth transistor may be coupled (e.g., connected) between a source terminal of the first transistor and the input voltage level. Further, gate and drain terminals of the first transistor may be coupled (e.g., connected) to each other. 
     In embodiments, the pass device, the first transistor, the third transistor, and the fourth transistor may be NMOS transistors and the second transistor may be a PMOS transistor. Further, the first, second, and fourth transistors may be coupled (e.g., connected) in series (not necessarily in this order) between a supply voltage level (e.g., Vdd) and ground (e.g., between said supply voltage level and the output voltage level). Yet further, the third transistor and the current source may be coupled (e.g., connected) in series (not necessarily in this order) between the drain terminal of the pass device and the supply voltage level. Accordingly, the proposed solution can be readily applied to a NMOS LDO structure. 
     In embodiments, the fourth transistor may be coupled (e.g., connected) between a source terminal of the first transistor and ground (e.g., between said source terminal and the output voltage level). Further, gate and drain terminals of the first transistor may be coupled (e.g., connected) to each other. 
     In embodiments, the buffer stage may further include a second circuit branch comprising a fifth transistor, a sixth transistor, and a seventh transistor coupled (e.g., connected) in series (not necessarily in this order). For example, the second circuit branch may be coupled (e.g., connected) between the supply voltage level and ground. The circuit may further include a second tracking circuit (e.g., VDS tracking circuit) for tracking a voltage across the second transistor and for generating a third control voltage on the basis of (e.g., depending on) the voltage across the second transistor. The fifth transistor may be a PMOS transistor and form a current mirror with the second transistor. The sixth transistor may be an NMOS transistor and a second voltage depending on the first control voltage (e.g., the first control voltage itself) may be supplied to a gate terminal of the sixth transistor. The seventh transistor may be a PMOS transistor and the third control voltage may be supplied to a gate terminal of the seventh transistor. 
     Another aspect of the disclosure relates to a method of operating a circuit for generating an output voltage and regulating the output voltage to a target voltage. The circuit may include a pass device (e.g., output pass device) coupled (e.g., connected) between an input voltage level and an output voltage level (e.g., an output node of the circuit). The pass device may be a pass transistor (e.g., output transistor). The method may include generating a first control voltage on the basis of (e.g., depending on) a reference voltage and the output voltage by means of an error amplifier stage (e.g., error amplifier). The first control voltage may be generated on the basis of (e.g., depending on) a fixed fraction of the output voltage. The method may further include generating a drive signal for the pass device on the basis of (e.g., depending on) the first control voltage by means of a buffer stage. The method may further include tracking a voltage across the pass device and generating a second control voltage on the basis of (e.g., depending on) the voltage across the pass device by means of a tracking circuit (e.g., VDS tracking circuit). The method may yet further include limiting a current flowing through the buffer stage on the basis of (e.g., depending on) the second control voltage by means of a variable resistance element included in the buffer stage. A resistance value of the variable resistance element may depend on the second control voltage. The current may be a current flowing to ground from a supply voltage level. The pass device and all other transistors mentioned throughout this disclosure may be MOS transistors, e.g. MOSFETs. 
     In embodiments, the buffer stage may further include a circuit branch comprising a first transistor and a second transistor coupled (e.g., connected) in series (not necessarily in this order) with the variable resistance element. The circuit branch (i.e., a series connection of the first transistor, the second transistor and the variable resistance element, not necessarily in this order) may be coupled (e.g., connected) between a supply voltage level and ground. The method may include limiting a current flowing through the circuit branch by means of the variable resistance element. The first transistor may form a current mirror with the pass device. The method may further include supplying a first voltage depending on the first control voltage to a gate terminal of the second transistor. 
     In embodiments, the tracking circuit may include a third transistor and a current source that may be coupled (e.g., connected) in series (not necessarily in this order) between a drain terminal of the pass device and a predetermined voltage level. The third transistor may be referred to as a tracking transistor. The third transistor may be of the same type as the pass device. For a PMOS pass device, the predetermined voltage level may be ground. For an NMOS pass device, the predetermined voltage level may a supply voltage level (e.g., Vdd). The method my include generating a bias current by means of the current source. A gate terminal and a drain terminal of the third transistor may be coupled (e.g., connected) to each other. The second control voltage may be the voltage at the gate terminal of the third transistor. 
     In embodiments, the variable resistance element may be a fourth transistor. The method may further include supplying the second control voltage to a gate terminal of the fourth transistor. For example, control terminals of the third and fourth transistors may be coupled (e.g., connected) to each other. 
     In embodiments, the pass device, the first transistor, the third transistor, and the fourth transistor may be PMOS transistors and the second transistor may be an NMOS transistor. The first, second, and fourth transistors may be coupled (e.g., connected) in series (not necessarily in this order) between a supply voltage level (e.g., the input voltage level for a PMOS pass device) and ground. Further, the third transistor and the current source may be coupled (e.g., connected) in series (not necessarily in this order) between the drain terminal of the pass device and ground. 
     In embodiments, the fourth transistor may be coupled (e.g., connected) between a source terminal of the first transistor and the input voltage level. Further, gate and drain terminals of the first transistor may be coupled (e.g., connected) to each other. 
     In embodiments, the pass device, the first transistor, the third transistor, and the fourth transistor may be NMOS transistors and the second transistor may be a PMOS transistor. The first, second, and fourth transistors may be coupled (e.g., connected) in series (not necessarily in this order) between a supply voltage level (e.g., Vdd) and ground (e.g., between said supply voltage level and the output voltage level). Further, the third transistor and the current source may be coupled (e.g., connected) in series (not necessarily in this order) between the drain terminal of the pass device and the supply voltage level. 
     In embodiments, the fourth transistor may be coupled (e.g., connected) between a source terminal of the first transistor and ground (e.g., between said source terminal and the output voltage level). Further, gate and drain terminals of the first transistor may be coupled (e.g., connected) to each other. 
     In embodiments, the buffer stage may further include a second circuit branch comprising a fifth transistor, a sixth transistor, and a seventh transistor coupled (e.g., connected) in series (not necessarily in this order). For example, the second circuit branch may be coupled (e.g., connected) between the supply voltage level and ground. The fifth transistor may be a PMOS transistor and form a current mirror with the second transistor. The sixth transistor may be an NMOS transistor and the seventh transistor may be a PMOS transistor. Then, the method may further include tracking a voltage across the second transistor and generating a third control voltage on the basis of the voltage across the second transistor by means of a second tracking circuit. The method may further include supplying a second voltage depending on the first control voltage to a gate terminal of the sixth transistor. The method may yet further include supplying the third control voltage to a gate terminal of the seventh transistor. 
     Notably, the method may be applied to any of the circuits described above, for example as a method of operating these circuits. In addition to steps for operating these circuits, the method may further include steps for providing or arranging some or all of the elements of these circuits and/or steps for coupling or connecting respective elements of these circuits. 
     Moreover, it will be appreciated that method steps and apparatus features may be interchanged in many ways. In particular, the details of the disclosed method can be implemented as an apparatus adapted to execute some or all or the steps of the method, and vice versa, as the skilled person will appreciate. In particular, it is understood that methods according to the disclosure relate to methods of operating the circuits according to the above embodiments and variations thereof, and that respective statements made with regard to the circuits likewise apply to the corresponding methods. 
     It is also understood that in the present document, the term “couple” or “coupled” refers to elements being in electrical communication with each other, whether directly connected e.g., via wires, or in some other manner. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Example embodiments of the disclosure are explained below with reference to the accompanying drawings, wherein like reference numbers indicate like or similar elements, and wherein 
         FIG. 1  schematically illustrates an example of a circuit for generating an output voltage and regulating the output voltage to a target voltage, embodying the principles of the disclosure. 
         FIG. 2  schematically illustrates the quiescent current of the circuit of  FIG. 1 . 
         FIG. 3  schematically illustrates an example of a circuit for generating an output voltage and regulating the output voltage to a target voltage, according to embodiments of the disclosure. 
         FIG. 4  schematically illustrates an example of a graph indicating a quiescent current in dependence on the input voltage, according to embodiments of the disclosure. 
         FIG. 5  schematically illustrates another example of a circuit for generating an output voltage and regulating the output voltage to a target voltage, according to embodiments of the disclosure. 
         FIG. 6  schematically illustrates another example of a circuit for generating an output voltage and regulating the output voltage to a target voltage, according to embodiments of the disclosure. 
         FIG. 7  shows a flow chart of a method of quiescent current control in a voltage regulator, embodying the principles of the disclosure. 
     
    
    
     DESCRIPTION 
     An example of a circuit (voltage regulator, i.e., circuit for generating an output voltage and regulating the output voltage to a target voltage)  100 , embodying the principles of the disclosure, is schematically illustrated in  FIG. 1 . This figure shows a generic PMOS LDO structure. The voltage regulator  100  includes a pass device (e.g., output pass device)  10  coupled (e.g., connected) between an input voltage level (input voltage) V in  and an output voltage level (output voltage) V out . For example, the pass device  10  may be coupled between the input voltage level V in  and an output node  20  of the voltage regulator  100 . In general, the pass device  10  may be a MOS, such as a MOSFET, for example. For the PMOS LDO structure, the pass device  10  may be a PMOS transistor. 
     The voltage regulator  100  further includes an error amplifier stage  30  having an error amplifier  35  and a buffer stage (e.g., current buffer)  50  coupled (e.g. connected) in series. The error amplifier stage  30  generates a first control voltage  60  on the basis of a reference voltage V ref  (e.g., a reference voltage depending on a target voltage for the output voltage V out ) and the output voltage V out . For example, the error amplifier stage  30  may generate the first control voltage  60  based on the reference voltage V ref  and a feedback voltage that is in a certain ratio to the output voltage V out . The feedback voltage may be tapped at a voltage divider that comprises a plurality of resistance elements (e.g., resistors)  94 ,  96  and that is coupled (e.g., connected) between the output voltage and ground. 
     The buffer stage  50  receives the first control voltage  60  (or a voltage  62  that depends on the first control voltage  60 ) as an input and is thus controlled by the first control voltage  60  (or, in more general terms, by the error amplifier stage  30 ). The buffer stage  50  generates a drive signal  64  for the pass device  10 . In particular, the buffer stage  50  generates a drive signal  64  for the pass device  10  based on the first control voltage  60 . 
     The buffer stage  50  comprises a first transistor  52  and a second transistor  54  that are coupled (e.g., connected) in series. The first transistor  52  forms a current mirror with the pass device  10 . A voltage  62  depending on the first control voltage  60  is supplied to a control terminal (e.g., gate terminal) of the second transistor  54 . Alternatively, the first control voltage  60  may be directly supplied to the control terminal of the second transistor  54 . For the PMOS LDO shown in  FIG. 1 , the first transistor  52  is a PMOS transistor, and the second transistor  54  is an NMOS transistor. 
     The voltage regulator  100  may further comprise an intermediate stage  40  including an inverter  45  coupled in series between the error amplifier stage  30  and the buffer stage  50 . The intermediate stage  40  may receive the first control voltage  60  and output the voltage  62  that depends on the first control voltage  60 . An intermediate node between the error amplifier stage  30  and the intermediate stage  40  may be coupled (e.g., connected) to the output node  20  through a capacitor  98 . 
     An output capacitor  92  may be coupled (e.g., connected) to the output node  20 . The output node  20  may provide the output voltage V out  to an electric load  90 . 
     In the above configuration, the quiescent current I q  of the buffer stage (current buffer)  50  is proportional to the load current I LOAD  if the input voltage V in  is high enough (e.g., &gt;200 mV). In this case, the quiescent current I q  is defined by the mirror ratio of the first transistor  52  and the pass device  10 . As the input voltage V in  starts to drop below a certain threshold (e.g., defined by V out +V ds,th ), the quiescent current I q  increases uncontrolled to its maximum value. This is shown in  FIG. 2 , in which curves  210  indicate the quiescent current I q  for the voltage regulator  100  of  FIG. 1  for maximum output current I MAX  (upper curve) and for the no load condition (lower curve), and curves  220  indicate the desired quiescent currents I q  under the aforementioned conditions. As the input voltage V in  continues to decrease further, the quiescent current I q  will reach its peak value I q,max , which is defined by the maximum current capability of the first and second transistors  52 ,  54 . Notably, this peak value is far beyond the quiescent current I q  in the normal operation region. This heavily disrupts the power efficiency of the LDO for input voltages V in  below the threshold value, e.g., for V in &lt;V OUT +V ds,th . Typically, V ds,th &lt;200 mV. Furthermore, the peak value I q,max  point is not dependent on the current load I LOAD  of the LDO. As can be also seen from  FIG. 2 , the two I q  curves  210 , i.e., at maximum load I q,IMAX  and at no load I q,noload , converge in the same I q,max , which even more reduces power efficiency for input voltages V in  below the threshold. 
     Broadly speaking, the present disclosure seeks to control the quiescent current I q  of the LDO to keep the quiescent I q  of the LDO proportional to the load current I LOAD  in all modes of operation, and to guarantee optimal power efficiency of the LDO. In other words, the present disclosure seeks to control the quiescent current to have characteristics as illustrated by curves  220  in  FIG. 2 . 
       FIG. 3  schematically illustrates an example of a circuit  200  for generating an output voltage and regulating the output voltage to a target voltage, according to embodiments of the disclosure. In the following, only elements that differ from elements already shown in  FIG. 1  will be described, and repeated description of the other elements will be omitted for reasons of conciseness. 
       FIG. 3  shows a generic PMOS LDO structure that includes, as the buffer stage  50 , a starved current mode buffer (SCB) for I q  control. The buffer stage  50  now includes, in addition to the first and second transistors  52 ,  54 , a variable resistance element  55  that is placed in series with the first and second transistors  52 ,  54 . Thus, the buffer stage may be said to comprise a (first) circuit branch that includes the first transistor  52 , the second transistor  54  and the variable resistance element  55  coupled (e.g., connected) in series (not necessarily in this order). As will be described in more detail below, the variable resistance element  55  has a function of limiting a current that flows through the buffer stage  50 . 
     The circuit  200  further comprises a tracking circuit (e.g., VDS tracking circuit)  70  for tracking a voltage across the pass device  10  (e.g., the drain-source voltage V ds  of the pass device  10 ). The tracking circuit further has a function of generating a second control voltage (e.g., starve voltage V pstarve )  65  on the basis of (e.g., depending on) the voltage across the pass device  10 . The variable resistance element  55  is controlled by the second control voltage  65 , i.e., the variable resistance element  55  limits the current flowing through the buffer stage  50  based on (e.g., depending on) the second control voltage  65 . 
     The tracking circuit  70  may comprise a third transistor  72  and a current source (e.g., bias current source)  74  that are coupled (e.g., connected) in series (not necessarily in this order) between a drain terminal of the pass device  10  and a predetermined voltage level. The current source  74  may generate a bias current for the third transistor  72 . The control terminal (e.g., gate terminal) and the drain terminal of the third transistor  72  may be coupled (e.g., connected) to each other. The second control voltage (V pstarve )  65  may be tapped at the gate terminal of the third transistor  72 . In this configuration, the second control voltage  65  is given by V pstarve =V in +V ds,PD +V gs,3 , where V in  is the input voltage, V ds,PD  is the voltage across the pass device  10  (e.g., the drain-source voltage of the pass device  10 ), and V gs,3  is the gate-source voltage of the third transistor  72 . Thus, the second control voltage  65  may be said to track the voltage across the pass device  10 . The gate-source voltage V gs,3  of the third transistor  72  is fixed and defined by the bias current I bias  generated by the current source  74 . 
     In various embodiments, the variable resistance element  55  may be a (fourth) transistor, and the second control voltage  65  may be supplied (e.g., fed, or provided) to a control terminal (e.g., gate terminal) of the fourth transistor  55 . To this end, the gate terminals of the third and fourth transistors  72 ,  55  may be coupled (e.g., connected) to each other. 
     Then, the gate-source voltage V gs,4  of the fourth transistor  55  is linearly dependent on the voltage V ds,PD  across the pass device  10 . The voltage V ds,PD  across the pass device  10  is the difference between the output voltage V out  and the input voltage V in , V ds,PD =V in −V out . 
     For V in &gt;&gt;V out +V ds,th , the fourth transistor  55  is in the linear region and acts as a serial resistor since its |V gs,4 |&gt;&gt;|V ds,4 |. As the input voltage V in  starts to approach the output voltage V out , the gate-source voltage of the fourth transistor  55  will be reduced and the resistance value of the fourth transistor  55  is slightly increasing, thereby reducing the quiescent current I q  in the buffer stage  55 . For V in ≤V out +V ds,th , the fourth transistor  55  will change its operation region from linear region to saturation region, and therefore the current in the buffer stage  55  will rapidly drop to its minimum value. The lowest value of the quiescent current I q  is defined by the current mirror ratio of the fourth transistor  55  and the third transistor  72 . 
     In general, the resistance value of the variable resistance element (e.g., fourth transistor)  55  may be said to depend on the second control voltage  65 . In particular, the resistance value may be inversely correlated with the second control voltage  65  (i.e., inversely correlated with the voltage across the pass device  10 ). Thus, the resistance value may increase for decreasing voltage across the pass device  10 , and vice versa. 
     Simulation results have shown that for V in &gt;&gt;V out  there is no difference in quiescent current I q  between the circuit  100  in  FIG. 1  and the proposed circuit  200  in  FIG. 3 . However, as the input voltage V in  starts to approach the output voltage V out , the quiescent current I q  of the circuit  100  rapidly increases to its maximum value independently of the load condition. For the proposed circuit  200 , the gate-source voltage |V gs,4 | of the fourth transistor  55  starts to decrease as V in  approaches V out  so that the fourth transistor  55  reduces (starves) the quiescent current I q  in the buffer stage  50 . If V in  continues to decrease, I q  is further reduced until it reaches its minimum value. Furthermore, the value of I q  for V in  close to V out  is now dependent on the load current I LOAD , which improves the power efficiency of the circuit  200  even more compared to the circuit  100 . 
     For the case of a PMOS LDO structure (illustrated, e.g., in  FIG. 3 ), the pass device  10  is a PMOS transistor, and the first, third, and fourth transistors  52 ,  72 ,  55  are PMOS transistors as well. The second transistor  54  is an NMOS transistor. The first circuit branch including the first, second and fourth transistors  52 ,  54 ,  55  may be coupled (e.g., connected) between a supply voltage (e.g., the input voltage V in ) and ground. Further, the predetermined voltage level may be ground. That is, the third transistor  72  and the current source  74  may be coupled (e.g., connected) between the drain terminal of the pass device  10  and ground. For an NMOS LDO as described further below, the predetermined voltage level may be a supply voltage (supply voltage level; e.g., V dd ). 
     In the example of  FIG. 3 , the fourth transistor  55 , the first transistor  52 , and the second transistor  54  are coupled (e.g., connected), in this order, between the supply voltage (e.g., the input voltage V in ) and ground. That is, the fourth transistor  55  is coupled (e.g., connected) between a source terminal of the first transistor  52  and the supply voltage (e.g., the input voltage V in ). 
     With the fourth transistor  55  placed (e.g., arranged) in the source of the first transistor  52 , the voltage |V ds,4,min |, which defines the voltage threshold for the drain-source voltage of the fourth transistor  55  at which the fourth transistor  55  goes from the linear region to the saturation region, is given by the on-state resistance R ds,4,on  of the fourth transistor  55  times the quiescent current I q , i.e., |V ds,4,min |=R ds,4,on ×I q . In typical implementations, this will yield a voltage |V ds,4,min | of approximately 0.2 V. Notably, for a configuration in which the fourth transistor  55  were placed in the drain of the first transistor  52  (e.g., a configuration in which the fourth transistor  55  is coupled between the drain terminal of the first transistor  52  and the drain terminal of the second transistor  54 ) rather than in the source of the first transistor  52 , the voltage |V ds,4,min | would be given by the gate-source voltage V gs,1  of the first transistor  52 , which would yield a significantly higher value (e.g., approximately 0.5 V in typical implementations). The lower the voltage |V ds,4,min |, the lower the input voltage V in  at which the fourth transistor  55  starts limiting the quiescent current I q . Accordingly, the circuit  200  in the example of  FIG. 3  will start limiting the quiescent current I q  at a lower input voltage V in  compared to a similar circuit in which the fourth transistor  55  is arranged in the drain of the first transistor  52 , thereby impacting operation of the LDO as little as possible for input voltages V in  above the output voltage V out . 
     To guarantee stable behavior of the LDO, the current in the buffer stage  50  should only be limited if the pass device  10  is in the linear region. This can be ensured by placing (e.g., arranging) the fourth transistor  55  in the source of the first transistor  52 , as shown in the example of  FIG. 3 . The reason is that for the placement of the fourth transistor  55  shown in the example of  FIG. 3  the quiescent current is limited at lower voltages of the input voltage V in  compared to a similar circuit in which the fourth transistor  55  is arranged in the drain of the first transistor  52 . 
     This is also shown in  FIG. 4 , which schematically illustrates a graph  410  indicating the input voltage V in , a graph  420  indicating the output voltage V out , a graph  430  indicating the quiescent current I q  if the fourth transistor  55  is placed in the source of the first transistor  52 , and a graph  440  indicating the quiescent current I q  if the fourth transistor  55  is placed in the drain of the first transistor  52 , each in dependence on the input voltage V in . Box  450  indicates the voltage range for which the pass device  10  is in the linear region, and V in,th,lin  indicates the voltage threshold at which the pass device  10  goes from the linear region to the saturation region. Further, V in,th,1  indicates a first voltage threshold at which the quiescent current I q  starts to be reduced or limited if the fourth transistor  55  is placed in the source of the first transistor  52 , and V in,th,2  indicates a second voltage threshold at which the quiescent current I q  starts to be reduced or limited if the fourth transistor  55  is placed in the drain of the first transistor  52 . As can be seen from  FIG. 4 , the first voltage threshold V in,th,1  falls into the voltage range in which the pass device  10  is in the linear region, whereas the second voltage threshold V in,th,2  falls into the voltage range in which the pass device  10  is in the saturation region. Reducing or limiting the quiescent current I q  while the pass device  10  is still in the saturation region may cause stability issues. 
     As noted above, the quiescent current I q  should only be limited if the pass device  10  is in the linear region (i.e., not in the saturation region anymore). This can be achieved by placing the fourth transistor  55  in the source of the first transistor  52 , as illustrated in the example of  FIG. 3 , thereby improving stability of the LDO. 
     The above concept for reducing (starving) the quiescent current I q  is generally applicable to LDO structures. Examples that illustrate application of the above concept to NMOS LDO structures will be described next. 
       FIG. 5  schematically illustrates another example of a circuit  300  for generating an output voltage and regulating the output voltage to a target voltage, according to embodiments of the disclosure. This figure shows a generic NMOS LDO structure. Now, the pass device (e.g., output pass device)  10 A is an NMOS transistor. Further, the circuit  300  comprises a buffer stage (current buffer)  50 A that differs from buffer stage  50  of circuit  100  in  FIG. 1 , as will be explained in more detail below. Otherwise, the circuits  100  and  300  may be identical. 
     Also here, the buffer stage  50 A generates a drive signal  64 A for the pass device  10 A based on the first control voltage  60 . Further, the buffer stage  50 A comprises a first circuit branch coupled (e.g., connected) between a supply voltage (e.g., V dd ) and ground. For example, the first circuit branch may be coupled (e.g., connected) between the supply voltage and the output voltage V out . The first circuit branch comprises a first transistor  52 A and a second transistor  54 A that are coupled (e.g., connected) in series. The first transistor  52 A forms a current mirror with the pass device  10 A. A voltage  66  depending on the first control voltage  60  is supplied to a control terminal (e.g., gate terminal) of the second transistor  54 A. For the NMOS LDO shown in  FIG. 5 , the first transistor  52 A is an NMOS transistor, and the second transistor  54 A is a PMOS transistor. The control (e.g., gate) and drain terminals of the first transistor  52 A are coupled (e.g., connected) to each other. 
     To adapt to the NMOS pass device  10 A, the buffer stage  50 A further comprises a second circuit branch coupled (e.g., connected) between the supply voltage (e.g., V dd ) and ground. For example, the second circuit branch may be coupled (e.g., connected) between the supply voltage and the output voltage V out . The second circuit branch comprises a fifth transistor  82  and a sixth transistor  84  coupled (e.g., connected) in series (not necessarily in this order). The fifth transistor  82  forms a current mirror with the second transistor  54 A. The first control voltage  60  (or a voltage  62  that depends on the first control voltage  60 ) is supplied to a control terminal (e.g., gate terminal) of the sixth transistor  84 . For the NMOS LDO shown in  FIG. 5 , the fifth transistor  82  is a PMOS transistor, and the sixth transistor  84  is an NMOS transistor. The control (e.g., gate) and drain terminals of the fifth transistor  82  are coupled (e.g., connected) to each other. In summary, the current buffer  50 A now comprise the first, second, fifth and sixth transistors  52 A,  54 A,  82 ,  84  to fit to the NMOS pass device  10 A. 
       FIG. 6  schematically illustrates an example of a circuit  400  for generating an output voltage and regulating the output voltage to a target voltage, according to embodiments of the disclosure. In the following, only elements that differ from elements already shown in  FIG. 5  will be described, and repeated description of the other elements is omitted for reasons of conciseness. 
       FIG. 6  shows a generic NMOS LDO structure that includes, as the buffer stage  50 A, a starved current mode buffer for I q  control. The buffer stage  50 A now includes, in addition to the first, second, fifth and sixth transistors  52 A,  54 A,  82 ,  84  a variable resistance element  55 A that is placed in series with the first and second transistors  52 A,  54 A. Thus, the first circuit branch includes the first transistor  52 A, the second transistor  54 A and the variable resistance element  55 A coupled (e.g., connected) in series (not necessarily in this order). As will be described in more detail below, the variable resistance element  55 A has a function of limiting a current that flows through the first circuit branch. 
     The circuit  400  further comprises a (first) tracking circuit  70 A for tracking a voltage across the pass device  10 A (e.g., the drain-source voltage V ds  of the pass device  10 A). The first tracking circuit  70 A (e.g., a pdrive VDS tracking circuit) further has a function of generating a second control voltage  65 A on the basis of (e.g., depending on) the voltage across the pass device  10 A. The variable resistance element  55 A is controlled by the second control voltage  65 A, i.e., the variable resistance element  55 A limits the current flowing through the first circuit branch (more generally, through the buffer stage  50 A) based on (e.g., depending on) the second control voltage  65 A. 
     The first tracking circuit  70 A may comprise a third transistor  72 A and a current source (e.g., bias current source)  74 A that are coupled (e.g., connected) in series (not necessarily in this order) between a drain terminal of the pass device  10 A and a predetermined voltage level. The current source  74 A may generate a bias current for the third transistor  72 A. The control terminal (e.g., gate terminal) and the drain terminal of the third transistor  72 A may be coupled (e.g., connected) to each other. The second control voltage  65 A may be tapped at the gate terminal of the third transistor  72 A. The second control voltage  65 A may be said to track the voltage across the pass device  10 A. The gate-source voltage V gs,3  of the third transistor  72 A is fixed and defined by the bias current I bias1  generated by the current source  74 A. Operation of the tracking circuit  70 A in circuit  400  is analogous to that of the tracking circuit  70  in circuit  200  described above. 
     In embodiments, the variable resistance element  55 A may be a (fourth) transistor, and the second control voltage  65 A may be supplied (e.g., fed, or provided) to a control terminal (e.g., gate terminal) of the fourth transistor  55 A. To this end, the gate terminals of the third and fourth transistors  72 A,  55 A may be coupled (e.g., connected) to each other. 
     Then, the gate-source voltage V gs,4  of the fourth transistor  55 A is linearly dependent on the voltage V ds,PD  across the pass device  10 A. The voltage V ds,PD  across the pass device  10 A is the difference between the output voltage V out  and the input voltage V in , V ds,PD =V in −V out . 
     Operation of the fourth transistor  55 A is analogous to that of the fourth transistor  55  in circuit  200  of  FIG. 3  described above. 
     For limiting a current that flows through the second circuit branch, the second circuit branch comprises, in addition to the fifth and sixth transistors  82 ,  84  also a seventh transistor  85  that acts as a second variable resistance element. Operation of the seventh transistor  85  will be described below. 
     For the case of an NMOS LDO structure (illustrated, e.g., in  FIG. 6 ), the pass device  10 A is an NMOS transistor, and the first, third, and fourth transistors  52 A,  72 A,  55 A are NMOS transistors as well. The second transistor  54 A is a PMOS transistor. The first circuit branch including the first, second and fourth transistors  52 A,  54 A,  55 A may be coupled (e.g., connected) between the supply voltage (e.g., V dd ) and ground (e.g., between the supply voltage and the output voltage). The second transistor  54 A, the first transistor  52 A, and the fourth transistor  55 A may be coupled (e.g., connected), in this order, between the supply voltage (e.g., V dd ) and ground (e.g., between the supply voltage and the output voltage). That is, the fourth transistor  55 A may be coupled (e.g., connected) between a source terminal of the first transistor  52 A and ground. Further, the predetermined voltage level may be the supply voltage (e.g., V dd ). That is, the third transistor  72 A and the current source  74 A may be coupled (e.g., connected) between the drain terminal of the pass device  10 A and the supply voltage. 
     In the example of  FIG. 6 , the fifth, sixth, and seventh transistors  82 ,  84 ,  85  are coupled (e.g., connected) in series. In particular, the seventh transistor  85  is a PMOS transistor that is coupled (e.g., connected) between the supply voltage and a source terminal of the fifth transistor  82 . The circuit  400  further comprises a second tracking circuit (e.g., a pdrive VDS tracking circuit)  75  for tracking a voltage across the second transistor  54 A and for generating a third control voltage  68  for controlling the seventh transistor  85 . The second tracking circuit  75  comprises an eighth transistor  76  (a PMOS transistor) and a second current source (e.g., bias current source)  77  that are coupled (e.g., connected) (not necessarily in this order) between a drain terminal of the second transistor  54 A and ground. The third control voltage  68  may be said to track the voltage across the second transistor  54 A. Operation of the second tracking circuit  75  is analogous to that of tracking circuit  70  in circuit  200  and tracking circuit  70 A in circuit  400 . The third control voltage  68  is supplied to the control terminal (e.g., gate terminal) of the seventh transistor  85 . 
     The circuit  400  of  FIG. 6  implements the concept of the present disclosure for an NMOS LDO structure. There are two additional VDS tracking circuits  70 A and  75  with the corresponding current starving transistors  55 A and  85  required to control the quiescent current I q  for the NMOS LDO. As the V ds  voltage of the pass device  10 A decreases below a certain threshold, the starving transistors  55 A and  85  will reduce the quiescent current I q  of the current buffer in the same manner as for the PMOS LDO structure in  FIG. 3 . 
     In the example of  FIG. 6 , the seventh transistor  85  is a PMOS transistor that is coupled (e.g., connected) between the supply voltage and a source terminal of the fifth transistor  82 . Further, the third control voltage  68  generated by the second tracking circuit  75  is supplied to the gate terminal of the seventh transistor  85  for controlling the seventh transistor  85 . 
     The concepts described in the present disclosure are generally applicable to voltage regulator configurations (e.g., LDO configurations) including a buffer stage. 
     Unless indicated otherwise, elements of a series connection of two or more elements may be coupled (e.g., connected) to each other in any order, not just the order explicitly stated. 
     It should be noted that the apparatus features described above correspond to respective method features that may however not be explicitly described, for reasons of conciseness. The disclosure of the present document is considered to extend also to such method features. In particular, the present disclosure is understood to relate to methods of operating the circuits described above. 
       FIG. 7  shows a flow chart of a method of quiescent current control in a voltage regulator, embodying the principles of the disclosure. The method  700  comprises generating  710  a first control voltage with a reference voltage and an output voltage. Furthermore, the method  700  comprises generating  720  a drive signal for a pass device with a first control voltage. In addition, the method  700  comprises tracking  730  a voltage across the pass device and generating a second control voltage with the voltage across the pass device. The method  700  also comprises limiting  740  a current flowing through a buffer stage with the second control voltage. 
     It should further be noted that the description and drawings merely illustrate the principles of the proposed apparatus. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed method. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.