Patent Publication Number: US-7903150-B2

Title: Differential amplifier circuit used in solid-state image pickup apparatus, and arrangement that avoids influence of variations of integrated circuits in manufacture and the like

Description:
This application is a division of application Ser. No. 10/216,740, filed Aug. 13, 2002. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a differential amplifier circuit used in an image input apparatus for, e.g., a video camera, digital still camera, and image scanner. 
     2. Related Background Art 
     In recent years, a cell size reduction of a photoelectric conversion element is strenuously being made using a micropatterning process to achieve higher resolution, and a photoelectric conversion signal output is lowering accordingly. Under the circumstance, an amplifier type solid-state image pickup device that can amplify and output a photoelectric conversion signal has received a lot of attention. As such amplifier type photoelectric conversion devices, MOS, AMI, CMD, BASIS devices, and the like are available. Of these devices, a MOS device accumulates photocarriers which is generated by a photodiode, in the gate electrode of a MOS transistor, and charge-amplifies and outputs its change in potential to an output unit in accordance with a drive timing from a scanning circuit. In recent years, of MOS devices, a CMOS solid-state image pickup device as well as its photoelectric conversion unit and peripheral circuit units, all of which are realized by CMOS processes has especially received a lot of attention. 
       FIG. 11  is a block diagram of a general CMOS solid-state image pickup device. In this example, the anodes of photodiodes D 11  to D 33  for generating photosignal charges are connected to the ground. The cathodes of the photodiodes D 11  to D 33  are connected to the gates of amplifier MOS transistors M 311  to M 333  via transfer MOS transistors M 111  to M 133 . The gates of the amplifier MOS transistors M 311  to M 333  are connected to the sources of reset MOS transistors M 211  to M 233  used to reset the transistors M 311  to M 333 . The drains of the reset MOS transistors M 211  to M 233  are connected to a reset power supply. Furthermore, the drains of the amplifier MOS transistors M 311  to M 333  are connected to a power supply, and their sources are connected to the drains of select MOS transistors M 411  to M 433 . 
     The gate of the transfer MOS transistor M 111  is connected to a first row select line (vertical scanning line) PTX 1  that runs horizontally. The gates of similar transfer MOS transistors M 121  and M 131  of other pixels connected to the same row are also connected in common to the first row select line PTX 1 . The gate of the reset MOS transistor M 211  is connected to a second row select line (vertical scanning line) PRES 1  which runs horizontally. The gates of similar reset MOS transistors M 211  and M 231  of other pixels connected to the same row are also connected in common to the second row select line PRES 1 . The gate of the select MOS transistor M 411  is connected to a third row select line (vertical scanning line) PSEL 1  that runs horizontally. The gates of similar select MOS transistors M 421  and M 431  of other pixels connected to the same row are also connected in common to the third row select line PSEL 1 . These first to third row select lines are connected to a vertical scanning circuit  2 , and receive signal voltages on the basis of operation timings to be described later. Pixels and row select lines with similar arrangements are connected to the remaining rows shown in  FIG. 11 . These row select lines receive signals PTX 2  and PTX 3 , PRES 2  and PRES 3 , and PSEL 2  and PSEL 3  generated by the vertical scanning circuit  2 . 
     The source of the select MOS transistor M 411  is connected to a vertical signal line V 1  which runs vertically. The sources of similar MOS transistors M 412  and M 413  of pixels connected to the same column are also connected to the vertical signal line V 1 . The vertical signal line V 1  is connected to a load MOS transistor N 82  serving as a load means. The select MOS transistors and load MOS transistors are similarly connected to remaining vertical signal lines V 2  and V 3  shown in  FIG. 11 . Furthermore, the sources of the load MOS transistors N 82  to N 84  are connected to a common GND line  4 , and their gates are connected to the gate of an input MOS transistor N 81  and in common to a voltage input terminal  5 . 
     Furthermore, the vertical signal line V 1  is connected to a capacitor CTN 1  used to temporarily hold a noise signal via a noise signal transfer switch N 91 , and also to a capacitor CTS 1  used to temporarily hold a photosignal via a photosignal transfer switch N 92 . The terminals, opposite to the vertical signal line V 1 , of the noise signal holding capacitor CTN 1  and photosignal holding capacitor CTS 1  are connected to the ground. The node between the noise signal transfer switch N 91  and noise signal holding capacitor CTN 1 , and the node between the photosignal transfer switch N 92  and photosignal holding capacitor CTS 1  are connected to the ground respectively via holding capacitor reset switches N 92  and N 98 , and are connected to a differential amplifier circuit  7  used to calculate the difference between a photosignal and noise signal via horizontal transfer switches N 913  and N 914 . The gates of the horizontal transfer switches N 913  and N 914  are connected in common to a column select line H 1 , and to a horizontal scanning circuit  3 . Read circuits with similar arrangements are connected to remaining columns V 2  and V 3  shown in  FIG. 11 . The gates of the noise signal transfer switches N 91 , N 93 , and N 95 , and photosignal transfer switches N 92 , N 94 , and N 96  are respectively connected in common to PTN and PTS, and receive signal voltages on the basis of operation timings to be described below. 
     The operation of the CMOS solid-state image pickup device shown in  FIG. 11  will be described below with reference to  FIG. 12 . Prior to read processes of photosignal charges from the photodiodes D 11  to D 33 , the gates PRES 1  of the reset MOS transistors M 211  to M 231  change to high level. As a result, the gates of the amplifier MOS transistors M 311  to M 331  are reset to the reset power supply. After the gates PRES 1  of the reset MOS transistors M 211  to M 231  return to low level, the gates PSEL 1  of the select MOS transistors M 411  to M 431  and the gates PTN of the noise signal transfer switches N 91 , N 93 , and N 95  change to high level. As a result, reset signals (noise signals) superposed with reset noise are read out to the noise signal holding capacitors CTN 1  to CTN 3 . 
     Then, the gates PTN of the noise signal transfer switches N 91 , N 93 , and N 95  return to low level. The gates PTX 1  of the transfer MOS transistors M 111  to M 131  change to high level, and photosignal charges in the photodiodes D 11  to D 31  are transferred to the gates of the amplifier MOS transistors M 311  to M 331 . After the gates PTX 1  of the transfer MOS transistors M 111  to M 131  return to low level, the gates PTS of the photosignal transfer switches N 92 , N 94 , and N 96  change to high level. As a result, photosignals are read out to the photosignal holding capacitors CTS 1  to CTS 3 . The gates PTS of the photosignal transfer switches N 92 , N 94 , and N 96  then return to low level. With the operations described so far, noise signals and photosignals of pixels connected to the first row are respectively held in the noise signal holding capacitors CTN 1  to CTN 3  and photosignal holding capacitors CTS 1  to CTS 3  connected to the respective columns. 
     The gates PRES 1  of the reset MOS transistors M 211  to M 231  and the gates PTX 1  of the transfer MOS transistors M 111  to M 131  change to high level to reset photosignal charges in the photodiodes D 11  to D 31 . After that, the gates of the horizontal transfer switches N 913  to N 918  of respective columns change to high level in turn in response to signals H 1  to H 3  from the horizontal scanning circuit  3 , and voltages held in the noise holding capacitors CTN 1  to CTN 3  and photosignal holding capacitors CTS 1  to CTS 3  are sequentially read out to the differential amplifier circuit  7 . In between signal read processes of respective columns, the negative (inverting) and positive-phase (non-inverting) input terminals of the differential amplifier circuit  7  are reset to a reset voltage Vres of a horizontal output line by reset switches N 919  and N 920 . The differential amplifier circuit  7  calculates the differences between photosignals and noise signals and sequentially outputs them onto an output terminal OUT. In this manner, the read processes of the pixels connected to the first row are completed. 
     After that, prior to read processes of the second row, the gates PCTR of reset switches N 97  to N 912  for the noise signal holding capacitors CTN 1  to CTN 3  and photosignal holding capacitors CTS 1  to CTS 3  change to high level to be reset to GND. Likewise, signals of pixels connected to the second and subsequent rows are sequentially read out in response to signals from the vertical scanning circuit  2 , thus completing the read processes from all pixels. 
     In the aforementioned CMOS solid-state image pickup device, it is a common practice to use a differential amplifier circuit using an operational amplifier shown in  FIG. 13  as the differential amplifier circuit used to calculate the difference between the photosignal and noise signal. The input/output characteristics in such differential amplifier circuit are determined by: 
                   Vout   =           Vinp   ·   R     ⁢           ⁢   94   ⁢     (       R   ⁢           ⁢   91     +     R   ⁢           ⁢   92       )       -     Vinn   ·     (       R   ⁢           ⁢   93     +     R   ⁢           ⁢   94       )           R   ⁢           ⁢     91   ·     (       R   ⁢           ⁢   93     +     R   ⁢           ⁢   94       )                   (   1   )               
If R 91 =R 93  and R 92 =R 94 , we have:
 
     
       
         
           
             
               Vout 
               = 
               
                 
                   ( 
                   
                     Vinp 
                     - 
                     Vinn 
                   
                   ) 
                 
                 · 
                 
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     92 
                   
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     91 
                   
                 
               
             
             ⁢ 
             
                 
             
           
         
       
     
     However, when the aforementioned differential amplifier circuit is formed on a single semiconductor substrate such as a monocrystalline silicon substrate by the manufacturing technique of semiconductor integrated circuits, conditions R 91 =R 93  and R 92 =R 94  may deviate due to variations or the like in the manufacture. 
     For example, if R 91 =R 93  and aR 92 =R 94 , equation (1) is rewritten as: 
     
       
         
           
             
               Vout 
               = 
               
                 
                   
                     ( 
                     
                       Vinp 
                       - 
                       Vinn 
                     
                     ) 
                   
                   · 
                   
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       92 
                     
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       91 
                     
                   
                 
                 + 
                 
                   Vinp 
                   · 
                   
                     
                       
                         ( 
                         
                           a 
                           - 
                           1 
                         
                         ) 
                       
                       ⁢ 
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       91 
                     
                     
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         91 
                       
                       + 
                       
                         
                           a 
                           · 
                           R 
                         
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         92 
                       
                     
                   
                 
               
             
             ⁢ 
             
                 
             
           
         
       
     
     This means that an output appears as Vout even when a signal Vinp=Vinn is input, and the common-mode rejection ratio (to be abbreviated as CMRR hereinafter) impairs. Consequently, the noise rejection ratio of the CMOS solid-state image pickup device impairs. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a high-performance differential amplifier circuit, and a solid-state image pickup device and image pickup system using the same. 
     In order to achieve the above object, according to an embodiment of the present invention, there is provided a differential amplifier circuit which comprises positive-phase and negative input terminals and amplifies and outputs a differential voltage between voltages applied to the two terminals, comprising: a first voltage-current conversion circuit, arranged to convert the differential voltage into a current using a first resistor and output the current; and a second voltage-current conversion circuit, arranged to convert a differential voltage between a reference voltage and a voltage obtained by impedance-converting the output from the first voltage-current conversion circuit by an impedance conversion circuit, into a current using a second resistor, wherein the output portions of the first and second voltage-current conversion circuits are connected, and the output portion of the impedance conversion circuit serves as an output terminal of the differential amplifier circuit. 
     With the above arrangement, even when a differential amplifier circuit is formed on a single semiconductor substrate such as a monocrystalline silicon substrate by the manufacturing technique of semiconductor integrated circuits, a differential amplifier circuit with high CMRR can always be manufactured without being influenced by variations and the like in the manufacture. 
     Other objects of the present invention will become apparent from the following description of the specification taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a differential amplifier circuit serving as a precondition of the first to fourth embodiments; 
         FIG. 2  is a block diagram showing an example of an operational amplifier used in the differential amplifier circuit shown in  FIG. 1 ; 
         FIG. 3  is a block diagram of a differential amplifier circuit according to the first embodiment of the present invention; 
         FIG. 4  is a block diagram showing an example of a constant current generation circuit used in the differential amplifier circuit of the present invention; 
         FIG. 5  is a block diagram of a differential amplifier circuit according to the second embodiment of the present invention; 
         FIG. 6  is a block diagram of a differential amplifier circuit according to the third embodiment of the present invention; 
         FIG. 7  is a block diagram of a differential amplifier circuit according to the fourth embodiment of the present invention; 
         FIG. 8  is a block diagram of a solid-state image pickup device according to the fifth embodiment of the present invention; 
         FIG. 9  is a timing chart for explaining the operation of the fifth embodiment; 
         FIG. 10  is a block diagram showing the seventh embodiment of the present invention, in which the solid-state image pickup device according to the fifth embodiment of the present invention is applied to a “still camera”; 
         FIG. 11  is a block diagram showing a conventional solid-state image pickup device; 
         FIG. 12  is a timing chart for explaining the operation of the conventional image pickup device; and 
         FIG. 13  is a block diagram of a differential amplifier circuit used in the conventional solid-state image pickup device. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. 
       FIG. 1  shows the basic arrangement of a differential amplifier circuit serving as a precondition of the first to fourth embodiments. The differential amplifier circuit has a positive-phase input terminal Vinp, negative input terminal Vinn, and output terminal Vout. Also, the circuit has NMOS transistors N 11  and N 12 , PMOS transistors P 11  and P 12 , constant current sources I 11  and I 12 , and resistors R 11  and R 12 . Furthermore, the circuit has operational amplifiers Amp 11  to Amp 13 . 
       FIG. 2  shows an example of the operational amplifiers Amp 11  and Amp 12 , which include a positive-phase input terminal Vinp, negative input terminal Vinn, output terminal Vout, NMOS transistors N 21  and N 22 , PMOS transistors P 21  and P 22 , and constant current source I 21 . 
     Referring to  FIG. 1 , the NMOS transistors N 11  and N 12  and the constant current sources I 11  and I 12  form source followers that serve as the output stages of the operational amplifiers Amp 11  and Amp 12 . The outputs from the source followers are connected to the negative input terminals of the operational amplifiers Amp 11  and Amp 12 , and are connected to each other via the resistor R 11 . The drain of the NMOS transistor N 11  is connected to the input terminal of a current mirror circuit formed by the PMOS transistors P 11  and P 12 . The output terminal of the current mirror circuit is connected to the drain of the NMOS transistor N 12 , and serves as a current output terminal of a voltage-current conversion circuit. 
     The operation will be explained below. When differential voltages are input to the positive-phase and negative input terminals Vinp and Vinn, the drain currents of the NMOS transistors N 11  and N 12  are respectively given by: 
                 N   ⁢           ⁢   11     :   I     =       I   ⁢           ⁢   11     -       Vinp   -   Vinn       R   ⁢           ⁢   11                         N   ⁢           ⁢   12     :   I     =       I   ⁢           ⁢   12     +       Vinp   -   Vinn       R   ⁢           ⁢   11               
Hence, assuming that I 11 =I 12 , as the output of the voltage-current conversion circuit, a differential current:
 
             I   =     2   ·       Vinp   -   Vinn       R   ⁢           ⁢   11               
between the drain currents of the NMOS transistors N 11  and N 12  appears. The output terminal of the voltage-current conversion circuit is connected to the input terminal of a current-voltage conversion circuit formed by the operational amplifier Amp 13  having a feedback path which includes the resistor R 12 . Hence, the output current is converted into a voltage by the resistor R 12 , thus outputting a voltage:
 
             Vout   =         (     Vinp   -   Vinn     )     ·         2   ·   R     ⁢           ⁢   12       R   ⁢           ⁢   11         +   Vref           
In the above circuit arrangement, variations of the ratio between the resistors R 11  and R 12  due to variations of semiconductor integrated circuit in the manufacture never impair CMRR. Hence, a differential amplifier circuit with high CMRR can always be manufactured.
 
     First Embodiment 
       FIG. 3  is a block diagram showing a differential amplifier circuit according to the first embodiment of the present invention. This embodiment adopts a circuit arrangement to which the basic arrangement shown in  FIG. 1  is applied. The differential amplifier has a positive-phase input terminal Vinp, negative input terminal Vinn, and output terminal Vout. Also, the circuit has NMOS transistors N 31  to N 35 , PMOS transistors P 31  to P 34 , constant current sources I 31  to I 35 , and resistors R 31  and R 32 . Furthermore, the circuit has operational amplifiers Amp 31  to Amp 34 , each of which is formed by the circuit shown in  FIG. 2  as in  FIG. 1 . The arrangement and operation of a first voltage-current conversion circuit which includes the operational amplifiers Amp 31  and Amp 32  and the resistor R 31  are the same as those in  FIG. 1 , and this circuit outputs a differential current: 
     
       
         
           
             
               I 
               ⁢ 
               
                   
               
               ⁢ 
               1 
             
             = 
             
               2 
               · 
               
                 
                   Vinp 
                   - 
                   Vinn 
                 
                 
                   R 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   31 
                 
               
             
           
         
       
     
     In this embodiment, the output terminal of the first voltage-current conversion circuit is connected to that of a second voltage-current conversion circuit, which includes the operational amplifiers Amp 33  and Amp 34  and the resistor R 32  as in the first voltage-current conversion circuit, and also to the negative input terminal of the second voltage-current conversion circuit via a source follower as an impedance conversion circuit formed by the NMOS transistor N 33  and constant current source I 33 . Furthermore, the output terminal of the first voltage-current conversion circuit serves as the output terminal Vout of the differential amplifier circuit. The positive-phase input terminal of the second voltage-current conversion circuit is connected to a reference voltage Vref. The operation of the second voltage-current conversion circuit is the same as that of the first voltage-current conversion circuit, and a current: 
               I   ⁢           ⁢   2     =     2   ·       Vref   -   Vout       R   ⁢           ⁢   32               
is output to the node, which serves as a current output terminal, between the drains of the NMOS transistor N 34  and PMOS transistor P 33 . Since the node between the current outputs of the two voltage-current conversion circuits has a high input impedance, these circuits operate so as to attain I 1 =I 2 . Hence, a voltage:
 
             Vout   =         (     Vinp   -   Vinn     )     ·       R   ⁢           ⁢   32       R   ⁢           ⁢   31         +   Vref           
is output.
 
     In the present invention, even when the ratio between the resistors R 31  and R 32  varies due to variations of semiconductor integrated circuits in the manufacture, such variations never impair CMRR. Hence, a differential amplifier circuit with high CMRR can always be manufactured. In the differential amplifier circuit of this embodiment, since a feedback signal is a current (feedback is made so as to attain I 1 =I 2 ), satisfactory frequency characteristics can be obtained even when a high gain is set. 
     Furthermore, when each of the constant current sources I 31 , I 32 , I 34 , and I 35  uses a constant current generation circuit shown in, e.g.,  FIG. 4 , good temperature characteristics can be obtained in terms of gain and linearity. In  FIG. 4 , the constant current generation circuit includes an operational amplifier Amp 41 , NMOS transistors N 41  to N 43 , PMOS transistors P 41  and P 42 , and resistor R 41 . A constant voltage Vbg has small temperature characteristics like a band gap voltage. The constant current generation circuit has an output terminal Iout. The operational amplifier Amp 41  is buffer-connected, and can obtain an output current: 
             Iout   =     Vbg     R   ⁢           ⁢   41             
Using, as the resistor R 41 , the same type of resistor as the resistors R 31  and R 32  which form the first and second voltage-current conversion circuits, changes in gain and linearity of the differential amplifier circuit with respect to a change in temperature can be suppressed.
 
     Second Embodiment 
       FIG. 5  is a block diagram of a differential amplifier circuit according to the second embodiment of the present invention. The differential amplifier circuit has a positive-phase input terminal Vinp, negative input terminal Vinn, and output terminal Vout. Also, the circuit has NMOS transistors N 51  to N 513 , PMOS transistors P 51  to P 54 , constant current sources I 51  to I 55 , and resistors R 51  to R 54 . In addition, the circuit has operational amplifiers Amp 51  to Amp 54 , each of which is formed by the circuit shown in  FIG. 2  as in the first embodiment. The arrangement and operation of the differential amplifier circuit are the same as those in the first embodiment. Furthermore, each of the first and second voltage-current conversion circuits includes a plurality of resistors which are connected via the NMOS transistors N 53  to N 56  or N 510  to N 513  as switch elements, and connections of which are controlled by gain control terminals GC 1  to GC 4 . In  FIG. 5 , each voltage-current conversion circuit includes two resistors for the sake of simplicity, but the present invention is not limited to this. In this embodiment, the same effects as in the first embodiment can be obtained and, also, the gain control of the differential amplifier circuit can be attained by a simple arrangement. 
     Third Embodiment 
       FIG. 6  is a block diagram of a differential amplifier circuit according to the third embodiment of the present invention. The differential amplifier circuit has a positive-phase input terminal Vinp, negative input terminal Vinn, and output terminal Vout. Also, the circuit has NMOS transistors N 61  to N 615 , PMOS transistors P 61  to P 64 , constant current sources I 61  to I 65 , and resistors R 61  to R 63 . In addition, the circuit has operational amplifiers Amp 61  to Amp 64 , each of which is formed by the circuit shown in  FIG. 2  as in the first embodiment. This embodiment is substantially the same as the first embodiment, except that means for switching the voltage-current conversion gain is added to the first voltage-current conversion circuit. 
     The gates and drains of the NMOS transistors N 61  and N 67 , and N 62  and N 68  are connected in common, and their sources are connected in common to the constant current sources I 61  and I 62  via the NMOS transistors N 64  and N 610 , and N 65  and N 611  to form the output stages of the operational amplifiers Amp 61  and Amp 62  as source followers. The outputs from the source followers are connected in common to the negative input terminals of the operational amplifiers Amp 61  and Amp 62  via the NMOS transistors N 63  and N 69 , and N 66  and N 612 , and the NMOS transistors N 61  and N 62 , and N 67  and N 68  are connected to each other via the resistors R 61  and R 62 . The common drain of the NMOS transistors N 61  and N 67  is connected to the input terminal of a current mirror circuit formed by the PMOS transistors P 61  and P 62 , and the output terminal of the current mirror circuit is connected to the common drain of the NMOS transistors N 62  and N 68  and also serves as a current output terminal of a voltage-current conversion circuit. The connections of the source followers of the output stages of the operational amplifiers Amp 61  and Amp 62  are selected by signals input to gain control terminals GC 1  and GC 2 . 
     The operation of the differential amplifier circuit is the same as that in the first embodiment. When GC 1  is at high level and GC 2  is at low level, a voltage: 
             Vout   =         (     Vinp   -   Vinn     )     ·       R   ⁢           ⁢   63       R   ⁢           ⁢   61         +   Vref           
is output. On the other hand, when GC 1  is at low level and GC 2  is at high level, a voltage:
 
             Vout   =         (     Vinp   -   Vinn     )     ·       R   ⁢           ⁢   63       R   ⁢           ⁢   62         +   Vref           
is output. Since the gain is switched by such arrangement, load capacitances connected to the output stages of the operational amplifiers Amp 61  and Amp 62  can be reduced, and the number of selectable gain levels can be increased while maintaining good frequency characteristics. In  FIG. 6 , the first voltage-current conversion circuit has two selectable gain levels for the sake of simplicity. However, by increasing the numbers of source followers of the output stages, resistors, and switch elements, the number of selectable gain levels can be increased.
 
     Fourth Embodiment 
       FIG. 7  is a block diagram of a differential amplifier circuit according to the fourth embodiment of the present invention. The differential amplifier circuit has a positive-phase input terminal Vinp, negative input terminal Vinn, and output terminal Vout. Also, the circuit has NMOS transistors N 71  to N 77 , PMOS transistors P 71  to P 712 , constant current sources I 71  to I 75 , and resistors R 71  and R 72 . In addition, the circuit has operational amplifiers Amp 71  to Amp 74 , each of which is formed by the circuit shown in  FIG. 2  as in the first embodiment. This embodiment implements gain control by an arrangement different from those in the second and third embodiments. 
     The NMOS transistors N 71  and N 72  and the constant current sources I 71  and I 72  form the output stages of the operational amplifiers Amp 71  and Amp 72  as source followers. The outputs from the source followers are connected to the negative input terminals of the operational amplifiers Amp 71  and Amp 72 , and are connected to each other via the resistor R 71 . The drain of the NMOS transistor N 71  is connected to the input terminal of a first current mirror circuit, which is formed by the PMOS transistors P 71 , P 75 , and P 76  having the same size in this example, and the drain of the NMOS transistor N 72  is connected to the input terminal of a second current mirror circuit, which is formed by the PMOS transistors P 72 , P 73 , and P 74  having the same size in this example. The drains of the PMOS transistors P 73  and P 74  are connected in common via the PMOS transistors P 77  and P 79 , so as to switch the mirror ratio by signals input to gain control terminals GC 1  and GC 2 . Also, the drains of the PMOS transistors P 75  and P 76  are connected in common via the PMOS transistors P 78  and P 710  to similarly switch the mirror ratio by signals input to the gain control terminals GC 1  and GC 2 . The common drains of the PMOS transistors P 77  and P 79 , and P 78  and P 710  are respectively connected to the input and output terminals of a third current mirror circuit, which is formed by the NMOS transistors N 73  and N 74 , and the output terminal of the third current mirror circuit serves as a current output terminal of the voltage-current conversion circuit. 
     The operation of the differential amplifier circuit is the same as that in the second embodiment. When GC 1  is at high level and GC 2  is at low level, a voltage: 
             Vout   =         (     Vinp   -   Vinn     )     ·       R   ⁢           ⁢   72       R   ⁢           ⁢   71         +   Vref           
is output. On the other hand, when GC 1  is at low level and GC 2  is at high level, a voltage:
 
             Vout   =       2   ·     (     Vinp   -   Vinn     )     ·       R   ⁢           ⁢   72       R   ⁢           ⁢   71         +   Vref           
is output. Since the gain is switched by such arrangement, the circuit arrangement can be simplified. In  FIG. 7 , the mirror ratio is switched between 1× and 2×. However; a change in magnification and an increase in the number of levels to be set can be easily implemented by the same arrangement.
 
     Fifth Embodiment 
       FIG. 8  is a block diagram of a solid-state image pickup device according to the fifth embodiment of the present invention, which uses a differential amplifier circuit of one of the first to fourth embodiments. A pixel block  1  of the fifth embodiment has the same arrangement as that in the prior art, and the same reference numerals denote the same parts. A vertical signal line V 1  is connected to a capacitor CT 1 , which temporarily holds a signal, via a clamp capacitor CO 1  and transfer switch N 88 , and also to the negative input terminal of a differential amplifier circuit  6  via a horizontal transfer switch N 811 . The positive-phase input terminal of the differential amplifier circuit  6  is connected to a reset voltage Vres of a horizontal output line, and its negative input terminal is connected to the reset voltage Vres of the horizontal output line via a reset switch N 814 . That terminal of the signal holding capacitor CT 1 , which is opposite to that connected to the vertical signal line V 1 , is connected to the ground. The node between the clamp capacitor CO 1  and transfer switch N 88  is connected to a clamp power supply via a clamp switch N 85 . The gate of the horizontal transfer switch N 811  is connected to a column select line H 1 , and also to a horizontal scanning circuit  3 . Read circuits with the same arrangement are connected to remaining columns V 2  and V 3  shown in  FIG. 8 . The gates of clamp switches N 85  to N 87  and those of transfer switches N 88  to N 810  connected to respective columns are respectively connected in common to a clamp signal input terminal PCOR and transfer signal input terminal PT, and receive signal voltages on the basis of operation timings to be described below. 
     The operation of this embodiment will be explained below with reference to  FIG. 9 . Prior to read processes of photosignal charges from photodiodes D 11  to D 33 , the gates PRES 1  of reset MOS transistors M 211  to M 231  change to high level. As a result, the gates of amplifier MOS transistors M 311  to M 331  are reset to a reset power supply. The gates PRES 1  of the reset MOS transistors M 211  to M 231  return to low level and, at the same time, the gates PCOR of the clamp switches N 85  to N 87  change to high level. After that, the gates PSELL of select MOS transistors M 411  to M 432  change to high level. As a result, reset signals (noise signals) superposed with reset noise are read out to the vertical signal lines V 1  to V 3  and are clamped by the clamp capacitors col to CO 3 . At the same time, the gates PT of the transfer switches N 88  to N 810  change to high level to reset the signal holding capacitors CT 1  to CT 8  to a clamp voltage. 
     The gates PCOR of the clamp switches N 85  to N 87  then return to low level. The gates PTX 1  of transfer MOS transistors M 111  to M 131  change to high level to transfer photosignal charges of the photodiodes D 11  to D 31  to the gates of the amplifier MOS transistors M 311  to M 331 . At the same time, photosignals are read out onto the vertical signal lines V 1  to V 3 . After the gates PTX 1  of the transfer MOS transistors M 111  to M 131  return to low level, the gates PT of the transfer switches N 88  to N 810  change to low level. Hence, change components (photosignals) from the reset signals are read out to the signal holding capacitors CT 1  to CT 3 . With the operations described so far, the photosignals of pixels connected to the first row are respectively held in the signal holding capacitors CT 1  to CT 3  connected to the respective columns. 
     The gates PRES 1  of the reset MOS transistors M 211  to M 231  and the gates PTX 1  of the transfer MOS transistors M 111  to M 131  change to high level, thus resetting the photosignal charges in the photodiodes D 11  to D 31 . After that, the gates of horizontal transfer switches N 811  to N 813  change to high level in turn in response to signals H 1  to H 3  from the horizontal scanning circuit, and the voltages held in the signal holding capacitors CT 1  to CT 3  are sequentially read out to the negative input terminal of the differential amplifier circuit, and are sequentially output to an output terminal OUT. In between signal read processes of respective columns, the negative input terminal of the differential amplifier circuit is reset to a reset voltage Vres of the horizontal output line by a reset switches N 814 . In this manner, the read processes of the pixels connected to the first row are complete. Likewise, signals of pixels connected to the second and subsequent rows are sequentially read out in response to signals from a vertical scanning circuit, thus completing the read processes from all pixels. 
       FIG. 10  is a block diagram showing a case wherein the solid-state image pickup device of the fifth embodiment is applied to a still camera (image pickup system). The still camera includes a barrier  101  which serves as both a lens protector and main switch, a lens  102  for forming an optical image of an object on a solid-state image pickup element  104 , an iris  103  used to vary the amount of light that has passed through the lens  102 , the solid-state image pickup element  104  for capturing the object image formed by the lens  102  as an image signal, an A/D converter  106  for analog-to-digital converting the image signal output from the solid-state image pickup element  104  via an image pickup signal processing circuit  105 , and a signal processing unit  107  for making various corrections of image data output from the A/D converter  106 , and compressing data. The still camera also includes a timing generation unit  108  for outputting various timing signals to the solid-state image pickup element  104 , image pickup signal processing circuit  105 , A/D converter  106 , and signal processing unit  107 , a system control and operation unit  109  for making various arithmetic operations and controlling the entire still camera, a memory unit  110  for temporarily storing image data, an interface (I/F) unit  111  for recording or reading out data on or from a recording medium, a detachable recording medium  112  such as a semiconductor memory or the like on or from which image data is recorded or read out, and an interface unit  113  used to communicate with an external computer or the like. Subsequently, a photographing operation of the above-described still camera will be explained. 
     When the barrier  101  is opened, a main power supply is turned on, a power supply of a control system is then turned on, and a power supply of an image pickup system circuit including the A/D converter  106  and the like is also turned on. 
     The system control and operation unit  109  fully opens the iris  103  to control an exposure value. A signal output from the solid-state image pickup element  104  is converted into digital data by the A/D converter  106  and the digital data is input to the signal processing unit  107 . The system control and operation unit  109  performs an arithmetic operation of an exposure value based on that data. 
     As a result of this photometry, the brightness is determined, and the system control and operation unit  109  controls the iris in accordance with that determination result. 
     The system control and operation unit  109  performs an arithmetic operation of the distance to an object on the basis of a high-frequency component extracted from the signal output from the solid-state image pickup element  104 . After that, the lens is driven to check if an in-focus state is attained. If it is determined that an in-focus state is not attained, the lens is driven again to perform distance measurement. 
     After an in-focus state is confirmed, main exposure starts. Upon completion of exposure, an image signal output from the solid-state image pickup element is A/D-converted by the A/D converter  106 , and is written in the memory unit by the system control and operation unit  109  via the signal processing unit  107 . After that, the data stored in the memory unit  110  is recorded on the detachable recording medium  112  such as a semiconductor memory or the like via the recording medium control I/F unit under the control of the system control and operation unit  109 . The stored data may be directly input to a computer via the external I/F unit  113  to process an image. 
     Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.