Patent Publication Number: US-2022224294-A1

Title: Equalizer circuit and related power management circuit

Description:
RELATED APPLICATIONS 
     This application claims the benefit of provisional patent application Ser. No. 63/135,134, filed Jan. 8, 2021, the disclosures of which are hereby incorporated herein by reference in their entireties. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure is related to an equalizer circuit, and in particular to an equalizer circuit in a power management circuit configured to operate across a wide modulation bandwidth. 
     BACKGROUND 
     Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences. 
     The redefined user experience requires higher data rates offered by wireless communication technologies, such as fifth-generation new-radio (5G-NR) technology configured to communicate a millimeter wave (mmWave) radio frequency (RF) signal(s) in an mmWave spectrum located above 12 GHz frequency. To achieve higher data rates, a mobile communication device may employ a power amplifier(s) to increase output power of the mmWave RF signal(s) (e.g., maintaining sufficient energy per bit). However, the increased output power of mmWave RF signal(s) can lead to increased power consumption and thermal dissipation in the mobile communication device, thus compromising overall performance and user experience. 
     Envelope tracking (ET) is a power management technology designed to improve efficiency levels of power amplifiers to help reduce power consumption and thermal dissipation in mobile communication devices. In an ET system, a power amplifier(s) amplifies an RF signal(s) based on a time-variant ET voltage(s) generated in accordance with time-variant amplitudes of the RF signal(s). More specifically, the time-variant ET voltage(s) corresponds to a time-variant voltage envelope(s) that tracks (e.g., rises and falls) a time-variant power envelope(s) of the RF signal(s). Understandably, the better the time-variant voltage envelope(s) tracks the time-variant power envelope(s), the higher linearity the power amplifier(s) can achieve. 
     However, the time-variant ET voltage(s) can be highly susceptible to distortions caused by trace inductance and/or load impedance, particularly when the time-variant ET voltage(s) is so generated to track the time-variant power envelope(s) of a high modulation bandwidth (e.g., &gt;200 MHz) RF signal(s). As a result, the time-variant voltage envelope(s) may become misaligned with the time-variant power envelope(s) of the RF signal(s), thus causing unwanted distortions (e.g., amplitude clipping) in the RF signal(s). In this regard, it is desirable to reduce distortions caused by trace inductance and/or load impedance in the time-variant ET voltage(s). 
     SUMMARY 
     Embodiments of the disclosure relate to an equalizer circuit and a related power management circuit. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit(s) via a signal path for amplifying a radio frequency (RF) signal(s). Notably, the voltage amplifier circuit can have an inherent impedance and the signal path can have an inherent trance inductance that can collectively distort the ET voltage. As such, an equalizer circuit is provided in the power management circuit to equalize the differential target voltage prior to generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function including a second-order complex-zero term and a real-zero term for offsetting a transfer function of the inherent trace inductance and the inherent impedance. By employing the second-order transfer function with the real-zero term to offset the inherent trace inductance and the inherent impedance, it is possible to reduce distortion in the ET voltage, especially when the RF signal(s) is modulated in a wide modulation bandwidth (e.g., &gt;200 MHz). 
     In one aspect, an equalizer circuit is provided. The equalizer circuit includes a voltage input that receives a differential target voltage comprising a negative target voltage and a positive target voltage. The equalizer circuit also includes a voltage output that outputs an equalized target voltage corresponding to the differential target voltage. The equalizer circuit also includes an equalizer tuning circuit coupled between the voltage input and the voltage output. The equalizer tuning circuit is configured to cause the equalized target voltage to be generated from the differential target voltage based on a transfer function comprising a second-order complex-zero term and a real-zero term. 
     In another aspect, a power management circuit is provided. The power management circuit includes an equalizer circuit. The equalizer circuit includes a voltage input that receives a differential target voltage comprising a negative target voltage and a positive target voltage. The equalizer circuit also includes a voltage output that outputs an equalized target voltage corresponding to the differential target voltage. The equalizer circuit also includes an equalizer tuning circuit coupled between the voltage input and the voltage output. The equalizer tuning circuit is configured to cause the equalized target voltage to be generated from the differential target voltage based on a transfer function comprising a second-order complex-zero term and a real-zero term. The power management circuit also includes a voltage amplifier circuit configured to generate an ET voltage based on the equalized target voltage. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1  is a schematic diagram of an exemplary conventional envelope tracking (ET) power amplifier apparatus configured to generate an ET voltage; 
         FIG. 2  is a schematic diagram of an exemplary equivalent circuit for illustrating various impedances and/or inductances in the conventional power amplifier apparatus of  FIG. 1  that can distort the ET voltage; 
         FIG. 3  is a graphic diagram providing an exemplary illustration of factors contributing to a voltage disturbance in the equivalent circuit of  FIG. 2  that can distort the ET voltage in  FIG. 1 ; 
         FIG. 4  is a schematic diagram of an exemplary power management circuit configured according to an embodiment of the present disclosure to implement a second-order complex-zero transfer function with a real-zero term to offset voltage disturbance in an ET voltage; 
         FIG. 5  is a graphic diagram providing an exemplary illustration as to how the power management circuit of  FIG. 4  can effectively reduce the voltage disturbance as shown in  FIG. 3  based on the second-order complex-zero transfer function with the real-zero term to offset voltage disturbance in the ET voltage; 
         FIG. 6  is a schematic diagram providing an exemplary illustration of an equalizer circuit in the power management circuit of  FIG. 4  configured according to an embodiment of the present disclosure to implement the second-order complex-zero transfer function with a real-zero term to offset voltage disturbance in the ET voltage; 
         FIG. 7  is a schematic diagram providing an exemplary illustration of an equalizer tuning circuit provided in the equalizer circuit of  FIGS. 6 ; and 
         FIGS. 8A and 8B  are schematic diagrams providing exemplary illustrations of alternative implementations of the equalizer tuning circuit in  FIG. 7 . 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     Embodiments are described herein with reference to an equalizer circuit and a related power management circuit. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit(s) via a signal path for amplifying a radio frequency (RF) signal(s). Notably, the voltage amplifier circuit can have an inherent impedance and the signal path can have an inherent trance inductance that can collectively distort the ET voltage. As such, an equalizer circuit is provided in the power management circuit to equalize the differential target voltage prior to generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function having a second-order complex-zero term and a real-zero term for offsetting a transfer function of the inherent trace inductance and the inherent impedance. By employing the second-order transfer function with the real-zero term to offset the inherent trace inductance and the inherent impedance, it is possible to reduce distortion in the ET voltage, especially when the RF signal(s) is modulated in a wide modulation bandwidth (e.g., &gt;200 MHz). 
     Before discussing the power management circuit and the equalizer circuit incorporated therein according to the present disclosure, starting at  FIG. 4 , an overview of a conventional ET power management apparatus that can experience ET voltage distortion is first provided with reference to  FIGS. 1 to 3 . 
       FIG. 1  is a schematic diagram of an exemplary conventional power management apparatus  10  configured to generate an ET voltage V CC . The conventional power management apparatus  10  includes a transceiver circuit  12 , an ET integrated circuit (ETIC)  14 , a power amplifier circuit  16 , and a signal line(s)  18  that couples the ETIC  14  to the power amplifier circuit  16 . 
     The transceiver circuit  12  is configured to generate and provide an RF signal  20 , which is associated with a time-variant power envelope P ENV , to the power amplifier circuit  16 . The transceiver circuit  12  is also configured to generate a target voltage V TGT  in accordance with (a.k.a. tracks) the time-variant power envelope P ENV . The ETIC  14  is configured to generate the ET voltage V CC  based on the target voltage V TGT  and the power amplifier circuit  16  is configured to amplify the RF signal  20  based on the ET voltage V CC . 
     Those skilled in the art will appreciate that the power amplifier circuit  16  may operate with improved efficiency and linearity when the ET voltage V CC  accurately tracks the power envelope P ENV  of the RF signal  20 . This is achieved when the ET voltage V CC  is temporally aligned with the target voltage V TGT . However, temporal alignment between the ET voltage V CC  and the target voltage V TGT  may be complicated by various impedances and/or inductances presenting in the conventional power management apparatus  10 . 
     To illustrate the various impedances and/or inductances,  FIG. 2  is a schematic diagram of an exemplary equivalent circuit  22  for illustrating the various impedances and/or inductances in the conventional power management apparatus  10  of  FIG. 1  that can distort the ET voltage V CC . Common elements between  FIGS. 1 and 2  are shown therein with common element numbers and will not be re-described herein. 
     In the equivalent circuit  22 , the ETIC  14  has an inherent impedance that can be modeled by an equivalent inductance L ETIC  and the signal line(s)  20  has an inherent trance inductance that can be modeled by an equivalent trance inductance L TRACE . Accordingly, the equivalent circuit  22  would have a total equivalent inductance L E  that equals a sum of the equivalent inductance L ETIC  and the equivalent trance inductance L TRACE  (L E =L ETIC +L TRACE ). 
     The power amplifier circuit  16  can be modeled as a current source with a modulated current I CC (s) and have a total equivalent capacitance C PA . Accordingly, an equivalent source impedance Z SOURCE (s) presented to the current source can be determined as in equation (Eq. 1) below. 
     
       
         
           
             
               
                 
                   
                     
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     In the equation (Eq. 1), s represents the s-transform notation, which can be expressed as s=j2πf. The modulated current I CC (s) is somewhat proportional to the target voltage V TGT  and can be expressed as in equation (Eq. 2) below. 
     
       
         
           
             
               
                 
                   
                     
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     In the equation (Eq. 2) above, Z ICC (s) represents an impedance at a collector (not shown) of the power amplifier circuit  16  and ΔD represents a group delay between the V TGT  and the time-variant power envelope P EVN  at an output stage (not shown) of the power amplifier circuit  16 . 
     Notably, the modulated current I CC  can create a voltage disturbance across the collector of the power amplifier circuit  16 . The voltage disturbance is approximately equal to Z SOURCE (s)*I CC (s). As illustrated and discussed in  FIG. 3 , the voltage disturbance may primarily be caused by the total equivalent inductance L E .  FIG. 3  is a graphic diagram providing an exemplary illustration of factors contributing to the voltage disturbance in the equivalent circuit  22  of  FIG. 2  that can distort the ET voltage in  FIG. 1 . 
       FIG. 3  illustrates a first transfer function curve  24  and a second transfer function curve  26 . Specifically, the first transfer function curve  24  shows a transfer function of the equivalent trace inductance L TRACE  that can cause a voltage disturbance in the ET voltage V CC . The second transfer function curve  26  shows a transfer function of the equivalent impedance L ETIC  that can also cause a voltage disturbance in the ET voltage V CC . As shown in  FIG. 3 , the equivalent trace inductance L TRACE  can cause the ET voltage V CC  to peak at frequency A and decline sharply thereafter. The equivalent inductance L ETIC , on the other hand, can cause the ET voltage V CC  to decline starting at frequency B. The changes in the ET voltage V CC  (a.k.a. voltage disturbance) caused by the transfer functions of the equivalent trace inductance L TRACE  and the equivalent inductance L ETIC  can lead to a distortion of the ET voltage V CC . 
     With reference back to  FIG. 2 , the transfer functions of the equivalent trace inductance L TRACE  and the equivalent inductance L ETIC  can be generally expressed as H(s) in an s-domain according to Equation (Eq. 3) below: 
     
       
         
           
             
               
                 
                   
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     In the equation (Eq. 3) above, N(s) and D(s) are simple polynomials that define one or more zeros and one or more poles of the transfer function, respectively, and s=j2πf. The one or more zeros are the roots of the polynomial equation N(s) and can be determined by solving the equation N(s)=0. The order of the polynomial N(s) determines the number of zeros of the transfer function H(s). Each zero corresponds to a zero output of the transfer function H(s). The polynomial N(s) is a zero-order polynomial when N(s) represents a constant value, is a first-order polynomial when N(s)=1+b 0 s (where b 0  is a constant), is a second-order polynomial when N(s)=1+b 0 s+b 1 s 2  (where b 1  is a constant), and so on. In particular, the transfer function H(s) is further referred to as a real-zero term when N(s) is the first-order polynomial N(s)=1+b 0 s, or as a second-order complex-zero transfer function when N(s) is the second-order polynomial N(s)=1+b 0 s+b 1 s 2 . Accordingly, a transfer function H(s) with both the second-order complex-zero term (1+b 0 s+b 1 s 2 ) and the real-zero term (1+b 0 s) can be referred to as a second-order complex-zero transfer function with a real-zero term. 
     In contrast to the zeros, the one or more poles are the roots of the polynomial D(s) and can be determined by solving the equation D(s)=0. The order of the polynomial D(s) determines the number of poles of the transfer function H(s). Each pole corresponds to an infinite output of the transfer function H(s). The polynomial D(s) is a zero-order polynomial when D(s) represents a constant value, is a first-order polynomial when D(s)=1+a 0 s (where a 0  is a constant), is a second-order polynomial when D(s)=1+a 0 s+a 1 s 2  (where a 1  is a constant), and so on. In particular, the transfer function H(s) is further referred to as a real-pole term when D(s) is the first-order polynomial N(s)=1+a 0 s, or as a second-order complex-pole transfer function when D(s) is the second-order polynomial N(s)=1+a 0 s+a 1 s 2 . Accordingly, a transfer function H(s) with both the second-order complex-pole term (1+a 0 s+a 1 s 2 ) and the real-pole term (1+a 0 s) can be referred to as a second-order complex-pole transfer function with a real-pole term. 
     Specifically, the transfer function H(s) of the equivalent trace inductance L TRACE  can be the second-order complex-pole transfer function and the transfer function H(s) of the equivalent inductance L ETIC  can be the real-pole transfer term. Thus, an overall transfer function H(s) of the equivalent trace inductance L TRACE  and the equivalent inductance L ETIC  can be a second-order complex-pole transfer function H(s) with a real-pole term. In this regard, to reduce or even eliminate the voltage disturbance in the ET voltage V CC , it is necessary to implement a second-order complex-zero transfer function H(s) with a real-zero term to offset the second-order complex-pole transfer function H(s) with the real-pole term. Specific embodiments related to creating the second-order complex-zero transfer function N(s) to offset the voltage disturbance are discussed next, starting at  FIG. 4 . 
       FIG. 4  is a schematic diagram of an exemplary power management circuit  28  configured according to an embodiment of the present disclosure to implement a second-order complex-zero transfer function H(s) with a real-zero term to offset voltage disturbance in an ET voltage V CC . The power management circuit  28  can be provided in a power management apparatus  30  that also includes a power amplifier circuit  32 . The power management circuit  28  includes a voltage amplifier circuit  34  configured to generate the ET voltage V CC  based on a differential target voltage V TGT  and provide the ET voltage V CC  to the power amplifier circuit  32  via a signal path  36  (e.g., a conductive trace) for amplifying an RF signal  38 . 
     Notably, the voltage amplifier circuit  34  can have an inherent impedance that can be modeled by the equivalent inductance L ETIC  as shown in  FIG. 2 . Similarly, the signal path  36  can have an inherent trance inductance that can be modeled by the equivalent inductance L TRACE  as shown in  FIG. 2 . Thus, according to previous discussions in  FIGS. 2 and 3 , the equivalent inductance L ETIC  and the equivalent inductance L TRACE  can collectively present the second-order complex-pole transfer function H(s) with the real-pole to cause the voltage disturbance to distort the ET voltage V CC . 
     As such, the power management circuit  28  is configured to include an equalizer circuit  40 . As discussed in detail below, the equalizer circuit  40  is configured to equalize the differential target voltage V TGT  to generate an equalized target voltage V TGT-E . Accordingly, the voltage amplifier circuit  34  can be configured to generate the ET voltage V CC  based on the equalized target voltage V TGT-E . 
     Specifically, the equalizer circuit  40  is configured to generate the equalized target voltage V TGT-E  based on a second-order complex-zero transfer function H(s) with a real-zero term. In this regard, the equalized target voltage V TGT-E  can effectively offset the transfer function H(s) of the equivalent trace inductance L TRACE  and the equivalent inductance L ETIC . As a result, it is possible to eliminate the voltage disturbance in the ET voltage V CC , especially when the RF signal  38  is modulated in a wide modulation bandwidth (e.g., &gt;200 MHz). 
       FIG. 5  is a graphic diagram providing an exemplary illustration as to how the equalizer circuit  40  in the power management circuit  28  of  FIG. 4  can effectively reduce the voltage disturbance as shown in  FIG. 3  based on the second-order complex-zero transfer function H(s) with the real-zero term. Common elements between  FIGS. 3 and 5  are shown therein with common element numbers and will not be re-described herein. 
       FIG. 5  further illustrates a third transfer function curve  42  and a fourth transfer function curve  44 . Specifically, the third transfer function curve  42  represents the second-order complex-zero transfer function H(s) with the real-zero term as implemented by the equalizer circuit  40 . The fourth transfer function curve  44  represents an overall transfer function of the power management circuit  28 . As shown by the almost-flat fourth transfer function curve  44 , the power management circuit  28  can effectively eliminate the voltage disturbance caused by the equivalent trace inductance L TRACE  and the equivalent inductance L ETIC  as a result of implementing the second-order complex-zero transfer function H(s) with the real-zero term represented by the third transfer function curve  42 . 
       FIG. 6  is a schematic diagram providing an exemplary illustration of the equalizer circuit  40  in the power management circuit  28  of  FIG. 4  configured according to an embodiment of the present disclosure to implement the second-order complex-zero transfer function H(s) with the real-zero term. Common elements between  FIGS. 4 and 6  are shown therein with common element numbers and will not be re-described herein. 
     U.S. patent application Ser. No. 17/142,350 (hereinafter “App&#39;350”), entitled “EQUALIZER FOR ENVELOPE POWER SUPPLY CIRCUITRY,” disclosed equalizer circuitry that can effectively offset the second-order complex-zero transfer function of the equivalent trace inductance L TRACE . The equalizer circuit  40  discussed herein differs from the equalizer circuitry in App&#39;350 in that the equalizer circuit  40  can further offset the real-zero term of the equivalent inductance L ETIC . The equalizer circuit  40  further differs from the equalizer circuitry in App&#39;350 in that the equalizer circuit  40  includes an equalizer tuning circuit  46 , which may be controlled (e.g., based on modulation bandwidth of the RF signal  38 ) to change the transfer function H(s) of the equalizer circuit  40 . 
     The equalizer circuit  40  includes a voltage input  48  that receives the differential target voltage V TGT , which includes a negative target voltage V TGT-M  and a positive target voltage V TGT-P . In a non-limiting example, the voltage input  48  includes a negative target voltage input  50 M for receiving the negative target voltage V TGT-M  and a positive target voltage input  50 P for receiving the positive target voltage V TGT-P . The equalizer circuit  40  also includes a voltage output  52  that outputs the equalized target voltage V TGT-E  corresponding to the differential target voltage V TGT . The equalizer tuning circuit  46  is coupled between the voltage input  48  and the voltage output  52 . 
     As discussed in detail below, the equalizer circuit  40  is configured to equalize the differential target voltage V TGT  based on the second-order complex-zero transfer function H(s) with the real-zero term such that the equalized target voltage V TGT-E  can offset the second-order complex-pole transfer function H(s) with the real-pole term. 
     The equalizer circuit  40  includes a first operational amplifier OPA 1  and a second operational amplifier OPA 2 . The first operational amplifier OPA 1  includes a first inverting input node  54 , a first non-inverting input node  56 , and a first output node  58 . The first inverting input node  54  is coupled to the positive target voltage input  50 P via a first resistor R 1  and a first capacitor C 1 , which are coupled in parallel with one another. A second resistor R 2  is coupled between the first inverting input node  54  and the first output node  58 . The first non-inverting input node  56  is coupled to a ground (GND). The second operational amplifier OP 2  includes a second inverting input node  60 , a second non-inverting input node  62 , and a second output node  64 . The second inverting input node  60  is coupled to the first output node  58  via a second capacitor C 2 . Further, the second inverting input node  60  may be coupled to the negative target voltage input  50 M via a third resistor R 3 , and additionally may be coupled to the second output node  64  via the equalizer tuning circuit  46 . The second non-inverting input node  62  is coupled to the ground (GND). The second output node  64  may be coupled to the voltage output  52 . While the equalizer circuit  40  is shown to only include the voltage output  52 , it may also be possible for the equalizer circuit  40  to include an inverted voltage output node (not shown) in some embodiments such that the equalized target voltage V TGT-E  can be a differential equalized target voltage. Specific details as to how the first operational amplifier OPA 1  and the second operational amplifier OPA 2  can implement a second-order complex-zero transfer function can be found in App&#39;350 and will not be redescribed herein. 
     In one embodiment, the equalizer tuning circuit  46  can be implemented based on a T-network configuration.  FIG. 7  is a schematic diagram providing an exemplary illustration of the equalizer tuning circuit  46  in the equalizer circuit  40  of  FIG. 6 . Common elements between  FIGS. 6 and 7  are shown therein with common element numbers and will not be re-described herein. 
     The equalizer tuning circuit  46  includes a left resistor R L  and a right resistor R R  coupled in series between the negative target voltage input  50 M and the voltage output  52 . The equalizer tuning circuit  46  also includes a tunable capacitor C 0  coupled between a coupling node  66 , which is located between the left resistor R L  and the right resistor R R , and the ground (GND). As shown, the left resistor R L , the right resistor R R , the tunable capacitor C 0 , and the shunt resistor Rs collectively form a T-network. In an embodiment, the equalizer tuning circuit  46  may further include a shunt resistor R S  coupled between the tunable capacitor C 0  and the ground (GND). 
     With reference back to  FIG. 6 , by incorporating the equalizer tuning circuit  46  as shown in  FIG. 7 , the equalizer circuit  40  can realize the second-order complex-zero transfer function H(s) with the real-zero term as expressed in equation (Eq. 4) below. 
     
       
         
           
             
               
                 
                   
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                                   s 
                                 
                               
                               ) 
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     4 
                   
                   ) 
                 
               
             
           
         
       
     
     As shown in the equation (Eq. 4), the transfer function H(s) includes a second-order complex-zero term 
     
       
         
           
             [ 
             
               1 
               + 
               
                 
                   ( 
                   
                     
                       R 
                       3 
                     
                     * 
                     
                       
                         R 
                         2 
                       
                       
                         R 
                         1 
                       
                     
                     * 
                     
                       C 
                       2 
                     
                   
                   ) 
                 
                 * 
                 s 
                 * 
                 
                   ( 
                   
                     1 
                     + 
                     
                       
                         R 
                         1 
                       
                       * 
                       
                         C 
                         1 
                       
                       * 
                       s 
                     
                   
                   ) 
                 
               
             
             ] 
           
         
       
     
     and a real-zero term 
     
       
         
           
             
               [ 
               
                 1 
                 + 
                 
                   
                     
                       C 
                       0 
                     
                     ⁡ 
                     
                       ( 
                       
                         
                           
                             R 
                             L 
                           
                           * 
                           
                             R 
                             R 
                           
                         
                         
                           
                             R 
                             L 
                           
                           + 
                           
                             R 
                             R 
                           
                         
                       
                       ) 
                     
                   
                   * 
                   s 
                 
               
               ] 
             
             . 
           
         
       
     
     As such, the transfer function H(s) realized by the equalizer circuit  40  can effectively offset the second-order complex-pole transfer function H(s) with the real-pole, as realized by the equivalent trace inductance L TRACE  and the equivalent inductance L ETIC . 
     Moreover, the equation (Eq. 4) shows that it is possible to change the real-zero term 
     
       
         
           
             [ 
             
               1 
               + 
               
                 
                   
                     C 
                     0 
                   
                   ⁡ 
                   
                     ( 
                     
                       
                         
                           R 
                           L 
                         
                         * 
                         
                           R 
                           R 
                         
                       
                       
                         
                           R 
                           L 
                         
                         + 
                         
                           R 
                           R 
                         
                       
                     
                     ) 
                   
                 
                 * 
                 s 
               
             
             ] 
           
         
       
     
     by changing a capacitance of the adjustable capacitor C 0 . In this regard, in a non-limiting example, the equalizer circuit  40  can be configured to further include a control circuit  68  and a lookup table (LUT)  70  to statically or dynamically adjust the real-zero term 
     
       
         
           
             [ 
             
               1 
               + 
               
                 
                   
                     C 
                     0 
                   
                   ⁡ 
                   
                     ( 
                     
                       
                         
                           R 
                           L 
                         
                         * 
                         
                           R 
                           R 
                         
                       
                       
                         
                           R 
                           L 
                         
                         + 
                         
                           R 
                           R 
                         
                       
                     
                     ) 
                   
                 
                 * 
                 s 
               
             
             ] 
           
         
       
     
     via the tunable capacitor C 0 . 
     In an embodiment, the LUT  70  may be preconfigured to establish a correlation between various capacitance values of the tunable capacitor C 0  and various modulation bandwidth of the RF signal  38 . In this regard, when the control circuit  68 , which can be a field-programmable gate array (FPGA) as an example, receive the differential target voltage V TGT  (e.g., the negative target voltage V TGT-M  and/or the positive target voltage V TGT-P ) indicating a specific modulating bandwidth of the RF signal  38 , the control circuit  68  may retrieve a respective capacitance from the LUT  70  corresponding to the specific modulation bandwidth and set the tunable capacitor C 0  (e.g., via a control signal  72 ) to the respective capacitance retrieved from the LUT  70 . As a result, it is possible to dynamically change the real-zero term 
     
       
         
           
             [ 
             
               1 
               + 
               
                 
                   
                     C 
                     0 
                   
                   ⁡ 
                   
                     ( 
                     
                       
                         
                           R 
                           L 
                         
                         * 
                         
                           R 
                           R 
                         
                       
                       
                         
                           R 
                           L 
                         
                         + 
                         
                           R 
                           R 
                         
                       
                     
                     ) 
                   
                 
                 * 
                 s 
               
             
             ] 
           
         
       
     
     between, for example, burst of symbols or frames. 
     Alternative to implementing the equalizer tuning circuit  46  based on the T-network configuration as shown in  FIG. 7 , it is also possible to implement the equalizer tuning circuit  46  based on a π-network configuration. In this regard,  FIGS. 8A and 8B  are schematic diagrams providing exemplary illustrations of alternative implementations of the equalizer tuning circuit  46  in  FIG. 7 . 
       FIG. 8A  is a schematic diagram providing an exemplary illustration of an equalizer tuning circuit  46 A configured according to an alternative embodiment of the present disclosure to realize a transfer function H(s) including a real-zero term. The equalizer tuning circuit  46 A can be functionally equivalent to the equalizer tuning circuit  46  in  FIG. 7  without the shunt resistor R S . As illustrated in  FIG. 8A , the equalizer tuning circuit  46 A is configured according to a π-network configuration that includes impedance Z a , Z b , and Z c . The impedance Z a , Z b , and Z c  can be determined based on equations (Eq. 5.1-5.3) below. 
     
       
         
           
             
               
                 
                   
                     Z 
                     a 
                   
                   = 
                   
                     
                       
                         Z 
                         ⁢ 
                         
                           R 
                           L 
                         
                         * 
                         
                           ZR 
                           R 
                         
                       
                       + 
                       
                         Z 
                         ⁢ 
                         
                           R 
                           R 
                         
                         * 
                         
                           ZC 
                           0 
                         
                       
                       + 
                       
                         Z 
                         ⁢ 
                         
                           R 
                           L 
                         
                         * 
                         
                           ZC 
                           0 
                         
                       
                     
                     
                       Z 
                       ⁢ 
                       
                         R 
                         L 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     5.1 
                   
                   ) 
                 
               
             
             
               
                 
                   
                     Z 
                     b 
                   
                   = 
                   
                     
                       
                         Z 
                         ⁢ 
                         
                           R 
                           L 
                         
                         * 
                         
                           ZR 
                           R 
                         
                       
                       + 
                       
                         Z 
                         ⁢ 
                         
                           R 
                           R 
                         
                         * 
                         
                           ZC 
                           0 
                         
                       
                       + 
                       
                         Z 
                         ⁢ 
                         
                           R 
                           L 
                         
                         * 
                         
                           ZC 
                           0 
                         
                       
                     
                     
                       Z 
                       ⁢ 
                       
                         R 
                         R 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     5.2 
                   
                   ) 
                 
               
             
             
               
                 
                   
                     Z 
                     c 
                   
                   = 
                   
                     
                       
                         Z 
                         ⁢ 
                         
                           R 
                           L 
                         
                         * 
                         
                           ZR 
                           R 
                         
                       
                       + 
                       
                         Z 
                         ⁢ 
                         
                           R 
                           R 
                         
                         * 
                         
                           ZC 
                           0 
                         
                       
                       + 
                       
                         Z 
                         ⁢ 
                         
                           R 
                           L 
                         
                         * 
                         
                           ZC 
                           0 
                         
                       
                     
                     
                       ZC 
                       0 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     5.3 
                   
                   ) 
                 
               
             
           
         
       
     
     In the equations (Eq. 1-Eq. 3) above, ZR L , ZR R , and ZC 0  represent equivalent impedance of the left resistor R L , the right resistor R R , and the tunable capacitor C 0  in  FIG. 7 , respectively. In an embodiment, the impedance Z c  can be modeled by an equivalent resistor R EQ  (R EQ =R L +R R ) coupled in series to an equivalent inductor L EQ  (L EQ =R L *R R *C 0 ). The equalizer tuning circuit  46  defines a real-zero term [(R L +R R )+(R L −R R )*C 0 *s]. 
       FIG. 8B  is a schematic diagram providing an exemplary illustration of an equalizer tuning circuit  46 B configured according to another alternative embodiment of the present disclosure to realize a real-zero term and a real-pole transfer function. The equalizer tuning circuit  46 B can be functionally equivalent to the equalizer tuning circuit  46  in  FIG. 7  with the shunt resistor R S . The equalizer tuning circuit  46 B defines a real-zero term [(R L +R R )+(R L *R R +(R L +R R )*R S )*C 0 *s] and a real-pole term [1+R S *C 0 *s]. 
     With reference back to  FIG. 4 , the voltage amplifier circuit  34  can include a voltage amplifier  74  (denoted as “VA”) coupled in series to an offset capacitor C OFF . The voltage amplifier  74  is configured to generate an initial ET voltage V AMP  based on the equalized target voltage V TGT-E . The offset capacitor C OFF  may be charged by a low-frequency current IDC to raise the initial ET voltage V AMP  by an offset voltage V OFF  to generate the ET voltage V CC  (V CC =V AMP +V OFF ). The voltage amplifier circuit  34  may include a feedback path  76 , which can provide a feedback of the ET voltage V CC  to the voltage amplifier  74 . 
     The power management circuit  28  can include a multi-level charge pump (MCP)  78  coupled in series to a power inductor  80 . The MCP  78  may be controlled (e.g., based on the differential target voltage V TGT ) to generate a low-frequency voltage V DC  at multiple levels based on a battery voltage V BAT . For example, the MCP  78  may operate in a buck mode to generate the low-frequency voltage V DC  at 0 V or V BAT . The MCP  78  may also operate in a boost mode to generate the low-frequency voltage V DC  at 2*V BAT . The power inductor  80  is configured to induce the low-frequency current IDC based on the low-frequency voltage V DC . 
     The power management circuit  28  may further include a processing circuit  82  coupled in between the equalizer circuit  40  and the voltage amplifier circuit  34 . The processing circuit  82  may perform further signal processing (e.g., anti-aliasing) on the equalized target voltage V TGT-E  prior to providing the equalized target voltage V TGT-E  to the voltage amplifier circuit  34 . 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.