Patent Publication Number: US-9898028-B2

Title: Low voltage, highly accurate current mirror

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims benefit of U.S. Provisional Patent Application Ser. No. 62/082,266, filed Nov. 20, 2014 and entitled “LOW VOLTAGE, HIGHLY ACCURATE CURRENT MIRROR,” which is herein incorporated by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to a low voltage current mirror with a highly accurate current ratio. 
     BACKGROUND 
     A current mirror is a type of current amplifier that provides a high impedance output current proportional to an input current. The output current is typically used to drive a load for high gain. A simple current mirror generally consists of a single input and a single output transistor pair, with the gate electrodes of the pair being tied together and to an input voltage node at the drain of the input transistor. The sources of the transistors are connected to a reference voltage node that is common to both transistors. The drain and gate of the input transistor are connected to a current source that provides a quiescent reference current. Because the input and output transistors have their gates and sources tied together, a corresponding output current arises in the conduction path of the output transistor. Generally, the input and output transistors are identical and there is a substantially unity gain in the current. Such current mirrors are commonly used to provide active loads in high gain amplifier stages. 
     SUMMARY 
     Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror circuit, which may be used for distributed current sensing in an integrated circuit (IC), for example. 
     Certain aspects of the present disclosure provide a current mirror. The current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. For certain aspects, an input node between the first and second pairs of transistors is configured to receive an input current for the current mirror, and an output node at the first pair of transistors is configured to sink an output current for the current mirror that is proportional to the input current 
     According to certain aspects, the switching network is configured to periodically (or randomly) interchange connections between the second pair of transistors and the third pair of transistors. 
     According to certain aspects, the switching network includes a dynamic element matching (DEM) circuit. 
     According to certain aspects, the current mirror further includes a current source configured to supply a bias current to a transistor in the first pair of transistors. The bias current may be negligible compared to the input current. For certain aspects, the current mirror may also include a source follower coupled to the current source and to the transistor in the first pair of transistors. The source follower may include a first transistor and a second transistor in cascode with the first transistor. In this case, a gate of the first transistor may be coupled to the current source and to a drain of the transistor in the first pair of transistors. A source of the first transistor may be coupled to at least one of a drain of the second transistor or to a gate of the second transistor. For certain aspects, the source follower further includes at least one of: a first capacitor connected between the gate of the first transistor and the source of the first transistor; or a second capacitor connected between the gate of the first transistor and a source of the transistor in the first pair of transistors, wherein the source of the transistor in the first pair of transistors is coupled to the input node. The gate of the second transistor may be coupled to gates of the third pair of transistors. For certain aspects, a source of the transistor in the first pair of transistors is coupled to the input node, and a drain of another transistor in the first pair of transistors is coupled to the output node. For certain aspects, the current source is coupled to a first power supply node, and the third pair of transistors is coupled to a second power supply node having a lower voltage than the first power supply node. 
     According to certain aspects, the first transistor pair includes a first transistor and a second transistor, and a gate of the first transistor is coupled to a gate of the second transistor. For certain aspects, the second pair of transistors includes a third transistor and a fourth transistor, a gate of the third transistor is coupled to a gate of the fourth transistor, a source of the first transistor is coupled to a drain of the third transistor, and a source of the second transistor is coupled to a drain of the fourth transistor. In this case, the third pair of transistors may include a fifth transistor and a sixth transistor, a gate of the fifth transistor may be coupled to a gate of the sixth transistor, and a first size ratio between the third transistor and the fourth transistor may equal a second size ratio between the fifth transistor and the sixth transistor. A third size ratio between the first transistor and the second transistor may be different from the first size ratio and the second size ratio. The third size ratio may be based on a ratio between a bias current of the current mirror and the output current of the current mirror, a drain of the first transistor may be configured to receive the bias current, and a drain of the second transistor may be configured to sink the output current. In this case, the bias current may be negligible compared to the input current, and a source of the first transistor and a drain of the third transistor may be coupled to the input node. In a first configuration of the switching network, a source of the third transistor may be coupled to a drain of the fifth transistor, and a source of the fourth transistor may be coupled to a drain of the sixth transistor. In a second configuration of the switching network, the source of the third transistor may coupled to the drain of the sixth transistor, and the source of the fourth transistor may be coupled to the drain of the fifth transistor. For certain aspects, the first transistor and the third transistor are in an input and bias currents branch of the current mirror, and the second transistor and the fourth transistor are in an output current branch of the current mirror. The fourth transistor may have a smaller size than the third transistor. The second transistor may have a larger size than the first transistor. 
     According to certain aspects, a ratio between the input current of the current mirror and the output current of the current mirror is 15:1. However, other current ratios may be used instead. 
     According to certain aspects, a transistor in the second pair of transistors separates the input node from the switching network. 
     According to certain aspects, the input node, the second pair of transistors, the switching network, and the third pair of transistors operate in a low voltage domain, and the output node and the first pair of transistors operate in a high voltage domain. In this case, the second pair of transistors may be configured to reduce charge sharing between the low voltage domain and the high voltage domain. 
     Certain aspects of the present disclosure provide an apparatus for generating an output current that is proportional to an input current. The apparatus generally includes means for receiving the input current; means for generating a bias current; first means for sinking the output current, wherein the output current is proportional to the bias current; second means for sinking the output current in cascode with the first means, wherein the output current is proportional to a sum of the input current and the bias current; third means for sinking the output current; and means for interchanging connections between the second means and the third means, wherein the means for receiving the input current is connected between the first means and the second means. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects. 
         FIG. 1  illustrates distributed on-chip current sensing, in accordance with certain aspects of the present disclosure. 
         FIG. 2  is an example circuit diagram for a current mirror, in accordance with certain aspects of the present disclosure. 
         FIG. 3  is an example circuit diagram that adds a source follower to the current mirror of  FIG. 2 , in accordance with certain aspects of the present disclosure. 
         FIG. 4  is an example circuit diagram for a current mirror with a 15:1 input-to-output-current ratio, in accordance with certain aspects of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Various aspects of the present disclosure are described below. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein is merely representative. Based on the teachings herein, one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein. Furthermore, an aspect may comprise at least one element of a claim. 
     The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. 
     EXAMPLE CURRENT MIRROR 
     In many applications, it may be desirable to measure the actual, real-time current consumption of various blocks (e.g., a central processing unit (CPU), digital signal processor (DSP), etc.) of an integrated circuit (IC). Current sensing of these blocks provides a tool for ever-increasing power management challenges, and may be used as a diagnostic tool or as an active control for power limits management. 
       FIG. 1  illustrates an IC  100  (also referred to as a “chip”) having multiple current sensors  110 , which are distributed in various parts of the IC. In this distributed on-chip current sensing scheme, the IC  100  includes relatively large currents coming from a low-voltage domain that are to be measured with high accuracy at a central sensing interface  120 . Often a high-voltage source is available on the sensing interface side of the IC  100 , but the currents are provided from the low-voltage domain. In order to measure such currents, a current mirror may be utilized, preferably a current mirror with a sufficiently accurate current ratio, low power consumption, and a small area penalty. 
     There are multiple issues with conventional current mirrors. For example, due to low available voltage headroom for the mirror in some ICs, certain current mirror circuits may not be functional at all. For example, the power supply voltage (Vdd) in the IC  100  can be as low as 630 mV, and the current-times-resistance (IR) drop in routing from the sensor  110  to the sensing interface  120  may be as high as 150 mV. Moreover, with future technologies, Vdd and the transistor threshold voltage (Vth) both are trending lower, but the IR drop stays the same, so the situation becomes more severe. With respect to area, the size of a conventional current mirror circuit is typically large so that the circuit can handle large currents with minimum gate-to-source voltage (Vgs), which produces large area overhead. Also in a typical current mirror, the current ratio may not be accurate due to mismatch in the transistors. Furthermore, the output impedance of a conventional current mirror is rather limited, typically due to area considerations that avoid large length devices. Adding another row of transistors in cascode is not practical because this limits the voltage headroom even more. 
     In an attempt to address at least some of these problems in a cascoded current mirror circuit, a small bias current may be injected to the drain of the input transistor, and the input current may be provided at the source of this input transistor. In this case, the input voltage can go down to the drain-to-source voltage (Vds) of the other transistor in the input current branch. This change permits low-voltage operation (e.g., threshold voltage (Vth) may be ˜500 mV and Vds may be ˜140 mV). Furthermore, a dynamic element matching (DEM) circuit may be used between the cascoded transistor pairs in an effort to average out the mismatch between transistors. However, a current density mismatch between the bias current transistor and the output current transistor in the current mirror topology may introduce a large error, and the output impedance may not be sufficiently high. 
       FIG. 2  is an example circuit diagram for a current mirror  200 , in accordance with certain aspects of the present disclosure. The current mirror  200  includes a first pair of transistors M 4  and M 5 , a second pair of transistors M 2  and M 3  connected in cascode with the first pair of transistors M 4  and M 5 , a switching network  201  (e.g., a DEM) coupled to the second pair of transistors M 2  and M 3 , and a third pair of transistors M 0  and M 1  coupled to the switching network  201 . Transistor M 4  may function as a bias transistor whose drain is coupled to a bias current source  202  configured to supply a small bias current (I bias ) from a first power supply node (e.g., VDD_High), also referred to as a power supply (or voltage) rail. For certain aspects, the sources of transistors M 0  and M 1  are coupled to a second power supply node  206 , which may have a lower voltage than the first power supply node  204 . For certain aspects, the gates of cascoded transistors M 4  and M 5  are connected together and biased with a bias voltage (V 3 ), as illustrated in  FIG. 2 . Likewise, the gates of the second pair of transistors M 2  and M 3  are connected together and biased with another bias voltage (V 2 ) for certain aspects. For certain aspects, the gates of the third pair of transistors M 0  and M 1  are also connected together and coupled to the drain of transistor M 4 , biased by the current source  202 , as shown. 
     The switching network  201  is configured to interchange connections between the second pair of transistors M 2  and M 3  and the third pair of transistors M 0  and M 1 . For certain aspects, interchanging connections between the pairs of transistors involves switching the source of M 2  from being connected with the drain of M 0  to being connected with the drain of M 1 , or vice versa. In this case, interchanging connections with the switching network  201  also involves switching the source of M 3  from being connected with the drain of M 1  to being connected with the drain of M 0 , or vice versa. These connections may be interchanged periodically (according to a periodic control signal, such as a clock) or randomly, for example. 
     In  FIG. 2 , an input node  208  between the first and second pairs of transistors is configured to receive an input current (I in ) for the current mirror  200 . As described above, I bias  may be small, which may mean that I bias  is negligible compared to I in . For certain aspects, the input node  208  is coupled to the source of transistor M 4  and to the drain of transistor M 2 . An output node  210  at the first pair of transistors is configured to sink an output current (I out ) for the current mirror  200 , where I out  is proportional to I in . For certain aspects, the output node  210  is coupled to the drain of the transistor M 5 . 
     Having a second row of cascoded transistors M 2  and M 3  in between the switching network  201  and the first row of cascoded transistors M 4  and M 5  permits the upper devices in  FIG. 2  being high voltage (HV) and the lower devices being low voltage (LV), as shown. This hybrid low-voltage/high-voltage solution eliminates the issues described above with conventional current mirrors. The current mirror  200  in  FIG. 2  tolerates low input voltages, provides high output impedance, and achieves low area. The second row of cascoded transistors M 2  and M 3  isolates the switching network  201  to eliminate the charge sharing from two different voltages. Transistor M 5  increases the output resistance of the current mirror  200 . The size ratio (K) of M 5 :M 4  is decided based on a typical ratio of I out  to I bias , for example. For certain aspects, the current mirror  200  utilizes an N:1 low-voltage DEM for matching between transistors M 0  and M 1 . The size ratio (N) of M 0 :M 1  (as well as M 2 :M 3 ) is decided, for example, based on the desired ratio of I out  to I in  for the current mirror  200 . For certain aspects as an example, N is equal to 15. 
     For certain aspects, the current mirror  200  of  FIG. 2  is capable of handling input currents ranging from at least 40 μA to 2.2 mA. Furthermore, the current mirror  200  operates with a minimum power supply voltage of 630 mV, for example, which typically is too low for conventional current mirrors. 
       FIG. 3  is an example circuit diagram illustrating the addition of a source follower to the current mirror  200  of  FIG. 2 , in accordance with certain aspects of the present disclosure. The source follower in  FIG. 3  includes transistors M 6  and M 8 , which are connected in cascode. The source follower serves to shift the mirror voltage (at the node  302  connected to the drain of M 4  and the bias current source  202 ) to a higher voltage. For certain aspects, the gate of transistor M 8  is coupled to node  302 , and the source of transistor M 8  is coupled to at least one of the drain or the gate of transistor M 6 . For certain aspects, the drain and the gate of transistor M 6  are shorted together. 
     For certain aspects, capacitors C 1  and/or C 2  are added for stability. Capacitor C 1  may be coupled to the node  302  and to at least one of the source of transistor M 8 , the gate of transistor M 6 , the drain of transistor M 6 , or the gate of transistor M 0 . Capacitor C 2  may be coupled to the node  302  and to the input node  208 . 
     According to certain aspects, the cascode bias voltage generator  304  is used to generate the bias voltages V 3  and V 2  for the first row of cascoded transistors M 4  and M 5  and the second row of cascoded transistors M 2  and M 3 , respectively. For certain aspects, the cascode bias voltage generator  304  is coupled to the drain of transistor M 7 , which may be sized similarly to transistor M 1 . For certain aspects, the source of transistor M 7  is coupled to the second power supply node  206 , and the gate of transistor M 7  is coupled to the gates of transistors M 1 , M 0 , and M 6 , as shown. 
       FIG. 4  is an example circuit diagram for a current mirror  400  with a 15:1 input-to-output-current ratio (I in /I out ), in accordance with certain aspects of the present disclosure. The circuit is similar to the current mirror  200  of  FIG. 2 , where the size ratios of M 0 :M 1  and M 2 :M 3  are both 15:1. Resistors R 1  and R 2  are added for biasing the gates of the first, second, and third transistor pairs in conjunction with the bias current supplied by the bias current source  202 . 
     The various operations or methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering. 
     For example, means for receiving an input current may comprise a terminal or an input node (e.g., input node  208  as depicted in  FIG. 2 ). Means for generating a bias current may include a current source (e.g., the bias current source  202  as illustrated in  FIG. 2 ). First, second, and/or third means for sinking an output current may each include a pair of transistors (e.g., transistors M 4  and M 5 , transistors M 2  and M 3 , or transistors M 0  and M 1  as shown in  FIG. 2 ). Means for interchanging connections between the second means and the third means may comprise a switching network (e.g., the switching network  201  as illustrated in  FIG. 2 ). 
     As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like. 
     As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c). 
     The various illustrative logical blocks, modules and circuits described in connection with the present invention may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. 
     The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims. 
     The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a wireless node. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the physical (PHY) layer. In the case of a user terminal  120  (see  FIG. 1 ), a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further. 
     The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may be implemented with an ASIC with the processor, the bus interface, the user interface in the case of an access terminal), supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more FPGAs, PLDs (Programmable Logic Devices), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system. 
     It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.