Patent Publication Number: US-8117390-B2

Title: Updating partial cache lines in a data processing system

Description:
This invention was made with United States Government support under Agreement No. HR0011-07-9-0002 awarded by DARPA. THE GOVERNMENT HAS CERTAIN RIGHTS IN THE INVENTION. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to data processing and, in particular, to handling updates to partial cache lines in a data processing system. 
     2. Description of the Related Art 
     A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of processor-addressable memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores. 
     Cache memories are commonly utilized to temporarily buffer cache lines that might be accessed by a processor in order to speed up processing by reducing access latency introduced by having to load needed data and instructions from memory. In some multiprocessor (MP) systems, the cache hierarchy includes at least two levels. The level one (L1), or upper-level cache is usually a private cache associated with a particular processor core and cannot be directly accessed by other cores in an MP system. Typically, in response to a memory access instruction such as a load or store instruction, the processor core first accesses the directory of the upper-level cache. If the requested cache line is not found in the upper-level cache, the processor core then accesses one or more lower-level caches (e.g., level two (L2) or level three (L3) caches) for the requested cache line. 
     With some workloads, updates are performed to scattered locations in memory. To perform each such update, a conventional cache hierarchy retrieves a full cache line of data from system memory and populates one or more levels of cache with the cache line. It is recognized herein that it is wasteful and inefficient to retrieve the entire cache line when an update will only be made to a small portion of the cache. In addition, placing the line in the cache is also wasteful since that line is unlikely to be accessed again in the near future in such workloads. 
     SUMMARY OF THE INVENTION 
     According to one embodiment, a processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing Of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a high level block diagram of an exemplary embodiment of a multiprocessor data processing system in accordance with one embodiment; 
         FIG. 2A  is a more detailed block diagram of an exemplary processing unit of the data processing system of  FIG. 1  in accordance with one embodiment; 
         FIG. 2B  is a more detailed block diagram of an exemplary embodiment of a processor core and associated cache hierarchy from  FIG. 2A ; 
         FIG. 3  illustrates an exemplary format of one of the directory entries in the L3 directory of  FIG. 2B ; 
         FIG. 4  is a high level logical flowchart of an exemplary process of prefetching partial cache line in one embodiment; 
         FIG. 5  is a high level logical flowchart of an exemplary process of servicing a core memory access request in one embodiment; 
         FIG. 6  is a high level logical flowchart of an exemplary process by which an L3 cache processes a snooped command on the interconnect fabric in one embodiment; and 
         FIG. 7  a high level logical flowchart of an exemplary process by which an L2 cache processes a snooped command on the interconnect fabric in one embodiment. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT(S) 
     With reference now to the figures and, in particular, with reference to  FIG. 1 , there is illustrated a high level block diagram of an exemplary embodiment of a multiprocessor data processing system. As shown, data processing system  100  includes multiple processing nodes  102   a,    102   b  for processing data and instructions. Processing nodes  102   a,    102   b  are coupled to a system interconnect  110  for conveying address, data and control information. System interconnect  110  may be implemented, for example, as a bused interconnect, a switched interconnect or a hybrid interconnect. 
     In the depicted embodiment, each processing node  102  is realized as a multi-chip module (MCM) containing four processing units  104   a - 104   d,  each preferably realized as a respective integrated circuit. The processing units  104   a - 104   d  within each processing node  102  are coupled for communication by a local interconnect  114 , which, like system interconnect  110 , may be implemented with one or more buses and/or switches. Local interconnects  114  and system interconnect  110  together form an interconnect fabric, which preferably supports concurrent communication of operations of differing broadcast scopes. For example, the interconnect fabric preferably supports concurrent communication of operations limited in scope to a single processing node  102  and operations broadcast to multiple processing nodes  102 . 
     The devices coupled to each local interconnect  114  include not only processing units  104 , but also one or more system memories  108   a - 108   d.  Data and instructions residing in system memories  108  can generally be accessed and modified by a processor core ( FIG. 2A ) in any processing unit  104  in any processing node  102  of data processing system  100 . In alternative embodiments of the invention, one or more system memories  108  can be coupled to system interconnect  110  rather than a local interconnect  114 . 
     Those skilled in the art will appreciate that data processing system  100  can include many additional unillustrated components, such as peripheral devices, interconnect bridges, non-volatile storage, ports for connection to networks or attached devices, etc. Because such additional components are not necessary for an understanding of the present invention, they are not illustrated in  FIG. 1  or discussed further herein. It should also be understood, however, that the enhancements provided by the present invention are applicable to data processing systems of diverse architectures and are in no way limited to the generalized data processing system architecture illustrated in  FIG. 1 . 
     Referring now to  FIG. 2A , there is depicted a more detailed block diagram of an exemplary processing unit  104  in accordance with one embodiment. In the depicted embodiment, each processing unit  104  includes multiple instances of a processor core and associated cache hierarchy, which are collectively identified by reference numeral  200 . In the depicted embodiment, each processing unit  104  also includes an integrated memory controller (IMC)  206  that controls read and write access to one or more of the system memories  108   a - 108   d  within its processing node  102  in response to requests received from processor cores and operations snooped on the local interconnect  114 . 
     Each processing unit  104  also includes an instance of coherence management logic  210 , which implements a portion of the distributed snoop-based coherency signaling mechanism that maintains cache coherency within data processing system  100 . In general, coherence management logic  210  receives partial responses provided by each participant in a interconnect operation (e.g., cache memories and IMCs  206 ) that snoops a request on the interconnect fabric and compiles the partial responses to determine an overall systemwide coherence response (a “a combined response”) for the request. In addition, each processing unit  104  includes an instance of interconnect logic  212  for selectively forwarding communications between its local interconnect  114  and system interconnect  110 . Finally, each processing unit  104  includes an integrated I/O (input/output) controller  214  supporting the attachment of one or more I/O devices, such as I/O device  216 . I/O controller  214  may issue operations on local interconnect  114  and/or system interconnect  110  in response to requests by I/O device  216 . 
     With reference now to  FIG. 2B  is a more detailed block diagram of an exemplary embodiment of a processor core and associated cache hierarchy  200  from  FIG. 2A . As illustrated, a processor core  220  includes an instruction sequencing unit  222  that obtains and orders instructions for execution by one or more execution units  224 . In a superscalar embodiment such as that illustrated, the EUs  224  may include one or more execution units for executing arithmetic and logic operations, as well as a load-store unit (LSU)  226  that executes memory access instructions, including load-type instructions that load data from memory into a general purpose register file (GPRF)  228  and store-type instructions that store data from GPRF  228  into memory. GPRF  228  thus holds the working data set of processor core  220 , and LSU  225  is utilized to move the data set to and from memory. 
     To provide low access latency to the data set of processor core  220 , processor core  220  is supported by cache memory. In one exemplary embodiment, the cache memory is arranged in a multi-level hierarchy including a store-through level one (L1) cache  228  within processor core  220 , a store-in level two (L2) cache  230 , and a L3 cache  232 . In some embodiments, L3 cache  232  is utilized as a victim cache for L2 cache  230  and accordingly is filled by cache lines evicted from L2 cache  230 . In some embodiments, the contents of L3 cache  232  are not exclusive of the contents of L2 cache  230 , meaning that a given cache line may be held concurrently in L2 cache  230  and L3 cache  232 . In order to decrease average access latency, LSU  225  may also execute prefetch instruction that causes data likely to be accessed by processor core  220  to be pre-loaded in the cache memory hierarchy of processor core  220  in advance of a demand access. 
     Although hereafter it will be assumed that the cache hierarchy includes only three levels of cache, those skilled in the art will appreciate that alternative embodiments may include additional levels (L4, L5, etc.) of on-chip or off-chip in-line or lookaside cache, which may be fully inclusive, partially inclusive, or non-inclusive of the contents the upper levels of cache. Further, any of the various levels of the cache hierarchy may be private to a particular processor core  220  or shared by multiple processor cores  220 . For example, in some implementations, the cache hierarchy includes L1 and L2 cache  228 ,  230  private to each processor core  220 , with multiple of the L2 caches  230  sharing a common L3 victim cache  232 . 
       FIG. 2B  further illustrates some principal elements of L2 cache  230  and L3 cache  232  relevant to the embodiments described herein. In particular, L2 cache  230  includes a data array  240  for temporarily holding copies of data and instructions residing in system memory  108  and a directory  242  of the contents of data array  302 . Assuming data array  240  and directory  242  are set associative as is conventional, memory locations in system memories  108  are mapped to particular congruence classes within data array  240  utilizing predetermined index bits within the system memory (real) addresses. The particular cache lines stored within data array  240  are recorded in directory  242 , which contains one directory entry for each cache line. While not expressly depicted in  FIG. 2B , it will be understood by those skilled in the art that each directory entry in directory  242  includes various fields, for example, a tag field that identifies the real address of the cache line held in the corresponding cache line of data array  240 , a LRU (Least Recently Used) field indicating a replacement order for the cache line with respect to other cache lines in the same congruence class, inclusivity bits indicating whether the cache line is held in the associated L1 cache  228 , and a state field that indicate the coherence state of the cache line. The coherency state indicates whether a valid copy of the cache line is present in data array  240  and if so, a level of read and/or write permission for the cache line. There are several well-known coherency protocols that can be employed including the Modified, Exclusive, Shared, Invalid (MESI) protocol and variants thereof. The technique of updating partial cache lines disclosed herein can be practiced with any coherence protocol capable of indicating exclusivity, namely, that only one cache currently holds a copy of a given cache line and that the copy is not modified relative to system memory  108 . 
     L2 cache  230  also includes a store queue (STQ)  244  that receives and processes store requests received from the associated processor core  220  via core-to-L2 interface  227 . For example, STQ  244  buffers and gathers the data of multiple store requests targeting the same cache line so that a single update to that cache line can be performed. STQ  244  is coupled to a merge buffer  246  that merges updates held by STQ  244  for a target cache line are merged with the current image of that cache line. In a conventional store operation, the current image of the cache line is retrieved from data array  240  (after retrieving it from the associated L3 cache  232 , another cache  230  or  232 , or system memory  108  if it was not already present in data array  240 ) and the specified update(s) is/are merged with the image and written back to data array  240 . 
     L2 cache  230  further includes control logic (often referred to collectively as a cache controller) to manage the flow of data and coherence information to, from and within L2 cache  230 . In the depicted embodiment, such control logic includes one or more Read-Claim (RC) machines  250  for independently and concurrently servicing load-type (LD), store-type (ST), a prefetch (PF) requests received from the affiliated processor core  220 . RC machines  250  service such commands by, among other actions, retrieving data into L2 cache  230  and, if necessary, supplying data to processor core  220  via core-to-L2 interface  227 . 
     As will be appreciated, the servicing of memory access requests by RC machines  250  may require the replacement or invalidation of cache lines within data array  240 . Accordingly, L2 cache  230  includes one or more CO (castout) machines  252  that manage the eviction of cache lines from data array  240 . Preferentially, valid cache lines are evicted to the associated L3 cache  232 , but may also be transmitted to system memory  108 . 
     L2 cache  230  further includes one or more SN (snoop) machines  254  responsible for monitoring (“snooping”) commands on fabric interface  259 , providing partial responses as necessary on the interconnect fabric, and updating L2 cache  230  as necessary to maintain cache coherency. In general, the partial responses indicate the coherence state of a target cache line of a command with respect to L2 cache  230  and whether and how it can service the snooped command. To process a snooped command, a SN machine  254 , among other operations, may alter the entry in directory  242  for the target cache line, may provide a copy of the target cache line to a cache that issued the command, and may push a target cache line to system memory  108 . 
     L2 cache  230  also has an L2-to-L3 interface that supports communication of commands and data from L2 cache  230  to L3 cache  232  and the return of data and status/coherence information from L3 cache  232  to L2 cache  230 . 
     Like L2 cache  230 , L3 cache  232  includes a data array  260  for temporarily holding copies of data and instructions residing in system memory  108  and a directory  242  of the contents of data array  302 . Data array  260  and directory  262  are preferably structured similar to data array  240  and directory  242  of L2 cache  230 , which are described above. 
     L3 cache  232  includes control logic (often referred to collectively as a cache controller) to manage the flow of data and coherence information to, from and within L2 cache  232 . In the depicted embodiment, such control logic includes one or more RD (read) machines  270  responsible for returning data from L3 cache  232  to L2 cache  230 . In general, load-type or store-type operations that miss in L2 cache  230  are forwarded to L3 cache  232 . If the operation hits in L3 cache  232 , the RD machine  270  returns a hit status to L2 cache  230  and forwards data to L2 cache  230  over L2-to-L3 interface  257 . 
     L3 cache  232  further includes one or more SN (snoop) machines  274  responsible for monitoring (“snooping”) commands on fabric interface  279 , providing partial responses as necessary on the interconnect fabric, and updating L3 cache  232  as necessary to maintain cache coherency. In general, the partial responses indicate the coherence state of a target cache line of a command with respect to L3 cache  232  and whether and how it can service the snooped command. To process a snooped command, a SN machine  274 , among other operations, may alter the entry in directory  262  for the target cache line, may provide a copy of the target cache line to a cache that issued the command, and may push a target cache line to system memory  108 . 
     L3 cache  232  also contains one or more PF (prefetch) machines  272  utilized to prefetch data from system memory  108  into L3 cache  232 . An L2 RC machine  250  can issue prefetch commands over the L2-to-L3 interface to instruct L3 cache  232  to prefetch data into L3 cache  232 . 
     To process a normal read request generated by execution by LSU  225  of a load instruction, a lookup is performed to determine if L1 cache  228  holds a copy of the target cache line. If so, requested data from the target cache line is returned from L1 cache  228 , and the read request is complete. If the target cache line is not present in L1 cache  228  (an L1 cache miss occurs), a read request is issued to L2 cache  230  over core-to-L2 interface  227 . In response to receipt of the read request, an RC machine  250  determines if the target cache line is present in L2 cache  230 . If so, the RC machine  250  returns data from the target cache line to processor core  220 , which generally populates L1 cache  228  with the data and places the requested data into GPRF  226 . 
     If the read request misses in L2 cache  230 , the RC machine  250  consults L3 cache  232  via L2-to-L3 interface to determine if L3 cache  232  holds the target cache line. If so, a RD machine  270  returns the target cache line to L2 cache  230 , which populates data array  240  (performing a castout of a cache line, if necessary, utilizing a CO machine  252 ) and directory  242 . The RC machine  250  then returns the target cache line to processor core  220 , which populates L1 cache  228  and places the requested data in GPRF  226 . 
     Finally, if the target cache line of the read request is not present in L3 cache  232 , L2 RC machine  250  issues a read command on the interconnect fabric to retrieve a copy of the target cache line either from another cache  230 ,  232  or from system memory  108 . Coherency responses on the interconnect fabric indicate if the read command was successful, and if so, the source of the target cache line. 
     To process a normal store request generated by execution by LSU  225  of a store instruction, the processor core first determines if the target cache line is present in L1 cache  228 . If so, the target cache line is updated in L1 cache  228 , and the store request is forwarded to STQ  244  and then dispatched to a RC machine  250  for servicing. Data array  240  of L2 cache  230  is inclusive of the contents of L1 cache  228 . Consequently, if the target cache line is present in L1 cache  228 , data array  240  of L2 cache  230  also contains the target cache line and is accordingly updated by RC machine  250 . 
     If the store request misses in L1 cache  228 , processor core  220  forwards the store request to STQ  244  and then to an RC machine  250  for servicing. If the store request hits in L2 cache  230 , the RC machine  250  updates L2 cache  230  with the store data. If the store request misses in L2 cache  230 , the RC machine  250  first attempts to obtain the target cache line from L3 cache  232 . If the target cache line is present in L3 cache  232 , a RD machine  270  returns the target cache line to L2 cache  230 , which populates which populates data array  240  (performing a castout of a cache line, if necessary, utilizing a CO machine  252 ) and directory  242 . 
     If the target cache line is not present in L3 cache  232 , the RC machine  250  issues a command on the interconnect fabric to retrieve a copy of the target cache line either from another cache  230 ,  232  or from system memory  108 . Coherency responses on the interconnect fabric indicate if the read command was successful, and if so, the source of the target cache line. The RC machine then updates the target cache line in L2 cache  230  with the data received from processor core  220 . 
     As can be seen from the foregoing, the processing of normal load and store requests entails the displacement and creation of full cache lines at various levels of the cache hierarchy. Typically, this behavior is advantageous due to the fact that recently referenced data is likely to be accessed again in the near future (temporal locality) or nearby data is likely to be referenced in the near future (spatial locality). However, when a workload does not exhibit spatial or temporal locality, retrieving full cache lines and populating L1 and L2 caches  228 ,  230  with these cache lines degrades performance. As appreciated herein, this performance degradation can be alleviated by prefetching partial cache lines from memory and placing them only in one lower level (e.g., L3) cache. Read and store requests that target the partial cache lines can then be serviced without polluting upper level caches (e.g., L1 and L2 caches  228 ,  230 ) with data not likely to again be accessed. 
     With reference now to  FIG. 3 , an exemplary format of one of the directory entries  300  in L3 directory  262  is depicted. In the depicted embodiment, directory entry  300  includes an address tag  308  that indicates the real address of the cache line present in data array  260  at the storage location corresponding to this directory entry  300 . Directory entry  300  further includes valid bits. V 0   302  and V 1   304 , which are used when a partial cache line resides in the corresponding storage location in data array  260  to indicate which half of the cache line is valid in L3 cache  232 . Those skilled in the art will appreciate that with additional valid bits, it would be possible to separately indicate validity for smaller portions of the full cache line. 
     Directory entry  300  further includes a state field  306  that indicates the coherence state of the cache line in the corresponding storage location in data array  260 . Table I below summarizes legal combinations of the states of valid bits  302 ,  304  and coherence states in one exemplary embodiment. In the illustrated embodiment, for efficiency and simplicity partial cache lines are only allowed to be present in L3 cache  232  in an exclusive state (among possibly multiple exclusive states in the coherence protocol). By maintaining partial cache lines in exclusive state(s) only, L3 cache  232  is able to immediately abandon the partial cache line when snooping a request for the full cache line since the partial cache line is not modified relative to system memory  108 . As a further simplification, one preferred embodiment permits partial cache lines to be prefetched only from system memory  108 . This simplification allows the cache coherence protocol to not have to support cache-to-cache intervention of partial cache lines. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                 V0 
                 V1 
                 Coherence State 
               
               
                   
                   
               
             
            
               
                   
                 0 
                 0 
                 Any legal state defined by the coherence protocol 
               
               
                   
                 0 
                 1 
                 Exclusive 
               
               
                   
                 1 
                 0 
                 Exclusive 
               
               
                   
                 1 
                 1 
                 Reserved 
               
               
                   
                   
               
            
           
         
       
     
     Referring now to  FIG. 4 , there is depicted a high level logical flowchart of an exemplary process of prefetching partial cache line in one embodiment. In the illustrated embodiment, a prefetched partial cache line is installed in a lower level cache (e.g., L3 cache  232 ), and subsequent read and store requests targeting the partial cache line can be processed without populating the upper level caches (e.g., L1 and L2 caches  228 ,  230 ) with all or a portion of the target cache line. 
     The process begins at block  400  and then proceeds to block  402 , which depicts a processor core  220  issuing a partial line prefetch request to L2 cache  230 . In response to the partial line prefetch request, L2 cache  230  dispatches a RC machine  250  to service the request. The RC machine  250  speculatively issues a partial line prefetch request to L3 cache  232  via L2-to-L3 interface  257  (block  404 ). 
     At block  406 , each of L2 cache  230  and L3 cache  232  consults its respective directory and determines if the target cache line of the partial line prefetch request is present in either cache. For a partial cache line prefetch request, a hit is considered to occur if an L3 cache  232  contains either the full target cache line or the requested partial cache line or if an L2 cache  230  contains the full target cache line. If a cache hit is detected at block  406 , the partial cache line prefetch request is aborted because the target cache line is already installed in the cache hierarchy (block  408 ). However, for workloads that utilize the partial cache line access techniques disclosed herein, hits at block  406  will be rare. 
     In response to a negative determination at block  406 , the an PF machine  272  issues a partial cache line prefetch command on the interconnect fabric to obtain the target partial cache line from an IMC  206  (block  410 ). As described above, coherence responses from the various participants on the interconnect fabric determine the source of the partial cache line. At block  412 , the PF machine  272  determines if the coherence response to the partial cache line prefetch command indicates the partial cache line was sourced from an IMC  206  in an exclusive coherence state. If so, the PF machine  272  installs the partial cache line in data array  260  of L3 cache  232  and sets coherence state field  306  and one of valid bits  302 ,  304  of the corresponding directory entry  300  as described above with reference to  FIG. 3  and Table I (blocks  414  and  416 ). If, however, a negative determination is made at block  412 , a normal full cache line prefetch command is instead performed (block  418 ). Following either of block  416  or block  418 , the process completes at block  420 . 
     With reference now to  FIG. 5 , there is illustrated a high level logical flowchart of an exemplary process of servicing a core memory access request in one embodiment. The illustrated process begins at block  500 , for example, with LSU  225  of a processor core  220  executing a memory access instruction, such as a load or store instruction. Following execution of the memory access instruction to determine the target real address of the memory access instruction and a determination that the memory access request cannot be serviced by the L1 cache  228 , processor core  220  issues a memory access request to its L2 cache  230  via the core-to-L2 interface  227  (block  502 ). In response to receipt of the memory access request, an RC machine  250  is dispatched to service the memory access request. The RC machine  250  then speculatively issues the memory access command to L3 cache  232  via L2-to-L3 interface  257  (block  504 ). 
     The RC machine  250  then determines at block  506  whether the memory access request missed in L2 cache  230  and hit a partial cache line in L3 cache  232 . If not, the memory access request is processed as a normal read or store request as described above. If, however, the RC machine  250  determines at block  506  that the memory access request missed in L2 cache  230  and hit a partial cache line in L3 cache  232 , the memory access request is serviced as a partial cache line memory access request, as described below with reference to block  520 - 524  for partial cache line read requests and as described with reference to blocks  530 - 536  for partial cache line store requests. 
     Referring first to block  520 , for a partial cache line read request, a RD machine  270  in L3 cache  232  returns the target partial cache line to the RC machine  250  of L2 cache  230  without any update to the corresponding directory entry  300  in L3 cache  232 . In response to receipt of the target partial cache line, the RC machine  250  returns the target partial cache line data to the processor core  220  without populating data array  240  with the target partial cache line and without performing any update to directory  242  (block  522 ). In response to receipt of the target partial cache line, processor core  220  places data from the target partial cache line in GPRF  226  without caching the target partial cache line in L1 cache  228  or updating its directory (block  524 ). Thereafter, the process of  FIG. 5  ends at block  540 . 
     In this fashion, the partial cache line of data is returned to the requesting processor core  220  directly from L3 cache  232  to GPRF  226  without polluting the upper level caches with the partial cache line (e.g., L1 and L2 caches  228 ,  230 ). In many cases, the partial cache line read serves as the first part of an update of the target partial cache line. Once the partial cache line data is present in GPRF  226 , the partial cache line data can be modified and manipulated as necessary or desired through the execution of one or more additional arithmetic or logical instructions by EUs  224 . 
     Referring now to block  530 , for a partial cache line store request, the RD machine  270  of L3 cache  232  returns the target partial cache line to the merge buffer  246 . L3 cache  232  also invalidates the directory entry  300  corresponding to target partial cache line to release its copy of the partial cache line because the partial cache line store request completes a read-modify-write cycle used to update the partial cache line (block  532 ). In response to receipt of the partial cache line in merge buffer  246 , L2 cache  230  merges the store data received from the processor core  220  in STQ  244  into merge buffer  246  without caching the partial cache line data (block  534 ). A CO machine  252  is then dispatched to write the updated partial cache line directly from merge buffer  246  into system memory  108 , thus completing the update of the partial cache line without polluting the upper level caches with the partial cache line (e.g., L1 and L2caches  228 ,  230 ). 
     Referring now to  FIG. 6 , there is depicted a high level logical flowchart of an exemplary process by which an L3 cache  232  processes a snooped command on the interconnect fabric. It should be noted that an L3 cache  232  of the cache hierarchy initiating a command does not, in general, snoop a command on the interconnect fabric. Rather, the L3 directory  262  is consulted when a RC machine  250  passes a request to an L3 RD machine  270  and before the memory access command is placed on the interconnect fabric. Consequently, the process shown in  FIG. 6  generally applies to L3 caches  232  other than the L3 cache  232  of the cache hierarchy that is the source of the command. 
     The process of  FIG. 6  begins at block  600  in response to an L3 cache  232  sensing a command on the interconnect fabric in one embodiment. In response to receipt of the command, an L3 SN machine  274  is dispatched to service the snooped command, and the SN machine  274  determines if the snooped command is a partial cache line prefetch command (block  602 ). If not, the SN machine  274  services the snooped command in a conventional manner (block  604 ), and the process terminates at block  614 . 
     If, one the other hand, the SN machine  274  determines at block  602  that the snooped command is a partial cache line prefetch command, SN machine  274  determines at blocks  606  and  608  whether or not the directory  262  indicates that the partial cache line prefetch command hits a partial or full cache line within L3 cache  232 . If a determination is made at block  606  that partial cache line prefetch request hits a full cache line, a partial cache line prefetch from an IMC  206  is not possible, and SN machine  274  provides an abort coherence (partial) response that will cause the partial cache line prefetch command to be aborted (block  610 ). Thereafter, the process ends at block  614 . 
     If SN machine  274  determines at block  608  that the partial cache line prefetch command did not result in a hit on a partial cache line, SN machine  274  provides no coherency response since its L3 cache  232  does not contain the target partial cache line. Consequently, the process simply terminates at block  614 . 
     If, however, SN machine  274  determines at block  608  that partial cache line prefetch command resulted in a hit on a partial cache line, SN machine  274  invalidates its locally cached copy of the target partial cache line without providing a coherency response (block  612 ), thus permitting an WIC  206  to source the target partial cache line in an exclusive state. Exclusivity is guaranteed by the design of the coherence protocol because, if a snoop hit on a partial cache line occurs in an L3 cache  232 , that L3 cache  232  is guaranteed to be the only cache in data processing system  100  to contain a full or partial copy of the target cache line. In this case, the snooping L3 cache  232  abandons its copy of the partial cache line to allow another L3 cache  232  to attempt to perform an update. Following block  612 , the process shown in  FIG. 6  ends at block  614 . 
     With reference now to  FIG. 7 , there is illustrated a high level logical flowchart of an exemplary process by which an L2 cache  230  processes a snooped command on the interconnect fabric in one embodiment. As described above, an L2 cache  230  of the cache hierarchy initiating a command does not, in general, self-snoop a command on the interconnect fabric. 
     The process of  FIG. 7  begins at block  700  in response to an L2 cache  230  sensing a command on the interconnect fabric. In response to receipt of the command, an L2 SN machine  254  is dispatched to service the snooped command, and the SN machine  254  determines if the snooped command is a partial cache line prefetch command (block  702 ). If not, the SN machine  274  services the snooped command in a conventional manner (block  704 ), and the process terminates at block  710 . 
     If, one the other hand, the SN machine  254  determines at block  702  that the snooped command is a partial cache line prefetch command, SN machine  254  determines at block  706  whether or not the L2 directory  242  indicates that the partial cache line prefetch command results in a hit. If so, a partial cache line prefetch from an IMC  206  is not possible, and SN machine  254  accordingly provides an abort coherence (partial) response that will cause the partial cache line prefetch command to be aborted (block  708 ). Thereafter, the process ends at block  710 . 
     Returning to block  706 , if the SN machine  254  determines that the partial cache line prefetch command did not result in a hit in its L2 cache  230 , SN machine  254  provides no coherency response since its L2 cache  230  does not contain the target cache line. Consequently, the process simply terminates at block  710 . 
     As has been described, in one embodiment, a processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line. 
     If the memory access request is a read request, the at least one upper level cache memory services the read request by transmitting the partial cache line to the processor core. The processor core places data from the partial cache line in the register file without caching the partial cache line in the at least one upper level cache memory. If, on the other hand, the memory access request is a store request, the lower level cache memory invalidates its copy of the partial cache line, and the at least one upper level cache services the store request by merging store data from the processor core with the partial cache line to obtain an updated partial cache line and writing the updated partial cache line directly to system memory without caching the updated partial cache line in the at least one upper level cache memory or the lower level cache memory. 
     While the invention has been particularly shown and described with reference to one or more preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. Further, although aspects have been described with respect to a computer system executing program code that directs the functions of the present invention, it should be understood that present invention may alternatively be implemented as a program product including a storage medium storing program code that can be processed by a data processing system. 
     As an example, the program product may include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, or otherwise functionally equivalent representation (including a simulation model) of hardware components, circuits, devices, or systems disclosed herein. Such data and/or instructions may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++. Furthermore, the data and/or instructions may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures).