Patent Publication Number: US-2020303192-A1

Title: Apparatus having integrated circuit well structures of vertical and/or retrograde profiles

Description:
RELATED APPLICATIONS 
     This application is a Continuation of U.S. application Ser. No. 15/892,584 filed on Feb. 9, 2018 and titled “METHODS OF FORMING INTEGRATED CIRCUIT WELL STRUCTURES,” (allowed), which claims the benefit of U.S. Provisional Patent Application Ser. No. 62/611,694, filed Dec. 29, 2017 and titled, “METHODS OF FORMING INTEGRATED CIRCUIT WELL STRUCTURES,” which is commonly assigned and incorporated by reference herein in its entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates generally to integrated circuits and, in particular, in one or more embodiments, the present disclosure relates to methods of forming integrated circuit well structures and memory containing such well structures. 
     BACKGROUND 
     Integrated circuit devices traverse a broad range of electronic devices. One particular type include memory devices, oftentimes referred to simply as memory. Memory devices are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. 
     Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand. 
     A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known. 
     In order for memory manufacturers to remain competitive, memory designers are constantly striving to increase the density of memory devices. Increasing the density of a memory device often involves reducing spacing between circuit elements. However, reduced spacing of circuit elements may hinder effective isolation of adjacent circuit elements. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified block diagram of a memory in communication with a processor as part of an electronic system, according to an embodiment. 
         FIGS. 2A-2B  are schematics of portions of an array of memory cells as could be used in a memory of the type described with reference to  FIG. 1 . 
         FIG. 3  depicts a related integrated circuit structure. 
         FIGS. 4A-4H  depict an integrated circuit structure during various stages of fabrication in accordance with embodiments. 
         FIG. 5A  is a schematic of a portion of an array of memory cells as could be used in a memory device of the type described with reference to  FIG. 1 . 
         FIG. 5B  is a cross-sectional view of a block select transistor of  FIG. 4A  formed on a portion of the integrated circuit structure of  FIG. 3F-3H . 
         FIG. 6  is a flowchart of a method of forming a portion of an integrated circuit device in accordance with an embodiment. 
         FIG. 7  is a flowchart of a method of forming a portion of an integrated circuit device in accordance with an embodiment. 
         FIG. 8  is a flowchart of a method of forming a portion of an integrated circuit device in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense. 
     The term “semiconductor” used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions. 
     The term “conductive” as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term “connecting” as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting unless otherwise apparent from the context. 
       FIG. 1  is a simplified block diagram of a first apparatus (e.g., an integrated circuit device), in the form of a memory (e.g., memory device)  100 , in communication with a second apparatus, in the form of a processor  130 , as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones and the like. The processor  130 , e.g., a controller external to the memory device  100 , may be a memory controller or other external host device. 
     Memory device  100  includes an array of memory cells  104  logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells (not shown in  FIG. 1 ) of at least a portion of array of memory cells  104  are capable of being programmed to one of at least two data states. 
     A row decode circuitry  108  and a column decode circuitry  110  are provided to decode address signals. Address signals are received and decoded to access the array of memory cells  104 . Memory device  100  also includes input/output (I/O) control circuitry  112  to manage input of commands, addresses and data to the memory device  100  as well as output of data and status information from the memory device  100 . An address register  114  is in communication with I/O control circuitry  112  and row decode circuitry  108  and column decode circuitry  110  to latch the address signals prior to decoding. A command register  124  is in communication with I/O control circuitry  112  and control logic  116  to latch incoming commands. 
     A controller (e.g., the control logic  116  internal to the memory device  100 ) controls access to the array of memory cells  104  in response to the commands and generates status information for the external processor  130 , i.e., control logic  116  is configured to perform access operations (e.g., read operations, program operations and/or erase operations) and other operations in accordance with embodiments described herein. The control logic  116  is in communication with row decode circuitry  108  and column decode circuitry  110  to control the row decode circuitry  108  and column decode circuitry  110  in response to the addresses. 
     Control logic  116  may also be in communication with a cache register  118 . Cache register  118  may latch data, either incoming or outgoing, as directed by control logic  116  to temporarily store data while the array of memory cells  104  is busy writing or reading, respectively, other data. During a program operation (e.g., write operation), data may be passed from the cache register  118  to data register  120  for transfer to the array of memory cells  104 ; then new data may be latched in the cache register  118  from the I/O control circuitry  112 . During a read operation, data may be passed from the cache register  118  to the I/O control circuitry  112  for output to the external processor  130 ; then new data may be passed from the data register  120  to the cache register  118 . A status register  122  is in communication with I/O control circuitry  112  and control logic  116  to latch the status information for output to the processor  130 . 
     Memory device  100  receives control signals at control logic  116  from processor  130  over a control link  132 . The control signals might include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, a write enable WE #, a read enable RE #, and a write protect WP #. Additional or alternative control signals (not shown) may be further received over control link  132  depending upon the nature of the memory device  100 . Memory device  100  receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor  130  over a multiplexed input/output (I/O) bus  134  and outputs data to processor  130  over I/O bus  134 . 
     For example, the commands may be received over input/output (I/O) pins [7:0] of I/O bus  134  at I/O control circuitry  112  and may be written into command register  124 . The addresses may be received over input/output (I/O) pins [7:0] of I/O bus  134  at I/O control circuitry  112  and may be written into address register  114 . The data may be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry  112  and may be written into cache register  118 . The data may be subsequently written into data register  120  for programming the array of memory cells  104 . For another embodiment, cache register  118  may be omitted, and the data may be written directly into data register  120 . Data may also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. The I/O bus  134  might further include complementary data strobes DQS and DQSN that may provide a synchronous reference for data input and output. Although reference may be made to I/O pins, they may include any conductive node providing for electrical connection to the memory device  100  by an external device (e.g., processor  130 ), such as conductive pads or conductive bumps as are commonly used. 
     It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device  100  of  FIG. 1  has been simplified. It should be recognized that the functionality of the various block components described with reference to  FIG. 1  may not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of  FIG. 1 . Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of  FIG. 1 . 
     Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins may be used in the various embodiments. 
       FIG. 2A  is a schematic of a portion of an array of memory cells  200 A as could be used in a memory of the type described with reference to  FIG. 1 , e.g., as a portion of array of memory cells  104 . Memory array  200 A includes access lines, such as word lines  202   0  to  202   N , and data lines, such as bit lines  204   0  to  204   M . The word lines  202  may be connected to global access lines (e.g., global word lines), not shown in  FIG. 2A , in a many-to-one relationship. For some embodiments, memory array  200 A may be formed over a semiconductor that, for example, may be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well. 
     Memory array  200 A might be arranged in rows (each corresponding to a word line  202 ) and columns (each corresponding to a bit line  204 ). Each column may include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings  206   0  to  206   M . Each NAND string  206  might be connected (e.g., selectively connected) to a common source (SRC)  216  and might include memory cells  208   0  to  208   N . The memory cells  208  may represent non-volatile memory cells for storage of data. The memory cells  208  of each NAND string  206  might be connected in series between a select gate  210  (e.g., a field-effect transistor), such as one of the select gates  210   0  to  210   M  (e.g., that may be source select transistors, commonly referred to as select gate source), and a select gate  212  (e.g., a field-effect transistor), such as one of the select gates  212   0  to  212   M  (e.g., that may be drain select transistors, commonly referred to as select gate drain). Select gates  210   0  to  210   M  might be commonly connected to a select line  214 , such as a source select line (SGS), and select gates  212   0  to  212   M  might be commonly connected to a select line  215 , such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates  210  and  212  may utilize a structure similar to (e.g., the same as) the memory cells  208 . The select gates  210  and  212  might represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal. 
     A source of each select gate  210  might be connected to common source  216 . The drain of each select gate  210  might be connected to a memory cell  208   0  of the corresponding NAND string  206 . For example, the drain of select gate  210   0  might be connected to memory cell  208   0  of the corresponding NAND string  206   0 . Therefore, each select gate  210  might be configured to selectively connect a corresponding NAND string  206  to common source  216 . A control gate of each select gate  210  might be connected to select line  214 . 
     The drain of each select gate  212  might be connected to the bit line  204  for the corresponding NAND string  206 . For example, the drain of select gate  212   0  might be connected to the bit line  204   0  for the corresponding NAND string  206   0 . The source of each select gate  212  might be connected to a memory cell  208   N  of the corresponding NAND string  206 . For example, the source of select gate  212   0  might be connected to memory cell  208   N  of the corresponding NAND string  206   0 . Therefore, each select gate  212  might be configured to selectively connect a corresponding NAND string  206  to the corresponding bit line  204 . A control gate of each select gate  212  might be connected to select line  215 . 
     The memory array in  FIG. 2A  might be a three-dimensional memory array, e.g., where NAND strings  206  may extend substantially perpendicular to a plane containing the common source  216  and to a plane containing a plurality of bit lines  204  that may be substantially parallel to the plane containing the common source  216 . 
     Typical construction of memory cells  208  includes a data-storage structure  234  (e.g., a floating gate, charge trap, etc.) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate  236 , as shown in  FIG. 2A . The data-storage structure  234  may include both conductive and dielectric structures while the control gate  236  is generally formed of one or more conductive materials. In some cases, memory cells  208  may further have a defined source/drain (e.g., source)  230  and a defined source/drain (e.g., drain)  232 . Memory cells  208  have their control gates  236  connected to (and in some cases form) a word line  202 . 
     A column of the memory cells  208  may be a NAND string  206  or a plurality of NAND strings  206  selectively connected to a given bit line  204 . A row of the memory cells  208  may be memory cells  208  commonly connected to a given word line  202 . A row of memory cells  208  can, but need not, include all memory cells  208  commonly connected to a given word line  202 . Rows of memory cells  208  may often be divided into one or more groups of physical pages of memory cells  208 , and physical pages of memory cells  208  often include every other memory cell  208  commonly connected to a given word line  202 . For example, memory cells  208  commonly connected to word line  202   N  and selectively connected to even bit lines  204  (e.g., bit lines  204   0 ,  204   2 ,  204   4 , etc.) may be one physical page of memory cells  208  (e.g., even memory cells) while memory cells  208  commonly connected to word line  202   N  and selectively connected to odd bit lines  204  (e.g., bit lines  204   1 ,  204   3 ,  204   5 , etc.) may be another physical page of memory cells  208  (e.g., odd memory cells). Although bit lines  204   3 - 204   5  are not explicitly depicted in  FIG. 2A , it is apparent from the figure that the bit lines  204  of the array of memory cells  200 A may be numbered consecutively from bit line  204   0  to bit line  204   M . Other groupings of memory cells  208  commonly connected to a given word line  202  may also define a physical page of memory cells  208 . For certain memory devices, all memory cells commonly connected to a given word line might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as all memory cells connected to word lines  202   0 - 202   N  (e.g., all NAND strings  206  sharing common word lines  202 ). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells. 
       FIG. 2B  is another schematic of a portion of an array of memory cells  200 B as could be used in a memory of the type described with reference to  FIG. 1 , e.g., as a portion of array of memory cells  104 . Like numbered elements in  FIG. 2B  correspond to the description as provided with respect to  FIG. 2A .  FIG. 2B  provides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array  200 B may incorporate vertical structures which may include semiconductor pillars where a portion of a pillar may act as a channel region of the memory cells of NAND strings  206 . The NAND strings  206  may be each selectively connected to a bit line  204   0 - 204   M  by a select transistor  212  (e.g., that may be drain select transistors, commonly referred to as select gate drain) and to a common source  216  by a select transistor  210  (e.g., that may be source select transistors, commonly referred to as select gate source). Multiple NAND strings  206  might be selectively connected to the same bit line  204 . Subsets of NAND strings  206  can be connected to their respective bit lines  204  by biasing the select lines  215   0 - 215   K  to selectively activate particular select transistors  212  each between a NAND string  206  and a bit line  204 . The select transistors  210  can be activated by biasing the select line  214 . Each word line  202  may be connected to multiple rows of memory cells of the memory array  200 B. Rows of memory cells that are commonly connected to each other by a particular word line  202  may collectively be referred to as tiers. 
     Various circuit elements may be formed on well structures of varying types and levels of conductivity.  FIG. 3  depicts a related integrated circuit structure demonstrating two adjacent well structures and their limitations. In general, a well structure might be formed of one or more regions (e.g., doped regions) of semiconductor material  346  in a semiconductor material  340 . One of the regions of semiconductor material  346  (e.g., 346 0 ) is typically formed over, and often in contact with, a region of semiconductor material  338 . The region of semiconductor material  338  might have a conductivity type, such as an n-type conductivity. The regions of semiconductor material  346  (e.g., each region of semiconductor material  346   0 - 346   2 ) might have a conductivity type the same as the conductivity type of the region of semiconductor material  338 , such as an n-type conductivity. The semiconductor material  340  might have a conductivity type that is different than (e.g., opposite of) the conductivity type of the semiconductor material  338 , such as a p-type conductivity. In combination, the regions of semiconductor material  346   0 - 346   2  and the region of semiconductor material  338  form a contiguous structure often referred to as a tub. The enclosed portion of the semiconductor material  340  between two stacks of the regions of semiconductor material  346   0 - 346   2  in contact with the region of semiconductor material  338 , e.g., within the tub, may represent a well having a different conductivity type than the well structures of the regions of semiconductor material  346 . 
     Each of the regions of semiconductor material  346  might be formed by implanting a dopant species into the semiconductor material  340 . As is well understood in the art, such implantation generally involves acceleration of ions directed at a surface of the semiconductor material  340 . To produce an n-type conductivity, the dopant species might include ions of arsenic (As), antimony (Sb), phosphorus (P) or another n-type impurity. To produce a p-type conductivity, the dopant species might include ions of boron (B) or another p-type impurity. 
     Each of the regions of semiconductor material  346  might be formed at different implant energy levels. Higher implant energy levels may generally lead to deeper doped regions for a given dopant species. For example, the region of semiconductor material  346   0  might be formed at a first implant energy level, the region of semiconductor material  346   1  might be formed at a second implant energy level less than the first implant energy level, and the region of semiconductor material  346   2  might be formed at a third implant energy level less than the second implant energy level. The region of semiconductor material  338  might be similarly formed, e.g., by implanting a dopant species into the semiconductor material  340 , e.g., at a higher implant energy level than is used for any of the regions of semiconductor material  346   0 - 346   2 . 
     While higher energy implants generally form doped regions at deeper levels (e.g., farther from the surface of the semiconductor material  340 ) for a given dopant species, they may also lead to an increased level of dopant migration or straggle, such that the region  346   0  might be wider than the region  346   1  which might be wider than the region  346   2 . As the spacing between adjacent well structures narrows, isolation characteristics might diminish and might lead to punch-through, or breakdown, between the adjacent well structures. Various embodiments may mitigate such widening of the doped regions of a multi-level well structure. Various embodiments may seek to form well structures having vertical or retrograde profiles. 
       FIGS. 4A-4H  depict an integrated circuit structure during various stages of fabrication in accordance with embodiments.  FIG. 4A  depicts a semiconductor material  440  over a region of semiconductor material  438 . The semiconductor materials  438  and  440  may each comprise silicon, such as monocrystalline silicon, or other semiconductor material. The semiconductor material  440  might have a conductivity type that is different than (e.g., opposite of) the conductivity type of the semiconductor material  438 . For example, the semiconductor material  438  might have a first conductivity type (e.g., an n-type conductivity) and the semiconductor material  440  might have second conductivity type (e.g., a p-type conductivity). The region of semiconductor material  438  might be formed by implanting a dopant species (e.g., one or more dopant species) into the semiconductor material  440 . Alternatively, the semiconductor material  440  might be formed over and subsequent to forming the semiconductor material  438 , such as by epitaxial growth, chemical vapor deposition, physical vapor deposition, etc. 
     A patterned mask  442   0  might be formed over the semiconductor material  440 . The patterned mask  442   0  might have an opening  454   0  exposing a portion of the semiconductor material  440  and having a width  448   0 . The patterned mask  442   0  might further have a thickness  450   0 . As one example, the thickness  450   0  might be 3-4 μm, e.g., 3.3 μm. The patterned mask  442   0  might represent a patterned photoresist material, or any other material configured to impede (e.g., block) implantation of dopant species. 
     Photolithographic processes are often used to define a desired pattern in integrated circuit fabrication. In a photolithographic process, a photoresist layer may be formed on the surface of the in-process device. The photoresist layer may contain a photo-sensitive polymer whose ease of removal is altered upon exposure to light or other electromagnetic radiation. To define the pattern, the photoresist layer may be selectively exposed to radiation and then developed to expose portions of the underlying layer. In a positive resist system, the portions of the photoresist layer exposed to the radiation are photosolubilized and a photolithographic mask is designed to block the radiation from those portions of the photoresist layer that are to remain after developing. In a negative resist systems, the portions of the photoresist layer exposed to the radiation are photopolymerized and the photolithographic mask is designed to block the radiation from those portions of the photoresist layer that are to be removed by developing. 
     In  FIG. 4B , a dopant species might be accelerated (e.g., implanted) into the semiconductor material  440  through the opening  454   0 . For example, a beam of ions  444   0  might be directed at the surface of the semiconductor material  440  to form a region of semiconductor material  446   0 , which might be in contact with the region of semiconductor material  438 . The region of semiconductor material  446   0  might have the first conductivity type. Although the region of semiconductor material  446   0  is depicted as having a rectangular profile, those of ordinary skill in the art will recognize that the profile shape may generally be more amorphous in nature. The region of semiconductor material  446   0  might be formed at a first level within the semiconductor material  440  nominally extending (e.g., extending) from a first depth  452   0  from the surface of the semiconductor material  440  (e.g., in contact with the region of semiconductor material  438 ) to a second depth  452   1  (e.g., to at least the second depth  452   1 ) from the surface of the semiconductor material  440 . 
     In  FIG. 4C , the patterned mask  442   0  of  FIGS. 4A-4B  is subjected to an isotropic removal process, such as an isotropic wet etch, an isotropic dry plasma etch, a dry-strip plasma clean, etc., to form the patterned mask  442   1 . The patterned mask  442   1  might have an opening  454   1  exposing a portion of the semiconductor material  440  and having a width  448   1 . The patterned mask  442   1  might further have a thickness  450   1 . Isotropic removal processes generally remove materials (e.g., uniformly) in all directions of contact, e.g., reducing thicknesses and widening openings of surface materials being removed. Accordingly, the width  448   1  may be greater (e.g., wider) than the width  448   0 , while the thickness  450   1  may be less (e.g., narrower) than the thickness  450   0 . As one example, the thickness  450   1  might be 1.5-2.5 μm, e.g., 2 μm. 
     In  FIG. 4D , a dopant species might be accelerated (e.g., implanted) into the semiconductor material  440  through the opening  454   1 . For example, a beam of ions  444   1  might be directed at the surface of the semiconductor material  440  to form a region of semiconductor material  446   1 , which might be in contact with the region of semiconductor material  446   0 . The region of semiconductor material  446   1  might have the first conductivity type. Although the region of semiconductor material  446   1  is depicted as having a rectangular profile, those of ordinary skill in the art will recognize that the profile shape may generally be more amorphous in nature. The region of semiconductor material  446   1  might be formed at a second level within the semiconductor material  440  nominally extending (e.g., extending) from the second depth  452   1  (e.g., from at least the second depth  452   1 ) to a third depth  452   2  (e.g., to at least the third depth  452   2 ) from the surface of the semiconductor material  440 . 
     The dopant species used to form the region of semiconductor material  446   1  may be the same as, or different than, the dopant species used to form the region of semiconductor material  446   0 , while having a same conductivity type. For example, the dopant species used to form the region of semiconductor material  446   0  and the region of semiconductor material  446   1  might both be phosphorus to form regions of n-type conductivity. Alternatively, the dopant species used to form the region of semiconductor material  446   0  might be phosphorus to form a region of n-type conductivity, while the dopant species used to form the region of semiconductor material  446   1  might be arsenic to also form a region of n-type conductivity. 
     In  FIG. 4E , the patterned mask  442   1  of  FIGS. 4C-4D  is subjected to an isotropic removal process, such as an isotropic wet etch, an isotropic dry plasma etch, a dry-strip plasma clean, etc., to form the patterned mask  442   2 . The patterned mask  442   2  might have an opening  454   2  exposing a portion of the semiconductor material  440  and having a width  448   2 . The patterned mask  442   2  might further have a thickness  450   2 . The width  448   2  may be greater (e.g., wider) than the width  448   1 , while the thickness  450   2  may be less (e.g., narrower) than the thickness  450   1 . As one example, the thickness  450   2  might be 0.5-1.0 μm, e.g., 0.8 μm. 
     In  FIG. 4F , a dopant species might be accelerated (e.g., implanted) into the semiconductor material  440  through the opening  454   2 . For example, a beam of ions  444   2  might be directed at the surface of the semiconductor material  440  to form a region of semiconductor material  446   2 , which might be in contact with the region of semiconductor material  446   1 . The region of semiconductor material  446   2  might have the first conductivity type. Although the region of semiconductor material  446   2  is depicted as having a rectangular profile, those of ordinary skill in the art will recognize that the profile shape may generally be more amorphous in nature. The region of semiconductor material  446   2  might be formed at a third level within the semiconductor material  440  nominally extending (e.g., extending) from the third depth  452   2  (e.g., from at least the third depth  452   2 ) to a fourth depth  452   3  from the surface of the semiconductor material  440 , which may be coincident with the surface of the semiconductor material  440 . The dopant species used to form the region of semiconductor material  446   2  may be the same as, or different than, the dopant species used to form the region of semiconductor material  446   1 , while having a same conductivity type. 
     While  FIGS. 4A-4F  depicted a well structure of a single stack of regions of semiconductor material  446 , such well structures would typically be used to form tubs, e.g., enclosing a portion of the semiconductor material  440  (e.g., a well) having the second conductivity type within a tub of material having the first conductivity type.  FIGS. 4G and 4H  each depict a well  456  in a portion of the semiconductor material  440  that is isolated from adjacent portions of the semiconductor material  440  by regions of semiconductor material  438  and  446  having the first conductivity type. By utilizing the isotropic removal of the patterned mask between the formation of regions of semiconductor material  446  at adjacent levels, a generally vertical profile of the regions of semiconductor material  446  might be generated, such as depicted in  FIG. 4G , with widths of each resulting region of semiconductor material being similar (e.g., the same). Additionally, as the risk of punch-through might be more severe at lower levels of the regions of semiconductor material  446 , a retrograde profile of the regions of semiconductor material  446  might be generated, such as depicted in  FIG. 4H , in order to increase the spacing between adjacent regions of semiconductor material  446  at the lower levels, e.g., by reducing the resulting widths of regions of semiconductor material  446  at lower levels, without affecting the spacing between adjacent regions of semiconductor material near (e.g., at) the surface of the semiconductor material  440 . While each region of semiconductor material  446  formed at one level (e.g., for a corresponding range of depths from the surface of the semiconductor material  440 ) is depicted in  FIG. 4H  to be wider than each region of semiconductor material  446  formed at a lower level (e.g., for a different corresponding range of depths farther from the surface of the semiconductor material  440 ), other options might be used. For example, the regions of semiconductor material  446   1  and  446   2  might have similar widths, such as shown and described with reference to  FIG. 4G , and the region of semiconductor material  446   0  might have a width less than the width of the region of semiconductor material  446   1 , such as shown and described with reference to  FIG. 4H . 
     By characterizing the implantation of desired dopant species at different levels of the semiconductor material  440 , as might be determined experimentally, empirically or through simulation, desired widths of openings  454  could be determined for each desired level to produce the desired profile. Similarly, by characterizing the isotropic removal of the patterned mask  442 , as might be determined experimentally, empirically or through simulation, a desired initial thickness could be determined that would permit formation of each of the subsequent desired widths of the openings  454  while maintaining sufficient thickness to impede implantation of dopant species where such is not desired. While three levels of regions of semiconductor material  446  were shown and described with reference to  FIGS. 4A-4H , fewer or more levels of regions of semiconductor material  446  might be used in accordance with embodiments. 
     Different types of circuitry might be formed over the regions of semiconductor material  446  (e.g., regions of semiconductor material  446   2 ) versus the well  456 . For example, p-type field-effect transistors (pFETs) might be formed in adjacent semiconductor regions  446   2  (e.g., as part of circuitry to select different blocks of memory cells of an array of memory cells for access), while n-type field-effect transistors (nFETs) might be formed in the well  456 .  FIGS. 5A-5B  provide an example of the use of a region of semiconductor material  446  in a memory. 
     As referenced with respect to  FIG. 2A , local access lines, e.g., word lines  202 , may be connected to global access lines in a many-to-one relationship.  FIG. 5A  is a schematic of a portion of an array of memory cells as could be used in a memory device of the type described with reference to  FIG. 1  and depicting this many-to-one relationship between local access lines (e.g., word lines  202 ) and global access lines (e.g., global word lines  502 ). 
     As depicted in  FIG. 5A , a plurality of blocks of memory cells  562  may have their local access lines (e.g., word lines  202 ) commonly selectively connected to a plurality of global access lines (e.g., global word lines  502 ). A block of memory cells  562  may include a plurality of NAND strings  206  commonly coupled to a particular set of word lines  202 . For example, the NAND strings  206   0 - 206   M  of  FIG. 2A , or some portion thereof, may represent a block of memory cells  562 . Although  FIG. 5A  depicts only blocks of memory cells  562   0  and  562   1  (Block  0  and Block  1 ), additional blocks of memory cells  562  may have their word lines  202  commonly connected to global word lines  502  in a like manner. Similarly, although  FIG. 5A  depicts only four word lines  202 , blocks of memory cells  562  may include fewer or more word lines  202 . In applying the structure of  FIG. 5A  to the array structures of  FIGS. 2A-2B , it is clear that there would be N+1 global word lines  502 , i.e., GWL  502   0  to  502   N . 
     To facilitate memory access operations to specific blocks of memory cells  562  commonly coupled to a given set of global word lines  502 , each block of memory cells  562  may have a corresponding set of block select transistors  558  in a one-to-one relationship with their word lines  202 . Control gates of the set of block select transistors  558  for a given block of memory cells  562  may have their control gates commonly connected to a corresponding block select line  560 . For example, for block of memory cells  562   0 , word line  202   00  may be selectively connected to global word line  502   0  through block select transistor  558   00 , word line  202   01  may be selectively connected to global word line  502   1  through block select transistor  558   01 , word line  202   02  may be selectively connected to global word line  502   2  through block select transistor  558   02 , and word line  202   03  may be selectively connected to global word line  502   3  through block select transistor  558   03 , while block select transistors  558   00 - 554   03  are responsive to a control signal (e.g., a common control signal) received on block select line  560   0 . 
     Block select transistors may be high-voltage devices. Such switching devices may require increased isolation.  FIG. 5B  is a cross-sectional view of a block select transistor  558 , having a control gate  566  and source/drain regions  564 , wherein the control gate  566  is connected to a block select line  560 . The block select transistor  558  may be formed in a region of semiconductor material  446  (e.g., a region of semiconductor material  446   2  of  FIG. 4F ), e.g., after removal of the patterned mask  442 . For a high-voltage pFET, the regions of semiconductor material  446  might have an N-level of conductivity to provide a high breakdown voltage, e.g., greater than about 30V. 
       FIG. 6  is a flowchart of a method of forming a portion of an integrated circuit device in accordance with an embodiment. At  671 , a patterned mask might be formed having an opening and exposing a semiconductor material (e.g., a portion of a surface of the semiconductor material). For example, a patterned mask might be formed over (e.g., on) a surface of the semiconductor material. At  673 , a first doped region might be formed at a first level of the semiconductor level through the opening. At  675 , a portion of the patterned mask might be removed isotropically to increase a width of the opening. And at  677 , a second doped region might then be formed at a second level of the semiconductor level through the opening. 
     For some embodiments, additional doped regions might be formed at additional levels of the semiconductor material. Accordingly, the process might proceed to  679 , where an additional portion (e.g., second portion) of the patterned mask might be removed isotropically to increase (e.g., further increase) the width of the opening. Subsequently, at  681 , an additional doped region (e.g., third doped region) might be formed at an additional level (e.g., third level) of the semiconductor level through the opening. This processing might be repeated for one or more additional doped regions of semiconductor material. 
       FIG. 7  is a flowchart of a method of forming a portion of an integrated circuit device in accordance with an embodiment. At  781 , a patterned mask might be formed having an opening and exposing a semiconductor material (e.g., a portion of a surface of the semiconductor material). For example, a patterned mask might be formed over (e.g., on) a surface of the semiconductor material. At  783 , a first dopant species might be implanted in the semiconductor material through the opening and using a first implant energy level. For example, the first dopant species might be phosphorus and the first implant energy level might be approximately 100 KeV, e.g., 960 KeV. 
     At  785 , the patterned mask might be isotropically etched to increase a width of the opening. And at  787 , a second dopant species might be implanted in the semiconductor material through the opening and using a second implant energy level less than the first implant energy level. The second dopant species might be the same as, or different from, the first dopant species. The second dopant species might provide a same conductivity type as the first dopant species. For example, the second dopant species might be phosphorus and the second implant energy level might be approximately 300-400 KeV, e.g., 320 KeV. 
     For some embodiments, additional doped species might be implanted at different implant energy levels. Accordingly, the process might proceed to  789 , where the patterned mask might again be isotropically etched to increase (e.g., further increase) the width of the opening. At  791 , an additional dopant species might be implanted in the semiconductor material through the opening and using an additional (e.g., second) implant energy level less than a prior (e.g., the first) implant energy level. The additional dopant species might be the same as, or different from, the prior (e.g., second) dopant species. The additional dopant species might provide a same conductivity type as the prior dopant species. For example, the additional dopant species might be phosphorus and the additional implant energy level might be approximately 100-200 KeV, e.g., 150 KeV. This processing might be repeated for one or more additional doped regions of semiconductor material. The implant energy level selected for implanting a dopant species at the surface of the semiconductor material might be chosen in response to desired electrical properties of circuitry formed in that region of semiconductor material. 
     For some embodiments, dopant species might be implanted through an opening of a particular width at more than one implant energy level, e.g., to increase a range of depth of a resulting doped region of semiconductor material.  FIG. 8  is a flowchart of a method of forming a portion of an integrated circuit device in accordance with such an embodiment, as an extension of the method of  FIG. 7 . For example, proceeding from  787  of  FIG. 7 , at third dopant species might be implanted in the semiconductor material through the opening and using a third implant energy level less than the second implant energy level. The third dopant species might be the same as, or different from, the second dopant species. The third dopant species might provide a same conductivity type as the second dopant species. For example, the third dopant species might be phosphorus and the second implant energy level might be approximately 100-200 KeV, e.g., 150 KeV. One or more additional dopant species might be implanted at successively lesser energy implant energy levels prior to isotropically etching the patterned mask. The process might then optionally proceed to  789  of  FIG. 7 . 
     CONCLUSION 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments.