Patent Publication Number: US-10784119-B2

Title: Multiple patterning with lithographically-defined cuts

Description:
BACKGROUND 
     The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of self-aligned multiple patterning. 
     A back-end-of-line interconnect structure may be used to connect device structures, which were fabricated on a substrate during front-end-of-line processing, with each other and with the environment external to the chip. Self-aligned patterning processes used to form an interconnect structure involve linear mandrels acting as sacrificial features that establish a feature pitch. Non-mandrel lines are arranged as linear spaces between sidewall spacers that are formed adjacent to the sidewalls of the mandrels. After the mandrels are pulled to define mandrel lines, the sidewall spacers are used as an etch mask to etch a pattern predicated on the mandrel lines and the non-mandrel lines into an underlying hardmask. The pattern is subsequently transferred from the hardmask to an interlayer dielectric layer as trenches in which the wires of the interconnect structure are formed. 
     Mandrel cuts may be formed in the mandrels in order to section the mandrels and define discontinuities between the different sections. Non-mandrel cuts may also be formed along non-mandrel lines and may include portions of the spacer material used to form the sidewall spacers. The mandrel cuts and non-mandrel cuts are included in the pattern that is transferred to the hardmask and subsequently transferred from the hardmask to form the trenches in the interlayer dielectric layer. The mandrel cuts and non-mandrel cuts appear in the interconnect structure as adjacent wires that are spaced apart at their tips with a tip-to-tip spacing related to the dimension of the discontinuity. 
     The tip-to-tip spacing for the sections of a cut mandrel is limited to a distance equal to twice the thickness of the sidewall spacers. If the tip-to-tip spacing is greater than this distance, the sidewalls spacers do not merge between the tips of the sections of the mandrel, which results in incomplete filling of the mandrel cut. Transverse to the length of the cut mandrel, the mandrel cut is arranged in the pattern laterally between non-mandrel lines that flank the cut mandrel line. The result of the incomplete filling can be a conductive link shorting wires in the BEOL interconnect structure formed using the non-mandrel lines at opposite side edges of the mandrel cut. 
     Even if the filling of the mandrel cut is complete, the wrapping of the sidewall spacers about the tips of the sections of the cut mandrel may introduce notches or indents at the side edges of the merged sidewall spacers. These notches or indents appear in the interconnect structure as kinks that project from the side edges of wires formed using the non-mandrel lines flanking the mandrel cut. The proximity of these kinks to each other may also result in shorting. 
     Improved methods of self-aligned multiple patterning are therefore needed. 
     SUMMARY 
     In an embodiment of the invention, a method includes depositing a hardmask over an interlayer dielectric layer, forming a first mandrel and a second mandrel over the hardmask, depositing a conformal spacer layer over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel, and forming a planarizing layer over the first mandrel, the second mandrel, and the hardmask. The method further includes patterning the planarizing layer to form a first trench that exposes a first lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel and a second trench that exposes a second lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel. A portion of the patterned planarizing layer covers a third lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel. After patterning the planarizing layer, the first lengthwise portion and the second lengthwise portion of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. The third lengthwise portion of the conformal spacer layer is masked during the etching process by the portion of the planarizing layer and defines a non-mandrel etch mask. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals are used to indicate like features in the various views. 
         FIGS. 1-11  are cross-sectional views of a structure at successive fabrication stages of a processing method in accordance with embodiments of the invention. 
         FIG. 1A  is a top view of the structure at the fabrication stage of  FIG. 1  in which  FIG. 1  is taken generally along line  1 - 1 . 
         FIG. 3A  is a top view of the structure in which  FIG. 3  is taken generally along line  3 - 3 . 
         FIG. 4A  is a top view of the structure in which  FIG. 4  is taken generally along line  4 - 4 . 
         FIG. 5A  is a top view of the structure in which  FIG. 5  is taken generally along line  5 - 5 . 
         FIG. 6A  is a top view of the structure in which  FIG. 6  is taken generally along line  6 - 6 . 
         FIG. 8A  is a top view of the structure in which  FIG. 8  is taken generally along line  8 - 8 . 
         FIG. 11A  is a top view of the structure in which  FIG. 11  is taken generally along line  11 - 11 . 
         FIGS. 12-14  are cross-sectional views of a structure at successive fabrication stages of a processing method in accordance with alternative embodiments of the invention. 
         FIG. 12A  is a top view of the structure in which  FIG. 12  is taken generally along line  12 - 12 . 
     
    
    
     DETAILED DESCRIPTION 
     With reference to  FIGS. 1, 1A  and in accordance with embodiments of the invention, an interlayer dielectric layer  10  may be composed of one or more electrically-insulating dielectric materials, such as a low-k dielectric material formed using a siloxane such as octamethylcyclotetrasiloxane (OMCTS). The interlayer dielectric layer  10  may be located on a substrate that includes device structures fabricated by front-end-of-line (FEOL) processing to form an integrated circuit. A layer stack including a hardmask  12  and a hardmask  14  is arranged over the interlayer dielectric layer  10  with the hardmask  12  arranged in a vertical direction between the interlayer dielectric layer  10  and the hardmask  14 . The layer stack may include an additional hardmask (not shown) composed of a dielectric material, such as silicon-oxygen nitride, between the hardmask  12  and the interlayer dielectric layer  10 . 
     The hardmasks  12 ,  14  are used to perform pattern transfer to the interlayer dielectric layer  10  during a self-aligned multiple patterning process, such as self-aligned double patterning (SADP). The hardmasks  12 ,  14  are composed of different materials characterized by dissimilar etch selectivities. The hardmask  12  may be composed of, for example, titanium nitride (TiN) or titanium oxide (TiO x ) deposited by, for example, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD). The hardmask  14  is removable from the hardmask  12  selective to the material of the hardmask  12 , and the hardmask  12  is removable from the interlayer dielectric layer  10  selective to the material of the interlayer dielectric layer  10 . The hardmask  14  may be composed of a dielectric material, such as silicon nitride (SiN), deposited by, for example, atomic layer deposition or chemical vapor deposition. As used herein, the terms “selective” and “selectivity” in reference to a material removal process (e.g., etching) denotes that the material removal rate (i.e., etch rate) for the targeted material is higher than the material removal rate (i.e., etch rate) for at least another material exposed to the material removal process. 
     Mandrels  16 ,  18 ,  20  are formed from a layer of material that is deposited on a top surface of the hardmask  14 . For example, lithography and etching processes may be used to pattern an etch mask with an etching process, which is used in turn to pattern the mandrels  16 ,  18 ,  20  with another etching process. The layer used to form the mandrels  16 ,  18 ,  20  may be composed of amorphous silicon (α-Si), amorphous carbon (α-C), or a spin-on hardmask (SOH). The etch mask used to pattern the mandrels  16 ,  18 ,  20  may be removed after patterning the mandrels  16 ,  18 ,  20 . Each of the mandrels  16 ,  18 ,  20  has a length, L 1 , and a width, W 1 , in a direction transverse to the length, L 1 . 
     With reference to  FIG. 2  in which like reference numerals refer to like features in  FIG. 1  and at a subsequent fabrication stage of the processing method, a conformal spacer layer  22  composed of a dielectric material is subsequently deposited using, for example, atomic layer deposition over the mandrels  16 ,  18 ,  20  and exposed areas of the hardmask  14 . The material constituting the conformal spacer layer  22  may be chosen so as to be removed by a given etch chemistry selective to the material of the mandrels  16 ,  18 ,  20 . For example, if the mandrels  16 ,  18 ,  20  are composed of amorphous silicon, the dielectric material constituting the conformal spacer layer  22  may be composed of a dielectric material such as titanium oxide (TiO x ) or silicon dioxide (SiO 2 ). 
     With reference to  FIGS. 3, 3A  in which like reference numerals refer to like features in  FIG. 2  and at a subsequent fabrication stage of the processing method, a planarizing layer  24  and a hardmask layer  25  are formed over the conformal spacer layer  22 . The planarizing layer  24 , which has a planar top surface, may be a spin-on hardmask that is composed of an organic material. In an embodiment, the organic material contained in the planarizing layer  24  may be a polymer that is carbon-based. In an embodiment, the organic material contained in the planarizing layer  24  may be an organic planarization layer (OPL) material. The planarizing layer  24  provides gap fill between the mandrels  16 ,  18 ,  20 , and has a thickness that is sufficient to cover and bury the mandrels  16 ,  18 ,  20  and conformal spacer layer  22 . The hardmask layer  25  may be composed of a dielectric material, such as silicon-oxygen nitride (SiON). 
     An etch mask  30  is formed over the hardmask layer  25  and the planarizing layer  24  by a lithography process. The etch mask  30  may include a lithography stack containing a photoresist and a bottom anti-reflection coating in which the photoresist may be applied as a fluid by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer, and in which the bottom anti-reflection coating may be applied before the photoresist is applied and patterned after the photoresist is developed. The etch mask  30  includes openings  31  that are arranged in a pattern of parallel lines, as well as a portion of a given length and width that covers an area on a top surface of the hardmask layer  25  that is arranged over a portion of the conformal spacer layer  22  between the mandrel  18  and the mandrel  20 . Other portions of the etch mask  30  cover respective areas on the top surface of the hardmask layer  25  that are arranged over the full lengths of the mandrels  16 ,  18 ,  20 . 
     With reference to  FIGS. 4, 4A  in which like reference numerals refer to like features in  FIG. 3  and at a subsequent fabrication stage of the processing method, the hardmask layer  25  and the planarizing layer  24  are patterned by an etching process to form trenches  32  that penetrate through the planarizing layer  24  at the locations of the openings  31  in the etch mask  30 . The etch mask  30  may be removed during the etching process transferring the pattern of trenches  32  to the planarizing layer  24 . The hardmask layer  25  may be removed after transferring the pattern of trenches  32  to the planarizing layer  24 . The trenches  32  and openings  31  are aligned in that their respective inner boundaries are continuous or substantially continuous. 
     The conformal spacer layer  22  is etched by another etching process where exposed by the trenches  32  to form sidewall spacers  26  adjacent to the mandrels  16 ,  18 ,  20  and to remove unmasked sections  20   b  of the conformal spacer layer  22  from the hardmask  14  over non-mandrel lines  28  between the sidewall spacers  26 . The sidewall spacers  26  are arranged adjacent to the vertical sidewalls of the mandrels  16 ,  18 ,  20 . The etching process may be an anisotropic etching process, such as reactive ion etching (RIE), that removes the material of the conformal spacer layer  22  selective to the materials of the mandrels  16 ,  18 ,  20  and the hardmask  14 . The sidewall spacers  26  have a thickness, t 1 , that may be nominally equal to the thickness of the conformal spacer layer  22 . 
     Non-mandrel lines  28  are defined as linear spaces or gaps arranged between the sidewall spacers  26  on the mandrels  16 ,  18 ,  20 . Portions  15  of the hardmask  14  are revealed along the non-mandrel lines  28  by the removal of unmasked sections  22   b  of the conformal spacer layer  22 . The planarizing layer  24  also includes a section, generally indicated by reference numeral  44 , that covers a lengthwise section  22   a  of the conformal spacer layer  22  over one of the non-mandrel lines  28 . A portion of the covered lengthwise section  22   a  of the conformal spacer layer  22  defines a non-mandrel cut mask  34 , which provides a mechanism for forming a non-mandrel cut that ultimately appears as a tip-to-tip cut between subsequently-formed interconnects. The non-mandrel cut mask  34  has a length, L 2 , and a width, w 2 , and is arranged over a portion  17  of the hardmask  14  of commensurate dimensions. The planarizing layer  24  also masks or covers the conformal spacer layer  22  over the mandrels  16 ,  18 ,  20  during the etching process forming the sidewall spacers  26 . Following the anisotropic etching process, planarizing layer  24  may be removed, and residual sections of the conformal spacer layer  22  are arranged over the mandrels  16 ,  18 ,  20  as a result of the masking. 
     With reference to  FIGS. 5, 5A  in which like reference numerals refer to like features in  FIG. 4  and at a subsequent fabrication stage of the processing method, a planarizing layer  36  and a hardmask layer  38  are formed over the mandrels  16 ,  18 ,  20 , the sidewall spacers  26 , the non-mandrel cut mask  34 , and areas of the hardmask  14  exposed by the non-mandrel lines  28 . The planarizing layer  36 , which has a planar top surface  36   a , may be a spin-on hardmask that is composed of an organic material. In an embodiment, the organic material contained in the planarizing layer  36  may be a polymer that is carbon-based. In an embodiment, the organic material contained in the planarizing layer  36  may be an organic planarization layer (OPL) material. The planarizing layer  36  provides gap fill of the gaps between the sidewall spacers  26  on the mandrels  16 ,  18 ,  20 , and has a thickness that is sufficient to cover and bury the mandrels  16 ,  18 ,  20  and sidewall spacers  26 . The planarizing layer  36  may be deposited in multiple stages including an initial stage in which a deposited layer is recessed. The hardmask layer  38  may be composed of a dielectric material, such as silicon-oxygen nitride (SiON). 
     An etch mask  40  is formed over the hardmask layer  38  and the planarizing layer  36  by a lithography process. The etch mask  40  may include a lithography stack containing a photoresist and a bottom anti-reflection coating in which the photoresist may be applied as a fluid by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer, and in which the bottom anti-reflection coating may be applied before the photoresist is applied and patterned after the photoresist is developed. The etch mask  40  includes openings  41  that are arranged with a layout in an inversed pattern that matches the pattern of the mandrels  16 ,  18 ,  20 . A portion of the etch mask  40  covers an area on a top surface of the hardmask layer  38  that is arranged over the entire width of a lengthwise section of the mandrel  18 , which subsequently provides a mandrel cut in the interconnect layout. 
     With reference to  FIGS. 6, 6A  in which like reference numerals refer to like features in  FIG. 5  and at a subsequent fabrication stage of the processing method, the hardmask layer  38  and the planarizing layer  36  are patterned by an etching process that forms trenches  43  that penetrate through the planarizing layer  36  at the locations of the openings  41  in the etch mask  40 . The trenches  43  expose the conformal spacer layer  22  over the mandrels  16 ,  18  and the conformal spacer layer  22  over unmasked lengthwise sections  20   b  of the mandrel  20 . Residual sections of the conformal spacer layer  22  exposed by the trenches  43  are etched and removed. The etch mask  40  may be removed during the etching process transferring the pattern of trenches  43  to the planarizing layer  36 . The hardmask layer  38  may be removed after transferring the pattern of trenches  43  to the planarizing layer  36 . The trenches  43  and openings  41  are aligned in that their respective inner boundaries are continuous or substantially continuous. 
     The trenches  43  in the planarizing layer  36  expose (i.e., reveal) the mandrel  16 , the mandrel  18 , and the unmasked lengthwise sections  20   b  of the mandrel  20  for subsequent removal. The trenches  43  have a width that is equal to or substantially equal to the width, W 1 , of the mandrels  16 ,  18 ,  20 . The planarizing layer  36  also includes a section, generally indicated by reference numeral  42 , that covers a lengthwise section  20   a  of the mandrel  20 . Only a fraction of the length, L 1 , of the mandrel  20  is overlapped in a lengthwise direction by the length, L 3 , of the section  42  of the planarizing layer  36 . The masked lengthwise section  20   a  of the mandrel  20  is arranged along the length of the mandrel  20  between the adjacent unmasked lengthwise sections  20   b  of the mandrel  20 . The masked lengthwise section  20   a  of the mandrel  20  provides a mechanism for forming a mandrel cut that ultimately appears as a tip-to-tip cut between subsequently-formed interconnects. The planarizing layer  36  also covers the sidewall spacers  26  and the non-mandrel cut mask  34  during the etching process forming the trenches  43 . 
     With reference to  FIG. 7  in which like reference numerals refer to like features in  FIG. 6  and at a subsequent fabrication stage of the processing method, the mandrel  16 , the mandrel  18 , and the unmasked lengthwise sections  20   b  ( FIG. 6A ) of the mandrel  20  are pulled and removed selective to the planarizing layer  36  with an etching process having a suitable etch chemistry. The patterned planarizing layer  36  masks the sidewall spacers  26 , the non-mandrel cut mask  34 , and the lengthwise section  20   a  of the mandrel  20  during the etching process. The trenches  43  in the planarizing layer  36  provide access for the etching process. Mandrel removal generates mandrel lines  46  that are arranged between the sidewall spacers  26  as linear spaces and over which strips of the hardmask  14  are revealed. The non-mandrel lines  28  and the mandrel lines  46  may have a parallel arrangement and alternate in a direction transverse to their respective lengths. 
     The section  42  of the planarizing layer  36  masks and covers the lengthwise section  20   a  ( FIG. 6A ) of the mandrel  20 , which is preserved and not pulled, arranged along the length of one of the mandrel lines  46 . The unetched lengthwise section  20   a  of the mandrel  20  interrupts and cuts the continuity of one of the mandrel lines  46 , and divides this mandrel line  46  into discrete sections separated by the lengthwise section  20   a  of the mandrel  20 . The unetched lengthwise section  20   a  of the mandrel  20  covers a portion  21  of the hardmask  14 . The removal of the lengthwise sections  20   b  of the mandrel  20  exposes respective portions  23  of the hardmask  14  that are arranged along the length of the associated mandrel line  46 . The portion  21  of the hardmask  14  is arranged along the length of the associated mandrel line  46  between the portions  23  of the hardmask  14 . Unbroken portions  27  of the hardmask  14  are exposed along the mandrel lines  46  after removing mandrels  16 ,  18 . 
     With reference to  FIGS. 8, 8A  in which like reference numerals refer to like features in  FIG. 7  and at a subsequent fabrication stage of the processing method, the planarizing layer  36  is removed by, for example, ashing using an oxygen plasma and/or an etching process. The unetched lengthwise section  20   a  of the mandrel  20  defines the location of a mandrel cut between a pair of linearly-aligned metal interconnects subsequently formed in the interlayer dielectric layer  10  using the sections of the associated mandrel line  46  formerly covered by the removed lengthwise sections  20   b  ( FIG. 6A ) of the mandrel  20 . The length of the unetched lengthwise section  20   a  of the mandrel  20  in a direction parallel to the length of the sections of the associated mandrel line  46  is equal to the length, L 3 , of the section  42  of the planarizing layer  36 , and subsequently determines a tip-to-tip spacing or distance between the tips or ends of the metal interconnects terminating at the unetched lengthwise section  20   a  of the mandrel  20  and facing each other across the length of the unetched section of the mandrel  20 . 
     The tip-to-tip spacing between the ends of the sections of the cut mandrel line  46 , which is defined independent of the formation of the sidewall spacers  26 , may be greater than a distance equal to twice the thickness of the sidewall spacers  26 . The tip-to-tip spacing between the ends of the sections of the cut mandrel line  46  may be varied by selecting the length, L 3 , of the section  42  of the planarizing layer  36 , and provides for variable-space mandrel cuts that can be produced independent of spacer thickness. The formation of the trenches  43  and subsequent mandrel pull decouples the formation of the mandrel cut in the mandrel line  46  from the wrapping of the sidewall spacers  26  about the tips of the divided sections of the mandrel  18 . As a result, kinking may be eliminated and the probability is reduced that interconnects in the BEOL interconnect structure formed using the non-mandrel lines  28  will be shorted as a consequence of kinking. 
     With reference to  FIG. 9  in which like reference numerals refer to like features in  FIG. 8  and at a subsequent fabrication stage of the processing method, the pattern including the non-mandrel lines  28  and mandrel lines  46  is transferred to the hardmask  14  by an etching process that removes unmasked portions of the hardmask  14 . The non-mandrel lines  28  and mandrel lines  46  are arranged between the sidewall spacers  26 , which cover areas of the hardmask  14  during the etching process. The unetched lengthwise section  20   a  ( FIG. 6A ) of the mandrel  20  masks a portion of the hardmask  14  along a lengthwise section of one of the mandrel lines  46  and the non-mandrel cut mask  34  masks a portion of the hardmask  14  along a lengthwise section of one of the non-mandrel lines  28 . The non-mandrel lines  28  and mandrel lines  46  extend through the full thickness of the hardmask  14 , and the material of the hardmask  12  may function as an etch stop for the etching process. The conformal spacer layer  22  over the lengthwise section  20   a  of mandrel  20  may be removed during the patterning of the hardmask  14  or by performing a separate etching process. 
     With reference to  FIG. 10  in which like reference numerals refer to like features in  FIG. 9  and at a subsequent fabrication stage of the processing method, the unetched lengthwise section  20   a  ( FIG. 6A ) of the mandrel  20  is removed with an etching process selective to the sidewall spacers  26  and the exposed material of the hardmask  12 . The hardmask  12  is then patterned by an etching process to transfer the pattern including the non-mandrel lines  28 , mandrel lines  46 , and cuts embodied by the non-mandrel cut mask  34  and the portion of the hardmask  12  formerly covered by the lengthwise section  20   a  of mandrel  20  from the hardmask  14  to the hardmask  12 . The patterned hardmask  14  operates as an etch mask during pattern transfer to the hardmask  12 . The etching process may stop on the dielectric material of the interlayer dielectric layer  10 , and the non-mandrel lines  28  and mandrel lines  46  extend through the full thickness of the hardmask  12  other than at the locations of the respective cuts. 
     With reference to  FIGS. 11, 11A  in which like reference numerals refer to like features in  FIG. 10  and at a subsequent fabrication stage of the processing method, the interlayer dielectric layer  10  is then patterned by an etching process with the patterned hardmask  12 , and optionally the patterned hardmask  14 , operating as an etch mask to transfer the pattern of non-mandrel lines  28  and mandrel lines  46  with cuts from the hardmask  12  to the interlayer dielectric layer  10  as a pattern of trenches  52 . A back-end-of-line interconnect structure  50  is formed by filling the trenches  52  in the interlayer dielectric layer  10  with one or more conductors to form interconnects  54 ,  56  as features in the form of wires that are embedded in the interlayer dielectric layer  10 . The interconnects  54  are formed in the interlayer dielectric layer  10  along the mandrel lines  46  in the transferred pattern, and the interconnects  56  are formed in the interlayer dielectric layer  10  along the non-mandrel lines  28  in the transferred pattern. 
     The primary conductor of the interconnects  54 ,  56  may be composed of a low-resistivity metal formed using a deposition process, such as copper (Cu) or cobalt (Co) deposited by, for example, electroplating or electroless deposition or chemical vapor deposition. A liner (not shown) composed of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a layered combination of these materials (e.g., a bilayer of TaN/Ta) may be applied to the trenches  52  before filling with a primary electrical conductor. In an embodiment, the interconnects  54 ,  56  may be conductive features located in a metallization level that is the closest of multiple metallization levels of the back-end-of-line interconnect structure  50  to the device structures and substrate, and in which the interconnects  54 ,  56  may be connected with the device structures by contacts in an intervening contact level. 
     The interlayer dielectric layer  10  includes a non-mandrel cut  57 , which is arranged between a pair of the interconnects  56 , that represents a preserved section of dielectric material of the interlayer dielectric layer  10  masked by a portion of the hardmask  12  that was formerly covered by the non-mandrel cut mask  34 . The divided interconnects  56  have a tip-to-tip spacing, d 1 , between their respective ends given by a dimension of the non-mandrel cut  57  parallel to the length, L 4 , of the interconnects  56 . The length, L 2 , of the non-mandrel cut mask  34  is equal to the tip-to-tip spacing, d 1 . 
     The interlayer dielectric layer  10  also includes a mandrel cut  55 , which is arranged between a pair of the interconnects  54 , that represents a preserved section of dielectric material of the interlayer dielectric layer  10  masked by a portion of the hardmask  12  during the etching process that was formerly covered by the section  42  of the planarizing layer  36 . The divided interconnects  54  have a tip-to-tip spacing, d 2 , between their respective ends given by a dimension of the mandrel cut  55  parallel to the length, L 4 , of the interconnects  54 . The length, L 3 , of the lengthwise section  20   a  of the mandrel  20  is equal to the tip-to-tip spacing, d 2 . 
     The tip-to-tip spacing, d 1 , for the non-mandrel cut  57  in the interconnect  54  may be greater than the tip-to-tip spacing, d 2 , for the mandrel cut  55  in the interconnect  54 . The tip-to-tip spacing, d 2 , for the mandrel cut  55  in the interconnect  54  is not limited to a distance equal to twice the thickness of the sidewall spacers  26 . As a result, the tip-to-tip spacing of the interconnects  54  can exceed the spacer-related distance without any susceptibility to shorting. The tip-to-tip spacing for the mandrel cut  55  is a variable space that can be selected as part of the device design. In addition, because the sidewall spacers  26  do not have to wrap about the tips of the sections of the cut mandrel  20 , indents are absent that could otherwise produce kinks at the side edges of the interconnects adjacent into the mandrel cut  55 . 
     With reference to  FIGS. 12, 12A  in which like reference numerals refer to like features in  FIGS. 1, 1A  and in accordance with an alternative embodiment of the processing method, the mandrel  18  may be shortened by removing a lengthwise section  18   a  with lithography and etching processes. A portion of the hardmask  14  is exposed by the removal of the lengthwise section  18   a  of the mandrel  18 . The mandrel  16  and mandrel  20 , as well as the non-removed section of mandrel  18 , may be masked during the etching process. 
     With reference to  FIG. 13  in which like reference numerals refer to like features in  FIG. 12  and at a subsequent fabrication stage of the processing method, the conformal spacer layer  22  is deposited as described in the context of  FIG. 2 . Over the area in which the section  18   a  ( FIG. 12A ) of the mandrel  18  is removed, the conformal spacer layer  22  deposits on the hardmask  14  in the space between the mandrel  16  and the mandrel  20 . The planarizing layer  24 , hardmask layer  25 , and etch mask  39  are formed as described in the context of  FIG. 3 . The etch mask  30  includes a section  30   a  that is spaced by an opening with a width, w 3 , from a portion of the conformal spacer layer  22  adjacent to the sidewall of the mandrel  20  that is shaped to form one of the sidewall spacers  26 . The section  30   a  of the etch mask  30  has a given length in a direction transverse to its width. The width, w 3 , is greater than the width of the non-mandrel lines  28  ( FIG. 14 ). 
     With reference to  FIG. 14  in which like reference numerals refer to like features in  FIG. 13  and at a subsequent fabrication stage of the processing method, the patterning of the layers  24 ,  25 , as described in the context of  FIGS. 4, 4A , forms stacked sections  24   a ,  25   a  of a given length and width at the location of the section  30   a  of the etch mask  30 . Over a section  28   a  of one of the non-mandrel lines  28  that is positioned adjacent to the stacked sections  24   a ,  25   a , a trench  49  is formed that exposes a lengthwise portion of the hardmask  14  also having the width, w 3 . This section  28   a  of the non-mandrel line  28  has a length that is equal or approximately equal to the length of the removed section  18   a  of the mandrel  18 , and a width that is equal or approximately equal to the width, w 3 . Over the remainder of its length, this particular non-mandrel line  28  has dimensions established by the spacing between adjacent sidewall spacers  26 . The conformal spacer layer  22  is protected and preserved over the area covered by the stacked sections  24   a ,  25   a  of layers  24 ,  25  adjacent to the trench  49 , which is established by the dimensions of the section  30   a  of the etch mask  30 . 
     The layers  24 ,  25 , including the stacked sections  24   a ,  25   a , are removed prior to the performance of  FIG. 5 . Processing continues as described in  FIGS. 5-11  with the section  28   a  of the non-mandrel line  28  being transferred in the pattern as a widened portion of one of the interconnects  56  that is formed in an manner that is unguided at one of its side edges (i.e., the side edge adjacent to the stacked sections  24   a ,  25   a  that are removed) because of the absence of the sidewall spacer due to the partial removal of the lengthwise section  18   a  of the mandrel  18 . 
     The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones. 
     References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/−10% of the stated value(s). 
     References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane. 
     A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.