Patent Publication Number: US-2009223832-A1

Title: Method and Apparatus for Preventing Galvanic Corrosion in Semiconductor Processing

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to European Patent Application EP 08150201.5 filed in the EPO Patent Office on Jan. 11, 2008, the entire contents of which is incorporated herein by reference. 
     BACKGROUND 
     1. Field of the Invention 
     The invention is related to semiconductor processing, in particular to wet cleaning processes. The invention is concerned with the prevention of galvanic corrosion of (semi)conductor structures during such process steps. 
     2. Description of the Related Art 
     In integrated circuit process technology, a silicon wafer is subjected to a series of process steps referred to as Front End Of Line processing (FEOL), which refers to the steps taking place up to and not including the first metallization steps. During FEOL, metal/polysilicon gate structures are produced on the wafer by known production techniques. With CMOS devices scaling beyond the 65 nm node, short channel effects become dominant, leading to high leakage currents. Non-planar device architectures such as Multiple Gate Field Effect Transistor (MUGFET) and in particular the double gated MUGFET structure known as FinFET are considered to overcome this effect. However, these structures represent a challenge in terms of gate patterning and processing. In the case of metal gate FinFET structures, in order to avoid severe recess of the buried field oxide, etching of the gate stack is performed in two steps, wherein a metal layer acts as etch stop layer during the first step. As a result, the wafer surface comprises polySi-stacks, surrounded by and in electrical contact with a metal layer covering the whole of the wafer surface. At this stage, the wafer needs to undergo a cleaning treatment, in order to remove residues from the preceding etch steps. Such cleaning typically takes place in an aqueous HF (Hydrofluoric acid) solution, which is an electrolytic solution. This combination however leads to corrosion of the polySi-structures, due to the phenomenon of galvanic corrosion. Because of the difference in electrochemical potential of the polysilicon and the surrounding metal, a galvanic cell is generated between these two materials, leading to a spontaneous oxidation-reduction reaction. While the metal acts a cathode, the polysilicon will act as the anode, and will thus be subjected to a forced and unwanted oxidation (i.e. corrosion), during the HF treatment. Specifically, the PolySi structures are underetched by the corrosion. 
     The same problem may occur during other processes where during a stage of the process, semiconductor or other structures comprising a first conductive material are produced on a wafer surface, and are surrounded by and in contact with a layer of a second conductive material, such as a metal layer, said contact taking place between said first and second material. 
     SUMMARY 
     The invention aims to provide a method and apparatus for cleaning a semiconductor substrate comprising structures surrounded by and in electrical contact with a conducting or semiconducting layer covering substantially the whole of the substrate surface, wherein corrosion of said structures is prevented. 
     The invention is firstly related to a method for cleaning a semiconductor substrate comprising on a surface of the substrate at least one structure comprising a first conducting or semiconducting material, surrounded by a layer of a second conducting or semiconducting material, said layer essentially extending over the totality of said surface, said first and second material being in physical contact, the method comprising the steps of:
         providing said substrate,   positioning a counter-electrode facing said substrate surface,   supplying an electrolytic fluid to the space between said surface and the electrode, said counter-electrode acting as an anode in the galvanic cell defined by the substrate surface, the cleaning fluid and the counter-electrode.       

     Furthermore, the invention is related to apparatus for cleaning a semiconductor substrate, while protecting a surface of the substrate by a cathodic protection mechanism, said apparatus comprising:
         a holder for holding a substrate, said holder comprising a means for clamping said substrate ( 1 , 13 ),   at least one counter-electrode, arranged to be placed facing said substrate surface,   a means for supplying a cleaning fluid to the space between said counter-electrode and said surface.       

     Specific embodiments of the method and apparatus of the invention are disclosed in combinations of the independent claims with one or more of the dependent claims. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIGS. 1   a - 1   e  illustrate a typical field of application of the present invention. 
         FIG. 2  illustrates the method of the invention, applied to a wafer as shown in  FIG. 1   d.    
         FIG. 3  illustrates the design of an apparatus according to one embodiment of the invention. 
         FIG. 4  illustrates another embodiment of an apparatus according to the invention. 
         FIG. 5  illustrates a further embodiment, comprising multiple counter-electrodes. 
     
    
    
     DETAILED DESCRIPTION  
       FIG. 1   a - 1   e  illustrates one of the main fields of application of the invention, which concerns the FEOL processing steps during processing of CMOS (complementary metal-oxide-semiconductor) devices. Active areas (I, II) and shallow trench isolation (STI) areas  2  are defined on a substrate  1 . A gate stack is formed by depositing a gate dielectric  3 , a gate electrode  4 ,  5  and a hard mask layer  6  over the whole substrate ( FIG. 1   a ). The gate dielectric  3  comprises at least one layer of dielectric material. The gate electrode has conductive properties and comprises at least one layer of metal  4  and a layer of polysilicon (poly-Si) or amorphous silicon (a-Si)  5 , overlying the metal layer. The hardmask layer  6  overlying the polySi/a-Si layer can be a Si-based dielectric, such as silicon oxide, silicon nitride or silicon carbide. 
     In standard CMOS processing, a single etch step is performed to produce the gate stacks as shown in  FIG. 1   b.  In the case of FinFETs, the wet removal of the hardmask layer  6  causes severe recess of the buried field oxide. Therefore the etch sequence of the gate stack is modified and the gate is patterned in 2 steps. In a first step the hardmask  6  and the polySi  5  is patterned using a photoresist mask  7 , stopping on the metal layer  4  as shown in  FIG. 1   c  for simplicity on planar device architecture. Multi-step etching may be necessary in other cases as well, even when the field oxide protection is not the main consideration. Gate electrodes comprising multiple layers (poly and one or more metal layers for example) may require etching in two or more steps, the number of steps being in relation to the number of layers present. 
     After the first etch step, the photoresist  7  and the hardmask layer  6  are removed ( FIG. 1   d ). Wet cleaning solutions, most preferably HF-based solutions are used to remove the photoresist residues and the hardmask  6 . When the metal layer  4  comprises a noble metal and the cleaning solution used to remove the resist residues and the hardmask  6  is a HF-based mixture, an under-etching (attack) of the polysilicon layer  5  occurs, because of the galvanic corrosion effect, as shown in  FIG. 1   e.    
     In a second etch step (not shown), the metal layer  4  and the gate dielectric  3  are etched, using the polySi/a-Si layer  5  as mask layer. After gate patterning a conventional FEOL process flow comprises junction formation (implantation and thermal annealing), dielectric spacers definition and silicidation. 
       FIG. 1   d  therefore shows an example of a substrate which is treatable by the method or in the apparatus of the invention. It concerns a semiconductor substrate  1 , preferably Si, comprising at least one elevated semiconductor structure  5  on its surface, preferably a polySi stack or a plurality of polySi stacks. Said at least one structure is surrounded by a metal layer  4 , extending substantially over the entire surface of the substrate and being in electrical contact with the structures  5 . This type of substrate is typically an intermediate product during FEOL CMOS processing. Other applications are however possible. The term ‘surrounding’ means that the semiconductor structures may be present on top of a continuous metal layer (case shown in  FIG. 1   d ), or that the metal layer is adjacent to the structures (illustrated e.g. by  FIG. 2 ). In both cases, the metal layer and the structures are in electrical contact. 
     Generally, according to the invention, the structures  5  are structures comprising a first conducting or semiconducting material, e.g. comprising a layer of such a material, and said structures  5  are surrounded (as defined above) by a layer of a second conducting or semiconducting material (preferably metal), wherein the first and second material are in physical contact and have a mutually different electrochemical potential. The structures  5  may comprise multiple layers of metal and/or semiconductor material. Substrate  1  can comprise any semiconducting material including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP and other III/V semiconductor compounds. Semiconductor substrate  1  can also be a layered substrate comprising the same or different semiconducting material, e.g., Si/Si or Si/SiGe, as well as a silicon-on-insulator (SOI) substrate. 
     According to a preferred embodiment, illustrated by  FIG. 2 , the method of the invention comprises the steps of:
         Providing a substrate as described above, i.e. provided with said structure(s)  5  on its surface, surrounded by a layer of conducting or semiconducting material, preferably metal. For the sake of conciseness, the following description refers to semiconductor structures and a metal layer, but these terms can be replaced by ‘structures comprising first conducting or semiconducting material’ and ‘layer of second conducting or semiconducting material’, respectively, throughout the description.   Positioning a counter-electrode  20  facing said surface,   Supplying an electrolytic cleaning fluid  21  to the space between the substrate surface and the electrode,   Using and/or actively applying a voltage difference between the metal layer present on the substrate surface, and the counter-electrode. The voltage difference may be due to a difference in electrochemical potential between the metal layer  4  and the counter electrode  20 , or it may be obtained or further enhanced by a power source  22  connected between the counter-electrode and the metal layer.   The preceding steps are preferably followed by standard rinsing and/or drying steps to produce a clean substrate. During rinsing and/or drying steps the counter-electrode is not required: it can be removed from the cleaning chamber or the distance between the counter-electrode and the substrate can be increased.       

     The abovementioned electrochemical potential difference and/or the polarity of the voltage applied by the external power source are such that the counter-electrode works as an anode in the galvanic cell defined by the substrate surface comprising metal layer and semiconductor structures, the fluid and the counter-electrode. The entire metal covered surface of the substrate then works as a cathode. In this way, cathodic protection of the metal layer  4  and of the semiconductor structures  5  is obtained. When an external voltage is applied, impressed current cathodic protection (ICCP) takes place. 
     The counter-electrode is ‘facing’ the substrate surface, in other words: the counter-electrode has a surface which is put at a given distance from the substrate surface so that the counter-electrode surface covers at least a portion of the substrate surface. The distance is preferably relatively short (order of mm). The invention is thus not related to embodiments wherein a counter-electrode is present in a separate container. According to one embodiment, the counter-electrode is flat, preferably circular-shaped, and positioned essentially parallel to the substrate surface which can be the surface of a circular semiconductor wafer. As explained later, the counter-electrode can equally have a concave-like surface. Another embodiment is related to multiple electrodes arranged at various distances over the surface. 
     The electrolytic cleaning fluid can be a liquid or a mixture of a liquid and a gas. For example in the case of FEOL CMOS processing, an aqueous HF solution may be used. This solution can be mixed with nitrogen gas. The cleaning fluid comprises substantially no metal ions. 
     In the method of the invention, a cleaning fluid is supplied to the space between the substrate and the counter-electrode. According to the preferred embodiment, this supply involves a continuous movement of cleaning fluid over the surface of the substrate. This can be obtained by supplying fluid in one or more locations, e.g. through nozzles, and draining the fluid at other locations, e.g. at the edges of the substrate. During the cleaning step, the substrate is preferably rotated. The rotation speed may be up to 2000 rpm. 
       FIG. 3  is a schematic view of an apparatus according to the invention. The apparatus comprises a support portion  10 , provided with a number of clamping and contact pins  11 . Four pins are shown in the drawing but more are possible. The pins are provided with a contact surface  12  that contacts the upper surface of a wafer/substrate  13 . While being contacted thus, the wafer is clamped between the pins in an adequate manner. Above the wafer surface, the counter-electrode  20  is present. The counter-electrode in this embodiment is circular and essentially concentrically positioned with respect to the equally circular wafer. Other shapes of the substrate and electrode are possible. A power source  22  is connected between the pins  11  and the counter electrode  20 . A means for supplying a cleaning fluid is provided, for example a nozzle  14 . In the embodiment of  FIG. 3 , a central opening  15  is provided in the counter-electrode  20 , and the nozzle  14  is arranged to supply fluid centrally through said central opening  15 . Said cleaning fluid is thus induced to flow outward from the central opening towards the edges of the wafer, where it is drained in an appropriate way, as indicated by the arrows in  FIG. 3 . Other ways of supplying the fluid to the space between the wafer and the counter-electrode can be imagined by the skilled person, and are within the scope of the present invention. 
     The support portion  10  may be rotatable, in which case adequate measures need to be taken to ensure the contact between the rotating pins  11  and the power source  22 . The pins and the wafer are rotating together as one piece. The rotation speed may be up to 2000 RPM. 
     According to another embodiment, the counter-electrode  20  has a specially designed and optimized cross section towards the wafer surface (for instance a concave-like shape), as shown in  FIG. 4 . This embodiment is apt to diminish an overprotection taking place at the wafer&#39;s edges. With a flat counter-electrode, the protection can be non-uniform over the wafer because of the non-uniform resistivity of the metal layer. The potential drop at the wafer surface from the edge to the center can be decreased by an optimized counter electrode shape, such as the shape shown in  FIG. 4 . In this particular embodiment, the distance between the wafer and the counter-electrode is substantially constant on a central portion of the wafer, and is diverging on an external portion of the wafer. Other shapes of the electrode are possible, as can be appreciated by the skilled person. 
     The size and number of counter-electrodes can also differ from the embodiment shown in  FIG. 4 . A single electrode of smaller size can be positioned to protect only a portion of the wafer surface. 
       FIG. 5  shows another possible embodiment, comprising a set of different counter-electrodes  30 , arranged in a grid, each electrode facing the wafer surface, each electrode being connected to the wafer surface via the power source  22 . In this embodiment, means are advantageously provided to adjust the vertical position of the individual electrodes with respect to the wafer surface, in order to position electrodes at the optimum distance from the wafer surface. For example, electrodes placed on the outer circumference of the wafer surface may be positioned at a larger distance from the wafer than electrodes placed in the center (as illustrated in  FIG. 5 ). This embodiment also allows to minimize the influence of the hydrodynamics of the cleaning fluid, which might be more likely to interfere with the cleaning performance when one massive counter-electrode is used. The embodiment with multiple counter-electrodes arranged in a grid allows the possibility to use a scanning nozzle that can provide the cleaning fluid through the openings of the grid. 
     According to another embodiment, the wafer and the counter-electrode are submerged together in a bath of the cleaning fluid. 
     In the method and apparatus of the invention, the counter-electrode  20  is preferably essentially inert to the cleaning fluid, so that substantially no contamination of the substrate is generated. In the case of HF, the counter-electrode can be a platinum electrode or a platinum-covered electrode (e.g. a semiconductor material/wafer covered with a layer of platinum). Applied current densities may be between 100 mA/m2 and 1 A/m2. 
     The present invention can be applied in different areas. There are applications for logic and for memory circuits. For logic, this is the metal gate/poly coupling in HF as described above or double metal gate stacks applications. For memory, the gate stack may have an additional layer (for instance W) to increase the conductivity. 
     The invention is related to the processing of any conductive stack by sequence of dry etching and cleaning (under cathodic protection), avoiding the corrosion (in particular galvanic enhanced corrosion) during the cleaning, leading to a well defined gate profile.