Patent Publication Number: US-9847760-B1

Title: Switched capacitor gain stage

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority from India provisional patent application No. 201641020736 filed on Jun. 13, 2016 which is hereby incorporated by reference in its entirety. 
     TECHNICAL FIELD 
     The present disclosure is generally related to an analog signal chain and more particularly to a switched capacitor gain stage circuit used in the analog signal chain. 
     BACKGROUND 
     Recent advancements in analog signal chain require gain stages that are capable of amplifying a wide dynamic range of analog input signals. A switched capacitor gain stage is widely used in analog signal chain. In the switched capacitor gain stage, the analog input signal is sampled in one phase, called the sampling phase, and then gained up in another phase, called the hold phase. 
     However, there are certain constraints associated with the switched capacitor gain stage. The switched capacitor gain stage is required to settle within the hold phase, and a final settled value is required to be linear. In applications which require multiple switched capacitor gain stages, a noise contribution of each stage is required to be minimal. All these limitations are very difficult to achieve especially in the case of RF ADCs where the frequency of operation is very high. 
     One conventional approach is to use a closed loop gain stage. The solution can support a large analog input signal swing but it is not a feasible solution when the frequency of operation is very high since it contains many poles inside the loop. Another approach is to use an open loop preamplifier. This solution can support reasonably high frequency of operation but it cannot support a large analog input signal swing and also provides an uncontrolled gain. 
     SUMMARY 
     According to an aspect of the disclosure, a circuit is disclosed. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block. 
    
    
     
       BRIEF DESCRIPTION OF THE VIEWS OF DRAWINGS 
         FIG. 1  illustrates a circuit; 
         FIG. 2  illustrates a circuit, according to an embodiment; 
         FIG. 3  illustrates a circuit, according to an embodiment; and 
         FIG. 4  is a flowchart to illustrate a method of operation of a circuit, according to an embodiment; and 
         FIG. 5  illustrates a transceiver, according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       FIG. 1  illustrates a circuit  100 . The circuit  100  includes a transistor  102 . The transistor  102  receives an input voltage Vin  104  through a first switch S 1   108 . The first switch S 1   108  is coupled to a gate terminal  102   g  of the transistor  102 . A capacitor C  110  is coupled to the first switch S 1   108  and the gate terminal  102   g  of the transistor  102 . One end of the capacitor C  110  is coupled to a ground terminal  126 . 
     A drain terminal  102   d  of the transistor  102  is coupled to a source voltage Vdd  118 . A source terminal  102   s  of the transistor  102  is coupled to an output terminal  114  and a current source  124 . One end of the current source  124  is coupled to the ground terminal  126 . 
     The operation of the circuit  100  illustrated in  FIG. 1  is explained now. The circuit  100  operates in a sample phase and a hold phase. In sample phase, the first switch S 1   108  is closed and the capacitor C  110  is charged to the input voltage Vin  104 . In the hold phase, the first switch S 1   108  is opened, and a voltage at the gate terminal  102   g  remains equal to the input voltage Vin  104 . An output voltage Vout generated at the output terminal  114  is equal to the voltage at the gate terminal  102   g  of the transistor  102 . Hence, the output voltage Vout is equal to the input voltage Vin  104 . The output voltage Vout follows the voltage at the gate terminal  102   g  of the transistor  102 . The circuit  100  is a low noise structure that also provides high bandwidth. 
       FIG. 2  illustrates a circuit  200 , according to an embodiment. The circuit  200  includes a gain stage block  202 . The gain stage block  202  is coupled to an input voltage Vin  204  through a first switch S 1   208 . A first capacitor C 1   220  is coupled between the first switch S 1   208  and a ground terminal  228 . A second capacitor C 2   222  is coupled between the first switch S 1   208  and a second switch S 2   212 . One end of the second switch S 2   212  is coupled to the ground terminal  228 . The first capacitor C 1   220  and the second capacitor C 2   222  are coupled to the gain stage block  202 . 
     A third switch S 3   216  is coupled between the second capacitor C 2   222  and a fixed terminal  206  of the gain stage block  202 . The gain stage block  202  includes a transistor  230 . A gate terminal  230   g  of the transistor  230  receives the input voltage Vin  204  through the first switch S 1   208 . A drain terminal  230   d  of the transistor  230  is coupled to a source voltage Vdd  210 . A source terminal  230   s  of the transistor  230  is coupled to an output terminal  234  and a current source  226 . One end of the current source  226  is coupled to the ground terminal  228 . 
     The fixed terminal  206  of the gain stage block  202  is coupled to at least one of an output terminal and an intermediate terminal of the gain stage block  202 . As illustrated in  FIG. 2 , the fixed terminal  206  is coupled to the output terminal  234  of the gain stage block  202 . The circuit  200  may include one or more additional components known to those skilled in the relevant art and are not discussed here for simplicity of the description. 
     The operation of the circuit  200  illustrated in  FIG. 2  is explained now. The circuit  200  operates in a sampling mode and a hold mode. In sampling mode, the first switch S 1   208  and the second switch S 2   212  are closed. The third switch S 3   216  is opened. The first capacitor C 1   220  and the second capacitor C 2   222  are charged to the input voltage Vin  204 . 
     In the hold mode, the first switch S 1   208  and the second switch S 2   212  are opened while the third switch S 3   216  is closed. The second capacitor C 2   222  gets discharged and all of its charge goes to the first capacitor C 1   220 . Thus, the first capacitor C 1   220  is charged to a third voltage (Vt) which is defined as follows:
 
 Vt =( C   1   +C   2 )* V   in   /C   1   (1)
 
The above equation 1 assumes that a gain of the gain stage block  202  is unity. In case, the gain of the gain stage block  202  is given as Gnv, the third voltage (Vt) is represented as:
 
                   Vt   =           C   ⁢           ⁢   1     +     C   ⁢           ⁢   2           C   ⁢           ⁢   1     +     C   ⁢           ⁢   2   ⁢     (     1   -   Gnv     )           *   Vin             (   2   )               
The gain (Gnv) of the gain stage block  202  is measured at the fixed terminal  206 . The voltage at the gate terminal  230   g  of the transistor  230  is equal to the third voltage (Vt). The voltage generated at the fixed terminal  206  of the gain stage block  202  is equal to a product of the third voltage (Vt) and the gain of the gain stage block  202 .
 
 Vf=Vt*Gnv   (3)
 
where Vf is the voltage generated at the fixed terminal  206  and Gnv is the gain of the gain stage block  202 .
 
     Also, the voltage Vf generated at the fixed terminal  206  and the input voltage Vin  204  have a non-inverting relationship. An output voltage Vout  240  is generated at the output terminal  234  of the gain stage block  202 . The output voltage Vout  240  follows the voltage generated at the gate terminal  230   g  of the transistor  230 . Thus, the output voltage Vout  240  is equal to the voltage generated at the fixed terminal Vf.
 
 V out= Vf=Vt*Gnv   (4)
 
     
       
         
           
             
               
                 
                   Vout 
                   = 
                   
                     
                       
                         
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         + 
                         
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       
                         C 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     * 
                     Vin 
                     * 
                     Gnv 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     When a value of the first capacitor C 1   220  is equal to the second capacitor C 2   222 , the output voltage Vout  240  is twice of the input voltage Vin  204 . Thus, the circuit  200  can be used as a gain stage in switched capacitor circuits. The circuit  200  will realize higher gain as compared to a conventional continuous time gain circuits. It is to be noted that the gain stage block  202  is one of the many ways of implementing the gain stage block and variations, and alternative constructions are apparent and well within the spirit and scope of the disclosure. 
     As compared to conventional approaches, the circuit  200  provides an accurate gain stage which can achieve high bandwidth in a given technology for a switched capacitor circuit. Also, the circuit  200  can support high swing of the input voltage Vin  204 , and is usable when frequency of operation is very high. The circuit  200  is a low noise circuit as compared to conventional circuits for a given bandwidth. The circuit  200  can be used as a variable gain amplifier in a signal chain and can also provide unity gain. 
     The circuit  200  can be used as a frontend gain stage and also as any gain stage in a signal chain for example in the MDAC (multiplying DAC) stage of a pipeline ADC. The circuit  200  absorbs parasitic capacitor at input into the first capacitor C 1   220 , and hence gives a better noise performance as compared to conventional gain stage circuits. 
       FIG. 3  illustrates a circuit  300 , according to an embodiment. The circuit  300  includes a gain stage block  302 . The gain stage block  302  is coupled to an input voltage Vin  304  through a first switch S 1   308 . A first capacitor C 1   320  is coupled between the first switch S 1   308  and a ground terminal  328 . A second capacitor C 2   322  is coupled between the first switch S 1   308  and a second switch S 2   312 . One end of the second switch S 2   312  is coupled to the ground terminal  328 . 
     A third switch S 3   316  is coupled between the second capacitor C 2   322  and a fixed terminal  306  of the gain stage block  302 . The gain stage block  302  includes a preamplifier that has six transistors illustrates as T 1  to T 6 . Transistors T 1  and T 2  are coupled to a source voltage Vdd  310 . Transistor T 5  and T 6  are coupled to a current source  332 . One end of the current source  332  is coupled to the ground terminal  328 . 
     Transistor T 5  is coupled to the input voltage Vin  304  through the first switch S 1   308 . Transistor T 6  receives an inverted input voltage  Vin   314 . The preamplifier generates an output voltage Vout  326  and an inverted output voltage  Vout   324 . The fixed terminal  306  of the gain stage block  302  is coupled to at least one of an output terminal and an intermediate terminal of the gain stage block  302 . As illustrated in  FIG. 3 , the fixed terminal  306  is coupled to an intermediate terminal  334  of the gain stage block  302 . The circuit  300  may include one or more additional components known to those skilled in the relevant art and are not discussed here for simplicity of the description. 
     The operation of the circuit  300  illustrated in  FIG. 3  is explained now. The circuit  300  operates in a sampling mode and a hold mode. In sampling mode, the first switch S 1   308  and the second switch S 2   312  are closed. The third switch S 3   316  is opened. The first capacitor C 1   320  and the second capacitor C 2   322  are charged to the input voltage Vin  304 . 
     In the hold mode, the first switch S 1   308  and the second switch S 2   312  are opened while the third switch S 3   316  is closed. The second capacitor C 2   322  gets discharged and all of its charge goes to the first capacitor C 1   320 . Thus, the first capacitor C 1   320  is charged to a third voltage (Vt) which is defined as follows:
 
 Vt =( C   1   +C   2 )* V   in   /C   1   (6)
 
The above equation 6 assumes that a gain of the gain stage block  302  is unity. In case, the gain of the gain stage block  302  is given as Gnv, the third voltage (Vt) is represented as:
 
                   Vt   =           C   ⁢           ⁢   1     +     C   ⁢           ⁢   2           C   ⁢           ⁢   1     +     C   ⁢           ⁢   2   ⁢     (     1   -   Gnv     )           *   Vin             (   7   )               
The gain (Gnv) of the gain stage block  302  is measured at the fixed terminal  306 . The voltage generated at the fixed terminal  306  of the gain stage block  302  is equal to a product of the third voltage (Vt) and the gain of the gain stage block  302 .
 
 Vf=Vt*Gnv   (8)
 
where Vf is the voltage generated at the fixed terminal  306  and Gnv is the gain of the gain stage block  302 .
 
     Also, the voltage Vf generated at the fixed terminal  306  and the input voltage Vin  304  have a non-inverting relationship. A voltage generated at the intermediate terminal of the gain stage block  302  follows the voltage generated at the fixed terminal  306 . Hence, the voltage generated at the intermediate terminal  334  is defined as:
 
 Vi=Vf=Vt*Gnv   (9)
 
     
       
         
           
             
               
                 
                   Vi 
                   = 
                   
                     
                       
                         
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         + 
                         
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       
                         C 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     * 
                     Vin 
                     * 
                     Gnv 
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     When a value of the first capacitor C 1   320  is equal to the second capacitor C 2   322 , the voltage at the intermediate terminal  334  is twice of the input voltage Vin  304 . Thus, the circuit  300  can be used as a gain stage in switched capacitor circuits. The circuit  300  will realize higher gain as compared to a conventional continuous time gain circuits. It is to be noted that the gain stage block  302  is one of the many ways of implementing the gain stage block and variations, and alternative constructions are apparent and well within the spirit and scope of the disclosure. 
     As compared to conventional approaches, the circuit  300  provides an accurate gain stage which can achieve high bandwidth in a given technology for a switched capacitor circuit. The circuit  300  is a low noise circuit as compared to conventional circuits for a given bandwidth. The circuit  300  can be used as a variable gain amplifier in a signal chain and can also provide unity gain. 
     The circuit  300  can be used as a frontend gain stage and also as any gain stage in a signal chain for example in the MDAC stage of a pipeline ADC. The circuit  300  absorbs parasitic capacitor at input into the first capacitor C 1   320 , and hence gives a better noise performance as compared to conventional gain stage circuits. 
       FIG. 4  is a flowchart  400  to illustrate a method of operation of a circuit, according to an embodiment. The flowchart  400  is explained in connection with the circuit  200 . At step  402 , a first switch and a second switch are closed. In circuit  200 , for example, the first switch S 1   208  and the second switch S 2   212  are closed to operate the circuit  200  in sampling mode. A third switch is opened at step  404 . In sampling mode, the third switch S 3   216  is opened in the circuit  200 . 
     At step  406 , a first capacitor and a second capacitor are charged to an input voltage. The first capacitor and the second capacitor are coupled to a gain stage block. In one version, the gain stage block is a non-inverting gain stage block. In circuit  200 , the first capacitor C 1   220  and the second capacitor C 2   222  are charged to the input voltage Vin  204 . The circuit  200  includes the gain stage block  202 . The gain stage block  202  is coupled to an input voltage Vin  204  through a first switch S 1   208 . 
     A first capacitor C 1   220  is coupled between the first switch S 1   208  and a ground terminal  228 . A second capacitor C 2   222  is coupled between the first switch S 1   208  and a second switch S 2   212 . The first capacitor C 1   220  and the second capacitor C 2   222  are coupled to the gain stage block  202 . A third switch S 3   216  is coupled between the second capacitor C 2   222  and a fixed terminal  206  of the gain stage block  202 . The fixed terminal  206  of the gain stage block  202  is coupled to at least one of an output terminal and an intermediate terminal of the gain stage block  202 . 
     At step  408 , the first switch and the second switch are opened. The third switch is closed at step  410 . In circuit  200 , in the hold mode, the first switch S 1   208  and the second switch S 2   212  are opened while the third switch S 3   216  is closed. At step  412 , the first capacitor is charged to a third voltage. A voltage generated at a fixed terminal of the gain stage block is proportional to the third voltage. In circuit  200 , the first capacitor C 1   220  is charged to a third voltage (Vt) which is defined in equation 1. 
     The voltage generated at the fixed terminal  206  of the gain stage block  202  is proportional to the third voltage. In one example, the voltage generated at the fixed terminal  206  of the gain stage block  202  is equal to a product of the third voltage (Vt) and a gain of the gain stage block  202 . Also, the voltage generated at the fixed terminal  206  and the input voltage Vin  204  have a non-inverting relationship. 
     The method illustrated by flowchart  400  can be used to implement a gain stage in switched capacitor circuits. The method will realize higher gain as compared to a conventional continuous time gain circuits. As compared to conventional approaches, the method provides an accurate gain stage which can achieve high bandwidth in a given technology for a switched capacitor circuit. 
     Also, the method can support high swing of the input voltage and is usable when frequency of operation is very high. The method can be used to implement any gain stage in a signal chain for example in the MDAC stage of a pipeline ADC. Also, it gives a better noise performance as compared to conventional gain stage circuits. 
       FIG. 5  illustrates a transceiver  500 , according to an embodiment. The transceiver  500  is incorporated into one or more of devices such as mobile device, laptop, network printer, router, base station, PDA and computer. These devices are connected to a communication network. The communication network may support exchange of data in accordance with the various wireless/wire line communications standards such as, and not limited to, WLAN, WIFI, Bluetooth, dedicated RF channel, GSM, CDMA, OFDM, satellite communication, cable networking, PSTN, DSL etc. These devices transmit and receive signal carrying information by processing the signal in accordance with one or more such standards. 
     The transceiver  500  may include one or more additional components known to those skilled in the relevant art and are not discussed here for simplicity of the description. The transceiver  500  may be in an environment which includes a processing unit such as a CPU (central processing unit), and a memory module. The processing unit can be, for example, a CISC-type (Complex Instruction Set Computer) CPU, RISC-type CPU (Reduced Instruction Set Computer), or a digital signal processor (DSP). 
     The memory module (which can be memory such as RAM, flash memory, or disk storage) stores one or more software applications (e.g., embedded applications) that, when executed by the processing unit, performs any suitable function associated with the transceiver  500 . 
     The transceiver  500  includes a gain stage  504  that receives an input voltage Vin  502 . An analog to digital converter (ADC)  508  is coupled to the gain stage  504  and generates a digital output signal Dout  510 . At least one of the gain stage  504  and the ADC  508  includes a switched capacitor gain stage (SCGS) circuit. The SCGS circuit is similar to one of the circuit  200  and the circuit  300 . 
     The SCGS circuit includes a gain stage block. The gain stage block receives the input voltage Vin  502  voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. One end of the second switch is coupled to the ground terminal. The first capacitor and the second capacitor are coupled to the gain stage block. 
     A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block. The gain stage includes a transistor. A gate terminal of the transistor receives the input voltage Vin  502  through the first switch. A drain terminal of the transistor is coupled to a source voltage. 
     The fixed terminal of the gain stage block is coupled to at least one of an output terminal and an intermediate terminal of the gain stage block. A voltage generated at the fixed terminal and the input voltage Vin  502  have a non-inverting relationship. The SCGS circuit operates in a sampling mode and a hold mode. In sampling mode, the first switch and the second switch are closed. The third switch is opened. The first capacitor and the second capacitor are charged to the input voltage. 
     In the hold mode, the first switch and the second switch are opened while the third switch is closed. The second capacitor gets discharged and all of its charge goes to the first capacitor when a gain of the gain stage block is unity. Thus, the first capacitor is charged to a third voltage. The SCGS circuit will realize higher gain as compared to a conventional continuous time gain circuits. 
     As compared to conventional approaches, the SCGS circuit provides an accurate gain stage which can achieve high bandwidth in a given technology. Also, the SCGS circuit can support high swing of the input voltage Vin  502 , and is usable when frequency of operation is very high. The SCGS circuit is a low noise circuit as compared to conventional circuits for a given bandwidth. The SCGS circuit can be used as a variable gain amplifier in a signal chain and can also provide unity gain. 
     The SCGS circuit can be used as a frontend gain stage and also as any gain stage in a signal chain for example in the MDAC stage of a pipeline ADC. The SCGS circuit absorbs parasitic capacitor at input into the first capacitor, and hence gives a better noise performance as compared to conventional gain stage circuits. 
     Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.