Patent Publication Number: US-6662057-B1

Title: Method and device for controlling processes in a computer system

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates both to a computer system and a method for controlling processes on such computer system which is configured particularly for the parallel execution of several processes using a scarce resource. 
     In a computer system as described the problem frequently arises above that a blocking of a scarce resource occurs when the several processes that access the resource exhaust its capacity. Such blockings lead to an unstable system state which, in turn can necessitate frequent undesirable restarting measures. 
     To solve this problem, it is possible to expand the scarce resource. But the same problem then occurs with another resource of the computer system, which is then scarce. Another known solution is to delay all processes accessing the resource in a constant manner. However, this leads to a delay of process execution and can prevent a blocking of the scarce resource only up to a certain elevated maximum load. 
     In addition, European patent EP-A-0-794 490 teaches a multitasking system, or the communication in a computer network in accordance with a client/server model, in which several clients can access one server. There, the access to the server is controlled via the number of threads specified by the client. When a certain number is exceeded, either a connection is not set up, or the client must wait until a thread is permitted. 
     It is therefore an object of the present invention to configure this type of computer system, and a method for controlling processes on the computer system, by which it is possible to prevent a blocking of the scarce resource. 
     SUMMARY OF THE INVENTION 
     This object is inventively achieved by a computer system, and method for controlling the same, having a first device for computing the capacity load C of the resource, a second device for determining a load responsibility of a process that accesses the resource, and a third device for delaying the execution of the process that accesses the resource depending on each of the capacity load C, the critical capacity load C crit  of the resource, and the load responsibility LR of the process. 
     The inventive device and the inventive method function adaptively; that is, depending on the current usage level of the resource and on the load responsibility of a process, so that other processes that only slightly load the resource can continue to run unaffected. It can, thus, be guaranteed that processes that are necessary for the stability of the system continue to run despite heavy loading of the resource. On the basis of the specific delaying of each individual process dependent on each of the current capacity load, the critical capacity load and the load responsibility of the respective process, the user of the computer system can implement desirable marginal conditions. For example, individual processes with higher priority can be delayed only shortly or not at all, despite an overcritical load. The delay of a process can increase with the respective load responsibility of the process. Processes whose load responsibility is below a limit value can remain completely unaffected by the delay. When the load of the scarce resource lies below a critical load, all processes can be executed without delay. 
     The load responsibility LR can be defined either as the number of accesses of the scarce resource that are required in the execution of a process, as the resource capacity demanded by the process, or as a combination of both. 
     The critical capacity load C crit  of the resource can be selected according to the type, task, and stability of the resource. The critical capacity load C crit  advantageously lies between 20% and 80% of the maximum capacity C max ; in particular, at approximately 50% of the maximum capacity. 
     A process whose load responsibility LR lies below a defined value advantageously is not delayed. In this way, processes that make little or no contribution to the critical load can continue to run without a delay. 
     When the actual instantaneous capacity load C of the resource lies below the critical capacity load C crit , all processes are executed without delay. The computer system can thus function at maximum speed when a critical load is not present. 
     The delay can be varied between a minimum and maximum delay time, wherein it is possible to select the minimum and maximum values according to the characteristics and requirements placed on the resource. 
    
    
     Additional features and advantages of the present invention are described in, and will be apparent from, the following Detailed Description of the Invention and the Figures. 
     BRIEF DESCRIPTION OF THE FIGURES 
     FIG. 1 shows a block diagram schematic of a computer system in accordance with the teachings of the present invention. 
     FIG. 2 is a graph diagram of Delay vs. Capacity Load which details the mode of functioning of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Essential terms that are needed to describe the present invention are defined as follows: 
     Computer System: 
     Computer system refers to any device for electronic data processing, regardless of whether it is a matter of a multi-purpose computer for executing application programs or a computer that is tailored to one task. In particular, computer systems for control and communication networks also are included here. 
     Resource: 
     Resource or operating device refers to components (hardware and software) of the computer system that can be used to perform a job—for instance, an information transmission—such as storage devices, interfaces, and data lines. 
     Process: 
     A process is a set of instructions that access a resource of the computer system. 
     When several processes P run in parallel in the computer system of the present invention, a heavy loading can occur due to accessing of a scarce resource R of the computer system. Referring to FIG. 1, a first device  1  measures the capacity load C of this resource R, potentially a storage unit, in which case the occupancy of the storage capacity can be used as a measure of the load. A second device  2  determines a load responsibility LR for each process (referenced P in FIG. 1) that accesses the scarce resource R, which load responsibility is a measure of the responsibility of the process for the capacity load C of the scarce resource R. A third device  3  then delays the execution of the process P that accesses the resource by a period depending on each of the current capacity load C, the critical capacity load C crit , the resource R, and the load responsibility LR of the process. If a process has a small load responsibility, it is not delayed. The third device  3  generates a delay of processes only when the actual capacity load C is above the critical capacity load C crit . Depending on the instantaneous capacity load and load responsibility of a process, it can be delayed by a period between a minimum delay D min  and a maximum delay D max . 
     FIG. 2 is a graph diagram of the delaying of a process P having a load responsibility LR=0 by the third device 3 depending on the current capacity C of the resource R. Below the critical capacity C crit , the process is not delayed. When this critical capacity C crit  is reached, a delay of D min  sets in which increases as capacity load rises up to the maximum value D max . 
     By delaying specific processes under load that access the scarce resources and contribute to the loading of the resource particularly heavily, the capacity bottlenecks can be eliminated, and a blocking of the resource and, thus, of the overall computer system can be avoided (like a speed limit on a highway for reducing the likelihood of a traffic jam). The stability of the system is thus improved, and individual processes that make no significant contribution to the capacity load of the computer system can continue to run with no significant delay. 
     A test example of the present invention is detailed below with reference to the attached FIGS. 1 and 2. 
     The delay of a process that accesses the scarce resource R (a memory having a capacity of 64 kbytes in the test case) was given by the formula:        D   =     min        (       D   max     ,       K   ×   LR     +     D   min     +         (       C   act     -     C   crit       )     ×     (       D   max     -     D   min       )           C   max     -     C   crit             )                       
     where the maximum delay was D max =15s; the minimum delay, D min =0.5s; and the constant, K=0.1s. 
     The following values were selected: 
     C crit =50% C max , (here: C crit =32 kByte) 
     D min =0.5s 
     D max =15s 
     K=0.1s. 
     The inventive computer system was tested under the given settings for several weeks. There were no blockings of the system owing to an overrun of the memory; that is, of the scarce resource R. In the enclosed computer printout, process refers to the name of a process that accesses the resource; time means the time at which the process occupies the resource; count means the load responsibility of a process when C is greater than C crit  (in this case the number of write processes of the process); size means the capacity load (occupancy) C of the memory, where C crit  equals 32 kBytes; and delay means the delay of the process that is brought about by the third device of the computer system. 
     If the capacity load rises above the critical capacity load, as it does at time 6:46:12.47, for example, a delay of a process sets in, which is greater the more heavily the process contributes to the loading of the scarce resource. When the capacity load falls below the critical limit again, as it does at time 06:47:23.21, the delay of the processes decreases exponentially over time. 
     An overrun of the memory, and thus a blocking of the computer system, did not occur during the entire system run. 
     Although the present invention has been described with reference to specific embodiments, those of skill in the art will recognize that changes may be made thereto without departing from the spirit and scope of the invention as set forth in the hereafter appended claims.