Patent Publication Number: US-10771091-B2

Title: Flash memory apparatus and storage management method for flash memory

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This continuation application claims the benefit of U.S. application Ser. No. 15/495,992, filed on Apr. 25, 2017, which claims the benefits of U.S. provisional application Ser. No. 62/328,025 filed on Apr. 27, 2016, which is entirely incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a flash memory apparatus, and more particularly to a flash memory apparatus and a corresponding storage management method for performing RAID-like (Redundant Array of Independent Disks-like) error correction code (ECC) encoding operation. 
     2. Description of the Prior Art 
     Generally speaking, when performing data programming to program data into a single-level-cell (SLC) block or a multiple-level-cell (MLC) block, a conventional flash memory controller is usually arranged to program corresponding parity check codes of other data pages of a word line of a data block into the last data page of the word line, so that the conventional controller can use the corresponding parity check codes to correct errors with a certain degree of error correction capability when program failure, word line open, or word line short occurs. However, the utilization rate of a flash memory space inevitably becomes lower. For example, if one word line includes eight data pages, the conventional controller is arranged to program data into seven data pages and program parity check codes into one data page. That is, it is necessary to use one eighth of memory space of a data block for storing parity check codes. The one eighth of memory space cannot be used to store data. This poor user experience is usually cannot be accepted for users. 
     SUMMARY OF THE INVENTION 
     Therefore one of the objectives of the invention is to provide a flash memory apparatus and corresponding flash memory storage management method for adopting an RAID-like (Redundant Array of Independent Disks-like) error code encoding operation, to reduce error rates, reduce number of necessary parity check codes, and to appropriately program the necessary parity check codes into corresponding memory locations of data pages, so as to be able to use the parity check codes to perform error correction when program failure, word line open, and word line short occurs, to solve the problems mentioned above. 
     According to embodiments of the invention, a flash memory apparatus comprises a flash memory module and a flash memory controller. The flash memory module comprises a plurality of single-level-cell blocks and at least one multiple-level-cell block. The flash memory controller has a plurality of channels respectively connected to the flash memory module and is configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programing and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks. When completing program of the plurality of single-level-cell blocks, the flash memory module is arranged for performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks to the at least one multiple-level-cell block according to an order of storing data in the plurality of single-level-cell blocks. 
     According to the embodiments, a flash memory storage management method, comprising: providing a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; classifying data to be programmed into a plurality of groups of data; respectively executing single-level-cell programing and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks; and, when completing program of the plurality of single-level-cell blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks to the at least one multiple-level-cell block according to an order of storing data in the plurality of single-level-cell blocks. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a device diagram of a flash memory apparatus according to an embodiment of the invention. 
         FIG. 2  is a diagram illustrating one SLC programming executed by the flash memory controller of  FIG. 1  to program a particular group of data into an SLC block of flash memory module according to a first embodiment of the invention. 
         FIG. 3  is a diagram illustrating data programming from one SLC block within flash memory module to the TLC block via the internal copy operation. 
         FIG. 4  is a diagram illustrating an embodiment of flash memory controller in  FIG. 1  programming/writing three groups of data into multiple SLC blocks within flash memory module and moving the data into the TLC block via the internal copy operation to form a super block. 
         FIG. 5  is a diagram illustrating one SLC programming executed by the flash memory controller of  FIG. 1  to program a particular group of data into an SLC block of flash memory module according to a second embodiment of the invention. 
         FIG. 6  is a diagram illustrating a second embodiment of flash memory controller in  FIG. 1  programming/writing three groups of data into multiple SLC blocks within flash memory module and moving the data into the TLC block via the internal copy operation to form a super block. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 1 , which is a device diagram of a flash memory apparatus  100  according to an embodiment of the invention. The flash memory apparatus  100  comprises a flash memory module  105  and a flash memory controller  110 . The flash memory module  105  is a flash memory module having a two-dimensional plane structure; however, this is not meant to be a limitation of the invention. The flash memory module  105  comprises multiple flash memory chips (not shown in  FIG. 1 ) and each flash memory chip includes multiple single-level-cell (SLC) blocks and multiple multiple-level-cell blocks. Each unit of the SLC blocks can be used for storing data of two bits, and each unit of the multiple-level-cell blocks can be used for storing data of 2 N  bits wherein N is an integer equal to or greater than 2. The multiple-level-cell block for example includes units of a multi-level cell (MLC) block which can be used for storing data of 2 2  bits, units of a triple-level cell (TLC) block which can be used for storing data of 2 3  bits, and/or units of a quad-level cell (QLC) block which can be used for storing data of 2 4  bits, and so on. 
     The flash memory controller  110  is connected to the flash memory module  105  via a plurality of channels. The flash memory controller  110  can use the different channels to simultaneously program data into different flash memory chips to improve the efficiency of data programming. The flash memory controller  110  includes an error correction code (ECC) encoding circuit  1101  and a parity check code buffer  1102 . The ECC encoding circuit  1101  is arranged to perform ECC encoding operation upon data. For example, in the embodiments, the ECC encoding operation comprises Reed-Solomon (RS) codes encoding operation and/or exclusive-OR (XOR) encoding operation for generating corresponding parity check codes respectively. The parity check code buffer  1102  is used for temporarily storing the generated corresponding parity check codes. The flash memory controller  110  is arranged for programming data into different flash memory chips by employing an RAID-like (Redundant Array of Independent Disks-like) memory management mechanism to reduce data error rate and referring to storage locations (storage locations of SLC block(s) and storage locations of TLC block(s)) of parity check codes generated by different encoding operations when programming data into SLC block(s) so that data errors can be corrected when programming data into SLC block(s) and also can be corrected when the flash memory module  105  performs an internal copy operation to copy and move data from SLC block(s) to a TLC block. 
     In practice, in order to improve the efficiency of data programming and reduce the data error rate, the flash memory module  105  is designed to include multiple channels (for example two channels in this embodiment but is not limited). When a channel is used by the controller  110  to program a certain data page, the controller  110  can use another channel to program another data page without waiting for the former channel. Each channel corresponds to respective sequencer in the controller  110  and corresponds to multiple flash memory chips (for example two chips in this embodiment but is not limited). Thus, one channel can be to perform data programming simultaneously for different data pages of multiple flash memory chips without waiting for completion of one chip. In addition, each flash memory chip includes a folded design including two different planes, and different data pages of two blocks respectively located on the two different planes can be programmed simultaneously without waiting for completion of data programming of one block when programming data into one flash memory chip. One super block of the flash memory module  105  is composed by multiple data pages of multiple flash memory chips of multiple channels. The flash memory controller  110  is arranged to program data by super blocks. The flash memory controller  110  programs data to SLC blocks within the flash memory module  105 , and the programmed data are buffered by the SLC blocks. Then, the programmed data is copied and programmed to a TLC block from the SLC blocks. It should be noted that in other embodiments each flash memory chip may not comprise the folded design, and one data page of one block is programmed when programming data into one flash memory chip. It is required to wait for some times for programming data to other data pages. 
     For the flow of data programming, data is programmed by the flash memory controller  110  to multiple SLC blocks  1051 A- 1051 C, and then the programmed data is moved from the SLC blocks  1051 A- 1051 C to the multiple-level-cell block  1052  such as the TLC block including TLC units for storing information of 2 3  bits in this embodiment. That is, data of the three SLC blocks  1051 A- 1051 C is programmed into one TLC block  1052 . To perform error correction protection for data programming of SLC blocks  1051 A- 1051 C and data programming of the TLC block  1052 , the flash memory controller  110  is arranged for classifying the data into three groups of data. It should be noted that the flash memory controller  110  is arranged for classifying the data into two groups of data if the multiple-level-cell block for example includes MLC units which can be used for storing data of 2 2  bits. The flash memory controller  110  is arranged for classifying the data into four groups of data if the multiple-level-cell block for example includes QLC units which can be used for storing data of 2 4  bits. That is, the units of multiple-level-cell block  1052  are used for storing information of 2 N  bits wherein N is an integer which is equal to or greater than 2, and the number of SLC blocks is designed as N. The flash memory controller  110  is arranged to classify data to be programmed into N groups of data to respectively program the data into N SLC blocks. 
     In this embodiment, after classifying the data into three groups of data, the flash memory controller  110  is arranged to execute a first SLC program to program the first group of data into the first SLC block  1051 A and use the ECC coding circuit  1101  to generate corresponding parity check codes and write the corresponding parity check codes into the first SLC block  1051 A. In this way, the data program of the SLC block  1051 A is completed. Then, the flash memory controller  110  is arranged to execute the second SLC program to program the second group of data into the second SLC block  1051 B and use the ECC coding circuit  1101  to generate corresponding parity check codes and write the corresponding parity check codes into the second SLC block  1051 B. In this way, the data program of the SLC block  1051 B is completed. The flash memory controller  110  then is arranged to execute the third SLC program to program the third group of data into the third SLC block  1051 C and use the ECC coding circuit  1101  to generate corresponding parity check codes and write the corresponding parity check codes into the third SLC block  1051 C. In this way, the data program of the third SLC block  1051 C is completed. 
     When the flash memory controller  110  performs SLC program to write a particular group of data into a particular SLC block or after programming the particular SLC block has been completed, the flash memory controller  110  is arranged to detect whether there are data errors. If data errors exist, for example program fail, one word line open, and/or two word line short occurs when programming a particular SLC block, the flash memory controller  110  is arranged for correcting the data errors by using corresponding parity check codes generated by the ECC encoding circuit  1101  when programming the particular SLC block. 
     When programming the above three groups of data into the three SLC blocks  1051 A- 1051 C or programming a particular SLC block has been completed, the flash memory module  105  is arranged for performing internal copy operation by copying and moving the three groups of data from the three SLC blocks  1051 A- 1051 C to the TLC block  1052  or copying and moving the particular group of data from the particular SLC block to the TLC block  1052  and then performing TLC programming to write the data into the TLC block  1052  (i.e. the above-mentioned super block) according to the order of the three groups of data. The TLC block  1052  is composed by data pages of word lines of different flash memory chips of different channels. A data page of a word line of the TLC block  1052  for example includes an upper page, a middle page, and a lower page. The internal copy operation of flash memory module  105  for example is used to program/write multiple data pages of the (N)th word line of an SLC block into multiple upper pages of a word line of the TLC block  1052 , to program/write multiple data pages of the (N+1)th word line of the SLC block into multiple middle pages of the same word line of the TLC block  1052 , and to program/write multiple data pages of the (N+2)th word line of the SLC block into multiple lower pages of the same word line of the TLC block  1052 , sequentially. After all the three groups of data have been programmed into the TLC block  1052 , the program operation for the super block is completed. 
     It should be noted that, to easily implement the internal copy operation, meet the requirement of randomizer seed rules of TLC block  1052 , and reduce the data error rate according to the ECC encoding capability, the internal copy operation is arranged to move data from SLC blocks into locations of upper, middle, and lower pages of multiple word lines of the TLC block  1052  according to the order of the data, and the flash memory controller  110  is arranged to program/write the different groups of data and generated corresponding parity check codes into the SLC blocks  1051 A- 1051 C according to the requirement of randomizer seed rules of TLC block  1052  and storage locations of parity check codes of ECC encoding. Thus, the ECC capability of ECC encoding circuit  1101  can be arranged to correct the errors which are resulted from program failure, one word line open and/or two word line short of an SLC block when programming the SLC block, and can be also arranged to correct the errors which are resulted from program failure, one word line open and/or two word line short of TLC block  1052  when programming the TLC block  1052 . 
     In addition, if the flash memory module  105  performs memory garbage collection, the flash memory controller  110  can externally read out and retrieve data from the SLC blocks  1051 A- 1051 C and/or from the TLC block  1052  to re-perform ECC encoding to execute SLC programming again. In addition, if performing SLC programming to write data into an SLC block and shutdown occurs, the flash memory controller  110  is arranged to read back data from the SLC block and re-encode and re-perform ECC encoding and SLC programming the read back data into another SLC block. In addition, if performing TLC programming to write data into the TLC block  1052  and shutdown occurs, the flash memory module  105  is arranged to discard data currently stored by the TLC block  1052  and perform the internal copy operation to copy and program corresponding data from the SLC blocks  1051 A- 1051 C into TLC block  1052 . 
     Please refer to  FIG. 2 , which is a diagram illustrating one SLC programming executed by the flash memory controller  110  of  FIG. 1  to program a particular group of data into an SLC block of flash memory module  105  according to a first embodiment of the invention. The ECC encoding circuit  1101  of flash memory controller  110  is arranged to perform RAID-like RS (Reed Solomon) encoding operation upon data to generate corresponding parity check codes, and the parity check code buffer  1102  is used for temporarily storing the generated parity check codes. 
     The flash memory module  105  includes two channels and two flash memory chips in which two sets of blocks of each chip include two different planes. To improve the efficiency of data programming, the flash memory controller  110  is arranged for respectively programming/writing data via the two channels into two different blocks of the two flash memory chips within flash memory module  105 . As shown in  FIG. 2 , in this embodiment, one SLC block for example includes (128) word lines which are respectively represented by WL 0 -WL 127 . The SLC block can be composed by only one SLC block or one set of sub-blocks of the SLC block, and depends on different definitions of SLC block in different embodiments. In this embodiment, one SLC block is composed by a set of (128) word lines each for example including (8) data pages. For the first word line WL 0  of the SLC block, the flash memory controller  110  programs/writes the data pages P 1  and P 2  into the flash memory chip CE 0  via channel CH 0  and folded planes PLN 0  and PLN 1 , then programs/writes the data pages P 3  and P 4  into another flash memory chip CE 1  via the same channel CH 0  and folded planes PLN 0  and PLN 1 , then programs/writes the data pages P 5  and P 6  into the flash memory chip CE 0  via another channel CH 1  and folded planes PLN 0  and PLN 1 , and then programs/writes the data pages P 7  and P 8  into the flash memory chip CE 1  via the channel CH 1  and folded planes PLN 0  and PLN 1 ; other and so on. 
     The flash memory controller  110  sequentially classifies every (M) word lines among the multiple word lines WL 0 -WL 127  of an SLC block into one group of data wherein the number (M) is an integer which is equal to or greater than two. For example, M is equal to three. Word lines WL 0 -WL 2  are classified into the first group of data. Word lines WL 3 -WL 5  are classified into the second group of data. Word lines WL 6 -WL 8  are classified into the third group of data. Word lines WL 9 -WL 11  are classified into the fourth group of data, and other so on. Word lines WL 120 -WL 122  are classified into a third group of data which is inversely counted, i.e. an antepenult group. Word lines WL 123 -WL 125  are classified into a second group of data which is inversely counted, i.e. a penultimate group. Word lines WL 126 -WL 127  are classified into the last/final group of data. The first, third, fifth groups of word lines and so on are odd groups of word lines, and the second, fourth, sixth groups of word lines and so on are even groups of word lines. When each time programming/writing one group of word line data (including data of three word lines), the flash memory controller  110  is arranged to use the ECC encoding circuit  1101  to execute ECC encoding upon the group of word line data to generate and output corresponding partial parity check codes to the parity check code buffer  1102  for buffering the partial parity check codes. 
     For buffering the partial parity check codes, the parity check code buffer  1102  is arranged to store partial parity check codes corresponding to odd groups of word line data in a first buffer area  1102 A and to store partial parity check codes corresponding to even groups of word line data in a second buffer area  1102 B. For example, when programming/writing data pages P 1 -P 24  of word lines WL 0 -WL 2 , the ECC encoding circuit  1101  performs ECC encoding upon data of the data pages P 1 -P 24  and then outputs generated partial parity check codes to the parity check code buffer  1102  and buffer the generated partial parity check codes in the first buffer area  1102 A. When programming/writing data pages P 1 -P 24  of word lines WL 3 -WL 5 , the ECC encoding circuit  1101  performs ECC encoding upon data of the data pages P 1 -P 24  and then outputs generated partial parity check codes to the parity check code buffer  1102  and buffer the generated partial parity check codes in the second buffer area  1102 B. When programming/writing data pages P 25 -P 48  of word lines WL 6 -WL 8 , the ECC encoding circuit  1101  performs ECC encoding upon data of the data pages P 25 -P 48  and then outputs generated partial parity check codes to the parity check code buffer  1102  and buffer the generated partial parity check codes in the first buffer area  1102 A. The ECC encoding operation and buffer operation are performed similarly for other data pages. When programming/writing data pages of word lines WL 120 -WL 122 , the ECC encoding circuit  1101  performs ECC encoding upon data of the data pages of word lines WL 120 -WL 122  and then outputs generated partial parity check codes to the parity check code buffer  1102  and buffer the generated partial parity check codes in the first buffer area  1102 A. 
     When programming/writing the last group of word lines (WL 123 -WL 125 ) among even groups of word lines, in addition to performing SLC programming and corresponding ECC encoding operation, the flash memory controller  110  is also arranged to read back partial parity check codes corresponding to all data of even groups of word lines data buffered by the second buffer area  1102 B, and to write/program all parity check codes (all partial parity check codes) corresponding to even groups of word line data into data pages of the last word line WL 125  of the last group of word lines among the even groups of word lines. For instance, the all partial parity check codes, i.e. RS parity check codes corresponding to data of even groups of word lines, are programmed to the last three data pages as marked by  205  on  FIG. 2 . 
     Additionally, in addition to performing SLC programming and corresponding ECC encoding operation, when programming the last word line WL 127  of the last group among the odd groups of data, the flash memory controller  110  is arranged to read back partial parity check codes corresponding to all odd groups of data, i.e. a portion of all parity check codes, from the first buffer area  1102 A. The flash memory controller  110  then programs/writes all parity check codes corresponding to the odd groups of data into the data pages such as the last three data pages marked by  210  of the last word line WL 127  of the last odd group of word lines, to store RS parity check codes corresponding to data of all the odd groups of word lines. After this, programming for one SLC block is completed. With respect to RS encoding operation, the parity check codes corresponding to data of the odd groups of word lines are stored/programmed to the last data pages of the last word line WL 127  of the last group among the odd groups of word lines. The parity check codes corresponding to data of the even groups of word lines are stored/programmed to the last data pages of the last word line WL 125  of the last group among the even groups of word lines. 
     In addition, as shown by the embodiment of  FIG. 2 , the ECC encoding circuit  1101  performs the ECC encoding operation such as an RS code encoding operation capable of correcting error(s) of any three data pages of one SLC block. For example, the ECC encoding circuit  1101  performs the ECC encoding operation upon data of the three word lines WL 0 -WL 2  to generate corresponding partial parity check codes. If data errors result from three data pages, e.g. data pages P 1 , P 9 , and P 17 , of the same folded plane of the same chip of the same channel, the ECC encoding circuit  1101  can use the generated partial parity check codes to correct data errors of the three data pages. 
     The flash memory controller  110  may detect program fail when programming/writing one SLC block. For example, if the controller  110  detects program fail of a data page such as P 9 , the ECC encoding circuit  1101  can use corresponding partial parity check codes to correct errors of the data page P 9 . 
     The flash memory controller  110  may detect one word line open when programming/writing one SLC block. For example, if the controller  110  detects one word line open of a data page such as P 9 , the ECC encoding circuit  1101  can use the corresponding partial parity check codes to correct errors of the data page P 9 . 
     The flash memory controller  110  may detect two word line short when programming/writing one SLC block. For example, if the controller  110  detects data errors of two data pages such as P 9  and P 17  resulting from two word line short of the two data pages, the ECC encoding circuit  1101  can use the corresponding partial parity check codes to correct errors of the two data pages P 9  and P 17 . If the controller  110  detects data errors of two data pages such as P 17  of word line WL 2  and P 1  of the word line WL 3  resulting from two word line short of the two data pages, the ECC encoding circuit  1101  can use partial parity check codes of one group of word lines WL 0 -WL 2  and partial parity check codes of another group of word lines WL 3 -WL 5  to respectively correct data errors of page P 17  of word line WL 2  and page P 1  of word line WL 3 . If the controller  110  detects data errors of two data pages such as P 1  and P 2  of word line WL 0  resulting from two word line short of the two data pages, the ECC encoding circuit  1101  can use partial parity check codes of one group of word lines WL 0 -WL 2  to respectively correct data errors of pages P 1  and P 2  of word line WL 0 . 
     Therefore, the ECC encoding circuit  1101  can correspondingly correct data page errors resulting from program fail, one word line open or two word line short when performing programming of one SLC block. 
     Please refer to  FIG. 3 , which is a diagram illustrating data programming from one SLC block within flash memory module  105  to the TLC block  1052  via the internal copy operation. As shown by  FIG. 3 , data of a group of three word lines within one SLC block is programmed to one word line within TLC block  1052 , to correspondingly form a least important bit (LSB) portion, a central important bit (CSB) portion, and a most important bit (MSB) portion of one data page of the word line within TLC block  1052 . For instance, data of word lines WL 0 -WL 2  of the SLC block is respectively programmed to the LSB portion, CSB portion, and MSB portion of word line WL 0  of TLC block  1052 . Data of word lines WL 3 -WL 5  of the SLC block is respectively programmed to the LSB portion, CSB portion, and MSB portion of word line WL 1  of TLC block  1052 . Data of word lines WL 6 -WL 8  of the SLC block is respectively programmed to the LSB portion, CSB portion, and MSB portion of word line WL 2  of TLC block  1052 . That is, the internal copy operation of flash memory module  105  is used to move and program data of one SLC block into partial word lines of the TLC block by the sequence of word lines of the SLC block. 
     Please refer to  FIG. 4 , which is a diagram illustrating an embodiment of flash memory controller  110  in  FIG. 1  programming/writing three groups of data into multiple SLC blocks  1051 A- 1051 C within flash memory module  105  and moving the data into the TLC block via the internal copy operation to form a super block. The ECC encoding circuit  1101  is arranged to separate data into odd groups of word line data and even groups of word line data each time when performing programming of SLC block(s), and is arranged to respectively store generated parity check codes at the last three data pages of the last word line of the odd groups of word lines and the last three data pages of the last word line of the even groups of word lines. When module  105  performs programming of TLC block, as shown in  FIG. 4 , the parity check codes corresponding to the first group among the odd groups of word lines are programmed and stored to the last three data pages, marked by  401 A, of the CSB portions of word line WL 42  of the super block. The parity check codes corresponding to the first group among the even groups of word lines are programmed and stored to the last three data pages, marked by  401 B, of the MSB portions of word line WL 41  of the super block. The parity check codes corresponding to the second group among the odd groups of word lines are programmed and stored to the last three data pages (marked by  402 A) of the LSB portions of word line WL 85  of the super block. The parity check codes corresponding to the second group among the even groups of word lines are programmed and stored to the last three data pages, marked by  402 B, of the MSB portions of word line WL 84  of the super block. The parity check codes corresponding to the third group among the odd groups of word lines are programmed and stored to the last three data pages, marked by  403 A, of the MSB portions of word line WL 127  of the super block. The parity check codes corresponding to the third group among the even groups of word lines are programmed and stored to the last three data pages, marked by  403 B, of the LSB portions of word line WL 127  of the super block. 
     If detecting data errors resulting from two word line short and occurring at two data pages (marked by  404 ) of word lines WL 0  and WL 1  of the super block, the flash memory module  105  is capable of correcting the errors occurring at the data page of word line WL 0  by using the parity check codes  401 A stored at the three data pages of the CSB portions of word line WL 42 , and is also capable of correcting the errors occurring at the data page of word line WL 1  by using the parity check codes  401 B stored at the three data pages of the MSB portions of word line WL 41 . 
     Similarly, if detecting data errors resulting from two word line short and occurring at two data pages (marked by  405 ) of word lines WL 43  and WL 44  of the super block, the flash memory module  105  is capable of correcting the errors occurring at the LSB and CSB portions of one data page of word line WL 43  and MSB portion of one data page of word line WL 44  (as marked by  405 ) by using the parity check codes  402 A stored at the LSB portions of the last three data pages of word line WL 85 , and is also capable of correcting the errors occurring at the MSB portion of one data page of word line WL 43  and LSB and CSB portions of one data page of word line WL 44  (as marked by  405 ) by using the parity check codes  402 B stored at the CSB portions of the last three data pages of word line WL 84 . 
     Similarly, if detecting data errors resulting from two word line short and occurring at two data pages (marked by  406 ) of word lines WL 125  and WL 126  of the TLC block, the flash memory module  105  is capable of correcting the errors occurring at the CSB and MSB portions of one data page of word line WL 125  and MSB portion of one data page of word line WL 126  (as marked by  406 ) by using the parity check codes  403 A stored at the MSB portions of the last three data pages of word line WL 127 , and is also capable of correcting the errors occurring at the LSB portion of one data page of word line WL 125  and CSB and MSB portions of one data page of word line WL 126  (as marked by  406 ) by using the parity check codes  403 B stored at the LSB portions of the last three data pages of word line WL 127 . 
     If detecting data errors resulting from one word line open or program fail and occurring at any one data page of any one word line of the super block (i.e. errors occurring at any three consecutive subpages), the flash memory module  105  is also capable of correcting errors occurring at any three consecutive subpages by using corresponding parity check codes. 
     According to the storage management mechanism for using flash memory controller  110  to program/write three groups of data and corresponding parity check codes into SLC blocks  1051 A- 1051 C within flash memory module  105 , when the flash memory module  105  uses the internal copy operation to sequentially program/write the data from SLC blocks  1051 A- 1051 C into the TLC block to form a super block, the flash memory module  105  can perform error correction by using the parity check codes stored at the SLC blocks  1051 A- 1051 C if detecting the errors resulting from one word line open, two word line short or program fail. 
     Please refer to  FIG. 5 , which is a diagram illustrating one SLC programming executed by the flash memory controller  110  of  FIG. 1  to program a particular group of data into an SLC block of flash memory module  105  according to a second embodiment of the invention. The ECC encoding circuit  1101  of flash memory controller  110  is arranged to perform RAID-like XOR (exclusive-OR) encoding operation upon data to generate corresponding parity check codes, and the parity check code buffer  1102  is used for temporarily storing the generated parity check codes. In addition, the XOR operation of ECC encoding circuit  1101  includes three different encoding engines to respectively perform XOR operations upon different word line data of SLC block(s). The description is detailed in the following paragraphs. 
     The flash memory module  105  includes two channels and two flash memory chips. To improve the efficiency of data programming, the flash memory controller  110  is arranged for respectively programming/writing data via the two channels into the two flash memory chips within flash memory module  105 , to respectively program data pages of one SLC block into different flash memory chips. In this embodiment, an SLC block of one SLC block data programming executed by flash memory controller  110  for example includes (128) word lines which are respectively represented by WL 0 -WL 127 . Each word line includes/has eight data pages. For example, regarding word line WL 0 , the ECC encoding circuit  1101  programs/writes data pages P 1  and P 2  into flash memory chip CE 0  by using the channel CH 0  and planes PLN 0  and PLN 1 , and then programs/writes data pages P 3  and P 4  into another flash memory chip CE 1  by using the same channel CH 0  and planes PLN 0  and PLN 1 . The ECC encoding circuit  1101  then programs/writes data pages P 5  and P 6  into flash memory chip CE 0  by using the channel CH 1  and planes PLN 0  and PLN 1 , and programs/writes data pages P 7  and P 8  into another flash memory chip CE 1  by using the channel CH 1  and planes PLN 0  and PLN 1 ; other and so on. 
     The ECC encoding circuit  1101  of flash memory controller  110  sequentially classifies every (M) word lines among the multiple word lines WL 0 -WL 127  of an SLC block into one group of word lines wherein the number (M) is an integer which is equal to or greater than two. For example, M is equal to three. For example, word lines WL 0 -WL 2  are classified into the first group. Word lines WL 3 -WL 5  are classified into the second group. Word lines WL 6 -WL 8  are classified into the third group. Word lines WL 9 -WL 11  are classified into the fourth group, and other so on. Word lines WL 120 -WL 122  are classified into a third group which is inversely counted, i.e. an antepenult group. Word lines WL 123 -WL 125  are classified into a second group which is inversely counted, i.e. a penultimate group. Word lines WL 126 -WL 127  are classified into the final group (the last group). The first, third, fifth groups and so on are odd groups of word lines, and the second, fourth, sixth groups and so on are even groups of word lines. When each time programming/writing one group of word line data (including data of three word lines), the flash memory controller  110  is arranged to use the ECC encoding circuit  1101  to execute/perform ECC encoding operation upon such group of word line data to generate and output corresponding partial parity check codes to the parity check code buffer  1102  for buffering the partial parity check codes. 
     When each time programming/writing data to one group of three word lines, the ECC encoding circuit  1101  is arranged for employing three different encoding engines to perform exclusive-OR (XOR) encoding operations upon the data to be programmed and thus generate and output corresponding partial parity check codes into the parity check code buffer  1102  for buffering the partial parity check codes. The parity check code buffer  1102  is arranged for storing/buffering the partial parity check codes corresponding to the odd groups of word line data in a first buffer area, and for storing/buffering the partial parity check codes corresponding to the even groups of word line data in a second buffer area. 
     For instance, the ECC encoding circuit  1101  includes a first encoding engine, a second encoding engine, and a third encoding engine. When programming the data pages P 1 -P 24  of word lines WL 0 -WL 2 , the ECC encoding circuit  1101  uses the first encoding engine to execute XOR operation upon data pages P 1 -P 8  of the word line WL 0  to generate a first partial parity check code, uses the second encoding engine to execute XOR operation upon data pages P 9 -P 16  of the word line WL 1  to generate a second partial parity check code, and then uses the third encoding engine to execute XOR operation upon data pages P 17 -P 24  of the word line WL 2  to generate a third partial parity check code. The ECC encoding circuit  1101  respectively outputs the generated partial parity check codes to the parity check code buffer  1102 , to buffer the generated partial parity check codes in the first buffer area. When programming data pages P 1 -P 24  of the word lines WL 3 -WL 5 , the ECC encoding circuit  1101  uses the first encoding engine to execute XOR operation upon data pages P 1 -P 8  of the word line WL 3  to generate another first partial parity check code, uses the second encoding engine to execute XOR operation upon data pages P 9 -P 16  of the word line WL 4  to generate another second partial parity check code, and then uses the third encoding engine to execute XOR operation upon data pages P 17 -P 24  of the word line WL 5  to generate another third partial parity check code. The ECC encoding circuit  1101  respectively outputs the generated partial parity check codes to the parity check code buffer  1102 , to buffer the generated partial parity check codes in the second buffer area. 
     Programming and encoding operations for other data pages are similar. That is, for data of the first, second, and third word lines of one group among the odd groups of word lines and for data of the first, second, and third word lines of one group among the even groups of word lines, the ECC encoding circuit  1101  is arranged for performing/executing different XOR operations to respectively generate corresponding parity check codes. To write/program the corresponding parity check codes into appropriate storage locations of SLC block(s), the ECC encoding circuit  1101  is arranged to write/program the corresponding parity check codes into last data pages (as shown by the rectangle with slanted lines in  FIG. 5 ) of last six word lines WL 122 -WL 127  when programming data pages of the last six word lines WL 122 -WL 127 . For instance, when programming data pages of the word line WL 122  which is a third word line of one group among the odd groups of word lines, the ECC encoding circuit  1101  programs/writes parity check codes corresponding to all third word lines among all odd groups of word lines into the last/final data page of the word line WL 122  wherein the parity check codes corresponding to all the third word lines are all the third partial parity check codes generated by the third encoding engine for the odd groups of word lines. For instance, when programming data pages of the word line WL 123  which is a first word line of one group among the even groups of word lines, the ECC encoding circuit  1101  programs/writes parity check codes corresponding to all first word lines among all even groups of word lines into the last/final data page of the word line WL 123  wherein the parity check codes corresponding to all the first word lines are all the first partial parity check codes generated by the first encoding engine for the even groups of word lines. For instance, when programming data pages of the word line WL 124  which is a second word line of one group among the even groups of word lines, the ECC encoding circuit  1101  programs/writes parity check codes corresponding to all second word lines among all even groups of word lines into the last/final data page of the word line WL 124  wherein the parity check codes corresponding to all the second word lines are all the second partial parity check codes generated by the second encoding engine for the even groups of word lines. 
     For instance, when programming data pages of the word line WL 125  which is a third word line of the last group among the even groups of word lines, the ECC encoding circuit  1101  programs/writes parity check codes corresponding to all third word lines among all even groups of word lines into the last/final data page of the word line WL 125  wherein the parity check codes corresponding to all the third word lines are all the third partial parity check codes generated by the third encoding engine for the even groups of word lines. 
     For instance, when programming data pages of the word line WL 126  which is a first word line of the last group among the odd groups of word lines, the ECC encoding circuit  1101  programs/writes parity check codes corresponding to all first word lines among all odd groups of word lines into the last/final data page of the word line WL 126  wherein the parity check codes corresponding to all the first word lines are all the first partial parity check codes generated by the first encoding engine for the odd groups of word lines. 
     For instance, when programming data pages of the word line WL 127  which is a second word line of the last group among the odd groups of word lines, the ECC encoding circuit  1101  programs/writes parity check codes corresponding to all second word lines among all odd groups of word lines into the last/final data page of the word line WL 127  wherein the parity check codes corresponding to all the second word lines are all the second partial parity check codes generated by the second encoding engine for the odd groups of word lines. Thus, data programming of one SLC block is completed. 
     That is, when programming data into one SLC block, the flash memory controller  110  is arranged for sequentially classifies every (M) word lines among all the word lines of the SLC block into one group of word lines to generate odd groups of word lines and even groups of word lines and for respectively performing (M) times of different XOR encoding operations upon each word line of each odd group and each word line of each even group to generate (M) partial parity check codes corresponding to each word line of the odd groups and (M) partial parity check codes corresponding to each word line of the even groups. The flash memory controller  110  then programs/writes the (M) partial parity check codes corresponding to each word line of the odd groups into the last/final data pages of last (M) word lines among the odd groups of word lines and programs/writes the (M) partial parity check codes corresponding to each word line of the even groups into the last/final data pages of last (M) word lines among the even groups of word lines. For example, M is equal to three in this embodiment but is not meant to be a limitation of the invention. 
     The ECC encoding circuit  1101  as shown in the embodiment of  FIG. 5  is arranged to perform XOR encoding operations which is capable of correcting errors occurring in any one data page of one word line of one SLC block. For example, when performing data programming of one SLC block, if detecting data errors resulting from program fail and occurring at a data page such as page P 9  of word line WL 1 , the ECC encoding circuit  1101  can use other correct data pages P 10 -P 16  of the same word line WL 1  and corresponding partial parity check code(s) generated by the second encoding engine when processing the word line WL 1  of the first group, to correct the errors occurring at the data page P 9 . 
     For example, when performing data programming of one SLC block, if detecting data errors resulting from one word line open and occurring at a data page such as page P 9  of word line WL 1 , the ECC encoding circuit  1101  can also use other correct data pages P 10 -P 16  of the same word line WL 1  and corresponding partial parity check code(s) generated by the second encoding engine when processing the word line WL 1  of the first group, to correct the errors occurring at the data page P 9 . 
     For example, when performing data programming of one SLC block, if detecting data errors resulting from two word line short and occurring at two data pages such as page P 9  of word line WL 1  and page P 17  of word line WL 2 , the ECC encoding circuit  1101  can use other correct data pages P 10 -P 16  of the word line WL 1  and corresponding partial parity check code(s) generated by the second encoding engine when processing the word line WL 1  of the first group, to correct the errors occurring at the data page P 9 . In addition, the ECC encoding circuit  1101  can use other correct data pages P 18 -P 24  of the word line WL 2  and corresponding partial parity check code(s) generated by the third encoding engine when processing the word line WL 2  of the first group, to correct the errors occurring at the data page P 17  of word line WL 2 . 
     If detecting data errors resulting from two word line short and occurring at two data pages such as page P 17  of word line WL 2  and page P 1  of word line WL 3 , the ECC encoding circuit  1101  can use other correct data pages P 18 -P 24  of the word line WL 2  and corresponding partial parity check code(s) generated by the third encoding engine when processing the word line WL 2  of the first group, to correct the errors occurring at the data page P 17  of word line WL 2 . In addition, the ECC encoding circuit  1101  can use other correct data pages P 2 -P 8  of the word line WL 3  and corresponding partial parity check code(s) generated by the first encoding engine when processing the word line WL 3  of the second group, to correct the errors occurring at the data page P 1  of word line WL 3 . 
     Thus, whether data page errors resulting from program fail, one word line open or two word line short occur when one SLC block is programmed, the ECC encoding circuit  1101  is able to correct the data page errors correspondingly. The internal copy operation of flash memory module  105  for programming data from the above-mentioned SLC blocks into the TLC block is similarly to the internal copy operation of the embodiment of  FIG. 3 , and is not detailed for brevity. 
     Please refer to  FIG. 6 , which is a diagram illustrating a second embodiment of flash memory controller  110  in  FIG. 1  programming/writing three groups of data into multiple SLC blocks  1051 A- 1051 C within flash memory module  105  and moving the data into the TLC block via the internal copy operation to form a super block. The ECC encoding circuit  1101  is arranged to separate data into odd groups of word line data and even groups of word line data each time when performing programming of SLC block(s), and is arranged to respectively store generated parity check codes at each last data page of the last three word lines of the odd groups and each last data page of the last three word lines of the even groups. When module  105  performs programming of TLC block, as shown in  FIG. 6  and marked by  605 A, the parity check codes corresponding to a first set of word lines are programmed and stored to the MSB portion of the last data page of word line WL 40 , last data page of word line WL 41 , and LSB and CSB portions of the last data page of word line WL 42  within the TLC block  1052 . Specifically, parity check codes corresponding to odd groups of word lines of SLC block(s) belonging to the first set are stored at the MSB portion of the last data page of word line WL 40  and LSB and CSB portions of the last data page of word line WL 42 . Parity check codes corresponding to even groups of word lines of SLC block(s) belonging to the first set are stored at the LSB, CSB, and MSB portions of the last data page of word line WL 41 . 
     As marked by  605 B, the parity check codes corresponding to a second set of word lines are programmed and stored to the CSB and MSB portions of the last data page of word line WL 83 , last data page of word line WL 84 , and LSB portion of the last data page of word line WL 85  within the TLC block  1052 . Specifically, for parity check codes corresponding to odd groups of word lines of SLC block(s) belonging to the second set, all the third partial parity check codes generated by the third encoding engine are stored at the CSB portion of the last data page of word line WL 83  of TLC block  1052 ; all the first partial parity check codes generated by the first encoding engine are stored at the MSB portion of the last data page of word line WL 84  of TLC block  1052 ; all the second partial parity check codes generated by the second encoding engine are stored at the LSB portion of the last data page of word line WL 85  of TLC block  1052 . Also, for parity check codes corresponding to even groups of word lines of SLC block(s) belonging to the second set, all the first partial parity check codes generated by the first encoding engine are stored at the MSB portion of the last data page of word line WL 83  of TLC block  1052 ; all the second partial parity check codes generated by the second encoding engine are stored at the LSB portion of the last data page of word line WL 84  of TLC block  1052 ; all the third partial parity check codes generated by the third encoding engine are stored at the CSB portion of the last data page of word line WL 84  of TLC block  1052 . 
     As marked by  605 C, the parity check codes corresponding to a third set of word lines are programmed and stored to the last data pages (LSB, CSB, and MSB portions) of word lines WL 126 -WL 127  of TLC block  1052 . Specifically, for parity check codes corresponding to odd groups of word lines of SLC block(s) belonging to the third set, all the third partial parity check codes generated by the third encoding engine are stored at the LSB portion of the last data page of word line WL 126  of TLC block  1052 ; all the first partial parity check codes generated by the first encoding engine are stored at the CSB portion of the last data page of word line WL 127  of TLC block  1052 ; all the second partial parity check codes generated by the second encoding engine are stored at the MSB portion of the last data page of word line WL 127  of TLC block  1052 . Also, for parity check codes corresponding to even groups of word lines of SLC block(s) belonging to the third set, all the first partial parity check codes generated by the first encoding engine are stored at the CSB portion of the last data page of word line WL 126  of TLC block  1052 ; all the second partial parity check codes generated by the second encoding engine are stored at the MSB portion of the last data page of word line WL 126  of TLC block  1052 ; all the third partial parity check codes generated by the third encoding engine are stored at the LSB portion of the last data page of word line WL 127  of TLC block  1052 . 
     Thus, when flash memory module  105  performs the internal copy operation to program data from the SLC blocks  1051 A- 1051 C to the TLC block  1052 , if detecting data errors resulting from two word line short and occurring at two data pages (marked by  610 ) of word lines WL 0  and WL 1  of the super block, the flash memory module  105  is capable of correcting the errors occurring at the LSB portion of the data page of word line WL 0  by using the first partial parity check codes stored at the CSB portion of the last data page of word line  42  of TLC block  1052  and data stored at LSB portions of the other data pages of word line WL 0 . Similarly, the flash memory module  105  is capable of correcting the errors occurring at the CSB portion of the data page of word line WL 0  by using the second partial parity check codes stored at the MSB portion of the last data page of word line  42  of TLC block  1052  and data stored at CSB portions of the other data pages of word line WL 0 . Similarly, the flash memory module  105  is capable of correcting the errors occurring at the MSB portion of the data page of word line WL 0  by using the third partial parity check codes stored at the MSB portion of the last data page of word line  40  of TLC block  1052  and data stored at MSB portions of the other data pages of word line WL 0 . Similarly, the flash memory module  105  is capable of correcting the errors occurring at the LSB portion of the data page of word line WL 1  by using the first partial parity check codes stored at the LSB portion of the last data page of word line  41  of TLC block  1052  and data stored at LSB portions of the other data pages of word line WL 1 . Similarly, the flash memory module  105  is capable of correcting the errors occurring at the CSB portion of the data page of word line WL 1  by using the second partial parity check codes stored at the CSB portion of the last data page of word line  41  of TLC block  1052  and data stored at CSB portions of the other data pages of word line WL 1 . Similarly, the flash memory module  105  is capable of correcting the errors occurring at the MSB portion of the data page of word line WL 1  by using the third partial parity check codes stored at the MSB portion of the last data page of word line  41  of TLC block  1052  and data stored at MSB portions of the other data pages of word line WL 1 . 
     If detecting data errors resulting from two word line short and occurring at consecutive data pages (e.g., as marked by  615  and  620 ) of any two consecutive word lines of the super block, the flash memory module  105  is capable of correcting errors by using corresponding parity check codes stored at each last data page of the last six data pages of one SLC block belonging to each set. In addition, if detecting data errors resulting from one word line open or program fail and occurring at any single one data page of any one word line of the TLC block  1052  (e.g. errors occurs at LSB, CSB, and MSB portions of the same data page or at consecutive portions of two different data pages, the flash memory module  105  is also capable of correcting the errors by using the corresponding parity check codes. 
     That is, according to the storage management mechanism for using flash memory controller  110  to program/write three sets of data and corresponding parity check codes into SLC blocks  1051 A- 1051 C within flash memory module  105 , when the flash memory module  105  uses the internal copy operation to sequentially program/write the data from SLC blocks  1051 A- 1051 C into the TLC block to form a super block, the flash memory module  105  can perform error correction by using the parity check codes stored at the SLC blocks  1051 A- 1051 C if detecting the errors resulting from one word line open, two word line short or program fail. 
     Further, the above-mentioned operations can be also applied for a flash memory module including MLC blocks and QLC blocks. When a flash memory module including MLC blocks, the classifying operation is arranged for separating data into two groups/sets, and the XOR encoding operation is implemented by using two encoding engines; other operations are similar to those associated with the flash memory module structure with TLC blocks. Identically, when a flash memory module including QLC blocks, the classifying operation is arranged for separating data into four groups/sets, and the XOR encoding operation is implemented by using four encoding engines; other operations are similar to those associated with the flash memory module structure with TLC blocks. 
     Regarding to ECC code overhead of the data storage mechanism mentioned above, if two channels are employed for programming two memory chips and two blocks can be simultaneously programmed based on the folded plane design of each memory chip, for data programming of one SLC block, there are (128) word lines in the SLC block and totally the SLC block has (8*128) data pages. Based on the data storage mechanism mentioned above, it is only required to use six data pages among the total (8*128) data pages to store corresponding parity check codes. The percentage of ECC code overhead compared to the total data storage space, i.e. 6/(128*8), is smaller than one. That is, for data programming of SLC blocks and TLC block(s), it is only necessary to use a data storage space of less than 1% of the total data storage space for storing corresponding parity check codes of ECC operation. The utilization rate of a flash memory storage space is higher compared to the conventional scheme. Additionally, if four channels are employed for programming four memory chips and two blocks can be simultaneously programmed based on the folded plane design of each memory chip, for data programming of one SLC block, there are (128) word lines in the SLC block and totally the SLC block has (4*4*2*128) data pages. Based on the data storage mechanism mentioned above, it is only required to use six data pages among the total (4*4*2*128) data pages to store corresponding parity check codes. The percentage of ECC code overhead compared to the total data storage space, i.e. 6/(4*4*2*128), is decreased to be smaller and is almost 0.15%. That is, for data programming of SLC blocks and TLC block(s), it is only necessary to use almost 0.15% of the total data storage space for storing corresponding parity check codes of ECC operation. The utilization rate of a flash memory storage space can be much higher compared to the conventional scheme. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.