Patent Publication Number: US-6035006-A

Title: Estimator having a feedback loop

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to data transmission, and in particular to signal estimation in the presence of distortion such as intersymbol interference (ISI). 
     2. Description of the Related Art 
     There has been proposed Delayed decision-feedback sequence estimation (DDFSE), which is a method of estimating the distorted signals, in &#34;Delayed Decision Feedback Sequence Estimation&#34; by A. Duel-Hallen and C. Heegard (IEEE Transactions on communications, pp 428-436, Vol. 37, No. 5, May 1989). DDFSE is an estimation algorithm that would reduce computational complexity with only slight degradation in the quality of signal estimation compared with MLSE (maximum-likelihood sequence estimation) in digital communications over intersymbol interference channels. 
     As another method for estimating the distorted signals, the inventor has proposed an adaptive reduced-state sequence estimation in NEC Research &amp; Development (pp 188-194, Vol. 35, No. 2, April 1994). the adaptive reduced-state sequence estimation (RSSE) uses a memory table to estimate both linearly and nonlinearly distorted signals with employing a loop configuration for feedback of estimated data. 
     In a signal estimator employing the feedback loop configuration as described above, it is necessary to complete a set of computations within a time period of a symbol. More specifically, as shown in FIG. 1, the estimator performs three kinds of computations, that is, generation of estimated signals, generation of branch metrics, and comparison for path metric selection, within the time period of Ts. In the case of a Viterbi algorithm having no loop therein, pipeline processing can be employed to achieve high-speed computation. However, since the signal estimator uses estimated data one symbol before for calculation of the subsequent symbol, the pipeline processing cannot be employed. 
     Therefore, to achieve high-speed computation, the signal estimator needs a high-speed arithmetic circuit which increases in consumption power, providing a tradeoff between speed and power consumption. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an estimation loop and a signal estimator including the same, which can achieve high-speed computations without increasing in power consumption. 
     Another object of the present invention is to provide a signal estimator which can reduce in delay time due to feedback computations so as to be applicable to a high-speed data transmission. 
     A signal estimation loop according to an aspect of the present invention generates an estimated signal from an input signal in each symbol period, wherein the input signal is received through a channel having an impulse response including a postcursor component for a plurality of symbols. The signal estimation loop includes a subtracter, a postcursor estimator, and a selector. The subtracter subtracts a postcursor estimation signal from the input signal to produce a subtracted signal which is used to generate the estimated signal. The postcursor estimator generates all possible postcursor estimation signals in a first past symbol period which is one symbol earlier based on a past estimated signal in a second past symbol period which is at least two symbols earlier. And the selector selects one of the possible postcursor estimation signals based on the estimated signal to output a selected one as the postcursor estimation signal to the subtracter in the symbol period. 
     Since all possible postcursor estimation signals are generated in the first past symbol period which is one symbol earlier and one of them is selected in the symbol period, high-speed estimation can be achieved. 
     A signal estimator according to another aspect of the present invention includes a first estimator for estimating the input signal based on the precursor component and center component to produce a first estimated signal, a delay memory for storing the first estimated signal to delay one symbol, and the signal estimation loop. 
     Since the precursor component and center component are canceled from the input signal before the postcursor estimation, the precursor, center and postcursor estimation can be performed in pipeline processing, resulting in further high-speed estimation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a time chart showing an operation of a conventional signal estimator having a feedback loop; 
     FIG. 2 is a block diagram showing a signal estimator according to an embodiment of the present invention; 
     FIG. 3 is a diagram showing an example of an impulse response of transmission channel for explanation of an operation of the embodiment; 
     FIG. 4 is a diagram showing the operation of the embodiment in Viterbi algorithm; 
     FIG. 5 is a time chart showing an operation of the embodiment; 
     FIG. 6 is a detailed block diagram showing the configuration of a precursor estimation signal generator in the embodiment; and 
     FIG. 7 is a detailed block diagram showing the configuration of a postcursor estimation signal generator in the embodiment. 
    
    
     DETAILED DESCRIPTION OF THE REFEREED EMBODIMENT 
     Referring to FIG. 2, there is shown a signal estimator according to an embodiment of the present invention. In general, transmission data has K values (K is an integer) and a transmission channel exhibits an impulse response including a precursor component for N symbols, a 0  -a N-1 , a center component for one symbol, a N , and a postcursor component for M symbols, a N+1  -a N+1 , where N and M are an integer. 
     In this embodiment, assume K=2, M=2 and N=1 for simplicity. More specifically, the transmission data has two values: +1 and -1, and the transmission channel exhibits an impulse response including a precursor component of a 0 , a center component of a 1 , and a postcursor component of a 2  and a 3 , as shown in FIG. 3. 
     In FIG. 2, input data which may be subjected to distortion due to ISI channel is received at an input terminal 101 and is supplied in common to four subtracters SUB 11  -SUB 14 . The respective subtracters SUB 11  -SUB 14  subtract precursor estimation signals S PRES1  -S PRS4  from the input data. The precursor estimation signals S PRE1  -S PRE4  are generated by a precursor estimation signal generator 102. More specifically, the precursor estimation signals S PRE1  -S PRE4  are four estimated precursor and center signal components which are generated in four cases of transmission data (X N , X N+1 ), (-1, -1), (+1, -1), (-1, +1), and (+1, +1), respectively. 
     The first difference signals between the input data and the precursor estimation signals S PRB1  -S PRE4  are stored onto registers REG 1  -REG 4  for one-symbol delay, respectively. As will be described later, the registers REG 1  -REG 4  allow pipeline processing. 
     The respective first difference signals stored in the registers REG 1  -REG 4  are supplied to four subtracters SUB 21  -SUB 24 . The first two subtracters SUB 21  and SUB 22  subtract a postcursor estimation signal S POSTa  from the first difference signals stored in the registers REG 1  and REG 2 , respectively. Similarly, the other two subtracters SUB 22  and SUB 24  subtract a postcursor estimation signal S POSTb  from the first difference signals stored in the registers REG 2  and REG 4 , respectively. 
     The second difference signals output from the subtracters SUB 21  -SUB 24  are squared by a square calculators SQ 1  -SQ 4 , respectively. The second difference signals are used as four branch metrics which are output to adders ADD 1  -ADD 4 , respectively. The adders ADD 1  and ADD 2  add a first selected path metric stored in a register 103 to the first and second branch metrics of the square calculators SQ 1  and SQ 2 , respectively, to produce two path metrics. Similarly, the adders ADD 3  and ADD 4  add a second selected path metric stored in a register 104 to the third and fourth branch metrics of the square calculators SQ 3  and SQ 4 , respectively, to produce two path metrics. The respective path metrics from the ADD 1  and ADD 3  are output to a first comparator and selector (CS) 105 which compares them and selects one which is smaller. The selected one is stored as the first selected path metric onto the register 103. Similarly, the respective path metrics from the ADD 2  and ADD 4  are output to a second CS 106 which compares them and selects one which is smaller. The selected one is stored as the second selected path metric onto the register 104. The respective CSs 105 and 106 output selection signals S SEL1  and S SEL2  each indicating which path metric is selected to first and second temporary decision sections 107 and 107. 
     The first and second temporary decision sections 107 and 108 store temporary decision data sequences corresponding to survivors, respectively, and the first temporary decision sections 107 selects one of the two survivor paths according to Viterbi algorithm to output estimated data corresponding to the original transmitted sequence. The first and second temporary decision sections 107 and 108 further output the data sequences of survivor paths to a postcursor estimation signal generator 109. 
     The postcursor estimation signal generator 109 includes fourth postcursor estimation signal generators PESG 1  -PESG 4  and two selectors SEL 1  and SEL 2 . The postcursor estimation signal generators PESG 1  -PESG 4  are supplied with predetermined values: -1, +1, -1, and +1, respectively, which are used as temporary decision data X N-1  one symbol before. In other words, the previous decision data X N-1  is not received from the temporary decision sections 107 and 108 but given as predetermined data. The further previous decision data X N-2  is received from the temporary decision sections 107 and 108. Here, the postcursor estimation signal generators PESG 1  and PESG 3  receive the decision data X N-2  from the temporary decision section 107 and the other postcursor estimation signal generators PESG 2  and PESG 4  receive the decision data X N-1  from the temporary decision section 108. Therefore, upon reception of the decision data X N-2 , each of the postcursor estimation signal generators PESG 1  -PESG 4  can start calculating a postcursor estimation signal as will be described in detail. 
     More specifically, the postcursor estimation signal generator PESG 1  generates a postcursor estimation signals S POST1  when X N-1  is -1 and X N-2 (1) is received from the temporary decision section 107. The postcursor estimation signal generator PESG 2  generates a postcursor estimation signal S POST2  when X N-1  is +1 and X N-2 (1) is received from the temporary decision section 107. The postcursor estimation signal generator PESG 3  generates a postcursor estimation signal S POST2  when X N-1  is -1 and X N-2 (2) is received from the temporary decision section 108. The postcursor estimation signal generator PESG, generates a postcursor estimation signal S POST4  when X N-1  is +1 and X N-2 (2) is received from the temporary decision section 108. The postcursor estimation signals S POST1  and S POST2  are output to the selector SEL 1  and the postcursor estimation signals S POST3  and S POST4  are output to the selector SEL 2 . 
     The selector SEL 1  selects the first selected postcursor estimation signal S POSTa  from the postcursor estimation signals S POST1  and S POST2  according to the selection signal S SEL1  received from the first CS 105. The selector SEL 2  selects the second selected postcursor estimation signal S POSTb  from the postcursor estimation signals S POST3  and S POST4  according to the selection signal S SEL2  received from the second CS 106. As described before, the selected postcursor estimation signal S POSTa  is output to the subtracters SUB 21  and SUB 22  and the selected postcursor estimation signal S POSTb  is output to the subtracters SUB 23  and SUB 24 . 
     OPERATION 
     Assume that a transmission data sequence is (X N-2 , X N-1 , X N , X N+1 ) and the transmission channel has the impulse response as shown in FIG. 3. In this case, the input signal which is subjected to distortion due to the ISI channel is represented as follows: 
     
         X.sub.N+1 a.sub.0 +X.sub.N a.sub.1 +X.sub.N-1 a.sub.2 +X.sub.N-2 a.sub.3. 
    
     The precursor estimation signal generator 102 generates the precursor estimation signals S PRE1  -S PRE4  by calculating the (X N+1  a 0  +X N  a 1 ) in the respective cases of transmission data (X N , X N+1 ); (-1, -1), (+1, -1), (-1, +1), and (+1, +1). The respective subtracters SUB 11  -SUB 14  subtract the precursor estimation signals S PRE1  -S PRE4  from the input signals. Therefore, one of the first difference signals is a signal obtained by canceling the precursor signal component and center signal component from the input signal. The precursor estimation can be separated from the decision feedback loop by storing the respective first difference signals onto the registers REG 1  -REG 4  to delay one symbol. In other words, the precursor estimation can be completed one symbol before the postcursor estimation. 
     The respective first difference signals stored in the registers REG 1  -REG 4  are supplied to the subtracters SUB 21  -SUB 24 . The subtracters SUB 21  and SUB 22  subtract the postcursor estimation signal S POSTa  from the first difference signals stored in the registers REG 1  and REG 2 , respectively, and the other two subtracters SUB 23  and SUB 24  subtract the postcursor estimation signal S POSTb  from the first difference signals stored in the registers REG 3  and REG 4 , respectively. The respective subtracters SUB 21  -SUB 24  output the second difference signals to the square calculators SQ 1  -SQ 4  for computations of branch metrics. 
     The postcursor estimation signals S POSTa  and S POSTb  are represented by (X N-1  a 2  +X N-2  a 3 ) which is generated by the postcursor estimation signal generator 109 using all possible combinations of the predetermined possible data X N-1 , -1 or +1, and the temporary decision data X N-2  received from the temporary decision sections 107 and 108 to select the postcursor estimation signals S POSTa  and S POSTb  according to the selection signals S SEL1  and S SEL2  as described before. 
     Referring to FIG. 4, comparisons will be made with the conventional signal estimator. According to prior art, each of the postcursor estimation signals S POSTa  and S POSTb , (X N-1  a 2  +X N-2  a 2 ), are calculated from only temporary decision data X N-1  and X N-2  received from the temporary decision sections 107 and 108. In other words, in FIG. 4, when calculating branch metrics at time T N , it is necessary to calculate temporary decision data from survivor paths at time T N-1  and T N-2  which are continuous paths to the paths P 1  and P 1 , respectively. Especially, in the case where the postcursor component of the impulse response is a long time away from no effect on subsequent signals, the time required for calculation becomes longer. Therefore, with increasing symbol rate, it becomes impossible to keep the branch metric calculation at time T N  waiting until survivor paths at time T N-1  are decided. 
     Contrarily, according to the embodiment of the present invention, all possible postcursor estimation signals S POST1  -S POST4  at time T N-1  are calculated when receiving the temporary decision data X N-2  and then only selection is performed at time T N-1  according to the selection signals S SEL1  and S SEL2 . The temporary decision data X N-2 (1) and X N-2 (2) are received from the temporary decision sections 107 and 108, respectively, because of sufficient lead time (2 symbols) to perform calculation of survivor paths at time T N-2 . More specifically, the postcursor estimation signal generators PESG 1  -PESG 4  calculate S POST1  =(-1×a 2  +X N-2 (1) ×a 3 ), S POST2  =(+1×a 2  +X N-2 (1) ×a 3 ), S POST3  =(-1×a 2  +X N-2 (2) ×a 3 ), and S POST4  =(-1×a 2  +X N- (2) ×a 3 ), respectively, and then the selectors SEL 1  and SEL 2  select the postcursor estimation signals S POSTa  and S POSTb  from them according to the selection signals S SEL1  and S SEL2 , respectively. Similarly, all possible postcursor estimation signals S POST1  -S POST4  at time T N  are calculated when receiving the temporary decision data X N-1 . 
     Therefore, it is necessary to operate a feedback loop including the subtracters SUB 21  -SUB 24 , the square calculators SQ 1  -SQ 4 , the adders ADD 1  -ADD 4 , the CSs 105 and 106, and the selectors SEL 1  and SEL 2  within one symbol. Since the respective selectors SEL 1  and SEL 2  can perform the selection operation within the time required for a single logical gate, the feedback loop can work within a sufficiently short time period, resulting in high-speed postcursor estimation applicable to high-speed data transmission. 
     Referring to FIG. 5, in the one-symbol time period Ts, the selectors SEL 1  and SEL 2  perform the selection of the postcursor estimation signals S POSTa  and S POSTb  from the postcursor estimation signals S POST1  -S POST4  which were already calculated in the preceding time period. After that, the branch metric calculations and the ACS (Add-Compare-Select) computations are performed. At the same time, all possible postcursor estimation signals S POST1  -S POST4  which will be used in the following time period are generated by the postcursor estimation signal generators PESG 1  -PESG 4 . In this manner, the whole processing time can be reduced. 
     Referring to FIG. 6, there is shown an example of the precursor estimation signal generator 102. This is comprised of four transversal filters each including two multipliers and one adder. Taking a first transversal filter as an example, a multiplier M 11  inputs a 0  and -1, a multiplier M 12  inputs a 1  and -1, and an adder A 1  adds the respective products to produce the precursor estimation signal S PRE1 , (-a 0  -a 1 ). Similarly, the respective precursor estimation signals S PRE2  -S PRE4  are (+a 0  -a 1 ), (-a 0  +a 1 ), and (+a 0  +a 1 ). 
     Referring to FIG. 7, there is shown an example of the postcursor estimation signal generator 109. This is also comprised of four transversal filters each including two multipliers and one adder. Taking a first transversal filter as an example, a multiplier M 51  inputs a 2  -1, a multiplier M 52  inputs a 3  and X M-2 (1), and an adder A 5  adds the respective products to produce the postcursor estimation signal S POST1 , (-a 1  +X N-2 (1) a 3 ). Similarly, the respective postcursor estimation signals S POST2  -S POST4  are (+a 2  +X N-2 (1) a 3 ), (-a 2  +X N-2 (2) a 1 ), and (+a 2  +X N-3 (2) a 3 ). 
     In general, the transmission data has K values and a transmission channel exhibits an impulse response including a precursor component for N symbols, a center component for one symbol, and a postcursor component for M symbols. In such a general case, the precursor estimation signal generator 102 generates K N-1  precursor estimation signals, resulting in the same number (K N+1 ) of subtracters SUB 11 , SUB 12  . . . , registers REG 1 , REG 2 , . . . , subtracters SUB 21 , SUB 22  . . . , square calculators SQ 1 , SQ 2 , . . . , and adders ADD 1 , ADD 2 , . . . Further, the postcursor estimation signal generator 109 has K N+1  postcursor estimation signal generators PESG 1 , PESG 2 , . . . and 2 M  selectors SEL 1 , SEL 2 , . . . . Furthermore, the signal estimator is provided with 2 M  CSs, 2 N  registers, and 2 N  temporary decision sections. 
     As described above, since the respective selectors SEL 1  and SEL 2  of the postcursor estimation signal generator 109 can perform the selection operation for a very short time, the total processing time is dramatically-reduced, resulting in high-speed postcursor estimation applicable to high-speed data transmission. Especially, in communications environments where multipath has a relatively large effect on performance, the postcursor component continues for a long time. In such cases, the signal estimator according to the present invention has great advantages because it can effectively and rapidly generates postcursor estimation signals for equalization.