Patent Publication Number: US-6992523-B2

Title: Low voltage current monitoring circuit

Description:
FIELD OF THE INVENTION 
   The present invention relates to current monitoring circuits, and, more particularly, to a low voltage current monitoring circuit that is independent of process, temperature and supply voltages even in high current and low voltage applications. 
   BACKGROUND OF THE INVENTION 
   Power-supply current monitoring for testing of CMOS logic circuits monitors the current passing through the power supply VDD or ground GND terminals during the application of an input stimulus or while the circuit is in a quiescent condition. 
   Many of the existing current monitors, however, fail to provide reliable monitoring due to fluctuation in process, temperature, and voltage supply. 
     FIG. 1  illustrates a voltage regulator arrangement connected to a current monitor  20 . The voltage regulator includes a closed loop, wherein amplifier  12  couples to drive main FET  16 . Main FET  16  is connected to a resistor divider represented by resistors R 2 , R 8 , R 7 , and R 3 . The connection from the voltage divider is fed back to the inverted input of amplifier, wherein the reference or bandgap voltage V ref  is fed into the non-inverting input of the amplifier. The following equation applies when deriving the value of the generated voltage V CC :
   V   CC   =V   ref (1+( R   8   +R   2 )/( R   7   +R   3 )) 
   The current monitor  20  includes a sense FET  14 , having a control node, a source node and a drain node, a resistor R 6 , a transistor Q 1 , a diode D 1 , and a resistor R 4 . The control node of sense FET  14  connects to amplifier  14 . In operation, the current that goes through the sense FET  14  is divided down by n since the size of sense FET  14  is 1/n times the size of the main FET  16 , where n is some integer value (i.e. 2, 3, 4, etc.). This same current flows across resistor R 6  and generates a voltage that is equivalent to the base emitter voltage of transistor Q 1 . Once the voltage across resistor R 6  is greater than the quiescent threshold voltage (˜0.7V) of transistor Q 1 , transistor Q 1  turns on. As a result, node P is pulled down and, thereby, the main FET  16  is turned off. Accordingly, excess current is prevented from flowing through main FET  16  after the threshold is reached. 
   Problems arise when the variations of process, temperature, voltage of the main FET  16 , sense FET  14 , and resistor R 6  cause the voltages to vary and, thereby, creating voltage mismatches within the circuit. If the drain-to-source voltage V DS  across main FET  16  and sense FET  14  do not match, the basic equation for the generating voltage V CC  will be defeated. 
     FIG. 2  shows another known current monitor  60  connected to sense the current of voltage regulator  80 . The voltage regulator  80  includes amplifier  52  coupled to the gate of the main FET  54 . The drain of the main FET  54  connects to resistors R 10  and R 12  which form a voltage divider to be fed back to the inverting input of amplifier  10 . In operation, the voltage regulator incorporates a closed loop using amplifier  52  which drives main FET  54 . The main FET  54  is connected to a voltage divider represented by resistors, R 10  and R 12 . The connection from the voltage divider is fed back to the inverted input of amplifier  52 , where the reference or bandgap voltage V ref  is fed into the non-inverting input of amplifier  52 . The following equation applies when deriving the value of V CC :
   V   CC   =V   ref (1+( R   10 )/( R   12 )) 
   Current monitor  60  includes a sense FET  62  coupled to an amplifier  64  that includes a feedback loop. Since the feedback loop exists, the voltage at node B 1  is controlled. It is necessary to make certain that the voltage at node A 1  equals the voltage at node B 1 . The current I lim /n represents the feedback current i fdb  that flows through resistor R 16 . The voltage at node C 1  is represented in the following equation:
 
 V   node C1   =V   supply   −R   16 ( I   lim   /n ).
 
Amplifier  64  controls transistor  66  such that the current through resistors, R 16  and R 18 , changes to make sure that the voltage at nodes A 1  and B 1  remain the same.
 
   In operation, if the voltage at node B 1  is greater than the voltage at node A 1  by for example 100 mV, the gate voltage of transistor  66  will rise since the gate to source voltage will increase. Initially transistor  66  is in the saturation region, once the gate to source voltage V gs  increases, the feedback current i fdb  will decrease to try to match and make the voltage at node A 1  equivalent to that of node B 1 , such that the voltage at node B 1  will decrease to equalize to that of node A 1 . 
   When the voltage at node A 1  is greater than that of node B 1 , however, the current that flows through transistor  66  will decrease and the feedback current i fdb  will increase to try to match and force transistor  66  into the saturation region. Thereby, the voltage at node B 1  will increase to that of node A 1 . 
   Problems arise when the transistors process varies, thereby the voltage and current values will differ. In addition, when the temperature and supply voltage changes, this type of current monitor fails to provide a reliable determination due to drain-to-source voltage mismatch of main FET  54  and sense FET  62 . 
   Thus, a need exists for a current monitor having a high performance, simple, and cost effective design that is independent of process, temperature and voltage. 
   The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above. 
   SUMMARY OF THE INVENTION 
   To address the above-discussed deficiencies of current monitors, the present invention teaches a current monitor having a high performance, simple, and cost effective design that is independent of process, temperature and voltage. The current monitor includes a sensing transistor that couples to the main transistor of an adjoining voltage regulator. Specifically, the control and source nodes of each transistor couple to one another, respectively. The size of the main transistor is a predetermined multiple integer n of the size of the sensing transistor. A first resistor couples between a supply voltage and the drain node of the main transistor. A second resistor couples between a supply voltage and the drain node of the sensing transistor, wherein the size of the second resistor is equal to the size of the first resistor multiplied by the predetermined multiple integer n. An inverting input of an amplifier couples to the drain node of the sensing transistor, while a third resistor connects between the supply voltage and a non-inverting input of the amplifier. A control node of a transistor connects to the output of the amplifier. A drain node of the transistor feeds back to the noninverting input of the amplifier. A feedback resistor coupled between the source node of the transistor and ground. A current source coupled to the supply voltage. A first input of a comparator connects to the current source, while the second input of a comparator couples to the source node of the transistor. A reference resistor connects between the first input of the comparator and ground. 
   These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein: 
       FIG. 1  illustrates a known voltage regulator and current monitor arrangement; 
       FIG. 2  display another known voltage regulator and current monitor arrangement; and 
       FIG. 3  shows voltage regulator and current monitor arrangement in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set for the herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. 
     FIG. 3  illustrates a voltage regulator  320  and the novel current monitor  360  arrangement in accordance with the present invention. The voltage regulator  320  includes amplifier  310  coupled to the gate of the main FET  312 . The drain of the main FET  312  connects to resistors R 10  and R 12  which form a voltage divider to be fed back to the inverting input of amplifier  310 . In operation, the voltage regulator incorporates a closed loop using amplifier  310  which drives main FET  312 . The main FET  312  is connected to a voltage divider represented by resistors, R 20  and R 22 . The connection from the voltage divider is fed back to the inverted input of amplifier  310 , where the reference or bandgap voltage V ref  is fed into the non-inverting input of amplifier  310 . The following equation applies when deriving the value of V CC :
   V   CC   =V   ref (1+( R   20 )/ R   22 )) 
   Within current monitor  360 , it is necessary that the voltage drop across resistor R S3  is equal to the voltage drop across resistor R S1 . Since amplifier  342  coupled to transistor  344  forms a feedback loop, the voltage is controlled. It is necessary to make certain that the voltage at node A 2  equals the voltage at node B 2 . The current Ilim/n represents the current that flows through resistor R S1 . The voltage at node A 2  is represented in the following equation:
 
 V   node A   =V   supply   −R   S1 ( I   lim   /n ).
 
   The amplifier  342  controls transistor  344  such that the current through resistor RS 2  changes to make sure that the voltage at nodes A 2  and B 2  remain the same. 
   A drain-to-source voltage V DS  offset cancellation is implemented by placing a resistor R S3  in series with the main FET  312  which tracks the V DS  between the main FET  312  and the sense FET  340 . The size of sense FET  340  is a predetermined multiple n of the size of the main FET  312 . Thereby, the size of resistor R S3  is equal to resistor R S1 /n. The current that flows across resistor R S3  is I lim , while the current that flows across resistor R S1  is I lim /n. Thereby, even when the battery voltage varies, it will not affect the matching between the main FET  312  and the sense FET  340 . It is important that the same amount of current must not flow through the sense FET  340  that flows through the main FET  312  or current will be wasted. The novel implementation decrements the current through the sense FET  340  by a factor of 1/n. This ratio will be constant with temperature, process, and voltage variation. 
   In operation, if the voltage at node B 2  is greater than the voltage at node A 2  by for example 100 mV, the gate voltage of transistor  344  will rise, since the gate to source voltage will increase. Initially transistor  344  is in the saturation region, once the gate-to-source voltage V gs  increases, the feedback current i fdb  will decrease to try to match and make the voltage at node A 2  equivalent to that of node B 2 , such that the voltage at node B 2  will decrease to equalize that of node A 2 . 
   When the voltage at node A 2  is greater that that of node B 2 , however, the current that flows through transistor  344  will decrease and the feedback current i fdb  will increase to try to match and make the saturation region. Thereby, the voltage at node B 2  will increase to that of node A 2 . 
   Those of skill in the art will recognize that the physical location of the elements illustrated in  FIG. 3  can be moved or relocated while retaining the function described above. 
   Advantages of this design include but are not limited to a current monitor having a high performance, simple, and cost effective design that is independent of process, temperature and voltage. 
   The reader&#39;s attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. 
   All the features disclosed in this specification (including any accompany claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. 
   The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.