Patent Publication Number: US-2023138505-A1

Title: Semiconductor device and method for fabricating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to Korean Patent Application No. 10-2021-0145646, filed on Oct. 28, 2021, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly, to a semiconductor device including a buried gate and a fabricating method thereof. 
     2. Description of the Related Art 
     In order to improve the degree of integration of the semiconductor device, a semiconductor device having a structure in which a word line is buried in a substrate is being researched. 
     SUMMARY 
     An embodiment of the present invention provides a method of fabricating a semiconductor device capable of improving word line interference between adjacent cells. 
     A semiconductor device according to an embodiment of the present invention comprises: a device isolation layer defining a plurality of active regions on a substrate and including a first region and a second region, the active regions being spaced apart in a first direction by the first region having a first interval and by the second region having a second interval, the second interval being larger than the first interval; a gate trench extending in the first direction to cross the active regions and the first and second regions of the device isolation layer; and a buried word line gap-filling the gate trench, wherein the first region of the device isolation layer disposed below the gate trench is formed by a first insulating layer, and wherein the second region of the device isolation layer disposed below the gate trench is formed by a stack structure of the first insulating layer and a second insulating layers. 
     A method of fabricating a semiconductor device according to an embodiment of the present invention comprises: forming a device isolation layer defining a plurality of active regions on a substrate and including a first region and a second region, the active regions being spaced apart in a first direction by the first region having a first interval and by the second region having a second interval, the second interval being larger than the first interval; forming a gate trench extending in the first direction to cross the active regions and the first and second regions of the device isolation layer; and forming a buried word line gap-filling the gate trench, wherein the first region of the device isolation layer disposed below the gate trench is formed by a first insulating layer, and wherein the second region of the device isolation layer disposed below the gate trench is formed by a stack structure of the first insulating layer and a second insulating layer. 
     A semiconductor device according to an embodiment of the present invention comprises: a plurality of active regions arranged along a first direction in a substrate and separated by alternating first and second regions of a device isolation layer; and a buried word line extending in the first direction and crossing the plurality of the active regions and the first and second regions of the device isolation layer, wherein the first region of the device isolation layer is formed by a first insulating layer and the second region of the device isolation layer is formed by a stack of the first insulating layer and a second insulating layer. 
     The present invention has the effect of improving the reliability of the semiconductor device by improving the word line interference between adjacent cells. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a plan view of a semiconductor device according to an embodiment of the present invention. 
         FIGS.  2 A and  2 B  are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention. 
         FIGS.  3  and  4    are cross-sectional views illustrating semiconductor devices according to embodiments of the present invention. 
         FIGS.  5 A to  5 H  are cross-sectional views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention. 
         FIGS.  6 A to  6 D  are cross-sectional views illustrating a method of fabricating the semiconductor device illustrated in  FIG.  3   . 
         FIGS.  7 A to  7 E  are cross-sectional views illustrating a method of fabricating the semiconductor device illustrated in  FIG.  4   . 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments described herein will be described with reference to cross-sectional views, plan views and block diagrams, which are schematic views of the present invention. Therefore, the structures of the drawings may be modified by fabricating tolerances. Various embodiments of the present invention are not limited to the specific structures shown in the drawings, but may include any changes in the structures that may be produced according to a fabricating process. Also, any regions and shapes of regions illustrated in the drawings with schematic views are intended to illustrate specific examples of structures of regions of the various elements, and are not intended to limit the scope of the invention. 
       FIG.  1    is a plan view of a semiconductor device according to an embodiment of the present invention.  FIGS.  2 A and  2 B  are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention.  FIG.  2 A  is a cross-sectional view taken along line A-A′ of  FIG.  1   , and  FIG.  2 B  is a cross-sectional view taken along line B-B′ of  FIG.  1   .  FIGS.  3  and  4    are cross-sectional views illustrating semiconductor devices according to embodiments of the present invention.  FIGS.  3  and  4    are cross-sectional views taken along line A-A′ of  FIG.  1   . 
     Referring to  FIGS.  1 ,  2 A, and  2 B , the semiconductor device according to an embodiment of the present invention may include a substrate  101  including an active region  103 , an isolation layer  102 , and gate structures BG formed in the substrate  101 . In addition, the semiconductor device may include bit lines BL and capacitors CAP formed on the substrate  101 . 
     The substrate  101  may be any material suitable for semiconductor processing. The substrate  101  may include a semiconductor substrate. The substrate  101  may be made of a material containing silicon. The substrate  101  may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon doped silicon, combinations thereof, or multiple layers thereof. The substrate  101  may include other semiconductor materials such as germanium. The substrate  101  may include a III/V group semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs). The substrate  101  may include a silicon on insulator (SOI) substrate. 
     The active region  103  defined by the device isolation layer  102  may be formed to have a major axis and a minor axis, and may be two-dimensionally arranged along the major axis direction and the minor axis direction. For example, the active region  103  may have a bar shape having a length longer than a width, and may be arranged in an island shape. 
     The device isolation layer  102  may include a device isolation trench  102 T defining a plurality of active regions  103  in the substrate  101  and an insulating layer gap-filled in the device isolation trench  102 T. In the device isolation layer  102 , an insulating structure gap-filling a region of the device isolation trench  102 T overlapping the field trench  105 F and an insulating structure gap-filling a region of the device isolation trench  102 T excluding the field trench  105 F may be different. The field trench  105 F may refer to the gate trench  105  formed in the device isolation trench  102 T. 
     The isolation insulating layer  102 R may be gap-filled in the device isolation trench  102 T in a region excluding the field trench  105 F. The top surface of the isolation insulating layer  102 R may be at the same level as the top surface of the substrate  101 . The insulating structure gap-filling a region of the device isolation trench  102 T overlapping the field trench  105 F may be different from an insulating structure in which the active regions  103  are spaced apart in the first direction D 1  by the first region R 1  having a first interval and from an insulating structure in which the active regions  103  are spaced apart in the first direction D 1  by the second region R 2  having a second interval which is greater than the first interval. A first insulating layer  102 L may be gap-filled in the first and second regions R 1  and R 2  to a first height. In the second region R 2 , the second insulating layer  102 U may be locally formed on the first insulating layer  102 L. The isolation insulating layer  102 R and the first insulating layer  102 L may be continuous. The isolation insulating layer  102 R and the first insulating layer  102 L may include the same material formed through the same process. 
     For example, the device isolation layer  102  may include the isolation insulating layer  102 R gap-filled in the device isolation trench  102 T, the first insulating layer  102 L gap-filled by a first height in the first and second regions R 1  and R 2  of the device isolation trench  102 T overlapping the field trench  105 F, and the second insulating layer  120 U locally formed over the first insulating layer  102 L in the second region R 2 . 
     The top surface of the first insulating layer  102 L may be located at a level lower than the top surface of the active region  103 . The active region  103  protruding between the first insulating layer  102 L may be referred to as a ‘fin  103 F.’ The first insulating layer  102 L may be formed to be gap-filled in the device isolation trench  102 T so that a sidewall thereof is in contact with the active region  103 . The first insulating layer  102 L may include, for example, silicon oxide. 
     The second insulating layer  102 U may be locally formed on the first insulating layer  102 L gap-filled in the second region R 2  of the device isolation trench. The second insulating layer  102 U may be formed to have a width smaller than the width of the second region R 2 . That is, the width W 2  of the second insulating layer  102 U may be smaller than the width W 1  of the first insulating layer  102 L formed in the second region R 2  (W 1 &gt;W 2 ). The sidewall of the second insulating layer  102 U may be spaced apart from the sidewall of the adjacent active region  103 . In the second region R 2 , the first insulating layer  102 L may be exposed between the second insulating layer  102 U and the adjacent active region  103 . Accordingly, fins  103 F of the same height may be formed by the first insulating layer  102 L disposed below the active region  103  in both the active regions  103  in contact with the first region R 1  and the second region R 2 , respectively. The second insulating layer  102 U may include, for example, silicon oxide. The second insulating layer  102 U may include the same material as the first insulating layer, or may include a different material. 
     The top surface of the second insulating layer  102 U may be located at a higher level than the top surface of the first insulating layer  102 L. That is, the top surface of the device isolation layer  102  formed in the first region R 1  may be located at a lower level than the top surface of the device isolation layer  102  formed in the second region R 2 . In this embodiment, the top surface of the second insulating layer  102 U may be located at a lower level than the top surface of the active region  103 . 
     In another embodiment, as shown in  FIG.  3   , the top surface of the second insulating layer  202 U may be positioned at the same level as the top surface of the active region  103 . 
     In another embodiment, as shown in  FIG.  4   , the top surface of the second insulating layer  302 U may be located at a higher level than the top surface of the active region  103 . 
     The word lines WL 1  and WL 2  may cross the active regions  103  and extend in a first direction D 1 . The bit lines BL may extend in a second direction D 2  crossing the first direction D 1 . The first direction D 1  and the second direction D 2  may cross perpendicularly. 
     As shown in  FIG.  1   , the active regions  103  are arranged to be tilted at a predetermined angle with respect to the word lines  109  (WL 1  and WL 2 ) and the bit lines BL, so that one active region  103  may cross two word lines WL and one bit line BL. Accordingly, one active region  103  has a structure of two unit cells, and one unit cell has a length of  2 F in the first direction D 1  and a length of  4 F in the second direction where “F” is the minimum feature size. Thus, the area of the unit cell is  6 F 2 . 
     According to the  6 F 2  cell structure, in order to minimize the cell area, the word line WL 1  and WL 2  and the bit line BL cross each other vertically and the active regions  103  are tilted in a diagonal direction with respect to the word line WL 1  and WL 2  and the bit line BL. The semiconductor device according to the present invention is not limited to the  6 F 2  cell structure, and may include any cell structure capable of improving the integration degree of the semiconductor device. 
     The gate structures BG may include gate trenches  105  formed in the substrate  101 , gate insulating layers  108  uniformly formed on inner walls of the gate trenches  105 , the word lines  109  partially filling the inside of the gate trenches  105 , and the gate capping layer  110  filling the remainder of the gate trenches  105  on the word line  109 . 
     The word line  109  is formed of buried gate lines, thereby implementing a buried channel transistor. The buried channel transistor may reduce a unit cell area and increase an effective channel length compared to a planar transistor. In addition, in the buried channel transistor, since the word line  109  is buried in the substrate  101 , the capacitance between the word line  109  and the bit line BL and the total capacitance of the bit line BL can be lowered to reduce parasitic capacitance. 
     The gate trench  105  may include an active trench  105 A crossing the active region  103  and a field trench  105 F formed in the device isolation layer  102 . The gate trench  105  may extend continuously from active trench  105 A to field trench  105 F. 
     The word line  109  may include an active gate electrode  109 A in the active trench  105 A and a field gate electrode  109 P in the field trench  105 F. Top surfaces of the active gate electrode  109 A and the field gate electrode  109 P may be located at the same level. The word line  109  may include a fin gate electrode  109 F formed in the fin  103 F along the first direction D 1 . The fins  103 F may be formed on both sides of the active region  103  in the first direction. That is, the fin  103 F may be formed between the active region  103  and the field trench  105 F in the second region R 2  and also be formed in the first region R 1  of the device isolation layer  102 . 
     A depth H 3  of the fin gate electrode  109 F may be greater than a depth H 2  of the field gate electrode  109 P. The bottom surface of the fin gate electrode  109 F may be located at a level lower than the bottom surface of the field gate electrode  109 P. The bottom surface of the fin gate electrode  109 F may be located at a lower level than the bottom surface of the active gate electrode  109 A in the first region R 1  of the device isolation layer  102  where word line interference between neighboring cells does not occur. Accordingly, the channel length may be sufficiently secured by the fin gate electrode  109 F to increase the driving current of the transistor and improve the operating characteristics. 
     Referring to  FIG.  2 B , a first impurity region  111  and a second impurity region  112  serving as a source and a drain of the transistor may be formed in the active region  103  disposed on both sides of the active gate electrode  109 A. The first impurity region  111  may be electrically connected to the bit line BL, and the second impurity region  112  may be electrically connected to the capacitor CAP. The bit line BL and the first impurity region  111  may be electrically connected to each other by a bit line contact plug BLC. The capacitor CAP and the second impurity region  112  may be electrically connected to each other by a storage contact plug SNC. 
     The active trench  105 A and the field trench  105 F may have different levels of bottom surfaces. The depth H 1  of the active trench  105 A may be smaller than the depths H 3  and H 2  of the field trench  105 F in the first and second regions R 2 . The bottom surface of the field trench  105 F may be located at a level lower than the bottom surface of the active trench  105 A. The field trench  105 F may have bottom surfaces at different levels in the first region R 1  and the second region R 2 . 
     In an embodiment of the present invention, the depth H 2  of the field trench  105 F of the second region R 2  may be smaller than the depth H 3  of the field trench  105 F of the first region R 1  due to the second insulating layer  102 U. See, for example,  FIG.  2 A . For example, the depth of the field gate electrode  109 P, that is the passing gate crossing the device isolation layer  102  formed between the second impurity regions  112  of the active regions  103  adjacent to each other with one word line  109  interposed therebetween, may be as shallow as the thickness of the second insulating layer  102 U. Accordingly, the area of the field gate electrode  109 P of a word line facing the active gate electrode  109 A of an adjacent word line is reduced, thereby preventing word line interference between neighboring cells (Row Hammer). The effect of preventing the word line interference phenomenon may increase as the area of the field gate electrode  109 P decreases. 
     In another embodiment, as shown in  FIG.  3   , the depth H 2  of the field trench  105 F in the second region R 2  may be similar to the depth H 1  of the active trench  105 A. The depth H 3  of the field trench  105 F in the first region R 1  may be greater than the depth H 2  of the field trench  105 F in the second region R 2 . 
     In another embodiment, as shown in  FIG.  4   , the depth H 2  of the field trench  105 F in the second region R 2  may be smaller than the depth H 1  of the active trench  105 A and the depth H 3  of the field trench  105 F in the first region R 1 . The depth H 3  of the field trench  105 F in the first region R 1  may be greater than the depth H 1  of the active trench  105 A. 
       FIGS.  5 A to  5 H  are cross-sectional views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention.  FIGS.  5 A to  5 H  are cross-sectional views taken along line A-A′ of  FIG.  1   . 
     As shown in  FIGS.  1  and  5 A , the device isolation trenches  102 T defining a plurality of active regions  103  may be formed in the substrate  101 . 
     The substrate  101  may be a material suitable for semiconductor processing. The substrate  101  may include a semiconductor substrate. The substrate  101  may be made of a material containing silicon. The substrate  101  may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon doped silicon, combinations thereof, or multiple layers thereof. The substrate  101  may include other semiconductor materials such as germanium. The substrate  101  may include a III/V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate  101  may include a silicon on insulator (SOI) substrate. 
     The active region  103  defined by the device isolation trench  102 T may be formed to have a major axis and a minor axis, and may be two-dimensionally arranged along the major axis direction and the minor axis direction. For example, the active region  103  may have a bar shape having a length longer than a width, and may be arranged is in an island shape. 
     The device isolation trench  102 T may include a first region R 1  and a second region R 2 . The active regions  103  may be spaced apart by the first region R 1  having a first interval along the first direction. The active regions  103  may be spaced apart by the second region R 2  having a second interval. 
     As shown in  FIGS.  1  and  5 B , the device isolation layer  102 A gap-filling the device isolation trench  102 T may be formed. For example, the insulating material may include silicon oxide. The device isolation layer  102 A may be formed through a series of processes of gap-filling an insulating material in the device isolation trench  102 T and etching the insulating material with the top surface of the substrate  103  as a target. The device isolation layer  102 A may be formed by a shallow trench isolation (STI) process. 
     As shown in  FIGS.  1  and  5 C , the gate trench  105  extending along the short axis direction of the active region  103  may be formed. The bottom surface of the gate trench  105  may be located at a higher level than the bottom surface of the device isolation trench  102 T. 
     The gate trench  105  may include an active trench  105 A crossing the active region  103  and a field trench  105 F formed in the device isolation layer  102 B. The gate trench  105  may continuously extend from the active trench  105 A to the field trench  105 F. The device isolation layer  102 B excluding the field trench  105 F may have the top surface at the same level as the top surface of the substrate  101 . The device isolation layer  102 B excluding the field trench  105 F may be referred to as an ‘isolation insulating layer  102 R’ (refer to  FIG.  2 B ). 
     As shown in  FIGS.  1  and  5 D , the device isolation layer  102 B (refer to  FIG.  5 C ) buried in the field trench  105 F may be further recessed. Accordingly, the bottom surface of the field trench  105 F may be located at a lower level than the bottom surface of the active trench  105 A. 
     The device isolation layer  102 B gap-filled in the device isolation trench  102 T overlapping the field trench  105 F may be referred to as a ‘first insulating layer  102 L.’ 
     The top surface of the first insulating layer  102 L may be located at a level lower than the top surface of the active trench  105 A. A protruding region of the active region  103  above the first insulating layer  102 L may be referred to as a ‘fin  103 F.’ 
     As shown in  FIGS.  1  and  5 E , a sacrificial spacer  106  may be formed on both sidewalls of the fin  103 F. The sacrificial spacer  106  may include an insulating material having an etch selectivity with respect to the device isolation layer  102 . For example, the sacrificial spacer  106  may include silicon nitride. 
     The sacrificial spacer  106  may be formed through, for example, a topology selective atomic layer deposition (TS-ALD) process. TS-ALD may include plasma ALD, and in particular, refers to a process of selectively depositing only on a horizontal surface or a vertical sidewall according to a plasma parameter. 
     The field trench  105 F disposed between the active regions  103  adjacent in the first direction D 1 , that is, the first region R 1  of the substrate isolation trench  102 T may be all gap-filled by the sacrificial spacer  106 . The sacrificial spacer  106  may be formed thickly on the sidewall of the fin  103 F to gap-fill all the first regions R 1  of the device isolation trench  102 T, and the sacrificial spacer  106  may be formed thinly on the top surface of the fin  103 F. The sacrificial spacer  106  formed on the sidewall of the fin  103 F to gap-fill all the first regions R 1  of the device isolation trench  102 T may have a first thickness. The sacrificial spacer  106  formed on the top surface of the fin  103 F may have a second thickness which is smaller than the first thickness. That is, both the top surface and the sidewall of the fin  103 F may be covered by the sacrificial spacers  106  having different thicknesses. In the second region R 2  of the device isolation trench  102 T, since the sacrificial spacer  106  is formed only on the sidewall of the adjacent active region  103 , all other regions are exposed. 
     As shown in  FIGS.  1  and  5 F , the insulating material layer  107  may be formed. The insulating material layer  107  may cover at least a part of the sacrificial layer  106 . 
     The insulating material layer  107  may include an insulating material having an etch selectivity with respect to the sacrificial spacer  106 . The insulating material layer  107  may include the same oxide material as the first insulating layer  102 L. For example, the insulating material layer  107  may include silicon oxide. In another embodiment, the insulating material layer  107  may include a different oxide material from the first insulating layer  102 L. 
     The insulating material layer  107  may be formed to have a low step coverage characteristic. The insulating material layer  107  may be thickly formed on a horizontal plane parallel to the surface of the substrate  101  and thinly formed in a direction perpendicular to the surface of the substrate  101 . For example, the insulating material layer  107  may be thickly formed on the first insulating layer  102 L formed in the second region R 2  of the device isolation trench  102 T and the sacrificial spacer  106  formed on the top surface of the fin  103 F. The insulating material layer  107  may be thinly formed on the sacrificial spacer  106  formed on the sidewall of the fin  103 F. 
     As shown in  FIGS.  1  and  5 G , the sacrificial spacer  106  (refer to  FIG.  5 F ) may be removed. The process of removing the sacrificial spacer  106  may be performed under conditions of having an etch selectivity with respect to the first insulating layer  102 L and the insulating material layer  107 . 
     The insulating material layer  107  formed on the sacrificial spacer  106  and the fin  103 F may be removed together when the sacrificial spacer  106  is removed. For example, since the top surface and the sidewall of the fin  103 F are all covered by the sacrificial spacer  106 , the insulating material layer  107  formed on the fin  103 F may be removed when the sacrificial spacer  106  formed between the top surface of the fin  103 F and the insulating material layer  107  is removed. As a result, both the top surface and both sidewalls of the fin  103 F may be exposed. 
     The stack structure of the first insulating layer  102 L and the second insulating layer  102 U may remain in the second region R 2  of the device isolation trench  102 T, and the first insulating layer  102 L may remain in the first region R 1  of the device isolation trench  102 T. 
     As shown in  FIGS.  1  and  5 H , a buried gate structure BG may be formed to gap-fill the gate trench  105 . 
     The buried gate structure BG may include a gate insulating layer  108  covering the surface of the gate trench  105  including the fin  103 F, a gate electrode  109  gap-filling a portion of the gate trench  105  over the gate insulating layer  108 , and a gate capping layer  110  gap-filling the remainder of the gate trench  105  over the gate electrode  109 . For example, the gate insulating layer  108  may be formed through an oxidation process. In another embodiment, the gate insulating layer  108  may be formed over the active trench  105 A and the field trench  105 F of the gate trench  105  depending on a fabricating process. 
     The buried gate structure BG may be referred to as a ‘word line WL.’ Since the word line is formed of buried gate lines, a buried channel transistor may be implemented. The buried channel transistor may reduce a unit cell area and increase an effective channel length compared to a planar transistor. In the buried channel transistor, since the word line is buried in the substrate, the capacitance between the word line and the bit line and the total capacitance of the bit line can be lowered to reduce parasitic capacitance. 
     As described above, in the present embodiment, by additionally forming the second insulating layer  102 U on the second region R 2  of the device isolation trench  102 T overlapping the field trench  105 F, the depth of the field gate electrode  109 P, that is, the passing gate which crosses the device isolation layer  102  formed between the second impurity regions  112  of the active regions  103  adjacent to each other with one word line  109  interposed therebetween, may be as shallow as a thickness of the second insulating layer  102 U. Accordingly, the area of the field gate electrode  109 P of a word line facing the active gate electrode  109 A of an adjacent word line is reduced, thereby preventing word line interference between neighboring cells (Row Hammer). 
     For example, when the first word line WL 1  of  FIG.  1    is turned off and the second word line WL 2  is turned on, the area of the field gate electrode of the second word line facing the active gate electrode of the first word line WL 1  is reduced. Then, the parasitic capacitance between the active gate electrode of the first word line WL 1  and the field gate electrode of the second word line WL 2  is reduced. Accordingly, it is possible to prevent the word line interference phenomenon in which the voltage applied to the field gate electrode of the second word line WL 2  increases the potential of the channel region under the active gate electrode of the turned-off first word line WL 1 . 
       FIGS.  6 A to  6 D  are cross-sectional views illustrating a method of fabricating the semiconductor device illustrated in  FIG.  3   .  FIGS.  6 A to  6 D  refer to the process after  FIG.  5 E . Among the reference numerals shown in  FIGS.  6 A to  6 D , the same reference numerals as those shown in  FIGS.  5 A to  5 H  indicate the same components. 
     As shown in  FIGS.  1  and  6 A , an insulating material layer  207  may be formed on the entire surface including the sacrificial spacer  106  formed by the process illustrated in  FIG.  5 E . The insulating material layer  207  may be formed to have a thickness such that the top surface of the insulating material layer  207  is located at a higher level than the top surface of the fin  103 F. 
     The insulating material layer  207  may include an insulating material having an etch selectivity with respect to the sacrificial spacer  106 . The insulating material layer  207  may include the same oxide material as the first insulating layer  102 L. For example, the insulating material layer  207  may include silicon oxide. In another embodiment, the insulating material layer  207  may include a different oxide material from the first insulating layer  102 L. 
     The insulating material layer  207  may be formed by, for example, a chemical vapor deposition process or an atomic layer deposition process. 
     As shown in  FIGS.  1 ,  6 B and  6 C , the insulating material layer  207  may be etched with a target such that the top surface of the fin  103 F is exposed. The insulating material layer  207  may be etched through a planarization process. The planarization process may include an etch-back process or a chemical mechanical polishing (CMP) process. In another embodiment, the insulating material layer  207  may be subjected to a planarization process with a target such that the sacrificial spacer  106  formed on the top surface of the fin  103 F is exposed. 
     The sacrificial spacer  106  may then be removed. The process of removing the sacrificial spacer  106  may be performed under conditions of having an etch selectivity with respect to the first insulating layer  102 L and the insulating material layer  207 . The insulating material layer  207  remaining between the sacrificial spacers  106  in the first region R 1  of the device isolation trench  102 T may be removed together when the sacrificial spacers  106  are removed. Also, the upper edge of the insulating material layer  207  formed between the sacrificial spacers  106  in the second region R 2  of the device isolation trench  102 T may be partially lost when the sacrificial spacer  106  is removed or during a cleaning process. 
     Accordingly, the second region R 2  of the device isolation trench  102 T may be formed to have a stack structure of the first insulating layer  102 L and the second insulating layer  202 U having a top surface at the same level as the top surface of the fin  103 F. The first insulating layer  102 L may remain in the first region R 1  of the device isolation trench  102 T. 
     As shown in  FIGS.  1  and  6 D , a buried gate structure BG may be formed to gap-fill the gate trench  105 . 
     The buried gate structure BG may include a gate insulating layer  108  covering the surface of the gate trench  105  including the fin  103 F, a gate electrode  109  gap-filling a portion of the gate trench  105  over the gate insulating layer  108 , and a gate capping layer  110  gap-filling the remainder of the gate trench  105  over the gate electrode  109 . In another embodiment, the gate insulating layer  108  may be formed over the active trench  105 A and the field trench  105 F of the gate trench  105  depending on a fabricating process. 
     In the device isolation layer  202  under the buried gate structure BG, the stack structure of the first insulating layer  102 L and the second insulating layer  202 U remains in the second region R 2 , and the first insulating layer  102 L remains in the first region R 1 . 
       FIGS.  7 A to  7 E  are cross-sectional views illustrating a method of fabricating the semiconductor device illustrated in  FIG.  4   .  FIGS.  7 A to  7 E  refer to the process to be performed after the process shown in  FIG.  5 E . Among the reference numerals illustrated in  FIGS.  7 A to  7 E , the same reference numerals as those illustrated in  FIGS.  5 A to  5 H  indicate the same components. 
     As shown in  FIGS.  1  and  7 A , an insulating material layer  307  may be formed on the entire surface including the sacrificial spacer  106  formed by the process shown in  FIG.  5 E . The insulating material layer  307  may be formed to have a thickness such that the top surface of the insulating material layer  307  is positioned at a higher level than the top surface of the fin  103 F. 
     The insulating material layer  307  may include an insulating material having an etch selectivity with respect to the sacrificial spacer  106 . The insulating material layer  307  may include the same oxide material as the first insulating layer  102 L. For example, the insulating material layer  307  may include silicon oxide. In another embodiment, the insulating material layer  307  may include a different oxide material from the first insulating layer  102 L. 
     The insulating material layer  307  may be formed by, for example, a chemical vapor deposition process or an atomic layer deposition process. 
     As shown in  FIGS.  1 ,  7 B, and  7 C , a mask pattern  310  may be formed on the insulating material layer  307  of the second region R 2  of the device isolation trench  102 T. The mask pattern  310  may be patterned smaller than the passing gate region. The mask pattern  310  may be formed to have an island shape. A width of the mask pattern  310  in the first direction D 1  may be smaller than a line width of the second region R 2 . A width of the mask pattern  310  in the second direction D 2  may be the same as the line width of the gate trench  105 . 
     Next, the insulating material layer  307  may be etched by using the mask pattern  310 . The etching of the insulating material layer  307  may be performed under a condition having an etching selectivity with respect to the substrate  101  and the sacrificial spacer  106 . Accordingly, the second insulating layer  302 U having a top surface at a higher level than the top surface of the fin  103 F may be formed. 
     Subsequently, the mask pattern  310  may be removed. 
     As shown in  FIGS.  1  and  7 D , the sacrificial spacer  106  (refer to  FIG.  7 C ) may be removed. The process of removing the sacrificial spacer  106  may be performed under a condition of having an etch selectivity with respect to the first insulating layer  102 L and the second insulating layer  302 U. 
     Accordingly, the stack structure of the first insulating layer  102 L and the second insulating layer  302 U may remain in the second region R 2  of the device isolation trench  102 T, and the first insulating layer  102 L may remain in the first region R 1  of the device isolation trench  102 T. 
     As shown in  FIGS.  1  and  7 E , a buried gate structure BG may be formed to gap-fill the gate trench  105 . 
     The buried gate structure BG may include a gate insulating layer  108  covering the surface of the gate trench  105  including the fin  103 F, a gate electrode  109  gap-filling a portion of the gate trench  105  over the gate insulating layer  108 , and a gate capping layer  110  gap-filling the remainder of the gate trench  105  over the gate electrode  109 . In another embodiment, the gate insulating layer  108  may be formed over the active trench  105 A and the field trench  105 F of the gate trench  105  depending on a fabricating process. 
     In the device isolation layer  302  under the buried gate structure BG, the stack structure of the first insulating layer  102 L and the second insulating layer  302 U remains in the second region R 2 , and the first insulating layer  102 L remains in the first region R 1 . 
     The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it will be apparent to those skilled in the art that various substitutions, modifications, and changes may be made thereto without departing from the spirit and scope of the present invention.