Patent Publication Number: US-6992911-B2

Title: Semiconductor memory device

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to a semiconductor memory device utilizing the polarization of a ferroelectric, particularly to a reference potential generation circuit for use in a ferroelectric memory circuit in order to determine a data state of a memory cell formed of a single transistor and a single ferroelectric capacitor. 
     A semiconductor memory device using a ferroelectric capacitor is a memory device utilizing the spontaneous polarization property of a ferroelectric used as a capacitive dielectric of a capacitor. On this account, it has characteristics that the refresh operation is unnecessary, which is needed for DRAM (Dynamic Random Access Memory) being a traditional semiconductor memory device, and data stored in memory cells is not lost irrespective of the state of a power source. 
     For the memory cell using the ferroelectric, there are those formed of a single MOS (Metal Oxide Semiconductor) transistor and a single ferroelectric capacitor (1T/1C) which is traditionally adopted in DRAM and those formed of two MOS transistors and two ferroelectric capacitors (2T/2C). Particularly, from increasing demands of downsizing and greater integration of semiconductor devices in recent years, attention is focused on the memory cell of the 1T1C structure in these memory cell configurations. 
     However, in the case of the semiconductor memory device using the ferroelectric memory cell of the 1T/1C structure, the space required for each memory cell is reduced to be suitable for greater integration, but the reference potential for amplifying the signals of the memory cells is needed when data stored in the memory cells is read out. More specifically, a reference potential generation circuit for generating the reference potential is required. 
     As a traditional reference generation circuit, it is described in JP-A-8-115596, for example. 
       FIG. 7  depicts a traditional example. The reference generation circuit is configured of bit lines BL and complementary bit lines BLb, both to be paired, reference cells RMC 0  to RMC 3  connected to each of the bit lines BL or the complementary bit lines BLb, reference word lines RWL, and a reference plate line RPL. 
     These reference cells RMC 0  to RMC 3  are disposed at the intersection of each of the bit lines and the reference word lines. 
     Among the reference cells RMC 0  to RMC 3 , the reference cells RMC 0  and RMC 2  are connected to bit lines BL 0  and BL 1 , which are configured of select transistors RT 0  and RT 2  operated by a reference word line RWL 1  and ferroelectric capacitors H 0  and H 2  that one terminals are connected to the select transistors RT 0  and RT 2  and the others are connected to the reference plate line RPL. In addition, the reference cells RMC 1  and RMC 3  are connected to complementary bit lines BLb 0  and BLb 1 , which are configured of select transistors RT 1  and RT 3  operated by a reference word line RWL 0  and ferroelectric capacitors H 1  and H 3  that one terminals are connected to select transistors RT 1  and RT 3  and the others are connected to the reference plate line RPL. 
     Furthermore, a switching transistor T 4  is connected between the two bit lines BL to which the reference cells RMC 1  and RMC 3  are connected, and a switching transistor T 5  is connected between the two complementary bit lines BLb to which the reference cells RMC 0  and RMC 2  are connected. The switching transistors T 4  and T 5  are operated by a bit line equalizer signal EQ 0  or EQ 1 . 
     The semiconductor memory device having the traditional 1T/1C structure has a reference control circuit for generating control signals for the reference potential generation circuit, word lines WL 0  and WL 1  and plate lines PL in addition to the reference potential generation circuit described above, and is configured of a sense amplifier circuit SA connected between one line of the bit lines BL or complementary bit lines BLb to which the reference cells RMC 0  to RMC 3  are connected and one line of the bit lines BL or complementary bit lines BLb to which memory cells MC 0  to MC 3  are connected, the sense amplifier circuit SA compares the potential generated in each of the bit lines and amplifies the signals of the memory cell. 
     Next, the readout operation in the semiconductor memory device having the traditional 1T/1C structure will be described. Here, the operation to read the data out of the MC 0  into which Data  1  is written will be described, for example, where first data (Data  1 ) is set to power source potential Vdd and second data (Data  0 ) is set to ground potential Vss. 
     When the data of the MC 0  connected to the bit line BL 0  is read out, Data  1  is written into the complementary bit line BLb 0  to which the potential reference potential is applied and into the reference cell connected to the BLb 1  through the BLb 0  and the switching transistor T 4 , the RMC 1 , for example, and Data  0  is written into the other RMC 3  beforehand. 
     First, when a memory cell block including the MC 0  is selected, a block select signal becomes active, and then the reference control circuit is activated by receiving the block select signal. 
     Subsequently, when the word line WL 0  is activated and then the plate line PL 0  is activated, the memory cell MC 0  connected to these lines is selected, and the charge corresponding to the data written in the MC 0  is carried to the BL 0 . At the same time, the reference word line RWL 0  and the reference plate line RPL are activated, and the charge corresponding to Data  1  written in the RMC 1  connected to these lines is carried to the BLb 0 , and the charge corresponding to Data  0  written in the RMC 3  is carried to the BLb 1 . 
     After that, the bit line equalizer signal EQ 0  is activated to operate switching transistor T 4 , and then the BLb 0  is connected to the BLb 1 . More specifically, the BLb 0  and BLb 1  are short-circuited. At this time, the potential of each of the complementary bit lines BLb 0  and BLb 1  is turned to the intermediate potential of the potential held by each of the complementary bit lines before the short circuit because the capacitances held by the BLb 0  and BLb 1  are nearly the same. The intermediate potential becomes the reference potential used when data is read out of the memory cell MC 0 . 
     In this manner, after the reference potential is generated in the BLb 0 , the reference control circuit turns the EQ 0  inactive to separate the BLb 0  from the BLb 1 . At the same time, a sense amplifier circuit SA 000  is activated, and the potential corresponding to Data  1  stored in the MC 0  that is amplified by the SA 000  and shown in the BL 0  and the reference potential shown in the BLb 0  are outputted to a digit line DB and complementary digit bit line DBb as data. 
     SUMMARY OF THE INVENTION 
     In the case of the reference potential generation circuit based on the reference cell having the traditional ferroelectric capacitor, when defective conditions occur in the reference memory cell RMC 1 , for example, caused by process variations, a malfunction is likely to occur in data readout of the memory cell (the memory cell connected to the bit lines BL 0  and BL 1 ) to read out data by comparing the reference potential generated in the complementary bit line BLb 0  connected to the RMC 1  and in the complementary bit line BLb 1  short-circuited with the complementary bit line BLb 0 . 
     In the case of the traditional reference potential generation circuit for generating the reference potential based on the data held by the reference memory cell, when the reference cell RMC 1  that is supposed to hold Data  1  is under defective conditions, a desired potential is outputted to the bit lines BL 0  and BL 1  and the complementary bit line BLb 0  other than the complementary bit line BLb 1 , but the potential (ΔV 1 ) corresponding to Data  1  is not outputted to the complementary bit line BLb 1 , and the ground potential (0 V), for example, is outputted. More specifically, even though the BLb 0  and BLb 1  are short-circuited, only the reference potential of ΔV 0 /2 is generated in the BLb 0  and BLb 1  because the BLb 0  is ΔV 0  and the BLb 1  is 0 V. 
     In this case, when the reference potential is generated in the BLb 0  and BLb 1  and then the sense amplifier circuits SA 000  and SA 001  connected to the BLb 0  or BLb 1  are activated to read data out of the memory cell MC 0  connected to the BL 0  and data held in the memory cell MC 2  connected to the BL 1 , the following problem arises particularly when Data  0  held in the MC 0  and MC 2  is read out. 
     When the data held in the MC 0  and MC 1  is read out, the sense amplifier circuits SA 000  and SA 001  connected between the bit lines and the complementary bit lines to be paired (BL 0  and BLb 0 , BL 1  and BLb 1 ) are activated, the potential difference from the reference potential is compared and then the data held in the memory cells (the MC 0  and MC 1 ) is read out. However, when the reference potential generated in the BLb 0  and BLb 1  is the potential lower than the intermediate potential of ΔV 0  and ΔV 1  due to the defective conditions of the RMC 1  is, particularly when the reference potential is the potential lower than ΔV 0  (for example, ΔV 0 /2), the reference potential (ΔV 0 /2) of the BLb 0  and BLb 1  always becomes the potential lower than the potential (ΔV 0 ) corresponding to Data  0 . Therefore, the output of the sense amplifier circuits SA is likely to be Data  1 , not Data  0 . 
     More specifically, even though defective conditions do not occur in the entire memory cells MC connected to the BL 0  and the BL 1  which use the RMC 1  as the reference cell for generating the reference potential, the normal operation of the semiconductor memory device is greatly affected when defective conditions occur in one of the reference memory cells RMC 1 . The defective conditions of the reference memory cells RMC greatly affect yields more than the defective conditions of the memory cells MC do. 
     Then, an object of the invention is to provide a reference potential generation circuit to reduce an influence upon the yields of reference cells with the downsizing and greater integration of a semiconductor memory device maintained, and to provide a more highly reliable semiconductor memory device. 
     In order to solve the problems, a first semiconductor memory device according to the invention includes: 
     a first bit line; 
     a memory cell formed of a first transistor connected to the first bit line and a first ferroelectric capacitor connected to the first transistor; 
     a second bit line; 
     a first reference cell formed of a second transistor connected to the second bit line and to a first word line to be controlled and a second ferroelectric capacitor connected to the second transistor, the first reference cell for holding a potential corresponding to predetermined data; 
     a third bit line; 
     a second reference cell formed of a third transistor connected to the third bit line and to the first word line to be controlled and a third ferroelectric capacitor connected to the third transistor, the second reference cell for holding a potential corresponding to predetermined data; 
     a first redundant reference cell formed of a fourth transistor connected to the second bit line and to a second word line to be controlled and a fourth ferroelectric capacitor connected to the fourth transistor, the first redundant reference cell for holding a potential corresponding to predetermined data; 
     a second redundant reference cell formed of a fifth transistor connected to the third bit line and to the second word line to be connected and a fifth ferroelectric capacitor connected to the fifth transistor, the second redundant reference cell for holding a potential corresponding to predetermined data; 
     a switching circuit connected between the second bit line and the third bit line for electrically connecting the second bit line to the third bit line in response to a first control signal and generating a reference potential in the second bit line and the third bit line; 
     a data read-out circuit connected to any one of the second bit line and the third bit line and to the first bit line for comparing the reference potential with a potential generated in the first bit line; and 
     a word line select circuit for selecting any one of the first word line and the second word line and generating the reference potential in the second bit line and the third bit line by the first and second redundant reference cells by selecting the second word line when the first or second reference cell is defective. 
     In addition, a second semiconductor memory device according to the invention includes: 
     a first bit line; 
     a first memory cell formed of a first transistor connected to the first bit line and a first ferroelectric capacitor connected to the first transistor; 
     a second bit line; 
     a first reference cell formed of a second transistor connected to the second bit line and to a first word line to be controlled and a second ferroelectric capacitor connected to the second transistor, the first reference cell for holding a potential corresponding to predetermined data; 
     a third bit line; 
     a second reference cell formed of a third transistor connected to the third bit line and to the first word line to be controlled and a third ferroelectric capacitor connected to the third transistor, the second reference cell for holding a potential corresponding to predetermined data; 
     a first redundant reference cell formed of a fourth transistor connected to the second bit line and to a second word line to be controlled and a fourth ferroelectric capacitor connected to the fourth transistor, the first redundant reference cell for holding a potential corresponding to predetermined data; 
     a second redundant reference cell formed of a fifth transistor connected to the third bit line and to the second word line to be controlled and a fifth ferroelectric capacitor connected to the fifth transistor, the second redundant reference cell for holding a potential corresponding to predetermined data; 
     a first switching circuit connected between the second bit line and the third bit line for electrically connecting the second bit line to the third bit line in response to a first control signal and generating a first reference potential in the second bit line and the third bit line; 
     an ordinary array having a first data read-out circuit that is activated by a first activating signal and connected to any one of the second bit line or third bit line and to the first bit line for comparing the first reference potential with a potential generated in the first bit line; 
     a fourth bit line; 
     a second memory cell formed of a sixth transistor connected to the fourth bit line and a sixth ferroelectric capacitor connected to the sixth transistor; 
     a fifth bit line; 
     a third reference cell formed of a seventh transistor connected to the fifth bit line and to the first word line to be controlled and a seventh ferroelectric capacitor connected to the seventh transistor, the third reference cell for holding a potential corresponding to predetermined data; 
     a sixth bit line; 
     a fourth reference cell formed of an eighth transistor connected to the sixth bit line and to the first word line to be controlled and an eighth ferroelectric capacitor connected to the eighth transistor, the fourth reference cell for holding a potential corresponding to predetermined data; 
     a third redundant reference cell formed of a ninth transistor connected to the fifth bit line and to the second word line to be controlled and a ninth ferroelectric capacitor connected to the ninth transistor, the third redundant reference cell for holding a potential corresponding to predetermined data; 
     a fourth redundant reference cell formed of a tenth transistor connected to the sixth bit line and to the second word line to be controlled and a tenth ferroelectric capacitor connected to the tenth transistor, the fourth redundant reference cell for holding a potential corresponding to predetermined data; 
     a second switching circuit connected between the fifth bit line and the sixth bit line for electrically connecting the fifth bit line to the sixth bit line in response to the first control signal and generating a second reference potential in the fifth bit line and the sixth bit line; 
     a redundant array having a second data read-out circuit that is activated by a second activating signal and connected to any one of the fifth bit line and the sixth bit line and to the fourth bit line for comparing the second reference potential with a potential generated in the fourth bit line; and 
     a word line select circuit for selecting any one of the first word line and the second word line, generating the reference potential in the second bit line and the third bit line by the first and second redundant reference cells by selecting the second word line when the first or second reference cell is defective, and generating the reference potential in the fifth bit line and the sixth bit line by the third and fourth redundant reference cells by selecting the second word line when the third or fourth reference cell is defective. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: 
         FIG. 1  is a diagram illustrating the essential part of a semiconductor memory device of a first embodiment according to the invention; 
         FIG. 2  is a block diagram illustrating the configuration of a memory cell array of the semiconductor memory device of the first embodiment according to the invention; 
         FIG. 3  is a circuit diagram illustrating the essential part of the semiconductor memory device and a circuit diagram illustrating a reference word line control circuit of the first embodiment according to the invention; 
         FIG. 4  is a distribution diagram illustrating the potential of the bit line when data is read out of each of the memory cells in the semiconductor memory device of the first embodiment according to the invention; 
         FIG. 5  is a circuit diagram illustrating the essential part of a semiconductor memory device and a circuit diagram illustrating a reference word line control circuit of a second embodiment according to the invention; 
         FIG. 6  is a circuit diagram illustrating the essential part of the semiconductor memory device and a circuit diagram illustrating another reference word line control circuit of the second embodiment according to the invention; and 
         FIG. 7  is a circuit diagram illustrating the essential part of the traditional semiconductor memory device. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Hereafter, a first embodiment according to the invention will be described in detail with reference to the drawings. 
       FIG. 1  depicts a reference potential generation circuit and a part of its peripheral circuit in a semiconductor memory device of a first embodiment. 
     In addition to the reference potential generation circuit shown in  FIG. 1 , the semiconductor memory device of the first embodiment is configured of the peripheral circuit formed of a reference word line control circuit for generating control signals of the reference potential generation circuit, memory cells MC 0  to MC 3  disposed at the intersections of bit lines BL and complementary bit lines BLb with word lines WL 0  and WL 1  for storing data, and a sense amplifier circuit SA (data read-out circuit) connected between the bit line BL to which any one of the memory cells MC 0  to MC 3  is connected and the complementary bit line BLb to which the corresponding reference cell is connected, the sense amplifier circuit SA compares the potential generated in each of the bit lines BL and the complementary bit lines BLb and amplifies signals of the memory cells. 
     In the reference potential generation circuit of the first embodiment, the bit lines BL and the complementary bit lines BLb to which the memory cells are connected, both to be paired, reference word lines RWL, and reference plate lines RPL are provided. At the intersection of each of the bit lines and the reference word lines, reference cells RMC 10  to RMC 13  and RMC 20  to RMC 23  are disposed. 
     Among the reference cells RMC 10  to RMC 13 , the reference cells RMC 10  and RMC 12  are connected to the bit lines BL, which are configured of select transistors RT 10  and RT 12  operated by the reference word line RWL 10  and ferroelectric capacitors H 10  and H 12  that one terminals are connected to the select transistors RT 10  and RT 12  and the others are connected to a reference plate line RPL 1 . In addition, the reference cells RMC 11  and RMC 13  are connected to the complementary bit lines BLb, which are configured of select transistors RT 11  and RT 13  operated by a reference word line RWL 11  and ferroelectric capacitors H 11  and H 13  that one terminals are connected to the select transistors RT 11  and RT 13  and the others are connected to the reference plate line RPL 1 . 
     A reference cell pair  110  is configured of the reference cells RMC 10  to RMC 13 . 
     Furthermore, in the semiconductor memory device of the first embodiment, redundant reference cells RMC 20  to RMC 23  are provided for the bit line pairs to be paired. The redundant reference cell is the reference cell that is connected to the same bit line pair other than the reference cells RMC 10  to RMC 13  for generating the reference potential in general. For example, it is the cell that is used when any one of the reference cells RMC 10  to RMC 13  is a defective cell and generates the correct reference potential in a desired bit line. Among the redundant reference cells RMC 20  to RMC 23 , the reference cells RMC 20  and RMC 22  are connected to the bit lines BL, which are configured of select transistors RT 20  and RT 22  operated by a reference word line RWL 20  and ferroelectric capacitors H 20  and H 22  that one terminals are connected to the select transistors RT 20  and RT 22  and the others are connected to a reference plate line RPL 2 . In addition, the reference cells RMC 21  and RMC 23  are connected to the complementary bit lines BLb, which are configured of select transistors RT 21  and RT 23  operated by a reference word line RWL 21  and ferroelectric capacitors H 21  and H 23  that one terminals are connected to the select transistors RT 21  and RT 23  and the others are connected to the reference plate line RPL 2 . 
     A reference cell pair  120  is configured of the reference cells RMC 20  to RMC 23 . 
     More specifically, it is configured to provide two or more, a plurality of the reference cell pairs  110  and  120  are provided for a single bit line pair (BL 0  and BLb 0 , BL 1  and BLb 1 ). 
     Furthermore, a switching transistor T 0  is connected between the two bit lines BL to which the reference cells RMC 10 , RMC 12 , RMC 20  and RMC 22  are connected, and a switching transistor T 1  is connected between the two complementary bit lines BLb to which the reference cells RMC 11 , RMC 13 , RMC 21  and RMC 23  are connected. The switching transistors T 0  and T 1  are operated by a bit line equalizer signal EQ 0  or EQ 1 , which generate the reference potential used in data readout of the memory cells by short-circuiting between two bit lines connected to the switching transistors T 0  and T 1 . 
     Next, the readout operation of the semiconductor memory device in the embodiment will be described. For example, in the case of reading data out of the memory cells MC 10 , MC 12 , MC 20 , MC 22  and so on, which are connected to the BL 0  and BL 1 , when defective conditions occur in the reference cell RMC 11  of the reference cell pair  110  due to process variations, the RMC 21  and RMC 23  similarly connected to the BLb 0  and BLb 1  and disposed in the reference cell pair  120  are used to generate the reference potential in the BLb 0  and BLb 1  instead that the RMC 11  and RMC 13  are used as the reference memory cells to generate the reference potential in the BLb 0  and BLb 1 . More specifically, instead of the reference word line RWL 11  and the reference plate line RPL 1  of the reference cell pair  110 , the reference word line RWL 21  and the reference plate line RPL 2  are turned to an active state, the reference cells RMC 21  and RMC 23  disposed in the reference cell pair  120  with no defective conditions are used to generate the correct reference potential in the BLb 0  and BLb 1 . After that, data is read out of the memory cells MC 10 , MC 12 , MC 20 , MC 22  and so on by the same method as that of the traditional semiconductor memory device. 
     In the semiconductor memory device of the first embodiment described above, a plurality of the reference cell pairs is provided for a single bit line pair. Thus, in the case where the reference cell under defective conditions is included, another reference cell pair can be selected from the plurality of the reference cell pairs, and the malfunction of the normal memory cell with the defective conditions of a single reference memory cell such as the malfunction that Data  1  is outputted in spite of the fact that Data  0  is held can be avoided. Consequently, the yields of a memory cell array can be improved. 
     In addition, as shown in  FIG. 2 , it is acceptable that a memory cell array  20  of the semiconductor memory device in the first embodiment is configured to have memory cell blocks MCB 0 , MCB 1  to MCBn having memory cells MC 10 , MC 11  to MCj 0  and MCj 1  formed of ferroelectric capacitors and select transistors, not shown; a reference block RB 10  formed of a reference memory cell RMC 10  connected to a bit line BL 0  and a reference memory cell RMC 11  connected to a complementary bit line BLb 0 ; memory cell blocks MCB 0  and MCB 1 ; reference blocks RB; switching transistors T 0  and T 1  for short-circuiting the adjacent bit line BL or complementary bit line BLb in order to generate the reference potential; column redundant memory cell blocks CMCB 0  and CMCB 1  formed of ferroelectric capacitors and select transistors, not shown; column redundant reference blocks CRB connected to a redundant bit line RBL 0  and a complementary redundant bit line RBLb 0 ; and redundant switching transistors RT 0  and RT 1  for short-circuiting the adjacent bit line BL or complementary bit line BLb in order to generate the reference potential by a column redundant array. 
     The semiconductor memory device shown in  FIG. 2  further has a replacement unit formed of the bit lines BL, the complementary bit lines BLb, the memory cell blocks MCB, the reference blocks RB, and the switching transistors T 0  and T 1 , and a single memory cell array is configured of an ordinary array formed of a plurality of replacement units  210  to  21   m  and the column redundant array formed of the redundant bit lines RBL, the complementary redundant bit lines RBLb, the column redundant memory cell blocks CMCB, the column redundant reference blocks CRB and the switching transistors RT 0  and RT 1 . 
     In this manner, a column redundant array  21  disposed in the memory cell array  20  is also configured in which a plurality of the column redundant reference blocks (CRB 10  and CRB 12 , CRB 20  and CRB 22 ), that is, a plurality of the reference cell pairs is provided for a single bit line pair (RBL 0  and RBLb 0 , RBL 1  and RBLb 1 ). Therefore, for example, in the case where defective conditions exist in many places such as in the memory cell block MCB 0  and in a reference block RB 12 , the replacement unit  210  having the memory cell block MCB 0  with defective conditions is repaired by the column redundant array  21 , and the reference block RB 12  is repaired by a reference block RB 22  connected to the same bit line to which the RB 12  is connected instead of the RB 12 . 
     More specifically, data of the memory cell block MCB 0  is correctly outputted to the bit line by the column redundant array  21 , and the correct reference potential generated in the reference block RB 22  is outputted to the bit line in the replacement unit  211 . Particularly, since a desired potential (Data  0  or Data  1 ) is outputted to a bit line BL 2  and a complementary bit line BLb 2  in the reference block RB 22 , the correct reference potential is generated in a bit line BL 3  or complementary bit line BLb 3  to be paired with the bit line BL 2  or complementary bit line BLb 2  in generating the reference potential. Thus, the entire memory cells MC in the memory cell blocks MCB 2  and MCB 3  connected to the bit lines BL 2  and BL 3  and the complementary bit lines BLb 2  and BLb 3  can be operated correctly. 
     In addition to this, in the semiconductor memory device shown in  FIG. 2 , a plurality of the reference blocks RB is provided for each of the bit line pairs of the plurality of the replacement units  210 ,  211  to  21   m  forming the ordinary array. On this account, even though defective conditions further occur in a reference block RB 1   n , a reference block RB 2   n  is used instead of the reference block RB 1   n,  and then the memory cells in memory cell blocks MCB(n−1) and MCBn can be operated correctly. 
     More specifically, according to the semiconductor memory device shown in  FIG. 2  having a plurality of the reference pairs provided for the bit line pairs in each of the replacement units and the column redundant array, the memory cell array  20  can be repaired even though a large number of defective cells are generated, and the yields of the memory cell array can be further improved. 
     Furthermore, as shown in  FIG. 3 , for the semiconductor memory device of the first embodiment having the plurality of the reference pairs provided for a single bit line pair, a reference word line control circuit  300  can be provided which creates reference cell select signals for selecting a reference cell to generate the reference potential based on external input signals TM 0 , TM 1  and TM 2  such as test mode signals to set a test mode. 
     The reference word line control circuit  300  shown in  FIG. 3  is configured to provide three reference cell pairs  110 ,  120  and  130  for a single bit line pair. Reference word line enable signals RWL 0 EN and RWL 1 EN and the external input signals TM 0  to TM 2  are inputted to the reference word line control circuit  300 , which has a first AND circuit  301  to which the external input signals TM 0  to TM 2  and the inverted signals of each of the external input signals are inputted and a second AND circuit  302  to which the reference word line enable signals RWL 0 EN and RWL 1 EN and the output of the first AND circuit  301  are inputted. 
     The reference word line enable signals RWL 0 EN and RWL 1 EN inputted to the second AND circuit  302  are the signals that activate any one of a plurality of the reference word lines RWL (RWL 10  or RWL 11 , RWL 20  or RWL 21 , RWL 30  or RWL 31 ) in each of the reference cell pairs. 
     In the semiconductor memory device of the first embodiment, the use of the reference word line control circuit  300  having this configuration allows the desired reference word lines RWL 10 , RWL 11 , RWL 20 , RWL 21 , RWL 30  and RWL 31  to be selected and activated by the external input signals TM 0 , TM 1  and TM 2  and the reference word line enable signals RWL 0 EN and RML 1 EN from the outside of the semiconductor memory device. 
     Here, the change in the polarization property (hysteresis curve) of the ferroelectric capacitor forming a part of the memory cell and the reference memory cell will be described with FIG.  4 . 
     In the ferroelectric capacitor using a ferroelectric film such as a metal oxide film as a capacitive dielectric, the polarization property of each of the ferroelectric capacitors is varied because of process variations generated in the fabrication process of semiconductor devices such as the variation in the state of a fabrication apparatus for use. As the result, there are the distributions of ΔV 0  and ΔV 1 . 
       FIG. 4  depicts the distributions of ΔV 0  and ΔV 1  of the ferroelectric capacitors H 10 , H 20 , H 30 , H 12 , H 22  and H 32  included in the entire memory cells MC 10 , MC 20 , MC 30 , MC 12 , MC 22  and MC 32  connected to the bit lines BL 0  and BL 1 , the reference potential Vref  110  generated by the RMC 11  and RMC 13  disposed in the reference cell pair  110 , the reference potential Vref  120  generated by the RMC 21  and RMC 23  disposed in the reference cell pair  120 , and the reference potential Vref  130  generated by the RMC 31  and RMC 33  disposed in the reference cell pair  130 . 
     Now, referring to a distribution diagram shown in  FIG. 4 , in the case where the reference potential Vref  110  generated by the reference cell pair  110  is used to read data out of the bit lines BL 0  and BL 1 , there is a portion  410  that the reference potential Vref  110  is overlapped with the distribution of the potential ΔV 0  supposed to correspond to Data  0 . More specifically, in the memory cell having the distribution of ΔV 0  in the portion  410  of the potential ΔV 0  supposed to correspond to Data  0  (the right side of the reference potential Vref  110 ), it is determined that the potential transferred to the corresponding bit line is higher than the potential Vref  110  even though the held data is Data  0 . Therefore, the error data of Data  1  is read out and outputted from the sense amplifier circuit SA. In addition, referring to the distribution diagram shown in  FIG. 4 , in the case where the reference potential Vref  130  generated by the reference cell pair  130  is similarly used to read data out of the bit lines BL 0  and BL 1 , there is a portion  420  that the reference potential Vref  130  is overlapped with the distribution of the potential ΔV 1  supposed to correspond to Data  1 . More specifically, in the memory cell having the distribution of ΔV 1  in the portion  420  of the potential ΔV 1  supposed to correspond to Data  1  (the left side more than the reference potential Vref  130 ), it is determined that the potential transferred to the corresponding bit line is lower than the reference potential Vref  130  even though the held data is Data  1 . Therefore, the error data of Data  0  is read out and outputted from the sense amplifier circuit SA. 
     Correspondingly, referring to the distribution diagram shown in  FIG. 4 , in the case where the reference potential Vref  120  generated by the reference cell pair  120  is used to read data out of the bit lines BL 0  and BL 1 , there is no portion that is overlapped with the reference potential Vref  120  in the distributions of ΔV 0  and ΔV 1 . Therefore, data is correctly read out of the entire memory cells, and incorrect data readout can be prevented. 
     As described above, in data readout of the memory cell showing the distributions in  FIG. 4 , it is apparent that it is desirable to select the most suitable reference cell pair  120  when defective conditions do not occur in the reference cells forming each of the reference cell pairs  110 ,  120  and  130 . 
     In the reference word line control circuit  300  shown in  FIG. 3 , any one of the reference word line enable signals RWLOEN and RWL 1 EN is turned to high level, the other is turned to low level, the high level is inputted to the TM 0 , and the low level is inputted to the TM 1  and TM 2  among the external input signals TM 0  to TM 2 . Thus, the reference cell pair  120  to generate the most suitable potential Vref  120  can be selected. 
     Furthermore, when the reference word line control circuit  300  shown in  FIG. 3  is adapted which has the configuration allowing a desired reference cell pair to be selected by the external input signals, the most suitable reference cell pair can be selected by the following method in actual semiconductor devices as well. 
     Hereafter, a method for selecting the most suitable reference cell pair will be described in the case of using the reference word line control circuit shown in FIG.  3 . 
     First, the input signals TM 0 , TM 1 , TM 2  and so on to be externally inputted to the reference word line control circuit  300  are all turned to low level (hereafter, it is denoted by L). In this case, the reference cell pair  110  is selected, and the reference potential used in data readout of the memory cell is the Vref  110 . When the readout test from the memory cell is performed in this state, the number of defective memory cells included in the overlapped portion  410  shown in  FIG. 4  appears, and the defective cells appear in readout of Data  0 . Subsequently, the external input signal TM 0  is turned to high level (hereafter, it is denoted by H), and the other TM 1 , TM 2  and so on are turned to L. In this case, the reference cell pair  120  is selected, and the reference potential used in data readout of the memory cell is the Vref  120 . When the readout test of the memory cell is performed in this state, the defective cells do not appear in data readout of Data  0  and Data  1 , and the entire memory cells are accepted. Lastly, the external input signal TM 1  is turned to H, and the other TM 0 , TM 2  and so on are turned to L. In this case, the reference cell pair  130  is selected, and the reference potential used in data readout of the memory cell is the Vref  130 . When the readout test of the memory cell is performed in this state, the number of defective cells included in the overlapped portion  420  shown in  FIG. 4  appears, and the defective memory cells appear in readout of Data  1 . 
     In this manner, by disposing the reference word line control circuit  300  shown in  FIG. 3 , a single reference cell pair is selected among the plurality of the reference cell pairs by the external input signals TM 0 , TM 1 , TM 2  and so on, the readout test of the memory cell is performed in each of the reference cell pairs, and the most suitable reference cell pair can also be selected for the memory cell array of the actual semiconductor device. More specifically, in the semiconductor memory device with the ferroelectric capacitor of the embodiment which can select the most suitable reference cell pair, the malfunctions in data readout are reduced, and consequently a highly reliable semiconductor memory device can be provided. 
     In addition, according to the semiconductor memory device of the embodiment having the reference word line control circuit  300  in which a desired reference cell is selected from a plurality of the reference cells by the external input signals TM 0 , TM 1  and TM 2  inputted from the outside of the semiconductor memory device, the most suitable reference cell,pair can be determined in each of semiconductor devices by properly changing the external input signals at the testing stage before the shipment of products. Consequently, it is preferable that highly reliable products can be provided for a short time. 
     Furthermore, in the semiconductor memory device of the first embodiment, the sizes of the entire memory cells and the reference memory cells (the sizes of the ferroelectric capacitor and the transistor forming of each cell) are nearly the same size. The layout of the ordinary array and the column redundant array can be designed in the same layout by this configuration. Therefore, variations in the exposure and etching processes of the peripheral part are reduced, and the semiconductor memory device can be provided at high yields. 
     In addition to this, according to the semiconductor memory device of the first embodiment in which the most suitable reference cell pair can be selected by the external input signals among the plurality of the reference cell pairs provided for the bit line pair, the most suitable reference cell pair can again be selected for a desired memory cell after the process step of easily performing imprint that changes the polarization property of the ferroelectric film forming the semiconductor memory device, such as the annealing process included in the fabrication process steps of the semiconductor device. Consequently, the reference potential can be selected in consideration of imprint of the ferroelectric film being the capacitive dielectric of the ferroelectric capacitor, and the reliability of the semiconductor device can be further improved. 
     Next, a second embodiment according to the invention will be described. 
       FIG. 5  depicts a reference potential generation circuit and a reference word line control circuit in a semiconductor memory device of the second embodiment. In addition, the same reference numerals and signs as those shown in the first embodiment are the same component or corresponding part. 
     As similar to the first embodiment described before, the semiconductor memory device of the second embodiment is configured to have a reference potential generation circuit formed of reference memory cells RMC 10  to RMC 13 , RMC 20  to RMC 23 , and RMC 30  to RMC 33  disposed at the intersections of bit lines BL and complementary bit lines BLb with reference word lines RWL 10 , RWL 11 , RWL 20 , RWL 21 , RWL 30  and RWL 31 ; memory cells MC 10  to MC 13  and MC 20  to MC 23  connected to the reference potential generation circuit through the bit lines BL and the complementary bit lines BLb and disposed at the intersections of word lines WL 10  and WL 11  for storing data; sense amplifier circuits SA connected between the bit lines BL and the complementary bit line BLb for amplifying signals of the memory cells; and a reference word line control circuit that receives a block select signal BLKSEL and reference word line enable signals RWL 0 EN and RWL 1 EN to output a select signal for selecting a single reference cell pair among a plurality of reference cell pairs. 
     The data readout and write operation of the memory cell in the semiconductor memory device of the second embodiment is the same as that of the traditional semiconductor memory device. 
     However, in the case of the second embodiment, the reference word line control circuit has logic fuses in which a desired reference cell pair is selected depending on the state of the fuses to be cut or uncut. More specifically, according to the configuration of the reference word line control circuit in the second embodiment, the select signal for selecting the reference cell pair can be generated from a signal internally created for use such as the block select signal BLKSEL, not from the external input signals. 
     To the reference word line control circuit of the second embodiment, the reference word line enable signals RWL 0 EN and RWL 1 EN and the block select signal BLKSEL are inputted, the reference word line enable signals RWL 0 EN and RWL 1 EN are the signals that activate any one of a plurality of the reference word lines RWL (RWL 10  or RWL 11 , RWL 20  or RWL 21 , RWL 30  or RWL 31 ) in each of the reference cell pairs and select whether to generate the reference potential in bit lines BL 0 , BL 1  and so on or in complementary bit lines BLb 0 , BLb 1  and so on, and the block select signal BLKSEL is the signal that selects a desired block to operate among a plurality of blocks in a semiconductor device, for example. The reference word lines RWL 10 , RWL 11  and so on for the reference cell pairs are selected and controlled by fuses  510  and  520  that have been cut by laser beam irradiation beforehand. 
     As similar to the reference word line control circuit of the first embodiment described before, a reference word line control circuit  500  shown in  FIG. 5  is also configured to provide three reference cell pairs  110 ,  120  and  130  for a single bit line pair connected to the reference word line control circuit  500 . 
     The reference word line control circuit  500  has reference word line enable signal lines RWLENL to which the reference word line enable signals RWL 0 EN and RWL 1 EN are inputted; a block select signal line BSEL to which the block select signal BLKSEL is inputted that is internally created and used in a semiconductor device, changing from L to H to L, for example; fuses  510  and  520  disposed between the reference word line enable signal lines RWLENL and the block select signal line BSEL, to which the inverted signal of the block select signal BLKSEL is inputted; and a select circuit  501  having switching transistors T 2  and T 4  connected to the output side of the fuses  510  and  520  to be controlled by the block select signal BLKSEL and switching transistors T 3  and T 5  similarly connected to the output side of the fuses  510  and  520  to be controlled by the inverted signals of the output signals of the fuses  510  and  520 . 
     The reference word line enable signals RWL 0 EN and RWL 1 EN and the block select signal BLKSEL internally used are inputted to the reference word line control circuit  500  of the second embodiment shown in  FIG. 5 , which has a first AND circuit  502  inputted with the output of the select circuit  501  to which the block select signal BLKSEL has been inputted and a second AND circuit  503  inputted with the reference word line enable signals RWL 0 EN and RWL 1  EN and the output of the first AND circuit  502 . 
     Hereafter, a method for selecting a reference cell pair  120  will be described by the reference word line control circuit shown in FIG.  5 . 
     In addition, Data  0  is written into the reference cell RMC 23  and Data  1  is written into the reference cell RMC 21  beforehand, and the fuse  510  connected to the transistors T 4  and T 5  is cut by laser beam irradiation. 
     First, the block select signal BLKSEL is turned to H, the RSEL 120  is turned to H among the reference cell pair select signals RSEL 110 , RSEL 120  and RSEL 130 , and the other RSEL 110  and RSEL 130  are turned to L. Subsequently, a reference plate line RPL 2  and the reference word line enable signal RWL 1 EN are turned to H, and the reference word line RWL 21  is turned to H. 
     Thus, data of the reference cell RMC 23  into which Data  0  has been written is transferred to the complementary bit line BLb 1 , the potential of the BLb 1  is turned to ΔV 0 , data of the reference cell RMC 21  into which Data  1  has been written is transferred to the complementary bit line BLb 0 , and the potential of the BLb 0  is turned to ΔV 1 . 
     After that, the bit line equalizer signal EQ 1  is turned to H, and the switching transistor T 1  is turned to an ON state to short-circuit between the complementary bit lines BLb 0  and BLb 1 . Thus, the reference potential Vref  120  having been generated by the reference cell pair  120  including the reference cells RMC 21  and RMC 23  is generated in the complementary bit line BLb 0  and BLb 1 . 
     According to the semiconductor memory device of the second embodiment in which the block select signal BLKSEL internally generated is used to create the select signal for the reference cell pair, the reference cell pair for use can be determined based on the state of the fuses (cut/uncut) without externally inputting a specific signal. Consequently, the number of terminals of a semiconductor device disposed outside can be reduced. 
     In addition, in the embodiment, the method that the fuse  510  is cut to generate the reference potential Vref  120  in the bit line BLb is exemplified for description. However, any fuse is not cut when the reference potential Vref  110  is generated, whereas the fuse  520  is cut by laser beam and then the reference potential is generated by the method described above when the reference potential Vref  130  is generated. Accordingly, a desired level of the reference potential can be generated properly. 
     Furthermore, as similar to the first embodiment described before, the semiconductor memory device of the second embodiment can also adopt the memory cell array configuration configured of the ordinary array formed of the plurality of the replacement units  210  to  21   m  and the column redundant array  21 , and can form the configuration of providing a plurality of the reference cell pairs for each of the replacement units and each of the bit line pairs of the column redundant array. 
     Moreover, in the semiconductor memory device of the second embodiment, in the case where the array block configuration is adapted which has a plurality of the memory cell arrays formed of the plurality of the replacement units and the column redundant array, it can be replaced by a reference word line control circuit shown in  FIG. 6  having fuses  611  to  614  and  621  to  624  connected in parallel between reference word line enable signal lines RWLENL and a block select signal line BSEL, the fuses can be cut by laser beam, and switching transistors T 11  to T 14  and T 21  to T 24  serially connected to each of the fuses to be controlled by array select signals ARYSEL. 
     For example, in the case of selecting a reference cell pair  120  in an array  60 , a reference cell pair  130  in an array  61 , a reference cell pair  110  in an array  62 , and the reference cell pair  120  in an array  63 , the fuses  611 ,  622  and  614  of the reference word line control circuit shown in  FIG. 6  are cut beforehand. After that, in the case of selecting the array  60  in an array block  601  by an address externally inputted, an array select signal ARYSEL  60  for selecting the array  60  is turned to H. At this time, the other array select signals ARYSEL are L. Thus, a reference cell pair select signal RSEL 120  is turned to an active state to activate reference word lines RWL 21  and RWL 22 , and the reference cell pair  120  is selected. Similarly, in the case of selecting the array  61 , an array select signal ARYSEL 61  for selecting the array  61  is turned to H. Thus, the reference cell pair select signal RSEL 130  is turned to an active state to activate reference word lines RWL 31  and RWL 32 , and the reference cell pair  130  is selected. Furthermore, an array select signal ARYSEL 62  is turned to H and a reference cell pair select signal RSEL 110  is turned to an active state when selecting the array  62 , whereas a reference cell pair select signal RSEL  120  is turned to an active state when selecting the array  63 . Accordingly, a desired reference cell pair can be selected at each array. 
     In this manner, according to the semiconductor memory device adopting the reference word line control circuit shown in  FIG. 6 , the use of the array select signals ARYSEL and the fuses  611  to  614  and  621  to  624  can select the most suitable reference cell pair for each of the array  60  to  63  forming the array block. 
     More specifically, since a response can properly be given to the variation of the polarization property (the difference in the hysteresis curves) of the ferroelectric film forming the memory cells caused by process variations in the memory cell part area, a more highly reliable semiconductor memory device can be provided. 
     Moreover, in the semiconductor memory device of the first and second embodiments, the configuration of providing two or three reference cell pairs for a single bit line pair is exemplified for description. However, in the invention, the number of the reference cell pairs provided for a single bit line pair is not limited to this. Desirably, a large number of reference cell pairs are provided for a single bit line pair when the number is plurals. 
     As described above, according to the invention having the reference potential generation circuit that provides a plurality of the reference cell pairs for a single bit line pair and the reference word line control circuit that selects the most suitable reference cell pair among a plurality of the reference cell pairs, even though a reference cell under defective conditions is included, another reference cell pair can be selected from the plurality of the reference cell pairs. Accordingly, the malfunctions of normal memory cells with the defective conditions of a single reference memory cell can be avoided. More specifically, the yields of the memory cell array can be improved. 
     In addition, according to the semiconductor memory device of the invention having the reference word line control circuit that can select the most suitable reference cell pair, the reference cell pair to generate the reference potential suitable for each of the memory cells is selected by the reference word line control circuit, and thus the malfunctions in data readout are reduced. Consequently, a highly reliable semiconductor memory device can be provided.