Patent Publication Number: US-2022238452-A1

Title: Method for preparing semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing linling layer

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional application of U.S. Non-Provisional application Ser. No. 17/097,876 filed Nov. 13, 2020, which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to a method for preparing a semiconductor device structure, and more particularly, to a method for preparing a semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing lining layer. 
     DISCUSSION OF THE BACKGROUND 
     Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while providing greater functionality and including greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, various types and dimensions of semiconductor devices providing different functionalities are integrated and packaged into a single module. Furthermore, numerous manufacturing operations are implemented for integration of various types of semiconductor devices. 
     However, the manufacturing and integration of semiconductor devices involve many complicated steps and operations. Integration in semiconductor devices becomes increasingly complicated. An increase in complexity of manufacturing and integration of the semiconductor device may cause deficiencies, such as void formed in conductive structure, which results from the difficulties in filling a high aspect ratio opening. Accordingly, there is a continuous need to improve the manufacturing process of semiconductor devices so that the problems can be addressed. 
     This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure. 
     SUMMARY 
     In one embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure comprises a substrate having a pattern-dense region and a pattern-loose region; a first conductive layer disposed over the substrate; a first dielectric layer disposed over the first conductive layer; a first conductive plug and a second conductive plug disposed in the first dielectric layer; wherein the first conductive plug and the second conductive plug comprises copper (Cu) and are separated from the first dielectric layer by the a first lining layer comprising manganese (Mn); wherein the first conductive plug and the second conductive plug have different aspect ratios. 
     In some embodiments, the semiconductor device structure further comprises a second conductive layer disposed over the first conductive layer, wherein the first conductive layer and the second conductive layer comprise copper (Cu), and the first conductive plug electrically connects the first conductive layer to the second conductive layer. 
     In some embodiments, the first lining layer comprises copper-manganese-silicon (CuMnSi). 
     In some embodiments, a width of the second conductive plug is greater than a width of the first conductive plug, and a height of the second conductive plug is greater than a height of the first conductive plug. 
     In some embodiments, the substrate comprises: a first lower conductive layer disposed below a semiconductor substrate; a second lower conductive layer disposed below the first conductive layer; a first lower conductive plug disposed between and electrically connecting the first lower conductive layer and the second lower conductive layer, wherein the first lower conductive plug comprises copper (Cu); and a first lower lining layer surrounding the first lower conductive plug, wherein the first lower lining layer comprises manganese (Mn). 
     In some embodiments, the semiconductor device structure further comprises a first lower dielectric layer surrounding the first lower lining layer, and an air gap between the first lower lining layer and the first lower dielectric layer. 
     In some embodiments, the first lining layer comprises: a first sub-lining layer disposed over and directly contacting the first conductive layer, wherein the first sub-lining layer comprises manganese silicon (MnSi); and a second sub-lining layer disposed over the first sub-lining layer, wherein the second sub-lining layer comprises manganese (Mn). 
     In some embodiments, the second lining layer comprises copper-manganese-silicon (CuMnSi). 
     In another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method comprises: preparing a substrate having a pattern-dense region and a pattern-loose region; forming a first conductive layer disposed over the substrate; forming a first dielectric layer disposed over the first conductive layer; etching the first dielectric layer to form a first opening and a second opening exposing the first conductive layer, wherein the first opening and the second opening have different aspect ratios; forming a first lining layer and a first conductive plug in the first opening and a second conductive plug in the second opening, wherein the first lining layer comprises manganese (Mn), the first conductive plug comprises copper (Cu), and the first conductive plug and the second plug are surrounded by the first lining layer; and forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer, wherein the second conductive layer comprises copper (Cu). 
     In some embodiments, preparing a substrate comprises: forming a first lower conductive layer over a semiconductor substrate, wherein the first lower conductive layer comprises copper (Cu); forming a first lower dielectric layer over the first conductive layer; etching the first lower dielectric layer to form a first lower opening exposing the first conductive layer; forming a first lower lining layer and a first lower conductive plug in the first lower opening, wherein the first lower lining layer comprises manganese (Mn), the first lower conductive plug comprises copper (Cu), and the first lower conductive plug is surrounded by the first lower lining layer; and forming a second lower conductive layer over the first lower dielectric layer, the first lower lining layer and the first lower conductive layer, wherein the second lower conductive layer comprises copper (Cu). 
     In some embodiments, the method for preparing a semiconductor device structure further comprises: forming an energy removable layer lining the first lower opening before the first lower lining layer and the first lower conductive plug are formed, wherein the first lower conductive layer is partially exposed after the energy removable layer is formed. 
     In some embodiments, the method for preparing a semiconductor device structure further comprises: performing a heat treatment process to transform the energy removable layer into an air gap after the second lower conductive layer is formed. 
     In some embodiments, the method for preparing a semiconductor device structure further comprises: forming a second lower dielectric layer over the second lower conductive layer; etching the second lower dielectric layer to form a second lower opening exposing the second lower conductive layer; forming a second lower lining layer and a second lower conductive plug in the second opening, wherein the second lower conductive plug is surrounded by the second lower lining layer, the second lower lining layer comprises manganese (Mn), and the second lower conductive plug comprises copper (Cu). 
     In some embodiments, the first lower conductive plug and the second lower conductive plug each further comprise tungsten (W). 
     In some embodiments, the third lower conductive layer is separated from the second lower dielectric layer by the second lower lining layer, and a portion of the second lower lining layer is sandwiched between the second lower conductive plug and the second lower conductive layer. 
     In some embodiments, forming the second lower lining layer comprises: forming a first sub-lining layer over a top surface of the second dielectric layer, wherein sidewalls and a bottom surface of the second lower opening are covered by the first sub-lining layer, and wherein the first sub-lining layer comprises manganese silicon (MnSi); forming a second sub-lining layer over the first sub-lining layer, wherein the second sub-lining layer comprises manganese (Mn); and forming a third sub-lining layer over the second sub-lining layer, wherein the third sub-lining layer comprises copper manganese (CuMn). 
     In some embodiments, a width of the second opening is greater than a width of the first opening. 
     In some embodiments, a height of the second opening is greater than a height of the first opening. 
     In some embodiments, a height of the second conductive plug is greater than a height of the first conductive plug. 
     In some embodiments, a width of the second conductive plug is greater than a width of the first conductive plug. 
     Embodiments of a semiconductor device structure are provided in the disclosure. In some embodiments, the semiconductor device structure includes a conductive plug disposed between and electrically connecting two conductive layers disposed in the vertical direction, and a lining layer surrounding the conductive plug. The conductive plug includes copper, and the lining layer includes manganese. The manganese-containing lining layer is configured to reduce or prevent voids from forming in the conductive plug, thereby decreasing the contact resistance of the conductive plug. As a result, the operation speed of the semiconductor device structure may be increased, which significantly improves the overall device performance. 
     The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a cross-sectional view illustrating a semiconductor device structure, in accordance with some embodiments. 
         FIG. 2  is a cross-sectional view illustrating a modified semiconductor device structure, in accordance with some embodiments. 
         FIG. 3  is a cross-sectional view illustrating a modified semiconductor device structure, in accordance with some embodiments. 
         FIG. 4  is a cross-sectional view illustrating a modified semiconductor device structure, in accordance with some embodiments. 
         FIG. 5  is a flow diagram illustrating a method for preparing a semiconductor device structure, in accordance with some embodiments. 
         FIG. 6  is a cross-sectional view illustrating an intermediate stage of sequentially forming a first conductive layer and a first dielectric layer over a semiconductor substrate during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 7  is a cross-sectional view illustrating an intermediate stage of etching the first dielectric layer to expose a portion of the first conductive layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 8  is a cross-sectional view illustrating an intermediate stage of forming an energy removable material over the first dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 9  is a cross-sectional view illustrating an intermediate stage of etching the energy removable material to form an energy removable layer in the first dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 10  is a cross-sectional view illustrating an intermediate stage of forming a lining material over the energy removable layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 11  is a cross-sectional view illustrating an intermediate stage of etching the lining material to form a lining layer in the first dielectric layer and surrounded by the energy removable layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 12  is a cross-sectional view illustrating an intermediate stage of forming a conductive plug in the first dielectric layer and surrounded by the lining layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 13  is a cross-sectional view illustrating an intermediate stage of forming a second conductive layer over the first dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 14  is a cross-sectional view illustrating an intermediate stage of forming a second dielectric layer with an opening exposing the second conductive layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 15  is a cross-sectional view illustrating an intermediate stage of forming a lining layer over the second dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 16  is a cross-sectional view illustrating an intermediate stage of forming a conductive plug in the second dielectric layer and surrounded by the lining layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 17  is a cross-sectional view illustrating an intermediate stage of forming a third conductive layer over the second dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 18  is a cross-sectional view illustrating an intermediate stage of forming a lining layer over the second dielectric layer during the formation of a modified semiconductor device structure, in accordance with some embodiments. 
         FIG. 19  is a cross-sectional view illustrating a semiconductor device structure having a pattern-dense region and a pattern-loose region, in accordance with some embodiments. 
         FIG. 20  is a flow diagram illustrating a method for preparing a semiconductor device structure having a pattern-dense region and a pattern-loose region, in accordance with some embodiments. 
         FIG. 21  is a cross-sectional view illustrating an intermediate stage of sequentially forming a first conductive layer and a first dielectric layer with first openings over a semiconductor substrate during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 22  is a cross-sectional view illustrating an intermediate stage of forming an energy removable layer in the first opening of the pattern-dense region during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 23  is a cross-sectional view illustrating an intermediate stage of forming lining layers in the first openings during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 24  is a cross-sectional view illustrating an intermediate stage of forming conductive plugs in the first openings and forming a second conductive layer over the first dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 25  is a cross-sectional view illustrating an intermediate stage of forming a second dielectric layer with second openings over the second conductive layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 26  is a cross-sectional view illustrating an intermediate stage of forming lining layers in the second openings during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 27  is a cross-sectional view illustrating an intermediate stage of forming conductive plugs in the second openings and forming a third conductive layer over the second dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments. 
         FIG. 28  is a partial schematic illustration of an exemplary integrated circuit, including an array of memory cells in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
       FIG. 1  is a cross-sectional view illustrating a semiconductor device structure  100   a , in accordance with some embodiments. The semiconductor device structure  100   a  includes a first conductive layer  103  disposed over a semiconductor substrate  101 , a first dielectric layer  105  disposed over the first conductive layer  103 , a second conductive layer  143  disposed over the first dielectric layer  105 , a second dielectric layer  145  disposed over the second conductive layer  143 , and a third conductive layer  173  disposed over the second dielectric layer  145 , as shown in  FIG. 1  in accordance with some embodiments. 
     The semiconductor device structure  100   a  also includes a lining layer  123 ′ and a conductive plug  133  disposed in the first dielectric layer  105 . In some embodiments, the conductive plug  133  is surrounded by the lining layer  123 ′, and the lining layer  123 ′ is surrounded by the first dielectric layer  105 . It should be noted that the first conductive layer  103  is electrically connected to the second conductive layer  143  by the conductive plug  133 . 
     Moreover, the semiconductor device structure  100   a  includes an energy removable structure  113 ′ disposed in the first dielectric layer  105  and between the lining layer  123 ′ and the first dielectric layer  105 . In some embodiments, an air gap  180  is enclosed by the energy removable structure  113 ′. In other words, the air gap  180  is disposed between the lining layer  123 ′ and the first dielectric layer  105 . In some embodiments, the lining layer  123 ′ is surrounded by the energy removable structure  113 ′ and the air gap  180 . In some other embodiments, the energy removable structure  113 ′ is not formed. In these cases, the lining layer  123 ′ is separated from the first dielectric layer  105  by the air gap  180 . 
     The semiconductor device structure  100   a  further includes a lining layer  153  and a conductive plug  163  disposed between the second conductive layer  143  and the third conductive layer  173 . In some embodiments, the conductive plug  163  is surrounded by the lining layer  153 . It should be noted that the second conductive layer  143  is electrically connected to the third conductive layer  173  by the conductive plug  163  and the lining layer  153 . 
     In some embodiments, the lining layer  153  is disposed between the second dielectric layer  145  and the third conductive layer  173 , extending between the conductive plug  163  and the second dielectric layer  145  and between the conductive plug  163  and the second conductive layer  143 . In some embodiments, the sidewalls and the bottom surface of the conductive plug  163  is covered by the lining layer  153 . In some embodiments, a portion of the lining layer  153  is sandwiched between the conductive plug  163  and the second conductive layer  143 . 
     In some embodiments, the lining layer  153  is a laminated multi-layer structure. As shown in  FIG. 1 , the lining layer  153  includes a first sub-lining layer  155 , a second sub-lining layer  157  disposed over the first sub-lining layer  155 , and a third sub-lining layer  159  disposed over the second sub-lining layer  157 , in accordance with some embodiments. In some embodiments, the first sub-lining layer  155  is in direct contact with the second conductive layer  143  and the second dielectric layer  145 . In some embodiments, the third sub-lining layer  159  is in direct contact with the conductive plug  163  and the third conductive layer  173 . 
     In some embodiments, the semiconductor device  100   a  is a dynamic random access memory (DRAM). In these cases, the conductive layers (including the first conductive layer  103 , the second conductive layer  143  and the third conductive layer  173 ) can serve as bit lines (BL), storage nodes and/or wiring layers for the DRAM, and the conductive plugs (including the conductive plugs  133  and  163 ) can serve as bit line contact plugs, capacitor contact plugs and/or interconnect structures for the DRAM. 
     In some embodiments, the first conductive layer  103 , the second conductive layer  143 , the third conductive layer  173 , and the conductive plugs  133  and  163  each include copper (Cu), and the lining layers  123 ′ and  153  each include manganese (Mn). In some other embodiments, the conductive plugs  133  and  163  each further include tungsten (W). In particular, the lining layers  123 ′ includes copper-manganese-silicon (CuMnSi), the first sub-lining layer  155  of the lining layer  153  includes manganese silicon (MnSi), the second sub-lining layer  157  of the lining layer  153  includes manganese (Mn), and the third sub-lining layer  159  of the lining layer  153  includes copper manganese (CuMn), in accordance with some embodiments. 
     The manganese-containing lining layers  123 ′ and  153  are configured to reduce or prevent voids from forming in the conductive plugs  133  and  163 , thereby decreasing the contact resistance of the conductive plugs  133  and  163 . As a result, the operation speed of the semiconductor device structure  100   a  may be increased, which significantly improves the overall device performance. 
       FIG. 2  is a cross-sectional view illustrating a modified semiconductor device structure  100   b , which is an alternative embodiment of the semiconductor device structure  100   a , in accordance with some embodiments. For reasons of consistency and clarity, similar components appearing in both  FIGS. 1 and 2  will be labeled the same. 
     Similar to the semiconductor device structure  100   a , the semiconductor device structure  100   b  includes the conductive plug  133  and the lining layer  123 ′ disposed in the first dielectric layer  105 , and the conductive plug  133  is surrounded by the lining layer  123 ′. A difference is that the energy removable structure  113 ″ and the air gap  180  are not formed in the first dielectric layer  105  of the semiconductor device structure  100   b . That is, the lining layer  123 ′ is in direct contact with the first dielectric layer  105 . 
     In addition, similar to the semiconductor device structure  100   a , the manganese-containing lining layers  123 ′ and  153  of the semiconductor device structure  100   b  are configured to reduce or prevent voids from forming in the conductive plugs  133  and  163 , thereby decreasing the contact resistance of the conductive plugs  133  and  163 . As a result, the operation speed of the semiconductor device structure  100   b  may be increased, which significantly improves the overall device performance. 
       FIG. 3  is a cross-sectional view illustrating a modified semiconductor device structure  200   a , which is an alternative embodiment of the semiconductor device structure  100   a , in accordance with some embodiments. For reasons of consistency and clarity, similar components appearing in both  FIGS. 1 and 3  will be labeled the same. 
     Similar to the semiconductor device structure  100   a , the semiconductor device structure  200   a  includes a lining layer  253  and the conductive plug  163  disposed between the second conductive layer  143  and the third conductive layer  173 . A difference is that the lining layer  253  of the semiconductor device structure  200   a  is a single layer. In some embodiments, the lining layer  253  includes copper-manganese-silicon (CuMnSi). 
     In addition, similar to the semiconductor device structure  100   a , the manganese-containing lining layers  123 ′ and  253  of the semiconductor device structure  200   a  are configured to reduce or prevent voids from forming in the conductive plugs  133  and  163 , thereby decreasing the contact resistance of the conductive plugs  133  and  163 . As a result, the operation speed of the semiconductor device structure  200   a  may be increased, which significantly improves the overall device performance. 
       FIG. 4  is a cross-sectional view illustrating a modified semiconductor device structure  200   b , which is an alternative embodiment of the semiconductor device structure  200   a , in accordance with some embodiments. For reasons of consistency and clarity, similar components appearing in both  FIGS. 3 and 4  will be labeled the same. 
     Similar to the semiconductor device structure  200   a , the semiconductor device structure  200   b  includes the conductive plug  133  and the lining layer  123 ′ disposed in the first dielectric layer  105 , and the conductive plug  133  is surrounded by the lining layer  123 ′. A difference is that the energy removable structure  113 ″ and the air gap  180  are not formed in the first dielectric layer  105  of the semiconductor device structure  200   b . That is, the lining layer  123 ′ is in direct contact with the first dielectric layer  105 . 
     In addition, similar to the semiconductor device structure  200   a , the manganese-containing lining layers  123 ′ and  253  of the semiconductor device structure  200   b  are configured to reduce or prevent voids from forming in the conductive plugs  133  and  263 , thereby decreasing the contact resistance of the conductive plugs  133  and  263 . As a result, the operation speed of the semiconductor device structure  200   b  may be increased, which significantly improves the overall device performance. 
       FIG. 5  is a flow diagram illustrating a method  10  of forming a semiconductor device structure (including the semiconductor device structure  100   a  and the modified semiconductor device structures  100   b ,  200   a  and  200   b ), and the method  10  includes steps S 11 , S 13 , S 15 , S 17 , S 19 , S 21  and S 23 , in accordance with some embodiments. The steps S 11  to S 23  of  FIG. 5  are elaborated in connection with the following figures. 
       FIGS. 6 to 17  are cross-sectional views illustrating intermediate stages of forming the semiconductor device structure  100   a , in accordance with some embodiments. As shown in  FIG. 6 , the semiconductor substrate  101  is provided. The semiconductor substrate  101  may be a semiconductor wafer such as a silicon wafer. 
     Alternatively or additionally, the semiconductor substrate  101  may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. 
     In some embodiments, the semiconductor substrate  101  includes an epitaxial layer. For example, the semiconductor substrate  101  has an epitaxial layer overlying a bulk semiconductor. In some embodiments, the semiconductor substrate  101  is a semiconductor-on-insulator substrate which may include a substrate, a buried oxide layer over the substrate, and a semiconductor layer over the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other applicable methods. 
     Still referring to  FIG. 6 , the first conductive layer  103  is formed over the semiconductor substrate  101 , and the first dielectric layer  105  is formed over the first conductive layer  103 , in accordance with some embodiments. The respective step is illustrated as the step S 11  in the method  10  shown in  FIG. 5 . 
     In some embodiments, the first conductive layer  103  includes copper (Cu), and the first conductive layer  103  is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a metal organic chemical vapor deposition (MOCVD) process, a sputtering process, a plating process, or another applicable process. In some embodiments, the first dielectric layer  105  includes silicon oxide, silicon nitride, silicon oxynitride, or another applicable dielectric material, and the first dielectric layer  105  is formed by a deposition process, such as a CVD process, a PVD process, an ALD process, a spin-on coating process, or another applicable process. 
     Next, an etching process is performed on the first dielectric layer  105  to form a first opening  110  exposing the first conductive layer  103 , as shown in  FIG. 7  in accordance with some embodiments. The respective step is illustrated as the step S 13  in the method  10  shown in  FIG. 5 . The formation of the first opening  110  may include forming a patterned mask (not shown) over the first dielectric layer  105 , and etching the first dielectric layer  105  by using the patterned mask as a mask. In addition, the etching process for forming the first opening  110  may be a wet etching process, a dry etching process, or a combination thereof. 
     Subsequently, an energy removable material  113  is conformally deposited over the first dielectric layer  105 , as shown in  FIG. 8  in accordance with some embodiments. In some embodiments, the sidewalls and the bottom surface of the first opening  110  are covered by the energy removable material  113 . Then, an anisotropic etching process is performed on the energy removable material  113  to remove the same amount of the energy removable material  113  vertically in all places, leaving an energy removable layer  113 ′ on the sidewalls of the first opening  110 , as shown in  FIG. 9  in accordance with some embodiments. 
     In some embodiments, the materials of the energy removable layer  113 ′ include a base material and a decomposable porogen material that is substantially removed once being exposed to an energy source (e.g., heat). In some embodiments, the base material includes hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon oxide (SiO 2 ), and the decomposable porogen material includes a porogen organic compound, which can provide porosity to the space originally occupied by the energy removable layer  113 ′ in the subsequent processes. 
     Moreover, the energy removable material  113  may be deposited by a CVD process, a PVD process, an ALD process, a spin-on coating process, or another applicable process. In addition, the anisotropic etching process performed on the energy removable material  113  may be a dry etching process. After the anisotropic etching process is performed, a remaining portion of the first opening  110 ′ surrounded by the energy removable layer  113 ′ is obtained, and the first conductive layer  103  is partially exposed by the remaining portion of the first opening  110 ′, in accordance with some embodiments. 
     It should be noted that the formation of the energy removable layer  113 ′ is optional. In some embodiments, the deposition process of the energy removable material  113  ( FIG. 8 ) and the anisotropic etching process for forming the energy removable layer  113 ′ ( FIG. 9 ) are not performed. In these cases, the air gap  180  and the energy removable structure  113 ″ are not formed, and the resulting structure may be similar to the semiconductor device structure  100   b  in  FIG. 2  or the semiconductor device structure  200   b  in  FIG. 4 . 
     Next, a lining material  123  is conformally deposited over the first dielectric layer  105 , as shown in  FIG. 10  in accordance with some embodiments. In some embodiments, the sidewalls and the bottom surface of the remaining portion of the first opening  110 ′ are covered by the lining material  123 . Then, an anisotropic etching process is performed on the lining material  123  to remove the same amount of the lining material  123  vertically in all places, leaving the lining layer  123 ′ on the sidewalls of the energy removable layer  113 ′, as shown in  FIG. 11  in accordance with some embodiments. 
     In some embodiments, the materials of the lining layer  123 ′ include manganese (Mn), such as copper-manganese-silicon (CuMnSi). In some embodiments, the lining material  123  is deposited by a CVD process, a PVD process, an ALD process, a sputtering process, or another applicable process. In addition, the anisotropic etching process performed on the lining material  123  may be a dry etching process. After the anisotropic etching process is performed, a remaining portion of the first opening  110 ″ surrounded by the lining layer  123 ′ is obtained, and the first conductive layer  103  is partially exposed by the remaining portion of the first opening  110 ″, in accordance with some embodiments. 
     After the lining layer  123 ′ is formed, the conductive plug  133  is formed in the remaining portion of the first opening  110 ″, as shown in  FIG. 12  in accordance with some embodiments. The respective step is illustrated as the step S 15  in the method  10  shown in  FIG. 5 . In some embodiments, the conductive plug  133  is surrounded by the lining layer  123 ′. 
     In some embodiments, the conductive plug  133  includes copper (Cu). In some embodiments, the conductive plug  133  includes copper (Cu) and tungsten (W). The formation of the conductive plug  133  may include conformally depositing a conductive material (not shown) over the first dielectric layer  105  and filling the remaining portion of the first opening  110 ″, and performing a planarization process to remove excess portion of the conductive material over the top surface of the first dielectric layer  105 . In some embodiments, the planarization process for forming the conductive plug  133  is a chemical mechanical polishing (CMP) process. 
     Next, the second conductive layer  143  is formed over the first dielectric layer  105 , as shown in  FIG. 13  in accordance with some embodiments. The respective step is illustrated as the step S 17  in the method  10  shown in  FIG. 5 . In some embodiments, the second conductive layer  143  includes copper (Cu). Some processes used to form the second conductive layer  143  are similar to, or the same as those used to form the first conductive layer  103 , and details thereof are not repeated herein. In some embodiments, the energy removable layer  113 ′, the lining layer  123 ′ and the conductive plug  133  are covered by the second conductive layer  143 . 
     In some embodiments, the second conductive layer  143  and the conductive plug  133  are formed by the same material and are formed simultaneously. For example, the excess portion of the conductive material over the top surface of the first dielectric layer  105  is not removed by the planarizing process, and the portion of the conductive material over the top surface of the first dielectric layer  105  forms the second conductive layer  143  without performing additional deposition process. 
     Subsequently, the second dielectric layer  145  is formed over the second conductive layer  143 , and an etching process is performed on the second dielectric layer  145  to form a second opening  150  exposing the second conductive layer  143 , as shown in  FIG. 14  in accordance with some embodiments. The respective step is illustrated as the step S 19  in the method  10  shown in  FIG. 5 . Some materials and processes used to form the second dielectric layer  145  are similar to, or the same as those used to form the first dielectric layer  105 , and details thereof are not repeated herein. In addition, the second opening  150  may be formed by using a patterned mask. Some processes used to form the second opening  150  are similar to, or the same as those used to form the first opening  110 , and details thereof are not repeated herein. 
     After the second opening  150  is formed, the lining layer  153  is formed over the second dielectric layer  145 , as shown in  FIG. 15  in accordance with some embodiments. In some embodiments, the second opening  150  is lined by the lining layer  153 . Specifically, the top surface  145 T of the second dielectric layer  145 , the sidewalls  150 S and the bottom surface  150 B of the second opening  150  (See  FIG. 14 ) are covered by the lining layer  153 , in accordance with some embodiments. 
     In some embodiments, the lining layer  153  is a multi-layer structure, which includes the first sub-lining layer  155 , the second sub-lining layer  157  and the third sub-lining layer  159 . In some embodiments, the first sub-lining layer  155  includes manganese silicon (MnSi), the second sub-lining layer  157  includes manganese (Mn), and the third sub-lining layer  159  includes copper manganese (CuMn). In some embodiments, the first sub-lining layer  155 , the second sub-lining layer  157  and the third sub-lining layer  159  are formed by deposition processes, such as CVD, PVD, ALD, MOCVD, sputtering, plating. After the lining layer  153  is formed, a remaining portion of the second opening  150 ′ surrounded by the lining layer  153  is obtained. 
     Next, the conductive plug  163  is formed in the remaining portion of the second opening  150 ′, as shown in  FIG. 16  in accordance with some embodiments. The respective step is illustrated as the step S 21  in the method  10  shown in  FIG. 5 . In some embodiments, the conductive plug  163  is surrounded by the lining layer  153 . 
     In some embodiments, the conductive plug  163  includes copper (Cu). In some embodiments, the conductive plug  163  includes copper (Cu) and tungsten (W). The formation of the conductive plug  163  may include conformally depositing a conductive material (not shown) over the lining layer  153  and filling the remaining portion of the second opening  150 ′, and performing a planarization process to remove excess portion of the conductive material over the top surface of the lining layer  153 . In some embodiments, the planarization process for forming the conductive plug  163  is a CMP process. 
     After the conductive plug  163  is formed, the third conductive layer  173  is formed over the second dielectric layer  145 , as shown in  FIG. 17  in accordance with some embodiments. The respective step is illustrated as the step S 23  in the method  10  shown in  FIG. 5 . In some embodiments, the third conductive layer  173  includes copper (Cu). Some processes used to form the third conductive layer  173  are similar to, or the same as those used to form the first conductive layer  103 , and details thereof are not repeated herein. In some embodiments, the lining layer  153  and the conductive plug  163  are covered by the third conductive layer  173 . Similar to the second conductive layer  143  and the conductive plug  133 , the third conductive layer  173  and the conductive plug  163  may be formed by the same material and may be formed simultaneously. 
     Referring back to  FIG. 1 , a heat treatment process is performed on the structure of  FIG. 17  to transform the energy removable layer  113 ′ into the air gap  180 . In some embodiments, the air gap  180  is enclosed by the energy removable structure  113 ″, which is the remaining portion of the energy removable layer  113 ′. 
     More specifically, the heat treatment process is used to remove the decomposable porogen materials of the energy removable layer  113 ′ to generate pores, and the pores are filled by air after the decomposable porogen materials are removed, such that the air gap  180  is obtained, in accordance with some embodiments. In some other embodiments, the heat treatment process can be replaced by a light treatment process, an e-beam treatment process, a combination thereof, or another applicable energy treatment process. For example, an ultra-violet (UV) light or laser light may be used to remove the decomposable porogen materials of the energy removable layer  113 ′, such that the air gap  180  is obtained. After the air gap  180  is formed, the semiconductor device  100   a  is obtained. 
       FIG. 18  is a cross-sectional view illustrating an intermediate stage of forming the lining layer  253  over the second dielectric layer  145  during the formation of the modified semiconductor device structure  200   a  of  FIG. 3 , in accordance with some embodiments. After the second opening  150  is formed (i.e., following the step of  FIG. 14 ), the lining layer  253  is formed over the second dielectric layer  145 , as shown in  FIG. 18  in accordance with some embodiments. 
     In some embodiments, the lining layer  253  is a single layer covering the top surface  145 T of the second dielectric layer  145 , the sidewalls  150 S and the bottom surface  150 B of the second opening  150  (See  FIG. 14 ). In some embodiments, the lining layer  253  includes copper-manganese-silicon (CuMnSi). After the lining layer  253  is formed, a remaining portion of the second opening  250  surrounded by the lining layer  253  is obtained. 
     Subsequently, the remaining portion of the second opening  250  is filled by the conductive plug  163 , and the third conductive layer  173  is formed to cover the lining layer  253  and the conductive plug  163 . After the third conductive layer  173  is formed, a heat treatment process is performed to transform the energy removable layer  113 ′ into the air gap  180 . In some embodiments, the air gap  180  is enclosed by the energy removable structure  113 ″, which is the remaining portion of the energy removable layer  113 ′. After the air gap  180  is formed, the modified semiconductor device  200   a  of  FIG. 3  is obtained. 
       FIG. 19  is a cross-sectional view illustrating a pattern-dense region A and a pattern-loose region B of a semiconductor device structure  300 , in accordance with some embodiments. The semiconductor device structure  300  may be similar to the semiconductor device structure  100   a  where like reference numerals represent like elements. 
     The semiconductor device structure  300  includes a first conductive layer  303  disposed over a semiconductor substrate  301 , a first dielectric layer  305  disposed over the first conductive layer  303 , a second conductive layer  343  disposed over the first dielectric layer  305 , a second dielectric layer  345  disposed over the second conductive layer  343 , and a third conductive layer  373  disposed over the second dielectric layer  345 . Details regarding this embodiment that are similar to those for the previously described embodiments will not be repeated herein. 
     In the pattern-dense region A, the semiconductor device structure  300  includes a lining layer  323   a  and a conductive plug  333   a  disposed in the first dielectric layer  305 , and a lining layer  353  and a conductive plug  363   a  disposed in the second dielectric layer  345 . In some embodiments, the conductive plug  333   a  is surrounded by the lining layer  323   a , and the conductive plug  363   a  is surrounded by the lining layer  353 . Moreover, the semiconductor device structure  300  includes an energy removable structure  313 ′ and an air gap  380  enclosed by the energy removable structure  313 ′ in the pattern-dense region A. 
     In the pattern-dense region B, the semiconductor device structure  300  includes a lining layer  323   b  and a conductive plug  333   b  disposed in the first dielectric layer  305 , and a conductive plug  363   a  disposed in the second dielectric layer  345 . In some embodiments, the conductive plug  333   b  is surrounded by the lining layer  323   b . It should be noted that the lining layer  353  extends from the pattern-dense region A to the pattern-loose region B, and the conductive plug  363   b  is surrounded by the lining layer  353 . 
     Specifically, the lining layer  353  is a multi-layered structure, which includes a first sub-lining layer  355  and a second sub-lining layer  357  disposed over the first sub-lining layer  355 . In some embodiments, the first sub-lining layer  355  is in direct contact with the second conductive layer  343  and the second dielectric layer  345 . In some embodiments, the second sub-lining layer  357  is in direct contact with the conductive plugs  363   a  and  363   b , and the third conductive layer  373 . In some embodiments, the conductive plugs  363   a  and  363   b  are referred to as a first conductive plug and a second conductive plug having different aspect ratios. 
     In some embodiments, the first conductive layer  303 , the second conductive layer  343 , the third conductive layer  373 , and the conductive plugs  333   a ,  333   b ,  363   a  and  363   b  each include copper (Cu), and the lining layers  323   a ,  323   b  and  353  each include manganese (Mn). In some other embodiments, the conductive plugs  333   a ,  333   b ,  363   a  and  363   b  each further include tungsten (W). In particular, the lining layers  323   a  and  323   b  each include copper-manganese-silicon (CuMnSi), the first sub-lining layer  355  of the lining layer  353  includes manganese-rich manganese silicon (MnSi) or manganese (Mn), and the second sub-lining layer  357  of the lining layer  353  includes copper manganese (CuMn), in accordance with some embodiments. 
       FIG. 20  is a flow diagram illustrating a method  30  of forming a semiconductor device structure  300 , and the method  30  includes steps S 31 , S 33 , S 35 , S 37 , S 39 , S 41  and S 43 , in accordance with some embodiments. The steps S 31  to S 43  of  FIG. 20  are elaborated in connection with the following figures. 
       FIGS. 21 to 27  are cross-sectional views illustrating intermediate stages of forming the semiconductor device structure  300 , in accordance with some embodiments. As shown in  FIG. 21 , the first conductive layer  303  is formed over the semiconductor substrate  301 , and the first dielectric layer  305  is formed over the first conductive layer  303 . The respective step is illustrated as the step S 31  in the method  30  shown in  FIG. 20 . 
     Some materials and processes used to form the semiconductor substrate  301  are similar to, or the same as those used to form the semiconductor substrate  101 , and details thereof are not be repeated herein. The first conductive layer  303  and the first dielectric layer  305  may be formed by deposition processes, such as CVD, PVD, ALD, sputtering, spin-on coating. 
     Still referring to  FIG. 21 , the first dielectric layer  305  is etched to form a first opening  310   a  in the pattern-dense region A and a first opening  310   b  in the pattern-loose region B, in accordance with some embodiments. In some embodiments, each of the first openings  310   a  and  310   b  exposes a portion of the first conductive layer  303 . The respective step is illustrated as the step S 33  in the method  30  shown in  FIG. 20 . The etching process for forming the first openings  310   a  and  310   b  may be wet etching process, dry etching process, or a combination thereof. 
     After the first openings  310   a  and  310   b  in the first dielectric layer  305  are formed, a patterned mask (not shown) may be formed to cover the structure in the pattern-loose region B, and an energy removable material (not shown) may be conformally deposited over the first dielectric layer  305 . Then, an anisotropic etching process may be performed on the energy removable material to remove the same amount of the energy removable material vertically in all places, leaving an energy removable layer  313  on the sidewalls of the first opening  310   a  in the pattern-dense region A, as shown in  FIG. 22  in accordance with some embodiments, 
     After the energy removable layer  313  is formed, a remaining portion of the first opening  310   a ′ is surrounded by the energy removable layer  313 . Some materials used to form the energy removable layer  313  may be similar to, or the same as those used to form the energy removable layer  113 ′ (See  FIG. 9 ), and details thereof are not repeated herein. Moreover, the patterned mask used to protect the first opening  310   b  in the pattern-loose region B may be removed after the anisotropic etching process for forming the energy removable layer  313  is performed. 
     Next, the lining layer  323   a  is formed in the remaining portion of the first opening  310   a ′, and the lining layer  323   b  is formed in the first opening  310   b , as shown in  FIG. 23  in accordance with some embodiments. The lining layers  323   a  and  323   b  may be formed simultaneously. 
     In some embodiments, the formation of the lining layers  323   a  and  323   b  includes conformally depositing a lining material (not shown) over the first dielectric layer  305  and covering the sidewalls and the bottom surfaces of the openings  310   a ′ and  310   b , and performing an anisotropic etching process to remove the same amount of the lining material vertically in all places, leaving the lining layer  323   a  on the sidewalls of the energy removable layer  313  in the pattern-dense region A and the lining layer  323   b  on the sidewalls of the first opening  310   b  in the pattern-loose region B. After the anisotropic etching process is performed, a remaining portion of the first opening  310   a ″ is surrounded by the lining layer  323   a , and a remaining portion of the first opening  310   b ′ is surrounded by the lining layer  323   b.    
     After the lining layers  323   a  and  323   b  are formed, the conductive plug  333   a  is formed in the pattern-dense region A and the conductive plug  333   b  is formed in the pattern-loose region B, as shown in  FIG. 24  in accordance with some embodiments. In some embodiments, the remaining portions of the first opening  310   a ″ are filled by the conductive plug  333   a , and the remaining portion of the first opening  310   b ′ is filled by the conductive plug  333   b . The respective step is illustrated as the step S 35  in the method  30  shown in  FIG. 20 . 
     The conductive plugs  333   a  and  333   b  may be formed simultaneously. In some embodiments, the formation of the conductive plugs  333   a  and  333   b  includes a deposition process and a subsequent planarization process. It should be noted that the lining layer  323   b  and the conductive plug  333   b  in the pattern-loose region B are not surrounded by any energy removable layer, in accordance with some embodiments. 
     Next, still referring to  FIG. 24 , the second conductive layer  343  is formed over the first dielectric layer  305 , in accordance with some embodiments. The respective step is illustrated as the step S 37  in the method  30  shown in  FIG. 20 . Some materials and processes used to form the second conductive layer  343  are similar to, or the same as those used to form the first conductive layer  303 , and details thereof are not repeated herein. 
     Subsequently, the second dielectric layer  345  is formed over the second conductive layer  343 , and the second dielectric layer  345  is etched to form a second opening  350   a  in the pattern-dense region A and a second opening  350   b  in the pattern-loose region B, as shown in  FIG. 25  in accordance with some embodiments. In some embodiments, each of the second openings  350   a  and  350   b  exposes a portion of the second conductive layer  343 . The respective step is illustrated as the step S 39  in the method  30  shown in  FIG. 20 . In some embodiments, the opening  350   a  and the opening  350   b  are referred to as a first opening and a second opening having different aspect ratios. 
     Some materials and processes used to form the second dielectric layer  345  are similar to, or the same as those used to form the first dielectric layer  305 , and details thereof are not repeated herein. In addition, the etching process for forming the second openings  350   a  and  350   b  may be wet etching process, dry etching process, or a combination thereof. As shown in  FIG. 25 , the second opening  350   a  in the pattern-dense region A has a width W 3 , and the second opening  350   b  in the pattern-loose region B has a width W 4 . It should be noted that the width W 4  is greater than the width W 3  in accordance with some embodiments. 
     After the second openings  350   a  and  350   b  are formed, the first sub-lining layer  355  of the lining layer  353  is conformally deposited over the second dielectric layer  345  and covering the sidewalls and the bottom surfaces of the second openings  350   a  and  350   b , and the second sub-lining layer  357  of the lining layer  353  is conformally deposited over the first sub-lining layer  355 , as shown in  FIG. 26  in accordance with some embodiments. The first sub-lining layer  355  and the second sub-lining layer  357  of the lining layer  353  are formed by deposition processes, such as CVD, PVD, ALD, MOCVD, sputtering, plating. After the lining layer  353  is formed, a remaining portion of the second opening  350   a ′ in the pattern-dense region A and a remaining portion of the second opening  350   b ′ in the pattern-loose region B are surrounded by the lining layer  353 . 
     As shown in  FIG. 26 , the width W 2  of the remaining portion of the second opening  350   b ′ is greater than the width W 1  of the remaining portion of the second opening  350   a ′, in accordance with some embodiments. Moreover, the depth H 2  of the remaining portion of the second opening  350   b ′ is greater than the depth D 1  of the remaining portion of the second opening  350   a ′, in accordance with some embodiments. 
     Next, the conductive plug  363   a  is formed in the pattern-dense region A, and the conductive plug  363   b  is formed in the pattern-loose region B, as shown in  FIG. 27  in accordance with some embodiments. In some embodiments, the remaining portion of the second opening  350   a ′ is filled by the conductive plug  363   a , and the remaining portion of the second opening  350   b ′ is filled by the conductive plug  363   b . The respective step is illustrated as the step S 41  in the method  30  shown in  FIG. 20 . 
     The conductive plugs  363   a  and  363   b  may be formed simultaneously. Similar to the conductive plugs  333   a  and  333   b , the formation of the conductive plugs  363   a  and  363   b  may include a deposition process and a subsequent planarization process. 
     Still referring to  FIG. 27 , the third conductive layer  373  is formed over the second dielectric layer  345 . In some embodiments, the lining layer  353 , and the conductive plugs  363   a  and  363   b  are covered by the third conductive layer  373 . Some processes used to form the third conductive layer  373  are similar to, or the same as those used to form the first conductive layer  303 , and details thereof are not repeated herein. The respective step is illustrated as the step S 43  in the method  30  shown in  FIG. 20 . 
     In some embodiments, the second opening  350   b  in the pattern-loose region B is wider than the second opening  350   a  in the pattern-dense region A (See  FIG. 25 , the width W 4  is greater than the width W 3 ). Therefore, after the lining layer  353  is formed, the depth D 2  of the remaining portion of the second opening  350   b ′ in the pattern-loose region B is greater than the depth D 1  of the remaining portion of the second opening  350   a ′ in the pattern-dense region A (See  FIG. 26 ). As a result, the width W 2  of the conductive plug  363   b  in the pattern-loose region B is greater than the width W 1  of the conductive plug  363   a  in the pattern-dense region A, and the height H 2  of the conductive plug  363   b  in the pattern-loose region B is greater than the height H 1  of the conductive plug  363   a  in the pattern-dense region A, as shown in  FIG. 27  in accordance with some embodiments. 
     A heat treatment process is performed to transform the energy removable layer  313  into the air gap  380 . In some other embodiments, the heat treatment process can be replaced by a light treatment process, an e-beam treatment process, a combination thereof, or another applicable energy treatment process. In some embodiments, the air gap  380  is enclosed by the energy removable structure  313 ′, which is the remaining portion of the energy removable layer  313 . After the air gap  380  is formed, the semiconductor device structure  300  is obtained. It should be noted that the lining layer  323   b  and the conductive plug  333   b  in the pattern-loose region B are not surrounded by any air gap, in accordance with some embodiments. 
       FIG. 28  is a partial schematic illustration of an exemplary integrated circuit, such as a memory device  1000 , including an array of memory cells  50  in accordance with some embodiments. In some embodiments, the memory device  1000  includes a DRAM. In some embodiments, the memory device  1000  includes a number of memory cells  50  arranged in a grid pattern and including a number of rows and columns. The number of memory cells  50  may vary depending on system requirements and fabrication technology. 
     In some embodiments, each of the memory cells  50  includes an access device and a storage device. The access device is configured to provide controlled access to the storage device. In particular, the access device is a field effect transistor (FET)  51  and the storage device is a capacitor  53 , in accordance with some embodiments. In each of the memory cells  50 , the FET  51  includes a drain  55 , a source  57  and a gate  59 . One terminal of the capacitor  53  is electrically connected to the source  57  of the FET  51 , and the other terminal of the capacitor  53  may be electrically connected to the ground. In addition, in each of the memory cells  50 , the gate  59  of the FET  51  is electrically connected to a word line WL, and the drain  55  of the FET  51  is electrically connected to a bit line BL. 
     The above description mentions the terminal of the FET  51  electrically connected to the capacitor  53  is the source  57 , and the terminal of the FET  51  electrically connected to the bit line BL is the drain  55 . However, during read and write operations, the terminal of the FET  51  electrically connected to the capacitor  53  may be the drain, and the terminal of the FET  51  electrically connected to the bit line BL may be the source. That is, either terminal of the FET  51  could be a source or a drain depending on the manner in which the FET  51  is being controlled by the voltages applied to the source, the drain and the gate. 
     By controlling the voltage at the gate  59  via the word line WL, a voltage potential may be created across the FET  30  such that the electrical charge can flow from the drain  55  to the capacitor  53 . Therefore, the electrical charge stored in the capacitor  53  may be interpreted as a binary data value in the memory cell  30 . For example, a positive charge above a threshold voltage stored in the capacitor  53  may be interpreted as binary “1.” If the charge in the capacitor  53  is below the threshold value, a binary value of “0” is said to be stored in the memory cell  30 . 
     The bit lines BL are configured to read and write data to and from the memory cells  50 . The word lines WL are configured to activate the FET  51  to access a particular row of the memory cells  50 . Accordingly, the memory device  1000  also includes a periphery circuit region which may include an address buffer, a row decoder and a column decoder. The row decoder and the column decoder selectively access the memory cells  50  in response to address signals that are provided to the address buffer during read, write and refresh operations. The address signals are typically provided by an external controller such as a microprocessor or another type of memory controller. 
     Referring back to  FIG. 19 , the air gap  380  is formed in the pattern-dense region A of the semiconductor device structure  300 , while no air gap is formed in the pattern-loose region B of the semiconductor device structure  300 . Moreover, the conductive plug  363   a  having smaller width W 1  and smaller height H 1  is formed in the pattern-dense region A, while the conductive plug  363   b  having greater width W 2  and greater height H 2  is formed in the pattern-loose region B. The pattern-dense region A may be any of the regions of the memory cells  50  in the memory device  1000 , and the pattern-loose region B may be any of the regions of the address buffer, the row decoder, or the column decoder in the memory device  1000 . 
     Embodiments of the semiconductor device structures  100   a ,  100   b ,  200   a ,  200   b  and  300  are provided in the disclosure. In some embodiments, the semiconductor device structures  100   a ,  100   b ,  200   a ,  200   b  and  300  each includes a conductive plug disposed between and electrically connecting two conductive layers in the vertical direction, and a lining layer surrounding the conductive plug. The conductive plug includes copper, and the lining layer includes manganese. The manganese-containing lining layer is configured to reduce or prevent voids from forming in the conductive plug, thereby decreasing the contact resistance of the conductive plug. As a result, the operation speed of the semiconductor device structures  100   a ,  100   b ,  200   a ,  200   b  and  300  may be increased, which significantly improves the overall device performance. 
     In one embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure comprises a substrate having a pattern-dense region and a pattern-loose region; a first conductive layer disposed over the substrate; a first dielectric layer disposed over the first conductive layer; a first conductive plug and a second conductive plug disposed in the first dielectric layer; wherein the first conductive plug and the second conductive plug comprises copper (Cu) and are separated from the first dielectric layer by the a first lining layer comprising manganese (Mn); wherein the first conductive plug and the second conductive plug have different aspect ratios. 
     In another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method comprises: preparing a substrate having a pattern-dense region and a pattern-loose region; forming a first conductive layer disposed over the substrate; forming a first dielectric layer disposed over the first conductive layer; etching the first dielectric layer to form a first opening and a second opening exposing the first conductive layer, wherein the first opening and the second opening have different aspect ratios; forming a first lining layer and a first conductive plug in the first opening and a second conductive plug in the second opening, wherein the first lining layer comprises manganese (Mn), the first conductive plug comprises copper (Cu), and the first conductive plug and the second plug are surrounded by the first lining layer; and forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer, wherein the second conductive layer comprises copper (Cu). 
     The embodiments of the present disclosure have some advantageous features. By forming the manganese-containing lining layer, the resistance of the conductive plug surrounded by the manganese-containing lining layer may be decreased. As a result, the operation speed of the semiconductor device structure is increased, which significantly improves the overall device performance. 
     Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof. 
     Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.