Patent Publication Number: US-2007096786-A1

Title: Reset circuit

Description:
FIELD OF THE INVENTION  
      The present invention relates to a reset circuit, and particularly to an improved reset circuit having a control circuit for protecting a computer system from an undesired reset.  
     DESCRIPTION OF RELATED ART  
      Reset circuits for resetting the state of a circuit system to an original state, and the operation of a conventional reset circuit, are illustrated in  FIG. 2 . Referring to  FIG. 2 , the conventional reset circuit comprises a resistor R′, a diode D′, a capacitor C′, and a reset button S′. The resistor R′ and the reset button S′ are connected between a power supply Vcc and the ground in series. The diode D′ and the capacitor C′ are connected between the power supply Vcc and the ground in series with a cathode of the diode D′ connected to the power supply Vcc and an anode of the diode D′ connected to the capacitor C′. A node between the diode D′ and the capacitor C′ is connected to a node between the resistor R′ and the reset button S′. The node between the resistor R′ and the reset button S′ acts as a reset signal output terminal A′. When the reset button S′ is not pressed down, the voltage at the output terminal A′ is at a high level, and the system works normally. When the reset button S′ is pressed down, the voltage at the output terminal A′ goes to a low level, and a reset signal is output from the power circuit for resetting the system. However, if the reset button is inadvertently pressed, an undesired reset of the system occurs, and the system may experience data damage, data loss, file corruption, or hardware damage. It is apparent that the system does not provide adequate protection against such occurrences.  
      What is needed is to provide an improved reset circuit which provides adequate protection against accidental reset.  
     SUMMARY OF THE INVENTION  
      An exemplary reset circuit includes a reset signal generator and a control circuit. The reset signal generator provides a first reset signal. The control circuit includes a first reset signal input, a control terminal, and an output. The first reset signal input receives the first reset signal, the control terminal receives a control signal, and the control circuit delivers a second reset signal at the output in response to the first reset signal and the control signal.  
      Other advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIG. 1  is a circuit diagram of a reset circuit in accordance with a preferred embodiment of the present invention; and  
       FIG. 2  is a circuit diagram of a conventional reset circuit. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
      Referring to  FIG. 1 , a reset circuit  100  in accordance with a preferred embodiment of the present invention includes a reset signal generator  110  and a control circuit  120 .  
      The reset signal generator  110  comprises a resistor R, a diode D, a capacitor C, and a reset button S. The resistor R and the reset button S are connected between a power supply Vcc and ground in series. The diode D and the capacitor C are connected between the power supply Vcc and ground in series with a cathode of the diode D connected to the power supply Vcc and an anode of the diode D connected to the capacitor C. A node between the diode D and the capacitor C is connected to a node M between the resistor R and the reset button S. The node M acts as a first reset signal output terminal.  
      The control circuit  120  includes a plurality of transistors Q 1 ˜Q 3 , and a plurality of resistors R 1 ˜R 4 . A base of the first transistor Q 1  acts as a first reset signal input of the control circuit  120  and is connected to the node M, a collector of the first transistor Q 1  is connected to the power supply Vcc via the resistor R 1 , and an emitter of the first transistor Q 1  is grounded. A base of the second transistor Q 2  is connected to the collector of the first transistor Q 1  via the resistor R 3 . A collector of the second transistor Q 2  is connected to the power supply Vcc via the resistor R 2 , and an emitter of the second transistor Q 2  is connected to a collector of the third transistor Q 3 . A base of the third transistor Q 3  is connected to a control terminal E via the resistor R 4 , and an emitter of the third transistor Q 3  is grounded. The node between the resistor R 2  and the collector of the second transistor Q 2  acts as an output A of the control circuit  120 .  
      In operation, if a system utilizing the reset circuit  100  need not be reset, a voltage at the control terminal E is set at a low level by a user command at a terminal of the system, the third transistor Q 3  is turned off, and the second transistor Q 2  is also turned off, a voltage at the output A of the control circuit  120  is always high, and the system can not be reset, even if the reset button S is pushed.  
      If the system needs to be reset, the voltage at the control terminal E is set at a high level, the third transistor Q 3  is turned on. If the reset button S is not pressed down, the voltage at the node M is at a high level, the first transistor Q 1  is turned on, the second transistor Q 2  is turned off, the voltage at the output A of the control circuit  120  is high, and the system works normally. If the reset button S is pressed down, the first reset signal is at a low level, the voltage at the base of the first transistor Q 1  is at a low level, the first transistor Q 1  is turned off, the second transistor Q 2  is turned on, the transistor Q 3  is turned on, so the voltage at the output A of the control circuit  120  is at a low level, and a second reset signal is output from the output A of the control circuit  120  for resetting the system.  
      According to the above embodiment, an enable control signal is output from the control terminal E of the control circuit  120  when the system is to be reset, and the reset signal generator  110  outputs a first reset signal to the control circuit  120 , a second reset signal is output from the control circuit  120  for resetting the system in accordance with the first reset signal and the control signal. When the system need not be reset, the control signal at the control circuit is disabled, the system cannot be reset even if the first reset signal is received. So the reset signal generator  110  associated with the control circuit  120  protects the system from an accidental reset.  
      It is believed that the present embodiment and its advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the invention or sacrificing all of its material advantages, the example hereinbefore described merely being preferred or exemplary embodiment of the invention.