Patent Publication Number: US-2023157144-A1

Title: Perovskite displays and methods of formation

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to U.S. Provisional Patent Application No. 63/005,047, filed on Apr. 3, 2020, U.S. Provisional Patent Application No. 63/006,768, filed on Apr. 8, 2020, and U.S. Provisional Patent Application No. 63/108,617, filed on Nov. 2, 2020, the entire contents of all of which are incorporated herein by reference. 
     Also incorporated by reference herein is “Photolithographic Patterning of Perovskite Thin Films for Multicolor Display Applications,” Chen Zou, Cheng Chang, Di Sun, Karl F. Bohringer, and Lih Y. Lin, Nano Letters 2020 20 (5), 3710-3717, DOI: 10.1021/acs.nanolett.0c00701. 
     Also incorporated by reference herein is “Suppressing Efficiency Roll-Off at High Current Densities for Ultra-Bright Green Perovskite Light-Emitting Diodes,” Chen Zou, Yun Liu, David S. Ginger, and Lih Y. Lin, ACS Nano 2020 14 (5), 6076-6086, DOI: 10.1021/acsnano.0c01817 
     Also incorporated by reference herein is “C. Chang, C. Zou, M. Odendahl, and L. Y Lin, “A Dry Lift-off Method for Patterning Perovskites,” in Conference on Lasers and Electro-Optics, OSA Technical Digest (Optical Society of America, 2020), paper SF3F.7. 
    
    
     FEDERAL FUNDING STATEMENT 
     This invention was made with government support under Grant No. ECCS1807397, awarded by the National Science Foundation. The government has certain rights in the invention. 
    
    
     BACKGROUND 
     Metal halide perovskites are emerging as attractive materials for various display applications, such as light-emitting diode (LED) displays and photoluminescent display technologies. These display applications typically involve the patterning of various material layers of a device structure. However, several lithographic methods widely used for patterning other materials have notable drawbacks when applied to perovskite materials. 
     SUMMARY 
     In a first aspect of the disclosure, a method comprises: forming a barrier layer on a substrate; removing a portion of the barrier layer to yield a patterned barrier layer and an exposed portion of the substrate within a hole in the patterned barrier layer; forming a first portion of a perovskite on the patterned barrier layer and a second portion of the perovskite on the exposed portion of the substrate; and removing the patterned barrier layer, thereby removing the first portion of the perovskite. 
     In a second aspect of the disclosure, a semiconductor structure comprises an array of perovskite islands on a substrate, the array of perovskite islands having a pitch of 10 μm or less. 
     In a third aspect of the disclosure, an intermediate structure for formation of a semiconductor structure comprises: a substrate; and a patterned layer of poly(p-xylylene) on the substrate, the patterned layer exposing a portion of the substrate. 
     In a fourth aspect of the disclosure, a semiconductor structure comprises: a substrate; an electrically insulating layer on the substrate, the electrically insulating layer forming an aperture; one or more functional layers on the electrically insulating layer and within the aperture; and an electrode layer on the one or more functional layers. 
     In a fifth aspect of the disclosure, a method of forming a semiconductor structure comprises: forming the electrically insulating layer on the substrate such that the electrically insulating layer forms the aperture that exposes the substrate; forming the one or more functional layers on the electrically insulating layer and within the aperture on the substrate; and forming the electrode layer on the one or more functional layers. 
     When the term “substantially” or “about” is used herein, it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including, for example, tolerances, measurement error, measurement accuracy limitations, and other factors known to those of skill in the art may occur in amounts that do not preclude the effect the characteristic was intended to provide. In some examples disclosed herein, “substantially” or “about” means within +/−0-5% of the recited value. 
     These, as well as other aspects, advantages, and alternatives will become apparent to those of ordinary skill in the art by reading the following detailed description, with reference where appropriate to the accompanying drawings. Further, it should be understood that this summary and other descriptions and figures provided herein are intended to illustrate the invention by way of example only and, as such, that numerous variations are possible. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic cross section of an intermediate structure, according to an example embodiment. 
         FIG.  2    is a schematic cross section of a semiconductor structure, according to an example embodiment. 
         FIG.  3    is a schematic diagram of a method for forming a semiconductor structure, according to an example embodiment. 
         FIG.  4    is a schematic cross section of an intermediate structure, according to an example embodiment. 
         FIG.  5    is a schematic cross section of an intermediate structure, according to an example embodiment. 
         FIG.  6    is a schematic cross section of an intermediate structure, according to an example embodiment. 
         FIG.  7    is a schematic cross section of an intermediate structure, according to an example embodiment. 
         FIG.  8    is a schematic cross section of a semiconductor structure, according to an example embodiment. 
         FIG.  9    is a schematic diagram of a method for forming a semiconductor structure, according to an example embodiment. 
         FIG.  10    is a schematic cross section of a semiconductor structure, according to an example embodiment. 
         FIG.  11    is a block diagram of a display system, according to an example embodiment. 
         FIG.  12    is a block diagram of a method, according to an example embodiment. 
         FIG.  13    is a block diagram of a method, according to an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     As noted above, more reliable methods for patterning and processing perovskite materials to produce display devices are needed. Examples of such methods and devices are discussed in the present disclosure. 
       FIG.  1    is a schematic cross section of an intermediate structure  100 . The intermediate structure  100  can be used to form a semiconductor structure  200  shown in  FIG.  2   . The intermediate structure  100  includes a substrate  102  and a patterned layer of poly(p-xylylene)  104  on the substrate  102 . The patterned layer of poly(p-xylylene)  104  exposes a portion  702  of the substrate  102 . 
     The substrate  102  can be formed of glass, silicon, polyester (PET), polyimide (PI), polyethylene naphthalate (PEN), polyetherimide (PEI), or sapphire. 
     The poly(p-xylylene)  104  can include one or more of Parylene™ C, Parylene™ Parylene™ FIT, Parylene™ AF-4, or Parylene™ F. 
       FIG.  2    is a schematic cross section of the semiconductor structure  200 . The semiconductor structure  200  includes an array of perovskite islands  108  on the substrate  102 . The array of perovskite  108  islands have a pitch  110  of 10 μm or less. The process described below can yield structures with this pitch. The perovskite islands  108  can absorb light and remit light in a different color. For example, the perovskite islands  108  can absorb blue light and remit green or red light. 
     The semiconductor structure  200  can be part of a display including a virtual reality display, an extended reality display, an augmented reality display, an energy efficient display, a full color display, a multi-color display, a full spectrum display, a high-definition display, a light emitting diode (LED) display, an organic light emitting diode (OLED) display, a monochrome display, and/or a liquid crystal display (LCD). 
       FIG.  3    is a schematic depiction of a method for forming the semiconductor structure  200 . 
     Panel a) shows the substrate  102 . Referring to panel b), chemical vapor deposition (CVD) is used to deposit a barrier layer  104  (e.g., of poly(p-xylylene)) on the substrate  102  at an ambient temperature of 18° C. to 23° C. The barrier layer  104  has a thickness of 1 μm to 5 μm. As shown, the barrier layer  104  covers a portion  702  of the substrate  102  and a portion  704  of the substrate  102 . In some examples, the portion  702  and the portion  704  are pixels (e.g., a light emitting diodes) of a display. More specifically, the portion  702  and the portion  704  are pixels that emit blue light. 
     In panel c), a photoresist layer  202  is formed (e.g., via spin coating) on the barrier layer  104 . In panel d), a mask (not shown) is used to cover a portion  202   b  of the photoresist layer  202  while a portion  202   a  of the photoresist layer  202  is exposed to light  204 . In panel e), the photoresist layer  202  is developed and the portion  202   b  is removed to form a hole  118  within the photoresist layer  202 . In this example, negative photoresist is used, but positive photoresist can instead be used. 
     In panel f), the barrier layer  104  is etched (e.g., via reactive ion etching or acetone immersion) at the bottom of the hole  118  to form the hole  106  in the barrier layer  104 . In panel g), the photoresist layer  202  is stripped away. In panel h), a first portion  108   a  of a perovskite is formed on the barrier layer  104  and a second portion  108   b  is formed on the exposed portion  702  of the substrate  102 . For example, the first portion  108   a  and the second portion  108   b  of the perovskite  108  can be formed via spin coating. 
     More specifically, one can dispense a solution of one or more of C 8 H 12 BrN (PEABr), CsBr, or PbBr 2  dissolved within dimethyl sulfoxide on the barrier layer  104  and on the exposed portion  702  of the substrate  102  and spin the substrate  102  such that the solution is spread across the barrier layer  104  and on the exposed portion  702  of the substrate  102 . 
     Additionally or alternatively, one can dispense a solution of one or more of C 8 H 12 ClN (PEACl), CsCl, PbCl 2 , C 8 H 12 IN(PEAI), CsI, or PbI 2  dissolved within dimethyl sulfoxide on the barrier layer  104  and on the exposed portion  702  of the substrate  102  and spin the substrate  102  such that the solution is spread across the barrier layer  104  and on the exposed portion  702  of the substrate  102 . 
     Generally, the perovskite  108  includes one or more metal halides with a formula ABX 3 , with A being a monovalent cation including one or more of Cs, methylammonium, or formamidinium, B being a metal including Pb or Sn, and X being a halide including Cl, Br, or I. The perovskite  108  is cured and solidified by annealing the perovskite  108  at an ambient temperature within a range of 90° C. to 110° C. 
     In panel i), the barrier layer  104  is removed, thereby concurrently removing the first portion  108   a  of the perovskite. For example, the barrier layer  104  can be immersed in a solvent such as acetone, dissolved, and rinsed away from the substrate  102 . In another example, the barrier layer  104  can be removed manually and/or via mechanical means (e.g., tweezers). 
     This process leaves the second portion  108   b  of the perovskite on the substrate  102 , forming the semiconductor structure  200 . As one of skill in the art can appreciate, the barrier layer  104  can be patterned using the aforementioned process to expose many portions (e.g., pixels) on the substrate  102  to be covered with the perovskite  108 . 
       FIG.  4    is a schematic cross section of an intermediate structure  150 . In some examples, an insulating layer  120  can be formed and patterned on the substrate  102  prior to forming the barrier layer  104  on the substrate  102 . The insulating layer  120  forms a second hole  122  that exposes the portion  702  of the substrate  102 . In this example, the insulating layer  120  is formed on an electrode layer  124  of the substrate  102 . 
     As shown in  FIG.  5   , the barrier layer  104  is then formed on the insulating layer  120  and within the hole(s)  122  of the insulating layer  120 . In  FIG.  6   , the portions of the barrier layer  104  within the holes  122  are etched or otherwise removed. The hole(s)  106  in the barrier layer are aligned with the hole(s)  122  in the insulating layer  120 . 
     In  FIG.  7   , the first portion  108   a  and the second portion  108   b  of the perovskite  108  are formed on the barrier layer  104  that remains and on the exposed portions  702  of the substrate  102 , respectively. A hole transport layer and an electron transport layer (not shown) can also be deposited to form an LED with the second portion  108   b  of the perovskite  108 . 
     In  FIG.  8   , the barrier layer  104  is removed as described above, and an additional electrode layer  126  is deposited on the insulating layer  120  and the second portion  108   b  of the perovskite  108 . The electrode layer  126  can be patterned so that pixels can be individually addressed. 
       FIG.  9    is a schematic depiction of a method for forming additional perovskite materials (e.g., having a different color) on the substrate  102 . In this example, the portions  108   a  and  108   b  of the perovskite  108  are configured to emit first light via photoluminescence, the first light having a first spectral power distribution (e.g., green). 
     In panel a), the portion(s)  108   b  of the perovskite  108  are already on the substrate  102 . In panel b), another barrier layer  104  is formed on the portion  108   b  of the perovskite  108  and on the substrate  102 . Also, a photoresist layer  202  is formed (e.g., via spin coating) on the barrier layer  104 . A mask is used to cover a portion  202   b  of the photoresist layer  202  while another portion  202   a  of the photoresist layer  202  is exposed to light  204 . In panel c), the photoresist layer  202  is developed and the portion  202   b  is removed to form a hole  118  within the photoresist layer  202 . In this example, negative photoresist is used, but positive photoresist can instead be used. 
     In panel d), a portion  207  of the barrier layer  104  is etched or otherwise removed from the substrate  102 . This exposes the portion  704  of the substrate within the hole  106  in the barrier layer  104 . In panel e), a first portion  208   a  of a second perovskite  208  is formed on the barrier layer  104  and a second portion  208   b  of the perovskite  208  is formed on the portion  704  of the substrate. In this context, the second perovskite  208  is configured to emit second light via photoluminescence, the second light having a second spectral power distribution (e.g., red). In panel f), the barrier layer  104  is removed, as described above, thereby removing the first portion  208   a  of the perovskite  208 . 
     This process leaves the second portion  208   b  of the perovskite  208  on the substrate  102  with the second portion  108   b  of the perovskite  108 , forming the semiconductor structure  200 . As one of skill in the art can appreciate, the barrier layer  104  can be patterned using the aforementioned process to expose many portions (e.g., pixels) on the substrate  102  to be covered with the perovskite  208 . In this way, pixels of the substrate  102  can be covered with numerous green or red perovskite materials to emit green or red light, whereas uncovered pixels of the substrate  102  can emit blue light. 
       FIG.  10    is a schematic cross section of a semiconductor structure  400 . The semiconductor structure  400  includes the substrate  102  (e.g., glass) and the electrically insulating layer  120  (e.g., silicon dioxide) on the substrate  102 . The electrically insulating layer  120  forms an aperture  402 . The semiconductor structure  400  also includes one or more functional layers  404  on the electrically insulating layer  120  and within the aperture  402 , and an electrode layer  124  (e.g, aluminum and/or lithium fluoride) on the one or more functional layers  404 . 
     The substrate  102  is substantially transparent to visible light. The substrate  102  includes an electrically conductive layer  125  in contact with the electrically insulating layer  120 . The electrically conductive layer  125  (e.g., indium tin oxide (ITO)) is substantially transparent to visible light. 
     In some examples, the one or more functional layers  404  are the active layers of a light emitting diode (LED). A first thickness  406  of the one or more functional layers  404  aligned with the aperture  402  can be greater than a second thickness  408  of the one or more functional layers  404  over the electrically insulating layer  120 . The one or more functional layers  404  can form a surface  410  that is indented toward the electrically insulating layer  120  over the aperture  402 . The one or more functional layers  404  are in contact with the electrically conductive layer  125 . The one or more functional layers  404  include one or more of a hole transport layer, a perovskite material that includes KBr, or 2,2′,2″-(1,3,5-Benzinetriyl)-tris(1-phenyl-1-H-benzimidazole) (TPBi). 
     The electrode layer  124  forms a surface  412  that can be indented toward the electrically insulating layer  120  over the aperture  402 . The semiconductor structure  400  can be part of a virtual reality, extended reality, or augmented reality display system. 
     In an example, the electrically insulating layer  120  is formed on the substrate  102  (e.g., on the electrically conductive layer  125 ) such that the electrically insulating layer  120  forms the aperture  402  that exposes the substrate  102 . That is, the electrically insulating layer  120  can be deposited and patterned using methods described above. 
     Next, the one or more functional layers  404  are formed (e.g., via spin coating or CVD) on the electrically insulating layer  120  and within the aperture  402  on the substrate  102 . The electrode layer  124  is also formed on the one or more functional layers  404  (e.g., via sputtering). 
       FIG.  11    is a schematic diagram of a display system  901 . The display system  901  includes one or more processors  902 , a non-transitory computer readable medium  904 , a communication interface  906 , a display  908 , and a user interface  910 . Components of the display system  901  are linked together by a system bus, network, or other connection mechanism  912 . 
     The one or more processors  902  can be any type of processor(s), such as a microprocessor, a digital signal processor, a multicore processor, etc., coupled to the non-transitory computer readable medium  904 . 
     The non-transitory computer readable medium  904  can be any type of memory, such as volatile memory like random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), or non-volatile memory like read-only memory (ROM), flash memory, magnetic or optical disks, or compact-disc read-only memory (CD-ROM), among other devices used to store data or programs on a temporary or permanent basis. 
     Additionally, the non-transitory computer readable medium  904  can be configured to store instructions  914 . The instructions  914  are executable by the one or more processors  902  to cause the display system  901  to perform any of the functions or methods described herein. 
     The communication interface  906  can include hardware to enable communication within the display system  901  and/or between the display system  901  and one or more other devices. The hardware can include transmitters, receivers, and antennas, for example. The communication interface  906  can be configured to facilitate communication with one or more other devices, in accordance with one or more wired or wireless communication protocols. For example, the communication interface  906  can be configured to facilitate wireless data communication for the display system  901  according to one or more wireless communication standards, such as one or more Institute of Electrical and Electronics Engineers (IEEE) 801.11 standards, ZigBee standards, Bluetooth standards, etc. As another example, the communication interface  906  can be configured to facilitate wired data communication with one or more other devices. 
     The display  908  can be any type of display component configured to display data. As one example, the display  908  can include a touchscreen display. As another example, the display  908  can include a flat-panel display, such as a liquid-crystal display (LCD) or a light-emitting diode (LED) display. Additionally or alternatively, the display  908  includes a virtual reality display, an extended reality display, and/or an augmented reality display. 
     The user interface  910  can include one or more pieces of hardware used to provide data and control signals to the display system  901 . For instance, the user interface  910  can include a mouse or a pointing device, a keyboard or a keypad, a microphone, a touchpad, or a touchscreen, among other possible types of user input devices. Generally, the user interface  910  can enable an operator to interact with a graphical user interface (GUI) provided by the display system  901  (e.g., displayed by the display  908 ). 
       FIG.  12    and  FIG.  13    are block diagrams of the method  300  and the method  500 . As shown in  FIG.  12    and  FIG.  13   , the method  300  and the method  500  include one or more operations, functions, or actions as illustrated by blocks  302 ,  304 ,  306 ,  308 ,  502 ,  504 , and  506 . Although the blocks are illustrated in a sequential order, these blocks may also be performed in parallel, and/or in a different order than those described herein. Also, the various blocks may be combined into fewer blocks, divided into additional blocks, and/or removed based upon the desired implementation. 
     At block  302 , the method  300  includes forming the barrier layer  104  on the substrate  102 , as shown in  FIG.  3    and  FIG.  5   . 
     At block  304 , the method  300  includes removing the portion  105  of the barrier layer  104  to yield the patterned barrier layer  104  and the exposed portion  702  of the substrate  102  within the hole  106  in the patterned barrier layer  104 , as shown in  FIG.  3    and  FIG.  6   . 
     At block  306 , the method  300  includes forming the first portion  108   a  of the perovskite  108  on the patterned barrier layer  104  and the second portion  108   b  of the perovskite  108  on the exposed portion  702  of the substrate  102 , as shown in  FIG.  3   . 
     At block  308 , the method  300  includes removing the patterned barrier layer  104 , thereby removing the first portion  108   a  of the perovskite  108 . 
     At block  502 , the method  500  includes forming the electrically insulating layer  120  on the substrate  102  such that the electrically insulating layer  120  forms the aperture  402  that exposes the substrate  102 , as shown in  FIG.  10   . 
     At block  504 , the method  500  includes forming the one or more functional layers  404  on the electrically insulating layer  120  and within the aperture  402  on the substrate  102 , as shown in  FIG.  10   . 
     At block  506 , the method  500  includes forming the electrode layer  124  on the one or more functional layers  404 , as shown in  FIG.  10   . 
     Examples of the present disclosure can thus relate to one of the enumerated clauses (ECs) listed below. 
     Clause 1 is a method comprising: forming a barrier layer on a substrate; removing a portion of the barrier layer to yield a patterned barrier layer and an exposed portion of the substrate within a hole in the patterned barrier layer; forming a first portion of a perovskite on the patterned barrier layer and a second portion of the perovskite on the exposed portion of the substrate; and removing the patterned barrier layer, thereby removing the first portion of the perovskite. 
     Clause 2 is the method of clause 1, wherein the barrier layer comprises poly(p-xylylene). 
     Clause 3 is the method of any of clauses 1-2, wherein the exposed portion of the substrate includes a first pixel. 
     Clause 4 is the method of any of clauses 1-3, wherein removing the portion of the barrier layer comprises dissolving or etching the portion of the barrier layer. 
     Clause 5 is the method of any of clauses 1-4, wherein removing the patterned barrier layer comprises dissolving or etching the patterned barrier layer. 
     Clause 6 is the method of any of clauses 1-5, wherein forming the barrier layer on the substrate comprises forming one or more of Parylene™ C, Parylene™ D. Parylene™ FIT, Parylene™ AF-4, or Parylene™ F on the substrate 
     Clause 7 is the method of any of clauses 1-6, wherein removing the portion of the barrier layer comprises removing multiple portions of the barrier layer to yield an array of exposed pixels of the substrate within holes in the patterned barrier layer, and wherein forming the second portion of the perovskite comprises forming the second portion of the perovskite on the exposed pixels of the substrate. 
     Clause 8 is the method of any of clauses 1-7, wherein forming barrier layer on the substrate comprises forming the barrier layer on glass, silicon, polyester (PET), polyimide (PI), polyethylene naphthalate (PEN), polyetherimide (PEI), or sapphire. 
     Clause 9 is the method of any of clauses 1-8, wherein forming the barrier layer on the substrate comprises forming the barrier layer via chemical vapor deposition (CVD). 
     Clause 10 is the method of any of clauses 1-9, wherein forming the barrier layer on the substrate comprises forming the barrier layer at an ambient temperature within a range of 18° C. to 23° C. 
     Clause 11 is the method of any of clauses 1-10, wherein forming the barrier layer on the substrate comprises forming the barrier layer on the substrate to have a thickness within a range of 1 μm to 5 μm. 
     Clause 12 is the method of any of clauses 1-11, wherein removing the portion of the barrier layer comprises: forming a photoresist layer on the barrier layer; exposing a portion of the photoresist layer not covered by a mask to light; developing the photoresist layer, thereby creating a second hole within the photoresist layer; and etching the barrier layer at a bottom of the second hole, thereby forming the hole in the patterned barrier layer. 
     Clause 13 is the method of clause 12, wherein etching the barrier layer at the bottom of the second hole comprises performing reactive ion etching (RIE). 
     Clause 14 is the method of any of clauses 12-13, wherein etching the barrier layer at the bottom of the second hole comprises etching the barrier layer with a solvent. 
     Clause 15 is the method of any of clauses 1-14, wherein forming the first portion and the second portion of the perovskite comprises forming the first portion and the second portion of the perovskite via spin coating. 
     Clause 16 is the method of clause 15, wherein forming the first portion and the second portion of the perovskite via spin coating comprises: dispensing a solution of one or more of C 8 H 12 BrN (PEABr), CsBr, or PbBr 2  dissolved within dimethyl sulfoxide on the patterned barrier layer and on the exposed portion of the substrate; and spinning the substrate such that the solution is spread across the patterned barrier layer and on the exposed portion of the substrate. 
     Clause 17 is the method of any of clauses 15-16, wherein forming the first portion and the second portion of the perovskite via spin coating comprises: dispensing a solution of one or more of C 8 H 12 ClN (PEACl), CsCl, PbCl 2 , C 8 H 12 IN (PEAI), CsI, or PbI 2  dissolved within dimethyl sulfoxide on the patterned barrier layer and on the exposed portion of the substrate; and spinning the substrate such that the solution is spread across the patterned barrier layer and on the exposed portion of the substrate. 
     Clause 18 is the method of any of clauses 1-17, wherein forming the first portion and the second portion of the perovskite comprises forming the first portion and the second portion of the perovskite to include one or more metal halides with a formula ABX 3 , with A being a monovalent cation including one or more of Cs, methylammonium, or formamidinium, B being a metal including Pb or Sn, and X being a halide including Cl, Br, or I. 
     Clause 19 is the method of any of clauses 1-18, wherein forming the first portion and the second portion of the perovskite comprises annealing the perovskite. 
     Clause 20 is the method of any of clauses 1-19, wherein removing the patterned barrier layer comprises clasping the patterned barrier layer and pulling the patterned barrier layer off of the substrate. 
     Clause 21 is the method of any of clauses 1-20, further comprising: prior to forming the barrier layer on the substrate, forming and patterning an insulating layer on the substrate to yield a patterned insulating layer and the exposed portion of the substrate within a second hole of the patterned insulating layer; and wherein forming the barrier layer on the substrate comprises forming the barrier layer on the patterned insulating layer and within the second hole of the patterned insulating layer, and wherein the hole in the patterned barrier layer is aligned with the second hole of the patterned insulating layer. 
     Clause 22 is the method of clause 21, wherein forming and patterning the insulating layer on the substrate comprises forming and patterning the insulating layer on an electrode layer of the substrate. 
     Clause 23 is the method of clause 22, further comprising depositing a second electrode layer on the patterned insulating layer and the second portion of the perovskite. 
     Clause 24 is the method of any of clauses 1-23, wherein the perovskite is a first perovskite configured to emit first light via photoluminescence, the first light having a first spectral power distribution, the method further comprising: forming an additional barrier layer on the second portion of the first perovskite and on the substrate; removing a portion of the additional barrier layer to yield a second patterned barrier layer and a second exposed portion of the substrate within a second hole in the second patterned barrier layer; forming a first portion of a second perovskite on the second patterned barrier layer and a second portion of the second perovskite on the second exposed portion of the substrate, wherein the second perovskite is configured to emit second light via photoluminescence, the second light having a second spectral power distribution that is substantially different from the first spectral power distribution; and removing the second patterned barrier layer, thereby removing the first portion of the second perovskite. 
     Clause 25 is the method of clause 24, wherein the second exposed portion of the substrate includes a second pixel. 
     While various example aspects and example embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various example aspects and example embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.