Patent Publication Number: US-7911367-B2

Title: Method and circuit for converting an N-bit digital value into an analog value

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority of European Patent Application No. 08009751.2 EP filed May 28, 2008, which is incorporated by reference herein in its entirety. 
     FIELD OF INVENTION 
     The invention relates to a method for converting an N-bit digital value into an analog value. 
     It further relates to a corresponding circuit. 
     BACKGROUND OF INVENTION 
     It is well known to convert a digital value into an analog value by first converting the digital value into a pulse width modulated (PWM) signal and then low-pass filtering the PWM signal to remove high frequency components, leaving only the low-frequency content. 
     Further known are PWM controllers having two ore more PWM channels. 
     SUMMARY OF INVENTION 
     There is a problem when an N-bit, e.g. 12 bit, digital-to-analog conversion (DAC) is wanted but the PWM controller only offers N-M bit, e.g. 8 bit. 
     An object of the invention is to provide a high precision DAC conversion by using lower-resolution PWM. 
     According to the invention, this is achieved by a method and a circuit as claimed in the independent claims. 
     Preferred embodiments of the method and circuit according to the invention are specified in the remaining claims. 
     According to the invention, an N-bit digital value is converted into an analog value by:
     converting the N-M most significant bits of the digital value into a first PWM signal whose period is a multiple of a base time period,   converting the M least significant bits of the digital value into a second PWM signal whose period is a ½ M  fraction of the period of the first PWM signal,   generating a third PWM signal by inserting, during the pulse pause of the first PWM signal, the pulse of a selected single period of the second PWM signal into the first PWM signal, and   low-pass filtering the third PWM signal.   

     The first PWM signal provides a coarse DAC, whereas the second PWM signal provides a fine DAC. The output of the fine DAC is used to correct the output of the coarse DAC, thus providing the high-precision third PWM signal which is then low-pass filtered. 
     The single period of the second PWM signal containing the pulse for fine correcting the coarse pulse of the first PWM signal may be selected by masking the second PWM signal with a mask pulse through an AND gate. The pulse for fine correction may be then simply inserted into the pulse pause of the first, coarse PWM signal by an OR operation of the first PWM signal and the masked second PWM signal. 
     Normally, a PWM cycle starts with a pulse of variable length followed by a pulse pause. To make it easier to insert the pulse for fine correction into the pulse pause of the first, coarse PWM signal, the N-M most significant bits of the digital value are preferably inverted before they are converted into the first PWM signal, and the first PWM signal is inverted so that the pulse of the first PWM signal is shifted from the beginning to the end of the PWM signal period. This allows generating the mask pulse for selecting the pulse for fine correction synchronously with the beginning of the period of the first PWM signal. 
     In a preferred embodiment of the invention a 12-bit digital value is converted into an analog value by using two 8-bit PWM signals. In the same way, two 16-bit PWM signals could be used for a 24-bit DAC. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For further description of the invention, reference is made to the accompanying drawings, in which, by way of example: 
         FIG. 1  is a simplified schematic diagram of a circuit for converting a digital value into an analog value; and 
         FIG. 2  shows a timing diagram of signals in the circuit of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION OF INVENTION 
     Referring to  FIG. 1 , a PWM controller  1  comprises a first 8-bit PWM signal output  2  providing an intermediate first 8-bit PWM signal PWM 1 ′, and a second 8-bit PWM signal output  3  providing a second 8-bit PWM signal PWM 2 . It is intended to convert a digital 12-bit value into a corresponding analog value. Thus, an N-bit DAC, here 12-bit DAC, is wanted but the PWM controller  1  only offers N-M bit, here 12−4 bit=8 bit. 
     For example, the circuit shown in  FIG. 1  is part of an industrial 4-20 mA process device which shall output a value of 8.102 mA. Thus, the digital value to be converted to analog is [(8.102 mA−4 mA)/(20 mA−4 mA)]·2 12 =1050=010000011010. 
     As shown in  FIG. 2 , the intermediate first 8-bit PWM signal PWM 1 ′ has a period of 2 12  T=4096 T, where T is a base time period (clock) provided by a timer of the PWM controller  1 . The resolution of the first 8-bit PWM signal PWM 1  is then (2 12  T)/2 8 =16 T. 
     The period of the second 8-bit PWM signal PWM 2  is set to a ½ M =½ 4  fraction of the period of the first PWM signal, i.e. 2 8  T=256 T. Thus, the resolution of the second 8-bit PWM signal PWM 2  is (2 8  T)/2 8 =1 T. 
     If the N−M=12−4=8 most significant bits of the digital value, i.e. 01000001, are PWM converted, one would obtain a PWM signal PWM 1 *, as shown at the top of  FIG. 2 . There, the pulse starts at the beginning of the PWM period (cycle) and is followed by a pulse pause at the end of the PWM cycle. To shift the pulse from the beginning to the end of the pulse cycle, the 8 most significant bits of the digital value, i.e. 01000001, are first inverted to 10111110 before they are converted into the intermediate first PWM signal PWM 1 ′. The intermediate first PWM signal PWM 1 ′ is then inverted by means of an inverter (NOT gate)  4  to a first PWM signal PWM 1 . 
     The remaining M=4 least significant bits of the digital value, i.e. 1010, are converted into the second PWM signal PWM 2 . The PWM controller  1  further generates at an output  5  a mask pulse MASK at the beginning of each cycle of the first PWM signal PWM 1 . The length of the mask pulse MASK is equal to the period of the second PWM signal PWM 2 . Through an AND gate  6 , the second PWM signal PWM 2  is masked with the mask pulse MASK to select the pulse of the first period of the second PWM signal PWM 2  during the period of the first PWM signal PWM 1 . That means that the selected pulse of the second PWM signal PWM 2  coincide with the beginning of the pulse pause of the first PWM signal PWM 1 . 
     The first PWM signal PWM 1  and the masked second PWM signal PWM 2   #  are fed to an OR gate to generate a third PWM signal PWM 3  which is then low-pass filtered by a low-pass filter  8  to obtain the wanted analog value. 
     If the PWM signal PWM* is used instead of PWM 1 , the mask pulse must be generated at the end of the cycle of the PWM signal PWM*. In this case, the NOT gate  4  is not needed.