Patent Publication Number: US-11043534-B2

Title: Cell pillar structures and integrated flows

Description:
PRIORITY APPLICATION 
     This application is a continuation of U.S. application Ser. No. 16/253,111, filed Jan. 21, 2019, which is a continuation of U.S. application Ser. No. 15/686,389, filed Aug. 25, 2017, now issued as U.S. Pat. No. 10,217,799, which is a divisional of U.S. application Ser. No. 15/056,548, filed Feb. 29, 2016, now issued as U.S. Pat. No. 9,773,841, which is continuation of U.S. application Ser. No. 13/838,579, filed Mar. 15, 2013, now issued as U.S. Pat. No. 9,276,011, all of which are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     Computers and other electronic systems, for example, digital televisions, digital cameras, and cellular phones, often have one or more memory and other devices to store information. Increasingly, memory and other devices are being reduced in size to achieve a higher density of storage capacity and/or a higher density of functionality. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  through  FIG. 1H  show various portions of a fabrication process to form strings of memory cells, according to an embodiment; 
         FIG. 2A  and  FIG. 2B  show various portions of a fabrication process to form strings of memory cells, according to an embodiment; and 
         FIG. 3  is a block diagram of a system embodiment, including a memory device according to various embodiments described herein. 
     
    
    
     DETAILED DESCRIPTION 
     The description that follows includes illustrative apparatuses (circuitry, devices, structures, systems, and the like) and methods (e.g., processes, protocols, sequences, techniques, and technologies) that embody the disclosed subject matter. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide an understanding of various embodiments of the subject matter. After reading this disclosure, it will be evident to person of ordinary skill in the art however, that various embodiments of the subject matter may be practiced without these specific details. Further, well-known apparatuses, methods, and operations have not been shown in detail so as not to obscure the description of various embodiments. 
     As used herein, the term “or” may be construed in an inclusive or exclusive sense. Additionally, although various embodiments discussed below focus on a three-dimensional (3D) NAND memory device, the embodiments are readily applicable to a number of other electronic devices. Consequently, the described embodiments are merely given for clarity in disclosure, and thus, are not limited to NAND memory devices or even to memory devices in general. 
     Generally, a 3D electronic device may be considered to be a device formed by a process that combines multiple levels of electronic devices (e.g., one device formed over another) using planar formations (e.g., multiple devices on a single level). Since multiple levels in 3D devices may use approximately the same area on a substrate, an overall density of devices (e.g., memory devices) can be increased in relation to the number of levels. Generally discussed herein are three-dimensional (3D) memories, memory cells, and methods of making and using the same. In one or more embodiments, a 3D vertical memory can include a memory stack sharing a common cell-pillar. A memory stack can include a stack of at least two memory cells and a dielectric between adjacent memory cells, where each memory cell includes a control gate (CG) and a charge storage structure, such as a floating gate (FG) or charge trap (CT), configured to store electrons or holes accumulated thereon. Information is represented by the amount of electrons or holes stored by the cell. 
     The methods and apparatuses discussed herein can be extended to NOR devices, microcontroller devices, other memory types, general purpose logic, and a host of other apparatuses. Various 3D devices including repeating devices (e.g., SRAM), transistors, standard CMOS logic, and so on may all benefit from application of the fabrication processes disclosed herein. 
     Prior art devices allowed a continuous cell pillar only from the source through the memory cells. However, a separate photolithography step caused a shoulder to be formed when the drain-side select gate (SGD) was later formed over the memory cells. The shoulder caused a pinch-point, thereby reducing current flow from source to a bitline formed over the SGD. 
     In various embodiments disclosed herein, a continuous cell pillar is formed substantially through all levels of the 3D devices. Therefore, the cell pillar (e.g., channel) is a continuous formation from at least the source-side select gate (SGS) to SGD. The continuous cell pillar improves current flow over prior art devices by, for example, removing polysilicon-to-polysilicon channel interfaces in between the SGD and the cell pillar and also between the SGS and the cell pillar, as well as eliminating structural offsets within the cell pillar formation of the prior art that limits the current path. Further, the disclosed subject matter reduces process steps and costs. In various embodiments, the channel-to-source interface may be defined by integrating a buffer polysilicon to a transition metal/semiconductor source (e.g., WSi x ) source or an etch stop formed using a high-dielectric constant (high-k) material. 
     Consequently, the disclosed subject matter eliminates certain photolithographic and registration operations and eliminates particular interface and critical dimension/registration offsets as found in the prior art in between, for example, the SGD, the SGS, and the cell-pillar. Further, the disclosed subject matter eliminates or reduces the number of chemical-mechanical planarization (CMP) steps for both the SGS and the cell pillar, reducing SG-to top and bottom access line (e.g., wordline) distances by approximately 50%. Further, an N+ buffer polysilicon may be utilized between the WSi x  source and the channel material forming an ohmic contact. 
       FIG. 1A  through  FIG. 1H  show various portions of a fabrication process to form strings of memory cells, according to an embodiment. As discussed above, the techniques and fabrication processes described herein can be extended to a number of different apparatuses (e.g., in addition to memory devices) to be fabricated using various processes, including, for example, a three-dimensional process. However, fabrication of a NAND memory device  100  will be described below to retain clarity and consistency in the discussions that follow. 
     In  FIG. 1A , initial formation of the NAND memory device includes forming a source material  101  having levels of various materials formed thereover including various dielectric materials and semiconductor materials as discussed in more detail below. Each of these and other materials described herein may be applied, deposited, or otherwise formed according to techniques and methods known independently in the art. The techniques and methods can include one or more deposition activities, such as chemical vapor deposition (CVD), atomic level deposition (ALD), physical vapor deposition (PVD), or other techniques. Forming multiple materials in various levels may be accomplished via stacked deposition operations. 
     Although the process acts and operations described herein may refer to particular conductor, semiconductor, or dielectric materials, such as silicon, silicon dioxide, silicon nitride, or others, a person of ordinary skill in the art and familiar with this disclosure will recognize that other conductor, semiconductor, and dielectric materials may be substituted and still be within a scope of the disclosed subject matter. Thus, the material choices and selections presented are merely provided as an aid in understanding one example of a fabrication process. 
     For example, various types of semiconductor materials, (e.g., single-crystal or amorphous silicon, germanium, other elemental semiconductor materials, compound semiconductor materials, etc.) may be used as an alternative for or in conjunction with other types of semiconductor material. Additionally, various types of dielectric materials, such as tantalum pentoxide (Ta 2 O 5 ), silicon nitride (Si x N y ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), and a variety of other organic or inorganic dielectric materials, may be used as an alternative to or in conjunction with others of the materials described. Also, various other combinations of materials may also be substituted or included. For example, in certain applications, described semiconductor materials may be substituted with conductor materials including, for example, silver (Ag), copper (Cu), Aluminum (Al), zinc (Zn), platinum (Pt), tungsten (W), titanium (Ti), or tantalum (Ta). 
     Further, various formation, process, and other discussions that follow may refer to one material placed, for example, “over” or “above” another material. Such descriptors are relative terms only and obviously depend upon an exact orientation of any resulting device. However, a person of ordinary skill in the art will readily understand the context of such relative terms upon reading and understanding the disclosure provided herein in conjunction with the respective drawings. 
     With continuing reference to  FIG. 1A , the source material  101  can include, for example, a conductively doped poly-silicon material or a conductively doped region of a semiconductor substrate. As referred to herein, a semiconductor substrate can be any of various types of substrates used in the semiconductor and allied industries, such as silicon wafers, other elemental semiconductor wafers, compound semiconductor wafers, thin film head assemblies, polyethylene-terephthalate (PET) films deposited or otherwise formed with a semiconducting material layer (followed by an annealing activity, such as excimer laser annealing (ELA) in some embodiments), as well as numerous other types of substrates known independently in the art. Also, in some embodiments, the source material  101  may be formed over a non-semiconductor material (e.g., quartz, ceramic, etc.), or vice-versa. Other embodiments for the source material  101  are discussed, below, with reference to  FIG. 2A . 
     A buffer material  103 A is formed over the source material  101  followed by an etch stop  105 A. The buffer material  103 A may be selected to be a conductive material, for example, a doped polysilicon. In a specific embodiment, the buffer material  103 A may be doped as an n-type polysilicon. In various embodiments, the etch stop  105 A may comprise a high dielectric constant (high-κ) material such as aluminum oxide (Al 2 O 3 ) or other high dielectric constant oxides. In other embodiments, one or more high-κ materials including, for example, hafnium silicate (HfSiO 4 ), zirconium silicate (ZrSiO 4 ), hafnium dioxide (HfO 2 ), and zirconium dioxide (ZrO 2 ) may be selected for the etch stop  105 A. Generally, a high dielectric constant material may be considered as any material having a dielectric constant equal or greater than the dielectric constant of silicon dioxide. The dielectric constant for silicon dioxide is approximately 3.9. 
     Formation of the etch stop  105 A is followed by formation of a source-side select gate (SGS) structure including a first dielectric material  107  (e.g., silicon dioxide, SiO 2 ), a semiconductor material  109  (e.g., conductively doped poly-silicon), and a second dielectric material  111  (e.g., SiO 2 ). 
     The first dielectric material  107  and the second dielectric material  111  may be of the same or different materials. Also, the first dielectric material  107  and the second dielectric material  111  may be formed from the same material but by different methods. For example, the first dielectric material  107  may comprise a thermally-grown silicon dioxide material and the second dielectric material  111  may comprise a deposited silicon dioxide material (or vice versa). As a person of ordinary skill in the art understands, there are certain optical, electrical, and other differences between these two types of formed silicon dioxides. Thus, the material choices and selections presented are merely provided as an aid in understanding one example of a fabrication process. 
     Depending upon an etchant used in later process steps, the semiconductor material  109  may be selected to be a p-type polysilicon (e.g., doped with boron). For example, as discussed in more detail below, a subsequent etch-back process step may employ tetramethyl-ammonium hydroxide (TMAH) as an etchant. TMAH selectively etches n-type and undoped polysilicon but only very slowly etches p-type polysilicon. Selecting the semiconductor material  109  to be p-type polysilicon reduces the amount of the semiconductor material  109  that is etched during a subsequent TMAH etch process. 
     Still continuing with  FIG. 1A , a number of alternating materials can be formed over the second dielectric material  111 . In various embodiments, forming the alternating materials begins a fabrication process to form vertical memory cells (e.g., a memory array). In other embodiments, forming the alternating materials begins a fabrication process to form other active device types. The number of alternating materials can be selected depending upon the application and device type desired. 
     The alternating materials comprise a number of additional dielectric materials  111  and a number of conductor materials  113 A. Each of the levels of the dielectric material  111  is separated from a respective adjacent one of the levels of the dielectric material  111  by at least a respective one of the levels of the conductor material  113 A. 
     Each of the additional dielectric materials  111  may comprise silicon dioxide or a number of other dielectric materials. In various embodiments, one or more of the additional dielectric materials  111  may comprise a solid electrolyte. The solid electrolyte may comprise a chalcogenide, for example, silver-doped germanium selenide (Ag—GeSe), silver-doped germanium sulfide (Ag—GeS 2 ), copper-doped germanium sulfide (Cu—GeS 2 ), or copper telluride (CuTe x ); or an oxide, e.g. a transition-metal oxide (e.g., ZrO x ), a semiconductor oxide (e.g., SiO x ), a rare earth oxide (e.g., YbO x ), another metal oxide (e.g., Al y O x ), or combinations thereof, (e.g., ZrSiO x ). In these embodiments, one or more of the memory cells in the memory array may comprise resistance change memory (RCM) cells. The RCM cells include the type of cell known as a conductive-bridging RAM (CBRAM) memory cell. An operation of the RCM is based on a voltage-driven ionic migration and electrochemical deposition of metal ions within a solid electrolyte. 
     The conductor materials  113 A may comprise conductively doped poly-silicon or a number of other conductor or semiconductor materials. Although each of the dielectric materials  111  and the conductor materials  113 A may be construed as being comprised of the same material on each level, respectively, various levels may comprise different materials. For example, a first level of the dielectric material  111  may comprise silicon dioxide while a later-formed second level of the dielectric material  111  may comprise tantalum pentoxide. Similarly, a first level of the conductor material  113 A may comprise conductively doped poly-silicon while a later-formed second level of the conductor material  113 A may comprise conductively-doped germanium, a doped compound-semiconductor material, or a metallic-ion donor such as silver. In a specific exemplary embodiment, the conductor material  113 A is a n-type polysilicon. 
     A drain-side select gate (SGD) comprising a semiconductor material  115  is formed over the alternating materials having the number of additional dielectric materials  111  and the number of conductor materials  113 A. As with the semiconductor material  109  and depending upon an etchant used in later process steps, the semiconductor material  115  may be selected to be a p-type polysilicon (e.g., polysilicon doped with boron or other elements from Group 13 of the periodic table). For example, as discussed in more detail below, a subsequent etch-back process step may employ TMAH as an etchant. TMAH selectively etches n-type and undoped polysilicon but only very slowly etches p-type polysilicon. In other embodiments, the semiconductor material  115  may be used for other types of active semiconductor switching devices. 
     A chemical-mechanical planarization (CMP) etch-stop material  117  may be formed over the semiconductor material  115  and comprises a relatively hard material to act as a stopping point for subsequent CMP processes. The CMP etch-stop material  117  may comprise one or more materials including dielectric materials such as various oxides, oxynitrides, or nitrides. 
     A cap material  119  is formed over the CMP etch-stop material  117  and provides protection for the underlying materials during subsequent process steps. The cap material  119  may comprise one more materials including oxides, nitrides, high-κ dielectric materials, polysilicon, and other materials independently known in the art. A hard-mask material  121  and a photoresist level  123  allow initial formation of a partial via, or shallow trench, for a subsequent pillar etch operation, discussed below. The hard-mask material  121  may comprise, for example, carbon with a dielectric anti-reflective coating. The cap material  119  and the hard-mask material  121  may be considered to be sacrificial materials provided to aid in subsequent formation steps. After the hard-mask material  121  is patterned and opened for the subsequent pillar etch operation, the photoresist level  123  may be removed. 
     Table I, below, shows a specific exemplary embodiment of various dimensions (e.g., thicknesses) of the various materials discussed above. A person of ordinary skill in the art will recognize that dimensions and relative dimensional ratios, other than those shown, may function for various device types. However, the dimensions given are provided simply as an aid in understanding the various embodiments discussed herein and should not be considered as the only workable, or even preferable, dimensions. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                 Material Level 
                 Element Number 
                 Dimension (nm) 
               
               
                   
                   
               
             
            
               
                   
                 Source Material 
                 101 
                 50 to 200 
               
               
                   
                 Buffer Material 
                 103A 
                  30 
               
               
                   
                 Etch Stop 
                 105A 
                 20 to 50 
               
               
                   
                 First Dielectric Material 
                 107 
                 20 to 50 
               
               
                   
                 Semiconductor Material 
                 109 
                 100 to 300 
               
               
                   
                 Dielectric Material 
                 111 
                  20 
               
               
                   
                 Conductor Material 
                 113A 
                  30 
               
               
                   
                 Semiconductor Material 
                 115 
                 100 to 300 
               
               
                   
                 CMP Etch-Stop Material 
                 117 
                 10 to 20 
               
               
                   
                 Cap Material 
                 119 
                 200 
               
               
                   
                   
               
            
           
         
       
     
     Referring now to  FIG. 1B , formation of the NAND memory device  100  continues with formation of a pillar opening  110 . The pillar opening  110  is performed in preparation for a subsequent channel formation, discussed below, and may be etched or otherwise formed to be a partial via of various shapes or a trench. For example, in various embodiments, the pillar opening  110  is a trench. In other embodiments, the pillar opening  110  may be comprised of geometries other than a trench. However, for ease in understanding fabrication operations of the disclosed subject matter discussed herein, the pillar opening  110  can be considered to be an opening (e.g., an aperture) formed at least partially through the various materials discussed above. 
     In a specific embodiment, the pillar opening  110  can be formed by an anisotropic dry etch process (e.g., reactive ion etch (RIE) or plasma etch). In other embodiments, depending upon materials selected, the pillar opening  110  may be formed by one or more various types of chemical etchants (e.g., such as potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH)), mechanical techniques, other types of ion milling, or laser ablation techniques. Related industries such as those involved in constructing micro-electrical mechanical systems (MEMS) devices may independently supply techniques for still further means to form the pillar opening  110 . 
     The etch stop  105 A of  FIG. 1A  allows the pillar opening  110  to be formed in a single step, unlike the prior art that requires a separate formation and etch of the SGD pillar as discussed above. As disclosed herein, formation of the pillar opening  110  provides a single continuous opening for later formation of channel material. As shown in  FIG. 1B , formation of the pillar opening  110  may etch partially into the etch stop  105 A ( FIG. 1A ), forming an etch stop  105 B that is at least partially-opened. In a specific exemplary embodiment, an aspect ratio of the overall height of the pillar opening  110  to the width of the opening may be up to 35:1 or more. 
     In  FIG. 1C , the hard-mask material  121  may be removed. The conductor materials  113 A ( FIG. 1A  and  FIG. 1B ) are recessed during a control-gate recess operation by etching or otherwise have portions removed laterally (forming a recess away from the sidewall of the pillar opening  110 ). The control-gate recess operation forms a number of control gates  113 B from the conductor material  113 A of  FIG. 1A , thereby forming a recessed pillar opening  120 . An isotropic etchant with a relatively high selectivity ratio may be used to form the recesses of the control gates  113 B. 
     In a specific embodiment, TMAH may be used to form the recesses. TMAH has approximately a 6:1 selectivity ratio based on its ability to etch n-type polysilicon approximately six times faster than p-type polysilicon or dielectric materials. Consequently, due to the high selectivity ratio of TMAH, the n-type polysilicon of the control gates  113 B is laterally etched faster than the p-type polysilicon of the semiconductor material  109 ,  115  or the dielectric materials  107 ,  111 ,  119 . Although the recessed pillar opening  120  is described as being performed using TMAH as an isotropic etch, a skilled artisan will recognize that other types of chemical and/or mechanical etch or formation processes may be used with an appropriate material selection. For example, other isotropic etchants may also be employed such as a hydrofluoric/nitric/acetic (HNA) acid chemical etchant. 
     During the TMAH etch operation and potential subsequent cleaning steps, the etch stop  105 B is opened to the underlying buffer material  103 A ( FIG. 1B ) that may be at least partially etched to form buffer material  103 B ( FIG. 1C ). Since the buffer material  103 B is a conductive material (e.g., n-type polysilicon), the recessed pillar opening  120  allows a subsequently formed channel to be in electrical communication with the source material  101 . 
     With reference now to  FIG. 1D , an inter-polysilicon dielectric (IPD) material  125 A, (e.g., a charge blocking dielectric (CBD) material), is formed on the sidewalls of the recessed pillar opening  120  of  FIG. 1C , followed by a charge-storage material  127 A being formed adjacent to the IPD material  125 A. As indicated in  FIG. 1D , the IPD material  125 A and the charge-storage material  127 A are primarily or entirely formed on opposing faces of the recessed pillar opening  120  ( FIG. 1C ). The formation of the IPD material  125 A and the charge-storage material  127 A results in a pillar opening  130  that is temporarily reduced in size from the various pillar openings discussed above. 
     The IPD material  125 A may comprise one or more of the various dielectric materials discussed herein, including various high-κ dielectric materials. In various embodiments, the IPD material  125 A may comprise an oxide-nitride-oxide (ONO) material. The charge-storage material  127 A may comprise one or more of the semiconductor materials discussed herein. For example, in various embodiments, the charge-storage material  127 A comprises polysilicon. In various embodiments, the charge-storage material  127 A comprises silicon nitride (e.g., Si 3 N 4 ). 
     In  FIG. 1E , an etch process substantially removes excess amounts of the IPD material  125 A and charge-storage material  127 A from sidewalls and bottom of the pillar opening  130  of  FIG. 1D , forming a cleared pillar opening  140  and leaving a number of charge-storage structures  127 B electrically separated from at least proximate (e.g., adjacent) ones of the control gates  113 B by a partially surrounding IPD material  125 B. Techniques to remove the materials from the pillar opening  130  are known independently in the art. 
     For example, the charge-storage material  127 A may be at least partially removed from the pillar opening  130 , and remaining portions of the charge-storage structures  127 B may be left in the recesses. In various embodiments, the charge-storage structures  127 B may be used to form floating gates or charge traps. Portions of the charge-storage material  127 A can be removed using a Certas™ (e.g., a vapor ammonia), an ammonium fluoride and nitric acid mix (NH4F—HNO3), an ozone (O3) or hydrofluoric acid (HF) mix or cycle (e.g., exposed surfaces can be exposed to ozone to create oxide (e.g., oxidize) the surface and the oxidized surface can be exposed to hydrofluoric acid to remove the oxide), hydrofluoric acid and nitric acid mix (HF—HNO3), hydrofluoric acid and hydrogen peroxide mix (HF—H2O2) or a TMAH process. The process used to remove portions of the charge-storage material  127 A can be selected as a function of the doping of the charge-storage material  127 A. For example, if the charge-storage material  127 A is n-type polysilicon, the TMAH process can be used to remove the portions of the charge-storage material  127 A. 
     In  FIG. 1F , a tunneling material  129  is formed on sidewalls and bottom within the cleared pillar opening  140  ( FIG. 1E ), followed by formation of a sacrificial liner  131 A. The tunneling material  129  may comprise one or more of the dielectric materials discussed herein. The sacrificial liner  131 A protects the tunneling material  129  from a subsequent punch-etch operation. 
     The tunneling material  129  may be formed from a number of dielectric materials discussed herein that allow for Fowler-Nordheim tunneling of electrons or direct tunneling of holes or other injection mechanisms. For example, in various embodiments, the tunneling material  129  comprises deposited and/or thermally-grown silicon dioxide. 
     In various embodiments, the sacrificial liner  131 A may comprise polysilicon. In other embodiments, if the tunneling material is a thermally-grown silicon dioxide, the sacrificial liner  131 A may comprise a deposited silicon dioxide that can be chemically removed with a buffered-oxide etchant (BOE), such as such as a combination of ammonium fluoride (NH 4 F) and hydrofluoric acid (HF) that readily etches materials such as silicon dioxide, but has little affect on materials such as polysilicon. In other embodiments, the sacrificial liner  131 A may comprise the same material as the conductor material  113 A, and is removed using an isotropic etchant, such as a directional RIE or plasma etch. In still other embodiments, the sacrificial liner  131 A may comprise another dielectric such as borophosphosilicate glass (BPSG) supplied from a tetraethoxysilane (TEOS) source. In still other embodiments, the sacrificial liner  131 A may comprise a solvent-based liquid that is applied to substrates using a spin-coat process, such as photoresist. The use and application of these various materials will be understood by a person of ordinary skill in the art upon reading and understanding the disclosure provided herein. 
     Referring now to  FIG. 1G , sacrificial liner portions  131 B is formed by, for example, a punch-etch operation that clears at least the bottom portion of the sacrificial liner  131 A ( FIG. 1F ) and the tunneling material  129  opening the pillar opening to the source material  101 . The cap material  119  may optionally be removed by the punch-etch operation. 
     In  FIG. 1H , any remaining sacrificial liner portions  131 B ( FIG. 1G ) nary be removed and the cleared pillar opening  140  may be filled with a channel-fill material  133  comprising, for example, poly-silicon or other semiconductor material. In various embodiments, the channel-fill material  133  may comprise any one or more of the elemental or compound semiconductor materials discussed above. The channel-fill material  133  may also comprise any of a number of types of single-crystal or amorphous semiconductor materials. For example, the channel-fill material  133  may comprise an epitaxial deposition of silicon, other elemental semiconductor, or compound semiconductor. In other examples, the channel-fill material  133  may comprise a polysilicon material (e.g., a conductively doped polysilicon material) formed by, for example, thermal decomposition or pyrolysis of silane such as a low-pressure chemical vapor deposition (LPCVD) process. Other techniques known independently in the art, such as DC sputtering, followed by a post-anneal activity in some embodiments, may also be utilized. 
     Although not shown explicitly in  FIG. 1H , the cap material  119  may be removed (e.g., if it has not already been removed in a prior process (e.g., an etch step) before the process associated with  FIG. 1H ). The channel-fill material  133  may then be planarized (e.g., using a chemical-mechanical planarization (CMP) technique) so that the upper surface of the channel-fill material  133  is substantially coplanar with an upper surface of the CMP etch-stop material  117 . 
     With reference now to  FIG. 2A  and  FIG. 2B , various portions of a fabrication process to form strings of memory cells or other electronic devices, are shown according to an embodiment. The NAND memory device structure  200  of  FIG. 2A  and  FIG. 2B  is similar to the NAND memory device  100  of  FIG. 1A  through  FIG. 1H . However, the etch stop  105 A ( FIG. 1A ) comprising, for example, a high-κ dielectric material, may no longer be required as an etch stop for formation of the pillar opening  110  ( FIG. 1B ). As indicated above, the etch stop  105 A of  FIG. 1A  allows the pillar opening  110  to be formed in a single step. 
     Instead of the etch stop  105 A, a source material  201  is selected to include a transition metal that may be combined with a semiconductor material, forming, for example, an inorganic compound. In a specific exemplary embodiment, tungsten disilicide (WSi 2 ), or more generally, tungsten suicide (WSi x ) may be formed for the source material  201  from, for example, using source gases of tungsten hexafluoride (WF 6 ) and monosilane (SiH 4 ) or dichlorosilane (H 2 SiCl 2 ) in a chemical vapor deposition (CVD) process. The resulting WSi x  film may subsequently be annealed to form a more conductive, stoichiometric form. In this example, the WSi x  film used to form the source material  201  is a relatively hard material and thus forms an etch stop. 
       FIG. 2B  shows the channel-fill material  133  added to the NAND memory structure  200 . As with the NAND memory device  100  of  FIG. 1H , a resulting cell pillar formed from the channel-fill material  133  is continuous from the semiconductor material  115  to the source material  201  (or the source material  101  in  FIG. 1H ). In a specific exemplary embodiment where NAND memory devices are formed using the disclosed subject matter, the cell pillar is continuous and formed in a single-process operation from the SGD to the source. 
       FIG. 3  is a block diagram of a system  300  with a memory device that may include one or more of the various embodiments described herein. The system  300  is shown to include a controller  303 , an input/output (I/O) device  311  (e.g., a keypad, a touchscreen, or a display), a memory device  309 , a wireless interface  307 , a static random access memory (SRAM) device  301 , and a shift register  315 , each coupled to one another via a bus  313 . A battery  305  may supply power to the system  300  in one embodiment. The memory device  309  may include a NAND memory, a flash memory, a NOR memory, a combination of these, or the like. The memory device  309  may include one or more of the novel devices and structures described herein. 
     The controller  303  may include, for example, one or more microprocessors, digital signal processors, micro-controllers, or the like. The memory device  309  may be used to store information transmitted to or by the system  300 . The memory device  309  may optionally also be used to store information in the form of instructions that are executed by the controller  303  during operation of the system  300  and may be used to store information in the form of user data either generated, collected, or received by the system  300  (such as image data). The instructions may be stored as digital information and the user data, as disclosed herein, may be stored in one section of the memory as digital information and in another section as analog information. As another example, a given section at one time may be labeled to store digital information and then later may be reallocated and reconfigured to store analog information. The controller  303  may include one or more of the novel devices and structures described herein. 
     The I/O device  311  may be used to generate information. The system  300  may use the wireless interface  307  to transmit and receive information to and from a wireless communication network with a radio frequency (RE) signal. Examples of the wireless interface  307  may include an antenna, or a wireless transceiver, such as a dipole antenna. However, the scope of the inventive subject matter is not limited in this respect. Also, the I/O device  311  may deliver a signal reflecting what is stored as either a digital output (if digital information was stored), or as an analog output (if analog information was stored). While an example in a wireless application is provided above, embodiments of the inventive subject matter disclosed herein may also be used in non-wireless applications as well. The I/O device  311  may include one or more of the novel devices and structures described herein. 
     The various illustrations of the procedures and apparatuses are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of the apparatuses and methods that might make use of the structures, features, and materials described herein. Based upon a reading and understanding of the disclosed subject matter provided herein, a person of ordinary skill in the art can readily envision other combinations and permutations of the various embodiments. The additional combinations and permutations are all within a scope of the present invention. 
     The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. The abstract is submitted with the understanding that it will not be used to interpret or limit the claims. In addition, in the foregoing Detailed Description, it may be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as limiting the claims. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.