Patent Publication Number: US-2023164928-A1

Title: Flexible circuit board and manufacturing method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of U.S. provisional application Ser. No. 63/281,085, filed on Nov. 19, 2021, and Taiwan application serial no. 111131699, filed on Aug. 23, 2022. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     Technical Field 
     The disclosure relates to a circuit board and a manufacturing method thereof, and in particular to a flexible circuit board and a manufacturing method thereof. 
     Description of Related Art 
     With the advancement of technology, various electronic products are developing towards the trend of being light, thin, short, and small, and flexible electronic products (for example, display devices, wearable devices, communication equipment, etc.) are gradually applied in daily life. At present, the flexible circuit boards applied in the flexible electronic products are usually formed by alternately stacking polyimide layers and copper layers. Since the polyimide layers are not easy to combine with the copper layers, the polyimide layers and the copper layers generally need to be bonded though an adhesive, such that the overall thickness of the flexible circuit board may not be easily reduced. In addition, at present, the circuit layer of the flexible circuit board is manufactured through a subtractive method, such that the line width is greater, which may not be beneficial to the manufacture of a thin circuit or a high-density circuit. 
     SUMMARY 
     The disclosure provides a flexible circuit board and a manufacturing method thereof, which can form a flexible circuit board with the design of a high-density circuit, and the overall thickness of the flexible circuit board is significantly reduced. 
     The flexible circuit board of the disclosure includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young&#39;s modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure. 
     In an embodiment of the disclosure, an elongation of the insulating layers is greater than 20%. 
     In an embodiment of the disclosure, the circuit structure has a conductive through hole. The first cover layer and the second cover layer respectively expose two ends of the conductive through hole. 
     In an embodiment of the disclosure, the conductive through hole includes a first opening, a second opening, and a part of the circuit layer plated on sidewalls of the first opening and the second opening. The first opening and the second opening overlap in a direction perpendicular to the top surface. 
     In an embodiment of the disclosure, the circuit layers include a first circuit layer, a second circuit layer, and a third circuit layer. The first circuit layer is close to the bottom surface of the circuit structure. The second circuit layer is disposed on the first circuit layer. The third circuit layer is disposed on the second circuit layer and is close to the top surface of the circuit structure. The insulating layers include a first insulating layer and a second insulating layer. The first insulating layer is disposed between the first circuit layer and the second circuit layer. The second insulating layer is disposed between the second circuit layer and the third circuit layer. 
     In an embodiment of the disclosure, a bottom end of the conductive through hole is flush with a bottom surface of the first insulating layer. 
     In an embodiment of the disclosure, the first opening penetrates the first insulating layer and the first circuit layer, and the second circuit layer extends to the sidewall of the first opening to be electrically connected to the first circuit layer. The second opening penetrates the second insulating layer, and the third circuit layer extends to the sidewall of the second opening to be electrically connected to the second circuit layer. 
     In an embodiment of the disclosure, the second opening exposes a part of the second circuit layer. 
     In an embodiment of the disclosure, a bottom surface of the first circuit layer is flush with a part of a bottom surface of the first insulating layer and a bottom surface of the second circuit layer. 
     In an embodiment of the disclosure, a number of the circuit layers is between 3 and 10 layers. 
     In an embodiment of the disclosure, there is no adhesive layer between the adjacent circuit layers and insulating layers. 
     The manufacturing method of the flexible circuit board of the disclosure includes the following steps. A carrier is provided. A circuit structure is formed on the carrier. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material, and a Young&#39;s modulus of the insulating layers is between 0.36 GPa and 8 GPa. A first cover layer is formed on the circuit structure. The carrier is removed. Then, a second cover layer is formed on one side of the circuit structure opposite to the first cover layer. 
     In an embodiment of the disclosure, the step of forming the circuit structure on the carrier includes forming a first circuit layer on the carrier. A first insulating layer is formed on the first circuit layer. A first opening is formed to penetrate the first insulating layer. A second circuit layer is formed on the first insulating layer and extended to a sidewall of the first opening to be electrically connected to the first circuit layer. A second insulating layer is formed on the second circuit layer. A second opening is formed to penetrate the second insulating layer, and the second opening overlaps with the first opening. A third circuit layer is formed on the second insulating layer and extended to a sidewall of the second opening to be electrically connected to the second circuit layer. 
     In an embodiment of the disclosure, an aperture of the second opening is greater than or equal to an aperture of the first opening. 
     In an embodiment of the disclosure, there is no adhesive layer between the first circuit layer and the first insulating layer and between the second circuit layer and the second insulating layer. 
     In an embodiment of the disclosure, a method for forming the first circuit layer, the second circuit layer, or the third circuit layer is a semi-additive process. 
     In an embodiment of the disclosure, a method for forming the first opening or the second opening includes a lithography etching process. 
     Based on the above, the flexible circuit board of the disclosure includes the circuit layers and the insulating layers stacked alternately. The material of the insulating layer is a photosensitive dielectric material and has a Young&#39;s modulus of 0.36 GPa to 8 GPa. Therefore, the insulating layer can have good flexibility and good adhesion with the circuit layer without using an additional adhesive between the insulating layer and the circuit layer, thereby reducing the overall thickness of the flexible circuit board, which facilitates the miniaturization of product when subsequently applied to an electronic product. In addition, since the circuit layer is formed through the semi-additive process, and the opening or the blind via of the insulating layer may be formed through the lithography process, the high-density wiring design of the circuit structure can be performed, thereby reducing the overall size of the flexible circuit board. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a schematic cross-sectional view of a flexible circuit board according to an embodiment of the disclosure. 
         FIG.  1 B  is a partially enlarged schematic cross-sectional view of a region R in  FIG.  1 A . 
         FIG.  2 A  to  FIG.  2 G  are schematic cross-sectional views of a manufacturing process of a flexible circuit board according to an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS 
       FIG.  1 A  is a schematic cross-sectional view of a flexible circuit board according to an embodiment of the disclosure.  FIG.  1 B  is a partially enlarged schematic cross-sectional view of a region R in  FIG.  1 A . 
     Please refer to  FIG.  1 A  and  FIG.  1 B . A flexible circuit board  10  includes a circuit structure  100 , a first cover layer  130 , and a second cover layer  140 . 
     The circuit structure  100  has a top surface  100   a  and a bottom surface  100   b  opposite to the top surface  100   a . The circuit structure  100  includes multiple circuit layers  110  and multiple insulating layers  120  stacked alternately. For example, the circuit layers  110  may include a first circuit layer  112 , a second circuit layer  114 , and a third circuit layer  116 , and the insulating layers  120  may include a first insulating layer  122  and a second insulating layer  124 . The first circuit layer  112  is close to the bottom surface  100   b  of the circuit structure  100 . The second circuit layer  114  is disposed on the first circuit layer  112 , and the first insulating layer  122  is disposed between the first circuit layer  112  and the second circuit layer  114 . In some embodiments, a part of the second circuit layer  114  may penetrate the first insulating layer  122  to be electrically connected to the first circuit layer  112 . The third circuit layer  116  is disposed on the second circuit layer  114 , and the second insulating layer  124  is disposed between the second circuit layer  114  and the third circuit layer  116 . In some embodiments, a part of the third circuit layer  116  may penetrate the second insulating layer  124  to be electrically connected to the second circuit layer  114 . The third circuit layer  116  is close to the top surface  100   a  of the circuit structure  100 . In some embodiments, a top surface of the third circuit layer  116  may be regarded as the top surface  100   a  of the circuit structure  100 . 
     The embodiment schematically shows three layers of the circuit layers  110  and two layers of the insulating layers  120 , but is not intended to limit the disclosure. The number of layers of the circuit layers and the insulating layers and the wiring design of the circuit layers may be adjusted according to actual requirements. In some embodiments, the number of layers of the circuit layers  110  may be between 3 and 10 layers, which is beneficial to the volume reduction of the flexible circuit board. 
     The material of the circuit layer  110  may include copper, silver, gold, an alloy of the above materials, or other suitable metal materials. The material of the insulating layer  120  may be a photosensitive dielectric material and the Young&#39;s modulus thereof is between 0.36 GPa and 8 GPa. In this way, the insulating layer  120  can have good flexibility and good adhesion with the circuit layer  110 , and it is not necessary to provide an adhesive layer between the insulating layer  120  and the circuit layer  110 , thereby reducing the overall thickness of the flexible circuit board. In other words, the adjacent circuit layer  110  and insulating layer  120  may be in direct contact without the adhesive layer. 
     In some embodiments, the thicknesses of the circuit layers  110  (for example, a thickness T 1  of the first circuit layer  112 , a thickness T 2  of the second circuit layer  114 , and a thickness T 3  of the third circuit layer  116 ) may be between 2 μm and 8 μm. 
     In some embodiments, the thicknesses of the insulating layers  120  (for example, a thickness T 4  of the first insulating layer  122  and a thickness T 5  of the second insulating layer  124 ) may be between 2 μm and 8 μm. 
     In some embodiments, the elongation of the insulating layer  120  is greater than 20% to have good flexibility and bendability. 
     The first cover layer  130  is disposed on the top surface  100   a  of the circuit structure  100 , and the second cover layer  140  is disposed on the bottom surface  100   b  of the circuit structure  100 . The materials of the first cover layer  130  and the second cover layer  140  may include polyimide, photosensitive cover materials, or other suitable materials. In some embodiments, the Young&#39;s moduli of the first cover layer  130  and the second cover layer  140  may be between 0.3 GPa and 3.0 GPa. The first cover layer  130  and the second cover layer  140  have bending resistance to protect the circuit structure  100  from being scratched or polluted by moisture, dust, etc. and provide support for the circuit structure  100 . 
     In some embodiments, a thickness T 6  of the first cover layer  130  and a thickness T 7  of the second cover layer  140  may be between 20 μm and 50 μm. 
     In some embodiments, the circuit structure  100  has a conductive through hole TH, and the first cover layer  130  and the second cover layer  140  may respectively expose two ends of the conductive through hole TH. In this way, electronic elements (not shown) disposed on the top surface  100   a  and the bottom surface  100   b  of the circuit structure  100  may be directly conducted through the conductive through hole TH to eliminate additional wiring design, so that the electronic elements are easily assembled on the flexible circuit board  10  and the thickness of the circuit structure  100  or the flexible circuit board  10  is reduced. 
     In some embodiments, the aperture of the conductive through hole TH may be between 15 μm and 25 μm. 
     In some embodiments, as shown in  FIG.  1 B , the conductive through hole TH may include a first opening OP 1 , a second opening OP 2 , and a part of the circuit layer  110  plated on sidewalls of the first opening OP 1  and the second opening OP 2 , and the first opening OP 1  and the second opening OP 2  overlap in a direction perpendicular to the first surface  100   a . For example, the first opening OP 1  may penetrate the first insulating layer  122  and the first circuit layer  112 , that is, the first opening OP 1  may be defined by an inner side wall s 1  of the first insulating layer  122  and an inner side wall s 2  of the first circuit layer  112 . The second circuit layer  114  may extend to the sidewall of the first opening OP 1  (that is, the inner side wall s 1  of the first insulating layer  122  and the inner side wall s 2  of the first circuit layer  112 ) to be electrically connected to the first circuit layer  112 . The second opening OP 2  may penetrate the second insulating layer  124 , and the position of the second opening OP 2  corresponds to the position of the first opening OP 1 . In other words, the second opening OP 2  may be defined by an inner side wall s 3  of the second insulating layer  124 , and the first opening OP 1  and the second opening OP 2  are communicated with each other. The third circuit layer  116  may extend to the sidewall of the second opening OP 2  to be electrically connected to the second circuit layer  114 . 
     In some embodiments, the aperture of the second opening OP 2  may be slightly greater than the aperture of the first opening OP 1 , but the disclosure is not limited thereto. In other embodiments, the aperture of the first opening OP 1  and the aperture of the second opening OP 2  may be equal. 
     In some embodiments, the first circuit layer  112  may include a first seed layer  112   a  and a first plating layer  112   b  disposed on the first seed layer  112   a . The second circuit layer  114  may include a second seed layer  114   a  and a second plating layer  114   b  disposed on the second seed layer  114   a . The third circuit layer  116  may include a third seed layer  116   a  and a third plating layer  116   b  disposed on the third seed layer  116   a.    
     In some embodiments, a bottom surface b 1  of the first circuit layer  112 , a part of a bottom surface b 2  of the first insulating layer  122 , and a part of a bottom surface b 3  of the second circuit layer  114  are flush with each other. In other words, a bottom end of the conductive through hole TH (that is, the bottom surface b 3  of the second circuit layer  114 ) is flush with the bottom surface b 2  of the first insulating layer  122  and a part of the bottom surface b 3  of the second circuit layer  114 , that is, the bottom end of the conductive through hole TH is coplanar with the bottom surface b 2  of the first insulating layer  122  and a part of the bottom surface b 3  of the second circuit layer  114 . 
     In some embodiments, a part of the bottom surface b 1  of the first circuit layer  112 , a part of the bottom surface b 2  of the first insulating layer  122 , and a part of the bottom surface b 3  of the second circuit layer  114  may constitute the bottom surface  100   b  of the circuit structure  100 . 
     In some embodiments, first cover layer  130  includes third opening OP 3 , and second cover layer  140  includes fourth opening OP 4 . The third opening OP 3  and the fourth opening OP 4  overlap with the conductive through hole TH, and the aperture of the third opening OP 3  and the aperture of the fourth opening OP 4  are respectively greater than the maximum aperture of the conductive through hole TH. 
     In some embodiments, the first cover layer  130  further includes a fifth opening OP 5  to expose a part of the third plating layer  116   b  of the third circuit layer  116 . In some embodiments, the second cover layer  140  further includes a sixth opening OP 6  to expose a part of the first seed layer  112   a  of the first circuit layer  112 . 
     In some embodiments, a thickness T of the flexible circuit board  10  may be between 60 μm and 100 μm. 
       FIG.  2 A  to  FIG.  2 G  are schematic cross-sectional views of a manufacturing process of a flexible circuit board according to an embodiment of the disclosure. It must be noted here that the embodiment of  FIG.  2 A  to  FIG.  2 G  continues to use the reference numerals and some content of the embodiment of  FIG.  1 A  and  FIG.  1 B , wherein the same or similar reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, which will not be repeated here. 
     Please refer to  FIG.  2 A . A carrier  101  is provided. The carrier  101  may be glass, steel plate, or other suitable materials, and the disclosure is not limited thereto, as long as the carrier  101  can carry a structure formed thereon or a component disposed thereon. Then, a release layer  102  may be formed on the carrier  101 , so that the carrier  101  may be separated from a film layer formed in the subsequent process steps by the release layer  102 . In some embodiments, the release layer  102  is composed of, for example, a material with weak adhesion. In other embodiments, the adhesion of the material constituting the release layer may be reduced by a thermal process, an ultraviolet (UV) process, a laser process, or other similar processes. 
     Please refer to  FIG.  2 A  to  FIG.  2 E . The circuit structure  100  is formed on the carrier  101 . In detail, first, as shown in  FIG.  2 A , the first circuit layer  112  may be formed on the carrier  101 . The first circuit layer  112  may be formed through a semi-additive process. For example, through sputtering, the first seed layer  112   a  may be first formed on the release layer  102 , a patterned photoresist layer (not shown) is then formed on the first seed layer  112   a  to expose the first seed layer  112   a  of a corresponding circuit pattern, and the first plating layer  112   b  is then formed on the exposed first seed layer  112   a  using electroplating. After that, the patterned photoresist layer and the first seed layer  112   a  located under the patterned photoresist layer are removed to form the first circuit layer  112 , wherein the first circuit layer  112  may include an opening OP 1 ′ to expose a part of the release layer  102 . 
     Please refer to  FIG.  2 B . The first insulating layer  122  is formed on the first circuit layer  112 , and the first opening OP 1  is formed to penetrate the first insulating layer  122 . For example, the first insulating layer  122  may be formed through blade coating, spin coating, or other suitable processes, and an opening OP 1 ″ and a blind via V 1  may be then formed in the first insulating layer  122 . Since the material of the first insulating layer  122  is a photosensitive dielectric material, the opening OP 1 ″ and the blind via V 1  may be formed through a lithography etching process. For example, a photomask (not shown) may be used as a mask to cure a part of the photosensitive dielectric material by photopolymerization and/or baking. In addition, after curing the part of the photosensitive dielectric material, the remaining uncured photosensitive dielectric material may be removed by wet cleaning or other suitable manners to form the first insulating layer  122  including the opening OP 1 ″ and the blind via V 1 . The first opening OP 1  may be composed of the opening OP  1 ′ of the first circuit layer  112  and the opening OP 1 ″ of the first insulating layer  122 , the position of the opening OP 1 ″ corresponds to the opening OP 1 ′, and the opening OP 1 ″ and the opening OP 1 ′ are communicated with each other. In some embodiments, the blind via V 1  may expose a part of the first circuit layer  112 . 
     In some embodiments, the apertures of the opening OP 1 ″ and the blind via V 1  may be between 15 μm and 25 μm. Since the first opening OP 1  and the blind via V 1  of the first insulating layer  122  may be formed through a lithography process, a small aperture opening or blind via may be manufactured, which facilitates the formation of a high-density wiring design. 
     Please refer to  FIG.  2 C . The second circuit layer  114  is formed on the first insulating layer  122  and extends to the sidewall of the first opening OP 1  to be electrically connected to the first circuit layer  112 . For example, the second circuit layer  114  may be formed by a method similar to that of the first circuit layer  112 . In detail, through sputtering, the second seed layer  114   a  may be first formed on the first insulating layer  122  and the sidewall of the first opening OP 1 , a patterned photoresist layer (not shown) is then formed on the second seed layer  114   a  to expose the second seed layer  114   a  of a corresponding circuit pattern, and the second plating layer  114   b  is then formed on the exposed second seed layer  114   a  using electroplating. After that, the patterned photoresist layer and the second seed layer  114   a  located under the patterned photoresist layer are removed to form the second circuit layer  114 . 
     In some embodiments, the second circuit layer  114  may fill the blind via V 1  to be electrically connected to the first circuit layer  112 . 
     In some embodiments, the second seed layer  114   a  may also extend to the part of the release layer  102  exposed by the first opening OP 1 , but the disclosure is not limited thereto. 
     Please refer to  FIG.  2 D . The second insulating layer  124  is formed on the second circuit layer  114 , the second opening OP 2  is formed to penetrate the second insulating layer  124 , and the second opening OP 2  overlaps with the first opening OP 1 . For example, the second insulating layer  124  may be formed though blade coating, spin coating, or other suitable processes in a manner similar to that of the first insulating layer  122 . Then, the second opening OP 2  and a blind via V 2  may be formed in the second insulating layer  124 . Since the material of the second insulating layer  124  is a photosensitive dielectric material, the second opening OP 2  and the blind via V 2  may be formed through a lithography etching process. The manner for forming the second opening OP 2  and the blind via V 2  is similar to the manner for forming the opening OP 1 ″ and the blind via V 1 , so details are not repeated here. 
     In some embodiments, the blind via V 2  may expose a part of the second circuit layer  114 . 
     In some embodiments, the second opening OP 2  may expose a part of the second circuit layer  114  and the first opening OP 1 . 
     In some embodiments, the aperture of the second opening OP 2  may be slightly greater than the aperture of the first opening OP 1  to facilitate the alignment of the second opening OP 2  and the first opening OP 1  during the manufacturing process, but the disclosure is not limited thereto. In other embodiments, the aperture of the second opening OP 2  may be the same as the aperture of the first opening OP 1 . 
     In some embodiments, the apertures of the second opening OP 2  and the blind via V 2  may be between 15 μm and 20 μm. Since the second opening OP 2  and the blind via V 2  of the second insulating layer  124  may be formed through the lithography process, a small aperture opening or blind via may be manufactured, which facilitates the implementation of the high-density wiring design. 
     Please refer to  FIG.  2 E . The third circuit layer  116  is formed on the second insulating layer  124  and extends to the sidewall of the second opening OP 2  to be electrically connected to the second circuit layer  114 . For example, the third circuit layer  116  may be formed by a method similar to that of the first circuit layer  112 . In detail, through sputtering, the third seed layer  116   a  may be formed on the second insulating layer  124  and the sidewall of the second opening OP 2 , a patterned photoresist layer (not shown) is then formed on the third seed layer  116   a  to expose the third seed layer  116   a  of a corresponding circuit pattern, and the third plating layer  116   b  is then formed on the exposed third seed layer  116   a  using electroplating. After that, the patterned photoresist layer and the third seed layer  116   a  located under the patterned photoresist layer are removed to form the third circuit layer  114 . 
     In some embodiments, the third circuit layer  116  may fill the blind via V 2  to be electrically connected to the second circuit layer  114 . 
     In some embodiments, the third seed layer  116   a  may also extend to the part of the second circuit layer  114  exposed by the opening OP 2 , but the disclosure is not limited thereto. 
     Since the circuit layers (the first circuit layer  112 , the second circuit layer  114 , and the third circuit layer  116 ) of the embodiment are manufactured using the semi-additive process, a thin circuit may be manufactured. In some embodiments, the line width of the first circuit layer  112 , the line width of the second circuit layer  114 , and the line width of the third circuit layer  116  may be between 5 μm and 8 μm. 
     The manufacturing of the circuit structure  100  having three layers of the circuit layers and two layers of the insulating layers may be roughly completed via the above steps. However, the disclosure is not limited thereto, and the above steps may be repeated according to actual requirements to form a circuit structure having more layers of the circuit layers and the insulating layers. 
     In some embodiments, the second opening OP 2  with the sidewall plated with the third circuit layer  116  and the first opening OP 1  with the sidewall plated with the second circuit layer  114  may constitute the conductive through hole TH. In this way, an electronic element (not shown) subsequently disposed on one side of the circuit structure  100  may be directly connected to an electronic element (not shown) disposed on the other side of the circuit structure  100  through the conductive through hole TH to simplify the complicated wiring design of the circuit structure  100 , so that the assembly of the electronic elements is easy and the thickness of the circuit structure  100  is reduced. 
     Please refer to  FIG.  2 F . The first cover layer  130  is formed on the circuit structure  100 , wherein the first cover layer  130  includes the third opening OP 3  and the fifth opening OPS. For example, if the material of the first cover layer is a polyimide cover film, the third opening OP 3  and the fifth opening OP 5  may be formed by punching or drilling first, and the polyimide cover film is then disposed on the third circuit layer  116  and the second insulating layer  124  using an alignment bonding manner to form the first cover layer  130 . If the material of the first cover layer is a liquid photosensitive cover material, the liquid photosensitive cover material may be disposed on the third circuit layer  116  and the second insulating layer  124  through spin coating or blade coating, and a photomask (not shown) is then used as a mask to cure a part of the photosensitive cover material through photopolymerization and/or baking. After curing the part of the photosensitive cover material, the remaining uncured photosensitive cover material may be removed by wet cleaning or other suitable manners to form the first cover layer  130 . 
     Please refer to  FIG.  2 G . The carrier  101  is removed. For example, external energy may be applied to the release layer  102  by ultraviolet, laser, visible light, heat, or other manners, so as to reduce the adhesion of the release layer  102 , and the release layer  102  and the carrier  101  are then removed at the same time. In some embodiments, the carrier  101  may also be removed by mechanical stripping or other suitable removal processes, which is not limited in the disclosure. 
     Then, please refer to  FIG.  1 A . The second cover layer  140  is formed on one side of the circuit structure  100  opposite to the first cover layer  130 , wherein the second cover layer  140  includes the fourth opening OP 4  and the sixth opening OP 6 . The manner for forming the second cover layer  140  is similar to that of the first cover layer  130 . For example, if the material of the second cover layer  140  is a polyimide cover film, the fourth opening OP 4  and the sixth opening OP 6  may be formed by punching or drilling first, and the polyimide cover film is then disposed on the first circuit layer  112  and the first insulating layer  122  using an alignment bonding manner to form the second cover layer  140 . If the material of the second cover layer  140  is a liquid photosensitive cover material, the liquid photosensitive cover material may be disposed on the first circuit layer  112  and the first insulating layer  122  through spin coating or blade coating, and a photomask (not shown) is then used as a mask to cure a part of the photosensitive cover material through photopolymerization and/or baking. After curing the part of the photosensitive cover material, the remaining uncured photosensitive cover material may be removed by wet cleaning or other suitable manners to form the second cover layer  140 . 
     After the above process, the manufacturing of the flexible circuit board  10  may be substantially completed. 
     In summary, the flexible circuit board of the disclosure includes the circuit layers and the insulating layers stacked alternately. The material of the insulating layer is a photosensitive dielectric material and has a Young&#39;s modulus of 0.36 GPa to 8 GPa. Therefore, the insulating layer can have good flexibility and good adhesion with the circuit layer without using an additional adhesive between the insulating layer and the circuit layer, thereby reducing the overall thickness of the flexible circuit board, which facilitates the miniaturization of product when subsequently applied to an electronic product. In addition, since the circuit layer is formed through the semi-additive process, and the opening or the blind via of the insulating layer may be formed through the lithography process, the high-density wiring design of the circuit structure can be performed, thereby reducing the overall size of the flexible circuit board.