Patent Publication Number: US-2023135542-A1

Title: Constant voltage generation circuit

Description:
TECHNICAL FIELD 
     The invention disclosed in this specification relates to a constant voltage generation circuit. 
     BACKGROUND ART 
     Conventionally, as one type of a constant voltage generation circuit, an ED type constant voltage source is widely known, in which a depression type metal oxide semiconductor field effect transistor (NMOSFET) and an enhancement type NMOSFET are combined (see, for example, Patent Citation 1). 
     LIST OF CITATIONS 
     Patent Literature 
     
         
         Patent Citation 1: JP-A-2011-029912 
       
    
     SUMMARY OF THE INVENTION 
     Technical Problem 
     However, the conventional constant voltage generation circuit described above has room for improvement in output accuracy. 
     In view of the task described above found by the inventor of this application, it is an object of the invention disclosed in this specification to provide a constant voltage generation circuit that has high output accuracy. 
     Means for Solving the Problem 
     For instance, a constant voltage generation circuit disclosed in this specification includes a depression type first transistor and an enhancement type second transistor that constitute an ED type reference voltage source, and a resistor connected between gate and source of the first transistor. 
     Further for example, a constant voltage generation circuit disclosed in this specification includes a depression type first transistor and an enhancement type second transistor that constitute an ED type reference voltage source, and a depression type third transistor that is connected to a drain of the first transistor and has a larger W/L than the first transistor. 
     Note that other features, elements, steps, advantages, and characteristics of the present invention will become more apparent from the description of the embodiments given below and the related attached drawings. 
     Advantageous Effects of the Invention 
     According to the invention disclosed in this specification, a constant voltage generation circuit that has high output accuracy can be provided. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a diagram illustrating a comparative example of a constant voltage generation circuit. 
         FIG.  2    is a diagram illustrating a first embodiment of the constant voltage generation circuit. 
         FIG.  3    is a diagram illustrating a drain current variation suppression effect by adding a resistor. 
         FIG.  4    is a diagram illustrating a second embodiment of the constant voltage generation circuit. 
         FIG.  5    is a diagram illustrating a third embodiment of the constant voltage generation circuit. 
         FIG.  6    is a diagram illustrating a fourth embodiment of the constant voltage generation circuit. 
         FIG.  7    is a diagram illustrating a fifth embodiment of the constant voltage generation circuit. 
         FIG.  8    is a diagram illustrating a sixth embodiment of the constant voltage generation circuit. 
         FIG.  9    is a diagram illustrating Vds(M 1 )-Id characteristic and VIN-VREF characteristic. 
         FIG.  10    is a diagram illustrating a seventh embodiment of the constant voltage generation circuit. 
         FIG.  11    is a diagram illustrating drain current variation suppression effect by adding a transistor. 
         FIG.  12    is a diagram illustrating VIN-Vds(M 1 ) characteristic. 
         FIG.  13    is a diagram illustrating an eighth embodiment of the constant voltage generation circuit. 
         FIG.  14    is a diagram illustrating a ninth embodiment of the constant voltage generation circuit. 
         FIG.  15    is a diagram illustrating a tenth embodiment of the constant voltage generation circuit. 
         FIG.  16    is a diagram illustrating an eleventh embodiment of the constant voltage generation circuit. 
         FIG.  17    is a diagram illustrating a twelfth embodiment of the constant voltage generation circuit. 
         FIG.  18    is a diagram illustrating a thirteenth embodiment of the constant voltage generation circuit. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Comparative Example 
       FIG.  1    is a diagram illustrating a comparative example (an example of a basic structure to be compared with embodiments described later) of a constant voltage generation circuit. A constant voltage generation circuit  1  of this comparative example is a so-called ED type reference voltage source, which includes a depression type N-channel MOS field effect transistor M 1  and an enhancement type N-channel MOS field effect transistor M 2 . 
     Note that the depression type means one in which drain current flows even at a gate-source voltage of 0 V. In contrast, the enhancement type means one in which drain current does not flow at a gate-source voltage of 0 V. 
     The transistor M 1  has a drain connected to an application terminal of an input voltage VIN (e.g. 5 V). The transistor M 2  has a source and a backgate that are connected to a ground terminal (i.e. a reference potential terminal). The gate, source, and backgate of the transistor M 1 , and the gate and drain of the transistor M 2  are all connected to an output terminal of a constant voltage VREF. 
     In the constant voltage generation circuit  1  of this comparative example, the gate and source of the transistor M 1  are short-circuited to each other, and hence the transistor M 1  has a gate-source voltage Vgs(M 1 ) of 0 V. Therefore, the transistor M 1  functions as a constant current source that generate constant drain current Id, and constant bias current (i.e. the drain current Id of the transistor M 1 ) flows in the transistor M 2 . As a result, the constant voltage VREF corresponding to gate-source voltage Vgs(M 2 ) of the transistor M 2  is generated. 
     &lt;Consideration about Process Variation&gt; 
     It is known that ON threshold value voltage Vth(M 1 ) of the transistor M 1  is easily affected by process variation. For instance, if the ON threshold value voltage Vth(M 1 ) shifts to the negative side, the drain current Id becomes larger than standard value Id 0 , and hence the constant voltage VREF is deviated from a desired value. 
     In this way, a main factor of output variation in the constant voltage generation circuit  1  is a large shift of the drain current Id due to the process variation of the ON threshold value voltage Vth(M 1 ). 
     In the following description, in view of the above consideration, novel embodiments are proposed that can suppress variation of the drain current Id due to the process variation so that output accuracy of the constant voltage VREF can be improved. 
     First Embodiment 
       FIG.  2    is a diagram illustrating a first embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the comparative example ( FIG.  1   ) described above and further includes a resistor R 1 . 
     A first terminal of the resistor R 1  is connected to the source of the transistor M 1 . A second terminal of the resistor R 1  is connected to the gate and backgate of the transistor M 1  and the output terminal of the constant voltage VREF. In this way, the resistor R 1  is connected between the gate and source of the transistor M 1  and between the backgate and source of the transistor M 1 . 
     Note that it is preferred to use a base resistor having a positive temperature characteristic as the resistor R 1 , for example. However, the type of the resistor R 1  is not limited to this, but it may be possible to use a poly resistor having a negative temperature characteristic as the resistor R 1 , for example. 
       FIG.  3    is a diagram illustrating variation suppression effect of the drain current Id by adding the resistor R 1 . Note that the horizontal axis represents the gate-source voltage Vgs(M 1 ) of the transistor M 1 , while the vertical axis represents the drain current Id flowing in the transistor M 1 . 
     If the resistor R 1  is not disposed (corresponding to the comparative example described above), the gate-source voltage Vgs(M 1 ) of the transistor M 1  is 0 V. Therefore, if the ON threshold value voltage Vth(M 1 ) of the transistor M 1  shifts to the negative side, the drain current Id flowing in the transistor M 1  becomes larger than the standard value Id 0  (Id shifts from Id 0  to Id 1 ). 
     In contrast, if the resistor R 1  is connected to the source of the transistor M 1  (corresponding to the first embodiment), a potential difference (=Id×R 1 ) corresponding to the drain current Id is generated between both terminals of the resistor R 1 . 
     Therefore, the gate-source voltage Vgs(M 1 ) of the transistor M 1  is shifted to the negative side (Vgs(M 1 )=−Id×R 1 ). 
     In other words, when the ON threshold value voltage Vth(M 1 ) of the transistor M 1  shifts to the negative side, as the drain current Id increases more, the source potential of the transistor M 1  is raised more. Consequently, the gate-source voltage Vgs(M 1 ) of the transistor M 1  is shifted to the negative side more. As a result, ON resistance of the transistor M 1  is increased, and hence the increase of the drain current Id can be suppressed. 
     Note that if the drain current Id flowing in the transistor M 1  is 100 nA or more and less than 1 μA (e.g. 100 nA), the resistance of the resistor R 1  should be 100 ka or more and less than 1 MΩ (e.g. 100 kΩ), for example. With this element design, the shift amount of the gate-source voltage Vgs(M 1 ) can be set to approximately −100 mV (variation corresponding to the drain current Id). 
     In addition, it can be said that the resistor R 1  is connected between the source and the backgate of the transistor Mt. Therefore, corresponding to the drain current Id, a difference between the source potential and the backgate potential of the transistor M 1  is also generated, and hence a so-called body effect occurs. 
     Note that the above-mentioned body effect is one of device characteristics of a MOSFET, and means a phenomenon in which a voltage applied between source and backgate causes an increase of a depletion layer region of the MOSFET, so that the ON threshold value voltage varies. 
     For instance, when the ON threshold value voltage Vth(M 1 ) of the transistor M 1  shifts to the negative side, as the drain current Id increases more, the source potential of the transistor M 1  is raised more. Consequently, the above-mentioned body effect works so that the ON threshold value voltage Vth(M 1 ) of the transistor M 1  is shifted to the positive side, i.e., that the shift of the ON threshold value voltage Vth(M 1 ) to the negative side is suppressed. As a result, the ON resistance of the transistor M 1  is increased, and hence the increase of the drain current Id can be suppressed. 
     In this way, in the constant voltage generation circuit  1  of this embodiment, when the drain current Id increases, both the negative side shift effect of the gate-source voltage Vgs(M 1 ) and the positive side shift effect (i.e. the body effect) of the ON threshold value voltage Vth(M 1 ) work due to the insertion of the resistor R 1 . Therefore, an increase of the drain current Id can be suppressed (Id shifts from Id 1  to Id 2 ), output accuracy of the constant voltage VREF can be improved, and further temperature characteristics can be improved. 
     For instance, if the resistor R 1  is not disposed, the output accuracy of the constant voltage VREF is ±4% to 6%. In contrast, if the resistor R 1  is disposed, the output accuracy of the constant voltage VREF is improved to be approximately ±1%. 
     In contrast, if the drain current Id shifts to be smaller than the standard value Id 0 , a voltage is hardly generated between both terminals of the resistor R 1 . Therefore, each of the negative side shift effect of the gate-source voltage Vgs(M 1 ) and the positive side shift effect (i.e. body effect) of the ON threshold value voltage Vth(M 1 ) does not work, and hence the effect of adding the resistor R 1  substantially vanishes. 
     Second Embodiment 
       FIG.  4    is a diagram illustrating a second embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the first embodiment ( FIG.  2   ) described above and further includes an enhancement type N-channel MOS field effect transistor M 4 . 
     The transistor M 4  has a drain connected to the application terminal of the input voltage VIN. The transistor M 4  has agate connected to the gate and backgate of the transistor M 1 , the drain of the transistor M 2 , and the second terminal of the resistor R 1 . The transistor M 4  has a source and a backgate that are connected to the output terminal of the constant voltage VREF. Note that the transistor M 4  functions as a source follower arranged to enhance current capacity of the constant voltage generation circuit  1 . 
     In other words, in the first embodiment ( FIG.  2   ) described above, the gate and backgate of the transistor M 1 , the drain of the transistor M 2 , and the second terminal of the resistor R 1  are directly connected to the output terminal of the constant voltage VREF, while in the second embodiment ( FIG.  4   ) they are connected to the output terminal of the constant voltage via the source follower. 
     With this structure, the current capacity of the constant voltage generation circuit  1  can be enhanced without affecting the temperature characteristic of the ED reference voltage source (the transistors M 1  and M 2 ). Note that as a matter of course, as the transistor M 4  it is preferred to use an element having larger current capacity than the transistor M 1  or M 2 . 
     Third Embodiment 
       FIG.  5    is a diagram illustrating a third embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the second embodiment ( FIG.  4   ) described above and is provided with additional resistors R 2  and R 3 . 
     The resistor R 2  has a first terminal connected to the output terminal of the constant voltage VREF. A second terminal of the resistor R 2  and a first terminal of the resistor R 3  are connected to the gate of the transistor M 2 . A second terminal of the resistor R 3  is connected to the ground terminal. The resistors R 2  and R 3  connected in this way function as a resistor voltage divider that divides the constant voltage VREF and applies the divided voltage to the gate of the transistor M 2 . 
     In other words, in the first embodiment ( FIG.  2   ) and the second embodiment ( FIG.  4   ) described above, the gate of the transistor M 2  is directly connected to the output terminal of the constant voltage VREF, while in the third embodiment ( FIG.  5   ) it is connected to the output terminal of the constant voltage via the resistor voltage divider. 
     With this structure, it is possible to generate the constant voltage VREF (=Vgs(M 2 )×((R 2 +R 3 )/R 3 )) higher than that in the first embodiment ( FIG.  2   ) or the second embodiment ( FIG.  4   ). 
     Note that this embodiment is based on the second embodiment ( FIG.  4   ), but it may be based on the first embodiment ( FIG.  2   ) and add the resistors R 2  and R 3 . 
     Fourth Embodiment 
       FIG.  6    is a diagram illustrating a fourth embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the third embodiment ( FIG.  5   ) described above and includes P-channel MOS field effect transistors M 5  and M 6  and a current source CS instead of the transistor M 4 . 
     Sources and backgates of the transistors M 5  and M 6  are all connected to the application terminal of the input voltage VIN. The transistor M 5  has a gate connected to the gate and backgate of the transistor M 1 , the drain of the transistor M 2 , and the second terminal of the resistor R 1 . The transistor M 6  has a gate connected to a drain of the transistor M 5  and a first terminal of the current source CS. A second terminal of the current source CS is connected to the ground terminal. The transistor M 6  has a drain connected to the output terminal of the constant voltage VREF. The transistors M 5  and M 6  and the current source CS connected in this way function as a source follower arranged to enhance current capacity of the constant voltage generation circuit  1 . 
     In this way, the structure in which a PMOSFET is used as the source follower can operate in a state where the input voltage VIN is lower (i.e. VIN-VREF is smaller) than that in the second embodiment ( FIG.  4   ) or the third embodiment ( FIG.  5   ) in which an NMOSFET is used as the source follower. In particular, it can be said that this structure is effective when an output target value of the constant voltage VREF is high. 
     Fifth Embodiment 
       FIG.  7    is a diagram illustrating a fifth embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the third embodiment ( FIG.  5   ) described above and includes a depression type N-channel MOS field effect transistor M 7  instead of the enhancement type transistor M 4 . 
     The structure in which the depression type NMOSFET is used as the source follower in this way can output the constant voltage VREF following the input voltage VIN from just after the input voltage VIN is applied. 
     Sixth Embodiment 
       FIG.  8    is a diagram illustrating a sixth embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment has a structure similar to that of the first to fifth embodiments described above, in which the resistor R 1  is inserted between the gate and source of the transistor M 1  forming the ED reference voltage source, and is modified so that the drain current Id is supplied to the transistor M 2  via the current mirror constituted of P-channel MOS field effect transistors M 8  and M 9 . 
     The drain of the transistor M 1  is connected to a drain of the transistor M 8  (i.e. an input terminal of the current mirror). The source of the transistor M 1  is connected to the first terminal of the resistor R 1 . The gate and backgate of the transistor M 1  and the second terminal of the resistor R 1  are all connected to the ground terminal. 
     Sources and backgates of the transistors M 8  and M 9  are connected to the application terminal of the input voltage VIN. Gates of the transistors M 8  and M 9  are connected to the drain of the transistor M 8 . The drain of the transistor M 9  (i.e. the output terminal of the current mirror) and the drain and gate of the transistor M 2  are connected to the output terminal of the constant voltage VREF. The source of the transistor M 2  is connected to the ground terminal. 
     In this way, even the circuit form, in which the drain current Id of the transistor M 1  is supplied to the transistor M 2  via the current mirror, can obtain the effect of inserting the resistor R 1  as described above. 
     &lt;Consideration about Input Voltage Characteristic&gt; 
       FIG.  9    is a diagram illustrating Vds(M 1 )-Id characteristic and VIN-VREF characteristic in the comparative example ( FIG.  1   ) described above. As described above, in the ED type reference voltage source, the transistor M 1  functions as the constant current source that determines the drain current Id, and the constant voltage VREF is determined in accordance with the gate-source voltage Vgs(M 2 ) of the transistor M 2  in which the drain current Id flows. 
     If the transistor M 1  is operating in a saturated region, the drain current Id is substantially constant, and hence the constant voltage VREF should be ideally constant without depending on the input voltage VIN. However, the actual drain current Id is not completely constant and has a small gradient of dependence on Vds determined by channel length modulation parameter λ, as expressed by Id∝(1+λ×Vds). 
     Note that the above-mentioned channel length modulation parameter λ is a characteristic unique to a device and varies also depending on the element size. Therefore, if the input voltage VIN (therefore the drain-source voltage Vds(M 1 )) varies, the drain current Id flowing in the transistor M 1  varies, and hence the constant voltage VREF may vary. 
     In the following description, in view of the above consideration, a novel embodiment is proposed in which variation of the drain current Id due to input voltage variation is suppressed so that output accuracy of the constant voltage VREF can be improved. 
     Seventh Embodiment 
       FIG.  10    is a diagram illustrating a seventh embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the comparative example ( FIG.  1   ) described above and further includes a depression type N-channel MOS field effect transistor M 3 . 
     The transistor M 3  has a drain connected to the application terminal of the input voltage VIN. The transistor M 3  has a source and a backgate that are connected to the drain of the transistor M 1 . The transistor M 3  has a gate connected to the gate of the transistor M 1 . In other words, the drain of the transistor M 1  is connected to the application terminal of the input voltage VIN via the transistor M 3 . 
     Note that the drain-source voltage Vds(M 1 ) of the transistor M 1  should be set to 0.2 V or more when using the transistor M 1  in the saturated region, and the size of the transistor M 3  should be determined to satisfy the above condition. Therefore, the transistor M 3  is designed to have a W/L value (i.e. a ratio of channel width W to channel length L) sufficiently larger than that of the transistor M 1 . For instance, when W/L of the transistor M 1  is denoted by “a” while W/L of the transistor M 2  is denoted by “b”, it is preferred to design so that b is approximately 20 to 100 times of a. 
       FIG.  11    is a diagram illustrating variation reduction effect of the drain current Id by adding the transistor M 3 . Note that the horizontal axis represents the gate-source voltage Vgs, and the vertical axis represents the drain current Id. 
     As described above, W/L of the transistor M 3  is designed to be sufficiently larger than W/L of the transistor M 1 . Therefore, the ON threshold value voltage Vth(M 3 ) of the transistor M 3  is sufficiently smaller than the ON threshold value voltage Vth(M 1 ) of the transistor M 1 . As a result, the transistor M 1  is more dominant in determining the drain current Id than the transistor M 3 . In other words, when the drain current determined by the transistor M 1  is denoted by Id(M 1 ), Id=Id(M 1 ) is satisfied. 
     In addition, the transistors M 1  and M 3  are connected in series, and hence the drain current Id determined as described above flows in the transistor M 3 , too. As a result, the transistor M 3  is stabilized in a state where the drain current Id(M 1 ) flows (in a state where Id=Id(M 1 )=id(M 3 ) is satisfied). In other words, the transistor M 3  is clamped in a state where a negative voltage is generated as the gate-source voltage Vgs(M 3 ). 
     The clamp voltage in this case is approximately 0.2 V or more, as it should be a voltage in the range where the transistor M 1  is in the saturated region, and it is necessary to consider an influence of characteristics and size of the element. 
       FIG.  12    is a diagram illustrating VIN-Vds(M 1 ) characteristic in the seventh embodiment. The series of operation described above enables the drain-source voltage Vds(M 1 ) of the transistor M 1  to be substantially constant even if the input voltage VIN varies. Therefore, variation of the drain current Id due to input voltage variation can be suppressed, and output accuracy of the constant voltage VREF can be improved. 
     Eighth Embodiment 
       FIG.  13    is a diagram illustrating an eighth embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the seventh embodiment ( FIG.  10   ) described above and further includes the enhancement type N-channel MOS field effect transistor M 4 . 
     The drain of the transistor M 4  is connected to the application terminal of the input voltage VIN. The gate of the transistor M 4  is connected to the gate and backgate of the transistor M 1 , the drain of the transistor M 2 , and the gate of the transistor M 3 . The source and backgate of the transistor M 4  are connected to the output terminal of the constant voltage VREF. Note that the transistor M 4  functions as a source follower arranged to enhance current capacity of the constant voltage generation circuit  1 . 
     In other words, in the seventh embodiment ( FIG.  10   ) described above, the gate and backgate of the transistor M 1 , the drain of the transistor M 2 , and the gate of the transistor M 3  are directly connected to the output terminal of the constant voltage VREF, while in the eighth embodiment ( FIG.  13   ) they are connected to the output terminal of the constant voltage via the source follower. 
     With this structure, current capacity of the constant voltage generation circuit  1  can be enhanced without affecting the temperature characteristic of the ED reference voltage source (the transistors M 1  and M 2 ). Note that as a matter of course, as the transistor M 4  it is preferred to use an element having larger current capacity than the transistor M 1  or M 2 . 
     Ninth Embodiment 
       FIG.  14    is a diagram illustrating a ninth embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the eighth embodiment ( FIG.  13   ) and is provided with the additional resistors R 2  and R 3 . 
     The first terminal of the resistor R 2  is connected to the output terminal of the constant voltage VREF. The second terminal of the resistor R 2  and the first terminal of the resistor R 3  are connected to the gate of the transistor M 2 . The second terminal of the resistor R 3  is connected to the ground terminal. The resistors R 2  and R 3  connected in this way function as a resistor voltage divider that divides the constant voltage VREF and applies the divided voltage to the gate of the transistor M 2 . 
     In other words, in the seventh embodiment ( FIG.  10   ) and the eighth embodiment ( FIG.  13   ) described above, the gate of the transistor M 2  is directly connected to the output terminal of the constant voltage VREF, while in the ninth embodiment ( FIG.  14   ) it is connected to the output terminal of the constant voltage via the resistor voltage divider. 
     With this structure, it is possible to generate constant voltage VREF (=Vgs(M 2 )×((R 2 +R 3 )/R 3 )) higher than that in the seventh embodiment ( FIG.  10   ) or the eighth embodiment ( FIG.  13   ) described above. 
     Note that this embodiment is based on the eighth embodiment ( FIG.  13   ), but it may be based on the seventh embodiment ( FIG.  10   ) and add the resistors R 2  and R 3 . 
     Tenth Embodiment 
       FIG.  15    is a diagram illustrating a tenth embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the ninth embodiment ( FIG.  14   ) described above and includes the P-channel MOS field effect transistors M 5  and M 6  and the current source CS instead of the transistor M 4 . 
     The sources and backgates of the transistors M 5  and M 6  are all connected to the application terminal of the input voltage VIN. The gate of the transistor M 5  is connected to the gate and backgate of the transistor M 1 , the drain of the transistor M 2 , and the gate of the transistor M 3 . The gate of the transistor M 6  is connected to the drain of the transistor M 5  and the first terminal of the current source CS. The second terminal of the current source CS is connected to the ground terminal. The drain of the transistor M 6  is connected to the output terminal of the constant voltage VREF. The transistors M 5  and M 6  and the current source CS connected in this way function as the source follower arranged to enhance current capacity of the constant voltage generation circuit  1 . 
     In this way, the structure in which the PMOSFETs are used as the source follower can operate in a state where the input voltage VIN is lower (i.e. VIN-VREF is smaller) than that in the eighth embodiment ( FIG.  13   ) or the ninth embodiment ( FIG.  14   ) in which the NMOSFET is used as the source follower. In particular, it can be said that this structure is effective when the output target value of the constant voltage VREF is high. 
     Eleventh Embodiment 
       FIG.  16    is a diagram illustrating an eleventh embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the ninth embodiment ( FIG.  14   ) and includes the depression type N-channel MOS field effect transistor M 7  instead of the enhancement type transistor M 4 . 
     In this way, the structure in which the depression type NMOSFET is used as the source follower can output the constant voltage VREF following the input voltage VIN from just after the input voltage VIN is applied. 
     Twelfth Embodiment 
       FIG.  17    is a diagram illustrating a twelfth embodiment of the constant voltage generation circuit. Similarly to the seventh to eleventh embodiments described above, the constant voltage generation circuit  1  of this embodiment has the structure in which the transistor M 3  is connected to the drain of the transistor M 1  constituting the ED reference voltage source, and is modified so that the drain current Id is supplied to the transistor M 2  via the current mirror constituted of the P-channel MOS field effect transistors M 8  and M 9 . 
     The drain of the transistor M 3  is connected to the drain of the transistor M 8  (i.e. the input terminal of the current mirror). The source and backgate of the transistor M 3  are connected to the drain of the transistor M 1 . In other words, the drain of the transistor M 1  is connected to the input terminal of the current mirror via the transistor M 3 . The gate and backgate of the transistor M 1  and the gate of the transistor M 3  are connected to the ground terminal. 
     The sources and backgates of the transistors M 8  and M 9  are connected to the application terminal of the input voltage VIN. The gates of the transistors M 8  and M 9  are connected to the drain of the transistor M 8 . The drain of the transistor M 9  (i.e. the output terminal of the current mirror) and the drain and gate of the transistor M 2  are connected to the output terminal of the constant voltage VREF. The source of the transistor M 2  is connected to the ground terminal. 
     In this way, even the circuit form, in which the drain current Id of the transistor M 1  is supplied to the transistor M 2  via the current mirror, can obtain the effect of inserting the transistor M 3  as described above. 
     Thirteenth Embodiment 
       FIG.  18    is a diagram illustrating a thirteenth embodiment of the constant voltage generation circuit. The constant voltage generation circuit  1  of this embodiment is based on the seventh embodiment ( FIG.  10   ) described above and further includes the resistor R 1 . 
     The first terminal of the resistor R 1  is connected to the source of the transistor M 1 . The second terminal of the resistor R 1  is connected to the gate and backgate of the transistor M 1  and the output terminal of the constant voltage VREF. In this way, the resistor R 1  is connected between the gate of the transistor M 1  and source, and between the backgate and source of the transistor M 1 . 
     This embodiment can obtain the variation suppression effect of the drain current Id by inserting the resistor R 1 . Therefore, not only the variation of the drain current Id due to the input voltage variation but also the variation of the drain current Id due to the process variation can be suppressed, and hence output accuracy of the constant voltage VREF can be further improved. 
     Note that this embodiment is based on the seventh embodiment ( FIG.  10   ), but it may be based on the eighth to twelfth embodiment, so that the resistor R 1  is inserted between the gate and source of the transistor M 1 . 
     &lt;Summary&gt; 
     In the following description, the various embodiments disclosed in this specification are summarized and described. 
     For instance, the constant voltage generation circuit disclosed in this specification includes a depression type first transistor and an enhancement type second transistor that constitute an ED type reference voltage source, and a resistor connected between gate and source of the first transistor (first structure). 
     Note that the constant voltage generation circuit having the first structure described above may have a structure in which the first transistor and the second transistor are NMOSFETs (second structure). 
     In addition, the constant voltage generation circuit having the second structure described above may have a structure in which the first transistor has a drain connected to an application terminal of an input voltage, the second transistor has a source connected to a reference potential terminal, a gate of the first transistor and a drain of the second transistor are connected to an output terminal of the constant voltage directly or via a source follower, and a gate of the second transistor is connected to the output terminal of the constant voltage directly or via a resistor voltage divider (third structure). 
     In addition, the constant voltage generation circuit having the third structure described above may have a structure in which the source follower includes an NMOSFET having a drain connected to an application terminal of the input voltage, a gate connected to the gate of the first transistor and the drain of the second transistor, and a source connected to the output terminal of the constant voltage (fourth structure). 
     In addition, in the constant voltage generation circuit having the fourth structure described above may have a structure in which the NMOSFET is a depression type (fifth structure). 
     In addition, the constant voltage generation circuit having the third structure described above may have a structure in which the source follower includes a first PMOSFET having a source connected to the application terminal of the input voltage, and a gate connected to the gate of the first transistor and the drain of the second transistor; a second PMOSFET having a source connected to the application terminal of the input voltage, a gate connected to a drain of the first PMOSFET, and a drain connected to the output terminal of the constant voltage; and a current source connected between the reference potential terminal and the drain of the first PMOSFET as well as the gate of the second PMOSFET (sixth structure). 
     In addition, the constant voltage generation circuit having the second structure described above may have a structure in which the drain of the first transistor is connected to the input terminal of the current mirror, the output terminal of the current mirror and the drain and gate of the second transistor are connected to the output terminal of the constant voltage, and the gate of the first transistor and the source of the second transistor are connected to the reference potential terminal (seventh structure). 
     In addition, the constant voltage generation circuit having any one of the first to seventh structures described above may have a structure in which the resistor is a base resistor having a positive temperature characteristic (eighth structure). 
     In addition, the constant voltage generation circuit having any one of the first to seventh structures described above may have a structure in which the resistor is a poly resistor having a negative temperature characteristic (ninth structure). 
     In addition, the constant voltage generation circuit having any one of the first to ninth structures described above may have a structure in which drain current flowing in the first transistor is 100 nA or more and less than 1 μA, and the resistor has a resistance of 100 kΩ or more and less than 1 MΩ (tenth structure). 
     Further for example, another constant voltage generation circuit disclosed in this specification includes a depression type first transistor and an enhancement type second transistor that constitute an ED type reference voltage source, and a depression type third transistor that is connected to a drain of the first transistor and has larger W/L than the first transistor (eleventh structure). 
     Note that the constant voltage generation circuit having the eleventh structure described above may have a structure in which the first transistor, the second transistor, and the third transistor are NMOSFETs (twelfth structure). 
     In addition, the constant voltage generation circuit having the twelfth structure described above may have a structure in which the drain of the first transistor is connected to an application terminal of an input voltage via the third transistor, a source of the second transistor is connected to the reference potential terminal, gates of the first transistor and the third transistor and a drain of the second transistor are connected to the output terminal of the constant voltage directly or via a source follower, and the gate of the second transistor is connected to the output terminal of the constant voltage directly or via a resistor voltage divider (thirteenth structure). 
     The constant voltage generation circuit having the thirteenth structure described above may have a structure in which the source follower includes an NMOSFET having a drain connected to an application terminal of the input voltage, a gate connected to the gates of the first transistor and the third transistor and the drain of the second transistor, and a source connected to the output terminal of the constant voltage (fourteenth structure). 
     In addition, the constant voltage generation circuit having the fourteenth structure described above may have a structure in which the NMOSFET is a depression type (fifteenth structure). 
     In addition, the constant voltage generation circuit having the thirteenth structure described above may have a structure in which the source follower includes a first PMOSFET having a source connected to the application terminal of the input voltage, a gate connected to the gates of the first transistor and the third transistor and the drain of the second transistor; a second PMOSFET having a source connected to the application terminal of the input voltage, a gate connected to the drain of the first PMOSFET, and a drain connected to the output terminal of the constant voltage; and a current source connected between the reference potential terminal and the drain of the first PMOSFET as well as the gate of the second PMOSFET (sixteenth structure). 
     In addition, the constant voltage generation circuit having the twelfth structure described above may have a structure in which the drain of the first transistor is connected to the input terminal of the current mirror via the third transistor, the output terminal of the current mirror and the drain and gate of the second transistor are connected to the output terminal of the constant voltage, and the gates of the first transistor and the third transistor and the source of the second transistor are connected to the reference potential terminal (seventeenth structure). 
     The constant voltage generation circuit having any one of the eleventh to seventeenth structures described above may have a structure further including a resistor connected between gate and source of the first transistor (eighteenth structure). 
     In addition, the constant voltage generation circuit having the eighteenth structure described above may have a structure in which the resistor is a base resistor having a positive temperature characteristic (nineteenth structure). 
     In addition, the constant voltage generation circuit having the eighteenth structure described above may have a structure in which the resistor is a poly resistor having a negative temperature characteristic (twelfth structure). 
     &lt;Other Variations&gt; 
     Note that other than the embodiments described above, the various technical features disclosed in this specification can be variously modified without deviating from the spirit of the technical creation. In other words, the embodiments described above are merely examples in every aspect and should not be interpreted as limitations. The technical scope of the present invention is not limited to the embodiments described above but should be interpreted to include all modifications within meanings and ranges equivalent to the claims. 
     INDUSTRIAL APPLICABILITY 
     The constant voltage generation circuit disclosed in this specification can be appropriately used as means arranged to generate a reference voltage or a threshold value voltage in a semiconductor device, for example. 
     LIST OF REFERENCE SIGNS 
     
         
         
           
               1  constant voltage generation circuit 
             CS current source 
             M 1  NMOSFET (corresponding to depression type first transistor) 
             M 2  NMOSFET (corresponding to enhancement type second transistor) 
             M 3  NMOSFET (corresponding to depression type third transistor) 
             M 4  NMOSFET (enhancement type) 
             M 5 , M 6  PMOSFET 
             M 7  NMOSFET (depression type) 
             M 8 , M 9  PMOSFET 
             R 1 , R 2 , R 3  resistor