Patent Publication Number: US-11657881-B2

Title: Dynamic reference current memory array and method

Description:
PRIORITY CLAIM 
     The present application is a continuation of U.S. application Ser. No. 16/774,938, filed Jan. 28, 2020, which is a continuation U.S. application Ser. No. 16/022,688, filed Jun. 29, 2018, now U.S. Pat. No. 10,553,288, issued Feb. 4, 2020, which is a continuation of U.S. application Ser. No. 15/587,039, filed May 4, 2017, now U.S. Pat. No. 10,020,064, issued Jul. 10, 2018, which is a continuation of U.S. application Ser. No. 14/024,109, filed Sep. 11, 2013, now U.S. Pat. No. 9,666,246, issued May 30, 2017, which are incorporated herein by reference in their entireties. 
    
    
     FIELD 
     The present disclosure is related to sensing data based on a dynamic reference current. 
     BACKGROUND 
     In an approach, a fixed value of a reference current is used in sensing data for a metal-oxide nitride-oxide semiconductor (MONOS) flash memory cells. For illustration, a flash memory cell is called a flash cell, a memory cell, etc. Further, a sense amplifier compares the value of the flash cell current with the value of the reference current. If the value of the cell current is higher than that of the reference current, the data stored in the flash cell is logically high. But if the value of the cell current is lower than that of the reference current, the data stored in the flash cell is logically low. After the flash cell is programmed and erased many times, such as over about 10,000 times, the flash cell experiences a charge loss. As a result, the cell current decreases. In contrast, the fixed value of the reference current stays the same. Consequently, the data revealed by the sense amplifier could be inaccurate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims. 
         FIG.  1    is a diagram of a circuit used to illustrate dynamic current sensing, in accordance with some embodiments. 
         FIG.  2    is a block diagram of a memory array that uses the dynamic current sensing mechanism in  FIG.  1   , in accordance with some embodiments. 
         FIG.  3    is a diagram of a circuit illustrating how the circuit in  FIG.  1    is used with the memory array in  FIG.  2   , in accordance with some embodiments. 
         FIG.  4    is a circuit diagram of a flash memory cell of the memory array in  FIG.  2   , in accordance with some embodiments. 
         FIG.  5    is a flow chart of a method illustrating operations of the circuit in  FIG.  3   , in accordance with some embodiments. 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art. 
     Some embodiments have one or a combination of the following features and/or advantages. In some embodiments, data sensing is based on a dynamic reference current. The reference current is dynamic because it varies as the current in a corresponding flash memory cell varies. As a result, the sense or read margin increases. 
       FIG.  1    is a diagram of a circuit  100 , in accordance with some embodiments. Circuit  100  is used to illustrate operations of a sense amplifier  120 , which senses a current Icell of a flash memory cell Fcell 10  based on a reference current Iref generated by a reference current generating circuit  110 . 
     Flash Memory Cell 
     In some embodiments, flash memory cell Fcell 10  is manufactured based on metal-oxide nitride-oxide semiconductor (MONOS) technology. After Fcell 10  is manufactured, Fcell 10  stores a “neutral” logical value, which is not a low logical nor a high logical value. So that Fcell 10  stores a low logical value, electrons are injected into the source side of flash cell Fcell 10 . In other words, injecting electrons into Fcell 10  programs Fcell 10  with a low logical value. So that Fcell 10  stores a high logical value, Fcell 10  is programmed with a low logical value, and the low logical value is then erased to result in a high logical value. 
     When Fcell 10  is accessed, Fcell 10  draws a current Icell. A value of Icell depends on a logical value stored in Fcell 10 . For example, if Fcell 10  stores a low logical value, Icell is relatively low, compared with reference current Iref. In contrast, if current Fcell 10  stores a high logical value, Icell is relatively high compared with Iref. In some embodiments, sense amplifier  120  compares a value of Icell with a value of Iref. If the value of Icell is less than the value of Iref, Fcell 10  stores a low logical value. But if the value of Icell is greater than the value of Iref, Fcell 10  stores a high logical value. 
     A line  185  corresponds to bit line BL in  FIG.  4   . Details of flash memory cells are explained with reference to  FIG.  4   . 
     Reference Current Generating Circuit 
     Current generating circuit  110  generates current Iref based on a current Iref 0  and a current Irfef 1 . 
     A reference cell CRef 010  generates a current Iref 0  corresponding to current Icell when Fcell stores a low logical value. In some embodiments, reference cell CRef 010  includes a flash cell Fcell in  FIG.  4    programmed to store a low logical value. A line  177  corresponds to bit line BL in  FIG.  4   . 
     A stabilization circuit  130  including an inverter INV 10  and a transistor N 15  stabilizes current Iref 0 . In some embodiments, inverter INV 10  includes a PMOS transistor (not shown) and an NMOS transistor (not shown). A size in terms of a width W and length L ratio of transistor N 15  is selected such that a voltage at the gate and at the source of transistor N 15  is at a specific value. As a result, a voltage drop across the gate and the source of transistor N 15  is stabilized. A current through transistor N 15  or current Iref 0  is therefore stabilized. 
     A PMOS transistor P 10  and a PMOS transistor P 20  generate a current IP 20  having half a value of current Iref 0 . Current IP 20  is a current provided by transistor P 20 . Current Iref 0  has the same value as a current drawn by PMOS transistor P 10 . For illustration, PMOS transistor P 10  and PMOS transistor P 20  are configured as a current mirror having a ratio 2:1. As a result, IP 20 =½ IRef 0 . In some embodiments, to select a 2:1 ratio, a size of PMOS transistor P 20  is designed to be about ½ that of PMOS transistor P 10 . 
     A reference cell CRef 110  generates a current Iref 1  corresponding to current Icell of Fcell 10  when Fcell 10  stores a high logical value. In some embodiments, reference cell CRef 110  includes a flash cell Fcell in  FIG.  4    programmed to store a high logical value. A line  187  corresponds to bit line BL in  FIG.  4   . 
     A stabilization circuit  140  with reference to current Iref 1  corresponds to stabilization circuit  130  with reference to current Iref 0 . For example, stabilization circuit  140  stabilizes current Iref 1 . Stabilization circuits  130  and  140  are shown in current generating circuit  110  for illustration. Embodiments of the disclosure are not limited to a location of stabilization circuit  130  or  140 . For example, at least one of stabilization circuit  130  or  140  is not part of current generating circuit  110 . Further, in some embodiments, at least one of stabilization circuit  130  or  140  is not used. 
     A PMOS transistor P 30  and a PMOS transistor P 40  with reference to current Iref 1  correspond to PMOS transistors P 10  and P 20  with reference to current Iref 1 , respectively. For example, PMOS transistors P 30  and P 40  generate a current IP 40  having half a value of current Iref 1 . In some embodiments, PMOS transistor P 30  and PMOS transistor P 40  are configured as a current mirror having a ratio 2:1. As a result, IP 40 =½ IRef 1 . In some embodiments, to select a 2:1 ratio, a size of PMOS transistor P 40  is designed to be about ½ that of PMOS transistor P 30 . 
     Current Iref is the sum of currents IP 20  and IP 40 . Mathematically expressed: 
     
       
         
           
             
               
                 
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     Current Iref is thus an average of current Icell when Fcell stores a high and a low logical value. Expressed in another way, current Iref is at the middle point of current Iref 0  and current Iref 1 . 
     An NMOS transistor N 10  of circuit  110  and an NMOS transistor N 20  of sense amplifier  120  function as a current mirror so that a current IN 20  is equal to current Iref. Current IN 20  is a current drawn by NMOS transistor N 20 . Explained in a different way, NMOS transistor N 10  converts current Iref to a voltage Vref on a line  175  provided to a gate of transistor N 20 . In some embodiments, voltage Vref is provided to a plurality of transistors N 20  of corresponding sense amplifiers  120  to sense a plurality of corresponding memory cells Fcells. For example, voltage Vref is provided to 16 transistors N 20  of corresponding 16 amplifiers  120  as illustrated with reference to  FIG.  2   . In such a condition, a pair of reference cells CRef 010  and CRef 110  functions with 16 sense amplifiers  120  and  16  memory cells Fcell in  FIG.  4   . 
     Sense Amplifier Circuit 
     A stabilization circuit  150  of sense amplifier  120  stabilizes current Icell in the same manner as stabilization circuit  130  stabilizing current Iref 0 . Inverter INV 30  and NMOS transistor N 35  correspond to inverter INV 10  and NMOS transistor N 15 , respectively. Stabilization circuit  150  is shown in sense amplifier  120  for illustration. Embodiments of the disclosure are not limited to a location of stabilization circuit  150 . For example, stabilization circuit  150  is not part of sense amplifier  120 . Further, in some embodiments, stabilization circuit  150  is not used. 
     A PMOS transistor P 50  and a PMOS transistor P 60  mirror current Icell such that a current IP 60  equals to current Icell. Current IP 60  is a current drawn by PMOS transistor P 60 . 
     A node NO receives current IP 60  and current IN 20 . When current IP 60  is greater than current IN 20 , a voltage at node NO increases such that an output circuit  160  generates an output SO having a high logical value. When current IP 60  is less than current IN 20 , however, a voltage at node NO decreases such that output circuit  160  generates output SO having a low logical value. Because current IP 60  equals current Icell and current IN 20  equals current Iref, effectively, when current Icell is greater than current Iref, output SO is logically high. But when current Icell is less than current Iref, output SO is logically low. 
     Various embodiments of the present disclosure are advantageous over other approaches. For example, both reference cells CRef 010  and CRef 110  each includes a flash cell Fcell in  FIG.  4   . In operation, when flash cell Fcell 10  is erased, reference cells CRef 010  and CRef 110  are also erased. As a result, when characteristics of Fcell 10  change, characteristics of reference cells CRef 010  and CRef 110  change in a similar manner. Further, because reference current Iref is an average of currents Iref 0  and Iref 1 , reference current Iref is consistently greater than current Iref 0  and lesser than current Iref 1  regardless of whether current Iref 0  and/or current Iref 1  changes. Consequently, if a value of cell current Icell changes due to a charge loss of repeated usages over the years, reference current Iref changes accordingly. In other words, a change in the value of current Icell is compensated by a change in the value of current Iref. As a result, a result of comparison by sense amplifier  120  between reference current Iref and cell current Iref reveals appropriate data. 
     In the above illustration, a value of current Iref is an average of currents Iref 0  and Iref 1 . Expressed differently, current Iref is at the middle point of current Icell when Fcell stores a low and a high logical value. Different values of current Iref are within the scope of the present disclosure. The values of current Iref are adjusted by adjusting the size of transistors P 10 , P 20 , P 30 , and/or P 40 . Effectively, the size ratio between transistors P 10  and P 20  and/or between transistors P 30  and P 40  change accordingly. For example, based on a ratio 3:1, IP 20 =⅓ IP 10 =⅓ Iref 0 , and IP 40 =⅓ IP 30 =⅓ Iref 1 . As a result, Iref=IP 20 +IP 40 =⅓ (Iref 0 +Iref 1 ). In some embodiments, based on a predetermined value of current Iref, the size ratio between transistor P 10  and P 20  and/or between transistor P 30  and P 40  is determined accordingly. In other words, the sizes of transistors P 10 , P 20 , P 30 , and P 40  are determined accordingly to provide the predetermined current Iref. 
     Because current Iref is an average of current Iref 0  and Iref 1 , current Iref changes as current Iref 0  and/or current Iref 1  changes. As a result, current Iref is a dynamic current, and sensing the data of Fcell 10  based on current Iref is called dynamic current sensing. 
     Memory Array 
       FIG.  2    is a block diagram of a memory array  200 , in accordance with some embodiments. Memory array  200  uses the dynamic current sensing mechanism illustrated in  FIG.  1   . Memory array  200  includes column segments GC 1  to GC 16 , and current reference segments Ref 0  and Ref 1 . 
     With reference to column segments GC 1  to GC 16 , for simplicity, details of only segment GC 1  are shown, but are also applicable to segments GC 2  to GC 16 . In some embodiments, segment GC 1  includes 64 columns divided into 8 (sub) segments GC 1 - 1  to GC 1 - 8 . Further, each segments GC 1 - 1  to GC 1 - 8  includes 8 columns (not shown). 
     Also for simplicity, details of reference current segment Ref 0  are shown, but are also applicable to current reference segment Ref 1 . In some embodiments, segment Ref 0  includes 8 columns Ref 0 - 1  to Ref 0 - 8 . Similarly, segment Ref 1  also includes 8 columns Ref 1 - 1  to Ref 1 - 8  (not shown). 
     In some embodiments, in operation, one column in each of a corresponding segment GC 1  to GC 16  is active at a time and functions with a corresponding pair of columns of corresponding current reference segments Ref 0  and Ref 1 . Effectively, 16 columns from 16 segments GC 1  to GC 16  function with a pair of columns of segments Ref 0  and Ref 1 . For example, one column in segment Ref 0  and one column in segment Ref 1  operate as a pair and function with a corresponding segment GC 1 - 1  to GC 1 - 8  of segment GC 1 , a corresponding segment GC 2 - 1  to GC 2 - 8  (not shown) of segment GC 2 , a corresponding segment GC 3 - 1  to GC 3 - 8  (not shown) of segment GC 3 , etc., for a total of 16 columns of segments GC 1  to GC 16 . For simplicity of discussion, one column in a segment is described, but the description is applicable to the other 15 columns. For example, a pair comprising columns Ref 0 - 1  and Ref 1 - 1  function with segment GC 1 - 1  of GC 1 . A pair comprising columns Ref 0 - 2  and Ref 1 - 2  function with segment GC 1 - 2  of GC 1 , and a pair comprising columns Ref 0 - 3  and Ref 1 - 3  function with segment GC 1 - 3  of GC 1 , etc. 
     For another example, when any one of 8 columns in segment GC 1 - 1  is active, a corresponding pair of Ref 0 - 1  and Ref 1 - 1  is selected to function with the active column in segment GC 1 - 1 . For another example, when any one of 8 columns in segment GC 1 - 2  is active, a corresponding pair of Ref 0 - 2  and Ref 1 - 2  is selected to function with the active column in segment GC 1 - 2 , and when any one of 8 columns in segment GC 1 - 3  is active, a corresponding pair of Ref 0 - 3  and Ref 1 - 3  is selected to function with the active column in segment GC 1 - 3 , etc. 
     Memory Array and Sense Amplifier Circuit 
       FIG.  3    is a diagram of a circuit  300 , in accordance with some embodiments. Circuit  300  is used to illustrate how circuit  100  in  FIG.  1    is used in conjunction with memory array  200  in  FIG.  2   . For illustration, segment GC 1 - 1  of segment GC 1  of memory array  200  is used with segments Ref 0  and Ref 1 , and is shown. Segments GC 1 - 2  to GC 1 - 8  of GC 1  used with segments Ref 0  and Ref 1  are in a manner similar to segment GC 1 - 1  being used with segments Ref 0  and Ref 1 . In some embodiments, segments GC 1 - 2  to GC 1 - 8  of segment GC 1  are also input into a multiplexer  310  as segment GC 1 - 1 . Effectively, 8 segments GC 1 - 1  to GC 1 - 8  of segments GC 1  are input into multiplexer  310 . Segments GC 1 - 2  to GC 1 - 8  are used with segments Ref 0  and Ref 1  in a manner similar to segment GC 1 - 1  being used with segments Ref 0  and Ref 1 . Segments GC 2  to GC 16  used with segments Ref 0  and Ref 1  are in a similar manner as segment GC 1  being used with segments Ref 0  and Ref 1 . Effectively, in some embodiments, 16 multiplexers  310  correspond to 16 segments GC 1  to GC 16 . 
     Segment GC 1 - 1  includes 8 columns each corresponding to a bit line BL in  FIG.  4   . As illustratively shown, segment GC 1 - 1  includes 8 bit line BL 1  to BL 8 . In some embodiments, each bit line BL 1  to BL 8  is coupled with 64 flash memory cells Fcell. For simplicity, flash memory cells Fcell coupled with bit line BL 1  are shown, and one memory cell Fcell of bit line BL 1  is labeled. 
     Effectively, in the illustration of  FIG.  3   , the flash memory cells coupled with bit lines BL 1  to BL 8  form an array having 8 columns and 64 rows. Flash memory cells in a row are coupled with a word line WL in  FIG.  4   . As illustratively shown, 64 rows of GC 1 - 1  correspond to 64 word lines WL 1  to WL 64 . 
     Similarly, segment Ref 0  includes 8 bit line RBL 1  to RBL 8 . In some embodiments, each bit line RBL 1  to RBL 8  of segment Ref 0  is also coupled with 64 reference cells CRef 0 . For simplicity, reference cells of bit line RBL 1  of section Ref 0  are shown, and one reference cell CRef 0  is labeled. In some embodiments, a reference cell CRef 0  includes a flash memory cell Fcell programmed with a low logical value. Effectively, the reference cells CRef 0  coupled with bit lines RBL 1  to RBL 8  of segment Ref 0  form an array with 8 columns and 64 rows. Reference cells in a row of section Ref 0  are coupled with a word line of section Ref 0 . As illustratively shown, 64 rows in segment Ref 0  correspond to 64 word lines RWL 1  to RWL 64 . 
     Segment Ref 1  also includes 8 bit lines RBL 1  to RBL 1 . Each bit line RBL 1  to RBL 8  of Ref 1  is coupled with 64 reference cells CRef 1 . For simplicity, reference cells coupled with bit line RBL 1  of segment Ref 1  are shown, and one reference cell CRef 1  is labeled. In some embodiments, a reference cell CRef 1  includes a flash memory cell Fcell programmed with a high logical value. Effectively, the reference cells CRef 1  coupled with bit line RBL 1  to RBL 8  of segment Ref 1  form an array with 8 columns and 64 rows. Reference cells CRef 1  in a row of section Ref 1  are coupled with a word line of section Ref 1 . As illustratively shown, 64 rows in segment Ref 1  correspond to 64 word lines RWL 1  to RWL 64 . Because each of word lines RWL 1  to RWL 64  also controls a row of reference cells CRef 0 , each of word lines RWL 1  to RWL 64  controls the same row of Ref 0  and Ref 1 . 
     In  FIG.  3   , 64 rows in segment GC 1 - 1  and segments Ref 0 , Ref 1  are used for illustration. A different number of rows is within the scope of the present disclosure. 
     In operation, a multiplexer  310  selects a memory cell Fcell in a column and a row of segment GC 1 - 1  to be sensed. For illustration, multiplexer  310  selects memory cell Fcell 10  represented by a dashed box that is coupled with word line WL 1  and bit line BL 1  of segment GC- 1 . 
     A multiplexer  320  selects a reference cell CRef 0  in a column and a row of segment Ref 0  to be used in sensing the selected memory cell Fcell 10 . For illustration, multiplexer  320  selects reference cell CRef 010  represented by a dashed box that is coupled with word line RWL 1  and bit line RBL 1  of segment Ref 0 . 
     In some embodiments, the column of the selected reference cell CRef 010  corresponds to the selected column of the selected memory cell Fcell 10 . For example, because the selected memory cell Fcell 10  is coupled with bit lint BL 1  of segment GC 1 - 1 , the selected reference cell CRef 010  is also coupled with bit line RBL 1  of segment Ref 0 . But if the selected memory cell Fcell 10  is coupled with another bit line of segment GC 1 - 1 , such as bit line BLi where i is an integer number, the selected reference cell CRef 010  is also coupled with a corresponding read bit line RBLi of segment Ref 0 . 
     A multiplexer  330  selects a reference cell CRef 1  in a column and a row of segment Ref 1  to be used with the selected reference cell CRef 010  to sense the selected memory cell Fcell 10 . For illustration, multiplexer  330  selects reference cell Cref 110  represented by a dashed box. Further, because the selected memory cell Fcell 10  and reference cell CRef 010  are coupled with corresponding bit lines BL 1  and RBL 1 , in some embodiments, the selected reference cell CRef 110  is also coupled with corresponding read bit line RBL 1  of section Ref 1 . 
     As illustratively shown in  FIG.  3   , memory cell Fcell 10 , reference cell CRef 010 , reference cell CRef 110 , current generating circuit  110 , and sense amplifier  120  constitute circuit  100  in  FIG.  1   . 
     Multiplexers  310 ,  320 , and  330  are used for illustration. Other ways to identify a corresponding flash memory cell Fcell, reference cell CRef 010 , or CRef 100  are within the scope of various embodiments. For example, in some embodiments, a flash memory cell, a reference cell CRef 010 , or CRef 110  is identified by a decoder based on corresponding address of the corresponding cell. 
     Flash Memory Cell, Circuit Diagram 
       FIG.  4    is a circuit diagram of a flash memory cell Fcell, in accordance with some embodiments. Memory cell Fcell includes a transistor  410  having four terminals serving as a bit line BL, a source line SL, a word line WL, and a control gate CG. Memory cell Fcell has a split gate region in which a first half of the gate region is coupled with word line WL and a second half of the gate region is coupled with control gate CG. When both word line WL and control gate CG are activated, for example with a high logical value, memory cell Fcell is activated. Source line SL is grounded. 
     In some embodiments, memory cell Fcell is programmed with a low logical value to generate reference cell CRef 010 , or is programmed with a high logical value to generate reference cell CRef 110 . In such a situation, word line WL corresponds to one of word line RWL 1  to RWL 64  in  FIG.  3   , and bit line BL corresponds to one of bit line RBL 1  to RBL 8 . 
     Flash memory cell Fcell in  FIG.  4    is used for illustration. Other memory cells and/or other configurations of flash memory cells are within the contemplated scope of the present disclosure. 
     Method 
       FIG.  5    is a flowchart of a method  500 , in accordance with some embodiments. Method  500  is used to illustrate operations of circuit  300  in  FIG.  3   . 
     In operation  510 , flash memory cell Fcell 10  is selected to be sensed. In some embodiments, a word line and a bit line corresponding flash memory cell Fcell 10  are activated, and multiplexer  310  selects flash memory cell Fcell 10 . 
     In operation  520 , a pair of reference cells CRef 010  and CRef 110  is selected to be used in sensing the selected memory cell Fcell 10 . In some embodiments, a word line and a bit line corresponding to reference cell CRef 010  are activated, and multiplexer  320  selects reference cell CRef 010 . Further, a word line and a bit line corresponding to reference cell CRef 110  are activated, and multiplexer  330  selects reference cell CRef 110 . 
     In operation  530 , current generating circuit  100  in  FIG.  1   , based on reference cells CRef 010  and CRef 110 , generates current Iref and voltage Vref for use by sense amplifier  120 . 
     In operation  540 , sense amplifier  120 , based on current Icell generated by flash memory cell Fcell 10  and reference current Iref, generates output SO. The logical value on output SO indicates a corresponding logical value stored in flash memory cell Fcell 10 . 
     In some embodiments, a memory array includes a plurality of column segments, each column segment including a plurality of columns of memory cells, a plurality of sense amplifiers, wherein each sense amplifier is selectively coupled to each column of the plurality of columns of a corresponding column segment of the plurality of column segments, a plurality of first reference cells, a plurality of second reference cells, and a reference current circuit. The reference current circuit is configured to generate a reference current based on a first current generated by a first reference cell of the plurality of first reference cells programmed to a low logical value and a second current generated by a second reference cell of the plurality of second reference cells programmed to a high logical value, and each sense amplifier of the plurality of sense amplifiers is configured to generate a mirror current based on the reference current, and generate a logical value based on a comparison of the mirror current to a cell current received from a memory cell of a column of the plurality of columns of the corresponding column segment of the plurality of column segments. In some embodiments, the memory array includes a plurality of first word lines, wherein each first word line of the plurality of first word lines is coupled to the memory cells of a corresponding row of a plurality of rows of memory cells of a column segment of the plurality of column segments, and a plurality of second word lines, wherein each second word line of the plurality of second word lines is coupled to the first reference cells of a corresponding row of a plurality of rows of first reference cells of the plurality of first reference cells, and to the second reference cells of a corresponding row of a plurality of rows of second reference cells of the plurality of second reference cells. In some embodiments, the memory array is configured to activate a second word line of the plurality of second word lines when a corresponding first word line of the plurality of first word lines is activated. In some embodiments, the plurality of first word lines includes a total of 64 first word lines, and the plurality of second word lines includes a total of 64 second word lines. In some embodiments, each row of the plurality of rows of memory cells of the column segment of the plurality of column segments includes a total of eight memory cells, each row of the plurality of rows of first reference cells of the plurality of first reference cells includes a total of eight first reference cells, and each row of the plurality of rows of second reference cells of the plurality of second reference cells includes a total of eight second reference cells. In some embodiments, the plurality of first reference cells includes a plurality of first bit lines corresponding to a plurality of columns of first reference cells of the plurality of first reference cells, the plurality of second reference cells includes a plurality of second bit lines corresponding to a plurality of columns of second reference cells of the plurality of second reference cells, a column segment of the plurality of column segments includes a plurality of third bit lines corresponding to the plurality of columns of memory cells, and each of the plurality of first bit lines, the plurality of second bit lines, and the plurality of third bit lines includes a same number of bit lines. In some embodiments, the memory array includes a first multiplexer coupled between the plurality of first reference cells and the reference current circuit, a second multiplexer coupled between the plurality of second reference cells and the reference current circuit, and a third multiplexer coupled between the column segment of the plurality of column segments and a corresponding sense amplifier of the plurality of sense amplifiers. In some embodiments, each of the first through third multiplexers is configured to select a same numbered bit line of the corresponding pluralities of first through third bit lines during a read operation. In some embodiments, the plurality of column segments includes a total of 16 column segments, and the plurality of sense amplifiers includes a total of 16 sense amplifiers. In some embodiments, the reference current circuit includes a first transistor configured to generate a reference voltage based on the reference current, and each sense amplifier of the plurality of sense amplifiers includes a second transistor configured to generate the mirror current based on the reference voltage. In some embodiments, each memory cell of the plurality of columns of memory cells of each column segment of the plurality of column segments, each first reference cell of the plurality of first reference cells, and each second reference cell of the plurality of second reference cells includes a MONOS flash memory cell. 
     In some embodiments, a memory array includes a plurality of columns of first reference cells, a plurality of first bit lines corresponding to the plurality of columns of first reference cells, a plurality of columns of second reference cells, a plurality of second bit lines corresponding to the plurality of columns of second reference cells, a plurality of column segments, each column segment including a plurality of columns of memory cells and a corresponding plurality of third bit lines, a plurality of sense amplifiers, wherein each sense amplifier is selectively coupled to each third bit line of the plurality of third bit lines of a corresponding column segment of the plurality of column segments, and a reference current circuit selectively coupled to each of the plurality of first bit lines and the plurality of second bit lines. The reference current circuit is configured to generate a reference current based on a first current generated by a first reference cell of the plurality of first reference cells programmed to a low logical value and a second current generated by a second reference cell of the plurality of second reference cells programmed to a high logical value, and each sense amplifier of the plurality of sense amplifiers is configured to generate a mirror current based on the reference current, and generate a logical value based on a comparison of the mirror current to a cell current received from a memory cell of a column of the plurality of columns of the corresponding column segment of the plurality of column segments. In some embodiments, the memory array is configured to select a same numbered bit line of the corresponding pluralities of first through third bit lines during a read operation. In some embodiments, the memory array includes a plurality of first word lines, wherein each first word line of the plurality of first word lines is coupled to the memory cells of a corresponding row of a plurality of rows of memory cells of a column segment of the plurality of column segments, and a plurality of second word lines, wherein each second word line of the plurality of second word lines is coupled to the first reference cells of a corresponding row of a plurality of rows of first reference cells of the plurality of columns of first reference cells, and to the second reference cells of a corresponding row of a plurality of rows of second reference cells of the plurality of columns of second reference cells, the the memory array is configured to activate a second word line of the plurality of second word lines when a corresponding first word line of the plurality of first word lines is activated. In some embodiments, each of the pluralities of first through third bit lines includes a total of eight bit lines. In some embodiments, the reference current circuit includes a first NMOS transistor coupled to a ground node, thereby configured to generate a reference voltage based on the reference current, and each sense amplifier of the plurality of sense amplifiers includes a second NMOS transistor coupled to the ground node, thereby configured to generate the mirror current based on the reference voltage. 
     In some embodiments, a data sensing method includes generating a cell current in a memory cell of a sub-segment of a plurality of sub-segments of a column segment of a plurality of column segments of a memory array, generating a first current in a first reference cell of a plurality of first reference cells programmed to a low logical value and a second current in a second reference cell of a plurality of second reference cells programmed to a high logical value, generating a reference current based on the first current and the second current, and using a sense amplifier to mirror the reference current and generate a logical value based on a comparison of the mirror current to the cell current. The sense amplifier is one sense amplifier of a plurality of sense amplifiers, and each sense amplifier is configured to mirror the reference current. In some embodiments, generating the cell current in the memory cell includes activating a first word line of a plurality of first word lines coupled to the column segment of the plurality of column segments, generating the first current in the first reference cell of the plurality of first reference cells includes activating a second word line of a plurality of second word lines coupled to the plurality of first reference cells, and generating the second current in the second reference cell of the plurality of second reference cells includes activating the second word line of the plurality of second word lines further coupled to the plurality of second reference cells. In some embodiments, the method includes conducting the reference current through a first transistor, thereby generating a reference voltage, and using each sense amplifier of the plurality of sense amplifiers to mirror the reference current includes receiving the reference voltage at a gate of a second transistor. In some embodiments, each of generating the cell current in the memory cell, generating the first current in the first reference cell, and generating the second current in the second reference cell includes generating the corresponding current in a flash memory cell. 
     A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, various transistors being shown as a particular dopant type (e.g., N-type or P-type Metal Oxide Semiconductor (NMOS or PMOS)) are for illustration purposes. Embodiments of the disclosure are not limited to a particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. The low or high logical value of various signals used in the above description is also for illustration. Various embodiments are not limited to a particular logical value when a signal is activated and/or deactivated. Selecting different logical values is within the scope of various embodiments. In various embodiments, a transistor functions as a switch. A switching circuit used in place of a transistor is within the scope of various embodiments. In various embodiments, a source of a transistor can be configured as a drain, and a drain can be configured as a source. 
     The above illustrations include exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments.