Patent Publication Number: US-8976091-B2

Title: Organic light emitting diode display and driving method thereof

Description:
This application claims the benefit of Taiwan application Serial No. 100128770, filed Aug. 11, 2011, the subject matter of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates in general to a display and a driving method thereof. 
     2. Description of the Related Art 
       FIG. 1  shows a schematic diagram of a conventional active matrix organic light-emitting diode (AMOLED) pixel. An AMOLED pixel  10  includes a driving transistor MOS_dri, which functions based on an N-type driving approach and implements mostly amorphous silicon (a-Si) and indium gallium zinc oxide (IGZO) back panel techniques. Although a threshold voltage of a-Si and IGZO transistor elements are characterized by having an initial high uniformity, degradation in the threshold voltage is nevertheless resulted after operating the elements for a period of time, such that the elements fail to output a current that is the same as an initial current to lead to mura (i.e., irregularity and inconsistency) in brightness or other issues of the display. 
     Further, an anode of an OLED  12  of the AMOLED pixel  10  is a transparent indium tin oxide (ITO) having a high work function. Thus, during an element manufacturing process, a special procedure is needed to reduce the work function of the ITO in order to obtain a reliable OLED element having preferred characteristics, and so the overall manufacturing process is made more complicated. 
     SUMMARY OF THE INVENTION 
     The disclosure is directed to a display and a driving method thereof. Through a threshold voltage compensation mechanism, under circumstances of a same data input, each organic light-emitting diode (OLED) pixel of the display is able to provide a same output current instead of a current that degrades with time. 
     According to an aspect of the disclosure, a display including a panel is provided. The panel includes multiple OLED pixels, each including an OLED, a driving transistor, a switch transistor, a first compensation block and a second compensation block. The driving transistor has a first terminal coupled to an anode of the OLED, a second terminal for receiving an operating voltage, and a control terminal for receiving a data voltage. The switch transistor has a first terminal coupled to the control terminal of the driving transistor, a second terminal for receiving the data voltage, and a control terminal for receiving a first control signal. The first compensation block is coupled to the first terminal and the control terminal of the driving transistor. The second compensation block is coupled to the first terminal of the driving transistor, and receives the first control signal and the data voltage. 
     According to another aspect of the disclosure, a driving method of a display is provided. The display includes a panel. The panel includes multiple OLED pixels, each including an OLED, a driving transistor, a switch transistor, a first compensation block and a second compensation block. The driving transistor has a first terminal coupled to an anode of the OLED, a second terminal for receiving an operating voltage, and a control terminal for receiving a data voltage. The switch transistor has a first terminal coupled to the control terminal of the driving transistor, a second terminal for receiving the data voltage, and a control terminal for receiving a first control signal. The first compensation block is coupled to the first terminal and the control terminal of the driving transistor. The second compensation block is coupled to the first terminal of the driving transistor, and receives the first control signal and the data voltage. The driving method includes steps below. In a reset phase, the first compensation block is reset, so that the first compensation block has a reference voltage and the data voltage, and the first control signal cuts off the driving transistor via the switch transistor and the second compensation block. In a compensation phase, the second compensation block couples a potential at the first terminal of the driving transistor to a low-level voltage, so that the driving transistor becomes floating on and discharges until cutoff, and the first compensation block maintains a voltage difference between the voltage at the first terminal of the cutoff driving transistor and the reference voltage as well as the data voltage. In a light-emitting phase, the OLED is turned on, so that the first voltage at the terminal of the driving transistor is a driving voltage, and the first compensation block feeds the voltage difference between the reference voltage and the voltage at the first terminal of the driving transistor in the compensation phase as well as the driving voltage back to the control terminal of the driving transistor. 
     According to yet another aspect of the disclosure, a display including a panel is provided. The panel includes multiple OLED pixels, each including an OLED, a driving transistor, a switch transistor, a first compensation block and a second compensation block. The driving transistor has a first terminal coupled to an anode of the OLED, a second terminal for receiving an operating voltage, and a control terminal for receiving a data voltage. The switch transistor has a first terminal coupled to the control terminal of the driving transistor, a second terminal for receiving the data voltage, and a control terminal for receiving a first control signal. The first compensation block is coupled to the second terminal and the control terminal of the driving transistor. The second compensation block is coupled to the second terminal of the driving transistor, and receives the first control signal and the data voltage. 
     The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a conventional AMOLED pixel. 
         FIG. 2  is a schematic diagram of an OLED pixel according to a first embodiment. 
         FIG. 3  is a driving timing diagram of the OLED pixel according to the first embodiment. 
         FIG. 4  is a schematic diagram of an OLED pixel according to a second embodiment. 
         FIG. 5  is a schematic diagram of an OLED pixel according to a third embodiment. 
         FIG. 6  is a driving timing diagram of the OLED pixel according to the third embodiment. 
         FIG. 7  is a schematic diagram of an OLED pixel according to a fourth embodiment. 
         FIG. 8  is a schematic diagram of an OLED pixel according to a fifth embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The disclosure is directed to a display and a driving method thereof. Through a threshold voltage compensation mechanism, under circumstances of a same data input, each OLED pixel of the display is able to provide a same output current instead of a current that degrades with time. 
     The display according to one embodiment includes a panel, a gate driver and a source driver. The panel includes a plurality of OLED pixels. The gate driver is for enabling the OLED pixels. The source driver is for driving the OLED pixels. In the description below, an N-type MOS transistor is taken as an example for explaining the embodiment. It should be noted that the disclosure is not limited to an N-type MOS transistor, and a P-type MOS transistor or a BJT transistor may also be implemented based on actual design requirements.  FIG. 2  shows a schematic diagram of an OLED pixel according to a first embodiment. An OLED pixel  200  includes an OLED  210 , a driving MOS transistor MOS_dri, a switch MOS transistor MOS_sw, a first compensation block  220  and a second compensation block  230 . The driving MOS transistor MOS_dri has a first terminal (a node S) coupled to an anode of the OLED  210 , a second terminal for receiving an operating voltage ELVDD, and a control terminal (a node G) for receiving a data voltage Data. The switch MOS transistor MOS_sw has a first terminal coupled to the control terminal of the driving MOS transistor MOS_dri, a second terminal for receiving the data voltage Data, and a control terminal for receiving a first control signal Sn. 
     The first compensation block  220  is coupled to the first terminal and the control terminal of the driving MOS transistor MOS_dri. The second compensation block  230  is coupled to the first terminal of the driving MOS transistor MOS_dri, and receives the first control signal Sn and the data voltage Data. In a reset phase, the first compensation block  220  is reset and thus has a reference voltage REF and the data voltage Data, and the first control signal Sn cuts off the driving MOS transistor MOS_dri via the switch MOS transistor MOS_sw and the second compensation block  230 . 
     In a compensation phase, the second compensation block  230  couples a potential at the first terminal of the driving MOS transistor MOS_dri to a low-level voltage, such that the driving MOS transistor MOS_dri becomes floating on and discharges until cutoff. Meanwhile, the first compensation block  220  maintains a voltage difference between the voltage at the first terminal of the cutoff driving MOS transistor MOS_dri and the reference voltage REF as well as the data voltage Data. In a light-emitting phase, the first compensation block  220  turns on the driving MOS transistor MOS_dri to drive the OLED  210 , and maintains the voltage difference (between the reference voltage REF and the voltage at the first terminal of the driving MOS transistor MOS_dri in the compensation phase), so as to feed the voltage at the first terminal of the turned on driving MOS transistor MOS_dri back to the control terminal of the turned on driving transistor MOS_dri. 
     In  FIG. 2 , the second compensation block  230  includes a first MOS transistor T 1 . The first MOS transistor T 1  has a first terminal coupled to the first terminal of the driving MOS transistor MOS_dri, a second terminal for receiving the data voltage Data, and a control terminal for receiving the first control signal Sn. The first compensation block  220  includes a second MOS transistor T 2 , a second capacitor C 2 , a third capacitor C 3 , and a third MOS transistor T 3 . The second MOS transistor T 2  has a first terminal fir receiving a reference voltage REF, and a control terminal for receiving a first enable signal En. The level of the reference voltage REF is higher than the level of the data voltage Data. 
     The second capacitor C 2  has a first terminal (a node A) coupled to a second terminal of the second MOS transistor T 2 , and a second terminal coupled to the first terminal of the driving MOS transistor MOS_dri. The third capacitor C 3  has a first terminal coupled to the second terminal of the second MOS transistor T 2 , and a second terminal coupled to the control terminal of the driving MOS transistor MOS_dri. The third MOS transistor T 3  has a first terminal coupled to the first terminal of the third capacitor C 3 , a second terminal coupled to the second terminal of the third capacitor C 3 , and a control terminal for receiving a second enable signal XEn or a second control signal Sn′. 
       FIG. 3  shows a driving timing diagram of an OLED pixel according to the first embodiment. In a reset phase t 1 , the first enable signal En turns on the second MOS transistor T 2 , and the node A is reset to the reference voltage REF; the first control signal Sn turns on the switch MOS transistor MOS_sw and the first MOS transistor T 1 , such that the data voltage Data is placed with a node G and a node S and the driving MOS transistor MOS_dri is cut off. At this point, a cathode voltage ELVSS at a cathode of the OLED  210  swings to a high potential to cut off the OLED  210 . Further, as observed from  FIGS. 2 and 3 , in the reset phase, the OLED pixel  200  is non-existent in a discharging path, inferring that not only unnecessary power consumption is prevented but also IR drop is not incurred when the OLED pixel  200  is applied to a large-size display device. 
     In a compensation phase t 2 , the first control signal Sn cuts off the switch MOS transistor MOS_sw, the potential at the node G is maintained at the data voltage Data, and the potential at the node A is maintained at the reference voltage REF. The first control signal Sn also cuts off the first MOS transistor T 1  and swings to the high-potential cathode voltage ELVSS to cut off the OELD  210 . Further, the potential at the node S is coupled to a low-level voltage V(s) by a parasitic capacitance Cgs 1  of the first MOS transistor T 1 . The low-level voltage can be calculated by an equation (1) below, where Cp is a bypass capacitance associated with the node S:
 
 V ( s )=Data+(Low−High)×(Cgs1/(Cgs1 +C 2 +Cp ))   (1)
 
The voltage difference between the gate voltage of the driving MOS transistor MOS_dry and the threshold voltage can be calculated by an equation (2) below:
 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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     Assuming Low is −10V, High is 10V, and Cgs 1  and C 2  are 0.2 pf, and the bypass capacitance Cp is neglected, the equation (2) may be simplified as Vgs−Vt=10−Vt. Therefore, when the threshold voltage Vt is smaller than 10V, the low-level voltage V(s) prompts the driving MOS transistor MOS_dri to become floating on and to discharge to a cutoff state. At this point, the potential at the node S is a cutoff potential Data−Vt. The voltage difference between the node A and the node S equal to (REF−Data+Vt) is maintained by the second capacitor C 2 . 
     The compensation phase t 2  can substantially be defined by the second enable signal XEn or the second control signal Sn′. In the disclosure, the compensation phase t 2  and a data write period (i.e., the reset phase t 1 ) are independent from each other, so that the time of the compensation phase may be appropriately adjusted instead of being limited to one data write period (i.e., scan line active time). Thus, compensation accuracy is further increased to make the disclosure even more suitable for a large-size, high-resolution display device. 
     In a light-emitting phase t 3 , the first enable signal En cuts off the second MOS transistor T 2 , the second enable signal XEn or the second control signal Sn′ turns on the third MOS transistor T 3 , and charge sharing occurs between the node A and the node G. As a result, the driving MOS transistor MOS_dri is turned on, the cathode voltage ELVSS is restored to a low potential, and the potential at the node S is fed back to the node A by via the second capacitor C 2  to maintain the voltage difference (REF−Data+Vt) in the compensation phase t 2 . At this point, the potential at the node S is Voled, the potential at the node A is (REF+Voled−Data+Vt), and the potential at the node G is the same as that at the node A. Thereof, the gate-source voltage difference of the driving MOS transistor MOS_dry is Vgs=(REF−Data+Vt). An output current I_dry of the driving MOS transistor MOS_dri is as shown in an equation (e), where Kp is ½(μ)(Cox)(W/L), μ is a carrier mobility, Cox is capacitance per unit area, and W/L is a width-length ratio.
 
 I _dri= Kp ×( Vgs−Vt ) 2   =Kp ×(REF−Data) 2    (3)
 
It is observed from the equation (3) that, the output current I_dri of the driving MOS transistor MOS_dri is irrelevant to the threshold voltage Vt and the voltage of the OLED  210 . That is to say, the OLED pixel  200  of the disclosure is capable of compensating the threshold voltage difference of the driving MOS transistor MOS_dri as well as outputting a same current instead of a current that degrades with time under circumstances of a same data input. Meanwhile, the OLED  200  of the disclosure is also capable of compensating the voltage change in the OLED  210 , and has a constant output current that does not change as the voltage of the OLED  210  increases with time under circumstances of a same data input.
 
       FIG. 4  shows a schematic diagram of an OLED pixel according to a second embodiment. An OLED pixel  300  includes an OLED  210 , a driving MOS transistor MOS_dri, a switch MOS transistor MOS_sw, a first compensation block  220 , and a second compensation block  330 . A structure and operation principles of the OLED pixel  300  are similar to those of the OLED pixel  200 , with a main difference being that the second compensation block  330  of the OLED pixel  300  further includes a first capacitor C 1 . The first capacitor C 1  has a first terminal coupled to the first terminal of the driving MOS transistor MOS_dri, and a second terminal coupled to the control terminal of the first MOS transistor T 1 . In the compensation phase, the first signal Sn cuts off the switch MOS transistor MOS_sw and the first MOS transistor T 1 , and the first capacitor C 1  replaces the parasitic capacitance Cgs 1  in  FIG. 2  to couple the potential at the first terminal of the driving MOS transistor MOS_dri to the low-level voltage V(s). C 1  replaces Cgs 1  in the equations (1) and (2), and C 1  is assumed to be 0.2 pf. The driving timing of the OLED pixel  300  is as shown in  FIG. 3 , and shall be omitted herein. 
       FIG. 5  shows a schematic diagram of an OLED pixel according to a third embodiment;  FIG. 6  shows a driving timing diagram of the OLED pixel according to the third embodiment. An OLED pixel  500  includes an OLED  210 , a driving MOS transistor MOS_dri, a switch MOS transistor MOS_sw, a first compensation block  220 , a second compensation block  330 , and a fourth MOS transistor T 4 . A structure and operation principles of the OLED pixel  500  are similar to those of the OLED pixel  300 , with a main difference being that the OLED pixel  500  further includes the fourth MOS transistor T 4 . The fourth MOS transistor T 4  has a first terminal coupled to the anode of the OLED  210 , a second terminal coupled to the first terminal of the driving MOS transistor MOS_dri, and a control end for receiving the second enable signal XEn. As observed from  FIG. 6 , the fourth MOS transistor T 4  separates the OLED  210  from the node S in the reset phase t 1  and the compensation phase t 2 , and electrically connects the OLED  210  with the node S in the light-emitting phase t 3 . Thus, without swinging, the cathode voltage ELVSS is maintained at a low potential. Further, in the OLED pixel  500 , an overall aperture rate of the pixel is favored supposing the third MOS transistor T 3  is controlled only by the second enable signal XEn. 
     As previously stated, the disclosure may also implement a P-type MOS transistor.  FIG. 7  shows a schematic diagram of an OLED pixel according to a fourth embodiment. An OLED pixel  700  includes an OLED  710 , a driving MOS transistor MOS_dri, a switch MOS transistor MOS_sw, a first compensation block  720 , a second compensation block  730 , and a fourth MOS transistor T 4 . The OLED pixel  700  has a circuit structure similar to that of the OLED pixel  500 , and a driving timing same as shown in  FIG. 6 . 
       FIG. 8  shows a schematic diagram of an OLED pixel according to a fifth embodiment. An OLED pixel  800  includes an OLED  810 , a driving MOS transistor MOS_dri, a switch MOS transistor MOS_sw, a first compensation block  820 , a second compensation block  830 , and a fourth MOS transistor T 4 . The OLED pixel  800  has a circuit structure similar to that of the OLED pixel  500 , and a driving timing same as shown in  FIG. 6 , with a main difference being that the level of the reference voltage REF is lower than the level of the data voltage Data. 
     The disclosure further provides a driving method for an OLED pixel. The OLED pixel includes an OLED, a driving transistor, a switch transistor, a first compensation block and a second compensation block. The driving transistor has a first terminal coupled to an anode of the OLED, a second terminal for receiving an operating voltage, and a control terminal for receiving a data voltage. The switch transistor has a first terminal coupled to the control terminal of the driving transistor, a second terminal for receiving the data voltage, and a control terminal for receiving a first control signal. The first compensation block is coupled to the first terminal and the control terminal of the driving transistor. The second compensation block is coupled to the first terminal of the driving transistor, and receives the first control signal and the data voltage. 
     The driving method for an OLED pixel includes steps below. In a reset phase, the first compensation block is reset, so that the first compensation block has a reference voltage and the data voltage, and the first control signal cuts off the driving transistor via the switch transistor and the second compensation block. In a compensation phase, the second compensation block couples a potential at the first terminal of the driving transistor to a low-level voltage such that the driving transistor becomes floating on and discharges until cutoff. Meanwhile, the first compensation block maintains a voltage difference between the voltage at the first terminal of the cutoff driving transistor and the reference voltage as well as the data voltage. In a light-emitting phase, the OLED is turned on, such that the voltage at the first terminal of the driving transistor is a driving voltage, and the first compensation block feeds the voltage difference between the voltage at the first terminal of the driving transistor and the reference voltage as well as the data voltage in the compensation phase back to the control terminal of the driving transistor. 
     Operation principles of the above driving method for an OLED pixel can be appreciated with reference to descriptions associated with  FIGS. 2 to 6 , and shall be omitted herein. 
     It is illustrated in the display and the driving method for the display according to the disclosed embodiments that, the OLED pixel of the display has a self-test capability on the threshold voltage through a threshold voltage compensation mechanism, and feeds back the driving voltage of the driving transistor so that each OLED pixel outputs a same current value instead of a current that degrades with time under circumstances of a same data input. Meanwhile, with the self-test capability on the threshold voltage provided by the threshold voltage compensation mechanism, the driving voltage of the driving transistor is fed back so that an output current of the OLED pixel does not change as the voltage of the OLED increases with time under circumstances of a same data input. 
     Further, as far as each OLED pixel in the disclosed display and the driving method thereof are concerned, in the reset phase, the OLED pixel is non-existent in a discharging path, inferring that not only unnecessary power consumption is prevented but also IR drop is not incurred when the OLED pixel is applied to a large-size display device. Moreover, in the disclosure, the compensation phase and the data write period are independent from each other, so that the time of the compensation phase may be appropriately adjusted instead of being limited to one data write period of a scan line active time. Thus, compensation accuracy is further increased to make the disclosure even more suitable for a large-size, high-resolution display device. 
     While the disclosure has been described by way of example and in terms of the preferred embodiments, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.