Patent Publication Number: US-4097772-A

Title: MOS switch with hysteresis

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to MOS hysteresis switching curcuits. 
     2. Brief Description of the Prior Art 
     MOS buffer circuits have been widely utilized to interface between inputs provided by external circuits and other more complex circuitry which acts in response to the input signals. However, most MOS buffer circuits do not provide very good noise immunity. Various types of latch circuits have been utilized in the prior art MOS buffer circuits, but the noise immunity of such latch circuits has been quite unsymmetrical, and the switching speed in at least one direction has been unsatisfactory considering the amount of power dissipation of such prior art latch circuits. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a simple buffer circuit having more symmetrical noise immunity and rapid switching to both logical states. 
     Briefly described, the invention is a hysteresis circuit. An input of the hysteresis circuit is coupled to an inverting field effect transistor coupled in series with the load circuit of the first inverting circuit. A depletion mode field effect transistor has its drain coupled to the source of the input field effect transistor and its source coupled to a reference voltage conductor. The gate of the depletion mode field effect transistor is coupled to an output of the second inverter circuit. 
     DESCRIPTION OF THE INVENTION 
     Referring to the the FIGURE, hysteresis circuit 10 is coupled between V DD  conductor 16 and ground conductor 15. The voltage V IN  is applied to input 14, which is connected to the gate of MOSFET 17. MOSFET 17 has its drain connected to V DD  and its source connected to node 13. Depletion mode MOSFET 12 has its drain connected to node 13 and its source and gate connected to V SS , also referred to as ground. Depletion mode MOSFET 18 has its drain connected to node 13 and its gate and source connected to node 19. Enhancement mode MOSFET 21 has its source connected to node 20, its drain connected to node 19, and its gate connected to node 23. Depletion mode MOSFET 11 has its gate and source connected to ground, and its drain connected to node 20. Enhancement mode MOSFET 24 has its source connected to ground, its gate connected to node 19, and its drain connected to node 23. Depletion mode MOSFET 22 has its drain connected to V DD , and its gate and source connected to node 23, at which output voltage V OUT  is produced. The following table shows exemplary values for the channel lengths (L) and channel widths (W) for each of the MOSFETs in the FIGURE. 
     
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          Channel    Channel                                              
Device    Width      Length     Ratio                                     
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11        18         12         1.5                                       
12        14         14         1.0                                       
17        200         8         25.0                                      
18        14         14         1.0                                       
21        20          6         3.33                                      
22        10         18         0.56                                      
24        50          6         8.33                                      
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     With these ratios and V DD  = 5 v, typical switching points would be in the range of 1.8 to 3.5 volts, dependent upon process parameter variations. 
     The operation is as follows. Assume that initially V IN  is low. MOSFET 24 is in the &#34;off&#34; condition, and node 23 is high at V DD  volts. MOSFET 21 is in the &#34;on&#34; condition, since node 23 is at V DD  volts. Depletion mode MOSFET 22 maintains node 23 at V DD  volts, since MOSFET 24 is off. The reason that MOSFET 24 is off is that MOSFET 18, being in the &#34;on&#34; condition due to the fact that it is a depletion mode MOSFET having its gate connected to its source, conducts the voltage at node 13 to the gate of MOSFET 24. Since V IN  is low, MOSFET 17 is off, and since MOSFET 12 is a depletion mode device, and is, therefore, always in the &#34;on&#34; condition, node 13 is at ground, thereby holding node 19 at ground through the resistance of MOSFET 18 and thereby holding MOSFET 24 off. V OUT  is therefore at V DD  volts. The circuit stays in this stable condition, with both V IN  low and V OUT  high, until V IN  is increased to the hysteresis point or switching point of hysteresis circuit 10. 
     As V IN  increases toward V DD  volts, MOSFET 17 is turned on, as its threshold voltage is exceeded. The geometry ratios of MOSFETs 17 and 12 are defined such that as V IN  increases, the voltage at node 13 also gradually increases. Due to the coupling effect of depletion mode MOSFET 18, the voltage at node 19 also increases. The geometry ratios of depletion mode MOSFETS 18 and 11 and enhancement mode MOSFET 21 are selected so as to insure that the voltage at node 19 also increases as V IN  as the voltage at node 13 increase. Eventually, the voltage at node 19 increases to the point where MOSFET 24 begins to be turned on hard. This results in the voltage at node 23 being pulled toward ground. This, in turn, results in MOSFET 21 being turned off, since it is an enhancement mode transistor. The voltage at node 19 then begins to rise toward the voltage at node 13. This causes regenerative action resulting in MOSFET 21 being turned off even more rapidly, and in the voltage at node 19 rising yet more rapidly, lowering the voltage at node 23 from V.sub. DD volts to ground. 
     Once MOSFET 24 is turned on, a lower value of V IN  is required than the value of the original hysteresis voltage point in order to turn MOSFET 24 off again. This is due to the fact that depletion mode MOSFETs 18 and 11 and enhancement mode MOSFET 21 form a voltage divider network which is &#34;deactivated&#34; until MOSFET 21 begins to be turned on rather substantially. But once V IN  has been reduced from V DD  volts toward ground to the point at which the voltage on node 19 (which is equal to the voltage on node 13, since MOSFET 21 is off and no current flows through depletion mode MOSFET 18) has reduced the overdrive voltage to MOSFET 24 sufficiently that node 23 rises enough to begin turning MOSFET 21 on, the feedback from node 23 turns MOSFET 21 on, thereby &#34;activating&#34; the above-mentioned voltage divider network and turning enhancement mode MOSFET 21 on harder. This operation results in regenerative switching wherein the voltage at node 13 falls even faster toward ground, and causing MOSFET 24 to be turned off yet faster, by means of depletion mode MOSFET 18. Consequently, once V IN  passes the second hysteresis point, V OUT  rapidly switches from ground to V DD . 
     Use of an enhancement MOSFET for MOSFET 21 provides good 37 tracking&#34; of threshold voltage between MOSFETs 22 and 24. This minimizes the effect of temperature and process variations on circuit performance.