Patent Publication Number: US-10777735-B2

Title: Contact via structures

Description:
DOMESTIC PRIORITY 
     This application is a divisional of U.S. application Ser. No. 16/127,384 entitled “CONTACT VIA STRUCTURES,” filed Sep. 11, 2018 incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     The present invention generally relates to semiconductor integrated circuits, and more particularly, to a contact via structure for back end of line metallization structures. 
     Integrated circuit processing can be generally divided into front end of the line (FEOL), middle of the line (MOL) and back end of the line (BEOL) metallization processes. The FEOL and MOL processing will generally form many layers of logical and functional devices. By way of example, the typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact (CA) formation. Layers of interconnections are formed above these logical and functional layers during the BEOL metallization processing to complete the integrated circuit structure. As such, BEOL metallization processing generally involves the formation of insulators and conductive wiring. Often, the BEOL metallization process can further include fabrication of magnetoresistive random access memory (MRAM) devices, capacitors, resistors and the like. 
     SUMMARY 
     Embodiments of the present invention are generally directed to semiconductor structures including one or more back end of the line metallization layer and methods of fabrication. A non-limiting example of the semiconductor structure including a back end of line (BEOL) metallization structure includes a first interconnect structure. The first interconnect structure includes an interlayer dielectric and one or more metal filled trenches therein. A via structure overlies the first interconnect structure. The via structure includes an interlayer dielectric including at least one metal filled via having a width dimension (W 1 ). A pillar device structure overlies and is in electrical contact with the at least one metal filled via, wherein the pillar structure includes layers of metal and wherein the pillar structure has a width dimension (W 2 ) greater than W 1 . 
     A non-limiting example of a method of fabricating a BEOL metallization structure according to embodiments of the invention includes forming a first interconnect structure by patterning a first dielectric layer to form a trench therein and depositing a metal conductor in the trench, wherein the metal conductor has a top surface coplanar to a top surface of the first dielectric layer. A second dielectric layer is formed on the first interconnect structure and patterned. Patterning the second dielectric layer includes forming a via opening to expose a surface of the metal conductor in the first interconnect structure. The via opening having a width dimension (W 1 ) is filled with a metal to form a metal filled via. Layers of metals and at least one insulating layer are deposited to form a multilayer stack. A metal hardmask is deposited onto the multilayer stack and a dielectric hardmask onto the metal hardmask. The dielectric hardmask and the metal hardmask are patterned to provide a patterned dielectric hardmask and metal hardmask with a width dimension (W 2 ), wherein the patterned dielectric hardmask and metal hardmask overlies the metal filled via. The multilayer stack is etched using an ion beam etch process, wherein the width dimension W 2  of the patterned dielectric hardmask and metal hardmask is greater than the width dimension W 1  of the metal filled via. 
     A non-limiting example of a method of fabricating a BEOL metallization structure includes forming a first interconnect structure by patterning a first dielectric layer to form a trench therein and depositing a metal conductor in the trench. The metal conductor has a top surface coplanar to a top surface of the first dielectric layer. A second dielectric layer is deposited onto the first interconnect structure. A trilayer is formed on the second dielectric layer. The trilayer includes an organic planarization layer, a Si-containing mask layer, and a photoresist layer. The photoresist layer is patterned to form a via opening having a width dimension (W 1 ). A tapered profile is formed by patterning the Si-containing mask layer to the organic planarizing layer, wherein a top opening in the Si-containing mask layer has the width dimension W 1  and a bottom opening in the Si-containing mask layer has a width dimension (W 2 ), wherein W 1  is greater than W 2 . The organic planarizing layer is etched to form a via opening having the width dimension W 2 . The second dielectric is reactive ion etched to form a via opening and expose a surface of the metal conductor in the first interconnect structure, wherein the via opening in the second dielectric layer has the width dimension W 2 . The via opening is filled with a metal to form a metal filled via. Layers of metals and at least one insulator material are deposited to form a multilayer stack. A metal hardmask is deposited onto the multilayer stack. A dielectric hardmask is deposited onto the metal hardmask. The dielectric hardmask and the metal hardmask are patterned to provide a patterned dielectric hardmask and metal hardmask with a width dimension W 3 , wherein the patterned dielectric hardmask and metal hardmask overlies the metal filled via. The multilayer stack is etched using an ion beam etch process, wherein the multilayer stack has the width dimension W 3  and the multilayer stack completely covers, the metal filled via. 
     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  depicts a cross section of a prior art structure for forming a pillar device structure on a metal landing pad prior to patterning of the multilayer structure; 
         FIG. 2  depicts a cross section of a prior art structure for forming a pillar device structure on a metal landing pad subsequent to patterning the pillar device structure; 
         FIG. 3  depicts a cross section of a structure including a first interconnect structure in accordance with one or more embodiments of the present invention; 
         FIG. 4  depicts a cross section of the structure of  FIG. 3  subsequent to via patterning of a dielectric layer in accordance with one or more embodiments of the present invention; 
         FIG. 5  depicts a cross section of the structure of  FIG. 4  subsequent to metal fill of the via and planarization in accordance with one or more embodiments of the present invention; 
         FIG. 6  depicts a cross section of the structure of  FIG. 5  subsequent to deposition of a multilayer structure including hardmask layers thereon in accordance with one or more embodiments of the present invention; 
         FIG. 7  depicts a cross section of the structure of  FIG. 6  subsequent to patterning of the hardmask layers in accordance with one or more embodiments of the present invention; 
         FIG. 8  depicts a cross section of the structure of  FIG. 7  subsequent to patterning the multilayer structure to form a pillar device structure in accordance with one or more embodiments of the present invention; 
         FIG. 9  depicts a cross section of a structure subsequent to deposition of a trilayer on a first interconnect structure in accordance with one or more embodiments of the present invention; 
         FIG. 10  depicts a cross section of the structure of  FIG. 9  subsequent to patterning a photoresist layer in the trilayer to form a tapered profile in accordance with one or more embodiments of the present invention; 
         FIG. 11  depicts a cross section of the structure of  FIG. 10  subsequent to transferring the opening in the photoresist layer to an underlying organic planarization layer in accordance with one or more embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention generally relates to BEOL metallization structures and processes that include multilayered structures, also referred to herein as pillar device structures, with alternating layers of metals and insulators, e.g. oxides, electrically coupled an underlying landing pad which in turn is electrically coupled an underlying interconnect line, i.e., conductor, wherein the landing pad has a smaller width dimension than the interconnect line and the pillar device structure. 
     Prior pillar device structures formed during BEOL metallization processing included a landing pad, or in some cases did not include a landing pad and these structures were formed directly onto a bottom electrode, which typically had a width that was equal to or greater than the pillar device structure and the underlying conductor. One of the problems with these prior art pillar device structures is that patterning the pillar device structure, which is typically done by ion beam etching, results in resputtering (i.e., redeposition) of underlying landing pad or interconnect metals onto the sidewalls of the pillar device structure. In the case of pillar device structures that include insulating barrier or highly resistive layers, such metal redeposition on the sidewalls of those layers can result in shorts or shunt conduction paths, and hence can impact device yields. Prior art represented by  FIGS. 1-2  illustrate a typical process for forming the pillar device structure. In  FIG. 1 , there is shown a cross section of a portion of a back end of the line structure  10  including a dielectric layer  12 . A conductor  14  is formed in the dielectric using lithographic processing, which further includes a relatively large landing pad  16 , which is also from of a conductive metal. The resulting structure is typically subjected to a planarization process such as chemical-mechanical planarization in which an abrasive slurry is applied by a rotating platen to form a planar surface. A pillar device structure  18  including alternating layers of metal and an insulator are then deposited onto the planar surface. A metal hard mask  20  and a dielectric hardmask  22  are then deposited on the pillar device structure  18  and patterned, which will be used to define the width of the pillar device structure. 
     Prior Art  FIG. 2  illustrates a cross section subsequent to patterning the pillar device structure  18  using an anisotropic etch process such as a combination of reactive ion etching (RIE) including a high sputtering component, or followed by non-reactive ion beam etching (IBE). In the RIE sputtering or IBE processes, materials are removed from the etch target by bombardment with directed and precisely controlled ion energies resulting in high precision removal. One of the problems with RIE sputtering or IBE of pillar device structures including alternating layers of metal and formed on a landing pad is that landing pad metal  24  can be redeposited onto the sidewalls of the pillar device structure, which can significantly degrade the pillar device performance and yields. 
     In the present invention, the landing pad is smaller than the intended width of the pillar device structure, which prevents metal redeposition during IBE. The smaller landing pad can even be sublithographic in width or diameter, by the inventive method. Thus in the present invention, the landing pad is not exposed during patterning of the pillar device structure, and only insulating material  12  can be redeposited on the pillar device structure&#39;s surface. 
     It is to be understood that the embodiments of the invention described herein are merely illustrative of the structures that can be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features can be exaggerated to show details of particular components. Therefore, specific structural and functional details described herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present description. For the purposes of the description hereinafter, the terms “upper”, “lower”, “top”, “bottom”, “left,” and “right,” and derivatives thereof shall relate to the described structures, as they are oriented in the drawing figures. The same numbers in the various figures can refer to the same structural component or part thereof. 
     As used herein, the articles “a” and “an” preceding an element or component are intended to be nonrestrictive regarding the number of instances (i.e. occurrences) of the element or component. Therefore, “a” or “an” should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular. 
     As used herein, the terms “invention” or “present invention” are non-limiting terms and not intended to refer to any single aspect of the particular invention but encompass all possible aspects as described in the specification and the claims. 
     Conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. 
     Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
     It is to be understood that the various layers and/or regions shown in the accompanying drawings are not drawn to scale, and that one or more layers and/or regions of a type commonly used in complementary metal-oxide semiconductor (CMOS) fabrication techniques, fin field-effect transistor (FinFET) devices, metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and/or other semiconductor fabrication techniques and devices, may or may not be explicitly shown in a given drawing. This does not imply that the layers and/or regions not explicitly shown are omitted from the actual devices. In addition, certain elements could be left out of particular views for the sake of clarity and/or simplicity when explanations are not necessarily focused on the omitted elements. Moreover, the same or similar reference numbers used throughout the drawings are used to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. 
     The semiconductor devices and methods for forming same in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention can include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention. 
     The embodiments of the present invention can be used in connection with semiconductor devices that could require, for example, CMOSs, MOSFETs, and/or FinFETs. By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology. 
     The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus. 
     As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. Yet, in another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value. 
     It will also be understood that when an element, such as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present, and the element is in contact with another element. 
     As used herein, the term “substrate” can include a semiconductor wafer, such as a type IV semiconductor wafer, e.g., silicon wafer, or a type III-V semiconductor wafer, such as a compound semiconductor, e.g., gallium arsenide semiconductor wafer. In one or more embodiments, a number of dielectric layers and semiconductor material layers can be arranged with the substrate to provide microelectronic devices, or smaller devices, which can include semiconductor devices, such as field effect transistors (FETs), fin type field effect transistors (FinFETs), bipolar junction transistors (BJT) and combinations thereof. The at least one device layer can also include memory devices, such as dynamic random access memory (DRAM), embedded dynamic random access memory (EDRAM), flash memory and combinations thereof. The at least one device layer can also include passive devices, such as resistors and capacitors, as well as electrical connections to the devices containing within the at least one device layer. 
     It should also be noted that not all masking, patterning, and lithography processes are shown, because a person of ordinary skill in the art would recognize where masking and patterning are utilized to form the identified layers and openings, and to perform the identified selective etching processes, as described herein. 
     Turning now to  FIGS. 3-7  schematically illustrated is a process flow for forming an integrated circuit including at least one patterned pillar device structure including alternating layers of metal and an insulator. 
     In  FIG. 3 , there is shown a portion of an integrated circuit including a BEOL metallization structures  100  including a first dielectric layer, e.g., an interlayer dielectric, a conductor  104 , e.g., a line, formed in the interlayer dielectric, and a second dielectric layer  106  formed on a planar surface of conductor  104  and first dielectric layer  102 . 
     Typically, the substrate is subjected to a planarization process subsequent to deposition of the conductor, which usually includes the formation of an overburden. By way of example, the surface can be planarized using an electropolishing process. In an electropolishing process, small amounts of metal are etched by electroetch or electrochemical etching to provide the conductor  104  with a top metal surface generally coplanar to the top surface of the first dielectric  102 . In another embodiment, the planar surface is formed by chemical mechanical polishing (CMP). The CMP process planarizes the surface of the interconnect structure by a combination of chemical and mechanical etching using multi-step polishing with selective and non-selective slurry compositions generally known in the art. Alternatively, a planar surface can be formed by a non-selective plasma etching process, termed “etchback”. The etchback process can include additional planarizing layers deposited onto metal layer. For example, a layer of photoresist can be deposited onto metal layer prior to performing the non-selective etch process. 
     The first and second dielectrics  102 ,  106  can be any low k (i.e., k value less than 3.9) or oxide dielectric material (k ˜4.0) including inorganic or organic dielectrics. The dielectric material can be porous or non-porous. Some examples of suitable dielectrics that can be used as the dielectric material include, but are not limited to: SiO 2 , silsesquioxanes, carbon doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof. The term “polyarylene” is used to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like. The first and second dielectrics  102 ,  106 , respectively, can be the same or different and can be deposited by PECVD procedures as is generally known in the art. 
     The conductor  104  can be copper, but can be any suitable conductor including, but not limited to copper, aluminum, tungsten, alloys thereof, and mixtures thereof. In some structures, copper can be used and can include an alloying element such as C, N, O, Cl, S, Mn, Al, etc. which have been shown to improve the reliability of the copper conductor. The amount of alloying element in the copper alloy is typically in the range of about 0.001 weight percent (wt. %) to about 10 wt %). 
     The conductor  104  can be formed by CVD, PVD (sputtering), electrochemical deposition or like processes. For example, the deposition of copper can be done by electroplating or electroless plating as are known in the art. 
     Optionally, a conformal seed layer (not shown) can be deposited prior to deposition of the conductor. The function of the seed layer is to provide a base upon which the metal conductor can be deposited. The seed layer can be formed by one or more methods known to those skilled in the art. For example, the seed layer can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or some variation of these two deposition processes. The seed layer can also be formed electrochemically or by an electroless process. In the case of PVD, the seed layer can be deposited by reactive or non-reactive sputtering from a single alloy target, or from multiple targets, by ionized sputtering. 
     The composition of the one or metals in the deposited seed layer is typically from 1 atomic percent to about 10 atomic percent. In some embodiments, the deposited seed layer will contain from about 1 atomic percent to about 7 atomic percent. Examples of seed layers are copper, copper manganese, and the like. 
       FIG. 4  schematically illustrates the structure  100  of  FIG. 3  subsequent to formation of a via opening  108  in the second dielectric  106  to the conductor  104 . 
       FIG. 5  schematically illustrates the structure  100  of  FIG. 4  subsequent to deposition of a metal  110  to fill the via opening followed by planarization to form a top planar surface. Suitable metals for filling the via opening include, without limitation, tungsten, aluminum, copper, tantalum, titanium, cobalt, ruthenium, iridium, rhodium, alloys thereof, nitrides thereof, and combination of at least one of the foregoing. 
       FIG. 6  schematically illustrates the structure  100  of  FIG. 5  subsequent to deposition of a pillar device structure  112  including combinations of metal layers and insulating layers such as various metal oxides onto the planar surface. The pillar device structure overlies the metal filled via  110 . Hard mask layers including a metal layer  114 , and a dielectric layer  116  are then deposited onto the pillar device structure  112 . 
     The dielectric hardmask layer  116  is not intended to be limited to any particular material so long as the dielectric hardmask functions is selective during a later RIE or IBE process to pattern the pillar device structure  112  as will be described in greater detail below. Exemplary dielectric hard mask material include, without limitation, silicon dioxide, silicon nitride, silicon carbide, and the like. 
     The metal hardmask is not intended to be limited, and can be a metal nitride such as tantalum nitride, titanium nitride, tungsten nitride, or the like. In one or more embodiments, the metal hardmask can be incorporated into the pillar device structure and function as a top electrode. 
       FIG. 7  schematically illustrates the structure  100  of  FIG. 6  subsequent to lithographic plus RIE patterning of the dielectric hardmask  116  and underlying metal hardmask  114 . Lithographic patterning generally includes applying a photoresist to the surface of the dielectric hardmask, exposing the photoresist to a desired pattern of radiation, and developing the exposed resist utilizing a photoresist developer to form a pattern. The photoresist pattern is then transferred into the dielectric hardmask using an etching process such as RIE. The etching process can be a dry or wet etching process. 
     The term “wet etching” generally refers to application of a chemical solution. This is preferably a time controlled dip in the etch solution. Preferred etch solutions include HNO 3 , HCL, H 2 SO 4 , HF or combinations thereof. 
     The term “dry etching” is used here to denote an etching technique such as reactive-ion-etching (RIE), ion beam etching, plasma etching or laser ablation. During the etching process, the pattern is first transferred to the dielectric layer. The patterned photoresist is typically, but not necessarily, removed from the structure after the pattern has been transferred into the dielectric film. The patterned feature formed into the dielectric material includes the contact holes. 
     The lithographic and etching process is repeated for patterning the metal hardmask  114 . 
       FIG. 8  schematically illustrates the structure  100  of  FIG. 7  subjected to RIE or IBE to patterning of the pillar device structure down to the insulating layer  106 . Because the hardmask layers  116  and  114  have a width dimension greater than the filled via  110 , and because the IBE process is highly directional, there is no metal redeposition onto sidewalls of the pillar device structure. Instead, the IBE process stops on the insulator layer  106 , and some of this insulating material can be re-deposited onto the pillar device structure sidewalls without detrimental electrical effects. The resulting structure  100  features a metal landing pad, i.e., the filled via  110 , having a critical dimension smaller than the hardmasks  116  and  114 . The metal landing pad, i.e., filled via  110 , is completely covered by the pillar device structure  112  such that the landing pad is not exposed during IBE, thereby eliminating metal redeposition. 
       FIGS. 9-11  schematically illustrate a process for forming the via opening in the insulating layer in accordance with one or more embodiments. The process can be subsequent to formation of the initial structure as shown in  FIG. 3 .  FIG. 9  schematically illustrates the cross section of structure  100  of  FIG. 3  subsequent to deposition of a trilayer. The trilayer includes an organic planarization layer  150  deposited onto the insulation layer  106 , a Si-containing mask layer  152  deposited onto the organic planarization layer  150 , and a photoresist layer  154  on the Si-containing mask layer  152 . The photoresist layer is patterned to form an opening  156  having a defined “lithographic” width (W 1 ). 
     The planarization layer  150  can be a polymer including carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. In one or more embodiments, the planarization layer  150  is a polymer with sufficiently low viscosity so that the top surface of the applied polymer forms a planar horizontal surface. The planarization layer  150 , which can be a spin-deposited layer, can be baked at an elevated temperature to cure the planarization layer, if needed, and reflow its top surface into a substantially planar form. Exemplary materials defining the organic planarizing layer that can be employed in the invention include, but are not limited to: diamond-like carbon (DLC), fluorinated DLC, polyimides, fluorinated polyimides, parylene-N, parylene-F, benzocyclobutanes, poly(arylene ethers), polytetrafluoroethylene (PTFE) derivatives marketed by Du Pont de Nemours, Inc. under the registered trademark Teflon AF, poly(naphthalenes), poly(norbornenes), foams of polyimides, organic xerogels, porous PTFE and other nano-, micro- or macro-porous organic materials. 
     The Si-containing mask layer  152  can serve as a mask to pattern the underlying layer. The Si-containing mask layer is not intended to be limited and can include a low-temperature oxide (SiO 2 ), a Si-containing antireflection layer (SiARC), or other polymeric layers of polyelectrolyte and colloidal particles, sol-gels produced through reactions of modified silanes and organic solvents, or conductive polymers. 
     The photoresist layer  154  can be formed using conventional deposition techniques such chemical vapor deposition, plasma vapor deposition, sputtering, dip coating, spin-on coating, brushing, spraying and other like deposition techniques can be employed. Following formation of the photosensitive resist layer, the photosensitive resist layer is exposed to a desired pattern of radiation such as ultraviolet radiation, vacuum ultraviolet radiation, extreme ultraviolet (EUV) radiation, X-ray radiation, electron beam radiation or the like. Illustrative examples of 193 nm vacuum ultraviolet photosensitive resist layers include a methacrylate polymer, a phenolic based polymer or a copolymer thereof. Other types of organic photoresists such as, for example, polyesters can also be employed. 
       FIG. 10  schematically illustrates the structure  100  of  FIG. 9  subsequent to patterning of the Si-containing mask layer  152  and the organic planarizing layer  150 . A tapered profile in layer  152  as shown can be made using a partially-polymerizing RIE process. The opening at the bottom of the Si-containing mask layer has a width dimension (W 2 ) less than W 1 . At least one etch process can be employed to transfer the pattern from the tapered Si-containing mask layer into the organic planarization layer  150  and form the opening having the width dimension W 2  with substantially vertical sidewalls in the layer  150 . The etching process can be a vertical dry etch (e.g. oxidizing RIE, plasma etching, ion beam etching, or laser ablation). During transfer of the pattern into layer  150  by oxidizing RIE, for instance, the patterned photoresist layer  154  is simultaneously removed. After transfer of the pattern into layer  150  by a non-oxidizing dry etch, for instance, a second etch step can be used to remove the photoresist layer  154 . 
       FIG. 11  schematically illustrates the structure  100  of  FIG. 10  subsequent to etching of the insulating layer  106  to the conductor  104 . The etching process can be a dry etch (e.g., reactive ion etching, plasma etching, ion beam etching, or laser ablation) and/or a wet chemical etch (e.g., (KOH)). During this etch process and in subsequent steps, the remaining layers  152  and  150  from the original trilayer are removed from the structure  100 , which can be further processed as exemplified in  FIGS. 5-8 . 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments of the invention described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments of the invention. The terminology used herein was chosen to best explain the principles of the embodiments of the invention, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments of the invention described herein.