Patent Publication Number: US-6909318-B2

Title: CMOS voltage booster circuit

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This application is a continuation-in-part of commonly assigned U.S. patent application Ser. No. 10/337,053 entitled CMOS Voltage Booster Circuits filed Jan. 6, 2003 now U.S. Pat. No. 6,864,738. 

   FIELD OF THE INVENTION 
   The present invention is generally related to voltage boosting circuits, and more particularly to pre-charging voltage boosting circuits. 
   BACKGROUND OF THE INVENTION 
     FIG. 1  illustrates at  10  the concept of voltage boosting. The purpose of a voltage booster is to generate a specified voltage higher than VDD at node V-boosted, where VDD is the power supply voltage. A voltage booster basically contains two parts: a pre-charge circuit and a boosting capacitor (C boost). Before node Boost_Ct 1  is pulled to high, the pre-charge circuit charges node Ncb to some positive voltage. Then, node Boost_Ct 1  is pulled to VDD and switch S 1  is turned on to charge load capacitor C_load to a voltage level above VDD. This boosted voltage level is determined by the voltage at node Ncb before Boost_Ct 1  goes high and the ratio of C_boost/C_load. The lower the pre-charged voltage at node Ncb, the larger the capacitance ratio is needed, and the larger the area cost for capacitor C_boost. Thus, it is best to pre-charge node Ncb to VDD before Boost_Ct 1  starts going high. 
   There are four ways known in the prior art of voltage boosters to pre-charge C_boost to VDD: 
   1) As shown in U.S. Pat. Nos. 5,999,461 and 4,186,436, when the boosted voltage is needed, the pre-charge circuit is enabled, but Boost_Ct 1  is not pulled to high until node Ncb is charged to VDD. Obviously, the major disadvantage is that some delay must be introduced. Thus, this scheme is not applicable to high speed devices. 
   2) As shown in U.S. Pat. Nos. 6,268,761 and 6,275,425, PMOS transistors are used to pre-charge node Ncb to VDD and keep the voltage at VDD during standby. The disadvantage is that the sizes of the PMOS transistors are huge when capacitor C_boost is large and pre-charging must be completed in a short time. 
   3) As shown in U.S. Pat. Nos. 5,175,448 and 5,636,115, NMOS transistors with their gate boosted above VDD are used to pre-charge node Ncb to VDD during standby. The advantage of using NMOS transistors is that the sizes of the transistors can be much smaller due to the higher drive capability of NMOSFET than PMOSFET. However, the voltage at node Ncb cannot be kept at VDD for a long time due to various leakages. When the voltage at node Ncb decreases, the size of capacitor C_boost must be increased in order to boost the voltage to the same level. 
   4) As shown in U.S. Pat. No. 5,701,096 charge pumps are used to continuously supply charge to capacitor C-boost and keep the voltage at some level. However, complex timing and control circuits must be introduced. 
   In one conventional memory application, a voltage booster is needed to boost the word line above VDD to VDD+Vthn, and the memory access time is about 11 ns. This means that there is no time for pre-charging the boosting capacitor after the chip is enabled, and the cycle time is about 20 ns. Thus, the boost capacitor must be quickly pre-charged to VDD as soon as the memory access is terminated. In the technique described in 3) above, the NMOS transistors are used as pre-charge devices. The boost capacitor is huge (60 pf) because the voltage on the booster capacitor decreases to a level below VDD due to the leakages. Furthermore, it takes a long time to pre-charge the boost capacitor to VDD due to the huge size. 
   SUMMARY OF THE INVENTION 
   The embodiments of the present invention take the advantages of both PMOS and NMOS transistors. A NMOS transistor with its gate boosted above VDD to VDD+Vthn is used to quickly charge the boosting capacitor to VDD at the end of each memory access and two small PMOS transistors connected back-to-back are used to keep the voltage at VDD during standby. This combination provides high speed with small devices and meets the voltage requirements. Compared the capacitor size is reduced from 60 pf to 10 pf, the power consumption is reduced by 76% during a memory access, and the boosting speed is significantly improved. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic depicting conventional voltage boosting; 
       FIG. 2  is a schematic of one embodiment of the CMOS voltage booster according to the present invention; 
       FIG. 3  is a graph of voltage VPWR with a 5 pf load capacitor; 
       FIG. 4  is a graph of various voltages illustrating that the voltage of node pg is the same potential as node VPWR during boosting; 
       FIG. 5  is a graph exhibiting the voltages of VPWR and pg during two memory accesses; 
       FIG. 6  is a graph of the voltage sequence for boosting the gate of NMOS transistor MN 1 ; 
       FIG. 7  is a schematic of a second embodiment of the CMOS voltage booster according to the present invention; 
       FIG. 8  is a graph of VPWR with a 5 pf load capacitor for the embodiment of  FIG. 6 ; and 
       FIG. 9  is a graph of the voltage of node pg and node VPWR, where transistor MP 3  effectively shorts nodes pg and VPWR, and turns transistor MP 1  off during boosting. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Referring now to  FIG. 2  there is shown a detailed electrical schematic of a first preferred embodiment of the present invention being a CMOS voltage booster  20 . This circuit  20  keeps the voltage of node VPWR at VDD when signal ENVPWR is low and boosts the voltage of node VPWR above VDD to VDD+Vthn as soon as possible when signal ENVPWR becomes high, where VDD is the power source voltage and Vthn is the threshold voltage of a NMOS FET. Capacitor C 1  is the main voltage booster capacitor which advantageously boosts the voltage at node VPWR when node inv 2  becomes high. NMOS FET MN 1  charges capacitor C 1  to VDD and PMOS transistors MP 1  and MP 2  keep the VPWR voltage at VDD during standby. 
   An application of this circuit  20  is to boost the voltage at a word line of a memory device above VDD to VDD+Vthn when signal ENVPWR is pulled to VDD and node VPWR is connected to the word line during a memory access. 
   Circuit  20  provides technical advantages by taking advantage of higher drive ability of a NMOS FET than a PMOS FET, whereby NMOSFET MN 1  with its gate ng boosted above VDD to VDD+Vthn is used to quickly charge the boosting capacitor C 1  to VDD at the end of each memory access. However, the NMOSFET MN 1  cannot keep the voltage at capacitor C 1  at VDD for a long time and thus the voltage at VPWR will eventually decrease to a level below VDD due to various leakages. To overcome this, two small PMOS transistors MP 1  and MP 2  are advantageously provided to keep the voltage of node VPWR at VDD during standby. This combination takes both the advantages of NMOS and PMOS transistors to reach high speeds with small devices and also meet the voltage requirements over time. 
   Moreover, the gate of NMOSFET MN 1  is boosted above VDD to VDD+Vthn by a small capacitor C 2  at the end of each memory access. The gate of NMOSFET MN 2  is connected to node VPWR. When node VPWR is boosted above VDD to VDD+Vthn during a memory access, the gate of NMOSFET MN 2  is boosted to the same voltage and capacitor C 2  is charged to VDD by NMOSFET MN 2 . Advantageously, no separate timing control and boosting circuits are needed for boosting the gate of NMOSFET MN 2  with this design. 
   In addition, the gates of the PMOS transistors MP 1  and MP 2  are advantageously boosted by small capacitors C 3  and C 4  to a voltage close to the voltage at node VPWR to turn MP 1  off when node VPWR is boosted above VDD by capacitor C 1 . 
   Advantageously, the moment that signal ENVPWR starts going high, node inv 0  is still low. NMOSFET MN 4  shunts node tell to low and NMOSFET MN 3  charges capacitor C 3  to some positive voltage. Similarly, NMOSFET MN 4  charges node tell to some positive voltage when node inv 2  is still low. Finally, when node inv 2  becomes high, node VPWR and node pg are boosted above VDD at the same time. Thus, no separate timing control circuit is needed for boosting the gate of PMOS transistor MP 1 . 
   In addition, by simply tying the gates of NMOS transistors MN 3  and MN 4  to VDD, these two transistors are able to play two functions: discharge nodes pg and tell to ground when signal ENVPWR is low and isolate nodes pg and tell from nodes ENVPWR and inv 0  when signal ENVPWR is high and nodes pg and tell are boosted above VDD. 
   Moreover, in this voltage booster circuit  20 , the voltages at some nodes are boosted to a level higher than VDD and may cause some breakdown. Thus, the maximum gate voltage stress is an important reliability issue in any booster circuit. A big advantage for this circuit  20  is that the voltage applied between gate and source is always lower than VDD for all the transistors in the circuit  20 . Thus, the maximum gate stress is always within the safe region. 
     FIG. 3  graphically shows at  30  the voltage VPWR at node VPWR from spice simulation for a nominal process, room temperature and VDD=1.3V, with a 5 pf load capacitor connected to the VPWR. As shown at  32 , when signal ENVPWR becomes high, node VPWR can be boosted above 2.1V. When signal ENVPWR becomes low at the end of an access, the voltage at node VPWR can be recovered to VDD within 3 ns and kept at VDD. 
   As shown in  FIG. 4 , when signal ENVPWR starts going high at 10 ns, voltage Vpg at node pg starts going up. After a slight delay node tell starts going up. At about 10.4 ns, node inv 2  starts going up. At this moment, the voltage at node pg is about 0.7V. At about 11.1 ns, node inv 2  reaches VDD, and the voltages at VPWR and pg are boosted to above 2.1V and 1.9V, respectively. 
     FIG. 5  shows the voltages at node VPWR and node pg during two memory accesses. The voltage difference between node VPWR and node pg is less than 0.2V, thus transistor MP 1  is kept off during boosting. At the end of boosting, node pg is quickly discharged to ground and transistors MP 1  and MP 2  are fully turned on to help charging of node VPWR back to VDD. 
   The voltages shown in  FIG. 6  exhibit the sequence of boosting the gate of NMOS transistor MN 1 . When signal ENVPWR becomes high, node inv 1  goes low after a slight delay. Node ng is pulled below VDD. Note that this dip only occurs during the first memory access. After that, the capacitor C 2  will be charged to VDD during each memory access. After a small delay, node inv 2  goes high and boosts node VPWR above VDD to VDD+Vthn. Since the gate of NMOS transistor MN 2  is connected to node VPWR, NMOS transistor MN 2  is fully turned on and drives node ng to VDD. NMOS transistor MN 1  is off and capacitor C 2  is charged to VDD. When signal ENVPWR becomes low, node inv 1  goes high after a slight delay and capacitor C 2  boosts the gate of NMOS transistor MN 1  above VDD to VDD+Vthn. NMOS transistor MN 1  is fully turned on and quickly drives node VPWR back to VDD. 
   Referring now to  FIG. 7 , there is shown a second preferred embodiment of the present invention, which is similar to the first preferred embodiment shown and described in reference to  FIG. 2 , wherein like numerals refer to like elements. 
   In the circuit  40 , the small boost capacitors C 3  and C 4  are not utilized, and a PMOS FET MP 3  shorts the output line VPWR to low at the moment voltage ENVPWR starts going high and node INV 1  is still low. Similarly, transistor MP 3  allows output line VPWR to achieve a positive voltage when node INV 2  is still low. When node INV 2  becomes high, VPWR and node pg are boosted above VDD at the same time. Advantageously, no separate timing control circuit is needed for boosting the gate of transistor MP 1 . The gate of transistor MN 3  is tied to high, such that transistor MN 3  discharges node pg to ground when control signal ENVPWR is low and isolates node INV 1  from ENVPWR when ENVPWR is high and node pg is boosted above VDD. 
   Like the circuit  10  of the first embodiment, circuit  40  prevents breakdown of transistors when boosting some nodes, including node pg, above VDD. Thus, the maximum gate voltage stress in the boost circuit is controlled providing a reliable circuit. Advantageously, all the transistors in circuit  40  are configured such that a voltage applied between the respective gate and source is always lower than VDD, and the maximum gate stress is always within the safe region. 
     FIG. 8  is a graph of signal VPWR of circuit  40  with a 5 pf load capacitor. 
     FIG. 9  is a graph of the voltage of node pg and node VPWR where transistor MP 3  effectively shorts nodes pg and VPWR, and turns transistor MP 1  off during boost. 
     FIG. 6  also represents the voltage sequence for boosting the gate of NMOS transistor MN 1  of circuit  40 . 
   Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.