Patent Publication Number: US-7899857-B2

Title: CPU datapipe architecture with crosspoint switch

Description:
FIELD OF THE INVENTION 
     This invention relates generally to a central processing unit (“CPU”) architecture. More particularly, this invention relates to a reconfigurable CPU within an Application Specific Integrated Circuit (“ASIC”). 
     BACKGROUND 
     Large-scale (multi-million gate) application specific integrated circuit (“ASIC”) designs are hampered by many logistical problems. Many of these problems are related to the functional integration, timing, reprogramming and testing of various ASIC sub-modules. If sub-module design changes or replacements are required to remedy top-level operational issues, or to provide differing functional capabilities, costly delays and recursive design changes can result. Design changes of this nature drive up engineering, manufacturing and test costs for ASIC manufacturers, and limit the applicability of a given ASIC design. 
     Stated differently, ASIC designs typically have limited reconfigurability at the module or sub-module level, which is to say they may be programmable via control registers, but they typically use fixed architectures. These fixed architectures do not allow for functional modules to be re-arranged or reconfigured by a user. Certain ASICs, such as field programmable gate arrays (“FPGAs”), permit the user to reconfigure or reprogram functional modules, however, they are an extreme example which require a great deal of specialized programming and a special, fine-grained ASIC architecture to implement. 
     Within the current state of the art for ASIC design, manufacture, and test, there does not exist a processing unit or means for efficiently and quickly reprogramming functional modules. Hence there is a need for an advanced ASIC processing architecture to address one or more of the drawbacks identified above. 
     SUMMARY 
     The central processing architecture herein disclosed advances the art and overcomes problems articulated above by providing a reconfigurable processing element, for matrix operations, within an application specific integrated circuit. 
     In particular, and by way of example only, according to an embodiment, provided is a programmable element for data processing including: a signal input formatter structured and arranged to receive and format an input signal from a host unit; a signal output formatter operable to format and output a manipulated signal to the host unit; a plurality of multi-stage signal processing modules coupled between the signal input formatter and the signal output formatter, wherein each stage of each multi-stage signal processing module comprises; at least one data manipulation module operable to manipulate the input signal; a crosspoint switch positioned to facilitate receipt of the input signal, parallel distribution of the input signal to the at least one data manipulation module, and transmittance of the manipulated signal to the signal output formatter; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals; and a host interface. 
     In another embodiment, provided is a processing unit for an application specific integrated circuit including: a host input interconnect operable to receive an input signal from a host; one or more programmable matrix elements, wherein each programmable matrix element comprises one or more signal input formatters structured and arranged to format the input signal; one or more multi-stage programmable signal processing modules structured and arranged to perform multiple, parallel data manipulation operations on the formatted input signal; one or more host interface modules positioned to provide control registers, memory access, and interrupt management functions for each stage of each multi-stage programmable signal processing modules; one or more signal output formatters structured and arranged to output a manipulated signal; and a host output interconnect operable to output the manipulated signal to the host. 
     In still another embodiment, provided is a processing unit for an application specific integrated circuit including: a means for interfacing with a host unit to receive an input signal therefrom; a programmable means for manipulating, in parallel, data from the input signal to perform one or more matrix operations on real and complex numbers; and a means for outputting to the host a manipulated signal. 
     In yet another embodiment, provided is an improved programmable array for an application specific integrated circuit of the type in which an input signal is manipulated by the array to execute specified matrix functions, the improvement comprising a plurality of multi-stage, parallel signal processing modules, wherein each stage of each s multi-stage, parallel signal processing module includes: at least one data manipulation module structured and arranged to manipulate the input signal; a crosspoint switch positioned to facilitate the receipt of the input signal, parallel distribution of the input signal to the at least one data manipulation module, and transmittance of the manipulated signal to a signal output formatter; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan view of a processing unit having a plurality of integrated programmable elements; 
         FIG. 2  is a plan view a programmable element; 
         FIG. 3  is a plan view of multi-stage signal processing unit; 
         FIG. 4  is a block diagram of a crosspoint switch; and 
         FIG. 5  is a matrix of crosspoint switch sources and destinations. 
     
    
    
     DETAILED DESCRIPTION 
     Before proceeding with the detailed description, it should be noted that the present teaching is by way of example, not by limitation. The concepts herein are not limited to use or application with one specific type of central processing architecture. Thus, although the instrumentalities described herein are for the convenience of explanation, shown and described with respect to exemplary embodiments, the principles herein may be equally applied in other types of central processing architectures. 
       FIG. 1  is a plan view of a reconfigurable processing unit or programmable array  100  for an application specific integrated circuit (“ASIC”)  102 . In at least one embodiment, the processing unit is a central processing unit (“CPU”). As shown, ASIC  102  interfaces with, and is an integral element of, a host device or host  104 , which may also be a subsystem or system. A host input interconnect  106  links the ASIC to the host device  104  for the purpose of transmitting data and/or control signals to ASIC  102 . In one embodiment, the host input interconnect is a switch which may be a crosspoint switch. 
     Processing unit  100  includes a plurality of programmable elements, of which elements  108 ,  110  and  112  are exemplary. In one embodiment, elements  108 - 112  primarily perform matrix operations or matrix-intensive mathematical algorithms. As such, these elements may be referred to as programmable matrix elements or “PMEs”. The input and output protocol for each PME  108 - 112  is a standard input/output (“I/O”) format for digital signal processing. In particular, as discussed in greater detail below, the input may be either a “0” or a “1”, as per a standard digital signal scheme. Further, one standard output is transmitted from each PME  108 - 112  to a host output interconnect  114 , which may also be a crosspoint switch. 
     Each PME, e.g. PME  108 , may include a plurality of multi-stage processing modules. In at least one embodiment, PME  108  includes eight two-stage processing modules or PME dual-stage subchips (“PMEDs”), of which PMEDs  116 ,  118 ,  120 ,  122 ,  124 ,  126 ,  128  and  130  are exemplary. Further, each PME  108 - 112  includes a multiplicity of bundled functions to include Reset/Enable, Host, Output Formatter, and SP 0 /SP 1  multiplexing functions housed within a single module, which may be designated “PME Other” ( 210   FIG. 2 ). 
     PMEs  108 - 112  are reconfigurable, which is to say each may be programmed or reprogrammed to perform one or more processing functions related to matrix operations. Each PME  108 - 112  may be programmed to function independently or in conjunction with other PMEs. Also, functions within each PME  108 - 112  may be performed in parallel, without many of the limitations of serial data processing. In particular, serial processing or functioning may be used exclusively to monitor and control processes, as opposed to impacting data transfer and flow. As such, processing unit or array  100  is a flexible processor capable of being selectively operated as one large parallel processor, multiple parallel processors, or as a number of independent processors. 
     PMEs  108 - 112  are clocked using a System Clock (not shown). In one embodiment, clock rates up 62.5 MHz shall be accepted, however, it can be appreciated that various clock rates may also be used without departing from the scope of this disclosure. Also, each PME  108 - 112  can be reset and/or enabled/disabled using a PME level reset or enable control bit respectively. Operationally, the response to the assertion of a “disabled” state for a given PME  108 - 112  shall be functionally identical to the assertion of the PME “reset” state, with the exception that no internal host modules shall be affected. 
     Referring now to  FIG. 2 , a somewhat more detailed examination of a programmable element, i.e. PME  200 , is disclosed. Although a general overview of a PME  200  and two-stage PMED  202  is provided in  FIG. 2 , as part of the overall architecture of element  200 , a more detailed description of a two-stage PMED is discussed with regard to  FIG. 3 . The circuitry interconnecting the various components of PME  200  has been simplified to facilitate discussion and explanation. It can be appreciated by those skilled in the art that standard integrated circuit inputs and outputs, as well as circuit interconnects, synchronization and clock signals, etc, are integral to PME  200 , and are therefore incorporated into the present disclosure. Only those standard features necessary to understand the disclosed invention are included in the associated figures. 
     As shown and discussed above, PME  200  includes a plurality of multi-stage, parallel signal processing modules or PMEDs, of which PMEDs  202 ,  204 ,  206  and  208  are exemplary. In a PME having eight such modules, PMEDs  202 - 208  represent one-half of the PMED set of eight. Each stage of each PMED, as well as the PME Other module  210 , includes a separate Host Interface, such as host interface  212  (PMED  202 ) and interface  214  (PME Other  210  e). The PMED host interface modules, e.g. module  210 , provide control registers, memory access, and interrupt management functions for each stage. 
     Similar to each PME, e.g. PME  200 , each PMED  202 - 208  includes a PMED reset and PMED enable/disable function. Through the reset/enable registers, for example register  216 , each PMED may be independently reset and enabled/disabled. PMED reset/enable register  216  is interconnected to a PME reset/enable register, e.g. register  218 . Additionally, each stage of each PMED may be independently reset or enabled/disabled through a stage reset/enable register (not shown). 
     In at least one embodiment, each PMED  202 - 208  is a two-stage module, for example Stage  0   220  and Stage  1   222  in PMED  202 . Numbering of stages may be by convention well known in the art. For example, the remaining stages of  FIG. 2  may be identified as stages  2  and  3  (PMED  204 ), stages  8  and  9  (PMED  206 ) and stages  14  and  15  (PMED  208 ). Of note, each PMED  202 - 208  has an “even” and an “odd” numbered stage for each stage “pair”, which is used to facilitate the transfer and processing of input signals. Given that  FIG. 2  represents one-half of an eight-stage PME, other stage pairs not represented may be numbered, for example, ( 4 , 5 ), ( 6 , 7 ), ( 10 , 11 ), ( 12 , 13 ). 
     Each stage of a PMED, e.g. Stage  0   220  and Stage  1   222  of module  202 , is interconnected to a stage signal input formatter, such as input formatter  224 . Each stage input formatter is structured and arranged to demulitplex a standard input signal  226  into two discrete signals streams or input signals, e.g. signals  228  and  230 . Signals  228  and  230  are communicated within Stage  0   220  to an interpolation module  232  and a crosspoint switch  234  respectively. 
     Interconnected to crosspoint switch  234  are a series of signal and/or data manipulation modules  236  for performing certain designated matrix/mathematical functions and/or data control/transfer on data integral to and derived from input signal  226 . As described in greater detail below, functions include addition, subtraction, division, etc. of real and complex numbers. Further, each stage includes Type “0” generic RAM modules (e.g. modules  238  and  240 ), and a Type “1” generic RAM modules, e.g. module  242 . Also, PME  200  includes a signal or PME Output formatter  244  interconnected to each stage (e.g. Stage  0   220 ), and a PME Programmable Control Module (“PGCM”)  246 . 
     Considering now  FIG. 3 , a more detailed examination of a PMED  300  is presented. As shown, each PMED  300  includes two stages, for example a Stage  0   302  and a Stage  1   304 , as well as a host interface  305 . In a PME having eight two-stage PMEDS, each stage  1 - 15  is capable of performing substantially the same functions. One stage, typically identified by convention as Stage  0   302 , includes additional functional capability. More specifically, in addition to the input formatting, interpolation, addition, subtraction, multiplication, accumulation, storage and scaling of both complex and real numbers provided by stages  1  through  15 , Stage  0   302  includes a complex/real number division function. 
     A stage reset/enable register  306  (Stage  0   302 ) may receive a control signal or command  307  from the PMEDs reset/enable manager (e.g. register  216   FIG. 2 ) to reset, enable or disable Stage  0 . Reset/enable register  306  has the capability to reset, enable or disable Stage  0   302  independent of any reset, enable or disable function performed on any other stage, e.g. Stage  1   304 . After reset, a stage is left in a “disabled” state and all related programming registers assume their default values. The same may be said for the assertion of a “disable” command from register  306 , with the exception that the corresponding PMEDs Host Interface Module  305  is not affected by the stage “disable” command. When a stage such as Stage  0   302  is enabled, the corresponding PMEDs host interface provides for a readback of the stage enable status. 
     Within each stage, an input formatter  308  and stage interpolation module  310  receive a single input signal  312  and output two (18,18) signals  314  and  316  respectively to a stage crosspoint switch module (“PCPS”)  318 . Stage input formatter  308  has the capability to route a “data valid” signal from each channel in a standard multiplexed input signal  312  to any of the signal streams being created by within a PME (e.g. PME  200   FIG. 2 ). Upon receipt of a “data valid” signal derived from the multiplexed input signal  312 , the stage shall reset/enable stage input formatter  308  via enable/reset register  306 . 
     As discussed briefly above, each PME/PMED/Stage may receive both input signal “0” and an input signal “1”. Stage interpolation module  310  provides input interpolation for each stage input signal “1”. The output is an “interpolated” signal “0”. In particular, interpolation is accomplished by inserting an indicated number of “zeroes” after each input signal “1” sample received. The number of “zeroes” inserted is controlled by an interpolation field of an interpolation control register within stage interpolation module  310 . If an indicated interpolation produces a sample rate exceeding the System Clock rate, an “interpolator error” interrupt signal is generated. 
     The outputs  314 ,  316  of the Stage  0   302  input formatter  308  and stage interpolation module  310  are directed toward the stage crosspoint switch module  318 . As an integral part of the present disclosure, PCPS  318  interconnects the signal processing resources within Stage  0   302 . As shown in  FIG. 3 , the specific resources include: an arithmetic unit module (“AU”)  320 ; a divider module  322 ; a multiply/accumulate module (“MAC”)  324 ; and two register array modules (“RAY”), i.e. RAY “0”  326  and Ray “1”  328 . 
     In at least one embodiment, AU module  320  accepts two (24, 24) standard inputs (typically represented as Input  0  and Input  1 ) from PCPS  318 , and provides one (24,24) standard output to PCPS  318 . A “sample hold” function  330  within AU module  320  receives a single control bit from a PCPS control bus  332  to determine its mode of operation. In a “normal” hold mode, an AU module  320  operation may only be performed when valid values are present at both inputs (i.e. Input  0  and Input  1 ). Values received at each input may be held until they are used in an AU operation and then released. Sample hold function  330  is capable of accepting values at the System Clock rate. If a new value is received on the same input before an AU operation occurs, the old value is overwritten. An “AU Hold Error” interrupt is generated for this condition. In a “latched” hold mode, sample hold function  330  may latch the next valid value received, and hold the value until the mode of AU module  320  is changed. AU operations occur any time both inputs to the module are valid. 
     AU module  320  may be capable of performing complex addition and subtraction operations at System Clock rates. For addition, an Output=Input  0 +Input  1 . Alternatively, for subtraction, an Output=Input  0 −Input  1 . AU module  320  receives a single control bit to determine whether the module adds or subtracts. AU module  320  is capable of switching modes at System Clock rate. If a numeric overflow occurs, an “AU Overflow Error” interrupt may be generated. 
     As noted above, only one stage (e.g. Stage  0 ) includes a complex/real number Divider module  322 . Divider module  322  accepts two (24, 24) standard inputs (typically represented as Input  0  and Input  1 ) from PCPS  318 , and provides one (24,24) standard output to PCPS  318 . A “sample hold” function  334  within Divider module  322  receives a single control bit from a PCPS control bus  332  to determine its mode of operation. In a “normal” hold mode, a Divider module  322  operation may only be performed when valid values are present at both inputs (i.e. Input  0  and Input  1 ). Values received at each input may be held until they are used in a Divider operation and then released. Sample hold function  334  is capable of accepting values at the System Clock rate. If a new value is received on the same input before a Divider operation occurs, the old value is overwritten. A “Divider Hold Error” interrupt is generated for this condition. In a “latched” hold mode, sample hold function  334  may latch the next valid value received, and hold the value until the mode of Divider module  322  is changed. Divider operations occur any time both inputs to the module are valid. Divider module  322  may be capable of performing complex/real division operations at System Clock rates, and may be capable of switching modes at System Clock rate as well. 
     In addition to an AU module  320  and Divider module  322 , each stage may include a MAC module  324 . MAC module  324  typically includes multiplier, accumulator and output scaler modules (not shown). MAC module  324  accepts two (24,24) standard inputs from PCPS  318  and provides one standard (24,24) output to PCPS  318 . MAC module  324  is capable of both real and complex number multiplication. A “sample hold” function  336  within MAC module  324  receives a single control bit from a PCPS control bus  332  to determine its mode of operation. In a “normal” hold mode, a MAC module  324  operation may only be performed when valid values are present at both inputs (i.e. Input  0  and Input  1 ). Values received at each input may be held until they are used in an AU operation and then released. Sample hold function  336  is capable of accepting values at the System Clock rate. If a new value is received on the same input before a MAC operation occurs, the old value is overwritten. A “MAC Hold Error” interrupt is generated for this condition. In a “latched” hold mode, sample hold function  336  may latch the next valid value received, and hold the value until the mode of MAC module  324  is changed. MAC operations occur any time both inputs to the module are valid. 
     The multiplier module within MAC module  324  may have four modes of operation: Single Real; Dual Real; Complex; and Complex Conjugate. The multiplier module within MAC module  324  receives two “Mode Control” bits to determine its mode of operation. As with other elements of the present disclosure, the multiplier module is capable of switching mode at System Clock rates. Of note, if a multiplication operation is “in process”, the operation will complete prior to a mode change. 
     The accumulator module (not shown) within MAC module  324  is capable of performing complex addition at the System Clock rate. The accumulator function can automatically add together a programmed number of complex MAC Adder inputs, output the sum, and then clear the accumulation sum. Three modes of accumulation include: single accumulation; multiple accumulation; and adder bypass. Single accumulation mode zeros the accumulation sum, adds together a predetermined number of MAC  324  multiplication products, and then outputs the accumulation sum. The multiple accumulation mode maintains four independent single accumulations by demulitplexing four adjacent input values. Further, adder bypass mode forces a zero on an adder input used for an accumulation feedback path, thereby causing the MAC Adder function to be bypassed. 
     Programmable scaling of MAC module  324  output is achieved via a MAC scaler output module (not shown). Scaling of intermediate results larger than 24 bits is accomplished via a barrel shift function. The amount of scaling is controlled via the host interface, and all outputs are rounded to 24-bits. The output scaler module is capable of operating at the System Clock rate. 
     Still referring to  FIG. 3 , each PMEDs stage may provide two Register Array (“RAY”) modules designated modules “0” and “1”, e.g. modules  326  and  328  respectively. Each RAY module  326 ,  328  accepts one standard (24,24) input from PCPS  318  and provides one (24,24) standard output to PCPS  318 . Further, each RAY module  326 ,  328  contains sixteen (24,24) registers. Three separate modes of operation are possible, to include: “linked datapipe source”; “ping-pong”, and “incremental feedback” modes. 
     In “linked datapipe source” mode, a given RAY accepts a burst of input data at up to the System Clock rate, and then outputs the data stream at the same or a slower rate. Each successive input shall be written into one of the registers at the rate received. An output read sequence may be initiated each time the initial register is written to. If data in a register is overwritten before it is output, or if the read sequence cannot complete in a timely manner due to a lack of data input, the a “RAY Error Interrupt” is generated. 
     When placed in the “ping-pong mode” of operation, the 16 RAY registers of a given RAY are divided into two 8-register banks, known by convention as “A” and “B” banks. One register bank is available for writing by the Host and one is available for reading to the RAY output. Typically, relative addressing of registers as “0” to “7” in each bank is maintained. Read sequences in process when the “ping-pong” control bit is changed are completed before the register bank is switched. Further, switching register banks may cause both read and writer pointers to be reset. 
     In the “incremental feedback mode” of operation, a RAY accepts a series of inputs. Each successive input is written to one of the RAY registers. A “cumulative” read buffer is maintained such that every input since the beginning of a write sequence is output from the RAY, in the order received, in response to each write. 
     As shown in  FIG. 3 , each PMED  300  may include two Type  0  Generic RAM modules (“GRM 0 ”), e.g. module  338  for Stage  0   302 . The PME Other module ( 210   FIG. 2 ) interconnects the sixteen GRM 0  modules present in a given PME  200  to provide a Scratchpad RAM  0  (SP 0 ) function. In a given PMED  300 , the SP 0  function provides a standard (24,24) interface to/from each of sixteen PCPSs (e.g. PCPS  318 ). Via SP 0  write ports (not shown), any PCPS  318  can supply data to any GRM 0   338 , and alternatively, any GRM 0   338  can supply data to any PCPS  318  via a SP 0  read port (not shown). In at least one embodiment, each GRM 0  module, e.g. module  338 , includes eight operational modes, i.e. Host; RCB; Normal Datapipe Source; Signal Triggered Datapipe Source; Datapipe Destination; Extended Precision Datapipe Destination; Type  1  FIR Filter ISM; and Type  2  FIR Filter ISM. 
     Still referring to  FIG. 3 , each PMED  300  may include a Type  1  Generic RAM module (“GRM 1 ”)  340 . The PME Other module ( 210   FIG. 2 ) interconnects the eight GRM 1  modules present in a given PME  200  to provide a Scratchpad RAM  1  (SP 1 ) function. In a given PMED  300 , the SP 1  function provides a standard (24,24) interface to/from each of sixteen PCPSs (e.g. PCPS  318 ). Via SP 1  write ports (not shown), any PCPS  318  can supply data to any GRM 1   340 , and alternatively, any GRM 1   340  can supply data to any PCPS  318  via a SP 1  read port (not shown). In at least one embodiment, each GRM 1  module, e.g. module  340 , includes eight operational modes, i.e. Host; RCB; Normal Datapipe Source; Signal Triggered Datapipe Source; Datapipe Destination; Extended Precision Datapipe Destination; Type  1  FIR Filter ISM; and Type  2  FIR Filter Coefficient Address Generator. To allow multi-stage operation, each GRM 1   340  is able to transfer data to/from any SP 1  port. Also, each GRM 1   340  is provided to both stages in a given PMED  300 . 
     As noted above, each PMED  300  includes a Programmable PME Control Module (“PGCM”)  342  (Stage  0   302 ). The function of each PME stage is programmed and controlled by the Host (not shown) via a RAM-based finite state machine which is the PGCM  342 . Each PGCM  342  has the ability to execute a user-supplied program at the System Clock rate. Further, each PGCM  342  provides a program storage capacity of 512 instructions and a signal routing function. The PGCM  342  program supports a given signal processing function by controlling the arithmetic, storage and signal routing assets of it&#39;s the associated stage. Each PGCM  342  can operate independently to control single-stage functions, or it may operate in conjunction with other stages to make multi-stage functions. 
     Cross-referencing for a moment  FIG. 3  with  FIG. 4 , typical connections for PCPS  318  are presented. As can be appreciated by referring to  FIGS. 3 and 4 , PCPS  318  is not multiplexed, which is to say signal streams are passed directly between stage resources. Crosspoint switch  318  may be programmed to interconnect arithmetic elements (e.g. AU module  320 , MAC module  324 ) in “datapipe” fashion. A PGCM  342  “shepherds” the data flow process without directly interfering with data transfers affected by crosspoint switch  318 . 
     As shown in  FIG. 4 , a specified number of parallel data pathways, or “datapipes” are available for the transfer of data, of which pathways  400  and  402  are exemplary. Representative input signals  406  are routed via datapipes (e.g.  400  and  402 ) to any one of several signal output locations  408 . In at least one embodiment, signal output is facilitated through an signal output formatter (e.g. output formatter  244   FIG. 2 ). During operation, each destination or data pathway in PCPS  318  shall have its source selected by 4-bits from the PCPS control bus  410 , which in turn is provided by the associated PGCM, e.g. PGCM  342  in  FIG. 3 . If an indicated connection is not valid (block  412  in  FIG. 4 ), an Invalid PCPS Connection Error interrupt will be generated  414 . In at least one embodiment, PCPS  318  is capable of switching connections at the System Clock (not shown) rate. 
     Typically, pathways  400 ,  402  in PCPS  318  carry a 24-bit in-phase word and a 24-bit quadrature word (24,24). Each pathway also contains a data flow control bit DV (“data valid”). PCPS  318  interconnections where the source and destination have the same bit width are mapped bit-to-bit. Alternatively, PCPS  318  interconnections where the source and destination have a different bit width are mapped as follows: (a) 18-bit sources are sign-extended into the LS bits of internal 24-bit PCPS  318  destinations thereby allowing for maximum growth for subsequent manipulations of 18-bit numbers; (b) 18-bit sources connected to a 24-bit output formatter destination are optionally mapped MS-bit to MS-bit, with any extra bits zero-filled, such that a given input value will produce the same output value if a direct connect is used; (c) certain modules, such as the MAC  324  and Divider  322  modules, having internal bit resolution greater than 24-bits, may have output scaler functions which allow the “best” 24-bits to be selected for output in a given functional application; and, similarly, (d) AU module  320  has an output scaler function which allows an 18-bit output to result from either the MS or LS part of a 24-bit word. For all other 24-bit sources it may be assumed that the “best” 18-bits are the MS bits of the 24. 
     Interconnection options within PCPS  318  may be controlled and/or restricted to minimize hardware requirements. For example, stage “input” and “interpolation” sources may be available to all destinations (modules, etc.) within a given stage. Similarly, stage “outputs” may have all sources within the same stage available to it. Referring for a moment to  FIG. 5 , a sample stage-by-stage summary of valid PCPS sources and destinations for at least one embodiment of the present disclosure is presented. In  FIG. 5 , the numbers (i.e. “0” and “1”) in the stage columns labeled “0” and “1”  500  are used in place of the “x” variable for each source and destination. For example, “Stage x Input Signal” for Stage “0” (indicated by arrow  502 ) would be “Stage “0” Input Signal”. Alternatively, “Inter-pair Input from Stage x” for Stage “0” (indicated by arrow  504 ) would be “Inter-pair Input Stage  1 ”. 
     As shown in  FIG. 5 , there may be several asymmetries in the resource allocations for various stages. For example, in at least one embodiment Stage  0  is the only stage to include a stage divider module, therefore there can be no Stage  1  Divider Output source, nor can there be a Stage  1  Divider Input  0  or Input  1 . Also, inter-pair connections may only be cross-linked between the stages of each pair of stages. Further, although each stage in a pair may drive an SP 1  Write Port (as shown in  FIG. 5 ), only one stage in each pair may actually write to the PMED RAM at any one time. By contrast, both stages of a pair (e.g. Stage  0  and Stage  1 ) may receive the same SP 1  Read Port simultaneously. 
     Changes may be made in the above methods, devices and structures without departing from the scope hereof. It should thus be noted that the matter contained in the above description and/or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present method, device and structure, which, as a matter of language, might be said to fall therebetween.