Patent Publication Number: US-2023148246-A1

Title: Electronic device with connector supporting multiple connection standards and signal switching method and power supply method thereof

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present application relates to a signal switching technique for a connector, and more particularly, to an electronic device with a connector supporting multiple connection standards, and a switching method and a power supply method thereof. 
     Description of the Prior Art 
     Conventionally, corresponding connectors need to be individually provided for multiple connection standards in order for an electronic device to support these multiple connection standards. However, as the number of connectors necessarily provided gets larger, both the volume and the cost of the electronic device are increased. 
     Although an electronic device may be equipped with a DisplayPort connector with customized pins to connect to a special device, such DisplayPort connector occupies a large area in an input/output panel, and the standard High-Definition Multimedia Interface Display Data Channel (HDMI DDC) bus is given up due to pin limitations of a DisplayPort connector, such that the electronic device cannot be connected to a common device using a standard DisplayPort connector or a standard HDMI connector. As a result, applications of a system terminal user are made inflexible. 
     SUMMARY OF THE INVENTION 
     In one embodiment, the present invention provides an electronic device with a connector supporting multiple connection standards. The electronic device includes the connector, a first multiplexer circuit, a processor and a controller. The connector includes a detection pin and at least one signal pin. The first multiplexer circuit is coupled to the at least one signal pin. The processor is coupled to the first multiplexer circuit. The controller monitors the detection pin. The first multiplexer circuit electrically connects the at least one signal pin to the controller. Upon detecting a hot-plug signal occurring at the detection pin, the controller issues a confirmation command via the first multiplexer circuit and the at least one signal pin to request a reply of a device signal. Upon receiving the device signal, the controller controls the first multiplexer circuit according to the device signal to electrically connect the at least one signal pin to the processor or the controller. 
     In one embodiment, the present invention provides a signal switching method for a connector supporting multiple connection standards. The signal switching method includes: electrically connecting at least one signal pin of a connector to a controller; monitoring a detection pin of the connector; upon detecting a hot-plug signal occurring at the detection pin, the controller issuing a confirmation command via the first multiplexer circuit and the at least one signal pin to request a reply of a device signal; and upon receiving the device signal, electrically connecting the at least one signal pin to a first interface of a processor or the controller according to the device signal. 
     In one embodiment, the present invention provides a power supply method for an electronic device with a connector supporting multiple connection standards. The power supply method includes: providing a first voltage to a power pin of the connector; monitoring a detection pin of the connector; upon detecting a hot-plug signal occurring at the detection pin, issuing a confirmation command via at least one signal pin to request a reply of a device signal; when the device signal is not received, continually providing the first voltage to the power pin; and upon receiving the device signal, switching to provide a second voltage to the power pin, wherein the second voltage is higher than the first voltage. 
     In conclusion, in the electronic device with a connector supporting multiple connection standards and the signal switching method thereof according to the embodiments of the present invention, the confirmation command is issued via the at least one signal pin of the connector to request a reply of a device signal, and the transmission path of the at least one signal pin of the connector is switched according to whether the device signal is received, so that a single connector is enabled to support multiple connection standards. Thus, the electronic device is able to perform transmission with a common device or a special device via this single connector, and to selectively apply one from the multiple connection standards. Moreover, in the electronic device with a connector supporting multiple connection standards and the signal switching method and the power supply method thereof according to the embodiments of the present invention, the confirmation command is issued via the at least one signal pin of the connector to request a reply of a device signal, and the first voltage or the second voltage is selectively provided to the power pin according to whether the device signal is received, so that the electronic device is able to connect to a common device or a special device that uses different voltages via this single connector. 
     The features and advantages of the present invention described in detail in the embodiments below are sufficient for a person skilled in the art to understand and accordingly implement the technical contents of the present invention. Moreover, a person skilled in the art would be able to easily understand the objects and advantages of the present invention on the basis of the disclosure, claims and drawings of the present application. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block schematic diagram of a common device connected to an electronic device according to an embodiment of the present invention; 
         FIG.  2    is a flowchart of a signal switching method according to an embodiment; 
         FIG.  3    is a block schematic diagram of a special device connected to an electronic device according to an embodiment of the present invention; 
         FIG.  4    is a flowchart of step S 04  according to an embodiment; 
         FIG.  5    is a flowchart of a signal switching method according to an embodiment; 
         FIG.  6    is a block schematic diagram of a special device connected to an electronic device according to an embodiment of the present invention; 
         FIG.  7    is a block schematic diagram of a common device connected to an electronic device according to an embodiment of the present invention; 
         FIG.  8    is a flowchart of step S 01  according to an embodiment; 
         FIG.  9    is a block schematic diagram of a power supply circuit according to an embodiment; 
         FIG.  10    is a block schematic diagram of a power supply circuit according to an embodiment; 
         FIG.  11    is a flowchart of a signal switching method according to an embodiment; 
         FIG.  12    is a block schematic diagram of an electronic device according to an embodiment; and 
         FIG.  13    is a flowchart of a power supply method according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     To better understand the above and other objects, features and advantages of the embodiments of the present invention, detailed description is provided with the accompanying drawings below. 
       FIG.  1    shows a block schematic diagram of a common device connected to an electronic device according to an embodiment of the present invention. Referring to  FIG.  1   , an electronic device  100  with a connector supporting multiple connection standards includes a connector  101 , a first multiplexer circuit  102 , a processor  103  and a controller  104 . The first multiplexer circuit  102  is coupled to the connector  101 , the processor  103  and the controller  104 . 
     The connector  101  is disposed at a housing of the electronic device  100 , and is applicable to being connected to an external device having a corresponding connector so that the electronic device  100  is enabled to perform transmission with the external device. In some embodiments, the external device may be another electronic device having a corresponding connector, so as to be connected to or separated from the connector  101  of the electronic device  100  by means of plugging; however, the present invention is not limited to the above. In some other embodiments, the external device may be an electronic device  300 . The electronic device  300  is connected to one end of a transmission line  200 , and is connected to or separated from the electronic device  100  by plugging the other end of the transmission line  200  with the connector  101 . In the description below, the external device is exemplified by the electronic device  300  that is connected to or separated from the electronic device  100  through the transmission line  200  for illustrations. It should be noted that this example is not to be construed as a limitation to the present invention. 
     The connector  101  includes a detection pin P 1  and at least one signal pin P 2 . The first multiplexer circuit  102  is coupled among the signal pin P 2  of the connector  101 , the processor  103  and the controller  104 , and the first multiplexer circuit  102  selectively electrically connects the signal pin P 2  to the processor  103  or the controller  104 . The controller  104  is coupled to the detection pin P 1  of the connector  101 , and the controller  104  is capable of detecting the detection pin P 1  so as to determine whether the electronic device  300  is connected to the connector  101  through the transmission line  200 . 
     In some implementation forms, the electronic device  100  may be a digital video recorder or a computer, and the electronic device  300  may be various types of screens, for example, a touch screen or a display screen. The connector  101  may be a standard High-Definition Multimedia Interface (HDMI) Type A connection port, the detection pin P 1  may be pin # 19  for hot-plugging detection in a standard HDMI connection port, and the signal pin P 2  may be pin # 15  and pin # 16  for Display Data Channel (DDC) in a standard HDMI connection port. The processor  103  may be implemented by a system on chip (SoC), a central processing unit (CPU), a microprocessor, an application processor (AP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof. However, the present invention is not limited to the above, and the processor  103  may be a core circuit suitable for executing various computations and operations in a system of the electronic device  100 . Moreover, the controller  104  may be implemented by a micro controller unit (MCU), a keyboard controller (KBC) or an embedded controller (EC). However, the present invention is not limited thereto, and the controller  104  may be any control circuit suitable for performing a specific task. 
     The electronic device  100  of any embodiment of the present invention is capable of performing the signal switching method according to any embodiment.  FIG.  2    shows a flowchart of a signal switching method according to an embodiment. Referring to  FIG.  1    and  FIG.  2   , in one embodiment of the signal switching method, the first multiplexer circuit  102  of the electronic device  100  can electrically connect the at least one signal pin P 2  of the connector  101  according to a selection signal SEL 1  generated by the controller  104  (step S 01 ), and the controller  104  of the electronic device  100  monitors the detection pin P 1  of the connector  101  (step S 02 ). 
     In step S 01  according to some embodiments, the selection signal SEL 1  generated by the controller  104  in a default state has a first set value, and the first multiplexer circuit  102  can normally electrically connect the signal pin P 2  to the controller  104  according to the first set value of the selection signal SEL 1 . In some embodiments, the controller  104  includes a first interface MCU_I 1 , and the first multiplexer circuit  102  can normally electrically connect the signal pin P 2  to the first interface MCU_I 1  of the controller  104 . In some implementation forms, the first interface MCU_I 1  of the controller  104  may be a transmission interface adopting an Inter-Integrated Circuit (I2C) connection standard. 
     Upon detecting by the controller  104  a hot-plug signal HPD occurring at the detection pin P 1  of the connector  101  in step S 02 , it means that the electronic device  300  is connected to the connector  101  through the transmission line  200 . At this point in time, the controller  104  may issue a confirmation command C 1  via the first interface MCU_I 1  thereof, and transmit the confirmation command C 1  via the first multiplexer circuit  102  and the signal pin P 2 , so as to request the electronic device  300  to return a device signal DEV as a reply (step S 03 ). In some implementation forms, the confirmation command C 1  may be an addressing command of the I2C connection standard. 
       FIG.  3    shows a block schematic diagram of a special device connected to an electronic device according to an embodiment of the present invention. Referring to  FIG.  2    and  FIG.  3   , in some embodiments, the electronic device  300  may be a special device having a controller  310 . Thus, after receiving the conformation command C 1  via the signal pin P 2  of the connector  101  of the electronic device  100 , the electronic device  300  may generate a device signal DEV by the controller  310  and return the device signal DEV as a reply to the electronic device  100 . 
     Herein, the controller  310  generates the device signal DEV having corresponding content according to the connection standard adopted for the transmission of the electronic device  300 . In some implementation forms, the electronic device  300  may use the I2C connection standard, a Universal Asynchronous Receiver/Transmitter (UART) connection standard or Universal Serial Bus (USB) 2.0 connection standard for transmission. 
     When the controller  104  of the electronic device  100  can receive the device signal DEV sent from the other electronic device  300  via the signal pin P 2  and the first multiplexer circuit  102  at the first interface MCU_I 1 , it means that the electronic device  300  is a special device. Thus, the controller  104  can learn from the content of the device signal DEV the connection standard that the electronic device  300  uses for transmission, and accordingly selectively electrically connects the signal pin P 2  of the connector  101  to the processor  103  or the controller  104  (step S 04 ). 
       FIG.  4    shows a flowchart of step S 04  according to an embodiment. Referring to  FIG.  2    to  FIG.  4   , in step S 04  according to an embodiment, the controller  104  can perform identification on the device signal DEV (step S 041 ). When the controller  104  identifies that the device signal DEV is first content the same as the connection standard adopted by the first interface MCU_I 1  of the controller  104 , the controller  104  can keep generating the selection signal SEL 1  having the first set value to the first multiplexer circuit  102 , so that the first multiplexer circuit  102  keeps electrically connecting the signal pin P 2  of the connector  101  to the first interface MCU_I 1  of the controller  104  (step S 042 ). 
     In step S 041  according to an embodiment, when the controller  104  identifies that the device signal DEV is second content, the controller  104  may generate a selection signal SEL 1  having a second set value, so as to control the first multiplexer circuit  102  to switch the signal pin P 2  of the connector  101  to be electrically connected to the processor  103  (step S 043 ). 
     In some embodiments, the processor  103  includes a first interface CPU_I 1 , and the first multiplexer circuit  102  electrically connects the signal pin P 2  to the first interface CPU_I 1  of the processor  103  in step S 043 . In some implementation forms, the first interface CPU_I 1  of the processor  103  may be implemented by a transmission interface of the USB 2.0 connection standard, and the second content of the device signal DEV is the USB 2.0 connection standard. 
     In some embodiments, the controller  104  may further include a second interface MCU_I 2 , and the connection standard adopted by the second interface MCU_I 2  is different from the connection standard adopted by the first interface MCU_I 1 . In step S 041  according to an embodiment, when the controller  104  identifies that the device signal DEV is third content, the controller  104  may generate a selection signal SEL 1  having a third set value, so as to control the first multiplexer circuit  102  to switch the signal pin P 2  of the connector  101  to be electrically connected to the second interface MCU_I 2  of the controller  104  (step S 044 ). In some implementation forms, the second interface MCU_I 2  of the controller  104  may be implemented by a transmission interface of a UART connection standard, and the third content of the device signal DEV is the UART connection standard. 
     In addition, the processor  103  may also include a transmission interface CPU_I 3  adopting a UART connection standard; in step S 044 , the controller  104  may also control the first multiplexer circuit  102  to electrically connect the signal pin P 2  of the connector  101  to the transmission interface CPU_I 3  adopting the UART connection standard in the processor  103 . 
     In some embodiments, the second interface MCU_I 2  of the controller  104  and the transmission interface CPU_I 3  of the processor  103  may coexist. In some other embodiments, only one of the second interface MCU_I 2  of the controller  104  and the transmission interface CPU_I 3  of the processor  103  may exist. 
     In some embodiments, the electronic device  100  may further include a second multiplexer circuit  105  and an Extended Display Identification Data (EDID) read-only memory (ROM)  106 , and the second multiplexer circuit  105  is coupled to the first multiplexer circuit  102 , the processor  103 , the controller  104  and the EDID ROM  106 . The second multiplexer circuit  105  is for selectively electrically connecting the first multiplexer circuit  102  or the EDID ROM  106  to the processor  103  according to a selection signal SEL 2  of the controller  104 . 
     In some embodiments, when the controller  104  can receive the device signal DEV via the signal pin P 2  and the first multiplexer circuit  102  at the first interface MCU_I 1 , the controller  104  may further generate a selection signal SEL 2  having a first selection value to the second multiplexer circuit  105 , so that the second multiplexer circuit  105  electrically connects the EDID ROM  106  to the processor  103  (step S 05 ). 
     In some embodiments, the processor  103  further includes a second interface CPU_I 2 . In step S 05 , the second multiplexer circuit  105  electrically connects the EDID ROM  106  to the second interface CPU_I 2  of the processor  103 , so that the processor  103  can read Extended Display Identification Data (EDID) stored in the EDID ROM  106 . 
     Referring to  FIG.  1   , in some embodiments, the electronic device  300  may be a common device without a controller (or referred to as a standard device), and the electronic device  300  does not generate the device signal DEV according to the confirmation command C 1 . In this case, the controller  104  of the electronic device  100  does not receive the device signal DEV after issuing the confirmation command C 1  in step S 03 . 
     Referring to  FIG.  1    and  FIG.  2   , in the signal switching method according to an embodiment, after the controller  104  performs step S 03  and does not receive any device signal DEV as a reply, it means that the electronic device  300  is a common device and the pin signal P 2  of the connector  101  merely serves an original intended purpose, for example, as a display data channel. Thus, the controller  104  may generate a selection signal SEL 1  having a fourth set value to the first multiplexer circuit  102 , so as to control the first multiplexer circuit  102  to electrically connect the signal pin P 2  to the second multiplexer circuit  105 , and may generate a selection signal SEL 2  having a second selection value to the second multiplexer circuit  105 , so as to control the second multiplexer circuit  105  to electrically connect the first multiplexer circuit  102  to the second interface CPU_I 2  of the processor  103 , such that the signal pin P 2  of the connector  101  may be electrically connected to the second interface CPU_I 2  of the processor  103  through the first multiplexer circuit  102  and the second multiplexer circuit  105  (step S 06 ). As such, after step S 06 , the processor  103  of the electronic device  100  may perform transmission with the electronic device  300  through the connection path between the second interface CPU_I 2  thereof and the signal pin P 2 . In some implementation forms, the connection path between the second interface CPU_I 2  of the processor  103  and the signal pin P 2  may be serve as a display data channel. For example, the electronic device  300  may transmit EDID through the connection path to the processor  103  of the electronic device  100 . It should be noted that, in step S 06 , the second multiplexer circuit  105  disconnects the connection path from the EDID ROM  106  to the second interface CPU_I 2  of the processor  103 , and forms the connection path from the first multiplexer circuit  102  to the second interface CPU_I 2  of the processor  103  instead. 
       FIG.  5    shows a flowchart of a signal switching method according to an embodiment. Referring to  FIG.  1    to  FIG.  5   , in some embodiments, the controller  104  may wait for a predetermined period of time after issuing the confirmation command C 1 , and if the device signal DEV is not yet received before the predetermined period of time expires, the controller  104  may determine that the electronic device  300  is only a common device and performs step S 06  (that is, performing step S 03  only once), as shown in  FIG.  2   . In some other embodiments, the controller  104  may perform step S 03  for a predetermined number of times, and if the device signal DEV is not yet received after performing step S 03  for the predetermined number of times, the controller  104  then determines that the electronic device  300  is only a common device and performs step S 06 , as shown in  FIG.  5   . In some implementation forms, the predetermined number of times may be between 3 and 10; however, the present invention is not limited to these exemplary values, and the predetermined number of times may be any appropriate value. 
       FIG.  6    shows a block schematic diagram of a special device connected to an electronic device according to an embodiment of the present invention. FIG.  7  shows a block schematic diagram of a common device connected to an electronic device according to an embodiment of the present invention. Referring to  FIG.  2    and  FIG.  5    to  FIG.  7   , in some embodiments, the electronic device  100  may further include a voltage level shifter  107  which is coupled between the processor  103  and the second multiplexer circuit  105 . In other words, the second multiplexer circuit  105  may be electrically connected to the processor  103  through the voltage level shifter  107 . Thus, in step S 05  according to an embodiment, the controller  104  controls the second multiplexer circuit  105  to electrically connect the EDID ROM  106  to the voltage level shifter  107 , so that the EDID ROM  106  may be electrically connected to the second interface CPU_I 2  of the processor  103  through the voltage level shifter  107 . 
     Moreover, in step S 06  according to an embodiment, the controller  104  controls the first multiplexer circuit  102  to electrically connect the signal pin P 2  to the second multiplexer circuit  105 , and controls the second multiplexer circuit  105  to electrically connect the first multiplexer circuit  102  to the voltage level shifter  107 , so that the signal pin P 2  of the connector  101  may be electrically connected to the second interface CPU_I 2  of the processor  103  through the first multiplexer circuit  102 , the second multiplexer circuit  105  and the voltage level shifter  107 . 
     In some embodiments, the voltage level shifter  107  can be used for shifting a voltage level. For example, after step S 06  is performed, the second interface CPU_I 2  of the processor  103  is used as a display data channel through the connection path between the voltage level shifter  107  and the signal pin P 2 , and the electronic device  300  may transmit EDID via this connection path for the processor  103 . Herein, the voltage level shifter  107  may perform voltage level shifting (for example, from 5 V to 3V) on the EDID received, and then transmit the EDID that has undergone the voltage level shifting to the processor  103 . 
     In some embodiments, the connector  101  may further include a video pin P 5 , and the voltage level shifter  107  may be further coupled to the video pin P 5  and the controller  104 . Herein, the voltage level shifter  107  serves as a repeater. The voltage level shifter  107  may receive a selection signal SEL 3  from the controller  104 , and selectively generate a notification signal HDMI_HPD to the processor  103  according to the selection signal SEL 3 . When the selection signal SEL 3  has a first selection value, the voltage level shifter  107  does not output the notification signal HDMI_HPD; when the selection signal SEL 3  has a second selection value, the voltage level shifter  107  outputs the notification signal HDMI_HPD to the processor  103 . Upon receiving the notification signal HDMI_HPD, the processor  103  outputs video data D 1  to the voltage level shifter  107 , and the voltage level shifter  107  enhances the video data D 1  and outputs the enhanced video data D 1  through the video pin P 5  of the connector  101  to the electronic device  300 , for the electronic device  300  to display corresponding video and audio. However, the present invention is not limited to the examples above. In some other embodiments, the processor  103  may also directly output the video data D 1  to the video pin P 5  of the connector  101  according to an instruction of the controller  104 . 
     In some implementation forms, the video pin P 5  of the connector  101  may be pin # 1  to pin # 12  used for transmitting time-minimized differential signal (TMDS) in a standard HDMI connection port. Moreover, the voltage level shifter  107  may be implemented by an integrated circuit, so as to have both the voltage level shifting and signal enhancement function. 
     Referring to  FIG.  1   ,  FIG.  3   ,  FIG.  6    and  FIG.  7   , in some embodiments, the electronic device  100  further includes a third multiplexer circuit  108 , the connector  101  further includes a control pin P 3 , and the third multiplexer circuit  108  is coupled to the control pin P 3 , the processor  103  and the controller  104 . The third multiplexer circuit  108  is for selectively electrically connecting the control pin P 3  of the connector  101  to the processor  103  or the controller  104  according to the selection signal SEL 2 . 
     In some implementation forms, the control pin P 3  of the connector  101  may be pin # 13  for Consumer Electronics Control (CEC) in a standard HDMI connection port. 
       FIG.  8    shows a flowchart of step S 01  according to an embodiment. Referring to  FIG.  1    to  FIG.  8   , in step S 01  of the signal switching method according to an embodiment, in addition to using the first multiplexer circuit  102  to electrically connect the at least one signal pin P 2  of the connector  101  to the controller  104  according to the selection signal SEL 1  generated by the controller  104  (step S 011 ), the electronic device  100  further uses the third multiplexer circuit  108  to electrically connect the control pin P 3  of the connector  101  to the controller  104  according to the selection signal SEL 2  generated by the controller  104  (step S 012 ), and uses the second multiplexer circuit  105  to electrically connect the EDID ROM  106  to the processor  103  (or couple to the voltage level shifter  107 ) according to the selection signal SEL 2  (step S 013 ). 
     In some embodiments, the selection signal SEL 1  generated by the controller  104  in a default state has the first set value and the selection signal SEL 2  has the first selection value, such that the first multiplexer circuit  102  may normally electrically connect the signal pin P 2  to the controller  104  according to the first set value of the selection signal SEL 1 , the third multiplexer circuit  108  may normally electrically connect the control pin P 3  to the controller  104  according to the first selection value of the selection signal SEL 2 , and the second multiplexer circuit  105  may normally electrically connect the EDI D ROM  106  to the processor  103  (or couple to the voltage level shifter  107 ) according to the first selection value of the selection signal SEL 2 . 
     In some embodiments, when the electronic device  300  is a special device, the electronic device  300  may output an activation signal to the control pin P 3  of the connector  101 . In some implementation forms, the activation signal may be generated by a power key. However, the present invention is not limited to the examples above, and in some other implementation forms, the activation signal may also be generated during system activation of the electronic device  300 . In some other embodiments, when the electronic device  300  is a common device, a standard CEC signal may be transmitted on the control pin P 3  of the connector  101  between the electronic device  100  and the electronic device  300 . 
     Thus, in the signal switching method according to some embodiments, when the controller  104  receives the device signal DEV at the first interface MCU_I 1 , the controller  104  keeps generating the selection signal SEL 2  having the first selection value, so that the third multiplexer circuit  108  keeps electrically connecting the control pin P 3  of the connector  101  to the controller  104  (step S 07 ). When the controller  104  does not receive any device signal DEV as a reply after performing step S 03  or after performing step S 03  for the predetermined number of times, the controller  104  generates the selection signal SEL 2  having the second selection value, so that the third multiplexer circuit  108  switches to electrically connect the control pin P 3  of the connector  101  to the processor  103  (step S 08 ). In some implementation forms, the first selection value may be logic “0”, and the second selection value may be logic “1”; however, the present invention is not limited to the above, and the first selection value and the second selection value may be designed according to application requirements. 
     In some embodiments, the electronic device  100  further includes a power supply circuit  109 , the connector  101  further includes a power pin P 4 , and the power supply circuit  109  is coupled to the power pin P 4  and the controller  104 . The power supply circuit  109  can provide a first voltage V 1  or a second voltage V 2  to the power pin P 4  according to the control of the controller  104 . When the controller  104  outputs a first enable signal EN 1  to the power supply circuit  109 , the power supply circuit  109  outputs the first voltage V 1  to the power pin P 4 . When the controller  104  outputs a second enable signal EN 2  to the power supply circuit  109 , the power supply circuit  109  outputs the second voltage V 2  to the power pin P 4 . In addition, the second voltage V 2  is higher than the first voltage V 1 . 
     In some implementation forms, the power pin P 4  of the connector  101  may be pin # 18  for power supply in a standard HDMI connection port. The first voltage V 1  may be, for example but not limited to, 5 V, the second voltage V 2  may be, for example but not limited to, 12 V, 14 V, 19 V, 24 V or 48 V, and the values of the first voltage V 1  and the second voltage V 2  may be designed according to requirements of the electronic device  300 . 
     In step S 01  of the signal switching method according to an embodiment, in addition to step S 011 , step S 012  and step S 013 , the electronic device  100  may further use the power supply circuit  109  to output the first voltage V 1  to the power pin P 4  of the connector  101  according to the first enable signal EN 1  generated by the controller  104  (step S 014 ), as shown in  FIG.  8   . In some embodiments, the controller  104  in a default state normally outputs the first enable signal EN 1  to the power supply circuit  109 , so that the power supply circuit  109  normally provides the first voltage V 1  to the power pin P 4  according to the first enable signal EN 1 . It should be noted that, the present invention does not define that step S 011 , step S 012 , step S 013  and step S 014  have to be performed in the order shown in  FIG.  8   , and step S 011 , step S 012 , step S 013  and step S 014  may be performed simultaneously or in predetermined order. 
     Moreover, in the signal switching method according to some embodiments, as shown in  FIG.  2    or  FIG.  5   , when the controller  104  does not receive any device signal DEV as a reply after performing step S 03  or after performing step S 03  for the predetermined number of times, the controller  104  keeps outputting the first enable signal EN 1  to the power supply circuit  109 , so that the power supply circuit  109  keeps providing the first voltage V 1  to the power pin P 4  according to the first enable signal EN 1  (step S 09 ). After the controller  104  performs step S 03  and the device signal DEV can be received from the first interface MCU_I 1 , the controller  104  does not output the first enable signal EN 1  but instead output the second enable signal EN 2  to the power supply circuit  109 , so that the power supply circuit  109  stops outputting the first voltage V 1 , and switches to provide the second voltage V 2  to the power pin P 4  according to the second enable signal EN 2  (step S 10 ). 
     It should be noted that, the present invention does not define that step S 10 , step S 04 , step S 05  and step S 07  have to be performed in the order shown in the drawings, and step S 10 , step S 04 , step S 05  and step S 07  may be performed simultaneously or in predetermined order. Moreover, the present invention likewise does not define that step S 09 , step S 06  and step S 08  have to be performed in the order shown in the drawings, and step S 09 , step S 06  and step S 08  may be performed simultaneously or in predetermined order. 
       FIG.  9    shows a block schematic diagram of a power supply circuit according to an embodiment. Referring to  FIG.  1    to  FIG.  9   , in some embodiments, the power supply circuit  109  may include a power conversion circuit  109 A and a power load switch  109 B. The power conversion circuit  109 A is coupled to the controller  104  and the power pin P 4 , and the power load switch  109 B is coupled to the controller  104  and the power pin P 4 . The power conversion circuit  109 A is for converting the second voltage V 2  to the first voltage V 1 , and outputting the first voltage V 1  obtained from the conversion to the power pin P 4  upon receiving the first enable signal EN 1  generated by the controller  104 . The power load switch  109 B is for receiving the second voltage V 2 , and outputting the second voltage V 2  to the power pin P 4  upon receiving the second enable signal EN 2  generated by the controller  104 . 
     In some implementation forms, the power conversion circuit  109 A may be implemented by, for example but not limited to, a low dropout linear regulator (LDO). In addition, the power load switch  109 B may be implemented by, for example but not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a GaN FET or an insulated gate bipolar transistor (IGBT). 
       FIG.  10    shows a block schematic diagram of a power supply circuit according to an embodiment. Referring to  FIG.  1    to  FIG.  10   , in some other embodiments, the power supply circuit  109  may include a power conversion circuit  109 C and the power load switch  109 B. The power conversion circuit  109 C is coupled to the controller  104  and the power pin P 4 , and the power load switch  109 B is coupled to the controller  104  and the power pin P 4 . The power conversion circuit  109 C is for converting the first voltage V 1  to the second voltage V 2 , and outputting the second voltage V 2  obtained from the conversion to the power pin P 4  upon receiving the second enable signal EN 2  generated by the controller  104 . The power load switch  109 B is for receiving the first voltage V 1 , and outputting the first voltage V 1  to the power pin P 4  upon receiving the first enable signal EN 1  generated by the controller  104 . In some implementation forms, the power conversion circuit  109 C may be implemented by, for example but not limited to, a buck converter. 
     In some embodiments, the electronic device  100  may further include a discharging circuit  110  which is coupled to the power pin P 4 . The charging circuit  110  may discharge the power pin P 4  or stop discharging the power pin P 4  according to a discharging signal DG 1  of the controller  104 . In some implementation forms, when the discharging signal DG 1  is at a high potential, the discharging circuit  110  may discharge the power pin P 4 . When the discharging signal DG 1  is at a low potential, the discharging circuit  110  does not discharge the power pin P 4  or stops discharging the power pin P 4 . However, the present invention is not limited to the above, and the discharging circuit  110  may also be modified to discharge the power pin P 4  when the discharging signal DG 1  is at a low potential, and may not discharge the power pin P 4  or stop discharging the power pin P 4  when the discharging signal DG 1  is at a high potential. 
       FIG.  11    shows a flowchart of a signal switching method according to an embodiment. Referring to  FIG.  1    to  FIG.  11   , in the signal switching method according to an embodiment, after the hot-plug signal HPD occurring at the detection pin P 1  is detected, the controller  104  performs a hysteretic separation detection on the detection pin P 1 , for example, only determines that the hog-plug signal HPD has disappeared from the detection pin P 1  upon detecting a separation signal lasting for a period of time. Accordingly, the controller  104  is able to accurately determine whether the electronic device  300  is still connected to the connector  101 , and does not make any misjudgment as a result of instantaneous disconnection caused by non-connection problems. 
     In some embodiments, as shown in  FIG.  11   , when the power supply circuit  109  provides the second voltage V 2  to the power pin P 4  (that is, after step S 10  is performed) and it is detected that the hot-plug signal HPD has disappeared from the detection pin P 1 , the controller  104  does not output the first enable signal EN 1  or the second enable signal EN 2 , so that the power supply circuit  109  stops supplying power to the power pin P 4  and outputs the discharging signal DG 1 . As a result, the discharging circuit  110  discharges the power pin P 4 , and generates the selection signal SEL 1  having the first set value, so that the first multiplexer circuit  102  restores electrical connection of the signal pin P 2  to the controller  104 , for example, to the first interface MCU_I 1  of the controller  104  (step S 11 ). After the discharging circuit  110  discharges the power pin P 4  for a predetermined period of time, the controller  104  stops outputting the discharging signal DG 1  so that the discharging circuit  110  stops discharging the power pin P 4 , and outputs the first enable signal EN 1  so as to control the power supply circuit  109  to restore supply of the first voltage V 1  to the power pin P 4  (step S 12 ). Since the electronic device  100  of the present invention can release residual voltage from the power pin P 4  through the discharging circuit  110 , the electronic device  300  that next connects to the connector  101  does not become damaged by any residual voltage on the power pin P 4 . 
     In some implementation forms, the predetermined time in step S 12  may be several hundreds of milliseconds; however, the present invention is not limited to the above. 
     In some other embodiments, the controller  104  performs step S 11  and step S 12  upon detecting that the hot-plug signal HPD has disappeared. In other words, even if the controller  104  detects that the hot-plug signal HPD has disappeared from the detection pin P 1  while the power supply circuit  109  provides the first voltage V 1  to the power pin P 4 , the controller  104  still performs step S 11  and step S 12  to release the residual voltage from the power pin P 4 , thereby ensuring that the electronic device  300  that next connects to the connector  101  does not become damaged by any residual voltage on the power pin P 4 . 
     In some other embodiments, upon detecting that the hot-plug signal HPD has disappeared, the controller  104  may first determine if an instantaneous disconnection of the electronic device  300  exists, for example, whether the hot-plug signal HPD again appears within a predetermined period of time, e.g., 50 ms. When the controller  104  determines that the instantaneous disconnection exists, the controller  104  may keep all current settings, and does not perform step S 11  or step S 12 . Conversely, when the controller  104  determines that the instantaneous disconnection does not exist, the controller  104  performs step S 11  and step S 12  to release the residual voltage from the power pin P 4 . 
       FIG.  12    shows a block schematic diagram of an electronic device according to an embodiment. Referring to  FIG.  12   , in some embodiments, when the processor  103  of the electronic device  100  receives update data for updating the EDID ROM  106 , the processor  103  may provide the update data to the controller  104  through a bus B 1  for the controller  104  to update the EDID ROM  106 . In some implementation forms, the bus B 1  may be an I2C bus. 
     After the controller  104  receives the update data, the controller  104  may control the second multiplexer circuit  105  to electrically connect the controller  104  to the EDID ROM  106 , so that the controller  104  can update the EDID ROM  106  using the update data. 
     In some embodiments, the second multiplexer circuit  105  may include a first multiplexer  105 A and a second multiplexer  105 B. The first multiplexer  105 A is coupled to the first multiplexer circuit  102 , the EDID ROM  106 , the second multiplexer  105 B and the controller  104 , and the second multiplexer  105 B is coupled to the processor  103  (or coupled to the voltage level shifter  107 ) and the controller  104 . The first multiplexer  105 A is for selectively electrically connecting the first multiplexer circuit  102  or the EDID ROM  106  to the second multiplexer  105 B according to the selection signal SEL 2  of the controller  104 , and the second multiplexer  105 B is for selectively electrically connecting the first interface MCU_I 1  of the controller  104  or the processor  103  (or the voltage level shifter  107 ) to the first multiplexer  105 A according to the selection signal SEL 3  of the controller  104 . 
     In some embodiments, the controller  104  may normally generate the selection signal SEL 3  having the second selection value to the second multiplexer  105 B, so that the second multiplexer  105 B normally electrically connects the first multiplexer  105 A to the processor  103  (or the voltage level shifter  107 ). In addition, the controller  104  may generate the selection signal SEL 3  having the first selection value to the second multiplexer  105 B only when the update data is received, so that the second multiplexer  105 B electrically connects the first multiplexer  105 A to the first interface MCU_I 1  of the controller  104 . 
     Thus, when the selection signal SEL 2  has the first selection value and the selection signal SEL 3  has the first selection value, the first multiplexer  105 A electrically connects the EDID ROM  106  to the second multiplexer  105 B, and the second multiplexer  105 B electrically connects the first multiplexer  105 A to the first interface MCU_I 1  of the controller  104 , such that the controller  104  may be electrically connected to the EDID ROM  106  by the first interface MCU_I 1  sequentially through the second multiplexer  105 B and the first multiplexer  105 A. Accordingly, the controller  104  can update the EDID ROM  106  using the update data. 
     In some embodiments, the update data may be stored in a storage device, and the processor  103  may obtain the update data by accessing the storage device. In some implementation forms, the storage device may be a hard drive or a portable disk. 
     Referring to  FIG.  12   , in one embodiment, the electronic device  100  having different output powers includes a connector  101 , a controller  104  and a power supply circuit  109 . The power supply circuit  109  is coupled to the connector  101 , and the controller  104  is coupled to the connector  101  and the power supply circuit  109 . 
     The connector  101  includes a detection pin P 1 , at least one signal pin P 2  and a power pin P 4 . The power supply circuit  109  is coupled to the power pin P 4 , and provides a first voltage V 1  to the power pin P 4 . Herein, the power supply circuit  109  normally provides the first voltage V 1  to the power pin P 4 . The controller  104  is electrically connected to the at least one signal pin P 2 , and monitors a detection pin P 1 . Upon detecting a hot-plug signal HPD occurring at the detection pin P 1 , it means that the electronic device  300  is connected to the electronic device  100  through the connector  101 , and the controller  104  issues a confirmation command C 1  via the at least one signal pin P 2  to request the electronic device  300  to return a device signal DEV as a reply. 
     When the device signal DEV is not received after the confirmation command C 1  is issued, or the device signal DEV as a reply is not received after repeatedly sending the confirmation command C 1  is over a predetermined number of times, the controller  104  controls the power supply circuit  109  (for example, outputting a first enable signal EN 1  to the power supply circuit  109 ) to keep providing the first voltage V 1  to the power pin P 4 . When the device signal DEV as a reply from the electronic device  300  is received after the confirmation command C 1  is issued, the controller  104  controls the power supply circuit  109  (for example, switches to output a second enable signal EN 2  to the power supply circuit  109 ) to switch to provide a second voltage V 2  higher than the first voltage V 1  to the power pin P 4 . 
     In some embodiments, the electronic device  100  having different output powers may further include a discharging circuit  110  which is coupled to the power pin P 4 . When the power supply circuit  109  provides the second voltage V 2  to the power pin P 4 , upon detecting by the controller  104  that the hot-plug signal HPD occurring at the detection pin P 1  has disappeared, the controller  104  controls the power supply circuit  109  to stop supplying power to the power pin P 4 , and controls the discharging circuit  110  to discharge the power pin P 4  so as to release the residual voltage from the power pin P 4 . After discharging for a predetermined period of time, the controller  104  again controls the discharging circuit  110  to stop discharging, and controls the power supply circuit  109  to restore supply of the first voltage V 1  to the power pin P 4 . 
     The electronic device  100  of any embodiment of the present invention is capable of performing the power supply method according to any embodiment.  FIG.  13    shows a flowchart of a power supply method according to an embodiment. Referring to  FIG.  13   , in the power supply method according to an embodiment, the controller  104  of the electronic device  100  may use the power supply circuit  109  to provide the first voltage V 1  to the power pin P 4  of the connector  101  (step S 21 ), and detect the detection pin P 1  of the connector  101  (step S 22 ). Upon detecting a hot-plug signal HPD occurring at the detection pin P 1 , the controller  104  issues the confirmation command C 1  via the at least one signal pin P 2  of the connector  101  to request the electronic device  300  to return the device signal DEV as a reply (step S 23 ). When the device signal DEV is not received, the controller  104  uses the power supply circuit  109  to keep providing the first voltage V 1  to the power pin P 4  (step S 24 ). When the device signal DEV is received, the controller  104  uses the power supply circuit  109  to switch to provide the second power V 2  to the power pin P 4  (step S 25 ). Wherein, the second voltage V 2  is higher than the first voltage V 1 . 
     In the power supply method according to an embodiment, when the power supply circuit  109  provides the second voltage V 2  to the power pin P 4 , upon detecting by the controller  104  that the hot-plug signal HPD occurring at the detection pin P 1  has disappeared, the controller  104  controls the power supply circuit  109  to stop supplying power to the power pin P 4 , and controls the discharging circuit  110  to discharge the power pin P 4  (step S 26 ). After discharging for a predetermined period of time, the controller  104  again controls the discharging circuit  110  to stop discharging, and controls the power supply circuit  109  to restore supply of the first voltage V 1  to the power pin P 4  (step S 27 ). 
     In conclusion, in the electronic device with a connector supporting multiple connection standards and the signal switching method thereof according to the embodiments of the present invention, the confirmation command is issued via at least one signal pin of the connector to request a reply of a device signal, and the transmission path of the at least one signal pin of the connector is switched according to whether the device signal is received, so that a single connector is enabled to support multiple connection standards. Thus, the electronic device is able to perform transmission with a common device or a special device via this single connector, and to selectively apply one from the multiple connection standards. Moreover, in the electronic device with a connector supporting multiple connection standards, the signal switching method thereof and the power supply method thereof, and the electronic device having different output powers according to the embodiments of the present invention, the confirmation command is issued via at least one signal pin of the connector to request a reply of a device signal, and the first voltage or the second voltage is selectively provided to the power pin according to whether the device signal is received, so that the electronic device is able to connect to a common device or a special device that uses different voltages via this single connector. 
     The technical contents of the present invention are disclosed by way of the preferred embodiments above. However, these embodiments are not to be construed as limitations to the present invention. Slight modifications and variations made by a person skilled in the art without departing from the spirit and scope of the present invention are encompassed within the scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.