Patent Publication Number: US-8988120-B2

Title: Frequency multiplier and signal frequency-multiplying method

Description:
This application claims the benefit of Taiwan application Serial No. 102100050, filed Jan. 2, 2013, the subject matter of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates in general to a frequency multiplier and a signal frequency-multiplying method, and more particularly, to a frequency multiplier and a signal frequency-multiplying method capable of reducing power consumption. 
     2. Description of the Related Art 
     In the prior art, the frequency of a signal is usually multiplied by a multiplier. However, as the multiplier frequently generates only one single signal, an additional circuit is to be added if generating differential signals is desired. As such, not only electric power consumption but also a circuit area is increased. 
     SUMMARY OF THE INVENTION 
     The invention is directed to a frequency multiplier and a signal frequency-multiplying method capable of generating differential signals without utilizing an additional circuit. 
     According to an embodiment of the present invention, a frequency multiplier is provided. The frequency multiplier comprises: a first output end; a second output end; a first impedance module, having one end coupled to a first predetermined potential level and the other end coupled to the first output end; a second impedance module, having one end coupled to a second predetermined potential level and the other end coupled to the second output end; a first path, coupled between the first output end and the second output end; and a second path, coupled between the first output end and the second output end. The first path and the second path receive an input signal and an inverted input signal, respectively. A phase of the inverted input signal is inverted to a phase of the input signal. The first path and the second path are conducted or non-conducted according to the input signal and the inverted input signal. When the first path is conducted, a first current flows from the first impedance module and passes along the first path to enter the second impedance module, so that the first impedance module generates a first output signal at the first output end and the second impedance module generates a second output signal at the second output end. When the second path is conducted, a second current flows from the first impedance module and passes along the second path to enter the second impedance module, so that the first impedance module generates a third output signal at the first output end and the second impedance module generates a fourth output signal at the second output end. The first path and the second path are not conducted simultaneously. A frequency of a first combination signal generated from the first and third output signals and a frequency of a second combination signal generated from the second and fourth output signals are an N times of a frequency of the input signal, where N is a positive rational number. 
     According to another embodiment of the present invention, a signal frequency-multiplying method for a frequency multiplier is provided. The frequency multiplier comprises a first path, a second path, a first impedance module and a second impedance module. The frequency-multiplying method comprises: receiving an input signal and an inverted input signal by the first path and the second path, respectively, wherein a phase of the inverted input signal is inverted to a phase of the input signal, and the first path and the second path are conducted or non-conducted according to the input signal and the inverted input signal; when the first path is conducted, rendering a first current to flow from the first impedance module and pass along the first path to enter the second impedance module, so that the first impedance module generates a first output signal at a first output end and the second impedance module generates a second output signal at a second output end; when the second path is conducted, rendering a second current to flow from the first impedance module and pass along the second path to enter the second impedance module, so that the first impedance module generates a third output signal at the first output end and the second impedance module generates a fourth output signal at the second output end; generating a first combination signal by combining the first output signal and the second output signal; and generating a second combination signal by combining the third output signal and the fourth output signal. The first path and the second path are not conducted simultaneously. A frequency of the first combination signal and a frequency of a second combination signal are N times of a frequency of the input signal, where N is a positive rational number. 
     Without implementing an additional circuit, the above embodiments are capable of generating frequency-multiplied differential signals as well as reducing power consumption and a circuit area. 
     The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a frequency multiplier according to an embodiment of the present invention. 
         FIG. 2  is a detailed exemplary circuit of the frequency multiplier in  FIG. 1 . 
         FIG. 3  is a schematic diagram depicting relations between currents and signals in the frequency multiplier in  FIG. 2 . 
         FIGS. 4 to 6  are other detailed exemplary circuits of the frequency multiplier in  FIG. 1 . 
         FIG. 7  is a signal frequency-multiplying method according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows a frequency multiplier  100  according to an embodiment of the present invention. As shown in  FIG. 1 , the frequency multiplier  100  comprises a first output end T o1 , a second output end T o2 , a first path  101 , a second path  103 , a first impedance module  105 , and a second impedance module  107 . The first path  101  and the second path  103 , both coupled between the first output end T o1  and the second output end T o2 , receive an input signal V in+  and an inverted input signal V in− , respectively. The phase of the inverted input signal V in−  is inverted to the phase of the input signal V in+ . The first path  101  and the second path  103  are conductive or non-conductive according to the input signal V in−  and the input signal V in+ . When the first path  101  is conducted, a first current I 1  flows from the first impedance module  105  and passes along the first path  101  to the second impedance module  107 , so that the first impedance module  101  generates a first output signal V o1  at the first output end T o1  and the second impedance module  107  generates a second output signal V o2  at the second output end T o2 . When the second path  103  is conducted, a second current I 2  flows from the first impedance module  105  and passes along the second path  103  to the second impedance module  107 , so that the first impedance module  105  generates a third output signal V o3  at the first output end T o1  and the second impedance module  107  generates a fourth output signal V o4  at the second output end T o2 . The first output signal V o1  and the third output signal V o3  are combined to generate a first combination signal V c1 ; the second output signal V o2  and the fourth output signal V o4  are combined to generate a second combination signal V c2 . The first path  101  and the second path  103  are not simultaneously conducted. The frequency of the first combination signal V c1  and the frequency of the second combination signal V c2  are N times of the frequency of the input signal V in+  or the inverted input signal V in− , where N is a positive rational number. 
       FIG. 2  shows a detailed exemplary circuit of the frequency multiplier shown in  FIG. 1 . As shown in  FIG. 2 , the first path  101  of the frequency multiplier  100  comprises a first N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) N 1  and a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) P 1 . The second path  103  comprises a second NMOSFET N 2  and a second PMOSFET P 2 . The first impedance module  105  comprises an inductor L 1  and a capacitor C a1 ; the second impedance module  107  comprises an inductor L 2  and a capacitor C a2 . The first NMOSFET N 1  comprises a first end T 1N1 , a second end T 2N1  and a control end T CN1 . The first PMOSFET P 1  comprises a first end T 1P1 , a second end T 2P1  and a control end T CP1 . The second NMOSFET N 2  comprises a first end T 1N2 , a second end T 2N2  and a control end T CN2 . The second PMOSFET P 2  comprises a first end T 1P2 , a second end T 2P2  and a control end T CP2 . Detailed connections between the components are as depicted in  FIG. 2 , and shall be omitted herein. It should be noted that the NMOSFETs and PMOSFETs can be replaced by other types of transistors. 
       FIG. 3  shows a schematic diagram of relations between the currents and signals of the frequency multiplier in  FIG. 2 . Referring to both  FIGS. 2 and 3  for operations of the frequency multiplier shown in  FIG. 2 , the control end T CN1  of the first NMOSFET N 1  and the control end T CP1  of the first PMOSFET P 1  of the first path  101  receive the input signal V in+  and the inverted input signal V in− , respectively. Thus, the first path  101  is conducted when the input signal V in+  is at a high potential level and when the inverted input signal V in−  is at a low potential level (periods T 1  and T 3  in  FIG. 3 ). The control end T CN2  of the second NMOSFET N 2  and the control end T CP2  of the second PMOSFET P 2  of the second path  103  receive the inverted input signal V in−  and the input signal V in+ , respectively. Thus, the second path  103  is conducted when the input signal V in+  is at a low potential level and when the inverted input signal V in−  is at a high potential level (periods T 2  and T 4  in FIG.  3 ). When the first path  101  is conducted, with the inductors L 1  and L 2  of the first impedance module  105  and the second impedance module  107 , the first output signal V o1  and the second output signal V o2  are generated from resonance, as shown in  FIG. 3 . Similarly, when the second path  103  is conducted, with the inductors L 1  and L 2  of the first impedance module  105  and the second impedance module  107 , the third output signal V o3  and the fourth output signal V o4  are generated from resonance, as shown in  FIG. 3 . Through the foregoing operations, the first combination signal T c1  is generated at the first output end T 1 , and the second combination signal T c2  is generated at the second output end T 2 . The first combination signal T c1  is generated by combining the first output signal V o1  and the third output signal V o3 , the second combination signal T c2  is generated by combining the second output signal V o2  and the fourth output signal V o4 . 
     In the embodiment, since the first combination signal T c1  and the second combination signal T c2  are generated by resonance of the input signal V in+  and the inverted input signal V in− , the frequencies of the first combination signal T c1  and the second combination signal T c2  display an integral multiple relationship with the frequencies of the input signal V in+  and the inverted input signal V in− . In this example, the frequencies of the first combination signal T c1  and the second combination signal T c2  are twice of the frequencies of the input signal V in+  and the inverted input signal V in− . By modifying the inductance values or capacitance values in the first impedance module  105  and the second impedance module  107 , the relationship between the two frequencies of the combination signals and the input signals may also be adjusted. More specifically, the frequencies of the first combination signal T c1  and the second combination signal T c2  are N times of the frequencies of the input signal V in+  and the inverted input signal V in− , where N is a positive rational number. 
       FIGS. 4 to 6  are other detailed exemplary circuits of the frequency multiplier in  FIG. 1 . In  FIG. 4 , a frequency multiplier  400  further includes capacitors C 1  and C 2 . The capacitor C 1  has one end coupled to the second end T 2N2  of the second NMOSFET N 2  and the other end coupled to ground. The capacitor C 2  has one end coupled to the second end T 2N2  of the second NMOSFET N 2  and the other end coupled to ground. Through the above structure, noises may be reduced while the current is kept stable. Again referring to  FIG. 2 , the second ends T 2N1  and T 2N2  of the first NMOSFET N 1  and the second NMOSFET N 2  are not coupled to each other, and the second ends T 2P1  and T 2P2  of the first PMOSFET P 1  and the second PMOSFET P 2  are not coupled to each other. In an embodiment shown in  FIG. 5 , in a frequency multiplier  500 , the second ends T 2N1  and T 2N2  of the first NMOSFET N 1  and the second NMOSFET N 2  as well as the second ends T 2P1  and T 2P2  of the first PMOSFET P 1  and the second PMOSFET P 2  are coupled to a same connection point T c . Through the structure in  FIG. 5 , circuit designs can be simplified. In an embodiment in  FIG. 6 , a frequency multiplier  600  further includes a capacitor C, which has one end coupled to the connection point T c  and the other end coupled to ground. Through the structure in  FIG. 6 , noises may be reduced while the current is kept stable. 
     Based on the above embodiments, a signal frequency-multiplying method is provided, as shown in  FIG. 7 . 
     In step  701 , an input signal V in+  and an inverted input signal V in−  are received by a first path  101  and a second path  103 , respectively. The phase of the inverted input signal V in−  is inverted to the phase of the input signal V in+ . The first path  101  and the second path  103  are conducted or non-conducted according to the input signal V in+  and the inverted input signal V in− . 
     In step  703 , when the first path  101  is conducted, a first current I 1  flows from a first impedance module  105  and passes along the first path  101  to a second impedance module  107 , so that the first impedance module  105  generates a first output signal V o1  at the first output end T o1  and the second impedance module  107  generates a second output signal V o2  at a second output end T o2 . 
     In step  705 , when the second path  103  is conducted, a second current I 2  flows from the first impedance module  105  and passes along the second path  103  to the second impedance module  107 , so that the first impedance module  105  generates a third output signal V o3  at the first output end T o1  and the second impedance module  107  generates a fourth output signal V o4  at a second output end T o2 . 
     In step  707 , a first combination signal V c1  is generated by combining the first output signal V o1  and the third output signal V o3 . 
     In step  709 , a second combination signal V c2  is generated by combining the second output signal V o2  and the fourth output signal V o4 . 
     The first path  101  and the second path  103  are not conducted simultaneously, and the frequencies of the first combination signal V c1  and the second combination signal V c2  are N times of that of the input signal, where N is a positive rational number. 
     The first combination signal V c1  and the second combination signal V c2  may be a pair of differential signals, or two independent signals. Thus, the foregoing frequency multiplier may be regarded as a frequency multiplier capable of generating differential signals, or as a frequency multiplier for generating two independent signals. 
     Without implementing an additional circuit, the above embodiments are capable of generating frequency-multiplied differential signals as well as reducing power consumption and a circuit area. 
     While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.