Patent Publication Number: US-6992005-B2

Title: Semiconductor device and method of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional application of prior application Ser. No. 10/127,418 filed Apr. 23, 2002 U.S. Pat. No. 6,750,541. 
     This application is based upon and claims priority of Japanese Patent Applications No. 2001-130694, filed in Apr. 27, 2001, and No. 2002-43117, filed in Feb. 20, 2002, the contents being incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a multi-layered wiring structure containing a copper layer wiring and a method of manufacturing the same. 
     2. Description of the Prior Art 
     Various semiconductor elements are miniaturized more and more with the progress of the process technology of the semiconductor integrated circuit (LSI). Also, the high density, the increase in layer number, and the reduction in thickness of the wirings in the LSI are making rapid progress, and thus the stress applied to the wirings and the density of the current flowing through the wirings are steadily increased respectively. Accordingly, when the current of the high density flows through the wirings, for example, the breaking phenomenon of the wiring that is called the electromigration (EM) is ready to occur. It is supposed that, the driving force of the electromigration is generated when metallic atoms are moved and diffused owing to the collision of the high-density electron flows. Since the degradation phenomenon by the electromigration becomes still more intense with the miniaturization of the element, the development of the wiring material and the wiring structure, through which the high-density current can be passed and which can achieve the high reliability, is required. 
     As the wiring in which the electromigration is hard to occur rather than the aluminum wiring, there is the copper wiring. 
     However, the fine patterning of the copper layer is difficult. As one of the effective approaches for manufacturing the copper wiring, the damascene method that has the steps of forming previously the wiring trench in the insulating film and then burying the copper layer therein is put to practical use. Also, the dual-damascene method that forms simultaneously the via and the wiring by forming the via hole under the wiring trench is known. 
     Then, an example of steps of forming the via by the damascene method is shown in  FIGS. 1A to 1D  hereunder. 
     First, as shown in  FIG. 1A , an interlayer insulating film  102  is formed on a semiconductor substrate  101 , and a first silicon oxide film  103  and a silicon nitride film  107  are formed on the interlayer insulating film  102 . Then, a first wiring trench  104  is formed in these films  103 ,  107  by patterning the first silicon oxide film  103  and the silicon nitride film  107 . Then, a barrier metal layer  105  and a first copper layer  106  are formed sequentially in the first wiring trench  104  and on the silicon nitride film  107  to bury the first wiring trench  104  completely. Then, the first copper layer  106  and the barrier metal layer  105  are polished by the chemical mechanical polishing (CMP) method and removed from the upper surface of the silicon nitride film  107 . 
     Accordingly, as shown in  FIG. 1B , the first copper layer  106  left only in the first wiring trench  104  is used as a copper wiring  106   a . Then, a second silicon oxide film  108  is formed on the silicon nitride film  107  and the copper wiring  106   a  respectively. 
     Then, as shown in  FIG. 1C , a via hole  109  is formed on the copper wiring  106   a  by patterning the second silicon oxide film  108 . 
     Then, as shown in  FIG. 1D , a second barrier metal layer  110  and a second copper layer  111  are formed in the via hole  109  and on the second silicon oxide film  108 . Then, the second copper layer  111  and the second barrier metal layer  110  are polished by the CMP method and removed from the upper surface of the second silicon oxide film  108 . Then, the second copper layer  111  left in the via hole  109  is used as a via  111   a.    
     The multi-layered copper wiring structure can be obtained by repeating the formation of the copper wiring and the formation of the via in compliance with above steps. 
     By the way, as shown in  FIG. 1C , if the via hole  109  is formed in the second silicon oxide film  108 , the copper wiring  106   a  is exposed from the via hole  109  and exposed directly to the outside air. 
     As a result, it is possible that the copper wiring  106   a  is contaminated, corroded and oxidized and thus the defective connection between the copper wiring  106   a  and the via  111   a  is caused. As its measure, the process of cleaning the copper wiring  106   a  from the via hole  109  is carried out. In this case, if the aspect ratio of the via hole  109  is increased, it becomes difficult to clean completely the surface of the copper wiring  106   a.    
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a semiconductor device that is capable of preventing the surface oxidation/corrosion of metal patterns used as the copper wiring or the via and a method of manufacturing the same. 
     According to the present invention, the cap layer made of the substance with which the electrical resistance on the first metal pattern film becomes smaller than the electrical resistance on the insulating film is formed on the first insulating film and the first metal pattern. The metal pattern is the copper wiring or the copper via, for example. 
     As the material of such cap layer, there are the zirconium nitride that is chemically stable, its compound, etc. It is preferable that the film thickness should be set to less than 20 nm. 
     Therefore, when the hole or the trench is formed on the first metal pattern and in the second insulating film formed on the first insulating film, the oxidation, the corrosion, and the contamination of the first metal pattern under the hole or the trench are prevented by the cap layer. 
     In addition, the second metal pattern formed in the hole or the trench is connected electrically to the first metal pattern via the cap layer. While, since the cap layer acts as the insulating portion on the first insulating film, the patterning of the cap layer can be omitted. 
     The zirconium, the titanium, the hafnium, the zirconium nitride, or any one of their compounds constituting such cap layer can be selectively etched on the first insulating film by adjusting the etching conditions while leaving on the first metal pattern. As a result, such cap layer may be removed selectively from the upper surface of the first insulating film by the selective etching without the mask, and may be left on the first metal pattern. 
     If it is intended to prevent surely the copper diffusion from the first metal pattern containing the copper to the insulating film, the second cap layer made of the copper diffusion preventing insulating material may be formed on the cap layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A to 1D  are sectional views showing steps of forming the multi-layered copper wiring structure in the prior art; 
         FIGS. 2A to 2F  are sectional views showing a semiconductor device manufacturing method according to a first embodiment of the present invention; 
         FIG. 3  is a sectional view showing a sample employed to check an underlying-layer dependency of a resistivity of a zirconium nitride film used in the semiconductor device according to the embodiment of the present invention; 
         FIG. 4  is a graph showing a relationship between a film thickness and the resistivity of the zirconium nitride film on the insulating film; 
         FIG. 5  is a graph showing a relationship between the film thickness and the resistivity of the zirconium nitride film on the metal film; 
         FIGS. 6A to 6L  are sectional views showing a semiconductor device manufacturing method according to a second embodiment of the present invention; 
         FIG. 7  is a graph showing changes in resistance of the wiring by annealing the copper wiring and the conductive cap layer formed thereon in the semiconductor device according to the embodiment of the present invention; 
         FIGS. 8A to 8C  are views showing a relationship between a film thickness of a ZrN cap layer on the copper wiring and a wiring resistance in the semiconductor device according to the embodiment of the present invention respectively; and 
         FIGS. 9A to 9E  are sectional views showing a semiconductor device manufacturing method according to a third embodiment of the present invention. 
         FIGS. 10A to 10E  are sectional views showing a semiconductor device manufacturing method according to a fourth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention will be explained with reference to the accompanying drawings hereinafter. 
     (First Embodiment) 
       FIGS. 2A to 2F  are sectional views showing steps of manufacturing a semiconductor device according to a first embodiment of the present invention. 
     First, a structure shown in  FIG. 2A  will be explained hereunder. 
     An element isolation insulating layer  2  is formed on a p-type silicon (semiconductor) substrate  1  to surround an active element region. A MOS transistor  3  is formed in the active element region. The MOS transistor  3  has a gate electrode  3   b  that is formed on the silicon substrate  1  by way of a gate insulating film  3   a , and first and second n-type impurity diffusion layers  3   c ,  3   d  that are formed on the silicon substrate  1  on both sides of the gate electrode  3   b  respectively to have the LDD structure. Also, an insulating sidewall  3   e  is formed on both side surfaces of the gate electrode  3   b.    
     A first interlayer insulating film  4  made of SiO 2  is formed on the silicon substrate  1  to cover the MOS transistor  3 . A first contact hole  4   a  and a second contact hole  4   b  are formed in the first interlayer insulating film  4  on the first n-type impurity diffusion layer  3   c  and the second n-type impurity diffusion layer  3   d  respectively. 
     A first conductive plug  5   a  and a second conductive plug  5   b  are buried in the first and second contact holes  4   a ,  4   b  respectively. The first and second conductive plugs  5   a ,  5   b  have a double-layered structure consisting of a titanium nitride film and a tungsten film respectively. 
     A first-layer wiring  7  that is connected to the second conductive plug  5   b  and made of aluminum is formed on the first interlayer insulating film  4 . Also, a second interlayer insulating film  8  made of any one of SiO 2 , BPSG, PSG, etc. is formed on the first interlayer insulating film  4  and the first-layer wiring  7 . A contact hole  8   a  is formed in the second interlayer insulating film  8  on the first conductive plug  5   a . A third conductive plug  9  having a double-layered structure consisting of the titanium nitride film and the tungsten film is buried in the contact hole  8   a.    
     The second interlayer insulating film  8  and the third conductive plug  9  is covered with a third interlayer insulating film  10  that has a thickness of 350 nm and is made of SiO 2 . Then, a first wiring trench  10   a  and a second wiring trench  10   b  are formed in the third interlayer insulating film  10 . 
     The first wiring trench  10   a  has a shape a part of which overlaps with the third conductive plug  9 . A first copper wiring  12   a  having a multi-layered structure consisting of a barrier metal layer  11   a  made of tantalum, tantalum nitride, titanium nitride, or the like and a copper layer  11   b  is formed in the first wiring trench  10   a . Also, a second copper wiring  12   b  having the same layer structure as the first copper wiring  12   a  is formed in the second wiring trench  10   b.    
     After the first and second copper wirings  12   a ,  12   b  are formed as described above, as shown in  FIG. 2B , a first cap layer  13  made of zirconium nitride (ZrN) is formed on the third interlayer insulating film  10  and the first and second copper wirings  12   a ,  12   b . The formation of the zirconium nitride may be executed by the CVD method using tetrakisdiethylaminozirconium (Zr{N(C 2 H 5 ) 2 } 4 ; TDEAZ) or the PVD method such as the sputter, the evaporation, or the like. 
     The ZrN cap layer  13  is formed to have a thickness that is larger than 0 nm but is less than 20 nm. Such ZrN cap layer  13  acts as a low resistance layer  13   a , whose resistivity is less than about 300 μΩ·cm, in the region where the ZrN cap layer  13  contacts to the barrier metal layer  11   a  and the copper layer  11   b  constituting the first and second copper wirings  12   a ,  12   b , and acts as a high resistance layer  13   b , whose resistivity is more than several thousands μΩ·cm or more than tens of thousands of μΩ·cm, in the region where the ZrN cap layer  13  contacts to the third interlayer insulating film  10  made of SiO 2 . Their details will be described later. 
     Then, as shown in  FIG. 2C , a fourth interlayer insulating film  14  having a thickness of 350 nm and made of SiO 2  is formed on the ZrN cap layer  13  by the CVD method. And, a silicon nitride film  15  having a thickness of 50 nm is formed on the fourth interlayer insulating film  14  by the CVD. More, a fifth interlayer insulating film  16  having a thickness of 300 nm and made of SiO 2  is formed on the silicon nitride film  15 . In this case, a zirconium nitride film having a thickness of less than 20 nm may be employed in place of the silicon nitride film  15 . 
     Then, as shown in  FIG. 2D , the fifth interlayer insulating film  16  is patterned, so that a third wiring trench  16   a  a part of which overlaps with the first copper wiring  12   a  is formed and simultaneously a fourth wiring trench  16   b  a part of which overlaps with the second copper wiring  12   b  is formed. Also, the fourth interlayer insulating film  14  is patterned, so that a first via hole  14   a  is formed in the region at which the third wiring trench  16   a  overlaps with the first copper wiring  12   a  and at the same time a second via hole  14   b  is formed in the region at which the fourth wiring trench  16   b  overlaps with the second copper wiring  12   b.    
     The order of the formation of the first and second via holes  14   a ,  14   b  and the formation of the third and fourth wiring trenches  16   a ,  16   b  may be selected arbitrarily. The silicon nitride film  15  can function as the etching stopper layer at the time when the third and fourth wiring trenches  16   a ,  16   b  are formed. 
     These via holes  14   a ,  14   b  are formed on the first-layer copper wirings  12   a ,  12   b  respectively to expose the low resistance layer  13   a  of the ZrN cap layer  13 . 
     Then, as shown in  FIG. 2E , a barrier metal layer  17  of 5 to 10 nm thickness is formed on inner peripheral surfaces and bottom surfaces of the first and second via holes  14   a ,  14   b  and the third and fourth wiring trenches  16   a ,  16   b  and on the upper surface of the fifth interlayer insulating film  16  respectively. The barrier metal layer  17  is formed by the sputter method and is formed any one of tantalum (Ta), tantalum nitride (TaN), and their laminated film, or titanium nitride (TiN), for example. 
     In addition, a copper seed layer  18  is formed on the barrier metal layer  17  by the sputter method to have a thickness of 30 to 100 nm. 
     Then, a copper layer  19  is formed on the copper seed layer  18  by the electrolytic plating, whereby the third and fourth wiring trenches  16   a ,  16   b  and the first and second via holes  14   a ,  14   b  are completely buried. Here, the copper seed layer  18  becomes a part of the copper layer  19 . 
     Then, as shown in  FIG. 2F , the copper layer  19  and the barrier metal layer  17  formed on the fifth interlayer insulating film  16  are removed by the CMP method. Thus, the copper layer  19 , the copper seed layer  18 , and the barrier metal layer  17  left in the first and second via holes  14   a ,  14   b  are used as first and second vias  20   a ,  20   b  respectively. Also, the copper layer  19  and the barrier metal layer  17  left in the third and fourth wiring trenches  16   a ,  16   b  are used as third and fourth copper wirings  21   a ,  21   b  respectively. 
     The third copper wiring  21   a  is connected electrically to the first copper wiring  12   a  via the first via  20   a  and the cap layer  13 . Also, the fourth copper wiring  21   b  is connected electrically to the second copper wiring  12   b  via the second via  20   b  and the cap layer  13 . 
     In addition, after a second-layer cap layer (not shown) that is made of the same material as the above cap layer  13  and has a thickness of less than 20 nm is formed on the third and fourth copper wirings  21   a ,  21   b  and the fifth interlayer insulating film  16 , the copper wiring having the multi-layered structure can be formed on the second interlayer insulating film  8  by repeating the formations of the interlayer insulating film, the copper wiring and the via in compliance with the above steps. 
     Meanwhile, the first and second vias  20   a ,  20   b  are connected to the first and second copper wirings  12   a ,  12   b  via the low resistance layer  13   a  of the ZrN cap layer  13 , which has a thickness of less than 20 nm, respectively. In this case, since the ZrN cap layer  13  acts as the high resistance layer  13   b  on the second interlayer insulating film  10  made of SiO 2 , the third copper wiring  21   a  and the fourth copper wiring  21   b  are never short-circuited via the ZrN cap layer  13 . In addition, since the zirconium nitride is chemically stable and is less oxidized than the copper, it is not possible that the ZrN cap layer  13  is oxidized or corroded even when such layer is exposed through the via hole and the wiring trench. Thus, the ZrN cap layer  13  can serve as the conductive/insulating protection film that prevents the oxidation and the corrosion of the copper wiring and the copper via. 
     The event that the electrical resistance value of the zirconium nitride film depends on the material of the underlying layer will be explained hereunder. 
     First, as shown in  FIG. 3 , an insulating film  31  having a thickness of 100 nm and made of SiO 2  and a metal film  32  having a thickness of 50 nm and made of titanium nitride (TiN) are formed in sequence on a silicon wafer  30 , and then a part of the insulating film  31  is exposed by patterning the metal film  32 . Then, a zirconium nitride (ZrN) film  33  is formed on the insulating film  31  and the metal film  32  by the CVD method. As the material used to form the zirconium nitride film  33  by the CVD method, TDEAZ and ammonia (NH 3 ) are employed. Also, the temperature of the silicon wafer  30  is set at 380° C. when the zirconium nitride film  33  is to be grown. 
     When a relationship between the film thickness and the resistivity of the zirconium nitride film  33  formed on the SiO 2  insulating film  31  is examined while changing the film thickness of the ZrN film  33  formed under such conditions, results shown in  FIG. 4  are obtained. According to  FIG. 4 , the resistivity of the zirconium nitride film  33  becomes about 3300 μΩ·cm when the film thickness is 20 nm, and the resistivity is abruptly increased when the film thickness is less than about 18.7 nm, and the resistivity becomes 10000 μΩ·cm when the film thickness is 17.8 nm. In this case, even if a silicon oxide nitride film, a silicon nitride film, or a silicon oxide fluoride film is used as the insulating film  31 , the similar results can be obtained. 
     While, when a relationship between the film thickness and the resistivity of the zirconium nitride film  33  formed on the TiN metal film  32  is examined, results shown in  FIG. 5  are obtained. If the copper film is used as the metal film  32 , the similar results are obtained. 
     According to  FIG. 4  and  FIG. 5 , if the zirconium nitride film  33  is formed on the insulating film  31  to have the thickness of less than 20 nm, the resistivity is increased to give the insulating film whose resistivity is more than several thousands μΩ·cm. In contrast, even if the film thickness of the zirconium nitride film  33  is less than 20 nm, the zirconium nitride film  33  formed on the metal film  32  acts as the conductive film whose resistivity is less than about 300 μΩ·cm. 
     As a result, it is understood that the resistivity of the zirconium nitride film depends on the material of an underlying film. This nature is similar in case the zirconium nitride film is formed by not the CVD method but the PVD method such as the sputter, the evaporation, or the like. 
     In this case, as the cap layer  13 , a film made of any substance of the zirconium nitride compound, the zirconium, the titanium, the hafnium, the zirconium compound, the titanium compound, or the hafnium compound may be formed in place of the zirconium nitride to have a thickness that is larger than 0 nm but less than 20 nm, for example. If the substance constituting the cap layer  13  is formed by the PVD method such as the sputter, etc., it is preferable that such substance should be oxidized on the third interlayer insulating film  10  by using the oxygen in the third interlayer insulating film  10  by annealing the formed substance at the temperature of almost 400° C., for example, to increase the electrical resistance. Also, if the oxidation of the substance constituting the cap layer  13  on the copper wirings  12   a ,  12   b  must be prevented perfectly, it is preferable that the cap layer  13  should be alloyed with upper portions of the first and second copper wirings (copper patterns)  12   a ,  12   b.    
     In the meanwhile, after the silicon oxide film of 100 nm thickness and the zirconium nitride film of 10 nm thickness were formed sequentially on the silicon wafer, the titanium nitride (TiN) film of 50 nm thickness was formed on the zirconium nitride film at the wafer temperature of 350° C. by the CVD method using the tetrakisdiethylaminotitanium (TDEAT) and the ammonia (NH 3 ). Then, when the resistivity of the titanium nitride film was measured, 200 μΩ·cm was obtained. Thus, it is found that the resistance of the TiN film (metal film) formed on the portion, whose resistance is increased higher, of the zirconium nitride film is not increased higher. 
     (Second Embodiment) 
     In the first embodiment, the cap layer  13  made of ZrN, Zr, Hf, or the like is formed on the copper wirings  12   a ,  12   b  and the third interlayer insulating film  10 . If the copper wirings  12   a ,  12   b  and the cap layer  13  are alloyed with each other by the annealing process, there is a possibility that copper elements are diffused from the cap layer  13  into the third interlayer insulating film  10  and the fourth interlayer insulating film  14 . 
     Therefore, steps of forming the semiconductor device having the structure that is able to prevent the copper diffusion into the third and fourth interlayer insulating films  10 ,  14  without fail will be explained hereunder. 
       FIGS. 6A to 6L  are sectional views showing steps of manufacturing a semiconductor device according to a second embodiment of the present invention. In  FIGS. 6A to 6L , the same symbols as those in  FIGS. 2A to 2f  denote the same elements. 
     First, steps required to form the structure shown in  FIG. 6A  will be explained hereunder. 
     The element isolation insulating layer  2  is formed on the p-type silicon substrate  1  to surround the active element region, and then the MOS transistor  3  having the structure shown in the first embodiment is formed in the active element region. 
     Then, the first interlayer insulating film  4  made of SiO 2  is formed on the silicon substrate  1  to cover the MOS transistor  3 . Then, the first contact hole  4   a  and the second contact hole  4   b  are formed in the first interlayer insulating film  4  on the first n-type impurity diffusion layer  3   c  and the second n-type impurity diffusion layer  3   d  respectively. Then, the first conductive plug  5   a  and the second conductive plug  5   b  are buried in the first contact hole  4   a  and the second contact hole  4   b  respectively. The first and second conductive plugs  5   a ,  5   b  have the double-layered structure consisting of the titanium nitride film and the tungsten film respectively. 
     Then, the first-layer wiring  7  that is connected to the second conductive plug  5   b  and made of aluminum is formed on the first interlayer insulating film  4 . Then, the second interlayer insulating film  8  is formed on the first interlayer insulating film  4  and the first-layer wiring  7 . Then, the contact hole  8   a  is formed in the second interlayer insulating film  8  on the first conductive plug  5   a , and then the third conductive plug  9  having the double-layered structure consisting of the titanium nitride film and the tungsten film is buried in the contact hole  8   a.    
     In this state, the third interlayer insulating film  10  that has a thickness of 300 nm and made of SiO 2  is formed on the second interlayer insulating film  8  and the third conductive plug  9  by the CVD method. Then, the silicon nitride film of 50 nm thickness is formed on the third interlayer insulating film  10  by the CVD method as a insulating first stopper layer  40 . 
     Then, resist  39  is coated on the first stopper layer  40 , and then opening portions  39   a ,  39   b  having wiring patterns that pass over the third conductive plug  9  are formed by exposing/developing the resist  39 . 
     Then, as shown in  FIGS. 6B and 6C , the first and second wiring trenches  10   a ,  10   b  are formed in the first stopper layer  40  and the third interlayer insulating film  10  by the etching using the resist  39  as a mask. The first wiring trench  10   a  has a shape a part of which is positioned on the third conductive plug  9 . In this case, as shown in  FIG. 6C , the first and second wiring trenches  10   a ,  10   b  may be formed by etching the third interlayer insulating film  10  while using the first stopper layer  40 , in which openings are formed, as a mask. 
     Then, as shown in  FIG. 6D , the first barrier metal layer  11   a  is formed on inner peripheral surfaces and bottom surfaces of the first and second wiring trenches  10   a ,  10   b  and the upper surface of the first stopper layer  40  respectively. The barrier metal layer  11   a  is formed by the sputter method and is made of any one of Ta, TaN, and their laminated film, or TiN, for example. 
     In addition, the copper seed layer  11   s  is formed on the barrier metal layer  11   a  by the sputter method to have a thickness of 30 to 100 nm. 
     Then, as shown in  FIG. 6E , the copper layer  11   b  is formed on the copper seed layer  11   s  by the electrolytic plating method, whereby the first and second wiring trenches  10   a ,  10   b  are completely buried. In this case, the copper seed layer  11   s  is contained in the copper layer  11   b.    
     Then, as shown in  FIG. 6F , the copper layer  11   b  and the barrier metal layer  11   a  formed on the upper surface of the third interlayer insulating film  10  are removed by the CMP method. Here the first stopper layer  40  acts as the CMP stopper. Accordingly, the copper layer  11   b  and the barrier metal layer  11   a  left in the first and second wiring trenches  10   a ,  10  are used as the first and second copper wirings  12   a ,  12   b  respectively. 
     After the first-layer copper wirings  12   a ,  12   b  are formed as above, as shown in  FIG. 6G , the first cap layer  13  made of zirconium nitride (ZrN) is formed on the first stopper layer  40  and the first and second copper wirings  12   a ,  12   b . This first cap layer  13  is formed by the ZrN forming method explained in the first embodiment. 
     As explained in the first embodiment, the first cap layer  13  made of ZrN is formed to have a thickness that is larger than 0 nm but smaller than 20 nm. Such ZrN cap layer  13  acts as the low resistance layer  13   a , whose resistivity is less than about 300 μΩ·cm, in the region where the ZrN cap layer  13  contacts to the barrier metal layer  11   a  and the copper layer  11   b  constituting the first and second copper wirings  12   a ,  12   b , and acts as the high resistance layer  13   b , whose resistivity is more than several thousands μΩ·cm or more than tens of thousands of μΩ·cm, in the region where the ZrN cap layer  13  contacts to the third interlayer insulating film  10  made of SiO 2 . 
     Then, as shown in  FIG. 6H , an insulating second cap layer  41  having the copper diffusion preventing function is formed on the first cap layer  13 . As the second cap layer  41 , an insulating layer made of silicon carbide (SiC), silicon nitride (SiN), or substance containing them as the base element, an insulating layer made of silicon carbide oxide (SiCO), silicon oxide nitride (SiON), or substance containing them as the base element, or the like is formed by the plasma-enhanced chemical vapor deposition (PE-CVD) method to have a thickness of 20 to 100 nm. 
     Typically the growth of these insulating layers constituting the second cap layer  41  is carried out by employing the parallel-plate type PE-CVD equipment, then introducing the material gas into the vacuum chamber, into which the silicon substrate  1  is loaded, through the shower head, then adjusting the substrate temperature at 350 to 400° C. by the pedestal, and then applying the high frequency power, whose power is 300 to 600 W and whose frequency is 13.56 MHz, to the electrode that opposes to the substrate. 
     In the formation of the silicon carbide, the organic silane formed mainly of the methylsilane is employed as the material, and also methane, ammonia, nitrogen, helium, etc. are added if necessary. 
     Also, in the formation of the silicon carbide oxide, the oxygen source such as the oxygen, the nitrogen monoxide, etc. is added to the gas used to form the silicon carbide. Normally, if the oxygen is added to the insulating film, there is the advantage that the dielectric constant of the film can be lowered and thus the adhesion between the insulating films can be improved, but the function as the copper diffusion preventing film is lowered. 
     In the formation of the silicon nitride, such silicon nitride is grown by the PE-CVD method, like the silicon carbide insulating film. In this case, typically the silane gas such as SiH 4 , Si 2 H 6 , etc. is used as the silicon material gas, and the silicon nitride may be also formed by using the organic silane gas. The nitrogen or the ammonia is supplied to the growth atmosphere as the nitrogen supply source together with the silicon material gas. In the formation of the silicon oxide nitride, the oxygen source such as the oxygen, the nitrogen monoxide is added to the gas used to grow the silicon nitride. 
     Then, the second cap layer  41  is formed under such conditions. Then, as shown in  FIG. 6I , a fourth interlayer insulating film  42  that has a thickness of 600 nm and is made of SiO 2  and a second stopper layer  43  that has a thickness of 50 nm and is made of silicon nitride are formed in sequence on the second cap layer  41  by the CVD method. 
     Then, as shown in  FIG. 6J , the second stopper layer  43 , the fourth interlayer insulating film  42 , and the second cap layer  41  are patterned, so that first and second via holes  41   a ,  41   b  to expose the low resistance layer  13   a  of the first cap layer  13  are formed in the second stopper layer  43 , the fourth interlayer insulating film  42 , and the second cap layer  41 , and also third and fourth wiring trenches  42   a ,  42   b  that overlap with the first and second via holes  41   a ,  41   b  respectively are formed in the second stopper layer  43  and the fourth interlayer insulating film  42 . The third and fourth wiring trenches  42   a ,  42   b  are formed to have a depth of about 350 nm from the upper surface of the second stopper layer  43 . 
     It may be selected arbitrarily which one of the formation of the first and second via holes  41   a ,  41   b  and the formation of the third and fourth wiring trenches  42   a ,  42   b  should be executed earlier, and separate resist patterns are employed as a mask respectively. Also, if the etching stopper layer such as the silicon nitride layer is formed in the middle of the fourth interlayer insulating film, the first and second via holes  41   a ,  41   b  and the third and fourth wiring trenches  42   a ,  42   b  may be formed by the steps similar to the first embodiment. The formation of the etching stopper layer in the fourth interlayer insulating film may be employed in following embodiments. 
     Then, as shown in  FIG. 6K , a barrier metal layer  44   a  is formed on respective inner peripheral surfaces and bottom surfaces of the first and second via holes  41   a ,  41   b  and the third and fourth wiring trenches  42   a ,  42   b  and on the upper surface of the second stopper layer  43 . The barrier metal layer  44   a  is formed by the sputter method and is constructed by any one of Ta, TaN, and their laminated film, or TiN, for example. 
     In addition, a copper seed layer  44   s  is formed on the barrier metal layer  44   a  by the sputter method to have a thickness of 30 to 100 nm. 
     Then, a copper layer  44   b  is formed on the copper seed layer  44   s  by the electrolytic plating method, whereby the third and fourth wiring trenches  42   a ,  42   b  and the first and second via holes  41   a ,  41   b  are buried completely. The copper seed layer  44   s  is formed integrally with the copper layer  44   b.    
     Next, steps required to form the structure shown in  FIG. 6L  will be explained hereunder. 
     The copper layer  44   b  and the barrier metal layer  44   a  are moved from the upper surface of the second stopper layer  43  by the CMP method while using the second stopper layer  43  as a polishing stopper. Thus, the copper layer  44   b  and the barrier metal layer  44   a  left in the first and second via holes  41   a ,  41   b  respectively are employed as first and second vias  45   a ,  45   b  whereas the copper layer  44   b  and the barrier metal layer  44   a  left in the third and fourth wiring trenches  42   a ,  42   b  are employed as third and fourth copper wirings  46   a ,  46   b  respectively. 
     The third copper wiring  21   a  is connected electrically to the first copper wiring  12   a  via the first via  20   a  and the cap layer  13 . Also, the fourth copper wiring  21   b  is connected electrically to the second copper wiring  12   b  via the second via  20   b  and the cap layer  13 . 
     Then, a third cap layer  47  made of the same material as the first cap layer  13  and a fourth cap layer  48  made of the same material as the second cap layer  43  are formed sequentially on the third and fourth copper wirings  46   a ,  46   b  and the second stopper layer  43 . 
     In addition, the copper wiring having the multi-layered structure is formed on the second interlayer insulating film  8  by repeating the same formations of the interlayer insulating films, the copper wirings, and the vias as described above. 
     In the semiconductor device constructed as above, the portions of the first and third cap layers  13 ,  47  made of ZrN, which are to be connected to the copper wirings  12   a ,  12   b ,  46   b , can act as the low resistance layer, while the portions of the first and third cap layers  13 ,  47 , which are to be connected to the insulating first and second stopper layers  40 ,  43 , can act as the high resistance layer. 
     If the first and second copper wirings  12   a ,  12   b  and the first cap layer  13  are alloyed with each other by the annealing, it is possible that the copper is diffused from the cap layer  13  to the fourth interlayer insulating film  42 . However, in the present embodiment, since the insulating second cap layer  41  for preventing the copper diffusion is formed further on the first cap layer made of ZrN, the copper diffusion from the first and second copper wirings  12   a ,  12   b  to the fourth interlayer insulating film  42  can be prevented without fail by the second cap layer  41 . Also, if the first and second stopper layers  40 ,  43  are formed of the silicon nitride, they can also function as the copper diffusion preventing layer. 
     By the way, as shown in  FIG. 6G , when it was examined how the sheet resistance of the copper wirings  12   a ,  12   b  is changed by the annealing after the first cap layer  13  made of ZrN is formed on the copper wirings  12   a ,  12   b , results shown in  FIG. 7  are obtained. Thus, it was found that the sheet resistance is seldom changed. 
     A broken line in  FIG. 7  shows a difference between the, sheet resistance, which is obtained when the annealing is not applied, and the sheet resistance, which is obtained when the annealing is applied, of the copper wiring  12   a ,  12   b  without the formation of the first cap layer  13 . Also, a solid line in  FIG. 7  shows a difference between the sheet resistance, which is obtained when the annealing is not applied, and the sheet resistance, which is obtained when the annealing is applied, of the copper wiring  12   a ,  12   b  to which the first cap layer  13  of 2.5 nm thickness is connected. In addition, a dot-dash line in  FIG. 7  shows a difference between the sheet resistance, which is obtained when the annealing is not applied, and the sheet resistance, which is obtained when the annealing is applied, of the copper wiring  12   a ,  12   b  to which the first cap layer  13  of 5.0 nm thickness is connected. 
       FIGS. 8A to 8C  show examined result of a relationship between the resistance of the copper wirings, which means the ZrN cap layer  13  and the copper wirings  12   a ,  12   b  totally, and the film thickness of the ZrN cap layer  13 . In this case, in  FIGS. 8A to 8C , plural vertical lines show wiring widths of 8 μm (∘), 4 μm (□), 2 μm (⋄), 1 μm (×), 0.54 μm (+), and 0.27 μm (Δ) in order from the left respectively. 
       FIG. 8A  shows a relationship between the resistance values of the copper wirings  12   a ,  12   b  and a cumulative percentage when the ZrN cap layer  13  is not formed.  FIG. 8B  shows a relationship between the resistance values of the copper wirings and the cumulative percentage when the ZrN cap layer  13  of 2 nm thickness is formed on the copper wirings  12   a ,  12   b .  FIG. 8C  shows a relationship between the resistance values of the copper wirings and the cumulative percentage when the ZrN cap layer  13  of 4 nm thickness is formed on the copper wirings  12   a ,  12   b.    
     According to  FIGS. 8A to 8C , the dependency of the resistance of the cap wirings on the ZrN film thickness is not found. 
     In this case, as the insulating/conductive cap layers  13 ,  47 , the film made of any one of the zirconium nitride compound, the zirconium, the titanium, the hafnium, the zirconium compound, the titanium compound, and the hafnium compound may be applied instead of the zirconium nitride. Such materials are true of following embodiments. 
     (Third Embodiment) 
       FIGS. 9A to 9E  are sectional views showing steps of forming a semiconductor device according to a third embodiment of the present invention. In  FIGS. 9A to 9E , the same symbols as those in  FIGS. 6A to 6L  denote the same elements. 
     In accordance with the steps shown in  FIGS. 6A to 6F  in the second embodiment, the MOS transistor  3  is formed on the silicon substrate  1 , then the interlayer insulating films  4 ,  8 ,  10  and the first stopper layer  40  are formed, then the wiring  7  is formed, then conductive plugs  5   a ,  5   b ,  9  are formed, and then the first and second copper wirings  12   a ,  12   b  are formed. 
     Then, as shown in  FIG. 9A , the first cap layer  13  made of ZrN is formed on the first and second copper wirings  12   a ,  12   b  and the first stopper layer  40 . The film thickness of the first cap layer  13  is not limited below 20 nm as described in the first and second embodiments, and the first cap layer  13  is formed to have a thickness of 40 nm, for example. 
     Then, as shown in  FIG. 9B , the first cap layer  13  is etched by the selective etching such that such first cap layer  13  is removed from the upper surface of the third interlayer insulating film  10  but left on the first and second copper wirings  12   a ,  12   b . Such selective etching is carried out under following conditions, for example. 
     Although depending on the CVD conditions such as the growth temperature, the gas flow rate, the addition amount of ammonia, etc., the film density of the ZrN layer is largely different in the metal phase (the low resistance layer  13   a ) on the metal film and the insulating phase (the high resistance layer  13   b ) on the insulating film. That is, in the ZrN layer, typically the film density of the insulating phase is 5.0 to 5.5 g/cm 3  while the film density of the metal phase is 6.0 to 6.6 g/cm 3 . Accordingly, since the etching rate of the ZrN layer according to various etchants depends on the film density, the ZrN insulating phase can be removed selectively by utilizing this nature. If the aqueous solution such as hydrofluoric acid, hydrochloric acid, sulfuric acid, etc. or the chemicals such as hydrogen peroxide, etc. as the etchant is appropriately heated, the desired etching rate against the ZrN film can be obtained. 
     For example, the etching rate of the metal phase ZrN by the hydrofluoric acid at the temperature of 25° C. is 40 nm/min whereas the etching rate of the insulating phase ZrN is 53 nm/min. Therefore, as shown in  FIG. 9A , if the first cap layer  13  having a thickness of 40 nm and made of ZrN is formed on the first and second copper wirings  12   a ,  12   b  and the third interlayer insulating film  10  and then the hydrofluoric acid of the concentration 1 wt % is supplied to the first cap layer  13  for 45 seconds, the first cap layer  13  of 10 nm thickness can be left only on the first and second copper wirings  12   a ,  12   b , as shown in  FIG. 9B . 
     As the etching equipment for etching the ZrN, the batch type etching equipment or the sheet-fed type etching equipment may be employed. However, it is preferable that, in order to etch the first cap layer  13  for a short time with good uniformity, the sheet-fed type etching equipment should be employed. 
     After the first cap layer  13  is etched by the selective etching as described above, as shown in  FIG. 9C , the fourth interlayer insulating film  42  that has a thickness of 600 nm and is made of SiO 2  and the second stopper layer  43  that has a thickness of 50 nm are formed sequentially on the first cap layer  13  and the first stopper layer  40  by the CVD method. 
     Then, as shown in  FIG. 9D , the second stopper layer  43  and the fourth interlayer insulating film  42  are patterned. Thus, the first and second via holes  41   a ,  41   b  to expose the first cap layer  13  are formed in the second stopper layer  43 , the fourth interlayer insulating film  42 , and the second cap layer  41 , and also the third and fourth wiring trenches  42   a ,  42   b  a part of which overlaps with the first and second via holes  41   a ,  41   b  respectively are formed in the second stopper layer  43  and the fourth interlayer insulating film  42 . Accordingly, the first cap layer  13  is exposed through the first and second via holes  41   a ,  41   b.    
     Next, steps required to form the structure shown in  FIG. 9E  will be explained hereunder. 
     Like the second embodiment, the barrier metal layer  44   a  is formed on the inner peripheral surfaces and the bottom surfaces of the first and second via holes  41   a ,  41   b  and the third and fourth wiring trenches  42   a ,  42   b  and on the upper surface of the second stopper layer  43  respectively. In addition, the copper seed layer (not shown) is formed on the barrier metal layer  44   a  to have a thickness of 30 to 100 nm. 
     The barrier metal layer  44   a  is formed by the sputter method, and is constructed any one of Ta, TaN, and their laminated film, or TiN, for example. Also, the copper seed layer is formed by the sputter method to have a thickness of 30 to 100 nm. 
     Then, the copper layer  44   b  is formed on the copper seed layer by the electrolytic plating method. Thus, the third and fourth wiring trenches  42   a ,  42   b  and the first and second via holes  41   a ,  41   b  are buried perfectly. In this case, the copper seed layer is formed integrally with the copper layer  44   b.    
     In addition, the copper layer  44   b  and the barrier metal layer  44   a  are moved from the upper surface of the second stopper layer  43  by the CMP method while using the second stopper layer  43  as the polishing stopper. Thus, the copper layer  44   b  and the barrier metal layer  44   a  left in the first and second via holes  41   a ,  41   b  respectively are employed as first and second vias  45   a ,  45   b , while the copper layer  44   b  and the barrier metal layer  44   a  left in the third and fourth wiring trenches  42   a ,  42   b  respectively are employed as third and fourth copper wirings  46   a ,  46   b.    
     The third copper wiring  21   a  is connected electrically to the first copper wiring  12   a  via the first via  20   a  and the cap layer  13 . Also, the fourth copper wiring  21   b  is connected electrically to the second copper wiring  12   b  via the second via  20   b  and the cap layer  13 . 
     After this, a second cap layer  49  made of the same material as the first cap layer  13  is formed on the third and fourth copper wirings  46   a ,  46   b  and the second stopper layer  43 . Then, like the first cap layer  13 , the second cap layer  49  is selectively etched to leave only on the third and fourth copper wirings  46   a ,  46   b.    
     In addition, the copper wiring having the multi-layered structure is formed on the second interlayer insulating film  8  by repeating the same formations of the interlayer insulating films, the copper wirings, and the vias as described above. 
     In the semiconductor device formed according to above steps, the ZrN cap layers  13 ,  45  left on the copper wirings  12   a ,  12   b ,  46   a ,  47   b  can prevent the oxidation of the copper wirings  12   a ,  12   b ,  46   a ,  47   b.    
     Also, since the ZrN cap layer formed on the third interlayer insulating film is removed, the limitation to the film thickness of the ZrN cap layer can be eliminated. Since the resistance value characteristic of the ZrN cap layer on the insulating film is changed abruptly around the film thickness of 20 nm, it is difficult to control the film thickness. However, if the selective etching of the ZrN cap layer according to the present embodiment is carried out, there is no possibility that the ZrN cap layer never acts as the low resistance layer on the insulating film. 
     The ZrN cap layer can be removed from the upper surface of the third interlayer insulating film by executing selectively the etching without the mask such as the resist, etc. with good precision. Therefore, the formation and the alignment of the resist patterns are not needed, and thus the throughput is never largely lowered. 
     (Fourth Embodiment) 
     In the third embodiment, the ZrN cap layer is removed selectively from the insulating cap layer. In this case, it is possible that, if the copper in the copper wiring reacts with ZrN in the cap layer, the copper is diffused into the interlayer insulating film through the cap layer. 
     For this reason, like the second embodiment, the copper diffusion from the copper wiring to the interlayer insulating film may be prevented surely by covering the ZrN layer left on the copper wirings with the insulating cap layer. The structure and the steps of forming the same will be explained hereunder. 
     First, in compliance with the steps shown in  FIGS. 6A to 6F , the MOS transistor  3  is formed on the silicon substrate  1 , then the interlayer insulating films  4 ,  8 ,  10 , then the first stopper layer is formed, the wiring  7  is formed, then the conductive plugs  5   a ,  5   b ,  9  are formed, and then the first and second copper wirings  12   a ,  12   b  are formed. Then, as shown in  FIG. 9A , the first cap layer  13  made of ZrN is formed on the first and second copper wirings  12   a ,  12   b  and the first stopper layer  40 . The film thickness of the first cap layer  13  is not limited to 20 nm or less, and the first cap layer  13  is formed to have a thickness of 40 nm, for example. 
     Then, as shown in  FIG. 10A , the first cap layer  13  is etched by the selective etching to remove from the upper surface of the third interlayer insulating film  10  and to leave on the first and second copper wirings  12   a ,  12   b . The selective etching of the first cap layer  13  is carried out by the method shown in the third embodiment. 
     Then, as shown in  FIG. 10B , the insulating second cap layer  41  having the copper diffusion preventing function is formed on the first cap layer  13 . As the second cap layer  41 , the insulating layer containing SiC, SiN as the base element or the insulating layer containing SiCO, SiON as the base element is formed by the PE-CVD method to have a thickness of 20 to 100 nm. The second cap layer  41  is formed in accordance with the method explained in the second embodiment. 
     Then, as shown in  FIG. 10C , the fourth interlayer insulating film  42  having a thickness of 600 nm and made of SiO 2  and the &#39;second stopper layer  43  of 50 nm thickness are formed sequentially on the second cap layer  41  by the CVD method. 
     Then, as shown in  FIG. 10D , the second stopper layer  43 , the fourth interlayer insulating film  42 , and the second cap layer  41  are patterned. Thus, the first and second via holes  41   a ,  41   b  to expose the first cap layer  13  are formed in the second stopper layer  43 , the fourth interlayer insulating film  42 , and the second cap layer  41 , and also the third and fourth wiring trenches  42   a ,  42   b  that overlap with the first and second via holes  41   a ,  41   b  respectively are formed in the second stopper layer  43  and the fourth interlayer insulating film  42 . 
     Next, steps required to form the structure shown in  FIG. 10E  will be explained hereunder. 
     Like the second embodiment, the barrier metal layer  44   a  is formed on the inner peripheral surfaces and the bottom surfaces of the first and second via holes  41   a ,  41   b  and the third and fourth wiring trenches  42   a ,  42   b  and on the upper surface of the second stopper layer  43  respectively. The barrier metal layer  44   a  is formed by the sputter method and is made of any one of Ta, TaN, and their laminated film or TiN, for example. 
     Then, the copper seed layer (not shown) of 30 to 100 nm thickness is formed on the barrier metal layer  44   a  by the sputter method. 
     In addition, the copper layer  44   b  is formed on the copper seed layer by the electrolytic plating method, whereby the third and fourth wiring trenches  42   a ,  42   b  and the first and second via holes  41   a ,  41   b  are completely buried. In this case, the copper seed layer is formed integrally with the copper layer  44   b.    
     Then, the copper layer  44   b  and the barrier metal layer  44   a  are removed from the upper surface of the second stopper layer  43  by the CMP method while using the second stopper layer  43  as the polishing stopper. As a result, the copper layer  44   b  and the barrier metal layer  44   a  left in the first and second via holes  41   a ,  41   b  respectively are used as the first and second vias  45   a ,  45   b , and also the copper layer  44   b  and the barrier metal layer  44   a  left in the third and fourth wiring trenches  42   a ,  42   b  respectively are used as the third and fourth copper wirings  46   a ,  46   b.    
     The third copper wiring  21   a  is connected electrically to the first copper wiring  12   a  via the first via  20   a  and the first cap layer  13 . Also, the fourth copper wiring  21   b  is connected electrically to the second copper wiring  12   b  via the second via  20   b  and the first cap layer  13 . 
     Then, the third cap layer  47  made of ZrN is formed on the third and fourth copper wirings  46   a ,  46   b  and the second stopper layer  43 . In addition, the third cap layer  47  is selectively etched to leave only on the third and fourth copper wirings  46   a ,  46   b.    
     Then, the fourth cap layer  48  made of the same material as the second cap layer  41  is left on the third cap layer  47  and the second stopper layer  43 . 
     Then, as described above, the copper wiring having the multi-layered structure is formed on the second interlayer insulating film  8  by repeating the formations of the interlayer insulating films, the copper wirings, and the vias. 
     In the semiconductor device formed according to above steps, the ZrN cap layers  13 ,  47  left only on the copper wirings  12   a ,  12   b ,  46   a ,  46   b  are covered with another cap layers  40 ,  48  made of the copper diffusion preventing insulating material. Therefore, it can be prevented that the copper is diffused from the copper wirings  12   a ,  12   b ,  46   a ,  46   b  to the interlayer insulating film via the ZrN cap layers  13 ,  47 . In addition, since the ZrN cap layers  13 ,  47  are removed selectively from the upper surface of the interlayer insulating film, the copper wirings are never short-circuited even if the film thickness is thicker than 20 nm. 
     (Other Embodiment) 
     In the above embodiments, the interlayer insulating film is formed of SiO 2 . But the interlayer insulating film may be formed of the low-dielectric constant insulating material. Since the influence of the wiring delay becomes aggravated with the miniaturization of the element, the application of the low-dielectric constant insulating material becomes important much more. As the low-dielectric constant insulating material, the organic polymer, the silicon oxide that is impregnated with the carbon, or the porous low-dielectric constant insulating material can be listed as the typical material. 
     As the method of forming the low-dielectric constant insulating material, the spin-on process of coating uniformly the liquid low-dielectric constant insulating material onto the substrate while rotating the substrate or the PE-CVD method is the representative method. If the porous low-dielectric constant insulating film is formed by the coating process, a hollow body is formed by executing the thermolysis of unstable components and the formation of the mold intermediate structure and the thermolysis of the mold by employing the hydrolysis and the condensation polymerization by virtue of the sol-gel method, and thus the annealing process at about 400° C. is needed. 
     Also, in the above embodiments, as the pre-step of burying the copper in the wiring trenches and the via holes, the barrier metal layer and the copper seed layer are formed by the sputter. But these layers may be formed by the CVD method. For example, if the titanium nitride is formed as the barrier metal by the CVD method, TDEAT and the ammonia are used as the reaction gas. In addition, the copper seed layer may be formed by the CVD method. As the growth gas for the copper seed layer, Cu(hfac)TMVS is employed as the material, for example. 
     As the method of forming the copper seed layer, the self ionizing plasma method which can give the good coverage to fine via holes, etc. may be employed. 
     In the above embodiments, the dual damascene method having the step of burying simultaneously the barrier metal and the copper in the via holes and the wiring trenches is explained. However, the formation of the via and the copper wiring is not limited to the dual damascene method. The damascene method by which the barrier metal and the copper are buried in the via holes, then the wiring trenches are formed, and then the barrier metal and the copper are buried again in the wiring trenches may be employed. In this case, the cap layer made of the zirconium, the titanium, the hafnium, the zirconium nitride, or any one of their compounds may also be formed on the copper vias and the copper wirings. 
     As described above, according to the present invention, the first cap layer made of the substance, the portion of which formed on the copper film has the smaller electrical resistance value than the portion formed on the insulating film, is formed on the first insulating film and the first metal pattern. Therefore, if the holes or the trenches are formed on the first metal pattern by patterning the second insulating film formed on the first insulating film, the first metal pattern can be protected by the first cap layer and thus the oxidation, the corrosion, and the contamination of the first metal pattern can be prevented. In addition, since the second metal pattern buried in the holes and the trenches is connected electrically to the first metal pattern through the first cap layer, the electrical conduction between the second metal pattern and first metal pattern can be assured. 
     Also, since the first cap layer acts as the insulating portion on the first insulating film, the patterning of the first cap layer can be omitted, which can contribute the reduction of the steps. In this case, since the first cap layer made of the zirconium nitride, or the like can be formed while changing the film density on the first insulating film and on the first metal pattern, such first cap layer can be removed selectively from the upper surface of the insulating film by the selective etching without the mask. As a result, the patterning step can be simplified. 
     In addition, the second cap layer made of the copper diffusion preventing insulating material is formed on the cap layer. Therefore, even if the first metal pattern contains the copper, the copper diffusion from the first metal pattern to the interlayer insulating film can be prevented without fail.