Patent Publication Number: US-9904343-B2

Title: System on chip circuits and related systems and methods of operating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. § 119(a) from Korean Patent Application No. 10-2013-0150175, filed Dec. 4, 2013, the disclosure of which is hereby incorporated herein by reference in its entirety. 
     BACKGROUND 
     Embodiments of the inventive concept relate to a system on chip (SoC), and more particularly, to a SoC for measuring and calculating power of at least one non-core power domain in analog mode and measuring and calculating power of at least one core power domain in digital mode. 
     As portable devices, such as smart phones and tablet personal computers (PCs) have recently come into wide use and the number of applications available in these devices has increased, approaches for controlling power consumed in the portable devices become important. It may be desirable to accurately measure total power consumed in a portable device. 
     SUMMARY 
     Some embodiments of the present inventive concept provide a system on chip (SoC) for calculating a total power in hybrid mode, i.e., using both analog and digital modes. 
     Further embodiments of the present inventive concept provide methods of operating a system on chip including a first power domain and a second power domain. The method includes measuring at least one of a voltage and a current, which are applied to the first power domain in analog mode to obtain a measurement result; calculating a first power consumed in the first power domain based on the measurement result; calculating a second power consumed in the second power domain in digital mode based on an activity of the second power domain; and controlling a total power of the system on chip based on the first power and the second power. At least one of the measuring, calculating a first power, calculating a second power and controlling are performed by at least one processor. 
     In still further embodiments, the first power domain may be a non-core power domain and the second power domain may be a core power domain including a processor. 
     In some embodiments, calculating the first power may include measuring a voltage difference corresponding to a voltage drop of a power switch connected to a power line of the first power domain; and calculating the first power based on the voltage difference, a resistance of the power switch, and a power supply voltage applied to the first power domain. 
     In further embodiments, calculating the first power may include measuring a total current supplied to the first power domain based on a current flowing in a power switch connected to a power line of the first power domain; and calculating the first power based on the measured total current and a power supply voltage applied to the first power domain. 
     In still further embodiments, calculating the first power may include converting the measurement result into a digital signal; and calculating the first power based on the digital signal and condition data related to the first power domain. 
     In some embodiments, calculating the second power may include calculating the second power based on parameters related to the activity, a weight of each of the parameters, and environmental conditions of the second power domain. 
     Further embodiments of the present inventive concept provide a system on chip (SoC) including a first power domain and a second power domain, The system on chip including a power monitoring circuit to measure at least one of a voltage and a current to provide a measurement result, the voltage or the current being applied to the first power domain in analog mode and to generate a digital signal based on the measurement result; a performance monitoring unit to monitor an activity of the second power domain; and a power calculation module to calculate a first power consumed in the first power domain based on the digital signal and calculate a second power consumed in the second power domain in digital mode based on the monitored activity. 
     In still further embodiments, the first power domain may be a non-core domain and the second power domain may be a core domain. 
     In some embodiments, the power calculation module may calculate the second power based on parameters related to the monitored activity, a weight of each of the parameters, and environmental conditions of the second power domain. 
     In further embodiments, a power management unit may control a total power of the system on chip based on the first power and the second power. 
     In still further embodiments, the first power domain may include a first peripheral circuit (PC 1 ). The power monitoring circuit may include a controller; a first sensing circuit to sense at least one of a current and a voltage, the current and/or the voltage being applied to a power switch connected to a power line provided for the first peripheral circuit, and to output a first sensed signal based on a sensing result; and an analog-to-digital converter to convert the first sensed signal into the digital signal according to control of the controller. 
     In some embodiments, the first power domain may include a second peripheral circuit (PC 2 ). The power monitoring circuit may further include a second sensing circuit to sense at least one of a current and a voltage, the current and/or the voltage being applied to a power switch connected to a power line provided for the second peripheral circuit, and to output a second sensed signal based on a sensing result; and a selector to select and output one of the first sensed signal and the second sensed signal according to the control of the controller, and the analog-to-digital converter to convert an output signal of the selector into the digital signal according to the control of the controller. 
     In further embodiments, a power management integrated circuit may control a total power of the system on chip based on the first power and the second power. 
     In still further embodiments, the first power domain may include a first peripheral circuit. The power monitoring circuit may include a controller; a first sensing circuit configured to sense at least one of a current and a voltage, the current and/or the voltage being applied to a power switch connected to a power line provided for the first peripheral circuit, and to output a first sensed signal based on a sensing result; and an analog-to-digital converter configured to convert the first sensed signal into the digital signal according to control of the controller. 
     In some embodiments, the first power domain may further include a second peripheral circuit. The power monitoring circuit may include a second sensing circuit to sense at least one of a current and a voltage, the voltage and/or the current being applied to a power switch connected to a power line provided for the second peripheral circuit, and to output a second sensed signal based on a sensing result; and a selector to select and output one of the first sensed signal and the second sensed signal according to the control of the controller, and the analog-to-digital converter to convert an output signal of the selector into the digital signal according to the control of the controller. 
     Further embodiments of the present inventive concept provide methods of operating a system on chip (SoC) including measuring a power consumed in a non-core power domain in a analog mode; measuring a power of a core power domain including a core processor in a digital mode; and calculating a total power based on the power consumed in a non-core power domain and the core power domain. 
     In still further embodiments, the method may further include controlling the total power and a total temperature of the SoC based on the power consumed in the non-core power domain and the core power domain. 
     In some embodiments, measuring power consumed in a non-core power domain may include measuring a voltage difference corresponding to a voltage drop of a power switch connected to a power line of the non-core power domain; and calculating the power consumed in the non-core power domain based on the voltage difference, a resistance of the power switch, and a power supply voltage applied to the non-core power domain. 
     In further embodiments, measuring the power of a core power domain may include calculating the power of the core power domain based on parameters related to an activity of the non-core power domain, a weight of each of the parameters, and environmental conditions of the core power domain. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
         FIG. 1  is a block diagram of a system on chip (SoC) according to some embodiments of the inventive concept. 
         FIG. 2  is a block diagram illustrating operations of a power monitoring circuit illustrated in  FIG. 1 . 
         FIG. 3  is a block diagram illustrating an example of a first sensing circuit illustrated in  FIG. 2 . 
         FIG. 4  is a block diagram illustrating another example of a first sensing circuit illustrated in  FIG. 2 . 
         FIG. 5  is a block diagram of a power calculation module illustrated in  FIG. 1 . 
         FIG. 6  is a block diagram of a SoC according to some embodiments of the inventive concept. 
         FIG. 7  is a block diagram for explaining the operation of a power monitoring circuit illustrated in  FIG. 6 . 
         FIG. 8  is a block diagram of a SoC according to some embodiments of the inventive concept. 
         FIG. 9  is a flowchart of illustrating a method of operating the SoC illustrated in  FIG. 1, 6 , or  8  according to some embodiments of the inventive concept. 
         FIG. 10  is a block diagram of an electronic system according to some embodiments of the inventive concept. 
         FIG. 11  is a block diagram of an electronic system according to some embodiments of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The inventive concept now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the inventive concept are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. 
     It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the teachings of the disclosure. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  is a block diagram of a system on chip (SoC)  10 A according to some embodiments of the inventive concept. The SoC  10 A may be implemented as a printed circuit board (PCB) such as a motherboard, an integrated circuit (IC), a processor, a multimedia processor, or an integrated multimedia processor. The SoC  10 A may also be an application processor. 
     The SoC  10 A may be divided into a plurality of power domains PWD 1  through PWD 4 . The SoC  10 A may measure at least one between voltage and current, which are provided to the first power domain PWD 1 , in analog mode and may calculate a first power PW 1  consumed in the first power domain PWD 1  based on the measurement result. 
     The SoC  10 A may calculate a second power PW 2  consumed in the second power domain PWD 2  based on the activity of the second power domain PWD 2 . In addition, the SoC  10 A may control the total power of the SoC  10 A based on the first power PW 1  and the second power PW 2 . The SoC  10 A may include a central processing unit (CPU)  100 , a first temperature sensor  107 , a first peripheral circuit  110 , a power monitoring circuit  130 A, a power calculation module  150 , and a power management unit  170 . 
     As used herein, the term “module” may indicate hardware that can perform functions and operations in accordance with the following descriptions, computer program codes for executing particular functions and operations, or an electronic recording medium, for example, a processor equipped with the computer program codes. In other words, the “module” may indicate the functional and/or structural combination of hardware for realizing the inventive concept and/or software for driving the hardware. Each module may be referred to as a device or circuit without departing from the scope of the present inventive concept. 
     The first power domain PWD 1  may include the first peripheral circuit  110 . The second power domain PWD 2  may include the CPU  100  and the first temperature sensor  107 . The third power domain PWD 3  may include the power monitoring circuit  130 A and the power calculation module  150 . The fourth power domain PWD 4  may include the power management unit  170 . Although the power monitoring circuit  130 A and the power calculation module  150  are defined to belong to the same power domain in the embodiments illustrated in  FIG. 1 , they may be defined to belong to different power domains from each other in other embodiments. The power domains PWD 1  through PWD 4  may be defined depending on the function and/or power measuring method of each of the elements  100 ,  110 ,  130 A,  150 , and  170 . 
     The CPU  100  may control the overall operation of the SoC  10 A. For example, the CPU  100  may control the operation of each of the elements  110 ,  130 A,  150 , and  170  through a bus  105 . The CPU  100  may be implemented as a multi-core. The multi-core may be a single computing component with two or more independent cores. 
     The CPU  100  may include a first performance monitoring unit  100 - 1 . The first performance monitoring unit  100 - 1  may monitor the activity of the second power domain PWD 2 , for example, the CPU  100 . For example, the first performance monitoring unit  100 - 1  may monitor parameters related to the activity of the CPU  100  and may transmit first monitoring data M_DATA 1  obtained by monitoring the parameters to the power calculation module  150 . The parameters may include an activity clock cycle, an integer/floating instruction counter, a load/store instruction counter, an L1/L2 cache access counter, a translation lookaside buffer (TLB) access counter, and a data cache access counter. Although the first performance monitoring unit  100 - 1  is implemented within the CPU  100  in the embodiments illustrated in  FIG. 1 , it may be implemented outside the CPU  100  in other embodiments. 
     The first temperature sensor  107  may sense heat generated in the second power domain PWD 2 , for example, the CPU  100  and measure temperature of the CPU  100 . The first temperature sensor  107  may be a thermal sensor. The first temperature sensor  107  may output first temperature information TI 1  about the measured temperature to the power calculation module  150 . 
     In these embodiments, a peripheral circuit may be a function block except for core processors, for example, the CPU  100  and/or a graphics processing unit (GPU) used in the SoC  100 . For example, the function block may be memory, universal serial bus (USB), peripheral component interconnect (PCI), digital signal processor (DSP), wired interface, wireless interface, controller, embedded software, codec, video module (for example, camera interface, Joint Photographic Experts Group (JPEG) processor, or video processor) or mixer, audio system, or driver. In other words, the second power domain PWD 2  may be a core power domain including a processor (or a core processor), such as the CPU  100  and the other domains PWD 1 , PWD 3 , and PWD 4  may be non-core power domains. 
     The power monitoring circuit  130 A may measure at least one between voltage and current, provided to the first power domain PWD 1 , in analog mode; generate a digital signal DS based on the measurement result; and transmit the digital signal DS to the power calculation module  150 . Regardless of what function block the first peripheral circuit  110  included in the first power domain PWD 1  is implemented as, the power monitoring circuit  130 A may directly measure data (or information), which is used by the power calculation module  150  to calculate the first power PW 1 , from the first power domain PWD 1  using the analog mode. The structure and operation of the power monitoring circuit  130 A will be discussed with reference to  FIGS. 2 through 4  below. 
     The power calculation module  150  may calculate the first power PW 1  consumed in the first power domain PWD 1  based on the digital signal DS. The power calculation module  150  may also calculate the second power PW 2  consumed in the second power domain PWD 2  in digital mode based on the first monitoring data M_DATA 1  and the first temperature information TI 1 . 
     For example, the power calculation module  150  may calculate the second power PW 2  based on parameters (for example, the first monitoring data M_DATA 1 ), weighted coefficient of each of the parameters, and environmental conditions (for example, the first temperature information TI 1 , frequency applied to the CPU  100 , and/or voltage applied to the CPU  100 ) of the second power domain PWD 2 . 
     The power calculation module  150  calculates both the first power PW 1  of the non-core power domain PWD 1  including at least one first peripheral circuit  110 , which performs a main function and/or operation of the SoC  10 A, and the second power PW 2  of the core power domain PWD 2  including a process, for example, the CPU  100 , thereby efficiently determining the total power of the SoC  10 A. The power calculation module  150  may transmit the first power PW 1  and the second power PW 2  to the power management unit  170 . According to some embodiments, the power calculation module  150  may operate according to the control of the CPU  100 . The structure and operation of the power calculation module  150  will be discussed with reference to  FIG. 5  below. 
     The power management unit  170  may control the total power of the SoC  10 A based on the first power PW 1  and the second power PW 2 . For example, the power management unit  170  may control the power state of each of the power domains PWD 1  and PWD 2 . The power state may be a power-up (or power-on) state or a power-down (or power-off) state. The power-up state may indicate a state in which the power or voltage of the power domain PWD 1  or PWD 2  is fully powered up. The power-down state may indicate a state in which the power domain PWD 1  or PWD 2  is powered-off or is in a low-power mode. The power management unit  170  may also control temperature of the SoC  10 A based on the first power PW 1  and the second power PW 2 . The temperature may be controlled using a thermal throttling method according to some embodiments. Since the total power of the SoC  10 A is accurately calculated using a hybrid method, the power management unit  170  efficiently controls the total power and/or temperature of the SoC  10 A. 
       FIG. 2  is a block diagram illustrating operations of the power monitoring circuit  130 A illustrated in  FIG. 1 . Referring to  FIGS. 1 and 2 , the first power domain PWD 1  may also include power lines PL for application of a power supply voltage VDD to the first peripheral circuit  110 . Each of the power lines PL may be connected to a power switch SW in the first power domain PWD 1 . The power switch SW may be implemented as a P-channel metal oxide semiconductor (PMOS) transistor or an N-channel MOS (NMOS) transistor. 
     The power monitoring circuit  130 A may include a controller  131 , a first sensing circuit  133 , and an analog-to-digital converter (ADC)  135 . 
     The controller  131  may control the overall operation of the power monitoring circuit  130 A. For example, the controller  131  may control the operation of each of the elements  133  and  135 . The controller  131  may generate a control signal CTRL and output the control signal CTRL to the ADC  135 . 
     The first sensing circuit  133  may measure at least one between voltage and current, which are provided to the power switch SW connected to each of the power lines PL, and may output a first sensed signal SS 1  based on the measurement result. In other words, the first sensing circuit  133  may be directly connected to each power line PL and may measure at least one between voltage and current provided to the power switch SW in analog mode. 
       FIG. 3  is a block diagram illustrating an example  133 A of the first sensing circuit  133  illustrated in  FIG. 2 . Referring to  FIG. 3 , the first sensing circuit  133 A may measure a voltage difference Vdiff corresponding to voltage drop of the power switch SW connected to each of the power lines PL in the first power domain PWD 1 . 
     The first sensing circuit  133 A may include a voltage equalization circuit  133 - 1 , a voltage amplifier circuit  133 - 3 , and a voltage comparator  133 - 5 . The first sensing circuit  133 A illustrated in  FIG. 3  illustrates an embodiment of the first sensing circuit  133  illustrated in  FIG. 2 . 
     The voltage equalization circuit  133 - 1  may measure voltages V 1 - 1  through V 1 -N and V 2 - 1  through V 2 -N applied to the power switches SW respectively connected to the power lines PL and generate equalized voltage EV 1  and EV 2  based on the measurement result. For example, the voltage equalization circuit  133 - 1  may measure the voltages V 1 - 1  through V 1 -N applied to first ends ND 1  of the respective power switches SW respectively connected to the power lines PL and may generate the first equalized voltage EV 1  by equalizing the voltages V 1 - 1  through V 1 -N. The voltage equalization circuit  133 - 1  may also measure the voltages V 2 - 1  through V 2 -N applied to second ends ND 2  of the respective power switches SW respectively connected to the power lines PL and may generate the second equalized voltage EV 2  by equalizing the voltages V 2 - 1  through V 2 -N. The voltage equalization circuit  133 - 1  may output the first equalized voltage EV 1  and the second equalized voltage EV 2  to the voltage amplifier circuit  133 - 3 . 
     The voltage amplifier circuit  133 - 3  may amplify the first equalized voltage EV 1  and the second equalized voltage EV 2 , thereby generating amplified voltages AEV 1  and AEV 2 . For example, the voltage amplifier circuit  133 - 3  may generate the first amplified voltage AEV 1  by amplifying the first equalized voltage EV 1  and may generate the second amplified voltage AEV 2  by amplifying the second equalized voltage EV 2 . The voltage amplifier circuit  133 - 3  may output the first amplified voltage AEV 1  and the second amplified voltage AEV 2  to the voltage comparator  133 - 5 . 
     The voltage comparator  133 - 5  may compare the first amplified voltage AEV 1  with the second amplified voltage AEV 2  and may generate the voltage difference Vdiff corresponding to the voltage drop of the power switches SW according to the comparison result. The voltage comparator  133 - 5  may output the voltage difference Vdiff to the ADC  135  as the first sensed signal SS 1 . 
     A resistance Rswitch illustrated in  FIG. 3  may be a total parallel resistance looking at the power switch SW of each power line PL connected to the first peripheral circuit  110 . 
       FIG. 4  is a block diagram for explaining another example  133 B of the first sensing circuit  133  illustrated in  FIG. 2 . Referring to  FIG. 4 , the first sensing circuit  133 B may measure a total current I supplied to the first power domain PWD 1 , for example, the first peripheral circuit  110 , based on currents I 1  through IN (where N is a natural number of at least 1) supplied to the power switch SW connected to each of the power lines PL in the first power domain PWD 1 . 
     The first sensing circuit  133 B may include a current collection circuit  133 - 7 , a current replication circuit  133 - 8 , and a resistance circuit  133 - 9 . The first sensing circuit  133 B illustrated in  FIG. 4  illustrates some embodiments of the first sensing circuit  133  illustrated in  FIG. 2 . 
     The current collection circuit  133 - 7  may collect the currents I 1  through IN supplied to the respective power switches SW respectively connected to the power lines PL and may generate the total current I by adding the collected currents I 1  through IN. The current collection circuit  133 - 7  may output the total current I to the current replication circuit  133 - 8 . 
     The current replication circuit  133 - 8  may generate a replica current Irep with respect to the total current I using current mirroring. The replica current Irep may be defined as Equation 1: 
                     Irep   =       1   M     ×   I       ,           (   1   )               
where M may be a scale down constant of at least 1. The current replication circuit  133 - 8  may output the replica current Irep to the resistance circuit  133 - 9 .
 
     The resistance circuit  133 - 9  may include an input node IN, an output node OUT, and a resistor R. The replica current Irep may be input to the input node IN of the resistance circuit  133 - 9  and flow across the resistor R, thereby causing voltage drop. Due to the voltage drop, an output voltage Vsense may be put across the output node OUT of the resistance circuit  133 - 9 . The output voltage Vsense may be defined as Equation 2:
 
 V sense=VDD− I rep×Rv,  (2)
 
where Rv may be a resistance of the resistor R. The resistance circuit  133 - 9  may output the output voltage Vsense to the ADC  135  as the first sensed signal SS 1 .
 
     Since the total current I actually supplied to the first peripheral circuit  110  is significantly large, it is hard to directly measure the total current I. Therefore, the total current I may be measured based on the replica current Irep obtained by scaling down the total current I using the current replication circuit  133 - 8 . Referring to  FIGS. 1 through 4 , the ADC  135  may convert the first sensed signal SS 1  into the digital signal DS according to the control of the controller  131 , i.e., in response to the control signal CTRL. The ADC  135  may output the digital signal DS to the power calculation module  150 . 
       FIG. 5  is a block diagram of the power calculation module  150  illustrated in  FIG. 1 . Referring to  FIGS. 1 through 5 , the power calculation module  150  may include a register  151  and calculation logic  153 . 
     The register  151  may store first condition data C_DATA 1  used to calculate the first power PW 1  consumed in the first power domain PWD 1 . The first condition data C_DATA 1  may be data related to the first power domain PWD 1 . For example, the first condition data C_DATA 1  may include the total parallel resistance Rswitch, the scale down constant M, the resistance Rv of the resistor R of the resistance circuit  133 - 9 , and/or data about the power supply voltage VDD. 
     The register  151  may store second condition data C_DATA 2  used to calculate the second power PW 2  consumed in the second power domain PWD 2 . The second condition data C_DATA 2  may be data related to the second power domain PWD 2 , for example, the CPU  100 . For example, the second condition data C_DATA 2  may include data about a weight of each of parameters related to the activity of the second power domain PWD 2 , for example, the CPU  100 ; data about a weight of the measured temperature of the CPU  100 , and data about environmental conditions (for example, frequency and/or voltage applied to the CPU  100 ) of the second power domain PWD 2 . The first condition data C_DATA 1  and the second condition data C_DATA 2  may be set in the register  151  according to the control of the CPU  100  according to some embodiments. 
     The calculation logic  153  may calculate the first power PW 1  consumed in the first power domain PWD 1  based on the digital signal DS. For example, the calculation logic  153  may calculate the first power PW 1  consumed in the first power domain PWD 1  using the digital signal DS and the first condition data C_DATA 1 . 
     When the power monitoring circuit  130 A measures the voltages V 1 - 1  through V 1 -N and V 2 - 1  through V 2 -N applied to the ends ND 1  and ND 2  of the power switches SW of the respective power lines PL included in the first power domain PWD 1  in analog mode, the first power PW 1  consumed in the first power domain PWD 1  may be calculated using Equation 3:
 
PW1= V diff× R switch×VDD.  (3)
 
     When the power monitoring circuit  130 A measures the currents I 1  through IN applied to the ends ND 1  and ND 2  of the power switches SW of the respective power lines PL included in the first power domain PWD 1  in analog mode, the first power PW 1  consumed in the first power domain PWD 1  may be calculated using Equation 4:
 
PW1= I ×VDD.  (4)
 
     The total current I may be calculated using Equations 1 and 2. 
     The calculation logic  153  may calculate the second power PW 2  consumed in the second power domain PWD 2  using monitoring data M_DATA, the temperature information TI, and the second condition data C_DATA 2 . The second power PW 2  may be calculated using Equation 5:
 
PW2= A 1× P 1+ . . . + AK×PK+b ×exp( c×T ).  (5)
 
     Terms relevant to the parameters A 1  through AK (where K is a natural number greater than 1) related to the activity of the second power domain PWD 2 , for example, the CPU  100  and terms relevant to the weights P 1  through PK of the respective parameters A 1  through AK may be related with dynamic power. Terms relevant to the measured temperature T and the weights “b” and “c” of the measured temperature T may be related with leakage current. 
     The calculation logic  153  may calculate the dynamic power of the second power domain PWD 2  using the monitoring data M_DATA and the second condition data C_DATA 2 . The calculation logic  153  may also calculate the leakage current of the second power domain PWD 2  using the temperature information TI and the second condition data C_DATA 2 . The calculation logic  153  may calculate the second power PW 2  consumed in the second power domain PWD 2  by adding the dynamic power and the leakage power. The calculation logic  153  may output the first power PW 1  and the second power PW 2  to the power management unit  170 . 
       FIG. 6  is a block diagram of a SoC  10 B according to other embodiments of the inventive concept. The SoC  10 B may include the CPU  100 , the first temperature sensor  107 , the first peripheral circuit  110 , a second peripheral circuit  115 , a power monitoring circuit  130 B, the power calculation module  150 , and the power management unit  170 . Apart from the structure and operations of the second peripheral circuit  115  and the power monitoring circuit  130 B, the structure and operations of the SoC  10 B illustrated in  FIG. 6  may be substantially the same as those of the SoC  10 A illustrated in  FIG. 1 . 
     The first power domain PWD 1  may include the first peripheral circuit  110  and the second peripheral circuit  115 . In other embodiments, different power domains may be defined for the first peripheral circuit  110  and the second peripheral circuit  115 , respectively. 
     The second peripheral circuit  115  may be a function block except for core processors, for example, the CPU  100  and/or a GPU used in the SoC  10 B. The power monitoring circuit  130 B may measure at least one between voltage and current, provided to the first power domain PWD 1 , in analog mode; generate the digital signal DS based on the measurement result; and transmit the digital signal DS to the power calculation module  150 . 
       FIG. 7  is a block diagram for explaining the operation of the power monitoring circuit  130 B illustrated in  FIG. 6 . Referring to  FIGS. 6 and 7 , the first power domain PWD 1  may also include power lines PL for application of the power supply voltage VDD to the second peripheral circuit  115 . Each of the power lines PL for applying the power supply voltage VDD to the second peripheral circuit  115  may be connected to a power switch SW. According to some embodiments, the power switch SW for the second peripheral circuit  115  may be implemented as a PMOS transistor or an NMOS transistor. The power monitoring circuit  130 B may include the controller  131 , the first sensing circuit  133 , a second sensing circuit  134 , the ADC  135 , and a selector  137 . 
     The controller  131  may control the overall operation of the power monitoring circuit  130 B. For example, the controller  131  may control the operation of each of the elements  133 ,  134 ,  135 , and  137 . The controller  131  may generate a control signal CTRL and output the control signal CTRL to the ADC  135 . The controller  131  may generate a selection signal SEL and output the selection signal SEL to the selector  137 . 
     The first sensing circuit  133  may measure at least one between voltage and current, which are provided to the power switch SW connected to each of the power lines PL provided for the first peripheral circuit  110 , and may output the first sensed signal SS 1  to the ADC  135  based on the measurement result. The second sensing circuit  134  may measure at least one between voltage and current, which are provided to the power switch SW connected to each of the power lines PL provided for the second peripheral circuit  115 , and may output a second sensed signal SS 2  to the ADC  135  based on the measurement result. The structure and operations of the second sensing circuit  134  may be substantially the same as those of the first sensing circuit  133 . For example, the second sensing circuit  134  may be implemented as the sensing circuit  133 A or  133 B illustrated in  FIG. 3 or 4 . 
     The selector  137  may output the first sensed signal SS 1  or the second sensed signal SS 2  to the ADC  135  according to the control of the controller  131 , . . . , in response to the selection signal SEL. When the selection signal SEL is at a first level, for example, logic 0 or logic low, the selector  137  may output the first sensed signal SS 1  received from the first sensing circuit  133  to the ADC  135 . When the selection signal SEL is at a second level, for example, logic 1 or logic high, the selector  137  may output the second sensed signal SS 2  received from the second sensing circuit  134  to the ADC  135 . In other words, the selector  137  may sequentially select and output the first sensed signal SS 1  and the second sensed signal SS 2  according to the control of the controller  131 . The selector  137  may be implemented as a multiplexer. 
     When the selector  137  is implemented in the power monitoring circuit  130 B, it is not necessary to provide the controller  131  and/or the ADC  135  for each of the peripheral circuits  110  and  115 , so that an area occupied by the power monitoring circuit  130 B in the SoC  10 B is reduced. 
     The ADC  135  may convert the output signal SS 1  or SS 2  of the selector  137  into the digital signal DS according to the control of the controller  131 , i.e., in response to the control signal CTRL and may output the digital signal DS to the power calculation module  150 . For example, according to the control of the controller  131  the ADC  135  may convert the first sensed signal SS 1  into the digital signal DS and output the first sensed signal SS 1  to the power calculation module  150  and then the ADC  135  may convert the second sensed signal SS 2  into the digital signal DS and output the second sensed signal SS 2  to the power calculation module  150 . 
     The power calculation module  150  may calculate the first power PW 1  consumed in the first power domain PWD 1  based on the digital signal DS. For example, the power calculation module  150  may calculate a power consumed in the first peripheral circuit  110  and a power consumed in the second peripheral circuit  115  based on the digital signals DS sequentially received and may add the calculated powers to calculate the first power PW 1  consumed in the first power domain PWD 1 . 
       FIG. 8  is a block diagram of a SoC  10 C according to some embodiments of the inventive concept. The SoC  10 C may include the CPU  100 , the first temperature sensor  107 , the first peripheral circuit  110 , the power monitoring circuit  130 A or  130 B (generically denoted by  130 ), the power calculation module  150 , the power management unit  170 , a GPU  190 , and a second temperature sensor  197 . The SoC  10 C may also include the second peripheral circuit  115 . Apart from the structure and operations of the GPU  190 , the structure and operations of the SoC  10 C illustrated in  FIG. 8  may be substantially the same as those of the SoC  10 A illustrated in  FIG. 1  or the SoC  10 B illustrated in  FIG. 6 . The SoC  10 C may be divided into a plurality of power domains PWD 1  through PWD 5 . 
     The power domains PWD 1  through PWD 5  may be defined depending on the function and/or power measuring method of each of the elements  100 ,  110 ,  130 ,  150 ,  170 , and  190 . The fifth power domain PWD 5  may include the GPU  190  and the second temperature sensor  197 . The GPU  190  may perform operations related to graphics processing. The GPU  190  may include a second performance monitoring unit  190 - 1 . 
     The second performance monitoring unit  190 - 1  may monitor the activity of the fifth power domain PWD 5 , for example, the GPU  190 . For example, the second performance monitoring unit  190 - 1  may monitor parameters related to the activity of the GPU  190  and may transmit second monitoring data M_DATA 2  obtained by monitoring the parameters to the power calculation module  150 . Although the second performance monitoring unit  190 - 1  is implemented within the GPU  190  in the embodiments illustrated in  FIG. 8 , it may be implemented outside the GPU  190  in other embodiments. 
     The second temperature sensor  197  may sense heat generated in the fifth power domain PWD 5 , for example, the GPU  190  and measure a temperature of the GPU  190 . The second temperature sensor  197  may be a thermal sensor. The second temperature sensor  197  may output second temperature information TI 2  about the measured temperature of the GPU  190  to the power calculation module  150 . 
     The power calculation module  150  may digitally calculate a third power PW 3  consumed in the fifth power domain PWD 5  based on the second monitoring data M_DATA 2  and the second temperature information TI 2 . For example, the power calculation module  150  may calculate the third power PW 3  based on the parameters (for example, the second monitoring data M_DATA 2 ) related to the activity of the GPU  190 , a weight of each of the parameters, and environmental conditions (for example, the second temperature information TI 2 , frequency applied to the GPU  190 , and/or voltage applied to the GPU  190 ) of the fifth power domain PWD 5 . 
     A method of calculating the third power PW 3  in digital mode may be the same as that discussed above with reference to  FIG. 5 . At this time, the register  151  of the power calculation module  150  may store third condition data used to calculate the third power PW 3 . The third condition data may be data related to the fifth power domain PWD 5 . For example, the third condition data may include data about a weight of each of the parameters related to the activity of the fifth power domain PWD 5 , for example, the GPU  190 , data about a weight of the measured temperature of the GPU  190 , and data about the environmental conditions (for example, frequency and/or voltage applied to the GPU  190 ) of the fifth power domain PWD 5 . 
       FIG. 9  is a flowchart illustrating operations of the SoC  10 A,  10 B, or  10 C (generically denoted by  10 ) illustrated in  FIG. 1, 6 , or  8  according to some embodiments of the inventive concept. Referring to  FIG. 9 , the SoC  10  may include a plurality of the power domains PWD 1 , PWD 2 , PWD 3 , PWD 4 , and/or PWD 5 . 
     The SoC  10  may measure at least one between voltage and current provided to at least one non-core power domain PWD 1  in analog mode and calculate the power PW 1  consumed in the least one non-core power domain PWD 1  based on the measurement result in operation S 110 . The SoC  10  may calculate at least one power PW 2  and/or PW 3  consumed in at least one core power domain PWD 2  and/or PWD 5  based on the activity of the at least one core power domain PWD 2  and/or PWD 5  in digital mode in operation S 130 . The SoC  10  may control its total power based on the calculated powers PW 1  and PW 2  and/or PW 3  in operation S 150 . 
       FIG. 10  is a block diagram of an electronic system  200 ,  300 , or  400  according to some embodiments of the inventive concept. Referring to  FIG. 10 , the electronic system  200 ,  300 , or  400  may be implemented as a personal computer (PC), a data server, or a portable electronic device. The portable electronic device  300  may be implemented as a laptop computer, a mobile telephone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, or an e-book. 
     The electronic system  200 ,  300 , or  400  may include the processor  10 , a power source  210 , a storage device  220 , a memory  230 , input/output (I/O) ports  240 , an expansion card  250 , a network device  260 , and a display  270 . The electronic system  200 ,  300 , or  400  may also include a camera module  280 . 
     The processor  10  may be the SoC  10  illustrated in  FIG. 1, 6 , or  8 . The processor  10  may be a multi-core processor. The processor  10  may control the operation of at least one of the elements  210  through  280 . 
     The power source  210  may supply an operating voltage to at least one of the elements  10  and  220  through  280 . The storage device  220  may be implemented as a hard disk drive (HDD) or a solid state drive (SSD). 
     The memory  230  may be implemented as a non-volatile memory that can store a program code for controlling the operation of the processor  10  or a volatile memory that can store data. The non-volatile memory may be flash memory, an embedded multimedia card (eMMC), and a universal flash storage (UFS). The volatile memory may be dynamic random access memory (DRAM). 
     According to some embodiments, a memory controller (not shown) that controls a data access operation, for example, a read operation, a write operation (or a program operation), or an erase operation, on the memory  230  may be integrated into or embedded in the processor  10 . Alternatively, the memory controller may be provided between the processor  10  and the memory  230 . 
     The I/O ports  240  may receive data from the electronic system  200 ,  300 , or  400  or transmit data from the electronic system  200 ,  300 , or  400  to an external device. For example, the I/O ports  240  may include a port for connection with a pointing device such as a computer mouse or a touch pad, a port for connection with an output device such as the display  270  or a printer, a port for connection with an input device such as a keypad or a keyboard, and/or a port for connection with a USB drive. 
     The expansion card  250  may be implemented as a secure digital (SD) card or a multimedia card (MMC). According to embodiments, the expansion card  250  may be a subscriber identity module (SIM) card or a universal SIM (USIM) card. 
     The network device  260  may enable the electronic system  200 ,  300 , or  400  to be connected with a wired or wireless network for communication with an external device. The display  270  may display data output from the storage device  220 , the memory  230 , the I/O ports  240 , the expansion card  250 , or the network device  260 . 
     The camera module  280  is a module that can convert an optical image into an electrical image. Accordingly, the electrical image output from the camera module  280  may be stored in the storage device  220 , the memory  230 , or the expansion card  250 . In addition, the electrical image output from the camera module  280  may be displayed through the display  270 . 
       FIG. 11  is a block diagram of an electronic system  500  according to other embodiments of the inventive concept. Referring to  FIG. 11 , the electronic system  500  may be implemented as a portable electronic device. The portable electronic device may be implemented as a laptop computer, a mobile telephone, a smart phone, a tablet PC, a PDA, an EDA, a digital still camera, a digital video camera, a PMP, a PND, a handheld game console, or an e-book. 
     The electronic system  500  may include a SoC  10 - 1  and a power management integrated circuit (PMIC)  510 . Unlike the SoC  10  illustrated in  FIG. 1, 6 , or  8 , the SoC  10 - 1  illustrated in  FIG. 11  may not include the power management unit  170  therein. In other words, the total power of the SoC  10 - 1  may be controlled by a separate voltage management circuit, for example, the PMIC  510  implemented outside the SoC  10 - 1 . 
     As discussed above, according to some embodiments of the inventive concept, a SoC measures a power consumed in a non-core power domain in analog mode and measures a power of a core power domain including a core process in digital mode regardless of a peripheral circuit included in the non-core power domain. Therefore, the total power of the SoC is efficiently and accurately measured in hybrid mode. Consequently, the total power and temperature of the SoC is efficiently controlled. 
     While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in forms and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.