Patent Publication Number: US-8116129-B2

Title: Variable resistance memory device and method of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED FOREIGN APPLICATION 
     This application is a divisional of, and claims priority from U.S. application Ser. No. 11/865,491 filed in the United States Patent and Trademark Office on Oct. 1, 2007, now U.S. Pat. No. 7,808,815 which in turn claims priority from Korean Patent Application No. 10-2006-0097305 filed on Oct. 2, 2006 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present disclosure is directed to a variable resistance memory device and method of manufacturing the same. 
     2. Description of the Related Art 
     With an ever-increasing demand for reduction of the power consumption of memory devices, research has been conducted on next-generation memory devices that are nonvolatile and do not need a refresh operation. Examples of next-generation memory devices that are nonvolatile and do not need a refresh operation include phase change random access memory (PRAM) devices using phase change materials, resistive random access memory (RRAM) devices using variable resistance materials such as transition metal oxides, and magnetic random access memory (MRAM) devices using ferromagnetic materials. The materials of next-generation memory devices such as PRAM, RRAM, and MRAM devices have a resistance that varies according to a current or voltage applied thereto and maintain a uniform resistance even after the current or voltage is cut off. In other words, since next-generation memory devices such as PRAM, RRAM, and MRAM devices have nonvolatile properties, they do not need a refresh operation. 
       FIG. 1  is a circuit diagram of a memory cell  10  of a typical next-generation memory device. 
     Referring to  FIG. 1 , the memory cell  10  includes a variable resistance device  11  and a switching device  12 . 
     The variable resistance device  11  is connected between a bit line BL and the switching device  12 , and the switching device  12  is connected between the variable resistance device  11  and a word line WL. 
     A next-generation memory device including the memory cell  10  may be classified as being a PRAM, RRAM, or MRAM device according to the type of the variable resistance device  11 . In other words, if the next-generation memory device including the memory cell  10  is a PRAM device, then the variable resistance device  11  may be formed of a material whose resistance varies according to temperature, such as Ge—Sb—Te (GST). If the next-generation memory device including the memory cell  10  is an RRAM device, then the variable resistance device  11  may be formed of a transition metal oxide and may be interposed between an upper electrode and a lower electrode. If the next-generation memory device including the memory cell  10  is an MRAM device, then the variable resistance device  11  may be comprised of an insulator that is interposed between upper and lower electrodes of a magnetic material. 
     PRAM cells are disclosed in U.S. Pat. No. 6,760,017, RRAM cells are disclosed in U.S. Pat. No. 6,753,561, and MRAM cells are disclosed in U.S. Pat. No. 6,724,674. 
     In the meantime, as the demand for increasing the storage capacity of a memory device increases, the size of memory chips has gradually increased. Accordingly, the resistance, the parasitic resistance, and the capacitance of each signal line in a memory device increase, thereby imposing restrictions on the memory device&#39;s ability to perform operations at high speed. In order to address this challenge, methods of forming a hierarchy of signal lines have been applied to typical DRAM devices, and an example of these methods is disclosed in U.S. Pat. No. 6,069,815. 
     In order to increase the storage capacity and operating speed of next-generation memory devices that use variable resistance materials, signal lines must be formed hierarchically. Therefore, it is desirable to develop a new hierarchical layout of signal lines for variable resistance memory cells, in which each variable resistance memory cell is comprised of a variable resistance device and a switching device. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides a variable resistance memory device which can provide high memory cell efficiency. 
     An embodiment of the present invention also provides a method of manufacturing a variable resistance memory device which can provide high memory cell efficiency. 
     These and other objects will be described in or be apparent from the following description of exemplary embodiments. 
     According to an aspect of the present invention, there is provided a variable resistance memory device. The variable resistance memory device includes a silicon substrate, a plurality of active lines which are formed on the silicon substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices which are formed on the active lines and are separated from one another, a plurality of variable resistance devices which are respectively formed on and connected to the switching devices, a plurality of local bit lines which are formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines which are formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines which are formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines which are formed on the global bit lines, are uniformly separated, and extend in the first direction. 
     According to another aspect of the present invention, there is provided a variable resistance memory device including a silicon substrate, a plurality of active lines which are formed on the silicon substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices which are formed on the active lines and are separated from one another, a plurality of variable resistance devices which are respectively formed on and connected to the switching devices, a plurality of local bit lines which are formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines which are formed on the local bit lines, are uniformly separated, and extend in the first direction, and a plurality of contacts which are formed for each group of variable resistance devices in the first direction and connect the plurality of active lines and the plurality of local word lines. 
     According to still another aspect of the present invention, there is provided a method of manufacturing a variable resistance memory device including forming a plurality of active lines on a silicon substrate so that the active lines are uniformly separated and extend in a first direction, forming a plurality of switching devices on the active lines so that the switching devices are uniformly separated, forming a plurality of variable resistance devices on the switching devices, forming a plurality of local bit lines on the variable resistance devices so that the local bit lines are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, forming a plurality of local word lines on the local bit lines so that the local word lines extend in the first direction, forming a plurality of global bit lines on the local word lines so that the global bit lines extend in the second direction, and forming a plurality of global word lines on the global bit lines so that the global word lines extend in the first direction. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features of the embodiments of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. 
         FIG. 1  is a circuit diagram of a memory cell using a general variable resistance memory device. 
         FIG. 2  is a circuit diagram of a memory cell array of a variable resistance memory device according to an embodiment of the present invention. 
         FIG. 3  is a layout diagram of a hierarchical signal line structure of the memory cell array illustrated in  FIG. 2 . 
         FIG. 4  is an enlarged view of portion A of  FIG. 3  and illustrates a cross point memory cell structure, according to an embodiment of the invention. 
         FIG. 5  is a cross-sectional view of a memory cell array illustrated in  FIG. 4 , taken in a first direction. 
         FIG. 6  is a cross-sectional view of the memory cell array illustrated in  FIG. 4 , taken in a second direction. 
         FIG. 7  is a cross-sectional view of a variable resistance memory device according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Features of embodiments of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of exemplary embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification. 
     For the convenience of explanation, while the invention will be described with regard to a PRAM device by way of example in the following embodiments, it is to be appreciated that the invention can also be applied to RRAM, and MRAM devices. 
       FIG. 2  is a circuit diagram of a memory cell array of a semiconductor memory device  200  according to an embodiment of the present invention. Referring to  FIG. 2 , the semiconductor memory device  200  includes a local word line driver region  210 , a local bit line selection region  220 , and a memory cell array region  230 . 
     A plurality of drivers are located in the local word line driver region  210 . That is to say, the drivers are respectively connected to a plurality of global word lines GWL 0  through GWLn, and select and activate one of a plurality of local word lines LWL 0  through LWL 3  in response to a plurality of local word line selection signals SA 00  through SA 11 . The drivers may be realized as inverters, but the present invention is not restricted thereto. 
     A plurality of switches are located in the local bit line selection region  220 . The switches connect a global bit line GBL to one of the local bit lines LBL 0  through LBL 3  in response to a plurality of local bit line selection signals LA 00  through LA 11 . Each of the switches may be comprised of only one NMOS transistor, but the present invention is not restricted thereto. 
     The local word lines LWL 0  through LWL 3  and the local bit lines LBL 0  through LBL 3  are arranged in the memory cell array region  230 . The local bit lines LBL 0  through LBL 3  intersect the local word lines LWL 0  through LWL 3 . A plurality of variable resistance memory cells, like the one illustrated in  FIG. 1 , are respectively disposed at the intersection between the local bit lines LBL 0  through LBL 3  and the local word lines LWL 0  through LWL 3 . The semiconductor memory device  200  may be a Phase change Random Access Memory (PRAM), Resistive Random Access Memory (RRAM) or Magnetic Random Access Memory (MRAM) device according to the materials of the variable resistance memory cells. 
     In other words, a plurality of word lines or bit lines for selecting each of the variable resistance memory cells of the semiconductor memory device  200  are formed hierarchically as the global word lines GWL 0  through GWLn and the local word lines LWL 0  through LWL 3  or as the global bit lines GBL and the local bit lines LBL 0  through LBL 3 . 
       FIG. 3  is a layout diagram of a hierarchical signal line structure of the memory cell array illustrated in  FIG. 2 . Referring to  FIG. 3 , the memory cell array includes a plurality of global word lines GWL, a plurality of local word lines LWL 0  through LWL 3 , a plurality of global bit lines GBL and a plurality of local bit lines LBL 0  through LBL 3 . 
     The global word lines GWL and the local word lines LWL 0  through LWL 3  are formed in a first direction, and the global bit lines GBL and the local bit lines LBL 0  through LBL 3  are formed in a second direction that is perpendicular to the first direction. The first direction may be a row direction, and the second direction may be a column direction. 
     The local bit lines LBL 0  through LBL 3 , the local word lines LWL 0  through LWL 3 , the global bit lines GBL, and the global word lines GWL may be formed of a metal having high conductivity. The local bit lines LBL 0  through LBL 3 , the local word lines LWL 0  through LWL 3 , the global bit lines GBL, and the global word lines GWL may be formed in different interconnection layers. In other words, the local bit lines LBL 0  through LBL 3  may be formed in a first metal interconnection layer, the local word lines LWL 0  through LWL 3  may be formed in a second metal interconnection layer, the global bit lines GBL may be formed in a third metal interconnection layer, and the global word lines GWL may be formed in a fourth metal interconnection layer. An insulation layer is formed among the first through fourth metal interconnection layers. 
     Also, four local bit lines (LBL 0  through LBL 3 ) are allocated for each of the global bit lines GBL, and four local word lines (LWL 0  through LWL 3 ) are allocated for each of the global word lines GWL. The number of local bit lines allocated for each of the global bit lines GBL or the number of local word lines allocated for each of the global word lines GWL may be increased to 2n (where n is a natural number). 
       FIG. 4  is an enlarged view of portion A of  FIG. 3 , and illustrates a cross point memory cell structure. In the cross point memory cell structure, memory cells have the same size as the intersection between word lines and a bit lines. A semiconductor memory device having the cross point memory cell structure can maximize memory cell efficiency. 
     Referring to  FIG. 4 , a plurality of variable resistance memory cells are respectively located at intersection between a plurality of local word lines LWL 0  through LWL 3  and a plurality of local bit lines LBL 0  through LBL 3 , as indicated by circles, thereby realizing a cross point memory cell structure. 
       FIG. 5  is a cross-sectional view of the memory cell array illustrated in  FIG. 4 , taken in a first direction V-V′, and  FIG. 6  is a cross-sectional view of the memory cell array illustrated in  FIG. 4 , taken in a second direction VI-VI′. The layout of a semiconductor memory device according to an embodiment of the present invention, and a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will hereinafter be described in detail with reference to  FIGS. 3 through 6 . 
     Referring to  FIGS. 3 through 6 , a plurality of active lines ACT are formed on a semiconductor substrate P-SUB, and are uniformly separated. The active lines ACT extend in the first direction (e.g., an x-direction). The active lines ACT may be formed of an n+-type material doped with a high concentration of impurities. 
     A plurality of switching devices  12  are formed on the active lines ACT so that the switching devices  12  are separated from one another. The switching devices  12  may be diodes. The switching devices  12  may be formed using a selective epitaxial growth method. The cathodes of the diodes comprising the switching devices  12  are connected to the active lines ACT. 
     A plurality of lower contacts BC are respectively formed on the switching devices  12 . The lower contacts BC electrically connect the anodes of the switching devices  12  to a plurality of local bit lines LBL 0  through LBL 3 . 
     Thereafter, a plurality of variable resistance elements GST are respectively formed on the lower contacts BC. Here, the variable resistance elements GST may be formed of a variety of types of compounds, including a binary (two-element) compound such as GaSb, InSb, InSe, Sb 2 Te 3 , or GeTe, a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSb 2 Te 4 , or InSbGe, or a quaternary (four-element) compound such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe), or Te 81 Ge 15 Sb 2 S 2 . The anodes of the diodes comprising the switching devices  12  are connected to the variable resistance elements GST. 
     Thereafter, a plurality of upper contacts TC are respectively formed on the variable resistance elements GST, thereby completing the formation of a plurality of variable resistance memory cells. 
     First through fourth metal interconnection layers M 1  through M 4  for accommodating a plurality of signal lines that are used to select each of the variable resistance memory cells are formed on the variable resistance memory cells. 
     The local bit lines LBL 0  through LBL 3  are formed in the first metal interconnection layer M 1 , which is the lowermost interconnection layer of the first through fourth metal interconnection layers M 1  through M 4 . The local bit lines LBL 0  through LBL 3  are uniformly separated and extend in the second direction (e.g., a y-direction). The local bit lines LBL 0  through LBL 3  are connected to the variable resistance elements GST via the upper contacts TC. 
     A plurality of local word lines LWL 0  through LWL 3  are formed in the second metal interconnection layer M 2 , which is formed on the first metal interconnection layer M 1 , and extend in the first direction (e.g., the x-direction). The local word lines LWL 0  through LWL 3  are uniformly separated. The local word lines LWL 0  through LWL 3  respectively correspond to the active lines ACT, and are connected to the active lines ACT via word line contacts WC. In particular, the word line contacts WC are arranged only in sub-word line drive regions illustrated in  FIG. 3 . In order to reduce the resistance of the active lines ACT, however, the word line contacts WC may also be formed for each group of memory cells. 
     Memory cells that are adjacent to the word line contacts WC are formed using a different method from those used to form memory cells that are not adjacent to the word line contacts WC, and thus has different properties from memory cells that are not adjacent to the word line contacts WC. Referring to  FIG. 7 , upper contacts TC may not be formed on variable resistance elements GST for memory cells that are adjacent to word line contacts WC. In other words, the memory cells that are adjacent to the word line contacts WC may serve as dummy memory cells. The dummy memory cells that are adjacent to the word line contacts WC may be formed in the second direction (e.g., the y-direction). 
     A plurality of global bit lines GBL are formed in the third metal interconnection layer M 3 , which is formed on the second metal interconnection layer M 2 . The global bit lines GBL are uniformly separated, and extend in the second direction (e.g., the y-direction). Four local bit lines LBL 0  through LBL 3  are allocated for each of the global bit lines GBL, and each of the global bit lines GBL is selectively connected to the four local bit lines LBL 0  through LBL 3  in response to a plurality of local bit line selection signals LA 00  through LA 11  by a plurality of selection transistors in the local bit line selection region  220  illustrated in  FIG. 2 . 
     A plurality of global word lines GWL are formed in the fourth metal interconnection layer M 4 , which is formed on the third metal interconnection layer M 3 . The global word lines GWL are uniformly separated, and extend in the first direction (e.g., the x-direction). Four local word lines LWL 0  through LWL 3  are allocated for each of the global word lines GWL, and each of the global word lines GWL is selectively connected to the four local word lines LWL 0  through LWL 3  by respective drivers in the local word line driver region  210  illustrated in  FIG. 2 . 
     The local bit lines LBL 0  through LBL 3 , the local word lines LWL 0  through LWL 3 , the global bit lines GBL, and the global word lines GWL may be formed of a metal having high conductivity. An insulation layer may be formed among the first through fourth metal interconnection layers M 1  through M 4  in order to electrically insulate the first through fourth metal interconnection layers M 1  through M 4  from one another. 
     According to the embodiment illustrated in  FIGS. 2 through 4 , four local bit lines are allocated for each global bit line, and four local word lines are allocated for each global word line. However, the present invention is not restricted to this. In other words, the number of local bit lines allocated for each global bit line or the number of local word lines allocated for each global word line may be altered. 
     According to another embodiment of the invention, a plurality of global word lines GWL are formed in the third metal interconnection layer M 3 , which is formed on the second metal interconnection layer M 2 . Also, a plurality of global bit lines GBL are formed in the fourth metal interconnection layer M 4 , which is formed on the third metal interconnection layer M 3 . 
     As described above, according to an embodiment of the present invention, a plurality of local bit lines, local word lines, global bit lines, and global word lines are formed in different interconnection layers, thus enabling a memory device to perform its operations at high speed. In addition, according to an embodiment of the present invention, a plurality of variable resistance memory cells are respectively formed at the intersection between a plurality of local bit lines and a plurality of local word lines, thus guaranteeing optimum memory cell efficiency. 
     While embodiments of the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. It is therefore desired that the present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description to indicate the scope of the invention.