Patent Publication Number: US-2023155506-A1

Title: Switching regulator circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority from Korean Patent Application No. 10-2021-0158838 filed on Nov. 17, 2021 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which are incorporated by reference herein in its entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates generally to a voltage conversion circuit, and more particularly, to a switching regulator circuit. 
     DISCUSSION OF RELATED ART 
     A supply voltage generated within an electronic device may drive various electronic components therein operating at different voltage levels, through use of voltage conversion circuitry that steps down or steps up the supply voltage. The supply voltage may also be dynamically stepped down to a given electronic component to reduce power consumption in low power operational modes. For example, when a digital circuit processing a digital signal operates in a mode requiring relatively low performance, a low-level supply voltage may be provided to the digital circuit, but when the digital circuit requires relatively high performance, a high-level supply voltage may be provided to the digital circuit. Accordingly, a switching regulator circuit capable of generating various levels of supply voltages may be used. The switching regulator circuit may be required to rapidly change a voltage level, yet have limited size constraints, and generate a supply voltage having reduced noise. 
     Miniaturized switching regulator circuits have been required for mobile devices such as Internet of Things (IoT) devices, true wireless stereo (TWS) devices, wireless sensor tags, and smartphones. The mobile devices include several semiconductor chips having various functions, such as a processor, an integrated circuit for communication, an integrated circuit for media processing, and a power management integrated circuit. Circuits within the semiconductor chips may require different respective powers according to an operating condition. To this end, a power management circuit providing multiple power levels/ranges is required. 
     A buck-boost voltage conversion circuit has been known as a power conversion technology that achieves high efficiency. The buck-boost voltage conversion circuit is used as a circuit for supplying power from a battery to each semiconductor chip. 
     However, the buck-boost voltage conversion circuit includes inductors occupying a large area on a substrate of a power management integrated circuit. When the number of inductors increases, it may restrict other design spaces of the power management integrated circuit. Therefore, it is desirable to minimize the number of inductors for this type of circuit. 
     SUMMARY 
     Aspects of the present disclosure provide a single in multi out (SIMO) converter circuit providing multiple outputs but using only one inductor in some embodiments, and a power management integrated circuit thereof. 
     Aspects of the present disclosure provide a switching regulator circuit having high efficiency, low ripple, and a fast response speed, and a power management integrated circuit thereof. 
     Aspects of the present disclosure also provide a switching regulator circuit having improved output voltage accuracy by operating adaptively to an error, and a power management integrated circuit thereof. 
     An embodiment of the present disclosure provides a switching regulator circuit comprising an input circuit including a first circuit part and a second circuit part, each including a plurality of input switches and configured to boost an input voltage and thereby generate an applied voltage. An inductor has a first end that receives the applied voltage. A multi-output end circuit includes a first unit output end and a second unit output end each connected to a second end of the inductor, where each of the first and second unit output ends includes at least one output switch. An error detection circuit may be configured to generate an error detection current and an error detection voltage based on a first output voltage of the first unit output end and a second output voltage of the second unit output end. An output switch controller may be configured to generate an output switch control signal for controlling the output switch based on the error detection voltage and the error detection current. A mode selector may be configured to select one of a plurality of operating modes based on the input voltage and respective target output voltage for the first or second unit output ends. An input switch controller may be configured to generate an input switch control signal for controlling the input switches based on the selected operating mode. The first circuit part may include a first flying capacitor and the second circuit part may include a second flying capacitor. The input switch controller may alternately charge the first flying capacitor and the second flying capacitor according to the input switch control signal, such that the input circuit outputs the applied voltage. 
     The control of the output switch in a given one of the unit output ends may control a turn-on time of that output switch, to thereby adjust the output voltage of that unit output end towards the target voltage associated therewith. 
     An embodiment of the present disclosure provides a switching regulator circuit comprising a first input circuit including a first circuit part and a second circuit part, each including a plurality of first input switches and a flying capacitor, boosting an input voltage, and outputting the boosted voltage as a first applied voltage, a first inductor receiving the first applied voltage, a second input circuit including a third circuit part and a fourth circuit part each including a plurality of second input switches, boosting an input voltage, and outputting the boosted voltage as a second applied voltage, a second inductor receiving the second applied voltage, a multi-output end circuit including a first unit output end, a second unit output end, and a third unit output end each connected to a common output end between the first inductor and the second inductor, each of the first to third unit output ends including at least one output switch, an error detection circuit generating first to third error detection currents and first to third error detection voltages based on first to third output voltages of the first to third unit output ends, respectively, an output switch controller generating an output switch control signal for controlling the output switch based on the first to third error detection currents, a mode selector configured to select operating modes based on the input voltage and respective target output voltages of the first through third unit output ends, and an input switch controller receiving a selection result of the mode selector and based thereon, generating an input switch control signal for controlling the first input switches and the second input switches. 
     An embodiment of the present disclosure provides a switching regulator circuit comprising an input circuit including a plurality of input switches, boosting an input voltage or a ground voltage, and outputting an applied voltage, an inductor receiving the applied voltage, a connection node switching circuit including a connection node switch connected between an output node of the inductor and a ground conductor, a multi-output end circuit including a first unit output end, a second unit output end, and a third unit output end connected to the output node of the inductor, each of the first to third unit output ends including at least one output switch, an error detection circuit generating first to third error detection currents and first to third error detection voltages based on first to third output voltages, respectively, of the first to third unit output ends, an output switch controller generating an output switch control signal for controlling the output switch based on the first to third error detection currents, a mode selector configured to select operating modes based on the input voltage and respective target output voltages of the first through third unit output ends, and an input switch controller configured to receive a selection result of the mode selector and based thereon, generate an input switch control signal for controlling the input switch and the connection node switch. 
     However, aspects of the present disclosure are not restricted to those set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. Various elements of the same or similar type may be distinguished by annexing the reference label with an underscore/dash and second label that distinguishes among the same/similar elements (e.g., _1, _2), or directly annexing the reference label with a second label (e.g., VO 1 , VON). However, if a given description uses only the first reference label (e.g., VO), it is applicable to any one of the same/similar elements having the same first reference label irrespective of the second label. 
         FIG.  1    depicts waveforms for describing a comparative example of a single in multi out (SIMO) converter according to a comparative example. 
         FIG.  2    is a diagram illustrating a semiconductor device according to some exemplary embodiments. 
         FIG.  3    is a circuit diagram illustrating a switching regulator circuit according to some exemplary embodiments, and  FIG.  4    is a timing diagram for describing an operation of the switching regulator circuit of  FIG.  3   . 
         FIG.  5    is a table for describing an operating mode setting condition of the switching regulator circuit according to some exemplary embodiments. 
         FIG.  6    is a circuit diagram illustrating a mode selector according to some exemplary embodiments. 
         FIG.  7    is a table for describing an operating mode setting condition of an input switch controller according to some exemplary embodiments. 
         FIG.  8    is a circuit diagram illustrating an error detection circuit and a compensation circuit according to some exemplary embodiments. 
         FIG.  9    is a circuit diagram illustrating an output switch controller according to some exemplary embodiments. 
         FIGS.  10 A,  10 B and  10 C  are graphs illustrating operations of output switch selection signals according to an error voltage according to some exemplary embodiments. 
         FIG.  11 A  is a schematic circuit diagram illustrating a modulation circuit of a switching regulator circuit according to some exemplary embodiments. 
         FIG.  11 B  is a timing diagram for describing an operation of the modulation circuit of  FIG.  11 A . 
         FIGS.  12 A,  12 B and  12 C  are diagrams for describing operations of an input circuit in a buck mode. 
         FIGS.  13 A,  13 B to  13 D  are diagrams for describing operations of the input circuit in a buck-boost mode. 
         FIGS.  14 A,  14 B and  14 C  are diagrams for describing operations of the input circuit in a synchronous boost mode. 
         FIGS.  15 A,  15 B,  15 C,  15 D and  15 E  are diagrams for describing operations of the input circuit in an interleaving boost mode. 
         FIG.  16    is a circuit diagram illustrating a switching regulator circuit according to some exemplary embodiments. 
         FIG.  17    is a circuit diagram illustrating a switching regulator circuit according to some exemplary embodiments. 
         FIG.  18    is a circuit diagram illustrating a switching regulator circuit according to some exemplary embodiments, and  FIG.  19    is a table illustrating operating modes of the switching regulator circuit of  FIG.  18   . 
         FIGS.  20 A,  20 B,  21 A,  21 B,  22 A and  22 B  are diagrams illustrating operating modes of the switching regulator circuit of  FIG.  19   . 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Hereinafter, various exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. 
     Herein, for brevity, once a particular voltage, current, signal or circuit element is first introduced by a name and a label (e.g., an input voltage VIN), it may be subsequently referred to by just the label (e.g., VIN) or an abbreviated form of the name followed by the label. 
     Herein, when a first circuit component (“component”), e.g., a switch, a capacitor, etc.) is said to be “connected to” a second circuit component (e.g., each connected to a common circuit node in a schematic), the first and second components may be directly or indirectly connected. When directly connected, the first and second components are connected without any intervening component ((e.g., each connected to a common circuit node in a schematic). If the context refers to a drawing showing a direct connection example, it is understood that the addition of an intervening component may be possible in an alternative embodiment to that illustrated. 
     Herein, “connected to ground” or a like phrase refers to a connection to a ground conductor (a conductor having a reference potential) within the circuit/device being described. One example of a ground is a power ground. Similarly, “connected to a supply voltage” such as “connected to VDD” means connected to a circuit node at which the supply voltage is applied. 
       FIG.  1    illustrates waveforms for describing a comparative example of a single in multi out (SIMO) converter according to a comparative example. An example of a conventional SIMO converter circuit requires a ramp-up time D for a current to be ramped up to an inductor. In this case, during the ramp-up time D, the SIMO converter circuit does not transfer electric charges charged in the inductor to output sections of the converter circuit (“output ends”) by turning off a switch connected to the output ends. However, the ramp-up time may also increase based on an amount of load current provided to the inductor. In this case, a large undershoot may occur in an output voltage VN of the output ends. 
     Meanwhile, since power may not be transferred to respective output ends during the ramp-up time, a high inductor peak current is required. Referring to Equation (1), a value obtained by multiplying a value obtained by dividing the total current sum of average output currents (I 1 , I 2 , . . . , IN) of the respective output ends by the remaining time (1-D) obtained by subtracting the ramp-up time from one duty by the number (N) of output ends is an average output current of all output ends. In Equation (1), when the number (N) of output ends and a ramp-up duty ratio (D) are high, the average output current (I L_ave ) also becomes high. 
         I   L_ave   =N ( I   1   +I   2   + . . . +I   N )/(1- D    (1)
 
     Referring to Equation (2), when a root mean square (RMS) current (I RMS ) of the inductor with respect to the ramp-up time becomes high, power loss may become large. In Equation (2), P LOSS  is power loss, R DCR  is a direct current (DC) resistance of the inductor, and I RMS  is an RMS current of the inductor. 
         P   Loss   =I   RMS   2   R   DCR    (2)
 
     There is also a method of periodically detecting an error in order to reduce the undershoot of the output voltage. However, such a method may not cope with a load transient phenomenon until the next error detection cycle, and when a detection cycle frequency is increased, a larger bias current needs to be provided to the inductor. 
       FIG.  2    is a diagram illustrating a semiconductor device according to some exemplary embodiments. 
     Referring to  FIG.  2   , a semiconductor device  1  includes a SIMO converter  100 , low drop out driver circuits (LDO)  10 - 1  to  10 - 4 , a central processing unit (CPU)  20 , a memory  30 , a radio frequency (RF) module  40 , and an RF-power amplifier (PA) module  50 . 
     The semiconductor device  1  may be a device including a communication function. For example, the semiconductor device  1  may include at least one of smartphones, tablet personal computers (PCs), mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbook computers, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, mobile medical devices, cameras, or wearable devices (e.g., head-mounted-devices (HMDs) such as electronic glasses, electronic garments, electronic bracelets, electronic necklaces, electronic appcessories® (a physical device and counterpart application for a mobile device), electronic tattoos, or smart watches). 
     The semiconductor device  1  may be a smart home appliance having a communication function. Some examples of the smart home appliance may include, a television (TV), a digital video disk (DVD) player, an audio player, a refrigerator, an air conditioner, a cleaner, an oven, a microwave oven, a washing machine, an air cleaner, a set-top box, a TV box (e.g., Samsung HomeSync™, Apple TV™, or Google TV™), game consoles, an electronic dictionary, an electronic key, a camcorder, and/or an electronic picture frame. 
     Further examples of the semiconductor device  1  may include at least one of various medical devices (e.g., a magnetic resonance angiography (MRA) device, a magnetic resonance imaging (MRI) device, a computed tomography (CT) device, an imaging device, an ultrasound machine, etc.), navigation devices, global positioning system (GPS) receivers, event data recorders (EDRs), flight data recorders (FDRs), vehicle infotainment devices, marine electronic devices (e.g., marine navigation systems and gyro compasses, etc.), avionics, security devices, vehicle head units, industrial or household robots, automatic teller&#39;s machines (ATMs) of financial institutions, or point of sales (POS) systems of stores. 
     The SIMO converter circuit  100  may be a switching regulator circuit. The SIMO converter circuit  100  embodied as switching regulator circuit may generate an output voltage having a level suitable for each of functional circuits  20  to  50  from a battery supply voltage VBAT provided from a battery by turning on/off at least one switch to adjust a path of an inductor current IL passing through an inductor L. An exemplary configuration of the switching regulator circuit  100  will be described later with reference to  FIG.  3   . 
     The LDO circuits  10 - 1  to  10 - 4 , which are linear regulators, are connected to the battery to perform more precise voltage conversion for the battery supply voltage VBAT. For example, the switching regulator circuit  100  may perform primary voltage conversion on the battery supply voltage VBAT and the LDO circuits  10 - 1  to  10 - 4  may perform secondary voltage conversion on the battery supply voltage VBAT to generate output voltages for the respective components  20  to  50 . 
     The CPU  20  controls the overall operation of the semiconductor device  1 . The memory  30  may be an operation memory of the semiconductor device  1 , or may be a non-volatile memory storing parameters, commands, and the like, necessary for an operation of the semiconductor device  1 . Alternatively, the memory  30  may be a non-volatile memory device storing data. 
     The RF module  40  performs data encoding and modulation. The RF-PA module  50  reflects a preset frequency in a transmission signal generated by the RF module  40  to generate a low-power RF signal, and amplifies the low-power RF signal into an analog signal having a preset power intensity. 
       FIG.  3    is a circuit diagram illustrating a switching regulator circuit according to some exemplary embodiments, and  FIG.  4    is a timing diagram for describing an operation of the switching regulator circuit of  FIG.  3   . 
     Referring to  FIG.  3   , the switching regulator circuit  100  may operate in any one of a plurality of operating modes according to a target level of an output voltage VO (any one of VO 1  to VON, where N is two or more). The operating modes of the switching regulator circuit  100  may include a buck mode, a buck-boost mode, a synchronous boost mode, and an interleaving boost mode. 
     The switching regulator circuit  100  in the buck mode may generate an output voltage VO of which a level is lower than a level of an input voltage VIN, and may be referred to as a buck (or step-down) converter. The switching regulator circuit  100  in the boost mode may generate an output voltage VO of which a level is higher than the level of the input voltage VIN, and may be referred to as a boost (or step-up) converter. In addition, the boost converter may operate in a plurality of boost modes. The switching regulator circuit  100  in the buck-boost mode may generate an output voltage VO (any one of VO 1  to VON) of which a level is lower than or higher than the level of the input voltage VIN. 
     The switching regulator circuit  100  may include an input circuit  110 :  110   a  and  110   b,  an inductor L, a multi-output “end circuit”  120  (an output circuit portion of the switching regulator circuit that provides multiple output voltages at respective output nodes N 31 -N 3 N), an error detection circuit  130   a,  a compensation circuit  130   b,  a pulse width modulation circuit  130   c,  an output switch controller  140 , an input switch controller (interchangeably, “buck-boost controller”)  150 , and a mode selector  160 . 
     The input circuit  110  may include a plurality of circuit parts  110   a  and  110   b  and a switch S 5 . According to some exemplary embodiments, a first circuit part  110   a  includes a plurality of input switches S 1   a  to S 4   a  and a flying capacitor (often referred to as a charge pump) CFa. A second circuit part  110   b  includes a plurality of switches S 1   b  to S 4   b  and a flying capacitor CFb. The switching regulator circuit  100  may be set to and operated in any one of the buck mode, the buck-boost mode, the synchronous boost mode, and the interleaving boost mode by controlling the switching of the first circuit part  110   a  and the second circuit part  110   b  according to the target level of the output voltage VO. 
     The first circuit part  110   a  according to some exemplary embodiments will be described in detail. The switch S 1   a  is connected to a power supply end to which the input voltage VIN is applied and a first end (that may be referred to as an output end of the first circuit part) of the flying capacitor CFa, and the input switch S 3   a  is connected between the first end of the flying capacitor CFa and a node N 1  (i.e., one end of the inductor L). The switch S 2   a  between a second end of the flying capacitor CFa and ground, and the switch S 4   a  is connected between the power supply (input voltage) VIN terminal and the second end of the flying capacitor CFa. The second circuit part  110   b  has the same circuit configuration as the first circuit part  110   a,  such that a detailed description thereof is omitted. In this case, the input voltage VIN may be the battery input voltage VBAT described with reference to  FIG.  2   . 
     Each of the output ends of the input switches S 3   a  and S 4   a  is connected to a common node N 1 , and the switch S 5   b  is connected between node N 1  and ground. A single inductor L is connected between the node N 1  and a node N 2 . 
     The multi-output circuit end  120  is connected between an output end of the inductor L, which is the node N 2 , and the error detection circuit  130   a.  The multi-output end circuit  120  includes at least one “unit output end”  121 _ 1  to  121 _N, generating independent output voltages VO 1  to VON for the respective functional circuits  20  to  50  (see  FIG.  1   ). The output voltages VO 1  to VON have supply voltage levels required by the respective functional circuits  20  to  50  (see  FIG.  1   ). Accordingly, it is desired for each of the output voltages VO 1  to VON to be in a respective target voltage range (e.g., according to the table of  FIG.  5   ). 
     For example, a first unit output end includes a switch SV 1  connected between the node N 2  and an output node N 31 , a load capacitor CL 1  connected between the output node N 31  and ground, and a current source  101  connected between the output node N 31  and ground. For instance, the multi-output end circuit  120  may include first to Nth unit output ends  121 _ 1  to  121 _N, where N is illustrated as four or more in  FIG.  3   , but in general, N may be two or more, and each unit output end (e.g., a k-th unit output end) includes a switch SVk, a capacitor CLk, and a current source (IOk). Here, k is a natural number. 
     The error detection circuit  130   a  receives output voltages VO 1  to VON from output nodes N 31  to N 3 N of the unit output ends and generates an error detection voltage VE. 
     The error detection voltage VE is output to the input switch controller  150  and the output switch controller  140 , and becomes a basic signal for controlling turn-on/off of the circuit part  110   a  or the switches SV 1 , SV 2 , . . . , SVN included in any one unit output end. 
     The output switch controller  140  controls the turn-on/off of the switches SV 1  and SV 2  to SVN of the unit output ends based on the error detection voltage VE. For example, suppose that an output voltage VOk of a unit output end  121 _ k  is lower than the target voltage for the output end  121 _ k  by the largest offset among all of the offsets for the output voltages VO 1  to VON (where each offset may be measured with respect to a respective reference voltage VOREF 1  to VOREFN). In this case, the turn-on duration of the switch SVk may be set longer than the turn-on durations of each of the other switches SV, which builds up charge within the capacitor CLk, so that the voltage VOk can be quickly raised to a voltage close to the target voltage (e.g., near the center of a target voltage range for the output end  121 _ k ). An analogous dynamic adjustment may occur when an output voltage VOk is higher than a preset maximum voltage within the target range. In this manner, the output voltages VO 1  to VON may be dynamically adjusted, with priority given to the output voltage that deviates furthest from its respective target voltage. In addition, the mode selector  160  may set the operating mode differently for each of the unit output ends  121 _ 1  to  121 _N based on the target voltage (as explained below with respect to  FIG.  5   ). 
     The input switch controller  150  outputs switch signals of the circuit parts  110   a  and  110   b  adjusted according to a control signal of the mode selector  160 . As described later, the input switch controller  150  may generate switching control signals of the input switches S 1   a,  S 2   a,  S 3   a,  and S 4   a  so that the flying capacitor CFa of the circuit part (e.g., the first circuit part  110   a ) operates as a charge pump by the input switches S 1   a,  S 2   a,  S 3   a,  and S 4   a.    
     Referring to  FIG.  4   , the switching operation of the circuit parts  110   a  and  110   b  operates independently of the switching operation of the multi-output end circuit  120  in the switching regulator circuit  100 . In other words, the circuit parts  110   a  and  110   b  and the multi-output end circuit  120  operate asynchronously. A turn-on sequence of an output switch SV operates according to an output voltage drop of each unit output end  121 . Accordingly, the switching of an output switch SV is not synchronized with a reference clock signal CK, and may be quickly turned on according to the error detection voltage VE based on an output voltage VO of each unit output end. 
     As an example, when the switching regulator circuit  100  operates in the buck mode as illustrated in  FIG.  4   , the first circuit part  110   a  and the second circuit part  110   b  may operate in the buck-boost mode or the boost mode. However, the multi-output end circuit  120  operates according to the error detection voltage based on the output voltage of each unit output end  121  regardless of an operating mode of the input circuit  110 . 
     The multi-output end circuit  120  may operate as follows: only a single one of first through Nth output switches SV 1 -SVN is turned on. (In  FIG.  3   , N is four or more, but in  FIG.  4   , the components and voltages of the unit output ends  121 _ 1  to  121 _ 3  are shown as an example, and described hereafter.). In this case, one of the output voltages VO 1 -VO 3  is built up by charges accumulated in a respective output load capacitor CL 1 -CL 3  when the corresponding output switch (any one of the output switches SV 1 -SV 3 ) is turned on, and thus, a voltage level rises. In the illustrated example, when the first output switch SV 1  is turned on, the output voltage VO 1  rises, and the output voltages VO 2 -VO 3  of the other unit output ends  121 _ 2  and  121 _ 3  fall. Subsequently, when SV 2  is turned on, the output voltage VO 2  rises, and the output voltages VO 1  and VO 3  fall. Subsequently, SV 3  is turned on, VO 3  rises, and VO 1  and VO 2  fall. 
     Meanwhile, describing an output voltage VX 1  of the node N 1  tied to the input end of inductor L and an input voltage VX 2  of the node N 2  tied to the output end of inductor L, the output voltage VX 1  generated by the circuit parts  110   a  and  110   b  in the buck mode corresponds to the battery input voltage VBAT. However, the input voltage VX 2  input to the multi-output end circuit  120  is generated as a higher voltage (for example, VO 1 ) or a lower voltage VO 3 , as illustrated in  FIG.  4   , than VBAT according to the inductor current IL in the inductor L. At this time, the input circuit  110  supplies a continuous output current as the inductor current IL. An operating mode of the input circuit  110  will be described later with reference to  FIGS.  5  to  7   . 
       FIG.  5    is a table for describing an operating mode setting condition of the switching regulator circuit according to some exemplary embodiments,  FIG.  6    is a circuit diagram illustrating a mode selector according to some exemplary embodiments, and  FIG.  7    is a table for describing an operating mode setting condition of an input switch controller according to some exemplary embodiments. 
     The mode selector  160  illustrated in  FIG.  6    selects one of a plurality of operating modes according to a relationship between the input voltage VIN and the output voltage VO in the table of  FIG.  5   , and switching of the circuit parts  110   a  and  110   b  is controlled as illustrated in  FIG.  7    according to the selected operating mode. The plurality of operating modes may include, for example, a buck mode, a buck-boost mode, a synchronous-boost mode, and an interleaving-boost mode. 
     The mode selector  160  may compare the input voltage VIN with a minimum value of an “output reference voltage”, e.g., a minimum output voltage VO_min (the minimum of VO measured during a most recent measurement interval) of each unit output end  121 . In addition, the mode selector  160  compares a maximum value of the output reference voltage, e.g., a maximum output voltage VO_max, of each unit output end  121  with an input voltage (e.g., VIN(1−a), VIN(1+a), or VIN(1+b)), which may be a multiple (greater or less than 1) of VIN. In this case, VIN(1−a) refers to a (1−a) multiple of the input voltage VIN, VIN(1+a) refers to a (1+a) multiple of the input voltage VIN, and VIN(1+b) refers to a (1+b) multiple of the input voltage VIN. It is noted that the constants a and b (e.g., 0.1 and 0.5, respectively) may be variously set according to characteristics of a power management integrated circuit. 
     For example, for a given unit output end  121 _ i,  the buck mode is selected when VO_min&lt;VIN and VO_max&lt;VIN(1−a) for that unit output end  121 _ i.    
     For example, the buck-boost mode is selected when VO_min&lt;VIN and any of the other conditions for the maximum output voltage in the table of  FIG.  5    are met: (i) VIN(1−a)&lt;VO_max&lt;VIN(1+b) or greater than the input voltage (VIN(1+b)&lt;VO_max). 
     For example, the synchronous boost mode (Boost-Synchronous) is selected when the minimum output voltage of the unit output end is greater than the input voltage (VO_min&gt;VIN) and the maximum output voltage of the unit output end is slightly greater than the input voltage (VIN(1+a)&lt;VO_max&lt;VIN(1+b)). 
     For example, the interleaving-boost mode (Boost-Interleaving) is selected when the minimum output voltage of the unit output end is greater than the input voltage (VO_min&gt;VIN) and the minimum output voltage of the unit output end is greater than the input voltage (VIN(1+b)&lt;VO_max). 
     In  FIG.  6   , according to some exemplary embodiments, the mode selector  160  includes comparators  161 - 1  to  161 -N, a selection circuit  162 , a multiplexer  163 , a division impedance  164 , and output comparators  165   a  to  165   d.    
     The comparators  161 - 1  to  161 -N compare preset output reference voltages VO 1 _REF to VON_REF (which may be the same as VREF 1  to VREFN, respectively, in  FIG.  3   ) with each other (N is generally 2 or more) and output comparison results through the selection circuit  162 , and the multiplexer  163  selects and outputs any one of the output reference voltages according to the comparison results. The preset output reference voltages VO 1 _REF to VON_REF may have voltage levels preset with respect to the output voltage VO of each of the functional circuits  20  to  50 . 
     In this case, the output reference voltages selected and output by the multiplexer  163  are the maximum output voltage VO_max having a maximum value and the minimum output voltage VO_min having a minimum value among the preset output reference voltages of the multi-output end circuit  120 . 
     The division impedance  164  is connected in series between a power supply and ground to generate one or more divided reference voltages VREF_BB, VREF_BT 1 , and VREF_BT 2  from the input voltage VIN. The divided reference voltage may be, for example, a value in which the multiple such as (1−a), (1+a), or (1+b) described with reference to  FIG.  5    is reflected in the input voltage VIN. 
     The output comparators  165   a  to  165   d  compare the divided reference voltages VREF_BT 2 , BREF_BT 1 , and VREF_BB with the maximum output voltage VO_max or compare the divided reference voltage VREF_BB with the minimum output voltage VO_min. The output comparators  165   a  to  165   d  may output mode detection signals VA, VB, VC, and VD to the input switch controller  150  as comparison results between the maximum output voltage or the minimum output voltage and the divided reference voltages. 
     Referring to  FIGS.  5  and  7   , the input switch controller  150  may select one of the plurality of operating modes based on the mode detection signals VA, VB, VC, and VD of the output comparators  165   a  to  165   d.  For example, the mode detection signal may have the number of bits corresponding to the plurality of operating modes. As an example, the number of operating modes is seven in an example illustrated in  FIG.  5   , and thus, the mode detection signal may be 4 bits. Each of the most significant bit to the least significant bit of the mode detection signal may be in a logic high state or a logic low state according to outputs of the output comparators  165   a  to  165   d.    
     The mode detection signal VA indicates whether or not the input voltage has a level greater than the minimum output voltage (VIN&gt;VO_min or VIN&lt;VO_min), and the mode detection signals VB, VC, and VD may be comparison results between the maximum output voltage VO_max and the input voltages VIN to which predetermined multiples a and b are applied. 
     For example, when the input voltage VIN is greater than the minimum output voltage VO_min (VO_min&lt;VIN), the mode detection signal VA is [L], and when the maximum output voltage VO_max is smaller than (1−a) times the input voltage (VO_max)&lt;VIN(1−a)), the mode detection signals VB, VC, and VD are output as [L, L, L], and the input switch controller  150  may detect the buck mode and control switching signals of the switches S 1   a,b,  S 2   a,b,  S 3   a,b,  S 4   a,b,  and S 5  (in case of No.  1  in  FIG.  7   ). 
     For example, when the input voltage VIN is greater than the minimum output voltage VO_min (VO_min&lt;VIN), the mode detection signal VA is [L], and when the maximum output voltage VO_max exceeds (1−a) times the input voltage and is smaller than (1+a) times the input voltage (VIN(1−a)&lt;VO_max)&lt;VIN(1+a)), the mode detection signals VB, VC, and VD are output as [H, L, L], and the input switch controller  150  may detect the buck-boost mode and control the switching signals of the switches S 1   a,b,  S 2   a,b,  S 3   a,b,  S 4   a,b,  and S 5  (in case of No.  2  in  FIG.  7   ). 
     For example, when the input voltage VIN is greater than the minimum output voltage VO_min (VO_min&lt;VIN), the mode detection signal VA is [L], and when the maximum output voltage VO_max exceeds (1+a) times the input voltage and is smaller than (1+b) times the input voltage (VIN(1+a)&lt;VO_max)&lt;VIN(1+b)), the mode detection signals VB, VC, and VD are output as [X, H, L], and the input switch controller  150  may detect the buck-boost mode and control the switching signals of the input switches S 1   a,b,  S 2   a,b,  S 3   a,b,  S 4   a,b,  and S 5  (in case of No.  3  in  FIG.  7   ). 
     For example, when the input voltage VIN is greater than the minimum output voltage VO_min (VO_min&lt;VIN), the mode detection signal VA is [L], and when the maximum output voltage VO_max exceeds (1+b) times the input voltage (VIN(1+b)&lt;VO_max), the mode detection signals VB, VC, and VD are output as [X, X, H], and the input switch controller  150  may detect the buck-boost mode and control the switching signals of the input switches S 1   a,b,  S 2   a,b,  S 3   a,b,  S 4   a,b,  and S 5  (in case of No.  4  in  FIG.  7   ). 
     For example, when the input voltage VIN is smaller than the minimum output voltage VO_min (VO_min&gt;VIN), the mode detection signal VA is [H], and when the maximum output voltage VO_max exceeds (1−a) times the input voltage and is smaller than (1+a) times the input voltage (VIN(1−a)&lt;VO_max)&lt;VIN(1+a)), the mode detection signals VB, VC, and VD are output as [X, L, L], and the input switch controller  150  may detect the buck-boost mode and control the switching signals of the input switches S 1   a,b,  S 2   a,b,  S 3   a,b,  S 4   a,b,  and S 5  (in case of No.  5  in  FIG.  7   ). 
     For example, when the input voltage VIN is smaller than the minimum output voltage VO_min (VO_min&gt;VIN), the mode detection signal VA is [H], and when the maximum output voltage VO_max exceeds (1+a) times the input voltage and is smaller than (1+b) times the input voltage (VIN(1+a)&lt;VO_max)&lt;VIN(1+b)), the mode detection signals VB, VC, and VD are output as [X, H, L], and the input switch controller  150  may detect the synchronous-boost mode and control the switching signals of the input switches S 1   a,b,  S 2   a,b,  S 3   a,b,  S 4   a,b,  and S 5  (in case of No.  6  in  FIG.  7   ). 
     For example, when the input voltage VIN is smaller than the minimum output voltage VO_min (VO_min&gt;VIN), the mode detection signal VA is [H], and when the maximum output voltage VO_max exceeds (1+b) times the input voltage (VIN(1+b)&lt;VO_max), the mode detection signals VB, VC, and VD are output as [X, X, H], and the input switch controller  150  may detect the interleaving-boost mode and control the switching signals of the input switches S 1   a,b,  S 2   a,b,  S 3   a,b,  S 4   a,b,  and S 5  (in case of No.  7  in  FIG.  7   ). 
       FIG.  8    is a circuit diagram illustrating an error detection circuit and a compensation circuit according to some exemplary embodiments.  FIG.  9    is a circuit diagram illustrating an output switch controller according to some exemplary embodiments. 
     Referring to  FIG.  8   , according to some exemplary embodiments, the error detection circuit  130   a  may include a plurality of unit error amplifiers  132 - 1  to  132 -N and a current addition circuit  133 , and the compensation circuit  130   b  of  FIG.  3    may be a compensation circuit  134  connected to an output end of an error detection voltage VE 0  of  FIG.  8   . 
     The unit error amplifiers  132 - 1  to  132 -N compare the preset output reference voltages VO 1 _REF to VON_REF described above with reference to  FIG.  6    with the output voltages VO 1  to VON of the respective unit output ends to generate error detection currents IE 1  to IEN. The error detection circuit  130   a  may further include voltage division circuits  131 - 1  to  131 -N. The voltage dividing circuits  131 - 1  to  131 - 1 N may adjust the output voltages VO 1  to VON in a voltage level range according to ratios between the output voltages and the reference voltages. 
     The current addition circuit  133  outputs a summed error detection current obtained by adding all of the respective error detection currents IE 1  to IEN. The summed error detection current is converted into a voltage signal by the compensation circuit  134  and is output as a summed error detection voltage VEO. The compensation circuit  134  may be a circuit including a resistor and/or capacitors. 
     Referring to  FIG.  9   , the output switch controller  140  receives the error detection currents IE 1  to IEN from the error detection circuit  130   a,  and generates and outputs output switch control signals for the output switches SV 1  and SV 2  to SVN. 
     The output switch controller  140  includes a current source IB inputting a preset current corresponding to each error detection current IE, a resistor RE for generating a voltage signal from the error detection current IE, a maximum voltage selection circuit  143 , and a minimum on-time adjustment circuit  145 . 
     The current sources providing a bias current I bias  may each be connected between a power supply VDD and error detection input nodes N 91 , N 92 , . . . N 9 N, the error detection currents IE are input to the error detection nodes N 91 , N 92 , . . . N 9 N, and resistors RE 1 , RE 2 , . . . , REN are connected between the error detection input nodes N 91 , N 92 , . . . , N 9 N and ground. 
     Referring to Equation (3), an error detection voltage (e.g., an error detection voltage V EN  of the error detection input node N 9 N) is generated by adding the bias current I bias  to the error detection current I EN  and then applying the resistor R EN . In Equation (3), the bias current I B  is an additional offset current of the error detection input node N 9 N, and a voltage is V OFFSET . (The same equations herein associated with the unit output end  121 _N apply to each of the other unit output ends  121   i  (i=to (N-1)), where “i” is substituted for N.) 
         V   EN   =R   EN ( I   EN   +I   bias )= R   EN   I   EN   +V   OFFSET    (3)
 
     The error detection voltage V EN  is based on the error detection current I EN  at the Nth unit output end node  121 _N of  FIG.  8   , and may thus be expressed as in Equation (4). 
       Δ V   EN   =R   EN   I   EN   =R   EN   G   M ( V   ON   REF   −V   ON   /Z   RATIO )   (4)
 
     The error detection current I EN  is a value obtained by applying the error amplifier  132  and a transconductance gain GM to a value obtained by dividing a difference (V ON_REF −V ON ) between the preset output reference voltage VREF and the output voltage VO by a resistance  131 -N division ratio (Z RATIO ). 
     Referring to Equation (5), an output error ratio (D ERR ) may be expressed as follows: 
     by a value obtained by dividing a value obtained by dividing a value obtained by subtraction of a current output voltage (V ON ) from an output reference voltage (VN REF ) for an N-th unit output end  121 _N by the resistance division ratio (Z RATIO ) by an output reference voltage (V ON     REF   ) of a current node. Here, when Equation (5) is substituted into Equation (4), a change amount (ΔV EN ) of the error detection voltage may be summarized as Equation (6). 
         D   ERR =−( V   ON     REF     −V   ON   /Z   RATIO )/ V   ON     REF      (5),
 
     where (Z RATIO ) is the resistance division ratio, VON is the output voltage for unit output end  121 _N, and VNREF is the output reference voltage associated with the unit output end  121 _N. 
     When Equation (5) is substituted into Equation (4), a change amount (ΔV EN ) of the error detection voltage may be summarized as Equation (6): 
       | D   ERR   |=|ΔV   EN /( R   EN   G   M   V   ON     REF   )|  (6)
 
     In circuit design, a maximum error rate is different for each power rail supplying a source voltage of a circuit, and thus, it is more practical to control the error ratio (D ERR ) compared to the change amount (ΔV EN ) of the error detection voltage in an actual environment. 
     In addition, when transconductance gains GM of the respective error amplifiers  132 - 1  to  132 -N are the same, matching performance of error measurements for each unit output end  121  is facilitated. Accordingly, in Equation (6), a resistance impedance R EN  may be selected according to the output error ratio D ERR  required for design. For example, to obtain an output having a high precision, the error detection voltage V EN  needs to rise rapidly with respect to a voltage error, and thus, a high resistance value R EN  is required. 
     The maximum voltage selection circuit  143  selects a node of a maximum error detection voltage among the error detection voltages VE 1  to VEN of the respective unit output ends. The maximum voltage selection circuit  143  continuously compares the error detection voltages VE 1 , VE 2 , . . . , VEN of different unit output ends with each other and outputs comparison results to the minimum on-time adjustment circuit  145 . Hence, the output switch control signals are not turned on/off by comparison with a specific threshold value, but the error detection voltages are compared with each other, and thus, a ripple phenomenon of the output voltage VO of each unit output end may be reduced. 
     The minimum on-time adjustment circuit  145  adjusts an on-time of an output switch control signal SVk (k is a natural number and refers to a selected output end) of the node of the maximum error detection voltage VEk among inputs of the maximum voltage selection circuit  143  so as to be maintained for a preset minimum unit time or longer. When an error detection voltage (e.g., VE(k- 1 )) of the other unit output end becomes a maximum error detection voltage during the on-time, the minimum on-time adjustment circuit  145  adjusts the on-time so that the output switch control signals of the output switches SV 1  to SVN do not overlap each other while moving to the next on-time section. 
     A minimum on-time TMIN may prevent the output switch from operating at a preset frequency or higher because switching loss of the output end may reduce power efficiency. In addition, the minimum on-time TMIN prevents overlap between on-times of the output switch control signals so that an output capacitor is not short-circuited. Operations of the output switch signals will be described later with reference to  FIGS.  10 A to  10 C . 
       FIGS.  10 A to  10 C  are graphs illustrating operations of output switch selection signals according to an error voltage according to some exemplary embodiments. 
     In  FIGS.  10 A to  10 C , a first output voltage VO 1 , a first load current IO 1 , and an first error detection voltage VE 1  are voltages and a current related to the first unit output end, a second output voltage VO 2 , a second load current  102 , and second error detection voltage VE 2  are voltages and a current related to the second unit output end, and a third output voltage VO 3 , a third load current  103 , and a third error detection voltage VE 3  are voltages and a current related to the third unit output end. The respective error detection voltages VE 1 , VE 2 , and VE 3  are generated based on the output voltages VO 1 , VO 2 , and VO 3  of the respective unit output ends according to the circuit of  FIG.  8   . The output switch control signals of the output switches SV 1 , SV 2 , and SVN turn on or off the output switches of  FIG.  3   . 
     Referring to  FIG.  10 A , when a position having a minimum output voltage at a point in time t 1  is the first unit output end VO 1  as a result of comparing the output voltages VO 1 , V 02 , and VO 3  of the respective unit output ends with each other in the multi-output end circuit  120 , the first error detection voltage VE 1  of the error detection voltages may have a maximum value. When the first error detection voltage VE 1  has the maximum value, the output switch controller  140  shifts a first output switch control signal SV 1  to a logic high state and causes the logic high state to have a preset minimum on-time TMIN, and prevents the other output switch control signals of the output switches SV 2  and SV 3  from being turned on while the first output switch control signal of the output switch SV 1  is in the logic high state. 
     Even though the second error detection voltage VE 2  becomes higher than the first error detection voltage VE 1  within the minimum on-time TMIN (t 1  to t 2 ), the output switch controller  140  maintains the first output switch control signal of the output switch SV 1  in the logic high state. 
     When the second output voltage VO 2  has a minimum output voltage at a point in time t 2 , the second error detection voltage VE 2  has a maximum value, and the second output switch control signal of the output switch SV 2  is shifted to a logic high state. At this time, when the minimum on-time of the first output switch control signal SV 1  has elapsed, the first output switch control signal of the output switch SV 1  is shifted to a logic low state, and only the second output switch control signal of the output switch SV 2  is in a logic high state during a minimum on-time TMIN. 
     When the third output voltage VO 3  has a minimum output voltage at a point in time t 3 , the third error detection voltage VE 3  has a maximum value, and the third output switch control signal of the output switch SV 3  is shifted to a logic high state. When the minimum on-time of the second output switch control signal SV 2  has elapsed, the second output switch control signal of the output switch SV 2  is shifted to a logic low state, and only the third output switch control signal of the output switch SV 3  is in a logic high state during a minimum on-time TMIN or longer. 
     In  FIG.  10 B , the output switch controller  140  may operate according to a change in the error detection voltage of the unit output end. For example, when the first error detection voltage of the first unit output end is greater than the second error detection voltage of the second unit output end, the output switch controller  140  may turn on the first output switch control signal of the output switch SV 1  so that an on-time of the first output switch control signal of the output switch SV 1  of the first unit output end is longer than an on-time of the second output switch control signal of the output switch SV 2  of the second unit output end and an on-time of or the third output switch control signal of the output switch SV 3  of the third unit output end. 
     In  FIG.  10 C , unlike  FIG.  10 B , when a load transient phenomenon occurs in the second unit output end ( 102  of  FIG.  3   ) at a point in time t 1 , the second error detection voltage VE 2  quickly rises due to the drop of the second output voltage V 02 . The output switch control signal of the output switch SV 2  of the second unit output end is turned on and is shifted to a logic high state when the second error detection voltage VE 2  becomes the largest compared to the other error detection voltages VE 1  and VE 3 . 
     Referring to  FIGS.  10 A to  10 C  together, the output switch control signals of the output switches SV 1 , SV 2 , and SV 3  may be turned on and be shifted to a logic high state during the minimum on-times according to an exemplary embodiment, but according to various exemplary embodiments, on-times of the output switch control signals of the output switches SV 1 , SV 2 , and SV 3  may be quickly adjusted according to a change in the output voltage VO or the load current IO. Accordingly, the output switch control signals of the output switches SV 1  to SV 3  may have a fast load transient response according to the output voltage. 
       FIG.  11 A  is a schematic circuit diagram illustrating a modulation circuit of a switching regulator circuit according to some exemplary embodiments, and  FIG.  11 B  is a timing diagram for describing an operation of the modulation circuit of  FIG.  11 A . 
     Referring to  FIG.  11 A , the switching regulator circuit  100  includes an input circuit  110 , an inductor L, a multi-output end circuit  120 , error detection and compensation circuits  130   a  and  130   b,  and a pulse width modulation circuit  130   c.    
     The input circuit  110  may operate in the same manner as the input circuit described with reference to  FIG.  3   . Redundant description is omitted. However, the mode selector  160  and the input switch controller  150  of  FIG.  3    may be included in the input circuit  110 . In addition, the inductor L, the multi-output end circuit  120 , and the error detection and compensation circuits  130   a  and  130   b  overlap those of the above-described exemplary embodiments, and a description thereof is thus omitted. 
     The pulse width modulation circuit  130   c  may include a comparator, a current-voltage converter, and a QR latch circuit. The pulse width modulation circuit  130   c  receives an error detection voltage VEO from the error detection and compensation circuits  130   a  and  130   b,  and compares the error detection voltage VEO with a ramp-up voltage VCS. The ramp-up voltage VCS is generated by current-voltage conversion based on a ramp-up current ICS generated by the input circuit  110  and input to the inductor L. 
     In the current-voltage conversion, as illustrated in  FIG.  11 B , the ramp-up current ICS may flow to a preset current sensing resistor to generate a gradient of the ramp-up voltage VCS. A comparison result between the ramp-up voltage VCS and the error detection voltage VEO is output from the QR latch circuit according to a clock signal CLK. A pulse width of a pulse width modulation (PWM) signal is determined according to the comparison result between the ramp-up voltage VCS and the error detection voltage VEO, and the PWM signal of which the pulse width is determined is output. Alternatively, in the current-voltage conversion, although not illustrated, according to some exemplary embodiments, in a case of a voltage mode control manner, a pulse width of a PMW signal may be determined using a ramp voltage having a triangular wave shape, and the PWM signal of which the pulse width is determined may be output. 
     The input circuit  110  may control the input switch controller  150  based on an output signal PWM of the pulse width modulation circuit  130   c.  The input switch controller  150  may be controlled based on a current mode, a voltage mode, a hysteresis mode, or the like, of the output signal PWM according to various exemplary embodiments. 
     In an alternative embodiment, the PWM modulator  130   c  is replaced with circuitry for providing a digital representation of the VEO signal. Such circuity may include a sample and hold circuit that periodically samples VEO, and an analog to digital (A/D) converter that digitizes the periodically sampled signal. The resulting digital signal may be applied to the input switch controller  150  where it is used for the same purpose as the PWM signal. 
       FIGS.  12 A to  15 E  are circuit diagrams and timing diagrams for describing operating modes of the switching regulator circuit. In the circuit diagrams, paths through which currents flow are indicated by dotted lines. 
       FIGS.  12 A to  12 C  are diagrams for describing operations of an input circuit in a buck mode.  FIGS.  12 A and  12 B  illustrate operations of the input circuit in a first phase (Phase  1 ) and a second phase (Phase  2 ) in the buck mode, respectively.  FIG.  12 C  depicts example waveforms of a voltage and a current for describing an operation of the input circuit in the buck mode. In the buck mode, the first circuit part  110   a  and the second circuit part  110   b  operate in a synchronous switching control manner to reduce conduction losses of the input switches S 1   a  and S 1   b  and the input switches S 3   a  and S 3   b.  The synchronous switching control manner may refer to a manner of controlling the switches so that the first flying capacitor CFa and the second flying capacitor CFb are charged in the same phase or are connected to the inductor L in the same phase over a plurality of phases of a switching cycle. 
     In  FIGS.  12 A and  12 C , in the first phase, in the first circuit part  110   a,  the input switches S 1   a,  S 2   a,  and S 3   a  are turned on (closed), and the input switches S 4   a  and S 5  are turned off. Also, in the second circuit part  110   b,  the input switches S 1   b,  S 2   b,  and S 3   b  are turned on, and the input switch S 4   b  is turned off. Currents for charging the flying capacitors CFa and CFb and a current applied to the inductor L may simultaneously flow to the first circuit part  110   a  and the second circuit part  110   b.  Accordingly, an inductor current IL may gradually rise, and an applied voltage VX may coincide with the input voltage VIN. 
     In  FIG.  12 B , in the second phase, in the first circuit part  110   a,  the input switches S 1   a,  S 2   a,  and S 5  are turned on, and the input switches S 3   a  and S 4   a  are turned off. Also, in the second circuit part  110   b,  the input switches S 1   b  and S 2   b  are turned on, and the input switches S 3   b  and S 4   b  are turned off. Accordingly, the input voltage VIN does not pass through the flying capacitors CFa and CFb, and the inductor L may be connected to a ground node based on the input switch S 5  to receive an applied voltage VX corresponding to a ground voltage GND. Accordingly, the inductor current IL may gradually fall, such that the applied voltage VX becomes equal to the ground voltage GND. In this case, each of the flying capacitors CFa and CFb may be charged according to the input voltage VIN. 
       FIGS.  13 A to  13 D  are diagrams for describing exemplary operations of the input circuit in a buck-boost mode. In the buck-boost mode, the input circuit operates in three phases, and the first circuit part  110   a  and the second circuit part  110   b  operate in a synchronous switching control manner.  FIG.  13 A  illustrates current paths of the input circuit  110  in a first phase (Phase  1 ),  FIG.  13 B  illustrates current paths of the input circuit  110  in a second phase (Phase  2 ),  FIG.  13 C  illustrates current paths of the input circuit  110  in the third phase (Phase  3 ), and  FIG.  13 D  shows graphs of a voltage and a current for describing an operation of the input circuit in the buck-boost mode. In  FIGS.  13 A to  13 C , current paths are indicated by dotted lines. 
     Referring to  FIGS.  13 A and  13 D , according to some exemplary embodiments, in the first phase, in the first circuit part  110   a,  the input switches S 3   a  and S 4   a  are turned on, and the input switches S 1   a,  S 2   a,  and S 5  are turned off. Similar to the first circuit part  110   a,  in the second circuit part  110   b,  the input switches S 3   b  and S 4   b  are turned on, and the input switches S 1   b  and S 2   b  are turned off. Each of the flying capacitors CFa and CFb is connected between the inductor L and the power supply end to which the input voltage VIN is applied. The flying capacitors CFa and CFb are charged based on the input voltage VIN, and unlike the buck mode of  FIG.  12   , currents flow only along paths passing through the flying capacitors. Accordingly, an inductor current IL applied to the inductor L may gradually rise, but an applied voltage VX may reach a voltage corresponding to about two times the input voltage VIN in proportion to the number of flying capacitors. 
     Referring to  FIGS.  13 B and  13 D , according to some exemplary embodiments, in the second phase, in the first circuit part  110   a,  the input switches S 1   a,  S 2   a,  and S 3   a  are turned on, and the input switches S 4   a  and S 5  are turned off. Similar to the first circuit part  110   a,  in the second circuit part  110   b,  the input switches S 1   b,  S 2   b,  and S 3   b  are turned on, and the input switch S 4   b  is turned off. Each of the flying capacitors CFa and CFb is connected between the power supply VIN and ground, such that currents for charging the flying capacitors CFa and CFb and a current applied to the inductor L may simultaneously flow to the first and second circuit parts  110   a  and  110   b.  Accordingly, an inductor current IL may gradually rise, and an applied voltage VX may coincide with the input voltage VIN. 
     In  FIGS.  13 C and  13 D , in the third phase, in the first circuit part  110   a,  the input switches S 1   a,  S 2   a,  and S 5  are turned on, and the input switches S 3   a  and S 4   a  are turned off. Also, in the second circuit part  110   b,  the input switches S 1   b  and S 2   b  are turned on, and the input switches S 3   b  and S 4   b  are turned off. Accordingly, the input voltage VIN does not pass through the flying capacitors CFa and CFb, and the inductor L may be connected to a ground node based on the input switch S 5  to receive an applied voltage VX corresponding to a ground voltage GND. Accordingly, the inductor current IL may gradually fall, such that the applied voltage VX becomes equal to the ground voltage GND. In this case, each of the flying capacitors CFa and CFb may be charged according to the input voltage VIN. 
     That is, in the buck-boost mode, the applied current IL applied to the inductor L gradually rises ({circle around (1)}), is maintained for a predetermined time ({circle around (2)}), and then gradually falls ({circle around (3)}) according to three phases. Based on the applied current, the applied voltage VX is also shifted to a voltage 2VIN corresponding to about two times the input voltage, a voltage VIN corresponding to the input voltage, and a ground voltage GND. 
       FIGS.  14 A to  14 C  are diagrams for describing operations of the input circuit in a synchronous boost mode.  FIG.  14 A  illustrates current paths of the input circuit  110  in a first phase (Phase  1 ),  FIG.  14 B  illustrates current paths of the input circuit  110  in a second phase (Phase  2 ), and  FIG.  14 C  shows graphs of a voltage and a current for describing an operation of the input circuit in the synchronous boost mode. Current paths are indicated by dotted lines. 
     Referring to  FIGS.  14 A and  14 C , according to some exemplary embodiments, in the first phase, in the first circuit part  110   a,  the input switches S 3   a  and S 4   a  are turned on, and the input switches S 1   a,  S 2   a,  and S 5  are turned off. Similar to the first circuit part  110   a,  in the second circuit part  110   b,  the input switches S 3   b  and S 4   b  are turned on, and the input switches S 1   b  and S 2   b  are turned off. Each of the flying capacitors CFa and CFb is connected between the inductor L and the power supply end to which the input voltage VIN is applied. Accordingly, an inductor current IL applied to the inductor L may gradually rise, but an applied voltage VX may reach a voltage corresponding to about two times the input voltage VIN in proportion to the number of flying capacitors. 
     Referring to  FIGS.  14 B and  14 C , according to some exemplary embodiments, in the second phase, in the first circuit part  110   a,  the input switches S 1   a,  S 2   a,  and S 3   a  are turned on, and the input switches S 4   a  and S 5  are turned off. Similar to the first circuit part  110   a,  in the second circuit part  110   b,  the input switches S 1   b,  S 2   b,  and S 3   b  are turned on, and the input switch S 4   b  is turned off. One end of each flying capacitor is connected to the power supply end and the inductor and the other end of each flying capacitor is connected to both ends of a ground end, such that currents for charging the flying capacitors CFa and CFb and a current applied to the inductor L may simultaneously flow to the first circuit part  110   a  and the second circuit part  110   b.  Accordingly, an inductor current IL may gradually rise, and an applied voltage VX may coincide with the input voltage VIN. 
     That is, in the synchronous boost mode, the applied current IL applied to the inductor L gradually rises ({circle around (1)}), and then gradually falls ({circle around (2)}) according to two phases. The applied voltage VX is also about two times the voltage (2VIN) of the input voltage in section {circle around (1)}, and is then shifted to a voltage VIN corresponding to one time the input voltage in section {circle around (2)}. 
       FIGS.  15 A to  15 E  are diagrams for describing operations of the input circuit in an interleaving boost mode.  FIGS.  15 A to  15 D  illustrate current paths of the input circuit  110  in a first phase (Phase  1 ) to a fourth phase (Phase  4 ), and  FIG.  15 E  shows graphs of a voltage and a current for describing an operation of the input circuit. 
     Referring to  FIGS.  15 A,  15 B, and  15 E , in the first phase, in the first circuit part  110   a,  the input switches S 3   a  and S 4   a  are turned on, and the input switches S 1   a,  S 2   a,  and S 5  are turned off. In the second circuit part  110   b,  the input switches S 1   b  and S 2   b  are turned on, and the input switches S 3   b  and S 4   b  are turned off. Meanwhile, in the second phase, in the first circuit part  110   a,  the input switches S 1   a  and S 3   a  are turned on, and the input switches S 2   a,  S 4   a,  and S 5  are turned off. In the second circuit part  110   b,  the input switches S 1   b  and S 2   b  are turned on, and the input switches S 3   b  and S 4   b  are turned off. While the second circuit part  110   b  continuously charges intensively the flying capacitor CFb with electric charges in the first phase and the second phase, the first circuit part  110   a  provides a voltage boosted in the flying capacitor CFa or the input voltage to the inductor L as an applied voltage. 
     In addition, referring to  FIGS.  15 C,  15 D, and  15 E , in the third phase, in the first circuit part  110   a,  the input switches S 1   a  and S 2   a  are turned on, and the input switches S 3   a  and S 4   a  are turned off. In the second circuit part  110   b,  the input switches S 3   b  and S 4   b  are turned on, and the input switches S 1   b,  S 2   b,  and S 5  are turned off. Meanwhile, in the fourth phase, in the first circuit part  110   a,  the input switches S 1   a  and S 2   a  are turned on, and the input switches S 3   a  and S 4   a  are turned off. In the second circuit part  110   b,  the input switches S 1   b  and S 3   b  are turned on, and the input switches S 2   b  and S 4   b  are turned off. Thus, in the third and fourth phases, the first circuit part  110   a  continuously charges intensively the flying capacitor CFb with electric charges, and the second circuit part  110   b  provides the input voltage VIN as an applied voltage VX or provides a voltage charged in the flying capacitor CFb as an applied voltage VX. 
     That is, in the interleaving boost mode, the first circuit part  110   a  and the second circuit part  110   b  alternately operate to reduce an average applied current IL input to the inductor L under a high duty condition. For example, while the first circuit part  110   a  charges the flying capacitor CFa, the second circuit part  110   b  provides power to the inductor, and conversely, while the second circuit part  110   b  charges the flying capacitor CFb, the first circuit part  110   a  provides power to the inductor. According to such an interleaving boost operation, an average current I S1  provided to the input switch S 1  is expressed by the following Equation (7). 
     
       
         
           
             
               
                 
                   
                     I 
                     
                       
                         S 
                         ⁢ 
                         1_ 
                         ⁢ 
                         INT 
                       
                       ⁢ 
                       _AVG 
                     
                   
                   = 
                   
                     
                       
                         Δ 
                         ⁢ 
                         
                           Q 
                           
                             F 
                             ⁢ 
                             L 
                             ⁢ 
                             Y 
                           
                         
                       
                       
                         1 
                         
                           F 
                           SW 
                         
                       
                     
                     = 
                     
                       
                         I 
                         O 
                       
                       ⁢ 
                       D 
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     In Equation (7), I S1_INT_AVG  refers to an average initial current applied to the switch S 1 , Q FLY  refers to a quantity of electric charges charged in the flying capacitors CFa and CFb), F SW  refers to an operating frequency of the switch, I O  refers to an output current, and D refers to a length of a duty in a switching cycle. Referring to Equation (7), an average current in the switch S 1  is stably applied, and the input circuit stably operates with high efficiency even in a state in which the duty D is high. 
     Thus, an operation of a booster converter may be reconfigured according to a duty ratio, and the above-described switching regulator circuit  100  may stably operate with high efficiency. 
       FIG.  16    is a circuit diagram illustrating a switching regulator circuit according to some exemplary embodiments. 
     Referring to  FIG.  16   , a switching regulator circuit  200  may include an input circuit  210 , an inductor L, a multi-output end circuit  220 , an error detection circuit  230   a,  a compensation circuit  230   b,  a pulse width modulation circuit  230   c,  an output switch controller  240 , an input switch controller  250 , and a mode selector  260 . The switching regulator circuit  200  includes the inductor L, the multi-output end circuit  220 , the error detection circuit  230   a,  the compensation circuit  230   b,  the pulse width modulation circuit  230   c,  the output switch controller  240 , the input switch controller  250 , and the mode selector  260  that are the same as those of the switching regulator circuit  100  described above with reference to  FIG.  3   , and a redundant description thereof is thus omitted. 
     The input circuit  210  may include one flying capacitor CF and a plurality of input switches S 1  to S 5 . Switches S 1  to S 4  are connected to each other in series between a power input terminal, to which a battery input voltage VIN is provided, and a ground conductor (e.g., a power ground)at a ground voltage GND. The flying capacitor CF is connected between a first common node between the switch S 1  and the switch S 2  and a second common node between the switch S 3  and the switch S 4 . The switch S 5  is connected between the power input end and the second common node. The input circuit  210  illustrated in  FIG.  16    may be implemented with fewer switches and capacitors than the input circuit  110  of  FIG.  3   . 
     The input circuit  210  may operate in a first phase to a fourth phase, and may operate according to a plurality of operating modes each including at least two of the first phase to the fourth phase. The plurality of operating modes may be determined based on at least one of an output voltage VO, an error detection voltage VE, or an error detection current IE. For example, each operating mode may be selected according to the reference described in  FIG.  5    or  FIG.  7    to generate an applied voltage VX 1  of the inductor L. 
     For example, the input circuit  210  may turn on the input switches S 1 , S 2 , and S 4  and turn off the input switches S 3  and S 5  in the first phase to provide a boosting voltage of the flying capacitor CF as the applied voltage VX 1 . For example, the input circuit  210  may turn on the input switches S 1  and S 4  and turn off the input switches S 2 , S 3 , and S 5  in the second phase to charge the flying capacitor CF with electric charges. For example, the input circuit  210  may turn on the input switches S 1  and S 2  and turn off the input switches S 3 , S 4 , and S 5  in the third phase to provide the input voltage VIN as the applied voltage VX 1 . For example, the input circuit  210  may turn on the input switches S 3  and S 4  and turn off the input switches S 1 , S 2 , and S 5  in the fourth phase to provide a ground voltage GND as the applied voltage VX 1 . 
       FIG.  17    is a circuit diagram illustrating a switching regulator circuit according to some exemplary embodiments. 
     Referring to  FIG.  17   , a switching regulator circuit  300  may include at least two input circuits  310 - 1  and  310 - 2  and at least two inverters L 1  and L 2  each connected to the input circuits. For example, the switching regulator circuit  300  may include a first input circuit  310 - 1  and a first inductor L 1 , a second input circuit  310 - 2  and a second inductor L 2 , a multi-output end circuit  320  including N unit output ends  121 _ 1  to  121 _N, an error detection circuit  330   a,  a compensator  330   b,  a pulse width modulation circuit  330   c,  an output switch controller  340 , an input switch controller  350 , and a mode selector  360 . In  FIG.  17   , N is illustrated as four or more, but in other embodiments, N may be as low as two. 
     For example, when any one (e.g. the RF-PA module  50 ) of the respective components  20  to  50  of  FIG.  2    receiving a converted voltage requires a much higher instantaneous peak current than the other components, a high instantaneous peak current may be generated using one or more inductors. For example, while the first input circuit  310 - 1  operates as a current source, the second input circuit  310 - 2  may operate in an interleaving boost mode to reduce an output ripple of the multi-output end circuit  320 . 
     Hence, the first input circuit  310 - 1  and the second input circuit  310 - 2  may be switched synchronously to operate alternately or may operate in an asynchronous boosting mode. 
       FIG.  18    is a circuit diagram illustrating a switching regulator circuit according to some exemplary embodiments, and  FIG.  19    is a table illustrating operating modes of the switching regulator circuit of  FIG.  18   . 
     Referring to  FIG.  18   , a switching regulator circuit  400  may include an input circuit  410 , an inductor L, a connection node switching circuit  415 , a multi-output end circuit  420 , an error detection circuit  430   a,  a compensator  430   b,  a pulse width modulation circuit  430   c,  an output switch controller  440 , an input switch controller  450 , and a mode selector  460 . Redundant description of components previously described will be omitted. The multi-output end circuit  420  includes at least two unit output ends  121 _ 1  to  121 _N (N=at least two, although at least four unit output ends  121 _ 1  to  121 _N are illustrated in  FIG.  18   ). 
     The input circuit  410  includes a plurality of input switches. The input switch S 1  is connected between a power supply end and an inductor input node VX 1 , and the input switch S 2  is connected between the inductor input node VX 1  and a ground conductor. The connection node switching circuit  415  includes a connection node switch S 3 . The connection node switch S 3  is connected between an inductor output node VX 2  and the ground conductor. The input switches S 1  and S 2  and the connection node switch S 3  are turned on/off under the control of the input switch controller  450 . 
     The switching regulator circuit  400  may operate in a plurality of operating modes. For example, the switching regulator circuit  400  may operate in a buck mode, a buck-boost mode, and a boost mode. 
     Referring to  FIG.  19   , the mode selector  460  may compare a maximum output voltage VO_max and a minimum output voltage VO_min of the multi-output end circuit  420  with an input voltage VIN or a scaled input voltage with respect to VIN, which may be VIN scaled by a predetermined scale factor (greater than or less than 1). The input voltage or scaled input voltage may be used to select an operating mode of the switching regulator circuit  400 . For example, the predetermined scale factor may be (1−a) or (1+a), where “a” is a constant, and for example, a=0.1, but any suitable value may be substituted. 
     For example, when the minimum output voltage is smaller than the input voltage (VO_min&lt;VIN) and the maximum output voltage is smaller than (1−a) times the input voltage (VO_max&lt;VIN(1−a)), the switching regulator circuit  400  may operate in the buck mode. 
     For example, when the minimum output voltage is smaller than the input voltage (VO_min&lt;VIN) and the maximum output voltage is greater than or equal to (1−a) times the input voltage and smaller than (1+a) times the input voltage (VIN(1−a)≤VO_max&lt;VIN(1+a)), the switching regulator circuit  400  may operate in the buck-boost mode. 
     For example, when the minimum output voltage is smaller than the input voltage (VO_min&lt;VIN) and the maximum output voltage is greater than or equal to (1+a) times the input voltage (VIN(1+a)≤VO_max)), the switching regulator circuit  400  may operate in the buck-boost mode. 
     For example, when the minimum output voltage is greater than the input voltage (VO_min&gt;VIN) and the maximum output voltage is greater than or equal to (1−a) times the input voltage and smaller than (1+a) times the input voltage (VIN(1−a)≤VO_max&lt;VIN(1+a)), the switching regulator circuit  400  may operate in the buck-boost mode. 
     For example, when the minimum output voltage is greater than the input voltage (VO_min&gt;VIN) and the maximum output voltage is greater than or equal to (1+a) times the input voltage (VIN(1+a)≤VO_max)), the switching regulator circuit  400  may operate in the boost mode. 
       FIGS.  20 A to  22 B  are diagrams illustrating operating modes of the switching regulator circuit of  FIG.  19   . 
     Referring to  FIGS.  20 A and  20 B , when the switching regulator circuit operates in the buck mode, the input circuit  410  and the connection node switching circuit  415  of the switching regulator circuit  400  operate in a first phase and a second phase. In the first phase ({circle around (1)}), the input switch S 1  is turned on, the input switch S 2  is turned off, and the connection node switch S 3  is turned off. The input voltage VIN is provided as an applied voltage VX 1  of the inductor L, and an output voltage VX 2  of the inductor is provided to the multi-output end circuit  420  so that an inductor current IL gradually rises. In the second phase ({circle around (2)}), the input switch S 2  and the input switch S 1  are turned off, and the connection node switch S 3  is turned off. A ground voltage GND is provided as the applied voltage VX 1  of the inductor L, and the output voltage VX 2  of the inductor is provided to the multi-output end circuit  420  so that an inductor current IL gradually falls. 
     Referring to  FIGS.  21 A and  21 B , when the switching regulator circuit operates in the buck-boost mode, the input circuit  410  and the connection node switching circuit  415  of the switching regulator circuit  400  operate in a first phase, a second phase, and a third phase. In the first phase ({circle around (1)}), the input switch S 1  is turned on, the input switch S 2  is turned off, and the connection node switch S 3  is turned off. The input voltage VIN is provided as an applied voltage VX 1  of the inductor L, and an output voltage VX 2  of the inductor is provided to the multi-output end circuit  420  so that an inductor current IL gradually rises. In the second phase ({circle around (2)}), the input switch S 1  is turned on, the input switch S 2  is turned off, and the connection node switch S 3  is turned on. For example, the inductor current is continuously generated, but is not provided to the multi-output end circuit  420  and flows to the ground conductor, and is thus maintained at a constant level. In the third phase ({circle around (3)}), the input switch S 2  and the input switch S 1  are turned off, and the connection node switch S 3  is turned off. A ground voltage GND is provided as the applied voltage VX 1  of the inductor L, and the output voltage VX 2  of the inductor is provided to the multi-output end circuit  420  so that an inductor current IL gradually falls. 
     Referring to  FIGS.  22 A and  22 B , when the switching regulator circuit operates in the boost mode, the input circuit  410  and the connection node switching circuit  415  of the switching regulator circuit  400  operate in a first phase and a second phase. In the first phase ({circle around (1)}), the input switch S 1  is turned on, the input switch S 2  is turned off, and the connection node switch S 3  is turned off. The input voltage VIN is provided as an applied voltage VX 1  of the inductor L, and an output voltage VX 2  of the inductor is provided to the multi-output end circuit  420  so that an inductor current IL gradually rises. In the second phase ({circle around (2)}), the input switch S 1  is turned on, the input switch S 2  is turned off, and the connection node switch S 3  is turned on. The input voltage VIN is provided as an applied voltage VX 1  of the inductor L, and an output voltage VX 2  of the inductor is provided to the ground conductor, such that the inductor current gradually decreases. 
     Exemplary embodiments of the present disclosure have been described hereinabove with reference to the accompanying drawings, but the present disclosure is not limited to the above-described exemplary embodiments, and may be implemented in various different forms, and one of ordinary skill in the art to which the present disclosure pertains may understand that the present disclosure may be implemented in other specific forms. Therefore, it is to be understood that the exemplary embodiments described above are illustrative rather than being restrictive in all aspects.