Patent Publication Number: US-11037842-B2

Title: Semiconductor device with inspection patterns

Description:
This application claims the benefit of priority to Korean Patent Application No. 10-2018-0120197, filed on Oct. 10, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     1. Field 
     The present disclosure relates to a semiconductor device and a method of fabricating the same. 
     2. Description of the Related Art 
     As semiconductor devices become smaller, the rate of occurrence of random defects as well as system defects may increase when fine patterns are realized, thus reducing the yield. Such random defects may occur as a process center set at the time of initial equipment setup is gradually changed as a process is performed or according to a change in hardware condition. If the process center is changed to eventually deviate from a process window, defects may occur, thus reducing the total yield. Detecting a change in the process center after the yield is reduced causes a loss of time/physical resources. Therefore, it would be useful to detect or monitor a change in the process center in advance and correct the change in the process center before the yield is reduced. 
     SUMMARY 
     Aspects of the present disclosure provide a semiconductor device including a substrate inspection pattern for detecting a change in a process center in advance. 
     Aspects of the present disclosure also provide a method of fabricating a semiconductor device including a substrate inspection pattern for detecting a change in a process center in advance. 
     However, aspects of the present disclosure are not restricted to the ones set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below. 
     According to certain aspects of the disclosed embodiments, a semiconductor device includes a first normal pattern which is disposed in an active area of a semiconductor chip, wherein the first normal pattern has a particular shape and the active area includes circuitry for operating the semiconductor chip, and includes a first defective pattern and a second normal pattern which are disposed in a dummy area of the semiconductor chip, wherein the dummy area of the semiconductor chip is an area that does not perform functions for operating the semiconductor chip. The second normal pattern has the same shape as the first normal pattern and the first defective pattern has the same shape as the first normal pattern except for a first defect. The first normal pattern is disposed at a first level layer of the semiconductor chip. The first defective pattern comprises a first part and a second part, and the second normal pattern comprises a third part corresponding to the first part and that matches the first part in shape and size and a fourth part corresponding to the second part, wherein the second part includes the first defect and matches the fourth part in shape and size except for the first defect. If the second part and fourth part were to be superimposed over each other, the second part would include a piece of material that is absent from the fourth part and that comprises the first defect. 
     According to certain aspects of the disclosed embodiments, a semiconductor device includes a first, non-operating, pattern which is disposed in a dummy area of a semiconductor chip and comprises first inspection patterns arranged successively, and a second, operating, pattern which is disposed in an active area of the semiconductor chip and is for operating the semiconductor chip. Each of the first inspection patterns comprises one or more first defective patterns and a plurality of first normal patterns, wherein each of the first normal patterns comprises a first part and a second part, and each of the first defective patterns comprises a third part corresponding to the first part and a fourth part corresponding to the second part, wherein the first part matches the third part in shape and size, and the second part and the fourth part match each other in shape and size except for a first defect. If the second part and fourth part were to be superimposed over each other, the fourth part would include a piece of material that is absent from the second part and that comprises the first defect, or the second part would include a piece of material that is absent from the fourth part such that the missing material in the fourth part comprises the first defect. 
     According to certain aspects of the disclosed embodiments, a method of fabricating a semiconductor device includes forming a first normal pattern in an active area of a semiconductor substrate, forming a first inspection pattern, which comprises a first defective pattern and a second normal pattern, in a dummy area of the semiconductor substrate, cutting the semiconductor substrate to form a plurality of semiconductor chips, and fabricating a plurality of semiconductor devices using the plurality of semiconductor chips. A shape of the second normal pattern is the same as a shape of the first normal pattern, the first normal pattern and the first inspection pattern are formed at the same level layer during fabricating the semiconductor device, the first defective pattern comprises a first part and a second part, and the second normal pattern comprises a third part corresponding to the first part and a fourth part corresponding to the second part, wherein the first part and the third part have the same size and shape, and the second part and the fourth part have a different size and/or shape. If the first normal pattern were to be superimposed over the first defective pattern, the first part would match the third part, and the second part would not match the fourth part. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and/or other aspects will become apparent and more readily appreciated from the following description of various embodiments, taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a diagram for explaining a process window and a process variation. 
         FIG. 2  is a diagram for explaining the relationship between a process center and a yield. 
         FIG. 3  is a diagram for explaining a reduced process window and detection of a change in the process center according to embodiments. 
         FIG. 4  illustrates a substrate inspection pattern SIP according to embodiments. 
         FIG. 5  illustrates an area in which the substrate inspection pattern SIP according to certain embodiments is disposed. 
         FIGS. 6 and 7  are respectively diagrams for explaining an operating pattern OP, a first normal pattern NP 1  and a first defective pattern DP 1  according to embodiments. 
         FIG. 8  is a flowchart illustrating a method of determining a first defective structure and a second defective structure to be included in a substrate inspection pattern according to embodiments. 
         FIG. 9  illustrates a defect determining pattern DDP according to embodiments. 
         FIG. 10  is a diagram for explaining a method of inspecting a defect determining pattern for defects by using the first equipment for measuring structural defects according to embodiments. 
         FIGS. 11 and 12  are respectively diagrams for explaining methods of inspecting a defect determining pattern for defects by using the second equipment for measuring electrical defects according to embodiments. 
         FIG. 13  is a diagram for explaining a method of determining a pattern to be used in a substrate inspection pattern according to embodiments. 
         FIG. 14  illustrates a substrate inspection pattern SIP according to embodiments. 
         FIG. 15  illustrates a defect determining pattern DDP according to embodiments. 
         FIG. 16  illustrates a method of determining an inspection pattern to be used in a substrate inspection pattern according to embodiments. 
         FIG. 17  is a flowchart illustrating a substrate inspection method according to embodiments. 
         FIG. 18  illustrates first through third substrate inspection patterns SIP 1  through SIP 3  according to embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a diagram for explaining a process window and a process variation.  FIG. 2  is a diagram for explaining the relationship between a process center and a yield. 
     Referring to  FIG. 1 , a first process window  10  represents a tolerance range of parameters of a specific process. When a process is performed outside the first process window  10 , a defect may occur in the process result, causing a reduction in the yield of the process. For example, the first process window  10  may represent an exposure amount and an error in depth of focus in a photolithography process. For ease of description, it will be assumed that the specific process is a photolithography process, the horizontal axis of the first process window  10  indicates the exposure amount of the photolithography process, and the vertical axis of the first process window  10  indicates the error in depth of focus of the photolithography process, but embodiments are not limited to this case. 
     A first process variation area  20  represents the degree of variation in the exposure amount and error in depth of focus of the photolithography process when the process center is located at a first point F 1 . The process center denotes, for example, a target exposure amount and a target error in depth of focus of photolithography equipment. A variation in the exposure amount and a variation in the error in depth of focus of the photolithography process may arise from the position of a substrate, but embodiments are not limited to this case. As another example, the variation in the exposure amount and the variation in the error in depth of focus of the photolithography process may arise from a process, voltage and temperature (PVT) variation. 
     When the process center for the photolithography process is located at the first point F 1 , even if the photolithography process is changed, the exposure amount and the error in depth of focus of the photolithography process may all be included in the first process window  10 , thus ensuring the yield. For example, since the first process variation area  20  is included in the first process window  10  when the process center is located at the center of the first process window  10 , the yield can be ensured. Therefore, when initially setting equipment or performing maintenance of the equipment, an operator may adjust a process recipe or modify hardware such that the process center is located at the first point F 1 . 
     However, when the photolithography process is repeatedly performed, the process center can be changed to another position due to various causes. For example, the process center can be changed due to an error in software/firmware or can be changed according to hardware condition. This will be described in detail with reference to  FIG. 2 . 
     Referring to  FIG. 2 , the process center may be changed from the first point F 1  to a second point F 2 . Here, a second process variation area  25  may be included in the first process window  10 . The second process variation area  25  represents the degree of variation in the exposure amount and error in depth of focus of the photolithography process when the process center is located at the second point F 2 . When the process center is located at the second point F 2 , even if the photolithography process is changed, the exposure amount and the error in depth of focus of the photolithography process may all be included in the first process window  10 , thus ensuring the yield. Therefore, even if the process center is changed from the first point F 1  to the second point F 2 , the yield can be ensured because the second process variation area  25  is still included in the first process window  10 . 
     Later, the process center may be changed from the second point F 2  to a third point F 3 . Here, at least a part of a third process variation area  30  may not be included in the first process window  10 . The third process variation area  30  represents the degree of variation in the exposure amount and error in depth of focus of the photolithography process when the process center is located at the third point F 3 . Therefore, when the process center is changed from the second point F 2  to the third point F 3 , the exposure amount and the error in depth of focus of the photolithography process may deviate from the first process window  10  in some cases. At least a part of the third process variation area  30  which is not included in the first process window  10  will be referred to as a defective area  32  for the sake of convenience. Therefore, if the photolithography process is performed in the defective area  32  due to a change in the photolithography process, a defect may occur in the process result. Hence, the total process yield may be reduced when the process center is located at the third point F 3 . 
     As illustrated in  FIGS. 1 and 2 , the first process window  10  may be set larger than the first, second and third process variation areas  20 ,  25  and  30 . Therefore, even if the process center is changed from the first point F 1  to the second point F 2 , the second process variation area  25  is still included in the first process window  10 , thus ensuring the yield of the photolithography process. Therefore, even if the process center is changed from the first point F 1  to the second point F 2 , the yield may be unaffected as long as the whole of the second process variation area  25  is included in the first process window  10 . Therefore, since the change of the process center from the first point F 1  to the second point F 2  does not affect the total yield, it may not be possible to identify whether the process center has been changed. 
     However, when the process center is changed from the second point F 2  to the third point F 3  (or if it is changed directly from the first point F 1  to the third point F 3 ), the total yield is reduced, in which case the change in the process center can be identified. Since a reduction in yield increases cost, it is important to detect a change in the process center before the yield is reduced. 
       FIG. 3  is a diagram for explaining a reduced process window and detection of a change in the process center according to certain embodiments. 
     Referring to  FIG. 3 , the process window can be reduced from a first process window  10  to a second process window  15  using a method according to certain embodiments. Here, the first process window  10  may be a range in which the yield of actual process results is ensured. The second process window  15  may be a range in which it is determined that the process center has not been changed. 
     In a case where the process center is changed from the first point F 1  to the second point F 2 , the second point F 2  and at least a part of the second process variation area  25  deviate from the second process window  15 . Therefore, it can be determined that the process center has been changed. However, since the second point F 2  and the second process variation area  25  are still included in the first process window  10 , there may be no great change in the yield. Therefore, according to some embodiments, it is possible to detect a change in the process center before the yield is reduced. 
     According to some embodiments, a defect may be intentionally formed in a specific area (e.g., a dummy area  130  in  FIG. 5 ) to reduce the process window. For example, when a defect is formed in a specific area, a process margin is reduced, resulting in a reduction of the process window. Therefore, a substrate inspection pattern (e.g., SIP in  FIG. 4 ) including an intentional defect may be formed in a specific area to reduce the process window only in the specific area, and the specific area may be monitored to detect in advance whether the process center has been changed. This will now be described in detail with reference to the attached drawings. 
       FIG. 4  illustrates a substrate inspection pattern SIP according to certain embodiments.  FIG. 5  illustrates an area in which the substrate inspection pattern SIP according to these embodiments is disposed. 
     Referring to  FIG. 4 , the substrate inspection pattern SIP may include first normal patterns NP 1  and first defective patterns DP 1  arranged alternately. Each of the first normal patterns NP 1  may include a first non-defective structure POR 1  and a second non-defective structure POR 2 . Each of the defective patterns DP 1  may include a first defective structure D 1  and a second defective structure D 2 . The first normal patterns NP 1  and the first defective patterns DP 1  may be located at the same level layer of a substrate. For example, if a vertical direction is defined as a Z direction, the first normal patterns NP 1  and the first defective patterns DP 1  may be disposed in an X-Y plane at the same height of a substrate on the Z axis. It should be noted that terms such as “pattern” and “structure” may be used interchangeably to refer to certain items, or may be used separately in connection with certain figures to refer to different portions of the figures. 
     The first non-defective structure POR 1  and the second non-defective structure POR 2  may not include an intentional defective structure. The “intentional defective structure” refers to a defective structure intentionally formed by a user to reduce the process window. Thus, an “intentional defective structure” is formed and known to a manufacturer in advance of testing, by design. 
     The first defective structure D 1  and the second defective structure D 2  may each include an intentional defective structure. For example, the first defective structure D 1  may be the result of the user intentionally forming a defective structure next to the first non-defective structure POR 1  to reduce the process window. The second defective structure D 2  may be the result of the user intentionally forming a defective structure next to the second non-defective structure POR 2  to reduce the process window. 
     Referring to  FIG. 5 , a substrate  100  may include a plurality of semiconductor devices (or semiconductor chips)  110 . Each of the semiconductor devices  110  may include an active area  120  in which a circuit, structure or wiring used for operating the semiconductor device  110  is formed and an inactive area  132  in which a circuit, structure or wiring is not formed, or in which no components are connected to any signal-transferring component. As such, components or materials formed in the inactive area  132  do not receive or transmit signals used for operation. For ease of description, a structure such as a circuit, structure or wiring used for operating any of the semiconductor devices  110  will be referred to as an operating pattern OP (see  FIG. 6 ). Structures or patterns that are not used for operating any of the semiconductor devices  110  may be referred to as non-operating patterns. For example, these non-operating patterns may be formed in the inactive area  132  or the cutting area  134 , which is described below. 
     For example, the substrate  100  may include a cutting area  134  for separating the semiconductor devices  110  into single semiconductor devices  110 . That is, the cutting area  134 , also described as a scribe region, is an area where a sawing or other cutting process is performed, and the semiconductor devices  110  included in the substrate  100  may be separated into single semiconductor devices  110  by the sawing or cutting process. 
     The substrate inspection pattern SIP according to the embodiments may be formed in the inactive area  132  and/or the cutting area  134  of the substrate  100 . For ease of description, the inactive area  132  and/or the cutting area  134  will be described as a dummy area  130 . The dummy area  130  may refer to any one of the inactive area  132  and the cutting area  134  or both the inactive area  132  and the cutting area  134 , and as used herein may refer to an area where signals are not transmitted or received or for which any signals transmitted or received are not used for operation of the semiconductor device. 
     According to certain embodiments, the substrate inspection pattern SIP may be formed in the dummy area  130 . For example, the first normal patterns NP 1  and the first defective patterns DP 1  may be disposed in the dummy area  130 . Therefore, the first defective structures D 1  and the second defective structures D 2  may be disposed in the dummy area  130 . Since the first defective structures D 1  and the second defective structures D 2  are disposed in the dummy area  130 , the process window of the dummy area  130 , which may be later set during a testing or inspecting process, may be the second process window  15 . 
     According to certain embodiments, the dummy area  130  does not overlap the active area  120 . For example, the substrate inspection pattern SIP may not be disposed in the active area  120 . Therefore, even if the substrate inspection pattern SIP is formed, the operating pattern OP (see  FIG. 6 ) of each of the semiconductor devices  110  may not include an intentional defective structure. Therefore, the process window of the active area  120 , which may be later set during a testing or inspecting process, may be the first process window  10 . For illustrative purposes, reference will be made to  FIGS. 6 and 7 . 
       FIGS. 6 and 7  are respectively diagrams for explaining an operating pattern OP, a first normal pattern NP 1  and a first defective pattern DP 1  according to embodiments. 
     Referring to  FIGS. 4 through 6 , an operating pattern OP may be disposed in the active area  120  of the substrate  100 . In addition, a substrate inspection pattern SIP may be disposed in the dummy area  130  of the substrate  100 . A first normal pattern NP 1  and a first defective pattern DP 1  may be alternately disposed in the dummy area  130  of the substrate  100 . A normal pattern may include, for example, patterns that have the same shape (e.g., same length and/or width, or same rectangular or “L” shapes), from a plan view, as patterns of the operating pattern OP. A defective pattern may include a shape that is different from the patterns of the operating pattern OP, such as shapes having edges with recesses or protrusions, compared to straight edges of the operating pattern OP, or shapes with different widths or lengths as those of the operating pattern OP. 
     The operating pattern OP may include a first structure ST 1 , a second structure ST 2 , and a third structure ST 3 . The second structure ST 2  is completely separated into parts spaced apart from each other. The first through third structures ST 1  through ST 3  may be structures used for operating a semiconductor device  110 . 
     The first normal pattern NP 1  may include a first non-defective structure POR 1  and a second non-defective structure POR 2 . The shape of the first non-defective structure POR 1  may be the same as the shape of at least a part (A) of the operating pattern OP. The shape of the second non-defective structure POR 2  is the same as the shape of at least a part (A) of the operating pattern OP. In one embodiment, the first non-defective structure POR 1  and the second non-defective structure POR 2  may be structures having the same size and shape and formed of the same material. 
     The first non-defective structure POR 1  may include a first part P 1  and a second part P 2 . The first part P 1  may have a first width W 1 , and the second part P 2  may have a second width W 2 . The second non-defective structure POR 2  may include a third part P 3  and a fourth part P 4 . The third part P 3  may have a third width W 3 , and the fourth part P 4  may have a fourth width W 4 . 
     The first defective pattern DP 1  may include a first defective structure D 1  and a second defective structure D 2 . According to embodiments, the first defective structure D 1  may be obtained by forming an intentional structural defect as compared to the first non-defective structure POR 1 . For example, the defect may include an additional piece of structural material that is not included in the first non-defective structure POR 1 . So, within the same plan-view area-size, the first defective structure D 1  may include all of the pattern included in the first non-defective structure POR 1 , with additional structural elements, such as an additional piece of material AP. The second defective structure D 2  may be obtained by forming an intentional structural defect as compared to the second non-defective structure POR 2 . For example, the defect may include missing pieces of structural material compared to the second non-defective structure POR 2 . So, within the same plan-view area-size, the second defective structure D 2  may include all of the pattern included in the second non-defective structure POR 2 , with the exception of one or more missing pieces of material MP. The first defective structure D 1  may include a fifth part P 5  and a sixth part P 6 . The fifth part P 5  may have a fifth width W 5 , and the sixth part P 6  may have a sixth width W 6 . The second defective structure D 2  may include a seventh part P 7  and an eighth part P 8 . The seventh part P 7  may have a seventh width W 7 , and the eighth part P 8  may have an eighth width W 8 . 
     According to embodiments, the first part P 1  of the first non-defective structure POR 1  may correspond to the fifth part P 5  of the first defective structure D 1 . The first width W 1  of the first part P 1  may be the same as the fifth width W 5  of the fifth part P 5 . In addition, the second part P 2  of the first non-defective structure POR 1  may correspond to the sixth part P 6  of the first defective structure D 1 . The second width W 2  of the second part P 2  may be different from the sixth width W 6  of the sixth part P 6 . For example, the second width W 2  may be greater than the sixth width W 6 . For example, because an extra piece of material AP may be included in the first defective structure D 1 , a top edge of the sixth part P 6  of the first defective structure D 1  may have a shorter width than a top edge of a corresponding part (e.g., second part P 2 ) of the first non-defective structure POR 1 . 
     According to certain embodiments, the third part P 3  of the second non-defective structure POR 2  may correspond to the seventh part P 7  of the second defective structure D 2 . The third width W 3  of the third part P 3  may be the same as the seventh width W 7  of the seventh part P 7 . In addition, the fourth part P 4  of the second non-defective structure POR 2  may correspond to the eighth part P 8  of the second defective structure D 2 . The fourth width W 4  of the fourth part P 4  may be different from the eighth width W 8  of the eighth part P 8 . For example, the fourth width W 4  may be smaller than the eighth width W 8 . Thus, each first structure ST 1  and third structure ST 3  of the second defective structure D 2  may have a recess in an outer edge, such that a width between facing edges of the first structure ST 1  and third structure ST 3  is greater for the eight part P 8  than the width between facing edges of the first structure ST 1  and third structure ST 3  for the corresponding fourth part P 4 . Therefore, the first part P 1  and the third part P 3  of the first normal pattern NP 1  may have the same widths as the fifth part P 5  and the seventh part P 7  of the first defective pattern DP 1 , respectively. In addition, the second part P 2  and the fourth part P 4  of the first normal pattern NP 1  may have different widths from the sixth part P 6  and the eighth part P 8  of the first defective pattern DP 1 , respectively. 
     The first defective structure D 1  and the second defective structure D 2  may be different defective structures. For example, as illustrated in  FIG. 6 , a second structure ST 2  of the first defective structure D 1  may not include completely separated pieces. This will be referred to as an undercut defect for the sake of convenience. In the second defective structure D 2 , a second structure ST 2  may be completely separated, but a first structure ST 1  and a third structure ST 3  may be include recessed edges. This will be referred to as an overcut defect for the sake of convenience. The first, second, and third structures ST 1 , ST 2 , and ST 3  may be, for example, conductive lines formed of a metal material or other conductive material. 
     It should be noted that ordinal numbers such as “first,” “second,” “third,” etc. may be used simply as labels of certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms that are not described using “first,” “second,” etc., in the specification, may still be referred to as “first” or “second” in a claim. In addition, a term that is referenced with a particular ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim). 
     Referring to  FIG. 7 , an operating pattern OP may include a first wiring Ml, a second wiring M 2 , and a third wiring M 3 . 
     A first normal pattern NP 1  may include a first non-defective structure POR 1  and a second non-defective structure POR 2 . The shape of the first non-defective structure POR 1  may be the same as the shape of at least a part (B) of the operating pattern OP. The shape of the second non-defective structure POR 2  is the same as the shape of at least a part (C) of the operating pattern OP. Therefore, the first non-defective structure POR 1  and the second non-defective structure POR 2  may be different-shaped structures. 
     The first non-defective structure POR 1  may include a first part P 1  and a second part P 2 . The first part P 1  may include an edge of the first wiring M 1  and an edge of the second wiring M 2 , and may include a first width W 1  between the edge of the first wiring M 1  and the edge of the second wiring M 2  in a first direction. The second part P 2  may include an edge of the first wiring M 1  and an edge of the second wiring M 2 , and may include a second width W 2  between the edge of the first wiring M 1  and the edge of the second wiring M 2  in the first direction. The edge of the second wiring M 2  in the first part P 1  may be the same edge as the edge of the second wiring M 2  in the second part P 2 . The second non-defective structure POR 2  may include a third part P 3  and a fourth part P 4 . The third part P 3  may be a portion of third wiring M 3  and may have a third width W 3  between opposite edges in the first direction, and the fourth part P 4  may be a portion of third wiring M 3  and may have a fourth width W 4  between opposite edges in a second direction perpendicular to the first direction. 
     A first defective pattern DP 1  may include a first defective structure D 1  and a second defective structure D 2 . According to certain embodiments, the first defective structure D 1  may be obtained by forming an intentional electrical defect compared to the first non-defective structure POR 1 . The second defective structure D 2  may be obtained by forming an intentional electrical defect compared to the second non-defective structure POR 2 . 
     The first defective structure D 1  may include a fifth part P 5  and a sixth part P 6  that respectively correspond to the first part P 1  and second part P 2  of the first non-defective structure POR 1 . The fifth part P 5  may include an edge of the first wiring M 1  and an edge of the second wiring M 2 , and may include a fifth width W 5  between the edge of the first wiring M 1  and the edge of the second wiring M 2  in a first direction, and the sixth part P 6  may include an edge of the first wiring M 1  and an edge of the second wiring M 2 , and may include a sixth width W 6  between the edge of the first wiring M 1  and the edge of the second wiring M 2  in a first direction. The second defective structure D 2  may include a seventh part P 7  and an eighth part P 8  that respectively correspond to the third part P 3  and fourth part P 4  of the second non-defective structure POR 2 . The seventh part P 7  may be a portion of third wiring M 3  and may have a seventh width W 7  between opposite edges in the first direction, and the eighth part P 8  may be a portion of third wiring M 3  and may have an eighth width W 8  between opposite edges in the second direction. 
     According to certain embodiments, the first part P 1  of the first non-defective structure POR 1  may correspond to the fifth part P 5  of the first defective structure D 1 . The first width W 1  of the first part P 1  may be the same as the fifth width W 5  of the fifth part P 5  in the first direction. In addition, the second part P 2  of the first non-defective structure POR 1  may correspond to the sixth part P 6  of the first defective structure D 1 . The second width W 2  of the second part P 2  may be different from the sixth width W 6  of the sixth part P 6  in the first direction. For example, the second width W 2  may be greater than the sixth width W 6 . Thus, the first wiring M 1  in the first defective structure D 1  may have an additional piece of material attached (in a continuous manner) to an end of the structure, compared to the first wiring M 1  of the first non-defective structure POR 1 . 
     According to certain embodiments, the third part P 3  of the second non-defective structure POR 2  may correspond to the seventh part P 7  of the second defective structure D 2 . The third width W 3  of the third part P 3  may be the same as the seventh width W 7  of the seventh part P 7 . In addition, the fourth part P 4  of the second non-defective structure POR 2  may correspond to the eighth part P 8  of the second defective structure D 2 . The fourth width W 4  of the fourth part P 4  may be different from the eighth width W 8  of the eighth part P 8 . For example, the fourth width W 4  may be greater than the eighth width W 8 . Therefore, the first part P 1  and the third part P 3  of the first normal pattern NP 1  may have the same widths as the fifth part P 5  and the seventh part P 7  of the first defective pattern DP 1 , respectively. In addition, the second part P 2  and the fourth part P 4  of the first normal pattern NP 1  may have different widths from the sixth part P 6  and the eighth part P 8  of the first defective pattern DP 1 , respectively. 
     The first defective structure D 1  and the second defective structure D 2  may be different defective structures. For example, as illustrated in  FIG. 7 , in the first defective structure D 1 , a gap between a first wiring M 1  and a second wiring M 2  may be reduced to generate a bridge BR. This will be referred to as a bridge defect for the sake of convenience. In the second defective structure D 2 , the width of a part of a third wiring M 3  may be changed to change the resistance of the third wiring M 3 . This will be referred to as a resistance defect for the sake of convenience. 
     Although the undercut defect, the overcut defect, the bridge defect, and the resistance defect have been described using  FIGS. 6 and 7 , embodiments are not limited to these cases. Those of ordinary skill in the art to which embodiments pertain will be able to implement the technical spirit of the embodiments by selecting and combining various types of defects. 
     The embodiments of  FIGS. 6 and 7  have been described above in connection with different widths of parts of a structure. However, these figures can also be described in a different manner. For example, both of these figures depict a first normal pattern which is disposed in an active area of a semiconductor chip (e.g., operating pattern OP). The first normal pattern has a particular shape (e.g., as depicted in parts (A), (B), or (C) of  FIG. 6 or 7 ). As mentioned further below, the active area includes circuitry for operating the semiconductor chip. The semiconductor chip further includes a first defective pattern (e.g., D 1  or D 2  of  FIG. 6 or 7 ) and a second normal pattern (e.g., POR 1  or POR 2  of  FIG. 6 or 7 ), which are disposed in a dummy area of the semiconductor chip. The dummy area of the semiconductor chip may be an area that does not perform functions for operating the semiconductor chip. The second normal pattern may have the same shape as the first normal pattern, and the first defective pattern may have the same shape as the first normal pattern except for a first defect (e.g., a recess or protrusion in the pattern). For example, the first defective pattern may include a first part and a second part, and the second normal pattern may comprise a third part corresponding to the first part and that matches the first part in shape and size and a fourth part corresponding to the second part. The second part may include the first defect and matches the fourth part in shape and size except for the first defect. For example, the first part in  FIG. 6  may be ST 1  and ST 3  of the first defective pattern (e.g., D 1 ), which matches the corresponding structure (described above as the “third part”) of the second normal pattern (e.g., POR 1  of  FIG. 6 , ST 1  and ST 3 ). As can be seen in  FIG. 6 , for example, if the second part (e.g., ST 2  of the first defective pattern such as D 1 ) and fourth part (e.g., ST 2  of the first non-defective pattern such as POR 2 ) were to be superimposed over each other, e.g., from a top-down view, the second part would include a piece of material (e.g., AP) that is absent from the fourth part and that comprises the first defect. In this manner, the second part including the first defect has an extended portion compared to the fourth part. 
     As can be seen looking back to  FIG. 4 , the first defective pattern may be one of a plurality of identical first defective patterns, and the second normal pattern may be one of a plurality of identical second normal patterns, and the plurality of identical first defective patterns and plurality of second normal patterns are alternately disposed at a first level layer. 
     If the same superimposing were done for the second non-defective pattern (e.g., POR 2 ) and second defective pattern (e. D 2 ), a different defect would be present, which includes material missing from the structure that forms the portions ST 1  and ST 2  of the second detective pattern (e.g., D 2 ). For example, the second defective pattern (e.g., D 2 ) and a third normal pattern (e.g., POR 2 ) may be disposed in the dummy area of the semiconductor chip, and the third normal pattern may have the same shape as the first normal pattern, while the second defective pattern has the same shape as the first normal pattern (and third normal pattern) except for a second defect different from the first defect. For example, the third normal pattern may include a fifth part (e.g., ST 2  of the second non-defective structure POR 2 ) and a sixth part (e.g., ST 1  and ST 3  of the second non-defective structure POR 2 ), and the second defective pattern may include a seventh part (e.g., ST 2  of the second defective structure D 2 ) corresponding to the fifth part and that matches the fifth part in shape and size and an eighth part (e.g., ST 1  and ST 3  of the second defective structure D 2 ) corresponding to the sixth part and that includes the second defect and matches the sixth part in shape and size except for the defect. Here, if the sixth part and eighth part were to be superimposed over each other, the sixth part would include a piece of material that is absent from the eighth part, and that missing material comprises the second defect. 
       FIG. 8  is a flowchart illustrating a method of determining a first defective structure and a second defective structure to be included in a substrate inspection pattern according to certain embodiments. 
     First, a defect determining pattern DDP (see  FIG. 9 ) is designed (operation S 810 ). The defect determining pattern DDP (see  FIG. 9 ) may be a pattern used to determine the size of a defective structure intentionally formed in a substrate inspection pattern SIP. The defect determining pattern DDP may be fabricated on a semiconductor device to be tested or inspected, for example. This will be described in detail with reference to  FIG. 9 . 
       FIG. 9  illustrates a defect determining pattern DDP according to embodiments. 
     Referring to  FIG. 9 , the defect determining pattern DDP may include first normal patterns NP 1 , a second defective pattern DP 2 , a third defective pattern DP 3 , a fourth defective pattern DP 4 , and a fifth defective pattern DP 5 . The type and number of defective patterns can vary depending on embodiments. The first normal patterns NP 1  and the second through fifth defective patterns DP 2  through DP 5  may be formed at the same level layer. 
     The second defective pattern DP 2  may include a (1-1) th  defective structure D 1 ′ and a (2-1) th  defective structure D 2 ′. The third defective pattern DP 3  may include a (1-2) th  defective structure D 1 ″ and a (2-2) th  defective structure D 2 ″. The fourth defective pattern DP 4  may include a (1-3) th  defective structure D 1 ′″ and a (2-3) th  defective structure D 2 ′″. The fifth defective pattern DP 5  may include a (1-4) th  defective structure D 1 ″″ and a (2-4) th  defective structure D 2 ″″. According to embodiments, the (1-1) th  through (2-4) th  defective structures D 1  through D 2 ″″ may be intentionally formed defective structures, with the numerical designators merely being used as a naming convention. 
     The defect determining pattern DDP may include the first normal patterns NP 1  and the intentional defective patterns DP 2  through DP 5  arranged alternately. In other words, the defect determining pattern DDP may include the first normal pattern NP 1 , the second defective pattern DP 2 , the first normal pattern NP 1 , the third defective pattern DP 3 , the first normal pattern NP 1 , the fourth defective pattern DP 4 , the first normal pattern NP 1 , and the fifth defective pattern DP 5  arranged in this order. Therefore, the defect determining pattern DDP may include non-defective structures POR 1  and POR 2  and defective structures D 1 ′, D 2 ′, D 1 ″, D 2 ″, D 1 ′″, D 2 ′″, D 1 ′″ and D 2 ″″ arranged alternately. 
     According to embodiments, the (1-1) th  defective structure D 1 ′, the (1-2) th  defective structure D 1 ′, the (1-3) th  defective structure D 1 ′″ and the (1-4) th  defective structure D 1 ″″ may include undercut defects (e.g., resulting in additional pieces of material compared to the first non-defective structure POR 1  of the normal pattern NP 1 ), and the (2-1) th  defective structure D 2 ′, the (2-2) th  defective structure D 2 ″, the (2-3) th  defective structure D 2 ′″ and the (2-4) th  defective structure D 2 ″″ may include overcut defects (e.g., resulting in removed pieces of material compared to the second non-defective structure POR 2  of the normal pattern NP 1 . According to embodiments, the (1-1) th  defective structure D 1 ′, the (1-2) th  defective structure D 1 ″, the (1-3) th  defective structure D 1 ′″ and the (1-4) th  defective structure D 1 ″″ may be bridge defects, and the (2-1) th  defective structure D 2 ′, the (2-2) th  defective structure D 2 ″, the (2-3) th  defective structure D 2 ′″ and the (2-4) th  defective structure D 2 ″″ may be resistance defects. However, these are only examples used for ease of description, and embodiments are not limited to these examples. Those of ordinary skill in the art to which embodiments pertain will be able to select various types of defects. 
     According to certain embodiments, the (1-1) th  defective structure D 1 ′, the (1-2) th  defective structure D 1 ″, the (1-3) th  defective structure D 1 ′″ and the (1-4) th  defective structure D 1 ′″ may be defects of the same type and different sizes. For example, the (1-1) th  defective structure D 1 ′ may be smaller than the (1-2) th  defective structure D 1 ″. For example, the (1-2) th  defective structure D 1 ″ may be smaller than the (1-3) th  defective structure D 1 ′″. For example, the (1-3) th  defective structure D 1 ′″ may be smaller than the (1-4) th  defective structure D 1 ″″. Using  FIG. 6 or 7  as examples, the (1-1) th  defective structure D 1 ′, the (1-2) th  defective structure D 1 ″, the (1-3) th  defective structure D 1 ′″ and the (1-4) th  defective structure D 1 ″″ may be different in the sixth width W 6  of the sixth part P 6 . 
     Likewise, the (2-1) th  defective structure D 2 ′, the (2-2) th  defective structure D 2 ″, the (2-3) th  defective structure D 2 ′″ and the (2-4) th  defective structure D 2 ″″ may be defects of the same type and different sizes. Using  FIG. 6 or 7  as examples, the (2-1) th  defective structure D 2 ′, the (2-2) th  defective structure D 2 ″, the (2-3) th  defective structure D 2 ′″ and the (2-4) th  defective structure D 2 ″″ may be different in the eighth width W 8  of the eighth part P 8 . 
     Referring again to  FIG. 8 , the defect determining pattern DDP may be inspected for defects by using substrate inspection equipment (operation S 820 ). The substrate inspection equipment according to embodiments may be first equipment for measuring structural defects and/or second equipment for measuring electrical defects. The substrate inspection equipment may include various electrical and mechanical parts, such as computer hardware and software for receiving user input, controlling mechanical equipment, performing analysis to determine defects, etc. The equipment may also include various optical and measurement components for performing measurements used in the analysis. Methods of measuring defects using the first equipment and the second equipment will now be described with reference to  FIGS. 10 through 12 . 
       FIG. 10  is a diagram for explaining a method of inspecting a defect determining pattern for defects by using the first equipment for measuring structural defects according to certain embodiments. 
     Referring to  FIG. 10 , the defect determining pattern DDP may be inspected for structural defects by using the first equipment. The first equipment may inspect whether the defect determining pattern DDP has a structural defect by using the average of measured values of the defect determining pattern DDP. For example, the first equipment may scan the defect determining pattern DDP to detect an image of the first normal pattern NP 1 , an image of the second defective pattern DP 2 , an image of the first normal pattern NP 1 , an image of the third defective pattern DP 3 , an image of the first normal pattern NP 1 , an image of the fourth defective pattern DP 4 , an image of the first normal pattern NP 1 , and an image of the fifth defective pattern DP 5  and generate image data of each first normal pattern NP 1  and image data of each of the second through fifth defective patterns DP 2  through DP 5 . Then, the first equipment may generate average image data by taking the average of the image data of the defect determining pattern DDP. For example, regions or pixels within an image scan for all scanned images that are in common across all of the images may be included in the average image data to have a specific weighting (e.g., full weight), and regions that differ may be averaged across all of the images to have a different weight (e.g., less than the full weight). Next, the first equipment may determine a difference value between the average image data and the image data of each first normal pattern NP 1  as a measured value of each first normal pattern NP 1  (e.g., by comparing the weight of each region or pixel of the average image data to the regions or pixels that are known to be in each first normal pattern NP 1 ). Likewise, the first equipment may determine a difference value between the average image data and the image data of each of the second through fifth defective patterns DP 2  through DP 5  as a measured value of each of the second through fifth defective patterns DP 2  through DP 5 . 
     According to embodiments, when the first equipment is used, the (1-1) th  defective structure D 1 ′, the (1-2) th  defective structure D 1 ′, the (1-3) th  defective structure D 1 ′″ and the (1-4) th  defective structure D 1 ″″ may include undercut defects which are different in the sixth width W 6  of the sixth part P 6 . In addition, the (2-1) th  defective structure D 2 ′, the (2-2) th  defective structure D 2 ″, the (2-3) th  defective structure D 2 ′″ and the (2-4) th  defective structure D 2 ″″ may include overcut defects which are different in the eighth width W 8  of the eighth part P 8 . 
       FIGS. 11 and 12  are respectively diagrams for explaining methods of inspecting a defect determining pattern for defects by using the second equipment for measuring electrical defects according to embodiments. 
     Referring to  FIG. 11 , a first pad PAD 1  and a second pad PAD 2  may be connected to the second defective pattern DP 2 . Likewise, a third pad PAD 3  and a fourth pad PAD 4  may be connected to the third defective pattern DP 3 , a fifth pad PAD 5  and a sixth pad PAD 6  may be connected to the fourth defective pattern DP 4 , and a seventh pad PAD 7  and an eighth pad PAD 8  may be connected to the fifth defect pattern DP 5 . 
     According to some embodiments, using the second equipment, a voltage or a current may be applied to the first pad PAD 1 , and a voltage or current output from the second pad PAD 2  or a time when the voltage or current is output may be detected. Here, the voltage or current output from the second pad PAD 2  or the time when the voltage or current is output may be determined as a measured value of the second defective pattern DP 2 . Likewise, using the second equipment, a voltage or a current may be applied to each of the third pad PAD 3 , the fifth pad PAD 5  and the seventh pad PAD 7 , and voltages or currents output from the fourth pad PAD 4 , the sixth pad PAD 6  and the eighth pad PAD 8  or times when the voltages or currents are output may be determined as measured values of the third defective pattern DP 3 , the fourth defective pattern DP 4  and the fifth defective pattern DP 5 , respectively. 
     Similarly, referring to  FIG. 12 , a first pad PAD 1  may be commonly connected to the second defective pattern DP 2 , the third defective pattern DP 3 , the fourth defective pattern DP 4 , and the fifth defective pattern DP 5 . Here, a second pad PAD 2 , a fourth pad PAD 4 , a sixth pad PAD 6 , and an eight pad PAD 8  may be connected to the second through fifth defective patterns DP 2  through DP 5 , respectively. 
     According to embodiments, using the second equipment, a voltage or a current may be commonly applied to the first pad PAD 1 , and voltages or currents output from the second pad PAD 2 , the fourth pad PAD 4 , the sixth pad PAD 6  and the eighth pad PAD 8  or times when the voltages or currents are output may be determined as measured values of the second defective pattern DP 2 , the third defective pattern DP 3 , the fourth defective pattern DP 4  and the fifth defective pattern DP 5 , respectively. 
     According to embodiments, when the second equipment is used, the (1-1) th  defective structure D 1 ′, the (1-2) th  defective structure D 1 ″, the (1-3) th  defective structure D 1 ′″ and the (1-4) th  defective structure D 1 ″″ may be bridge defects which are different in the sixth width W 6  of the sixth part P 6 . In addition, the (2-1) th  defective structure D 2 ′, the (2-2) th  defective structure D 2 ″, the (2-3) th  defective structure D 2 ′″ and the (2-4) th  defective structure D 2 ″″ may be resistance defects which are different in the eighth width W 8  of the eighth part P 8 . 
     Referring again to  FIG. 8 , a pattern to be used in a substrate inspection pattern SIP may be determined based on the measured values of the defect determining pattern DDP obtained using the first equipment and/or the second equipment, and the substrate inspection pattern SIP may be designed (operation S 830 ). For illustrative purposes, reference will be made to  FIG. 13 . 
       FIG. 13  is a diagram for explaining a method of determining a pattern to be used in a substrate inspection pattern according to embodiments. It should be noted that a substrate inspection pattern is included on a substrate or wafer actually being manufactured into semiconductor devices to be separated and included in end products. According to certain embodiments, a defect determining pattern DDP, on the other hand, is included on a substrate not being manufactured into a semiconductor device, but which is used to determine which substrate inspection patterns should be included on a substrate/wafer actually being manufactured into semiconductor devices to be separated and included in end products. A semiconductor device as described herein may be in the form of a semiconductor chip or semiconductor package, for example, and may include a semiconductor chip formed and singulated from a wafer, as described above. 
     Referring to  FIG. 13 , the result of measuring each pattern of the defect determining pattern DDP using the first equipment and/or the second equipment may be determined as pass or fail. For example, one or more measured values, or measured value differences with normal patterns, of each of a plurality of defective patterns DP 2 , DP 3 , DP 4  and DP 5  included in the defect determining pattern DDP (e.g., an average image value, or voltage, current, or timing value) may be compared with one or more respective predetermined reference values to determine pass or fail. 
     According to certain embodiments, the measurement result of each defective pattern included in the defect determining pattern DDP may be analyzed, and a defective pattern determined last as pass may be determined as a first defective pattern DP 1  to be used in the substrate inspection pattern SIP. For example, when the measurement result of the second defective pattern DP 2  is pass, the measurement result of the third defective pattern DP 3  is pass, the measurement result of the fourth defective pattern DP 4  is fail and the measurement result of the fifth defective pattern DP 5  is fail, the third defective pattern DP 3  may be determined as the first defective pattern DP 1 . In some embodiments, the sizes of the different defective patterns are analyzed in order from smaller to larger, or larger to smaller, to help in this determination. 
     According to certain embodiments, since the first defective pattern DP 1 , also described as a selected defective pattern, is a defective pattern whose measurement result is pass, the measurement result of the substrate inspection pattern SIP may be determined as pass when the process center is located at the first point F 1  (see  FIG. 3 ). However, since an area (i.e., the dummy area  130 ) in which the first defective pattern DP 1  is formed has a small process margin (that is, a narrow process window), the process window may be reduced from the first process window  10  to the second process window  15 . Therefore, if the process center is changed to the second point F 2  (see  FIG. 2 ), the measurement result of the substrate inspection pattern SIP may be determined as fail. 
       FIG. 14  illustrates a substrate inspection pattern SIP according to embodiments.  FIG. 15  illustrates a defect determining pattern DDP according to embodiments.  FIG. 16  illustrates a method of determining an inspection pattern to be used in a substrate inspection pattern according to embodiments. For ease of description, a description of elements and features identical or similar to those described above will be omitted or given briefly. 
     Referring to  FIG. 14 , the substrate inspection pattern SIP may include inspection patterns IP arranged successively. The substrate inspection pattern SIP may be disposed in the dummy area  130  of the substrate  100 . 
     Each of the inspection patterns IP may include one or more first defective patterns DP 1  and a plurality of first normal patterns NP 1 . The first defective patterns DP 1  and the first normal patterns NP 1  may be located at the same level layer of the semiconductor device being manufactured. 
     Referring to  FIG. 15 , the defect determining pattern DDP may include a first determining pattern DTP 1 , a second determining pattern DTP 2 , a third determining pattern DTP 3 , and a fourth determining pattern DTP 4 . Although the defect determining pattern DDP includes four determining patterns in the drawing, embodiments are not limited to this case. The number of determining patterns included in the defect determining pattern DDP may vary as needed. 
     The first determining pattern DTP 1  may include at least one second defective pattern DP 2  and a plurality of first normal patterns NP 1 . The second determining pattern DTP 2  may include at least one third defective pattern DP 3  and a plurality of first normal patterns NP 1 . The third determining pattern DTP 3  may include at least one fourth defective pattern DP 4  and a plurality of first normal patterns NP 1 . The fourth determining pattern DTP 4  may include at least one fifth defective pattern DP 5  and a plurality of first normal patterns NP 1 . 
     Referring to  FIG. 16 , in a method similar to the above-described method, a determining pattern measured last as pass is determined as an inspection pattern IP by using defect measurement results of the defect terming pattern DDP. For example, when the defect measurement result of the first determining pattern DTP 1  is pass, the defect measurement result of the second determining pattern DTP 2  is pass, the defect measurement result of the third determining pattern DTP 3  is fail and the defect measurement result of the fourth determining pattern DTP 4  is fail, the second determining pattern DTP 2  is determined as the inspection pattern IP. 
       FIG. 17  is a flowchart illustrating a substrate inspection method according to embodiments. 
     Referring to  FIG. 17 , an operating pattern OP may be formed on an active area  120  of a substrate  100 , and a substrate inspection pattern SIP may be formed on a dummy area  130  of the substrate  100  (operation S 1710 ). The active area  120  may be an area that is used during normal operations of a semiconductor device formed from the substrate, and the dummy area  130  may be an area that is not used during normal operation of the semiconductor device. For example, the active area  120  may include circuitry used for operating the semiconductor device (e.g., a semiconductor chip), such as for supplying signals or voltage to portions of the semiconductor device that are used to store and retrieve, or to process data. The dummy area  130  may be an area that does not include such circuitry and/or is not used for any of these types of operating functions. 
     The substrate  100  is inspected for defects by using substrate inspection equipment (operation S 1720 ). Then, the defect measurement result of the substrate  100  is analyzed (operation S 1730 ). It is determined whether the defect measurement result of the active area  120  of the substrate  100  indicates pass (operation S 1740 ). 
     If the defect measurement result of the active area  120  of the substrate  100  indicates pass, it is determined whether the defect measurement result of the dummy area  130  of the substrate  100  indicates pass (operation S 1750 ). 
     If the defect measurement result of the active area  120  of the substrate  100  indicates pass and the defect measurement result of the dummy area  130  of the substrate  100  indicates pass, it is determined that a corresponding process is without a defect and without a change beyond a threshold amount in a process center (operation S 1760 ). For example, a manufacturing computer system can be programmed to automatically proceed with manufacturing operations without issuing any notification when it is determined that the process is without defect. 
     If the defect measurement result of the active area  120  of the substrate  100  indicates pass and the defect measurement result of the dummy area  130  of the substrate  100  indicates fail, it is determined that the corresponding process is without a defect, but its process center has been changed more than a threshold amount (operation S 1770 ). For example, a manufacturing computer system can be programmed to automatically issue a notification when it is determined that the process center has changed in this manner. As a result, a user may recognize the change in the process center and initialize the process center by modifying a process recipe or changing hardware and/or software of process equipment. 
     If the defect measurement result of the active area  120  of the substrate  100  indicates fail, a semiconductor substrate (or semiconductor device) that has gone through the corresponding process is determined to be defective (operation S 1780 ). 
       FIG. 18  illustrates first through third substrate inspection patterns SIP 1  through SIP 3  according to embodiments. 
     Referring to  FIG. 18 , a plurality of substrate inspection patterns SIP 1  through SIP 3  may be stacked vertically (in the Z direction) in a dummy area  130  of a substrate  100 . For example, the first substrate inspection pattern SIP 1  may be formed at a first level layer L 1  in the dummy area  130  of the substrate  100 . In addition, the second substrate inspection pattern SIP 2  may be formed at a second level layer L 2  in the dummy area  130  of the substrate  100 . In addition, the third substrate inspection pattern SIP 3  may be formed at a third level layer L 3  in the dummy area  130  of the substrate  100 . In other words, in the dummy area  130  of the substrate  100 , the second substrate inspection pattern SIP 2  may be formed on the first substrate inspection pattern SIP 1 , and the third substrate inspection pattern SIP 3  may be formed on the second substrate inspection pattern SIP 2 . 
     The first substrate inspection pattern SIP 1 , the second substrate inspection pattern SIP 2 , and the third substrate inspection pattern SIP 3  according to this embodiment may include different defects, or at least some of the first through third substrate inspection patterns SIP 1  through SIP 3  may include the same defect. Therefore, at least some of the first through third substrate inspection patterns SIP 1  through SIP 3  may be measured using different substrate inspection equipment. For example, the first substrate inspection pattern SIP 1  and the second substrate inspection pattern SIP 2  may be measured for defects using first equipment, and the third substrate inspection pattern SIP 3  may be measured for defects using second equipment. However, this is only an example, and embodiments are not limited to this case. According to embodiments, since a plurality of substrate inspection patterns SIP 1  through SIP 3  can be stacked in the dummy area  130 , there is no need to form the substrate inspection patterns SIP 1  through SIP 3  in different areas. This can increase the integration density of semiconductor devices  110  and reduce cost. 
     Although the method of detecting a change in the process center using a substrate inspection pattern SIP according to embodiments has been described above, embodiments are not limited to this method. Since the substrate inspection pattern SIP includes a part in which a defective structure is intentionally formed, the type, size, shape and position of the defective structure included in the substrate inspection pattern SIP can be identified in advance. Since the type, size, shape and position of the defective structure are already known, the substrate inspection pattern SIP can be used in various fields. 
     According to embodiments, a defect of the substrate inspection pattern SIP may be detected using substrate inspection equipment, and the type, size, shape and position of the detected defect structure may be compared with those of the known defective structure to evaluate the performance of the substrate inspection equipment. 
     According to embodiments, a substrate inspection pattern SIP may be formed to include intentionally formed defective structures by using an extreme ultraviolet (EUV) exposure device. Here, the intentionally formed defective structures may correspond to the positions of slits of the EUV exposure device, respectively. Optical proximity correction (OPC) may be performed using the type, size, shape and position of a defective structure corresponding to the position of each slit. 
     According to embodiments, a substrate inspection pattern SIP may be formed using first photoresist, and a substrate inspection pattern SIP may be formed using a second photoresist. Here, the size, shape and position of a defective structure included in the substrate inspection pattern SIP formed using the first photoresist may be compared with those of a defective structure included in the substrate inspection pattern SIP formed using the second photoresist. In doing so, it is possible to identify material characteristics of the first photoresist and the second photoresist. 
     In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred example embodiments without departing from the spirit and scope of the present disclosure. Therefore, the disclosed preferred example embodiments of the present disclosure are used in a generic and descriptive sense only and not for purposes of limitation.