Patent Publication Number: US-2022224336-A1

Title: Digital logic compatible inputs in compound semiconductor circuits

Description:
FIELD OF THE INVENTION 
     The invention relates to compound semiconductor circuits generally and, more particularly, to a method and/or apparatus for implementing digital logic compatible inputs in compound semiconductor based integrated circuits. 
     BACKGROUND 
     Digital logic circuits are designed to input and output two types of signals: a logic “1” or HIGH and a logic “0” or LOW. The HIGH state is typically represented by the full supply voltage and the LOW state is typically represented by a circuit ground potential. However, real digital circuits cannot output ideal voltage levels, and are designed to accept substantial deviation from the ideal values. Conventional compound semiconductor integrated circuits (ICs), such as gallium arsenide (GaAs) based ICs, are typically paired with silicon ICs to facilitate digital control of the compound semiconductor ICs. 
     It would be desirable to implement digital logic compatible inputs in compound semiconductor based integrated circuits. 
     SUMMARY 
     The invention concerns an apparatus including a device comprising a semiconductor junction configured to generate a reference voltage, a voltage divider circuit, a comparator circuit, and a first output circuit. The voltage divider circuit may be configured to generate a first predetermined threshold voltage in response to the reference voltage. The comparator circuit may be configured to generate a first intermediate signal in response to a comparison of the first predetermined threshold voltage and an input signal. The first output circuit may be configured to generate a first output signal in response to the first intermediate signal. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       Embodiments of the invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a diagram of a system illustrating a context of the invention; 
         FIG. 2  is a diagram illustrating a transfer function in accordance with an example embodiment of the invention; 
         FIG. 3  is a diagram illustrating an integrated circuit context in accordance with an example embodiment of the invention; 
         FIG. 4  is a diagram illustrating an example single-bit input buffer circuit in accordance with an example embodiment of the invention; 
         FIG. 5  is a diagram illustrating an example implementation of the input buffer circuit of  FIG. 4 ; 
         FIG. 6  is a diagram illustrating an example multi-bit input buffer circuit in accordance with another example embodiment of the invention; and 
         FIG. 7  is a diagram illustrating an integrated circuit in accordance with another example embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Embodiments of the present invention include providing digital logic compatible inputs in compound semiconductor based integrated circuits that may (i) provide input threshold voltage level(s) that is(are) stable over variations in process, voltage, and/or temperature (PVT), (ii) allow CMOS logic level control of III-V compound semiconductor circuits, (iii) be implemented using gallium arsenide (GaAs) process technology, (iv) be utilized to implement circuits that transition to predefined voltage levels at predefined thresholds, (v) utilize a semiconductor junction as a bandgap reference, and/or (vi) be implemented as one or more integrated circuits. 
     Referring to  FIG. 1 , a block diagram of a system  80  is shown illustrating an example context of the invention. The system (or module or circuit or apparatus)  80  may implement, for example, a communication system. In some embodiments, the system  80  may implement a wireless communication system. In an example, the system  80  may form part of a communications link. In some embodiments, the communications link may be part of a fifth generation (5G) wireless communications system (e.g., for which a standard is currently under development by the Next Generation Mobile Networks (NGMN) Alliance). In other embodiments, the communications link may be part of systems including, but not limited to, a fourth generation (4G) wireless communications system (e.g., International Mobile Telecommunications-Advanced (IMT-A) standard published by the International Telecommunications Unit Radiocommunication Sector (ITU-R)), a satellite communication (SATCOM) system, and/or a point-to-point communications system such as common data link (CDL). However, other communications standards may be implemented to meet the design criteria of a particular application. In an example, the system  80  may be configured to operate at common wireless radio frequencies, millimeter-wave frequencies, and/or microwave frequencies. In an example, system may be configured to facilitate communication with and/or between a plurality of communications devices (or terminals). In an example, the communications devices may include, but are not limited to, cellular telephones, mobile devices, tablets, and internet-of-things (IoT) equipment. 
     In various embodiments, the system  80  may comprise a block (or circuit or module)  90  and a block (or circuit or module)  100 . In an example, the circuit  90  may implement a digital control circuit portion of the system  80 . In an example, the circuit  100  may implement a variety of circuit elements of a communication system. In various embodiments, the circuit  100  may be implemented using a III-V compound semiconductor technology (e.g., GaAs, GaN, InP, InGaP, SiC, etc.). In an example, the circuit  90  may be configured to generate a number of signals (e.g., CTRL 0 -CTRLN). In an example, the signals CTRL 0 -CTRLN may be implemented as digital control signals. In an example, each of the signals CTRL 0 -CTRLN may have a first state (e.g., a logic 0 or LOW) and a second state (e.g., a logic 1 or HIGH). Each of the first and the second states may be represented by a predefined voltage level or voltage range. In an example, the signals CTRL 0 -CTRLN may be implemented having CMOS logic compliant levels. In an example, the circuit  100  may comprise a variety of high frequency (e.g., radio, millimeter-wave, microwave, etc.) circuits including, but not limited to, power amplifier (PA) stages, variable gain amplifier (VGA) stages, variable phase shift stages, filters, and switches. In an example, respective bias, phase, and/or gain values of the circuit  100  may be programmed in response to the signals CTRL 0 -CTRLN. 
     In an example, the circuit  90  may implement a control circuit. In various embodiments, the circuit  90  may be implemented using one or more of an application specific integrated circuit (ASIC), controller, microprocessor, or circuitry configured accordingly. The circuit  90  is generally operational to control the operations of the of the system  80  and the circuit  100 . In some embodiments, the circuit  90  may determine setting, configuration, and/or operating values used in the circuit  100 . In various embodiments, the circuit  90  may be implemented as one or more integrated circuits. 
     Referring to  FIG. 2 , a diagram is shown illustrating a control signal transfer function in accordance with an embodiment of the invention. In an example, the circuit  100  may be configured to receive the number of signals (e.g., CTRL 0 -CTRLN). In an example, the signals CTRL 0 -CTRLN may be implemented as digital control signals. Each of the signals CTRL 0 -CTRLN may have a first state (e.g., a logic 0 or LOW) and a second state (e.g., a logic 1 or HIGH). The first state may be represented by a first predefined threshold (e.g., TH 1 ). The second state may be represented by a second predefined threshold (e.g., TH 2 ). When the control signals CTRL 0 -CTRLN have a voltage level in a range from zero (ground potential) up to and including TH 1 , the signals CTRL 0 -CTRLN are considered to be a logic 0 or LOW. When the control signals CTRL 0 -CTRLN have a voltage level in a range from TH 2  up to and including VDD, the signals CTRL 0 -CTRLN are considered to be a logic 1 or HIGH. In an example, the signals CTRL 0 -CTRLN may be implemented having CMOS logic compliant levels, where VDD is 5V, TH 1  is 1.5V, and TH 2  is 3.5V. However, other signal specifications may be implemented accordingly to meet design criteria of a particular implementation. 
     In general, gate circuit interpretations for signals having a voltage level between the thresholds TH 1  and TH 2  are not guaranteed. In an example, a threshold (e.g., TH 3 ) may be defined in order to allow interpretation of signals that fall slightly out of the specified ranges. In an embodiment implement the TH 3  threshold, when a signal has a voltage level below TH 3 , the signal may be considered to be a logic 0 or LOW, and when the signal has a voltage level above TH 3 , the signal may be considered to be a logic 1 or HIGH. 
     Referring to  FIG. 3 , a diagram of a circuit  100  is shown illustrating an integrated circuit context in accordance with an example embodiment of the invention. In various embodiments, the circuit  100  may comprise a III-V compound semiconductor integrated circuit. In an example, the circuit  100  may be implemented using process technology including, but not limited to, gallium arsenide (GaAs), indium gallium phosphide (InGaP), indium phosphide (inP), gallium nitride (GaN), and silicon carbide (SiC). In various embodiments, the circuit  100  may be configured to work with standard digital logic (e.g., CMOS, TTL, etc.) signals. In an example, compatibility with standard digital logic control signals (e.g., CMOS, etc.) generally facilitates easy integration of high power, high speed III-V compound semiconductor integrated circuits with CMOS control circuits. The circuit  100  is generally configured to allow direct application of externally generated digital logic level (e.g., CMOS, etc.) control signals to input pins (or pads) of the circuit  100 . The circuit  100  is generally configured to generate internal control signals in response to externally generated digital logic level (e.g., CMOS, etc.) control signals. 
     In various embodiments, the circuit  100  may comprise a block (or circuit)  102 , a block (or circuit)  104 , a block (or circuit)  106 , and or any combination or number thereof. In an example, the circuit  102  may implement a single-bit input buffer circuit. In an example, the circuit  104  may implement internal (core) circuitry of the circuit  100 . In an example, the circuit  106  may implement a multi-bit input buffer circuit. The circuit  102  and/or the circuit  106  are generally configured to provide a digital control interface between the circuit  104  and external circuitry connected to the circuit  100 . In various embodiments, the circuit  102  may have an input that receives an external control signal (e.g., CTRL_IN) and one or more outputs that present one or more internal control signals to the circuit  104 . In an example, the input of the circuit  102  may be configured to receive the external signal via a connection (e.g., a pin, a pad, a bump, or other method of electrically connecting the circuit  100  to external circuitry) to an external source. In various embodiments, the external signal may be characterized as having at least two logic states (e.g., a logic LOW and a logic HIGH) represented by predefined voltage levels (e.g., CMOS levels, etc.). The circuit  102  may be configured to generate the internal control signal(s) responsive to a particular state of the input signal CTRL_IN. 
     In various embodiments, the circuit  106  may have a number (e.g., n) of inputs that receive a corresponding number of external control signals (e.g., IN_ 0 -IN_N) and a corresponding number (e.g., n,  2   n ,  2   n , etc.) of outputs that present internal control signals to the circuit  104 . In an example, the inputs of the circuit  106  may be configured to receive the external signals via respective connections (e.g., pins, pads, bumps, or other method of electrically connecting the circuit  100  to external circuitry) to an external source or sources. In various embodiments, the external signals may be characterized as having at least two logic states (e.g., a logic LOW and a logic HIGH) represented by predefined voltage levels (e.g., CMOS levels, etc.). The circuit  106  may be configured to generate the internal control signals responsive to particular states of the input signals IN_ 0 -IN_N. 
     In an example, the circuit  104  may comprise a variety of high frequency, (e.g., radio, millimeter-wave, microwave, etc.) circuits including, but not limited to, power amplifier (PA) stages, variable gain amplifier (VGA) stages, variable phase shift stages, filters, and switches. In an example, respective bias, phase, and/or gain values of the circuit  100  may be programmed in response to the internal control signals received from the circuit  102  and/or the circuit  106 . In another example, signal paths may be controlled by one or more switches within the circuit  104  to vary signal routs in response to one or more of the internal control signals. 
     Referring to  FIG. 4 , a block diagram of the circuit  102  is shown illustrating an example implementation of a single-bit input buffer circuit in accordance with an example embodiment of the invention. In an example, the circuit  102  may comprise a block (or circuit)  110 , a block (or circuit)  112 , a block (or circuit)  114 , and a block (or circuit)  116 . The block  110  may implement an input comparator circuit. The block  112  may implement a reference generator circuit. The blocks  114  and  116  may implement output driver circuits. In an example, the circuit  110  may have a first input that may receive the signal CTRL_IN, a second input that may receive a predefined threshold voltage (e.g., THLD), and one or more outputs that may present a respective intermediate signal. The circuit  110  may be configured to generate the one or more intermediate signals in response to the signals CTRL_IN and THLD. In an example, a value of the one or more intermediate signals may be based upon a comparison between a voltage level of the signal CTRL_IN and a voltage level of the signal THLD. 
     The circuit  112  may be configured to generate the predefined threshold voltage THLD based upon a substantially stable characteristic of the III-V compound semiconductor material. In an example, the circuit  112  may be implemented as a bandgap reference voltage generator. In an example, the circuit  112  may use a junction of the compound semiconductor to produce a reference voltage level that is substantially stable over process, voltage, and temperature (PVT) corners of the particular semiconductor technology. In an example, the circuit  112  may be configured to generate the signal THLD as the threshold value TH 3  in  FIG. 2 . 
     Each of the circuits  114  and  116  may receive a respective intermediate signal from the circuit  110 . The circuit  114  may be configured to generate a respective output signal (e.g., OUT_ 1 ) in response to the respective intermediate signal received from the circuit  110 . The circuit  116  may be configured to generate a respective output signal (e.g., OUT_ 2 ) in response to the respective intermediate signal received from the circuit  110 . The signals OUT_ 1  and OUT_ 2  are generally configured to control respective portions of the core circuitry  104 . 
     Referring to  FIG. 5 , a schematic diagram is shown illustrating an example implementation of the single-bit input buffer circuit  102  of  FIG. 4 . In an example, the circuit  102  may implement the circuits  110 - 116  using a number of transistors Q 1 -Q 6 , a number of resistors R 1 -R 13 , and a semiconductor junction device  118 . In an example, the circuit  110  may comprise transistors Q 1 -Q 4  and resistors R 1 -R 4 . The resistor R 1  may be connected between a positive supply voltage (e.g., VDD) and a drain terminal of the transistor Q 1 . The drain terminal of the transistor Q 1  may be connected to a gate terminal of the transistor Q 1  and a gate terminal of the transistor Q 2 . A source terminal of the transistor Q 1  and a source terminal of the transistor Q 2  may be connected to a circuit ground potential (e.g., GND). A drain terminal of the transistor Q 2  may be connected to source terminals of the transistors Q 3  and Q 4 . The resistor R 2  may be configured to couple the signal CTRL_IN to a gate terminal of the transistor Q 3 . The resistor R 3  may be connected between the positive supply voltage VDD and a drain terminal of the transistor Q 3 . The resistor R 4  may be connected between the positive supply voltage VDD and a drain terminal of the transistor Q 4 . 
     The transistors Q 1  is generally configured to generated a reference current. The reference current is generally mirrored by the transistor Q 2  for use in a differential comparator formed by the transistors Q 3  and Q 4 . The differential comparator formed by the transistor Q 3  and Q 4  compares the voltage level of the signal CTRL_IN presented to the gate of the transistor Q 3  to a reference voltage level presented to a gate of the transistor Q 4 . Intermediate signals representative of the comparison are presented at the respective source terminals of the transistor Q 3  and Q 4 . 
     In an example, the reference generator circuit  112  may be implemented as a bandgap reference. In an example, the resistor R 5  may be connected between the positive supply voltage VDD and first terminal of the semiconductor junction device  118 . A second terminal of the semiconductor junction device  118  may be connected to the ground potential GND. The semiconductor junction device  118  is generally configured to present a bandgap voltage of the particular compound semiconductor material (e.g., 1.2V for GaAs). In an example, the semiconductor junction device  118  may be implemented as a diode junction, transistor junction, parasitic junction, or other junction type that may be produced in a particular semiconductor technology. 
     In various embodiments, the voltage presented at the first terminal of the semiconductor junction device  118  is presented to a voltage divider formed by the resistors R 6  and R 7 . In an example, the first terminal of the semiconductor junction device  118  is connected to a first terminal of the resistor R 6 . A second terminal of the resistor R 6  is connected to a first terminal of the resistor R 7  and the gate terminal of the transistor Q 4 . A second terminal of the resistor R 7  is connected to the ground potential GND. The values of the resistors R 6  and R 7  are generally selected to produce a desired threshold level (e.g., TH 3 ). 
     In an example, the output driver circuit  114  may be implemented with the transistor Q 5  and the resistors R 8 -R 10 . The resistor R 8  may be connected between the positive supply voltage VDD and a drain terminal of the transistor Q 5 . A source terminal of the transistor Q 5  may be connected to the ground potential GND. A gate terminal of the transistor Q 5  may be connected to a first terminal of the resistor R 9  and a first terminal of the resistor R 10 . A second terminal of the resistor R 9  may be connected to the drain terminal of the transistor Q 4 . A second terminal of the resistor R 9  may be connected to the circuit ground potential GND. The output signal OUT  1  may be presented at the drain terminal of the transistor Q 5 . The values of the resistors R 9  and R 10  are generally selected to produce a desired switch point for the transistor Q 5 . 
     In an example, the output driver circuit  116  may be implemented with the transistor Q 6  and the resistors R 11 -R 13 . The resistor R 11  may be connected between the positive supply voltage VDD and a drain terminal of the transistor Q 6 . A source terminal of the transistor Q 6  may be connected to the ground potential GND. A gate terminal of the transistor Q 6  may be connected to a first terminal of the resistor R 12  and a first terminal of the resistor R 11 . A second terminal of the resistor R 12  may be connected to the drain terminal of the transistor Q 3 . A second terminal of the resistor R 13  may be connected to the circuit ground potential GND. The output signal OUT_ 2  may be presented at the drain terminal of the transistor Q 6 . The values of the resistors R 12  and R 13  are generally selected to produce a desired switch point for the transistor Q 6 . 
     Referring to  FIG. 6 , a block diagram is shown illustrating an example implementation of the multi-bit input buffer circuit  106  of  FIG. 3 . In an example, the circuit  106  may comprise a number of blocks (or circuits)  120   a - 120   n , a block (or circuit)  122 , and a number of blocks (or circuits)  124   a - 124   n . The blocks  120   a - 120   n  may implement input comparator circuits. The block  112  may implement a reference generator circuit. The blocks  124   a - 124   n  may implement output driver circuits. In an example, each of the circuits  120   a - 120   n  may have a first input that may receive a respective one of the signals IN_ 0 -IN_N, a second input that may receive a predefined threshold voltage (e.g., THLD), and one or more outputs that may present a respective intermediate signal. The circuits  120   a - 120   n  may be configured to generate the one or more intermediate signals in response to the respective one of the signals IN_ 0 -IN_N and the signal THLD. In an example, a value of the one or more intermediate signals may be based upon a comparison between a voltage level of the respective one of the signals IN_ 0 -IN_N and a voltage level of the signal THLD. 
     The circuit  122  may be configured to generate the predefined threshold voltage THLD based upon a substantially stable junction potential characteristic of the III-V compound semiconductor material. In an example, the circuit  122  may be implemented as a bandgap reference voltage generator. In an example, the circuit  122  may use a junction device of the compound semiconductor to produce a reference voltage level that is substantially stable over process, voltage, and temperature (PVT) corners of the particular semiconductor technology. In an example, the circuit  122  may be configured to generate the signal THLD as the threshold value TH 3  in  FIG. 2 . 
     Each of the circuits  124   a - 124   n  may receive a respective intermediate signal from a corresponding circuit  120   a - 120   n . The circuits  124   a - 124   n  may be configured to generate respective output signals (e.g., OUT_ 0 -OUT_N) in response to the respective intermediate signal received from the corresponding circuit  120   a - 120   n . In some embodiments, a number of blocks (or circuits)  126   a - 126   n  may be implemented similarly to the circuit  116  of  FIG. 4  and configured to generate a second set of respective output signals in response to a respective intermediate signal received from the circuits  120   a - 120   n . The signals OUT_ 0 GOUT_N are generally configured to control respective portions of the core circuitry  104 . 
     Referring to  FIG. 7 , a diagram of an integrated circuit  200  is shown illustrating another example implementation in accordance with an example embodiment of the invention. In various embodiments, the circuit  200  may comprise a III-V compound semiconductor integrated circuit. In an example, the circuit  200  may be implemented using process technology including, but not limited to, gallium arsenide (GaAs), indium phosphide (InP), indium gallium phosphide (InGaP), gallium nitride (GaN) and silicon carbide (SiC). In various embodiments, the circuit  200  may be configured to work with standard digital logic (e.g., CMOS, TTL, etc.) signals. In an example, compatibility with standard digital logic control signals (e.g., CMOS, etc.) generally facilitates easy integration of high power, high speed III-V compound semiconductor integrated circuits with CMOS control circuits. The circuit  200  is generally configured to allow direct application of externally generated digital logic level (e.g., CMOS, etc.) control signals to input pins (or pads) of the circuit  200 . The circuit  200  is generally configured to generate internal control signals in response to externally generated digital logic level (e.g., CMOS, etc.) control signals. 
     In various embodiments, the circuit  200  may comprise a block (or circuit)  202 , a number of blocks (or circuits)  204   a - 204   b , a block (or circuit)  206 , a block (or circuit)  208 , and or any combination or number thereof. In an example, the circuit  202  may implement a single-bit input buffer circuit with integrated reference generator. In an example, the circuits  204   a - 204   b  may implement single-bit input buffer circuits without internal reference generators. The circuit  206  may implement a reference generator circuit for providing a reference voltage to the circuit  204   a  and  204   b . The circuit  208  may implement internal (core) circuitry of the circuit  200 . The circuit  202  and/or the circuits  204   a  and  204   b  are generally configured to provide a digital control interface between the circuit  208  and external circuitry connected to the circuit  200  (e.g., via pins, pads, bumps, or other method of electrically connection). In various embodiments, the external signal may be characterized as having at least two logic states (e.g., a logic LOW and a logic HIGH) represented by predefined voltage levels (e.g., CMOS levels, etc.). 
     In an example, the reference threshold voltage source  206  may be placed individually near an input buffer (comparator), or shared between multiple input buffers (comparators). The implementation of shared versus individual reference generators may be a matter of balancing current consumption reduction versus physical layout and routing constraints. In general, when I/O blocks (or circuits) need to be spread across (or around) the die or there are signal routing constraints, the threshold reference generators may be duplicated and placed where needed. 
     Although embodiments of the invention have been described in the context of a 5G application, the present invention is not limited to 5G applications, but may also be applied in other high power, high data rate wireless and wired communications applications where different rapid switching, multiple channel, and multiple user issues may exist. The present invention addresses concerns related to high speed wireless communications, mobile and stationary transceivers and point-to-point links. Future generations of wireless communications applications using radio frequency (RF), microwave, and millimeter-wave links can be expected to provide increasing power, increasing speed, increasing flexibility, and increasing numbers of interconnections and layers. The present invention may also be applicable to wireless communications systems implemented in compliance with either existing (legacy, 2G, 3G, 4G) specifications or future specifications. 
     The terms “may” and “generally” when used herein in conjunction with “is(are)” and verbs are meant to communicate the intention that the description is exemplary and believed to be broad enough to encompass both the specific examples presented in the disclosure as well as alternative examples that could be derived based on the disclosure. The terms “may” and “generally” as used herein should not be construed to necessarily imply the desirability or possibility of omitting a corresponding element. 
     While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.