Patent Publication Number: US-7913150-B2

Title: Error detection in a communications link

Description:
BACKGROUND 
     1. Field of the Invention 
     This application is related to integrated circuits and more particularly to data communications links between integrated circuits. 
     2. Description of the Related Art 
     In a typical communications system, error detection and correction techniques are used to maintain the integrity of data communicated across a channel that experiences noise. Due to high data rates of typical high-speed communications interfaces, error detection techniques may be implemented by dedicated circuitry. Hardware implementations of error detection techniques may be costly, e.g., occupy substantial portions of an integrated circuit die. Accordingly, improved techniques for implementing error detection circuitry on an integrated circuit are desired. 
     SUMMARY 
     An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols. 
     In at least one embodiment of the invention, an apparatus for detecting errors in data transmitted over a communications link having at least a first mode of operation and a second mode of operation includes a select circuit configured to select between a first digital code and a second digital code. The selection is based, at least in part, on a selected mode of operation. The first digital code is based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths. The first logical operation is consistent with the first mode of operation. The second digital code is based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream. The second logical operation is consistent with the second mode of operation. The apparatus includes a circuit configured to generate a next value of an error detection code, based, at least in part, on a third digital code and a selected one of the first and second digital codes. The third digital code is based, at least in part, on a third logical operation of at least a plurality of bits of a current value of the error detection code and the third logical operation is consistent with the first and second modes of operation. 
     In at least one embodiment of the invention, a method for detecting errors in data transmitted over a communications link having at least a first mode of operation and a second mode of operation includes generating a next value of an error detection code, based, at least in part, on a selected one of a first digital code and a second digital code and based, at least in part, on a third digital code. The first digital code is based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths. The first logical operation is consistent with the first mode of operation. The second digital code is based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream. The second logical operation is consistent with the second mode of operation. The third digital code is based, at least in part, on a third logical operation of at least a plurality of bits of a current value of the error detection code and consistent with the first and second modes of operation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. 
         FIG. 1  illustrates a block diagram of two integrated circuit devices coupled by a communications link consistent with one or more embodiments of the present invention. 
         FIG. 2  illustrates a block diagram of portions of an exemplary communications link including error detection circuitry consistent with one or more embodiments of the present invention. 
         FIG. 3  illustrates a block diagram of an exemplary error detection circuit consistent with one or more embodiments of the present invention. 
         FIG. 4  illustrates a table of an exemplary implementation of a portion of a cyclic redundancy check operation consistent with a first mode of operation and consistent with one or more embodiments of the present invention. 
         FIG. 5  illustrates a table of an exemplary implementation of a portion of a cyclic redundancy check operation consistent with a second mode of operation and consistent with one or more embodiments of the present invention. 
         FIG. 6  illustrates a table of an exemplary implementation of a portion of a cyclic redundancy check operation consistent with both the first and second modes of operation and consistent with one or more embodiments of the present invention. 
     
    
    
     The use of the same reference symbols in different drawings indicates similar or identical items. 
     DESCRIPTION OF THE PREFERRED EMBODIMENT(S) 
     Referring to  FIG. 1 , integrated circuit  102  communicates with integrated circuit  104  by an exemplary communications link including transmit interfaces  110 , receive interfaces  114 , and communications paths  106  and  108 , which include respective, individual communications paths for clock signals (e.g., CLK[m:0]), control signals (e.g., CTL[m:0]), and data signals (e.g., n-bits of commands, addresses, or data, i.e., CAD[n:0]). Those individual communications paths may be single-ended or differential communications paths. In at least one embodiment of the communications link, a bit-time is half of a clock period in duration, i.e., two data bits (e.g., two CAD[n:0] bits or two CTL[m:0] bits) are transmitted on a corresponding communications path per clock cycle (e.g., a period of a respective one of CLK[m:0]). However, the teachings herein may be adapted for bit-times having one clock period in duration (i.e., one data bit is transmitted on a corresponding communications path per clock cycle) or for other suitable bit-time durations. Communications paths  106  and  108  are unidirectional, i.e., communications paths  106  provide paths from integrated circuit  102  to integrated circuit  104  and communications paths  108  provide paths to integrated circuit  102  from integrated circuit  104 . Integrated circuit  102  includes a sideband control mechanism (e.g., interface  130 ) that provides access to control and/or status registers internal to integrated circuit  102  (e.g., locations in storage circuit  120 ). Interface  130  may be a Joint Test Action Group (i.e., JTAG) interface, System Management Bus (i.e., SMBus) interface, or other suitable interface. In at least one embodiment, interface  130  communicates test, characterization, and/or diagnostic information between the corresponding integrated circuit and an external processing device (not shown). 
     Referring to  FIG. 2 , an exemplary transmit interface (e.g., transmit interface  202 ) may perform exemplary transmit operations (e.g., transmitter circuits  220  may perform scrambling operations, signal encoding, signal level shifting, or other appropriate signal processing operations). The transmitted signals are received by an exemplary receive interface (e.g., receive interface  204 ), which performs exemplary receive operations (e.g., receive circuits  222  may perform signal equalization, signal level shifting, signal decoding, signal descrambling or other appropriate signal processing functions). 
     Communications link  200  implements a typical error detection technique that transmits a number of bits that is greater than the number of bits in the original data. Transmit interface  202  sends the original data bits, followed by redundancy (i.e., check) bits, which are used to detect errors. In at least one embodiment of communications link  200 , transmit interface  202  implements a cyclic redundancy check. A cyclic redundancy check treats a block of data as the coefficients to a polynomial. A binary division without a bit-carry (e.g., by using an exclusive-or instead of subtraction) of the data polynomial by a fixed, predetermined polynomial generates a remainder that is used as the redundancy bits (i.e., a “CRC checksum” or “CRC”). The receiver can regenerate the CRC from the received data bits and compare the regenerated CRC to a received CRC to determine whether or not an error has occurred. An error is detected when a mismatch occurs between the received CRC and the regenerated CRC. 
     A block of data used for a CRC checksum operation may vary according to the communications protocol. In at least one embodiment, communications link  200  is compliant with multiple protocols. For example, a protocol referred to herein as a “periodic protocol” requires computing a CRC periodically over a predetermined number of bit-times (e.g., 512 bit-times). The CRC may be initialized to all ones and may be bit-wise inverted prior to transmission. The CRC is inserted into a data stream for transmission over the link after the end of a fixed data window (e.g., 64 bit-times after the end of a 512 bit-time window). The data used to compute the CRC for the periodic protocol may be based on a link width. For example, a link may be 2, 4, 8, 16, or 32 bits wide, i.e., the link may include 2, 4, 8, 16, or 32 paths for communicating command, address, or data information. A separate CRC may be computed independently for individual groups of a predetermined number of paths (e.g., each 8-bit lane) of the link. Another communications protocol requires initializing the CRC (e.g., to all ones) for every packet, appending the CRC to every packet, and is referred to herein as a “packet-based protocol.” The data used to compute the CRC in the packet-based protocol may be independent of the link width. The packet-based protocol may be included for a hardware-based retry mode that allows recovery from soft errors at the link level. 
     Exemplary transmit interface  202  includes exemplary error detection facility circuit  206  that receives multiple (e.g., four) bit-times of data in parallel (e.g., DATA[35:0]) for transmission over a nine-bit link (i.e., 8-bit lane CAD[7:0] and corresponding control path CTL). A checksum generator circuit (e.g., CRC generator  232 ) generates an output CRC checksum based on the data for transmission over the link. CRC generator  232  operates on multiple bit-times (e.g., DATA[35:0] which includes four bit-times of data for transmission over 8-bit lane CAD[7:0] and corresponding control path CTL) in parallel. Note that in other embodiments, error detection facility  206  receives other suitable numbers of bit-times of data for processing in parallel. 
     CRC generator circuit  232  includes logic circuitry to implement CRC operations consistent with a plurality of modes of operation. For example, referring to  FIG. 3 , CRC generation circuit  300  may be configured to generate a CRC consistent with a periodic protocol or consistent with a packet-based protocol. Exemplary CRC generator circuit  300  receives the four bit-times of data for transmission over nine communications paths and computes a CRC checksum value for the four bit-times in parallel, e.g., CRC[31:0], which is stored in storage element  316 . The operation used to generate the CRC consistent with the periodic protocol shares some logic terms with the operation used to generate the CRC consistent with the packet-based protocol, e.g., as a result of the two protocols implementing the same CRC polynomial. The operation including those common terms is performed by common logic circuit  308 . 
     However, generation of the CRC consistent with the periodic protocol requires some operations exclusive to the periodic protocol. Those operations are performed by periodic protocol logic circuit  304 . Packet-based protocol logic circuit  306  performs at least operations exclusive to the packet-based protocol. In at least one embodiment of CRC generation circuit  300 , to provide logical separation between the data and the CRC, which is transmitted immediately after the data, packet-based protocol logic circuit  306  effectively introduces a plurality of dummy bits (e.g., 32 dummy bits) into the data stream. The logical separation reduces susceptibility of an error burst affecting both data and the CRC checksum. Exemplary operations performed by periodic protocol logic circuit  304 , packet-based protocol logic circuit  306 , and common logic circuit  308  include bitwise shifts of the operands and bitwise exclusive-ors of the operands. 
     Select circuit  310  provides as an output, a selected one of the outputs of the periodic protocol logic circuit  304  and the packet-based protocol logic circuit  306  according to a select signal indicating a selected mode of operation indicative of a particular communication link protocol. Logic circuit  312  combines the output of select circuit  310  with the output of common logic circuit  308  to generate the next value of the CRC. Control logic  314  generates a reset signal that resets CRC accumulation storage element  316  (e.g., sets individual bits of storage element to all ones or all zeros) consistent with the selected protocol. For example, storage element  316  is reset to all ones every packet when the packet-based protocol mode is selected. CRC accumulation storage element  316  is reset to all ones periodically, e.g., every 512 bit-times, when the periodic protocol mode is selected. 
     The output of logic circuit  312 , which is stored in CRC accumulation storage element  316 , is consistent with a CRC checksum based on the following polynomial function:
 
x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1.
 
In periodic mode, an exemplary CRC operation may be performed on the contents of CRC accumulation storage element  316  across a single bit-time (nine bits) of data, consistent with the following pseudocode:
 
                                            static uint poly = 0x04C11DB7; /*polynomial*/           unit compute_CRC (uint data, unint CRC)           {             int j;             for (j = 0; j &lt; 9; ++j){             /* do nine times for nine communications paths */               uint tmp = CRC &gt;&gt; 31 /* store highest bit */               CRC = (CRC &lt;&lt; 1) | ((data &gt;&gt; j) &amp; 1);               /* shift message in */               CRC = (tmp) ? CRC {circumflex over ( )} poly : CRC;               /* subtract poly if greater */               };               return CRC;           };                        
To improve circuit performance (e.g., reduce latency), a circuit implementation may unroll the loop and include logic to perform the operations on multiple bit-times of data (e.g., four bit-times or other suitable number of bit-times).
 
     In an exemplary packet-based protocol, the CRC operation is independent of the link width. In various embodiments of the invention, bits from individual bit-times of individual double words of a packet may be combined for processing, consistent with the following pseudocode (where the subscripts enumerate corresponding bit-times): 
                                case (size) {       2: data = {CTL 12 , CAD 15 [1:0], CAD 14 [1:0], CAD 13 [1:0], CAD 12 [1:0],         CTL 8 , CAD 11 [1:0], CAD 10 [1:0], CAD 9 [1:0] , CAD 8 [1:0],         CTL 4 , CAD 7 [1:0], CAD 6 [1:0], CAD 5 [1:0] , CAD 4 [1:0],         CTL 0 , CAD 3 [1:0], CAD 2 [1:0], CAD 1 [1:0] , CAD 0 [1:0]}       4: data = {CTL 6 , CAD 7 [3:0], CAD 6 [3:0], CTL 4 , CAD 5 [3:0], CAD 4 [3:0],         CTL 2 , CAD 3 [3:0], CAD 2 [3:0], CTL 0 , CAD 1 [3:0], CAD 0 [3:0], }       8: data = {CTL 3 , CAD 3 [7:0], CTL 2 , CAD 2 [7:0],         CTL 1 , CAD 1 [7:0], CTL 0 , CAD 0 [7:0]}       16: data = {CTL 1 [1], CAD 1 [15:8], CTL 1 [0], CAD 1 [7:0],         CTL 0 [1], CAD 0 [15:8], CTL 0 [0], CAD 0 [7:0]}       32: data = {CTL[3], CAD[31:24], CTL[2], CAD[23:16],         CTL[1], CAD[15:8], CTL[0], CAD[7:0]}.                    
In the exemplary packet-based mode, the CRC operation is modified to limit burst errors from affecting both data and the CRC. In at least one embodiment of a CRC computation, a predetermined number of pad bits (e.g., 32 bits) are appended to the data, thus requiring at least one additional pass through the CRC operation loop above. Rather than performing extra passes through the CRC loop for each pad bit (e.g., 32 extra passes), the CRC operation may be modified to effectuate the data padding by any suitable technique. For example, rearranging the CRC operation to introduce the data at the most-significant end of the CRC register operates as if the data had been zero-padded by the number of bits of the CRC register. An exemplary resulting CRC operation is consistent with the following pseudocode:
 
                                static uint poly = 0x04C11DB7; /*polynomial*/       unit compute_CRC (uint data, unint CRC)       {         int j;         for (j = 0; j &lt; 36; ++j){         /* do 36 times for four bit-times over nine communications paths */         /* XOR highest bit with message */           uint tmp = ((CRC &gt;&gt; 31 &amp; 1 ){circumflex over ( )}((data &gt;&gt; j) &amp; 1);           CRC = (tmp) ? (CRC &lt;&lt; 1) {circumflex over ( )} poly : (crc &lt;&lt; 1);           /* subtract poly if greater */           };           return CRC;       };                    
As a result of rearranging the CRC operation to effectuate zero-padding of the data in the same number of loop iterations as a CRC operation without the zero-padding, a circuit corresponding to the CRC operation effectuating zero-padding of the data includes additional logical terms that are not present in a circuit implementing the CRC operation without zero-padding of the data.
 
     Referring to  FIGS. 3-6 , exemplary logical operations implemented by periodic protocol logic circuit  304 , packet-based protocol logic circuit  306 , and common logic circuit  308  include the bit-wise exclusive-or operations of  FIG. 4 ,  FIG. 5 , and  FIG. 6 , respectively. The output of common logic circuit  308  (i.e., CTree[31:0] of  FIG. 6 ) is the result of a logical operation on CRC[31:0] (i.e., C[ 31 : 0 ] in  FIGS. 4-6 ) and individual bits of DATA[35:0] (i.e., D[35:0] in  FIGS. 4-6 ) that includes only terms common to both the periodic protocol and the packet-based protocol. The output of periodic protocol logic circuit  304  (i.e., Tree 1 [31:0] of  FIG. 4 ) is the result of a logical operation on individual bits of DATA [35:0] including at least terms exclusive to the periodic protocol. Periodic protocol logic circuit  304  may implement a logical operation that includes terms common to the packet-based protocol, but are not included in the operation implemented by common logic circuit  308  to reduce delay through common logic circuit  308 . For example, common logic circuit  308  may be implemented using 2-input XOR gates or 3-input XOR gates forming a tree of XOR gates having a number of levels (e.g., a number of levels may equal log 2  (number of terms in an operation)). By including one or more terms in a tree of XOR gates in periodic protocol logic circuit  304  and packet-based protocol logic circuit  306  instead of in common logic circuit  308 , a number of levels of gates in common logic circuit  308  may be reduced, thereby reducing the latency of CRC generation circuit  300 . Note that allocation of terms to operations associated with periodic protocol logic circuit  304 , packet-based protocol logic circuit  306 , and common logic circuit  308  may be automated. 
     The output of packet-based protocol logic circuit  306  (i.e., Tree 2 [31:0] of  FIG. 5 ) is the result of a logical operation on individual bits of DATA [35:0] including at least terms exclusive to the packet-based protocol. Packet-based protocol logic circuit  306  may implement a logical operation that includes terms common to the periodic protocol, but are not included in the operation implemented by common logic circuit  308  to reduce delay through common logic circuit  308 . Note that the particular terms designated in Tree 1 , Tree 2 , and CTree are exemplary only and other allocations of terms to periodic protocol logic circuit  304 , packet-based protocol logic circuit  306 , and common logic circuit  308 , for the same or other checksum computations are consistent with the invention described herein. 
     Referring back to  FIG. 2 , control circuits  252  may queue individual bits of DATA[35:0] and issue appropriate bit-times of data or selectively issue the output CRC checksum to transmitter circuits  220  for transmission over corresponding transmission paths (e.g., corresponding ones of CAD[7:0] and CTL). Receiver circuits  222  of receive interface  204  receive the signals from communications paths CAD[0:7] and CTL. Receiver circuits  222  may perform signal equalization, signal level shifting, noise reduction, or other appropriate signal processing functions on signals received from respective ones of the communications paths. The received signals are then received by circuits  262 , which may queue a number of bit-times of the data or CRC checksum for further processing. Circuits  262  also extract a received CRC checksum from the received signals and supply the received CRC to error detection circuit  243 . Circuits  262  supply the data stream to CRC generator  242 . CRC generator  242  operates substantially the same as CRC generator  232  to regenerate the CRC from the received data and supplies the regenerated CRC to error detection circuit  243 . Error detection circuit  243  compares the regenerated CRC to the received CRC. If the regenerated CRC and the received CRC do not match, an error is detected and any suitable error correction technique is effectuated. 
     The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in an embodiment in which a particular CRC polynomial is applied to four bit-times of data in parallel for communications over a communications link having eight CAD communications path and one CTL communications path, one of skill in the art will appreciate that the teachings herein can be utilized for communications links having other widths and applying other CRC polynomials to other numbers of bit-times of data in parallel. In addition, techniques described herein may be applied to other protocols and error detection schemes other than a CRC (e.g., repetition schemes, parity schemes, polarity schemes, and Hamming-based distance checks). Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.