Patent Publication Number: US-2022216198-A1

Title: Diode triggered silicon controlled rectifier

Description:
FIELD OF THE INVENTION 
     The present disclosure relates to semiconductor structures and, more particularly, to diode triggered silicon controlled rectifiers and methods of manufacture. 
     BACKGROUND 
     A Silicon Controlled Rectifier (SCR) is a semiconductor or integrated circuit (IC) that allows the control of current using a small current. A diode triggered SCR is a very useful ESD protection device due to trigger voltage tunability; however, diode triggered SCRs cannot be used for mid or high voltage electrostatic discharge (ESD) protection. This is due to the fact that the trigger voltage tunability does not scale with a number of trigger diodes. 
     For example, diode triggered SCRs are known to exhibit the Darlington effect which reduces the amount of current in each subsequent diode. In essence, the voltage dropped by each additional diode is reduced. Also, the leakage of the SCR is increased. Accordingly, there is a diminishing gain achieved with of additional diodes, which is caused by the Darlington effect. 
     SUMMARY 
     In an aspect of the disclosure, a structure comprises: a diode string comprising a first type of diodes; and a second type of diode in bulk technology in series with the diode string of the first type of diodes. 
     In an aspect of the disclosure, a structure comprises: multiple P+ and N+ regions forming a diode string without Darlington effect; and a single diode or string of diodes in bulk technology electrically connected to the diode string. 
     In an aspect of the disclosure, a structure comprises: a diode string comprising, in series, alternating P+ regions and N+ regions in semiconductor on insulator material; and a single diode or string of diodes in a bulk wafer electrically connected to a last N+ region of the diode string. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. 
         FIG. 1  shows stringed diodes and respective fabrication processes in accordance with aspects of the present disclosure. 
         FIG. 2  shows the stringed diodes of  FIG. 1  with a diode triggered silicon controlled rectifier (SCR) and respective fabrication processes in accordance with aspects of the present disclosure. 
         FIG. 3  shows the stringed diodes with a diode triggered silicon controlled rectifier (SCR) of  FIG. 2  and respective fabrication processes in accordance with aspects of the present disclosure. 
         FIG. 4  shows a schematic diagram of a diode triggered silicon controlled rectifier (SCR) in accordance with aspects of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure relates to semiconductor structures and, more particularly, to diode triggered silicon controlled rectifiers (SCR) and methods of manufacture. More specifically, the present disclosure provides a diode triggered SCR with hybrid diodes. In embodiments, the hybrid diodes include diodes formed on both semiconductor on insulator (SOI) technologies (i.e., SOI diodes) and bulk substrate technologies (i.e., bulk diodes). Advantageously, the present disclosure provides a solution for mid-voltage low capacitance low leakage ESD protection. 
     In more specific embodiments, the diode triggered SCRs include a combination of trigger diodes in bulk and SOI technologies. The diode triggered SCRs are capable of maintaining trigger voltage tunability and scaling with any number of trigger diodes, thus offering an ESD protection solution for both mid or high voltage range. This is due to the fact that the diode triggered SCRs are able to mitigate the Darlington effect observed in known diode triggered SCRs. For example, the SOI diodes are capable of eliminating the Darlington effect as they are strictly two (2) terminal diodes. By avoiding the Darlington effect, the SOI diodes will exhibit lower leakage and higher voltage trigger (Vtrigger). On the other hand, the bulk diodes inject electrons into the substrate to facilitate triggering. In addition, the last diode of the diode string is a bulk diode and, hence, does not form a bulk diode string. 
     The diode triggered SCRs of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the diode triggered SCRs of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the diode triggered SCRs use three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. 
       FIG. 1  shows stringed diodes and respective fabrication processes in accordance with aspects of the present disclosure. In particular, the structure  10  includes SOI technology  12  and bulk technology  14 . The SOI technology  12  includes two (2) terminal diodes  25   a ,  25   b ; whereas, the bulk technology includes a transistor  27  in a bulk wafer which acts as a diode. It should be understood by those of skill in the art that although two diodes  25   a ,  25   b  are shown in SOI technology, additional diodes are also contemplated herein. Although a single transistor  27  is shown, the use of additional transistors is contemplated herein. 
     In embodiments, the SOI technology  12  includes a substrate  12   a , e.g., wafer, in addition to an insulator layer  12   b  and a semiconductor material  12   c . The substrate  12   a  can be a p-type substrate, the insulator layer  12   b  can be a buried oxide material and the semiconductor material  12   c  can be any suitable semiconductor material. For example, the semiconductor material  12   c  may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. 
     In further embodiments, the bulk technology  14  can be formed from the SOI technology  12 . Specifically, the bulk technology  14  can be formed by etching or removing the insulator layer  12   b  and the semiconductor material  12   c  from the SOI technology  12 , leaving the p-type substrate  12   a . The insulator layer  12   b  and the semiconductor material  12   c  can be removed by conventional lithography and etching processes, e.g., reactive ion etching (RIE), using selective chemistries as should be understood by those of skill in the art. 
     Prior to forming the bulk technology  14 , a plurality of shallow trench isolation regions  16   a ,  16   b  are formed using conventional lithography, etching and deposition processes. For example, a resist formed over the semiconductor material  12   c  is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., RIE, will be used to form one or more trenches in the insulator material  12   b  and substrate  12   a , through the openings of the resist. Following the resist removal by a conventional oxygen ashing process or other known stripants, insulator material, e.g., oxide, can be deposited within the trenches by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. Any residual material on the surface of the semiconductor material  12   c  can be removed by conventional chemical mechanical polishing (CMP) processes. 
     In embodiments, at least one shallow trench isolation region  16   a  will be formed between the SOI technology  12  and the bulk technology  14 ; whereas, at least one shallow trench isolation region  16   b  will be formed between a P+ region  18   a  and a N+ region  18   b  of the bulk technology  14 . In embodiments, the shallow trench isolation region  16   b  will extend into a N-well  20  of the bulk technology  14 , which can extend into the substrate  12   a  of the SOI technology  12 . The P+ region  18   a , N+ region  18   b  and the N-well  20  can be formed by conventional ion implantation processes known to those of skill in the art such that no further explanation is required for a complete understanding of the present disclosure. In embodiments, the P+ region  18   a , N-well  20  and the p-type substrate  12   a  will form a PNP transistor  27  (which acts as a very low leakage diode) in the bulk technology  14 . The PNP transistor  27  (e.g., diode  27 ) is a last diode of the diode string and, hence, does not form a bulk diode string. Accordingly, the diode  27  is capable of dropping a large voltage without the Darlington effect due to it receiving a large current. 
     Still referring to  FIG. 1 , by using conventional ion implantation processes known to those of skill in the art, a N-well  22  is formed in the semiconductor material  12   c . Thereafter, alternating P+ regions  24   a  and N+ regions  24   b  are formed in the semiconductor material  12   c , with a P+ region  24   a  and N+ region  24   b  of adjacent diodes  25   a ,  25   b  contacting one another. In this way, the adjacent diodes  25   a ,  25   b  are strictly two (2) terminal diodes in series, which can eliminate the Darlington effect. The shallow trench isolation region  16   a  separates the diodes  25   a ,  25   b  from the diode  27 . A ground pad  26  electrically contacts the N+ region  18   b  and an I/O pad  28  electrically contacts the P+ region  24   a ′. 
     A silicide block layer  30  is formed over each of the diodes  25   a ,  25   b , i.e., over the N-well  20  and contacting the respective P+ and N+ regions  24   a ,  24   b . In embodiments, the silicide block layer  30  can be formed by conventional silicide processes. As should be understood by those of skill in the art, the silicide process begins with deposition of a thin transition metal layer, e.g., nickel, cobalt or titanium, over the diodes  25   a ,  25   b . After deposition and patterning processes, the structure is heated allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) in the active regions of the semiconductor device (e.g., diodes  25   a ,  25   b ) forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal can be removed by chemical etching, leaving silicide contacts in the active regions of the device. The N+ region of the SOI diode  25   b  is electrically connected to the P+ region of the bulk diode  27 . A dielectric layer  32  (e.g., oxide) can then be deposited over the diodes  25   a ,  25   b ,  27 , with wiring connections between the pads, diodes, etc., embedded within the dielectric layer  32 . It should be noted that, although the diodes  25   a  and  25   b  are shown bounded by silicide block, they could also be bounded with the FET gate material or any other available insulator. 
       FIG. 2  shows the stringed diodes of  FIG. 1  with a diode triggered silicon controlled rectifier (SCR) and respective fabrication processes. More specifically, the structure  10   a  of  FIG. 2  show the stringed diodes  25   a ,  25   b ,  27  of  FIG. 1  represented at reference numeral  100  and a SCR represented at reference numeral  110 . As should be understood by one of skill in the art, the stringed diodes  25   a ,  25   b  and  27  will help trigger the SCR  110 . 
     In embodiments, the SCR  110  is formed in bulk technology and includes a P-well  50  and a N-well  52  formed using conventional ion implantation processes as already described herein. Alternating P+ regions  54   a  and N+ regions  54   b  are formed in the respective P-well  50  and N-well  52 , separated by shallow trench isolation regions  16   c . In embodiments, the alternating P+ regions  54   a  and N+ regions  54   b  formed in the respective P-well  50  and N-well  52  form a PNP transistor  55   a  and NPN transistor  55   b , respectively. A shallow trench isolation region  16   d  separates the SCR  110  from the stringed diodes  100  of  FIG. 1 . 
     The bulk technology, shallow trench isolation regions, the P+ regions (anodes), and the N+ regions (cathodes) are formed in the manner already described herein. In this embodiment, the ground pad  26  is connected to the P+ region  54   a ′ and N+ region  54   b ′ of the P-well  50 , in addition to the N+ region  18   b . Also, in this embodiment, the I/O pad  28  is connected to the P+ region (anode)  54   a  in the N-well  52 . The SCR  110  and the stringed diode  25   a  are connected through the respective N+ region  54   b  of the SCR  110  and P+ region  24   a  of the diode  25   a.    
     In operation using the structure  10   a  of  FIG. 2 , an ESD event on the I/O pad  28  will pass current through the P+ region  54   a , N-well  52  and N+ region  54   b  to the stringed diodes  25   a ,  25   b ,  27 . The current will pass through the bulk diode  27  and N+ region  18   b  to the ground pad  26 . The current will then trigger the SCR  110 . Once the SCR is triggered, most of the current from the P+ region (anode)  54   a  can flow backwards into the N+ region (cathode)  54   b ′ of the P-well  50 . 
       FIG. 3  shows stringed diodes with a diode triggered SCR  110  of  FIG. 2  and respective fabrication processes. More specifically, the structure  10   b  of  FIG. 3  includes a string of diodes  25   a ,  25   b  that are fabricated from doped gate material as represented by reference numerals  62   a ,  62   b . That is, in this embodiment, the alternating P+ regions  24   a  and N+ regions  24   b  shown in  FIG. 1  are replaced with doped gate material  62   a ,  62   b . The doped gate material can be a P-doped poly material  62   a  and N-doped poly material  62   b , separated by a N-well region  22 . The P-doped poly material  62   a  and the N-doped poly material  62   b  can be formed on a gate dielectric material (also represented by reference numerals  62   a ,  62   b ). In embodiments, the gate dielectric material can be a high-k dielectric material such as hafnium oxide; although other dielectric materials are also contemplated herein. In addition, instead of using SOI technology, in this embodiment the doped gate material  62   a ,  62   b  is formed over a shallow isolation structure  60  formed in the N-well  20  of the bulk technology. In embodiments, the P-doped poly material  62   a  and a N-doped poly material  62   b  can be deposited and patterned using conventional deposition, lithography and patterning processes. 
       FIG. 4  shows a schematic diagram of a diode triggered silicon controlled rectifier in accordance with aspects of the present disclosure. As shown in  FIG. 4 , the stringed diodes  25   a ,  25   b ,  27  are provided in series. The arrow represents the forward bias and drive current of the diodes  25   a ,  25   b ,  27 . By using the diodes  25   a ,  25   b  in SOI technology, it is possible to avoid bipolar gain and hence the Darlington effect. Particularly, unlike conventional structures, there will be no leakage of the diodes  25   a ,  25   b  to ground, and hence there will be no diminishing gains by using additional diodes (which causes the 
     Darlington effect). Also, by maintaining a fraction of the diodes in bulk allows for the injection of carriers into substrate which facilitates triggering. 
     The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.