Patent Publication Number: US-2002003238-A1

Title: Structure including cubic boron nitride films and method of forming the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
     [0001] The present application is a continuation-in-part of U.S. patent application Ser. No. 09/607,207 entitled “Semiconductor Structure, Semiconductor Device, Communicating Device, Integrated Circuit, and Process for Fabricating the Same”, filed Jun. 28, 2000, by the assignee hereof. 
    
    
     
       FIELD OF THE INVENTION  
       [0002] This invention relates generally to structures and devices including a cubic boron nitride material and to a method for their fabrication, and more specifically to structures and devices and to the fabrication and use of structures and devices that include a thin film of cubic boron nitride.  
       BACKGROUND OF THE INVENTION  
       [0003] Structures including cubic boron nitride (cBN) material are desirable for several reasons. For example, cBN is relatively hard and chemically inert and is thus often used to form protective coatings for cutting and grinding tools. In addition, cBN films exhibit high heat conductivity and yet are electrically insulating, so they may be used as dielectric or insulating films for semiconductor manufacturing applications. Furthermore, suitably doped cBN films are semiconductive and exhibit a wide band gap (about 5 eV) and therefore the doped cBN films may be used to form semiconductive thin films.  
       [0004] If a large area thin film of high quality cBN material could be formed at relatively low cost, a variety of structures and semiconductor devices could advantageously be fabricated in or using that film at a low cost compared to the cost of fabricating such structures and devices using bulk cBN. In addition, if a thin film of high quality cBN material could be realized beginning with a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the high quality cBN material layer.  
       [0005] Accordingly, a need exists for a structure that provides a high quality cBN film or layer over another monocrystalline material and for a process for making such a structure. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0006] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:  
     [0007]FIGS. 1 and 2 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention; and  
     [0008]FIG. 3 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer. 
    
    
     [0009] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.  
     DETAILED DESCRIPTION OF THE DRAWINGS  
     [0010]FIG. 1 illustrates schematically, in cross section, a portion of a structure  100  in accordance with an embodiment of the invention. Structure  100  includes a monocrystalline substrate  102 , an accommodating buffer layer  104  comprising a monocrystalline material, and a cBN layer  106 . In this context, the term “monocrystalline” shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.  
     [0011] In accordance with one embodiment of the invention, structure  100  also includes an amorphous intermediate layer  108  positioned between substrate  102  and accommodating buffer layer  104 . Structure  100  may also include a template layer  110  between the accommodating buffer layer and cBN layer  106 . As will be explained more fully below, the template layer helps to initiate the growth of the subsequently grown monocrystalline cBN material. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer, and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.  
     [0012] Substrate  102 , in accordance with an embodiment of the invention, is a monocrystalline semiconductor or compound semiconductor wafer, preferably of large diameter. The wafer can be of, for example, a material from Group IV of the periodic table, and preferably a material from Group IVB. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably substrate  102  is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer  104  is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate. In accordance with one embodiment of the invention, amorphous intermediate layer  108  is grown on substrate  102  at the interface between substrate  102  and the growing accommodating buffer layer by the oxidation of substrate  102  during the growth of layer  104 . The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in subsequently formed films (e.g., cBN layer  106 ).  
     [0013] Accommodating buffer layer  104  is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying material layer. For example, the material could be an oxide or nitride having a lattice structure closely matched to the substrate and to the subsequently applied layer. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxides or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitrides may include three or more different metallic elements.  
     [0014] Amorphous interface layer  108  is preferably an oxide formed by the oxidation of the surface of substrate  102 , and more preferably is composed of a silicon oxide. The thickness of layer  108  is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate  102  and accommodating buffer layer  104 . Typically, layer  108  has a thickness in the range of approximately 0.5-5 nm.  
     [0015] Layer  106  is formed of cBN that is epitaxially gown overlying monocrystalline layer  104 . A thickness of layer  106  may vary from application to application. For example, when layer  106  is used to form dielectric layer for semiconductor devices, layer  106  thickness may range from 1 nm to 1000 nm and when layer  106  is used as a protective coating for cutting or grinding tool applications, the thickness of layer  106  may range from 1000 nm to 100,000 nm.  
     [0016] Appropriate materials for template  110  are discussed below. Suitable template materials chemically bond to the surface of an underlying layer at selected sites and provide sites for the nucleation of the subsequent epitaxial growth of monocrystalline material. When used, template layer  110  has a thickness ranging from about 1 to about 10 monolayers.  
     [0017]FIG. 2 schematically illustrates, in cross section, a portion of a structure  200  in accordance with another exemplary embodiment of the invention. Structure  200  is similar to structure  100 , except that structure  200  includes an amorphous layer  202 , rather than accommodating buffer layer  104  and amorphous interface layer  108 .  
     [0018] As explained in greater detail below, amorphous layer  202  may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline layer  110  is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer  202  formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer  202  may comprise one or two amorphous layers. Formation of amorphous layer  202  between substrate  102  and layer  106  (subsequent to layer  110  formation) relieves stresses between layers  102  and  110  and provides a true compliant substrate for subsequent processing—e.g., monocrystalline material layer  106  formation.  
     [0019] The processes previously described above in connection with FIG. 1 is adequate for growing monocrystalline material layers over a monocrystalline substrate. However, the process described in connection with FIG. 2, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline material layers because it allows any strain in layer  110  to relax.  
     [0020] In accordance with one embodiment of the present invention, layer  110  serves as an anneal cap during layer  202  formation. Accordingly, layer  110  is preferably thick enough to provide a suitable template for layer  106  growth (at least one monolayer) and thin enough to allow layer  110  to form as a substantially defect free monocrystalline material. Alternatively, a portion of layer  106  may be formed before the structure is exposed to an anneal process designed to form layer  202 .  
     [0021] The following non-limiting, illustrative examples describe various combinations of materials useful in structures  100  and  200  in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.  
     EXAMPLE 1  
     [0022] In accordance with one embodiment of the invention, monocrystalline substrate  102  is a silicon substrate oriented in the ( 100 ) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment of the invention, accommodating buffer layer  104  is a monocrystalline layer of Sr z Ba 1-z TiO 3  where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO x ) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer  106 . The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 5 nm. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1 to 2 nm.  
     [0023] To facilitate the epitaxial growth of layer  106  on the monocrystalline oxide, a template layer may be formed. In accordance with one embodiment of the invention, the template includes a surfactant that comprises, but is not limited to, elements such as Al, In and Ga. In one exemplary embodiment, Al is used for the surfactant and functions to modify the surface and surface energy of layer  110 . Preferably, the surfactant layer is epitaxially grown, to a thickness of one to two monolayers. The surfactant increases the surface energy of the monocrystalline oxide layer and also shifts the crystalline structure of the template to a diamond-like sp 3  structure.  
     [0024] Additional aluminum (e.g., 1-3 monolayers) may be additionally deposited and exposed to a gas such as nitrogen to form aluminum nitride, which acts as a seed layer for subsequent cBN epitaxial growth.  
     [0025] Once layer  110  is formed, cBN layer  106  is grown to a desired thickness. In accordance with one aspect of this embodiment, layer  106  includes a_thick cBN film.  
     EXAMPLE 2  
     [0026] This example provides exemplary materials useful in structure  200 , as illustrated in FIG. 2. Substrate material  102 , template layer  110 , and layer  106  may be the same as those described above in connection with example 1.  
     [0027] Amorphous layer  202  is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer  108  materials as described above) and accommodating buffer layer materials (e.g., layer  104  materials as described above). For example, amorphous layer  202  may include a combination of SiO x  and Sr z Ba 1-z  TiO 3  (where z ranges from 0 to 1), which may combine or mix during an anneal process to form amorphous oxide layer  202 .  
     [0028] The thickness of amorphous layer  202  may vary from application to application and may depend on such factors as desired insulating properties of layer  202 , type of device formed using layer  106 , and the like. In accordance with one exemplary aspect of the present embodiment, layer  202  thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.  
     [0029] Referring again to FIGS.  1 - 2 , substrate  102  is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer  104  is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms “substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.  
     [0030]FIG. 3 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve  300  illustrates the boundary of high crystalline quality material. The area to the right of curve  300  represents layers that have a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.  
     [0031] In accordance with one embodiment of the invention, substrate  102  is a ( 100 ) or ( 111 ) oriented monocrystalline silicon wafer and accommodating buffer layer  104  is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer  108 , a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable.  
     [0032] Still referring to FIGS.  1 - 2 , layer  106  is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer  106  differs from the lattice constant of substrate  102 . To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer  106 , substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. In the case of strontium titanate and cBN, the lattice mismatch is about eight percent, whereas the lattice mismatch between silicon and cBN is about thirty-three percent.  
     [0033] The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a structure such as the structures depicted in FIGS.  1 - 2 . The process starts by providing a monocrystalline substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the substrate is a silicon wafer having a ( 100 ) orientation. The substrate is preferably oriented on axis or, at most, about 4° off axis toward [110]. At least a portion of the substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term “bare” in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term “bare” is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 850° C. to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2×1 structure, includes strontium, oxygen, and silicon. The ordered 2×1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.  
     [0034] In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 850° C. At this temperature, a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2×1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.  
     [0035] Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800° C. and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2×1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.  
     [0036] After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of cBN. For example, the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.  
     [0037] As noted above, the template layer may also include a surfactant. In this case, 1-2 monolayers of surfactant such as aluminum are deposited using, for example, MBE and the surfactant is then exposed to a gas such as As, P, Sb and N, for example, to form a capping layer.  
     [0038] Following the formation of the template layer, layer  106  is formed using, for example, rf biased magnetron sputtering or chemical vapor deposition (CVD) techniques.  
     [0039] Structure  200 , illustrated in FIG. 2, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate  102 , and forming layer  110  and/or layer  106  over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer  202 . In accordance with one embodiment of the invention, layer  106  is then subsequently grown over layer  110 . Alternatively, the anneal process may be carried out subsequent to growth of all or part of layer  106 .  
     [0040] In accordance with one aspect of this embodiment, layer  202  is formed by exposing substrate  102 , the accommodating buffer layer, and the amorphous oxide layer to a rapid thermal anneal process with a peak temperature of about 700° C. to about 1000° C. and a process time of about 5 seconds to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing, electron beam annealing, or “conventional” thermal annealing processes (in the proper environment) may be used to form layer  202 . When conventional thermal annealing is employed to form layer  202 , an overpressure of one or more constituents of layer  110  or  106  may be required to prevent degradation of layer  110  or  106  during the anneal process.  
     [0041] The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a cBN layer by the processes of molecular beam epitaxy, CVD and/or sputtering. The process can also be carried out by the process of metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), the like, or any combination of such processes. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, peroskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.  
     [0042] Clearly, those embodiments specifically describing structures having cBN portions and Group IV semiconductor portions are meant to illustrate embodiments of the present invention and not limit the present invention. There are a multiplicity of other combinations and other embodiments of the present invention. For example, the present invention includes structures and methods for fabricating material layers which form structures suitable for grinding or cutting and for semiconductor structures suitable for microelectronic devices and integrated circuits including other layers such as metal and insulating layers. More specifically, the invention includes structures and methods for forming a compliant substrate which is used in the fabrication of structures, devices and integrated circuits and the material layers suitable for fabricating those structures, devices, and integrated circuits. By using embodiments of the present invention, it is now simpler to integrate devices that include cBN layers as well as other material layers that are used to form those devices with other components that work better or are easily and/or inexpensively formed. This allows a device to be shrunk, the manufacturing costs to decrease, and yield and reliability to increase.  
     [0043] In accordance with one embodiment of this invention, a monocrystalline semiconductor or compound semiconductor wafer can be used in forming cBN films over the wafer. In this manner, the wafer is essentially a “handle” wafer used during the fabrication of cBN-based electrical components. Therefore, electrical components can be formed using cBN films over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.  
     [0044] By the use of this type of substrate, fabrication costs for cBN-based devices should decrease because larger substrates can be processed more economically and more readily compared to the relatively smaller substrates (e.g. conventional substrates used to form cBN films).  
     [0045] In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.  
     [0046] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not necessarily include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.