Patent Publication Number: US-2020280175-A1

Title: Vertical-cavity surface-emitting laser

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 62/811,624, filed on Feb. 28, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. 
    
    
     BACKGROUND 
     Field 
     Exemplary embodiments of the invention relate to a highly reliable vertical-cavity surface-emitting laser. 
     Discussion of the Background 
     A vertical-cavity surface-emitting laser (VCSEL) is a laser that emits a laser beam in a vertical direction from a substrate surface. A typical VCSEL includes an active layer disposed between mirrors. Electrons and holes injected through the mirrors generate light in the active layer, and a laser is generated and emitted through resonance by the mirrors. 
     Current flowing perpendicular to the VCSEL needs to be limited to a small region, and, to this end, various etching and oxidation processes have been used. For example, an isolated post is formed by etching the mirror layers and the active layer to form a trench in a ring shape, which allows current to be concentrated in an aperture of a small region by forming an oxidation layer using the trench. 
     However, when the aperture is formed by oxidation using the trench, various problems may occur. For example, oxidation proceeds from the trench into a post. As such, as a diameter of the post becomes larger, the oxidation time becomes longer thereby rendering the oxidation process more difficult. Meanwhile, when a size of the post is reduced, a size of the contact layer in ohmic contact with the upper mirror may also be reduced. In this case, a connection area between the pad electrode and the contact layer may be reduced, thereby adversely affecting reliability. 
     Furthermore, when forming a plurality of emitter arrays, a plurality of posts surrounded by trenches have to be formed, which may increase manufacturing complexity as a wide area would need to be etched to form the ring-shaped trench. Moreover, when forming a pad electrode, as a connection between the pad and an emitter passes through the trench, the process yield may be lowered as there is a risk of electrical disconnection. In addition, a trench having a large area is formed around the emitter, which may adversely affect the emitter&#39;s reliability from a surface defect. 
     The above information disclosed in this Background section is only for understanding of the background of the inventive concepts, and, therefore, it may contain information that does not constitute prior art. 
     SUMMARY 
     VCSELs constructed according to exemplary embodiments of the invention have high reliability and are capable of preventing the occurrence of electrical disconnection due to a trench. 
     Exemplary embodiments also provide a VCSEL capable of preventing the performance of an emitter from being reduced by defects. 
     Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts. 
     A vertical-cavity surface-emitting laser (VCSEL) according to an exemplary embodiment includes: a lower mirror; an upper mirror; an active layer interposed between the lower mirror and the upper mirror; an aperture forming layer interposed between the upper mirror and the active layer, and including an oxidation layer and a window layer surrounded by the oxidation layer; a ring-shaped trench passing through the upper mirror, the aperture forming layer, and the active layer to define an isolation region therein; and a plurality of oxidation holes disposed in the isolation region surrounded by the trench, and passing through the upper mirror and the aperture forming layer. 
     The oxidation holes may be disposed in the isolation region surrounded by the trench so that the window layer may be formed precisely, and a surface defect caused during the formation of trench may be prevented from moving near the window layer, thereby providing a highly reliable VCSEL. 
     The trench may extend to a partial thickness of the lower mirror. 
     The VCSEL may further include an ohmic contact layer disposed on the upper mirror, in which the ohmic contact layer may include a ring-shaped circular portion and protrusions protruding outwardly from the circular portion, and the oxidation holes may be disposed between the protrusions. 
     The ohmic contact layer may include the protrusions, and the oxidation holes may be disposed between the protrusions, and thus, the oxidation holes may be disposed at narrower intervals, thereby reducing a size of the emitter. 
     The ring-shape of the circular portion may be partially incised. 
     The ohmic contact layer may have a symmetrical structure, such that the protrusions may be spaced apart at an equal interval from one another. 
     The oxidation holes may have an elliptic shape. 
     The oxidation holes may have a circular or a quadrangular shape. 
     The VCSEL may further include a surface protection layer covering the ohmic contact layer and the upper mirror, and an upper insulation layer disposed on the surface protection layer, in which the trench and the oxidation holes may pass through the surface protection layer, and the upper insulation layer may cover the trench and the oxidation holes. 
     The VCSEL may further include a plurality of via holes passing through the upper insulation layer and the surface protection layer to expose the ohmic contact layer, and the via holes may be disposed to correspond to the protrusions. 
     The VCSEL may further include a pad and a connector disposed on the upper insulation layer, in which the pad may be disposed outside of the trench, and the connector may extend from the pad and electrically connected to the ohmic contact layer through the via holes. 
     A VCSEL including an emitter array according to another exemplary embodiment includes: a lower mirror; an upper mirror; an active layer interposed between the lower mirror and the upper mirror; an aperture forming layer interposed between the upper mirror and the active layer, and including an oxidation layer and a window layer surrounded by the oxidation layer; a ring-shaped trench passing through the upper mirror, the aperture forming layer, and the active layer to define an isolation region therein; and a plurality of oxidation holes disposed in the isolation region surrounded by the trench, and passing through the upper mirror and the aperture forming layer, in which the emitter array may include a plurality of emitters and be disposed in the isolation region surrounded by the trench, and the plurality of oxidation holes may be disposed to correspond to the emitters in the emitter array. 
     The oxidation holes together with the trench may be disposed in the isolation region so that the window layer may be formed precisely, and thus, a surface defect may be prevented from moving to the aperture. 
     The trench may be extended to a partial thickness of the lower mirror from the upper mirror. 
     The VCSEL may further include ohmic contact layers disposed on the upper mirror to correspond to each emitter, in which each ohmic contact layer may include a ring-shaped circular portion and protrusions protruding outwardly from the circular portion, and the oxidation holes may be disposed between the protrusions. 
     The ring-shape of the circular portion may be partially incised. 
     The ohmic contact layer may have a symmetrical structure, such that the protrusions may be spaced apart at an equal interval from one another. 
     The VCSEL may further include a surface protection layer covering the ohmic contact layer and the upper mirror, and an upper insulation layer disposed on the surface protection layer, in which the trench and the oxidation holes may pass through the surface protection layer, and the upper insulation layer may cover the trench and the oxidation holes. 
     The VCSEL may further include a plurality of via holes passing through the upper insulation layer and the surface protection layer to expose the ohmic contact layer, and the via holes may be disposed corresponding to the protrusions. 
     The VCSEL may further include a pad and a connector disposed on the upper insulation layer, in which the pad may be disposed outside of the trench, and the connector may extend from the pad and electrically connect to the ohmic contact layer through the via holes. 
     The connector may have a mesh shape including circular openings corresponding to each emitter. 
     The oxidation holes may have at least one of an elliptic, a circular, and a quadrangular shape. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention, and together with the description serve to explain the inventive concepts. 
         FIG. 1  is a schematic plan view of a VCSEL according to an exemplary embodiment. 
         FIG. 2A  is an enlarged schematic plan view of an emitter region of  FIG. 1 . 
         FIG. 2B  is a schematic cross-sectional view taken along line A-A of  FIG. 2A . 
         FIGS. 3A, 3B, 4A, 4B, 5A, and 5B  are schematic plan views and cross-sectional views illustrating a method of manufacturing a VCSEL according to an exemplary embodiment. 
         FIG. 6  is a schematic plan view of a VCSEL according to another exemplary embodiment. 
         FIG. 7A  is an enlarged schematic plan view of a portion of an emitter array of  FIG. 6 . 
         FIG. 7B  is a schematic cross-sectional view taken along line B-B of  FIG. 7A . 
         FIG. 7C  is a schematic cross-sectional view taken along line C-C of  FIG. 7A . 
         FIG. 8  is a schematic plan view illustrating an ohmic contact layer according to another exemplary embodiment. 
         FIGS. 9A, 9B, and 9C  are schematic plan views illustrating oxidation holes for forming an oxidation layer according to exemplary embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. It is apparent, however, that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various exemplary embodiments. Further, various exemplary embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concepts. 
     Unless otherwise specified, the illustrated exemplary embodiments are to be understood as providing exemplary features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts. 
     The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an exemplary embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements. 
     When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z—axes, and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure. 
     Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly. 
     The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art. 
     Various exemplary embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized exemplary embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. 
     Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. 
       FIG. 1  is a schematic plan view of a vertical-cavity surface-emitting laser (VCSEL) according to an exemplary embodiment,  FIG. 2A  is an enlarged schematic plan view of an emitter region of  FIG. 1 , and  FIG. 2B  is a schematic cross-sectional view taken along line A-A of  FIG. 2A . 
     Referring to  FIG. 1 ,  FIG. 2A , and  FIG. 2B , a VCSEL  100  includes an emitter  150 , a pad  40 , and a connector  41 . The emitter  150  includes a lower mirror  25 , an active layer  27 , an aperture forming layer  29 , and an upper mirror  31 . The VCSEL  100  may also include a substrate  21 , a buffer layer  23 , an ohmic contact layer  33 , a surface protection layer  35 , and an upper insulation layer  39 , and a lower electrode  51 . The VCSEL  100  may also include a trench  37  and an isolation region surrounded by the trench  37 , and oxidation holes  29   a  disposed in the isolation region. 
     The substrate  21  may be a conductive substrate, for example, a semiconductor substrate, such as n-type GaAs. The substrate  21  may also be a growth substrate capable of growing semiconductor layers thereon, and may be selected according to the semiconductor layer to be grown. 
     The buffer layer  23  may be formed to assist the growth of the semiconductor layers, but in some exemplary embodiments, the buffer layer  23  may be omitted. When the substrate  21  is a GaAs substrate, the buffer layer  23  may be, for example, a GaAs layer. 
     The lower mirror  25  has a distributed Bragg reflector structure, and may include n-type semiconductor layers. The lower mirror  25  may be formed by, for example, repeatedly stacking semiconductor layers having different refractive indices. For example, the lower mirror  25  may be formed by alternately stacking an AlGaAs layer having a relatively low Al content and an AlGaAs layer having a relatively high Al content. In particular, the lower mirror  25  may be formed by alternately stacking an Al 0.15 Ga 0.85 As layer having an Al content of 15% and an Al 0.85 Ga 0.15 As layer having an Al content of 85%. As an n-type impurity, Si may be doped at a concentration of approximately 1 to 3×10 18 /cm 3 . The lower mirror  25  may include, for example, 30 or more pairs of semiconductor layers having different refractive indices. A thickness of each layer in the lower mirror  25  may be set to be one-fourth of a wavelength of light in each layer. One pair of semiconductor layers having different refractive indices may have a thickness in a range of about 100 nm to about 200 nm. 
     The active layer  27  may be disposed on the lower mirror  25 , and may contact the lower mirror  25 . The active layer  27  may have a barrier layer and a well layer, and the well layer may be interposed between the barrier layers. In particular, the active layer  27  may have a multi-quantum well structure having a plurality of well layers, and may include, for example, a stacked structure of GaAs/InGaAs/GaAs. Compositions of the barrier layer and the well layer may be varied according to a desired laser wavelength, and the well layer may include, for example, an InAlGaAs-based four-component, three-component, or two-component system. In addition, although the active layer  27  according to the illustrated exemplary embodiment is described as being GaAs-based, the inventive concepts are not limited thereto. For example, in some exemplary embodiments, InAlGaN-based or InAlGaP-based semiconductor layers may be used, and in this case, the barrier layer and the well layer may have a nitride-based or phosphide-based composition. 
     The well layer in the active layer  27  may be formed of an un-doped layer, and the barrier layer may also be formed of the un-doped layer. A thickness of the well layer may be about 2 nm to about 8 nm, and a thickness of the barrier layer may be approximately in a range of 2 nm to 15 nm. 
     The upper mirror  31  is disposed on the active layer  27 . The upper mirror  31  may have a distributed Bragg reflector structure, and may include p-type semiconductor layers. The upper mirror  31  may be formed by, for example, repeatedly stacking semiconductor layers having different refractive indices. For example, the upper mirror  31 , like the lower mirror  25 , may be formed by alternately stacking an AlGaAs layer having a relatively low Al content and an AlGaAs layer having a relatively high Al content. In particular, the upper mirror  31  may be formed by alternately stacking an Al 0.15 Ga 0.85 As layer having an Al content of 15% and an Al 0.85 Ga 015 As layer having an Al content of 85%. As a p-type impurity, for example, C may be doped at a concentration of about 1 to 5×10 18 /cm 3 . The upper mirror  31  may include, for example, 20 or more pairs of semiconductor layers having different refractive indices. However, the number of pairs in the upper mirror  31  may be relatively smaller than that in the lower mirror  25 . Meanwhile, a thickness of each layer may be set to be one-fourth of a wavelength of light in each layer. 
     The aperture forming layer  29  is disposed between the active layer  27  and the upper mirror  31 . The aperture forming layer  29  may include an oxidation layer  29   x  and a window layer  29   w . The window layer  29   w  is surrounded by the oxidation layer  29   x , thereby forming an aperture defining a passage of current. The aperture forming layer  29  may be formed of, for example, an AlGaAs layer having a higher Al content than the layers in the upper mirror  31 . For example, an Al content in the aperture forming layer  29  may be about 90% or more. The oxidation layer  29   x  is formed by oxidizing the AlGaAs layer in a region except the window layer  29   w.    
     A width of the aperture formed by the oxidation layer  29   x , that is, a width t of the window layer  29   w  is not particularly limited, but may be, for example, in a range of 3 μm to 12 μm. 
     Although the window layer  29   w  or the aperture is shown as having a disk shape in  FIG. 2A , however, the inventive concepts are not limited thereto. The window layer  29   w  may have the disk shape, but may have other shapes, such as a polygonal shape close to the disk in other exemplary embodiments. 
     The ohmic contact layer  33  is disposed on the upper mirror  31 . In particular, the ohmic contact layer  33  may form an ohmic contact with the upper mirror  31  on the isolation region surrounded by the trench  37 . The ohmic contact layer  33  may include, for example, Ti, Pt, and Au, and ohmic contact may be formed using a rapid thermal annealing process, for example. The ohmic contact layer  33 , as shown in  FIG. 2A , may include a partial ring-shaped circular portion  33   a  and protrusions  33   b  protruding outwardly from the circular portion  33   a . The protrusions  33   b  may increase a connection area for the connection of pad  40 . 
     The surface protection layer  35  protects the upper mirror  31  and the ohmic contact layer  33  while forming the trench  37 . The surface protection layer  35  may be, in particular, used as an etching mask. The surface protection layer  35  may be formed of a light transmissive substance, and may be formed of, for example, a silicon oxide film or a silicon nitride film. The surface protection layer  35  may also be formed to have a thickness, which is an integer multiple of one-fourth of a light wavelength in the surface protection layer  35 . For example, when the surface protection layer  35  is formed of Si 3 N 4 , the surface protection layer  35  may be formed to have a thickness that is an integer multiple of about 118 nm. In addition, the surface protection layer  35  may be formed to have a tensile strain, and thus, may be formed at, for example, 250° C. 
     The trench  37  may pass through the upper mirror  31 , the aperture forming layer  29 , and the active layer  17 , and to a partial thickness of the lower mirror  25 . The trench  37  may have a substantially ring shape to define an isolation region therein, and the emitter  150  is formed in the isolation region. A width of the trench  37  may be in a range of 20 nm to 30 um, without being limited thereto. In addition, an outer wall of the trench  37  has substantially a circular shape, an inner side is a shape including a concave portion and a convex portion, without being limited thereto, and may be formed in a ring shape of various shapes in other exemplary embodiments. 
     Although all regions other than the window layer  29   w  are shown as the oxidation layer  29   x  in  FIG. 2B , in some exemplary embodiments, a non-oxidation layer such as the window layer  29   w  may be retained outside of the trench  37 . The aperture forming layer  29  in the isolated region surrounded by the trench  37  is oxidized and be formed as the oxidation layer, except for the window layer  29   w.    
     The trench  37  improves light efficiency by preventing current from flowing to other regions except for the aperture, e.g., window layer  29   w.    
     Oxidation holes  29   a  are formed to expose the aperture forming layer  29 . To this end, the oxidation holes  29   a  may pass through the upper mirror  31  and the aperture forming layer  29 , and may further pass through the active layer  27  and some thicknesses of the lower mirror  25 . The oxidation holes  29   a  may also pass through the surface protection layer  35 . 
     The oxidation holes  29   a  may be disposed outside of the ohmic contact layer  33 , and in particular, may be disposed between the protrusions  33   b . Further, the oxidation holes  29   a  are formed on the isolation region surrounded by the trench  37 . The oxidation holes  29   a  are disposed in the isolation region away from the trench  37 , and thus, defects that may occur during formation of the trench  37  may be prevented from moving into the aperture while forming the oxidation layer  29   x . In addition, since the ohmic contact layer  33  is formed to have the protrusions  33   b , the oxidation holes  29   a  may be disposed closer to one another, thereby reducing the size of the emitter  150 . 
     In addition, the oxidation holes  29   a  may be formed to have sizes smaller than those of the protrusions  33   b , respectively. For example, a planar area of the oxidation hole  29   a  may be smaller than that of the protrusion  33   b . The sizes of the oxidation holes  29   a  are made to be relatively small, such that infiltration of moisture or the like through the oxidation holes  29   a  may be suppressed after the oxidation layer  29  is formed. For example, a depth of the oxidation holes  29   a  may be about 3 μm, and a diameter of the hole may be about 4 μm. 
     The aperture forming layer  29  is oxidized through the oxidation holes  29   a , thereby defining the oxidation layer  29   x  and the window layer  29   w . In this case, the upper mirror  31 , the active layer  27 , and the lower mirror  25  exposed to sidewalls of the oxidation holes  29   a  may be partially oxidized. According to the illustrated exemplary embodiment, the aperture is formed using the oxidation holes  29   a  rather than using the trench  37 , and thus, it is possible to precisely form a small aperture while the isolation region is formed to have a relatively large size, thereby reducing the time required for the oxidation process. Furthermore, the size of the isolation region may be formed to be relatively large, and thus, a width of the ohmic contact layer  33  may be made to be relatively large, and, in particular, it is possible to form the protrusions  33   b , thereby increasing a connection area of the pad  40 . 
     The upper insulation layer  39  covers the surface protection layer  35 , and covers the trench  37  and the oxidation holes  29   a . The trench  37 , the upper mirror  31 , the oxidation layer  29   x , the active layer  27 , and the lower mirror  25  exposed in the oxidation holes  29   a  are covered with the upper insulation layer  39  to be insulated. The upper insulation layer  39  may be formed of a light transmissive substance, and may be formed of, for example, a silicon oxide film or a silicon nitride film. The upper insulation layer  39  may also be formed to have a thickness which an integer multiple of one-fourth of a light wavelength in the upper insulation layer  39 . For example, when the upper insulation layer  39  is formed of Si 3 N 4 , a thickness thereof may be about 200 nm, 300 nm, or 500 nm. In addition, the upper insulation layer  39  is formed to have a tensile strain, and thus, may be formed at 250° C., for example. 
     Via holes  39   a  passing through the upper insulation layer  39  and the surface protection layer  35  to expose the ohmic contact layer  33  are formed. The via holes  39   a  are disposed to correspond to the protrusions  33   b  of the ohmic contact layer  33 . As shown in  FIG. 2A , the via holes  39   a  may be formed to expose the protrusion  33   b  and the circular portion  33   a  together. Although the via holes  39   a  are illustrated as having a quadrangular shape in  FIG. 2A , the shapes thereof are not particularly limited and may be circular in some exemplary embodiments. 
     The pad  40  and the connector  41  may be disposed on the upper insulation layer  39 . The pad  40  is a region for bonding wires, and is disposed over a relatively wide region. The pad  40  may be disposed, for example, outside of the trench  37  to reduce parasitic capacitance. 
     The connector  41  electrically connects the pad  40  and the ohmic contact layer  33 . The connector  41  may be connected to the ohmic contact layer  33  through the via holes  39   a . The connector  41  may have a partial ring-shaped circular portion along the ohmic contact layer  33 , and an opening  41   a  may be provided inside the ring-shaped circular portion to emit a laser beam. 
     The pad  40  and the connector  41  may be formed of the same metal material, for example, Ti/Pt/Au. The pad  40  and the connector  41  may be formed to have a thickness of about 2 μm or more. 
     A lower electrode  51  is disposed under the substrate  21 , and may be used as, for example, an n-pad. When the substrate  21  is a GaAs substrate, the lower electrode  51  may be formed of AuGe/Ni/Au, which may have a thickness of about 900 Å, 300 Å, 1000˜3000 Å, respectively, for example. 
       FIGS. 3A, 3B, 4A, 4B, 5A, and 5B  are schematic plan views and cross-sectional views illustrating a method of manufacturing a VCSEL according to an exemplary embodiment. Each cross sectional view is a view taken along line A-A of the corresponding plan view. 
     Referring to  FIG. 3A  and  FIG. 3B , semiconductor layers  23 ,  25 ,  27 ,  29 , and  31  are formed on a substrate  21 , and an ohmic contact layer  33  is formed. 
     The substrate  21  may be, for example, an n-type GaAs substrate. The semiconductor layers may include a buffer layer  23 , a lower mirror  25 , an active layer  27 , an aperture forming layer  29 , and an upper mirror  31 . The semiconductor layers may be formed using, for example, epitaxial growth techniques, such as metal organic chemical vapor deposition or molecular beam epitaxy. 
     The buffer layer  23  may be formed of, for example, a GaAs layer on the substrate  21 . The lower mirror  25  may be formed on the buffer layer  23 , and the active layer  27 , the aperture forming layer  29 , and the upper mirror  31  may be sequentially formed on the lower mirror  25 . The lower mirror  25  and the upper mirror  31  may be formed by repeatedly stacking AlGaAs/AlGaAs having different Al compositions, respectively. Since the structures of the lower mirror  25 , the active layer  27 , the aperture forming layer  29 , and the upper mirror  31  have been already described above, repeated descriptions thereof will be omitted to avoid redundancy. 
     The ohmic contact layer  33  is formed on the upper mirror  31 . The ohmic contact layer  33  is formed to include a partial ring-shaped circular portion  33   a  and protrusions  33   b  protruding outwardly from the circular portion  33   a . The ohmic contact layer  33  may be heat-treated through a rapid thermal annealing process after forming a metal layer using a lift-off technique. The metal layer may be formed of, for example, Ti/Pt/Au, which may be formed to have thicknesses of about 300 Å, 300 Å, and 1000 to 3000 Å, respectively. The thermal annealing process may provide a favorable ohmic contact between the ohmic contact layer  33  and the upper mirror  31 . 
     Although  FIG. 3A  exemplarily shows that a single ohmic contact layer  33  is formed on the substrate  21 , in some exemplary embodiments, the substrate  21  may have a diameter of, for example, 10 mm, and multiple ohmic contact layers  33  may be formed in each device region. 
     In addition, although the ohmic contact layer  33  may use a negative photoresist or a positive photoresist as a mask, the positive photoresist is more suitable for forming a high density array. 
     Referring to  FIG. 4A  and  FIG. 4B , a surface protection layer  35  covering the upper mirror  31  and the ohmic contact layer  33  is formed. The surface protection layer  35  protects the upper mirror  31  while forming a trench  37  and oxidation holes  29   a.    
     The surface protection layer  35  may be formed of, for example, Si 3 N 4  or SiO 2 , and may have a thickness which is an integer multiple of one-fourth of a light wavelength in the surface protection layer  35 . For example, when the surface protection layer  35  is formed of Si 3 N 4 , a thickness thereof may be formed to be an integer multiple of about 118 nm. 
     Next, a photoresist is formed on the surface protection layer  3 , and the trench  37  and the oxidation holes  29   a  are formed by performing an etching process using the photoresist as a mask. An isolation region surrounded by the trench  37  is formed by the trench  37 , and the oxidation holes  29   a  are disposed around the ohmic contact layer  33  in the isolation region, while being spaced apart from the trench  37 . The photoresist may be removed after the etching process is complete. 
     The trench  37  and the oxidation holes  29   a  may pass through the surface protection layer  35 , the upper mirror  31 , the aperture forming layer  29 , and the active layer  27 , and to a partial thickness of the lower mirror  25 . 
     The oxidation holes  29   a  may be disposed between the protrusions  33   b , and may have sizes smaller than those of the protrusions  33   b . The oxidation holes  29   a  have a depth of about 3 μm, a diameter (or width) of about 4 μm at a side of an inlet, and sidewalls thereof may be inclined at about 80 degrees. Shapes of the oxidation holes  29   a  may vary, which will be described in more detail later with reference to  FIGS. 9A through 9C . Since the ohmic contact layer  33  is formed to have the protrusions  33   b , the width of the circular portion  33   a  may be reduced, thereby reducing a distance between the oxidation holes  29   a.    
     Subsequently, the aperture forming layer  29  exposed through the oxidation holes  29   a  is oxidized. Oxidation may be performed at a temperature in a range of 400° C. to 430° C., for example. By adjusting an Al composition ratio of the aperture forming layer  29 , the temperature and composition of the aperture forming layer  29  may be set to exhibit an oxidation rate of 10 times or more than those of the layers in the lower and upper mirrors  25  and  31 . 
     An oxidation layer  29   x  is formed by the oxidation process in the aperture forming layer  29  around the trench  37  and the oxidation holes  29   a . The oxidation layer  29   x  proceeds to the inside of the aperture forming layer  29  through the aperture forming layer  29  exposed to inner walls of the trench  37  and the oxidation holes  29   a . Accordingly, a window layer  29   w  (aperture) is formed under a region surrounded by the ohmic contact layer  33 . Meanwhile, as shown in  FIG. 4B , a portion of the oxidation layer  29   x  may also be formed in an outer region of the trench  37 . 
     Since the oxidation proceeds at a relatively high temperature of 400° C. to 430° C., surface defects generated while forming the trench  37  may move. At this time, since the oxidation hole  29   a  are disposed in the isolation region, the defects may be prevented from moving toward the window layer  29   w.    
     Referring to  FIG. 5A  and  FIG. 5B , an upper insulation layer  39  is formed on the surface protection layer  35 . The upper insulation layer  39  may be formed of a light transmissive substance, and may be formed of, for example, Si 3 N 4  or SiO 2 . The upper insulation layer  39  covers sidewalls and bottoms of the trench  37  and the oxidation holes  29   a  to insulate semiconductor layers exposed in the trench  37  and the oxidation holes  29   a.    
     Via holes  39   a  may be formed by patterning the upper insulation layer  39  and the surface protection layer  35  to expose the ohmic contact layer  33 . The via holes  39   a  may be formed to correspond to the protrusions  33   b  of the ohmic contact layer  33 , as shown in  FIG. 5A . 
     According to an exemplary embodiment, when the via holes  39   a  are formed, a device isolation region, for example, a scribing line to divide a plurality of device regions formed on the substrate  21  may be formed together. The scribing line may be formed by etching the surface protection layer  35  and the upper insulation layer  39 , such that the surface protection layer  35  and the upper insulation layer  39  are prevented from being peeled off during a subsequent scribing process to individualize the devices. 
     Subsequently, a pad  40  and a connector  41  are formed, as shown in  FIG. 1 . The pad  40  and the connector  41  may be formed using a lift off technique, and may be formed of, for example, Ti/Pt/Au. In addition, a lower electrode  51  may be formed on a lower surface of the substrate  21 . 
     Thereafter, the devices are individualized along the scribing line, thereby forming the VCSEL of  FIG. 1 . 
       FIG. 6  is a schematic plan view of a VCSEL according to another exemplary embodiment,  FIG. 7A  is an enlarged schematic plan view of a portion of an emitter array of  FIG. 6 ,  FIG. 7B  is a schematic cross-sectional view taken along line B-B of  FIG. 7A , and  FIG. 7C  is a schematic cross-sectional view taken along line C-C of  FIG. 7A . 
     Referring to  FIG. 6 ,  FIG. 7A ,  FIG. 7B , and  FIG. 7C , a VCSEL  200  is generally similar to the VCSEL  100  described with reference to  FIG. 1 ,  FIG. 2A , and  FIG. 2B , except that a plurality of emitter arrays  250  are included, and accordingly, shapes of the trench  37  and the pad  40  are modified. As such, repeated descriptions of the substantially the same elements of the VCSEL already described above will be omitted. 
     The trench  37  is formed to have a ring shape to define an isolation region therein. The emitter array  250  may be disposed in the isolated region surrounded by the ring-shaped trench  37 , and the pad  40  is located outside of the trench  37 . Emitters in the emitter array  250  may be arranged in a honeycomb shape, for example, as shown in the drawing. 
     The pad  40  may be formed adjacent to a region of the emitter array  250  and on one side of the substrate  21 . In the illustrated exemplary embodiment, as shown in  FIG. 6 , the pad  40  may be formed over a wide area outside of the trench  37  to facilitate electrical connection. However, the inventive concepts are not limited thereto, and in some exemplary embodiments, the pad  40  may be formed to a shape similar to that shown in  FIG. 1 . 
     The trench  37  is formed to have a relatively greater width than a thickness of the pad  40 . For example, the pad  40  may be formed to have a thickness of 2 μm to 6 μm and the trench  37  may be formed to have a relatively greater width of 20 μm to 30 μm. Accordingly, disconnection of a connector  41  due to the trench  37  may be prevented. 
     As shown in  FIG. 7A , an ohmic contact layer  33 , oxidation holes  29   a , and via holes  39   a  are formed in each emitter region, and an opening  41   a , through which the laser can be emitted, is formed by the connector  41 . Each emitter includes a lower mirror  25 , an active layer  27 , an aperture forming layer  29 , and an upper mirror  31 , like those described with reference to  FIG. 1 ,  FIG. 2A , and  FIG. 2B . The aperture forming layer  29  includes an oxidation layer  29   x  and a window layer  29   w . The aperture forming layer  29  in the emitter array  250  is the oxidation layer  29   x , except for the window layer  29   w , and thus, current flow is limited to the window layer  29   w . A basic structure of each emitter in the emitter array  250  is substantially the same as that of the emitter  150  described above. 
     An ohmic contact layer  33  may be formed in each emitter, and, as described above, the ohmic contact layer  33  may include a partial ring-shaped circular portion  33   a  and protrusions  33   b . Further, in each emitter region, oxidation holes  29   a  are disposed between the protrusions  33   b , and via holes  39   a  are formed to correspond to the protrusions  33   b . The oxidation holes  29   a  and the via holes  39   a  formed in each emitter are substantially the same as those formed in the emitter  150  described above. In particular, by forming the oxidation holes  29   a  separately in each emitter, sizes of the oxidation holes  29   a  may be smaller than those of the protrusions  33   b , thereby improving reliability of the device. 
     The connector  41  connecting the pad  40  and the ohmic contact layers  33  may be connected to each emitter through the via holes  39   a . Each of the emitters may be connected in parallel. Although the connector  41  described above has the partial ring shape, the connector  41  according to the illustrated exemplary embodiment may have a mesh shape forming circular openings  41   a  as shown in the drawings. 
     Further, the connector  41  may cover all of the trenches  37 , and, accordingly, disconnection of the connector  41  in the trench  37  may be further prevented. 
     Since a manufacturing method of the VCSEL  200  having the emitter array  250  is substantially similar to that of the VCSEL  100  described above, repeated descriptions thereof will be omitted. 
     According to the illustrated exemplary embodiment, the emitters in the emitter array  250  are not separated from one another by the trench. Accordingly, it is possible to prevent the connector  41  from being disconnected in the trench, which may provide a large step difference. Further, damage to the window layer  29   w  due to surface defects caused during the formation of the trench may be prevented, thereby providing a highly reliable emitter array. 
       FIG. 8  is a schematic plan view for illustrating an ohmic contact layer according to another exemplary embodiment. 
     Referring to  FIG. 8 , unlike the ohmic contact layer  33  including the partial ring-shaped circular portion  33   a  and protrusions  33   b , an ohmic contact layer  133  according to the illustrated exemplary embodiment includes a ring-shaped circular portion  133   a  and protrusions  133   b . That is, the circular portion  133   a  according to the illustrated exemplary embodiment has a constant width and a closed circular ring shape, and the protrusions  133   b  are spaced apart from one another at a regular interval and are disposed symmetrically. In this case, oxidation holes may be disposed between the protrusions  133   b.    
     The ohmic contact layer  133  are symmetrically formed, and thus, an aperture  29   w  formed therein may be formed to have a shape closer to a circle. 
     The oxidation holes  29   a  have been described as being disposed around the ohmic contact layer  33 , and each of the oxidation holes  29   a  has been described as having an elliptic shape. Long axes of the oxidation holes  29   a  are disposed in a direction perpendicular to a straight line connecting a center of the emitter  150  and a center of the oxidation hole  29   a , respectively. Accordingly, the shape of the window layer  29   w  (aperture) surrounded by the oxidation layer  29   x  formed by using the oxidation holes  29   a  becomes almost circular. 
     However, the inventive concepts are not limited to a particular shape of the oxidation holes  29   a , and the shape of the oxidation holes  29   a  may be variously modified.  FIGS. 9A through 9C  are schematic plan views illustrating oxidation holes for forming the oxidation layer according to exemplary embodiments. 
     As shown in  FIG. 9A , the oxidation holes  29   b  may have substantially a circular shape. Oval or circular oxidation holes  29   a  and  29   b  may be easily patterned, and may increase stability of the upper insulation layer  39  or the connector  41  formed thereon. Meanwhile, as shown in  FIG. 9B , the oxidation holes  29   c  may have substantially a square or rectangular shape and be disposed at locations corresponding to each vertex of the regular hexagon. In addition, as shown in  FIG. 9C , although the oxidation holes  29   d  may have a quadrangular shape, a side close to the center of the emitter may be curved. 
     Moreover, in some exemplary embodiments, the number of oxidation holes surrounding the center of the emitter may be greater than six, and, accordingly, it is possible to form the shape of the aperture much closer to a circle. 
     Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art.