Patent Publication Number: US-10789868-B2

Title: Shift register circuit and method for driving the same, gate driving circuit and method for driving the same, and display apparatus

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority to the Chinese Patent Application No. 201810002108.2, filed on Jan. 2, 2018, which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present disclosure relates to the field of display technologies, and more particularly, to a shift register circuit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. 
     BACKGROUND 
     A gate driving circuit in the related art is composed of multiple stages of cascaded shift register circuits, and each of the stages of shift register circuits is connected to a corresponding gate line, so that a scanning signal is input to various rows of gate lines in a display panel sequentially through various stages of shift register circuits. However, such a gate driving circuit has a complicated structure design, and occupies a large space of the display panel, which is disadvantageous for ultra-narrow bezel design of the display panel. 
     SUMMARY 
     The embodiments of the present disclosure provide a shift register circuit, comprising an input circuit, a reset circuit, a control circuit and a multi-output circuit, wherein 
     the input circuit is configured to receive an input signal and output a signal to a first node based on the input signal; 
     the reset circuit is configured to receive a reset signal and a first reference signal, and output the first reference signal to the first node under control of the reset signal; 
     the control circuit is configured to control a potential at the first node to be an inverted potential of a potential at the second node; and 
     the multi-output circuit is configured to receive the first reference signal and M clock signals, and output M driving signals according to the corresponding clock signals and the first reference signal under the control of signals at the first node and the second node, where M is an integer greater than or equal to 2. 
     In an embodiment, the multi-output circuit comprises M output sub-circuits each configured to receive the first reference signal and a corresponding one of the M clock signals, and output a corresponding driving signal according to the received first reference signal and corresponding clock signal under the control of the signals at the first node and the second node. 
     In an embodiment, the output sub-circuit comprises a first switch transistor, a second switch transistor, and a storage capacitor, wherein 
     the first switch transistor has a gate connected to the first node, a first electrode configured to receive a corresponding clock signal, and a second electrode configured to output a corresponding driving signal; 
     the second switch transistor has a gate connected to the second node, a first electrode configured to receive the first reference signal, and a second electrode configured to output the corresponding driving signal; and 
     the storage capacitor is connected between the first node and the second electrode of the first switch transistor. 
     In an embodiment, the M driving signals are sequentially defined as a first driving signal to an M th  driving signal in a scanning order; and 
     the reset circuit is further configured to receive the M th  driving signal, a second reference signal, and a frame reset signal, and output the first reference signal to the first node under the control of all the M th  driving signal, the frame reset signal, and the reset signal. 
     In an embodiment, the reset circuit comprises a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, and a stabilization capacitor, wherein 
     the third switch transistor has a gate configured to receive the M th  driving signal, a first electrode configured to receive the second reference signal, and a second electrode connected to a gate of the fourth switch transistor; 
     the fourth switch transistor has a first electrode configured to receive the reset signal, and a second electrode connected to a gate of the fifth switch transistor; 
     the fifth switch transistor has a first electrode configured to receive the first reference signal, and a second electrode connected to the first node; 
     the sixth switch transistor has a gate configured to receive the frame reset signal, a first electrode configured to receive the first reference signal, and a second electrode connected to the gate of the fourth switch transistor; and 
     the stabilization capacitor is connected between the gate of the fourth switch transistor and the gate of the fifth switch transistor. 
     In an embodiment, the input circuit comprises a seventh switch transistor, wherein 
     the seventh switch transistor has a gate and a first electrode both configured to receive the input signal, and a second electrode connected to the first node. 
     In an embodiment, the control circuit comprises a first control sub-circuit and a second control sub-circuit, wherein 
     the first control sub-circuit is configured to receive the first reference signal, and output the first reference signal to the first node under control of a signal at the second node; and 
     the second control sub-circuit is configured to receive the first reference signal and a second reference signal, output the second reference signal to the second node under control of only the second reference signal, and output the first reference signal to the second node under control of a signal at the first node. 
     In an embodiment, the first control sub-circuit comprises an eighth switch transistor, wherein 
     the eighth switch transistor has a gate connected to the second node, a first electrode configured to receive the first reference signal, and a second electrode connected to the first node. 
     In an embodiment, the second control sub-circuit comprises a ninth switch transistor, a tenth switch transistor, an eleventh switch transistor, and a twelfth switch transistor, wherein 
     the ninth switch transistor has a gate and a first electrode both configured to receive the second reference signal, and a second electrode connected to a gate of the tenth switch transistor; 
     the tenth switch transistor has a first electrode configured to receive the second reference signal, and a second electrode connected to the second node; 
     the eleventh switch transistor has a gate connected to the first node, a first electrode configured to receive the first reference signal, and a second electrode connected to the second node; and 
     the twelfth switch transistor has a gate connected to the first node, a first electrode configured to receive the first reference signal, and a second electrode connected to the gate of the tenth switch transistor. 
     In an embodiment, the shift register circuit further comprises M frame reset circuits in one-to-one correspondence to the M output sub-circuits, and each configured to receive a frame reset signal and the first reference signal, and reset a driving signal output by a corresponding output sub-circuit according to the first reference signal under the control of the frame reset signal. 
     In an embodiment, the frame reset circuit comprises a thirteenth switch transistor, wherein 
     the thirteenth switch transistor has a gate configured to receive the frame reset signal, a first electrode configured to receive the first reference signal, and a second electrode configured to output the first reference signal to reset the driving signal. 
     The embodiments of the present disclosure further provide a gate driving circuit, comprising N cascaded shift register circuits according to any of the above embodiments, wherein the M driving signals are sequentially defined as a first driving signal to an M th  driving signal in a scanning order, where N is a positive integer greater than 1, wherein 
     an input signal of a first stage of shift register circuit is a frame start signal; and 
     an input signal of each of remaining stages of shift register circuits other than the first stage of shift register circuit is an n th  driving signal of a previous stage of shift register circuit 
     where when M is an even, 
               n   =       M   2     +   1       ,         
and when M is an odd,
 
     
       
         
           
             n 
             = 
             
               
                 
                   M 
                   + 
                   1 
                 
                 2 
               
               . 
             
           
         
       
     
     In an embodiment, various stages of shift register circuits receive the same reset signal, wherein the reset signal is a periodic square wave signal, with each cycle comprising a turn-on period in which the reset circuit is turned on and a turn-off period in which the reset circuit is turned off, wherein each of the turn-on periods comprises a first edge and a second edge appearing successively in time, and 
     wherein a first edge of a turn-on period of an i th  cycle of the reset signal is synchronized with or lags behind a second edge of a current period of an M th  clock signal in an i th  stage of shift register circuit, and is synchronized with or is ahead of a first edge of a next cycle of the M th  clock signal, where 1≤i≤N. 
     In an embodiment, various stages of shift register circuits receive the same frame reset signal, wherein a first edge of the frame reset signal lags behind or is synchronized with a second edge of a last clock signal in a last stage of shift register circuit in a current period, and a second edge of the frame reset signal is ahead of or synchronized with a first edge of a first clock signal in a first stage of shift register circuit in a next period. 
     The embodiments of the present disclosure further provide a display apparatus, comprising a plurality of gate lines and the gate driving circuit according to any of the above embodiments, wherein each stage of shift register circuit drives M gate lines of the plurality of gate lines, respectively. 
     The embodiments of the present disclosure further provide a method for driving the shift register circuit according to any of the above embodiments, comprising an input phase, an output phase, and a reset phase, comprising: 
     in the input phase, outputting a signal to the first node through the input circuit based on the input signal, 
     in the output phase, outputting M driving signals according to the M clock signals through the output circuit under the control of the signal at the first node, and 
     in the reset phase, outputting the first reference signal to the first node through the reset circuit under the control of the reset signal, and outputting the M driving signals through the multi-output circuit according to the first reference signal under the control of the signal at the second node. 
     The embodiments of the present disclosure further provide a method for driving the shift register circuit according to any of the above embodiments, comprising: 
     in a display driving phase, performing the method according to any of the above embodiments for each stage of shift register circuit in the gate driving circuit; and 
     in a blanking time phase, resetting each of the driving signals in each stage of shift register circuit through the frame reset circuit by using the first reference signal under the control of the frame reset signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a structural diagram of a shift register circuit according to an embodiment of the present disclosure; 
         FIG. 2 a    is a structural diagram of a shift register circuit according to an embodiment of the present disclosure; 
         FIG. 2 b    is a structural diagram of a shift register circuit according to an embodiment of the present disclosure; 
         FIG. 3  is a specific structural diagram of a shift register circuit according to an embodiment of the present disclosure; 
         FIG. 4  is a specific structural diagram of a shift register circuit according to an embodiment of the present disclosure; 
         FIG. 5  is a circuit timing diagram according to an embodiment of the present disclosure; 
         FIG. 6  is a flowchart of a method for driving a shift register circuit according to an embodiment of the present disclosure; 
         FIG. 7  is a structural diagram of a gate driving circuit according to an embodiment of the present disclosure; 
         FIG. 8  is a diagram of a clock signal transmitted on a clock signal line connected to the gate driving circuit shown in  FIG. 7 ; 
         FIG. 9  is a timing diagram of a driving signal output by the gate driving circuit shown in  FIG. 7 ; 
         FIG. 10  is a structural diagram of a display apparatus according to an embodiment of the present disclosure; and 
         FIG. 11  is a flowchart of a method for driving a gate driving circuit according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In order to make the purposes, technical solutions and advantages of the present disclosure more clear, specific implementations of the shift register circuit and the method for driving the same, the gate driving circuit and the display apparatus according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are to be construed as being illustrating and explaining the present disclosure only and not to limit the present disclosure. The embodiments in the present application and the features in the embodiments can be combined with each other without a conflict. 
     In the following description of the present disclosure, a specific structure of each part of the shift register circuit will be described by way of example. In a specific implementation, a specific structure of each part of the circuit is not limited to the structure according to the embodiments of the present disclosure, and may also be other structures known to those skilled in the art, which will not be limited here. 
     Further, in a specific implementation, in the following embodiments, all the switch transistors are set as N-type transistors. It should be understood that in other embodiments, all the switch transistors may also be P-type transistors. In this case, the technical solutions according to the present disclosure can be realized only by inverting a level of a control signal, which is not limited here in the present disclosure. 
     It should be noted that, in the shift register circuit according to the embodiments of the present disclosure, when all the transistors are N-type transistors, a first reference signal is a high potential signal, and a second reference signal is a low potential signal. When all the transistors are P-type transistors, the first reference signal is a low potential signal and the second reference signal is a high potential signal. 
     It should also be understood that a source and a drain of a transistor are interchangeable. Without loss of generality, in the embodiments of the present disclosure, a source of a transistor acts as a first electrode and a drain of the transistor acts as a second electrode. Similarly, the drain of the transistor may act as a first electrode and the source of the transistor may act as a second electrode, which are not specifically distinguished from each other here. 
     The embodiments of the present disclosure provide a shift register circuit, as shown in  FIG. 1 , comprising: an input circuit  1 , a reset circuit  2 , a control circuit  3 , and a multi-output circuit  4 . 
     The input circuit  1  is configured to receive an input signal Input and output a signal to a first node A based on the input signal Input. For example, the output signal may be, for example, the input signal Input or 0. 
     The reset circuit  2  is configured to receive a reset signal Reset and a first reference signal Vref 1 , and output the first reference signal Vref 1  to the first node A under the control of the reset signal Reset. 
     In an embodiment, the reset signal Reset may be an output signal from another stage of shift register circuit. In another embodiment, as will be described below, the reset signal Reset may be a predetermined square wave signal which is common to all shift register circuits and is not related to association among various stages of shift register circuits. 
     The control circuit  3  is configured to control a potential at the first node A to be an inverted potential of a potential at the second node B. 
     In an embodiment, as shown in  FIGS. 2 a  and 2 b   , the control circuit may comprise a first control sub-circuit  31  and a second control sub-circuit  32 . 
     The first control sub-circuit  31  is configured to receive the first reference signal Vref 1 , and output the first reference signal Vref 1  to the first node A under the control of a signal at the second node B. 
     The second control sub-circuit  32  is configured to receive the first reference signal Vref 1  and a second reference signal Vref 2 , output the second reference signal Vref 2  to the second node B under the control of only the second reference signal Vref 2 , and output the first reference signal Vref 1  to the second node B under the control of a signal at the first node A. In this way, the potentials at the first node A and the second node B are controlled to be inverted, which prevents the potentials at the first node A and the second node B from interfering with an output driving signal. 
     The multi-output circuit  4  is configured to receive the first reference signal Vref 1  and M clock signals CK_m (where m is an integer, and 1≤m≤M; and M=3 is taken as an example in  FIG. 1 ), and M driving signals Output_m are output according to each clock signal CK_m and the first reference signal Vref 1  under the control of the signals at the first node A and the second node B; where M is an integer greater than or equal to 2. 
     In an embodiment, as shown in  FIGS. 2 a  and 2 b    (M=3 is taken as an example in both  FIGS. 2 a  and 2 b   ), the multi-output circuit may comprise M output sub-circuits  41 _ m  each configured to receive the first reference signal Vref 1  and a corresponding one of the M clock signals CK_m, and output a corresponding driving signal Output_m according to the received first reference signal Vref 1  and corresponding one of the M clock signals CK_m under the control of the signals at the first node A and the second node B. Thus, each output sub-circuit outputs a driving signal. 
     In the embodiment of  FIGS. 2 a  and 2 b   , each output sub-circuit is connected to a clock signal, and different output sub-circuits are connected to different clock signals. Therefore, the output sub-circuits are in one-to-one correspondence to the clock signals, and it may be considered that each output sub-circuit  41 _ m  is connected to a “corresponding clock signal CK_m”. 
       FIGS. 3 and 4  illustrate a more detailed exemplary structure of the shift register circuit of  FIGS. 2 a    and  2   b.    
     As shown in  FIGS. 3 and 4 , in an embodiment, the input circuit  1  may comprise a seventh switch transistor M 7 . 
     The seventh switch transistor M 7  has a gate and a first electrode both configured to receive the input signal Input, and a second electrode connected to the first node A. 
     Specifically, when the seventh switch transistor is turned on under the control of the input signal, the input signal may be transmitted to the first node to control the potential at the first node. 
     In an embodiment, the reset circuit  2  may comprise a third switch transistor M 3 , a fourth switch transistor M 4 , a fifth switch transistor M 5 , a sixth switch transistor M 6 , and a stabilization capacitor C 0 . 
     The third switch transistor M 3  has a gate configured to receive an M th  driving signal Output_M, i.e., receiving a third driving signal Output_ 3 , a first electrode configured to receive the second reference signal Vref 2 , and a second electrode connected to a gate of the fourth switch transistor M 4 . 
     The fourth switch transistor M 4  has a first electrode configured to receive the reset signal Reset, and a second electrode connected to a gate of the fifth switch transistor M 5 . 
     The fifth switch transistor M 5  has a first electrode configured to receive the first reference signal Vref 1 , and a second electrode connected to the first node A. 
     The sixth switch transistor M 6  has a gate configured to receive a frame reset signal FRe, a first electrode configured to receive the first reference signal Vref 1 , and a second electrode connected to the gate of the fourth switch transistor M 4 . 
     The stabilization capacitor C 0  is connected between the gate of the fourth switch transistor M 4  and the gate of the fifth switch transistor M 5 . 
     In an embodiment, when the third switch transistor is turned on under the control of the M th  driving signal, the second reference signal may be output to the gate of the fourth switch transistor. When the sixth switch transistor is turned on under the control of the frame reset signal, the first reference signal may be output to the gate of the fourth switch transistor. When the fourth switch transistor is turned on under the control of the signal input to the gate thereof, the reset signal may be output to the gate of the fifth switch transistor. When the fifth switch transistor is turned on under the control of the signal input to the gate thereof, the first reference signal may be output to the first node to perform reset control on the potential at the first node. 
     In an embodiment, the first control sub-circuit  31  may comprise an eighth switch transistor M 8 . 
     The eighth switch transistor M 8  has a gate connected to the second node B, a first electrode configured to receive the first reference signal Vref 1 , and a second electrode connected to the first node A. 
     Specifically, when the eighth switch transistor is turned on under the control of the signal at the second node, the first reference signal may be output to the first node to control the potential at the first node. 
     In an embodiment, the second control sub-circuit  32  may comprise a ninth switch transistor M 9 , a tenth switch transistor M 10 , an eleventh switch transistor M 11 , and a twelfth switch transistor M 12 . 
     The ninth switch transistor M 9  has a gate and a first electrode both configured to receive the second reference signal Vref 2 , and a second electrode connected to a gate of the tenth switch transistor M 10 . 
     The tenth switch transistor M 10  has a first electrode configured to receive the second reference signal Vref 2 , and a second electrode connected to the second node B. 
     The eleventh switch transistor M 11  has a gate connected to the first node A, a first electrode configured to receive the first reference signal Vref 1 , and a second electrode connected to the second node B. 
     The twelfth switch transistor M 12  has a gate connected to the first node A, a first electrode configured to receive the first reference signal Vref 1 , and a second electrode connected to the gate of the tenth switch transistor M 10 . 
     Specifically, when the ninth switch transistor is turned on under the control of the second reference signal, the second reference signal may be output to the gate of the tenth switch transistor to control the tenth switch transistor to be turned on. When the twelfth switch transistor is turned on under the control of the first node, the first reference signal may be output to the gate of the tenth switch transistor to control the tenth switch transistor to be turned off. When the tenth switch transistor is turned on, the second reference signal may be output to the second node to control the potential at the second node. When the eleventh switch transistor is turned on under the control of the first node, the first reference signal may be output to the second node to control the potential at the second node. 
     In a specific implementation, width to length ratios of channels of the twelfth switch transistor and the ninth switch transistor are set, so that when the potential at the first node is a high potential, a rate at which the twelfth switch transistor outputs the first reference signal to the gate of the tenth switch transistor under the control of the signal at the first node is greater than a rate at which the ninth switch transistor outputs the second reference signal to the gate of the tenth switch transistor, and thereby the tenth switch transistor is turned on. Similarly, width to length ratios of the eleventh switch transistor and the tenth switch transistor are set, so that when a rate at which the eleventh switch transistor outputs the first reference signal to the second node is greater than a rate at which the tenth switch transistor outputs the second reference signal to the second node, it is ensured that the potential at the second node is a low potential, thereby avoiding abnormality of the output driving signal. 
     In an embodiment, the exemplary output sub-circuit  41 _ m  may comprise a first switch transistor M 1 _ m , a second switch transistor M 2 _ m , and a storage capacitor Cst_m. 
     The first switch transistor M 1 _ m  has a gate connected to the first node A, a first electrode configured to receive a corresponding clock signal CK_m, and a second electrode configured to output a corresponding driving signal Output_m. 
     The second switch transistor M 2 _ m  has a gate connected to the second node B, a first electrode configured to receive the first reference signal Vref 1 , and a second electrode configured to output the corresponding driving signal Output_m. 
     The storage capacitor Cst_m is connected between the first node A and the second electrode of the first switch transistor M 1 _ m.    
     Specifically, when the first switch transistor is turned on under the control of the signal at the first node, the connected clock signal may be output as a corresponding driving signal, so that a potential of the driving signal is controlled through the connected clock signal. When the second switch transistor is turned on under the control of the signal at the second node, the connected first reference signal may be output as a corresponding driving signal so that the potential of the driving signal is controlled through the first reference signal. Charging and discharging are performed under the control of the signals at the first node and the second electrode of the first switch transistor, and when the first node is in a floating state, a voltage difference between the first node and the second electrode of the first switch transistor can be maintained to be stable due to the bootstrap action of the capacitor. 
     The shift register circuit according to the embodiments of the present disclosure comprises an input circuit, a reset circuit, a control circuit, and a multi-output circuit, wherein the multi-output circuit may be configured to output M driving signals. Therefore, each stage of shift register circuit may be connected to a plurality of gate lines. When the shift register circuit is applied to a display apparatus, a number of shift register circuits may be reduced, which is advantageous for a narrow bezel design. 
     In a specific implementation, when the shift register circuit according to the embodiments of the present disclosure is applied to the display apparatus, a first stage of shift register circuit corresponds to N gate lines in a display panel of the display apparatus, and therefore, the more the number of driving signals which can be output in the shift register circuit according to the embodiments of the present disclosure, the smaller the number of shift register circuits required when the shift register circuits are applied to the display apparatus. However, as the multi-output circuit in the shift register circuit is controlled by the first node and the second node, the more the number of driving signals in the shift register circuit, the longer the period of time in which the potential at the first node needs to be maintained, but in normal conditions, the potential at the first node may be attenuated after being maintained for a period of time, which influences the stability of the driving signal once the potential at the first node is attenuated. Therefore, in a specific implementation, in the shift register circuit according to the embodiments of the present disclosure, the multi-output circuit may output two driving signals, that is, M=2. Alternatively, the multi-output circuit may also output three driving signals, that is, M=3. Alternatively, the multi-output circuit may also output four driving signals, that is, M=4. Of course, the multi-output circuit may also output more driving signals, which is not limited here. 
     Further, in order to prevent an interference of a driving signal in a previous frame to a driving signal in a next period, in a specific implementation, in the shift register circuit according to the embodiments of the present disclosure, as shown in  FIG. 2 b   , the shift register circuit may further comprise M frame reset circuits  5 _ m  which are in one-to-one correspondence to the M output sub-circuits in the shift register circuit, and each of the M frame reset circuits  5  is configured to receive the frame reset signal FRe and the first reference signal Vref 1 , and reset a driving signal output by a corresponding output sub-circuit according to the first reference signal Vref 1  under the control of the frame reset signal FRe. In this way, each driving signal is reset after a scanning process in one frame is performed, which can avoid the interference of the driving signal in the previous frame to the driving signal in the next frame. 
     In an embodiment, as shown in  FIG. 4 , the frame reset circuit  5 _ m  may comprise a thirteenth switch transistor M 13 _ m.    
     The thirteenth switch transistor M 13 _ m  has a gate configured to receive the frame reset signal FRe, a first electrode configured to receive the first reference signal Vref 1 , and a second electrode configured to output the reference signal Vref 1  to reset the corresponding driving signal Output_m. 
     Specifically, when the thirteenth switch transistor is turned on under the control of the frame reset signal, the first reference signal may be output to reset the driving signal. 
     An operation process of the shift register circuit according to the embodiments of the present disclosure will be described below in conjunction with a circuit timing diagram. Here, M=3 is taken as an example for illustration. In the following description, 1 represents a high potential signal, and 0 represents a low potential signal, wherein 1 and 0 represent logic potentials thereof, which are only for better explanation of the operation process of the shift register circuit according to the embodiments of the present disclosure, instead of potentials applied to gates of various switch transistors in a specific implementation. 
     An operation process of the shift register circuit shown in  FIG. 3  will be described below by taking a structure of the shift register circuit shown in  FIG. 3  as an example, and a corresponding circuit timing diagram is shown in  FIG. 5 . Specifically, an input phase T 1 , an output phase T 2 , and a reset phase T 3  in the circuit timing diagram shown in  FIG. 5  are selected. Here, the output phase T 2  may be further divided into a first output sub-phase T 21 , a second output sub-phase T 22 , a third output sub-phase T 23 , a fourth output sub-phase T 24 , and a fifth output sub-phase T 25 . Here, the first reference signal Vref 1  is a low potential signal, and the second reference signal Vref 2  is a high potential signal. 
     As shown in  FIG. 5 , a Blanking Time (abbreviated as BT) is generally provided between two adjacent display frames. In a specific implementation, in the blanking time phase BT, the input signal Input, each clock signal CK_m, and the reset signal Reset are all low potential signals. Further, in a specific implementation, the frame reset signal FRe is a high potential signal in the blanking time phase BT, and is a low potential signal in other phases. Due to the action of the frame reset signal FRe in the blanking time phase BT, the sixth switch transistor M 6  may be controlled to be turned on to output the first reference signal Vref 1  at a low potential to the stabilization capacitor C 0  and the gate of the fourth switch transistor M 4 , and the four switch transistor M 4  may be controlled to be turned off to prevent the influence of the turn-on of the fourth switch transistor M 4  on the potential at the first node A in an input phase T 1  of a next display frame. 
     The operation process of the shift register circuit shown in  FIG. 3  using the circuit timing diagram shown in  FIG. 5  is as follows. 
     In the input phase T 1 , as Input=1, the seventh switch transistor M 7  is turned on to output the input signal Input at a high potential to the first node A, so that the signal at the first node A is a high potential signal to control the eleventh switch transistor M 11 , the twelfth switch transistor M 12 , and the first switch transistors M 1 _ 1 -M 1 _ 3  to be all turned on. As the twelfth switch transistor M 12  is turned on to output the first reference signal Vref 1  at a low potential to the gate of the tenth switch transistor M 10 , and as the eleventh switch transistor M 11  is turned on to output the first reference signal Vref 1  at a low potential to the second node B, the signal at the second node B is a low potential signal to control the second switch transistors M 2 _ 1 ˜M 2 _ 3  to be all turned off. As the first switch transistor M 1 _ 1  is turned on, a clock signal CK_ 1  is output as a driving signal Output_ 1 . As the first switch transistor M 1 _ 2  is turned on, a clock signal CK_ 2  is output as a driving signal Output_ 2 . As the first switch transistor M 1 _ 3  is turned on, a clock signal CK_ 3  is output as a driving signal Output_ 3 . Therefore, the shift register circuit outputs the driving signals Output_ 1 -Output_ 3  in the input phase T 1  respectively. 
     Then, the input signal Input is pulled down, that is, Input=0, and therefore, the seventh switch transistor M 7  is turned off, so that the first node A is in a floating state. Due to the action of a storage capacitor Cst_ 1 , the signal at the first node A may be maintained to be a high potential signal, to control the first switch transistors M 1 _ 1 -M 1 _ 3  to be all turned on, so that the driving signals Output_ 1 -Output_ 3  are all low potential signals. 
     In the output phase T 2 , in the first output sub-phase T 21 , Input=0, CK_ 1 =1, CK_ 2 =0, CK_ 3 =0, and Output_ 3 =0. As Input=0, the seventh switch transistor M 7  is turned off, so that the first node A is in a floating state. Due to the action of the storage capacitor Cst_ 1 , the signal at the first node A may be maintained to be a high potential signal, and the first switch transistors M 1 _ 1 ˜M 1 _ 3  are all turned on. As the first switch transistor M 1 _ 1  is turned on and outputs the clock signal CK_ 1  as the driving signal Output_ 1 , the driving signal Output_ 1  is a high potential signal. Due to the bootstrap action of the storage capacitor Cst_ 1 , the potential of the signal at the first node A may be further pulled up to output the clock signal CK_ 1  as the driving signal Output_ 1 , wherein the driving signal Output_ 1  is a high potential signal. As the first switch transistor M 1 _ 2  is turned on and outputs the clock signal CK_ 2  as the driving signal Output_ 2 , the driving signal Output_ 2  is a low potential signal. As the first switch transistor M 1 _ 3  is turned on and outputs the clock signal CK_ 3  as the driving signal Output_ 3 , the driving signal Output_ 3  is a low potential signal. As Output_ 3 =0, the third switch transistor M 3  is turned off. Further, as the signal at the first node A is a high potential signal, the eleventh switch transistor M 11  and the twelfth switch transistor M 12  are both turned on, and the signal at the second node B is a low potential signal, to control the second switch transistors M 2 _ 1 -M 2 _ 3  to be all turned off. 
     In the second output sub-phase T 22 , Input=0, CK_ 1 =1, CK_ 2 =1, CK_ 3 =0, and Output_ 3 =0. As Input=0, the seventh switch transistor M 7  is turned off, so that the first node A is in a floating state. As the potential of the signal at the first node A is pulled up under the bootstrap action of the high potential signals of the storage capacitor Cst_ 1  and CK_ 1 , the first switch transistors M 1 _ 1 ˜M 1 _ 3  are all turned on. As the first switch transistor M 1 _ 1  is turned on and outputs the clock signal CK_ 1  as the driving signal Output_ 1 , the driving signal Output_ 1  is maintained to be a high potential signal. As the first switch transistor M 1 _ 2  is turned on and outputs the clock signal CK_ 2  as the driving signal Output_ 2 , the driving signal Output_ 2  is maintained to be a high potential signal, and the potential of the signal at the first node A is further pulled up due to the bootstrap action of a storage capacitor Cst_ 2 . As the first switch transistor M 1 _ 3  is turned on and outputs the clock signal CK_ 3  as the driving signal Output_ 3 , the driving signal Output_ 3  is a low potential signal. As Output_ 3 =0, the third switch transistor M 3  is turned off. Further, as the signal at the first node A is a high potential signal, the eleventh switch transistor M 11  and the twelfth switch transistor M 12  are both turned on, so that the signal at the second node B is a low potential signal, to control the second switch transistors M 2 _ 1 -M 2 _ 3  to be all turned off. 
     In the third output sub-phase T 23 , Input=0, CK_ 1 =0, CK_ 2 =1, CK_ 3 =0, and Output_ 3 =0. As Input=0, the seventh switch transistor M 7  is turned off, so that the first node A is in a floating state. As the potential of the signal at the first node A is pulled up under the bootstrap action of the high potential signals of the storage capacitor Cst_ 2  and CK_ 2 , the first switch transistors M 1 _ 1 -M 1 _ 3  are all turned on. As the first switch transistor M 1 _ 1  is turned on, and the clock signal CK_ 1  at a low potential is output as the driving signal Output_ 1 , the driving signal Output_ 1  is a low potential signal. As the first switch transistor M 1 _ 3  is turned on, and the clock signal CK_ 3  at a low potential is output as the driving signal Output_ 3 , the driving signal Output_ 3  is a low potential signal. As the first switch transistor M 1 _ 2  is turned on, and the clock signal CK_ 2  at a high potential is output as the driving signal Output_ 2 , the driving signal Output_ 2  is a high potential signal. Therefore, the potential of the signal at the first node A is pulled up only under the bootstrap action of the high potential signals of the storage capacitor Cst_ 2  and CK_ 2  in the T 23  phase, so that the potential of the signal at the first node A in this phase is the same as the potential of the signal at the first node A in the T 21  phase. Further, as the signal at the first node A is a high potential signal, the eleventh switch transistor M 11  and the twelfth switch transistor M 12  are both turned on, so that the signal at the second node B is a low potential signal, to control the second switch transistors M 21 -M 23  to be all turned off. 
     In the T 24  phase, Input=0, CK_ 1 =0, CK_ 2 =1, CK_ 3 =1, and Output_ 3 =1. As Input=0, the seventh switch transistor M 7  is turned off, and the first node A is in a floating state. As the potential of the signal at the first node A is pulled up under the bootstrap action of the high potential signals of the storage capacitor Cst_ 2  and CK_ 2 , the first switch transistors M 1 _ 1 ˜M 1 _ 3  are all turned on. As the first switch transistor M 1 _ 1  is turned on and outputs the clock signal CK_ 1  at a low potential as the driving signal Output_ 1 , the driving signal Output_ 1  is maintained to be a low potential signal. As the first switch transistor M 1 _ 2  is turned on and outputs the clock signal CK_ 2  at a high potential as the driving signal Output_ 2 , the driving signal Output_ 2  is a high potential signal. As the first switch transistor M 1 _ 3  is turned on and outputs the clock signal CK_ 3  at a high potential as the driving signal Output_ 3 , the driving signal Output_ 3  is a high potential signal, and the potential of the signal at the first node A may be further pulled up under the bootstrap action of a storage capacitor Cst_ 3 . Therefore, on the basis that the potential of the signal at first node A is pulled up under the bootstrap action of the high potential signals of the storage capacitor Cst_ 2  and CK_ 2  in the T 24  phase, the potential of the signal at first node A is further pulled up under the bootstrap action of the high potential signals of the storage capacitor Cst_ 3  and CK_ 3  in the T 24  phase, so that the potential of the signal at the first node A in this phase is the same as the potential of the signal at the first node A in the T 22  stage. As Output_ 3 =1, the third switch transistor M 3  is turned on and outputs the second reference signal Vref 2  at a high potential to the gate of the fourth switch transistor M 4  and the stabilization capacitor C 0  to control the fourth switch transistor M 4  to be turned on. The turned-on fourth switch transistor M 4  outputs the reset signal Reset at a low potential to the gate of the fifth switch transistor M 5 , so that the fifth switch transistor M 5  is turned off, so as not to influence the potential at the first node A. Further, as the signal at the first node A is a high potential signal, the eleventh switch transistor M 11  and the twelfth switch transistor M 12  are both turned on, so that the signal at the second node B is a low potential signal to control the second switch transistors M 2 _ 1 -M 2 _ 3  to be all turned off. 
     In the T 25  phase, Input=0, CK_ 1 =0, CK_ 2 =0, CK_ 3 =1, and Output_ 3 =1. As Input=0, the seventh switch transistor M 7  is turned off, so that the first node A is in a floating state. As the potential of the signal at the first node A is pulled up under the bootstrap action of the high potential signals of the storage capacitor Cst 3  and CK_ 3 , the first switch transistors M 1 _ 1 -M 1 _ 3  are all turned on. As the first switch transistor M 1 _ 1  is turned on and outputs the clock signal CK_ 1  at a low potential as the driving signal Output_ 1 , the driving signal Output_ 1  is a low potential signal. As the first switch transistor M 1 _ 2  is turned on and outputs the clock signal CK_ 2  at a low potential as the driving signal Output_ 2 , the driving signal Output_ 2  is a low potential signal. As the first switch transistor M 1 _ 3  is turned on and outputs the clock signal CK_ 3  at a high potential as the driving signal Output_ 3 , the driving signal Output_ 3  is a high potential signal. Therefore, the potential of the signal at the first node A is pulled up only under the bootstrap action of the high potential signals of the storage capacitor Cst_ 3  and CK_ 3  in the T 25  phase, so that the potential of the signal at the first node A in this phase is the same as the potential of the signal at the first node A in the T 21  phase. As Output_ 3 =1, the third switch transistor M 3  is turned on and outputs the second reference signal Vref 2  at a high potential to the gate of the fourth switch transistor M 4  and the stabilization capacitor C 0  to control the fourth switch transistor M 4  to be turned on. The turned-on fourth switch transistor M 4  outputs the reset signal Reset at a low potential to the gate of the fifth switch transistor M 5 , so that the fifth switch transistor M 5  is turned off, so as not to influence the potential at the first node A. Further, as the signal at the first node A is a high potential signal, the eleventh switch transistor M 11  and the twelfth switch transistor M 12  are both turned on, so that the signal at the second node B is a low potential signal, to control the second switch transistors M 2 _ 1 -M 2 _ 3  to be all turned off. 
     In the reset phase T 3 , Input=0, Output_ 3 =0, and Reset=1. As Input=0, the seventh switch transistor M 7  is turned off. As Output_ 3 =0, the third switch transistor M 3  is turned off, the gate of the fourth switch transistor M 4  is in a floating state, and the signal at the gate of the fourth switch transistor M 4  may be maintained to be a high potential signal due to the action of the stabilization capacitor C 0 , so that the fourth switch transistor M 4  is turned on. The turned-on fourth switch transistor M 4  outputs the reset signal Reset at a high potential to the gate of the fifth switch transistor M 5  to control the fifth switch transistor M 5  to be turned on, to output the first reference signal Vref 1  at a low potential to the first node A, so that the signal at the first node A is a low potential signal, thereby controlling the eleventh switch transistor M 11 , the twelfth switch transistor M 12 , and the first switch transistors M 1 _ 1 -M 1 _ 3  to be all turned off. As the ninth switch transistor M 9  is turned on under the control of the second reference signal Vref 2 , the second reference signal Vref 2  is provided to the gate of the tenth switch transistor M 10 , to control the tenth switch transistor M 10  to be turned on. The turned-on tenth switch transistor M 10  outputs the second reference signal Vref 2  at a high potential to the second node B, so that the signal at the second node B is a high potential signal to control the eighth switch transistor M 8  and the second switch transistors M 2 _ 1 -M 2 _ 3  to be all turned on. The turned-on eighth switch transistor M 8  provides the first reference signal Vref 1  at a low potential to the first node A, which further causes the signal at the first node A to be a low potential signal. The turned-on second switch transistor M 2 _ 1  outputs the first reference signal Vref 1  at a low potential as the driving signal Output_ 1 , so that the driving signal Output_ 1  is a low potential signal. The turned-on second switch transistor M 2 _ 2  outputs the first reference signal Vref 1  at a low potential as the driving signal Output_ 2 , so that the driving signal Output_ 2  is a low potential signal. The turned-on second switch transistor M 2 _ 3  outputs the first reference signal Vref 1  at a low potential as the driving signal Output_ 3 , so that the driving signal Output_ 3  is a low potential signal. 
     Before the blanking time phase BT arrives after the reset phase T 3 , the fourth switch transistor M 4  is always in a turn-on state due to the retention action of the stabilization capacitor C 0 , so that the signal at the first node A may be reset once each time the reset signal Reset is a high potential signal. Thereby, the signal at the first node A may be reset multiple times in one display frame to prevent instability of the signal at the first node A from interfering with the output. 
     After one frame, in the blanking time phase BT, the frame reset signal FRe is a high potential signal, and therefore the sixth switch transistor M 6  is turned on to output the first reference signal Vref 1  at a low potential to the gate of the fourth switch transistor M 4  and the stabilization capacitor C 0 , to control the stabilization capacitor C 0  to discharge, and control the fourth switch transistor M 4  to be turned off to prevent the fourth switch transistor M 4  from influencing the signal at the first node A when the input signal Input is at a high potential in a next display frame. 
     As shown in  FIG. 5 , the driving signal Output_ 1 , the driving signal Output_ 2 , and the driving signal Output_ 3  sequentially have the same phase difference, which is less than ⅓ clock cycle. 
     As shown in  FIG. 5 , the clock signal CK_ 1 , the clock signal CK_ 2 , and the clock signal CK_ 3  sequentially have the same phase difference, which is less than ⅓ clock cycle. 
     The shift register circuit according to the embodiments of the present disclosure may output three different driving signals only through the cooperation of sixteen switch transistors and four capacitors, so that one stage of shift register circuit can drive three gate lines. Compared with a solution in the related art that it is required to provide three stages of shift register circuits, a number of the shift register circuits according to the embodiments of the present disclosure may be reduced by 2, thereby facilitating a narrow bezel design when the shift register circuit is applied to the display apparatus. 
     An operation process of the shift register circuit shown in  FIG. 4  will be described by taking a structure of the shift register circuit shown in  FIG. 4  as an example, and a corresponding circuit timing diagram is shown in  FIG. 5 . Specifically, an input phase T 1 , an output phase T 2 , and a reset phase T 3  in the circuit timing diagram shown in  FIG. 5  are selected. Here, the output phase T 2  may be further divided into a first output sub-phase T 21 , a second output sub-phase T 22 , a third output sub-phase T 23 , a fourth output sub-phase T 24 , and a fifth output sub-phase T 25 . Here, the first reference signal Vref 1  is a low potential signal, and the second reference signal Vref 2  is a high potential signal. 
     The structure of the shift register circuit shown in  FIG. 4  differs from the structure of the embodiments shown in  FIG. 3  in that frame reset circuits  5 _ m , that is, thirteenth switch transistors M 13 _ 1  to M 13 _ 3 , are added in the structure of  FIG. 4 . Therefore, the operation process of the shift register circuit shown in  FIG. 4  in the input phase T 1 , the output phase T 2 , and the reset phase T 3  is substantially the same as that of the embodiment of  FIG. 3 , and details are not described here. The operation process of the shift register circuit in a blanking time phase BT will be exemplarily described in detail in the present embodiment. 
     In the blanking time phase BT, as the frame reset signal FRe is a high potential signal, the sixth switch transistor M 6  and the thirteenth switch transistors M 13 _ 1  to M 13 _ 3  are all turned on. The turned-on sixth switch transistor M 6  outputs the first reference signal Vref 1  at a low potential to the gate of the fourth switch transistor M 4  and the stabilization capacitor C 0  to control the stabilization capacitor C 0  to discharge and control the fourth switch transistor M 4  to be turned off to prevent the fourth switch transistor M 4  from influencing the signal at the first node A when the input signal Input is at a high potential in a next display frame. The turned-on thirteenth switch transistor M 13 _ 1  outputs the first reference signal Vref 1  at a low potential as the driving signal Output_ 1  to perform frame reset on the driving signal Output_ 1 . The turned-on thirteenth switch transistor M 13 _ 2  outputs the first reference signal Vref 1  at a low potential as the driving signal Output_ 2  to perform frame reset on the driving signal Output_ 2 . The turned-on thirteenth switch transistor M 13 _ 3  outputs the first reference signal Vref 1  at a low potential as the driving signal Output_ 3  to perform frame reset on the driving signal Output_ 3 . Thereby, the problem that driving signals of two adjacent display frames interfere with each other can be avoided. 
     The above description is only made by taking switch transistors in the shift register circuit being N-type transistors as an example. When the switch transistors included in the shift register circuit are P-type transistors, a stable output operation of the corresponding shift register circuit can be realized only by inverting potentials of the above signals, and a specific process will not be described here. 
     It should be illustrated that in the input phase, the clock signal CK_ 2  and the clock signal CK_ 3  each have a phase in which it is a high potential signal, and therefore the corresponding gate line may further be pre-charged to improve the driving capability. 
     The embodiments of the present disclosure further provide a method for driving any of the above shift register circuits according to the embodiments of the present disclosure. As shown in  FIG. 6 , the method may comprise: an input phase, an output phase, and a reset phase. 
     In S 601 , in the input phase, a signal is output to the first node through the input circuit based on the input signal. 
     In S 602 , in the output phase, M driving signals are output through the output circuit according to the M clock signals under the control of the signal at the first node. 
     In S 603 , in the reset phase, the first reference signal is output to the first node through the reset circuit under the control of the reset signal, and the M driving signals are output through the multi-output circuit according to the first reference signal under the control of the signal at the second node. 
     The method according to the embodiments of the present disclosure can output M driving signals, and when the shift register circuit is applied to a display apparatus, a number of shift register circuits can be reduced, which is advantageous for a narrow bezel design. 
     In a specific implementation, various clock signals have the same cycle, and various driving signals are in one-to-one correspondence to the clock signals. When the shift register circuit according to the embodiments of the present disclosure is connected to three clock signals, three driving signals are output, and the three different clock signals may be defined as a clock signal CK_ 1  to a third clock signal CK_ 3 ; wherein the first clock signal CK_ 1  to the third clock signal CK_ 3  sequentially have the same phase difference, which may be less than ⅓ clock cycle. When the shift register circuit according to the embodiments of the present disclosure is connected to four clock signals, four driving signals are output, and the four different clock signals may be defined as a first clock signal CK_ 1  to a fourth clock signal CK_ 4 ; wherein the first clock signal CK_ 1  to the fourth clock signal CK_ 4  sequentially have the same phase difference, which is less than ¼ clock cycle. 
     In a specific implementation, when the shift register circuit according to the embodiments of the present disclosure outputs three driving signals, with respect to an operation process of one stage of shift register circuit in each frame, as shown in  FIG. 5 , a rising edge of the reset signal Reset is aligned with a falling edge of the clock signal CK_ 3 , and a falling edge of the reset signal Reset is ahead of a rising edge of the clock signal CK_ 2 . The above description is made only by taking an effective pulse signal of the input signal Input being a high potential signal as an example. When the effective pulse signal of the input signal Input is a low potential signal, a stable operation of the corresponding shift register circuit can be realized only by inverting the potential of the Reset signal. 
     The embodiments of the present disclosure further provide a gate driving circuit, comprising: N cascaded shift register circuits according to any of the above embodiments of the present disclosure, wherein the M driving signals are sequentially defined as a first driving signal to an M th  driving signal in a scanning order, where N is a positive integer greater than 1, wherein 
     an input signal of a first stage of shift register circuit is a frame start signal; and 
     an input signal of each of remaining stages of shift register circuits other than the first stage of shift register circuit is an n th  driving signal of a previous stage of shift register circuit, 
     where when M is an even, 
               n   =       M   2     +   1       ,         
and when M is an odd,
 
     
       
         
           
             n 
             = 
             
               
                 
                   M 
                   + 
                   1 
                 
                 2 
               
               . 
             
           
         
       
     
     In a specific implementation, by taking M=3 as an example, as shown in  FIG. 7 , the gate driving circuit comprises a plurality of cascaded shift register circuits: SR( 1 ), SR( 2 ), SR( 3 ), SR( 4 ) . . . SR(k−1), SR(k) . . . SR(K−1), SR(K) (with a total of K shift register circuits, where 1≤k≤K), wherein a frame start signal STV is input as an input signal Input of the first stage of shift register circuit SR( 1 ); 
     except for the first stage of shift register circuit SR( 1 ), an input signal Input of each of remaining stages of shift register circuits SR(k) is a third driving signal Output_ 3  of a previous stage of shift register circuit SR(k−1) which is adjacent to the current stage of shift register circuit SR(k). 
     In a specific implementation, by taking M=3 as an example, as shown in  FIG. 7 , a clock signal CK_ 1  of a (4a−3) th  stage of shift register circuit, a clock signal CK_ 2  of a (4a−2) th  stage of shift register circuit, and a clock signal CK_ 3  of a (4a−1) th  stage of shift register circuit are connected to the same clock signal line ck_ 1 . A clock signal CK_ 2  of the (4a−3) th  stage of shift register circuit, a clock signal CK_ 3  of the (4a−2) th  stage of shift register circuit, and a clock signal CK_ 1  of a (4a) th  stage of shift register circuit are connected to the same clock signal line ck_ 2 . A clock signal CK_ 3  of the (4a−3) th  stage of shift register circuit, a clock signal CK_ 1  of the (4a−1) th  stage of shift register circuit, and a clock signal CK_ 2  of the (4a) th  stage of shift register circuit are connected to the same clock signal line ck_ 3 . A clock signal CK_ 1  of the (4a−2) th  stage of shift register circuit, a clock signal CK_ 2  of the (4a−1) th  stage of shift register circuit, and a clock signal CK_ 3  of the (4a) th  stage of shift register circuit are connected to the same clock signal line ck_ 4 . Here, a is a positive integer. As shown in  FIG. 8 , clock signals output from the clock signal line ck_ 1  to the clock signal line ck_ 4  sequentially have the same phase difference, which is less than ⅓ clock cycle. A timing diagram of driving signals output by the entire gate driving circuit is as shown in  FIG. 9 . 
     The gate driving circuit comprises multiple stages of cascaded shift register circuits, so that driving signals are sequentially input to gate lines in a display panel of the display apparatus through the gate driving circuit. Here, a scanning order is generally from a first row of gate lines to a last row of gate lines of the display panel, which of course refers to a scanning order during forward scanning. In practical applications, there may also be reverse scanning for display panel, in which case the scanning order is from the last row of gate lines to the first row of gate lines of the display panel. Thereby, the M driving signals may be sequentially defined as a first driving signal to an M th  driving signal in the scanning order to sequentially drive M (for example, adjacent) gate lines when being applied to the display panel. 
     In the gate driving circuit, for a certain stage of shift register circuit, a driving signal output by a next stage of shift register circuit is generally used as a reset signal of the current stage of shift register circuit to reset a signal at a first node in the shift register circuit, which causes the cascaded shift register circuits to influence each other. For example, in  FIGS. 2 a  and 2 b   , the Reset signal received by the shift register circuit may be a driving signal output by a next stage of shift register circuit. 
     In another embodiment, various stages of shift register circuits may receive the same reset signal, wherein the reset signal is a periodic square wave signal, with each cycle comprising a turn-on period in which the reset circuit is turned on and a turn-off period in which the reset circuit is turned off, wherein each of the turn-on periods comprises a first edge and a second edge appearing successively in time. Here, a first edge of a turn-on period of an i th  cycle of the reset signal is synchronized with or lags behind a second edge of a current period of an M th  clock signal in an i th  stage of shift register circuit, and is synchronized with or is ahead of a first edge of a next cycle of the M th  clock signal, where 1≤i≤N. Therefore, the reset signal may be used to reset the first node in time in one display frame after a last gate driving signal is output in one shift register circuit and before a next cycle of a clock signal in the shift register circuit arrives, so as not to influence the driving signal output to each gate line, thereby not influencing the display content. In this embodiment, the influence due to cascaded reset among various stages of shift register circuits can be avoided. 
     In an embodiment, various stages of shift register circuits may receive the same frame reset signal, wherein a first edge of the frame reset signal lags behind or is synchronized with a second edge of a last clock signal in a last stage of shift register circuit in a current period, and a second edge of the frame reset signal is ahead of or synchronized with a first edge of a first clock signal in a first stage of shift register circuit in a next period. 
     The embodiments of the present disclosure further provide a method for driving a gate driving circuit according to any of the above embodiments of the present disclosure. As shown in  FIG. 11 , the method for driving the gate driving circuit comprises a display driving phase and a blanking time phase. 
     In S 1101 , in the display driving phase, the method for driving a shift register circuit in  FIG. 6  is performed for each stage of shift register circuit in the gate driving circuit. 
     In S 1102 , in the blanking time phase, each of the driving signals in each stage of shift register circuit is reset through the frame reset circuit by using the first reference signal under the control of the frame reset signal. 
     The embodiments of the present disclosure further provide a display apparatus, as shown in  FIG. 10  (by taking M=3 as an example), comprising a plurality of gate lines and the gate driving circuit according to any of the embodiments of the present disclosure. Here, each stage of shift register circuit SR(k) drives M gate lines Gate of the plurality of gate lines respectively. For an implementation of the display apparatus, reference can be made to the embodiments of the shift register circuit described above, and the repeated parts will not be described. 
     In a specific implementation, the display apparatus according to the embodiments of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. It can be understood by those of ordinary skill in the art that there are other indispensable components of the display apparatus, which will not be described here, and should not be construed as limiting the present disclosure. 
     It will be apparent to those skilled in the art that various modifications and changes can be made in the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and changes fall within the scope of the claims of the present disclosure and equivalent technologies thereof, these amendments and changes are also intended to be included within the present disclosure.