Patent Publication Number: US-9426916-B1

Title: Arrangement of memory devices in a multi-rank memory module

Description:
CLAIM OF PRIORITY 
     The present application claims priority to U.S. Provisional Application No. 61/682,249 filed on Aug. 11, 2012, which is incorporated herein by reference in its entirety. 
    
    
     FIELD 
     The disclosure herein is related generally to memory modules, and more particularly to multi-rank memory modules. 
     DESCRIPTION OF RELATED ART 
     The disclosure herein is related generally to memory modules, and more particularly to multi-rank memory modules. 
     BACKGROUND 
     Computer systems often utilize modules comprising one or more printed circuit boards (PCBs). Each PCB has one or more components (e.g., integrated circuits or ICs) mounted thereon, and the components can be mounted on one side or on both sides of the PCB. The one or more PCBs also include module connectors for coupling the components in the module to the computer system. For a memory module, the components may include memory devices that are organized in ranks such that the memory devices in a rank are selectable by a single chip select signal and, when selected, communicate respective data bits of a data signal. The memory module may also include one or more register devices to provide registered control/address signals to the memory devices. When the memory module has multiple ranks of memory devices, it is important that the multiple ranks of memory devices and their connections to respective module connectors are properly arranged to insure the quality and integrity of the data signals communicated thereto and therefrom. It is also helpful to balance their loads on the registered C/A signals. 
     SUMMARY 
     A multi-rank memory module is operable in a memory system with a memory controller. The memory module according to one embodiment comprises a module board having a first side and an opposing second side; and memory devices organized in three ranks. The memory devices in a first rank of the three ranks are all mounted on the first side, the memory devices in a second rank of the three ranks are all mounted on the second side, and the memory devices in a third rank of the three ranks include some memory devices mounted on the first side, and some memory devices mounted on the second side. 
     In certain embodiments, the multi-rank memory module further comprises module connectors along an edge of the module board and data/strobe signal hubs disposed away from the edge of the module board. The module connectors include data/strobe signal pins and control/address (C/A) signal pins, and each respective data/strobe signal hub is coupled to a respective data/strobe signal pin and to a respective set of first, second and third memory devices in different ranks. The respective data/strobe signal hub is positioned to reduce difference in lengths of first, second and third signal paths. The first signal path is between the respective data/strobe signal pin and the first memory device, the second signal path is between the respective signal pin and the second memory device, and the third signal path is between the respective data/strobe signal pin and the third memory device. Thus, better alignment of different data bits in a data signal is achieved. The data/strobe signal hubs are positioned away from the edge of the module board to reduce reflection from discreet components disposed near the edge of the module board, resulting in improved signal quality and integrity. 
     In certain embodiments, the data/strobe signal hubs include a first signal hub and a second signal hub coupled to respective ones of first data/strobe signal pin and second data/strobe signal pin. The multi-rank memory module further comprises a first signal trace between the first data/strobe signal pin and the first signal hub, and a second signal trace between the second data/strobe signal pin and the second signal hub. One of the first and second signal traces being routed to increase its length so as to reduce difference in lengths between the first signal trace and the second signal trace. 
     In certain embodiments, the multi-rank memory module further comprises a first register providing registered control/address (C/A) signals to memory devices in the first and second ranks, and a second register providing registered C/A signals to memory devices in the third rank. 
     In another embodiment, a multi-rank memory module comprises a main module board having a first side and an opposing second side, a first daughterboard coupled to the main module board and disposed on the first side of the main module board, and a second daughterboard coupled to the main module board and disposed on the second side of the main module board. The memory module further comprises memory devices organized in ranks, and each rank has a first portion of the memory devices therein mounted on the first daughter board and a second portion of the memory devices therein mounted on the second daughter board. The memory module further comprises a first register device providing registered C/A signals to memory devices mounted on the first daughter board, and a second register device providing registered C/A signals to memory devices mounted on the second daughter board. 
     In certain embodiment, each daughter board has a rigid portion and a flexible portion. Memory devices mounted on the rigid portion are coupled to the main module board via flexible traces on the flexible portion. The memory devices are organized in first, second and third ranks. The rigid portion of each respective daughter board has a first side and an opposing second side, and memory devices mounted on the respective daughter board include a first row of memory devices in the first rank mounted on a first side of the respective daughter board, a second row of memory devices in the second rank mounted on the first side of the respective daughter board, and a third row of memory devices in the third rank mounted on a second side of the respective daughter board. 
     In certain embodiments, the multi-rank memory module further comprises module connectors along an edge of the main module board and data/strobe signal hubs on the first and second daughter boards. The module connectors include data/strobe pins and each respective data/strobe signal hub is coupled to a respective one of the data/strobe pins and to a first memory device in the first rank, a second memory device in the second rank and a third memory device in the third rank. The respective data/strobe signal hub is positioned to reduce difference in lengths of first, second and third signal paths, the first signal path between the respective data/strobe signal pin and the first memory device, the second signal path between the respective signal pin and the second memory device, and the third signal path between the respective data/strobe signal pin and the third memory device. 
     In yes another embodiment, a multi-rank memory module comprises a module board, and module connectors along an edge of the module board via which the multi-rank memory module communicate respective bits of a data signal. The memory module further comprises dual-die packages (DDP) each including two stacked memory dies therein mounted the module board, and single-die packages (SDP) each having a single memory die therein mounted on the module board. Each SDP corresponds to a respective DDP and is disposed on an opposing side of the module board from the respective DDP. The each SDP and the respective DDP are coupled to a same subset of module connectors for communicating a subset of data bits of the data signal. The memory module further comprises at least one register device mounted on the module board and providing registered C/A signals to memory dies. 
     In certain embodiments, the at least one register comprises a first register device providing registered C/A signals to the DDPs and device a second register device providing registered C/A signals to the single-die packages. 
     In certain other embodiments, the at least one register device includes a single register device providing registered C/A signals to the DDPs and the SDPs. 
     In certain embodiments, the registered C/A signals include first, second and third chip select signals, and the memory die in the each SDP and the memory dies in the respective DDP receive respective ones of the first, second and third chip select signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a memory system comprising a memory controller and a memory module coupled to a printed circuit board according to embodiments. 
         FIGS. 2A and 2B  are block diagrams illustrating arrangement of memory devices on a memory module according to one embodiment of the present disclosure. 
         FIGS. 3A and 3B  are zoomed in views of portions of a memory module according to an embodiment of the present disclosure. 
         FIG. 3C  is a side view of a memory module illustrating dimensions thereof according to one embodiment of the present disclosure. 
         FIG. 4A  is a schematic diagram illustrating certain data signal hubs and signal traces on a memory module according to an embodiment of the present disclosure. 
         FIG. 4B  is a three-dimensional view of certain data signal hubs and signal traces on a memory module according to an embodiment of the present disclosure. 
         FIG. 4C  is a side view of a memory module illustrating certain data signal hubs and signal traces thereon according to one embodiment of the present disclosure. 
         FIG. 4D  is a schematic diagram of electrical connections between certain memory devices and a respective module connector via a data signal hub and signal traces according to one embodiment of the present disclosure. 
         FIG. 5A  is a side view of a memory module illustrating arrangement of memory devices and certain data signal hubs and signal traces thereon according to an embodiment of the present disclosure. 
         FIG. 5B  is a schematic diagram of electrical connections between certain memory devices and a respective module connector via a data signal hub and signal traces according to one embodiment of the present disclosure. 
         FIG. 5C  is a block diagram illustrating memory device loads on registered control/address signals in a memory module according to an embodiment of the present disclosure. 
         FIG. 6A  is a side view of a memory module illustrating arrangement of memory devices and certain data signal hubs and signal traces thereon according to an embodiment of the present disclosure. 
         FIG. 6B  is a schematic diagram of electrical connections between certain memory devices and a respective module connector via a data signal hub and signal traces according to one embodiment of the present disclosure. 
         FIG. 6C  is a block diagram illustrating memory device loads on registered control/address signals in a memory module having two register devices according to an embodiment of the present disclosure. 
         FIG. 6D  is a block diagram illustrating memory device loads on registered control/address signals in a memory module using a single register device according to an embodiment of the present disclosure. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     As shown in  FIG. 1 , which illustrates a exemplary memory system  100  having a memory controller  110  and a memory module  120  coupled to each other by a memory bus  130 . The memory module  120  includes at least one module board  122  and has a primary side (front side)  120   a  and a secondary side (back side)  120   b , and memory devices  124  mounted on both the primary side  120   a  and the secondary side  120   b . The memory module further includes module connectors  126  in the form of, for example, metal pins or pads formed on one or both sides of the module board and near a bottom edge  128  of the module board. The memory controller can be mounted on a circuit board  140 , and the memory bus  130  includes signal lines, which can be signal traces on or in the circuit board  140 . The module connectors are coupled to respective signal lines on the circuit board by, for example, inserting the bottom edge  128  of the module board into a slot or socket  150  on the circuit board  140 , which may include metal contacts formed inside to facilitates connection of the module connectors with the respective signal lines in the memory bus  130 . 
     In one embodiment, the memory module  120  can be a multi-rank registered DIMM (dual in-line memory module) compatible with the DDR3 (double data rate  3 ) standard published by JEDEC (the Joint Electron Devices Engineering Council). The memory devices can be DRAM (dynamic random access memory) devices, and the module board  122  can be a multi-layered printed circuit board. The present description may also apply to other types of memory modules and/or memory devices. 
     In the context of the present description, a rank refers to one or more memory devices that are selectable by a common chip-select (CL) signal, a memory controller refers to any device capable of sending instructions or commands, or otherwise controlling the memory devices, and a memory bus refers to any component, connection, or groups of components and/or connections, used to provide electrical communication between a memory module and a memory controller. For example, in various embodiments, the memory bus  105  may include printed circuit board (PCB) transmission lines, one or more sockets, module connectors, component packages, and/or any other components or connectors that provide connections for signal transmission. 
       FIGS. 2A and 2B  are block diagrams of an exemplary memory module  120  illustrating memory devices arranged on the primary (front) side  120   a  and the secondary (back) side  120   b , respectively, of the memory module  120 . As shown, the memory module  120  according to one embodiment can have 9×6=54 memory devices, U 1  to U 36  and U 39 -U 56 , organized in first, second and third ranks. For example, the first rank includes memory devices U 19 -U 36  on the back (secondary) side  120   b  of the memory module  120 , which are selectable by a first chip select signal, the second rank includes memory devices U 1 -U 18  on the front (primary) side  120   a  of the memory module  120 , which are selectable by a second chip select signal, and the third rank includes memory devices U 39 -U 47  on the primary side  120   a  and memory devices U 48 -U 56  on the secondary side  120   b  of the module board  120 , which are selectable by a third chip select signal. 
     In one embodiment, the memory devices in the first rank are arranged in two rows, with memory devices U 19 -U 27  arranged in a first row from a left edge A of the module board  122  to a right edge A′ of the module board  122 , and memory devices U 28 -U 36  arranged in a second row from the left edge A of the module board  122  to the right edge A′ of the module board  122 . Likewise, the memory devices in the second rank are arranged in two rows, with memory devices U 1 -U 9  arranged in a third row from a left edge A of the module board  122  to a right edge A′ of the module board  122 , and memory devices U 10 -U 18  arranged in a fourth row from the left edge A of the module board  122  to the right edge A′ of the module board  122 . The memory devices in the third rank are also arranged in two rows, with memory devices U 39 -U 47  arranged in a fifth row from a left edge A of the module board  122  to a right edge A′ of the module board  122  on the front side  120   a , and memory devices U 48 -U 66  arranged in a sixth row from the left edge A of the module board  122  to the right edge A′ of the module board  122  on the back side  120   b.    
     As also shown in  FIGS. 2A and 2B , the memory module  120  further includes two register devices U 37  and U 38  both disposed on the primary side of the module board  122  near a middle portion between the left edge A and the right edge A′ of the module board  122 . In one embodiment, one of the register devices U 37  and U 38  provides control/address information to the first rank and the second rank, while the other one of the register devices U 37  and U 38  provides control/address information to the third rank. Other arrangements to allocate the memory devices with respect to the register devices are also possible and consistent with the present description. For example, in another embodiment, one of the register devices U 37  and U 38  provides control/address information to the second rank and the other one of the register devices U 37  and U 38  provides control/address information to the first rank and the third rank. 
     In one embodiment, as shown in  FIGS. 3A and 3B , which illustrates blown-up views of portions of the front side  120   a  of the memory module  120 , the module board  122  has a bottom edge  128  and a top edge  302 , the memory devices and the register devices include input/output (I/O) pins  305  in the form of, for example, contact pads or solder balls, that are connected to corresponding contact pads/pins or solder balls on the module board  122 . Memory module  120  further includes module connectors  126  disposed near the bottom edge  128  of the module board. The memory module  120  may also include discrete components such as capacitors and resisters disposed on the one or both sides of the module board, as also illustrated in  FIGS. 3A and 3B . 
     In one embodiment, the module board  122  is a multi-layered PCB board (e.g., 12-layered PCB board). The memory module has a height (distance between the bottom edge  128  and the top edge  302 ) equal to or less than about 47 mm. In a further embodiment, the height is about 46.5 mm. In a further embodiment, as shown in  FIG. 3C , the height is about 40.7 mm. Reduction in height is made possible by placing both of the register devices U 37  and U 38  on the primary side  120   a  of the memory module  120 . Placing both of the register devices U 37  and U 38  on the primary side  120   a  also results in improved signal integrity and better routing of signal lines/traces and placement of discrete components in/on the module board for this multi-rank memory module. 
     The module connectors  126  include input/output (I/O) pins such as data/strobe pins, via which data/strobe signals are communicated between the memory devices and the memory controller  110 , and control/address (C/A) pins, via which C/A signals are received from the memory controller  110 . For example, in one embodiment, the module connectors  126  include the following I/O pins disposed near the bottom edge  128  of the module board  122  on the front side  120   a , arranged from the left edge A of the module board  122  to the right edge A′ of the module board  122  in the order of, for example: DQ 0 , DQ 1 , DQS 0 #, DQS 0 , DQ 2 , DQ 3 , DQ 8 , DQ 9 , DQS 1 #, DQS 1 , DQ 10 , DQ 11 , DQ 16 , DQ 17 , DQS 2 #, DQS 2 , DQ 18 , DQ 19 , DQ 24 , DQ 25 , DQS 3 #, DQS 3 , DQ 26 , DQ 27 , CB 0 , CB 1 , DQS 8 #, DQS 8 , CB 2 , CB 3 , CKE 0 , BA 2 , ERROUT#, A 11 , A 7 , A 5 , A 4 , A 2 , CK 1 , CK 1 #, PAR_IN, A 10 , BA 0 , WE, CAS, CS 1 , ODT 1 , CS 2 , DQ 32 , DQ 33 , DQS 4 #, DQS 4 , DQ 34 , DQ 35 , DQ 40 , D 41 , DQS 5 #, DQS 5 , DQ 42 , DQ 43 , DQ 48 , DQ 49 , DQS 6 #, DQS 6 , DQ 50 , DQ 51 , DQ 56 , DQ 57 , DQS 7 #, DQS 7 , DQ 58 , DQ 59 , SA 0 , SCL, SA 2 . 
     The module connectors  126  also include the following I/O pins disposed near the bottom edge  128  of the module board  122  on the back side  120   b , arranged from the left edge A of the module board  122  to the right edge A′ of the module board  122 , in the order of, for example: DQ 4 , DQ 5 , DQS 9 #, DQS 9 , DQ 6 , DQ 7 , DQ 12 , DQ 13 , DQS 10 , DQS 10 #, DQ 14 , DQ 15 , DQ 20 , DQ 21 , DQS 11 , DQS 11 #, DQ 22 , DQ 23 , DQ 28 , DQ 29 , DQS 12 , DQS 12 #, DQ 30 , DQ 31 , CB 4 , CB 5 , DQS 17 , DQS 17 #, CB 6 , CB 7 , MCLR, RESET#, CKE 1 , A 15 , A 14 , A 12 , A 9 , A 8 , A 6 , A 3 , A 1 , CK 0 , CK 0 #, A 0 , BA 1 , RAS, CS 0 , ODT 0 , A 13 , CS 3 , DQ 36 , DQ 37 , DQS 13 , DQS 13 #, DQ 38 , DQ 39 , DQ 44 , D 45 , DQS 14 , DQS 14 #, DQ 46 , DQ 47 , DQ 52 , DQ 53 , DQS 15 , DQS 15 #, DQ 54 , DQ 55 , DQ 60 , DQ 61 , DQS 16 , DQS 16 #, DQ 62 , DQ 63 , SA 1 , SDA. 
     In one embodiment, the register devices, U 37  and U 38 , generate registered control/address (C/A) signals based on control/address (C/A) signals received from the memory controller via respective module connectors  126  and provide the registered C/A signals to the memory devices via signal traces on/in the module board  122 . 
     For example, the register device U 37 A receives row/column address signals from the memory controller  110  via C/A pins A 0  through A 15  and corresponding I/O pins  305  of the register device U 37 A. The register device U 37 A also receives bank address signals from the memory controller  110  via C/A pins BA 0  through BA 2  and corresponding I/O pins  305  of the register device U 37 A. The register device U 37 A further receives control signals RAS (row address strobe), CAS (column address strobe), WE (write enable), CS 0 , CS 1 , CKE 0  (clock enable), CKE 1 , ODT 0  (on-die termination), etc. from the memory controller  110  via corresponding C/A pins and corresponding I/O pins of the register device U 37 A. 
     In response, the register device U 37 A outputs registered C/A signals via corresponding I/O pins of the register device U 37 A. In a further embodiment, the register device outputs two identical sets of registered C/A signals, one toward the left edge A of the module board and one toward the right edge A′ of the module board. The first set of the two identical sets of registered C/A signals include, for example, registered row/column address signals A 0 A, A 1 A, . . . , A 15 A, registered bank address signals BA 0 A, BA 1 A, and BA 2 A, and registered control signals RASA, CASA, WEA, CS 0 A, CS 1 A, CKE 0 A, CKE 1 A, ODT 0 A. The second set of the two identical sets of registered C/A signals include, for example, registered row/column address signals A 0 B, A 1 B, . . . , A 15 B, registered bank address signals BA 0 B, BA 1 B, and BA 2 B, and registered control signals RASB, CASB, WEB, CS 0 B, CS 1 B, CKE 0 B, CKE 1 B, ODT 0 B. 
     Similarly, the register device U 38 A receives row/column address signals from the memory controller  110  via C/A pins A 0  through A 15  and via corresponding I/O pins of the register device U 38 A. The register device U 38 A also receives bank address signals from the memory controller  110  via C/A pins BA 0  through BA 2  and corresponding I/O pins of the register device U 38 A. The register device U 38 A further receives control signals RAS (row address strobe), CAS (column address strobe), WE (write enable), CS 0 , CS 1 , CKE 0  (clock enable), CKE 1 , ODT 0  (on-die termination), etc. from the memory controller  110  via corresponding C/A pins and corresponding I/O pins of the register device U 38 A. 
     In response, the register device U 38 A outputs registered C/A signals via corresponding I/O pins of the register device U 38 A. In a further embodiment, the register device outputs two identical sets of registered C/A signals, one toward the left edge A of the module board and one toward the right edge A′ of the module board. The first set of the two identical sets of registered C/A signals may include, for example, registered row/column address signals A 0 A_ 2 , A 1 A_ 2 , . . . , A 15 A_ 2 , registered bank address signals BA 0 A_ 2 , BA 1 A_ 2 , and BA 2 A_ 2 , and registered control signals RASA_ 2 , CASA_ 2 , WEA_ 2 , CS 2 A, CKE 2 A, ODT 1 A. The second set of the two identical sets of registered C/A signals may include, for example, registered row/column address signals A 0 B_ 2 , A 1 B_ 2 , . . . , A 15 B_ 2 , registered bank address signals BA 0 B_ 2 , BA 1 B_ 2 , and BA 2 B_ 2 , and registered control signals RASB_ 2 , CASB_ 2 , WEB_ 2 , CS 2 B, CKE 2 B, ODT 1 B. 
     In one embodiment, each respective memory device on the memory module  120  receives a set of registered C/A signals from one of the register devices and, in response thereto, communicate corresponding bits of data and strobe signals with the memory controller  110  via corresponding data/strobe pins of the memory module and corresponding I/O pins of the respective memory device. In one embodiment, each data pin correspond to a corresponding data bit of a data signal, which can be, for example, 72-bit wide or 64-bit wide with or without error correction bits, respectively. In one embodiment, each memory device is 4-bit wide, and a respective group of three memory devices, one from each of the three ranks, correspond to 4 respective data pins. 
     For example, a first group of memory devices include memory device U 1  from the second rank, memory device U 19  from the first rank, and memory device U 39  from the third rank. Memory device U 1  receives the first set of registered C/A signals output by the register device  37 A except the chip select signal CS 0 A and in response communicate corresponding data and strobe bits via data/strobe pins DQ 0  DQ 1 , DQ 2 , DQ 3 , DQS 0 , and DQS 0 # with the memory controller  110 ; memory device U 19  receives the first set of registered C/A signals output by the register device  37 A except the chip select signal CS 1 A and in response communicate data and strobe signals via data/strobe pins DQ 0  DQ 1 , DQ 2 , DQ 3 , DQS 0 , and DQS 0 # with the memory controller  110 ; and memory device U 39  receives the first set of registered C/A signals output by the register device  38 A and in response communicate data and strobe signals via data/strobe pins DQ 0  DQ 1 , DQ 2 , DQ 3 , DQS 0 , and DQS 0 # with the memory controller  110 . 
     Also, a second group of memory devices include memory device U 10  from the second rank, memory device U 28  from the first rank, and memory device U 48  from the third rank. Memory device U 10  receives the first set of registered C/A signals output by the register device  37 A except the chip select signal CS 0 A and in response communicate corresponding data and strobe bits via data/strobe pins DQ 4  DQ 5 , DQ 6 , DQ 7 , DQS 9 , and DQS 9 # with the memory controller  110 ; memory device U 28  receives the first set of registered C/A signals output by the register device  37 A except the chip select signal CS 1 A and in response communicate data and strobe signals via data/strobe pins DQ 4  DQ 5 , DQ 6 , DQ 7 , DQS 9 , and DQS 9 # with the memory controller  110 ; and memory device U 48  receives the first set of registered C/A signals output by the register device  38 A and in response communicate data and strobe signals via data/strobe pins DQ 4  DQ 5 , DQ 6 , DQ 7 , DQS 9 , and DQS 9 # with the memory controller  110 . 
     Each memory device receives the corresponding registered C/A signals from one of the register devices via signal lines in the form of, for example, board traces. Further, each memory device is also coupled to the respective data/strobe pins via signal lines in the form of, for example, board traces. 
     In certain embodiments, memory module  200  includes contact hubs (such as contact hubs  401  and  402  shown in  FIG. 4A ) that are positioned away from the bottom edge  128  of the module board  122 , and signal lines (such as board traces  411  to  412  shown in  FIG. 4A ) connecting the respective contact hubs to corresponding ones of the data/strobe pins  126 . The contact hubs can be, for example, metal pads or solder balls disposed on or near the primary side or secondary side of the memory module  120 , and/or vias in the module board  122 . 
     In one embodiment, each contact hub is coupled to a corresponding I/O pin of each of a group of memory devices including one memory device from each of the ranks. For example, as shown in  FIG. 4 , in which solid dots  415  represent contact pins on memory devices disposed on the primary side  120   a  of the memory module  120  and empty dots  416  represent contact pins on memory devices disposed on the secondary side  120   b  of the memory module  120 , contact hub  401  is coupled via star traces  421  to a corresponding contact pin of memory device U 1  in the second rank, a corresponding contact pin of memory device U 19  in the first rank, and a corresponding contact pin of memory device U 39  in the third rank. 
     Similarly, as also shown in  FIG. 4A , contact hub  402  is coupled via star traces  422  to a corresponding contact pin of memory device U 10  in the second rank, a corresponding contact pin of memory device U 28  in the first rank, and a corresponding contact pin of memory device U 48  in the third rank. 
     Thus, memory devices are connected to the module connectors  126  via the contact hubs and multiple memory devices can be coupled to the respective module connectors via a same set of signal traces on/in the module board  201 . For example, as shown in  FIG. 4A , memory devices U 1 , U 19 , and U 39  are coupled to the module connector for DQ 0  via a same contact hub  401  and a same signal trace  411 . 
     In one embodiment, each of the contact hubs is positioned to reduce difference in lengths of the signal paths between respective ones of the memory devices coupled thereto and a corresponding module connector. For example, as shown in  FIG. 4A , contact hub  401  is positioned to be between memory devices U 1  and U 39  and closer to memory device U 39  in order to reduce differences in the signal path lengths via the star traces  421 , resulting in reduced differences in the signal path lengths from memory devices U 1 , U 19 , and U 39  to each of the module pins for DQ[0:3], DQS 0  and DQS 0 #. 
     Similarly, as shown in  FIG. 4B , contact hub  402  is positioned to be between memory devices U 48  and U 28  and closer to memory device U 28  in order to reduce differences in the signal path lengths via the star traces  422 , so as to reduce differences in the signal path lengths from memory devices U 10 , U 28 , and U 48  to each of the module pins for DQ[4:7], DQS 9  and DQS 9 #. 
     Further, one or more of the signal traces  411  and  412  may be routed to reduce a difference in length therebetween. As also shown in  FIG. 4A , since the contact hub  402  is closer to the bottom edge  128  of the module board  201  than the contact hub  401 , the signal trace  412  is routed to make it significantly longer than the distance between the contact hub  402  and the bottom edge  128  of the module board so as to reduce the difference in lengths between signal trace  411  and signal trace  412 . Thus, as shown in  FIG. 4A , instead of using a straighter path between module connector for DQ 4  and contact hub  402 , a more circuitous route for the signal trace  412  is used. 
     In one embodiment, as shown in  FIG. 4B , one or more of the star traces  421  may include at least one via  421   a  and at least one signal trace  421   b  in at least one different layer of the module board from the other ones of the star traces  421  in order to reach the memory device on a side of the module board that is different from the side on which the contact hub  401  is disposed, or to which the contact hub  401  is closer. In one embodiment, contact hub  401  is disposed on or is closer to the primary side  120   a  of the memory module  120 . 
     Likewise, one or more of the star traces  422  may include at least one via  422   a  and at least one signal trace  422   b  in at least one different layer of the module board in order to reach the memory device on a side of the module board that is different from the side on which the contact hub  402  is disposed, or to which the contact hub  402  is closer. In one embodiment, contact hub  402  is disposed on or is closer to the secondary side  120   b  of the memory module  120 . 
     The signal traces shown in  FIGS. 4A and 4B  are exaggerated and straightened for ease of illustration. In practice the signal lines or traces between the module connectors and the contact hubs, and between the contact hubs and the input/output pins of the memory devices are routed around various contacts and/or vias on/in the module board. Each of these traces may include multiple sections in different layers of the module board and may include one or more vias. 
       FIG. 4C  is a side view of the memory module  120  and  FIG. 4D  is a schematic diagram illustrating electrical couplings between the data/strobe pin DQ 0  and memory devices U 1 , U 19 , and U 39 . As shown in  FIG. 4D , the signal trace  411  can include one or more board traces  411   a  in the same or different layers, one or more vias  411   b , and one or more discrete component  411   c.    
     In certain embodiments, the memory module  120  can include more than one module boards, and the memory devices can be arranged differently. For example, the memory module  120  can utilize the planar-X technology disclosed in commonly-owned co-pending U.S. patent application Ser. No. 13/653,254, entitled “Circuit with Flexible Portion,” filed on Oct. 16, 2012, and U.S. patent application Ser. No. 13/731,034, entitled “Module Having at Least One Thermally Conductive Layer between Printed Circuit Boards,” filed on Dec. 30, 2012, each of which is incorporated by reference herein in its entirety. The planar-X technology can provide a more symmetric topology for a 3-ranked memory module with significantly shorter vertical dimension. 
     As shown in  FIG. 5A , the memory module  120  can have a main module board  122   a  and two daughter boards  122   b  and  122   c  each having a flexible portion  500  having flexible traces that are coupled respectively to corresponding contacts  501  on the main module board  122   a . Some of the memory devices, such as the first group of memory devices U 1 , U 19 , and U 39  are mounted on the daughter board  122   b , and some of the memory devices, such as the second group of memory devices U 10 , U 28 , and U 48  are mounted on the daughter board  122   c . These memory devices are coupled via signal traces on the daughter boards and the main module board to the module connectors  126  near the bottom edge  128  of the main module board  122   a , as shown in  FIG. 5A . 
     For example, as shown in  FIG. 5A , the first group of memory devices are coupled to a corresponding data/strobe pin (e.g., DQ 0 ) among the module connectors  126  near the bottom edge  128  of the main module board  122   a  via star traces  421 , contact hub  401 , signal trace  411  on the daughter board  122   b , a corresponding flexible trace on the flexible portion  501 , and a corresponding trace on the main module board  122   a .  FIG. 5B  is a schematic diagram illustrating electrical couplings between the data/strobe pin and memory devices U 1 , U 19 , and U 39 . 
       FIG. 5C  is a top view of the planar-X multi-rank memory module shown in  FIG. 5A , illustrating arrangement of the memory devices  510  and one register  520  on one side of a daughter board  500 , which can be either one of the daughter boards  122   b  and  122   c . As shown, the register  520  outputs two sets of registered C/A signals, one toward a left side A of the daughter board  500  and one toward the right side A′ of the daughter board  500 . The two sets of registered C/A signals are similar to those output by register  37 A described above except that each set of registered C/A signals would include three chip select signals CS 0 , CS 1  and CS 2  instead of two chip select signals CS 0  and CS 1 . Some of the C/A signals such as the chip select signals are provided respectively to memory devices in different ranks. 
     The set of registered C/A signals toward the left edge A are output via each of two sets of C/A signal line  530   a  and  530   b  to the memory devices  510  disposed between the left edge A and the register device  520 . Likewise, the set of registered C/A signals toward the right edge A′ are output via each of two sets of C/A signal line  530   c  and  530   d  to the memory devices  510  disposed between the left edge A and the register device  520 . Thus, the set of signal lines  530   b  would have twice the amount of memory device load as the set of signal lines  530   a . Likewise, the set of signal lines  530   d  would have twice the amount of memory device load as the set of signal lines  530   c . Although this configuration may result in asymmetric loading for registered C/A signals from the registers, with proper termination, good signal quality for the registered C/A signals can be achieved. Note that because two register devices are used, this configuration would result in two register device loads for each pre-registered C/A signal from the memory controller. 
       FIG. 6A  illustrates a planar design for a 3-ranked RDIMM (registered dual in-line memory module)  120  according to embodiments. As shown in  FIG. 6A , the 3-ranked RDIMM  120  includes a module board  122 , and dual-die packages (DDP) on one side of the module board and single die packages (SDP) on opposite side of the module board  122 . This placement can create asymmetric data lines, as the DRAMs located closer to the bottom edge  128  of the module board  122  would have shorter trace length compared to the DRAMs located along the top edge of the module board  122 . Also data signals communicated with the DDP would have higher loading compared to data signals communicated with the SDP, as shown in  FIG. 6B . 
       FIG. 6C  is a top view of the 3-ranked RDIMM shown in  FIG. 6A , which utilizes two register devices  602 , one on each side of the module board  122  to drive the DRAMs on the same side of the module board. The input/output signals of register  602  on the same side of the DDPs can be the same or similar to the register  37 U, and the input/output signals of register  602  on the same side of the SDPs can be the same or similar to the register  38 U. In such a configuration, the output of each register would have fairly balanced loading for the registered C/A signals. The register device on the same side of the DDP&#39;s, however, would drive twice the number of DRAMs than the register device on the opposite side of the module board. Higher number of resisters can be used to terminate all registered C/A signals to insure good signal quality. Again, this configuration would result in two loads for each pre-registered C/A signal. 
       FIG. 6D  is a top view of the 3-ranked RDIMM shown in  FIG. 6A , which utilized only one register device  602  on one side of the module board  122 , e.g., the same side of the module board as the DDP&#39;s. This register device  602  can be similar to the register  520  (e.g., outputting three chip select signals) and would drive the DRAMs on both sides of the module board  122 . This configuration would result in symmetrical loading for the registered C/A signals and one memory device load for each pre-registered C/A signal. It should be more suited for high-speed operation with two DIMM per channel.