Patent Publication Number: US-2023133063-A1

Title: Leakage and loading detector circuit

Description:
TECHNICAL FIELD 
     Various exemplary embodiments disclosed herein relate generally to a circuit that monitors its external terminals to detect current leakage when nothing is connected to the circuit or the presence of a load between terminals of the circuit. 
     SUMMARY 
     A summary of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope of the invention. Detailed descriptions of an exemplary embodiment adequate to allow those of ordinary skill in the art to make and use the inventive concepts will follow in later sections. 
     Various embodiments relate to a detector circuit, including: a voltage source configured to produce a first voltage on a first output, a second voltage on a second output, and third voltage on a third output, wherein the first voltage is greater than the second voltage and the second voltage is greater than the third voltage; a first switch connected to the second output; a sampling capacitor connected to the switch, wherein the sampling capacitor is charged by the voltage source when the switch is closed; a first comparator with one input connected to the first output and a second input connected to the sampling capacitor; a second comparator with one input connected to the third output and a second input connected to the sampling capacitor; a multiplexer with a plurality of inputs configured to be connected to a plurality of terminals of an external circuit and an output connected to the sampling capacitor, the first input of the first comparator, and the first input of the second comparator; and a controller with inputs connected to the first comparator, the second comparator, and a clock generation unit, wherein the controller is configured to produce control signals to control the first switch and the multiplexer and wherein the controller is configured to produce an output signal indicting the presence of a current leak on one of the plurality of terminals. 
     Further various embodiments relate to a sensor system, including: a sensor; and a sensor interface circuit including a detector circuit including: a voltage source configured to produce a first voltage on a first output, a second voltage on a second output, and third voltage on a third output, wherein the first voltage is greater than the second voltage and the second voltage is greater than the third voltage; a first switch connected to the second output; a sampling capacitor connected to the switch, wherein the sampling capacitor is charged by the voltage source when the switch is closed; a first comparator with one input connected to the first output and a second input connected to the sampling capacitor; a second comparator with one input connected to the third output and a second input connected to the sampling capacitor; a multiplexer with a plurality of inputs configured to be connected to a plurality of terminals of an external circuit and an output connected to the sampling capacitor, the first input of the first comparator, and the first input of the second comparator; and a controller with inputs connected to the first comparator, the second comparator, and a clock generation unit, wherein the controller is configured to produce control signals to control the first switch and the multiplexer and wherein the controller is configured to produce an output signal indicting the presence of a current leak on one of the plurality of terminals. 
     Various embodiments are described, wherein the voltage source includes a bandgap voltage source and a bandgap buffer. 
     Various embodiments are described, further including a plurality of additional switches connected between each of the plurality of terminals and ground, wherein the control signals produced by the controller include signals to control the plurality of additional switches. 
     Various embodiments are described, wherein the controller is configured to: close the first switch to charge the sampling capacitor; connect one of the plurality terminals to the sampling capacitor using the multiplexer; open the first switch; and monitor the outputs of the first comparator and the second comparator to determine if there is a current leak on the connected terminal. 
     Various embodiments are described, wherein the controller is further configured to measure the leakage current. 
     Various embodiments are described, wherein the output signal further indicates a connection to the external circuit. 
     Various embodiments are described, wherein the controller is configured to: connect all but one of the plurality of terminals to ground using the plurality of additional switches; close the first switch to charge the sampling capacitor; open the first switch; connect one terminal not connected to ground to the sampling capacitor using the multiplexer; and monitor the outputs of the first comparator and the second comparator to determine if the detection circuit is connected to the external circuit. 
     Various embodiments are described, wherein the controller is further configured to measure a resistance of the external circuit. 
     Various embodiments are described, wherein the output signal indicates a connection to the external circuit when a voltage on the sampling capacitor drops below the third voltage. 
     Various embodiments are described, wherein the output signal indicates the presence of a current leak when a voltage on the sampling capacitor drops below the third voltage. 
     Further various embodiments relate to a method for detecting a current leak in an external circuit using a detector circuit, including: producing a first voltage on a first output of a voltage source, a second voltage on a second output of a voltage source, and third voltage on a third output of a voltage source, wherein the first voltage is greater than the second voltage and the second voltage is greater than the third voltage; charging a sampling capacitor using the second voltage by closing a switch connected between the sampling capacitor and the voltage source; opening the first switch; comparing a voltage on the sampling capacitor with the first output; comparing a voltage on the sampling capacitor with the second output; selecting one of a plurality of inputs configured to be connected to a plurality of terminals of an external circuit; connecting the selected input to the sampling capacitor; producing control signals, by a controller, to control the first switch and the selecting one of a plurality of inputs; and producing an output signal indicting the presence of a current leak on one of the plurality of terminals. 
     Various embodiments are described, producing, by the controller, signals to control a plurality of additional switches connected between each of the plurality of terminals and ground. 
     Various embodiments are described, further including measuring, by the controller, the leakage current. 
     Various embodiments are described, wherein the output signal further indicates a connection to the external circuit. 
     Various embodiments are described, further including; connecting all but one of the plurality of terminals to ground using the plurality of additional switches; closing the first switch to charge the sampling capacitor; opening the first switch; connecting one terminal not connected to ground to the sampling capacitor using the multiplexer; and monitoring the outputs of the first comparator and the second comparator to determine if the detection circuit is connected to the external circuit. 
     Various embodiments are described, further including measuring, by the controller, a resistance of the external circuit. 
     Various embodiments are described, wherein the output signal indicates a connection to the external circuit when a voltage on the sampling capacitor drops below the third voltage. 
     Various embodiments are described, wherein the output signal indicates the presence of a current leak when a voltage on the sampling capacitor drops below the third voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to better understand various exemplary embodiments, reference is made to the accompanying drawings, wherein: 
         FIG.  1    illustrates a diagram of a detection circuit that may be used to detect current leakage in and connectivity to a circuit; 
         FIG.  2    illustrates the operation circuit during the leakage current detection mode; 
         FIG.  3    illustrates plots of various voltages and control signals during the leakage current detection mode; 
         FIG.  4    illustrates the operation of the circuit during the sensor connection and/or hydration mode; and 
         FIG.  5    illustrates plots of various voltages and control signals during the sensor connection and/or hydration mode. 
     
    
    
     To facilitate understanding, identical reference numerals have been used to designate elements having substantially the same or similar structure and/or substantially the same or similar function. 
     DETAILED DESCRIPTION 
     The description and drawings illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Additionally, the term, “or,” as used herein, refers to a non-exclusive or (i.e., and/or), unless otherwise indicated (e.g., “or else” or “or in the alternative”). Also, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. 
     During the production of circuits including circuits to interface electrochemical sensors, a monitoring circuit may be used to measure a pad/node leakage during production testing. Further, once the electrochemical sensor is placed in use, the monitoring circuit may verify that the electrochemical sensor has been successfully connected and is operating. One example of such an electrochemical sensor is a continuous glucose monitoring sensor. A continuous glucose monitoring (CGM) sensor is hydrated and then variations in the glucose level may be measured through terminals of the chip interfacing the CGM sensor so that the glucose level may be monitored. The CGM sensor may include three terminals: CE; RE, and WE. Likewise, the circuit interfacing the CGM sensor may also have CE, RE, and WE terminals. The RE terminal is a reference electrode of the sensor that maintains a constant reference voltage for WE electrode. The WE terminal is a work electrode of the sensor where the electrochemical reaction occurs, hence the current is generated and read. The CE terminal is a counter electrode of the sensor that is a connection to the electrolyte for current to compensate for reaction at the WE terminal. The current reading of a CGM circuit needs to be accurate to a few pA, and potential leakage on the RE pin can damage the sensor. During production, each of these terminals may be tested to determine if the terminal has any current leakage in order to prevent damage to the CGM sensor via leakage at the RE terminal. Due to the low-power nature of wearables electronics applications where a CGM or another sensor is deployed, it is equally important to be able to detect when a CGM sensor is physically connected to an integrated circuit and hydrated by the interstitial fluid on the human body, i.e., when the dedicated CGM sensor analog front-end (AFE) may start operating. Further, once the CGM circuit is in use, a resistance should appear between the RE and WE terminals of the CGM circuit. A detector circuit is described herein that may be used to detect current leakage of the various terminals of a circuit. Further, the detector circuit may be able to monitor the sensor during use to verify that it is properly connected and loaded, i.e., hydrated in the case of a CGM sensor. The detector circuit described herein will avoid the use of expensive and complex analog to digital circuits and other such circuits to result in a detector circuit that is accurate and inexpensive to implement. 
     A glucose monitoring circuit with three terminals is used as an example herein, but other types of circuits or sensors that requires leakage detection during production and/or determining the connection and operation of the circuit during use. Further, the detection circuit described herein may be used with circuits that have any number of terminals that need to be monitored. 
       FIG.  1    illustrates a diagram of a detection circuit that may be used to detect current leakage and connectivity between pins in a circuit. The monitored system is a CGM system where the leakage of a CGM readout circuit and the hydration of the CGM sensor are detected. The detection circuit  100  includes a bandgap voltage reference  102 , bandgap buffer  104 , sampling capacitor C,  106 , first comparator  108 , second comparator  110 , controller  112 , clock generation unit  114 , and a mux  116 . The bandgap voltage reference  102  produces three output voltages: V bg  and V bg +/−ΔV. The voltage V bg  is buffered by the bandgap buffer  104  to isolate the bandgap voltage from the sampling capacitor C s    106  as the sensor capacitance can be much larger than the integrated Cs, and in that case the bandgap voltage may jump down when connected to the empty parasitic capacitor. In this example, the bandgap buffer  104  is implemented with an operational amplifier, but other implementations may be used as well. The switch  118  is connected between the bandgap buffer  104  and the sampling capacitor C s    106 . When the switch  118  is closed the buffered bandgap voltage V bg  is sampled by charging the sampling capacitor C s    106 . The switch  118  may be controlled by a control signal  126  output by the controller  112 . The switch  118  may be implemented using any type of switch typically used in electrical circuits. 
     The first comparator  108  receives V bg +ΔV as one input and the sampling capacitor voltage V cap  as the other input. The output of the first comparator  108  indicates whether the sampling capacitor voltage V cap  is above or below V bg +ΔV. The second comparator  110  receives V bg −ΔV as one input and the sampling capacitor voltage V cap  as the other input. The output of the second comparator  110  indicates whether the sampling capacitor voltage V cap  is above or below V bg −ΔV. The comparators  108 ,  110  may be implemented using operational amplifiers or any other typically used circuit. 
     The controller  112  receives the outputs of the first comparator  108  and the second comparator  112  and a clock signal from the clock generation unit  114 . The controller  112  produces various control signals  126  that are used to control the MUX  116  and the various switches  118 ,  120 ,  122 ,  124 . The operation of the controller  112  will be further described below. The controller  112  may be implemented using a small programable microcontroller, a processor, a state machine, or dedicated logic that implements the desired control features and steps. 
     The MUX  116  is connected to the three terminals CE  130 , RE  132 , and WE  134  of a chip interfacing the CGM sensor. The output of the MUX  116  is connected to a node between the sampling capacitor C s    106  and the first comparator  108  and the second comparator  110 . The MUX  116  receives a control signal  126  from the controller  112  that controls which of the three inputs (i.e., CE  130 , RE  132 , and WE  134 ) if any are connected to the output of the MUX  116 . The MUX  116  is shown as having three inputs, but the MUX  116  may have fewer or more inputs depending upon the number of inputs that the circuit to be monitored has. 
     The switches  120 ,  122 ,  124  are connected to the terminals  130 ,  132 ,  134 . The switches  120 ,  122 ,  124  are also connected to ground which is designated as VSS, so that when any of the switches  120 ,  122 ,  124  are closed, the corresponding terminal is connected to ground. Three switches are illustrated, but fewer or more switches may be used depending upon the number of circuit inputs that need to be monitored. 
     The detection circuit  100  has two modes of operation including a leakage current detection mode and a sensor connection and/or hydration mode. The leakage current detection mode may be used during production to detect if any of the terminals of the chip exhibit excessive current leakage. The sensor connection and/or hydration mode may be used to detect that the sensor is properly connected and/or properly hydrated (as in the case of a CGM sensor). 
       FIG.  2    illustrates the operation of the detection circuit during the leakage current detection mode.  FIG.  3    illustrates plots of various voltages and control signals in the detection circuit during the leakage current detection mode. The leakage current detection mode includes the following steps: open the switches  120 ,  122 ,  124  connecting the terminals CE  130 , RE  132 , and WE  134  to ground; sample the bandgap voltage on sampling capacitor C s    106  by closing switch  118 ; connect the terminal to be measured to C, by using the MUX  116 ; and open the switch  118  and then the controller  112  monitors the comparator outputs for a period of time. This process may be repeated for each of the terminals as needed. 
       FIG.  2    illustrates a current leakage source  140  connected to the WE terminal  134 . As this leakage source is now connected to the sampling capacitor C S , the leakage source will cause the sense capacitor voltage V cap  to decrease or increase over time. As a result, the output of the first comparator  108  will indicate that the sense capacitor voltage C cap  is now greater than V bg +ΔV or the output of the second comparator  110  will indicate that the sense capacitor voltage C cap  is now less than V bg −ΔV after a certain time interval based upon the clock signal from the clock generation unit. A counter in the controller  112  may count clock cycles from the clock generation unit  114 , and the leakage current may be derived by measuring the time between the opening of the switch  118  and the time when the sense capacitor voltage C cap  falls below V bg −ΔV or above V bg +ΔV as follows: 
     
       
         
           
             
               ± 
               
                 I 
                 leak 
               
             
             = 
             
               ± 
               
                 
                   Δ 
                   ⁢ 
                   V 
                   * 
                   
                     C 
                     s 
                   
                 
                 
                   Δ 
                   ⁢ 
                   t 
                 
               
             
           
         
       
     
     If measuring the actual value of the leakage current is not essential, and the measurement objective is to only detect a maximum allowed leakage current in production, the programmable parameter Δt may be fixed by the controller. Note that this circuit can detect both leakage current polarities on a node, i.e., a current flowing into the sense capacitor C s    106  or a current flowing out of the sense capacitor C s    106 . 
       FIG.  3    includes plots of the voltages V bg +ΔV  302 , V cap    304 , and V bg −ΔV  306 . Further, plots of the output for the first comparator  308  and the second comparator  310  are illustrated. A plot of an enable signal  312  that is used to enable the operation of the detection circuit is also illustrated. A plot of a control signal connect_vref  314  illustrates the time when the switch  118  is closed to charge the sampling capacitor C s    106 . Finally, a control signal connect_sensor  316  illustrates the time when the MUX  116  connects one of the terminals  130 ,  132 ,  134  to the sampling capacitor C S    106 . When the enable signal  312  goes high the detection circuit can begin to operate. At this point V cap  is 0V so the output of the second comparator  110  goes high because V cap  is below V bg −ΔV. The output  308  of the first comparator remains zero because V cap  is below V bg +ΔV except for startup artifacts which will be digitally gated out. Shortly after the enable signal  312  goes high, the signal connect_ref  314  goes high to close the switch  118  for a period of time so that the sampling capacitor C s    106  is charged. Also the connect_sensor signal  316  goes high to enable the MUX  116  to connect one of the terminals to be tested to the sampling capacitor C s    106 . As a result, the plot of V cap    304  increases to the value of V bg  that causes the output  310  of the second comparator to become low because V cap  is now above V bg −ΔV. Over time the value of Vcap decreases because of a current leak, and once V cap    304  decreases below V bg −ΔV  306 , the output  310  of the second comparator goes high. This indicates to the controller  112  that there is a current leak and the controller may indicate to a user or testing apparatus that the pin being tested has a current leak. Then the enable signal  312  goes low, which disables the detection circuit so the output  310  of the second comparator goes low. Further, one of the switches  120 ,  122 ,  124  corresponding to the terminal being tested may be closed to ground the sampling capacitor C s    106  to discharge it so that its output  304  goes to 0V. In other embodiments this may not be done in order to save power. 
       FIG.  4    illustrates the operation of the detection circuit during the sensor connection and/or hydration mode.  FIG.  5    illustrates plots of various voltages and control signals in the detection circuit during the sensor connection and/or hydration mode. The sensor connection and/or hydration mode includes the following steps: connect the CE terminal  130  and the WE terminal  134  to ground; sample the bandgap voltage on sampling capacitor C s    106  by closing switch  118 ; connect the RE terminal  132  to the sampling capacitor C s    106  using the MUX  116  and then open the switch  118 ; and monitor the comparator outputs using the controller  112  for a period of time to determine if V cap  decays indicating connection and/or hydration and to determine a load resistance value R if desired. 
     A hydrated CGM sensor connected between WE and RE will create an impedance to ground in parallel to the discharging sampling capacitor C s    106 . A maximum impedance can be measured by defining a programmable time interval after opening the switch  118  and the voltage difference ΔV on the output of the second comparator  110 . 
     The discharging voltage on the sampling capacitor C s    106  will have the following exponential equation: 
     
       
         
           
             
               
                 
                   V 
                   cap 
                 
                 = 
                 
                   
                     V 
                     bg 
                   
                   ( 
                   
                     e 
                     
                       - 
                       
                         t 
                         
                           RC 
                           s 
                         
                       
                     
                   
                   ) 
                 
               
               ) 
             
             . 
           
         
       
     
     Accordingly, knowing the value of V cap  at a specific time t, will allow the value of R to be calculated. This value then can be used to determine if the sensor is connected and is properly operating/hydrated. 
       FIG.  5    includes plots of voltages at voltages V bg +ΔV  510 , V cap    512 , and V bg −ΔV  514 . A plot of a control signal enable_and_ground_CE_WE  504  is shown that indicates when the terminals CE  130  and WE  134  are grounded, and the detection circuit is enabled. A plot of a control signal connect_vref  506  illustrates the time when the switch  118  is closed to charge the sampling capacitor C s    106 . A control signal connect_sensor  508  illustrates the time when the MUX  116  connects the RE terminal  132  to the sampling capacitor C s    106 . Finally, a plot of the output  502  of the first comparator  108  and the output  516  of the second comparator  110  are illustrated. 
     When the enable signal  504  goes high, the terminals CE  130  and WE  134  are grounded. This causes the voltage at the CE terminal  130  and WE terminal  134  to be grounded and go to 0V. Further, at this point the output  516  of the second comparator  110  will go high indicating that V cap    512  is below V bg −ΔV  514 . Next, the signal connect_vref  506  goes high to close the switch  118  for a period of time so that the sampling capacitor C s    106  is charged. This results in V cap    514  increasing to the voltage level of V bg , and the output of the second comparator  110  will go low indicating that V cap    512  is above V bg −ΔV  514 . Shortly thereafter the connect_sensor signal  508  goes high to enable the MUX  116  to connect the RE terminal  132  to the sampling capacitor C s    106 . Over time the value of V cap  decreases because the charge on the sampling capacitor  106  is dissipated in the resistance R (as described by the equation above), and once V cap    512  decreases below V bg −ΔV  514 , the output  516  of the second comparator goes high. This indicates to the controller  112  that the sensor is connected and/or hydrated. Based upon the voltage change and the amount of time taken to result in the voltage change, a value for R may be calculated as described above. The enable signal  504  can then go low to disable the operation of the detection circuit. 
     In an alternative embodiment, for a better resolution, it is also possible to calibrate the detection circuit in the leakage monitor mode by applying an external known current and repeating the leakage measurement. The application of the known current allows for the calculation of a calibration constant that is used to compensate the repeated leakage measurement. 
     The values of V bg  and ΔV may be programmable and allow for the ability to detect a wide range of leakage currents and resistance values. 
     The detection circuit described herein may effectively measure the leakage of a node/pad during chip or integrated circuit (IC) test production to help identified faulty samples to be discarded or to detect a finite impedance between two electrodes in order to wake-up more power consuming sensor readout circuitry during application. The detection circuit does not require any ADC or complex circuitry. Further the detection circuit can be easily calibrated, and it can be programmed for a wide range of leakage currents and resistance values. 
     It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. 
     Although the various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects thereof, it should be understood that the invention is capable of other embodiments and its details are capable of modifications in various obvious respects. As is readily apparent to those skilled in the art, variations and modifications can be affected while remaining within the spirit and scope of the invention. Accordingly, the foregoing disclosure, description, and figures are for illustrative purposes only and do not in anyway limit the invention, which is defined only by the claims.