Patent Publication Number: US-2023152681-A1

Title: Euv masks to prevent carbon contamination

Description:
RELATED APPLICATIONS 
     The present application is a continuation application of U.S. application Ser. No. 17/532,939, filed Nov. 22, 2021, now U.S. Pat. No. 11,561,464, issued Jan. 24, 2023, which is a continuation application of U.S. application Ser. No. 16/746,640, filed Jan. 17, 2020, now U.S. Pat. No. 11,221,554, issued Jan. 11, 2022, which are herein incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     Optical lithography may be performed in a variety of different ways. One example of an optical lithography process includes extreme ultra violet (EUV) lithography. EUV lithography is based on exposure with a portion of the electromagnetic spectrum having a wavelength of 10-15 nanometers. 
     In one example, an EUV mask may be used to define structures within layers of a substrate. EUV masks may be reflective. Thus, a pattern on an EUV mask may be defined by selectively removing an absorber layer to uncover portions of an underlying mirror coated on a substrate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    illustrates a cross-sectional view of an extreme ultra-violet (EUV) mask according to at least one embodiment of the present disclosure; 
         FIG.  2    illustrates a cross-sectional view of the EUV mask with a multi-layered absorber layer according to at least one embodiment of the present disclosure; 
         FIG.  3    illustrates a flowchart of a method of forming an EUV mask according to at least one embodiment of the present disclosure; 
         FIGS.  4 A- 4 J  are partial cross-sectional views of the EUV mask at various stages of manufacture in accordance with at least one embodiment of the present disclosure; and 
         FIG.  5    illustrates a schematic view of an example EUV lithography system that uses the EUV mask of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     The advanced lithography process, method, and materials described in the current disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs can be processed according to the above disclosure. 
     The present disclosure is related to various embodiments of an EUV mask that prevents carbon contamination. Carbon contamination can negatively affect the critical dimension of features formed in an absorber layer and a capping layer of the EUV mask. For example, some metal capping layers may have many free radicals that can react with the hydrocarbons near the EUV mask surface during exposure. During exposure, the hydrocarbons can be cracked near the surface of the EUV mask when exposed to high energy. The buildup of carbon on the metal layer can create issues in the wafer critical dimension. 
     The present disclosure broadly provides a multi-layered absorber layer or multi-layered capping layer in the EUV mask. At least one layer of the EUV mask may include an oxide. The oxide may act as an insulator that minimizes reaction of the absorber layer with hydrocarbons or carbon during wafer printing. 
       FIG.  1    illustrates an example of an EUV mask  100  of the present disclosure. The EUV mask  100  may include a substrate  102 , a multi-layered (ML) mirror layer  104 , a metal capping layer  106 , and a multi-layered absorber layer  108 . In one embodiment, the substrate  102  may be a low thermal expansion material (LTEM) that is deposited on a layer  150 . The layer  150  may be a tantalum boron (TaB) layer or chromium nitride (CrN) layer. The substrate  102  may have a low defect level and a smooth surface. The substrate  102  may be glass, a glass-ceramic material, or silicon. 
     In one embodiment, the ML mirror layer  104  may include alternating layers of a high index of refraction material  112  and a low index of refraction material  114 . In one example, the high index of refraction material  112  may be Molybdenum (Mo) and the low index of refraction material  114  may be Silicon (Si). However, it should be noted that any types of materials can be used. In one embodiment, 40 pairs of the high index of refraction material  112  and the low index of refraction material  114  may be formed on the substrate  102 . However, it should be noted that any number of pairs can be deployed in the ML mirror layer  104 . 
     The thickness of the high index of refraction material  112  and the low index of refraction material  114  may be a function of an illumination wavelength that is selected and an incidence angle of the illumination light. In one embodiment, the thickness of the high index of refraction material  112  and the low index of refraction material  114  may be selected to maximize the constructive interference of the EUV light reflected at each interface and to minimize the overall absorption of the EUV light. 
     In one embodiment, the thickness of the high index of refraction material  112  and the low index of refraction material  114  may be approximately one quarter of the illumination wavelength. For example, if the wavelength is 10 nanometers (nm), the thickness of the high index of refraction material  112  and the low index of refraction material  114  may each be approximately 2.5 nm. In one embodiment, the thickness of the high index of refraction material  112  and the low index of refraction material  114  may be different. 
     In one embodiment, a metal capping layer  106  may be deposited on top of the last layer of the ML mirror layer  104 . The metal capping layer  106  may prevent oxidation of the high index of refraction material  112  (e.g., Mo) by exposure to the environment. In one embodiment, the metal capping layer  106  may comprise ruthenium (Ru) or ruthenium oxide (RuO 2 ). The metal capping layer  106  may be deposited with a thickness of approximately 2.5-5.5 nm. In one embodiment, the metal capping layer  106  may be deposited with a thickness of approximately 3.5 nm. 
     In one embodiment, the multi-layered absorber layer  108  may comprise multiple layers including an oxide containing absorber layer. In other words, the multi-layered absorber layer  108  may include at least one layer that contains an oxide. The oxide may act as an insulator to prevent carbon contamination. For example, the oxide may minimize reaction layers of the multi-layered absorber layer  108  with hydrocarbons or carbon that is produced during printing of the multi-layered absorber layer  108 . The hydrocarbons can contaminate the capping layer which may impact the critical dimension of the wafer. Further details of the different layers are illustrated in  FIG.  2    and discussed in further details below. 
     In one embodiment, the multi-layered absorber layer  108  may include features  110   1  to  110   n  (hereinafter also referred to individually as a feature  110  or collectively as features  110 ). The features  110  may be etched into the multi-layered absorber layer  108 . The features  110  may define areas where EUV light may pass through to the ML mirror layer  104  to define structures in a semiconductor device. 
     As noted above, some metal capping layers may have free radicals that can react with hydrocarbons near the EUV mask surface during exposure to the EUV light. The hydrocarbons may be cracked into carbon. The aliphatic hydrocarbons or aromatic hydrocarbons may be directly deposited on the metal capping layer  106 . The carbon or hydrocarbon on the metal capping layer  106  can create issues in the critical dimensions (CD) of the features on the wafer. For example, carbon or hydrocarbon contamination can create CD drift including proximity trends or CD uniformity changes. These issues can negatively affect the performance of the EUV mask  100 . 
     The present disclosure provides the multi-layered absorber layer  108  that may include oxides to eliminate carbon contamination and improve CD uniformity in the features  110 . The oxide layer or layers in the multi-layered absorber layer  108  may act as an insulator that does not react with the carbon or hydrocarbons during exposure to EUV light. The oxides may also prevent the carbon or hydrocarbons from reacting with the free radicals in the metal capping layer  106 . 
       FIG.  2    illustrates a more detailed view of the multi-layered absorber layer  108  in the EUV mask  100 . The EUV mask  100  illustrated in  FIG.  2    may include the same layers and be fabricated the same way as the EUV mask  100  illustrated in  FIG.  1   . For example,  FIG.  2    illustrates the EUV mask  100  with the substrate  102  on the TaB layer  150 , the ML mirror layer  104 , the metal capping layer  106 , and the multi-layered absorber layer  108 . The dimensions of the ML mirror layer  104  and the metal capping layer  106  may be similar to the dimensions described above with respect to  FIG.  1   . 
     In one embodiment, the multi-layered absorber layer  108  may be an oxide based absorber layer that includes a first metal oxide layer  116 , a metal nitride layer  118 , and a second metal oxide layer  119 . The metal nitride layer  118  may be located between the first metal oxide layer  116  and the second metal oxide layer  119 . In one embodiment, the first metal oxide layer  116  and the second metal oxide layer  119  may be the same material. In one embodiment, the first metal oxide layer  116  and the second metal oxide layer  119  may be different materials. 
     In one embodiment, the metal nitride layer  118  may be thicker than the first metal oxide layer  116  and the second metal oxide layer  119 . In one embodiment, the first metal oxide layer  116  may have a thickness that is approximately the same as a thickness of the second metal oxide layer  119 . 
     Notably, the oxide layers are part of the absorber layer and not formed as a separate buffer layer as described by other EUV masks and methods. Furthermore, the multi-layered absorber layer  108  may include metal oxide layers that surround, on both sides or opposite sides, the metal nitride layer of the multi-layered absorber layer  108 . 
     In one embodiment, the first metal oxide layer  116  may have a thickness of approximately 0 nm-5.5 nm depending on the material of the first metal oxide layer  116 . In one embodiment, the first metal oxide layer  116  may comprise tantalum boro-oxide (TaBO). The TaBO may be deposited to have a thickness of approximately 0 nm-2 nm. 
     In one embodiment, the first metal oxide layer  116  may comprise tantalum pentoxide (Ta 2 O 5 ). The Ta 2 O 5  may be deposited to have a thickness of approximately 1 nm-2 nm. 
     In one embodiment, the first metal oxide layer  116  may comprise ruthenium oxide (RuO 2 ). The RuO 2  may be deposited to have a thickness of approximately 0 nm-5.5 nm. 
     In one embodiment, the first metal oxide layer  116  may comprise ruthenium niobium oxide (RuNbO). The RuNbO may have greater than 20 atom per cent of Nb. The RuNbO may be deposited to have a thickness of approximately 0 nm-5.5 nm. 
     In one embodiment, the first metal oxide layer  116  may comprise niobium pentoxide (Nb 2 O 5 ). The Nb 2 O 5  may be deposited to have a thickness of approximately 0 nm-5.5 nm. 
     In some embodiments, the metal capping layer  106  may be optional depending on the material. For example, the metal capping layer  106  may comprise RuO 2 , RuNbO, or Nb 2 O 5 . 
     In one embodiment, the metal nitride layer  118  may comprise tantalum boro-nitride (TaBN). The TaBN may be deposited to have a thickness between 60 nm-75 nm. In one embodiment, the TaBN may be deposited to have a thickness of approximately 66 nm-67 nm. 
     In one embodiment, when the first metal oxide layer  116  comprises TaBO, the TaBO may have a thickness of approximately 1 nm-2 nm. The thickness may allow a small amount of TaBO to remain on the metal capping layer  106  during etching of the multi-layered absorber layer  108 . For example, after the multi-layered absorber layer  108  is etched less than 1 nm of the TaBO may remain on the metal capping layer  106 . The thickness of the TaBO may reduce the over etch time of the metal nitride layer  118  by approximately 30 per cent. 
     In one embodiment, the second metal oxide layer  119  may comprise TaBO. The TaBO may be deposited to have a thickness of approximately 1 nm-5 nm. In one embodiment, the TaBO may be deposited to have a thickness of approximately 2 nm. 
     In one embodiment, the features  110  may be etched into the metal nitride layer  118  of the multi-layered absorber layer  108  via a photolithography process, followed by a main etch and an over etch process. For example, a hard mask may be deposited on the multi-layered absorber layer  108 . A photoresist may be spun onto the hard mask. An electron beam writer or laser beam writer may be used to define the features  110 . Portions of the photoresist that are not covered by the patterned mask may be exposed to a radiation light source or ultraviolet light source and developed. The pattern may be transferred into the hard mask and the features  110  may then be etched into the multi-layered absorber layer  108 . The hard mask, remaining photoresist, and patterned mask may be removed.  FIGS.  4 A- 4 J  illustrate further details of the above process. In one embodiment, the main etch and the over etch may be performed via an ion etch or a dry etch in the presence of various gases. 
     In one embodiment, the main etch may performed via an ion etch over 30-50 seconds (s) with a source power of approximately 100-500 Watts (W) and a bias power of approximately 5-30 W at a pressure of approximately 1-3 milliTorr (mTorr). The ion etch may be performed in the presence of chlorine gas (Cl 2 ) at 50-150 standard cubic centimeters per minute (sccm) and Helium (He) gas at 10-100 sccm. In one embodiment, the main etch may be performed via an ion etch in approximately 35 s with a source power of approximately 300 W and a bias power of approximately 15 W at a pressure of approximately 2 mTorr. The etch may be performed in the presence of Cl 2  gas at approximately 100 sccm and He gas at approximately 60 sccm. It should be noted that the values provided above are one example of values or value ranges that can be applied to etch the multi-layered absorber layer  108 . 
     In one embodiment, the over etch may be performed via an ion etch at approximately 30 per cent of the main etch time. Similar ranges for the source power, the bias power, the pressure, the flow of Cl 2  gas, and He gas may be used for the over etch. 
     In one embodiment, the features  110  may be etched into the metal nitride layer  118  of the multi-layered absorber layer  108  by pulsing the source power. In other words, the source power may be turned on and off in a pulsing fashion to etch the features  110  into the multi-layered absorber layer  108 . 
       FIG.  3    illustrates a flowchart of a method  300  of forming an EUV mask according to at least one embodiment of the present disclosure. The method  300  may be performed via one or more different tools within a fabrication plant under the control of controller or processor. 
     While the method  300  is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
     The method  300  begins at block  302 . At block  304 , the method  300  deposits a multi-layered absorber layer on a multi-layered mirror layer. The multi-layered absorber layer may include at least one oxide layer or oxides that may prevent carbon contamination that can adversely affect the critical dimensions of features formed in the multi-layered absorber layer. The multi-layered absorber layer may include a first metal oxide layer, a metal nitride layer, and a second metal oxide layer. 
     At block  306 , the method  300  deposits a hard mask layer on the multi-layered absorber layer. The hard mask layer may serve as an etch stop when a subsequent photoresist layer is removed. The hard mask layer may be a metal-oxy-nitride compound. In one embodiment, the hard mask layer may be a chromium oxynitride (CrON), chromium nitride (CrN), chromium carbon oxynitride (CrCON), and the like. The hard mask layer may be deposited to have a thickness of approximately 3-10 nm. 
     At block  308 , the method  300  deposits a photoresist on the hard mask layer. The photoresist may be spun onto the hard mask layer. The photoresist may be a radiation-sensitive layer that may be coated onto the hard mask layer. The photoresist may be deposited to have a thickness of approximately 100-1000 nm. 
     At block  310 , the method  300  performs an exposure, a post exposure bake, and develop of the photoresist. For example, an electron beam writer or a laser beam writer may be used to define a pattern on the photoresist. The photoresist may then be processed via a post exposure bake and develop. 
     After the photoresist is developed, critical dimensions of the features in the photoresist may be measured. After measurement, the features in the photoresist may be transferred to the multi-layered absorber layer using the following blocks of the method  300 . 
     At block  312 , the method  300  may perform a hard mask etch. For example, the features developed into the photoresist may define the portions of the hard mask layer that may be etched. The select portions of the hard mask layer may then be etched. In one embodiment, a dry etch, a wet etch, or a combination of both may be used to perform the etch. 
     At block  314 , the method  300  removes the photoresist and measures critical dimensions of the features etched in a portion of the multi-layered absorber layer. In one embodiment, any type of measurement or metrology tool may be used to measure the critical dimensions. For example, a critical dimension scanning electron microscope (CD-SEM) tool may be used. 
     At block  316 , the method  300  completes etching of the multi-layered absorber layer. The multi-layered absorber layer may be etched via an ion etch process or a dry etch process. Example process parameters for an ion etch process are provided above. In one embodiment, the ion etch may be performed by pulsing the power source on and off. 
     At block  318 , the method  300  strips the hard mask layer. The hard mask layer may be selectively etched off of the multi-layered absorber layer. For example, a wet etch process or a dry etch process may be used to remove the hard mask layer. The remaining structure after the hard mask layer is removed may be the EUV mask of the present disclosure with the multi-layered absorber layer. As noted above, the multi-layered absorber layer may include oxides that prevent carbon contamination. At block  320 , the method  300  ends. 
       FIGS.  4 A- 4 J  illustrate a plurality of partial cross-sectional views illustrating one embodiment of a method of forming the EUV mask at various stages of manufacture in accordance with at least one embodiment of the present disclosure. Referring to  FIG.  4 A , a substrate  102  is provided. The substrate  102  may be a low thermal expansion material (LTEM). Examples of LTEMs may include glass, a glass-ceramic material, or silicon. The substrate  102  may be deposited on the layer  150 . The layer  150  may be a TaB layer or a CrN layer. 
     In  FIG.  4 B , a multi-layered mirror layer  104  may be deposited or formed on the substrate  102 . In one embodiment, the multi-layered mirror layer  104  may be formed on the substrate  102  via an ion beam deposition (IBD) or a direct current (DC) magnetron sputtering. 
     The multi-layered mirror layer  104  may include alternating layers of a high index of refraction material  112  and a low index of refraction material  114 . In one embodiment, the high index of refraction material  112  may be Mo and the low index of refraction material  114  may be Si. 
     The multi-layered mirror layer  104  may have between 20-60 pairs of the high index of refraction material  112  and the low index of refraction material  114 . In one embodiment, the multi-layered mirror layer  104  may include 40 pairs of the high index of refraction material  112  and the low index of refraction material  114 . 
     In  FIG.  4 C , a metal capping layer  106  may be deposited on the multi-layered mirror layer  104 . In one embodiment, the metal capping layer  106  may be deposited via an ion beam sputtering process. In one embodiment, the metal capping layer  106  may be optional depending on the materials used for the multi-layered absorber layer  108  illustrated in  FIG.  4 D , and discussed below. 
     In one embodiment, the metal capping layer  106  may prevent oxidation of the high index of refraction material  112  (e.g., Mo) by exposure to the environment. The metal capping layer  106  may comprise a material that has a slower etching rate than the multi-layered absorber layer  108 , illustrated in  FIG.  4 D , and discussed below. As a result, the metal capping layer  106  may protect the multi-layered mirror layer  104  when the multi-layered absorber layer  108  is patterned via an etch process. 
     In one embodiment, the metal capping layer  106  may comprise ruthenium (Ru), ruthenium oxide (RuO 2 ), or ruthenium niobium oxide (RuNbO), niobium pentoxide (Nb 2 O 5 ), and the like. The metal capping layer  106  may be deposited with a thickness of approximately 2.5-5.5 nm. In one embodiment, the metal capping layer  106  may be deposited with a thickness of approximately 3.5 nm. 
     In  FIG.  4 D , the multi-layered absorber layer  108  is formed over the multi-layered mirror layer  104 . In some embodiments where the metal capping layer  106  is deposited, the multi-layered absorber layer  108  may be formed on the metal capping layer  106 . 
     In one embodiment, the multi-layered absorber layer  108  may include a first metal oxide layer  116 , a metal nitride layer  118 , and a second metal oxide layer  119 . The layers of the multi-layered absorber layer  108  may be deposited or formed via a chemical vapor deposition (CVD) or an ion beam sputtering process one layer at a time. 
     In one embodiment, the first metal oxide layer  116  may comprise tantalum boro-oxide (TaBO), tantalum pentoxide (Ta 2 O 5 ), ruthenium oxide (RuO 2 ), ruthenium niobium oxide (RuNbO), or niobium pentoxide (Nb 2 O 5 ). When the first metal oxide layer  116  comprises TaBO or Ta 2 O 5  the metal capping layer  106  may be deposited. When the first metal oxide layer  116  comprises RuO 2 , RuNbO, or Nb 2 O 5  the metal capping layer  106  may be removed or the process associated with  FIG.  4 C  may be skipped. 
     In one embodiment, the metal nitride layer  118  may comprise tantalum boro-nitride (TaBN). In one embodiment, the second metal oxide layer  119  may comprise TaBO. 
     As discussed above, the oxide in the first metal oxide layer  116  and the second metal oxide layer  119  may act as insulators that prevent carbon contamination in the edges and center of the features of the multi-layered absorber layer  108 . The carbon contamination may adversely affect the critical dimensions of the features that are formed in the multi-layered absorber layer  108 . 
     In addition, when the first metal oxide layer  116  is TaBO, the TaBO may be deposited to have a desired thickness that may reduce the over etch time. For example, the desired thickness may allow a small amount of the TaBO to remain on the metal capping layer  106 . For example, the TaBO may be deposited to have a thickness of approximately 1-2 nm such that approximately less than 1 nm of the TaBO remains on the metal capping layer  106  after the multi-layered absorber layer  108  is etched. 
     In  FIG.  4 E , a hard mask layer  120  may be deposited onto the multi-layer absorber layer  108 . In one embodiment, the hard mask layer  120  may be deposited via a CVD process. The hard mask layer  120  may serve as an etch stop when a subsequent photoresist layer is removed. The hard mask layer  120  may be a metal-oxy-nitride compound. In one embodiment, the hard mask layer  120  may be a chromium oxynitride (CrON) that may be deposited to have a thickness of approximately 6 nm. 
     In  FIG.  4 F , photoresist  122  may be deposited onto the hard mask layer  120 . The photoresist  122  may be coated onto the hard mask layer  120 , exposed, baked, and developed with a pattern of features that may eventually be transferred to the multi-layered absorber layer  108 . 
     In  FIG.  4 G , the photoresist  122  may be etched to create the features  124   1 - 124   n  (hereinafter also referred to individually as features  124  or collectively as features  124 ) that were patterned into the photoresist  122  in  FIG.  4 F . The features  124  may correspond to the features  110  etched into the multi-layered absorber layer  108  as illustrated in  FIG.  4 I , and discussed in further details below. 
     In  FIG.  4 H , the etching process may continue to etch the features  124  through the hard mask layer  120  and into the multi-layered absorber layer  108 . In one example, the etching process in  FIG.  4 H  may use a reactive ion etch or a dry etch. In one embodiment, a reactive ion etch is used with the parameters described above. 
     In one embodiment, after the features  124  are partially etched into the multi-layered absorber layer  108 , the critical dimensions of the features  124  may be measured. If the measurement of the critical dimensions of the features  124  meets the desired critical dimensions, then the features  124  may be etched through the multi-layered absorber layer  108 . 
     In  FIG.  4 I , the features  110   1  to  110   n  may be formed through the multi-layered absorber layer  108  leaving a portion of the first metal oxide layer  116  on the metal capping layer  106 .  FIG.  4 I  illustrates the hard mask layer  120  without the photoresist  122  that has been removed. The photoresist  122  may be etched away as the features  110  are etched into the multi-layered absorber layer  108 . In one embodiment, the features  110  may be etched into the multi-layered absorber layer  108  by pulsing the power source during a reactive ion etch process. 
     In one embodiment, the features  110  may be used to define structures in a semiconductor device. For example, the EUV mask  100  may be used to create structures in accordance with the pattern of features  110  etched into the multi-layered absorber layer  108 . An example of a lithography system that can use the EUV mask  100  and the process to create structures is illustrated in  FIG.  5    and discussed in further details below. 
     In  FIG.  4 J , the hard mask layer  120  may be stripped away resulting in the final EUV mask  100  that is formed in accordance with at least one embodiment of the present disclosure. The hard mask layer  120  may be selectively etched off of the multi-layered absorber layer  108 . For example, a wet etch process or a dry etch process may be used to remove the hard mask layer  120 . 
       FIG.  5    illustrates a schematic view of a lithography system  10  that describes a process of how the EUV mask  100  may be used in such a lithography system. The lithography system  10  may also be generically referred to as a scanner that is operable to perform lithography exposure processes. In the present embodiment, the lithography system  10  is an extreme ultraviolet (EUV) lithography system designed to expose a resist layer by EUV light (or EUV radiation). The resist layer is a material sensitive to the EUV light. The EUV lithography system  10  employs a radiation source  12  to generate EUV light  40 , such as EUV light having a wavelength ranging between about 1 nm and about 100 nm. In one particular example, the EUV light  40  has a wavelength centered at about 13.5 nm. Accordingly, the radiation source  12  is also referred to as EUV radiation source  12 . The EUV radiation source  12  may utilize a mechanism of laser-produced plasma (LPP) to generate the EUV radiation, which will be further described later. 
     The lithography system  10  also employs an illuminator  14 . In some embodiments, the illuminator  14  includes various reflective optics such as a single mirror or a mirror system having multiple mirrors in order to direct the light  40  from the radiation source  12  onto a mask stage  16 , particularly to the EUV mask  100  secured on the mask stage  16 . 
     The lithography system  10  also includes the mask stage  16  configured to secure the EUV mask  100 . In some embodiments, the mask stage  16  includes an electrostatic chuck (e-chuck) to secure the EUV mask  100 . In the present disclosure, the terms mask, photomask, and reticle are used interchangeably. In the present embodiment, the lithography system  10  is a EUV lithography system. The EUV mask  100  may be fabricated as described above. 
     The lithography system  10  also includes a projection optics module (or projection optics box (POB))  20  for imaging the pattern of the EUV mask  100  onto a semiconductor substrate  22  secured on a substrate stage (or wafer stage)  24  of the lithography system  10 . The POB  20  includes reflective optics in the present embodiment. The light  40  directed from the EUV mask  100 , carrying the image of the pattern defined on the EUV mask  100 , is collected by the POB  20 . The illuminator  14  and the POB  20  may be collectively referred to as an optical module of the lithography system  10 . 
     In the present embodiment, the semiconductor substrate  22  is a semiconductor wafer, such as a silicon wafer or other type of wafer to be patterned. The semiconductor substrate  22  is coated with a resist layer sensitive to the EUV light  40  in the present embodiment. Various components including those described above are integrated together and are operable to perform lithography exposing processes. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 
     Therefore, the present disclosure relates to an EUV mask and a method for forming the same. In some embodiments, the present disclosure relates to an EUV mask that prevents carbon contamination. The EUV mask comprises a multi-layered mirror that is formed on the substrate. A metal capping layer is formed on the multi-layered mirror layer. A multi-layered absorber layer is formed over the multi-layered mirror layer. The multi-layered absorber layer comprises features that are etched into the multi-layered absorber layer to define structures on a semiconductor device. 
     In other embodiments, the present disclosure relates to an EUV mask that includes an oxide containing absorber layer to prevent carbon contamination. The EUV mask comprises a multi-layered mirror that is formed on the substrate. A metal capping layer is formed on the multi-layered mirror layer. An oxide containing absorber layer is formed over the multi-layered mirror layer. The oxide containing absorber layer comprises features that are etched into the oxide containing absorber layer to define structures on a semiconductor device. 
     In yet other embodiments, the present disclosure relates to a method for forming the EUV mask that prevents carbon contamination. The method comprises depositing a multi-layered absorber layer on a multi-layered mirror layer. In some embodiments, a metal capping layer may be deposited between the multi-layered absorber layer and the multi-layered mirror layer. A hard mask layer is deposited on the multi-layered absorber layer. Photoresist is coated on the hard mask layer. An exposure, post exposure bake, and develop of the photoresist is performed. The hard mask layer is etched with the features developed in the photoresist. The photoresist is removed and the multi-layered absorber layer is etched to form features in the multi-layered absorber layer to define structures on a semiconductor device. Then the hard mask layer is removed. 
     In some embodiments, an extreme ultra-violet (EUV) mask includes a substrate, a multi-layered mirror layer, a capping layer, a first tantalum-containing oxide layer, a tantalum-containing nitride layer, and a second tantalum-containing oxide layer. The multi-layered mirror layer is over the substrate. The capping layer is over the multi-layered mirror layer. The first tantalum-containing oxide layer is over the capping layer. The tantalum-containing nitride layer is over the first tantalum-containing oxide layer. The second tantalum-containing oxide layer is over the tantalum-containing nitride layer. In some embodiments, the tantalum-containing nitride layer and the second tantalum-containing oxide layer have a same chemical element besides tantalum. In some embodiments, the tantalum-containing nitride layer comprises boron. In some embodiments, the second tantalum-containing oxide layer comprises boron. In some embodiments, the capping layer comprises ruthenium. In some embodiments, the second tantalum-containing oxide layer has a same thickness as the first tantalum-containing oxide layer. In some embodiments, the second tantalum-containing oxide layer has a thinner thickness than the tantalum-containing nitride layer. In some embodiments, the EUV mask further includes a tantalum boron layer, the substrate sandwiched between the tantalum boron layer and the multi-layered mirror layer. 
     In some embodiments, an extreme ultra-violet (EUV) mask includes a substrate, a multi-layered mirror layer, and a multi-layered absorber layer. The multi-layered mirror layer is over the substrate. The multi-layered absorber layer is over the multi-layered mirror layer and includes a first metal oxide layer, a metal nitride layer, and a second metal oxide layer. The metal nitride layer is over the first metal oxide layer. A first metal element of the first metal oxide layer is different than a second metal element of the metal nitride layer. The second metal oxide layer is over the metal nitride layer and has the second metal element of the metal nitride layer. In some embodiments, the first metal element comprises ruthenium. In some embodiments, the second metal element comprises tantalum. In some embodiments, the metal nitride layer is free of the second metal element. In some embodiments, the second metal oxide layer is free of the first metal element. In some embodiments, the second metal oxide layer has a thinner thickness than the first metal oxide layer. 
     In some embodiments, an extreme ultra-violet (EUV) mask includes a substrate, a multi-layered mirror layer, a metal oxide layer, a metal nitride layer, and a tantalum boron-oxide layer. The multi-layered mirror layer is over the substrate. The metal oxide layer is over the multi-layered mirror layer. The metal nitride layer is over the metal oxide layer and has a thicker thickness than the metal oxide layer. The tantalum boron-oxide layer is over the metal nitride layer and has a thinner thickness than the metal nitride layer. In some embodiments, the metal oxide layer is made of a same material as the tantalum boron-oxide layer. In some embodiments, the metal oxide layer is made of a different material than the tantalum boron-oxide layer. In some embodiments, the metal nitride layer is made of tantalum boron-nitride. In some embodiments, the EUV mask further includes a ruthenium oxide layer sandwiched between the multi-layered mirror layer and the metal oxide layer. In some embodiments, the EUV mask further includes a chromium nitride layer, the substrate sandwiched between the chromium nitride layer and the multi-layered mirror layer. 
     In some embodiments, a method includes forming a multi-layered reflective layer over a substrate; depositing a metal capping layer over the multi-layered reflective layer; depositing a first metal oxide layer over the metal capping layer; depositing a metal nitride layer over the first metal oxide layer; depositing a second metal oxide layer over the metal nitride layer; forming a plurality of features on the second metal oxide layer and the metal nitride layer. In some embodiments, the first and second metal oxide layers and the metal nitride layer have a same metal element. In some embodiments, the metal element comprises tantalum. In some embodiments, the first metal oxide layer comprises boron. In some embodiments, the metal nitride layer comprises boron. In some embodiments, the second metal oxide layer comprises boron. In some embodiments, the first metal oxide layer is in contact with the metal capping layer. In some embodiments, the metal capping layer comprises ruthenium. In some embodiments, the first metal oxide layer has a thinner thickness than the metal nitride layer. In some embodiments, the first metal oxide layer has a same thickness as the second metal oxide layer. 
     In some embodiments, a method includes forming a multi-layered reflective layer over the substrate; depositing a capping layer over the multi-layered reflective layer; forming a multi-layered absorber layer over the capping layer. The multi-layered absorber layer includes a tantalum boron-oxide layer over the capping layer, and a metal nitride layer over the tantalum boron-oxide layer. In some embodiments, the metal nitride layer is made of a tantalum-containing material. In some embodiments, the metal nitride layer comprises boron. In some embodiments, the first tantalum boron-oxide layer is in contact with the metal nitride layer. In some embodiments, the method further includes depositing a second tantalum boron-oxide layer over the metal nitride layer. 
     In some embodiments, an extreme ultra-violet mask includes a substrate, a multi-layered reflective layer, a metal oxide layer, a tantalum-containing nitride layer, and a tantalum-containing oxide layer. The multi-layered reflective layer is over the substrate. The metal oxide layer is over the multi-layered reflective layer. The tantalum-containing nitride layer is over the metal oxide layer. The tantalum-containing oxide layer is over the tantalum-containing nitride layer. In some embodiments, the metal oxide layer have a chemical element besides tantalum. In some embodiments, the metal oxide layer comprises ruthenium oxide. In some embodiments, the tantalum-containing oxide layer comprises boron. In some embodiments, the metal oxide layer is boron-free. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.