Patent Publication Number: US-9431845-B2

Title: Switching charger, the control circuit and the control method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority to and the benefit of Chinese Patent Application No. 201210504857.8, filed Nov. 30, 2012, which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present invention relates to electronic circuits, and more particularly but not exclusively to switching chargers and the method thereof. 
     BACKGROUND 
     A charger should be capable of providing a constant current to a load. For switching chargers, the constant current is achieved by limiting the bounds of a current flowing through an inductor of the switching charger.  FIG. 1  schematically shows a prior art switching charger. As shown in  FIG. 1 , a control circuit  100  detects a voltage across a resistor Rsen coupled in series with an inductor L to generate a current sense signal. Based on the current sense signal, the control circuit  100  generates a control signal G 1  to control the power switches M 1  and M 2 , so as to regulate a current supplied to the load be a constant value. However, the resistor Rsen introduces power consumption. Meanwhile, it is difficult to integrate the resistor Rsen with the control circuit  100 . Thus, two extra pins are needed to be coupled to the resistor Rsen. 
     SUMMARY 
     It is an object of the present invention to provide an improved switching charger without extra pins and external resistor for current sensing. 
     In accomplishing the above objective, there has been provided, in accordance with an embodiment of the present invention, a switching charger, comprising: a control circuit configured to provide a control signal; a power stage having a high-side power switch and a low-side power switch coupled in series, the high-side power switch and the low-side power switch turned ON and OFF alternatively by the control signal; an inductor having a first terminal coupled to the connection of the high-side power switch and the low-side power switch, and a second terminal coupled to a load; and an output capacitor having a first terminal coupled to the second terminal of the inductor, and a second terminal coupled to a reference ground; a current sense circuit integrated to the control circuit, wherein the current sense circuit has a first input terminal coupled to the high-side power switch, a second input terminal coupled to the low-side power switch, a first output terminal configured to generate a high-side current sense signal indicating the current flowing through the high-side power switch, and a second output terminal configured to generate a low-side current sense signal indicating the current flowing through the low-side power switch. 
     Furthermore, there has been provided, in accordance with an embodiment of the present invention, a control circuit for a switching charger, wherein the switching charger has a high-side power switch and a low-side power switch, the control circuit comprising: a feedback amplifier having a first input terminal configured to receive a feedback signal indicating the charging voltage, a second input terminal configured to receive a feedback reference signal, and an output terminal configured to generate a amplified feedback signal based on the feedback signal and the feedback reference signal; a select circuit having a first input terminal configured to receive a current reference signal, a second input terminal coupled to the feedback amplifier to receive the amplified feedback signal, and an output terminal configured to generate a current control signal based on the current reference signal and the amplified feedback signal, wherein the current control signal is the lower value of the current reference signal and the amplified feedback signal; a hysteretic control circuit having a first input terminal coupled to the output terminal of the select circuit to receive the current control signal, a second input terminal configured to receive the input voltage, a third input terminal configured to receive the charging voltage, a fourth input terminal coupled to the output terminal of the control circuit to receive the control signal, and a fifth input terminal configured to receive a frequency control signal having pulses at moment when the power stage is turned ON, wherein based on the current control signal, the input voltage, the charging voltage, the control signal and the frequency control signal, the hysteretic control circuit provides a lower limit signal via a first output terminal, and a higher limit signal via a second output terminal; a current sense circuit having a first input terminal coupled to the high-side power switch, a second input terminal coupled to the low-side power switch, a first output terminal configured to generate a high-side current sense signal indicating a current flowing through the high-side power switch, and a second output terminal configured to generate a low-side current sense signal indicating a current flowing through the low-side power switch; a comparison circuit having a first input terminal coupled to the first output terminal of the hysteretic control circuit to receive the lower limit signal, a second input terminal coupled to the second output terminal of the hysteretic control circuit to receive the higher limit signal, a third input terminal coupled to the first output terminal to receive the high-side current sense signal, a fourth input terminal coupled to the second output terminal to receive the low-side current sense signal, and based on the lower limit signal, the higher limit signal, the high-side current sense signal and the low-side current sense signal, the comparison circuit provides a set signal via a first output terminal, and a reset signal via a second output terminal; and a logic circuit having a set terminal coupled to the comparison circuit to receive the set signal, a reset terminal coupled to the comparison circuit to receive the reset signal, and an output terminal configured to generate the control signal based on the set signal and the reset signal. 
     In addition, there has been provided, in accordance with an embodiment of the present invention, a control method for controlling a switching charger, wherein the switching charger has a high-side power switch and a low-side power switch, the control method comprising: generating a higher limit signal and a lower limit signal; sensing a current flowing through the high-side power switch to generate a high-side current sense signal; sensing a current flowing through the low-side power switch to generate a low-side current sense signal; and turning OFF the high-side power switch when the high-side current sense signal is higher than the higher limit signal, and turning ON the high-side power switch when the low-side current sense signal is lower than the lower limit signal. 
     The presented switching charger and the method thereof eliminates the need of two extra pins and an external resistor, thus the application of switching charger is simplified, and the cost of the whole system is saved. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically shows a prior art switching charger. 
         FIG. 2  schematically shows a switching charger in accordance with an embodiment of the present invention. 
         FIG. 3  shows the waveforms of the signals of the switching charger in  FIG. 2 . 
         FIG. 4  schematically shows a circuit configuration of the control circuit  200  in accordance with an embodiment of the present invention. 
         FIG. 5  schematically shows a circuit configuration of the hysteretic signal generator  401  in accordance with an embodiment of the present invention. 
         FIG. 6  shows the waveforms of the signals of the hysteretic signal generator  401  in  FIG. 5 . 
         FIG. 7  schematically shows a circuit configuration of the operational circuit  402  in accordance with an embodiment of the present invention. 
         FIG. 8  schematically shows a circuit configuration of the high-side current sense circuit  801  for sensing the current flowing through the high-side power switch M 1  in accordance with an embodiment of the present invention. 
         FIG. 9  schematically shows a circuit configuration of the low-side current sense circuit  901  for sensing the current flowing through the low-side power switch M 2  in accordance with an embodiment of the present invention. 
         FIG. 10  shows a flowchart  1000  of a control method for a switching charger having a high-side power switch and a low-side power switch in accordance with an embodiment of the present invention. 
     
    
    
     The use of the similar reference label in different drawings indicates the same of like components. 
     DETAILED DESCRIPTION 
     Embodiments of switching chargers are described in detail herein. In the following description, some specific details, such as example circuits for these circuit components, are included to provide a thorough understanding of embodiments of the invention. One skilled in relevant art will recognize, however, that the invention can be practiced without one or more specific details, or with other methods, components, materials, etc. 
     The following embodiments and aspects are illustrated in conjunction with circuits and methods that are meant to be exemplary and illustrative. In various embodiments, the above problem has been reduced or eliminated, while other embodiments are directed to other improvements. 
       FIG. 2  schematically shows a switching charger in accordance with an embodiment of the present invention. In the example of  FIG. 2 , the switching charger receives an input voltage Vin, and then provides a charging current and a charging voltage Vbatt to a battery based thereupon. The switching charger comprises: a control circuit  200  configured to provide a control signal G 1 ; a power stage  210  having an input terminal, a ground terminal, a control terminal and an output terminal SW, the input terminal being configured to receive the input voltage Vin, the ground terminal being coupled to a reference ground, and the control terminal being coupled to the control circuit  200  to receive the control signal G 1 , wherein the power stage  210  having a high-side power switch M 1  and a low-side power switch M 2  coupled in series, and the high-side power switch M 1  and the low-side power switch are turned ON and OFF alternatively by the control signal G 1 ; an inductor L having a first terminal coupled to the output terminal SW of the power stage  210 , and a second terminal coupled to a load; and an output capacitor Cout having a first terminal coupled to the second terminal of the inductor L, and a second terminal coupled to the reference ground; wherein the control circuit  200  senses a current flowing through the inductor L 1  by detecting a current flowing through the power stage  210 . 
     In the example of  FIG. 2 , the power stage  210  is defined as being turned ON when the high-side power switch M 1  is ON and the low-side power switch M 2  is OFF. The power stage  210  is defined as being turned OFF when the high-side power switch M 1  is OFF and the low-side power switch M 2  is ON. In one embodiment, the power switches M 1  and M 2  comprise controllable devices, e.g., MOSFET (Metal Oxide Semiconductor Field Effect Transistor), Bipolar Junction Transistor and so on. In one embodiment, the high-side power switch M 1  is controlled by the control signal G 1 , and the power stage  210  further comprises an inverter  209  configured to invert the control signal G 1  to a signal G 2  to control the low-side power switch M 2 . In one embodiment, the high-side power switch M 1  comprises the controllable devices, e.g., MOSFET, Bipolar Junction Transistor and so on, while the low-side power switch M 2  comprises a diode. 
     In one embodiment, the first terminal of the inductor L is coupled to the input voltage Vin when the power stage  210  is ON, and is coupled to the reference ground when the power stage  210  is OFF. 
     As shown in  FIG. 2 , the control circuit  200  comprises: a feedback amplifier  201  having a first input terminal configured to receive a feedback signal Vfb indicating the charging voltage Vbatt, a second input terminal configured to receive a feedback reference signal Vref 1 , and an output terminal configured to generate an amplified feedback signal Vcom based on the feedback signal Vfb and the feedback reference signal Vref 1 ; a select circuit  202  having a first input terminal configured to receive a current reference signal Vic, a second input terminal coupled to the feedback amplifier  201  to receive the amplified feedback signal Vcom, and an output terminal configured to generate a current control signal Vmid based on the current reference signal Vic and the amplified feedback signal Vcom; a hysteretic control circuit  203  having a first input terminal coupled to the output terminal of the select circuit  202  to receive the current control signal Vmid, a second input terminal configured to receive the input voltage Vin, a third input terminal configured to receive the charging voltage Vbatt, a fourth input terminal coupled to the output terminal of the control circuit  200  to receive the control signal G 1 , and a fifth input terminal configured to receive a frequency control signal FRE having pulses at moment when the power stage  210  is turned ON, and based on the current control signal Vmid, the input voltage Vin, the charging voltage Vbatt, the control signal G 1 , and the frequency control signal FRE, the hysteretic control circuit  203  provides a lower limit signal Vhys_L via a first output terminal, and a higher limit signal Vhys_H via a second output terminal; a current sense circuit  205  having a first input terminal coupled to the high-side power switch M 1 , a second input terminal coupled to the low-side power switch M 2 , a first output terminal configured to generate a high-side current sense signal Vihs indicating a current flowing through the high-side power switch M 1 , and a second output terminal configured to generate a low-side current sense signal Vils indicating a current flowing through the low-side power switch M 2 ; a comparison circuit  206  having a first input terminal coupled to the first output terminal of the hysteretic control circuit  203  to receive the lower limit signal Vhys_L, a second input terminal coupled to the second output terminal of the hysteretic control circuit  203  to receive the higher limit signal Vhys_H, a third input terminal coupled to the first output terminal of the current sense circuit  205  to receive the high-side current sense signal Vihs, a fourth input terminal coupled to the second output terminal of the current sense circuit  205  to receive the low-side current sense signal Vils, and based on the lower limit signal Vhys_L, the higher limit signal Vhys_H, the high-side current sense signal Vihs and the low-side current sense signal Vils, the comparison circuit  206  provides a set signal Vs via a first output terminal, and a reset signal Vr via a second output terminal; and a logic circuit  207  having a set terminal coupled to the comparison circuit  206  to receive the set signal Vs, a reset terminal coupled to the comparison circuit  206  to receive the reset signal Vr, and an output terminal configured to generate the control signal G 1  based on the set signal Vs and the reset signal Vr. 
     In one embodiment, the logic circuit  207  comprises a RS flip-flop having a set terminal coupled to the comparison circuit  206  to receive the set signal Vs, a reset terminal coupled to the comparison circuit  206  to receive the reset signal Vr, and an output terminal configured to generate the control signal G 1  based on the set signal Vs and the reset signal Vr. 
     Persons of ordinary skill in the art should know that the current flowing through the high-side power switch M 1  is equal to a current flowing through the inductor L when the high-side power switch M 1  is ON, and the current flowing through the low-side power switch M 2  is equal to the current flowing through the inductor L when the low-side power switch M 2  is ON. Because the high-side power switch M 1  and the lower-side power switch M 2  are turned ON alternatively, so the current flowing through the inductor L is known by detecting the currents flowing through the high-side power switch M 1  and the low-side power switch M 2 . 
       FIG. 3  shows the waveforms of the signals of the switching charger in  FIG. 2 . The operation of the switching charger in  FIG. 2  is described with reference to  FIGS. 2 and 3 . As shown in  FIG. 3 , the operation of the switching charger comprises a constant current mode and a constant voltage mode. When the switching charger works under constant current mode, the switching charger provides a constant current to the load, i.e. the battery. When the switching charger works under constant voltage mode, the switching charger provides a constant voltage to the load, i.e., the battery. 
     When the switching charger works under constant current mode, the charging voltage Vbatt is lower than a preset value, i.e., the feedback signal Vfb is lower than the feedback reference signal Vref 1 , causing the saturation of the feedback amplifier  201 . So the output signal Vcom of the feedback amplifier  201  is logical high, and is higher than the current reference signal Vic (the current reference signal Vic has a preset constant value). The select circuit  202  chooses the lower value of the amplified feedback signal Vcom and the current reference signal Vic as the current control signal Vmid. So the current reference signal Vic is chosen to be the current control signal Vmid by the select circuit  202  under constant current mode. The hysteretic control circuit  103  generates the lower limit signal Vhys_L and the higher limit signal Vhys_H based on the input voltage Vin, the charging voltage Vbatt, the control signal G 1 , the frequency control signal FRE and the current control signal Vmid. The comparison circuit  206  compares the high-side current sense signal Vihs with the higher limit signal Vhys_H, and compares the low-side current sense signal Vils with the lower limit signal Vhys_L. During when the high-side power switch M 1  is turned OFF, and the low-side power switch M 2  is turned ON, the comparison circuit  206  generates the set signal Vs to set the logic circuit  207  so as to turn ON the high-side power switch M 1  and to turn OFF the low-side power switch M 2  if the low-side current sense signal Vils decreases to the lower limit signal Vhys_L. After that, the inductor L receives the input voltage Vin, and the current flowing through the inductor L increases. As a result, the high-side current sense signal Vihs increases and the low-side current sense signal Vils becomes zero. The comparison circuit  206  generates the reset signal Vr to reset the logic circuit  207  so as to turn OFF the high-side power switch M 1  and to turn ON the low-side power switch M 2  when the high-side current sense signal Vihs increases to the higher limit signal Vhys_H. After that, the inductor L is coupled to the reference ground, and the current flowing through the inductor L decreases. As a result, the low-side current sense signal Vils decreases and the high-side current sense signal Vihs becomes zero. The value of the current control signal Vmid is the average value of the higher limit signal Vhys_H and the lower limit signal Vhys_L, i.e., the value of the current control signal Vmid indicates the average current flowing through the inductor L, and the charging current provided to the load. Thus, the charging current is constant as long as the current control signal Vmid is constant. 
     When the battery is charged by a constant current under constant current mode, the charging voltage Vbatt increases. When the feedback signal Vfb representing the charging voltage Vbatt increases to the feedback reference signal Vref 1 , the switching charger works under constant voltage mode. The amplified feedback signal Vcom decreases as the feedback signal Vfb increases. When the amplified feedback signal Vcom decreases to the current reference signal Vic, the amplified feedback signal Vcom is chosen by the select circuit  202  as the current control signal Vmid. As described before, the current control signal Vmid indicates the charging current provided to the load. So when the amplified feedback signal Vcom decreases as the feedback signal Vfb increases, the charging current decreases too. As a result, the increase of the charging voltage Vbatt slows down. After the decrease of the charging current and the increase of the charging voltage Vbatt reach equilibrium, the charging voltage Vbatt is constant and has a value corresponding to the feedback reference signal Vref 1  because the feedback signal Vfb is clamped to the feedback reference signal Vref 1  by the feedback amplifier  201 . 
     In one embodiment, the power stage  210  comprises a drive circuit configured to increase the drive capability of the control signals G 1  and G 2 . 
       FIG. 4  schematically shows a circuit configuration of the control circuit  200  in accordance with an embodiment of the present invention. 
     In one embodiment, the select circuit  202  comprises: a diode D 1  having a cathode terminal coupled to the feedback amplifier  201  to receive the amplified feedback signal Vcom, and an anode terminal; a resistor R 3  having a first terminal coupled to the anode terminal of the diode D 1  and a second terminal configured to receive a current reference signal Vic; wherein: the diode D 1  is OFF when the current reference signal Vic is lower than or equal to the amplified feedback signal Vcom, and current reference signal Vic is chosen to be the current control signal Vmid; the diode D 1  is ON when the current reference signal Vic is higher than the amplified feedback signal Vcom, and the amplified feedback signal is chosen to be the current control signal Vmid. 
     In one embodiment, the hysteretic control circuit  203  comprises: a hysteretic signal generator  401  having a first input terminal configured to receive the input voltage Vin, a second input terminal configured to receive the charging voltage Vbatt, a third input terminal coupled to the output terminal of the control circuit  200  to receive the control signal G 1 , a fourth input terminal configured to receive the frequency control signal FRE, and an output terminal configured to generate a hysteretic signal Vhys based on the input voltage Vin, the charging voltage Vbatt, the control signal G 1  and the frequency control signal FRE; and an operational circuit  402  having a first input terminal coupled to the output terminal of the hysteretic signal generator  401  to receive the hysteretic signal Vhys, a second input terminal coupled to the select circuit  202  to receive the current control signal Vmid, wherein based on the hysteretic signal Vhys and the current control signal Vmid, the operational circuit  402  provides the lower limit signal Vhys_L via a first output terminal, and provides the higher limit signal Vhys_H via a second output terminal. 
     In one embodiment, the frequency control signal FRE comprises the set signal Vs. The set signal has a pulse to set the RS flip-flop at every switching cycle. And the control signal G 1  turns ON the high-side power switch M 1  when the RS flip flop is set. The frequency control signal FRE may comprises any signal that has a pulse at the moment the high-side power switch M 1  is turned ON. 
       FIG. 5  schematically shows a circuit configuration of the hysteretic signal generator  401  in accordance with an embodiment of the present invention. In the example of  FIG. 5 , the hysteretic signal generator  401  comprises: a COT (Constant ON Time) signal generator  501  having a first input terminal configured to receive the input voltage Vin, a second input terminal configured to receive the set signal Vs, a third input terminal configured to receive the charging voltage Vbatt, and an output terminal configured to generate a COT signal Ton_ref based on the input voltage Vin, the set signal Vs and the charging voltage Vbatt; a charge and discharge circuit  502  having a first input terminal coupled to the COT signal generator  501  to receive the COT signal Ton_ref, a second input terminal coupled to the output terminal of the control circuit  200  to receive the control signal G 1 , and an output terminal configured to provide a charge/discharge current based on the COT signal Ton_ref and the control signal G 1 ; and a hysteretic capacitor C 1  having a first terminal coupled to the output terminal of the charge and discharge circuit  502  to receive the charge/discharge current, and a second terminal coupled to the reference ground, wherein the hysteretic capacitor C 1  provides the hysteretic signal Vhys on the first terminal. In one embodiment, the charge and discharge circuit  502  further comprises an inverter  503  configured to invert the COT signal Ton_ref. 
     In one embodiment, the COT signal generator  501  comprises: a first controlled current source  11  having an input terminal configured to receive an internal power supply Vcc, a control terminal configured to receive the input voltage Vin, and an output terminal configured to provide a charge current Ic; a reference capacitor C 2  having a first terminal coupled to the first controlled current source  11  to receive the charge current Ic, and a second terminal coupled to the reference ground, wherein the reference capacitor C 2  provides a sawtooth signal Vc 2  on the first terminal; a frequency switch Ms having a first terminal coupled to the first terminal of the reference capacitor C 2 , a second terminal coupled to the second terminal of the reference capacitor C 2 , and a control terminal configured to receive the set signal Vs, wherein the frequency switch Ms is turned ON by the pulse of the set signal Vs; a controlled voltage source V 1  having a first terminal configured to provide a COT reference signal Vref 2  relating to the charging voltage Vbatt, a second terminal coupled to the reference ground, and a control terminal configured to receive the charging voltage Vbatt; and a COT comparator  5011  having a first input terminal (inverting input terminal) coupled to the reference capacitor C 2  to receive the sawtooth signal Vc 2 , a second input terminal (non-inverting input terminal) coupled to the controlled voltage source V 1  to receive the COT reference signal Vref 2 , and an output terminal configured to generate the COT signal Ton_ref based on the sawtooth signal Vc 2  and the COT reference signal Vref 2 . 
     In one embodiment, the charge current Ic provided by the first controlled current source  11  is directly proportional to the input voltage Vin:
 
 Ic=K 1× V in  (1)
 
     Wherein K 1  is constant. 
     In one embodiment, a relationship between the COT reference signal Vref 2  provided by the controlled current source V 1  and the charging voltage Vbatt is:
 
 V ref2= K 2× V batt  (2)
 
     Wherein K 2  is constant. 
     In a switching cycle, the frequency switch Ms is turned ON at the pulse of the set signal Vs. Then the reference capacitor C 2  is discharged and the sawtooth signal Vc 2  decreases to zero. As a result, the COT signal Ton_ref is logical high. When the frequency switch Ms is turned OFF at the end of the pulse of the set signal Vs, the first controlled current source  11  charges the reference capacitor C 2 , and the sawtooth signal Vc 2  increases. When the sawtooth signal Vc 2  reaches the COT reference signal Vref 2 , the COT comparator  5011  flips, and the COT signal Ton_ref becomes logical low. The sawtooth signal Vc 2  continues to increase until the frequency switch Ms is turned ON. Then the reference capacitor C 2  is discharged, and the COT signal Ton_ref becomes logical high again. The operation repeats, and the COT signal has a waveform shown in  FIG. 6 . In one embodiment, the logical high period of the COT signal Ton_ref is defined as ON time, while the logical low period of the COT signal Ton_ref is defined as OFF time. The ON time TON of the COT signal Ton_ref is constant when the charge current Ic, the reference capacitor C 2  and the COT reference signal Vref 2  are set. The ON time TON is also referred as constant ON time. 
     The ON time TON of the COT signal Ton_ref could be written as: 
     
       
         
           
             
               
                 
                   TON 
                   = 
                   
                     
                       
                         K 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                       
                         K 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     × 
                     C 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                     × 
                     
                       Vbatt 
                       Vin 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     In one embodiment, the charge and discharge circuit  502  comprises: a second current source I 2  having an input terminal and an output terminal; a first switch Q 1  having a first terminal coupled to the output terminal of the second current source I 2 , a second terminal coupled to the reference ground, and a control terminal coupled to the COT signal generator  501  to receive the COT signal Ton_ref; a second switch Q 2  having a first terminal coupled to the first terminal of the hysteretic capacitor C 1 , a second terminal coupled to the input terminal of the second current source I 2 , and a control terminal coupled to the output terminal of the control circuit  200  to receive the control signal G 1 ; a third switch D 3  having a first terminal coupled to the output terminal of the second current source I 2 , and a second terminal coupled to the first terminal of the hysteretic capacitor C 1 ; and a fourth switch D 4  having a first terminal coupled to the reference ground, and a second terminal coupled to the input terminal of the second current source I 2 ; wherein when the ON time of the control signal G 1 , i.e., the ON time of the high-side power switch M 1 , is shorter than the ON time TON of the COT signal Ton_ref, the second current source I 2  charges the hysteretic capacitor C 1 ; when the ON time of the control signal G 1  is longer than the ON time TON of the COT signal Ton_ref, the second current source I 2  discharges the hysteretic capacitor C 1 ; and when the ON time of the control signal G 1  is equal to the ON time TON of the COT signal Ton_ref, the charges in the hysteretic capacitor C 1  remains the same. 
     In one embodiment, the first switch Q 1  may be turned ON by a logical low signal while the second switch Q 2  may be turned ON by a logical high signal. In some embodiments, the first switch Q 1  may be turned ON by a logical high signal and the second switch Q 2  may be turned ON by a logical high signal too. Thus, the inverter  503  may be omitted in some embodiments. 
       FIG. 6  shows the waveforms of the signals of the hysteretic signal generator  401  in  FIG. 5 . The operation of the hysteretic signal generator is described with reference to  FIGS. 5 and 6 . 
     During subinterval t 1 , the control signal G 1  and the COT signal Ton_ref are both logical high. As a result, the first switch Q 1  is turned OFF and the second switch Q 2  is turned ON. Then the current provided by the second current source I 2  flows through the circle consisting of the second current source I 2 , the third switch D 3  and the second switch Q 2 . At this time, the hysteretic signal Vhys remains the same. During subinterval t 2 , the control signal G 1  is logical high and the COT signal Ton_ref is logical low. As a result, the first switch Q 1  and the second switch Q 2  are both turned ON. Then the current provided by the second current source I 2  flows through the circle consisting of the second current source I 2 , the second switch Q 2  and the first switch Q 1 . During this time, the hysteretic capacitor C 1  is discharged, and the hysteretic signal Vhys decreases. During subinterval t 3 , the control signal G 1  and the COT signal Ton_ref are both logical low. As a result, the first switch Q 1  is turned ON, and the second switch Q 2  is turned OFF. Then the current provided by the second current source I 2  flows through the circle consisting of the second current source I 2 , the first switch Q 1  and the fourth switch D 4 . During this time, the hysteretic signal Vhys remains the same too. As can be seen from  FIGS. 5 and 6 , the hysteretic capacitor C 1  is discharged and the hysteretic signal Vhys decreases only when the ON time of the control signal G 1  is longer than the ON time of the COT signal Ton_ref. 
     Based on the similar theory, the first switch Q 1  and the second switch Q 2  are turned OFF when the control signal G 1  is logical low and the COT signal Ton_ref is logical high. During this time, the current provided by the second current source I 2  flows through a circle consisting of the second current source I 2 , the third switch D 3  and the fourth switch D 4 . Meanwhile, the hysteretic capacitor C 1  is charged and the hysteretic signal Vhys increases. 
     In a conclusion, the hysteretic signal Vhys decreases when the ON time of the control signal G 1  is longer than the ON time of the COT signal Ton_ref. Because the hysteretic signal Vhys represents the hysteretic window of an inductor current flowing through the inductor L, and the rising slope of the inductor current is fixed, the rising time will decrease when the hysteretic window of the inductor current decreases. The hysteretic signal Vhys increases when the ON time of the control signal G 1  is shorter than the ON time of the COT signal Ton_ref. As a result, the hysteretic window of an inductor current flowing through the inductor L increases in the next switching cycle, then the rising time will increase. The rising time is equivalent to the ON time of the control signal G 1 . It could be concluded that the ON time of the control signal G 1  is regulated to be equal to the ON time of the COT signal Ton_ref. 
     The solution of Equation (3) for the switching frequency fsw yields: 
     
       
         
           
             
               
                 
                   fsw 
                   = 
                   
                     
                       D 
                       TON 
                     
                     = 
                     
                       
                         
                           Vbatt 
                           / 
                           Vin 
                         
                         
                           
                             
                               K 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             
                               K 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                           × 
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                           × 
                           
                             Vbatt 
                             Vin 
                           
                         
                       
                       = 
                       
                         
                           K 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         
                           K 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                           × 
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Wherein D is the duty cycle of the switching charger. As can be seen from the Equation (4) that the switching frequency fsw is fixed and is decided by the capacitance of the reference capacitor C 2 , the constants K 1  and the constant K 2 . 
       FIG. 7  schematically shows the operational circuit  402  in accordance with an embodiment of the present invention. As shown in  FIG. 7 , the operational circuit  402  comprises: a second controlled current source Ihys having a first terminal configured to receive the internal power supply Vcc, a control terminal coupled to the hysteretic signal generator  401  to receive the hysteretic signal Vhys, and an output terminal configured to provided a current K 3 ×Vhys that is proportional to the hysteretic signal Vhys; a first resistor R 4  having a first terminal and a second terminal, the first terminal configured to provide the higher limit signal Vhys_H; a second resistor R 5  having a first terminal coupled to the second terminal of the first resistor R 4 , and a second terminal configured to provide the lower limit signal Vhys_L; a third resistor R 6  having a first terminal coupled to the second terminal of the second resistor R 5 , and a second terminal coupled to the reference ground; and a clamp circuit  701  having a first terminal coupled to the select circuit  202  to receive the current control signal Vmid, and a second terminal coupled to the connection of the first resistor R 4  and the second resistor R 5 , wherein the voltage at the connection of the first resistor R 4  and the second resistor R 5  is clamped to the current control signal Vmid. 
     In one embodiment, the internal power supply Vcc is equal to the input voltage Vin. In one embodiment, the internal power supply Vcc is generated by a bandgap circuit known to persons of ordinary skill in the art. 
     The operation of the clamp circuit  701  is well known by persons of ordinary skill in the art, and is not described here for brevity. 
     As can be seen from  FIG. 7 , the higher limit signal Vhys_H and the lower limit signal Vhys_L may be written as: 
     
       
         
           
             
               
                 
                   Vhys_H 
                   = 
                   
                     
                       Vmid 
                       + 
                       
                         K 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         3 
                         × 
                         Vhys 
                         × 
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         4 
                       
                     
                     = 
                     
                       Vmid 
                       + 
                       
                         
                           1 
                           2 
                         
                         × 
                         Vhys 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   Vhys_L 
                   = 
                   
                     
                       Vmid 
                       - 
                       
                         K 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         3 
                         × 
                         Vhys 
                         × 
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         5 
                       
                     
                     = 
                     
                       Vmid 
                       - 
                       
                         
                           1 
                           2 
                         
                         × 
                         Vhys 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     Wherein the resistance of the resistor R 4  is equal to the resistance of the resistor R 5 , and the product of the resistance of resistor R 4  and the constant K 3  is 
     
       
         
           
             
               1 
               2 
             
             . 
           
         
       
     
     Persons of ordinary skill in the art should know that any circuit may generate the higher limit signal Vhys_H and the lower limit signal Vhys_L as expressed by the Equations (5) and (6) may be used without detracting from the merits of the present invention. 
     The operational circuit  402  and the select circuit  202  are simple and common. Persons of ordinary skill in the art may deduce other circuits for replacement after reading the present invention. Also, the operational circuit  402  and the select circuit  202  may be automatically generated by hardware description language, for example, VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) or Verilog HDL, by person of ordinary skill in the art. 
       FIG. 8  schematically shows a high-side current sense circuit  801  for sensing the current flowing through the high-side power switch M 1  in accordance with an embodiment of the present invention. In  FIG. 8 , the current sense circuit  801  comprises: a first detect switch Ms 1  having a first terminal, a second terminal and a control terminal, the first terminal configured to receive the input voltage Vin, the control terminal coupled to the control terminal of the high-side power switch M 1 ; a second detect switch Ms 2  having a first terminal, a second terminal and a control terminal, the first terminal coupled to the second terminal of the first detect switch Ms 1 , the control terminal coupled to the control terminal of the high-side power switch M 1 ; an error amplifier  802  having a first input terminal, a second input terminal and an output terminal, the first input terminal coupled to the second terminal of the first detect switch Ms 1 , the second input terminal coupled to the second terminal of the second detect switch Ms 2 ; a third detect switch Ms 3  having a first terminal coupled to the second terminal of the first detect switch Ms 1 , a control terminal coupled to the output terminal of the error amplifier  802  and a second terminal configured to provide a high-side sensing current Isen 1  indicating the current flowing through the high-side power switch M 1 ; and a resistor Rs 1 , having a first terminal coupled to the second terminal of the third detect switch Ms 3  to receive the high-side sensing current Isen 1 , and a second terminal coupled to the reference ground, wherein the high-side sensing current Isen 1  flows through the resistor Rs 1  to generate a high-side current sense signal Vihs. 
     In one embodiment, the first input terminal of the error amplifier  802  is a non-inverting input terminal, and the second input terminal of the error amplifier  802  is an inverting input terminal. Assuming the voltage at the non-inverting input terminal is VP 1 , and the voltage at the inverting input terminal is VN 1 . As can be deviated from the circuit in  FIG. 8 , VP 1 =Vin−Isen 1 *RdsONs 1 , and VN 1 =Vin−Ipow 1 *RdsON 1 . Because the voltages at two input terminals of an error amplifier is equal, i.e., VP 1 =VN 1 , Isen 1 =Ipow 1 *(RdsON 1 /RdsONs 1 ). So the high-side sensing current Isen 1  is directly proportional to current Ipow 1  flowing through the high-side power switch M 1 , with a proportionality RdsON 1 /RdsONs 1 . Wherein RdsON 1  is the ON resistance of the high-side power switch M 1  and RdsONs 1  is the ON resistance of the first detect switch Ms 1 . Thus the high-side current sense signal Vihs could be written as Vihs=Isen 1 *Rs 1 . 
       FIG. 9  schematically shows a low-side current sense circuit  901  for sensing the current flowing through the low-side power switch M 2  in accordance with an embodiment of the present invention. As shown in  FIG. 9 , the low-side current sense circuit  901  comprises: a fourth detect switch Ms 4  having a first terminal, a second terminal and a control terminal, the first terminal coupled to the reference ground, and the control terminal coupled to the control terminal of the low-side power switch M 2 ; a fifth detect switch Ms 5  having a first terminal, a second terminal and a control terminal, the first terminal coupled to the second terminal of the low-side power switch M 2 , and the control terminal coupled to the control terminal of the low-side power switch M 2 ; an error amplifier  902  having a first input terminal, a second input terminal and an output terminal, the first input terminal coupled to the second terminal of the fourth detect switch Ms 4 , and the second input terminal coupled to the second terminal of the fifth detect switch Ms 5 ; a sixth detect switch Ms 6  having a first terminal coupled to the second terminal of the fifth detect switch Ms 5 , a control terminal coupled to the output terminal of the error amplifier  902 , and a second terminal configured to provide a low-side sensing current Isen 2  indicating the current flowing through the low-side power switch M 2 ; a current mirror circuit  903  having a first terminal coupled to the second terminal of the sixth detect switch Ms 6  to receive the low-side sensing current Isen 2 , and a second terminal configured to provide a mirror current proportional to the low-side sensing current Isen 2 ; a resistor Rs 2  having a first terminal coupled to the second terminal of the current mirror circuit  903  to receive the mirror current, and a second terminal coupled to the reference ground, wherein the mirror current flows through the resistor Rs 2  to generate the low-side current sense signal Vils. 
     In one embodiment, the first input terminal of the error amplifier  902  is a non-inverting input terminal, and the second input terminal of the error amplifier  902  is an inverting input terminal. Assuming the voltage at the non-inverting input terminal is VP 2 , and the voltage at the inverting input terminal is VN 2 . As can be deviated from the circuit in  FIG. 9 , VP 2 =Vsw+Ipow 2 *RdsON 2 , and VN 2 =Vsw+Isen 2 *RdsONs 5 . Because the voltages at two input terminals of an error amplifier is equal, i.e., VP 2 =VN 2 , Isen 2 =Ipow 2 *(RdsON 2 /RdsONs 5 ). So the low-side sensing current Isen 2  is directly proportional to current Ipow 2  flowing through the low-side power switch M 2 , with a proportionality RdsON 2 /RdsONs 5 . Wherein RdsON 2  is the ON resistance of the low-side power switch M 2  and RdsONs 5  is the ON resistance of the fifth detect switch Ms 5 . 
     In one embodiment, the current mirror circuit  903  comprises a mirror switch Mr 1  and a mirror switch Mr 2  respectively having a first terminal, a second terminal and a control terminal. The first terminal of the mirror switch Mr 1  and the first terminal of the mirror switch Mr 2  are coupled together to receive the input voltage Vin, and the control terminal of the mirror switch Mr 1  and the control terminal of the mirror switch Mr 2  are coupled together. In one embodiment, the mirror switch Mr 1  has the same size with the mirror switch Mr 2 , and the mirror current is equal to the low-side sensing current Isen 2 . So the low-side current sense signal Vils could be written as: Vils=Isen 2 *Rs 2 . Persons of ordinary skill in the art should know that the size of the mirror switch Mr 1  and the size of the mirror switch Mr 2  may be different, and any circuit applies the low-side sensing current Isen 2  to a resistor may be used without detracting from the merits of the present invention. 
     In one embodiment, other circuits sense the current flowing through the high-side power switch M 1  and the low-side power switch may be used without detracting from the merits of the present invention, e.g., a current mirror circuit. 
     By adopting the high-side current sense circuit  801  and the low-side current sense circuit  901  to sense the current flowing through the high-side power switch M 1  and the low-side power switch M 2 , the resistor Rsen coupled in series with the inductor L is omitted. Because the high-side current sense circuit  801  and the low-side current sense circuit  901  may be integrated into the control circuit  200 , the discrete resistor Rsen may hardly integrated is saved, and also the pins coupled to the resistor Rsen is saved too. Thus the cost of the circuit is reduced. 
       FIG. 10  shows a flowchart  1000  of a control method for a switching charger having a high-side power switch and a low-side power switch in accordance with an embodiment of the present invention. The method comprises: step  1001 , generating a higher limit signal and a lower limit signal; step  1002 , sensing a current flowing through the high-side power switch to generate a high-side current sense signal; step  1003 , sensing a current flowing through the low-side power switch to generate a low-side current sense signal; and step  1004 , turning OFF the high-side power switch when the high-side current sense signal is higher than the higher limit signal, and turning ON the high-side power switch when the low-side current sense signal is lower than the lower limit signal. 
     In one embodiment, the step  1001  comprises: amplifying the error between a feedback signal indicating an output voltage of the switching charger and a feedback reference signal to generate an amplified feedback signal; selecting the smaller value of the amplified feedback signal and a current reference signal to be a current control signal; generating a hysteretic window signal; and generating the higher limit signal and the lower limit signal based on the current control signal and the hysteretic window signal. 
     In one embodiment, the step  1001  comprises: generating a COT signal having an ON time period directly proportional to the output voltage of the switching charger and inversely proportional to the input voltage of the switching charger; generating the hysteretic window signal based on the comparison of the ON time of the COT signal and the ON time of the high-side power switch; wherein: the hysteretic window signal decreases when the ON time of the high-side power switch is longer than the ON time of the COT signal; the hysteretic window signal increases when the ON time of the high-side power switch is shorter than the ON time of the COT signal; and the hysteretic window signal remains the same when the ON time of the high-side power switch is equal to the ON time of the COT signal. 
     In one embodiment, the higher limit signal has a value equal to the sum of the current control signal and half of the hysteretic window signal, and the lower limit signal has a value equal to the difference of the current control signal and the half of the hysteretic window signal. 
     In one embodiment, the higher limit signal has a value equal to the current control signal, and the lower limit signal has a value equal to the difference of the current control signal and the hysteretic window signal. 
     In one embodiment, the higher limit signal has a value equal to the sum of the current control signal and the hysteretic window signal, and the lower limit signal has a value equal to the current control signal. 
     It is to be understood in these letters patent that the meaning of “A” is coupled to “B” is that either A and B are connected to each other as described below, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element that in turn is connected to B. 
     This written description uses examples to disclose the invention, including the best mode, and also to enable a person skilled in the art to make and use the invention. The patentable scope of the invention may include other examples that occur to those skilled in the art.