Patent Publication Number: US-7908444-B2

Title: Status holding circuit and status holding method

Description:
INCORPORATION BY REFERENCE 
     This patent application claims a priority on convention based on Japanese Patent Application No. 2009-037595. The disclosure thereof is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a technique of holding data related to a circuit operation. 
     2. Description of Related Art 
     In a one-chip microcomputer and a system LSI mounted with a peripheral function macro, a technique of holding data indicating events such as an operation status and an unordinary status (error) of the function macro is used. Flags indicating such data are collected at one location or registers of as smaller number as possible. When such an event has occurred, these flags are set to “1”. 
     When a plurality of unordinary statuses (errors) have occurred at a same address, in order to recognize the details of unordinary statuses and adequately find a solution, it is desirable that an order is indicated in which the flags are set to “1”. 
     As a related art, an error detecting circuit described in Japanese Patent Publication (JP-A-Showa 63-73435) is known.  FIG. 1  shows a configuration of this error detecting circuit. The error detecting circuit includes SR latches holding an error occurrence state, a counter (timer) generating an error occurrence order; and registers (latches) receiving a count value when an error has occurred First, in response to a reset signal, error flip-flops  101 -i (i=1 to n), a counter  102 , and register  103 -i are initially set to “0”. If an error signal  111 - 1  is generated, the register  103 - 1  holds “0” while the registers  103 - 2  to  103 -n are incremented to the value of “1”. Next, if an error signal  111 - 2  is generated, the register  103 - 1  holds “0”, the register  103 - 2  holds “1”, and registers 3-3 to 3-n are set to “2”. By repeating such an operation, the error occurrence order can be found even when a plurality of errors have occurred. 
     However, the above Japanese Patent Publication does not describe a method of reading the error occurrence order in detail. In the circuit described in the above Japanese Patent Publication, a CPU needs to read all the registers in order to completely recognize the error occurrence order. When a plurality of errors have occurred at a same time, a plurality of registers must hold a same value. Thus, an increase in the number of errors requires a long time for judgment on whether or not a system unordinary status is present and a recovery operation. For example, where a total number of errors is n, in order for the CPU to find a first error and a second error, a read command needs to be issued n times. Therefore, when a CPU clock frequency is relatively lower than a clock frequency of a peripheral macro, the above problem may become more remarkable. 
     SUMMARY OF THE INVENTION 
     In an aspect of the present invention, a status holding circuit includes: status holding sections of M stages (M is an integer equal to or more than 2) connected in series. Each of the status holding sections includes: N latches (N is an integer equal to or more than 2) provided for N input signals to N input terminals, respectively; and a switch circuit configured to set a data to a j th  latch of the N latches in an i th  status holding section of the M-stage status holding sections when a status signal is supplied to a j th  input terminal of the N input terminals at an i th  timing. 
     In another aspect of the present invention, a method of holding status signals in a status holding circuit comprising M-stage status holding sections (M is an integer equal to or more than 2) connected in series. Each of the status holding sections includes N latches (N is an integer equal to or more than 2) provided for N input signals to N input terminals, respectively; and a switch circuit. The method is achieved by setting an i th  latch of the N latches in a j th -stage status holding section when a first status signal is supplied to an input terminal of the i th  latch in the j th -stage status holding section at a k th  timing (k is an integer equal to or smaller than M); and by negating the N latches in the j th -stage status holding section by the switch circuit in the j th -stage status holding section in response to the setting, so as not to receive any status signal. 
     According to the present invention, data of a j-kind of state signal generated at i-th timing is stored at a j-th latch of an i th  status holding section, which makes it easy to find out the kind and generation timing of the state signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  shows a configuration of an error detecting circuit in a related art; 
         FIG. 2  shows a configuration of a status holding circuit according to the present invention; 
         FIGS. 3 to 5  are diagrams illustrating an operation of the status holding circuit according to the present invention; 
         FIG. 6  is a flow chart showing an operation of reading error data in the present invention; and 
         FIG. 7  is a diagram comparing data read-out procedures between the related art and the present embodiment. 
     
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Hereinafter, a status holding circuit according to the present invention will be described with reference to the attached drawings. 
       FIG. 2  shows a configuration of a status holding circuit in the present embodiment. By registers of M stages each including N latch circuits, this status holding circuit holds N kinds of status signals indicating a device state, i.e., first to M th  (where N≧M) status signals in occurrence order. the present embodiment, the state signal is described as an error signal indicating a kind of error. The status holding circuit includes logic gates that hold contents of all errors upon occurrence of the errors, and thereby the error occurrence order can be recognized through a sequentially read operation from the registers at fixed addresses. 
     The status holding circuit has N-bit registers (status holding sections) R 1  to RM of the M stages (where M is an integer equal to or larger than 2). Each of the registers R 1  to RM is identified by an address assigned individually. The M-stage registers are connected in series. The status holding sections R 1  to RM have a same circuit configuration. The status holding section R 1  of a first stage will be now described. The status holding section R 1  includes N latches DLR 11  to DLR 1 N disposed in parallel. Each of the latches DLR 11  to DLR 1 N is a D-type latch with a reset terminal. The n latches DLR 11  to DLR 1 N are respectively connected to signal lines I 1  to IN to transfer N kinds of error signals (status signals). 
     The signal lines with a same configuration are respectively connected to the N latches DLR 11  to DLR 1 N. The first latch DLR 11  will be described in detail. The reset terminal of the latch DLR 11  is connected to a reset signal line Reset. A data input terminal D of the latch DLR 11  is connected to the signal line I 1 . A gate terminal GT of the latch DLR 11  is connected to an output terminal of a logical summation circuit OR 1  to be described later. 
     N logical product circuits A 11  to A 1 N are provided for the N latches DLR 11  to DLR 1 N in the same register R 1 , respectively. An output terminal Q of the latch DLR 11  is connected to a first input terminal of the logic product circuit A 11  corresponding to the latch DLR 11 . A signal to the first input terminal is inverted and received by the circuit A 11 . A second input terminal of the logic product circuit A 11  is connected to the corresponding signal line I 1  included in the N kinds of signal lines I 1  to IN. A third input terminal of the logic product circuit A 11  is connected to the output terminal of a logical summation circuit OR 1 . An output terminal of the logic product circuit A 11  is connected to a data input terminal D of a latch DLR 21  which is included in the N latches DLR 21  to DLR 2 N of the register R 2  at the next stage and which corresponds to this logical product circuit A 11 . 
     Respective output terminals of the N latches DLR 11  to DLR 1 N in the same register R 1  are connected to the input terminals of the same logical summation circuit OR 1 . That is, the logical summation circuit OR 1  is an N-bit logical summation gate. The output terminal of the logical summation circuit OR 1  is connected to the respective third input terminals of the N logical product circuits A 11  to A 1 N in the register R 1  at the same stage. The output terminal of the logical summation circuit OR 1  is logically inverted and connected to the respective gate input terminals GT of the N latches DLR 11  to DLR 1 N in the register R 1  at the same stage. The N logical product circuits and one logical summation circuit included in each of the M-stage registers R 1  to RM function as a switch circuit for holding the error signals supplied from the signal lines I 1  to IN together with their input timing. 
     The registers R 2  to RM at the second to M th  stages have a same configuration as that of the register R 1  at the first stage. They differ from the register R 1  in the following points. In the registers R 2  to RM at the second to M th  stages, data input terminals D of the latches DLR 21  to DLRMN and the second input terminals of logical product circuits A 21  to AMN are connected to output terminals of the logical product circuits A 11  to AMN at the previous stage, instead of the signal lines I 1  to  1 N. Output terminals of latches DLRM 1  to DLRMN of the register RM at the M th  stage are respectively connected to output signal lines OUT 1  to OUTN of the status holding circuit  1 . 
     Next, referring to  FIGS. 3 ,  4  and  5  as an example (where M=2 and N=5), an operation of the status holding circuit  1  according to the present embodiment will be described. In this example, for five kinds of errors, a second error signal can be held together with their generation timing. 
     Next,  FIG. 3  shows a case where the second kind of error has occurred at the first timing, that is, a case where the error signal is supplied to the second signal line I 2 . In initial setting, a rest signal is supplied to the input terminals R of all the latches, whereby values of flags inside all the latches DLR 11  to DLR 25  are set to “0”. Furthermore, the gate terminals GT of all the latches DLR 11  to DLR 25  are set to “1”, that is, into a gate-open state. 
     An error signal with the value of “1” is supplied to the signal line I 2  at the first timing to indicate that an error (for example, high potential) has occurred. The error signal is supplied to an input terminal D of the second latch DLR 12  of the register R 1  at the first stage. Only the flag of the latch DLR 12  is set to “1”. An output signal with the value of “1” is outputted from the output terminal of the latch DLR  12 . 
     The logical summation circuit OR 1  realizes a negate function of negating the N latches DLR 11  to DLR 15  included in the register R 1 . More specifically, the output signal of the latch DLR 12  is supplied to the input terminal of the logical summation circuit OR 1 . As a result, the output signal with the value of “1” is outputted from the output terminal of the logical summation circuit OR 1 . A value “0” obtained by inverting this output signal is supplied to the respective gate input terminals GT of the latches DLR 11  to DLR 15  of the register R 1  at the first stage. As a result, the gates are closed, and a state of the register R 1  at the first stage is held with no change for an error signal supplied at the second timing or thereafter. That is, the N latches DLR 11  to DLR 15  is disabled to receive another error signal. Through this operation, only the error signal generated at the first timing is recorded in the register R 1  at the first stage. 
     Through the above operation, a transfer function is realized of transferring an error signal to one of the M-stage registers R 1  to RM in accordance with input timing. Specifically, in response to the error signal at first timing, the logical value of the output signal of the logical summation circuit OR 1  at the register R 1  at the first stage changes from “0” to “1”. As a result, the logical values of input signals of the third input terminals of the logical product circuits A 11  to A 15  change from “0” to “1”. Through this switching, an error signal supplied at or before the first timing is not transferred to the second stage and the subsequent. An error signal supplied after the first timing is transferred to the second stage. Typically, when an error signal has been supplied to the status holding circuit  1  at i th  timing, after this timing, the register Ri at an i th  stage transfers the error signal to the register Ri+1 at the (i+1) th  stage. As a result, when the error signal has been supplied to a j th  input terminal included in N kinds of input terminals at the i th  timing, i.e. the signal line Ij, the j th  latch DLRij included in the register Ri at the i th  stage is set. 
       FIG. 4  shows the operation of the status holding circuit  1  when an error signal with the value of “1” is generated on the first signal line Il at the second timing, following a state of  FIG. 3 . The error signal is supplied to the input terminal D of the first latch DLR 11  of the register R 1  at the first stage. Since the gate terminal GT of the latch DLR 11  has been set to “0”, i.e. an “OFF state”, the value of “0” of the flag of the latch DLR 11  does not change. The error signal is further supplied to the second input terminal of the logical product circuit A 11  corresponding to the first signal line I 1  in the register R 1  at the first stage. At this point, the value of “1” obtained by inverting the value of “0” of the output signal from the output terminal Q of the latch DLR 11  is supplied to the first input terminal of the logical product circuit A 11 . Furthermore, the signal with the value of “1” outputted from the output terminal of the logical summation circuit OR 1  is supplied to the third input terminal of the logical product circuit A 11 , as described above. Thus, the logical product circuit A 11  outputs the error signal with the value of “1” to the corresponding latch DLR 21  of the register R 2  at the second stage. 
     The error signal with the value of “1” is supplied to the data input terminal D of the latch DLR 21  at the second register R 2 . The value of the flag of the latch DLR 21  is set to “1”. The output signal with the value of “1” is outputted from the output terminal Q of the latch DLR 21 . This output signal is supplied to the input terminal of the logical summation circuit OR 2 . The logical summation circuit OR 2  outputs an output signal with the value of “1” from its output terminal. This output signal is logically inverted and supplied to gate input terminals GT of all the latches DIR 21  to DIR 25  of the register R 2  at the second stage. As a result, even if any error signal has been supplied at the second timing or thereafter, data of the register R 2  at the second stage is held with no change. 
       FIG. 5  shows the operation of the status holding circuit  1  when an error signal with the value of “1” is generated at the first signal line I 1  and the fifth signal line  15  at the second timing, following the state of  FIG. 3 . The example of  FIG. 5  differs from the example of  FIG. 4  in a point that the error signal with the value of “1” is generated on the fifth signal line  15 . In this case, the signal with the value of “1” is supplied to the second input terminal of the fifth logical product circuit A 15  of the register R 1  at the first stage. Since this error signal is supplied after the first timing, the logical product circuit A 15  outputs the supplied signal with the value of “1” to the latch DLR 25  of the register R 2  at the second stage. The flag of the latch DLR 25  is set to “1”. The output terminal Q of the latch DLR 25  outputs the output signal with the value of “1”. This output signal is supplied to the logical summation circuit OR 2 . The logical summation circuit OR 2  outputs the output signal with the value of “1”. This output signal is logically inverted and supplied to the gate input terminals GT of all the latches DLR 21  to DLR 25  of the register R 2  at the second stage. As a result, the values of the flags of the register R 2  at the second stage are held at the second timing and thereafter. In this manner, data of two or more errors generated at the same timing are written into the register at a same address. 
       FIG. 6  shows a flow chart showing an operation of reading error data held in the status holding circuit  1  shown in  FIGS. 3 to 5 . A CPU operates based on a program, which has been loaded from a recording medium, describing a procedure shown in this flow chart, thereby executing an unordinary process for error signals. First, the CPU specifies an address identifying the register R 1  (Error status reg.  1 ), and reads data held in the register R 1  (step S 1 ). This data indicates a kind of error occurrence at the first timing. In the example of  FIG. 5 , it is interpreted that the second kind of error has occurred at the first timing. Next, the CPU specifies an address identifying the register R 2  (Error status reg.  2 ), and reads data held in the register R 2  (step S 2 ). This data indicates kinds of error occurring at the second timing. In the example of  FIG. 5 , it is interpreted that the first and fifth kinds of errors have occurred at the second timing. Next, the CPU judges whether or not the error occurrence order is normal (step S 3 ). If the CPU judges that the error occurrence order is normal (Yes in step S 3 ), the CPU executes an ordinary system recovery process (step S 4 ). If the error occurrence order is judged to be not normal order (No in step S 3 ), the CPU execute a process such as alarm display for an unordinary operation (step S 5 ) and then stops the system. 
     In the present embodiment, every time an error has occurred (a flag is set), statuses of all error flags are sequentially stored into the registers. Thus, compared to the related art, the number of times of read by the CPU to check occurrence order can be reduced. In the circuit of  FIG. 1 , the error occurrence order could not be judged until the last register  103 -n is read. On the other hand, in the present embodiment, the error occurrence order can be recognized through two times of read operation. As a result, the judging operation of whether or not system is in the normal state and the recovery operation can be performed earlier. 
     In the present embodiment, the events and their occurrence timings can be recognized by reading specific registers by the CPU or an external unit. Since there is no limit except for a limit of N≧M, on a relation between the number N of kinds of status signals or error signals to be sampled and the number M of times of occurrence of the signals, M and N can be freely set in accordance with system configuration of a one-chip microcomputer or a SOC (System on Chip) and a bit width and analysis depth of the CPU. 
       FIG. 7  is a diagram showing a comparing result in a data read procedure between the related art technique and the present embodiment. In the conventional technique, after the registers  103 - 1  to  103 -n would have been sequentially read, an error occurrence at first time and an error occurrence at second time would be sequentially recognized. Then, error judgment would be performed, and the normal recovery processing would be performed. A time period from error occurrence to normal recovery is indicated as T 1 . Thus, in order to recognize error occurrence order, the time period T 1  is required to read all the registers and search for the error occurrence order. This time period becomes great obstacle for a short-time recovery from an error in a peripheral macro. This becomes more remarkable with an increase in the number of errors. Specifically, this becomes more remarkable in a case where a CPU clock frequency fcpu is relatively lower than a peripheral macro clock frequency fmacro, since the recovery time T 1  is extended. 
     On the other hand, in the present embodiment, the first register R 1  is read, and the second register R 2  is read. Next, error judgment is performed, and the normal recovery process is executed. A time period from error occurrence to normal recovery is indicated as T 2 . In the present embodiment, even when the number N of errors to be sampled increases, if N is up to a bit width of the CPU, the number of times of read operation by the CPU is only equivalent to the number M of error occurrence timings. Thus, in a case where a CPU clock frequency fcpu is lower than a peripheral macro clock frequency fmacro, the judgment operation on whether or not system is in the unordinary state and the recovery operation can be performed in a shorter time in the present embodiment. 
     Although the present invention has been described above in connection with several embodiments thereof, it would be apparent to those skilled in the art that those embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.