Patent Publication Number: US-8969771-B2

Title: Imaging system and imaging device

Description:
TECHNICAL FIELD 
     The present invention relates to an imaging system and an imaging device. 
     BACKGROUND ART 
     An example of the A/D (Analog to Digital) converting method used in recent imaging devices is a method called column A/D which installs an A/D converter for each pixel column of an image sensor. An example of A/D conversion used in column A/D is an integrating type A/D conversion. Japanese Patent Laid-Open No. 2005-348325 discloses in particular a multi-step scheme which performs A/D conversion in two or more steps divisionally for higher and lower bits. 
     Japanese Patent Laid-Open No. 2005-348325 discloses an imaging device including sensing elements arranged in a two-dimensional array, and A/D converters provided in a one-to-one-correspondence with the columns of sensing elements. In this imaging device, each A/D converter holds, in a storage unit, an electrical signal corresponding to the analog signals of sensing elements as an initial value. The storage unit is charged or discharged by a first fixed signal input after that. Time is discretely measured from the start of charge or discharge until the electrical signal in the storage unit reaches a reference signal. The storage unit is discharged or charged by a second fixed signal input after that. The time until the electrical signal in the storage unit which has exceeded the reference signal, after the measurement reaches the reference signal, is discretely measured as a digital value. More specifically, the output from an integrator is set as a pixel signal voltage, and integration then starts as a negative slope. At a certain time, the output of the integrator falls below the reference voltage, and A/D conversion of N higher bits ends. Integration is temporarily interrupted at the end. However, since switches are controlled in discrete time, the difference between the integrator output and the reference voltage is not 0, and a potential difference (residual signal) exists between them. In the next step, the first potential difference is integrated again, thereby converting M lower bits. At a certain time later, the output of the integrator intersects the reference voltage of the comparator, and A/D conversion of M lower bits ends. 
     However, in the above-described prior art, if the residual signal that is the difference between the reference voltage and the integrator output after higher conversion contains an offset caused by leakage, delay, or the like, determination may be unable to finish until the end of the lower count period, or conversely, the output from the comparator may be inverted before lower conversion count. In this case, the conversion linearity becomes more poor. 
     SUMMARY OF INVENTION 
     The present invention provides a technique advantageous for adjusting the linearity of a voltage level input to an A/D converting circuit and a digital signal output from the A/D converting circuit. 
     The first aspect of the present invention provides an imaging system including a plurality of pixels arranged in a matrix each of which outputs a pixel signal corresponding to incident light, and a plurality of A/D converting circuits provided in correspondence with columns of the plurality of pixels, the A/D converting circuit comprising: a holding unit which holds the pixel signal as a voltage level; a comparator which compares the voltage level held by the holding unit with a reference level; a circuit capable of changing the voltage level held by the holding unit so as to approach the reference level at one of a first rate and a second rate lower than the first rate, wherein the voltage level of the pixel signal held by the holding unit is changed by the circuit at the first rate, higher bits are determined in accordance with inversion of a relationship between the reference level and the voltage level held by the holding unit, after that, the voltage level held by the holding unit is changed at the second rate, and lower bits are determined in accordance with inversion of the relationship between the reference level and the voltage level held by the holding unit; and an adjusting unit which adjusts the voltage level held by the holding unit during a period until the voltage level held by the holding unit is changed at the second rate after determination of the higher bits so that the lower bits and the voltage level held by the holding unit hold a linear relationship throughout a possible range of the voltage level held by the holding unit after determination of the higher bits. 
     Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram showing an imaging system to which the present invention is applied; 
         FIG. 2  is a circuit diagram for explaining the first embodiment; 
         FIG. 3  is a timing chart showing the driving timing and operation waveforms in  FIG. 2 ; 
         FIGS. 4A to 4C  are timing charts for explaining an overrange state; 
         FIG. 5  is a circuit diagram for explaining a difference adjusting method according to the present invention; 
         FIG. 6  is a circuit diagram for explaining the second embodiment; 
         FIG. 7  is a timing chart showing the driving timing and operation waveforms in  FIG. 6 ; 
         FIG. 8  is a circuit diagram for explaining the third embodiment; 
         FIG. 9  is a timing chart showing the driving timing and operation waveforms in  FIG. 8 ; 
         FIG. 10  is a circuit diagram for explaining the fourth embodiment; 
         FIG. 11  is a timing chart showing the driving timing and operation waveforms in  FIG. 10 ; and 
         FIG. 12  is a timing chart showing the driving timing according to the fifth embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
       FIG. 1  illustrates an imaging system according to an embodiment of the present invention. Referring to  FIG. 1 , an imaging system  50  includes an optical system  1 , an imaging device  8 , an adjusting device  7  constructing an adjusting unit or adjusting circuit, and a signal processing circuit  5 . The optical system  1  may be a part of the imaging device  8 . The imaging device  8  includes an imaging unit  2 , A/D converting circuit  3 , and memory  4 . The optical system  1  forms an image of an object on the imaging plane of the imaging unit  2 . The imaging unit  2  is a solid-state image sensor such as a CMOS image sensor or a CCD image sensor. The imaging unit  2  has, on its imaging plane, pixels arranged in a two-dimensional array, that is, in a matrix formed from a plurality of rows and a plurality of columns. Each pixel includes a photoelectric conversion element which generates a pixel signal in accordance with incident light. The signal of an image sensed by the imaging unit  2  is output from it as an analog pixel signal V_pix. The A/D converting circuit  3  converts the analog pixel signal V_pix output from the imaging unit  2  into a digital signal and outputs it. The signal processing circuit  5  processes the digital signal output from the A/D converting circuit  3  and outputs the processed digital signal from an output terminal  6 . 
     The circuits including the imaging unit  2  and the A/D converting circuit  3  may be formed either on one semiconductor chip or on a plurality of semiconductor chips. At least the pixel array of the imaging unit  2  and the A/D converting circuit are formed on a single semiconductor chip. The memory  4  may also be formed on the same semiconductor chip as that of the imaging unit  2 . When the imaging unit  2  and the A/D converting circuit  3  are formed on one semiconductor chip, an A/D converting circuit may be provided for one or a plurality of pixel columns. Alternatively, there may be provided A/D converting circuits equal in number to the pixel signal outputs, or any other form may be adopted. 
     The adjusting device  7  includes a providing unit  71  which provides a plurality of reference signal to the A/D converting circuit  3 , and a processing unit  72  which stores adjusting data in the memory  4 . Note that, for example, a nonvolatile memory or a volatile memory backed up by a battery is used as the memory  4 . 
       FIG. 2  is a circuit diagram showing the arrangement of the A/D converting circuit  3  according to the first embodiment, which performs two-step A/D conversion, that is, higher conversion and lower conversion. A higher current source circuit  101  serving as a first current source and a lower current source circuit  102  serving as a second current source change the voltage level held by an integrating circuit  12  constructing a holding unit at a first slope ΔV 1 /Δt 1  and a second slope ΔV 2 /Δt 2  shown in  FIG. 3 , respectively. The higher current source circuit  101  and the lower current source circuit  102  supply currents I_hi and I_lo to the integrating circuit  12 , respectively. The values of these currents determine a first rate and a second rate lower than the first rate. The expression “supply a current” includes both an operation of flowing a current to the integrating circuit  12  and an operation of drawing a current from the integrating circuit  12 . When performing lower conversion of M bits, I_hi=−I_lo×2M. A switch  103  controlled by a control signal C 0  from a control unit  1001  selects one of the higher current source circuit  101  and the lower current source circuit  102 . A switch  104  controlled by a control signal C 1  from the control unit  1001  selects one of the selected current source and the pixel output V_pix. The signal selected by the switch  104  is supplied to the integrating circuit  12  constructing the holding unit via an input capacitance  105 . The integrating circuit  12  includes an operational amplifier  106 , a reset switch  107  controlled by a control signal C 2  from the control unit  1001 , an integration control switch  108  controlled by an integration control circuit  115 , and an integration capacitance  109 . 
     The output of the integrating circuit  12  is provided to a node Vout and supplied to a comparator  111  via a connection capacitance  110 . The comparator  111  compares the output of the integrating circuit  12  with a reference voltage Vref at the leading edge of a clock signal CLK 1 . When the output of the integrating circuit  12  is less than the reference voltage Vref, the comparator  111  outputs a signal latch_h. When the output of the integrating circuit  12  is more than the reference voltage Vref, the comparator  111  outputs a signal latch_l. The outputs latch_h and latch_l are supplied to a higher memory  112  and a lower memory  113 , respectively. A counter  114  is controlled by a clock signal CLK 2  whose phase is adjusted by a variable phase shifter  99  and a control signal C 4  from the control unit  1001 . The counter  114  supplies a higher count value COUNT_hi and a lower count value COUNT_lo to the higher memory  112  and the lower memory  113 , respectively. The higher memory  112  and the lower memory  113  respectively hold count values when the signals latch_h and latch_l are input. The final digital signal output of A/D conversion is a value obtained by combining higher bits as the value of the higher memory  112  and lower bits as the value of the lower memory  113 . 
     The integration control circuit  115  on/off-controls the integration control switch  108 . The integration control circuit  115  operates based on the clock signal CLK 2  and a control signal C 3  from the control unit  1001  so as to turn off the integration control switch  108  at the leading edge of the clock signal CLK 2  after the signal latch_h is input. The integration control circuit  115  also turns on the integration control switch  108  at the leading edge of the clock signal CLK 2  input from the variable phase shifter  99  after the control signal C 3  has gone high. Referring to  FIG. 2 , a write unit  11  sets, via the switch  104 , the pixel output V_pix in the integrating circuit  12  constructing the holding unit as the initial value. 
       FIG. 3  is a timing chart showing the driving timing and operation waveforms of the driving state in  FIG. 2 . Referring to  FIG. 3 , Vout represents the potential of the node Vout in  FIG. 2 . An operation of causing the A/D converting circuit  3  to A/D-convert the analog pixel signal V_pix output from the imaging unit  2  in a normal imaging operation will be described first. The switch  104  included in the write unit  11  selects the pixel signal V_pix to supply it to the integrating circuit  12 . The node Vout is charged by the pixel signal V_pix. At time t 31 , the integration control circuit  115  turns on the integration control switch  108  in synchronism with the leading edge of the clock signal CLK 2  to start an integrating operation to determine higher bits. At this time, since the switches  103  and  104  select the higher current source circuit  101  as the input to the integrating circuit  12 , the integrating circuit  12  is discharged by the higher current I_hi to lower the voltage level of the node Vout. An operation of changing the voltage level of the integrating circuit  12  from the initial level set at the pixel output V_pix at the first slope (first rate) (=−ΔV 1 /Δt 1 ) is thus performed. The comparator  111  performs comparison at the leading edge of the clock signal CLK 1 . For this reason, at time t 32  corresponding to the first leading edge of the clock signal CLK 1  after the voltage level of the node Vout falls below the reference voltage Vref, that is, after the voltage relationship has been inverted, the comparator  111  inverts the comparison result and outputs the signal latch_h of high level. Upon receiving the signal latch_h of high level, the higher memory  112  holds the count value at that point of time. The count value is determined as the higher bit value. On the other hand, the integration control circuit  115  turns off the integration control switch  108  at the leading edge of the clock signal CLK 2  after the signal latch_h of high level has been input so as to stop the integrating operation at time t 33 . Time t 34  is the timing the higher bits of the counter  114  are “111”, and corresponds to the end time of higher conversion. At time t 35  after the higher bit determination, the switch  103  is connected to the lower current source circuit  102 , and the integration control switch  108  is turned on again to start the integrating operation for determining lower bits. An operation of changing the output voltage level of the integrating circuit  12 , which intersects the reference voltage Vref so as to generate a difference from the reference voltage Vref, at the second slope (second rate) (=+ΔV 2 /Δt 2 ) is thus performed. At time t 36 , the output voltage level of the integrating circuit  12  exceeds the reference voltage Vref (that is, the voltage relationship is inverted again). Hence, the comparator  111  inverts the comparison result again and outputs the signal latch_l of high level. Upon receiving the signal latch_l of high level, the lower memory  113  holds the count value at that point of time. Time t 37  is the timing the lower bits of the counter  114  are “111”, and corresponds to the end time of lower conversion. 
     In this embodiment, the comparator  111  and the integration control switch  108  operate based on the clock signals CLK 1  and CLK 2 . This applies an offset to the generation amount of the difference between the reference voltage Vref and the output voltage level of the integrating circuit  12  during a period p 31  from the time t 32  at which comparison is performed to the time t 33  at which the integrating operation stops. The variable phase shifter  99  can adjust the period p 31  by changing the timings of the clock signals CLK 1  and CLK 2 . The variable phase shifter  99  includes, for example, a DLL circuit. The offset amount to be applied to the residual signal that is the difference between the output voltage level of the integrating circuit  12  to be provided to the node Vout and the reference voltage Vref serving as the reference level can be adjusted by the length of the period p 31 . This enables adjustment to end lower determination within a lower conversion period p 2  and consequently allows the suppression of degradation of linearity. 
     In this example, control is done using the clock signals CLK 1  and CLK 2 . However, the two clock signals may be generated by delaying one clock signal. Alternatively, the period p 31  may be generated using the leading and trailing edges of one clock signal. 
     As the method of determining the adjusting amount of the residual signal, there exists a method of determining the adjusting amount based on the lower output (lower bit output) upon sweeping the input.  FIGS. 4A to 4C  show lower outputs in overrange states and within an appropriate range. In  FIG. 4A , a minimum output continues. In this case, since the residual signal is smaller than the ideal, overrange occurs (lower determination is performed in only the first half of the lower conversion period p 2  in  FIG. 3 ). Similarly,  FIG. 4B  shows that a maximum output continues. Since the residual signal is larger than the ideal, overrange occurs (lower determination is performed in only the second half of the lower conversion period p 2  in  FIG. 3 ). That is, the lower bits nonlinearly change within the change range of the outputs of the photoelectric conversion elements, as can be seen. To the contrary,  FIG. 4C  illustrates an operation within an appropriate range, and the minimum output or maximum output does not continue. More specifically, the relationship between the value of the outputs of the photoelectric conversion elements and the value of the lower signal of the digital signal linearly changes throughout the possible range of the value of the outputs of the photoelectric conversion elements (lower determination is performed throughout the lower conversion period p 2  in  FIG. 3 ), as is apparent. This state is assumed to be ideal. Hence, if the minimum output continues, adjustment is done to increase the residual signal. Conversely, if the maximum output continues, adjustment is done to decrease the residual signal. An appropriate adjusting amount can be obtained by continuing the adjustment until the minimum or maximum output stops continuing. 
     In the first embodiment, when the minimum output continues upon sweeping the input, the period p 31  is gradually prolonged. The period p 31  obtained when the minimum output has stopped continuing is appropriate as the adjusting amount. 
     A method of adjusting the period p 31  at the time of calibration will be described next with reference to  FIG. 5 . For example, when shipping from the factory, a sweep signal generator  97  that can be provided in the providing unit  71  of the adjusting device  7  shown in  FIG. 1  can supply a continuously changing sweep signal to the integrating circuit  12  ( FIG. 2 ). More specifically, the sweep signal generator  97  sequentially supplies a plurality of voltage levels to the integrating circuit  12  to perform higher and lower A/D conversion. The signal from the lower memory  113  is supplied to a detection circuit  98  that can be provided in the processing unit  72  of the adjusting device  7  shown in  FIG. 1  so that the detection circuit  98  detects the degree of continuation of the maximum or minimum value in the lower signal. An adjusting data determining circuit  100  having, for example, an LUT (lookup table) can determine the adjusting data in accordance with the output from the detection circuit  98 . The adjusting data is stored in the memory  4 . Note that the detection circuit  98  and the adjusting data determining circuit  100  can be provided in the processing unit  72  of the adjusting device  7  shown in  FIG. 1 . The variable phase shifter  99  constructing the difference control circuit can be controlled by the output of the adjusting data determining circuit  100 . More specifically, the phase difference between the clock signals CLK 1  and CLK 2  is controlled to change the period p 31  so that an ideal residual signal is obtained. As described above, if the minimum output continues, the period p 31  is gradually prolonged. Conversely, if the maximum output continues, the period p 31  is gradually shortened. The period p 31  is controlled such that when the adjusting device  7  sequentially supplies the plurality of voltage levels, the voltage level and the digital signal output from the A/D converting circuit  3  hold a linearly relationship throughout the possible range of the voltage level. This implements the relationship as shown in  FIG. 4C . Data of the thus obtained period p 31  is stored in the memory  4  shown in  FIG. 1  or  5 . In the normal operation of the imaging device  8 , the data of the period p 31  stored in the memory  4  is used as adjusting data. Note that the adjusting data to be stored in the memory  4  may be generated for each column in the pixel area and stored at different addresses. Alternatively, adjusting data common to all columns may be stored. The above-described adjusting method is applicable to any embodiment other than the first embodiment. 
       FIG. 6  is a circuit diagram showing the arrangement of an A/D converting circuit  3  according to the second embodiment. The difference from  FIG. 2  will be explained. Referring to  FIG. 6 , a comparator  111  and a counter  114  are controlled by a common clock signal CLK 1 . A control unit  1002  of the second embodiment includes a pulse generation circuit  116 . An integration control circuit  115  controls the start of the integrating operation based on the leading edge of a pulse ENINT generated by the pulse generation circuit  116  and the stop of the integrating operation based on the leading edge of a signal latch_h. In the second embodiment, the start of count by the counter  114  at the time of lower conversion is controlled by a control signal C 4  so as to ensure a delay from the end of count by the counter  114  in higher conversion, and output of the pulse ENINT is controlled during that time. The remaining components are the same as in  FIG. 2 . 
       FIG. 7  is a timing chart showing the driving timing and operation waveforms of the driving state in  FIG. 6 . A node Vout is charged in advance by the pixel output. At time t 71 , the pulse ENINT of high level is input to the integration control circuit  115  to turn on an integration control switch  108  to start the integrating operation of higher bits. Simultaneously, the counter  114  starts the count operation. At this time, since switches  103  and  104  select a higher current source circuit  101  to supply a current to an input capacitance  105 , the integrating circuit is discharged by a higher current I_hi to lower the potential of the node Vout. The comparator  111  performs comparison at the leading edge of the clock signal CLK 1 . For this reason, at time t 72  corresponding to the first leading edge of the clock signal CLK 1  after the potential of the node Vout falls below a reference voltage Vref, the comparator  111  inverts the comparison result and outputs the signal latch_h of high level. Upon receiving the signal latch_h of high level, a higher memory  112  holds the count value at that point of time. Upon receiving the signal latch_h of high level simultaneously, the integration control circuit  115  turns off the integration control switch  108  to stop the integrating operation. Time t 73  is the timing the higher bits of the counter  114  are “111”, and corresponds to the end time of higher conversion. 
     After that, the switch  103  is connected to a lower current source circuit  102 . At time t 74 , the pulse ENINT rises, and the integration control switch  108  is turned on again to start lower integration. At this time, the counter  114  does not operate in synchronism with turning on the integration control switch  108 . The count operation starts at time t 75  after the elapse of a period p 71  from the time t 74 . The period p 71  is determined by the time t 74  the pulse ENINT is generated (the number of clock signals CLK 1  from the time t 71  the preceding pulse ENINT has been generated). 
     At time t 76 , the comparator  111  inverts the comparison result again and outputs a signal latch_l of high level. Upon receiving the signal latch_l of high level, a lower memory  113  holds the count value. Time t 77  is the timing the lower bits of the counter  114  are “111”, and corresponds to the end time of lower conversion. 
     In this embodiment, the offset amount of the residual signal can be adjusted by the length of the period p 71  from the lower bit integration start time t 74  to the count start time t 75 . Adjusting the period p 71  to a value corresponding to the difference from the ideal value of the residual signal enables adjustment to perform conversion within a lower conversion period p 2  and consequently allows to suppress degradation of linearity. The adjusting amount determining method is the same as that described in the first embodiment. More specifically, a sweep signal generator  97 , detection circuit  98 , and adjusting data determining circuit  100  are provided, as in the first embodiment. An input V_pix to the integrating circuit is swept by a sweep signal supplied from the sweep signal generator  97  provided in a providing unit  71  and continuously changed. The detection circuit  98  detects the output from the lower memory  113  at this time. The detection circuit  98  detects the degree of continuation of the maximum or minimum value in the lower signal. The adjusting data determining circuit  100  determines adjusting data in accordance with the output from the detection circuit  98 . Note that the detection circuit  98  and the adjusting data determining circuit  100  are provided in a processing unit  72  of an adjusting device  7  shown in  FIG. 1 . The adjusting data is supplied to the pulse generation circuit  116  to control the timing of the pulse ENINT, thereby adjusting the period p 71 . Data of the thus obtained period p 71  is stored in a memory  4  shown in  FIG. 1 . In the normal operation of an imaging device  8 , the data of the period p 71  stored in the memory  4  is used as adjusting data to control the timing of the pulse ENINT. Note that in the second embodiment, the count start time t 75  of the counter  114  in lower conversion by the control signal C 4  or the count start time t 75  and the timing t 74  of the pulse ENINT may be adjusted together. 
       FIG. 8  is a circuit diagram showing an example of the arrangement of an A/D converting circuit  3  according to the third embodiment. The difference from  FIG. 2  will be explained. Referring to  FIG. 8 , an offset current source circuit  121  is provided in addition to a higher current source circuit  101  and a lower current source circuit  102 . A current I_off supplied by the offset current source circuit  121  has an arbitrary value. A switch  122  controlled by a control signal C′ 0  from a control unit  1003  selects one of the current source circuits  101 ,  102 , and  121 . An integration control switch  108  is controlled by a signal from an integration control circuit  115  driven by signals CLK 1  and latch_h and also by a signal from a pulse width control circuit  150  provided in the control unit  1003 . The integration control switch  108  in  FIG. 8  is connected if one of the signal from the integration control circuit  115  and the signal from the pulse width control circuit  150  is at high level. In the third embodiment, the start of count by a counter  114  at the time of lower conversion is controlled by a control signal C 4  so as to ensure a delay from the end of count by the counter  114  in higher conversion, and output of the signal from the pulse width control circuit  150  is controlled during that time. The remaining components are the same as in  FIG. 2 . 
       FIG. 9  is a timing chart showing the driving timing and operation waveforms of the driving state in  FIG. 8 . A node Vout is charged in advance by the pixel output. At time t 91 , the integration control circuit  115  turns on the integration control switch  108  in synchronism with the clock signal CLK 1  to start the integrating operation of higher bits. Simultaneously, the counter  114  starts the count operation. At this time, since the switches  122  and  104  select the higher current source circuit  101  to supply a current to an input capacitance  105 , the integrating circuit is discharged by a higher current I_hi to lower the potential of the node Vout. A comparator  111  performs comparison at the leading edge of the clock signal CLK 1 . For this reason, at time t 92  corresponding to the first leading edge of the clock signal CLK 1  after the potential of the node Vout falls below a reference voltage Vref, the comparator  111  inverts the comparison result and outputs the signal latch_h of high level. Upon receiving the signal latch_h of high level, a higher memory  112  holds the count value at that point of time. Upon receiving the signal latch_h of high level simultaneously, the integration control circuit  115  turns off the integration control switch  108  to stop the integrating operation. Time t 93  is the timing the higher bits of the counter  114  are “111”, and corresponds to the end time of higher conversion. 
     After that, the switch  122  is connected to the offset current source circuit  121 . At time t 94 , a signal OFFSET SEL output from the pulse width control circuit  150  falls to turn on the integration control switch. After a period p 91  where the signal OFFSET SEL is at high level, offset integration stops at time t 95 . Then, the switch  122  is connected to the lower current source circuit  102 , and integration of lower bits and lower count start at time t 96 . 
     At time t 97 , the comparator  111  inverts the comparison result again and outputs a signal latch_l of high level. Upon receiving the signal latch_l of high level, a lower memory  113  holds the count value. Time t 98  is the timing the lower bits of the counter  114  are “111”, and corresponds to the end time of lower conversion. 
     In this embodiment, a period where the offset current I_off supplied by the offset current source circuit  121  serving as a third current source is injected is provided between higher conversion and lower conversion so that integration is performed during the period p 91  using the arbitrary offset current I_off. Hence, the lower residual amount can be adjusted by the changing the period p 91 . Adjusting the period p 91  to a value corresponding to the difference from the ideal value of the lower residual signal enables adjustment to end lower determination within a lower conversion period p 2  and consequently allows to suppress degradation of linearity. As a detailed adjusting method, an input V_pix to the integrating circuit is swept and continuously changed, as described above. More specifically, a plurality of voltage levels are sequentially supplied to the integrating circuit of the A/D converting circuit. A detection circuit  98  detects the output from the lower memory  113  at this time. The detection circuit  98  detects the degree of continuation of the maximum or minimum value in the lower signal. An adjusting data determining circuit  100  determines adjusting data in accordance with the output from the detection circuit  98 . The detection circuit  98  and the adjusting data determining circuit  100  can be provided in a processing unit  72  of an adjusting device  7  shown in  FIG. 1 . The adjusting data is supplied to the pulse width control circuit  150  which controls the pulse width of the signal OFFSET SEL. The integration control switch  108  can be controlled by the output of the pulse width control circuit  150  to control the integration period p 91  by the offset current I_off. Data of the thus obtained period p 91  is stored in a memory  4  shown in  FIG. 1 . In the normal operation of an imaging device  8 , the data of the period p 91  stored in the memory  4  is used as adjusting data. 
       FIG. 10  is a circuit diagram of an A/D converting circuit  3  according to the fourth embodiment. The difference from  FIG. 8  will be explained. Referring to  FIG. 10 , a current DAC  131  is used as a current source circuit to supply an arbitrary current. An example of the current DAC  131  is a circuit for supplying a current corresponding to a digital control signal C″ 0  from outside. In the fourth embodiment, a control unit  1004  includes a pulse generation circuit  150 ′ for a fixed pulse width, and a current control circuit  160  which generates the control signal C″ 0  to adjust the current of the current DAC  131  in accordance with adjusting data. The remaining components are the same as in  FIG. 8 . 
       FIG. 11  is a timing chart showing the driving timing and operation waveforms of the driving state in  FIG. 10 . A node Vout is charged in advance by the pixel output. At time t 111 , an integration control circuit  115  turns on an integration control switch  108  in synchronism with a clock signal CLK 1  to start the integrating operation of higher bits. The current DAC  131  supplies a higher current I_hi during a period p 0 . After higher determination at time t 112 , higher conversion ends at time t 113  that is the timing the higher bits of a counter  114  are “111”. At time t 114 , a signal OFFSET SEL of high level turns on the integration control switch  108  to perform the integrating operation during a period p 112 . The period p 112  can be fixed. During the period p 112 , the current DAC  131  supplies an arbitrary current I_off determined by the control signal C″ 0 . 
     At time t 115 , the integrating operation by the offset current stops. At time t 116 , the integrating operation of lower bits starts. At time t 117 , lower determination is performed. During a period p 2 , the current DAC  131  supplies a lower current I_lo. When performing lower conversion of M bits, I_hi=−I_lo×2M. Using the current DAC  131  enables to set the current I_off to be supplied during the period p 112  to an arbitrary value and adjust the residual amount. Adjusting the current I_off to a value corresponding to the difference from the ideal value of the lower residual signal enables adjustment to end lower determination within the lower conversion period p 2  and consequently allows to suppress degradation of linearity. As a detailed adjusting method, an input V_pix to the integrating circuit is swept and continuously changed, as described above. More specifically, a plurality of voltage levels are sequentially supplied to the integrating circuit of the A/D converting circuit. A detection circuit  98  detects the output from a lower memory  113  at this time. The detection circuit  98  detects the degree of continuation of the maximum or minimum value in the lower signal. An adjusting data determining circuit  100  determines adjusting data in accordance with the output from the detection circuit  98 . Note that the detection circuit  98  and the adjusting data determining circuit  100  are provided in a processing unit  72  of an adjusting device  7  shown in  FIG. 1 . The adjusting data is supplied to the current DAC  131  to control the current I_off, thereby performing adjustment. Data of the thus obtained current value I_off is stored in a memory  4  shown in  FIG. 1 . In the normal operation of an imaging device  8 , the data of the current I_off stored in the memory  4  is used as adjusting data. 
     An A/D converting circuit  3  according to the fifth embodiment will be explained next. In the fifth embodiment, redundancy bits are used in lower conversion. That is, the number of lower bits is changeable. The circuit diagram to be used in the description of this embodiment is the same as  FIG. 2 . However, lower count by a counter  114  is done using (M+1) bits by adding one redundancy bit to the M bit accuracy of higher count. Hence, the lower output is (M+1) bits. The LSB (Least Significant Bit) of the higher output corresponds to the MSB (Most Significant Bit) of the lower output. The current supplied from the current source circuit is I_hi=−I_lo×2M. 
       FIG. 12  is a timing chart showing the driving timing and operation waveforms of the driving state according to the embodiment. Vout_h and Vout_l are the maximum signal and minimum signal of an integration output Vout, respectively. At time t 121 , higher conversion starts. As for the integration output Vout, the comparator inverts the output at time t 122  so that the higher count is stored in a higher memory  112 . After that, after the elapse of a period p 31  corresponding to the phase difference between clock signals CLK 1  and CLK 2 , the integrating operation stops at time t 123 . At time t 124  corresponding to the timing the higher bits of the counter  114  are “111”, higher conversion ends. After that, at time t 125 , lower integration and count start. The comparator inverts the output at time t 126  when the input is Vout_h and at time t 127  when the input is Vout_ 1 , and outputs signals latch_ 11  and latch_ 12 . The signal latch_ 11  is the signal latch_ 1  output from the comparator  111  when Vout_h is used for conversion. The signal latch_ 12  is the signal latch_l output from the comparator  111  when Vout_ 1  is used for conversion. Time t 128  is the timing the lower bits of the counter  114  are “1111”, and corresponds to the end time of lower conversion. 
     Ideally, lower conversion is done within the range of a period p 22  from the time t 126  to the time t 127 . However, the actual inversion timing distribution of the integrator is represented by the lower inversion timing distribution in  FIG. 12  due to random noise or variations between ADCs. When the lower bits include redundancy bits, the period p 31  is adjusted such that the distribution falls within a lower conversion period p 21 , thereby suppressing degradation of linearity. 
     In this embodiment, the residual signal adjusting function and lower bit redundancy are combined to suppress degradation of linearity even when the lower output varies. In addition, a lower residual signal adjusting accuracy is allowed. 
     In the above-described embodiments, only the read circuit corresponding to one column of the pixel array is shown. In the pixel array in which the pixels are arranged two-dimensionally, read circuits with the same arrangement are provided in parallel. In  FIGS. 2 ,  6 ,  8 , and  10 , the higher current source circuit  101 , lower current source circuit  102 , and counter  114  are common to the plurality of read circuits. Note that though a current is supplied to the integrating circuit in the embodiments, the embodiments are also applicable to a multi-step type A/D converting circuit arrangement using a voltage. 
     While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all modifications, equivalent structures and functions. 
     This application claims the benefit of Japanese Patent Application No. 2010-005153, filed Jan. 13, 2010 and No. 2010-171177, filed Jul. 29, 2010, which are hereby incorporated by reference herein in their entirety.