Patent Publication Number: US-2022230969-A1

Title: Package structure and method of fabricating the same

Description:
BACKGROUND 
     Semiconductor devices and integrated circuits used in a variety of electronic applications, such as cell phones and other mobile electronic equipment, are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies have been developed for the wafer level packaging. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1A  to  FIG. 1I  are schematic top and sectional views of various stages in a method of fabricating a semiconductor package according to some exemplary embodiments of the present disclosure. 
         FIG. 2  is a schematic sectional view of a semiconductor package according to some other exemplary embodiments of the present disclosure. 
         FIG. 3A  to  FIG. 3D  are schematic top and sectional views of various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure. 
         FIG. 4  to  FIG. 8  are top views of a first ring structure in accordance with various embodiments of the present disclosure. 
         FIG. 9  is a schematic sectional view of a package structure according to some exemplary embodiments of the present disclosure. 
         FIG. 10  is a schematic sectional view of a package structure according to some other exemplary embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “over”, “overlying”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In conventional package structures, corner molding usually has larger molding stress due to a larger molding volume, which induces local deformation and presents a higher risk of molding crack and delamination. In some embodiments of the present disclosure, while providing a ring structure (stiffener ring) to reduce the warpage of the package substrates, the design of the ring structure is modified to help reduce the molding stress and warpage of the package structure. In some embodiments, the package structure has a larger distance between the inner surfaces of the ring structure and the inner semiconductor package at corner portions, than that at other portions. The inner surfaces of the ring structure shrink at corner portions to leave more space from the inner semiconductor package. 
       FIG. 1A  to  FIG. 1I  are schematic top and sectional views of various stages in a method of fabricating a semiconductor package according to some exemplary embodiments of the present disclosure. Referring to  FIG. 1A , an interposer structure  100  is provided. In some embodiments, the interposer structure  100  includes a core portion  102 , and a plurality of through vias  104  and conductive pads  106  formed therein. In some embodiments, the core portion  102  is a substrate such as a bulk semiconductor substrate, silicon on insulator (SOI) substrate or a multi-layered semiconductor material substrate. The semiconductor material of the substrate (core portion  102 ) may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some embodiments, the core portion  102  is doped or undoped. 
     In some embodiments, the conductive pads  106  are formed on a first surface  102   a  of the core portion  102 . In some embodiments, through vias  104  are formed in the core portion  102  and connected with the conductive pads  106 . In some embodiments, the through vias  104  extend into the core portion  102  with a specific depth. In some embodiments, the through vias  104  are through-substrate vias. In some embodiments, the through vias  104  are through-silicon vias when the core portion  102  is a silicon substrate. In some embodiments, the through vias  104  are formed by forming holes or recesses in the core portion  102  and then filling the recesses with a conductive material. In some embodiments, the recesses are formed by, for example, etching, milling, laser drilling or the like. In some embodiments, the conductive material is formed by an electro-chemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD), and the conductive material may include copper, tungsten, aluminum, silver, gold or a combination thereof. In some embodiments, the conductive pads  106  connected with the through vias  104  are formed as conductive parts of the redistribution layer(s) formed on the interposer structure  100 . In some embodiments, the conductive pads  106  include under bump metallurgies (UBMs). In certain embodiments, the interposer structure  100  may further include active or passive devices, such as transistors, capacitors, resistors, or diodes passive devices formed in the core portion  102 . 
     As shown in  FIG. 1A , the core portion  102  has a plurality of package regions PKR and a dicing lane DL separating each of the plurality of package regions PKR. The through vias  104  and conductive pads  106  are formed in the core portion  102  within the package regions PKR. In some embodiments, a plurality of semiconductor dies  21  (first semiconductor dies) and a plurality of semiconductor dies  22  (second semiconductor dies) are provided on the interposer structure  100 , or on the core portion  102  within the package regions PKR. The semiconductor dies  21  and semiconductor dies  22  are individual dies singulated from a wafer. In some embodiments, the semiconductor dies  21  contain the same circuitry, such as devices and metallization patterns, or the semiconductor dies  21  are the same type of dies. In some embodiments, the semiconductor dies  22  contain the same circuitry, or the semiconductor dies  22  are the same type of dies. In certain embodiments, the semiconductor dies  21  and the semiconductor dies  22  have different circuitry or are different types of dies. In some embodiments, the semiconductor dies  21  and the semiconductor dies  22  may have the same circuitry. 
     In some embodiments, the semiconductor dies  21  are major dies, while the semiconductor dies  22  are tributary dies. In some embodiments, the major dies are arranged on the core portion  102  in central locations of each package region PKR, while tributary dies are arranged side-by-side and spaced apart from the major dies. In some embodiments, the tributary dies are arranged aside the major dies, and around or surrounding the major dies. In one embodiment, four, six or eight tributary dies are arranged around one major die per one package region PKR. For example, referring to  FIG. 1B , in an exemplary embodiment, eight semiconductor dies  22  (tributary dies) are surrounding one semiconductor die  21  (major die) in each of the package region PKR. 
     Referring back to  FIG. 1A , in some embodiments, the semiconductor dies  21  has a surface area larger than that of the semiconductor dies  22 . Also, in some embodiments, the semiconductor dies  21  and the semiconductor dies  22  are of different sizes, including different surface areas and/or different thicknesses. In some embodiments, the semiconductor dies  21  are a logic die, including a central processing unit (CPU) die, graphics processing unit (GPU) die, system-on-a-chip (SoC) die, a microcontroller or the like. In some embodiments, the semiconductor dies  21  is a power management die, such as a power management integrated circuit (PMIC) die. In some embodiments, the semiconductor dies  22  are a memory die, including dynamic random access memory (DRAM) die, static random access memory (SRAM) die or a high bandwidth memory (HBM) die. In some alternative embodiments, the semiconductor dies  22  are dummy dies, which do not perform any electrical functions. The disclosure is not limited thereto, and the number, sizes and types of the semiconductor die disposed on the core portion  102  may be appropriately adjusted based on product requirement. 
     As illustrated in  FIG. 1A , the semiconductor dies  21  include a body  210  and connecting pads  212  formed on an active surface  211  of the body  210 . In certain embodiments, the connecting pads  212  may further include pillar structures for bonding the semiconductor dies  21  to other structures. In some embodiments, the semiconductor dies  22  include a body  220  and connecting pads  222  formed on an active surface  221  of the body  220 . In other embodiments, the connecting pads  222  may further include pillar structures for bonding the dies  22  to other structures. 
     In some embodiments, the semiconductor dies  21  and the semiconductor dies  22  are attached to the first surface  102   a  of the core portion  102 , for example, through flip-chip bonding by way of the electrical connectors  110 . Through a reflow process, the electrical connectors  110  are formed between the connecting pads  212 ,  222  and conductive pads  106 , and are physically connecting the semiconductor dies  21 ,  22  to the core portion  102  of the interposer structure  100 . In some embodiments, the electrical connectors  110  are located in between the semiconductor dies  21 ,  22  and the interposer structure  100 . In certain embodiments, semiconductor dies  21 ,  22  are electrically connected to the through vias  104  and the conductive pads  106  through the electrical connectors  110 . In some alternative embodiments, when the semiconductor dies  22  are dummy dies, the semiconductor dies  22  may be attached to the electrical connectors  110  through physical connection without establishing an electrical connection thereto. In other words, the connecting pads  222  of the semiconductor dies  22  may be dummy pads, for example. 
     In one embodiment, the electrical connectors  110  are micro-bumps, such as micro-bumps having copper metal pillars. In another embodiment, the electrical connectors  110  are solder bumps, lead-free solder bumps, or micro bumps, such as controlled collapse chip connection (C4) bumps or micro bumps containing copper pillars. In some embodiments, the bonding between the semiconductor dies  21 ,  22  and the core portion  102  is solder bonding. In some embodiments, the bonding between the semiconductor dies  21 ,  22  and the core portion  102  is direct metal-to-metal bonding, such as copper-to-copper bonding. 
     Referring to  FIG. 1C , thereafter, an underfill structure  112  may be formed to cover the plurality of electrical connectors  110 , and to fill up the spaces in between the semiconductor dies  21 ,  22  and the interposer structure  100 . In some embodiments, the underfill structure  112  further cover side walls of the semiconductor dies  21 ,  22 , and is located within the package region PKR. Thereafter, an insulating encapsulant  114  (or molding compound) may be formed over the interposer structure  100  (or over the core portion  102 ) to cover the underfill structure  112 , and to surround the semiconductor dies  21  and  22 . 
     In some embodiments, the insulating encapsulant  114  is formed on the first surface  102   a  of the core portion  102  in the package regions PKR and over the dicing lanes DL. In some embodiments, the insulating encapsulant  114  is formed through, for example, a compression molding process or transfer molding. In one embodiment, a curing process is performed to cure the insulating encapsulant  114 . In some embodiments, the semiconductor dies  21 ,  22  and the electrical connectors  110  are encapsulated by the insulating encapsulant  114 . In some embodiments, a planarization process, including grinding or polishing, is performed to partially remove the insulating encapsulant  114 , exposing backside surfaces  21 S,  22 S of the semiconductor dies  21 ,  22 . Accordingly, the backside surfaces  21 S,  22 S of the semiconductor dies  21 ,  22  are levelled with a top surface  114   a  of the insulating encapsulant  114 . The top surface  114   a  being opposite to a backside surface  114   b  of the insulating encapsulant  114 , wherein the backside surface  114   b  is in contact with the core portion  102 . In some alternative embodiments, the backside surfaces  21 S,  22 S of the semiconductor dies  21 ,  22  are not exposed from the insulating encapsulant  114 , and are well protected by the insulating encapsulant  114 . 
     In some embodiments, a material of the insulating encapsulant  114  includes polymers (such as epoxy resins, phenolic resins, silicon-containing resins, or other suitable resins), dielectric materials having low permittivity (Dk) and low loss tangent (Df) properties, or other suitable materials. In an alternative embodiment, the insulating encapsulant  114  may include an acceptable insulating encapsulation material. In some embodiments, the insulating encapsulant  114  may further include inorganic filler or inorganic compound (e.g. silica, clay, and so on) which can be added therein to optimize coefficient of thermal expansion (CTE) of the insulating encapsulant  114 . The disclosure is not limited thereto. 
     Referring to  FIG. 1D , the structure of  FIG. 1C  is turned upside down or flipped, and placed on a carrier Cx, so that the carrier Cx directly contacts the backside surfaces  21 S,  22 S of the semiconductor dies  21 ,  22  and the top surface  114   a  of the insulating encapsulant  114 . As shown in  FIG. 1D , at this stage of processing, the interposer structure  100  has not been thinned and has a thickness Tx. In other words, the through vias  104  are not revealed, and are embedded in the core portion  102  of the interposer structure  100 . 
     Referring to  FIG. 1E , a thinning process is performed to the interposer  100  to partially remove or thin the core portion  102  of the interposer structure  100  until the through vias  104  are exposed and a second surface  102   b  of the core portion  102  is formed. In some embodiments, the thinning process may include a back-grinding process, a polishing process or an etching process. In some embodiments, after the thinning process, the interposer structure  100  is thinned to a thickness Ty. In some embodiments, a ratio of the thickness Ty to the thickness Tx ranges from about 0.1 to about 0.5. 
     Referring to  FIG. 1F , a redistribution structure  116  is formed on the second surface  102   b  of the core portion  102  in the package region PKR and over the dicing lanes DL. The second surface  102   b  being opposite to the first surface  102   a  of the core portion  102 . In some embodiments, the redistribution structure  116 , the core portion  102 , the through vias  104  and conductive pads  106  constitutes the interposer structure  100 ′. In some embodiments, the redistribution structure  116  electrically connects the through vias  104  and/or electrically connects the through vias  104  with external devices. In certain embodiments, the redistribution structure  116  includes at least one dielectric layer  116   a  and metallization patterns  116   b  in the dielectric layer  116   a . In some embodiments, the metallization patterns  116   b  may comprise pads, vias and/or trace lines to interconnect the through vias  104  and to further connect the through vias  104  to one or more external devices. Although one layer of dielectric layer  116   a , and one layer of the metallization patterns  116   b  is shown in  FIG. 1F , it should be noted that the number of layers of the dielectric layer  116   a  and the metallization patterns  116   b  is not limited thereto, and this could be adjusted based on requirement. 
     In some embodiments, the material of the dielectric layer  116   a  comprises silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or low-K dielectric materials (such as phosphosilicate glass materials, fluorosilicate glass materials, boro-phosphosilicate glass materials, SiOC, spin-on-glass materials, spin-on-polymers or silicon carbon materials). In some embodiments, the dielectric layer  116   a  is formed by spin-coating or deposition, including chemical vapor deposition (CVD), PECVD, HDP-CVD, or the like. In some embodiments, the metallization patterns  116   b  include under-metal metallurgies (UBMs). In some embodiments, the formation of the metallization patterns  116   b  may include patterning the dielectric layer using photolithography techniques and one or more etching processes and filling a metallic material into the openings of the patterned dielectric layer. Any excessive conductive material on the dielectric layer may be removed, such as by using a chemical mechanical polishing process. In some embodiments, the material of the metallization patterns  116   b  includes copper, aluminum, tungsten, silver, and combinations thereof. 
     As further illustrated in  FIG. 1F , a plurality of conductive terminals  118  is disposed on the metallization patterns  116   b , and are electrically coupled to the through vias  104 . In some embodiments, the conductive terminals  118  are placed on the top surface  116   s  of the redistribution structure  116 , and electrically connected to the through vias  104  by the metallization patterns  116   b  within the package region PKR. In certain embodiments, the conductive terminals  118  are positioned on and physically attached to the metallization patterns  116   b . In some embodiments, the conductive terminals  118  include lead-free solder balls, solder balls, ball grid array (BGA) balls, bumps, C4 bumps or micro bumps. In some embodiments, the conductive terminals  118  may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or a combination thereof. In some embodiments, the conductive terminals  118  are formed by forming the solder paste on the redistribution structure  116  by, for example, evaporation, electroplating, printing or solder transfer and then reflowed into the desired bump shapes. In some embodiments, the conductive terminals  118  are placed on the redistribution structure  116  by ball placement or the like. In other embodiments, the conductive terminals  118  are formed by forming solder-free metal pillars (such as a copper pillar) by sputtering, printing, electroless or electro plating or CVD, and then forming a lead-free cap layer by plating on the metal pillars. The conductive terminals  118  may be used to bond to an external device or an additional electrical component. In some embodiments, the conductive terminals  118  are used to bond to a circuit substrate, a semiconductor substrate or a packaging substrate. 
     Referring to  FIG. 1G , in a subsequent step, the carrier Cx is de-bonded. For example, the de-bonding process includes projecting a light such as a laser light or an UV light on a debond layer (e.g., light-to-heat-conversion release layer) that is attached to the carrier Cx (not shown), so that the carrier Cx can be easily removed along with the debond layer. In some embodiments, the backside surfaces  21 S,  22 S of the semiconductor dies  21 ,  22  are revealed after the de-bonding process. 
     Referring to  FIG. 1H , after de-bonding the carrier Cx, the structure shown in  FIG. 1G  is attached to a tape TP (e.g., a dicing tape) supported by a frame FR. Subsequently, the structure shown in  FIG. 1G  is diced or singulated along the dicing lanes DL to form a plurality of semiconductor packages SM. For example, the dicing process is performed to cut through the redistribution structure  116 , the core portion  102 , and the insulating encapsulant  114  to remove portions of the redistribution structure  116 , the core portion  102 , and the insulating encapsulant  114  along the dicing lanes DL. In some embodiments, the dicing process or the singulation process typically involves dicing with a rotating blade or a laser beam. In other words, the dicing or singulation process is, for example, a laser cutting process, a mechanical sawing process, or other suitable processes. After debonding the carrier Cx, the singulated semiconductor package SM illustrated in  FIG. 1I  can be obtained. 
       FIG. 2  is a schematic sectional view of a semiconductor package according to some other exemplary embodiments of the present disclosure. The semiconductor package SM 2  illustrated in  FIG. 2  is similar to the semiconductor package SM illustrated in  FIG. 1I . Therefore, the same reference numerals may be used to refer to the same or liked parts, and its detailed description will be omitted herein. The difference between the embodiments is that the interposer structure  100 ′ illustrated in  FIG. 1I  is replaced with a redistribution layer RDL illustrated in  FIG. 2 . As illustrated in  FIG. 2 , the redistribution layer RDL is disposed on the insulating encapsulant  114  and electrically connected to the semiconductor dies  21 ,  22  through the electrical connectors  110 . 
     In some embodiments, the redistribution layer RDL is formed by sequentially forming one or more dielectric layers  101 A and one or more conductive layers  101 B in alternation. In certain embodiments, the conductive layers  101 B are sandwiched between the dielectric layers  101 A, and are electrically and physically connected to the electrical connectors  110 . In the exemplary embodiment, the numbers of the dielectric layers  101 A and the conductive layers  101 B included in the redistribution layer RDL is not limited thereto, and may be designated and selected based on the design requirements. For example, the numbers of the dielectric layers  101 A and the conductive layers  101 B may be one or more than one. 
     In some embodiments, the material of the dielectric layers  101 A is polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof or the like, which may be patterned using a photolithography and/or etching process. In some embodiments, the material of the dielectric layers DI 1  is formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like. The disclosure is not limited thereto. 
     In some embodiments, the material of the conductive layer  101 B is made of conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using a photolithography and etching process. In some embodiments, the conductive layer  101 B may be patterned copper layers or other suitable patterned metal layers. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc. 
     In certain embodiments, the redistribution layer RDL further includes a plurality of conductive pads  101 C disposed on the conductive layers  101 B for electrically connecting with conductive terminals  118 . In some embodiments, the materials of the conductive pads  101 C may include copper, nickel, titanium, tungsten, or alloys thereof or the like, and may be formed by an electroplating process, for example. The number of conductive pads  101 C are not limited in this disclosure, and may be selected based on the design layout. In some alternative embodiments, the conductive pads  101 C may be omitted. In other words, the conductive terminals  118  formed in subsequent steps may be directly disposed on the conductive layers  101 B of the redistribution layer RDL. 
       FIG. 3A  to  FIG. 3D  are schematic top and sectional views of various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure. Referring to  FIG. 3A , in some embodiments, the semiconductor package SM obtained in  FIG. 1H  is mounted or attached onto a circuit substrate  300  through the conductive terminals  118 . In some embodiments, the circuit substrate  300  includes contact pads  310 , contact pads  320 , metallization layers  330 , and vias (not shown). In some embodiments, the contact pads  310  and the contact pads  320  are respectively distributed on two opposite sides of the circuit substrate  300 , and are exposed for electrically connecting with later-formed elements/features. In some embodiments, the metallization layers  330  and the vias are embedded in the circuit substrate  300  and together provide routing function for the circuit substrate  300 , wherein the metallization layers  330  and the vias are electrically connected to the contact pads  310  and the contact pads  320 . In other words, at least some of the contact pads  310  are electrically connected to some of the contact pads  320  through the metallization layers  330  and the vias. In some embodiments, the contact pads  310  and the contact pads  320  may include metal pads or metal alloy pads. In some embodiments, the materials of the metallization layers  330  and the vias may be substantially the same or similar to the material of the contact pads  310  and the contact pads  320 . 
     Furthermore, in some embodiments, the semiconductor package SM is bonded to the circuit substrate  300  through physically connecting the conductive terminals  118  and the contact pads  310  to form a stacked structure. In certain embodiments, the semiconductor package SM is electrically connected to the circuit substrate  300 . In some embodiments, the circuit substrate  300  is such as an organic flexible substrate or a printed circuit board. In such embodiments, the conductive terminals  118  are, for example, chip connectors. In some embodiments, a plurality of conductive balls  340  are respectively formed on the substrate  300 . As illustrated in  FIG. 3A , for example, the conductive balls  340  are connected to the contact pads  320  of the circuit substrate  300 . In other words, the conductive balls  340  are electrically connected to the circuit substrate  300  through the contact pads  320 . Through the contact pads  310  and the contact pads  320 , some of the conductive balls  340  are electrically connected to the semiconductor package SM (e.g. the semiconductor dies  21  and  22  included therein). In some embodiments, the conductive balls  340  are, for example, solder balls or BGA balls. In some embodiments, the semiconductor package SM is bonded to the circuit substrate  300  through physically connecting the conductive terminals  118  and the contact pads  310  of the circuit substrate  300  by a chip on wafer on substrate (CoWoS) packaging processes. In addition, as illustrated in  FIG. 3A , passive devices PDx (integrated passive device or surface mount devices) may be mounted on the circuit substrate  300 . For example, the passive devices PDx may be mounted on the contact pads  310  of the circuit substrate  300  through a soldering process. The disclosure is not limited thereto. In certain embodiments, the passive devices PDx may be mounted on the circuit substrate surrounding the semiconductor package SM. In some alternative embodiments, the passive devices PDx are omitted. 
     As further illustrated in  FIG. 3A , in some embodiments, an underfill structure  350  is formed to fill up the spaces in between the circuit substrate  300  and the semiconductor package SM. In certain embodiments, the underfill structure  350  fills up the spaces in between adjacent conductive terminals  118  and covers the conductive terminals  118 . For example, the underfill structure  350  surrounds the plurality of conductive terminals  118 . In some embodiments, the passive devices PDx is exposed by the underfill structure  350 , and kept a distance apart from the underfill structure  350 . In other words, the underfill structure  350  does not cover the passive devices PDx. 
     Referring to  FIG. 3B , in a subsequent step, a first ring structure RS 1  (first stiffener ring) is attached to the circuit substrate  300  through a first adhesive AD 1 , and a second ring structure RS 2  (second stiffener ring) is attached to the first ring structure RS 2  through a second adhesive AD 2 . The first ring structure RS 1  may surround the interposer structure  100 ′ and partially surround the insulating encapsulant  114 , while the second ring structure RS 2  may partially surround the insulating encapsulant  114  and the semiconductor dies  21 ,  22 . In some embodiments, depending on the thicknesses of the semiconductor dies  21 ,  22 , the first ring structure RS 1  may also be partially surrounding the semiconductor dies  21 ,  22 . 
     In some embodiments, the first ring structure RS 1  is made of a material having a smaller coefficient of thermal expansion (CTE) than a material of the second ring structure RS 2 . In some embodiments, the first ring structure RS 1  and the second ring structure RS 2  are both formed of a metallic material. For example, in one embodiment, the first ring structure RS 1  is made of stainless steel 304SS, and the second ring structure RS 2  is made of stainless steel 430SS. The disclosure is not limited thereto. After attaching the first ring structure RS 1  and the second ring structure RS 2  onto the circuit substrate  300 , a package structure PKS 1  according to some embodiments of the present disclosure may be accomplished. 
     The first ring structure RS 1  and the second ring structure RS 2  will be described in more details by referring to the top views illustrated in  FIG. 3C  and  FIG. 3D .  FIG. 3C  illustrates a top view of the first ring structure RS 1 , while  FIG. 3D  illustrates a top view of the second ring structure RS 2 . In the top views from  FIG. 3C  and  FIG. 3D , the underfill structure  350  and the passive devices PDx are omitted for ease of illustration. 
     As shown in  FIG. 3B  and  FIG. 3C , in some embodiments, the first ring structure RS 1  (first stiffener ring) is attached to the circuit substrate  300  and surrounding the semiconductor package SM. Furthermore, the first ring structure RS 1  is located in between the circuit substrate  300  and the second ring structure RS 2 . In some embodiments, the first ring structure RS 1  includes a central opening OP 1  and a plurality of corner openings OP 2  extending out from corners of the central opening OP 1 . In some embodiments, the central opening OP 1  of the first ring structure RS 1  is a square-shaped or rectangular-shaped opening having four corners, and corner digging is performed at the four corners to form the plurality of corner openings OP 2 . In other words, the corner openings OP 2  are joined with the central opening OP 1 , and extends out from the four corners of the square-shaped or rectangular-shaped central opening OP 1 . In certain embodiments, the corner openings OP 2  has a polygonal outline. For example, in the exemplary embodiment, corner digging is performed with a square-shaped outline at a position overlapped with the four corners of the central opening OP 1  to form the corner openings OP 2 . 
     In some embodiments, the semiconductor package SM is located in the central opening OP 1 , and the plurality of corner openings OP 2  is surrounding the corners of the semiconductor package SM. For example, the semiconductor package SM is encircled by the central opening OP 1  and the corner openings OP 2  of the first ring structure RS 1 . In some embodiments, each of the corner openings OP 2  has a first width d 1  extending in a first direction DR 1  and a second width d 2  extending in a second direction DR 2 . For example, the first direction DR 1  is perpendicular to the second direction DR 2 , and the first width d 1  is substantially equal to the second width d 2 . Furthermore, the first width d 1  and the second width d 2  do not extend beyond a ring foot (outer corners) of the first ring structure RS 1 . That is, a continuous ring-like structure is formed by the first ring structure RS 1 . 
     In some embodiments, the semiconductor package SM is spaced apart from a boundary of the central opening OP 1  by a distance d 3  and a distance d 4 . In some embodiments, the distance d 3  is measured in the first direction DR 1  and the distance d 4  is measured in the second direction DR 2 . In some embodiments, the distance d 3  and the distance d 4  is the minimum distance from the corresponding sidewall of the semiconductor package SM to the corresponding inner sidewall of the central opening OP 1 . The distance d 3  may be substantially equal to the distance d 4 , or may be greater than or smaller than distance d 4 , and this may be adjusted based on design requirements. Furthermore, in certain embodiments, the distance d 3  is smaller than the first width d 1 , while the distance d 4  is smaller than the second width d 2 . 
     In some embodiments, a minimum distance (distance d 3  or distance d 4 ) of the semiconductor package SM to a boundary of the central opening OP 1  is smaller than a maximum distance d 5  from the corners of the semiconductor package SM to a boundary of corner openings OP 2 . In some embodiments, the maximum distance d 5  may extend from the corners of the semiconductor package SM to a region that is slightly larger than the corners of the central openings OP 1 , or to a region that is slightly smaller than a ring foot (outer corners) of the first ring structure RS 1 . In certain embodiments, when the minimum distance of a first sidewall of the semiconductor package SM to an inner sidewall of the first ring structure RS 1  is distance d 3 , a minimum distance of a second sidewall of the semiconductor package SM to an inner sidewall of the first ring structure RS 1  is distance d 4 , then a maximum distance d 5  from a corner of the semiconductor package SM to an inner corner of the first ring structure RS 1  satisfy the following relationship: d 5 &gt;√{square root over ( )}((d 3 ) 2 +(d 4 ) 2 ). In other words, the maximum distance d 5  may be appropriately adjusted as long as it extends over the corners of the central opening OP 1  and does not extend beyond the ring foot (outer corners) of the first ring structure RS 1 . By controlling the dimensions and relative distances of the central opening OP 1  and the corner openings OP 2 , a molding stress in the semiconductor package SM may be significantly reduced. 
     As further illustrated in  FIG. 3B  and  FIG. 3C , in some embodiments the first ring structure RS 1  (first stiffener ring) includes a frame portion RS 1 -A and a plurality of protruding parts RS 1 -B extending out from inner surfaces of the frame portion RS 1 -A towards the semiconductor package SM. For example, the frame portion RS 1 -A is a ring-shaped structure, and the plurality of protruding parts RS 1 -B are separated from one another while being attached to the inner surface of the frame portion RS 1 -A. In certain embodiments, each of the protruding parts RS 1 -B are extending towards the interposer structure  100 ′ of the semiconductor package SM. The design and shape of the frame portion RS 1 -A and the plurality of protruding parts RS 1 -B defines an outline of the central opening OP 1  and corner openings OP 2 . 
     In some embodiments, each of the protruding parts RS 1 -B includes a first side SD 1 , a second side SD 2 , a third side SD 3  and a fourth side SD 4 . For example, the first side SD 1  is joined with the frame portion RS 1 -A. The second side SD 2  is opposite to the first side SD 1 , wherein the second side SD 1  includes a planar surface that is parallel to a side surface SM-SD of the interposer structure  100 ′ (of the semiconductor package SM). Furthermore, the third side SD 3  and the fourth side SD 4  are respectively joining the second side SD 2  to the first side SD 1 . In the exemplary embodiment, the first side SD 1 , the second side SD 2 , the third side SD 3  and the fourth side SD 4  of each of the protruding parts RS 1 -B are joined together to form a rectangular outline. However, the disclosure is not limited thereto, and the outline of the protruding parts RS 1 -B may be adjusted based on design requirements. By designing the first ring structure RS 1  to include the plurality of protruding parts RS 1 -B facing the side surface SM-SD of the interposer structure  100 ′, the molding stress located at corners of the semiconductor package SM may be significantly reduced. 
     Referring to  FIG. 3B  and  FIG. 3D , the second ring structure RS 2  (second stiffener ring) is attached to the first ring structure RS 1  to surround the semiconductor package SM. In some embodiments, the second ring structure RS 2  includes a second central opening OP 3  that is overlapped with the central opening OP 1  of the first ring structure RS 1 . In some embodiments, an outline of the central opening OP 1  of the first ring structure RS 1  is substantially equal to an outline of the second central opening OP 3  of the second ring structure RS 2 . That is, the second central opening OP 3  is a square-shaped or rectangular-shaped opening having four corners (without corner digging). 
     Furthermore, the second ring structure RS 2  includes a second frame portion RS 2 -A with an overlapping part RS 2 -OV and non-overlapping parts RS 2 -NV. For example, the overlapping part RS 2 -OV of the second frame portion RS 2 -A is overlapped with the frame portion RS 1 -A and the plurality of protruding parts RS 1 -B of the first ring structure RS 1 , whereas the non-overlapping parts RS 2 -NV of the second frame portion RS 2 -A are located at four inner corners of the second stiffener ring RS 2 . In some embodiments, the non-overlapping parts RS 2 -NV of the second frame portion RS 2 -A corresponds to a position of the corner openings OP 2  of the first ring structure RS 1 . In some embodiments, the first ring structure RS 1  has a first thickness H 1 , while the second ring structure RS 2  has a second thickness H 2 . In one embodiment, the first thickness H 1  is greater than the second thickness H 2 . For example, a ratio of the first thickness H 1  to the second thickness H 2  may be in a range of 1.1:1 to 1.8:1. However, the disclosure is not limited thereto, and the first thickness H 1  and the second thickness H 2  may be adjusted based on product requirements. In some alternative embodiment, the second thickness H 2  is greater than the first thickness H 1 . 
     In the exemplary embodiment, the first ring structure RS 1  and the second ring structure RS 1  may have a thickness that sums up to be substantially equal to or greater than a height of the semiconductor package SM on the circuit substrate  300 . However, the disclosure is not limited thereto, and their thicknesses may be appropriately adjusted. Furthermore, the first ring structure RS 1  and the second ring structure RS 2  may together serve to reduce the warpage on the circuit substrate  300  caused by bonding of the semiconductor package SM thereto. In addition, the semiconductor package SM will be constrained by the first and second ring structures RS 1 , RS 2  to control the interfacial stress while reducing the internal stress of the semiconductor package SM. Overall, the package structure PKS 1  including the first and second ring structures RS 1 , RS 2  will have improved reliability. 
       FIG. 4  to  FIG. 8  are top views of a first ring structure in accordance with various embodiments of the present disclosure. In various embodiments, the design of the first ring structure RS 1  shown in  FIG. 3C  may be adjusted according to  FIG. 4  to  FIG. 8 , all of these designs can help to reduce a molding stress in the semiconductor package SM. The various designs of the first ring structure RS 1  illustrated in  FIG. 4  to  FIG. 8  may be similar to the first ring structure RS 1  illustrated in  FIG. 3C . Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein. 
     Referring to  FIG. 4 , the difference between the first ring structure RS 1  shown in  FIG. 3C  and the first ring structure RS 1  shown in  FIG. 4  is in the design of the corner openings OP 2 . For example, the corner openings OP 2  of  FIG. 3C  has a first width d 1  that is substantially equal to the second width d 2 . However, the disclosure is not limited thereto. Referring to  FIG. 4 , the first width d 1  may be adjusted to be greater than the second width d 2 . Alternatively, in some other embodiments, the first width d 1  may be adjusted to be smaller than the second width d 2 . In other words, the dimensions of the first width d 1  and the second width d 2  of the corner openings OP 2  may be adjusted based on design requirements. 
     Referring to  FIG. 5 , the difference between the first ring structure RS 1  shown in  FIG. 3C  and the first ring structure RS 1  shown in  FIG. 5  is in the shape of the corner openings OP 2 . For example, as illustrated in  FIG. 5 , the corner openings OP 2  has a polygonal outline. In the exemplary embodiment, corner digging is performed with a hexagonal shaped outline at a position overlapped with the four corners of the central opening OP 1  to form the corner openings OP 2 . In addition, as illustrated in  FIG. 5 , besides having a frame portion RS 1 -A and a plurality of protruding parts RS 1 -B, the first ring structure RS 1  may further include a plurality of corner parts RS 1 -B 2  located at the four corners of the frame portion RS 1 -A, and joined with the frame portion RS 1 -A. In some embodiments, the corner parts RS 1 -B 2  are physically separated from the protruding parts RS 1 -B. 
     Referring to  FIG. 6 , the difference between the first ring structure RS 1  shown in  FIG. 3C  and the first ring structure RS 1  shown in  FIG. 6  is in the shape of the corner openings OP 2 . For example, as illustrated in  FIG. 6 , the corner openings OP 2  has a curved outline. In the exemplary embodiment, corner digging is performed with a circular shaped outline at a position overlapped with the four corners of the central opening OP 1  to form the corner openings OP 2 . Furthermore, as illustrated in  FIG. 6 , in some embodiments, each of the protruding parts RS 1 -B includes the first side SD 1 , the second side SD 2 , the third side SD 3  and the fourth side SD 4 , whereby the third side SD 3  and the fourth side SD have curved surfaces. In some embodiments, besides having a frame portion RS 1 -A and a plurality of protruding parts RS 1 -B, the first ring structure RS 1  may further include a plurality of corner parts RS 1 -B 2  located at the four corners of the frame portion RS 1 -A, and joined with the frame portion RS 1 -A. In some embodiments, the corner parts RS 1 -B 2  are physically separated from the protruding parts RS 1 -B. 
     Referring to  FIG. 7 , the difference between the first ring structure RS 1  shown in  FIG. 3C  and the first ring structure RS 1  shown in  FIG. 7  is in the design of the corner openings OP 2 . For example, as illustrated in  FIG. 7 , the corner openings OP 2  has a polygonal outline. In the exemplary embodiment, corner digging is performed with a squared-shaped outline at approximately 45 degrees angle relative to the first direction DR 1  or the second direction DR 2  (i.e. the square shape is turned 45 degrees during corner digging), at a position overlapped with the four corners of the central opening OP 1  to form the corner openings OP 2 . Furthermore, in some embodiments, each of the protruding parts RS 1 -B includes the first side SD 1 , the second side SD 2 , the third side SD 3  and the fourth side SD 4 , whereby the four sides (SD 1 , SD 2 , SD 3  and SD 4 ) are joined together to form a trapezoidal outline. In addition, in some embodiments, besides having a frame portion RS 1 -A and a plurality of protruding parts RS 1 -B, the first ring structure RS 1  may further include a plurality of corner parts RS 1 -B 2  located at the four corners of the frame portion RS 1 -A, and joined with the frame portion RS 1 -A. In some embodiments, the corner parts RS 1 -B 2  are physically separated from the protruding parts RS 1 -B. 
     Referring to  FIG. 8 , the difference between the first ring structure RS 1  shown in  FIG. 3C  and the first ring structure RS 1  shown in  FIG. 8  is in the number and design of the corner openings OP 2 . As illustrated in  FIG. 8 , the corner openings OP 2  has a square-shaped outline with rounded corners. In the exemplary embodiment, corner digging is performed with a square-shaped outline with rounded corners at a position aligned with the sides of the four corners of the central opening OP 1  to form the plurality of corner openings OP 2 . For example, in the illustrated embodiment, two corner openings OP 2  are extending out from the four corners of the central opening OP 1 . Similar to the previous embodiments, besides having a frame portion RS 1 -A and a plurality of protruding parts RS 1 -B, the first ring structure RS 1  may further include a plurality of corner parts RS 1 -B 2  located at the four corners of the frame portion RS 1 -A, and joined with the frame portion RS 1 -A. In some embodiments, the corner parts RS 1 -B 2  are physically separated from the protruding parts RS 1 -B. 
     Based on the embodiments shown in  FIG. 4  to  FIG. 8 , it is noted that the design of the corner openings OP 2  may be adjusted based on design requirements. For example, various ways of corner digging may be performed to form the corner openings OP 2  with polygonal outline, curved outline, or with irregular outlines. By forming the corning openings OP 2  at corners of the central opening OP 1 , the molding stress in the semiconductor package SM may be significantly reduced. 
       FIG. 9  is a schematic sectional view of a package structure according to some exemplary embodiments of the present disclosure. The package structure PKS 2  illustrated in  FIG. 9  is similar to the package structure PKS 1  illustrated in  FIG. 3B . Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein. The difference between the embodiments is that the semiconductor package SM 2  is used in replacement of the semiconductor package SM in  FIG. 9 . The details of the semiconductor package SM 2  may be referred to the descriptions of  FIG. 2 , thus will not be repeated herein. In the previous embodiments, the various designs of the first ring structure RS 1  are applied to the semiconductor package SM as examples. However, the disclosure is not limited thereto. For example, the various designs of the first ring structure RS 1  may be applied to surround the semiconductor package SM 2  to reduce a molding stress thereof. In some embodiments, the first ring structure RS 1  may surround the redistribution layer RDL and partially surround the insulating encapsulant  114 , while the second ring structure RS 2  may partially surround the insulating encapsulant  114  and the semiconductor dies  21 ,  22 . 
       FIG. 10  is a schematic sectional view of a package structure according to some other exemplary embodiments of the present disclosure. The package structure PKS 3  illustrated in  FIG. 10  is similar to the package structure PKS 1  illustrated in  FIG. 3B . Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein. The difference between the embodiments is that a lid structure  401  is further provided in  FIG. 10 . Referring to  FIG. 10 , in some embodiments, the lid structure  401  may be attached to the second ring structure RS 2  through a third adhesive (not shown). The lid structure  401  may cover the semiconductor package SM, so that the semiconductor package SM is located in between the lid structure  401  and the circuit substrate  300 . In some embodiments, when the lid structure  401  is provided, a thermal interface metal  402  is further attached on a backside of the semiconductor package SM. In certain embodiments, the thermal interface metal  402  is sandwiched in between the lid structure  401  and the semiconductor package SM, and fills up the space therebetween to enhance the heat dissipation. 
     In the above-mentioned embodiments, the package structure includes at least a first ring structure (first stiffener ring) and a second ring structure (second stiffener ring) disposed on the circuit substrate surrounding the semiconductor package. The first ring structure is designed to include central openings and a plurality of corner openings formed by corner digging. By designing the first ring structure in such a way, the molding stress at corners of the semiconductor package may be significantly reduced, while the warpage of the package structure is appropriately controlled. Overall, a risk of molding crack or delamination may be prevented, and the reliability of the package structure may be improved. 
     In accordance with some embodiments of the present disclosure, a package structure includes a circuit substrate, a semiconductor package, and a first ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package. 
     In accordance with some other embodiments of the present disclosure, a package structure includes a circuit substrate, an interposer structure, a first semiconductor die and a plurality of second semiconductor dies, an insulating encapsulant, a first stiffener ring and a second stiffener ring. The interposer structure is disposed on and electrically connected to the circuit substrate. The first semiconductor die and the second semiconductor dies are disposed on a backside surface of the interposer structure and electrically connected to the interposer structure. The insulating encapsulant is disposed on the backside surface of the interposer structure and surrounding the first semiconductor die and the plurality of second semiconductor dies. The first stiffener ring and the second stiffener ring are attached to the circuit substrate, wherein the first stiffener ring is located in between the circuit substrate and the second stiffener ring, and the interposer structure, the first semiconductor die and the plurality of second semiconductor dies are encircled by the first stiffener ring and the second stiffener ring. The first stiffener structure includes a frame portion and a plurality of protruding parts extending out from inner surfaces of the frame portion towards the interposer structure, and each of the plurality of protruding parts are separated from one another. 
     In accordance with some other embodiments of the present disclosure, a package structure including a semiconductor package and a ring structure is provided. The semiconductor package is disposed on a substrate. The ring structure is disposed on the substrate and surrounding the semiconductor package, wherein when a minimum distance of a first sidewall of the semiconductor package to an inner sidewall of the ring structure is d 3 , a minimum distance of a second sidewall of the semiconductor package to an inner sidewall of the ring structure is d 4 , then a maximum distance d 5  from a corner of the semiconductor package to an inner corner of the ring structure satisfy the following relationship: d 5 &gt;√{square root over ( )}((d 3 ) 2 +(d 4 ) 2 ), and the first sidewall is perpendicular to the second sidewall. 
     In accordance with yet another embodiment of the present disclosure, a method of fabricating a package structure is described. The package structure includes the following steps. A circuit substrate is provided. A semiconductor package is disposed on the circuit substrate, and electrically connected to the circuit substrate. A first ring structure is attached to the circuit substrate to surround the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package. A second ring structure is attached to the first ring structure to surround the semiconductor package, wherein the second ring structure comprises a second central opening that is overlapped with the central opening of the first ring structure. 
     Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.