Patent Publication Number: US-7590235-B2

Title: Reduction calculations in elliptic curve cryptography

Description:
The present invention relates to a method of performing a reduction operation and to apparatus for performing a reduction operation. 
     Elliptic Curve Cryptography (ECC) involves the use of calculations on an elliptic curve relationship over GF(p) and requires the multiplication of long integers which are carried out repeatedly during the implementation of, for example, public key algorithms in cryptographic processors. 
     Typically, the multiplication operations must be carried out many hundreds of times to complete an encryption or decryption operation, and so it is important that the cryptographic devices that perform these operations execute the long multiplications quickly using a high speed multiplier. 
     Increasingly, such cryptographic algorithms are used in electronic devices for example smart cards, and in these applications processing capability and power consumption is severely limited. 
     One conventional calculation method is the Quisquater system which operates on the Most Significant Word using the operation
 
 R′=R+ ( −N′*MSW ),
 
     where N′ is a special multiple of N. In fact, −N′ is used in its 2&#39;s complement notation. 
     The reduction operation is inefficient, and the result may be too large, necessitating the addition of (−N′) to R′. 
     Another conventional calculation method is the Mongomery system which operates on the Least Significant Word using the operation
 
 R′=R+N*Q  
 
     where Q=LSW*M mod 2n. 
     Again the reduction operation is inefficient and might be one bit too large requiring restoration by subtraction of N. 
     It is therefore an object of the present invention to provide a more efficient reduction operation. 
     It is also an object of the present invention to provide a reduction operation with a lower number of multiplication operations. 
     It is also an object of the present invention to provide a reduction operation which provides fewer overflows in the calculation operations. 
     It is also an object of the present invention to provide a reduction operation in which the reduction operation is completed faster. 
     According to one aspect, the present invention provides a method of performing a reduction operation in a cryptographic calculation, the method comprising selecting a modulus having a first section with a plurality of “1” Most Significant Word states and a second section which comprises a plurality of “1” or “0” states whereby the number formed of the two sections is a modulus or a multiple of a modulus, and operating a reduction operation on the modulus/multiple. 
     By this selection of a particular form of a modulus/multiple for use in the calculation, the reduction operation involves fewer multiplication operations. 
     Thus a significant benefit provided by the present invention is that the time taken to complete the entire calculating operation is reduced. 
     Moreover, the degree of security afforded by the method of the present invention is maintained as compared to conventional cryptographic methods. 
     Preferably the method comprises monitoring the number of leading “1” to determine if the number is less than (k−2). Advantageously, when the number of leading “1”s is less than (k−2), the next calculation is initiated. 
     Thus a further advantage of the present invention is that a number of multiplication operations can be processed simultaneously, thereby reducing the time taken to complete calculating operations. 
     In one embodiment of the present invention for 192-bit ECC and a word size for 64-bit, the modulus comprises a first section of 138 bits and a second section of 54 bits. 
     In another embodiment of the present invention for 128-bit ECC and a word size of 64-bit, the modulus comprises a first section of 74 bits and a second section of 54 bits. 
     In another embodiment of the present invention for 256-bit ECC and a word size of 64-bit, the modulus comprises a first section of 202 bits and second section of 54 bits. 
     The invention can also work with a number of moduli, which have less significant bits than a multiple of the word size. In that case, the system works with a multiple of the modulus, which has the required number of leading 1&#39;s. Only at the very last end, the result has to be reduced to the original (smaller) modulus. 
     In one preferred arrangement, the method of the present invention utilises modulus, consisting of m words with all the words except the Least Significant Word (LSW) consisting of “1”s and the LSW has, for example, ten leading “1”s can be any number but bearing in mind the larger it is, then the less often an additional reduction is required. 
     According to another aspect, the present invention provides a computer program product directly loadable into the internal memory of a digital computer, comprising software code portions for performing the method of the present invention when said product is run on a computer. 
     According to another aspect, the present invention provides a computer program directly loadable into the internal memory of a digital computer, comprising software code portions for performing the method of the present invention when said program is run on a computer. 
     According to another aspect, the present invention provides a carrier, which may comprise electronic signals, for a computer program embodying the present invention. 
     According to another aspect, the present invention provides electronic distribution of a computer program product, or a computer program, or a carrier of the present invention. 
     According to another aspect, the present invention provides apparatus for performing a reduction operation in a cryptographic calculation, the apparatus comprising means to select a modulus or a multiple of a modulus having a first section with a plurality of “1” states and a second section having a plurality of “1” or “0” states whereby the number formed of the two sections is a modulus or a multiple of a modulus. 
    
    
     
       In order that the present invention may more readily be understood, a description is now given, by way of example only, reference being made to the accompanying drawings, in which: 
         FIG. 1  is an application of the present invention in a smart card; 
         FIG. 2  is a schematic drawing of a reduction operation embodying the present invention for 192-bit ECC and 64-bit words; 
         FIG. 3  is a schematic drawing of another reduction operation of the present invention for 128-bit ECC and 64-bit words; 
         FIG. 4  is a schematic drawing of another reduction operation of the present invention for 256-bit ECC and 64-bit words; 
         FIG. 5  is a hardware implementation of the present invention. 
     
    
    
       FIG. 1  shows a block diagram of a hardware implementation of the present invention incorporating a smart card  50  with the following components:
         Microcontroller  51  for general control to communicate with the outside world via the interface. It sets pointers for data in RAM/ROM and starts the coprocessor.   Interface to the outside world, for contact with smart cards e.g. according to ISO-7816-3.   A Read Only Memory (ROM)  52  for the program of the microcontroller.   A Programmable Read Only Memory (Flash or EEPROM)  53  for the non-volatile storage of data or programs.   RAM  54  for storage of volatile data, e.g for storage of intermediate results during calculations.   Coprocessor  55  dedicated to perform special high-speed tasks for ECC or RSA calculations. When a task is ready, control is returned to the microcontroller.       
     In a variant, the present invention is implemented in software with a microprocessor, ALU to provide add, subtract, shift operations with programming of the controller to provide control logic, and degree detection by shift registers. 
     There is shown in  FIG. 2  a reduction operation of the present invention which is performed with a modulus comprising in total 192 bit words and having a first section which has all “1” states being two 64-bit words and 10 bits. The second section of the modulus is 54 bits and can be any number provided that the total number is a prime. The bigger the number, the less often that an additional reduction is required. 
     In general, N can be written as:
 
 N=n   m-1   B   m-1   + . . . n   1   B+n   0  ( B= 2 64 )
 
     The special requirements for the selection of N are:
         n1 . . . n m-1  are fixed and contain only 1&#39;s (n 1 = . . . n m-1 =B−1).   n 0  is general except for k MSBs which are also 1, leaving 64-k bits free to choose.       

     Then N is written as
 
 N=B   m   −B+n   0   =B   m   −n   0 ′ with  n   0   ′=B−n   0  
 
     Let R be the result, which has to be reduced by 1 word.
 
 R=r   m   B   m   +r   m-1   B   n-1   + . . . r   1   B+r   0  
 
     Reduce the result by subtraction of the product r m N from R as follows:
 
 R′=R−r   m   ·N  
 
=r m   B   m   +r   m-1   B   m-1   + . . . r   1   B+r   0   −r   m ( B   m   −B+n   0 )
 
= r   m-1   B   m-1   + . . . +r   2   B   2   +r   1   B+r   0   +r   m ·( B−n   0 )=( R−r   m   B   m )+ r   m   ·n   0 ′
 
     This means that, for the reduction, omit the word r m  and add to the Least Significant Word r 0  the product r m ·n 0 ′. The reduction implies only one multiplication instead of the normal m multiplications. 
     n 0 ′ is always positive, since n 0 &lt;B. The result is also always positive. 
     Instead of n 0 , store and use n 0 ′. 
     In some cases, the result is 1 bit too large. Then it is necessary to subtract N again.
 
 R′= ( B   m   +r   m-1   B   m-1   + . . . +r   1   B+r   0 )−( B   m   −n   0 ′)= r   m-1   B   m-1   + . . . +r   1   B+ ( r   0   +n   0 ′)=( R−B   m )+n 0 ′.
 
     So, we have only to add n 0 ′ and discard the overflow bit B m . 
     For every multiplication by one word, do such a reduction. Alternatively, do first all multiplications and then the reductions. The last method is described here. The description below is for 192-bit ECC and a 64-bit word size (m=3).
 
 N=B   3   −B+n   0   =B   3   −n   0 ′; 2 9   ≦n   0   &lt;B ( B= 2 64 ).
 
     R is the result of the multiplication of three 64-bit words by also three 64-bit words, which results in 6 words (r 0  . . . r 5 ). 
     Then the reduction is done as follows:
         Multiplication of n 0 ′ by r 4  and adding r 1 (being step S 1 );   Multiplication of n 0 ′ by r 5  and adding r 2 , and the carry c of the previous multiplication. Moreover r 3  is added to the upper part of the multiplication. The result consists of the lower half again called r 2  and the upper half q (step S 2 );   Multiplication of q by n 0 ′ and adding r 0  and adding the new r 1  to the upper part (step S 3 );   When the last multiplication gives an overflow, the overflow is added to r 2  e.g by the multiplication of n 0 ′ by 0 (to give 0), the addition of r 1  (gives r 1  as lower half and the addition of r 2  to the upper part, i.e. the overflow bit) (step S 4 );   When this gives again an overflow (i.e. only when r 2  consists of all-ones (chance 2 −64 )), n 0 ′ is added (step S 5 ).   This can be done by the multiplication of n 0 ′ by 1, and adding r 0  to the lower half of r 1  to the upper half.       

     The carry of the second multiplication (q) is used as multiplicand in the next multiplication, and can be enlarged by 1 bit. 
     When the input r 1  to the multiplication of n 0 ′q does not have 8 leading ones (the probability being less than 1/256), there will be no overflow, since n 0 ′q has at least 8 leading zeros because of n 0 ′. In that case, the program does not wait for the overflow to proceed. 
     Handling of overflows involves time, which has to be minimised wherever possible. Accordingly, n 0  has a number of leading ones (k), so n 0 ′ has at least k−1 leading zeros. 
     Thus, the product n 0 ′c 2  has at least k−2 leading zeros, since q might be enlarged by 1 bit. 
     In order to produce an overflow, the addition of B.c 0 +r 0  has to have at least k−2 leading ones and a carry c from the lower bits. 
     The probability that this will happen is less than 2 −(k-2) . Therefore by making k high, the likelihood of an overflow is very small. 
     The probability of the second overflow is extremely small (2 −64 ), since r 2  has to consist completely of ones. 
     In practice, a pipelined multiplier is used to provide efficient calculation operations, so a number of multiplications are being processed at the same time. It takes a few clock cycles to get the result from the multiplier. When it is necessary to wait to determine whether an overflow occurs, the next multiplications cannot begin until the overflow has been calculated. Thus r 1  is monitored and if it does not have k−2 leading “1”s there will be no overflow a few cycles later so the next multiplication can be started. 
     There is shown in  FIG. 3  a different embodiment for 128-bit ECC and a word size of 64-bit incorporating a modulus N having 128 bits. 
     In this embodiment,
 
 N=B   2   −B+n   0   =B   2   −n   0 ′; 2 9   ≦n   0   &lt;B.  
 
     The operands have to be in normal space. 
     Then the reduction is done as follows:
         Multiplication of n 0 ′ by r 3  and adding r 1 . Also r 2  is added to the upper part of the multiplication (step S 10 ); The result consists of the lower half again called r 1  and the upper half called q.   Multiplication of q by n 0 ′ and adding r 0  and adding the new r 1  to the upper part (step S 11 );   When the last multiplication gives an overflow then we add n 0 ′ (step S 12 ), e.g. by the multiplication/addition n 0 ′·1+B·r 1 +r 0 .       

     There is shown in  FIG. 4  a different embodiment for 256-bit ECC and a word size of 64-bit incorporating a prime number having 256 bits. 
     In this embodiment,
 
 N=B   4   −B+n   0   +B   4   −n   0 ′; 2 9   &lt;n   0   &lt;B.  
 
     The operands have to be in normal space. 
     Then the reduction is done as follows:
         Multiplication of n 0 ′ by r 5  and adding r 1  (being step S 20 ) with the new result called r 1 ;   Multiplication of n 0 ′ by r 6  and adding r 2  and the carry c of the previous multiplication (step S 21 ) with the new result called r 2 .   Multiplication of n 0 ′ by r 7  and adding r 3  and the carry c of the previous multiplication.   Moreover r 4  is added to the upper part of the multiplication (step S 22 ). The step consists of the lower half again called r 3  and the upper half q.   Multiplication of q by n 0 ′ and adding r 0  and adding the new r 1  to the upper part (step S 23 );   When the last multiplication gives an overflow, the overflow is added to r 2  (step S 24 );   When this again gives an overflow, it is added to r 3  (step S 25 );   When this gives again an overflow, n 0 ′ is added (step S 26 ).       

     The carry of the third multiplication (q) is used as multiplicand and in the next multiplication, and can be enlarged by 1 bit. 
       FIG. 5  is a block diagram of a hardware implementation of the present invention having the following components:
         X-, Y-, U- and Z-registers  10  to  13  for storing the input operands X, Y, U and R respectively;   C- and R-register  14 ,  15  for storing outputs C and R;   RAM  16  for storing the intermediate results;   Multiplier  17  which performs the operation B.C+R=X*Y+B*U+Z+c;   State machine  18  which controls the operations and the transport between RAM and registers or between registers.       
     Multiplier  17  calculates the product of X and Y and adds, if required, the previous carry c, which is internally stored. The result is split into two equal parts, Z being added to the lower half and U to the upper half. 
     The output of C-reg  14  can also be directly used as y-input (for example for q in  FIG. 2 ). 
     In another form the present invention is implemented by software running on a microprocessor with appropriate ALU&#39;s to provide add, subtract and shift operations, and shift registers.