Patent Publication Number: US-9906122-B2

Title: Methods to reduce current spikes in capacitive DC-DC converters employing gain-hopping

Description:
RELATED APPLICATIONS 
     This application claims benefit of U.S. Provisional Application No. 61/619,845, filed Apr. 3, 2012, entitled “Methods to Reduce Current Spikes in Capacitive DC-DC Converters Employing Gain-Hopping,” and is related to U.S. application Ser. No. 13/312,879, filed Dec. 6, 2011, entitled “System and Method for Capacitive DC-DC Converter with Variable Input and Output Voltages,” both of which are hereby incorporated by reference for all purposes as if set forth herein in their entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to capacitive DC-DC converters, and more specifically to a system and method to reduce current spikes in capacitive DC-DC converters that employ gain hopping. 
     BACKGROUND OF THE INVENTION 
     Capacitive DC-DC voltage converters are known in the art. Although such voltage converters have known advantages for integrated circuit applications, they also have known disadvantages, such as limited capability to drive high current loads. 
     SUMMARY OF THE INVENTION 
     A capacitive voltage converter providing multiple gain modes comprising a switched capacitor array having a voltage input and a voltage output. A skip gating control coupled to the switched capacitor array and configured to control a switch resistance value of the switched capacitor array, and to control a switching sequence of the switched capacitor array. An override control coupled to the skip gating control and the switched capacitor array, the override control configured to detect transitions in a gain mode and to modify the switch resistance value of the switched capacitor array and the switching sequence of the switched capacitor array for a finite amount of time following the gain mode transition. 
     Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views, and in which: 
         FIG. 1  is a diagram of a system for a capacitive dc-dc converter with variable input and output voltages in accordance with an exemplary embodiment of the present disclosure; 
         FIG. 2  is a diagram showing gain modes as a function of voltage in accordance with an exemplary embodiment of the present disclosure; 
         FIG. 3  is a diagram of a current response and of an efficiency response of a system in accordance with an exemplary embodiment of the present disclosure; 
         FIGS. 4A and 4B  are flow charts of an algorithm for controlling a mode of operation of a DC-DC converter in accordance with an exemplary embodiment of the present disclosure; 
         FIG. 5  is a diagram showing the effect of R SW  on current in accordance with an exemplary embodiment of the present invention; 
         FIG. 6  is a diagram of capacitor configurations for phase transitions in accordance with an exemplary embodiment of the present invention; 
         FIG. 7  is a diagram showing current overshoot and reverse flow conditions that can occur with uncorrected phase transitions; 
         FIG. 8  is a diagram showing current response when applying an override system in accordance with an exemplary embodiment of the present invention; and 
         FIG. 9  is a diagram showing current flow as a function of phase and gain mode in accordance with an exemplary embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the description that follows, like parts are marked throughout the specification and drawings with the same reference numerals. The drawing figures might not be to scale and certain components can be shown in generalized or schematic form and identified by commercial designations in the interest of clarity and conciseness. 
     Capacitive DC-DC converters (“charge-pumps”) are becoming increasingly common for generation of ASIC power supplies at low or moderate current levels. Because they require no external inductive components, they offer an inexpensive bill of materials, a small footprint, and limited electromagnetic interference concerns. 
     A control loop can be used for capacitive DC-DC converters to regulate the charge-pump output voltage. While “skip mode” regulation (which consists in stopping the charge-pump switching activity when the output voltage exceeds the target voltage) and “gain hopping” regulation (which dynamically adjusts charge-pump gain as a function of input voltage, output voltage and loading conditions) are known, skip mode regulation without gain control is very inefficient if the input voltage varies over wide voltage ranges, and gain hopping involves significant power losses at the transitions between low and high gain and is only effective for certain combinations of input and output voltages. 
     Furthermore, because of their pulsed nature, capacitive DC-DC converters tend to generate large spikes on the input and output currents, which can be detrimental to other circuitry in the system by means of ground bounce noise and radiated emissions. While “linear mode” analog loops that continuously modulate the resistance of the charge-pumps switches as a function of the output current can be used to address this problem, it is not known how to combine skip mode (which is used for overall output voltage control and to achieve high-efficiency at light current loads) with gain hopping (which is used for high-efficiency over wide voltage ranges) and with linear mode (which is used for controlling current spikes). 
     Accordingly, a system and method for controlling a DC-DC converter that combines skip mode, gain hopping and switch resistance control is disclosed. A skip comparator stops switching activity in a capacitor array whenever the output voltage exceeds the target voltage plus a small overhead voltage ΔV. In parallel, a hop comparator selects one of two gain modes for the switched cap array: a higher gain that is used when V OUT  is less than V TARGET , and a lower gain that is used when V OUT  is greater than V TARGET . 
     To support an input voltage that can vary over a wide range, more than two gain modes are utilized. In one exemplary embodiment, four gain modes are utilized, namely:
         mode D 0  with a gain=1   mode D 1  with a gain=⅔   mode D 2  with a gain=½   mode D 3  with a gain=⅓       

     Gain selection logic which is based on the outputs of two analog to digital converters representing V IN  and V TARGET  is used to determine which of two gain modes are required. For example, if V IN =3.3 V and V TARGET =1.0V, the charge-pump can operate either in mode D 2  (gain=½) or mode D 3  (gain=⅓). The decision between D 2  and D 3  is a function of the hop signal, as discussed further herein. 
     The current flowing into the charge pump at any given time is proportional to ((G×V IN )−V OUT )/R SW , where G is the charge-pump gain and R SW  is the resistance of the switched capacitor array. While R SW  should be kept sufficiently low in order for the charge-pump to be able to deliver the largest required output current in the worst-case conditions for V IN /V OUT  (such as when ((G×V IN )−V OUT ) is small), under more favorable conditions (such as when ((G×V IN )−V OUT ) is large) a small value of R SW  can cause unnecessarily high current peaks and does not improve the overall power efficiency. 
     In order to reduce current peaks, an “R SW  selection table” is introduced. This table is used to compute ((G×V IN )−V TARGET )) by combining the A/D outputs and gain mode information (D 0 -D 3 ) to select a higher value for the R SW  parameter when possible. R SW  can be modulated in discrete steps by splitting each switch of the capacitor array into an array of smaller switches, each providing a resistance multiple of R SW . 
     Simulations show that the current peaks can be reduced significantly (such as by 3 to 4 times normal) by having eight discrete levels for R SW , with minimal impact to the overall power efficiency. Based on these simulations, finer quantization for R SW  does not appear to be necessary. The selection of the optimal value for R SW  is made by way of a lookup table having V IN , V TARGET , maximum load current that needs to be driven and gain mode as inputs. 
     In most scenarios, switch resistance is not a constant but varies as a function of V IN  in a non-linear manner. In one exemplary embodiment, the switches can be driven much more efficiently (lower resistance) at a higher voltage than at a lower voltage. The dependence of R SW  on V IN  can also be included in the lookup table without any further hardware requirements, as only the content of the lookup table needs to be updated. In this manner, the charge-pump can take full advantage of the lower resistance available at higher V IN  when necessary, while properly scaling the switch resistance up when possible. 
     This exemplary architecture is quite simple and inexpensive in terms of hardware requirements. The skip gating block consists of one AND gate for each switch control signal. The gain selection logic is relatively simple digital combinational logic. The lookup table is quite small in size. For this design, each ADC is 3-bit resolution and the table stores 128×3-bit words. The analog to digital converter (ADC) used for V IN  can be of low resolution, such as a 3-bit ADC, with minimal impact to the overall efficiency curve. A second ADC block connected to V TARGET  is usually unnecessary as the V TARGET  information is already available in digital format for a charge-pump with programmable output voltage. 
     The disclosed SHL mode uses two comparators instead of one in order to decouple the hop control from the skip control. Using one comparator, the charge pump gain is increased as soon as the skip duty ratio exceeds 80% so the charge pumps ends up working in a higher gain setting more frequently than is necessary, which causes a drop in efficiency. Using two comparators allows the charge-pump to stay in skip mode (at a lowest gain setting) even as the duty ratio approaches 100%. In addition, switch resistance control is added to the control loop. An analog feedback loop for switch resistance control is replaced with an open-loop discrete control, to eliminate analog components from the design (filter, variable-resistance switches), and to allow co-existence with gain-hopping. 
       FIG. 1  is a diagram of a system  100  for a capacitive dc-dc converter with variable input and output voltages in accordance with an exemplary embodiment of the present disclosure. System  100  can be implemented in hardware or a suitable combination of hardware and software, and can be one or more software systems operating on a hardware platform. As used herein, “hardware” can include a combination of discrete components, an integrated circuit, an application-specific integrated circuit, a field programmable gate array, or other suitable hardware. As used herein, “software” can include one or more objects, agents, threads, lines of code, subroutines, separate software applications, two or more lines of code or other suitable software structures operating in two or more software applications or on two or more processors, or other suitable software structures. In one exemplary embodiment, software can include one or more lines of code or other suitable software structures operating in a general purpose software application, such as an operating system, and one or more lines of code or other suitable software structures operating in a specific purpose software application. 
     System  100  includes switched capacitor array  102 , which is a suitable combination of series and/or parallel connected switched capacitors that allows the values of the resistance and the topology of the switched-capacitor network to be controllably modified. In one exemplary embodiment, switched capacitor array  102  can be the combination of series and parallel connected switched capacitors shown in  FIG. 4.5  of “Design of High Efficiency Step-Down Switched Capacitor DC/DC Converter,” Mengzhe Ma, Oregon State University (May 21, 2003), which is hereby incorporated by reference, or other suitable switched capacitor arrays. 
     Switched capacitor array  102  receives input voltage V IN  and outputs voltage V OUT . By controlling the gain and resistance of switched capacitor array  102 , the current consumed by switched capacitor array  102  and the efficiency of switched capacitor array  102  can be controlled, so as to minimize the current consumed and to maximize the efficiency. Controls for selecting switches that control the resistance and capacitor settings of switched capacitor array  102  are received from R SW  selection table  104  and skip gating  106 . As discussed above and further herein, R SW  selection table  104  is used to select values of resistance for switched capacitor array  102 , and skip gating  106  is used to control topology and switching activity for switched capacitor array  102   
     R SW  selection table  104  receives inputs representing the target voltage V TARGET  from analog to digital converter  112 , the input voltage V IN  from analog to digital converter  110  and the gain mode control signal from gain selection logic  108 , and generates a resistor selection setting as a function of those inputs. An example of values for R SW  selection table  104  is provided below. The values range from 1 ohm to 8 ohms, and higher resistance values are chosen when V IN  is larger. This exemplary lookup table can be selected when the gain mode is D 3 , with similar tables being used for each of the other gain modes (such as D 0 , D 1  and D 2 ). 
     
       
         
           
               
               
            
               
                   
               
               
                 TARGET 
                 V IN   
               
            
           
           
               
               
               
               
               
               
               
            
               
                 (volts) 
                 &lt;2.8 
                 2.8-3.0 
                 3.0-3.2 
                 3.2-3.4 
                 3.4-3.6 
                 &gt;3.6 
               
               
                   
               
               
                 0.7-0.8 
                 1 Ω 
                 2 Ω 
                 4 Ω 
                 5 Ω 
                 6 Ω 
                 8 Ω 
               
               
                 0.8-0.9 
                 1 Ω 
                 1 Ω 
                 2 Ω 
                 3 Ω 
                 5 Ω 
                 6 Ω 
               
               
                 0.9-1.0 
                 1 Ω 
                 1 Ω 
                 1 Ω 
                 1 Ω 
                 3 Ω 
                 5 Ω 
               
               
                 1.0-1.1 
                 1 Ω 
                 1 Ω 
                 1 Ω 
                 1 Ω 
                 1 Ω 
                 2 Ω 
               
               
                   
               
            
           
         
       
     
     Gain selection logic  108  receives an input representing target voltage V TARGET  from analog to digital converter  112 , an input representing input voltage V IN  from analog to digital converter  110  and the output of comparator  116 , which receives V TARGET  and V OUT  and which generates and output indicative of whether V TARGET  is larger or smaller than V OUT . Gain selection logic  108  outputs a control signal to R SW  selection table  104  and skip gating  106  indicating which gain region the system should be operating in (D 0  through D 3 ). 
     Skip gating  106  receives the output from gain selection logic  108  and a signal from comparator  114 , which compares V OUT  and V TARGET  plus a small overhead voltage ΔV. Capacitor  118  is coupled to the output V OUT  in order to reduce voltage ripple. 
     Override  120  is used to alter the normal switching activity to reduce current spikes. One problem associated with gain-hopping is that the voltage on the fly capacitors has to change as the mode of operation changes. A sudden voltage change results in several problems:
         The presence of large current spikes on the input and output nodes as the fly capacitors are quickly charged/discharged. Current spikes can generate noise on the power/ground lines and impact performance for other components in the system.   A loss of power efficiency as the large current flows through the (resistive) capacitor switches, as power dissipation equals I 2 ×R.   Supply pumping in the case of negative current spikes, as the current is being pushed into the input supply.   EMI (conducted emissions).       

     For instance, when the charge-pump is in D 3 , the steady-state voltage on the fly capacitors is approximately Vin/3. In D 2 , the steady-state voltage on the fly capacitors is V IN /2. Assuming the gain transitions from D 2  to D 3  between PH 2  and PH 1 , as PH 1 -D 3  starts, the two fly capacitors are connected in series and try to drive V OUT  to 0 V. Since the bulk capacitor on V OUT  is already charged to V IN /3, a large current spike will flow out of V OUT  and into V IN  as shown in  FIG. 9 . As shown in  FIG. 9 , when transitioning from state D 2  to state D 3 , it is better to be in phase two to avoid current spikes on V IN . Likewise, in a transition from D 3  to D 2 , it is better to be in phase one. 
     In one exemplary embodiment, override  120  alters the PH 1 -PH 2  switching pattern shown in  FIG. 6  immediately after the gain transition. For instance, one of the two phases can be forced for a certain number of cycles to allow the capacitors to change their voltage in the most favorable state (i.e. avoid drawing currents from the output node), such as by overriding a clock signal that is provided to the capacitor switches for a predetermined number of clock cycles. In another exemplary embodiment, override  120  alters the normal switch resistance immediately after the gain transition. For instance, the switch resistance can be increased for a certain number of clock cycles to reduce the magnitude of the current spikes. 
     In the previous example, when transitioning from D 2  to D 3 , the switch matrix is forced to PH 2  for a predetermined number of clock cycles, such as 4 clock cycles, until the capacitor voltage is close to V DD /3. In addition, the switch resistance can be increased by a suitable amount, such as a factor of 3, for a predetermined number of clock cycles, such as two clock cycles. When normal switching activity resumes, the overshoot and reverse current conditions shown in  FIG. 7  no longer exists. Similar measures can be applied to the D 3 -D 2  transition. The end result is shown in  FIG. 8 , which avoids the overshoot condition through the use of increased switch resistance and which avoids the reverse current conditions by overriding the normal clock operation. 
     The number of clock cycles and the resistance value depends on the gain transition as shown in the table below: 
     
       
         
           
               
               
               
               
             
               
                   
               
               
                   
                 Force 
                 Num of Clk 
                 Switch 
               
               
                 Gain Transition 
                 phase 
                 cycles 
                 resisitance 
               
               
                   
               
             
            
               
                 D0 → D1/D1 → D0 
                 None 
                 0 
                 No change 
               
               
                 D1 → D2 
                 Ph1 
                 2 
                 Increase by a 
               
               
                   
                   
                   
                 factor N1 
               
               
                 D2 → D1 
                 No change 
                 0 
                 No change 
               
               
                 D2 → D3 
                 Ph2 
                 2 
                 Increase by a 
               
               
                   
                   
                   
                 factor N1 
               
               
                 D3 → D2 
                 Ph1 
                 2 
                 Increase by a 
               
               
                   
                   
                   
                 factor N2 
               
               
                   
               
            
           
         
       
     
     To improve the efficiency, for some input voltages and load current, the charge pump (switched capacitor DC-DC converter) is controlled to hop between the minimum gain and a higher gain, so that the charge pump can deliver enough charge to support a large load current at a desired output voltage without significantly reducing the efficiency. The charge pump runs at a lower gain for a few clock cycles, and runs at a higher gain for another few clock cycles. Consequently, the converter keeps hopping between different gains to make the average gain as low as possible to maximize the efficiency. 
     When the charge pump hops between gain configurations, though, there tends to be a difference in amount of voltage across the fly capacitors during the gain transitions. A sudden change in voltage during the first gain transition leads to a spike of current on the capacitor nodes which can cause EMI problems at the input Vin, due to conductive emission. 
     In order to prevent the current spike, the clock signal can be forced high in one of the phases, long enough to pre-charge the fly capacitors to the most appropriate voltage, so that when the next phase arrives, the current spike is lower than cases where the clock signal continues unmodified. 
     In operation, system  100  provides for the combination of a skip mode control for a DC-DC converter (which is used for overall output voltage control and to achieve high-efficiency at light current loads) with gain hopping mode of operation for a DC-DC converter (which is used for high-efficiency over wide voltage ranges) and with a linear mode of operation for a DC-DC converter (which is used for controlling current spikes). System  100  thus provides for improved efficiency and reduced current requirements. 
       FIG. 2  is a diagram  200  showing gain modes as a function of voltage in accordance with an exemplary embodiment of the present disclosure. Diagram  200  shows four exemplary gain modes that can be utilized to improve the efficiency of a DC-DC voltage converter, namely:
         mode D 0  with a gain=1   mode D 1  with a gain=⅔   mode D 2  with a gain=½   mode D 3  with a gain=⅓       

     Gain selection logic  108  is used to determine which of two gain modes are required as a function of the inputs discussed above or other suitable inputs. For example, if V IN =3.3 V and V TARGET =1.0 V, the charge-pump can operate either in mode D 2  (gain=½) or mode D 3  (gain=⅓). The decision between D 2  and D 3  is a function of the hop signal. In the lower portion of a gain region, a hop mode of operation is selected, whereas in the higher portion of a gain region, a skip mode of operation is selected. The mode of operation is automatically selected depending on loading conditions: for example, if the charge-pump can provide the required output current using only gain mode D 3 , it will normally not use gain mode D 2 , thus achieving the highest possible power efficiency. 
       FIG. 3  is a diagram of a current response  300 A and of an efficiency response  300 B of a system such as system  100 , in accordance with an exemplary embodiment of the present disclosure. Current response  300 A increases in magnitude as the efficiency response follows a gain curve downward with increasing input voltage, then reduces in magnitude in the region between gain curves. By controlling the value of the switch resistance R SW  of the switched capacitor bank, the current peak can be maintained at a level that is a factor of two or more less than the current peaks seen in prior art systems. 
       FIGS. 4A and 4B  are flow charts of algorithms  400 A and  400 B for controlling a mode of operation of a DC-DC converter in accordance with an exemplary embodiment of the present disclosure. Algorithms  400 A and  400 B can be implemented in hardware or a suitable combination of hardware and software, and can be one or more software systems operating on a hardware platform. 
     Algorithm  400 A begins at  402 , where a value of V IN  is received and digitized. In one exemplary embodiment, the analog value of V IN  can be received at an analog to digital converter and can be converted into a binary value representing the analog voltage magnitude. The algorithm then proceeds to  406  and  418 . 
     Likewise, at  404 , an analog value of a target output voltage V TARGET  is received and digitized. In one exemplary embodiment, the analog value of V TARGET  can be received at an analog to digital converter and can be converted into a binary value representing the analog voltage magnitude. The algorithm then proceeds to  406  and  418 . 
     At  406 , a gain region is selected, such as based on the value of V IN  or other suitable variables. The algorithm then proceeds to  408 , the output voltage V OUT  is compared to the target voltage V TARGET , such as by providing the voltages as inputs to a comparator and generating an output. If the value of V OUT  is larger than the target voltage V TARGET , then the algorithm proceeds to  412 , where a low gain mode is selected, otherwise, the algorithm proceeds to  410  where a high gain mode is selected. The algorithm then proceeds to  418 , where a switch resistance is selected, and to  414 , where it is determined whether V OUT  is greater than V TARGET  plus a small overhead voltage ΔV. If V OUT  is greater than V TARGET  plus a small overhead voltage ΔV, the algorithm returns to  402  and  404 , otherwise, the algorithm proceeds to  416 , where switching activity is performed. 
     Algorithm  400 B shares common elements with algorithm  400 A, but instead of  408  to  412 , provides  418  to  422  as described herein. At  418 , it is determined whether a gain mode has changed. If the gain mode has not changed, the algorithm proceeds to  414 , otherwise, the algorithm proceeds to  420 , where a normal resistance setting is overridden, and the algorithm then proceeds to  422 , where a normal switching pattern is overridden, such as to maintain a higher resistance value and to prevent a sudden change in capacitance that would result in a current spike, as described in greater detail herein. The algorithm then proceeds to  414 . 
     In operation, algorithms  400 A and  400 B allow a capacitor array in a DC-DC converter to be controlled so as to improve efficiency, reduce current to the capacitor array, and for other suitable purposes. 
       FIG. 5  is a diagram  500  showing the effect of R SW  on current in accordance with an exemplary embodiment of the present invention. The top line ( 502 ) shows an example of the current drawn as a function of voltage when the switch resistance uniformly equals 1 ohm, and the bottom line ( 504 ) shows an example of the current for the same voltage profile when the switch resistance is allowed to vary as described herein. By reducing the current requirements for the capacitor array, the efficiency of the DC-DC converter is improved. 
     It should be emphasized that the above-described embodiments are merely examples of possible implementations. Many variations and modifications may be made to the above-described embodiments without departing from the principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.