Patent Publication Number: US-8994570-B1

Title: Multi-level quantizers and analogue-to-digital converters

Description:
TECHNICAL FIELD 
     Embodiments of the invention relate to multi-level quantizers, and to analogue-to-digital converters. 
     BACKGROUND 
     From seismic monitoring to audio to wireless applications, delta-sigma (DS) analogue-to-digital converters (ADCs) have been widely used due to their relaxed analogue requirements, inherent anti-aliasing filtering and low power consumption. With the widespread use of portable electronic equipment, low-power and low-cost designs become crucially important in many applications. Hence there have been many proposals and novel implementations to improve the with the aim of cost and power-consumption reduction. 
     The quantizers of such ADCs can be implemented in many ways, but usually operate by comparing an analogue signal to a series of references, and then generating an n-bit digital output in accordance with the comparisons. In certain applications a greater number of bits in the quantizer can be desirable for many reasons. 
     One possible implementation uses one or more reference ladders (e.g. a chain of series-connected resistors) to generate a series of voltages at the nodes between the resistors, all separated by a reference voltage equal to the voltage drop across the resistor. 
     In a stable and low-cost industrial design, due to the mismatch between components, the reference ladders may require reference voltages of the order of 50 mV or more, otherwise calibration and trimming may be needed. For a 3-bit output signal, requiring six resistors, such a reference ladder will consume headroom of 300 mV; for a 4-bit output signal, requiring 14 resistors, the reference ladder will consume headroom of 700 mV. 
     The input signal to be quantized may also add to the total voltage swing of the reference ladder, and thus it is clear that output signals having a resolution of 4-bits or greater will be difficult to achieve in low-voltage applications, due to the excess headroom required by the reference ladders. A solution is needed. 
     SUMMARY OF INVENTION 
     According to a first aspect of the invention, there is provided an analogue-to-digital converter, comprising: one or more reference ladders coupled to receive an input signal to be quantized, each reference ladder comprising a plurality of impedances, and a current source providing a reference current through the plurality of impedances, a plurality of nodes being interleaved with the plurality of impedances; a switching arrangement, for coupling and decoupling one or more of the plurality of impedances from the input signal; a plurality of comparators, each comparator coupled to receive signals from respective nodes of the one or more reference ladders, and to provide an output comparison signal; an output, configured to receive the plurality of output comparison signals and to output a quantized signal corresponding to the input signal; and control logic, configured to control the switching arrangement in dependence on the quantized signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the following drawings, in which: 
         FIG. 1  shows a delta-sigma (DS) analogue-to-digital converter (ADC) with a feedback topology according to embodiments of the invention; 
         FIG. 2  shows a conventional implementation of the quantizer in the ADC of  FIG. 1 ; 
         FIG. 3  shows a quantizer according to embodiments of the invention; and 
         FIG. 4  shows a quantizer according to further embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a feedback, third-order DS ADC  10  according to embodiments of the invention. 
     An input  12  receives an analogue input signal V in  which is to be converted to digital. Three integrators  14 ,  16 ,  18  are used in series to successively integrate the combination of the analogue input signal with a respective feedback signal. The output of the third integrator  18  is fed to a quantizer  20 , where it is compared with a series of references in order to generate an n-bit output Out. As previously stated, the n-bit output Out is fed back via a single feedback loop having three output paths, and subtracted from the inputs of each of the integrators  14 ,  16 ,  18 . Digital-to-analogue converters (DACs)  22 ,  24 ,  26  convert the digital signal Out to analogue prior to its subtraction from the inputs of the respective integrators  14 ,  16 ,  18 . It will be appreciated by the skilled person that alternatively a single DAC may be employed in the feedback loop to convert the signal Out to analogue. 
     The quantizer  20  can be implemented in various ways.  FIG. 2  shows one example of a conventional quantizer  20  in which the input is a differential signal having positive and negative components, and also shows a possible implementation of the third integrator  18 . 
     The integrator  18  comprises an opamp OP 3 , with respective capacitors C 3  connected between the positive input and the positive output, and the negative input and the negative output. Each of the integrators  14 ,  16 ,  18  can be implemented in this way, although alternative circuits will be apparent to the skilled person. The outputs of the third integrator  18  are fed to the quantizer  20 . 
     The inputs to the quantizer  20  are labelled in p  for the positive component of the signal, and in n  for the negative component. Both components are buffered in a buffer  22  although this is optional and the components may not be buffered at all. One possible implementation of the buffer  22  includes respective transistors for the positive and negative components of the signal, with those components connected to the gate terminals of the transistors. The drain terminals are connected to a reference voltage (such as ground), and the source terminals are connected respectively to positive and negative reference ladders. 
     The quantizer  20  further comprises positive and negative reference ladders  24 ,  26 , with the positive and negative signal components in p  and in n  being connected to respective ends of the reference ladders  24 ,  26 . The illustrated example generates a 3-bit output signal, and thus each reference ladder comprises a chain of six series-connected resistors, with reference nodes at both ends of the ladders, and between pairs of resistors in the ladder. Nodes p 0  and n 0  are positioned at the start of the reference ladders, and thus the voltages at these nodes are equal to in p  and in n  respectively; nodes p 1  to p 5  and n 1  to n 5  are positioned between the resistors of the positive and negative reference ladders, respectively; and nodes p 6  and n 6  are positioned at the ends of the positive and negative reference ladders, respectively. 
     In the illustrated example, for simplicity, each of the resistors in the reference ladders  24 ,  26  is identical and has the same value of resistance. Those skilled in the art will appreciate, however, that resistors having different resistances could be employed depending on the reference voltages which are required for quantization. Similarly, the illustrated example includes nodes between each consecutive pair of resistors in the ladder. Those skilled in the art will appreciate that in alternative arrangements nodes may be placed only between certain resistors, grouping resistances into identical or different groups to achieve reference voltages as required for quantization. 
     Current sources  28 ,  30  generate a reference current I ref  through the positive reference ladder  24  and the negative reference ladder  26  respectively. Assuming this reference current is constant and the resistors are all identical, the voltages at the respective nodes are as follows: 
                       V     p   ⁢           ⁢   6       =       V   inp     +     6   ⁢           ⁢     U   ref                   V     n   ⁢           ⁢   6       =       V   inn     +     6   ⁢           ⁢     U   ref                       V     p   ⁢           ⁢   5       =       V   inp     +     5   ⁢           ⁢     U   ref                   V     n   ⁢           ⁢   5       =       V   inn     +     5   ⁢           ⁢     U   ref                   …       …               V     p   ⁢           ⁢   0       =     V   inp               V     n   ⁢           ⁢   0       =     V   inn             ,         
where U ref  is the reference voltage drop across each of the resistors as a result of the current I ref .
 
     Note that, in alternative embodiments, the reference ladders may employ capacitors or other impedances instead of resistors in order to generate the reference voltage drop U ref . 
     The quantizer  20  further comprises seven comparators  32   n  which are arranged to compare the voltages at the nodes of the positive and negative reference ladders in order to generate a quantization decision. In the illustrated example, which is a continuous time DS ADC, each comparator is driven to generate an output at a sampling frequency f s . In other examples which are not continuous time, the input signal itself may be latched at a particular sampling frequency. 
     Each comparator  32   n  compares the voltage at one node of the positive reference ladder  24  with the voltage at a corresponding node of the negative reference ladder  26 . In the illustrated example, the nodes are paired such that the voltage at p 6  is compared with the voltage at n 0  in one comparator  32   7 , the voltage at p 5  is compared with the voltage at n 1  in another comparator  32   6 , and so on until the voltage at p 0  is compared with the voltage at n 6  in the final comparator  32   1 . The differential signal V in  is equal to V inp −V inn , and thus the seven comparators  32   1  to  32   7  effectively compare the differential signal V in  with seven different reference voltages:
           32   7 : V in &lt; &gt;+6U ref        32   6 : V in &lt; &gt;+4U ref        32   5 : V in &lt; &gt;+2U ref        32   4 : V in &lt; &gt;0U ref        32   3 : V in &lt; &gt;−2U ref        32   2 : V in &lt; &gt;−4U ref        32   1 : V in &lt; &gt;−6U ref          

     The outputs of the respective comparators  32  are latched, and a digital coder  34  generates a 3-bit output signal on the basis of the seven comparison signals generated by the comparators. 
     As described above, a problem with the quantizer  20  shown in  FIG. 2  is that, depending on the level of the input voltage, the voltage swing at nodes p 6  and n 6  can be very significant indeed. With each resistor in the reference ladder consuming 50 mV for a typical implementation, the 3-bit example illustrated consumes 300 mV of headroom. A 4-bit example would consume 700 mV headroom and a greater number of bits consumes exponentially greater headroom. 
     Embodiments of the invention seek to address this problem by adjusting the reference ladder dynamically to track the input and output signals of the quantizer. 
     In more detail, delta-sigma modulators have an inherently oversampling nature such that the high-frequency output signal tends to track closely the low-frequency input signal. The oversampling ratio (OSR) is defined as the ratio of the sampling frequency to the Nyquist rate of the input bandwidth. The higher the OSR and the greater the number of bits in the output signal, the smoother the tracking between the digital output and the analogue input. Embodiments of the invention thus utilize an OSR which is reasonably high, e.g. 8 or more. In certain embodiments, the OSR may be equal to 10 or more and in other embodiments still the OSR may be equal to 50 or more. The input signal will therefore not have changed drastically from one sample of the output signal to the sample immediately following. Depending on the value of the OSR, the output signal may shift one, two or possibly a few quantization levels in consecutive samples, but is unlikely to have shifted very many quantization levels at once. 
     In order to make a quantization decision, therefore, only certain comparators of the quantizer need to be active at any one time. For example, say the output signal at a sampling interval t n  is equal to +3U ref . To make that decision, only comparators  32   5  and  32   6  need to be active. At the next sampling interval t n+1 , and assuming the OSR is sufficiently high, it can be assumed that the input signal can only have moved up to 5U ref , stayed at +3U ref , or moved down to +1U ref . Thus for the sampling interval t n+1 , comparators  32   1 ,  32   2 ,  32   3  and  32   4  can be deactivated. 
     Further still, if only a subset of the comparators  32  is active for any one sample of the digital output signal, also only a subset of the references in the reference ladders  24 ,  26  is in operation for that sample. According to embodiments of the invention, this principle can be used to reduce the voltage swing at the reference ladders as will be explained below. 
       FIG. 3  shows a quantizer  120  according to embodiments of the invention. Also shown is the third integrator  18 ; this is identical to the component described previously and therefore a similar reference numeral is employed. In general, features which are identical to those described previously are given like reference numerals. 
     The quantizer  120  is substantially identical to the quantizer  20  illustrated in  FIG. 2 , save for some extra features which will now be explained. First and second switching arrangements  125 ,  127  are provided for the positive and negative reference ladders  24 ,  26  respectively, which allow one or more of the resistors in each ladder to be effectively disconnected from the current path between the input signal and from the current sources  28 ,  30 . 
     In the illustrated embodiment, the first switching arrangement  125  provides that node p 1  is connected to node p 6  (i.e. the node at the end of the reference ladder  24 ) via a switch S p1 ; node p 2  is connected to node p 6  via a switch S p2 ; and so on until node p 5  is connected to node p 6  via a switch S p5 . Similarly, the second switching arrangement  127  provides that node n 1  is connected to node n 6  (i.e. the node at the end of the reference ladder  26 ) via a switch S n1 ; node n 2  is connected to node n 6  via a switch S n2 ; and so on until node n 5  is connected to node n 6  via a switch S n5 . 
     Thus, by closing switch S p1 , the reference ladder  24  is effectively shortened to contain only a single resistor between the input signal and the current source  28 ; the remaining resistors are disconnected from the current path. By closing switch S p2  and opening switch S p1 , the reference ladder  24  is effectively shortened to contain only two resistors between the input signal and the current source  28 . The other switches of the first switching arrangement  125  operate in a similar manner to disconnect different resistors from the current path. Thus, by closing any of the switches S p , the effective length of the positive reference ladder  24  can be shortened. The switches S n  of the second switching arrangement  127  can be closed to effectively shorten the negative reference ladder  26  in a similar manner. 
     The quantizer  120  further comprises logic circuitry  136  which receives the quantized output signal Out and generates control signals for the switching arrangements  125 ,  127  as described in more detail below. 
     Let&#39;s assume that V in  is a sine signal applied to the quantizer  120 . At a particular sampling time t n , V in  is around its positive peak. This means that V inp  is around its maximum (and so V p6  is also at its maximum), while V inn  is around its minimum (and V n6  is also around its minimum). Hence it is desirable to reduce the swing of V p6 . 
     It can be observed from the equations above that comparators  32   6  and  32   7  are active to make the quantization decision when V in  is at or near its maximum value, while comparators  32   1  to  32   5  are inactive. Thus the only voltages which are required are those at nodes p 0 , p 1 , n 5  and n 6 . The voltages at nodes p 2  to p 6  are not required. 
     In the next sampling time t n+1 , assuming the OSR is sufficiently high, it can be assumed that V in  will not have changed significantly from its value at t n  and thus the only comparators which will be active are comparators  32   6  and  32   7 . In this situation, switch S p1  can be closed for the sampling interval t n+1 , and thus the logic circuitry  136  generates a suitable control signal. Consequently the highest swing of the positive reference ladder  24  which happens at p 6  goes down from V inp +6U ref  to V inp +U ref ; a drop of 5U ref . 
     If V in  is around its negative peak i.e. V p6  is close to its minimum and V n6  is around its maximum value, the swing of V n6  should be reduced. In this situation, comparators  32   1  and  32   2  are in operation to make the quantization decision while comparators  32   3  to  32   7  are inactive. Hence, only the voltages at nodes n 0 , n 1 , p 5  and p 6  are needed to make a correct decision. Therefore, in a similar manner to that described above, switch S n1  can be closed for the following sampling interval, and thus the logic circuitry  136  generates a suitable control signal. Consequently the highest swing of the negative reference ladder  26  which happens at V n6  is reduced from V inn +6U ref  to V inn +U ref . 
     When the swing of V in  is small, i.e. both V inp  and V inn  are around their mid points, the output of the quantizer  120  can be decided only by comparator  32   4 . Hence, only those voltages at nodes p 3  and n 3  are needed for making the quantization decision and in the subsequent sampling time interval switches S 93  and S n3  can both be closed. The highest swing of the positive reference ladder which happens at V p6  goes down from V inp +6U ref  to V inp +3U ref , while the highest swing of the negative reference ladder which happens at V n6  goes down from V inn +6U ref  to V inn +3U ref . 
     The same algorithm can of course be used by the logic circuitry  136  to control other switches of the switching arrangements  125 ,  127 , depending on the value of a preceding sample of the output signal Out, such that the number of resistors which are connected in each of the reference ladders  24 ,  26  can be varied according to the amplitude of the signal. 
     In general, embodiments of the invention therefore allow fewer nodes to be used in making a quantization decision without compromising on the accuracy of the decision itself. In some embodiments of the invention, the required number of reference voltages may vary depending on how accurate the tracking is between the analogue quantizer input and its digital output. For example, the output of a quantizer using a high OSR and/or having a high number of bits will track the analogue input closely. In that case the control over the number of resistors connected in the reference ladder can be managed at a high level of granularity. If the OSR is low, however, or if the quantizer uses only two bits (for example), the digital output signal may not track the analogue input as closely. In that case the output of the digital signal may change more significantly from one sample to the next, and therefore the control over the number of resistors connected in the reference ladder can be managed at a reduced level of granularity. For example, the switching arrangements  125 ,  127  may not comprise a switch for every node of the reference ladder, or the logic circuitry  136  may control the switches so that only every other switch rather than every switch in the switching arrangement is controlled. 
     The invention has been described with respect to a continuous-time, feedback, third order, 3-bit delta-sigma modulator. However, those skilled in the art will appreciate that the principles described above can be applied within any quantizer utilizing one or more reference ladders, regardless of the number of bits. Further, the quantizer can be employed in any modulator or ADC, not just delta-sigma modulators (whether continuous time or switched capacitor), and in any topology (i.e. feedback, feedforward, hybrid, etc). For example the quantizer can be used in a standalone Flash ADC. 
       FIG. 4  shows the combination of an integrator  218  and a quantizer  220  according to further embodiments of the invention in which the reference ladders are incorporated into the final stage of the final integrator  218 , rather than the quantizer  220  itself. 
     The integrator  218  comprises an opamp OP 3 ′, with respective capacitors C 3  connected between the positive input and the positive output, and the negative input and the negative output. The opamp OP 3 ′ comprises a first amplification stage  240  which receives a differential input signal in n , in p  to be amplified. The positive and negative outputs of the first amplified stage are fed to a final stage. In the illustrated embodiment the final stage comprises two PMOS transistors  242  with the positive and negative components of the signal connected to their respective gate terminals. The source terminals of the respective transistors are connected to a reference voltage (e.g. ground), while the drain terminals of the respective transistors are coupled to respective reference ladders  24 ′,  26 ′ in the same manner as the input signals in n  and in p  are coupled to reference ladders  24 ,  26  in the embodiment described with respect to  FIG. 3 . The reference ladders  24 ′,  26 ′ are thus effectively coupled to receive the input signal to be quantized. First and second switching arrangements  25 ′,  27 ′ are again provided for the positive and negative reference ladders  24 ′,  26 ′ respectively. 
     The quantizer  220  comprises a plurality of comparators  232  which receive the voltages at the nodes of the reference ladders  24 ′,  26 ′, a digital coder  234  for receiving the outputs of the comparators and generated a quantized signal, and logic circuitry  236  which receives the quantized signal and generates control signals in the manner described above, with the exception that the control signals are provided to the switching arrangements  25 ′,  27 ′ in the integrator  218 . Otherwise the circuit operates in the same manner as that described above. 
     Embodiments of the present invention thus provide methods and circuits for converting an analogue input signal to a digital output signal. The circuits employ one or more reference ladders for generating reference voltages with which to compare the analogue signal for quantization. Selected impedances of the reference ladder can be dynamically decoupled from the input signal in dependence on the value of the output signal in order to reduce headroom in the reference ladders, thus making possible accurate quantization in low-voltage applications. 
     Those skilled in the art will appreciate that various amendments and alterations can be made to the embodiments described above without departing from the scope of the invention as defined in the claims appended hereto.