Patent Publication Number: US-2023154868-A1

Title: Semiconductor devices with reinforced substrates

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is a divisional of U.S. patent application Ser. No. 17/013,321, filed Sep. 4, 2020, which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present technology generally relates to semiconductor devices, and more particularly relates to semiconductor devices having substrates with reinforcement structures configured to mitigate thermomechanical stresses. 
     BACKGROUND 
     Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a protective covering. The semiconductor die can include functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the semiconductor die to be connected to higher level circuitry. 
     In some semiconductor assemblies, a packaged semiconductor die can be electrically coupled to a printed circuit board (PCB) via solder bumps arranged in a ball grid array (BGA). However, cyclic heating and/or cooling of the semiconductor package can induce significant thermomechanical stress between the semiconductor package and the PCB due to a mismatch in the coefficients of thermal expansion (CTE) of these components. Often, the stress can induce cracking of the semiconductor package at or near the solder joints, which can render the semiconductor package inoperable. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating clearly the principles of the present technology. 
         FIG.  1 A  is a side cross-sectional view of a semiconductor assembly. 
         FIG.  1 B  is a side cross-sectional view of the semiconductor assembly of  FIG.  1 A  when subjected to thermomechanical stress. 
         FIG.  2 A  is a side-cross sectional view of a semiconductor assembly including a package substrate with reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  2 B  is a side-cross sectional view of another example of a semiconductor assembly including a package substrate with reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  2 C  is a side-cross sectional view of another example of a semiconductor assembly including a package substrate with reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  2 D  is a side-cross sectional view of another example of a semiconductor assembly including a package substrate with reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  2 E  is a side-cross sectional view of another example of a semiconductor assembly including a package substrate with reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  2 F  is a side-cross sectional view of another example of a semiconductor assembly including a package substrate with reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  3 A  is a bottom cross-sectional view of a package substrate including reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  3 B  is a bottom cross-sectional view of another example of a package substrate including reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  3 C  is a bottom cross-sectional view of another example of a package substrate including reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  3 D  is a bottom cross-sectional view of another example of a package substrate including reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  3 E  is a bottom cross-sectional view of another example of a package substrate including reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  3 F  is a bottom cross-sectional view of another example of package substrate including reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  3 G  is a bottom cross-sectional view of another example of package substrate including reinforcement structures configured in accordance with embodiments of the present technology. 
         FIG.  4 A  is a simulated strain energy density map of an array of connectors within the semiconductor assembly of  FIG.  1 B . 
         FIG.  4 B  is a simulated strain energy density map of an array of connectors within the semiconductor assembly of  FIG.  2 A . 
         FIG.  5    is a schematic view of a system that includes a semiconductor device or package configured in accordance with embodiments of the present technology. 
     
    
    
     DETAILED DESCRIPTION 
     Specific details of several embodiments of semiconductor devices, and associated systems and methods, are described below. In some embodiments, for example, a semiconductor device configured in accordance with the present technology includes a substrate coupled to a semiconductor die. The substrate can include a base structure and a reinforcement structure (e.g., a structure formed from a strengthening or stiffening material, such as a metallic material) at least partially embedded in the base structure (e.g., at least partially surrounded by the base structure). The reinforcement structure can be located at least partially within a region associated with the periphery of the semiconductor die referred to herein as “a die shadow region” of the substrate, and it can have a higher stiffness than the base structure. In some embodiments, the geometry, properties, and arrangement of the reinforcement structure reduces or prevents deformation of the substrate at or near the die shadow region, such as warping or bending due to CTE mismatch during cyclic heating and cooling. The reinforcement structures described herein can reduce the amount of thermomechanical stress on the semiconductor device during operation (e.g., on the solder connectors coupling the substrate to a PCB), thus reducing the likelihood of cracking, fatigue, or other mechanical and/or electrical failures. The present technology can improve the reliability and robustness of semiconductor devices, particularly in applications involving temperature and/or power cycling or other harsh field usage conditions such as automotive applications. 
     A person skilled in the relevant art will recognize that suitable stages of the methods described herein can be performed at the wafer level or at the die level. Therefore, depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques. 
     Numerous specific details are disclosed herein to provide a thorough and enabling description of embodiments of the present technology. A person skilled in the art, however, will understand that the technology may have additional embodiments and that the technology may be practiced without several of the details of the embodiments described below with reference to  FIGS.  2 A- 5   . For example, some details of semiconductor devices and/or packages well known in the art have been omitted so as not to obscure the present technology. In general, it should be understood that various other devices and systems in addition to those specific embodiments disclosed herein may be within the scope of the present technology. 
     As used herein, the terms “vertical,” “lateral,” “upper,” “lower,” “above,” and “below” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation. 
       FIG.  1 A  is a side cross-sectional view of a semiconductor assembly  100  (“assembly  100 ”) including a semiconductor package  102  coupled to a PCB  104  via an array of connectors  120  (e.g., a solder BGA). The semiconductor package  102  includes a semiconductor die  108  mounted on a package substrate  110  and encapsulated by a mold material  112 . As can be seen in  FIG.  1 A , the package substrate  110  includes a die shadow region  116  vertically underneath the semiconductor die  108  and at least generally aligned with the peripheral edges of the semiconductor die  108  (e.g., the region of the substrate  110  within the footprint defined by the perimeter of the semiconductor die  108 ). 
       FIG.  1 B  is a side cross-sectional view of the assembly  100  when subjected to thermomechanical stress, e.g., during manufacturing and/or usage. Thermomechanical stresses may be induced, for example, by the assembly process, by thermal cycling and/or thermal shock during component/board level reliability testing, and/or by temperature and/or power cycling during end-customer usage. In some embodiments, the semiconductor package  102  or a component thereof (e.g., the package substrate  110 ) has a CTE that is different than the CTE of the PCB  104 , and the CTE mismatch between these components causes them to deform (e.g., warp, bend) relative to one another during cooling and/or heating of the assembly  100 . For example, as shown in  FIG.  1 B , the semiconductor package  102  and PCB  104  has a warped, non-planar shape after heating and/or cooling. The relative deformation of the semiconductor package  102  and the PCB  104  results in thermomechanical loading of the connectors  120  that leads to fatigue and/or creep failures. For example, as shown in  FIG.  1 B , cracks can form and propagate within the connectors  120  located near or within the die shadow region  116 , particularly connectors  120   a - b  at or near the edges of the die shadow region  116 . Cracks can also form and propagate at the interface between the connectors  120  and the semiconductor package  102  or the PCB  104 , such as in the material of the package substrate  110  and/or the PCB  104 . Once the crack length reaches a critical value, the electrical coupling between the package  102  and the PCB  104  is disrupted, rendering the assembly  100  fully or partially inoperable. This process is accelerated under conditions where the assembly  100  is subject to cyclic loading and/or extreme temperature fluctuations (e.g., in automotive applications). 
       FIG.  2 A  is a side-cross sectional view of a semiconductor assembly  200  having a package substrate with reinforcement structures configured in accordance with embodiments of the present technology. The assembly  200  includes a semiconductor package  202  coupled to a PCB  204  via an array of connectors  220 . The semiconductor package  202  includes a semiconductor die  208 , which can include a semiconductor substrate (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) and various types of semiconductor components and/or functional features, such as memory circuits (e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, or other type of memory circuits), controller circuits (e.g., DRAM controller circuits), logic circuits, processing circuits, circuit elements (e.g., wires, traces, interconnects, transistors, etc.), imaging components, and/or other semiconductor features. Although the illustrated embodiment shows a single semiconductor die  208 , in other embodiments the semiconductor package  202  can include multiple semiconductor dies (e.g., two, four, five, six, seven, eight nine, ten, or more dies) arranged in one or more die stacks. 
     The semiconductor package  202  can also include a package substrate  210  carrying the semiconductor die  208 . The package substrate  210  can include a redistribution structure, an interposer, a printed circuit board, a dielectric spacer, another semiconductor die (e.g., a logic die), or another suitable substrate. In some embodiments, the package substrate  210  includes semiconductor components (e.g., doped silicon wafers or gallium arsenide wafers), nonconductive components (e.g., various ceramic substrates, such as aluminum oxide (Al 2 O 3 ), etc.), aluminum nitride, and/or conductive portions (e.g., interconnecting circuitry, through-silicon vias (TSVs), etc.). The package substrate  210  can be electrically coupled to the semiconductor die  208  via a plurality of interconnectors (e.g., bumps, micro-bumps, pillars, columns, studs, etc.—not shown). 
     The semiconductor package  202  can further include a mold material  212  formed over the package substrate  210  and/or at least partially around the semiconductor die  208 . The mold material  212  can be a resin, epoxy resin, silicone-based material, polyimide, or any other material suitable for encapsulating the semiconductor die  208  and/or at least a portion of the package substrate  210  to protect these components from contaminants and/or physical damage. In some embodiments, the semiconductor package  202  includes other components such as external heatsinks, a casing (e.g., thermally conductive casing), electromagnetic interference (EMI) shielding components, etc. 
     The semiconductor package  202  can be electrically coupled to the PCB  204  via the array of connectors  220  (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxies, and/or other suitable electrically conductive elements). Each connector  220  can electrically couple the package substrate  210  to the PCB  204 , e.g., via respective bond pads on the surfaces of these components (not shown). As a result, the semiconductor die  208  can be electrically coupled to the PCB  204  via the package substrate  210  and connectors  220 . Optionally, the connectors  220  can be surrounded by an underfill material (not shown). 
     The package substrate  210  includes one or more reinforcement structures  230   a  configured with respect to the semiconductor die  208  to reduce or mitigate thermomechanical stresses on the connectors  220 . As discussed above, the connectors  220  located near or underneath a die shadow region  216  may be particularly susceptible to failure due to thermomechanical stress. Accordingly, the reinforcement structures  230   a  can increase the stiffness of the package substrate  210  at or near at least portions of the die shadow region  216  to reduce or prevent bending or other deformation of the package substrate  210 , e.g., during temperature cycling. In the illustrated embodiment, for example, the package substrate  210  includes a base structure  218 , and the reinforcement structures  230   a  are at least partially embedded in and/or at least partially surrounded by the base structure  218 . Each reinforcement structure  230   a  can be located partially or entirely within the die shadow region  216 . For example, the embodiment of  FIG.  2 A  includes two reinforcement structures  230   a  located partially underneath the edges of the semiconductor die  208  and overlapping peripheral edges or boundaries of the die shadow region  216 . In other embodiments, the package substrate  210  can include fewer or more reinforcement structures  230   a  (e.g., one, three, four, five, six, seven, eight, nine, ten, or more), and/or the reinforcement structures  230   a  can be at different locations, as described further below. 
     The reinforcement structures  230   a  can each comprise a material having a high Young&#39;s modulus and/or high CTE, including, but not limited to copper, aluminum, silicon, or other suitable metals or strengthening or stiffening materials. The material of the reinforcement structures  230   a  can have a higher Young&#39;s modulus and/or CTE than the material of base structure  218  of the package substrate  210 . For example, the base structure  218  can be made of any material typically used for semiconductor package substrates, such as a laminate (e.g., epoxy-based laminates, resin-based laminates), polymer (e.g., polyimide), fiber-reinforced material, or combinations thereof. As a result, the reinforcement structures  230   a  can have a greater stiffness than the base structure  218 . For example, the reinforcement structures  230   a  can be at least 2 times, 3 times, 4 times, 5 times, 10 times or 20 times stiffer than the base structure  218 . Stiffer reinforcement structures  230   a  may reduce or inhibit bending or warping of the package substrate  210  during cyclic heating and/or cooling of the semiconductor package  202 , thus reducing thermomechanical loads on the package substrate  210  and/or connectors  220  that may lead to creep, cracking, and/or other mechanical and/or electrical failures. 
     The reinforcement structures  230   a  can have any suitable dimension (e.g., cross-sectional area, width, height, etc.). For example, the reinforcement structures  230   a  can include a height h 1  that is less than the total thickness T 1  of the package substrate  210 . In some embodiments, the height h 1  can be no more than 5%, 10%, 20%, 30%, 40%, or 50% of the thickness T 1 . Optionally, the height h 1  can be within a range from 20% to 30% of the thickness T 1 . The thickness T 1  of the package substrate  210  can be within a range from 100 to 300 microns. In such embodiments, the height h 1  can be no more than 5, 25, 50, 75, 100, 125, or 150 microns. 
     The reinforcement structures  230   a  can be positioned over and/or aligned with one or more connectors  220 . The reinforcement structures  230   a  can have a width w 1  that partially or completely spans one or more connectors  220  (e.g., connectors located adjacent or near the die shadow region  216 , or that are otherwise vulnerable to failure). For example, in the illustrated embodiment, the reinforcement structures  230   a  are positioned over connectors  220   a - b  near a peripheral portion  219  of the die shadow region  216 . In other embodiments, however, some or all of the reinforcement structures  230   a  can be positioned over other connectors  220 , such as one or more connectors  220   c  near a central or interior portion  217  of the die shadow region  216 . 
     In some embodiments, the connectors  220  are arranged in an array having a pitch p, and the width w 1  is within a range from 25% to 200% of the pitch p. For example, the width w 1  can be at least 5%, 10%, 15%, 20%, 25%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, 110%, 120%, 130%, 140%, 150%, 160%, 170%, 180%, 190%, or 200% of the pitch p. As another example, the width w 1  can be no more than 5%, 10%, 15%, 20%, 25%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, 110%, 120%, 130%, 140%, 150%, 160%, 170%, 180%, 190%, or 200% of the pitch p. In some embodiments, the width w 1  can be at least 50, 100, 150, 200, 250, 300, 350, 400, 450 or 500 microns. Alternatively or in combination, the width w 1  can be no more than 50, 100, 150, 200, 250, 300, 350, 400, 450 or 500 microns. 
     As discussed above, the reinforcement structures  230   a  can be at least partially or entirely within the die shadow region  216  of the substrate  210 . The die shadow region  216  can include a central portion  217  and a peripheral portion  219  which surrounds the central portion  217 . The peripheral portion  219  can be located near the edges of the die shadow region  216  and have an outer boundary defined by the perimeter of the semiconductor die  208 , while the central portion  217  can be spaced inwardly from the peripheral portion  219 . In some embodiments, the peripheral portion  219  exhibits more strain under thermomechanical loading than the central portion  217 . Accordingly, the reinforcement structures  230   a  can be localized to the peripheral portion  219  of the die shadow region  216 , such that the central portion  217  only includes the base structure  218  without any reinforcement structures  230   a.  In other embodiments, however, the reinforcement structures  230   a  can extend into the central portion  217  or can be located entirely within the central portion  217 , such the central portion includes both the base structure  218  and the reinforcement structures  230   a.    
     In the illustrated embodiment, the reinforcement structures  230   a  extend laterally outward from the outer boundary of the die shadow region  216  such that the peripheral portion  219  includes only a portion of the reinforcement structures  230   a.  In other embodiments, however, the reinforcement structures  230   a  can be entirely within the die shadow region  216  such that the peripheral portion  219  includes the entirety of the reinforcement structure  230   a.  In the illustrated embodiment, the peripheral portion  219  also includes a portion of the base structure  218  under the reinforcement structures  230   a.  In other embodiments, the peripheral portion  219  can include only the reinforcement structure  230   a  without the base structure  218 . 
     In some embodiments, the peripheral portion  219  has a width w 2 . The width w 2  can be approximately equal to, less than, or greater than the pitch p of the connectors  220 . For example, the width w 2  of the peripheral portion  219  can be approximately 5%, 10%, 15%, 20%, 25%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, 110%, 120%, 130%, 140%, 150%, 160%, 170%, 180%, 190%, or 200% of the pitch p. In a further example, the width w 2  of the peripheral portion  219  can be approximately 50, 100, 150, 200, 250, 300, 350, 400, 450, or 500 microns. 
     The reinforcement structures  230   a  can have any suitable cross-sectional shape. In the illustrated embodiment, for example, the reinforcement structures  230   a  each have a rectangular shape. In other embodiments, some or all of the reinforcement structures  230   a  can have a different cross-sectional shape, such as a circular, square, oblong, oval, rectilinear, elliptical, polygonal, or curvilinear cross-sectional shape, or a combination thereof. Optionally, some or all of the corners of the reinforcement structures  230   a  can be rounded, e.g., to reduce stress concentration. 
     The reinforcement structures  230   a  can be positioned at any suitable vertical location within the package substrate  210 . For example, the package substrate  210  includes an upper surface  210   a  near the semiconductor die  208 , and a lower surface  210   b  opposite the upper surface  210   a  spaced apart from the semiconductor die  208  and near the connectors  220 . In the illustrated embodiment, the reinforcement structures  230   a  are positioned near or at the upper surface  210   a  of the package substrate  210 , and extend partially through the thickness T 1  of the package substrate  210  toward the lower surface  210   b  of the package substrate  210 . In other embodiments, some or all of the reinforcement structures  230   a  can be at a different vertical location within the package substrate  210 , as discussed in greater detail below. In some embodiments, the reinforcement structures  230   a  contact the semiconductor die  208 . In other embodiments, the reinforcement structures  230   a  do not contact the semiconductor die  208  but instead are spaced apart from the semiconductor die  208  (e.g., by a die attach film, interconnectors such as microbumps, underfill material, etc.). 
     The semiconductor assembly  200  can be manufactured in a variety of different ways. For example, the package substrate  210  can be manufactured by forming one or more recesses in the base structure  218 . In some embodiments, each recess is formed by removing a portion of the base structure  218  (e.g., by cutting, drilling, etc.). Alternatively, the base structure  218  can be pre-formed with the recesses. Subsequently, each reinforcement structure  230   a  can be positioned at least partially or entirely in a corresponding recess and secured to the base structure  218  in order to form the package substrate  210  (e.g., by deposition, bonding, laminating, etc.). In some embodiments, each reinforcement structure  230   a  is a pre-formed solid component that is inserted into the recess. In other embodiments, each reinforcement structure  230   a  can be formed in situ within the recess (e.g., by deposition or other processes known to those of skill in the art). The semiconductor die  208  can then be mounted onto the package substrate  210  such that the semiconductor die  208  is positioned at least partially over the reinforcement structures  230   a.  The semiconductor die  208  can include an active or front side  208   a  facing toward the package substrate  210  and a back side  208   b  facing away from the package substrate  210 . In other embodiments, however, the semiconductor die  208  can be mounted with the front side  208   a  facing up and away from the package substrate  210  and the back side  208   b  facing down toward the package substrate  210 . 
       FIGS.  2 B- 2 F  illustrate semiconductor assemblies with various examples of reinforcement structures configured in accordance with embodiments of the present technology. The assemblies shown in  FIGS.  2 B- 2 F  can be generally similar to the assembly  200  described with respect to  FIG.  2 A . Accordingly, like numbers are used to identify similar or identical components, and discussion of the assemblies shown in  FIGS.  2 B- 2 F  will be limited to those features that differ from the assembly  200  of  FIG.  2 A . 
       FIG.  2 B  is a side cross-sectional view of a semiconductor assembly  200   b  including a package substrate  210  with reinforcement structures  230   b  configured in accordance with embodiments of the present technology. The reinforcement structures  230   b  are generally similar to the reinforcement structures  230   a  of  FIG.  2 A , except that a height h 2  of the reinforcement structures  230   b  is greater than or equal to 50% of the thickness T 1 , and less than 100% of the thickness T 1 . In some embodiments, the height h 2  is at least 50%, 60%, 70%, 80%, 90%, or 95% of the thickness T 1  For example, the thickness T 1  of the package substrate  210  can be within a range from 100 to 300 microns, and the height h 2  can be at least 50 microns and less than 300 microns (e.g., greater than or equal to 60, 70, 80, 90 100, 125, 150, 175, 200, 225, 250, or 275 microns). 
       FIG.  2 C  is a side cross-sectional view of a semiconductor assembly  200   c  including a package substrate  210  with reinforcement structures  230   c  configured in accordance with embodiments of the present technology. The reinforcement structures  230   c  are generally similar to the reinforcement structures  230   a  of  FIG.  2 A , except that the reinforcement structures  230   c  extend through the entire thickness T 1  of the package substrate  210  such that a height h 3  of the reinforcement structures  230   c  is equal to or approximately equal to the thickness T 1 . For example, the thickness T 1  of the package substrate  210  can be within a range from 100 to 300 microns, and the height h 3  can be 100, 125, 150, 175, 200, 225, 250, 275 or 300 microns. Further, because the reinforcement structures  230   c  extend through the entire thickness T 1  of the package substrate  210 , the reinforcement structures  230   c  are at or near both the upper surface  210   a  and the lower surface  210   b  of the package substrate  210 . 
       FIG.  2 D  is a side cross-sectional view of a semiconductor assembly  200   d  including a package substrate  210  with reinforcement structures  230   d  configured in accordance with embodiments of the present technology. The reinforcement structures  230   d  are generally similar to the reinforcement structures  230   a  of  FIG.  2 A , except that reinforcement structures  230   d  are located at or near the lower surface  210   b  of the package substrate  210 , rather than the upper surface  210   a.  As previously described with respect to  FIGS.  2 A- 2 C , the height h 4  of the reinforcement structures  230   d  can be less than or equal to 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95% of the thickness T 1  of the package substrate  210 . 
       FIG.  2 E  is a side cross-sectional view of a semiconductor assembly  200   e  including a package substrate  210  with reinforcement structures  230   e  configured in accordance with embodiments of the present technology. The reinforcement structures  230   e  are generally similar to the reinforcement structures  230   a  of  FIG.  2 A , except that the reinforcement structures  230   e  are located between the upper surface  210   a  and lower surface  210   b  of the package substrate  210 , without contacting the upper surface  210   a  and lower surface  210   b.  The reinforcement structures  230   e  are accordingly embedded completely within the package support substrate  210  (i.e., surrounded completely by the material of the package substrate  210 ). The reinforcement structures  230   e  can be spaced apart from the upper surface  210   a  by a first distance d 1 , and can be spaced apart from the lower surface  210   b  by a second distance d 2 . For example, the first distance d 1  and second distance d 2  can each independently be 5, 25, 50, or 100 microns, or any other suitable distance. In some embodiments, the first distance d 1  and second distance d 2  can each independently be no more than 50%, 40%, 30%, 20%, or 10% of the total thickness T 1  of the package substrate  210 . In some embodiments, the first distance d 1  and second distance d 2  are equal or approximately equal. In other embodiments, the first distance d 1  can be greater than the second distance d 2 , or vice-versa. 
     The semiconductor assembly  200   e  can be manufactured in many different ways. In some embodiments, for example, the semiconductor assembly  200   e  is manufactured by forming recesses in a first substrate section (e.g., corresponding to the lower portion of the base structure  218 ) and positioning the reinforcement structures  230   e  into the recesses, e.g., as discussed with above respect to  FIG.  2 A . Subsequently, the package substrate  210  is assembled by coupling a second substrate section (e.g., corresponding to the upper portion of the base structure  218 ) to the first substrate section (e.g., by laminating, bonding), such that the reinforcement structures  230   e  are disposed between the first and second substrate sections. As another example, the package substrate  210  can be assembled from three different substrate sections: a lower substrate section (e.g., corresponding to the lower portion of the base structure  218 ), a middle substrate section (e.g., including the reinforcement structures  230   e  and corresponding to the portion of the base structure  218  adjacent to the reinforcement structures  230   e ), and an upper substrate section (e.g., corresponding to the upper portion of the base structure  218 ). The three substrate sections can be formed separately, then subsequently coupled to each other by laminating, bonding, etc. to form the package substrate  210 . 
       FIG.  2 F  is a side cross-sectional view of a semiconductor assembly  200   f  including a package substrate  210  with reinforcement structures  230   f  configured in accordance with embodiments of the present technology. The reinforcement structures  230   f  are generally similar to the reinforcement structures  230   a  of  FIG.  2 A , except that the reinforcement structures  230   f  protrude above the upper surface  210   a  of the package substrate  210  and separate the semiconductor die  208  from the upper surface  210   a.  The portion of the reinforcement structures  230   f  protruding above the upper surface  210   a  can have a height h 5  of 5, 10, 25, 50, 75, 100, 125, 150, 175, or 200 microns. In some embodiments, the configuration shown in  FIG.  2 F  further reduces deformation of the package substrate  210  due to CTE mismatch by separating the semiconductor die  208  from the package substrate  210 . 
     In the illustrated embodiment, the semiconductor die  208  is oriented with the active side  208   a  facing away from the package substrate  210  and the back side  208   b  facing toward the package substrate  210 . The active side  208   a  of the semiconductor die  208  can be electrically coupled to the package substrate  210  via wire bonds (not shown). In other embodiments, the semiconductor die  208  can be oriented with the active side  208   a  facing toward the package substrate  210  and the back side  208   b  facing away from the package substrate  210 . In such embodiments, the height h 5  can be sufficiently small so that the active side  208   a  can be electrically coupled to the package substrate  210  via interconnectors such as microbumps, pillars, etc. For example, the height h 5  can be less than or equal to 150, 125, 100, 75, 50, 25, 10, or 5 microns. 
       FIG.  3 A  is a bottom cross-sectional view of a package substrate  310  including a reinforcement structure  330   a  configured in accordance with embodiments of the present technology. The package substrate  310  can generally be similar to the package substrate  210  described with respect to  FIGS.  2 A- 2 F . Accordingly, like numbers are used to identify components of the package substrate  310  that are similar or identical to the corresponding components of  FIGS.  2 A- 2 F . For example, the package substrate  310  includes a base structure  318  and a reinforcement structure  330   a  at least partially embedded in the base structure  318 . The reinforcement structure  330   a  can be configured with any suitable layout, geometry (e.g., size, shape), and positioning along and/or within a die shadow region  316  of the package substrate  310 . In the illustrated embodiment, the reinforcement structure  330   a  spans all of the edges and corners of the die shadow region  316 . The reinforcement structure  330   a  can include a central aperture  332  (e.g., a square-shaped aperture) such that the reinforcement structure  330   a  is localized to the peripheral portion of the die shadow region  316  (e.g., along the edges and corners) and does not extend substantially into the central portion of the die shadow region  316 . In some embodiments, the reinforcement structure  330   a  is a single continuous structure embedded in the base structure  318 . In other embodiments, the reinforcement structure  330   a  can include a plurality of individual, discrete structures distributed throughout the die shadow region  316  (e.g., positioned along all the edges and/or corners of the die shadow region  316 ), as discussed in further detail below. 
       FIGS.  3 B- 3 G  illustrate package substrates with various example configurations of reinforcement structures in accordance with embodiments of the present technology. The package substrates shown in  FIGS.  3 B- 3 G  can be generally similar to the package substrate  310  described with respect to  FIG.  3 A . Accordingly, like numbers are used to identify similar or identical components, and description of the package substrates shown in  FIGS.  3 B- 3 G  will be limited to those features that differ from the package substrate  310  of  FIG.  3 A . Moreover, the various features of the package substrates described with respect to  FIGS.  3 A- 3 G  can be combined with each other and/or incorporated in any of the semiconductor assemblies discussed with reference to  FIGS.  2 A- 2 F . 
       FIG.  3 B  is a bottom cross-sectional view of a package substrate  310   b  including reinforcement structures  330   b  configured in accordance with embodiments of the present technology. The reinforcement structures  330   b  are generally similar to the reinforcement structure  330   a  of  FIG.  3 A , except that the reinforcement structures  330   b  are positioned along only some of the edges of the die shadow region  316 . For example, the embodiment of  FIG.  3 B  illustrates two reinforcement structures  330   b  positioned along opposing edges of the die shadow region  316 . Each reinforcement structure  330   b  can have an elongated shape (e.g., a rectangular shape) that spans the entire length of the corresponding edge of the die shadow region  316 . Alternatively, each reinforcement structure  330   b  can span only a portion of the length of the corresponding edge (e.g., 75%, 50%, or 25% of the length of the edge). In other embodiments, the package substrate  310   b  can include the reinforcement structures  330   b  along adjacent edges (e.g., two or three adjacent edges) of the die shadow region  316 . Optionally, the package substrate  310   b  can include fewer or more reinforcement structures  330   b  (e.g., a single reinforcement structure  330   b  positioned along a single edge, three reinforcement structures  330   b  positioned along three edges of the die shadow region  316 ). 
       FIG.  3 C  is a bottom cross-sectional view of a package substrate  310   c  including reinforcement structures  330   c  configured in accordance with embodiments of the present technology. The reinforcement structures  330   c  are generally similar to the reinforcement structure  330   a  of  FIG.  3 A , except that the reinforcement structures  330   c  include multiple structures distributed along the edges and corners of the die shadow region  316 . For example, the embodiment of  FIG.  3 C  illustrates four reinforcement structures  330   c  distributed along each of the four edges of the die shadow region  316  and four reinforcement structures  330   c  at each of the four corners of the die shadow region  316 . In other embodiments, the package substrate  310   c  includes reinforcement structures  330   c  distributed along only some of the edges and/or corners of the die shadow region  316  (e.g., only along three edges, two edges, or a single edge; only at three corners, two corners, or a single corners). Optionally, the package substrate  310   c  can include fewer or more reinforcement structures  330   c  (e.g., one, two, three, four, five, six, seven, eight, nine, ten, or more) distributed along each edge of the die shadow region  316 . In some embodiments, some or all of the reinforcement structures  330   c  at the corners of the die shadow region  316  can be omitted. Each reinforcement structure  330   c  can independently have any suitable shape (e.g., a square or rectangular shape), as discussed further below. 
       FIG.  3 D  is a bottom cross-sectional view of a package substrate  310   d  including reinforcement structures  330   d  configured in accordance with embodiments of the present technology. The reinforcement structures  330   d  are generally similar to the reinforcement structure  330   a  of  FIG.  3 A , except that the reinforcement structures  330   d  are located only at the corners of the die shadow region  316 . For example, the embodiment of  FIG.  3 D  illustrates one reinforcement structure  330   d  located at each of the four corners of the die shadow region  316 . Alternatively, the reinforcement structures  330   d  can be located at three corners, two corners, or a single corner of the die shadow region  316 . In other embodiments, the package substrate  310   d  can include fewer or more reinforcement structures  330   d  (e.g., one, two, three, five, six or more) at each corner of the die shadow region  316 . Each reinforcement structure  330   d  can independently have any suitable shape (e.g., a square or rectangular shape), as discussed further below. 
       FIG.  3 E  is a bottom cross-sectional view of a package substrate  310   e  including reinforcement structures  330   e  configured in accordance with embodiments of the present technology. The reinforcement structures  330   e  are generally similar to the reinforcement structures  330   d  of  FIG.  3 D , except that the reinforcement structures  330   e  have a different cross-sectional shape. For example, the embodiment of  FIG.  3 E  illustrates the reinforcement structures  330   e  as each having a rectangular shape with rounded corners. This configuration can be advantageous for reducing stress concentration at the corners of the reinforcement structures  330   e.    
       FIG.  3 F  is a bottom cross-sectional view of a package substrate  310   f  including reinforcement structures  330   f  configured in accordance with embodiments of the present technology. The reinforcement structures  330   f  are generally similar to the reinforcement structures  330   d  of  FIG.  3 D , except that the reinforcement structures  330   f  have a different cross-sectional shape. For example, the embodiment of  FIG.  3 F  illustrates the reinforcement structures  330   f  as each having a circular shape. 
       FIG.  3 G  is a bottom cross-sectional view of a package substrate  310   g  including a circular or elliptical reinforcement structure  330   g  configured in accordance with embodiments of the present technology. The reinforcement structure  330   g  can overlap some or all of the corners of the die shadow region  316 . Optionally, the reinforcement structure  330   g  can include a central aperture  334  (e.g., a circular or elliptical aperture) such that the reinforcement structure  330   g  is localized to the peripheral portion of the die shadow region  316  and does not extend substantially into the central portion of the die shadow region  316 . The reinforcement structure  330   g  may be advantageous because the circular or elliptical shape is expected to avoid stress concentrations in corners. 
     It will be appreciated that the reinforcement structures  330   a - g  described with respect to  FIGS.  3 A- 3 G  can have any suitable cross-sectional shape (e.g., oblong, oval, elliptical, polygonal, or curvilinear, or a combination thereof). In embodiments where a package substrate includes multiple reinforcement structures, some or all of the reinforcement structures can have the same shape or different shapes. Moreover, some or all of the reinforcement structures can have the same dimensions (e.g., cross-sectional are, height, width, etc.) or different dimensions. The number and configuration of reinforcement structures  330   a - g  can also be varied as desired. 
       FIGS.  4 A and  4 B  illustrate simulated strain energy density maps for connectors in semiconductor assemblies under thermomechanical loading. More specifically,  FIG.  4 A  is a strain energy density map  400   a  of the array of connectors  120  of the assembly  100  of  FIGS.  1 A and  1 B  (which do not include reinforcement structures), and  FIG.  4 B  is a strain energy density map  400   b  of the array of connectors  220  of the assembly  200  of  FIG.  2 A  (which includes reinforcement structures). In  FIGS.  4 A and  4 B , each cell represents a single connector of the respective array. Shaded cells correspond to connectors underneath the respective die shadow regions  402   a - b,  while unshaded cells correspond to connectors outside the die shadow regions  402   a - b.  The numerical value in each cell indicates the amount of strain energy density on the corresponding connector. Strain energy density can correspond to the fatigue life for a connector. For example, a higher strain energy density value can correspond to a lower mean life for the connector. 
     Referring to  FIGS.  4 A and  4 B  together, the maximum strain energy density value for the connectors in  FIG.  4 A  is 0.43 (indicated by bolded values in  FIG.  4 A ), while the maximum strain energy density value for the connectors in  FIG.  4 B  is 0.35 (indicated by bolded value in  FIG.  4 B ), a reduction of approximately 20%. The simulation results shown in  FIGS.  4 A and  4 B  demonstrate that the reinforcement structures described herein can reduce the amount of strain on connectors underneath the die shadow region, which may improve the fatigue life of the connector and/or reduce the likelihood of failure. 
     Any one of the semiconductor devices and/or packages having the features described above with reference to  FIGS.  2 A- 4 B  can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system  500  shown schematically in  FIG.  5   . The system  500  can include a processor  502 , a memory  504  (e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices  506 , and/or other subsystems or components  508 . The semiconductor dies and/or packages described above with reference to  FIGS.  2 A- 4 B  can be included in any of the elements shown in  FIG.  5   . The resulting system  500  can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system  500  include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system  500  include lights, cameras, vehicles, etc. With regard to these and other example, the system  500  can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system  500  can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media. 
     From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Accordingly, the invention is not limited except as by the appended claims. Furthermore, certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.