Patent Publication Number: US-5633941-A

Title: Centrally controlled voice synthesizer

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a centrally controlled voice synthesizer, and more particularly to one which mangages the memory therein in a centralized manner thus optimizing the finite memory. 
     2. Description of the Prior Art 
     A voice synthesizer is a device which is used to duplicate voice including melody and/or speech and emits the voice duplication from a speaker connected thereto. Normally the voice duplication emitted from the synthesizer is composed of a plurality of &#34;sections&#34; each of which comprises a plurality of &#34;words&#34;. FIG. 5 illustrates a plurality of words as labeled WORD(1), WORD(2), . . . , WORD(N). Each word comprises a plurality of data bits. For example, WORD(1) comprises a plurality of data bits such as DATA(1), DATA(2), . . . , DATA(K1). Each word is deemed as a small unit of a voice and may be one or several syllables of a voice. FIG. 6 illustrates a conventional voice synthesizer which comprises a voice-controlled circuit 90 connected to a voice memory 91, an address memory 92, a control memory 93, a timing circuit 94, a decoder 95, and an input circuit 96. The voice memory 91 has its output connected to a digital-to-analog (D/A) converter 97 which is connected to a speaker 98. A code selection circuit 99 is connected between the input circuit 96 and the decoder 95. The voice memory 91 stores voice data. The address memory 92 stores a beginning address and an end address for each word. The control memory 93 stores silent data and a terminating signal for each &#34;section&#34; of the voice. The code selection circuit 99 is used to deal with input/output signals. From the above, it is understood that the control data and voice data are dispersedly stored in the code selection circuit 99, the address memory 92, the control memory 93, and the voice memory 91. This dispersed arrangement of the memories 91, 92, and 93 results in complicated wiring and software programming thus increasing inconvenience and cost. 
     The present invention has arisen to mitigate and/or obviate the afore-described disadvantages of the conventional voice synthesizer. 
     SUMMARY OF THE INVENTION 
     The primary objective of the present invention is to provide a voice synthesizer which provides an optimal arrangement in the memory thus simplifying the wiring and software on the memory. 
     In accordance with one aspect of the invention, there is provided a centrally controlled voice synthesizer comprising a memory which is preprogrammed with voice data, address data, and control data; 
     an input processor for receiving an external signal and outputting a triggering signal; 
     a clock generator for generating clock signals; 
     a control logic unit receiving the clock signal from the clock generator, being triggered by the triggering signal from the input processor thus fetching the voice data, the address data, and the control signal from the memory; 
     a decoder decodes the data fetched from the memory via the logic control unit and generates a control signal; 
     a rhythm generator for outputting a rhythm signal to the logic control unit upon receiving the clock signal from the clock generator and the control signal from the decoder; 
     a digital-to-analog converter connected to the memory and converts digital voice data from the memory to an analog voice signal; and 
     a transistor connected to the digital-to-analog converter for amplifying the analog voice signal and driving an external speaker to emit corresponding voice. 
     Further objectives and advantages of the present invention will become apparent from a careful reading of the detailed description provided hereinbelow, with appropriate reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram in accordance with the present invention; 
     FIG. 2 is a hierarchy structure of memory management of the voice synthesizer of the present invention; 
     FIG. 3 is a state processing flow chart of a control logic unit in accordance with the present invention; 
     FIG. 4 is flow chart for reading the hierarchy voice data of the present invention; 
     FIG. 5 is an example for defining the voice data used in the voice synthesizer; and 
     FIG. 6 is a conventional circuit block diagram of a voice synthesizer. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a voice synthesizer in accordance with the present invention comprises a control logic unit 10 functioning as a control center, a memory 20, an input processor 30, a decoder 40, a rhythm generator 50, and a timing circuit 60. The memory 20 has an output terminal thereof connected to a digital-to-analog (D/A) converter which is connected to a speaker 22 via a transistor 23. The speaker 22 emits voice duplication according to voice data outputted from the output terminal of the memory 20. 
     The control logic unit 10 reads control code from a heading of the memory 20 upon receiving a triggering signal from the input processor 30 and then forwards the read control code to be decoded in the decoder 40 from which a control signal is outputted in response to the control code read from the heading of the memory 20. 
     The memory 20 has defined a hierarchy structure of data for simultaneously storing voice data, melody data, address data, and control signal. The detailed of the hierarchy structure of data will be described in detail later. 
     The input processor 30 receives an input signal sent thereto and generates a triggering signal in response to the control signal from the decoder 40. 
     The decoder 40 decodes the data read from the memory via the control logic unit 10 and generates a control signal. 
     The rhythm generator 50 generates a timing control signal for controlling the melody signal emitted from the memory 20. 
     The digital-to-analog converter 21 converts the voice data, which is digital form, to analog voice signal by which the speaker 22 is driven to emit the corresponding sound. 
     The timing circuit 60 generates a timing signal and forwards the timing signal to the control logical unit 10 and the rhythm generator 50. 
     From the above discussion, it can be summarized that the logic control unit 10 reads the hierarchy voice data from the memory 20; the decoder 40 decodes the hierarchy voice data from the memory 20 and provides a control signal to the input processor 30, the input processor 30 which cooperates with the inputted signal and outputs a control signal to the control logic unit 10 thus enabling operation of the whole system. 
     FIG. 2 illustrates the hierarchy structure of the voice data in the memory 20. The arrangement of the memory 20 is substantially classified into three types which are section heading 70, word heading 71, and word data table 72. The section heading 70 includes heading address data (HAD) 701, voice or melody data (VMD) 702, triggering type data 703, and output control data (OCD) 704. The word heading 71 includes heading address data (HAD) 711, output control data (OCD) 712, rhythm setting data (RSD) 713, and end of section data (EOS) 714. The word data table 72 includes a plurality of data units 721 such as DATA(1), DATA(2), . . . , DATA(n), and an end of word data (EOW) 722. Each data unit 721 may contains four, five, six or seven data bits depending on an encoding manner. 
     FIGS. 3 and 4 should be referred together for easy understanding data accessing on the memory 20. FIG. 3 is a state processing flow chart of the control logic unit 10 and FIG. 4 is a detailed flow chart for reading the hierarchy voice data in the memory according to the flow chart of FIG. 3. The input processor 30 outputs a triggering signal to trigger the control logic unit 10 upon receiving an external trigger signal. The control logic unit 10 remains in a &#34;STAND-BY&#34; state 31 when it is not trigged by the input processor 30. The control logic unit 10 changes to an &#34;S&#34; state upon receiving the triggering signal from the input processor 30. The control logic unit 10 reads the section heading 70, fetching the control code and a heading address 701 of a first voice word in the memory 20, and forwarding the control code to the decoder 40. The decoder outputs a control signal according to the control code, and in the meantime the control logic unit 10 changes from the &#34;S&#34; state to a &#34;W&#34; state. The control logic unit 10 reads from a word heading 71 of a first word and fetches the corresponding control code and the heading address 711 of the first word, thereafter the decoder 40 receives the control code and outputs a corresponding control signal, and in the meantime the control logic unit 10 changes from the &#34;W&#34; state to a &#34;T&#34; state. 
     In the &#34;T&#34; state, the data units 721 in the memory 20 are read by the logic control unit 10 unit by unit and are forwarded to the digital-to-analog converter 21 until the end of word EOW 722 is read. 
     The logic control unit 10 may remain in the &#34;T&#34; state 34 or change to the &#34;W&#34; state 33, or the &#34;S&#34; state 32, or the &#34;STAND-BY&#34; state 31 according to some conditions as will be discussed as follows. A path 34 is defined from the &#34;T&#34; state 34 to itself when the read data unit 721 is not equal to the &#34;end of word&#34; data unit 722. A path 33 is defined from the &#34;T&#34; state to the &#34;W&#34; state when the read data unit 721 is equal to the &#34;end of word&#34; data unit 722, and the &#34;end of section&#34; flag EOS is equal to &#34;0&#34;. A path 32 is defined from the &#34;T&#34; state to the &#34;S&#34; state when the read data unit 721 is equal to the &#34;end of word&#34; data unit 722, the &#34;end of section&#34; flag EOS is equal to &#34;1&#34;, and the control logic unit 10 is still triggered by the input processor 30. A path 31 is defined from the &#34;T&#34; state to the &#34;STAND-BY&#34; state when the read data unit 721 is equal to the &#34;end of word&#34; data unit 722, the &#34;end of section&#34; flag EOS is equal to &#34;1&#34;, and the control logic unit 10 is not triggered by the input processor 30. 
     The control logic unit 10 continuously reads hierarchy voice data from the memory 20 according to the above mentioned flow chart and conditions thus optimizing the memory 20. 
     While the present invention has been explained in relation to its preferred embodiment, it is to be understood that various modifications thereof will be apparent to those skilled in the art upon reading this specification. Therefore, it is to be understood that the invention disclosed herein is intended to cover all such modifications as fall within the scope of the appended claims.