Patent Publication Number: US-7224009-B2

Title: Method for forming a low leakage contact in a CMOS imager

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   The present application is a divisional of U.S. Ser. No. 10/637,529 filed Aug. 11, 2003 U.S. Pat. No. 6,927,090 which is a divisional of U.S. Ser. No. 09/207,593 filed Dec. 8, 1998 U.S. Pat. No. 6,639,261. The subject matter of both patent applications are incorporated in their entirety by reference herein. 

   FIELD OF THE INVENTION 
   The invention relates generally to improved semiconductor imaging devices and in particular to a silicon imaging device which can be fabricated using a standard CMOS process. Particularly, the invention relates to CMOS imager having a doped polysilicon contact from a diffusion node to a gate of a source follower transistor. 
   DISCUSSION OF RELATED ART 
   There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays. CCDs are often employed for image acquisition and enjoy a number of advantages which makes it the incumbent technology, particularly for small size imaging applications. CCDs are also capable of large formats with small pixel size and they employ low noise charge domain processing techniques. However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there has been some attempts to integrate on-chip signal processing with the CCD array, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer which also results in image smear. 
   Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television. 
   The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD since standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost. 
   A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, a photodiode, or a photoconductor overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photodiode, or photoconductor having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference. 
   In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate or a photoconductor. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout. 
   CMOS imagers of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12) pp. 2046–2050, 1996; Mendis et al, “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452–453, 1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515, which are herein incorporated by reference. 
   To provide context for the invention, an exemplary CMOS imaging circuit is described below with reference to  FIG. 1 . The circuit described below, for example, includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate. It should be understood that the CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge. 
   Reference is now made to  FIG. 1  which shows a simplified circuit for a pixel of an exemplary CMOS imager using a photogate and having a pixel photodetector circuit  14  and a readout circuit  60 . It should be understood that while  FIG. 1  shows the circuitry for operation of a single pixel, that in practical use there will be an M×N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below. 
   The photodetector circuit  14  is shown in part as a cross-sectional view of a semiconductor substrate  16  typically a p-type silicon, having a surface well of p-type material  20 . An optional layer  18  of p-type material may be used if desired, but is not required. Substrate  16  may be formed of, for example, Si, SiGe, Ge, and GaAs. Typically the entire substrate  16  is p-type doped silicon substrate and may contain a surface p-well  20  (with layer  18  omitted), but many other options are possible, such as, for example p on p− substrates, p on p+ substrates, p-wells in n-type substrates or the like. The terms wafer or substrate used in the description includes any semiconductor-based structure having an exposed surface in which to form the circuit structure used in the invention. Wafer and substrate are to be understood as including, silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation. 
   An insulating layer  22  such as, for example, silicon dioxide is formed on the upper surface of p-well  20 . The p-type layer may be a p-well formed in substrate  16 . A photogate  24  thin enough to pass radiant energy or of a material which passes radiant energy is formed on the insulating layer  22 . The photogate  24  receives an applied control signal PG which causes the initial accumulation of pixel charges in n+ region  26 . The n+ type region  26 , adjacent one side of photogate  24 , is formed in the upper surface of p-well  20 . A transfer gate  28  is formed on insulating layer  22  between n+ type region  26  and a second n+ type region  30  formed in p-well  20 . The n+ regions  26  and  30  and transfer gate  28  form a charge transfer transistor  29  which is controlled by a transfer signal TX. The n+ region  30  is typically called a floating diffusion region. It is also a node for passing charge accumulated thereat to the gate of a source follower transistor  36  described below. A reset gate  32  is also formed on insulating layer  22  adjacent and between n+ type region  30  and another n+ region  34  which is also formed in p-well  20 . The reset gate  32  and n+ regions  30  and  34  form a reset transistor  31  which is controlled by a reset signal RST. The n+ type region  34  is coupled to voltage source VDD. The transfer and reset transistors  29 ,  31  are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. It should be understood that it is possible to implement a CMOS imager in an n-well in which case each of the transistors would be p-channel transistors. It should also be noted that while  FIG. 1  shows the use of a transfer gate  28  and associated transistor  29 , this structure provides advantages, but is not required. 
   Photodetector circuit  14  also includes two additional n-channel transistors, source follower transistor  36  and row select transistor  38 . Transistors  36 ,  38  are coupled in series, source to drain, with the source of transistor  36  also coupled over lead  40  to voltage source VDD and the drain of transistor  38  coupled to a lead  42 . The drain of row select transistor  38  is connected via conductor  42  to the drains of similar row select transistors for other pixels in a given pixel row. A load transistor  39  is also coupled between the drain of transistor  38  and a voltage source VSS. Transistor  39  is kept on by a signal VLN applied to its gate. 
   The imager includes a readout circuit  60  which includes a signal sample and hold (S/H) circuit including a S/H n-channel field effect transistor  62  and a signal storage capacitor  64  connected to the source follower transistor  36  through row transistor  38 . The other side of the capacitor  64  is connected to a source voltage VSS. The upper side of the capacitor  64  is also connected to the gate of a p-channel output transistor  66 . The drain of the output transistor  66  is connected through a column select transistor  68  to a signal sample output node VOUTS and through a load transistor  70  to the voltage supply VDD. A signal called “signal sample and hold” (SHS) briefly turns on the S/H transistor  62  after the charge accumulated beneath the photogate electrode  24  has been transferred to the floating diffusion node  30  and from there to the source follower transistor  36  and through row select transistor  38  to line  42 , so that the capacitor  64  stores a voltage representing the amount of charge previously accumulated beneath the photogate electrode  24 . 
   The readout circuit  60  also includes a reset sample and hold (S/H) circuit including a S/H transistor  72  and a signal storage capacitor  74  connected through the S/H transistor  72  and through the row select transistor  38  to the source of the source follower transistor  36 . The other side of the capacitor  74  is connected to the source voltage VSS. The upper side of the capacitor  74  is also connected to the gate of a p-channel output transistor  76 . The drain of the output transistor  76  is connected through a p-channel column select transistor  78  to a reset sample output node VOUTR and through a load transistor  80  to the supply voltage VDD. A signal called “reset sample and hold” (SHR) briefly turns on the S/H transistor  72  immediately after the reset signal RST has caused reset transistor  31  to turn on and reset the potential of the floating diffusion node  30 , so that the capacitor  74  stores the voltage to which the floating diffusion node  30  has been reset. 
   The readout circuit  60  provides correlated sampling of the potential of the floating diffusion node  30 , first of the reset charge applied to node  30  by reset transistor  31  and then of the stored charge from the photogate  24 . The two samplings of the diffusion node  30  charges produce respective output voltages VOUTR and VOUTS of the readout circuit  60 . These voltages are then subtracted (VOUTS−VOUTR) by subtractor  82  to provide an output signal terminal  81  which is an image signal independent of pixel to pixel variations caused by fabrication variations in the reset voltage transistor  31  which might cause pixel to pixel variations in the output signal. 
     FIG. 2  illustrates a block diagram for a CMOS imager having a pixel array  200  with each pixel cell being constructed in the manner shown by element  14  of  FIG. 1 .  FIG. 4  shows a 2×2 portion of pixel array  200 . Pixel array  200  comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array  200  are all turned on at the same time by a row select line, e.g., line  86 , and the pixels of each column are selectively output by a column select line, e.g., line  42 . A plurality of rows and column lines are provided for the entire array  200 . The row lines are selectively activated by the row driver  210  in response to row address decoder  220  and the column select lines are selectively activated by the column driver  260  in response to column address decoder  270 . Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit  250  which controls address decoders  220 ,  270  for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry  210 ,  260  which apply driving voltage to the drive transistors of the selected row and column lines. 
     FIG. 3  shows a simplified timing diagram for the signals used to transfer charge out of photodetector circuit  14  of the  FIG. 1  CMOS imager. The photogate signal PG is nominally set to 5V and the reset signal RST is nominally set at 2.5V. As can be seen from the figure, the process is begun at time t 0  by briefly pulsing reset voltage RST to 5V. The RST voltage, which is applied to the gate  32  of reset transistor  31 , causes transistor  31  to turn on and the floating diffusion node  30  to charge to the VDD voltage present at n+ region  34  (less the voltage drop Vth of transistor  31 ). This resets the floating diffusion node  30  to a predetermined voltage (VDD−Vth). The charge on floating diffusion node  30  is applied to the gate of the source follower transistor  36  to control the current passing through transistor  38 , which has been turned on by a row select (ROW) signal, and load transistor  39 . This current is translated into a voltage on line  42  which is next sampled by providing a SHR signal to the S/H transistor  72  which charges capacitor  74  with the source follower transistor output voltage on line  42  representing the reset charge present at floating diffusion node  30 . The PG signal is next pulsed to 0 volts, causing charge to be collected in n+ region  26 . A transfer gate voltage TX, similar to the reset pulse RST, is then applied to transfer gate  28  of transistor  29  to cause the charge in n+ region  26  to transfer to floating diffusion node  30 . It should be understood that for the case of a photogate, the transfer gate voltage TX may be pulsed or held to a fixed DC potential. For the implementation of a photodiode with a transfer gate, the transfer gate voltage TX must be pulsed. The new output voltage on line  42  generated by source follower transistor  36  current is then sampled onto capacitor  64  by enabling the sample and hold switch  62  by signal SHS. The column select signal is next applied to transistors  68  and  70  and the respective charges stored in capacitors  64  and  74  are subtracted in subtractor  82  to provide a pixel output signal at terminal  81 . 
   The operation of the charge collection of the CMOS imager is known in the art and is described in several publications such as Mendis et al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19–29 1994; Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol. 32(2), 1997; and Eric R, Fossum, “CMOS Image Sensors: Electronic Camera on a Chip,” IEDM Vol. 95 pages 17–25 (1995) as well as other publications. These references are incorporated herein by reference. 
   Prior CMOS imagers suffer from several drawbacks regarding the charge flow and contact between the floating diffusion area  30  and the source follower transistor  36 . For example, tungsten metal, which is typically used to contact the floating diffusion region and the source follower transistor, is deposited with tungsten fluoride and a reaction sometimes takes place between the tungsten fluoride and the substrate resulting in the formation of silicon fluoride which creates worm holes in the substrate. These worm holes create a conductive channel for current to leak into the substrate, creating a poor performance for the imager. Since the size of the pixel electrical signal is very small due to the collection of photons in the photo array, the signal to noise ratio of the pixel should be as high as possible within a pixel. Thus, leakage into the substrate is a significant problem to be avoided in CMOS imagers. 
   Conventional floating diffusion regions also typically have a highly n+ doped region to facilitate an ohmic metal-semiconductor contact between the contact metallization and the underlying n-doped silicon region to achieve charge transfer to the source follower transistor  36 . However, this same highly doped n+ region  30  creates current leakage into the substrate due to high electric fields caused by the abrupt junction. Also, typically there must be an over etch of the contact to account for non-uniformities across the wafer and non-uniformity of an insulating layer thickness. Accordingly, resistance in the conductive path between the floating diffusion region and gate of the source follower transistor should be as low as possible without resulting in added junction leakage. 
   Several of the above-described drawbacks can be seen from  FIGS. 5–8  which show a side view of several CMOS imagers of the prior art. It should be understood that similar reference numbers correspond to similar elements for  FIGS. 5–7 . Reference is now made to  FIG. 5 . This figure shows the region between the floating diffusion and the source follower transistor of a prior CMOS imager having a photogate as the photoactive area and which further includes a transfer gate. The imager  100  is provided with three doped regions  143 ,  126  and  115 , which are doped to a conductivity type different from that of the substrate, for exemplary purposes regions  143 ,  126  and  115  are treated as n type, which are within a p-well of a substrate. The first doped region  143  is the photosite charge collector, and it underlies a portion of the photogate  142 , which is a thin layer of material transparent or partially transparent to radiant energy, such as polysilicon, indium-tin oxide or tin oxide. An insulating layer  140  of silicon dioxide, silicon nitride, or other suitable material is formed over a surface of the doped layer  143  of the substrate between the photogate  142  and first doped region  143 . 
   The second doped region  126  transfers charge collected by the photogate  142  and it serves as the source for the transfer transistor  128 . The transfer transistor  128  includes a transfer gate  139  formed over a gate oxide layer  140 . The transfer gate  139  has insulating spacers  149  formed on its sides. 
   The third doped region  115  is the floating diffusion region and is connected to a gate  136  of a source follower transistor by contact lines  125 ,  127 ,  129  which are typically metal contact lines as described in more detail below. The imager  100  typically includes a highly n+ doped region  120  within n-doped region  115  under the floating diffusion region contact  125  which provides good ohmic contact of the contact  125  with the n-doped region  115 . The floating diffusion contact  125  connects n+ region  120  of the floating diffusion region with the gate  136  of the source follower transistor. In other embodiments of the prior art, the entire region  115  may be doped n+ thereby eliminating the need for n+ region  120 . 
   The source and drain regions of the source follower transistor are not seen in  FIG. 5  as they are perpendicular to the page but are on either side of gate  136 . The source follower gate  136  is usually formed of a doped polysilicon which may be silicided and which is deposited over a gate oxide  140 , such as silicon dioxide. The floating diffusion contact  125  is usually formed of a tungsten plug typically a Ti/TiN/W metallization stack as described in further detail with respect to  FIG. 8 . The floating diffusion contact  125  is formed in an insulating layer  135  which is typically an undoped oxide followed by the deposition of a doped oxide such as a BPSG layer  135  deposited over the substrate. The tungsten metal which forms the floating diffusion/source follower contact  125  is typically deposited by CVD using a tungsten fluoride such as WF 6 . 
   Typically, the layer  135  must be etched with a selective dry etch process prior to depositing the tungsten plug connector  125 . The imager  100  also includes a source follower contact  127  formed in layer  135  in a similar fashion to floating diffusion contact  125 . Source follower contact  127  is also usually formed of a tungsten plug typically a Ti/TiN/W metallization stack as described in further detail below. The floating diffusion contact  125  and the source follower contact  127  are connected by a metal layer  129  formed over layer  135 . Typically metal layer  129  is formed of aluminum, copper, tungsten or any other metal. 
   Separating the source follower transistor gate  136  and the floating diffusion region  115  is a field oxide layer  132 , which serves to surround and isolate the cells. The field oxide  132  may be formed by thermal oxidation of the substrate using the Local Oxidation of Silicon (LOCOS) or by the Shallow Trench Isolation (STI) process which involve the chemical vapor deposition of an oxide material. 
   It should be understood that while  FIG. 5  shows an imager having a photogate as the photoactive area and additionally includes a transfer transistor, additional CMOS imager structures are also well known. For example, CMOS imagers having a photodiode or a photoconductor as the photoactive area are known. Additionally, while a transfer transistor has some advantages as described above, it is not required. Accordingly, the  FIG. 5  structure is not limiting of the environment of the invention but is only used to illustrate the problem to be solved by the invention. 
   The prior art metal contacts  125 ,  127  described with reference to  FIG. 5  typically include a thin layer  123  formed of titanium, titanium nitride or a mixture thereof formed in the etched space in the layer  135 . A tungsten plug  122  is then filled in the etched space in the layer  135  inside the thin layer  123 . The contact  125  contacts n+ region  120  and forms a TiSi 2  area  121  by a reaction between the titanium from layer  123  with the silicon substrate in n+ region  120 . 
   Reference is now made to  FIG. 6 . This figure illustrates an enlarged and partially cut away side view of a semiconductor imager undergoing a processing method according to the prior art. The imager  104  has the floating diffusion region  115  having an n+ doped region  120  and the source follower transistor gate  136  already formed therein. The floating diffusion  115  and the source follower gate  136  are under layer  135 , which, as noted, is preferably composed of oxides, typically a layered structure of an undoped and doped, i.e., BPSG, oxides. A resist  155  is applied to layer  135  in order to etch through layer  135  to form the contacts to the floating diffusion region  115  and the source follower transistor gate  136 . Layer  135  is then etched to form the hole  156  in layer  135  for the floating diffusion contact  125  and hole  157  in layer  135  for the source follower transistor contact  127  as shown in  FIG. 7 . However, as can be seen from  FIG. 7 , since the field oxide  132  and layer  135  are both similar oxides it is difficult to control the etching process when attempting to align the hole  156  with the edge of the field oxide  132 . In fact, the etching process often etches deep into the n+ region  120  or etches through the exposed edge of the field oxide  132  causing charge leakage to the substrate as shown by the arrows in  FIG. 7 . Etching deep into the n+ region  120  results in poor contact resistance to the n+ region  120 . Etching through the n+ region  120  or through the exposed region of the filed oxide  132  can result in charge leakage to the substrate. 
   Reference is now made to  FIG. 8 . This figure illustrates the floating diffusion contact  125  between the floating diffusion region  115  and the metal layer  129  which are illustrated in  FIGS. 5–7 . It should be understood that while  FIG. 8  shows a typical connection between the floating diffusion  115  and the metal layer  129 , the source follower contact  127  deposited in an etched hole in layer  135  is formed of similar materials. The contact includes a thin layer  123  formed of titanium, titanium nitride or a mixture thereof formed in the etched space in the layer  135 . A tungsten plug  122  is then filled in the etched space in the layer  135  inside the thin layer  123 . The contact  125  contacts n+ region  120  and forms a TiSi 2  area  121  by a reaction between the titanium from layer  123  with the silicon substrate in n+ region  120 . 
   The devices described with reference to  FIGS. 5–8  have several drawbacks. For example, during etching, caution must be taken to avoid etching through the n+ layer  120  or even deep into n-doped region  115  where the n-type dopant concentration is reduced. Additionally, when the tungsten metal is deposited by CVD using tungsten fluoride, a reaction sometimes takes place between the tungsten fluoride and the substrate resulting in the formation of silicon fluoride which creates worm holes through the n+ region  120  and into the substrate. These worm holes may create a channel for current to leak into the substrate, creating a poor performance for the imager. While Ti/TiN barrier layers are deposited to form a good ohmic contact to the n+ region due to the TiSi2 reaction and provide a TiN barrier between the W metallization and the Si substrate, worm holes and contact leakage still occur. Also, the prior art floating diffusion region  115  included the highly n+ region  120  to provide an ohmic contact; however, this same highly doped n+ region sets up high electric fields with respect to the p-type region under field oxide region  132  which fosters current leakage into the substrate. Accordingly, a better low resistance conductive path is required between region  120  and gate  136  of the source follower transistor which provides a good ohmic contact, while avoiding substrate leakage. 
   SUMMARY OF THE INVENTION 
   The present invention provides a CMOS imager in which the floating diffusion is connected to a gate of the source follower transistor by a doped polysilicon contact. The doped polysilicon contact provides a better ohmic contact with less leakage into the substrate. The present invention also provides doped polysilicon plugs to connect the floating diffusion and the gate of the source follower transistor by a metal interconnector formed over a BPSG layer. The doped polysilicon contact between the floating diffusion region and the gate of the source follower transistor also allows the floating diffusion region and the source follower transistor to be placed closer together, thereby reducing size of a pixel and allowing an increased photo area per cell size which, it turn, increases the signal to noise ratio of the imager. In addition, the problems with worm holes and connecting of the floating diffusion contact are completely avoided as there is no need for the highly doped n+ region  120  in the present invention and additionally no need for any metallization to be directly in contact with the silicon substrate at the floating diffusion node. 
   The above and other advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a representative circuit of a CMOS imager. 
       FIG. 2  is a block diagram of a CMOS active pixel sensor chip. 
       FIG. 3  is a representative timing diagram for the CMOS imager. 
       FIG. 4  is a representative pixel layout showing a 2×2 pixel layout according to one embodiment of the present invention. 
       FIG. 5  is a partially cut away side view of a semiconductor imager having a photogate and a transfer gate according to the prior art. 
       FIG. 6  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to the prior art. 
       FIG. 7  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to the prior art subsequent to  FIG. 6 . 
       FIG. 8  is an enlarged view of a floating diffusion contact according to the prior art. 
       FIG. 9  shows a partially cut away side view of a semiconductor imager of a first embodiment of the present invention at an intermediate step of processing. 
       FIG. 10  shows a partially cut away side view of a semiconductor imager of the present invention subsequent to  FIG. 9 . 
       FIG. 11  shows a partially cut away side view of a semiconductor imager of the present invention subsequent to  FIG. 10 . 
       FIG. 12  shows a partially cut away side view of a semiconductor imager of the present invention subsequent to  FIG. 11 . 
       FIG. 13  shows a partially cut away side view of a semiconductor imager of the present invention subsequent to  FIG. 12 . 
       FIG. 14  shows a partially cut away side view of a semiconductor imager of the present invention subsequent to  FIG. 13 . 
       FIG. 15  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to a second embodiment the present invention. 
       FIG. 16  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to a second embodiment the present invention subsequent to  FIG. 15 . 
       FIG. 17  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to a second embodiment the present invention subsequent to  FIG. 16 . 
       FIG. 18  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to a second embodiment the present invention subsequent to  FIG. 17 . 
       FIG. 19  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to a second embodiment the present invention subsequent to  FIG. 18 . 
       FIG. 20  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to a second embodiment the present invention subsequent to  FIG. 19 . 
       FIG. 21  shows a partially cut away side view of a semiconductor imager undergoing a processing method according to a second embodiment the present invention subsequent to  FIG. 20 . 
       FIG. 22  is an illustration of a computer system having a CMOS imager according to the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. 
   The terms “wafer” and “substrate” are to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium arsenide. 
   The term “pixel” refers to a picture element unit cell containing a photosensor and transistors for converting electromagnetic radiation to an electrical signal. For purposes of illustration, a representative pixel is illustrated in the figures and description herein, and typically fabrication of all pixels in an imager will proceed simultaneously in a similar fashion. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
   The invention is now described with reference to  FIGS. 9–22 .  FIG. 9  shows a partially cut away cross-sectional view of a CMOS semiconductor wafer similar to that shown in  FIG. 1 . It should be understood that similar reference numbers correspond to similar elements for  FIGS. 9–21 .  FIG. 9  shows the region between the floating diffusion and the source follower transistor for an imager having a photodiode as the photosensitive area and which does not include a transfer gate. As with  FIG. 5  above, the source follower transistor source and drain regions are in a plane perpendicular to  FIG. 9 . The pixel cell  300  includes a substrate which includes a p-type well  311  formed in a substrate. The pixel cell  300  includes an n-doped region  315  which forms the floating diffusion region. It should be understood that the CMOS imager of the present invention can also be fabricated using p-doped regions in an n-well. 
   The pixel cell  300  also includes a field oxide regions  332 , which may be formed by thermal oxidation of the substrate using the LOCOS process or by the STI process which involve the chemical vapor deposition of an oxide material. The field oxide regions  332  form an isolation around the source follower transistor area  330 . 
   The pixel cell  300  includes an oxide or other insulating film  318  deposited on the substrate by conventional methods. Preferably the oxide film  318  is formed of a silicon dioxide grown onto the substrate. Doped region  352  is formed in the substrate as shown in  FIG. 9  in the area that will later become the photodiode  350 . It should be understood that the regions  315  and  352  may be doped to the same or different dopant concentration levels. Additionally, while two separate doped regions are shown in the figure, a single doped region may incorporate both regions  315  and  352 . There may be other dopant implantations applied to the wafer at this stage of processing such as n-well and p-well implants or transistor voltage adjusting implants. For simplicity, these other implants are not shown in the figure. 
   A doped polysilicon layer  320  is next deposited over the pixel cell  300  and patterned using resist and etching methods. The doped polysilicon layer  320  is deposited according to conventional methods. The doped polysilicon layer  320  will form the gate for the source follower transistor. The gate also includes sidewall insulating spacers  356 , all as shown in  FIG. 10 . 
   An insulating layer  360  is deposited and planarized as shown in  FIG. 11 . The layer  360  may include materials such as BPSG, PSG, BSG or the like. A resist layer  355  is applied to the pixel cell over insulating layer  360  as shown in  FIG. 12 . A space in the resist layer  355  is provided which is aligned over n-doped region  315  and a space in the resist layer  355  is also provided over source follower transistor gate  320 . The insulating layer  360  and insulating layer  318  over the n-doped region  315  are then etched as shown in  FIG. 13 . The insulating layer over the source follower transistor gate  320  is also etched as shown. 
   A doped polysilicon layer  340  is then deposited in the holes etched in the insulating layer  360  to connect the n-doped region  315  and the source follower transistor gate  320  as shown in  FIG. 14 . The doped polysilicon layer  340  may also be formed of a composite layered structure of doped polysilicon/refractory metal silicide or doped polysilicon/refractory metal silicide/insulator for improved conductivity. Preferably the refractory metal silicide is a tungsten, cobalt, or titanium silicide. The layered structure could also be a layered structure of polysilcon/barrier metal/metal where the barrier metal is Ti/TiN, TaNx, TiN, MoNx, or WNx and where the metal is W, Ta or Mo. 
   The n-type dopant from in the doped polysilicon layer  340  diffuses out of the doped polysilicon and into n-doped region  315  to form contact region  325 . Contact region  325  forms a good low leakage damage free contact to n-doped region  315 . It is also possible to add an n-type dopant implant into the silicon prior to polysilicon deposition to improve leakage and contact resistance. 
   After the processing to produce the imager shown in  FIG. 14 , the pixel cell  300  of the present invention is then processed according to known methods to produce an operative imaging device. For example, a passivation layer may be applied and planarized and contact holes etched therein to form conductor paths to transistor gates, etc. The passivation layer may include materials such as BPSG, PSG, BSG or the like. Conventional metal and insulation layers are formed over the passivation layer and in the through holes to interconnect various parts of the circuitry in a manner similar to that used in the prior art ( FIG. 5 ) to form the floating diffusion region to source follower gate connection. Additional insulating and passivation layers may also be applied. The imager is fabricated to arrive at an operational apparatus that functions generally similar to the imager depicted in  FIGS. 1–4  although it should be understood that  FIG. 14  differs from the imagers shown in  FIGS. 1–4  in that  FIG. 14  includes a photodiode as the photocollection device as opposed to the photogate  24  illustrated in  FIG. 1 . Additionally,  FIG. 1  shows an optional transfer gate  28  which, as discussed above, is not needed, nor illustrated, with respect to the imager depicted in  FIG. 14 . 
   The doped polysilicon contact between the floating diffusion region  315  and the source follower transistor gate  320  provides a good contact between the floating diffusion region  315  and the source follower transistor gate  320  without using processing techniques which might cause charge leakage to the substrate during device operation. The doped polysilicon contact also allows the source follower transistor to be placed closer to the floating diffusion region thereby allowing for an increased photosensitive area on the pixel and short conductor between the floating diffusion region and gate of the source follower transistor which increases the signal to noise ratio of the imager. 
   Reference is now made to  FIGS. 15–21  which illustrate a partially cut away side view of a semiconductor imager undergoing a processing method according to a second embodiment of the present invention. It should be understood that like reference numbers represent like elements through the figures. Reference is first made to  FIG. 15 . The pixel cell  301  includes a substrate which includes a p-type well  311  formed in a substrate and an n-doped region  315  which forms the floating diffusion region. It should be understood that the CMOS imager of the present invention can also be fabricated using p-doped regions in an n-well. The pixel cell  301  also includes a field oxide regions  332 , which may be formed by thermal oxidation of the substrate using the LOCOS process or by the STI process which involve the chemical vapor deposition of an oxide material as set forth above with reference to  FIG. 9 . The pixel cell  301  includes an oxide or other insulating film  318  deposited on the substrate by conventional methods, preferably a silicon dioxide grown onto the substrate  311 . Doped region  352  is formed in the substrate as shown in  FIG. 15  in the area that will later become the photodiode  350 . As set forth above, regions  315  and  352  may be doped to the same or different dopant concentration levels or a single doped region may incorporate both regions  315  and  352 . There may be other dopant implantations applied to the wafer at this stage of processing such as n-well and p-well implants or transistor voltage adjusting implants. For simplicity, these other implants are not shown in the figure. 
   A doped polysilicon layer  320  is next deposited over the pixel cell  300  and patterned using resist and etching methods. The doped polysilicon layer  320  is deposited according to conventional methods. The doped polysilicon layer  320  will form the gate for the source follower transistor. The gate also includes sidewall insulating spacers  356  to arrive at the structure shown in  FIG. 16 . 
   An insulating layer  360  is deposited and planarized as shown in  FIG. 17 . The layer  360  may include materials such as BPSG, PSG, BSG or the like. A resist layer  355  is applied to the pixel cell over insulating layer  360  as shown in  FIG. 18 . A space in the resist layer  355  is provided which is aligned over n-doped region  315  and a space in the resist layer  355  is also provided over source follower transistor gate  320 . The insulating layer  360  and insulating layer  318  over the n-doped region  315  are then etched as shown in  FIG. 19 . The insulating layer over the source follower transistor gate  320  is also etched as shown. 
   A doped polysilicon layer is then deposited in the holes etched in the insulating layer  360  to connect the n-doped region  315  and the source follower transistor gate  320 . The doped polysilicon layer is then removed from over the insulating layer  360  by chemical mechanical planarization or dry etch to provide doped polysilicon plugs  341  as shown in  FIG. 20 . The doped polysilicon plugs  341  may also be formed of a composite layered structure of doped polysilicon/refractory metal silicide or doped polysilicon/refractory metal silicide/insulator for improved conductivity, or titanium silicide. Preferably the refractory metal silicide is a tungsten, titanium or cobalt silicide. 
   The n-type dopant from in the doped polysilicon plugs  341  diffuses out of the doped polysilicon and into n-doped region  315  to form contact region  325 . Contact region  325  forms a good low leakage damage free contact to n-doped region  315 . It is also possible to add an n-type dopant implant into the silicon prior to polysilicon deposition to improve leakage and contact resistance. 
   A metal layer is then deposited over the insulating layer  360  to form a metal interconnector  370 . The metal interconnector  370  serves to electrically connect doped polysilicon plugs  341 , thereby connecting the floating diffusion region  315  and the gate  320  of the source follower transistor. The metal interconnector is deposited according to conventional methods. Preferably the metal interconnector is deposited by physical vapor deposition or sputtering or CVD. The metal interconnector  370  may be formed of any conductive metal. Preferably the metal interconnector  370  is formed of Ti/TiN/W, Ti/Al—Cu, Ti/Al—Cu/TiN, Ti/TiN/Al—Cu/TiN, Ti/TiN/Cu, TiN/Cu or TaN/Cu. 
   After the processing to produce the imager shown in  FIG. 21 , the pixel cell  301  of the present invention is then processed according to known methods to produce an operative imaging device. For example, a passivation layer may be applied and planarized and contact holes etched therein to form conductor paths to transistor gates, etc. The passivation layer may include materials such as BPSG, PSG, BSG or the like. Conventional metal and insulation layers are formed over the passivation layer and in the through holes to interconnect various parts of the circuitry in a manner similar to that used in the prior art to form the floating diffusion region to source follower gate connection. Additional insulating and passivation layers may also be applied. The imager is fabricated to arrive at an operational apparatus that functions similar to the imager depicted in  FIGS. 1–4  as it should be understood that  FIG. 21  differs from the imagers shown in  FIGS. 1–4  as  FIG. 21  includes a photodiode as the photocollection device as opposed to the photogate  24  illustrated in  FIG. 1 . Additionally,  FIG. 1  shows an optional transfer gate  28  which, as discussed above, is not needed, nor illustrated, with respect to the imager depicted in  FIG. 21 . 
   The doped polysilicon plugs  341  together with the metal interconnector  370  provide a good contact between the floating diffusion region  315  and the source follower transistor gate  320  without using processing techniques which might cause charge leakage to the substrate during device operation. The doped polysilicon plugs  341  together with the metal interconnector  370  also allow the source follower transistor to be placed closer to the floating diffusion region thereby allowing for an increased photosensitive area on the pixel and short conductor between the floating diffusion region and gate of the source follower transistor which increases the signal to noise ratio of the imager. 
   A typical processor based system which includes a CMOS imager device according to the present invention is illustrated generally at  500  in FIG.  22 . A processor based system is exemplary of a system having digital circuits which could include CMOS imager devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system and data compression system for high-definition television, all of which can utilize the present invention. 
   A processor based system, such as a computer system, for example generally comprises a central processing unit (CPU)  544 , for example, a microprocessor, that communicates with an input/output (I/O) device  546  over a bus  552 . The CMOS imager  542  also communicates with the system over bus  452 . The computer system  500  also includes random access memory (RAM)  548 , and, in the case of a computer system may include peripheral devices such as a floppy disk drive  554  and a compact disk (CD) ROM drive  556  which also communicate with CPU  544  over the bus  552 . CMOS imager  542  is preferably constructed as an integrated circuit which includes the CMOS imager having a buried contact line between the floating diffusion region and the source follower transistor, as previously described with respect to  FIGS. 9–21 . It may also be desirable to integrate the processor  554 , CMOS imager  542  and memory  548  on a single IC chip. 
   It should again be noted that although the invention has been described with specific reference to CMOS imaging circuits having a photogate and a floating diffusion, the invention has broader applicability and may be used in any CMOS imaging apparatus. For example, the CMOS imager array can be formed on a single chip together with the logic or the logic and array may be formed on separate IC chips. Additionally, while the figures describe the invention with respect to a photodiode type of CMOS imager, any type of photocollection devices such as photogates, photoconductors or the like may find use in the present invention. Similarly, the process described above are but two methods of many that could be used. Accordingly, the above description and accompanying drawings are only illustrative of preferred embodiments which can achieve the features and advantages of the present invention. It is not intended that the invention be limited to the embodiments shown and described in detail herein. The invention is only limited by the scope of the following claims.