Patent Publication Number: US-5424936-A

Title: Boost-input backed-up uninterrupted power supply

Description:
BACKGROUND 
     This invention relates to the field of uninterruptable power supplies that are powered from single or multi-phase power from electrical mains ac service. The uninterruptable power supply provides single or multi-phase ac electrical service to a load without substantial interruption in the event of short term interruption of the mains ac service. 
     RELATED ART 
     The &#34;Uninterruptable Power Supplies&#34; described in U.S. Pat. No. 5,126,585, issued Jun. 30, 1992 to J. T. Boys teaches the use of &#34;a reversible rectifiers connected between an AC supply and a high voltage internal DC bus,&#34; and a second reversible rectifier interconnecting storage batteries to the high voltage DC bus . . . &#34;. The reversible rectifier may be the means &#34;for reversibly converting an incoming alternating current at first AC voltage into a direct current . . . &#34; The object of the invention by Boys is to provide an output load with an ac voltage service while reflecting a unity power factor back to the ac voltage service providing power to its input. According to the Boys reference, the reversible rectifier is of a type that the instantaneous current consumption of the Boys UPS mimics a pure resistance causing minimal harmonic pollution of the utility supply. 
     Unlike the Boys UPS, the subject invention uses a conventional rectifier input and increases the reflected power factor to near unity. The topology of the Boys UPS shows the use of two pairs of switches in separate pairs. The first pair operates within a first reversible rectifier to source power from the input ac voltage source as ac current to a +dc voltage bus and -dc voltage bus. The peak operating voltage of each of these dc busses is maintained above the peak swing of the ac voltage source providing power to the Boys UPS. The second reversible rectifier sources power from a 210 volt storage battery stack to the +dc bus and the -dc bus in the event of loss of ac voltage from the input power source. 
     The subject invention uses a pair of boost converters, each boost converter using a single switch. Each boost converter is either powered from a respected+unregulated bus or an unregulated bus formed at the output of a full bridge input rectifier or from a source selected battery source in the event of loss of input ac voltage. The output of each boost regulator provides power to a respective regulated +DC or -DC bus. A positive and negative battery stack is used. Power factor correction is achieved by the use of intelligent PWM Controllers that sample the input ac voltage service and schedule the power conversion rate from the unregulated bus to the regulated bus to substantially remain in phase with the input the input ac voltage. 
     SUMMARY OF THE INVENTION 
     A first object of the invention backed-up power supply is to use an input rectifier and filter coupled to an input voltage source to convert the input voltage source into at least an unregulated positive dc voltage source and an unregulated negative dc voltage source. Each respective unregulated source has a respective unregulated dc voltage value with respect to the return. A positive and negative battery referenced to the return provide respective positive and negative battery voltages at corresponding positive and negative battery output terminals. 
     A current switch, such as a clamp or blocking diode, a semiconductor switch or a relay actuated switch isolates the unregulated positive and negative dc voltage sources from their respective battery voltages for unregulated voltage source values equal to or greater than their respective battery voltage. The current switch means clamps the unregulated dc voltage values to their respective battery voltage in response to loss of the sinusoidal input voltage source. 
     It is a second object of the invention backed-up power supply to provide a boost regulator comprising a positive and negative boost circuit coupled to receive power from the unregulated positive and negative dc voltage sources to provide positive and negative regulated dc voltage with respect to a return or neutral. 
     It is a third object of the backed-up power supply to use a dc-to-ac converter responsive to a reference signal and coupled to convert the positive and negative regulated dc voltage into at least a first uninterrupted output voltage for application to a load. The uninterrupted output voltage is continuously sampled and scaled to provide an output voltage sense signal. The output voltage sense signal is combined with the reference signal to provide an amplified error signal. The dc-to-ac converter is further characterized to continuously adjust and scale the output voltage in amplitude and phase to minimize the amplified error signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of a backed-up power supply powered from a two-phase sinusoidal input voltage source for providing an uninterrupted output voltage to a load; 
     FIG. 2 is a schematic block diagram of a backed-up power supply powered from a two-phase sinusoidal input voltage source for providing a first and second uninterrupted sinusoidal output voltages to respective loads (a second embodiment); 
     FIG. 3 is a schematic of an isolated converter half-bridge drive circuit; 
     FIG. 4 is a schematic of a converter control circuit; 
     FIG. 5 is a schematic of a converter current sense signal conditioner; 
     FIG. 6 is a schematic of a converter differential dc output current detection circuit; 
     FIG. 7 is a schematic of a converter output voltage sense circuit; 
     FIG. 8 is a schematic of a positive boost regulator; 
     FIG. 9 is a graphical depiction of voltages and currents at points within the circuit; 
     FIG. 10 is a schematic of a negative boost regulator with output voltage sensing; 
     FIG. 11 is a schematic of input ac voltage sense circuit for the power factor correction signal to a negative boost regulator; 
     FIG. 12 is a schematic of a negative boost regulator isolated power switch drive circuit; 
     FIG. 13 is a schematic of a positive battery charging circuit; 
     FIG. 14 is a schematic of a negative battery charging circuit; 
     FIG. 15 is a schematic block diagram of a backed-up power supply powered from a two-phase sinusoidal input voltage source for providing a single phase uninterrupted output voltage to a load, (a third embodiment); and 
     FIG. 16 is a schematic block diagram of a backed-up power supply powered from a two-phase sinusoidal input voltage source for providing a single phase uninterrupted output voltage to a load, (a fourth embodiment). 
    
    
     PREFERRED EMBODIMENT 
     FIGS. 1 and 2 show alternative embodiments of the invention uninterruptable or backed-up sinusoidal power supply 10 powered from an input voltage source 12 for providing an uninterrupted sinusoidal output voltage to load 14 at output terminal 16. In the embodiment of FIG. 1, the input voltage source input power is from a two-phase 60 Hz 120 Vac service from a utility grid shown as φA (phase A) and φB (phase B). 
     Block 18 in combination with capacitor filter 20 represents an input rectifier and filter means that comprises a conventional bridge rectifier, RFI filter, transient suppressor and fusing means (not shown) coupled to receive the input voltage source, φA and φB ac voltage and for converting the input voltage source into at least an unregulated positive dc voltage source providing an unregulated positive dc voltage, D+ at the D+ terminal 22 and an unregulated negative dc voltage source providing an unregulated negative dc voltage D-, at the D- terminal 24. The unregulated positive and negative voltage sources maintain respective unregulated dc voltage values at D+ terminal 22 and D- terminal 24 with respect to a return, such as the neutral or ground terminal 26. In the embodiments of FIGS. 1 and 2, the load return terminal 28 for the load 14 is electrically common with neutral terminal 26. Those in the art will understand that the load return 28 could be isolated from the neutral by the use of an isolation transformer (not shown). The primary winding of the isolation transformer would be connected between the first phase output terminals 16 and neutral terminal 26. The load 14 would be driven by the secondary of the isolation transformer. The load return terminal 28 could be isolated from the neutral terminal 26 with this arrangement if required. 
     Positive filter inductor 30, L15 couples the D+terminal 22 to the D+ output terminal 32 and negative filter inductor 34 couples the D- terminal 24 to the filtered D- output terminal 36. The positive and negative filter inductors 30, L15 and 34, L25 have high inductance values, typically in the hundreds of microhenries, and are sized to provide current smoothing for current being sourced to the filtered D+ output terminal 32 or sunk from the filtered D- output terminal 36. 
     The elements within phantom block 38 represent a battery means, referenced to the neutral terminal or return 26, and having a first battery 40 for providing a positive battery voltage, BTI+ at a first battery positive output terminal, BTI+ terminal 42 and a second battery 44 for providing a negative battery voltage, BTI- at a corresponding second battery negative output terminal, BTI- terminal 46. 
     Current is sourced to the D+ output terminal 32 from the first battery 40 when the voltage at the D+ output terminal 32 drops below the positive battery voltage BTI+. Current is sunk into the D- output terminal 36 from a second battery 44 when the voltage at the D- output terminal 36 drops below the positive battery voltage BTI-. 
     Positive current switch diode 48 and negative current switch diode 50 represent a current switch means having a positive current switch 48 and a negative current switch 50 for isolating (switch open) the unregulated positive and negative dc voltage source voltages at D+ terminal 22 and D- terminal 24 from their respective positive and negative battery voltages, BTI+ and BTI-, for unregulated positive and negative dc voltage source voltages, D+ and D-, equal to or greater than the battery voltages, BTI+ and BTI-. 
     The current switch diodes become forward biased (switch closed) and clamp the unregulated dc voltage values at the D+ output terminal 32 and the D- output terminal 36 to substantially equal the respective positive and negative battery voltages at terminals 42 and 46 in response to loss of the sinusoidal input voltage source φA and φB. Positive current switch diode 48 is back biased for unregulated positive dc voltage source values greater than the positive battery voltage value. Negative current switch diode 50 is back biased for unregulated negative dc voltage source values greater than the negative battery voltage value. To stop the batteries 40, 44 from discharging, boost logic is turned off by microprocessor controller 82 during the low input mains voltages as shown in FIGS. 9b and 9c as intervals A and B for the positive boost regulator circuit 54 and the negative boost regulator 56 circuits respectively. 
     The elements within phantom block 52 represents a boost regulator means coupled to receive power from the unregulated positive and negative dc voltage sources at voltages D+ and D- via positive filter inductor 30 and negative filter inductor 34 to filtered D+ output terminal 32 and filtered D- output terminal 36 respectively. In the event of loss of either or both of the unregulated positive and negative dc voltage sources, D+ and D-, power is obtained from the first and second batteries at the positive and negative battery output terminals 42 and 46 via corresponding positive current switch 48 or negative current switch 50 to the respective D+ output terminal 32 and the D- output terminal 36. Those in the art will understand that the current switches 48, 50 operate to provide a source selection function between dc sources for the respective inputs of a positive boost converter 54 and a negative boost converter 56 within the boost regulator means 52. 
     The diode arrangement of diodes 48 and 50 is believed to be the best mode for practicing a current switch because of its simplicity and low Cost; however, as known by those in the art, source selection is possible using relays, or other semiconductor devices such as transistors or FETS in combination with threshold detection circuits and appropriate drivers and blocking devices where necessary. It is also known in the art that relay contacts can be used to bridge semiconductor switching devices for the purpose of reducing the forward voltage drop associated with diodes or SCRs or the saturated voltage drop associated with semiconductor switching devices such as transistors. 
     The boost regulator means 52 of FIGS. 1, 2 comprises a positive boost regulator circuit 54 shown in detail in FIG. 8 and a negative boost regulator circuit 56, shown in detail in FIGS. 10 and 11, which, in combination, provide a positive and a negative regulated dc voltages, DC+ and DC-, at positive and negative regulated voltage terminals 58 and 60 respectively with respect to the return 26. The successful use of a positive and negative boost regulator in combination with source selection for sourcing power from alternate sources, i.e. an ac voltage source via an input rectifier and filter means 18 rectifier and capacitor filter 20 or a battery means 38, to a single or multiple output dc-to-ac converter is believed to be a novel minimum complexity arrangement which also provides substantial power factor correction ability. 
     The use of the input rectifier and capacitor filter allows the use of the same design for a wide range of input frequency, while permitting the use of additional input phases by selecting the use of two additional diodes for each input power phase to be added. The invention topology is also suitable for use with wild frequency, single or multiple input power phase sources for input power without redesign. 
     Referring again to FIG. 1, the elements within phantom block 64 represent a single phase dc-to-ac converter responsive to a positive and a negative regulated dc voltage, DC+ and DC-, at respective positive and negative regulated voltage terminals 58 and 60 for converting the positive and negative regulated dc voltages into at least a first uninterrupted sinusoidal output voltage at output terminal 16. 
     Referring to FIG. 2, the elements within phantom block 66 represent a two phase or multiple output dc-to-ac converter means coupled to convert the positive and a negative regulated dc voltage DC+ and DC- at respective positive and negative regulated voltage terminals 58 and 60 into at least a first and second uninterrupted sinusoidal output voltages at a first phase output terminal 16 and at a second phase output terminal 70 respectively. The circuit within phantom block 66 represents two circuits, each being identical to the topology of the single phase dc-to-ac converter circuit such as that shown in FIG. 1 in phantom block 64 but each being driven from a separately controlled reference signal via first and second reference signal lines 72, 74 respectively. 
     In the embodiments, of FIGS. 1 and 2, the dc-to-ac converter can be functionally arranged to sample the line voltages and to program the first and second reference voltages on the first and second reference signal lines 72, 74 to synchronize the output voltage to the loads, i.e. the first and second uninterrupted sinusoidal output voltages at output terminals 16 and 70, to match the frequency and phase of the respective input voltage sources φA and φB respectively. 
     An analog-to-digital converter 76 shown in FIG. 1 or 77 shown in FIG. 2 samples the input voltage sources φA as in FIG. 1, or φA and φB as in FIG. 2 on input mains or input power lines IL1, 78 and IL3, 80 with respect to the neutral line, IL2, 26 and make the real time sequence of the sampled values available as digital inputs to microprocessor controller 82. The voltage versus time relationship of a typical φA and φB voltage is illustrated as curve 79 and curve 81 respectively in FIG. 9a. 
     The continuous sequence of sampled values of the input voltages enables the microprocessor controller 82 to continuously have the amplitudes of the input mains φA and φB voltages available for use in generating and controlling the amplitude, frequency and phase relationships of reference voltage signals on the reference signal lines 72, 74. 
     In the alternative, the output voltages can be adjusted or programmed to provide an output service that is different in output voltage or frequency or both from that of the input voltage sources φA and φB on input mains or input power lines IL1, 78 and IL3, 80 with respect to neutral, IL2 26. Subject to limitations imposed by the values of the load, the switching frequency of the dc-to-ac converter, the value of the converter inductor inductance and its dc design current limitations, the output capacitance, the output frequency of the service can be made to approach or even equal zero on demand under the control of the microprocessor controller 82 by its control of the reference signal voltage on signal lines 72, 74. 
     Referring to FIGS. 1 and 2, input mains phase A and input mains phase B typically provide power at 120 Vac at 60 Hz for domestic U.S. applications and at 50 Hz with 220 Vac for European applications. The input voltages are delivered to the input rectifier and filter means 18 on input mains or input power lines IL1, 78 and IL3, 80 with respect to neutral, IL2 26. The input rectifier and filter 18 typically provides a conventional ballun wound or common mode inductor as part of a pi-section filter to suppress common mode noise emissions on the input mains. Each of the input mains are typically fused with appropriate fuses for the application. Transient suppressors such as MOV devices from GE would be provided between each of the input mains and neutral. The components forming the pi-section filter, the fusing components and the transient suppression components are not shown. 
     The input rectifier and filter 18 typically uses a bridge rectifier that provides the unregulated positive dc voltage source D+ and the unregulated negative dc voltage source D- to capacitor filter 20. The rectifier typically provides a full wave rectified output to peak charge capacitor filter 20 on successive cycles. For a system rated to deliver 3 KW of output power, capacitor filter 20 would typically have a value of 0.47 μF. 
     As an example, if the circuit of FIGS. 1 and 2 are operated with a total dc-to-ac converter output load of 3 KVA, with a two phase input of 120 Vac phase shifted at 120 degrees at input mains φA (phase A) 78 and φB (phase B) 80 with respect to the neutral terminal 26 as shown, the unregulated positive dc voltage at D+ will rise to 338 Vp with respect to the unregulated negative dc voltage D- and fall to a low of 10 to 30 V with respect to the unregulated negative dc voltage D- at four times the line frequency. At 60 Hz, the line frequency period is 16.66 ms. The ripple frequency period of the voltage at D+ with respect to D- would be approximately 4.166 ms for this example application and power service. 
     In a typical application, such as that shown in FIG. 1, the load is source selected via a source selection relay K1, 84 under the control of microprocessor controller 82. The microprocessor controller 82, in combination with corresponding analog and digital signal conditioning circuitry (not shown) monitors numerous performance parameters within the backed-up sinusoidal power supply 10 for the purpose of detecting a failure. At the onset of a failure, the microprocessor controller 82 initiates a pick or transfer signal to source selection relay K1, 84 to transfer the load from the output terminal 16 to the input main terminal 78. 
     The source selection relay K1, 84 represents a microprocessor controlled source selector for the output load 14. The output service is normally provided by the dc=to-ac converter shown within phantom line 64, typically a half bridge inverter topology with totem pole Switches such as pull-up IGBT switch Q1A, 86 and pull-down IGBT switch Q1B, 88. The IGBT switches are pulse width modulated typically at a wild frequency rate up to 20 Khz for a 50-60 Hz output frequency with inductor LA, 90 providing volt second averaging and instantaneous current control. In the two phase dc-to-ac converter 66 in FIG. 2, inductor LB, 94 also provides volt second averaging and instantaneous current control. 
     FIG. 3 represents a preferred embodiment of an inverter drive circuit shown as block 96 in FIG. 1. The two phase dc-to-ac converter 66 in FIG. 2 requires a first phase inverter drive circuit 96 and a second phase drive circuit 98. The first and second phase inverter drive circuits 96 and 98 are each identical in topology to the circuit of FIG. 3. Input terminals 102 for the first phase inverter drive circuit input terminal and 104 for the second phase inverter drive circuit input terminal represent respective first and second phase inverter drive circuit input terminals. The first and second phase inverter drive circuit input terminals receive respective pulse width modulated input signals A and B (not shown) as outputs from the first and second phase control circuits 124 and 126 respectively. 
     Referring to FIG. 3, block 106 represents a high voltage MOS gate driver integrated circuit such as the IR2110 from the International Rectifier Company of E1 Segundo, Calif. The high voltage MOS gate driver integrated circuit provides a high side output channel signal at a high side output channel output terminal Ho 108 that can be referenced to a floating rail, 500 volts above the reference for the low side output channel at a low side output channel output terminal Lo 110. In the present application, the high side output channel is referenced to the half bridge output terminal and driver circuit output terminal 120, approximately + or -210 Vdc above or below neutral 26. 
     The pulse width modulated high side channel output signal at the high side output channel output terminal Ho 108 is substantially in phase with the high side channel input drive signal at high side output channel input terminal Hin 114. The pulse width modulated low side channel output signal at low side output channel output terminal Lo 110 is substantially in phase with the low side channel input drive signal at low side output channel input terminal 116. The resistor, diode and zener components between the Ho terminal 108 and the gate of the pull-up IGBT 86 and between the Lo terminal 110 and the gate of the pull-down IGBT 88 are conventional speed-up and gate to source protective elements known in the art. 
     The dc-to-ac converter means 64, as depicted in FIG. 3, has an output capacitor 118, CA between output terminal 16 and neutral, the capacitor being in parallel with the load 14. The junction of the drain (emitter) of pull-up switch 86 and the source (collector) of pull-down switch 88 form the driver circuit output terminal 120. The inductor 90 couples the driver circuit output terminal 120 to the first phase output terminal 16. Each respective first or second phase inverter drive circuit 96, 98 applies a respective pulse width modulated bi-polar voltage from the positive regulated dc voltage source +DC 58, +210 Vdc, and the negative regulate dc voltage source -DC, 60, -210 Vdc to the inductor 90, LA input terminal at the driver circuit output terminal 120 in response to a pulse width modulated driver signals from a respective control circuit means such as the first and second phase control circuits 124, 126 for the first and second phases in FIG. 2. 
     FIG. 4 provides a schematic functional representation of an enablement for a first or second control circuit 124, 126. Each respective phase control circuit 124, 126 is responsive to a respective reference signal, such as first and second reference signals on signal lines 72 and 74 discussed previously in connection with FIGS. 1 and 2. Each respective phase control circuit 124, 126 also senses and responds to its respective output voltage via first and second output voltage sense lines 128 and 130 as depicted in connection with FIG. 2, for providing an amplified error signal, at a point such as comparator input 132, having a first polarity to indicate that the output voltage is above a value related to the reference signal and an error signal having a second polarity to indicate that the output voltage is below value related to the reference signal. By way of example, operational amplifier error amplifier 134 represents a means for summing the output voltage sense signal on the first output voltage sense line 128 with the first input voltage reference signal 72 to provide the amplified error signal at comparator input 132. The amplified error signal has a first polarity to indicate that the output voltage sense signal is above a value related to the reference signal and the amplified error signal has a second polarity to indicate that the output voltage is below a value related to the reference signal. 
     Operation of the first and second phase inverter drive circuits 96, 98 will now be further explained with reference to the circuit topology of FIG. 3. The first phase control circuit 124 provides a first phase pulse width modulated drive signal &#34;A&#34; to the first phase inverter drive circuit input terminal 102. A positive logic signal at A with respect to neutral turns on a first level shifting PNP transistor 136. Current passes through the transistor 136 to the resistor divider formed by resistors 140 and 142 which are sized to limit current flow and dissipation and to provide a positive logic signal at terminal 144 with respect to the DC- terminal 60. First inverter 146 provides an inverted signal at its output terminal 150 with respect to the input signal A at 102. The inverted and level shifted signal &#34;A&#34; is applied to the input of a high channel second inverter 154. The high channel second inverter 154 again inverts the level shifted signal &#34;A&#34; at its input and provides a non-inverted level shifted signal &#34;A&#34; as an output signal at its output 156. 
     Resistor 158 and capacitor 160 provide a delay for a positively rising signal at output 156. Diode 162 provides a fast discharge of the voltage on capacitor 160 for a negatively going logic level at output 156. The voltage on capacitor 160 is coupled to the input of the high channel at the Hin terminal 114 in phase but slightly delayed for positively going signals at &#34;A&#34; 102. Since the high voltage MOS gate driver 106 provides no inversion, the signal &#34;A&#34; is essentially in phase with the signal at the gate of pull-up switch 86 and the voltage at the output drive node 120 at the left side of LA 90. 
     The operation of resistor 172, capacitor 174, diode 176 duplicate the function and delays of corresponding components in the high channel. The absence of one inverter in the lower channel results in the signal at the low channel output Lo 110 being out of phase with the signal &#34;A&#34; at 102, and the low command occurring without substantial delay. The topology of FIG. 3 operates to insure a delay between the turn-on of the pull-up switch 86 and the turn-off of the pull-down switch 88 thereby providing protection against overlap with both switches being in the conductive state. 
     Referring again to FIGS. 1, 2 and 4, control circuits such as first phase control circuit 124 and the second phase control circuit 126, as characterized above, each receive an input voltage reference signal, (phase) from a respective first or second reference signal line, 72, 74 that is generated by a computer using software or data values from a read-only memory, the data values then being coupled to a digital-to-analog converter, or from the output of a conventional reference oscillator such as a Hartley or Blocking, or Colpitts oscillator. 
     A sinusoidal reference voltage is used for a sinusoidal output voltage in the case of a backed-up ac power supply. The reference for a particular single phase dc-to-ac converter 64 is usually synchronized to the frequency and phase of the respective input power line. 
     It should also be understood that the amplitude and phase angle of the reference can be controlled as needed for the different input/output requirements of a particular UP System. The frequency of the input voltage reference can be manually adjusted or automatically controlled to program the dc-to-ac converter to operate as a frequency converter or to provide an output voltage with any frequency or phase corresponding to that of the input voltage reference. 
     Where the input voltage reference on signal line 72, or 74 originates from a microprocessor, computer or other form of digital industrial controller, the frequencies, amplitude and phase angle can be controlled by feeding different parameters into the software, as required, the time dependent output being delivered to signal lines 72 and 74 from a digital-to-analog converter. 
     FIG. 4 depicts a schematic functional representation of a portion of a control circuit means. The circuitry within phantom block 182 represents an embodiment of a comparator means or comparator circuit having a comparator 183 with a comparator output 184. The comparator 183 is responsive to an amplified error signal at comparator input 132 for providing successive pulse width modulated driver signals to the first phase inverter drive circuit input terminal 102. Each successive pulse has a first or second state, such as a logic 1 or a logic 0 state. Each successive state has a duration controlled to continuously drive the amplified error signal to a smaller absolute value. In practice the amplified error signal will have a small characteristic sinusoidal envelope shape at the comparator input 132 at the line frequency of the output voltage (typically 60 Hz). But when the amplified error signal is compared with the instantaneous output current signal 188, the comparator output will be switching back and forth at a wild frequency of the inverter in the 10-20 Khz range as required to operate the output switches. 
     In the embodiment of FIG. 4, the comparator means or comparator circuit 182 within control circuit 124, further comprises a current sense means, such as the current sense circuit 186 shown in more detail in FIG. 5. The current sense circuit 186 provides an output current sense signal on comparator input signal line 188 that faithfully represents the amplitude and phase of the instantaneous output current passing through the inductor 90 to the load 16. The comparator circuit 182 sums the amplified error signal on comparator input 132 with the output current sense signal on comparator input signal line 188 to provide the successive pulse width modulated driver signals at the comparator output 184. The comparator output 184 is coupled to the first phase inverter drive circuit input terminal 102. The amplitude of the current sense signal is scalled to impose a limit on the amplitude of current sourced to the load. 
     By way of example, if the amplified error signal assumes a value that turns on the pull-up switch 86 and turns off the pull-down switch 88 and the current through inductor 90 increases, eventually the sense signal on the comparator input signal line will rise to a value that is sufficient to reverse the state of the signal at the first phase inverter drive circuit input terminal 102 causing the voltage to stop rising on the load and the current to stop increasing. The polarity of the current sense signal on the comparator current sense input signal line 188 is selected to cancel the amplified error signal at the comparator input 132 with increasing current values in response to an amplified but limited error signal on comparator input 132. 
     Referring again to the control circuit of FIG. 4, the diodes within phantom block 192 form a bi-polar clipper circuit. The zener is back biased for signals of positive or negative polarity applied on comparator input 132. The 10.0 Vz zener breaks down and allows current to flow with + or -10.0 V plus two forward diode drops totaling about 1.2 V. The bi-polar clipper circuit, with the values shown, therefore clamps the amplified error signal voltage at comparator input 132 to voltages within the range of ±11.2 V. 
     Referring to FIG. 5, since the range of the amplified error signal at comparator input 132 is limited to a predetermined range by the bi-polar clipper circuit 192 for amplified error signals of positive or negative polarity, the output current sense signal to the comparator current sense input signal line 188 is scaled to provide a signal that will cancel the maximum amplitude of the amplified error signal at comparator input 132 as the current out of the dc-to-ac converter output sensed by the first phase hall effect current sensor 194 reaches the maximum peak output current design limit. The scaling of the output current sense signal therefore imposes a limit on the amplitude of the instantaneous current sourced to the load. 
     The fidelity of the output voltage depends on the ability of the dc-to-ac converter to quickly correct for changes in the reference voltage and also load current. For this reason, the peak output current limit might typically be three or five times the rated output current thereby enabling the output voltage to faithfully track the form of the reference voltage while delivering linear or non-linear load currents to the load as required by the load. 
     The control circuit 124, 126 should be totally insensitive to non-linear loads as long as current required by a non-linear load does not reach the design peak output current limit. If the non-linear load requirement exceeds that output current limit, as when over loaded, the convertor limits the output load current to the load resulting in the distortion of the sinusoidal output voltage at the load 16 while protecting the pull-up and pull-down switches 86, 88 from failure. 
     The current sense circuit of FIG. 5 uses a first phase hall effect current sensor 194. The second phase circuit in FIG. 2 uses a second phase hall effect current sensor 196. Both hall effect current sensors are obtained from the F. W. Bell Company of Orlando, Fla. A model BB-100 hall effect sensor would be used in the current sense circuit of FIG. 5 with a design peak current limit of 75 amps. The full scale output of the BB-100 is ±5 V at 100A. The current sense amplifier 198 provides a gain of three as shown. A current of 10 A passing through the current sensor 194 will provide a 0.5 V signal. The current sense amplifier 198 would amplify this value to 1.5 V which is then applied to the comparator current sense input signal line 188 to the comparator circuit. 
     FIG. 6 is a schematic of a converter differential dc output current detection circuit that monitors the high frequency switching voltage across inductor LA, 90 and provides a low-pass filtering and integration for the purpose of detecting any dc voltage component that might exist or develop across inductor LA. Any dc component of voltage is amplified by 20. Both input channels for dc detection differential amplifier 202 are balanced so that common mode transitions on the two inputs to first and second input resistors 204 and 206 produce a balanced result at the input to the amplifier and do not influence the error voltage at the input of the amplifier. Only the volt second average of the difference voltage across inductor LA, 90 will contribute to the output voltage out of differential amplifier 202 and to the differential output voltage dc sense signal input 210 to the error amplifier 134 on FIG. 4. 
     FIG. 7 is a schematic of a converter output voltage sense circuit 214 that monitors the voltage applied to the load 14 at output terminal 16, and, depending on the respective phase, provides an output voltage sense signal to error amplifier 134 via the first output voltage sense line 128 or the second output voltage sense line 130. The circuit shown is an inverting low pass amplifier configuration with a pot adjustment provided for final scaling of the required output voltage. 
     The pot adjustment show as the &#34;DC BAL. ADJ. on FIG. 7 is a balance trim adjustment that is provided to permit the circuit to be adjusted to balance out the effects from amplifier dc offsets, error contributions from balanced resistor and capacitor networks and from output switching and swinging diode asymmetry. A similar function is provided by the &#34;DC BIAS BALANCE ADJ.&#34; input into the comparator means circuit 182 on FIG. 4. 
     POSITIVE AND NEGATIVE BOOST CIRCUITS 
     As stated above, phantom block 52 in FIGS. 1 and 2 represents a boost regulator means that comprises a positive boost regulator circuit 54 shown in detail in FIG. 8 and a negative boost regulator circuit 56, shown in detail in FIGS. 10, 11 and 12, which, in combination, provide a positive and a negative regulated dc voltages, DC+ and DC-, at positive and negative regulated voltage terminals 58 and 60 respectively with respect to the return 26. Operation of the positive boost circuit will be explained with reference to FIG. 8. 
     As explained above, in discussing FIGS. 1 and 2, the voltage at the filtered D- terminal 24 is an unregulated negative dc voltage D- that is under-filtered and connected to the inductor L25, 34, which in turn is connected to a current switch, 50, and inductor L24, 240. When the input system input power at IL1, φA at 78 and IL3, φB at 80 is available, inductor L25, 34, and inductor L24, 240 can be considered as one combined inductor, if the negative current switch is open. 
     By controlling the on time of the GTDRV (gate drive) signal to the negative boost switch 241, the negative boost circuit delivers a controlled amount of energy to the combined inductor by switching the right end of negative filter inductor 240 to neutral and allowing current to increase in the inductor. As the current ramps up in the inductor, the energy stored in the inductor increases in accordance with a (1/2)*L* 2 relationship. As the negative boost switch 241 is turned off, the energy previously stored in the combined inductor, negative filter inductor L25, 34, and negative boost inductor, L24, 240 is transferred to the DC- terminal 60 by forward biasing clamp diode 244. The voltage at the filtered D- terminal 24 has a ripple voltage and current at line frequency equivalent to the number of input phases, typically twice the line frequency for a two phase input. The voltage swing is the line voltage peak swing with respect to the reference neutral 26. The negative filter inductor L25, 34 has a high value of inductance that is designed to draw good line current from the input source. The value of the negative filter inductor L25, 240 is typically in the hundreds of microhenries. 
     In operation, both negative filter inductors L25, 34 and negative boost inductor L24, 240, can be considered as a single inductor for operation on line power; but, when batteries are providing power, negative filter inductor L25, 34 will not come into the picture. The negative boost inductor 240, L24, is rated by determining the maximum output current required from the negative regulated dc voltage terminal, 60, the negative power switch 241 current rating, the minimum voltage of second battery 44 at terminal 46, and the desired switching frequency. The energy stored in the combined inductors by turning on the negative boost switch 241 is passed through clamp diode 244, negative boost current sensor 242, and onto capacitor 903. 
     FIG. 9a graphically and schematically shows the approximate voltage applied by the input main IL1, φA at 77 and IL3 φB at 81 with respect to the neutral terminal at 26. The voltage waveform shown in phantom represents a missing third phase that could be, but which is not used in the topologies of FIGS. 1 and 2. The peak-to-peak swing is approximately 330 volts and the period is slightly in excess of 16.6 ms for 60 Hz and 120/208 Vac service. 
     FIG. 9b schematically shows the general shape of the voltage waveform of the unregulated positive dc voltage source voltage waveform 21 at D+ terminal 22 with respect to neutral. Substantial noise is present on this terminal but is not depicted for clarity. As the voltages at the D+ in FIG. 9b and the D- terminal shown in FIG. 9c enters the low mains voltage interval designated by bracketed intervals A and B respectively, discharge of the first and second batteries 40, 44 is avoided by the microprocessor interrupting operation of the positive and negative boost circuits 54, 56 during these respective intervals. 
     FIG. 9c shows the general shape of the voltage waveform 23 of the unregulated negative dc voltage source at D- terminal 24 with respect to neutral 26. Substantial noise is present on this terminal, due to the switching frequency of the boost and the dc-to-ac converters, but is not depicted for clarity. 
     FIG. 9d depicts the shape of the input current passing through the IL1 service line past terminal 78 and into the rectifier 18. The current in this line is substantially in phase with the input main phase φA voltage and has a peak-to-peak swing of approximately 14 amps. The synchronization of the φA voltage and current for a circuit operating at or near rated power indicates that the invention circuit presents the input power source with a near unity power factor. Noise present on the current waveform is omitted for clarity. 
     FIG. 9e shows the waveform of the current passing through negative boost inductor L24 in a timed relationship with the input voltage waveforms 79 and 81 above in FIG. 9a. The current through L24, i.e. I L24 , is substantially in phase with the voltage waveform of FIG. 9c. Switching noise present on the IL24 current waveform is omitted for clarity. 
     Referring to FIGS. 8 and 10, the positive boost controller 218 is a pulse width modulated controller such as the Unitrode UC 3854 High Power Factor Pre-regulator is used as a controller for both the positive and negative voltage boost circuits. The primary components within the positive boost circuit 54 are the positive boost inductor 220, L14, current sensor 222, clamp diode 224, positive boost switch 243, output capacitor 228, current sensor scaling amplifier 230 and other components to be discussed later. 
     The voltage at the D+ output terminal 32 is an unregulated positive dc voltage that is under-filtered and clamped by diode 48 to preclude this voltage from dropping below the battery 40 voltage minus the diode drop of diode 48. In practice, the voltage at the D+ output terminal 32 ripples at twice line frequency (for a two-phase input) between the peak line input voltage and the battery 40 voltage. Use of a true current switch, in place of the clamp diode 48 or 50, improves the sinusoidal shape of the waveform of the input current throughout each input power cycle thereby improving the input power factor. Use of a true current switch, such as relay contact or a solid state transistor switch also prevents current from being drawn repeatedly from the first and second batteries 40 and 44 thereby increasing the service life of the batteries. 
     Positive filter inductor 30, L15 has a high value of inductance measured in the hundreds of microhenries (400 μH), so in operation, the current in positive filter inductor 30, L15 builds up to a fairly constant level. The inductance of positive boost inductor 220, L14, is less than the inductance of the positive filter inductor 30, L15. Current through the positive filter inductor 30, L15 that is not sunk by positive boost switch 243 passes through clamp diode 224, L14, current sensor 222 and onto capacitor 228. 
     In the embodiment of FIGS. 1, and 2, with a lowest battery voltage limit specified at 50 Vdc for the positive and negative batteries 40, 44, positive filter inductor 30, L15 is designed based on the switch positive boost switch 243 current rating and the energy storage required for consecutive boost cycles at rated output power. 
     By way of example, a system designed to operate from two phase service, 120/240 Vac input mains and to provide two phase output power at 120/240 Vac to a 2100 watt load at rated power would typically have 180 volts p-p ripple at the unregulated positive dc voltage terminal 22, and 0.5 volts of ripple on the positive regulated voltage terminal 58 while using a positive filter inductor having an inductance of 400 μH, a boost inductor 220, L14, having an inductance of 100 μH, a capacitor filter having 0.047 μF and an output capacitor 228 having 3000 μF. The positive battery 40 would typically have a no load voltage of 60 Vdc, a float voltage of 67.5 Vdc and a cut-off low battery limit loaded voltage of 50 Vdc. 
     The inductance value of boost inductor 220, L14, is established by determining the maximum output current required from the positive regulated voltage terminal. The peak boost inductor current is typically four times (210/50) this average value. A maximum on-time is established for the positive boost switch 243. This time is typically slightly less than the boost duty cycle period. The inductance value for positive boost inductor 220, L14, is calculated based on the minimum battery buss voltage, peak inductor current and switching frequency. If V=L*Di/Dt, then L=(V* Dt)/Di where Di is four times the average output current, V is the minimum battery buss voltage, and Dt is the maximum on time of the switch. The maximum switching frequency is based on the Dt max (maximum switch on time) plus the minimum time required to transfer the energy stored in the boost inductor. 
     The positive boost regulator circuit of FIG. 8 samples the DC+ voltage via first and second DC+ voltage sense resistors 234 and 236 with second sense resistor 236 being a variable resistor for adjusting and setting the final positive regulated dc voltage on terminal 58. Sense resistors 234 and 236 form a positive boost regulator circuit output voltage sense divider for scaling the positive regulated dc voltage on terminal 58 to approximately +7.5 Vdc for delivery to the VSENSE input of the UC 3854 High Power Factor Pre-regulator. The UC3854 is a component available from the Unitrode Corporation of Merrimack, N.H., 03054-0399. Use of the UC3854 is described in a publication titled &#34;Linear Integrated Circuits Data And Applications Handbook&#34; published in 1990 and available from the Unitrode Integrated Circuits Corporation, 7 Continental Boulevard, P.O. Box 399, Merrimack, N.H., 03054-0399. 
     FIG. 8 shows the UC3854 input CT receiving a synchronizing clock input from the master clock at 19.53 Khz. The current sensed by current sensor 222 has a ramp triangular shape in the battery backup mode. Current sense scaling amplifier 230 provides a scaled ramp up followed by a ramp down signal into the MULTOUT input of the positive boost controller 218. As the rising ramp voltage into the MULTOUT input exceeds an internal voltage threshold, and internal latch is reset shutting elf the gate drive to positive boost switch 243 thereby allowing the current through positive boost inductor 220, L14, to pass through positive boost clamp diode 224 onto and into positive boost output capacitor 228. The internal voltage adjusts up and down as a function of the difference between the scaled VSENSE input and an internal precision voltage reference. 
     Continuing with FIG. 8, input IAC and the VRMS terminals on the positive boost controller 218 senses the filtered D+ output terminal voltage. The signals on these terminals are high in value and is utilized as a signal by the UC3854 control logic to adjust the duty cycle of the controller to increase the power factor that is reflected onto the input mains by operation of the boost regulator circuit 54. The GTDRV terminal on the controller provides a gate drive signal to switch 243. The filter network between the ISENSE and the CA terminals are feedback compensation components. The VCC and the ENA terminals are power input and enable terminals. 
     System power supplies provide a regulated dc voltage to the VCC terminal and the enable ENA terminal is used by the computer or system controller to turn the boost regulators on and off after start-up. Precision regulators (not shown) provide +5 Vdc and -5 Vdc with respect to the return ground, the neutral terminal 26 to the positive boost hall effect current sensor, 222, CS1 which in turn provides a positive boost current sense voltage signal representing the instantaneous current that is passing through positive filter inductor, 30, L15 and the positive boost inductor 220, L14, with respect to time to the positive boost current sensor scaling amplifier 230 inverting input. The 2.15K resistor to neutral is a scaling resistor. The positive boost current sense signal is coupled via a 5.1K resistor to the ISENSE input of the positive boost controller 218. 
     The D+ voltage signal is scaled by a network or resistors and capacitors to provide inputs to IAC and VRMS. The IAC and VRMS inputs are processed with the VSENS input to provide a variable threshold for an internal comparator within the UC 3854. The ISENSE is compared to the variable threshold voltage by the comparator and as the threshold is exceeded, the UC3854 turns off the GTDRV signal to the positive boost switch 243. The switch is commanded on, i.e. into the conduction mode at the next clock cycle. 
     Analog functions within the UC3854 control the variable threshold to permit a longer positive boost switch 243 on-time at lower D+ voltages and shorter on-time limits at higher D+ voltages. The threshold limits are reduced to low values for shorter on times as the DC+ voltage reaches a value that causes the VSENSE level to equal the value of a predetermined precision reference internal to the UC3854. The analog functions internal to the UC3854 are characterized to raise or lower the threshold limits of the internal variable threshold to cause the demand of the positive boost circuit to approximate that of a unity power factor load while regulating the DC+ voltage to be substantially constant. 
     Some principles of the positive boost regulator circuit component design apply to the components used in the negative boost circuit 56 shown in FIGS. 10, 11 and 12. One significant difference is that the emitter 232 of the negative boost switch 241 is not connected to neutral 26. FIG. 12 shows the isolation and level shifting circuit 264 for this application. 
     FIG. 10 shows the negative regulated dc voltage, DC- being sensed and scaled by a negative boost inverting amplifier 250 via negative boost sense input resistor 252. Since the logic power is referenced to the neutral and the negative voltage has to be regulated, an inverted differential mode amplifier 250 is used to scale the negative boost output voltage sense signal. The negative boost inverting amplifier 250 attenuates the signal sensed at the DC- terminal 60 and inverts the signal before providing the inverted negative boost output voltage sense signal to the VSENSE input of the negative boost controller 248. The output of amplifier 250 is connected to a negative regulated dc voltage adjusting pot 266, a 50K pot, via a 1.0K input scaling resistor 268. The 50K variable pot is used to adjust the negative regulated dc voltage DC- at the negative regulated voltage terminal 60 to its nominal value, typically, -210 Vdc. When balanced, negative boost inverting amplifier 250 provides an output signal to the VSENSE input pin of controller 248 at approximately +7.5 V. The negative controller 248 receives a clock at the CT terminal at about 19.53 Khz. 
     In the event of input mains power failure, battery switches, such as clamp diodes 48, 50 turn on and as positive boost inductor 220, L14, and positive boost switch 243 boost the BTI+ voltage and regulate the positive DC Bus to +210 Vdc and, referring to FIG. 10 and 11, the negative boost inductor, 240, L24 and negative boost switch 241 operate to boost the BTI- voltage and regulate the negative DC Bus to -210 Vdc. 
     The power factor correction and input voltage compensation circuit is formed by balanced positive and negative boost circuits operating at a switching frequency at or above 19.53 Khz. The positive boost switch 243 is referenced to neutral but the negative boost switch 241 is referenced to DC- at -210 Vdc. Positive boost inductor 220, L14, is the energy storage inductor for the positive boost circuit and negative boost inductor 240 is the energy storage inductor for the negative boost circuit. Winding L16 and L26 are logic power windings that provide logic power in the event of loss of input mains power. The clamp diodes for the positive and negative boost circuits are 224 and 244 respectively. The positive boost circuit output voltage of approximately +210 Vdc is supported by the positive boost output capacitors 228 at the DC+ terminal and the negative boost circuit output voltage of approximately -210 Vdc is supported by the negative boost output capacitor 246 at the DC- terminal 60. 
     Referring to FIG. 10, as in the case of FIG. 8, precision regulators (not shown) provide +5 Vdc and -5 Vdc with respect to the return ground, the neutral terminal 26 to the negative boost hall effect current sensor provides a negative boost current sense voltage signal representing the instantaneous current passing through negative boost inductor, 240, L24 with respect to time to the negative boost current sensor scaling amplifier 245 inverting input. The 2.15K resistor to neutral is a scaling resistor. The negative boost current sense signal is coupled via a 5.1K MULTOUT input resistor 272 to the MULTOUT input of the negative boost controller 248. An ISENSE terminating resistor 274 that is also a 5.1K resistor couples the ISENSE pin of the negative boost controller 248 to neutral. The filter components between the ISENSE pin and the CAOUT pin are feedback components. The voltage VAOUT directly controls the on time of the negative boost switch via the isolation and level shifting circuit 264 at input 276 of the isolation and level shifting circuit 264 depicted in FIG. 12. 
     FIG. 11 shows the unregulated negative dc voltage, D- being sensed at the D- terminal by first and second negative dc voltage input resistors 254, 256 which couple a scaled portion of the unregulated negative dc voltage, D- to the input of the negative boost input voltage scaling amplifier 258. The negative boost input voltage scaling amplifier 258 scales, buffers and inverts the scaled portion of the unregulated negative dc voltage, D- and couples it to the input of the negative boost voltage-to-current converter 260. 
     The negative boost voltage-to-current converter 260 converts the scaled portion of the unregulated negative dc voltage, D- into a corresponding sampled unregulated negative dc voltage, D- current drive signal which is coupled to the IAC input of the negative boost controller 248. 
     Continuing with FIG. 11, the ENA input to negative boost controller 248 is an enable pin that is used to turn-on and turn-off the negative boost regulator circuit 56. Voltage is applied to the VCC pin as logic power is available. The voltage into at the VRMS pin of controller 248 should be a dc voltage proportional to the RMS value of the input line voltage. Since the line voltage waveshape does not change significantly with time, the average value is obtained by a two-pole filter which attenuates harmonics that are present without introducing excessive delay. Voltage at the VSENS pin of controller 248 is fed to an inverting amplifier within the UC3854 that is referenced to an internal reference voltage of +7.5 Vdc. The resulting signal voltage is multiplied by the signal into the IAC terminal and divided by a signal proportional to the square of the signal into the VRMS terminal within the negative boost controller 248. The result of this analog computation is available as a signal at the MULTOUT terminal which becomes a current threshold command and is used in controlling the output of the controller 248 to obtain a near unity power factor. 
     With each clock pulse the real current is compared with the current command and controls an internal RS flip flop to control the duty cycle of the GTDRV terminal signal within the negative boost controller 248. 
     FIG. 12 shows the circuitry comprising the isolation and level shifting circuit 264 which is to isolate the logic from the negative boost power switch, 232. It is a low cost version using only one open collector driver IC ULN 2004 and a FET (VN10KMA). In normal operation, with a high level signal at input 276, opto-coupler, 288 turns on forcing a low state at level shifted terminal 290. A low at 290 forces the output open collectors of the first inverters 292 and second inverter 294 to assume an open state. The 100 Pf capacitor at the output of inverter 292 is discharged as a result of the output of second inverter 292 having been low. 
     As the output of second inverter 294 transitions from a low to a high, it turns on speed-up FET 298. The inverted output of the first inverter 292 transitions from a low to a high as result of current from the 300K resistor passing through zener 302. The transition from a low to a high at the output of the first inverter is coupled via an RC delay circuit to the input of a third inverter 300 and also to the inputs of fourth and fifth inverters 306 and 308. 
     In normal operation, the collector voltage of the negative boost switch 310 drops to within a few volts of DC- before the input voltage to the inputs of the third, fourth and fifth inverters rises to a level sufficient to reach the input threshold for a high level input. As the collector voltage of the negative boost switch 241 drops below the voltage required to break down zener 302, the voltage rise on the 100 Pf capacitor stops. As a result, the input levels to each of these three inverters remains low during the remaining commanded on-time for the negative boost switch 241. A low at the input of the third inverter 300 permits the input to the speed-up switch to remain high thereby holding the gate of the negative boost switch high. A continuing low on the inputs of the fourth and fifth inverters allows their output collectors to remain open as the gate of the negative boost switch 241 remains high. 
     In the event of a fault, that prevents the collector voltage of the negative boost circuit from falling below the avalanche voltage of the zener 302, current passes through the zener limited by the 300K resistor and charges the 100 pF capacitor and the RC network formed by the 24K and 200 pF capacitor resulting in a high logic state into the inputs of the third, fourth and fifth inverters within a predetermined time period (typically within 2-4 us). A high into the input of the third inverter results in a low at the gate of the speed-up switch 298 and a hard low into the gate of the negative boost switch 241 from the output collector of the third inverter 300. The output collectors of the fourth and fifth inverters also assist in clamping the gate of the negative boost switch 241 to DC- for the remainder of the commanded on-time. This fault protection feature prevents the negative boost switch 241 from being commanded on into a fault for more than the predetermined interval established by the 300K resistor, the Vz of zener 302, the RC time constant of the 24K and 200 pF capacitor, the 100 pF capacitor and the input threshold and bias characteristics of the third, fourth and fifth inverters. 
     At the conclusion of a commanded on time, the high into the input of the isolator 288 goes low resulting in a high into the input of the first and second inverters. A high into the input of the second inverter 294 turns on its output switch thereby turning off the speed-up switch 298. 
     A high into the first inverter 292 turns on its output NPN thereby discharging the 100 pF capacitor and opening the collector outputs of the fourth and fifth inverters. The gate of the negative boost switch is positively switched to ground by the output NPN of the second inverter 294 via diode 312 and gate resistor 314. 
     As described above, different functions within the negative boost controller 248 control the variable threshold within the negative boost controller 248 IC to permit a longer power switch, 241 on-time at lower D- voltages and shorter on time limits at higher D- voltage to draw current from the whole cycle, to give reflected unity power factor load to the lines φA, 78 and φB, 83 and also regulate the DC-, 60, voltage to a pre-adjusted and set value. This is done as the DC- voltage reaches a value that causes the V sense level to equal the value of the precision internal reference level to the UC3854. 
     FIGS. 13 and 14 are detailed schematics of the positive battery BTI+ charging logic block, 320 and the negative battery BTI- charging logic block, 322 respectively, shown as blocks in FIGS. 1 and 2. Referring now to FIG. 13, the positive regulated voltage terminal, DC+, 58 is connected to positive current sense resistor, 328 using signal line 330. The right side of the positive current sense resistor, 328 is connected to the drain of the positive switch FET, 332. The source of the positive switch FET is connected to the input side of the positive charger inductor, 334, which has a typical value of 330 μH at 3 A rating. The output side of the positive charger inductor, 334 is connected to the positive charger filler capacitor, 336 which has a typical value of 470 μF. The output side of the positive charger inductor, 334 is also connected to the terminal the first battery positive output terminal 42. 
     A 60 Vdc battery stack typically has a float voltage of approximately 67.5 Vdc at the first battery positive output terminal 42 while the positive regulated voltage terminal DC+, 58, is at +210 Vdc. The positive battery BTI+ charging circuit 320 operates as a buck regulator in the current control mode and uses positive battery charger controller 338, a 3843N IC as a PWM controller. 
     All logic is referenced to neutral 26, but the source of the positive switch (FET) 334 is at about 67.5 Vdc when switched off and +210 Vdc when switched on, so a pulse transformer, 340 is used to level shift the gate signal coming from the O/P terminal of the positive battery charger controller 338 to a signal referenced to the source of the positive switch FET 332. 
     Current mode control requires a current sense signal so a current sense transistor 342, a 2N6520, is used to level shift the current signal supplied to the ISENSE terminal of the positive battery charger controller 338. Input capacitor 344 receives a synchronizing clock signal from the master clock at 39 KHZ. The positive battery charger controller 338, a 3843N IC samples the BTI+ voltage via first and second BTI+ voltage sense resistors 346 and 348. 
     The filter network between the VFB and COMP terminals on the positive battery charger controller 338 are (feed back) compensation components. The positive and negative chargers are controlled by a computer (not shown) that monitors the state of the batteries. Diode, 350 is a free wheeling or clamp diode for the buck regulator. 
     FIG. 14 is a schematic for the negative battery BTI- charging logic block 322, that is powered from the negative regulated voltage terminal, DC-, 60. The negative regulated voltage terminal, DC-, 60 is connected to the source of negative switch FET, 354 through a negative current sense resistor, 356. The drain of the negative switch FET 354 is connected to the input of the negative charger inductor 358, and has a typical value of 330 μH. The drain of the negative switch FET, 354 is also connected to the anode of the negative clamp diode, 352. The cathode of the negative clamp diode 352 is connected to neutral. 
     The negative charger inductor 358 is connected to the negative terminal of negative charger filter capacitor 360 which has typical value of 470 μF. The negative regulated voltage terminal, DC-, 60 has a typical voltage value of -210 V. The typical second battery nominal voltage BT-, 44 is -60 VDC with a maintained I float voltage of -67.5 Vdc. 
     The negative battery BTI- charging circuit 322 operates as a buck regulator in the current control mode and uses negative battery charger controller 362, a 3483N IC as a PWM controller. The circuit logic is referenced to the negative regulated voltage terminal, DC-, terminal 60. A negative charger amplifier 364 is used in the differential mode to scale down the sense voltage from the second battery negative output terminal 46 and also to invert the error signal. The negative battery charger controller 362 samples the BTI- voltages via the output of negative charger amplifier 364 and first and second sense resistors 366 and 368. The filter network between terminals VFB and CMP are compensation (feed back) components. The negative battery charger controller 362 provides a gate drive signal from the O/P terminal that is a duty cycle controlled signal, to drive negative switch FET, 354 to regulate the BTI- voltage. Each power cycle of the regulator is synchronized with a clock pulse received via input capacitor 370 from the master clock at 39 KHZ. 
     The signal sensed at VFB is compared with a precision internal reference voltage level to generate an internal error signal. The internal error signal is internally compared with the current feed back signal into the ISENSE pin for to control the on-time of each power cycle that starts with each clock cycle. 
     FIG. 15 is a modified version of the circuit of FIG. 1 that provides a third alternative embodiment with a reduction in complexity by use of a higher battery buss voltage, such as a buss voltage in excess of but in the range of 200 Vdc. In this alternative embodiment, the battery busses are moved to the output of the clamp diodes 224 and 244 respectively. The first battery positive output terminal 42 is connected .to the cathode of the positive boost clamp diode 224 and the second battery negative output terminal 46 is connected to the anode of the negative boost clamp 244. This third alternative embodiment requires that the output voltage of the boost regulators be adjusted to provide a slight charge to the batteries as they approach a fully charged state. The positive and negative current switches 48, 50 are eliminated as are the positive and negative charging blocks 320, 322. 
     FIG. 16 is a modified version of FIG. 1 that provides a fourth alternative embodiment in which the first and second batteries 40, 44 are each low voltage battery stacks of typically 48 Vdc, which is much lower than the buss voltage of the input mains voltage 79 at IL1, 78 and 81 at IL3, 80. This fourth embodiment uses fewer battery cells in series for each battery than used by the batteries in the embodiment of FIG. 3. A reduction in the number of cells required by the embodiment of FIG. 16 implies greater economy and higher reliability than that the topology employed by the third embodiment of FIG. 15. 
     The embodiment of FIG. 16 reintroduces the use of current switches 48 and 50 and the positive and negative battery charging circuits 320 and 322. However, connecting the positive current switch cathode to the D+ terminal and the negative current switch anode to the D- terminal 24 permits the design to combine the function of the series combination of the positive filter inductor 30, L15, and the positive boost inductor 220, L14, into a single component, and the series combination of the negative filter inductor 34 and the negative boost inductor 240 into a single component. 
     The positive and negative filter inductors 30, L15 and 34, L25 are designed to meet the inductance requirements of line input mains voltage at input terminals 78, 80, current distortion and also higher current ratings to compensate for the lower battery buss voltages at terminals 42, 46 respectively. For a given output power requirement, the use of the alternative embodiment of FIG. 16 requires the combination of the positive filter inductor 30, L15 and positive boost inductor 220, L14, into a single positive boost inductor will result in a larger and more expensive component. The component size and cost can be reduced with the use of two chokes for each of the combination positive and negative boost inductors. 
     The positive and negative filter inductor 30, L15, and 34, L25 in the embodiment of FIG. 16 are designed for higher values of inductance, such as 800 μH, and with a current rating of 11 A for reduced input mains IL1 and IL3 current distortion. The positive battery boost inductor 220, L14, and the negative battery boost inductors 240 are designed for lower values of inductance in the range of 100 μH and with current ratings in the 22 amp range to meet the higher battery current requirements. 
     By way of example, for a system having an output rating of 3 KVA, 2 KW, 120/208, two-phase, three wire input, the positive and negative filter chokes 30, 34 would be designed to have 800 μH and would be rated at 11.1 amps. The low battery voltage limits would be 50 Volts for terminals 42 and 46 with respect to the return 26. To deliver the required power of 2 KW to the critical load, the average current from each battery bank is 22.3 amps. If only one combined positive filter inductor and positive boost inductor were used, this inductor would be designed for 800 μH and 22.3 amps which would be very large and expensive. An identical component would be necessary for the negative boost service. 
     Splitting the combined inductors into separate inductors on separate cores results in reduced size and cost. If both inductors are formed on the same core, with a tap for the battery switches 48 and 50 connections, the voltage swing at the rectifier output terminal 22 with respect to the D- terminal 24 would be approximately 1600 volts as a result of the volts/turn ratios. This example clearly illustrates that use of separate inductors on separate cores is the preferred embodiment if size, manufacturability and cost are to be minimized. 
     The embodiments of the invention described herein represent preferred embodiments, and variations and modifications will suggest themselves to those skilled in the pertinent arts. Some possible modifications have been mentioned above such as using a PNP level shifter of transistor 136 in FIG. 3 in place of the Opto-coupler level shifter 288 shown in FIG. 12. A cyclic sequence of digital output values from a micro-processor to the input of a digital-to-analog converter could be used to enable the output of the digital-to-analog converter to supply the reference voltage signal on signal line 72 and or 74. The values for the sinusoidal reference signals on signal lines 72 and 74 of FIG. 2 could also be obtained from a predetermined sequence of outputs of a ROM (read only memory) or by generating the values required from an algorithm and sequentially delivering them to a digital-to-analog converter for application to the circuit of FIG. 4. 
     Current sensing can be achieved by the use of current sense transformers or low ohmic value current sense resistors in co-operation with appropriate scaling and level shifting circuitry in place of the hall effect elements 194, 196, 222 and 242 described. These and other modifications that may suggest themselves to those skilled in the pertinent arts should be considered to be within the spirit and scope of the present invention, as defined in the claims that follow.