Patent Publication Number: US-2023132605-A1

Title: H-bridge driver with output signal compensation

Description:
FIELD OF DISCLOSURE 
     This disclosure relates generally to H-bridge drivers, and more particularly to H-bridge drivers configured with structures and functionality to mitigate or eliminate differential output polarity reversal that may occur under certain operating conditions. 
     BACKGROUND 
     An H-bridge is an electronic circuit that switches the polarity of a voltage that is applied to a load. H-bridges are used, for example, in electric-motor-based applications, such as robotics. An H-bridge may be used to control the flow of current to allow the electric motor to run in the forward and reverse directions. 
     A standard H-bridge-based driver (e.g., an RS-485 standard protocol driver) may include transient-voltage-suppression (TVS) diodes for surge protection of the system. However, under certain operating conditions, the polarity of the differential output voltage (VOD) flips when a driver enable signal is de-asserted to disable the driver in the presence of a high common mode load, which could potentially cause a glitch in the output to a receiver, such as a microcontroller, and disrupt communication. 
     During operation of a standard H-bridge driver with TVS diodes, current is steered from a P-stack on one bus output side through a common mode load and through an N-stack on the other bus output side. When the standard H-bridge is turned off and the bus output voltages discharge to the common mode load, the two TVS diode pairs discharge different amounts of reverse leakage current, generating a differential reverse leakage current that causes the polarity of the VOD to flip. 
     This VOD polarity flip is due in part to the design of the standard H-bridge driver. When the standard H-bridge driver is disabled, the P-stack driver and N-stack driver disable at slightly different times. During disable, as the bus output voltages discharge below 0 V, the gate-source voltage (V GS ) of a transistor-diode on one output node is greater than V GS  of a transistor-diode on the other output node. This creates unequal reverse leakage currents through the respective TVS diode pairs. This differential reverse leakage current initiates the VOD polarity flip. 
     Differential TVS diode capacitance discharge current contributes to keeping VOD polarity flipped for a longer period of time. As the drivers continue to discharge toward the common mode load after the driver stacks are disabled, based on the initial discharge voltages on the output nodes, the floating middle nodes of the respective two TVS diode pairs have different voltages. Hence, the different TVS diode pair capacitances generate different discharging currents, which maintains the VOD polarity flip for additional time. 
     A solution to this VOD polarity flip issue is thus desirable. 
     SUMMARY 
     In accordance with an example, a driver circuit comprises at least one current source (e.g., current source  142  and/or  144 ), coupled between a supply voltage terminal (e.g., Vcc) and a first output node (e.g., Y) of the driver circuit. These current source(s) are configured to supply a charge current during a pre-charge monopulse time period (e.g., t d ) during and less than a driver disable time period (e.g., t pz ) when the driver circuit is disabled. The supplied charge current is less than a current supplied by the current source(s) when the driver circuit is enabled. The driver circuit comprises another current source (e.g., current source  124 ) coupled to a ground terminal of the driver circuit, which current source is configured to be disabled during the driver disable time period, and a charge current source (e.g., current source  154 ) coupled between the supply voltage terminal and a second output node (e.g., Z) of the driver circuit, which current source is configured to be enabled during the pre-charge monopulse time period. The driver circuit comprises a first current switch (e.g., M Y_NDiode ) coupled to the first output node, the first current switch having a control terminal and configured to be charged during the pre-charge monopulse time period, and a second current switch (e.g., M Z_NDiode ) coupled to the second output node and to the third current source, the second current switch having a control terminal and configured to be charged during the pre-charge monopulse time period. A first pull-down switch of the driver circuit is coupled between the control terminal of the first current switch and ground, and a second pull-down switch of the driver circuit is coupled between the control terminal of the second current switch and ground. Each pull-down switch is configured to be activated during the pre-charge monopulse time period. 
     In accordance with an example, a driver circuit comprises first and second current switches (e.g., M Y_NDiode  and M Z_NDiode ); a first charge current source (e.g., current source  142  and/or current source  144 ) configured to deliver a charge current during a pre-charge monopulse time period (e.g., t d ) during and less than a driver disable time period (e.g., t pz ) when the driver circuit is disabled, and a second charge current source (e.g., current source  154 ) configured to be enabled during the pre-charge monopulse time period. The first and second charge current sources are configured to charge the first and second current switches during the pre-charge monopulse time period. The driver circuit comprises first and second pull-down switches coupled to the first and second current switches, respectively. The first and second pull-down switches are configured to be enabled during the pre-charge monopulse time period to discharge internal voltages of the first and second current switches, respectively. 
     In accordance with an example, a method comprises disabling, for a first time period (e.g., t pz ), a first current source (e.g., current source  142 ) coupled to a first current switch (e.g., M Y_NDiode ) at a first output node (e.g., Y) of a driver circuit; disabling, for the first time period, a second current source (e.g., current source  124 ) coupled to a second current switch (e.g., M Z_NDiode ) at a ground terminal of the driver circuit; enabling, for a second time period (e.g., t d ) during and less than the first time period, a third current source (e.g., current source  154 ) coupled to the second current switch at a second output node (e.g., Z) of the driver circuit; operating, for the second time period, a fourth current source (e.g., current source  144 ) coupled to the first current switch at the first output node; enabling, for the second time period, a first pull-down switch coupled between the first current switch and the ground terminal; and enabling, for the second time period, a second pull-down switch coupled between the second current switch and the ground terminal. 
     These and other features will be better understood from the following detailed description with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features of the disclosure may be understood from the following figures taken in conjunction with the detailed description. 
         FIG.  1    is a circuit diagram of an example H-bridge driver with a common mode load. 
         FIG.  2    shows a driver enable (DE) signal with respect to time, in which the hatched portion indicates a period during which an H-bridge driver, such as that of  FIG.  1    is operating in an enabled state. 
         FIG.  3    shows a DE signal with respect to time, in which the hatched portion indicates a driver disable time period during which an H-bridge driver, such as that of  FIG.  1   , is in a disabled state. 
         FIG.  4    shows a DE signal with respect to time, in which the hatched portion indicates a compensation time period during which compensation current is supplied to components of an H-bridge driver, such as that of  FIG.  1   . 
         FIG.  5    shows signals after applying technique to reduce differential reverse leakage current in an example H-bridge driver. 
         FIG.  6    shows signals after applying technique to compensate for differential TVS diode pair capacitance discharging current in an example H-bridge driver. 
         FIG.  7    is a flow diagram of an example method of operating an example H-bridge driver. 
     
    
    
     The same reference numbers are used in the drawings to designate the same or similar (structurally and/or functionally) features. 
     DETAILED DESCRIPTION 
     Specific examples are described in detail below with reference to the accompanying figures. These examples are not intended to be limiting. In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The objects depicted in the drawings are not necessarily drawn to scale, and graphs are approximate representations. 
     In examples, structure and/or functionality is provided to reduce or eliminate differential reverse leakage and/or discharge capacitance current in H-bridge drivers and similarly constructed components. In examples, such structure and/or functionality is enabled during driver disable or mode change in an H-bridge driver half-duplex configuration. In examples, the polarity flip of the output voltage, during disable or mode change, is mitigated or eliminated to improve communication between an H-bridge driver and downstream components, e.g., a microcontroller. 
       FIG.  1    is a circuit diagram of an example H-bridge driver  100  with a common mode load  102 . Common mode load  102  may include a common mode voltage, e.g., −12 V, at a voltage terminal  104 , and a resistive network that includes resistors  106  and  108 , each of which is coupled to voltage terminal  104 , and a resistor  110 . Resistors  106  and  108  also coupled to bus output nodes Y and Z, respectively, which output nodes are bridged by resistor  110 . Resistors  106  and  108  may each be approximately 375Ω, and resistor  110  may be approximately 54Ω. 
     Coupled between the Y bus output node and ground (GND) is a first pair of transient-voltage-suppression (TVS) diodes  112 . A second pair of TVS diodes  114  is coupled between the Z output node and ground. Each TVS diode pair  112 ,  114  is comprised of two diodes coupled back-to-back. The node between the two diodes of pair  112  is denoted N 1 , and the node between the two diodes of pair  114  is denoted N 2 . 
     First and second current switches  116  and  118  are coupled to bus output nodes Y and Z, respectively. Each of switches  116  and  118  may be comprised of an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) and a diode coupled between the drain and source of the n-type MOSFET. The source of first current switch  116  (M Y_NDiode ) is coupled to the Y bus output node, and the source of second current switch  118  (M Z_NDiode ) is coupled to the Z bus output node. The drain of current switch  116  is coupled to an N stack, Y side current source  122  (I NSTACK_Y ), and the drain of current switch  118  is coupled to an N stack, Z side current source  124  (I NSTACK_Z ). Each of current sources  122  and  124  is also coupled to ground. 
     The control terminals (e.g., gates) of first and second current switches  116  and  118  are controlled by first and second control switches  126  and  128 , respectively. Each of control switches  126  and  128  may be comprised of a p-type MOSFET and a diode coupled between the drain and source of the p-type MOSFET. The drain of control switch  126  is coupled to the control terminal of current switch  116 , and the drain of control switch  128  is coupled to the control terminal of current switch  118 . The sources of control switches  126  and  128  are coupled to a power supply terminal (V cc ). The gate of each of control switches  126  and  128  is controlled by input signal DE, which is the inverted signal of driver enable DE signal. 
     A resistor  132  is coupled between the control terminal (e.g., gate) and source of current switch  116 , and a resistor  134  is coupled between the control terminal (e.g., gate) and source of current switch  118 . Each of resistor  132  and  134  may be approximately 5 kΩ 
     H-bridge driver  100  also includes P stack current sources. On the Y bus output node side, there are two such current sources  142  and  144 , which are configured to deliver currents I PSTACK_1_Y  and I PSTACK_2_Y , respectively. Each of current source  142  and  144  is coupled between the power supply terminal (e.g., V cc ) and the Y bus output node. A Z side, P stack current source  146 , configured to deliver current I PSTACK_Z , is coupled between V cc  and the Z bus output node. 
     Coupled in parallel with current sources  142  and  144  is a Y side, compensation current source  148 , which is configured to deliver current I COMP_Y . Compensation current source  148  is coupled between V cc  and the Y bus output node. Another compensation current source  152  on the Z side is configured to deliver current I COMP_Z  and is coupled between V cc  and the Z bus output node. A pre-charge current source  154 , configured to deliver current I pre-charge , is coupled in parallel with current sources  146  and  152 . 
     H-bridge driver  100  further includes a pair of pull-down switches  156  and  158 . Each of pull-down switches  116  and  118  may be comprised of an n-type MOSFET and a diode coupled between the drain and source of the n-type MOSFET. The drain of pull-down switch  156 , disposed on the Y side, is coupled to the control terminal of current switch  116 , and the source of pull-down switch  156  is coupled to ground (GND). Pull-down switch  158  is similarly disposed on the Z side. That is, the drain of pull-down switch  158  is coupled to the control terminal of current switch  118 , and the source of pull-down switch  158  is coupled to ground. The control terminals (e.g., gates) of pull-down switches  156  and  158  are configured to receive a pre-charge pulse to activate them and rapidly discharge voltages of current switches  116  and  118 , as described below. 
     In an example, when the DE signal is asserted (DE=1) and applied to control switches  126  and  128  for a period of time, which is designated by the hatched portion in  FIG.  2   , H-bridge driver  100  operates in the enabled state. During this time period, based on a driver input signal (DIN), P stack current sources  142  and  144 , as well as N stack current source  124 , are ON. As a result, current flows from P stack current sources  142  and  144  to the Y bus output node, into common mode load  102  (across resistor  110  and also through resistors  106  and  108  toward voltage terminal  104 ). Current also flows into the Z bus output node, then through current switch  118 , and is then discharged to ground through N stack current source  124 . In an example operation during this time period (DE=1), control switches  126  and  128  are turned ON by  DE , which results in a voltage signal, e.g., a 5 V signal, being applied to the control terminals (e.g., gates) of current switches  116  and  118 . As a result, the gate-to-source voltage (V GS ) of current switch  118  is greater than the V GS  of current switch  116 . In this example, the V GS  of current switch  118  is approximately 5 V, while the V GS  of current switch  116  is approximately 1 V. Also, the voltage at node N 1  in TVS diode pair  112  is greater than the voltage at node N 2  in TVS diode pair  114 . 
     Thus, as shown in  FIGS.  3  and  5   , after DE transitions (e.g., to 0) and H-bridge driver  100  enters a disabled state, a pre-charge pulse is applied to pull-down switches  156  and  158  for a pre-charge monopulse time period (t d ), which is within but less than a driver disable time period (t pz ), where t pz  represents a time during which H-bridge driver  100  is disabled. Driver disable time period (t pz ) may be set in accordance with the RS-485 standard (incorporated by reference in its entirety), which is based on the maximum data rate supported by the driver. For example, for a 10 Mbps data rate driver, driver disable time period (t pz ) is 75 ns (max). Pre-charge monopulse time period (t d ) may be, for example, less than 50 ns across all supply, temperature and technology process corners. 
     The transition of DE to the disabled level (e.g., to 0) also disables one of the Y side, P stack current sources, e.g., current source  142 , which is turned OFF. During the duration of the pre-charge pulse, the other Y side, P stack current source, e.g., current source  144  remains ON, continuing to deliver current I PSTACK_2_Y , and pre-charge current source  154  is enabled to deliver current I Pre-charge . In an example, current sources  144  and  154  are operated during the pre-charge monopulse time period (t d ), such that the current delivered by the Y side, P stack current source that remains ON, e.g., I PSTACK_2_Y  from current source  144 , is greater than the I pre-charge  current (that is, I PSTACK_2_Y &gt;I pre-charge ). As a result, the voltage at each of the bus output nodes Y and Z is pulled to a value higher than a threshold turn-on voltage V TN  of n-type MOSFET switches  116  and  118 . Also, during the pre-charge monopulse time period (t d ), pull-down switches  156  and  158  are enabled via application of the discharge signal, to rapidly discharge V GS  of each of current switches  116  and  118  to less than 0 V, as shown in  FIG.  5   . Thus, there is no appreciable reverse leakage current through TVS diode pairs  112  and  114 . That is, I Diode_Y  and I Diode_Z , which represent the reverse leakage currents through TVS diode pairs  112  and  114 , respectively, are each at or near zero, as shown in  FIG.  5    and thus so is the differential reverse leakage current. As a result, as shown in  FIG.  5   , the differential output voltage (difference between the voltage at Y and Z, denoted VOD) remains positive; the polarity of VOD does not flip. 
     To maintain VOD greater than 0 V, current compensation is applied during a current compensation time period (t comp ), which occurs after the driver disable time period (t pz ) and the pre-charge monopulse time period (t d ) within t pz . Compensation time period (t comp ) may be set in the range of 500 ns-600 ns. At the start of the current compensation time period (t comp ), the P stack current source that was ON in the pre-charge monopulse time period (t d ), e.g., current source  144 , is disabled, as is pre-charge current source  154 . With these current sources now disabled, voltages of the TVS diode pairs  112  and  114  discharge toward common mode load  102 , decreasing the bus output node voltages, i.e., voltages at Y and Z, and generating capacitance-based discharge currents I Diode_Y  and I Diode_Z , which are typically of different values. Thus, a compensation current source is enabled during t comp  to offset or compensate for the differential capacitance-based discharge current. Based on the value of DIN, either compensation current source  148  is enabled or compensation current source  152  is enabled. When compensation current source  148  is enabled, the current (I COMP_Y ) it delivers is greater than the difference I Diode_Z —I Diode_Y  (i.e., I COMP_Y &gt;I Diode_Z —I Diode_Y ). When compensation current source  152  is enabled, the current (I COMP_Z ) it delivers is greater than the difference I Diode_Y —I Diode_Z (i.e., I COMP_Z &gt;I Diode_Y —I Diode_Z ). 
     As shown in  FIG.  6   , in an example in which compensation current source  148  is enabled to deliver current I COMP_Y , VOD remains above 0 V, thus avoiding a polarity flip. Current compensation time period (t comp ) may be set based on the expected maximum capacitance of TVS diode pairs  112 ,  114 . For compatibility with the RS-485 standard, I COMP  (from either compensation current source) should not exceed 10% of the short-circuit output current (I os ). That is, I COMP &lt;I os . 
       FIG.  7    is a flow diagram  700  of an example method of operating an example H-bridge driver. Operation  702  includes disabling, for a first time period (e.g., t pz ), a first current source (e.g., current source  142 ) coupled to a first current switch (e.g., current switch  116 ) at a first output node (e.g., bus output node Y) of a driver circuit (e.g., H-bridge driver  100 ). In operation  704 , a second current source (e.g., current source  124 ) coupled to a second current switch (e.g., current switch  118 ) at a ground terminal is also disabled for the first time period. 
     During a second time period (t d ), which is within but less than the first time period, operations  706 ,  708 ,  710  and  712  are performed. In operation  706 , a third current source (e.g., current source  154 ) coupled to the second current switch at a second output node (e.g., bus output node Z) of the driver circuit is enabled for t d . In operation  708 , a fourth current source (e.g., current source  144 ) coupled to the first current switch at the first output node continues to operate for t d . In operation  710 , a first pull-down switch (e.g., pull-down switch  156 ) coupled between the first current switch and the ground terminal is enabled, and in operation  712 , a second pull-down switch (e.g., pull-down switch  158 ) coupled between the second current switch and the ground terminal is enabled. Both pull-down switches  156  and  158  are enabled for t d . In operation  714 , after the first time period, during a third time period (t comp ), the third and fourth current sources may be disabled and a compensation current source (e.g., current source  148 ) is enabled. In operation  716 , after the third time period (t comp ), the compensation current source is disabled. 
       FIG.  7    depicts one possible order of operations. Not all operations need necessarily be performed in the order described. Some operations may be combined into a single operation, which may be based on the time period in which they occur. For example, operations  702  and  704  may be considered a single operation. Similarly, operations  706 ,  708 ,  710  and  712  may be considered a single operation, or grouped based components, e.g., enabling of current sources and enabling of pull-down switches. Additional operations may be performed as well. 
     As the foregoing demonstrates, various examples of structure and/or functionality are provided to reduce or eliminate differential reverse leakage and/or discharge capacitance current in H-bridge drivers and similarly constructed components. For example, an additional P stack current source on one output side that remains operable after driver disable, a pre-charge current source on the other output side that is enabled during a pre-charge monopulse time period within the driver disable time period, and a pair of pull-down switches cooperate with each other and other driver components to reduce differential leakage current. In another aspect, compensation current is provided using an enabled compensation current source to offset or compensate for differential TVS diode capacitance-based discharge current. In examples, structure and/or functionality is provided to mitigate or eliminate polarity flip of the output voltage during drive disable or mode change to improve communication between an H-bridge driver and downstream components, e.g., a microcontroller. 
     The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A. 
     A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. 
     As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronic or semiconductor component. Also, as used herein, the term “pre-charge” is relative to operation(s) that occur at a later period of time, i.e., the current compensation time period. 
     A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party. 
     While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type MOSFET may be used in place of an n-type MOSFET, and vice versa, with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)). 
     Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor. 
     Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a signal ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” and/or “substantially” preceding a value means +/−10 percent of the stated value. 
     Modifications of the described examples are possible, as are other examples, within the scope of the claims. For example, in an arrangement in which only one Y side, P stack current source is employed, i.e., the functionality of current sources  142  and  144  are combined into a single current source, that current source may be controlled to be partially enabled during the pre-charge monopulse time period (t d ) and then disabled during the current compensation time period (t comp ). Moreover, features described herein may be applied in other environments and applications consist with the teachings provided.