Patent Publication Number: US-9886049-B2

Title: Low drop-out voltage regulator and method for tracking and compensating load current

Description:
BACKGROUND 
     The present invention generally relates to a low drop-out voltage regulator and, more particularly, to a voltage regulator that tracks and compensates load current, and a corresponding method for tracking and compensating load current. 
     High performance power supplies use low drop-out voltage regulators (LDO) as power converters for their improved efficiency and reduced noise. For these reasons, LDOs also are widely used in various devices like mobile phones, electronic instruments, portable computers, etc. 
     A typical LDO includes an error amplifier, an output stage, and a sampling and feedback circuit. The sampling and feedback circuit samples an output voltage provided by the output stage, and feeds back to the error amplifier, such that a voltage feedback loop is formed to ensure a stable output of the LDO. 
     In operation, the output current of the LDO varies with connected loads. Specifically, in some of the applications, variations in load are remarkable such that the output current fluctuates beyond the range of stable operation. Further, mutual interference exists between the load and the intrinsic control loop of the LDO, which effects the frequency response and output stability of the LDO. 
     The present invention provides a low drop-out voltage regulator with improved output stability along with actual load current variations. The present invention also provides a corresponding method for a low drop-out voltage regulator to track and compensate load current. 
     SUMMARY 
     This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. 
     A low drop-out voltage regulator includes an error amplifier comprising a non-inverting input terminal, an inverting input terminal and an output terminal, one of the non-inverting input terminal and the inverting input terminal being connected to a reference voltage; an output circuit connecting the output terminal of the error amplifier to an external load and that generates an output current and an output voltage for the external load; a current tracking circuit coupled to the output circuit and that receives the output current and generates a tracking current that tracks the output current; and a load tracking-compensation circuit coupled to the current tracking circuit and the output circuit, and that generates a control voltage based on the tracking current and provides the control voltage to the output circuit. 
     A method for tracking and compensating load current of a low drop-out voltage regulator, wherein the low drop-out voltage regulator comprises an error amplifier and an output circuit. The method includes receiving an output current of the output circuit, and generating a tracking current which tracks the output current, and generating a control voltage according to the tracking current, and providing the control voltage to the output circuit. 
     The described low drop-out voltage regulator and its method for tracking and compensating load current adaptably adjust the compensation for the output circuit according to dynamic load current variations, which enables improvement of the frequency response, and further stables the operation of the LDO in connecting large or small loads. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying drawings, in which like reference numerals have been used to designate like elements, and in which: 
         FIG. 1  is a schematic circuit diagram of a low drop-out voltage regulator (LDO) in accordance with an embodiment of the present invention; 
         FIG. 2  is a schematic circuit diagram of a load tracking-compensation circuit of an LDO according to an embodiment of the present invention; 
         FIG. 3  is a small-signal model of an LDO with load current tracking and compensation according to an embodiment of the present invention; 
         FIG. 4  is a graph of an exemplary DC function waveform of an LDO according to an embodiment of the present invention; 
         FIG. 5  illustrates a Bode plot of a frequency response of a current loop of an LDO according to an embodiment of the present invention; 
         FIG. 6  illustrates a Bode plot of frequency compensation of a voltage loop of an LDO according to an embodiment of the present invention; and 
         FIG. 7  is a flow chart of a method for tracking and compensating load current of an LDO according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a schematic circuit diagram of a low drop-out voltage regulator  100  in accordance with an embodiment. The low drop-out voltage regulator (LDO)  100  includes an error amplifier  102 , an output circuit  104 , a current tracking circuit  106 , and a load tracking compensation circuit  108 . 
     The error amplifier  102  includes a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal is coupled to a reference voltage V ref , and the output terminal is coupled to the output circuit  104 . 
     In one embodiment, the reference voltage V ref  is provided by a band-gap reference voltage source (not shown), which can be implemented in various known ways. 
     The output circuit  104  is connected to the output terminal of the error amplifier  102  and receives an output of the error amplifier  102 . The output circuit  104  provides a corresponding output current and output voltage accordingly. The output current I out  and the output voltage V out  of the output circuit  104  are provided to external loads as the output current and output voltage of the LDO  100 . 
     In one embodiment, the output circuit  104  is implemented as a transistor, e.g., a MOS transistor. A gate terminal of the transistor is connected to the output terminal of the error amplifier  102  to receive the output of the error amplifier  102  and take it as a gate voltage V gate  of the transistor. As a result, a source terminal or a drain terminal of the transistor can be output as the output current I out  and output voltage V out  of the LDO  100 . 
     Still referring to  FIG. 1 , in one embodiment, a buffer stage circuit  110  is connected between the error amplifier  102  and the output circuit  104 . The buffer stage circuit  110  buffers and/or amplifies the output of the error amplifier  102 . It will be appreciated by those of skill in the art that the buffer stage circuit  110  is optional and is not necessarily included in the structure of the LDO  100 . 
     A voltage feedback circuit  112  is coupled between the output of the output circuit  104  and the inverting input terminal of the error amplifier  102 . The voltage feedback circuit  112  receives the output voltage V out  of the output circuit  104  and samples the output voltage V out . The voltage feedback circuit  112  provides the sampled voltage to the inverting input terminal of the error amplifier  102 . A closed loop feedback is formed through the voltage feedback circuit  112  accordingly. 
     In one embodiment, the voltage feedback  112  is implemented as a serial connection of resistors R 1  and R 2 . A node between the resistors R 1  and R 2  is coupled to the inverting input terminal of the error amplifier  102 . 
     It will be understood by those of skill in the art that the non-inverting input terminal and the inverting input terminal of the error amplifier  102  can be interchanged while not necessarily configured as shown in  FIG. 1 . 
     The current tracking circuit  106  includes a current mirror circuit  162 , an amplifier circuit  164 , and a track generation circuit  166 . In one embodiment, the current mirror circuit  162  comprises a transistor having the same or proportional parameters as the transistor of the output circuit  104 . The transistor of the current mirror circuit  162  is connected to be a mirror of the transistor of the output circuit  104 , such that a sensing current I sns , which is a mirror of the output current I out  is provided at one of a source terminal or a drain terminal of the transistor of the current mirror circuit  162 . 
     One terminal of the amplifier circuit  164  is connected to the output terminal of the current mirror circuit  162  for receiving the sensing current I sns  provided by the current mirror circuit  162 . The amplifier circuit  164  generates a corresponding feedback-control voltage accordingly. In one embodiment, the amplifier circuit  164  includes two transistors T 1  and T 2  having the same parameters. Gate terminals of the transistors T 1  and T 2  are coupled to each other, one of a source terminal and a drain terminal of the transistor T 1  is connected to a terminal of the transistor of the output circuit  104 , which provides the output voltage V out , while the other is coupled to the gate terminal of the transistor T 1 . One of a source terminal and a drain terminal of the transistor T 2  is connected to the output terminal of the current mirror circuit  162 , which provides the sensing current I sns , while the other is configured to output the feedback-control voltage. The feedback-control voltage provided by the amplifier circuit  164  reflects the sensing current I sns , such that the feedback-control voltage can be used for the current feedback loop of the LDO  100 . 
     The track generation circuit  166  is connected to the output terminal of the current mirror circuit  162  for receiving the sensing current I sns . The track generation circuit  166  is configured to provide a tracking current I track  for the load tracking compensation circuit  108 . It will be appreciated by those of skill in the art that the tracking current I track  reflects of the current output of the LDO  100  in its operation where a load is connected. 
     In one embodiment, the track generation circuit  166  includes transistors T 3  and T 4  having gate terminals connected together. The gate terminal of the transistor T 3  is coupled to a terminal of the amplifier  164  where the feedback-control voltage is provided, and coupled to the gate terminal of the transistor T 4 , so that the feedback-control voltage V I   _   ctrl  drawn through the gates of the transistors T 3  and T 4 , and further provided to the current feedback loop of the LDO  100 . One of a source terminal and a drain terminal of the transistor T 3  is coupled to the output of the current mirror circuit  162  for receiving the sensing current I sns . The transistor T 4  is connected as a mirror of the transistor T 3  such that the tracking current I track , which is a mirror of the sensing current I sns  is provided by one of a source terminal or a drain terminal of the transistor T 4 , which is a mirror of the terminal of the transistor T 3  connected to the output of the current mirror circuit  162 . 
     The load tracking compensation circuit  108  is connected between the current tracking circuit  106  and the output circuit  104 . The load tracking compensation circuit  108  receives the tracking current I track  and a feedback-control voltage V I   _   ctrl , and provides a control voltage V ctrl  to the output circuit  104 . In a presently preferred embodiment, the control voltage V ctrl  is provided to the output circuit  104  by way of the buffer stage circuit  110 . The load tracking compensation circuit  108  adaptively adjusts the control voltage V ctrl  based on the output current of the LDO  100  in conditions where loads are connected, and so adaptively adjusts a compensation to the primary stage circuit of the LDO so that the LDO  100  is very robust against load variations. 
     Referring to  FIG. 2 , a schematic diagram of the load tracking compensation circuit  108  in accordance with an embodiment of the present invention is shown. 
     The load tracking-compensation circuit  108  includes a current feedback circuit  202 , and a current compensation circuit  204 . The current feedback circuit  202  receives the feedback-control voltage V I   _   ctrl  (as shown in  FIG. 1 ) and provides the current feedback loop of the LDO  100  with the control voltage V ctrl . The current compensation circuit  204  receives the tracking current I track  and compensates for load current variations of the LDO through the control voltage V ctrl . 
     In the embodiment illustrated in  FIG. 2 , the current feedback circuit  202  includes a feedback transistor T 5  with connection nodes G 51 , G 52  and G 53 , where the connection node G 51  is a gate node, and connection nodes G 52  and G 53  are respectively one of a source node and a drain node. The gate node G 51  is connected to receive the feedback-control voltage V I   _   ctrl . A capacitor C 1  is coupled between the gate node G 51  and the connection node G 52 , which forms a current feedback loop based on the feedback-control voltage V I   _   ctrl . The current feedback circuit  202  enables output stability of the LDO  100  by using the control voltage V ctrl . It will be understood by those of skill in the art that the connection of the transistor T 5  and the capacitor C 1  forms a Miller compensation circuit, which compensates for the frequency response of the LDO based on the feedback-control voltage V I   _   ctrl . 
     The current compensation circuit  204  includes a first capacitor C m1 , a second capacitor C m2 , and a switching element T sw . The first capacitor C m1  is coupled between the output terminal of the current feedback circuit  202  and the control voltage V ctrl  on the output terminal of the load tracking-compensation circuit  108 . The second capacitor C m2  is connected in series with the switching element T sw  before being connected in parallel to the first capacitor C m1 . The switching element T sw  receives the tracking current I track , and controls the parallel connection of the second and first capacitors C m2  and C m1  accordingly. As shown in  FIG. 2 , the switching element T sw  is implemented with a switching transistor. A gate terminal of the switching transistor is coupled to the track generation circuit ( FIG. 1 ) and receives the tracking current I track . The switching transistor is switched on or off by the tracking current I track , so that the connected second capacitor C m2  connects or disconnects to the first capacitor C m1 . It is noted that the switching element T sw  can comprises other types of switching elements or other controllable switching circuits, while not being limited to the switching transistor shown in  FIG. 2 . 
     The current compensation circuit  204  further includes transistors T 6  and T 7  having gate terminals connected together. The transistor T 6  includes connection nodes G 61 , G 62 , and G 63 , where G 61  is a gate node and G 62  and G 63  are respectively one of a source node and a drain node thereof. The transistor T 7  includes connection nodes G 71 , G 72 , and G 73 , where G 71  is a gate node, and G 72  and G 73  are respectively one of a source node and a drain node. The connection nodes G 62  and G 72  of the transistors T 6  and T 7  are each coupled to receive the tracking current I track . The parallel connection of the first capacitor C m1  and second capacitor C m2  is coupled between connection nodes G 63  and G 73  of the transistors T 6  and T 7 . The connection nodes G 63  and G 61  of the transistor T 6  are connected together. An output connection node G 73  of the transistor T 7  is connected to the control voltage V ctrl  provided by the load tracking-compensation circuit  108 . 
     According to the current compensation circuit  204 , a capacitor comprising the first and second capacitors C m1  and C m2  composes a Miller compensation network together with the transistors T 6  and T 7 , with a capacitance of the first capacitor C m1  or a capacitance of the parallel connection of the capacitors C m1  and C m2  being the Miller capacitance of the Miller compensation network. 
     According to the described LDO  100 , a transfer function of the system is: 
     
       
         
           
             
               A 
               ⁡ 
               
                 ( 
                 s 
                 ) 
               
             
             ≈ 
             
               A 
               
                 ( 
                 
                   1 
                   + 
                   
                     
                       ɛ 
                       * 
                     
                     ⁢ 
                     
                       s 
                       ω 
                     
                   
                   + 
                   
                     
                       s 
                       2 
                     
                     
                       ω 
                       2 
                     
                   
                 
                 ) 
               
             
           
         
       
     
     wherein A is the loop gain, ε is the damping coefficient, ω is the Conjugate pole-frequency, while s is the s-domain frequency. 
     The damping coefficient ε can be expressed as: 
     
       
         
           
             ɛ 
             ∝ 
             
               
                 
                   C 
                   m 
                 
                 
                   I 
                   out 
                 
               
             
           
         
       
     
     wherein, I out  is the output current of the LDO, and C m  is the Miller capacitance of the Miller compensation network. 
     It can be seen that, when the load increases and thereby increases the load current, the switching element T sw  is conductive so that a capacitance connected to the control voltage V ctrl  node at the output terminal increases, the damping coefficient can be held at a relatively stable level so the loop is very stable. 
     The current feedback circuit  202  further includes a transistor T 8  coupled between the feedback transistor T 5  and the current compensation circuit  204 . One of a source terminal and a drain terminal of the transistor T 8  is connected to the current compensation circuit  204 , while the other is connected to the connection node G 52  of the feedback transistor T 5 . A resistor R 1  is connected between the source terminal and the drain terminal of the transistor T 8 . As described above, connection of the transistor T 5  and the capacitor C 1  forms a Miller compensation circuit, the gain thereof is:
 
 A   v   =g   m   ·R   out  
 
     wherein, A v  is the gain of the Miller compensation circuit, g m  is the transconductance, and R out  is the external impedance. It can be seen that the gain of the current feedback circuit  202  is impacted to a large extent by the external impedance connected to the capacitor C 1 , e.g., the impedance of the current compensation circuit  204  or especially the transistor T 6  thereof. On the other hand, the gate connection of the transistor T 6  results in a reverse-connected diode like circuit, such that the impedance of the current compensation circuit  204  is limited. Accordingly it is possible that the gain of the current feedback circuit  202  will not result in predetermined outcome. The transistor T 8  can increase the external impedance of a Miller compensation circuit formed by the transistor T 5  and the capacitor C 1 , and improve the gain of the current feedback circuit  202 . 
     The current feedback circuit  202  further includes a transistor T 9  having a gate terminal connected to the gate of the transistor T 8  so that the transistor T 8  operates in its saturation zone, which ensures the impedance of the transistor T 8 . It can be expected that, as the control current I ctrl  increases, the transistor T 8  will go into its linear zone while the impedance thereof will no longer be sustained. The resistor R 1  connected between the source terminal and the drain terminal of the transistor T 8  is able to clamp the source-drain voltage, so that the transistor T 8  operates in its saturation zone and ensures its impedance. 
     With reference to  FIG. 3 , which shows a small-signal model of the LDO  100  with load current tracking and compensation according to the present invention, F z  stands for a gain block from the output current I out  to the output voltage V out , F p  stands for a gain block from the control voltage V ctrl  to the output voltage V out , F g  stands for a gain block from the output current I out  to the sensing current I sns , and Fs stands for a gain block from the control voltage V ctrl  to the sensing current I sns . Besides the voltage feedback loop expressed by F y  and fed back from the output voltage V out , the embodiment of the present invention includes the tracking and compensation to the output current I out  through a feedback loop T i  (shown with dashed lines) from the sampled current I sns  to the control voltage V ctrl  (expressed by F i ). Due to the control of the tracking current I track , the capacitor C m2  is operably connected or disconnected, thereby a Miller capacitance composed by the capacitor C m2  and the C m1  is adjustable. In such a way, when the LDO  100  is connected with a relatively large load, the risk of the generated sub-harmonic oscillation in the current loop can be eliminated and further, negative impact on voltage loop stability when a light load is connected also is relieved or negligible. 
       FIG. 4  is a graph shown an exemplary DC function waveform of an LDO according to an embodiment of the present invention. As can be seen, when the load current is below the maximum operation limit, voltage loop adjustment dominates in the circuit. As the load current increases and exceeds the safe operating area (SOA), current loop adjustment will dominate in the circuit, and there&#39;s a clamp of maximum output current. In conditions between normal operation and SOA, there&#39;s both voltage loop and current loop adjustments. 
       FIG. 5  illustrates a Bode diagram of a frequency response of a current loop of an LDO according to an embodiment of the present invention. Included in  FIG. 5  is a comparison of frequency response waveforms between presence and absence of load current tracking and compensation. There are two (2) poles in the current loop, while the damping factor is controlled by the capacitors C m1  and C m2  ( FIG. 2 ). As a large load is connected, a frequency peak will appear after the unit gain frequency in case there&#39;s only fixed Miller capacitance instead of load tracking and compensation in the current loop, and thus the operation of the close loop goes unstable. In one embodiment of the LDO  100 , an adjustable Miller capacitance is formed by the fixed capacitor C m1  and the controllably connected capacitor C m2 , in such a way that the compensation loop can track the non-dominant pole and eliminate the frequency peak, while stabilizing the loop operation. 
     Referring to  FIG. 6 , a Bode diagram of a frequency compensation of a voltage loop of an LDO according to an embodiment of the present invention is illustrated. Being similar to those shown in  FIG. 5 , included in  FIG. 6  is a comparison of the frequency responses between presence and absence of load current tracking and compensation. If a fixed Miller capacitance is incorporated in the circuit, the phase margin of the voltage loop will be relatively low. Through the adjustable Miller compensation capacitor, the voltage loop stability is improved, which is especially distinctive when a light load is connected. 
     According to the LDO of an embodiment of the present invention, the unit gain bandwidth of the system is: 
     
       
         
           
             GBW 
             = 
             
               
                 
                   g 
                   in 
                 
                 * 
                 
                   g 
                   p 
                 
                 * 
                 
                   r 
                   
                     o 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
               
               
                 C 
                 L 
               
             
           
         
       
     
     where g m  is the input stage transductance, g p  is the output stage transconductance, r ol  is the output impedance, and C L  is the load capacitance. 
     The non-dominant pole of the LDO is: 
     
       
         
           
             
               P 
               nd 
             
             = 
             
               1 
               
                 
                   r 
                   
                     o 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 * 
                 
                   C 
                   m 
                 
               
             
           
         
       
     
     where C m  is the miller capacitance in the Miller compensation. 
     It can then be concluded that the phase margin of the system is: 
     
       
         
           
             PM 
             = 
             
               
                 
                   180 
                   π 
                 
                 ⁢ 
                 
                   
                     tan 
                     
                       - 
                       1 
                     
                   
                   ⁡ 
                   
                     ( 
                     
                       
                         P 
                         nd 
                       
                       GBW 
                     
                     ) 
                   
                 
               
               ∝ 
               
                 
                   tan 
                   
                     - 
                     1 
                   
                 
                 ⁡ 
                 
                   ( 
                   
                     1 
                     
                       C 
                       m 
                     
                   
                   ) 
                 
               
             
           
         
       
     
     It can be seen from the above that, if the compensation capacitance C m  is too high, when a light load is connected, the phase margin will drop and impact the system stability. The LDO according to the present invention switches off the switching element T sw  when the light load is connected, thereby ensuring a relatively small capacitor is connected at that time. 
       FIG. 7  is a flow chart of a method for load current tracking in an LDO in accordance with an embodiment of the present invention. For easy description, the flow is described hereinafter with reference to the LDO  100  illustrated in  FIGS. 1 and 2 . 
     A sensing current is generated in block  702 . Specifically, referring to the LDO  100  in  FIGS. 1 and 2 , the current mirror circuit  162  is used as a mirror to the output circuit  104 , and the current mirror circuit  162  provides the sensing current I sns  based on the output current I out  provided by the output circuit  104 . 
     A tracking current is generated in block  704 . In accordance with the LDO  100 , the track generation circuit  166  is used for receiving the sensing current I sns  and providing the tracking current I track . 
     In block  706 , connection or disconnection of the second capacitor to the first capacitor in parallel is controlled using the tracking current. The switching element T sw  receives the tracking current I track  and is switched on or off accordingly, such that the second capacitor C m2  connects or disconnects to the circuit, and accordingly, a parallel connection with the first capacitor C m1  is formed or not. More specifically, the switching element T sw  may comprise a switching transistor, where the gate terminal of the switching transistor is connected to receive the tracking current I track . The switching transistor is conductive or shutoff according to the tracking current I track , such that the connected second capacitor C m2  is connected or disconnected in parallel with the first capacitor C m1 . 
     A control voltage is generated in block  708 . The current compensation circuit  204  generates the control voltage V ctrl  through the control current I ctrl . 
     It will be understood that the frequency response of the LDO is impacted with the variation of the output current due to the connection of the load to the LDO. In order to release the LDO from the impact to its output current due to the connected load and stabilize the frequency response, corresponding compensation is required in the current loop. The LDO of the present invention adjusts the Miller compensation using a controllably connectable capacitor instead of the conventional Miller compensation with a fixed capacitor, and further controls the compensation extent to the circuit. Further, the control of the compensation is based on the output current feedback in connections with loads, the compensation is accordingly adaptive and reflects the compensation requirement of the LDO itself. The LDO of the present invention implements an adaptive control to the current compensation and improves the frequency response characteristics as well as system stability. 
     The use of the terms “a” and “an” and “the” and similar referents in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of protection sought is defined by the claims as set forth hereinafter together with any equivalents thereof entitled to. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illustrate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the term “based on” and other like phrases indicating a condition for bringing about a result, both in the claims and in the written description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention as claimed. 
     Preferred embodiments are described herein, including the best mode known to the inventor for carrying out the claimed subject matter. Of course, variations of those preferred embodiments will become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventor expects skilled artisans to employ such variations as appropriate, and the inventor intends for the claimed subject matter to be practiced otherwise than as specifically described herein. Accordingly, this claimed subject matter includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed unless otherwise indicated herein or otherwise clearly contradicted by context.