Patent Publication Number: US-5252516-A

Title: Method for producing interlevel stud vias

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a process for manufacturing multi-level interconnections in integrated circuits for semiconductor devices, and more particularly, to an improved process that reduces interlevel defects when using a reactive ion etch (RIE) to form very small vias. 
     2. Description of the Prior Art 
     As illustrated in FIG. 1, one type of prior art multi-layer interconnection of integrated circuits for semiconductor devices has a number of metal levels 10 interconnected by vias/studs 12. In this type of prior art multi-layer metal interconnections are separated by silicon oxide layers 14 (e.g., sputtered quartz, ECR oxide, or PECVD oxide) covered with a passivating oxide layer 16 formed by chemical vapor deposition (PECVD silicon nitride). The via metallization is typically tungsten or aluminum copper and the wiring pattern metallization is typically an alloy, such as an aluminum-copper alloy. A RIE process is used to form vias with a very small feature size. 
     While generally satisfactory, a significant failure mode in the above-described multilevel interconnection of the integrated circuit is the occurrence of interlevel short circuits. Such shorts may be caused by photolithography misregistration, pinholes in the passivating oxide layer, metal fencing and metal particles. Examples of such defects are shown in FIG. 1 and labeled A, B, C, and D. 
     SUMMARY OF THE INVENTION 
     An object of this invention is the provision of a process that reduces interlevel defects in semiconductor chips that use a RIE process for forming via openings; a process that improves reliability and product yield. 
     Briefly, this invention contemplates the provision process in which a metallized level is covered with a relatively thick non-conformal oxide layer, such as sputtered quartz (SiO 2 ). This layer is, in turn, covered with a relatively thin oxide blanket resistant to RIE, such as aluminum oxide (Al 2  O 3 ) or Yttrium Oxide (Y 2  O 3 ). A mask, with exposed via opening, is formed in a conventional manner on the aluminum oxide surface and the aluminum oxide in the open areas is removed. For example Al 2  O 3  is etched with BCl 3  and O 2  gases or with wet etch of H 3  PO 4 . An RIE process is used to form vias; an RIE process does not attack Al 2  O 3  or Y 2  O 3  oxide. Via metallization, such as tungsten, is then deposited as a blanket layer by conformal CVD, filling the via openings. A chemical mechanical polishing step is used to planarize the upper surface of the assembly, and remove the tungsten down to the upper surface of the thin oxide layer. The next metal level is then formed on this planarized surface using suitable prior art process steps including either a lift-off or metal RIE step in forming the metal pattern. The process is then repeated for successive layers starting with a relatively thick sputtered quartz coating. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: 
     FIG. 1 is a representational, sectional view of a prior art multi-metal interconnection of integrated circuits, illustrating various interlevel defects which can occur with comparable prior art processes. 
     FIGS. 2A through 2G are representational, sectional views illustrating the status of a multi-metal interconnection of integrated circuits at various stages of manufacture following process steps in accordance with the teachings of this invention. 
    
    
     DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION 
     Referring now to the drawings, and more particularly to FIG. 2 (starting at FIG. 2A), as an initial step in this exemplary embodiment of the process of this invention, a relatively thick oxide layer 24 is formed over a metal level, represented here by a pattern of conductors 15 as in the prior art module of FIG. 1. The oxide layer 24 is formed by a non-conformal process and serves as a primary insulation for passivating the metal conductors 15 and for intralevel and interlevel insulation. The oxide layer may be, for example, sputtered silicone oxide (SiO 2 ), PECVD oxide, or electron-cyclotron resonance (ECR) oxide. The conductor pattern 15 is formed using a suitable prior art process (e.g., a lift-off process or a reactive ion etching of the metal) and the conductive material may be, for example, an aluminum-copper alloy. 
     Next, a relatively thin (e.g., 2.8-3.0 KÅ) layer 20 of oxide, such as aluminum oxide (Al 2  O 3 ) or Yttrium (Y 2  O 3 ) is formed on the top surface of the thick oxide layer 24 in order to passivate layer 24 in the event of misregistration or a defect, such as a pin hole or other defect, in layer 24. Layer 20 may be formed by CVD. The oxide layer 20 is not attacked by subsequent reactive ion etching used to form sub-micron via openings. Thus, layer 20 also serves as an etch stop and prevents accidental over etching in the event of a via opening misalignment. 
     Referring now to FIG. 2B, the layer 20 is removed where it is desired to form via openings. This may be conveniently accomplished by the conventional steps of masking the layer, forming openings in the mask, and etching away the oxide layer 20 exposed by the openings. For example, BCl 3  and Q 2  can be used to etch Al 2  O 3  or wet etch process with H 3  PO 4 . Via openings 22 extending to the metal layer conductors 15 are next formed in the relatively thick oxide layer 24 by a RIE. 
     As illustrated in FIG. 2C, a conductive layer 25, preferably tungsten, is formed to fill the via openings 22; a tungsten layer 25 may be formed conveniently by CVD. A chemical-mechanical polishing step planarizes the assembly to the upper surface of the thin oxide layer 20, as illustrated in FIG. 2D. 
     Referring now to FIG. 2E, a metallization layer 26 is formed on the planarized surface of the assembly, as shown in FIG. 2E. This second level metallization can be formed to a conductive pattern (10&#39; FIG. 2F) using any suitable prior art process, such as lift-off or a metal reactive ion etch, for example. The process steps just described are then repeated, starting with the forming of a relatively thick oxide layer 24&#39; that is then covered with a thin layer of oxide 20&#39;. The wafer at this state in its manufacture is illustrated in FIG. 2G and is essentially the same state as illustrated in FIG. 2A. 
     While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.