Patent Publication Number: US-9847294-B2

Title: Semiconductor device allowing metal layer routing formed directly under metal pad

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of U.S. application Ser. No. 15/250,888 filed on Aug. 29, 2016, which is a continuation application of U.S. application Ser. No. 14/165,594 filed on Jan. 28, 2014, which claims the benefit of U.S. Provisional Application No. 61/759,497 filed on Feb. 1, 2013. 
    
    
     BACKGROUND 
     The disclosed embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device which can allow a metal layer routing formed directly under a metal pad. 
     Please refer to  FIG. 1 .  FIG. 1  is a simplified top-view diagram of a conventional semiconductor device  100 , wherein the semiconductor device  100  can be a chip. As shown in  FIG. 1 , the semiconductor device  100  comprises: a metal pad  102 , a power line  104 , and a ground line  106 . However, the power line  104  and a ground line  106  can not be formed under the metal pad  102 , and thus the semiconductor device  100  has a problem of requiring a large layout area for the power line  104  and a ground line  106 . 
     SUMMARY 
     In accordance with exemplary embodiments of the present invention, a semiconductor device is proposed to solve the above-mentioned problem. 
     According to an aspect of the present invention, an exemplary semiconductor device is disclosed. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer. 
     According to another aspect of the present invention, an exemplary semiconductor device is disclosed. The semiconductor device comprises: a metal pad and a plurality of first power/ground lines. The metal pad is positioned on a first metal layer of the semiconductor device. The plurality of first power/ground lines are formed in a second metal layer and directly under the metal pad, at least oxide region is formed between adjacent first power/ground lines. 
     According to another aspect of the present invention, an exemplary semiconductor device is disclosed. The semiconductor device comprises: a metal pad, a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer. 
     Briefly summarized, compared with prior art, since the semiconductor device disclosed by the present invention can allow a metal layer routing formed directly under a metal pad, the layout area size of the semiconductor device can be reduced effectively. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified top-view diagram of a conventional semiconductor device. 
         FIG. 2  is a simplified cross-sectional diagram of a semiconductor device according to a first exemplary embodiment of the present invention. 
         FIG. 3  is a simplified top-view diagram of the semiconductor device in  FIG. 2 . 
         FIG. 4  is a simplified cross-sectional diagram of a semiconductor device according to a second exemplary embodiment of the present invention. 
         FIG. 5  is a simplified top-view diagram of the semiconductor device in  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ” 
     Please refer to  FIG. 2  and  FIG. 3 .  FIG. 2  is a simplified cross-sectional diagram of a semiconductor device  200  according to a first exemplary embodiment of the present invention, and  FIG. 3  is a simplified top-view diagram of the semiconductor device  200 , wherein the semiconductor device  200  can be a chip. As shown in  FIG. 2  and  FIG. 3 , the semiconductor device  200  comprises: a metal pad  202 , a first specific metal layer routing  204 , and a second specific metal layer routing  205 . The metal pad  202  is positioned on a first metal layer  206  of the semiconductor device  200 , wherein the metal pad  202  has a thickness smaller than 20 KA (i.e. 2 micrometers), and material of the metal pad  202  can be aluminum. The first specific metal layer routing  204  is formed on a second metal layer  208  of the semiconductor device  200 , and directly under the metal pad  202 . In addition, please note that the above embodiment is only for an illustrative purpose and is not meant to be a limitation of the present invention. 
     The first specific metal layer routing  204  has a uniform pattern, wherein the uniform pattern has a metal density range between 30% and 70%. Please note that if the metal density of the uniform pattern is higher than 70%, the first specific metal layer routing  204  under the metal pad  202  will fail. If the metal density of the uniform pattern is lower than 30%, it will be hard to design the first specific metal layer routing  204  under the metal pad  202 . As shown in  FIG. 3 , the first specific metal layer routing  204  comprises four first power lines  210 , four first ground lines  212 , and an unused metal line  214 , wherein there are oxide regions  216  between the first power lines  210 , the first ground lines  212 , and the unused metal line  214 , and each oxide region  216  can have a width greater than 2 micrometers. In addition, the unused metal line  214  is kept as a dummy pattern for robust bondability. The second specific metal layer routing  205  is formed on the second metal layer  208  of the semiconductor device  200  and connected to the first specific metal layer routing  204 , wherein the second specific metal layer routing  205  is not positioned under the metal pad  202 . The second specific metal layer routing  205  comprises a second power line  218  and a second ground line  220 . Please note that the first metal layer  206  and the second metal layer  208  are adjacent metal layers of the semiconductor device  200 , and there is an oxide layer  209  between the first metal layer  206  and the second metal layer  208 . In addition, please note that the above embodiment is only for an illustrative purpose and is not meant to be a limitation of the present invention. For example, the numbers of the first power lines  210 , the first ground lines  212 , and the unused metal line  214  can be changed according to different design requirements. 
     Briefly summarized, compared with prior art, since the semiconductor device disclosed by the present invention can allow the metal layer routing formed directly under the metal pad, the layout area size of the semiconductor device can be reduced effectively. 
     Please refer to  FIG. 4  and  FIG. 5 .  FIG. 4  is a simplified cross-sectional diagram of a semiconductor device  300  according to a second exemplary embodiment of the present invention, and  FIG. 5  is a simplified top-view diagram of the semiconductor device  300 , wherein the semiconductor device  300  can be a chip. As shown in  FIG. 4  and  FIG. 5 , the semiconductor device  300  comprises: a metal pad  302 , a first specific metal layer routing  304 , and a second specific metal layer routing  305 . The metal pad  302  is positioned on a first metal layer  306  of the semiconductor device  300 , wherein the metal pad  302  has a thickness smaller than 20 KA (i.e. 2 micrometers), and material of the metal pad  302  can be aluminum. The first specific metal layer routing  304  is formed on a second metal layer  308  of the semiconductor device  300 , and directly under the metal pad  302 . In addition, please note that the above embodiment is only for an illustrative purpose and is not meant to be a limitation of the present invention. 
     The first specific metal layer routing  304  has a uniform pattern, wherein the uniform pattern has a metal density range between 30% and 70%. Please note that if the metal density of the uniform pattern is higher than 70%, the first specific metal layer routing  304  under the metal pad  302  will fail. If the metal density of the uniform pattern is lower than 70%, it will be hard to design the first specific metal layer routing  304  under the metal pad  302 . As shown in  FIG. 5 , the first specific metal layer routing  304  comprises four first IO routing lines  310  and five unused metal lines  314 , wherein there are oxide regions  316  between the first IO routing lines  310  and five unused metal lines  314 , and each oxide region  316  can have a width greater than 3 micrometers. In addition, the unused metal lines  314  are kept as a dummy pattern for robust bondability. The second specific metal layer routing  305  is formed on the second metal layer  308  of the semiconductor device  300  and connected to the first specific metal layer routing  304 , wherein the second specific metal layer routing  305  is not positioned under the metal pad  302 . The second specific metal layer routing  305  comprises four second IO routing lines  318 , wherein the second IO routing lines  318  can have at least a via plug for connecting to other metal line in other metal layer. Please note that the first metal layer  306  and the second metal layer  308  are adjacent metal layers of the semiconductor device  300 , and there is an oxide layer  309  between the first metal layer  306  and the second metal layer  308 . In addition, please note that the above embodiment is only for an illustrative purpose and is not meant to be a limitation of the present invention. For example, the numbers of the first IO routing lines  310  and the unused metal line  314  can be changed according to different design requirements. 
     Briefly summarized, compared with prior art, since the semiconductor device disclosed by the present invention can allow the metal layer routing formed directly under the metal pad, the layout area size of the semiconductor device can be reduced effectively. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.