Patent Publication Number: US-2022224318-A1

Title: Monotonic and glitch-free phase interpolator and communication device including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2021-0002312 filed on Jan. 8, 2021 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety. 
     BACKGROUND 
     1. Technical Field 
     Example embodiments relate generally to semiconductor integrated circuits and more particularly to phase interpolators with monotonic and glitch-free characteristics and communication devices including the phase interpolators. 
     2. Description of the Related Art 
     Despite improvements of speed of peripheral devices, such as memory, communication devices, or graphic devices and a data transmission rate, operating speeds of peripheral devices have not kept up with an operating speed of processors, in some cases. Further, a speed difference between new microprocessors and their peripheral devices is often present. Thus, some high performance digital systems have been required to dramatically improve speed of peripheral devices. 
     For example, like a data transmission between a memory device and a memory controller, in an input and output method of transmitting data by synchronizing a clock signal, a load of a bus increases and a transmission frequency becomes faster. Thus, it is very important to temporally synchronize the clock signal and data. To this end, a phase locked loop (PLL) circuit, a delay locked loop (DLL) circuit, etc. are used. The PLL and the DLL generally include a phase interpolator. The phase interpolator is a circuit that appropriately controls two selection delay clock signals of different phases and generates an optional delay clock signal between the two selection delay clock signals. The phase interpolator is used in various application circuits since it can precisely output a desired phase. 
     SUMMARY 
     At least one example embodiment of the present disclosure provides a phase interpolator including a digital-to-analog converter (DAC) controlled by two-dimensional thermometer codes and capable of having improved or enhanced performance 
     At least one example embodiment of the present disclosure provides a communication device including the phase interpolator. 
     According to example embodiments, a phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates a first thermometer code, a second thermometer code, and a selection signal based on a phase interpolation code. The digital-to-analog converter includes a plurality of unit cells that are arranged in a matrix formation including a plurality of rows and a plurality of columns, determines two of a plurality of weight signals as a first target weight signal and a second target weight signal based on the selection signal, and adjusts an amount of current of the first and second target weight signals by controlling the plurality of unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of a plurality of input clock signals as a first target clock signal and a second target clock signal corresponding to the first and second target weight signals and generates an output clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the output clock signal is between phases of the first and second target clock signals. The plurality of unit cells include a first unit cell and a second unit cell that are different types. 
     According to example embodiments, a communication device includes a phase interpolator and a data sampler. The phase interpolator generates a phase interpolation clock signal based on a phase interpolation code and a plurality of input clock signals. The data sampler generates sample data by sampling an input data stream based on the phase interpolation clock signal. The phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates a first thermometer code, a second thermometer code, and a selection signal based on the phase interpolation code. The digital-to-analog converter includes a plurality of unit cells that are arranged in a matrix formation including a plurality of rows and a plurality of columns, determines two of a plurality of weight signals as a first target weight signal and a second target weight signal based on the selection signal, and adjusts an amount of current of the first and second target weight signals by controlling the plurality of unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of the plurality of input clock signals as a first target clock signal and a second target clock signal corresponding to the first and second target weight signals and generates the phase interpolation clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the phase interpolation clock signal is between phases of the first and second target clock signals. The plurality of unit cells include a first unit cell and a second unit cell that are different types. 
     According to example embodiments, a phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates a first thermometer code of (X−1) bits, a second thermometer code of (Y−1) bits, and a selection signal of two bits based on a phase interpolation code, where each of X and Y is a natural number greater than or equal to two. The digital-to-analog converter includes X*Y unit cells that are arranged in a matrix formation including X rows and Y columns, determines two of a first weight signal, a second weight signal, a third weight signal, and a fourth weight signal as a first target weight signal and a second target weight signal based on the selection signal, and adjusts an amount of current of the first and second target weight signals by controlling the X*Y unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of a first input clock signal, a second input clock signal, a third input clock signal, and a fourth input clock signal as a first target clock signal and a second target clock signal corresponding to the first and second target weight signals and generates a phase interpolation clock signal by performing a phase interpolation operation on the first and second target clock signals based on the first and second target weight signals. Two adjacent input clock signals among the first, second, third, and fourth input clock signals have a phase difference of 90 degrees from each other. A phase of the phase interpolation clock signal is between phases of the first and second target clock signals. The X*Y unit cells include a first unit cell and a second unit cell that are different types, a number of the second unit cell is one, and a number of the first unit cell is (X*Y−1). The first unit cell operates based on all of the first and second thermometer codes and the selection signal and the second unit cell operates based on only the selection signal. The X*Y unit cells are always turned on and each of the X*Y unit cells is assigned to one of the first and second target weight signals based on at least one of the first and second thermometer codes and the selection signal. 
     The phase interpolator and the communication device according to example embodiments may include the digital-to-analog converter, which is controlled by the two-dimensional thermometer codes, to perform the phase interpolation operation on two input clock signals. Thus, the phase interpolator may have a relatively improved differential non-linearity (DNL) performance, the glitch-free characteristic, and the monotonic characteristic even when a control signal (or control code) having a relatively small number of bits is used. Accordingly, the phase interpolator may be implemented with a relatively small size and a relatively improved performance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. 
         FIG. 1  is a block diagram illustrating a phase interpolator according to example embodiments. 
         FIG. 2  is a block diagram illustrating an example of a phase interpolator of  FIG. 1 . 
         FIG. 3  is a diagram for describing an operation of a phase interpolator of  FIG. 2 . 
         FIG. 4  is block diagram illustrating an example of a decoder and a digital-to-analog converter included in a phase interpolator of  FIG. 2 . 
         FIG. 5  is a block diagram illustrating an example of a first unit cell included in a digital-to-analog converter of  FIG. 4 . 
         FIG. 6  is a circuit diagram illustrating an example of a first unit cell of  FIG. 5 . 
         FIG. 7  is a block diagram illustrating an example of a second unit cell included in a digital-to-analog converter of  FIG. 4 . 
         FIG. 8  is a circuit diagram illustrating an example of a second unit cell of  FIG. 7 . 
         FIG. 9  is a block diagram for describing first and second unit cells included in a digital-to-analog converter of  FIG. 4 . 
         FIG. 10  is a circuit diagram illustrating an example of a phase mixer included in a phase interpolator of  FIG. 2 . 
         FIGS. 11A, 11B, 11C, 11D, 12 and 13  are diagrams for describing an operation of a phase interpolator of  FIG. 2 . 
         FIG. 14  is a flowchart illustrating a method of generating a phase interpolation clock signal according to example embodiments. 
         FIG. 15  is a block diagram illustrating a communication device and a communication system including the communication device according to example embodiments. 
         FIG. 16  is a block diagram illustrating a communication device according to example embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Various example embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout this application. 
       FIG. 1  is a block diagram illustrating a phase interpolator according to example embodiments. 
     Referring to  FIG. 1 , a phase interpolator  100  includes a decoder  200 , a digital-to-analog converter (DAC)  300  and a phase mixer  400 . 
     The decoder  200  generates a first thermometer code TCODE 1 , a second thermometer code TCODE 2  and a selection signal SEL_IQ based on a phase interpolation code PI_CODE. 
     The phase interpolation code PI_CODE may be a code that represents the amount (or degree) of a phase interpolation operation performed by the phase mixer  400 . The first and second thermometer codes TCODE 1  and TCODE 2  and the selection signal SEL_IQ may be used to control an operation of the digital-to-analog converter  300 . The selection signal SEL_IQ may be a signal or digital code that is used to select two of a plurality of input clock signals CLK and to select two of a plurality of weight signals W_CLK corresponding to the selected input clock signals, and may be referred to as a clock selection signal. 
     The digital-to-analog converter  300  includes a plurality of unit cells  310  and  350  that are arranged in a matrix formation (e.g., a two-dimensional form) including a plurality of rows and a plurality of columns. The digital-to-analog converter  300  determines two of the plurality of weight signals W_CLK as a first target weight signal and a second target weight signal based on the selection signal SEL_IQ and adjusts and outputs the amount (or magnitude) of current of the first and second target weight signals by controlling the plurality of unit cells  310  and  350  based on the first and second thermometer codes TCODE 1  and 
     TCODE 2  and the selection signal SEL_IQ. A detailed configuration of the digital-to-analog converter  300  will be described with reference to  FIG. 4 . 
     The plurality of weight signals W_CLK may be signals that are used to assign or allocate different weights to the selected input clock signals. As described above, the digital-to-analog converter  300  may include the plurality of unit cells  310  and  350  arranged in the two-dimensional form, may be controlled based on the two thermometer codes TCODE 1  and TCODE 2  to generate and output the selected weight signals, and thus may be referred to as a digital-to-analog converter controlled by two-dimensional thermometer codes. 
     Unlike a general digital-to-analog converter including a plurality of unit cells that are the same type, the digital-to-analog converter  300  that is included in the phase interpolator  100  according to example embodiments and is controlled by the two-dimensional thermometer codes may include the plurality of unit cells  310  and  350  that are different types. For example, the plurality of unit cells  310  and  350  may include a first unit cell  310  and a second unit cell  350  that are different types. For example, the first unit cell  310  may operate based on all of the first and second thermometer codes TCODE 1  and TCODE 2  and the selection signal SEL_IQ and the second unit cell  350  may operate based on only the selection signal SEL_IQ. Detailed configurations of the first and second unit cells  310  and  350  will be described with reference to  FIGS. 5 through 9 . 
     In addition, unlike a general digital-to-analog converter that performs a digital-to-analog conversion operation by selectively turning on and off a plurality of unit cells based on a control code, the digital-to-analog converter  300  that is included in the phase interpolator  100  according to example embodiments and is controlled by the two-dimensional thermometer codes may include the plurality of unit cells  310  and  350  all of which are always turned on. For example, the digital-to-analog converter  300  may perform a digital-to-analog conversion operation for a phase interpolation operation such that each of the plurality of unit cells  310  and  350  is assigned or allocated to one of the first and second target weight signals based on at least one of the first and second thermometer codes TCODE 1  and TCODE 2  and the selection signal SEL_IQ. Detailed operations of the plurality of unit cells  310  and  350  will be described later. 
     In some example embodiments, the number of the unit cells  310  and  350  and the number of bits of the first and second thermometer codes TCODE 1  and TCODE 2  may be correlated with each other and the number of bits of the first and second thermometer codes TCODE 1  and TCODE 2  may be set or determined based on the number of the plurality of unit cells  310  and  350 . For example, the number of the plurality of rows and the number of the plurality of columns of the plurality of unit cells  310  and  350  may be X and Y, respectively, where each of X and Y is a natural number greater than or equal to two, and the total number of the plurality of unit cells  310  and  350  may be J (e.g., J=X*Y), where J is a natural number greater than or equal to four. In this example, when the first thermometer code TCODE 1  is a row thermometer code applied to the plurality of rows and the second thermometer code TCODE 2  is a column thermometer code applied to the plurality of columns, the number of bits of the first thermometer code TCODE 1  and the number of bits of the second thermometer code TCODE 2  may be (X−1) and (Y−1), respectively. In addition, among the plurality of unit cells  310  and  350 , the number of the second unit cells  350  may be one and the number of the first unit cells  310  may be (J−1) (e.g., (X*Y)−1). 
     The phase mixer  400  determines two of the plurality of input clock signals CLK as a first target clock signal and a second target clock signal and generates an output clock signal OCLK based on the first and second target weight signals and the first and second target clock signals (e.g., by performing the phase interpolation operation on the first and second target clock signals based on the first and second target weight signals). The first and second target clock signals correspond to the first and second target weight signals, respectively, and a phase of the output clock signal is between phases of the first and second target clock signals. The output clock signal OCLK may be referred to as a phase interpolation clock signal. A detailed configuration of the phase mixer  400  will be described with reference to  FIG. 10 . 
     The phase interpolation operation may be used to generate a clock signal having phase ranges between the phases of two input clocks, which have phases different from each other. For example, a clock signal having a phase in the range of about 0 to 90 degrees may be generated using a clock signal having about 0 degree phase and another clock signal having about 90 degree phase. When the phase interpolation operation is used as described above, a clock signal synchronized with a data signal may be generated and provided within a relatively short time even if jitter occurs on the data signal transmitted with a relatively high speed. 
     The plurality of input clock signals CLK may have different phases, and the phases of the plurality of input clock signals CLK may partially overlap each other. For example, two adjacent input clock signals among the plurality of input clock signals CLK may be determined as the first and second target clock signals based on the selection signal SEL_IQ. 
     In some example embodiments, the number of the input clock signals CLK, the number of the weight signals W_CLK and the number of bits of the selection signal SEL_IQ may be correlated with each other, and the number of the weight signals W_CLK and the number of bits of the selection signal SEL_IQ may be determined based on the number of the input clock signals CLK. For example, the number of the plurality of input clock signals CLK may be  2   K , where K is a natural number greater than or equal to one. In this example, the number of the plurality of weight signals W_CLK may be  2   K  that is equal to the number of the plurality of input clock signals CLK, and the number of bits of the selection signal SEL_IQ may be K. 
     In some example embodiments, the phase interpolator  100  may have a glitch-free characteristic. The glitch-free characteristic may indicate that only one of: (1) a plurality of selection bits, (2) a plurality of first bits, and (3) a plurality of second bits is toggled or transitioned when the phase interpolation code PI_CODE sequentially increases or decreases. 
     The plurality of selection bits may be included in the selection signal SEL_IQ, the plurality of first bits may be included in the first thermometer code TCODE 1  and may be referred to as a plurality of row bits, and the plurality of second bits may be included in the second thermometer code TCODE 2  and may be referred to as a plurality of column bits. In other words, in the phase interpolator  100  having the glitch-free characteristic, only one of outputs of the decoder  200  (e.g., only one control bit) may be toggled when the phase interpolation code PI_CODE is changed. 
     In some example embodiments, the phase interpolator  100  may have a monotonic or monotonicity characteristic. The monotonic characteristic may represent that the number of unit cells assigned to the first target weight signal (or the second target weight signal) among the plurality of unit cells  310  and  350  increases or decreases by one when the phase interpolation code PI_CODE sequentially increases or decreases. In other words, in the phase interpolator  100  having the monotonic characteristic, only one unit cell (e.g., only one current source) may be added to a weight (e.g., to a corresponding weight signal) based on a thermometer scheme. 
     The phase interpolator  100  according to example embodiments may include the digital-to-analog converter  300 , which is controlled by the two-dimensional thermometer codes, to perform the phase interpolation operation on two input clock signals. Thus, the phase interpolator  100  may have a relatively improved differential non-linearity (DNL) performance, the glitch-free characteristic, and the monotonic characteristic even when a control signal (or control code) having a relatively small number of bits is used. Accordingly, the phase interpolator  100  may be implemented with a relatively small size and a relatively improved performance 
       FIG. 2  is a block diagram illustrating an example of a phase interpolator of  FIG. 1 . The descriptions repeated with  FIG. 1  will be omitted. 
     Referring to  FIG. 2 , a phase interpolator  100   a  includes a decoder  200   a , a digital-to-analog converter  300   a , and a phase mixer  400   a.    
       FIG. 2  illustrates an example where K= 2 , X= 8 , Y= 4  and J= 32  in the phase interpolator  100  of  FIG. 1 . For example, the plurality of input clock signals CLK may include a first input clock signal CLK 0 , a second input clock signal CLK 90 , a third input clock signal CLK 180  and a fourth input clock signal CLK 270 . The plurality of weight signals W_CLK may include a first weight signal W_CLK 0 , a second weight signal W_CLK 90 , a third weight signal W_CLK 180  and a fourth weight signal W_CLK 270  that correspond to the first input clock signal CLK 0 , the second input clock signal CLK 90 , the third input clock signal CLK 180 , and the fourth input clock signal CLK 270 , respectively. A selection signal SEL_IQ[ 1 : 0 ] may include two selection bits. The digital-to-analog converter  300   a  may include a total of 8*4=32 unit cells. A first thermometer code R[ 6 : 0 ] may include seven row bits, and a second thermometer code C[ 2 : 0 ] may include three column bits. 
     The decoder  200   a  may generate the first thermometer code R[ 6 : 0 ] of 7 bits, the second thermometer code C[ 2 : 0 ] of 3 bits, and the selection signal SEL_IQ[ 1 : 0 ] of 2 bits based on the phase interpolation code PI_CODE. For example, the phase interpolation code PI_CODE may include a total of 128 values that are decimal numbers ranging from 0 to 127, and may generate a control code having a total of 12 bits based on the 128 values. 
     The digital-to-analog converter  300   a  may include a plurality of unit cells  310   a  and  350   a , may select two of the first, second, third and fourth weight signals W_CLK 0 , W_CLK 90 , W_CLK 180  and W_CLK 270  based on the selection signal SEL_IQ[ 1 : 0 ], and may adjust and output the amount of current of the selected two weight signals by controlling the plurality of unit cells  310   a  and  350   a  based on the first thermometer code R[ 6 : 0 ], a second thermometer code C[ 2 : 0 ] and the selection signal SEL_IQ[ 1 : 0 ]. For example, the plurality of unit cells  310   a  and  350   a  may include a first unit cell  310   a  and a second unit cell  350   a  that are different types. The first and second unit cells  310   a  and  350   a  may correspond to the first and second unit cells  310  and  350  in  FIG. 1 , respectively. The number of the first and second unit cells  310   a  and  350   a  may be  31  and  1 , respectively. 
     The phase mixer  400   a  may select two of the first, second, third and fourth input clock signals CLK 0 , CLK 90 , CLK 180 , and CLK 270  and may generate an output clock signal CLK_I by performing the phase interpolation operation on the selected two input clock signals based on the selected two weight signals. The selected two input clock signals may correspond to the selected two weight signals, and the output clock signal CLK_I may have a phase between the selected two input clock signals. The phase mixer  400   a  may also generate an inversion output clock signal CLK_IB in which the output clock signal CLK_I is inverted. A pair of the differential output clock signals CLK_I and CLK_IB may be generated by or from the phase mixer  400   a.    
     Two adjacent input clock signals among the first, second, third, and fourth input clock signals CLK 0 , CLK 90 , CLK 180 , and CLK 270  may have a phase difference of about 90 degrees from each other. For example, a phase difference between the first and second input clock signals CLK 0  and CLK 90  may be about 90 degrees. Similarly, a phase difference between the second and third input clock signals CLK 90  and CLK 180  may be about 90 degrees, a phase difference between the third and fourth input clock signals CLK 180  and CLK 270  may be about 90 degrees, and a phase difference between the fourth and first input clock signals CLK 270  and CLK 0  may be about 90 degrees. 
     The output clock signal CLK_I may be generated based on the selected two input clock signals in which two adjacent input clock signals are selected from among the first, second, third, and fourth input clock signals CLK 0 , CLK 90 , CLK 180 , and CLK 270 . For example, the output clock signal CLK_I may be generated based on the first and second input clock signals CLK 0  and CLK 90  and the first and second weight signals W_CLK 0  and W_CLK 90 . For another example, the output clock signal CLK_I may be generated based on the second and third input clock signals CLK 90  and CLK 180  and the second and third weight signals W_CLK 90  and W_CLK 180 . Alternatively, the output clock signal CLK_I may be generated based on the third and fourth input clock signals CLK 180  and CLK 270  and the third and fourth weight signals W_CLK 180  and W_CLK 270  or based on the fourth and first input clock signals CLK 270  and CLK 0  and the fourth and first weight signals W_CLK 270  and W_CLK 0 . 
       FIG. 3  is a diagram for describing an operation of a phase interpolator of  FIG. 2 . 
     Referring to  FIG. 3 , when the phase interpolation code PI_CODE input to the phase interpolator  100   a  corresponds to one of decimal numbers ranging from 0 to 31, the selection signal (SEL_IQ[ 1 : 0 ]) may be decoded as “11” in binary and the first and second input clock signals CLK 0  and CLK 90  may be selected to perform the phase interpolation operation on a first quadrant. For example, the selection signal SEL_IQ[ 1 : 0 ] may be decoded as a Gray code. For example, the output clock signal CLK_I, having a phase substantially the same as that of the first input clock signal CLK 0 , may be generated when the phase interpolation code PI_CODE corresponds to zero in decimal and the output clock signal CLK_I having a phase increased by about 90/32 degrees with respect to the first input clock signal CLK 0  may be generated whenever the phase interpolation code PI_CODE increases by one. 
     Similarly, when the phase interpolation code PI_CODE corresponds to one of decimal numbers ranging from 32 to 63, the selection signal SEL_IQ[ 1 : 0 ] may be decoded as “10” in binary and the second and third input clock signals CLK 90  and CLK 180  may be selected to perform the phase interpolation operation in a second quadrant. When the phase interpolation code PI_CODE corresponds to one of decimal numbers ranging from 64 to 95, the selection signal SEL_IQ[ 1 : 0 ] may be decoded as “00” in binary and the third and fourth input clock signals CLK 180  and CLK 270  may be selected to perform the phase interpolation operation in a third quadrant. When the phase interpolation code PI_CODE corresponds to one of decimal numbers ranging from 96 to 127, the selection signal SEL_IQ[ 1 : 0 ] may be decoded as “01” in binary and the fourth and first input clock signals CLK 270  and CLK 0  may be selected to perform the phase interpolation operation in a fourth quadrant. 
     An example of setting the first thermometer code R[ 6 : 0 ], the second thermometer code C[ 2 : 0 ] and the selection signal SEL_IQ[ 1 : 0 ] depending on a change in the phase interpolation code PI_CODE will be described with reference to  FIGS. 11 and 12 . 
       FIG. 4  is block diagram illustrating an example of a decoder and a digital-to-analog converter included in a phase interpolator of  FIG. 2 . 
     Referring to  FIGS. 2 and 4 , the decoder  200   a  may include a first decoder  210  and a second decoder  220 . 
     The first decoder  210  may generate seven row bits R[ 0 ], R[ 1 ], R[ 2 ], R[ 3 ], R[ 4 ], R[ 5 ] and R[ 6 ] that are included in the first thermometer code R[ 6 : 0 ] based on the phase interpolation code PI_CODE. For example, the row bit R[ 0 ] may be a least significant bit (LSB) of the first thermometer code R[ 6 : 0 ] and the row bit R[ 6 ] may be a most significant bit (MSB) of the first thermometer code R[ 6 : 0 ]. The first decoder  210  may be referred to as a row decoder. 
     The second decoder  220  may generate three column bits C[ 0 ], C[ 1 ] and C[ 2 ] that are included in the second thermometer code C[ 2 : 0 ] based on the phase interpolation code PI_CODE and may generate the selection signal SEL_IQ[ 1 : 0 ] based on the phase interpolation code PI_CODE. For example, the column bit (C[ 0 ]) may be an LSB of the second thermometer code C[ 2 : 0 ] and the column bit C[ 2 ] may be an MSB of the second thermometer code C[ 2 : 0 ]. As will be described with reference to  FIG. 5 , the selection signal SEL 3 Q[ 1 : 0 ] may include a first selection bit SEL _IQ[ 0 ] and a second selection bit SEL 3 Q[ 1 ], the first selection bit SEL_IQ[ 0 ] may be an LSB of the selection signal SEL 3 Q[ 1 : 0 ], and the second selection bit SEL 3 Q[ 1 ] may be an MSB of the selection signal SEL 3 Q[ 1 : 0 ]. The second decoder  210  may be referred to as a column decoder. 
     In some example embodiments, each of the first decoder  210  and the second decoder  220  may include a binary-to-thermometer decoder. 
     The digital-to-analog converter  300   a  may be implemented in the form of a current cell array that includes a plurality of unit cells U_ 0 [ 0 ], U_ 1 [ 0 ], U_ 2 [ 0 ], U_ 3 [ 0 ], UAW, U_ 1 [ 1 ], U_ 2 [ 1 ], U_ 3 [ 1 ], U_ 0 [ 2 ], U_ 1 [ 2 ], U_ 2 [ 2 ], U_ 3 [ 2 ], U_ 0 [ 3 ], U_ 1 [ 3 ], U_ 2 [ 3 ], U_ 3 [ 3 ], U_ 0 [ 4 ], U_ 1 [ 4 ], U_ 2 [ 4 ], U_ 3 [ 4 ], U_ 0 [ 5 ], U_ 1 [ 5 ], U_ 2 [ 5 ], U_ 3 [ 5 ], U_ 0 [ 6 ], U_ 1 [ 6 ], U_ 2 [ 6 ], U_ 3 [ 6 ], U_ 0 [ 7 ], U_ 1 [ 7 ], U_ 2 [ 7 ] and U_ 3 [ 7 ]. For example, a position of the unit cell U_ 0 [ 0 ] that is located at the lowermost and rightmost part of the current cell array may be defined as a first row and a first column, and a position of the unit cell U_ 3 [ 7 ] that is located at the uppermost and leftmost part of the current cell array may be defined as an eighth row and a fourth column. In this example, a position of an arbitrary unit cell U_m[n] may be represented by an (n+ 1 )-th row and an (m+ 1 )-th column, where m is an integer greater than or equal to zero and less than or equal to three, and n is an integer greater than or equal to zero and less than or equal to seven. 
     The unit cells U_ 0 [ 0 ], U_ 1 [ 0 ], U_ 2 [ 0 ], U_ 3 [ 0 ], U_ 0 [ 1 ], U_ 1 [ 1 ], U_ 2 [ 1 ], U_ 3 [ 1 ], U_ 0 [ 2 ], U_ 1 [ 2 ], U_ 2 [ 2 ], U_ 3 [ 2 ], U_ 0 [ 3 ], U_ 1 [ 3 ], U_ 2 [ 3 ], U_ 3 [ 3 ], U_ 0 [ 4 ], U_ 1 [ 4 ], U_ 2 [ 4 ], U_ 3 [ 4 ], U_ 0 [ 5 ], U_ 1 [ 5 ], U_ 2 [ 5 ], U_ 3 [ 5 ], U_ 0 [ 6 ], U_ 1 [ 6 ], U_ 2 [ 6 ], U_ 3 [ 6 ], U_ 0 [ 7 ], U_ 1 [ 7 ] and U_ 2 [ 7 ] may correspond to the first unit cell  310   a  in  FIG. 2  and may operate based on all of the first thermometer code R[ 6 : 0 ], the second thermometer code C[ 2 : 0 ] and the selection signal SEL_IQ[ 1 : 0 ]. For example, each of the unit cells U_ 0 [ 0 ] to U_ 3 [ 0 ], U_ 0 [ 1 ] to 
     U_ 3 [ 1 ], U_ 0 [ 2 ] to U_ 3 [ 2 ], U_ 0 [ 3 ] to U_ 3 [ 3 ], U_ 0 [ 4 ] to U_ 3 [ 4 ], U_ 0 [ 5 ] to U_ 3 [ 5 ], U_ 0 [ 6 ] to U_ 3 [ 6 ], and U_ 0 [ 7 ] to U_ 2 [ 7 ] may operate based on two row bits, one column bit and two selection bits SEL _IQ[ 0 ] and SEL_IQ[ 1 ]. For example, depending on a position of each unit cell, the row bits may be replaced with a power supply voltage or a ground voltage, or the column bit may be replaced with an inversion column bit or the ground voltage. 
     The unit cell U_ 3 [ 7 ] may correspond to the second unit cell  350   a  in  FIG. 2 , and may operate based on only the selection signals SEL_IQ[ 1 : 0 ]. For example, the unit cell U_ 3 [ 7 ] may operate based on only the two selection bits SEL_IQ[ 0 ] and SEL 3 Q[ 1 ]. For example, the unit cell U_ 3 [ 7 ] may be added to continuously rotate the phase at the moment when the quadrant is changed (e.g., to switch the direction of the current only when the quadrant is changed) in a process of performing the phase interpolation operation illustrated in  FIG. 3 . 
     All of the plurality of unit cells U_ 0 [ 0 ] to U_ 3 [ 0 ], U_ 0 [ 1 ] to U_ 3 [ 1 ], U_ 0 [ 2 ] to U_ 3 [ 2 ], U_ 0 [ 3 ] to U_ 3 [ 3 ], U_ 0 [ 4 ] to U_ 3 [ 4 ], U_ 0 [ 5 ] to U_ 3 [ 5 ], U_ 0 [ 6 ] to U_ 3 [ 6 ], and U_ 0 [ 7 ] to U_ 3 [ 7 ] may be commonly connected to a first node (e.g., a first node N 11  in  FIGS. 6 and 8 ) outputting the first weight signal W_CLK 0 , a second node (e.g., a second node N 12  in  FIGS. 6 and 8 ) outputting a second weight signal W_CLK 90 , a third node (e.g., a third node N 13  in  FIGS. 6 and 8 ) outputting the third weight signal W_CLK 180 , and a fourth node (e.g., a fourth node N 14  in  FIGS. 6 and 8 ) outputting the fourth weight signal W_CLK 270 . 
     As described with reference to  FIG. 1 , all of the plurality of unit cells U_ 0 [ 0 ] to U_ 3 [ 0 ], UAW to U_ 3 [ 1 ], U_ 0 [ 2 ] to U_ 3 [ 2 ], U_ 0 [ 3 ] to U_ 3 [ 3 ], U_ 0 [ 4 ] to U_ 3 [ 4 ], U_ 0 [ 5 ] to U_ 3 [ 5 ], U_ 0 [ 6 ] to U_ 3 [ 6 ], and U_ 0 [ 7 ] to U_ 3 [ 7 ] may always be turned on and thus the sum of currents flowing through the first through fourth nodes may always be constant. The number of unit cells assigned to each of the selected two weight signals may be changed based on the first thermometer code R[ 6 : 0 ], the second thermometer code C[ 2 : 0 ] and the selection signal SEL_IQ[ 1 : 0 ], the amount of current of the selected two weight signals may be adjusted based on the number of unit cells assigned to the selected two weight signals, and thus the phase interpolation operation illustrated in  FIG. 3  may be performed. 
       FIG. 5  is a block diagram illustrating an example of a first unit cell included in a digital-to-analog converter of  FIG. 4 . 
     Referring to  FIG. 5 , the first unit cell  310   a  may include a current source  320 , a weight selection signal generator  330 , and a current supplier  340 . The first unit cell  310   a  of  FIG. 5  may be the unit cell U_m[n] that is located in the (n+1)-th row and the (m+1)-th column among the plurality of unit cells U_ 0 [ 0 ] to U_ 3 [ 0 ], U_ 0 [ 1 ] to U_ 3 [ 1 ], U_ 0 [ 2 ] to U_ 3 [ 2 ], U_ 0 [ 3 ] to U_ 3 [ 3 ], U_ 0 [ 4 ] to U_ 3 [ 4 ], U_ 0 [ 5 ] to U_ 3 [ 5 ], U_ 0 [ 6 ] to U_ 3 [ 6 ], and U_ 0 [ 7 ] to U_ 3 [ 7 ] in  FIG. 4 . 
     The current source  320  may generate a unit current I_UNIT. As described above, the first unit cell  310   a  may always be turned on and thus the current source  320  may always be turned on. 
     The weight selection signal generator  330  may generate a first weight selection signal SELO, a second weight selection signal SEL 90 , a third weight selection signal SEL 180 , and a fourth weight selection signal SEL 270  based on a first row bit R[n−1], a second row bit R[n], a first column bit C[m], the first selection bit SEL_IQ[ 0 ], and the second selection bit SEL_IQ[ 1 ]. The first, second, third, and fourth weight selection signals SELO, SEL 90 , SEL 180  and SEL 270  may correspond to the first, second, third, and fourth weight signals W_CLK 0 , W_CLK 90 , W_CLK 180  and W_CLK 270 , respectively. 
     The current supplier  340  may provide an output (e.g., the unit current I_UNIT) of the current source  320  to one of the first, second, third and fourth weight signals W_CLK 0 , W_CLK 90 , W_CLK 180  and W_CLK 270  based on the first, second, third and fourth weight selection signals SELO, SEL 90 , SEL 180  and SEL 270 . In other words, the first unit cell  310   a  may be assigned to one of the first, second, third, and fourth weight signals W_CLK 0 , W_CLK 90 , W_CLK 180  and W_CLK 270  based on the first, second, third, and fourth weight selection signals SELO, SEL 90 , SEL 180  and SEL 270 . 
       FIG. 6  is a circuit diagram illustrating an example of a first unit cell of  FIG. 5 . 
     Referring to  FIG. 6 , a current source  320   a  may correspond to the current source  320  in  FIG. 5 , may be connected to a power supply voltage VDD, and may generate the unit current I_UNIT. 
     The weight selection signal generator  330   a  may include an OR gate  331 , an AND gate  332 , an inverter  333  and NAND gates  335 ,  336 ,  337  and  338 . 
     The OR gate  331  may perform an OR operation on the first column bit C[m] and the second row bit Rlnl. The AND gate  332  may perform an AND operation on the first row bit R[n−1] and an output of the OR gate  331 . The inverter  333  may invert an output of the AND gate  332 . The NAND gate  335  may generate the first weight selection signal SELO by performing a NAND operation on an output of the inverter  333  and the first selection bit 
     SEL_IQ[ 0 ]. The NAND gate  336  may generate the second weight selection signal SEL 90  by performing the NAND operation on the output of the AND gate  332  and the second selection bit SELM 11 . The NAND gate  337  may generate the third weight selection signal SEL 180  by performing the NAND operation on the output of the inverter  333  and a first inversion selection bit/SEL_IQ[ 0 ] in which the first selection bit SEL_IQ[ 0 ] is inverted. The NAND gate  338  may generate the fourth weight selection signal SEL 270  by performing the NAND operation on the output of the AND gate  332  and a second inversion selection bit/SEL_IQ[ 1 ] in which the second selection bit SEL_IQ[ 1 ] is inverted. 
     The current supplier  340   a  may include transistors  341 ,  343 ,  345  and  347 . 
     The transistor  341  may be connected between the current source  320   a  and the first node N 11  outputting the first weight signal W_CLK 0  and may have a gate electrode receiving the first weight selection signal SELO. The transistor  343  may be connected between the current source  320   a  and the second node N 12  outputting the second weight signal W_CLK 90  and may have a gate electrode receiving the second weight selection signal SEL 90 . The transistor  345  may be connected between the current source  320   a  and the third node N 13  outputting the third weight signal W_CLK 180  and may have a gate electrode receiving the third weight selection signal SEL 180 . The transistor  347  may be connected between the current source  320   a  and the fourth node N 14  outputting the fourth weight signal W_CLK 270  and may have a gate electrode receiving the fourth weight selection signal SEL 270 . 
     In some example embodiments, only one of the first, second, third and fourth weight selection signals SELO, SEL 90 , SEL 180  and SEL 270  may be activated. For example, when the first weight selection signal SELO is activated, the unit current I_UNIT may be provided to the first node N 11 . Alternatively, when the second weight selection signal SEL 90 , the third weight selection signal SEL 180  or the fourth weight selection signal SEL 270  is activated, the unit current I_UNIT may be provided to the second node N 12 , the third node N 13  or the fourth node N 14 , respectively. 
     In some example embodiments, the transistors  341 ,  343 ,  345  and  347  may be p-type metal oxide semiconductor (PMOS) transistors, however, example embodiments are not limited thereto. 
       FIG. 7  is a block diagram illustrating an example of a second unit cell included in a digital-to-analog converter of  FIG. 4 . The descriptions repeated with  FIG. 5  will be omitted. 
     Referring to  FIG. 7 , the second unit cell  350   a  may include a current source  360 , a weight selection signal generator  370  and a current supplier  380 . The second unit cell  350   a  of  FIG. 7  may be the unit cell U_ 3 [ 7 ] that is located in the eighth row and the fourth column in  FIG. 4 . 
     The current source  360  may generate a unit current I_UNIT. The amount of the unit current I_UNIT generated from the current source  360  may be substantially equal to the amount of the unit current I_UNIT generated from the current source  320  in  FIG. 5 . 
     The weight selection signal generator  370  may generate a first weight selection signal SEL 0 ′, a second weight selection signal SEL 90 ′, a third weight selection signal SEL 180 ′, and a fourth weight selection signal SEL 270 ′ based on the first selection bit SEL_IQ[ 0 ] and the second selection bit SEL_IQ[ 1 ]. The first, second, third and fourth weight selection signals SEL 0 ′, SEL 90 ′, SEL 180 ′, and SEL 270 ′ may correspond to the first, second, third, and fourth weight signals W_CLK 0 , W_CLK 90 , W_CLK 180  and W_CLK 270 , respectively. 
     The current supplier  380  may provide an output (e.g., the unit current I_UNIT) of the current source  360  to one of the first, second, third, and fourth weight signals W_CLK 0 , W_CLK 90 , W_CLK 180 , and W_CLK 270  based on the first, second, third and fourth weight selection signals SEL 0 ′, SEL 90 ′, SEL 180 ′, and SEL 270 ′. 
       FIG. 8  is a circuit diagram illustrating an example of a second unit cell of  FIG. 7 . The descriptions repeated with  FIG. 6  will be omitted. 
     Referring to  FIG. 8 , a current source  360   a  may correspond to the current source  360  in  FIG. 7 , may be connected to the power supply voltage VDD, and may generate the unit current I_UNIT. 
     The weight selection signal generator  370   a  may include an XOR gate  371 , an inverter  373 , and NAND gates  375 ,  376 ,  377 , and  378 . 
     The XOR gate  371  may perform an XOR operation on the first selection bit SEL_IQ[ 0 ] and the second selection bit SEL_IQ[ 1 ]. The inverter  373  may invert an output of the XOR gate  371 . The NAND gate  375  may generate the first weight selection signal SEL 0 ′ by performing the NAND operation on an output of the inverter  373  and the first selection bit SEL_IQ[ 0 ]. The NAND gate  376  may generate the second weight selection signal SEL 90 ′ by performing the NAND operation on the output of the XOR gate  371  and the second selection bit SEL_IQ[ 1 ]. The NAND gate  377  may generate the third weight selection signal SEL 180 ′ by performing the NAND operation on the output of the inverter  373  and the first inversion selection bit/SEL_IQ[ 0 ]. The NAND gate  378  may generate the fourth weight selection signal SEL 270 ′ by performing the NAND operation on the output of the XOR gate  371  and the second inversion selection bit/SEL_IQ[ 1 ]. 
     The current supplier  380   a  may include transistors  381 ,  383 ,  385  and  387 . 
     The transistor  381  may be connected between the current source  360   a  and the first node N 11  outputting the first weight signal W_CLK 0  and may have a gate electrode receiving the first weight selection signal SEL 0 ′. The transistor  383  may be connected between the current source  360   a  and the second node N 12  outputting the second weight signal W_CLK 90  and may have a gate electrode receiving the second weight selection signal SEL 90 ′. The transistor  385  may be connected between the current source  360   a  and the third node N 13  outputting the third weight signal W_CLK 180  and may have a gate electrode receiving the third weight selection signal SEL 180 ′. The transistor  387  may be connected between the current source  360   a  and the fourth node N 14  outputting the fourth weight signal W_CLK 270  and may have a gate electrode receiving the fourth weight selection signal SEL 270 ′. 
       FIG. 9  is a block diagram for describing first and second unit cells included in a digital-to-analog converter of  FIG. 4 . The descriptions repeated with  FIGS. 5, 6, 7 and 8  will be omitted. 
     Referring to  FIG. 9 , first unit cells (U_ 0 [ 7 : 0 ])  311  may be the first unit cells (e.g., the first unit cells U_ 0 [ 0 ] to U_ 0 [ 7 ]) that are located in the first column of the digital-to-analog converter  300   a  of  FIG. 4 . First unit cells (U_ 1 [ 7 : 0 ])  312  may be the first unit cells (e.g., the first unit cells U_ 1 [ 0 ] to U_ 1 [ 7 ]) that are located in the second column of the digital-to-analog converter  300   a  of  FIG. 4 . First unit cells (U_ 2 [ 7 : 0 ])  313  may be the first unit cells (e.g., the first unit cells U_ 2 [ 0 ] to U_ 2 [ 7 ]) that are located in the third column of the digital-to-analog converter  300   a  of  FIG. 4 . First unit cells (U_ 3 [ 6 : 0 ])  314  may be the first unit cells (e.g., the first unit cells U_ 3 [ 0 ] to U_ 3 [ 6 ]) that are located in the fourth column of the digital-to-analog converter  300   a  of  FIG. 4 . The second unit cell  350   a  may be the second unit cell U_ 3 [ 7 ] that is located in the eighth row and the fourth column of the digital-to-analog converter  300   a  of  FIG. 4 . 
     In some example embodiments, depending on an arrangement of the first unit cells  311 ,  312 ,  313  and  314  in the digital-to-analog converter  300   a , the first row bit R[n−1] may be replaced with the power supply voltage VDD, the second row bit R[n] may be replaced with a ground voltage VSS, or the first column bit C[m] may be replaced with the ground voltage VSS or a first inversion column bit/C[m] in which the first column bit C[m] is inverted. 
     For example, the digital-to-analog converter  300   a  may include an inverter that generates the first inversion column bit/C[m]. 
     For example, in the first unit cells  311 , a bit R[ 4 ] corresponding to the first row bit R[n−1] input to the unit cell U_ 0 [ 0 ] that is located in the first row and the first column may not exist and thus the first row bit R[n−1] input to the unit cell U_ 0 [ 0 ] may be replaced with the power supply voltage VDD. In addition, in the first unit cells  311 , a bit R[ 7 ] corresponding to the second row bit R[n] input to the unit cell U_ 0 [ 7 ] that is located in the eighth row and the first column may not exist and thus the second row bit R[n] input to the unit cell U_ 0 [ 7 ] may be replaced with the ground voltage VSS. Further, in the first unit cells  311 , the bit C[ 0 ] may be input as the first column bit C[m] to the unit cells U_ 0 [ 0 ], U_ 0 [ 2 ], U_ 0 [ 4 ] and U_ 0 [ 6 ] that are located in odd-numbered rows, and an inversion bit/C[ 0 ] in which the bit C[ 0 ] is inverted may be input as the first column bit C[m] to the unit cells U_ 0 [ 1 ], U_ 0 [ 3 ], U_ 0 [ 5 ] and U_ 0 [ 7 ] that are located in even-numbered rows. 
     As a result, in the first unit cells  311 , the first row bit R[n−1], the second row bit R[n] and the first column bit C[m] that are input to the unit cell U_ 0 [ 0 ] may be the power supply voltage VDD, the bit R[ 0 ] and the bit C[ 0 ], respectively. The first row bit R[n−1], the second row bit R[n] and the first column bit C[m] that are input to the unit cell U_ 0 [ 1 ] may be the bits R[ 0 ], R[ 1 ] and/C[ 0 ], respectively. Similarly, the bits R[ 1 ], R[ 2 ] and C[ 0 ] may be input to the unit cell U_ 0 [ 2 ]. The bits R[ 2 ], R[ 3 ] and/C[ 0 ] may be input to the unit cell U_ 0 [ 3 ]. The bits R[ 3 ], R[ 4 ] and C[ 0 ] may be input to the unit cell U_ 0 [ 4 ]. The bits R[ 4 ], R[ 5 ] and/C[ 0 ] may be input to the unit cell U_ 0 [ 5 ]. The bits R[ 5 ], R[ 6 ] and C[ 0 ] may be input to the unit cell U_ 0 [ 6 ]. The bit R[ 6 ], the ground voltage VSS and the bit/C[ 0 ] may be input to the unit cell U_ 0 [ 7 ]. 
     As with the first unit cells  311 , in the first unit cells  312 , the power supply voltage VDD, the bit R[ 0 ] and the bit C[ 1 ] may be input to the unit cell U_ 1 [ 0 ]. The bits R[ 0 ], R[ 1 ] and/C[ 1 ] may be input to the unit cell U_ 1 [ 1 ]. The bits R[ 1 ], R[ 2 ] and C[ 1 ] may be input to the unit cell U_ 1 [ 2 ]. The bits R[ 2 ], R[ 3 ] and/C[ 1 ] may be input to the unit cell U_ 1 [ 3 ]. The bits R[ 3 ], R[ 4 ] and C[ 1 ] may be input to the unit cell U_ 1 [ 4 ]. The bits R[ 4 ], R[ 5 ] and/C[ 1 ] may be input to the unit cell U_ 1 [ 5 ]. The bits R[ 5 ], R[ 6 ] and C[ 1 ] may be input to the unit cell U_ 1 [ 6 ]. The bit R[ 6 ], the ground voltage VSS and the bit/C[ 1 ] may be input to the unit cell U_ 1 [ 7 ]. 
     As with the first unit cells  311  and  312 , in the first unit cells  313 , the power supply voltage VDD, the bit R[ 0 ] and the bit C[ 2 ] may be input to the unit cell U_ 2 [ 0 ]. The bits R[ 0 ], R[ 1 ] and/C[ 2 ] may be input to the unit cell U_ 2 [ 1 ]. The bits R[ 1 ], R[ 2 ] and C[ 2 ] may be input to the unit cell U_ 2 [ 2 ]. The bits R[ 2 ], R[ 3 ] and/C[ 2 ] may be input to the unit cell 
     U_ 2 [ 3 ]. The bits R[ 3 ], R[ 4 ] and C[ 2 ] may be input to the unit cell U_ 2 [ 4 ]. The bits R[ 4 ], R[ 5 ] and/C[ 2 ] may be input to the unit cell U_ 2 [ 5 ]. The bits R[ 5 ], R[ 6 ] and C[ 2 ] may be input to the unit cell U_ 2 [ 6 ]. The bit R[ 6 ], the ground voltage VSS and the bit/C[ 2 ] may be input to the unit cell U_ 2 [ 7 ]. 
     A bit C[ 3 ] corresponding to the first column bit C[m] input to the first unit cells  314  that are located in the fourth column may not exist, and thus the first column bit C[m] input to the first unit cells  314  may be replaced with the ground voltage VSS. Thus, in the first unit cells  314 , the power supply voltage VDD, the bit R[ 0 ] and the ground voltage VSS may be input to the unit cell U_ 3 [ 0 ]. The bit R[ 0 ], the bit R[ 1 ] and the ground voltage VSS may be input to the unit cell U_ 3 [ 1 ]. The bit R[ 1 ], the bit R[ 2 ] and the ground voltage VSS may be input to the unit cell U_ 3 [ 2 ]. The bit R[ 2 ], the bit R[ 3 ] and the ground voltage VSS may be input to the unit cell U_ 3 [ 3 ]. The bit R[ 3 ], the bit R[ 4 ] and the ground voltage VSS may be input to the unit cell U_ 3 [ 4 ]. The bit R[ 4 ], the bit R[ 5 ] and the ground voltage VSS may be input to the unit cell U_ 3 [ 5 ]. The bit R[ 5 ], the bit R[ 6 ] and the ground voltage VSS may be input to the unit cell U_ 3 [ 6 ]. 
     When the bits and voltages are applied to the plurality of unit cells  311 ,  312 ,  313 ,  314  and  350   a  as described above, the digital-to-analog converter  300   a  may operate as follows. 
     First, an example where the phase interpolation operation is performed in the first quadrant will be described. When the phase interpolation code PI_CODE corresponds to zero in decimal, all unit cells may be assigned to the first weight signal W_CLK 0  and the first input clock signal CLK 0 . Whenever the phase interpolation code PI_CODE increases by one, the number of unit cells assigned to the second weight signal W_CLK 90  and the second input clock signal CLK 90  may increase by one, and the number of unit cells assigned to the first weight signal W_CLK 0  and the first input clock signal CLK 0  may decrease by one. 
     For example, an order in which the unit cells are assigned to the second weight signal W_CLK 90  and the second input clock signal CLK 90  may be as follows: (1) the unit cell U_ 0 [ 0 ], (2) the unit cell U_ 1 [ 0 ], (3) the unit cell U_ 2 [ 0 ], (4) the unit cell U_ 3 [ 0 ], (5) the unit cell U_ 2 [ 1 ], (6) the unit cell U_ 1 [ 1 ], (7) the unit cell U_ 0 [ 1 ], (8) the unit cell U_ 3 [ 1 ], (9) the unit cell U_ 0 [ 2 ], (10) the unit cell U_ 1 [ 2 ], (11) the unit cell U_ 2 [ 2 ], (12) the unit cell U_ 3 [ 2 ], (13) the unit cell U_ 2 [ 3 ], (14) the unit cell U_ 1 [ 3 ], (15) the unit cell U_ 0 [ 3 ], (16) the unit cell U_ 3 [ 3 ], (17) the unit cell U_ 0 [ 4 ], (18) the unit cell U_ 1 [ 4 ], (19) the unit cell U_ 2 [ 4 ], (20) the unit cell U_ 3 [ 4 ], (21) the unit cell U_ 2 [ 5 ], (22) the unit cell U_ 1 [ 5 ], (23) the unit cell U_ 0 [ 5 ], (24) the unit cell U_ 3 [ 5 ], (25) the unit cell U_ 0  [ 6 ], (26) the unit cell U_ 1 [ 6 ], (27) the unit cell U_ 2 [ 6 ], (28) the unit cell U_ 3 [ 6 ], (29) the unit cell U_ 2 [ 7 ], (30) the unit cell U_ 1 [ 7 ], (31) the unit cell U_ 0 [ 7 ], and (32) the unit cell U_ 3 [ 7 ]. 
     In this example, in the first, second and third columns, the unit cells may be sequentially added to the second weight signal W_CLK 90  in an order of the first column, the second column and the third column in the first row, and the unit cells may be sequentially added to the second weight signal W_CLK 90  in an order of the third column, the second column and the first column in the second row. In addition, the unit cells may be sequentially added to the second weight signal W_CLK 90  in the order of the first column, the second column and the third column again in the third row, and the unit cells may be sequentially added to the second weight signal W_CLK 90  in the order of the third column, the second column and the first column again in the fourth row. In other words, the unit cells in the first, second and third columns may be added to the second weight signal W_CLK 90  in a zigzag scheme or manner. 
     After that, an example where the phase interpolation operation is performed in the second quadrant will be described. When the phase interpolation code PI_CODE corresponds to 32 in decimal, all unit cells may be assigned to the second weight signal W_CLK 90  and the second input clock signal CLK 90 . Whenever the phase interpolation code PI_CODE increases by one, the number of unit cells assigned to the third weight signal W_CLK 180  and the third input clock signal CLK 180  may increase by one and the number of unit cells assigned to the second weight signal W_CLK 90  and the second input clock signal CLK 90  may decrease by one. 
     For example, an order in which the unit cells are assigned to the third weight signal W_CLK 180  and the third input clock signal CLK 180  may be opposite to the order in which the unit cells are assigned to the second weight signal W_CLK 90  and the second input clock signal CLK 90  in the first quadrant, and may be as follows: (1) the unit cell U_ 3 [ 7 ], (2) the unit cell U_ 0 [ 7 ], (3) the unit cell U_ 1 [ 7 ], (4) the unit cell U_ 2 [ 7 ], (5) the unit cell U_ 3 [ 6 ], (6) the unit cell U_ 2 [ 6 ], (7) the unit cell U_ 1 [ 6 ], (8) the unit cell U_ 0 [ 6 ], (9) the unit cell U_ 3 [ 5 ], (10) the unit cell U_ 0 [ 5 ], (11) the unit cell U_ 1 [ 5 ], (12) the unit cell U_ 2 [ 5 ], (13) the unit cell U_ 3 [ 4 ], (14) the unit cell U_ 2 [ 4 ], (15) the unit cell U_ 1 [ 4 ], (16) the unit cell U_ 0 [ 4 ], (17) the unit cell U_ 3 [ 3 ], (18) the unit cell U_ 0 [ 3 ], (19) the unit cell U_ 1 [ 3 ], (20) the unit cell U_ 2 [ 3 ], (21) the unit cell U_ 3 [ 2 ], (22) the unit cell U_ 2 [ 2 ], (23) the unit cell U_ 1 [ 2 ], (24) the unit cell U_ 0 [ 2 ], (25) the unit cell U_ 3 [ 1 ], (26) the unit cell UAW, (27) the unit cell U_ 1 [ 1 ], (28) the unit cell (U_ 2 [ 1 ], (29) the unit cell U_ 3 [ 0 ], (30) the unit cell U_ 2 [ 0 ], (31) the unit cell U_ 1 [ 0 ], and (32) the unit cell U_ 0 [ 0 ]. 
     After that, the phase interpolation operation in the third quadrant may be similar to that in the first quadrant. After that, the phase interpolation operation in the fourth quadrant may be similar to that in the second quadrant. 
     As described above, only one unit cell may be added to the weight signal whenever the phase interpolation code PI_CODE increases by one and thus the monotonic characteristic may be implemented. 
       FIG. 10  is a circuit diagram illustrating an example of a phase mixer included in a phase interpolator of  FIG. 2 . 
     Referring to  FIGS. 2 and 10 , the phase mixer  400   a  may include a first circuit  410 , a second circuit  420  and an amplifier  430 . The phase mixer  400   a  may further include capacitors Cl, C 2 , and C 3 , resistors R 1  and R 2 , and inverters  441  and  443 . 
     The first circuit  410  may receive the first and third weight signals W_CLK 0  and W_CLK 180 , may operate based on the first and third input clock signals CLK 0  and CLK 180 , and may be connected to a node N 21  and a node N 22 . The first circuit  410  may include transistors  411 ,  413 ,  415  and  417 . 
     The transistor  411  may be connected between the first weight signal W_CLK 0  and the node N 21  and may have a gate electrode receiving the first input clock signal CLK 0 . The transistor  413  may be connected between the first weight signal W_CLK 0  and the node N 22  and may have a gate electrode receiving the third input clock signal CLK 180 . The transistor  415  may be connected between the third weight signal W_CLK 180  and the node 
     N 21  and may have a gate electrode receiving the third input clock signal CLK 180 . The transistor  417  may be connected between the third weight signal W_CLK 180  and the node N 22  and may have a gate electrode receiving the first input clock signal CLK 0 . 
     The second circuit  420  may receive the second and fourth weight signals W_CLK 90  and W_CLK 270 , may operate based on the second and fourth input clock signals 
     CLK 90  and CLK 270  and may be connected to the node N 21  and the node N 22 . The second circuit  420  may include transistors  421 ,  423 ,  425  and  427 . 
     The transistor  421  may be connected between the second weight signal W_CLK 90  and the node N 21  and may have a gate electrode receiving the second input clock signal CLK 90 . The transistor  423  may be connected between the second weight signal W_CLK 90  and the node N 22  and may have a gate electrode receiving the fourth input clock signal CLK 270 . The transistor  425  may be connected between the fourth weighting signal W_CLK 270  and the node N 21  and may have a gate electrode receiving the fourth input clock signal CLK 270 . The transistor  427  may be connected between the fourth weighting signal W_CLK 270  and the node N 22  and may have a gate electrode receiving the second input clock signal CLK 90 . 
     In some example embodiments, the transistors  411 ,  413 ,  415 ,  417 ,  421 ,  423 ,  425  and  427  may be PMOS transistors, however, example embodiments are not limited thereto. 
     Current sources  401 ,  403 ,  405  and  407  illustrated in  FIG. 10  may not be components that are actually included in the phase mixer  400   a , but may conceptually represent that the amount of current of the first, second, third and fourth weight signals W_CLK 0 , W_CLK 90 , W_CLK 180  and W_CLK 270  are changed by the digital-to-analog converter  300   a.    
     The amplifier  430  may be connected to the nodes N 21  and N 22 , and may generate the output clock signal CLK_I and the inversion output clock signal CLK_IB that are a pair of differential signals based on operations of the first and second circuits  410  and  420 . For example, the amplifier  430  may be a current mode logic (CML) amplifier. 
     The capacitor C 1  may be connected between the nodes N 21  and N 22 . The resistor R 1  may be connected between the node N 21  and the ground voltage VSS. The resistor R 2  may be connected between the node N 22  and the ground voltage VSS. The capacitor C 2  and the inverter  441  may be connected in series between an output of the amplifier  430  and an output terminal providing the output clock signal CLK_I. The capacitor C 3  and the inverter  443  may be connected in series between the output of the amplifier  430  and an output terminal providing the inversion output clock signal CLK_IB. 
       FIGS. 11A, 11B, 11C, 11D, 12 and 13  are diagrams for describing an operation of a phase interpolator of  FIG. 2 . 
     Referring to  FIGS. 11A, 11B, 11C, 11D and 12 , the phase interpolation code PI_CODE, the first thermometer code R[ 6 : 0 ], the second thermometer code C[ 2 : 0 ] and the selection signal SEL_IQ[ 1 : 0 ] may be implemented as illustrated. In this example, when the phase interpolation code PI_CODE is changed, only one bit of the outputs of the decoder  200   a  may be toggled as illustrated in  FIG. 12  and thus the glitch-free characteristic may be implemented. 
     Referring to  FIG. 13 , CASE 1  represents a conventional phase interpolator including a digital-to-analog converter that is controlled by a binary code of 5 bits. CASE 2  represents a conventional phase interpolator including a digital-to-analog converter that is controlled by a thermometer code of 7 bits and a binary code of 2 bits. CASES represents a conventional phase interpolator including a digital-to-analog converter that is controlled by a thermometer code of 31 bits. CASE 4  represents the phase interpolator  100   a  of  FIG. 2  according to example embodiments including the digital-to-analog converter  300   a  that is controlled by the two-dimensional thermometer codes including the first thermometer code R[ 6 : 0 ] of 7 bits and the second thermometer code C[ 2 : 0 ] of 3 bits 
     In the conventional phase interpolators such as CASE 1  and CASE 2  in which the digital-to-analog converters are controlled based on a binary code, although the number of control bits is reduced, the DNL characteristic may be deteriorated and the monotonic characteristic and the glitch-free characteristic cannot be guaranteed. In the conventional phase interpolator such as CASE 2  in which the digital-to-analog converter is controlled based on a one-dimensional thermometer code, the DNL characteristic may be better and the monotonic characteristic and the glitch-free characteristic may be obtained, but the number of control bits may be greatly increased. In the phase interpolator  100   a  according to example embodiments such as CASE 4  in which the digital-to-analog converter is controlled based on the two-dimensional thermometer codes, the performance such as the DNL performance, the monotonic characteristic and the glitch-free characteristic may be improved or enhanced even though a relatively small number of control bits are used. 
     Although example embodiments are described based on a specific number of signals, bits, unit cells, and a specific code configuration, example embodiments are not limited thereto. For example, the number of signals, bits, unit cells, and a code configuration may be variously changed according to example embodiments. 
       FIG. 14  is a flowchart illustrating a method of generating a phase interpolation clock signal according to example embodiments. 
     Referring to  FIGS. 1 and 14 , in a method of generating a phase interpolation clock signal according to example embodiments, the first thermometer code TCODE 1 , the second thermometer code TCODE 2  and the selection signal SEL_IQ are generated based on the phase interpolation code PI_CODE (step S 100 ). For example, step S 100  may be performed by the decoder  200  and the phase interpolation code PI_CODE, the first thermometer code 
     TCODE 1 , the second thermometer code TCODE 2  and the selection signal SEL_IQ may be implemented as described with reference to  FIGS. 3, 11 and 12 . 
     Two of the plurality of weight signals W_CLK are determined as the first and second target weight signals based on the selection signal SEL_IQ, and the amount of current of the first and second target weight signals are adjusted by controlling the plurality of unit cells  310  and  350  based on the first and second thermometer codes TCODE 1  and TCODE 2  and the selection signal SEL_IQ (step S 200 ). For example, step S 200  may be performed by the digital-to-analog converter  300 , the plurality of unit cells  310  and  350  may include the first unit cell  310  and the second unit cell  350  that are different types, and the first and second unit cells  310  and  350  may be implemented as described with reference to  FIGS. 1, 5, 6, 7, 8 and 9 . 
     Two of the plurality of input clock signals CLK are determined as the first and second target clock signals corresponding to the first and second target weight signals, and the output clock signal OCLK is generated based on the first and second target weight signals and the first and second target clock signals (e.g., by performing the phase interpolation operation on the first and second target clock signals based on the first and second target weight signals) (step S 300 ). For example, step S 300  may be performed by the phase mixer  400 , and the output clock signal OCLK may be generated to have the glitch-free characteristic and the monotonic characteristic. 
     As will be appreciated by those skilled in the art, the disclosure may be embodied as a system, method, computer program product, and/or a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. The computer readable program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, the computer readable medium may be a non-transitory computer readable medium. 
       FIG. 15  is a block diagram illustrating a communication device and a communication system including the communication device according to example embodiments. 
     Referring to  FIG. 15 , a communication system  900  includes a communication channel  901 , a first communication device  910  and a second communication device  920 . 
     The first communication device  910  and the second communication device  920  may communicate with each other. Each of the first communication device  910  and the second communication device  920  may be a processing device including a computer, a network element (e.g., a router and switches), a portable communication device, or the like. 
     The first communication device  910  includes a phase interpolator  912  and a data sampler  914 . The first communication device  910  may further include a clock generator  911 , a receiver  913 , a data processor  915 , and a memory  916 . The second communication device  920  may include a data processor  921 , a memory  922 , and a transmitter  923 . For example, each of the data processors  915  and  921  may be a microprocessor, a central processing unit (CPU), or the like. For example, each of the memories  916  and  922  may include a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), a static access memory (SRAM), or the like. 
     In the second communication device  920 , the data processor  921  may perform a data processing operation on data to be transmitted using the memory  922 . The transmitter  923  may output the data on which the data processing operation is performed through the channel  901  in the form of a data stream. 
     In the first communication device  910 , the receiver  913  may receive an input data stream and may provide the received input data stream to the data sampler  914 . The clock generator  911  may generate a plurality of input clock signals CLK. For example, the clock generator  911  may include a phase locked loop (PLL) circuit and/or a delay locked loop 
     (DLL) circuit. The phase interpolator  912  may generate a phase interpolation clock signal PI_CLK based on a phase interpolation code PI_CODE and the plurality of input clock signals CLK. The phase interpolator  912  may be the phase interpolator according to example embodiments and may be implemented as described with reference to  FIGS. 1 through 14 . The data sampler  914  may generate sample data by sampling the input data stream based on the phase interpolation clock signal PI_CLK. For example, the data sampler  914  may generate the sample data by performing a data sampling operation multiple times. The data processing unit  915  may perform a data processing operation on the sample data using the memory  916 . 
       FIG. 16  is a block diagram illustrating a communication device according to example embodiments. 
     Referring to  FIG. 16 , a communication device  1000  may include a clock generator  1200  and a clock and data recovery (CDR) loop circuit  1400 . For example, the communication device  1000  may be a CDR device. The CDR loop circuit  1400  may include a phase interpolator  1410 , a data sampler  1420  and a CDR loop control circuit  1430 . 
     The clock generator  1200  may generate a plurality of input clock signals CLK based on a crystal reference clock signal CCLK that is received from outside (e.g., from an oscillator located outside the communication device  1000 ). For example, the clock generator  1200  may include a PLL circuit and/or a DLL circuit. The phase interpolator  1410  may generate a phase interpolation clock signal PI_CLK based on a loop control signal 
     LCS received from the CDR loop control circuit  1430 , a phase interpolation code PI_CODE, and the plurality of input clock signals CLK. The phase interpolator  1410  may be the phase interpolator according to example embodiments and may be implemented as described with reference to  FIGS. 1 through 14 . The data sampler  1420  may receive an input data stream DAT_STREAM from an outside (e.g., from another communication device) and may perform a sampling operation on the input data stream DAT_STREAM based on the phase interpolation clock signal PI_CLK to generate sample data DAT_SAM. 
     The CDR loop control circuit  1430  may generate the loop control signal LCS based on a result of performing clock and data recovery operations. For example, the CDR loop control circuit  1430  may determine whether the phase interpolation clock signal PI_CLK generated from the phase interpolator  1410  is located in the center of the sample data DAT_SAM based on  4  phases sample data DAT_SAM. As a result of the determination, the CDR loop control circuit  1430  may generate the loop control signal LCS. Based on the above-described CDR loop operation, the phase interpolator  1410  may generate a recovery clock signal RCVD_CLK and may provide the recovery clock signal RCVD_CLK to the data sampler  1420 . The data sampler  1420  may generate recovery data RCVD_DAT based on the recovery clock signal RCVD_CLK. As such, the CDR loop circuit  1400  may generate the recovery clock signal RCVD_CLK and the recovery data RCVD_DAT and may provide the recovery clock signal RCVD_CLK and the recovery data RCVD_DAT to a processor of the communication device  1000  (not illustrated). 
     The disclosure may be applied to various electronic devices and systems that include the phase interpolators and the communication devices. For example, the disclosure may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, etc. 
     As is traditional in the field, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the disclosure. An aspect of an embodiment may be achieved through instructions stored within a non-transitory storage medium and executed by a processor. 
     The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.