Patent Publication Number: US-11037899-B2

Title: Package structures and methods of forming the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 16/403,641, filed on May 6, 2019. The prior application Ser. No. 16/403,641 is a continuation application of and claims the priority benefits of U.S. application Ser. No. 15/159,810, filed on May 20, 2016, now issued as U.S. Ser. No. 10,283,479B2. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area. 
     These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of the type of packages for semiconductors include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices. Some 3DICs are prepared by placing chips over chips on a semiconductor wafer level. The 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked chips. However, there are many challenges related to 3DICs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  illustrates a flow chart of a method of forming a package structure in accordance with some embodiments. 
         FIG. 2A  to  FIG. 2I  illustrate cross-sectional views of a method of forming a package structure in accordance with some embodiments. 
         FIG. 3  illustrates a simplified view of a package structure in accordance with some embodiments. 
         FIG. 4  illustrates a simplified top view of a package structure in accordance with alternative embodiments. 
         FIG. 5A  illustrates a cross-sectional view of a package structure in accordance with alternative embodiments. 
         FIG. 5B  illustrates a simplified top view of a package structure of  FIG. 5A . 
         FIG. 6  illustrates a cross-sectional view of a package structure in accordance with alternative embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below for the purposes of conveying the present disclosure in a simplified manner. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the same reference numerals and/or letters may be used to refer to the same or similar parts in the various examples the present disclosure. The repeated use of the reference numerals is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “over”, “above”, “upper” and the like, may be used herein to facilitate the description of one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the Figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. 
       FIG. 1  illustrates a flow chart of a method of forming a package structure in accordance with some embodiments.  FIG. 2A  to  FIG. 2I  illustrate cross-sectional views of a method of forming a package structure in accordance with some embodiments. 
     Referring to  FIG. 1  and  FIG. 2A , at step  10 , a carrier  100  is provided. 
     In some embodiments, the carrier  100  has a package area  101  including an integrated circuit area  102  and a periphery area  104  aside the integrated circuit area  102 . In some embodiments, the periphery area  104  surrounds the integrated circuit area  102 . In some embodiments, the carrier  100  may have a glue layer (not shown) thereon for de-bond usage. In some embodiments, the carrier  100  may be a glass carrier, and the glue layer may be a Ultra-Violet (UV) glue layer or a Light-to-Heat Conversion (LTHC) glue layer. In some embodiments, the glue layer is even protected by forming a polymer layer thereon. The polymer material may be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof and/or the like. 
     Referring to  FIG. 1  and  FIG. 2B , at step  20 , at least one dummy substrate DS is placed on the carrier  100 . 
     In some embodiments, the dummy substrate DS includes a group IV element or a group III-V semiconductor compound, such as Si, Ge, SiGe, GaAs, InAs, InGaAs, or the like. In some embodiments, the dummy substrate DS includes silicon substrate or a substrate formed of other suitable semiconductor materials. In some embodiments, the dummy substrate DS is provided with a glue layer  110 . In some embodiments, the glue layer  110  is formed of an adhesive such as a die attach film (DAF), epoxy, silver paste, or the like, although other types of adhesives may be used. 
     Referring to  FIG. 1  and  FIG. 2C , at step  30 , at least one first integrated circuit C 1  is placed on the carrier  100  in a manner such that a bottom b 1  of the first integrated circuit C 1  and a bottom b 2  of the dummy substrate DS are arranged to together form a rotationally symmetrical shape sp (shown in  FIG. 3 ). In some embodiments, in a first direction D 1 , the first integrated circuit C 1  is picked and placed on the carrier  100 . In some embodiments, the first integrated circuit C 1  is provided with a glue layer  112 . In some embodiments, the first integrated circuit C 1  and the dummy substrate DS are separated by a distance d in a second direction D 2  perpendicular to the first direction D 1 . In some embodiments, the step of placing the first integrated circuit C 1  is after the dummy substrate DS is placed on the carrier  100 . In alternative embodiments, the step of placing the first integrated circuit C 1  is before the dummy substrate DS is placed on the carrier  100 . 
     Referring to  FIG. 1  and  FIG. 2C , at step  40 , at least one second integrated circuit C 2  is placed on the dummy substrate DS. In some embodiments, in the first direction D 1 , the second integrated circuit C 2  is picked and placed on the dummy substrate DS. In some embodiments, the second integrated circuit C 2  is provided with a glue layer  114 . In some embodiments, the step of placing the second integrated circuit C 2  is after the first integrated circuit C 1  is placed on the carrier  100 . In alternative embodiments, the step of placing the second integrated circuit C 2  is before the first integrated circuit C 1  is placed on the carrier  100 . 
     In some embodiments, each of the first and second integrated circuits C 1 , C 2  is, for example, a die, and includes an interconnection  122 , a pad  124  and a connector  126 . The interconnection  122  is formed over a substrate  120 . In some embodiments, the glue layer  114  is disposed between the substrate  120  of the second integrated circuit C 2  and the dummy substrate DS. The substrate  120  includes, for example but not limited to, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The pad  124  is formed over and electrically connected to the interconnection  122 . In some embodiments, each of the first and second integrated circuits C 1 , C 2  includes an active surface (not shown), the pad  124  is distributed on the active surface. The connector  126  is formed over and electrically connected to the pad  124 . In some embodiments, the connector  126  is formed as the top portion of each of the first and second integrated circuits C 1 , C 2 . The connector  126  protrudes from the remaining portion or lower portion of each of the first and second integrated circuits C 1 , C 2 . The connector  126  can be electrical connectors, dummy connectors or both. The connector  126  include solder bumps, gold bumps, copper posts or the like. In some embodiments, the connector  126  is a copper bump. In some embodiments, the pad  124  is partially exposed by a passivation layer  128 , and the connector  126  is encapsulated by a protection layer  130 . 
     In some embodiments, a coefficient of thermal expansion (CTE) of the dummy substrate DS is similar to a CTE of the substrate  120  of at least one of the first integrated circuit C 1  disposed adjacent thereto and the second integrated circuit C 2  disposed thereon. In some embodiments, the CTE of the dummy substrate DS is, for example, substantially equal to the CTE of the substrate  120  of at least one of the first and second integrated circuits C 1 , C 2 . In some embodiments, a material of the dummy substrate DS may be the same with the substrate  120  of at least one of the first and second integrated circuits C 1 , C 2 . In alternative embodiments, a material of the dummy substrate DS may be different from the substrate  120  of at least one of the first and second integrated circuits C 1 , C 2 . In alternative embodiments, the dummy substrate DS may have a CTE similar to or substantially equal to an effective CTE of at least one of the first and second integrated circuits C 1 , C 2 . 
     In some embodiments, a thickness T 1  of the first integrated circuit C 1  is substantially equal to a total thickness of a thickness T of the dummy substrate DS, a thickness T 2  of the second integrated circuit C 2  disposed thereon and a thickness T 3  of the glue layer  114 , that is, T 1 =T 2 +T+T 3 . In some embodiments, before placing the first and second integrated circuits C 1 , C 2 , a grinding process is performed on at least one of the first and second integrated circuits C 1 , C 2 . In alternative embodiments, each of the first and second integrated circuits C 1 , C 2  is a package having a die and an encapsulant aside the die and having a determined thickness. 
       FIG. 3  illustrates a simplified view of a package structure of  FIG. 2C  in accordance with some embodiments. Referring to  FIG. 3 , the bottom of the first integrated circuit C 1  and the bottom of the dummy substrate DS are arranged to together form the rotationally symmetrical shape sp. It is note that the term “the rotationally symmetrical shape” means a shape substantially having rotational symmetry and a shape substantially composed of a shape of the bottom of the first integrated circuit C 1 , a shape of the bottom of the dummy substrate DS and a shape of a gap therebetween. In some embodiments, the rotationally symmetrical shape sp is substantially a rectangle. In alternative embodiments, the rotationally symmetrical shape sp may be a square or a regular polygon. In some embodiments, the package area  101  is substantially a rotationally symmetrical shape such as a rectangle. In some embodiments, a center of the rotationally symmetrical shape sp forming by the bottom of the first integrated circuit C 1  and the bottom of the dummy substrate DS is overlapped with a center of the package area  101 . Accordingly, distances between the rotationally symmetrical shape sp and opposite borders  101   a - 101   d  of the package area  101  are respectively the same. In detail, the package area  101  has borders  101   a - 101   d , the border  101   a  is opposite to the border  101   b , and the border  101   c  is opposite to the border  101   d . In some embodiments, a distance d 1  between the border  101   a  and the rotationally symmetrical shape sp is substantially equal to a distance d 1 ′ between the opposite border  101   b  and the rotationally symmetrical shape sp. In some embodiments, a distance d 2 ′ between the border  101   c  and the rotationally symmetrical shape sp is substantially equal to a distance d 2  between the opposite border  101   d  and the rotationally symmetrical shape sp. In alternative embodiments, for better wafer and package warpage control, the distances d 1 , d 1 ′, d 2 , d 2 ′ between the borders  101   a - 101   d  and the rotationally symmetrical shape sp are the same, that is, d 1 =d 1 ′=d 2 =d 2 ′. 
     In some embodiments, in a third direction D 3  perpendicular to the second direction D 2 , a width W 1  of the first integrated circuit C 1  is, for example, larger than a width W 2  of the second integrated circuit C 2 . In some embodiments, in the third direction D 3 , a width W of the dummy substrate DS is, for example, substantially equal to the width W 1  of the first integrated circuit C 1 . 
     In some embodiments, the first integrated circuit C 1  includes a first side s 1 , a second side s 2  adjacent to the first side s 1 , and a third side s 3  opposite to the second side s 2 , wherein the first side s 1  has the width W 1 . The dummy substrate DS includes a first side s 1 , a second side s 2  adjacent to the first side s 1 , and a third side s 3  opposite to the second side s 2 , wherein the first side s 1  has the width W. In some embodiments, the first integrated circuit C 1  and the dummy substrate DS are arranged together form the rotationally symmetrical shape sp by aligning the second side s 2  of the first integrated circuit C 1  and the second side s 2  of the dummy substrate DS in the second direction D 2  with the distance d therebetween. Accordingly, a distance d 1  between the border  101   a  of the package area  101  and the second side s 2  of the first integrated circuit C 1  is substantially equal to a distance d 1  between the border  101   a  of the package area  101  and the second side s 2  of the dummy substrate DS. In some embodiments, the distance d 1 ′ between the border  101   b  of the package area  101  and the third side s 3  of the first integrated circuit C 1  is substantially equal to a distance d 1 ′ between the border  101   b  of the package area  101  and the third side s 3  of the first integrated circuit C 1 . In some embodiments, the distance d 1  is substantially equal to the distance d 1 ′. In some embodiments, a distance d 2  between the border  101   d  of the package area  101  and the first side s 1  of the first integrated circuit C 1  is substantially equal to a distance d 2 ′ between the border  101   c  of the package area  101  and the first side s 1  of the dummy substrate DS. 
     Referring to  FIG. 1  and  FIG. 2D , at step  50 , an encapsulant  140  is formed in the integrated circuit area  102  and the periphery area  104  to encapsulate the first integrated circuit C 1 , the second integrated circuit C 2  and the dummy substrate DS. A material of the encapsulant  140  may include molding compound materials including resin and filler, a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), any combination thereof and/or the like. In alternative embodiments, the insulating material may be formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), any combination thereof and/or the like. In some embodiments, the CTE of the dummy substrate DS is significantly lower than a CTE of the encapsulant  140 . 
     In some embodiments, a forming method of the encapsulant  140  includes the following steps. An insulating material is formed on the carrier  100  across the integrated circuit area  102  and the periphery area  104 , to cover the first and second integrated circuits C 1 , C 2  and the dummy substrate DS. In some embodiments, the insulating material is a molding compound formed by molding process. Then, the insulating material is grinded until the top surfaces of the connectors  126  and the top surfaces of the protection layers  130  are exposed. After the insulating material is grinded, an encapsulant  140  is formed. In some embodiments, the connectors  126  and the protection layers  130  of the first and second integrated circuits C 1 , C 2  are not revealed and are well protected by the insulating material during the formation of the insulating material. As shown in  FIG. 2D , it is noted that the top surface of the encapsulant  140 , the top surfaces of the connectors  126 , and the top surfaces of the protection layers  130  are substantially coplanar. In alternative embodiments, the protective layer  130  may cover the top surfaces of the connectors  126 , and the portions of the protection layer  130  are grinded during the grinding process of the insulating material. 
     Referring to  FIG. 2E , a dielectric layer  150  is formed on the top surfaces of the first and second integrated circuits C 1 , C 2  and the top surface of the encapsulant  140 . The dielectric layer  150  includes at least one contact opening  152 . In some embodiments, a plurality of contact opening  152  for exposing the top surfaces of the connectors  126  are formed in the dielectric layer  150 . It is noted that the number of the contact openings  152  is corresponding to the number of the connectors  126 . In some embodiments, the dielectric layer  150  is a polybenzoxazole (PBO) layer, for example. 
     Then, a plurality of conductive through vias  160  is formed on the dielectric layer  150  to electrically connect to the connectors  126  through the contact openings  152 . In some embodiments, the plurality of conductive through vias  160  is formed by photolithography, plating, and photoresist stripping process. For example, the conductive through vias  160  include copper posts. 
     Referring to  FIG. 1  and  FIG. 2F , at step  60 , at least one third integrated circuit C 3  is placed over the first and second integrated circuits C 1 , C 2 . In some embodiments, the third integrated circuit C 3  is picked and placed on the dielectric layer  150 . In some embodiments, the third integrated circuit C 3  is provided with a glue layer  170 . Then, an encapsulant  180  is formed over the dielectric layer  150  to cover the third integrated circuit C 3  and the conductive through vias  160 . In some embodiments, the third integrated circuit C 3  is a die having a structure similar to the first and second integrated circuits C 1 , C 2 . In alternative embodiments, the third integrated circuit C 3  is a package having a die and an encapsulant aside the die. In some embodiments, the method of forming the encapsulant  180  is similar to the method of forming the encapsulant  140 , so the details are not iterated herein. As shown in  FIG. 2F , it is noted that the top surfaces of the conductive through vias  160 , the top surface of the encapsulant  180 , and the top surfaces of the connector  126  and the protection layer  130  of the third integrated circuit C 3  are substantially coplanar. 
     As shown in  FIG. 2E  and  FIG. 2F , the third integrated circuit C 3  is picked and placed on the dielectric layer  150  after the formation of the conductive through vias  160 . However, the disclosure is not limited thereto. In alternative embodiments, the third integrated circuit C 3  is picked and placed on the dielectric layer  150  before the formation of the conductive through vias  160 . In some embodiments, the first, second and third integrated circuits C 1 , C 2 , C 3  may be memory chips, such as a DRAM, SRAM, NVRAM, or logic circuits. In this embodiment, the first and second integrated circuits C 1 , C 2  are memory chips, and the third integrated circuit C 3  is a logic circuit. 
     Referring to  FIG. 2G , after the encapsulant  180  is formed, a redistribution circuit structure RDL electrically connected to the connector  126  of the third integrated circuit C 3  is formed on the top surfaces of the conductive through vias  160 , the top surface of the encapsulant  180 , the top surface of the connectors  126 , and the top surface of the protection layer  130 . The redistribution circuit structure RDL is fabricated to electrically connect with at least one connector underneath. Here, the afore-said connector(s) may be the connector  126  of the third integrated circuit C 3  and/or the conductive through vias  160  in the encapsulant  180 . The fabrication of the redistribution circuit structure RDL includes the following steps. First, a dielectric layer  200 - 1  is formed on the encapsulant  180  and the protection layer  130 , wherein openings  200  in the dielectric layer  200 - 1  expose the connector  126  and the conductive through vias  160 . Then, patterned conductive layers  210 - 1  are formed in the openings  200  of the dielectric layer  200 - 1  to electrically connect to the connector  126  and the conductive through vias  160 , respectively. In some embodiments, a dielectric layer  200 - 2  is formed on the dielectric layer  200 - 1 , wherein openings  200  in the dielectric layer  200 - 2  expose the patterned conductive layers  210 - 1 . Thereafter, patterned conductive layers  210 - 2  are formed in the openings  200  of the dielectric layer  200 - 2  to electrically connect to the patterned conductive layers  210 - 1 . In some embodiments, a dielectric layer  200 - 3  is formed on the dielectric layer  200 - 2 , and an opening  200  in the dielectric layer  200 - 3  exposes the patterned conductive layer  210 - 2 . In other words, after the dielectric layer  200 - 1  and the patterned conductive layer  210 - 1  are formed, steps of forming the dielectric layer and the patterned conductive layers can be repeated at least one time so as to fabricate the redistribution circuit structure RDL over the third integrated circuit C 3  and the encapsulant  180 . The redistribution circuit structure RDL includes a plurality of dielectric layers and a plurality of patterned conductive layers stacked alternately. 
     As shown in  FIG. 2G , in some embodiments, the topmost patterned conductive layer of the redistribution circuit structure RDL may include at least one under-ball metallurgy (UBM) pattern  212  for electrically connecting with conductive ball and/or at least one connection pad (not shown) for electrically connecting with at least one passive component. The number of the under-ball metallurgy pattern  212  and the connection pad is not limited in this disclosure. 
     Referring to  FIG. 2H , after the redistribution circuit structure RDL is formed, a conductive ball  214  is placed on the under-ball metallurgy pattern  212 , and a plurality of passive components (not shown) are mounted on the connection pads. In some embodiments, the conductive ball  214  may be placed on the under-ball metallurgy pattern  212  by ball placement process, and the passive components may be mounted on the connection pads through reflow process. 
     In some embodiments, the third integrated circuit C 3 , the encapsulant  180 , the redistribution circuit structure RDL and the conductive ball  214  are sequentially formed over the carrier  100 . However, the disclosure is not limited thereto. In alternative embodiments, a package structure including the third integrated circuit C 3 , the encapsulant  180 , the redistribution circuit structure RDL and the conductive ball  214  are pre-formed on another carrier, and the package structure is de-bonded from the carrier and electrically connected to a package structure of  FIG. 2D . 
     Referring to  FIG. 2H  and  FIG. 2I , after the conductive ball  214  is formed, the carrier  100  is removed. In some embodiments, the formed structure is de-bonded from the glue layers (not shown) such that the formed structure is separated from the carrier  100 . In some embodiments, the formed structure is peeled from the carrier  100  and the glue layer  110  and the glue layer  112  are retained underneath the dummy substrate DS and the first integrated circuit C 1  respectively. In alternative embodiments, the formed structure de-bonded from the carrier  100  may be electrically connected to another package. 
     Conventionally, packaging the integrated circuits having different sizes may induce asymmetric wafer warpage and surface defects such as crystal originated pits. In some embodiments, by adding the dummy substrate and arranging the dummy substrate and the first integrated circuit to together form the rotationally symmetrical shape, the size difference between the first and second integrated circuits is compensated. Accordingly, a better wafer warpage is obtained and surface defects such as crystal originated pits are prevented. 
       FIG. 4  illustrates a simplified top view of a package structure in accordance with alternative embodiments. Referring to  FIG. 4 , in some embodiments, a package structure includes a first integrated circuit C 1 , a plurality of second integrated circuits C 2  and a plurality of dummy substrates DS. In some embodiments, the first integrated circuit C 1  and the second integrated circuits C 2  have different widths from one other, wherein the second integrated circuits C 2  are respectively disposed over the dummy substrates DS. In some embodiments, the first integrated circuit C 1  and the dummy substrates DS are arranged to together form a rotationally symmetrical shape sp. In some embodiments, the rotationally symmetrical shape sp is a rectangle, for example. In some embodiments, distances d 1 , d 1 ′, d 2 , d 2 ′ between the rotationally symmetrical shape sp and borders  101   a ,  101   b ,  101   d  and  101   c  of a package region  101  are respectively constant. In some embodiments, the distance d 1  is substantially equal to the distance d 1 ′, and the distance d 2  is substantially equal to the distance d 2 ′. In some embodiments, one first integrated circuit C 1  is disposed on the carrier  100 . However, the number of the first integrated circuit C 1  is not limited in this disclosure. In alternative embodiments, a plurality of the first integrated circuits C 1  and at least one dummy substrates DS are arranged to together form a rotationally symmetrical shape. In alternative embodiments, for better wafer and package warpage control, the distances d 1 , d 1 ′, d 2 , d 2 ′ between the borders  101   a - 101   d  and the rotationally symmetrical shape sp are the same, that is, d 1 =d 1 ′=d 2 =d 2 ′. 
     In some embodiments, by adding the dummy substrates and arranging the dummy substrates and the first integrated circuit to together form the rotationally symmetrical shape, the size difference between the first and second integrated circuits is compensated. Accordingly, a better wafer warpage is obtained and surface defects such as crystal originated pits are prevented. 
     The above embodiments illustrate examples where the first integrated circuit C 1  on the carrier  100  and the second integrated circuit C 2  on the dummy substrate DS have different sizes (e.g., widths). However, it should be noted that the disclosure is not limited thereto.  FIG. 5A  illustrates a cross-sectional view of a package structure in accordance with alternative embodiments, and  FIG. 5B  illustrates a simplified top view of a package structure of  FIG. 5A . Referring to  FIG. 5A  and  FIG. 5B , in some embodiments, a package structure includes at least one first integrated circuit C 1 , at least one second integrated circuit C 2  and at least one dummy substrate DS disposed in an integrated circuit region  102 . In some embodiments, the first integrated circuit C 1  and the second integrated circuit C 2  have a substantially identical width W, W 1  and have different thicknesses T 1 , T 2 . In some embodiments, the second integrated circuit C 2  having a smaller thickness T 2  than the first integrated circuit C 1  is disposed on the dummy substrate DS having a thickness T. In some embodiments, the thickness T of the dummy substrate DS is substantially equal to a thickness difference between the first and second integrated circuits C 1 , C 2  subtracting a thickness T 3  of the glue layer  114 . In some embodiments, the dummy substrate DS and the second integrated circuit C 2  have a substantially identical width W. In other words, a total thickness of the thickness T of the dummy substrate DS, the thickness T 2  of the second integrated circuit C 2  and the thickness T 3  of the glue layer  114  is substantially equal to the thickness T 1  of the first integrated circuit C 1 , that is, T 1 =T 2 +T+T 3 . Accordingly, a top surface of the second integrated circuit C 2  is substantially coplanar with a top surface of the first integrated circuit C 1 . In some embodiments, each of the first and second integrated circuits C 1 , C 2  is a package or a chip having a determined thickness and difficult to be processed by reducing thickness process such as grinding. In alternative embodiments, the first and second integrated circuits C 1 , C 2  are dies. 
     In some embodiments, the dummy substrate DS compensates the thickness difference between the first and second integrated circuits C 1 , C 2 , and thus subsequent processes such as placing a third integrated circuit C 3  thereon may be performed on a substantially planar surface. 
     The above embodiments illustrate examples where the connector  126  of the first and second integrated circuit C 1 , C 2  is directly connected to the through vias  160 . However, it should be noted that the disclosure is not limited thereto. In some embodiments, as shown in  FIG. 6 , a redistribution circuit structure RDL′ is further disposed between the connector  126  of the first and second integrated circuit C 1 , C 2  and the through vias  160 . In some embodiments, the redistribution circuit structure RDL′ includes a first dielectric layer  300 - 1  and patterned conductive layers  310 - 1  disposed therein and thereon. In some embodiments, the method of forming the redistribution circuit structure RDL′ is similar to the method of forming the redistribution circuit structure RDL, so the details are not iterated herein. 
     In view of the above, the present disclosure provides a package structure including at least one first integrated circuit, at least one second integrated circuit and at least one dummy substrate, wherein the second integrated circuit is disposed on the dummy substrate. In some embodiments, the first and second integrated circuits have different sizes, and the dummy substrate and the first integrated circuit are arranged to together form a rotationally symmetrical shape. Therefore, the size difference between the first and second integrated circuits is compensated by the dummy substrate. Accordingly, a better wafer warpage is obtained and surface defects such as crystal originated pits are prevented. In alternative embodiments, the first and second integrated circuits have different thickness, and a total thickness of the dummy substrate and the second integrated circuit is substantially equal to a thickness of the first integrated circuit. Accordingly, top surfaces of the first and second integrated circuits are substantially coplanar with one another since the dummy substrate compensates the thickness difference between the first and second integrated circuits, and subsequent processes may be performed on a substantially planar surface. 
     In accordance with some embodiments of the present disclosure, a package structure includes a first die, a second die, a dummy substrate and an encapsulant. A bottom surface of the second die is adhered to a top surface of the dummy substrate through a glue layer, and a total area of the bottom surface of the second die is different from a total area of the top surface of the dummy substrate. A total thickness of the first die is substantially equal to a total thickness of the second die, the dummy substrate and the glue layer. The encapsulant is disposed aside the first die, the second die and the dummy substrate. 
     In accordance with alternative embodiments of the present disclosure, a package structure includes a first die, a second die, a dummy substrate and an encapsulant. A bottom surface of the second die is adhered to a top surface of the dummy substrate through a glue layer. A first surface of the glue layer is adhered to the bottom surface of the second die, and a total area of the first surface of the glue layer is substantially equal to a total area of the bottom surface of the second die. A top surface of the second die is substantially coplanar with a top surface of the first die. The encapsulant is disposed aside the first die, the second die and the dummy substrate. 
     In accordance with yet alternative embodiments of the present disclosure, a method of forming a package structure includes at least the following steps. A first die is placed on the carrier. A dummy substrate is placed on a carrier. A second die is adhered onto the dummy substrate through a glue layer. A bottom surface of the second die is adhered to a top surface of the dummy substrate, a total area of the bottom surface of the second die is substantially equal to a total area of a surface of the glue layer. A top surface of the second die is substantially coplanar with a top surface of the first die. An encapsulant is formed to encapsulate the first die, the second die and the dummy substrate. 
     In accordance with some embodiments of the present disclosure, a package structure includes a first die, at least one second die, a semiconductor substrate and a glue layer. The semiconductor substrate includes no active devices. The glue layer is disposed between the at least one second die and the semiconductor substrate. The glue layer has a top surface adhered to the least one second die and a bottom surface adhered to a topmost surface of the semiconductor substrate. A total area of the bottom surface of the glue layer is substantially equal to a total area of the topmost surface of the semiconductor substrate, and a total thickness of the first die is substantially equal to only a total thickness of the at least one second die, the semiconductor substrate and the glue layer. 
     In accordance with some embodiments of the present disclosure, a package structure includes a first die, at least one second die, a semiconductor substrate and at least one glue layer. The semiconductor substrate includes no active devices. The glue layer is disposed between the at least one second die and the semiconductor substrate. The glue layer has a top surface adhered to a bottom surface of the least one second die and a bottom surface adhered to a topmost surface of the semiconductor substrate. A total area of the top surface of the at least one glue layer is substantially equal to a total area of the bottom surface of the least one second die, and a total thickness of the first die is substantially equal to only a total thickness of the at least one second die, the semiconductor substrate and the at least one glue layer. 
     In accordance with some embodiments of the present disclosure, a method of forming a package structure includes at least the following steps. A first die is placed on a carrier. A semiconductor substrate including no active elements is placed on the carrier. A bottom surface of at least one second die is adhered onto a topmost surface of the semiconductor substrate through at least one glue layer. A top surface of the at least one glue layer is adhered to the bottom surface of the at least one second die, a total area of the top surface of the at least one glue layer is substantially equal to a total area of the bottom surface of the least one second die, and a total thickness of the first die is substantially equal to only a total thickness of the at least one second die, the semiconductor substrate and the at least one glue layer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.