Patent Publication Number: US-2010123412-A1

Title: Pulse generating circuit

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a high-voltage pulse generating circuit which is capable of providing a high-voltage pulse. 
       FIG. 8  shows a high-voltage pulse generating circuit  100  which is disclosed in Japanese Patent Publication Application No. 2005-295667. The high-voltage pulse generating circuit  100  is designed to provide a high-voltage pulse for generating plasma. As shown in  FIG. 8 , the high-voltage pulse generating circuit  100  includes a direct current power source  102 , an inductor  104 , a first semiconductor switch  106 , a second semiconductor switch  108  and a diode  110 . The inductor  104 , the first semiconductor switch  106  and the second semiconductor switch  108  are connected in series between the ends of the direct current power source  102 . One end of the inductor  104  is connected to the anode of the first semiconductor switch  106 , and the other end of the inductor  104  is connected to the cathode of the diode  110 . The anode of the diode  110  is connected to the gate of the first semiconductor switch  106 . 
     When the second semiconductor switch  108  is turned on and in the conductive state, the first semiconductor switch  106  is also in the conductive state. Consequently, voltage of the direct current power source  102  is applied to the inductor  104 , so that induction energy is stored in the inductor  104 . Then, the second semiconductor switch  108  is turned off, and the first semiconductor switch  106  is turned off rapidly. Thus, a high-voltage pulse PL is generated in the inductor  104 , and outputted therefrom through output terminals  112 ,  114 . 
     However, the above Publication provides no description about decreasing the pulse width of the high-voltage pulse generated by the high-voltage pulse generating circuit  100 . Since the controlling for the pulse width of the high-voltage pulse solely depends on the characteristics of each circuit element, the pulse width cannot be decreased in the high-voltage pulse generating circuit  100 . 
     The present invention is directed to a high-voltage pulse generating circuit which is capable of providing a high-voltage pulse whose width is relatively narrow. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a high-voltage pulse generating circuit includes a direct current power source, a transformer, a switching device and a switching control circuit. The transformer includes a primary winding and a secondary winding. The switching device is connected between the direct current power source and the primary winding. The switching control circuit controls the switching device to be in the non-conductive state after the switching device is set in the conductive state during first conductive time and further controls the switching device to be in the conductive state during second conductive time after one of the voltages of the primary winding and the secondary winding pass the predetermined value and to be in the non-conductive state. 
     Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
         FIG. 1  is a circuit diagram showing a high-voltage pulse generating circuit  1  according to a first preferred embodiment of the present invention; 
         FIG. 2  is a waveform diagram of a pulse generated by the high-voltage pulse generating circuit  1  of  FIG. 1 ; 
         FIG. 3  is a circuit diagram showing a high-voltage pulse generating circuit  1 A according to a second preferred embodiment of the present invention; 
         FIG. 4  is a waveform diagram of a pulse generated by the high-voltage pulse generating circuit  1 A of  FIG. 3 ; 
         FIG. 5  is a circuit diagram showing a high-voltage pulse generating circuit  1 C according to a third preferred embodiment of the present invention; 
         FIG. 6  is a waveform diagram of a pulse generated by the high-voltage pulse generating circuit  1 C of  FIG. 5 ; 
         FIG. 7  is a circuit diagram showing a high-voltage pulse generating circuit  1 B according to an another embodiment of the present invention; and 
         FIG. 8  is a circuit diagram showing the high-voltage pulse generating circuit  100  according to the background art. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following will describe a high-voltage pulse generating circuit according to a first preferred embodiment of the present invention with reference to  FIGS. 1 and 2 .  FIG. 1  is a circuit diagram of the high-voltage pulse generating circuit  1  according to the first preferred embodiment of the present invention. The high-voltage pulse generating circuit  1  includes a direct current power source  11 , a gate control circuit  12 , a transformer TS 1 , a transistor TR 1 , a capacitor C 1 , a capacitor C 2 , a diode D 1  and a discharge tube  13 . The gate control circuit  12  serves as a switching control circuit, and the capacitor C 1  serves as a first capacitor. The transformer TS 1  includes a primary winding W 1  and a secondary winding W 2  and is of flyback type. According to the first preferred embodiment of the present invention, the turn ratio between the primary winding W 1  and the secondary winding W 2  is one to ten. The transistor TR 1  serves as a switching device, such as an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). The high-voltage pulse generating circuit  1  is adopted to generate at the discharge tube  13  plasma utilized for cleaning a semiconductor substrate surface or a glass substrate surface, or producing ozone to purify exhaust gas, deodorize and sterilize. 
     A node N 2  connected to the end of the primary winding W 1  on the dot side thereof is connected to the positive electrode of the direct current power source  11 , and a node N 1  connected to the end of the primary winding W 1  on the non-dot side thereof is connected to the collector of the transistor TR 1 . The capacitor C 1  is connected between the nodes N 1  and N 2 . The gate control circuit  12  is connected to the gate of the transistor TR 1  for applying a gate voltage VG 1 . The emitter of the transistor TR 1  is connected to the negative electrode of the direct current power source  11  and a ground voltage VSS. The ground voltage VSS serves as low-level reference potential. 
     A node connected to the secondary winding W 2  on the dot side thereof is connected to one end of the discharge tube  13 , and a node connected to the secondary winding W 2  on the non-dot side thereof is connected to the other end of the discharge tube  13  through the diode D 1 . The capacitor C 2  and the discharge tube  13  are connected to each other in parallel. 
     The following will describe an operation of the high-voltage pulse generating circuit  1  with reference to the waveform diagram of  FIG. 2 . The waveform of voltage VTR in  FIG. 2  represents the voltage at the node N 1 . The waveform of voltage VO in  FIG. 2  represents the output voltage at the secondary winding W 2  of the transformer TS 1  under a condition where the discharge tube  13  connected to the high-voltage pulse generating circuit  1  is deemed to be a resistance load. As shown in  FIG. 2 , the gate voltage VG 1  is set at high level at time T 1 , and the transistor TR 1  is switched to be in the conductive state. Thus, a power supply voltage VCC of the direct current power source  11  serving as high-level reference potential is applied to the transformer TS 1 . The current flowing through the primary winding W 1  increases at a constant gradient VCC/L 1 , wherein L 1  represents the inductance of the primary winding W 1 . 
     The gate voltage VG 1  is at low level at time T 2 , and the transistor TR 1  is switched to be in the non-conductive state. Then, the current flowing through the primary winding W 1  is shut off, and induced electromotive force is generated, accordingly, so that the voltage VTR at the node N 1  and the voltage VO applied to the discharge tube  13  are increased rapidly. The length of time period between the times T 1  and T 2  during which the transistor TR 1  is in the conductive state for the first time will be referred to as first conductive time P 1 . The value of the first conductive time P 1  is set as desired in accordance with the turn ratio of the transformer TS 1  and the inductance of the primary winding W 1 . 
     The voltage VTR and the voltage VO reach the respective peak levels at time T 3 . Since the turn ratio of the transformer TS 1  is 1 to 10, in the case where the peak level of the voltage VTR is, for example, 1 kV, the peak level of the voltage VO is 10 kV. 
     At time T 4 , after the voltages VTR and VO excess the respective peak levels, the gate voltage VG 1  is set at high level again, so that the transistor TR 1  is switched to be in the conductive state. Therefore, the energy stored in the transformer TS 1  is released through the transistor TR 1 , so that the voltages VTR and VO are rapidly dropped as indicated by the solid line in  FIG. 2 . The length of time period between the times T 2  and T 4  during which the transistor TR 1  is in the non-conductive state will be referred to as non-conductive time P 0 . The value of the non-conductive time PO may be previously set at any suitable time that is close to a length of time period while the voltages VTR and VO start rising at the time T 2  and reach the respective peak levels at the time T 3 . The peak level of the voltage VO can be adjusted by the voltage of the direct current power source  11  and the first conductive time P 1 , as well as the non-conductive time P 0 . The length of time period between the times T 2  and T 3 , which is determined by LC resonance between the primary winding W 1  and the capacitor C 1 , may be previously calculated using the inductance L 1  of the primary winding W 1  and the capacitance of the capacitor C 1 . 
     The voltages VTR and VO are dropped to 0 volt at time T 5  and, therefore, the energy stored in the transformer TS 1  is released completely as indicated by the solid line in  FIG. 2 . Then, the gate voltage VG 1  is set at low level, and the transistor TR 1  is switched to be in the non-conductive state. Thus, one cycle pulse generating operation of the high-voltage pulse generating circuit  1  is completed. The length of time period between the times T 4  and T 5  during which the transistor TR 1  is in the conductive state for the second time will be referred to as second conductive time P 2 . The value of the second conductive time P 2  may be previously determined appropriately in accordance with the time required for releasing of the energy. 
     The following will describe advantageous effects of the high-voltage pulse generating circuit  1  according to the first preferred embodiment of the present invention. According to the conventional high-voltage pulse generating circuit  1 , the transistor corresponding to the transistor TR 1  of  FIG. 1  is maintained in the non-conductive state during the second conductive time P 2 . In this case, the voltages VTR and VO are gradually decreased, as indicated by the dotted line in  FIG. 2 , and reach 0 volt at time T 6 . 
     Meanwhile, according to the high-voltage pulse generating circuit  1  of the present invention, the transistor TR 1  is switched to be in the conductive state during the second conductive time P 2 . In this case, the voltages VTR and VO are rapidly decreased from the time T 4 , as indicated by the solid line in  FIG. 2 , and reach 0 volt at the time T 5 . Therefore, the pulse width of the voltage VTR is narrowed from pulse width PW 2  to pulse width PW 1  while having the peak level at the time T 3 , and also the pulse width of the voltage VO is narrowed from pulse width PW 3  to the pulse width PW 1  while having the peak level at the time T 3 . This makes the fall period of the voltages VTR and VO indicated by shaded area in  FIG. 2  to be shortened. 
     In generating plasma at the discharge tube  13 , the voltages VTR and VO in voltage rising time RR 1  or between the times T 2  and T 3 , are effective to produce plasma. On the other hand, the voltages VTR and VO in voltage falling time RR 2  or between the times T 3  and T 7 , are not effective for production of plasma and such voltages become heat loss. According to the first preferred embodiment of the present invention, the shaded region in  FIG. 2  corresponding to the voltage falling time RR 2  may be reduced thereby to decrease the amount of heating due to the heat loss. This makes possible downsizing of a plasma generating device and saving of electric power for plasma generation. 
     According to the first preferred embodiment of the present invention, the pulse width is narrowed from the pulse width PW 3  to the pulse width PW 1 , that is about 30% reduction of the width. Since the pulse density may be increased by continuously producing pulses, the performance of the high-voltage pulse generating circuit  1  is improved. 
     The following will describe a high-voltage pulse generating circuit  1 A according to the second preferred embodiment of the present invention with reference to  FIGS. 3 and 4 . The high-voltage pulse generating circuit  1 A includes transistors TR 11  and TR 12  which are an insulated gate bipolar transistor (IGBT), a first gate control circuit  12 A, a second gate control circuit  12 B, a capacitor C 3 , a capacitor C 4  and a switch SW 1  in addition to the structure of the high-voltage pulse generating circuit  1  of the first preferred embodiment. 
     Each of the transistors TR 11  and TR 12  serves as a switching device. The transistor TR 11  serves as a first switching device, and the transistor TR 12  serves as a second switching device. The switch SW 1  serves as a third switching device. Each of the first gate control circuit  12 A and the second gate control circuit  12 B serves as a switching control circuit. The capacitor C 3  serves as a second capacitor, and the capacitor C 4  serves as a third capacitor. 
     The first gate control circuit  12 A is connected to the gate of the transistor TR 11  for applying a gate voltage VG 11  to the gate. The collector of the transistor TR 12  is connected to the node N 1 , the emitter of the transistor TR 12  is connected to a node N 3  and the gate of the transistor TR 12  is connected to the second gate control circuit  12 B. The second gate control circuit  12 B outputs a gate voltage VG 12 . One end of the capacitor C 3  as a first end is connected to the emitter of the transistor TR 11 , negative electrode of the direct current power source  11  and the ground voltage VSS, and the other end of the capacitor C 3  as a second end is connected to the node N 3 . One end of the switch SW 1  is connected to the node N 2  and the positive electrode of the direct current power source  11 , and the other end of the switch SW 1  is connected to the node N 3 . The capacitor C 4  and the direct current power source  11  are connected to each other in parallel. The rest of the structure of the high-voltage pulse generating circuit  1 A is substantially the same as that of the high-voltage pulse generating circuit  1  of the first preferred embodiment and, therefore, the description thereof will be omitted. 
     The following will describe the operation of the high-voltage pulse generating circuit  1 A with reference to the waveform diagram of  FIG. 4 . The waveform of voltage VO in  FIG. 4  represents the voltage of the transformer TS 1  at the secondary winding W 2  under a no-load condition where the discharge tube  13  is not connected to the high-voltage pulse generating circuit  1 A. The gate voltage VG 11  is set at high level at time T 1 A, and the transistor TR 11  and the switch SW 1  are switched to be in the conductive state and energy begins to be stored in the transformer TS 1 . Part of the energy stored in the capacitor C 3  is allocated to the capacitor C 4  so that the voltages of the capacitors C 3  and C 4  become substantially the same, which is as much as the power supply voltage VCC. 
     The gate voltage VG 11  is set at low level at time T 2 A, and the transistor TR 11  and the switch SW 1  are switched to be in the non-conductive state. Then, the voltage VTR at the node N 1  and the voltage VO applied to the discharge tube  13  are increased rapidly due to the induced electromotive. 
     The voltages VTR and VO reach their respective peak levels at time T 3 A. At time T 4 A, after the voltages VTR and VO excess their respective peak levels, the gate voltage VG 12  is set at high level, and the transistor TR 12  is switched to be in the conductive state. In this case, the switch SW 1  is turned off, a current path is formed from the transformer TS 1  to the capacitor C 3  through the transistor TR 12 . The energy stored in the transformer TS 1  is transferred to the capacitor C 3  through the transistor TR 12 , which causes the voltages VTR and VO to be dropped rapidly. The voltage VC 3  of the capacitor C 3  is increased from the power supply voltage VCC depending on the amount of the energy transferred from the transformer TS 1 . The increased value of the voltage of the capacitor C 3  is determined by various characteristics such as inductance L 1  of the primary winding W 1 , the capacitance of the capacitor C 3  or the pulse recurrence frequency of the pulse generating operation in the high-voltage pulse generating circuit  1 . 
     When releasing of the energy from the transformer TS 1  is completed, the gate voltage VG 12  is set at low level at time T 5 A, and the transistor TR 12  is switched to be in the non-conductive state. Thus, the pulse generating operation of the high-voltage pulse generating circuit  1 A is completed. 
     The following will describe the first advantageous effect of the high-voltage pulse generating circuit  1 A according to the second preferred embodiment of the present invention. According to the high-voltage pulse generating circuit  1 A, energy released from the transformer TS 1  may be recovered to be stored in the capacitor C 3  during the second conductive time P 2  or the time between the times T 4 A and T 5 A when the transistor TR 12  is switched to be in the conductive state. Thus, energy loss in the operation of the high-voltage pulse generating circuit  1 A may be reduced. 
     The following will describe the second advantageous effect of the high-voltage pulse generating circuit  1 A according to the second preferred embodiment. According to the high-voltage pulse generating circuit  1 A, the switch SW 1  is turned on during the first conductive time P 1  or the time between the times T 1 A and T 2 A, so that part of the energy stored in the capacitor C 3  is allocated to the capacitor C 4  and the energy stores of the capacitors C 3  and C 4  becomes substantially the same. During the second conductive time P 2  or the time between the times T 4 A and T 5 A, the transistor TR 12  is switched to be in the conductive state and the energy stored in the transformer TS 1  is transferred to the capacitor C 3 . The voltage VC 3  of the capacitor C 3  is increased from the power supply voltage VCC depending on the amount of the energy transferred from the transformer TS 1 . In the high-voltage pulse generating circuit  1 A, the transistor TR 12  is an insulated gate bipolar transistor (IGBT) having a unidirectional characteristic. Thus, current path is prevented from being formed in the reverse direction to the current path formed from the direct current power source  11  through the primary winding W 1 , the transistor TR 12  and the capacitor C 3 , and the voltage VC 3  of the capacitor C 3  is raised from the power supply voltage VCC and then maintained. 
     Therefore, in the case where the transistor TR 12  is maintained in the conductive state even elapsed after the time T 5 A when energy releasing from the primary winding W 1  is completed, current through the primary winding W 1  during the second conductive time P 2  is prevented from flowing, so that means the setting the length of the second conductive time P 2  is eased. More specifically, the second conductive time P 2  may be set to end anytime before the next high-voltage pulse generating operation starts or before the gate voltage VG 11  is set at the high level. Thus, stable operating margin of the second gate control circuit  12 B may be broader. 
     The following will describe the third advantageous effect of the high-voltage pulse generating circuit  1 A according to the second preferred embodiment. In the high-voltage pulse generating circuit  1 A, the transistors TR 11 , TR 12  are connected to the primary winding W 1  in series, respectively. When the transistor TR 11  is switched to be in the conductive state during the first conductive time P 1 , the transformer TS 1  stores energy. The energy stored in the transformer TS 1  is released by maintaining the transistor TR 12  in the conductive state during the second conductive time P 2 . Thus, store and release of energy can be effected by different transistors. Therefore, in the case where the time interval between the first conductive time P 1  and the second conductive time P 2  or the length of the non-conductive time P 0  is relatively narrow, switching operation can be performed reliably regardless of the switching speed of the transistors. 
     In the second preferred embodiment, the transistor TR 12  is an insulated gate bipolar transistor (IGBT) which has the unidirectional characteristic. Alternatively, the transistor TR 12  may be a bidirectional device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). In this structure, the voltage or current of the capacitor C 3  should be detected, and the gate voltage VG 12  is set at low level by the second gate control circuit  12 B before starting the energy stored in the capacitor C 3  returned to the transformer TS 1 , so that the transistor TR 12  is turned to be in the non-conductive state. Therefore, the current path of the capacitor C 3  can be prevented from being formed in the reverse direction after the capacitor C 3  reaches the peak levels. 
     The following will describe a high-voltage pulse generating circuit  1 C according to the third preferred embodiment of the present invention with reference to  FIGS. 5 and 6 . The high-voltage pulse generating circuit  1 C dispenses with the switch SW 1  of the second preferred embodiment and includes a transistor TR 13  in addition to the structure of the high-voltage pulse generating circuit  1 A of the second preferred embodiment. The transistor TR 13  corresponds to the transistor TR 12  of the second preferred embodiment and is a metal-oxide-semiconductor field-effect transistor (MOSFET) serving as a bidirectional switch. 
     Each of the transistors TR 11  and TR 13  serves as a switching device. The transistor TR 11  serves as a first switching device, and the transistor TR 13  serves as a second switching device. Each of the first gate control circuit  12 A and the third gate control circuit  12 C serves as a switching control circuit. The capacitor C 3  serves as a second capacitor, and the capacitor C 4  serves as a third capacitor. 
     The drain of the transistor TR 13  is connected to the node N 1 , the source of the transistor TR 13  is connected to the node N 3 , and the gate of the transistor TR  13  is connected to the third gate control circuit  12 C. The third gate control circuit  12 C outputs a gate voltage VG 13 . The rest of the structure of the high-voltage pulse generating circuit  1 C is substantially the same as that of the high-voltage pulse generating circuit  1 A of the second preferred embodiment and, therefore, the description thereof will be omitted. 
     The following will be describe the operation of the high-voltage pulse generating circuit  1 C with reference to the waveform diagram of  FIG. 6 . The waveform of voltage VO in  FIG. 6  represents the voltage of the transformer TS 1  at the secondary winding W 2  under a no-load condition where the current flow from the high-voltage pulse generating circuit  1 C to the discharge tube  13  is deemed to be very low. As shown in  FIG. 6 , the gate voltage VG 11  is set at high level at the time T 1 A, and the transistor TR 11  is turned to be in the conductive state. Thus, the transformer TS 1  stores energy. At this time, the voltage VC 3  of the capacitor C 3  is maintained to a voltage close to the power supply voltage VCC. The gate voltage VG 11  is set at low level at the time T 2 A, and the transistor TR 11  is switched to be in the non-conductive state. Then, the voltage VTR at the node N 1  and the voltage VO applied to the discharge tube  13  are increased rapidly due to the induced electromotive. 
     The voltages VTR and VO reach the respective peak levels at the time T 3 A. At time T 4 A after the voltages VTR and VO excess the respective peak levels, the gate voltage VG 13  is set at high level, and the transistor TR 13  is switched to be in the conductive state. In this case, a current path is formed from the transformer TS 1  to the capacitor C 3  through the transistor TR 13 . The energy stored in the transformer TS 1  is transferred to the capacitor C 3  through the transistor TR 13 , which causes the voltage VTR to be dropped rapidly to a voltage close to the voltage of the capacitor C 3  and the voltage VO also to be dropped rapidly. 
     The voltage VC 3  of the capacitor C 3  is alternatively increased and decreased according to the resonance frequency f (f=½π√(L 1 *C 31 )) which is determined by the inductance L 1  of the primary winding W 1  and the capacitance C 31  of the capacitor C 3 . Specifically, a current flowing in a direction from the transformer TS 1  to the capacitor C 3  is referred to as a current I 13 C, and a current flowing in the opposite direction to the current I 13 C is referred to as a current I 13 D as shown in  FIG. 5 . The current I 13 C flows to the capacitor C 3 , so that the voltage VC 3  of the capacitor C 3  is increased from the power supply voltage VCC and reach the peak level. Subsequently, the current I 13 D flows from the capacitor C 3 , so that the energy stored in the capacitor C 3  is transferred to the primary winding W 1  to be reduced. The gate voltage VG 13  is set at low level at the time T 5 A when the voltage VC 3  becomes the same as the power supply voltage VCC, and the transistor TR 13  is switched to be in the non-conductive state. The transistor TR 13  is switched to be in the non-conductive state at a time when the voltage VC 3  is decreased after the voltage VC 3  is increased. At the time during the second conductive time P 2 , the current I 13 D flows in the opposite direction to the current I 13 C and the energy stored in the capacitor C 3  is released during the second conductive time P 2 . The current I 13 D flows back to the capacitor C 4  through the primary winding W 1 , and the energy stored in the capacitor C 4 . Thus, one cycle pulse generating operation of the high-voltage pulse generating circuit  1 C is completed. 
     The time T 5 A or the second conductive time P 2  may be set a predetermined time by a periodic waveform of the voltage VC 3  according to the resonance frequency f (f=½π√(L 1 *C 31 )). The time T 5 A may be set a time when a device (not shown) used for monitoring the voltage VC 3  of the capacitor C 3  detects that the voltage VC 3  is decreased back to the power supply voltage VCC after the voltage VC 3  is once increased from the power supply voltage VCC, and then the transistor TR 13  may be turned off at the time T 5 A. Or, the time T 5 A may also be set a time when a device (not shown) used for monitoring the voltage VTR detects that the voltage is decreased back to the power supply voltage VCC after the voltage VTR is once increased from the power supply voltage VCC and then the transistor TR 13  is turned off. The voltage VC 3  has a waveform relative to the power supply voltage VCC according to the resonance frequency f, and the level of the waveform of the voltage VC 3  indicated by solid line and dot line in  FIG. 6  is gradually reduced. According to the third preferred embodiment, the time T 5 A is set at a time when the voltage VC 3  is decreased after the voltage VC 3  excess their first peak level. 
     The following will describe advantageous effects of the high-voltage pulse generating circuit  1 C according to the third preferred embodiment of the present invention. The energy released from the transformer TS 1  is once stored in the capacitor C 3  during the second conductive time P 2  or the time between the time T 4 A and the time T 5 A when the transistor TR  13  is switched to be in the conductive state. Then, the transistor TR 13  is switched to be in the non-conductive state at a time when the energy stored in the capacitor C 3  is transferred to the primary winding W 1  again due to LC resonance, so that the energy stored in the capacitor C 3  is transferred and stored in the capacitor C 4  through the primary winding W 1 . Thus, energy loss in the operation of the high-voltage pulse generating circuit  1 C may be reduced. 
     Since the transistor TR 13  is a bidirectional switch, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), the energy may be stored in and released from the capacitor C 3  through the transistor TR 13 . 
     The present invention is not limited to the above-described embodiments, but may be modified into various alternative embodiments, as exemplified below. 
     As shown in the high-voltage pulse generating circuit  1 B of  FIG. 7 , a resistance device R 1  may be used instead of the switch SW 1 . Each of the transistors TR 11  and TR 12  serves as a switching device. The transistor TR 11  serves as a first switching device, and the transistor TR 12  serves as a second switching device. Each of the first gate control circuit  12 A and the second gate control circuit  12 B serves as a switching control circuit. The capacitor C 3  serves as a second capacitor, and the capacitor C 4  serves as a third capacitor. 
     During the second conductive time P 2  when the transistor TR 12  is in the conductive state, a current I 12  flowing through the transistor TR 12  is divided at the node N 3  into a current I 12 A flowing to the capacitor C 3  and a current I 12 B flowing to the capacitor C 4 . The dividing ratio of the current I 12  is determined depending on the resistance of the resistance device R 1  such that the current I 12 A becomes greater than the current I 12 B in accordance with setting greater the resistance value of the resistance device R 1 . 
     According to the above-described embodiments, the values of the non-conductive time P 0  and the second conductive time P 2  are previously determined appropriately, but the present invention is not limited to such arrangement. The non-conductive time P 0  may have a value close to the lengths of time before or after the voltages VTR and VO reach the respective peak levels at the time T 3  after they start to rise at the time T 2 , and may not include a value when the voltages VTR and VO reach the peak level. The value of the non-conductive time P 0  may be determined by detecting that at least one of the voltages VTR and VO reaches the corresponding predetermined value near the corresponding peak level. The value of the second conductive time P 2  may be determined by detecting that at least one of the voltages VTR and VO is decreased less than corresponding predetermined value. 
     According to the above-described embodiments, the time T 5 A is set at a time when the voltage VC 3  of the capacitor C 3  is decreased after the voltage VC 3  of the capacitor C 3  excess the first peak level of the waveform of the voltage VC 3  of the capacitor C 3 . Alternatively, the time T 5 A may be set at a time when the voltage VC 3  of the capacitor C 3  is decreased after the voltage VC 3  of the capacitor C 3  excess the second or other peak level. 
     According to the above-described embodiments, the voltage VC 3  of the capacitor C 3  is maintained to be near the power supply voltage VCC. Alternatively, the capacitor C 3  may be maintained in a state where the capacitor C 3  stores no energy. 
     Application of the high-voltage pulse generating circuits  1  through  1 C is not limited to apply to an ozone generating device. A pulse generating device for plasma may be applied to any devices.