Patent Publication Number: US-7911837-B2

Title: Multi-state memory cell with asymmetric charge trapping

Description:
RELATED APPLICATION 
     This application is a Divisional of U.S. application Ser. No. 11/432,019, titled “MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING,” filed May 11, 2006 (allowed) now U.S. Pat. No. 7,616,482, which is a Divisional of application Ser. No. 10/785,785 filed Feb. 24, 2004 now U.S. Pat. No. 7,072,217, titled “MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING,” issued Jul. 4, 2006, which are commonly assigned and incorporated herein by reference. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates generally to memory cells and in particular the present invention relates to multi-state non-volatile memory cells. 
     BACKGROUND OF THE INVENTION 
     Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicate a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write. 
     Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. The transistors can be erased to restore the threshold voltage of the transistor. The memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. These non-volatile memory devices are commonly referred to as flash memories. 
     Flash memories may use floating gate technology or trapping technology. Floating gate cells include source and drain regions that are laterally spaced apart to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. The floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. The non-volatile memory function for the floating gate technology is created by the absence or presence of charge stored on the isolated floating gate. The trapping technology functions as a non-volatile memory by the absence or presence of charge stored in isolated traps that capture and store electrons or holes. 
     In order for memory manufacturers to remain competitive, memory designers are constantly trying to increase the density of flash memory devices. Increasing the density of a flash memory device generally requires reducing spacing between memory cells and/or making memory cells smaller. Smaller dimensions of many device elements may cause operational problems with the cell. For example, the channel between the source/drain regions becomes shorter possibly causing severe short channel effects. Additionally, possible charge migration from one corner of the cell to the other becomes more of a concern with smaller cell size. 
     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for higher density memory devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a cut away view of one embodiment for programming a multi-state NAND memory cell with asymmetric charge trapping of the present invention. 
         FIG. 2  shows a cut away view of another embodiment for programming a multi-state NAND memory cell with asymmetric charge trapping of the present invention. 
         FIG. 3  shows a cut-away view of an embodiment for erasing a multi-state NAND memory cell with asymmetric charge trapping of the present invention. 
         FIG. 4  shows a cut-away view of yet another embodiment of a multi-state NAND memory cell with asymmetric charge trapping of the present invention. 
         FIG. 5  shows a cut-away view of an embodiment for reading the multi-state NAND memory cell with asymmetric charge trapping of the present invention. 
         FIG. 6  shows a portion of a multi-state NAND memory cell array of the present invention. 
         FIG. 7  shows a table of voltages for operation of the embodiment of  FIG. 6 . 
         FIG. 8  shows a block diagram of one embodiment of an electronic system of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer or substrate, used in the following description, include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. 
     The charge on a floating gate memory forms a Gaussian surface that spreads across the floating gate. The charge in a trapping based memory of the present invention is localized and does not spread. This property permits asymmetric charge and the ability to form multi-state cells. 
       FIG. 1  illustrates a cut-away view of one embodiment for programming a multi-state NAND memory cell with asymmetric charge trapping. This embodiment is comprised of a substrate  101  with two active areas  105  and  107 . Each region  105  and  107  acts alternatively as a drain or source region, depending on the operation performed and voltages that are applied. 
     In one embodiment, the drain and source regions  105  and  107  are n-type conductive material while the substrate  101  is a p-type conductive material. In an alternate embodiment, these conductive material types are switched. 
     Above the channel between the drain/source regions  105  and  107  is an oxide-nitride-oxide (ONO) structure  103 ,  109 , and  111 . The nitride layer  103  is isolated from the substrate by a first oxide layer  111  and from a control gate  100  by a second oxide layer  109 . The nitride layer  103  is the trapping layer that stores the asymmetric charges of the present invention. The present invention is not limited to any certain quantity of dielectric and/or trapping layers. 
     The present invention is also not limited in the composition of the dielectric/trapping layers. In one embodiment, the oxide material can be aluminum oxide. The trapping layer may be a silicon nanocrystal material. Alternate embodiments use other types of dielectric materials and/or other trapping layer materials. 
     The embodiment of  FIG. 1  illustrates the programming of one data bit in the left side of the trapping layer  103 . This is accomplished by applying a relatively high negative voltage to the control gate  100 . This voltage turns off the channel in order to prevent leakage from the drain region  105  to the source region  107 . In one embodiment, the gate voltage is between −10V and −15V. Alternate embodiments may use other gate voltage ranges. 
     An asymmetric bias is applied to the drain  105  and source regions  107 . In one embodiment, a positive 5V is applied to the drain region  105  and the source region  107  is grounded (i.e., 0V). The large potential on the left side of the junction from both the gate  100  and junction field causes a gate induced drain leakage (GIDL) condition that injects holes into the trapping layer  103  near the left junction. The injected holes neutralize the electrons from a previous erased condition thus resulting in a reduced threshold voltage. 
     The right junction has a reduced field since the junction bias is zero. This results in a bias condition that does not inject holes. The electrons on the right side of the channel are not compensated by holes thus resulting in the initial programmed or erased condition remaining. 
       FIG. 2  illustrates a cut-away view of a second embodiment for programming a multi-state NAND memory cell with asymmetric charge trapping. The embodiment of  FIG. 2  illustrates the programming of one data bit in the right side of the trapping layer  103 . This is accomplished by applying a relatively high negative voltage to the control gate  100 . This voltage turns off the channel in order to prevent leakage from the drain region  107  to the source region  105 . In one embodiment, the gate voltage is between −10V and −15V. Alternate embodiments may use other gate voltage ranges. 
     An asymmetric bias is applied to the drain  107  and source regions  105 . In one embodiment, a positive 5V is applied to the drain region  107  and the source region  105  is grounded (i.e., 0V). The large potential on the right side of the junction from both the gate  100  and junction field causes a GIDL condition that injects holes into the trapping layer  103  near the right junction. The injected holes neutralize the electrons from a previous erased condition thus resulting in a reduced threshold voltage. 
     The left junction has a reduced field since the junction bias is zero. This results in a bias condition that does not inject holes. The electrons on the left side of the channel are not compensated by holes thus resulting in the above-described programmed condition remaining. 
       FIG. 3  illustrates a cut-away view of an embodiment for erasing a multi-state NAND memory cell with asymmetric charge trapping. The erase operation is performed by tunneling electrons into the trapping layer  103  from a uniform sheet of charge in the inversion region  301 . This forms a high threshold level by a continuous uniform sheet of trapped charge in the trapping layer  103 . The erase operation is accomplished in one embodiment by applying a positive gate voltage in the range of 10-20V. Both the drain and source regions are grounded (i.e., 0V). Alternate embodiments may use other voltages and voltage ranges. 
       FIG. 4  illustrates a cut-away view of yet another embodiment of a multi-state NAND memory cell with asymmetric charge trapping. This embodiment creates a discontinuous trapping layer  403  by extending the control gate into the trapping layer  403 . This results in better sensing, better data retention, and resistance to secondary emissions. 
       FIG. 5  illustrates a method for reading the left side of the multi-state NAND memory cell of the present invention using asymmetrical biasing of the source/drain regions. The left data bit  500  can be read by applying a relatively high bias to the right source/drain region  501  of the cell. In one embodiment, this drain voltage is in the range of 1-3V. The left drain/source region  503 , acting as a source, is grounded and V G  is a positive voltage in the range of 3-6V. Alternate embodiments may use other voltages and voltage ranges. 
     The right data bit  502  is read using an inverse process. In this embodiment, the left drain/source region  503  is grounded while the right source/drain region  501  has a relatively high voltage applied (e.g., 1-3V). V G  in this read embodiment is also in the range of 3-6V. Alternate embodiments may use other voltages and voltage ranges. 
       FIG. 6  illustrates two string arrays of multi-state NAND memory cells of the present invention. A table of voltages for different modes of operation of a selected column of this memory array is illustrated in  FIG. 7 . 
     The portion of the NAND memory array of  FIG. 6  is comprised of two columns  601  and  602  of multi-state NAND memory cells as described above. One column  601  is selected while the second column  602  is unselected. The selected column  601  is comprised of a select gate  605  for the drain voltage, V d , and a select gate  606  for the source voltage V s . The selected column  601  is also comprised of three multi-state NAND memory cells  610 - 612  that are connected to control gate voltages V WL1 -V WL3  respectively. The columns of  FIG. 6  are for purposes of illustration only since a real memory column is comprised of a substantially larger quantity of cells. 
     Referring to the voltage table of  FIG. 7 , two versions of an erase operation are illustrated. In one option, as described above, the drain and source voltages, V d  and V s , are 0V and the control gate voltage, V H , are in the range of 10-20V. In this embodiment, the control gates of the select gates  605  and  606  are connected to V H /2. Other erase operation embodiments may use GIDL hole injection from both sides of the array simultaneously. 
     The second option for an erase operation leaves the drain and source connections floating as an open connection (O/C). In this embodiment, the select gates  605  and  606  are also floating. 
     During a program operation of the left bit in the middle cell  611 , V WL2  is −V H  (e.g., −10 to −20V), V d  is V DP  (e.g., 3 to 6V), and V S  is connected to ground. The control gates of the select gates  605  and  606  are connected to V X1  and the control gates of the other cells  610  and  612  in the column  601  are connected to V X2 . In one embodiment V X1  is approximately equal to V X2  which is approximately equal to V DP +V T . V T  is the threshold voltage of the cell as is well known in the art. The program operation of the right bit in the middle cell  611  uses substantially the same voltages as the left bit but in this case V S  is connected to V DP  and V d  is connected to ground. Alternate embodiments use other embodiments to achieve substantially similar results. 
     During a read operation of the left bit in the middle cell  611 , V WL2  is V R  (e.g., 3-6 V), V d  is V DR , and V S  is connected to ground. The control gates of the select gates  605  and  606  are connected to V Y1 , and the control gates of the other cells  610  and  612  in the column  601  are connected to V Y2 . In one embodiment, V Y1 , is approximately equal to V Y2  which is approximately equal to V DR +V T  where V DR  in the range of 4-6V. The read operation of the right bit in the middle cell  611  uses substantially the same voltages as the left bit but in this case V S  is connected to ground and V d  is connected to V DR . Alternate embodiments use other embodiments to achieve substantially similar results. 
       FIG. 8  illustrates a functional block diagram of a memory device  800  that can incorporate multi-state NAND memory cells of the present invention. The memory device  800  is coupled to a processor  810 . The processor  810  may be a microprocessor or some other type of controlling circuitry. The memory device  800  and the processor  810  form part of an electronic system  820 . The memory device  800  has been simplified to focus on features of the memory that are helpful in understanding the present invention. 
     The memory device includes an array of memory cells  830 . In one embodiment, the memory cells are non-volatile floating-gate memory cells and the memory array  830  is arranged in banks of rows and columns. 
     An address buffer circuit  840  is provided to latch address signals provided on address input connections A 0 -Ax  842 . Address signals are received and decoded by a row decoder  844  and a column decoder  846  to access the memory array  830 . It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array  830 . That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts. 
     The memory device  800  reads data in the memory array  830  by sensing voltage or current changes in the memory array columns using sense/buffer circuitry  850 . The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array  830 . Data input and output buffer circuitry  860  is included for bi-directional data communication over a plurality of data connections  862  with the controller  810 ). Write circuitry  855  is provided to write data to the memory array. 
     Control circuitry  870  decodes signals provided on control connections  872  from the processor  810 . These signals are used to control the operations on the memory array  830 , including data read, data write, and erase operations. The control circuitry  870  may be a state machine, a sequencer, or some other type of controller. 
     The flash memory device illustrated in  FIG. 8  has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. 
     CONCLUSION 
     In summary, the multi-state NAND cell of the present invention is a trapping based memory that allows asymmetric charges to be stored, thereby providing storage for two data bits. The memory cell provides high memory density, low power operation, and improved reliability due to the trapping function. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.