Patent Publication Number: US-2007108842-A1

Title: Apparatus and method for transient protection and synchronization of a plurality of power rails for a system on a chip

Description:
BACKGROUND OF THE INVENTION  
      1. Field of the Invention  
      This invention relates generally to integrated circuits and, more particularly, to the conductors (or rails) supplying power to an integrated circuit.  
      2. Background of the Invention  
      As miniaturization of semiconductor elements and the density of components have increased, more than one power supply conductor or power rail has been necessary to provide power to different sets of elements. For example, an OMAP circuit can require one power rail for the OMAP CORE and another power rail for the OMAP I/O (input/output) circuits. Notwithstanding the need for two power supply voltages, the circuit elements are interconnected and therefore the voltage for a first portion of the circuit can result in damage to the second portion. Furthermore, the transients themselves can be a problem. When, as happens during testing, an already-activated power terminal (sometimes referred to as a “hot” connection) coupled to the supply rails, the resulting transient voltage can damage the components.  
      A need has therefore been felt for apparatus and an associated method having the feature of providing protection for interconnected circuits powered by separate power voltages. It would be yet another feature of the apparatus and associated method to prevent circuit element damage when an already-activated power line is coupled to a circuit power rail. It would be yet another feature of the apparatus and associated method to prevent the separate application of power to one of a plurality of circuits having interconnected elements. It would be yet a further feature of the apparatus and associated method to prevent the separate application of power to each of a multiplicity of circuits, the circuits having interconnected elements.  
     SUMMARY OF THE INVENTION  
      The foregoing and other features are accomplished, according the present invention, by providing a transistor between the power supply and the power rail providing a separate voltage to each of a plurality of circuits. The control terminals of the transistors are inter-connected such that the two transistors can not be activated independently. In addition, the components of the circuits associated with each transistor reduce the transient voltages resulting from a full voltage application to the power rail.  
      Other features and advantages of present invention will be more clearly understood upon reading of the following description and the accompanying drawings and the claims.  
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIG. 1  is a circuit diagram for protecting the circuits coupled to two power rails according to the present invention.  
       FIG. 2  is a circuit diagram for protecting the circuits coupled to three power rails according to the present invention. 
    
    
     1. DETAILED DESCRIPTION OF THE FIGURES  
      Referring to  FIG. 1 , an input terminal of a first power rail, INPUT  1 , is coupled through capacitor C 1  to ground, through resistor R 1  to ground potential, to a source terminal of p-channel field effect transistor Q 4 , to a first terminal of resistor R 2 , and to a first terminal of resistor R 3 . The second terminal of resistor R 3  is coupled to a gate terminal of transistor Q 4  and to a drain terminal of n-channel, field effect transistor Q 2 . The drain terminal of transistor Q 4  is coupled through capacitor C 4  to ground and is coupled to the output terminal of the first power rail, OUTPUT  1 . The second terminal of resistor R 2  is coupled through capacitor C 2  to ground and to the source terminal of n-channel field effect transistor Q 1 . The drain terminal of transistor Q 1  is coupled to the gate terminal of transistor Q 2 , through resistor R 5  to ground, and to the gate terminal of n-channel field effect transistor Q 3 . The gate terminal of transistor Q 1  is coupled through capacitor C 3  to ground and through resistor R 4  to the second input terminal INPUT  22 . The source terminals of transistors Q 2  and Q 3  are coupled to ground. The source terminal of p-channel field effect transistor Q 5  is coupled to the second input terminal INPUT  2 , through resistor R 6  to ground, through capacitor C 5  to ground and through resistor R 7  to the gate terminal of transistor Q 5  and the drain terminal of transistor Q 3 . The drain terminal of transistor Q 5  is coupled through capacitor C 6  to ground and is coupled to the second output terminal OUTPUT  2 .  
      In one implementation, the resistors have a value of 10 Ohms, the capacitors have a value of 0.01 μFarads, transistors Q 1 , Q 2 , and Q 3  are 2N7000 transistors, and transistors Q 4  and Q 5  are Si191DH transistors. It will be clear that other components and other component values can be used to implement the invention.  
      Referring to  FIG. 2  the extension of the circuit shown in  FIG. 1  to three power rails is illustrated. In addition to the components of  FIG. 2 , the third input terminal, INPUT  3 , is coupled through resistor R 8  to ground, through capacitor C 7  to ground, to a first terminal of resistor R 9 , and to the source terminal of p-channel, field effect transistor Q 6 . The second terminal of resistor R 9  is coupled to gate terminal of transistor Q 6  and to the drain terminal of Q 3 . The drain terminal of transistor Q 6  is coupled through capacitor C 8  to ground and the output terminal OUTPUT  3 . The dotted line marked EXTENDED and coupled to the second terminal of resistor R 9 , to the gate terminal of transistor Q 6 , and to the drain terminal of Q 3  indicated the extension to the protection of additional power rails.  
      In the preferred embodiment, the components have the same values and identification numbers as the components of  FIG. 1 .  
     2. OPERATION OF THE PREFERRED EMBODIMENT  
      In the modern integrated circuit technology, a plurality of circuits having differing power requirements can be inter-connected, e.g., a system on a chip (SOC). For example, in a system on a chip the core circuit, the I/O circuit, and the memory circuit can each require different voltage values, i.e., processing core can require 1.2 volt supply, an associated I/O circuit can require a 3.3 volt supply and a memory can require a 1.8 volt supply. However, these circuits are not independent, but the voltage in one circuit can affect the voltage applied to components in different circuits. In the present invention, a transistor is coupled between the power supply and the chip power rail for each circuit. The control terminals are interconnected in such a manner as to prevent separate activation of the power rails (i.e., the output terminals). In addition, the inter-connection of the control (gate) terminals prevents transients being applied to the output terminals. The present circuit is particularly valuable when an active power supply terminal is applied directly to a system on a chip, such as in the testing of the chip.  
      While the invention has been described with respect to the embodiments set forth above, the invention is not necessarily limited to these embodiments. Accordingly, other embodiments, variations, and improvements not described herein are not necessarily excluded from the scope of the invention, the scope of the invention being defined by the following claims.