Patent Publication Number: US-7220645-B2

Title: Method of manufacturing semiconductor device

Description:
The subject matter of application Ser. No. 10/391,104 is incorporated by reference. The present application is a continuation of U.S. application Ser. No. 10/391,104, filed Mar. 18, 2003, now U.S. Pat. No. 6,908,820 which claims priority to Japanese Patent Application No. JP2002-079942, filed Mar. 22, 2002. The present application claims priority to the previously filed application. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a method of manufacturing a semiconductor device, and is for contriving a higher degree of integration and a higher performance in an LSI of, for example, a MOS transistor or the like which uses an SOI substrate. 
     In recent years, in the LSI of the MOS transistor (hereinafter referred to as MOSFET), a higher degree of integration and a higher performance have been demanded, and a structure in which an SOI (silicon on insulator) layer is formed on a semiconductor substrate with a buried oxide layer therebetween, i.e., a MOSFET using an SOI substrate (hereinafter referred to as SOI-MOSFET) has been paid attention to. In the SOI-MOSFET, perfect device separation is achieved by an insulation layer (silicon oxide layer), so that soft errors and latch-up are suppressed, and high reliability can be obtained even in an LSI with a high degree of integration. In addition, since it is possible to reduce junction capacity of a diffusion layer, charging and discharging attendant on switching are suppressed, which is advantageous in view of contriving a higher speed and a lower electric power consumption. 
     The SOI-MOSFETs as above-mentioned are generally classified into two kinds according to the operation mode. One of the two kinds is a fully depleted SOI-MOSFET with an operation mode in which a depleted layer induced in a body portion beneath the gate electrode reaches the bottom surface of the body portion, i.e., reaches the interface between the body portion and the buried oxide film. The other of the two kinds is a partially depleted SOI-MOSFET with an operation mode in which the depleted layer does not reach the bottom surface of the body portion, and an electrically neutral region remains in the body portion. 
       FIG. 9  shows a general sectional view of a general fully depleted SOI-MOSFET. In  FIG. 9 , an SOI substrate  90  provided with an SOI layer  91  on an Si substrate  90   a  with a buried oxide film  90   b  therebetween is used, and a plurality of device separation regions  92  are formed on a part on the principal surface side of the SOI substrate  90  at predetermined intervals. 
     An impurity (impurity for a body portion) for an n-MOS or p-MOS, for example,. is implanted into an Si active layer region (SOI layer)  91   a  located between the device separation regions  92 , and a gate electrode  93   b  is formed on a part of the surface of the Si active layer region  91   a  (the surface where the body portion is located) with a gate insulation film  93   a  therebetween. 
     In addition, an impurity is implanted into the Si active layer region  91   a  by use of the gate electrode  93   b  as a mask, whereby extension portions  91   b  located between the source/drain portions and the body portion (located beneath side walls  93   c  which will be described later), i.e., the extension portions  91   b  in the source/drain portions are formed. 
     Thereafter, the side walls  93   c  are formed on the side wall sides of the gate electrode  93   b . With the side walls  93   c  as a mask, an impurity is implanted into the source/drain portions of the Si active layer region  91   a  to form a diffusion layer (a source/drain layer, which is omitted in the figure). Further, a metallic film is built up on the surfaces of the source/drain portions and the surface of the gate electrode  93   b , and is thermally treated (annealing treatment) to form a silicide film  94  (and a gate silicide film  93   d ). 
     Then, an inter-layer insulation film is formed so as to cover the device separation region  92 , the source/drain portions (silicide film  94 ), the gate electrode  93   b  (gate silicide film  93   d ) and the side walls  93   c , thereafter contact holes for electrical connection are opened in the portions of the inter-layer insulation film where the source/drain portions (silicide film  94 ) are located, and a wiring is formed so as to fill up the contact holes, thereby manufacturing a fully depleted SOI-MOSFET. In  FIG. 9 , symbol  93   e  denotes a diffusion layer formed on the gate electrode  93   b , together with the extension portions  91   b , and the inter-layer insulation film, the contact holes and the wiring are omitted in the figure. 
     In the case of the fully depleted SOI-MOSFET as above-mentioned, in order that an electrically neutral region in the body portion does not remain, a very thin SOI layer must be formed on the oxide film (namely, the buried oxide film) in a uniform thickness, so that the difficulty on the basis of the manufacturing process is increased; however, there is obtained a great merit that the sub-threshold characteristic (S characteristic) among operation characteristics is improved. 
     Incidentally, in the fully depleted SOI-MOSFET, since the thickness of the depleted layer in the body portion is restricted by the buried oxide film, the depleted electric charge amount is largely reduced as compared with the partially depleted type, and, in place, movable electric charges contributing to the drain current are increased. As a result, a steep S characteristic is obtained, and, in the case of forming a fully depleted SOI-MOSFET in the 0.13  m generation and later generations, for example, the thickness of the SOI layer must be suppressed to be about 30 nm or less. 
     Namely, according to the fully depleted SOI-MOSFET, even where a very steep S characteristic is obtained, the threshold voltage can be lowered while suppressing the off-leak current, so that a sufficient drain current can be secured even at a low operating voltage, and a device with an extremely low power consumption such as to be capable of operating at a voltage of 1 V or less (and a threshold voltage of 0.3 V or less), for example, can be produced. 
     Therefore, in the case of manufacturing an LSI of a super-low power consumption device with high degree of integration and high performance in the future, it is important to establish a process which makes it possible to constitute a fully depleted SOI-MOSFET for a very thin (for example, 30 nm or less in thickness) SOI layer. 
     In the case where the SOI layer is a thin film as above-mentioned, according to the general technology for manufacturing the fully depleted SOI-MOSFET, the body portion in the SOI layer would be thinned, and the source/drain portions and the extension portions would also be thinned. As a result, the sheet resistance in the source/drain portions and the extension portions is raised, i.e., the parasitic resistance of the transistor is raised, thereby lowering the driving capability. 
     The sheet resistance of the source/drain portions can be sufficiently reduced by forming a silicide film as shown in  FIG. 9 , but, as for the sheet resistance of the extension portions, it is necessary to raise the impurity concentration (for example, to about 1×10 15 /cm 2 ) in the extension portions. When the impurity concentration in the extension portions is raised, however, the extension portion on the source side would be heavily influenced by the electric field (electric line of force) imposed from the drain side, and, particularly in the case where the transistor constituted has a small gate length, the threshold voltage (absolute value of the threshold voltage) is steeply lowered (roll-off characteristic is worsened). 
     As a method of improving the roll-off characteristic, there is known a method in which, as for example indicated by void arrows in a general illustration in  FIG. 10  (the same components as those in  FIG. 9  are denoted by the same symbols as above, and description thereof is omitted), after the formation of the extension portions  91   b  an impurity different in polarity from the impurity in the source/drain portions is halo-implanted (halo ion implantation) to thereby form an impurity layer (hereinafter referred to as reverse-characteristic layer)  95  different from the source/drain layer in electrical characteristics so as to cover the surroundings of the extension portions (the lower surface side of the source/drain portions, the lower surface side of the extension portions, and the gate electrode side), thereby shielding the influence of the electric field from the drain side. 
     The general halo implantation is carried out, for example, by a method in which the arrangement angle of an SOI substrate arranged in an ion implantation apparatus is adjusted so that ions are obliquely implanted at an implantation angle relative to the direction of a normal to the implanted surface (the surface of the Si active layer region, in an embodiment which will be described later) of more than 7°. 
     However, in the case where the reverse-characteristic layer is formed on the lower surface side (the buried oxide film side) of the extension portions as shown in  FIG. 10 , particularly in a fully depleted SOI-MOSFET in which p-MOS is formed, there is the problem that the sheet resistance of the extension portions is raised. 
     Due to the foregoing, in the fully depleted SOI-MOSFET in which a thin film SOI layer is formed, it is impossible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance, and, therefore, it has been impossible to secure a sufficient driving capability. 
     SUMMARY OF THE INVENTION 
     The present invention has been made based on the above-mentioned problems. Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a halo implantation suited particularly to a fully depleted SOI-MOSFET provided with a thin film SOI layer is carried out to make it possible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance and to secure a sufficient driving capability. 
     In order to attain the above object, according to the present invention, there is provided a method of manufacturing a semiconductor device, using an SOI substrate provided with an SOI layer on an Si substrate with a buried oxide film therebetween, forming a plurality of device separation regions in the SOI layer, and implanting an impurity into an Si active layer region between the device separation regions to form a body portion and source/drain portions so as thereby to constitute a MOSFET, the method comprising the steps of: forming a gate electrode on the body portion of the Si active layer region with a gate insulation film therebetween, implanting an impurity into the Si active layer region to form extension portions of the source/drain portions, and halo-implanting an impurity different in polarity from the impurity in the source/drain portions into the Si active layer region to form a reverse-characteristic layer. In the method, the range of projection of the halo implantation is so set as to reach the inside of the buried oxide film. 
     According to the present invention, the impurity for the reverse-characteristic layer can be introduced, in a sufficient concentration, into the body portion side of the extension portions. Namely, since the impurity for the reverse-characteristic layer is scarcely introduced into the extension portions, it is possible to simultaneously achieve suppression of a rise in parasitic resistance (suppression of a rise in sheet resistance in the extension portions) and an improvement of roll-off characteristic, and to secure a sufficient driving capability. 
     In the halo implantation, the implantation angle may be such that the implanted impurity is implanted to the body portion side of the extension portions in the Si active layer region without being interfered by device separation regions adjacent to the Si active layer region surface (the implanted surface), the gate electrode, or the like (preferably, an angle of more than 7°). 
     In addition, the present invention promises a conspicuous effect of improving the driving capability, in a semiconductor device in which the Si active layer region is so formed that a depleted layer induced at the body portion reaches the interface between the SOI layer and the buried oxide film in the SOI substrate. 
     Examples of the SOI substrate in the present invention include various semiconductor substrates comprising a buried insulation layer therein, such as Si, Si-Ge, etc. Examples of the materials for forming the gate insulation film include insulating materials of Si compounds such as SiO 2 , SiN, SiON, SiOF, etc.; high dielectric constant films such as Ta 2 O 5 ; and laminate films composed of a combination of more than one of the insulating materials and the high dielectric constant films. 
     Examples of the gate electrode material in the present invention include polycrystalline silicon (or amorphous silicon) containing an impurity such as B, As, P, etc.; high melting point metals such as W, Mo, Ta, Ti, etc.; metallic silicides such as WSi 2 , MoSi 2 , TiSi 2 , CoSi 2 , NiSi, etc.; metallic nitrides such as WN, TaN, TiN, etc.; and laminate films composed of a combination of more than one of the polycrystalline silicon, the high melting point metals, the metallic silicides, and the metallic nitrides. 
     Examples of the impurity to be introduced into the Si active layer region in the present invention include various Group 3A and Group 5A materials such as B, In, P, As, Sb, etc. Examples of the material for forming the side walls include insulating materials of Si compounds such as SiO 2 , SiN, SiON, SiOF, etc.; polycrystalline silicon (or amorphous silicon); and laminate films composed of a combination of more than one of the insulating materials and polycrystalline silicon. 
     Examples of the material for the silicide film formed in the Si active layer region in the present invention include various materials such as TiSi 2 , CoSi 2 , NiSi, WSi 2 , MoSi 2 , etc. 
     According to the present invention, implantation energy and implantation angle are so adjusted that the range of projection in halo implantation reaches the buried oxide film of the SOI substrate, thereby forming the reverse-characteristic layer. By this, even in the case of a fully depleted SOI-MOSFET in which, for example, the SOI layer in the form of a thin film (for example, a thin film such that the depleted layer induced at the body portion reaches the interface between the SOI layer and the buried oxide film in the SOI substrate) is formed, it is possible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance, and thereby to obtain an LSI with high speed and low power consumption which securely displays a sufficient driving capability. 
     The above and other objects, features and advantages of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings which show by way of example some preferred embodiments of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a manufacturing step chart (formation of device separation regions) of a semiconductor device according to one embodiment of the present invention; 
         FIG. 2  is a manufacturing step chart (formation of a gate electrode) of the semiconductor device according to the present embodiment; 
         FIG. 3  is a manufacturing step chart (formation of extension portions) of the semiconductor device according to the present embodiment; 
         FIG. 4  is a manufacturing step chart (formation of a reverse-characteristic layer) of the semiconductor device according to the present embodiment; 
         FIG. 5  is a manufacturing step chart (formation of a source/drain layer and a silicide layer) of the semiconductor device according to the present embodiment; 
         FIG. 6  is a manufacturing step chart (formation of a contact plug) of the semiconductor device according to the present embodiment; 
         FIG. 7  is a sheet resistance characteristic diagram of the extension portions relative to halo implantation energy in the present embodiment; 
         FIG. 8  is a threshold voltage characteristic diagram relative to gate length in the present embodiment; 
         FIG. 9  is a general sectional view of a general fully depleted SOI-MOSFET; and 
         FIG. 10  is a general sectional view of a fully depleted SOI-MOSFET in which a reverse-characteristic layer is formed. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Now, a semiconductor device and a method of manufacturing the same according to one embodiment of the present invention will be described below. 
     In the present embodiment, an SOI substrate in which an SOI layer in the form of a thin film (a thin film such that a depleted layer inducted at a body portion reaches the interface between the SOI layer and a buried oxide film in the SOI substrate) is formed on an Si substrate with an oxide film (a thicker oxide film) therebetween is used, and a plurality of device separation regions are formed at a part of the principal surface side of the SOI substrate at predetermined intervals by, for example, an STI (shallow trench isolation) method. An impurity for n-MOS or p-MOS is implanted into an Si active layer region (SOI layer) located between the device separation regions, and a gate electrode is formed on a part of the surface thereof (the part where the body portion is located) with a gate insulation film therebetween. 
     An impurity at a comparatively high concentration is implanted into source/drain portions and extension portions of the Si active layer region by using the gate electrode as a mask, to form the extension portions. Thereafter, halo implantation is carried out while adjusting implantation energy and implantation angle so that the range of projection (Rp) reaches the inside of the buried oxide film, thereby forming a reverse-characteristic layer on the body portion side of the extension portions in the Si active layer region. 
     In addition, after formation of side walls on the side wall sides of the gate electrode, an impurity is implanted by use of the side walls as a mask to thereby form a source/drain layer, thereafter a metallic film is built up on the surfaces of the source/drain portions, and a heat treatment (annealing treatment) is conducted to form a silicide film. 
     Then, an inter-layer insulation film is formed so as to cover the device separation regions, the source/drain portions (silicide film), the gate electrode and the side walls, and contact holes for electrical connection are opened at the positions of the source/drain portions (silicide film) and the gate electrode in the inter-layer insulation film. 
     As mentioned above, the reverse-characteristic layer is formed not by simply conducting halo implantation but by conducting halo implantation while adjusting the implantation energy and implantation angle so that the range of projection (Rp) reaches the inside of the buried oxide film, whereby the reverse-characteristic layer is not formed at the extension portions, so that a rise in the sheet resistance in the extension portions can be suppressed. Besides, since the reverse-characteristic layer is formed on the body portion side of the extension portions in the Si active layer region, roll-off characteristic can be improved. 
     EXAMPLE 
     An example of the method of manufacturing a semiconductor device (SOI-MOSFET) according to the present embodiment will be described in detail below, based on the drawings (which show respective manufacturing steps). First, in  FIG. 1 , an SOI substrate  1  in which an SOI layer  2  in the form of a thin film (for example, 33 nm in thickness) is formed on an Si substrate  1   a  with a comparatively thick buried oxide film (for example, an oxide film of 100 nm in thickness)  1   b  therebetween was used, a thermal oxide film  3   a  (for example, 10 nm in thickness) was formed on the surface of the SOI layer  2  (upon this formation, the thickness of the SOI layer becomes about 29 nm), and thereafter an Si 3 N 4  film  3   b  (for example, 100 nm in thickness) as a protective film for CMP (chemical mechanical polish) was formed on the surface of the thermal oxide film  3   a  by a low pressure CVD (low pressure chemical vapor deposition) method. 
     Then, only the portions of the Si 3 N 4  film  3   b  where the device separation regions (described later) are located were removed by desired lithography and etching, and thereafter etching was conducted through the portions thus removed, to form trench grooves  3   c  in the SOI layer  2  (and the thermal oxide film  3   a ). In this example, the formation and etching of the Si 3 N 4  film  3   b  and the etching of the SOI layer  2  were conducted under the following conditions. 
     [Film Formation Conditions for Si 3 N 4  Film  3   b]   
     
         
         
           
             Gas used: SiH 2 Cl 2 /NH 3 /N 2 =50/200/200 sccm 
             Pressure: 70 Pa 
             Heated substrate temperature: 760° C.
 
[Etching Conditions for Si 3 N 4  Film  3   b] 
 
             Gas used: CF 4 /Ar=100/900 sccm 
             Pressure: 105 Pa 
             Heated substrate temperature: 10° C. 
             RF power: 600 W
 
[Etching Conditions for SOI Layer  2 ]
 
             Gas used: C 4 F 8 /O 2 /Ar=5/4/100 sccm 
             Pressure: 5.3 Pa 
             Heated substrate temperature: 10° C. 
             RF power: 400 W
 
Then, the inside walls of the trench grooves  3   c  were oxidized (for example, 5 nm in thickness; omitted in the figure), and thereafter an SiO 2  film was formed (for example, 300 nm in thickness) so as to fill up the trench grooves  3   c  by a low pressure CVD method, an annealing treatment was conducted, and the SiO 2  film at other portions than the trench grooves  3   c  was removed by a CMP method, whereby a plurality of device separation regions  4  were formed at predetermined intervals. In this example, the formation of the SiO 2  film, the annealing treatment thereof, and the CMP thereof for the device separation regions  4  were conducted under the following conditions.
 
[Film Formation Conditions for SiO 2 ]
 
             Gas used: SiH 4 /O 2 /N 2 =250/250/100 scm 
             Pressure: 13.3 Pa 
             Heated substrate temperature: 520° C.
 
[Annealing Treatment Conditions for SiO 2 ]
 
             Annealing temperature: 1000° C. 
             Annealing time: 30 min
 
[CMP Conditions for SiO 2 ]
 
             Polishing pressure: 300 g/cm 2    
             Revolution number: surface plate 30 rpm; polishing head 30 rpm 
             Polishing pad used: IC-1000 (trade name) 
             Slurry used: NH 4 OH-based slurry (containing fumed silica) 
             Slurry flow rate: 100 cc/min 
             Temperature of slurry used: 25–30° C.
 
Next, in  FIG. 2 , the remaining Si 3 N 4  film  3   b  was removed by a wet treatment using hot phosphoric acid, and an impurity for n-MOS or p-MOS (an impurity for the body portion) was implanted into the SOI layer  2  between the device separation regions  4 , i.e., the Si active layer region  2   a . In this example, the implantation of the impurity for the n-MOS or the p-MOS was conducted under the following conditions. Incidentally, the implantation angle shown below represents the angle of the direction of ion implantation (and the halo implantation which will be described later) relative to the direction of a normal to the surface of the Si active layer region  2   a.  
 
[Implantation Conditions in the Case of n-MOS]
 
             Impurity: BF 2+   
             Implantation energy: 20 keV 
             Dose: 3×10 12 /cm 2    
             Implantation angle: 7°
 
[Implantation Conditions in the Case of p-MOS]
 
             Impurity: P +   
             Implantation energy: 10 keV 
             Dose: 3 ×10 12 /cm 2    
             Implantation angle: 7°
 
Thereafter, the thermal oxide film  3   a  was removed, an insulation film and polysilicon (polysilicon by a low pressure CVD method) were sequentially formed (for example, respectively 1.8 nm and 150 nm in thickness) on the surface of the Si active layer region  2   a , and the polysilicon and the insulation film were processed into desired patterns by etching, to form a gate insulation film  5   a  and a gate electrode  5   b . In this example, the formation and etching of the polysilicon were conducted under the following conditions.
 
[Film Formation Conditions for Polysilicon]
 
             Gas used: SiH 4 /N 2 /He=100/200/400 sccm 
             Pressure: 70 Pa 
             Heated substrate temperature: 610° C.
 
[Etching Conditions for Polysilicon]
 
             Gas used: C 2 Cl 3 F 3 /SF 6 =60/10 sccm 
             Pressure: 1.3 Pa 
             Heated substrate temperature: 20° C. 
             RF power: 150 W
 
Next, as shown in  FIG. 3 , an impurity was implanted into the Si active layer region  2   a  (the source/drain portions and the extension portions) by using the gate electrode  5   b  as a mask, to form the extension portions  6 . In  FIG. 3 , symbol  5   c  denotes a diffusion layer formed on the surface of the gate electrode  5   b  by the impurity used for formation of the extension portions  6 .
 
           
         
       
    
     At the time of implanting the impurity for forming the extension portions  6  as described above, it is necessary to set the concentration (dose) of the impurity to be high (set to such a level that the parasitic resistance of the transistor can be lowered and a sufficient driving capability of the transistor can be secured) in order to sufficiently reduce the sheet resistance of the extension portions  6 . In this example, the implantation of the impurity for forming the extension portions  6  was carried out under the following conditions. 
     [Implantation Conditions in the Case of n-MOS] 
     
         
         
           
             Impurity: As +   
             Implantation energy: 2.5 keV 
             Dose: 1×10 15 /cm 2    
             Implantation angle: 0°
 
[Implantation Conditions in the Case of p-MOS]
 
             Impurity: BF 2+   
             Implantation energy: 2.5 keV 
             Dose 8×10 14 /cm 2    
             Implantation angle: 0°
 
Next, as shown in  FIG. 4 , an impurity different in polarity from the impurity for a source/drain layer which will be described later was halo-implanted so that the range of projection (Rp) reaches the inside of the buried oxide film by use of the gate electrode  5   b  as a mask, to form a reverse-characteristic layer  7  on the body portion side of the extension portions  6  in the Si active layer region  2 . After the formation of the reverse-characteristic layer  7  as above-mentioned, a short time heat treatment (RTA: rapid thermal anneal) may be conducted in order to prevent increased-speed diffusion due to defects. Besides, the halo implantation is carried out divisionally in a plurality of times while adjusting the arrangement angle of the SOI substrate  1  arranged in, for example, a halo implantation apparatus (the angle of the surface of the SOI layer relative to the ion implantation direction) according to the arrangement (pattern) of the gate electrodes  5   b  relative to the SOI substrate  1 . In this example, the implantation of the impurity (divisional implantation in eight times) and the RTA for the reverse-characteristic layer  7  were conducted under the following conditions.
 
[Implantation Conditions in the Case of n-MOS]
 
             Impurity: B +   
             Implantation energy: 12 keV 
             Dose: (1×10 13 /cm 2 )×8 times 
             Implantation angle: 28° 
             Range of projection: 37 nm
 
[Implantation Conditions in the Case of p-MOS]
 
             Impurity: P +   
             Implantation energy: 25 keV 
             Dose: (1.4×10 13 /cm 2 )×8 times 
             Implantation angle: 28° 
             Range of projection: 31 nm
 
[RTA Conditions for Reverse-Characteristic layer  7 ]
 
             Annealing temperature: 950°C. 
             Annealing time: 10 sec 
             Atmosphere used: in N 2  atmosphere
 
Next, in  FIG. 5 , first an SiO 2  film  8   a  (for example, 10 nm in thickness) and an Si 3 N 4  film  8   b  (for example, 50 nm in thickness) were sequentially formed so as to cover the gate electrode  5   b , and the Si 3 N 4  film  8   b  and the SiO 2  film  8   a  were processed into desired patterns by etching, to form side walls  8 . In this example, the formation of the SiO 2  film  8   a  and the formation of the Si 3 N 4  film  8   b  were conducted under the same conditions as those for the formation of the SiO 2  film and the formation of the Si 3 N 4  film  3   b  in the device separation regions  4  described above.
 
           
         
       
    
     Thereafter, with the side walls  8  as a mask, an impurity was implanted into the Si active layer region  3   a  (source/drain portions) to a depth larger (for example, a little larger) than the impurity in the extension portions  6 , to form a source/drain layer  9 . As a result, the extension portions  6  remain only at the portions located beneath the side walls  8 . In this example, RTA was conducted for activating the source/drain layer  9 . Besides, the implantation of the impurity into the source/drain layer  9  and the RTA were conducted under the following conditions. Generally, in the case of forming a source/drain layer by an implantation energy not less than 5 keV, the implantation angle is set at about 7° in order to prevent channeling. 
     [Implantation Conditions in the Case of n-MOS] 
     
         
         
           
             Impurity: P +   
             Implantation energy: 15 keV 
             Dose: (2×10 15 /cm 2 )×4 times 
             Implantation angle: 7°
 
[Implantation Conditions in the Case of p-MOS]
 
             Impurity: B +   
             Implantation energy: 5 kev 
             Dose: (1 ×10 15 /cm 2 )×4 times 
             Implantation angle: 7°
 
[RTA Conditions for Source/Drain Layer  9 ]
 
             Annealing temperature: 950° C. 
             Annealing time: 10 sec 
             Atmosphere used: in N 2  atmosphere
 
Then, a thin film of Co (for example, 5 nm in thickness) was formed so as to cover the surfaces of the source/drain portions (source/drain layer  9 ) in the Si active layer region  2   a  and the gate electrode  5   b  by sputtering, and the surfaces of the source/drain portions in the Co film (and the surface of the gate electrode  5   b ) were silicidized by RTA, to form a silicide film  10  (and a gate silicide film  5   d ) composed of CoSi.
 
           
         
       
    
     Thereafter, the Co film at portions other than the surfaces of the source/drain portions (and the surface of the gate electrode  5   b ) (namely, the Co film located on the surfaces of the side walls  8  and the device separation regions  4 ) was removed by an aqueous sulfuric acid solution. In this example, the formation of the silicide film  10  (and the gate silicide film  5   d ) and the RTA were conducted under the following conditions. 
     [Film Formation Conditions for the Silicide Film  10 ] 
     
         
         
           
             Gas used: Ar=100 sccm 
             Pressure: 0.4 Pa 
             Heated substrate temperature: 450° C. 
             DC power: 0.8 kW
 
[RTA Conditions for the Silicide Film  10 ]
 
             Annealing temperature: 550° C. 
             Annealing time: 30 sec 
             Atmosphere used: in N 2  or N 2 /Ar atmosphere
 
Furthermore, the silicide film  10  formed as above-mentioned was subjected again to RTA (hereinafter referred to as re-RTA), and the CoSi film was further brought into reaction with the Si layer of the Si active layer region to convert it into a CoSi 2  film, whereby the resistance of the silicide film  10  was sufficiently lowered. In this example, the re-RTA was conducted under the following conditions.
 
[Re-RTA Conditions]
 
             Annealing temperature: 700° C. 
             Annealing time: 30 sec 
             Atmosphere used: in N 2  or N 2 /Ar atmosphere
 
Incidentally, it has been found that the thickness of the Si layer consumed at the time of forming the CoSi 2  film by silicidization is about 3.64 times that of the Co film formed by sputtering, and the thickness of the CoSi 2  film obtained is about 3.52 times that of the Co film. Therefore, when the SOI layer  2  having a thickness of 29 nm is used and the Co film having a thickness of 5 nm is formed in the silicide film  10  as in the present example, a CoSi 2  film having a thickness of about 18 nm is formed, so that an Si layer having a thickness of about 11 nm is left at the portion located beneath the CoSi 2  film.
 
           
         
       
    
     Next, as shown in  FIG. 6 , for example an SiO 2  film was built up so as to cover the surfaces of the source/drain portions of the Si active layer region  2   a  and the surfaces of the device separation regions  4 , the gate silicide film  5   d  and the side walls  8  in the SOI substrate  1  by a low pressure CVD method to form an inter-layer insulation film  11  (for example, 700 nm in thickness), and thereafter contact holes  11   a  for electrical connection were opened on the upper side of the silicide film  10  in the inter-layer insulation film  11  by desired lithography and etching. In this example, the etching for opening the contact holes  11   a  was conducted under the following conditions. 
     [Etching Conditions for Contact Holes  11   a]   
     
         
         
           
             Gas used: C 4 F 8 /CO/Ar=10/100/200 sccm 
             Pressure: 6 Pa 
             Heated substrate temperature: 20° C. 
             RF power: 1600 W
 
Thereafter, a Ti film (for example, 20 nm in thickness) and a TiN film (for example, 30 nm in thickness) were sequentially formed on the surfaces of the inside walls (and the bottom portions) of the contact holes  11   a  by sputtering, to form barrier metals  12   a . Furthermore, a W film was formed so as to fill up the contact holes  11   a  by a CVD method, and the W film at portions other than the contact holes  11   a  was etched back, to form contact plugs  12  (and desired wiring or the like), whereby a semiconductor device was manufactured. In this example, the formation of the barrier metals  12   a  (the Ti film and the TiN film) and the formation and etching of the contact plugs  12  (the W film) were carried out under the following conditions.
 
[Film Formation Conditions for Ti Film]
 
             Gas used: Ar=100 sccm 
             Pressure: 0.4 Pa 
             Heated substrate temperature: 200° C. 
             DC power: 6 kW
 
[Film Formation Conditions for TiN Film]
 
             Gas used: Ar/N 2 =20/70 sccm 
             Pressure: 0.4 Pa 
             Heated substrate temperature: 200° C. 
             Microwave: 12 kW
 
[Film Formation Conditions for W Film]
 
             Gas used: WF 6 /H 2 /Ar=80/500/2800 sccm 
             Pressure: 10640 Pa 
             Heated substrate temperature: 400° C.
 
[Etch-Back Conditions for W Film]
 
             Gas used: SF 6 /Ar=110/90 sccm 
             Pressure: 35 Pa 
             RF power: 275 W
 
In the semiconductor device of the p-MOS manufactured by the example described above, the sheet resistance of the extension portions when the halo implantation energy was varied was measured, and the results are shown in the characteristic diagram of  FIG. 7 . Besides, in the semiconductor device of the p-MOS, the threshold voltage when the semiconductor device was manufactured by setting the halo implantation energy at 15 keV (the range of projection reaching the inside of the Si active layer region) and 25 keV (the range of projection reaching the inside of the buried oxide film) and by varying the gate length was measured, and the results are shown in the characteristic diagram of  FIG. 8 .
 
           
         
       
    
     From the results shown in  FIG. 7 , it is seen that the sheet resistance of the extension portions is lowered as the halo implantation energy is raised. In addition, from the results shown in  FIG. 8 , it is confirmed that, by conducting the halo implantation so that the range of projection reaches the inside of the buried oxide film, a sufficient threshold voltage can be secured even when the gate length is small, and good roll-off characteristic can be obtained. 
     As has been described above, according to the present embodiment, by forming the reverse-characteristic layer through adjusting the implantation energy and the implantation angle so that the range of projection in the halo implantation reaches the inside of the buried oxide film in the SOI substrate, it is ensured that the reverse-characteristic layer is formed on the body portion side of the extension portions in the Si active layer region, so that the roll-off characteristic can be improved. In addition, since the reverse-characteristic layer is scarcely formed at the extension portions, the rise of the sheet resistance in the extension portions can be suppressed. 
     While the present invention has been described in detail above only as to the described embodiment, it is apparent to those skilled in the art that a variety of modifications and corrections are possible within the technical thought of the invention, and it is natural that such modifications and corrections belong to the scope of the appended claims. 
     For example, while the implantation angle in the halo implantation has been set at 28° in the present embodiment, it suffices for the angle to be so set that the implanted impurity is implanted on the body portion side of the extension portions in the Si active layer region without being interfered by the device separation regions adjacent to the implanted surface (in the example, the surface of the Si active layer region), the gate electrode or the like. 
     Besides, while the full-silicide structure comprising CoSi 2  has been shown in the silicide film, the material and structure for the gate electrode and the silicide film are not limited to those described above. Further, the materials for the SOI substrate (the Si substrate, the buried oxide film, and the SOI layer), the gate insulation film, the gate electrode, the extension portions, the source/drain layer and the like are not limited to those described in the above embodiment, and the same functions or effects as those of the above embodiment can be obtained also when the various materials described in the paragraph of “Summary of the Invention” are applied. 
     While a preferred embodiment of the present invention has been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.