Patent Publication Number: US-7710701-B1

Title: System and method for providing a process, temperature and over-drive invariant over-current protection circuit

Description:
TECHNICAL FIELD OF THE INVENTION 
   The system and method of the present invention is generally directed to the manufacture of integrated circuits and, in particular, to a system and method for providing a process, temperature and over-drive invariant over-current protection circuit. 
   BACKGROUND OF THE INVENTION 
   The design of a typical power supply circuit may be characterized as a voltage regulation problem. Experienced circuit designers recognize, however, that the task of designing an efficient power supply circuit requires that the issues of current measurement and current control be considered. One of the most important reasons for monitoring current in a power supply circuit is to be able to provide current limit or over-load protection for the power supply circuit. 
   In prior art circuits the current limit function is normally placed inside power integrated circuit (IC) chips in order to save external board area and to reduce the cost of manufacturing the power supply circuit. In the case of switching regulators (which include power switches inside the IC chip) the over-load protection is usually implemented inside the IC chip by sensing the current through power switching and then comparing the sensed signal with a reference signal to determine whether the power supply is in an over-load condition. 
   Because components outside of the IC chip have no control of the current limit, it is a very important and challenging task to be able to keep the accuracy of over-load protection during variations of operating conditions such as process, temperature and over-drive voltage variations. It would be desirable to have a current sense and current limit circuit that could guarantee an overall performance of over-load protection under variable operating conditions. 
     FIG. 1  illustrates a schematic diagram of a prior art current sense and current limit circuit  100 . Circuit  100  comprises a level shifter  110  having an output connected to the input of a driver  120  as shown in  FIG. 1 . Level shifter  110  receives an input signal from an IN node. Level shifter  110  and driver  120  both receive a CBOOT signal from a CBOOT node. Level shifter  110  and driver  120  both receive an SW signal from a SW node. 
   The output of driver  120  is connected to the gate of an n-channel transistor  130  (designated M 1 ) and to the gate of an n-channel transistor  140  (designated M 2 ). Transistor  130  M 1  is a high-side Power Field Effect Transistor (FET). Transistor  130  M 1  is sometimes referred to as power transistor  130  M 1 . Transistor  140  M 2  is a sense Field Effect Transistor (FET) that has a much smaller size than Transistor  130  M 1 . For example, a typical width of transistor  130  M 1  is ten thousand microns (10K μ) and a typical width of transistor  140  M 2  is ten microns (10μ). Resistor  150  (designated R 1 ) is a current sense resistor. Resistor  160  (designated R 3 ) is a current reference resistor. Typical values of resistance for resistor  150  R 1  and for resistor  160  R 3  are in the range of one thousand ohms (1 kΩ) to ten thousand ohms (10 kΩ). 
   As shown in  FIG. 1 , the drain of transistor  130  M 1  is connected to a first end of current sense resistor  150  R 1  and to a first end of current reference resistor  160  R 3  and to the input voltage node VIN that supplies the input voltage V IN . The source of transistor  130  M 1  is connected to the SW node. The drain of transistor  140  M 2  is connected to a second end of the current sense resistor  150  R 1  and to a sense “drain to source voltage” node (designated “VDS sen” in  FIG. 1 ). The source of transistor  140  M 2  is connected to the SW node. 
   The second end of the current reference resistor R 3  is connected to a reference “drain to source voltage” node (designated “VDS ref” in  FIG. 1 ). The second end of the current reference resistor R 3  is also connected to a first side of a current source  170  (designated I 1 ). The second side of the current source  170  I 1  is connected to ground. 
   When the input signal IN is high, transistor  130  M 1  and transistor  140  M 2  are fully turned on and both of them are operating in the triode region. The voltage drop across the drain and source of transistor  130  M 1  (designated V DS1 ) is given by the expression:
 
V DS1 ≅I O R DSON1   Eq. (1)
 
   In Equation (1) the expression I O  represents the load current and the expression R DSON1  represents the drain to source resistance of transistor  130  M 1 . 
   The voltage drop V R1  across the current sense resistor  150  R 1  is given by the expressions:
 
 V   R1   =V   IN   −V   VDS sen   Eq. (2)
 
   
     
       
         
           
             
               
                 
                   V 
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 = 
                 
                   
                     V 
                     
                       DS 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                     
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
   
   
     
       
         
           
             
               
                 
                   V 
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 = 
                 
                   
                     I 
                     O 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     R 
                     
                       DSON 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                     
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
   
   The expression V VDSsen  represents the reference drain to source voltage on the drain of transistor  140  M 2 . The expression V DS1  represents the drain to source voltage of transistor  130  M 1 . The expression R DSON2  represents the drain to source resistance of transistor  140  M 2 . From Equation (4) one can see that the voltage drop V R1  is proportional to the value of the load current I O . 
   The reference current passes through current reference resistor  160  R 3 . The current reference resistor  160  R 3  sets the current limit trip value. When the voltage drop across the current sense resistor  150  R 1  is greater than the voltage drop across the current reference resistor R 3 , then the voltage on the VDSsen node will be lower than the voltage on the VDSref node. The voltage on the VDSsen node and the voltage on the VDSref node are provided to the inputs of a current limit comparator circuit (not shown in  FIG. 1 ). When the voltage on the VDSsen node is lower than the voltage on the VDSref node then the current limit comparator will be triggered and the output of the current limit comparator will go high to flag this fault condition. 
   The current limit will be tripped when the voltage drop across the current sense resistor  150  R 1  is equal to the voltage drop across the current reference resistor  160  R 3 . This equality condition is expressed as:
 
V R1 =V R3   Eq. (5)
 
   The equality condition leads to the result: 
   
     
       
         
           
             
               
                 
                   
                     I 
                     O 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     R 
                     
                       DSON 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                     
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                 
                 = 
                 
                   
                     I 
                     REF 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   R 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   3 
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
   
   The limit value I O(LIMIT)  of the load current I O  is: 
   
     
       
         
           
             
               
                 
                   I 
                   
                     O 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       ( 
                       LIMIT 
                       ) 
                     
                   
                 
                 = 
                 
                   
                     I 
                     REF 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         
                           R 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         + 
                         
                           R 
                           
                             DSON 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                       
                       ) 
                     
                     
                       R 
                       
                         DSON 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
   
   From Equation (7) it would seem that in order to guarantee that the current trip value keeps constant over input voltage (V IN ) variations, temperature variations, and process variations, then the current sense resistor  150  R 1 , and the current reference resistor  160  R 3 , and the resistors R DSON1  and R DSON2  should be the same type of resistors and match over a wide range (assuming that the reference current I REF  has a zero temperature coefficient). 
   In reality this requirement cannot be met because all of the underlying requirements cannot be simultaneously satisfied. The mismatch of the resistors causes the current limit trip value to vary widely over the input voltage (V IN ) variations, and the temperature variations, and the process variations. 
     FIG. 2  illustrates simulation results for the prior art current sense and current limit circuit  100  over temperature for a range of different over-drive voltages for an ideal current limit of four amperes (4.0 A). As shown in  FIG. 2 , the temperature ranges from minus forty degrees Celsius (−40° C.) to a positive one hundred degrees Celsius (+140° C.). The current range is from three amperes (3.0 A) to six amperes (6.0 A). 
   The variation of the current limit trip value as a function of temperature for an overdrive voltage of four volts (4.0 V) is shown in curve  210 . The variation of the current limit trip value as a function of temperature for an overdrive voltage of five volts (5.0 V) is shown in curve  220 . The variation of the current limit trip value as a function of temperature for an overdrive voltage of six volts (6.0 V) is shown in curve  230 . 
   The results illustrated in  FIG. 2  show that there is a variation of over sixty percent (60%) in the current limit trip value. This is even without the process variations being considered. It would be very difficult for a designer of power supply circuitry to design an efficient power supply circuit when faced with such wide variations in the current limit trip value. 
   Therefore, there is a need in the art for a system and method that is capable of solving the poor performance problems that are exhibited by prior art devices. In particular, there is a need in the art for a system and method for providing an efficient process, temperature and over-drive invariant over-current protection circuit. 
   The present invention provides an over-current protection circuit that comprises a power transistor, a sense transistor, at least one current sense transistor and at least one current reference transistor. The over-current protection circuit provides a current limit trip value that remains substantially constant over temperature variations, and over-drive voltage variations, and process variations. 
   Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. 
   Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
       FIG. 1  illustrates a schematic diagram of a prior art current sense and current limit circuit; 
       FIG. 2  illustrates a graph of current versus temperature showing simulation results for the prior art current sense and current limit circuit shown in  FIG. 1  for a range of different over-drive voltages; 
       FIG. 3  illustrates a schematic diagram of a current sense and current limit circuit of the present invention; and 
       FIG. 4  illustrates a graph of current versus temperature showing simulation results for the current sense and current limit circuit of the present invention shown in  FIG. 3  for a range of different over-drive voltages. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 3 and 4 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented with any type of suitably arranged current sense and current limit device. 
     FIG. 3  illustrates a schematic diagram of a current sense and current limit circuit  300  of the present invention. The current sense and current limit circuit  300  of the present invention solves the problem of the wide variation of the current limit trip value over variable conditions of process, temperature and over-drive voltage. 
   Circuit  300  of the present invention comprises a level shifter  310  having an output connected to the input of a driver  315  as shown in  FIG. 3 . Level shifter  310  receives an input signal from an IN node. Level shifter  310  and driver  315  both receive a CBOOT signal from a CBOOT node. 
   The CBOOT node is connected a first side of a first diode  320  (designated D 1 ) and to a first side of a capacitor  325  (designated C 1 ). A second side of the first diode  320  D 1  is connected to a first side of a first voltage source  330  (designated V 1 ). The second side of the first voltage source  330  is connected to ground. 
   Level shifter  310  and driver  315  both receive an SW signal from an SW node. The SW node is connected to a second side of the capacitor  325 . The SW node is also connected to a first side of an inductor  335  (designated L). The second side of the inductor  335  is connected to ground. The SW node is also connected to a first side of a second diode  340  (designated D 2 ). A second side of the second diode  340  is connected to ground. 
   The output of driver  315  is connected to the gate of an n-channel transistor  345  (designated MN 4 ) and to the gate of an n-channel transistor  350  (designated MN 5 ). Transistor  350  MN 5  is a high-side Power Field Effect Transistor (FET). Transistor  350  MN 5  is sometimes referred to as power transistor  350  MN 5 . Transistor  345  MN 4  is a sense Field Effect Transistor (FET) that has a much smaller size than transistor  350  MN 5 . For example, a typical width of the power transistor  350  MN 5  is ten thousand microns (10K μ) and a typical width of the sense transistor  345  MN 4  is ten microns (10μ). Transistor  350  MN 5  in  FIG. 3  is analogous to transistor  130  M 1  in  FIG. 1 . Transistor  345  MN 4  in  FIG. 3  is analogous to transistor  140  M 2  shown in  FIG. 1 . 
   As shown in  FIG. 3 , the drain of transistor  350  MN 5  is connected to the input voltage node VIN that supplies the input voltage V IN . The VIN node is connected to a first side of a second voltage source  355  (designated V 2 ). The second side of the second voltage source  355  is connected to ground. The source of transistor  350  MN 5  is connected to the SW node. 
   The drain of transistor  345  MN 4  is connected to a source of an n-channel transistor  360  MN 2  and to a sense “drain to source voltage” node (designated “VDS sen” in  FIG. 3 ). The source of transistor  345  MN 4  is connected to the SW node. The drain of transistor  360  MN 2  is connected to the input voltage node VIN. Transistor  360  MN 2  in  FIG. 3  is analogous to current sense resistor  150  R 1  in the prior art circuit  100  shown in  FIG. 1 . Transistor  360  MN 2  will sometimes be referred to as current sense transistor  360  MN 2 . 
   Circuit  300  also comprises an n-channel transistor  365  (designated MN 1 ) and an n-channel transistor  370  (designated MN 3 ). A typical width of transistor  365  MN 1  is ten microns (10μ). A typical width of transistor  370  MN 3  is also ten microns (10μ). The source of transistor  370  MN 3  is connected to a reference “drain to source voltage” node (designated “VDS ref” in  FIG. 3 ). The source of transistor  370  MN 3  is also connected to a first side of a current source  375  (designated Iref). The second side of the current source  375  is connected to ground. 
   The “VDS ref” node is connected to a non-inverting input of a current limit comparator circuit  380 . The “VDS sen” node is connected to an inverting input of the current limit comparator circuit  380 . The output of the current limit comparator circuit  380  provides the current limit trip value. The output of the current limit comparator circuit  380  is connected to the current limit trip value output node (designated “CNT_LIMIT” in  FIG. 3 ). 
   The drain of transistor  370  MN 3  is connected to a source of transistor  365  MN 1 . The drain of transistor  365  MN 1  is connected to the input voltage node VIN. Transistor  370  MN 3  and transistor  365  MN 1  in  FIG. 3  are analogous to current reference resistor  160  R 3  in the prior art circuit  100  shown in  FIG. 1 . Transistor  370  MN 3  and transistor  365  MN 1  will sometimes be referred to as current reference transistor  370  MN 3  and current reference transistor  365  MN 1 . 
   The drain of transistor  365  MN 1  is also connected to a first end of a resistor  385  (designated R 1 ). A typical value of resistance for the resistor  385  R 1  is ten thousand ohms (10 kΩ). The second end of resistor  385  R 1  is connected to a source of a p-channel transistor  390  (designated M 1 ). The drain of the transistor  390  M 1  is connected to the CBOOT node. The gate of the transistor  390  M 1  is connected to the input voltage node VIN. The second end of resistor  385  R 1  is also connected to the gate of transistor  365  MN 1  and to the gate of transistor  360  MN 2  and to the gate of transistor  370  MN 3 . 
   The length of the transistor  365  MN 1  and the length of the transistor  350  MN 5  are the same. The size of the transistor  365  MN 1  and the size of the transistor  370  MN 3  are the same. 
   The operation of circuit  300  of the present invention will now be described. When the input signal IN is high, then transistor  350  MN 5  is fully turned on and the voltage on the SW node will be close in value to the voltage on the VIN node. Through the capacitor  325  C 1 , the voltage on the CBOOT node will be higher in value than the voltage on the on the VIN node. This higher value of voltage on the CBOOT node will then turn on the p-channel transistor  390  M 1 , and the n-channel transistors  365  MN 1 ,  360  MN 2  and  370  MN 3 . Transistor  365  MN 1  and transistor  350  MN 5  are in the triode region and have similar over-drive voltage. 
   The voltage drop across the drain and source of the transistor  350  MN 5  (designated V DS5 ) is given by the expression:
 
V DS5 ≅I O R DSON5   Eq. (8)
 
   In Equation (8) the expression I O  represents the load current and the expression R DSON5  represents the drain to source resistance of the power transistor  350  MN 5 . 
   The voltage drop V DS2  across the drain and source of the current sense transistor  360  MN 2  is given by the expressions:
 
 V   DS2   =V   IN   −V   VDS sen   Eq. (9)
 
   
     
       
         
           
             
               
                 
                   V 
                   
                     DS 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 = 
                 
                   
                     V 
                     
                       
                         DS 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         5 
                       
                       ⁢ 
                       
                           
                       
                     
                   
                   ⁢ 
                   
                     
                       R 
                       
                         DSON 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       + 
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                       
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
   
   
     
       
         
           
             
               
                 
                   V 
                   
                     DS 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 = 
                 
                   
                     I 
                     O 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       R 
                       
                         DSON 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         5 
                       
                     
                     
                         
                     
                   
                   ⁢ 
                   
                     
                       R 
                       
                         DSON 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       + 
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                       
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
   
   The expression V VDSsen  represents the sense voltage at the source of the transistor  360  MN 2 . The expression V DS2  represents the drain to source voltage across the transistor  360  MN 2 . The expression R DSON2  represents the drain to source resistance of transistor  360  MN 2 . The expression R DSON5  represents the drain to source resistance of transistor  350  MN 5 . From Equation (11) one can see that the voltage drop V DS2  is proportional to the value of the load current I O . 
   The reference current passes through transistor  365  MN 1  and through transistor  370  MN 3 . This causes transistor  365  MN 1  and transistor  370  MN 3  to set the current limit trip value. When the voltage drop across transistor  360  MN 2  is greater than the voltage drop across transistor  365  MN 1  and transistor  370  MN 3 , the voltage on the VDSsen node (at the source of transistor  360  MN 2 ) will be lower than the voltage of the VDSref node (at the source of transistor  370  MN 3 ). This will trigger the current limit comparator  380  and the output of the current limit comparator  380  will go high to flag this fault condition. 
   The current limit will be tripped when the voltage drop across the transistor  360  MN 2  is equal to the voltage drop across the transistor  365  MN 1  and transistor  370  MN 3 . This equality condition is expressed as:
 
 V   DSON2   =V   DSON1   +V   DSON3   Eq. (12)
 
   The equality condition leads to the result: 
   
     
       
         
           
             
               
                 
                   
                     I 
                     O 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     R 
                     
                       DSON 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       R 
                       
                         DSON 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       + 
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                       
                     
                   
                 
                 = 
                 
                   
                     I 
                     REF 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                       + 
                       
                         R 
                         
                           DSON 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                     
                     ) 
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
   
   The limit value I O(LIMIT)  of the load current I O  is: 
   
     
       
         
           
             
               
                 
                   I 
                   
                     O 
                     ⁡ 
                     
                       ( 
                       LIMIT 
                       ) 
                     
                   
                 
                 = 
                 
                   
                     I 
                     REF 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         
                           R 
                           
                             DSON 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         + 
                         
                           R 
                           
                             DSON 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                         
                       
                       ) 
                     
                     
                       R 
                       
                         DSON 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         
                           R 
                           
                             DSON 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         + 
                         
                           R 
                           
                             DSON 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             4 
                           
                         
                       
                       ) 
                     
                     
                       R 
                       
                         DSON 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         5 
                       
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
   
   Now assume that all of the transistor devices are operating in the deep triode region. Also assume that transistor  365  MN 1  and transistor  370  MN 3  are the same size. Then one obtains 
   
     
       
         
           
             
               
                 
                   R 
                   DSON 
                 
                 = 
                 
                   μ 
                   · 
                   
                     C 
                     OX 
                   
                   · 
                   
                     w 
                     L 
                   
                   · 
                   
                     V 
                     OV 
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
   
   The term μ·C OX  is a process parameter for the field effect transistors (FETs). The letter L represents the length of the transistor. The expression V OV  represents the over-drive voltage. In the current sense and current limit circuit  300  of the present invention the terms μ·C OX  and L and V OV  are the same for the transistors MN 1  through MN 5  (i.e., transistor  365  (MN 1 ), transistor  360  (MN 2 ), transistor  370  (MN 3 ), transistor  345  (MN 4 ), and transistor  350  (MN 5 )). 
   The letter “w” represents the width of each respective transistor. The term w 1  represents the width of transistor  365  (MN 1 ). The term w 2  represents the width of transistor  360  (MN 2 ). The term w 3  represents the width of transistor  370  (MN 3 ). The term w 4  represents the width of transistor  345  (MN 4 ). The term w 5  represents the width of transistor  350  (MN 5 ). 
   Using the expression set forth in Equation (15), it is possible to simplify Equation (14) to: 
   
     
       
         
           
             
               
                 
                   I 
                   
                     O 
                     ⁡ 
                     
                       ( 
                       LIMIT 
                       ) 
                     
                   
                 
                 = 
                 
                   
                     I 
                     REF 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       w 
                       2 
                     
                     
                       0.5 
                       ⁢ 
                       
                         w 
                         1 
                       
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         
                           w 
                           2 
                         
                         + 
                         
                           w 
                           4 
                         
                       
                       ) 
                     
                     
                       
                         w 
                         2 
                       
                       ⁢ 
                       
                         w 
                         4 
                       
                     
                   
                   ⁢ 
                   
                     w 
                     5 
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   16 
                   ) 
                 
               
             
           
         
       
     
   
   Equation (16) can be further simplified to: 
   
     
       
         
           
             
               
                 
                   I 
                   
                     O 
                     ⁡ 
                     
                       ( 
                       LIMIT 
                       ) 
                     
                   
                 
                 = 
                 
                   
                     I 
                     REF 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       w 
                       5 
                     
                     
                       0.5 
                       ⁢ 
                       
                         w 
                         1 
                       
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         
                           w 
                           2 
                         
                         + 
                         
                           w 
                           4 
                         
                       
                       ) 
                     
                     
                       w 
                       4 
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   17 
                   ) 
                 
               
             
           
         
       
     
   
   From Equation (17) it is seen that the current limit trip value is only related to the widths of transistor  365  MN 1 , transistor  360  MN 2 , transistor  345  MN 4  and transistor  350  MN 5 . The current limit trip value is not related to any other factors (e.g., temperature). Because the transistors of the present invention are the same kind of device they have much better matching than the matching in the prior art device  100  (e.g., matching of resistor  150  and resistor  160  with the effective resistance R DSON  of transistor  130  M 1  and transistor  140  M 2 ). 
   The current sense and current limit circuit  300  of the present invention provides a substantially constant current limit trip value over variations in process, temperature and over-drive voltages. This feature is illustrated by simulation results shown in  FIG. 4 . 
     FIG. 4  illustrates a graph  400  of current versus temperature showing simulation results for the current sense and current limit circuit of the present invention  300  for a range of different over-drive voltages for an ideal current limit of four amperes (4.0 A). As shown in  FIG. 4 , the temperature ranges from minus forty degrees Celsius (−40° C.) to a positive one hundred degrees Celsius (+140° C.). The current range is from three and eighty three hundredths amperes (3.83 A) to three and ninety one hundredths amperes (3.91 A). 
   The variation of the current limit trip value as a function of temperature for an overdrive voltage of four volts (4.0 V) is shown in curves  410 ,  420  and  430 . The curve designated  410  represents the variation of the current trip value with respect to temperature for a fast process corner. The curve designated  420  represents the variation of the current trip value with respect to temperature for a typical process corner. The curve designated  430  represents the variation of the current trip value with respect to temperature for a slow process corner. 
   The variation of the current limit trip value as a function of temperature for an overdrive voltage of five volts (5.0 V) is shown in curves  440 ,  450  and  460 . The curve designated  440  represents the variation of the current trip value with respect to temperature for a fast process corner. The curve designated  450  represents the variation of the current trip value with respect to temperature for a typical process corner. The curve designated  460  represents the variation of the current trip value with respect to temperature for a slow process corner. 
   The variation of the current limit trip value as a function of temperature for an overdrive voltage of six volts (6.0 V) is shown in curves  470 ,  480  and  490 . The curve designated  470  represents the variation of the current trip value with respect to temperature for a fast process corner. The curve designated  480  represents the variation of the current trip value with respect to temperature for a typical process corner. The curve designated  490  represents the variation of the current trip value with respect to temperature for a slow process corner. 
   The simulation results illustrated in  FIG. 4  show that there is only a one and seven tenths percent (1.7%) variation of the current limit trip value under severe condition variations. These results show that the current sense and current limit circuit of the present invention  300  significantly improves the current limit accuracy under variable operating conditions. 
   The system and method of the present invention provides a substantially constant value of current limit trip value over a wide variation of operating conditions. The present invention provides a significant improvement in the accuracy of over-load protection during variations in temperature, process and over-drive voltage. The current sense and current limit circuitry of the present invention is not complex. Therefore, it will not be necessary to increase design complexity and die size to manufacture the current sense and current limit circuitry of the present invention. 
   The magnitude of the reference current in the present invention can be made arbitrarily small by adding additional transistors in series with transistor  365  MN 1  and transistor  370  MN 3 . Alternatively, the magnitude of the reference current in the present invention can be made arbitrarily small by increasing the attenuation of transistor  360  MN 2  and transistor  345  MN 4 . 
   The foregoing description has outlined in detail the features and technical advantages of the present invention so that persons who are skilled in the art may understand the advantages of the invention. Persons who are skilled in the art should appreciate that they may readily use the conception and the specific embodiment of the invention that is disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Persons who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 
   Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.