Patent Publication Number: US-8543966-B2

Title: Test path selection and test program generation for performance testing integrated circuit chips

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of integrated circuits; more specifically, it relates to methods of selecting critical delay paths of integrated circuits for performance testing integrated circuit chips. 
     BACKGROUND 
     A current method of testing the performance of integrated circuits relies on a functional test of the logic circuits of the integrated circuits. This method consumes large amounts of time and computer/tester resource to generate the test code and to perform the actual test itself. Another current method of testing the performance of integrated circuits relies on performing a performance screen on ring oscillators formed in various physical locations on the integrated circuit chip. The problem with this technique is false rejects and false accepts because ring oscillator performance does not measure metal line variation. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove. 
     SUMMARY 
     A first aspect of the present invention is a method, comprising: identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths. 
     A second aspect of the present invention is a method, comprising: (a) identifying clock domains having multiple critical paths of an integrated circuit design having multiple clock domains; (b) selecting a clock domain of the multiple clock domains; (c) selecting N critical paths of the clock domain; (d) using a computer, retaining only sensitizable critical paths of the N critical paths; (e) selecting M of the sensitizable critical paths to include paths from different regions of the integrated circuit design and to include sensitizable paths of different Vt families; (f) generating timing test margins for the M sensitizable critical paths; (g) setting up test clock frequencies for each of the M sensitizable critical paths; (h) repeating steps (b) through (g) for each clock domain of the multiple clock domains. 
     A third aspect of the present invention is a method, comprising: (a) generating a latch location file of critical path latches of an integrated circuit design; (b) partitioning the integrated circuit design into R multiple contiguous regions, each region including at least one clock domain; (c) selecting a region of the multiple regions; (d) selecting a clock domain of the selected region; (e) selecting critical path latches of the clock domain; (f) selecting Z latches of the critical path latches of the clock domain; (g) for each of the Z latches selecting P statistical paths; (h) using a computer, retaining only sensitizable paths of the Z*P statistical paths; (i) selecting W sensitizable paths of the sensitizable paths the Z*P statistical paths; (j) repeating steps (d) through (i) for each clock domain of the selected region; (k) selecting K of sensitizable paths of W sensitizable paths of all clock domains of the selected region; (l) repeating steps (c) through (k) for all the regions of the integrated circuit design; and (m) returning K times R sensitizable paths grouped by clock domain. 
     A fourth aspect of the present invention is a computer program product, comprising: a computer usable storage device having a computer readable program code embodied therein, the computer readable program code comprising an algorithm adapted to implement a method for test path selection and test program generation for performance testing integrated circuit chips, the method comprising the steps of: identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and creating a test program to performance test the test paths. 
     These and other aspects of the invention are described below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
         FIG. 1  illustrates clock domains and data paths of an exemplary integrated circuit chip; 
         FIG. 2  illustrates the exemplary integrated circuit chip of  FIG. 1  partitioned into regions for practicing an embodiment of the present invention; 
         FIG. 3  is an exemplary schematic diagram of a scan latch circuit used in testing logic circuits of integrated circuits; 
         FIG. 4  is a schematic diagram illustrating two critical paths belonging to different clock domains in a same region of an integrated circuit chip; 
         FIG. 5  is an exemplary schematic diagram of a simple logic circuit illustrating the principle of path sensitization; 
         FIG. 6  is a flow diagram of the concept of test path selection according to embodiments of present invention; 
         FIG. 7  is a flow diagram of the general method of test path selection according to embodiments of present invention; 
         FIG. 8  is a flow diagram of the method of verifying the selected test paths according to embodiments of present invention; 
         FIG. 9  is a flow diagram of a method of selecting test paths according to an embodiment of the present invention; 
         FIG. 10  is a flow diagram of a method of selecting test paths according to another embodiment of the present invention; and 
         FIG. 11  is a schematic block diagram of a general-purpose computer that may be used in practicing embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments of the present invention select critical paths (paths where timing delays are critical to the integrated circuit meeting performance specifications) from each clock domain of the integrated circuit. The selection is performed using methodologies that ensure that the selected critical paths provide test coverage for all physical regions of the integrated circuit chip having clocked logic circuits by selecting paths from all clock domains. The method of the embodiments of the present invention may be called Path Performance Testing (PPT). 
     The term critical path is defined as a data path between an input point and an output point where the time delay of the data signal being presented at the input point and received at the output point must be between upper and lower performance specifications or the integrated circuit will be rejected. Not all data paths are critical paths. In one example, the input and output points of data paths are latches. In one example, the input and output points of data paths are latches of Level Sensitive Scan Design (LSSD) scan chains. 
       FIG. 1  illustrates clock domains and data paths of an exemplary integrated circuit chip. In  FIG. 1 , an integrated circuit chip  100  includes a clock domain  105  having critical paths  107  and  108 , a clock domain  110  having a critical path  112 , a clock domain  115  having critical paths  117  and  118  and a clock domain  120  having a critical path  122 . A clock domain is logical region of an integrated circuit chip where the elements (e.g., latches, logic gates, etc.) of all critical paths are clocked with the same clock signal. The clock signals of different clock domains may differ from each other in, for example, having different periods, different frequencies, being independently powered (some clock domains may be turned off while others remain powered) and are not necessarily synchronous to each other. While four clock domains are illustrated in  FIG. 1 , there may be more or less than four clock domains. The number of critical paths within any given clock domain may be more than tens of thousands. 
       FIG. 2  illustrates the exemplary integrated circuit chip of  FIG. 1  partitioned into regions for practicing an embodiment of the present invention. In  FIG. 2 , integrated circuit  100  has been partitioned into sixteen contiguous regions A 1 , A 2 , A 3 , A 4 , B 1 , B 2 , B 3 , B 4 , C 1 , C 2 , C 3 , C 4 , D 1 , D 2 , D 3 , and D 4 . Some regions include portions of only one clock domain (e.g., clock region A 1  includes only a portion of clock region  105 ) and some clock regions may include portions of multiple clock regions (e.g., region B 1  includes a portion of clock domain  105  and  110 ). Some regions may include no clock domains. While critical paths  108 ,  112 ,  117 ,  118  and  122  of  FIG. 1  are not illustrated in  FIG. 2  for clarity, critical path  107  has been illustrated to show that any given critical paths may cross region boundaries. For example, critical path  107  starts in region B 1 , passes through region B 2 , then through A 2 , back again into region B 2 , then through region B 3  and ends in region A 3 . 
       FIG. 3  is an exemplary schematic diagram of a scan latch circuit used in testing logic circuits of integrated circuits. In  FIG. 3 , and LSSD scan chain  125  includes a first set of latches  130 A through  130 N, a second set of latches  140 A through  140 N and a third set of latches  150 A through  150 N. Each latch has a first input for operational data, a second input for test data, a first output for operational data and a second output for resultant test data. Data is clocked through logic gates in clouds of logic  135 A through  135 N from respective latches  130 A through  130 N to respective latches  140 A through  140 N by a data clock, usually designated the “A” clock. Data is clocked through logic gates in clouds of logic  145 A through  145 N from respective latches  140 A through  140 N to respective latches  150 A through  150 N by the same data clock. Test data is clocked through latches  130 A through  130 N, latches  140 A through  140 N and through latches  150 A through  150 N, by a first test clock, usually designated clock “C.” Test data is clocked through logic circuits  135 A to  145 A through logic circuits  135 N to  145 N by a second test clock, usually designated clock “B.” Clock “A” is the domain clock. A critical path starts and stops with a scan latch and includes a data path within the logic gates of the logic cloud connected by the two scan latch, for example latch  130 A, logic cloud  135 A and latch  140 A. It is possible for other scan latch to be part of the critical path between the two latches, for example, latch  130 C, logic cloud  135 C, latch  140 C, cloud of logic  145 C and latch  150 C. 
       FIG. 4  is a schematic diagram illustrating two critical paths belonging to different clock domains in a same region of an integrated circuit chip. In region  155 , a logic circuit  160  of a first clock domain comprises latches  161 ,  162 ,  163  and  164  and delays D 1 , D 2 , D 3 , D 4  and D 5 . The delays represent the timing delay through combination logic (sequences of logic gates). There are three possible critical paths for logic circuit  160 . The first is latch  163 , delay D 4 , delay D 5 , and latch  164 . The second is latch  162 , delay D 3 , delay D 5 , and latch  164 . The third is latch  161 , delay D 1 , delay D 2 , latch  162 , delay D 3 , delay D 5 , and latch  164 . Region  155  also includes a logic circuit  170  of a second clock domain and comprising latches  171  and  172  and delay D 6 . Logic circuit  160  presents a problem in that the output at latch  164  depends on the output of delays D 3  and D 4 . This is resolved by an algorithm called “branch-and-bound.” 
       FIG. 5  is an exemplary schematic diagram of a simple logic circuit illustrating the principle of path sensitization. In  FIG. 5 , a logic circuit comprises an AND gate A 1  having a first input A and a second input B, and output D which is also a first input of a NAND gate N 1 , having a second input C and an output E. To robustly test the path A to E, C must be kept a zero if a fault on A is to be detected independent of the value on B. The test pattern generated for testing the path A to E must include placing a zero on C while A transitions from zero to one and from one to zero. The same is true for robustly testing the path B to E. Application of path sensitization ensures that only robust tests are created for a given critical path, with no glitches, false fails or false accepts (test escapes). 
       FIG. 6  is a flow diagram of the concept of test path selection according to embodiments of present invention. In step  200 , an integrated circuit is designed. In step  205 , a beginning of life timing simulation for all data paths is performed to generate process parameter values. For example, the simulated delay of path i is Di. Running a canonical timing model of path i gives the delay as a function of nominal process delay DNi and process parameter induced delay SPi. Solving the equation Di=DNi+Σ P (SPi) gives values for path i for DN and Sp. The equation is solvable when the number of paths n is larger than the number of parameters P. In step  210 , the critical paths are identified. In step  215 , the sensitizable paths are identified. The sensitizable paths are the subset of critical paths that are testable. Sensitizable paths are generated, for example, using an Automatic Test Pattern Generator (ATPG) check program. In step  220 , a subset of the sensitizable paths (i.e., test paths) is selected to ensure adequate integrated circuit chip test coverage. The test paths should provide test coverage for delay limits (e.g., 2σ, 3σ, etc.) for the following process parameters: across chip variations (e.g., high and low density of polysilicon lines, high and low density of substrate isolation, density of wiring, etc.) and wiring levels (e.g., which wiring levels are used and the length of wire on each level). Test paths should not be chosen from chip regions with large AC power drops as the voltage will not be the same along the whole path and the transistors in the path will switch at different nominal speeds. A general methodology for selecting the subset of sensitizable parts is described infra with respect to  FIGS. 7 and 8 . More specific embodiments are described infra with respect to  FIGS. 9 and 10 . In step  225 , a test program is generated, for example, a PPT At Speed Structural Test (ASST) including Test Manufacturing Data (TMD) is generated. The TMD contains the information required to setup a tester to perform PPT ASST testing according to embodiments of the present invention. 
       FIG. 7  is a flow diagram of the general method of test path selection according to embodiments of present invention. In step  230 , the test environment is defined. This includes running an across-chip AC power noise simulation which includes power-up-power-down cycling to select a power level range having minimum or no signal-to power coupling noise to perform a static timing simulation. Then the static timing is performed with the selected power range and a test temperature, to set beginning of life timing parameters. In step  235 , the test coverage method for PPT (see  FIGS. 9 and 10  and discussion infra) is selected. In step  240 , critical paths by clock domain are selected. In step  245 , for each critical path, timing delay sensitivities to process parameter are calculated. In step  250 , a subset of the critical paths (i.e., test paths) is selected. The selection criteria includes: selecting critical paths with a range of different process parameters and selecting critical paths within the low power supply voltage variation region of the integrated circuit design. The low power supply voltage variation regions are determined from the AC power noise simulation of step  230 . It is preferred that the critical paths start in regions of the integrated circuit away from power sources (e.g., where power is physically supplied to the integrated circuit. In step  255 , test path delay limits acceptance limits are setup. These include worst case (WC) (e.g., late data arrival and early clock at the input point of the path) and best case (BC) (e.g., early data arrival and late clock at the input point of the path). In step  260 , the frequency shmooed delay of each path of a subset of the critical paths is run on a sample of integrated circuit chips using a tester. The results are evaluated in step  280  of  FIG. 8  discussed infra. 
       FIG. 8  is a flow diagram of the method of verifying the selected test paths according to embodiments of present invention. In step  270 , the integrated circuit design is timed as described supra. In step  275 , the test paths are selected as described supra. In step  280 , the test paths are evaluated by testing a sample of physical integrated circuit chips as illustrated in steps  255 ,  260  and  265  of  FIG. 7  and described supra. In step  285  it is determined from the regression analysis if the Path ASST TMD results are acceptable. If the results are acceptable, then in step  290 , the Path ASST TMD is released to manufacturing test. If the results are acceptable, then in step  295 , the test paths selection “rules” are modified and the method loops back to step  275 . 
       FIG. 9  is a flow diagram of a method of selecting test paths according to an embodiment of the present invention. In step  300 , the first/next clock domain of the integrated circuit is selected. In step  305 , N critical paths are selected based on a branch-and-bound algorithm. N is an integer greater than 1. In one example, N is at least about 1000. In step  310 , an ATPG check is run on the N paths and only the sensitizable (e.g., testable) paths are retained. In step  315 , a path file is created. The path file includes such information as physical path location, designed path timing delay, designed slack (slack is the difference between required arrival time of data at a latch and the actual time the data arrives), and designed upper and lower timing bounds (e.g., WC and BC) for each path. In step  320 , M of the sensitizable paths are selected to include paths from different regions of the chip and to include a variety of paths of different Vt (threshold voltage) families because the designed delay in a path is a function of the designed Vt of the transistors of the circuit path. M is an integer greater than 1. It should be understood that the term paths of different Vt does not mean that the path has transistors of different Vt, but rather, the transistors of one path have different Vts of another path, the transistors in any given path having the same Vt. In one example, step  320  is performed automatically. In one example, step  320  is performed manually. In one example, step  320  is performed automatically and then adjusted manually. In step  325 , timing test margins (frequency and/or voltage) for the M sensitizable paths are generated based on the maximum frequency of the clock circuit (often a phase-lock-loop (PLL) circuit) generating the clock signal of the current clock domain. In step  330 , the clock spreadsheet generated during design of the integrated circuit is updated to reflect the test clock frequency to be used for each of the M paths based on the test margins of step  330 . In one example, step  330  is performed automatically. In one example, step  330  is performed manually. In one example, step  330  is performed automatically and then adjusted manually. In step  335 , it is determined if there is another clock domain to process. If so, the method loops back to step  300 , otherwise the method proceeds to step  340 . In step  340 , a path ASST is generated based on the updated clock spreadsheet. In step  345 , a path ASST TMD is generated using, for example, an ATPG tool. Note M and N may vary from clock domain to clock domain. 
       FIG. 10  is a flow diagram of a method of selecting test paths according to another embodiment of the present invention. In step  400 , a latch location file is generated. The latch location file includes the location on the integrated circuit of all scan latches (e.g., LSSD latches) in the integrated circuit design. In step  405 , the integrated circuit design is partitioned into X by Y (=R) regions. See for example,  FIG. 2  where X=Y=4 and integrated circuit  100  has been partitioned into 16 regions. In step  410 , a loop of steps by region is started. In step  415 , a sub-loop of steps by clock domain is started which is performed for all clock domains in the current region. There are C clock domains in each region, but C may vary from region to region. X is an integer greater than 1. Y is an integer greater than 1. C is an integer greater than 1. 
     Starting the clock domain sub-loop, in step  420 , all latches in the Current region and using the clock of the current clock domain are selected. In step  425 , Z latches having the highest slack sensitivities to Vt families are selected. In order to break “ties” slack sensitivities to wiring parameters (e.g., length of wires by wiring level), test margins (e.g., voltage, frequency), may be used. Z is an integer greater than 1. In one example, Z=200. In step  430 , for each of the Z latches, P statistical [define statistical] paths are selected based on process parameter sensitivities (e.g., across chip variations (e.g., high and low density of polysilicon lines, high and low density of substrate isolation, density of wiring, etc.) and wiring levels (e.g., which wiring levels are used and the length of wire on each level). P is an integer greater than 1. In one example, P=5. In step  435 , an ATPG check is run on the Z*P (in the examples, 200*5=1000). It is preferred that the values of Z and P should be chosen to present about a thousand paths with P about two orders of magnitude greater than Z. In step  435 , an ATPG check is run on the Z*P paths to remove unsensitizable paths. In step  440 , W sensitizable paths having the highest slack sensitivities to Vt families are selected. In order to break “ties” slack sensitivities to wiring parameters (e.g., length of wires by wiring level), test margins (e.g., voltage, frequency), may be used. In one example, W=2. Steps  420  through  440  are repeated for each clock domain in the current region. 
     Continuing the region loop, in step  445 , K of the W*C sensitizable paths having the highest slack sensitivities to Vt families are selected. In order to break “ties” slack sensitivities to wiring parameters (e.g., length of wires by wiring level), test margins (e.g., voltage, frequency), may be used. In one example, K=2. In step  450 , the test timing margins (voltage, frequency) are calculated for the K paths. Steps  410 ,  445  and  450  are repeated for each region. 
     In step  455 , there will be X*Y*K sensitizable paths grouped by clock domains. In the example of X=4, Y=4 and K=2 there will be 32 paths. In step  460 , a path ASST is generated for PPT testing the X*Y*K sensitizable paths. Also a path ASST TMD is generated using, for example, an ATPG tool. Note M and N may vary from clock domain to clock domain. 
     Generally, the method described herein with respect to methods for selecting critical paths for performance testing integrated circuit chips is practiced with a general-purpose computer and the methods described supra in the flow diagrams of  FIGS. 6 ,  7 ,  8 ,  9  and  10  may be coded as a set of instructions on removable or hard media for use by the general-purpose computer. 
       FIG. 11  is a schematic block diagram of a general-purpose computer that may be used in practicing embodiments of the present invention. In  FIG. 11 , computer system  500  has at least one microprocessor or central processing unit (CPU)  505 . CPU  505  is interconnected via a system bus  510  to a random access memory (RAM)  515 , a read-only memory (ROM)  520 , an input/output (I/O) adapter  525  for connecting a removable data and/or program storage device  530  and a mass data and/or program storage device  535 , a user interface adapter  540  for connecting a keyboard  545  and a mouse  550 , a port adapter  555  for connecting a data port  560  and a display adapter  565  for connecting a display device  570 . 
     ROM  520  contains the basic operating system for computer system  500 . The operating system may alternatively reside in RAM  515  or elsewhere as is known in the art. Examples of removable data and/or program storage device  530  include magnetic media such as floppy drives and tape drives and optical media such as CD ROM drives. Examples of mass data and/or program storage device  535  include electronic, magnetic, optical, electromagnetic, infrared, and semiconductor devices. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD. In addition to keyboard  545  and mouse  550 , other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected to user interface  540 . Examples of display devices include cathode-ray tubes (CRT) and liquid crystal displays (LCD). 
     A computer program with an appropriate application interface may be created by one of skill in the art and stored on the system or a data and/or program storage device to simplify the practicing of this invention. In operation, information for the computer program created to run the present invention is loaded on the appropriate removable data and/or program storage device  530 , fed through data port  560  or typed in using keyboard  545 . 
     Certain portions of embodiments of the present invention are practiced with a computer (e.g., computer  500  of  FIG. 11 ) linked to or included in a test system. 
     Thus the embodiments of the present invention provide methods of selecting critical delay paths of integrated circuits for performance testing integrated circuit chips; the methods allow performance testing of integrated circuit chips that require less time and resource than conventional performance testing methods and at the same time reduce, if not eliminate, false accepts and false rejects. 
     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.