Patent Publication Number: US-10312159-B2

Title: BiMOS device with a fully self-aligned emitter-silicon and method for manufacturing the same

Description:
RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 15/083,774, filed Mar. 29, 2016 (now U.S. Pat. No. 9,812,369), which claims priority under 35 U.S.C. § 119 to German Patent Application No. 102015208133.8, filed on Apr. 30, 2015, the contents of which are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     Embodiments relate to a method for manufacturing a bipolar junction transistor. Further embodiments relate to a method for manufacturing a BiMOS device (BiMOS is a semiconductor technology that integrates a bipolar junction transistor and a MOS device (MOS=metal-oxide-semiconductor) in one single integrated circuit device). Further embodiments relate to a BiMOS device. Some embodiments relate to a BiCMOS structure featuring a fully self-aligned emitter-silicon with advantageous vertical dimensions (BiCMOS is a semiconductor technology that integrates a bipolar junction transistor and a CMOS transistor (CMOS=complementary metal-oxide-semiconductor) in one single integrated circuit device). 
     BACKGROUND 
     In a common BiCMOS architecture in which the emitter is manufactured in a self-aligned way relative to the collector and the base, the emitter silicon is patterned by means of a damascene process. However, this process flow inevitably results in the upper edge of the emitter silicon to be located above the upper edge of the CMOS gate. Due to the longer feed line length, this result in an increase in the emitter resistance, which has a negative impact on the switching frequency of the bipolar device. 
     Up to now, the emitter is patterned by a poly-CMP process (CMP=chemical mechanical polishing) with a stop on the GC topography (GC=Gate Conductor). This results in pattern breaking at the wafer edge and in a strong dependence of the emitter height on the specific layout (occupancy density, surroundings) of more than ±30 nm among various layouts. 
     Therefore, it would be desirable to have a concept for manufacturing a BiMOS device that allows adjusting an height of an emitter of a bipolar junction transistor of the BiMOS device (substantially) independent on a height of a gate of a MOS device of the BiMOS device. 
     SUMMARY 
     Embodiments provide a method for manufacturing a bipolar junction transistor. The method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate, wherein the layer stack comprises a first isolation layer arranged on a surface region of the substrate, a sacrificial layer arranged on the first isolation layer and a second isolation layer arranged on the sacrificial layer, wherein the layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to the surface region of the substrate. The method further comprises providing a collector layer of the first semi conductive type on the substrate within the window of the layer stack. The method further comprises providing a base layer of a second semi conductive type on the collector layer within the window of the layer stack. The method further comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved, wherein the emitter layer is of the first semi conductive type. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer. 
     Further embodiments provide a method for manufacturing a BiMOS device, i.e. a bipolar junction transistor and a MOS device on the same substrate. The method comprises providing a substrate of a first conductive type. The method further comprises providing a MOS device on a surface region of the substrate. The method further comprises providing a layer stack, wherein the layer stack is arranged on the surface region of the substrate and in a MOS region on the MOS device, wherein the layer stack comprises a first isolation layer arranged on the surface region of the substrate and in the MOS region on the MOS device, a sacrificial layer arranged on the first isolation layer and a second isolation layer arranged on the sacrificial layer, wherein the layer stack comprises in a bipolar region, different from the MOS region, a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to the surface region of the substrate. The method further comprises providing a collector layer of the first semi conductive type on the substrate within the window of the layer stack. The method further comprises providing a base layer of a second semi conductive type on the collector layer within the window of the layer stack. The method further comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved and such that the emitter layer or emitter layer stack is arranged on the second isolation area also in the MOS region, wherein the emitter layer is of the first semi conductive type. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer in the bipolar region and the MOS region. 
     Further embodiments provide a BiMOS device. The BiMOS device comprises a substrate of a first conductive type, a MOS device arranged on a surface region of the substrate in a MOS region, and a layer stack arranged on the surface region of the substrate and on the MOS device in the MOS region. The layer stack comprises a first isolation layer arranged on the surface region of the substrate and in the MOS region on the MOS device, a sacrificial layer arranged on the first isolation layer and a second isolation layer arranged on the sacrificial layer. Further, the layer stack comprises in a bipolar region, different from the MOS region, a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to the surface region of the substrate. Further, the BiMOS device comprises a bipolar junction transistor arranged on the surface region of the substrate in the bipolar region, wherein the bipolar junction transistor comprises a collector layer of the first semi conductive type arranged on the substrate within the window of the layer stack, a base layer of a second semi conductive type arranged on the collector layer within the window of the layer stack, and an emitter layer or an emitter layer stack comprising the emitter layer arranged on the base layer within the window of the layer stack, wherein the emitter layer is of the first semi conductive type. Thereby, a distance between the surface region of the substrate and an upper region of the emitter layer or emitter layer stack of the bipolar junction transistor is smaller than a distance between the surface region of the substrate and an upper surface region of the sacrificial layer in the MOS region. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention are described herein making reference to the appended drawings. 
         FIG. 1  shows a flowchart of a method for manufacturing a bipolar junction transistor according to an embodiment; 
         FIG. 2 a    shows a schematic cross-sectional view of the bipolar junction transistor after providing a substrate and a layer stack arranged on the substrate according to an embodiment; 
         FIG. 2 b    shows a schematic cross-sectional view of the bipolar junction transistor after providing the substrate and the layer stack arranged on the substrate according to a further embodiment; 
         FIG. 2 c    shows a schematic cross-sectional view of the bipolar junction transistor after providing the substrate and the layer stack arranged on the substrate according to a further embodiment; 
         FIG. 2 d    shows a schematic cross-sectional view of the bipolar junction transistor after removing the top layer shown in  FIGS. 2 b  and 2 c   , according to an embodiment; 
         FIG. 2 e    shows a schematic cross-sectional view of the bipolar junction transistor after providing a base layer of a second semi conductive type on the collector layer within the window of the layer stack, according to an embodiment; 
         FIG. 2 f    shows a schematic cross-sectional view of the bipolar junction transistor after providing a spacer on sidewalls of the window of the layer stack, according to an embodiment; 
         FIG. 2 g    shows a schematic cross-sectional view of the bipolar junction transistor after providing an emitter layer stack comprising an emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved, according to an embodiment; 
         FIG. 2 h    shows a schematic cross-sectional view of the bipolar junction transistor after selectively removing the emitter layer or emitter layer stack at least up to the second isolation layer, according to an embodiment; 
         FIG. 3  shows a flowchart of a method for manufacturing a BiMOS device according to an embodiment; 
         FIG. 4 a    shows a schematic cross-sectional view of a BiMOS device before selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer in the bipolar region and in the MOS region, according to an embodiment; 
         FIG. 4 b    shows a schematic cross-sectional view of the BiMOS device after selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer in the bipolar region and in the MOS region, according to an embodiment; 
         FIG. 4 c    shows a schematic cross-sectional view of a final BiMOS device according to an embodiment; 
         FIG. 5 a    shows a schematic cross-sectional view of the BiMOS device after providing the emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved and such that the emitter layer stack is arranged on the second isolation layer also in the MOS region, according to an embodiment; 
         FIG. 5 b    shows in a diagram the ratio of the resulting divot from a conformal deposition to the deposition thickness (divot/dep) for an emitter width of 250 nm; 
         FIGS. 5 c  and 5 d    show in a table a divot depth (relative divot depth and absolute divot depth) as a function of a deposited silicon thickness and emitter width; 
         FIG. 6 a    shows a scanning electron microscope image of the bipolar region of the BiMOS device; 
         FIG. 6 b    shows a scanning electron microscope image of the bipolar region of the BiMOS device; 
         FIG. 6 c    shows a scanning electron microscope image of the MOS region of the BiMOS device; 
         FIG. 7 a    shows a scanning electron microscope image of the MOS region of the BiMOS device with a new dielectric stack; and 
         FIG. 7 b    shows a scanning electron image of a step coverage of a conventional deposition on a CMOS gate topography. 
     
    
    
     Equal or equivalent elements or elements with equal or equivalent functionality are denoted in the following description by equal or equivalent reference numerals. 
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows a flowchart of a method  10  for manufacturing a bipolar junction transistor (BJT). The method comprises a step  12  of providing a substrate of a first conductive type and a layer stack arranged on the substrate, wherein the layer stack comprises a first isolation layer arranged on a surface region of the substrate, a sacrificial layer arranged on the first isolation layer and a second isolation layer arranged on the sacrificial layer, wherein the layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to the surface region of the substrate. The method further comprises a step  14  of providing a collector layer of the first semi conductive type on the substrate within the window of the layer stack. The method further comprises a step  16  of providing a base layer of a second semi conductive type on the collector layer within the window of the layer stack. The method further comprises a step  18  of providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved, wherein the emitter layer is of the first semi conductive type. The method further comprises a step  20  of selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer. 
     In the following, the method  10  for manufacturing the bipolar junction transistor is described in detail with respect to  FIGS. 2 a  to 2 h   , which show schematic cross-sectional views of the bipolar junction transistor after different steps of the method  10  for manufacturing the bipolar junction transistor. 
       FIG. 2 a    shows a schematic cross-sectional view of the bipolar junction transistor  100  after providing a substrate  102  and a layer stack  104  arranged on the substrate  102 . The substrate  102  can be of the first conductive type. The layer stack  104  can comprise a first isolation layer  106  arranged on a surface region  108  of the substrate  102 , a sacrificial layer  110  arranged on the first isolation layer  106  and a second isolation layer  112  arranged on the sacrificial layer  110 . The layer stack  104  can comprise a window  114  formed in the layer stack  104  through the second isolation layer  112 , the sacrificial layer  110  and the first isolation layer  106  up to the surface region  108  of the substrate  102 . 
     Observe that the expression “arranged on” as used herein may refer to that a first layer (e.g. the first isolation layer  106 ) is arranged directly on a second layer (e.g. the substrate  102 ), i.e. without a third layer between the first layer and the second layer. However, the expression “arranged on” as used herein may also refer to that a third layer is arranged between the first layer (e.g. the first isolation layer  106 ) and the second layer (e.g. the substrate  102 ). 
     At least one out of the first isolation layer  106  and the second isolation layer  112  can comprise a relative permittivity of less than 9. According to an exemplary implementation, at least one out of the first isolation layer  106  and the second isolation layer  112  can comprise a relative permittivity of less than 7. The relative permittivity of the first isolation layer  106  and/or the second isolation layer  112  might be chosen to less than 7 when the sacrificial layer is a SiN (silicon nitride) layer. Further, at least one out of the first isolation layer  106  and the second isolation layer  112  can comprise a relative permittivity of less than 4.5. For example, at least one out of the first isolation layer  106  and the second isolation layer  112  can be a SiO 2  (silicon dioxide) layer which comprises a relative permittivity of 4.3. 
     Thus, as indicated in  FIG. 2 a   , the first isolation layer can be a first SiO 2  layer, wherein the second isolation layer can be a second SiO 2  layer. Thereby, at least one out of the first isolation layer  106  and the second isolation layer  112  can be a HDP SiO2 layer (HDP=high density plasma), i.e. a SiO2 layer manufactured using a high density plasma process. 
       FIG. 2 b    shows a schematic cross-sectional view of the bipolar junction transistor  100  after providing the substrate  102  and the layer stack  104  arranged on the substrate  102 , according to a further embodiment. Compared to  FIG. 2 a   , the layer stack  104  may optionally further comprise a top layer (or top mask)  120  arranged on the second isolation layer  112 . The top layer  120  can be, for example, a SiN layer (or SiN hardmask). Thereby, the window  114  can be formed in the layer stack  104  also through the top layer  120 . 
       FIG. 2 c    shows a schematic cross-sectional view of the bipolar junction transistor  100  after providing the substrate  102  and the layer stack  104  arranged on the substrate  102 , according to a further embodiment. Compared to  FIG. 2 a   , the layer stack  104  may optionally further comprise a top layer (or top mask)  120  arranged on the second isolation layer  112 . The top layer  120  can be, for example, a carbon layer (or carbon hardmask). The carbon layer can be manufactured using chemical vapor deposition (CVD). Thereby, the window  114  can be formed in the layer stack  104  also through the top layer  120 . 
     As indicated in  FIGS. 2 b  and 2 c   , the first isolation layer  106  and the second isolation layer  112  may comprise a pullback with respect to the sacrificial layer  110  and the optional top layer  120 . For example, as already mentioned, the first isolation layer  106  and the second isolation layer  112  can be SiO 2  layers, wherein in that case the pullback may be achieved using a HF etch process (HF=hydrofluoric acid). 
       FIG. 2 d    shows a schematic cross-sectional view of the bipolar junction transistor  100  after removing the top layer  120  shown in  FIGS. 2 b  and 2 c   . As discussed with respect to  FIGS. 2 b  and 2 c   , the top mask  120  can be a SiN hardmask or a carbon hardmask, respectively. A SiN hardmask can be removed, for example, by a top SiN RTCVD (RTCVD=rapid thermal chemical vapor deposition) SiN (fast etching in HFEG (HFEG=hydrofluoric ethylene glycol (HFEG). or by a dummy SiN LPCVD (LPCVD=low pressure chemical vapor deposition) (slow etching in HFEG). A (CVD) carbon hardmask (as the masking layer) can be removed by a dry and/or wet etch process, or by a damage free strip by O 2  (oxygen) plasma after the SiO 2  pullback. 
     As shown in  FIG. 2 d   , the window  114  formed in the layer stack  104  can comprise a trapezoidal form in at least one out of a first area  122  between the first isolation layer  106  and a second area  124  between the second isolation layer  112 . In  FIG. 2 d   , the window  114  of the layer stack  104  comprises both a trapezoidal form in the first area  122  in between the first isolation layer  106  and a trapezoidal form in the second area  124  in between the second isolation layer  112 . Thereby, the shorter one of the two bases of the trapezoidal form of the first area  122  between the first isolation layer can be facing the sacrificial layer  110 . Similarly, the shorter one of the two bases of the trapezoidal form of the second area  124  between the second isolation layer can be facing the sacrificial layer  110 . 
     In other words, flanks of at least one out of the first isolation layer  106  and the second isolation layer  112  facing the window  114  of the layer stack  104  can be at least partially rounded or beveled (tapered). Thereby, the flanks of at least one out of the first isolation layer  106  and second isolation layer  112  can be at least partly rounded or beveled such that an opening of the window  114  is smaller towards the sacrificial layer  110  than towards a surface region  108  of the substrate  102  or an upper surface region  128  of the second isolation layer  112 . For example, at least one out of the first isolation layer  106  and the second isolation layer  112  can be a SiO 2  layer. In that case, flanks that are at least partially rounded or beveled can be achieved by means (or using) a high density plasma (HDP) process, e.g. HDP SiO 2 . 
     Further, at least one out of the first isolation layer  106  and the second isolation layer  112  can comprise a first isolation sublayer  106 _ 1  and  112 _ 1  having a first etch rate and a second isolation sublayer  106 _ 2  and  112 _ 2  having a second etch rate different from the first etch rate. 
     As already mentioned, at least one out of the first isolation layer  106  and the second isolation layer  112  can be a SiO 2  layer. In that case, the first isolation sublayer  106 _ 1  and  112 _ 1  can be a HDP SiO 2  sublayer, e.g. a SiO 2  layer manufactured using a high density plasma process, wherein the second isolation sublayer  106 _ 2  and  112 _ 2  can be a conformal SiO 2  sublayer. Thereby, for the first isolation layer  106 , the second isolation sublayer (conformal SiO 2  sublayer)  106 _ 2  may be arranged on the substrate  102 , wherein the first isolation sublayer (HDP SiO 2  sublayer)  106 _ 1  may be arranged on the second isolation sublayer (conformal SiO 2  sublayer)  106 _ 2 . For the second isolation layer  112  the first isolation sublayer (HDP SiO 2  sublayer)  112 _ 1  may be arranged on the sacrificial layer  110 , wherein the second isolation sublayer (conformal SiO 2  sublayer)  112 _ 2  may be arranged on the first isolation sublayer (HDP SiO 2  sublayer)  112 _ 1 . 
     The graded wet etch rates of the first and second SiO 2  layers  106  and  112  are indicated in  FIG. 2 d    by the arrows from high to low. The at least partly rounding or tapering of the first and/or second isolation layer  106  and  112  may be achieved by a short hot PHOS (PHOS=) or HFEG. For example, the taper of the first and/or second isolation layer  106  and  112  may be achieved by a dilute HF wet etch or by a dry etch. 
     Note that the above described shape of the layer stack  104  may also be achieved without the optional top layer  120  shown in  FIGS. 2 b    and  2   c.    
     Compared to  FIG. 2 a   ,  FIG. 2 d    further shows a collector layer  130  of the first semi conductive type provided on the substrate  102  within the window  140  of the layer stack  104 . For example, the collector layer  130  may be epitaxially grown on the substrate  102  (and on the first isolation layer  106 ) within the window  114  of the layer stack  104 . The collector layer  130  can be a silicon collector layer. 
       FIG. 2 e    shows a schematic cross-sectional view of the bipolar junction transistor  100  after providing a base layer  132  of a second semi conductive type on the collector layer  130  within the window  114  of the layer stack  104 . For example, the base layer  132  may be epitaxially grown on the collector layer  130  within the window  114  of layer stack  104 . The base layer can be a SiGe (silicon-germanium) layer. Thus, the bipolar junction transistor (BJT)  100  can be a heterojunction bipolar transistor (HBT). 
       FIG. 2 f    shows a schematic cross-sectional view of the bipolar junction transistor  100  after providing a spacer (emitter-base spacer)  140  on sidewalls of the window  114  of the layer stack  104 . The spacer  140  may comprise a SiO 2  layer  142  provided on sidewalls of the window  114  of the layer stack  104 . Optionally, the spacer may further comprise a SiN layer  144  provided on the SiO 2  layer  142 . 
       FIG. 2 g    shows a schematic cross-sectional view of the bipolar junction transistor  100  after providing an emitter layer stack  150  comprising an emitter layer  152  on the base layer  132  (and on the spacer  140 ) within the window  114  off layer stack  104 , such that an overfill of the window  114  of the layer stack  104  is achieved. The emitter layer  152  can be of the first semi conductive type. 
     Providing the emitter layer stack  150  can comprise growing the emitter layer  152  on the base layer  132  within the window  114  of the layer stack  104  and depositing an optional cap layer  154  on the emitter layer  152 . For example, the emitter layer can be epitaxially grown on the base layer  132 . Thereby, in  FIG. 2 g    a monocrystalline grown portion of the emitter layer  152  is indicated with reference numeral  152 ′. The cap layer  154  can be a polysilicon cap layer. The polysilicon cap layer  154  can be deposited using a process that avoids a void in the polysilicon cap layer  154 . For example, LPCVD (LPCVD=low pressure chemical vapor deposition) can be used for depositing the polysilicon cap layer  154 . 
     Instead of providing the emitter layer stack  150  comprising the emitter layer  152  and the cap layer  154 , it is also possible to provide (only) an emitter layer  152  on the base layer  132  within the window  114  of the layer stack  104 , such that an overfill of the window  114  of the layer stack  104  is achieved. 
     As shown in  FIG. 2 g   , the emitter width (EW) can be tapered in order to avoiding seam. 
       FIG. 2 h    shows a schematic cross-sectional view of the bipolar junction transistor  100  after selectively removing the emitter layer  152  or emitter layer stack  150  at least up to the second isolation layer  112 . As indicated in  FIG. 2 h   , optionally the emitter layer  152  or the emitter layer stack  150  can be selectively removed until an overetch of the emitter layer  152  or emitter layer stack  150  within the window  114  of the layer stack  104  is achieved, such that an upper surface region  156  of the emitter layer stack  150  or emitter layer  152  is lower than the upper surface region  128  of the second isolation layer  112 . 
     For example, the emitter layer  152  or emitter stack layer  150  can be selectively removed using a dry etch process. Naturally, also a wet etch process may be used. Further, the etch process may be an isotropic etch process. In other words, an isotropic recess with endpoint can be used for removing the emitter layer  152  or emitter layer stack  150 . Optionally, an overetch of, for example, ±15 nm may be achieved. For example, an emitter having a width of 220 nm may have a resulting height between 30 nm and 80 nm. 
     Observe that the expression “selectively removing” used herein means that (substantially) only the emitter layer  152  or emitter layer stack  150  is removed, or in other words, that the emitter layer  152  or emitter layer stack  150  is removed without removing the second isolation layer  112 . 
     The first semi conductive type can be a n-type, i.e. a semiconductor material comprising primarily free electrons as charge carriers, wherein the second semi conductive type can be a p-type, i.e. a semiconductor material comprising primarily free holes as charge carriers. 
     The above described method  10  for manufacturing the bipolar junction transistor  100  can be advantageously used for manufacturing a BiMOS device. BiMOS is a semiconductor technology that integrates a bipolar junction transistor and a MOS device (MOS=metal-oxide-semiconductor), e.g., a MOS transistor, in one single integrated circuit device. 
       FIG. 3  shows a flowchart of a method  30  for manufacturing a BiMOS transistor device, i.e. a bipolar junction transistor and a MOS device (e.g., MOS transistor) on the same substrate. The method comprises a step  32  of providing a substrate of a first conductive type. The method further comprises a step  34  of providing a MOS device (e.g., a MOS transistor, MOS resistor ora capacitor) on a surface region of the substrate. The method further comprises a step  36  of providing a layer stack, wherein the layer stack is arranged on the surface region of the substrate and in a MOS region on the MOS device, wherein the layer stack comprises a first isolation layer arranged on the surface region of the substrate and in the MOS region on the MOS device, a sacrificial layer arranged on the first isolation layer and a second isolation layer arranged on the sacrificial layer, wherein the layer stack comprises in a bipolar region, different from the MOS region, a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to the surface region of the substrate. The method further comprises a step  38  of providing a collector layer of the first semi conductive type on the substrate within the window of the layer stack. The method further comprises a step  40  of providing a base layer of a second semi conductive type on the collector layer within the window of the layer stack. The method further comprises a step  42  of providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved and such that the emitter layer or emitter layer stack is arranged on the second isolation area also in the MOS region, wherein the emitter layer is of the first semi conductive type. The method further comprises a step  44  of selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer in the bipolar region and the MOS region. 
     Subsequently it is assumed that the MOS device is a MOS transistor. However, the MOS device could also be a resistor or a capacitor causing the same or similar topography than the MOS transistor. 
     In the following, the method  30  for manufacturing the BiMOS device is described in detail with respect to  FIGS. 4 a  to 4 c   , which show schematic cross-sectional views of the BiMOS device after different steps of the method  30  for manufacturing the BiMOS device. 
       FIG. 4 a    shows a schematic cross-sectional view of a BiMOS device  200  before selectively removing the emitter layer  152  or the emitter layer stack  150  at least up to the second isolation layer  112  in the bipolar region and in the MOS region. 
     Further,  FIG. 4 a    shows in the bipolar region of the BiMOS device  200  a bipolar junction transistor  100 . The bipolar junction transistor  100  of the BiMOS device  200  is equal or equivalent to the bipolar junction transistor  100  shown and discussed throughout  FIGS. 1 to 2   h , such that the description thereof is also applicable to the bipolar junction transistor  100  of the BiMOS device  200  shown in  FIGS. 4 a    to  4   c.    
     In addition,  FIG. 4 a    shows in a MOS region of the BiMOS device  200  a MOS transistor  202 , or more precisely, a gate of the MOS transistor  202 . The layer stack  104  is arranged in the MOS region on the MOS transistor  202  and in an area surrounding the MOS transistor  202  on the substrate  102 . 
     The layer stack  104  can be provided on the surface region  108  of the substrate and on the MOS transistor  202  such that a leveling of the second isolation layer  112  caused by the buried MOS transistor  202  (buried under the layer stack  104 ) comprises a maximum inclination of 30° (or 20° or 10° or 5°) relative to the surface region  108  of the substrate  102 . In other words, as indicated in  FIG. 4 a   , the layer stack  104  can be provided such that a sidewall angle smaller than 30° is achieved, which is desired for a residual free poly recess process. 
     Further, as indicated in  FIG. 4 a   , a distance (along a geometrical line parallel to the surface  108  of the substrate  102 ) of 1.5 μm or less between the bipolar junction transistor  100  and the MOS transistor  202 , or more precisely, between a sidewall  141  of the spacer  140  facing the MOS transistor  202  and a sidewall  203  of the gate of the MOS transistor  202 , is achievable by the method  30  for manufacturing the BiMOS device  200  disclosed herein. In contrast to this, a conventional CMP based manufacturing method would require a distance of more than 10 μm to remove material from lower lying regions. 
     Further, a distance between a face (or sidewall) of the emitter window  114  facing the MOS transistor  202  and a face (or sidewall)  203  of a gate (MOS device poly (gate conductor, or poly conductor) of the MOS transistor  202  facing the bipolar junction transistor  100  can be smaller than 200 nm, 500 nm, 1 μm, 1.5 μm or 3 μm. 
     For 130 nm and 90 nm technology, a target gate contact height is 150 nm, wherein a minimum of 120 nm and a maximum of 180 nm is estimated. 
     Further, as can be derived from  FIG. 4 a   , there are no pinching structures in the MOS region due to the HDP step coverage (HDP=high density plasma). 
       FIG. 4 b    shows a schematic cross-sectional view of the BiMOS device  200  after selectively removing the emitter layer  152  or the emitter layer stack  150  at least up to the second isolation layer  112  in the bipolar region and in the MOS region. Thereby, the emitter layer  152  or the emitter layer stack  150  is removed in the bipolar region and in the MOS region up to the second isolation layer  112  without removing the layer stack  104 , or more precisely, the second isolation layer  112 . 
     In  FIG. 4 b    several distances or heights are indicated by arrows. In detail, D 1  indicates a height of the first isolation layer  106 . D 2  indicates a height of the sacrificial layer  110 . D 3  indicates a height of the MOS transistor  202 , or more precisely, of the gate contact of the MOS transistor  202 . D 4  indicates a height of the collector layer  130  and base layer  132 . D 5  indicates a distance between a top surface region of the sacrificial layer  110  and the top surface region  156  of the emitter layer in the bipolar region. D 6  indicates a height of the emitter layer  152  or emitter layer stack  150 . 
     The emitter layer  152  or the emitter layer stack  150  can be removed in the bipolar region and in the MOS region up the second isolation layer  112  such that a distance between the surface region  108  of the substrate  102  and an upper surface region  156  of the emitter layer  152  or emitter layer stack  150  of the bipolar junction transistor  100  is smaller than a distance between the surface region  108  of the substrate  102  and an upper surface region  157  of the sacrificial layer  110  in the MOS region (directly above the MOS transistor  202 ). In other words, a top level  156  of the emitter electrode may be closer to the silicon substrate  102  than D 1 +D 2 +D 3 . 
     Further, the emitter layer  152  or the emitter layer stack  150  can be removed such that a distance between the surface region  108  of the substrate  102  and the upper region  156  of the emitter layer  152  or emitter layer stack  150  of the bipolar junction transistor  100  is smaller than a distance between the surface region  108  of the substrate  102  and an upper surface region  158  of the first isolation layer  106  in the MOS region (above the MOS transistor  202 ). In other words, a top level  156  of the emitter electrode may be closer to the silicon substrate  102  than D 1 +D 3 . 
     Further, the emitter layer  152  or emitter layer stack  150  can be removed such that a distance between the surface region  108  of the substrate  102  and an upper region  156  of the emitter layer  152  or emitter layer stack  150  is smaller than or equal to a distance between the surface region  108  of the substrate  102  and an upper surface region  160  of the MOS transistor  202 . In other words, a top level  156  of the emitter electrode can be closer to the silicon substrate  102  than D 3 . This is the most aggressive case. It allows a shorter HBT stack (HBT=heterojunction bipolar transistor) and thus a faster device. 
     In the following, target dimensions for a SiGe heterojunction bipolar transistor are given. A height D 1  of the first isolation layer  106  can be between 50 and 85 nm (smaller values for high performance). A height D 2  of the sacrificial layer  110  can be between 40 and 80 nm (idem). A height D 3  of the MOS transistor (or MOS gate)  202  can be between 105 and 190 nm (lower limit by reliability, example: 90 nm technology. A height D 4  of the collector layer  130  and base layer  132  together can be 65 to 125 nm (smaller is faster). The distance D 5  between the top surface region of the sacrificial layer  110  and the top surface region  156  of the emitter layer in the bipolar region can be between 0 and 40 nm. A height of the emitter layer  152  or emitter layer stack  150  can be between 40 to 60 nm (minimum limited by silicidation process). 
       FIG. 4 c    shows a schematic cross-sectional view of a final BiMOS device  200  according to an embodiment. Compared to  FIG. 4 b   , in the bipolar region the sacrificial layer  110  has been replaced by a contact layer  170  contacting the base layer  132  of the bipolar junction transistor  100 . Further, a SiN layer  172  has been provided on the substrate  102 , in the bipolar region on the contact layer  170  and emitter layer  152  or emitter stack layer  150 , and in the MOS region on the MOS transistor  202 , or more precisely, on the gate of the MOS transistor  202 . Furthermore, contacts  180  contacting via the contact layer  170  the base layer  132 , the emitter layer  152 , the gate of the MOS transistor  202  and a source/drain of the MOS transistor  202  have been provided. 
     In  FIG. 4 c   , the distances D 1  to D 5  already indicated in  FIG. 4 b    are also indicated. 
     Thereby, the upper surface region  156  of the emitter layer  152  or emitter layer stack  150  of the bipolar junction transistor  100  can be smaller than a sum of a distance between the surface region  108  of the substrate  102  and an upper surface region of the contact layer  170  in the bipolar region and a distance between the surface region  108  of the substrate  102  and an upper surface region  160  of the MOS transistor  202  in the MOS region. In other words, a top level  156  of the emitter electrode may be closer to the silicon substrate  102  than D 1 +D 2 +D 3 . 
     Further, a distance between the surface region  108  of the substrate  102  and an upper surface region  156  of the emitter layer  152  or emitter layer stack  150  of the bipolar junction transistor  100  can be smaller than a sum of a distance between the surface region  108  of the substrate  102  and an upper surface region  173  of the first isolation layer  106  in the bipolar region and a distance between the surface region  108  of the substrate  102  and the upper surface region  160  of the MOS transistor  202  in the MOS region. In other words, a top level  156  of the emitter electrode may be closer to the silicon substrate  102  than D 1 +D 3 . 
     Further, a distance between the surface region  108  of the substrate  102  and an upper region of the emitter layer  152  or emitter layer stack  150  of the bipolar junction transistor  100  can be smaller than or equal to a distance between the surface region  108  of the substrate  102  and an upper surface region  160  of the MOS transistor in the MOS region. In other words, a top level  156  of the emitter electrode may be closer to the silicon substrate  102  than D 3 . 
       FIG. 5 a    shows a schematic cross-sectional view of the BiMOS device  202  after providing the emitter layer stack  150  comprising the emitter layer  152  on the base layer  132  within the window  114  of the layer stack  104 , such that an overfill of the window  114  of the layer stack  104  is achieved and such that the emitter layer stack  150  is arranged on the second isolation layer  112  also in the MOS region (not shown in  FIG. 5 a   ). Thus,  FIG. 5 a    substantially shows the same as  FIG. 4 a   , such that the description of  FIG. 4 a    is also applicable to the BiMOS device  202  shown in  FIG. 5 a   . However, compared to  FIG. 4 a   , in  FIG. 5 a    further an emitter width (EW), a height of the polysilicon layer  154  and a divot are indicated by arrows. Further, in  FIG. 5 a    a height h is indicated describing a height of the polysilicon emitter layer  154  directly above the emitter layer  152 . 
     Thereby,  FIG. 5 a    shows a special case where a thickness or height r 0  of the polysilicon emitter layer  154  is equal to the emitter width (EW_CD). In that case, the divot depth can be calculated to:
 
Divot depth=(1-sqrt(1.25))*EW_CD.
 
     In general the general case, the divot depth can be calculated to:
 
( r 0- h )/ r 0=1-sqrt(1-( e /(2 r 0))^2)
 
     Therefore, a divot of ˜20 nm (or smaller) for a 400 nm deposition is expected. 
       FIG. 5 b    shows in a diagram the ratio of the resulting divot from a conformal deposition to the deposition thickness (divot/dep) for an emitter width (EW_CD) of 250 nm. Thereby, the ordinate describes the ratio of the divot depth to the deposited film thickness and the abscissa describes the deposited film thickness. 
       FIGS. 5 c  and 5 d    show in a table a divot depth (relative divot depth and absolute divot depth) as a function of a deposited silicon thickness and emitter width. Further, in  FIGS. 5 c  and 5 d    the relation (r 0 -h)/r 0 =1 sqrt(1-(e/(2r0)){circumflex over ( 0 )}2) is given. Thereby, in  FIGS. 5 c  and 5 d   , arrows indicate possible target configurations. All values are indicated in nm. 
       FIGS. 6 a  and 6 b    show scanning electron microscope images of bipolar regions of BiMOS device  200  windows, which were filled with emitter material and subsequently recessed to a potential target depth. Further,  FIG. 6 a   , and  FIG. 6 b    show recess depths of 122 nm and 95 nm which closely match the predicted difference derived from the recess depth calculation shown in  FIGS. 5 c  and 5 d    for the emitter recess are indicated. 
     It is noted that for  FIGS. 6 a  and 6 b   , from divot calculation a difference of 25 nm is expected. 
       FIG. 6 c    shows a scanning electron microscope image of the MOS region of the BiMOS device  200 . From  FIG. 6 c    it can be seen that the process enables a surprisingly flat final topography. 
       FIG. 7 a    shows a scanning electron microscope image of the MOS region of the BiMOS device with a new dielectric stack (LPCVD &amp; HDP SiO 2 /LPSiN/HDP SiO 2 ). The profile achieved by HDP 2× SiO 2  has a sidewall angle smaller than 10°. 
       FIG. 7 b    shows a scanning electron image of a step coverage of a conventional deposition on a CMOS gate topography. Note that this is not the target stack, different technology (LPCVD SiO2, PolySi, SiN, from bottom to top). 
     As becomes clear after the above discussion, a BiMOS (or BiCMOS) architecture wherein the emitter is to be produced in a self-aligned way relative to the collector and the base is provided. At present, the emitter silicon is patterned by means of a damascene process. However, this process flow inevitably results in the upper edge of the emitter silicon to be located above the upper edge of the CMOS gate. Due to the longer feed line length, this result in an increase in the emitter resistance, which has a negative impact on the switching frequency of the bipolar device. This problem is solved by the methods for manufacturing disclosed herein, the height of the emitter no longer being linked directly to the height of the MOS gate. Further, process tolerances and process complexity are reduced at the same time. 
     Up to now, the emitter has been patterned by a poly-CMP process, as described before, including a stop on a PC topography. The results were the above described problems relating to pattern breaking at the wafer edge and a strong dependence of the emitter height on the specific layout (occupancy density, surroundings) of more than ±30 nm among various layouts. 
     Instead of using a CMP process including pre-planarization, an advantageous combination of depositions and recess processes based on dry-etching is suggested. 
     Thus, an advantage is that the emitter height may be set to be independent of the MOS gate height, in particular, to be considerably lower than the MOS gate height. This allows minimizing the feed line resistance of the emitter. Further, an advantage is that vertical tolerances are expected to be reduced to less than half the value, thereby reducing the tolerances of electrical parameters considerably. For HBTs (heterojunction bipolar transistors) with fmax &gt;500 GHz, the feed line resistance of an emitter is a decisive quantity for the device performance. Further, an advantage is that the process costs may be reduced, since expensive CMP processes can be avoided. 
     Embodiments provide an HBT architecture wherein the emitter height may be set to be independent of the MOS topography in order to minimize feed line resistances.