Patent Publication Number: US-11044086-B2

Title: Apparatus for generating identification key and management method thereof

Description:
TECHNICAL FIELD 
     The following description relates to a digital security field, and more particularly, to an apparatus for generating an identification key used for a digital signature and an encryption and decryption method, and a management method thereof. 
     BACKGROUND ART 
     A physically unclonable function (PUF) may provide an unpredictable digital value. Individual PUFs may provide different digital values, even though an accurate manufacturing process is provided and the individual PUFs are manufactured through the same manufacturing process. 
     The PUF may be referred to as a “physical one-way function (POWF)” that is practically impossible to be duplicated, or as a “physical random function (PRF).” 
     The above characteristic of the PUF may be used to generate an encryption key for security and/or authentication. For example, the PUF may be used to provide a unique key to distinguish devices from one another. 
     Korean Patent Registration No. 10-1139630 (hereinafter, referred to as “&#39;630 patent”) provides a method of implementing a PUF. The &#39;630 patent discloses a method of generating a PUF by probabilistically determining whether an inter-layer contact or a via is generated between conductive layers or conductive nodes of a semiconductor, based on a semiconductor process variation. 
     In one of embodiments disclosed in the &#39;630 patent, a via to be formed between conductive layers may be designed to be small in size, and accordingly a situation in which the via is formed, and a situation in which the via is not formed may randomly occur. In other words, a random digital value may be generated, and artificially guessing of the random digital value is impossible. 
     (Patent Document 1) Korean Patent Registration No. 10-1139630 
     DISCLOSURE OF INVENTION 
     Technical Solutions 
     According to an aspect, there is provided an identification key generation apparatus including an identification key provider configured to provide a plurality of resistors generated based on a random connection state between conductive layers of a semiconductor due to a semiconductor process variation, a discriminator configured to discriminate a first group having a resistance value greater than a first threshold value and less than a second threshold value among the plurality of resistors, and a reader configured to read at least one resistor that does not belong to the first group among the plurality of resistors, and to provide an identification key in a form of a digital value. 
     The identification key generation apparatus may further include a controller configured to record, in a memory, information used to identify a resistor included in the first group among the plurality of resistors. The information used to identify the resistor included in the first group may be an address of the resistor included in the first group among the plurality of resistors. 
     The plurality of resistors may be vias or contacts located between the conductive layers. 
     The discriminator may include a first discrimination element configured to determine whether a value of each of the plurality of resistors is greater than the first threshold value, in a first time interval, and a second discrimination element configured to determine whether a value of each of the plurality of resistors is greater than the second threshold value, in a second time interval different from the first time interval. 
     The discriminator may further include a third discrimination element configured to determine whether a value of each of the plurality of resistors is greater than a third threshold value, and the third threshold value may be greater than the first threshold value and less than the second threshold value. The reader may be configured to provide the identification key based on a result of a comparison between the third threshold value and a value of at least one resistor that does not belong to the first group among the plurality of resistors. 
     According to another aspect, there is provided an identification key generation apparatus including an identification key provider configured to provide a plurality of resistors generated based on a random connection state between conductive layers of a semiconductor due to a semiconductor process variation, a discriminator configured to discriminate a first group having a resistance value greater than a first threshold value and less than a second threshold value among the plurality of resistors, using a pull-up resistor configured to pull an output voltage applied to each of the plurality of resistors up to a supply voltage in an off state of a selection transistor, and a reader configured to read at least one resistor that does not belong to the first group among the plurality of resistors and to provide an identification key in a form of a digital value. 
     The discriminator may be configured to discriminate, as the first group, a resistor at which a time required to discharge the output voltage to be less than or equal to a threshold voltage after the selection transistor is turned on is greater than a first threshold time and less than a second threshold time, among the plurality of resistors. 
     The reader may be configured to read the identification key based on a result of a comparison between a third threshold time and the time required to discharge the output voltage to be less than or equal to the threshold voltage, using at least one resistor that does not belong to the first group among the plurality of resistors, and the third threshold time may be greater than the first threshold time and less than the second threshold time. 
     The discriminator may be configured to discriminate, as the first group, a resistor of which the output voltage is greater than a first threshold voltage and less than a second threshold voltage when a predetermined reference time elapses after the selection transistor is turned on, among the plurality of resistors. 
     The reader may be configured to read the identification key based on a result of a comparison between the output voltage and a third threshold voltage, using at least one resistor that does not belong to the first group among the plurality of resistors, and the third threshold voltage may be greater than the first threshold voltage and less than the second threshold voltage. 
     According to another aspect, there is provided a method of generation an identification key, the method including discriminating a first group having a resistance value greater than a first threshold value and less than a second threshold value among a plurality of resistors generated based on a random connection state between conductive layers of a semiconductor due to a semiconductor process variation, and reading at least one resistor that does not belong to the first group among the plurality of resistors and generating an identification key in a form of a digital value. 
     The method may further include recording, in a memory, information used to identify a resistor included in the first group among the plurality of resistors. The information used to identify the resistor included in the first group may be an address of the resistor included in the first group among the plurality of resistors. 
     The plurality of resistors may be either vias or contacts located between the conductive layers. 
     The discriminating of the first group may include determining whether a value of each of the plurality of resistors is greater than the first threshold value, in a first time interval, and determining whether a value of each of the plurality of resistors is greater than the second threshold value, in a second time interval different from the first time interval. 
     The discriminating of the first group may further include determining whether a value of each of the plurality of resistors is greater than a third threshold value, the third threshold value being greater than the first threshold value and less than the second threshold value. The generating of the identification key may include generating the identification key based on a result of a comparison between the third threshold value and a value of at least one resistor that does not belong to the first group among the plurality of resistors. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram illustrating an identification key generation apparatus according to an embodiment. 
         FIG. 2  is a diagram illustrating a characteristic of a physically unclonable function (PUF) of a via of an identification key generation apparatus according to an embodiment. 
         FIG. 3  is a diagram illustrating a characteristic of a PUF of a via of an identification key generation apparatus according to an embodiment. 
         FIG. 4  is a diagram illustrating a process of discriminating a resistance of an inter-layer contact or a via in an identification key generation apparatus according to an embodiment. 
         FIGS. 5A and 5B  are diagrams illustrating a discriminator of an identification key generation apparatus according to an embodiment. 
         FIGS. 6A through 6C  are diagrams illustrating a reader of an identification key generation apparatus according to an embodiment. 
         FIG. 7  is a diagram illustrating a reader of an identification key generation apparatus according to an embodiment. 
         FIG. 8  is a diagram illustrating a reader of an identification key generation apparatus according to an embodiment. 
         FIGS. 9A and 9B  are diagrams illustrating a discriminator of an identification key generation apparatus according to an embodiment. 
         FIGS. 10A and 10B  are diagrams illustrating a reader of an identification key generation apparatus according to an embodiment. 
         FIGS. 11 and 12  are diagrams illustrating a reader of an identification key generation apparatus according to an embodiment. 
     
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     The following structural or functional descriptions are exemplary to merely describe embodiments, and the scope of the embodiments is not limited to the descriptions provided in the present specification. Various changes and modifications can be made thereto after an understanding of the present disclosure. 
     Although terms of “first” or “second” are used to explain various components, the components are not limited to the terms. These terms should be used only to distinguish one component from another component. For example, a “first” component may be referred to as a “second” component, or similarly, and the “second” component may be referred to as the “first” component. 
     It will be understood that when a component is referred to as being “connected to” another component, the component may be directly connected or coupled to the other component or intervening components may be present. 
     As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components or a combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined herein, all terms used herein including technical or scientific terms have the same meanings as those generally understood by one of ordinary skill in the art after an understanding of the present disclosure. Terms defined in dictionaries generally used should be construed to have meanings matching with contextual meanings in the related art and the present disclosure and are not to be construed as an ideal or excessively formal meaning unless otherwise defined herein. 
     In the following description, embodiments may be used to recognize a fingerprint of a user. An operation of recognizing a fingerprint of a user may include an operation of authenticating or identifying the user. In an example, an operation of authenticating a user may include an operation of determining whether the user is enrolled in advance. In this example, a result obtained by authenticating the user may be output as true or false. In another example, an operation of identifying a user may include an operation of determining that the user corresponds to any one user among a plurality of pre-enrolled users. In this example, a result obtained by identifying the user may be output as an identification (ID) of any one pre-enrolled user. When the user does not correspond to any one user among the plurality of pre-enrolled users, a signal indicating that the user is not identified may be output. 
     Embodiments may be implemented as various types of products, for example, personal computers (PCs), laptop computers, tablet computers, smartphones, televisions (TV), smart home appliances, intelligent vehicles, kiosks or wearable devices. For example, examples embodiments may be employed to authenticate a user in a smartphone, a mobile device or a smart home system. Embodiments may be applicable to a payment service by user authentication. Also, examples embodiments may be applicable to an intelligent vehicle system to automatically start a vehicle by authenticating a user. Hereinafter, examples embodiments will be described in detail below with reference to the accompanying drawings, and like reference numerals refer to the like elements throughout. 
       FIG. 1  is a block diagram illustrating an identification key generation apparatus according to an embodiment. 
     In an example, an identification key generation apparatus  100  may include an identification key provider  110 , a discriminator  120  and a reader  130 . The identification key generation apparatus  100  may further include a memory (not shown) and a controller (not shown). 
     The identification key provider  110  may provide an identification key having randomness, using a semiconductor process. For example, the identification key provider  110  may include an inter-layer contact or via (inter-layer contact/via)  113  that connects a first node  111  and a second node  112  corresponding to conductive layers of a semiconductor. 
     Generally, an inter-layer contact or a via is designed to connect conductive layers, whereas in an embodiment, the inter-layer contact/via  113  may be intentionally designed to have randomness so that nodes may be shorted or open in a semiconductor process, which has been disclosed in detail in the &#39;630 patent. A connection characteristic of the inter-layer contact/via  113  formed as described above may be measured and expressed as a resistance value between the first node  111  and the second node  112  that are connected by the inter-layer contact/via  113 . Also, a resistance value of the inter-layer contact/via  113  may be compared to a predetermined threshold value, and whether an electrical short occurs may be determined. 
     The identification key provided by the identification key generation apparatus  100  may desirably have time invariance, that is, the identification key may be invariant over time. For example, a plurality of inter-layer contacts/vias  113  intentionally designed to have randomness may have various resistance value distributions in a probabilistic manner. When an inter-layer contact/via  113  is manufactured, a connection state (for example, a resistance value, or a binary value digitized by comparing the resistance value to a threshold value) of the inter-layer contact/via  113  may remain unchanged, that is, invariant over time. 
     However, due to a variety of causes, for example, an influence of naturally occurring noise, an influence of an environment, such as a temperature or humidity, and/or aging of a circuit over time, a resistance value between a first node and a second node may slightly change. The above change may be a negative factor in terms of time invariance. In other words, since resistance values slightly change due to aging of elements or an environmental change, it may be easily understood that a digitized result value of a corresponding element may change when a resistance value that does not exceed a threshold value exceeds the threshold value or when a resistance value exceeding the threshold value does not exceed the threshold value. Also, even though a physical value does not change, an error of a “measurement” is an inevitable measurement phenomenon, which also functions as a negative factor in terms of the above-described time invariance. Thus, embodiments provide solutions to remove the time invariance. 
     To solve the above problem of time invariance, the discriminator  120  may discriminate, as a first group (that is, a unused group or an invalid group), a resistance of the inter-layer contact/via  113  in a resistance value range in which time invariance is expected not to be guaranteed. The reader  130  may provide an identification key of a physically unclonable function (PUF) in a form of a digital value based on a resistance of the inter-layer contact/via  113  that does not belong to the first group among binary values provided by the PUF. 
     For example, the identification key generation apparatus  100  may record information used to identify a resistor discriminated as a resistor included in the first group by the discriminator  120  in the memory (not shown), using the controller. In this example, the information stored in the memory may be an address of the resistor included in the first group. A resistor corresponding to an address stored in the memory may be recognized to have time variance, and may be excluded so as not to be used during providing of the identification key. Thus, the identification key generation apparatus  100  may increase reliability of a finally provided identification key by excluding a resistor of the first group with time invariance expected not to be guaranteed, when the identification key is read from the reading unit  130 . 
       FIGS. 2 and 3  are diagrams illustrating a characteristic of a PUF of a via of an identification key generation apparatus according to an embodiment. As described above, a plurality of vias designed to have randomness may have various resistance value distributions in a probabilistic manner based on, for example, a size of a via hole formed in the semiconductor process, and the like. Accordingly, the plurality of vias may be modeled as resistors  210 ,  220 ,  230  and  240  of  FIG. 2 . 
     The resistors  210 ,  220 ,  230  and  240  may have values of R a , R b , R c  and R d , respectively. For example, when R a &lt;R b &lt;R e &lt;R d , and R b &lt;R th &lt;R c  in which R th  denotes a threshold value are satisfied, the resistors  210  and  220  may be determined to be shorted, and the resistors  230  and  240  may be determined to be open. In this example, the resistors  210  and  240  may be expected to have time invariance due to a relatively great difference between R th  and each of R a  and R d . However, due to a relatively small difference between R th  and each of R b  and R c , the resistors  220  and  230  may have a high possibility of an occurrence of a time variance problem based on a condition, for example, noise, during reading of an identification key. 
     As a result, when the resistors  220  and  230  are used together to provide an identification key, reliability of a finally provided identification key may decrease. Thus, the resistors  220  and  230  with time invariance expected not to be guaranteed may desirably be excluded from a generation of an identification key. 
       FIG. 4  is a diagram illustrating a process of discriminating a resistance of an inter-layer contact or a via in an identification key generation apparatus according to an embodiment. The identification key generation apparatus may discriminate and select, in advance, a resistance with time invariance expected not to be guaranteed, and may store an address value corresponding to the resistance in a separate memory device. 
     Since data stored in the memory device is an address of a resistor recognized to have time variance, the data is not information requiring security. Unlike the above-described embodiment, it is possible to implement a method of storing an address of a resistor with time invariance expected to be guaranteed in a memory device. 
     A first threshold value R th.min  and a second threshold value R th.max  for a determination of reliability may be selected. When a third threshold value R th.nor  is used as a criterion to read a digital value of “0” or “1” to be used for a generation of an identification key from each resistance, the third threshold value R th.nor  may be greater than the first threshold value R th.min  and less than the second threshold value R th.max . 
     The first threshold value R th.min  and the second threshold value R th.max  may be threshold values to discriminate a resistance with low reliability, and may be selected as values obtained by applying a constant margin to a boundary value between R a  and R b  or a boundary value between R c  and R d  to increase reliability. In an example, a value of a target resistance to be discriminated is denoted by R via . In this example, when R via &lt;R th.min  is satisfied, the target resistance may be read as “short” with high reliability. When R via &gt;R th.max  is satisfied, the target resistance may be read as “open” with high reliability. However, when R th.min &lt;R via &lt;R th.max  is satisfied, the target resistance may be discriminated as a resistance with low reliability and excluded from a generation of an identification key. 
     In an example, a relationship between R via , and R th.min , R th.nor  and R th.max  may be expressed as shown in Table 1 below. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 R via   
                 R th.min (=10k) 
                 R th.nor (=100k) 
                 R th.max (=1M) 
               
               
                   
               
             
            
               
                 R via  &lt; 10k 
                 Short 
                 Short 
                 Short 
               
               
                 R via  = 10k 
                 Open/short 
                 Short 
                 Short 
               
               
                 10k &lt; R via  &lt; 100k 
                 Open 
                 Short 
                 Short 
               
               
                 R via  = 100k 
                 Open 
                 Open/short 
                 Short 
               
               
                 100k &lt; R via  &lt; 1M 
                 Open 
                 Open 
                 Short 
               
               
                 R via  = 1M 
                 Open 
                 Open 
                 Open/short 
               
               
                 R via  &gt; 1M 
                 Open 
                 Open 
                 Open 
               
               
                   
               
            
           
         
       
     
     As shown in Table 1, R th.min =10 k, R th.nor =100 k, and R th.max =1M are selected. For example, a discriminator may include three discrimination elements respectively corresponding to the above threshold values to compare Rvia and each of the threshold values. Each of the discrimination elements may include a transistor or a resistor. 
     In an example of R via &lt;10 k, discrimination results may be “short” in all the three discrimination elements. In an example of R via =10 k, a discrimination result may be “open” or “short in an R th.min  discrimination element, due to a factor such as noise, and the like. In this example, when the discrimination result is “short”, a resistor may be stably shorted in the same manner as an example of R th.min &lt;10 k. When the discrimination result is “open”, the resistor may be shorted with low reliability. In an example of 10 k&lt;R via &lt;100 k, a discrimination result may be “open” in an R th.min  discrimination element, and discrimination results may be “short” in the other discrimination elements. In an example of R via =100 k, a discrimination result may be “open” or “short” in an R th.nor  discrimination element due to a factor such as noise, and the like. In this example, the discrimination result of “short” may be the same as the example of 10 k&lt;R via &lt;100 k, and the discrimination result of “open” may be the same as an example of 100k&lt;R via &lt;1M. In the example of 100 k&lt;R via &lt;1M, a discrimination result may be “short” in an R th.max  discrimination element, and discrimination results may be “open” in the other discrimination elements. In an example of R via =1M, a discrimination result may be “open” or “short” in an R th.max  discrimination element due to noise, and the like. In this example, the discrimination result of “short” may be the same as the example of 100 k&lt;R via &lt;1M, and the discrimination result of “open” may be the same as an example of R via &gt;1M. In the example of R via &gt;1M, discrimination results 3 may be “open” in all the three discrimination elements. 
       FIGS. 5A and 5B  are diagrams illustrating a discriminator of an identification key generation apparatus according to an embodiment. 
     In an embodiment, the discriminator may include a first transistor  501 , a second transistor  502 , a third transistor  503 , and a selection transistor  505 .  FIG. 5A  also illustrates a via  504  that provides an identification key. 
     The first transistor  501 , the second transistor  502  and the third transistor  503  may be configured to compare a reference resistance value R via  to R th.min , R th.nor  and R th.max , respectively. 
     For example, when the first transistor  501  is selected, a relationship between R via  and V x  may be formed as indicated by reference numeral  506  of  FIG. 5B . In other words, when R via  is equal to R th.min , “V x =V th ” may be satisfied. Based on the above configuration, R via  and R th.min  may be compared using the first transistor  501 . 
     When the second transistor  502  is selected, the relationship between R via  and V x  may be formed as indicated by reference numeral  507  of  FIG. 5B . In other words, when R via  is equal to R th.nor , “V x =V th ” may be satisfied. Based on the above configuration, R via  and R th.nor  may be compared using the second transistor  502 . 
     When the third transistor  503  is selected, the relationship between R via  and V x  may be formed as indicated by reference numeral  508  of  FIG. 5B . In other words, when R via  is equal to Rth.max, “V x =V th ” may be satisfied. Based on the above configuration, R via  and R th.max  may be compared using the third transistor  503 . 
       FIGS. 6A through 6C  are diagrams illustrating a reader of an identification key generation apparatus according to an embodiment. 
     In an example, the reader may include an inverter  600  as shown in  FIG. 6A . The inverter  600  may be configured to have V th  as a logic threshold voltage. For example, the inverter  600  may be used as a reader for an output voltage V X  of a discriminator, as shown in  FIG. 6B . 
     Referring to  FIG. 6C , V PUF  may have a value of “0” in a portion of V x &gt;V th , and V PUF  may have a value of “1” in a portion of V x &lt;V th . In another example, V PUF  may be designed to have a value opposite to the above-described example. Thus, a value of V x  may be read by selecting the first transistor  501 , the second transistor  502  and the third transistor  503  one by one in a discrimination operation, and only the second transistor  502  may be selected in an identification key reading operation. 
     In an example of R via &lt;R th.min , values of “0”, “0”, and “0” may be read by selecting the first transistor  501 , the second transistor  502  and the third transistor  503  one by one, and a discrimination result may be “short” indicating that time invariance is guaranteed. 
     In an example of R th.min &lt;R via &lt;R th.nor , values of “1”, “0”, and “0” may be read by selecting the first transistor  501 , the second transistor  502  and the third transistor  503  one by one, and a discrimination result may be “short” indicating that time invariance is not guaranteed. 
     In an example of R th.min &lt;R via &lt;R th.nor , values of “1”, “1”, and “0” may be read by selecting the first transistor  501 , the second transistor  502  and the third transistor  503  one by one, and a discrimination result may be “open” indicating that time invariance is not guaranteed. 
     In an example of R via &gt;R th.max , values of “1”, “1”, and “1” may be read by selecting the first transistor  501 , the second transistor  502  and the third transistor  503  one by one, and a discrimination result may be “open” indicating that time invariance is guaranteed. 
       FIGS. 7 and 8  are diagrams illustrating a reader of an identification key generation apparatus according to an embodiment. For example, instead of the inverter  600  of  FIG. 6A , a logic buffer  700  of  FIG. 7  or a Schmitt trigger inverter  800  of  FIG. 8  may be used. 
     The logic buffer  700  and/or the Schmitt trigger inverter  800  may be configured to have V th  as a logic threshold voltage, and may be used as a reader for an output voltage V x  of a discriminator, as described above with reference to  FIGS. 6B and 6C . 
       FIGS. 9A and 9B  are diagrams illustrating a discriminator of an identification key generation apparatus according to an embodiment. 
     In an example, the discriminator of the identification key generation apparatus may include a pull-up resistor  910  and a selection transistor  505 . The pull-up resistor  910  may be configured to pull V x  up to VDD while a selection transistor is in an off state.  FIG. 9A  also illustrates a via  504  that provides an identification key. 
     A rate at which a pulled-up voltage is discharged based on a value of R via  after the selection transistor  505  is turned on may change due to an RC delay, and accordingly the value of R via  may be measured based on the rate, to determine whether an electrical short by a via occurs. 
     In an example, a discharge rate after the selection transistor  505  is turned on may be lower than a discharge rate corresponding to R th.max , as indicated by reference numeral  920  of  FIG. 9B , which may be determined as R via &gt;R th.max . 
     In another example, the discharge rate after the selection transistor  505  is turned on may be higher than a discharge rate corresponding to R th.max , and may be lower than a discharge rate corresponding to R th.nor , as indicated by reference numeral  930  of  FIG. 9B , which may be determined as R th.min &lt;R via &lt;R th.nor . 
     In another example, the discharge rate after the selection transistor  505  is turned on may be higher than a discharge rate corresponding to R th.nor , and may be lower than a discharge rate corresponding to R th.min , as indicated by reference numeral  940  of  FIG. 9B , which may be determined as R th.min &lt;R via &lt;R th.nor . 
     In another example, the discharge rate after the selection transistor  505  is turned on may be higher than a discharge rate corresponding to R th.min , as indicated by reference numeral  950  of  FIG. 9B , which may be determined as R via &lt;R th.min . 
       FIGS. 10A and 10B  are diagrams illustrating a reader of an identification key generation apparatus according to an embodiment. 
     In an example, the reader of the identification key generation apparatus may include a pull-up resistor R pu  and a selection transistor select. The pull-up resistor R pu  may be configured to pull V x  up to VDD while the selection transistor is in an off state.  FIG. 10A  also illustrates a via R via  that provides an identification key. 
     A rate at which a pulled-up voltage is discharged up to a threshold voltage V th  based on a value of R via  after the selection transistor is turned on may change due to an RC delay, and accordingly an identification key may be read from the value of R via  based on the rate. 
     For example, when an amount of time required to discharge the pulled-up voltage to the threshold voltage V th  is denoted by t, an identification key generator with time variance may be verified based on a first threshold time t th.min  and a second threshold time t th.max . Also, a final identification key may be read based on a third threshold time t th.nor . 
     In an example, PUF=1 may be read when t≥t th.nor  is satisfied, as indicated by reference numerals  1010  and  1020  of  FIG. 10B , and PUF=0 may be read when t≤t th.nor  is satisfied, as indicated by reference numerals  1030  and  1040  of  FIG. 10B . In another example, a read PUF may be designed to have values opposite to those of the above-described example. 
     When t th.max ≥t≥t th.nor  is satisfied, as indicated by reference numeral  1020  of  FIG. 10B , and when t th.min ≤t≤t th.nor  is satisfied, as indicated by reference numeral  1030  of  FIG. 10B , time invariance of the read R via  may be determined not to be guaranteed. The identification key generation apparatus may increase reliability of a finally provided identification key by excluding a resistor with time invariance expected not to be guaranteed when an identification key is read by the reader. 
       FIGS. 11 and 12  are diagrams illustrating a reader of an identification key generation apparatus according to an embodiment. 
     In an example, to measure an amount of time in which a pulled-up voltage is discharged to a threshold voltage V th  after a selection transistor is turned on, a reader  1120  may measure, based on a clock  1130 , a duration during which an output voltage V x  of an identification key generator  1110  is maintained to be greater than or equal to the threshold voltage V th . To this end, the reader  1120  may include a comparator  1121 , a counter  1122 , and a logic  1123 . 
     For example, the reader  1120  may compare, using the comparator  1121 , the output voltage V x  of the identification key generator  1110  to the threshold voltage V th . When V x ≥V th  is satisfied, a value of “1” may be provided to an enable signal EN of the counter  1122 . When the duration during which the output voltage V x  of the identification key generator  1110  is maintained to be greater than or equal to the threshold voltage V th  is measured based on a clock, as described above, the reader  1120  may verify, using the logic  1123 , an identification key generator with time variance by comparing an output O n  of the counter  1122  to a first threshold time t th.min  and/or a second threshold time t th.max , and may read a final identification key by comparing the output O n  to a third threshold time t th.nor . 
     In an example, PUF=1 may be read when t≥t th.nor  is satisfied, as indicated by reference numerals  1210  and  1220  of  FIG. 12 , and PUF=0 may be read when t≤t th.nor  is satisfied, as indicated by reference numerals  1230  and  1240  of  FIG. 12 . In another example, a read PUF may be designed to have values opposite to those of the above-described example. 
     When t th.max ≥t≥t th.nor  is satisfied, as indicated by reference numeral  1220  of  FIG. 12 , and when t th.min ≤t≤t th.nor  is satisfied, as indicated by reference numeral  1230  of  FIG. 12 , time invariance of the read R via  may be determined not to be guaranteed. The identification key generation apparatus may increase reliability of a finally provided identification key by excluding a resistor with time invariance expected not to be guaranteed when an identification key is read by the reader. 
     The units described herein may be implemented using hardware components, software components, and/or a combination thereof. A processing device may be implemented using one or more general-purpose or special purpose computers, such as, for example, a processor, a controller and an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor or any other device capable of responding to and executing instructions in a defined manner. The processing device may run an operating system (OS) and one or more software applications that run on the OS. The processing device also may access, store, manipulate, process, and create data in response to execution of the software. For purpose of simplicity, the description of a processing device is used as singular, however, one skilled in the art will appreciated that a processing device may include multiple processing elements and multiple types of processing elements. For example, a processing device may include multiple processors or a processor and a controller. In addition, different processing configurations are possible, such a parallel processors. 
     The software may include a computer program, a piece of code, an instruction, or some combination thereof, to independently or collectively instruct or configure the processing device to operate as desired. Software and data may be embodied permanently or temporarily in any type of machine, component, physical or virtual equipment, computer storage medium or device, or in a propagated signal wave capable of providing instructions or data to or being interpreted by the processing device. The software also may be distributed over network coupled computer systems so that the software is stored and executed in a distributed fashion. The software and data may be stored by one or more non-transitory computer readable recording mediums. 
     The method according to the above-described embodiments may be recorded in non-transitory computer-readable media including program instructions to implement various operations embodied by a computer. The media may also include, alone or in combination with the program instructions, data files, data structures, and the like. The program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of non-transitory computer-readable media include magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD ROM disks and DVDs; magneto-optical media such as optical discs; and hardware devices that are specially configured to store and perform program instructions, such as read-only memory (ROM), random access memory (RAM), flash memory, and the like. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter. The described hardware devices may be configured to act as one or more software modules in order to perform the operations of the above-described embodiments of the present invention, or vice versa. 
     While this disclosure includes specific examples, it will be apparent to one of ordinary skill in the art that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.