Patent Publication Number: US-11656267-B2

Title: Transistor characterization

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to French patent application number 2003211, filed Mar. 31, 2020, the contents of which is incorporated herein by reference in its entirety. 
     TECHNICAL BACKGROUND 
     The present disclosure generally concerns electronic devices and, more particularly, field-effect transistor characterization methods. 
     PRIOR ART 
     To characterize a field-effect transistor, the effective mobility of the majority charge carriers (electrons or holes) in its conduction channel may in particular be estimated. The effective mobility values obtained by usual characterization methods are however often erroneous, for example, due to a trapping of charges during the measurement. This alters the transistor characterization. 
     SUMMARY 
     There is a need to improve transistor characterization devices and methods. 
     An embodiment overcomes all or part of the disadvantages of known transistor characterization devices and methods. 
     An embodiment provides a method of characterizing a field-effect transistor, comprising: 
     a step of application, to the gate of the transistor, of a single ramp of the gate voltage; 
     a step of measurement of a drain current and of a gate capacitance of the transistor during the application of the ramp of the gate voltage; and 
     a step of interpretation both of variations of the gate capacitance and of variations of the drain current of the transistor. 
     According to an embodiment, the ramp is applied for a time period in the range from 1 μs to 20 μs, preferably from 1 μs to 5 μs. 
     According to an embodiment, the ramp is a straight line having a substantially constant slope. 
     According to an embodiment, the slope of the ramp is, in absolute value, between 0.1 V/μs and 10 V/μs, preferably between 0.5 V/μs and 1.5 V/μs. 
     According to an embodiment, the drain of the transistor is submitted, during the application of the ramp, to a drain voltage in the range from 1 mV to 500 mV, preferably from 50 mV to 150 mV, with respect to the transistor source. 
     According to an embodiment, the source and a substrate of the transistor are, during the application of the ramp, taken to a reference potential, preferably the ground. 
     According to an embodiment, the variations of the gate capacitance of the transistor are deduced from variations of the displacement current in the transistor during the application of the ramp. 
     According to an embodiment, a value of the effective mobility of the carriers in the transistor is calculated based on: 
     the gate length of the transistor; 
     the gate width of the transistor; 
     the drain current of the transistor; 
     the drain voltage of the transistor; and 
     the integral of the gate capacitance of the transistor with respect to the gate voltage during the application of the ramp. 
     According to an embodiment, a gate leakage current of the transistor is deduced from a measurement of the source current and from a measurement of the drain current during the application of the ramp. 
     According to an embodiment, an offset of the threshold voltage of the transistor is estimated during first successive phases of application of the ramp of the gate voltage, separated by second phases of application of a non-zero constant voltage to the gate of the transistor. 
     An embodiment provides an electronic device adapted to implementing the method such as described, the device comprising: 
     a first pulsed current-vs.-voltage characteristic measurement system which may be coupled, preferably connected, to the gate of the transistor; 
     a measurement acquisition system coupled to the first pulsed current-vs.-voltage characteristic measurement system; and 
     a second pulsed current-vs.-voltage characteristic measurement system which may be coupled, preferably connected, to the drain of the transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments and implementation modes in connection with the accompanying drawings, in which: 
         FIG.  1    is a partial simplified cross-section view of an example of a transistor of the type to which the described embodiments and implementation modes apply as an example; 
         FIG.  2    is an electric diagram of an example of an electronic transistor characterization device; 
         FIG.  3    is an example of a timing diagram associated with an example of a transistor characterization method; 
         FIG.  4    is a partial simplified cross-section view of the transistor of  FIG.  1    during a step of the method of  FIG.  3   ; 
         FIG.  5    is a partial simplified cross-section view of the transistor of  FIG.  1    during another step of the method of  FIG.  3   ; 
         FIG.  6    is an example of a graph of variation of the source current and of the drain current of the transistor of  FIG.  1    during the implementation of the method of  FIG.  3   ; 
         FIG.  7    is an electric diagram of an embodiment of an electronic transistor characterization device; 
         FIG.  8    is an example of a timing diagram associated with an implementation mode of a transistor characterization method; 
         FIG.  9    is an electric diagram of an embodiment of another electronic transistor characterization device; 
         FIG.  10    is a partial simplified cross-section view of an example of a transistor in an operating mode; 
         FIG.  11    is a partial simplified cross-section view of the transistor of  FIG.  10    in another operating mode; and 
         FIG.  12    is an example of a timing diagram associated with an implementation mode of a method of estimating a drift in the threshold voltage of a transistor. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Like features have been designated by like references in the various figures. In particular, the structural and/or functional elements common to the different embodiments and implementation modes may be designated with the same reference numerals and may have identical structural, dimensional, and material properties. 
     For clarity, only those steps and elements which are useful to the understanding of the described embodiments and implementation modes have been shown and will be detailed. 
     Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements. 
     In the following disclosure, unless otherwise specified, when reference is made to absolute positional qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or to relative positional qualifiers, such as the terms “above”, “below”, “upper”, “lower”, etc., or to qualifiers of orientation, such as “horizontal”, “vertical”, etc., reference is made to the orientation shown in the figures. 
     Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%. 
       FIG.  1    is a partial simplified cross-section view of an example of a transistor  100  of the type to which the described embodiments and implementation modes apply as an example. 
     In the shown example, transistor  100  is a field-effect transistor. Transistor  100  is for example a metal-oxide-semiconductor field-effect transistor, more commonly called MOS transistor. Transistor  100  is for example formed inside and on top of a semiconductor substrate  102 , for example, a doped silicon wafer or piece of wafer of a first conductivity type. 
     As illustrated in  FIG.  1   , transistor  100  comprises a source region  104 S and a drain region  104 D. In the shown example, source and drain regions  104 S and  104 D are separate, and extend vertically from the upper surface of substrate  102 . Source and drain regions  104 S and  104 D are for example each made of doped silicon of a second conductivity type, different from the first conductivity type. 
     Transistor  100  further comprises a gate region  104 G. In the shown example, gate region  104 G is located on top of and in contact with the upper surface of substrate  102 . At the surface of substrate  102 , gate region  104 G extends horizontally above a portion of substrate  102  laterally bordered with source and drain regions  104 S and  104 D. In  FIG.  1   , gate region  104 G extends above source and drain regions  104 S and  104 D. In the shown example, gate region  104 G partially coats the respective upper surfaces of source region  104 S and of drain region  104 D. Region  104 G is typically made of an electrically-insulating material, for example, an oxide. 
     In the shown example, a source electrode  106 S, a gate electrode  106 G, and a drain electrode  106 D are respectively formed on top of and in contact with the source region  104 S, the gate region  104 G, and the drain region  104 D of transistor  100 . Each of these electrodes  106 S,  106 G,  106 D for example partly covers the free upper surface of the region  104 S,  104 G,  104 D with which it is associated. As an example, electrodes  106 S,  106 G, and  106 D respectively form the source, gate, and drain terminals of transistor  100 . Source, gate, and drain electrodes  106 S,  106 G, and  106 D are for example made of an electrically-conductive material. 
     In a case where substrate  102  is p-type doped and where source and drain regions  104 S and  104 D are each n-type doped, transistor  100  is called n-channel transistor or nMOS transistor. The majority charge carriers are electrons in this case. If a voltage V GS  greater than a threshold voltage V TH  is applied between the gate and source electrodes  106 G and  106 S of transistor  100 , electrons may flow within the n channel formed between source and drain regions  104 S and  104 D. 
     In another case where substrate  102  is n-type doped and where the source and drain regions  104 S and  104 D are each p-type doped, transistor  100  is called p-channel transistor, or pMOS transistor. The majority charge carriers are holes in this case. If a voltage V GS  smaller than a threshold voltage V TH  is applied between the gate and source electrodes  106 G and  106 S of transistor  100 , holes may flow within the p channel formed between source and drain regions  104 S and  104 D. 
     When a transistor is desired to be characterized, for example, transistor  100 , the effective mobility, noted μ eff , of the majority charge carriers of its conduction channel, may in particular be estimated. In other words, one may estimate the effective mobility of the electrons, in the case of an nMOS-type transistor, or of the holes, in the case of a pMOS-type transistor. The effective mobility μ eff  is for example representative of the electric performance and of the reliability of transistor  100 . 
     To estimate the effective mobility μ eff  of the carriers of a transistor such as transistor  100 , measurements of drain current I D  and measurements of gate capacitance C may be performed according to a variable potential V G  imposed on its gate. These two categories of measurements are respectively designated with the terms “I D (V G ) characteristics” and “C(V G ) characteristics” in the following description. 
       FIG.  2    is an electric diagram of an example of an electronic transistor characterization device  200 . Device  200  may in particular enable to obtain the characteristics I D (V G ) and C(V G ) of a transistor, for example, the transistor  100  of  FIG.  1   . In the example of  FIG.  2   , it is considered that transistor  100  is a pMOS-type transistor having an n-type substrate  102  and having source and drain regions  104 S and  104 D which are each heavily p-type doped (p+). 
     In the shown example, device  200  comprises a signal generator  202 , for example, a pulse generator. An output of signal generator  202  is coupled or connected to the gate of transistor  100 , that is, to gate electrode  106 G (not shown), via two cables  204 - 1  and  204 - 2  having a tee connector  206  interposed therebetween. 
     The output of generator  202  is further coupled or connected to an input (Ch 1 ) of an acquisition and/or recording electronic device  208  (OSC), for example, an oscilloscope, via cable  204 - 1 , tee  206 , and another cable  204 - 3 . More particularly, in  FIG.  2   , an end of cable  204 - 3  is connected to tee  206 , the other end of cable  204 - 3  being connected to input Ch 1  of oscilloscope  208 . 
     In the shown example, the drain of transistor  100 , that is, drain electrode  106 D (not shown), is connected to an inverting input (−) of an operational amplified  210 D via another cable  204 - 4 . The non-inverting input (+) of amplifier  210 D is taken to a drain potential node V D . At the output of amplifier  210 D, a voltage V(I D ) which is an image of the drain current I D  of transistor  100 , for example, proportional to current I D , is obtained. In the shown example, the output of amplifier  210 D is connected to another input (Ch 3 ) of oscilloscope  208  via another cable  204 - 5 . In  FIG.  2   , a resistor (R 1 ) is connected between the inverting input and the output of amplifier  210 D. 
     In the shown example, the source of transistor  100 , that is, source electrode  106 S (not shown in  FIG.  2   ), is connected to an inverting input (−) of another operational amplifier  210 S via another cable  204 - 6 . The non-inverting input (+) of amplifier  210 S is taken to a reference potential, for example, the ground. At the output of amplifier  210 S, a voltage V(I S ) which is an image of a source current I S  of transistor  100 , for example, proportional to current I S , is obtained. In the shown example, the output of amplifier  210 S is connected to another input (Ch 4 ) of oscilloscope  208  via another cable  204 - 7 . In  FIG.  2   , another resistor (R 2 ) is connected between the inverting input and the output of amplifier  210 S. 
     In  FIG.  2   , the substrate  102  of transistor  100  is taken to the reference potential. In the shown example, the surface of substrate  102  opposite to source, gate, and drain regions  104 S,  104 G, and  104 D is set to ground via another cable  204 - 8 . 
     Cables  204 - 1 ,  204 - 2 ,  204 - 3 ,  204 - 4 ,  204 - 5 ,  204 - 6 ,  204 - 7 , and  204 - 8  are for example coaxial cables, having a grounded jacket. In the shown example, the jacket of each cable  204 - 3 ,  204 - 5 ,  204 - 7  is connected to a ground terminal (GND) of oscilloscope  208 . As an example, the signal generator  202  and the oscilloscope  208  of circuit  200  may respectively have an output impedance and an input impedance equal to approximately 50Ω. 
     The operation of device  200  is discussed in further detail in relation with  FIGS.  3  to  6    hereabove. 
       FIG.  3    is an example of a timing diagram associated with an example of a transistor characterization method.  FIG.  3    for example illustrates the variation, over time (t), of the voltage V G  imposed on gate electrode  106 G ( FIG.  1   ) of transistor  100  by the generator  202  ( FIG.  2   ) of device  200 . 
     In the shown example, gate voltage V G  first follows a first decreasing linear ramp  300 - 1 , in other words a straight line having a negative slope. Voltage V G  then follows a second increasing linear ramp  300 - 2 , in other words another line having a positive slope. In the example illustrated in  FIG.  3   , gate voltage V G  decreases from 0 V to −2 V between a time t 0  and a time t 1 , subsequent to time t 0 . Gate voltage V G  then increases from −2 V to 0 V between time t 1  and a time t 2 , subsequent to time t 1 . In  FIG.  3   , times t 0  and t 1  are separated by a time period D 1 , while times t 1  and t 2  are separated by another time period D 2 . As an example, time periods D 1  and D 2  are each in the order of a few microseconds or tens of microseconds. 
     In practice, the transition between ramp  300 - 1  of negative slope and ramp  300 - 2  of positive slope may occur via a plateau. Gate voltage V G  may for example be maintained at a constant value of approximately −2 V for a few tenths or hundredths of microseconds between ramps  300 - 1  and  300 - 2 . 
     As an example, during ramps  300 - 1  and  300 - 2 , the bias potential V D  ( FIG.  2   ) of the drain of transistor  100  is maintained at a substantially constant value. Potential V D  is for example maintained equal to approximately minus one hundred millivolts (−100 mV) between times t 0  and t 2 . 
       FIG.  4    is a partial simplified cross-section view of the transistor  100  of  FIG.  1    during a step of a method of  FIG.  3   .  FIG.  4    symbolizes, in particular, electric currents which flow through transistor  100  during the application of the decreasing ramp  300 - 1  ( FIG.  3   ) of gate voltage V G . 
     In the following description, I D   ON  and I S   ON  designate the currents respectively measured from the drain electrode  106 D and from the source electrode  106 S of transistor  100  ( FIG.  1   ) during ramp  300 - 1  of negative slope. 
     During the application of ramp  300 - 1 , drain current I D   ON  is equal, in absolute value, to a channel current, noted I ch , minus a gate leakage current on the drain side, noted I G_D , and minus a displacement current on the drain side, noted I dis_D . In other words, current I D   ON  verifies the following relation: 
     
       
         
           
             
               
                 
                   
                     
                       
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                         I 
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                     ⁢ 
                     
                       I 
                       ch 
                     
                   
                   - 
                   
                     I 
                     G_D 
                   
                   - 
                   
                     I 
                     dis_D 
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     1 
                   
                   ] 
                 
               
             
           
         
       
     
     Similarly, during the application of ramp  300 - 1 , source current I S   ON  is equal, in absolute value, to the sum of a gate leakage current on the source side, noted I G_S , of a displacement current on the source side, noted I dis_S , and of channel current I ch . In other words, current I S   ON  verifies the following relation: 
     
       
         
           
             
               
                 
                   
                     
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                       I 
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                   = 
                   
                     
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                       ch 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     2 
                   
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     During ramp  300 - 1 , the displacement current on the drain side is due to a charge of a capacitive element between the gate electrode  106 G and the drain electrode  106 D of transistor  100  ( FIG.  1   ). Similarly, during ramp  300 - 1 , the displacement current I dis_S  on the source side is due to a charge of a capacitive element located between the gate electrode  106 G and the source electrode  106 S of transistor  100  ( FIG.  1   ). During ramp  300 - 1 , current I dis_D  is oriented from drain region  104 D to gate region  104 G, and current I dis_S  is oriented from source region  104 S to gate region  104 G. 
     The gate leakage current I G_D  on the drain side corresponds to an unwanted current crossing gate region  104 G on the side of drain region  104 D. Similarly, the gate leakage current I G_S  on the source side corresponds to an unwanted current crossing gate region  104 G on the side of source region  104 S. During ramp  300 - 1 , current I G_D  is oriented from drain region  104 D to gate region  104 G, and current I G_S  is oriented from source region  104 S to gate region  104 G. 
     During ramp  300 - 1 , channel current I ch  is oriented from source region  104 S to drain region  104 D. 
       FIG.  5    is a partial simplified cross-section view of the transistor  100  of  FIG.  1    during another step of the method of  FIG.  3   .  FIG.  5    symbolizes, in particular, electric currents which flow through transistors  100  during the application of the increasing ramp  300 - 2  ( FIG.  3   ) of gate voltage V G . 
     In the rest of the description, note I D   OFF  and I S   OFF  the currents respectively measured from the drain electrode  106 D and from the source electrode  106 S of transistor  100  ( FIG.  1   ) during ramp  300 - 2  of positive slope. 
     During the application of ramp  300 - 2 , drain current I D   OFF  is equal, in absolute value, to the sum of the displacement current I dis_D  on the drain side and of the channel current I ch , minus the gate leakage current I G_D  on the drain side. In other words, current I D   OFF  verifies the following relation: 
     
       
         
           
             
               
                 
                   
                     
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                       I 
                       D 
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                   = 
                   
                     
                       I 
                       dis_D 
                     
                     + 
                     
                       I 
                       ch 
                     
                     - 
                     
                       I 
                       G_D 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     3 
                   
                   ] 
                 
               
             
           
         
       
     
     Similarly, during the application of ramp  300 - 2 , source current I S   OFF  is equal, in absolute value, to the sum of the gate leakage current I G_S  on the source side and of the channel current I ch , minus the displacement current I dis_S  on the source side. In other words, current I S   OFF  verifies the following relation: 
     
       
         
           
             
               
                 
                   
                     
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                       I 
                       S 
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                   = 
                   
                     
                       I 
                       G_S 
                     
                     - 
                     
                       I 
                       dis_S 
                     
                     + 
                     
                       I 
                       ch 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     4 
                   
                   ] 
                 
               
             
           
         
       
     
     During ramp  300 - 2 , the displacement current I dis_D  on the drain side is due to a discharge of the capacitive element between the gate electrode  106 G and the drain electrode  106 D of transistor  100  ( FIG.  1   ). Similarly, during ramp  300 - 2 , the displacement current I dis_S  on the source side is due to a discharge of the capacitive element between the gate electrode  106 G and the source electrode  106 S of transistor  100  ( FIG.  1   ). During ramp  300 - 2 , current I dis_D  is oriented from gate region  104 G to drain region  104 D, and current I dis_S  is oriented from gate region  104 G to source region  104 S. 
     During ramp  300 - 2 , the leakage current I G_D  on the drain side, the leakage current I G_S  on the source side, and the channel current I ch  are oriented in the same way as during ramp  300 - 1 . 
     In the example of the method discussed hereabove in relation with  FIGS.  3  to  5   , the currents I D   ON  and I S   ON  measured during ramp  300 - 1  and the currents I D   OFF  and I S   OFF  measured during ramp  300 - 2  enable to obtain drain current I D  by applying the following formula: 
     
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     
                       
                         
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                       + 
                       
                         
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                       + 
                       
                         
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                       + 
                       
                         
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                     4 
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     5 
                   
                   ] 
                 
               
             
           
         
       
     
     Based on the previous formula, the characteristic I D (V G ) of transistor  100  can be deduced. 
     Further, in the example of the method discussed hereabove in relation with  FIGS.  3  to  5   , the currents I D   ON  and I S   ON  measured during ramp  300 - 1  and the currents I D   OFF  and I S   OFF  measured during ramp  300 - 2  enable to obtain a gate leakage current, noted IG, by applying the following formula: 
     
       
         
           
             
               
                 
                   
                     I 
                     G 
                   
                   = 
                   
                     
                       
                         
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                       + 
                       
                         
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                       - 
                       
                         
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                     2 
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     6 
                   
                   ] 
                 
               
             
           
         
       
     
     Based on the above equations [Math 1] to [Math 4], a general displacement current noted I dis , can be deduced. Current I dis  verifies the following relation: 
     
       
         
           
             
               
                 
                   
                     I 
                     dis 
                   
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                     2 
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     7 
                   
                   ] 
                 
               
             
           
         
       
     
     Starting from current I dis , the characteristic C(V G ) of transistor  100  can be deduced by applying the following formula: 
     
       
         
           
             
               
                 
                   C 
                   = 
                   
                     
                       I 
                       dis 
                     
                     
                       
                         dV 
                         c 
                       
                       dt 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     8 
                   
                   ] 
                 
               
             
           
         
       
     
     Assuming that transistor  100  has a gate length L and a gate width W, the effective mobility μ eff  of transistor  100  can be calculated by applying the following relation: 
     
       
         
           
             
               
                 
                   
                     μ 
                     eff 
                   
                   = 
                   
                     
                       L 
                       W 
                     
                     · 
                     
                       
                         I 
                         D 
                       
                       
                         
                           Q 
                           i 
                         
                         ⁢ 
                         
                           V 
                           D 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     9 
                   
                   ] 
                 
               
             
           
         
       
     
     In relation [Math 9], Q i  represents the density of mobile charges in the channel of transistor  100 . Density Q i  corresponds to the integral of characteristic C(V G ): 
     
       
         
           
             
               
                 
                   
                     
                       Q 
                         
                     
                     i 
                   
                   = 
                   
                     
                       ∫ 
                       
                         + 
                         ∞ 
                       
                       
                         V 
                         G 
                       
                     
                     
                       CdV 
                       G 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                         
                     10 
                   
                   ] 
                 
               
             
           
         
       
     
       FIG.  6    is an example of a graph of the variation of the source current I S  (in microamperes) and of the drain current I D  (in microamperes) of the transistor  100  of  FIG.  1    according to gate potential V G  (in volts) during the implementation of the method of  FIG.  3   . In particular,  FIG.  6    illustrates an example of the variation of current I D   ON  (curve  600 - 1 ) and of current I S   ON  (curve  600 - 2 ) during ramp  300 - 1 , as well as of current I D   OFF  (curve  600 - 3 ), and of current I S   OFF  (curve  600 - 4 ) during ramp  300 - 2 . 
     In the shown example, curves  600 - 1  and  600 - 4  are almost superimposed and curves  600 - 2  and  600 - 3  are almost superimposed. As illustrated in  FIG.  6   , displacement current I dis  is in this case substantially equal, for a given gate potential V G , for example, −2 V, to the interval between curves  600 - 2  and  600 - 4  or to the interval between curves  600 - 3  and  600 - 1 . In other words, in the shown example where I D   ON ≈I S   OFF  and where I D   OFF ≈I S   ON , relation [Math 7] may be simplified as follows: 
     
       
         
           
             
               
                 
                   
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     A disadvantage of the characterization method discussed hereabove in relation with  FIGS.  3  to  6    lies in the fact that, as in the example illustrated in  FIG.  6   , curves  600 - 1  and  600 - 4  are often very close to curves  600 - 2  and  600 - 3 . This generally does not enable to accurately estimate the value of displacement current I dis , the transistor characteristic C(V G ) is thus altered. 
     Another disadvantage of the characterization method discussed hereabove in relation with  FIGS.  3  to  6    lies in the fact that the estimation of displacement current I dis  requires the application of two ramps  300 - 1  and  300 - 2  having opposite slopes. The measurements performed during ramp  300 - 2  are for example likely to be disturbed by trap states, which may for example be activated during the application of ramp  300 - 1 . This may alter the estimate of current I dis  and adversely affect the accuracy of the characteristic C(V G ) obtained at the end of the two ramps  300 - 1  and  300 - 2 . 
     What has been described hereabove in relation with an example of a pMOS-type transistor also applies to other field-effect transistors, for example, nMOS-type transistors. 
       FIG.  7    is an electric diagram of an embodiment of an electronic transistor characterization device  700 , for example, the transistor  100  of  FIG.  1   . In the following description, it is considered that transistor  100  is an nMOS-type transistor having its substrate  102  for example p-type doped and having its source and drain regions  104 S and  104 D for example each n-type doped. 
     Device  700  comprises a first pulsed current-vs.-voltage characteristic measurement (Pulsed IV) system  702  (PIV 1 ). As an example, system  702  is a measurement system known under trade name “Model B1350” of KEYSIGHT. System  702  is coupled, preferably connected, to the gate electrode or terminal  106 G of transistor  100 . In the shown example, system  702  is further coupled to a measurement acquisition system  704  (PC), for example, a computer. 
     In operation, system  702  is configured to submit electrode  106 G to voltage pulses V G  and to measure the resulting electric current. This current corresponds to the general displacement current I dis  as previously discussed in relation with  FIG.  5   . The voltage pulses applied to the gate of transistor  100  by system  702  for example each have a duration in the order of some ten or even some hundred nanoseconds. 
     In the shown example, the source electrode  106 S of transistor  100  is taken to a reference potential, preferably the ground (V S =0 V). Similarly, the drain electrode  106 D of transistor  100  is taken to the reference potential, preferably the ground (V D =0 V). In other words, the source and the drain of transistor  100  are both grounded. 
     Device  700  particularly enables to obtain the characteristic C(V G ) of a transistor by applying to the gate electrode  106 G a single voltage ramp V G  having a positive or negative slope. In practice, the system  702  of device  700  is for example configured to apply, to the gate electrode  106 G of transistor  100 , voltage pulses V G  having an increasing amplitude in the case of a ramp with a positive slope. 
       FIG.  8    is an example of a timing diagram associated with an implementation mode of a transistor characterization method.  FIG.  8    for example corresponds to a timing diagram of an implementation mode of a method of characterizing transistor  100  by using the device  700  of  FIG.  7   . 
     In the shown example, the gate voltage applied to the gate electrode  106 G of transistor  100  ( FIG.  7   ) follows a ramp  800  having a positive slope between a time t 0  and a time t 1 , subsequent to time t 0 . Ramp  800  is for example a straight line having a substantially constant slope. During ramp  800 , the displacement current I dis  is measured from gate electrode  106 G. This for example enables to deduce the characteristic C(V G ) of transistor  100  by applying formula [Math 8]. 
     Ramp  800  is applied for a time period (t 1 -t 0 ) in the range from 1 μs to 20 μs, preferably from 1 μs to 5 μs, for example, equal to approximately 3 μs. 
     In the shown example, ramp  800  has a slope dV G /dt between 0.1 V/μs and 10 V/μs, preferably between 0.5 V/μs and 1.5 V/μs. Ramp  800  for example has a slope dV G /dt equal to approximately 1 V/μs. The faster ramp  800 , the higher the displacement current I dis . An advantage of using a ramp  800  comprising a slope in the order of one volt per microsecond lies in the fact that this for example enables to achieve a measurement accuracy greater than that which would be obtained due to the method discussed in relation with  FIG.  6   . 
     The step of measuring the current I dis  from the gate of transistor  100  may in practice be preceded by a calibration step. The calibration step is for example carried out in a configuration where measurement points of system  702  ( FIG.  7   ) are not placed into contact with transistor  100 . This for example enables to obtain a parasitic displacement current value originating from an intrinsic capacitance of system  702 . This value may then be subtracted from the measurement of the displacement current I dis  performed by placing the measurement points of system  702  in contact with transistor  100  and by applying ramp  800  of gate voltage V G . 
     An implementation mode where the transistor is of pMOS type and where ramp  800  has a positive slope has been described in relation with  FIG.  8   . This is however not limiting. It will be within the abilities of those skilled in the art to adapt the described implementation mode to other types of field-effect transistors, particularly to an nMOS-type transistor. Further, it will be within the abilities of those skilled in the art to transpose the described embodiment to a characterization method where voltage ramp V G  is a straight line having a negative slope and a value equal, to within the sign, to the value of slope  800 . 
       FIG.  9    is an electric diagram of an embodiment of another electronic device  900  for characterizing transistors, for example, transistor  100 . The device  900  of  FIG.  9    comprises elements common with the device  700  of  FIG.  7   . These common elements will not be described again hereafter. 
     The device  900  of  FIG.  9    differs from the device  700  of  FIG.  7    mainly in that, in the case of device  900 , the drain electrode  106 D of transistor  100  is coupled, preferably connected, to a second pulsed current-vs.-voltage characteristic measurement system  902  (PIV 2 ). System  902  is for example similar to system  702 . In the shown example, system  902  is coupled to computer  704  (PC). 
     In operation, system  902  is configured to submit the drain electrode  106 D of transistor  100  to a voltage V D  in the range from 1 mV to 500 mV, preferably from 50 mV to 150 mV. System  902  is for example configured to apply a voltage equal to approximately 100 mV to the drain of transistor  100 . In operation, system  902  is further configured to measure drain current I D  from the drain electrode  106 D of transistor  100 . 
     By applying to electrode  106 G a single ramp  800  ( FIG.  8   ) of voltage V G  and by imposing on electrode  106 S a substantially constant voltage Vs, variations of the displacement current I dis  and of the drain current I D  can be measured at a time. In other words, one may, based on a single ramp, interpret both variations of the gate capacitance C and of the drain current I D  of transistor  100 . This for example enables to obtain in a single ramp  800  characteristic C(V G ) and characteristic I D (V G ) of transistor  100 . Based on characteristic C(V G ), the mobility μ eff  of the carriers in the channel of transistor  100  can in particular be deduced, for example, by applying relation [Math 9]. 
     It could be believed that the measurement of characteristic C(V G ) would be disturbed by the application of a non-zero drain voltage V D , for example, due to a modification of the potential difference between source and drain electrodes  106 S and  106 D. In practice, the inventors have however observed that the application of a voltage V D  smaller than 500 mV has a negligible influence on the obtained characteristics C(V G ). This is particularly true for transistors having a gate capacitance C greater than approximately 10 pF, for example, for transistors having a gate with a width in the order of 30 nm and a surface area in the order of 8,000 μm 2  and submitted to a ramp having a slope equal to approximately 1 V/μs. 
     In the implementation mode discussed in relation with  FIG.  9   , it is considered for simplification that the gate leakage current I G_S  on the source side and the gate leakage current I G_D  on the drain side of transistor  100  are both negligible. This may for example be explained by the fact that the gate region  104 G of transistor  100  has a thickness in the order of a few tens of nanometers. As an example, gate region  104 G is formed of a layer of alumina (Al 2 O 3 ) having a 30-nm thickness. 
     As a variant, for example, in cases where currents I G_S  and I G_D  are not negligible, a third pulsed current-vs.-voltage characteristic measurement system (not shown) may be coupled, preferably connected, to the source electrode  106 S of transistor  100 . As an example, the third system may be configured to apply a zero source voltage Vs and to measure the source current I S  during ramp  800  ( FIG.  8   ) of voltage V G . Considering for simplification that the leakage current of substrate  102  ( FIG.  1   ) is negligible, gate leakage current I G  verifies in this case the following relation: 
     
       
         
           
             
               
                 
                   
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     Although implementation modes of transistor characterization methods applied to a case where transistor  100  is of nMOS type have been described hereabove in relation with  FIGS.  7  to  9   , it will be within the abilities of those skilled in the art to transpose what has been previously discussed to other types of field-effect transistors, in particular to a case where transistor  100  is of pMOS type. 
       FIG.  10    is a partial simplified cross-section view of an example of a transistor  1000  in an operating mode.  FIG.  10    more particularly symbolizes an accumulation of electric charges in the vicinity of an interface between a substrate  1002 , inside and on top of which is formed transistor  1000 , and a gate oxide region  1004 G. 
     In the shown example, gate oxide region  1004 G has, in cross-section view, a “U” shape. Region  1004 G extends vertically from the upper surface of substrate  1002 . A gate electrode  1006 G is for example formed on top of and in contact with gate oxide region  1004 G. 
     In  FIG.  10   , region  1004 G separates two portions of a passivation layer  1008  partially covering the upper surface of substrate  1002 . In  FIG.  10   , the portions of passivation layer  1008  are symbolized by hatched areas. 
     As an example: 
     substrate  1002  is made of gallium nitride (GaN); 
     gate oxide region  1004 G is made of alumina (Al 2 O 3 ); and 
     passivation layer  1008  is made of aluminum gallium nitride (AlGaN). 
       FIG.  10    illustrates in particular a situation where a gate potential V G  greater than a threshold voltage of transistor V TH    1000  is applied to gate electrode  1006 G. In this situation, charges  1010  forming part of an electron channel  1012  formed between two portions of a two-dimensional electron gas (2DEG) are submitted to an electric field symbolized by arrows  1014  directed towards gate electrode  1006 G. This causes the trapping, in gate oxide layer  1004 G, of charges  1016  originating from electron channel  1012 . The operating mode illustrated in  FIG.  10    is called “build-up mode” due to the fact that charges, here electrons, build up in gate oxide layer  1004 G. 
       FIG.  11    is a partial simplified cross-section view of the transistor  1000  of  FIG.  10    in another operating mode.  FIG.  11    more particularly symbolizes the influence of the electric charges  1016  trapped in the gate oxide region  1004 G of transistor  1000 . 
       FIG.  11    particularly illustrates a situation subsequent to the application, to the gate electrode  1006 G of transistor  1000 , of a gate potential V G  greater than threshold voltage V TH  for a time period for example in the order of several seconds. In this situation, the charges  1016  trapped in gate oxide layer  1004 G each generate an electric field symbolized by arrows  1100 . The electric field  1100  generated by each charge  1016  tends to oppose the electric field  1014  of the charges  1010  of electron channel  1012 . 
     The presence of charges  1016  in layer  1004 G causes a phenomenon called bias temperature instability (BTI). This phenomenon particularly causes a progressive degradation of the electric performance of transistor  1000 . As an example this phenomenon may be responsible for an offset or a drift ΔV TH  of the threshold voltage V TH  of transistor  1000  over time. 
       FIG.  12    is an example of a timing diagram associated with an implementation mode of a method of estimating a drift ΔV TH  in the threshold voltage of a transistor, for example, transistor  1000  ( FIG.  10   ). 
     In the shown example, a substantially constant gate voltage V G , noted V stress , is applied between a time t 0  (t 0   a , t 0   b , t 0   c ) and a time t 1  (t 1   a , t 1   b , t 1   c ), on electrode  1006 G ( FIG.  10   ). Between successive times t 1  and t 0 , V stress  stops being applied to estimate the characteristics C(V G ) and I D (V G ) of transistor  1000 . To achieve this, ramps of gate voltage V G  for example similar to the ramp  800  described in relation with  FIG.  8    are applied. As an example, voltage V stress  is in the order of several volts, for example, equal to approximately 4 V. The time of application of voltage V stress  between two consecutive times t 0  and t 1  is, for example, in the order of several seconds. 
     The methods of estimating characteristics C(V G ) and I D (V G ) discussed hereabove in relation with  FIGS.  7  to  9    advantageously enable to limit the time separating each time t 1  from the next time t 0 . This for example limits the occurrence of a so-called recovery phenomenon, during which the charges  1016  ( FIG.  10   ) trapped in gate oxide layer  1004 G tend to return to the channel  1012  formed in substrate  1002 . The recovery phenomenon indeed alters the estimation of characteristic C(V G ), since it causes an attenuation of electric field  1100 . 
     An advantage of the characterization methods discussed hereabove in relation with  FIGS.  7  to  12    lies in the fact that they are capable of providing an estimate of the displacement current I dis  and a characteristic C(V G ) of the transistor more accurate than those which would be obtained by current characterization methods. 
     Another advantage of the characterization methods discussed hereabove in relation with  FIGS.  7  to  12    lies in the fact that the estimation of displacement current I dis  is achieved by the application of a single ramp  800 . The measurements performed during ramp  800  are particularly unlikely to be disturbed by trap states. This improves the accuracy of the estimation of current I dis  and of the characteristic C(V G ) obtained at the end of a single ramp  800 . 
     Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In particular, what is described hereabove in relation with an implementation mode where voltage ramp  800  has a positive slope can be transposed by those skilled in the art to a case where the voltage ramp applied to the transistor gate has a negative slope. 
     Finally, the practical implementation of the described embodiments and variants is within the abilities of those skilled in the art based on the functional indications given hereabove. In particular, the practical implementation of pulsed current-vs.-voltage characteristic measurement systems  702  and  902  is within the abilities of those skilled in the art.