Patent Publication Number: US-2009219768-A1

Title: Semiconductor memory device having shared bit line sense amplifier scheme and driving method thereof

Description:
FIELD OF THE INVENTION 
     The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having a shared bit line sense amplifier scheme and a driving method thereof. 
     DESCRIPTION OF RELATED ARTS 
     In most of semiconductor memory devices including DRAM, a bit line sense amplifier is used to sense a slight data signal applied on a bit line. The semiconductor memory device has a core region where a plurality of memory cells are arranged. In the core region, a memory cell array and the bit line sense amplifier array are repeatedly arranged in a column direction. That is, the memory cell arrays are arranged above and under the bit line sense amplifier. A shared bit line sense amplifier scheme is proposed which can maximize the efficiency of the bit line sense amplifier and reduce chip area. In the shared bit line sense amplifier scheme, a single bit line sense amplifier is commonly used by the upper and lower memory cell arrays. 
       FIG. 1  is a circuit diagram of a DRAM core having a shared bit line sense amplifier scheme. 
     Referring to  FIG. 1 , the bit lines sense amplifier includes two PMOS transistors connected between a pull-up voltage line RTO and bit line pair BL and BLB, and two NMOS transistors connected between a pull-down voltage line SB and bit line pair BL and BLB. 
     The bit line sense amplifier is shared by an upper cell array CELL ARRAY 0  and a lower cell array CELL ARRAY 1 . A bit line disconnection unit, a bit line equalization unit, a bit line precharge unit, and a column selection unit are arranged between the bit line sense amplifier and the memory cell array. 
     Specifically, NMOS transistors M 0  to M 4  are disposed between the bit line sense amplifier and the cell array  0  block. The NMOS transistors M 1  and M 2  connect/disconnect an upper bit line pair BLU and BLBU to the bit line sense amplifier in response to an upper bit line disconnection signal BISH. The NMOS transistors M 3  and M 4  precharge the bit line pair BL and BLB to a bit line precharge voltage VBLP (generally Vdd/2) in response to a bit line equalization signal BLEQ. The NMOS transistor M 0  equalizes the upper bit line pair BLU and BLBU in response to the bit line equalization signal BLEQ. 
     Also, NMOS transistors M 5  to M 7 , and two NMOS transistors are disposed between the bit line sense amplifier and the cell array CELL ARRARY 1 . The NMOS transistors M 5  and M 6  connect/disconnect a lower bit line pair BLD and BLBD to the bit line sense amplifier in response to a lower bit line disconnection signal BISL. The NMOS transistor M 7  equalizes the lower bit line pair BLD and BLBD in response to a bit line equalization signal BLEQ. Two NMOS transistors selectively connect the bit line pair BL and BLB to segment data bus pair SIO and SIOB in response to a column select signal CY. 
       FIG. 2  is a block diagram of a conventional bit line control circuit for generating the bit line disconnection signals BISH and BISL and the bit line equalization signal BLEQ. 
     Referring to  FIG. 2 , the conventional bit line control circuit includes a block controller  100 , a bit line disconnection signal generator  110 , and a bit line equalization signal generator  120 . The block controller  100  receives a block address signal AX to generate block selection signals BS_ 0  and BS_ 1  corresponding to the memory cell arrays. The bit line disconnection signal generator  110  generates the bit line disconnection signals BISH and BISL in response to the block selection signals BS_ 0  and BS_ 1 . The bit line equalization signal generator  120  generates the bit line equalization signal BLEQ in response to the block selection signals BS_ 0  and BS_ 1 . The block controller  100  includes a plurality of block selection signal generators corresponding to the memory cell arrays. 
     Referring again to  FIG. 1 , the NMOS transistors M 0  to M 7  are turned on in a precharge state. When an active command is applied and the cell array  0  block is selected, the block selection signals BS_ 0  and BS_ 1  become logic level HIGH and logic level LOW, respectively. 
     In combination of the block selection signals BS_ 0  and BS_ 1 , the upper bit line disconnection signal BISH maintains logic level HIGH so that the NMOS transistors M 1  and M 2  are turned on, and the lower bit line disconnection signal BISL is deactivated to logic level LOW so that the NMOS transistors M 5  and M 6  are turned off. 
     When the block selection signal BS_ 0  is activated to logic level HIGH, the bit line equalization signal BLEQ is deactivated to logic level LOW so that the NMOS transistors M 0 , M 3 , M 4  and M 7  are turned off. 
     As illustrated in  FIG. 2 , the bit line disconnection signal generator  110  and the bit line equalization signal generator  120  have to be separately provided. Because the separate signal lines have to be provided, a large number of metal lines are required. As described above, the bit line sense amplifiers are arranged in an array form, and a large number of bit line sense amplifier arrays are provided. Consequently, a chip area increases due to the bit line control circuit and the metal lines. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a semiconductor memory device having a shared bit line sense amplifier scheme and a driving method thereof, capable of preventing the increase of a chip area caused by a bit line control circuit and metal lines. 
     In accordance with an aspect of the present invention, there is provided a semiconductor memory device including: a bit line sense amplifier for amplifying data applied on a bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from a bit line pair of an upper cell array in response to an upper bit line disconnection signal; a lower bit line disconnection unit for selectively disconnecting the bit line sense amplifier from a bit line pair of a lower cell array in response to a lower bit line disconnection signal; an upper bit line equalization unit for equalizing the bit line pair of the upper cell array in response to the lower bit line disconnection signal; and a lower bit line equalization unit for equalizing the bit line pair of the lower cell array in response to the upper bit line disconnection signal. 
     In accordance with another aspect of the present invention, there is provided a method for driving a semiconductor memory device including: amplifying data applied on a bit line pair; selectively disconnecting a bit line sense amplifier from a bit line pair of an upper cell array in response to an upper bit line disconnection signal; selectively disconnecting the bit line sense amplifier from a bit line pair of a lower cell array in response to a lower bit line disconnection signal; equalizing the bit line pair of the upper cell array in response to the lower bit line disconnection signal; and equalizing the bit line pair of the lower cell array in response to the upper bit line disconnection signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a circuit diagram of a DRAM core having a shared bit line sense amplifier scheme; 
         FIG. 2  is a block diagram of a conventional bit line control circuit for generating a bit line disconnection signal and a bit line equalization signal; 
         FIG. 3  is a circuit diagram of a DRAM core in accordance with an embodiment of the present invention; 
         FIG. 4  is a circuit diagram of a bit line control circuit for generating an upper bit line disconnection signal and a lower bit line disconnection signal in  FIG. 3 ; and 
         FIGS. 5A to 5C  show a circuit diagram of a bit line equalizer of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, a semiconductor memory device having a shared bit line sense amplifier scheme and a driving method thereof in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
       FIG. 3  is a circuit diagram of a DRAM core in accordance with an embodiment of the present invention. 
     Referring to  FIG. 3 , the DRAM includes a bit line sense amplifier, an upper bit line disconnection unit  42 , a lower bit line disconnection unit  46 , an upper bit line equalization unit  40 , and a lower bit line equalization unit  48 . The bit line sense amplifier amplifies data applied on the bit line pair connected to an upper cell array CELL ARRAY 0  or a lower cell array CELL ARRARY 1 . The upper bit line disconnection unit  42  selectively disconnects the bit line sense amplifier from the bit line pair BLU and BLBU of the cell array CELL ARRAY 0  in response to an upper bit line disconnection signal BISH. The lower bit line disconnection unit  46  selectively disconnects the bit line sense amplifier from the bit line pair BLD and BLBD of the cell array CELL ARRARY 1  in response to a lower bit line disconnection signal BISL. The upper bit line equalization unit  40  equalizes the bit line pair BLU and BLBU of the cell array CELL ARRAY 0  in response to the lower bit line disconnection signal BISL. The lower bit line equalization unit  48  equalizes the bit line pair BLD and BLBD of the cell array CELL ARRARY 1  in response to the upper bit line disconnection signal BISH. 
     A column select unit  44  is disposed between the upper bit line disconnection unit  42  and the lower bit line disconnection unit  46 . The column select unit  44  selectively connects a bit line pair BL and BLB and a segment data bus pair SIO and SIOB in response to the column select signal CY. 
     The upper bit line disconnection unit  42  includes NMOS transistors M 8  and M 9  having gates receiving the upper bit line disconnection signal BISH and connects/disconnects the upper bit line pair BLU and BLBU and the bit line sense amplifier. 
     In addition, the lower bit line disconnection unit  46  includes NMOS transistors M 10  and M 11  having gates receiving the lower bit line disconnection signal BISL and connects/disconnects the lower bit line pair BLD and BLBD and the bit line sense amplifier. 
     The bit line sense amplifier includes two PMOS transistors connected between a pull-up voltage line (RTO line) and the bit line pair BL and BLB, and two NMOS transistors connected between a pull-down voltage line SB and the bit line pair BL and BLB. The column select unit  44  includes two NMOS transistors having gates receiving the column select signal CY and selectively connects the bit line pair BL and BLB and the segment data bus pair SIO and SIOB. 
       FIG. 4  is a circuit diagram of a bit line control circuit for generating the upper bit line disconnection signal and the lower bit line disconnection signal in  FIG. 3 . 
     Referring to  FIG. 4 , the bit line control circuit includes a block controller  200  and a bit line disconnection signal generator  210 . The block controller  200  receives a block address signal AX to generate block selection signals BS_ 0  and BS_ 1  corresponding to the memory cell arrays. The bit line disconnection signal generator  210  generates the bit line disconnection signals BISH and BISL in response to the block selection signals BS_ 0  and BS_ 1 . 
     Compared with the related art shown  FIG. 1 , the bit line control circuit of the present invention does not include the bit line equalization signal generator  120 . The reason for this is that the bit line equalization units  40  and  48  are controlled by the bit line disconnection signals BISH and BISL, instead of the bit line equalization signal BLEQ. 
     The block controller  200  includes a plurality of block selection signal generators corresponding to the respective memory cell arrays. 
     The bit line disconnection signal generator  210  includes an upper bit line disconnection signal generator for generating the upper bit line disconnection signal BISH in response to the lower block selection signal BS_ 1 , and a lower bit line disconnection signal generator for generating the lower bit line disconnection signal BISL in response to the upper block selection signal BS_ 0 . 
     The upper bit line disconnection signal generator includes an inverter INV 1  receiving the lower block selection signal BS_ 1  and a level shifter LS 1  for increasing an activation level of an output signal of the inverter INV 1 , and the lower bit line disconnection signal generator includes an inverter INV 3  receiving the upper block selection signal BS_ 0  and a level shifter LS 2  for increasing an activation level of an output signal of the inverter INV 3 . 
     In the level shifter LS 1 , two PMOS transistors MP 1  and MP 2  have sources connected to a high voltage terminal VPP and gates and drains cross-connected together. An NMOS transistor MN 1  has a drain connected to the drain of the PMOS transistor MP 1 , a source connected to an input terminal N 1 , and a gate receiving a power supply voltage VDD. An NMOS transistor MN 2  has a drain connected to the drain of the PMOS transistor MP 2 , a source connected to a ground terminal VSS, and a gate connected to the input terminal N 1 . An inverter INV 2  is connected to the drain of the PMOS transistor MP 2 . 
     The level shifters LS 1  and LS 2  are implemented using well-known circuits. The reason why the bit line disconnection signals BISH and BISL are generated using the level shifters LS 1  and LS 2  is that the bit line disconnection transistors are driven at the high voltage VPP higher than the power supply voltage VDD, considering the loss of threshold voltage. 
       FIGS. 5A to 5C  show a circuit diagram of the bit line equalization units  40  and  48  of  FIG. 3 , respectively. 
     Referring to  FIG. 5A , the bit line equalization units  40  and  48  include an NMOS transistor having a gate receiving a bit line disconnection signal BIS and connected between the bit line pair BL and BLB, and two NMOS transistors having gates receiving the bit line disconnection signal BIS and connected between the bit line precharge voltage VBLP (generally VBPL=Vdd/2) and the bit line pair BL and BLB. 
     Referring to  FIG. 5B , the bit line equalization units  40  and  48  include two NMOS transistors having gates receiving the bit line disconnection signal BIS and connected between the bit line precharge voltage VBLP (generally Vdd/2) and the bit line pair BL and BLB. 
     Referring to  FIG. 5C , the bit line equalization unit  40  and  48  include an MOS transistor having a gate receiving the bit line disconnection signal BIS and connected between the bit line pair BL and BLB. 
     In  FIGS. 5A and 5B , the bit line precharge voltage VBLP is applied to both the upper bit line equalization unit  40  and the lower bit line equalization unit  48 . On the contrary, in  FIG. 5(C) , the bit line precharge voltage VBLP is applied to one of the upper bit line equalization unit  40  and the lower bit line equalization unit  48 . 
     Because the upper bit line disconnection signal BISH and the lower bit line disconnection signal BISL are in logic level HIGH in the precharge state, the NMOS transistors M 8  to M 11  are turned on. All the NMOS transistors of the bit line equalization units  40  and  48  are also turned on. 
     When an active command is applied and the cell array CELL ARRAY 0  is selected, the block selection signals BS_ 0  and BS_ 1  become logic level HIGH and logic level LOW, respectively. In combination of the block selection signals BS_ 0  and BS_ 1 , the upper bit line disconnection signal BISH maintains logic level HIGH. Therefore, the NMOS transistors M 8  and M 9  of the upper bit line disconnection unit  42  and all NMOS transistors of the lower bit line equalization unit  48  are also turned on. Meanwhile, the lower bit line disconnection signal BISL is deactivated to logic level LOW, so that the NMOS transistors M 10  and M 11  of the lower bit line disconnection unit  46  and all NMOS transistors of the upper bit line equalization unit  40  are turned off. 
     In contrast, when the cell array CELL ARRARY 1  is selected, the block selection signals BS_ 0  and BS_ 1  become logic level LOW and logic level HIGH, respectively. Therefore, the lower bit line disconnection signal BISL maintains logic level HIGH. Therefore, the NMOS transistors M 10  and M 11  of the lower bit line disconnection unit  46  and all NMOS transistors of the upper bit line equalization unit  40  are also turned on. Meanwhile, the upper bit line disconnection signal BISH is deactivated to logic level LOW, so that the NMOS transistors M 8  and M 9  of the upper bit line disconnection unit  42  and all NMOS transistors of the lower bit line equalization unit  48  are turned off. 
     As described above, even if the bit line equalization unit is controlled using the bit line disconnection signals, the memory device can be operated normally. That is, an additional circuit for generating the bit line equalization signal is not needed. 
     In accordance with the present invention, the bit line control circuit can be simplified, thus reducing the memory chip area. 
     The present application contains subject matter related to Korean patent application No. 2005-90956 and 2005-133985, filed in the Korean Patent Office on Sep. 29, 2005 and Dec. 29, 2005, respectively, the entire contents of which are incorporated herein by reference. 
     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.