Patent Publication Number: US-2023154998-A1

Title: Semiconductor device and manufacturing method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional application of U.S. patent application Ser. No. 17/026,562 filed Sep. 21, 2020, now U.S. Pat. No. 11,563,102, which is a continuation application of U.S. patent application Ser. No. 15/908,348 filed Feb. 28, 2018, now U.S. Pat. No. 10,784,362, which claims priority to U.S. Provisional Patent Application 62/578,919, filed Oct. 30, 2017, the entire disclosures of each which are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The disclosure relates to semiconductor integrated circuits, and more particularly to semiconductor devices including negative capacitance field effect transistors (NC FETs). 
     BACKGROUND 
     The subthreshold swing is a feature of a transistor&#39;s current-voltage characteristic. In the subthreshold region the drain current behavior is similar to the exponentially increasing current of a forward biased diode. A plot of logarithmic drain current versus gate voltage with drain, source, and bulk voltages fixed will exhibit approximately logarithmic linear behavior in this metal-oxide-semiconductor (MOS) FET operating region. To improve the subthreshold properties, a negative capacitance field effect transistor (NC FET) using a ferroelectric material has been proposed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  shows a cross sectional view of a metal-insulator-semiconductor (MIS) FET-type NC FET and  FIG.  1 B  shows a cross sectional view of a metal-insulator-metal-insulator-semiconductor (MIMIS) FET-type NC FET. 
         FIGS.  2 A,  2 B,  2 C and  2 D  show various stages of manufacturing operations for a negative capacitance structure in accordance with an embodiment of the present disclosure. 
         FIGS.  3 A,  3 B,  3 C and  3 D  show various stages of manufacturing operations for a negative capacitance structure in accordance with an embodiment of the present disclosure.  FIGS.  3 E and  3 F  show various stages of manufacturing operations for a negative capacitance structure in accordance with another embodiment of the present disclosure. 
         FIGS.  4 A,  4 B,  4 C and  4 D  show various atomic structures of HfO 2 .  FIG.  4 E  shows X-Ray Diffraction (XRD) measurement results. 
         FIGS.  5  and  6    show electron energy loss spectroscopy (EELS) measurement results. 
         FIGS.  7 A,  7 B,  7 C and  7 D  show various stages of manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. 
         FIGS.  8 A,  8 B,  8 C and  8 D  show various stages of manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. 
         FIGS.  9 A,  9 B and  9 C  show various stages of manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. 
         FIGS.  10 A,  10 B and  10 C  show various stages of manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. 
         FIGS.  11 A,  11 B and  11 C  show various stages of manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. 
         FIGS.  12 A,  12 B and  12 C  show various stages of manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. 
         FIGS.  13 A,  13 B,  13 C and  13 D  show various stages of manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. 
         FIGS.  14 A,  14 B,  14 C and  14 D  show manufacturing operations for an NC FET in accordance with another embodiment of the present disclosure. 
         FIGS.  15 A,  15 B,  15 C and  15 D  show manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. In the accompanying drawings, some layers/features may be omitted for simplification. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” Further, in the following fabrication process, there may be one or more additional operations in/between the described operations, and the order of operations may be changed. 
     To lower subthreshold swing (S.S.) of a field effect transistor (FET), a negative-capacitance (NC) technology, such as integrating ferroelectric (FE) materials, provides a feasible solution to lower V DD  (power supply) significantly, and achieves an FET having a steep S.S. for low power operation. 
     In an NC FET, a capacitor (e.g., a ferroelectric (FE) capacitor) having a negative capacitance is connected to a gate of a MOS FET in series. The ferroelectric negative capacitor can be a separate capacitor connected by a conductive layer (e.g., wire/contact) to the gate of the MOS FET, in some embodiments. In other embodiments, one of the electrodes of the negative capacitor is a gate electrode of the MOS FET. In such a case, the negative capacitor is formed within sidewall spacers of the MOS FET. 
     In conventional devices, high-K gate materials, such as HfO 2 , are usually an amorphous layer. However, the un-doped HfO 2  is amorphous and paraelectric, which does not show a negative-capacitance effect. Ferroelectric materials having Perovskite structure, such as PZT or BaTiO 3 , have excellent FE characteristics. However, these materials still pose difficulties because formation of these materials is not fully compatible with silicon-based semiconductors, and the ferroelectric properties degrade with reducing the thickness thereof due to a size effect. 
     In the present disclosure, a doped HfO 2  layer having an orthorhombic crystal phase, which shows a ferroelectric property, and its production methods are provided. In addition, in the present disclosure, the crystal orientation of the doped HfO 2  layer is controlled to achieve a largest ferroelectric effect by controlling the doped HfO 2  intrinsic polarization to be parallel coupled with the external electric-field from a gate electrode. To control the crystal orientation, at least one of a bottom crystal structure control layer and an upper crystal structure control layer is provided. 
       FIG.  1 A  shows a cross sectional view of a cross sectional view of metal-insulator-semiconductor (MIS) FET-type NC FET, and  FIG.  1 B  shows a cross sectional view of a metal-insulator-metal-insulator-semiconductor (MIMIS) FET-type NC FET. Although  FIGS.  1 A and  1 B  show NC FETs of a planar MOS transistor structure, fin FETs and/or gate-all-around FETs can be employed. 
     As shown in  FIG.  1 A , an MIS NC FET includes a substrate  100 , a channel  101  and source and drain  102 . The source and drain  102  are appropriately doped with impurities. Further, the source and drain and the channel (active regions) are surrounded by an isolation insulating layer (not shown), such as shallow trench isolation (STI), made of, for example, silicon oxide. 
     An interfacial layer  103  is formed over the channel layer  101 , in some embodiments. The interfacial layer  103  is made of silicon oxide having thickness in a range from about 0.5 nm to about 1.5 nm in some embodiments. 
     A ferroelectric dielectric layer  105  is disposed over the interfacial layer  103 . The ferroelectric dielectric layer  105  includes HfO 2  doped with one or more elements selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr. In some embodiments, the ferroelectric dielectric layer  105  includes HfO 2  doped with Si and/or Zr. In certain embodiments, the ferroelectric dielectric  105  layer includes HfO 2  doped with Zr, such as HfZrO 2  (Hf:Zr=1:1). Further, in other embodiments, the ferroelectric dielectric  105  layer includes HfO 2  doped with Al at a concentration in a range from about 7 mol % to about 11 mol %. In the present disclosure, the ferroelectric dielectric layer  105  includes an orthorhombic crystal phase, which is (111) oriented. A (111) orientated layer means that the main surface (the surface parallel to the surface of a substrate on which the layer is formed) has a (111) crystal surface (i.e., having a normal vector parallel to a &lt;111&gt; direction). The orthorhombic crystal of the ferroelectric dielectric layer  105  is substantially single crystalline or the majority of the crystalline phases is (111) oriented crystals, in some embodiments. In other embodiments, the orthorhombic crystal of the ferroelectric dielectric layer  105  is (111) oriented polycrystalline. The orthorhombic crystal phase identification and (111) orientation identification and can be determined by X-ray diffraction (XRD) patterns. The orthorhombic crystal phase identification and (111) orientation identification of a specific crystal grain can be detected by a precession electron diffraction (PED) technique, which can detect a preferred orientation of each crystal grain and interlayer spacing of layers (d-spacing). The thickness of the ferroelectric dielectric layer  105  is in a range from about 1.0 nm to about 5 nm in some embodiments. 
     A gate electrode layer  106  is disposed over the ferroelectric dielectric layer  105 . The gate electrode layer  106  includes one or more metallic layers. In some embodiments, the gate electrode layer  106  includes a first conductive layer (a capping layer) disposed on the ferroelectric dielectric layer  105 , a second layer (a barrier layer) disposed on the first conductive layer, a third conductive layer (a work function adjustment layer) disposed on the second conductive layer, a fourth conductive layer (a glue layer) disposed on the third conductive layer and/or a fifth conductive layer (a main gate metal layer) disposed on the fourth conductive layer. 
     The capping layer includes a TiN based material, such as TiN and TiN doped with one or more additional elements. In some embodiments, the TiN layer is doped with Si. The barrier layer includes TaN in some embodiments. 
     The work function adjustment layer includes one or more layers of conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FinFET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel FinFET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer. 
     The glue layer includes Ti, TiN and/or TaN in some embodiments. The main gate metal layer includes a metal selected from a group of W, Cu, Ti, Al and Co. 
     Further, sidewall spacers  109  are formed on opposing side faces of the gate structure as shown in  FIG.  1 A . The sidewall spacers  109  include one or more layers of insulating material, such as silicon oxide, silicon nitride and silicon oxynitride. 
     In  FIG.  1 B , similar to  FIG.  1 A , a channel  101  and source and drain  102  are formed on a substrate  100 . A first gate dielectric layer  113  is disposed over the channel  101 . The first gate dielectric layer  113  includes one or more high-k dielectric layers (e.g., having a dielectric constant greater than  3 . 9 ) in some embodiments. For example, the one or more gate dielectric layers may include one or more layers of a metal oxide or a silicate of Hf, Al, Zr, combinations thereof, and multi-layers thereof. Other suitable materials include La, Mg, Ba, Ti, Pb, Zr, in the form of metal oxides, metal alloy oxides, and combinations thereof. Exemplary materials include MgO x , SiN (Si 3 N 4 ), Al 2 O 3 , La 2 O 3 , Ta 2 O 3 , Y 2 O 3 , HfO 2 , ZrO 2 , GeO 2 , Hf x Zr 1-x O 2 , Ga 2 O 3 , Gd 2 O 3 , TaSiO 2 , TiO 2 , HfSiON, YGe x O y , YSi x O y  and LaAlO 3 , and the like. In certain embodiments, HfO 2 , ZrO 2  and/or Hf x Zr 1-x O 2  is used. The formation methods of first gate dielectric layer  113  include molecular-beam deposition (MBD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like. In some embodiments, the first gate dielectric layer  113  has a thickness of about 1.0 nm to about 5.0 nm. 
     In some embodiments, an interfacial layer (not shown) may be formed over the channel  101  prior to forming the first gate dielectric layer  113 , and the first gate dielectric layer  113  is formed over the interfacial layer. 
     A first gate electrode  114  as an internal electrode is disposed on the first gate dielectric layer  113 . The first gate electrode  114  may be one or more metals, such as W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. In some embodiments, the first gate electrode  114  includes one or more of TiN, WN, TaN, and Ru. Metal alloys such as Ti—Al, Ru—Ta, Ru—Zr, Pt—Ti, Co—Ni and Ni—Ta may be used and/or metal nitrides, such as WN x , TiN x , MoN x , TaN x , and TaSi x N y  may also be used. In some embodiments, at least one of W, Ti, Ta, TaN and TiN is used as the first gate electrode  114 . In some embodiments, the first gate electrode  114  includes a work function adjustment layer. 
     A ferroelectric dielectric layer  115  is formed on the first gate electrode  114 . The ferroelectric dielectric layer  115  is substantially the same as the ferroelectric dielectric layer  105 . 
     Further, a second gate electrode  116  as an external gate is disposed on the ferroelectric dielectric layer  115 . The second gate electrode  116  may be a metal selected from a group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. The second gate electrode  116  is made of the same material as or different material from the first gate electrode  114 . Further, sidewall spacers  119  are formed on opposing side faces of the gate structure as shown in  FIG.  1 B . The sidewall spacers  119  include one or more layers of insulating material, such as silicon oxide, silicon nitride and silicon oxynitride. 
     As shown in  FIGS.  1 A and  1 B , the ferroelectric dielectric layers  105  and  115  and the first gate dielectric layer  113  have a “U-shape” in the cross section, having a thin center portion and thick side portions in the vertical direction. 
       FIGS.  2 A,  2 B,  2 C and  2 D  show various stages of manufacturing operations for a negative capacitance structure in accordance with an embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after the processes shown by  FIGS.  2 A- 2 D , and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with  FIGS.  1 A and  1 B  may be employed in the following embodiments, and detailed explanation thereof may be omitted. 
     As shown in  FIG.  2 A , an interfacial layer  20  is formed on a substrate  10 . In some embodiments, the substrate  10  is made of a suitable elemental semiconductor, such as silicon, diamond or germanium; a suitable alloy or compound semiconductor, such as Group-IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenic phosphide (GaAsP), or gallium indium phosphide (GaInP)), or the like. Further, the substrate  10  may include an epitaxial layer (epi-layer), which may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure. 
     In some embodiments, the interfacial layer  20  is a silicon oxide, which may be formed by chemical reactions. For example, a chemical silicon oxide may be formed using deionized water+ozone (DIO 3 ), NH 4 OH+H 2 O 2 +H 2 O (APM), or other methods. Other embodiments may utilize a different material or processes for the interfacial layer. In some embodiments, the interfacial layer  20  has a thickness of about 0.5 nm to about 1.5 nm. 
     Then, a dielectric layer  30  is formed over the interfacial layer  20 . The dielectric layer  30  includes HfO 2  doped with one or more elements selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr. 
     The formation methods of the dielectric layer  30  include molecular-beam deposition (MBD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like. In some embodiments, HfO 2  doped with Zr can be formed by ALD using HfCl 4  and H 2 O as a first precursor and ZrCl 4  and H 2 O as a second precursor at a temperature in a range from about 200° C. to 400° C. In a case of HfO 2  doped with Si, SiH 4 , Si 2 H 6 , and/or SiH 2 Cl 2  or other suitable silicon source gas may be used. The dielectric layer  30  as deposited is amorphous and paraelectric. The thickness of the dielectric layer  30  is in a range from about 1 nm to about 5 nm in some embodiments. 
     After the dielectric layer  30  is formed, a capping layer  40 , as an upper crystal structure control layer, is formed on the dielectric layer  30 , as shown in  FIG.  2 B . The capping layer  40  includes a TiN based material, such as TiN and TiN doped with one or more additional elements, in some embodiments. In some embodiments, the TiN layer is doped with Si. The capping layer  40  can be formed by ALD, CVD or physical vapor deposition including sputtering or any other suitable methods. The thickness of the capping layer  40  is in a range from about 1 nm to about 5 nm in some embodiments. 
     In the present disclosure, the TiN-based capping layer  40  includes crystal grains that are (111) and/or (220) oriented. The (111) and (220) orientation of the capping layer  40  can facilitate controlling the crystal orientation of the HfO 2  layer to have a (111) orientation. The TiN-based capping layer  40  can be formed by an ALD. As-deposited in one deposition step in the ALD, the TiN-based layer forms a monoatomic layer in a close-packed configuration (i.e., (111) oriented), with a high density. In some embodiments, the monoatomic layer shows (200) and/or (220) orientation with a lower density. After the annealing operation, when observed by an X-ray diffraction method, a (111) signal becomes more clear and sharper even though (200) and/or (222) are also observed. 
     In some embodiments, the TiN-based capping layer  40  can be formed by using TiCl 4  and NH 3  as precursors, with Ar as a carrier gas, at a temperature in a range from about 350° C. to about 450° C. In some embodiments, a Si doping gas, such as SiH 4 , is added. By controlling ALD conditions and an annealing temperature, it is possible to control the crystalline orientation of the TiN-based capping layer  40  to be (111) oriented. In other embodiments, TaN and/or W, which also has a controlled crystal orientation, is used as the capping layer  40 . 
     After the capping layer  40  is formed, an annealing operation is performed as shown in  FIG.  2 C . The annealing operation is performed at a temperature in a range from about 700° C. to about 1000° C. in an inert gas ambient, such as N 2 , Ar and/or He. The annealing period is in a range from about 10 sec to 1 min in some embodiments. After the annealing, a cooling operation is performed. In some embodiments, the substrate is cooled down to less than 100° C. or to room temperature (about 25° C.). The annealing operation after the capping layer  40  is formed provides driving a force for the Zr-doped HfO 2  structure transition from amorphous phase to high-temperature tetragonal phase, which is (111) oriented, and capping layer  40  provides the mechanical stress needed for the crystalline transition from the high-temperature tetragonal phase to the high-pressure ferroelectric orthorhombic phase during cooling. Due to the crystalline orientations of the capping layer  40  (i.e., (111) and (220)), the (111) oriented doped-HfO 2  layer  30  can be obtained. 
     When a transmission electron microscopy (TEM) image is taken, it was observed that the irregularity of the TiN-based capping layer coincides with the Zr-doped HfO 2  grain boundary directly above, which indicates that the polycrystalline structure of the TiN-based capping layer influences the growth direction and the orientation of the Zr-doped HfO 2  during the post annealing and cooling. 
     In some embodiments, after the capping layer  40  is formed, an amorphous silicon layer is formed on the capping layer  40 , and then the annealing operation is performed. After the annealing operation and cooling operation are performed, the amorphous silicon layer is removed. 
     After the cooling operation, a barrier layer  52  made of, for example, TaN, is formed over the capping layer  40 , as shown in  FIG.  2 D . The barrier layer  52  can be formed by ALD, 
     CVD or physical vapor deposition including sputtering or any other suitable methods. When ALD is utilized, the ALD is performed at a temperature in a range from about 300° C. to about 400° C. in some embodiments. The thickness of the barrier layer  52  is in a range from about 1 nm to about 5 nm in some embodiments. In some embodiments, the annealing operation to convert the amorphous structure to the orthorhombic structure may be performed after the barrier layer  52  is formed. 
     Further, a work function adjustment layer  54  is formed on the barrier layer  52 . In some embodiments, the work function adjustment layer  54  includes TiN for a p-type transistor and TiAl for an n-type transistor. Any other suitable metallic material can be used as the work function adjustment layer  54 . In some embodiments, a TiAl layer is also formed on a TiN work function adjustment layer for a p-type transistor. The work function adjustment layer  54  can be formed by ALD, CVD or physical vapor deposition including sputtering or any other suitable methods. When ALD is utilized, the ALD is performed at a temperature in a range from about 300° C. to about 400° C. in some embodiments. The thickness of the work function adjustment layer  54  is in a range from about 1 nm to about 5 nm in some embodiments. 
     Further, a main gate metal layer  58  is formed over the work function adjustment layer  54 . The main gate metal layer  58  includes one or more metals, such as W, Cu, Ti, Al and Co, or other suitable material. In some embodiments, when the main gate metal layer  58  is W, a glue layer  56  is formed on the work function adjustment layer  54 . In some embodiments, the glue layer  56  is Ti. As shown in  FIG.  2 D , the gate electrode  50  may include a barrier layer  52  disposed on the capping layer  40 , a work function adjustment layer  54  disposed on the barrier layer  52 , a glue layer  56  disposed on the work function adjustment layer  54  and a main gate metal layer  58 . In some embodiments, the capping layer may be considered as a part of the gate electrode  50 . 
       FIGS.  3 A- 3 F  show various stages of manufacturing operations for a negative capacitance structure in accordance with an embodiment of the present disclosure. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with  FIGS.  1 A- 2 D  may be employed in the following embodiments, and detailed explanation thereof may be omitted. In the embodiment of  FIGS.  3 A- 3 F , instead of or in addition to the crystalline capping layer  40 , a seed dielectric layer  25 , as a bottom crystal structure control layer, is utilized to control the crystalline orientation of the doped-HfO 2  layer. 
     As shown in  FIG.  3 A , after the interfacial layer  20  is formed on the substrate  10 , a seed dielectric layer  25  is formed before the dielectric layer  30  is formed. In some embodiments, the seed dielectric layer  25  includes a layer that can easily form a tetragonal or orthorhombic structure. In certain embodiments, ZrO 2  is used as the seed dielectric layer  25 . Polycrystalline ZrO 2  easily forms a tetragonal phase, when its grain size is smaller than a critical value (e.g., 30 nm). When observed by an XRD method, an as-deposited and a post-annealed ZrO 2  film show a strong orthorhombic-phase (111) signal and a strong tetragonal-phase (011) signal. Such structures of the ZrO 2  layer are beneficial for growth of an orthorhombic-phase doped HfO 2  layer. 
     In some embodiments, the ZrO 2  seed layer can be formed by ALD using ZrCl 4  and H 2 O as precursors with Ar or N 2  as a carrier gas. In other embodiments, tetrakis-(dimethylamino)zirconium (Zr[N(CH 3 ) 2 ] 4 ) with oxygen plasma together with Ar or N 2  as a carrier gas is used. The ALD is performed at a temperature in a range from about 250° C. to 300° C. in some embodiments. The thickness of the seed dielectric layer  25  is in a range from about 0.5 nm to about 2.0 nm in some embodiments and is in a range from about 0.5 nm to about 1.0 nm in other embodiments. 
     After the seed dielectric layer  25  is formed, the dielectric layer  30 , for example, Zr-doped HfO 2 , is formed on the seed dielectric layer  25 , as shown in  FIG.  3 A . Then, similar to  FIG.  2 B , a capping layer  40  is formed on the dielectric layer  30 . The capping layer  40  can be a crystalline orientation controlled layer as set forth above or a polycrystalline or amorphous layer. 
     Subsequently, similar to the operations explained with respect to  FIG.  2 C , after the capping layer  40  is formed, an annealing operation is performed as shown in  FIG.  3 C . After the annealing (and cooling) operation, the dielectric layer  30  becomes a (111) oriented crystalline layer. Due to the seed dielectric layer  25 , the (111) oriented doped-HfO 2  layer  30  can be obtained. In addition, after the annealing (and cooling) operation, the seed dielectric layer  25  also becomes an orthorhombic (111) oriented ZrO 2  layer. Further, similar to the operations explained with respect to  FIG.  2 D , a gate electrode  50  is formed as shown in  FIG.  3 D . The orthorhombic crystal phase identification and (111) orientation identification ofdoped-HfO 2  layer  30  can be determined by X-ray diffraction (XRD) patterns. The orthorhombic crystal phase identification and (111) orientation identification of specific crystal grain can be detected by a precession electron diffraction (PED) technique, which can detect a preferred orientation of each crystal grain and interlayer spacing of layers (d-spacing). 
       FIGS.  3 E and  3 F  show various stages of manufacturing operations for a negative capacitance structure in accordance with another embodiment of the present disclosure. In this embodiment, instead of forming a single layer of the doped-HfO 2  layer  30 , the dielectric layer includes alternately stacked one or more HfO 2  layer  30 A and one or more ZrO 2  layers  30 B formed over the seed dielectric layer  25 , as shown in  FIG.  3 E . 
     The alternate structure of one or more HfO 2  layer  30 A and one or more ZrO 2  layers  30 B can be formed by ALD. Each of the layers can be a monoatomic layer or multi-atomic layer (e.g., two or three monoatomic layers). Although  FIG.  3 E  shows four layers of HfO 2  layer  30 A and four layers of ZrO 2  layers  30 B, the number of the layers is not limited to four, and it can be two, three or five or more. 
     After the annealing and cooling operations, the stacked layer of HfO 2  layer  30 A and ZrO 2  layers  30 B becomes a single layer of Zr-doped HfO 2  (HfZrO 2 ), having a (111) oriented orthorhombic structure, which is determined by the PED technique, as shown in  FIG.  3 F . In some embodiments, at least a part of the seed dielectric layer  25  is consumed to be the single layer of Zr-doped HfO 2 . 
       FIGS.  4 A,  4 B,  4 C and  4 D  show various atomic structures of HfO 2 .  FIG.  4 A  shows the amorphous structure of the doped HfO 2  as deposited. By applying heat, the amorphous structure transitions to a tetragonal crystal structure (phase), as shown in  FIG.  4 B . When the heated HfO 2  having a tetragonal crystal structure is cooled with a capping metal thereon, the HfO 2  becomes an orthorhombic crystal structure (phase), as shown in  FIG.  4 C . If the heated HfO 2  having a tetragonal crystal structure is cooled without the capping metal thereon, the HfO 2  becomes a mixture of a monolithic crystal structure (left) and a tetragonal crystal structure (right), as shown in  FIG.  4 D . The orthorhombic HfO 2  has a non-centrosymmetric structure, and thus spontaneous polarization is generated by four oxygen ions displacement. Accordingly, better ferroelectric properties can be obtained by the orthorhombic HfO 2 . 
       FIG.  4 E  shows X-Ray Diffraction (XRD) measurement results. The samples are a 3-nm thick doped HfO 2  as deposited and a 3-nm thick doped HfO 2  after the annealing operation with a capping layer. The doped HfO 2  as deposited shows a broad spectrum indicating amorphous structure. In contrast, the doped HfO 2  after the annealing operation with a capping layer shows peaks corresponding to orthorhombic phase. 
       FIGS.  5  and  6    show electron energy loss spectroscopy (EELS) measurement results. As set forth above, after the dielectric layer  30  is converted to an orthorhombic phase, additional layers are formed with some thermal operations. The dopant elements in HfO 2  such as semiconductor material (Si) and metal elements (Zr, Al, La, Y, Gd and/or Sr) introduced by in-situ doping during the ALD growth are substantially uniformly distributed in the doped HfO 2  layer. As shown in  FIGS.  5  and  6   , Ti arising from the capping layer  40  (TiN based material) diffuses into the HfZrO 2  layer. When a TiAl layer is used as a work function adjustment layer  54  for an n-type transistor, Al may also diffuse into the HfZrO 2  layer, as shown in  FIG.  5   . In some embodiments, the HfZrO 2  layer includes Al in an amount of 5-7 mol %. When a TiN layer is used as a work function adjustment layer  54  for a p-type transistor, Ti originating from the TiN work function adjustment layer may also diffuse into the HfZrO 2  layer, as shown in  FIG.  6   . For the p-type transistor, Al may not diffuse into the HfZrO 2  layer (below a detection limit), even if a TiAl layer is formed on the TiN work function adjustment layer. In some embodiments, the HfZrO 2  layer includes Ti in an amount of 2-5 mol %. 
     In some embodiments, the ferroelectric HfO 2  layer consists of an orthorhombic crystal phase. In other embodiments, the ferroelectric HfO 2  layer is substantially formed by an orthorhombic crystal phase. In such a case, the orthorhombic crystal phase is about 80% or more of the ferroelectric HfO 2  layer, and the remaining phases may be amorphous, a monolithic phase and/or a tetragonal phase. 
       FIGS.  7 A- 13 C  show various stages of manufacturing operations for an NC FET in accordance with an embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after the processes shown by  FIGS.  7 A- 13 C , and some of the operations described below are replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with  FIGS.  1 A- 3 F  may be employed in the following embodiments, and detailed explanation thereof may be omitted. 
       FIG.  7 A  shows a perspective view and  FIG.  7 B  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. As shown in  FIGS.  7 A and  7 B , a substrate  200  is provided. In some embodiments, the substrate  200  is made of a suitable elemental semiconductor, such as silicon, diamond or germanium; a suitable alloy or compound semiconductor, such as Group-IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenic phosphide (GaAsP), or gallium indium phosphide (GaInP)), or the like. Further, the substrate  200  may include an epitaxial layer (epi-layer), which may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure. The upper portion of the substrate  200  can be multilayers of Si and SiGe. 
       FIG.  7 C  shows a perspective view and  FIG.  7 D  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. As shown in  FIGS.  7 C and  7 D , fin structures  210  are formed by etching the substrate  200  and forming an isolation insulating layer  220 . The fin structures  210  may be patterned by any suitable method. For example, the fin structures  210  may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin structures  210 . In some embodiments, the width of the fin structures  210  is in a range from about 4 nm to about 10 nm and the pitch of the fin structures  210  is in a range from about 10 nm to about 50 nm. 
     Then, an insulating material layer  220  is formed over the fin structures, thereby embedding the fin structures. The insulating material layer  220  may be made of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. In some embodiments, the insulating material layer  220  is formed through a process such as CVD, flowable CVD (FCVD), or a spin-on-glass process, although any acceptable process may be utilized. Subsequently, portions of the insulating material layer  220  extending over the top surfaces of the fin structures  210  are removed using, for example, an etch process, chemical mechanical polishing (CMP), or the like, as shown in  FIGS.  7 C and  7 D . 
       FIG.  8 A  shows a perspective view and  FIG.  8 B  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. Further, as shown in  FIGS.  8 A and  8 B , the insulating material layer  220  is recessed so that the upper portions of the fin structures  210  are exposed. The recessed insulating material layer  220  is called an isolation insulating layer or a shallow trench isolation (STI). The height of the exposed fin structures  210  measured from the upper surface of the isolation insulating layer  220  is in a range about 30 nm to about 100 nm in some embodiments. 
       FIG.  8 C  shows a perspective view and  FIG.  8 D  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. Subsequently, a dummy gate dielectric layer  215  is formed over the upper portions of the fin structure  210 , as shown in  FIGS.  8 C and  8 D . The dummy gate dielectric layer  215  is a silicon oxide layer formed by CVD or ALD, in some embodiments. The thickness of the dummy gate dielectric layer  215  is in a range from about 1 nm to about 3 nm in some embodiments. 
     Then, a polysilicon layer  230  is formed over the dummy gate electrode layer  215 , and further a hard mask layer is formed on the polysilicon layer. The hard mask layer is patterned into hard mask pattern  235  by suitable lithography and etching operations, as shown in  FIGS.  9 A- 9 C . The hard mask pattern  235  includes one or more layers of insulating material, such as silicon oxide and silicon nitride, in some embodiments. 
       FIG.  9 A  shows a perspective view,  FIG.  9 B  is a cross sectional view along the Y direction and  FIG.  9 C  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. By using the hard mask pattern  235  as an etching mask, the polysilicon layer is patterned into dummy gate electrodes  230 , as shown in  FIGS.  9 A- 9 C . In some embodiments, the width of the dummy gate electrode  230  is in a range from about 8 nm to about 20 nm. 
       FIG.  10 A  shows a perspective view,  FIG.  10 B  is a cross sectional view along the Y direction and  FIG.  10 C  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. Sidewall spacers  240  are formed on opposing side faces of the dummy gate electrodes  230 . The sidewall spacers  240  include one or more layers of insulating material, such as silicon oxide, silicon nitride and silicon oxynitride. Moreover, source/drain epitaxial layers  250  are formed over source/drain regions of the fin structures  210 . The source/drain epitaxial layer  250  includes SiP, SiAs, SiGeP, SiGeAs, GeP, GeAs, and/or SiGeSn or other suitable material for an n-type FET, and SiB, SiGa, SiGeB, SiGeGa, GeB, GeGa and/or SiGeSn or other suitable material for a p-type FET. The thickness of the source/drain epitaxial layers  250  is in a range from about 3 nm to about 8 nm in some embodiments. In some embodiments, an alloy layer, such as, a silicide layer, is formed over the source/drain epitaxial layers  250 . 
       FIG.  11 A  shows a perspective view,  FIG.  11 B  is a cross sectional view along the Y direction and  FIG.  11 C  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. Subsequently, a contact etch stop layer (CESL)  245  and an interlayer dielectric layer  260  are formed, and a planarization operation, such as a CMP operation, is performed to exposed upper surfaces of the dummy gate electrodes  230 , as shown in  FIGS.  11 A- 11 C . 
     In some embodiments, the CESL layer  245  is made of a silicon nitride based material, such as SiN and SiON, and the interlayer dielectric layer  260  is made of a silicon oxide based material, such as SiO 2  or a low-k material. In some embodiments, an annealing operation is performed after the interlayer dielectric layer is formed. 
       FIG.  12 A  shows a perspective view,  FIG.  12 B  is a cross sectional view along the Y direction and  FIG.  12 C  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. Then, the dummy gate electrodes  230  and the dummy gate dielectric layer  215  are removed by using dry and/or wet etching, thereby forming gate spaces  265 , as shown in  FIGS.  12 A- 12 C . Further, in the gate spaces  265 , an interfacial layer  271  and a ferroelectric dielectric layer  270  are formed as shown in  FIGS.  12 A- 12 C . In some embodiments, a seed dielectric layer (not shown) is formed between the interfacial layer  271  and the dielectric layer  270 . As set forth above, the interfacial layer  271  is made of silicon oxide, the seed dielectric layer is made of ZrO 2 , and the dielectric layer  270  is a Zr doped HfO 2  layer. 
       FIG.  13 A  shows a perspective view,  FIG.  13 B  is a cross sectional view along the Y direction and  FIG.  13 C  is a cross sectional view along the X direction, showing one of various stages of the manufacturing operation according to an embodiment of the present disclosure. Then, similar to the operations described with  FIGS.  2 A- 3 F , a capping layer  281  (see,  FIG.  13 D ) is formed, and an annealing operation is performed to convert the amorphous HfO 2  layer to an orthorhombic HfO 2  layer. Further, a gate electrode  280  is formed, as shown in  FIGS.  13 A- 13 C . The capping layer and the gate electrode may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof. After the conductive materials for the gate electrode are formed, a planarization operation, such as CMP, is performed to remove excess materials above the interlayer dielectric layer  260 . 
       FIG.  13 D  shows an enlarged cross sectional view of a top portion of the fin structure of  FIG.  13 C . In some embodiments, the silicon substrate  200  is a (100) substrate, and thus the top of the fin structure  210  has a (100) orientation and side faces of the fin structure  210  have a (110) orientation. The interfacial layer  271  is formed on the fin structure  210 , a ferroelectric dielectric layer  270  is formed on the interfacial layer  271 , and a capping layer  281  similar to the capping layer  40  of  FIGS.  2 A- 3 F  is formed on the ferroelectric layer  270 . 
     As set forth above, the ferroelectric dielectric layer  270  is, for example, a Zr doped HfO 2  layer. The polarization P of the Zr doped HfO 2  is parallel to the c axis of orthorhombic structure. When the Zr doped HfO 2  is (111) oriented, the total polarization is P/√3. 
     In the present disclosure, since the capping layer  40 / 281  and/or the seed dielectric layer  25  are used to control the crystal orientation of the Zr doped HfO 2  layer, the grain orientation of the Zr doped HfO 2  formed on the top and side faces of the fin structure  210  is (111), as shown in  FIG.  13 D . The orthorhombic crystal phase identification and (111) orientation identification of specific crystal grain can be determined by the precession electron diffraction (PED) technique. Accordingly, it is possible to achieve a largest ferroelectric effect by controlling the doped HfO 2  polarization to be parallel with the external electric-field from the gate electrode  280  for all directions. 
     After forming the gate structures, further CMOS processes are performed to form various features such as additional interlayer dielectric layers, contacts/vias, interconnect metal layers, and passivation layers, etc. 
       FIGS.  14 A- 14 D  show other manufacturing operations for an NC FinFET in accordance with some embodiments of the present disclosure. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is understood that additional operations can be provided before, during, and after processes shown by  FIGS.  14 A- 15 D , and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with respect to  FIGS.  1 A,  2 A- 3 F and  7 A- 13 C  may be employed in the following embodiments, and detailed explanation thereof may be omitted. 
     As shown in  FIG.  14 A , the fin structures  320  are patterned by using the hard mask pattern  312 , and the isolation insulating layer  325  is formed. Then, a dummy gate dielectric layer (not shown) and a polysilicon layer  332  are formed over the fin structures  320 , and further a hard mask pattern  334  is formed on the polysilicon layer  332 , as shown in  FIG.  14 B . The hard mask pattern  324  includes one or more layers of insulating material, such as silicon oxide and silicon nitride. 
     By using the hard mask pattern  334  as an etching mask, the polysilicon layer  332  is patterned into a dummy gate electrode  332 . Further, sidewall spacers  336  are formed on opposing side faces of the dummy gate electrode  332 , and an interlayer dielectric layer  342  is formed, as shown in  FIG.  14 C . The sidewall spacers  336  include one or more layers of insulating material, such as silicon oxide, silicon nitride and silicon oxynitride, and the interlayer dielectric layer  342  includes one or more layers of insulating material such as silicon oxide based material such as silicon dioxide (SiO 2 ) and SiON. The material of the sidewall spacers  333  and the material of the interlayer dielectric layer  342  are different from each other, so that each of these layers can be selectively etched. In one embodiment, the sidewall spacer  333  is made of SiOCN, SiCN or SiON and the interlayer dielectric layer  342  is made of SiO 2 . 
     Then, the dummy gate electrode  332  and the dummy gate dielectric layer are removed by using dry and/or wet etching, thereby forming a gate space  333 , as shown in  FIG.  14 D . 
     In the gate space, a first gate dielectric layer  303  and a first gate electrode  304  are formed as shown in  FIGS.  15 A and  15 B . After the conductive material is formed over the first gate dielectric layer  303 , a planarization operation, such as CMP, is performed to form the first gate electrode  304 . The first gate dielectric layer  303  is made of, for example, a high-k dielectric material, and the first gate electrode  304  is made of, for example, a conductive material such as TiN or other metal material. Further, an etch-back operation is performed to reduce the height of the first gate dielectric layer  303  and the first gate electrode  304 . The conductive material may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof. 
     Then, a ferroelectric dielectric layer  305  and a second gate electrode  306  are formed in the gate space  333 , as shown in  FIGS.  15 C and  15 D . A ferroelectric dielectric layer  305  is formed by the operations described with respect to  FIGS.  2 A- 3 F . A conductive material is formed over the ferroelectric dielectric layer  303 . After the conductive material is formed over the ferroelectric dielectric layer  305 , a planarization operation, such as CMP, is performed to form the second gate electrode  306 , as show in  FIGS.  15 C and  15 D . 
     After forming the gate structures, further CMOS processes are performed to form various features such as additional interlayer dielectric layers, contacts/vias, interconnect metal layers, and passivation layers, etc. 
     Other methods and structures for manufacturing MIMIS NC FETs are described in U.S. patent application Ser. No. 15/476,221 and Ser. No. 15/447,479, the entire contents of each of which are incorporated herein by reference. 
     It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages. 
     For example, in the present disclosure, a doped HfO 2  having an orthorhombic crystal phase is employed for an NC FET. By using a capping metallic layer during an annealing operation, it is possible to effectively convert an amorphous structure of the as-deposited HfO 2  layer to an orthorhombic crystal structure. As compared to other perovskite ferroelectric films (such as, PZT or BaTiO 3 ), the ferroelectric HfO 2  disclosed herein can maintain polarization without degradation down to 3 nm. 
     In accordance with an aspect of the present disclosure, in a method of manufacturing a negative capacitance structure, in a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed followed by a cooling operation. A second metallic layer is formed over the dielectric layer. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase, and the first metallic film includes a (111) oriented crystalline layer. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer includes HfO 2  doped with one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer includes HfO 2  doped with Zr and includes a (111) oriented crystalline layer. In one or more of the foregoing or following embodiments, the annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient. In one or more of the foregoing or following embodiments, the second metallic layer is formed after the cooling operation. In one or more of the foregoing or following embodiments, the first metallic layer includes TiN doped with Si. In one or more of the foregoing or following embodiments, the second metallic layer is TaN. In one or more of the foregoing or following embodiments, the forming a dielectric layer includes alternately forming one or more HfO 2  layers and one or more ZrO 2  layers over a substrate. In one or more of the foregoing or following embodiments, the dielectric layer as formed is amorphous. 
     According to another aspect of the present disclosure, in a method of manufacturing a negative capacitance structure, a seed dielectric layer is formed over a substrate. A dielectric layer is formed over the seed dielectric layer. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed followed by a cooling operation. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase, and the seed dielectric layer becomes a dielectric layer including an orthorhombic crystal phase. In one or more of the foregoing or following embodiments, the seed dielectric layer is ZrO 2 . In one or more of the foregoing or following embodiments, the dielectric layer includes HfO 2  containing Zr. In one or more of the foregoing or following embodiments, the forming a dielectric layer includes alternately forming one or more HfO 2  layers and one or more ZrO 2  layers over a substrate. In one or more of the foregoing or following embodiments, the annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient. In one or more of the foregoing or following embodiments, the capping metallic layer includes TiN doped with Si. In one or more of the foregoing or following embodiments, in the method, a second metallic layer is further formed over the dielectric layer. In one or more of the foregoing or following embodiments, the second layer is formed after the cooling operation. In one or more of the foregoing or following embodiments, in the method, an interfacial oxide layer is further formed over the substrate before the seed dielectric layer is formed. 
     In accordance with another aspect of the present disclosure, in a method of manufacturing a negative capacitance fin field effect transistor (NC-FinFET), a dummy gate structure is formed over a fin structure. A source/drain structure is formed over the fin structure on opposing sides of the dummy gate structure. An interlayer dielectric layer is formed over the source/drain structure. The dummy gate structure is removed, thereby exposing a channel region of the fin structure. An interfacial layer is formed over the exposed fin structure. A dielectric layer is formed over the interfacial layer. After the dielectric layer is formed, an annealing operation is performed followed by a cooling operation. A gate electrode including one or more metallic layers is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. At least one of a bottom crystal structure control layer between the interfacial layer and the dielectric layer and an upper crystal structure control layer between the dielectric layer and the gate electrode is provided. In one or more of the foregoing or following embodiments, the dielectric layer includes Zr doped HfO 2 . 
     In accordance with one aspect of the present application, a negative capacitance structure includes a channel layer made of a semiconductor, a ferroelectric dielectric layer disposed over the channel layer, and a gate electrode layer disposed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes a (111) oriented orthorhombic crystal. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer includes HfO 2  doped with one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer includes HfO 2  doped with Zr and includes a (111) oriented crystalline layer. The orthorhombic crystal phase identification and (111) orientation identification of specific crystal grain can be detected by the PEDz technique. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer further includes Ti in an amount of 2-5 mol %. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer further includes Al in an amount of 5-7 mol %. In one or more of the foregoing or following embodiments, the gate electrode layer includes a Si-doped TiN layer in contact with the ferroelectric dielectric layer. In one or more of the foregoing or following embodiments, the Si-doped TiN layer is (111) orientated. In one or more of the foregoing or following embodiments, the negative capacitance structure further includes an interfacial layer disposed on the channel layer, and a seed dielectric layer disposed on the interfacial layer. In one or more of the foregoing or following embodiments, the seed dielectric layer includes ZrO 2 . 
     In accordance with another aspect of the present application, a negative capacitance field effect transistor (NC-FET) includes a channel layer made of a semiconductor, an interfacial layer disposed on the channel layer, a ferroelectric dielectric layer disposed over the interfacial layer, and a gate electrode layer disposed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes a (111) oriented orthorhombic crystal. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer includes HfO 2  doped with one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer includes HfZrO 2 . In one or more of the foregoing or following embodiments, at least one of a bottom crystal structure control layer between the interfacial layer and the dielectric layer and an upper crystal structure control layer between the dielectric layer and the gate electrode is formed. In one or more of the foregoing or following embodiments, the bottom crystal structure control layer includes ZrO 2 . In one or more of the foregoing or following embodiments, the upper crystal structure control layer includes Si-doped TiN. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer further includes Ti in an amount of 2-5 mol %. In one or more of the foregoing or following embodiments, the NC-FET is an n-type FET and the work function adjustment layer includes TiAl. In one or more of the foregoing or following embodiments, the ferroelectric dielectric layer further includes Al in an amount of 5-7 mol %. 
     In accordance with another aspect of the present application, a negative capacitance field effect transistor (NC-FET) includes a channel layer made of a semiconductor, a first dielectric layer disposed over the channel layer, a first conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the first conductive layer, and a gate electrode layer disposed over the second dielectric layer. The ferroelectric dielectric layer includes a (111) oriented orthorhombic crystal. In one or more of the foregoing or following embodiments, the NC-FET further comprises an interfacial layer disposed on the channel layer. At least one of a bottom crystal structure control layer between the interfacial layer and the first dielectric layer and an upper crystal structure control layer between the first dielectric layer and the first conductive layer is provided. 
     The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.