Patent Publication Number: US-2020287509-A1

Title: Operational amplifier

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-039523, filed Mar. 5, 2019, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate to an operational amplifier. 
     BACKGROUND 
     Operational amplifiers capable of rail-to-rail input and output operation are known. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a configuration example of an operational amplifier according to a first embodiment. 
         FIG. 2  is a circuit diagram of differential circuitry included in the operational amplifier according to the first embodiment. 
         FIG. 3  is a circuit diagram of output circuitry included in the operational amplifier according to the first embodiment. 
         FIG. 4  is a block diagram illustrating a configuration example of an operational amplifier according to a comparative example of the first embodiment. 
         FIG. 5  is a circuit diagram of output circuitry included in the operational amplifier according to the comparative example of the first embodiment. 
         FIG. 6  is a graph illustrating an example of a relationship between an input voltage and an offset voltage, in each of the operational amplifier according to the first embodiment and the operational amplifier according to the comparative example of the first embodiment. 
         FIG. 7  is a circuit diagram of output circuitry included in an operational amplifier according to a second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, an operational amplifier includes a first input terminal, a second input terminal, an output terminal, differential circuitry, and output circuitry. The differential circuitry including a first node, a second node, a first transistor, and a second transistor. The first transistor being coupled to the first input terminal at a gate and coupled to the first node at one end. The second transistor being coupled to the second input terminal at a gate, coupled to the second node at one end, and coupled to another end of the first transistor at another end. The output circuitry including a third node, a fourth node, a fifth node, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The fifth node being coupled to the output terminal. The third transistor being coupled to the first node at a gate and coupled to the third node at one end. The fourth transistor being coupled to the second node at a gate and coupled to the fourth node at one end. The fifth transistor being coupled to the fourth node at a gate and coupled to the third node at one end. The sixth transistor being coupled to the fourth node at each of a gate and one end. The seventh transistor being coupled to the second node at a gate and coupled to the fifth node at one end. The eighth transistor being coupled to the third node at a gate and coupled to the fifth node at one end. 
     Hereinafter, embodiments will be described with reference to the accompanying drawings. Each of the embodiments is an example of an apparatus and a method to embody a technical idea of the invention. The drawings are schematic or conceptual, and the dimensions and ratios, etc. in the drawings are not always the same as the actual ones. The technical ideas of the present invention are not limited by shapes, structures, or arrangements, etc. of the components. 
     In the description that follows, components having substantially the same functions and configurations will be denoted by the same reference symbols. The numbers after the letters constituting the reference symbols are used to discriminate between components that are denoted by the reference symbols sharing letters in common and that have similar configurations. If there is no need to discriminate between components that are denoted by the reference symbols sharing letters in common, such components are denoted by reference symbols that include the letters only. 
     [1] First Embodiment 
     Hereinafter, a description will be given of an operational amplifier  1  according to a first embodiment. 
     [1-1] Configuration of Operational Amplifier  1   
       FIG. 1  is a configuration example of the operational amplifier  1  according to the first embodiment. The operational amplifier  1  is an operational amplifier capable of rail-to-rail input and output operation. As shown in  FIG. 1 , the operational amplifier  1  includes, for example, terminals T 1 -T 5 , differential circuitry  10 , and output circuitry  20 . In the operational amplifier  1 , each of the terminals T 1 -T 5  can be coupled to an external device, and the differential circuitry  10  and the output circuitry  20  are integrated on, for example, a single semiconductor chip. 
     The terminal T 1  is a positive-side power-supply terminal of the operational amplifier  1 , and is coupled to a power line PW. The terminal T 1  is applied with, for example, a power-supply voltage VDD. The terminal T 2  is a negative-side power-supply terminal of the operational amplifier  1 , and is coupled to a power line GW. The terminal T 2  is applied with, for example, a power-supply voltage VSS, which is lower than the power-supply voltage VDD. The terminal T 3  is a non-inverting input terminal of the operational amplifier  1 . A signal INP is input to the terminal T 3 . The terminal T 4  is an inverting input terminal of the operational amplifier  1 . A signal INN is input to the terminal T 4 . The terminal T 5  is an output terminal of the operational amplifier  1 . A signal Vout is output from the terminal T 5 . 
     The differential circuitry  10  is coupled to both of the power lines PW and GW and both of the terminals T 3  and T 4 , and differentially amplifies the signal input to the terminal T 3  and the signal input to the terminal T 4 . The differential circuitry  10  includes a pair of nodes VX and VY, to which the signals differentially amplified by the differential circuitry  10  are output. 
     The output circuitry  20  is coupled to both of the power lines PW and GW, the terminal T 5 , and both of the nodes VX and VY of the differential circuitry  10 . The output circuitry  20  outputs, as a signal Vout, a voltage based on the voltage of each of the nodes VX and VY to the terminal T 5 . 
       FIG. 2  illustrates an example of a circuit configuration of the differential circuitry  10  included in the operational amplifier  1  according to the first embodiment. As shown in  FIG. 2 , the differential circuitry  10  includes a first differential circuit  11 , a second differential circuit  12 , a current control circuit  13 , and a folded cascode circuit  14 . 
     The first differential circuit  11  differentially amplifies the signal input to the terminal T 3  and the signal input to the terminal T 4 , and outputs the differentially amplified signals to the folded cascode circuit  14 . The first differential circuit  11  includes, for example, transistors MP 11  and MP 12 . Each of the transistors MP 11  and MP 12  is, for example, a p-type MOSFET. 
     The source of the transistor MP 11  is coupled to a node N 1 . The gate of the transistor MP 11  is coupled to the terminal T 3 . The drain of the transistor MP 11  is coupled to a node N 2 . The source of the transistor MP 12  is coupled to the node N 1 . The gate of the transistor MP 12  is coupled to the terminal T 4 . The drain of the transistor MP 12  is coupled to a node N 3 . In the present specification, the current that flows from the transistor MP 11  into the node N 2  will be referred to as a “current I 2 ”, and the current that flows from the transistor MP 12  into the node N 3  will be referred to as a “current I 3 ”. 
     The second differential circuit  12  differentially amplifies the signal input to the terminal T 3  and the signal input to the terminal T 4 , and outputs the differentially amplified signals to the folded cascode circuit  14 . The second differential circuit  12  includes, for example, transistors MN 11  and MN 12 . Each of the transistors MN 11  and MN 12  is, for example, an n-type MOSFET. 
     The source of the transistor MN 11  is coupled to a node N 5 . The gate of the transistor MN 11  is coupled to the terminal T 3 . The drain of the transistor MN 11  is coupled to a node N 6 . The source of the transistor MN 12  is coupled to the node N 5 . The gate of the transistor MN 12  is coupled to the terminal T 4 . The drain of the transistor MN 12  is coupled to a node N 7 . In the present specification, the current that flows from the node N 6  into the transistor MN 11  will be referred to as a “current I 4 ”, and the current that flows from the node N 7  into the transistor MN 12  will be referred to as a “current I 5 ”. 
     The current control circuit  13  controls the currents that flow through the first differential circuit  11  and the second differential circuit  12 , in accordance with the signals INP and INN. The current control circuit  13  includes, for example, a transistor MP 13 , transistors MN 13  and MN 14 , and a constant current source CS 1 . The transistor MP 13  is, for example, a p-type MOSFET. Each of the transistors MN 13  and MN 14  is, for example, an n-type MOSFET. 
     The constant current source CS 1  is coupled between the power line PW and the node N 1 . The constant current source CS 1  is applied with, for example, the power-supply voltage VDD, and supplies a current I 1  to the node N 1 . The source of the transistor MP 13  is coupled to the node N 1 . The drain of the transistor MP 13  is coupled to a node N 4 . A voltage V 1  is input to the gate of the transistor MP 13 . The drain and the gate of the transistor MN 13  are coupled to the node N 4 . The source of the transistor MN 13  is coupled to the power line GW. The drain of the transistor MN 14  is coupled to the node N 5 . The source of the transistor MN 14  is coupled to the power line GW. The gate of the transistor MN 14  is coupled to the node N 4 . 
     The folded cascode circuit  14  amplifies the signals input from the first differential circuit  11  and the second differential circuit  12 , and outputs the amplified signals to the nodes VX and VY. The folded cascode circuit  14  includes, for example, transistors MP 14 , MP 15 , MP 16 , and MP 17 , and transistors MN 15 , MN 16 , MN 17 , and MN 18 . Each of the transistors MP 14 , MP 15 , MP 16 , and MP 17  is, for example, a p-type MOSFET. Each of the transistors MN 15 , MN 16 , MN 17 , and MN 18  is, for example, an n-type MOSFET. 
     The source of the transistor MP 14  is coupled to the power line PW. The drain of the transistor MP 14  is coupled to the node N 7 . The gate of the transistor MP 15  is coupled to the gate of the transistor MP 14 . The source of the transistor MP 15  is coupled to the power line PW. The drain of the transistor MP 15  is coupled to the node N 6 . The gates of the transistors MP 14  and MP 15  are applied with a voltage V 4 . 
     The source of the transistor MP 16  is coupled to the node N 7 . The drain of the transistor MP 16  is coupled to the node VX. The gate of the transistor MP 17  is coupled to the gate of the transistor MP 16 . The source of the transistor MP 17  is coupled to the node N 6 . The drain of the transistor MP 17  is coupled to the node VY. The gates of the transistors MP 16  and MP 17  are respectively applied with a voltage V 3 . 
     The source of the transistor MN 15  is coupled to the node N 3 . The drain of the transistor MN 15  is coupled to the node VX. The gate of the transistor MN 16  is coupled to the gate of the transistor MN 15 . The source of the transistor MN 16  is coupled to the node N 2 . The drain of the transistor MN 16  is coupled to the node VY. The gate of the transistor MN 15  and the gate of the transistor MN 16  are applied with the voltage V 2 . The source of the transistor MN 17  is coupled to the power line GW. The gate of the transistor MN 17  is coupled to the node VX. The drain of the transistor MN 17  is coupled to the node N 3 . The source of the transistor MN 18  is coupled to the power line GW. The gate of the transistor MN 18  is coupled to the node VX. The drain of the transistor MN 18  is coupled to the node N 2 . 
     Since the above-described differential circuitry  10  provides differential amplification, paired transistors are provided in, for example, a substantially equal size. That is, the paired transistors MP 11  and MP 12 , MN 11  and MN 12 , MP 14  and the MP 15 , MP 16  and MP 17 , MP 15  and MP 16 , and MP 17  and MP 18  are respectively provided in a substantially equal size. 
     The sizes of the transistor MN 13  and the transistor MN 14  are, for example, substantially equal. The threshold voltages of the transistor MP 11 , the transistor MP 12 , and the transistor MP 13  are, for example, substantially equal. 
     The above-described folded cascode circuit  14  includes two current paths. Specifically, the folded cascode circuit  14  includes, between the power lines PW and GW, a current path that runs through the transistors MP 14 , MP 16 , MN 15 , and MN 17  in this order, and a current path that runs through the transistors MP 15 , MP 17 , MN 16 , and MN 18  in this order. In the description that follows, the current that flows from the power line PW into the transistors MP 14  and MP 15  will be respectively denoted as “I 6 ” and “I 7 ”, and the current that flows from the transistors MN 17  and MN 18  into the power line GW will be respectively denoted as “I 8 ” and “I 9 ”. 
     Since the transistors MN 17  and MN 18  form a current mirror, the amounts of current flowing through the paired transistors in the folded cascode circuit  14 , whose gates are commonly coupled, are substantially equal when an in-phase input voltage is input to the terminals T 3  and T 4 , and a differential signal is not input thereto. Specifically, the amounts of current flowing through the transistors MP 14  and MP 15  are substantially equal; the amounts of current flowing through the transistors MP 16  and MP 17  are substantially equal; the amounts of current flowing through the transistors MN 15  and MN 16  are substantially equal; and the amounts of current flowing through the transistors MN 17  and MN 18  are substantially equal. 
       FIG. 3  shows an example of a circuit configuration of the output circuitry  20  included in the operational amplifier  1  according to the first embodiment. As shown in  FIG. 3 , the output circuitry  20  includes a drive circuit  21 , an output circuit  22 , and a phase compensation circuit  23 . 
     The drive circuit  21  generates a drive voltage based on the voltage of the node VX and the voltage of the node VY, and outputs the drive signal to a node N 9 . The drive circuit  21  includes, for example, transistors MP 21  and MP 22 , and transistors MN 21  and MN 22 . Each of the transistors MP 21  and MP 22  is, for example, a p-type MOSFET. Each of the transistors MN 21  and MN 22  is, for example, an n-type MOSFET. 
     The source of the transistor MP 21  is coupled to the power line PW. The gate and the drain of the transistor MP 21  are coupled to a node N 8 . The source of the transistor MP 22  is coupled to the power line PW. The gate of the transistor MP 22  is coupled to the node N 8 . The drain of the transistor MP 22  is coupled to the node N 9 . The source of the transistor MN 21  is coupled to the power line GW. The gate of the transistor MN 21  is coupled to the node VY. The drain of the transistor MN 21  is coupled to the node N 8 . The source of the transistor MN 22  is coupled to the power line GW. The gate of the transistor MN 22  is coupled to the node VX. The drain of the transistor MN 22  is coupled to the node N 9 . 
     The output circuit  22  generates a signal Vout based on the voltage of the node VY and the voltage of the node N 9 , and outputs the signal Vout from the terminal T 5 . The output circuit  22  includes, for example, transistors MP 23  and MN 23 . The transistor MP 23  is, for example, a p-type MOSFET. The transistor MN 23  is, for example, an n-type MOSFET. 
     The source of the transistor MP 23  is coupled to a power line PW. The gate of the transistor MP 23  is coupled to the node N 9 . The drain of the transistor MP 23  is coupled to a node N 10 . The source of the transistor MN 23  is coupled to the power line GW. The gate of the transistor MN 23  is coupled to the node VY. The drain of the transistor MN 23  is coupled to the node N 10 . 
     The phase compensation circuit  23  compensates for phase characteristics of the operational amplifier  1 . The phase compensation circuit  23  includes a resistor element R 21  and capacitor elements C 21  and C 22 . 
     One end of the resistor element R 21  is coupled to the node N 10 . The other end of the resistor element R 21  is coupled to one of the electrodes of the capacitor element C 21 , and to one of the electrodes of the capacitor element C 22 . The other electrode of the capacitor element C 21  is coupled to the node N 9 . The other electrode of the capacitor element C 22  is coupled to the node VY. 
     In the drive circuit  21  included in the output circuitry  20  described above, the transistor MP 21  and the transistor MP 22  are substantially equal in size. Also, the transistor MN 21  and the transistor MN 22  are substantially equal in size. The node N 10  is coupled to the terminal T 5 . 
     That is, the voltage of the node N 10  in the output circuitry  20  corresponds to the signal Vout. 
     [1-2] Operation of Operational Amplifier  1   
     The operational amplifier  1  according to the first embodiment is capable of rail-to-rail input and output operation. That is, a voltage equal to or greater than the power-supply voltage VSS, and equal to or less than the power-supply voltage VDD, is input to the operational amplifier  1 . The operational amplifier  1  outputs a voltage equal to or greater than the power-supply voltage VSS, and equal to or less than the power-supply voltage VDD, based on the input voltage. In rail-to-rail input and output operation, the differential circuitry  10  switches its operation according to the signals input to the terminals T 3  and T 4 . 
     The operational amplifier  1  according to the first embodiment operates as a voltage follower circuit when the terminals T 5  and T 4  are coupled. Specifically, the operational amplifier  1  operates in such a manner that the signal Vout output from the terminal T 5  and the signal INP input to the terminal T 3  are equal. That is, the operational amplifier  1  operates in such a manner that the voltages of the terminals T 3 , T 4 , and T 5  are equal. 
     A description will be given below of the detailed operation of each of the differential circuitry  10  and the output circuitry  20  when the operational amplifier  1  is used as a voltage follower circuit. In the description that follows, let us assume that the power-supply voltage VDD is applied to the terminal T 1 , the terminal T 2  is grounded, and the signal INP is input to the terminal T 3 . To simplify the description, the voltage of the signal Vout will be denoted “Vout”, the voltage of the signal INP will be denoted “Vin”, the voltage of the node VX will be denoted “VX”, and the voltage of the node VY will be denoted “VY”. 
     [1-2-1] Operation of Differential Circuitry  10   
     A description will be given of the operation of the differential circuitry  10  according to the first embodiment, with reference to  FIG. 2 . When the signal INP is input to the operational amplifier  1 , the gates of the transistors MP 11  and MN 11  are respectively applied with the voltage Vin. At this time, the current I 1  is supplied to the node N 1  from the constant current source CS 1 , and the gate of the transistor MP 13  is applied with the voltage V 1 . 
     The operation of the differential circuitry  10  according to the first embodiment changes based on the magnitude relationship of the voltages Vin and V 1 . For the operational amplifier  1 , there will be, for example, three possible operating points: (1) case where Vin is less than V 1 , (2) case where Vin is greater than V 1 , and (3) case where Vin is substantially equal to V 1 . 
     &lt;(1) Case where Vin is Less than V 1 &gt; 
     In the case where Vin is less than V 1 , the transistors MP 11  and MP 12  are turned on, and the transistor MP 13  is turned off. That is, the first differential circuit  11  is turned on, the current I 2  flows from the transistor MP 11  to the node N 2 , and the current I 3  flows from the transistor MP 12  to the node N 3 . With the transistor MP 13  turned off, the current path between the nodes N 1  and N 4  is cut off. This gives I 1 =I 2 +I 3 . Since the current I 2  and the current I 3  are substantially equal in the present example, 
         I 2= I 3=(½)× I 1.
 
     When the transistor MP 13  is turned off, the voltage of the node N 4  decreases, and the transistor MN 13  is turned off. With the transistor MN 13  turned off, the transistor MN 14 , forming a current mirror circuit with the transistor MN 13 , is also turned off. With the transistor MN 14  turned off, the amount of current at the node N 5  decreases, and the transistors MN 11  and MN 12  are turned off. That is, the second differential circuit  12  is turned off, and the current path between the node N 5  and each of the nodes N 6  and N 7  is cut off. 
     Consequently, a current I 8 , which flows through the transistor MN 17 , is equal to the sum of the current I 3  and the current I 6 ; and a current I 9 , which flows through the transistor MN 18 , is equal to the sum of the current I 2  and the current I 7 . Based on these relationships, the current I 8 , which flows through the transistor MN 17 , can be expressed as follows: I 8 =I 6 +(½)×I 1 . 
     Since the gate of the transistor MN 17  is coupled to the source of the transistor MN 17  via the transistor MN 15 , the gate voltage of the transistor MN 17  (namely, the voltage of the node VX) is determined by the current flowing through the transistor MN 17  and the characteristics of the transistor MN 17 . Specifically, the voltage of the node VX can be expressed, using the basic formula for the strong-inversion operation of the MOS, as follows: VX=β√(2×(I 6 +(½)×I 1 ))+VthMN 17 , where β is a value determined by the processing and the size of the transistor, and VthMN 17  is the threshold voltage of the transistor MN 17 . 
     Unlike the node VX, the node VY is not coupled to the gates of the transistors included in the folded cascode circuit  14 . Thus, the operating point of the node VY is determined by the output circuitry  20  coupled to the node VY outside the differential circuitry  10 . 
     &lt;(2) Case where Vin is Greater than V 1 &gt; 
     In the case where Vin is greater than V 1 , the transistors MP 11  and MP 12  are turned off, and the transistor MP 13  is turned on. That is, the first differential circuit  11  is turned off, and the current path between the node N 1  and each of the nodes N 2  and N 3  is cut off. 
     The transistor MP 13  is turned on, and the current flows from the transistor MP 13  to the node N 4 . The amount of current that flows through the node N 4  is substantially equal to the current I 1 . When the transistor MP 13  is turned on, the voltage of the node N 4  increases, and the transistor MN 13  is turned on. With the transistor MN 13  turned on, the transistor MN 14 , forming a current mirror circuit with the transistor MN 13 , is also turned on. With the transistor MN 14  turned on, the voltage of the node N 5  decreases, and the transistors MN 11  and MN 12  are turned on. That is, the second differential circuit  12  is turned on, the current I 4  flows from the node N 6  to the transistor MN 11 , and the current I 5  flows from the node N 7  to the transistor MN 12 . The amount of current that flows from the node N 5  to the transistor MN 14  is substantially equal to the sum of the currents I 4  and I 5 . Since the transistor MN 14  and the transistor MN 13  are substantially equal in size, the amount of current that flows through the node N 5  and the amount of current that flows through the node N 4  are substantially equal. That is, the amount of current that flows through the node N 5  is substantially equal to the current I 1 . Since the current I 4  and the current I 5  are substantially equal in the present example, I 4 =I 5 =(½)×I 1 . 
     Consequently, the current I 8 , which flows through the transistor MN 17 , takes the value obtained by subtracting the current I 5  from the current I 6 ; and the current I 9 , which flows through the transistor MN 18 , takes the value obtained by subtracting the current I 4  from the current I 7 . Based on these relationships, the current I 8 , which flows through the transistor MN 17 , can be expressed as follows: I 8 =I 6 −(½)×I 1 . Thus, the voltage of the node VX can be expressed as follows: VX=β√(2×(I 6 −(½)×I 1 ))+VthMN 17 . 
     &lt;(3) Case where Vin is Substantially Equal to V 1 &gt; 
     In the case where Vin is substantially equal to V 1 , the transistors MP 11 , MP 12 , and MP 13  are turned on. That is, the first differential circuit  11  and the second differential circuit  12  are turned on, and the sum of the current flowing through the first differential circuit  11  and the current flowing through the second differential circuit  12  is substantially equal to the current I 1 . Consequently, the current I 8 , which flows through the transistor MN 17 , takes a value between the value in the above-described case (1) and the value in the above-described case (2). Thus, the voltage of the node VX takes a value between the value in the above-described case (1) and the value in the above-described case (2). 
     [1-2-2] Operation of Output Circuitry  20   
     Next, a description will be given of the operation of the output circuitry  20  based on the above-described operation of the differential circuitry  10 , with reference to  FIG. 3 . The output circuitry  20  determines the operating point of the node VY based on the voltage of the node VX, and generates a signal Vout based on the voltages of the nodes VX and VY. 
     A description will be given of the method of determining the operating point of the node VY at the output circuitry  20 . At the output circuitry  20 , the transistor MN 22  supplies a current based on the voltage of the node VX, coupled to its gate, from the node N 9  to the power line GW. A current I 11 , which flows through the transistor MN 22 , is supplied from the transistor MP 22 . The transistors MP 21  and MP 22  are substantially equal in size, and form a current mirror circuit. Thus, the transistor MP 21  supplies a current I 10 , which is substantially equal to the current I 11 , to the transistor MN 21 . 
     The gate voltage of the transistor MN 21  is based on the current I 10  supplied from the transistor MP 21 . The transistors MN 21  and MN 22  are provided in a substantially equal size, and the currents flowing therethrough are substantially equal. Thus, the voltage of the node VY, to which the gate of the transistor MN 21  is coupled, and the voltage of the node VX, to which the gate of the transistor MN 22  is coupled, are substantially equal. 
     A description will be given of the method of generating the signal Vout at the output circuitry  20 . At the output circuitry  20 , the drive circuit  21  controls the voltage of the node N 9  based on differential signals output to the nodes VX and VY from the differential circuitry  10 , thereby controlling the transistor MP 23  included in the output circuit  22 . Specifically, the differential signals of the nodes VX and VY are respectively input to the gates of the transistors MN 22  and MN 21 . The transistors MN 21  and MN 22  are coupled to a current mirror circuit formed of the transistors MP 21  and MP 22 . This allows the differential signals of the nodes VX and VY to be synthesized at the node N 9 . The signal of the node N 9  can be thus used to control the transistor MP 23 . 
     The output circuit  22  outputs the signal Vout to the terminal T 5 , based on the voltages of the nodes N 9  and VY. Specifically, the transistor MP 23  outputs a voltage to the terminal T 5 , based on the voltage of the node N 9 . The transistor MN 23  outputs a voltage to the terminal T 5 , based on the voltage of the node VY. A signal Vout, obtained by synthesizing the outputs of both of the transistors MP 23  and MN 23 , is output to the terminal T 5 . 
     [1-3] Advantageous Effects of First Embodiment 
     According to the above-described operational amplifier  1  of the first embodiment, it is possible to suppress an offset voltage, thus improving the operation reliability. Advantageous effects of the operational amplifier  1  according to the first embodiment will be described in detail below. 
     When the operational amplifier is used as, for example, a voltage follower circuit, it is desirable that the non-inverting input and the output signal be at the same voltage. However, in an operational amplifier, a difference may be caused in the output voltage by variations, etc. between the element on the non-inverting input side and the element on the inverting input side. Such a difference in voltage between the non-inverting input and the output signal is called, for example, “an offset voltage”. In an operational amplifier, it is preferable that the offset voltage be close to 0 V. 
       FIG. 4  illustrates a configuration example of an operational amplifier  2  according to a comparative example of the first embodiment. The operational amplifier  2  according to the comparative example is configured in such a manner that the output circuitry  20  of the operational amplifier  1  according to the first embodiment, described with reference to  FIG. 1 , is replaced by output circuitry  30 . As shown in  FIG. 4 , the output circuitry  30  is coupled only to a node VY of the differential circuitry  10 , in the operational amplifier  2  according to the comparative example. That is, a node VX is not coupled to the output circuitry  30  in the operational amplifier  2  according to the comparative example. 
       FIG. 5  is a circuit diagram of the output circuitry  30 , included in the operational amplifier  2  according to the comparative example of the first embodiment. As shown in  FIG. 5 , the output circuitry  30  includes a drive circuit  31 , an output circuit  32 , and a phase compensation circuit  33 . The drive circuit  31  generates a signal for driving a transistor MP 32 , included in the output circuit  32 , based on the voltage of the node VY. The drive circuit  31  determines the operating point of the node VY. In the operational amplifier  2  according to the comparative example, the operating point of the node VY is the voltage based on the current I 12  supplied from the constant current source CS 2  and the characteristics of the transistor MN 31 . The output circuit  32  outputs the signal Vout, based on the signal generated by the drive circuit  31  and the signal of the node VY. The phase compensation circuit  33  compensates for phase characteristics of the operational amplifier  2 . 
     In the operational amplifier  2  according to the comparative example, the voltage of the node VY is determined by the output circuitry  30 . On the other hand, the voltage of the node VX changes according to the voltages of the terminals T 3  and T 4 . The node VX, though not illustrated, is included in the differential circuitry  10  of the operational amplifier  2 . That is, in the operational amplifier  2  according to the comparative example, a difference may be generated between the voltage of the node VX and the voltage of the node VY. 
     In contrast, the operational amplifier  1  according to the first embodiment includes the output circuitry  20  coupled to the nodes VX and VY. In the operational amplifier  1  according to the first embodiment, the output circuitry  20  determines the voltage of the node VY to be equal to the voltage of the node VX. That is, the operational amplifier  1  according to the first embodiment is configured in such a manner that, when the voltage of the node VX changes, the voltage of the node VY also changes to be equal thereto, thus keeping the voltages of the nodes VX and VY substantially equal. 
       FIG. 6  illustrates an example of a relationship between an input voltage and an offset voltage in each of the operational amplifier  1  according to the first embodiment and the operational amplifier  2  according to the comparative example of the first embodiment. Specifically,  FIG. 6  illustrates an example in which each of the operational amplifiers  1  and  2  is used as a voltage follower circuit, and the input voltage falls within the range from 0 V to VDD. In  FIG. 6 , the lateral axis represents the input voltage (e.g., the voltage input to the terminal T 3 ), and the vertical axis represents the offset voltage. As illustrated in  FIG. 6 , the offset voltage of the operational amplifier  2  according to the comparative example fluctuates from a negative value to a positive value, according to the voltage applied to the terminal T 3 . On the other hand, changes in the offset voltage of the operational amplifier  1  according to the first embodiment are suppressed, regardless of the input voltage; namely, the voltage applied to the terminal T 3 . 
     By thus setting the voltages of the nodes VY and VX to be substantially equal, using the output circuitry  20 , the operational amplifier  1  according to the first embodiment is capable of suppressing the offset voltage. In addition, since the operational amplifier  1  according to the first embodiment is capable of suppressing a change in the offset voltage caused by a change in the voltage applied to the terminal T 3 , it is possible to achieve a high common-mode rejection ratio (CMRR). 
     The above-described operational amplifier  1  according to the first embodiment is capable of suppressing the offset voltage even during a low-voltage operation. This advantageous effect will be described below, by taking an example in which the operational amplifier  1  is operated as a voltage follower at a low power-supply voltage. 
     A transistor switches from operating in the saturation region to operating in the non-saturation region when, for example, the drain-to-source voltage decreases. A transistor has different characteristics when operating in the saturation region when operating in the non-saturation region. It is thus desirable that each of the paired transistors operate in the same region, in a circuit that performs, for example, differential amplification. In order to allow a transistor to operate in the saturation region during a low-voltage operation, it is effective to design the threshold voltage of the transistor to be low. In the present example, let us assume that the differential circuitry  10  is formed of transistors with low threshold voltages. 
     When the differential circuitry  10  is designed in such a manner that the transistors MN 15  to MN 18  operate in the saturation region while Vin is between 0 V and V 1 , the transistor MN 15  is apt to operate in the non-saturation region while Vin is between V 1  and VDD. When, for example, the operating points of the transistors MN 15  and MN 16  differ, the transistor MN 15  is apt to operate in the non-saturation region, and the transistor MN 16  is apt to operate in the saturation region. Consequently, the operational amplifier may have a high offset voltage during a low-voltage operation, causing deterioration in the CMRR. 
     In the operational amplifier  2  according to the comparative example, the voltage of the node VY is determined by the output circuitry  30 . In this case, the drain-to-source voltage of the transistor MN 16  may be greater than the drain-to-source voltage of the transistor MN 15 . Thus, in the operational amplifier  2  according to the comparative example, the transistor MN 15  may operate in the non-saturation region, and the transistor MN 16  may operate in the saturation region. 
     In contrast, in the operational amplifier  1  according to the first embodiment, the voltage of the node VY is set by the output circuitry  20  to be substantially equal to the voltage of the node VX. Thus, in the operational amplifier  1  according to the first embodiment, it can be expected that, when the transistor MN 15  switches to operating in the non-saturation region, the transistor MN 16  also switches to operating in the non-saturation region. 
     This allows the paired transistors to operate in the non-saturation region in differential amplification, even when the power-supply voltage is low, in the operational amplifier  1  according to the first embodiment. Consequently, the operational amplifier  1  according to the first embodiment is capable of suppressing the offset voltage even during a low-voltage operation. 
     [2] Second Embodiment 
     An operational amplifier  1  according to the second embodiment differs from the operational amplifier  1  according to the first embodiment in terms of the circuit configuration of the differential circuitry  10 . Differences from the first embodiment will be described below, with reference to the operational amplifier  1  according to the second embodiment. 
     [2-1] Configuration of Operational Amplifier  1   
       FIG. 7  is a circuit diagram of the differential circuitry  10  included in the operational amplifier  1  according to the second embodiment. As shown in  FIG. 7 , the differential circuitry  10  includes a differential circuit  41  and a current mirror circuit  42 . 
     The differential circuit  41  includes, for example, transistors MP 41  and MP 42 , and a constant current source CS 3 . Each of the transistors MP 41  and MP 42  is, for example, a p-type MOSFET. 
     The constant current source CS 3  is coupled between a power line PW and the source of each of the transistors MP 41  and MP 42 . The constant current source CS 3  is applied with, for example, the power-supply voltage VDD, and supplies the constant current to the source of each of the transistors MP 41  and MP 42 . The gate of the transistor MP 41  is coupled to the terminal T 3 . The drain of the transistor MP 41  is coupled to the node VY. The gate of the transistor MP 42  is coupled to the terminal T 4 . The drain of the transistor MP 42  is coupled to the node VX. 
     The current mirror circuit  42  includes transistors MN 41  and MN 42 . Each of the transistors MN 41  and MN 42  is, for example, an n-type MOSFET. 
     The source of the transistor MN 41  is coupled to the power line GW. The gate and the drain of the transistor MN 41  are coupled to the node VY. The source of the transistor MN 42  is coupled to the power line GW. The gate of the transistor MN 42  is coupled to the node VY. The drain of the transistor MN 42  is coupled to the node VX. 
     As described above, the operational amplifier  1  according to the second embodiment includes the differential circuitry  10 , which includes the differential circuit  41  formed of, for example, a p-type MOSFET, and not including a differential circuit formed of an n-type MOSFET. The other configuration of the operational amplifier  1  according to the second embodiment is similar to that of the operational amplifier  1  according to the first embodiment, and detailed descriptions thereof will be omitted. 
     [2-2] Advantageous Effects of Second Embodiment 
     In the above-described operational amplifier  1  according to the second embodiment, the differential circuitry  10  differentially amplifies the signal input to the terminal T 3  and the signal input to the terminal T 4 , and outputs the differentially amplified signals to the nodes VX and VY. The output circuitry  20  operates in a manner similar to the first embodiment. That is, the output circuitry  20  in the second embodiment operates in such a manner that the voltage of the node VX and the voltage of the node VY are equal. In the operational amplifier  1  according to the second embodiment, it is possible to suppress the offset voltage and to achieve a high CMRR, as in the first embodiment, even though the operable input range is equal to or greater than the power-supply voltage VSS, and less than the power-supply voltage VDD, making it difficult to perform a rail-to-rail input operation. 
     [3] Other Modifications 
     Various modifications may be made to the circuit configuration of the operational amplifier  1  according to the above-described embodiments. For example, in each of the operational amplifiers  1  according to the first and second embodiments, the transistors may be switched between the n-type and the p-type. In other words, in each of the operational amplifiers  1  according to the first and second embodiments, the transistors described as being p-type MOSFETs may be replaced by n-type MOSFETs, and those described as being n-type MOSFETs may be replaced by p-type MOSFETs. 
     When such switching of the transistors between the n-type and the p-type is adopted in the operational amplifier  1 , the coupling direction of the constant current source, the power-supply voltage, etc., may also be suitably changed. Specifically, when the transistors are switched between the n-type and the p-type in the operational amplifier  1  according to the first embodiment, the configuration is changed in such a manner that the power line PW is grounded, the power-supply voltage VDD is applied to the power line GW, and the constant current source CS 1  allows a current to flow from the node N 1  to the power line PW. When the transistors are switched between the n-type and the p-type in the operational amplifier  1  according to the second embodiment, the configuration is changed in such a manner that the power line PW is grounded, the power-supply voltage VDD is applied to the power line GW, and the constant current source CS 3  allows a current to flow from the other end of each of the transistors MP 41  and MP 42  to the power line PW. 
     In the operational amplifier  1  according to the first embodiment, when the transistors in the output circuitry  20  are switched between the n-type and the p-type, the current mirror coupling in the folded cascode circuit  14  of the differential circuitry  10  is changed from the n-type to the p-type. Specifically, the gates of the transistors MN 17  and MN 18  are applied with the voltage V 5 , instead of being coupled to the drain of the transistor MN 15 . In addition, the gates of the transistors MP 14  and MP 15  are coupled to the node VX, instead of being applied with the voltage V 4 . In the operational amplifier  1  according to the first embodiment, the circuit configuration of the differential circuitry  10  may be modified in the above-described manner. 
     In the present specification, “capable of rail-to-rail input and output operation” means that the operational amplifier  1 , which operates on two power-supply rails (e.g., VDD and VSS), is capable of inputting and outputting voltages ranging from a voltage substantially equal to VDD to a voltage substantially equal to VSS. Such an operation of the operational amplifier  1  may be rephrased as “permitting a full-swing input and output operation”. 
     In the above-described embodiments, a case has been described, as an example, where the operational amplifier  1  is used as a voltage follower circuit; however, the application of the operational amplifier  1  is not limited thereto. The operational amplifier  1  may be used, for example, as a non-inverting amplification circuit having a voltage gain, or alternatively as an inverting amplifier circuit, or even as a filter circuit having frequency characteristics. The operational amplifier  1  according to the above-described embodiments is capable of suppressing the offset voltage in various applications. 
     In the present embodiment, the “size” of a transistor means, for example, the gate length and the gate width of the transistor. When the same voltage is applied between the gate and the source of each of a plurality of transistors equal in size, the current-driving capabilities of the transistors are equal. When the same amount of current flows between the drain and the source of each of a plurality of transistors equal in size, the gate-to-source voltages of the transistors are equal. Even when the manufactured transistors have slightly different sizes due to variations in processing, etc., such sizes can be expressed as being substantially equal, and their current drivabilities can be expressed as being substantially equal. When substantially the same amounts of current flow through a plurality of transistors substantially equal in size, the gate-to-source voltages of the transistors can be expressed as being substantially equal. 
     The operational amplifier according to the embodiments may be incorporated into various devices. For example, the operational amplifier may be incorporated into personal computers, mobile communication devices such as mobile phones, Internet of things (IoT) sensors, household electrical goods, etc. 
     In the present specification, the term “couple” refers to electrical coupling, and does not exclude intervention of, for example, another element. In addition, “electrical coupling” may be performed via an insulator, if the same operation is ensured thereby. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.