Patent Publication Number: US-8525568-B2

Title: Clock generation circuit

Description:
BACKGROUND OF THE PRESENT INVENTION 
     1. Field of Invention 
     The present invention relates to the field of integrated circuit, and more particularly to a clock generation circuit. 
     2. Description of Related Arts 
     A clock generation circuit is an important part of the integrated circuit design. Usually, off-chip crystals or crystal oscillators are used in integrated circuits to provide accurate clock sources. But the system cost is increased at the same time. Therefore, it is very necessary to design a precious on-chip clock generation circuit. 
     In traditional on-chip clock generation circuits, a ring oscillator capable of being compensated by process, voltage, temperature, etc. or a RC oscillator is often adopted for generating an accurate clock cycle. However, the ring oscillator capable of being compensated by process, voltage, temperature is more complex to be designed, and more difficult to be technically implemented technical. On the other hand, although it is simple to design a RC oscillator, influenced by the process variations among resistor and capacitor, the accuracy of the clock frequency is limited. 
     SUMMARY OF THE PRESENT INVENTION 
     An object of the present invention is to provide a clock generation circuit which has simple structure, and is capable of generating high-precision clock frequency. 
     Accordingly, in order to accomplish the above object, the present invention provides a clock generation circuit comprising a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator, wherein the RS trigger outputs clock signals to the input control terminal of the first demux circuit and the input control terminal of the second demux circuit, when the first demux circuit is enabled, the capacitor is charged by the second current source, and when the second demux circuit is enabled, the capacitor is discharged by the second current source. 
     Compared with existing technologies, the clock generation circuit of the present invention has advantages of simple structure, small process variation, and low cost. Also, the clock cycle generated by the clock generation circuit of the present invention is only relative to capacitance and current ratio. Therefore, the present invention eliminates the effect of resistors so that the accuracy of the clock is able to be improved with maximum possibility 
     These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a clock generation circuit according to a first preferred embodiment of the present invention. 
         FIG. 2  is a circuit diagram of the clock generation circuit according to the above first preferred embodiment of the present invention. 
         FIG. 3  is a circuit diagram of the clock generation circuit according to a second preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to  FIG. 1  of the drawings, a schematic diagram of a clock generation circuit according to a first preferred embodiment of the present invention is illustrated, in which the clock generation circuit comprises a first current source I 1 , a second current source I 2 , a resistor R connected to the first current source I 1 , a capacitor C, a first comparator CMP 1  connected to the capacitor C, a second comparator CMP 2  connected to the capacitor C, a RS trigger connected both to the first comparator CMP  1  and the second comparator CMP 2 , and a first demux circuit and a second demux circuit both connected to the second current source I 2 . 
     According to the first embodiment, the first current source I 1  comprises a first power supply terminal and a first ground terminal, wherein the first current source I 1  is proportional to 
               1     R   2       ,         
and given
 
               I   ⁢           ⁢   1     =         K   1       R   2       .           
The second current source I 2  comprises a second power supply terminal and a second ground terminal, wherein the second current source I 2  is proportional to
 
               1   R     ,         
and given
 
               I   ⁢           ⁢   2     =         K   2     R     .           
The first power supply terminal and the second power supply terminal are both connected to a power supply VD, and the first ground terminal and the second ground terminal are both connected to a ground VS, wherein the first demux circuit is served as a first switch T 1 , and the second demux circuit is served as a second switch T 2 . Here, K 1  and K 2  are both proportion coefficient.
 
     A first side of the resistor R is connected to the first power supply terminal and the non-inverting input terminal of the first comparator CMP 1 , and a second side of the resistor R is connected to the first ground terminal and the reversed input terminal of the second comparator CMP 2 . One side of the first switch T 1  is connected to the second power supply terminal, and the other side of the first switch T 1  is connected to one side of the capacitor C and the reversed input terminal of the first comparator CMP 1 . One side of the second switch T 2  is connected to the second ground terminal, and the other side of the second switch T 2  is connected to one side of the capacitor C and the non-inverting input terminal of the second comparator CMP 2 . The output terminal of the first comparator CMP 1  is connected to the trigger input terminal SB of the RS trigger, and the output terminal of the second comparator CMP 2  is connected to the reset input terminal RB of the RS trigger, wherein the output terminal O of the RS trigger outputs clock signals CLK which are input to the input control terminal of the first switch T 1  and the input control terminal of the second switch T 2 . 
     The working principle of the clock generation circuit mentioned above is described as follows. When the first current source I 1  flows through the resistor R, there is a voltage difference V 1 −V 2  generated between a voltage V 1  applied on the first side of the resistor R and a voltage V 2  applied on the second side of the resistor R, wherein the voltage V 1  and voltage V 2  are respectively the input signal of the non-inverting input terminal of the first comparator CMP 1  and the input signal of the reversed input terminal of the second comparator CMP 2 . When the first demux circuit is enabled, the capacitor C is charged by the second current source I 2 , and when the second demux circuit is enabled, the capacitor C is discharged by the second current source I 2 . The capacitor voltage of the capacitor C is marked as V 0 . Given V 0 &gt;V 1 &gt;V 2 , the first comparator CMP 1  outputs a low level signal, and the second comparator CMP 2  outputs a high level signal. During this period, the clock signal CLK of the RS trigger enables the second demux circuit, and the capacitor C is discharged by the second current source I 2  and the capacitor voltage V 0  starts to get smaller. Until V 2 &lt;V 0 &lt;V 1 , the first comparator CMP 1  and the second comparator CMP 2  both output a low level signal. During this period, keeping the output of the RS trigger uncharged and the second demux circuit enabled, the capacitor C is discharged by the second current source I 2  and the capacitor voltage V 0  continues to get smaller. Until V 0 &lt;V 2 &lt;V 1 , the first comparator CMP 1  outputs a high level signal, and the second comparator CMP 2  outputs a low level signal. During this period, the clock signal CLK of the RS trigger enables the first demux circuit, and the capacitor C is charged by the second current source I 2  and the capacitor voltage V 0  starts to get bigger. Until V 2 &lt;V 0 &lt;V 1 , the first comparator CMP 1  and the second comparator CMP 2  both output a low level signal. During this period, keeping the output of the RS trigger uncharged and the first demux circuit enabled, the capacitor C is charged by the second current source I 2  and the capacitor voltage V 0  continues to get bigger. Until V 0 &gt;V 1 &gt;V 2 , the first comparator CMP 1  outputs a low level signal, and the second comparator CMP 2  outputs a high level signal. During this period, the clock signal CLK of the RS trigger enables the second demux circuit, and the capacitor C is discharged by the second current source I 2  and the capacitor voltage V 0  starts to get smaller, therefore, an entire clock cycle is completed. 
     Taking no account of the delay of the comparators CMP 1 , CMP 2  and the RS trigger, the formulas of the clock cycle are described as follows. 
     The voltage difference generated by the first current source I 1  flowing through the resistor R is 
     
       
         
           
             
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             = 
             
               
                 
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     The charge and discharge rate of the capacitor C charged/discharged by the second current source I 2  is 
     
       
         
           
             SR 
             = 
             
               
                 
                   
                     K 
                     2 
                   
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                     R 
                   
                 
                 C 
               
               = 
               
                 
                   
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                     2 
                   
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                 . 
               
             
           
         
       
     
     The entire charge time or the entire discharge time of the capacitor C charged/discharged by the second current source I 2  is 
     
       
         
           
             
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               ⁢ 
               
                   
               
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                       1 
                     
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                         1 
                       
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                   . 
                 
               
             
           
         
       
     
     The entire clock cycle is 
     
       
         
           
             T 
             = 
             
               
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                 ⁢ 
                 
                     
                 
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                 ⁢ 
                 
                     
                 
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                 . 
               
             
           
         
       
     
     From the formulas above, it is clearly that the clock cycle generated by the clock generation circuit of the present invention is only relative to the capacitance of the capacitor C and the ratio of the first current source I 1  to the second current source I 2 . That is, the present invention eliminates the effect of the resistor R so that the accuracy of the clock is able to be improved with maximum possibility. 
     Referring to  FIG. 2  of the drawings, a circuit diagram of the clock generation circuit according to the first preferred embodiment of the present invention is illustrated, in which the clock generation circuit comprises a first field effect transistor (FET) MP 1 , a second FET MP 2 , a third FET MP 3 , a fourth FET MP 4 , a fifth FET MP 5 , a sixth FET MP 6 , a seventh FET MP 7 , an eighth FET MP 8 , a ninth FET MN 1 , a tenth FET MN 2 , an eleventh FET MN 3 , a twelfth FET MN 4 , a thirteenth FET MN 5 , a fourteenth FET MN 6 , a fifteenth FET MN 7 , a sixteenth FET MN 8 , a first resistor R 1 , a second resistor R 2 , the resistor R, the capacitor C, the first comparator CMP 1 , the second comparator CMP 2 , and the RS trigger. Here, the first FET MP 1 , the second FET MP 2 , the ninth FET MN 1 , the tenth FET MN 2  and the first resistor R 1  are connected together to constitute the first current source I 1 . And the fourth FET MP 4 , the fifth FET MP 5 , the sixth FET MP 6 , the twelfth FET MN 4 , the thirteenth FET MN 5 , the fourteenth FET MN 6  and the second resistor R 2  are connected together to constitute the second current source I 2 . The first demux circuit comprises the eighth FET MP 8 , and the second demux circuit comprises the sixteenth FET MN 8 . Other components constitute the external bias circuits. 
     According to the first preferred embodiment, the first FET MP 1 , the second FET MP 2 , the third FET MP 3 , the fourth FET MP 4 , the fifth FET MP 5 , the sixth FET MP 6 , the seventh FET MP 7  and the eighth FET MP 8  are P-type metal oxide semiconductor (PMOS); the ninth FET MN 1 , the tenth FET MN 2 , the eleventh FET MN 3 , the twelfth FET MN 4 , the thirteenth FET MN 5 , the fourteenth FET MN 6 , the fifteenth FET MN 7  and the sixteenth FET MN 8  are N-type metal oxide semiconductor (NMOS). In other embodiments or alternatives, the FETs can be replaced by the other switching components or circuits which are capable of achieving the same function as required. 
     The connection relations of the clock generation circuit according to the first preferred embodiment are described as follows. The gate electrode of the first FET MP 1 , the gate electrode and the drain electrode of the second FET MP 2 , and the gate electrode of the third FET MP 3  are all connected to the drain electrode of the tenth FET MN 2 ; the source electrode and the bulk electrode of the first FET MP 1 , the source electrode and the bulk electrode of the second FET MP 2 , the source electrode and the bulk electrode of the third FET MP 3 , the source electrode and the bulk electrode of the fourth FET MP 4 , the source electrode and the bulk electrode of the fifth FET MP 5 , the source electrode and the bulk electrode of the sixth FET MP 6 , the source electrode and the bulk electrode of the seventh FET MP 7 , the source electrode and the bulk electrode of the eighth FET MP 8  are all connected to a power supply VD; the drain electrode of the first FET MP 1  is connected to the drain electrode and the gate electrode of the ninth FET MN 1 , and the gate electrode of the tenth FET MN 2 . The drain electrode of the third FET MP 3  is connected to the gate electrode and the drain electrode of the eleventh FET MN 2  via the resistor R. The gate electrode of the fourth FET MP 4 , the gate electrode and the drain electrode of the fifth FET MP 5 , the gate electrode of the sixth FET MP 6  and the gate electrode of the seventh FET MP 7  are all connected to the drain electrode of the thirteenth FET MN 5 ; the drain electrode of the fourth FET MP 4  is connected to the drain electrode and the gate electrode of the twelfth FET MN 4 , and the gate electrode of the thirteenth FET MN 5 . The drain electrode of the sixth FET MP 6  is connected to the gate electrode and the drain electrode of the fourteenth FET MN 6 , and the gate electrode of the fifteenth FET MN 7 . The drain electrode of the seventh FET MP 7  is connected to the source electrode of the eighth FET MP 8 . The gate electrode of the eighth FET MP 8  and the gate electrode of the sixteenth FET MN 8  are both connected to the output terminal O of the RS trigger; the drain electrode of the eighth FET MP 8  and the drain electrode of the sixteenth FET MN 8  are both connected to the reversed input terminal of the first comparator CMP 1  and the non-inverting input terminal of the second comparator CMP 2 , and are also connected through the capacitor C to ground VS. The source electrode and the bulk electrode of the ninth FET MN 1 , the bulk electrode of the tenth FET MN 2 , the source electrode and the bulk electrode of the eleventh FET MN 3 , the source electrode and the bulk electrode of the twelfth FET MN 4 , the bulk electrode of the thirteenth FET MN 5 , the source electrode and the bulk electrode of the fourteenth FET MN 6 , the source electrode and the bulk electrode of the fifteenth FET MN 7 , and the bulk electrode of the sixteenth FET MN 8  are all connected to ground VS. The source electrode of the tenth FET MN 2  is connected through the first resistor R 1  to ground VS; the source electrode of the thirteenth FET MN 5  is connected through the second resistor R 2  to ground VS. The drain electrode of the fifteenth FET MN 7  is connected to the source electrode of the sixteenth FET MN 8 . 
     The working principle of the clock generation circuit according to the first preferred embodiment is described as follows. The ninth FET MN 1  and the tenth FET MN 2  operate in saturation regions, and have same width/length ratio A 1 . The first FET MP 1 , the second FET MP 2  and the third FET MP 3  constitute a current amplifier, whose amplification factor is parameter determined by design, and here is assumed to be 1. Ignoring the body effects on PMOS and NMOS, according to the present working state of the clock generation circuit, we can see that the current flowing through the resistor R is 
     
       
         
           
             
               I 
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             = 
             
               
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                     μ 
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                         ox 
                       
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     So, the voltage difference between the two sides of the resistor R is
 
Δ V=V 1− V 2= I   1   R.  
 
     The twelfth FET MN 4  and the thirteenth FET MN 5  operate in subthreshold regions, and have same width/length ratio A 2 . The fourth FET MP 4 , the fifth FET MP 5 , the sixth FET MP 6  and the seventh FET MP 7  constitute a current amplifier, whose amplification factors is parameter determined by design, and here is assumed to be 1. Ignoring the body effects on PMOS and NMOS, according to the present working state of the clock generation circuit, we can see that the charge current and the discharge current of the capacitor C is 
     
       
         
           
             
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     So, the entire clock cycle is 
     
       
         
           
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     Here, μ n  denotes the electron mobility of NMOS; C ox  denotes the Cox of the capacitor C; 
               (     W   L     )     1         
denotes the width/length ratio of the ninth FET MN 1 ; ξ denotes the non-ideality factor when the transistors operating in subthreshold regions; V T  denotes thermodynamic constants. If the resistors as mentioned above are same in type, the effects generated by production process and temperature among different resistors can be canceled each other out. The temperature coefficient of V T  is a positive value, and the temperature coefficient of μ n  is a negative value, so that the temperature characteristics can be compensated. Even in standard CMOS process, the capacitor C can be ordinary MOS or N-well NMOS, and the capacitance of the capacitor is in approximate direct proportion to W*L*C ox . Hence, the C ox  in denominator is canceled so as to eliminate process variation among different transistors. In summary, the clock cycle generated by the clock generation circuit according to the first preferred embodiment has good temperature coefficient, small process variation, simply design, and low cost.
 
     Referring to  FIG. 3  of the drawings, a circuit diagram of the clock generation circuit according to a second preferred embodiment of the present invention is illustrated, in which the clock generation circuit comprises a first field effect transistor (FET) MP 1 , a second FET MP 2 , a third FET MP 3 , a fourth FET MP 4 , a fifth FET MP 5 , a sixth FET MP 6 , a seventh FET MP 7 , an eighth FET MP 8 , a ninth FET MP 9 , a tenth FET MP 10 , an eleventh FET MP 11 , a twelfth FET MN 1 , a thirteenth FET MN 2 , a fourteenth FET MN 3 , a fifteenth FET MN 4 , a sixteenth FET MN 5 , a seventeenth FET MN 6 , an eighteenth FET MN 7 , a nineteenth FET MN 8 , a first triode PNP 1 , a second triode PNP 2 , a third triode PNP 3 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a fourth resistor R 4 , the resistor R, the capacitor C, the first comparator CMP 1 , the second comparator CMP 2 , an operation amplifier AMP 1 , and the RS trigger. Here, the first FET MP 1 , the second FET MP 2 , the twelfth FET MN 1 , the thirteenth FET MN 3  and the first resistor R 1  are connected together to constitute the first current source I 1 . And the fourth FET MP 4 , the fifth FET MP 5 , the sixth FET MP 6 , the ninth FET MP 9 , the eleventh FET MP 11 , the fifteenth FET MN 4 , the sixteenth FET MN 5 , the second resistor R 2 , the third resistor R 3 , the fourth resistor R 4 , the first triode PNP 1 , the second triode PNP 2 , the third triode PNP 3 , and the operation amplifier AMP 1  are connected together to constitute the second current source I 2 . The first demux circuit comprises the tenth FET MP 10 , and the second demux circuit comprises the nineteenth FET MN 8 . Other components constitute the external bias circuits. 
     According to the second preferred embodiment, the first FET MP 1 , the second FET MP 2 , the third FET MP 3 , the fourth FET MP 4 , the fifth FET MP 5 , the sixth FET MP 6 , the seventh FET MP 7 , the eighth FET MP 8 , the ninth FET MP 9 , the tenth FET MP 10 , and the eleventh FET MP 11  are P-type metal oxide semiconductor (PMOS); the twelfth FET MN 1 , the thirteenth FET MN 2 , the fourteenth FET MN 3 , the fifteenth FET MN 4 , the sixteenth FET MN 5 , the seventeenth FET MN 6 , the eighteenth FET MN 7 , and the nineteenth FET MN 8  are N-type metal oxide semiconductor (NMOS). In other embodiments or alternatives, the FETs can be replaced by the other switching components or circuits which are capable of achieving the same function as required. 
     The connection relations of the clock generation circuit according to the second preferred embodiment are described as follows. The gate electrode of the first FET MP 1 , the gate electrode and the drain electrode of the second FET MP 2 , and the gate electrode of the third FET MP 3  are all connected to the drain electrode of the tenth FET MN 2 ; the source electrode and the bulk electrode of the first FET MP 1 , the source electrode and the bulk electrode of the second FET MP 2 , the source electrode and the bulk electrode of the third FET MP 3 , the source electrode and the bulk electrode of the fourth FET MP 4 , the source electrode and the bulk electrode of the fifth FET MP 5 , the source electrode and the bulk electrode of the sixth FET MP 6 , the source electrode and the bulk electrode of the seventh FET MP 7 , the bulk electrode of the eighth FET MP 8 , the source electrode and the bulk electrode of the ninth FET MP 9 , the source electrode and the bulk electrode of the tenth FET MP 10 , the bulk electrode of the eleventh FET MP 11  are all connected to a power supply VD; the drain electrode of the first FET MP 1  is connected to the drain electrode and the gate electrode of the twelfth FET MN 1 , the gate electrode of the thirteenth FET MN 2 . The drain electrode of the third FET MP 3  is connected through the resistor R to the gate electrode and the drain electrode of the fourteenth FET MN 3 . The gate electrode of the fourth FET MP 4 , the gate electrode and the drain electrode of the fifth FET MP 5 , and the gate electrode of the sixth FET MP 6  are all connected to the drain electrode of the sixteenth FET MN 5 ; the drain electrode of the fourth FET MP 4  is connected to the drain electrode and the gate electrode of the fifteenth FET MN 4 , and the gate electrode of the sixteenth FET MN 5 . The drain electrode of the sixth FET MP 6  is connected to the non-inverting input terminal of the operation amplifier AMP 1 , and is also connected through the third resistor R 3  to the emitter of the third triode PNP 3 . The gate electrode and the drain electrode of the ninth FET MP 9 , the gate electrode of the tenth FET MP 10 , the gate electrode of the seventh FET MP 7 , and the source electrode of the eleventh FET MP 11  are connected together. The drain electrode of the tenth FET MP 10  is connected to the gate electrode and the drain electrode of the seventeenth FET MN 6 , and the gate electrode of the eighteenth FET MN 7 . The drain electrode of the seventeenth FET MP 7  is connected to the source electrode of the eighth FET MP 8 . The gate electrode of the eighth FET MP 8 , the gate electrode of the nineteenth FET MN 8  are both connected to the output terminal O of the RS trigger; the drain electrode of the eighth FET MP 8 , the drain electrode of the nineteenth FET MN 8  are both connected to the reversed input terminal of the first comparator CMP 1  and the reversed input terminal of the second comparator CMP 2 , and also connected through the capacitor C to ground VS. The source electrode and the bulk electrode of the twelfth FET MN 1 , the bulk electrode of the thirteenth FET MN 2 , the source electrode and the bulk electrode of the fourteenth FET MN 3 , the bulk electrode of the fifteenth FET MN 4 , the bulk electrode of the sixteenth FET MN 5 , the source electrode and the bulk electrode of the seventeenth FET MN 6 , the source electrode and the bulk electrode of the eighteenth FET MN 7 , the bulk electrode of the nineteenth FET MN 8 , the base and the collector of the first triode PNP 1 , the base and the collector of the second triode PNP 2 , and the base and the collector of the third triode PNP 3  are all connected to the power supply VD. The source electrode of the thirteenth FET MN 2  is connected through the first resistor R 1  to the power supply VD. The source electrode of the fifteenth FET MN 4  is connected to the emitter of the first triode PNP 1 . The source electrode of the sixteenth FET MN 5  is connected through the second resistor R 2  to the emitter of the second triode PNP 2 . The drain electrode of the eighteenth FET MN 7  is connected to the source electrode of the nineteenth FET MN 8 . 
     The working principle of the clock generation circuit according to the second preferred embodiment is described as follows. The twelfth FET MN 1  and the thirteenth FET MN 2  operate in saturation regions, and have same width/length ratio B 1 . The first FET MP 1 , the second FET MP 2  and the third FET MP 3  constitute a current amplifier, whose amplification factor is parameter determined by design, and here is assumed to be 1. Ignoring the body effects on PMOS and NMOS, according to the present working state of the clock generation circuit, we can see that the current flowing through the resistor R is 
     
       
         
           
             
               I 
               1 
             
             = 
             
               
                 2 
                 
                   
                     μ 
                     n 
                   
                   ⁢ 
                   
                     
                       
                         C 
                         ox 
                       
                       ⁡ 
                       
                         ( 
                         
                           W 
                           L 
                         
                         ) 
                       
                     
                     1 
                   
                 
               
               * 
               
                 1 
                 
                   R 
                   1 
                   2 
                 
               
               * 
               
                 
                   
                     ( 
                     
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                       - 
                       
                         1 
                         
                           
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                             ⁢ 
                             
                                 
                             
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                             1 
                           
                         
                       
                     
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                   2 
                 
                 . 
               
             
           
         
       
     
     So, the voltage difference between the two sides of the resistor R is
 
Δ V=V 1− V 2= I   1   R.  
 
     The fifteenth FET MN 4 , the sixteenth FET MN 5 , the fourth FET MP 4 , and the fifth FET MP 5  all operate in saturation regions, and have same width/length ratio  1 . The area ratio of the first triode PNP 1  and the second triode PNP 2  is a given B 2 . 
     So, a reference voltage between the high side of the third resistor R 3  and the non-inverting input terminal of the operation amplifier AMP 1  is 
                 V   3     =       V   be     +         R   3       R   2       ⁢     V   T     ⁢   ln   ⁢           ⁢   B   ⁢           ⁢   2         ,         
the second current source is
 
                 I   2     =         V   3       R   4       =         V   be     +         R   3       R   2       ⁢     V   T     ⁢   ln   ⁢           ⁢   B   ⁢           ⁢   2         R   4           ,         
so, the entire clock cycle is
 
     
       
         
           
             T 
             = 
             
               
                 2 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 Δ 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 T 
               
               = 
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     V 
                   
                   
                     
                       I 
                       3 
                     
                     C 
                   
                 
                 = 
                 
                   
                     
                       2 
                       
                         
                           μ 
                           n 
                         
                         ⁢ 
                         
                           
                             
                               C 
                               ox 
                             
                             ⁡ 
                             
                               ( 
                               
                                 W 
                                 L 
                               
                               ) 
                             
                           
                           1 
                         
                       
                     
                     * 
                     
                       1 
                       
                         R 
                         1 
                         2 
                       
                     
                     * 
                     
                       
                         ( 
                         
                           1 
                           - 
                           
                             1 
                             
                               
                                 B 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                           
                         
                         ) 
                       
                       2 
                     
                     * 
                     R 
                     * 
                     C 
                     * 
                     
                       
                         R 
                         4 
                       
                       
                         
                           V 
                           be 
                         
                         + 
                         
                           
                             
                               R 
                               3 
                             
                             
                               R 
                               2 
                             
                           
                           ⁢ 
                           
                             V 
                             T 
                           
                           ⁢ 
                           ln 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           B 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                   = 
                   
                     
                       2 
                       
                         
                           μ 
                           n 
                         
                         ⁢ 
                         
                           
                             
                               C 
                               ox 
                             
                             ⁡ 
                             
                               ( 
                               
                                 W 
                                 L 
                               
                               ) 
                             
                           
                           1 
                         
                         ⁢ 
                         
                           ( 
                           
                             
                               V 
                               be 
                             
                             + 
                             
                               
                                 
                                   R 
                                   3 
                                 
                                 
                                   R 
                                   2 
                                 
                               
                               ⁢ 
                               
                                 V 
                                 T 
                               
                               ⁢ 
                               ln 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               B 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                           
                           ) 
                         
                       
                     
                     * 
                     
                       
                         ( 
                         
                           1 
                           - 
                           
                             1 
                             
                               
                                 B 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                           
                         
                         ) 
                       
                       2 
                     
                     * 
                     
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           R 
                           4 
                         
                       
                       
                         R 
                         1 
                         2 
                       
                     
                     * 
                     C 
                   
                 
               
             
           
         
       
     
     Here, μ n  denotes the electron mobility of NMOS; C ox  denotes the Cox of the capacitor C; 
               (     W   L     )     1         
denotes the width/length ratio of the twelfth FET MN 1 ; ξ denotes the non-ideality factor when the transistors operating in subthreshold regions; V T  denotes thermodynamic constants. The temperature coefficient of
 
               V   be     +         R   3       R   2       ⁢     V   T     ⁢   ln   ⁢           ⁢   B   ⁢           ⁢   2           
as mentioned above is adjustable, therefore, the negative temperature characteristic of the μ n  can be compensated by adjusting the temperature coefficient of
 
               V   be     +         R   3       R   2       ⁢     V   T     ⁢   ln   ⁢           ⁢   B   ⁢           ⁢   2.           
The resistor R, the first resistor R 1 , the second resistor R 2 , the third resistor R 3  and the fourth resistor R 4  are same in type, so that the effects generated by production process and temperature among different resistors can be canceled each other out. Even in standard CMOS process, the capacitor C can be ordinary MOS or N-well NMOS, and the capacitance of the capacitor is in approximate direct proportion to W*L*C ox . Hence, the C ox  in denominator is canceled so as to eliminate process variation among different transistors. In summary, the clock cycle generated by the clock generation circuit according to the second preferred embodiment has good temperature coefficient, small process variation, simply design, and low cost.
 
     The clock generation circuit provided by the present invention has advantages of simple structure, small process variation, and low cost. Also, the clock cycle generated by the clock generation circuit of the present invention is only relative to the capacitance of the capacitor C and the ratio of the first current source I 1  to the second current source I 2 . That is, the present invention eliminates the effect of the resistors so that the accuracy of the clock is able to be improved with maximum possibility. 
     One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting. 
     It will thus be seen that the objects of the present invention have been fully and effectively accomplished. Its embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.