Patent Publication Number: US-7917886-B2

Title: Automatic system and method for providing PCB layout

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to automatic systems and methods for providing printed circuit board (PCB) layout, and particularly to an automatic system and a method for providing PCB layout for high-speed signals. 
     2. Description of Related Art 
     Sizes of PCBs and chips mounted on the PCBs are continuing to be miniaturized, while frequencies of electronic signals transmitted on the PCBs are being increased. Thus, high-speed or high-frequency signals transmitted between chips via traces and holes on a PCB are liable to generate unwanted reflections. The high-speed or high-frequency signals may also be prone to cross-talk and electromagnetic interference. To eliminate interference, technicians may often manually calculate values of the interference of each layer of the PCB and choose a layout layer for high-speed signals having the least interference. However, if lots of high-speed signals are to be provided with a layout layer, manually dealing with the layout layer may become too difficult for the technicians, which makes PCB layout inaccurate and inefficient. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an exemplary embodiment of an automatic system for providing PCB layout. 
         FIG. 2  is a schematic view of parts of layers of an exemplary PCB, showing certain components including traces of the PCB. 
         FIG. 3  is a flowchart of an exemplary embodiment of an automatic method for providing PCB layout. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS. 1 and 2 , an exemplary embodiment of an automatic system  10  is disclosed for providing printed circuit board (PCB) layout for producing a PCB capable of transmitting high-speed signals with little or no interference. The automatic system  10  includes an input device  100 , a data processing device  200 , and a storage device  300 . In one embodiment, the input device  100  can be a keyboard or a mouse, etc., and the data processing device  200  can be a computer, a server, or a microprocessor, etc. The data processing device  200  includes an invoking module  202 , a calculating module  204 , a determining module  206 , and an output module  208 . 
     The input device  100  is to receive input information including a transmission bit rate, such as 6.4 Gb/s, of a high-speed signal to be transmitted in the PCB, and relative permittivity, such as 4.2, of the PCB. The input device  100  also transmits the transmission bit rate and the relative permittivity to the data processing device  200 . 
     The storage device  300  includes a database which connects to the data processing device  200  via a connection. In one embodiment, the connection is a database connectivity, such as open database connectivity (ODBC) or java database connectivity (JDBC). The database is to store information of a plurality of PCBs. In one embodiment, information of the PCBs may include names or thicknesses of each layer of each PCB. For example, as shown in table 1, names, from a top layer to a bottom layer, of the PCB may be S 1 , C 1  . . . S 2 , and thicknesses, from the top layer to the bottom layer, may be 1 mil, 2.3 mil . . . 1 mil. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Information of PCB 
               
            
           
           
               
               
            
               
                   
                 Layer name 
               
            
           
           
               
               
               
               
               
               
               
               
               
               
               
               
               
               
            
               
                   
                 S1 
                 C1 
                 F1 
                 C2 
                 F2 
                 C3 
                 F3 
                 C4 
                 F4 
                 C5 
                 F5 
                 C6 
                 S2 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
               
               
               
               
               
            
               
                 Thickness (mil) 
                 1 
                 2.3 
                 3.7 
                 1.35 
                 4 
                 1.35 
                 13 
                 2.7 
                 4 
                 13 
                 3.7 
                 2.3 
                 1 
               
               
                   
               
            
           
         
       
     
     The invoking module  202  is to read the information of a corresponding PCB from the database of the storage device  300 , according to the transmission bit rate of the high-speed signal and the relative permittivity of the PCB input through the input device  100 . 
     The calculating module  204  is to calculate an actual length of a via stub of each layer of the PCB according to the information of the PCB. A via stub is a part of a through via and functions as a short transmission line for the high-speed signal, and can be a major factor in whether or not resonance reflection has an impact on signal integrity. The calculating module  204  also calculates an ideal length of the via stub of the PCB, according to a preset formula for reducing resonance reflection of the high-speed signal. In this embodiment, the actual length of the via stub of each layer equals the thickness of the PCB minus the thicknesses of high-speed signal layout layers through which a high-speed signal is transmitted of the PCB combined. For example, in a ten-layer PCB, an actual length of a via stub of a third layer equals the thickness of the fourth to tenth layers combined. 
     As shown in  FIG. 2 , if a high-speed signal is transmitted along a trace  24  via layers  20  and  22  through a through via  21  of a PCB, a thickness of high-speed signal layout layers that the high-speed signal passes through is L 1 , and an actual length of a via stub of the layer  22  is L 2 . As shown in table 1, the actual length of the via stub of the layer C 5  is F 5 +C 6 +S 2 =3.7+2.3+1=7 mil. If a length of the via stub of a high-sp signal layout layer of the PCB is L, a method for calculating the ideal length L MAX  of the via stub of the PCB is as follows. To reduce the resonance reflection during the high-speed signal being transmitted in the through via, the following formulas need to be satisfied 
               L   =         1   4     ⁢   λ     =       C     4   ⁢       ɛ   r       ×     f   res         =         2.95275         ɛ   r       ×     f   res         ⁢           ⁢   and   ⁢           ⁢     f   res       ≥     10   ×   f             ,         
that is
 
                   2.95275         ɛ   r       ×   L       ≥     10   ×       B   ⁢           ⁢   R     2         =     5   ⁢   B   ⁢           ⁢   R       ,     
     ⁢     L   ≤     0.59055         ɛ   r       ×   B   ⁢           ⁢   R         ,     
     ⁢       L   MAX     =     0.59055         ɛ   r       ×   B   ⁢           ⁢   R         ,         
where λ is a wavelength of the high-speed signal, C is the high-speed signal transmission rate, which is taken to equal the speed of light (2.95275*10 8  m/s), ε r  is relative permittivity of the PCB, f res  is a resonant frequency when the high-speed signal transmitted in the via stub, BR is a transmission bit rate of the high-speed signal transmitted in the PCB. For example, if BR=6 Gb/s, and ε r =4, the ideal length L MAX  of the via stub of the PCB equals to 49.2125 mil.
 
     The determining module  206  is to compare the ideal length L MAX  and the actual length of the via stub of each layer of the PCB. If the actual length is less than or equal to the ideal length L MAX  of the via stub of the PCB, this layer can be used as a high-speed signal layout layer. If the actual length is greater than the ideal length L MAX  of the via stub, this layer cannot be used as a high-speed signal layout layer. 
     The output module  208  is to send a result of a comparison between the actual length and the ideal length L MAX  of the determining module  206  to the storage device  300 , the result is stored in the database of the storage device  300 . 
     Referring to  FIG. 3 , an exemplary embodiment of an automatic method using the above mentioned automatic system  10  for providing printed circuit board (PCB) layout for producing a PCB capable of transmitting high-speed signals with little or no interference includes the following steps. 
     In step S 300 , the invoking module  202  of the data processing device  200  reads the information of the PCB from the database of the storage device  300 , according to a transmission bit rate of a high-speed signal and a relative permittivity of the PCB, input through the input device  100 . 
     In step S 302 , the calculating module  204  calculates an actual length of a via stub of each layer according to the information of the PCB, the actual length of the via stub of each layer equals the thickness of the PCB minus the thicknesses of high-speed signal layout layers through which a high-speed signal is transmitted of the PCB combined. 
     In step S 304 , the calculating module  204  calculates an ideal length L MAX  of the via stub of the PCB according to a preset formula 
               L   MAX     =     0.59055         ɛ   r       ×   B   ⁢           ⁢   R             
for reducing resonance reflection of the high-speed signal and the transmission bit rate of the high-speed signal and relative permittivity of the PCB, where ε r  is the relative permittivity of the PCB, and BR is the transmission bit rate of the high-speed signal transmitted in the PCB.
 
     In step S 306 , the determining module  206  sets an initial layer as a current layer, such as the first layer. 
     In step S 308 , the determining module  206  determines whether a number (e.g No. 1) assigned to represent the next layer to be checked is less than or equal to the number of total layers of the PCB, if the assigned number is less than or equal to the number of the total layers of the PCB, the procedure goes to step S 310 , if not, the procedure ends. 
     In step S 310 , the determining module  206  compares the ideal length L MAX  and the actual length of the via stub of the current layer. If the ideal length L MAX  is less than or equal to the actual length of the current layer, the current layer can not be used as a high-speed signal layout layer, the procedure goes to step S 312 . If the ideal length L MAX  is greater than the actual length of the current layer, the current layer can be used as a high-speed signal layout layer, the procedure goes to step S 314 . 
     In step S 312 , the determining module  206  increments the assigned number by one and the procedure returns to step S 308 . 
     In step S 314 , the output module  206  sends a result of the comparison between the actual length and the ideal length L MAX  of the determining module  206  to the storage device  300 , to store the result in the database of the storage device  300 . 
     The automatic system and method can not only automatically choose layout layers for the high-speed signal, but also reduce the resonance reflection of the high-speed signal transmission to ensure transmission quality of the high-speed signal. 
     It is to be understood, however, that even though numerous characteristics and advantages of the embodiments have been set forth in the foregoing description, together with details of the structure and function of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.