Patent Publication Number: US-8970052-B2

Title: Semiconductor device stack with bonding layer and wire retaining member

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS 
     Japan Priority Application 2009-019564, filed Jan. 30, 2009 including the specification, drawings, claims and abstract, is incorporated herein by reference in its entirety. Japan Priority Application 2009-270146, filed Nov. 27, 2009 including the specification, drawings, claims and abstract, is incorporated herein by reference in its entirety. This application is a Divisional of U.S. application Ser. No. 12/687,311, filed Jan. 14, 2010, incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device having a plurality of stacked semiconductor chips and a method of manufacturing the semiconductor device. 
     2. Description of the Related Art 
     In recent years, a multiple chip package (MCP) in which a plurality of semiconductor chips are stacked has attracted attention as a technique to reduce the package area while reducing the manufacturing cost. An MCP in which two semiconductor chips are stacked will be described by way of example. First, the first semiconductor chip is mounted on a package substrate, and electrodes of this semiconductor chip and electrodes on the package substrate are connected to each other by wires. The second semiconductor chip is thereafter mounted on the first semiconductor chip with an adhesive, and electrodes of the second semiconductor chip and electrodes on the package substrate are connected to each other by wires. 
     With the MCP, there is a problem of contact between wires that led out from the electrodes of the semiconductor chip on the lower layer side and the surface of this semiconductor chip. 
     Japanese Patent Laid-Open Nos. 2004-312008, 2008-198909 and 11-135539 disclose means for preventing such an undesirable contact. 
     According to Japanese Patent Laid-Open No. 2004-312008, an insulating supporting structure is provided on the periphery of the semiconductor chip on the lower layer side to prevent undesirable contact between wires and the semiconductor chip. 
     According to Japanese Patent Laid-Open No. 2008-198909, wires from the semiconductor chip on the lower layer side are embedded in a resin interposed between the semiconductor chips in the upper and lower layers. 
     According to Japanese Patent Laid-Open No. 11-135539, wires are sandwiched in a two-layer polyimide tape in a structure that as different from the MCP structure. 
     Recent semiconductor devices are operated at higher speeds and there is a demand for minimizing parasite capacitance of the wire or the like. In particular, MCPs such as those described above are of such a construction that the parasitic capacitance of the wires from the semiconductor chip on the lower layer side can be increased due to passage of the wires between the two semiconductor chips. However, any of Japanese Patent Laid-Open Nos. 2004-312008, 2008-198909 and 11-135539 is not concerned with this point. 
     SUMMARY OF THE INVENTION 
     In one embodiment, there is provided a semiconductor device that includes elements as described below. In the semiconductor device, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads (i.e., electrodes) in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. Further, a retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip. 
     That is, the inventors of the present invention have found that an increase in parasitic capacitance of wires that pass through the space between the first and second semiconductor chips can be limited by positioning the wires generally at the center of the spacing between the first semiconductor chip and the second semiconductor chip in a region including a middle point between bonding pads and a peripheral edge of the first semiconductor chip. In the one embodiment, on the basis of this finding, the wire retaining member, to achieve this effects, is provided on the first semiconductor chip. According to the embodiment, a semiconductor device can be provided in which the parasitic capacitances of the bonding wires from the first semiconductor chip with respect to the upper and lower semiconductor chips are reduced to improve a signal characteristic. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a side sectional view of a semiconductor device according to a first embodiment of the present invention; 
         FIG. 2  is an enlarged sectional view of a bonding pad peripheral portion of the semiconductor chip on the lower layer side shown in  FIG. 1 ; 
         FIG. 3  is a plan view in a state where the semiconductor chip on the upper layer side shown in  FIG. 1  is removed; 
         FIG. 4  is a schematic side sectional view of a semiconductor device in a second embodiment of the present invention; 
         FIG. 5  is a plan view showing a state where the semiconductor chip on the upper layer side shown in  FIG. 1  is removed; 
         FIG. 6  is a schematic side sectional view of a semiconductor device in a third embodiment of the present invention; 
         FIG. 7  is a schematic side sectional view of a semiconductor device in still another embodiment of the present invention; 
         FIG. 8  is a plan view of the first semiconductor chip in the semiconductor device shown in  FIG. 7 ; and 
         FIG. 9  is a side sectional view of a modified example of the semiconductor device in still another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
     Referring to  FIG. 1 , a semiconductor device according to a first exemplary embodiment of the present invention is illustrated as an MCP having two stacked semiconductor chips  20  and  30  (hereinafter referred to simply as “chip”). In the present exemplary embodiment, in particular, each of chips  20  and  30  is a DRAM chip. Chip  20  on the lower layer side is mounted on package substrate  10  with die attached film (DAF)  21 . As shown in  FIG. 3 , chip  20  has bonding pads (electrodes)  28  arranged in two rows in its central region. Each bonding pad  28  is connected to one end of corresponding wire  80 . The other end of wire  80  is connected to an upper surface of corresponding electrode  12  on package substrate  10 . Bump electrodes  11  for mounting and connecting on a mother board such as a printed circuit board are provided on the back surface of package substrate  10 . 
     A pair of retaining members  50  are formed on chip  20  according to one of the features of the present invention, and wires  80  are bonded so as to pass over retaining members  50  as shown in  FIG. 3 . Each retaining member  50  is formed of a resin tape and is provided over a region including middle point  51  between bonding pads  28  of chip  20  and peripheral edge  55 . This is because the amount of deflection of wires  80  is maximized at about middle point  51 , and because reducing the parasitic capacitance or the like of wires  80  requires positioning wires  80  generally at the center of the spacing between two chips  20  and  30 . It is, therefore, preferable to cover the front surface of chip  20  with retaining members  50  as much as possible. However, a smaller size of retaining member  50  may suffice as long as retaining member  50  covers a region including middle point  51 . Briefly speaking, the size of retaining member  50  may be determined depending on the ease of manufacture or the like. Also, retaining members  50  may be provided by being divided so that wires  80  are positioned generally at the center of the spacing between chips  20  and  30  in regions including middle points  51  instead of providing retaining members  50  so as to cover regions including middle points  51 . 
     While use of a resin tape as retaining member  50  has been described, retaining member  50  may be formed by application and setting of a resin paste material. That is, resin-based retaining member  50  may be formed by application of a paste material or by attaching a material in film form. 
     Since wires  80  are positioned generally at the center of the spacing between two chips  20  and  30 , the height of retaining members  50  is set generally equal to the half of spacing H between chips  20  and  30 . As shown in an enlarged state with respect to a portion including bonding pads  28  of chip  20 , chip  20 , as well as chip  30 , has its surface covered with passivation film  29  having openings through which bonding pads  28  are exposed. Therefore spacing H is the distance from the surface of passivation film  29  to the back surface of the semiconductor substrate (silicon substrate) of chip  30  on the upper layer side. Wires  80  are bonded to exposed surfaces of bonding pads  28 . In the present exemplary embodiment, a reverse bonding method is used. That is, gold pieces  85  are provided in advance on bonding pads of chip  20  by using tip portions of gold wires provided as bonding wires. Wires  80  are first bonded to electrodes  12  on package substrate  10 . Wires  80  are thereafter extended over retaining members  50 , bonded to gold pieces  85  and cut. The distance between retaining members  50  and bonding pads  28  or electrodes  20  can be set smaller in this way. A reduction in area is also achieved. The reverse bonding method is also used for wire bonding to chip  30  on the upper layer side. 
     Chip  20  is of a multilayer wiring structure and has wiring  24  and  26  in a plurality of layers and vias  25  and  27  for connection between wirings  24  and  26  and bonding pads  28 . Each via is formed by filling a via hole with a metal or the like. 
     Referring back to  FIG. 1 , it is not necessary to perform bonding of wires  80  so that wires  80  are in contact with retaining members  50 . This is because wires  80  are eventually brought into contact with retaining members  50  due to a load when chip  30  is stacked on chip  20 . 
     That is, DAF  31  is provided on the back surface of chip  30 ; film over wire (FOW)  40  made of resin is applied on DAF  31 ; and chip  30  is stacked on chip  20  so that the gap between retaining members  50  is filled with FOW  40 . At this time, the thicknesses of FOW  40  and DAF  31  are adjusted so that the sum of the thickness of FOW  40  and the thickness of DAF  31  is substantially equal to the thickness (height) of retaining members  50 . As a result, wires  80  are brought into contact with retaining members  50 . Wires  80  can be positioned generally at the center between two chips  20  and  30 . Each of retaining members  50  and FOW  40  is a resin in a broad sense, but the materials of regaining members  50  and FOW  40  are different from each other. 
     Retaining members  60  for retaining wires  90  are provided on chip  30  on the upper layer side in the same way. The material of retaining members  60  is applied in a molten state from above wires  90  after bonding pads  38  of chip  30  and electrodes  12  on the package substrate have been connected by wires  90 . The material is set after being applied. Wires  90  are thereby fixed and retained, with their portions embedded in retaining members  60 . 
     Finally, a resin mold  70  is formed around two stacked chips  20  and  30 , thereby completing semiconductor device  100  as an MCP. 
       FIGS. 4 and 5  show a second exemplary embodiment of the present invention.  FIG. 5  is a plan view of a shape as seen in a state where a chip on the upper layer side is removed. 
     A semiconductor device in the present exemplary embodiment has wiring substrate  101 , first semiconductor chip  102   a  and second semiconductor chip  102   b . First semiconductor chip  102   a  is mounted by being stacked on wiring substrate  101 , and second semiconductor chip  102   b  is mounted by being stacked on first semiconductor chip  102   a . First semiconductor chip  102   a  is joined onto wiring substrate  101  with die bonding material  104 . Second semiconductor chip  102   b  is joined onto first semiconductor chip  102   a  with die attach film (DAF)  107 . 
     First semiconductor chip  102   a  and second semiconductor chip  102   b  stacked on wiring substrate  101  and first bonding wires  106   a  and second bonding wires  106   b  described below are encapsulated in mold resin  109 . The maximum diameter of a tiller contained in mold resin  109  may be, for example, 70 μm. 
     A plurality of first connection terminals  111   a  are arranged in a straight line in an upper surface of wiring substrate  101 . A plurality of rows of terminals formed of a plurality of first connection terminals  111   a  are formed on wiring substrate  101 . In the example shown in  FIG. 5 , two rows of terminals are respectively formed on two side portions of wiring substrate  101 . The arrangement may alternatively be such that a plurality of rows of terminals is formed on one side portion of wiring substrate  101 . 
     A plurality of second connection terminals  111   b  are arranged in straight lines in the upper surface of wiring substrate  101  outside the rows of first connection terminals  111   a . A plurality of rows of terminals formed of second connection terminals  111   b  may be formed like the rows of terminals that are formed of first connection terminals  111   a.    
     A plurality of solder balls  105  are provided in the lower surface of wiring substrate  1 . 
     A plurality of first bonding pads  110   a  are arranged in a straight line in a central region of upper surface  102   a   1  of first semiconductor chip  102   a . Such a pad arrangement is frequently seen in semiconductor chips such as DRAM chips. A plurality of rows of pads formed of a plurality of first bonding pads  110   a  may be formed. The rows of pads may be provided in staggered form. Upper surface  102   a   1  is the front surface of the semiconductor chip in which a circuit is formed. 
     First bonding wires  106   a  connect first bonding pads  110   a  and first connection terminals  111   a  to each other. First bonding wires  106   a  are connected to first bonding pads  110   a  by passing through the space between upper surface  102   a   1  of first semiconductor chip  102   a  and lower surface  102   b   1  of second semiconductor chip  102   b . Lower surface  102   b   1  is the back surface positioned opposite from the front surface of the semiconductor chip. In the following description, portions of first bonding wires  106   a  passed through the space between upper surface  102   a   1  of first semiconductor chip  102   a  and lower surface  102   b   1  of second semiconductor chip  102   b  are referred to as “section B” as occasion demands. 
     First wire retaining members  108   a  formed of a coating material are provided in regions on upper surface  102   a   1  of first semiconductor chip  102   a  each including center line C bisecting distance L between the center of first bonding pad  110   a  and end  2   a   2  of first semiconductor chip  102   a . As the coating material, an insulating resin paste material containing a filler whose maximum diameter is 50 μm can be used. Each first wire retaining member  108   a  is formed so as to extend along the longitudinal direction of the pad row of first bonding pads  110   a . The material of first wire retaining members  108   a  is applied in a molten state from above first bonding wires  106   a  after first bonding pads  110   a  and first connection terminals  111   a  have been connected by first bonding wires  106   a . The material of the first wire retaining members  108   a  is set after being applied. Sections B of first bonding wires  106   a  are thereby fixed and retained, with their portions (portions indicated by Lc in  FIG. 4 ) embedded in first wire retaining members  108   a . Each of first wire retaining member  108 s is formed so as to extend along the longitudinal direction of the pad row of first bonding pads  110   a , as described above. Thus, first wire retaining member  108   a  fixes and retains the plurality of first bonding wires  106   a  connected to these first bonding pads  110   a.    
     A plurality of second bonding pads  110   b  and second wire retaining members  108   b  are also provided on an upper surface of second semiconductor chip  102   a . The plurality of second bonding pads  110   b  are arranged in a straight line. A plurality of rows of pads formed of second bonding pads  110   b  may be formed. The rows of these pads may be provided in staggered form. Second bonding wires  106   b  connect second bonding pads  110   b  and second connection terminals  111   b  to each other. The material of second wire retaining members  108   b  is applied in a molten state from above second bonding wires  106   b  after second bonding pads  110   b  and second connection terminals  111   b  have been connected by second bonding wires  106   b . The material of the second wire retaining members  108   b  is set after being applied. Second bonding wires  106   b  are thereby fixed and retained, with their portions embedded in second wire retaining members  108   b.    
     First wire retaining member  108   a  in the present exemplary embodiment is not one-sidedly disposed closer to an end of the semiconductor chip but is disposed in the region including the center line C. That is, first wire retaining member  108   a  is disposed at a substantially middle position between first bonding pads  110   a  and end  102   a   2  of first semiconductor chip  102   a , at which the displacement of sections B of first bonding wires  106   a  caused by an external force is maximized. Thus, the deformation of first bonding wires  106   a  in sections B when an external force is applied can be reduced. 
     Central portions of first bonding wires  106   a  in sections B are retained with first wire retaining members  108   a , as described above, thus enabling effective limiting of the deformation of first bonding wires  106   a  at the time of mold encapsulation in comparison with the insulating supporting structure in Japanese Patent Laid-Open No. 2004-312008 one-sidedly disposed closer to a semiconductor chip. 
     Let the length of the bonding wires extending from first wire retaining member  108   a  to the first bonding pad  110   a  side be wire length La. Let the length of the bonding wires extending from first wire retaining member  108   a  to the first connection terminal  111   a  side be wire length Lb. Further, let the length of first bonding wires  106   a  retained by first wire retaining member  108   a  be wire length Lc. At this time, wire length Lc may be set so as to satisfy the relationship: Lc&gt;(La+Lb+Lc)/2. That is, a portion of each first bonding wire  106   a  in section B having a length equal to or larger than half the length of section B may be retained by first wire retaining member  108   a.    
     First bonding wires  106   a  are retained by first wire retaining members  108   a  as described above to enable first bonding wires  106   a  to be positioned generally at the center of the spacing between semiconductor chips  102   a  and  102   b  even in a case where sections B of first bonding wires  106   a  receive an external force at the time of encapsulation. That is, when the chip periphery is encapsulated with mold resin  109 , external force is applied to first bonding wire  106   a . Even in such an event, the present exemplary embodiment enables preventing the distances between first bonding wires  106   a , semiconductor chips  102   a  and  102   b  from being changed before and after the encapsulation process. 
     Thus, according to the present exemplary embodiment, it is possible to prevent an increase in parasitic capacitance between first bonding wires  106   a  and first semiconductor chips  102   a  that is caused by bringing first bonding wires  106   a  closer to first semiconductor chip  102   a . That is, sections B of first bonding wires  106   a  are placed at a particular height between the semiconductor chips by first wire retaining members  108   a  and, therefore, a stable parasitic capacitance is produced by bonding wire  106  between bonding wires  106   a  and semiconductor chip  102   a . Consequently, a product free from signal degradation at wire bonding portions can be obtained. 
       FIG. 6  shows a side sectional view of a semiconductor device according to a third embodiment of the present invention. A large difference of this semiconductor device from that shown  FIG. 4  resides in that no DAF is provided on the back surface of a chip on the upper layer side. Die attach paste  113  is used for joining chips to each other. Components identical to those of the exemplary embodiment shown in  FIG. 4  will be described by using the same reference characters. 
     In the present exemplary embodiment, first wire retaining members  108   a  formed of die attach film having thickness t are provided on upper surface  102   a   1  of first semiconductor chip  102   a . First bonding wires  106   a  are connected after the die attach film has been placed on upper surface  102   a   1  of first semiconductor chip  102   a . First bonding wires  106   a  on first wire retaining members  108   a  are fixed and retained on first wire retaining members  108   a  by temporarily melting first wire retaining members  108   a  in the form of a die attach film and by thereafter setting the molten film. Thus, the die attach film is placed between upper surface  102   a   1  of first semiconductor chip  102   a  and first bonding wires  106   a , heated and molten and thereafter set. 
     The same point as that in the exemplary embodiment shown in  FIG. 4  will be discussed. Let the length of the bonding wires extending from first wire retaining member  108   a  to the first bonding pad  110   a  side be wire length La. Let the length of the bonding wires extending from first wire retaining member  108   a  to the first connection terminal  111   a  side be wire length Lb. Further, let the length of first bonding wires  106   a  retained by first wire retaining member  108   a  be wire length Lc. At this time, wire length Lc satisfies the relationship: Lc&gt;(La+Lb+Lc)/2. That is, a portion of each first bonding wire  106   a  in section B having a length equal to or larger than half the length of section B is retained by first wire retaining member  108   a . Thus, in the present exemplary embodiment in which first wire retaining members  108   a  are formed of die attach film, a construction for retaining first bonding wires  106   a  in a wide region can be easily realized. 
     Further, first bonding wires  106   a  are fixed on first wire retaining members  108   a  having thickness t, and the thickness of die attach paste  113  on first wire retaining members  108   a  is also set to t. In sections B, therefore, first bonding wires  106   a  are positioned generally at the center of the spacing between upper surface  102   a   1  of semiconductor chip  102   a  and the back surface of semiconductor chip  102   b.    
     Consequently, the present exemplary embodiment has the same advantages as the exemplary embodiment shown in  FIG. 4 . That is, it is possible to prevent an increase in parasitic capacitance between first bonding wires  106   a  and first semiconductor chips  102   a  that is caused by bringing first bonding wires  106   a  closer to first semiconductor chip  102   a . The region in which sections B of bonding wires  106   a  that are positioned between the semiconductor chips can be placed at a particular height can be increased in comparison with the exemplary embodiment shown in  FIG. 4 . Therefore stabilization of the parasitic capacitance can be improved. Consequently, a further improvement in signal characteristics can be achieved in comparison with the exemplary embodiment shown in  FIG. 4 . 
       FIG. 7  shows a side sectional view of a semiconductor device according to still another embodiment of the present invention.  FIG. 8  shows a plan view of a first semiconductor chip in the semiconductor device shown in  FIG. 7 .  FIG. 9  shows a side sectional view of a modified example of the semiconductor device in the present exemplary embodiment. 
     In the exemplary embodiments described above, all of bonding wires  106   a  between semiconductor chips are placed at a predetermined height by retaining members. The present exemplary embodiment differs from those described above in that bonding wires  106   a  are placed at respective optimum positions between semiconductor chips according to the kinds of external pins electrically connected to bonding wires  106   a  (e.g., those for a power supply system, a GND system and a signal system). In other respects, the construction is the same as that in the exemplary embodiment shown in  FIG. 4 . The same description of the construction will not be repeated. Also, the same components as those in the exemplary embodiment shown in  FIG. 4  will be described by using the same reference characters. 
     In the present exemplary embodiment, only signal-system wires  106   a   1  in a plurality of bonding wires  106   a  passed through the space between upper surface  102   a   1  of first semiconductor chip  102   a  and lower surface  102   b   1  of second semiconductor chip  102   b  are placed at a substantially middle position between the upper and lower chips by first wire retaining members  108   a . First wire retaining members  108   a  are disposed only in places through which signal-system wires  106   a   1  are passed. Signal-system wires  106   a   1  are passed through a position at which the parasitic capacitance is minimized with respect to each of first semiconductor chip  102   a  and second semiconductor chip  102   b  (that is, a position substantially coinciding with the center between the two chips). Therefore signal quality at the signal-system wire portions is improved. While a paste resin material is used for first wire retaining members  108   a  in the present exemplary embodiment, die attach film can be used in place of the paste resin material. If wire retaining members  108   a  in the form of a die attach film are used, as in the case of the exemplary embodiment shown in  FIG. 6 , signal-system wires  106   a   1  can be easily placed in a wide area at a substantially middle position between the upper and lower chips. 
     On the other hand, power-system wires or GND-system wires (hereinafter referred to as power supply GND system wires  106   a   2 ) in the above-described plurality of bonding wires  106   a  are placed so as to lie in close vicinity to upper surface  102   a   1  of first semiconductor chip  102   a . However, power supply GND system wires  106   a   2  are not in electrical contact with upper surface  102   a   1 . By placing power supply GND system wires  106   a   2  in this way, the parasitic capacitance between power supply GND system wires  106   a   2  and first semiconductor chip  102   a  can be increased to improve electrical characteristics of the power supply GND system. Also in a case where power supply GND system wires  106   a   2  are placed so as to lie in close vicinity to lower surface  102   b   1  of second semiconductor chip  102   b , as shown in  FIG. 9 , the effect of improving electrical characteristics of the power supply GND system, as in the case of placement of power supply GND system wires  106   a   2  shown in  FIG. 7 , can also be obtained. Wire retaining members formed of a coating material or a die attach film, as in the above-described embodiments, may be used for the purpose of placing power supply GND system wires  106   a   2  in close vicinity to upper surface  102   a   1  of first semiconductor chip  2   a  or in close vicinity to lower surface  102   b   1  of second semiconductor chip  102   b.    
     While exemplary embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to the illustrated structure and form; the present invention can be implemented by suitably changing or combining the above-described exemplary embodiments without departing from the technical spirit of the present invention. For example, the present invention can be applied in a similar manner even to a case where three or more semiconductor chips are stacked. 
     Although the inventions has been described above in connection with several preferred embodiments thereof, it will be appreciated by those skilled in the art that those embodiments are provided solely for illustrating the invention, and should not be relied upon to construe the appended claims in a limiting sense.