Patent Publication Number: US-11398828-B2

Title: Analog-to-digital converter

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of International Application No. PCT/JP2018/035248, filed on Sep. 25, 2018, the entire contents of which are incorporated herein by reference. 
    
    
     BACKGROUND 
     The disclosure relates to an analog-to-digital converter that converts an inputted analog signal into a digital value. 
     There has been utilized a flash analog-to-digital converter (hereinafter, called AD converter) that includes potential comparators (hereinafter, called comparators), a comparing voltage generator including voltage-dividing resistors connected in series to generate comparing voltages of the number of the comparators, and an encoder circuit that converts output results from the comparators into digital values. 
     Regarding such an AD converter, Japanese Patent Application Publication Nos. S61-186025 (PTL 1) and H07-326970 (PTL 2) disclose techniques that make it possible to change the resolution by adding a switch in a comparing potential generator, for example. An object of PTL 1 is to make it possible to change the resolution of the AD converter depending on the situation, and an object of PTL 2 is to facilitate testing by utilizing the changing of the resolution. 
     However, although it is possible to change the resolution for a single analog signal in the related techniques, if there is a need for conversion of multiple analog signals into digital values rather than achieving high resolution, the same number of AD converters as that of the analog signals to be converted are required. For this reason, in order to satisfy both the needs for the AD conversion at a high resolution and the AD conversion at a low resolution for multiple analog signals, a number of AD converters that may perform the AD conversion at a high resolution have to be provided, which brings about a large layout area and high cost. Targeting only one of these needs leads to poor versatility. 
     SUMMARY 
     An analog-to-digital converter that converts an inputted analog signal into a digital value according to one or more embodiments may include: unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal; and an adder that adds the digital values converted by the unit circuits. Each unit circuit may include coupling switches that couple the series resistor circuit with the series resistor circuit of another one of the unit circuits and connect the series resistor circuits between the high potential side reference voltage and the low potential side reference voltage and a sharing switch that shares the inputted analog signal with the other unit circuit that is coupled with the series resistor circuit. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a configuration diagram illustrating an analog-to-digital converter according to one or more embodiments; 
         FIG. 2  is an explanatory diagram illustrating a first usage example of an analog-to-digital converter, such as that illustrated in  FIG. 1 ; 
         FIG. 3  is an explanatory diagram illustrating a second usage example of an analog-to-digital converter, such as that illustrated in  FIG. 1 ; and 
         FIG. 4  is a configuration diagram illustrating another configuration example of an analog-to-digital converter according to one or more embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     An analog-to-digital converter according to one or more embodiments is described in detail with reference to the drawings. In the following embodiments, the configurations indicating similar functions are marked with the same reference numerals, and redundant descriptions thereof are omitted. 
       FIG. 1  is a configuration diagram illustrating an AD converter  1  according to one or more embodiments. As illustrated in  FIG. 1 , the AD converter  1  includes two unit circuits  10   1  and  10   2 , an adder  20 , and a selector  30 . The two unit circuits  10   1  and  10   2  may have the same configurations; thus, they are described as a unit circuit  10 . In one or more embodiments, the term “unit circuit” may refer to an analog-to-digital converter that includes at least one comparator to compare an inputted analog value with a reference voltage input value, convert the comparison result into a digitally converted value of 0 or 1 according to the magnitude relationship of the voltages, and output the digitally converted value. 
     The unit circuit  10  includes a series resistor circuit  11  that generates three reference voltages having regular potential intervals, three comparators CP 1  to CP 3  that compare an inputted analog signal with each of the three reference voltages, and an encoder  12  that converts the comparison results from the comparators CP 1  to CP 3  into a digital value of two bits. 
     The series resistor circuit  11  includes resistors R 1  to R 4  connected in series, and an open end of the resistor R 1  is a high potential side terminal while an open end of the resistor R 4  is a low potential side terminal. The resistors R 2  and R 3  have the same resistance values. Thus, when a voltage is applied between the high potential side terminal and the low potential side terminal, potentials of nodes on the low potential sides of the resistors R 1  to R 3  are inputted to inverting input terminals of the comparators CP 1  to CP 3 , respectively, as the three reference voltages having regular potential intervals. 
     The sum of a resistance value of the resistor R 1  and a resistance value of the resistor R 4  is set to be the same as each resistance value of the resistors R 2  and R 3 . When the resistance value of the resistor R 1  is set to be the same as the resistance value of the resistor R 2  or R 3 , the resistor R 4  may be omitted. When the resistance value of the resistor R 4  is set to be the same as the resistance value of the resistor R 2  or R 3 , the resistor R 1  may be omitted. 
     The comparators CP 1  to CP 3  compare the inputted analog signal with each of the three reference voltages generated by the series resistor circuit  11 . When the analog signal is greater than the reference voltage, an output of the corresponding one of the comparators CP 1  to CP 3  becomes a high level signal. When the analog signal is smaller than the reference voltage, an output of the corresponding one of the comparators CP 1  to CP 3  becomes a low level signal. 
     The encoder  12  converts the outputs from the comparators CP 1  to CP 3 , or the number of the high level signals outputted from the comparators CP 1  to CP 3 , into a digital value of two bits. 
     The unit circuit  10  includes a first terminal T 1 , a second terminal T 2 , a third terminal T 3 , a fourth terminal T 4 , a fifth terminal T 5 , a sixth terminal T 6 , a seventh terminal T 7 , an eighth terminal T 8 , a first switch SW 1 , a second switch SW 2 , a third switch SW 3 , and a fourth switch SW 4 . 
     The first terminal T 1  is a high potential input terminal that is connected with a high potential side reference voltage VCC. The first terminal T 1  is connected to the high potential side terminal of the series resistor circuit  11  through the first switch SW 1 . 
     The second terminal T 2  is a low potential input terminal that is connected with a low potential side reference voltage GND. The second terminal T 2  is connected to the low potential side terminal of the series resistor circuit  11  through the second switch SW 2 . 
     The third terminal T 3  is a terminal to which the analog signal is inputted and is connected to non-inverting input terminals of the comparators CP 1  to CP 3 . 
     The fourth terminal T 4  is connected to an output terminal of the encoder  12  and is a terminal to which the digital value of two bits converted by the encoder  12  is outputted. 
     The fifth terminal T 5  is a high potential side analog signal sharing terminal that shares the analog signal with a unit circuit  10  on the high potential side. The sixth terminal T 6  is a low potential side analog signal sharing terminal that shares the analog signal with a unit circuit  10  on the low potential side. The fifth terminal T 5  is connected to the non-inverting input terminals of the comparators CP 1  to CP 3 , and the sixth terminal T 6  is connected to the non-inverting input terminals of the comparators CP 1  to CP 3  through the third switch SW 3 . The fifth terminal T 5  and the non-inverting input terminals of the comparators CP 1  to CP 3  may be connected with each other through the third switch SW 3 . 
     The seventh terminal T 7  is a terminal that is connected with the eighth terminal T 8  of another unit circuit  10  arranged on the high potential side and is connected to the high potential side terminal of the series resistor circuit  11  through the fourth switch SW 4 . In the unit circuit  10   1  that is arranged to be closest to the high potential side, the seventh terminal T 7 , the fourth switch SW 4  and the first switch SW 1  may be omitted, and the high potential side terminal of the series resistor circuit  11  and the first terminal T 1  may be connected with each other directly. 
     The eighth terminal T 8  is a terminal that is connected with the seventh terminal T 7  of another unit circuit  10  arranged on the low potential side and is connected to the low potential side terminal of the series resistor circuit  11 . In the unit circuit  10   2  that is arranged to be closest to the lowest potential side, the eighth terminal T 8  and the second switch SW 2  may be omitted, and the low potential side terminal of the series resistor circuit  11  and the second terminal T 2  may be connected with each other directly. 
     The fourth switch SW 4  may be connected between the eighth terminal T 8  and the low potential side terminal of the series resistor circuit  11 . 
     On and off of the first switch SW 1  to the fourth switch SW 4  are switched statically or dynamically by a control device such as a microcomputer. For example, it may be possible to control on and off of the first switch SW 1  to the fourth switch SW 4  by a rewritable flag register. 
     The adder  20  adds the digital value of two bits outputted by the fourth terminal T 4  of the unit circuit  10   1  to the digital value of two bits of the fourth terminal T 4  of the unit circuit  10   2  and outputs a digital value of three bits. 
     The selector  30  includes three input terminals to which the digital values of two bits outputted from the fourth terminal T 4  of the unit circuit  10   1  and the fourth terminal T 4  of the unit circuit  10   2  and the digital value of three bits outputted from the adder  20  are inputted, and two output terminals. The selector  30  arbitrarily selects the input signals inputted from the three input terminals and outputs the input signal from the corresponding one of the two output terminals by a control circuit such as a microcomputer. 
     The AD converter  1  may function the unit circuits  10   1  and  10   2  as individual AD converters of resolution of two bits by turning on the first switches SW 1  and the second switches SW 2  and turning off the third switches SW 3  and the fourth switches SW 4  in the unit circuits  10   1  and  10   2  as illustrated in  FIG. 2 . The fourth switch SW 4  in the unit circuit  10   1  and the third switch SW 3  in the unit circuit  10   2  may be turned on. 
     Specifically, with the first switch SW 1  and the second switch SW 2  being turned on and the fourth switch SW 4  being turned off, the high potential side terminals of the series resistor circuits  11  of the unit circuits  10   1  and  10   2  are connected to the high potential side reference voltage VCC, while the low potential side terminals of the series resistor circuits  11  of the unit circuits  10   1  and  10   2  are connected to the low potential side reference voltage GND. It may be desirable to exclusively control on and off of the pair of the first switch SW 1  and the second switch SW 2  and the fourth switch SW 4  to prevent a short circuit between the high potential side reference voltage VCC and the low potential side reference voltage GND. 
     With the third switch SW 3  being turned off, analog signals a and b inputted to the third terminals T 3  of the unit circuits  10   1  and  10   2  are converted into the digital values of two bits by the unit circuits  10   1  and  10   2  and outputted from the fourth terminals T 4 , respectively. With the selector  30  selecting and outputting the digital values of two bits outputted from the unit circuits  10   1  and  10   2 , respectively, it is possible to obtain a digital signal a, which is obtained by AD-converting the analog signal a at a resolution of two bits, and a digital signal b, which is obtained by AD-converting the analog signal b at a resolution of two bits. 
     The AD converter  1  may couple the unit circuits  10   1  and  10   2  with each other and function them as an AD converter of resolution of three bits by turning on the first switch SW 1  and the third switch SW 3  and turning off the second switch SW 2  and the fourth switch SW 4  in the unit circuit  10   1 , while turning on the second switch SW 2  and the fourth switch SW 4  and turning off the first switch SW 1  and the third switch SW 3  in the unit circuit  10   2 , as illustrated in  FIG. 3 . The fourth switch SW 4  in the unit circuit  10   1  and the third switch SW 3  in the unit circuit  10   2  may be turned on. 
     The first switch SW 1 , the second switch SW 2  and the fourth switch SW 4  function as coupling switches that couple the series resistor circuit  11  with the series resistor circuit  11  of another unit circuit  10  and connect the series resistor circuits  11  between the high potential side reference voltage VCC and the low potential side reference voltage GND. Specifically, with the fourth switch SW 4  of the unit circuit  10   2  being turned on, the low potential side terminal of the series resistor circuit  11  in the unit circuit  10   1  and the high potential side terminal of the series resistor circuit  11  in the unit circuit  10   2  are coupled with each other. With the first switch SW 1  being turned on and the second switch SW 2  being turned off in the unit circuit  10   1 , and with the first switch SW 1  being turned off and the second switch SW 2  being turned on in the unit circuit  10   2 , the series resistor circuit  11  in the unit circuit  10   1  and the series resistor circuit  11  in the unit circuit  10   2  being coupled with each other are connected between the high potential side reference voltage VCC and the low potential side reference voltage GND. With this configuration, eight reference voltages having regular potential intervals are generated, and three high reference voltages on the high potential side are inputted to the inverting input terminals of the comparators CP 1  to CP 3  in the unit circuit  10   1 , respectively, while the three low reference voltages on the low potential side are inputted to the inverting input terminals of the comparators CP 1  to CP 3  in the unit circuit  10   2 , respectively. 
     The third switch SW 3  functions as a sharing switch that shares the inputted analog signal with another unit circuit  10  that is coupled with the series resistor circuit  11 . Specifically, with the third switch SW 3  of the unit circuit  10   1  being turned on, the unit circuits  10   1  and  10   2  share the analog signal inputted thereto with each other. With this configuration, the analog signal inputted to the third terminal T 3  in the unit circuit  10   1  is converted into a digital value of high two bits by the unit circuit  10   1  to be outputted from the fourth terminal T 4 , and also converted into a digital value of low two bits by the unit circuit  10   2  to be outputted from the fourth terminal T 4 . Consequently, the adder  20  outputs a digital value of three bits, which is obtained by adding the digital value of high two bits outputted from the unit circuit  10   1  to the digital value of low two bits outputted from the unit circuit  10   2 . With the selector  30  selecting and outputting the digital value of three bits outputted from the adder  20 , it is possible to obtain a digital signal that is obtained by AD-converting an analog signal at a resolution of three bits. 
     As described above, the AD converter  1  may AD-convert a single analog signal at a resolution of three bits by connecting the two unit circuits  10   1  and  10   2  in series. On the other hand, the AD converter  1  also may AD-convert two analog signals at a resolution of two bits by separating the two unit circuits  10   1  and  10   2  from each other. 
     It is possible to set the resolution and the number of the unit circuit  10  as appropriate. When 2 m  unit circuits  10  of resolution of n bits are provided, it is possible to AD-convert a single analog signal at a resolution of n+m bits by connecting the 2 m  unit circuits  10  in series. It is possible to AD-convert 2 m  analog signals at a resolution of n bits by separating the 2 m  unit circuits  10  from each other. With the number and the combination of the series connection of the 2 m  unit circuits  10  being set as appropriate, it is possible to easily switch between the setting of AD-converting few analog signals at a high resolution and the setting of AD-converting many analog signals at a low resolution, in a range from the resolution of n+m bits with the highest accuracy to the resolution of n bits with the lowest accuracy. 
     For example, when four unit circuits  10  of resolution of two bits are provided, it is possible to AD-convert a single analog signal at a resolution of four bits by connecting the four unit circuits  10  in series. It is further possible to AD-convert two analog signals at a resolution of three bits by connecting the unit circuits  10  in series by two. It is still further possible to AD-convert four analog signals at a resolution of two bits by separating the four unit circuit  10  from each other, respectively. 
     For example, when eight unit circuits  10  of resolution of two bits are provided, it is possible to AD-convert a single analog signal at a resolution of five bits by connecting the eight unit circuits  10  in series. It is further possible to AD-convert two analog signals at a resolution of four bits by connecting the unit circuit  10  in series by four. It is further possible to AD-convert four analog signals at a resolution of three bits by connecting the unit circuits  10  in series by two. It is further possible to AD-convert eight analog signals at a resolution of two bits by separating the eight unit circuits  10  from each other, respectively. It is still further possible to set the number and the combination of the series connection of the eight unit circuits  10  as appropriate. For example, four unit circuits  10  may be connected in series while the other four are separated from each other. 
     The resolution of the unit circuit  10  is not necessarily in the unit of bit. For example, the unit circuit  10  may be an AD converter that includes four reference potentials and comparators and performs the digital conversion into five states from 0 to 4. 
     The outputs from the unit circuits  10  connected in series are also not necessarily in the unit of bit. For example, when three AD converters that performs the digital conversion into five states from 0 to 4 are connected in series, the unit circuits  10  are AD converters that include  12  reference potentials and comparators in total and output digital values from 0 to 12 (in decimal number). 
       FIG. 4  is a diagram illustrating an AD converter  1   a  provided with eight unit circuits  10 . When four or more unit circuits  10  are provided, it may be preferable to include multiple adders  20  in the form of binary tree as illustrated in  FIG. 4 . In this case, the AD converter  1   a  may be configured such that a selector  30   a  may arbitrarily select digital values outputted from the four or more unit circuits  10  and digital values outputted from the adders  20 . For example, when the resolution of the unit circuit  10  is n, it is possible to output a digital value of resolution of n+1 from the adder  20  in a first row, a digital value of resolution of n+2 from the adder  20  in a second row, and a digital value of resolution of n+3 from the adder  20  in a third row as a final stage, respectively. 
     As described above, the analog-to-digital converter according to one or more embodiments may be an analog-to-digital converter  1  that converts an inputted analog signal into a digital value and includes: unit circuits  10  that each generate reference voltages having regular potential intervals by a series resistor circuit  11  connected between a high potential side reference voltage VCC and a low potential side reference voltage GND and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal; and an adder  20  that adds the digital values converted by the unit circuits  10 , in which each unit circuit  10  includes a first switch SW 1 , a second switch SW 2  and a fourth switch SW 4  that function as coupling switches that couple the series resistor circuit  11  with the series resistor circuit  11  of another one of the unit circuits  10  and connect the series resistor circuits  11  between the high potential side reference voltage VCC and the low potential side reference voltage GND, and a third switch SW 3  that functions as a sharing switch that shares the inputted analog signal with the other unit circuit  10  that is coupled with the series resistor circuit  11 . 
     According to the above described configuration, since it is possible to switch between the series connection and the separation of the unit circuits  10  of low resolution by the coupling switches and the sharing switch, both the needs for the AD conversion at high resolution and the AD conversion at low resolution for multiple analog signals may be satisfied, and thus it is possible to provide a versatile microcomputer. For example, an analog-to-digital converter mounted in a microcomputer and the like may have either needs for requiring high accuracy rather than the number of AD conversion and requiring the number of AD conversion rather than high accuracy, depending on the intended use. 
     In one or more embodiments, the analog-to-digital converter further includes: 2 m  pieces of the unit circuits  10  that each generate (2 n −1) pieces of the reference voltages having regular potential intervals by the series resistor circuit  11  and convert the reference voltages into a digital value of n bits by comparing the reference voltages with the inputted analog signal; and the adder  20  that adds the digital values of n bits converted by the 2 m  unit circuits  10  and outputs a digital value of (n+m) bits. 
     According to the above described configuration, with the number and the combination of the series connection of the 2 m  unit circuits  10  being set as appropriate, it is possible to easily switch between the setting of AD-converting few analog signals at a high resolution and the setting of AD-converting many analog signals at a low resolution, in a range from the resolution of n+m bits with the highest accuracy to the resolution of n bits with the lowest accuracy. 
     In one or more embodiments, the coupling switches (the first switch SW 1 , the second switch SW and the fourth switch SW 4 ) couple m pieces of the series resistor circuits  11  with each other and generate (2 n −1)×m pieces of the reference voltages having regular potential intervals between the high potential side reference voltage VCC and the low potential side reference voltage GND. 
     According to the above described configuration, with the series resistor circuits  11  being coupled with each other, it is possible to implement the AD conversion at a resolution of high accuracy. 
     In one or more embodiments, the analog-to-digital converter further includes a selector  30  that arbitrarily selects the digital values outputted from the 2 m  unit circuits  10  and the digital value outputted from the adder  20  and outputs the digital value from the corresponding one of output terminals. 
     According to the above described configuration, it is possible to select the digital value to be outputted as appropriate. 
     In one or more embodiments, when m is two or greater, a plurality of the adders  20  are provided in the form of binary tree, and the selector  30  arbitrarily selects the digital values outputted from the 2 m  unit circuits  10  and the digital values outputted from the adders  20  and outputs the digital value from the corresponding one of the output terminals. 
     According to the above described configuration, it may be possible to set the resolution of the digital value to be outputted as appropriate. 
     One or more embodiments are described above, and are merely examples that may be changed and implemented without departing from the intent of the invention. 
     According to the analog-to-digital converter of one or more embodiments, the coupling switches and the sharing switch may enable the switching between the series connection and the separation of the unit circuits of low resolution, and thus both the needs for the AD conversion at high resolution and the AD conversion at low resolution for multiple analog signals may be satisfied, and accordingly high versatility may be achieved.