Patent Publication Number: US-7596589-B2

Title: Time-mode analog computation circuits and methods

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 60/561,354, filed Apr. 12, 2004, which is incorporated herein by reference. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     The United States government may have certain rights to the invention by virtue of support through National Science Foundation grant no. EIA 0135946 and National Aeronautics and Space Administration grant no. NCC 2-1363. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to analog computational circuits, more specifically to computation circuits, which utilize time as both input and output quantities (operating in time-mode). 
     BACKGROUND OF THE INVENTION 
     Conventional VLSI circuits typically perform computational procedures using voltages and currents for both input and output signals. With technology scaling, the degrees of freedom for using voltages and currents for computations are generally more restricted. This can result in computational circuits that exhibit a poor signal-to-noise ratio (SNR), very limited Dynamic Range (DR), and/or high power consumption. 
     These factors are likely to be significant impediments to the development of more efficient and more effective analog computation circuits in the future, especially in light of the problems posed by technology scaling. Complementary metal-oxide semiconductor (CMOS) process technology, in particular, has lead to scaling that requires significant reductions in the chip “real estate” consumed by analog circuitry. Moreover, as CMOS process technology continues to shrink the usable voltage swing in such circuits, traditional analog circuit designs have been rendered less practicable. Thus there is a need for an alternative to conventional voltage-based and current based computations. 
     SUMMARY OF THE INVENTION 
     The present invention provides the circuit building blocks and techniques for computations using analog temporal signal function representations for both inputs and outputs. The invention enables computations using the timing of asynchronous events, for example. The computations performed with the circuits and methods of the invention produce results that can be expressed as time. For example, the result of a computation with the invention can be a time-based parameter corresponding to the timing of a signal output. This obviates the need for translation of temporal signals to an analog or digital form. The invention further overcomes limitations to scaling inherent in voltage-based and current-based computation circuits. 
     One embodiment of the invention is a time-mode analog computation circuit. The time-mode analog computation circuit can include one or more inputs for receiving one or more temporal input signals. The time-mode analog computation circuit further can include circuitry for performing a mathematical operation based on the one or more temporal input signals. A result of the mathematical operation can be expressed in the timing of an output signal generated by the circuit. 
     Another embodiment of the present invention is a signal processing method. The method can include providing one or more temporal input signals and performing a mathematical operation based on the one or more temporal input signals. The method, moreover, further includes expressing a result of the mathematical operation in a timing of an output signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A fuller understanding of the present invention and the features and benefits thereof will be accomplished upon review of the following detailed description together with the accompanying drawings, in which: 
         FIG. 1  is a schematic diagram of a time-mode computation circuit that computes the average or weighted average of two temporal signals, according to one embodiment of the invention. 
         FIG. 2  is a schematic diagram of a time-mode computation circuit that computes the weighted or unweighted sum of two temporal signals, according to another embodiment of the invention. 
         FIG. 3  is a schematic diagram of a time-mode computation circuit that computes the weighted difference of two temporal signals, according to yet another embodiment of the invention. 
         FIG. 4  is a schematic diagram of a time-mode computation circuit that computes the thresholded difference between two temporal signals, according to still another embodiment of the invention. 
         FIG. 5  is a schematic diagram of a time-mode computation circuit that computes the scalar multiplication of a temporal signal, according to another embodiment of the invention. 
         FIG. 6  is a schematic diagram of a time-mode computation circuit that computes the maximum of two temporal signals, according to yet another embodiment of the invention. 
         FIG. 7  is a schematic diagram of a time-mode computation circuit that computes the minimum of two temporal signals, according to still another embodiment of the invention. 
         FIG. 8  shows Cadence-Spectre simulation results for arithmetic mean of two input steps using circuit  100  shown in  FIG. 1  occurring at t 1 =200 μs and t 2 =400 μs. 
         FIG. 9  shows t OUT  measured data from circuit  100  when one step input was provided to circuit  100  and the current source I 1  was varied. 
         FIG. 10  shows t OUT  measured data from circuit  100  when t 1  was varied externally. 
         FIG. 11  shows t OUT  measured data from circuit  100  where the first input (t 1 ) entering circuit  100  was fixed as 1 μs, 8.5 μs and 32.5 μs for three different sets of measurements. The transition time (t 2 ) of the second input was varied externally and C=20 pF, I=1.552 uA, and Vref=2.5V. 
         FIG. 12  t OUT  measured data from circuit  100  where t 2  was varied and C=20 pF, I 1 =1.46 uA, I 2 =0.29 uA, Vref=2.5V with t 1  fixed at 1 μs, 8.5 μs and 32.5 μs. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A time-mode analog computation circuit according to the invention includes at least one input for receiving a temporal input signal and circuitry for performing a mathematical operation on the temporal input signal, a result of the mathematical operation being expressed in a timing of an output signal generated by the computation circuit. The invention thus provides analog computation using the timing of asynchronous events. Although described herein mainly with respect to MOS designs, one of ordinary skill in the art having the benefit of the description will appreciate that the invention can be practiced using bipolar, Bi-MOS, and other transistor-based devices and processes. 
     With conventional devices and processes that use time-based signal representations, such as pulse-width modulation (PWM) and sigma-delta converters, temporal codes are used only as temporary representations; computation is only performed after their translation to a traditional analog or digital form. Computation according to the invention, by contrast, represents a computed output quantity as a time, or more precisely, a time-based parameter. Translation from a temporal representation to an analog or digital form is not required, therefore, with the invention because computation is not based upon voltage or current levels but rather on the timing of changes in voltage or current levels. The invention thus overcomes the limitations imposed with conventional voltage-based and current-based computation circuits as the scaling process proceeds. Significantly, therefore, time-based computation circuits according to the invention are not substantially impacted by the scaling of technology. 
     The input to the time-mode computation circuits can be supplied from a variety of sources. For instance, the inputs could be from time-based sensors whose outputs encode measured real-world quantities in the timing of the signals. Another possibility is that the inputs to the time-mode computation circuit are the outputs from other time-mode circuits, since several layers of time-mode blocks can be cascaded. The outputs from the computation circuits according to the invention, moreover, can be stored in a digital memory after an appropriate analog-to-digital conversion of the time-mode signal. 
     As demonstrated herein, time-mode computation according to the invention can in many instances provide both a high signal-to-noise ratio (SNR) and an expansive dynamic range (DR). Moreover, power consumption in many instances can be reduced as compared to conventional voltage-based and current-based computation circuits. Therefore, VLSI circuits, which require some type of computation circuitry can be improved by representing signals in time, performing time-based computation, and representing computed output quantities as a time and/or a plurality of times (i.e., time-based parameters) according to the invention. 
     Exemplary circuitry for performing time-mode computations are described operationally herein for step inputs, where tpu input corresponds to a time-varying voltage signal, v(t), or time-varying current signal, i(t), represented by the following step waveforms or functions, respectively: 
     
       
         
           
             
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     Using such an analog temporal step function representation for the inputs, computation outputs, represented as time-based parameters, are described for the following computations:
         1) Weighed Averaging;   2) Addition;   3) Weighed Subtraction;   4) Scalar Multiplication;   5) Maximum Value Determination;   6) Minimum Value Determination; and   7) Thresholded Difference Determination.       

     These time-based computation circuits can be classified based on their output style: 
     
       
         
           
               
               
               
             
               
                   
               
               
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       FIG. 1  illustrates a time-mode analog computation circuit  100 , according to one embodiment of the invention. The computation circuit  100  illustratively includes two inputs, a first input  102   a  and a second input  102   b , for receiving two distinct temporal input signals and circuitry  104  for performing a mathematical operation based on the temporal input signals. The mathematical operation performed by the circuitry  104 , more particularly, is the computation of an average or weighted average of the two temporal signals. The result of the mathematical operation, as explained below, is expressed in a timing of an output signal generated by the circuitry. 
     The two distinct temporal input signals are illustratively step inputs, the waveforms or functions of which are shown adjacent the two inputs  102   a ,  102   b  where the step inputs are respectively received. The use of signals that can be represented as step functions not only simplifies somewhat the discussion of the operation of the computation circuit  100 , but has the added advantage that such signal representation closely approximates “fast-rise” time signals that typically hold particular interest for modern circuit designers. 
     The circuitry  104 , more particularly, illustratively includes a first current source  106   a  and a second current source  106   b . A first transistor  108   a  is electrically connected to the first current source  106   a , and a second transistor  108   b  is connected to the second current source  106   b . Illustratively, each of the transistors  108   a ,  108   b  is a p-channel metal oxide semiconductor (PMOS) transistor comprising a source, drain, and gate. A first signal inverter  110   a  is illustratively connected between the first input  102   a  and the gate of the first transistor  108   a , and a second signal inverter  110   b  is illustratively connected between the second input  102   b  and the gate of the second transistor  108   b.    
     As further shown, the drain of each of the transistors  108   a ,  108   b  connects to a capacitor  112 , having capacitance C. The drain of each of the transistors  108   a ,  108   b  also connects to a first input of a comparator  114 , the second input of the comparator receiving a threshold voltage, V TH . 
     Operatively, the computation circuit  100  performs a weighted average of temporal signals, illustratively provided by the two step inputs. The rising edge of a step input at the first input  102   a  occurs at time t 1 . The rising edge of the step input at the second input  102   b  occurs at time t 2 . Each of the transistors  108   a ,  108   b  acts as a switch. Accordingly, at t 1 , the increase in voltage at the gate of the first transistor  108   a  opens a path for the first current source  106   a  connected to the first transistor. The first current source  106   a  provides a current I 1 . The resulting current, I 1 , reaches the capacitor  112  connected to the first transistor  108   a , and the capacitor begins to charge. If t 2 &gt;t 1 , then the increase in voltage at the gate of the second transistor occurs subsequently. When it does, the increase in voltage at the gate of second transistor  108   b  opens a path for the second current source  106   b  that is also connected to the capacitor  112 . With the path open, the second current source  106   b  provides a current, I 2 , to the capacitor  112 , and the rate that the capacitor charges increases correspondingly. 
     Initially, a voltage across the capacitor  112  can be reset to 0 v. The voltage remains at zero until t 1  when the step in voltage at the gate of the first transistor  108   a  occurs, turning on the first transistor. The charge across the capacitor  112  continues to increase until t 2  when the step in voltage at the gate of the second transistor  108   b  occurs, turning on the second transistor and causing the voltage across the capacitor to increase faster. The comparator  114  senses the voltage across the capacitor  112 , and when the voltage reaches the threshold, V TH , the comparator responds by generating a step output. The time at which the step output occurs is designated t OUT . 
     During the period between t 1  and t 2 , the voltage, V temp , across the capacitor  112  is: 
                 V   temp     =         I   1     C     ⁢     (       t   2     -     t   1       )         ,         
where I 1  is the current provided by the first current source  106   a  and C is the capacitance of the capacitor  112 .
 
     Similarly, during the period t 2  to t OUT , the voltage across the capacitor is: 
                   V   TH     -     V   temp       =           I   1     +     I   2       C     ⁢     (       t   OUT     -     t   2       )         ,         
wherein, I 1  is again the current provided by the first current source  106   a , I 2  is the current provided by the first current source  106   b , and C is again the capacitance of the capacitor  112 .
 
     The preceding equations can be used to solve for an equation describing the output of the circuit in terms of time; that is in terms of a time-based parameter as opposed to one based on either voltage or current: 
                     t   OUT     =             I   1     ⁢     t   1       +       I   2     ⁢     t   2             I   1     +     I   2         +       C   ⁢           ⁢     V   TH           I   1     +     I   2                   (   1   )               
where, as described above, t OUT  is the time at which the output step occurs; that is, when the output of the circuitry transitions from a low voltage to a high voltage.
 
     Thus, the two current sources  106   a ,  106   b  connected to a respective source of each of the transistors  108   a ,  108   b  charge the capacitor  112  according to the particular timing of the respective step inputs, with the result being that the output of the computation circuit  100  is a time-based parameter. The time-based parameter, more particularly, corresponds to a time at which the comparator  114 , sensing the voltage across the capacitor  112 , generates a step output when the voltage across the capacitor reaches the threshold voltage V TH  of the comparator. 
     From the above equation, it is observed that the computation circuit  100  computes the weighted average of two input time steps occurring at t 2  and t 1  when the condition |I 2 t 2 −I 1 t 1 |&lt;CV TH  is met. 
     When I 1 =I 2 =I, the following is obtained: 
     
       
         
           
             
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     This output corresponds to an unweighted (simple) averaging of the two input time steps occurring at t 1  and t 2  when the condition 
                      t   1     -     t   2            &lt;       C   ⁢           ⁢     V   TH       I           
is met, offset by the time interval represented by CV TH /2I. By varying the amount of current provided by the current sources I 1  and I 2 , so that I 1  and I 2  are not equal, circuit  100  could compute the weighted average of two input signals. For example, if I 1 =2I 2 , input t 1  would be given twice the weight given to t 1 .
 
     It should be noted at this point that although the operation of a computation circuit according to the invention is herein described primarily in terms of voltage step inputs, the invention can readily be adapted to process other types of signals and other signal forms corresponding to discrete timing events. For instance, the computation circuits can perform computations based upon current-based step inputs, provided that the circuit uses this input to open or close an appropriate switch provided by a PMOS or other type of transistor. For example, if current-based inputs are used in place of voltage-based inputs, when a transistor is off, no current flows through its drain to charge the capacitor. However, as soon as a non-zero current input is provided, the transistor turns on and starts to conduct current from the current source to charge the capacitor as already described. 
     Moreover, although only two step inputs are provided to the computation circuit  100  shown in  FIG. 1 , with an appropriate number of inputs added, an arbitrary number of input steps, such as 3, 4, 5, or more step inputs can be received. Note also that the signal inverters  110   a ,  110   b  shown in  FIG. 1  would not be necessary if n-channel metal oxide semiconductor (NMOS) transistors were used to sink current instead of PMOS transistors. 
     Referring now to  FIG. 2 , a time-mode analog computation circuit  200 , according to another embodiment of the invention is illustrated. The computation circuit  200  illustratively includes a first input  202   a  and a second input  202   b  for receiving, respectively, a first temporal input signal at t 1  and a second temporal input signal at time t 2 . The computation circuit also includes circuitry  204  for performing a mathematical operation based on the temporal input signals, the mathematical operation defining the computation of a weighted or unweighted sum of the two temporal input signals and the result of the mathematical operation being expressed as a timing of an output signal generated by the circuit. 
     The circuitry  204 , more particularly, illustratively includes a first current source  206   a , a second current source  206   b , and a third current source  206   c . The circuitry  204  further includes a first transistor  208   a  and a second transistor  208   b . Illustratively, the first and second transistors  208   a ,  208   b  are each PMOS transistors having a source, drain, and gate. The gate of the first transistor  208   a  is electrically connected to the first input  202   a , with a first signal inverter  210   a  being connected between the gate and first input. The gate of the second transistor  208   b  is electrically connected to the second input  202   b , with a second signal inverter  210   b  being connected between the gate and second input. The third current source  206   c  is connected between the drains of the first and second transistors  208   a ,  208   b  and ground. 
     Additionally, the circuitry  204  illustratively includes a capacitor  212  connected between ground and the respective drains of each of the first and second transistors  208   a ,  208   b . The circuitry  204  also illustratively includes a comparator  214  having a first input connected to the respective drains of each of the first and second transistors  208   a ,  208   b  and a second input connected to a voltage source providing a threshold voltage, V TH . A logic AND gate  216  having a first input connected to the output of the comparator  214  and a second input for receiving the first temporal input signal at t 1  and an output is also a component of the circuitry  204 . Illustratively, both the first temporal input signal at t 1  and the second temporal input signal at time t 2  are each step inputs. 
     The output of the logic AND gate  216  provides a single-ended output. The inputs and outputs occurring at t 1 , t 2  and t OUT , respectively, are defined with respect to a time reference. When the reference time begins, the third current source  206   c  provides a current I 3  that starts discharging the capacitor  212 . When the first temporal signal is applied to the computation circuit  200  at time t 1 , the first current source  206   a  provides a current I 1 . As a result, a total current defined by the difference I 1 − 3  between the respective currents provided by the first and third current sources  206   a ,  206   c , respectively, starts charging the capacitor  212 . When the second input signal is applied to the computation circuit  200  at a time t 2 , the second current source  202   b  provides current I 2  and the net current I 1 +I 2 −I 3  charges the capacitor  212 . When the voltage across capacitor  212  reaches the threshold voltage, V TH , of the comparator  214 , the computation circuit  200  outputs a step output at time t OUT . 
     Without the logic AND gate  216  in series with the output of the comparator  214  shown in  FIG. 2 , the output of the comparator would contain an unwanted pulse at the reference time because the positive and negative terminals of the comparator would carry the same voltage, V TH . The logic AND gate  216  connected to the output of the comparator  214  ensures that the output from the block contains only a step output at time t OUT , t OUT  again being the time when the output of the computation circuit  200  illustratively makes its transition from a low to high voltage. The time value, t OUT  is determined according to the following formula: 
                     t   OUT     =         (       I   1         I   1     +     I   2     -     I   3         )     ⁢     t   1       +       (       I   2         I   1     +     I   2     -     I   3         )     ⁢     t   2                 (   2   )               
From equation (2), it is observed that the computation circuit  200  computes a weighted sum of the two step inputs occurring, respectively, at times t 1  and t 2 . When I 1 =I 2 =I 3 =I, the following result is obtained:
   t   OUT   =t   1   +t   2    
     This situation corresponds to the sum of two step inputs occurring at t 1  and t 2 , as already stated. However, by controlling the magnitudes of the current sources, functionalities different from the block-sum and weighted sum alternately can be obtained. 
     A computation circuit  300  for computing a weighted difference of two temporal signals, according to yet another embodiment of the invention, is illustrated in  FIG. 3 . The computation circuit  300  illustratively includes a first input  302   a  for receiving the first of the two temporal input signals at time t 1  and a second input  302   b  for receiving the second of the two temporal input signals at time t 2 . The computation circuit  300  further includes circuitry  304  for computing the weighted difference, the result of the computation being expressed in a timing of an output signal generated by the circuit. 
     The circuitry  304  illustratively includes first and second current sources  306   a ,  306   b  as well as first and second transistors  308   a ,  308   b . Illustratively, the first transistor  308   a  is a PMOS transistor having a source, drain, and gate, wherein the source is connected to the first current source  306   a  and the gate is connected to a signal inverter  310  that, in turn, is connected to the first input  302   a . The second transistor  308   b  is illustratively an NMOS transistor having a source, drain, and gate, wherein the drain of the second transistor is connected to the drain of the first transistor  308   a . The gate of the second transistor  308   b  is connected to the second input  302   b , and the source of the second transistor  308   b  is connected to the second current source  306   b.    
     The circuitry  304  further illustratively includes a capacitor  312  connected between ground and the juncture of the drain of the first transistor  308   a  and the drain of the second transistor  308   b . Also illustratively included in the circuitry  304  is a comparator  314  having first and second inputs and an output. The first input of the comparator  314  is connected to the juncture of the drain of the first transistor  308   a  and the drain of the second transistor  308   b . The second input of the comparator  314  is connected to a voltage source providing a threshold voltage, V TH . The circuitry  304  also illustratively includes a logic AND gate  316 . The logic AND gate  316  has a first input connected to the output of the comparator  314  and a second input that receives the first temporal input signal at time t 1 . Illustratively, both the first temporal input signal at t 1  and the second temporal input signal at time t 2  are each step inputs. The output of the computation circuit  300  is the output of the logic AND gate  316 . The output is a single-ended output having absolute time as its reference. 
     Note that in replacing a PMOS transistor with an NMOS transistor and changing the direction of the current provided by the second current source, the previously described computation circuit  100  is transformed into the computation circuit  300  shown in  FIG. 3  for performing a weighted subtraction of input signals occurring at t 1  and t 2 . 
     It is assumed with respect to the computation circuit  300  that the capacitor  316  is initially charged to a voltage V TH . As soon as the first temporal signal, illustratively a step input, is applied to circuit  300  at time t 1 , the first current source  306   a  provides a current I 1  that begins charging the capacitor  312 . When the step input occurs at time t 2 , the second current source  306   b  provides a current I 2 (I 2 &gt;I 1 ) that begins discharging the capacitor  312 . When the capacitor  312  voltage reaches the threshold voltage, V TH , the comparator  314  outputs a step output at time t OUT . As with circuit  200 , the output of the comparator  314  in circuit  300  would contain an unwanted pulse at the reference time because the positive and negative terminals of the comparator would carry the same voltage V TH . The AND gate  316  connected to the output of the comparator  314  ensures that the output from the block contains only a step output at time t OUT . 
     The output of the computation circuit  300  at time t OUT  is given by the following equation: 
                     t   OUT     =           I   2     ⁢     t   2       -       I   1     ⁢     t   1             I   2     -     I   1                 (   3   )               
From the equation it is seen equation that the computation circuit  300  applies a weight
 
             (       I   2         I   2     -     I   1         )         
to t 2  and a weight
 
             (       I   1         I   2     -     I   1         )         
to t 1 .
 
       FIG. 4  illustrates a computation circuit  400  that computes a threshold difference between two temporal signals, according to still another embodiment of the invention. The computation circuit  400  illustratively includes a first input  402   a  for receiving the first of the two temporal input signals at time t 1  and a second input  402   b  for receiving the second of the two temporal input signals at time t 2 . Illustratively, the computation circuit  400  additionally includes circuitry  404  for computing the threshold difference, the result being expressed in a timing of an output signal generated by the circuit. 
     The circuitry  404  illustratively includes a first current source  406   a  and a second current source  406   b . The circuitry also illustratively includes a first transistor  408   a  and a second transistor  408   b . The first transistor  408   a  is illustratively a PMOS transistor having a source, drain, and gate. The source of the first transistor  408   a  is connected to the first current source  406   a , and the gate of the first transistor is connected to a signal inverter  410 , which, in turn, is connected to the first input  402   a . The second transistor  408   b  is illustratively an NMOS transistor having a source, drain, and gate. The drain of the second transistor  408   b  is connected to the drain of the first transistor  408   a , and the gate of the second transistor is connected to the second input  402   b . The source of the second transistor  408   b  is connected to the second current source  406   b.    
     Illustratively, the circuitry  404  further includes a capacitor  412  connected between ground and the juncture of the drain of the first transistor  408   a  and the drain of the second transistor  408   b . The circuitry further includes a first comparator  414   a  and a second comparator  414   b . The first comparator  414   a  has a first input connected to the juncture of the drain of the first transistor  408   a  and the drain of the second transistor  408   b , and a second input of the of the first comparator  414   a  is connected to a voltage source providing a threshold voltage, V TH . The second comparator  414   b  has a first input connected also to the juncture of the drain of the first transistor  408   a  and the drain of the second transistor  408   b . A second input of the second comparator  414   b , however, is connected to a voltage source providing a negative threshold voltage, −V TH . 
     The computational circuit  400  can be used to check whether the time difference between two temporal signals is greater than or equal to a threshold value (CV TH /I). One application for such as circuit is for time-based edge detection. For example, the thresholded difference circuit  400  can be used to process the outputs of a time-based imager and determine the presence or absence of edges in images. A similar time-based edge detection circuit can also be used to determine significant differences between adjacent sensors in arrays of any type of time-based sensor, each such sensor generating signals in response to predetermined phenomena or conditions as will be readily understood by-one of ordinary skill in the art. 
     By replacing a PMOS transistor with an NMOS transistor and changing the direction of the second current source in circuit  100 , the computation circuit  400  is obtained, which can be used to obtain thresholded differences of steps. There are two situations to be considered assuming that the voltage across capacitor  412  (V C ) is initially reset to a midrange voltage value. 
     In the first situation, one of two steps inputs (at t 1  or at t 2 , repectively) is applied to circuit  400  before the other. If the initial step input is applied to the first input  402   a  of the circuit  400  (i.e., t 1 &lt;t 2 ), then the first current source  406   a  provides a current I 1 =I that linearly charges the capacitor  412  until the capacitor attains the positive threshold V TH . Conversely, if the initial step input is applied to the second input  402   b  of the circuit  400  (i.e., t 2 &lt;t 1 ), then the second current source  406   b  provides a current I 2 =I, and the capacitor discharges until the capacitor attains the negative threshold, −V TH . A step output at a time t OUT  is given as follows: 
                     t   OUT     =       t   i     +       CV   TH     I               (   4   )               
where i=1 when the initial step input is applied to the first input  402   a , and, alternatively, i=2 when the initial step input is applied to the second input  402   b.    
     The threshold implemented by circuit  400  is CV TH /I. This threshold value can be simply programmed by choosing appropriate values for V TH  and I. 
     In the second situation, the two step inputs arrive within the threshold time CV TH /I. Since the positive and negative current sources exactly cancel each other, no step is generated from either the positive or negative output indicating no edge between pixels. Mismatches between the two current sources will eventually cause one of the outputs to fire, but generally at a time much longer than the frame time of the system. If the threshold time CV TH /I is set to be the minimum difference in intensities required between a bright pixel and dark pixel, circuit  400  can be used to determine the presence or absence of an edge between 2 adjacent pixels. 
       FIG. 5  illustrates a computation circuit  500  for computing a scalar multiplication of a temporal signal, according to still an embodiment of the invention. The computation circuit  500  illustratively includes an input  502  for receiving a temporal input signal and circuitry  504  for performing scalar multiplication based upon the temporal signal, the result being expressed in a timing of an output signal generated by the circuit. 
     The circuitry  504  illustratively includes first and second current sources  506   a ,  506   b  and a transistor  508 . The transistor  508  is illustratively an NMOS transistor having a source, drain, and gate. The drain of the transistor  508  is connected to the first current source  506   a , and the source of the transistor is connected to the second current source  506   b . The gate of the transistor  508  is connected to the input  502 . 
     The circuitry  504  further illustratively includes a capacitor  512  connected between ground and a juncture of the first current source  506   a  and the drain of the transistor  508 . The circuitry  504  also illustratively includes a comparator  514  having a first input connected to the capacitor and the juncture of the first current source  506   a  and the drain of the transistor  508 . A second input of the comparator  514  is connected to a voltage source that supplies a threshold voltage, V TH . Illustratively, the circuitry  504  also includes a logic AND gate  516  having a first input connected to the output of the comparator  514  and second input for receiving the temporal signal, as shown. The output of computation circuit  500  is the output of the logic AND gate  516 . The output of the computation circuit  500  is a single-ended output, and the inputs and outputs are defined with respect to a reference time. 
     By removing the PMOS transistor that controlled the first current source and replacing the PMOS transistor with an NMOS transistor, while also changing the direction of the second current source of the circuit  100 , the computation circuit  500  performs scalar multiplication of a temporal signal entering circuit  500  at time t 2 . 
     If it is assumed that the capacitor  512  is initially charged to a voltage, V TH , the first current source  506   a  starts to charge the capacitor with a current I 1  as soon as the reference time starts. When the input step occurs at time t 2 , the second current source  506   b  provides a current I 2 (&gt;I 1 ) that starts discharging the capacitor  512 . When the capacitor voltage reaches V TH , the comparator outputs a step at time t OUT . The output of the comparator  514  would also contain an unwanted pulse at the reference time because the positive and negative terminals of the comparator would carry the same voltage V TH . The logic AND gate  516  connected to the output of the comparator  514  ensures that the output from circuit  500  contains only a step output at time t OUT . 
     The time-based output t OUT  from circuit  500  is given by the following equation: 
                     t   OUT     =       (       I   2         I   2     -     I   1         )     ⁢     t   2               (   5   )               
From equation (5), it is seen that circuit  500  multiplies time t 2  with a scalar
 
     
       
         
           
             
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       FIG. 6  illustrates a circuit  600  that computes the maximum of two temporal signals, according to an embodiment of the invention. The circuit  600  supports inputs and outputs that have absolute time as the reference. The output from circuit  600  is a single-ended output. The circuit  600  processes two temporal signals, such as time steps occurring at t 1  and t 2  as illustrated in  FIG. 6 , and determines the maximum, Max (t 1 , t 2 ), of the two steps. Thus, if t 1  is 300 μs and t 2  is 600 μs, t OUT  is 600 μs. If the signal was to be represented using voltages or currents as in conventional computation circuits, an extremely complex circuit would be required to compute Max(V 1 , V 2 ) or Max(I 1 , I 2 ). In time-based analog computation according to the invention, as demonstrated by the circuit  600  shown in  FIG. 6 , the circuitry to compute Max(t 1 , t 2 ) is substantially simplified. 
       FIG. 7  illustrates a circuit  700  that computes the minimum of two temporal signals, according to an embodiment of the invention. The circuit  700  supports inputs and outputs that have absolute time as the reference. The output from the circuit  700  is a single-ended output. The circuit  700  processes two time steps, such as time steps occurring at t 1 , and t 2  as shown in  FIG. 7 , and determines the minimum, Min(t 1 , t 2 ), of the two steps. The circuit  700  achieves the same efficiencies over conventional computational architectures as noted above relative to circuit  600 . 
     The time-based computation circuits according to the invention are expected to be applicable to a wide variety of applications. For example, present and future VLSI/Nano chips can benefit from the invention. Other applications for time-mode circuits according to the invention include Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, adaptive filters, multilayer perceptrons and other types of neural networks. 
     EXAMPLES 
     The present invention is further illustrated by the following specific examples, which should not be construed as limiting the scope or content of the invention in any way. 
     Circuit  100  shown in  FIG. 1  was simulated and prototype time-mode circuits according to the invention measured under a variety of conditions.  FIG. 8  shows Cadence-Spectre simulation results where circuit  100  was used to compute the arithmetic mean of two input steps, t 1 , and t 2 . The values of t 1 , t 2 , C, V TH  and I(I 1 =I 2 ) used in the simulation were 200 μs, 400 μs, 20 pF, 2.5V and 50 nA, respectively. The output expected from circuit  100  from equation (1) above is 800 μs which includes a 500 μs offset term (CV TH /I) thus computing the actual mean of t 1  and t 2  of 300 μs. The output obtained from simulations performed was 801 μs. It is noted that random variations in this delay and in the current sources can lead to inaccuracies in the calculations generated. 
       FIG. 9  shows measured data from a fabricated integrated circuit  100  when one step input was provided to circuit  100  (entering circuit  100  at t 1 ) with C=20 pF and Vref=2.5V. The current source I was varied and the output t OUT  was measured and plotted. The output expected from circuit  100  when 
     
       
         
           
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       FIG. 10  shows t OUT  measured data from circuit  100  when one step input was provided to circuit  100  (entering circuit  100  at t 1 ) with C=20 pF, I=1.0476 uA and Vref=2.5V. The input transition time t 1  was varied externally from off-chip and the output t OUT  was measured and plotted. The output expected from circuit  100  is 
               t   OUT     =       t   1     +       CV   TH     I             
which is also plotted In  FIG. 9 . The mean squared error between the expected results and the measured results=7.0201×10 −14  sec 2 .
 
       FIG. 11  shows t OUT  measured data from circuit  100  where the first input (t 1 ) entering circuit  100  was fixed as 1 μs, 8.5 μs and 32.5 μs for three different sets of measurements. The circuit  100  components had the following values: C=20 pF, I=1.552 uA and V TH =2.5V. The transition time (t 2 ) of the second input was varied externally and the output t OUT  was measured and plotted. The output expected from circuit  100  for different values of t 1  and t 2  is 
               t   OUT     =           t   1     +     t   2       2     +         CV   TH       2   ⁢   I       .             
The Mean squared error between the expected results and the measured results are shown in  FIG. 11 .
 
       FIG. 12  shows t OUT  measured data from circuit  100  where the first input (t 1 ) entering circuit  100  was fixed as 1 μs, 8.5 μs and 32.5 μs for three different sets of measurements. The circuit components had the following values: C=20 pF, I 1 =1.46 uA, I 2 =0.29 uA and V TH =2.5V. The transition time of the second input (t 2 ) was varied externally and the output t OUT  was measured and plotted. The output expected from the block for different values of t 1  and t 2  is 
               t   OUT     =             I   1     ⁢     t   1       +       I   2     ⁢     t   2             I   1     +     I   2         +         CV   TH         I   1     +     I   2         .             
The Mean squared error between the expected results and the measured results are shown in  FIG. 12 .
 
     Circuit  100  demonstrated the following measured results under the conditions C=20 pF, I 1 =I 2 =0.29 uA and V TH =2.5V at room temperature:
         SNR: 56 dB   Common-mode DR: Close to Infinity   Differential-mode DR: 62 dB   Power Consumption: 0.6 μW       

     This invention has been described herein in considerable detail to provide those skilled in the art with information relevant to apply the novel principles and to construct and use such specialized components as are required. However, it is to be understood that the invention can be carried out by different equipment, materials and devices, and that various modifications, both as to the equipment and operating procedures, can be accomplished without departing from the scope of the invention itself.