Patent Publication Number: US-11664297-B2

Title: Manufacturing method for reflowed solder balls and their under bump metallurgy structure

Description:
This application is a divisional of U.S. patent application Ser. No. 16/311,199, filed Dec. 19, 2018, entitled “MANUFACTURING METHOD FOR REFLOWED SOLDER BALLS AND THEIR UNDER BUMP METALLURGY STRUCTURE”, which is a 371 of International Application No. PCT/KR2017/004854, FILED May 11, 2017 and claims the benefit of Korean Application No. 10-2016-0091017, filed Jul. 18, 2016, the contents of which are incorporated herein by reference. 
    
    
     BACKGROUND TO RELATED APPLICATION 
     Technical Field 
     The present invention relates to a wiring structure of an electronic device and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same. 
     Background Art 
     In general, flip chip refers to a packaging technology capable of directly mounting an electrical apparatus or a semiconductor device face-down on a substrate or a board. An under bump metallurgy (UBM) structure used in the package technology is a metal structure provided between a solder ball and an electrode of a semiconductor chip or device. The UBM structure needs not to be oxidized in a subsequent process to achieve a low electrical resistance. 
     Related technology includes Korean Application Publication 2003-0066919 published on Aug. 14, 2003 and entitled “STRUCTURE AND METHOD FOR MANUFACTURING SOLDER BUMP OF FLIP CHIP PACKAGE”). 
     DETAILED DESCRIPTION OF THE INVENTION 
     Technical Problem 
     The present invention provides a semiconductor package capable of preventing deterioration of electrical characteristics thereof due to oxidation of an under bump metallurgy (UBM) structure, and a method of manufacturing the same. However, the scope of the present invention is not limited thereto. 
     Technical Solution 
     According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed. 
     In the first step, a thickness of the UBM structure may be greater than a thickness of an intermetallic compound formed at an interface of the solder ball and the UBM structure. 
     The second step may include a step for melting the primary solder ball to cover the side wall of the UBM structure and then cooling and contracting the primary solder ball to form an antioxidant layer on the side wall of the UBM structure and form the secondary solder ball on the upper surface of the UBM structure. 
     The second step may include a step for melting the primary solder ball to cover the side wall of the UBM structure and then cooling and contracting the primary solder ball to form an antioxidant layer on the side wall of the UBM structure and form the secondary solder ball not on the side wall of the UBM structure but on only the upper surface of the UBM structure. 
     The antioxidant layer may include a tin (Sn) component of the solder ball, and the UBM structure may be configured as a copper (Cu) layer. 
     The antioxidant layer may include a tin (Sn) component of the solder ball, and the UBM structure may include a structure in which a copper (Cu) layer, a nickel (Ni) layer, and a gold (Au) layer are sequentially stacked on one another, or a structure in which a Cu layer and a Ni layer are sequentially stacked on one another. 
     According to another aspect of the present invention, there is provided a semiconductor package including an under bump metallurgy (UBM) structure having a side wall surface-processed by a reflow soldering process, and a solder ball formed on an upper surface of the UBM structure. 
     A thickness of the UBM structure may be greater than a thickness of an intermetallic compound formed at an interface of the solder ball and the UBM structure. 
     The thickness of the UBM structure may be 20 μm to 50 μm. 
     Advantageous Effects 
     As described above, according to an embodiment of the present invention, a semiconductor package capable of preventing deterioration of electrical characteristics thereof due to oxidation of an under bump metallurgy (UBM) structure may be implemented. However, the scope of the present invention is not limited to the above-described effect. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 ,  3 ,  4 ,  5 , and  6    are cross-sectional views for sequentially describing the steps of a method of manufacturing a semiconductor package, according to an embodiment of the present invention. 
         FIG.  2    is a cross-sectional view of describing one of the steps of a method of manufacturing a semiconductor package, according to a comparative example of the present invention. 
         FIG.  7    is a graph showing a temperature profile of a reflow process used in the method of manufacturing a semiconductor package, according to an embodiment of the present invention. 
     
    
    
     MODE OF THE INVENTION 
     Hereinafter, the present invention will be described in detail by explaining embodiments of the invention with reference to the attached drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to one of ordinary skill in the art. In the drawings, the sizes of elements may be exaggerated or reduced for convenience of explanation. 
       FIGS.  1 ,  3 ,  4 ,  5 , and  6    are cross-sectional views for sequentially describing the steps of a method of manufacturing a semiconductor package, according to an embodiment of the present invention, and  FIG.  7    is a graph showing a temperature profile of a reflow process used in the method of manufacturing a semiconductor package, according to an embodiment of the present invention. 
     Referring to  FIG.  1   , a semiconductor chip or device including a conductive electrode pad  20  on a substrate  10  is initially prepared. The substrate  10  may include, for example, a wafer containing silicon (Si) or a substrate containing polymer and ceramic including glass. The conductive electrode pad  20  may be formed by coating and patterning metal on the substrate  10 . In this case, the metal may include aluminum (Al) or tungsten (W). The conductive electrode pad  20  may be electrically connected to a rewiring pattern  50  formed to efficiently establish an electrical connection with an external circuit to be coupled onto the semiconductor device. The rewiring pattern  50  may be electrically connected to an under bump metallurgy (UBM) structure  70  formed on the rewiring pattern  50 . To prevent unnecessary electrical shorts and physical or chemical damages due to an external factor, a first passivation pattern  40  and a second passivation pattern  60  may be formed between the conductive electrode pad  20  and the rewiring pattern  50  and between the rewiring pattern  50  and the UBM structure  70 . 
     The UBM structure  70  may serve as a wetting layer for good adhesion of solder thereto in a subsequent process, and also serve as a diffusion barrier to prevent permeation of a solder component into the semiconductor chip. The UBM structure  70  provided between solder and the semiconductor device needs to have a low electrical resistance. 
     The UBM structure  70  may have various configurations and may include, for example, a structure in which a copper (Cu) layer, a nickel (Ni) layer, and a gold (Au) layer are sequentially stacked on one another, or a structure in which a Cu layer and a Ni layer are sequentially stacked on one another. As another example, the UBM structure  70  may include a structure configured as a Cu layer. Alternatively, the UBM structure  70  may include a Cr/Cr—Cu/Cu structure, a TiW/Cu structure, or an Al/NiV/Cu structure. 
     A primary solder ball  80   a  may be formed on the UBM structure  70 . For example, the primary solder ball  80   a  may be formed on at least an upper surface  70   u  of the UBM structure  70  and, in this case, at least a part of a side wall  70   s  of the UBM structure  70  may be exposed. The primary solder ball  80   a  is an initial element to be implemented as a final solder ball  80  through a subsequent reflow process. 
     The final solder ball  80  may be understood as a sort of a bump. The bump may serve to increase an electrode height to facilitate implementation of a flip chip and also serve to replace an electrode material with a material easily connectable to an external electrode. In terms of a bump shape, a solder bump may be formed in, for example, a ball shape due to a surface tension effect after a reflow process. A material of the primary solder ball  80   a  may include CuSn or include AuSn, PbSn, PbSn 5 , AgSn, or the like. The primary solder ball  80   a  may be formed by mounting a solder ball by using a nozzle, or be formed using an electroplating method, a screen printing method, a Super-Juffit method, or the like. 
     Referring to  FIGS.  3  and  4   , a reflow process is performed on the primary solder ball  80   a  while the side wall  70   s  of the UBM structure  70  is exposed. In this case, the primary solder ball  80   a  is melted or softened to entirely cover the side wall  70   s  of the UBM structure  70 . As a temperature of the reflow process increases, a solder ball  80   b  having a concave part gradually changes into a hemispherical solder ball  80   c  due to the UBM structure  70 . 
     Referring to  FIG.  5   , as the temperature of the reflow process decreases, a molten solder ball  80   d  is cooled and contracted. Particularly, a part of the solder ball  80   d  adjacent to the side wall  70   s  of the UBM structure  70  may have a very small thickness. 
     Referring to  FIG.  6   , the molten solder ball  80   d  is continuously cooled and contracted to form a secondary solder ball  80  on the upper surface  70   u  of the UBM structure  70 . In this case, a tin (Sn) component of the secondary solder ball  80  may be coated on the side wall  70   s  of the UBM structure  70  to prevent oxidation of the UBM structure  70 . Ultimately, an antioxidant layer may be formed on the side wall  70   s  of the UBM structure  70  and the secondary solder ball  80  may be formed on the upper surface  70   u  of the UBM structure  70 . 
     More specifically, the antioxidant layer may be formed the side wall  70   s  of the UBM structure  70  and the secondary solder ball  80  may be formed not on the side wall  70   s  of the UBM structure  70  but on only the upper surface  70   u  of the UBM structure  70 . 
     Herein, the antioxidant layer serves to at least reduce or prevent oxidation of the side wall  70   s  of the UBM structure  70 . When energy-dispersive x-ray (EDX) composition analysis is performed on the conductive electrode pad  20  having the above-described configuration, a layer containing Sn is observed on the side wall  70   s  of the UBM structure  70 . 
     A comparative example of the present invention to be compared to the configuration of  FIG.  1    is illustrated in  FIG.  2   . 
     Referring to  FIG.  2   , before a reflow process is performed on the primary solder ball  80   a , an additional passivation pattern  75  is formed not to expose the side wall  70   s  of the UBM structure  70 . The additional passivation pattern  75  may prevent oxidation of the side wall  70   s  of the UBM structure  70  in a reflow process. However, since additional deposition and photolithography processes are required to form the passivation pattern  75 , manufacturing costs are increased. 
       FIG.  7    is a graph showing a temperature profile of the reflow process used in the method of manufacturing a semiconductor package, according to an embodiment of the present invention. 
     Referring to  FIG.  7   , a temperature (unit: ° C.) profile of the reflow process based on time (unit: sec.) is shown. In the graph, ‘step1’ corresponds to the step of  FIG.  1   , ‘step2’ corresponds to the step of  FIG.  3   , ‘step3’ corresponds to the step of  FIG.  4   , and ‘step5’ corresponds to the step of  FIG.  5   . In the method of manufacturing a semiconductor package, according to an embodiment of the present invention, the primary solder ball  80   a  may be formed to expose the side wall  70   s  of the UBM structure  70  in ‘step1’ before the temperature is increased for the reflow process. As such, oxidation of the UBM structure  70  may be effectively prevented without forming the additional passivation pattern  75  as illustrated in  FIG.  2   . 
     The above-described configuration may be easily implemented when the UBM structure  70  has a thickness equal to or greater than a certain thickness. The thickness of the UBM structure  70  may be greater than a thickness (e.g., about 8 μm) of an intermetallic compound formed at an interface of the UBM structure  70  and the solder ball. In this case, the thickness of the UBM structure  70  may be 20 μm to 50 μm. For example, when the thickness of the UBM structure  70  is 30 μm, the antioxidant layer may be effectively formed. 
     While the present invention has been particularly shown and described with reference to embodiments thereof, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the following claims.