Patent Publication Number: US-11394315-B2

Title: PoDL powered device with active rectifier bridge to obviate the need for DC-coupling inductors

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based on and claims priority from U.S. Provisional Application Ser. No. 62/911,664, filed Oct. 7, 2019, by Andrew J. Gardner et al., incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The invention relates to single-wire-pair, Power over Data Lines (PoDL) systems, where DC power and differential data signals are provided over the same twisted wire pair, and, in particular, to techniques to DC-couple a Powered Device (PD) to the wire pair without the need for inductors, while also performing DC polarity correction using an active full-bridge rectifier. 
     BACKGROUND 
     It is known to transmit DC power over differential data lines to power remote equipment. Power over Data Lines (PoDL) is an example of one such system. In PoDL, limited power is transmitted over a single, twisted wire pair along with the differential data. Certain standards for PoDL are found in IEEE P802.3bu and IEEE P802.3cg. 
     The DC voltage does not affect the differential data due to the use of DC coupling/decoupling circuits and AC coupling/decoupling circuits. In this way, the need for providing any external power source for the Powered Devices (PDs) can be eliminated. The PD load, powered by the DC power, may be a sensor, video camera, etc. A separate PHY (a transceiver) in the PD is AC-coupled to the wire pair and may communicate with a PHY in the Power Source Equipment (PSE) via differential data signals. The PHY is the physical layer of the OSI network model and may include receivers, transmitters, amplifiers, decoders, and other well-known devices which transmit and receive the differential signals on the wires and generate signals for further processing. The requirements for such PHYs are specified in the IEEE standards. 
       FIG. 1  is an example of one type of conventional PoDL system to which the present invention will be compared. 
     A twisted wire pair  10  is coupled between the PSE  12  and one or more PDs  14 ,  15 . The PSE  12  provides a DC voltage across the wires in the wire pair  10 . The PDs  14 ,  15  are insensitive to the polarity of the DC voltage since they include a full-bridge rectifier. The PDs  14 ,  15  include at least a PD load and a PD controller, where the PD controller communicates with the PSE  12  during start-up and controls a switch to connect the full DC voltage on the wires to the PD load. 
     The ends of the wire pair  10  are terminated by RC circuits comprising resistor R 1  and capacitor C 1 , and resistor R 2  and capacitor C 2 . Termination circuits reduce signal reflections. 
     The PSE  12  includes a DC voltage source and processing circuitry for determining whether the PDs  14 ,  15  are PoDL-compatible and for determining the power requirements of the PDs  14 ,  15 . Prior to the PSE  12  closing a switch to couple the full DC voltage (e.g., 54 V) across the wires, the PSE  12  and the PDs  14 ,  15  perform a low-power handshaking routine that does not involve the PHYs  18 - 20 . The signals during the handshaking mode are DC or low frequency, so are passed by the DC-coupling inductors L 1 -L 6 . 
     When the PSE  12  closes the switch, the inductors L 1 -L 6  pass the DC voltage to power the PD loads and present a high impedance to the AC differential signals. The PHYs  18 - 20  are coupled to the wires via AC-coupling capacitors C 3 -C 8 , which pass the differential signals and block the DC voltage. 
       FIG. 2  illustrates an example of a PD  20  coupled to the wire pair  10 . Inductors L 7  and L 8  DC-couple the PD  20  to the wire pair  10  via a passive full-bridge rectifier  22 , comprising diodes D 1 -D 4 . The PHY  24  is AC-coupled to the wire pair  10  using capacitors C 9  and C 10 . 
     The circuits of  FIGS. 1 and 2  perform adequately. The AC-coupling capacitors C 3 -C 10  may be very small (e.g., &lt;100 nF) and inexpensive. However, the inductors L 1 -L 8  are relatively large and expensive. 
     If the PoDL system is a multi-drop system, with multiple PDs coupled to the same wire pair at different locations, the overall cost of the inductors is even more significant. 
     What is needed is a lower cost solution for providing polarity insensitive DC-coupling to a PD in a PoDL system, where inductors (which couple the full DC power to the PD) are not required. 
     SUMMARY 
     A PD for a PoDL system is disclosed where the PD contains a gyrator that provides DC voltage polarity correction, DC-couples the DC voltage to the PD load, presents a high impedance to the differential data, and does not require an inductor for DC-coupling. 
     Transistors are used in a first portion of a full-bridge rectifier, along with capacitors, to couple a positive DC voltage to the positive voltage terminal of the PD load while effectively blocking AC signals from being coupled to the positive voltage terminal of the PD load. Similarly, transistors are used in a second portion of the full-bridge rectifier, along with capacitors, to couple a negative DC voltage to the negative voltage terminal of the PD load while effectively blocking AC signals from being coupled to the negative voltage terminal of the PD load. The rectifier couples the proper polarity DC voltage to the PD load without the need for inductors. The capacitors used in the rectifier are significantly smaller and less expensive than inductors. 
     In one embodiment, each of the two portions of the full-bridge rectifier uses at least four transistors, which may be MOSFETs or bipolar transistors, or a combination of both. In another embodiment, transistors and diodes are used in each portion of the full-bridge rectifier. 
     In embodiments using all MOSFET transistors in the full-bridge rectifier, the drains of some MOSFETs are coupled to the wires. Since these MOSFETs operate in saturation, the variations in the AC data signals on the wires do not significantly affect the conductivity of the MOSFETs and the voltage applied to the positive voltage terminal of the PD load. Similarly, when using bipolar transistors, the collectors of some of the transistors are coupled to the wires, so the variations in the AC data signals on the wires do not significantly affect the voltage applied to the PD load. 
     Further, the data signals vary the gate and source voltages (or the base and emitter voltages) similarly, so do not have a significant effect on the conductivity of the transistors. 
     The full-bridge rectifier is self-controlled by the polarity of the DC voltage. 
     Thus, the full-bridge rectifier emulates relatively large value DC-coupling inductors by conducting DC voltages and blocking AC data signals. In this respect, the rectifier is a gyrator since it emulates inductors using capacitive effects and transistors. 
     In one embodiment, there are multiple PDs using the same wire pair, so the benefits of not requiring inductors are increased. This is referred to as a multi-drop system. 
     Other embodiments are described. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a prior art PoDL, multi-drop system. 
         FIG. 2  illustrates an example of a PD node using DC-coupling inductors and a passive full-bridge rectifier for rectifying DC voltage on the wire pair. 
         FIG. 3  illustrates one embodiment of the invention, where the DC-coupling inductors are replaced with a gyrator that effectively blocks AC data signals, rectifies the DC voltage, and passes the DC voltage to the PD load. 
         FIG. 4  illustrates how four of the MOSFETs in the full-bridge rectifier of  FIG. 3  can be replaced with diodes. 
         FIG. 5  illustrates how the N-channel MOSFETs of  FIG. 3  can be replaced with P-channel MOSFETs. 
         FIG. 6  illustrates how one full-bridge rectifier portion uses N-channel MOSFETs while the other full-bridge rectifier portion uses P-channel MOSFETs. 
         FIG. 7  illustrates how the full-bridge rectifier uses a combination of NPN bipolar transistors and MOSFETs. 
         FIG. 8  illustrates how the full-bridge rectifier uses a combination of NPN bipolar transistors and diodes. 
         FIG. 9  illustrates how the full-bridge rectifier uses a combination of PNP bipolar transistors and diodes. 
         FIG. 10  illustrates how the full-bridge rectifier uses a combination of PNP bipolar transistors and P-channel MOSFETs. 
         FIG. 11  illustrates how one full-bridge rectifier portion uses a combination of PNP bipolar transistors and P-channel MOSFETs, and the other full-bridge rectifier portion uses a combination of NPN bipolar transistors and N-channel MOSFETs. 
         FIG. 12  is similar to  FIG. 3  but adds a circuit for PD inrush current control. 
         FIG. 13  is similar to  FIG. 3  but has a different configuration for the capacitors and adds switches to control the application of DC voltage across the PD load terminals. 
     
    
    
     Elements that are the same or equivalent in the various figures are labelled with the same numerals. 
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       FIG. 3  illustrates one embodiment of the invention. Only one PD node is shown coupled to wires  26  and  27  of a twisted wire pair  10  via a conventional MDI  16 . A PSE is not shown since it may be conventional, such as the PSE of  FIG. 1 . The PSE applies a DC voltage (e.g., 44 V) across the wires  26  and  27 . During normal operation of the PoDL system, a conventional DC voltage source in the PSE has its positive power supply terminal coupled to one of the wires  26  or  27  and its negative power supply terminal (relative to the positive voltage) coupled to the other one of the wires  26  or  27 . There may be multiple PD nodes coupled to the same wire pair  10 , and each PD load is powered by the same PSE. The PD loads may include voltage regulators that convert the DC voltage across the wires  26  and  27  to the appropriate voltage for the PD load. 
     The PD nodes may include conventional PHYs  28  to communicate with other PHYs via the wires  26  and  27  using Ethernet differential data signals. 
     The present invention is primarily directed to the DC voltage coupling to the PD load  30 . Requirements of the DC coupling circuit are that it rectifies the DC voltage, filters out the AC data signals so as not to add any significant loading to the data path, and applies the rectified DC voltage to the PD load  30 . The PD load  30  includes all elements that require power to operate, such as a camera, processing circuits, etc. Although not shown in  FIG. 3 , a regulated DC voltage is also applied to the PHY  28  for operating the PHY  28 . The PD load  30  and PHY  28  may be conventional. 
     No inductors are required in the PD nodes since the DC-coupling is performed by gyrators. 
     The AC-coupling capacitors C 1  and C 2  couple the differential data signals to the PHY  28  and block the DC voltage. 
     It is assumed that the top terminal of the PD load  30  is a positive voltage input terminal, and the bottom terminal of the PD load  30  is a negative voltage input terminal. 
     Assuming that the PSE DC voltage source supplies a positive voltage V+ to the wire  27  and a negative voltage V− to the wire  26 , the positive voltage is applied to the drain of the MOSFET M 1  via the impedance Z 2 . It will be assumed that the impedance Z 2  is a resistor or a short circuit. The positive voltage is also applied to the drain of the MOSFET M 4  via impedances Z 2  and Z 1 . It will be assumed that the impedance Z 1  is a resistor or a short circuit. 
     The MOSFETs M 1 -M 8  are N-channel types and have their sources connected to their bodies. 
     The body diode in the MOSFET M 1  is reverse biased, and the body diode in the MOSFET M 2  is forward biased. Therefore, current flows through the resistors R 1  and R 5  between the wire  27  and the PD load  30 , causing there to be voltage drops across the resistors R 1  and R 5 . At the same time, the capacitor C 3  is charged to the voltage differential between the top terminal of the PD load  30  and the voltage at the common node of resistors R 1  and R 5 . 
     The resistors R 1  and R 5  are selected so that the voltage drop across the resistor R 5  exceeds the threshold voltage of the MOSFETs M 1  and M 2 . The resistors R 1  and R 5  may have equal values, so each drops the gate-source voltage Vgs. The Vgs of the MOSFETs M 1  and M 2  is the same. Both MOSFETs M 1  and M 2  thus conduct to apply the V+ voltage to the top terminal of the PD load  30 . The optimal values of the resistors R 1  and R 5  can be easily determined by simulation. 
     The MOSFET M 1  operates in its saturation mode, where the current is fairly independent of its drain-source voltage. The MOSFET M 2 , on the other hand, operates in the triode region, where the drain-source voltage is very low and the MOSFET behaves like a voltage dependent resistor. 
     The capacitor C 3  blocks the DC voltage and smooths out voltage ripples. 
     Accordingly, when a positive DC voltage is applied to the wire  27 , both MOSFETs M 1  and M 2  are on to couple the positive voltage to the top terminal of the PD load  30  with a typical voltage drop of 2V to 3V. 
     A data signal on the wire  27  is effectively filtered out by the MOSFET M 1 . Since the MOSFET M 1  operates in its saturation mode, its drain voltage is relatively independent of its current. Any small variations in voltage due to the data signals at the drain of the MOSFET M 1  do not change the current, so there is insignificant effect on the data signals and on the input to the PD load  30 . 
     The resistor R 1  attenuates the data signal, and the capacitor C 3  smooths the voltage across the MOSFET M 2  so there is insignificant ripple in the DC voltage applied to the top terminal of the PD load  30  as a result of the differential data signals. 
     Further, any AC current flowing into the capacitor C 3  has little effect on the current through the MOSFETs M 1  and M 2  due to the gate voltage changing along with the source voltage, since the resistor R 5  is connected between the source and gate of the MOSFETs M 1  and M 2 . 
     The MOSFETs M 5  and M 6  on the right side of  FIG. 3  are off since the negative voltage (V−) on the wire  26  causes the Vgs of the N-channel MOSFETs M 5  and M 6  to be negative. The capacitor C 5  blocks the DC voltage. 
     Regarding the negative voltage on the wire  26 , an initial current flows through the PD load  30 , which causes the capacitor C 6  to charge so the drain of the MOSFET M 7  is more positive than its source. The body diode of the MOSFET M 8  is forward biased. The voltage drops across the resistors R 4  and R 8  create a Vgs that is higher than the threshold voltages of the MOSFETs M 7  and M 8  to turn them on to cause the negative voltage V− to be applied to the bottom terminal of the PD load  30  with a typical voltage drop of 2V to 3V. 
     Any data signal on the wire  26  does not affect the current through the MOSFETs M 7  and M 8  since the gate-source voltage (Vgs) does not change. MOSFET M 7  operates in saturation, while the MOSFET M 8  operates in its triode region. Slight voltage variations at the drain of the MOSFET M 7  do not affect its current. The capacitor C 6  smooths out ripples, and there is negative feedback which further reduces ripples. 
     On the bottom left side of the  FIG. 3 , the MOSFETs M 3  and M 4  are off since there is a negative Vgs. 
     In one embodiment, the gyrator of  FIG. 3  emulates DC-coupling inductors having a value on the order of millihenries. The design of  FIG. 3 , using a short for the impedances Z 1  and Z 2 , may be satisfactory for data rates up to about 100 Mbps. For Gigabit Ethernet, the AC filtering of the gyrator may not be large enough to adequately filter out the high frequency AC signals. So, the impedances Z 1  and Z 2  may be small value inductors, which would be on the order of 1/1000 the value of conventional inductors used in a PoDL system. Depending on the PoDL requirements for data speeds, the impedances Z 1  and Z 2  can be a small inductor, a small inductor in parallel with a resistor, a ferrite bead (presenting a small value inductance), or a short circuit. A wide range of data speeds may therefore be used with the same circuit. 
     If the DC voltage polarity was reversed, MOSFETs M 5  and M 6 , the resistors R 3  and R 7 , and the capacitor C 5  would operate to couple the positive voltage on the wire  26  to the top terminal of the PD load  30 . Similarly, the MOSFETs M 3  and M 4 , the resistors R 2  and R 6 , and the capacitor C 4  would operate to couple the negative voltage on the wire  27  to the bottom terminal of the PD load  30 . 
       FIG. 4  illustrates how the MOSFETs M 2 , M 4 , M 6 , and M 8  in the full-bridge rectifier of  FIG. 3  can be replaced with diodes D 2 , D 4 , D 6 , and D 8 , respectively. These replace the body diodes of the MOSFETs M 2 , M 4 , M 6 , and M 8 , so there is no benefit of the reduced voltage drops of the MOSFETs M 2 , M 4 , M 6 , and M 8 . Negative feedback and the saturation states of the MOSFETs cause the DC-coupling of the gyrator to not be significantly affected by the differential data signals. 
       FIG. 5  illustrates how the N-channel MOSFETs of  FIG. 3  can be replaced with P-channel MOSFETs, while the locations of the capacitors C 3 -C 6  and resistors R 1 -R 4  are reversed. The general operation is the same as the operation of the circuit of  FIG. 3  except that, when a positive DC voltage is applied to the wire  27  and a negative DC voltage is applied to the wire  26 , a negative Vgs is generated for MOSFETs M 9  and M 10  to turn them on to apply the positive voltage V+ to the top terminal of the PD load  30 . The body diode of the MOSFET M 9  initially conducts to cause a current to flow through the resistors R 5  and R 1  to generate the initial Vgs voltage to turn the MOSFETs M 9  and M 10  on. Similarly, a negative Vgs is applied to the MOSFETs M 15  and M 16  to turn them on to apply the negative voltage V− to the bottom terminal of the PD load  30 . The other MOSFETs M 11 -M 14  are off. The AC filtering is similar to that for  FIG. 3 . 
       FIG. 6  illustrates how the top full-bridge rectifier portion uses N-channel MOSFETs while the bottom full-bridge rectifier portion uses P-channel MOSFETs. The operation of the top part of  FIG. 6  is the same as that in  FIG. 3 . The operation of the bottom part of  FIG. 6  is the same as that in  FIG. 5 . 
       FIG. 7  illustrates how the full-bridge rectifier uses a combination of NPN bipolar transistors and N-channel MOSFETs. When a positive DC voltage is applied to the wire  27  and a negative DC voltage is applied to the wire  26 , the base-emitter of the transistor Q 1  is forward biased to turn on the transistors Q 1  and Q 2 , connected in a Darlington configuration. The Vgs of the MOSFET M 2  is sufficiently positive, which turns on the MOSFET M 2  to create a current path between the wire  27  and the top terminal of the PD load  30 . Similarly, the transistors Q 7  and Q 8  are turned on by the negative voltage on the wire  26 , along with the MOSFET M 8 , to create a current path between the wire  26  and the bottom terminal of the PD load  30 . The remaining transistors Q 5 , Q 6 , M 6 , Q 3 , Q 4 , and M 4  are off when the DC polarity is as shown. The AC data signals on the wires  26  and  27  are effectively filtered out due to the AC signals having an insignificant effect on the current conducted, since slight changes in collector voltages and drain voltages, due to the AC data signals, have an insignificant effect on the current conducted by the various transistors. Also, negative feedback cancels out the AC effects. 
       FIG. 8  illustrates how the full-bridge rectifier uses a combination of NPN bipolar transistors and diodes. The operation is the same as in  FIG. 7 . The diodes D 1 , D 2 , D 3 , and D 4  have the same orientations as the body diodes in the MOSFETs M 2 , M 4 , M 6 , and M 8  in  FIG. 7 . The diodes have a higher voltage drop than the MOSFETs when the MOSFETs are turned on. 
       FIG. 9  illustrates how the full-bridge rectifier uses a combination of PNP bipolar transistors and diodes. With the voltage polarity shown, the base-emitter of the transistor Q 9  is forward biased to turn on the transistors Q 9  and Q 10 , connected in a Darlington configuration. The diode D 5  is forward biased to create a current path between the wire  27  and the top terminal of the PD load  30 . Similarly, the transistors Q 15  and Q 16  are turned on by the negative voltage on the wire  26 , and the diode D 8  is forward biased, to create a current path between the wire  26  and the bottom terminal of the PD load  30 . The remaining transistors and diodes Q 13 , Q 14 , D 7 , Q 11 , Q 12 , and D 6  are off when the DC polarity is as shown. The AC data signals on the wires  26  and  27  are effectively filtered out due to the AC signals having an insignificant effect on the current conducted, since slight changes in collector voltages, due to the AC data signals, have an insignificant effect on the current conducted by the various transistors. Also, negative feedback cancels out the AC effects. 
       FIG. 10  illustrates how the full-bridge rectifier uses a combination of PNP bipolar transistors and P-channel MOSFETs.  FIG. 10  is the same as  FIG. 9  except that the diodes D 5 -D 8  are replaced with P-channel MOSFETs M 9 , M 11 , M 13 , and M 15 . With the DC polarity shown, the transistors Q 9 , Q 10 , and M 9  are turned on to create a current path between the wire  27  and the top terminal of the PD load  30 , and the transistors Q 15 , Q 16 , and M 15  are turned on to create a current path between the wire  26  and the bottom terminal of the PD load  30 . 
       FIG. 11  illustrates how one full-bridge rectifier portion uses a combination of PNP bipolar transistors and P-channel MOSFETs, and the other full-bridge rectifier portion uses a combination of NPN bipolar transistors and N-channel MOSFETs. The top half is the same as in  FIG. 7 , and the bottom half is the same as in  FIG. 10 . 
       FIG. 12  is similar to  FIG. 3  but adds a circuit for PD inrush current control. When the PoDL system is first turned on or if there is an abrupt change in the PD load  30 , there may be a large in-rush current due to capacitances charging. This may cause a high voltage slew rate across the PD load  30 , which may cause damage. In  FIG. 12 , a voltage slew rate above a threshold causes a high enough current to flow through the resistor R 12  to cause the voltage at the non-inverting input of the differential amplifier  36  to equal the reference voltage VREF. At this point, the amplifier  36  servos the gate-to-source voltage of the N-channel MOSFETs M 16  and M 17  sufficiently to cause the voltage at resistor R 12  to remain at VREF during the in-rush time to limit the voltage slew across the PD load  30 . By making the MOSFETs M 16  and M 17  conductive, some current is routed around the PD load  30  to limit the in-rush current into the PD load  30 . Once, the in-rush period is over, the voltage at resistor R 12  will remain below VREF, and the MOSFETs M 16  and M 17  will be off. 
       FIG. 13  is similar to  FIG. 3  but adds switches to control the application of DC voltage across the PD load terminals. In  FIG. 13 , the capacitors C 3  and C 5  are connected to the bottom terminal of the PD load  30 . The switches S 1  and S 2  may be MOSFETs which are initially held on when voltage is applied to the PD connector. After a delay interval, the switches S 1  and S 2  may be turned off, thus allowing the voltage at the intersection of R 1 /R 5 /C 3  to charge to a final value with an exponential decay characteristic of an R-C low pass filter. The voltage across the PD load  30  will track this decay thus limiting the slew rate of the voltage. 
     In one embodiment, no PHY is included in the PD, and the PD is powered by the DC voltage on the wires. Other PDs coupled to the same wires may include PHYs and be powered by the same PSE. 
     Accordingly, various embodiments of gyrators have been described that perform a function of a DC-coupling inductor and full bridge rectifier for a PD coupled to a wire pair so that the PSE can provide a DC voltage on the wire pair of either polarity. The gyrator presents a high impedance to differential data signals so that a PD load does not significantly affect the data signals on the wire pair. 
     Any of the disclosed features may be combined for a particular application. 
     While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications that are within the true spirit and scope of this invention.