Patent Publication Number: US-7218699-B2

Title: Frequency divider

Description:
RELATED APPLICATIONS 
   The present application is based on, and claims priority from, French Application Number 0400496, filed Jan. 20, 2004, the disclosure of which is hereby incorporated by reference herein in its entirety. 
   BACKGROUND OF THE INVENTION 
   The invention pertains to a frequency division device with at least three division ratios. 
   It can be applied, for example, in the field of frequency synthesis as a front-end divider for a fractional ratio division chain. 
   Prior art front-end dividers are generally dividers with two consecutive division ratios. 
   SUMMARY OF THE INVENTION 
   The invention relates to a device for dividing a frequency F e . The device comprises at least the following elements:
         three flip-flop circuits (U 1 , U 2 , U 3 ), each of the flip-flop circuits receiving the frequency F e  to be divided, every feedback loop between an output of a flip-flop circuit and its input or the input of the other flip-flop circuits comprising a single multiplexer (M 1 , M 2 , M 3 ), wherein   one of the flip-flop circuits commands the loading of all the flip-flop circuits (U 1 , U 2 , U 3 ) during a period of F e.          

   A multiplexer comprises, for example two inputs, one selection bit and one output and is integrated into a flip-flop circuit. 
   The device may have two latch circuits (U 4 , U 5 ) and two multiplexers (M 4 , M 5 ), respectively receiving the inputs INC 1  and INC 2  of the divider. The multiplexer may be integrated with a flip-flop circuit. 
   The device can be applied to a divider with three division ratios 2/3/4. 
   The invention has especially the following advantages: its working frequency is the maximum because the feedback loop paths between the D flip-flop circuit output and its input or the input of another D flip-flop circuit are minimal in terms of numbers of logic layers. In normal operation, these paths comprise only one multiplexer. The multiplexer is integrated or can be integrated with the D flip-flop circuit as a function of the technology. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other features and advantages of the present invention shall appear more clearly from the following description which in no way restricts the scope of the invention, and from the appended figures, of which: 
       FIG. 1  exemplifies a frequency divider dividing by the ratios 2, 3, 4, 
       FIG. 2  shows an alternative embodiment of the divider of  FIG. 1 . 
   

   MORE DETAILED DESCRIPTION 
   In order to understand the principle implemented in the frequency divider according to the invention, the following example relates to a three-ratio divider. The principle can also be applied to frequency dividers with more than 3 ratios, for example 4, 5 etc. 
     FIG. 1  provides a schematic view of a frequency divider dividing a frequency F e  by three ratios 2, 3 and 4. The choice between the three division ratios is done by means of a command bus formed by two bits referenced P 1  and P 2 . 
   The frequency divider comprises, for example, three D flip-flop circuits U 1 , U 2 , U 3  whose outputs are referenced Q 1 , Q 2  and Q 3 . Q 1  is the output of the divider. The input signals P 1  and P 2  can be used to control the division ratio of this divider. This scheme is optimal in terms of operating frequency because any feedback function between an output Q, Q of a D flip-flop circuit D and its input or the input of another D flip-flop circuit comprises, in normal operation, only one multiplexer M 1 , M 2 , M 3  which, in most technologies, is generally integrated or can be integrated with the D flip-flop circuit. A multiplexer comprises, for example, two inputs E i1 , E i2 , one selection bit SELi and one output Si, with i=1, 2, 3. 
   Any flip-flop circuit having an output that stores the value of the input at the instant of the clock transition (positive or negative clock signal edge) may also be used to replace a D flip-flop circuit. 
   In the present description, the term “multiplexer” designates a multiplexer or any other device that possesses one or more signal inputs, a selection input and an output that copies the value of one of the signal inputs as a function of the selection command. 
   The three flip-flop circuits work on the same clock signal F e . The circuit thus constituted is characterized, for example, by the following equations:
 
 Q 1 =P 1 *Q 3 +Q 2 *  Q   3
 
 Q 2 =P 2 *Q 3 +  Q   2 *  Q   3
 
 Q 3 =  Q   1 *  Q   3
 
   where “*” designates a logic AND and “+” designates a logic OR. 
   The following table 1 groups together the division ratio values obtained by the divider of  FIG. 1 . 
   
     
       
         
             
             
             
             
           
             
                 
                 
             
             
                 
               P1 
               P2 
               Division ratio obtained as a function of P1 and P2 
             
             
                 
                 
             
           
          
             
                 
               0 
               1 
               The circuit divides by 2 
             
             
                 
               1 
               0 
               The circuit divides by 3 
             
             
                 
               1 
               1 
               The circuit divides by 4 
             
             
                 
                 
             
          
         
       
     
   
     FIG. 2  represents an alternative embodiment used to process the disallowed case where P 1 =P 2 =0. 
   As compared with the divider of  FIG. 1 , the divider additionally has, for example, two latches U 4 , U 5  and two 2 multiplexers M 4 , M 5 , respectively receiving the inputs INC 1  and INC 2  of the divider. The two latches may be replaced by two flip-flop circuits or any other device having the same function. 
   The working of the divider is given in the following table 2. 
   
     
       
         
             
             
             
             
           
             
                 
                 
             
             
                 
               INC1 
               INC2 
                 
             
             
                 
                 
             
           
          
             
                 
               0 
               0 
               The circuit divides by 2 
             
             
                 
               1 
               0 
               The circuit divides by 3 
             
             
                 
               0 
               1 
               The circuit divides by 3 
             
             
                 
               1 
               1 
               The circuit divides by 4 
             
             
                 
                 
             
          
         
       
     
   
   For these two embodiments, one of the D flip-flop circuits commands the loading of the three flip-flop circuits U 1 , U 2 , U 3  during a period of the clock signal F e . This operation is the optimum from the viewpoint of the positioning time for the commands P 1  and P 2  and the elimination of the false cycles. 
   Another characteristic of the device according to the invention is that Q 1  has a low state with a duration equal to only one period of F e  for all three division ratios. This low state is, for example, located at the end of a cycle of Q 1 . This characteristic is used when this circuit is used as a front-end divider in a division chain, in giving a possibility of selection of only one edge of the frequency F e  per output cycle of the front-end divider. 
   According to another alternative embodiment, each D flip-flop circuit is subdivided into at least two latch circuits. 
   Another variant consists in keeping the same logic equations giving Q 1 , Q 2  and Q 3  which are characteristic of the circuit and in applying the usual logic transformations to them. An example of a transformation consists in complementing the two parts of each equation. 
   Without departing from the framework of the invention, any flip-flop circuit whose output stores the value of the input at the instant of the clock transition (positive or negative clock signal edge) can be used in the divider according to the invention.