Patent Publication Number: US-2023153202-A1

Title: Memory system for performing recovery operation, memory device, and method of operating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2021-0156056, filed on Nov. 12, 2021 in the Korean Intellectual Property Office and Korean Patent Application No. 10-2022-0055022, filed on May 3, 2022 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference in their entireties herein. 
     1. TECHNICAL FIELD 
     The present inventive concept relates to a memory system, and more particularly, to a memory system for performing a recovery operation, a memory device, and a method of operating them. 
     2. DISCUSSION OF RELATED ART 
     A non-volatile memory device is a semiconductor memory device that includes a plurality of memory cells having non-volatile store data. As an example of a non-volatile memory device, a flash memory system is widely applied to various electronic devices, such as a universal serial bus (USB) drive, a digital camera, a mobile phone, a smart phone, a tablet personal computer (PC), a memory card, and a solid state drive (SSD). It is desirable for a memory system that includes a non-volatile memory device to have an increased reliability of programmed data while enabling a large capacity storage, 
     SUMMARY 
     Embodiments of the present inventive concept provide a memory device for performing a recovery operation to reduce degradation of the reliability of the memory device on which program/erase operations are repeatedly performed. Embodiments of the present inventive concept provide a memory device that cures itself by using Joule heat generated as a current flowing in the memory device, a memory system including the same, and a method of operating the same. 
     According to an embodiment of the present inventive concept, a method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, includes detecting a first memory block having a degradation count greater than or equal to a first reference value from among the plurality of memory blocks by the memory controller. A first command for the first memory block is transmitted to the memory device by the memory controller. A recovery operation is performed by applying a first voltage to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines connected to the first memory block. The second voltage is greater than a voltage applied to the bit line during a program operation, a read operation, or an erase operation performed on the memory device. 
     According to an embodiment of the present inventive concept, a memory device includes a memory cell array comprising a plurality of memory blocks. Each of the plurality of memory blocks comprises a plurality of memory cells, a plurality of word lines respectively connected to the plurality of memory blocks, and a plurality of bit lines respectively connected to the plurality of memory blocks. A control circuit controls the memory device to perform a control operation on a first memory block from among the plurality of memory blocks. During the control operation, the control circuit copies first data stored on the first memory block from among the plurality of memory blocks and stores the first data on a second memory block from among the plurality of memory blocks and erases the first data stored on the first memory block; applies a first voltage to sonic selected word lines from among a plurality of word lines connected to the first memory block and applies a second voltage to a bit line connected to the first memory block among the plurality of bit lines; controls the first voltage to be greater than a voltage applied to turn on memory cells connected to the some selected word lines from among the word lines connected to the first memory block; and controls the second voltage to be greater than a voltage applied to the bit line during a program operation, a read operation, or an erase operation performed on the memory cell array. 
     According to an embodiment of the present inventive concept, a memory system includes a memory device comprising a plurality of memory blocks. A memory controller transmits commands to control the memory device. In response to the commands, the memory device copies first data stored on a first memory block from among the plurality of memory blocks and stores the first data on a second memory block from among the plurality of memory blocks, erases the first data stored on the first memory block, applies a first voltage to all of word lines connected to the first memory block, and applies a second voltage to a bit line connected to the first memory block. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the word lines connected to the first memory block. The second voltage is greater than a voltage applied to the bit line during a pre-charging operation for the memory device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG.  1    is a block diagram showing a memory system according to an embodiment of the present inventive concept; 
         FIG.  2    is a block diagram of a memory device according to an embodiment of the present inventive concept; 
         FIG.  3    is a perspective view showing the memory cell array of  FIG.  2   ; 
         FIG.  4    is a perspective view of a first memory block from among the memory blocks of  FIG.  2    according to an embodiment of the present inventive concept; 
         FIG.  5    is a circuit diagram showing an equivalent circuit of a first memory block from among the memory blocks of  FIG.  2    according to an embodiment of the present inventive concept; 
         FIG.  6    is a cross-sectional view of a non-volatile memory cell according to an embodiment of the present inventive concept; 
         FIGS.  7 A to  7 C  are cross-sectional views showing that a recovery operation is performed according to embodiments of the present inventive concept; 
         FIG.  8    is a flowchart of a method of operating a memory system for performing a recovery operation, according to an embodiment of the present inventive concept; 
         FIG.  9    is a flowchart of operation S 130  of  FIG.  8    in detail according to an embodiment of the present inventive concept; 
         FIG.  10    is a flowchart of a method of operating a memory system for performing a recovery operation, according to an embodiment of the present inventive concept; 
         FIG.  11    is a flowchart of a method that may be performed after operation S 120  of  FIG.  8    according to an embodiment of the present inventive concept; 
         FIGS.  12 A to  12 E  are flowcharts for describing operations S 330  to S 350  of  FIG.  11    in detail according to embodiments of the present inventive concept; 
         FIG.  13    is a flowchart of an embodiment that may be performed after operation S 120  of  FIG.  8    according to an embodiment of the present inventive concept; 
         FIGS.  14 A to  14 E  are flowcharts for describing operations S 430  to S 460  of  FIG.  13    in detail according to embodiments of the present inventive concept; 
         FIG.  15    is a block diagram showing a memory device that is applied to a solid state drive (SSD) system according to an embodiment of the present inventive concept; 
         FIG.  16    is a diagram showing a method of forming a memory cell array, according to an embodiment of the present inventive concept; and 
         FIG.  17    is a diagram for describing a BVNAND structure that may be applied according to an embodiment of the present inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       FIG.  1    is a block diagram showing a memory system according to an embodiment of the present inventive concept. Referring to  FIG.  1   , a memory system  1  may include a memory controller  10  and a memory device  100 . The memory controller  10  may include a block management module  11  and an error correction code (ECC) engine  12 . The memory device  100  may include a memory cell array  110 , a row decoder  140 , and a recovery control circuit  132 , 
     According to some embodiments, the memory system  1  may be implemented as an internal memory embedded in (e.g., applied to) an electronic device, such as an embedded universal flash storage (UFS) memory device, an embedded multi-media card (eMMC), or a solid state drive (SSD). According to some embodiments, the memory system  1  may be implemented as an external memory that is detachably attached to an electronic device, such as a UFS memory card, a compact flash (CF) memory card, a secure digital (SD) memory card, a micro secure digital (micro-SD) memory card, a mini secure digital (mini-SD) memory card, an extreme digital (xD) memory card, or a memory stick. However, embodiments of the present inventive concept are not necessarily limited thereto. 
     The memory controller  10  may control the memory device  100  to read data stored in the memory device  100  or to program data to the memory device  100  in response to a write/read request from a host HOST. As program/erase cycles are repeated in each memory block of the memory device  100 , the reliability of the memory block may degrade, and the memory controller  10  may control the memory device  100  to recover the degraded reliability of the memory block. For example, the memory controller  10  may provide an address ADDR, a command CMD, and a control signal CTRL to the memory device  100 , thereby controlling a program operation, a read operation, an erase operation, and a recovery operation performed on the memory device  100 . Also, data DATA to be programmed and read data DATA may be transmitted and received between the memory controller  10  and the memory device  100 . 
     According to an embodiment, as program/erase cycles of a memory block accumulate, the reliability of the memory block may degrade. In an embodiment, to reduce degradation of the reliability of a memory block, the memory system  1  may perform wear leveling management, bad block management, a recovery operation for self-curing, etc. The memory controller  10  may provide an address ADDR, a command CMD, a control signal CTRL, and data DATA for performing wear leveling management, bad block management, and a recovery operation on the memory device  100 . Detailed descriptions of the recovery operation are provided below. 
     In an embodiment, the block management module  11  may include a counter for the degradation count of each memory block of the memory cell array  110 . The degradation count may be a program/erase count for a memory block, a read count for a memory block, or the number of error bits of data read from a memory block. However, embodiments of the present inventive concept are not necessarily limited thereto, and the degradation count may be various pieces of information indicating and/or relating to degradation of a memory block. 
     According to an embodiment, the counter of the block management module  11  may update degradation counts every time an operation that accumulates degradation counts for memory blocks in the memory device  100  is performed. According to an embodiment, a degradation count may increase every time a program/erase operation is performed on a corresponding memory block. According to an embodiment, a degradation count may increase every time a read operation is performed on a corresponding memory block. According to an embodiment, a degradation count may increase when the number of error bits detected when a read operation is performed on a corresponding memory block increases. The value of a degradation count may differ from one memory block to another. 
     The block management module  11  may compare a first reference value with a degradation count. The memory controller  10  may provide a recovery command and an address of a memory block having a degradation count that is greater than or equal to the first reference value to the memory device  100 , and a recovery operation may be performed on the corresponding memory block. The block management module  11  may compare a second reference value with a degradation count. The memory controller  10  may manage a memory block having a degradation count greater than or equal to the second reference value as a bad. block. The first reference value may be less than the second reference value. According to some embodiments, when a degradation count corresponds to the number of error bits, the first reference value may be the maximum number of error bits that may be error-corrected by the ECC engine  12 . According to some embodiments, the first reference value may differ from one memory block to another. According to some embodiments, the memory system  1  may further include an additional memory device other than the memory device  100 , and the value of the first reference value may differ from one memory device to another. 
     According to an embodiment, the memory controller  10  may compare a first reference value or a second reference value stored in the block management module  11  with degradation counts, thereby determining whether memory blocks in the memory device  100  are bad blocks and whether a recovery operation for recovering degraded reliability of memory blocks is necessary to be performed, 
     The ECC engine  12  may be configured to detect and correct an error in data read from the memory device  100  by using an error correction code. The ECC engine  12  may include all of the circuits, systems, or devices for error correction. When the ECC engine  12  performs error correction and the number of errors is greater than an error bit correction threshold, error bit correction may fail. 
     According to an embodiment, the memory controller  10  may perform a recovery operation based on whether data correction of the ECC engine  12  is successful, 
     The recovery control circuit  132  may control the memory device  100  to perform a recovery operation in response to a recovery command received from the memory controller  10 . According to an embodiment, the recovery control circuit  132  may control the memory device  100  to apply voltages to word lines and bit lines of a memory block to be recovered. For example, a voltage applied to a word line may be greater than or equal to a turn-on voltage for turning on memory cells or a pass voltage. A voltage applied to a bit line may be higher than a voltage applied during a pre-charge operation. According to an embodiment, when the recovery control circuit  132  applies a voltage to word lines, the recovery control circuit  132  may control the memory device  100 , such that the voltage is applied to some selected word lines from among a plurality of word lines connected to a memory block to be recovered. According to an embodiment, when the recovery control circuit  132  applies a voltage to word lines, the recovery control circuit  132  may control the memory device  100 , such that the voltage is applied to all of a plurality of word lines connected to a memory block to be recovered. 
       FIG.  2    is a block diagram of a memory device according to an embodiment. For example,  FIG.  2    may show an example implementation of the memory device  100  of  FIG.  1   . 
     Referring to  FIG.  2   , the memory device  100  may include the memory cell array  110 , a voltage generator  120 , a control logic  130 , the row decoder  140 , and a page buffer  150 . In an embodiment, the memory device  100  may further include various other components related to a memory operation, such as a data input/output circuit or an input/output interface, etc. 
     The memory cell array  110  may include a plurality of memory cells and may be connected to word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. In an embodiment, the memory cell array  110  may be connected to the row decoder  140  through the word lines WL, the string select lines SSL, and the ground select lines GSL and may be connected to the page buffer  150  through the bit lines BL. 
     For example, the memory cells included in the memory cell array  110  may be non-volatile memory cells that retain stored data even when the supplied power is cut off For example, in an embodiment in which the memory cells are non-volatile memory cells, the memory device  100  may be electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM). Hereinafter, embodiments are described in which the memory cells are NAND flash memory cells, but it will be understood that embodiments of the present inventive concept are not necessarily limited thereto. 
     The memory cell array  110  may include a plurality of memory blocks BLK 1  to BLKz, and each memory block may have a planar structure or a 3-dimensional structure. In an embodiment, the memory cell array  110  may include at least one of a single-level cell block including single-level cells (SLCs), a multi-level cell block including multi-level cells (MLCs), a triple-level cell block including triple-level cells (TLCs), and a quad-level cell block including quad-level cells (QLCs). For example, some memory blocks from among the memory blocks BLK 1  to BLKz may be single-level cell blocks, and the other memory blocks may be multi-level cell blocks, triple-level cell blocks, or quad-level cell blocks. 
     The voltage generator  120  may generate various voltages used in the memory device  100 , such as a program voltage provided to a selected word line for a program operation, a pass voltage provided to an unselected word line, a string select voltage provided to the string select lines SSL and a ground select voltage provided to the ground select lines GSL. 
     According to an embodiment, the voltage generator  120  may generate a first voltage V 1  provided to word lines of a memory block to be recovered during a recovery operation of the memory device  100 . For example, in an embodiment the first voltage V 1  may be simultaneously applied to all of word lines connected to a memory block to be recovered. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment the first voltage V 1  may be applied only to some selected word lines from among a plurality of word lines connected to a memory block to be recovered. According to an embodiment, the voltage generator  120  may generate a second voltage V 2  provided to bit lines connected to a memory block to be recovered. The second voltage V 2  may be transmitted to the page buffer  150 . 
     The control logic  130  may output various internal control signals for programming data to the memory cell array  110  or reading data from the memory cell array  110  based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller  10 . For example, the control logic  130  may output a voltage control signal CTRL_vol for controlling levels of various voltages generated by the voltage generator  120 . According to an embodiment, the control logic  130  may output a control signal for controlling levels of voltages used in a recovery operation for recovering a memory block with degraded reliability. 
     The control logic  130  may provide a row address X-ADDR to the row decoder  140  and provide a column address Y-ADDR to the page buffer  150 . 
     The row decoder  140  may select at least one of word lines of a selected memory block in response to the row address X-ADDR. According to an embodiment, the row decoder  140  may provide the first voltage V 1  to word lines of a memory block to be recovered in response to the row address X-ADDR during a recovery operation. 
     The page buffer  150  may operate in response to the control of the control logic  130 . For example, the page buffer  150  may operate as a write driver or a sense amplifier. According to an embodiment, during a program operation, the page buffer  150  may operate as a write driver and apply a voltage according to data DATA to be stored in the memory cell array  110  to the bit lines BL. According to an embodiment, during a read operation, the page buffer  150  may operate as a sense amplifier and sense data DATA stored in the memory cell array  110 . According to an embodiment, during a recovery operation, the page buffer  150  may provide the second voltage V 2  to the bit line BL in response to the column address Y-ADDR. 
     The control logic  130  may include the recovery control circuit  132 . However, embodiments of the present inventive concept are not necessarily limited thereto, and the recovery control circuit  132  may be provided outside the control logic  130 . 
     According to an embodiment, the recovery control circuit  132  may control the voltage generator  120 , the row decoder  140 , and the page buffer  150 , such that a recovery operation may be performed on memory blocks with degraded reliability from among a plurality of memory blocks included in the memory cell array  110 . For example, a memory block on which a recovery operation is to be performed may be a memory block having a degradation count greater than or equal to the first reference value. The first reference value may differ from one memory block to another. The first reference value may differ from one memory device to another. 
     The recovery control circuit  132  may perform a recovery operation on a degraded memory block, thereby recovering the data retention characteristic of the degraded memory block. 
     According to an embodiment, the recovery control circuit  132  may control the voltage generator  120 , the row decoder  140 , and the page buffer  150  to apply the first voltage V 1  to word lines of a memory block and apply the second voltage V 2  to bit lines of the memory block to perform a recovery operation on the memory block. The first voltage V 1  and the second voltage V 2  may be different from each other. For example, the first voltage V 1  applied to the word line may be a turn-on voltage for turning on memory cells or a pass voltage. The second voltage V 2  applied to bit lines may be a voltage that is higher than voltages applied during a program operation, an erase operation, a read operation, and a pre-charge operation. For example, in an embodiment the first voltage V 1  applied to word lines may be a voltage that is higher than a voltage applied during a program operation. The second voltage V 2  that is applied to bit lines may be a voltage higher than voltages applied during a program operation, an erase operation, a read operation, and a pre-charge operation. 
     According to an embodiment, when the recovery control circuit  132  applies a voltage to word lines, the recovery control circuit  132  may control the memory device  100 , such that the voltage is applied to some selected word lines from among a plurality of word lines connected to a memory block to be recovered. According to an embodiment, when the recovery control circuit  132  applies a voltage to word lines, the recovery control circuit  132  may control the memory device  100 , such that the voltage is applied to all of a plurality of word lines connected to a memory block to be recovered. 
       FIG.  3    is a perspective view showing the memory cell array of  FIG.  2   . 
     Referring to  FIG.  3   , the memory cell array  110  includes the memory blocks BLK 1  to BLKz. Each memory block BLK has a 3-dimensional structure (e.g., a vertical structure). For example, each memory block BLK may include a structure extending in first to third directions. For example, in an embodiment each memory block BLK includes a plurality of NAND strings (e.g., NS 11  to NS 31  of  FIG.  5   ) extending in a second direction. For example, a plurality of NAND stings (e.g., NS 11  to NS 31  of  FIG.  5   ) may be provided in first and third directions. 
     Each NAND string NS is connected to a bit line BL, a string select line SSL, a ground select line GSL, word lines WL, and a common source line CSL. For example, each memory block may be connected to the bit lines BL, the string select lines SSL, the ground select lines GSL, the word lines WL, and the common source line CSL. The memory blocks BLK 1  to BLKz are described in more detail with reference to  FIG.  4   . 
       FIG.  4    is a perspective view of an implementation example of a first memory block from among the memory blocks of  FIG.  2   . 
     Referring to  FIG.  4   , memory blocks included in a memory cell array (e.g.,  110  of  FIG.  2   ) are formed in a vertical direction with respect to a substrate SUB. Although  FIG.  4    shows that the memory block includes two selection lines GSL and SSL, eight word lines WL 1  to WL 8 , and three bit lines BL 1  to BL 3 , embodiments of the present inventive concept are not necessarily limited thereto and the actual numbers may be less than or greater than the above numbers. 
     The substrate SUB has a first conductivity type (e.g., a p type), and common source lines CSL that extend in a first direction and are doped with impurities of a second conductivity type (e.g., an n type) are provided in the substrate SUB. In an embodiment, the substrate SUB may include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin-film substrate obtained by performing a selective epitaxial growth (SEG). The substrate SUB may include a semiconductor material, e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. However, embodiments of the present inventive concept are not necessarily limited thereto. 
     A first memory stack ST 1  may be provided on the substrate SUB. For example, a plurality of insulation layers IL extending in the first direction are sequentially arranged in a third direction in a region of the substrate SUB between two adjacent common source lines CSL (e.g., in the second direction), and the insulation layers IL are a certain distance apart from each other in the third direction. For example, the insulation layers IL may include an insulating material, such as silicon oxide. A plurality of pillars P, which are sequentially arranged by etching in the first direction and penetrate through the insulation layers IL in the third direction, are provided in the region of the substrate SUB between two adjacent common source lines CSL. For example, the pillars P may contact the substrate SUB by penetrating through the insulation layers IL. In an embodiment, a surface layer S of each pillar may include a silicon-based material doped with impurities of the first conductivity type and function as a channel region. In an embodiment, an internal layer I of each pillar may include an insulating material, such as silicon oxide or an air gap. 
     A charge storage layer CS is provided along exposed surfaces of the insulation lavers IL, the pillars P, and the substrate SUB in the region between the two adjacent common source lines CSL. The charge storage layer CS may include a gate insulation layer (also referred to as a ‘tunneling insulation layer’), a charge trapping layer, and a blocking insulation layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Also, gate electrodes GE, such as selected gate lines GSL and SSL and word lines WL 1  through WL 4 , are provided on the exposed surface of the charge storage layer CS in the region between the two adjacent common source lines CSL. 
     In a memory block BLK 1  according to an embodiment of the present inventive concept, a second memory stack ST 2  formed in the same manner as the first memory stack ST 1  may be additionally provided on the first memory stack ST 1  (e.g., in the third direction) formed by the above-described manner. Drains or drain contacts DR are respectively provided on the pillars P extending to the second memory stack ST 2 . For example, the drains or the drain contacts DR may include a silicon-based material doped with impurities of the second conductivity type. Bit lines BL 1  to BL 3  extending in the second direction and arranged a certain distance apart from one another in the first direction are provided on the drain contacts DR. 
       FIG.  5    is a circuit diagram showing an equivalent circuit of a first memory block from among the memory blocks of  FIG.  2   . 
     Referring to  FIG.  5   , the first memory block BLK 1  may be a NAND flash memory having a vertical structure, and each of the memory blocks BLK 1  to BLKz shown in  FIG.  2    may be implemented as shown in  FIG.  5   . The first memory block BLK 1  may include a plurality of NAND cell strings NS 11  to NS 33 , the word lines WL 1  to WL 8 , the bit lines BL 1  to BL 3 , a plurality of ground select lines GSL 1  to GSL 3 , a plurality of string select lines SSL 1  to SSL 3 , and the common source line CSL. However, embodiments of the present inventive concept are not necessarily limited thereto and the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines may vary from those shown in  FIG.  5   . 
     NAND cell strings NS 11 , NS 21 , and NS 31  are provided between a first bit line BLI and the common source line CSL, NAND cell strings NS 12 , NS 22 , and NS 32  are provided between a second bit line BL 2  and the common source line CSL, and NAND cell strings NS 13 , NS 23 , and NS 33  are provided between a third bit line BL 3  and the common source line CSL. In an embodiment, each NAND cell string (e.g., NS 11 ) may include a string select transistor SST, a plurality of memory cells MC 1  to MC 8 , and a ground select transistor GST that are coupled in series. 
     NAND cell strings commonly coupled to one bit line may constitute one column. For example, the NAND cell strings NS 11 , NS 21 , and NS 31  commonly coupled to the first bit line BL 1  may correspond to a first column, the NAND cell strings NS 12 , NS 22 , and NS 32  commonly coupled to the second bit line BL 2  may correspond to a second column, and the NAND cell strings NS 13 , NS 23 , and NS 33  commonly coupled to the third bit line BL 3  may correspond to a third column. 
     NAND cell strings coupled to one string select line may constitute one row. For example, NAND cell strings NS 11 , NS 12 , and NS 13  coupled to a first string select line SSL 1  may correspond to a first row, NAND cell strings NS 21 , NS 22 , and NS 23  coupled to a second string select line SSL 2  may correspond to a second row, and NAND cell strings NS 31 , NS 32 , and NS 33  coupled to a third string select line SSL 3  may correspond to a third row. 
     The string select transistor SST may be coupled to corresponding string select lines SSL 1  to SSL 3 . The memory cells MC 1  to MC 8  may be coupled to corresponding word lines WL 1  to WL 8 , respectively. The ground select transistor GST may be connected to the corresponding ground select lines GSL 1  to GSL 3 , and the string select transistor SST may be connected to the corresponding bit lines BL 1  to BL 3 . The ground select transistor GST may be connected to the common source line CSL. 
     According to an embodiment, word lines of the same height (e.g., WL 1 ) are coupled to each other in common, the string select lines SSL 1  to SSL 3  are separated from one another, and the ground select lines GSL 1  to GSL 3  are also separated from one another. For example, when programming memory cells coupled to a first word line WL 1  and belonging to the NAND cell strings NS 11 , NS 12 , and NS 13  corresponding to a first column, the first word line WL 1  and the first string select line SSL 1  are selected. However, embodiments of the present inventive concept are not necessarily limited thereto, and, according to an embodiment, the ground select lines GSL 1  to GSL 3  may be connected to one another in common. 
       FIG.  6    is a cross-sectional view of a non-volatile memory cell according to an embodiment. 
     Referring to  FIG.  6   , a non-volatile memory cell  600  includes a control gate  610 , a blocking layer  620 , a first semiconductor layer  630 , a tunneling layer  640 , and a source  650 , a drain  660 , a second semiconductor layer  670 , a buried oxide (BOX) layer  680 , and a substrate  690 . 
     When program/erase operations are repeated on the non-volatile memory cell  600 , an unwanted trap site may be formed in the tunneling layer  640 . Therefore, charges trapped in the first semiconductor layer  630  may escape through the tunneling layer  640 , and thus data may be lost. This phenomenon is called vertical charge migration in a direction perpendicular to a channel layer. In a non-volatile memory having a three-dimensional structure, since a plurality of cells constituting one string share the first semiconductor layer  630 , charge migration may occur toward adjacent cells, such as lateral charge migration. Due to the charge migration, the data retention characteristics of a semiconductor device degrades, and thus the reliability of the memory device deteriorates. For example, the charge migration phenomenon becomes more significant as the process becomes finer, e.g., when multi-bit technology is implemented in one cell to increase device integration. Therefore, there is a growing need to reduce the reliability degradation of a non-volatile memory device itself. 
     A non-volatile memory device according to an embodiment may have a substrate having an SOI structure. For example, a bias voltage is applied to the substrate  690  to prevent leakage of data (e.g., charge carriers) stored in the second semiconductor layer  670 . The BOX layer  680  is formed on the substrate  690  and prevents leakage of data stored in the second semiconductor layer  670 . In an embodiment, the BOX layer  680  may include a material having low thermal conductivity, such as SiO 2 , Al 2 O 3 , HfO 2 , etc. In an embodiment, the second semiconductor layer  670  may include silicon, and, in this embodiment the second semiconductor layer  670  and the BOX layer  680  may include an SOI. 
     In an embodiment, the tunneling layer  640  may include, for example, a silicon oxide layer. The first semiconductor layer  630  may include a silicon nitride film or a high-k film having a higher dielectric constant. For example, the first semiconductor layer  630  may include a Si 3 N 4  film, a metal oxide film, a metal nitride film, or a combination thereof. Here, the first semiconductor layer  630  includes a trap site that stores charges passing through the tunneling layer  640 . The first semiconductor layer  630  may be referred to as a charge trapping layer. 
     The blocking layer  620  blocks electrons from escaping to the control gate  610  in the process of being trapped at the trap site of the first semiconductor layer  630  and blocking charges of the control gate  610  from being injected into the first semiconductor layer  630 . In an embodiment in which the first semiconductor layer  630  includes a nitride, a tunneling insulation layer, a first data storage layer, and a blocking insulation layer may have an ONO structure. The control gate  610  may include at least one material selected from a group consisting of TaN, TiN, W, WN, HfN, and tungsten silicide. The control gate  610  may be connected to a corresponding word line and a program voltage may be applied thereto, and the drain  660  may be connected to a corresponding bit line. 
       FIGS.  7 A to  7 C  are cross-sectional views showing that a recovery operation is performed according to embodiments of the present inventive concept. 
       FIG.  7 A  is a cross-sectional view showing non-volatile memory cells according to an embodiment form a string structure.  FIG.  7 A  may show an example of an operation for self-curing of a memory device, such as a recovery operation, according to an embodiment. A memory cell string of  FIG.  7 A  may be a part of a memory block of which reliability is degraded as the degradation counts accumulate. 
     Referring to  FIG.  7 A , a memory cell string  700  includes control gates  711 ,  712 , and  713 , a blocking layer  720 , a first semiconductor layer  730 , a tunneling layer  740 , a second semiconductor layer  750 , and a BOX layer  760 . For example, in an embodiment the first semiconductor layer  730  may be a charge trapping layer, and the second semiconductor layer  750  may be a channel polysilicon. Hereinafter,  FIG.  7 A  will be described with reference to  FIGS.  1  and  2   . 
     According to an embodiment, a word line voltage may be applied through word lines WL 1 , WL 2 , and WLn connected to the control gates  711 ,  712 ,and  713 , respectively. A bit line voltage may be applied through the bit line BL connected to the second semiconductor layer  750 . Although three word lines WL 1 , WL 2 , and WLn are shown in  FIG.  7 A , embodiments of the present inventive concept are not necessarily limited thereto and there may be more or fewer word lines. 
     According to an embodiment, the memory device  100  may receive a first command from the memory controller  10  to perform a recovery operation and may then perform the recovery operation. For example, the first command may be a recovery command. When the recovery operation is performed, the first voltage V 1  may be applied to the word lines WL 1 , WL 2 , and WLn, and the second voltage V 2  may be applied to the bit line BL. A recovery current  770  may flow along a channel of the memory cell string  700  by the first voltage V 1  and the second voltage V 2 . Joule heat is generated in a memory device by the recovery current  770 , and the memory device may recover reliability degradation by using the Joule heat. Detailed descriptions thereof are given below with reference to  FIGS.  7 B and  7 C . 
     According to an embodiment, the first voltage V 1  applied to word lines may be greater than or equal to a turn-on voltage for turning on memory cells or a pass voltage and may be greater than or equal to a voltage applied during the program operation. The second voltage V 2  applied to bit lines may be a voltage higher than voltages applied during a program operation, an erase operation, a read operation, and a pre-charge operation. The first voltage V 1  and the second voltage V 2  may be different from each other. For example, the memory device  100  may perform a recovery operation by applying the first voltage V 1  higher than a turn-on voltage to word lines and applying the second voltage V 2  higher than a voltage applied during a program operation, a read operation, or an erase operation to a bit line. For example, the memory device  100  may perform a recovery operation by applying the first voltage V 1  higher than a turn-on voltage to word lines and applying the second voltage V 2  higher than a pre-charge voltage to a bit line. 
       FIG.  7 B  shows a portion of the cross-section of the memory string shown in  FIG.  7 A . For example,  FIG.  7 B  may show a portion A of  FIG.  7 A . Hereinafter, descriptions identical to those already given above with reference to  FIG.  7 A  may be omitted for economy of description, and.  FIG.  7 B  will be described with reference to  FIGS.  1 ,  2 , and  7 A . 
       FIG.  7 B  shows trapped electrons  781  and trapped holes  782  that are trapped in the tunneling layer  740  as program/erase operations are repeated on a memory block. 
     According to an embodiment, a recovery current  770  may flow along the second semiconductor layer  750  by the first voltage V 1  applied to word lines and the second voltage V 2  applied to a bit line. Joule heat is generated by the recovery current  770 , and the Joule heat may anneal out the trapped electrons  781  and the trapped holes  782 . As the trapped electrons  781  and the trapped holes  782  escape from the tunneling layer  740 , degradation of the data retention characteristics of the memory device  100  may be reduced. 
       FIG.  7 C  shows a portion of the cross-section of the memory string shown in  FIG.  7 A . For example,  FIG.  7 C  may show a portion A of  FIG.  7 A . Hereinafter, descriptions identical to those already given above with reference to  FIG.  7 A  are omitted, and  FIG.  7 C  will be described with reference to  FIGS.  1 ,  2 , and  7 A . 
       FIG.  7 C  shows that unwanted trap sites  783  are formed in the tunneling layer  740  as program/erase operations are repeated on the memory block. 
     According to an embodiment, the recovery current  770  flows along the second semiconductor layer  750  by the first voltage V 1  applied to a word line WLn and the second voltage V 2  applied to the bit line BL. Joule-heat is generated by the recovery current  770 , and the Joule heat may remove the trap sites  783 . As the trap sites  783  are removed and charges trapped in the first semiconductor layer  730  escape through the tunneling layer  740 , degradation of the data retention characteristics of the memory device  100  may be reduced. 
       FIG.  8    is a flowchart of a method of operating a memory system for performing a recovery operation, according to an embodiment.  FIG.  8    may be described below with reference to  FIG.  1   . According to an embodiment, operations S 100  to S 130  may be performed during the idle time of the memory device  100 , such as a period of time in which data is not being read or programmed on the memory device  100 . 
     Referring to  FIG.  8   , in operation S 100 , the memory controller  10  may determine respective degradation counts of a plurality of memory blocks of the memory device  100 . According to an embodiment, a degradation count may be a program/erase count for a memory block indicating the number of times a program/erase operation was performed by the memory block, a read count for a memory block indicating a number of times a read operation was performed by the memory block, or an error bit count indicating a number of error bits of data read from a memory block. However, embodiments of the present inventive concept are not necessarily limited thereto, and a degradation count may be various pieces of information indicating degradation of a memory block. 
     In operation S 110 , the memory controller  10  may compare the degradation counts with the first reference value to determine whether the memory block of the memory device  100  is degraded. Information regarding the first reference value serving as a criterion for determining degradation may be stored in the block management module  11 . In an embodiment, when a degradation count is determined to be less than the first reference value, a recovery operation may not be performed. When a degradation count is determined to be greater than or equal to the first reference value, operation S 120  may be performed. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment, operation S 120  may only be performed when the degradation count is determined to be greater than the first reference value. When the degradation count is determined to be equal to the first reference value, operation S 120  may not be performed. 
     In operation S 120 , the memory controller  10  may transmit a first command to the memory device  100  together with an address of a first memory block, such that the memory device  100  may perform a recovery operation on the first memory block. According to an embodiment, the first command may be a recovery command. 
     In operation S 130 , the memory device  100  may perform a recovery operation in response to the first command received from the memory controller  10 . An example of operation S 130  of recovering a memory block is described in detail below with reference to  FIG.  9   . 
     In an embodiment, the memory controller  10  may initialize a degradation count of a memory block after performing a recovery operation thereon. The memory controller  10  may include (e.g., store) initialization count information regarding initialization counts of memory blocks and information regarding a reference initialization count. As the degradation count of the first memory block is initialized, the memory controller  10  may update the initialization count information. According to an embodiment, when the initialization count reaches the reference initialization count, the first memory block may be determined to be (e.g., set as) a bad block. 
       FIG.  9    is a flowchart of operation S 130  of  FIG.  8    in detail. 
     In operation S 131 , the memory device  100  may receive the first command from the memory controller  10 . In operation S 132 , the memory device  100  may apply the first voltage V 1  to word lines of the first memory block and apply the second voltage V 2  to a bit line of the first memory block to perform a recovery operation on the first memory block. In operation S 133 , the recovery current  770  may flow along a channel of a memory cell string by the first voltage V 1  and the second voltage V 2 . In operation S 134 , Joule heat is generated in a memory device by the recovery current  770 , and the first memory block may recover reliability degradation by using the Joule heat. Therefore, the degraded reliability of the first memory block may be recovered. 
       FIG.  10    is a flowchart of a method of operating a memory system for performing a recovery operation, according to an embodiment. Hereinafter, descriptions identical to those already given above with reference to  FIGS.  8  and  9    will be omitted, and  FIG.  10    will be described with reference to  FIGS.  1 ,  8 , and  9   . 
     Referring to  FIG.  10   , in operation S 200 , the memory controller  10  may check respective program/erase cycles (“PIE cycle” in  FIG.  10   ) of a plurality of memory blocks of the memory device  100 . In operation S 210 , to determine whether the memory blocks of the memory device  100  are degraded, the memory controller  10  may compare the number of program/erase cycles with the first reference value, thereby detecting degraded memory blocks. When the number of the program/erase cycle is less than the first reference value, a recovery operation may not be performed. When the number of the program/erase cycle is greater than or equal to the first reference value, operation S 220  may be performed. 
     In operation S 220 , the memory controller  10  may transmit a second command to the memory device  100  to count the number of error bits of a memory block having a program/erase cycle greater than or equal to the first reference value. 
     In operation S 230 , in response to the second command, the memory device  100  may transmit data stored in a first memory block to the memory controller  10 . The ECC engine  12  included in the memory controller  10  may detect an error by counting the number of error bits of data read from the memory device  100  by using an error correction code and correct the error. When the number of errors is greater than or equal to the number of correctable error bits, error bit correction may fail, and operation S 240  may be performed. When the number of errors is less than the number of correctable error bits, error correction may be successful, and a recovery operation may not be performed. According to some embodiments, in operation S 230 , the memory device  100  may count the numbers of the error bits of memory blocks and transmit the numbers of error bits to the memory controller  10 . The memory controller  10  may compare the numbers of error bits with a reference number. 
     In operation S 240 , the memory controller  10  may transmit a first command to the memory device  100 . According to an embodiment, the first command may be a recovery command. 
     In operation S 250 , the memory device  100  may perform a recovery operation in response to the first command received from the memory controller  10 . 
       FIG.  11    is a flowchart of an embodiment that may be performed after operation S 120  of  FIG.  8   .  FIGS.  12 A to  12 E  are flowcharts for describing operations S 330  to S 350  of  FIG.  11    in detail. 
     Hereinafter, descriptions identical to those already given above with reference to  FIGS.  8  and  9    may be omitted for economy of description.  FIG.  11    will be described with reference to  FIGS.  1 ,  2 , and  12 A to  12 E , 
     Referring to  FIG.  11   , in operation S 330 , a first memory block BLK  1  may be a memory block with degraded reliability. For example, referring to  FIG.  12 A , the degradation count of the first memory block BLK  1  may be greater than or equal to a reference value (e.g., a first reference value). Therefore, the memory controller  10  may determine the first memory block BLK  1  to be a memory block that needs a recovery operation. Data A may be stored in the first memory block BLK 1  before the recovery operation is performed. 
     In operation S 330 , the memory device  100  may copy data of the first memory block BLK  1  and store it on a second memory block BLK  2  that may be a normal block without reliability degradation. For example, referring to  FIG.  12 B , the memory device  100  may copy the data A of the first memory block BLK  1  and store it on the second memory block BLK  2 . In an embodiment, after the data A of the first memory block BLK  1  is copied to and stored on the second memory block BLK  2 , the memory controller  10  may update a mapping table, such that a physical address mapped with a logical address of the data A is re-mapped from a physical address of the first memory block BLK  1  to a physical address of the second memory block BLK  2 . 
     In operation S 340 , the memory device  100  may erase data stored in the first memory block BLK  1 . For example, referring to  FIG.  12 C , the memory device  100  may erase the data A stored in the first memory block BLK  1 . 
     In operation S 350 , the memory device  100  may perform a recovery operation on the first memory block BLK  1 . For example, referring to  FIG.  12 D , the memory device  100  may perform a recovery operation on the first memory block BLK  1 . 
     In an embodiment, after operation S 350 , the memory device  100  may copy the data. A stored in the second memory block BLK  2  and store data A in the first memory block BLK  1 . For example, referring to  FIG.  12 E , the memory device  100  may copy the data A that has been copied to the second memory block BLK  2  to the first memory block BLK  1  on which a recovery operation has been completed. 
       FIG.  13    is a flowchart of an embodiment that may be performed after operation S 120  of  FIG.  8   .  FIGS.  14 A to  14 E  are flowcharts for describing operations S 430  to S 460  of  FIG.  13    in detail. 
     Hereinafter, descriptions identical to those already given above with reference to  FIGS.  8  and  9    may be omitted for economy of description.  FIG.  13    will be described with reference to  FIGS.  1 ,  2 , and  14 A to  14 E . 
     Referring to  FIG.  13   , in operation S 430 , the first memory block BLK  1  and a third memory block BLK  3  may be memory blocks with degraded reliability. For example, referring to  FIG.  14 A , degradation counts of the first memory block BLK  1  and the third memory block BLK  3  may be greater than or equal to the first reference value. The memory controller  10  may determine the first memory block BLK  1  and the third memory block BLK  3  as memory blocks that need a recovery operation performed thereon. Before the recovery operation is performed, data A may be stored in the first memory block BLK  1 , and data B may be stored in the third memory block BLK  3 . 
     In operation S 430 , the memory device  100  may copy data of the first memory block BLK  1  and store it on the second memory block BLK  2 , and may copy data of the third memory block BLK  3  and store it on a fourth memory block BLK  4 . For example, referring to  FIG.  14 B , the memory device  100  may copy the data A of the first memory block BLK  1  and store it on the second memory block BLK  2  and copy the data B of the third memory block BLK  3  and store it on the fourth memory block BLK  4 . In an embodiment, after the data A of the first memory block BLK  1  is copied and stored on the second memory block BLK  2 , the memory controller  10  may update a mapping table, such that a physical address mapped with a logical address of the data A is re-mapped from a physical address of the first memory block BLK  1  to a physical address of the second memory block BLK  2 . Likewise, after the data B of the third memory block BLK  3  is copied and stored on the fourth memory block BLK  4 , the memory controller  10  may update a mapping table, such that a physical address mapped with a logical address of the data B is re-mapped from a physical address of the third memory block BLK  3  to a physical address of the fourth memory block BLK  4 . 
     In operation S 440 , the memory device  100  may erase data of the first memory block BLK  1 . For example, referring to  FIG.  14 C , the memory device  100  may erase the data A of the first memory block BLK  1 . 
     In an embodiment, in operation S 450 , the memory device  100  may erase data of the third memory block BLK  3  simultaneously while performing a recovery operation on the first memory block BLK  1 . For example, referring to  FIG.  14 D , the memory device  100  may perform a recovery operation on the first memory block BLK  1 . At the same time, the memory device  100  may erase the data B of the third memory block BLK  3 . 
     In operation S 460 , the memory device  100  may perform a recovery operation on the third memory block BLK  3 . For example, referring to  FIG.  14 E , the memory device  100  may perform a recovery operation on the third memory block BLK  3 . 
       FIG.  15    is a block diagram showing an example in which a memory device according to an embodiment is applied to an SSD system. 
     Referring to  FIG.  15   , an SSD system  1000  may include a host  1100  and an SSD  1200 . The SSD  1200  may exchange signals with the host  1100  through a signal connector and may receive power through a power connector. The SSD  1200  may include an SSD controller  1210 , an auxiliary power supply device  1220 , and a plurality of memory devices, such as Flash  1   1230 , Flash  2   1240  and Flash n  1250  in which n is an integer greater than or equal to 3. Here, the SSD  1200  may be implemented according to embodiments described above with reference to  FIGS.  1  to  14 E . Therefore, the memory devices  1230 ,  1240 , and  1250  may each perform a recovery operation. In an embodiment, a first reference value serving as a criterion for determining whether a recovery operation is needed may differ from one memory device to another. The memory devices  1230 ,  1240 , and  1250  may each include a recovery control circuit  1232 , and thus, voltages for a recovery operation may be applied to word lines and a bit line of a memory block to be recovered during a recovery operation. Therefore, the reliability of the data retention characteristics of the SSD system  1000  may be increased. 
       FIG.  16    is a diagram showing a method of forming a memory cell array, according to an embodiment. In detail,  FIG.  16    shows a cross-section obtained along a line A-A′ of  FIG.  4   . Descriptions already given above with reference to  FIG.  4    may he omitted for economy of description. 
     Referring to  FIG.  16   , the first memory stack ST 1  may be formed on a plurality of layers formed by the method described above with reference to  FIG.  4    through a first etching Etch 1 . Also, the second memory stack ST 2  may be formed through a second etching Etch 2  on a plurality of layers formed independently from the first memory stack ST 1 . The first memory stack ST 1  and the second memory stack ST 2  may be stacked to be vertically aligned to share channel holes with each other. The first memory stack ST 1  may include a first memory cell MC 1  connected to a second word line WL 2 , and the second memory stack ST 2  may include a second memory cell MC 2  connected to a sixth word line WL 6 . 
     Since the first memory stack ST 1  and the second memory stack ST 2  are formed through the same formation process including the same etching process, widths W 1  and W 2  of channel holes included in memory cells (e.g., MC 1  and MC 2 ) at the same height may form similar profiles to each other. According to an embodiment, a first width W 1  of channel holes included in the first memory cell MC 1  may be the same as or similar to a second width W 2  of channel holes included in the second memory cell MC 2 . Therefore, various operations of the first memory cell MC 1  and the second memory cell MC 2  may be similar. 
       FIG.  17    is a diagram for describing a BVNAND structure that may be applied to an embodiment of the present inventive concept. 
     Referring to  FIG.  17   , the memory device  100  may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first water, and connecting the upper chip and the lower chip to each other through bonding. For example, the bonding may refer to an electric connection between a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding may be a Cu-Cu bonding, and the bonding metal may also include aluminum (Al) or tungsten (W). 
     The peripheral circuit region PERI and the cell region CELL of the memory device  100  may each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. 
     The peripheral circuit region PERI may include a first substrate  210 , an interlayer insulation layer  215 , a plurality of circuit elements  220   a ,  220   b  , and  220   c  formed on the first substrate  210 , first metal layers  230   a  ,  230   b  , and  230   c  respectively connected to the circuit elements  220   a  ,  220   b , and  220   c , and second metal layers  240   a  ,  240   b , and  240   c  respectively formed on the first metal layers  230   a  ,  230   b  , and  230   c . According to an embodiment, the first metal layers  230   a  ,  230   b  , and  230   c  may include tungsten having relatively high electrical resistivity, whereas the second metal layers  240   a  ,  240   b  , and  240   c  may include copper having relatively low electrical resistivity. 
     Although only the first metal layers  230   a  ,  230   b , and  230   c  and the second metal layers  240   a  ,  240   b  , and  240   c  are shown and described in the present specification, embodiments of the present inventive concept are not necessarily limited thereto, and one or more metal layers may be further formed on the second metal layers  240   a  ,  240   b  , and  240   c . At least some of the one or more metal layers formed on the second metal layers  240   a  ,  240   b  , and  240   c  may include a material such as aluminum having a lower electrical resistivity than copper constituting the second metal layers  240   a  ,  240   b , and  240   c.    
     The interlayer insulation layer  215  is provided on the first substrate  210  to cover the circuit elements  220   a  ,  220   b  , and  220   c , the first metal layers  230   a  ,  230   b  , and  230   c , and the second metal layers  240   a  ,  240   b , and  240   c  and may include an insulation material such as a silicon oxide or a silicon nitride. 
     Lower bonding metals  271   b  and  272   b  may be formed on the second metal layer  240   b  in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals  271   b  and  272   b  in the peripheral circuit region PERI may be electrically connected to upper bonding metals  371   b  and  372   b  in the cell region CELL through bonding, wherein the lower bonding metals  271   b  and  272   b  and the upper bonding metals  371   b  and  372   b  may include aluminum, copper, or tungsten. 
     The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate  310  and a common source line  320 . On the second substrate  310 , a plurality of word lines  331  to  338  and  330  may be stacked in a direction perpendicular to the top surface of the second substrate  310  (e.g., a Z-axis direction). String select lines and a ground select line may be arranged on top and bottom of the word lines  330 , and the word lines  330  may be arranged between the string select lines and the ground select line. 
     In the bit line bonding area BLBA, a channel structure CH may extend in a direction (e.g., the Z-axis direction) perpendicular to the top surface of the second substrate  310  and penetrate through the word lines  330 , the string select lines, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulation layer, and the channel layer may be electrically connected to a first metal layer  350   c  and a second metal layer  360   c . For example, the first metal layer  350   c  may be a bit line contact, and the second metal layer  360   c  may be a bit line (hereinafter, referred to as “bit line”). In an embodiment, the bit line  360   c  may extend in a first direction parallel to the top surface of the second substrate  310  (e.g., a Y-axis direction). 
     In an embodiment shown in  FIG.  17   , a region in which the channel structure CH and the bit line  360   c  are arranged may be defined as the bit line bonding area BLBA. The bit line  360   c  may be electrically connected to circuit elements  220   c , which provide a page buffer  393  in the peripheral circuit region PERI, in the bit line bonding area BLBA. For example, the bit line  360   c  is connected to the upper bonding metals  371   c  and  372   c  in the peripheral circuit region PERI, and the upper bonding metals  371   c  and  372   c  may be connected to the lower bonding metals  271   c  and  272   c  that are connected to the circuit elements  220   c  of the page buffer  393 . 
     In the word line bonding area WLBA, the word lines  330  may extend in a second direction (e.g., a X-axis direction) perpendicular to the first direction (e.g., the Y-axis direction) and parallel to the top surface of the second substrate  310  and may be connected to a plurality of cell contact plugs  341  to  347  and  340 . The word lines  330  and the cell contact plugs  340  may be connected to each other at pads provided by at least some of the word lines  330  extending to different lengths in the second direction. A first metal layer  350   b  and a second metal layer  360   b  may be sequentially connected to the top of the cell contact plugs  340  connected to the word lines  330 . In the word line bonding area WLBA, the cell contact plugs  340  may be connected to the peripheral circuit region PERI through the upper bonding metals  371   b  and  372   b  in the cell region CELL and the lower bonding metals  271   b  and  272   b  in the peripheral circuit region PERI 
     The cell contact plugs  340  may be electrically connected to the circuit elements  220   b  that provide a row decoder  394  in the peripheral circuit region PERI. In an embodiment, an operating voltage of the circuit elements  220   b  forming the row decoder  394  may be different from an operating voltage of the circuit elements  220   c  forming the page buffer  393 . For example, the operating voltage of the circuit elements  220   c  forming the page buffer  393  may be greater than the operating voltage of the circuit elements  220   b  forming the row decoder  394 . 
     A common source line contact plug  380  may be provided in the external pad bonding area PA. The common source line contact plug  380  includes a conductive material like a metal, a metal compound, or polysilicon and may be electrically connected to the common source line  320 . A first metal layer  350   a  and a second metal layer  360   a  may be sequentially stacked on the common source line contact plug  380 . For example, an area in which the common source line contact plug  380 , the first metal layer  350   a , and the second metal layer  360   a  are arranged may be defined as the external pad bonding area PA. 
     In an embodiment, first and second input/output pads  205  and  305  may be arranged in the external pad bonding area PA. Referring to  FIG.  17   , a lower insulation layer  201  covering the bottom surface of the first substrate  210  may be formed below the first substrate  210 , and first input/output pads  205  may be formed on the lower insulation layer  201 . The first input/output pad  205  is connected to at least one of the circuit elements  220   a  ,  220   b  , and  220   c  arranged in the peripheral circuit region PERI through a first input/output contact plug  203  and may be separated from the first substrate  210  by a lower insulation layer  201 . Also, a side insulation film may be provided between the first input/output contact plug  203  and the first substrate  210  to electrically separate the first input/output contact plug  203  from the first substrate  210 . 
     In  FIG.  17   , an upper insulation film  301  covering the top surface of the second substrate  310  may be formed on the second substrate  310 , and a second input/output pad  305  may be provided on the upper insulation film  301 . The second input/output pad  305  may be connected to at least one of the circuit elements  220   a  ,  220   b  , and  220   c  arranged in the peripheral circuit region PERI through a second input/output contact plug  303 . According to an embodiment, the second input/output pad  305  may be electrically connected to the circuit element  220   a  , 
     According to an embodiment, the second substrate  310  and the common source line  320  may not be arranged in an area where the second input/output contact plug  303  is provided. Also, the second input/output pad  305  may not overlap the word lines  330  in the third direction (e.g., the Z-axis direction). Referring to  FIG.  17   , the second input/output contact plug  303  is separated from the second substrate  310  in a direction parallel to the top surface of the second substrate  310  and may penetrate through the interlayer insulation layer  315  in the cell region CELL and may be connected to the second input/output pad  305 . 
     According to an embodiment, the first input/output pad  205  and the second input/output pad  305  may be selectively formed. For example, the memory device  100  may include only the first input/output pad  205  provided on the first substrate  210  or only the second input/output pad  305  provided on the second substrate  310 . Alternatively, the memory device  100  may include both the first input/output pad  205  and the second input/output pad  305 . 
     In each of the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell region CELL and the peripheral circuit region PERI, a metal pattern of an uppermost metal layer may exist as a dummy pattern or the uppermost metal layer may be omitted. 
     In the memory device  100 , in the external pad bonding area PA, in correspondence to an upper metal pattern  372   a  formed on the uppermost metal layer in the cell region CELL, a lower metal pattern  273   a  having the same shape as the upper metal pattern  372   a  in the cell region CELL may be formed on the uppermost metal layer in the peripheral circuit region PERI. The lower metal pattern  273   a  formed on the uppermost metal layer in the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, in correspondence to the lower metal pattern  273   a  formed on the uppermost metal layer in the peripheral circuit region PERI, the upper metal pattern  372   a  having the same shape as the lower metal pattern  273   a  in the peripheral circuit region PERI may be formed on the uppermost metal layer in the cell region CELL. 
     Lower bonding metals  271   b  and  272   b  may be formed on the second metal layer  240   b  in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals  271   b  and  272   b  in the peripheral circuit region PERI may be electrically connected to upper bonding metals  371   b  and  372   b  in the cell region CELL through bonding. 
     Also, in the bit line bonding area BLBA, in correspondence to a lower metal pattern  252  formed on the uppermost metal layer in the peripheral circuit region PERI, an upper metal pattern  392  having the same shape as the lower metal pattern  252  may be formed on the uppermost metal layer in the cell region CELL. A contact may not be formed on the upper metal pattern  392  formed on the uppermost metal layer in the cell region CELL. 
     While the present inventive concept has been particularly shown and described with reference to non-limiting embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.