Patent Publication Number: US-9419521-B2

Title: Control method and control apparatus using control signals to control states of transistors in BUCK-BOOST topology

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of International Application No. PCT/CN2013/071614, filed on Feb. 17, 2013, which claims priority to Chinese Patent Application No. 201210249141.8, filed on Jul. 18, 2012, both of which are hereby incorporated by reference in their entireties. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     Not applicable. 
     REFERENCE TO A MICROFICHE APPENDIX 
     Not applicable. 
     TECHNICAL FIELD 
     The present invention relates to the field of communications technologies, and in particular, to a control method and a control apparatus. 
     BACKGROUND 
     With the increase of the power of a router, an entire enterprise network equipment, and a board, some high-power subrack-shaped equipment requires that a direct current/direct current (DC/DC) voltage regulator module in a system supports flexible configuration, so as to meet customers&#39; requirements for investment and power distribution in an equipment room. To improve the conversion efficiency of a DC/DC voltage regulator module, a single-inductor buck-boost (BUCK-BOOST) topology is used, which is a topological structure supporting a DC/DC voltage regulator module in achieving high efficiency. 
       FIG. 1  is a circuit diagram of a single-inductor buck-boost topology in the prior art. As illustrated in  FIG. 1 , a metal-oxide-semiconductor field-effect transistor (MOSFET) T 1 , a MOSFET T 3 , an inductor L 1  form a buck conversion circuit, that is, a BUCK circuit, and a MOSFET T 2 , a MOSFET T 4 , the inductor L 1  form a boost conversion circuit, that is, a BOOST circuit. The circuit of the topology needs to, based on an input signal, perform a switchover among three topology states: buck, pass, and boost. 
     Currently, a method for controlling a switchover among three topology states is to check the state of an input signal by using three comparators. The state of an input signal is transmitted to a complex programmable logic device (CPLD) by using an optocoupler. Then, the CPLD determines the state of the BUCK-BOOST topology based on the state of the input signal. Finally, a pulse width modulation (PWM) controller controls a switchover among three topology states based on the state of the BUCK-BOOST topology. For example, when an input signal is in the range from 36 volts (V) to 48V, the topology enters the BOOST state; when the input signal is in the range from 46V to 54V, the topology enters the PASS state; and when the input signal is in the range from 52V to 72V, the topology enters the BUCK state. When a topology state switchover is being performed, the state of the PWM controller also changes suddenly. To prevent the state of a PWM controller from changing suddenly, a soft start needs to be implemented during a switchover among three topology states: buck, boost, and pass. The foregoing control method is capable of achieving a switchover among three topology states: BUCK, PASS, and BOOST. 
     However, specific implementation of the control method is very complicated, and the implementation circuit includes a power nonconventional device like CPLD. In addition, because the adjustment output signal in the BUCK state is different from the adjustment output signal in the BOOST state due to the issue related to the maximum duty cycle of a PWM controller, different modules cannot be in the BUCK state and the BOOST state simultaneously, directly resulting in that different modules cannot work in a scenario in which input signals dramatically differ from each other. The prior art cannot meet the demand that a system requires a plurality of DC/DC voltage regulator modules to work in parallel and achieve current equalization. 
     SUMMARY 
     Embodiments of the present invention provide a control method and a control apparatus to resolve, to a certain extent, problems in the prior art that a control circuit is complicated and that a soft start needs to be implemented during a state switchover, thus achieving a smooth switchover among three topology states. 
     In the first aspect, a control method is provided in the present invention. The method is applied to a BUCK-BOOST topology, and includes: processing an output signal of the topology to obtain a PWM signal; performing an OR operation between the PWM signal and a first modulation signal to obtain a first control signal, so as to control a state of a first transistor on the topology; and performing an AND operation between the PWM signal and a second modulation signal to obtain a second control signal, so as to control a state of a second transistor on the topology. 
     In the second aspect, a control apparatus is provided in the present invention. The apparatus is applied to a BUCK-BOOST topology, and includes a PWM signal generating circuit, an OR gate, and an AND gate. An input end of the PWM signal generating circuit is connected to an output end of the topology, an output end of the PWM signal generating circuit is connected to each of an input end of the OR gate and an input end of the AND gate, an output end of the OR gate is connected to a gate of a first transistor on the topology, and an output end of the AND gate is connected to a gate of a second transistor on the topology. The PWM signal generating circuit is configured to process an output signal of the topology to obtain a PWM signal, and to transmit the PWM signal to the OR gate and the AND gate. The OR gate is configured to receive the PWM signal from the PWM signal generating circuit, and perform an OR operation between the PWM signal and a first modulation signal to obtain a first control signal, so as to control a state of the first transistor on the topology. The AND gate is configured to receive the PWM signal from the PWM signal generating circuit, and perform an AND operation between the PWM signal and a second modulation signal to obtain a second control signal, so as to control a state of the second transistor on the topology. 
     Therefore, the method and apparatus disclosed in embodiments of the present invention use a PWM signal generating circuit to process an output signal of a topology to obtain a PWM signal; perform an OR operation between the PWM signal and a first modulation signal to obtain a first control signal, so as to control a state of a first transistor on the topology, where the first transistor may be in switch mode or constant on mode; and perform an AND operation between the PWM signal and a second modulation signal to obtain a second control signal, so as to control a state of a second transistor on the topology, where the second transistor may be in constant off mode or switch mode. When the first transistor is in switch mode and the second transistor is in constant off mode, the topology is in the BUCK state; when the first transistor is in constant on mode and the second transistor is in switch mode, the topology is in the BOOST state; and when the first transistor is in constant on mode and the second transistor is in constant off mode, the topology is in the PASS state. Application of the method and apparatus disclosed in embodiments of the present invention can achieve three topology states and a smooth switchover among the three topology states. In addition, the control circuit is relatively simple, expanding the control scope and improving the control precision. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a single-inductor BUCK-BOOST topology according to Embodiment 1 of the present invention; 
         FIG. 2  is a flowchart of a control method according to Embodiment 2 of the present invention; 
         FIG. 3  is a schematic diagram of a PWM signal generating circuit according to Embodiment 3 of the present invention; 
         FIG. 4  is a schematic diagram of a first modulation signal, a second modulation signal, a PWM signal, a first control signal, and a second control signal in a control method according to Embodiment 4 of the present invention; 
         FIG. 5  is a schematic diagram of a first modulation signal, a second modulation signal, a PWM signal, a first control signal, and a second control signal in a control method according to Embodiment 5 of the present invention; 
         FIG. 6  is a schematic diagram of a first modulation signal, a second modulation signal, a PWM signal, a first control signal, and a second control signal in a control method according to Embodiment 6 of the present invention; 
         FIG. 7  is a schematic diagram of a first modulation signal, a second modulation signal, a PWM signal, a first control signal, and a second control signal in a control method according to Embodiment 7 of the present invention; 
         FIG. 8  is a schematic diagram of a first modulation signal, a second modulation signal, a PWM signal, a first control signal, and a second control signal in a control method according to Embodiment 8 of the present invention; 
         FIG. 9  is a schematic diagram of a first modulation signal, a second modulation signal, a PWM signal, a first control signal, and a second control signal in a control method according to Embodiment 9 of the present invention; 
         FIG. 10  is a schematic diagram of a first modulation signal, a second modulation signal, a PWM signal, a first control signal, and a second control signal in a control method according to Embodiment 10 of the present invention; 
         FIG. 11  is a schematic diagram of a first modulation signal, a second modulation signal, a PWM signal, a first control signal, and a second control signal in a control method according to Embodiment 11 of the present invention; 
         FIG. 12  is a schematic structural diagram of a control apparatus according to Embodiment 12 of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the following clearly describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are merely a part rather than all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. 
     The present invention discloses a control method and a control apparatus. By processing an output signal of a BUCK-BOOST topology to obtain a PWM signal; performing an OR operation between the PWM signal and a first modulation signal to obtain a first control signal and simultaneously performing an AND operation between the PWM signal and a second modulation signal to obtain a second control signal; and using the first control signal and the second control signal to control the high-side transistor of the BUCK circuit and the low-side transistor of the BOOST circuit on the BUCK-BOOST topology, a smooth switchover among three states of the BUCK-BOOST topology is achieved and a special soft start operation is not required. 
       FIG. 1  is a circuit diagram of a single-inductor BUCK-BOOST topology according to Embodiment 1 of the present invention. As illustrated in the figure, a single-inductor BUCK-BOOST topology primarily includes a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4 , and an inductor L 1 . The first transistor T 1 , the third transistor T 3 , and the inductor L 1  form a BUCK circuit, where the first transistor T 1  is the high-side transistor of the BUCK circuit and the third transistor T 3  is the low-side transistor of the BUCK circuit. The second transistor T 2 , the fourth transistor T 4 , and the inductor L 1  form a BOOST circuit, where the second transistor T 2  is the low-side transistor of the BOOST circuit and the fourth transistor T 4  is the high-side transistor of the BOOST circuit. Additionally, the voltage of an input signal of the topology is represented by V i , and the voltage of an output signal of the topology is represented by V o . When the voltage V i  of an input signal is higher than the voltage V o  of an output signal, the first transistor T 1  and the third transistor T 3  are in switch mode, the second transistor T 2  is in constant off mode, and the fourth transistor T 4  is in constant on mode. In this case, the state of the topology is defined as the BUCK state. When the voltage V, of an input signal is very close to the voltage V o  of an output signal, the second transistor T 2  and the third transistor T 3  are in constant off mode, and the first transistor T 1  and the fourth transistor T 4  are in constant on mode. In this case, the state of the topology is defined as the PASS state. When the voltage V i  of an input signal is lower than the voltage V o  of an output signal, the second transistor T 2  and the fourth transistor T 4  are in switch mode, the third transistor T 3  is in constant off mode, and the first transistor T 1  is in constant on mode. In this case, the state of the topology is defined as the BOOST state. When the topology is in the BUCK state, the BUCK circuit enters the switch mode and the BOOST circuit enters the constant on mode; when the topology is in the BOOST state, the BUCK circuit enters the constant on mode and the BOOST circuit enters the switch mode; when the topology is in the PASS state, both the BUCK circuit and the BOOST circuit enter the constant on mode. 
     The first transistor T 1  and the second transistor T 2  are switch transistors, for example, a triode, a MOSFET transistor, or an insulated-gate bipolar transistor (IGBT). The third transistor T 3  and the fourth transistor T 4  may also be switch transistors or diodes. 
     When the third transistor T 3  and the fourth transistor T 4  are diodes, taking the BUCK circuit as an example, the first transistor T 1 , that is, the high-side transistor of the BUCK circuit, is a switch transistor, and the third transistor T 3 , that is, the low-side transistor of the BUCK circuit, is a diode. When the high-side transistor of the BUCK circuit conducts, the diode T 3  bears a reverse voltage at both ends, and as a result, the diode T 3  turns off, that is, enters the off state. When the high-side transistor of the BUCK circuit turns off, because the current in the inductor L will freewheel, the freewheeling current forces the diode T 3  to conduct, that is, to enter the on state. Therefore, when a diode is used, the diode turns off when the high-side transistor conducts, and conducts when the high-side transistor turns off. The conduction relationship of a diode is the same as the switching sequence when a low-side transistor is a switch transistor, and details are not provided herein again. 
     The foregoing “switch mode” indicates that both the on and off states exist in a cycle time. For example, it is assumed that the frequency of a switching mode power supply is 100 kilohertz (kHz) and the cycle T of the switching mode power supply is 10 microseconds (us). It is also assumed that the duty cycle of a transistor is 30%. That is, the transistor is on in 30% of the time and off in 70% of the time, or is on in 3 us and off in 7 us. The transistor also enters this on/off state in a next cycle. Therefore, the “switch mode” mentioned in all the following embodiments provided for the present invention indicates that both the on and off states exist in a cycle time. 
       FIG. 2  is a flowchart of a control method according to an embodiment of the present invention. As shown in the figure, the embodiment of the present invention specifically includes the following steps: 
     Step  210 : Process an output signal of a single-inductor BUCK-BOOST topology to obtain a PWM signal, that is, a PWM modulation signal. In the prior art, a circuit generating a PWM modulation signal is a PWM modulation signal generating circuit. The PWM modulation signal generating circuit generally consists of a loop circuit and a comparator. 
     Specifically, the working principles of the PWM modulation signal generating circuit are as follows: when the voltage V o  of an output signal increases, resulting in that the voltage V fb  of a feedback signal is higher than the voltage V ref  of a reference signal, the voltage of a loop COMP signal output by the loop circuit decreases, and after the voltage of the loop COMP signal is compared with the voltage of a comparison signal, the duty cycle of an output PWM modulation signal decreases, with the final aim of decreasing the voltage V o  of the output signal; when the voltage V o  of the output signal decreases, resulting in that the voltage V fb  of the feedback signal is lower than the voltage V ref  of the reference signal, the voltage of a loop COMP signal output by the loop circuit increases, and after the voltage of the loop COMP signal is compared with the voltage of the comparison signal, the duty cycle of an output PWM modulation signal increases, with the final aim of increasing the voltage V o  of the output signal. 
     The following describes how to obtain the PWM modulation signal based on the output signal of the topology in detail. 
     First, obtain the loop signal based on the output signal of the topology and the reference signal. 
     Specifically, an operational amplifier on the loop circuit performs operational amplification on an input feedback signal of the output signal of the topology and on the reference signal. When the voltage of the feedback signal is higher than the voltage of the reference signal, the voltage of the output signal of the operational amplifier decreases, and when the voltage of the feedback signal is lower than the voltage of the reference signal, the voltage of the output signal of the operational amplifier increases. In this way, the loop signal is obtained. Its used circuit is a typical loop circuit, as illustrated in  FIG. 3 . The loop circuit is a negative feedback circuit, consisting of an operational amplifier X 1 , peripheral capacitors C 1 , C 2 , and C 3 , and resistors R 1 , R 2 , R 3 , and R 4 , where, at the negative input end of the operational amplifier X 1 , the voltage V fb  of the feedback signal of the voltage V o  of the output signal is input. The relationship between the voltage V fb  of the feedback signal and the voltage V o  of the output signal is shown in Formula (1). 
     
       
         
           
             
               
                 
                   
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     At the positive input end of the operational amplifier X 1 , the voltage V ref  of the reference signal is input, where the value range of the voltage V ref  of the reference signal is self-defined, ranging from 0.8V to 3V. Generally, voltage adjustment on a digital switchmode power supply is achieved by adjusting V ref . Finally, after the operational amplifier X 1  performs an operation, the loop circuit outputs the voltage of the loop COMP signal. The relationship between the voltage V o  of the output signal and the voltage of the COMP signal is as follows: when the voltage V o  of the output signal increases, resulting in that the voltage V fb  of the feedback signal of the voltage V o  of the output signal is higher than the voltage V ref  of the reference signal, the operational amplifier X 1  outputs a low level, that is, the COMP level decreases, resulting in that the duty cycle of an output PWM signal decreases and finally the output voltage V o  decreases; when the voltage V o  of the output signal decreases, the voltage of the COMP signal increases, resulting in that the duty cycle of the output PWM signal increases and finally the output voltage V o  increases. Therefore, the function of the loop circuit is, through such a negative feedback function, to enable V fb  to be equal to V ref , and finally ensure that the voltage V o  of the output signal stabilizes at a fixed value. 
     Second, obtain the PWM signal based on the loop signal and the comparison signal. 
     Specifically, the loop signal and the comparison signal, for example, a sawtooth wave signal, are input into a comparator X 2 , as illustrated in  FIG. 3 . After the comparator X 2  performs comparison, a PWM modulation signal is obtained. The loop signal is input into the positive input end of the comparator X 2 , and the comparison signal is input into the negative input end of the comparator X 2 . The comparison signal may be a sawtooth wave, a triangular wave, a resistor-capacitor (RC) charging waveform, or a voltage signal converted from current sampling, and so on. The working principles of the comparator X 2  are as follows: when the voltage of the loop signal is higher than the voltage of the comparison signal, the comparator X 2  outputs a high level, and when the voltage of the loop signal is lower than the voltage of the comparison signal, the comparator X 2  outputs a low level; in this way, the PWM signal is obtained. 
     The foregoing loop circuit or comparator may be achieved using an analog circuit or a digital circuit. Both analog and digital circuits are relatively mature technologies among existing technologies, so details are not provided herein again. The embodiments of the present invention may use any PWM modulation signal generating circuit. Therefore, all PWM modulation signal generating circuits apply to the present invention. 
     Step  220 : Perform an OR operation between the PWM modulation signal and a first modulation signal D 1  to obtain a first control signal S 1 , so as to control a state of a first transistor T 1  on the topology; perform an AND operation between the PWM modulation signal and a second modulation signal D 2  to obtain a second control signal S 2 , so as to control a state of a second transistor T 2  on the topology, where the first modulation signal, the second modulation signal, and the PWM modulation signal are synchronous, and the falling edges of the first modulation signal and the second modulation signal and the rising edge of the PWM modulation signal occur at the same time. 
     Specifically, the PWM modulation signal and the first modulation signal D 1  are input into an OR gate U 1 , the first control signal S 1  is obtained after the OR gate U 1  performs an operation on the signals, and the OR gate U 1  uses the first control signal S 1  to control the first transistor T 1  on the single-inductor BUCK-BOOST topology, where, an input end of the OR gate U 1  inputs the PWM modulation signal, and another input end inputs the first modulation signal D 1 , where the first modulation signal D 1  is pre-set based on actual situations. 
     Specifically, the PWM modulation signal and the second modulation signal D 2  are input into an AND gate U 2 , the second control signal S 2  is obtained after the AND gate U 2  performs an operation on the signals, and the AND gate U 2  uses the second control signal S 2  to control the second transistor T 2  on the single-inductor BUCK-BOOST topology, where, an input end of the AND gate U 2  inputs the PWM modulation signal, and another input end inputs the second modulation signal D 2 , where the second modulation signal D 2  is pre-set based on actual situations. 
     The first control signal controls the first transistor on the single-inductor BUCK-BOOST topology, the signal obtained after a first NOT gate performs a NOT operation on the first control signal S 1  controls a third transistor T 3  on the topology, and the signal obtained after a second NOT gate performs a NOT operation on the second control signal S 2  controls a fourth transistor T 4  on the topology. 
     Additionally, the third transistor T 3  and the fourth transistor T 4  may be switch transistors or diodes. When the third transistor T 3  and the fourth transistor T 4  are switch transistors, they need to be controlled by the first control signal S 1  and the second control signal S 2 . When the third transistor T 3  and the fourth transistor T 4  are diodes, they do not need to be controlled by the signal obtained after the first NOT gate performs a NOT operation on the first control signal S 1  and by the signal obtained after the second NOT gate performs a NOT operation on the second control signal S 2 . A diode is capable of automatically performing an on-off action. 
     The following takes the assumption that the third transistor T 3  and the fourth transistor T 4  are switch transistors as an example to describe how the control method provided in embodiments of the present invention achieves the three topology states BUCK, PASS, and BOOST in detail. The duty cycle of the first modulation signal D 1  is represented by r 1 , the duty cycle of the second modulation signal D 2  is represented by r 2 , the duty cycle of the PWM signal is represented by r, the duty cycle of the first control signal S 1  is represented by z 1 , and the duty cycle of the second control signal S 2  is represented by z 2 . In addition, 1−r 1 , that is, the difference between 1 and the duty cycle of the first modulation signal D 1 , is a first threshold, and 1−r 2 , that is, the difference between 1 and the duty cycle of the second modulation signal D 2 , is a second threshold. 
     First, the process of how the BUCK state is achieved is described. 
     When the duty cycle r of the PWM modulation signal is less than 1−r 1  and less than or equal to 1−r 2 : the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain the first control signal S 1 , to control the first transistor T 1  on a topology to be in switch mode, where the duty cycle z 1  of the first control signal S 1  is r+r 1 ; the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain the low-level second control signal S 2 , to control the second transistor T 2  on the topology to be in constant off mode, where the duty cycle z 2  of the second control signal S 2  is 0; a NOT operation is performed on the first control signal S 1 , to control the third transistor T 3  on the topology to be in switch mode, and in this case, the BUCK circuit is in the BUCK state; a NOT operation is performed on the second control signal S 2 , to control the fourth transistor T 4  on the topology to be in constant on mode, and in this case, the BOOST circuit is in the PASS state. Therefore, in this case, the topology is in the BUCK state. 
     For example, reference is made to  FIG. 4 . When the duty cycle r 1  of the first modulation signal D 1  is greater than the duty cycle r 2  of the second modulation signal D 2 , assuming that the duty cycle r 1  of the first modulation signal D 1  is 54%, that the duty cycle r 2  of the second modulation signal D 2  is 44%, and that the duty cycle r of the PWM modulation signal is 30%, the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain that the duty cycle z 1  of the first control signal S 1  is 84%, and the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain that the duty cycle z 2  of the second control signal S 2  is 0. Therefore, in this case, the topology is in the BUCK state. 
     Reference is made to  FIG. 5 . When the duty cycle r 1  of the first modulation signal D 1  is less than the duty cycle r 2  of the second modulation signal D 2 , assuming that the duty cycle r 1  of the first modulation signal D 1  is 44%, that the duty cycle r 2  of the second modulation signal D 2  is 54%, and that the duty cycle r of the PWM modulation signal is 30%, the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain that the duty cycle z 1  of the first control signal S 1  is 74%, and the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain that the duty cycle z 2  of the second control signal S 2  is 0. Therefore, in this case, the topology is in the BUCK state. 
     Reference is made to  FIG. 6 . When the duty cycle r 1  of the first modulation signal D 1  is equal to the duty cycle r 2  of the second modulation signal D 2 , assuming that the duty cycle r 1  of the first modulation signal D 1  is 50%, that the duty cycle r 2  of the second modulation signal D 2  is 50%, and that the duty cycle r of the PWM modulation signal is 30%, the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain that the duty cycle z 1  of the first control signal S 1  is 80%, and the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain that the duty cycle z 2  of the second control signal S 2  is 0. Therefore, in this case, the topology is in the BUCK state. 
     Second, the process of how the BOOST state is achieved is described. 
     When the duty cycle r of the PWM modulation signal is greater than 1−r 2  and greater than or equal to 1−r 1 : the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain the high-level first control signal S 1 , to control the first transistor T 1  on the topology to be in constant on mode, where the duty cycle z 1  of the first control signal S 1  is 100%; the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain the second control signal S 2 , to control the second transistor T 2  on the topology to be in switch mode, where the duty cycle z 2  of the second control signal S 2  is r−(1−r 2 ); a NOT operation is performed on the first control signal S 1 , to control the third transistor T 3  on the topology to be in constant off mode, and in this case, the BUCK circuit is in the PASS state; a NOT operation is performed on the second control signal S 2 , to control the fourth transistor T 4  on the topology to be in switch mode, and in this case, the BOOST circuit is in the BOOST state. Therefore, in this case, the topology is in the BOOST state. 
     For example, reference is made to  FIG. 7 . When the duty cycle r 1  of the first modulation signal D 1  is greater than the duty cycle r 2  of the second modulation signal D 2 , assuming that the duty cycle r 1  of the first modulation signal D 1  is 54%, that the duty cycle r 2  of the second modulation signal D 2  is 44%, and that the duty cycle r of the PWM modulation signal is 70%, the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain that the duty cycle z 1  of the first control signal S 1  is 100%, and the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain that the duty cycle z 2  of the second control signal S 2  is 14%. Therefore, in this case, the topology is in the BOOST state. 
     Reference is made to  FIG. 8 . When the duty cycle r 1  of the first modulation signal D 1  is less than the duty cycle r 2  of the second modulation signal D 2 , assuming that the duty cycle r 1  of the first modulation signal D 1  is 44%, that the duty cycle r 2  of the second modulation signal D 2  is 54%, and that the duty cycle r of the PWM modulation signal is 70%, the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain that the duty cycle z 1  of the first control signal S 1  is 100%, and the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain that the duty cycle z 2  of the second control signal S 2  is 24%. Therefore, in this case, the topology is in the BOOST state. 
     Reference is made to  FIG. 9 . When the duty cycle r 1  of the first modulation signal D 1  is equal to the duty cycle r 2  of the second modulation signal D 2 , assuming that the duty cycle r 1  of the first modulation signal D 1  is 50%, that the duty cycle r 2  of the second modulation signal D 2  is 50%, and that the duty cycle r of the PWM modulation signal is 70%, the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain that the duty cycle z 1  of the first control signal S 1  is 100%, and the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain that the duty cycle z 2  of the second control signal S 2  is 20%. Therefore, in this case, the topology is in the BOOST state. 
     Third, the process of how the PASS state is achieved is described. 
     Assuming that the duty cycle r 1  of the first modulation signal D 1  is greater than the duty cycle r 2  of the second modulation signal D 2 , when the duty cycle r of the PWM modulation signal is greater than 141 and less than 1−r 2 : the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain the high-level first control signal S 1 , to control the first transistor T 1  on the topology to be in constant on mode, where the duty cycle z 1  of the first control signal S 1  is 100%; the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain the low-level second control signal S 2 , to control the second transistor T 2  on the topology to be in constant off mode, where the duty cycle z 2  of the second control signal S 2  is 0; a NOT operation is performed on the first control signal S 1 , to control the third transistor T 3  on the topology to be in constant off mode, and in this case, the BUCK circuit is in the PASS state; a NOT operation is performed on the second control signal S 2 , to control the fourth transistor T 4  on the topology to be in constant on mode, and in this case, the BOOST circuit is in the PASS state. Therefore, in this case, the topology is in the PASS state. 
     For example, reference is made to  FIG. 10 . Assuming that the duty cycle r 1  of the first modulation signal D 1  is 54%, that the duty cycle r 2  of the second modulation signal D 2  is 44%, and that the duty cycle r of the PWM modulation signal is 51%, the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain that the duty cycle z 1  of the first control signal S 1  is 100%, and the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain that the duty cycle z 2  of the second control signal S 2  is 0. Therefore, in this case, the topology is in the PASS state. 
     In addition, the entering to the PASS state may also be achieved by checking the level of a loop COMP signal. Specifically, directly enabling, after determining that the level of a loop COMP signal is in the range from a first level threshold to a second level threshold, both the high-side transistor of a BUCK circuit and the high-side transistor of a BOOST circuit to be in constant on mode, may also enable a single-inductor BUCK-BOOST topology to enter the PASS state. 
     The foregoing method for achieving the PASS state has a problem: even though the voltage difference between an input voltage and an output voltage is very small, due to the effect of loop integration, a loop circuit, sooner or later, results in that a COMP signal exceeds the signal range of the PASS state, or the duty cycle of the PWM modulation signal r exceeds the (1−r 1 )˜(1−r 2 ) range, and consequently, the circuit switches over repeatedly between the PASS state and a non-PASS state. Using the following method can achieve the absolute PASS state: detecting an input signal V i  an output signal V o , and output currents, and forcibly maintaining, when the input signal V i  and the output signal V o  are approximately equal to each other and when the output current of each module is relatively balanced, the level of the loop signal in the signal range within which the BUCK-BOOST topology is in the PASS state. This method uses the manner of clamping the COMP level to achieve the PASS state, and ensures a very high efficiency for a voltage regulating DC/DC module in a system when the input voltage and the output voltage are close to each other. 
     Further, when it is assumed that the duty cycle r 1  of the first modulation signal D 1  is less than the duty cycle r 2  of the second modulation signal D 2 , and when the duty cycle r of the PWM modulation signal is greater than 1−r 2  and less than 1−r 1  : the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain the first control signal S 1 , to control the first transistor T 1  on the topology to be in switch mode, where the duty cycle z 1  of the first control signal S 1  is equal to r+r 1 ; the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain the second control signal S 2 , to control the second transistor T 2  on the topology to be in switch mode, where the duty cycle z 2  of the second control signal S 2  is r-(1−r 2 ); a NOT operation is performed on the first control signal S 1 , to control the third transistor T 3  on the topology to be in switch mode, and in this case, the BUCK circuit is in the BUCK state; a NOT operation is performed on the second control signal S 2 , to control the fourth transistor T 4  on the topology to be in switch mode, and in this case, the BOOST circuit is in the BOOST state. Therefore, in this case, the topology is in the BUCK-BOOST state. 
     For example, reference is made to  FIG. 11 . Assuming that the duty cycle r 1  of the first modulation signal D 1  is 44%, that the duty cycle r 2  of the second modulation signal D 2  is 54%, and that the duty cycle r of the PWM modulation signal is 51%, the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain that the duty cycle z 1  of the first control signal S 1  is 95%, and the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain that the duty cycle z 2  of the second control signal S 2  is 5%. Therefore, in this case, the topology is in the BUCK-BOOST state. 
     In addition, the control method provided in embodiments of the present invention also ensures a smooth switchover between the BUCK state and the BOOST state. For example, when the duty cycle of a first modulation signal is 55%, the duty cycle of a second modulation signal is 45%, the voltage V i  of an input signal is a high voltage, for example, 75V, and the voltage V o  of an output signal is 50V, the BUCK-BOOST topology works in the BUCK state. When the input signal jumps, that is, the voltage of the input signal falls from a high voltage to a relatively low voltage, for example, jumping from 75V to 36V, the duty cycle of the PWM signal output by the loop circuit and the comparator changes from a small value to a large value. After the AND gate and the NOT gate perform operations for the PWM signal, the duty cycle of the first control signal gradually becomes larger and larger until the first transistor T 1 , that is, the high-side transistor of the BUCK circuit, is completely in constant on mode and the BUCK-BOOST topology enters the PASS state. When the duty cycle of the PWM modulation signal further increases, the duty cycle of the low-side transistor of the BOOST circuit starts to increase slowly from 0, until the BUCK-BOOST topology enters the BOOST state. During the entire switchover from the BUCK state to the BOOST state, the duty cycle of the high-side transistor of the BUCK circuit gradually increases until it enters the constant on mode, and the duty cycle of the low-side transistor of the BOOST circuit gradually increases from 0. The switchover process is very smooth and does not require an extra soft start operation. Additionally, this control method also ensures that different voltage regulating DC/DC modules in a system can work normally in the scenario in which the input voltage difference is relatively large. 
     Therefore, the control method provided in embodiments of the present invention, by processing an output signal of a single-inductor BUCK-BOOST topology to obtain a PWM signal, performing an OR operation between the PWM signal and a first modulation signal to obtain a first control signal so as to control a first transistor on the topology, and simultaneously performing an AND operation between the PWM signal and a second modulation signal to obtain a second control signal so as to control a second transistor, three topology states BUCK, PASS, and BOOST are achieved, and a smooth switchover among the three topology states is achieved, and a special soft start operation is not required. The method, with simple implementation, can be applied in different input signal scenarios. 
       FIG. 12  is a schematic diagram of a topology control apparatus according to an embodiment of the present invention. The apparatus is applied to a single-inductor BUCK-BOOST topology. As illustrated in the figure, the topology control apparatus provided in the embodiment specifically includes: a PWM signal generating circuit  11 , an OR gate  13 , and an AND gate  14 . 
     An input end of the PWM signal generating circuit  11  is connected to an output end of the topology, an output end of the PWM signal generating circuit  11  is connected to an input end of the OR gate  13  and an input end of the AND gate  14 , an output end of the OR gate  13  is connected to a grid of a first transistor  15  on the topology, and an output end of the AND gate  14  is connected to a grid of a second transistor  16  on the topology. 
     The PWM signal generating circuit  11  is configured to process an output signal of the topology to obtain a PWM signal. The OR gate  13  is configured to perform an OR operation between the PWM signal and a first modulation signal to obtain a first control signal, so as to control a state of the first transistor  15  on the topology. The AND gate  14  is configured to perform an AND operation between the PWM signal and a second modulation signal to obtain a second control signal, so as to control a state of the second transistor  16  on the topology. 
     The PWM signal generating circuit  11  consists of a loop circuit  21  and a comparator  22 . The loop circuit  21  is configured to obtain a loop signal based on the output signal of the topology and a reference signal. The comparator  22  is configured to obtain the PWM signal based on the loop signal and a comparison signal. An input end of the loop circuit  21  is connected to an output end of the topology, an output end of the loop circuit  21  is connected to an input end of the comparator  22 , and an output end of the comparator  22  is connected to the input end of the OR gate  13  and the input end of the AND gate  14 . 
     Further, the apparatus includes a first NOT gate  17  and a second NOT gate  18 . An input end of the first NOT gate  17  is connected to the output end of the OR gate  13 , an output end of the first NOT gate  17  is connected to a grid of a third transistor  19  on the topology, an input end of the second NOT gate  18  is connected to the output end of the AND gate  14 , and an output end of the second NOT gate  18  is connected to a grid of a fourth transistor  20  on the topology. The first NOT gate  17  is configured to perform a NOT operation on the first control signal to control the third transistor on the topology. The second NOT gate  18  is configured to perform a NOT operation on the second control signal to control the fourth transistor on the topology. 
     Specifically, an operational amplifier on the loop circuit  21  performs operational amplification on an input feedback signal of an output signal of the topology and on the reference signal. When a voltage of a feedback signal is higher than a voltage of the reference signal, a voltage of the output signal of the operational amplifier decreases, and when the voltage of the feedback signal is lower than the voltage of the reference signal, the voltage of the output signal of the operational amplifier increases. In this way, the loop signal is obtained. Its used circuit is a typical loop circuit, as illustrated in  FIG. 3 . The loop circuit is a negative feedback circuit, consisting of an operational amplifier X 1 , peripheral capacitors C 1 , C 2 , and C 3 , and resistors R 1 , R 2 , R 3 , and R 4 , where, at the negative input end of the operational amplifier X 1 , the voltage V fb  of the feedback signal of the output signal Vo is input. The relationship between the voltage V fb  of the feedback signal and the voltage V o  of the output signal is shown in Formula (1). At the positive input end of the operational amplifier X 1 , the voltage V ref  of a reference signal is input, where the value range of the voltage V ref  of the reference signal is self-defined, ranging from 0.8V to 3V. Generally, voltage adjustment on a digital switchmode power supply is achieved by adjusting V ref . Finally, after the operational amplifier X 1  performs an operation, the loop circuit outputs the voltage of a loop COMP signal. The relationship between the voltage V o  of the output signal and the voltage of a COMP signal is as follows: when the voltage V o  of the output signal increases, resulting in that the voltage V fb  of the feedback signal of the voltage V o  of the output signal is higher than the voltage V ref  of the reference signal, the operational amplifier X 1  outputs a low level, that is, a COMP level decreases; when the voltage V o  of the output signal decreases, the voltage of the COMP signal increases. Therefore, the function of the loop circuit is, through such a negative feedback function, to enable V fb  to be equal to V ref , and finally ensure that the voltage V o  of the output signal stabilizes at a fixed value. The foregoing loop circuit may be achieved using an analog circuit or a digital circuit. Both analog and digital circuits are relatively mature technologies among existing technologies, so details are not provided herein again. In the embodiments of the present invention, any loop circuit may be used. 
     In the comparator  22 , a voltage of the loop signal and a voltage of a comparison signal are input into the comparator X 2 , as illustrated in  FIG. 3 . After the comparator X 2  performs comparison, a voltage of the PWM modulation signal is obtained. The voltage of the loop signal is input into the positive input end of the comparator X 2 , and the voltage of the comparison signal is input into the negative input end of the comparator X 2 , where the comparison signal is a sawtooth wave. The working principles of the comparator X 2  are as follows: when the voltage of the loop signal is higher than the voltage of the comparison signal, the comparator X 2  outputs a high level, and when the voltage of the loop signal is lower than the voltage of the comparison signal, the comparator X 2  outputs a low level. The comparator may be achieved using an analog circuit or a digital circuit. Both analog and digital circuits are relatively mature technologies among existing technologies, so details are not provided herein again. In the embodiments of the present invention, any comparator may be used. 
     In the OR gate  13 , the PWM modulation signal and the first modulation signal are input into the OR gate  13 , a first control signal is obtained after the OR gate  13  performs an operation on the signals, and the OR gate  13  uses the first control signal to control the first transistor  15  on the single-inductor BUCK-BOOST topology, where, an input end of the OR gate  13  inputs the PWM modulation signal, and another input end inputs the first modulation signal, where the first modulation signal is pre-set based on actual situations. 
     In the AND gate  14 , the PWM modulation signal and the second modulation signal are input into the AND gate  14 , a second control signal is obtained after the AND gate  14  performs an operation on the signals and the AND gate  14  uses the second control signal to control the second transistor  16  on the single-inductor BUCK-BOOST topology, where, at one input end of the AND gate  14 , the PWM modulation signal is input, and at the other input end, the second modulation signal is input, where the second modulation signal is pre-set based on actual situations. 
     Additionally, the third transistor  19  and the fourth transistor  20  may be switch transistors or diodes. When the third transistor  19  and the fourth transistor  20  are switch transistors, a NOT operation needs to be performed on the first control signal by the first NOT gate  17  to control the third transistor  19 , and a NOT operation needs to be performed on the second control signal by the second NOT gate  18  to control the fourth transistor  20 . When the third transistor  19  and the fourth transistor  20  are diodes, the apparatus neither needs the first NOT gate  17  nor the second NOT gate  18 , nor needs the first control signal and the second control signal that are used for controlling diodes, because a diode is capable of automatically performing an on-off action. 
     The following takes the assumption that the third transistor  19  and the fourth transistor  20  are switch transistors as an example to describe how the control method provided in the embodiments of the present invention achieves the three topology states BUCK, PASS, and BOOST in detail. The duty cycle of the first modulation signal D 1  is represented by r 1 , the duty cycle of the second modulation signal D 2  is represented by r 2 , the duty cycle of the PWM signal is represented by r, the duty cycle of the first control signal S 1  is represented by z 1 , and the duty cycle of the second control signal S 2  is represented by z 2 . In addition, 1−r 1 , that is, the difference between 1 and the duty cycle of the first modulation signal D 1 , is a first threshold, and 1−r 2 , that is, the difference between 1 and the duty cycle of the second modulation signal D 2 , is a second threshold. 
     First, the process of how the BUCK state is achieved is described. 
     When the duty cycle r of the PWM modulation signal is less than 1−r 1  and less than or equal to 1−r 2 : the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain the first control signal S 1 , to control the first transistor T 1  on the topology to be in switch mode, where the duty cycle z 1  of the first control signal S 1  is r+r 1 ; the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain the low-level second control signal S 2 , to control the second transistor T 2  on the topology to be in constant off mode, where the duty cycle z 2  of the second control signal S 2  is 0; a NOT operation is performed on the first control signal S 1 , to control the third transistor T 3  on the topology to be in switch mode, and in this case, the BUCK circuit is in the BUCK state; a NOT operation is performed on the second control signal S 2 , to control the fourth transistor T 4  on the topology to be in constant on mode, and in this case, the BOOST circuit is in the PASS state. Therefore, in this case, the topology is in the BUCK state. 
     Second, the process of how the BOOST state is achieved is described. 
     When the duty cycle r of the PWM modulation signal is greater than 1−r 2  and greater than or equal to 1−r 1 : the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain the high-level first control signal S 1 , to control the first transistor T 1  on the topology to be in constant on mode, where the duty cycle z 1  of the first control signal S 1  is 100%; the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain the second control signal S 2 , to control the second transistor T 2  on the topology to be in switch mode, where the duty cycle z 2  of the second control signal S 2  is r-(1−r 2 ); a NOT operation is performed on the first control signal S 1 , to control the third transistor T 3  on the topology to be in constant off mode, and in this case, the BUCK circuit is in the PASS state; a NOT operation is performed on the second control signal S 2 , to control the fourth transistor T 4  on the topology to be in switch mode, and in this case, the BOOST circuit is in the BOOST state. Therefore, in this case, the topology is in the BOOST state. 
     Third, the process of how the PASS state is achieved is described. 
     Assuming that the duty cycle r 1  of the first modulation signal D 1  is greater than the duty cycle r 2  of the second modulation signal D 2 , when the duty cycle r of the PWM modulation signal is greater than or equal to 141 and less than or equal to 1−r 2 : the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain the high-level first control signal S 1 , to control the first transistor T 1  on the topology to be in constant on mode, where the duty cycle z 1  of the first control signal S 1  is 100%; the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain the low-level second control signal S 2 , to control the second transistor T 2  on the topology to be in constant off mode, where the duty cycle z 2  of the second control signal S 2  is 0; a NOT operation is performed on the first control signal S 1 , to control the third transistor T 3  on the topology to be in constant off mode, and in this case, the BUCK circuit is in the PASS state; a NOT operation is performed on the second control signal S 2 , to control the fourth transistor T 4  on the topology to be in constant on mode, and in this case, the BOOST circuit is in the PASS state. Therefore, in this case, the topology is in the PASS state. 
     In addition, the entering to the PASS state may be achieved by checking the level of a loop COMP signal. Specifically, directly enabling, after determining that the level of a loop COMP signal is in the range from a high level to a low level, both the high-side transistor of a BUCK circuit and the high-side transistor of a BOOST circuit to be in constant on mode, may also enable a single-inductor BUCK-BOOST topology to enter the PASS state. Or, the method of detecting an input signal V i  an output signal V o , and output currents is used, and when the input signal V i  and the output signal V o  are approximately equal to each other and when the output current of each module is relatively balanced, the level of the loop signal is forcibly maintained in the signal range within which the BUCK-BOOST topology is in the PASS state. 
     Further, when it is assumed that the duty cycle r 1  of the first modulation signal D 1  is less than the duty cycle r 2  of the second modulation signal D 2 , and when the duty cycle r of the PWM modulation signal is greater than 1−r 2  and less than 1−r 1 : the OR gate performs an OR operation between the PWM modulation signal and the first modulation signal D 1  to obtain the first control signal S 1 , to control the first transistor T 1  on the topology to be in switch mode, where the duty cycle z 1  of the first control signal S 1  is equal to r+r 1 ; the AND gate performs an AND operation between the PWM modulation signal and the second modulation signal D 2  to obtain the second control signal S 2 , to control the second transistor T 2  on the topology to be in switch mode, where the duty cycle z 2  of the second control signal S 2  is r−(1−r 2 ); a NOT operation is performed on the first control signal S 1 , to control the third transistor T 3  on the topology to be in switch mode, and in this case, the BUCK circuit is in the BUCK state; a NOT operation is performed on the second control signal S 2 , to control the fourth transistor T 4  on the topology to be in switch mode, and in this case, the BOOST circuit is in the BOOST state. Therefore, in this case, the topology is in the BUCK-BOOST state. 
     In addition, the control apparatus provided in the embodiment of the present invention also ensures a smooth switchover between the BUCK state and the BOOST state. For example, when the duty cycle of the first modulation signal is 55%, the duty cycle of the second modulation signal is 45%, the voltage V i  of the input signal is a high voltage, for example, 75V, and the voltage V o  of the output signal is 50V, the BUCK-BOOST topology works in the BUCK state. When the input signal jumps, that is, the voltage of the input signal falls from a high voltage to a relatively low voltage, for example, jumping from 75V to 36V, the duty cycle of the PWM signal output by the loop circuit and the comparator changes from a small value to a large value. After the AND gate and the NOT gate perform operations for the PWM signal, the duty cycle of the first control signal gradually becomes larger and larger until the first transistor T 1 , that is, the high-side transistor of the BUCK circuit, is completely in constant on mode and the BUCK-BOOST topology enters the PASS state. When the duty cycle of the PWM modulation signal further increases, the duty cycle of the low-side transistor of the BOOST circuit starts to increase slowly from 0, until the BUCK-BOOST topology enters the BOOST state. During the entire switchover from the BUCK state to the BOOST state, the duty cycle of the high-side transistor of the BUCK circuit gradually increases until it enters the constant on mode, and the duty cycle of the low-side transistor of the BOOST circuit gradually increases from 0. The switchover process is very smooth and does not require an extra soft start operation. 
     Therefore, the control apparatus provided in the embodiment of the present invention, by using a PWM signal generating circuit to process an output signal of a single-inductor BUCK-BOOST topology to obtain a PWM signal, using an OR gate to perform an OR operation between the PWM signal and a first modulation signal to obtain a first control signal so as to control a state of a first transistor on the topology, and simultaneously using an AND gate to perform an AND operation between the PWM signal and a second modulation signal to obtain a second control signal so as to control a state of a second transistor, three topology states BUCK, PASS, and BOOST are achieved, and a smooth switchover among the three topology states is achieved, and a special soft start operation is not required. The apparatus, with simple implementation, can be applied in different input signal scenarios. 
     A person of ordinary skill in the art should also be further aware that, in combination with the examples described in the embodiments disclosed in this specification, units and algorithm steps may be implemented by electronic hardware, computer software, or a combination thereof. In order to clearly describe the interchangeability between the hardware and the software, the foregoing has generally described compositions and steps of each embodiment according to functions. Whether the functions are performed by hardware or software depends on particular applications and design constraint conditions of the technical solutions. A person skilled in the art may use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of the present invention. 
     In combination with the embodiments disclosed in this specification, the described method or algorithm steps may be implemented by hardware, a software module executed by a processor, or a combination thereof. The software module may be located in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other storage media well-known in the art. 
     The objectives, technical solutions, and beneficial effects of the present invention are further described in detail in the foregoing specific embodiments. It should be understood that the foregoing descriptions are merely specific embodiments of the present invention, but are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, and so on made within the idea and principle of the present invention shall fall within the protection scope of the present invention.