Patent Publication Number: US-2023143396-A1

Title: Bipolar transistor with collector contact

Description:
BACKGROUND 
     The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a collector contact and methods of manufacture. 
     Bipolar transistors can be vertical transistors or lateral transistors. Lateral bipolar junction transistors may be used in many different applications such as automotive applications. These devices can attain very high Ft (current gain cut-off frequency) and high Fmax (power gain cut off frequency) values compared to CMOS. In advanced nodes, though, as contact size shrinks, emitter resistance (Re) and collector resistance (Rc) increase as does the collector capacitance (Cbc). This negatively impacts Ft/Fmax. 
     SUMMARY 
     In an aspect of the disclosure, a structure comprises: a lateral bipolar transistor comprising an emitter, a base and a collector; an emitter contact to the emitter; a base contact to the base; and a collector contact to the collector and extending to an underlying substrate underneath the collector. 
     In an aspect of the disclosure, a structure comprises: a substrate comprising a handle substrate, an insulator material on the handle substrate and a semiconductor material on the insulator material; a lateral bipolar transistor comprising a collector, an emitter and a base; an emitter contact to the emitter; a base contact to the base; and a collector contact to the collector and extending to the handle substrate, through the insulator material and the semiconductor material. 
     In an aspect of the disclosure, a method comprises: forming a lateral bipolar transistor comprising an emitter, a base and a collector; an emitter contact to the emitter; a base contact to the base; and forming a collector contact to the collector and extending to an underlying substrate underneath the collector. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. 
         FIG.  1    shows a lateral heterojunction bipolar transistor and respective fabrication processes in accordance with aspects of the present disclosure. 
         FIG.  2    shows a top cross-sectional view of the lateral heterojunction bipolar transistor of  FIG.  1   . 
         FIGS.  3 A- 3 F  show fabrication processes for manufacturing a collector contact for a lateral heterojunction bipolar, amongst other features, in accordance with aspects of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a collector contact and methods of manufacture. More specifically, the present disclosure relates to a collector contact for a heterojunction bipolar transistor within a single diffusion break and that contacts to the underlying substrate. Advantageously, the collector contact provides improved thermal conduction, e.g., provides an improved thermal dissipation pathway for the heterojunction bipolar transistor (i.e., improved bipolar thermal resistance (Rth)). In addition, by implementing the different aspects of the present disclosure, e.g., collector contact, it is possible to provide a reduction in contact resistance (Rc) of more than 50% and, hence improved Ft, compared to conventional structures. 
     In more specific embodiments, the heterojunction bipolar transistor may be a lateral heterojunction bipolar transistor. The lateral heterojunction bipolar transistor may include a collector contact landing on both a collector silicide and a substrate (e.g., handle wafer or substrate). The collector contact may be isolated by spacers which surround the collector contact and extend within the substrate. In embodiments, the spacers may extend through a buried insulator layer. In further embodiments, the collector contact wraps around with a raised collector region, e.g., epitaxial semiconductor material and silicide. The collector contact may extend through a portion of a dummy gate structure which includes a second spacer formed around the spacers. 
     The lateral heterojunction bipolar transistor of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the lateral heterojunction bipolar transistor of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the lateral heterojunction bipolar transistor uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, precleaning processes may be used to clean etched surfaces of any contaminants, as is known in the art. Moreover, when necessary, rapid thermal anneal processes may be used to drive-in dopants or material layers as is known in the art. 
       FIG.  1    shows a lateral heterojunction bipolar transistor in accordance with aspects of the present disclosure. In particular, the lateral heterojunction bipolar transistor  10  includes a substrate  12 . In embodiments, the substrate  12  may include a handle wafer (substrate)  12   a , a buried insulator material  12   b  over the handle wafer  12   a , and a semiconductor substrate  12   c  over the buried insulator material  12   b . The handle wafer  12   a  provides mechanical support to the buried insulator layer  12   b  and the semiconductor substrate  12   c.    
     In embodiments, the handle wafer (substrate)  12   a  and the semiconductor substrate  12   c  may include any appropriate semiconductor material such as, for example, Si, SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors or any combinations thereof. The semiconductor substrate  12   c  may also comprise any suitable crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). The buried insulator layer  12   b  may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride or a combination thereof. An exemplary insulator layer may be a buried oxide layer (BOX). 
     Still referring to  FIG.  1   , the handle wafer  12   a  may be a P-substrate with an N-well  14 . The semiconductor substrate  12   c  may also comprise an n-type substrate. The N-well  14  may act as a contact (e.g., subcollector) for a collector and may be provided by a deep ion implantation process; whereas n-type dopants in the semiconductor substrate  12   c  may be provided by a shallow ion implantation process. 
     As should be known to those of skill in the art, the ion implantation process includes introducing a certain concentration of dopant by, for example, ion implantation. In embodiments, a patterned implantation mask may be used to define selected areas exposed for the implantation. The implantation mask may include a layer of a light-sensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The N-well  14  and semiconductor substrate  12   c  may be doped with n-type dopants, e.g., Arsenic (As), Phosphorus (P) and Sb, among other suitable examples. 
     A deep trench isolation structure  16  may be provided in the substrate  12 . In embodiments, the deep trench isolation structure  16  extends into the handle wafer  12   a , e.g., contacts the subcollector region in the handle wafer  12   a . The deep trench isolation structure  16  may be formed by conventional lithography, etching and deposition methods known to those of skill in the art. For example, a resist formed over the semiconductor substrate  12   c  is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to transfer the pattern from the resist layer to the semiconductor substrate  12   c  to form one or more trenches in the semiconductor substrate  12   c . Following the resist removal by a conventional oxygen ashing process or other known stripants, insulator material (e.g., oxide) can be deposited by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. Any residual material on the surface of the semiconductor substrate  12   c  can be removed by conventional chemical mechanical polishing (CMP) processes. 
     A collector  18 , an emitter  20  and a base  22  may be formed over the semiconductor substrate  12   c . In embodiments, the collector  18  and the emitter  20  may be a raised collector  18  and a raised emitter  20  formed by epitaxial growth processes starting on the semiconductor substrate  12   c . For example, the raised collector  18  and the raised emitter  20  may be formed by growing semiconductor material, e.g., Si material, directly on the semiconductor substrate  12   c . The base  22  may be formed in contact with the underlying semiconductor substrate  12   c , optionally extending to the buried insulator layer  12   b . In embodiments, the base  22  may be fabricated by forming a trench into the semiconductor substrate  12   c  using conventional lithography and etching processes as described herein. The trench may optionally extend to the buried insulator layer  12   b . Following the trench formation, an epitaxial growth process using, e.g., SiGe material, may be used to form the base  22 . In this way, the base  22  may be a raised base. In embodiments, the raised collector  18 , the raised emitter  20  and the raised base  22  may comprise Si/SiGe/Si, all SiGe or all Si, as further examples. 
     The structure  10  may also include dummy gate structures  24 , one of which may be removed to form a collector contact  25  extending to and contacting the handle wafer  12   a . The collector contact  25  may have a greater width dimension than the emitter contact  30  and the base contact  32 , and may increase the contact surface area to the handle wafer  12   a  to provide an improved heat conduction or passageway for heat transfer away from the bipolar heterojunction bipolar transistor. The formation of the collector contact  25  is described in more detail with respect to  FIGS.  3 A- 3 F . 
     In embodiments, the dummy gate structures  24  may be polysilicon material formed by conventional deposition processes, e.g., CVD, followed by a patterning process as is known in the art. In embodiments, a sidewall spacer  24   a  may be formed on sidewalls of the dummy gate structures  24 , in addition to the base  22 . The sidewall spacers  24   a  may be oxide and/or nitride material deposited by a conventional deposition method, e.g., CVD, followed by an etching process known to those of skill in the art such that no further explanation is required for a complete understanding of the present disclosure. In embodiments, the material of the sidewall spacers on top of the dummy gate structures  24  may be removed during a single diffusion break cut process as described below. The sidewall spacer  24   a  that surrounds the base  22  will isolate the base  22  from the collector  18  and the emitter  20 . 
     The collector contact  25  may be formed between the sidewall spacers  24   a  of the removed dummy gate structure as described with respect to  FIGS.  3 A- 3 F . In embodiments, the collector contact  25  may also include sidewall spacers  27 , between the sidewall spacers  24   a  of the removed dummy gate structure. At least one dummy gate structure  24  may be formed partially over the deep trench isolation structure  16  and the semiconductor substrate  12   c . The sidewall spacers  27  may extend to the handle wafer  12   a , underneath the bipolar transistor, e.g., collector  18 , the emitter  20  and the base  22 . 
     The collector  18 , the emitter  20  and the base  22  may be subjected to a silicide process to form silicide contacts  26 , prior to the formation of the respective contacts  30 ,  32 ,  26  in dielectric material  28 . The silicide process will form the silicide contacts  26  on each of the collector  18 , emitter  20  and base  22 , in addition to the dummy gate structures  24 . As should be understood by those of skill in the art, the silicide process begins with deposition of a thin transition metal layer, e.g., nickel, cobalt or titanium, over fully formed and patterned semiconductor material (e.g., collector  18 , emitter  20  and base  22  and dummy gate structures  24 ). After deposition of the material, the structure is heated allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) forming a low-resistance transition metal silicide, e.g., NiSi. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts  26 . 
     The contacts  30 ,  32  may be formed by conventional lithography, etching and deposition processes, where the formation of the contact  25  is described in more detail below. It should be understood the contacts  30 ,  32  may be offset from one another, e.g., provided in a different cross-sectional plane, as shown in a top view of  FIG.  2   , with both the contacts  30 ,  32  shown in  FIG.  1    being provided for convenience of this description. The contacts  30 ,  32  may be formed, for example, by first depositing interlevel dielectric material  28  over the structure, followed by a lithography and etching process to form trenches to the silicide  26  of the emitter  20  and the base  22 . A conductive material, e.g., tungsten, aluminum or copper, with a liner (e.g., TiN), may be deposited within the trenches in contact with the silicide contacts  26 . Any residual material may be removed from the interlevel dielectric material  28  by a conventional CMP process. 
       FIG.  2    shows a top cross-sectional view of the structure  10  of  FIG.  1   . As shown in this representation, the collector contact  25  extends over and contacts (directly) the silicide contact  26  of the collector  18 . In addition, the collector contact  25  extends over both sidewall spacers  24   a ,  27 , with part of the collector contact  25  being surrounded by the spacers  24   a ,  27 . The collector contact  25  also extends a length of the dummy gate structure (i.e., the removed dummy gate structure structure). In this way, the collector contact  25  has an increased surface area contacting the underlying handle wafer which, in turn, provides for an increased thermal pathway for heat to be removed from the structure. That is, the increased surface area of the collector contact  25  will improve self-heating and heat dissipation, in addition to providing improved thermal conductivity. 
     Moreover, the collector  18 , emitter  20  and base  22  are separated and isolated from one another by the sidewall spacers  24   a . Further, the contacts  32  for the base  22  are not in the same plane as the contacts  20 ,  25  for the collector  18  and the emitter  20 . This arrangement provides improved capacitance. In addition, the contact  30  only contacts the emitter  20  (e.g., silicide contact  26  of emitter  20 ). Similarly, the contact  32  only contacts the base  22  (e.g., silicide contact  26  of base  22 ). The contacts  30 ,  32 ,  25  may be tungsten, aluminum or copper, which further contributes to a thermal conduction pathway attributed to the collector contact  25 . 
       FIGS.  3 A- 3 F  show fabrication processes for manufacturing a collector contact, amongst other features, in accordance with aspects of the present disclosure. In embodiments,  FIG.  3 A  shows a middle of the line module  10   a . The middle of the line module  10   a  includes, for example, at least one dummy gate structure  24  with sidewall spacers  24   a . In this representation, the sidewalls spacers  24   a  may include nitride and/or oxide material that completely lines the dummy gate structure  24 , in addition to any exposed surfaces. The dummy gate structures  24  may comprise polysilicon material deposited by CVD processes and patterned by lithography and etching processes as already described herein. The dummy gate structures  24  may be formed on the semiconductor substrate  12   c . A dielectric material  28  may be deposited on the dummy gate structures  24  using conventional deposition processes, e.g., CVD. The dielectric material  28  may include alternating layers of oxide and nitride, as an example. 
     In  FIG.  3 B , a single diffusion break (e.g., trench)  36  may be formed in the dielectric material  28 , extending through the material of the sidewall spacer  24   a  and exposing the underlying dummy gate structure  24 . In embodiments, the single diffusion break  36  may be formed by conventional lithography and etching methods known to those of skill in the art. For example, a resist formed over the dielectric material  28  is exposed to energy (light) and developed utilizing a conventional resist developer to form a pattern (opening). An etching process with a selective chemistry, e.g., RIE, will be used to transfer the pattern from the resist layer to the dielectric material  28  and through the material of the sidewall spacers  24   a . The resist may be removed by a conventional oxygen ashing process or other known stripants. 
     In  FIG.  3 C , the single diffusion break (e.g., trench)  36  is extended through the dummy gate structure  24 , the semiconductor substrate  12   c  and the insulator layer  12   b , extending within the handle wafer  12   a . In embodiments, the extension of the single diffusion break (e.g., trench)  36  requires a dummy polysilicon etching process, in addition to etch chemistries that etch through the semiconductor substrate  12   c , the insulator layer  12   b , and partly within the handle wafer  12   a . In embodiments, this etching process can be a timed etch to ensure that the single diffusion break (e.g., trench)  36  extends to within the handle wafer  12   a . Also, as shown, the single diffusion break (e.g., trench)  36  will be provided between the sidewall spacers  24   a , e.g., leaving the sidewalls spacers  24   a  intact, while removing the material of the sidewall spacers  24   a  on top of the dummy gate structure  24  and the dummy gate structure  24 , itself. 
     In  FIG.  3 D , a liner  38  may be deposited on sidewalls of the single diffusion break (e.g., trench)  36 . In embodiments, the liner  38  may be provided on the sidewall spacers  24   a , the semiconductor substrate  12   c , the insulator layer  12   b  and the handle wafer  12   a . The liner  38  may be an insulator material, e.g., a nitride material or other low-k dielectric material, deposited by a conventional deposition method. The liner  38  may be removed from the bottom surface of the trench  36  and top surface of the dielectric material  28  by a known anisotropic etching process. In embodiments, the liner  38  or any residual portions of the liner  38  on the top surface of the dielectric material  28  may be removed by a CMP process. 
     In  FIG.  3 E , an additional trench  40  may be formed over the collector  18 . In embodiments, the trench  40  may merge with the single diffusion break (e.g., trench)  36  to form a single trench structure, e.g., single diffusion break. The additional trench  40  may be formed by conventional etching processes, which will remove portions of the liner  38  and the dielectric material  28 . In embodiments, the additional trench  40  will expose the silicide  26  of the collector  18 . Moreover, a trench  42  may be formed in the dielectric material  26 , which exposes the silicide  26  of the emitter  20 . The trench  42  may also be formed by a conventional etching process. Although not shown a trench may be formed to the base in a similar manner. 
     In  FIG.  3 F , the collector contact  25  may be formed within the trenches  36 ,  42  and the contact  30  may be formed in the trench  42 . The collector contact  25  lands on both the silicide  26  of the collector  18  and on the handle wafer  12   a  through the trenches  36 ,  40  (e.g., single diffusion break). The contact  30  may be the emitter contact which lands on the silicide  26  of the emitter  20 . The contacts  25 ,  30  may include a liner material, e.g., TiN or TaN, in addition to a metal material, e.g., tungsten, aluminum or copper. The material of the contacts  25 ,  30  may be deposited by a CVD process, followed by a planarization process (e.g., CMP) to remove any residual or excess material from a top surface of the dielectric material  28 . 
     The lateral heterojunction bipolar transistor can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things. 
     The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.