Patent Publication Number: US-7904048-B2

Title: Multi-tap direct sub-sampling mixing system for wireless receivers

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to and incorporates by reference provisional application U.S. 60/947192 “A Configurable Low-Noise High Linearity Multi-Tap Direct Sub-Sampling Mixing (MTDSM) System For Wireless Receiver” filed on 29 Jun. 2007. 
    
    
     FIELD OF THE INVENTION 
     This invention generally relates to filters and more specifically to a switched capacitor filter. 
     BACKGROUND OF THE INVENTION 
     As signal processing systems move to higher levels of integration, it becomes necessary to integrate analog functions on chips in which most of the area is consumed by digital circuitry. When the analog circuitry occupies only a small percentage of the total chip area, economic considerations limit the addition of any process steps, such as fabrication of high-value capacitors, which are not required by the digital circuits. 
     The switched capacitor (“SC”) filter provided a practical alternative. The original idea was to replace a resistor by a switched capacitor simulating the resistor. Thus the equivalent resistor could be implemented with a capacitor, and two switches operating with two clock phases. The basic building blocks involved in SC circuits are capacitors, MOSFET switches, and op-amps, which can be used to make higher-order blocks such as voltage gain amplifiers, integrators, and second-order filters. These are discrete-time filters that operate like continuous-time filters, but through the use of switches, the capacitance values can be kept very small. As a result, SC filters are amenable to VLSI implementations. 
     Infinite impulse response (IIR) is a property of signal processing systems. Systems with that property are known as IIR systems or when dealing with electronic filter systems as IIR filters. They have an impulse response function which is non-zero over an infinite length of time. This is in contrast to finite impulse response filters (FIR) which have fixed-duration impulse responses. The simplest analog IIR filter is an RC filter made up of a single resistor (R) feeding into a node shared with a single capacitor (C). This filter has an exponential impulse response characterized by an RC time constant. 
     The switching functions of the MOSFETs produces a discrete response rather than a continuous response from the filter. Therefore, Z Transforms are employed rather than S Transforms, and, just as in digital filters, aliasing effects occur. Any Z Transform approximation to a continuous function may be used to design a switched capacitor filter. 
     U.S. Pat. No. 7,079,826, “Digitally controlled analog RF filtering in subsampling communication receiver architecture” describes a method of down-converting a first periodic voltage waveform into a second periodic voltage waveform by sampling the first periodic waveform and transforming the first voltage waveform into a corresponding current waveform, integrating each half-cycle of the current waveform by charging a corresponding capacitor; and combining the samples to produce the second voltage waveform, and is incorporated herein by reference in its entirety. 
     U.S. Pat. No. 7,006,813, “Efficient charge transfer using a switched capacitor resistor” describes a method for setting a voltage on a sampling capacitor by applying a first substantially constant charging current to a charging capacitor for a first period of time to store a first charge on the charging capacitor, using the charging capacitor to share the first charge with the sampling capacitor, and leaving a residual charge on the charging capacitor; maintaining the residual charge on the charging capacitor after sharing with the sampling capacitor, and applying a second charging current to the charging capacitor for a second period of time to bring the charge on the charging capacitor from the residual charge to a second charge, and is incorporated herein by reference in its entirety. 
     U.S. Pat. No. 7,057,540, “Sigma-delta (.SIGMA..DELTA.) analog-to-digital converter (ADC) structure incorporating a direct sampling mixer” describes a sampling circuit using switched capacitors with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream, and is incorporated herein by reference in its entirety. 
     US Publication 20070105522, “Offset balancer, method of balancing an offset and a wireless receiver employing the balancer and the method” describes an offset balancer for use with a differential mixer employing wireless reception and an offset quantifier configured to indicate an existing DC offset of the mixer corresponding to an existing second-order intercept point applicable to the wireless reception, and is incorporated herein by reference in its entirety. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides a multi-tap direct sub-sampling mixing system for wireless receivers with a dynamically configurable passive switched capacitor filter. A front end amplifier is connected to receive a signal. The passive switched capacitor filter is connected to receive the amplified signal and has an output for providing a filtered signal. The switched capacitor filter has at least two sections that are each operable as a pole, wherein a first section of the at least two sections has sets of at least two stacked capacitors interconnected with a set of switches operable to amplify in input voltage provided to an input of the first section in response to operation of the set of switches; and a back end section connected to the output of the switched capacitor filter to receive the filtered signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Particular embodiments in accordance with the invention will now be described, by way of example only, and with reference to the accompanying drawings: 
         FIG. 1  is a block diagram of a digital system with a passive switched capacitor filter; 
         FIG. 2  is a schematic of one embodiment of a passive switched capacitor filter for use in the digital system of  FIG. 1 ; 
         FIG. 3  is a timing diagram illustrating operation of control signals provided to the switched capacitor filter of  FIG. 2 ; 
         FIG. 4  is a schematic of another embodiment of a passive switched capacitor filter for use in the digital system of  FIG. 1 ; 
         FIG. 5  is a timing diagram illustrating operation of control signals provided to the switched capacitor filter of  FIG. 4 ; 
         FIG. 6  is a frequency response plot for a particular configuration of the filter of  FIG. 4 ; 
         FIG. 7  is a schematic of another embodiment of a passive switched capacitor filter for use in the digital system of  FIG. 1 ; 
         FIG. 8  is a timing diagram illustrating operation of control signals provided to the switched capacitor filter of  FIG. 7 ; and 
         FIG. 9  is a block diagram of another digital system with an embodiment of a passive switched capacitor filter. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION 
       FIG. 1  is a block diagram of a digital system  100  with a passive switched capacitor filter  120 . Digital system  100  is representative of a variety of different systems that are designed for receiving an analog signal, filtering the signal to select a particular frequency band, and then converting the filtered signal to the digital domain for further processing by a digital signal processor. One example of such a system is a radio receiver. Various types of radio receivers have need for selecting a particular frequency and processing a data or audio signal being transmitted on that frequency. A particular embodiment of digital system  100  is in a cellular telephone handset. 
     The Global System for Mobile Communications (GSM: originally from Groupe Special Mobile) is currently the most popular standard for mobile phones in the world and is referred to as a 2G (second generation) system. W-CDMA (Wideband Code Division Multiple Access) is a type of 3G (third generation) cellular network. W-CDMA is the higher speed transmission protocol designed as a replacement for the aging 2G GSM networks deployed worldwide. More technically, W-CDMA is a wideband spread-spectrum mobile air interface that utilizes the direct sequence Code Division Multiple Access signaling method (or CDMA) to achieve higher speeds and support more users compared to the older TDMA (Time Division Multiple Access) signaling method of GSM networks. 
     Digital system  100  includes an analog front end portion and analog backend portion (ABE)  130 . The analog front end includes low noise amplifier  106  that receives a radio frequency (RF) signal from an antenna, not shown, and amplifies the low level signal using low noise amplification techniques. The total gain is limited in order to minimize compression of the later stages which results in degradation to signal to noise ratio (SNR) of the signal under blocking condition due to strong interferers. The amplified RF signal is then connected to multi-tap direct sub-sampling mixing (MTDSM) system  102  for further amplification and filtering. 
     Transconductance amplifier (TA)  110  produces an analog output signal in which the current is proportional to the input voltage signal. The output of TA  110  is provided to mixer  112  that down mixes the RF signal to a lower intermediate frequency. The output of mixer  112  is developed across holding capacitor CH and provided to passive switched capacitor filter (SCF)  120 . SCF  120  includes two infinite impulse response (IIR) stages IIR 1   121  and IIR 2   122 . 
     FeedBack REFerence (FBREF) circuit  114  provides a reference voltage signal to digital to analog converter (DAC)  123  that produces an analog common mode voltage used by IIR 2 . FBREF  114  is basically a voltage buffer for VREF. VREF is provided from a bandgap reference device which is a reference voltage for the whole analog portion  102 . In this embodiment, VREF is approximately 0.9 v. Feedback control unit (FCU)  116  is a sigma-delta modulator that controls DAC  123 . Digital control unit (DCU)  118  generates the timing signals used to control the various MOSFET switches within SCF  120 . DCU  118  generates a series of non-overlapping timing signals using a shift register circuit. 
     An output of SCF  120  is provided to ABE  130 . ABE  130  includes intermediate frequency amplifier (IFA)  132  that further amplifies the signal produced by SCF  120  that is then connected to analog to digital converter (ADC)  134 . ADC  134  samples and converts the continuous time signal to a digital signal that is then provided to a digital signal processing (DSP) unit, not shown, for further processing. 
     Due to noise generated by the conversion processes in ABE  130 , a sufficient input signal to ABE  130  is needed to maintain certain SNR required by DBB. The analog front end (AFE) circuits must provide sufficient gain while maintaining a good front-end linearity. Passive SCF  120  helps in providing the needed front end gain by producing gain in addition to filtering. This approach is superior to doing the same thing in an active filter since a passive SCF has lower noise and better linearity. This allows the gain level of the LNA and TA to be set at a lower value in order to improve linearity. SCF is also used to cancel the DC offset at the output of ADC  130  which degrades the SNR performance of a receiver. Furthermore, SCF  130  is dynamically configurable in order to better support different wireless standards. This enables support of different standards such as GSM and W-CDMA. 
       FIG. 2  is a schematic of one embodiment of a passive switched capacitor filter  200  for use in digital system  100 . SCF  200  is a passive 2-pole switch capacitor filter implementation that provides an on-chip filter that has lower power and low noise requirement as compared to prior passive or active SCF filters. SCF  200  is a two pole filter, the first pole being implemented in IIR 1   210  and the second pole in IIR 2   220 . IIR 1  incorporates stacked capacitors  212   a  and  212   b  in a first bank A and  214   a  and  214   b  in a second bank B. In operation, these capacitors and switches perform as a virtual resistor, while capacitor  216  performs as the capacitor of a classic RC filter. 
       FIG. 3  is a timing diagram illustrating operation of control signals provided to switched capacitor filter  200  from DCU  118 . All of the control signals are non-overlapping so that one group of switches is turned off before the next group is turned on. The various arrows indicate signals that are critical for non-overlapped operation. Control signal S A  controls MOSFET switches S A , control signal S B  controls MOSFET switches S B , etc. MOSFET switches  216 S A  are closed on the first half of a cycle while MOSFET switches  217 S B - 218 S B  are open. During the first half of the cycle voltage V output from mixer  112  ( FIG. 1 ) is applied to both capacitor  212   a  and capacitor  212   b  in parallel. During the second half of the cycle, switches  216  S A  are opened and switches  216 S B - 218 S B  are closed. Switch  218 S B  connects capacitor  212   a  and capacitor  212   b  in series so that the voltage applied to filter capacitor  216  is doubled, thereby producing a gain within filter stage  210 . Bank B operates in a similar manner on the opposite half cycles. 
     Filter stage  220  has two banks of switched capacitors, bank A and bank B, that each has two mirror image portions, a positive side and a negative side referenced to ground. Filter stage  220  samples the voltage across capacitor  216 . The positive portion of bank A includes capacitor  222  that is connected to one output of filter stage  210  by switch  226  S A  that is closed during the first half of the cycle. Simultaneously, precharge capacitor  224  is connected to reference voltage 2V CM  by switch  227 S A . During the second half of the cycle, switches  226 S A  and  227 S A  are opened and charge on capacitor  222  is transferred to filter capacitor  228  via switch S DA . After a period of time, switch S DA  is opened and capacitor  222  is discharged to ground by reset switch S RA  for a period of time. Then switch S RA  is opened and capacitor  222  is connected to precharge capacitor  224  for a period of time via switch S PA . The negative portion of bank A operates in a similar manner, while the positive and negative portions of Bank B operate in a similar manner on the opposite half cycles to produce a filtered output across filter capacitor  228 . However, due to the reset of sampling capacitors of IIR 2 , gain is degraded and finite input impedance exists. 
       FIG. 4  is a schematic of another embodiment of a passive switched capacitor filter  400  for use in the digital system of  FIG. 1 . A different topology is utilized in  FIG. 4  to improve the gain and the input impedance. This is mainly accomplished by implementing a different way of common mode generation. Compared to SCF  200  in  FIG. 2 , the sampling capacitor&#39;s reset signals S RA  and S RB  are gone, and the gain is improved since less charge is dumped to ground. 
       FIG. 5  is a timing diagram illustrating operation of control signals provided to switched capacitor filter  400  from DCU  118  ( FIG. 1 ). All of the control signals are non-overlapping so that one group of switches is turned off before the next group is turned on. The various arrows indicate signals that are critical for non-overlapped operation. Control signal S A  controls MOSFET switches S A , control signal S B  controls MOSFET switches S B , etc. 
     Let the discrete-time period be 0.5 TS. The z-domain equations for V 1 ( z ) and V 2 ( z ) are 
     
       
         
           
             
               
                 
                   
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     Solving (1) and (2), the z-domain transfer from V(z) to V 1 ( z ), V 1 ( z ) to V 2 ( z ), and V(z) to V 2 ( z ) could be derived. 
     
       
         
           
             
               
                 
                   
                     
                       
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                 TABLE 1 
               
             
            
               
                   
               
               
                 Summary of characteristics for SCF 200 and SCF 400 
               
            
           
           
               
               
               
            
               
                 Charac- 
                   
                   
               
               
                 teristic 
                 SCF 200 
                 SCF 400 
               
               
                   
               
               
                 Gain SCF   
                 
                   
                     
                       
                         
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     Table 1 summarizes the characteristics of SCF  200  and SCF  400 . It could be easily shown that SCF  400  has higher gain and input impedance than SCF  200 . This is because 
     
       
         
           
             
               
                 
                   
                     
                       
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     For example, in SCF  400 , assume the following values: C 1 =0.54 pF, C 2 =136.192 pF, C 3 =0.157 pF, C 4 =29.824 pF, CCM=0.15 pF, and fS=225 MHz. Using the equations from Table 1, DC gain=4.8669 dB, Input impedance R in =8.271 KΩ, f 3 dB, IIR2 =375.047 KHz. 
       FIG. 6  shows the results calculated using Matlab, a known circuit simulation tool. The −3 dB pole frequency of the SCF f 3 dB, SCF =205.3 KHz, and the −3 dB pole frequency of IIR 1  f 3 dB, IIR1 =286 KHz. The single pole response of each of IIR 1  and IIR 2  is illustrated and the combined two pole response of SCF  400  is also illustrated. 
       FIG. 7  is a schematic of another embodiment of a passive switched capacitor filter  700  for use in digital system  100 . SCF  700  is a two pole filter, the first pole being implemented in IIR 1   710  and the second pole in IIR 2   720 . IIR 1   710  incorporates three stacked capacitors C R1  in a first bank A and three capacitors C R1  in a second bank B. In operation, these capacitors and related switches SA, SAX, S B  and SBX perform as a virtual resistor, while capacitor C B1  performs as the capacitor of a classic RC filter, similar to the operation of SCF  200  and SCF  400 . In this embodiment, configuration switches SX allow one capacitor C R1  to be bypassed in each of bank A and bank B so that either a two capacitor stack or a three capacitor stack can be dynamically selected during operation to thereby change the gain of SCF  700 . When switches SX are closed to bypass the one capacitor C R1  switches SAX and SAB are disabled so that the corresponding capacitor C R1  is not charged. 
     When IIR 1   710  is operated with two stacked capacitors in each bank, the gain of SCF  700  is similar to that of SCF  400  at around 4 dB. When IIR 1  is operated with three stacked capacitors, the gain of SCF  700  is approximately 7 dB. 
     SCF  700  also includes two bypass switches SY that allow the output of IIR 1  to be either connected to the input of IIR 2  for further filter processing or to be connected directly to outputs  730 - 731  and thereby bypass filter section IIR 2   720 . In this manner, the bandwidth response can be dynamically selected during operation of digital system. For example, this dynamic bandwidth selection allows good operation for both GGE and WCDMA cellular phone applications. 
     Multi-tap operation is provided by allowing control circuitry, not shown, to change the configuration of the capacitor stack and filter coefficients dynamically under program control of a system that is using SCF  700 . 
     SCF  700  also includes a reset switches DAC 0  and DAC 1  that cause sampling capacitors C R2  to be reset at the end of each sample period. Switches DAC 0 Z and DAC 1 Z are controlled in such a way that they operate in an inverted manner from DAC 0  and DAC 1 , respectively. By changing the duty cycle of DAC 0  and DAC 1 , the SCF output common mode can be set to desired values. This set of switches has multiple purposes. It is basically a 1-bit DAC, indicated as DAC  123  in  FIG. 1 , where the digital signals (DAC 1 , DAC 1 Z, DAC 0 , DAC 0 Z) are converted into an analog signal that takes a value in the range between the Vref signal and ground. This analog signal is coupled to the common mode capacitors C CM  via switches SA and SB. These digital signals are generated from a sigma-delta modulator in FCU  116  (referring to  FIG. 1 ) which provides very high resolution even though DAC  123  is just a single-bit DAC. The functions provided by DAC  123  are as follows: 1) control common mode to SCF output  730 - 731 ; and 2) Cancel out any DC offset at SCF output  730 - 731  and at the output of ABE  130 . 
     FCU  116  monitors the DC offset at the output of ADC  134 . FCU  116  then sets the duty cycle of DAC 0  and DAC 1  and injects a negative DC offset into DAC 0  and DAC 1  which defines the common mode and cancels the DC offset at SCF  700  output. 
     SCF  700  also contains control circuitry, not shown, that allows switches SA, SB and SX in IIR 1   710  to be disabled under program control while switches S A  and S B  continue to operate in IIR 2   720  to allow gain calibration of ABE  130 . 
       FIG. 8  is a timing diagram illustrating operation of control signals provided to the switched capacitor filter of  FIG. 7 . All of the control signals are non-overlapping so that one group of switches is turned off before the next group is turned on. The various arrows indicate signals that are critical for non-overlapped operation. Timing for signals S A , S B , S DA , S DB , S PA  and S PB  is the same as that shown in  FIG. 6 . Control signal S A  controls MOSFET switches S A , control signal S B  controls MOSFET switches S B , etc. Scenario  1   802  and scenario  2   804  illustrate two possible timing relationships with S A  and S B . 
     As mentioned earlier, switches DAC 0 , DAC 1 , DAC 0 Z and DAC 1 Z form one bit DAC  123 . Control signals S DAC0  and S DAC1  are modulated by a sigma-delta modulator in FCU  116  to have various duty cycles and to cancel DC offset Other sequences are generated as needed by FCU provide common mode control, as discussed above. 
       FIG. 9  is a block diagram of another digital system  1000  with an embodiment of a passive switched capacitor filter. Digital system  1000  a representative cell phone  1000  that includes an embodiment of the present invention for analog front end filtering using a passive configurable switched capacitor filter. Digital baseband (DBB) unit  1002  is a digital processing processor system that includes embedded memory and security features. In this embodiment, DBB  1002  is an open media access platform (OMAP™) available from Texas Instruments designed for multimedia applications. Some of the processors in the OMAP family contain a dual-core architecture consisting of both a general-purpose host ARM™ (advanced RISC (reduced instruction set processor) machine) processor and one or more DSP (digital signal processor). The digital signal processor featured is commonly one or another variant of the Texas Instruments TMS320 series of DSPs. The ARM architecture is a 32-bit RISC processor architecture that is widely used in a number of embedded designs. 
     Although the invention finds particular application to Digital Signal Processors (DSPs), implemented, for example, in an Application Specific Integrated Circuit (ASIC), it also finds application to other forms of processors. An ASIC may contain one or more megacells which each include custom designed functional circuits combined with pre-designed functional circuits provided by a design library. 
     Analog baseband (ABB) unit  1004  performs processing on audio data received from stereo audio codec (coder/decoder)  1009 . Audio codec  1009  receives an audio stream from FM Radio tuner  1008  and sends an audio stream to stereo headset  1016  and/or stereo speakers  1018 . In other embodiments, there may be other sources of an audio stream, such a compact disc (CD) player, a solid state memory module, etc. ABB  1004  receives a voice data stream from handset microphone  1013   a  and sends a voice data stream to handset mono speaker  1013   b . ABB  1004  also receives a voice data stream from microphone  1014   a  and sends a voice data stream to mono headset  1014   b . Usually, ABB and DBB are separate ICs. In most embodiments, ABB does not embed a programmable processor core, but performs processing based on configuration of audio paths, filters, gains, etc being setup by software running on the DBB. In an alternate embodiment, ABB processing is performed on the same OMAP processor that performs DBB processing. In another embodiment, a separate DSP or other type of processor performs ABB processing. 
     RF transceiver  1006  includes a receiver for receiving a stream of coded data frames from a cellular base station via antenna  1007  and a transmitter for transmitting a stream of coded data frames to the cellular base station via antenna  1007 . The transceiver includes an analog front end that incorporates a configurable passive switched capacitor (SCF) filter as described above. A control program executing on DBB  1002  can dynamically configure the capacitances and/or filter coefficients of the switched capacitor filter by setting various control bits in the control circuitry of the SCF as described above in order to adjust the operating characteristics of cell phone  1000  as needed. In this embodiment, a single transceiver supports both GSM and WCDMA operation by dynamically changing the filter characteristics of the SCM in the analog front end. Other embodiments may have transceivers for a later developed transmission standard with appropriate configuration of the SCF. RF transceiver  1006  is connected to DBB  1002  which provides processing of the frames of encoded data being received and transmitted by cell phone  1000 . RF transceiver  1006  contains an analog front end having a passive switched capacitor filter as described above. 
     The basic WCDMA DSP radio consists of control and data channels, rake energy correlations, path selection, rake decoding, and radio feedback. Interference estimation and path selection is performed by instructions stored in memory  1012  and executed by DBB  1002  in response to signals received by transceiver  1006 . 
     DBB unit  1002  may send or receive data to various devices connected to USB (universal serial bus) port  1026 . DBB  1002  is connected to SIM (subscriber identity module) card  1010  and stores and retrieves information used for making calls via the cellular system. DBB  1002  is also connected to memory  1012  that augments the onboard memory and is used for various processing needs. DBB  1002  is connected to Bluetooth baseband unit  1030  for wireless connection to a microphone  1032   a  and headset  1032   b  for sending and receiving voice data. 
     DBB  1002  is also connected to display  1020  and sends information to it for interaction with a user of cell phone  1000  during a call process. Display  1020  may also display pictures received from the cellular network, from a local camera  1026 , or from other sources such as USB  1026 . 
     DBB  1002  may also send a video stream to display  1020  that is received from various sources such as the cellular network via RF transceiver  1006  or camera  1026 . DBB  1002  may also send a video stream to an external video display unit via encoder  1022  over composite output terminal  1024 . Encoder  1022  provides encoding according to PAL/SECAM/NTSC video standards. 
     As used herein, the terms “applied,” “connected,” and “connection” mean electrically connected, including where additional elements may be in the electrical connection path. “Associated” means a controlling relationship, such as a memory resource that is controlled by an associated port. The terms assert, assertion, de-assert, de-assertion, negate and negation are used to avoid confusion when dealing with a mixture of active high and active low signals. Assert and assertion are used to indicate that a signal is rendered active, or logically true. De-assert, de-assertion, negate, and negation are used to indicate that a signal is rendered inactive, or logically false. 
     While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to persons skilled in the art upon reference to this description. For example, in another embodiment, a passive, configurable SCF with more than two poles or more than two stacked capacitors may be implemented. 
     It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope and spirit of the invention.