Patent Publication Number: US-7596651-B2

Title: Multi-character adapter card

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to computer adapter cards and more particularly to computer adapter cards having improved versatility. 
   2. Description of the Related Art 
   To provide additional versatility and functionality, today&#39;s computer systems are often designed to accept and interface with adapter cards, also known as expansion boards, accessory cards, or expansion cards. These adapter cards are generally printed circuit boards that can be inserted into or otherwise connected to an expansion slot or connector on a computer&#39;s motherboard. Many adapter cards incorporate one or more ASIC chips (“ASICs”) designed to provide unique functions to the adapter cards. These ASICs may be used in place of a general-purpose commercial logic chips to simplify the design of the circuit board. Many ASICs integrate several functions or logic control blocks into a single chip. Although development costs can be quite high, ASICs may lower manufacturing costs where large quantities of the chips are needed. 
   Many adapter cards include a memory device such as an EEPROM, flash memory, or other programmable device interface which can be used to personalize ASICs on the adapter cards. For example, code or data stored on a memory device may be used to set internal registers of the ASIC. The ASIC may read this code or data when the chip is powered on, after a reset, or when code instructs it to do so. This allows an adapter card to become active with a defined personality or character. 
   In some cases, it may be desirable for an adapter card to exhibit different characteristics depending on the application of the adapter card or where the adapter card is placed in a computer system. In some cases, multiple versions of an adapter card may be provided to handle different applications or configurations of a computer system. In certain cases, this is accomplished using different ASICs in adapter cards intended for different applications. In other cases, the personality or characteristics of an adapter card might be programmed by external software to configure the adapter card for a particular application. Although effective, these techniques can be inefficient and costly. 
   In view of the foregoing, what is needed is an adapter card capable of assuming multiple personalities or characters. Such an adapter carder could be used to exhibit different characteristics depending on the application of it used for or where the adapter card is placed in a computer system. Ideally, such an adapter card could utilize the same ASIC for both applications and could be programmed without the need for external software. Further needed is an adapter card that can be switched from one character to another using a simple external control. 
   SUMMARY OF THE INVENTION 
   The present invention has been developed in response to the present state of the art, and in particular, in response to the problems and needs in the art that have not yet been fully solved by currently available apparatus and methods. Accordingly, the present invention has been developed to provide an adapter card capable of assuming multiple personalities or characters and which is dynamically reconfigurable in situ. 
   In a first aspect of the invention, one embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data. 
   In selected embodiments, the one or more programmable devices include first and second programmable devices wherein the first programmable device stores the first character data and the second programmable device stores the second character data. In such embodiments, the switching mechanism may modify an address of the first and second programmable devices to switch between the first and second character data. In other embodiments, the switching mechanism may selectively assert and de-assert a chip select line of the first and second programmable devices to switch between the first and second character data. 
   In other embodiments, the one or more programmable device may include a single programmable device storing both the first and second character data in different address ranges of the programmable device. In such embodiments, the switching mechanism may modify an address used to access the character data on the single programmable device, thereby causing the logic chip to read from a different address range of the single programmable device. 
   In another aspect of the invention, one embodiment of a method in accordance with the invention includes providing an adapter card connectable to a motherboard of a computer system and integrating, on the adapter card, a logic chip to provide functionality to the adapter card. The method includes reading data, by the logic chip, upon initialization. This data may include first character data to program the logic chip to have a first character, and second character data to program the logic chip to have a second character. The method includes switching, in response to an external input, between the first and second character data, thereby causing the logic chip to read one of the first and second character data. 
   In another aspect of the invention, one embodiment of a system includes a computer system configured to receive an adapter card to enhance the functionality of the computer system. An adapter card is connected to the computer system and includes a logic chip connected to the adapter card to provide functionality to the adapter card. One or more programmable devices are connected to the adapter card to store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism, controlled by an external input, switches between the first and second character data, thereby causing the logic chip to read one of the first and second character data. 
   In yet another aspect of the invention, one embodiment of an apparatus includes means for connecting an adapter card to a computer system to enhance the functionality thereof. The adapter card includes a logic chip to provide functionality to the adapter card. The apparatus further includes means for storing data read by the logic chip upon initialization. This data includes first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. The apparatus also includes means for switching, in response to an external input, between the first and second character data such that the logic chip assumes one of the first and second characters. 
   In another aspect of the invention, an apparatus in accordance with the invention includes an adapter card connectable to a motherboard of a computer system and an application-specific integrated chip (ASIC) integrated with the adapter card to provide functionality thereto. The ASIC includes at least one register. One or more programmable devices are integrated onto the adapter card to store data loaded into the at least one register upon initialization. This data includes first character data to program the ASIC with a first character, and second character data to program the ASIC with a second character. A switching mechanism, controlled by an external input, is provided to switch between the first and second character data, thereby causing the at least one register to load one of the first and second character data. 
   The present invention provides a novel adapter card capable of assuming multiple characters. The features and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order that the advantages of the invention will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which: 
       FIG. 1  is a high-level schematic block diagram of one embodiment of a computer system for receiving an adapter card in accordance with the invention; 
       FIG. 2  is a high-level schematic block diagram of one embodiment of an adapter card utilizing a card input to modify the address of two or more programmable devices; 
       FIG. 3  is a high-level schematic block diagram of one embodiment of an adapter card utilizing a card input to assert and de-assert a chip select line of two or more programmable devices; 
       FIG. 4  is a high-level schematic block diagram of one embodiment of an adapter card utilizing a card input to modify the address space accessed on a programmable device; 
       FIG. 5  is a high-level schematic block diagram of one embodiment of an adapter card using one or more switches, coupled to a card input, to toggle between two or more programmable devices; 
       FIG. 6  is a high-level schematic block diagram of one embodiment of an adapter card using a manually operated switch to toggle between two programmable devices; 
       FIG. 7  is a high-level schematic block diagram of one embodiment of an adapter card using a manually operated switch to modify the address of two or more programmable devices; 
       FIG. 8  is a high-level schematic block diagram of one embodiment of an adapter card utilizing a manually operated switch to assert and de-assert a chip select line of two or more programmable devices; and 
       FIG. 9  is a high-level schematic block diagram of one embodiment of an adapter card utilizing a manually operated switch to modify the address space accessed in a programmable device. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   It will be readily understood that the components of the present invention, as generally described and illustrated in the Figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of the embodiments of apparatus and methods in accordance with the present invention, as represented in the Figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of certain examples of presently contemplated embodiments in accordance with the invention. The presently described embodiments will be best understood by reference to the drawings, wherein like parts are designated by like numerals throughout. 
   Referring to  FIG. 1 , one embodiment of a computer system  10  useable with an adapter card  42  in accordance with the invention is illustrated. As shown, a computer system  10 , such as a personal computer  10 , a workstation  10 , a server  10 , or other computer  10  may include various components providing various functionalities thereto. For example, a computer system  10  may include a central processing unit  12  to process executable and operational data stored in a connected memory device such as random access memory  16 , or a hard drive connected to an IDE port  32 . The CPU  12  may be connected to a main or local bus  14  having a relatively large bandwidth to accommodate the speed of the CPU  12 . The local bus  14  may be connected to various high-speed memory devices  16 ,  18  where instructions and operational data may be stored for ready and immediate access by the CPU  12 . 
   The controller  20  may act as an interface  20  between the CPU  12  and the memory  16 ,  18 . For example, local memory may include an L2 cache  18  and random access memory  16 . The L2 cache  18  may be used to speed up data transfers between the CPU  12  and random access memory  16 . The L2 cache  18  may also serve as a staging area to speed up instruction execution and data retrieval. The local bus  14  may connect to a bridge  22  acting as an interface between the local bus  14  and other buses  24 , such as a PCI bus  24 . The bridge  22  may function as an arbitrator or “traffic cop” for data exchanges between the buses  14 ,  24 , and may resolve differences in protocols, clock speeds, and the like between the buses  14 ,  24 . 
   A bus, such as a PCI bus  24 , may be used to interconnect, switch, or multiplex data exchanged between various onboard devices  28 ,  30 ,  32 ,  34 , as well as add-on or adapter cards  42   a ,  42   b  (also expansion cards, expansion boards, and accessory cards) installed into one or several expansion slots  26   a - c . In certain embodiments, a PCI bus  24  may implement technologies such as PCI-X or PCI-E that provide significant increases in bandwidth. In certain embodiments, a secondary bus  24 , such as a PCI bus  24 , may support sound hardware  28 , video hardware  30 , IDE ports  32  for interfacing with hard drives or other storage devices, or any other number of components  34 . 
   In a similar manner, a secondary bus  24 , such as a PCI bus  24 , may connect to one or several other bridges  36  for interfacing with other buses  38 ,  42 , or components. For example, a bridge  36  may interface with other slower legacy buses  38 ,  39  having lower bandwidths. A legacy bus  38 ,  39  may interface with older but still useful adapter cards  42   c , or other components  44 ,  46 ,  48 . For example, a bridge  36  may connect to an ISA bus  38  (Industry Standard Architecture) that accepts many slower legacy adapter cards  42   c . The bridge  36  may also connect to devices such as a real-time clock  46  that may store the current time and date even when the computer system  10  is powered off. 
   Other devices in the computer system  10  may include non-volatile memory  48  storing a basic input output system  48  (BIOS) to provide an interface between an installed operating system and hardware in the computer system  10 . Other devices may include a keyboard and mouse controller  44 , or other controllers  44 , providing basic input and output functionality to external devices such as mice, keyboards, and the like. 
   Referring to  FIG. 2 , as mentioned, an adapter card  42  may be used to provide additional versatility and functionality to a computer system  10 . In selected embodiments, an adapter card  42  may include a circuit board insertable or otherwise connectable to an expansion slot or connector of a computer system  10 , most typically on the computer&#39;s motherboard. Many adapter cards  42  include one or more logic chips  44 , most typically ASICs, but which may also include programmable gate arrays, general purpose processors, or other types of integrated circuits. In certain embodiments, an ASIC  44  may be designed to provide unique functions to the adapter card  42  and may integrate several functions or logic control blocks into a single chip. 
   In certain embodiments, the logic chip  44  may read configuration and other programming data from a programmable device, such as a ROM, PROM, EEPROM, flash memory, or other programmable device mounted to the adapter card  42 . For example, this data may be read into internal registers of an ASIC  44  when the chip is powered on, after a reset, or when code indicates that it should read the data. This data may give the ASIC  44  a defined personality or character. 
   In some cases, it may be desirable for an adapter card  42  to exhibit different characteristics depending on the application of the adapter card  42  or where the adapter card  42  is placed in a computer system  10 . To provide this functionality, an adapter card  42  in accordance with the invention may be equipped to assume one of several characters  48   a ,  48   b  in situ (i.e., after installation or connection to a computer system  10 ). The configuration data used to program the logic chip  44  with these distinct characters  48   a ,  48   b  will be labeled “character 1” and “character 2” herein for discussion purposes. 
   In selected embodiments, an adapter card  42  in accordance with the invention may be equipped with multiple programmable devices  46   a ,  46   b , each storing distinct character data  48   a ,  48   b . In certain embodiments, the logic chip  44  may be configured to read character data  48   a ,  48   b  from a specific address when the chip  44  is powered on, reset, or when instructed to do so by code. For example, where a logic chip  44  communicates with a programmable device  46   a ,  46   b  by way of an I2C interface (i.e., over an I2C bus  50 ), the logic chip  44  may attempt to access character data by transmitting a specific address onto the bus  50  along with a request to read data located at the address. A programmable device  46   a ,  46   b  having the address assigned thereto may then respond with an acknowledge signal and transmit the character data  48   a ,  48   b  to the logic chip  44  onto the bus  50 . The logic chip  44  may then receive and configure itself with the character data received over the bus  50 . 
   Because the logic chip  44  requests data from a specific address, a switching mechanism  52  may be used to switch between the character data  48   a ,  48   b  by modifying the address of each programmable device  46   a ,  46   b . In certain embodiments, an address of a programmable device  46   a ,  46   b  may be set by way of several I/O pins (e.g., three I/O pins) on the programmable device  46   a ,  46   b . In certain embodiments, a card input  54  may be connected to one or more of the I/O pins of a first programmable device  46   a  and the inverse  56  of the card input  54  may be connected to the corresponding I/O pins of a second programmable device  46   b.    
   In this way, the value of the card input  54  may be used to alter the address of each programmable device  46   a ,  46   b  such that it matches the specific address accessed by the logic chip  44 . For example, a high value on the card input  54  may be used to set the address of a first programmable device  46   a  to match the specific address used by logic chip  44  (while changing the address of the second programmable device  46   b  to one not matching the specific address). Similarly, a low value on the card input  54  may be used to set the address of a second programmable device  46   b  to match the specific address used by logic chip  44  (while changing the address of the first programmable device  46   a  to one not matching the specific address). In this way, the logic chip  44  may initialize and program itself with one of two distinct versions of character data  48   a ,  48   b  depending on the value of the card input  54 . 
   In certain embodiments, the card input  54  may be controlled with hardware or software on the computer system  10  and external to the adapter card  42 . In this way, the computer system  10  may be able to control and set the character of the adapter card  42  as needed to fit a particular application. As will be explained in more detail hereafter, in other embodiments the card input  54  may be controlled through a manual action (e.g., manually flipping a switch). 
   Referring to  FIG. 3 , in another embodiment, a switching mechanism  52  may be used to select one of several programmable devices  46   a ,  46   b  connected to a common bus  50  by asserting and de-asserting a chip select line of each programmable device  46   a ,  46   b . For example, a card input  54  may be connected to a chip select line of a first programmable device  46   a  and the inverse  56  of the card input  54  may be connected to a chip select line of a second programmable device  46   b . Other methods for asserting and de-asserting chip select lines may be used where there are more than two programmable devices  46   a ,  46   b  or where other devices are also connected to the bus  50 . Upon initialization, the logic chip  44  may then read character data  48   a ,  48  from the programmable device  46   a ,  46   b  having the asserted chip select line. 
   Referring to  FIG. 4 , in another embodiment, different character data  48   a ,  48   b  may be stored in a single programmable device  46  in different address ranges. An external control, such as the card input  54 , may be used to select which character data  48   a ,  48   b  is read by the logic chip  44 . For example, in selected embodiments, a logic chip  44  may access a programmable device  46 , such as flash memory, by way of a parallel address. First character data  48   a  may be stored in a high half of the programmable device  46  and second character data  48   b  may be stored in a low half of the programmable device  46 . 
   A switching mechanism  52  may include a card input  54  to control a high order address bit of an address transmitted to the programmable device  46 . In this way, a high value on the card input  54  may be used to access the high half of the programmable device  46  and thereby read first character data  48   a . A low value on the card input  54  may be used to access a low half of the programmable device  46  and thereby read second character data  48   b . Thus, a switching mechanism  52  in accordance with the invention may also be used to switch between different versions of character data  48   a ,  48   b  stored in a single programmable device  46 . 
   Referring to  FIG. 5 , in another embodiment, a switching mechanism  52  may include one or more switches  60   a ,  60   b  to switch between several programmable devices  46   a ,  46   b . For example, switches  60   a ,  60   b  may be used to selectively connect and disconnect each programmable device  46   a ,  46   b  from a bus  50 . In such an embodiment, each programmable device  46   a ,  46   b  may be assigned the same address or range of addresses. A card input  54  may be used to control each of the switches  60   a ,  60   b . For example, the card input  54  may be connected to a first switch  60   a  and the inverse  56  of the card input  54  may be connected to a second switch  60   b . Thus, when the first switch  60   a  is closed, the other switch  60   b  is open and vice versa. Thus, only one programmable device  46   a ,  46   b  is connected to the bus  50  at any given time. 
   When the logic chip  44  attempts to read character data from the address assigned to the programmable devices  46   a ,  46   b , data is retrieved from the programmable device  46   a ,  46   b  connected to the bus  50 . Thus, one of two versions of character data  48   a ,  46   b  may be read from the programmable devices  46   a ,  46   b  depending on the value of the card input  54 . This enables different character data to be read by the logic chip  44  by simply changing the card input  54   
   Referring to  FIG. 6 , in other embodiments, a switching mechanism  52  may include a manually operated switch  62  to switch between different programmable devices  46   a ,  46   b , each storing different character data  48   a ,  48   b . For example, the switch  62  in a first (e.g., upward) position may create a connection between the logic chip  44  and a first programmable device  46   a  while disconnecting a second programmable device  46   b  from the logic chip  44 . The switch  62  in a second (e.g., downward) position may open the connection between the logic chip  44  and the first programmable device  46   a  and create a connection between the logic chip  44  and the second programmable device  46   a . Such a switch  62  may be used to create a direct connection between the logic chip  44  and one of the programmable devices  46   a ,  46   b , or be used to connect one of the programmable devices  46   a ,  46   b  to a bus connected to the logic chip  44 . 
   Referring to  FIG. 7 , in another embodiment, a switching mechanism  52  may include a manually operated switch  62  to alter the address of various programmable devices  46   a ,  46   b . For example, as previously mentioned, an address of a programmable device  46   a ,  46   b  may be set by way of various I/O pins connected to the programmable device  46   a ,  46   b . In certain embodiments, a first output  64   a  of a switch  62  may be connected to one or more address pins of one programmable device  46   a  and a second output  64   b  of the switch  62  may be connected to one or more address pins of the other programmable device  46   b . A power source  66  may provide power to the switch  62  to direct to the outputs  64   a ,  64   b.    
   In this way, the switch  62  may be used to alter the addresses of the programmable devices  46   a ,  46   b  such that the address of one programmable device  46   a ,  46   b  matches a specific address accessed by the logic chip  44 . For example, a high value on the output  64   a  (with a low value on the output  64   b ) may be used to set the address of a first programmable device  46   a  to match the specific address accessed by logic chip  44 . Similarly, a high value on the output  64   b  (with a low value on the output  64   a ) may be used to set the address of a second programmable device  46   b  to match the specific address used by the logic chip  44 . In this way, the logic chip  44  may initialize and program itself with one of two versions of character data  48   a ,  48   b  depending on the value of the outputs  64   a ,  64   b.    
   Referring to  FIG. 8 , in another embodiment, a switching mechanism  52  may include a manually operated switch  62  to select one of several programmable devices  46   a ,  46   b  connected to a common bus  50 . The switch  62  may be used to assert and de-assert chip select lines of each programmable device  46   a ,  46   b . For example, a first output  64   a  of the switch  62  may be connected to a chip select line of a first programmable device  46   a  and a second output  64   b  of the switch  62  may be connected to a chip select line of a second programmable device  46   b . The chip select line of the first programmable device  46   a  may be asserted when the switch  62  is in a first position (e.g., upward) and the chip select line of the second programmable device  46   b  may be asserted when the switch  62  is in a second position (e.g., downward). Only one chip select line is asserted at any one time. The logic chip  44  may then read character data  48   a ,  48   b  from the programmable device  46   a ,  46   b  having the asserted chip select line. 
   Referring to  FIG. 9 , in another embodiment, various versions of character data  48   a ,  48   b  may be stored in different address ranges of a single programmable device  46 . A switching mechanism  52  may include a manually operated switch  62  to select which character data is read by the logic chip  44 . For example, where the logic chip  44  accesses the programmable device  46  by way of a parallel address, first character data  48   a  may be stored in a high half of the programmable device  46  and second character data  48   b  may be stored in a low half of the programmable device  46 . 
   The switch  62  may be used to control a high order address bit of an address transmitted to the programmable device  46 . Thus, a high value on the output  64  of the switch  62  may be used to access the high half of the programmable device  46  to read the first character data  48   a . A low value on the output  64  may be used to access a low half of the programmable device  46  to read second character data  48   b . In this way, the switch  62  may be used to switch between several versions of character data  48   a ,  48   b  stored in a single programmable device  46 . 
   The adapter cards  42  illustrated in  FIGS. 2 through 9  may be used in a wide variety of applications where two or more different characters  48   a ,  48   b  are needed or desirable. For example, in one embodiment, an adapter card  42  may be provided with PCIE ports that attach to two different computer systems  10 . The CPU  12  of each computer system  10  may utilize generic discovery code to discover the adapter card  42 . One PCIE port on the adapter card  42  may appear to be an endpoint while the other PCIE port may appear to be a switch. The adapter card  42  may be owned by either CPU  12 . 
   Accordingly, the owning CPU  12  may see a switch so that it can configure the card, whereas the non-owning CPU  12  may see an endpoint so that it stops at that port. When ownership changes, the ports may be reconfigured so that the CPU  12  which previously saw an endpoint sees a switch, and vice versa. This is an example of how an adapter card  42  may be programmed or initialized with two different characters  48   a ,  48   b , or configurations. The card I/O  54  may be used to designate which CPU  12  owns the adapter card  42  and to initialize the ports appropriately. This allows for rapid initialization and reduces the need for complicated system software to reconfigure the adapter card  42 . 
   The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.