Patent Publication Number: US-11049950-B2

Title: Trench power seminconductor device and manufacturing method thereof

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
     This application claims the benefit of priority to Taiwan Patent Application No. 105129317, filed on Sep. 9, 2016. The entire content of the above identified application is incorporated herein by reference. 
     This application is a divisional application of Ser. No. 15/641,455 filed on Jul. 5, 2017, and entitled “TRENCH POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”, now pending, the entire disclosures of which are incorporated herein by reference. 
     Some references, which may include patents, patent applications and various publications, may be cited and discussed in the description of this disclosure. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to the disclosure described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure is related to a power semiconductor and a manufacturing method thereof, and in particular, to a trench power transistor and a manufacturing method thereof. 
     2. Description of Related Art 
     Current power metal-oxide-semiconductor field-effect transistors (power MOSFET) are designed to have a vertical structure to improve the packing density. The working loss of power MOSFFT is categorized into switching loss and conducting loss. In addition, the intrinsic gate-to-drain capacitance (Cgd) is one of the important parameters affecting switching loss. When the intrinsic gate-to-drain capacitance is too high, the switching loss increases, which may limit the switching speed of the power trench MOSFET and may lead to the trench power MOSFET being unfavorable to be implemented in high frequency circuits. 
     SUMMARY 
     The object of the present disclosure is to provide a trench power semiconductor device and a manufacturing method thereof, which can decrease the effective capacitance between the gate and the drain by using a gate having a PN junction formed therein. 
     In order to achieve the aforementioned object, according to an embodiment of the present disclosure, a manufacturing method of a trench power semiconductor device is provided. The manufacturing method includes forming an epitaxial layer on a substrate; forming a body region into the epitaxial layer; and forming a trench in the epitaxial layer. Then, an initial gate structure is formed into the trench. The initial gate structure includes a gate insulating layer covering the trench, a laminated layer covering the gate insulating layer corresponding to the lower part of the trench, a first heavily doped semiconductor structure extending from the lower part of the trench to the upper part of the trench, and two second heavily doped semiconductor structures disposed on the laminated layer. Each of the two second heavily doped semiconductor structures is individually disposed between the gate insulating layer and the first heavily doped semiconductor structure. The first heavily doped semiconductor structure and the second heavily doped semiconductor structure have a first conductive impurity and a second conductive impurity, respectively. Then, a doping process is performed, in which a second conductive impurity is implanted into the body region to form a first surface doped region and to form a second surface doped region on the top of the first heavily doped semiconductor structure simultaneously. Afterwards, a thermal diffusion process is performed, so that the first surface doped region forms a source region, and a gate is formed in the trench. In addition, the gate includes a lower doped region surrounded by the laminated layer, and an upper doped region on the laminated layer and the lower doped region, and a PN junction is formed between the lower doped region and the upper doped region. 
     In order to achieve the aforementioned object, according to another embodiment of the present disclosure, a trench power semiconductor device is provided. The trench power semiconductor device includes a substrate, an epitaxial layer and a gate structure. The epitaxial layer is disposed on the substrate, and has a trench. The gate structure is disposed in the trench, and includes a gate insulating layer, a laminated layer and a gate. The gate insulating layer covers an inside wall surface of the trench. The laminated layer covers the gate insulating layer corresponding to the lower part of the trench. The gate is disposed in the trench, and separated from the laminated layer and the epitaxial layer by the gate insulating layer. The gate includes an upper doped region on the laminated layer and a lower doped region surrounded by the laminated layer, a PN junction is formed between the upper doped region and the lower doped region, and the impurity concentration of the upper doped region decreases along the direction from the peripheral portion of the upper doped region to the central portion of the upper doped region. 
     To sum up, in the trench power semiconductor device and the manufacturing method thereof in accordance with the present disclosure, the PN junction can be formed in the gate. Since a junction capacitance (Cj) of the PN junction is generated under reverse bias, and the junction capacitance is in series with the parasitic capacitance (Cp) between the gate and the drain, the effective capacitance (Cgd) of gate-to-drain can be reduced. On the other hand, in the manufacturing method of the trench power semiconductor device, structures in the trench are doped during performing of the source doping process. Afterwards, the thermal diffusion process is performed, so as to simultaneously form the source region and the gate with a PN junction. Therefore, the diffusion of the conductive impurities in the upper doped region and the lower doped region of the gate, which causes the lack of the PN junction in the gate and poor characteristics of devices due to repeated thermal diffusion processes, can be prevented. 
     In order to further understand the techniques, means and effects of the present disclosure, the following detailed descriptions and appended drawings are hereby referred to, such that, and through which, the purposes, features and aspects of the present disclosure can be thoroughly and concretely appreciated; however, the appended drawings are merely provided for reference and illustration, without any intention to be used for limiting the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. 
         FIG. 1  is a flow diagram of a manufacturing method of a trench power semiconductor device according to an exemplary embodiment of the present disclosure. 
         FIGS. 2A-2J  are diagrams individually showing local sectional views of a trench power semiconductor device in each step of the manufacturing method according to an exemplary embodiment of the present disclosure. 
         FIG. 3  is a local sectional view of the trench power semiconductor device according to an exemplary embodiment of the present disclosure. 
     
    
    
     DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
       FIG. 1  shows a flow diagram of a manufacturing method of a trench power semiconductor device according to an exemplary embodiment of the present disclosure. Referring to  FIGS. 2A-2J , which individually show local sectional views of a trench power semiconductor device in each step of the manufacturing method according to an exemplary embodiment of the present disclosure. 
     In step S 100 , an epitaxial layer  11  is formed on a substrate  10 , as shown in  FIG. 2A .  FIG. 2A  illustrates the substrate  10 , and the epitaxial layer  11  is formed on the substrate  10 . The substrate  10  may exemplarily be a silicon substrate having a first heavily doped region with high doping concentration as a drain of the trench power MOSFET, while the epitaxial layer  11  is provided with low doping concentration. 
     The substrate  10  has a first conductive impurity with high concentration, so as to form the first heavily doped region. The first heavily doped region is used as the drain of the trench power MOSFET, and the first heavily doped region can be distributed at a local region or a whole region of the substrate  10 . In accordance with the present embodiment, the first heavily doped region is distributed in the whole region of the substrate  10 , but the present embodiment is not limited thereto. The said first conductive impurity may be N-type or P-type conductive impurities. If the substrate  10  is a silicon substrate, the N-type conductive impurities may be Group VA atoms such as phosphorus or arsenic, and the P-type conductive impurities may be Group III atoms such as boron, aluminum or gallium. 
     If the trench power MOSFET is N-type, the substrate  10  is doped with N-type conductive impurities. Similarly, if the trench power MOSFET is P-type, the substrate  10  is doped with P-type conductive impurities. The N-type trench power MOSFET is illustrated in the embodiment of the present disclosure. 
     The epitaxial layer  11  is formed on the substrate  10  and doped with a lower concentration of the first conductive impurity. That is, taking the N-type trench power MOSFET (NMOS) for example, the substrate  10  is a heavily N-type doped (N+) substrate and the epitaxial layer  11  is a lightly N-type doped (N−) layer. On the contrary, taking the P-type trench power MOSFET (PMOS) for example, the substrate  10  is a heavily P-type doped (P+) substrate and the epitaxial layer  11  is a lightly P-type doped (P−) layer. 
     In step S 101 , a body region  111  is formed in the epitaxial layer  11  and disposed at a side away from the substrate  10 , as shown in  FIG. 2A . In addition, the region excluding the body region  111  in the epitaxial layer  11  forms a drift region  110  of the trench power semiconductor device. 
     According to the present embodiment, the body-doping process and the body-thermal diffusion process are performed in advance, so that the body region  111  is formed in the epitaxial layer  11 . This is to prevent the doped structure in the gate structure from being affected by the body region during the thermal diffusion process. 
     Afterwards, the trench is formed in the epitaxial layer in step S 102 . The trench  112  of the present disclosure is a deep trench, as shown in  FIG. 2B . The trench  112  extends downwardly from the surface of the epitaxial layer  11  to the drift region  110  and particularly, over the body region  111 , such that the bottom of the trench  112  nears the substrate  10 . 
     More particularly, in the step for forming the trench  112 , a mask (not shown) is used to define the positions of the gate structure in advance, and the trench  112  can be formed in the epitaxial layer  11  by performing dry etching or wet etching. 
     Then, the initial gate structure is formed in the trench in step S 103 .  FIGS. 2C-2H  illustrate the detail processes of forming the initial gate structure of the embodiment of the present disclosure. 
     Firstly, the gate insulating layer  120 , a first initial dielectric layer  122 ′ and a second initial dielectric layer  123 ′ are sequentially formed in the inside wall surface  112   a  of the trench  112 , as shown in  FIG. 2C . Particularly, the gate insulating layer  120 , the first initial dielectric layer  122 ′ and the second initial dielectric layer  123 ′ cover the whole surface of the epitaxial layer  11  and the inside wall surface  112   a  of the trench  112 . 
     In addition, the materials of which the first initial dielectric layer  122 ′ is composed are different from the materials of which the second initial dielectric layer  123 ′ and the gate insulating layer  120  are composed. For instance, the materials of which the gate insulating layer  120  and the second initial dielectric layer  123 ′ are composed may be oxide, such as silicon oxide; the materials of which the first initial dielectric layer  122 ′ is composed may be nitride, such as silicon nitride. Specifically, the materials of the gate insulating layer  120 , the first initial dielectric layer  122 ′ and the second initial dielectric layer  123 ′ not limited to that disclosed in the present disclosure, as long as the second initial dielectric layer  123 ′ and the first initial dielectric layer  122 ′ are provided with high etch selectivity therebetween, and the first initial dielectric layer  122 ′ and the gate insulating layer  120  are provided with high etch selectivity therebetween, so that selective etching can be performed in following processes. 
     The aforementioned etch selectivity means the etching ratio between two different materials (e.g. the first initial dielectric layer  122 ′ and the second initial dielectric layer  123 ′, or the gate insulating layer  120  and the first initial dielectric layer  122 ′) under the same etching conditions. Since the etch selectivity between the second initial dielectric layer  123 ′ and the first initial dielectric layer  122 ′ is high, the first initial dielectric layer  122 ′ is not removed during the etch process for removing the second initial dielectric layer  123 ′. Similarly, since the first initial dielectric layer  122 ′ and the gate insulating layer  120  are provided with the high etch selectivity therebetween, the gate insulating layer  120  is not removed when performing the etch process to eliminate the first initial dielectric layer  122 ′. 
     Then, referring to  FIG. 2D , the first heavily doped semiconductor structure  125 ′ is formed in the trench  112 , and extends from the upper part to the lower part of the trench  112 . 
     In one embodiment, the first conductive semiconductor material is formed on the second initial dielectric layer  123 ′ in advance, then filled into the trench  112 . The first conductive semiconductor material may be the doped polycrystalline silicon (poly-Si) containing conductive impurities. The method for forming the first conductive semiconductor material may be the in-situ doping CVD process. In another embodiment, the intrinsic polycrystalline silicon (poly-Si) is deposited, followed by performing the ion implantation to implant the impurities into the polycrystalline silicon. Afterwards, the thermal drive-in process is performed, thereby finishing the formation of the first conductive semiconductor material. 
     Then, the first conductive semiconductor material on the epitaxial layer  11  is removed by etching back, which leaves the first conductive semiconductor material in the trench  112  to form the first heavily doped semiconductor structure  125 ′. The first heavily doped semiconductor structure  125 ′ has a first side S 1  and a second side S 2  facing the first side S 1 . 
     The first heavily doped semiconductor structure  125 ′ includes the first conductive impurity, which can be N-type impurities or P-type impurities. Particularly, when the desired trench power semiconductor device is N-type MOSFET, the first heavily doped semiconductor structure  125 ′ is doped with P-type impurities so as to form the P-type semiconductor structure. When the trench power semiconductor device is P-type MOSFET, the first heavily doped semiconductor structure  125 ′ is doped with N-type impurities so as to form the N-type semiconductor structure. 
     Referring to  FIG. 2E , the second initial dielectric layer  123 ′ at the upper part of the trench  112  is removed. In particular, the second initial dielectric layer  123 ′ on the epitaxial layer  11  and at the upper part of the trench  112  is removed to form a second dielectric layer  123  at the lower part of the trench  112 . 
     In one embodiment, a part of the second initial dielectric layer  123 ′ can be removed by wet etching. It is worth noting that the second initial dielectric layer  123 ′ and the first heavily doped semiconductor structure  125 ′ are provided with the high etch selectivity, and therefore the first heavily doped semiconductor structure  125 ′ is used as a mask when eliminating the second initial dielectric layer  123 ′ at the upper part of the trench  112 . 
     In addition, the high etch selectivity also exists between the second initial dielectric layer  123 ′ and the first initial dielectric layer  122 ′. Therefore, the first initial dielectric layer  122 ′ is retained to protect the gate insulating layer  120  when the second initial dielectric layer  123 ′ at the upper part of the trench  112  is etched. 
     Afterwards, as shown in  FIG. 2F , the first initial dielectric layer  122 ′ at the upper part of the trench  112  is removed to form the laminated layer  121  at the lower part of the trench  112 . 
     In detail, the first initial dielectric layer  122 ′ on the epitaxial layer  11  and at the upper part of the trench  112  will be removed, so that the first dielectric layer  122  is formed at the lower part of the trench  122 . 
     Similarly, the first heavily doped semiconductor structure  125 ′ and the second initial dielectric layer  123  are used as a mask when eliminating a part of the first initial dielectric layer  122 ′ by the etch process. On the other hand, since the first initial dielectric layer  122 ′ and the gate insulating layer  120  are provided with the high etch selectivity therebetween, the gate insulating layer  120  will be retained during the elimination of the part of the first initial dielectric layer  122 ′. 
     In sum, after removing the parts of the first initial dielectric layer  122 ′ and the second initial dielectric layer  123 ′, the laminated layer  121  is formed at the lower part of the trench  112 . The laminated layer  121  covers the lower part of the inner surface  120   s  of the gate insulating layer  120 , and includes the first dielectric layer  122  and the second dielectric layer  123 . In the present embodiment, the top of the laminated layer  121  is lower than the bottommost edge of the body region  111 , that is, lower than the level of the lowest point of the body region  111 . 
     In addition, as shown in  FIG. 2F , after removing the parts of the first initial dielectric layer  122 ′ and the second initial dielectric layer  123 ′, the upper part of the inner surface  120   s  of the gate insulating layer  120 , a part of the first side S 1  and a part of the second side S 2  of the first heavily doped semiconductor structure  125 ′ are exposed. In other words, two grooves h are formed by individually removing the upper part of the first initial dielectric layer  122 ′ and the upper part of the second initial dielectric layer  123 ′. The two grooves h are disposed respectively between the gate insulating layer  120  and the first side S 1 , and between the gate insulating layer  120  and the second side S 2 . 
     Referring to  FIG. 2G , the second conductive semiconductor material  126 ′ is formed to completely cover the first heavily doped semiconductor structure  125 ′ and the gate insulating layer  120 , as well as to fill into the two grooves h. 
     The second conductive semiconductor material  126 ′ contains the second conductive impurity, which can be N-type impurities or P-type impurities. The second conductive semiconductor material  126 ′ can be doped poly-Si. When the trench power semiconductor device is N-type MOSFET, the second conductive semiconductor material  126 ′ is doped with N-type impurities; when the trench power semiconductor device is P-type MOSFET, the second conductive semiconductor material  126 ′ is doped with P-type impurities. That is, the conductive type of the second conductive semiconductor material  126 ′ is opposite to the conductive type of the body region  111  and the first heavily doped semiconductor structure  125 ′. In one embodiment, the second conductive semiconductor material  126 ′ can be formed by performing the in-situ doping CVD process. 
     Afterwards, referring to  FIG. 2H , the second conductive semiconductor material  126 ′ on the epitaxial layer  11  is removed by etching back, so that each of the two second heavily doped semiconductor structures  126 ″ is formed respectively in each of the two grooves h. The initial gate structure  12 ′ is formed through the aforementioned steps. 
     Then, referring to  FIG. 1  again, a doping process is performed in step S 104 , in which a second conductive impurity is additively implanted into the body region to form a first surface doped region and to form a second surface doped region on the top of the first heavily doped semiconductor structure simultaneously. 
     Particularly, in the present embodiment, the ion implantation is performed for the body region  111  and the initial gate structure  12 ′ without using any masks. During the ion implantation, the second conductive impurity is implanted in the body region  111  and the initial gate structure  12 ′, so as to form a first surface doped region A 1  at the surface of the body region  111 , and to form a second surface doped region A 2  on the top of the first heavily doped semiconductor structure  125 ″ and the top of the second heavily doped semiconductor structure  126 ″ simultaneously. 
     The second surface doped region A 2  includes a first region A 21  of the first heavily doped semiconductor structure  125 ″ and a second region A 22  on the top of the two second heavily doped semiconductor structures  126 ″. 
     It is worth noting that the first conductive impurity is already present in the first heavily doped semiconductor structure  125 ″, and the concentration of the implanted second conductive impurity is much higher than the concentration of the first conductive impurity in the first heavily doped semiconductor structure  125 ″ after implanting the second conductive impurity by the doping process. Therefore, the conductivity of the first region A 21  is similar to the second conductive type, that is, the same conductive type as that of the second heavily doped semiconductor structure  126 ″. 
     Then, the thermal diffusion process is performed in the step S 105 , so that the first surface doped region forms a source region and a gate is formed in the trench. 
     Referring to  FIG. 2J , the gate  124  includes an upper doped region  126  and a lower doped region  125 , a PN junction  127  is formed between the upper doped region  126  and the lower doped region  125 , and the upper doped region  126  is formed through the diffusion of the second conductive impurity in the second surface doped region A 2  and the second heavily doped semiconductor structure  126 ″. Accordingly, the upper doped region  126  has two lateral side portions  126   a , a surface portion A 21 ′, and a central portion  126   b . The central portion  126   b  is below the surface portion A 21 ′, and the surface portion A 21 ′ and the central portion  126   b  are located between the two lateral side portions  126   a . Since the second conductive impurities diffuse from the second doped region A 2  and the second heavily doped semiconductor structure  126 ″ toward the first heavily doped semiconductor structure  125 ″ during the thermal diffusion process, the concentrations of the second conductive impurities at the lateral side portions  126   a  and at the surface portion A 21 ′ are higher than that at the central portion  126   b  of the upper doped region  126 . 
     It is worth noting that the heating temperature and the heating time should be controlled during the thermal diffusion process to prevent the second conductive impurity from diffusing to the lower part of the first heavily doped semiconductor structure  125 ″, which leads to the PN junction  127  being unable to be formed in the gate  124  and affects the electrical characteristics of the trench power semiconductor device  1 . In one embodiment, the second conductive impurity is diffused through the rapid thermal diffusion process. 
     That is, the lower part of the first heavily doped semiconductor structure  125 ″ forms the aforementioned lower doped region  125 . Accordingly, after performing the thermal diffusion process, the source region  113  formed in the body region  111 , and the upper doped region  126  and lower doped region  125  of the gate  124  formed in the trench  112 , can be obtained simultaneously. 
     Though the first surface doped region A 1  and the second surface doped region A 2  have approximately the same depths before performing the thermal diffusion process, the diffusing rate of the second conductive impurity in the first surface doped region A 1  is smaller than that of the second conductive impurity in the second surface doped region A 2  during the thermal diffusion process. Therefore, the position of the PN junction  127  formed between the upper doped region  126  and the lower doped region  125  is lower than the level of the lowest point of the body region  111 . Moreover, in one embodiment, the position of the PN junction  127  is lower than the top of the laminated layer  121 . 
     Referring to  FIGS. 2J and 3 ,  FIG. 3  shows the local sectional view of the trench power semiconductor device according to an exemplary embodiment of the present disclosure. 
     The trench power semiconductor device  1  includes the substrate  10 , the epitaxial layer  11  and the gate structure  12 . The gate structure  12  is disposed in the trench  112  of the epitaxial layer  11 , and includes the gate insulating layer  120 , the laminated layer  121  and the gate  124 . In addition, the gate  124  is separated from the laminated layer  121  and the epitaxial layer  11  by the gate insulating layer  120 . 
     As mentioned above, the laminated layer  121  covers the gate insulating layer  120  corresponding to the lower part of the trench  112 , and includes the first dielectric layer  122  and the second dielectric layer  123 . Since the first dielectric layer  122  and the second dielectric layer  123  are formed by etching the first initial dielectric layer  122 ′ and the second initial dielectric layer  123 ′, respectively, the first dielectric layer  122  and the second dielectric layer  123  are also provided with a high etch selectivity therebetween. In one embodiment, the materials of which the first dielectric layer  122  is composed and the second dielectric layer  123  is composed can be respectively silicon nitride and silicon oxide. 
     The gate  124  includes the lower doped region  125  surrounded by the laminated layer  121 , and the upper doped region  126  on the laminated layer  121  and the lower doped region  125 , and the PN junction  127  is formed between the lower doped region  125  and the upper doped region  126 . Since the upper doped region  126  is formed through the diffusion of the second conductive impurity in the second surface doped region A 2  and the second heavily doped semiconductor structure  126 ″, the second conductive impurity concentration in the upper doped region  126  decreases along the direction from the peripheral portion (that includes the two lateral side portions  126   a  and the surface portion A 21 ′) of the upper doped region  126  to the central portion thereof. 
     Moreover, the trench power semiconductor device  1  has the body region  111  and the source region  113 . The body region  111  is disposed in the epitaxial layer  11 , and is adjacent to the upper part of the gate structure  12 ; the source region  113  is disposed on the body region  111 , and is adjacent to the upper part of the gate structure  12 . The level of the bottommost edge of the body region  111  is higher than the top of the laminated layer  121 . In other words, the top of the laminated layer  121  is beneath the bottommost edge of the body region  111 . 
     In accordance with the embodiment of the present disclosure, the gate structure  12  may extend from the surface of the epitaxial layer  11  into the drift region  110  because the trench  112  is a deep trench. Therefore, the aforementioned deep trench structure helps increase the breakdown voltage of the trench power semiconductor device  1 , while increasing the parasitic capacitance (Cp) between the gate and drain. 
     As shown in  FIG. 3 , the parasitic capacitance (Cp) between the gate  124  and the drain is caused by connecting the first capacitance (C 1 ), the second capacitance (C 2 ) and the third capacitance (C 3 ) in parallel, the value of the parasitic capacitance (Cp) is equivalent to a sum of the values of the first capacitor C 1 , the second capacitor (C 2 ) and the third capacitor (C 3 ), i.e., Cp=C 1 +C 2 +C 3 . 
     As mentioned previously, the switching speed of the trench power semiconductor device  1  may be attenuated due to an excessive parasitic capacitance (Cp). Accordingly, the PN junction  127  is formed in the gate  124  in the embodiment of the present disclosure. Since the junction capacitance (Cj) of the PN junction  127  is generated under reverse bias, and the junction capacitance (Cj) is in series with the parasitic capacitance (Cp), the effective capacitance (Cgd) of gate-to-drain, parasitic capacitance (Cp) and the junction capacitance (Cj) is equivalent to the following relation: Cgd=(Cp*Cj)/(Cp+Cj). Since the value of the effective capacitance (Cgd) of gate-to-drain is smaller than that of the parasitic capacitance (Cp), the switching loss of the trench power semiconductor device  1  can be reduced. 
     In addition, in order to generate the junction capacitance (Cj) at the PN junction  127  of the gate  124  when the trench power semiconductor device  1  is in the conducting (ON) state, the conductive type of the impurities in the upper doped region  126  is the same as that of the impurities in the source region  113 , whereas different from that of the impurities in the body region  111 . Taking the N-type trench power MOSFET as an example, both of the source region  113  and the upper doped region  126  are doped with N-type conductive impurities, whereas both of the body region  111  and the lower portion  125  are doped with P-type conductive impurities. 
     When a positive bias is applied to the upper doped region  126  of the gate  124 , the electrons in the body region  111  are accumulated at the side walls of the trench  112  and form a channel between the source and the drain so that the trench power semiconductor device  1  is at the conducting (ON) state. 
     However, a depletion region caused by reverse bias at the PN junction  127  of the gate  124  decreases the effective capacitance (Cgd) of gate-to-drain. On the contrary, taking the P-type trench power MOSFET for example, both of the source region  113  and the upper doped region  126  are doped with P-type conductive impurities, whereas both of the body region  111  and the lower doped portion  125  are doped with N-type conductive impurities. 
     In summary, in the trench power semiconductor device and the manufacturing method thereof in accordance with the present disclosure, a PN junction is formed in the gate. Since a junction capacitance (Cj) of the PN junction is generated under reverse bias, and the junction capacitance is in series with the parasitic capacitance (Cp) between the gate and the drain, the effective capacitance (Cgd) of gate-to-drain can be reduced. 
     On the other hand, in the manufacturing method of the trench power semiconductor device, the body thermal diffusion process of the body region is performed before the step of the formation of the initial gate structure. Then, structures in the trench are doped during performing of the source doping process. Afterwards, the thermal diffusion process is performed, so as to simultaneously form the source region and the gate with a PN junction. Therefore, the diffusion of the conductive impurities in the upper doped region and the lower doped region of the gate, which causes the lack of the PN junction in the gate and poor characteristics of devices due to repeated thermal diffusion processes, can be prevented. 
     The descriptions illustrated supra set forth simply the preferred embodiments of the present invention; however, the characteristics of the present invention are by no means restricted thereto. All changes, alterations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the present invention delineated by the following claims. 
     The abovementioned descriptions represent merely the exemplary embodiment of the present disclosure, without any intention to limit the scope of the present disclosure thereto. Various equivalent changes, alterations or modifications based on the claims of present disclosure are all consequently viewed as being embraced by the scope of the present disclosure.