Patent Publication Number: US-11650932-B2

Title: Integrated non-volatile memory assembly with address translation

Description:
This application claims the benefit of U.S. Provisional Patent Application No. 63/105,354, “INTEGRATED NON-VOLATILE MEMORY ASSEMBLY WITH ADDRESS TRANSLATION,” filed on Oct. 25, 2020, which is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). One example of non-volatile memory is flash memory (e.g., NAND-type and NOR-type flash memory). 
     Users of memory systems that include non-volatile memory can write data to the non-volatile memory and later read that data back. For example, a digital camera may take a photograph and store the photograph in non-volatile memory. Later, a user of the digital camera may view the photograph by having the digital camera read the photograph from the non-volatile memory. Performance of memory systems is important to users. That is, users typically do not want to wait for the memory system to write to or read from the non-volatile memory. For example, a user of a digital camera with non-volatile memory does not want to wait for a first photograph to be stored before taking additional photographs. Therefore, there is a desire for high performance memory systems that utilize non-volatile memory. 
     Many electronic apparatuses make use of embedded or connected memory systems. An electronic apparatus that includes an embedded memory system, or is connected to a memory system, is often referred to as a host. 
     In many storage systems, the non-volatile memory is addressed internally to the memory system using physical addresses associated with one or more memory die. However, the host will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the memory system is free to store the data as it wishes among the locations of the one or more memory die. To enable this system, the memory system&#39;s controller (referred to as the memory controller) typically performs translation between the logical addresses used by the host and the physical addresses used by the memory die (“address translation”). One example implementation is to maintain data structures that identify the current translation between logical addresses and physical addresses. One example of such a data structure is referred to as a L2P table. For purposes of this document, a L2P table is a data structure that identifies translation between logical addresses and physical addresses. The L2P table does not need to literally be a table, and many different forms of a data structure can function as and be referred to as a L2P table as long as they enable translation of a logical address to a physical address. For purposes of this document, the one or more data structures that enable translation of logical addresses to a physical addresses can be referred to as one L2P table or multiple L2P tables. For example, the data structure can be broken up into blocks or other units. 
     Typically, the memory controller is connected to a local volatile memory that stores all or a portion of the L2P tables. In some examples, the memory space of a memory system is so large that the local memory cannot hold all of the L2P tables as well as any other information (besides L2P tables) that the local memory is used to store. In such a case, the entire set of L2P tables are stored in the non-volatile memory and a subset of the L2P tables are cached in the local memory (referred to as L2P cache). The bigger the L2P cache, the higher performance of the memory system. However, the bigger cache requires bigger local memories, which increases the costs of a memory system. Additionally, some address spaces are so large that it is not practical (even if cost is not a consideration) to implement a local memory big enough to store all L2P tables. 
     Typically, when a host requests that a memory system perform a memory operation (e.g., write or read), before the memory system performs the operation the memory system first translates one or more logical addresses from the host to one or more physical addresses in the memory system. This process of address translation takes time, which slows down the performance of the memory operation. If, during the address translation, the L2P table needed to perform the address translation is not stored in the L2P cache (referred to as a cache miss), then additional time is needed to fetch the L2P table from the non-volatile memory and transfer that L2P table to the memory controller so that the memory controller can perform the address translation. Thus, the performance of the memory operation is reduced when there is a cache miss due to the time used to fetch the L2P table from the non-volatile memory and transfer that L2P table to the memory controller. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram of one embodiment of a memory system connected to a host. 
         FIG.  2    is a block diagram of one embodiment of a Front End Processor circuit. 
         FIG.  3    is a block diagram of one embodiment of a Back End Processor circuit. 
         FIG.  4    is a functional block diagram of an integrated memory assembly. 
         FIG.  5    is a block diagram of one embodiment of a read/write circuits and ECC circuit of an integrated memory assembly. 
         FIG.  6 A  depicts an example of a sparse parity check matrix H. 
         FIG.  6 B  depicts a sparse bipartite graph which corresponds to the sparse parity check matrix of  FIG.  6 A . 
         FIG.  7    is a block diagram depicting one embodiment of a sense block. 
         FIG.  8    is a block diagram of one embodiment of an integrated memory assembly. 
         FIG.  9    is a block diagram of one embodiment of an integrated memory assembly in which a control die controls two memory dies. 
         FIGS.  10 A and  10 B  are top views of semiconductor wafers. 
         FIG.  10 C  depicts an example pattern of bond pads on a planar surface of a semiconductor die. 
         FIG.  11    depicts a side view of an embodiment of an integrated memory assembly stacked on a substrate. 
         FIG.  12    depicts a side view of an embodiment of an integrated memory assembly stacked on a substrate. 
         FIG.  13    is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array. 
         FIG.  14    depicts one embodiment of an integrated memory assembly. 
         FIG.  15    depicts one embodiment of an integrated memory assembly in which one control die controls two memory die. 
         FIG.  16    is a flowchart describing one embodiment of a process for programming non-volatile memory cells organized into a memory array on a memory die. 
         FIG.  17 A  illustrates example threshold voltage distributions for a population of non-volatile memory cells when each memory cell stores one bit of data. 
         FIG.  17 B  illustrates example threshold voltage distributions for a population of non-volatile memory cells when each memory cell stores three bits of data. 
         FIG.  18    illustrates example threshold voltage distributions for a population of non-volatile memory cells when each memory cell stores four bits of data. 
         FIG.  19    is a flowchart describing one embodiment of a process for programming a storage system. 
         FIG.  20    is a flowchart describing one embodiment of a process for reading data from a storage system. 
         FIG.  21    is a flow chart describing one embodiment of a process for performing a memory operation. 
         FIG.  22    is a block diagram depicting an example of components that can be used to perform a memory operation. 
         FIGS.  23 A,  23 B,  23 C and  23 D  together form a flow chart describing one embodiment of a process for performing a memory operation. 
         FIG.  24    is a flow chart describing one embodiment of a process for performing a memory operation. 
         FIG.  25    is a flow chart describing one embodiment of a process for performing a read process with address translation. 
         FIG.  26    is a flow chart describing one embodiment of a process for a control dies to perform address translation. 
         FIG.  27    is a block diagram describing one example embodiment for interleaving logical addresses among different memory die. 
         FIG.  28    is a block diagram describing the placement of address translation information (and/or other metadata) within a namespace. 
     
    
    
     DETAILED DESCRIPTION 
     Performance of a memory system is increased by reducing the amount of time used to perform address translation. For example in prior systems, if the L2P table needed to perform the address translation is not stored in the L2P cache in the local memory (referred to as a cache miss), then additional time is needed to fetch the L2P table from the non-volatile memory and transfer that L2P table to the memory controller so that the memory controller can perform the address translation. In the technology introduced herein, the additional time needed to transfer the L2P table to the memory controller after a cache miss is avoided or reduced by performing the address translation at the memory die such that the L2P table fetched after a cache miss is not transferred to the memory controller as part of the address translation process. 
     The memory is implemented using multiple dies, including pairs of memory dies and control dies. The memory die includes the memory array. The control die includes one or more control circuits (e.g., including one or more processors) that can operate (e.g., read, write, erase) the memory die. If the control die is configured to perform address translation, then time and power are saved by not transferring an L2P table from the memory to the memory controller. 
     In some embodiments, the control die and the memory die are fabricated on different semiconductor wafers, which permits use of different semiconductor fabrication processes on the different wafers. For example, semiconductor fabrication processes may involve high temperature anneals. Such high temperature anneals may be needed for proper formation of some circuit elements, but could be damaging to other circuit elements such as memory cells. It can be challenging to form complex circuitry such as decoders on the memory die due to limitations of semiconductor fabrication processes. Also, the fabrication process that is used to form memory cells on the memory die may place constraints on the size of the transistors that are formed on the memory die. In some embodiments, the control circuits on the control die have transistors that are a different size (e.g., smaller) than memory cell transistors on the memory die. The different (e.g., smaller) size of the transistors on the control die may improve performance of the control circuits on the control die. For example, smaller transistors may use less power than larger transistors. Also, using smaller transistors allows one embodiment of a control die to have more transistors for control circuits on the control die. 
     One embodiment of the present technology for performing address translation includes an apparatus that comprises a first semiconductor die (e.g., memory die) and a second semiconductor die (e.g., a control die). The first semiconductor die includes non-volatile memory cells and a first plurality of pathways. The second semiconductor die includes one or more control circuits for operating the first semiconductor die, an interface to a memory controller, and a second plurality of pathways directly connected to the first plurality of pathways. The second semiconductor die is directly connected to the first semiconductor die; for example, the second semiconductor die is bonded to the first semiconductor die. The one or more control circuits are configured to transfer signals through pathway pairs of the first plurality of pathways and the second plurality of pathways. The one or more control circuits are configured to receive a request from the memory controller (via the interface to the memory controller) to perform a memory operation on the non-volatile memory cells of the first semiconductor die, receive an indication of a logical address from the memory controller (the logical address is for the memory operation), perform a logical address to physical address translation operation on the second semiconductor die using the received indication of the logical address resulting in a physical address for the non-volatile memory cells of the first semiconductor die, and perform the memory operation on the non-volatile memory cells using the physical address and the pathway pairs. The proposed technology for performing address translation at the control die can also be used to perform other operations on other metadata at the control die. 
       FIGS.  1 - 5    describe one example of a memory system for implementing the technology disclosed herein for efficiently performing address translation or other metadata operations.  FIG.  1    is a block diagram of one embodiment of a memory system  100  connected to a host  120 . Memory system (i.e., non-volatile memory system)  100  can implement the technology disclosed herein. Many different types of memory systems can be used with the technology disclosed herein. One example memory system is a solid state drive (“SSD”); however, other types of memory systems can also be used including removable memory cards and USB memory devices. Memory system  100  comprises a memory controller  102 , integrated memory assembly  104  for storing data, and local memory (e.g., DRAM/ReRAM)  106 . Memory controller  102  comprises a Front End Processor Circuit (FEP)  110  and one or more Back End Processor Circuits (BEP)  112 . In one embodiment FEP  110  circuit is implemented on an ASIC. In one embodiment, each BEP circuit  112  is implemented on a separate ASIC. Ion one embodiment, the ASICs for each of the BEP circuits  112  and the FEP circuit  110  are implemented on the same semiconductor such that memory controller  102  is manufactured as a System on a Chip (“SoC”). FEP  110  and BEP  112  both include their own processors. In one embodiment, FEP  110  and BEP  112  work as a master slave configuration where the FEP  110  is the master and each BEP  112  is a slave. For example, FEP circuit  110  implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logical address to physical address translation, communication with the host, management of DRAM (local volatile memory) and management of the overall operation of the SSD (or other non-volatile storage system). The BEP circuit  112  manages memory operations in the integrated memory assemblies/die at the request of FEP circuit  110 . In some embodiments, an integrated memory assembly is referred to as a memory package. For example, the BEP circuit  112  can carry out the read, erase and programming processes. Additionally, the BEP circuit  112  can perform buffer management, set specific voltage levels required by the FEP circuit  110 , perform error correction (ECC), control the Toggle Mode interfaces to the memory packages, etc. In one embodiment, each BEP circuit  112  is responsible for its own set of memory packages. Controller  102  is one example of a control circuit. 
     In one embodiment, there are a plurality of integrated memory assemblies  104 . In an embodiment, each integrated memory assembly  104  includes one or more memory die and one or more control die. Each memory die may include one or more memory structures. A control die may control operations on a memory die. For example, a control die may control and perform read, write, and erase operations on a memory die. In one embodiment, memory controller  102  communicates with a control die in order to instruct the control die to perform read, write, or erase operations on one or more non-volatile memory die or one or more memory structures. In one embodiment, each memory die in the integrated memory assembly  104  utilizes NAND flash memory (including two dimensional NAND flash memory and/or three dimensional NAND flash memory). In other embodiments, the integrated memory assembly  104  can include other types of memory; for example, PCM memory and MRAM. 
     Memory controller  102  communicates with host  120  by way of an interface  130  that implements NVM Express (NVMe) over PCI Express (PCIe). For working with memory system  100 , host  120  includes a host processor  122 , host memory  124 , and a PCIe interface  126 . Host memory  124  is the host&#39;s physical memory, and can be DRAM, SRAM, non-volatile memory or another type of storage. Host  120  is external to and separate from memory system  100 . In one embodiment, memory system  100  is embedded in host  120 . 
       FIG.  2    is a block diagram of one embodiment of FEP circuit  110 .  FIG.  2    shows a PCIe interface  150  to communicate with host  120  and a host processor  152  in communication with that PCIe interface. The host processor  152  can be any type of processor known in the art that is suitable for the implementation. Host processor  152  is in communication with a network-on-chip (NOC)  154 . A NOC is a communication subsystem on an integrated circuit, typically between cores in a SoC. NOC&#39;s can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of SoCs and the power efficiency of complex SoCs compared to other designs. The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Connected to and in communication with NOC  154  is the memory processor  156 , SRAM  160  and a DRAM controller  162 . The DRAM controller  162  is used to operate and communicate with the DRAM (e.g., DRAM  106 ). SRAM  160  is local RAM memory used by memory processor  156 . Memory processor  156  is used to run the FEP circuit and perform the various memory operations. Also in communication with the NOC are two PCIe Interfaces  164  and  166 . In the embodiment of  FIG.  2   , memory controller  102  includes two BEP circuits  112 ; therefore, there are two PCIe Interfaces  164 / 166 . Each PCIe Interface communicates with one of the BEP circuits  112 . In other embodiments, there can be more or less than two BEP circuits  112 ; therefore, there can be more than two PCIe Interfaces. 
       FIG.  3    is a block diagram of one embodiment of the BEP circuit  112 .  FIG.  3    shows a PCIe Interface  200  for communicating with the FEP circuit  110  (e.g., communicating with one of PCIe Interfaces  164  and  166  of  FIG.  1 B ). PCIe Interface  200  is in communication with two NOCs  202  and  204 . In one embodiment the two NOCs can be combined to one large NOC. Each NOC ( 202 / 204 ) is connected to SRAM ( 230 / 260 ), a buffer ( 232 / 262 ), processor ( 220 / 250 ), and a data path controller ( 222 / 252 ) via an XOR engine ( 224 / 254 ), an ECC engine ( 226 / 256 ). The ECC engines  226 / 256  are used to perform error correction, as known in the art. Herein, the ECC engines  226 / 256  may be referred to as controller ECC engines. 
     The ECC engines  226 / 256  may encode data bytes received from the host, and may decode and error correct the data bytes read from the control die  304 . In some embodiments, the ECC engines  226 / 256  calculate parity bits for each unit of data (e.g., page) that is being stored at one time. The parity bits (also referred to as an error correction code) may be stored with the unit of data (e.g., page). The combination of the unit of data and its associated parity bits are referred to as a codeword. In one embodiment, the parity bits are stored remotely from the unit of data (e.g., page). 
     In some embodiments, memory controller  102  does not send the entire codeword to an integrated memory assembly  104 . Instead, memory controller  102  sends only the data bits, with a control die on the integrated memory assembly  104  generating the parity bits. Optionally, memory controller  102  could send the entire codeword. In some cases, a control die of the integrated memory assembly  104  does not send an entire codeword to memory controller  102 . Instead, the control die decodes the codeword, and sends back only the data bits to memory controller  102 . However, in some cases, the control die may be unable to successfully decode a codeword. In this case, the control die may send the entire codeword to memory controller  102 , which uses ECC engines  226 / 256  to decode the codeword. 
     In some embodiments, the ECC engines have different modes, such as ECC mode A  226   a / 256   a  and ECC mode B  226   b / 256   b . The two modes may differ in their resolution. In general, a higher resolution decoder is able to correct a higher number of bit errors. In one embodiment, the resolution refers to the number of bits in messages that are passed in an iterative message passing decoder. For example, the messages in ECC Mode B  226   b / 256   b  may have 6 bits, whereas the messages in ECC Mode A  226   a / 256   a  may have 3 bits. In some embodiments, using fewer bits in the messages (corresponding to a lower resolution) results in faster decoding. Using fewer bits in the messages may also consume less power. Further details of decoders having different resolutions are described in U.S. Pat. No. 10,218,384, entitled “ECC Decoder with Multiple Decode Modes,” which is incorporated herein by reference. 
     The XOR engines  224 / 254  may be used to form redundancy information that is based on information from each codeword in a set of codewords. The redundancy information may be stored in one of the memory dies. This redundancy information may be used to recover the data bits for each of the codewords in the set. As one example, each codeword could be 4 kilobytes, each codeword may be for one page of data, and redundancy information may be formed from a bitwise XOR of each of the codewords. In one embodiment, the bitwise XOR has the same number of bits of each codeword. 
     Data path controller  222  is connected to a memory interface  228  for communicating by way of four channels with integrated memory assemblies. Thus, the top NOC  202  is associated with memory interface  228  for four channels for communicating with integrated memory assemblies and the bottom NOC  204  is associated with memory interface  258  for four additional channels for communicating with integrated memory assemblies. In one embodiment, each memory interface  228 / 258  includes four Toggle Mode interfaces (TM Interface), four buffers and four schedulers. There is one scheduler, buffer and TM Interface for each of the channels. The processor can be any standard processor known in the art. The data path controllers  222 / 252  can be a processor, FPGA, microprocessor or other type of controller. The XOR engines  224 / 254  and ECC engines  226 / 256  are dedicated hardware circuits, known as hardware accelerators. In other embodiments, the XOR engines  224 / 254  and ECC engines  226 / 256  can be implemented in software. The scheduler, buffer, and TM Interfaces are hardware circuits. In other embodiments, the memory interface (an electrical circuit for communicating with memory dies) can be a different structure than depicted in  FIG.  3   . Additionally, memory controllers with structures different than  FIGS.  2  and  3    can also be used with the technology described herein. 
       FIG.  4    is a functional block diagram of one embodiment of an integrated memory assembly  104 . In one embodiment, the integrated memory assembly  104  includes two semiconductor die (or more succinctly, “die”): memory die  302  and control die  304 . Memory die  302  includes include memory structure  326 . Memory structure  326  includes non-volatile memory cells. Control die  304  includes control circuitry  310 . In some embodiments, the memory die  302  and the control die  304  are directly bonded together, as will be described in more detail below. For purposes of this document, the phrase directly bonded refers to the memory die being bonded to the control die with no other die between the memory die and the control die. 
     Control circuitry  310  comprises a set of electrical circuits that perform memory operations (e.g., write, read, erase and others) on memory structure  326 . Control circuitry  310  includes state machine  312 , an on-chip address decoder  314 , a power control circuit  316 , storage region  318 , read/write circuits  328 , ECC engine  330 , memory controller interface  332 , memory die interface  340 , and address translation circuit  334 . In another embodiment, a portion of the read/write circuits  328  are located on control die  304  and a portion of the read/write circuits  328  are located on memory die  302 . For example, the read/write circuits  328  may contain sense amplifiers. In one embodiment, the sense amplifiers (for reading data from the memory die) are located on the control die  304 . In one embodiment, the sense amplifiers are located on the memory die  302 . 
     Herein, the term, “memory die,” “memory semiconductor die,” or the like, means a semiconductor die that contains non-volatile memory cells for storage of data. Herein, the term, “control die,” “control semiconductor die,” or the like, means a semiconductor die that contains control circuitry for performing memory operations on non-volatile memory cells on a memory die. Typically, numerous semiconductor die are formed from a single semiconductor (e.g., silicon) wafer. 
     State machine  312  is an electrical circuit that controls the operations performed by control die  304 . In some embodiments, state machine  312  is implemented by or replaced by a microprocessor, microcontroller and/or RISC processor. 
     Storage region  318  can be volatile memory (e.g., DRAM or SRAM) used to store software for programming a processor (e.g., the RISC processor used to implement or replace state machine  312 ) and for storing data (e.g., data for the decoding process and encoding process and operational parameters). In one embodiment, storage region  312  is implemented with SRAM or DRAM. 
     The on-chip address decoder  314  provides an address interface between addresses used by host  120  or memory controller  102  to the hardware address used by row decoders and column decoders (not expressly depicted in  FIG.  4   ). Power control circuit  316  controls the power and voltages supplied to the word lines, bit lines, and select lines during memory operations. The power control circuit  316  includes voltage circuitry, in one embodiment. Power control circuit  316  may include charge pumps or other voltage sources for creating voltages. The power control circuit  316  executes under control of the state machine  312 . 
     The read/write circuits  328  includes sense blocks (which may contain sense amplifies (SA), in some embodiments. The sense amplifies include bit line drivers, in some embodiments. The read/write circuits  328  executes under control of the state machine  312 , in one embodiment. Each memory structure  326  is addressable by word lines by way of a row decoder (not depicted in  FIG.  3 A ) and by bit lines by way of a column decoder (not depicted in  FIG.  3 A ), in some embodiments. 
     The error correction code (ECC) engine  330  is a circuit configured to decode and error correct codewords. Herein, ECC engine  330  may be referred to as an on-die ECC engine. In one embodiment, the on-die ECC engine  330  is configured to encode data bits from memory controller  102  into codewords that contain the data bits and parity bits. The control circuitry stores the codewords in the memory structure  326 . In one embodiment, the on-die ECC engine  330  is also configured to decode the codewords which are read from the memory structure  326 . In some embodiments, if the on-die ECC engine  330  is successful at decoding a codeword, then the control die  304  only sends back the data bits to the memory controller  102 . In some embodiments, if the on-die ECC engine  330  is not successful at decoding a codeword, then the memory controller ECC engine  226 / 256  may be used to decode the codeword. 
     In some embodiments, first the control die  304  attempts to decode a codeword using ECC engine  330 . If decoding fails, the memory controller  102  may attempt to decode that codeword. In some embodiments, the memory controller  102  has multiple ECC modes. For example, ECC mode A  226 A (see  FIG.  3   ) may be used to attempt to decode a codeword that the control die  304  could not decode. If ECC Mode A  226   a  fails to decode the codeword, then ECC mode B  226   b  may be used by the memory controller  102 . For example, the on-die ECC engine  330  may use a hard bit decoder to attempt to decode a codeword. Under typical conditions, hard bit decoding may be successful most of the time. In the event that the on-die ECC engine  330  fails to successfully decode the codeword, the codeword may be passed to memory controller  102 . In one embodiment, memory controller  102  first attempts to decode using a soft bit decoder at one level of resolution. This first attempt may be made by ECC Mode A  226   a . If the first attempt by memory controller  102  fails, then the memory controller may use a soft bit decoder at higher level of resolution. This second attempt may be made by ECC Mode B  226   b . Note that the aforementioned hard bit decoder may use less power than the soft bit decoders. Hence, most of the time the decoding may be achieved using a low power decoder on the control die  304 . None of the on-die ECC engine  330 , ECC Mode A  226 A, nor ECC Mode B  226   b  are limited to the foregoing examples. 
     In one embodiment, all or a subset of the circuits of control circuitry  310  can be considered one or more control circuits. The one or more control circuits can include hardware only (e.g., electrical circuits) or a combination of hardware and software (including firmware). For example, a controller programmed by firmware is one example of a control circuit. One or more control circuits can include a processor, PGA (Programmable Gate Array, FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), microcontroller, integrated circuit or other type of circuit. 
     Memory interface  340  is an electrical interface between control die  304  and memory doe  302 , employing pathways  352 . Pathways  352  are pathways between one or more components in the control circuitry  310  and the memory structure on memory die  302 . A portion of each pathway resides in memory die  302  and a portion of each pathway resides in control die  304 . The term pathway may be used for a portion of pathways  352  that is entirely within one of the die. Thus, it may be stated that the memory die  302  has a first plurality of pathways and that the control die  304  has a second plurality of pathways such that the first plurality of pathways are directly connected to the second plurality of pathways (e.g., no intervening pathways). In one embodiment, the control die  304  and the memory die  302  are configured to transfer signals through pathway pairs of the first plurality of pathways and the second plurality of pathways. In some embodiments, the memory die  302  and the control die  304  are bonded to each other, or otherwise attached to each other, to facilitate signal transfer through the pathway pairs. 
     A pathway may be used to provide or receive a signal (e.g., voltage, current). A pathway includes an electrically conductive path. A pathway may include one or more of, but is not limited to, a bond pad, metal interconnect, via, transistor, electrically conducting material and other material that may transfer or carry an electrical signal. In one embodiment, pathways  352  allow the control circuitry  310  to provide voltages to word lines, select lines, and bit lines on memory die  302 . Pathways  352  may be used to receive signals from, for example, bit lines. In one embodiment, there are about 100,000 pathways  352 . However, there could be more or fewer than 100,000 pathways. Having such a large number of pathways  352  allows a very large amount of data, or other signals, to be passed in parallel. 
     Memory controller interface  332  is an electrical interface for communicating with memory controller  102 . For example, memory controller interface  332  may implement a Toggle Mode Interface that connects to the Toggle Mode interfaces of memory interface  228 / 258  for memory controller  102 . In one embodiment, memory controller interface  332  includes a set of input and/or output (I/O) pins that connect to communication channel  336  (also refers to herein as a data bus). In one embodiment, communication channel  336  connects to the memory controller  102  as part of the Toggle Mode Interface. In one embodiment, a communication channel  336  of one integrated memory assembly  104  connects to another integrated memory assembly  104 . 
     Memory interface  340  is significantly wider than memory controller interface  332  because memory interface  340  has significantly more signals than memory controller interface  332 . Therefore, more data can be sent in parallel for memory interface  340  as compared to memory controller interface  332 . In some examples, memory interface  340  is 4×, 10×, 20×, or 50× wider than memory controller interface  332 . 
     Communication channel  336  is depicted as being connected to integrated memory assembly  104  for generality. Communication channel  336  may connect to either or both of die  302  and/or  304 . In one embodiment, communication channel  336  connects memory controller  102  directly to control die  304 . In one embodiment, communication channel  336  connects memory controller  102  directly to memory die  302 . If communication channel  336  connects memory controller  102  directly to memory die  302 , then pathway  352  may be used to allow communication between memory controller  102  and control circuitry  310 . 
     Address translation circuit  334  is used to perform address translation (e.g., logical address to physical address). In other embodiments, the address translation function can be implemented using software running on the state machine or other processor. More details of the operation and function of address translation circuit  334  are provided below. 
     In one embodiment, memory structure  326  comprises a monolithic three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material. 
     In another embodiment, memory structure  326  comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used. 
     The exact type of memory array architecture or memory cell included in memory structure  326  is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure  326 . No particular non-volatile memory technology is required for purposes of the new claimed embodiments disclosed herein. Other examples of suitable technologies for memory cells of the memory structure  326  include phase change memory (“PCM”), Magnetoresistive Random-Access Memory (“MRAM”), and the like. Examples of suitable technologies for memory cell architectures of the memory structure  326  include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like. 
     A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art. 
     Although  FIG.  4    depicts one control die  304  and one memory die  302  in an integrated memory assembly  104 , there may be more than one control die  304  and more than one memory die  302  in an integrated memory assembly  104 . 
       FIG.  5    is a block diagram of one embodiment of the read/write circuits  328  and ECC engine  330  of the control die  304 . The read/write circuits  328  have sense amplifiers  350  and latches  360 . The latches  360  may include data latches  360   a  and parity latches  360   b . In one embodiment, the data latches  360   a  store data bits of the codeword and the parity latches store parity bits of the codeword. It is not required that there be specific latches for data bits and for parity bits.  FIG.  5    depicts four sets of data latches  360 ( 1 ),  360 ( 2 ),  360 ( 3 ),  360 ( 4 ). Each set may be used to store a codeword for a different page. In an embodiment in which four bits are stored per memory cell, four pages are stored in a set of memory cells. The four pages may be referred to as a lower page (LP), lower-middle page (LMP), upper-middle page (UMP), and an upper page (UP). In an embodiment in which three bits are stored per memory cell, three pages are stored in a set of memory cells and the four pages may be referred to as a lower page (LP), middle page (MP), and an upper page (UP). In another embodiment, the sense amplifiers  350  are on the memory die  302 , but the latches  360  remain on the control die  304 . 
     The on-die ECC engine  330  is able to encode data bits received from memory controller  102 . In one embodiment, the on-die ECC engine  330  forms codewords that each contain data bits and parity bits. In one embodiment, memory controller  102  provides the codewords to the control die  304 . Control circuitry  310  stores the codewords into non-volatile memory cells in the memory structure  326 . Upon a request from memory controller  102  to read data, control circuitry  310  reads codewords from memory structure  326 . The on-die ECC engine  330  is also able to decode and error correct the codewords read from the memory structure  326 . In some embodiments, the on-die ECC engine  330  calculates parity bits for each unit of data (e.g., page) that is being stored. The parity bits (also referred to as an error correction code or error correction information) may be stored with the unit of data (e.g., page). The combination of the unit of data and its associated parity bits are referred to as a codeword. In one embodiment, the parity bits are stored remotely from the unit of data (e.g., page). 
     In an embodiment, upon successfully decoding a codeword, the control die  304  sends only the data bits, but not the parity bits, to memory controller  102 . Therefore, bandwidth over communication lines between memory controller  102  and the integrated memory assembly  104  is saved. Also, substantial power may be saved. For example, the interface between the control die and the controller could be a high speed interface. 
     The on die ECC engine  330  includes syndrome calculation logic  370 , an encoder  380 , and a decoder  390 . The encoder  380  is configured to encode data using an ECC scheme, such as a low-density parity check (LDPC) encoder, a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a Turbo Code encoder, an encoder configured to encode one or more other ECC encoding schemes, or any combination thereof. The encoder  380  may form a codeword, which contains data bits  382  and parity bits  384 . The data bits may be provided by memory controller  102 . 
     Based on the bits in the latches  360 , the sense amplifiers  350  may control bit line voltages in the memory structure  326  when the non-volatile memory cells are being programmed. In this manner, the codewords may be programmed into non-volatile memory cells in the memory structure  326 . It will be appreciated that other voltages may also be applied to the memory structure  326 , such applying a program voltage to memory cells that are selected for programming by a voltage generator on control die  304  applying the program voltage and boosting voltages to various word lines of memory structure  326 . 
     Decoder  390  is configured to decode the codewords that were stored in the memory die  302 . In one embodiment, sense amplifiers  350  sense bit lines in the memory structure  326  in order to read a codeword. The sense amplifiers  350  may store the read codeword into latches  360 . The decoder  390  is able to detect and correct errors in the codeword. In one embodiment, the decoder  390  is a relatively low power decoder, as compared to a decoder on memory controller  102 . In one embodiment, the decoder on memory controller  102  is able to correct more bit errors in the codeword than can typically be corrected by decoder  390 . Thus, decoder  390  may provide a power versus error correction capability tradeoff. For example, decoder  390  may be very efficient with respect to power consumption, but at the expense of possibly not being able to correct a high number of errors in a codeword. 
     In one embodiment, the decoder  390  implements a hard bit decoder. In another embodiment, the decoder  390  implements a soft bit decoder. Alternatively, decoder  390  may implement both a hard bit decoder and a soft bit decoder. For example, the control die  304  may first attempt to decode a codeword with the hard bit decoder. If that fails, then the control die  304  may attempt to decode using the soft bit decoder. 
     In some embodiments, the decoder  390  is based on a sparse bipartite graph having bit (or variable) nodes and check nodes. The decoder  390  may pass messages between the bit nodes and the check nodes. Passing a message between a bit node and a check node is accomplished by performing a message passing computation. The message passing computation may be based on belief propagation. 
     Syndrome calculation logic  370  (e.g., an electrical circuit and/or software) is able to determine a syndrome weight for codewords. The syndrome weight refers to the number of parity check equations that are unsatisfied. The initial syndrome weight of a codeword may correlate with the bit error rate (BER) of that codeword. Thus, the control die  304  may estimate a BER for a codeword based on the initial syndrome weight. In one embodiment, the syndrome logic is implemented in hardware. The syndrome weight can be determined without fully decoding a codeword. Hence, the initial syndrome weight can be calculated in less time and with less power than for decoding a codeword. In some embodiments, the control die  304  makes management decisions based on the estimated BER. For example, the control die  304  may determine what technique should be used to decode a codeword, what read reference voltages should be used to read memory cells, etc. based on the estimated BER. 
     In one embodiment, on-die ECC engine  330  uses a sparse parity check matrix.  FIG.  6 A  depicts an example of a sparse parity check matrix H (which may also be represented as a sparse bipartite graph). The matrix includes M rows and K+M columns, which are in correspondence with K information bits and M parity bits in each codeword of length N=K+M. Further, the parity bits are defined such that M parity check equations are satisfied, where each row of the matrix represents a parity check equation. 
       FIG.  6 B  depicts a sparse bipartite graph  392  which corresponds to the sparse parity check matrix of  FIG.  6 A . Specifically, the code can be defined by a sparse bipartite graph G=(V,C,E) with a set V of N bit nodes  394  (N=13 in this example), a set C of M check nodes  396  (M=10 in this example) and a set E (E=38 in this example) of edges  398  connecting bit nodes  394  to check nodes  396 . The bit nodes correspond to the codeword bits and the check nodes correspond to parity-check constraints on the bits. A bit node  394  is connected by edges  398  to the check nodes  396  it participates in. 
     During decoding, one embodiment of the decoder  390  attempts to satisfy the parity checks. In this example, there are ten parity checks, as indicated by the check nodes cn1 through cn10. The first parity check at cn1 determines if v2⊕v4⊕v11⊕v13=0, where “⊕” denotes the exclusive-or (XOR) logical operation. This check is satisfied if there is an even number of “1” in bits corresponding to variable nodes v2, v4, v11 and v13. This check is denoted by the fact that arrows from variable nodes v2, v4, v11 and v13 are connected to check node cn1 in the bi-partite graph. The second parity check at cn2 determines if v1⊕v7⊕v12=0, the third parity check at cn3 determines if v3⊕v5⊕v6⊕v9⊕v10=0, the fourth parity check at cn4 determines if v2⊕v8⊕v11=0, the fifth parity check at cn5 determines if v4⊕v7⊕v12=0, the sixth parity check at cn6 determines if v1⊕v5⊕v6⊕v9=0, the seventh parity check at cn7 determines if v2⊕v8⊕v10⊕v13=0, the eighth parity check at cn8 determines if v4⊕v7⊕v11⊕v12=0, the ninth parity check at cn9 determines if v1⊕v3⊕v5⊕v13=0 and the tenth parity check at cn10 determines if v7⊕v8⊕v9⊕v10=0. 
     In one embodiment, the decoder  390  uses an iterative probabilistic decoding process involving iterative message passing decoding algorithms. These algorithms operate by exchanging messages between bit nodes and check nodes over the edges of the underlying bipartite graph representing the code. 
     The decoder  390  may be provided with initial estimates of the codeword bits (based on the content that is read from the memory structure  326 ). These initial estimates may be refined and improved by imposing the parity-check constraints that the bits should satisfy as a valid codeword. This may be done by exchanging information between the bit nodes representing the codeword bits and the check nodes representing parity-check constraints on the codeword bits, using the messages that are passed along the graph edges. 
       FIG.  7    is a block diagram depicting one embodiment of a sense block  450 . The sense block is part of the read/write circuits  328 . An individual sense block  450  is partitioned into one or more core portions, referred to as sense circuits or sense amplifiers  350 ( 1 )- 350 ( 4 ), and a common portion, referred to as a managing circuit  480 . In one embodiment, there will be a separate sense circuit for each bit line/NAND string and one common managing circuit  480  for a set of multiple, e.g., four or eight, sense circuits. Each of the sense circuits in a group communicates with the associated managing circuit by way of data bus  454 . Thus, there are one or more managing circuits which communicate with the sense circuits of a set of storage elements (memory cells). 
     The sense amplifier  350 ( 1 ), as an example, comprises sense circuitry  460  that performs sensing by determining whether a conduction current in a connected bit line is above or below a predetermined threshold level. The sensing can occur in a read or verify operation. The sense circuit also supplies a bit line voltage during the application of a program voltage in a program operation (e.g., write operation). 
     The sense circuitry  460  may include a Vbl selector  462 , a sense node  464 , a comparison circuit  466  and a trip latch  468 . During the application of a program voltage, the Vbl selector  462  can pass a program enable voltage (e.g., V_pgm_enable) or a program-inhibit voltage (e.g., Vbl_inh) to a bit line connected to a memory cell. The Vbl selector  462  can also be used during sensing operations. Herein, a “program enable voltage” is defined as a voltage applied to a memory cell that enables programming of the memory cell while a program voltage (e.g., Vpgm) is also applied to the memory cell. In certain embodiments, a program enable voltage is applied to a bit line coupled to the memory cell while a program voltage is applied to a control gate of the memory cell. Herein, a “program inhibit voltage” is defined as a voltage applied to a bit line coupled to a memory cell to inhibit programming of the memory cell while a program voltage (e.g., Vpgm) is also applied to the memory cell (e.g., applied to the control gate of the memory cell). Note that boosting voltages (e.g., Vpass) may be applied to unselected word lines along with the program inhibit voltage applied to the bit line. The bit lines are part of memory structure  326  on memory die  302 . 
     Program inhibit voltages are applied to bit lines coupled to memory cells that are not to be programmed and/or bit lines having memory cells that have reached their respective target threshold voltage through execution of a programming process. These may be referred to as “unselected bit lines.” Program inhibit voltages are not applied to bit lines (“selected bit lines”) having a memory cell to be programmed. When a program inhibit voltage is applied to an unselected bit line, the bit line is cut off from the NAND channel, in one embodiment. Hence, the program inhibit voltage is not passed to the NAND channel, in one embodiment. Boosting voltages are applied to unselected word lines to raise the potential of the NAND channel, which inhibits programming of a memory cell that receives the program voltage at its control gate. 
     A transistor  470  (e.g., an nMOS) can be configured as a pass gate to pass Vbl from the Vbl selector  462 , by setting the control gate voltage of the transistor sufficiently high, e.g., higher than the Vbl passed from the Vbl selector. For example, a selector  472  may pass a power supply voltage Vdd, e.g., 3-4 V to the control gate of the transistor  470 . 
     The sense amplifier  350 ( 1 ) is configured to control the timing of when the voltages are applied to the bit line. During sensing operations such as read and verify operations, the bit line voltage is set by the transistor  470  based on the voltage passed by the selector  472 . The bit line voltage is roughly equal to the control gate voltage of the transistor minus its Vt (e.g., 3 V). For example, if Vbl+Vt is passed by the selector  472 , the bit line voltage will be Vbl. This assumes the source line is at 0 V. The transistor  470  clamps the bit line voltage according to the control gate voltage and acts as a source-follower rather than a pass gate. The Vbl selector  462  may pass a relatively high voltage such as Vdd which is higher than the control gate voltage on the transistor  470  to provide the source-follower mode. During sensing, the transistor  470  thus charges up the bit line. 
     In one approach, the selector  472  of each sense amplifier can be controlled separately from the selectors of other sense amplifiers, to pass Vbl or Vdd. The Vbl selector  462  of each sense amplifier can also be controlled separately from the Vbl selectors of other sense amplifiers. 
     During sensing, the sense node  464  is charged up to an initial voltage such as Vsense_init=3 V. The sense node is then connected to the bit line by way of the transistor  470 , and an amount of decay of the sense node is used to determine whether a memory cell is in a conductive or non-conductive state. In one embodiment, a current that flows in the bot line discharges the sense node (e.g., sense capacitor). The length of time that the sense node is allowed to decay may be referred to herein as an “integration time.” The comparison circuit  466  is used to compare the sense node voltage to a trip voltage at a sense time. If the sense node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vt is at or below the voltage of the verification signal. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vt is above the voltage of the verification signal. The sense amplifier  350 ( 1 ) includes a trip latch  468  that is set by the comparison circuit  466  based on whether the memory cell is in a conductive or non-conductive state. The data in the trip latch can be a bit which is read out by the processor  482 . 
     The managing circuit  480  comprises a processor  482 , four example sets of data latches  484 ,  485 ,  486 ,  487  and an I/O Interface  488  coupled between the sets of data latches and data bus  332  (data bus may connect to memory controller  102 ). One set of data latches, e.g., comprising individual latches LDL, LMDL, UMDL, and UDL, can be provided for each sense amplifier. In some cases, fewer or additional data latches may be used. LDL stores a bit for a lower page of data, LMDL stores a bit for a lower-middle page of data, UMDL stores a bit for an upper-middle page of data, and UDL stores a bit for an upper page of data. This is in a sixteen level or four bits per memory cell memory device. In one embodiment, there are eight levels or three bits per memory cell and, therefore, only three latches (LDL, MDL, UDL) per sense amplifier. 
     The processor  482  performs computations, such as to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. Each set of data latches  484 - 487  is used to store data bits determined by processor  482  during a read operation, and to store data bits imported from the data bus  332  during a program operation which represent write data meant to be programmed into the memory. I/O interface  488  provides an interface between data latches  484 - 487  and the data bus  332 . 
     The processor  482  may also be used to determine what voltage to apply to the bit line, based on the state of the latches. 
     During reading, the operation of the system is under the control of state machine  312  that controls the supply of different control gate voltages to the addressed memory cell (e.g., by applying voltages from power control  316  to word lines on the memory structure  326  by way of the pathways between control die  304  and memory die  302  discussed herein). As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit may trip at one of these voltages and a corresponding output will be provided from sense circuit to processor  482  by way of the data bus  454 . At that point, processor  482  determines the resultant memory state by consideration of the tripping event(s) of the sense circuit and the information about the applied control gate voltage from the state machine by way of input lines  490 . It then computes a binary encoding for the memory state and stores the resultant data bits into data latches  484 - 487 . 
     Some implementations can include multiple processors  482 . In one embodiment, each processor  482  will include an output line (not depicted) such that each of the output lines is wired-OR&#39;d together. In some embodiments, the output lines are inverted prior to being connected to the wired-OR line. This configuration enables a quick determination during a program verify test of when the programming process has completed because the state machine receiving the wired-OR can determine when all bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logic zero for that bit will be sent to the wired-OR line (or a data one is inverted). When all bits output a data 0 (or a data one inverted), then the state machine knows to terminate the programming process. Because (in one embodiment) each processor communicates with four sense amplifiers, the state machine needs to read the wired-OR line four times, or logic is added to processor  482  to accumulate the results of the associated bit lines such that the state machine need only read the wired-OR line one time. Similarly, by choosing the logic levels correctly, the global state machine can detect when the first bit changes its state and change the algorithms accordingly. 
     During program or verify operations for memory cells, the data to be programmed (write data) is stored in the set of data latches  484 - 487  from the data bus  332 , in the LDL, LMDL, UMDL, and UDL latches, in a four-bit per memory cell implementation. 
     The program operation, under the control of the state machine, applies a set of programming voltage pulses to the control gates of the addressed memory cells. Each voltage pulse may be stepped up in magnitude from a previous program pulse by a step size in a process referred to as incremental step pulse programming. Each program voltage is followed by a verify operation to determine if the memory cells has been programmed to the desired memory state. In some cases, processor  482  monitors the read back memory state relative to the desired memory state. When the two are in agreement, the processor  482  sets the bit line in a program inhibit mode such as by updating its latches. This inhibits the memory cell coupled to the bit line from further programming even if additional program pulses are applied to its control gate. 
     Each set of data latches  484 - 487  may be implemented as a stack of data latches for each sense amplifier. In one embodiment, there are three data latches per sense amplifier  350 . In some implementations, the data latches are implemented as a shift register so that the parallel data stored therein is converted to serial data for data bus  332 , and vice versa. All the data latches corresponding to the read/write block of memory cells can be linked together to form a block shift register so that a block of data can be input or output by serial transfer. In particular, the bank of read/write circuits is adapted so that each of its set of data latches will shift data in to or out of the data bus in sequence as if they are part of a shift register for the entire read/write block. 
     The data latches identify when an associated memory cell has reached certain milestones in a program operation. For example, latches may identify that a memory cell&#39;s Vt is below a particular verify voltage. The data latches indicate whether a memory cell currently stores one or more bits from a page of data. For example, the LDL latches can be used to store a lower page of data. An LDL latch is flipped (e.g., from 0 to 1) when a lower page bit is stored in an associated memory cell. An LMDL, UMDL or UDL latch is flipped when a lower-middle, upper-middle or upper page bit, respectively, is stored in an associated memory cell. This occurs when an associated memory cell completes programming. 
       FIG.  8    is a block diagram of one embodiment of an integrated memory assembly  104 .  FIG.  8    depicts further details of one embodiment of the integrated memory assembly  104  of  FIGS.  1  and  4   . Memory die  302  contains a plane  520  of memory cells. The memory die  302  may have additional planes. The plane is divided into M blocks. In one example, each plane has about 1040 blocks. However, different numbers of blocks can also be used. In one embodiment, a block comprising memory cells is a unit of erase. That is, all memory cells of a block are erased together. In one embodiment, the block is the unit of erase. However, other embodiments can utilize other units of erase. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize the memory structure  326  to enable the signaling and selection circuits. One representative bit line (BL) is depicted for each plane. There may be thousand or tens of thousands of such bit lines per each plane. Each block may be divided into a number of word lines, as will be described more fully below. In one embodiment, a block represents a groups of connected memory cells as the memory cells of a block share a common set of unbroken word lines and unbroken bit lines. In the structure of  FIG.  8   , Block 0 and Block M−1 of plane  520  are at the edges of the memory structure (or otherwise referred to as being located in an edge region/section of the memory structure). 
     Control die  304  includes a number of sense amplifiers (SA)  350 . Each sense amplifier  350  is connected to one bit line. The sense amplifier contains a bit line driver. Thus, the sense amplifier may provide a voltage to the bit line to which it is connected. The sense amplifier is configured to sense a condition of the bit line. In one embodiment, the sense amplifier is configured to sense a current that flows in the bit line. In one embodiment, the sense amplifier is configured to sense a voltage on the bit line. 
     The control die  304  includes a number of word line drivers  560 ( 1 )- 560 ( n ). The word line drivers  560  are configured to provide voltages to word lines. In this example, there are “n” word lines per block of memory cells. In one embodiment, one of the blocks in the plane  520  is selected at a time for a memory array operation. If the memory operation is a program or read, one word line within the selected block is selected for the memory operation, in one embodiment. If the memory operation is an erase, all of the word lines within the selected block are selected for the erase, in one embodiment. The word line drivers  560  (e.g. part of Power Control  316 ) provide voltages to the word lines in a first selected block (e.g., Block 2) in memory die  302 . The control die  304  may also include charge pumps, voltage generators, and the like, which may be used to provide voltages for the word line drivers  560  and/or the bit line drivers. 
     The memory die  302  has a number of bond pads  570   a ,  570   b  on a first major surface  582  of memory die  302 . There may be “n” bond pads  570   a , to receive voltages from a corresponding “n” word line drivers  560 ( 1 )- 560 ( n ). There may be one bond pad  570   b  for each bit line associated with plane  520 . The reference numeral  570  will be used to refer in general to bond pads on major surface  582 . 
     In some embodiments, each data bit and each parity bit of a codeword are transferred through a different bond pad pair  570   b ,  574   b . The bits of the codeword may be transferred in parallel over the bond pad pairs  570   b ,  574   b . This provides for a very efficient data transfer relative to, for example, transferring data between the memory controller  102  and the integrated memory assembly  104 . For example, the data bus between the memory controller  102  and the integrated memory assembly  104  may, for example, provide for eight, sixteen, or perhaps 32 bits to be transferred in parallel. However, the data bus between the memory controller  102  and the integrated memory assembly  104  is not limited to these examples. 
     The control die  304  has a number of bond pads  574   a ,  574   b  on a first major surface  584  of control die  304 . There may be “n” bond pads  574   a , to deliver voltages from a corresponding “n” word line drivers  560 ( 1 )- 560 ( n ) to memory die  302   a . There may be one bond pad  574   b  for each bit line associated with plane  520 . The reference numeral  574  will be used to refer in general to bond pads on major surface  582 . Note that there may be bond pad pairs  570   a / 574   a  and bond pad pairs  570   b / 574   b . In some embodiments, bond pads  570  and/or  574  are flip-chip bond pads. 
     In one embodiment, the pattern of bond pads  570  matches the pattern of bond pads  574 . Bond pads  570  are bonded (e.g., flip chip bonded) to bond pads  574 . Thus, the bond pads  570 ,  574  electrically and physically couple the memory die  302  to the control die  304 . Also, the bond pads  570 ,  574  permit internal signal transfer between the memory die  302  and the control die  304 . Thus, the memory die  302  and the control die  304  are bonded together with bond pads. Although  FIG.  5 A  depicts one control die  304  bonded to one memory die  302 , in another embodiment one control die  304  is bonded to multiple memory dies  302 . 
     Herein, “internal signal transfer” means signal transfer between the control die  304  and the memory die  302 . The internal signal transfer permits the circuitry on the control die  304  to control memory operations in the memory die  302 . Therefore, the bond pads  570 ,  574  may be used for memory operation signal transfer. Herein, “memory operation signal transfer” refers to any signals that pertain to a memory operation in a memory die  302 . A memory operation signal transfer could include, but is not limited to, providing a voltage, providing a current, receiving a voltage, receiving a current, sensing a voltage, and/or sensing a current. 
     The bond pads  570 ,  574  may be formed for example of copper, aluminum and alloys thereof. There may be a liner between the bond pads  570 ,  574  and the major surfaces ( 582 ,  584 ). The liner may be formed for example of a titanium/titanium nitride stack. The bond pads  570 ,  574  and liner may be applied by vapor deposition and/or plating techniques. The bond pads and liners together may have a thickness of 720 nm, though this thickness may be larger or smaller in further embodiments. 
     Metal interconnects and/or vias may be used to electrically connect various elements in the dies to the bond pads  570 ,  574 . Several conductive pathways, which may be implemented with metal interconnects and/or vias are depicted. For example, a sense amplifier  350  may be electrically connected to bond pad  574   b  by pathway  512 . There may be thousands of such sense amplifiers, pathways, and bond pads. Note that the BL does not necessarily make direct connection to bond pad  570   b . The word line drivers  560  may be electrically connected to bond pads  574   a  by pathways  502 . Note that pathways  502  may comprise a separate conductive pathway for each word line driver  560 ( 1 )- 560 ( n ). Likewise, there may be a separate bond pad  574   a  for each word line driver  560 ( 1 )- 560 ( n ). The word lines in block 2 of the memory die  302  may be electrically connected to bond pads  570   a  by pathways  504 . In  FIG.  8   , there are “n” pathways  504 , for a corresponding “n” word lines in a block. There may be a separate pair of bond pads  570   a ,  574   a  for each pathway  504 . 
       FIG.  9    depicts another embodiment of an integrated memory assembly  104  in which one control die  304  may be used to control two memory die  302   a ,  302   b . The control die  304  has a number of a number of bond pads  574 ( a ),  574 ( b ) on a first major surface  584 , as discussed in connection with  FIG.  8   . The control die  304  has a number of a number of bond pads  576 ( a ),  576 ( b ) on a second major surface  588 . There may be “n” bond pads  576 ( a ) to deliver voltages from a corresponding “n” word line drivers  560 ( 1 )- 560 ( n ) to memory die  302   b . The word line drivers  560  may be electrically connected to bond pads  576   a  by pathways  506 . There may be one bond pad  576   b  for each bit line associated with plane  530  on memory die  302   b . The reference numeral  576  will be used to refer in general to bond pads on major surface  588 . 
     The second memory die  302   b  has a number of bond pads  572 ( a ),  572 ( b ) on a first major surface  586  of second memory die  302   b . There may be “n” bond pads  572 ( a ), to receive voltages from a corresponding “n” word line drivers  560 ( 1 )- 560 ( n ). The word lines in plane  530  may be electrically connected to bond pads  572   a  by pathways  508 . There may be one bond pad  572 ( b ) for each bit line associated with plane  530 . The reference numeral  572  will be used to refer in general to bond pads on major surface  586 . Note that there may be bond pad pairs  572 ( a )/ 576 ( a ) and bond pad pairs  572 ( b )/ 576 ( b ). In some embodiments, bond pads  572  and/or  576  are flip-chip bond pads. 
     In an embodiment, the “n” word line drivers  560 ( 1 )- 560 ( n ) are shared between the two memory die  302   a ,  302   b . For example, a single word line driver may be used to provide a voltage to a word line in memory die  302   a  and to a word line in memory die  302   b . However, it is not required that the word line drivers  560  are shared between the memory dies  302   a ,  302   b.    
       FIG.  10 A  is a top view of a semiconductor wafer  635   a  from which multiple control die  304  may be formed. The wafer  635   a  has numerous copies of integrated circuits  603 . Each of the integrated circuits  603  contains the control circuitry  310  (see  FIG.  4   ). Wafer  635   a  is diced into semiconductor dies, each containing one of the copies of the integrated circuits  603 . Therefore, numerous control semiconductor dies  304  may be formed from the wafer  635   a . Also note that even before the wafer  635   a  is diced, as the term “control semiconductor die” is used herein, each region in which an integrated circuit  603  resides may be referred to as a control semiconductor die  304 . 
       FIG.  10 B  is a top view of a semiconductor wafer  635   b  from which multiple memory die  302  may be formed. The wafer  635   b  has numerous copies of integrated circuits  605 . Each of the integrated circuits  605  contains memory structure  326  (see  FIG.  4   ), in one embodiment. The wafer  635   b  is diced into semiconductor dies, each containing one of the copies of the integrated circuits  605 , in some embodiments. Therefore, numerous memory semiconductor dies  302  may be formed from the wafer  635   b . Also note that even before the wafer  635   b  is diced, as the term “memory semiconductor die” is used herein, each region in which an integrated circuit  605  resides may be referred to as a memory semiconductor die  302 . 
     The semiconductor wafers  635  may start as an ingot of monocrystalline silicon grown according to either a CZ, FZ or other process. The semiconductor wafers  635  may be cut and polished on major surfaces to provide smooth surfaces. The integrated circuits  603 ,  605  may be formed on and/or in the major surfaces. Note that forming the integrated circuits  603 ,  605  on different wafers  635   a ,  635   b  facilitates use of different semiconductor fabrication processes on the different wafers  635   a ,  635   b . For example, semiconductor fabrication processes may involve high temperature anneals. Such high temperature anneals may be needed for formation of some circuit elements, or may be useful for improving properties of circuit elements. For example, a high temperature anneal can desirably reduce the resistance of polysilicon on the memory dies  302 . However, the high temperature anneal could be damaging to other circuit elements. For example, a high temperature anneal can potentially be damaging to CMOS transistors, such as the transistors that may be used on the semiconductor dies  304 . In one embodiment, a high temperature anneal that is used when fabricating the integrated circuits  605  on wafer  635   b  is not used when fabricating the integrated circuits  603  on wafer  635   a . For example, in one embodiment, a high temperature anneal that is used when fabricating the memory dies is not used when fabricating the control dies. 
     The dicing of the wafers  635  into semiconductor dies may occur before or after bonding. In one embodiment, the two wafers  635 ,  635   b  are bonded together. After bonding the two wafers together, dicing is performed. Therefore, numerous integrated memory assemblies  104  may be formed from the two wafers  635 . In another embodiment, the two wafers  635   a ,  635   b  are diced into semiconductor dies  304 ,  302 . Then, one of each of the semiconductor dies  304 ,  302  are bonded together to form an integrated memory assembly  104 . Regardless of whether dicing occurs prior to or after bonding, it may be stated that the integrated memory assembly  104  contains a control semiconductor die  304  and a memory semiconductor die  302  bonded together. 
     As has been discussed above, the control die  304  and the memory die  302  may be bonded together. Bond pads on each die  302 ,  304  may be used to bond the two dies together.  FIG.  10 C  depicts an example pattern of bond pads on a planar surface of a semiconductor die. The semiconductor die could be memory die  302  or control die  304 . The bond pads could be any of bond pads  570  or  574 , as appropriate for the semiconductor die. There may be many more bond pads than are depicted in  FIG.  10 C . As one example, 100,000 or more interconnections may be required between two of the semiconductor die. In order to support such large numbers of electrical interconnections, the bond pads may be provided with a small area and pitch. In some embodiments, the bond pads are flip-chip bond pads. 
     The semiconductor dies  302 ,  304  in the integrated memory assembly  104  may be bonded to each other by initially aligning the bond pads  570 ,  574  on the respective dies  302 ,  304  with each other. Thereafter, the bond pads may be bonded together by any of a variety of bonding techniques, depending in part on bond pad size and bond pad spacing (i.e., bond pad pitch). The bond pad size and pitch may in turn be dictated by the number of electrical interconnections required between the first and second semiconductor dies  302  and  304 . 
     In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 5 μm to 5 μm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu. 
     When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor dies including the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond to each other, and the film layers on the respective dies may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 1 μm to 5 μm. Bonding techniques may be used providing bond pads with even smaller sizes and pitches. 
     Some embodiments may include a film on surface of the dies  302  and  304 . Where no such film is initially provided, a space between the dies may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies  302 ,  304 , and further secures the dies together. Various materials may be used as under-fill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA. 
     As noted herein, there may be more than one control die  304  and more than one memory die  302  in an integrated memory assembly  104 . In some embodiments, the integrated memory assembly  104  includes a stack of multiple control die  304  and multiple memory die  302 .  FIG.  11    depicts a side view of an embodiment of an integrated memory assembly  104  stacked on a substrate  802 . The integrated memory assembly  104  has three control die  304  and three memory die  302 . Each control die  304  is bonded to one of the memory die  302 . Some of the bond pads  570 ,  574 , are depicted. There may be many more bond pads. A space between two dies  302 ,  304  that are bonded together is filled with a solid layer  848 , which may be formed from epoxy or other resin or polymer. This solid layer  848  protects the electrical connections between the dies  302 ,  304 , and further secures the dies together. Various materials may be used as solid layer  848 , but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA. 
     The integrated memory assembly  104  may for example be stacked with a stepped offset, leaving the bond pads  804  at each level uncovered and accessible from above. Wire bonds  806  connected to the bond pads  804  connect the control die  304  to the substrate  802 . A number of such wire bonds may be formed across the width of each control die  304  (i.e., into the page of  FIG.  8 A ). 
     A through silicon via (TSV)  812  may be used to route signals through a control die  304 . A through silicon via (TSV)  814  may be used to route signals through a memory die  302 . The TSVs  812 ,  814  may be formed before, during or after formation of the integrated circuits in the semiconductor dies  302 ,  304 . The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used. 
     Solder balls  808  may optionally be affixed to contact pads  810  on a lower surface of substrate  802 . The solder balls  808  may be used to electrically and mechanically couple the integrated memory assembly  104  to a host device such as a printed circuit board. Solder balls  808  may be omitted where the integrated memory assembly  104  is to be used as an LGA package. The solder balls  808  may form a part of the interface between the integrated memory assembly  104  and memory controller  102 . 
     In the embodiment of  FIG.  11   , the memory dies  302  and the control dies  304  are arranged as pairs. That is, each memory die  302  is bonded to and in communication with a corresponding/matching/paired control die. 
       FIG.  12    depicts a side view of an embodiment of an integrated memory assembly  104  stacked on a substrate  802 . The integrated memory assembly  104  has three control die  304  and three memory die  302 . In this example, each control die  304  is bonded to at least one memory die  302 . Optionally, a control die  304  may be bonded to two memory die  302 . For example, two of the control die  304  are bonded to a memory die  302  above the control die  304  and a memory die  302  below the control die  304 . 
     Some of the bond pads  570 ,  574  are depicted. There may be many more bond pads. A space between two dies  302 ,  304  that are bonded together is filled with a solid layer  848 , which may be formed from epoxy or other resin or polymer. In contrast to the example in  FIG.  11   , the integrated memory assembly  104  in  FIG.  12    does not have a stepped offset. A through silicon via (TSV)  812  may be used to route signals through a memory die  302 . A through silicon via (TSV)  814  may be used to route signals through a control die  304 . 
     Solder balls  808  may optionally be affixed to contact pads  810  on a lower surface of substrate  802 . The solder balls  808  may be used to electrically and mechanically couple the integrated memory assembly  104  to a host device such as a printed circuit board. Solder balls  808  may be omitted where the integrated memory assembly  104  is to be used as an LGA package. 
       FIG.  13    is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array that can comprise memory structure  326 , which includes a plurality non-volatile memory cells. For example,  FIG.  13    shows a portion of one block comprising memory. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers with vertical columns of materials extending through the dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108-304 alternating dielectric layers and conductive layers. One example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers and 110 dielectric layers. More or fewer than 108-304 layers can also be used. The alternating dielectric layers and conductive layers are divided into four “fingers” or sub-blocks by local interconnects LI, in an embodiment.  FIG.  9    shows two fingers and two local interconnects LI. Below the alternating dielectric layers and word line layers is a source line layer SL. Vertical columns of materials (also known as memory holes) are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the vertical columns/memory holes is marked as MH. Note that in  FIG.  913   , the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the vertical column/memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. One example of a suitable memory structure  326  is described in U.S. Pat. No. 10,553,298, incorporated herein by reference in its entirety. 
       FIG.  14    is a diagram of one embodiment of an integrated memory assembly  104 . In an embodiment depicted in  FIG.  14   , memory die  302  is bonded to control die  304 . This bonding configuration is similar to an embodiment depicted in  FIG.  8   . Note that although a gap is depicted between the pairs of adjacent dies, such a gap may be filled with an epoxy or other resin or polymer.  FIG.  14    shows additional details of one embodiment of pathways  352 . 
     The memory die includes a memory structure  326 . Memory structure  326  is adjacent to substrate  1072  of memory die  302 . In some embodiments, substrate  1072  is formed from a portion of a silicon wafer. In this example, the memory structure  326  include a three-dimensional memory array. The memory structure  326  has a similar structure as the example depicted in  FIG.  13   . There are a number of word line layers (WL), which are separated by dielectric layers. The dielectric layers are represented by gaps between the word line layers. Thus, the word line layers and dielectric layers form a stack. There may be many more word line layers than are depicted in  FIG.  14   . As with the example of  FIG.  13   , there are a number of columns that extend through the stack. One column  1002  is referred to in each stack with reference numeral  1002 . The columns contain memory cells. For example, each column may contain a NAND string. There are a number of bit lines (BL) adjacent to the stack. 
     Word line driver  560  concurrently provides voltages to a word line  1042  in memory die  302 . The pathway from the word line driver  560  to the word line  1042  includes conductive pathway  1032 , bond pad  574   a   1 , bond pad  570   a   1 , and conductive pathway  1034 . In some embodiments, conductive pathways  1032 ,  1034  are referred to as a pathway pair. Conductive pathways  1032 ,  1034  may each include one or more vias (which may extend vertically with respect to the major surfaces of the die) and one or more metal interconnects (which may extend horizontally with respect to the major surfaces of the die). Conductive pathways  1032 ,  1034  may include transistors or other circuit elements. In one embodiment, the transistors may be used to, in effect, open or close the pathway. Other word line drivers (not depicted in  FIG.  10 A ) provide voltages to other word lines. Thus, there are additional bond pad  574   a ,  570   a  in addition to bond pads  574   a   1 ,  570   a   1 . As is known in the art, the bond pads may be formed for example of copper, aluminum and alloys thereof. 
     Sense amplifier  350  is in communication with a bit line in memory die  302 . The pathway from the sense amplifier  350  to the bit line includes conductive pathway  1052 , bond pad  574   b , bond pad  570   b , and conductive pathway  1054 . In some embodiments, conductive pathways  1052 ,  1054  are referred to as a pathway pair. Conductive pathways  1052 ,  1054  may include one or more vias (which may extend vertically with respect to the major surfaces of the die) and one or more metal interconnects (which may extend horizontally with respect to the major surfaces of the die). The metal interconnects may be formed of a variety of electrically conductive metals including for example copper and copper alloys as is known in the art, and the vias may be lined and/or filled with a variety of electrically conductive metals including for example tungsten, copper and copper alloys as is known in the art. Conductive pathways  1052 ,  1054  may include transistors or other circuit elements. In one embodiment, the transistors may be used to, in effect, open or close the pathway. 
     The control die  304  has a substrate  1076 , which may be formed from a silicon wafer. The sense amplifiers  350 , word line driver(s)  560 , and other circuitry  1020  may be formed on and/or in the substrate  1076 . The circuitry  1020  may include some or all of the control circuitry  310 . In some embodiments, sense amplifiers  350 , word line driver(s)  560 , and/or other circuitry  1020  comprise CMOS circuits. 
     There is an external signal path that allows circuitry on the control die  304  to communicate with an entity external to the integrated memory assembly  104 , such as memory controller  102 . Therefore, circuitry  1020  on the control die  304  may communicate with, for example, memory controller  102 . Optionally, circuitry on the control die  304  may communicate with, for example, host  120 . The external pathway includes via  1058  in control die  304 , bond pad  574   c , bond pad  570   c , through silicon via (TSV)  1060 , and external pad  1078 . The TSV  1060  extends through substrate  1072 . 
     The TSV  1060 , may be formed before, during or after formation of the integrated circuits in the semiconductor dies  302 ,  304 . The TSV may be formed by etching holes through the wafers. For example, holes may be etched through substrate  1072 . The holes also may be etched through material adjacent to the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used. 
     Numerous modifications to the embodiment depicted in  FIG.  14    are possible. One modification is for sense amplifiers  350  to be located on memory die  302 . 
       FIG.  15    depicts one embodiment of an integrated memory assembly  104 . This bonding configuration is similar to an embodiment depicted in  FIG.  8   . The configuration in  FIG.  15    adds an extra memory die relative to the configuration in  FIG.  14   . Hence, similar reference numerals are used for memory die  302   a  in  FIG.  15   , as were used for memory die  302  in  FIG.  14   . In an embodiment depicted in  FIG.  15   , first memory die  302   a  is bonded to control die  304 , and control die  304  is bonded to second memory die  302   b . Note that although a gap is depicted between the pairs of adjacent dies, such a gap may be filled with an epoxy or other resin or polymer. 
     Each memory die  302   a ,  302   b  includes a memory structure  326 . Memory structure  326   a  is adjacent to substrate  1072  of memory die  302   a . Memory structure  326   b  is adjacent to substrate  1074  of memory die  302   b . The substrates  1072 ,  1074  are formed from a portion of a silicon wafer, in some embodiments. In this example, the memory structures  326  each include a three-dimensional memory array. 
     Word line driver  560  concurrently provides voltages to a first word line  1042  in memory die  302   a  and a second word line  1044  in memory die  302   b . The pathway from the word line driver  560  to the second word line  1044  includes conductive pathway  1032 , through silicon via (TSV)  1068 , bond pad  576   a   1 , bond pad  572   a   1 , and conductive pathway  1036 . Other word line drivers (not depicted in  FIG.  10 B ) provide voltages to other word lines. 
     Sense amplifier  350   a  is in communication with a bit line in memory die  302   a . The pathway from the sense amplifier  350   a  to the bit line includes conductive pathway  1052 , bond pad  574   b , bond pad  570   b , and conductive pathway  1054 . Sense amplifier  350   b  is in communication with a bit line in memory die  302   b . The pathway from the sense amplifier  350   b  to the bit line includes conductive pathway  1054 , TSV  1056 , bond pad  576   b , bond pad  572   b , and conductive pathway  1048 . 
     Numerous modifications to the embodiment depicted in  FIG.  10 B  are possible. One modification is for sense amplifiers  350   a  to be located on first memory die  302   a , and for sense amplifiers  350   b  to be located on second memory die  302   b.    
       FIG.  16    is a flowchart describing one embodiment of a process  1100  for programming NAND strings of memory cells. For purposes of this document, the term program and programming are synonymous with write and writing. In one embodiment, erasing memory cells can also be thought of as writing. In one example embodiment, the process of  FIG.  16    is performed on integrated memory assembly  104  using the control circuitry  310  discussed above. For example, the process of  FIG.  16    can be performed at the direction of state machine  312 . In one embodiment, process  1100  is used to program a codeword into memory structure  326 . The process of  FIG.  16    is performed by control die  104  to program memory cells on the memory die. In one embodiment, the process of  FIG.  16    is performed at the direction of state machine  312 . 
     In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step  1102  of  FIG.  11   , the programming voltage (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level) and a program counter PC maintained by state machine  312  is initialized at 1. 
     In one embodiment, the group of memory cells selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same word line (the selected word line). There will likely be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are supposed to be inhibited from programming. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming. Those NAND strings (e.g., unselected NAND strings) that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When a channel has a boosted voltage, the voltage differential between the channel and the word line is not large enough to cause programming. To assist in the boosting, in step  1104  the control die will pre-charge channels of NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. 
     In step  1106 , NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as “unselected NAND strings.” In one embodiment, the unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes. A program inhibit voltage is applied to the bit lines coupled the unselected NAND string. 
     In step  1108 , a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming) by the control die. If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage, in one embodiment. Herein, such a NAND string is referred to as a “selected NAND string.” 
     In step  1108 , the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they are inhibited from programming. 
     In step  1110 , memory cells that have reached their target states are locked out from further programming by the control die. Step  1110  may include performing verifying at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. In step  1110 , a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state. 
     If, in step  1112 , it is determined that all of the memory cells have reached their target threshold voltages (pass), the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step  1114 . Otherwise if, in step  1112 , it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step  1116 . 
     In step  1116 , the memory system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have, so far, failed to reach their target state. This counting can be done by state machine  312 , memory controller  102 , or other logic. In one implementation, each of the sense blocks will store the status (pass/fail) of their respective cells. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state. 
     In step  1118 , it is determined whether the count from step  1116  is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step  1114 . In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step  1118  is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allow for future/additional errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria. 
     If the number of failed memory cells is not less than the predetermined limit, than the programming process continues at step  1120  and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 12, 16, 19 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step  1124 . If the program counter PC is less than the program limit value PL, then the process continues at step  1122  during which time the Program Counter PC is incremented by 1 and the program voltage Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size (e.g., a step size of 0.1-1.0 volts). After step  1122 , the process loops back to step  1104  and another program pulse is applied to the selected word line (by the control die) so that another iteration (steps  1104 - 1122 ) of the programming process of  FIG.  16    is performed. 
     At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.  FIG.  17 A  is a graph of threshold voltage versus number of memory cells, and illustrates example threshold voltage distributions for the memory array when each memory cell stores single bit per memory cell data.  FIG.  17 A  shows two threshold voltage distributions: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Memory cells that have threshold voltages in threshold voltage distribution E are, therefore, in the erased data state (e.g., they are erased). Memory cells that have threshold voltages in threshold voltage distribution P are, therefore, in the programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data “1” and programmed memory cells store data “0.” Memory cells that store single bit per memory cell data are referred to as single level cells (“SLC”). 
       FIG.  17 B  illustrates example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”). In the example embodiment of  FIG.  17 B , each memory cell stores three bits of data. Other embodiments, however, may use other data capacities per memory cell (e.g., such as one, two, four, or five bits of data per memory cell).  FIG.  17   b    shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents memory cells that are erased. The other seven threshold voltage distributions (data states) A-G represent memory cells that are programmed and, therefore, are also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected. 
       FIG.  17 B  shows seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., A, B, C, D, . . . ) a memory cell is in. 
       FIG.  17 B  also shows seven verify reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system will test whether those memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test whether the memory cells have threshold voltages greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether memory cells have their threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system will test whether those memory cells have a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system will test whether those memory cells have a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system will test whether those memory cells have a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system will test whether those memory cells have a threshold voltage greater than or equal to VvG.  FIG.  17 B  also shows Vev, which is a voltage level to test whether a memory cell has been properly erased. 
     In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state Er directly to any of the programmed data states A-G using the process of  FIG.  16   . For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state Er. Then, a programming process is used to program memory cells directly into data states A, B, C, D, E, F, and/or G. For example, while some memory cells are being programmed from data state ER to data state A, other memory cells are being programmed from data state ER to data state B and/or from data state ER to data state C, and so on. The arrows of  FIG.  17 B  represent the full sequence programming. In some embodiments, data states A-G can overlap, with control die  304  and/or memory controller  102  relying on error correction to identify the correct data being stored. 
     In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read compare levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG, of  FIG.  17   ) or verify operation (e.g. see verify target levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG of  FIG.  17 B ) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased). 
     There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used. 
       FIG.  18    depicts threshold voltage distributions when each memory cell stores four bits of data.  FIG.  18    depicts that there may be some overlap between the threshold voltage distributions (data states) S0-S15. The overlap may occur due to factors such as memory cells losing charge (and hence dropping in threshold voltage). Program disturb can unintentionally increase the threshold voltage of a memory cell. Likewise, read disturb can unintentionally increase the threshold voltage of a memory cell. Over time, the locations of the threshold voltage distributions may change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read reference voltages can help to mitigate such effects. Using ECC during the read process can fix errors and ambiguities. When using four bits per memory cell, the memory can be programmed using the full sequence programming discussed above, or multi-pass programming processes. 
       FIG.  19    is a flow chart describing one embodiment of a process performed by memory controller  102  to cause data to be programmed into memory cells on memory die  302 . In the embodiment of  FIG.  19   , control die  304  encodes data for ECC purposes, rather than memory controller  102 . In step  1402 , memory controller  102  receives data from host  120  by way of interface  130  (see  FIG.  1   ). The data can be user data. For purposes of this document, user data is data received from an entity external to the memory system for storage in the memory system. For example, user data may be received from a host, another computing device, a sensor (e.g., a camera), etc. User data is not data preloaded in the memory system or data generated by the memory system. In an example implementation where the memory system is embedded in a digital camera, then user data would include image files captured by the camera. The memory controller may also receive a write command from the host and one or more logical addresses for the write command. The memory controller can translate the logical addresses to physical addresses. 
     In step  1404  of  FIG.  19   , memory controller  102  transfers raw data (e.g., user data not encoded with ECC information) to integrated memory assembly  104  (e.g., to one or more control die  304 ) by way of communication channel (e.g., a Toggle Mode interface). In step  1406 , memory controller  102  instructs one or more control die  304  to program the transferred raw data into one or more memory die  302 . In one embodiment, the instruction to perform the programming comprises sending one or more addresses and one or more commands by way of the communication channel (e.g., a Toggle Mode Interface—see memory controller interface  332 ). In some embodiments, step  1408  is performed before step  1406 . In step  1408 , the one or more control die  304  program the data into one or more memory die  302 . If there is more data to be programmed (step  1410 ), then the process of  FIG.  22    loops back to step  1402 ; otherwise, programming is complete (step  1412 ). 
       FIG.  20    is a flow chart describing one embodiment of a process performed by memory controller  102  to cause data to be read from memory cells on memory die  302 . In step  1502 , memory controller  102  sends a request to read to one or more control die  304 . In one embodiment, the instruction to perform the reading comprises sending one or more addresses and one or more commands by way of the communication channel (e.g., a Toggle Mode Interface—see memory controller interface  332 ). In step  1504 , one or more control die  304  perform a read process on one or more memory die  302  and store the data read in latches  360  on the one or more control die  302 . In step  1506 , the one or more control die  304  (e.g., decoder  390 ) decode the data read (as discussed above) and stored in the latches  360  on the one or more control die  304 . In step  1508 , the one or more control die  304  send the decoded data to memory controller  102  by way of the communication channel (e.g., a Toggle Mode Interface—see memory controller interface  332 ). In one embodiment, the one or more control die  304  send the decoded data bits but not the parity bits to memory controller  102  by way of the communication channel. In another embodiment, the control die sends the data read to the memory controller, and the memory controller decodes the data. 
     In one embodiment, a memory structure  326  is divided into blocks. A block may be divided into pages. In one example, a page is the unit of programming and/or the unit of reading, and a page comprises data in memory cells connected to a same word line. In other examples, different units of programming and reading can be used, and different arrangements of pages can be used. In some embodiments, pages are divided into fragments (also referred flash management units). In some example implementations, a fragment is the unit of programming and/or the unit of reading. In one example implementation, a page is 16K of data and a fragment is 4K of data; however, other amounts can also be implemented. In another embodiment, data can be arranged in metablocks. For purposes of this document, a metablock is a collection of blocks across multiple memory dies (e.g., one physical block on each of a plurality of memory dies). A metablock may be divided into metapages. For purposes of this document, a metapage is a collection of pages across multiple memory dies (e.g., one page in a single block on each of a plurality of memory dies). A metapage exists in a metablock. Metapages comprise a plurality of fragments. 
     In one embodiment, memory controller  102  maintains a validity map in its local volatile memory (e.g., DRAM  106  or SRAM  160 ). The validity map includes a set of data for every physical block and/or every metablock. The set of data for a block or metablock comprises an identification of each fragment and a flag indicating whether that fragment is valid data or invalid data. In alternative embodiments, the validity bitmap may indicate the validity of pages or other units, rather than fragments. 
     As discussed above, the non-volatile memory is addressed internally to the memory system using physical addresses associated with the one or more memory die while the host will use logical addresses to address the various memory locations. To enable this use of logical and physical addresses, the memory controller typically performs address translation between the logical addresses used by the host and the physical addresses used by the memory die using L2P tables. Each record of an L2P table may indicate a logical address and a corresponding physical address. In one embodiment, the L2P tables are arranged or indexed by logical address. For example, a record in the L2P tables can be found by knowing a logical block address and an offset of the page or fragment. 
     For example, in the process of  FIG.  19   , after receiving the data and a logical address from the host in step  1402 , the memory controller chooses a physical address to store the data and stores the physical address with its corresponding logical address in a L2P table. That physical address is provided to the one or more control die in step  1406 , and the one or more control die program the host data to that physical address in the one or more memory die in step  1408 . In regard to the process of  FIG.  20   , the memory controller typically sends the physical address to the one or more control die when requesting a read operation (step  1502 ) and the one or more control die use that physical address to read the requested data (step  1504 ). Prior to step  1502 , it is typical that the memory controller will access a L2P table to translate the logical address for the read process to a physical address. 
     Memory controller  102  may also maintain P2L tables that are used to translate physical addresses to logical addresses. Each record of a P2L table may indicate a physical address and a corresponding logical address. In one embodiment, the P2L tables are arranged or indexed by physical address. For example, a record in the P2L tables can be found by knowing a physical block address and an offset of the page or fragment. A memory controller may use a P2L table to perform garbage collection. 
     In one embodiment, the entire set of validity bitmaps, L2P tables and P2L tables are stored in one or more of the non-volatile memory structures  326  of the multiple memory die  302  of the memory system  100 . A subset of the validity bitmaps, L2P tables and P2L tables are stored in caches in DRAM  106  or SRAM  160 . When memory controller  102  needs to access the validity bitmaps, L2P tables and P2L tables, it first checks to see if the needed data is in the caches in DRAM  106  or SRAM  160 . If so (cache hit), then the data from the cache is used. If not (cache miss), then the portions of the validity bitmaps, L2P tables and/or P2L tables needed are read from the non-volatile memory structures  326  of the multiple memory die  302  of the memory system  100  and transferred to memory controller  102  to load in the cache in DRAM  106  (or SRAM  160 ) to be used by memory controller  102 . The transfer of the validity bitmaps, L2P tables and/or P2L tables causes the time to perform a memory operation to increase and also uses extra power. Therefore, to avoid the transfer of the validity bitmaps, L2P tables and/or P2L tables to the memory controller or to prevent the transfer from slowing doing a memory operation, it is proposed to use the validity bitmaps, L2P tables and/or P2L tables at the control die (which is at the memory die) to support the memory operation. For example, it is proposed to perform the address translation using the L2P table at the control die (which is at the memory die). 
       FIG.  21    is a flow chart describing one embodiment of a process for performing a memory operation that includes performing the address translation using the L2P table at the control die. In step  1602  of  FIG.  21   , memory controller  102  receives a request from host  120  to perform a memory operation for a logical address. For example, the memory operation may be to read or write (e.g., program or erase) host data. In step  1604 , memory controller  102  determines that a local cache does not contain information for the memory controller to perform a logical address to physical address translation operation for the logical address (cache miss). In step  1606 , in response to the cache miss of step  1604 , memory controller  102  requests that control die  304  perform the logical address to physical address translation operation. In step  1608 , control die  304  receives the request to perform the logical address to physical address translation operation, including receiving an indication of the logical address. The indication of the logical address can be the actual logical address or data that can be used to find/generate the actual logical address (e.g., a pointer to a location in a data structure such as a L2P table). In step  1610 , memory controller  102  requests that control die  304  perform the memory operation (e.g., read, write, etc.). In step  1612 , control die  304  receives the request from memory controller  102  to perform the memory operation on the non-volatile memory cells of memory die  302 . 
     In step  1614 , control die  304  performs the logical address to physical address translation operation on the control die (without intervention by the memory controller) using the received indication of the logical address. The logical address corresponds to a physical address for the non-volatile memory cells of the memory die  302 . In one embodiment, the logical address to physical address translation operation includes performing any one or more of updating a L2P table, updating a P2L table, translating a logical address to a physical address, and translating a physical address to a logical address. In step  1616 , control die  304  performs the memory operation on the non-volatile memory cells of the memory die  302  using the physical address. For example, control die  304  reads data from or writes data to memory die  302 . Other memory operations can also be performed. In step  1618 , control die  304  reports to the memory controller  102  (e.g., status of logical address to physical address translation operation, status of memory operation and/or host data in one or more reporting messages). 
       FIG.  22    is a block diagram depicting an example of components that can be used to perform a memory operation that includes performing the address translation using the L2P table at the control die. That is,  FIG.  22    provides one embodiment of a system for performing the process of  FIG.  21   .  FIG.  22    shows memory controller  120  including a data/command path  1702  in communication with L2P module  1704 , VB module  1710 , P2L module  1720 . L2P module  1704  manages the use and maintenance of L2P tables, and address translation using the L2P tables. VB module  1710  manages the use and maintenance of validity bitmaps. P2L module  1720  manages the use and maintenance of P2L tables, and address translation using the P2L tables. L2P cache  1708  is a portion of DRAM  106  (or SRAM  160 ) that stores the above-described L2P cache. L2P cache manager  1706 , in communication with L2P module  1704  and L2P cache  1708 , manages the L2P cache  1708 . P2L cache  1724  is a portion of DRAM  106  (or SRAM  160 ) that stores the P2L cache. P2L cache manager  1722 , in communication with P2L module  1720  and P2L cache  1724 , manages the P2L cache  1724 . VB cache  1714  is a portion of DRAM  106  (or SRAM  160 ) that stores the VB cache. VB cache manager  1712 , in communication with VB module  1710  and VB cache  1714 , manages the VB cache  1714 . In one embodiment, L2P module  1704 , VB module  1710 , P2L module  1720 , L2P cache manager  1706 , P2L cache manager  1722  and VB cache manager  1712  are implemented in software (e.g., running on memory processor  156  and/or processor  220 / 250 —see  FIGS.  2  and  3   ), while in other embodiments they are electrical circuits. 
     Memory controller  102  is in communication with one or more integrated memory assemblies  104  via communication path  1770 . Communication path  1770  is an example implementation of communication channel  336  of  FIG.  4    (see also the channels for communicating of  FIG.  3   ) and can be implemented as a Toggle Mode interface or other type of interface. Integrated assembly  104  includes one or more control die  304  connected to (e.g., bonded to) one or more memory die  302 , as discussed above. As depicted, one or more integrated assemblies  104  are physically separate form memory controller  102 . 
       FIG.  22    also depicts a subset of the components of control die  304 . Commands from memory controller  102  are received at the command parser  1750 , which is in communication with L2P module  1752 , VB module  1754 , P2L module  1756  and Read/Write circuits  328 . Command parser  1750  parses the received command and sends instructions/commands to the other components. In one embodiment, command parser  1750  is part of state machine  312 , another processor (e.g., RISC processor), or a stand-alone electrical circuit. L2P cache  1743  is a local cache of a subset of L2P tables. In one example, L2P cache  1753  stores recently used L2P tables. L2P module  1752  is connected to and manages L2P cache  1753  (e.g., L2P module  1752  is a cache controller). L2P module  1752  also performs logical address to physical address translation operations. In one embodiment, L2P module  1752  is an electrical circuit that is part of address translation circuit  334 . In another embodiment, L2P module  1752  is implemented in software running on the state machine, RISC processor, microcontroller or other processor. P2L module  1756  performs physical address to logical address translation operations. In one embodiment, P2L module  1756  is an electrical circuit that is part of address translation circuit  334 . In another embodiment, P2L module  1756  is implemented in software running on the state machine, RISC processor, microcontroller or other processor. One example implementation of control die  304  includes a P2L cache (not depicted in  FIG.  22   ) connected to P2L module  1756  that is a local cache of a subset of P2L tables. VB module  1754  uses and manages a validity bitmap. In one embodiment, VB module  1754  is an electrical circuit that is part of address translation circuit  334 . In another embodiment, VB module  1754  is implemented in software running on the state machine, RISC processor, microcontroller or other processor. One example implementation of control die  304  includes a VB cache (not depicted in  FIG.  22   ) connected to VB module  1754  that is a local cache of a subset of the validity bitmaps. 
     Although  FIG.  22    depicts one control die  304  and one memory die, some embodiments may have multiple control die and multiple memory die. For example, a system may have one or more integrated memory assemblies having a first semiconductor die (memory die), a second semiconductor die (control die) bonded to the first semiconductor die for performing address translation for physical addresses on the first semiconductor die, a third semiconductor die (memory die), and a fourth semiconductor die (control die) bonded to the third semiconductor die for performing address translation for physical addresses on the third semiconductor die. 
       FIG.  22    shows control die  304  with ECC module  330 , which (in some embodiments) is used by control die  304  to encode data to be stored in memory die  304  with error correction information and decode data read from memory die  304  (e.g., correct errors in the data read and remove ECC information). In some embodiments, ECC module  330  is also used to decode L2P tables when reading the L2P tables from memory die  302  and encode L2P tables when writing updated L2P tables to memory die  302 . The encoding and decoding by ECC module  330  is performed entirely on control die  304 . 
     In the system depicted in  FIG.  22   , both the memory controller  102  and the control die  304  can perform the address translation. For example, the memory controller is configured to receive commands from a host, perform logical address to physical address translation operations for at least a first subset of the received commands, instruct the control die to perform logical address to physical address translation operations for at least a second subset of the received commands and instruct the control die to perform memory operations for the received commands; while the control die is configured to perform logical address to physical address translation operations for the second subset of the received commands and perform memory operations for the first subset of the received commands and the second subset of the received commands. In one embodiment, the memory controller determines whether the memory controller or the control die performs the address translation operation(s) for a command. 
       FIGS.  23 A,  23 B,  23 C and  23 D  together form a flow chart describing one embodiment of a process for performing a memory operation that includes performing the address translation using an L2P table at the control die. The process of  FIGS.  23 A,  23 B,  23 C and  23 D  is one embodiment of an example implementation of the process of  FIG.  21    for which the memory operation is a write operation. 
     In step  1802 , memory controller  102  receives a write request from host  120 . In step  1804 , memory controller  102  receives host data to write to non-volatile memory. In step  1806 , memory controller  102  receives a logical addresses for the write request. The write request, host data and logical address are received from host  120  via interface  130 . In step  1808 , memory controller  102  determines a physical location (e.g., page, fragment, block, etc.) in non-volatile memory to write the received host data. After the host data is written to the chosen physical location, the validity bit map will need to be updated. Thus, in step  1810 , memory controller  102  determines if the validity bitmap is in the cache (local cache in DRAM  106  or SRAM  160 ). For example, VB module  1710  instructs VB cache manager  1712  to determine if the validity bitmap is in VB cache  1714 . If (in step  1812 ) the validity bitmap is in the cache (cache hit), then the memory controller  102  (VB cache manager  1712 ) updates the validity bitmap in VB cache  1714  (step  1814 ). If (in step  1812 ) the validity bitmap is in not the cache (cache miss), then in step  1816  memory controller  102  determines whether to load the validity bitmap into the cache from the non-volatile memory. For example, VB cache manager  1712  may decide (e.g., using artificial intelligence or based on history) that the particular validity bitmap is needed often or will be needed soon so it is best to load it into the VB cache  1714 . Thus, in step  1818 , memory controller  102  will fetch the validity bitmap from the non-volatile memory, load it into VB cache  1714 , and update it based on the chosen physical address from step  1808 . If VB cache manager  1712  decides not to load the validity bitmap, then (in step  1820 ) memory controller  102  (e.g., VB module  1710  or another component) determines to have control die  304  update the validity bitmap. In step  1822 , memory controller  102  (e.g., VB module  1710  or another component) determines the address of the record(s) in the validity bitmap that need to be changed and what the changes are to the those records in the validity bitmap. After steps  1814 ,  1818  and/or  1822 , the process continues at  1902  of  FIG.  23 B  (see A). 
     In step  1902 , memory controller  102  determines if the L2P table for the logical address received in step  1806  is in the L2P cache. For example, L2P module  1704  queries L2P cache manager  1706  to determine if the record/entry of the appropriate L2P table is in L2P cache  1708 . If (in step  1914 ) the record/entry of the appropriate L2P table is in L2P cache  1708  (cache hit), then in step  1916  memory controller  102  (e.g., L2P module  1704  and/or L2P cache manager  1706 ) updates L2P table and performs the normal write process (e.g., performs the process of  FIG.  19   ). If (in step  1914 ) the record/entry of the appropriate L2P table is not in L2P cache  1708  (cache miss), then in step  1918  memory controller  102  (e.g., L2P cache manager  1706 ) determines whether to load the L2P table into the cache from the non-volatile memory. For example, L2P cache manager  1706  may decide (e.g., using artificial intelligence or based on history) that the particular L2P is needed often or will be needed soon so it is best to load it into the L2P cache  1708 . Thus, in step  1920 , memory controller  102  will fetch the L2P table from the non-volatile memory, load it into L2P cache  1708 , and update it based on the chosen physical address from step  1808 . If L2P cache manager  1706  decides not to load the validity bitmap, then the (in step  1922 ) memory controller  102  (e.g., L2P module  1704  or another component) determines to have control die  304  update L2P table. In step  1924 , memory controller  102  (e.g., L2P module  1704  or another component) determines the address of the entry(s)/record(s) in the L2P table that need to be changed and what the changes are to the those entries/records in the L2P table. After steps  1916 ,  1920  and/or  1924 , the process continues at  2002  of  FIG.  23 C  (see B). 
     In step  2002 , memory controller  102  determines if the P2L table for the physical address chosen in step  1808  is in the P2L cache. For example, P2L module  1720  queries P2L cache manager  1722  to determine if the record/entry of the appropriate P2L table is in P2L cache  1724 . If (in step  2004 ) the record/entry of the appropriate P2L table is in P2L cache  1724  (cache hit), then in step  2006  memory controller  102  (e.g., P2L module  1704  and P2L cache manager  1706 ) updates P2L table. If (in step  2004 ) the record/entry of the appropriate P2L table is not in P2L cache  1724  (cache miss), then in step  2008  memory controller  102  (e.g., P2L cache manager  1722 ) determines whether to load the P2L table into the cache from the non-volatile memory. For example, P2L cache manager  1722  may decide (e.g., using artificial intelligence or based on history) that the particular P2L is needed often or will be needed soon so it is best to load it into the P2L cache  1724 . Thus, in step  2010 , memory controller  102  will fetch the P2L table from the non-volatile memory, load it into P2L cache  1724 , and update it based on the logical address received from the host. If P2L cache manager  1722  decides not to load the validity bitmap, then the (in step  2012 ) memory controller  102  (e.g., P2L module  1720  or another component) determines to have control die  304  update P2L table. In step  2014 , memory controller  102  (e.g., P2L module  1720  or another component) determines the address of the entry(s)/record(s) in the P2L table that need to be changed and what the changes are to the those entries/records in the P2L table. After steps  2006 ,  2010  and/or  2014 , the process continues at  2102  of  FIG.  23 D  (see C). 
     In step  2102 , memory controller  102  sends a metadata flush command to control die  304 . The metadata flush command indicates which of the L2P table(s), P2L table(s) and validity bitmap(s) need to be updated by control die  304  (as determined in steps  1820 ,  1922 ,  2012 ). The metadata flush command also includes: (1) addresses of entries/records in the L2P table(s), P2L table(s) and validity bitmap(s) that need to be updated; and (2) the changes that need to be made to the L2P table(s), P2L table(s) and validity bitmap(s). 
     In step  2104 , control die  304  reads the addressed L2P table (e.g., page, block or other unit) from non-volatile memory and stores the L2P table (or portion) in local storage (e.g., SRAM, latches, etc.) on control die  304 . In one embodiment, reading the L2P table from non-volatile memory includes ECC module on control  304  decoding the L2P table to correct errors and remove the error correction information (ECC decoding). In step  2106 , control die  304  updates the L2P table while stored on the control die  304 . For example, L2P cache module  1752  will update the field for the physical address (from step  1808 ) in the entry for the logical address received from the host, in the L2P table stored in L2P cache  1753  on control die  304 . In step  2108 , control die  304  writes the updated L2P table to non-volatile memory. In one embodiment, writing the updated L2P table to non-volatile memory includes encoding the updated L2P table with error correction data prior to writing to non-volatile memory. 
     In step  2110 , control die  304  loads/reads (and ECC decodes) the validity bitmap (e.g., page, block or other unit) from non-volatile memory and stores the validity bitmap (or portion) in local storage (e.g., SRAM, latches, etc.) on control die  304 . In step  2112 , control die  304  updates the validity bitmap while stored on control die  304 . In step  2114 , control die  304  writes the updated validity bitmap to non-volatile memory. In one embodiment, writing the updated validity bitmap to non-volatile memory includes encoding the updated validity bitmap with error correction data prior to writing to non-volatile memory. 
     In step  2116 , control die  304  reads (and ECC decodes) the P2L table (e.g., page, block or other unit) from non-volatile memory and stores P2L table (or portion) in local storage (e.g., SRAM, latches, etc.) on control die  304 . In step  2118 , control die  304  updates the P2L table. In step  2120 , control die  304  writes the updated P2L table to non-volatile memory. In one embodiment, writing the updated P2L table to non-volatile memory includes encoding the updated P2L table with error correction data prior to writing to non-volatile memory. 
     In step  2122 , control die  304  informs memory controller  102  that the L2P table(s), validity bitmap(s) and P2L table(s) were successfully updated and (in some embodiments) the location of the updated L2P table(s), validity bitmap(s) and P2L table(s). In response, memory controller  102  updates a master table indicating status and location of L2P table(s), P2L table(s) and validity bitmap(s). 
     In step  2124 , memory controller  102  sends a write command to control die  304 . In step  2126 , memory controller  102  sends the physical address to control die  304 . In step  2128 , memory controller  102  sends the host data to control die  304 . In step  2130 , control die  304  writes the host data to the physical address in the memory die  302 . 
     In one embodiment, the updating of the L2P table(s), P2L table(s) and validity bitmap(s) in steps  2106 ,  2112  and  2118  are performed on control die  304  by control die  304  with no involvement of memory controller  102  and without transferring the L2P table(s), P2L table(s) and validity bitmap(s) to memory controller  102 . 
     In embodiments where there are multiple control dies and multiple memory dies, all of the L2P tables, P2L tables and validity bitmaps for a memory die are managed/updated by the corresponding control die bonded to that memory die. 
       FIG.  24    is a flow chart describing one embodiment of a process for performing a memory operation that includes performing the address translation using the L2P table at the control die. The process of  FIG.  24    is one embodiment of an example implementation of the process of  FIG.  21    for which the memory operation is a read operation. 
     In step  2202 , memory controller  102  receives a read request from host  120 . In step  2204 , memory controller  102  receives a logical address for the read request. The read request and logical address are received from host  120  via interface  130 . In step  2206 , memory controller  102  determines if the L2P table for the received logical address is in L2P cache. For example, L2P module  1704  queries L2P cache manager  1706  to determine if the record/entry of the appropriate L2P table for the received logical address is in L2P cache  1708 . If (in step  2208 ) the record/entry of the appropriate L2P table is in L2P cache  1708  (cache hit), then in step  2220  memory controller  102  (e.g., L2P module  1704 ) performs address translation to determine the physical address associated with the received logical address based on the L2P table in the cache. In step  2222 , memory controller requests control die  304  to read the host data at the physical address. In step  2224 , control die reads the host data from the memory die at the physical address. In step  2226 , control die reports the data read to the memory controller, In step  2228 , memory controller  102  reports the data read to the host. In one embodiment, steps  2222 - 2228  can include performing the process of  FIG.  20   . 
     If, in step  2208 , it is determined that the record/entry of the appropriate L2P table is not in L2P cache  1708  (cache hit), then in step  2220  memory controller  102  (e.g., L2P cache manager  1706 ) determines whether to load the L2P table into the cache from the non-volatile memory. For example, L2P cache manager  1706  may decide (e.g., using artificial intelligence or based on history) that the particular L2P is needed often or will be needed soon so it is best to load it into the L2P cache  1708 . Thus, in step  2242 , memory controller  102  will fetch the L2P table from the non-volatile memory and load it into L2P cache  1708 . The process then continues at step  2220 . 
     If L2P cache manager  1706  decides not to load the L2P table into the L2P cache in the memory controller, then in step  2244  memory controller  102  will perform a read process with the control die performing address translation. 
       FIG.  25    is a flow chart describing one embodiment of a process for performing a read process with the control die  304  performing address translation. Thus, the process of  FIG.  25    is one example implementation of step  2244  of  FIG.  24   . In step  2302  of  FIG.  25   , memory controller  102  determines the L2P table (e.g., page of data) to be read for the logical address to physical address translation (e.g., determine metablock number and offset). In step  2304 , memory controller  102  sends a request to read and perform address translation, which includes sending the address of L2P table in non-volatile memory (e.g., metablock number and offset). The logical address being translated can be included in the request, but does not need to be since the address of the entry in the L2P table is included. In step  2306 , control die  304  reads the L2P table (e.g., page, block or other unit) from the non-volatile memory, decodes it and stores the L2P table (or portion) in local storage (e.g., SRAM, latches, etc.), such as L2P cache  1753 . In step  2308 , control die  304  uses the L2P table to determine the physical address that corresponds to the logical address received from the host for this read command. In step  2310 , control die  304  reads the host data at the determined physical address, including decoding of data. In step  2312 , control die  304  sends the host data read to memory controller  102 . In step  2314 , control die  304  sends the L2P table to memory controller  102  (optional). In step  2316 , memory controller  102  sends the host data read to host  120 . 
       FIG.  26    is a flow chart describing one embodiment of a process for a control die to perform address translation. Thus, the process of  FIG.  26    is one example implementation of step  2308  of  FIG.  25   . In one embodiment, the process of  FIG.  26    is performed by L2P module  1752  of control die  304 . 
     In step  2402  of  FIG.  26   , control die  304  loads configuration information for addresses translation. The configuration information may include how many planes in a memory die, an indication of how addresses are interleaved among planes and/or dies, the size of the entries in the L2P tables, addresses of the L2P tables, etc. The configuration information may be stored on the memory die  302 . In step  2040 , control die  304  access metablock or block number of the L2P table and the offset into the block of the entry in the L2P table for the logical address that needs to be translated to a physical address. In one embodiment, control die  304  accesses the metablock or block number and the offset from the request in step  2304 . In step  2406 , control die  304  determines whether the metablock or block number of the L2P table is within an appropriate range for L2P tables in the connected memory die  302 . If not, then in step  2408 , control die  304  responds to the memory controller  102  with an error message. If the metablock or block number of the L2P table is within an appropriate range for L2P tables, then in step  2410  control die  304  performs one or more sensing operations for the page of data (or fragment or other unit of data) of the metablock indicated by offset. In step  2412 , control die  304  obtains the physical address (the result of the address translation). That page of data read in step  2410  contains the entry in the L2P table for the logical address being translated. That entry includes the physical address or data to determine the physical address. In step  2414 , control die  304  determines the die number for the physical address obtained in step  2412 . In step  2416 , control die  304  determines whether the die number for the physical address obtained in step  2412  is the same die as the memory die  302  that stored the L2P table read in step  2410 . If not, then in step  2418 , control die  304  responds to the memory controller  102  with an error message because (in one embodiment) the L2P tables stored on a memory die are only supposed to store address translation information for logical and physical addresses of the same memory die. If the die number for the physical address obtained in step  2412  is the same die as the memory die  302  that stored the L2P table read in step  2410 , then in step  2420 , the logical address to physical address translation has completed successfully. 
       FIG.  27    is a block diagram describing one example embodiment for interleaving logical addresses among different memory die.  FIG.  27    represents a memory system with multiple integrated memory assemblies that each include a control die bonded to a memory die. For example,  FIG.  27    shows memory die 0 (Die 0), memory die 1 (Die 1), memory die 2 (Die 2), and memory die 3 (Die 3). In one embodiment, each of the four memory dies include a three dimensional non-volatile memory structure (e.g., memory array) that comprises non-volatile memory cells; each of the four memory dies is directly bonded to a corresponding control die; and each control die performs logical address to physical address translation for its bonded memory die. The entire control dies are not depicted in  FIG.  27   ; however, the drawing does show a portion of the control dies that performs the address translation (e.g., L2P module  1752  of each control die) in the form of GAT Inst 0, GAT Inst 1, GAT Inst 2, GAT Inst 3, and GAT Inst 4. GAT Inst 0 performs global address translation (e.g., logical address to physical address translation) for memory die 0 (Die 0). GAT Inst 1 performs global address translation (e.g., logical address to physical address translation) for memory die 1 (Die 1). GAT Inst 2 performs global address translation (e.g., logical address to physical address translation) for memory die 2 (Die 2). GAT Inst 3 performs global address translation (e.g., logical address to physical address translation) for memory die 3 (Die 3). 
     In one embodiment, the range of logical addresses (referred to as the logical address space and referenced in  FIG.  27    as LBA Range) is divided into 32K groups of consecutive logical addresses. The assignment of the groups of consecutive logical addresses is interleaved so that the first group LG0 is assigned to GAT Inst 0 and memory die 0 (Die 0), the second group LG8 is assigned to GAT Inst 1 and memory die 1 (Die 1), the third group LG16 is assigned to GAT Inst 2 and memory die 2 (Die 2), the fourth group LG24 is assigned to GAT Inst 3 and memory die 3 (Die 3), the fifth group LG32 is assigned to GAT Inst 0 and memory die 0 (Die 0), the sixth group LG40 is assigned to GAT Inst 1 and memory die 1 (Die 1), the seventh group LG48 is assigned to GAT Inst 2 and memory die 2 (Die 2), the eighth group LG56 is assigned to GAT Inst 3 and memory die 3 (Die 3), etc. Thus, the groups (or other units) of consecutive logical addresses are interleaved between the integrated memory assemblies such that consecutive groups (or other units) of consecutive logical addresses are assigned to different integrated memory assemblies. Each control die performs logical address to physical address translation for its bonded memory die for logical addresses in the logical address space that is assigned to the memory die. This architecture of interleaving promotes concurrent performance of memory operations on different memory dies, which increases performance of memory operations. The architecture of  FIG.  27    also allows an integrated memory assembly to use and maintain address translation data (and other metadata) for and within the same integrated memory assembly so translation can be entirely performed within that integrated memory assembly. Note that although  FIG.  27    shows four memory dies, more or less than four can also be implemented. 
       FIG.  28    is a block diagram describing the placement of address translation information (and/or other metadata) within a namespace. An NVMe namespace is a quantity of non-volatile memory that can be formatted into logical blocks. Namespaces are used when a storage virtual machine is configured with the NVMe protocol. One or more namespaces are provisioned and connected to an NVMe host. Each namespace can support various block sizes. A namespace ID (NSID) is an identifier used to provide access to a namespace.  FIG.  28    shows two examples NVMe Set 0 and NVMe Set 1, each of which are a collection of one or more namespaces. NVME Set 0 includes two namespaces: Namespace 1 and Namespace 2. Name space 1 is assigned logical addresses LBA 0-5000. Namespace 2 is assigned logical addresses LBA 0-2000. 
     NVME Set 0 includes one memory die, Die 0, which is configured to store host data in host data block MB7 (metablock 7) and host data block 8 (metablock 9), as well as other host data blocks. Die 0 is also configured to store address translation information (e.g., L2P tables) in metadata block 5 (GAT block 5), metadata block 9 (GAT block 9), as well as other metadata blocks. One control die is connected/bonded to Die 0 for using the L2P tables in metadata block 5 (GAT block 5) and metadata block 9 (GAT block 9) to perform address translation for host data in host data block MB7 (metablock 7) and host data block 8 (metablock 9). NVME Set 0 provides an example where all of the address translation information (and other metadata) are on the same die as the corresponding host data. 
     NVME Set 1 includes three memory die: Die 1, Die 2 and Die 3, each of which is connected/bonded to a corresponding control die (CBA). NVME Set 1 includes one namespace, Namespace 2, which is assigned logical addresses LBA 0-10000. Namespace 2 can store host data in host data block MB Z (on Die 1) and host data block MB A, as well as other host data blocks. Namespace 2 can store address translation information (e.g., L2P tables) in metadata block X (on Die 1), metadata block Y (on Die 2), as well as other metadata blocks. NVME Set 1 represents an implementation where the non-volatile memory cells of multiple memory (semiconductor) dies (e.g., Die 1 and Die 2) are in a same namespace, but each memory die stores the address translation information for the host data stored on that memory die in order to guarantee quality of service. In other embodiments, address translation information can be stored in the same namespace but different memory die. 
     A non-volatile storage system has been proposed in which both the memory controller and the control die can perform the address translation. 
     One embodiment includes an apparatus that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die includes non-volatile memory cells and a first plurality of pathways. The second semiconductor die includes one or more control circuits. The second semiconductor die further comprises an interface to a memory controller and a second plurality of pathways directly connected to the first plurality of pathways. The second semiconductor die is directly connected to the first semiconductor die. The one or more control circuits are configured to transfer signals through pathway pairs of the first plurality of pathways and the second plurality of pathways. The one or more control circuits are configured to: receive a request from the memory controller (via the interface to the memory controller) to perform a memory operation on the non-volatile memory cells of the first semiconductor die, receive an indication of a logical address from the memory controller (the logical address is for the memory operation), perform a logical address to physical address translation operation on the second semiconductor die using the received indication of the logical address resulting in a physical address for the non-volatile memory cells of the first semiconductor die, and perform the memory operation on the non-volatile memory cells using the physical address and the pathway pairs. In one set of example embodiments, the first semiconductor die is a memory die and the second semiconductor die is a control die. 
     One embodiment includes a method, comprising: a memory controller receiving a request to perform a memory operation for a first logical address; the memory controller determining that a local cache of logical to physical translations does not contain a translation for the first logical address; in response to determining that the local cache of logical to physical translations does not contain the translation for the first logical address, the memory controller sending a command to perform the memory operation and an indication of the first logical address to a control die that is bonded to a memory die; in response to receiving the first logical address from the memory controller, the control die translating the first logical address to a first physical address that corresponds to a physical location in a non-volatile memory structure in the memory die; and in response to receiving the command from the memory controller and in response to translating the first logical address to the first physical address, the control die performing the memory operation using the first physical address. 
     One embodiment is an apparatus comprising a memory controller and a first integrated memory assembly separate from the memory controller and in communication with the memory controller via a communication path. The integrated memory assembly comprises a memory die that includes a three dimensional memory structure of non-volatile memory cells and a control die bonded to the memory die. The control die has a first interface for communicating with the memory controller and a second interface for communicating with the memory die. The second interface is wider than the first interface. The memory controller is configured to receive commands from a host, perform logical address to physical address translation operations for at least a first subset of the received commands, instruct the control die to perform logical address to physical address translation operations for at least a second subset of the received commands and instruct the control die to perform memory operations for the received commands. The control die is configured to perform logical address to physical address translation operations for the second subset of the received commands and perform memory operations for the first subset of the received commands and the second subset of the received commands. 
     In one example implementation, the three dimensional memory structure stores logical address to physical address translation information; the memory controller includes a first L2P cache that is configured to temporarily store a first subset of the logical address to physical address translation information, the memory controller is configured to perform logical address to physical address translation operations for the first subset of the received commands using the first L2P cache; and the control die includes a second L2P cache that is configured to temporarily store a second subset of the logical address to physical address translation information, the control die is configured to perform logical address to physical address translation operations for the second subset of the received commands using the second L2P cache. 
     For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment. 
     For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., by way of one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element by way of intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them. 
     For purposes of this document, the term “based on” may be read as “based at least in part on.” 
     For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects. 
     For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects. 
     For purposed of this document, the terms “top” and “bottom,” “upper” and “lower” and “vertical” and “horizontal,” and forms thereof, as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the technology inasmuch as the referenced item can be exchanged in position and orientation. 
     In regard to the various flow charts depicted in the drawings, the steps of the flow chart can be performed in the order depicted, or the order of steps can be adjusted top suit the particular implementation. 
     The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the disclosed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.