Patent Publication Number: US-8970290-B2

Title: Method and apparatus for implementing slew rate control using bypass capacitor

Description:
REFERENCE TO RELATED APPLICATION 
     The present application is a continuation of U.S. patent application Ser. No. 13/630,778, filed Sep. 28, 2012, now pending, which is a continuation of U.S. patent application Ser. No. 13/272,950, filed Oct. 13, 2011, now U.S. Pat. No. 8,299,772, which is a continuation of U.S. patent application Ser. No. 12/572,952, filed Oct. 2, 2009, now U.S. Pat. No. 8,063,622. U.S. patent application Ser. No. 13/630,778 and U.S. Pat. Nos. 8,063,622 and 8,299,772 are hereby incorporated herein by reference. 
    
    
     BACKGROUND INFORMATION 
     1. Field of the Disclosure 
     The present invention relates generally to circuits in which a capacitive element is charged. More specifically, the present invention relates to charging of a capacitive circuit during a power-up condition. 
     2. Background 
     Power systems may be used for a multitude of purposes and applications. Power converters are typically electrical circuits that are coupled to a source of electrical energy, which applies a voltage across the input terminals of the power converter. Electrical circuits often require an initialization period in which a power source (e.g. a capacitor) is able to power up the circuitry after an input voltage is initially applied across the input terminals. A challenge for circuit designers is to gradually activate the power source, sometimes a supply capacitor, in the same manner over a wide range of input voltage conditions. For instance, without the ability to control the charging of a supply capacitor, which supplies power to the rest of the circuit at power up, some circuits may experience race conditions or other similar types of issues in which unknown or unwanted results may occur for circuit elements. In addition, if instantaneous input voltage is too high an overshoot condition may occur, in which case the supply capacitor is over charged due to the fast rate of charge of the supply capacitor and the slow response time of the circuit. This can cause other circuit elements to be exposed to high voltages that may be beyond their voltage rating. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
         FIG. 1  is a block diagram illustrating generally an example circuit in which the slew rate of a voltage across a capacitance circuit being charged during power up is set in accordance with the teachings of the present invention. 
         FIG. 2  is a schematic illustrating generally an example circuit in which the slew rate of the voltage across the capacitance circuit being charged during power up is set using a portion of the capacitance in accordance with the teachings of the present invention. 
         FIG. 3  shows waveforms associated with the example circuit of  FIG. 2  in which the slew rate of a voltage across a capacitance being charged during power up is controlled using a portion of the capacitance in accordance with the teachings of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Methods and apparatuses for implementing slew rate control of a capacitor element are described. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention. 
     Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale. 
     As will be discussed, an example slew rate control circuit in accordance with the teachings of the present invention sets the slew rate of a voltage across an integrated supply capacitor during power up mode in a high impedance integrated circuit using a portion of the capacitance of the supply capacitor. The control of the slew rate allows all internal nodes of the high impedance integrated circuit to power up in a controlled manner, which helps to avoid race conditions. 
     In one example, a slew rate control circuit in accordance with the teachings of the present invention may be used as part of an integrated circuit that is connected directly to an ac line voltage of, for example, 85Vac to 265Vac and will be exposed to high voltage instantly when ac power is applied. In one example, the slew rate control circuit can accommodate dc voltages that may be present on the ac line at the time of turn on so the dc voltage at a given time can be anywhere between 0 and 375 volts when power up is initiated. 
     To illustrate,  FIG. 1  is a block diagram illustrating generally an example integrated circuit  100  in which the slew rate of a voltage across a capacitance circuit being charged is set by controlling a rate of change of voltage across a portion of the capacitance of a capacitance circuit  105  in accordance with the teachings of the present invention. As shown in the depicted example, an integrated circuit  100  includes a regulator circuit  103 , which is coupled to regulate a supply voltage V SUPPLY  across capacitance circuit  105  during a normal operation mode of circuit  100 . In the example, regulator circuit  103  is coupled to receive the input voltage V IN , which in one example is a rectified dc line voltage. During operation, the regulator circuit  103  is coupled to charge a capacitance C SUPPLY  between a first node A and a second node B of the capacitance circuit  105 . As shown, a slew rate control circuit  107  is also coupled to regulator circuit  103  and capacitance circuit  105 . During operation, the slew rate control circuit  107  is coupled to set a slew rate (the change in voltage over change in time) of the supply voltage V SUPPLY  between the first and second nodes of the capacitance circuit  105  during a power up mode of circuit  100 . In power up mode, slew rate control circuit  107  receives a slew rate control current I SC  from capacitance circuit  105 . In particular, slew rate control circuit  107  limits the slew rate control current I SC  to control the slew rate across capacitance circuit  105 . 
     As will be discussed in greater detail below, one example of slew rate control circuit  107  sets the slew rate of supply voltage V SUPPLY  across capacitance circuit  105  between the first node A and second node B only during the power up mode of circuit  100 . The slew rate is the rate of change of the voltage across capacitance circuit  105 . The setting of the slew rate by slew rate control circuit  107  helps to ensure that the rest of the circuitry on integrated circuit  100  will start-up in a controlled manner without any race conditions in accordance with the teachings of the present invention. After the power up mode is complete, regulator circuit  103  regulates the supply voltage V SUPPLY  only during normal operation mode of circuit  100 . As shown in the depicted example, a power up signal PU  111  is coupled to be received by the slew rate control circuit  107  to indicate the power up mode of circuit  100 . 
     In one example, supply voltage V SUPPLY  that is regulated by regulator circuit  103  during normal operation mode is coupled to power other circuitry that is included in integrated circuit  100 . As shown in  FIG. 1 , the other circuitry in integrated circuit  100  may include for example controller circuitry  109 , which is coupled to supply voltage V SUPPLY  to receive operating power. It is appreciated that controller circuitry  109  is shown in  FIG. 1  for explanation purposes and that other types of circuitry that are powered by V SUPPLY  during normal operation mode may be included in integrated circuit  100  in accordance with the teachings of the present invention. 
       FIG. 2  is a schematic illustrating generally an example circuit  200  in which the slew rate of a voltage V SUPPLY  across a capacitance circuit  205  being charged is controlled during power up mode using a portion of the capacitance in capacitance circuit  205  in accordance with the teachings of the present invention. In one example, regulator  203 , capacitance circuit  205 , and slew rate controller  207  are all example implementations of regulator  103 , capacitance circuit  105 , and slew rate controller  107 , respectively, of integrated circuit  100  of  FIG. 1  in accordance with the teachings of the present invention. As shown in the depicted example, circuit  200  includes a regulator circuit  203 , which is coupled to regulate a supply voltage V SUPPLY  across a capacitance circuit  205  during normal operation. During operation, the regulator circuit  203  is coupled to charge capacitance circuit  205  between a first node  213  and a second node  236  with a supply current I S . As shown, a slew rate control circuit  207  is coupled to the regulator circuit  203  and the capacitance circuit  205 . 
     In one example, integrated circuit  200  may be included in a low power integrated circuit and slew rate control circuit  207  is used to control the slew rate (dv/dt) of a supply voltage, V SUPPLY  in the illustrated example, until it has reached a regulation threshold value V REF . During operation, the slew rate control circuit  207  is coupled to set the slew rate of supply voltage V SUPPLY  between the first and second nodes  213  and  236  during a power up mode of circuit  200 . 
     As shown in  FIG. 2 , capacitance circuit  205  includes a first electrical element coupled to a second electrical element. In the depicted example, the first and second electrical elements are illustrated as capacitor C F  coupled to capacitor C SC . Capacitor C F  has a first capacitance and capacitor C CS  has a second capacitance. In one example, the capacitance of the capacitance circuit  205  is equal to the capacitance of capacitor C F  during the power up mode. However, the capacitance of the capacitance circuit  205  is equal to a sum of the capacitance of capacitor C F  and the capacitance of capacitor C SC  during the normal operation mode. Thus, the overall capacitance of the capacitance circuit  205  is greater during normal operating mode than the overall capacitance of the capacitance circuit  205  during power up mode. 
     In one example, capacitors C F  and C CS  are both integrated on the silicon of integrated circuit in which circuit  200  is included and are chosen to keep the area of capacitance circuit  205  down while at the same time maintaining a low ripple of the supply voltage V SUPPLY  (e.g. 0.5 Volts peak-to-peak) during normal operation mode. In one example, the overall capacitance of capacitance circuit  205  is approximately 200 pF, where capacitor C F  is a 125 pF and capacitor C SC  is 75 pF. In one example, the current consumption of the entire integrated circuit in which circuit  200  is included is in the range of 15 to 20 uA. 
     As shown in the depicted example, slew rate control circuit  207  includes a switch T 3  and a resistor R SC  that are coupled to capacitance circuit  205 . Switch T 3  is switched off by slew rate control circuit  207  during power up mode, when supply voltage V SUPPLY  is less than a regulation voltage, and switch T 3  is switched on by slew rate control circuit  207  when supply voltage exceeds a regulation voltage. In operation switch T 3  continues to stay on during normal operation mode in accordance with the teachings of the present invention. As a result, the slew rate control circuit  207  is coupled to utilize a portion of the capacitance from capacitance circuit  205  during the power up mode. In particular, the portion of the capacitance that is utilized or borrowed from capacitance circuit  205  is the capacitance of capacitor C SC  as a result of switch T 3  being switched off. As shown, when switch T 3  is switched off, meaning T 3  is unable to conduct current, a first node of capacitor C SC  that was coupled to node  236  substantially through switch T 3  is now coupled to node  236  substantially through resistor R SC . However, slew rate control circuit  207  discontinues utilizing this portion of capacitance from the capacitance circuit  205  during normal operation mode. In particular, slew rate control circuit  207  discontinues utilizing or borrowing capacitor C SC  from capacitance circuit  205  in response to the supply voltage V SUPPLY  across capacitance circuit  205  between the first and second nodes  213  and  236  reaching a regulation threshold voltage. In one example, the regulation threshold voltage is a predetermined voltage of approximately 5.6 volts. Thus, in one example, switch T 3  is switched by slew rate control circuit  207  in response to the supply voltage V SUPPLY  in accordance with the teachings of the present invention. 
     As shown in  FIG. 2 , slew rate control circuit  207  also includes a latch  237  that is coupled to receive a power up signal PU  211 . In one example, latch  237  is a set-reset SR latch and latch  237  is set in response to PU signal through an inverter  241  as shown. In the example, during the ramp-up of the supply voltage V SUPPLY  at power up, PU signal will start “low” setting the latch  237  through inverter  241 , which forces switch T 3  to stay off. When switch T 3  is off, capacitor C SC  is utilized by slew rate control circuit  207  and is, in effect, borrowed from capacitance circuit  205 . 
     As shown in the depicted example, with switch T 3  switched off, capacitor C SC  and resistor R SC  are in series such that a portion of supply current I S , which is slew rate control current I SC  flows through capacitor C SC  and resistor R SC . In one example, resistor R SC  has a resistance of approximately 750 Kohms and capacitor C SC  has a capacitance of approximately 75 pF. As shown in the depicted example, the base terminals of bipolar transistors Q 1  and Q 2  are coupled to resistor R SC . Thus, the voltage drop across resistor R SC  while resistor R SC  and bipolar transistors Q 1  and Q 2  conduct current is limited to a V BE  base-emitter voltage drop of bipolar transistors Q 1  and Q 2 , which is equal to a diode drop or approximately 0.7 Volts. Thus, by selecting the resistance of resistor R SC , the current through resistor R SC  is set according to Ohm&#39;s law, which in this example is approximately 0.7 Volts divided by the resistance of resistor R SC . By setting slew rate control current I SC  through the resistor R SC  and capacitor C SC , the slew rate of charging capacitance circuit  205  during the power up mode is set in accordance with the teachings of the present invention. 
     Since the voltage at a node  255  is set by a base to emitter voltage drop of bipolar junction transistor (BJT) Q 2 , charge current I SC  can be set by setting value of resistor R SC . Since capacitor C SC  is governed by the following equation: 
     
       
         
           
             
               
                 ⅆ 
                 v 
               
               
                 ⅆ 
                 t 
               
             
             = 
             
               
                 I 
                 SC 
               
               
                 C 
                 SC 
               
             
           
         
       
     
     where dv/dt is the slew rate or rate at which the voltage increases across capacitance circuit  205 , I SC  is the slew rate control current that charges capacitor C SC , and C SC  is the capacitance value of the capacitor C SC . As shown, one variable to limit and/or lower dv/dt is the slew rate control current I SC  charging the capacitor C SC . In one example, capacitor C SC  and resistor R SC  are utilized by slew rate control circuit  207  to generate a slew rate limited ramp-up of the supply voltage V SUPPLY  across capacitance circuit  205  during power up mode. 
     The following description of the example illustrated in  FIG. 2  applies when input voltage terminal  270  is more positive than input voltage terminal  260 , as indicated by the polarity symbols at terminals  270  and  260 . When the input voltage has the opposite polarity, such that terminal  260  is more positive than input voltage terminal  270 , current source  229 A is substituted for current source  229 , resistor R 3 A is substituted for resistor R 3 , switch T 1 A is substituted for switch T 1 , switch T 2 A is substituted for switch T 2 , and supply current I SA  is substituted for supply current I S  in the following description. 
     In the illustrated example, regulator circuit  203  includes a switch T 1  coupled to be switched on and off to provide supply current I S  from current source  229 , which is coupled to the input voltage V IN  as shown. In one example, V IN  during power up mode can be an instantaneous dc voltage and current source  229  provides supply current I S  of approximately 0.2 to 0.5 mA. In one example, current source  229  may vary in response to input voltage V IN . When switch T 1  is switched on, supply current I S  from current source  229  is coupled to be received by the capacitance circuit  205  and controlled by slew rate control circuit  207  through node  213  as shown. When circuit  200  is initially turned on during the power up mode, switch T 1  is switched on during the power up mode, which enables the supply current I S  from current source  229  to begin charging capacitance circuit  205  to ramp-up the supply voltage V SUPPLY . 
     In one example, regulator circuit  203  also includes a comparator  225 , which is coupled to receive a voltage V X  representative of the supply voltage V SUPPLY  through a resistor divider formed with resistors R 1  and R 2 . As shown in the depicted example, comparator  225  is coupled to compare the received voltage representative of the supply voltage V SUPPLY  with a reference voltage V REG . In the example, reference voltage V REG  corresponds to the supply voltage V SUPPLY  being equal to the regulation threshold voltage V REF , such as for example approximately 5.6 volts. 
     When circuit  200  is initially powered up, comparator  225  senses that the supply voltage V SUPPLY  is less than the regulation threshold voltage, which results in comparator  225  causing switch T 2  to be switched off. When switch T 2  is switched off, the gate of switch T 1  is pulled high through resistor R 3  to turn on switch T 1 . When switch T 1  is switched on, supply current I S  from current source  229  charges the capacitance circuit  205  through a node  213  as shown. In addition, to control slew rate across capacitance circuit  205 , transistors Q 1  and Q 2  shunt excess current from current source  229  to ground  236 . In other words, the excess current from current source  229  that is not used to charge capacitor C SC  is directed to ground  236  through transistors Q 1  and Q 2 . 
     When comparator  225  senses that the supply voltage V SUPPLY  has reached the regulation threshold voltage, comparator  225  is coupled to turn switch T 2  on. When switch T 2  is switched on, the gate of switch T 1  is pulled low, which turns off switch T 1 . When switch T 1  is switched off, supply current I S  from current source  229  is no longer received by the capacitance circuit  205  at node  213 . In this manner, regulator circuit  203  provides regulation of supply voltage V SUPPLY  during a normal mode of operation. 
     In the example illustrated in  FIG. 2 , slew rate control circuit includes a current mirror formed with transistors T 4  and T 5 . Bipolar transistor Q 1  is coupled to transistor T 5 . As shown in the example, bipolar transistor Q 2  is coupled across transistors T 5  and Q 1 , with the bases of bipolar transistors Q 1  and Q 2  coupled to resistor R SC  as described previously. In the example, a current comparator  259  is formed with a current source  257  coupled to transistor T 4 . 
     As described above, when the supply voltage V SUPPLY  has reached the regulation threshold voltage V REF , switch T 1  is switched off such that the charge current from current source  229  is no longer received at node  213 . As a result, bipolar transistors Q 1  and Q 2  stop conducting current. At this point, a current comparator output signal CC  238  of the current comparator  259  will then become low, which indicates that the slew rate control circuit  207  is no longer active. Latch  237  is then reset by the low current comparator output signal CC  238  through inverter  239 , which allows transistor T 3  to be switched on. When transistor T 3  is switched on, slew rate control circuit  207  discontinues utilizing or borrowing capacitor C SC  and the capacitance of capacitor C SC  is therefore returned to capacitance circuit  205  in accordance with the teachings of the present invention. With transistor T 3  switched on and slew rate control circuit  207  deactivated, the overall capacitance of capacitance circuit  205  is now the sum of capacitor C F  and capacitor C SC . Furthermore, with transistor T 3  switched on integrated circuit  200  is switched from operation in a power up mode to a normal mode in which voltage supply V SUPPLY  is now regulated. 
     It is appreciated that by using the capacitance of capacitance circuit  205  as both a bypass capacitor to provide the supply voltage V SUPPLY  during normal operation mode of circuit  200  as well as for controlling the slew rate of the supply voltage V SUPPLY  across capacitance circuit  205  during power up mode, the total overall amount of silicon area of circuit  200  in the integrated circuit to implement capacitance circuit  205  and slew rate control circuit  207  is reduced if compared to a solution that uses independent capacitances for capacitance circuit  205  for and the slew rate control circuit  207 . 
       FIG. 3  shows waveforms associated with an example circuit in which the slew rate of a capacitance circuit being charged is set using a slew rate control circuit in accordance with the teachings of the present invention. 
     At time t 0 , it is assumed that the circuit is beginning to power up in power up mode  361  since supply voltage V SUPPLY  does not have any power to operate circuitry in circuit  200 . At this point, V SUPPLY  starts up at substantially zero volts and power up signal PU  211  is by default set, which indicates power up mode. When supply voltage V SUPPLY  reaches a first voltage threshold V TH1  at time t 1 , circuitry (e.g. transistors) in circuit  200  has sufficient voltage to operate. As shown, supply voltage V SUPPLY  is not controlled and increases without control until circuitry in circuit  200  has power to operate at time t 1 . In one example, voltage threshold V TH1  may be around 0.8 Volts. When supply voltage V SUPPLY  reaches a power up voltage threshold V PU  at time t 2 , power up signal PU  211  goes high to leave latch  237  in  FIG. 2  in the “set” condition, which keeps switch T 3  switched off. While supply voltage V SUPPLY  is below the regulation threshold voltage V REF , comparator  225  keeps switch T 2  switched off and switch T 1  switched on, which allows current source  229  to charge capacitance circuit  205  in a controlled manner. At this point, the slew rate of the supply voltage V SUPPLY  is controlled as discussed above with respect to  FIG. 2 . In one example, slew rate of supply voltage V SUPPLY  is controlled from a time t 1  to a time t 3 . The slew rate control current I SC  conducted through slew rate control circuit  207  is sensed by the current comparator  259 , which outputs the high current comparator output signal CC  238  from a time t 0  to a time t 3  as shown. 
     As supply voltage V SUPPLY  continues to charge, but before supply voltage V SUPPLY  reaches the regulation threshold voltage V REF , the power up signal PU  211  becomes high at time t 2 , which allows the latch  237  to be reset eventually when V SUPPLY  reaches the regulation threshold voltage V REF  at time t 3 . In one example, the power up signal PU  211  becomes high after V SUPPLY  has risen to about one-third of the regulation threshold voltage V REF  of, for example, 5.6 Volts, which indicates that V SUPPLY  has risen enough for all the circuitry to be in an active state. In one example, when the power up signal PU  211  is set to high, latch  237  will be ready to receive a reset request from signal CC  238 . Switch T 3  remains off to keep the slew rate of the supply voltage controlled, as discussed above with respect to  FIG. 2 . 
     At a time t 3 , supply voltage V SUPPLY  has risen to the regulation threshold voltage V REF  as shown. At this point, power up mode  361  is completed and normal operation mode  363  begins. Since supply voltage V SUPPLY  has now reached regulation threshold voltage V REF , comparator  225  causes switch T 2  to be switched on and switch T 1  is switched off at time t 3  as shown. With switch T 1  switched off due to V SUPPLY  reaching the regulation threshold voltage V REF , current comparator output signal CC  238  goes low at time t 3  as shown. With current comparator output signal CC  238  going low, latch  237  is reset, which causes switch T 3   345  to be switched on at time t 3  as shown. As a result, capacitor C SC  of the capacitance circuit  205  is now connected to ground and the capacitance of capacitor C SC  is now no longer utilized by the slew rate control circuit  207  in accordance with the teachings of the present invention. 
     Between times t 3  and t 4 ,  FIG. 3  shows that the switches T 1  and T 2  are switched on and off in the regulator circuit  203  to regulate supply voltage V SUPPLY  at the regulation threshold voltage V REF . In particular, a time t X  is the charge time of the capacitor circuit, and a time t Y  is the discharge time of the capacitor circuit. 
     The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention. 
     These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.