Patent Publication Number: US-8988902-B2

Title: Power converter controller IC having pins with multiple functions

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application Ser. No. 61/559,840, “Power Converter Controller IC Having Pins with Multiple Functions” filed Nov. 15, 2011, the subject matter of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Field of the Disclosure 
     The present disclosure relates to a power converter and, more specifically, to a power converter controller IC (integrated circuit) that has one or more IC pins with multiple functions. 
     2. Description of the Related Art 
     With the recent explosive growth in the number of electronic devices, the demand for power converters used as adapters or chargers for these electronic devices has also grown at a rapid rate. Power converters are typically controlled by power converter controller ICs. In particular, switched mode power converters are typically controlled by power converter controller ICs that control the on-times (T ON ) or off-times (T OFF ) of the switch in the power converters to regulate the output voltage and power of the power converters. 
     The power converter industry is under significant pressure to manufacture power converter controller ICs that are highly efficient but can also be manufactured at low cost. Because the manufacturing cost of ICs is highly dependent upon the die size, the number of pins, the packaging, and testing of the IC, it is desirable to reduce the number of pins of an IC. However, it is difficult to reduce the number of pins in conventional power converter controller ICs. In conventional power converter controller ICs, each pin of the IC is associated with a single, separate parameter or function and thus the IC requires as many pins as the number of parameters or functions supported by the IC. Thus, in general, reducing the number of pins in the power converter controller IC also reduces the number of parameters or functions supported by the controller IC and sacrifices the performance of the power converter. 
     SUMMARY 
     Embodiments of the present disclosure include a power converter controller IC that uses one or more IC pins to support a plurality of functions, such as configuration of an operational parameter supported by the controller IC and shutdown protection. In some embodiments, a plurality of functions may be supported by a single IC pin, thereby reducing the number of pins required in the controller IC and also reducing the manufacturing cost of the controller IC. Other embodiments of the controller IC share a comparison circuit among different pins and the different functions provided by those pins. Use of a shared comparison circuit further reduces the cost of manufacturing the controller IC without sacrificing the performance of the IC. 
     In one embodiment, the controller IC comprises an IC pin to connect to circuitry that is external to the controller IC. The controller IC also includes control circuitry that operates in different modes during distinct periods of time. During one mode (e.g., configuration mode), the control circuitry configures a parameter of the controller IC, such as cable drop compensation (CDC), based on the voltage at the IC pin. During a different mode (e.g., shutdown protection mode), the control circuitry provides shutdown protection by powering down the power converter based on the voltage at the same IC pin, thereby providing protection from a harmful condition such as an over-voltage or over-temperature condition. 
     In one embodiment, the controller IC comprises a second IC pin to connect to its own external circuitry. During a third mode of operation (e.g., another shutdown protection mode), the control circuitry also provides shutdown protection by powering down the power converter based on the voltage at the second IC pin. A comparison circuit compares the voltage from the first IC pin to a reference voltage during the first and second modes. The comparison circuit is also shared with the second IC pin and compares the voltage from the second IC pin to a reference voltage during a third mode. The control circuitry configures a parameter based on an output of the comparison circuit during the first mode, and provides shutdown protection based on an output of the comparison circuit during the second and third modes. 
     In one embodiment, the controller IC is part of a power converter that converts an input voltage to an output voltage. The power converter also includes a transformer coupled between the input voltage and the output voltage of the power converter and a switch configured to control current through the transformer according to on and off times of the switch. The controller IC controls the on times and off times of the switch. 
     The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The teachings of the embodiments of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. 
         FIG. 1  is an AC-DC flyback power converter with primary-side sensing, according to one embodiment. 
         FIG. 2A  illustrates the circuitry connected to the MULTI and SD pins of the power converter controller, according to one embodiment. 
         FIG. 2B  illustrates the circuitry connected to the MULTI and SD pins of the power converter controller, according to another embodiment. 
         FIG. 3  is a timing diagram for the different operating modes of the power converter controller, according to one embodiment. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The Figures (FIG.) and the following description relate to preferred embodiments of the present disclosure by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the claimed disclosure. 
     Reference will now be made in detail to several embodiments of the present disclosure, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein. 
       FIG. 1  illustrates AC-DC flyback power converter with primary-side sensing, according to one embodiment. Although the power converter of  FIG. 1  is an AC-DC flyback converter with primary side sensing of the feedback signals, it should be noted that the present disclosure is not limited to a flyback converter and that it can be applied to any type of power converter of any topology and any type of feedback sensing. The power converter includes, among other components, a bridge rectifier BR 1 , a transformer T 1 , a transistor switch Q 1 , a transistor switch Q 2 , an output rectifier diode D 1 , output filter capacitor C 7 , a power converter controller IC  100 , resistors R 1 , R 2 , capacitor C 2  and negative temperature coefficient (NTC) resistor R 3 . The transformer T 1  also includes a primary winding  110 , a secondary winding  112 , and an auxiliary bias winding  114 . 
     The rectifier BR 1  receives an input AC voltage and converts it into a full-wave rectified voltage for use in generating the output DC voltage. The power converter controller  100  controls the opening and closing of the switch Q 1  using an output control signal  102  in the form of pulses with on-times (T ON ) and off-times (T OFF ). The output control signal  102  may be a periodic pulse with a fixed period, or a pulse with its period varying as necessary. When the switch Q 1  is turned on because the pulse  102  is high during the on-time, energy is stored in the primary side windings of the transformer T 1  because the diode D 1  is reverse biased. When the switch Q 1  is turned off, the energy stored in the primary windings  110  of the transformer T 1  is released to the secondary side  112  of the transformer T 1  because the diode D 1  becomes forward biased. The diode D 1  rectifies the output voltage on the secondary windings  112  of the transformer T 1  and the capacitor C 7  filters the output voltage signal on the secondary windings  112  of the transformer T 1  for generating the output DC voltage. By controlling the period of time during which the switch Q 1  is on or off, i.e., the on-times (T ON ) and off-times (T OFF ), the power converter controller  100  can control the amount of power delivered to the DC output. 
     As shown in  FIG. 1 , the power converter controller IC  100  has only 8 pins: Output, Vcc, I SENSE , ASU (active start up), Gnd, MULTI, SD (shutdown) and V SENSE . In one embodiment, the IC controller  100  operates the MULTI pin in different modes at different periods of time such that the MULTI pin can serve different functions. During a configuration mode (e.g. at power on), the controller IC  100  senses the resistance of external resistors R 1  and R 2  through the MULTI pin to configure an operational parameter of the controller IC  100 . R 1  and R 2  may be configured by a user of the controller IC  100  to set the parameter to a desired configuration. During a shutdown protection mode (e.g., during or after startup), the controller IC  100  receives a divided down version of the voltage across the auxiliary windings N BIAS  of the transformer T 1  through the MULTI pin and uses this voltage for over-voltage protection (OVP). In some embodiments, the voltage of the MULTI pin may also serve as a feedback voltage (i.e. as V SENSE ) for regulating the DC output voltage. 
     Similarly, the SD pin may also serve different functions at different periods of time. During a configuration mode, the controller IC senses the value of external capacitor C 2  through the SD pin to configure a parameter of the controller IC  100 . The value of C 2  may be configured by a user of the controller IC  100  to set the parameter to a desired configuration. During a shutdown protection mode, the controller IC  100  senses the resistance of NTC resistor R 3  through the SD pin for providing over-temperature (OTP) protection or other forms of shutdown protection. 
     In the various shutdown modes, the voltages at the SD pin and the MULTI pins are thus used as indications of harmful conditions that could potentially damage the power converter or a load (not shown) of the power converter. If a protection condition is sensed, the IC controller  100  then provides shutdown protection by, for example, turning off switch Q 1  to power off the output Vout of the power converter. The MULTI pin and SD pin are explained in more detail in conjunction with  FIGS. 2A ,  2 B and  3 . 
     The power converter controller  100  receives a supply voltage  130  via the Vcc pin, and is connected to ground via the Gnd pin. The ASU pin provides a control signal for active start up functionality of the supply voltage  130 , and the pin may be left floating if active start up is not desired. When the AC input voltage is initially applied to the power converter, transistor Q 2  is switched on to charge the power supply voltage  130  through the transistor Q 2 . Once the power supply voltage  130  has reached a threshold level and the flyback operation of the power converter is enabled, the switch Q 2  is turned off and the power supply voltage  130  is maintained by a reflected secondary voltage on the auxiliary windings N BIAS  of the transformer T 1 . 
     The power converter controller  100  generates and outputs the pulse  102  for controlling the switch Q 1  via the Output pin. The I SENSE  and V SENSE  pins receive feedback signals for regulating the on and off times of switch Q 1 . Specifically, the I SENSE  pin senses the current flowing through switch Q 1 . The V SENSE  pin receives a divided-down version of the reflected secondary voltage on the auxiliary windings N BIAS  of the transformer T 1 . 
       FIG. 2A  illustrates the circuitry connected to the MULTI and SD pins of the power converter controller  100 , according to one embodiment.  FIG. 2A  shows only a portion of the power converter controller  100  circuitry, and other portions of the power converter controller  100  that are not specifically relevant for explaining the present disclosure are omitted in  FIG. 2A . As shown, the controller IC  100  includes a current source I 1 , a control logic  210 , several switches S 1 , S 2 , S 3  and S 4 , a comparator CMP, and a reference voltage supply  212 . 
     A current source I 1  can be connected to the MULTI pin through switch S 1 , or the current source I 1  can be connected to the SD pin through switch S 2 , depending on whether the switches S 1  and S 2  are switched on or off. Switches S 1  and S 2  thus allow the current source I 1  to be shared between the MULTI pin and the SD pin. Additionally, the non-inverting input of the comparator CMP can be connected to the MULTI pin through switch S 3  or the SD pin through switch S 4 , depending on whether the switches S 3  and S 4  are switched on or off. Switches S 3  and S 4  thus allow sharing of the comparator CMP between the MULTI pin and the SD pin. 
     The on/off status of each switch S 1 , S 2 , S 3  and S 4  is controlled by the digital control logic  210  via control signals  221 ,  223 ,  222  and  224 , respectively. In one embodiment, the switches are implemented with metal oxide semiconductor field effect transistors (MOSFET) or bipolar junction transistors (BJT). The digital control logic  210  controls the voltage level of reference voltage signal  205  produced by the reference voltage supply  212  via control signal  225 . The digital control logic  210  may also control the amount of current generated by the current supply I 1  via control signal  220 . 
     The comparator CMP compares the voltage  204  at its non-inverting input to the reference voltage  205  at the inverting input and generates an output signal  206  that indicates whether the voltage  204  is greater than reference voltage  205 . For example, if voltage  204  is higher than reference voltage  205 , the output  206  of comparator CMP may be a logic “1”. If voltage  204  is lower than reference voltage  205 , the output  206  of comparator CMP may be a logic “0.” During some modes of operation, the control logic  210  may configure a parameter of the control logic  210  based on the output  206  of the comparator. In other modes of operation, the control logic  210  may determine whether to power down the power converter based on the output  206  of the comparator. 
     When the power converter controller  100  is first powered on, the parallel resistance of R 1  and R 2  is used in setting an operational parameter of the digital control logic  210 . Specifically, during a configuration mode when the power converter controller  100  is first powered on, switch S 1  and S 3  are closed and switches S 2  and S 4  are open. Current source I 1  provides a current (e.g., a 100 μA-300 μA current) to the MULTI pin. Signal  102  is not driven and thus the N BIAS  winding is virtually shorted. As a result R 1  and R 2  are essentially connected in parallel to ground. The current provided to the MULTI pin thus generates a voltage at the MULTI pin that is proportional to the parallel resistance of R 1  and R 2 . This voltage is provided to the positive input of the comparator CMP as voltage  204  and compared to a reference voltage  205 . The reference voltage  205  produced by reference voltage supply  212  is ramped up in incremental steps until it exceeds the voltage  204 , upon which the output  206  of the comparator CMP switches logic states. Alternatively, the reference voltage  205  may be ramped down until it is lower than the voltage  204 . By ramping up and down the reference voltage  205 , the resistance range of the parallel resistors R 1  and R 2  can be identified (i.e. from the reference voltage  205  level that causes the comparator CMP output  206  to trip), and the digital control logic  210  then uses this information to set an operational parameter accordingly. 
     In one embodiment, an operational parameter refers to any configurable setting of the power converter controller  100  that affects the operation of the power converter controller  100 . Examples of configurable operational parameters include: cable drop compensation (CDC), shut-down temperature for OTP, shut-down voltage for OVP, maximum switching frequency of the power converter, length of a soft-start time and/or scheme and minimum no-load switching frequency of the power converter, etc. Any of these parameters can be set according to the external circuitry (e.g. R 1  and R 2 ), which allows the parameters of the controller IC to be tailored to the specific needs of the power converter. 
     CDC is a parameter that compensates for voltage drop over a cable (not shown) that is connected between the DC output of the power converter and a load device. A cable typically has an electrical resistance that causes a non-trivial amount of voltage to drop across the cable, especially as the current carried by the cable increases. CDC accounts for this voltage drop by increasing the output DC voltage level in an attempt to maintain a target voltage at the load device. The following table shows an example of how the combined resistance of R 1  and R 2  results in different settings for the CDC parameter: 
     
       
         
           
               
               
            
               
                   
                   
               
               
                   
                 Paralleled R1 and R2 Resistance (kΩ) 
               
            
           
           
               
               
               
               
               
               
            
               
                   
                 0-2.20 
                 2.37-3.21 
                 3.40-4.64 
                 4.87-6.65 
                 6.98-100 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
            
               
                 CDC setting 
                 1 
                 2 
                 3 
                 4 
                 5 
               
               
                 Compensation 
                 0 
                 75 
                 150 
                 300 
                 450 
               
               
                 amount (mV) 
               
               
                   
               
            
           
         
       
     
     This table represents the CDC at full load when the non-compensated DC output is 5.0 V. For different DC output voltages, the compensated voltage may be scaled up or down accordingly as needed. In other embodiments, there may be a greater or fewer numbers of possible CDC settings and the resistance ranges for each CDC setting may be different. 
     Maximum switching frequency of the power converter refers to the maximum frequency at which the output control signal  102  switches between T ON  and T OFF . The switching frequency in a switch-mode power supply is a critical parameter that relates to many key performance criteria of power supplies including cost, size, efficiency, Electromagnetic Interference (EMI), etc, which often conflict between each other. Allowing the switching frequency to be selectable by external circuitry provides a user with the flexibility to make the right trade-off between the performance criteria based on their own needs. 
     Soft-start time refers to the time allotted for soft-start, and soft-start scheme refers to a specific method of building up the output voltage during soft-start. Soft-start is a key requirement for power supplies. During soft-start, the IC controller  100  brings up the output voltage in a controlled fashion to limit the inrush current at startup, to prevent output voltage overshoot, and to reduce component stress when compared to a hard start. To meet the above requirements, a good soft-start scheme needs to be tailored for the power supply&#39;s output stage, such as the output capacitor C 7  and load (not shown). Allowing the soft-start time and/or soft-start scheme to be selectable by external circuitry provides a user with flexibility in designing the output stage. 
     No-load switching frequency refers to the switching frequency of the output signal  102  when the output of the power converter is not driving a load. The no-load switching frequency is also an important parameter and the setting of this parameter involves a trade-off between no-load standby power consumption and dynamic transient response. Allowing the no-load switching frequency to be selectable by external circuitry also provides flexibility in designing a power converter. 
     During a protection mode, the resistance of the external resistors R 1  and R 2  are used to provide OVP protection through the MULTI pin. The protection mode may occur after the configuration mode is complete and is distinct from the configuration mode. Specifically, S 2  and S 3  are now closed, and S 1  and S 4  are open in the protection mode. During off-times (T OFF ) of the switch Q 1  when energy is being transferred from the primary windings  110  to the secondary windings  112  of the transformer T 1 , the voltage at the MULTI pin corresponds to the DC output voltage reflected on the N BIAS  winding but scaled down by the turns ratio between the auxiliary winding N BIAS  and the secondary winding  112  of the transformer T 1 , and further scaled down by the voltage divider formed by resistors R 1  and R 2 . This voltage is fed to the comparator&#39;s CMP non-inverting input as voltage  204  and compared to the reference voltage  205 . The reference voltage signal  205  is set to a voltage level (e.g. in the range 1.0 V-2.0V) that should not be exceeded by the voltage  204  at the non-inverting input unless an over-voltage condition is present. If the voltage  204  at the non-inverting input exceeds the voltage level of the reference voltage signal  205 , the comparator CMP output  206  switches high to indicate an over-voltage condition and the digital control logic  210  powers down the power converter to prevent any further damage. 
     In one embodiment, to power down the power converter, the IC controller  100  turns off Q 1  so that transformer T 1  stops storing energy. The controller IC  100  still consumes current (e.g., several mA) because some functions blocks inside the IC are still active. The power supply voltage  130  at the Vcc pin voltage gradually drops because transformer T 1  stops transferring energy to both the output side and to the Vcc pin. When the supply voltage  130  drops below a certain voltage level (e.g. 5.5V), the IC  100  totally shuts down. Consequently, the supply voltage  130  can be charged up again until it reaches a Vcc startup threshold (e.g. 12V), and a new soft-start process begins. If the OVP condition persists, the IC  100  will shut down again and continue to power cycle until the fault is cleared. If the fault is cleared, the IC  100  completes the soft-start, and the IC  100  runs at a stable condition. 
     By controlling the state of the switches S 1 , S 2 , S 3  and S 4  and by operating in different modes, multiple functions such as configuration of operating parameters and OVP can thus be shared with a single MULTI pin. Using the MULTI pin to support multiple functions increases the functionality of the IC controller  100  without significantly increasing the manufacturing cost of the controller  100 . 
     Additionally, during another protection mode, the resistance of NTC R 3  is used to provide over-temperature protection through the SD pin. Specifically, during this other protection mode switches S 2  and S 4  are closed and switches S 1  and S 3  are open. The current provided by current source I 1  generates a voltage at the SD pin that is proportional to the resistance of R 3 . As the temperature increases, R 3  decreases in resistance because it is a NTC device. The decreased resistance also causes the voltage at the SD pin to decrease. The voltage at the SD pin is fed to the comparator&#39;s CMP non-inverting input as voltage  204  and compared to the reference voltage  205 . The reference voltage  205  is set to a voltage level (e.g. 1.0 V-2.0V) that should be higher than the voltage  204  at the non-inverting input unless an over temperature condition exists. If the voltage  204  falls below the reference voltage  205 , the output of the comparator  206  switches low to indicate an over-temperature condition and the digital control logic  210  powers down the power converter to prevent any further damage. 
     By changing the state of the switches S 3  and S 4 , the comparator CMP can thus be shared between the MULTI pin and the SD pin while maintaining the functionality provided by both the MULTI pin and the SD pin. Sharing the comparator CMP is beneficial for reducing the manufacturing cost of the IC controller  100  without affecting the performance of the controller  100 . 
     In one embodiment, the OTP of the controller IC  100  has hysteresis such that OTP is triggered at a high temperature (e.g. 150 degrees Celsius) and recovers at a lower temperature (e.g. 100 degrees Celsius). In other words, once OTP is triggered, the IC controller  100  will continue to shut down the power converter in subsequent power cycles until the temperature drops to an acceptable level. 
     In some embodiments, the SD pin can be used to provide general shutdown protection and is not just limited to providing OTP. R 3  can be any type of device so long as its resistance can vary and represent certain desirable protection features of the power converter, such as over/under voltage conditions, over current conditions, short circuit conditions, etc. Under a given protection tripping condition, the resistance of R 3  can drop to a level that causes the SD voltage to drop below the reference voltage  205 , thereby triggering a shutdown and protecting the power converter from damage. In other embodiments, any external circuitry that causes a voltage at the SD pin to change (i.e. rise or drop) during a fault condition can be used in place of R 3 . 
     In another embodiment, the SD pin is also a multi-function pin that is used to configure an operational parameter (e.g., CDC) at startup. During startup, switches S 2  and S 4  may be closed while switches S 1  and S 3  are open. Current source I 1  provides a current to the SD pin, which charges capacitor C 2 . As the capacitor C 2  charges, the voltage at the SD pin ramps up with a slope that is inversely proportional to C 2  at the beginning of the ramp. This voltage is fed to the comparator&#39;s CMP non-inverting input as voltage  204  and compared to the reference voltage  205 . The amount of time that passes before voltage  204  at the non-inverting input exceeds the reference voltage  205  is used by the digital control logic to set the parameter. After the parameter is configured, the SD pin is then used for OTP during a protection mode. 
       FIG. 2B  illustrates the circuitry connected to the MULTI and SD pins of the power converter controller  100 , according to another embodiment. The controller  100  in  FIG. 2B  is similar to the controller  100  from  FIG. 2A , but now includes an additional feedback signal  290  that provides a feedback voltage from the MULTI pin to the control logic  210 . The addition of the feedback signal  290  allows the MULTI pin to be used for V SENSE  functionality in addition to parameter configuration and OVP protection. Thus, the need for a separate V SENSE  pin is eliminated. 
     Specifically, the resistance of the external resistors R 1  and R 2  not only can be used to provide OVP protection, but also can provide the output voltage feedback information which can be used for the feedback loop control and regulation. This is because the voltage at the MULTI pin corresponds to the DC output voltage reflected on the N BIAS  winding but scaled down by the turns ratio between the auxiliary winding N BIAS  and the secondary winding  112  of the transformer T 1 , and further scaled down by the voltage divider formed by resistors R 1  and R 2 . The control logic  210  then uses the feedback signal (V SENSE )  290  to regulate the T ON  and T OFF  times of the switch Q 1 , thereby regulating the DC output level of the power converter. 
     The MULTI pin is thus similar to the V SENSE  pin of  FIG. 1  in terms of the ability to obtain the output voltage information for feedback control. Therefore, the MULTI pin and V SENSE  pin can be further simplified and combined as one pin. On the other hand, the embodiment shown in  FIG. 1  uses the MULTI pin and the V SENSE  pin separately to provide extra or supplemental voltage feedback and protection, which can enhance the reliability and robustness of the power converter under abnormal or fault conditions. In some embodiments, the MULTI pin may only be used for parameter configuration and V SENSE  functionality but not OVP protection. 
       FIG. 3  is a timing diagram of the power converter controller  100  according to one embodiment. As shown, the control logic  210  operates in different modes during distinct (i.e. non-overlapping) periods of time. At time T 0 , the supply voltage Vcc is off and the control logic  210  is in a Shutdown Mode. Prior to time T 1 , the supply voltage Vcc is powered on. After the supply voltage Vcc rises to a sufficient voltage level, the digital control logic  210  enters the Configuration Mode at time T 1 . S 1  is and S 3  are closed and S 2  and S 4  are open. During the Configuration Mode, the voltage at the MULTI pin is sensed and compared to the reference voltage  205  in order to set a parameter supported by the IC controller  100 . 
     At time T 2 , parameter configuration is complete and the control logic  210  starts toggling back and forth between the OTP Mode and the OVP Mode. During OTP Mode, S 2  and S 4  are closed and S 1  and S 3  are open. This configuration of switches allows the voltage at the SD pin to be compared to the reference voltage  205  to provide OTP if the temperature is too high, or to provide other forms of shutdown protection if a protection tripping condition is met. During OVP mode, S 2  and S 3  are closed and S 1  and S 4  are open. This configuration of switches allows the voltage at the MULTI pin to be compared to the reference voltage  205  to provide OVP by shutting down the power controller if the voltage is too high. Additionally, the voltage at the MULTI pin can be used as the output voltage feedback for control and regulation purpose. 
     In one embodiment, the OTP and OVP Modes can each be a number of cycles long, such as 8 to 32 or more, as determined by an internal clock of the control logic  210  as well as the power converter operations. 
     In embodiments where the SD pin but not the MULTI pin is used to set a parameter, the on/off status of the switches is reversed during the Configuration Mode. S 1  and S 3  would be open and S 2  and S 4  would be closed to allow a current to be injected into the SD pin. In embodiments where the SD pin and the MULTI pin are both used to set different parameters, there may be two separate Configuration Modes. During one Configuration Mode for setting a parameter according to a voltage at the MULTI pin, S 1  and S 3  are closed. During another Configuration Mode for setting a parameter according to a voltage at the SD pin, S 2  and S 4  are closed. 
     Upon reading this disclosure, those of ordinary skill in the art will appreciate still additional alternative structural and functional designs for a multi-function pin for a power converter controller IC through the disclosed principles of the present disclosure. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and components disclosed herein. Various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure disclosed herein without departing from the spirit and scope of the disclosure as defined in the appended claims.