Patent Publication Number: US-2019181086-A1

Title: Isolation device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 15/798,963, filed Oct. 31, 2017, which is a continuation of U.S. patent application Ser. No. 15/228,727, filed Aug. 4, 2016, now U.S. Pat. No. 9,812,389, which is a continuation-in-part of U.S. patent application Ser. No. 14/873,211, filed Oct. 2, 2015, now U.S. Pat. No. 9,793,203 and Ser. No. 14/872,692, filed Oct. 1, 2015, now U.S. Pat. No. 9,576,891, the entire disclosures of which are hereby incorporated herein by reference. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure is generally directed toward electronic isolation and devices for accommodating the same. 
     BACKGROUND 
     A galvanic isolator provides a way for transmitting signal from one electrical circuit to another electrical circuit in a control system when the two electrical circuits may otherwise be electrically isolated from one another. Usually the two electrical circuits operate at different voltages, and thus, are electrically isolated. For example, consider an application in which a 5V battery powered controller board is configured to control a motor circuit operating at 240V. In this example, the 240V motor circuit may be electrically isolated from the 5V controller circuit, while permitting the 5V controller circuit to send or receive signals from the 240V motor circuit. In another example involving a solid-state lighting system, a 240V Alternate Current (AC) power supply may be converted to two different Direct Current (DC) power domains. The two DC power domains are electrically isolated as there is no direct current path between the two DC domains, but there may be control signals that need to be communicated between the two power domains. In these applications, an isolator may be used to provide voltage and/or noise isolation while still permitting signaling and/or information exchange between the two circuit systems. 
     Galvanic isolators may be further categorized into opto-isolators, capacitive isolators, magnetic isolators and radio frequency based isolators depending on the technology used to electrically isolate the electrical circuits from one another. An opto-isolator may comprise an optical emitter and an optical receiver. Over time, degradation may occur and optical signals emitted from the optical emitter may degrade. Opto-isolators are usually for low frequency applications because photodiode as well as light-emitting diodes used as emitter in most capacitive isolators have built-in-capacitance that limits the transmission speed of opto-isolators. 
     Capacitive isolators ay not have the optical degradation issue of the opto-isolators. However, incorporating high voltage capacitor into a semiconductor die may be technically challenging. Capacitors that are fabricated by using conventional semiconductor process may not meet the requirement of high voltage tolerance. For example, opto-isolators may be able to meet isolation requirement such as breakdown voltage specification of 8 kV. However, typically most capacitive isolators fabricated under conventional CMOS process have breakdown voltage of 2 kV, which is relatively low compared to opto-isolators. 
     Most capacitive isolators available today have off-chip capacitors relying on capacitors outside a semiconductor package. Some of these capacitive isolators may have capacitors arranged in series in order to meet the breakdown voltage specification. However, having capacitors in series also means floating electrical node that is not testable, and may be susceptible to noise. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is described in conjunction with the appended figures, which are not necessarily drawn to scale: 
         FIG. 1  illustrates an illustrative block diagram of an isolation device according to embodiments of the present disclosure; 
         FIG. 2A  illustrates a diagrammatic cross sectional view of an isolation device according to embodiments of the present disclosure; 
         FIG. 2B  shows a diagrammatic top view of the isolation device shown in  FIG. 2A ; 
         FIG. 2C  illustrates an exemplary diagram showing operation of an iso-potential ring in accordance with embodiments of the present disclosure; 
         FIG. 2D  illustrates various implementations of the second plate of the isolation device shown in  FIG. 2A ; 
         FIG. 2E  illustrates an exemplary diagram showing how the trench intercepts a residue material in accordance with embodiments of the present disclosure; 
         FIG. 2F  illustrates a diagrammatic top view of a first alternative trench having a plurality of curvature trench members; 
         FIG. 2G  illustrates a diagrammatic top view of a second alternative trench having a plurality of linear trench members; 
         FIG. 2H  illustrates a diagrammatic cross-sectional view of a third alternative trench that terminates at a topmost interconnect metal layer; 
         FIG. 2I  illustrates a diagrammatic cross-sectional view of a fourth alternative trench that terminates at an edge stop layer; 
         FIG. 2J  illustrates a diagrammatic cross-sectional view of a fifth alternative trench that is filled partially by a passivation layer; 
         FIG. 3  illustrates a diagrammatic cross sectional view of an isolation device with an enhanced isolation layer with a substantially flat top surface; 
         FIG. 4  illustrates a diagrammatic cross sectional view of an isolation device having double passivation layers; 
         FIG. 5  illustrates a diagrammatic cross sectional view of an isolation device with a high isolative material; 
         FIG. 6A  illustrates a diagrammatic view of a first isolation system with two semiconductor dies; 
         FIG. 6B  illustrates a first diagrammatic view of a trench filled with isolation materials; 
         FIG. 6C  illustrates a second diagrammatic view of a trench filled with isolation materials; 
         FIG. 6D  illustrates a third diagrammatic view of a trench filled with isolation materials; 
         FIG. 7  illustrates a diagrammatic cross sectional view of a second isolation system with circuits operating in different voltage ranges; 
         FIG. 8  illustrates a diagrammatic cross sectional view of an isolation capacitor with at least one trench; 
         FIG. 9  illustrates a diagrammatic cross sectional view of an isolation capacitor with an isolation material with a thick portion; 
         FIG. 10  illustrates a flow chart showing a first method of operating a capacitive isolator with an enhanced isolation layer; 
         FIG. 11  illustrates a flow chart showing a method of operating a capacitive isolator with a trench; 
         FIG. 12  is a schematic block diagram depicting an isolation system in accordance with embodiments of the present disclosure; 
         FIG. 13  is a schematic block diagram depicting details of a capacitive isolator in accordance with embodiments of the present disclosure; 
         FIG. 14  is a cross-sectional view of a capacitive isolator construction in accordance with embodiments of the present disclosure; 
         FIG. 15  depicts a first intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 16  depicts a second intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 17  depicts a third intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 18  depicts a fourth intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 19  depicts a fifth intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 20  depicts a sixth intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 21  depicts a seventh intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 22  depicts a eighth intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 23  depicts a ninth intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 24  depicts a tenth intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 25  depicts a eleventh intermediate device in accordance with embodiments of the present disclosure; 
         FIG. 26  depicts a final isolation device in accordance with embodiments of the present disclosure; 
         FIG. 27  is a flowchart depicting a method of manufacturing an isolation device in accordance with at least some embodiments of the present disclosure; 
         FIG. 28A  is a top view of an isolation system in accordance with embodiments of the present disclosure; 
         FIG. 28B  is a side view of the isolation system depicted in  FIG. 28A ; 
         FIG. 28C . is a cross-sectional detailed view of the IC chip depicted in  FIG. 28B ; and 
         FIG. 29  depicts an isometric view and cross-sectional detailed view of an isolation device in accordance with embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The ensuing description provides embodiments only, and is not intended to limit the scope, applicability, or configuration of the claims. Rather, the ensuing description will provide those skilled in the art with an enabling description for implementing the described embodiments. It being understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the appended claims. 
     Various aspects of the present disclosure will be described herein with reference to drawings that are schematic illustrations of idealized configurations. As such, variations from the shapes of the illustrations as a result, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the various aspects of the present disclosure presented throughout this document should not be construed as limited to the particular shapes of elements (e.g., regions, layers, sections, substrates, etc.) illustrated and described herein but are to include deviations in shapes that result, for example, from manufacturing. By way of example, an element illustrated or described as a rectangle may have rounded or curved features and/or a gradient concentration at its edges rather than a discrete change from one element to another. Thus, the elements illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the precise shape of an element and are not intended to limit the scope of the present disclosure. 
     It will be understood that when an element such as a region, layer, section, substrate, or the like, is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will be further understood that when an element is referred to as being “formed” or “established” on another element, it can be grown, deposited, etched, attached, connected, coupled, or otherwise prepared or fabricated on the other element or an intervening element. 
     Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top” may be used herein to describe one element&#39;s relationship to another element as illustrated in the drawings. It will be understood that relative terms are intended to encompass different orientations of an apparatus in addition to the orientation depicted in the drawings. By way of example, if an apparatus in the drawings is turned over, elements described as being on the “lower” side of other elements would then be oriented on the “upper” side of the other elements. The term “lower” can, therefore, encompass both an orientation of “lower” and “upper” depending of the particular orientation of the apparatus. Similarly, if an apparatus in the drawing is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The terms “below” or “beneath” can therefore encompass both an orientation of above and below. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure. 
     As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The term “and/or” includes any and all combinations of one or more of the associated listed items. 
     Referring now to  FIGS. 1-29 , various configurations of isolation systems, isolators, isolation devices, and intermediate isolator configurations are depicted and described. Although some of the isolation systems depicted in the figures correspond to isolation systems of components thereof at intermediate stages of manufacturing (or in disassembled states), one of ordinary skill in the art will appreciate that any of the intermediate products herein can be considered an isolator or isolation system without departing from the scope of the present disclosure. In some embodiments, the isolators described herein may be incorporated into any system which requires current and/or voltage monitoring, but is susceptible to transients. In some embodiments, the isolation system in which an isolator described herein is rated to operate at about 5 kV, 10 kV, or more. Stated another way, the input side (e.g., a high-voltage side) of the isolator or isolation system may be directly connected to a 5 kV, 10 kV, 15 kV or greater source without damaging the isolator or any electronic devices attached to the output side (e.g., a low-voltage side) of the isolator. Accordingly, an isolation system which employs one or more of the isolators disclosed herein may be configured to operate in high-voltage or high-current systems but may also be configured to separate the high-voltage or high-current systems from a low-voltage or low-current system. 
       FIG. 1A  depicts an illustrative block diagram of an isolation device 
       100 . The isolation device  100  may be implemented in a semiconductor die. The isolation device  100  may be operable to isolate a first circuit  172  from a second circuit  174  while allowing a first signal  170  to be transmitted from the first circuit  172  to the second circuit  174 . The isolation device  100  may comprise a substrate  110 , a plurality of metal layers  150 , an isolation material  140 , a first plate  122 , a second plate  125 , at least one trench  160 , and a passivation layer  148 . 
     The substrate  110  may have a first surface  112  facing the first plate  122  and the second plate  125 . The substrate  110  may be a thin silicon wafer in which the first surface  112  may be further processed to form one or more integrated circuits. The plurality of metal layers  150  may be disposed adjacent to the first surface  112 . The plurality of metal layers  150  may comprise a first interconnect metal layer  151  and a topmost metal layer  159 . The plurality of metal layers  150  may comprise additional metal layers other than the first interconnect metal layer  151  and the topmost metal layer  159 . The plurality of metal layers  150  may comprise between three to eight metal layers, but in the future, there may be even more metal layers introduced. Each of the plurality of the metal layers  150  may be substantially parallel to the first surface  112 . The first interconnect metal layer  151  may be positioned closest to the first surface  112  measuring along a first axis  199 . The first axis  199  may be substantially perpendicular to the first surface  112 . The first interconnect metal layer  151  may be positioned at a first distance d 1  away from the first surface  112 . 
     The topmost metal layer  159  may be positioned furthest from the first surface  112  measuring along the first axis  199 . The topmost metal layer  159  may be positioned at a topmost distance dt away from a first adjacent metal layer formed nearest to the topmost metal layer  159  measuring along the first axis  199 . The first adjacent metal layer may be the first interconnect metal layer  151  if there is no other additional metal layer. The topmost distance dt may be at least three times the first distance d 1 . In the embodiment shown in  FIG. 1 , the first distance d 1  may be approximately one micrometer and the topmost distance dt may be at least four micrometers. In one embodiment the topmost distance dt may be at least ten micrometers. In yet another embodiment, the topmost distance dt may be more than twelve micrometers. The topmost distance dt of the isolation device  100  may be one parameter that may eventually determine the breakdown voltage of the isolation device  100 . 
     The isolation distance di may be defined as the distance between the first plate  122  and the second plate  125  as illustrated in  FIG. 1 . The isolation distance di may be approximately equal to the topmost distance dt for an isolation device  100  fabricated using only two metal layers  150  with the bottom metal layer  151  being used to make the second plate  125 . However, in most cases, the topmost distance dt is different from the isolation distance di as there may be more additional interconnect metal layer as illustrated in subsequent embodiments. The topmost distance dt may contribute primarily to the determination of the isolation distance di. 
     The isolation distance di, the first distance d 1 , and the topmost distance dt shown in the illustrative block diagram may be substantially uniform. However, in some embodiments, the plurality of metal layers  150 , the first plate  122  and the second plate  125  may not be completely flat, and thus, the isolation distance di, the first distance d 1 , and the topmost distance dt may differ depending on the location where the measurement is taken. 
     However, the difference may be too small and insignificant. For avoidance of doubt, the isolation distance di, the first distance d 1 , and the topmost distance dt for actual physical devices would be the average effective distance measured per the definition defined above. 
     The isolation material  140  may surround the plurality of metal layers  150  but expose a surface  123  of the topmost metal layer  159 . The isolation material  140  may comprise one or more passivation layers  148  covering the topmost surface  123  of the first plate  122 , as well as all surfaces of all other metal layers  150  exposed outside the isolation device  100 . For example, in the embodiment shown in  FIG. 1 , the topmost surface  123  of the first plate  122  is exposed and configured to receive a first wire bond (not shown). In other words, the first plate  122  may be a bond pad configured to be exposed externally so as to receive a wire bond or a bond ball for external electrical connections. The isolation device  100  may comprise additional plurality of bond pads exposed outside the isolation device  100  for receiving wire bonds or solder balls. The additional plurality of bond pads may be a portion of the topmost metal layer  159  as illustrated in the embodiment shown in  FIG. 3A . Alternatively, the isolation device  100  may comprise additional plurality of bond pads formed using a metal layer other than the topmost metal layer  159  as shown in the embodiment illustrated in  FIG. 2A . 
     As shown in  FIG. 1 , a portion of the isolation material  140  may be sandwiched between the first plate  122  and the second plate  125 . The isolation material  140  may allow capacitive coupling signals  171  to travel between the first plate  122  and the second plate  125  enabling communication between the first circuit  172  and second circuit  174  even though the first circuit  172  and second circuit  174  are electrically isolated from one another. 
     The isolation material  140  may comprise a plurality of isolation layers such as a first isolation layer  141 , the enhanced isolation layer  149 , and the passivation layer  148 . The enhanced isolation layer  149  may be disposed adjacent to the topmost metal layer  159 . The enhanced isolation layer  149  may be substantially thicker than each of all other plurality of isolation layers  141 . The enhanced isolation layer  149  may comprise high isolation materials such as polyimide. The isolation material  140  may also comprise silicon dioxide or silicon nitride in substantial quantities without departing from the scope of the present disclosure. 
     The enhanced isolation layer  149  may be the primary layer of the isolation material  140  providing electrical isolation between the first plate  122  and the second plate  125 . While not intended, depositions of electrically conductive impurities and residue materials may exist between the plurality of isolation layers  141 . For example such depositions of residue materials  137  may be disposed between the first isolation layer  141  and the enhanced isolation layer  149  as shown in  FIG. 1 . This may be highly undesirable as the residue materials  137  may provide an unwanted electrical path. When a high electric field is applied across the capacitive element between the first plate  122  and the second plate  125 , these unwarranted electrical paths may subsequently breakdown and may damage the isolation device  100 . One way to break such unwanted electrical breakdown path is by having the at least one trench  160  to intercept the unwarranted electrical path and to cut off the potential leakage current that may flow through the residue materials  137 . 
     The at least one trench  160  may extend at least partially through the isolation material  140  in a direction substantially perpendicular to the first surface  112 . The at least one trench  160  may be positioned adjacent to the first plate  122  and the second plate  125 . The at least one trench  160  may be looping around the first plate  122  planarly on a plane parallel to the substrate  110 . In this way, the at least one trench  160  may interrupt and break any potential break-down path caused by the residue materials that exist on the plane between the isolation layers  141 ,  149 . The at least one trench  160  may extend through the enhance isolation layer  149  so as to interrupt electrical paths that may exist between the enhanced isolation layer  149  and the passivation layer  148 . 
     The isolation device  100  may comprise at least two circuits  172 ,  174  such as the first circuit  172  and the second circuit  174  that may be electrically isolated from one another. For example, the first circuit  172  may comprise the first plate  122 , and the second circuit  174  may be all other portions of the isolation device  100  outside the first plate  122 . On many occasions, the first circuit  172  and the second circuit  174  may be connected to different power sources, different ground or reference voltages, or to different regulated power supply nodes that may originate from a single power supply. The different power sources and the different regulated power nodes may have different operating voltages. For example, the first signal  170  may be coupled to the first plate  122 . The first signal  170  may operate within a first voltage range V 1 . The second plate  125  may be configured to be biased within a second voltage range V 2 . The first voltage range V 1  may be substantially larger than the second voltage range V 2 . 
     The first signal  170  may be transmitted from the first circuit  172  to the second circuit  174  through a coupling device formed using the first plate  122  and the second plate  125 . For example, the first plate  122  and the second plate  125  may form an isolation capacitor in which the first signal  170  may be converted into a capacitive coupling signal  171 . The first plate  122  may form a first capacitive element, whereas the second plate  125  may form the second capacitive element. The first plate  122  may be a portion of the topmost metal layer  159 . The first plate  122  may be coupled directly to the first circuit  172  so as to receive the first signal  170 . For example, the first plate  122  may be wire bonded or electrically connected to other portions of the first circuit  172 . The first plate  122  may be isolated from all other plurality of metal layers  150 . 
     The second plate  125  may be disposed adjacent to the first plate  122  but be distanced away and electrically isolated from the first plate  122 . The second plate  125  may be configured to indirectly receive the first signal  170  via a capacitive coupling between the second plate  125  and the first plate  122 . The second plate  125  may be electrically connected to the second circuit  174 . For example, the second plate  125  may be coupled electrically to a via and subsequently electrically coupled to the second circuit  174  through the plurality of metal layers  150 . 
     The first plate  122  and the second plate  125  may be positioned in parallel to each other. The first plate  122  and the second plate  125  may be substantially in parallel such that the second plate  125  may be configured to receive the first signal  170  through the capacitive coupling signal  171  without receiving an electrical current directly from the first circuit  172 . The first plate  122  may be spaced apart from the second plate  125  through the isolation material  140 . 
     The first plate  122  and the second plate  125  may be made from highly electrically conductive materials such as one of the plurality of metal layers  150 . However, the first plate  122  and the second plate  125  may be formed using other materials such as poly-silicon, or highly doped diffusion layers. 
     The block diagram shown in  FIG. 1  is illustrated without associating the isolation device  100  with a specific arrangement, or being fabricated using a specific process. Subsequent embodiments may show drawings illustrating the similar device using a specific arrangement or using a specific process. All components shown in subsequent embodiments that are in common with the isolation device  100  may share similar characteristics or may be identical. 
       FIG. 2A  shows a diagrammatic cross sectional view of an isolation device  200 .  FIG. 2B  shows a diagrammatic top view of the isolation device  200  shown in  FIG. 2  without showing all layers of the isolation device  200  to keep the top view simple. The isolation device  200  may be made using a CMOS manufacturing process, a bipolar process or a bi-CMOS process. The embodiment shown in  FIG. 2A  primarily illustrates back-end processed layers that may be used in any of the process illustrated above. Back-end process usually refers to processing of metal layers  250  and all subsequent process steps in manufacturing a semiconductor die. While terminology of the layers may follow those in CMOS process, the front-end layers (prior to forming metal layers  250 ) may be applicable to bipolar process, a bi-CMOS process or any other semiconductor integrated circuit manufacturing process. 
     Referring to  FIGS. 2A-2B , the isolation device  200  may comprise a substrate  210 , a plurality of metal layers  250 , a first plate  222 , a second plate  225 , an iso-potential ring  229 , an isolation zone  226 , an isolation material  240 , at least one trench  260 , and a passivation layer  248 . The iso-potential ring  229 , the at least one trench  260  and the isolation zone  226  may be optional. 
     The number of layers of the plurality of metal layers  250  may depend on the technology chosen for the isolation device  200 . For example, the isolation device  200  may be implemented in a six metal layers process may have a total of six metal layers. If implemented in a four metal layers process, the plurality of metal layers  250  may have a total of four metal layers. As shown in  FIG. 2A , the isolation material  240  may comprise the passivation layer  248 , a plurality of isolation layers  241 - 246  and a neck portion of isolation layer  249 . Each of the isolation layers  241 - 246  and the neck portion  249  may separate each of the metal layers  250 . In other words, each of the plurality of isolation layers  241 - 246  may be sandwiched between two adjacent metal layers of the plurality of metal layers  250 , or between the first interconnect metal layer  251  and the substrate  210 . 
     The plurality of metal layers  250  and the plurality of isolation layers  241 - 246  may be formed layer-by-layer, one on top of another. This process may also be referred as multi-metallization structure. The neck portion  249  may be disposed on the topmost isolation layer  246  on an area adjacent to the first plate  222  but not covering the entire isolation device  200 . As illustrated in  FIG. 2A , the neck portion  249  may be protruding in a direction substantially along a first axis  299  that is substantially perpendicular to the substrate  210 . 
     The plurality of isolation layers  241 - 246  may comprise inter-metal dielectric layers (referred hereinafter as “IMD”), or inter level dielectric (referred hereinafter as “ILD”). IMD or ILD is a dielectric material used to electrically separate closely spaced interconnect lines arranged in several levels (multilevel metallization) in an advanced integrated circuit. IMD or ILD may feature low dielectric constant k as close to 1 as possible to minimize capacitive coupling between adjacent metal lines. Each of the plurality of isolation layers  241 - 246  may be made from silicon dioxide, silicon nitride or any other similar isolative material. 
     In the embodiment shown in  FIG. 2A , the plurality of metal layers  250  may comprise the topmost metal layer  259  and a plurality of interconnect metal layers  251 - 256  as illustrated on the right hand side of the diagrammatic cross-sectional view. The plurality of interconnect metal layers  251 - 256  may be primarily configured to electrically interconnect various portions of the isolation device  200  that are isolated from the first plate  222 . Therefore, the plurality of interconnect metal layers  251 - 256  may be electrically interconnected to each other, or to any lower layer of the substrate  210  through a via. 
     The plurality of interconnect metal layers  251 - 256  may comprise the first interconnect metal layer  251  and a topmost interconnect metal layer  256 . The first interconnect metal layer  251  may be the metal layer positioned closest to the substrate  210 . The topmost interconnect metal layer  256  may be the metal layer positioned closest to the topmost metal layer  259 . There may be additional interconnect metal layers  252 - 255  between the first interconnect metal layer  251  and the topmost interconnect metal layer  256 . 
     For example, the plurality of interconnect metal layers  251 - 256  may further comprise a second interconnect metal layer  252 . The second interconnect metal layer  252  may be disposed adjacent to the first interconnect metal layer  251  such that the first interconnect metal layer  251  may be sandwiched between the second interconnect metal layer  252  and the substrate  210 . The plurality of interconnect metal layers  251 - 256  may further comprise a third interconnect metal layer  253  disposed adjacent to the first interconnect metal layer  251  such that the second interconnect metal layer  252  is sandwiched between the first interconnect metal layer  251  and the third interconnect metal layer  253 . The second plate  225  may be formed by a portion of the second interconnect metal layer  252 , the third interconnect metal layer  253  or any other layers of the plurality of interconnect metal layers  254 - 256 . 
     Optionally, the topmost metal layer  259  may be a layer dedicated for isolation purposes. For example, the topmost metal layer  259  may be configured to form the first plate  222  of the isolation device  200  that is not electrically interconnected to other portions of the isolation device  200 . The plurality of interconnect metal layers  251 - 256  may be electrically isolated from the topmost metal layer  259 . Each of the plurality of interconnect metal layers  251 - 256  may be connected to at least one other layer of the plurality of interconnect metal layers  251 - 256  but isolated from the topmost metal layer  259 . The topmost metal layer  259  is chosen to form the top plate  222  that comprise a surface  223  so as to wire bond the top plate  222  to an external circuit. As shown in  FIG. 2A , the surface  223  is connected to a bond ball  276  and a wire bond  277 . 
     The isolation material  240  may comprise an enhanced isolation layer  249 . The enhanced isolation layer  249  may have higher isolation capabilities in that the enhanced isolation layer  249  may have at least one of the following properties. First, the enhanced isolation layer  249  may have substantially higher thickness. Second, the enhanced isolation layer  249  may be made or mixed with highly isolative material such as polyimide. 
     The topmost interconnect metal layer  256  may comprise at least one surface  257  for external electrical connections similar to that of the surface  223  of the topmost metal layer  259 . For example, the surface  223  of the topmost metal layer  259  and at least one surface  257  of the topmost interconnect metal layer  256  may be exposed without being covered by the isolation material  240  so as to receive wire bonds  278  respectively. The surface  223  of the topmost metal layer  259  and the at least one surface  257  may be electrically connected to different external circuits. 
     The first interconnect metal layer  251  may be positioned at a first distance d 1  away from the substrate  210 . The plurality of interconnect metal layers  251 - 256  may be positioned at respective distances d 2 -d 6  away from an adjacent metal layer respectively as shown in  FIG. 2A . The distances d 1 -d 6  may be approximately between 0.8-1.6 microns. In the embodiment shown in  FIG. 2A , the first distance d 1  may be relatively lower than the respective distances d 2 -d 6 . Each of the plurality of interconnect metal layers  251 - 256  may be positioned at equal distance from each other and hence each of the distances d 2 -d 6  may be approximately equal to an average value davg. For example, the first distance d 1  may be approximately 1 micron but each of the distances d 2 -d 6  may be approximately 1.5 micron. 
     As shown in  FIG. 2A , the topmost metal layer  259  may be positioned at a topmost distance dt away from the topmost interconnect metal layer  256 . The height of the neck portion  249  may have a height that is approximately the topmost distance dt. The topmost distance dt may be at least three times the average value davg of the respective distances d 2 -d 5 . The topmost distance dt may be at least four times the first distance d 1 . 
     The distance dc between the first plate  222  and the second plate  225  may be the sum of the topmost distance dt the distances d 2 -d 6  as illustrated by the formula below: 
         dC=dt+d 2 +d 3 +d 4 +d 5 +d 6 
     If the second plate  225  is implemented using other layers, the formula may need to be adjusted accordingly by adding or taking out the relevant distances d 1 -d 6  between the plurality of interconnect metal layers  251 - 256 . For example, if the second plate  225  is implemented using the second interconnect metal layer  252 , the distance dc between the first plate  222  and the second plate  225  may be the sum of the topmost distance dt the distances d 3 -d 6  as illustrated by the formula below: 
         dC=dt+d 3+ d 4+ d 5+ d 6 
     The breakdown voltage of the isolation device  200  may depend on the value of dc, and therefore, may be theoretically adjusted through any of the parameters d 2 -d 6  and dt. However, practically the topmost distance dt may be a more effective parameter to adjust compared to others because the topmost layer of isolation material  249  is next to the first plate  222 . In addition, while adjusting the topmost distance dt has no effect on the entire isolation device  200 , adjusting other parameters such as the d 1 -d 6  may affect parasitic capacitances of wire traces and affect performance of other circuitry. Another reason that adjusting the topmost distance dt may be more effective is that a residue material  237  may be formed under the neck portion  249  of the isolation material  240  and not within the isolation material  240 . As explained in subsequent paragraph, the residue material  237  may weaken the breakdown voltage of the isolation device  200 . 
     The passivation layer  248  may be configured to cover the substrate  210 , the plurality of metal layers  250  and the first plate  222 . The passivation layer  248  may be configured to expose an external surface  223  of the first plate  222  and at least one additional portion of the topmost metal layer  259  so as to receive at least one of a solder ball  276  and a wire bond  277 . In another embodiment, the passivation layer  248  may extend planarly in parallel with the topmost isolation layer  246  without covering the neck portion  249  of the isolation material. The neck portion  249  may be disposed on the passivation layer  248  but covered by an additional passivation layer. 
     Referring to  FIG. 2A  and  FIG. 2B , the topmost metal layer  259  may comprise the iso-potential ring  229  disposed around the first plate  222 . The iso-potential ring  229  may be electrically isolated from other portions of the topmost metal layer  259  and the topmost interconnect metal layer  256 . In addition, the iso-potential ring  229  may be disposed at a predetermined fixed distance from the first plate  222  measuring horizontally from the plate perimeter  292  of the first plate  222 . The iso-potential ring  229  may be disposed completely surrounding the first plate  222 . For example, the first plate  222  may have a plate perimeter  292 . The iso-potential ring  229  may be disposed at a predetermined distance away from the plate perimeter  292  and hence a ring-shape iso-potential ring  229  may be formed. The iso-potential ring  229  may be located approximately more than 5 microns from the plate perimeter  292  of the first plate  222 . The iso-potential ring  229  may be concentric with the first plate  222 . The at least one trench  260  may be surrounding the iso-potential ring  229  as shown in  FIG. 2B . 
     In the embodiment shown in  FIG. 2A , the iso-potential ring  229  may be disposed adjacent the first plate  222  on a plane that is substantially parallel to the substrate  210 . In another embodiment, the iso-potential ring  229  may be a portion of other metal layers  251 - 256  forming a ring shape on a plane that may be vertically distance away from the first plate  222 . In yet another embodiment, the isolation device  200  may comprise an additional iso-potential ring disposed on one of the interconnect metal layers  251 - 256  in addition to the iso-potential ring  229  formed using the topmost metal layer  259 . 
     The iso-potential ring  229  may be configured to evenly distribute the electric field generated from the first plate  222  to avoid creating a breakdown path resulted from neighboring metal layers  251 - 256 . This may be explained through an example in  FIG. 2C .  FIG. 2C  illustrates an exemplary diagram illustrating how the iso-potential ring  229  works. For example, the first plate  222  may be electrically biased at a fixed voltage level. Depending on the voltage level of the surrounding interconnect metal layers such as the metals  2561 ,  2562 , the electric field F adjacent to the first plate  222  may be uneven. In the embodiment shown in  FIG. 2C , the electric field F may be concentrated at one side, causing a potential breakdown path near the metal  2562  because the metal  2562  is located nearer to the first plate  222 . However, if an iso-potential ring  229  is disposed surrounding the first plate, such uneven electric field F may be avoided. 
     The iso-potential ring  229  may be an optional feature that may increase the high voltage tolerance as well as reliability performance of the isolation device  200 . Another way that may increase the high voltage tolerance and reliability performance may be by having an isolation zone  226 . Similarly, the isolation zone  226  may be optional, may be formed with or without the iso-potential ring  229 . 
     Referring to  FIG. 2A , the isolation zone  226  may be devoid of the plurality of metal layers  250  surrounding the first plate  222  other than the optional iso-potential ring  229  or other residue materials  237  that may exist out of the manufacturing control. The isolation zone  226  may comprise the at least one trench  260  extending through the isolation material  240  surrounding the iso-potential ring  229  along the first axis  299 . The isolation zone  226  may enable electric flux from the first plate  222  to reach the second plate  225 , and may be configured avoid formation of unwanted breakdown path as illustrated in  FIG. 2C . 
     The isolation zone  226  may extend substantially perpendicularly relative to the first plate  222  between the first plate  222  and the second plate  225 . The isolation zone  226  may has a zone perimeter  294 . The zone perimeter  294  may extend outwardly from the plate perimeter  292 . The zone perimeter  294  of the isolation zone  226  may extend at least twenty microns outwardly from the plate perimeter  292 . 
     The second plate  225  may be a portion of the first interconnect metal layer  251  as shown in  FIG. 2A . The isolation device  200  may comprise a protective well disposed below the second plate  225  so as to electrically isolate the second plate  225  from a portion of the substrate  210  surrounding the second plate  225 . The protective well  294  may be N-type or a P-type well that is electrically disconnected from the substrate  210 . Metal layers may be highly conductive and suitable for making the second plate  225 , but the second plate  225  may be a portion of any other layers as illustrated in  FIG. 2D . 
       FIG. 2D  illustrates various implementations of the second plate  225 . The first plate  222  remain the same as  FIG. 2A . For example, the second plate  225  may be a portion of a well layer having higher electrical conductivity relative to the substrate  210  as shown in  FIG. 2D (a), an active region or a region within the substrate  210  that may be highly doped as shown in  FIG. 2D (b), a topmost interconnect metal layer as shown in  FIG. 2D (c), a highly-doped poly-silicon layer as shown in  FIG. 2D (d), or a topmost metal layer as shown in  FIG. 2D (e) and  FIG. 2D (f). The second plate  225  and the first plate  222  may be positioned side-by-side on a substantially flat plane such that each of the second plate  225  and the first plate  222  has side surfaces extending substantially along the first axis  299  facing each other. As shown in  FIG. 2D (f), the at least one trench  260  may extend into the substantially flat plane separating the first plate  222  and the second plate  225 . In this arrangement, the at least one trench  260  extends substantially in parallel with the first axis  299 . The substrate  210  may be p-type or n-type as indicated in  FIG. 2D . 
     Referring to  FIG. 2A , the first plate  222  may extend substantially planarly on a first plane. The second plate  225  may extend on a second plane that is substantially parallel to the first plane but distanced away from the first plane. As shown in  FIG. 2A , the first plate  222  and the second plate  225  may be arranged such that both the first plate  222  and the second plate  225  are substantially in parallel with a first external surface  298  of the isolation device  200 . The first external surface  298  may extend substantially parallel to the substrate  210  other than the neck portion  249  of the isolation material  240 . The at least one trench  260  may extend into the first external surface  298  along the direction that is in parallel with the first axis  299 . In other words, the at least one trench  260  may extend substantially orthogonal relative to the external surface  298 . 
     The at least one trench  260  may circumscribe at least one of the first plate  222  and the second plate  225  or both the first plate  222  and the second plate  225  such that the at least one trench forms a closed loop geometrical figure surrounding the at least one of the first plate  222  and the second plate  225 . The geometrical figure surrounding the at least one of the first plate  222  and the second plate  225  may be a square, rectangle, circle or any shape having a closed loop. Referring to  FIG. 2A  and  FIG. 2B , the at least one trench  260  may encircle the first plate  222  and the second plate  225  on a third plane that is distanced away but substantially parallel to the first plate  222 . As shown in  FIG. 2B , the at least one trench forms a circular shape surrounding the first plate  222 . The external surface  298  may be located on the third plane. The at least one trench  260  may be coaxially aligned to at least one of the first plate  222  and the second plate  225 , or both the first plate  222  and the second plate  225 . 
     In one embodiment, the at least one trench  260  may be disposed on the neck portion  249  of the isolation material  240  encircling the first plate  222  on the first plane. In another embodiment, the at least one trench  260  and the second plate  225  may be disposed on the third plane such that the at least one trench  260  may be encircling the second plate  225  and being vertically distanced away from the first plate  222 . 
     In yet another embodiment, the at least one trench  260 , the first plate  222  and the second plate  225  may be positioned on the third plane where the external surface  298  is located. The at least one trench  260  may circumscribe one of the first plate  222  and the second plate  225 , but not both. For example, the at least one trench  260  may encircle the second plate  225  on the second plane. Various implementations of the at least one trench  260  discussed in previous paragraphs may be applied in combination using additional trenches (not shown). 
       FIG. 2E  illustrates how the at least one trench  260  may be employed to improve isolation voltage. As the isolation material  240  are formed layers by layers along with formation of the plurality of metal layers  250 , residue materials  237  may be trapped within the isolation material  240 . The residue materials  237  may be unintentional by-products that may be highly conductive relative to the isolation material  240 . The residue materials  237  may be metal traces, or deposition of conductive material that exist in extremely small quantities. Generally, the residue materials  237  may be found in parallel to the substrate  210 . However, the residue materials  237  may not cover the entire surface of the isolation layers  241 - 246 , but merely a small surface portion on the isolation layers  241 - 246 . 
     Formation of the residue materials  237  may be unavoidable. As the residue materials  237  are an unintended by-product of the manufacturing process, the residue materials  237  may occur randomly and may have irregular shape. The residue materials  237  may extend planarly in parallel with the substrate  210 . Generally the residue materials  237  may be trapped between two of the plurality of isolation layers  241 - 246  and  249 . On some occasions, the residue materials  237  may be in contact with a neighboring metal layer  228  as illustrated in  FIG. 2E . As a result, the residue material  237  may cause a potential breakdown path as shown in  FIG. 2E . In the example shown in  FIG. 2E , the isolation voltage between the top plate  222  and the bottom plate  225  may be 8 kV, but due to the alternate breakdown path caused by the residue materials  237 , the isolation voltage may be reduced to 2 kV. 
     By having the at least one trench  260  that may intercept and cut through the residue material  237 , the conductive residue material  237  between the top plate  222  and the bottom plate  225  may be intercepted. For example, as shown in  FIG. 2E , the at least one trench  560  may intersect one of the residue materials  237  into two electrically isolated portions. As a result, the electrical path may be broken and the residue material  237  may be unable to provide any current path for breakdown. As a result, the isolation voltage may remain at a higher level. In the example shown in  FIG. 2E , the isolation voltage may remain at 8 kV or higher by employing at least one trench  260  to intercept and interrupt the residue materials. By surrounding the first plate  222  and the second plate  225  with the at least one trench  260 , potential current path provided by the residue material  237  may be interrupted, ensuring higher isolation voltage in the process. 
     When the at least one trench  260  surrounds or circumscribes the first plate  222  and the second plate  225  in a complete closed loop manner cutting through the isolation layers  241 - 246 , all potential breakdown path can be completely eliminated. However, some manufacturing process may not allow a complete closed loop trench  260 . For isolation devices  200  that are fabricated using such manufacturing process, the at least one trench  260  having curvatures or linear segment of trench members illustrated in  FIG. 2F  and  FIG. 2G  may be employed. 
       FIG. 2F  illustrates a diagrammatic top view of the at least one trench  260  having a plurality of trench members  262 . The plurality of trench members  262  may collectively form a partial circular ring. Each of the plurality of trench members  262  may have substantially similar size and shape. The plurality of trench members  260  may collectively encircle the at least one of the first plate  222  and the second plate  225 . As shown in  FIG. 2F , each of the plurality of trench members  262  may comprise a curvature segment. The curvature segment of each of the plurality of trench members  262  may extend axially from a curvature center  296 . The curvature center  296  may be located on at least one of the first plate  222  and the second plate  225 . 
     Similar to the at least one trench  260  shown in  FIG. 2A , the plurality of trench members  262  may be surrounding at least one of the first plate  222  and the second plate  225  on a horizontal plane substantially in parallel with the substrate  210 . Optionally, the at least one trench  260  may further comprise a plurality of additional trench members  264 . The additional trench members  264  may be surrounding the plurality of trench members  262 . The plurality of additional trench members  264  and the plurality of trench members  262  may be coaxially aligned. 
     Each of the trench members  262 ,  264  may be separated by a distance allowable by the manufacturing process. For optimal size, the separation distances g 1 -g 3  may be at a minimum distance. For example, the separation distances g 1 -g 3  may be less than five microns. The width of the first trench member wl may be approximately equal to the width of the second trench member w 2 . Each of the trench members  262 ,  264  may have a minimum width of less than 10 microns. 
     Referring to  FIG. 2F  and  FIG. 2A , the plurality of trench members  262  and the plurality of additional trench members  264  may be arranged such that any cross sectional view, taken along a plane substantially perpendicular to the substrate  210  extending through the first plate  222 , may intersect at least two cross-sectional trenches of the trench member  262  or the additional trench member  264  sandwiching thereby at least one of the first plate  222  and the second plate  225 . For example, a cross sectional view taken along line A-A′ will yield two cross-sectional trench members  262 ,  264 , i.e. two trench members  262 ,  264  on each side of the first plate  222  but a cross sectional view taken along line B-B′ will yield one cross-sectional trench member  262 , one trench member  262  on each side of the first plate  222  as shown in  FIG. 2A . 
     Alternatively, each of the plurality of trench members  262  may comprise a linear trench segment as illustrated in  FIG. 2G .  FIG. 2G  illustrates a diagrammatic top view of the at least one trench  260  having a plurality of linear trench members  266  without showing the top plate  222 . The plurality of linear trench members  266  may form a hexagonal or an octagonal shape surrounding the first plate  222  or the second plate  225 . 
     In the embodiment shown in  FIG. 2A , the at least one trench  260  may intercept and extend through the passivation layer  248 . The at least one trench  260  may then be filled up using an additional isolation material such as silicon nitride, silicon dioxide, polyimide, a mixture of some or all of the above mentioned material or any other isolative material. 
     The at least one trench  260  may extend through the entire isolation material  240  touching the substrate  210  as shown in  FIG. 2A . Optionally the at least one trench  260  may intercept or extend through one or more isolation layers  241 - 246  of the isolation material  240  but not the entire isolation material  240  as shown in  FIG. 2H ,  FIG. 2I  and  FIG. 2G . 
     For protection purpose, the isolation device  200  may comprise the passivation layer  248  that substantially cover the isolation material  240 . The at least one trench  260  may be formed before or after the passivation layer  248  is formed.  FIG. 2H  illustrates an alternative embodiment of the at least one trench  260  that extends through the passivation layer  248  but not extending through any of the plurality of isolation layers  241 - 246  shown in  FIG. 2A . As shown in  FIG. 2H , the at least one trench  260  may stop at an iso-potential ring  229  implemented using a topmost interconnect metal layer  256  shown in  FIG. 2A . The embodiment shown in  FIG. 2H  may be suitable for manufacturing process with impurities or residue materials  237  present mostly at the external surface  298  but at relatively much lower probability within the plurality of isolation layers  241 - 246  shown in  FIG. 2A . 
     As shown in  FIG. 2I , optionally the isolation device  200  may further comprise an etch stop layer  281 . The etch stop layer  281  may be disposed between the plurality of isolation layers  241 - 246 . The etch stop layer  281  may be configured to stop the formation of the at least one trench  260  during manufacturing process and thus, the etch stop layer  281  may be connected to a bottom portion of the at least one trench  260 . The at least one trench  260  may be filled up before being covered by the passivation layer  248 . For example, the at least one trench  260  may be filled up using a dielectric material. The passivation layer  248  may cover the dielectric material. The dielectric material and the isolation material  240  may consist essentially of silicon nitride. The dielectric material and the isolation material  240  may consist essentially of silicon dioxide. The arrangement shown in  FIG. 2I  may be suitable for manufacturing process in which the formation of passivation layer  248  is clean and substantially free from residue materials  237 , but where the formation of the isolation layers  241 - 246  may be susceptible to formation of residue materials  237 . 
     Another alternative arrangement of the at least one trench  260  is shown in  FIG. 2J .  FIG. 2J  is substantially similar to the embodiment shown in  FIG. 2I  but differs at least in that the at least one trench  260  may be made large enough that the at least on trench  260  is not filled up with any dielectric material. The passivation layer  248  may be disposed within the at least one trench  260  and hence, the passivation layer  248  may cover substantially an inner portion of the at least one trench  260 . 
       FIG. 3  illustrates a diagrammatic cross sectional view of an isolation device  300 . The isolation device  300  may comprise a substrate  310 , a first plate  322 , a second plate  325 , an isolation material  340 , at least one trench  360 , and a plurality of metal layers  350 . The plurality of metal layers  350  may comprise a topmost metal layer  359  and a plurality of interconnect metal layers  351 - 354 . The isolation material  340  may comprise a passivation layer  348 , an enhanced isolation layer  349 , and a plurality of dielectric layers  341 - 344 . The first dielectric layer  341  may be sandwiched between the plurality of interconnect metal layers  351  and the substrate  310 . Each of the plurality of dielectric layers  342 - 344  may be sandwiched between two of the plurality of interconnect metal layers  351 - 354 . The at least one trench  360  may extend through at least two layers of the plurality of dielectric layers  341 - 344 . 
     The isolation device  300  may be substantially similar to the isolation device  200  shown in  FIG. 2A  but differs at least in that the isolation device  300  does not have the neck portion  249  shown in  FIG. 2A . Instead, the isolation device  300  may comprise an enhanced isolation layer  349  that may have a substantially uniform thickness. The enhanced isolation layer  349  may have higher isolation capabilities in that the enhanced isolation layer  349  may be substantially thicker than the thickness of each of the isolation layers  341 - 344 . In one embodiment, the enhanced isolation layer  349  may have a thickness that is more than four times the average thickness of the plurality of isolation layers  341 - 344 . In another embodiment, the enhanced isolation layer  349  may have a thickness that is more than five times the average thickness of the plurality of isolation layers  341 - 344 . 
     In addition to the enhanced thickness discussed above, the enhanced isolation layer  349  may have higher isolation capabilities in that the enhanced isolation layer  349  may comprise material that is highly isolative, or the enhanced isolation layer  349  may be added with highly isolative material. In order to establish electrical contact to the isolation device  300 , the topmost metal layer  359  may comprise bond pads having exposed external surfaces  323  and  357 . For example, the top plate  322  may have the exposed surface  323  configured to receive an external electrical connection from a first circuit. Similarly, an additional bond pad with the exposed surface  357  may be configured to receive an additional external electrical connection from a second circuit. The isolation device  300  may comprise an elongated via  385  that extends through the enhanced isolation layer  349  so as to establish electrical connection to the plurality of interconnect metal layers  351 - 354 . The topmost metal layer  359  may be reserved for bond pads. 
     In addition, the isolation device  300  may differ from the previously discussed isolation devices  100  and  200  in that the second plate  325  may be in direct contact with the at least one trench  360 . The reason for this difference is that the second plate  325  may be configured to function as an etch stop layer to the at least one trench  360 . This optional feature may be applicable to the isolation devices  100  and  200  discussed previously. 
     The passivation layer  348  of the isolation device  300  may be substantially flat and uniformly cover the top surface of the isolation device  300  other than the exposed surfaces  323  and  357 . With this configuration, the isolation device  300  may be less sensitive to moisture since the flat top surface without neck portion may ensure coverage of the passivation layer  348 . The thickness of the passivation layer  348  may be substantially uniform. 
       FIG. 4  illustrates a diagrammatic cross sectional view of an isolation device  400 . The isolation device  400  may comprise a substrate  410 , a first plate  422 , a second plate  425 , an isolation material  440 , at least one trench  460 , a plurality of metal layers  450 , a first iso-potential ring  4291 , a second iso-potential ring  4292 , a first passivation layer  4481  and a second passivation layer  4482 . 
     The isolation material  440  may comprise an enhanced isolation layer  449 , a plurality of dielectric layers  441 - 446 , the first passivation layer  4481  and the second passivation layer  4482 . The enhanced isolation layer  449  may form a neck portion of the isolation device  400  protruding from an upper surface  498 . 
     The plurality of metal layers  450  may comprise a topmost metal layer  459  and a plurality of interconnect metal layers  451 - 456 . In  FIG. 4 , an illustrative topmost metal layer  459  is drawn on the right hand side of the neck portion  449 . The top plate  422  and the first iso-potential ring  4291  may be formed using the topmost metal layer  459 . 
     The isolation device  400  may be substantially similar to the isolation device  200  shown in  FIG. 2A  but differs at least in the following points. 
     First, the isolation device  400  may comprise the additional passivation layer  4482  instead of a single passivation layer  248  illustrated in  FIG. 2A . The first passivation layer  4481  may cover the plurality of dielectric layers  441 - 446  and the plurality of interconnect metal layers  451 - 456 , except that surfaces on the topmost interconnect metal layer  456  may be exposed. Consequently, the neck portion of the isolation device  400  may be disposed on the first passivation layer  4481  instead of the dielectric layer  446 . Having two passivation layers  4481  and  4482  may be desirable in terms of ease of manufacturing. The neck portion  449  may be un-protected, as the side surfaces are not covered. However, moisture may not sip in further as the neck portion  449  is sitting on the first passivation layer  4481 . 
     Second, the at least one trench  460  of the isolation device  400  may be disposed on the neck portion  449 . The at least one trench  460  may stop at the first passivation layer  4481 . In this case, a bottom portion of the at least one trench  460  may be in direct contact with the first passivation layer  4481 . Alternatively, the at least one trench  460  may intercept at least one dielectric layer  441 - 446  or all of the plurality of dielectric layers  441 - 446 . In the case that the at least one trench  460  cut through all the dielectric layers  441 - 446 , the at least one trench  460  may be in direct contact with the substrate  410 . 
     Third, the isolation device  400  may comprise one additional trench  468  compared to the isolation device  200  shown in  FIG. 2A . While the at least one trench  460  is disposed on the neck portion  449 , the additional trench  468  may be defined by the opening of the first passivation layer  4481  on the first surface  498 . This may be effective to interrupt residue materials that may occur on the first surface  498  and thus, improve isolation capabilities. 
     Fourth, the isolation device  400  comprises two iso-potential rings  4291 ,  4292  instead of one iso-potential ring  229  as shown in  FIG. 2A . the two iso-potential rings  4291 ,  4292  of the isolation device  400  are the first iso-potential ring  4291  disposed on the plane where the first plate  422  is located, and the second iso-potential ring  4292  that is located on a plane disposed planarly between the first plate  422  and the second plate  425 . The iso-potential rings  4291 ,  4292  are substantially parallel to the first plate  422  and the second plate  425 . The first iso-potential ring  4291  may surround the first plate  422  on the neck portion  449  of the isolation device  400 . The second iso-potential ring  4292  may surround the first plate  422  on the first surface  498  of the isolation device  400  on the plane that is distanced away from the first plate  422 . Similar to previously described embodiments, the first plate  422 , the second plate  425 , the first iso-potential ring  4291  and the second iso-potential ring  4292  may be concentric. While the first iso-potential ring  4291  may be a portion of the topmost metal layer  459 , the second iso-potential ring  4292  may be a portion of the topmost interconnect metal layer  456 . 
       FIG. 5  illustrates a diagrammatic cross sectional view of an isolation device  500 . The isolation device  500  may comprise an isolation material  540 , a substrate  510 , a high isolative material  539 , a first plate  522  and a second plate  525 . The isolation material  540  may comprise substantially silicone dioxide material. The isolation material  540  may comprise a plurality of isolation layers  541 - 546 , a passivation layer  548 , and an enhanced isolation layer  549  similar to the isolation devices  200 ,  300  and  400  discussed previously. The isolation device  500  may differ from the isolation devices  200 ,  300  and  400  at least in that the isolation device  500  comprises a layer of high isolative material  539 . The highly isolative material  539  may be made from a material that provides higher isolation compared to the isolation material  540 . One example of the highly isolative material  539  may be polyimide. 
     In the embodiment shown in  FIG. 5 , the high isolative material  539  may be embedded within the enhanced isolation layer  549  such that the highly isolative material  539  may be sandwiched between the first plate  522  and the topmost isolation layer  546  In other embodiments, the high isolative material  539  may be sandwiched between two of the plurality of isolation layers  541 - 546  or between the topmost isolation layer  546  and the enhanced isolation layer  549 . The high isolative material  539  may be in direct contact with one of the first plate  522  and the second plate  525 . 
     In yet another embodiment, the highly isolative material  539  may be disposed between the plurality of isolation layers  541 - 546  between the first plate  522  and the second plate  525 . The highly isolative material  539  may be configured to cover any potential residue material  537  that may exist between the first plate  522  and the second plate  525  so as to break any potential breakdown path as illustrated in  FIG. 2E . 
       FIG. 6A  illustrates a diagrammatic view of an isolation system  600 . The isolation system  600  may comprise a primary die  601 , a first circuit  672 , an additional die  602 , and a second circuit  674 . The terminology “primary” as referred to the primary die  601  is by no means indicating importance of the die relative to other dies or other components. The terminology “primary” merely distinguishes the two dies  601 ,  602 . The terminology “primary” is chosen for the primary die  601  because majority of the elements recited here are disposed on the primary die  601 . 
     The primary die  601  may comprise a topmost metal layer  659 , a plurality of additional metal layers  651 - 653 , a substrate  610 , a coupling device  620 , and an isolation material  640 . The substrate  610  may be a semiconductor substrate  610  that integrated circuits are formed on. The isolation material  640  may comprise an enhanced isolation layer  649 , a first passivation layer  6481 , a second passivation layer  6482 , and a plurality of isolation layers  641 - 643 . The isolation layers  641 - 643  may also be referred as dielectric layers. The plurality of isolation layers  641 - 643  comprises a topmost dielectric layer  643 . The topmost dielectric layer  643  may be positioned furthest from the semiconductor substrate  610 . 
     The plurality of additional metal layers  651 - 653  may be interconnect-metal layers. For example, the plurality of additional metal layers  651 - 653  may comprise a topmost interconnect metal layer  653 , and a first interconnect metal layer  651 , and a second interconnect metal layer  652 . The plurality of metal layers  651 - 653  may be electrically interconnected through “vias.” However, the plurality of additional metal layers  651 - 653  may be electrically isolated from the topmost metal layer  659 . 
     A surface of the topmost interconnect metal layer  653  may be exposed so as to receive a wire bond or a solder ball to establish electrical connections externally. Similarly, a surface of the topmost metal layer  659  may be exposed so as to receive a wire bond or a solder ball  676  to establish electrical connections externally. 
     The coupling device  620  may be disposed within the primary die  601 . The coupling device  620  may comprise a first plate  622  and a second plate  625 . The first plate  622  of the coupling device  620  may be formed by a portion of the topmost metal layer  659 . The first plate  622  may be electrically connected to the second circuit  674  resided in the additional die  602 . The second plate  625  may be electrically connected to the first circuit  672  that reside in the primary die  601 . 
     The second plate  625  of the coupling device  620  may be formed by a conductive layer  658  of the primary die  601 . The conductive layer  658  may be one of the additional metal layers  651 - 653 , a sub-layer within the substrate  610  that has been made highly conductive such as active layer, poly-silicon layer or a highly doped well layer, or any other layer within the substrate  610  that is substantially more electrically conductive relative to the substrate  610 . 
     In one embodiment, the conductive layer  658  that forms the second plate  625  may be closest to the substrate  610  such that the plurality of additional metal layers  651 - 653  may be sandwiched between the conductive layer  658  and the topmost metal layer  659 . For example, the conductive layer  658  may be a poly-silicon layer deposited on the substrate  610 . 
     A portion of the isolation material  640  may be sandwiched between the first plate  622  and the second plate  625 . The isolation material  640  may be surrounding the plurality of additional metal layers  651 - 653 . Each of the plurality of additional isolation layers  641 - 643  may be sandwiched between two layers selected from the additional metal layer  651 - 653  and the substrate  610 . The additional isolation layer  641 - 643  may be referred as dielectric layers  651 - 653 . The enhanced isolation layer  649  maybe in direct contact with the topmost metal layer  659 . The plurality of additional isolation layer  641 - 643  may be arranged such that the enhanced isolation layer  649  is sandwiched between the plurality of additional isolation layers  641 - 643  and the topmost metal layer  659 . 
     The enhanced isolation layer  649  may be functionally thicker than the plurality of additional isolation layers  641 - 643 . While each of the plurality of additional isolation layers  641 - 643  has a thickness that is sufficient to separate the plurality of metal layers  651 - 653  to minimise capacitive coupling noise, the enhanced isolation layer  649  may have a relatively higher thickness that is capable of withstanding high voltage difference across the first plate  622  and the second plate  625  compared to each of the plurality of additional isolation layers  641 - 643  may not withstand. For example, each of the plurality of additional isolation layers  641 - 643  may breakdown at a breakdown voltage, Vbreakdown, the voltage difference across the enhanced isolation layer  649  may be at least five times Vbreakdown. In the embodiment shown in  FIG. 6 , the enhanced isolation layer  649  may be sandwiched between the first plate  622  and the semiconductor substrate  610 . The enhanced isolation layer  649  may form a neck portion  649 . The neck portion  649  may protrude out from the semiconductor substrate  610 . 
     As explained in previous embodiments, unwanted and undesirable residue materials  637  may be formed between the isolation material  640  when the primary die  601  is fabricated. The residue materials  637  may be sandwiched between any two layers from the enhanced isolation layer  649  and the plurality of additional isolation layers  641 - 643 . Generally, the residue materials  637  may be accumulated planarly parallel to the substrate  610  and one of the additional isolation layers  641 - 643 . The residue materials  637  may be metal traces or deposition of conductive material that appears in microscopic amount. 
     As the residue materials  637  may be electrically conductive, the residue materials  637  may be substantially highly conductive relative to the isolation materials  640 . The residue materials  637  may comprise microscopic metallic traces that are not electrically connected to the plurality of the additional metal layers  651 - 653 . The residue materials  637  may comprise electrically conductive material that attracts electrical flux generated from the first plate  622 . 
     The semiconductor substrate  610  may be covered by the first passivation layer  6481 . The first passivation layer  6481  may be covering the plurality of additional metal layers  651 - 653 , the plurality of isolation layers  641 - 643 , and the trench  660 . This is to prevent moisture from sipping in to the plurality of metal layers  640  and other internal layers other than exposed surface that are meant for receiving external electrical connections. 
     The isolation system  600  may further comprise a solder ball  676 . The primary die  601  and the additional die  602  may be positioned facing each other such that the solder ball  676  may be sandwiched between the primary die  601  and the additional die  602 . The solder ball  676  may be in direct contact with the first plate  622  of the coupling device  620  of the primary die  601 . The additional die  602  may comprise a metal pad  691 . The solder ball  676  may be in direct contact with the metal pad  691 . 
     The first circuit  672  may be integrated substantially in the primary die  601 . The second circuit  674  may be integrated substantially in the additional die  602 . However, in other embodiment, the first circuit  672  may be integrated in the primary die  601 , as well as other additional dies (not shown). Similarly, the second circuit  674  may be integrated substantially in more than one die  602 . 
     An additional coupling device  621  may be disposed within the primary die  601 . The additional coupling device  621  may have an additional first plate  623  and an additional second plate  629 . The additional first plate  623  may be a portion of the topmost metal layer  659  and the additional second plate  629  may be a portion of the conductive layer  658 . The additional first plate  623  may be electrically coupled to the second circuit  674 . The additional second plate  629  may be electrically connected to the first circuit  672 . 
     In the embodiment shown in  FIG. 6 , a first coupling device  620  is configured to transmit a signal  670  from the second circuit  674  in the additional die  602  to the first circuit  672  resided in the primary die  601 . The second coupling device  621 , on the other hand, is configured to transmit a return signal  671  from the first circuit  672  in the primary die  601  to the second circuit  674  resided in the additional die  602 . Optionally, the coupling device  620  and the additional coupling device  621  may be configured to transmit a differential signal between the first circuit  672  and the second circuit  674 . 
     The isolation system  600  may further comprise a trench  660 . The trench  660  may be circumscribing at least one of the first plate  622  and the second plate  625  intersecting the semiconductor substrate  610  as shown in previous embodiments. The trench  660  may intersect the semiconductor substrate  610  at an angle α between 60 degrees and 120 degrees relative to the semiconductor substrate  610 . The trench  660  may have a pointed end. In the example shown in  FIG. 6A , the primary die  601  may comprise a plurality of dielectric layers  641 - 643 . The plurality of dielectric layers  641 - 643  may have a topmost dielectric layer  643 . The topmost dielectric layer  643  may be positioned furthest from the semiconductor substrate  610 . The trench  660  may be covered by the topmost dielectric layer  643 . 
     The trench  660  may be filled with an additional isolation material, and subsequently the trench  660  may be covered by the first passivation layer  4481 .  FIGS. 6B-6C  illustrate a diagrammatic view of the trench  660  filled with isolation materials. Referring to  FIG. 6B , the additional isolation material may overfill the trench  660  such that the additional isolation material may form a bump portion. The first passivation layer  648  may cover the bump portion of the additional isolation material. 
     Referring to  FIG. 6A  and  FIG. 6B , the semiconductor substrate  610  may extend planarly on a horizontal plane. The trench  660  may have a height dimension h that may extend substantially perpendicularly relative to the horizontal plane. The trench  660  may have a width dimension w that is at least two microns but less than twenty microns. In one embodiment, the width dimension w may be at least five microns. As shown in  FIG. 6B , the trench  660  may have a tapering end towards the substrate in the vertical direction. In addition, as shown in  FIG. 6B , the trench  660  may have a rounded end. 
     The trench  660  may be under filled as shown in  FIG. 6C . Optionally, the trench  660  may be formed after the passivation layer  6481  is formed as shown in the embodiment illustrated in  FIG. 6D . In this case, the trench  660  may be made by using ultra-sound drilling. 
       FIG. 7  illustrates a diagrammatic cross sectional view of an isolation system  700  operating in different voltage ranges. The isolation system  700  may comprise a first circuit  772 , a second circuit  774 , and a capacitive isolator  720 . The first circuit  772  may be operating at a first voltage range Vrange 1 . The second circuit  774  may be operating at a second voltage range Vrange 2  that is different from the first voltage range Vrange 1 . For example, the first voltage range Vrange 1  may be between plus minus thirty volts and the second voltage range Vrange 2  may be between plus minus five volts. The second circuit  774  may comprise one or more metal layers  750  established on a substrate  710 . The substrate  710  may be a semiconductor substrate  710 . 
     The capacitive isolator  720  may electrically isolate the first circuit  772  from the second circuit  774  while enabling control signals  770  to pass between the first circuit  772  and second circuit  774  in electrical flux  771 . The capacitive isolator  720  may comprise a first capacitive element  722 , a second capacitive element  725 , an isolation material  740 , and at least one trench  760 . In one example, the isolation material  740  maybe a dielectric material  740  covering the semiconductor substrate  710 . 
     The first capacitive element  722  may be in electrical communication with the first circuit  772  and may be disposed adjacent to the one or more metal layers  750 . The second capacitive element  725  may be positioned in an overlapping arrangement with the first capacitive element  722 . The second capacitive element  725  may be in electrical communication with the one or more metal layers  750  of the second circuit  774 . 
     The isolation material  740  may be positioned between the first capacitive element  722  and the second capacitive element  725 . The isolation material  740  may substantially prevent current from flowing directly between the first capacitive element  722  and the second capacitive element  725 , but enables electrical flux  771  to pass between the first capacitive element  722  and the second capacitive element  725 . 
     The isolation material  740  may comprise an enhanced isolation layer  749 , residue materials  737 , at least one additional isolation layer such as a first isolation layer  741 , and a second isolation layer  742  that may be formed between the isolation material  740 . The enhanced isolation layer  749  may be in direct contact with one of the first capacitive element  722  and the second capacitive element  725 . The at least one additional isolation layer  741 - 742  may be disposed adjacent to the other one of the first capacitive element  722  and the second capacitive element  725 . The residue materials  737  may be disposed between the enhanced isolation layer  749  and the at least one additional isolation layer  741 ,  742 . 
     The at least one trench  760  may be planarly surrounding at least one of the first capacitive element  722  and the second capacitive element  725 . For example, the at least one trench  760  may form a close loop on a first plane that is parallel to the substrate  710  surrounding one of the first capacitive element  722  and the second capacitive element  725 . The first plane may be located on a plane where one of the first or second capacitive elements  722  and  725  is located on, or alternatively, the first plane may be located between the first capacitive element  722  and second capacitive element  725  as illustrated in previous embodiments. The at least one trench  760  may extend through the dielectric material  740 . 
       FIG. 8  illustrates a diagrammatic cross sectional view of an isolation capacitor  800 . The isolation capacitor  800  may comprise a first capacitive element  822 , a second capacitive element  825 , a semiconductor substrate  810 , an isolation material  840 , and at least one trench  860 . 
     The first capacitive element  822  may be in electrical communication with a first circuit  872 . The second capacitive element  825  may be in electrical communication with a second circuit  874 . The second circuit  874  may be electrically separated from the first circuit  872  for various reasons. For example, each of the first circuit  872  and the second circuit  874  may need to be operated at different voltages. In another example, the first circuit  872  and the second circuit  874  may draw power from different transformers located on different devices that are physically separated. In yet another example, one of the first circuit  872  and the second circuit  874  may be susceptible to noisy environment and need to be electrically isolated. 
     The first capacitive element  822  and the second capacitive element  825  may be established on the semiconductor substrate  810 . The isolation material  840  may be covering a top surface  812  of the semiconductor substrate  810 . At least one of the first capacitive element  822  and the second capacitive element  825  may be buried within the isolation material  840 . 
     The isolation material  840  may comprise a passivation layer  848 , and a plurality of isolation layers  841 ,  842  and  849 . The plurality of isolation layers  841 ,  842  and  849  may be positioned between the first capacitive element  822  and the second capacitive element  825 . The plurality of isolation layers  841 ,  842 , and  849  may substantially prohibit electrical current from flowing between the first capacitive element  822  and second capacitive element  825 , thereby maintaining an electrical isolation between the first circuit  872  and second circuit  874 . The plurality of isolation layers  841 ,  842 , and  849  may allow a capacitively coupled signal  871  to travel between the first capacitive element  822  and second capacitive element  825  thereby enabling communication between the first circuit  872  and second circuit  874  even though the first circuit  872  and second circuit  874  are electrically isolated from one another. 
     The plurality of isolation layers  841 ,  842 ,  849  may comprise a first layer  849  that is thicker than any other layers of the plurality of isolation layers  841  and  842 . For example, the first layer  849  may have enhanced isolation capabilities through having a substantially thicker layer. Alternatively, the first layer  849  may be made from a material that has a high breakdown voltage. 
     The at least one trench  860  may be circulating at least one of the first capacitive element  822  and the second capacitive element  825 . The at least one trench  860  may be circulating both the first capacitive element  822  and the second capacitive element  825  on a plane that is parallel to one of the first capacitive element  822  and the second capacitive element  825 . The at least one trench  860  may be extending through the isolation material  840  on a horizontal plane. 
       FIG. 9  illustrates a diagrammatic cross sectional view of an isolation capacitor  900  having an embedded enhanced isolation layer  949 . The isolation capacitor  900  may comprise a first capacitive element  922 , a second capacitive element  925 , a semiconductor substrate  910 , and an isolation material  940 . The isolation capacitor  900  may be substantially similar to the isolation device  200  and the isolation capacitor  800  but differs in that the isolation capacitor  900  comprises the embedded enhanced isolation layer  949 . The embedded enhanced isolation layer  949  may be a single integrated portion of a material embedded and surrounded by the isolation material  940 . The embedded enhanced isolation layer  949  may have similar characteristics to the enhanced isolation material  249  illustrated in  FIG. 2A  in that the embedded enhanced isolation layer  949  may have a thickness dimension that is at least 3 times to 5 times thicker than any other isolation layers  941 - 946  of the isolation material  940 . In addition, the embedded enhanced isolation layer  949  may be made from a material that is more tolerant towards high voltage. 
       FIG. 10  illustrates a flow chart showing a method of operating a capacitive isolator. The method may begin by receiving electrical current at a first capacitive element as shown in Step  1010 . The first electrical current may be received from a first circuit operating at a first voltage range. The first capacitive element may be disposed adjacent to an enhanced isolation layer. In Step  1020 , the first electrical current may be converted into electric flux at the first capacitive element. In Step  1030 , the electric flux may be transmitted across an isolation layer. The isolation layer electrically isolates the first capacitive element from a second capacitive element and thereby electrically isolates the first circuit from a second circuit. The second circuit may be operating at a second voltage range that is different from the first voltage range. The second capacitive element may be disposed adjacent to an isolation layer that is thinner relative to the enhanced isolation layer. In Step  1040 , the electric flux may be received at the second capacitive element. In Step  1050 , the electric flux received at the second capacitive element may be converted into second current that is provided to the second circuit. 
       FIG. 11  illustrates a flow chart showing a method of operating a capacitive isolator with a trench. The method may begin by receiving electrical current at a first capacitive element as shown in Step  1110 . The first electrical current may be received from a first circuit operating at a first voltage range. The first capacitive element may be formed on a substrate plane. In Step  1120 , the first electrical current may be converted into electric flux at the first capacitive element. In Step  1130 , the electric flux may be transmitted across an isolation layer. The isolation layer electrically isolates the first capacitive element from a second capacitive element and thereby electrically isolates the first circuit from a second circuit. The second circuit may be operating at a second voltage range that is different from the first voltage range. The second capacitive element may be sandwiched between the first capacitive element and the semiconductor substrate and being surrounded by a trench intersecting the substrate plane. In Step  1140 , the electric flux may be received at the second capacitive element. In Step  1150 , the electric flux received at the second capacitive element may be converted into second current that is provided to the second circuit. 
     Different aspects, embodiments or implementations may, but need not, yield one or more of the following advantages. For example, the enhanced isolation layer and the at least one trench discussed in various embodiments may improve isolation capability. This may contributes towards higher breakdown of the isolation device. 
     Although specific embodiments of the invention have been described and illustrated herein above, the invention should not be limited to any specific forms or arrangements of parts so described and illustrated, but should also taking into consideration any combination of features illustrated in the same embodiment, or in other embodiments. For example, various alternative implementations of the at least one trench and the enhanced isolation layer may be combined in any other embodiments. The isolation system  600  and the isolation system  700  may employ the isolation devices  100 ,  200 ,  300 , and  400  although not specifically disclosed above. Similarly, the isolation capacitor  800  and the isolation capacitor  900  may employ the enhanced isolation layer and the at least one trench discussed in the isolation devices  100 ,  200 ,  300 , and  400 . 
     Referring now to  FIG. 12 , yet another capacitive isolation system  1200  will be described in accordance with at least some embodiments of the present disclosure. The system  1200  is shown to include a first circuit  1204  and second circuit  1208  separated by an isolation boundary  1212 . In some embodiments, an isolator  1216  may provide a mechanism for carrying communication signals across the isolation boundary  1212 . 
     The components of the system  1200  may be similar or identical to other isolation components described herein in connection with  FIGS. 1-11 . For instance, first circuit  1204  may be similar or identical to first circuit  172  and second circuit  1208  may be similar or identical to second circuit  174 . 
     The first circuit  1204  may be operating in a high-voltage environment (e.g., with a ground potential at or exceeding 1 kV) whereas the second circuit  1208  may be operating in a low-voltage environment (e.g., with a ground potential below 100V). Of course, the opposite condition may also be true without departing from the scope of the present disclosure. The isolation boundary  1212  may provide the mechanism for protecting the low-voltage environment from the high-voltage environment. The isolator  1216  may be configured to establish and maintain the isolation boundary  1212  while simultaneously facilitating the exchange of communications from the first circuit  1204  to the second circuit  1208  and vice versa. It should be appreciated, however, that the second circuit  1208  may be operating in the high-voltage environment and the first circuit  1204  may be operating in the low-voltage environment. 
     For ease of discussion, the first circuit  104  will be explained as an input circuit whose current and/or voltage is being measured and by the second circuit  108  (e.g., an output circuit). The isolation boundary  112  is provided to electrically insulate the currents/voltages at the input circuit from the output circuit. 
     In some embodiments, the first circuit  1204  receives a first input signal  1220  at a first voltage (e.g., a high voltage). The first circuit  1204  outputs a first output signal  1224  to the isolator  1216 . The first output signal  1224  is still at the same nominal voltage as the first input signal  1220 . The isolator  1216  communicates information from the first output signal  1224  to the second circuit  1208  via a second input signal  1228 . The second input signal  1228  is now as a second voltage (e.g., a low voltage) by operation of the isolator  1216 . The second circuit  1208  then processes the second input signal  1228  and generates a second output signal  1232  that is communicated to additional circuitry or controller components. Even though the first circuit  1204  operates at a different voltage than the second circuit  1208  and there is an electrical isolation between the two circuits  1204 ,  1208 , the isolator  1216  is able to preserve the information from the first output signal  1224  and communicate that information to the second circuit  1208  via the second input signal  1228 . The second input signal  1228  may correspond to a logical representation or copy of the first output signal  1224 . The second input signal  1228  is essentially a reproduction of the first output signal  1224  on different circuitry and at a different potential. 
     With reference now to  FIG. 12 , additional details of the isolator  1216  will be described in accordance with at least some embodiments of the present disclosure. The isolator  1216 , as discussed above, is responsible for communicating information between the first circuit  1204  and second circuit  1208  while simultaneously maintaining the isolation boundary  1212  between the circuits  1204 ,  1208 . Communication of the signal  1224  across the isolation boundary  1212  is achieved by one or more isolation components  1304 ,  1308 , which may correspond to capacitive isolation components as will be discussed in further detail herein. 
     The isolator  1216  may comprise first isolation component(s)  1304  on its input side and second isolation component(s)  1308  on its output side. The first isolation component(s)  1304  and second isolation component(s)  1308  may correspond to capacitive plates or the like that work together to communicate signals between one another wirelessly, thereby maintaining the isolation boundary  1212 . In some embodiments, the isolation components  1304 ,  1308  communicate with one another via capacitive coupling. Other coupling techniques such as inductive coupling, magnetic coupling, or the like may also be used by isolator  1216 . 
     With reference now to  FIG. 14 , additional details of an isolation device  1400  in the form of a capacitive isolator will be described in accordance with at least some embodiments of the present disclosure. It should be appreciated that while a capacitive isolator is depicted as the example of the isolation device, that inductive or other types of mechanism can be used to carry information across the isolation boundary  1212 . 
     In some embodiments, the isolation device  1400  may correspond to one example of a device that can operate as isolator  1216 . Although not depicted, the isolation device  1400  may include a substrate that supports one or more other elements depicted in  FIG. 14 . More specifically, the isolation device  1400  may share many characteristics or common elements as other isolation devices disclosed herein, such as devices  100 ,  200 ,  300 ,  400 ,  500 , and/or  600 . The isolation device  1400  is shown to include a plurality of dielectric layers  1404   a - e . These dielectric layers  1404   a - e  may be built upon a substrate as shown in other figures herein. The dielectric layers  1404   a - e  may correspond to discrete isolation layers stacked one upon another. The bottom or lowest most dielectric layer  1404   a  may be referred to as the first isolation layer. The next dielectric layer  1404   b , which is stacked upon bottom dielectric layer  1404   a , may be referred to as the second isolation layer. The next dielectric layer  1404   c , which is stacked upon dielectric layer  1404   b , may be referred to as the third isolation layer. The next dielectric layer  1404   d , which is stacked upon dielectric layer  1404   c , may be referred to as the fourth isolation layer. The top or highest dielectric layer  1404   e , which is stacked upon dielectric layer  1404   d , may be referred to as the fifth isolation layer or top most isolation layer. Although five discrete dielectric layers  1404   a - e  are depicted in  FIG. 14 , it should be appreciated that the isolation device  1400  may comprise a greater or lesser number of dielectric layers without departing from the scope of the present disclosure. The thickness of each dielectric layer  1404   a - e  may vary depending upon the material used and the desired isolation from layer to layer. In some embodiments, the dielectric layers  1404   a - e  may have a thickness that varies from 1.0 um to 2.0 um and, more specifically, in the range of 1.1 um to 1.5 um. The dielectric layers  1404   a - e  may be constructed of SiO2 or a similar material/compound that is capable of providing electrical isolation capabilities. 
     A nitride layer  1408  may be stacked upon the top dielectric layer  1404   e  and an oxide layer  1410  may be stacked upon the nitride layer. In some embodiments, the nitride layer  1408  may comprise Si3N4 or a functionally equivalent material/compound. The nitride layer  1408  may have a thickness between 0.5 um and 0.75 um and, more specifically, approximately 0.6 um. The oxide layer  1410  may correspond to any type of oxide (e.g., SiO2) that is capable of bonding with the nitride layer  1408 . 
     An enhanced isolation layer  1412  may be stacked upon the oxide layer  1410 . The enhanced isolation layer  1412  may be similar or identical to other enhanced isolation layers depicted and described herein (e.g., enhanced isolation layers  149 ,  249 ,  349 ,  449 ,  549 ,  649 ,  749 ,  849 , or  949 ). The enhanced isolation layer  1412 , in some embodiments, may be wafer-bonded to the oxide layer  1410  or directly to the nitride layer  1408  (in embodiments not including an oxide layer  1410 ). In some embodiments, the enhanced isolation layer  1412  comprises SiH4 and/or SiO2. More specifically, the enhanced isolation layer  1412  may comprise an amorphous SiO2 with a dielectric strength of at least 1000V/um. Compared with SiO2 that is deposited via chemical vapor deposition, which exhibits a dielectric strength of approximately 400V/um, the amorphous SiO2 of the enhanced isolation layer  1412  provides excellent electrical isolation properties and capabilities. The thickness of the enhanced isolation layer  1412  may be approximately 4 um to 6 um, or more particularly approximately Sum (within machining tolerances, etc.). 
     The isolation device  1400  further exhibits one or more passivation layers  1416 ,  1420  on the enhanced isolation layer. The one or more passivation layers  1416 ,  1420  may include a lower passivation layer  1416  and an upper passivation layer  1420 . The lower passivation layer  1416  may comprise SiO2 and be anywhere between 1.4 um and 1.8 um thick, or more specifically 1.6 um thick. The upper passivation layer  1416  may comprise Si3N4 and be anywhere between 0.5 um and 0.7 um thick, or more specifically 0.6 um thick. The lower passivation layer  1416  is shown to have the top metal layer provided therein where the upper passivation layer  1420  covers the lower passivation layer  1416  and does not have a metal layer provided therein. The top metal layer, as will be discussed in further detail herein may include a first capacitive plate  1444  and outer plate edges  1448 . 
     Referring back to the dielectric layers  1404   a - e , there may be provided a number of conductive vias  1424  and metal layers  1428  in and between each of the dielectric layers  1404   a - e . In the depicted example, the first dielectric layer  1404   a  comprises one or multiple conductive vias  1424  extending therethough. The conductive vias  1424  may be electrically conductive vias that extend between a first surface of the dielectric layer  1404  and an opposing surface of the dielectric layer  1404 . The conductive vias  1424  may comprise a conductive material (e.g., metal or the like) that fills or lines a hole or opening in the dielectric layer. Thus, the conductive vias  1424  extending through the first dielectric layer  1404   a  may extend to a top surface of first dielectric layer  1404   a  and provide electrical connectivity to a metal layer  1428  in the second dielectric layer  1404   b . The metal layer  1428  in the second dielectric layer  1404   b  may correspond to a first metal layer  1428  and may have a thickness of approximately 580 nm. The first metal layer  1428  may connect to a second conductive via  1424  that extends from the first metal layer  1428  to a top surface of the second dielectric layer  1404   b . The second conductive via  1424  may have a thickness of approximately 900 nm, making the overall thickness of the second dielectric layer  1404   b  approximately 1480 nm. Other thicknesses can be used for the metal layer  1428 , conductive vias  1424 , and/or dielectric layer  1404  without departing from the scope of the present disclosure. 
     This second conductive via  1424  may electrically communicate with another metal layer  1428  in the third dielectric layer  1404   c . The metal layer  1428  in the third dielectric layer  1404   c  may correspond to a second metal layer  1428  and may have a thickness similar or identical to other metal layers  1428  described herein. Yet another conductive via  1424  may provide connectivity between the second metal layer  1428  and a metal layer  1428  in the fourth dielectric layer  1404   d . As can be appreciated, this stacking of dielectric layers  1404  with metal layers  1428  and conductive vias  1424  may continue for as many dielectric layers  1404  are desired. The successive stacking of metal layers  1428  and conductive vias  1424  may result in creating a seal ring stack  1468  that is substantially surrounding or enclosing the other circuitry components that will be described in further detail herein (e.g., the capacitive components). The metal layers  1428  in the seal ring stack  1468  may correspond to simple bonding pads or traces within the dielectric layers  1404 . 
     As shown in  FIG. 14 , the top most dielectric layer  1404   e  may comprise a metal layer that not only includes simple metal layer  1428  components, but the top metal layer in the top most dielectric layer  1404   e  may also comprise a bonding pad  1436  and a second capacitive plate  1440 . The bonding pad  1436  and second capacitive plate  1440  may be electrically connected with one another by a lateral trace  1432  extending through a dielectric layer positioned below the top most dielectric layer  1404   e . It should be appreciated that, in some embodiments, the lateral trace  1432  may be electrically connected to other internal circuitry within the stack of dielectric layers  1404   a - e . Moreover, the bonding pad  1436  may be electrically connected to other internal circuits, which means that the electrical connection between the bonding pad  1436  and second capacitive plate  1440  may be achieved through the lateral trace  1432  as well as one or multiple other internal circuit elements. The additional circuit elements are not depicted in detail, but are generally represented by the logical break shown separating the lateral trace  1432  in  FIG. 14 . 
     More specifically, in the depicted embodiment, the lateral trace  1432  is shown to extend through the fourth dielectric layer  1404   d  and is connected to both the second capacitive plate  1440  and the bonding pad  1436  by a plurality of conductive vias  1424 . It should be appreciated that multiple internal circuit components may intersect the lateral trace  1432  or provide connections between the lateral trace  1432  and the bonding pad  1436 . The lateral trace  1432 , bonding pad  1436 , internal circuits therebetween, and second capacitive plate  1440  may be electrically isolated from the top or first capacitive plate  1444  by the enhanced isolation layer  1412  and other dielectric materials/layers positioned therebetween. However, it should be appreciated that the enhanced isolation layer  1412  provides a majority of the electrical isolation between the first capacitive plate  1444  and the second capacitive plate  1440 . In some embodiments, the lateral trace  1432 , bonding pad  1436 , and second capacitive plate  1440  operate at a lower voltage than the first capacitive plate  1444 . In some embodiments, the first capacitive plate  1444  and outer edges  1448  may correspond to first isolation components  1304  whereas the metal layers  1428  and elements thereof (e.g., lateral trace  1432 , bonding pad  1436 , second capacitive plate  1440 ) in the dielectric layers  1404   a - e  may correspond to second isolation components  1308  operating at a substantially different voltage than the first isolation components  1304 . 
     The phenomenon used to carry a signal between the first capacitive plate  1444  and second capacitive plate  1440  is not surprisingly a capacitive phenomenon. Thus, the plates  1440 ,  1444  may be capacitively coupled with one another, thereby facilitating the communication of signals therebetween without requiring the transmission of electrical current therebetween. It should be appreciated that other phenomenon, such as inductive phenomenon and the like could be used to carry such signals across the enhanced isolation layer  1412 . To the extent that the capacitive plates  1440 ,  1444  are used, the plates  1440 ,  1444  may be designed to overlap one another to facilitate an efficient transmission of signals between the plates  1440 ,  1444 . 
     The isolation device  1400  is also depicted to include a top pad opening  1456  and a bottom pad opening  1460 . The top pad opening  1456  is established substantially over the first capacitive plate  1444  whereas the bottom pad opening  1460  is established substantially over the bonding pad  1436 . The top pad opening  1456 , therefore, exposes the top surface of the first capacitive plate  1444  for wire bonding or the like. Similarly, the bottom pad opening  1460  exposes the top surface of the bonding pad  1436  for wire bonding or the like. The top pad opening  1456  extends through the upper passivation layer  1420  and at least some of the lower passivation layer  1416  to the first capacitive plate  1444 . In some embodiments, the top pad opening  1456  extends through a raised portion  1452  of the passivation layers  1416 ,  1420  that may have been created during deposition of the passivation layers  1416 ,  1420  on the metal structure of the first capacitive plate  1444 . 
     The bottom pad opening  1460  extends deeper into the structure of the isolation device  1440  than the top pad opening  1456 . More specifically, the bottom pad opening  1460  is shown to extend through the passivation layers  1416 ,  1420  as well as the enhanced isolation layer  1412 , the oxide layer  1410 , the nitride layer  1408 , and at least some of the top most dielectric layer  1404   e  to expose the bonding pad  1436  for wirebonding or the like. The bottom pad opening  1460  may be formed with a single etching or drilling process or with multiple processes. For instance, the bottom pad opening  1460  may be formed using a two-step formation process (e.g., etching, machining, etc.) 
     Because of the desire to maintain the isolation boundary  1212 , there may be a need to ensure that currents do not pass between the top capacitive plate  1444  and the bonding wire that will ultimately connect with the bonding pad  1436 . As such, one or more trenches  1464  may be established around the top capacitive plate  1444  to further facilitate an electrical isolation between the first isolation components  1304  and second isolation components  1308 . In the depicted embodiment, the trench  1464  is shown to completely circumscribe the top capacitive plate  1444  and the trench  1464  extends completely through the passivation layers  1416 ,  1420  in addition to partially extending into the enhanced isolation layer  1412 . By having the trench  1464  extend below the bottom surface of the top capacitive plate  1444 , the likelihood of currents passing between the capacitive plate  1444  and a bonding wire passing through the bottom pad opening  1460  is greatly reduced. It should be appreciated that the trench  1464  may be configured to extend completely through the enhanced isolation layer  1412  if desired and may also extend into the oxide layer  1410  and/or nitride layer  1408  without departing from the scope of the present disclosure. As discussed herein, the plates  1440 ,  1444  may be electrically isolated from one another. As used herein, the term “electrical isolation” refers to the ability to maintain an electrical isolation of two or more components within the device (e.g., device  1400 ) and does not necessarily mean that both components cannot be connected to a common ground or be connected to a power source outside the device  1400 . 
     In some embodiments, the depth of the trenches  1464  may be controlled using a number of different methods. Moreover, the trenches  1464  may be optional in some embodiments. More specifically, the trench(es)  1464  may extend to a bottom metal plate as there is no layer to stop such an extension. One option to limit the depth of the trench(es)  1464  is to control an exposure time, thereby controlling the amount of etching that occurs. Problematically, using time control may result in inaccurate depths and can result in high variation of depths from one device to the next. However, it may be possible to use time control to ensure that the trench  1464  cuts through at least one third the thickness of the enhanced isolation layer  1412 . The actual depth of the trench(es)  1464  may be anywhere between ⅕ and ⅔ the thickness of the enhanced isolation layer  1412 . 
     Another option to control trench depth  1464  is to utilize an etch stop layer positioned below and/or within the enhanced isolation layer  1412 . While possible, this may not be desirable due to the additional costs required to add such a layer. However, such an approach can ensure a more consistent and accurate trench  1464  depth. 
     Yet another option is to trench toward one of the bottom metal layers (e.g., a metal layer  1424  within the dielectric layers  1404   a - e ). In this way, the bottom metal layers can act as an edge stop (see  FIG. 3 ). As discussed herein, the trench  1464 , among other things, is provided to intercept and/or interrupt any residue conductive material that could possibly weaken the isolation capabilities of the device  1400 . Residue conductive materials may occur between dielectric layers  1404   a - e . The design proposed herein provides not only a trench  1464 , but a possible filling material (e.g., an optional polyimide coating). It should be appreciated, however, that the trench  1464  and similar structures discussed herein are optional structures that may not be necessary to achieve a functioning device  1400 . For instance, the bottom pad opening  1460  may be sufficiently deep and the bonding pad  1436 /capacitive pad  1440  may be sufficiently distanced away from the capacitive pad  1444  and other electrical components on the top most metal layer of the device  1400 . If such a distancing is maintained, then the need for the trench  1464  may be minimized and/or obviated. 
     With simultaneous reference now to  FIGS. 15-27 , a method  2700  (or aspects thereof) for fabricating an isolation device will be described in accordance with at least some embodiments of the present disclosure. It should be appreciated that the method  2700 , or steps thereof, can be used to manufacture or fabricate any of the isolation devices or systems depicted and described herein. Moreover, various figures will depict as so-called “intermediate device”, which could be an example of any isolation device during its intermediate stages of manufacture. It should be appreciated, however, that the term “intermediate” should not be construed as limiting these examples to only devices that are incomplete. Rather, it should be appreciated that an intermediate device may actually correspond to a completed isolation device and can be used in isolation systems without departing from the scope of the present disclosure. 
     The manufacturing process  2700  may begin by receiving an intermediate product having one or more metal layers  1428  and/or conductive vias  1424  (step  2704 ). As shown in  FIG. 15 , a first intermediate device  1500  is shown to include a plurality of dielectric layers  1404   a - e  having metal layers  1428  and conductive vias  1424  established therein. In some embodiments, some of the metal layers  1428  and conductive vias  1424  may be used to construct a seal ring stack  1468  whereas other aspects of the metal layers  1428  may be used to form the lateral trace  1432 , bonding pad  1436 , and/or second capacitive plate  1440 . The intermediate device  1500  may also include the nitride layer  1408  covering the top most dielectric layer  1404   e . The nitride layer  1408  may be provided on the dielectric layers  1404   a - e  during a flat passivation (step  2708 ) or similar type of deposition process. 
     As shown in  FIG. 16 , the method  2700  may continue with the creation of an initial opening  1604  in the nitride layer  1408  (step  2712 ). This initial opening  1604  may be formed centrally with respect to the bonding pad  1436 , meaning that the initial opening  1604  is substantially centered (within machining tolerances) with respect to the center of the bonding pad  1436 . Creation of the initial opening  1604  may result in a second intermediate device  1600 . 
       FIG. 17  depicts a next step in the process where an oxide layer  1704  is deposited over the nitride layer  1408  (step  2716 ). The deposited oxide layer  1704  may be similar or identical to oxide layer  1410  in composition, but may not correspond to a final version of oxide layer  1410 . In this third intermediate device  1700 , deposition of the oxide layer  1704  over the initial opening  1604  creates a depression  1708  in the deposited oxide layer  1704 . The depression  1708  may be coincident with the initial opening  1604 . 
     The method  2700  continues by performing a chemical and/or mechanical planarization (CMP) process on the oxide layer  1704  to create a planarized oxide layer  1804  (step  2720 ). The planarized oxide layer  1804  of the fourth intermediate device  1800  may have the same thickness as the oxide layer  1410  and the depression  1708  may be totally (or at least observably) removed from the oxide layer  1804 . 
       FIG. 19  depicts a next step where a bulk isolation material  1904  is deposited on the oxide layer  1410 ,  1804  (step  2724 ). In some embodiments, the bulk isolation material  1904  may correspond to a piece of silicon wafer that is wafer-bonded to the oxide layer  1410 ,  1804  to create the fifth intermediate device  1900 . The bulk isolation material  1904  may comprise similar or identical material properties as the enhanced isolation layer  1412 . In some embodiments, the bulk isolation material  1904  exhibits a dielectric strength of at least 800V/um, but possibly more than 1000V/um. 
     As shown in  FIG. 20 , the bulk isolation material  1904  may then be subjected to a CMP process (step  2728 ) to create a planarized enhanced isolation layer  2004 . In this sixth intermediate device  2000 , the planarized enhanced isolation layer  2004  may be similar or identical to the enhanced isolation layer  1412  in both composition and thickness. In some embodiments, the sixth intermediate device  2000  establishes an isolation distance D 1  that will ultimately control the amount of voltage difference that can be sustained. Specifically, the isolation distance D 1  may include the thickness of the planarized isolation layer  2004 , the thickness of the oxide layer  1804 , and at least the thickness of the nitride layer  1408 . The isolation distance D 1  may further include a distance between a top of the second capacitive plate  1440  and the top surface of the top most dielectric layer  1404   e . In some embodiments, the isolation distance D 1  may be approximately 5.0 um plus or minus 0.5 um. 
     After the planarization has been performed, the method  2700  may continue by building to upper metal layer  2104  for the top capacitive plate (step  2732 ). In this step, as shown in  FIG. 21 , the seventh intermediate device  2100  is shown to include a plate  2108  and outer edges  2112  as part of the upper metal layer  2104 . In some embodiments, the upper metal layer  2104  constitutes electrically conductive elements that will be connected to a first circuit  1204  whereas other metal layers (e.g., metal layers in the dielectric layers  1404   a - e ) will be connected to a second circuit  1208  that is electrically isolated from the first circuit  1204 . The upper metal layer  2104  is shown to be established directly on the planarized enhanced isolation layer  2004  and the plate  2108  is an example of the first capacitive plate  1444 . In some embodiments, the total area of the outer edges  2112  and plate  2108  is greater than an area of the second capacitive plate  1440 . As depicted, the second capacitive plate  1440  may be centered (in one or two axes) with respect to the plate  2108 . The plate  2108  and outer edges  2112  may be structurally identical to the plate  1444  and outer edges  1448 , respectively. 
     With reference to  FIG. 22 , the method  2700  continues with the development of an eighth intermediate device  2200  by depositing one or more passivation layers over the upper metal layer  2104  and enhanced isolation layer  2004  (step  2736 ). In some embodiments, a lower passivation layer  2204  and then an upper passivation layer  2208  may be deposited in this step. In some embodiments, the eighth intermediate device  2200  includes a raised portion  2212 , which may eventually correspond to raised portion  1452 . Similarly, the passivation layers  2204 ,  2208  may be similar or identical to passivation layers  1416 ,  1420 , respectively. 
     Thereafter, a first etching process may be performed to expose the first capacitive plate  1444 ,  2108  and also to create one or more isolation trenches  2312  around the first capacitive plate  1444 ,  2108  (step  2740 ). In some embodiments, both trench(es)  2312  and top pad opening  2304  may be formed during the same etching process, although this is not a requirement. Furthermore, a partial opening  2308  may be established over the bonding pad  1436 . The partial opening  2308  may have a similar or identical depth as the trench(es)  2312 . In some embodiments, the ninth intermediate product  2300  may include the openings  2304  and trench(es)  2312 , which may be similar or identical to opening  1456  and trench(es)  1464 , respectively. The partial opening  2308  may also correspond to an uppermost portion of the bottom pad opening  1460 . 
     Thereafter, as seen in  FIG. 24 , a tenth intermediate product  2400  is created by further extending the partial opening  2308  to create a bottom pad opening  2404 , which may be similar or identical to pad opening  1460  (step  2744 ). The further expansion of the bottom pad opening i 2404  may be achieved by mechanical and/or chemical etching. The bottom pad opening  2404  exposes a bonding surface  2408  of the bonding pad  1436 . 
     Thus, the method  2700  further proceeds by bonding one or more wires  2504 ,  2508  to exposed bonding pads on the eleventh intermediate device  2500  (step  2748 ). As shown in  FIG. 25 , a first bonding wire  2504  is attached to bonding pad  1436  while a second bonding wire  2508  is attached to the first capacitive plate  1444 ,  2104 . The bonding wires  2504 ,  2508  each pass through openings in the passivation layer(s)  1416 ,  1420  and the first bonding wire  2504  further passes through the enhanced isolation layer  1412 ,  2004 . Moreover, the bonding wires  1504 ,  1508  are physically separated from one another to ensure that transient currents do not inadvertently pass therebetween. In addition, the lateral distance between the bottom pad opening  1460 ,  2404  and the top pad opening  1456 ,  2304  helps to ensure that an electrical isolation is maintained between the components operating at different voltages. The lateral trace  1432  is further responsible creating this lateral separation between openings. 
     A last optional step is performed whereby an optional polyimide coating  2604  is applied to the top surface of the upper passivation layer  1420 ,  2208  (step  2752 ). In some embodiments, the polyimide coating may fill some or all of the trench(es)  1464 ,  2312 . Filling the trenches in this way may further facilitate the desired electrical isolation between the electrical components operating at a high voltage and the electrical components operating at a lower voltage. 
     With reference now to  FIGS. 28A-C , additional details of an isolation device and the system in which it operates will be described in accordance with at least some embodiments of the present disclosure. The isolation device depicted in these figures may have features similar or identical to features shown or described in connection with any of the devices discussed herein.  FIGS. 28A and 28B  depict the system view in which a first leadframe  2804  is shown supporting a first Integrated Circuit (IC) chip  2812  while a second leadframe  2808  is shown supporting a second IC chip  2816 . As can be appreciated, the first leadframe  2804  may be electrically connected to a first circuit  1204  operating at a first operational voltage whereas the second leadframe  2808  may be connected to a second circuit  1208  operating at a second operational voltage. In this configuration, it is desirable to maintain an electrical isolation between the first leadframe  2804  and second leadframe  2808 . It should be appreciated that the form factor of leadframes  2804 ,  2808  is only for illustrative purposes and should not be construed as limiting embodiments of the present disclosure to any particular type of configuration. 
     In the depicted embodiment, the first IC chip  2812  is physically mounted on the first leadframe  2804  and electrically connected to the first leadframe  2804  via one or more first bonding wires  2820 . Similarly, the second IC chip  2816  is physically mounted on the second leadframe  2808  and electrically connected to the second leadframe  2808  via one or more third bondwires  2828 . Electrical communication between IC chips  2812 ,  2816  is achieved via one or more second bondwires  2824 , which traverse between the IC chips  2812 ,  2816 . In some embodiments, the first leadframe  2804 , first IC chip  2812  (and components therein), the first bondwire(s)  2820 , and second bondwire(s)  2824  operate at a first operational voltages. 
     As shown in the detailed view of  FIG. 28C , the second bondwire(s)  2824  may be connected to a first capacitive plate of the second IC chip  2816 . Electrical signals from the second bondwire(s)  2824  may be communicated to the second capacitive plate (which is separated from the first capacitive plate via the enhanced isolation layer) via capacitive coupling or the like. The second IC chip  2816 , may therefore be considered an illustrative isolator  1216  and, more specifically, an example of an isolation device  1400  (or some other isolation device depicted or described herein). The third bondwire(s)  2828  may operate at a different operational voltage than the second bondwire(s)  2824  and the enhanced isolation layer may facilitate these different operational voltages. 
     With reference now to  FIG. 29 , additional details of a trench  2904  that can be used to facilitate electrical isolation of the metal components surrounded thereby from other components not surrounded thereby will be described in accordance with at least some embodiments of the present disclosure. The isolation device depicted in  FIG. 29  may be similar or identical to other isolation devices depicted and described herein, such as isolation device  1400  or isolation device  2600 . The views of  FIG. 29  simply illustrate further perspectives of such devices. 
     As shown in  FIG. 29 , a first capacitive plate  2908  may be provided as part of an upper metal layer and that first capacitive plate  2908  may be surrounded by one or more trenches  2904 . In the depicted embodiment, the trench  2904  fully circumscribes the first capacitive plate  2908 . The second capacitive plate  2912  is positioned directly underneath the first capacitive plate  2908 , but separated from the first capacitive plate by the enhanced isolation layer. There is a wirebond that connects directly to the first capacitive plate  2908  through top pad opening  1456 . The other wirebond is established with a lower bonding pad  1436 , which is electrically connected with the second capacitive plate  2912  via a lateral trace  1432  or some other laterally-extending conductive element. 
     As can be appreciated, any of the capacitive isolators depicted and described herein may be implemented as on-chip solutions (e.g., as a single silicon wafer). In some embodiments, the capacitive isolators may be implemented in an Integrated Circuit (IC) chip having other circuit elements provided therein. Moreover, the terms capacitive isolator and isolation capacitor may be interchangeable terms as used herein. Indeed, any system, system component, or specific device exhibiting features and/or functions of an electrical isolator as well as a capacitive coupler may be considered either a capacitive isolator or isolation capacitor. 
     Specific details were given in the description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments. 
     While illustrative embodiments of the disclosure have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed, and that the appended claims are intended to be construed to include such variations, except as limited by the prior art.