Patent Publication Number: US-8976577-B2

Title: High density magnetic random access memory

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part of U.S. patent application Ser. No. 13/441,841, filed on Apr. 7, 2012 and claims the benefit of U.S. provisional patent application No. 61/472,788, filed on Apr. 7, 2011 by the present inventors. 
    
    
     FEDERALLY SPONSORED RESEARCH 
     Not Applicable. 
     SEQUENCE LISTING OR PROGRAM 
     Not Applicable. 
     RELEVANT PRIOR ART 
     U.S. Pat. No. 5,640,343, Jun. 17, 1997—Gallagher et al. 
     U.S. Pat. No. 7,224,601, May 29, 2007—Panchula 
     U.S. Pat. No. 7,529,121, May 5, 2009—Kitagawa et al. 
     U.S. Pat. No. 7,440,339, Oct. 21, 2009—Nejad et al. 
     BACKGROUND 
     A magnetic random access memory (MRAM) using spin-induced switching is a strong candidate for providing a dense and fast non-volatile storage solution for future memory applications. An MRAM includes an array of memory cells arranged in rows and columns.  FIG. 1  shows a schematic view of an MRAM cell employing a spin-induced writing mechanism according to a prior art. The cell comprises a magnetoresistive element (or a magnetic tunnel junction) J, a selection transistor T, a bit line BL, a word line WL, and a source line SL. The bit and word lines are formed in different layers and intersect each other in space. The magnetoresistive (MR) element J and the selection transistor T are connected in series and disposed in a vertical space between the intersecting bit and word lines. They are connected to the source line SL at one end and to the bit line BL at another end. The word line is connected to a gate terminal of the selection transistor T. The MR element J comprises at least a pinned (or reference) layer  12  with a fixed direction of magnetization (shown by a solid arrow), a free (or storage) layer  16  with a reversible magnetization direction (shown by a dashed arrow), and a tunnel barrier layer  14  disposed between the pinned and free magnetic layers. The direction of the magnetization in the free layer  16  can be controlled by a direction of a spin-polarized current I S  running through the element J in a direction perpendicular to a film surface. The spin-polarized current I S  in the MR element is reversible or bidirectional. A resistance of the MR element depends on a mutual orientation of the magnetizations in the magnetic layers  12  and  16 . The resistance is low when the magnetization directions in the layers  12  and  16  are parallel to each other (logic “0”), and high when the magnetization directions are antiparallel (logic “1”). A difference in resistance between two magnetic states can exceed several hundred percent at room temperature. 
       FIG. 2  shows a circuit diagram of a portion of an MRAM  20  with spin-induced switching according to a prior art. The MRAM  20  includes an array  22  of memory cells C 11 -C 33  (other cells are not shown) disposed in a vertical space between pluralities of parallel bits and parallel word lines at their intersections. Each memory cell comprises an MR element J and transistor T connected in series. A plurality of parallel bit lines BL 1 -BL 3  is connected to a bit line driver  24 . A plurality of the word lines WL 1 -WL 3  is connected to a word line driver  26 . A plurality of the parallel source lines SL 1 -SL 3  is connected to a source line driver  28 . Selection of a memory cell in the array  22  is provided by applying a suitable signal to appropriate bit and word lines. For instance, to select the memory cell C 22  that is located at the intersection of the bit line BL 2  and the word line WL 2 , the signals need to be applied to these lines through the drivers  24  and  26 , respectively. 
     Cell size is one of the key parameters of MRAM. It substantially depends on the size and number of selection transistors supplying a spin-polarized write current to an MR element. The number of the transistors controlling the write current usually varies from one or two per MR element. It depends on the saturation current of the selection transistor and magnitude of the spin-polarized current required to cause switching of the MR element. Frequently, especially for MR elements having in-plane magnetization in the magnetic layers, one selection transistor cannot provide the required spin-polarized current due to its saturation. This obstacle prevents MRAM cell size reduction. 
     Another important parameter of the MRAM is a write speed. The write speed depends on the magnitude of the spin-polarized current running through the MR element. High speed (short duration of the write current pulse) requires higher magnitude of the spin-polarized current that can be limited by the saturation current of the selection transistor or by a breakdown of the tunnel barrier layer. 
     The present disclosure addresses to the above problems. 
     SUMMARY 
     In accordance with one embodiment a magnetic memory device comprises: a substrate and a stack of planar memory arrays disposed on a substrate surface, each memory array comprising a plurality of parallel first conductive lines, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction being disposed at an intersection region, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance, wherein the electrical resistance of said each magnetic tunnel junction is controlled by a bidirectional spin-polarized current running between the first and second terminals in a direction perpendicular to the substrate surface. 
     In accordance with another embodiment a magnetic memory device comprises: a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array comprising a plurality of parallel first conductive lines, each first conductive line comprising a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction comprising a controllable electrical resistance, being disposed at an intersection region and electrically coupled to one of the first parallel conductive lines at a first end and to one of the second parallel conductive lines at a second end, wherein the electrical resistance of said each magnetic tunnel junction is controlled by a joint effect of a magnetic field and a bidirectional spin-polarized current applied simultaneously to said each magnetic tunnel junction. 
     In accordance with yet another embodiment a magnetic memory device comprises: a substrate, a plurality of planar memory arrays vertically stacked on the substrate, each planar memory array comprising a plurality of parallel first conductive lines, a plurality of parallel second conductive lines overlapping the first conductive lines in a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction being disposed at an intersection region and comprising a free ferromagnetic layer having a reversible magnetization direction, a pinned ferromagnetic layer having a fixed magnetization direction, and a tunnel barrier layer disposed between the free ferromagnetic layer and the pinned ferromagnetic layer, said each magnetic tunnel junction being electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal; a circuitry area disposed on the substrate beneath the plurality of planar memory arrays and comprising an electrical circuitry; and a plurality of interconnects disposed adjacent to the circuitry area to provide an electrical coupling of the plurality of first conductive lines and the plurality of second conductive lines to the electrical circuitry, wherein an electrical resistance of said each magnetic tunnel junction depends on a mutual orientation of the magnetizations directions in the free and pinned ferromagnetic layers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic view of a memory cell with spin-induced switching according to a prior art. 
         FIG. 2  is a circuit diagram of a magnetic random access memory with spin-induced switching according to a prior art. 
         FIGS. 3A and 3B  is a circuit diagram of magnetic random access memory with a spin-induced switching according to an embodiment of the present disclosure illustrating writing of logic “0” and logic “1” to a memory cell. 
         FIG. 4  is a schematic view of a memory cell with a spin-induced switching according to an embodiment of the present disclosure. 
         FIG. 5  is a schematic view of a memory cell with a hybrid switching mechanism. 
         FIG. 6A  is a circuit diagram of magnetic random access memory with a hybrid switching mechanism illustrating writing a logic “0” to a memory cell according to another embodiment of the present disclosure. 
         FIG. 6B  is a circuit diagram of magnetic random access memory with a hybrid switching mechanism illustrating writing logic “1” to several memory cells simultaneously according to another embodiment of the present disclosure. 
         FIG. 7  is a circuit diagram of the magnetic random access memory shown in  FIG. 6A  during a read operation. 
         FIGS. 8A and 8B  are plane and cross sectional views of the MR elements made of in-plane magnetic materials, respectively. 
         FIGS. 9A and 9B  are plane and cross sectional views of the MR elements made of perpendicular magnetic materials, respectively. 
         FIG. 10  is a 3D-configuration of a magnetic memory employing a spin-induced switching mechanism according to an embodiment of the present disclosure. 
         FIGS. 11A and 11B  illustrate a configuration of bit lines and word lines shared by cell arrays in a memory block shown in  FIG. 10  and the relation between bit line interconnects and word line interconnects. 
         FIG. 12  illustrates a 3D-configuration of magnetic memory employing a hybrid writing mechanism according to another embodiment of the present disclosure 
         FIGS. 13A and 13B  illustrate a configuration of bit lines and word lines shared by cell arrays in a memory block shown in  FIG. 12  and the relation between bit line interconnects and word line interconnects. 
     
    
    
     EXPLANATION OF REFERENCE NUMERALS 
       12  pinned (or reference) magnetic layer 
       14  tunnel barrier layer 
       16  free (or storage) magnetic layer 
       20 ,  30 ,  60 ,  100 ,  120  magnetic random access memory (MRAM) 
       22  array of memory cells 
       24  bit line driver 
       26  word line driver 
       28  source line driver 
       52  conductor 
       54  magnetic flux concentrator 
       56  non-magnetic gap 
       1010  control circuitry area 
       1012  memory block 
       1014  bit line interconnects 
       1016  word line interconnects 
       1024  bit line interconnect contact area 
       1026  word line interconnect contact area 
     BL, BL 1 , BL 2 , BL 3  bit line 
     C, C 11 -C 33  memory cell 
     J, J 11 -J 33  magnetic tunnel junction 
     SA 1 -SA 3  sense amplifier 
     SL, SL 1 , SL 2 , SL 3  source line 
     T, T 11 -T 33  selection transistor 
     Tb 1 -Tb 6  bit line transistor 
     Ts 1 -Ts 3  read transistor 
     Tw 1 -Tw 6  word line transistor 
     WL, WL 1 , WL 2 , WL 3  word line 
     DETAILED DESCRIPTION 
     Embodiments of the present disclosure will be explained below with reference to the accompanying drawings. Note that in the following explanation the same reference numerals denote constituent elements having almost the same functions and arrangements, and a repetitive explanation will be made only when necessary. 
     Note also that each embodiment to be presented below merely discloses a device or method for embodying the technical idea of the present disclosure. Therefore, the technical idea of the present disclosure does not limit the materials, structures, arrangements, and the like of constituent parts to those described below. The technical idea of the present disclosure can be variously changed within the scope of the appended claims. 
     Refer now to the drawings,  FIG. 1 ,  FIG. 4 , and  FIG. 5  which illustrate exemplary aspects of the MR element. Specifically, these figures illustrate the MR element having a multilayer structure with a perpendicular direction of magnetization in the magnetic layers. The direction (or orientation) of the magnetization in the magnetic layers are shown by solid or dashed arrows. The magnetization in the magnetic layers can be directed perpendicular or in-plane to surface of the magnetic layers. The MR element can store binary data by using steady logic states determined by mutual orientation of the magnetizations in the magnetic layers separated by a tunnel barrier layer. The logic state “0” or “1” of the MR element can be changed by a spin-polarized current running through the element in the direction across the tunnel barrier layer or perpendicular to a film surface. 
     The MR element herein mentioned in this specification and within the scope of the claims is a general term of a tunneling magnetoresistance (TMR) element using an insulator or semiconductor as the tunnel barrier layer. Although the above mentioned figures each illustrate the major components of the MR element, another layer (or layers) such as a seed layer, a pinning layer, a cap layer, and others may also be included. 
       FIGS. 3A and 3B  show a circuit diagram of a portion of an MRAM  30  according to an embodiment of the present disclosure. The memory includes an array  22  of memory cells C 11 -C 33 , a plurality of parallel bit lines BL 1 -BL 3  connected at their end to a bit line driver  24 , and a plurality of parallel word lines WL 1 -WL 3  connected at their end to word line driver  26 . 
     Each memory cell comprises an MR element without a selection transistor. The MR element is connected to the appropriate bit and word lines at its ends and disposed at the intersection of the lines in a vertical space between them. A schematic view of the memory cell of the MRAM  30  is shown on  FIG. 4 . The MR element J has a pillar structure and comprises at least a pinned magnetic layer  12  having a fixed magnetization direction (shown by a solid arrow), a free magnetic layer  16  having a variable (or reversible) magnetization direction (shown by a dashed arrow), and a tunnel barrier layer  14  disposed between the pinned and free magnetic layers. The free magnetic layer  16  can be made of a magnetic material with a substantial spin-polarization and has a the magnetization directed substantially perpendicular to a layer surface in its equilibrium state. For example, the free magnetic layer  16  can be made of (Co 30 Fe 70 ) 85 B 15  (% atomic) alloy having a thickness of about 1.5 nm. The pinned magnetic layer  12  can be made of a magnetic material with a substantial spin-polarization and has the magnetization directed substantially perpendicular to a layer surface. For example, the pinned magnetic layer can be made of the (Co 30 Fe 70 ) 85 B 15  (% atomic) alloy having a thickness of about 2.5 nm. The tunnel barrier layer  14  can be made of MgO having a thickness of about 1.1 nm. The free, tunnel barrier and pinned layers form a substantially coherent texture having a BCC (body-centered cubic) structure with (001) plane orientation. The MR element with this crystalline structure provides a substantial tunneling magnetoresistance (TMR≧100% at room temperature) and a density of spin-polarized write current of about 1·10 6  A/cm 2  or less. These parameters are essential for MRAM. 
     In the MRAM  30  shown in  FIGS. 3A and 3B  the pluralities of the conductive bit and the word lines intersect each other but are spaced from each other in direction perpendicular to a plane of substrate (not shown). Each of the memory cells C 11 -C 33  comprises an appropriate MR element J 11 -J 33  that is disposed at an intersection of a bit and word line in the vertical space between them. The MR element is electrically connected to the intersecting bit and word lines at its opposite ends. For instance the memory cell C 22  comprises the MR element J 22  disposed at the intersection of the bit line BL 2  and the word line WL 2 . The MR element J 22  is electrically connected to the word line WL 2  at its first end and to the bit line BL 2  at its second end. 
     The bit lines BL 1 -BL 3  extend in the X-direction. They are electrically connected at one end to a bit line driver  24  that includes CMOS transistors Tb 1 -Tb 6 . For example, the bit line BL 2  is connected at one end to a common drain terminal formed by an n-type transistor Tb 3  and p-type transistor Tb 4 . A source terminal of the p-type transistor Tb 4  is connected to a power supply. A source terminal of the n-type transistor Tb 3  is connected to a ground. Similarly the bit lines BL 1  and BL 3  are connected to the pairs of CMOS transistors Tb 1 , Tb 2  and Tb 5 , Tb 6 , respectively. Gate terminals of the transistors Tb 1 -Tb 6  are connected to the bit line driver  24 . The bit line driver  24  operates as a row selection switch. 
     The word line WL 1 -WL 3  extend in the Y-direction crossing the X-direction. One end of each word line WL 1 -WL 3  is connected to the word line driver  26 . The driver  26  comprises a plurality of read/write circuits. Each of the read/write circuits includes at least a pair of CMOS transistors comprising one of p-type transistors Tw 2 , Tw 4  or Tw 6  and one of n-type transistors Tw 1 , Tw 3  or Tw 5  connected in series to each other, and one of a sense amplifiers SA 1 -SA 3 . Each of the transistors pairs Tw 1  and Tw 2 , Tw 3  and Tw 4 , and Tw 5  and Tw 6  is connected to a power supply at a source terminal of the appropriate p-type transistor and to the ground at a source terminal of the appropriate n-type transistor. The word line is connected to a common drain terminal of the CMOS transistor pair and to one input terminal of the sense amplifier SA through a read transistor Ts. For example, the word line WL 2  is connected by its end to the common drain terminal formed by the transistor Tw 3  and Tw 4  and to the first input terminal of the sense amplifier SA 2  through the read transistor Ts 2 . Second input terminal of the sense amplifier SA 2  is connected to a reference element (not shown). Gates of the transistors Tw 1 -Tw 6  are connected to the word line driver  26 . The driver  26  operates as a column selection switch. 
     The sense amplifier SA 1 -SA 3  comprises at least two inputs. One input of the amplifier is connected to the end of the word line WL 1 -WL 3  and to the common drain terminal of the transistor pair by means of the read transistor Ts 1 -Ts 3 . The other input of the sense amplifier is connected to a reference element (not shown). The sense amplifier judges a data value of the MR element inside of the selected memory cell based on a reference signal Ref. 
     The memory  30  shown in  FIGS. 3A and 3B  comprises the array  22  of the MR elements J 11 -J 33  disposed above the silicon wafer (not shown). The selection transistors Tb 1 -Tb 6  and Tw 1 -Tw 6  may be positioned along a perimeter of the array  22 . The wafer area located underneath of the memory array may not be occupied by the selection transistors and can be used for other electrical circuits. Hence, the present design can provide a substantial reduction of a chip/die size. Moreover, the peripheral location of the selection transistors provides a possibility of using large selection transistors or several transistors providing a substantial write current that is essential for high speed writing. 
     The MRAM  30  shown in  FIGS. 3A and 3B  employs a spin-induced switching mechanism of the MR elements. According to spin-induced switching the orientation of magnetization in the free layer  16  can be reversed by a spin-polarized current I S  running through the MR element ( FIG. 4 ). Electrons of the write current have a substantial degree of spin polarization that is predetermined by magnetic properties of the pinned layer  12 . The spin-polarized electrons running through the free layer  16  transfer a moment of their spin causing the magnetization in the free layer to change its direction. Direction of the magnetization in the free layer  16  can be controlled by a direction of the spin-polarized current I S  running through the MR element. The direction of the spin-polarized current in the MR element shown on  FIG. 4  corresponds to writing a logic “0” or to parallel orientation of magnetization directions in the free  16  and pinned  12  magnetic layers. 
       FIG. 3A  shows writing of a logic “0” to the MR element J 22  of the memory cell C 22 . A switching current I S  is produced in the MR element by applying appropriate input signals to the gate of the transistor Tb 4  (Write  0 ) and to the gate of the transistor Tw 3  (Write  0 ). Both transistors are opened. The spin-polarized current I S  is running from the power supply (not shown) through the transistor Tb 4 , bit line BL 2 , MR element J 22 , word line WL 2 , and transistor Tw 3  to the ground. The appropriate bit and word lines, and MR element are shown in bold. For the MR element having a configuration shown in  FIG. 4  the current I S  is running in the direction from the free layer  16  to the pinned layer  12  through the tunnel barrier layer  14 . The spin-polarized conductance electrons are moving in the opposite direction from the pinned layer  12  to the free layer  16 . For the given direction of the current I S,  the magnetization in the free layer  16  will be directed in parallel to the magnetization direction of the pinned layer  12 . This mutual orientation of the magnetizations corresponds to a low resistance state of the MR element or to a logic “0”. 
       FIG. 3B  illustrates writing logic “1” to the MR elements J 22 . The write current I S  is supplied to the MR element J 22  by simultaneously applying an appropriate input signal to the gate of the transistors Tb 3  (Write  1 ) and Tw 4  (Write  1 ). The transistors are opened and the current I S  is running from the transistor Tw 4  to the transistor Tb 3  through the word line WL 2 , MR element J 22 , and bit line BL 2  (shown in bold). In the MR element J 22  having a configuration shown in  FIG. 4  the spin-polarized current I S  is running in the direction from the pinned layer  12  to the free layer  16 . This direction of the spin-polarized current can direct the magnetization in the free layer  16  anti parallel to the magnetization direction of the pinned layer  12 . This mutual orientation of the magnetizations corresponds to a high resistance state or to a logic “1”. 
     According to theory, the magnitude of the minimum spin-polarized current that is required to reverse the magnetization direction in the free layer is given by 
                     I     G   0       =       -         (       2   ⁢   e     h     )     ⁢     (     α   ⁢           ⁢     M   S     ⁢   V     )           g   ⁡     (   θ   )       ⁢   p         ⁢     H   EFF               (   1   )               
where e is an electron charge, h is Planck&#39;s constant, α is Gilbert&#39;s damping constant, M S  is saturation magnetization of the free layer material, V is volume of the free layer, and p is a spin polarization of the current. The factor g(θ) depends on the relative angle θ between vectors of magnetization (shown by arrows in  FIG. 4 ) in the pinned  12  an free  16  layers. The value of the factor g(θ) is minimal and close to zero when the vectors of the magnetizations in the free and pinned layers are parallel or anti parallel to each other (θ is equal to 0 or 180 degrees). The factor g(θ) has its maximum value when the vectors of magnetizations in the layers are perpendicular to each other (the angle θ is equal to 90 or 270 degrees). The effective magnetic field H EFF  acting on the free layer depends on the direction of magnetization (in-plane or perpendicular) in the pinned and free layers. The effective field is given by the following equations for the in-plane and for perpendicular magnetic materials, respectively:
 
 H   EFF//   =H   K// +2 πM   S   +H   APP   +H   DIP   (2)
 
 H   EFF⊥   =H   K⊥ −4 πM   S   +H   APP   +H   DIP ,  (3)
 
where H K//  and H K⊥ , are the field of uniaxial crystalline anisotropy of in-plane and perpendicular magnetic material, respectively; H APP  and H DIP  are the applied external field and the dipole field from the pinned layer acting on the free layer. The factor −4πM S  arises from the demagnetizing field of the thin film geometry of the free layer having the perpendicular anisotropy. The same factor for the free layer with in-plane anisotropy is equal to +2πM S . Hence, the MTJ with perpendicular anisotropy may require substantially smaller (depends on H K  and M S ) switching current than that with similar parameters but having the in-plane anisotropy.
 
     The direction of the magnetization in the free layer  16  of the MR element in its equilibrium states can be parallel or anti-parallel to the magnetization direction in the pinned layer. At these conditions the switching current that is required to reverse the magnetization direction in the free layer has its maximum value. Moreover, the magnitude of the current depends significantly on the duration of the current pulse. The magnitude of the switching current is almost inversely proportional to the pulse duration. Hence, the high speed writing (short current pulse) requires high switching current. The magnitude of the switching current is limited by the probability of a tunnel barrier layer breakdown. The above obstacles limit switching speed and endurance of MRAM with spin-induced switching. 
     The equation (1) suggests that the spin-polarized write current can be reduced significantly by changing the angle θ between the vectors of the magnetization in the free and pinned layers. Since the orientation of magnetization in the pinned layer  12  is fixed, the angle θ can be changed by tilting the magnetization in the free layer  16  from its equilibrium state. Tilting of the magnetization of the free layer  16  can be provided by applying a bias magnetic field along a hard magnetic axis of the free layer  16 . 
       FIG. 5  shows a schematic view of the memory cell comprising an MR element with perpendicular magnetization in the pinned  12  and free  16  magnetic layers along with adjacent bit BL and word WL lines. In addition to the spin-polarized switching current I S  a bias current I B  is further supplied to the bit line BL. The bias current I B  running through the bit line BL produces a bias magnetic field H B  (shown by arrow) that is applied along the hard axis of the free layer  16 . To increase the bias magnetic field locally, in vicinity of the MR element for further reducing the bias current I B,  the bit line BL comprises a conductive wire  52  and a magnetic flux concentrator (magnetic flux cladding)  54 . The magnetic flux concentrator  54  is made of a soft magnetic material having a high permeability and a low coercivity such as NiFe. The flux concentrator  54  comprises a non-magnetic gap  56  formed on a side of the bit line BL facing the MR element. The free layer  16  is disposed adjacent to the non-magnetic gap  56  where the bias magnetic field H B  has a maximum. Additional layers, such as a seed layer can be placed between the free layer  16  and the bit line BL. Insertion of the additional layer (or layers) between the free magnetic layer  16  and the bit line BL can result in a reduction of the bias field. The magnetic field H B  decreases almost inversely proportional with the distance between the free layer  16  and the bit line surface containing the non-magnetic gap  56 .  FIG. 5  illustrates one exemplary implementation where a magnetic cladding is wrapped around a bit line that carries the bias current. Other magnetic flux cladding designs may also be used. The magnetic flux cladding can be used for a word line as well. 
     The bias magnetic field H B  generated by the bias current I B  is proportional to the current. For example, a current of 0.1 mA can generate a bias magnetic field of about 10 Oe in the vicinity of the MR element made with 65 nm technology node. This magnitude of the bias field H B  is not sufficient to cause an unwanted reversal of the magnetization in the memory cells exposed to the bias field. The reversal of the magnetization can be achieved when both the bias magnetic field H B  and spin-polarized current I S  affect the selected MR element simultaneously. Hence the proposed hybrid writing mechanism provides a good selectivity of the MR elements in the array and significant reduction of the spin-polarized current I S . That is important for achieving a high endurance of MRAM operating at high speed, especially. 
       FIGS. 6A and 6B  show a circuit diagram of a portion of MRAM  60  employing a hybrid write mechanism. The memory  60  comprises the bit line driver  24  connected to the opposite ends of the bit lines BL 1 -BL 3 . The word lines WL 1 -WL 3  are connected at one end to the word line driver  26 . 
     To write a logic “0” to the MR element J 22  ( FIG. 6A ) a bias current I B  is supplied to the bit line BL 2  by applying an appropriate input signal to the gate of transistor Tb 3  (Write  0 ) and to the gate of the transistor Tb 4  (Write  0 ). The bias current I B  running through the bit line BL 2  produces a bias magnetic field that is applied along the hard axis of the free layer. The bias field causes a tilt of the magnetization vector in the free layer from its equilibrium state that is perpendicular to the film surface. The magnitude and duration of the bias magnetic field can be controlled effectively by the input signal “Write  0 ” and “Write  0 ” applied to the gate of the transistor Tb 3  and Tb 4  respectively. The bias current I B  alone cannot cause a reversal of the magnetization direction in the MR element J 22  and adjacent to the bit line BL 2  elements J 21  and J 23 . Switching of the magnetization direction in the free layer is a joint effect of the bias magnetic field and a spin momentum transfer of polarized electrons of the current I S  running through the MR element. To cause switching the spin-polarized current I S  is supplied to the MR element J 22 . The current I S  is running from the transistors Tb 3  to the transistor Tw 3  through the MR element J 22  located at the intersection of the bit line BL 2  and word line WL 2  (shown in bold). Simultaneous effect of the bias magnetic field and spin-polarized current results in a logic state reversal of the MR element J 22 . 
     The input signals applied to the gate of the transistors Tb 3 , Tb 4 , and Tw 4  are synchronized in time. Pulses of the currents I B  and I S  can overlap each other partially (shifted in time) or completely. The order of the pulses at partial overlapping can be any. The transistor Tb 4  should be opened while any of the transistors Tb 3  or Tw 4  are opened. 
     The memory  60  also provides a possibility of simultaneous writing to the several MR elements having electrical contact with the energized bit line BL 2  ( FIG. 6B ). The bias current is supplied to the bit line BL 2  by applying an appropriate input signal to the gate of the transistors Tb 3  (Write  1 ) and Tb 4  (Write  1 ). The bias current I B  produces a bias magnetic field along the entire line and tilts the direction of the magnetization in all MR elements adjacent to the bit line. This field is not sufficient to cause a reversal of the magnetization directions in the energized MR elements. To accomplish reversal a spin-polarized current needs to be applied to the element.  FIG. 6B  shows a circuit diagram of a portion of memory  60  during writing logic “1” to the memory cells C 22  and C 23  simultaneously when a bias current is applied to the line BL 2 . The appropriate input signals “Write  1 ” are applied to the gate of the transistors Tw 4  and Tw 6  connected to the end of the word lines WL 2  and WL 3 , respectively. The MR elements J 22  and J 23  located at the intersection of the word lines WL 2  and WL 3  with a bit line BL 2  are exposed to the cumulative effect of the bias magnetic field produced by the bias current I B  and spin-polarized current I S  running through the elements. 
     Data can be written to the memory cells C 21 , C 22 , and C 23  at the same time by applying an appropriate signal to the gate of the transistors Tw 1  or Tw 2 , Tw 3  or Tw 4 , and Tw 5  or Tw 6 . Simultaneous writing to several memory cells can provide significant reduction of a write energy per bit by means of more effective use of the bias current. 
     The transistors Tb 1 -Tb 6  connected to the bit lines BL 1 -BL 3  and the transistors Tw 1 -Tw 6  connected to the word lines WL 1 -WL 3  are exposed to different magnitudes of the current running through them during writing. Therefore they can have different saturation currents that can be achieved by using different size of transistors or by using several transistors. For instance the transistors Tb 1 -Tb 6  can have higher saturation current than the transistors Tw 1 -Tw 6 . The transistors Tw 1 -Tw 6  control the switching spin-polarized current in the MR elements of the array  22 . 
       FIG. 7  shows a circuit diagram of the memory  60  according in the read mode of operation. To read the data stored in the memory cell C 22  an appropriate input signal is applied to the transistors Tb 3  (Read), Tw 3  (Read), and Ts 2  (Read). A signal produced by a read current I R  running through the MR element J 22  represents a read signal that is proportional to the resistance of the MR element: high resistance for logic “1” and a low voltage for logic “0”. The read current I R  is smaller than the spin-polarized write current I S  and cannot cause the reversal of the magnetization in the free layer of the MR element J 22  specifically due to absence of the bias magnetic field. The read signal is applied to one input of the sense amplifier SA 2  through the opened transistor Ts 2 . A reference read signal Ref from a reference memory cell (not shown) is applied to another input of the sense amplifier SA 2 . The output of the sense amplifier SA 2  provides information about the data stored in the memory cell C 22 . 
     The MR elements of the disclosed MRAMs can use magnetic materials with in-plane and/or perpendicular direction of the magnetization in the equilibrium state. Magnetic materials exhibiting in-plane magnetization direction may have an uniaxial magneto-crystalline anisotropy that is not sufficient to provide a required thermal stability. To overcome this disadvantage the MR element employing in-plane magnetic materials (in-plane MR elements) can use a shape anisotropy in addition to the magneto-crystalline anisotropy. For that reason the MR element (or the free layer only) can have a shape of an elongated ellipse with an easy axis of the magneto-crystalline anisotropy oriented along a major axis of the ellipse. The ratio between the minor and major axis of the elliptical MR element can vary in the range from about 1:1.1 to about 1:5 depending on the technology node F of the manufacturing process. Frequently the technology node F can be equal to the size of the minor axis of the MR element. For example, the MR elements built using the technology node F=65 nm can have the ratio between the minor and major axis of about 1:2. It means, that lengths of the minor and major axis of the MR element are 65 nm and 130 nm, respectively. 
     Magnetic materials exhibiting a perpendicular magnetization direction usually have a substantial uniaxial magneto-crystalline anisotropy that can be significantly higher than that of the in-plane magnetic materials. For that reason the perpendicular MR elements having any shape, including round, can provide the required thermal stability. 
       FIGS. 8A and 8B  show plane and cross-sectional views of the MR elements made of the in-plane magnetic materials, respectively. The major axis of the elliptical MR element J and the easy axis of the magnetic anisotropy (shown by an arrow) of the free  12  and pinned  16  magnetic layers are oriented in parallel to each other and to the bit line BL, as well. In the given exemplary embodiment the bit line BL is used to carry a bias current I B . The bias current running through the bit line BL can produce a bias magnetic field H B  that is applied along the hard magnetic axis of the free layer (along the minor ellipse axis). The bias magnetic field H B  can tilt the magnetization direction of the free layer  12  from its equilibrium state. That can result in a reduction of the spin-polarized switching current I S  required for writing to the MR element J. The elliptical shape of the in-plane MR element J may cause a cell size increase. For instance, in the given exemplary embodiment shown in  FIG. 8A  the cell size is about of 6 F 2 . 
     MR elements made of magnetic materials with a perpendicular magnetization direction (anisotropy) are shown in  FIGS. 9A and 9B . The perpendicular MR element J can be formed in a round shape providing similar or higher thermal stability than the in-plane MR element having a similar thickness of the free layer and made with the same technology node F. A size of the perpendicular memory cell C can be of about 4 F 2 . Hence, the perpendicular MR elements can provide a substantial increase of the memory cell density along with a reduction of the write current. 
     The arrays  22  of the memory cells shown in  FIG. 8A  and  FIG. 9A  can be arrange in a three dimensional (3D) configuration.  FIG. 10  shows a 3D-configuration of the magnetic memory  100  employing two-dimensional (2D) magnetic memory  30  with spin-induced switching ( FIGS. 3A and 3B ). In the given exemplary embodiment the 3D-MRAM  100  includes a substrate (not shown) comprising a control circuitry area  1010  for use in formation of column-related and row-related control circuits therein, and a memory block  1012  stacked thereon. 
     The memory block  1012  includes four layers of the memory cell arrays  22 - 1 ,  22 - 2 ,  22 - 3 , and  22 - 4  stacked one above another in the vertical direction (Z-direction) above a semiconductor substrate (or wafer). The layers of the memory cell arrays are electrically isolated from each other by insulator layers (not shown). Note that the number of the memory cell arrays in the block  1012  can be any. Each of the memory cell arrays  22 - n  comprises magnetic memory cells C arranged in rows and columns. The memory cell C can use a MR element J employing magnetic materials with in-plane ( FIGS. 8A and 8B ) or perpendicular ( FIGS. 9A and 9B ) magnetization direction (anisotropy). 
     As shown in  FIG. 10 , the control circuitry area  1010  is formed on the semiconductor substrate (not shown) immediately beneath the memory block  1012 . The control circuitry area  1010  can include a row-related control circuitry comprising a bit line driver  24 , and a column-related control circuitry comprising a column driver  26 . 
     Connections of the bit lines BL and the word lines WL in the stacked memory cell arrays  22 - n  to the drivers  24  and  26 , respectively require vertical conductive lines (via-contacts or interconnects) located on the sides of the memory block  1012 . The bit lines BL can have one end connected to the bit line driver  24  by means of the vertical bit line interconnects  1014  that can be formed in a bit line interconnect contact area  1024 . Respectively, the word lines WL can have one end connected to the word line driver  26  by vertical word line interconnects  1016  formed in a word line contact area  1026 . The interconnect contact areas  1024  and  1026  can be provided along two sides of the control circuit area  1010 . For example, the bit line interconnect contact area  1024  can be located along a side that is parallel to Y-direction, and the word line interconnect contact area  1026  can be located along a side of the control circuit area  1010  that is parallel to X-direction. 
     The configuration of the bit lines BL and word lines WL shared by the cell arrays  22 - 1 - 22 - 4  in the memory block  1012  and the relation between the bit line interconnects  1014  and the word line interconnects  1016  are described with reference to  FIGS. 11A and 11B .  FIG. 11A  is an X-Z-sectional view of the memory block  1012  taken along a bit line BL.  FIG. 11B  shows an Y-Z-sectional view of the memory block  1012  taken along a word line WL.  FIGS. 11A and 11B  show examples of the interconnects configured for the bit lines BL and word lines WL. 
     As shown in  FIG. 11A , each bit line of the memory cell arrays  22 - 1  through  22 - 4  can be independently connected to the bit line driver  24  ( FIG. 10 ) by means of a separate vertical bit line interconnect  1014 . Each bit line can be electrically coupled to the driver  24  at one of its ends through the interconnect  1014 . In some circumstances, a bit line may be connected to the bit line driver  24  by several interconnects to maintain an uniform signal along a length of the line. The given configuration provides a possibility of an individual selection of the bit lines in the memory block  1012 . 
       FIG. 11B  illustrates a configuration of the word lines in the memory block  1012 . In the given exemplary embodiment one word line of each of the memory cell arrays  22 - 1  through  22 - 4  can be electrically coupled to an appropriate word line interconnect  1016 . The four word lines can be coupled in common to the interconnect  1016  at one of their ends. In some circumstances, to supply an uniform value of the signal along the entire length of the word lines; the lines can be coupled to the word line driver  26  ( FIG. 10 ) by two or more interconnects  1016 . One word interconnect line  1016  can provide a simultaneous electrical coupling to the word line drive  26  of four word lines. The word line interconnect  1016  can run through all memory cell arrays  22 - 1  through  22 - 4 . 
     Selection of a memory cell (MR element) in the memory block  1012  can be achieved by applying appropriate signals to one bit interconnect line  1014  and to one word interconnect line  1016 . The selected memory cell is located at the intersection of the activated bit and word lines. An operation of the 3D-memory  100  is similar to the operation of the 2D-memory  30  disclosed above ( FIGS. 3A and 3B ). 
     During writing a logic “0” to the selected MR element J 22  ( FIG. 3A ), non-selected elements J 21 , J 23  and others which are electrically connected to the energized bit line BL 2  may change their logic state due to a spin-polarized leakage current through them to the ground. To prevent the unwanted writing to the non-selected MR elements the word line driver  26  can apply an intermediate voltage to these elements. The value of the intermediate voltage is less than that of the power supply but higher than the ground voltage. The intermediate voltage can reduce the spin-polarized leakage current in the non-selected MR elements to the value that is less than the current necessary to reverse the magnetization direction in a free layer. This method can be used during a read operation ( FIG. 7 ). 
     During writing logic “1” ( FIG. 3B ) the intermediate voltage can be applied to the non-selected MR element J 12 , J 32  and other coupled to the energized word line WL 2  by the bit line driver  24 . 
     In the given exemplary embodiment the bit lines BL can be independently driven on a layer basis while the word lines WL can be commonly connected in all the layers (one line per layer). Note that the word lines WL may also be independently driven on a layer basis. Alternatively, the bit lines BL may be commonly connected while the word lines WL are independently driven. The bit lines BL and the word lines WL may be configured such that at least one of them is shared by the upper and lower layers. In this case, the upper and lower memory cells in the arrays  22 - n  are arranged symmetric about the common line. The arrangement of the MR elements J is not limited to the shown example. 
       FIG. 12  shows another embodiment of the 3D magnetic memory according to the present disclosure. The magnetic memory  120  employs a hybrid writing mechanism that is disclosed above ( FIGS. 6A and 6B ). A configuration of the bit lines BL and word lines WL in the 3D-memory  120  is specified in  FIGS. 13A and 13B  that illustrate X-Z and Y-Z-sectional views taken along one of the bit lines and one of the word lines, respectively. 
     As in the 3D-memory  100 , the bit lines BL in the memory  120  can be independently connected to the bit line driver  24  by means of the appropriate vertical bit line interconnects  1014  ( FIG. 13A ). More specifically, both ends each of the bit lines can be independently electrically coupled to the driver  24 . The vertical bit line interconnects  1014  can be located on the opposite sides of the memory block  1012  along the Y-direction. The word lines WL of the 3D-memory  120  can have similar configuration as the word lines of the 3D-memory  100 . Hence, the word lines WL in all the layers in one Y-Z-section can be commonly connected to an appropriate vertical word line interconnect  1016 . An operation of the 3D-memory  120  is similar to the operation of the 2D-memory  60  ( FIGS. 6A and 6B ) described above. 
     During writing a logic “0” to the selected MR element J 22  ( FIG. 6A ), non-selected magnetically biased elements J 21 , J 23  and others which are electrically and magnetically coupled with the energized bit line BL 2  may change their logic state due to a spin-polarized current leaking through them to the ground. To prevent the unwanted writing to the non-selected MR elements the word line driver  26  can apply the intermediate voltage to these elements. This approach can be used during writing logic “1” ( FIG. 6B ) for non-selected MR elements J 12 , J 13 , J 21 , J 32 , J 33 , and others. 
     While the specification of this disclosure contains many specifics, these should not be construed as limitations on the scope of the disclosure or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination. 
     It is understood that the above embodiments are intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the embodiments should be, therefore, determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. 
     While the disclosure has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the disclosure can be practiced with modification within the spirit and scope of the appended claims. Specifically, one of ordinary skill in the art will understand that the drawings herein are meant to be illustrative, and the spirit and scope of the disclosure are not limited to the embodiments and aspects disclosed herein but may be modified.