Patent Publication Number: US-2022223543-A1

Title: Semiconductor package having stiffening structure

Description:
CROSS-REFERENCE TO THE RELATED APPLICATION 
     The present application is a continuation of and claims priority under 35 U.S.C. § 120 to U.S. patent application Ser. No. 16/848,106, filed on Apr. 14, 2020, which claims priority to Korean Patent Application No. 10-2019-0146833, filed on Nov. 15, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     Some example embodiments of the disclosure relate to semiconductor packages including logic chips, memory chips, and a stiffening structure, mounted on an interposer of a substrate. 
     2. Description of the Related Art 
     For next-generation high-performance communication appliances, a semiconductor package including a logic device and high-bandwidth memory (HBM) devices are being studied. Such semiconductor packages may include an interposer mounted on a substrate, and a logic chip and a plurality of memory stacks mounted on the interposer. In particular, semiconductor packages designed to be suitable for mobile communication are manufactured to be thin and, as such, may be very weak against external physical stress, such as warpage. Further, warpage of chips may easily occur in an extension direction of boundary areas (or boundary lines) of the chips. In this case, the resultant semiconductor package may be physically or electrically damaged. 
     SUMMARY 
     Some example embodiments of the disclosure provide packages having a stiffening structure capable of avoiding or limiting warpage. 
     Some example embodiments of the disclosure also provide stiffening structures capable of protecting constituent elements from physical impact. 
     Various problems to be solved by some example embodiments of the disclosure will be concretely described in the specification. 
     A semiconductor package according to an embodiment of the disclosure may include a substrate, an interposer on the substrate, and a first logic chip and a second logic chip on the interposer, the first logic chip and the second logic chip are side-by-side so as to be adjacent to each other, memory stacks including a plurality of stacked memory chips, each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip, the memory stacks on the interposer, and stiffening chips on the interposer, the stiffening chips between corresponding ones of the memory stacks, the stiffening chips aligned with and overlapping a boundary area between the first logic chip and the second logic chip. 
     A semiconductor package according to some example embodiments of the disclosure may include a substrate, an interposer on the substrate, first and second logic chips on the interposer such that the first and second logic chips are adjacent to each other, first memory stacks at opposite side surfaces of the first logic chip, and second memory stacks at opposite side surfaces of the second logic chip, and stiffening chips between the first memory stacks and the second memory stacks. The first and second logic chips may be electrically connected through a wiring inside the interposer. A minimum distance between the first logic chip and the second logic chip may be smaller than a minimum distance between the first memory stacks and the second memory stacks. The stiffening chips may be adjacent to a boundary area between the first logic chip and the second logic chip and aligned with an extension line of the boundary area. The stiffening chips may have a greater width than the boundary area. 
     A semiconductor package according to some example embodiments of the disclosure may include a substrate, an interposer on the substrate, a plurality of logic chips on the interposer, adjacent to one another within 100 mm, and the logic chips are electrically connected through the interposer, a plurality of memory stacks on the interposer, each of the memory stacks includes a plurality of stacked memory chips, and through vias extending vertically through the memory chips, and a plurality of stiffening chips on the interposer, longer sides of the stiffening chips are parallel to shorter sides of the memory stacks, shorter sides of the stiffening chips have a length corresponding to ½ or less of a length of longer sides of the memory stacks, and each of the stiffening chips has a greater width than a boundary area between corresponding ones of the logic chips such that the stiffening chip horizontally overlaps with portions of the corresponding logic chips, and a molding compound surrounding side surfaces of the interposer, side surfaces of the logic chips, side surfaces of the memory stacks and side surfaces of the stiffening chips. 
     Various effects according to example embodiments of the disclosure will be described in the specification. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a projected top view schematically showing a semiconductor package according to some example embodiments of the disclosure. 
         FIG. 1B  is a cross-sectional view or a projected side view of the semiconductor package shown in  FIG. 1A , taken along line I-I′ in  FIG. 1A . 
         FIGS. 1C and 1D  are cross-sectional views or projected side views of the semiconductor package shown in  FIG. 1A , taken along line II-IF in  FIG. 1A . 
         FIG. 1E  is an enlarged side view of the memory stacks. 
         FIG. 2A  is a projected top view schematically showing a semiconductor package according to some example embodiments of the disclosure. 
         FIG. 2B  is a cross-sectional view or a projected side view of the semiconductor package shown in  FIG. 2A , taken along line in  FIG. 2A . 
         FIGS. 2C and 2D  are cross-sectional views or projected side views of the semiconductor package shown in  FIG. 2A , taken along line IV-IV′ in  FIG. 2A . 
         FIGS. 2E to 2H  are projected top views schematically showing semiconductor packages according to various example embodiments of the disclosure, respectively. 
         FIGS. 3A and 3B  are cross-sectional views schematically showing semiconductor packages according to example embodiments of the disclosure, respectively. 
         FIG. 4A  is a projected top view or a projected layout view of a semiconductor package according to some example embodiments of the disclosure. 
         FIGS. 4B and 4C  are cross-sectional views or projected side views of the semiconductor package shown in  FIG. 4A , taken along line V-V′ in  FIG. 4A . 
         FIGS. 5A and 5B  are cross-sectional views schematically showing semiconductor packages and according to example embodiments of the disclosure, respectively. 
         FIGS. 6A to 6F  are projected top views of semiconductor packages according to example embodiments of the disclosure, respectively. 
     
    
    
     DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS 
       FIG. 1A  is a projected top view schematically showing a semiconductor package  100 A according to some example embodiments of the disclosure. 
     Referring to  FIG. 1A , the semiconductor package  100 A according to some example embodiments of the disclosure may include an interposer  20  disposed on a substrate  10 , upper and lower logic chips  31  and  32 , a plurality of memory stacks  41   a  to  41   d  and  42   a  to  42   d , and stiffening chips  51   a  and  51   b.    
     The interposer  20  may be mounted on the substrate  10 . Each of the substrate  10  and the interposer  20  may include one of a printed circuit board (PCB), a flexible PCB (FPCB), a silicon-based substrate, a ceramic substrate, a glass substrate, and/or an insulating circuit board. In some example embodiments, the substrate  10  may include a PCB or an FPCB. The interposer  20  may include a silicon-based substrate or a re-distribution structure. 
     The upper and lower logic chips  31  and  32  may be disposed side-by-side in a column direction such that upper and lower logic chips  31  and  32  are disposed adjacent to each other. Each of the upper and lower logic chips  31  and  32  may include one of a core processor, an application specific integrated circuit (ASIC), a mobile application processor (AP) and/or other processing chips. The terms “upper” and “lower” are used to distinguish the logic chips  31  and  32  from each other in the drawings. The upper and lower logic chips  31  and  32  may be horizontally disposed at the same level. 
     The memory stacks  41   a  to  41   d  and  42   a  to  42   d  may include first to fourth upper memory stacks  41   a  to  41   d  disposed side-by-side with respect to the upper logic chip  31  in a row direction, and first to fourth lower memory stacks  42   a  to  42   d  disposed side-by-side with respect to the lower logic chip  32  in the row direction. The row direction and the column direction are relative to each other, and may be interchanged with each other. 
     The first to fourth upper memory stacks  41   a  to  41   d  may be symmetrically disposed in parallel in the row direction at opposite sides of the upper logic chip  31 . In detail, the first and second upper memory stacks  41   a  and  41   b  may be disposed at a first side surface of the upper logic chip  31 , for example, at a left side of the upper logic chip  31 , whereas the third and fourth memory stacks  41   c  and  41   d  may be disposed at a second side surface of the upper logic chip  31 , for example, at a right side of the upper logic chip  31 . The first and second upper memory stacks  41   a  and  41   b  may be aligned with each other in the column direction while being disposed side-by-side in the column direction. Similarly, the third and fourth upper memory stacks  41   c  and  41   d  may be aligned with each other in the column direction while being disposed side-by-side in the column direction. Accordingly, the first and third upper memory stacks  41   a  and  41   c  may be disposed at a higher level than the second and fourth upper memory stacks  41   b  and  41   d.    
     The first to fourth lower memory stacks  42   a  to  42   d  may be symmetrically disposed in parallel in the row direction at opposite sides of the lower logic chip  32 . In detail, the first and second lower memory stacks  42   a  and  42   b  may be disposed at a first side surface of the lower logic chip  32 , for example, at a left side of the lower logic chip  32 , whereas the third and fourth memory stacks  42   c  and  42   d  may be disposed at a second side surface of the lower logic chip  32 , for example, at a right side of the lower logic chip  32 . The first and second lower memory stacks  42   a  and  42   b  may be aligned with each other in the column direction while being disposed side-by-side in the column direction. Similarly, the third and fourth lower memory stacks  42   c  and  42   d  may be aligned with each other in the column direction while being disposed side-by-side in the column direction. Accordingly, the first and third lower memory stacks  42   a  and  42   c  may be disposed at a higher level than the second and fourth lower memory stacks  42   b  and  42   d.    
     The stiffening chips  51   a  and  52   b  may be disposed to be aligned with a boundary area (boundary line) between the upper logic chip  31  and the lower logic chip  32  in the row direction while overlapping with the boundary area (boundary line) in the row direction. The stiffening chips  51   a  and  51   b  may have a greater width than the boundary area (boundary line) between the upper logic chip  31  and the lower logic chip  32 . Accordingly, the stiffening chips  51   a  and  51   b  may overlap with a portion of the upper logic chip  31  and a portion of the lower logic chip  32  in the row direction. 
     The stiffening chips  51   a  and  51   b  may include a first stiffening chip  51   a  disposed at a left side of the boundary area (boundary line) between the upper logic chip  31  and the lower logic chip  32 , and a second stiffening chip  51   b  disposed at a right side of the boundary area (boundary line) between the upper logic chip  31  and the lower logic chip  32 . The first stiffening chip  51   a  may be aligned with the first and second upper memory stacks  41   a  and  41   b  and the first and second lower memory stacks  42   a  and  42   b  in the column direction. The second stiffening chip  51   b  may be aligned with the third and fourth upper memory stacks  41   c  and  41   d  and the third and fourth lower memory stacks  42   c  and  42   d  in the column direction. For example, the first stiffening chip  51   a  may be disposed between the second upper memory stack  41   b  and the first lower memory stack  42   a , whereas the second stiffening chip  51   b  may be disposed between the fourth upper memory stack  41   d  and the third lower memory stack  42   c . The stiffening chips  51   a  and  51   b  may be smaller than the memory stacks  41   a  to  41   d  and  42   a  to  42   d . Shorter sides of the stiffening chips  51   a  and  51   b  have a smaller length than a length of longer sides of the memory stacks  41   a  to  41   d  and  42   a  to  42   d  such that the shorter-side length is ½ or less of the longer-side length. Longer sides of the stiffening chips  51   a  and  51   b  may have a smaller length than shorter sides of the memory stacks  41   a  to  41   d  and  42   a  to  42   d . The longer sides of the stiffening chips  51   a  and  51   b  may be parallel with the shorter sides of the memory stacks  41   a  to  41   d  and  42   a  to  42   d . Portions of the shorter sides of the stiffening chips  51   a  and  51   b  may be aligned with portions of the memory stacks  41   a  to  41   d  and  42   a  to  42   d.    
     The upper logic chip  31  and the lower logic chip  32  may be disposed to be spaced apart from each other or adjacent to each other by a distance of about 0.04 to 0.08 mm. In some example embodiments, the upper logic chip  31  and the lower logic chip  32  may be disposed to be spaced apart from each other or adjacent to each other by a distance of about 0.06 mm. That is, the logic chips  31  and  32  may be disposed to be very closely adjacent to each other. The logic chips  31  and  32  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d  may be disposed to be spaced apart from each other or adjacent to each other by a distance of about 0.5 to 0.9 mm. In some example embodiments, the logic chips  31  and  32  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d  may be disposed to be spaced apart from each other or adjacent to each other by a distance of about 0.7 mm. 
     When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value include a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes. While the term “same” or “identical” is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%). 
     For example, a first gap (e.g., a first minimum distance) between the logic chips  31  and  32  may be smaller than a second gap (a second minimum distance) between one of the logic chips  31  and  32  and adjacent one of the memory stacks  41   a  to  41   d  and  42   a  to  42   d . A third gap (a third minimum distance) between one the logic chips  31  and  32  and adjacent one of the stiffening chips  51   a  and  51   b  may be greater than the second gap (the second minimum distance). For example, the memory stacks  41   a  to  41   d  and  42   a  to  42   d  may be disposed nearer to the logic chips  31  and  32  than the stiffening chips  51   a  and  51   b , respectively. A fourth gap (a fourth minimum distance) between one of the stiffening chips  51   a  and  51   b  and adjacent one of the memory stacks  41   a  to  41   d  and  42   a  to  42   d  may be smaller than a fifth gap (a fifth minimum distance) between adjacent two of the memory stacks  41   a  to  41   d  and  42   a  to  42   d.    
       FIG. 1B  is a cross-sectional view or a projected side view of the semiconductor package  100 A shown in  FIG. 1A , taken along line I-I′ in  FIG. 1A .  FIGS. 1C and 1D  are cross-sectional views or projected side views of the semiconductor package  100 A shown in  FIG. 1A , taken along line II-IF in  FIG. 1A . 
     Referring to  FIGS. 1A to 1D , the semiconductor package  100 A,  100 Aa or  100 Ab according to some example embodiments of the disclosure may include the interposer  20  disposed on the substrate  10 , the logic chips  31  and  32 , the memory stacks  41   a  to  41   d  and  42   a  to  42   d , the stiffening chips  51   a  and  51   b , and a molding compound  80 . The semiconductor package  100 A,  100 Aa or  100 Ab may further include substrate bumps  61 , interposer bumps  62 , chip bumps  63 , and underfills  71  and  72 . The substrate bumps  61  may be disposed at a lower portion of the substrate  10 . The interposer bumps  62  may be disposed between the substrate  10  and the interposer  20 . The chip bumps  63  may be disposed between the interposer  20  and the logic chips  31  and  32  and between the interposer  20  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d . Each of the substrate bumps  61 , the interposer bumps  62  and the chip bumps  63  may include a solder ball or metal. The stiffening chips  51   a  and  51   b  may have a hexahedral or solid shape. In some example embodiments, the stiffening chips  51   a  and  52   a  may each include a solid dummy chip and a plurality of stacked dummy chips. That is, each of the stiffening chips  51   a  and  51   b  may include a chip stack. The stiffening chips  51   a  and  51   b  may include a portion of a silicon wafer (a silicon die), a portion of a printed circuit board, a metal or ceramic die, an epoxy compound, a solidified polymer resin, an inorganic material such as glass, and/or other hard materials. 
     The substrate  10  may have a thickness of about 1.5 to 2 mm. In some example embodiments, the substrate  10  may have a thickness of about 1.722 mm. The interposer  20  may be thinner than the substrate  10 , or, alternatively, the interposer  20  and the substrate  10  may have same thickness. For example, the interposer  20  may have a thickness of about 0.5 to 1.5 mm. In some example embodiments, the interposer  20  may have a thickness of about 0.11 mm. That is, the substrate  10  and the interposer  20  are very thin and, as such, may not provide much protection for electrical connections of the logic chips  31 , the memory stacks  41   a  to  41   d  and  42   a  to  42   d , the interposer  20  and the substrate  10  from physical stress such as warpage. The diameter or vertical height of the substrate bumps  61  may be about 0.2 to 0.8 mm. In some example embodiments, the diameter or vertical height of the substrate bumps  61  may be about 0.46 mm. The diameter or vertical height of the interposer bumps  62  may be about 0.05 to 0.1 mm smaller than that of the substrate bumps  61 . In some example embodiments, the diameter or vertical height of the interposer bumps  62  may be about 0.07 mm. The diameter or vertical height of the chip bumps  63  may be about 0.02 to 0.05 mm. In some example embodiments, the diameter or vertical height of the chip bumps  63  may be about 0.0356 mm smaller than that of the interposer bumps  62 . The total height of the semiconductor package  100 A may be about 2.7 to 3.3 mm. In some example embodiments, the total height of the semiconductor package  100 A may be 3.082 mm. The vertical height of the logic chips  31  and  32  may be about 0.65 to 0.72 mm. In some example embodiments, the vertical height of the logic chips  31  and  32  may be about 0.685 mm. Accordingly, the total vertical height of the interposer bumps  62 , the interposer  20 , the chip bumps  63  and the logic chips  31  and  32  may be about 0.8 to 1.0 mm. In some example embodiments, the total vertical height of the interposer bumps  62 , the interposer  20 , the chip bumps  63  and the logic chips  31  and  32  may be about 0.9 mm. 
     The semiconductor package  100 A,  100 Aa or  100 Ab may include substrate bump pads  11  disposed at the lower portion of the substrate  10 , and interposer bump pads  12  disposed at an upper portion of the substrate  10 . The substrate bump pads  11  and the interposer bump pads  12  may be electrically connected through substrate wirings  15  and substrate vias  16 . The substrate bump pads  11  may contact the substrate bumps  61 , respectively, and, as such, may be electrically connected to an external circuit board. The interposer bump pads  12  may contact respective interposer bumps  62  and, as such, may be electrically connected to the interposer  20 . 
     The interposer  20  may internally include an interposer wiring  25  and interposer vias. The interposer wiring  25  and the interposer vias  26  may include a conductor such as metal. The interposer wiring  25  and the interposer vias  26  may electrically connect the interposer bumps  62  and the chip bumps  63 . The chip bumps  63  may electrically connect the interposer  20  and the logic chips  31  and  32  while electrically connecting the interposer  20  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d . For example, the upper and lower logic chips  31  and  32  may be electrically connected through the chip bumps  63 , the interposer wiring  25  and the interposer vias  26 , for dual processing thereof. The first to fourth upper memory chips  41   a  to  41   d  may be electrically connected to the upper logic chip  31  through the chip bumps  63 , the interposer wiring  25  and the interposer vias  26 . The first to fourth lower memory chips  42   a  to  42   d  may be electrically connected to the lower logic chip  32  through the chip bumps  63 , the interposer wiring  25  and the interposer vias  26 . 
     The underfills  71  and  72  may include an interposer underfill  71  and a chip underfill  72 . The interposer underfill  71  may be formed between the substrate  10  and the interposer  20  to surround the interposer bumps  62 . The interposer underfill  71  may provide bonding force between the substrate  10  and the interposer  20 . The chip underfill  72  is formed between the interposer  20  and the logic chips  31  and  32  and between the interposer  20  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d  to surround the chip bumps  63 . The chip underfill  72  may provide bonding force between the interposer  20  and the logic chips  31  and  32  and between the interposer  20  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d . The underfills  71  and  72  may include a thermosetting resin. 
     The molding compound  80  may surround an upper surface of the substrate  10 , side and upper surfaces of the interposer  20 , side surfaces of the logic chips  31  and  32  and side surfaces of the memory stacks  41   a  to  41   d  and  42   a  to  42   d . The molding compound  80  may be filled between the logic chips  31  and  32  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d . Upper surfaces of the logic chips  31  and  32  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d  may be exposed without being covered by the molding compound  80 . In some example embodiments, the upper surfaces of the logic chips  31  and  32  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d  may be covered by the molding compound  80 . The molding compound  80  may include an epoxy molding compound (EMC). 
     Referring to  FIG. 1C , the interposer  20  and the stiffening chip  51   a  may be connected and fixed through an adhesive structure, for example, the chip bumps  63 . The chip bumps  63  between the interposer  20  and the stiffening chip  51   a  may also be surrounded by the chip underfill  72 . For example, when the stiffening chip  51   a  includes an under bumped metal (UBM), a metal pad or the like, the stiffening chip  51   a , the chip bumps  63  and the interposer  20  may have physical bonding force. As described above, the chip underfill  72  may reinforce bonding force between the interposer  20  and the stiffening chip  51   a.    
     Referring to  FIG. 1D , the interposer  20  and the stiffening chip  51   a  may be connected and fixed through an adhesive structure, for example, an adhesive layer  75 . The adhesive layer  75  may include a curable resin having an adhesive property such as a die attach film (DAF) or a non-conductive film (NCF). When the stiffening chip  51   a  does not include a UBM or a metal pad, the interposer  20  and the stiffening chip  51   a  may be physically bonded and fixed by the adhesive layer  75 . In some example embodiments, when the stiffening chip  51   a  includes a dummy chip, no electrical connection may be formed between the interposer  20  and the stiffening chip  51   a.    
       FIG. 1E  is an enlarged side view of the memory stacks  41   a  to  41   d  and  42   a  to  42   d . Referring to  FIG. 1E , each of memory stacks  41   x  and  42   x  may include a plurality of stacked memory chips  40   a  to  40   d , through vias  65 , and adhesive films  73 . The memory chips  40   a  to  40   d  in each of the memory stacks  41   a  to  41   d  and  42   a  to  42   d  may include non-volatile memory chips such as dynamic random access memory (DRAM), resistive random access memory (RRAM), magneto-resistive random access memory (MRAM), phase-changeable random access memory (PRAM) and/or flash memory or other various memory chips. In some example embodiments, the memory chip of the lowermost layer, that is, the memory chip  40   a , may include a base die. The base die may include a test logic circuit such as design for test (DFT), joint test action group (JTAG), or memory built-in self-test (MBIST), a signal interface circuit such as PHY, or the like. 
     When the lowermost memory chip  40   a  is a base die, the number of stacked memory chips may be 4 or more. In  FIG. 1E , only three memory chips  40   x  are shown, although the inventive concepts are not limited thereto. The through vias  65  may be connected to corresponding ones of the chip bumps  63  while extending vertically through the memory chips  40   a  to  40   d . The through vias  65  may be vertically aligned with corresponding ones of the chip bumps  63 . Each adhesive film  73  may be interposed between adjacent ones of the stacked memory chips  40   a  to  40   d . Each adhesive film  73  may include a die attach film (DAF). In some example embodiments, each adhesive film  73  may include an underfill material. 
       FIG. 2A  is a projected top view schematically showing a semiconductor package  100 B according to some example embodiments of the disclosure.  FIG. 2B  is a cross-sectional view or a projected side view of the semiconductor package  100 B shown in  FIG. 2A , taken along line in  FIG. 2A .  FIGS. 2C and 2D  are cross-sectional views or projected side views of the semiconductor package  100 B shown in  FIG. 2A , taken along line IV-IV′ in  FIG. 2A . 
     Referring to  FIGS. 2A to 2D , the semiconductor package  100 B according to some example embodiments of the disclosure may include an interposer  20  disposed on a substrate  10 , logic chips  31  and  32 , memory stacks  41   a  to  41   d  and  42   a  to  42   d , and a stiffening dam  55 . The substrate  10 , the interposer  20 , the logic chips  31  and  32 , and the memory stacks  41   a  to  41   d  and  42   a  to  42   d  have been described with reference to  FIGS. 1A to 1E  and, as such, no additional description thereof will be given. The stiffening dam  55  may be disposed on the interposer  20  in the form of a frame, although the stiffening dam  55  may be in another form, for example having a rounded cross-section. The stiffening dam  55  may include a portion of a silicon wafer, a portion of a printed circuit board, a metal or ceramic bar, an epoxy compound, a solidified polymer resin, an inorganic material such as glass, or other hard materials. 
     An upper end of the stiffening dam  55  may be lower than upper ends of the logic chips  31  and  32  and upper ends of the memory stacks  41   a  to  41   d  and  42   a  to  42   d  such that a molding compound  80  may uniformly fill an inside of the stiffening dam  55  and an outside of the stiffening dam  55 . The stiffening dam  55  may be bonded and fixed to an upper surface of the interposer  20  by an adhesive material. The stiffening dam  55  may have a vertical height of about 0.64 to 0.75 mm. In some example embodiments, the vertical height of the stiffening dam  55  including the adhesive material may be about 0.71 mm. The vertical height (thickness) of the adhesive material may be about 0.08 to 0.12 mm. In some example embodiments, the vertical height (thickness) of the adhesive material may be about 0.1 mm. Referring to  FIG. 2C , a stiffening chip  51   a  may be connected and fixed to the interposer  20  through chip bumps  63  and a chip underfill  72 . Referring to  FIG. 2D , the stiffening chip  51   a  may be bonded and fixed to the interposer  20  through an adhesive layer  75 . 
       FIGS. 2E to 2H  are projected top views schematically showing semiconductor packages  100 Bc to  100 Bf according to respective example embodiments of the disclosure. No description will be given of overlapping constituent elements. 
     Referring to  FIG. 2E , the semiconductor package  100 Bc according to some example embodiments of the disclosure may include stiffening dams  56  surrounding upper, lower and opposite lateral sides of logic chips  31  and  32 , and memory stacks  41   a  to  41   d  and  42   a  to  42   d . Each stiffening dam  56  may have a bar shape, although other shapes may be used, for example a crescent shape. For example, no stiffening dam  56  may be disposed at corners of the interposer  20 . 
     Referring to  FIG. 2F , the semiconductor package  100 Bd according to some example embodiments of the disclosure may include stiffening dams  56  surrounding opposite lateral sides of logic chips  31  and  32 , and memory stacks  41   a  to  41   d  and  42   a  to  42   d  while having a bar shape. For example, the stiffening dams  56  disposed at upper and lower sides in  FIG. 2E  may be omitted. 
     Referring to  FIG. 2G , the semiconductor package  100 Be according to some example embodiments of the disclosure may include a plurality of stiffening dams  57  each having the form of a segment. The segment type stiffening dams  57  may be disposed such that a part of the stiffening dams  57  are aligned and overlap with an extension line of a boundary area (boundary line) between the logic chips  31  and  32  in a row direction, and the remaining part of the stiffening dams  57  are aligned and overlap with extension lines of boundary areas (boundary lines) between the logic chips  31  and  32  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d  in a column direction, respectively. 
     Referring to  FIG. 2H , the semiconductor package  100 Bf according to some example embodiments of the disclosure may include segment type stiffening dams  57  aligned and overlapping with an extension line of a boundary area (boundary line) between the logic chips  31  and  32  in a row direction. For example, as compared to the case of  FIG. 2G , the stiffening dams  57 , which are aligned and overlap with the extension lines of the boundary areas (boundary lines) between the logic chips  31  and  32  and the memory stacks  41   a  to  41   d  and  42   a  to  42   d  in the column direction, respectively, may be omitted. 
       FIGS. 3A and 3B  are cross-sectional views schematically showing semiconductor packages  100 Ca and  100 Cb according to example embodiments of the disclosure, respectively. 
     Referring to  FIGS. 1A, 3A and 3B , each of the semiconductor packages  100 Ca and  100 Cb according to some example embodiments of the disclosure may include an interposer  20  disposed on a substrate  10 , logic chips  31  and  32 , memory stacks  41   a  to  41   d  and  42   a  to  42   d , stiffening chips  51   a  and  51   b , a molding compound  80 , and a stiffening cover  95 . The stiffening cover  95  may cover the interposer  20 , the logic chips  31  and  32 , the memory stacks  41   a  to  41   d  and  42   a  to  42   d , the stiffening chips  51   a  and  51   b , and the molding compound  80 . The stiffening cover  95  may completely cover upper surfaces of the logic chips  31  and  32 , the memory stacks  41   a  to  41   d  and  42   a  to  42   d , the stiffening chips  51   a  and  51   b , and the molding compound  80 , and side surfaces of the molding compound  80 . Referring to  FIG. 3A , the stiffening chip  51   a  may be connected and fixed to the interposer  20  through chip bumps  63  and a chip underfill  72 . Referring to  FIG. 3B , the stiffening chip  51   a  may be bonded and fixed to the interposer  20  through an adhesive layer  75 . 
       FIG. 4A  is a projected top view or a projected layout view of a semiconductor package  100 D according to some example embodiments of the disclosure.  FIGS. 4B and 4C  are cross-sectional views or projected side views of the semiconductor package  100 D shown in  FIG. 4A , taken along line V-V′ in  FIG. 4A . 
     Referring to  FIGS. 4A to 4C , the semiconductor package  100 D,  100 Da or  100 Db according to some example embodiments of the disclosure may include an interposer  20  disposed on a substrate  10 , logic chips  31  and  32 , memory stacks  41   a  to  41   d  and  42   a  to  42   d , and stiffening structures  51   a ,  55 , and  91 . The stiffening structures  51   a ,  55 , and  91  may include a stiffening chip  51   a , a stiffening dam  55 , and a stiffening plate  91 . The stiffening plate  91  may be disposed on the logic chips  31  and  32 . The stiffening plate  91  may have the form of a bar or segments extending to be vertically aligned or overlap with a boundary area (boundary line) between the logic chips  31  and  32 . The stiffening plate  91  may include a material which is hard while exhibiting excellent thermal conductivity, such as metal. Accordingly, the stiffening plate  91  may additionally perform a heat dissipation function. In some example embodiments, an upper surface of the stiffening plate  91  may have a heat sink structure (e.g., grooves and protrusions). 
     Referring to  FIG. 4B , the stiffening chip  51   a  may be connected and fixed to the interposer  20  through an adhesive structure such as chip bumps  63 . Referring to  FIG. 4C , the stiffening chip  51   a  may be bonded and fixed to the interposer  20  through an adhesive structure such as an adhesive layer  75 . Constituent elements not described may be understood by referring to other drawings. 
       FIGS. 5A and 5B  are cross-sectional views schematically showing semiconductor packages  100 Ea and  100 Eb according to example embodiments of the disclosure, respectively. Referring to  FIGS. 5A and 5B , each of the semiconductor packages  100 Ea and  100 Eb according to some example embodiments of the disclosure may include an interposer  20  disposed on a substrate  10 , logic chips  31  and  32 , memory stacks  41   a  to  41   d  and  42   a  to  42   d , a stiffening chip  51   a , a stiffening dam  55 , a molding compound  80 , and a stiffening cover  95 . The stiffening cover  95  may cover the interposer  20 , the logic chips  31  and  32 , the memory stacks  41   a  to  41   d  and  42   a  to  42   d , the stiffening chip  51   a , and the molding compound  80 . The stiffening cover  95  may completely cover upper and side surfaces of the logic chips  31  and  32 , the memory stacks  41   a  to  41   d  and  42   a  to  42   d , the stiffening dam  55 , and the molding compound  80 . Referring to  FIG. 5A , the stiffening chip  51   a  may be connected and fixed to the interposer  20  through chip bumps  63 . Referring to  FIG. 5B , the stiffening chip  51   a  may be bonded and fixed to the interposer  20  through an adhesive layer  75 . In some example embodiments, the stiffening dam  55  may be omitted. 
       FIGS. 6A to 6F  are projected top views of semiconductor packages  100 Fa to  100 Ff according to example embodiments of the disclosure, respectively. 
     Referring to  FIG. 6A , the semiconductor package  100 Fa according to one example embodiments of the disclosure may include an interposer  20  disposed on a substrate  10 , a plurality of logic chips  31  to  33 , memory stacks  41   a  to  41   d ,  42   a  to  42   d  and  43   a  to  43   d , and stiffening chips  51   a ,  51   b ,  52   a  and  52   b . The logic chips  31  to  33  may be disposed side-by-side to be aligned in a column direction. The memory stacks  41   a  to  41   d ,  42   a  to  42   d  and  43   a  to  43   d  may be disposed in a row direction such that each group of the memory stacks  41   a  to  41   d ,  42   a  to  42   d  and  43   a  to  43   d  is disposed adjacent to two side surfaces of a corresponding one of the logic chips  31  to  33 . For example, the memory stacks  41   a  to  41   d ,  42   a  to  42   d  and  43   a  to  43   d  may include first and second upper memory stacks  41   a  and  41   b  disposed adjacent to a first side surface of the upper logic chip  31 , third and fourth upper memory stacks  41   c  and  41   d  disposed adjacent to a second side surface of the upper logic chip  31 , first and second intermediate memory stacks  42   a  and  42   b  disposed adjacent to a first side surface of the intermediate logic chip  32 , third and fourth intermediate memory stacks  42   c  and  42   d  disposed adjacent to a second side surface of the intermediate logic chip  32 , first and second lower memory stacks  43   a  and  43   b  disposed adjacent to a first side surface of the lower logic chip  33 , and third and fourth lower memory stacks  43   c  and  43   d  disposed adjacent to a second side surface of the lower logic chip  33 . 
     A first upper stiffening chip  51   a  may be disposed between the second upper memory stack  41   b  and the first intermediate memory stack  42   a . A second upper stiffening chip  51   b  may be disposed between the fourth upper memory stack  41   d  and the third intermediate memory stack  42   c . A first upper stiffening chip  52   a  may be disposed between the second intermediate memory stack  42   b  and the first lower memory stack  43   a . A second lower stiffening chip  52   b  may be disposed between the fourth intermediate memory stack  42   d  and the third lower memory stack  43   c . The first and second upper memory stacks  41   a  and  41   b , the first upper stiffening chip  51   a , the first and second intermediate memory stacks  42   a  and  42   b , the first lower stiffening chip  52   a , and the first and second lower memory stacks  43   a  and  43   b  may be aligned in the column direction. The third and fourth upper memory stacks  41   c  and  41   d , the second upper stiffening chip  51   b , the third and fourth intermediate memory stacks  42   c  and  42   d , the second lower stiffening chip  52   b , and the third and fourth lower memory stacks  43   c  and  43   d  may be aligned in the column direction. Referring to  FIG. 6B , the semiconductor package  100 Fb according to some example embodiments of the disclosure may further include a stiffening dam  55 . 
     Referring to  FIG. 6C , the semiconductor package  100 Fc according to some example embodiments of the disclosure may include an interposer  20  disposed on a substrate  10 , a plurality of logic chips  31  to  34 , memory stacks  41   a  to  41   d ,  42   a  to  42   d ,  43   a  to  43   d  and  44   a  to  44   d , and stiffening chips  51   a ,  51   b ,  52   a ,  52   b ,  53   a  and  53   b . The logic chips  31  to  34  may be disposed side-by-side to be aligned in a column direction. Each group of the memory stacks  41   a  to  41   d ,  42   a  to  42   d ,  43   a  to  43   d  and  44   a  to  44   d  may be disposed at opposite side surfaces of a corresponding one of the logic chips  31  to  34  in a separated state. For example, the memory stacks  41   a  to  41   d ,  42   a  to  42   d ,  43   a  to  43   d  and  44   a  to  44   d  may include first and second upper memory stacks  41   a  and  41   b  disposed adjacent to a first side surface of the upper logic chip  31 , third and fourth upper memory stacks  41   c  and  41   d  disposed adjacent to a second side surface of the upper logic chip  31 , first and second intermediate upper memory stacks  42   a  and  42   b  disposed adjacent to a first side surface of the intermediate upper logic chip  32 , third and fourth intermediate upper memory stacks  42   c  and  42   d  disposed adjacent to a second side surface of the intermediate upper logic chip  32 , first and second intermediate lower memory stacks  43   a  and  43   b  disposed adjacent to a first side surface of the intermediate lower logic chip  33 , third and fourth intermediate lower memory stacks  43   c  and  43   d  disposed adjacent to a second side surface of the intermediate lower logic chip  33 , first and second lower memory stacks  44   a  and  44   b  disposed adjacent to a first side surface of the lower logic chip  34 , and third and fourth lower memory stacks  44   c  and  44   d  disposed adjacent to a second side surface of the lower logic chip  34 . 
     A first upper stiffening chip  51   a  may be disposed between the second upper memory stack  41   b  and the first intermediate upper memory stack  42   a . A second upper stiffening chip  51   b  may be disposed between the fourth upper memory stack  41   d  and the third intermediate upper memory stack  42   c . A first intermediate stiffening chip  52   a  may be disposed between the second intermediate upper memory stack  42   b  and the first intermediate lower memory stack  43   a . A second intermediate stiffening chip  52   b  may be disposed between the fourth intermediate upper memory stack  42   d  and the third intermediate lower memory stack  43   c . A first lower stiffening chip  53   a  may be disposed between the second intermediate lower memory stack  43   b  and the first lower memory stack  44   a . A second lower stiffening chip  53   b  may be disposed between the fourth intermediate lower memory stack  43   d  and the third lower memory stack  44   c . The first and second upper memory stacks  41   a  and  41   b , the first upper stiffening chip  51   a , the first and second intermediate upper memory stacks  42   a  and  42   b , the first intermediate stiffening chip  52   a , the first and second intermediate lower memory stacks  43   a  and  43   b , the first lower stiffening chip  53   a , and the first and second lower memory stacks  44   a  and  44   b  may be aligned in the column direction. The third and fourth upper memory stacks  41   c  and  41   d , the second upper stiffening chip  51   b , the third and fourth intermediate upper memory stacks  42   c  and  42   d , the second intermediate stiffening chip  52   b , the third and fourth intermediate lower memory stacks  43   c  and  43   d , the second lower stiffening chip  52   b , and the third and fourth lower memory stacks  44   a  and  44   b  may be aligned in the column direction. Referring to  FIG. 6D , the semiconductor package  100 Fd according to some example embodiments of the disclosure may further include a stiffening dam  55 . 
     Referring to  FIG. 6E , the semiconductor package  100 Fe according to some example embodiments of the disclosure may include an interposer  20  disposed on a substrate  10 , a plurality of logic chips  31  to  34 , memory stacks  41  to  44 , and stiffening chips  51 . For example, the logic chips  31  to  34  may be arranged in the form of a lattice or windows. The memory stacks  41  to  44  may be disposed around the logic chips  31  to  34 . For example, the memory stacks  41  to  44  may be disposed around the logic chips  31  to  34  such that four memory stacks are allocated to each logic chip. The stiffening chips  51  may be disposed to be aligned and overlap with extension lines of boundary areas (boundary lines) of the logic chips  31  to  34 . For example, each stiffening chip  51  may be disposed between corresponding ones of the memory stacks  41  to  44  while being aligned with another stiffening chip  51  in one of row and column directions. Referring to  FIG. 6F , the semiconductor package  100 Ff according to some example embodiments of the disclosure may further include a stiffening dam  55 . 
     Semiconductor packages according to example embodiments of the disclosure may include a stiffening structure and, as such, may have superior resistance against physical stress such as warpage. 
     While the embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the disclosure and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.