Patent Publication Number: US-10776042-B2

Title: Methods for garbage collection and apparatuses using the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This Application claims priority of Taiwan Patent Application No. 106109513, filed on Mar. 22, 2017, the entirety of which is incorporated by reference herein. 
     BACKGROUND 
     Technical Field 
     The present invention relates to flash memory, and in particular to methods for garbage collection and apparatuses using the same. 
     Description of the Related Art 
     Flash memory devices typically include NOR flash devices and NAND flash devices. NOR flash devices are random access—a host accessing a NOR flash device can provide the device any address on its address pins and immediately retrieve data stored in that address on the device&#39;s data pins. NAND flash devices, on the other hand, are not random access but serial access. It is not possible for NAND to access any random address in the way described above. Instead, the host has to write into the device a sequence of bytes which identifies both the type of command requested (e.g. read, write, erase, etc.) and the address to be used for that command. The address identifies a page (the smallest chunk of flash memory that can be written in a single operation) or a block (the smallest chunk of flash memory that can be erased in a single operation), and not a single byte or word. In reality, the NAND flash device always reads from the memory cells and writes to the memory cells complete pages. After a page of data is read from the array into a buffer inside the device, the host can access the data bytes or words one by one by serially clocking them out using a strobe signal. 
     If the data in some of the units of a page are no longer needed (such units are also called stale units), only the units with good data in that page are read and rewritten into another previously erased empty block. Then the free units and the stale units are available for new data. This is a process called garbage collection. The process of garbage collection involves reading data from the flash memory and rewriting data to the flash memory. It means that a flash controller first requires a read of the whole page, and then a write of the parts of the page which still include valid data. However, it may hinder data access operations requested by the host. It the worst case, it may cause the request time of a data access command to expire. Accordingly, what is needed are methods for garbage collection and apparatuses that use these methods to overcome the drawbacks described above. 
     BRIEF SUMMARY 
     An embodiment of the invention introduces a method for garbage collection, performed by a processing unit, including at least the following steps: executing instructions of a GC (garbage collection) process to direct a first access interface to read data from a storage unit, collect good data from the read data and direct the first access interface to program the good data into a spare block of the storage unit. 
     An embodiment of the invention introduces an apparatus for garbage collection including at least a first access interface, a second access interface and a processing unit. A first access interface is coupled to a storage unit. The second access interface is coupled to a host device. A processing unit, coupled to the first access interface and the second access interface, executes instructions of a GC process to direct the first access interface to read data from the storage unit, collect good data from the read data and direct the first access interface to program the good data into a spare block of the storage unit. 
     During the GC process, each time that a timer has counted to a time period, the processing unit directs a second access interface to clock a portion of data requested by a host device out to the host device and resets the timer. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is the system architecture of a flash memory according to an embodiment of the invention. 
         FIG. 2  is a schematic diagram illustrating interfaces to storage units of a flash storage according to an embodiment of the invention. 
         FIG. 3  is a schematic diagram depicting connections between one access sub-interface and multiple storage sub-units according to an embodiment of the invention. 
         FIG. 4  is a flowchart illustrating a method for GC according to an embodiment of the invention. 
         FIG. 5  is a schematic diagram of GC according to an embodiment of the invention. 
         FIG. 6  is a message exchange diagram for integrating a host read process with a GC process according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. It should be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements. 
       FIG. 1  is the system architecture of a flash memory  10  according to an embodiment of the invention. The system architecture  10  of the flash memory contains a processing unit  110  being configured to write data into a designated address of a storage unit  180 , and read data from a designated address thereof. Specifically, the processing unit  110  writes data into a designated address of the storage unit  180  through an access interface  170  and reads data from a designated address thereof through the same interface  170 . The flash memory  10  uses several electrical signals for coordinating commands and data transfer between the processing unit  110  and the storage unit  180 , including data lines, a clock signal and control lines. The data lines are employed to transfer commands, addresses and data to be written and read. The control lines are utilized to issue control signals, such as CE (Chip Enable), ALE (Address Latch Enable), CLE (Command Latch Enable), WE (Write Enable), etc. The access interface  170  may communicate with the storage unit  180  using a SDR (Single Data Rate) protocol or a DDR (Double Data Rate) protocol, such as ONFI (open NAND flash interface), DDR toggle, or others. The processing unit  110  may communicate with the host device  160  through an access interface  150  using a standard protocol, such as USB (Universal Serial Bus), ATA (Advanced Technology Attachment), SATA (Serial ATA), PCI-E (Peripheral Component Interconnect Express) or others. 
     The storage unit  180  may contain multiple storage sub-units and each storage sub-unit may be practiced in a single die and use an access sub-interface to communicate with the processing unit  110 .  FIG. 2  is a schematic diagram illustrating interfaces to storage units of a flash storage according to an embodiment of the invention. The flash memory  10  may contain j+1 access sub-interfaces  170 _ 0  to  170 _ j , where the access sub-interfaces may be referred to as channels, and each access sub-interface connects to i+1 storage sub-units. That is, i+1 storage sub-units may share the same access sub-interface. For example, assume that the flash memory contains 4 channels (j=3) and each channel connects to 4 storage sub-units (i=3): The flash memory  10  has 16 storage sub-units  180 _ 0 _ 0  to  180 _ j _i in total. The processing unit  110  may direct one of the access sub-interfaces  170 _ 0  to  170 _ j  to read data from the designated storage sub-unit. Each storage sub-unit has an independent CE control signal. That is, it is required to enable a corresponding CE control signal when attempting to perform data read from a designated storage sub-unit via an associated access sub-interface. It is apparent that any number of channels may be provided in the flash memory  10 , and each channel may be associated with any number of storage sub-units, and the invention should not be limited thereto.  FIG. 3  is a schematic diagram depicting connections between one access sub-interface and multiple storage sub-units according to an embodiment of the invention. The processing unit  110 , through the access sub-interface  170 _ 0 , may use independent CE control signals  320 _ 0 _ 0  to  320 _ 0 _ i  to select one of the connected storage sub-units  180 _ 0 _ 0  and  180 _ 0 _ i , and then read data from the designated location of the selected storage sub-unit via the shared data line  310 _ 0 . 
     After being accessed many times, one page may contain a portion of stale data. To address the aforementioned drawbacks, an embodiment of the invention introduce a method for GC (garbage collection) that performs data reads requested by the host device  160  interlaced with data-read-and-write operations of a GC process. For example, instructions of the GC process are executed to direct the access interface  170  to read data from the storage unit  180 , collect good data from the read data and direct the access interface  170  to program good data into a spare block of the storage unit  180 . In the GC process, each time a timer counts to a predetermined time period, the access interface  150  is directed to clock out at least a portion of data requested by the host device  160  and the timer is reset to avoid a read exception occurring in the host device  160  because no data has been received after a tolerable time.  FIG. 4  is a flowchart illustrating a method for GC according to an embodiment of the invention. The method is performed when relevant microcode, macrocode or software instructions are loaded and executed by the processing unit  110 . After each time a read command is received from the host device  160  through the access interface  150  (step S 410 ), it is determined whether a GC process needs to be performed (step S 430 ). In step S 410 , the read command contains information regarding a logical location. The logical location may be represented by one or more LBAs (Logical Block Addresses). In step S 430 , the processing unit  110  may determine whether the total number of spare blocks is fewer than a threshold. If so, the GC process is needed. Otherwise, no GC process is needed. 
     When no GC process is needed (the “No” path of step S 430 ), the access interface  170  is directed to read data requested by the read command from the storage unit  180 , the data is stored in the data buffer  120  (step S 471 ) and the access interface  150  is directed to clock the data of the data buffer  120  out to the host device  160  (step S 473 ). In order to optimize the data write efficiency, data with continuous LBAs is distributed stored across different physical regions of the storage unit  180 . Thus, the DRAM (Dynamic Random Access Memory)  130  stores a storage mapping table, also referred to as an H2F (Host-to-Flash) table, to indicate which location of the storage unit  180  data of each LBA is physically stored in. In step S 471 , the processing unit  110  reads physical region(s) corresponding to logical location(s) from the storage mapping table, and then, directs the access interface  170  to read data from the physical region(s) of the storage unit  180 . For example, the storage unit  180  may contain two channels and each channel may contain four storage sub-units. A controller (not shown) of the storage unit  180  may direct the two channels to read data of 128K bytes from the eight storage sub-units in one batch and the processing unit  110  stores the data in the data buffer  120 . In step S 473 , the processing unit  110  may set one or more registers to clock data out to the host device  160  page by page. For example, one page may contain data of 16K bytes. The processing unit  110  may use eight batches, and in each batch, to clock one page of data out to the host device  160 . In some embodiments, the data buffer  120  may be implemented in the DRAM  130 . 
     When a GC process is needed (the “Yes” path of step S 430 ), a timer is set to count to a shorter time period than the maximum tolerable time that the host device  160  waits for a data reply, such as 50 milliseconds (step S 451 ), the access interface  170  is directed to read data requested by the read command from the storage unit  180 , the read data is stored in the data buffer  120  (step S 453 ), instructions for the GC process are executed to read or write one page of data (step S 455 ) and it is determined whether the GC process is completed (step S 457 ). In some embodiments, information regarding the maximum tolerable time may be set and stored in a non-volatile storage device before the flash memory leaves the factory, and is read from the non-volatile storage device in step S 451 . In some embodiments, information regarding the maximum tolerable time may be carried in the read command issued by the host device  160 . 
       FIG. 5  is a schematic diagram of GC according to an embodiment of the invention. Assume one page stores data of four sections: Through being accessed several times, the 0 th  section  511  of the page P 1  of the block  510  contains good data and the remaining sections contain stale data. The 1 st  section  533  of the page P 2  of the block  530  contains good data and the remaining sections contain stale data. The 2 nd  and 3 rd  sections  555  and  557  of the page P 3  of the block  550  contain good data and the remaining sections contain stale data. In order to collect good data of the pages P 1  to P 3  in one page so as to store the good data in a new page P 4  of the block  570 , the GC process is performed. Specifically, space in the data buffer  120  is allocated to store one page of data. The processing unit  110  may read data of the page P 1  from the block  510  via the access sub-interface  170 , hold data of the 0 th  section  511  of the page P 1  and store it in the 0 th  section of the allocated space of the data buffer  120  (step S 455 ). Next, the processing unit  110  may read data of the page P 2  from the block  530  via the access sub-interface  170 , hold data of the 1 st  section  533  of the page P 2  and store it in the 1 st  section of the allocated space of the data buffer  120  (step S 455 ). Next, the processing unit  110  may read data of the page P 3  from the block  550  via the access sub-interface  170 , hold data of the 2 nd  and 3 rd  section  555  and  557  of the page P 3  and store it in the 2 nd  and 3 rd  section of the allocated space of the data buffer  120  (step S 455 ). Finally, the processing unit  110  may program data of the allocated space of the data buffer  120  into the page P 4  of the block  570  (step S 455 ). 
     In some embodiments, the timer issues an interrupt to the processing unit  110  when counting to the time period, enabling the processing unit to suspend the currently executed task, such as the instruction execution of the GC process, and execute an ISR (Interrupt Service Routine). The ISR, when being executed, sets one or more registers of the access interface  150  for clocking one page of data out to the host device  160  and resets the timer to recount the time. When the ISR is executed completely, the processing unit  110  resumes the suspended task, such as the instruction execution of the GC process. 
     In some embodiments, in step S 455 , the processing unit  110  may read the value of the timer after a read or write for one page of data, and determine whether the timer has counted to the time period. When the timer has counted to the time period, the processing unit  110  sets one or more registers of the access interface  150  for clocking one page of data out to the host device  160  and resets the timer to recount the time. 
     Scenarios are introduced to illustrate the aforementioned GC method.  FIG. 6  is a message exchange diagram for integrating a host read process with a GC process according to an embodiment of the invention. The processing unit  110  receives a read command CMD read  for requesting to read DATA r  of 128K bytes from the host device  160  via the access interface  150  (step S 410 ). Next, when a GC process needs to be performed (the “Yes” path of step S 430 ), a timer is set to count to a time period t c  (step S 451 ), a data read request REQ r  is sent to the storage unit  180  via the access interface  170 , receives the data DATA r  of 128K bytes from the storage unit  180  and the data DATA r  is stored in the data buffer  120  (step S 453 ). Next, instructions of the GC process are periodically executed, such as a data read request REQ gc_r  for reading one page of data or a data write request REQ gc_w  for programming one page of data (step S 455 ). Each time the timer has counted to the time period t c , the processing unit  110  sets one or more registers of the access interface  150  for clocking one page (16K Bytes) of data DATA r  of the data buffer  120  out to the host device  160 . 
     Although the embodiment has been described as having specific elements in  FIGS. 1 to 3 , it should be noted that additional elements may be included to achieve better performance without departing from the spirit of the invention. While the process flow described in  FIG. 4  includes a number of operations that appear to occur in a specific order, it should be apparent that these processes can include more or fewer operations, which can be executed serially or in parallel (e.g., using parallel processors or a multi-threading environment). 
     While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.