Patent Publication Number: US-11049850-B2

Title: Methods of bonding the strip-shaped under bump metallization structures

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a divisional of U.S. application Ser. No. 16/215,373, filed on Dec. 10, 2018, entitled “Semiconductor Devices Having a Plurality of First and Second Conductive Strips” which claims priority to U.S. Provisional Application No. 62/737,729, filed on Sep. 27, 2018, entitled “Semiconductor Devices and Methods of Forming the Same,” and is related to the following co-pending and commonly assigned U.S. patent application Ser. No. 16/215,325, filed on Dec. 10, 2018, and entitled “Semiconductor Device with Multiple Polarity Groups,” which applications are hereby incorporated by references in their entireties. 
    
    
     BACKGROUND 
     The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  illustrates a cross-sectional view of an Integrated Passive Device (IPD) bonded to an integrated fan-out (InFO) package, in accordance with some embodiments. 
         FIGS. 2A-B  illustrate cross-sectional views of intermediate steps in the bonding of an IPD to an InFO package, in accordance with some embodiments. 
         FIGS. 3A-C  illustrate plan views of patterns of Under-Bump Metallization (UBM) structures, in accordance with some embodiments. 
         FIG. 4  illustrates a plan view of an intermediate step in the bonding of an IPD to an InFO package, in accordance with some embodiments. 
         FIGS. 5A-B  illustrate plan views of patterns of UBM structures, in accordance with some embodiments. 
         FIGS. 6A-D  illustrate plan views of patterns of UBM structures, in accordance with some embodiments. 
         FIG. 7  illustrates a cross-sectional view of a semiconductor package, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embodiments of the present disclosure are discussed in the context of semiconductor packages, and specifically, methods and structures of semiconductor packages comprising an integrated passive device (IPD) bonded to an integrated fan-out (InFO) package. In some embodiments, the under bump metallization (UBM) structures of the IPD device and the InFO package include strip-shaped features. The strip-shaped features may have different lengths or a different arrangement in the UBM structures of the IPD device than in the UBM structures of the InFO package. In some cases, the use of different UBM structures in this manner may allow for improved bonding. 
       FIG. 1  illustrates a cross-sectional view of a portion of a semiconductor package  1200  according to an embodiment. The semiconductor package  1200  includes an InFO package  1100  and an IPD  180  attached to the InFO package  1100 . As illustrated in  FIG. 1 , the InFO package  1100  includes one or more UBM structures  149  that may be bonded to one or more corresponding UBM structure  189  of the IPD  180 . As shown in  FIG. 1 , the UBM structures  149  may be bonded to the UBM structure  189  through a solder region  173 . Only one UBM structure  149  of the InFO package  1100  and only one UBM structure  189  of the IPD  180  are shown in the cross-sectional view of  FIG. 1 , but the InFO package  1100  may include multiple UBM structures  149  or the IPD  180  may include multiple UBM structures  189  in some embodiments. In some embodiments, the number of UBM structures  149  is the same as the number of UBM structures  189 . Note that the various features shown in  FIG. 1  are for illustration purpose only and not limiting, and other shapes, configurations, or arrangements are also possible. For example, the UBM structure  189 , the UBM structure  149 , or the soldier region  173  may include separated regions. The UBM structure  189  may be connected to the InFO package  1100  differently than shown, and the UBM structure  149  may be connected to the IPD  180  differently than shown. Various embodiments for the UBM structure  189  and the UBM structure  149  are discussed hereinafter. These and other variations of the semiconductor package  1200  are fully intended to be included within the scope of the present disclosure. 
     As illustrated in  FIG. 1 , the InFO package  1100  includes a die  120  (also referred to as a semiconductor die, or an integrated circuit (IC) die) embedded in a molding material  130 , and a redistribution structure  140  formed on a front side of the die  120  having die connectors  128 . The redistribution structure  140  includes electrically conductive features, such as conductive lines (e.g.,  131 ,  133 ,  135 ) and vias (e.g.,  132 ,  134 ,  136 ,  138 ), that are formed in one or more dielectric layers (e.g.,  142 ,  144 ,  146 ,  148 ) of the redistribution structure  140 . The UBM structure  149  may be formed over a topmost dielectric layer (e.g.,  142 ) of the redistribution structure  140  and is electrically coupled to the redistribution structure  140 . The UBM structure  149  may also be electrically coupled to one or more die connectors  128  through the redistribution structure  140 . The UBM structure  149  may be configured to be bonded to the UBM structure  189  of the IPD  180 , as described below. 
     The die  120  may include a substrate, such as a semiconductor substrate including silicon, may be doped or undoped, or may be an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate may include other semiconductor materials, such as germanium, a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, or indium antimonide, a combination thereof, or the like. The substrate may include a binary, ternary, or quaternary compound semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, combinations thereof, or the like. Other types of substrates, such as multi-layered or substrates having a graded doping or graded composition, may also be used. Devices, such as transistors (e.g., FinFETs, MOSFETs, etc.), diodes, capacitors, resistors, oscillators, or other active or passive devices, may be formed in and/or on the semiconductor substrate and may be interconnected by interconnect structures. The interconnect structures may include, for example, metallization patterns in one or more dielectric layers on the substrate, forming an integrated circuit. 
     The die  120  may also include pads (not shown), such as aluminum pads, to which external connections are made. The pads may be on an “active side” (or “front side”) of the die  120 . A passivation film (not shown) may be formed at the front side of the die  120  and on portions of the pads. Openings may be formed extending through the passivation film to the pads, and die connectors  128 , such as conductive pillars (which may include a metal such as copper), extend into the openings of the passivation film. In this manner, the die connectors  128  are mechanically and electrically coupled to the pads. The die connectors  128  may be formed by, for example, a plating process or the like. The die connectors  128  are electrically coupled to the integrated circuits of the die  120 . 
     A dielectric material  129  may be formed on the active sides of the die  120 , such as on the passivation film or the die connectors  128 . The dielectric material  129  may laterally encapsulate the die connectors  128 , and the dielectric material  129  may be laterally coterminous with the die  120 . The dielectric material  129  may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), another type of material, or a combination thereof. The dielectric material  129  may be formed, for example, by spin coating, lamination, CVD, PVD, ALD, or the like. 
     Referring further to  FIG. 1 , the molding material  130  around the die  120  may include a material such as an epoxy, an organic polymer, a polymer (with or without a silica-based or glass filler added), or another type of material. The molding material  130  may be formed using any suitable formation method, such as wafer level molding, compressive molding, transfer molding, or the like. Although not illustrated, the molding material  130  may be formed after the die  120  is attached to a first side of a carrier, after which the molding material  130  is formed over the first side of the carrier and around the die  120 . In some embodiments, conductive pillars such as through-substrate vias (TSVs) are formed over the first side of the carrier before the molding material  130  is formed. 
     As illustrated in  FIG. 1 , the redistribution structure  140  is formed over the die  120  and the molding material  130 . In some embodiments, the one or more dielectric layers (e.g.,  142 ,  144 ,  146 ,  148 ) of the redistribution structure  140  are formed of a material such as the examples described above for the dielectric material  129 , or may be formed from another material. The one or more dielectric layers of the redistribution structure  140  may be formed by a suitable deposition process, such as spin coating, CVD, laminating, the like, or a combination thereof. 
     In some embodiments, the conductive features of the redistribution structure  140  include conductive lines (e.g.,  131 ,  133 ,  135 ) and conductive vias (e.g.,  132 ,  134 ,  136 ,  138 ) formed of a suitable conductive material such as copper, titanium, tungsten, aluminum, a combination, or the like. In some embodiments, the redistribution structure  140  may be formed by forming a dielectric layer, forming openings in the dielectric layer to expose underlying conductive features, forming a seed layer over the dielectric layer and in the openings, forming a patterned photoresist with a designed pattern over the seed layer, plating (e.g., electroplating or electroless plating) the conductive material in the designed pattern and over the seed layer, and removing the photoresist and portions of seed layer on which the conductive material is not formed. In some embodiments, the redistribution structure  140  may be formed using a damascene process or a dual-damascene process, though other methods of forming the redistribution structure  140  are also possible and are fully intended to be included within the scope of the present disclosure. 
     The dielectric layers and the conductive features in the redistribution structures  140  of  FIG. 1  are intended as non-limiting examples. For example, other numbers of the dielectric layers and other numbers of layers of the conductive features are also possible and are fully intended to be included within the scope of the present disclosure. The discussion herein may refer to the redistribution layer (RDL)  131  as the topmost RDL of the redistribution structure  140 , with the understanding that when other numbers of RDLs are used in the redistribution structure  140 , the topmost RDL refers to the RDL furthest from the die  120 . 
       FIG. 1  also illustrates the UBM structure  149  formed over the InFO package  1100  and electrically coupled to the redistribution structure  140 . In some embodiments, the UBM structure  149  includes one or more layers of one or more conductive materials, such as silver, gold, aluminum, palladium, nickel, nickel alloys, tungsten alloys, chromium, chromium alloys, the like, another metallic material, or combinations thereof. In some embodiments, the UBM structure  149  includes three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBM structure  149 . Any suitable materials or layers of material that may be used for the UBM structure  149  are fully intended to be included within the scope of the present disclosure. In some cases, the UBM structure  149  may include an adhesion layer, a barrier layer and a wetting layer, which may be arranged in that order. 
     In some embodiments, the UBM structure  149  may be created by forming the openings in the topmost dielectric layer (e.g.,  142 ) of the redistribution structure  140  to expose conductive features (e.g., copper lines or copper pads) of the redistribution structure  140 . After the openings are formed, the material of the UBM structure  149  may be formed in the openings, the material of the UBM structure  149  having electrical contact with the exposed conductive features. For example, the UBM structures  149  may be created by forming each layer of the UBM structure  149  over the topmost dielectric layer (e.g.,  142 ) and along the interior of the openings through the topmost dielectric layer to the exposed conductive features of the redistribution structure  140 . The forming of each layer may be performed using a plating process, such as electroplating or electroless plating, although other processes of formation, such as sputtering, evaporation, or PECVD process, may alternatively be used. 
     As shown in  FIG. 1 , the IPD  180  may include a substrate  181  and one or more passive devices  183  (e.g.,  183 A and  183 B). The passive devices  183  may include capacitors, resistors, inductors, or other passive devices, and may be formed in the substrate  181  or on the substrate  181 . Passive devices  183 A and  183 B shown in  FIG. 1  are illustrative examples, and the passive devices  183  may include more, fewer, or different passive devices in other embodiments. In some embodiments, the IPD  180  includes an interconnect structure  199 , which includes dielectric layers (e.g.,  191 , 193 ) and metallization layers (e.g.,  185 ,  187 ) formed in the dielectric layers. In addition, the interconnect structure  199  also includes vias (e.g.,  186 , 188 ) formed in the dielectric layers  191  and  193 . The UBM structure  189  may be formed over the topmost dielectric layer (e.g.,  193 ) of the IPD  180 . The UBM structure  189  is electrically coupled to the passive devices  183  through the interconnect structure  199 . As illustrated in  FIG. 1 , the UBM structure  189  may be bonded to the UBM structure  149  by, e.g., solder regions  173 . In some embodiments, the solder regions  173  have a thickness between about 0.5 μm and about 250 μm. 
     The substrate  181  of the IPD  180  may be a same or similar substrate as those described above for substrate of the die  120 , or may be a different type of substrate. Each of the passive devices  183  may have pads  182 , such as copper pads or aluminum pads, that are used for electrically coupling the passive devices  183  to electrical circuits external to the passive devices  183 . The formation of the interconnect structure  199  may use any suitable method, such as the method described above for forming the interconnect structure of the die  120 . 
     As illustrated in  FIG. 1 , the metallization layer  185  is formed over and electrically coupled with the passive devices  183 . The metallization layer  185  may be, for example, conductive lines connected to the pads  182 . The metallization layer  187  may be formed over the dielectric layer  191 , and the UBM structure  189  may be formed over the topmost dielectric layer (e.g.,  193 ) of the interconnect structure  199 . Vias  186  may be formed between and electrically couple the metallization layers  185  and  187 , and vias  188  may be formed between and electrically couple the metallization layer  187  and the UBM structure  189 . Note that not all of the features of the IPD  180  are visible in the cross-sectional view of  FIG. 1 . For example, an additional dielectric layer may be interposed between the metallization layer  185  and the substrate  181 . In addition, the UBM structure  189  and the various electrical connections illustrated in  FIG. 1  are illustrative examples and are not limiting. As discussed hereinafter, various designs of the UBM structure  189  and various electrical connections between the UBM structure  189  and the interconnect structure  199  are possible. These and other modifications are fully intended to be included within the scope of the present disclosure. 
     The interconnect structure  199  in  FIG. 1  has two dielectric layers  191 , 193  and two metallization layers  185 , 187  as illustrative examples. Other numbers of dielectric layers, other numbers of metallization layers, and other numbers of vias are also possible and are fully intended to be included within the scope of the present disclosure. The discussion herein may refer to the metallization layer  187  as the topmost metallization layer (e.g., furthest from the substrate  181 ) of the interconnect structure  199 , and may refer to the dielectric layer  193  as the topmost dielectric layer of the interconnect structure  199 , with the understanding that when other numbers of dielectric layers and other numbers of metallization layers are used in the interconnect structure  199 , the topmost metallization layer and the topmost dielectric layer refer to the metallization layer and the dielectric layer of the interconnect structure  199  that are furthest from the substrate  181 , respectively. 
       FIGS. 2A-B  illustrates cross-sectional views of intermediate steps in the bonding of an IPD  180  to an InFO package  1100  to form a semiconductor package  1200  according to an embodiment. The IPD  180  shown in  FIGS. 2A-B  includes a UBM structure  189 , which may be similar to the IPD  180  described previously. The InFO package  1100  shown in  FIGS. 2A-B  includes a UBM structure  149 , which may be similar to the InFO package  1100  described previously.  FIG. 2A  shows the IPD  180  being held by a bond head  200  as part of a pick-and-place process. In other embodiments, other techniques may be used to bond the IPD  180  to the InFO package  1100 . 
     As shown in  FIG. 2A , a solder  202  is formed on the UBM structure  189  of the IPD  180 . The material of the solder  202  may include a eutectic material, and the use of the word “solder” herein includes both lead-based and lead-free solders, such as Pb—Sn compositions for lead-based solder, lead-free solders including InSb, tin, silver, and copper (“SAC”) compositions, and other eutectic materials that have a common melting point and form conductive solder connections in electrical applications. For lead-free solder, SAC solders of varying compositions may be used, such as SAC  105  (Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC  305 , and SAC  405 , as examples. Lead-free conductive materials such as solder balls may be formed from SnCu compounds as well, without the use of silver (Ag). Lead-free solder may also include tin and silver, Sn—Ag, without the use of copper. These are examples, and other types or compositions of the solder  202  may be used. The solder  202  may be formed on the UBM structure  189  using techniques as known in the art. 
     In  FIG. 2A , a flux material  204  is formed on the UBM structure  149  of the InFO package  1110 . The flux material  204  may be applied to the surfaces of the UBM structure  149  by, e.g., a jetting process, a flux stencil process, or another process, and may be formed to a thickness of between about 1 μm and about 100 μm. The flux material  204  may be, e.g., a no-clean flux or another type of flux. In some cases, the flux material  204  includes a solder material or solder paste. 
     In some embodiments, flux material  204  includes a material that may improve a connection of a subsequently formed solder region  173  over the UBM structure  149  or the UBM structure  189 . For example, the flux material  204  may improve the connection by deoxidizing a native oxide layer on the UBM structure  149  or the UBM structure  189 . The flux material  204  may also have other properties or dimensions or include other types of materials. In some cases, a flux material similar to the flux material  204  may also be formed on the UBM structure  189  of the IPD  180 . 
       FIG. 2B  shows the IPD  180  bonded to the InFO package  1100 . In some embodiments, the UBM structure  149  may be aligned to the UBM structure  189  during the bonding procedure, within processing tolerances.  FIG. 2B  also shows the IPD  180  and the InFO package  1100  after a reflow process is performed on the solder  202 , forming solder region  173 . The solder region  173  bonds and electrically connects the UBM structure  189  of the IPD  180  to the UBM structure  149  of the InFO package  1100 . In some cases, other processing steps may be performed after placement of the IPD  180  on the InFO package  1100  but prior to performing the reflow process. For example, other processing steps may be performed on parts of the semiconductor package  1200  that may or may not be shown in  FIGS. 2A-B . 
     In some embodiments, the reflow process includes heating the solder  202  to a predetermined temperature, e.g., to a melting point of the material of the solder  202 . During the reflow process, the solder  202  undergoes a wetting process that causes adhesion of the solder  202  to the UBM structure  189  and the UBM structure  149 . In some cases, the reflow process may cause the solder  202  to spread on the UBM structure  189  or the UBM structure  149 . In some embodiments, a portion of the flux material  204  is left remaining around the edges of solder region  173  after the reflow process. In some embodiments, the remaining flux material (not shown) may then be removed using a cleaning process. 
     Turning to  FIGS. 3A-C , plan views of a UBM pattern  300  and a UBM pattern  310  are shown, according to an embodiment. The plan view of  FIG. 3A  is indicated by view A-A shown in  FIG. 2A , the plan view of  FIG. 3B  is indicated by view B-B shown in  FIG. 2A , and the plan view of  FIG. 3C  is indicated by view C-C shown in  FIG. 2A  (e.g., showing an overlapping view of the UBM pattern  300  and the UBM pattern  310 ). The UBM pattern  300  includes multiple UBM structures, and the UBM pattern  310  also includes multiple UBM structures, as described in greater detail below. The UBM pattern  300  is configured to be bonded to the UBM pattern  310 , e.g., by a solder region  173 . In  FIGS. 3A-C , some features are not shown for clarity. Some or all of the UBM pattern  300  or the UBM pattern  310  may be similar to the UBM structure  189  of the IPD  180  or may be similar to the UBM structure  149  of the InFO package  1100 , as described previously. While the UBM patterns  300 ,  310  and other patterns of UBM structures described below may be disposed on the IPD  180  or on the InFO package  1100  in other embodiments, for clarity the UBM pattern  300  is described as being disposed on the IPD  180  and the UBM pattern  310  is described as being disposed on the InFO package  1100 . The UBM patterns  300 ,  310  include multiple separated elongated or strip-shaped UBM structures, referred to herein as “strips,” although in some embodiments the UBM structures described herein may have features that are not “strip-shaped.” As described below, the UBM pattern  300  and the UBM pattern  310  each include sets of strips having different lengths or positions relative to strips of the same UBM pattern or relative to strips of another UBM pattern. The arrangements of strips shown in  FIGS. 3A-C  and other figures are illustrative examples, and the UBM patterns described herein may have more strips, fewer strips, or different strip characteristics, sizes, or arrangements than shown without deviating from the scope of this disclosure. Dimensions and relative dimensions described herein are assumed to be within processing tolerances. Additionally, while the UBM patterns, UBM structures, and techniques herein are described in the context of an IPD being bonded to an InFO package, the UBM patterns, UBM structures, and techniques may be used for bonding other structures, packages, devices, ICs, wafers, and the like, and all such contexts are within the scope of this disclosure. 
     The UBM pattern  300  shown in  FIG. 3A  includes strips  301 A-C,  302 A-C, and  303 . The UBM pattern  310  shown in  FIG. 3B  includes strips  311 A-C,  312 A-C, and  313 . In some cases, the strips  301 A-C, the strips  302 A-C, the strips  311 A-C, and the strips  312 A-C may each be considered different sets of strips. In some embodiments, a UBM pattern may include more sets of strips than shown. In the embodiment shown in  FIG. 3A , the strips  301 A-C and  302 A-C have the same length L 1  and the same width W 1 . The strip  303  has a length L 2  and shares the same width W 1 . While L 2  is shown in  FIG. 3A  to be different than length L 1 , L 2  may be the same as L 1  in other embodiments. In some embodiments, the length L 1  may be between about 10 μm and about 1000 μm and the width W 1  may be between about 10 μm and about 1000 μm. In some embodiments, the strips of the UBM pattern  300  may have a width/length ratio between about 1:1 and about 1:100, such as about 1:8.5. In some embodiments, the strips of the UBM pattern  300  may be separated by a width W 2  between about 10 μm and about 1000 μm, and may have a pitch P 1  of adjacent strips between about 20 μm and about 2000 μm. In some embodiments, the strips of the UBM pattern  300  have a “staggered” arrangement such that one set of strips (e.g.,  301 A-C) are offset in a lengthwise direction relative to another set of strips (e.g.,  302 A-C), with strips of one set being interleaved with strips of the other set. For example, as shown in  FIG. 3A , the strips  301 A-C have an offset of O 1  relative to the strips  302 A-C. In some embodiments, the offset O 1  between sets of strips may be between about 10 μm and about 1000 μm. In other words, the ends of one set of strips proximal an edge of the IPD  180  are closer to that edge than the ends of the other set of strips that are proximal that edge. As shown in  FIG. 3A , the UBM pattern  300  also includes an example additional strip  303  that has different dimensions than strips  301 A-C or  302 A-C, and that has a left end aligned to the left ends of strips  301 A-C and a right end aligned to the right ends of strips  302 A-C. Strip  303  is shown as an example for illustrative purposes, and in some embodiments, strip  303  may be omitted, or other additional strips having different lengths or offsets may be present. 
     Turning to  FIG. 3B , the strips  311 A-C and  312 A-C of the UBM pattern  310  have the same length L 3  and the same width W 3 . The strip  313  has a length L 4 , shown in  FIG. 3B  to be the same as length L 3 , but L 4  may be different than L 3  in other embodiments. In some embodiments, the length L 3  may be between about 10 μm and about 1000 μm and the width W 3  may be between about 10 μm and about 1000 μm. In some embodiments, the strips of the UBM pattern  310  may have a width/length ratio between about 1:1 and about 1:100, such as about 1:8.5. In some embodiments, the length L 3  is greater than the length L 2 . In some embodiments, the strips of the UBM pattern  310  may be separated by a width W 4  between about 10 μm and about 1000 μm, and may have a pitch P 2  of adjacent strips between about 20 μm and about 2000 μm. In some embodiments, the pitch P 2  is the same as the pitch P 1  of the UBM pattern  300 , or the width W 3  is the same as the width W 1  of the UBM pattern  300 . In some embodiments, the strips of the UBM pattern  310  have a staggered arrangement such that one set of strips (e.g.,  311 A-C) are offset in a lengthwise direction relative to another set of strips (e.g.,  312 A-C), with strips of one set being interleaved with strips of the other set. As shown in  FIG. 3B , the strips  311 A-C have an offset of O 2  relative to the strips  312 A-C. In some embodiments, the offset O 2  between sets of strips may be between about 10 μm and about 1000 μm. The UBM pattern  310  may also include one or more additional strips having different lengths or offsets, for example, the strip  313  may have a different length L 4  than strips  311 A-C or  312 A-C or may itself have an offset O 3  relative to the strips  311 A-C and  312 A-C. In some embodiments, the offset O 3  may be between about 10 μm and about 1000 μm. In some embodiments, strip  313  may be omitted, or other additional strips having different lengths or offsets may be present. In some embodiments, the strip  313  has the same length or the same width as the strip  303  of the UBM pattern  300 . That is, in those embodiments, L 4  is equal to L 2  and the strip  313  shares the same width W 1 . 
       FIG. 3C  shows the solder  202  formed on the UBM pattern  300  and the UBM pattern  300  having been aligned to the UBM pattern  310 , according to an embodiment.  FIG. 3C  shows the view indicated as C-C in  FIG. 2A , with striped regions indicating the UBM pattern  310  and dotted regions indicating the UBM pattern  310  with solder  202 . Each strip of the UBM pattern  300  may correspond to a strip of the UBM pattern  310 . For example, strip  301 A corresponds to strip  311 A, strip  302 A corresponds to strip  302 A, etc. During the bonding process, each strip of the UBM pattern  300  is bonded to its respective corresponding strip of the UBM pattern  310 . In the embodiment shown, each of the strips  301 A-C and  302 A-C has an end that is aligned to an end of its corresponding strip  311 A-C and  312 A-C. For example, the end of strip  301 A is aligned to the end of corresponding strip  311 A at the location  351  shown in  FIG. 3C , and the end of strip  302 C is aligned to the end of corresponding strip  312 C at the location  352  shown in  FIG. 3C . As shown in  FIG. 3C , the length L 1  of the strips  301 A-C and  302 A-C is less than the length L 3  of the strips  311 A-C, and thus portions of each of strips  311 A-C and  312 A-C are not covered by the solder  202  and are thus “exposed.” In some embodiments, the exposed portions of strips  311 A-C and  312 A-C may be located at opposite ends of each strip. In the example shown in  FIG. 3C , the ends of the strips  311 A-C close to one edge of the IPD  180  are exposed, and the ends of the strips  312 A-C close to the opposite edge of the IPD  180  are exposed. Which portions of which strips are exposed and the dimensions or locations of the exposed portions may be controlled by controlling the lengths, offsets, or positions of the strips of the UBM pattern  300  relative to the lengths, offsets, or positions of the strips of the UBM pattern  310 . In the embodiment shown in  FIGS. 3A-C , strip  303  is aligned to strip  313  and is the same size as strip  313 , and thus strip  313  does not have an exposed portion. 
       FIG. 4  shows the UBM structures  300  and  310  during a bonding process, according to an embodiment.  FIG. 4  shows the view indicated as D-D in  FIG. 2B , with dotted regions indicating solder regions  173 , and with the UBM pattern  300  being shown by the dotted lines. In  FIG. 4 , the UBM pattern  300  is placed on the UBM pattern  310  of the InFO package  1100 , similar to  FIG. 3C . A reflow process is then performed on the solder  202 , forming solder regions  173 . The reflow process may be similar to that described above with respect to  FIG. 2B . During the reflow process, the solder  202  melts and, due to wetting, spreads over the exposed portions of the strips  311 A-C in a first direction and over the exposed portions of the strips  312 A-C in an opposite second direction, indicated by the arrows in  FIG. 4 . Because of the adhesion of the wetted solder  202  to the UBM structures  300  and  310 , a wetting force is imparted on each strip  301 A-C and  302 A-C by the solder  202  in the same direction on each strip as the solder  202  spreads. Additionally, due to the staggered arrangement of the strips, the amount of solder  202  spreading in the first direction is about equal to the amount of solder  202  spreading in the opposite second direction. Thus, the wetting force imparted on the IPD  180  is approximately balanced, with the wetting force from one set of strips in the first direction about equal and opposite to the wetting force from the other set of strips in the opposite second direction. In some embodiments, the number of strips configured to have solder  202  spread in one direction is the same as the number of strips configured to have solder  202  spread in the opposite direction. 
     In some cases, the IPD  180  may have a tilted orientation (“tilt”) relative to the InFO package  1100  after the reflow process is performed, and the balanced wetting force due to the arrangement of strips can reduce the amount of tilt that the IPD  180  has after the reflow process. The tilt of the IPD  180  may be due to uneven solder spreading, uneven heating, misalignment, or other reasons. In some cases, a tilted IPD  180  after bonding to an InFO package  1100  may cause the distance (e.g., H 1  as shown in  FIG. 2B ) between one edge of the IPD  180  and the InFO package  1100  to be different than the distance (e.g., H 2  as shown in  FIG. 2B ) between the opposite edge of the IPD  180  and the InFO package  1100 . In some cases, a tilted IPD  180  can reduce the quality of the solder region  173  bonding the IPD  180  to the InFO package  1100 . For example, a tilt may cause the solder region  173  to have excessive formation of inter-metallic compound (IMC), cold joint problems, cracking of the solder region  173 , poor adhesion of the solder region  173  to the UBM structure  189  or UBM structure  149 , or other issues that may degrade device performance. In this manner, the use of the patterns of UBM structures as described herein may reduce the difference between the distances H 1  and H 2  due to tilting of the IPD  180 . In some embodiments, the use of the patterns of UBM structures as described herein can produce a difference between H 1  and H 2  of less than about 1000 μm. In this manner, the amount of IPD  180  tilt may be lessened and thus the bond between the IPD  180  and the InFO  110  may be improved. 
     The UBM structures  300  and  310  shown in  FIGS. 3A-4  are examples, and other patterns or configurations of strips are possible.  FIGS. 5A-B  and  6 A-D illustrate some illustrative examples of patterns of strips according to some embodiments, but other patterns are possible. For example, each pattern of strips may be used for the IPD  180  or the InFO package  1100 . In some embodiments, features of different strip patterns may be combined. For example, both segmented and unsegmented strips (described below) may be used in the same UBM pattern. Additionally, strips of different lengths, widths, offsets, or other characteristics may be combined in the same UBM pattern. A UBM pattern may also include two or more sets of strips having the same characteristics, such as a set of segmented strips interleaved with a set of unsegmented strips. In some embodiments, a UBM pattern of the IPD  180  may have strips with different characteristics than a UBM pattern of the InFO package  1100 . In some embodiments, different sets of strips A, B, and C may be interleaved in different arrangements, such as an “AABBAABB” arrangement, an “ABCABC” arrangement, or another arrangement. These and other configurations or combinations of configurations are considered within the scope of this disclosure. 
       FIG. 5A  shows a UBM pattern  502  having segmented strips and a UBM pattern  512  without segmented strips, according to an embodiment. The UBM structures of the UBM pattern  502  may be bonded to the UBM structures of the UBM pattern  512  or other UBM structures. The UBM pattern  502  includes UBM structures having segmented strips, in which each strip is divided into separated segments. For example, each strip shown in  FIG. 5A  includes a first segment  504 A and a second segment  504 B. The segments of a strip may be electrically connected or coupled, for example through an RDL or interconnect. In other cases, one or more segments of a strip may be electrically isolated, for example, a segment may be a “dummy” segment that remains electrically floating or otherwise electrically isolated after the bonding process. In some embodiments, the segments may be separated by a distance between about 10 μm and about 1000 μm. In some embodiments, a strip may have more than two segments, and the segments of a strip may different lengths or have separations of different distances. The segmented strips  504 A/B of the UBM pattern  502  shown in  FIG. 5A  are shown having offsets, but in other cases the segmented strips may not have offsets. In some cases, the positions or sizes of the separations within some strips may have offsets relative to other strips. In some cases, both a UBM pattern on the IPD  180  and a UBM pattern on the InFO package  1100  may have segmented strips. In some embodiments, the separations of the segmented strips  504 A/B of the UBM pattern  502  correspond to exposed portions of the strips  514  of the UBM pattern  512 , though the strips  514  may also have additional exposed portions. In some embodiments, the solder  202  is formed on the segmented strips  504 A/B and provides a balanced wetting force when expanding into the exposed portions of the strips  514  during a reflow process. 
       FIG. 5B  shows a UBM pattern  506  with offsets and a UBM pattern  516  without offsets according to an embodiment. The UBM structures of the UBM pattern  516  may be bonded to the UBM structures of the UBM pattern  506  or other UBM structures. As shown in  FIG. 5B , the UBM pattern  506  includes offset strips  508 , but the UBM pattern  516  includes strips  518  that do not have offsets. In some embodiments, the length of the strips  508  is less than the length of the strips  518  and thus the strips  518  have exposed portions during the reflow process. In some embodiments, the solder  202  is formed on the strips  508  and provides a balanced wetting force when expanding into the exposed portions of the strips  518  during a reflow process. 
       FIGS. 6A-D  show plan views of a first UBM pattern having strips  602  placed over a second UBM pattern having strips  604 , according to some embodiments. The plan views of  FIGS. 6A-D  are similar to that of  FIG. 3C , and the first UBM pattern and second UBM pattern may be similar to previously described UBM patterns or UBM structures. In Figured  6 A-D, striped regions indicate the strips  604  of the second UBM pattern, and cross-hatched regions indicate where the strips  602  of the first UBM pattern completely overlap the strips  604  of the second UBM pattern. In  FIG. 6A , the strips  602  have a length that is less than the length of the strips  604  by a length difference LD 1 . Alternating strips  602  are also offset from each other by an offset separation OS 1 . In the embodiment shown in  FIG. 6A , the length difference LD 1  is approximately equal to the offset separation OS 1 . However, a length difference between strips of two UBM patterns may be different than the offset separation between strips of one of the UBM patterns. For example, in  FIG. 6B , the offset separation OS 2  of the strips  602  is less than the length difference LD 2  between strips  602  and  604 . As shown, a greater length difference may have larger exposed regions and thus produce larger wetting forces during reflow. In  FIG. 6C , the offset separation OS 3  of the strips  602  is greater than the length difference LD 3  between strips  602  and  604 . In the example configuration shown in  FIG. 6C , ends of strips  604  and  602  that are coaligned extend in a lengthwise direction beyond ends of strips  604  that are exposed.  FIG. 6D  shows an example configuration in which an offset separation of strips  602  or strips  604  is greater than a length difference between strips  602  and strips  604 . Each strip  602  or  604  may have a proximal end that is closer in a lengthwise direction to the center of the UBM pattern than a distal end of the strip  602  or  604 . In the example of  FIG. 6D , the proximal end of each strip  604  is coaligned to the proximal end of each strip  602 , and the distal end of each strip  604  is exposed. As shown in  FIGS. 4-6D , different configurations of UBM patterns, UBM structures, or strips are possible. In this manner, one or both of the UBM structures of the UBM patterns that are bonded together may be configured for a particular application or process. 
       FIG. 7  illustrates a cross-sectional view of a semiconductor package  1300  including bottom package  1100 ′, a top package  160 , and an IPD  180 , in some embodiments. The semiconductor package  1200  illustrated in  FIG. 1  may correspond to a portion of the semiconductor package  1300  illustrated in  FIG. 7 , wherein like reference numerals refer to like elements. 
     In  FIG. 7 , an IPD  180 , which may be similar to an IPD  180  described previously, is attached to a bottom package  1100 ′, which may be an InFO package similar to InFO package  1100  described previously. The bottom package  1100 ′ has a die  120  between a front side redistribution structure  140  and a backside redistribution structure  110 . The front side redistribution structure  140  may be the same or similar to the redistribution structure  140  of  FIG. 1 , and the backside redistribution structure  110  include conductive features (e.g., conductive lines  114  and vias) formed in one or more dielectric layers (e.g.,  111 , 113 ). A molding material  130  is formed between the front side redistribution structure  140  and the backside redistribution structure  110 . Conductive pillars  119 , such as copper pillars or TSVs, are formed in the molding material  130 . The conductive pillars  119  electrically couple the front side redistribution structure  140  with the backside redistribution structure  110 . 
     As shown in  FIG. 7 , a top package  160 , which may be a memory package, is bonded to the bottom package  1100 ′ through conductive joints  168 . As illustrated in  FIG. 7 , the top package  160  has a substrate  161  and one or more semiconductor dies  162  (e.g., memory dies or other devices) attached to an upper surface of the substrate  161 . In some embodiments, the substrate  161  includes silicon, gallium arsenide, silicon on insulator (“SOI”) or other similar materials. In some embodiments, the substrate  161  is a multiple-layer circuit board. In some embodiments, the substrate  161  includes ceramic, glass, plastic, tape, film, or other supporting materials. The substrate  161  may include conductive features (e.g., conductive lines and vias) formed in/on the substrate  161 . As illustrated in  FIG. 7 , the substrate  161  has conductive pads  163  formed on the upper surface and a lower surface of the substrate  161 , which conductive pads  163  are electrically coupled to the conductive features of the substrate  161 . The one or more semiconductor dies  162  are electrically coupled to the conductive pads  163  by, e.g., bonding wires  167 . A molding material  165 , which may comprise an epoxy, an organic polymer, a polymer, or the like, is formed over the substrate  161  and around the semiconductor dies  162 . In some embodiments, the molding material  165  may be conterminous with the substrate  161 , as illustrated in  FIG. 7 . 
     In some embodiments, a reflow process is performed to electrically and mechanically couple the semiconductor package  160  to the backside redistribution structure  110 . Conductive joints  168  are formed between the conductive pads  163  and the conductive feature  114 . In some embodiments, the conductive joints  168  include solder regions, conductive pillars (e.g., copper pillars with solder regions on at least end surfaces of the copper pillars or TSVs), or any other suitable conductive joints. 
     Embodiments may achieve advantages. For example, the use of a pattern of UBM structures having a staggered arrangement (e.g., having sets of UBM structures with offsets) or having lengths dissimilar to corresponding bonded UBM structures may reduce the tilt that a device has after bonding to a substrate. In this manner, the bond between the device and the substrate may be improved, and defects in the bond may be reduced, which can improve yield. In some cases, the use of techniques described herein may allow for a bond having low resistance and low inductance. Additionally, different processing tools may not be required. 
     In an embodiment, a semiconductor package includes a semiconductor device including a first under bump metallization (UBM) structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips configured to be bonded to one of the multiple first conductive strips or one of the multiple second conductive strips. In an embodiment, the semiconductor device is an integrated passive device (IPD). In an embodiment, the substrate is an integrated fan-out (InFO) package. In an embodiment, the second UBM structure further including multiple fourth conductive strips, wherein the multiple fourth conductive strips are offset in the first direction from the multiple third conductive strips by a second offset distance. In an embodiment, the first offset distance is between about 10 μm and about 1000 μm. In an embodiment, the first UBM structure includes a semiconductor strip that has the same lateral dimensions as a semiconductor strip of the second UBM structure. In an embodiment, the multiple first semiconductor strips have a first length, wherein the multiple second semiconductor strips have the first length, and wherein the multiple third semiconductor strips have a second length that is different from the first length. In an embodiment, a difference between the first length and the second length is a distance that is less than the first offset distance. 
     In an embodiment, a semiconductor device includes an integrated passive device (IPD) including multiple first bonding structures and multiple second bonding structures disposed on a surface of the IPD, wherein the first bonding structures and the second bonding structures have a first length, and wherein the first bonding structures are offset from the second bonding structures by a first offset distance, and a substrate including multiple third bonding structures and multiple fourth bonding structures disposed on a surface of the substrate, wherein the third bonding structures and the fourth bonding structures have a second length that is greater than the first length, wherein the third bonding structures are offset from the fourth bonding structures by a second offset distance, and wherein each one of the multiple third bonding structures is bonded to a respective one of the multiple first bonding structures. In an embodiment, the second length is between about 10 μm and about 1000 μm greater than the first length. In an embodiment, the multiple first bonding structures is bonded to the multiple third bonding structures using a solder material. In an embodiment, each of the first bonding structures is adjacent at least one second bonding structure, and wherein each of the first bonding structures is offset in a lengthwise direction from an adjacent second bonding structure by the first offset distance. In an embodiment, the first offset distance is less than a difference between the first length and the second length. In an embodiment, the second offset distance is the same as the first offset distance. In an embodiment, the first bonding structures of the multiple first bonding structures have first ends facing a first lengthwise direction and the third bonding structures of the multiple third bonding structures have first ends facing the first lengthwise direction, and wherein the first ends of the multiple first bonding structures are aligned with the first ends of the multiple third bonding structures. In an embodiment, the first bonding structures of the multiple first bonding structures are in a parallel arrangement. 
     In an embodiment, a method includes forming a first pattern of first under bump metallization (UBM) structures over a semiconductor device, the first pattern of first UBM structures including parallel conductive strips, forming a second pattern of second UBM structures over a substrate, the second pattern of second UBM structures including parallel conductive strips, forming a solder material on the first UBM structures, placing the first UBM structures over the second UBM structures, wherein a first end of each of the first UBM structures is aligned with a first end of a respective second UBM structure, and wherein a second end of each of the first UBM structures is offset from a second end of a respective second UBM structure, and performing a reflow process to flow the solder material toward the second end of each of the respective second UBM structures. In an embodiment, the method also includes forming a flux material on the second UBM structures. In an embodiment, after performing the reflow process, a difference between a first distance of an end of the semiconductor device from the substrate and a second distance of an opposite end of the semiconductor device from the substrate is less than about 1000 μm. In an embodiment, the second end of each respective second UBM structure is closer to an edge of the semiconductor device than the first end of each respective second UBM structure. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.