Patent Publication Number: US-8984250-B2

Title: Memory controller, memory device and method for determining type of memory device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a memory device, and more particularly, to a flash memory controller, a flash memory device and a method for determining a type of a memory device. 
     2. Description of the Prior Art 
     The flash memory devices can be classified into two types, double data rate NAND-type (DDR NAND-type) flash memory device and single data rate NAND-type (SDR NAND-type) flash memory device. A flash memory controller, built in the flash memory device, will detect a type of the flash memory device automatically when the flash memory controller starts up, and then the flash memory controller can be correctly operated. 
     The conventional flash memory controller determines the type of the flash memory device by reading a content of a specific bit stored in a flash memory chip. However, because an error may have occurred when the flash memory controller reads the content of the specific bit, and an address of the specific bit may be varied when flash memory controllers are provided by different manufacturers, the flash memory controller may erroneously determine the type of the flash memory device when a single bit is used in this determination step, which influences the operations of the flash memory device. 
     SUMMARY OF THE INVENTION 
     It is therefore an objective of the present invention to provide a memory controller, a memory device and a method for determining a type of a memory device, which can correctly determine the type of the memory device, to solve the above-mentioned problems. 
     According to one embodiment of the present invention, a memory controller comprises a clock detector and a microprocessor. The clock detector is utilized for detecting if a specific pin of the memory controller has a clock signal thereon to generate a detecting result. The microprocessor is coupled to the clock generator, and is utilized for determining which type of memory devices that the memory controller is applied to according to the detecting result. 
     According to another embodiment of the present invention, a method for determining a type of a memory device comprises: detecting if a specific pin of a memory controller placed in the memory device has a clock signal thereon to generate a detecting result; and determining the type of the memory device according to the detecting result. 
     According to another embodiment of the present invention, a memory device comprises at least a memory chip and a memory controller coupled to the memory chip, where the memory controller comprises a clock detector and a microprocessor. The clock detector is utilized for detecting if a specific pin of the memory controller has a clock signal thereon to generate a detecting result. The microprocessor is coupled to the clock generator, and is utilized for determining which type of memory devices that the memory controller is applied to according to the detecting result. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a diagram illustrating a memory device according to one embodiment of the present invention. 
         FIG. 1B  shows a DDR NAND-type flash memory device using a clock signal DQS to sample data. 
         FIG. 2  is a flowchart of a method of determining a type of the memory device according to one embodiment of the present invention. 
         FIG. 3  is a diagram illustrating the clock detector according to one embodiment of the present invention. 
         FIG. 4  is a diagram illustrating the clock detector according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 1A .  FIG. 1A  is a diagram illustrating a memory device  100  according to one embodiment of the present invention. The memory device  100  of this embodiment can be a portable memory device, such as a memory card complying with SD/MMC, CF, MS, or XD standards. The memory device  100  comprises a flash memory  120 , and further comprises a controller arranged to access the flash memory  120 , where the aforementioned controller of this embodiment is a memory controller  110 . According to this embodiment, the memory controller  110  comprises a plurality of pins  111 _ 1 - 111 _n, a microprocessor  112 , a read only memory (ROM)  112 M, a clock detector  113 , a control logic  114 , a buffer memory  116 , and an interface logic  118 . The ROM  112 M is arranged to store a program code  112 C, and the microprocessor  112  is arranged to execute the program code  112 C to control access to the flash memory  120 . In addition, in this embodiment, the pin  111   —   n  is arranged to receiver/transmit a clock signal DQS (SQ Strobe), and one of the pin  111 _ 1 - 111 _(n−1) is arranged to receiver/transmit another clock signal WE (Write Enable). 
     Typically, the flash memory  120  comprises a plurality of blocks, and the controller (e.g. the memory controller  110  that executes the program code  112 C by utilizing the microprocessor  112 ) performs data copying, erasure and combining operations on the flash memory  120  by copying, erasing and combining in units of blocks. In addition, a block can be utilized for recording a specific amount of pages, where the controller (e.g. the memory controller  110  that executes the program code  112 C by utilizing the microprocessor  112 ) performs data writing operations on the flash memory  120  by writing/programming in units of pages. 
     In practice, the memory controller  110  that executes the program code  112 C by utilizing the microprocessor  112  is capable of performing various control operations by utilizing the internal components within the memory controller  110 . For example, the memory controller  110  utilizes the control logic  114  to control access to the flash memory  120  (e.g. operations of accessing at least one block or at least one page), utilizes the buffer memory  116  to perform buffering operations for the memory controller  110 , and utilizes the interface logic  118  to communicate with a host device. 
     In addition, when the memory device  100  is a DDR NAND-type flash memory device, the pin  111   —   n  is electrically connected to the flash memory  120 , and the memory controller  110  uses the clock signal DQS to transmit data to the flash memory  120  (especially from the host device to the flash memory  120 ) or to read data from the flash memory  120  (especially the data read by the host device). When the memory controller  110  intends to store data into the flash memory  120 , the memory controller  110  transmits the clock signal DQS to the flash memory  120 ; and when the memory controller  110  intends to read data from the flash memory  120 , the memory controller  110  receives the clock signal DQS from the flash memory  120 . Furthermore, the memory controller  110  uses the clock signal WE to transmit commands or addresses to the flash memory  120 . In addition, when the memory controller  110  intends to read data from the flash memory  120 , first, the microprocessor  112  transmits a read command to the flash memory  120 , and after the microprocessor  112  transmits the read command to the flash memory  120 , the flash memory  120  will transmit the clock signal DQS and the data synchronously to the memory controller  110 . On the other hand, when the memory device  100  is a SDR NAND-type flash memory device, the pin  111   —   n  is not electrically connected to the flash memory  120  (i.e., the pin  111   —   n  is floating). 
     In addition, please refer to  FIG. 1B .  FIG. 1B  shows a DDR NAND-type flash memory device using the clock signal DQS to sample the data. As shown in  FIG. 1B , the clock signal DQS is used to sample the data DATA, and both the rising edge and the falling edge of the clock signal DQS are used to sample the data DATA which is transmitted from the flash memory  120  to the memory controller  110  via at least the pins  111 _ 1 - 111 _ 3 . Please note that, when the memory controller  110  intends to transmits the commands or the addresses to the flash memory  120 , the memory controller  110  only uses the rising edge of the clock signal WE to sample the commands or the addresses. 
     Therefore, because the DDR NAND-type flash memory device has the clock signal DQS and the SDR NAND-type flash memory device does not have the clock signal DQS, an embodiment of the present invention provides a method to determine a type of the memory device  100  by detecting if a specific pin (i.e., the pin  111   —   n ) of the memory controller  110  has a clock signal (i.e., the clock signal DQS). Particularly, the type of the memory device  100  is determined by detecting if the specific pin receives the clock signal DQS from the flash memory  120 . 
     Please refer to  FIG. 1A  and  FIG. 2  together.  FIG. 2  is a flowchart of a method of determining a type of the memory device  100  according to one embodiment of the present invention. Referring to  FIG. 2 , the flow is described as follows. 
     In Step  200 , the flow is started, and the memory device  100  starts up. Then, in Step  202 , the microprocessor  112  transmits a read command to the flash memory  120  to ask for data stored in the flash memory  120 . Then, in Step  204 , after the microprocessor  112  transmits the read command to the flash memory  120 , the clock detector  113  detects if the pin  111   —   n  has the clock signal DQS thereon. If the pin  111   —   n  has the clock signal DQS thereon, the flow enters Step  206  to set the memory controller  110  to be operated at a DDR NAND-type mode; and if the pin  111   —   n  does not have the clock signal DQS thereon, the flow enters Step  208  to set the memory controller  110  to be operated at a SDR NAND-type mode. When the memory controller  110  is set to be operated at the DDR NAND-type mode, the memory controller  110  will notice the related circuit (i.e., the control logic  114 ) to use the clock signal DQS to sample the data DATA, that is using the rising edge and the falling edge of the clock signal DQS to sample the data DATA. 
     In addition, please refer to  FIG. 1B . because a voltage level of the clock signal DQS is varied between logic values “1” and “0”, therefore, in Step  204 , it can determine if the pin  111   —   n  has the clock signal DQS thereon by detecting if the voltage level at the pin  111   —   n  is toggled. That is, if the voltage level at the pin  111   —   n  is not toggled, it is represented that the pin  111   —   n  does not have the clock signal DQS thereon; on the contrary, if the voltage level at the pin  111   —   n  is toggled, it is represented that the pin  111   —   n  has the clock signal DQS thereon. Particularly, in order to prevent from an irregular interference on the pin  111   —   n , it can determine if the pin  111   —   n  has the clock signal DQS thereon after detecting toggles at the pin  111   —   n  a plurality of times. 
     Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating the clock detector  300  according to one embodiment of the present invention. As shown in  FIG. 3 , the clock generator  300  includes a control unit (in this embodiment, a flip-flops  310  serves as the control unit), a flip-flop group  320  including a plurality of flip-flops  320 _ 1 - 320 _M, a flip-flop  330  and a checking logic  340 , where clock receiving terminals of the flip-flops  310  and  330  are coupled to a system clock CLK, clock receiving terminals of the flip-flops  320 _ 1 - 320 _M are coupled to the pin  111   —   n , and an output terminal of the flip-flop  330  has a predetermined logic value “0”. The flip-flops shown in  FIG. 3  are D-type flip-flops, but it is not a limitation of the present invention. In the operations of the clock detector  300 , first, after the memory device  100  starts up, the microprocessor  112  sends an enable signal EN (i.e., logic “1”) to an input node D of the flip-flop  310 . Then, the flip-flop  310  sends the enable signal EN to the flip-flop  320 _ 1 . Then, if the memory device  100  is a DDR NAND-type flash memory device, the enable signal EN will be transmitted to the checking logic  340  because the flip-flops  320 _ 1 - 320 _M and  330  can be triggered by the clock signal DQS from the pin  111   —   n , and the checking logic  340  can receive the enable signal EN having logic “1”. On the contrary, if the memory device  100  is a SDR NAND-type flash memory device, the flip-flop group  320  cannot transmit the enable signal EN to the checking logic  340  because the flip-flop  320 _ 1  is not triggered by the clock signal DQS, and the checking logic  340  receives the predetermined logic “0”. In light of above, the checking logic  340  can determine the type of the memory device  100  by determining the voltage level at the output terminal of the flip-flop  330 . 
     It is noted that, because the voltage level at the pin  111   —   n  may be varied due to noises, a plurality of flip-flops  320 _ 1 - 320 _M are arranged in the flip-flop group  320  to prevent from erroneously determining a SDR NAND-type flash memory device to be a DDR NAND-type flash memory device. In other words, the enable signal EN is transmitted to the checking logic  340  only if the voltage level of the clock signal DQS varies between logics “0” and “1” many times. Therefore, the erroneous determination can be avoided. It is noted that, the clock detector  300  shown in  FIG. 3  is for illustrative purposes only, in other embodiments of the present invention, the flip-flop group  320  can include only one flip-flop. This alternative design should fall within the scope of the present invention. 
     Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating the clock detector  400  according to another embodiment of the present invention. As shown in  FIG. 4 , the clock detector  400  comprises a sampling unit  420 , a decision unit  420  and a counter  430 . In the operations of the clock detector  400 , the sampling unit  410  uses a system clock CLK to sample the clock signal DQS from the pin  111   —   n  to generate a sample signal S 1 , where a frequency of the system clock CLK is greater than a frequency of the clock signal DQS. Then, the decision unit  420  determines if a state of the sampled signal S 1  is varied (e.g., from logic “0” to logic “1”). If it is determined that the state of the sampled signal S 1  is varied, the decision unit  420  generates an enable signal S 2  to the counter  430  to increase a counting value counted by the counter  430 ; and if it is determined that the state of the sampled signal S 1  is not varied, the decision unit  420  does not generate the enable signal S 2  to the counter  430  (i.e., the counting value is not changed). Therefore, the type of the memory device  100  can be determined by using the counting value counted by the counter  430 . For example, if the counting value is greater than a threshold value, it is determined that the memory device  100  is a DDR NAND-type flash memory device; and if the counting value is not greater than a threshold value, it is determined that the memory device  100  is a SDR NAND-type flash memory device. 
     Briefly summarized, in the memory controller, memory device and method for determining the type of the memory device of the present invention, the type of the memory device is determined by detecting if a specific pin of the memory controller has a clock signal thereon. Therefore, compared with the prior art flash memory device, the present invention can determine the type of the memory device more accurately to prevent from influencing the operations of the memory device. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.