Patent Publication Number: US-2023162919-A1

Title: Multi-terminal multilayer capacitor

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of priority to Japanese Patent Application No. 2020-136462 filed on Aug. 12, 2020 and is a Continuation Application of PCT Application No. PCT/JP2021/027872 filed on Jul. 28, 2021. The entire contents of each application are hereby incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a multi-terminal multilayer capacitor. 
     2. Description of the Related Art 
     Various techniques have been proposed in order to reduce ESL (equivalent series inductance) of a capacitor. For example, Japanese Unexamined Patent Application Publication No. 2006-135333 discloses a multilayer capacitor array configured to include a capacitor body, first and second internal electrodes alternately arranged to face each other with a multilayer dielectric layer interposed therebetween, first and second external terminals formed on at least one of upper and lower surfaces of the body, and first and second conductive via holes formed in a stacking direction of the body and connected to the first and second external terminals, respectively. In particular, in the multilayer capacitor array, in order to reduce ESL, the first conductive via holes and the second conductive via holes are arranged (alternately arranged) such that magnetic fields induced by currents flowing through the internal electrodes connected to the first conductive via holes and the second conductive via holes cancel each other. 
     In addition, Japanese Unexamined Patent Application Publication No. 2002-160467 discloses a multilayer capacitor in which an internal electrode and an external terminal electrode are connected to each other through a via hole conductor, and an island-like cutout portion through which the via hole conductor passes is formed in the internal electrode electrically insulated from the via hole conductor in order to reduce the ESL. In this multilayer capacitor, a plurality of the island-like cutout portions is connected to each other, and cutout connection portions are formed so as to connect the respective outer side portions of the internal electrodes to the island-like cutout portions. That is, the cutout connection portion is formed so as to divide (split) the internal electrode into a plurality of regions insulated from each other. 
     SUMMARY OF THE INVENTION 
     However, in the multilayer capacitor array described in Japanese Unexamined Patent Application Publication No. 2006-135333, since the plurality of vias is conductively connected to the internal electrodes, there is a problem that a decrease in capacitance (effective value) due to the skin effect may occur in a high-frequency region, for example. 
     In the multilayer capacitor described in Japanese Unexamined Patent Application Publication No. 2002-160467, the internal electrode is divided (split) into a plurality of regions by the cutout connection portion, and thus, for example, characteristics such as capacitance and ESR (equivalent series resistance) may deteriorate, and the mechanical strength of the element may decrease. In particular, when vias are arranged at a narrow pitch, these problems may become significant. 
     Preferred embodiments of the present invention provide multi-terminal multilayer capacitors each capable of reducing or preventing a decrease in capacitance (effective value) while maintaining a low ESL in a high-frequency region, and capable of securing mechanical strength of an element. 
     A multi-terminal multilayer capacitor according to a preferred embodiment of the present invention includes first internal electrodes and second internal electrodes alternately stacked with a dielectric layer interposed between the first internal electrode and the second internal electrode, a plurality of first vias located inside the first internal electrode and the second internal electrode in a plan view, electrically connected to the first internal electrode and insulated from the second internal electrode, and penetrating the first internal electrode and the second internal electrode in a stacking direction, a plurality of second vias located inside the first internal electrode and the second internal electrode in a plan view, electrically connected to the second internal electrode and insulated from the first internal electrode, and penetrating the first internal electrode and the second internal electrode in a stacking direction, a first slit extending between a first insulating portion and the first via, the first insulating portion being located around the second via that penetrates the first internal electrode and insulating the second via and the first internal electrode from each other, a second slit extending between a second insulating portion and the second via, the second insulating portion being located around the first via that penetrates the second internal electrode and insulating the first via and the second internal electrode from each other, a plurality of first external terminals connected to the plurality of first vias, respectively, and a plurality of second external terminals connected to the plurality of second vias, respectively, wherein the first internal electrode is split into a plurality of first regions by the first slit and the first via electrically connects the plurality of first regions, and the second internal electrode is split into a plurality of second regions by the second slit and the second via electrically connects the plurality of second regions. 
     According to a multilayer capacitor according to a preferred embodiment of the present invention, when the first internal electrode is split into a plurality of regions by the first slit, the first via is positioned to electrically connect the plurality of regions, and when the second internal electrode is split into a plurality of regions by the second slit, the second via is positioned to electrically connect the plurality of regions. Therefore, the first and second internal electrodes are prevented from being divided (split) into a plurality of regions insulated from each other. When a voltage is applied to the first and second external terminals, a common voltage is applied to the first and second internal electrodes through the conductive connection with the first and second vias. Therefore, the capacitance can be increased as compared with the case where the internal electrode is electrically divided (split). Further, since the multi-terminal multilayer capacitor includes two conductors as a whole, the occurrence of an unnecessary resonance mode at a high frequency can be reduced or prevented. 
     In addition, the first slit extends between the first via and the first insulating portion that is located around the second via penetrating the first internal electrode and insulates the second via and the first internal electrode from each other, and the second slit extends between the second via and the second insulating portion that is located around the first via penetrating the second internal electrode and insulates the first via and the second internal electrode from each other. Therefore, when the first and second vias are viewed in a cross section including the center thereof and the first and second slits, the path of the conductor surface along the axial direction of the first and second vias is shortened. Thus, the impedance along the axial direction of the first and second vias is reduced. As a result, the voltage drop seen in the axial direction of the first and second vias is reduced, and the decrease in the capacitance in the high-frequency region is mitigated (that is, the frequency characteristic of the capacitance is flattened). In addition, an effect of reducing ESR and ESL can be obtained. 
     Further, the plurality of first vias is located inside the first internal electrode and the second internal electrode in a plan view, and the plurality of second vias is located inside the first internal electrode and the second internal electrode in a plan view. That is, the first and second vias are not located at the outer edge portions of the first and second internal electrodes. Therefore, the outer edges (outer peripheries) of the first and second internal electrodes are not divided by the first and second slits. Thus, the mechanical strength of the element can be ensured. 
     As a result, according to a preferred embodiment of the present invention, a decrease in capacitance (effective value) can be reduced or prevented while maintaining a low ESL in a high-frequency region, and the mechanical strength of the element can be secured. 
     The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a perspective view illustrating a configuration of a multi-terminal multilayer capacitor according to a first preferred embodiment of the present invention. 
         FIG.  2    is a cross-sectional view taken along line II-II of  FIG.  1   . 
         FIG.  3    is a cross-sectional view taken along line III-III of  FIG.  1   . 
         FIG.  4    is a diagram illustrating an equivalent circuit of the multi-terminal multilayer capacitor according to the first preferred embodiment of the present invention. 
         FIG.  5    is an exploded perspective view illustrating the internal structure of the multi-terminal multilayer capacitor according to the first preferred embodiment of the present invention. 
         FIGS.  6 A and  6 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of the multi-terminal multilayer capacitor according to the first preferred embodiment of the present invention. 
         FIGS.  7 A and  7 B  include graphs illustrating impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor according to the first preferred embodiment of the present invention and a comparative example. 
         FIGS.  8 A and  8 B  include graphs illustrating capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor according to the first preferred embodiment of the present invention and the comparative example. 
         FIGS.  9 A and  9 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a second preferred embodiment of the present invention. 
         FIGS.  10 A and  10 B  include graphs illustrating impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor according to the second preferred embodiment of the present invention and the comparative example. 
         FIGS.  11 A and  11 B  include graphs illustrating capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor according to the second preferred embodiment of the present invention and the comparative example. 
         FIGS.  12 A and  12 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a third preferred embodiment of the present invention. 
         FIGS.  13 A and  13 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a fourth preferred embodiment of the present invention. 
         FIGS.  14 A and  14 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a fifth preferred embodiment of the present invention. 
         FIGS.  15 A and  15 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a sixth preferred embodiment of the present invention. 
         FIG.  16    is an exploded perspective view illustrating the internal structure of the multi-terminal multilayer capacitor according to the sixth preferred embodiment of the present invention. 
         FIGS.  17 A and  17 B  include graphs illustrating impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor according to the sixth preferred embodiment of the present invention and the comparative example. 
         FIGS.  18 A and  18 B  include graphs illustrating capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor according to the sixth preferred embodiment of the present invention and the comparative example. 
         FIGS.  19 A and  19 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a seventh preferred embodiment of the present invention. 
         FIGS.  20 A and  20 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to an eighth preferred embodiment of the present invention. 
         FIGS.  21 A and  21 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a ninth preferred embodiment of the present invention. 
         FIGS.  22 A and  22 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a tenth preferred embodiment of the present invention. 
         FIGS.  23 A and  23 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to an eleventh preferred embodiment of the present invention. 
         FIGS.  24 A and  24 B  include plan views illustrating the configuration of a first internal electrode and a second internal electrode of a multi-terminal multilayer capacitor according to a twelfth preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Note that in the drawings, the same or corresponding portions are denoted by the same reference numerals. Additionally, in each of the drawings, the same elements are denoted by the same reference numerals, and overlapping descriptions thereof will be omitted. 
     First Preferred Embodiment 
     First, a configuration of a multi-terminal multilayer capacitor  1  according to a first preferred embodiment will be described with reference to  FIG.  1    to  FIG.  6 B .  FIG.  1    is a perspective view illustrating the configuration of the multi-terminal multilayer capacitor  1 .  FIG.  2    is a cross-sectional view taken along line II-II of  FIG.  1   .  FIG.  3    is a cross-sectional view taken along line III-III of  FIG.  1   .  FIG.  4    is a diagram illustrating an equivalent circuit of the multi-terminal multilayer capacitor  1 . Here, although minute L (inductance) and R (resistance) are parasitic on first and second external terminals  41  and  42 , in the equivalent circuit illustrated in  FIG.  4   , these parasitic L and R are collected into ESL and ESR and are not directly illustrated.  FIG.  5    is an exploded perspective view illustrating the internal structure of the multi-terminal multilayer capacitor  1 .  FIGS.  6 A and  6 B  include plan views illustrating the configuration of a first internal electrode  11  and a second internal electrode  12  of the multi-terminal multilayer capacitor  1 . 
     The multi-terminal multilayer capacitor  1  includes, for example, a multilayer body  10  has a rectangular or substantially rectangular parallelepiped shape, and nine external terminals  41  and  42 , more specifically, four first external terminals  41  and five second external terminals  42 , located on the top surface (upper surface) of the multilayer body  10 . 
     The multilayer body  10  is configured by the first internal electrodes  11  and second internal electrodes  12  that are alternately stacked facing each other with a plurality of dielectric layers (insulator layers)  13  with a rectangular or substantially rectangular shape interposed therebetween. The dielectric layer  13  is formed of, for example, a dielectric ceramic containing BaTiO 3 , CaTiO 3 , SrTiO 3 , CaZrO 3 , or the like as a main component. Note that in addition to these main components, accessory components such as a Mn compound, a Fe compound, a Cr compound, a Co compound, and a Ni compound may be added. 
     The first internal electrode  11  and the second internal electrode  12  preferably have, for example, a rectangular or substantially rectangular thin film shape. Each of the first internal electrode  11  and the second internal electrode  12  is formed of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like. 
     A plurality of (for example, four in the present preferred embodiment) first vias  21  is located in the multilayer body  10 , the first vias  21  being positioned inside the first internal electrode  11  and the second internal electrode  12  in a plan view (i.e., no contact with the outer edges), electrically connected (conducted) to the first internal electrode  11  and insulated from the second internal electrode  12 , and penetrating the multilayer body  10  in the stacking direction (thickness direction). 
     Similarly, a plurality of (for example, five in the present preferred embodiment) second vias  22  is located in the multilayer body  10 , the second vias  22  being positioned inside the first internal electrode  11  and the second internal electrode  12  in a plan view (i.e., no contact with the outer edges), electrically connected (conducted) to the second internal electrode  12  and insulated from the first internal electrode  11 , and penetrating the multilayer body  10  in the stacking direction (thickness direction). 
     The plurality of (for example, four) first external terminals  41  is connected to end portions of the plurality of (for example, four) first vias  21 , respectively. Similarly, the plurality of (for example, five) second external terminals  42  is connected to end portions of the plurality of (five) second vias  22 , respectively. The first external terminal  41  and the second external terminal  42  are formed of, for example, a conductive material including silver as a main component. 
     The present preferred embodiment has the configuration in which the first external terminals  41  (the first vias  21 ) and the second external terminals  42  (the second vias  22 ) are alternately arranged in rows and columns (matrix) in a plan view. 
     An annular first insulating portion (cavity)  111  is located in the first internal electrode  11 , the first insulating portion  111  being located around the second via  22  that penetrates the first internal electrode  11  and insulating the second via  22  and the first internal electrode  11  from each other. In addition, a linear first slit (gap)  31  is extending between the first insulating portion  111  and the first via  21 . 
     Similarly, an annular second insulating portion (cavity)  121  is located in the second internal electrode  12 , the second insulating portion  121  being located around the first via  21  that penetrates the second internal electrode  12  and insulating the first via  21  and the second internal electrode  12  from each other. In addition, a linear second slit (gap)  32  is extending between the second insulating portion  121  and the second via  22 . 
     In the present preferred embodiment, the first slits  31  and the second slits  32  are positioned to define a lattice shape (a grid shape) of three rows and three columns. Note that the shape of the first and second slits  31  and  32  is not limited to three rows and three columns, and can be arbitrarily set in accordance with requirements or the like (the same applies hereinafter). Additionally, in the present preferred embodiment, the first slit  31  and the second slit  32  overlap (coincide with) each other in a plan view. 
     Here, when the first internal electrode  11  is split into a plurality of regions (for example, five regions in the present preferred embodiment) by the first slit  31 , the first via  21  is disposed so as to electrically connect (conduct) the plurality of regions. Therefore, the first internal electrode  11  is a single internal electrode having a common potential. Similarly, when the second internal electrode  12  is split into a plurality of regions (for example, five regions in the present preferred embodiment) by the second slit  32 , the second via  22  is disposed so as to electrically connect (conduct) the plurality of regions. Therefore, the second internal electrode  12  is a single internal electrode having a common potential. 
     By being configured as described above, according to the present preferred embodiment, when the first internal electrode  11  is split into a plurality of (five) regions by the first slit  31 , the first via  21  is disposed so as to electrically connect (conduct) the plurality of regions, and when the second internal electrode  12  is split into a plurality of (five) regions by the second slit  32 , the second via  22  is disposed so as to electrically connect (conduct) the plurality of regions. Therefore, the first and second internal electrodes  11  and  12  are prevented from being divided (split) into a plurality of regions insulated from each other. When a voltage is applied to the first and second external terminals  41  and  42 , a common voltage is applied to each of the first and second internal electrodes  11  and  12  through the conductive connection with the first and second vias  21  and  22 . Therefore, the capacitance can be increased as compared with the case where the internal electrode is electrically divided (split). In addition, since the multi-terminal multilayer capacitor  1  includes two conductors as a whole, occurrence of an unnecessary resonance mode at a high frequency can be reduced or prevented. 
     In addition, according to the present preferred embodiment, the first slit  31  is extending between the first via  21  and the first insulating portion  111  that insulates the second via  22  and the first internal electrode  11  from each other, and the second slit  32  is extending between the second via  22  and the second insulating portion  121  that insulates the first via  21  and the second internal electrode  12  from each other. Therefore, when the first and second vias  21  and  22  are viewed in a cross section including the center thereof and the first and second slits  31  and  32 , the path of the conductor surface along the axial direction of the first and second vias  21  and  22  is shortened. Thus, the impedance along the axial direction of the first and second vias  21  and  22  is reduced. As a result, the voltage drop seen in the axial direction of the first and second vias  21  and  22  is reduced, and the decrease in the capacitance in the high-frequency region is mitigated (that is, the frequency characteristic of the capacitance is flattened). In addition, an effect of reducing ESR and ESL can be obtained. 
     Furthermore, according to the present preferred embodiment, the plurality of first vias  21  and the plurality of second vias  22  are positioned inside the first internal electrode  11  and the second internal electrode  12  (i.e., no contact with the outer edge) in a plan view. That is, the first and second vias  21  and  22  are not located at the outer edge portions of the first and second internal electrodes  11  and  12 . Therefore, the outer edges (outer peripheries) of the first and second internal electrodes  11  and  12  are not divided by the first and second slits  31  and  32 . Therefore, the mechanical strength of the element can be secured, and the flatness of the element can be secured. 
     As a result, according to the present preferred embodiment, a decrease in capacitance (effective value) can be reduced or prevented while maintaining a low ESL in a high-frequency region, and the mechanical strength of the element can be secured. 
     Here, impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor  1  according to the present preferred embodiment and a comparative example are illustrated in  FIGS.  7 A and  7 B . Note that in the comparative example, the first slit  31  and the second slit  32  were not provided (the same applies to the following description).  FIG.  7 A  illustrates impedance characteristics (simulation results) of the multi-terminal multilayer capacitor  1  and the comparative example, and  FIG.  7 B  illustrates ESR characteristics (simulation results) of the multi-terminal multilayer capacitor  1  and the comparative example. In the graph of  FIG.  7 A , the horizontal axis represents frequency (Hz) and the vertical axis represents impedance (Ω). Additionally, in the graph of  FIG.  7 B , the horizontal axis represents frequency (Hz) and the vertical axis represents ESR (Ω). 
     As illustrated in  FIG.  7 A , according to the multi-terminal multilayer capacitor  1 , it was confirmed that the impedance (particularly, the impedance in the vicinity of 100 MHz) was reduced as compared with the comparative example. In addition, as illustrated in  FIG.  7 B , according to the multi-terminal multilayer capacitor  1 , it was confirmed that the ESR was lowered as compared with the comparative example. 
     Next, capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor  1  and the comparative example are illustrated in  FIGS.  8 A and  8 B .  FIG.  8 A  illustrates capacitance characteristics (simulation results) of the multi-terminal multilayer capacitor  1  and the comparative example, and  FIG.  8 B  illustrates ESL characteristics (simulation results) of the multi-terminal multilayer capacitor  1  and the comparative example. In the graph of  FIG.  8 A , the horizontal axis represents frequency (Hz) and the vertical axis represents capacitance (F). Additionally, in the graph of  FIG.  8 B , the horizontal axis represents frequency (Hz) and the vertical axis represents ESL (H). As illustrated in  FIG.  8 A , in the comparative example, a decrease in capacitance was observed in a high-frequency region (particularly, a region of 10 MHz or higher), but according to the multi-terminal multilayer capacitor  1 , it was confirmed that the capacitance did not decrease even in a high-frequency region (particularly, a region of 10 MHz or higher). In addition, as illustrated in  FIG.  8 B , it was confirmed that the multi-terminal multilayer capacitor  1  can keep the ESL low. 
     Second Preferred Embodiment 
     In the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above, the first slits  31  and the second slits  32  are positioned to define a lattice shape, but as illustrated in  FIGS.  9 A and  9 B , first slits  31 B and second slits  32 B may be positioned to define three straight lines extending parallel or substantially parallel to the contours of a first internal electrode  11 B and a second internal electrode  12 B.  FIGS.  9 A and  9 B  include plan views illustrating the configuration of the first internal electrode  11 B and the second internal electrode  12 B of a multi-terminal multilayer capacitor  1 B according to a second preferred embodiment. 
     Note that also in the present preferred embodiment, the first slit  31 B and the second slit  32 B overlap (coincide with) each other in a plan view. In this case, the first and second internal electrodes  11 B and  12 B do not have electrically divided (split) regions. The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above, and thus detailed description thereof is omitted here. 
     Here, impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor  1 B according to the present preferred embodiment and the comparative example are illustrated in  FIGS.  10 A and  10 B .  FIG.  10 A  illustrates impedance characteristics (simulation results) of the multi-terminal multilayer capacitor  1 B and the comparative example, and  FIG.  10 B  illustrates ESR characteristics (simulation results) of the multi-terminal multilayer capacitor  1 B and the comparative example. In the graph of  FIG.  10 A , the horizontal axis represents frequency (Hz) and the vertical axis represents impedance (Ω). Additionally, in the graph of  FIG.  10 B , the horizontal axis represents frequency (Hz) and the vertical axis represents ESR (Ω). 
     As illustrated in  FIG.  10 A , according to the multi-terminal multilayer capacitor  1 B, it was confirmed that the impedance (particularly, the impedance in the vicinity of 100 MHz) was reduced as compared with the comparative example. In addition, as illustrated in  FIG.  10 B , according to the multi-terminal multilayer capacitor  1 B, it was confirmed that the ESR was lowered as compared with the comparative example. In other words, it was confirmed that even the multi-terminal multilayer capacitor  1 B according to the second preferred embodiment can also achieve effects equivalent to those of the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above. 
     Next, capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor  1 B and the comparative example are illustrated in  FIGS.  11 A and  11 B .  FIG.  11 A  illustrates capacitance characteristics (simulation results) of the multi-terminal multilayer capacitor  1 B and the comparative example, and  FIG.  11 B  illustrates ESL characteristics (simulation results) of the multi-terminal multilayer capacitor  1 B and the comparative example. In the graph of  FIG.  11 A , the horizontal axis represents frequency (Hz) and the vertical axis represents capacitance (F). Additionally, in the graph of  FIG.  11 B , the horizontal axis represents frequency (Hz) and the vertical axis represents ESL (H). 
     As illustrated in  FIG.  11 A , in the comparative example, a decrease in capacitance was observed in a high-frequency region (particularly, a region of 10 MHz or higher), but according to the multi-terminal multilayer capacitor  1 B, it was confirmed that the capacitance did not decrease even in a high-frequency region (particularly, a region of 10 MHz or higher). In addition, as illustrated in  FIG.  11 B , it was confirmed that the multi-terminal multilayer capacitor  1 B can keep the ESL low. In other words, it was confirmed that even the multi-terminal multilayer capacitor  1 B according to the second preferred embodiment can also achieve effects equivalent to those of the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above. 
     Third Preferred Embodiment 
     In the multi-terminal multilayer capacitor  1 B according to the second preferred embodiment described above, the first slit  31 B and the second slit  32 B are positioned to define three straight lines so as to overlap each other, but as illustrated in  FIGS.  12 A and  12 B , the direction in which a second slit  32 C extends may be rotated by 90° with respect to the direction in which the first slit  31 B extends.  FIGS.  12 A and  12 B  include plan views illustrating the configuration of the first internal electrode  11 B and a second internal electrode  12 C of a multi-terminal multilayer capacitor  1 C according to a third preferred embodiment. 
     That is, the first slit  31 B and the second slit  32 C are perpendicular or substantially perpendicular to each other in a plan view. Therefore, in the present preferred embodiment, the first slit  31 B and the second slit  32 C do not overlap each other (that is, do not coincide with each other) in a plan view. Also, in this case, the first and second internal electrodes  11 B and  12 C do not have electrically divided (split) regions. The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1 B according to the second preferred embodiment described above, and therefore detailed description thereof is omitted here. 
     According to the present preferred embodiment, since the first slit  31 B and the second slit  32 C do not overlap (i.e., do not coincide with each other) in a plan view, the magnetic field entering and leaving the first slit  31 B and the second slit  32 C is not linearly distributed (i.e., outside of the optimum condition), but effects substantially equivalent to those of the multi-terminal multilayer capacitor  1 B according to the second preferred embodiment described above can be achieved. 
     Fourth Preferred Embodiment 
     In the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above, the widths of the first slit  31  and the second slit  32  are constant, but as illustrated in  FIGS.  13 A and  13 B , a first slit  31 D may be formed in a tapered shape that narrows toward the first via  21 . Similarly, a second slit  32 D may have a tapered shape that narrows toward the second via  22 .  FIGS.  13 A and  13 B  include plan views illustrating the configuration of a first internal electrode  11 D and a second internal electrode  12 D of a multi-terminal multilayer capacitor  1 D according to a fourth preferred embodiment. The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above, and thus detailed description thereof is omitted here. 
     According to the present preferred embodiment, by forming the first and second slits  31 D and  32 D in a tapered shape, the conductive connection between the first and second internal electrodes  11 D and  12 D and the first and second vias  21  and  22  can be reliably achieved, and the influence of positional deviation or the like (variation) can be reduced. In addition, when the element is fired in the manufacturing process, the element is similarly contracted, however, by forming the first and second slits  31 D and  32 D in a tapered shape, the shapes of the first and second slits  31 D and  32 D can be favorably secured (maintained) even after the firing. 
     Fifth Preferred Embodiment 
     With respect to the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above, a land pattern may be provided at the connecting portions between the first and second vias  21  and  22  and the first and second slits  31  and  32 . 
     To be more specific, as illustrated in  FIGS.  14 A and  14 B , the connecting portion of a first internal electrode  11 E to the first via  21  preferably has an annular shape. That is, an annular first land pattern  112 E is located around the first via  21  penetrating the first internal electrode  11 E. Similarly, the connecting portion of a second internal electrode  12 E to the second via  22  preferably has an annular shape. That is, an annular second land pattern  122 E is located around the second via  22  penetrating the second internal electrode  12 E. Note that  FIGS.  14 A and  14 B  include plan views illustrating the configuration of the first internal electrode  11 E and the second internal electrode  12 E of a multi-terminal multilayer capacitor  1 E according to a fifth preferred embodiment. 
     A first slit  31 E connects between the first insulating portion  111  and the first land pattern  112 E (first via  21 ). Similarly, a second slit  32 E connects between the second insulating portion  121  and the second land pattern  122 E (second via  22 ). Note that the diameters of the first and second land patterns  112 E and  122 E are larger than the widths of the first and second slits  31 E and  32 E and are larger than the diameters of the first and second vias  21  and  22 . The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above, and thus detailed description thereof is omitted here. 
     According to the present preferred embodiment, by providing the first and second land patterns  112 E and  122 E, the conductive connection between the first and second internal electrodes  11 E and  12 E and the first and second vias  21  and  22  can be reliably achieved, and the influence of positional deviation or the like (variation) can be reduced. 
     Sixth Preferred Embodiment 
     The multi-terminal multilayer capacitor  1 B according to the second preferred embodiment described above has the configuration in which the first external terminals  41  (first vias  21 ) and the second external terminals  42  (second vias  22 ) are alternately arranged, but as illustrated in  FIGS.  15 A and  15 B  and  FIG.  16   , a configuration may be adopted in which the plurality of (three in the present preferred embodiment) first external terminals  41  (first vias  21 ) is linearly aligned (i.e., aligned with the same polarity) and the plurality of (for example, three in the present preferred embodiment) second external terminals  42  (second vias  22 ) is linearly aligned (i.e., aligned with the same polarity) in a plan view. Note that  FIGS.  15 A and  15 B  include plan views illustrating the configuration of a first internal electrode  11 F and a second internal electrode  12 F of a multi-terminal multilayer capacitor  1 F according to a sixth preferred embodiment. In addition,  FIG.  16    is an exploded perspective view illustrating the internal structure of the multi-terminal multilayer capacitor  1 F. 
     In this case, the plurality of (for example, three) linearly aligned first external terminals  41  (first vias  21 ) and the plurality of (for example, three) linearly aligned second external terminals  42  (second vias  22 ) are alternately arranged (for example, nine terminals). The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1  according to the first preferred embodiment described above, and thus detailed description thereof is omitted here. 
     By arranging the first external terminal  41  (first via  21 ) and the second external terminal  42  (second via  22 ) as described above (i.e., by aligning the first and second external terminals  41  and  42  with the same polarity) and designing the land pattern of the mounting substrate to match the layout of the first and second external terminals  41  and  42 , mounting on a linear line such as a microstrip line or a coplanar line becomes easy (possible). In particular, when the first and second external terminals  41  and  42  are positioned in three rows, they are arranged in a ground-signal-ground (GSG) arrangement, and through-type capacitors are connected together to define a single chip configuration. As such, handling at the time of mounting is facilitated. 
     Here, impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor  1 F according to the present preferred embodiment and the comparative example are illustrated in  FIGS.  17 A and  17 B .  FIG.  17 A  illustrates impedance characteristics (simulation results) of the multi-terminal multilayer capacitor  1 F and the comparative example, and  FIG.  17 B  illustrates ESR characteristics (simulation results) of the multi-terminal multilayer capacitor  1 F and the comparative example. In the graph of  FIG.  17 A , the horizontal axis represents frequency (Hz) and the vertical axis represents impedance (Ω). Additionally, in the graph of  FIG.  17 B , the horizontal axis represents frequency (Hz) and the vertical axis represents ESR (Ω). 
     As illustrated in  FIG.  17 A , according to the multi-terminal multilayer capacitor  1 F, it was confirmed that the impedance (particularly, the impedance at or below 100 MHz) was reduced as compared with the comparative example. In addition, as illustrated in  FIG.  17 B , according to the multi-terminal multilayer capacitor  1 F, it was confirmed that the ESR was lowered as compared with the comparative example. That is, it was confirmed that even the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment can also achieve effects equivalent to those of the multi-terminal multilayer capacitor  1 B according to the second preferred embodiment described above. 
     Next, capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor  1 F and the comparative example are illustrated in  FIGS.  18 A and  18 B .  FIG.  18 A  illustrates capacitance characteristics (simulation results) of the multi-terminal multilayer capacitor  1 F and the comparative example, and  FIG.  18 B  illustrates ESL characteristics (simulation results) of the multi-terminal multilayer capacitor  1 F and the comparative example. In the graph of  FIG.  18 A , the horizontal axis represents frequency (Hz) and the vertical axis represents capacitance (F). Additionally, in the graph of  FIG.  18 B , the horizontal axis represents frequency (Hz) and the vertical axis represents ESL (H). 
     As illustrated in  FIG.  18 A , in the comparative example, a decrease in capacitance was observed in a high-frequency region (particularly, a region of 10 MHz or higher), but according to the multi-terminal multilayer capacitor  1 F, it was confirmed that the capacitance did not decrease even in a high-frequency region (particularly, a region of about 10 MHz or higher). In addition, as illustrated in  FIG.  18 B , it was confirmed that, according to the multi-terminal multilayer capacitor  1 F, although the ESL was slightly higher than that of the comparative example, the ESL could be maintained relatively low. In other words, it was confirmed that the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment can also achieve effects substantially equivalent to those of the multi-terminal multilayer capacitor  1 B according to the second preferred embodiment described above. 
     Seventh Preferred Embodiment 
     With respect to the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment described above, as illustrated in  FIGS.  19 A and  19 B , a configuration may be adopted in which the plurality of (for example, two in the present preferred embodiment) first external terminals  41  (first vias  21 ) is linearly aligned (i.e., aligned with the same polarity), the plurality of (for example, three in the present preferred embodiment) second external terminals  42  (second vias  22 ) is linearly aligned (i.e., aligned with the same polarity), and the plurality of (for example, two) linearly aligned first external terminals  41  (first vias  21 ) and the plurality of (three) linearly aligned second external terminals  42  (second vias  22 ) are alternately arranged in a staggered manner (i.e., offset by a half pitch) in a plan view (seven terminals). 
     Furthermore, in the present preferred embodiment, a first slit  31 G extends in a direction oblique to the contour of a first internal electrode  11 G, and a second slit  32 G extends in a direction oblique to the contour of a second internal electrode  12 G. Note that  FIGS.  19 A and  19 B  include plan views illustrating the configuration of the first internal electrode  11 G and the second internal electrode  12 G of a multi-terminal multilayer capacitor  1 G according to a seventh preferred embodiment. Other configurations are the same or similar to those of the multi-terminal multilayer capacitor  1  (according to the first preferred embodiment) described above, and thus detailed description thereof will be omitted here. 
     By arranging the first external terminal  41  (first via  21 ) and the second external terminal  42  (second via  22 ) as described above (i.e., by aligning the first and second external terminals  41  and  42  with the same polarity) and designing the land pattern of the mounting substrate to match the layout of the first and second external terminals  41  and  42 , mounting on a linear line such as a microstrip line or a coplanar line becomes easy (possible). In particular, when the first and second external terminals  41  and  42  are positioned to define three rows, they are arranged in a ground-signal-ground (GSG) arrangement, and through-type capacitors are connected together to define a single chip configuration. As such, handling at the time of mounting is facilitated. 
     The multi-terminal multilayer capacitor  1 G according to the present preferred embodiment can also achieve effects equivalent to those of the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment described above. 
     Eighth Preferred Embodiment 
     With respect to the multi-terminal multilayer capacitor  1 G according to the seventh preferred embodiment described above, as illustrated in  FIGS.  20 A and  20 B , the shape of a slit  32 H of a second internal electrode  12 H may be left-right symmetrical (left-right reversed).  FIGS.  20 A and  20 B  include plan views illustrating the configuration of the first internal electrode  11 G and the second internal electrode  12 H of a multi-terminal multilayer capacitor  1 H according to an eighth preferred embodiment. 
     In the present preferred embodiment, the first slit  31 G and the second slit  32 H do not overlap with each other (that is, do not coincide with each other) in a plan view. The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1 G according to the seventh preferred embodiment described above, and therefore detailed description thereof is omitted here. 
     By arranging the first external terminal  41  (first via  21 ) and the second external terminal  42  (second via  22 ) as described above (i.e., by aligning the first and second external terminals  41  and  42  with the same polarity) and designing the land pattern of the mounting substrate to match the layout of the first and second external terminals  41  and  42 , mounting on a linear line such as a microstrip line or a coplanar line becomes easy (possible). In particular, when the first and second external terminals  41  and  42  are positioned to define three rows, they are arranged in a ground-signal-ground (GSG) arrangement, and through-type capacitors are connected together to define a single chip configuration. As such, handling at the time of mounting is facilitated. 
     According to the present preferred embodiment, surface paths of the first and second vias  21  and  22  and the first and second internal electrodes  11 G and  12 H become long, and current paths passing through the first and second slits  31 G and  32 H are not shortest. As a result, the impedance and ESR of the current path increase, and the Joule loss of the multi-terminal multilayer capacitor  1 H as a whole also increases. When a capacitor is used to decouple a power supply circuit, since there is a design method in which noise is suppressed by actively increasing the ESR, the present preferred embodiment is effective in such a case. 
     Ninth Preferred Embodiment 
     The multi-terminal multilayer capacitor  1 G according to the seventh preferred embodiment described above has the configuration in which the plurality of (for example, two) linearly aligned first external terminals  41  (first vias  21 ) and the plurality of (three) linearly aligned second external terminals  42  (second vias  22 ) are alternately arranged in a staggered manner (i.e., shifted by a half pitch), but as illustrated in  FIGS.  21 A and  21 B , a configuration may be adopted in which the plurality of (three) linearly aligned first external terminals  41  (first vias  21 ) and the plurality of (for example, two) linearly aligned second external terminals  42  (second vias  22 ) are alternately arranged in a staggered manner (i.e., shifted by a half pitch) in a plan view (eight terminals). 
     Furthermore, in the present preferred embodiment, a first slit  31 J extends in an oblique direction (y-shape) with respect to the contour of a first internal electrode  11 J, and a second slit  32 J extends in an oblique direction (y-shape) with respect to the contour of a second internal electrode  12 J. Note that  FIGS.  21 A and  21 B  include plan views illustrating the configuration of the first internal electrode  11 J and the second internal electrode  12 J of a multi-terminal multilayer capacitor  1 J according to a ninth preferred embodiment. The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1 G according to the seventh preferred embodiment described above, and therefore detailed description thereof is omitted here. 
     By arranging the first external terminal  41  (first via  21 ) and the second external terminal  42  (second via  22 ) as described above (i.e., by aligning the first and second external terminals  41  and  42  with the same polarity) and designing the land pattern of the mounting substrate to match the layout of the first and second external terminals  41  and  42 , mounting on a linear line such as a microstrip line or a coplanar line becomes easy (possible). In particular, when the first and second external terminals  41  and  42  are positioned in three rows, they are arranged in a ground-signal-ground (GSG) arrangement, and through-type capacitors are connected together to define a single chip configuration. As such, handling at the time of mounting is facilitated. 
     The multi-terminal multilayer capacitor  1 J according to the present preferred embodiment can also achieve effects equivalent to those of the multi-terminal multilayer capacitor  1 G according to the seventh preferred embodiment described above. 
     Tenth Preferred Embodiment 
     The multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment described above has the configuration in which the plurality of (for example, three) linearly aligned first external terminals  41  (first vias  21 ) and the plurality of (for example, three) linearly aligned second external terminals  42  (second vias  22 ) are alternately arranged (3×3 (3 rows×3 columns)=9 terminals), but as illustrated in  FIGS.  22 A and  22 B , a configuration may be adopted in which the plurality of (for example, five) linearly aligned first external terminals  41  (first vias  21 ) and the plurality of (for example, five) linearly aligned second external terminals  42  (second vias  22 ) are alternately arranged (5×5 (5 rows×5 columns)=25 terminals). Note that  FIGS.  22 A and  22 B  include plan views illustrating the configuration of a first internal electrode  11 K and a second internal electrode  12 K of a multi-terminal multilayer capacitor  1 K according to a tenth preferred embodiment. The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment described above, and therefore detailed description thereof is omitted here. 
     According to the multi-terminal multilayer capacitor  1 K of the present preferred embodiment, the areas of the first and second internal electrodes  11 K,  12 K are increased. This increases the capacitance of the multi-terminal multilayer capacitor  1 K as a whole. 
     Eleventh Preferred Embodiment 
     In the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment described above, the widths of the first slit  31 F and the second slit  32 F are constant, but as illustrated in  FIGS.  23 A and  23 B , a first slit  31 L may have a tapered shape that narrows toward the first via  21 . Similarly, the second slit  32 L may have a tapered shape that narrows toward the second via  22 .  FIGS.  23 A and  23 B  include plan views illustrating the configuration of a first internal electrode  11 L and a second internal electrode  12 L of a multi-terminal multilayer capacitor  1 L according to an eleventh preferred embodiment. The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment described above, and therefore detailed description thereof is omitted here. 
     According to the present preferred embodiment, by providing the first and second slits  31 L and  32 L in a tapered shape, the conductive connection between the first and second internal electrodes  11 L and  12 L and the first and second vias  21  and  22  can be reliably achieved, and the influence of positional deviation or the like (variation) can be reduced. In addition, when the element is fired in the manufacturing process, the element is similarly contracted, however, by providing the first and second slits  31 L and  32 L with a tapered shape, the shapes of the first and second slits  31 L and  32 L can be favorably secured (maintained) even after the firing. 
     Twelfth Preferred Embodiment 
     With respect to the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment described above, land patterns may be provided at the connecting portions between the first and second vias  21  and  22  and the first and second slits  31 F and  32 F. 
     To be more specific, as illustrated in  FIGS.  24 A and  24 B , the connecting portion of a first internal electrode  11 M to the first via  21  preferably has an annular shape. That is, an annular first land pattern  112 M is located around the first via  21  penetrating the first internal electrode  11 M. Similarly, the connecting portion of a second internal electrode  12 M to the second vias  22  preferably has an annular shape. That is, an annular second land pattern  122 M is located around the second via  22  penetrating the second internal electrode  12 M. Note that  FIGS.  24 A and  24 B  include plan views illustrating the configuration of the first internal electrode  11 M and the second internal electrode  12 M of a multi-terminal multilayer capacitor  1 M according to a twelfth preferred embodiment. 
     A first slit  31 M connects between the first insulating portion  111  and the first land pattern  112 M (first via  21 ). Similarly, a second slit  32 M connects between the second insulating portion  121  and the second land pattern  122 M (second via  22 ). The other configurations are the same as or similar to those of the multi-terminal multilayer capacitor  1 F according to the sixth preferred embodiment described above, and therefore detailed description thereof is omitted here. 
     According to the present preferred embodiment, by providing the first and second land patterns  112 M and  122 M, the conductive connection between the first and second internal electrodes  11 M and  12 M and the first and second vias  21  and  22  can be reliably achieved, and the influence of positional deviation or the like (variation) can be reduced. 
     Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described preferred embodiments and various modifications are possible. For example, the number and arrangement (array) of the first and second vias  21  and  22  and the first and second external terminals  41  and  42 , and the shape and arrangement of the first and second slits  31  and  32  described above are merely examples, and can be arbitrarily set in accordance with requirements or the like. 
     While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.