Patent Publication Number: US-2023146035-A1

Title: Package substrate and semiconductor package including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims the benefit below 35 USC 119(a) of Korean Patent Application No. 10-2021-0131674 filed on Oct. 5, 2021 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. 
     BACKGROUND 
     The present inventive concept relates to a package substrate, a semiconductor package including the same, and a method of forming the same. 
     According to weight reduction and the implementation of high performance in electronic devices, miniaturization and high performance are required in the semiconductor package field as well. In order to implement miniaturization, weight reductions, high performance, high capacity, and high reliability of the semiconductor package, research into and development of mounting a plurality of semiconductor chips in a single semiconductor package are being continuously conducted. 
     SUMMARY 
     Example embodiments provide a package substrate on which a plurality of semiconductor chips may be mounted. 
     Example embodiments provide a semiconductor package including a plurality of semiconductor chips. 
     According to example embodiments, a semiconductor package includes a package substrate including a base having a front side and an opposing back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the package substrate, spaced apart from the first support pattern in a horizontal direction parallel to the front side of the base, and on the protective insulating layer; and a first upper semiconductor chip vertically overlapping the lower semiconductor chip and the first support pattern, on the package substrate. 
     According to example embodiments, a semiconductor package includes a package substrate including a base having a front side and an opposing back side, front pads on the front side of the base, a support pattern having a thickness greater than a thickness of each of the front pads, on the front side of the base, and a protective insulating layer having openings exposing the front pads, respectively, on the front side of the base, and in contact with at least a portion of the support pattern; a lower semiconductor chip on the protective insulating layer and spaced apart from the support pattern in a horizontal direction; and a first upper semiconductor chip vertically overlapping the lower semiconductor chip and the support pattern, on the protective insulating layer and the lower semiconductor chip. The support pattern includes a metal post, and a lower surface of the support pattern is on a level lower than upper surfaces of the front pads. 
     According to example embodiments, a package substrate includes a base having a front side and an opposing back side; rear pads below the back side of the base; front pads on the front side of the base; support patterns having a thickness greater than a thickness of each of the front pads, on the front side of the base; and a protective insulating layer having openings exposing the front pads respectively, on the front side of the base, and on an upper surface and a side surface of each of the support patterns. The base includes a plurality of base insulating layers, and an interconnection structure penetrating through the plurality of base insulating layers and electrically connecting the front pads and the rear pads. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The above and other aspects, features, and advantages of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: 
         FIGS.  1  to  2 B  are views illustrating a package substrate and a semiconductor package including the same according to example embodiments; 
         FIG.  3    is a cross-sectional view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  4    is a cross-sectional view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  5    is a cross-sectional view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIGS.  6  and  7    are views illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  8 A  is a top view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  8 B  is a top view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  8 C  is a top view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  8 D  is a top view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  8 E  is a top view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  8 F  is a top view illustrating a modified example of a semiconductor package according to an example embodiment; 
         FIG.  8 G  is a top view illustrating a modified example of a semiconductor package according to an example embodiment; and 
         FIG.  9    is a process flow diagram illustrating an illustrative example of a method of forming a semiconductor package according to an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, terms used to distinguish the components of the semiconductor package from each other may be replaced with other terms with reference to the drawings. For example, terms such as “upper” and “lower” or terms such as “front”, “back” and “rear” may be replaced with other terms, for example, terms such as “first” and “second” and used to describe elements of the specification. Terms such as “first” and “second” may be used to describe various elements, but the elements are not limited by the terms, and “first element” may be referred to as “second element”. 
       FIG.  1    is a top view illustrating a package substrate and a semiconductor package including the same according to example embodiments,  FIG.  2 A  is a cross-sectional view illustrating an area taken along line Ia-Ia′ of  FIG.  1   , and  FIG.  2 B  is a partially enlarged view of the area marked with ‘A’ of  FIG.  2 A . 
     Referring to  FIGS.  1 ,  2 A and  2 B , a package substrate  50  according to an example embodiment may include a base  15  having a front side  15   s   1  and an opposing back side  15   s   2 , front pads  20  on the front side  15   s   1  of the base  15 , support patterns  25  having a thickness greater than a thickness of each of the front pads  20  on the front side  15   s   1  of the base  15 , and a protective insulating layer  30  having openings  30   o  respectively exposing the front pads  20 , on the front side  15   s   1  of the base  15 , and on an upper surface and a side surface of each of the support patterns  25 . 
     The base  15  may include a plurality of base insulating layers  5  and a conductive structure  10  penetrating through the plurality of base insulating layers  5 . The plurality of base insulating layers  5  may include first, second, and third base insulating layers  5   a ,  5   b , and  5   c  that are sequentially stacked. The conductive structure  10  may include an interconnection structure electrically connecting the front pads  20  and rear pads  35 . 
     The conductive structure  10  may include at least one of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C), or an alloy of two or more metals thereof. 
     The front pads  20  may be formed of a conductive material. For example, the front pads  20  may be formed of the same material as the conductive structure  10 . 
     The support patterns  25  may be spaced apart from each other. The support patterns  25  may be formed of a conductive material. For example, the support patterns  25  may include a copper material. 
     The protective insulating layer  30  may include a solder resist material or a photo solder resist material. 
     The package substrate  50  may further include the rear pads  35  below the back side  15   s   2  of the base  15 , a rear insulating layer  40  having openings to expose the rear pads  35 , below the back side  15   s   2  of the base  15 , and lower connection patterns  45  contacting the rear pads  35 , below the rear pads  35 . The lower connection patterns  45  may have a land, ball, or pin shape. The lower connection patterns  45  may include a solder material, for example, tin (Sn) or an alloy including tin (Sn) (e.g., Sn—Ag—Cu). The lower connection patterns  45  may be electrically connected to an external device such as a module board or a system board. 
     In an example, the package substrate  50  may be a printed circuit board. In another example, the package substrate  50  may be a redistribution substrate. In another example, the package substrate  50  may be an interposer substrate. 
     A semiconductor package  1   a  according to an example embodiment may include the package substrate  50 . 
     The semiconductor package  1   a  may include a lower semiconductor chip  60  on the package substrate  50 , a first upper semiconductor chip  75 , and one or more second upper semiconductor chips  90   a  and  90   b . 
     The lower semiconductor chip  60  may be on the protective insulating layer  30  and may be between at least two of the support patterns  25  in a top view. For example, in a top view, the support patterns  25  may include a first support pattern  25   a  and a second support pattern  25   b  that are arranged in a first horizontal direction X, and a third support pattern  25   c   and a fourth support pattern  25   d  arranged in a second horizontal direction (Y) perpendicular to the first horizontal direction X. The first and second horizontal directions X and Y may be parallel to the front side  15   s   1  of the base  15 . The lower semiconductor chip  60  may be between the first support pattern  25   a  and the second support pattern  25   b  and between the third support pattern  25   c  and the fourth support pattern  25   d . Accordingly, the lower semiconductor chip  60  may be surrounded by the first to fourth support patterns  25   a ,  25   b ,  25   c , and  25   d . 
     The first and second support patterns  25   a  and  25   b  may have a line shape or a bar shape extending in the second horizontal direction (Y). The first support pattern  25   a  may have a width greater than the width of the second support pattern  25   b . 
     The first and second support patterns  25   a  and  25   b  may have a larger size than the third and fourth support patterns  25   c  and  25   d . 
     A center of the lower semiconductor chip  60  may deviate from a center of the package substrate  50 . For example, the center of the lower semiconductor chip  600  may be located between the center of the package substrate  50  and one side of the package substrate  50 . 
     The protective insulating layer  30  may include a first portion  30 U positioned on an upper surface of each of the support patterns  25 , and a second portion that does not cover the support patterns  25  and the front pads  20 . A portion of the second portion  30 L may be located below the lower semiconductor chip  60 . 
     In the protective insulating layer  30 , the thickness of the first portion  30 U may be in a range of about 10 µm to about 20 µm 
     In the protective insulating layer  30 , the thickness of the second portion  30 L of the protective insulating layer  30  positioned below the lower semiconductor chip  60  may range from about 10 µm to about 40 µm 
     The thickness of the lower semiconductor chip  60  may be in a range of about  70  µm to about 200 µm. 
     The upper surface of the lower semiconductor chip  60  and the upper surface of the first portion  30 U of the protective insulating layer  30  positioned on the upper surface of each of the support patterns  25  may be located substantially on the same level. 
     The front pads  20  may include a first front pad  20   a , a second front pad  20   b , and a third front pad  20   c . 
     The semiconductor package  1   a  may further include a first adhesive layer  55  in contact with the lower surface of the lower semiconductor chip  60  and the protective insulating layer  30  positioned below the lower semiconductor chip  60 . 
     The semiconductor package  1   a  may further include a first bonding wire  65  electrically connecting a chip pad  60 P of the lower semiconductor chip  60  and the first front pad  20   a . 
     The first upper semiconductor chip  75  may vertically overlap the lower semiconductor chip  60  and the support patterns  25  on the package substrate  50 . 
     The semiconductor package  1   a  may further include a second adhesive layer  70 . The second adhesive layer  70  may contact a lower surface of the first upper semiconductor chip  75 , an upper surface of the protective insulating layer  30  positioned on upper surfaces of the support patterns  25 , and an upper surface of the lower semiconductor chip  60 . 
     The semiconductor package  1   a  may further include a second bonding wire  80  electrically connecting the chip pad  75   p  of the first upper semiconductor chip  75  and the second front pad  20   b . 
     The one or more second upper semiconductor chips  90   a  and  90   b  may be on the first upper semiconductor chip  75 . The one or more second upper semiconductor chips  90   a  and  90   b  may be provided as a plurality of upper semiconductor chips. The semiconductor package  1   a  may further include third adhesive layers  85   a  and  85   b  contacting lower surfaces of the plurality of second upper semiconductor chips  90   a  and  90   b , respectively. 
     The semiconductor package  1   a  may further include a third bonding wire  93  electrically connecting the chip pads  90   p  of the plurality of second upper semiconductor chips  90   a  and  90   b  and the third front pad  20   c  to each other. 
     The lower semiconductor chip  60 , the first upper semiconductor chip  75 , and the plurality of second upper semiconductor chips  90   a  and  90   b  may be on different height levels. Accordingly, the semiconductor package  1   a  may include a plurality of semiconductor chips stacked in the vertical direction Z on the package substrate  50 , for example, the lower semiconductor chip  60 , the first upper semiconductor chip  75 , and the plurality of second upper semiconductor chips  90   a  and  90   b . 
     The semiconductor package  1   a  may further include an encapsulant  96  on the package substrate  50 . The encapsulant  96  may be on the first upper semiconductor chip  75  and the plurality of second upper semiconductor chips  90   a  and  90   b  and may be in contact with a portion of the protective insulating layer  30  and a side surface of the lower semiconductor chip  60 . The encapsulant  96  may be Epoxy Molding Compound (EMC). 
     In an example embodiment, the lower semiconductor chip  60 , the first upper semiconductor chip  75 , and the one or more second upper semiconductor chips  90   a  and  90   b  may be different types of semiconductor chips. For example, the lower semiconductor chip  60  may be a controller semiconductor chip, the first upper semiconductor chip  75  may be a DRAM memory semiconductor chip, and one or more second upper semiconductor chips  90   a  and  90   b  may be a NAND flash memory semiconductor chip. Accordingly, the semiconductor package  1   a  may include at least two types, for example, three types of semiconductor chips. Accordingly, by including various types of semiconductor chips in one semiconductor package  1   a , it is possible to provide the semiconductor package  1   a  which is miniaturized, has high performance, and has high reliability. In addition, the one or more second upper semiconductor chips  90   a  and  90   b , which may be NAND flash memory semiconductor chips for storing data, may be provided in plurality. Accordingly, the semiconductor package  1   a  having an increased data storage capacity may be provided. 
     In an example embodiment, the types of the lower semiconductor chip  60 , the first upper semiconductor chip  75 , and the one or more second upper semiconductor chips  90   a  and  90   b  may not be limited to the above-described controller semiconductor chip, DRAM memory semiconductor chip and NAND flash memory semiconductor chip. For example, the first upper semiconductor chip  75  may include at least one of the following: logic chips, such as a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, and an application-specific IC (ASIC). At least one of the second upper semiconductor chips  90   a  and  90   b  may include at least one of a volatile memory semiconductor chip (e.g., DRAM memory semiconductor chip) or non-volatile memory (e.g., NAND flash memory semiconductor chip). 
     In an example embodiment, the support patterns  25  may be formed as metal posts formed of a metal material, for example, copper posts (Cu posts), which may be easily adjusted in thickness, inexpensively formed compared to a dummy semiconductor chip, and formed in various shapes or sizes, thereby improving productivity. 
     In an example embodiment, the lower semiconductor chip  60  may be closer to the third front pad  20   c  than to the second front pad  20   b . For example, the distance between the lower semiconductor chip  60  and the third front pad  20   c  may be smaller than the distance between the lower semiconductor chip  60  and the second front pad  20   b . Accordingly, it is possible to reduce the routing distance between the controller semiconductor chip, for example, the lower semiconductor chip  60  and the NAND flash memory semiconductor chip, for example, the one or more second upper semiconductor chips  90   a  and  90   b , and thus, performance of the semiconductor package  1   a , for example, signal integrity (SI) characteristics, may be improved. 
     In an example embodiment, the support patterns  25  may serve to prevent the first upper semiconductor chip  75  from being bent or deformed. For example, the support patterns  25 , which may be formed of a metal material whose thickness and size may be easily adjusted, may change in thickness according to the thickness of the lower semiconductor chip  60 . Accordingly, the support patterns  25  and the first portions  30 U of the protective insulating layer  30  on upper surfaces of the support patterns  25  may support the first upper semiconductor chip  75  together with the lower semiconductor chip  60  and may reduce or prevent bending or deformation of the first upper semiconductor chip  75 . 
     In an example embodiment, the support patterns  25  may be sized or positioned such that the encapsulant  96  fills spaces between the support patterns  25  and the lower semiconductor chip  60  without voids. 
     In an example embodiment, the support patterns  25  may be formed as various shapes or sizes to reduce or prevent the semiconductor package  1   a  from being bent or deformed. 
     Next, various modifications of the semiconductor package according to an example embodiment will be described with reference to  FIGS.  3 ,  4  and  5   , respectively.  FIGS.  3 ,  4 , and  5    are cross-sectional views illustrating various modified examples of a semiconductor package according to an example embodiment. 
     In a modified example, referring to  FIG.  3   , a semiconductor package  1   b  in the modified example may include support patterns  125  that may replace the support patterns  25  described with reference to  FIGS.  1  to  2 B . For example, each of the support patterns  125  may include a first support layer  122  and a second support layer  124  that are sequentially stacked. The first support layer  122  may be formed of the same material and the same thickness as the front pads  20 . The second support layer  124  may have a thickness greater than that of the first support layer  122 . The first support layer  122  may include a copper material. The second support layer  124  may include a copper material, but embodiments are not limited thereto. For example, the second support layer  124  may include a metal material and/or an insulating material that may be adhered to the first support layer  122 . 
     In a modified example, referring to  FIG.  4   , a semiconductor package  1   c  in the modified example may further include a heat dissipation structure  10   h . The heat dissipation structure  10   h  may be included in the package substrate  50  described with reference to  FIGS.  1  to  2 B . The heat dissipation structure  10   h  may be a portion of the conductive structure  10  of the base  15 . The heat dissipation structure  10   h  may be electrically isolated and may be in contact with the support patterns  25 , and in the conductive structure  10 , may be referred to as an interconnection structure  10   i  electrically connecting the front pads  20  and the rear pads  35 . Accordingly, the conductive structure  10  may include the interconnection structure  10   i  and the heat dissipation structure  10   h . The heat dissipation structure  10   h  may improve heat dissipation characteristics of the semiconductor package  1   c . 
     In a modified example, referring to  FIG.  5   , a semiconductor package  1   d  in the modified example may include the support patterns  125  as described in  FIG.  3    and the heat dissipation structure  10   h  as described in  FIG.  4   . Each of the support patterns  125  may include the first support layer  122  and the second support layer  124  stacked in sequence, and the first support layers  122  of the support patterns  125  may be in contact with the heat dissipation structure  10   h . 
     In some embodiments, the support patterns  25  and  125  may be in various shapes or sizes to reduce or prevent bending or deformation of the semiconductor package  1   a . Hereinafter, illustrative examples in which the support patterns  25  and  125  are deformed in various shapes and sizes will be described with reference to  FIGS.  6 ,  7 , and  8 A to  8 G . 
     First, a modified example of a semiconductor package according to an example embodiment will be described with reference to  FIGS.  6  and  7   .  FIG.  6    is a top view illustrating a modified example of a semiconductor package according to an example embodiment, and  FIG.  7    is a cross-sectional view illustrating a region taken along the line Ib-Ib′ of  FIG.  6   . 
     In a modified example, referring to  FIGS.  6  and  7   , a semiconductor package  1   d  in the modified example may include support patterns  225  that may replace the support patterns  25  in  FIG.  1   . For example, the support patterns  225  may include first support patterns  225   a  and second support pattern  225   b  arranged in the first horizontal direction (X), and a third support pattern  225   c  and a fourth support pattern  225   d  arranged in the second horizontal direction (Y). 
     In the top view of  FIG.  6   , the first support patterns  225   a  may be in plural on one side of the lower semiconductor chip  60 . Accordingly, in the top view as illustrate in  FIG.  6   , the number of the first support patterns  225   a  on the left side of the lower semiconductor chip  60  may be more than the number of the second support patterns  225   b  on the right side of the lower semiconductor chip  60 . 
     Next, various examples of the support patterns in a top view in the semiconductor package according to an example embodiment will be described with reference to  FIGS.  8 A to  8 G , respectively.  FIGS.  8 A to  8 G  are top views illustrating various modified examples of a semiconductor package according to an example embodiment. 
     In a modified example, referring to  FIG.  8 A , a semiconductor package  1   f  in the modified example may include support patterns  25  from which the third and fourth support patterns  25   c  and  25   d  among the first to fourth support patterns  25   a ,  25   b ,  25   c , and  25   d  described with reference to  FIG.  1    are omitted. Accordingly, the lower semiconductor chip  60  may be between the first and second support patterns  25   a  and  25   b . 
     In a modified example, referring to  FIG.  8 B , a semiconductor package  1   g  in the modified example may include a plurality of lower semiconductor chips  160  that may replace the lower semiconductor chip  60  described in  FIG.  1   . The plurality of lower semiconductor chips  160  may be on the same plane and may be spaced apart from each other. The plurality of lower semiconductor chips  160  may include a first lower semiconductor chip  160   a  and a second lower semiconductor chip  160   b  that are spaced apart from each other in the second horizontal direction (Y). 
     The semiconductor package  1   g  may include support patterns  25  in which the third and fourth support patterns  25   c  and  25   d  among the first to fourth support patterns  25   a ,  25   b ,  25   c , and  25   d  described in  FIG.  1    are omitted. Accordingly, the plurality of lower semiconductor chips  160  may be between the first support pattern  25   a  and the second support pattern  25   b . 
     In a modified example, referring to  FIG.  8 C , a semiconductor package  1   h  in the modified example may include a plurality of lower semiconductor chips  160  that may replace the lower semiconductor chip  60  described in  FIG.  1   . The plurality of lower semiconductor chips  160  may include a first lower semiconductor chip  160   a  and a second lower semiconductor chip  160   b  that are spaced apart from each other in the second horizontal direction (Y). 
     The semiconductor package  1   g  may include support patterns  25  in which the third and fourth support patterns  25   c  and  25   d  among the first to fourth support patterns  25   a ,  25   b ,  25   c , and  25   d  described in  FIG.  1    are omitted. The support patterns  25  may further include an intermediate support pattern  25   e  between the first lower semiconductor chip  160   a  and the second lower semiconductor chip  160   b . 
     In a modified example, referring to  FIG.  8 D , a semiconductor package  1   i  in the modified example may include support patterns  325  that may replace the support patterns  25  in  FIG.  1   . The support patterns  325  may include first support patterns  325   a  spaced apart from each other by dividing the first support pattern  25   a  of  FIG.  1    described in  FIG.  1   , second support pattern  325   b  spaced apart from each other by dividing the second support pattern (refer  25   b  of  FIG.  1   ) described with reference to  FIG.  1   , and third and fourth support patterns  325   c  and  325   d  corresponding to the third and fourth support patterns ( 25   c  and  25   d  of  FIG.  1   ) described in  FIG.  1   , respectively. The first support patterns  325   a  may be arranged in the first horizontal direction (X) and the second horizontal direction (Y). The support patterns  325  may have a dot shape or a square shape. 
     In a modified example, referring to  FIG.  8 E , a semiconductor package  1   j  in the modified example may include support patterns  425  that may replace the support patterns  25  in  FIG.  1   . Each of the support patterns  425  may have a line shape or a bar shape extending in any one direction, for example, the second direction Y. 
     In a modified example, referring to  FIG.  8 F , a semiconductor package  1   k  in the modified example may include support patterns  525  that may replace the support patterns  25  in  FIG.  1   . In a top view, the support patterns  525  may include a plurality of first support patterns  525   a  on the left side of the lower semiconductor chip  60 , a plurality of second support patterns  525   b  on the right side of the lower semiconductor chip  60 , a third support pattern  525   c  above the lower semiconductor chip  60 , and a fourth support pattern  525   d  below the lower semiconductor chip  600 . 
     The length of each of the first and second support patterns  525   a  and  525   b  in the second vertical direction Y may be greater than the length of each of the third and fourth support patterns  525   c  and  525   d  in the second vertical direction Y. A length of each of the first and second support patterns  525   a  and  525   b  in the second vertical direction Y may be greater than a length of the lower semiconductor chip  60  in the second vertical direction Y. 
     The center of the lower semiconductor chip  60  may be in a position deviated from the center of the package substrate  50 , but the example embodiment of the present inventive concept is not limited thereto. For example, the center of the lower semiconductor chip  60  may coincide with the center of the package substrate  50 . 
     In a modified example, referring to  FIG.  8 G , a semiconductor package  11  in the modified example may include support patterns  525  in which the third and fourth support patterns  525   c  and  525   d  among the first to fourth support patterns  525   a ,  525   b ,  525   c  and  525   d  in  FIG.  8 F  are omitted. Accordingly, the support patterns  525  may include the first support patterns  525   a  and the second support patterns  525   b . The semiconductor package  11  in the modified example may include a plurality of lower semiconductor chips  160  that may replace the lower semiconductor chip  60  described with reference to  FIG.  1   . The plurality of lower semiconductor chips  160  may include a first lower semiconductor chip  160   a  and a second lower semiconductor chip  160   b  that are spaced apart from each other in the second horizontal direction (Y). The support patterns  525  may further include an intermediate support pattern  525   e  between the first lower semiconductor chip  160   a  and the second lower semiconductor chip  160   b . 
     Next, referring to  FIG.  9   , an illustrative example of a method of forming a semiconductor package according to an example embodiment will be described with reference to  FIG.  9   .  FIG.  9    is a process flow diagram illustrating an example of a method of forming a semiconductor package according to an example embodiment. 
     Referring to  FIG.  9    together with  FIGS.  1  to  2 B , the base  15  may be formed (S 10 ). The base  15  may have the front side  15   s   1  and the back side  15   s   2  opposing each other. The base  15  may include the plurality of base insulating layers  5  and the conductive structure  10  penetrating through the plurality of insulating layers  5 . 
     The support patterns  25  may be formed on the front side  15   s   1  of the base  15  (S 20 ). The protective insulating layer  30  may be formed on the support patterns  25 , on the front side  15   s   1  of the base  15 , and to have the openings  30   o  exposing the first, second and third front pads  20   a ,  20   b  and  20   c  on the base  15  (S 30 ). The front pads  20  including the first to third front pads  20   a ,  20   b  and  20   c  may be formed like a portion of the conductive structure  10 . 
     The support patterns  25  may be formed of a conductive material such as a copper material. 
     The protective insulating layer  30  may be on an upper surface and a side surface of each of the support patterns  25 . The protective insulating layer  30  may be formed of a solder resist material or a photo solder resist material. 
     In an example, the support patterns  25  may be formed after the front pads  20  are formed. 
     In another example, the support patterns  25  may be replaced with the support patterns ( 125  in  FIG.  3   ) formed by including forming the first support layer ( 122  in  FIG.  3   ) simultaneously with the front pads  20  and forming the second support layer ( 124  in  FIG.  3   ) on the first support layer ( 122  in  FIG.  3   ). 
     The lower semiconductor chip  60  electrically connected to the first front pad  20   a  may be mounted (S 40 ). Mounting the lower semiconductor chip  60  may include forming a first adhesive layer  55  on the lower surface of the lower semiconductor chip  60 , enabling the first adhesive layer  55  formed on the lower surface of the lower semiconductor chip  60  to contact the protective insulating layer  30  in a position spaced apart from the support patterns  25 , and forming the first bonding wire  65  electrically connecting the chip pad  60 P of the lower semiconductor chip  60  and the first front pad  20   a  by performing a wire bonding process. 
     A first upper semiconductor chip  75  may be mounted to vertically overlap the lower semiconductor chip  60  and the support patterns  25  and electrically connected to the second front pad  20   b  (S 50 ). 
     Mounting the first upper semiconductor chip  75  may include forming a second adhesive layer  70  on a lower surface of the first upper semiconductor chip  75 , enabling the first adhesive layer  70  formed on the lower surface of the first upper semiconductor chip  75  to contact the portions  30 U of the protective insulating layer  30  positioned on the upper surfaces of the support patterns  25  and the upper surface of the lower semiconductor chip  60 , and forming a second bonding wire  80  electrically connecting the chip pad  75   p  of the first upper semiconductor chip  75  and the second front pad  20   b  by performing a wire bonding process. 
     One or more second upper semiconductor chips  90   a  and  90   b  may be mounted to be electrically connected to the third front pad  20   c , on the first upper semiconductor chip  75  (S 60 ). 
     The one or more second upper semiconductor chips  90   a  and  90   b  may be plural. The mounting of the plurality of second upper semiconductor chips  90   a  and  90   b  may include forming third adhesive layers  85   a  and  85   b  on lower surfaces of the plurality of second upper semiconductor chips  90   a  and  90   b , respectively, sequentially stacking and attaching the plurality of second upper semiconductor chips  90   a  and  90   b  to the first upper semiconductor chip  75 , using the third adhesive layers  85   a  and  85   b , and forming a third bonding wire  93  electrically connecting the chip pads  90   p  of the second upper semiconductor chips  90   a  and  90   b  and the third front pad  20   c  by performing a wire bonding process. 
     Subsequently, an encapsulant ( 96  in  FIG.  2 A ) may be formed on the package substrate  50 . The encapsulant  96  may be on the first upper semiconductor chip  75  and the one or more second upper semiconductor chips  90   a  and  90   b , on the package substrate  50 , and may fill spaces between the support patterns  25  and the lower semiconductor chip  60 . 
     As set forth above, according to example embodiments, there is provided a semiconductor package including a package substrate a support pattern on a base and a protective insulating layer on at least an upper surface and a side surface of the support pattern, on the base, a lower semiconductor chip horizontally spaced apart from the support pattern, on the package substrate, and an upper semiconductor chip vertically overlapping the support pattern and the lower semiconductor chip. The support pattern may serve to support the upper semiconductor chip together with the lower semiconductor chip. Accordingly, since the upper semiconductor chip of the semiconductor package may be prevented from being bent or deformed, reliability of the semiconductor package may be improved. 
     The support pattern may be formed of a metal material such as copper or the like, instead of the dummy semiconductor chip, thereby improving productivity. For example, productivity may be improved by forming the support pattern as a metal post formed of a metal material with easy thickness control. 
     While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.