Patent Publication Number: US-7910412-B2

Title: Method of fabricating an array substrate

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application is a Continuation Application of U.S. patent application Ser. No. 09/793,103, filed on Feb. 27, 2001 now issued as U.S. Pat. No. 7,223,621, which claims priority to Korean Application No. 2000-9796, filed Feb. 28, 2000, all of which are hereby incorporated by reference as if fully set forth herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to X-ray sensing devices and to liquid crystal display (LCD) devices. More particularly, it relates to a method of fabricating thin film transistor (TFT) array substrates for use in X-ray sensing devices and in LCD devices. 
     2. Description of Related Art 
     X-ray sensing devices (referred to as X-ray detectors hereinafter) and liquid crystal display (LCD) devices include thin film transistors (TFTs) as switching elements. The X-ray detectors act as sensing devices and the LCD devices act as displaying devices. 
     Since the X-ray detectors employ TMTs, the X-ray detectors have the advantage of providing real time diagnosis. Operating principles and configurations of the X-ray detectors are explained hereinafter. 
       FIG. 1  is a cross-sectional view illustrating one pixel of an array substrate of a related art X-ray detector. That X-ray detector includes a thin film transistor (TFT) “T” on a substrate  1 , a photoconductive film  2 , and various conductive elements that are described subsequently. Also included, but not shown in  FIG. 1 , are a scanning integrated circuit and a data integrated circuit. 
     Still referring to  FIG. 1 , the photoconductive film  2  produces electron-hole pairs  6  in proportion to the strength of incident radiation, such as X-rays. Thus, the photoconductive film  2  acts as a photoelectric transducer that converts incident X-rays into electron-hole pairs  6 . An external voltage Ev is applied across a conductive electrode  7  to a pixel electrode  8 . That voltage causes the electron-hole pairs  6  in the photoconductive film  2  to separate such that X-ray induced electrical charges accumulate on the pixel electrode  8 . Those electrical charges are applied to a second capacitor electrode  13 , and are consequently stored in a storage capacitor “S” formed by the second capacitor electrode  13  and a first capacitor electrode  11  that is formed over a ground line  9 . The pixel electrode  8 , the first capacitor electrode  11  and the second capacitor electrode  13  are beneficially comprised of a transparent conductive material such as Indium-Tin-Oxide (ITO). Furthermore, an insulating dielectric layer  15  is interposed between the first capacitor electrode  11  and the second electrode  13 . That dielectric layer is beneficially comprised of Silicon Nitride (SiN x ). 
     When forming the first capacitor electrode  11 , the transparent conductive material such as ITO is deposited and patterned at a temperature of 210 degrees Celsius. However, when forming the insulating dielectric layer  15 , the deposition and patterning processes are performed, at a temperature of 250 degrees Celsius. Therefore, during the process of forming the insulating dielectric layer  15  after forming the first capacitor electrode  11 , the higher temperature (250 degrees Celsius) affects a surface of the first capacitor electrode  11 , and thus contact defects between the first capacitor electrode  11  and the insulating dielectric layer  15  occur. Namely, a gap or a space is formed in the interface where the first capacitor electrode  11  and the insulating dielectric layer  15  contact each other. 
     The problem described above also occurs in an array substrate for use in an LCD device.  FIG. 2  is a cross-sectional view illustrating one pixel of a related art LCD device. As shown, the LCD device  21  has lower and upper substrates  25  and  29  and an interposed liquid crystal layer  31 . The lower substrate  25  has the TFT “T” as a switching element to change an orientation of the liquid crystal molecules and includes a pixel electrode  23  to apply a voltage to the liquid crystal layer  31  according to signals of the TFT “T”. And, a protective insulation layer  33  is formed on the pixel electrode  23  and on the TFF “T” to protect the pixel electrode  23  and the TFT “T”. The upper substrate  29  has a common electrode  27  thereon. The common electrode  27  serves as an electrode for applying a voltage to the liquid crystal layer  31 . 
     Still referring to  FIG. 2 , the pixel electrode  23  contacts the drain electrode of the TFT “T” and applies a signal received therefrom to the liquid crystal layer  31 . Thus, the signal re-arranges the liquid crystal molecules into a determined pattern due to a spontaneous polarization in accordance with the applied signal. The LCD device displays images, due to the fact that the transmittance of light generated from a backlight device (not shown) is controlled by the re-arrangement of the liquid crystal molecules. Meanwhile, the pixel electrode  23  is formed of ITO as in the case of the X-ray detector described above, and the protective insulation layer  33  is formed of silicon nitride (SiN x ). 
     In the above-mentioned LCD device, during the process of forming the protective insulation layer after forming the pixel electrode, the higher temperature (250 degrees Celsius) affects the surface of the pixel electrode, and thus contact defects between the pixel electrode and the protective insulation layer occur. Namely, a gap or a space, as described in the case of the X-ray detector, is formed in the interface where the pixel electrode and the protection layer touch each other. These gaps or spaces decrease the manufacturing yield and throughput. 
     SUMMARY OF THE INVENTION 
     This invention has been developed in order to address the above-described problem. 
     An object of this invention is to provide an array substrate for use in an X-ray sensing device and in an LCD device. Furthermore, it is an object of the present invention to reduce defects occurring in the interface where the transparent conductive metallic layer and insulating layer touch each other. 
     Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from that description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     In order to accomplish the above object, the principles of the present invention provide a method of fabricating an array substrate for use in an X-ray sensing device and in an LCD device, the array substrate having gate, source and drain electrodes as a switching element, and a transparent conductive metallic layer, the method including: treating a surface of the transparent conductive metallic layer with plasma gas; and forming an insulation layer on the transparent conductive metallic layer and over the switching element. 
     The insulation layer is beneficially made of silicon nitride (SiNx), and the transparent conductive metallic layer is beneficially made of ITO (indium-tin-oxide). 
     The transparent conductive metallic layer is a pixel electrode that contacts the drain electrode or is one of the capacitor electrodes. 
     The plasma gas beneficially includes one of nitrogen (N), helium (He) and argon (Ar). 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which: 
         FIG. 1  is a cross-sectional view of one pixel of a conventional X-ray sensing device; 
         FIG. 2  is a cross-sectional view of one pixel of a conventional LCD device; 
         FIG. 3  is a partial plan view of an array substrate for use in an X-ray detector that is in accord with the principles of the present invention; 
         FIG. 4A to 4D  are cross-sectional views taken along line IV-IV of  FIG. 3 ; 
         FIG. 5  is a partial plan view of an array substrate for use in an LCD device in accord with the principles of the present invention; 
         FIG. 6A to 6E  are cross-sectional views taken along line VI-VI of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS 
     Reference will now be made in detail to illustrated embodiments of the present invention, examples of which are shown in the accompanying drawings. 
       FIG. 3  is a plan view illustrating one pixel of an array substrate for an X-ray detector according to one embodiment. As shown, gate line  50  is arranged in a transverse direction and data line  53  is arranged in a longitudinal direction. A TFT “T” is formed near the crossing of the gate and data lines  50  and  53 . The TFT acts as a switching element and comprises gate, source and drain electrodes  73 ,  32  and  33  respectively. A ground line  42  is arranged perpendicular to the gate line  50 . That ground line  42  crosses a storage capacitor region “S”. The ground line  42  acts as a common line for neighboring pixels. 
     A first capacitor electrode  58  and a second capacitor electrode  60  of a storage capacitor “S” are located in a pixel area, with the pixel area being the region between the gate and data lines. Additionally, although not shown in  FIG. 3 , a dielectric insulation layer  81  (see  FIG. 4D ) of Silicon Nitride (SiN x ) is interposed between first capacitor electrode  58  and the second capacitor electrode  60 . Pixel electrode  62  that extends over the TFT “T” is then located in the pixel area. Although not shown in  FIG. 3 , in order to store the charges which are generated in the photoconductive film (not shown), the pixel electrode  62  electrically connects to the second capacitor electrode  60  of that pixel. Furthermore, the pixel electrode  62  is electrically connected to the drain electrode  33  of that pixel&#39;s TFT “T” via a drain contact hole  85 . 
     An operating principle of the x-ray detector will be explained hereinafter. The charges generated in the photoconductive film (not shown) are gathered in the pixel electrode  62  and stored in the storage capacitor “S” that is comprised of the second capacitor electrode  60 , the first capacitor electrode  58  and the dielectric insulation layer (not shown). These stored charges transfer to the drain electrode  33  through the pixel electrode  62 , and display the X-ray images. 
     The fabrication steps of the array substrate illustrated in  FIG. 3  will be explained with reference to  FIGS. 4A to 4D , which are cross-sectional views taken along lines IV-IV. 
     Referring to  FIG. 4A , a first metal layer is formed on a substrate  71  by depositing a metallic material such as Aluminum (Al), Al-alloy, Molybdenum (Mo), Tantalum (Ta), Tungsten (W), Niobium (Nb) or Antimony (Sb). A gate line (see element  50  of  FIG. 3 ) and a gate electrode  73  that extends from the gate line are then formed by patterning the first metal layer. Then, a first insulation layer  75  is deposited over the substrate  71  and over the first patterned metal layer. The first insulation layer  75  can be comprised of an inorganic substance, such as Silicon Nitride (SiN x ) or Silicon Oxide (SiO x , or of an organic substance such as BCB (Benzocyclobutene) or an acryl. Silicon Nitride (SiN x ) is assumed to be employed hereinafter. 
     Still referring to  4 A, a pure amorphous silicon (a-Si:H) layer and a doped amorphous silicon (n +  a-Si:H) layer are sequentially formed over the first insulation layer  75 . Those silicon layers are then patterned in an island shape to form a semiconductor layer  77 . Either CVD (Chemical Vapor Deposition) or the ion injection method is used to form the doped amorphous silicon layer. CVD is beneficially employed in the present invention. 
     Next, a source electrode  32 , a drain electrode  33 , and a ground line  42  are then formed by depositing a second metal layer. The second metal layer is then patterned to form the source electrode  32 , which extends from the data line (reference element  53  of  FIG. 3 ) over the gate electrode  73 ; the drain electrode  33 , which is spaced apart from the source electrode  32  and over the gate electrode  73 ; and the ground line  42 , which crosses under the storage capacitor “S” (see  FIG. 3 ). A portion of the doped amorphous silicon layer of the semiconductor layer  77  is then etched to form a channel region “CH” using the source and drain electrodes  32  and  33  as masks. Thus, the TFT “T” (see  FIG. 3 ) is complete. 
     Next, the first capacitor electrode  58  is formed over the ground line  42  by depositing and patterning a transparent conductive material such as Indium-Tin-Oxide (ITO). The first capacitor electrode  58  is in electrical contact with the ground line  42 . At this time, the first capacitor electrode  58  can exchange places with the ground line  42 . 
       FIG. 4B  shows a step of performing an N 2  plasma process. As shown, the surface of the first capacitor electrode  58  is plasma-treated by the N 2  plasma gas  79 . The N 2  plasma gas  79 , which is accelerated and then strikes against the surface of the first capacitor electrode  58 , removes the impurities that adhere to a surface of the first capacitor electrode  58 . Simultaneously, the N 2  plasma gas  79  changes the lattice structure of the surface of the first capacitor electrode  58 . Therefore, the interface characteristics, between the first capacitor electrode  58  and a dielectric insulation layer that is formed in a later step, are sufficiently improved. Namely, the plasma treatment, which is performed before forming the dielectric insulation layer, is an important process because it prevents product defects, such as a gap or a space between the first capacitor electrode  58  and a dielectric insulation layer. In the above-mentioned plasma treatment, an inert gas such as argon (Ar) or helium (He) can be used instead of N 2  gas. 
     Referring to  FIG. 4C , a dielectric insulation layer  81  is then formed over the TFT, over the first capacitor electrode  58 , and over the first insulation layer  75  by depositing Silicon Nitride (SiN x ). The step of performing the plasma treatment and the step of forming the dielectric protection layer can be conducted in the same chamber. 
     Referring to  FIG. 4D , a second capacitor electrode  60 , which corresponds in size to the first capacitor electrode  58 , is then formed on the dielectric insulation layer  81  and over the first capacitor electrode  58 . The second capacitor electrode  60  is beneficially comprised of a transparent conductive material such as Indium-Tin-Oxide (ITO). A second insulation layer  83  is then formed, beneficially by depositing an organic substance such as BCB (Benzocyclobutene). BCB is a good choice because it has a low dielectric permittivity. 
     Next, the second insulation layer  83  and the dielectric insulation layer  81  are etched to form a drain contact hole  85  over the drain electrode  33 . Simultaneously, a capacitor electrode contact hole  87  is formed by etching the second insulation layer  83  over the second capacitor electrode  60 . 
     Still referring now to  FIG. 4D , a pixel electrode  62 , which connects to the drain electrode  33  via the drain contact hole  85 , and to the second capacitor electrode  60  via the capacitor electrode contact hole  87 , is formed by depositing and patterning a transparent conductive material such as ITO. 
     With respect to the above-mentioned processes, since the surface of the first capacitor electrode is plasma-treated by the N 2  plasma before forming the dielectric insulation layer on the first capacitor electrode, the interface characteristics between the dielectric insulation layer and the first capacitor electrode are improved. And thus, the gaps or the spaces are prevented from being formed in the interface where the first capacitor electrode and the dielectric insulation layer contact each other. 
       FIG. 5  is a plan view of one pixel of an array substrate for use in an LCD device. As shown, the array substrate for use in the LCD device is generally comprised of a TFT “T”, a pixel “P” and gate and data lines  93  and  95 . The gate line  93  and data line  95  cross each other and define the pixel region “P”. The TFT “T” is positioned near the crossing of the gate line  93  and the data line  95 . The TFT “T” also includes a gate electrode  103  that is extends from the gate line  93 , an active layer  101 , a source electrode  97  that extends from the data line  95  and overlaps one end of the gate electrode  103 , and a drain electrode  99  that is spaced apart from the source electrode  97  and overlaps the other end of the gate electrode  103 . A pixel electrode  105  is formed in the pixel region “P” and directly contacts the drain electrode  99 . Some portion of the pixel electrode  105  overlaps the gate line  93  and forms a storage capacitor “C” with the gate line  93  and with a first insulation layer (See  FIG. 6C ). 
     The fabrication steps of the array substrate illustrated in  FIG. 5  will be explained with reference to  FIGS. 6A to 6E , which are cross-sectional views taken along line VI-VI of  FIG. 5 . 
     Referring now to  FIG. 6A , a first metal layer is formed on a substrate  91  by depositing a metallic material such as Aluminum (Al), Al-alloy, Molybdenum (Mo), Tantalum (Ta), Tungsten (W), Niobium (Nb) or Antimony (Sb). The first metal layer is patterned to form a gate line  93  and a gate electrode  103  that extends from the gate line  93 . After the first metal layer is patterned, a first insulation layer  92  is formed on the substrate  91  and over the patterned first metal layer. Beneficially, the first insulation layer  92  is an inorganic substance such as Silicon Nitride (SiN x ) or Silicon Oxide (SiO x ). 
     Referring now to  FIG. 6B , a pure amorphous silicon (a-Si:H) layer and a doped amorphous silicon (n +  a-Si:H) layer are then sequentially formed over the first insulation layer  92 . Those silicon layers are then patterned to form an active layer  101  and an ohmic contact layer  101   a  in an island shape. Either CVD (Chemical Vapor Deposition) or an ion injection method is beneficial in forming the doped amorphous silicon layer. 
     Referring now to  FIG. 6C , a source electrode  97 , a drain electrode  99 , and a data line  95  are then formed. First, a second metal layer is deposited. That second metal layer is then patterned to form the source electrode  97 , the drain electrode  99 , and the data line  95 . Referring now to both  FIG. 5  and  FIG. 6C , the source electrode  97  is formed over the gate electrode  103  as an extension of the data line  95 . The drain electrode  99  is formed over part of the gate electrode  103  and spaced apart from the source electrode  97 . A portion of the to ohmic contact layer  101   a  on the active layer  101  is then etched to form a channel region “CH” using the source and drain electrodes  97  and  99  as masks. Thus, the TFT “T” (see  FIG. 5 ) is completed. 
     Still referring to  FIG. 6C , a pixel electrode  105  is then formed on the first insulation layer  92  by depositing and patterning a transparent conductive material such as Indium-Tin-Oxide (ITO). As shown, the pixel electrode  105  is in contact with the drain electrode  99  by overlapping one end of the drain electrode  99 . Moreover, the pixel electrode  105  overlaps some portion of the gate line  93 , and thus a storage capacitor “C” is formed. Namely, the storage capacitor “C” is comprised of the gate line  93 , the pixel electrode  105 , and the interposed first insulation layer  92 . 
     Referring now to  FIG. 6D , an N 2  plasma process is performed. As shown, a surface of the pixel electrode  105  is plasma-treated by the N 2  plasma gas  96 . The N 2  plasma gas  96 , which is accelerated and then strikes against the surface of the pixel electrode  105 , removes the impurities that adhere to the surface of the pixel electrode  105 . Simultaneously, the N 2  plasma gas  96  changes the lattice structure of the surface of the pixel electrode  105 . Therefore, the interface characteristics, between the pixel electrode  105  and a second insulation layer that is formed in a later step, are sufficiently improved. Namely, the plasma treatment, which is performed before forming the second insulation layer, is an important process because it prevents the product defects as described above with respect to the X-ray detector. In the above-mentioned plasma treatment, an inert gas such as argon (Ar) or helium (He) can be used instead of N 2  gas. 
     Referring to  FIG. 6E , a Silicon Nitride (SiN x ) insulation layer  107  is then formed over the TFT “T,” over the pixel electrode  105  and over the first insulation layer  92 . The step of performing the plasma treatment and the step of forming the insulation layer  107  can be conducted in the same chamber. 
     As described above, it is desirable that the ITO electrode is plasma-treated by the N 2  plasma before forming the insulation layer on the ITO. Accordingly, in the illustrated embodiment of the present invention, since the capacitor and pixel electrode that are made of the transparent conductive material such as ITO (indium-tin-oxide) are plasma-treated by the N 2  plasma gas, the interface characteristics are improved, and the gaps or spaces are prevented between the transparent conductive material and the silicon (Si)-based layer. Therefore, the manufacturing yield is raised, and the manufacturing defects caused in the array substrate are decreased. The throughput of the array substrate is also increased. 
     Other embodiments and features of the invention will be apparent to the skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.