Patent Publication Number: US-11387231-B2

Title: Semiconductor device

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present disclosure relates to a semiconductor device. 
     Description of the Background Art 
     Conventionally, a semiconductor device provided with a bootstrap capacitor is known (for example, see European Patent Application No. 743752). The bootstrap capacitor is included in a bootstrap circuit that is used to ensure a proper power supply to a driver circuit biased to a high potential. In the semiconductor device mentioned above, the bootstrap capacitor, which serves as a target element to be charged, is basically charged in a very short time. Therefore, as disclosed in European Patent Application No. 743752, the bootstrap capacitor is charged via a LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor that may operate as a substitute for a high breakdown voltage diode. 
     SUMMARY OF THE INVENTION 
     In the semiconductor device mentioned above, in order to prevent the semiconductor device from being damaged by the operation of a parasitic transistor that includes the LDMOS transistor, the source potential control circuit and the back gate potential control circuit are connected. The two control circuits control the potentials of the source electrode and the back gate electrode of the LDMOS transistor so as to prevent the parasitic transistor from operating. Such a complicated circuit including the source potential control circuit and the back gate potential control circuit is a main factor that increases the manufacturing cost of the semiconductor device. 
     The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a semiconductor device capable of reducing the manufacturing cost. 
     A semiconductor device according to the present disclosure is a semiconductor device that supplies a charging current to charge a target element, and includes a semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a source electrode, a drain electrode, a back gate electrode, and a gate electrode. The first semiconductor region is electrically connected to the first electrode of the target element. The first semiconductor region is formed on the main surface of the semiconductor layer. The second semiconductor region is formed on the main surface of the semiconductor layer and arranged adjacent to the first semiconductor region. The third semiconductor region is formed on the surface of the second semiconductor region and is supplied with a power supply voltage. The source electrode is connected to the third semiconductor region and is supplied with the power supply voltage. The drain electrode is connected to the first semiconductor region and is electrically connected to the first electrode. The back gate electrode is connected to a region in the second semiconductor region separated from the third semiconductor region and is grounded. The gate electrode is arranged to face a channel region located in the second semiconductor region between the third semiconductor region and the first semiconductor region with a gate insulating film interposed therebetween. The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage. 
     The foregoing and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a first embodiment; 
         FIG. 2  is a schematic cross-sectional view illustrating a part of the semiconductor device illustrated in  FIG. 1 ; 
         FIG. 3  is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a comparative example; 
         FIG. 4  is a schematic cross-sectional view illustrating a part of the semiconductor device illustrated in  FIG. 3  according to the comparative example; 
         FIG. 5  is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a second embodiment; 
         FIG. 6  is a schematic cross-sectional view illustrating a part of the semiconductor device illustrated in  FIG. 5 ; 
         FIG. 7  is a schematic plan view illustrating a part of a semiconductor device according to a third embodiment; 
         FIG. 8  is a schematic sectional view taken along line VIII-VIII in  FIG. 7 ; 
         FIG. 9  is a schematic sectional view taken along line IX-IX in  FIG. 7 ; 
         FIG. 10  is a schematic plan view illustrating a part of a semiconductor device according to a fourth embodiment; 
         FIG. 11  is a schematic sectional view taken along line XI-XI in  FIG. 10 ; 
         FIG. 12  is a schematic sectional view taken along line XII-XII of  FIG. 10 ; 
         FIG. 13  is a circuit diagram illustrating a potential detection circuit in a semiconductor device according to a fifth embodiment; 
         FIG. 14  is a schematic plan view illustrating a part of a semiconductor device on which the circuit illustrated in  FIG. 13  is mounted; 
         FIG. 15  is a schematic sectional view taken along line XV-XV in  FIG. 14 ; 
         FIG. 16  is a schematic sectional view taken along line XVI-XVI in  FIG. 14 ; 
         FIG. 17  is a schematic sectional view taken along line XVII-XVII in  FIG. 14 ; 
         FIG. 18  is a schematic sectional view taken along line XVIII-XVIII in  FIG. 14 ; 
         FIG. 19  is a schematic plan view illustrating a part of a semiconductor device according to a sixth embodiment; 
         FIG. 20  is a schematic sectional view taken along line XX-XX of  FIG. 19 ; 
         FIG. 21  is a schematic sectional view taken along line XXI-XXI in  FIG. 19 ; 
         FIG. 22  is a schematic sectional view taken along line XXII-XXII in  FIG. 19 ; and 
         FIG. 23  is a circuit diagram illustrating a potential detection circuit in the semiconductor device according to a seventh embodiment. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, embodiments of the present disclosure will be described. It should be noted that the same or corresponding components are denoted by the same reference numerals, and the description thereof will not be repeated. 
     First Embodiment 
     &lt;Configuration of Semiconductor Device&gt; 
       FIG. 1  is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a first embodiment, and  FIG. 2  is a schematic cross-sectional view illustrating a part of the semiconductor device illustrated in  FIG. 1 .  FIG. 2  illustrates a cross-sectional configuration of a region where a high breakdown voltage N-channel MOS transistor  30  (also referred to as NchMOS) is formed and a region where a high potential circuit is formed in the semiconductor device. 
     The semiconductor device illustrated in  FIGS. 1 and 2  is a semiconductor device which mainly includes a high breakdown voltage control IC  25  and a bootstrap capacitor  39 , and is configured to control a transistor  36  and a transistor  35 . The high breakdown voltage control IC  25  mainly includes a transistor  30  which is a high breakdown voltage NchMOS transistor, a high potential circuit  26 , and a low potential circuit  27 . The high potential circuit  26  includes a transistor  31  which is a P-channel MOS transistor, and a transistor  32  which is an N-channel MOS transistor. The low potential circuit  27  includes a transistor  33  which is a P-channel MOS transistor, and a transistor  34  which is an N-channel MOS transistor. 
     The high breakdown voltage control IC  25  includes a first node  71 , a second node  72 , a third node  73 , a fourth node  74 , a fifth node  75 , a sixth node  76  and a seventh node  77 . The first electrode of the bootstrap capacitor  39  is connected to the first node  71  (node VB). The source of the transistor  31  is connected to the first node  71 . The drain of the transistor  31  is connected to the drain of the transistor  32  and the second node  72 . The source of the transistor  32  is connected to the third node  73  (node VS). The second electrode of the bootstrap capacitor  39  is connected to the third node  73  via the eighth node  78 . The gate electrode of the transistor  36 , which is a high voltage power semiconductor element, is connected to the second node  72 . The drain of the transistor  36  is connected to the high voltage power supply node  70 . The source of the transistor  36  is connected to the eighth node  78 . 
     The source of the transistor  33  in the low potential circuit  27  is connected to the seventh node  77  (node VCC). The drain of the transistor  33  is connected to the drain of the transistor  34  and the fourth node  74 . The source of the transistor  34  is connected to the fifth node  75  (node COM) and the sixth node  76  (node COM). The gate electrode of the transistor  35 , which is a low voltage power semiconductor element, is connected to the fourth node  74 . The drain of the transistor  35  is connected to the eighth node  78 . The source of the transistor  35  is connected to the fifth node  75  via the ninth node  79 . The ninth node  79  is grounded. 
     The positive electrode of the power supply  38  is connected to the seventh node  77 . The negative electrode of the power supply  38  is connected to the sixth node  76 . The gate electrode of the transistor  30  is connected to a gate driving circuit  37 . The gate driving circuit  37  is connected to the sixth node  76  and the seventh node  77 . The source of the transistor  30  is connected to the seventh node  77 . The drain of the transistor  30  is connected to the source of the transistor  31  and the first node  71 . The back gate electrode of the transistor  30  is grounded via the fifth node  75 . 
       FIG. 2  is a schematic cross-sectional view illustrating the transistor  30  and the high potential circuit  26  of the semiconductor device illustrated in  FIG. 1 . As illustrated in  FIG. 2 , the semiconductor device is formed, for example, on a semiconductor layer  1  which is a P-type semiconductor substrate having a first conductivity type. The main surface of the semiconductor layer  1  is formed with an N-type diffusion region  2  of an N conductivity type and a P-type diffusion region  3   a  of a P conductivity type which are arranged adjacent to each other. The N-type diffusion region  2  functions as a drift layer of the transistor  30  and contributes to electric conduction and breakdown voltage resistance. The main surface of the P-type diffusion region  3   a  is formed with a P + -type diffusion region  4   a  and an N-type diffusion layer  21 . The P + -type diffusion region  4   a  and the N-type diffusion layer  21  are separated from each other. An N + -type diffusion region  5   a  is formed in a part of the surface of the N-type diffusion layer  21 . The N-type diffusion layer  21  and the N + -type diffusion region  5   a  function as a source region for the transistor  30 . Isolation insulating films  14   f  and  14   a  are formed from a LOCOS oxide film or the like on the main surface of the semiconductor layer  1  and configured to sandwich the P + -type diffusion region  4   a  therebetween. The isolation insulating film  14   a  is arranged between the P + -type diffusion region  4   a  and the N + -type diffusion region  5   a . The isolation insulating film  14   a  and an isolation insulating film  14   b  are formed to sandwich the N + -type diffusion region  5   a  therebetween. The isolation insulating film  14   b  is disposed in the N-type diffusion layer  21  at a position separated from an edge of the N-type diffusion region  2 . 
     An insulating film  15  is formed as a gate insulating film for the transistor  30  on the surface of the N-type diffusion layer  21 , the P-type diffusion region  3   a  and the N-type diffusion region  2  at the other side of the isolation insulating film  14   b  relative to the N + -type diffusion region  5   a . An isolation insulating film  14   c  is formed on the surface of the N-type diffusion region  2  at the other side of the insulating film  15  relative to the isolation insulating film  14   b . A gate electrode  9   a  of the transistor  30  is formed on the insulating film  15 . The gate electrode  9   a  extends from the insulating film  15  to both the isolation insulating film  14   b  and the isolation insulating film  14   c . A back gate electrode  10   a  of the transistor  30  is connected to the P + -type diffusion region  4   a . A source electrode  10   b  of the transistor  30  is connected to the N + -type diffusion region  5   a . The source electrode  10   b  is connected to the positive electrode of the power supply  38 . The back gate electrode  10   a  is grounded. 
     An N + -type diffusion region  5   b  is formed on the surface of the N-type diffusion region  2  at the other side of the isolation insulating film  14   c  relative to the gate electrode  9   a . The N + -type diffusion region  5   b  is separated from the isolation insulating film  14   c . An insulating film  15  is formed on the surface of the N-type diffusion region  2 , extending from the isolation insulating film  14   c  to a position on the surface of the N + -type diffusion region  5   b . A polysilicon electrode  9   b  is formed to extend from the insulating film  15  to a position on the surface of the isolation insulating film  14   c . The polysilicon electrode  9   b  functions as a field plate. 
     The N + -type diffusion region  5   b  is connected by a drain electrode  10   c  of the transistor  30 . The drain electrode  10   c  is connected to the first node  71  and the first electrode of the bootstrap capacitor  39 . 
     The high potential circuit  26  is formed with a P-type diffusion region  3   b  on the surface of the N-type diffusion region  2 . The transistor  31  is formed on the surface of the N-type diffusion region  2 , and the transistor  32  is formed on the surface of the P-type diffusion region  3   b . Specifically, a P + -type diffusion region  4   b  and a P + -type diffusion region  4   c  are formed on the surface of the N-type diffusion region  2 . The P + -type diffusion region  4   b  is arranged to face the N + -type diffusion region  5   b  with the isolation insulating film  14   d  interposed therebetween. The P + -type diffusion region  4   b  is a source region for the transistor  31 . The P + -type diffusion region  4   c  is separated from the P + -type diffusion region  4   b . The P + -type diffusion region  4   c  is a drain region for the transistor  31 . The region between the P + -type diffusion region  4   b  and the P + -type diffusion region  4   c  forms a channel region for the transistor  31 . An insulating film  15  is formed on the surface of the N-type diffusion region  2 , extending from the P + -type diffusion region  4   b  to the P + -type diffusion region  4   c . The insulating film  15  located between the P + -type diffusion region  4   b  and the P + -type diffusion region  4   c  functions as a gate insulating film of the transistor  31 . A gate electrode  9   c  of the transistor  31  is formed on the insulating film  15 . 
     An N + -type diffusion region  5   c  and an N + -type diffusion region  5   d  are formed on the surface of the P-type diffusion region  3   b . The N + -type diffusion region  5   c  is arranged to face the P + -type diffusion region  4   c  with the isolation insulating film  14   e  interposed therebetween. The N + -type diffusion region  5   c  is a drain region for the transistor  32 . The N + -type diffusion region  5   d  is separated from the N + -type diffusion region  5   c . The N + -type diffusion region  5   d  is a source region for the transistor  32 . The region between the N + -type diffusion region  5   c  and the N + -type diffusion region  5   d  serves as a channel region for the transistor  32 . An insulating film  15  is formed on the surface of the P-type diffusion region  3   b , extending from the N + -type diffusion region  5   c  to the N + -type diffusion region  5   d . The insulating film  15  located between the N + -type diffusion region  5   c  and the N + -type diffusion region  5   d  functions as a gate insulating film of the transistor  32 . A gate electrode  9   d  of the transistor  32  is formed on the insulating film  15 . A P-type diffusion region  4   d  is formed on the surface of the P-type diffusion region  3   b , and is arranged adjacent to the N + -type diffusion region  5   d.    
     The drain electrode  10   c  of the transistor  30  is electrically connected to the N + -type diffusion region  4   b  of the transistor  31 . The P + -type diffusion region  4   c , which is the drain region for the transistor  31 , is connected to the N + -type diffusion region  5   c  of the transistor  31  via the electrode  10   d . An electrode  10   e  is formed to connect the N + -type diffusion region  5   d  and the P-type diffusion region  4   d . The electrode  10   e  is electrically connected to the third node  73  and the second electrode of the bootstrap capacitor  39 . 
     An interlayer insulating film  11  is formed so as to cover the gate electrodes  9   a ,  9   c  and  9   d  and the polysilicon electrode  9   b . A part of the back gate electrode  10   a , the source electrode  10   b , the drain electrode  10   c , the electrodes  10   d  and  10   e  extend on the upper surface of the interlayer insulating film  11 . A passivation film  12  is formed on the interlayer insulating film  11 . 
     In the semiconductor device mentioned above, the N-type diffusion layer  21  is configured to form a part of the source region for the transistor  30 , and withstand a breakdown voltage equal to or greater than the power supply voltage with respect to the P + -type diffusion region  4   a  as the back gate layer. The breakdown voltage may be arbitrarily adjusted by changing the impurity concentration in the N-type diffusion layer  21 , the size of the N-type diffusion layer  21 , or the like. 
     Each of the back gate electrode  10   a , the source electrode  10   b , the drain electrode  10   c , and the electrodes  10   d  and  10   e  may be made of any conductive material such as any metal. For example, each electrode may be made of aluminum (Al). The gate electrodes  9   a ,  9   c , and  9   d  may be made of silicon, for example. 
     The N-type diffusion region  2  also functions as a well for electrically isolating the high potential circuit  26  from the semiconductor layer  1 . However, the high potential circuit  26  may be electrically isolated by any other means. For example, the high potential circuit  26  may be electrically isolated from the semiconductor layer  1  by introducing a buried diffusion layer directly below the high potential circuit  26 . In addition, the P-type diffusion region  3   a  may be used as a back gate of the transistor  30 . As illustrated in  FIG. 2 , the drain region for the transistor  30  is preferably formed contiguously with the N-type diffusion region  2  where the high potential circuit  26  is formed, which makes it possible to reduce the footprint of the semiconductor device. If there is no influence on the breakdown voltage of the semiconductor device, a buried diffusion layer may be introduced so as to electrically connect the N-type diffusion region  2  where the high potential circuit  26  is formed and the drain region for the transistor  30 . 
     &lt;Effect of Semiconductor Device&gt; 
     The semiconductor device according to the present disclosure is a semiconductor device that supplies a charging current to a bootstrap capacitor  39  which serves as a target element to be charged, and includes, for example, a semiconductor layer  1  of a first conductivity type (P-type) as a P-type substrate, an N + -type diffusion region  5   b  and an N-type diffusion region  2  as a first semiconductor region of a second conductivity type (N-type), a N + -type diffusion region  4   a  and a P-type diffusion region  3   a  as a second semiconductor region of the first conductivity type, an N + -type diffusion region  5   a  as a third semiconductor region of the second conductivity type, a source electrode  10   b , a drain electrode  10   c , a back gate electrode  10   a , and a gate electrode  9   a . The first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ) is electrically connected to the first electrode of the bootstrap capacitor  39 . The first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ) is formed on the main surface of the semiconductor layer  1 . The second semiconductor region (the N + -type diffusion region  4   a  and the P-type diffusion region  3   a ) is formed on the main surface of the semiconductor layer  1  at a position adjacent to the first semiconductor region (the N-type diffusion region  2 ). The N + -type diffusion region  5   a  as the third semiconductor region is supplied with a power supply voltage (Vcc). The N + -type diffusion region  5   a  is formed on the surface of the second semiconductor region (the N + -type diffusion region  4   a  and the P-type diffusion region  3   a ). The source electrode  10   b  is connected to the third semiconductor region (the N + -type diffusion region  5   a ) and is supplied with the power supply voltage. The drain electrode  10   c  is connected to the first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ) and is electrically connected to the first electrode of the bootstrap capacitor  39 . The back gate electrode  10   a  is connected to a region in the second semiconductor region (the P + -type diffusion region  4   a  and the P-type diffusion region  3   a ) separated from the third semiconductor region (the N + -type diffusion region  5   a ) and is grounded. The gate electrode  9   a  is formed as a gate insulating film in the second semiconductor region (the P + -type diffusion region  4   a  and the P-type diffusion region  3   a ) and arranged to face a channel region located between the third semiconductor region (the N + -type diffusion region  5   a ) and the first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ) via the insulating film  15 . The breakdown voltage between the source electrode  10   b  and the back gate electrode  10   a  is greater than the power supply voltage. 
     With the above configuration, since a voltage greater than the power supply voltage (Vcc) may be applied to the source electrode  10   b  and the back gate electrode  10   a  may be fixed at the ground potential, the bootstrap capacitor  39  may be charged without providing an additional circuit for controlling the potential of the source electrode and the potential of the back gate electrode as in the related art. In other words, the charging operation may be performed on the bootstrap capacitor  39  by fixing the potential of the source electrode  10   b  and the potential of the back gate electrode  10   a  and controlling only the voltage of the gate electrode  9   a . As a result, it is possible to simplify the configuration of the circuit required for charging the bootstrap capacitor  39 , which makes it possible to reduce the manufacturing cost of the semiconductor device. 
     The semiconductor device includes an N-type diffusion layer  21  as the fourth semiconductor region of the second conductivity type. The fourth semiconductor region (the N-type diffusion layer  21 ) is formed in the second semiconductor region (the P + -type diffusion region  4   a  and the P-type diffusion region  3   a ) and arranged to surround the periphery of the third semiconductor region (the N + -type diffusion region  5   a ) and isolate the third semiconductor region (the N + -type diffusion region  5   a ) from the second semiconductor region (the N + -type diffusion region  4   a  and the P-type diffusion region  3   a ). The N-type diffusion layer  21  extends in the second semiconductor region (the P + -type diffusion region  4   a  and the P-type diffusion region  3   a ) from the periphery of the N + -type diffusion region  5   a  to a region which is opposed to the first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ) and separated from the first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ). The channel region is arranged in the second semiconductor region (the P + -type diffusion region  4   a  and the P-type diffusion region  3   a ) between the N-type diffusion layer  21  and the first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ). 
     Thus, the formation of the N-type diffusion layer  21  makes the breakdown voltage between the source electrode  10   b  and the back gate electrode  10   a  greater than the power supply voltage. With such a configuration, it is possible for the semiconductor device to perform the charging operation on the bootstrap capacitor  39  as described above. 
     The semiconductor device may have a breakdown voltage of 300 V or more. In the present disclosure, the breakdown voltage refers to a maximum voltage that may be applied between the drain electrode  10   c  and the source electrode  10   b.    
     Thus, the semiconductor device according to the present disclosure may be used as a high breakdown voltage semiconductor for performing gate driving of a power semiconductor that controls a high voltage power source such as a power source of an electric motor or the like. 
     The Effect of the semiconductor device according to the present embodiment will be described in more detail in comparison with a semiconductor device according to a comparative example.  FIG. 3  is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a comparative example, and  FIG. 4  is a schematic cross-sectional view illustrating a part of the semiconductor device illustrated in  FIG. 3  according to the comparative example. 
     The semiconductor device illustrated in  FIG. 3  according to the comparative example basically has the same circuit configuration as that of the semiconductor device according to the present embodiment illustrated in  FIG. 1  except that a source potential control circuit  140  is connected to the source electrode of the transistor  30  which serves as a high breakdown voltage MOS transistor and a back gate potential control circuit  139  is connected to the back gate electrode of the transistor  30 .  FIG. 4  is a schematic cross-sectional view of the transistor  30  and the high potential circuit  26  in the semiconductor device illustrated in  FIG. 3 . The semiconductor device according to the comparative example illustrated in  FIG. 4  basically has the same configuration as the semiconductor device according to the present embodiment illustrated in  FIG. 2  except that the configuration of the transistor  30  is different from that in the semiconductor device illustrated in  FIG. 2 . Specifically, in the semiconductor device illustrated in  FIG. 4 , a P-type diffusion region  6  is formed inside the N-type diffusion region  2 . A P + -type diffusion region  4   a  and an N + -type diffusion region  5   a  are formed on the surface of the P-type diffusion region  6  and separated from each other. A P + -type diffusion region  4   e  is formed on the main surface of the semiconductor layer  1  and separated from the P-type diffusion region  6  with the isolation insulating film  14   a  interposed therebetween. A back gate electrode  10   a  is connected to the P + -type diffusion region  4   a . A source electrode  10   b  is connected to the N + -type diffusion region  5   a . An electrode  10   f  is connected to the P + -type diffusion region  4   e . As described above, the back gate potential control circuit  139  is connected to the back gate electrode  10   a , and the source potential control circuit  140  is connected to the source electrode  10   b . The electrode  10   f  is grounded. 
     In the semiconductor device according to the comparative example as described above, in order to prevent the accidental operation of the transistor  30  and suppress the operation of the parasitic bipolar element, the back gate potential control circuit  139  and the source potential control circuit  140  are provided, which makes the circuit configuration of the semiconductor device according to the comparative example complicated, leading to an increase in the manufacturing cost. 
     On the contrary, the semiconductor device according to the present embodiment is formed with the N-type diffusion layer  21  so that a voltage sufficiently greater than the power supply voltage (Vcc) may be applied to the N + -type diffusion region  5   a  which serves as the source region. In addition, the back gate electrode  10   a  is grounded. Therefore, it is possible for the semiconductor device according to the present embodiment to prevent the parasitic bipolar element from operating with a simple circuit configuration, without the need of providing the back gate potential control circuit  139  and the source potential control circuit  140  as in the comparative example. 
     When the transistor  30  is used to charge the bootstrap capacitor  39 , the high potential circuit  26  transitions to a low potential when the output of the high potential circuit  26  is LOW and the transistor  36  which serves as a switch element is in an off state, the output of the low potential circuit  27  is high and the transistor  35  which serves as a switch element is in an on state. In this state, the bootstrap capacitor  39  may be charged by the transistor  30  which is a high breakdown voltage NchMOS transistor. The charging period is determined by an output command to each of the high potential circuit  26  and the low potential circuit  27  in the charging system. Therefore, the charging period may be logically determined by the system. The logically determined charging period may be sent to the gate driving circuit  37  of the transistor  30  to control the gate of the transistor  30  at an optimal timing so as to charge the bootstrap capacitor  39 . 
     Further, according to the semiconductor device of the present embodiment, since the back gate electrode  10   a  of the transistor  30  is grounded, as illustrated in  FIG. 2 , the P-type diffusion region  3   a  that constitutes the back gate may be formed in contact with the semiconductor layer  1 , without including the N-type diffusion region  2  that constitutes the drain layer of the transistor  30 , whereby the parasitic PNP transistor that is composed of the back gate, the drain and the semiconductor layer  1  as in the semiconductor device according to the comparative example may be eliminated. 
     Regarding the parasitic NPN transistor composed of the source, the back gate and the drain, in the semiconductor device according to the present embodiment, the source and the back gate are constantly and reversely biased by the power supply voltage (Vcc). Therefore, the parasitic operation in the state where the source of the transistor  30  becomes the emitter of the NPN transistor (in other words, the drain of the transistor  30  is in a high potential state and functions as the collector) may be sufficiently suppressed. As a result, it is possible to prevent the semiconductor device from being damaged by the parasitic operation. Note that the parasitic operation in the reverse direction, in other words, the parasitic operation in a state where the drain of the transistor  30  functions as the emitter of the NPN transistor contributes to the charging operation on the bootstrap capacitor  39 , and thereby will cause no problem. When the potential of the drain electrode of the transistor  30  becomes equal to or greater than the power supply voltage (Vcc), the charging operation is automatically terminated. 
     As described above, according to the semiconductor device of the present embodiment, it is possible to simplify the configuration of the system while eliminating the formation of the parasitic bipolar transistor and suppressing the parasitic operation, which makes it possible to reduce the manufacturing cost and improve the reliability (robustness) of the semiconductor device. 
     Second Embodiment 
     &lt;Configuration of Semiconductor Device&gt; 
       FIG. 5  is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a second embodiment, and  FIG. 6  is a schematic cross-sectional view illustrating a part of the semiconductor device illustrated in  FIG. 5 .  FIG. 6  illustrates a schematic cross-sectional view of a part of the transistor  30  in the semiconductor device. 
     The semiconductor device illustrated in  FIGS. 5 and 6  basically has the same configuration as the semiconductor device illustrated in  FIGS. 1 and 2 , but differs from the semiconductor device illustrated in  FIGS. 1 and 2  in that a limit resistor  41  is connected to the source of the transistor  30 . 
     As illustrated in  FIG. 5 , the source of the transistor  30  is connected to the seventh node  77  via the limit resistor  41 . The limit resistor  41  may be configured in various manners. For example, as illustrated in  FIG. 6 , the planar shape of the N-type diffusion layer  21  may be modified so as to relatively increase a distance L 1  between the N + -type diffusion region  5   a  and the channel region below the gate electrode  9   a . As a result, the N-type diffusion layer  21  located between the N + -type diffusion region  5   a  to which the source electrode  10   b  is connected and the channel region below the gate electrode  9   a  functions as the limit resistor. The resistance value of the limit resistor may be adjusted by changing the impurity concentration of the N-type diffusion layer  21  and the shape of the N-type diffusion layer  21 . The limit resistor has an effect of preventing the bootstrap capacitor  39  or any other elements in the semiconductor device from being damaged by a rush current that flows from the source to the drain of the transistor  30  when the parasitic NPN transistor is operating in the semiconductor device. 
     &lt;Effect of Semiconductor Device&gt; 
     The semiconductor device according to the present embodiment may further include a limit resistor  41 . The limit resistor  41  is arranged on a current path from the power supply  38 , which supplies the power supply voltage (Vcc), to the channel region. 
     Thus, the inclusion of the limit resistor  41  makes it possible to reduce the possibility that the bootstrap capacitor  39  or the like is damaged by the rush current that flows from the source electrode  10   b  to the drain electrode  10   c  when the parasitic NPN transistor is operating in the semiconductor device. 
     In the semiconductor device according to the present embodiment, the limit resistor  41  may be a portion of the N-type diffusion layer  21  which serves as the fourth semiconductor region and is located between the N + -type diffusion region  5   a  which serves as the third semiconductor region and the channel region. Thus, the resistance value of the limit resistor  41  may be easily adjusted by changing the impurity concentration and the shape of the N-type diffusion layer  21 . 
     Generally in the driving circuit of a power stage to which the semiconductor device according to the present embodiment is applied, a large current is supplied to a load having a large inductance such as an electric motor. Therefore, the potential of the third node  73  (VS), which is an intermediate connection point between the switch elements, may be affected by the surge of the inductance and become a negative potential. If the voltage of the third node  73  becomes a negative voltage equal to or less than (the potential (VB) of the first node  71 −the potential (VS) of the third node)), the voltage of the first node  71  is also biased to a negative voltage. As a result, the drain of the transistor  30  becomes a negative potential, which induces the parasitic NPN transistor into operation. 
     Specifically, the drain of the transistor  30  functions as an emitter, and the semiconductor layer  1  and the back gate of the transistor  30  are forward biased toward the drain to inject holes into the drain (the emitter), thereby functioning as a base. The source functions as a collector of the parasitic NPN transistor to inject electrons into the emitter (the drain). Since the bipolar transistor basically operates at a low impedance, a rush current is generated to flow from the source to the drain of the transistor  30 , which may damage the constituent elements in the semiconductor device such as the bootstrap capacitor  39 . However, by providing the N-type diffusion layer  21  as illustrated in  FIGS. 5 and 6 , it is possible to impart an appropriate electrical resistance to the source of the transistor  30 . As a result, when the parasitic NPN transistor is in operation, the N-type diffusion layer  21  may function as a limit resistor. 
     Third Embodiment 
     &lt;Configuration of Semiconductor Device&gt; 
       FIG. 7  is a schematic plan view illustrating a part of a semiconductor device according to a third embodiment,  FIG. 8  is a schematic sectional view taken along line VIII-VIII in  FIG. 7 , and  FIG. 9  is a schematic sectional view taken along line IX-IX in  FIG. 7 . The semiconductor device illustrated in  FIGS. 7 to 9  basically has the same configuration as the semiconductor device illustrated in  FIGS. 1 and 2 , but differs in the configuration of the gate of the transistor  30  and the structure for withstanding the breakdown voltage between the source and the back gate. 
     In other words, in the semiconductor device illustrated in  FIGS. 7 to 9 , the transistor  30  has a trench gate structure. Specifically, a trench  51  is formed to surround the N + -type diffusion region  5   a  which serves as the source region for the transistor  30 . The P-type diffusion region  3   a  includes a first region  3   aa  located outside the trench  51  and a second region  3   ab  located inside the trench  51 . The second region  3   ab  is arranged inside the trench  51  so as to be in contact with the bottom surface of the N + -type diffusion region  5   a . The first region  3   aa  is arranged to be in contact with the bottom surface of the P + -type diffusion region  4   a . The P-type diffusion region  6  extends across the bottom surface of the first region  3   aa  to a position on the bottom surface of the second region  3   ab  inside the trench  51 . The N-type diffusion region  2  extends inside the trench  51  across a part  51   a  of the trench  51 . The P-type diffusion region  6  that extends inside the trench  51  across the other part  51   b  of the trench  51  is in contact with the N-type diffusion region  2  inside the trench  51 . In order to ground the second region  3   ab  of the P-type diffusion region  3   a , the P-type diffusion region  6  is in contact with the second region  3   ab  inside the trench  51 . The N-type diffusion region  2  is in contact with the second region  3   ab  of the P-type diffusion region  3   a  inside the trench  51 . An insulating film  15  is formed on the inner wall of the trench  51  as a gate insulating film. A gate electrode  9   a  is formed on the insulating film  15 . A region in the second region  3   ab  that faces the part  51   a  of the trench  51  serves as the channel region for the transistor  30 . The gate electrode  9   a  is formed to fill the inside of the trench  51 . The trench  51  extends from the main surface of the semiconductor layer  1  to a position in the P-type diffusion region  6  or the N-type diffusion region  2  that is further than the bottom surface of the second region  3   ab.    
     A field plate  20  made of a conductive film is arranged on the isolation insulating film  14   c  at a position closer to the trench  51  and a position further away from the trench  51 , respectively. 
     &lt;Effect of Semiconductor Device&gt; 
     In the semiconductor device according to the present embodiment, the main surface of the semiconductor layer  1  is formed with a trench  51 . The part  51   a  of the trench  51  partitions the channel region and the first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ). The insulating film  15 , which serves as a gate insulating film, is formed on the inner wall surface of the part  51   a  of the trench that faces the channel region. The gate electrode  9   a  is formed inside the trench  51 . The trench  51  extends from the main surface of the semiconductor layer  1  to a position further than the bottom surface of the second semiconductor region (the P + -type diffusion region  4   a  and the P-type diffusion region  3   a ). The other part  51   b  of the trench  51  is formed in a region between the back gate electrode  10   a  and the source electrode  10   b . The second semiconductor region (the P-type diffusion region  3   a ) includes a first region  3   aa  and a second region  3   ab . The first region  3   aa  is located closer to the back gate electrode  10   a  than the other part  51   b  of the trench  51 . The second region  3   ab  is located closer to the source electrode  10   b  than the other part  51   b  of the trench  51  and includes a channel region. The first semiconductor region (the N-type diffusion region  2 ) extends across a region located below the part  51   a  of the trench  51  so as to be in contact with the channel region. The semiconductor device further includes an extending region (P-type diffusion region  6 ) of the first conductivity type (P-type). The P-type diffusion region  6  is formed in the semiconductor layer  1  as an extending region so as to be in contact with the first region  3   aa  and the second region  3   ab . The P-type diffusion region  6  extends from the bottom surface of the first region  3   aa  across a region located below the other part  51   b  of the trench  51  to the bottom surface of the second region  3   ab.    
     Thus, the adoption of a so-called trench gate structure using the trench  51  makes it possible to improve the breakdown voltage between the source electrode  10   b  and the back gate electrode  10   a , which makes it possible to make the breakdown voltage between the source electrode  10   b  and the back gate electrode  10   a  greater than the power supply voltage (Vcc). 
     In the semiconductor device, the trench  51  may be formed on the main surface of the semiconductor layer  1  and arranged to surround the third semiconductor region (the N + -type diffusion region  5   a ). Therefore, the N + -type diffusion region  5   a  to which the source electrode  10   b  is connected may be separated from the surrounding region, which makes it possible to arrange an element that functions differently from the bootstrap circuit in the region where the high breakdown voltage NchMOS transistor  30  is formed. 
     In the structure of the semiconductor device described in the first embodiment, an N-type diffusion layer  21  is formed so as to improve the breakdown voltage between the source region and the back gate. In this case, in order to prevent the breakdown voltage from decreasing due to the electric field concentration at a corner portion of the N-type diffusion layer  21 , it is generally necessary to introduce a deeper diffusion layer or to reduce the concentration of the P-type diffusion region  3   a  electrically connected to the back gate. These measures may increase the current gain of the parasitic NPN transistor unless the structure is properly designed, which lowers the reliability of the semiconductor device. 
     Therefore, in the present embodiment, in order to improve the breakdown voltage between the source and the back gate, an N + -type diffusion region  5   a  serving as the source region is formed inside the trench  51  of the trench gate structure. As a result, the corner portion of the N-type diffusion layer  21  as illustrated in  FIG. 2  is eliminated, which makes it possible to prevent the breakdown voltage from being reduced by the electric field concentration. Further, as illustrated in  FIG. 8 , the junction between the source and the back gate is mainly a one-dimensional junction between the lower portion of the N + -type diffusion region  5   a  located inside the trench  51  and the upper portion of the second region  3   ab  in the P-type diffusion region. Further, the gate electrode  9   a  inside the trench  51  serves as a field plate to extend the depletion layer, thereby reducing the electric field. Therefore, the breakdown voltage is improved in the region in contact with the trench  51 . Therefore, the breakdown voltage between the source and the back gate is not determined by the boundary such as the end portion of the N-type diffusion layer  21  as illustrated in  FIG. 2 . As a result, it is possible to improve the breakdown voltage of the semiconductor device and make the breakdown voltage stable. 
     Fourth Embodiment 
     &lt;Configuration of Semiconductor Device&gt; 
       FIG. 10  is a schematic plan view illustrating a part of a semiconductor device according to a fourth embodiment,  FIG. 11  is a schematic sectional view taken along line XI-XI in  FIG. 10 , and  FIG. 12  is a schematic sectional view taken along line XII-XII of  FIG. 10 . The semiconductor device illustrated in  FIGS. 10 to 12  basically has the same configuration as the semiconductor device illustrated in  FIGS. 7 to 9  except that the structure of the P-type diffusion region  3   a  is different from that of the semiconductor device illustrated in  FIGS. 7 to 9 . In other words, in the semiconductor device illustrated in  FIGS. 10 to 12 , a part of the P-type diffusion region  3   a  extends from the trench  51  to the isolation insulating film  14   c . The P-type diffusion region  3   a  includes a first region  3   aa  located below the P + -type diffusion region  4   a , a second region  3   ab  located below the N + -type diffusion region  5   a  and inside the trench  51 , a third region  3   ac  extending from the trench  51  to the isolation insulating film  14   c , and a fourth region  3   ad  which is located around the trench  51  and connects the first region  3   aa  and the third region  3   ac . As illustrated in  FIG. 10 , a plurality of trenches  51  are formed along the boundary between the P-type diffusion region  3   a  and the N-type diffusion region  2  and separated from each other. The fourth region  3   ad  is arranged between the plurality of trenches  51 . The third region  3   ac  is in contact with the N-type diffusion region  2 . The third region  3   ac  extends from the surface of the trench  51  to the isolation insulating film  14   c.    
     &lt;Effect of Semiconductor Device&gt; 
     In the semiconductor device according to the present embodiment, the second semiconductor region (the P + -type diffusion region  4   a  and the P-type diffusion region  3   a ) further includes a third region  3   ac  and a fourth region  3   ad . The third region  3   ac  is located at the other side of the part  51   a  of the trench  51  relative to the second region  3   ab . The fourth region  3   ad  is located outside the trench  51  and connects the first region  3   aa  and the third region  3   ac.    
     Since the first region  3   aa  and the third region  3   ac  are connected by the fourth region  3   ad , as a result the third region  3   ac  is grounded. Therefore, the depletion of the N-type diffusion region  2  adjacent to the third region  3   ac  is promoted, which makes it possible to improve the breakdown voltage and the stability of the semiconductor device. 
     Fifth Embodiment 
     &lt;Configuration of Semiconductor Device&gt; 
       FIG. 13  is a circuit diagram illustrating a potential detection circuit in a semiconductor device according to a fifth embodiment.  FIG. 14  is a schematic plan view illustrating a part of a semiconductor device on which the circuit illustrated in  FIG. 13  is mounted.  FIG. 15  is a schematic sectional view taken along line XV-XV in  FIG. 14 .  FIG. 16  is a schematic sectional view taken along line XVI-XVI in  FIG. 14 .  FIG. 17  is a schematic sectional view taken along line XVII-XVII in  FIG. 14 .  FIG. 18  is a schematic sectional view taken along line XVIII-XVIII in  FIG. 14 . 
     The semiconductor device illustrated in  FIGS. 13 to 18  basically has the same configuration as the semiconductor device illustrated in  FIGS. 1 and 2  except in that it includes a determination circuit  80  for determining the potential of the first node  71  connected to the first electrode of the bootstrap capacitor  39 . The determination circuit  80  mainly includes a first charging circuit  81 , a second charging circuit  82 , a first switch element  83 , a second switch element  84 , a third switch element  85 , a comparator  62 , and a gate control circuit  61 . The first charging circuit  81  includes a first capacitor  81   a , a first charging node  81   b , a first resistor  81   c , and a first diode  81   d . The first capacitor  81   a  has two electrodes. One electrode of the first capacitor  81   a  is grounded, and the other electrode of the first capacitor  81   a  is electrically connected to the first charging node  81   b . The first diode  81   d  is connected in parallel with the first capacitor  81   a.    
     The second charging circuit  82  includes a second capacitor  82   a , a second charging node  82   b , a second resistor  82   c , and a second diode  82   d . The second capacitor  82   a  has two electrodes. One electrode of the second capacitor  82   a  is grounded, and the other electrode of the second capacitor  82   a  is electrically connected to the second charging node  82   b . The second diode  82   d  is connected in parallel with the second capacitor  82   a.    
     The source of the first switch element  83  is connected to the seventh node  77 , from which the power supply voltage (Vcc) is supplied. The drain of the first switch element  83  is connected to the first charging node  81   b . The first charging node  81   b  is connected to the comparator  62 . 
     The source of the second switch element  84  is connected to the seventh node  77 , from which the power supply voltage (Vcc) is supplied. The drain of the second switch element  84  is connected to the second charging node  82   b . The second charging node  82   b  is connected to the comparator  62 . The second charging node  82   b  is also connected to the source of the third switch element  85 . The drain of the third switch element  85  is connected to the first node  71 . The drain of the transistor  30  is connected to the first node  71 . The source of the transistor  30  is connected to the seventh node  77 . The gate electrode of the transistor  30 , the gate electrode of the first switch element  83 , the gate electrode of the second switch element  84 , and the gate electrode of the third switch element  85  are connected to the gate control circuit  61 . The output of the comparator  62  is input to the gate control circuit  61 . 
     The power supply voltage (Vcc) is supplied to the first charging node  81   b  via the first switch element  83 . The power supply voltage (Vcc) is supplied to the second charging node  82   b  via the second switch element  84 . The first capacitor  81   a  and the second capacitor  82   a  have the same capacitance. The second charging node  82   b  is connected to the first node  71  via the third switch element  85 . When the voltage of the second charging node  82   b  is greater than the voltage of the first charging node  81   b , the determination circuit  80  determines that the voltage of the first node  71  is greater than the power supply voltage (Vcc). 
       FIG. 14  illustrates a planar layout of the semiconductor device in which the circuit illustrated in  FIG. 13  is mounted.  FIG. 14  illustrates the planar shapes of an electrode layer serving as the gate electrode of the transistor  30 , the first switch element  83 , the second switch element  84  and the third switch element  85 , and the N + -type diffusion regions  5   a ,  5   f , and  5   g  serving as the source region or the drain region. The transistor  30  and the like are arranged along a boundary between the N-type diffusion region  2  and the P-type diffusion region  3   a . Specifically, an N + -type diffusion region  5   a  is formed on the surface of the P-type diffusion region  3   a  so as to extend along the boundary. An N + -type diffusion region  5   f  is formed on the surface of the P-type diffusion region  3   a  at a position separated from the N + -type diffusion region  5   a  along the boundary. The N + -type diffusion region  5   f  extends in a direction away from the boundary. An N + -type diffusion region  5   g  is formed on the surface of the P-type diffusion region  3   a  at a position separated from the N + -type diffusion region  5   f  along the boundary. The N + -type diffusion region  5   g  extends in a direction away from the boundary. In other words, the N + -type diffusion region  5   f  and the N + -type diffusion region  5   g  are formed so as to extend substantially parallel to each other. The N + -type diffusion region  5   a  is formed on the surface of the P-type diffusion region  3   a  at a position separated from the N + -type diffusion region  5   g  along the boundary. The N + -type diffusion region  5   a  extends along the boundary. 
     A gate electrode  9   g  is formed to extend from a position adjacent to the N + -type diffusion region  5   a  across the surface of the P-type diffusion region  3   a  to the N-type diffusion region  2 . An insulating film  15  is disposed below the gate electrode  9   g  as a gate insulating film. A first electrode layer  9   e  is formed to be separated from the gate electrode  9   g  along the boundary. An insulating film  15  is formed below the first electrode layer  9   e  as a gate insulating film. The first electrode layer  9   e  is arranged adjacent to the N + -type diffusion region  5   a  and configured to cover a part of the N + -type diffusion region  5   f . The first electrode layer  9   e  extends from the P-type diffusion region  3   a  across the boundary to the N-type diffusion region  2 . 
     A second electrode layer  9   f  is formed so as to be separated from the first electrode layer  9   e  along the boundary. An insulating film  15  is formed below the second electrode layer  9   f  as a gate insulating film. The second electrode layer  9   f  is arranged adjacent to the other N + -type diffusion region  5   a  and configured to cover a part of the N + -type diffusion region  5   g . The second electrode layer  9   f  is formed only on the P-type diffusion region  3   a . The second electrode layer  9   f  is arranged at a position separated from the boundary. A gate electrode  9   h  is formed to extend from a position adjacent to the other N + -type diffusion region  5   a  across the surface of the P-type diffusion region  3   a  to the N-type diffusion region  2 . An insulating film  15  is disposed below the gate electrode  9   h  as a gate insulating film. 
     As illustrated in  FIG. 14 , the gate electrode  9   g  of the transistor  30  is disposed between the N + -type diffusion region  5   a  and the N-type diffusion region  2 . A portion of the first electrode layer  9   e  located between the N + -type diffusion region  5   a  and the N-type diffusion region  2  serves as a gate electrode of the transistor  30 . A portion of the first electrode layer  9   e  located between the N + -type diffusion region  5   a  and the N + -type diffusion region  5   f  serves as a gate electrode of the second switch element  84 . A portion of the first electrode layer  9   e  located between the N + -type diffusion region  5   f  and the N-type diffusion region  2  serves as a gate electrode of the third switch element  85 . A portion of the second electrode layer  9   f  located between the other N + -type diffusion region  5   a  and the N + -type diffusion region  5   g  serves as a gate electrode of the first switch element  83 . The gate electrode  9   g  of the transistor  30  is arranged between the other N + -type diffusion region  5   a  and the N-type diffusion region  2 . 
     &lt;Effect of Semiconductor Device&gt; 
     The semiconductor device according to the present embodiment includes a determination circuit  80 . The determination circuit  80  determines whether or not the voltage of the first node  71  on the current path between the first electrode of the bootstrap capacitor  39  and the first semiconductor region (the N + -type diffusion region  5   b  and the N-type diffusion region  2 ) is greater than the power supply voltage (Vcc). The determination circuit  80  includes a first charging circuit  81 , a second charging circuit  82 , a first switch element  83 , a second switch element  84 , and a third switch element  85 . The first charging circuit  81  includes a first capacitor  81   a  and a first charging node  81   b . The first capacitor  81   a  has two electrodes. One electrode of the first capacitor  81   a  is grounded. The other electrode of the first capacitor  81   a  is electrically connected to the first charging node  81   b.    
     The second charging circuit  82  includes a second capacitor  82   a  and a second charging node  82   b . The second capacitor  82   a  has two electrodes. One electrode of the second capacitor  82   a  is grounded. The other electrode of the second capacitor  82   a  is electrically connected to the second charging node  82   b . The first charging node  81   b  is supplied with the power supply voltage (Vcc) via the first switch element  83 . The second charging node  82   b  is supplied with the power supply voltage (Vcc) via the second switch element  84 . The first capacitor  81   a  and the second capacitor  82   a  have the same capacitance. The second charging node  82   b  is connected to the first node  71  via the third switch element  85 . When the voltage of the second charging node  82   b  is greater than the voltage of the first charging node  81   b , the determination circuit  80  determines that the voltage of the first node  71  is greater than the power supply voltage (Vcc). 
     Since the determination circuit  80  may determine whether or not the voltage of the first node  71  is greater than the power supply voltage, it is possible to perform or terminate the charging operation on the bootstrap capacitor  39  based on the determination result. 
     In the bootstrap charging system included in the semiconductor device according to each of the embodiments described above, it is desirable to reliably terminate the charging operation on the bootstrap capacitor  39  when the potential (VB) of the first node  71  is greater than the potential (VS) of the third node  73  or the power supply voltage (Vcc). To this end, it is desirable that the potential (VB) of the first node  71  may be indirectly monitored on the low potential side. 
     In the determination circuit  80  illustrated in  FIG. 13 , two switch elements having the same characteristics are used respectively as the first switch element  83  and the second switch element  84 , two resistors having the same resistance value are used respectively as the first resistor  81   c  and the second resistor  82   c , two elements having the same capacitance value are used respectively as the first capacitor  81   a  and the second capacitor  82   a , and two diodes having the same characteristics are used respectively as the first diode  81   d  and the second diode  82   d  so as to constitute two charging circuits. The first charging node  81   b  and the second charging node  82   b  are connected to the comparator  62  so as to monitor the voltage of the first charging node  81   b  and the voltage of the second charging node  82   b . As illustrated in  FIG. 13 , the second charging node  82   b  is connected to the source of the third switch element  85  which is a high breakdown voltage MOST transistor similar to the transistor  30 . The drain of the third switch element  85  is connected to the first node  71 . On the other hand, in the first charging node  81   b , as illustrated in the cross-sectional view of  FIG. 17 , a gap is formed between the second electrode layer  9   f  and the first electrode layer  9   e  so as to prevent the surface layer of the P-type diffusion region  3   a  below the second electrode layer  9   f  which serves as the gate electrode of the high breakdown voltage NchMOS transistor from becoming a channel. The source of the first switch element  83  and the source of the second switch element  84  are supplied with the power supply voltage (Vcc), and controlled by the gate control circuit  61 . 
     When the gate of the first switch element  83  and the gate of the second switch element  84  are turned on, the currents flow through the first switch element  83  and the second switch element  84 , and the first resistor  81   c  and the second resistor  82   c  to charge the first capacitor  81   a  and the second capacitor  82   a , respectively. At this time, the third switch element  85  on the side of the second switch element  84  is also turned on. Therefore, if the potential (VB) of the first node  71  becomes lower than the power supply voltage (Vcc), a part of the current of the second switch element  84  flows through the third switch element  85  toward the first node  71 . As a result, the current flowing through the second resistor  82   c  becomes smaller than the current flowing through the first resistor  81   c , and thereby, the potential (V 1 ) of the first charging node  81   b  is greater than the potential (V 2 ) of the second charging node  82   b.    
     When the potential (VB) of the first node  71  is greater than the power supply voltage (Vcc) and the potential (V 2 ) of the second charging node  82   b  is lower than the power supply voltage (Vcc), the currents from both the second switch element  84  and the third switch element  85  flow through the second resistor  82   c . In this case, the potential (V 1 ) of the first charging node  81   b  is smaller than the potential (V 2 ) of the second charging node  82   b . Since the potential (V 1 ) of the first charging node  81   b  is equal to or lower than the power supply voltage (Vcc), even if the potential (V 2 ) of the second charging node  82   b  becomes greater than the power supply voltage (Vcc), the potential (V 1 ) of the first charging node  81   b  is lower than the potential (V 2 ) of the second charging node  82   b.    
     By comparing the potential (V 1 ) of the first charging node  81   b  and the potential (V 2 ) of the second charging node  82   b  using the comparator  62 , it is possible to determine that the potential (VB) of the first node  71  becomes equal to or greater than the power supply voltage (Vcc). The determination result is fed back to the gate control circuit  61 , the gate control circuit  61  turns off the gates of the first switch element  83 , the second switch element  84  and the third switch element  85 , and thereby, it is possible to terminate the charging operation on the bootstrap capacitor  39  via the first node  71 . In the determination circuit  80 , in order to further improve the determination accuracy, the power supply voltage (Vcc) may be input to the comparator  62  as a reference of the potential (V 1 ) of the first charging node  81   b  and the potential (V 2 ) of the second charging node  82   b.    
     Sixth Embodiment 
     &lt;Configuration of Semiconductor Device&gt; 
       FIG. 19  is a schematic plan view illustrating a part of a semiconductor device according to a sixth embodiment,  FIG. 20  is a schematic sectional view taken along line XX-XX of  FIG. 19 ,  FIG. 21  is a schematic sectional view taken along line XXI-XXI in  FIG. 19 , and  FIG. 22  is a schematic sectional view taken along line XXII-XXII in FIG.  19 . 
     The semiconductor devices illustrated in  FIGS. 19 to 22  basically have the same configuration as the semiconductor layers illustrated in  FIGS. 13 to 18  except that the planar shapes of the N + -type diffusion regions  5   h ,  5   i  and  5   j , the first electrode layer  9   e  and the second electrode layer  9   f  constituting each switch element and the like are different from those in the semiconductor device illustrated in  FIGS. 13 to 18 . 
     Similar to  FIG. 14 ,  FIG. 19  illustrates the planar shapes of an electrode layer serving as the gate electrode of the transistor  30 , the first switch element  83 , the second switch element  84  and the third switch element  85 , and the N + -type diffusion regions  5   a ,  5   h ,  5   i ,  5   j  and  5   k  serving as the source region or the drain region. Specifically, an N + -type diffusion region  5   a  is formed on the surface of the P-type diffusion region  3   a  so as to extend along a boundary between the N-type diffusion region  2  and the P-type diffusion region  3   a . An N + -type diffusion region  5   h  is formed on the surface of the P-type diffusion region  3   a  at a position separated from the N + -type diffusion region  5   a  along the boundary. The N + -type diffusion region  5   h  includes a first portion  5   ha  extending along the boundary and a second portion  5   hb  contiguous with the first portion  5   ha  and extending in a direction away from the boundary. An N + -type diffusion region  5   j  is formed in a region located at the other side of the boundary relative to the first portion  5   ha.    
     An N + -type diffusion region  5   i  is formed on the surface of the P-type diffusion region  3   a  at a position separated from the N + -type diffusion region  5   h  along the boundary. The N + -type diffusion region  5   i  includes a first portion  5   ia  extending along the boundary and a second portion  5   ib  contiguous with the first portion  5   ia  and extending in a direction away from the boundary. An N + -type diffusion region  5   k  is formed in a region at the other side of the boundary relative to the first portion  5   ia. The planar shape of the N   + -type diffusion region  5   h  and the planar shape of the N + -type diffusion region  5   j  are line-symmetrical about a center line located between the second portion  5   hb  and the second portion  5   ib  and extending parallel to the second portion  5   hb , and similarly, the planar shape of the N + -type diffusion region  5   i  and the planar shape of the N + -type diffusion region  5   k  are line-symmetrical about the center line. An N + -type diffusion region  5   a  is formed on the surface of the P-type diffusion region  3   a  at a position separated from the N + -type diffusion region  5   i  along the boundary. The N + -type diffusion region  5   a  extends along the boundary. 
     A gate electrode  9   g  is formed to extend from a position adjacent to the N + -type diffusion region  5   a  across the surface of the P-type diffusion region  3   a  to the N-type diffusion region  2 . An insulating film  15  is disposed below the gate electrode  9   g  as a gate insulating film. A first electrode layer  9   e  is formed to be separated from the gate electrode  9   g  along the boundary. An insulating film  15  is formed below the first electrode layer  9   e  as a gate insulating film. The first electrode layer  9   e  is arranged adjacent to the N + -type diffusion region  5   j  and configured to cover the first portion  5   ha  of the N + -type diffusion region  5   h . The first electrode layer  9   e  extends from the P-type diffusion region  3   a  across the boundary to the N-type diffusion region  2 . In the planar view, the N + -type diffusion region  5   h  is arranged to divide the first electrode layer  9   e  into a first electrode portion  9   ea  on the side of the N + -type diffusion region  5   j  and a second electrode portion  9   eb  on the side of the N-type diffusion region  2 . 
     A second electrode layer  9   f  is formed to be separated from the first electrode layer  9   e  along the boundary. An insulating film  15  is formed below the second electrode layer  9   f  as a gate insulating film. The second electrode layer  9   f  is arranged adjacent to the other N + -type diffusion region  5   a  and configured to cover a part of the N + -type diffusion region  5   g . The second electrode layer  9   f  is formed only on the P-type diffusion region  3   a . The second electrode layer  9   f  is arranged at a position separated from the boundary. A gate electrode  9   g  is formed to extend from a position adjacent to the other N + -type diffusion region  5   a  across the surface of the P-type diffusion region  3   a  to the N-type diffusion region  2 . An insulating film  15  is disposed below the gate electrode  9   g  as a gate insulating film. 
     As illustrated in  FIG. 19 , the gate electrode  9   g  of the transistor  30  is disposed between the N + -type diffusion region  5   a  and the N-type diffusion region  2 . A portion of the first electrode layer  9   e  located between the N + -type diffusion region  5   j  and the first portion  5   ha  of the N + -type diffusion region  5   h  serves as a gate electrode of the second switch element  84 . A portion of the first electrode layer  9   e  located between the first portion  5   ha  of the N + -type diffusion region  5   h  and the N-type diffusion region  2  serves as a gate electrode of the third switch element  85 . A portion of the second electrode layer  9   f  located between the N + -type diffusion region  5   k  and the first portion  5   ia  of the N + -type diffusion region  5   i  serves as a gate electrode of the first switch element  83 . The gate electrode  9   g  of the transistor  30  is arranged between the other N + -type diffusion region  5   a  and the N-type diffusion region  2 . 
     &lt;Effect of Semiconductor Device&gt; 
     The semiconductor device according to the present embodiment includes a fifth semiconductor region of the second conductivity type (the N + -type diffusion region  5   j ), a sixth semiconductor region of the second conductivity type (the N + -type diffusion region  5   h ), a seventh semiconductor region of the second conductivity type (the N + -type diffusion region  5   k ), and an eighth semiconductor region of the second conductivity type (the N + -type diffusion region  5   i ). The fifth semiconductor region (the N + -type diffusion region  5   j ) is formed in the second semiconductor region (the P-type diffusion region  3   a ) and is separated from the third semiconductor region (the N + -type diffusion region  5   a ). The sixth semiconductor region (the N + -type diffusion region  5   h ) is formed in the second semiconductor region (the P-type diffusion region  3   a ) and is separated from the fifth semiconductor region (the N + -type diffusion region  5   j ). The seventh semiconductor region (the N + -type diffusion region  5   k ) is formed in the second semiconductor region (the P-type diffusion region  3   a ) and is separated from the fifth semiconductor region (the N + -type diffusion region  5   j ). The eighth semiconductor region (the N + -type diffusion region  5   i ) is formed in the second semiconductor region (the P-type diffusion region  3   a ) and is separated from the seventh semiconductor region (the N + -type diffusion region  5   k ). The sixth semiconductor region (the N + -type diffusion region  5   h ) includes a first portion  5   ha  which is formed closer to the first semiconductor region (the N-type diffusion region  2 ) than the fifth semiconductor region (the N + -type diffusion region  5   j ) and is separated from the first semiconductor region (the N-type diffusion region  2 ). The semiconductor device further includes a first electrode layer  9   e  and a second electrode layer  9   f . The first electrode layer  9   e  is formed to extend from a position between the fifth semiconductor region (the N + -type diffusion region  5   j ) and the first portion  5   ha  across the first portion  5   ha  to the first semiconductor region (the N-type diffusion region  2 ). The first electrode layer  9   e  is arranged with the first insulating film (the insulating film  15 ) interposed therebetween. The second electrode layer  9   f  is formed to extend from a position between the seventh semiconductor region (the N + -type diffusion region  5   k ) and the eighth semiconductor region (the N + -type diffusion region  5   i ) to the eighth semiconductor region (the N + -type diffusion region  5   i ). The second electrode layer  9   f  is arranged with the second insulating film (the insulating film  15 ) interposed therebetween. The second electrode layer  9   f  is disposed at a position separated from the boundary between the first semiconductor region (the N-type diffusion region  2 ) and the second semiconductor region (the P-type diffusion region  3   a ). In a planar view, the sixth semiconductor region (the N + -type diffusion region  5   h ) is formed so as to divide the first electrode layer  9   e  into a first electrode portion  9   ea  on the side of the fifth semiconductor region (the N + -type diffusion region  5   j ) and a second electrode portion  9   eb  on the side of the first semiconductor region (the N-type diffusion region  2 ). The fifth semiconductor region (the N + -type diffusion region  5   j ) is a source region for the second switch element  84 . The first portion  5   ha  is a drain region for the second switch element  84  and a source region for the third switch element  85 . The first semiconductor region (the N-type diffusion region  2 ) is a drain region for the third switch element  85 . The first electrode portion  9   ea  of the first electrode layer  9   e  is a gate electrode of the second switch element  84 . The second electrode portion  9   eb  of the first electrode layer  9   e  is a gate electrode of the third switch element  85 . The seventh semiconductor region (the N + -type diffusion region  5   k ) is a source region for the first switch element  83 . The eighth semiconductor region (the N + -type diffusion region  5   i ) is a drain region for the first switch element  83 . The second electrode layer  9   f  is a gate electrode of the first switch element  83 . 
     Since the N + -type diffusion region  5   h  is formed to divide the first electrode layer  9   e  into the first electrode portion  9   ea  on the side of the fifth semiconductor region (the N + -type diffusion region  5   j ) and the second electrode portion  9   eb  on the side of the first semiconductor region (the N-type diffusion region  2 ), it is possible to prevent the fifth semiconductor region (the N + -type diffusion region  5   j ) from functioning as the source region for the third switch element  85 . 
     In other words, the N + -type diffusion region  5   h  is configured to surround the N + -type diffusion region  5   j . By adopting this configuration, the N + -type diffusion region  5   j  which serves as the source of the second switch element  84  may be prevented from functioning as the source of the third switch element  85  as much as possible. Similarly to the semiconductor device illustrated in  FIG. 14 , the second electrode layer  9   f  is separated from the first electrode layer  9   e  so that the high breakdown voltage NchMOS transistor does not operate between the first portion  5   ia  of the N + -type diffusion region  5   i  and the N-type diffusion region  2 . By adopting this configuration, it is possible to prevent the current from being generated by the parasitic MOS structure not shown in the circuit diagram. As a result, it is possible for the determination circuit  80  to stably output a signal voltage for detecting the potential (VB) of the first node  71 , preventing the malfunction of the determination circuit  80 . 
     Seventh Embodiment 
     &lt;Configuration of Semiconductor Device&gt; 
       FIG. 23  is a circuit diagram illustrating a potential detection circuit in the semiconductor device according to the seventh embodiment. The semiconductor device illustrated in  FIG. 23  basically has the same configuration as the semiconductor device illustrated in  FIG. 13  except that the configuration of the first charging circuit  81  and the configuration of the second charging circuit  82  in the determination circuit  80  are different from those in the semiconductor device illustrated in  FIG. 13 . In other words, in the semiconductor device illustrated in  FIG. 23 , the first charging circuit  81  includes a fourth switch element  81   e , and the second charging circuit  82  includes a fifth switch element  82   e . The fourth switch element  81   e  is connected in parallel to the first capacitor  81   a . The fifth switch element  82   e  is connected in parallel to the second capacitor  82   a.    
     &lt;Effect of Semiconductor Device&gt; 
     The semiconductor device according to the present embodiment includes a fourth switch element  81   e  and a fifth switch element  82   e . The fourth switch element  81   e  is connected in parallel to the first capacitor  81   a . The fifth switch element  82   e  is connected in parallel to the second capacitor  82   a . When the first switch element  83  and the second switch element  84  are turned off, the fourth switch element  81   e  and the fifth switch element  82   e  are turned on, and the first capacitor  81   a  and the second capacitor  82   a  are discharged. 
     Thus, by controlling the fourth switch element  81   e  and the fifth switch element  82   e , it is possible to reliably discharge the first capacitor  81   a  of the first charging circuit  81  and the second capacitor  82   a  of the second charging circuit  82  and reset the same to the initial state. 
     In the determination circuit  80  of the semiconductor device illustrated in  FIG. 13 , the state of the first capacitor  81   a  and the state of the second capacitor  82   a  are subjected to the influence of the discharge immediately after the completion of the previous charge or the subsequent discharge. Therefore, the initial state of the first capacitor  81   a  and the initial state of the second capacitor  82   a  at each charging operation may be different. Therefore, contrary to the circuit operation assumed in the semiconductor device illustrated in  FIG. 13 , for example, when the potential (V 2 ) of the second charging node  82   b  is greater than the potential (V 1 ) of the first charging node  81   b  in the initial state, the potential (VB) of the first node  71  may be immediately determined as being greater than the power supply voltage (Vcc), which may terminate the charging operation. 
     Therefore, if the first charging circuit  81  includes the fourth switch element  81   e  and the second charging circuit  82  includes the fifth switch element  82   e  as in the semiconductor device illustrated in  FIG. 23 , it is possible to stabilize the voltage (VC 1 ) of the first capacitor  81   a  and the voltage (VC 2 ) of the second capacitor  82   a  in the determination circuit  80 , which makes the operation of the determination circuit  80  stable. For example, while the gate of the first switch element  83  and the gate of the second switch element  84  are being turned off so as to perform the charging operation, the gate of the fourth switch element  81   e  and the gate of the fifth switch element  82   e  are turned on. In this way, it is possible to release the residual charges of the first capacitor  81   a  and the second capacitor  82   a  so as to reset the capacitors to the initial state, preventing the malfunction of the determination circuit  80 . 
     It should be understood that the embodiments disclosed herein have been presented for the purpose of illustration and description but not limited in all aspects. It is intended that the scope of the present disclosure is not limited to the description above but defined by the scope of the claims and encompasses all modifications equivalent in meaning and scope to the claims.