Patent Publication Number: US-7902585-B2

Title: Linear variable voltage diode capacitor and adaptive matching networks

Description:
PRIORITY CLAIM AND REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. §119 from pending provisional application Ser. No. 60/688,644, filed Jun. 8, 2005. 
    
    
     FIELD 
     The invention is the field of electronics and semiconductor circuits. An example application of the invention is to high frequency electronic circuits, e.g., radio frequency circuits such as cellular handset circuits. Other example applications of the invention are to tunable filters, dynamic tuners for power amplifiers, switches, and voltage controlled oscillators. 
     BACKGROUND 
     Diode capacitors are used in a wide range of circuits. Nonlinear response to a variable voltage condition limits the usefulness of diode capacitors in certain applications. The nonlinearity may have to be addressed with supplemental circuitry in some cases. In other cases, the nonlinearity may limit the operational range of the circuit. 
     As an example, voltage variable (or tunable) diode capacitors are used extensively in high-frequency electronic design applications. Cellular handset circuits, for example, use voltage variable diode capacitors in voltage controlled oscillators that are used for tuning. Voltage variable diode capacitors are used in a wide variety of additional circuits, including, for example, tunable filters and high-frequency switches. Their utility and performance are compromised as the capacitance of the diodes used to construct the variable voltage capacitors varies nonlinearly with the voltage applied to the capacitor. With higher signal levels, the nonlinearity creates inter-modulation and cross-modulation distortion. Such distortion can limit circuit performance. 
     In R. G. Meyer and M. Stephens “Distortion in Variable Capacitance Diodes,” IEEE J. of Solid-State Circuits, vol. SC-10, no. 1, 1975, variable capacitor diodes are discussed. The paper discusses the anti-parallel connection of two varactor (voltage variable reactance) diodes to realize a composite voltage variable capacitor with improved linearity. In a special case referred to as the abrupt junction case, nonlinearities are cancelled, and the resulting configuration is almost perfectly linear. However, nonlinearity cancellation is less effective outside of the abrupt junction special case, minimizing the general utility of the technique. The abrupt junction case requires maintenance of a large dc bias voltage range to realize a large capacitance variation. 
     Variable diode capacitors are used in RF and microwave circuits, for example. Such circuits also use matching networks. Reducing loss with adaptive matching networks holds promise for the further advancement of RF and microwave circuits. For example, low loss adaptive matching networks can be used to tune the matching conditions for power amplifiers to dynamically optimize the load impedance, in order to provide the best performance at varying output powers and antenna conditions. Other example uses of adaptive passive networks are for tunable filters, multi-band radios, and reconfigurable RF systems. 
     Typical variable capacitance circuits use varactor diodes for tuning. Applications of these circuits include voltage controlled oscillators, tunable filters, switches, phase shifters and tunable impedance matching networks. Achieving low-distortion in these circuits is highly desirable—especially for large-signal applications like power amplifiers. 
     Some alternative strategies for variable capacitance circuits are being researched. One example are capacitors based upon microelectromechanical systems (MEMS). MEMS capacitors provide a very high Quality Factor (Q) and extraordinarily high linearity, but require non-standard processing and packaging techniques, and high control voltages. Additionally, and their reliability and switching speed are still poor compared to semiconductor-based solutions. Other proposed tuning techniques, based on voltage-variable dielectrics, exhibit similar drawbacks of manufacturability and performance. 
     In view of such integration issues, varactor diodes seem a logical choice for implementing RF adaptivity. However, their inherently nonlinear behavior disqualifies them for use with modern communication standards characterized by high peak-to-average power ratios, and their related Q factors are usually too low at the microwave frequencies of interest for the most demanding applications. 
     In particular, next-generation wireless systems, such as multi-mode transceivers and “cognitive radios,” require circuit techniques that facilitate RF adaptivity. Some examples of adaptive circuits include tunable filters, tunable matching networks for low-noise and power amplifiers, and multi-band VCO&#39;s. An ideal tuning element for these applications will exhibit extremely low loss, low dc power consumption, high linearity, ruggedness to high voltage and high current, wide tuning range, high reliability, very low cost, low area usage, and be continuously tunable, with a high tuning speed. 
     PIN Diodes or GaAs pseudomorphic high electron mobility transistors (PHEMTs) are commonly used today for these challenging applications. However, these solutions are considered to be too expensive, or to consume too much dc power, to be an acceptable long term solution for cost and performance sensitive applications. 
     SUMMARY OF INVENTION 
     The invention provides a highly linear voltage variable diode capacitor. A preferred embodiment includes a plurality of varactor diodes. There are anti-series and anti-parallel connections of the varactor diodes. The varactor diodes are sized and the connections are arranged to minimize second and third-order distortion. In a preferred embodiment of the invention, four nonlinear voltage variable reactance (varactor) diodes are arranged such that the resulting variable capacitor can be made almost perfectly linear, even though the four diodes that comprise it are themselves highly nonlinear. The only requirement on the four varactor diodes is that their capacitance nonlinearity be known a priori, and that the nonlinearity satisfy a certain minimum exponential relationship to the applied voltage. Embodiments of the invention provide a linear voltage variable diode capacitor with a high-tuning range, a high Quality factor, and high linearity. 
     An preferred embodiment integrated variable voltage diode capacitor topology applied to a circuit providing a variable voltage load for controlling variable capacitance. The topology includes a first pair of anti-series varactor diodes ( 10 ,  12 ,  14 ,  16 ), wherein the diode power-law exponent n for the first pair of anti-series varactor diodes in the circuit is equal or greater than 0.5, and the first pair of anti-series varactor diodes have an unequal size ratio that is set to control third-order distortion. The topology also includes a center tap between the first pair anti-series varactor diodes for application of the variable voltage load. In preferred embodiments, a second pair of anti-series varactor diodes is arranged anti-parallel to the first pair of anti-series varactor diodes so the combination of the first pair of anti-series varactor diodes and the second pair of anti-series varactor diodes control second-order distortion as well. 
     In embodiments of the invention, a low distortion varactor is applied to low-loss, silicon-on-glass technology, which can be used, for example, for the implementation of integrated tuners for adaptive matching. Close-to-ideal continuously variable tuning capabilities make these networks suitable for providing optimum loading conditions an RF circuit output stage, for example, under varying output power or antenna matching conditions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  respectively show an anti-series, and anti-series/anti-parallel circuit topology used in embodiments of the invention; 
         FIGS. 2A and 2B  respectively illustrate the capacitances associated with the varactor diodes in the  FIG. 1A  and  FIG. 1B  circuit topologies; 
         FIG. 3  illustrate an anti-parallel diode bias configuration applied to the  FIG. 1A  topology; 
         FIG. 4  shows simulated IP3(V) for a single varactor and a voltage driven DFVS under a two-tone test as function of the tone spacing and center tap impedance; 
         FIG. 5A  plots the resulting breakdown voltage for a uniformly doped silicon varactor device, as function of doping concentration; 
         FIG. 5B  plots effective single varactor diode capacitance tuning ratio (c ratio ) for silicon (solid lines) and GaAs (dashed lines) based varactor diodes at different RF voltage amplitudes as function of doping; 
         FIG. 6  illustrates a circuit topology with multi-varactor stacks in series to lower the RF voltage per diode and consequently improve the voltage handling and tuning range capabilities; 
         FIG. 7  shows calculated capacitance tuning ratio for the uniformly doped multi-stacked DFVS configuration, featuring 2, 4 and 8 anti-series diodes, (N d =2×10 16  and N d =4×10 16 ) as function of applied RF voltage; 
         FIG. 8  shows simulated IP3(V) for a single reversed diode, and (multi)-DFVS varactor configurations, featuring 2, 4 and 8 anti-series diodes, as function of the tone spacing and center tap impedance (f c =1 GHz, C 0 eff =10 pF, V center tap =5V, n=0.5, C D =0.1 pF); 
         FIG. 9A  shows a cross section of a silicon-on-glass varactor device integration of the invention; 
         FIG. 9B  shows the layout of an experimental device in accordance with  FIG. 9A ; 
         FIG. 10  plots the measured and simulated IM3 &amp; IM5 components as function of power for different tone-spacing (Δf=100 kHz and Δf=10 MHz) of an experimental device using a center-tap impedance of 47 kΩ and a center-tap bias of 2V; 
         FIG. 11  shows an experimental band pass filter and  FIG. 12  shows its response; 
         FIG. 13  is a schematic diagram of an experimental varactor diode-based tuner designed for a load impedance of 50Ω; 
         FIG. 14A  shows the measured values of s 11  at 2 GHz for the experimental tuner in accordance with  FIG. 13 ; and 
         FIG. 14B  plots the measured loss contours (Gp in dB) at all the different tuning points, the losses range from 0.5 dB at 1Ω to 3.5 dB for Z in =40Ω for the experimental tuner in accordance with  FIG. 13 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention provides a linear variable voltage diode capacitor varactor diode-based circuit having, in preferred embodiments, substantially no second or third order distortion. Integrated circuit topologies of the invention and a high performance varactor diode process technology are provided. For a given diode power-law capacitance coefficient (n≧0.5), varactor diode based circuits of the invention can act as variable capacitors with extremely low or, in the special case of n=0.5, theoretically no distortion when the ratio of nonidentical diode areas in an anti-series configuration is properly set. 
     Ultra-low distortion varactor topologies of the invention will have many applications, including for RF adaptivity in next generation wireless applications. Example application circuits have been fabricated and tested; including a substantially distortion free varactor stack (DFVS), providing theoretically no distortion, and a high tuning range varactor stack (HTRVS), which provides a higher tuning range with only a very small amount of nonlinear distortion. Center tap loading by the control voltage circuitry is addressed by providing a sufficiently high AC impedance to avoid linearity degradation for signals with low-tone spacing. In the preferred embodiment of the anti-series varactor diode variable capacitors, an anti-parallel diode bias pair in the center tap connection is used to minimize or eliminate linearity degradation. 
     In other embodiments, the use of multiple stacked anti-series varactors improves voltage handling and capacitance tuning range when dealing with large RF signals. Linearity is improved for a given center tap impedance. 
     A preferred embodiment of varactor-based topologies use silicon-on-glass integration. In preferred embodiments, both sides of an intrinsic varactor are contacted by low-ohmic thick-metal contacts, and extremely high Q&#39;s can be obtained even for very large capacitance values. The high performance of these structures in terms of low losses, linearity, tuning range, speed, and low cost, makes them suitable for many applications, including, e.g., the implementation of tunable filters, switches and adaptive matching networks. 
     Preferred example embodiment tuners have a close-to-ideal continuously variable tuning capability, making them very suitable for providing optimum loading conditions to a power amplifier output stage, under varying output power or antenna matching conditions. Experimental embodiments achieved high performance of the filter and tuner networks in terms of loss, size, cost, tuning range, power handling and linearity, and are compatible with current requirements in modern communication systems. A contemplated application is to provide true RF adaptivity, which can dramatically improve the performance of wireless systems. 
     Preferred embodiment diode based variable capacitors of the invention are formed in silicon, and a preferred embodiment is a silicon on glass fabrication. Embodiments of the invention provide a linear variable voltage diode capacitor varactor diode-based circuit formed by a silicon-based process technology having a quality factor (Q) in a range from about 100 to over 500 at 2 GHz with capacitance values up to 50 pF, and with extremely low parasitic capacitances. However, other material systems can be used, including Group III-V material systems. 
     Preferred embodiments will be discussed with respect to the drawings. Operational and design theory for preferred embodiments will also be presented along with data relating to experimental embodiments. The invention is not limited by the operational and design theory, or the experimental data, but artisans will appreciate broader aspects of the invention and additional embodiments from the discussion thereof. 
       FIGS. 1A and 1B  schematically illustrate preferred general topologies for a variable voltage varactor diode capacitor of the invention. The  FIG. 1A  topology is an anti-series connection of two varactor diodes  10  (D A ) and  12  (D B ) to minimize third-order distortion. The ratio of the areas of D A  and D B  determines the value of capacitance C 2  that is provided, which can be set to zero for n≧0.5. The  FIG. 1B  topology shows anti-series/anti-parallel connection of varactor diodes  10 ,  12 ,  14 ,  16  to minimize second and third-order distortion. In this case, both capacitances provided C 1  and C 2  can be set to zero.  FIGS. 2A and 2B  respectively illustrate the capacitances associated with the varactor diodes in the  FIG. 1A  and  FIG. 1B  circuit topologies. 
     Cancellation can only occur for cases where the diode power-law exponent n is greater than 0.5. This can be achieved by a number of fabrication techniques. A constant doping profile in the diode (the so-called “abrupt junction” case) results in an n=0.5 and the resulting ideal value of s is unity. 
     In cases where n&gt;0.5 a method is provided to directly calculate the required diode area ratio to minimize C 2 . As examples, in the case where n=1, the required area ratio is exactly two. In the case of n=2 the ideal hyper-abrupt junction diode—the required area ratio is 2.6. These values are straightforward to realize with high accuracy in any standard integrated circuit process that includes varactor diodes. 
     From equation (21) below, it is also clear that choosing a value of s≠1 in order to null C 2  will result in a finite value of C 1  and a potential for third-order distortion through second-order interaction. This interaction can be eliminated through placing the identical diodes in anti-parallel configuration, as shown in  FIG. 1B . The linear capacitance of  FIGS. 1A and 1B  are the same, but the circuit of  FIG. 1B  can have C 1 =0. 
     With reference to  FIGS. 1B and 2B , the nonlinear capacitance terms in a varactor diode circuit can be set to zero for any value of diode capacitance power exponent n≧0.5 and by setting the ratio of the diode areas using equation (23) below. Operational theory, design, and experimental data will now be discussed to illustrate preferred embodiments of the invention, and to provide artisans with information to practice the preferred embodiments and variations thereof that are within the scope of the invention. 
     For a reverse-biased varactor diode, or any nonlinear capacitance, the current through the capacitor can be written in the most general way as: 
     
       
         
           
             
               
                 
                   
                     i 
                     c 
                   
                   = 
                   
                     
                       
                         C 
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                       ⁢ 
                       
                         
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                   ( 
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     where, ν is the small-signal incremental voltage applied to the varactor, and the coefficients C 0 , C 1 , . . . C n  are the non-linear Taylor coefficients that depend on the dc operating point of the varactor, i.e., 
     
       
         
           
             
               
                 
                   
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                     ⁡ 
                     
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     The coefficients C 1 , . . . C n  are responsible for the generation of distortion products in the circuit. In particular, the second-order distortion created by C 1  and the third-order distortion created by C 2  should both be made as small as possible. 
     If two capacitors C A  and C B  are connected in the “anti-series” configuration, as shown in  FIGS. 1A and 2A , then equation (3) can be written:
 
 C   A/B (ν A/B )= C   A0/B0   +/−C   A1/B1 ν A/B   +C   A2/B2 ν A/B   2 + . . .  (3)
 
     where the minus sign in (3) comes from the reversed connection of C B . When current flows through the capacitors, the incremental charge is given by
 
 Q (ν x )=∫ 0   ν     x     C (ν) dν   (4)
 
     In this case, the incremental charge on the two capacitors C A  and C B  is the same, and is given by 
     
       
         
           
             
               
                 
                   
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     since the two charges are equal, we can set Q(ν A )=Q(ν B )=Q and solve for ν A  and ν B  through a series reversion. The total voltage across the series capacitor ν is the sum of the two individual voltages ν A  and ν B , so 
     
       
         
           
             
               
                 
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                     where 
                   
                 
               
               
                 
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     Taking the results from (6)-(9) and performing one last reversion and a differentiation yields: 
     
       
         
           
             
               
                 
                   
                     
                       
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                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     where the linear and quadratic terms in ν need to be minimized—ideally to zero—in order to reduce the distortion in the circuit. This result is essentially identical to that reported in R. G. Meyer and M. L. Stephens, “Distortion in variable-capacitance diodes,” Journal of Solid-State Circuits, vol. SC-10, issue 1, pp. 47-55, February 1975. However, the invention provides practical and generalized low-distortion varactor topologies that provide specific solutions to the problem recognized in the art of reducing distortion. Also, artisans have previously assumed, based upon the use of identical varactors in the anti-series configuration, that identical varactors should be used in the anti-series and anti-parallel connection. This has limited the topology for achieving low distortion to the special case of n=0.5. 
     There are several possibilities for minimizing the C 2  term in (10), which is primarily responsible for the third-order distortion in the current. If the nonlinear capacitors are fabricated in the same semiconductor process and operated at the same dc bias, but their sizes differ by some constant s, then their nonlinear coefficients will each differ by s, i.e. C B0 =sC A0 , C B1 =sC A1 , and C B2 =sC A2 . In this case, the quadratic term in (10) (C 2 ) can be set to zero when; 
     
       
         
           
             
               
                 
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                   ( 
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     This was recognized in K. Buisman, et al., “Low-distortion, low loss varactor-based adaptive matching networks, implemented in a silicon-on-glass technology,” in Proc. 2005 Radio Frequency IC Symp., Long Beach, Calif., June 2005, pp. 389-392; and by Q. Han, et al, “Perturbation analysis and experimental verification on intermodulation and harmonic distortion in an anti-series varactor pair,” IEICE Trans. on Electronics, Vol. E88-C, No. 1, pp. 89-97, January 2005. 
     However, setting C 2  to zero will not completely eliminate third-order distortion in a circuit application, due to the second-order interaction between the C 1  and C 0  terms through the finite source impedance. Complete elimination of third-order distortion would also require that C 1  in (10) be eliminated. From (8), C 1  can only be set to zero for the case of two equal sized capacitors (s=1) with an identical grading coefficient, this is in contradiction to requirement for s, following from (11), for the elimination of C 2  in most cases. 
     To address this dilemma, it is recognized in the invention that the effect of a finite C 1  term can be independently eliminated, by the use of the anti-parallel connection of an identical network, as shown in  FIGS. 1B and 2B , when a particular diode area ratio is used. With the anti-parallel connection of two nonlinear capacitors,
 
 C   x (ν)= C   x0   +C   x1   ν+C   x2 ν 2 + . . .  (12)
 
 C   y (ν)= C   y0   −C   y1   ν+C   y2 ν 2 + . . .  (13)
 
     the resulting total capacitance is then the sum of all the individual capacitances, i.e.,
 
 C (ν)=( C   x0   +C   y0 )+ C   x1   −C   y1 )ν+( C   x2   +C   y2 )ν 2 + . . .  (14)
 
     If the topology uses size-matched diodes in the anti-parallel connection of  FIGS. 1B and 2B , the following expression is obtained,
 
 C (ν)=2 C   x0 +2 C   x2 ν 2 + . . .  (15)
 
     The result is perfect cancellation of all second-order components, which arise from the C 1  terms. Combining the results of (11)—canceling the third-order distortion (so C x2 =0)—with (15)—canceling second-order (and all even) distortion products—results in a capacitor with no residual distortion of order less than five, representing a substantial improvement. 
     To derive a mathematical description for the low distortion varactor configurations, we first recall the classical capacitance relation of a single varactor diode, which can be expressed as: 
     
       
         
           
             
               
                 
                   
                     C 
                     ⁡ 
                     
                       ( 
                       V 
                       ) 
                     
                   
                   = 
                   
                     K 
                     
                       
                         ( 
                         
                           ϕ 
                           + 
                           V 
                         
                         ) 
                       
                       n 
                     
                   
                 
               
               
                 
                   ( 
                   16 
                   ) 
                 
               
             
           
         
       
     
     where; φ is the built-in potential of the diode, V is the applied voltage, n is the power law exponent of the diode capacitance, and K is the capacitance constant. The power law exponent can exhibit wide variation in different situations, from a value of n≈0.3 for an implanted junction to n≈0.5 for a uniformly doped junction to n≈2 for a hyper-abrupt junction. 
     In order to develop the low distortion varactor diode circuits we first derive the Taylor coefficients of (16) yielding, 
     
       
         
           
             
               
                 
                   
                     
                       C 
                       0 
                     
                     = 
                     
                       K 
                       
                         
                           ( 
                           
                             ϕ 
                             + 
                             
                               V 
                               
                                 B 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                           
                           ) 
                         
                         n 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
             
               
                 
                   
                     C 
                     1 
                   
                   = 
                   
                     
                       - 
                       
                         C 
                         0 
                       
                     
                     ⁢ 
                     
                       n 
                       
                         ϕ 
                         + 
                         
                           V 
                           
                             B 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     and 
                   
                 
               
               
                 
                   ( 
                   18 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       C 
                       2 
                     
                     = 
                     
                       
                         C 
                         0 
                       
                       ⁢ 
                       
                         
                           n 
                           ⁡ 
                           
                             ( 
                             
                               n 
                               + 
                               1 
                             
                             ) 
                           
                         
                         
                           2 
                           ⁢ 
                           
                             
                               ( 
                               
                                 ϕ 
                                 + 
                                 
                                   V 
                                   
                                     B 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                   
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   19 
                   ) 
                 
               
             
           
         
       
     
     where V B1  is the dc bias voltage on the diodes from  FIG. 2 . 
     The diode configuration represented in  FIG. 1A  can now be employed to realize a voltage variable capacitor with low third-order distortion. In this case, we set the ratio of the diode areas D B /D A  to be s as in (11) and—following the same procedure as in (6)-(10)—this yields expressions for the linear and nonlinear terms of the capacitance of the circuit of  FIG. 2A  of 
     
       
         
           
             
               
                 
                   
                     
                       C 
                       0 
                     
                     = 
                     
                       
                         sK 
                         A 
                       
                       
                         
                           ( 
                           
                             1 
                             + 
                             s 
                           
                           ) 
                         
                         ⁢ 
                         
                           
                             ( 
                             
                               ϕ 
                               + 
                               
                                 V 
                                 
                                   B 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                             
                             ) 
                           
                           n 
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   20 
                   ) 
                 
               
             
             
               
                 
                   
                     C 
                     1 
                   
                   = 
                   
                     
                       
                         
                           ( 
                           
                             1 
                             - 
                             s 
                           
                           ) 
                         
                         ⁢ 
                         
                           nC 
                           0 
                         
                       
                       
                         
                           ( 
                           
                             1 
                             + 
                             s 
                           
                           ) 
                         
                         ⁢ 
                         
                           ( 
                           
                             ϕ 
                             + 
                             
                               V 
                               
                                 B 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 I 
                               
                             
                           
                           ) 
                         
                       
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     and 
                   
                 
               
               
                 
                   ( 
                   21 
                   ) 
                 
               
             
             
               
                 
                   
                     C 
                     2 
                   
                   = 
                   
                     
                       
                         
                           C 
                           0 
                         
                         ⁢ 
                         
                           n 
                           ⁡ 
                           
                             [ 
                             
                               
                                 
                                   ( 
                                   
                                     
                                       s 
                                       2 
                                     
                                     + 
                                     1 
                                   
                                   ) 
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     n 
                                     + 
                                     1 
                                   
                                   ) 
                                 
                               
                               - 
                               
                                 s 
                                 ⁡ 
                                 
                                   ( 
                                   
                                     
                                       4 
                                       ⁢ 
                                       n 
                                     
                                     + 
                                     1 
                                   
                                   ) 
                                 
                               
                             
                             ] 
                           
                         
                       
                       
                         2 
                         ⁢ 
                         
                           
                             ( 
                             
                               ϕ 
                               + 
                               
                                 V 
                                 
                                   B 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                             
                             ) 
                           
                           2 
                         
                         ⁢ 
                         
                           
                             ( 
                             
                               s 
                               + 
                               1 
                             
                             ) 
                           
                           2 
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   22 
                   ) 
                 
               
             
           
         
       
     
     Note that—as in (11)—C 2  (21) can be made equal to zero by setting 
     
       
         
           
             
               
                 
                   s 
                   = 
                   
                     
                       
                         4 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         n 
                       
                       + 
                       1 
                       + 
                       
                         
                           
                             12 
                             ⁢ 
                             
                               n 
                               2 
                             
                           
                           - 
                           3 
                         
                       
                     
                     
                       2 
                       ⁢ 
                       
                         ( 
                         
                           n 
                           + 
                           1 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   23 
                   ) 
                 
               
             
           
         
       
     
     resulting in zero third-order distortion caused by the capacitance term C 2 . The result of (23) demonstrates that cancellation can only occur for cases where the diode power-law exponent is equal or greater than 0.5. The second root of (23) (and from (11)) can be neglected because the two roots are inverses of each other; diode area ratios of value s and 1/s both result in C 2 =0. Simulations have shown that a deviation of more than 25% of the calculated ratio s essentially eliminates the desired distortion cancellation effect. Accordingly, in exemplary embodiments, devices meet the ratio s with a deviation of 25% or less. 
     A constant doping profile in the diode (the so-called “abrupt junction” case where n=0.5) results in a value of s of unity, as has been previously recognized. This case is particularly attractive because—from (15)—this set of conditions (n=0.5, s=1), sets both C 2  and C 1  equal to zero. A more elaborate analysis shows that all higher order distortion terms vanish, yielding (in theory) a “distortion-free” operation for this unique case 
     The explanation for this desirable “distortion free” behavior can be intuitively seen from rewriting (1) for the diode stored charge as a function of the applied voltage for the n=0.5 case, i.e. 
     
       
         
           
             
               
                 
                   V 
                   = 
                   
                     ϕ 
                     ( 
                     
                       
                         
                           Q 
                           0 
                           2 
                         
                         - 
                         
                           Q 
                           2 
                         
                       
                       
                         Q 
                         0 
                         2 
                       
                     
                     ) 
                   
                 
               
               
                 
                   ( 
                   24 
                   ) 
                 
               
             
           
         
       
     
     where Q 0 =2K/φ n-1 . 
     When an incremental voltage ν is applied to the diode pair, an incremental charge q is stored in the diodes, and the incremental voltage—in terms of the stored charge is: 
     
       
         
           
             
               
                 
                   
                     
                       
                         v 
                         = 
                           
                         ⁢ 
                         
                           
                             V 
                             A 
                           
                           + 
                           
                             V 
                             B 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             ϕ 
                             ( 
                             
                               
                                 
                                   Q 
                                   0 
                                   2 
                                 
                                 - 
                                 
                                   
                                     ( 
                                     
                                       Q 
                                       + 
                                       q 
                                     
                                     ) 
                                   
                                   2 
                                 
                               
                               
                                 Q 
                                 0 
                                 2 
                               
                             
                             ) 
                           
                           - 
                           
                             ϕ 
                             ( 
                             
                               
                                 
                                   Q 
                                   0 
                                   2 
                                 
                                 - 
                                 
                                   
                                     ( 
                                     
                                       Q 
                                       - 
                                       q 
                                     
                                     ) 
                                   
                                   2 
                                 
                               
                               
                                 Q 
                                 0 
                                 2 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             
                               4 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               ϕ 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               Q 
                             
                             
                               Q 
                               0 
                               2 
                             
                           
                           ⁢ 
                           q 
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             2 
                             
                               C 
                               0 
                             
                           
                           ⁢ 
                           q 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   25 
                   ) 
                 
               
             
           
         
       
     
     So, the incremental charge has a linear relationship with the applied incremental voltage in the special case of n=0.5, and the diode pair acts like an ideal voltage-controlled linear capacitor. This principle of producing a linear controlled source from the difference between two square-law controlled sources has been used extensively in the design of linear MOS transconductors that exploit the square law behavior of long channel MOSFETs. See, e.g., E. Seevinck and R. Wassenaar, “A versatile CMOS linear transconductor/square-law function circuit,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 3, pp. 366-377, June, 1987. 
     This result can also be used to calculate the ideal center-tap voltage for the special case of n=0.5, 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       V 
                       CT 
                     
                   
                   = 
                   
                     
                       
                         Δ 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         V 
                       
                       2 
                     
                     - 
                     
                       
                         
                           ( 
                           
                             C 
                             
                               C 
                               0 
                             
                           
                           ) 
                         
                         2 
                       
                       ⁢ 
                       
                         
                           
                             ( 
                             
                               Δ 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 V 
                                 / 
                                 2 
                               
                             
                             ) 
                           
                           2 
                         
                         ϕ 
                       
                     
                   
                 
               
               
                 
                   ( 
                   26 
                   ) 
                 
               
             
           
         
       
     
     which exhibits only the fundamental frequency and second-order distortion. 
     For process technologies that allow a higher capacitance tuning range (n&gt;0.5) the solution of (23) provides a direct way to calculate the required diode area ratio to minimize C 2 . For example, in the case where n=1, the required area ratio is exactly two. In the case of n=2, which corresponds to the ideal hyper-abrupt junction, the required area ratio is 2.6. These area ratios are straightforward to realize with high accuracy in any standard integrated circuit process that includes varactor diodes. 
     Although this approach can minimize C 2 , it is clear from our previous analysis that a value of s≠1 will result in a finite value of C 1 . The placement of a matched varactor stack in anti-parallel configuration, as shown in  FIG. 1A , this distortion contribution can be eliminated. The resulting linear capacitance of the varactor diode circuits of  FIGS. 1A and 1B  are identical, but the circuit of  FIG. 1B , as represented by the capacitances in  FIG. 2B , now has C 1 =C 2 =0 when the proper area ratio is set. It should be noted that all the even-order distortion coefficients are zero (C 1 , C 3 , C 5 , . . . =0) in this topology, but the higher coefficients that create odd-order distortion (C 4 , C 6 , C 8 , . . . ) of  FIG. 1B  are not zero, although the IM3 contributions at (2ω 2 −ω 1 ) due to the 5 th  and higher order nonlinearities are very small. 
     The circuit topology of  FIG. 1A  provides a substantially distortion-free varactor stack when s=1 and n=0.5, corresponding to a uniform doping profile of the varactors. The circuit of  FIG. 1B  is more generalized, however, and provides substantially distortion free varactor stack for any value n&gt;0.5, by setting the proper ratio of the diode areas, which sets C 1  and C 2  to zero. This topology provides more freedom for use in different process technologies and facilitates linear operation with a higher C max /C min  ratio than the n=0.5 case. 
     The intercept points of the varactor topologies are a function of the control voltage and can be expressed analytically as shown in Table I, below. It is appropriate to express the intercept point values in voltage rather than the more traditional available power, since the available power to the diodes will depend on the impedance matching conditions. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                 IP2 
                 IP3 
                 IP4 
               
               
                   
               
             
            
               
                 Single diode 
                 
                   
                     
                       
                         
                           ϕ 
                           + 
                           
                             V 
                             
                               n 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                         
                         n 
                       
                     
                   
                 
                 
                   
                     
                       
                         2 
                         ⁢ 
                         
                           
                             
                               2 
                               ⁢ 
                               
                                 
                                   ( 
                                   
                                     ϕ 
                                     + 
                                     
                                       V 
                                       
                                         B 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         1 
                                       
                                     
                                   
                                   ) 
                                 
                                 2 
                               
                             
                             
                               n 
                               ⁡ 
                               
                                 ( 
                                 
                                   n 
                                   + 
                                   1 
                                 
                                 ) 
                               
                             
                           
                         
                       
                     
                   
                 
                 
                   
                     
                       
                         2 
                         ⁢ 
                         
                           
                             ( 
                             
                               
                                 - 
                                 
                                   
                                     ( 
                                     
                                       ϕ 
                                       + 
                                       
                                         V 
                                         
                                           B 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           1 
                                         
                                       
                                     
                                     ) 
                                   
                                   3 
                                 
                               
                               
                                 n 
                                 ⁡ 
                                 
                                   ( 
                                   
                                     
                                       n 
                                       2 
                                     
                                     + 
                                     
                                       3 
                                       ⁢ 
                                       
                                           
                                       
                                       ⁢ 
                                       n 
                                     
                                     + 
                                     2 
                                   
                                   ) 
                                 
                               
                             
                             ) 
                           
                           
                             1 
                             3 
                           
                         
                       
                     
                   
                 
               
               
                   
               
               
                 Distortion Free 
                 ∞ 
                 ∞ 
                 ∞ 
               
               
                 Varnetor Stack 
               
               
                 High Tuning 
                 ∞ 
                 ≈3.4(φ + V DC ) 
                 ∞ 
               
               
                 Range Varactor 
               
               
                 Stack 
               
               
                 (HTRVS) 
               
               
                   
               
            
           
         
       
     
     Table I shows the theoretical voltage intercept points for differing diode configurations. The calculated IP2, IP3, and IP4 for the High Tuning-Range Varactor Stack correspond to the n=1, s=2 condition. Since there is no 3 rd -order distortion for this configuration, the IP3 value is the extrapolated intercept point of the residual 5 th  order distortion at 2ω 2 −ω 1 . 
     To this point, it has been assumed that the dc biasing network of the center tap has a sufficiently high impedance so that it has no effect on the RF operation of the varactor stack configuration. However, in practical situations the shunting impedance of the center contact must be maximized to avoid linearity degradation. This occurs when the AC current through the bias network for the various harmonic components becomes significant compared to the desired AC current through the diodes. In this situation, the conditions for distortion cancellation are violated. This is especially a problem for intermodulation measurements at small tone spacings since, from (26), the center tap voltage has a component at the difference frequency of a two-tone test. Since the capacitive reactance increases without bound as the frequency goes to zero, there is a lower frequency limit of tone spacing where the intermodulation cancellation effect is effective. Referring to the configuration of  FIGS. 1A and 2A , this condition is 
     
       
         
           
             
               
                 
                   
                     R 
                     01 
                   
                   &gt;&gt; 
                   
                     1 
                     
                       2 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       π 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         C 
                         A 
                       
                       ⁢ 
                       Δ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   27 
                   ) 
                 
               
             
           
         
       
     
     This condition can be satisfied by an integrated resistor, but the resistance value can become prohibitively large for even moderate tone spacings. In the regime of ultra-low tone spacing, where (27) cannot be satisfied, the IP 3  improvement over a single diode (slightly more than a factor two) can be almost entirely explained by the factor two reduction in RF voltage across each diode. 
     A better way to implement the high impedance at the center-tap while keeping the area required for the bias circuit small is the use of a small anti-parallel diode pair is shown by the topology depicted in  FIG. 3 , where anti-parallel diode bias is provided by a pair of varactor diodes C D  (18) and R D . (20). This is quite effective for most applications, since the zero bias impedance of the diodes is very high. 
     The effect of center-tap impedance on linearity is shown with a specific simulation example of IIP3 in  FIG. 4 .  FIG. 4 . shows simulated IP3(V) for a single varactor and a voltage driven DFVS under a two-tone test as function of the tone spacing and center tap impedance (f c =1 GHz, C 0 =10 pF, V center tap =5V, n=0.5, C D =0.1 pF). The figure shows three distinct regions of operation: the shunt dc leakage impedance of the diodes R D  limits the linearity at very low tone spacings, the zero-bias capacitance C D  of the anti-diode pair limits the IIP3 to a constant value at moderate tone spacings, and the linearity approaches the ideal infinite IIP3 at high tone spacings. In the moderate tone spacing regime, where the anti-parallel biasing diode capacitance limits the linearity, the IIP3 is given by 
     
       
         
           
             
               
                 
                   
                     IIP 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                     ⁢ 
                     
                       ( 
                       V 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         2 
                         ⁢ 
                         
                           
                             
                               C 
                               0 
                               2 
                             
                             ⁡ 
                             
                               ( 
                               
                                 
                                   2 
                                   ⁢ 
                                   
                                     C 
                                     0 
                                   
                                 
                                 + 
                                 
                                   C 
                                   D 
                                 
                               
                               ) 
                             
                           
                           4 
                         
                       
                       
                         3 
                         ⁢ 
                         
                           C 
                           1 
                           2 
                         
                         ⁢ 
                         
                           
                             C 
                             D 
                           
                           ⁡ 
                           
                             ( 
                             
                               
                                 C 
                                 D 
                                 3 
                               
                               + 
                               
                                 4 
                                 ⁢ 
                                 
                                   C 
                                   0 
                                 
                                 ⁢ 
                                 
                                   C 
                                   D 
                                   2 
                                 
                               
                               + 
                               
                                 6 
                                 ⁢ 
                                 
                                   C 
                                   0 
                                   2 
                                 
                                 ⁢ 
                                 
                                   C 
                                   D 
                                 
                               
                               + 
                               
                                 2 
                                 ⁢ 
                                 
                                   C 
                                   0 
                                   3 
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   28 
                   ) 
                 
               
             
           
         
       
     
     which is approximately 
     
       
         
           
             
               
                 
                   
                     IIP 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                     ⁢ 
                     
                       ( 
                       V 
                       ) 
                     
                   
                   ≈ 
                   
                     8 
                     ⁢ 
                     
                       ( 
                       
                         ϕ 
                         + 
                         
                           V 
                           BJ 
                         
                       
                       ) 
                     
                     ⁢ 
                     
                       
                         
                           C 
                           0 
                         
                         
                           3 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             C 
                             D 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   29 
                   ) 
                 
               
             
           
         
       
     
     for the uniformly doped n=0.5 case and for small values of C D . This illustrates the importance of maintaining a low parasitic capacitance in the diode dc bias circuit. 
     Anti-parallel diodes in the center tap should not corrupt the intended RF signal flow. Ideally, no RF current leaves through the center tap connection. Good performance should be realized for center tap connections that have a capacitance that is significantly lower, e.g. significantly less then 50% of the capacitance of diodes in the RF path. 
       FIG. 4 . shows that the distortion-free varactor stack outperforms the single varactor in terms of linearity; however, the best results are obtained when the cut-off frequency of the dc bias network (½πc eff Z s ) is much lower than the difference frequency. In addition to the requirement of high center tap impedance, the varactor diodes should not become forward biased nor exceed the diode voltage-breakdown conditions during the RF signal cycle. These technological constraints must be considered in practical RF applications requiring variable capacitance. 
     The varactor diodes in the above analysis have been considered as an ideal circuit element with a capacitance behavior as given by (16). However, when considering real devices, physical implementations and their related constraints need to be addressed. In particular, it is necessary to ensure that the extrinsic parasitic elements do not increase the loss and degrade the linearity. For this purpose, a simplified varactor diode structure, with an abrupt junction between an uniform lightly doped N −  region and a much more heavily doped P +  region will be used as an example. Calculations assume that the RF performance degradation due to the P +  and N ++  contact region is negligible. 
     A first consideration is the intrinsic breakdown voltage and Quality Factor of this simplified structure. A subsequent consideration is the available capacitance control range for a uniformly doped varactor. 
     The varactor diode capacitance is given by: 
     
       
         
           
             
               
                 
                   
                     C 
                     t 
                   
                   ≈ 
                   
                     
                       ɛ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         A 
                         j 
                       
                     
                     
                       x 
                       n 
                     
                   
                 
               
               
                 
                   ( 
                   30 
                   ) 
                 
               
             
           
         
       
     
     where ∈ is the silicon permittivity, A j  is the diode area, and x n  is the depletion width given by 
     
       
         
           
             
               x 
               n 
             
             = 
             
               
                 
                   
                     
                       2 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       ɛ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         
                           N 
                           a 
                         
                         ⁡ 
                         
                           ( 
                           
                             ϕ 
                             - 
                             
                               V 
                               j 
                             
                           
                           ) 
                         
                       
                     
                     
                       
                         qN 
                         d 
                       
                       ⁡ 
                       
                         ( 
                         
                           
                             N 
                             a 
                           
                           + 
                           
                             N 
                             d 
                           
                         
                         ) 
                       
                     
                   
                 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 and 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 ϕ 
               
               = 
               
                 
                   v 
                   i 
                 
                 ⁢ 
                 
                   ln 
                   ⁡ 
                   
                     ( 
                     
                       
                         
                           N 
                           a 
                         
                         ⁢ 
                         
                           N 
                           d 
                         
                       
                       
                         N 
                         i 
                         2 
                       
                     
                     ) 
                   
                 
               
             
           
         
       
     
     where N a , N d  and N t  are respectively; the acceptor, donor and intrinsic carrier concentrations, and κ t  is the thermal voltage given by kT/q. In the rest of the calculations, assumptions are based upon silicon-based devices operating at 2 GHz, N a =10 19  cm −3  and a critical breakdown field for silicon E crit =6×10 5 V/cm. 
     Using the expression for x n  the breakdown voltage can be determined by setting the maximum value of the electric field E max    
     (qN d x n /∈) equal to the critical electrical field for silicon, yielding: 
     
       
         
           
             
               
                 
                   
                     V 
                     break 
                   
                   = 
                   
                     
                       
                         - 
                         
                           ɛ 
                           2 
                         
                       
                       ⁢ 
                       
                         ( 
                         
                           
                             
                               N 
                               a 
                             
                             + 
                             
                               N 
                               d 
                             
                           
                           
                             
                               qN 
                               d 
                             
                             ⁢ 
                             
                               N 
                               a 
                             
                           
                         
                         ) 
                       
                       ⁢ 
                       
                         E 
                         crit 
                         2 
                       
                     
                     + 
                     
                       ϕ 
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   31 
                   ) 
                 
               
             
           
         
       
     
       FIG. 5A  plots intrinsic quality factor and breakdown voltage for silicon (solid lines) and GaAs (dashed lines) varactor diodes as a function of doping.  FIG. 5B  plots effective single varactor diode capacitance tuning ratio (c ratio ) for silicon (solid lines) and GaAs (dashed lines) based varactor diodes at different RF voltage amplitudes as function of doping.  FIG. 5A  plots the resulting breakdown voltage for a uniformly doped silicon varactor device, as function of doping concentration. As the doping level is lowered, the resulting breakdown voltage of the diode increases. But unfortunately, the series resistance of the undepleted region also increases, lowering the effective Q of the structure. 
     The Q of a varactor is defined as: 
     
       
         
           
             
               
                 
                   Q 
                   = 
                   
                     
                       Im 
                       ⁡ 
                       
                         ( 
                         
                           Z 
                           var 
                         
                         ) 
                       
                     
                     
                       Re 
                       ⁡ 
                       
                         ( 
                         
                           Z 
                           var 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   32 
                   ) 
                 
               
             
           
         
       
     
     where Z var  is the series impedance of the varactor diode. The diode series resistance is assumed to be completely dominated by the effective resistance of the undepleted N region (without contact resistances). Assuming the worst-case series resistance corresponds to the completely undepleted situation, we can write: 
     
       
         
           
             
               
                 
                   
                     R 
                     var 
                   
                   = 
                   
                     
                       
                         
                           φ 
                           si 
                         
                         ⁢ 
                         l 
                       
                       
                         A 
                         j 
                       
                     
                     ≈ 
                     
                       
                         x 
                         n 
                       
                       
                         
                           qN 
                           d 
                         
                         ⁢ 
                         
                           μ 
                           n 
                         
                         ⁢ 
                         
                           A 
                           j 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   33 
                   ) 
                 
               
             
           
         
       
     
     The length l is set to the thickness of the lightly-doped N region, which follows from the maximum depletion width for a given doping concentration. Furthermore, φ Si  represents the doping dependent resistivity of silicon, which, based on room-temperature data for the doping range of 10 15 ˜10 18  cm −3 , is approximately 
     
       
         
           
             
               
                 
                   
                     φ 
                     Si 
                   
                   = 
                   
                     
                       4 
                       × 
                       
                         10 
                         12 
                       
                     
                     
                       N 
                       d 
                       
                         0 
                         , 
                         8 
                       
                     
                   
                 
               
               
                 
                   ( 
                   34 
                   ) 
                 
               
             
           
         
       
     
     Using (30)-(34), the Q of the varactor diode is calculated in  FIG. 5A  versus doping concentration for the zero-bias condition. This situation represents the worst-case condition, since the Q tends to improve for higher reverse bias of the diode, due to the decrease in capacitance as well as series resistance. 
     The result of this analysis is that, to maintain a Q of greater than 100 for a silicon device, the diode doping level must exceed 4×10 16  cm −3  which limits the breakdown voltage to less than 30V. Although this represents an excellent level of performance, further Q enhancement can be achieved in a material system with a better mobility/breakdown voltage tradeoff, such as GaAs or other Group III-V materials. 
     The effective capacitance tuning range for a single diode as a function of doping concentration for different RF voltages for the uniformly doped case is plotted in  FIG. 5B . Here again, there is a clear tradeoff between capacitance tuning range and Q; and a higher diode doping level improves the Q of the diode but lowers the achievable tuning range. 
     When considering the anti-series connection of two identical uniformly doped varactor diodes, the RF voltage across a single diode under low power conditions will be approximately half the RF voltage applied to the entire varactor stack. At higher power levels, the diode capacitances will be significantly modulated by the RF signal, and the voltage distribution between the two diodes will not be equal. In practice, this is not a problem, since the largest RF voltage will be across the smallest capacitance, which is offered by the most strongly reverse biased diode. This effect will slightly improve the usable capacitance tuning range compared to the results in  FIGS. 5A and 5B , although in practice the improvement is rather small. 
       FIG. 6  illustrates a circuit topology with multi-varactor stacks  22  and  24  in series to lower the RF voltage per diode and consequently improve the voltage handling and tuning range capabilities. The voltage handling capabilities of the varactor stack can be improved by combining varactor diodes in series  FIG. 6 . This can yield a lower control voltage and a higher Q factor for a given signal level than a single varactor stack using a thicker epilayer, provided that the additional connections do not degrade the Q. The major penalty for this action is a larger device area for a given capacitance (roughly 4× the area for each doubling of the number of varactor diodes). 
     The improvement in tuning range of these multiple varactor stacks for higher applied RF voltages is illustrated in  FIG. 7 .  FIG. 7  shows calculated capacitance tuning ratio for the uniformly doped multi-stacked DFVS configuration, featuring 2, 4 and 8 anti-series diodes, (N d =2×10 16  and N d =4×10 16 ) as function of applied RF voltage. For simplicity it is assumed that a uniform voltage division over the diodes while V source  represents the applied RF voltage over the whole (multi-) varactor stack. Note that GaAs based devices have a Q advantage over silicon due to the higher mobility, but GaAs provides basically no improvement in tuning range over silicon for a given uniform varactor doping concentration. The control voltage of these multi-varactor stacks is constrained by the breakdown voltage of a single varactor and is limited to ˜30V and ˜60V for N d =4×10 16  and N d =2×10 16  respectively. 
       FIG. 8  shows simulated IP3(V) for a single reversed diode, and (multi)-DFVS varactor configurations, featuring 2, 4 and 8 anti-series diodes, as function of the tone spacing and center tap impedance (f c =1 GHz, C 0 eff =10 pF, V center tap =5V, n=0.5, C D =0.1 pF). The reduced voltage swing per diode in multi-stacked DFVS configurations is also directly beneficial for the linearity. This is illustrated in  FIG. 8 . where the IP3 (V) is given for a single diode, a DFVS, a multi-DFVS configuration with 4 anti-series diodes (as given in  FIG. 6 ) and a multi-DFVS configuration featuring 8 anti-series diodes.  FIG. 8  shows the exact doubling of the IP3 (V), at very low tone spacing, for each halving of the RF voltage per diode when utilizing multi-DFVS configurations. Also the requirement on the high center-tap impedance for a slightly higher tone-spacing seems to be somewhat relaxed, making the practical implementation of linear tunable narrowband applications easier. 
     The varactor diode stack can act as a controllable capacitor, whose value can be adjusted through the center tap voltage. In order to maintain acceptable linearity, each of the individual varactor diodes in the stack must remain sufficiently reversed biased during large-signals. 
     Although varactors have been around for decades and anti-series diode structures are used in oscillators or even, recently, for distortion reduction in electronically scannable antennas, it is believed that no commercially available varactor technology is currently suited to fulfill the demands for “distortion-free” operation, Q&gt;100@2 GHz, and capacitance &gt;10 pF. 
     A silicon-on-glass varactor device integration is provided and has been tested.  FIG. 9A  shows a cross section of a silicon-on-glass varactor device integration. In  FIG. 9A  a glass substrate  26  is attached to a silicon wafer  28 . The diode topologies  10  and  12  are fabricated within a uniform doping region of the silicon wafer  28 . Oxide and contact patterning  30  in the wafer  28  on both front and back sides of the wafer  28  permits the varactor diodes to be directly contacted on both sides of the wafer  28 , which was done with copper plated aluminum in experimental devices. 
       FIG. 9B  shows the layout of an experimental device in accordance with  FIG. 9A . The device of  FIG. 9A  provides a low loss substrate and patterning of both the front and back sides of the wafer so the intrinsic varactor can be directly contacted by thick metal on both sides. This eliminates the need for a buried layer or finger structures, as would be the case in conventional integrated varactor implementations. In the experimental device, a 4 μm copper layer has been plated on 1.4 μm aluminum, to minimize the metal losses. 
     The measured Q of DFVS structures realized in the experimental devices (using a uniform doping of 1×10 17  cm −3 ) varied from 100 to 600 as the bias voltage changed, due the decreasing length of the undepleted region at larger reverse bias voltages. 
     To test the level of “distortion-free” operation achieved, a two-tone test (f c =2.14 GHz) was performed on a single varactor and a DFVS using a 50Ω terminated two-port configuration. For the calibrated power measurement of all frequency components of interest, the system of described in M. Spirito, et al, “A novel active harmonic load-pull setup for on-wafer device linearity characterization,” in 2004 IEEE MTT-S Int. Microwave Symp. Dig., Fort Worth, Tex., June 2004, pp. 1215-1218, was used. 
       FIG. 10  plots the measured and simulated IM3 &amp; IM5 components as function of power for different tone-spacing (Δf=100 kHz and Δf=10 MHz) using a center-tap impedance of 47 kΩ and a center-tap bias of 2V. These results match the theory presented above very well. There is a substantial improvement in linearity using the DFVS configuration over a single-varactor diode. Note that due to the fact that the RF voltage is split over the diodes of the DFVS, the forward drive conditions occur at a 6 dB higher power level for this configuration. The better suppression of the IM3 and IM5 products at the higher tone spacing is also clearly visible, supporting the theory introduced previously. 
     Several different experimental circuits have been implemented to verify the RF adaptivity features of varactor diode variable capacitor topologies of the invention, including a tunable bandpass filter and a low loss tuner. For these circuits an epi-layer of 1 μm, was employed, yielding a breakdown voltage for a single varactor diode of approximately 30V. 
     A bandpass filter was implemented and tested. The filter was simple tunable single-pole/single zero filter having the configuration shown in  FIG. 11 . The  FIG. 11  filter can be adapted, for example, as a SAW filter replacement in a mobile handset, minimizing transmit leakage to the receiver/mixer in frequency-duplex cellular systems. The variable capacitors C 1  and C 2  in  FIG. 11  were implemented with anti-series varactor diode arrangements consistent with  FIG. 2A  and sized equally (since n=0.5 for that case). 
     The requirements for such a filter are extremely low loss in the receive band, high rejection in the transmit band, and high linearity to avoid cross-modulation distortion. A combination of a low loss on-chip microstrip transmission lines and bondwires was utilized to create the required inductance. 
     The measured tunable filter insertion loss and stopband suppression as s 21  versus frequency for the experimental device formed according to  FIG. 11  is given in  FIG. 12 , and the loss in the passband is 2-3 dB over the 1 GHz variation. The transmit/receive channel-spacing for this filter is 400 MHz. 
     A triple-beat/XMOD distortion test was performed in order to characterize the large-signal behavior of experimental filters. For this purpose, two signals are presented in the stopband at 1.999 and 2.001 GHz with a power level of −5.6 dBm to account for the transmit-breakthrough signal. A jammer signal (f jam =2.5 GHz, 0 dBm) signal is presented in the passband. The resulting distortion components at f dist =2.498 and 2.502 GHz, are −98.5 dBc with respect to the jammer signal. The resulting IIP3 for this test condition is approximately
 
 IIP 3≈10 log(2)+ P   tx1   −ΔP   xmod /2=46 dBm.  (35)
 
     In addition, a two-tone test was performed in the passband of the tunable filter, also yielding an IIP3 of +46 dBm. These excellent results for the large-signal performance provide a wide design margin for a designer of adaptive wireless systems. 
     Experimental integrated adaptive matching networks based on the two-stage ladder-matching network of shown in  FIG. 13 , which includes the  FIG. 3 , diode biased variable circuit topology, were formed using a doping level of 4×10 16  cm −3  for the uniformly doped varactors to obtain a good tradeoff between tuning range, quality factor (Q&gt;100 @ 2 GHz), and breakdown voltage (˜30V). 
     The layout of the experimental tuner fabricated in accordance with  FIG. 13  consisted of low loss coplanar transmission lines and varactor diodes arranged to continuously vary the impedance transformation. The topology was been selected for its ease of implementation and the low Q it offers for the high input power/low input impedance condition. There are only two control voltages (&lt;18V) and the total structure is very compact (&lt;3.5 mm 2 ). In contrast to MEMS based adaptive matching networks, the tuning speed of the varactor based matching network can be very fast, a property that can be used in a dynamic load-line amplifier. 
       FIG. 14A  shows the measured values of s 11  at 2 GHz for the experimental tuner in accordance with  FIG. 13 . The  FIG. 14A  plots shows a close-to-ideal distribution of impedance points, which cover the ohmic control range of 0.2 to 49 ohm. A maximum VSWR&gt;250:1 is seen in the data. An important parameter of a tuner is G p (=P out /P in ), which is the only true measure for the losses in power amplifier applications (note that G max  was better than −0.2 dB for all tuner settings).  FIG. 14B  plots the measured loss contours (Gp in dB) at all the different tuning points, the losses range from 0.5 dB at 1Ω to 3.5 dB for Z in =40Ω. The measured OIP3 of the tuner was 41 dBm for the Z in =37 ohm case and 52 dBm for the Z in =2 ohm case, with an input frequency of 2 Ghz and a tone spacing of 20 MHz.