Patent Publication Number: US-2003235952-A1

Title: Method for manufacturing non-volatile memory device

Description:
TECHNICAL FIELD  
       [0001] The present invention relates to a method for manufacturing a non-volatile memory device, and more particularly to a method for manufacturing a non-volatile memory device having a plurality of charge storing regions for each word gate.  
       BACKGROUND  
       [0002] Non-volatile semiconductor memory devices include a MONOS (Metal Oxide Nitride Oxide Semiconductor) type and a SONOS (Silicon Oxide Nitride Oxide Silicon) type in which a gate dielectric layer between a channel region and a control gate is composed of a stacked layered body of a silicon oxide layer—a silicon nitride layer—a silicon oxide layer, wherein a charge is trapped in the silicon nitride layer.  
       [0003] One known MONOS type non-volatile memory device is shown in FIG. 12 (H. Hayashi, et al, 2000 Symposium on VLSI Technology Digest of Technical Papers p.122-p.123). The MONOS type memory cell  100  has a word gate  14  formed over a semiconductor substrate  10  through a first gate dielectric layer  12 . Also, a first control gate  20  and a second control gate  30  in the form of sidewalls are disposed on both sides of the word gate  14 . A second gate dielectric layer  22  is present between a bottom section of the first control gate  20  and the semiconductor substrate  10 , and a dielectric layer  24  is present between a side surface of the first control gate  20  and the word gate  14 . Similarly, a second gate dielectric layer  22  is present between a bottom section of the second control gate  30  and the semiconductor substrate  10 , and a dielectric layer  24  is present between a side surface of the second control gate  30  and the word gate  14 . Impurity layers  16  and  18  that each compose a source region or a drain region are formed in the semiconductor substrate  10  between the opposing control gates  20  and  30  of adjacent memory cells.  
       [0004] In this manner, each memory cell  100  includes two MONOS type memory elements on the side surfaces of the word gate  14 . Also, these MONOS type memory elements are independently controlled. Therefore, a single memory cell  100  can store 2-bit information.  
       [0005] In view of the foregoing, one object of the present invention is to provide a method for manufacturing a MONOS type non-volatile memory device having a plurality of charge storing regions.  
       SUMMARY  
       [0006] A first dielectric layer is formed above a semiconductor layer, a first conductive layer is formed above the first dielectric layer, a first silicon oxide layer is formed above the first conductive layer, and a stopper layer is formed above the first silicon oxide layer. Next, the stopper layer, the first silicon oxide layer and the first conductive layer are patterned. An ONO film composed of a bottom silicon oxide layer, a silicon nitride layer and a top silicon oxide layer is then formed above the semiconductor layer and on both sides of the first conductive layer. A second conductive layer is formed above the ONO film. Next, the second conductive layer is anisotropically etched to form sidewall-like control gates on both side surfaces of the first conductive layer through the ONO film. An impurity layer which is to become a source region or a drain region is then formed in the semiconductor layer. A second silicon oxide layer is then formed over an entire surface of the substrate. The second silicon oxide layer is then polished such that the stopper layer is exposed. Next, the stopper layer is removed by dry etching and the first silicon oxide layer is removed. Finally, the first conductive layer is patterned to form a word gate. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0007]FIG. 1 schematically shows a plan view illustrating a layout of a semiconductor device.  
     [0008]FIG. 2 schematically shows a cross-sectional view taken along a line A-A of FIG. 1.  
     [0009]FIG. 3 shows one step in accordance with an embodiment of the present invention.  
     [0010]FIG. 4 shows one step in accordance with the embodiment of the present invention.  
     [0011]FIG. 5 shows one step in accordance with the embodiment of the present invention.  
     [0012]FIG. 6 shows one step in accordance with the embodiment of the present invention.  
     [0013]FIG. 7 shows one step in accordance with the embodiment of the present invention.  
     [0014]FIG. 8 shows one step in accordance with the embodiment of the present invention.  
     [0015]FIG. 9 shows one step in accordance with the embodiment of the present invention.  
     [0016]FIG. 10 shows one step in accordance with the embodiment of the present invention.  
     [0017]FIG. 11 shows one step in accordance with the embodiment of the present invention.  
     [0018]FIG. 12 shows a cross-sectional view of a known MONOS type memory cell. 
    
    
     DETAILED DESCRIPTION  
     [0019] 1. Structure Of The Non-Volatile Memory Device  
     [0020]FIG. 1 shows a plan view of a layout of a semiconductor device including a non-volatile memory device that is obtained by a manufacturing method in accordance with the present embodiment.  
     [0021] The semiconductor device includes a memory region  1000 . MONOS type non-volatile memory devices (hereafter referred to as “memory cells”) are arranged in a plurality of rows and columns in a matrix configuration in the memory region  1000 . In the memory region  1000 , a first block B 1  and parts of adjacent other blocks B 0  and B 2  are shown. Each of the blocks B 0  and B 2  has a structure that is the reverse of that of the block B 1 .  
     [0022] An element isolation region  300  is formed in a part of the region between the first block B 1  and the adjacent blocks B 0  and B 2 . A plurality of word lines (WL)  50  extending in an X direction (row direction) and a plurality of bit lines (BL)  60  extending in a Y direction (column direction) are provided in each of the blocks. Each one of the word lines  50  is connected to a plurality of word gates  14   a  arranged in the X direction. The bit lines  60  are composed of impurity layers  16  and  18 .  
     [0023] A conductive layer  40 , which composes the first and second control gates  20  and  30 , is formed in a manner to enclose each of the impurity layers  16  and  18 . In other words, the first and second control gates  20  and  30  extend respectively in the Y direction, and one of the end sections of one set of the first and second control gates  20  and  30  are mutually connected by the conductive layer that extends in the X direction. Further, the other end sections of the one set of the first and second control gates  20  and  30  are both connected to one common contact section  200 . Therefore, the conductive layer  40  functions as a control gate of a memory cell, and functions as a wiring that connects the control gates together that are arranged in the Y direction.  
     [0024] Each of the memory cells  100  includes one word gate  14   a , first and second control gates  20  and  30 , and impurity layers  16  and  18 . The first and second control gates  20  and  30  are formed on both sides of the word gate  14   a . The impurity layers  16  and  18  are formed on the outer sides of the control gates  20  and  30 . The impurity layers  16  and  18  are commonly shared by adjacent memory cells  100 .  
     [0025] The impurity layers  16  that are mutually arranged adjacent to each other in the Y direction, i.e., the impurity layer  16  formed in the block B 1  and the impurity layer  16  formed in the block B 2 , are mutually electrically connected by a contact impurity layer  400  that is formed within the semiconductor substrate. The contact impurity layer  400  is formed on the opposite side of the common contact section  200  of the control gates with respect to the impurity layer  16 .  
     [0026] A contact  350  is formed on the contact impurity layer  400 . The bit lines  60  composed of the impurity layers  16  are electrically connected to wiring layers in the upper layers through the contact  350 .  
     [0027] Similarly, two adjacent impurity layers  18  arranged in the Y direction, i.e., the impurity layer  18  formed in the block B 1  and the impurity layer  18  formed in the block B 0 , are mutually electrically connected by the contact impurity layer  400  on the side where the common contact section  200  is not disposed. As seen in FIG. 1, in each of the blocks, the plurality of common contact sections  200  for the impurity layers  16  and the impurity layers  18  are arranged on mutually opposite sides in a staggered fashion as viewed in a plan view layout. Also, in each of the blocks, the plurality of contact impurity layers  400  for the impurity layers  16  and the impurity layers  18  are arranged on mutually opposite sides in a staggered fashion as viewed in a plan view layout.  
     [0028] Referring to FIG. 2, a cross-sectional structure of the semiconductor device is described. FIG. 2 is a cross-sectional view taken along a line A-A of FIG. 1.  
     [0029] In the memory region  1000 , the memory cell  100  includes a word gate  14   a , impurity layers  16  and  18 , a first control gate  20  and a second control gate  30 . The word gate  14   a  is formed above the semiconductor substrate  10  through a first gate dielectric layer  12 . The impurity layers  16  and  18  are formed in the semiconductor substrate  10 . Each of the impurity layers is to become a source region or a drain region. Also, silicide layers  92  are formed on the impurity layers  16  and  18 .  
     [0030] The first and second control gates  20  and  30  are formed along both sides of the word gate  14   a . The first control gate  20  is formed above the semiconductor substrate  10  through a second gate dielectric layer  22 , and formed on one of the side surfaces of the word gate  14   a  through a side dielectric layer  24 . Similarly, the second control gate  30  is formed above the semiconductor substrate  10  through a second gate dielectric layer  22 , and formed on the other side surface of the word gate  14   a  through a side dielectric layer  24 . A cross-sectional configuration of each of the control gates is similar to the cross-sectional configuration of a sidewall dielectric layer on a conventional MOS transistor.  
     [0031] The second gate dielectric layer  22  is an ONO film. More specifically, the second gate dielectric layer  22  is a stacked layered film composed of a bottom silicon oxide layer  22   a , a silicon nitride layer  22   b  and a top silicon oxide layer  22   c . The bottom silicon oxide layer  22   a  forms a potential barrier between a channel region and a charge storing region. The silicon nitride layer  22   b  functions as a charge storing region that traps carriers (for example, electrons). The top silicon oxide layer  22   c  forms a potential barrier between the control gate and the charge storing region.  
     [0032] The side dielectric layer  24  is an ONO film. More specifically, the side dielectric layer  24  is composed of a stacked layer of a bottom silicon oxide layer  24   a , a silicon nitride layer  24   b  and a top silicon oxide layer  24   c . The side dielectric layers  24  electrically isolate the word gate  14   a  from the control gates  20  and  30 , respectively. Also, upper ends of at least the bottom silicon oxide layers  24   a  of the side dielectric layers  24  are positioned above the upper ends of the control gates  20  and  30  with respect to the semiconductor substrate  10  in order to prevent short-circuits of the word gate  14   a  and the first and second control gates  20  and  30 . The side dielectric layers  24  and the second gate dielectric layers  22  are formed in the same film forming steps, and have the same layered structure.  
     [0033] A second silicon oxide layer  70  is formed between the adjacent first control gate  20  and second control gate  30  of adjacent memory cells  100 . The second silicon oxide layer  70  covers the control gates  20  and  30  such that at least the gates  20  and  30  are not exposed. Furthermore, an upper surface of the second silicon oxide layer  70  is positioned above an upper surface of the word gate  14   a  with respect to the semiconductor substrate  10 . By forming the second silicon oxide layer  70  in this manner, electrical isolation of the first and second control gates  20  and  30  from the word gate  14   a  and the word line  50  can be more securely achieved.  
     [0034] An interlayer dielectric layer  72  is formed over the semiconductor substrate  10  where the memory cells  100  are formed.  
     [0035] 2. Method For Manufacturing The Non-Volatile Memory Device:  
     [0036] Next, referring to FIGS.  3 - 11 , a method for manufacturing a non-volatile memory device in accordance with an embodiment of the present invention is described. Each cross-sectional view corresponds to a cross section taken along a line A-A of FIG. 1. Also, portions in FIGS.  3 - 11  that are substantially the same as the portions indicated in FIGS. 1 and 2 are assigned the same reference numbers, and their description is not repeated.  
     [0037] (1) First, an element isolation region  300  (see FIG. 1) is formed on a surface of a semiconductor substrate  10  by a trench isolation method. Next, an impurity layer  17   a  is formed in the semiconductor substrate  10  by implanting ions of a P-type impurity as a channel dope. Then, a contact impurity layer  400  (see FIG. 1) is formed in the semiconductor substrate  10  by implanting ions of an N-type impurity.  
     [0038] Next, a dielectric layer  120  that is to become a gate dielectric layer is formed on the surface of the semiconductor substrate  10 . Then, a gate layer (first conductive layer)  140  that is to become word gates  14   a  is deposited on the dielectric layer  120 . The gate layer  140  is composed of doped polysilicon. Then, a first silicon oxide layer  280  is formed on the gate layer  140 . The first silicon oxide layer  280  may be formed by using, for example, a thermal oxidation method or a CVD method. Then, a stopper layer S 100 , which is to be used in a CMP step to be conducted later, is formed over the gate layer  140 . The stopper layer S 100  is composed of a silicon nitride layer.  
     [0039] (2) Then, a resist layer (not shown) is formed. Then, the stopper layer S 100  and the first silicon oxide layer  280  are patterned by using the resist layer as a mask. Thereafter, the gate layer  140  is etched by using the patterned stopper layer S 100  and the first silicon oxide layer  280 . As a result, as shown in FIG. 4, the gate layer  140  is patterned to form gate layers  140   a.    
     [0040]FIG. 5 shows a plan view of the state after the patterning step. By the patterning step, opening sections  160  and  180  are provided in a stacked layered body of the gate layer  140   a , the first silicon oxide layer  280  and the stopper layer S 100  in the memory region  1000 . The opening sections  160  and  180  generally correspond to regions where impurity layers  16  and  18  are formed by an ion implantation to be conducted later. Then, in subsequent steps, side dielectric layers and control gates are formed along side surfaces of the opening sections  160  and  180 .  
     [0041] Then, as shown in FIG. 4, impurity layers  17   b  are formed in the semiconductor substrate  10  by implanting ions of a P-type impurity for preventing punch-through.  
     [0042] (3) Then, the surface of the semiconductor substrate is washed with hydrofluoric acid. As a result, exposed portions of the dielectric layer  120  are removed. Next, as shown in FIG. 6, a bottom silicon oxide layer  220   a  is formed by a thermal oxidation method. The thermally oxidized films are formed between the semiconductor substrate  10  and exposed surfaces of the gate layers  140   a . It is noted that a CVD method may be used to form the bottom silicon oxide layer  220   a.    
     [0043] Then, an annealing treatment is conducted for the bottom silicon oxide layer  220   a . The annealing treatment is conducted in an atmosphere containing NH 3  gas. This pre-treatment makes it easier to evenly deposit a silicon nitride layer  220   b  on the bottom silicon oxide layer  220   a . Then, the silicon nitride layer  220   b  can be formed by a CVD method.  
     [0044] Next, a top silicon oxide layer  220   c  is formed by a CVD method, more specifically, by a high temperature oxidation (HTO) method. The top silicon oxide layer  220   c  may also be formed by using an ISSG (In-situ Steam Generation) treatment. Films that are formed by the ISSG treatment are dense. When films are formed by the ISSG treatment, an annealing treatment for densifying an ONO film to be described later can be omitted.  
     [0045] It is noted that, in the steps described above, if the silicon nitride layer  220   b  and the top silicon oxide layer  220   c  are formed in the same furnace, contamination of the interface thereof that may occur when they are taken outside the furnace can be prevented. By so doing, ONO films with a uniform quality can be formed, and therefore memory cells  100  having stable electric characteristics can be obtained. Also, a washing step that may be conducted to remove contaminants on the interface is not required, such that the number of steps can be reduced.  
     [0046] After forming the layers described above, an annealing treatment with a wet oxidation or an LMP oxidation may be conducted if desired, to densify each of the layers.  
     [0047] In accordance with the present embodiment, the ONO films  220  become second gate dielectric layer  22  and side dielectric layers  24  (see FIG. 2) through a patterning step to be conducted later.  
     [0048] (4) As shown in FIG. 7, a doped polysilicon layer (second conductive layer)  230  is formed over the top silicon oxide layer  220   c . The doped polysilicon layer  230  will be etched later and become conductive layers  40  that compose control gates  20  and  30  (see FIG. 1).  
     [0049] (5) Next, as shown in FIG. 8, the doped polysilicon layer  230  is entirely anisotropically etched. As such, first and second control gates  20  and  30  are formed along the side surfaces of the opening sections  160  and  180  (see FIG. 5) in the memory region  1000 . Here, as indicated in FIG. 8, the anisotropic etching is conducted until the upper surface of the formed control gates  20  and  30  becomes lower than the upper surface of the gate layers  140   a.    
     [0050] Next, as shown in FIG. 8, an N-type impurity is ion-implanted to form impurity layers  19  in the semiconductor substrate  10 .  
     [0051] (6) Next, in the memory region  1000 , a dielectric layer such as a silicon oxide layer or a silicon nitride layer (not shown) is formed over the entire surface. Then, by anisotropically etching the dielectric layer, dielectric layers  152  are left on the control gates  20  and  30 , as shown in FIG. 9. Further, by this etching, dielectric layers deposited on regions where silicide layers are to be formed in succeeding steps are removed, and the semiconductor substrate is exposed.  
     [0052] Next, as shown in FIG. 9, an N-type impurity is ion-implanted to form impurity layers  16  and  18  in the semiconductor substrate  10 .  
     [0053] Next, a metal for forming silicide is deposited over the entire surface thereof. The metal for forming silicide may be, for example, titanium or cobalt. Thereafter, the metal formed over the semiconductor substrate is silicified to form silicide layers  92  on exposed surfaces of the semiconductor substrate. Then, in the memory region  1000 , a second silicon oxide layer  70  is formed over the entire surface thereof. The second silicon oxide layer  70  is formed in a manner to cover the stopper layers S 100 .  
     [0054] (7) As shown in FIG. 10, the second silicon oxide layer  70  is polished by a CMP method until the stopper layers S 100  are exposed, and the second silicon oxide layer  70  is planarized. By this polishing, the second silicon oxide layers  70  are left between the opposing control gates  20  and  30 .  
     [0055] (8) The stopper layers S 100  are removed by a dry etching method. Then, the first silicon oxide layer  280  is removed by, for example a dry etching method.  
     [0056] The dry etching for the stopper layer S 100  may be conducted according to, for example, a CDE (Chemical Dry Etching) method, using a gas containing CF 4  and O 2  as an etching gas, a gas containing CF 4 , and N 2 , a gas containing CF 4 , N 2  and O 2 , or a gas that replaces CF 4  in the aforementioned gas with a fluoride such as NF 3 . In this etching step, the selection ratio between the silicon nitride layer and the silicon oxide layer may preferably be as large as possible.  
     [0057] As a result, upper surfaces of at least the gate layers  140   a  are exposed. Then, a doped polysilicon layer is deposited on the entire surface.  
     [0058] Then, as shown in FIG. 11, patterned resist layers R 100  are formed over the doped polysilicon layer. By patterning the doped polysilicon layer using the resist layers R 100  as a mask, word lines  50  are formed.  
     [0059] In succession, the gate layers  140   a  are etched by using the resist layers R 100  as a mask. By this etching, the gate layers  140   a  without the word lines  50  formed on them are removed. As a result, word gates  14   a  arranged in an array can be formed. The regions where the gate layers  140   a  are removed correspond to regions where P-type impurity layers (element isolation impurity layers)  15  are to be later formed (see FIG. 1).  
     [0060] In this etching step, the conductive layers  40  that form the first and second control gates  20  and  30  remain without being etched because they are covered by the second silicon oxide layers  70 .  
     [0061] Then, a P-type impurity is doped over the entire surface of the semiconductor substrate  10 . As a result, P-type impurity layers (element isolation impurity layers)  15  (see FIG. 1) are formed in regions between the word gates  14   a  in the Y direction. By these P-type impurity layers  15 , the non-volatile semiconductor memory devices  100  are more securely isolated from one another.  
     [0062] By the steps described above, the semiconductor device shown in FIGS. 1 and 2 is manufactured.  
     [0063] Advantages obtained by the manufacturing method are as follows.  
     [0064] In accordance with the present manufacturing method, in the aforementioned step (8), the stopper layer S 100  (see FIG. 10) is removed by dry etching. As a result, assembling work after the manufacturing process can be facilitated. In addition, the removal of the stopper layer S 100  by dry etching is an excellent method in view of miniature processing and waste material treatment.  
     [0065] One embodiment of the present invention has been described so far. However, the present invention is not limited to this embodiment, and many modifications can be made within the scope of the subject matter of the present invention. For example, although a semiconductor substrate in a bulk form is used as a semiconductor layer in the above embodiment, a semiconductor layer composed of a SOI substrate may be used.  
     [0066] The entire disclosure of JP 2002-046196 filed Feb. 22, 2002 is incorporated by reference.