Patent Publication Number: US-6657967-B1

Title: Dummy bit elimination device and coding apparatus for FEC code word

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a dummy bit elimination device for eliminating dummy bits added to an,FEC (Forward Error Correction) code which is transmitted on a submarine cable system. 
     2. Description of the Prior Art 
     In a submarine cable system, a processing device for generating FEC code, for example a Reed-Solomon code, based on an optical signal input adds the dummy bits to the FEC code to simplify the configuration thereof. 
     Adding the dummy bit according to a conventional method, however, increases a bit rate on the communication channel. A transmission loss is increased in accordance with the increased bit rate. Thus, for example, it was required to compensate the loss by increasing a number of repeaters. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a dummy bit elimination device for eliminating the dummy bit added to the FEC code that is transmitted on the submarine cable system. 
     According to a first aspect of the present invention, there is provided a dummy bit elimination device included in a coding apparatus, which device comprises: means for eliminating only dummy bits from FEC code supplied thereto so as to output only the FEC Code; wherein the coding apparatus comprises: a means for converting an optical signal into an electrical signal data; a demultiplexer for demultiplexing the data; a coding means for generating an FEC (Forward Error Correction) code having the demultiplexed data and additional parities, and dummy bits for each of the demultiplexed data; a multiplexer for multiplexing inputs thereto; and a means for converting an output of the multiplexer into an optical signal; and wherein the dummy bit elimination device and an output of the dummy bit elimination device are fed to the multiplexer. 
     According to a second aspect of the present invention, there is provided a coding apparatus, which apparatus comprises: a means for converting an optical signal into an electric signal data; a demultiplexer for demultiplexing the data; a coding means for generating an FEC code having the demultiplexed data and additional parities, and dummy bits for each of demultiplexed data; a dummy bit eliminating means for eliminating only the dummy bits from outputs of the coding means so as to output only the FEC codes; a multiplexer for multiplexing outputs of the dummy bit eliminating means; and a means for converting an output of the multiplexer into an optical signal. 
     The coding apparatus may be combined with a submarine cable system. 
     According to a third aspect of the present invention, there is provided a coding apparatus which comprises: a coding means for continuously outputting an FEC code word having an input data and additional parities, and dummy bits to simplify an FEC coding; and a dummy bit eliminating means for eliminating only the dummy bits from a continuity consisting of the FEC code and the dummy bits so as to output only the FEC code. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more fully understood from the following detailed description with reference to the accompanying drawings in which: 
     FIG. 1 is a block diagram showing a coding apparatus configuration including a dummy bit elimination device for the FEC code word according to the present invention; 
     FIG. 2 is a diagram showing the output format of demultiplexer  2  in FIG. 1; 
     FIG. 3 is a diagram showing the output format of FEC coder  3  in FIG. 1; 
     FIG. 4 is a diagram showing the output format of multiplexer  5  in case that there is not provided a converter  4  shown in FIG. 1; 
     FIG. 5 is a diagram showing the output format of converter  4  in FIG. 1; and 
     FIG. 6 is a diagram showing the output format of multiplexer  5  in case that there is provided a converter  4  shown in FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram showing a coding apparatus configuration including a dummy bit elimination including a dummy bit elimination device according to an embodiment of the present invention. A 2.4G optical signal is fed into 2.5G optical receiver (2.5G OR)  1  and is output from 2.6G optical sender (2.6G OS)  6  as a 2.6G optical signal through demultiplexer (DMUX)  2 , FEC coder (FEC COD)  3 , converter  4  and multiplexer (MUX)  5 . Clock signals, for activating the above circuits, generated at 2.5G optical receiver  1  and divided at 1/N divider  7  are supplied to FEC coder  3 , converter  4 , multiplexer  5  and 2.6G optical sender  6  through phase locked loops  8  and  9  (PLL 1  and PLL 20 ). 
     The 2.4G optical signal is converted at 2.5G optical receiver  1  into STM 16  signal in a form of an electric signal and is then fed to demultiplexer  2 . Demulitiplexer  2  separates STM 16  signal into STM 1  signals a as many as 16 and feeds them to FEC coder  3  in parallel. 
     FIG. 2 shows STM 1  signals a as many as 16, each of which consists of 238 bytes data. 
     Each STM 1  signal a is encoded at FEC coder  3  into an FEC COD output signal b which includes overhead bit OH, parity bits which form a part of the FEC code, and dummy bits as shown in FIG.  3 . 
     According to the conventional method, FEC COD output signal b is fed into multiplexer  5  and become a multiplexed signal in multiplexer  5 . FIG. 4 shows the multiplexed signal generated at mulitiplexer  5 . In this case, the bit rate on the communication channel may be increased due to the dummy bits. 
     According to the embodiment, the FEC COD output signal b is fed into converter  4  for eliminating the dummy bits. Converter  4  outputs signal c not including the additional dummy bits as shown in FIG.  5 . Signal c consists of overhead bits, data and parities but does not include the dummy bits as shown in the figure. 
     Signal c is processed at multiplexer  5  into multiplexed signal d shown in FIG.  6 . 
     Multiplexed signal d is converted into the optical signal at 2.6G optical sender  6  and is sent out on the communication channel. 155 MHz clock signal extracted at 2.5G optical receiver  1  is fed to 1/N divider  7  and is divided into a long cycle signal of 81 KHz. 81 KHz signal is supplied to PLL  8  (PLL 1 ). PLL  8  generates write clock e and read clock f of 166 MHz for use in FEC coder  3  for FEC process. 
     PLL  8  (PLL 1 ) also sends 2.6G multiplexing clock g to PLL  9  (PLL 2 ). PLL  9  regenerates 166 MHz clock from 2.6G clock g and feeds write clock h and read clock i to converter  4  for eliminating the dummy bits. A frequency of clock h is determined lower than that of clock g. 
     PLL  9  (PLL 2 ) also supplies multiplexing clock j which synchronizes with clock i to multiplexer  5  and 2.6G optical sender  6 . Thus, the multiplexed signal according to the present invention, from which the dummy bits are eliminated, may be generated. 
     Converter  4  and PLL  9  (PLL 2 ) may be fabricated in one package IC. The IC may not be employed when the signal that includes the dummy bits is transmitted. In this case, signal b is directly fed into multiplexer  5  and 2.6G multiplexing clock g output from PLL  8  (PLL 1 ) is directly fed to multiplexer  5  and 2.6G optical sender  6 . A configuration to transmit dummy bits and another configuration not to transmit dummy bits may be alternated with a switching means. 
     According to the present invention, it is possible to eliminate dummy bits which are additionally output from the simplified FEC processor as explained above. Thus, the bit rate on the communication channel can be prevented from increasing. 
     In addition, according to the present invention, it is possible to generate the signal having no dummy bits while using the simplified FEC processor. Thus, the circuit scale of the whole coding apparatus for generating the signal having no dummy bits can be reduced. 
     Further, according to the present invention, the converter and PLL 2  may be simply inserted into the conventional FEC processor. Thus, the conventional FEC processor may be appropriable 
     Still further, according to the present invention, it is possible to easily alternate the configuration to transmit dummy bits and the configuration not to transmit dummy bits. 
     Having explained preferred embodiments of the present invention, it will now become apparent to those of ordinary skill in the art that other embodiments incorporated these concepts may be used. Accordingly, it is submitted that the invention should not be limited to the explained embodiments but rather should be limited only by the spirit and scope of the appended claims.