Patent Publication Number: US-2023154989-A1

Title: Methods of Forming Conductive Pipes Between Neighboring Features, and Integrated Assemblies Having Conductive Pipes Between Neighboring Features

Description:
TECHNICAL FIELD 
     Integrated assemblies and methods of forming integrated assemblies. Methods of forming conductive pipes between neighboring features. Integrated assemblies having conductive pipes between neighboring features. 
     BACKGROUND 
     Patterned features are commonly utilized in integrated assemblies. In some example applications, the patterned features may be conductive features utilized as interconnects, and/or utilized to bring suitable voltage (e.g., VDD, VSS, etc.) to integrated circuitry. It is becoming increasing difficult to fabricate patterned features with increasing levels of integration due to the tight spacings available for the patterned features. It would be desirable to develop new methods for forming patterned features and to develop new architectures utilizing the patterned features. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 - 1 B  are views of a region of an example integrated assembly.  FIG.  1    is a diagrammatic top-down view along the cross-section  1 - 1  of  FIGS.  1 A and  1 B .  FIGS.  1 A and  1 B  are diagrammatic cross-sectional side views along the lines A-A and B-B, respectively, of  FIG.  1   . 
         FIGS.  2 - 5    are views of a region of an example integrated assembly at sequential process stages of an example method.  FIGS.  2 - 5    are diagrammatic top-down views.  FIGS.  2 A- 5 A  are diagrammatic cross-sectional side views along the lines A-A of  FIGS.  2 - 5   , respectively. 
         FIG.  6    is a diagrammatic cross-sectional side view of a region of an example integrated assembly. 
         FIGS.  7 - 9    are diagrammatic cross-sectional side views of a region of an example integrated assembly at sequential process stages of an example method. 
         FIGS.  10 - 13    are views of a region of an example integrated assembly at sequential process stages of an example method.  FIGS.  10 - 13    are diagrammatic top-down views.  FIGS.  10 A- 13 A  are diagrammatic cross-sectional side views along the lines A-A of  FIGS.  10 - 13   , respectively.  FIGS.  10 B- 12 B  are diagrammatic cross-sectional side views along the lines B-B of  FIGS.  10 - 12   , respectively. 
         FIGS.  14 - 16    are diagrammatic top-down views of a region of an example integrated assembly at sequential process stages of an example method. 
         FIGS.  17 - 20    are diagrammatic top-down views of a region of an example integrated assembly at sequential process stages of an example method. 
         FIGS.  21 - 21 B  are views of a region of an example integrated assembly.  FIG.  21    is a diagrammatic cross-sectional top-down view along the lines C-C of  FIGS.  21 A and  21 B .  FIGS.  21 A and  21 B  are diagrammatic cross-sectional side views along the lines A-A and B-B, respectively, of  FIG.  21   . 
         FIG.  22 A  is a diagrammatic top-down view of a region of an example prior art integrated circuit. 
         FIG.  22 B  is a schematic diagram of the example prior art integrated circuit of  FIG.  22 A . 
         FIG.  23 A  is a diagrammatic top-down view of a region of an example embodiment integrated circuit which may comprise the prior art arrangement of  FIG.  22 B . 
         FIG.  23 B  is a duplicate of the schematic diagram of  FIG.  22 B . 
         FIG.  24    is a diagrammatic cross-sectional top-down view of an example integrated assembly. 
         FIG.  25    is a diagrammatic cross-sectional top-down view of an example integrated assembly. 
     
    
    
     DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS 
     Some embodiments include methods of forming conductive pipes (linear structures) between features of an integrated assembly. Some embodiments include integrated assemblies comprising conductive pipes. Some embodiments include logic circuits (e.g., 2NFET, 2PFET circuits; where NFET refers to a field effect transistor with n-type source/drain regions and PFET refers to a field effect transistor with p-type source/drain regions). Example embodiments are described with reference to  FIGS.  1 - 25   . 
     Referring to  FIGS.  1 - 1 B , an integrated assembly  10  includes a pair of features  12  and  14 . The features are shown to be linear structures, with such linear structures extending along a first direction corresponding to an illustrated x-axis direction. The linear features may be straight (as shown), wavy, curved, etc., and are substantially parallel to one another. The term “substantially parallel” means parallel to within reasonable tolerances of fabrication and measurement. 
     The features  12  and  14  may be supported by an underlying semiconductor base (not shown). The base may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. 
     The features  12  and  14  are spaced from one another by an intervening space  16 . In the illustrated embodiment, the space  16  has about a same width W along an illustrated y-axis as the features  12  and  14 . Accordingly, the features  12  and  14  may be considered to be formed along (on) a pitch P with the width of the space  16  being about ½ P. 
     The features  12  and  14  comprise a material  18 . The material  18  may comprise any suitable composition(s). Although the material  18  shown to be homogeneous, in other embodiments the material  18  may be heterogeneous and may comprise two or more discrete compositions. Further, although the features  12  and  14  are shown comprising the same material  18  as one another, in other embodiments the features may comprise different compositions relative to one another. 
     The material  18  may be conductive, insulative, semiconductive, etc. If the material  18  includes two or more discrete compositions, such compositions may have different conductivities relative to one another. For instance, in some embodiments one of the compositions may be conductive while another is insulative, etc. 
     A conductive pipe (structure, feature, line, etc.)  20  is within the space  16 . The conductive pipe  20  is shown in dashed-line (phantom) view in  FIG.  1    to indicate that it is beneath other materials. 
     The conductive pipe comprises a conductive material  22 . The conductive material  22  may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, tantalum, cobalt, molybdenum, nickel, platinum, ruthenium, copper, aluminum, palladium, silver, gold, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive material  22  may comprise, consist essentially of, or consist of one or more of metal nitride, metal carbide, metal silicide and metal boride. In some embodiments, the conductive material  22  may comprise a tungsten core which is laterally surrounded by a layer comprising titanium nitride. 
     The conductive pipe  20  is substantially parallel to the features  12  and  14 , and in the shown embodiment is about halfway between the features  12  and  14  within the intervening space  16 . 
     A first conductive post (block, structure, etc.)  24  is along one side of the pipe  20 , and a second conductive post (block, structure, etc.)  26  is along an opposing second side of the pipe  20 . The posts  20  and  24  comprise the same composition  22  as the pipe  20 . 
     A first dielectric material  28  is within the intervening space  16 , under the conductive pipe  20 , and along sidewalls of the features  12  and  14 . The first dielectric material  28  may comprise any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon nitride, silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. 
     A second dielectric material  30  is within the intervening space  16 , and is over the first dielectric material  28 . The second dielectric material  30  is over and under the conductive pipe  20 , and in the shown embodiment is also along sidewalls of the conductive pipe  20 . The second dielectric material  30  may be less dense than the first dielectric material  28 . The second dielectric material  30  may comprise any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon nitride, silicon dioxide, porous silicon dioxide, carbon-doped silicon oxide, boron-doped silicon dioxide, silicon oxynitride, etc. 
     In some embodiments, the first and second dielectric materials  28  and  30  may both comprise silicon nitride, with the second dielectric material  30  being less dense than the first dielectric material. In some embodiments, the first and second dielectric materials  28  and  30  may both comprise silicon dioxide, with the second dielectric material being less dense than the first dielectric material. In some embodiments, the first dielectric material  28  may comprise silicon nitride, and the second dielectric material  30  may comprise silicon dioxide. In some embodiments, the first dielectric material  28  may comprise silicon nitride, and the second dielectric material  30  may comprise silicon oxynitride. 
     A third dielectric material  32  is over the second dielectric material  30 . The third dielectric material may be denser than the second dielectric material  30 , and may comprise any of the compositions described above as being suitable for the first dielectric material  28 . The first and third dielectric materials  28  and  32  may comprise a same composition as one another, or may comprise different compositions relative to one another. 
     In the shown embodiment, a planarized surface  33  extends across the second and third dielectric materials  30  and  32 . The planarized surface  33  is spaced from upper surfaces  17  of the features  12  and  14  by at least the second dielectric material  30 , and in the shown embodiment is spaced from such surfaces by both the second dielectric material  30  and the first dielectric material  28 . 
     An advantage of the configuration of  FIGS.  1 - 1 B  is that the features  12  and  14  may be formed on a very tight pitch P (e.g., a pitch corresponding to the minimum pitch achievable by a fabrication process), and the pipe  20  may be formed within the space between such features. Accordingly, the conductive pipe  20  may be packed into tight spaces of an integrated assembly and may provide a conductive interconnect within such tight spaces. 
     The assembly of  FIGS.  1 - 1 B  may be formed with any suitable processing. Example processing is described with reference to  FIGS.  2 - 5   . 
     Referring to  FIGS.  2  and  2 A , the assembly  10  is shown to comprise the features  12  and  14  as fins extending upwardly from a pillar  34  of material  18 . In some embodiments, the material  18  of  FIGS.  2  and  2 A  may be semiconductor material. The semiconductor material may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon, germanium, III/V semiconductor material (e.g., gallium phosphide), semiconductor oxide, etc.; with the term III/V semiconductor material referring to semiconductor materials comprising elements selected from groups III and V of the periodic table (with groups III and V being old nomenclature, and now being referred to as groups  13  and  15 ). In some embodiments, the semiconductor material  18  of  FIGS.  2  and  2 A  may comprise, consist essentially of, or consist of silicon. The silicon may be in any suitable crystalline form (e.g., monocrystalline, polycrystalline, amorphous, etc.). 
     The fins  12  and  14  may be referred to as a first fin and a second fin, respectively. The fins may have regions of any suitable conductivity type in embodiments in which the material  18  is semiconductor material. For instance, in some embodiments the fins  12  and  14  may comprise regions which are p-type (e.g., may comprise regions having silicon which is conductively doped with boron), and/or may comprise regions which are n-type (e.g., may comprise regions having silicon which is conductively doped with one or both of phosphorus and arsenic). In some embodiments, the fin  12  may include first regions having a first conductivity type and the fin  14  may comprise second regions having a second conductivity type, with the second conductivity type being different than the first conductivity type (e.g., one of the first and second conductivity types may be p-type while the other is n-type). 
     The fins  12  and  14  (i.e., the first and second features  12  and  14 ) are spaced from one another by the intervening space  16 , and extend substantially parallel to one another along the illustrated x-axis direction. 
     Referring to  FIGS.  3  and  3 A , the dielectric material  28  is formed within the intervening space  16 . In the illustrated embodiment, the dielectric material  28  extends conformally along outer surfaces of the features  12  and  14 , and narrows the intervening space  16 . The dielectric material  28  may be referred to as a first dielectric material. 
     The second dielectric material  30  is formed over the first dielectric material  28 , and within the space  16  narrowed by the first dielectric material. The second dielectric material  30  may have a lower density than the first dielectric material  28 , and accordingly a void  36  may be generated within the material  30  during the deposition of the material  30 . Specifically, a top region  37  of the second material  30  may pinch off at a top of the intervening space  16  to preclude the material  30  from completely filling the space, and to thereby create the void  36 . 
     In the illustrated embodiment, the void  36  corresponds to a tube (as shown relative to the top-down view of  FIG.  3   ), with such tube extending substantially parallel to the first and second features  12  and  14 . The tube  36 , and the features  12  and  14 , are shown in dashed-line view in  FIG.  3    to indicate that the tube and the features are beneath other materials. 
     The tube  36  has a first end  39  and an opposing second end  41 . 
     A third dielectric material  32  is formed over the second dielectric material  30 . The third dielectric material  32  may be denser than the second dielectric material  30 . In some embodiments, the third dielectric material  32  may be tailored to effectively seal the void within the second dielectric material  30 . For instance, the third dielectric material  32  may be provided to have high conformality so that it may effectively seal the void  32  in the second dielectric material  30  to the extent that additional sealing is needed or desired. 
     In some embodiments, the dielectric materials  28 ,  30  and  32  may all comprise a same composition (e.g., silicon dioxide or silicon nitride), but the deposition conditions may be varied so that the middle dielectric material  30  has a lower density than the upper and lower dielectric materials  28  and  32 . In some embodiments, the middle dielectric material  30  may comprise a different composition than the upper and lower dielectric materials  28  and  32 . For instance, the upper and lower dielectric materials  28  and  32  may both comprise silicon nitride while the middle dielectric material comprises silicon dioxide. Alternatively, the upper and lower dielectric materials  28  and  32  may both comprise silicon dioxide while the middle dielectric material comprises silicon nitride. As another example, the upper and lower dielectric materials  28  and  32  may both comprise silicon nitride while the middle dielectric material  30  comprises silicon oxynitride. 
     In some embodiments, the density of the middle dielectric material  30  may be influenced by incorporating one or more dopants (and/or other additives) into the material. For instance, the middle dielectric material  30  may comprise carbon-doped silicon dioxide, boron-doped silicon dioxide, etc. 
     The upper and lower dielectric materials  28  and  32  may comprise a same composition as one another, or may comprise different compositions relative to one another. 
     The dielectric materials  28 ,  30  and  32  may be formed with any suitable processing, including, for example, atomic layer deposition (ALD) and/or chemical vapor deposition (CVD), etc. 
     In some embodiments, one or both of the dielectric materials  28  and  32  may be omitted. 
       FIG.  3 A  shows the planarized surface  33  extending across the third dielectric material  32 . In other embodiments the planarized surface  33  may be formed to extend across regions of both the third dielectric material  32  and the second dielectric material  30 , as shown in  FIG.  1 A . 
     Referring to  FIGS.  4  and  4 A , openings  38  are formed along the ends  39  and  41  of the tube  36 . The openings may be utilized to allow access to the ends  39  and  41  of the tube  36 . Although openings are shown being formed along both of the opposing ends  39  and  41  of the tube  36 , in other embodiments an opening be formed only along one of the ends of the tube. 
     Referring to  FIGS.  5  and  5 A , the conductive material  22  is formed within the openings  38 , and is flowed through such openings into the tube  36 . In the illustrated embodiment, the conductive material  22  fills the tube  36  to form the conductive pipe  20  described above with reference to  FIGS.  1 - 1 B . The material  22  may comprise any of the compositions described above with reference to  FIGS.  1 - 1 B . The material  22  may be formed with any suitable processing, including, for example, one or more of ALD, CVD and physical vapor deposition (PVD). 
     In some embodiments, the material  22  may comprise one or more metals and/or metal-containing compositions. For instance, in some embodiments the material  22  may comprise a liner of metal nitride (e.g., titanium nitride, tungsten nitride, etc.) which lines the tube  36 , and may comprise a metal core material within the lined tube. The metal core material may, for example, comprise, consist essentially of, or consist of tungsten, titanium, etc. 
     In some embodiments, the formation of the conductive material  22  within the tube  36  may be considered to be a method for patterning the conductive pipe  20  within the region  16  between the features  12  and  14 . The illustrated conductive pipe  20  is substantially parallel to the first and second features  12  and  14 . 
     Although the dielectric materials  28 ,  30  and  32  are shown to comprise homogeneous compositions in the embodiments of  FIGS.  1 - 5   , in other embodiments one or more of such other materials may comprise a laminate of two or more compositions. For instance,  FIG.  6    shows an enlarged view of the space  16  between the features  12  and  14  at a processing stage of similar to that of  FIG.  5 A  in an example embodiment in which the dielectric materials  28  and  30  each comprise laminates of two or more compositions. Specifically, the dielectric material  28  comprises a laminate of the compositions  28   a ,  28   b  and  28   c , and the dielectric material  30  comprises a laminate of the compositions  30   a  and  30   b . The laminates may comprise abrupt boundaries between adjacent compositions and/or may comprise gradients between adjacent compositions. 
     An advantage of utilizing laminate configurations for one or more of the dielectric materials may be that such can enable the dielectric materials to be tailored for particular applications. For instance, the laminate configuration of the dielectric material  30  may enable the cross-sectional shape of the void  36  to be tailored for particular applications. 
     The compositions  28   a - c  may comprise any of the substances described above as being suitable for the dielectric material  28 , and the compositions  30   a  and  30   b  may comprise any of the substances described above as being suitable for the dielectric material  30 . 
     In some embodiments, one or more etchants may be flowed through the openings  38  ( FIG.  4   ) and into the tube  36  to widen the tube prior to formation of the conductive material  22  ( FIG.  5   ) within such tube. For instance,  FIG.  7    shows an enlarged view of the space  16  between the features  12  and  14  at the processing stage of  FIGS.  4  and  4 A .  FIG.  8    shows a processing stage subsequent to that of  FIG.  7   , and shows the tube  36  widened with one or more etchants flowed into the tube through the openings  38  ( FIG.  4   ). If the dielectric material  30  comprises silicon dioxide, the etchant(s) may include hydrochloric acid. If the dielectric material  30  comprises silicon nitride, the etchant(s) may include phosphoric acid. 
     The original location of the tube  36  is shown with a dashed line  43  in  FIG.  8    so that the reader may readily understand that the tube  36  has been widened at the processing stage of  FIG.  8    relative to that of  FIG.  7   . 
     Referring to  FIG.  9   , the conductive material  22  is formed within the widened tube  36  to form a conductive pipe  20  of the type described above with reference to  FIG.  5   . 
     The embodiment of  FIGS.  2 - 5    shows the dielectric materials  28 ,  30  and  32  formed along the entire length of the space  16  between the features  12  and  14 . In other embodiments, the dielectric materials may be formed only along segments of such space so that the resulting tube  36  extends only along segments of the space, rather than extending the full length of the space. An example of such other embodiments is described with reference to  FIGS.  10 - 13   . 
     Referring to  FIGS.  10 - 10 B , the assembly  10  is shown at a process stage similar to that of  FIGS.  3  and  3 A , except that the space  16  between the features  12  and  14  is subdivided amongst three segments  44 ,  46  and  48 . The segments  44  and  48  comprise the dielectric materials  28 ,  30  and  32  described above with reference to  FIGS.  3  and  3 A . 
     The segment  46  comprises dielectric materials  40  and  42 . The dielectric materials  40  and  42  may comprise any suitable composition(s). In some embodiments, the dielectric material  40  may be identical to the dielectric material  28 , and the dielectric material  42  may be identical to the dielectric material  32 . In some embodiments, the dielectric materials  40  and  42  may be replaced with a single dielectric material. 
     The less-dense (soft) material  30  is omitted from the segment  46 , and accordingly the void  36  does not formed along the segment  46 . The configuration of  FIG.  10    may be considered to have the segments  44  and  48  corresponding to first regions  50  of the intervening space  16 , and to have the segment  46  corresponding to a second region  52  of the intervening space. Tubes  36  extend across the first regions  50  of the intervening space  16 , and do not extend across the second region  52  of the intervening space. In some items, the tube  36  within the segment  44  of the intervening space  16  may be referred to as a first tube  51 , and the tube within the third segment  48  may be referred to as a second tube  53 . 
     Referring to  FIGS.  11 - 11 B , the openings  38  are formed with processing analogous to that described above with reference to  FIGS.  4  and  4 A . 
     Referring to  FIGS.  12 - 12 B , the conductive material  22  is formed within the openings  38  and the tubes  51  and  53  with processing analogous to that described above with reference to  FIGS.  5  and  5 A . 
     The conductive material  22  within the tube  51  forms a first conductive pipe  20   a , and the conductive material  22  within the tube  53  forms a second conductive pipe  20   b.    
     The conductive material  22  within the openings  38  forms blocks (posts)  24  and  26  of the type described above with reference to  FIG.  1   . 
     In some embodiments, the features  12  and  14  may be considered to extend a first distance Di along the x-axis direction, and the pipes  20   a  and  20   b  may each be considered to extend a second distance D 2  along the x-axis direction; with the second distance being less than the first distance. In the illustrated embodiment, the second distance D 2  is less than one-half of the first distance D 2 . In the shown embodiment, the pipes  20   a  and  20   b  extend about the same distance as one another (i.e., are about the same length as one another). In other embodiments the pipe  20   a  may be a different length than the pipe  20   b.    
     In the illustrated embodiment, the first and second conductive pipes  20   a  and  20   b  are spaced from one another by an intervening gap corresponding to the segment  46 . The intervening gap  46  may be considered to be an insulative region  46  between the first and second conductive pipes  20   a  and  20   b . The pipe  20   a  may be considered to have a first terminal end  55   a  on one side of the insulative region  46 , and the pipe  20   b  may be considered to have a second terminal end  55   b  on an opposing second side of the insulative region  46 . 
     In some embodiments, conductive interconnects may be formed to extend downwardly to one or both of the terminal ends  55   a  and  55   b . For instance,  FIGS.  13  and  13 A  show electrical interconnects  54  extending downwardly through the insulative materials  28 ,  30  and  32  to be electrically coupled with the terminal ends  55   a  and  55   b  of the conductive pipes  20   a  and  20   b.    
     The electrical interconnects  54  may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the electrical interconnects  54  may comprise the conductive material  22  (i.e., the same conductive material as is utilized in the blocks  24  and  26 , and as is utilized in the pipes  20   a  and  20   b ). 
     The electrical interconnects  54  may be coupled with other circuitry (not shown). Such other circuitry may be at any suitable elevational level, and in some embodiments may be at an elevational level above the features  12  and  14 . 
     In some embodiments, the features  12  and  14  may be comprised of segments which are spaced by intervening gaps, and it may be desired to form conductive structures which are continuous across such intervening gaps. Methodology described in  FIGS.  14 - 20    may be utilized to fabricate such conductive structures. 
     Referring to  FIG.  14   , the construction  10  comprises a configuration in which the feature  12  comprises a pair segments  12   a  and  12   b , and in which the feature  14  comprises a pair of segments  14   a  and  14   b . The segments  12   a  and  14   a  are spaced from the segments  12   b  and  14   b  by an intervening gap  56 . 
     Referring to  FIG.  15   , conductive pipes  20   a  and  20   b  are formed between the features  12  and  14  with processing analogous to that described above with reference to  FIGS.  2 - 5   . Specifically, the conductive pipe  20   a  is formed between the features  12   a  and  14   a , and the conductive pipe  20   b  is formed between the features  12   b  and  14   b . The insulative material  32  is shown to extend across the features  12   a ,  12   b ,  14   a  and  14   b , and to extend across the pipes  20   a  and  20   b , in a configuration analogous to that of  FIGS.  5  and  5 A . The pipes  20   a  and  20   b  are spaced from one another by the intervening gap  56 . 
     Referring to  FIG.  16   , conductive material  58  is formed within the intervening gap  56 , and is patterned to conductively couple the first conductive pipe  20   a  to the second conductive pipe  20   b . In some embodiments, the conductive material  58  may be considered to be patterned as a feature (structure)  59  which bridges across the gap  56  to electrically couple the first and second conductive pipes  20   a  and  20   b  with one another. 
     The conductive material  58  may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments the conductive material  58  may comprise a same composition as the conductive material  22 , and in other embodiments the conductive material  58  may comprise a different composition than the conductive material  22 . 
     Referring to  FIG.  17   , the assembly  10  shown at a process stage analogous to that of  FIG.  2   , with the features  12  and  14  extending along the x-axis direction. 
     Referring to  FIG.  18   , the tube  36  is formed with processing analogous to that described above reference to  FIGS.  3  and  3 A . 
     Referring to  FIG.  19   , a patterned chop subdivides the feature  12  into first and second structures  12   a  and  12   b , subdivides the feature  14  into first and second structures  14   a  and  14   b , and subdivides the tube  36  into first and second structures  36   a  and  36   b  . The intervening gap  56  is thus formed to extend between the first structures ( 12   a ,  14   a  and  36   a ) and the second structures ( 12   b ,  14   b  and  36   b ). 
     Referring to  FIG.  20   , the bridging structure  59  is formed to extend across the intervening gap  56 , and to couple the first tube  36   a  with the second tube  36   b . The bridging structure  59  comprises the conductive material  58 , and such conductive material may be flowed into the tubes  36   a  and  36   b  to form the pipes  20   a  and  20   b  extending outwardly from the bridging structure  59 . In some embodiments, the conductive material  58  comprises both metal nitride (e.g., titanium nitride, tungsten nitride, etc.) and relatively pure metal (e.g., tungsten). The metal nitride may be flowed into the tubes  36   a  and  36   b  to line the tubes, and then the relatively pure metal may be flowed into the lined tubes to form a metal core surrounded by the metal nitride liner. 
     In some embodiments, the structures described above may be incorporated into integrated circuitry as described with reference to  FIGS.  21 - 21 B . 
     The assembly  10  of  FIGS.  21 - 21 B  includes the features  12  and  14  configured as fins of semiconductor material  18 , with such fins extending upwardly from a pillar  34  of the semiconductor material. Stippling is provided within the semiconductor material  18  to assist the reader in identifying the semiconductor material. 
     The semiconductor material  18  may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon, germanium, III/V semiconductor material (e.g., gallium phosphide), semiconductor oxide, etc.; with the term III/V semiconductor material referring to semiconductor materials comprising elements selected from groups III and V of the periodic table (with groups III and V being old nomenclature, and now being referred to as groups  13  and  15 ). For instance, in some embodiments the semiconductor material  18  may comprise, consist essentially of, or consist of silicon. The silicon may be in any suitable crystalline form, and in some embodiments may correspond to monocrystalline silicon. 
     The fin  12  is shown to include p-type source/drain regions S/D. The p-type regions of the fin  12  may comprise silicon doped with boron to a concentration of at least about 10 20  atoms/cm 3 . 
     The fin  14  is shown to include n-type source/drain regions S/D. The n-type regions of the fin  14  may comprise silicon doped with one or both of phosphorus and arsenic to a total concentration of at least about 10 20  atoms/cm 3 . 
     The source/drain regions S/D along the first fin  12  may be referred to as first source/drain regions, and the source/drain regions S/D along the second fin  14  may be referred to as second source/drain regions. 
     Gating structures  60   a  and  60   b  extend across the fins  12  and  14 , with the gating structures extending along the illustrated y-axis direction. One of the gating structures  60   a  and  60   b  may be referred to as a first gating structure, and the other may be referred to as a second gating structure. 
     The gating structures comprise conductive gating materials  62   a - c . The gating materials  62   a - c  may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, two or more of the gating materials  62   a - c  may be compositionally the same as one another, and in other embodiments two or more of the gating materials may be compositionally different relative to one another. 
     Insulative material (gate dielectric material)  62  is along outer surfaces of the fins  12  and  14 . The insulative material  62  may comprise any suitable composition(s), and in some embodiments may comprise one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, hafnium oxide, etc. 
     The fin  12  includes channel regions  64   a  and  64   b  between the illustrated source/drain regions S/D along such fin, and the fin  14  includes channel regions  66   a  and  66   b  between the illustrated source/drain regions S/D along such fin. The channel regions  64   a  and  66   a  are operatively proximate the gating structure  60   a  , and the channel regions  64   b  and  66   b  are operatively proximate the gating structure  60   b . The term “operatively proximate” refers to a gating structure in appropriate proximity to a channel region such that an electric field may be selectively induced on the channel region by electrical activation/deactivation of the gating structure. The selective inducement of electric field on the channel region may be utilized achieve controlled coupling/decoupling of source/drains S/D on opposing sides of the channel region. 
     The channel regions  64  and  66  may be appropriately doped to achieve desired threshold voltages. 
     Circuitry analogous to that of  FIG.  21 - 21 B  may be utilized in logic devices. 
       FIGS.  22 A and  22 B  illustrate an example prior art logic device comprising two NFET devices  68   a  and  68   b  (labeled as transistors T 1  and T 2 ), and two PFET devices  70   a  and  70   b  (labeled as transistors T 3  and T 4 ). The illustrated device also includes a capacitor  69 . 
       FIG.  22 B  is a schematic illustration of the prior art device, and  FIG.  22 A  is a diagrammatic illustration of a region of a semiconductor assembly  72  comprising the device. 
     The diagrammatic illustration of  FIG.  22 A  shows that the assembly may be considered to comprise six tracks (labeled Tracks 1-6). The tracks are on a pitch Pi which may be a minimum lithographic pitch of a fabrication process. The outer tracks (Track-1 and Track-6) comprise conductive structures (powerlines, wiring lines)  74  and  76  which provide VDD and VSS to the device (i.e., which are coupled with reference nodes at VDD and VSS). 
     In some embodiments, a logic device analogous to that of  FIGS.  22 A and  22 B  may be formed utilizing processing in accordance with one or more of the embodiments of  FIGS.  1 - 21    to achieve a higher degree of integration as compared to the prior art device of  FIG.  22 A . 
       FIG.  23 A  shows an assembly  10  comprising an example logic cell  78  having two NFET transistors  68   a  and  68   b , and two PFET transistors  70   a  and  70   b  . The logic cell  78  may be referred to as a two-NFET-two-PFET device. 
       FIG.  23 B  schematically illustrates the two-NFET-two-PFET logic cell  78 . The schematic illustration of  FIG.  23 B  is identical to that of  FIG.  22 B . 
     The six tracks (Tracks 1-6) described above relative to  FIG.  22 A  are shown along the right side of the logic cell  78  of  FIG.  23 A . However, the logic cell primarily utilizes only four of such six tracks. Accordingly, four tracks  77  are shown along the left side of  FIG.  23 A , with such four tracks being identified as a First Track, Second Track, Third Track and Fourth Track. The four tracks  77  extend along a first direction which corresponds to an illustrated x-axis direction. The four tracks  77  are spaced from one another by intervening spaces  79 . The tracks and spaces ( 77 ,  79 ) alternate with one another along a second direction (the illustrated y-axis direction). The second direction (y-axis direction) is shown to be orthogonal to the first direction (x-axis direction). In some embodiments, the second direction may be substantially orthogonal to the first direction, with the term “substantially orthogonal” meaning orthogonal to within reasonable tolerances of fabrication and measurement. 
     The tracks  77  and the intervening spaces  79  are on a pitch P 1 . Such pitch may be a minimum lithographic pitch of a fabrication process. 
     A first semiconductor-containing feature  80  is along the First Track, and a second semiconductor-containing feature  82  is along the Fourth Track. The first semiconductor-containing feature  80  is paired with an adjacent semiconductor-containing feature  81 , and the second semiconductor feature  82  is paired with an adjacent semiconductor-containing feature  83 . The features  80 - 83  may correspond to semiconductor fins analogous to the fins  12  and  14  of  FIG.  21   . In the illustrated embodiment, the fins  80  and  81  are paired with one another, and a conductive pipe  20   a  is formed between such fins. Also, the fins  82  and  83  are paired with one another, and a conductive pipe  20   b  is formed between such fins. The conductive pipes  20   a  and  20   b  may be formed with processing analogous to that described above with reference to  FIGS.  2 - 5   . 
     The fins  80  and  81  may be considered to be spaced from one another by a first gap  16   a , and the fins  82  and  83  may be considered to be spaced from one another by a second gap  16   b . The conductive pipes  20   a  and  20   b  are within the first and second gaps, respectively. The conductive pipe  20   a  is substantially parallel to the fins  80  and  81 , and the conductive pipe  20   b  is substantially parallel to the fins  82  and  83 . 
     In the illustrated embodiment, the fins  80 - 83  are all formed on the pitch P 1 , and the conductive pipes  20   a  and  20   b  are not on such pitch. Instead, the conductive pipe  20   a  is spaced from the fin  80  by a first distance D 1  which is less than or equal to about one-half of the pitch P 1 , and the conductive pipe  20   b  is spaced from the fin  82  by a second distance D 2  which is also less than or equal to about one-half of the pitch P 1 . 
     In some embodiments, the distances D 1  and D 2  may be the same as one another, and in other embodiments such distances may be different from one another. In some embodiments, the first and second distances D 1  and D 2  may be less than or equal to about one-fourth of the pitch P 1 . 
     In the illustrated embodiment, the conductive pipe  20   a  is on an opposite side of the first semiconductor-containing feature  80  from the Second Track, and the conductive pipe  20   b  is on an opposite side of the semiconductor-containing feature  82  from the Third Track. Accordingly, a pair of outer edges of the logic cell  78  are bounded by the conductive pipes  20   a  and  20   b.    
     The conductive pipe  20   a  is shown to be coupled with VDD (i.e., is coupled with a reference voltage node at VDD), and the conductive pipe  20   b  is shown to be coupled with VSS (i.e., is coupled with a reference voltage node at VSS). In other embodiments, the conductive pipes may be coupled with other suitable supply voltages. 
     The semiconductor-containing feature  80  is shown to comprise three p-type source/drain regions (S/D-1, S/D-2 and S/D-3), and the semiconductor-containing feature  82  is shown to comprise three n-type source/drain regions (S/D-4, S/D-5 and S/D-6). The regions S/D-1, S/D-2 and S/D-3 may be referred to as first, second and third source/drain regions, and the regions S/D-4, S/D-5 and S/D-6 may be referred to as fourth, fifth and sixth source/drain regions. 
     First and second gating structures  60   a  and  60   b  extend along the second direction (y-axis direction), and cross the tracks  77 . 
     The first and second source/drain regions S/D-1 and S/D-2 are on opposing sides of the second gating structure  60   b  relative to one another, and the second and third source/drain regions S/D-2 and S/D-3 are on opposing sides of the first gating structure  60   a  relative to one another. The fourth and fifth source/drain regions S/D-4 and S/D-5 are on opposing sides of the second gating structure  60   b  relative to one another, and the fifth and sixth source/drain regions S/D-5 and S/D-6 are on opposing sides of the first gating structure  60   a  relative to one another. 
     A first electrical connection  84  extends from the first source/drain region S/D-1 to the first conductive pipe  20   a , and a second electrical connection  86  extends from the third source/drain region S/D-3 to the first conductive pipe  20   a . A third electrical connection  88  extends from the sixth source/drain region S/D-6 to the second conductive pipe  20   b . A fourth electrical connection  90  extends from the second source/drain region S/D-2 to the fourth source/drain region S/D-4. 
     Input/output (I/O) is provided relative to the logic cell  78 . In the shown embodiment, a first input/output (I/O-1) has a region (interconnect) which extends along the Third Track, and which is electrically coupled with the first gating structure  60   a  through an interconnect  91   a.    
     A second input/output (I/O-2) has a region (interconnect) which extends along the Second Track, and which is electrically coupled with the second gating structure  60   b  through an interconnect  91   b.    
     A third input/output (I/O-3) has a region (interconnect) which extends along the Third Track. A fifth electrical connection  92  extends from the fourth source/drain region (S/D-4) to the interconnect associated with I/O-3. 
     The terms “first”, “second” and “third” input/outputs are arbitrary. For instance, either of the input/outputs I/O-1 and I/O-2 may be referred to as the “first” and “second” input/output. 
     The electrical connections  84 ,  86 ,  88 ,  90  and  92  may comprise any suitable materials and may be formed at any suitable elevational level(s). In some embodiments, the gating structures  60   a  and  60   b  may be at a first elevational level, and the connections  90  and  92  may be at a second level which is above the first level. The electrical connections  84 ,  86  and  88  may be at the same elevational level as the gating structures  60   a  and  60   b , or may be at a different elevational level relative to such gating structures. The electrical connections  84 ,  86 ,  88 ,  90  and  92  may comprise any suitable electrically conductive materials and may comprise any suitable structural configurations. 
     The capacitor  69  is shown to be electrically coupled along the connection  92 , and thus is electrically coupled with the fourth source/drain region (S/D-4). The capacitor  69  may be formed at any suitable location, and may or may not be formed at the illustrated location. One of the electrodes of the capacitor  69  shown to be coupled with ground voltage (GND); or, in other words, with an electrical node at ground voltage. In other embodiments, the electrode may be coupled with any other suitable voltage. 
     The conductive pipes  20  described herein may be provided in any suitable locations and may be utilized for any suitable applications. For instance,  FIG.  24    shows an application in which conductive features  12  are formed along a first pitch P 1 , and in which the conductive pipes  20  are provided between the features and are utilized to reduce the pitch. Specifically, the features  12  and the pipes  20  may be conductive structures which alternate with one another, which together are formed along a second pitch which is less than the first pitch P 1 . Conventional processes utilize multiple techniques for reducing pitch. Such techniques are commonly referred to as pitch-multiplication techniques, with example pitch-multiplication techniques being pitch-doubling techniques. The pitch-doubling techniques effectively reduce a pitch between features by about half (i.e., form twice as many features within a defined area of a semiconductor substrate). The methodology described with reference to  FIG.  24    may be considered to be an example of utilizing the pipes  20  in a pitch-multiplication technique. The structure of  FIG.  24    may be utilized at any suitable level within an integrated circuit. For instance, the structure may be utilized in a memory array, an electrical bus, etc. 
       FIG.  25    shows another application of a conductive pipe  20  formed in accordance with embodiments described herein. The illustrated embodiment has the conductive pipe  20  formed between a pair of features  12  and  14 . Regions  100   a - c  are under the features  12  and  14 , and are under the conductive pipe  20 . The regions  100   a - c  may correspond to, for example, active regions across a memory array (i.e., may comprise semiconductor material  102 ). The illustrated conductive pipe  20  is coupled to the outer regions  100   a  and  100   c  through the conductive blocks  24  and  26 , but extends across the inner region  100   b  without being coupled to such region. Specifically, the conductive pipe  20  may be elevationally above the region  100   b  . Accordingly, the pipe  20  may be utilized as an electrical interconnect which extends from the region  100   a  to the region  100   c , and which passes over the region  100   b  without being electrically coupled to such region. In some embodiments, the regions  100   a  and  100 c may be referred to as first and second active regions, and the region  100   b  may be referred to as a third active region. 
     The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc. 
     Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. 
     The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences. 
     The terms “electrically connected” and “electrically coupled” may both be utilized in this disclosure. The terms are considered synonymous. The utilization of one term in some instances and the other in other instances may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow. 
     The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation. 
     The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings. 
     When a structure is referred to above as being “on”, “adjacent” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on”, “directly adjacent” or “directly against” another structure, there are no intervening structures present. The terms “directly under”, “directly over”, etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment. 
     Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not. 
     Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. A first dielectric material is within the intervening space, under the conductive pipe, and along sidewalls of the features. A second dielectric material is within the intervening space and over the first dielectric material. The second dielectric material is over and under the conductive pipe. 
     Some embodiments include integrated circuitry having first, second, third and fourth tracks which extend along a first direction, and which are spaced from one another by intervening spaces. The tracks and the intervening spaces alternate with one another along a second direction which is substantially orthogonal to the first direction. The tracks and the intervening spaces are on a pitch. A first semiconductor-containing feature is along the first track. A second semiconductor-containing feature is along the fourth track. A first gating structure extends along the second direction and crosses the first, second, third and fourth tracks. A second gating structure extends along the second direction and crosses the first, second, third and fourth tracks. First, second and third source/drain regions are within the first semiconductor-containing feature. The first and second source/drain regions are on opposing sides of the second gating structure relative to one another, and the second and third source/drain regions are on opposing sides of the first gating structure relative to one another. Fourth, fifth and sixth source/drain regions are within the second semiconductor-containing feature. The fourth and fifth source/drain regions are on opposing sides of the second gating structure relative to one another, and the fifth and sixth source/drain regions are on opposing sides of the first gating structure relative to one another. A first conductive pipe is adjacent to the first semiconductor-containing feature and is on an opposite side of the first semiconductor-containing feature from the second track. The first conductive pipe is substantially parallel to the first semiconductor-containing feature and is spaced from the first semiconductor-containing feature by a first distance which is less than about one-half of the pitch. A second conductive pipe is adjacent to the second semiconductor-containing feature and is on an opposite side of the second semiconductor-containing feature from the third track. The second conductive pipe is substantially parallel to the second semiconductor-containing feature and is spaced from the second semiconductor-containing feature by a second distance which is less than about one-half of the pitch. A first electrical connection extends from the first source/drain region to the first conductive pipe. A second electrical connection extends from the third source/drain region to the first conductive pipe. A third electrical connection extends from the sixth source/drain region to the second conductive pipe. 
     Some embodiments include a method of forming an integrated assembly. First and second features are formed to be spaced from one another by an intervening space. The first and second features are substantially parallel to one another. A dielectric material is formed within the intervening space. The dielectric material pinches off at a top of the intervening space to form a tube which extends substantially parallel to the first and second features. Conductive material is formed within the tube to thereby pattern a conductive pipe within the tube. The conductive pipe is substantially parallel to the first and second features. 
     In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.