Patent Publication Number: US-2011063878-A1

Title: Power-supply controller

Description:
CLAIM OF PRIORITY 
     The present application claims the benefit of copending U.S. Provisional Patent Application Ser. No. 61/243,290 filed Sep. 17, 2009; the present application also claims the benefit of copending U.S. Provisional Patent Application Ser. No. 61/306,130, filed Feb. 19, 2010; all of the foregoing applications are incorporated herein by reference in their entireties. 
    
    
     SUMMARY 
     This Summary is provided to introduce, in a simplified form, a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. 
     An embodiment of a controller for a power supply includes circuitry that is operable to allow the power supply to operate as follows. During a first portion of a supply period, a first current flows through a first winding of the power supply, through a second winding of the power supply, and to an output node of the power supply. And during a second portion of the supply period, a second current flows through the first winding, through a third winding of the power supply, and to the output node. Each of the first, second, and third windings may be electrically coupled to one or more of the other windings during one or more portions of the supply period. Furthermore, the first, second, and third windings may be magnetically coupled to one another. 
     For example, in an embodiment, such a controller may be part of a DC-DC voltage-step-down converter that may more efficient, and that may have less interdependence between an output-signal ripple and a transient response, than a conventional buck converter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of an embodiment of a DC-DC-converting power supply and a load powered by the supply. 
         FIG. 2  is timing diagram of signals generated during operation of an embodiment of the power supply of  FIG. 1 . 
         FIG. 3  is a schematic diagram showing current flows that occur while an embodiment of the power supply of  FIG. 1  is operating during a first inductor-charging portion of the supply period of  FIG. 2 . 
         FIG. 4  is a schematic diagram showing current flows that occur while an embodiment of the power supply of  FIG. 1  is operating during a first inductor-discharging portion of the supply period of  FIG. 2 . 
         FIG. 5  is a schematic diagram showing current flows that occur while an embodiment of the power supply of  FIG. 1  is operating during a second inductor-charging portion of the supply period of  FIG. 2 . 
         FIG. 6  is a schematic diagram showing current flows that occur while an embodiment of the power supply of  FIG. 1  is operating during a second inductor-discharging portion of the supply period of  FIG. 2 . 
         FIG. 7  is a schematic diagram showing current flows that occur while an embodiment of the power supply of  FIG. 1  is operating during a high-output-current period of  FIG. 2 . 
         FIG. 8  is a schematic diagram of an embodiment of a power supply that includes two or more of the power-delivery circuits of  FIG. 1 . 
         FIG. 9  is a diagram of an embodiment of a system that incorporates either or both of the power supply of  FIG. 1  and the power supply of  FIG. 8 . 
     
    
    
     DETAILED DESCRIPTION 
     DC-DC converters may be used for converting an input DC signal (e.g., an input voltage or input current) having a first level into a regulated output DC signal (e.g., an output voltage or output current) having a second level. 
     For example, a conventional buck converter converts an input DC voltage having a higher level (e.g., 5 Volts (V)) into a regulated output DC voltage having a lower level (e.g., 1.3 V). 
     Unfortunately, such a conventional buck converter may have problems including relatively poor conversion efficiency and a relatively high level of interdependence between the output-voltage ripple amplitude and the step-up load-transient response time—a step-up load transient is a relatively sudden and significant increase in the load current. 
     Regarding poor conversion efficiency, in a conventional buck converter, the high-side transistors are subjected to lossy switching transitions as the phase inductor forces both full load current and full input voltage on each transition. Further, the high-side transistor is forced to supply reverse-recovery current for the freewheeling diode, and this adds additional loss. These losses also scale with frequency and input voltage. 
     And regarding the interdependence between the output-voltage ripple amplitude and the step-up load-transient response time, the ripple amplitude increases as Vin increases, and decreases as the value of the phase inductor increases; and the transient response time decreases as Vin increases, and increases as the value of the phase inductor increases. Therefore, changes in Vin and in the inductor value that improve (i.e., reduce) the ripple amplitude may worsen (i.e., lengthen) the transient response, and changes in Vin and in the inductor value that improve (i.e., shorten) the transient response may worsen (i.e., increase) the ripple amplitude. Consequently, a buck-converter designer may be forced to choose a middle ground in which neither the ripple amplitude nor the or transient response is optimal. 
       FIG. 1  is a schematic diagram of an embodiment of a DC-DC converting power supply  10  for providing a regulated output voltage Vout to a load  12 . As discussed below, the power supply  10  may have improved conversion efficiency as compared to a conventional DC-DC converter such as a conventional buck converter, and may reduce the interdependence between the output-voltage ripple amplitude superimposed on Vout and the supply&#39;s step-up load-transient response. 
     The power supply  10  includes a power-delivery circuit  14 , and includes a controller  16  for controlling the operation of the power-delivery circuit. 
     The power-delivery circuit  14  includes a first input node  18 , a first power-supply stage  20 , a first, e.g., primary, winding  22 , a first, e.g., primary, current sensor  24 , a second power-supply stage  26 , second and third, e.g., secondary, windings  28   1  and  28   2 , magnetically coupled to each other and to the primary winding  22  second and third, e.g., secondary, current sensors  30   1  and  30   2 , a third power-supply stage  32 , a reference node  34 , an output filter inductor  36 , an output node  38 , an output filter capacitor  40 , and an output current sensor  42 . 
     The first input node  18  receives an input voltage Vin, which has a greater magnitude than Vout. For example, Vin may be 5 V, and Vout may be 1.3 V. The power-delivery circuit  14 , in response to the controller  16 , effectively steps down Vin to generate Vout. 
     The first power-supply stage  20  includes switching transistors  48  and  50 , which, in response to switching-control signals S 1  and S 2  from the controller  16 , couple and uncouple respective nodes of the primary winding  22  to and from the input node  18 . In an embodiment, the transistors  48  and  50  are N-channel MOS-type power transistors having their substrates tied to their sources such that the transistor body diodes have their cathodes coupled to the input node  18 . 
     The primary winding  22  may be modeled to include a magnetizing inductance Lp and a leakage inductance L lkp , and conducts a current Ip, which may flow in either direction depending on the operational state of the power supply  10  as discussed below. 
     The primary current sensor  24  provides to the controller  16  at least one signal that indicates the magnitude and direction of the primary current Ip. 
     The second power-supply stage  26  includes switching transistors  52  and  54 , which, in response to switching-control signals S 3  and S 4  from the controller  16 , couple and uncouple respective nodes of the primary winding  22  to and from respective nodes of the secondary windings  28   1  and  28   2 . In an embodiment, the transistors  52  and  54  are N-channel MOS-type power transistors having their substrates tied to their sources such that the transistor body diodes have their anodes coupled to the respective nodes of the secondary windings  28   1  and  28   2 . 
     The secondary windings  28   1  and  28   2  may be modeled to include respective magnetizing inductances Ls 1  and Ls 2  and a shared leakage inductance L lks , and conduct respective currents Is 1  and Is 2 , which typically flow toward the output node  38 . Each of the secondary windings  28  includes a common node (the output node of the leakage inductance L lks ) coupled to the filter inductor  36 , and includes a respective node coupled to the second and third power-supply stages  26  and  32 . 
     The secondary current sensor  30   1  provides to the controller  16  at least one signal that indicates the magnitude and direction of the secondary current Is 1 ; likewise, the secondary current sensor  30   2  provides to the controller at least one signal that indicates the magnitude and direction of the secondary current Is 2 . 
     The third power-supply stage  32  includes switching transistors  56  and  58 , which, in response to switching-control signals S 5  and S 6  from the controller  16 , couple and uncouple respective nodes of the secondary windings  28   1  and  28   2  to and from the reference node  34 . In an embodiment, the transistors  56  and  58  are N-channel MOS-type power transistors having their substrates tied to their sources such that the transistor body diodes have their anodes coupled to the node  34 . 
     The reference node  34  receives a reference voltage such as ground as shown in  FIG. 1 . Although shown coupled to the reference node  34 , the load  12  may be coupled to a node other than node  34 . 
     The output filter inductor  36  and the output filter capacitor  40  are optional components that may further smoothen Vout by reducing the ripple component of the voltage at the output of the leakage inductance L lks . 
     The output current sensor  42  provides to the controller  16  at least one signal that indicates the magnitude and direction of the output current Iout through the filter inductor  36  (or through the leakage inductance L lks  if the filter inductor  36  is omitted). 
     Still referring to  FIG. 1 , the controller  16  receives the signals Vout, Ip, Is 1 , Is 2 , and Iout (or signals representative of these signals) the power-delivery circuit  14 , and generates the switching signals S 1 -S 6  in response to these fed back signals. For example, the controller  16  may compare Vout (or a signal representative of Vout) to a reference signal (not shown in  FIG. 1 ), and adjust the on and off times of at least one of the signals S 1 -S 6  to regulate Vout to a set voltage level. The controller  16  may also compare the secondary-winding currents Is 1  and Is 2  to Iout, and adjust the on and off times of at least one of the signals S 1 -S 6  to balance the secondary-winding currents such that the average level of Is 1  is substantially equal to the average level of Is 2 . Furthermore, the controller  16  may monitor Ip, Is 1 , Is 2 , or Iout for an over-current condition, and may adjust the on and off times of at least one of the signals S 1 -S 6  in response to a detected over-current condition to prevent damage to the power-delivery circuit  14  or to the load  12 . Moreover, the controller  16  may monitor Vout for an over-voltage condition, and may adjust the on and off times of at least one of the signals S 1 -S 6  in response to a detected over-voltage condition to prevent damage to the power-delivery circuit  14  or to the load  12 . Because conventional techniques for voltage regulation, phase-current balancing, over-current protection, and over-voltage protection exist, further details of these techniques are omitted for brevity. 
     And the load  12  may be an integrated circuit (IC) such as a processor, memory, or system on a chip (SoC). 
     Still referring to  FIG. 1 , the interaction of the magnetically coupled primary winding  22  and the secondary windings  28   1  and  28   2 , may improve the efficiency of the power supply  10 , and may reduce the dependency between the amplitude of the Vout ripple and the step-up-load-transient response of the power supply as compared to a conventional buck converter. 
     The interaction of the primary and secondary windings  22 ,  28   1 , and  28   2  may reduce the current through the transistors  48 ,  50 ,  52 , and  54 —these transistors may be considered to be akin to the high-side transistors of a conventional buck converter—and thus may increase the efficiency of the power supply  10  by reducing the power dissipated by these transistors. For example, during a state of the power supply  10  in which the primary winding  22  and the secondary winding  28   1  are being charged by a current Ip=Is 1  flowing from Vin, through the closed transistor  50  (the transistor  48  is open), through the primary winding  22 , through the closed transistor  52  (the transistor  54  is open), and through the secondary winding  28   1 , the total current Iout is equal to the sum of Is 1  and Is 2 =Ip(Np+Ns 1 )/Ns 2 , where Np is the number of turns in the primary winding  22 , Ns 1  is the number of turns in the secondary winding  28   1 , and Ns 2  is the number of turns in the secondary winding  28   2  (the transistor  58  may also be closed to allow the magnetically induced current Is 2  to bypass the body diode of this transistor). If, for example, Np=8 and Ns 1 =Ns 2 =1, then Iout=Ip+9·Ip=10·Ip. So for a given output current Iout, Ip=Iout·Ns 2 /(Np+Ns 1 +Ns 2 ), or Ip=Iout/10 in the given example. In contrast, the current through a high-side transistor of a conventional buck converter is equal to Iout divided by the number of phases in the buck converter. Consequently, because the power dissipated in the closed transistors  50  and  52  is proportional to Ip 2 , and because the current Ip is reduced from Iout by the transformer turns ratio per above, the combined power dissipated by the transistors  50  and  52  may be less than the power dissipated by a high-side transistor of a conventional buck converter for a same load current and transistor-on time. Furthermore, that the transistors  50  and  52  may achieve ZVS when turning on may also reduce the power dissipated by these transistors as compared to a high-side transistor of a conventional buck converter. A similar analysis applies during a state of the power supply  10  in which the transistors  48 ,  54 , and  56  are closed and the transistors  50 ,  52 , and  58  are open, in which case Ip=Iout·Ns 1 /(Np+Ns 1 +Ns 2 ). If Ns 1 =Ns 2 , then Iout is the same during both of the above-described operational states of the power supply  10 . Furthermore, the above-described operational states of the power supply  10  are further described below in conjunction with  FIGS. 2-7 . 
     Still referring to  FIG. 1 , the interaction of the primary and secondary windings  22 ,  28   1 , and  28   2  may also reduce the interdependency of the amplitude of the ripple voltage superimposed on Vout and the step-up load-transient response of the power supply  10 . While the transistors  50 ,  52 , and  58  are closed and the transistors  48 ,  54 , and  56  are open, a voltage Vs at the node common to the secondary windings  28   1  and  28   2  equals Vin×Ls 1 /(Lp+Ls 1 +Ls 2 )=Vin×Ns 1 /(Np+Ns 1 +Ns 2 ) (where the primary and secondary windings are formed from wires have similar inductive properties); for example, wherein Np=8 and Ns 1 =Ns 2 =1, then Vs=Vin/10. A similar analysis may be made for the state of the power supply  10  in which the transistors  48 ,  54 , and  56  are closed, and the transistors  50 ,  52 , and  58  are open. Therefore, because the output ripple amplitude superimposed on Vout decreases as Vs decreases, the output ripple amplitude also decreases as the transformer turns ratio increases (for a given Vin). Furthermore, the step-up load-transient response time increases with the value of the secondary leakage inductance L lks  and with the value of the filter inductor  36  (if present). Consequently, because the transformer turns ratio is independent of the secondary leakage inductance L lks  and the inductance L filter  of the filter inductor  36 , a designer may adjust the output ripple amplitude and the step-up load-transient response time independently of one another. That is, the transformer turns ratio of the power supply  10  is an additional variable that a conventional buck converter does not have, and that allows a designer to adjust, among other things, the output ripple and transient response time. For example, suppose a designer wants to reduce the transient-response time of the supply  10  for a given value of Vin by decreasing the secondary-leakage/output inductance Llks+Lfilter. In a conventional buck converter and for a given value for Vin, this would also increase the output voltage ripple. But in the power supply  10 , for a given value of Vin, the designer may increase the transformer turns ratio to reduce the value of Vs, and to thus offset the would-be increase in the output ripple caused by the lower secondary-leakage/output inductance. Or, suppose a designer wants to reduce the output-ripple magnitude for given values of Vin, phase inductance, and switching frequency. In a conventional buck converter, this would be difficult to impossible to do. But in the power supply  10 , the designer may achieve a reduction in output ripple without changing the value of Vin, the value of the secondary-leakage/output inductance, or the switching frequency by increasing the transformer turns ratio to reduce Vs. 
     Still referring to  FIG. 1 , alternate embodiments of the power supply  10  are contemplated. For example, at least one of the transistors  48 ,  50 ,  52 ,  54 ,  56 , and  58  may be any suitable type other than an N-channel MOS power transistor, and, for MOS-type ones of these transistors, the body diodes may be eliminated. Furthermore, there may be more than one primary winding  22  and there may be fewer or more than two secondary windings  28 . Moreover, at least one of the windings  22  and  28  may not be magnetically coupled to the other windings. In addition, at least one of the current sensors  24 ,  30 , and  38  may be omitted. Furthermore, the filter inductor  36  may be omitted. Moreover, the supply  10  may include more than one filter inductor  36  and more than one filter capacitor  40  arranged in any suitable topology. In addition, the controller  16  may receive fewer than all of the signals Vout, Ip, Is 1 , Is 2 , and Iout, or may receive additional signals. Furthermore, the power-supply  10  may regulate the output current Iout instead of the output voltage Vout. 
       FIG. 2  is a timing diagram of the switching signals S 1 -S 6  during operation of an embodiment of the power supply  10  of  FIG. 1 . 
       FIGS. 3-7  are schematic diagrams showing respective current flows through the power supply  10  of  FIG. 1  during various operational states of an embodiment of the power supply, where the operational states correspond to respective portions of the timing diagram of  FIG. 2  as further discussed below. Furthermore, some components (e.g., the current sensors,  24 ,  30 , and  42 ) of the power supply  10  have been omitted from  FIGS. 3-7  for clarity. 
     Referring to  FIGS. 1-7 , the operation of an embodiment of the power supply  10  is described. 
     Referring to  FIG. 2 , at a time t 1 , the controller  16  generates the signals S 1  and S 5  logic high, generates the signals S 3  and S 4  logic low, and transitions the signals S 2  and S 6  from logic high to logic low such that the transistors  48  and  56  are on, the transistors  52  and  54  are off, and the transistors  50  and  58  transition from on to off. 
     In response to the transistor  50  turning off, the discharging current Ip that was flowing from Vin, through the transistor  50 , through the primary winding  22 , and through the transistor  48  now flows through the body diodes of the transistors  54  and  58 , through the primary winding, through the transistor  48 , and to Vin. 
     At a time t 2 , which is delay d 1  after the time t 1  sufficient to allow the body diode of the transistor  54  to be conducting the current Ip at time t 2  per above, the controller  16  transitions S 4  from logic low to logic high such that the transistor  54  transitions from off to on. Because its body diode is conducting when it turns on, the transistor  54  may achieve zero-voltage switching (ZVS), which may reduce the power that the transistor  54  dissipates while turning on. In an alternate embodiment, the controller  16  may wait until the time t 2  to transition S 6  low so that the transistor  58  stays on at least until the transistor  54  transitions from off to on. By keeping the transistor  58  on, the current Ip conducted by the body diode of the transistor  54  flows through the on transistor  58  instead of through the body diode of the transistor  58 , thus potentially reducing the power dissipated by the transistor  58  during this time period. In another alternate embodiment, S 4  may transition high at time t 1  such that the transistor  54  does not achieve ZVS. 
     At some time after time t 2 , the time depending, e.g., on the leakage inductance L lkp , the current Ip reverses direction, and begins to flow from Vin, through the on transistor  48 , through the primary winding  22 , through the on transistor  54 , and through the secondary winding  28   2 . 
     Consequently, during a portion D 1  of the switching period P sw , a linearly increasing current Ip flows from Vin, through the on transistor  48 , through the primary winding  22 , through the on transistor  54 , and through the secondary winding  28   2  as indicated by the longer dashed line in  FIG. 3 . Because this current Ip is being sourced by Vin, it may be thought of as a current that is energizing, e.g., charging, the leakage inductances L lkp  and L lks  and the filter inductor  36  (if present). 
     Also during the portion D 1  of the switching period P sw , an increasing magnetically induced current Is 1  circulates through the on transistor  56  and the secondary winding  28   1  as shown by the shorter dashed line in  FIG. 3 , where, as discussed above, Is 1 =Ip(Np+Ns 2 )/Ns 1 . 
     At a time t 3 , the controller  16  transitions S 4  low to turn off the transistor  54 , such that the off transistors  52  and electrically isolate the primary winding  22  from the secondary windings  28 . 
     Also at time t 3 , the current Is 2  that was flowing through the transistor  54  now begins to flow through the body diode of the transistor  58 . 
     At a time t 4 , which is a delay d 2  after the time t 3  sufficient to allow the body diode of the transistor  58  to be conducting the current Is 2  at time t 4  per above, the controller  16  transitions S 6  from logic low to logic high to turn on the transistor  58 . Because its body diode is conducting when it turns on, the transistor  58  may achieve zero-voltage switching (ZVS), which may reduce the power that the transistor  58  dissipates while turning on. Alternatively, the controller  16  may transition S 6  from logic low to logic high at the time t 3  such that the transistor  58  does not achieve ZVS. 
     Also at the time t 4 , the controller  16  transitions S 2  from logic low to logic high to turn on the transistor  50 , which may achieve ZVS to reduce power dissipation for reasons similar to those discussed above for the transistor  58 . Alternatively, the controller  16  may transition S 2  from logic low to logic high at the time t 3  such that the transistor  50  does not achieve ZVS. 
     Consequently, during a portion D 2  of the switching period P sw , a linearly decreasing current Ip flows from Vin, through the on transistor  48 , through the primary winding  22 , through the on transistor  50 , and back to Vin as indicated by the upper dashed line in  FIG. 4 . Because this current Ip not being sourced by Vin (the transistors  48  and  50  effectively cause zero volts to be across the primary winding  22  by coupling both nodes of the primary winding to the input node  18 ), Ip may be thought of as a current that is de-energizing, e.g., discharging, the leakage inductance L lkp . 
     Also, during the portion D 2  of the switching period P sw , a linearly decreasing current Is 1  flows from ground, through the transistor  56 , through the secondary winding  28   1 , through the leakage inductance L lks , through the filter inductor  36  (if present), through the parallel combination of the filter capacitor  40  and the load  12 , and back to ground as shown by the left-most most lower dashed line in  FIG. 4 ; likewise, a linearly decreasing current Is 2  flows from ground, through the transistor  58 , through the secondary winding  28   2 , through the leakage inductance L lks , through the filter inductor  36  (if present), through the parallel combination of the filter capacitor  40  and the load  12 , and back to ground as shown by the right-most lower dashed line in  FIG. 4 . Because the currents Is 1  and Is 2  are not being sourced by Vin, they may be thought of as currents that are de-energizing, e.g., discharging, the leakage inductance L lks ; therefore, Is 1  and Is 2  may be similar to the “freewheeling” current(s) of a conventional buck converter. 
     In an embodiment, the portion D 2  of the switching period P sw  is short enough such that the currents Ip, Is 1 , and Is 2  do not decay to or below zero. The maximum length of D 2  before these currents decay to zero depends, e.g., on the sizes of the leakage inductances L lkp  and L lks , on the size of the filter inductance L filter  (if the filter inductor  36  is present), and on the size of the load  12 . Therefore, a designer may set the sizes L lkp , L lks , ad L filter  (If present) such that during steady-state operation, Ip, Is 1 , and Is 2  do not decay to zero or reverse direction (i.e., go below zero). 
     At a time t 5 , the controller  16  transitions the signals S 1  and S 5  from logic high to logic low, generates the signals S 3  and S 4  logic low, and generates the signals S 2  and S 6  logic high such that the transistors  48  and  56  transition from on to off, the transistors  52  and  54  are off, and the transistors  50  and  58  are on. 
     In response to the transistor  48  turning off, the discharging current Ip that was flowing from Vin, through the transistor  48 , through the primary winding  22 , and through the transistor  50  now flows through the body diodes of the transistors  52  and  56 , through the primary winding, through the transistor  50 , and to Vin. 
     At a time t 6 , which is a delay d 3  after the time t 5  sufficient to allow the body diode of the transistor  52  to be conducting the current Ip at the time t 6  per above, the controller  16  transitions S 3  from logic low to logic high such that the transistor  52  transitions from off to on. Because its body diode is conducting when it turns on, the transistor  52  may achieve ZVS to reduce power dissipation. In an alternate embodiment, the controller  16  may wait until the time t 6  to transition S 5  low so that the transistor  56  stays on at least until the transistor  52  transitions from off to on. By keeping the transistor  56  on, the current Ip conducted by the body diode of the transistor  52  flows through the on transistor  56  instead of through the body diode of the transistor  56 , thus potentially reducing the power dissipated by the transistor  56  during this time period. In another alternate embodiment, the controller  16  may transition S 3  high at time t 5  such that the transistor  52  does not achieve ZVS. 
     At some time after the time t 6 , the time depending, e.g., on the leakage inductance L lkp , the current Ip reverses direction, and begins to flow from Vin, through the on transistor  50 , through the primary winding  22 , through the on transistor  52 , and through the secondary winding  28   1 . 
     Consequently, during a portion D 3  of the switching period P sw , a linearly increasing charging current Ip flows from Vin, through the on transistor  50 , through the primary winding  22 , through the on transistor  52 , and through the secondary winding  28   1  as indicated by the longer dashed line in  FIG. 5 . 
     Also during the portion D 3  of the switching period P sw , an increasing magnetically induced current Is 2  circulates through the on transistor  58  and the secondary winding  28   2  as shown by the shorter dashed line in  FIG. 5 , where, as discussed above, Is 2 =Ip(Np+Ns 1 )/Ns 2 . 
     At a time t 7 , the controller  16  transitions S 3  low to turn off the transistor  52  such that the off transistors  52  and  54  electrically isolate the primary winding  22  from the secondary windings  28 . 
     Also at the time t 7 , the current Is 1  that was flowing through the transistor  52  now begins to flow through the body diode of the transistor  56 . 
     At a time t 8 , which is delay d 4  after the time t 7  sufficient to allow the body diode of the transistor  56  to be conducting the current Is 1  at the time t 8  per above, the controller  16  transitions S 5  from logic low to logic high to turn on the transistor  56 . Because its body diode is conducting when it turns on, the transistor  58  may achieve ZVS to reduce turn-on power dissipation in this transistor. Alternatively, the controller  16  may transition S 5  from logic low to logic high at the time t 7  such that the transistor  56  does not achieve ZVS. 
     Also at the time t 8 , the controller  16  transitions S 1  from logic low to logic high to turn on the transistor  48 , which may achieve ZVS to reduce power dissipation for reasons similar to those discussed above for the transistor  56 . Alternatively, the controller  16  may transition S 1  from logic low to logic high at the time t 7  such that the transistor  48  does not achieve ZVS. 
     Consequently, during a portion D 4  of the switching period P sw , a linearly decreasing discharging current Ip flows from Vin, through the on transistor  50 , through the primary winding  22 , through the on transistor  48 , and back to Vin as indicated by the upper dashed line in  FIG. 6 . 
     Also, during the portion D 4  of the switching period P sw , a linearly decreasing discharging current Is 1  flows from ground, through the transistor  56 , through the secondary winding  28   1 , through the leakage inductance L lks , through the filter inductor  36  (if present), through the parallel combination of the filter capacitor  40  and the load  12 , and back to ground as shown by the left-most lower dashed line in  FIG. 6 ; likewise, a linearly decreasing discharging current Is 2  flows from ground, through the transistor  58 , through the secondary winding  28   2 , through the leakage inductance L lks , through the filter inductor  36  (if present), through the parallel combination of the filter capacitor  40  and the load  12 , and back to ground as shown by the right-most lower dashed line in  FIG. 6 . In an embodiment, as discussed above in conjunction with  FIG. 4  and the portion D 2  of the switching period P sw , the portion D 4  of the switching period P sw  is short enough such that the currents Ip, Is 1 , and Is 2  do not decay to or below zero. 
     At a time t 9 , a new switching period P sw  begins, and the steady-state sequence described above in conjunctions with  FIGS. 1-6  repeats. 
     Still referring to  FIGS. 1-6 , alternate operational embodiments exist. For example, under heavy load conditions the charging portions D 1  and D 3  the switching period P sw  may increase, and the discharging portions D 2  and D 4  may decrease, without losing the transformer action, up to a theoretical maximum point of a 50% duty cycle (a charging current Ip always flowing in one direction or another) where D 2 =D 4 =0, and where ZVS may be unachievable for any of the transistors. Increasing the duty cycle above 50% would result in a high Iout mode for at least part of the switching period. An embodiment of the power supply  10  operating in a high Iout mode is discussed below in conjunction with  FIG. 7 . 
     Referring to  FIGS. 1 ,  2 , and  7 , the operation of an embodiment of the power supply  10  during a high Iout period is described. For example, the power supply  10  may enter a high Iout mode in response to a step-up load transient, which, as discussed above, occurs when the current sunk by the load  12  increases relatively suddenly and significantly. Although a high Iout period is described as commencing while the power supply  10  is in a discharging state such as that described above in conjunction with  FIG. 4  and the portion D 2  of the steady-state switching period P sw , it is understood that the below-described operation may be similar if the high Iout period commences while the power supply  10  is in another state. Furthermore, although described as occurring in response to a step-up load transient, a high Iout period may occur in response to other conditions, and may even occur as a portion of the steady-state switching period P sw  depending on the design of the power supply  10 . 
     Some time before a time t 10 , the controller  16  senses a step-up load transient. For example, the controller  16  may sense the step-up load transient by sensing a relatively sudden drop in Vout that exceeds a threshold drop. Because there exist conventional techniques for detecting a step-up load transient, further details of such techniques are omitted for brevity. 
     At the time t 10 , the controller transitions S 5  and S 6  low to transition the transistors  56  and  58  from on to off. 
     Therefore, the currents Is 1  and Is 2  that were flowing through the on transistors  56  and  58  now flow through the body diodes of these transistors. 
     Then, at a time t 11 , which is a delay d 5  after the time t 11  sufficient to allow the transistors  56  and  58  to turn off, the controller  16  transitions S 3  and S 4  from logic low to logic high to turn on the transistors  52  and  54 . 
     Therefore, during a time period P transient , the transistors  48 ,  50 ,  52 , and  54  are on, and the transistors  56  and  58  are off, such that a charging current flows from Vin, through the on transistors  48  and  52 , through the secondary winding  28   1 , and to the load  12 , and such that a charging current Is 2  flows from Vin, through the on transistors  50  and  54 , through the secondary winding  28   2 , and into the load  12 . Because Vin is effectively applied directly to the secondary windings  28   1  and  28   2  via the on transistors  48  and  52 , and  50  and  54 , respectively, the currents Is 1  and Is 2  may increase more quickly to meet the rather sudden increased current demand of the load  12 . 
     At some time after the time t 11  but before a time t 12 , the controller  16  senses that Iout has reached a level that is substantially sufficient to satisfy the increased current demands of the load  12 . For example, the controller  16  may sense that Vout has risen above a threshold, or the controller may limit the transient period P transient  to a fixed length. Because there exist conventional techniques for detecting the end of a step-up load transient, further details of such techniques are omitted for brevity. 
     At the time t 12 , the controller  16  transitions S 1  and S 4  from logic high to logic low to turn off the transistors  48  and  54  such that the power supply  10  transitions to the state discussed above in conjunction with  FIG. 5  and the portio D 4  of P sw . But it is understood that the controller  16  may control S 1 -S 6  so as to transition the power supply  10  to another suitable state. 
       FIG. 8  is a diagram of a power supply  60 , which is similar to the power supply  10  of FIGS.  1  and  2 - 7  except that the power supply  60  includes more than one power-delivery circuit  14 . Therefore, the supply  60  may be able to deliver a higher current Iout to the load  12  than the supply  10 . 
     A controller  62  receives Vout and Iout, receives from each power-delivery circuit  14   1 - 14   n  respective signals Ip 1 -Ip n , Is 11 -Is 1n , and Is 21 -Is 2n , and provides to each power-delivery circuit respective sets of switching signals S 1   1 -S 6   1  to S 1   n -S 6   n . 
     The output currents from the power-delivery circuit  14   1 - 14   n  are summed at a node  62  to generate Iout, and the controller  16  may balance these output currents, and the currents Is 1  and Is 2  of each delivery circuit  14 , as discussed above in conjunction with  FIG. 1 . Also, the filter capacitor  40  of each power-delivery circuit  14   1 - 14   n  may be replaced with a single filter capacitor  40  (or multiple filter capacitors  40  in parallel). 
     As discussed above in conjunction with  FIG. 1 , the filter inductor  36  may be omitted or there may be multiple filter inductors, and there may be multiple filter capacitors  40 . 
       FIG. 9  is a block diagram of an embodiment of a computer system  70 , which incorporates an embodiment of the power supply  10  of FIGS.  1  and  3 - 7 , an embodiment of the power supply  60  of  FIG. 8 , or embodiments of both the supplies  10  and  60 . Although the system  70  is described as a computer system, it may be any system for which an embodiment of the power supply  10  or the power supply  60  is suited. Furthermore, for clarity, the system  70  is described below as including the power supply  10  of  FIG. 1 . 
     The system  70  includes computing circuitry  72 , which, in addition to the supply  10 , includes a processor  74  powered by the supply, at least one input device  76 , at least one output device  78 , and at least one data-storage device  80 . 
     In addition to processing data, the processor  74  may program or otherwise control the supply  10 . For example, the functions of the controller  16  ( FIG. 1 ) may be performed by the processor  74 . 
     The input device (e.g., keyboard, mouse)  76  allows the providing of data, programming, and commands to the computing circuitry  72 . 
     The output device (e.g., display, printer, speaker)  78  allows the computing circuitry  72  to provide data in a form perceivable by a human operator. 
     And the data-storage device (e.g., flash drive, hard disk drive, RAM, optical drive)  80  allows for the storage of, e.g., programs and data. 
     From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.