Patent Publication Number: US-9406815-B2

Title: Adding decoupling function for TAP cells

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of U.S. application Ser. No. 13/106,521, now U.S. Pat. No. 9,082,886 B2, entitled “Adding Decoupling Function for TAP Cells,” filed May 12, 2011, which application is incorporated herein by reference. 
    
    
     BACKGROUND 
     Tap cells are commonly used in the integrated circuit design. Tap cells provide the body bias of the transistors and have the function of preventing the undesirable latch-up of integrated circuits, which latch-up is resulted from parasitic bipolar transistors of integrated circuits. Through the tap cells, n-well regions are coupled to VDD power rails, and p-well regions or p-type substrates are coupled to VSS power rails, which are electrical ground. Coupling the well regions and substrate regions to the VDD power rails and VSS power rails, respectively, may result in a reduction in the substrate resistance, and the reduction in the undesirable positive feedback in the integrated circuit. 
     For process uniformity and device performance reasons, dummy gate electrodes (dummy polysilicon lines) were added in the tap cells. This causes the adverse increase in the chip area usage of the tap cells. Since the tap cells need to be placed with appropriate distances from each other, an integrated circuit may include many tap cells. The chip-area penalty caused by the dummy gate electrodes is thus high. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  illustrates a layout of an integrated circuit in accordance with an embodiment, wherein the integrated circuit includes a tap cell comprising decoupling capacitors; 
         FIG. 2  illustrates a schematic cross-sectional view of the structure shown in  FIG. 1 , wherein the cross-sectional view comprises the decoupling capacitor formed of n-well pickup regions and the respective gate electrodes; 
         FIG. 3  illustrates a schematic cross-sectional view of the structure shown in  FIG. 1 , wherein the cross-sectional view comprises the decoupling capacitor formed of p-well pickup regions and the respective gate electrodes; and 
         FIG. 4  schematically illustrates an integrated circuit comprising a plurality of rows of cells, in which tap cells are included. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure. 
     A tap cell comprising decoupling capacitors is provided in accordance with an embodiment. The variations and the operation of the embodiment are then discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. 
       FIG. 1  illustrates an exemplary layout of a part of an integrated circuit, wherein a part of a row of cells is illustrated. The row of cells includes cells  20 ,  22 , and  24 . Cells  20 ,  22 , and  24  are standard cells that may be pre-built and saved in a design library, and are used for forming the illustrated integrated circuit through the steps of placement and route. Cells  20  and  24  represent any logic cells having logic functions, and may be inverter cells, NAND gate cells, multiplexers, and the like. Cell  22  is a tap cell, which is used for coupling n-well region  26  and p-well region (or p-substrate)  28  to VDD power rail  30  and VSS power rail  40 , respectively. Each of VDD power rail  30  and VSS power rail  40  includes a part extending into each of tap cell  22  and cells  20  and  24 . VDD power rail  30  and VSS power rail  40  may be located in a metal layer, which may be the bottom metal layer, for example. 
     In an embodiment, the illustrated row includes n-well region  26  and p-well region (or p-substrate)  28 . The row of cells includes a plurality of gate electrode lines  50  (including  50 A 1 ,  50 A 2 , and  50 B). Gate electrode lines  50  may be formed of polysilicon, and hence are alternatively referred to as POLY lines  50  throughout the description, although they may also be formed of other conductive materials such as metals, metal alloys, metal silicides, and the like. In an embodiment, all POLY lines  50  in tap cell  22  are parallel to each other and have a uniform pitch or non-uniform pitches. Furthermore, throughout the entire row, POLY lines  50  are parallel to each other, and may have a uniform pitch. 
     N-well pickup regions  54  are formed in n-well region  26 , and may be surrounded by isolation regions  56 , which may be shallow trench isolation regions in some embodiments. N-well pickup regions  54  are heavily doped with an n-type impurity such as phosphorous, arsenic, or the like. P-well pickup regions  58  are formed in p-well region  28 , and may be surrounded by isolation regions  56 . P-well pickup regions  58  are heavily doped with a p-type impurity such as boron, indium, or the like. In the described embodiments, the term “heavily doped” means an impurity concentration of above about 10 19 /cm 3 . One skilled in the art will recognize, however, that “heavily doped” is a term of art that depends upon the specific device type, technology generation, minimum feature size, and the like. It is intended, therefore, that the term be interpreted in light of the technology being evaluated and not be limited to the described embodiments. 
     Contact plugs  60  electrically connect n-well pickup regions  54  to VDD power rail  30 , for example, through metal jog(s)  62 , which are the metal lines/pads that may be formed in the same metal layer as VDD power rail  30 . Contact plugs  70  electrically connect p-well pickup regions  58  to VSS power rail  40 , for example, through metal jog(s)  72 , which may be formed in the same metal layer as VSS power rail  40 . Furthermore, contact plug(s)  64  electrically connect POLY line(s)  50 A 1  to VDD power rail  30 , for example, through metal jog  62 , and contact plugs  74  electrically connect POLY lines  50 A 2  to VSS power rail  40 , for example, through metal jogs  72 . 
       FIG. 2  illustrates a schematic cross-sectional view of a part of the structure shown in  FIG. 1 , wherein the cross-sectional view is obtained from the plane crossing line  2 - 2  in  FIG. 1 . N-well pickup regions  54  (N+) may be formed by implanting an n-type impurity into n-well region  26 . Accordingly, N-well pickup regions  54  extend into n-well region  26 . It is shown that gate electrode  50 A 1  is connected to n-well pickup regions  54 . Furthermore, n-well pickup regions  54  are interconnected, and are connected to VDD power rail  30 . Gate electrodes  50 A 2 , however, are connected to VSS power line  40 . Accordingly, decoupling MOS capacitor  66  is formed, wherein decoupling MOS capacitor may include a plurality of sub-capacitors connected in parallel. Each of gate electrodes  50 A 2  acts as one capacitor plate of one of the sub-capacitors. N-well pickup regions  54  and the channel regions  55  directly under gate electrodes  50 A 2  act as the other capacitor plates of the sub-capacitors. 
       FIG. 3  illustrates a schematic cross-sectional view of a part of the structure shown in  FIG. 1 , wherein the cross-sectional view is obtained from the plane crossing line  3 - 3  in  FIG. 1 . P-well pickup regions  58  (P+) may be formed by implanting a p-type impurity into p-well region  28 . Accordingly, p-well pickup regions  58  extend into p-well region  28 . It is shown that gate electrode  50 A 1  is connected to VDD power rail  30 . In some embodiments, there is a plurality of gate electrodes  50 A 1 , and the plurality of gate electrodes  50 A 1  may be interconnected. P-well pickup regions  58  are interconnected, and p-well pickup regions  58  and gate electrodes  50 A 2  are connected to VSS power rail  40 . Accordingly, decoupling MOS capacitor  76  is formed, wherein decoupling MOS capacitor  76  may include a plurality of sub-capacitors (although one is shown) connected in parallel. Each of gate electrodes  50 A 1  acts as one capacitor plate of each of the sub-capacitors. P-well pickup regions  58  and the respective channel region(s)  57  directly under gate electrode(s)  50 A 1  act as the other capacitor plates of the sub-capacitors. 
     Referring back to  FIG. 1 , in an embodiment, POLY lines  50 B are dummy POLY lines, which are electrically floating. There may exist pickup regions  54  or  58  formed on one side, but not on the other side, of the respective dummy POLY lines  50 B. POLY lines  50 A 1  and  50 A 2 , which are connected to VDD power rail  30  and VSS power rail  40 , respectively, may be placed in an alternating pattern such as a GPG pattern, with letter “G” representing POLY line  50 A 2 , and letter “P” representing POLY line  50 A 1 . In alternative embodiments, POLY lines  50 A 1  and  50 A 2  may be placed in any other patterns such as GGP, GPP, GPGPG, GGPPP, and the like. Furthermore, dummy POLY lines  50 B may be inserted between any POLY lines  50 A 1  and  50 A 2  that are in tap cell  22 . In an embodiment, as shown in  FIG. 1 , tap cell  22  may be free from other integrated circuit devices such as resistors and transistors that do not act as MOS capacitors. 
       FIG. 4  illustrates a plurality of cells placed as two rows, namely row  1  and row  2 . Since tap cell  22  is a standard cell, an integrated circuit including a plurality of rows of cells may include a plurality of tap cells identical to cell  22 . The integrated circuit may also include other tap cells that are different from the illustrated tap cell  22 , but also include decoupling MOS capacitors similar to MOS capacitors  66  and  76  as shown in  FIGS. 2 and 3 , respectively. Furthermore, a row of cells may include a plurality of tap cells identical to cell  22 . In an embodiment, tap cells  22  may form a column (or a row) in a circuit including a plurality of rows and/or columns of standard cells. Furthermore, the VDD power rails  30  of neighboring tap cells  22  may be combined, and the VSS power rails  40  of neighboring tap cells  22  may be combined. The edges of tap cells  22  in the same column may be aligned, wherein the edges are perpendicular to VDD power rails  30  and VSS power rail  40 , although the edge may also be misaligned. 
     Referring again to  FIG. 1 , since tap  22  includes MOS capacitors including contact plugs connected to gate electrodes, and well pickup regions on opposite sides of the gate electrode, the environment of tap cell  22  is similar to that of logic cells  20  and  24 . Accordingly, the uniformity of patterns is improved. Furthermore, in addition to the function of providing well coupling to VDD and VSS power rails, tap cell  22  also provides decoupling capacitors for power rails. Therefore, the chip area occupied by tap cell  22  is used efficiently. 
     In accordance with embodiments, a circuit includes a tap cell. The tap cell includes a well region, a first well pickup region in the well region, a VDD power rail and a VSS power rail spaced apart from the VDD power rail. The tap cell also includes a first jog extending from the VDD power rail toward the VSS power rail, with the first jog forming a continuous region with the VDD power rail. The tap cell further comprises a first capacitor including a first gate electrode line acting as a first capacitor plate, and the first well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is overlapped by and connected to the first jog, and a second one of the first and second capacitor plates is coupled to the VSS power rail. 
     In accordance with other embodiments, a circuit comprises a tap cell. The tap cell includes a VDD power rail and a VSS power rail. The tap cell also includes a first capacitor. The first capacitor includes an n-well region, a first gate electrode over the n-well region and connected to the VSS power rail, and a first well pickup region in the n-well region and on a first side of the first gate electrode, wherein the first well pickup region is connected to the VDD power rail. The tap cell further includes a second capacitor. The second capacitor includes a p-well region, a second gate electrode over the p-well region and connected to the VDD power rail, wherein each of the first and the second gate electrodes comprises portions overlapped by both the VDD power rail and the VSS power rail, and a second well pickup region in the p-well region and on a first side of the second gate electrode, wherein the second well pickup regions are connected to the VSS power rail. 
     In accordance with yet other embodiments, a circuit includes a VDD power rail, a VSS power rail spaced apart from the VDD power rail, a first gate electrode forming a first capacitor plate of a first capacitor, an n-well pickup region forming a part of a second capacitor plate of the first capacitor, a second gate electrode parallel to the first gate electrode, wherein the second gate electrode forms a first capacitor plate of a second capacitor, and a p-well pickup region forming a part of a second capacitor plate of the second capacitor. The circuit also includes a first jog extending from the VDD power rail toward the VSS power rail, wherein the first jog overlaps the first gate electrode and the second gate electrode, a second jog extending from the VSS power rail toward the VDD power rail, wherein the second jog overlaps the first gate electrode and the second gate electrode. The circuit further includes a first contact plug interconnecting the first jog and the second gate electrode, and a second contact plug interconnecting the second jog and the first gate electrode. 
     Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.