Patent Publication Number: US-10777107-B2

Title: Array substrate, testing method and display apparatus

Description:
RELATED APPLICATIONS 
     The present application is a National Phase of International Application Number PCT/CN2017/112986, filed on Nov. 25, 2017, and claims the priority of China Application No. 201711048840.5, filed on Oct. 31, 2017. 
     FIELD OF THE DISCLOSURE 
     The disclosure relates to a testing apparatus, and more particularly to an array substrate, testing method and display apparatus. 
     BACKGROUND 
     With continuous development, Liquid Crystal Display (LCD) is widely used as the display device of electronic products, such as mobile phone, digital camera, TV, computer, etc. With the increased requirements on LCD display quality, the narrow border design of LCD has become an important technique to be researched. A narrow border LCD can effectively reduce the width of the splicing seam in the splicing screen, significantly increase effective areas of displayed image to improve the overall display quality, and be beneficial for immersion of the viewer. 
     During the process for manufacturing LCD, the yield rate of products is not high because of the complicated process of the array substrate. In order to improve the yield rate of the products after the box is formed, an array test for testing the display elements and circuits on the substrate should be performed after the array substrate is accomplished. The result of the test on the substrate is very important for the subsequent maintenance. Generally, the test circuit for testing the substrate is located at the border so that a challenge for achieving narrow border occurs. Therefore, it is a problem needs to be solved urgently that how to achieve the effect of narrow border while ensuring performance of substrate testing. 
     SUMMARY 
     Embodiments of the present invention provides an array substrate which is capable of achieving the effect of narrow border while ensuring performance of substrate testing. 
     Furthermore, a display apparatus comprising the array substrate mentioned above is provided. 
     Furthermore, a testing method of the array substrate mentioned above is provided. 
     In a first aspect, the embodiments of the present invention provide an array substrate. The array substrate comprises a display area and a non-display area formed around boundaries of the display area, wherein the display area comprises a plurality of pixel units arranged in matrix for displaying an image and a plurality of data lines for connecting the pixel units, the data lines are used for providing data signals to the pixel units and are extended along a first direction, and the non-display area comprises a testing circuit. The testing circuit comprises: a test switching control terminal to which a test switching control signal is input; a first test control terminal to which a low voltage level signal is input; a first number of a plurality of second test control terminals to which a test signal is input; a switching unit comprising the first number of a plurality of first switching elements, wherein the first switching elements are parallelly arranged along the first direction and are connected to the test switching control terminal and the first test control terminal, and the switching unit controls the array substrate to be in a non-testing status in accordance with the test switching control signal; and a plurality of testing units parallelly arranged along a second direction perpendicular to the first direction, wherein each of the testing units is connected to the switching unit, the first number of the second test control terminals and the first number of corresponded data lines, and the testing units test electrical characteristics of the corresponded data lines and pixel units when the switching unit controls the array substrate to be in a testing status in accordance with the test switching control signal. 
     In a second aspect, the embodiments of the present invention provide a testing method for testing pixel array in an array substrate. The array substrate comprises a display area and a non-display area formed around boundaries of the display area, the display area comprises a plurality of pixel units arranged in matrix for displaying an image and a plurality of data lines for connecting the pixel units, the data lines are used for providing data signals to the pixel units, the non-display area comprises a testing circuit, and the testing circuit comprises a test switching control terminal, a first test control terminal, a first number of a plurality of second test control terminals, a switching unit and a plurality of testing units, wherein the switching unit comprises the first number of a plurality of first switching elements parallelly arranged along a first direction, each of the first switching elements comprises a first control terminal, a first conducting terminal and a second conducting terminal, the testing units are parallelly arranged along a second direction perpendicular to the first direction, each of the testing units comprises a voltage input terminal and the first number of a plurality of second switching elements, the first switching elements are corresponding to the second switching elements one by one, and each of the second switching elements comprises a second control terminal, a third conducting terminal and a fourth conducting terminal. The testing method comprises: in a non-testing stage, controlling the first number of the first switching elements to be turned on and controlling a low voltage level signal input to the first test control terminal to be transmitted through the first number of the turned-on first switching elements to the corresponded second switching elements to terminate the second switching elements to cut off connections between the testing circuit and the data lines; and, in a testing stage, controlling the first number of the first switching elements to be terminated and controlling the testing units in accordance with a test signal input to the first number of the second test control terminals to test electrical characteristics of the corresponded data lines and pixel units. 
     In a third aspect, the embodiments of the present invention provide a display apparatus comprising the array substrate described in the first aspect above. 
     Comparing with the existed techniques, through parallelly arranging the first number of the first switching elements along the first direction and parallelly arranging the testing units along the second direction perpendicular to the first direction, the space in the first direction occupied by the testing circuit can be effectively decreased and narrow border can be achieved while ensuring performance of substrate testing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to make the descriptions of the technique solutions of the embodiments of the present invention or the existed techniques, the drawings necessary for describing the embodiments or the existed techniques are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and, for those with ordinary skill in this field, other drawings can be obtained from the drawings described below without creative efforts. 
         FIG. 1  is a structural schematic diagram of a display apparatus provided by one embodiment of the present invention. 
         FIG. 2  is a structural schematic diagram of the array substrate in the display apparatus shown in  FIG. 1 . 
         FIG. 3  is a schematic diagram of a testing circuit of the array substrate. 
         FIG. 4  is a control timing diagram of the testing circuit shown in  FIG. 3 . 
         FIG. 5  is a flow chart of a testing method of the array substrate provided by one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The technique solutions of the embodiments of the present invention will be clearly and fully described below accompanying with the drawings of the embodiments of the present invention. Obviously, the embodiments described below are only a part, but not all, of the embodiments of the present invention. Other embodiments obtained by those with ordinary skill in this art without creative efforts should belong to the protection scope of the present invention. 
     The array substrate, testing method and display apparatus provided by the embodiments of the present invention are described as follows. 
     Please refer to  FIG. 1 , which is a structural schematic diagram of a display apparatus  1  provided by one embodiment of the present invention. In the present embodiment, the display apparatus with liquid crystal (Liquid Crystal Display, LCD) is described as an example. Obviously, in other embodiments of the present invention, the display apparatus  1  could be, but not limited to, Electroluminescent (EL) display apparatus. 
     As shown in  FIG. 1 , the display apparatus  1  comprises: a color film substrate  2 , an array substrate  3 , and a liquid crystal layer  4  disposed between the color film substrate  2  and the array substrate  3 . The liquid crystal layer comprises a plurality of liquid crystal molecules  41 . 
     The array substrate  3  is disposed primarily with scan lines (not shown), data lines (not shown) and pixel electrodes (not show). The scan lines are disposed perpendicularly to the data lines. The pixel electrodes are formed within pixel areas defined by crossing of the scan lines and data lines. At least one switching element is disposed corresponding to one pixel electrode, and the switching element is generally accomplished by a Thin Film Transistor (TFT). Scan signals are transmitted through the scan lines to conduct the TFTs, and image signals transmitted by the data lines are applied to corresponded pixel electrodes through the TFTs to form electric field between the pixel electrodes and common electrodes on the color film substrate  2  to control twisting of the liquid crystal molecules for displaying images. In correspondence with each pixel unit, a color filtering material is formed on the color film substrate  2 . The color filtering material filters lights passing through the liquid crystal layer  4  to realize color image displaying. 
     During the manufacturing process of the array substrate  3 , it is necessary to detect defects through detecting procedures. For example, through comparison detection on the pixel patterns of the array substrate, the pattern defect or manufacturing defect can be detected. Generally, the detecting procedures are realized through designing testing circuits on the array substrate. 
     Please refer to  FIG. 2 , which is a structural schematic diagram of the array substrate  3  shown in  FIG. 1 . As shown in  FIG. 2 , the array substrate  3  comprises: a display area  31  and a non-display area  32  formed around the boundaries of the display area  31 . The display area  31  comprises a plurality of data lines  312  extended along a first direction F 1  and parallelly arranged along the second direction F 2 , a plurality of scan lines  313  extended along the second direction F 2  and parallelly arranged along the first direction F 1 , a plurality of pixel units  311  arranged in matrix and at intersections of the data lines  312  and the scan lines  313  for displaying images. The scan lines  313  control a row of the pixel units  311  connecting with the scan lines  313  for preparing to receive the data signals, and the data lines  312  provide the data signals to the pixel units  311  to display image. 
     The non-display area  32  comprises the testing circuit  321 , wherein the testing circuit  321  is parallelly arranged with the display area  31  along the first direction F 1 . In the present embodiment, the first direction F 1  is the same as the vertical or column direction of the array substrate  3 , the second direction F 2  is the same as the horizontal or row direction, and the testing circuit  321  is formed near the up side of the display area  31 . It is noted that, the testing circuit  321  formed near the up side of the display area  31  is only an example and is not for limiting the present invention. The testing circuit  321  could be formed near other locations of the boundaries of the display area  31 , such as left side, right side or down side. 
     Please refer to  FIG. 3 , which is a schematic diagram of a testing circuit of the array substrate  3  shown in  FIG. 3 . As shown in  FIG. 3 , the testing circuit  321  comprises: a test switching control terminal  3211 , a first test control terminal  3212 , a first number of a plurality of second test control terminals  3213 , a switching unit  3214  and a plurality of testing units  3215 . 
     The test switching control terminal  3211  is used for inputting a test switching control signal ATEN, the first test control terminal  3212  is used for inputting a low voltage level signal, and the first number of the second test control terminals  3213  are used for inputting test signal SW. 
     The switching unit  3214  comprises the first number of the first switching elements  32141  parallelly arranged along the first direction F 1 . Each first switching element  32141  comprises a first control terminal c 1 , a first conducting terminal e 1  and a second conducting terminal e 2 , wherein the first number of the first switching elements  32141  are parallelly connected to each other, the first conducting terminal e 1  of each first switching element  32141  is connected to the first test control terminal  3212 , the first control terminals c 1  of the first number of the first switching elements  32141  are connected to the test switching control terminal  3211 , and the second conducting terminals e 2  of the first number of the first switching elements  32141  are connected to the testing units  3215 . 
     The first control terminals c 1  of the first switching elements  32141  are used for receiving the test switching control signal ATEN input to the test switching control terminal  3211  to turn on or terminate the first switching elements  32141 , that is, ending or performing of the array substrate testing is controlled through turning on or terminating the first switching elements  32141 . 
     The testing units  3215  are parallelly arranged along the second direction F 2 . Each testing unit  3215  comprises a voltage input terminal  32151  and the first number of a plurality of second switching elements  32152 , wherein the first switching elements  32141  are corresponding to the second switching elements  32152  one by one, and the second switching element  32152  comprises a second control terminal c 2 , a third conducting terminal e 3  and a fourth conducting terminal e 4 . 
     The voltage input terminal  32151  is used for inputting a voltage signal. The second control terminal c 2  is used for controlling to turn on or terminate the second switching element  32152 . When the second switching element  32152  is turned on, the voltage signal provided through the voltage input terminal  32151  is applied to the data line  312  through the second switching element  32152  to realize testing on the pixel unit  311 . 
     It is noted that, the test signal received by the second control terminals c 2  of the different second switching elements  32152  of the same test unit is a signal set provided by the second test control terminal  3213 . Specifically, the signal set could be timing signals and control the different second switching elements  32152  to be turned on in different time. For example, when the test signal input by the second test control terminal  3213  in a first time period is 100000 (the first number used in this example is 6), the first one of the second switching elements  32152  is turned on and other five of the second switching elements  32152  are terminated. In another example, when the test signal input by the second test control terminal  3213  in a sixth time period is 000001, the last one of the second switching elements  32152  is turned off and other five of the second switching elements  32152  are terminated. It is noted that, the example described above are only a part but not all of the embodiments. 
     The second control terminal c 2  of the second switching element  32152  is connected to the second conducting terminal e 2  of the first switching element  32141  and the second test control terminal  3213 , the third conducting terminal e 3  of the second switching element  32152  is connected to the voltage input terminal  32151 , and the fourth conducting terminal e 4  of the second switching element  32152  is connected to one of the data lines  312 . 
     The first switching element  32141  and the second element  32152  are three-terminal elements. Specifically, the first switching element  32141  and the second switching element  32152  could be thin film transistor (TFT), field effect transistor (FET) or other three-terminal elements having switching function. The TFT is used as an example of the first switching element  32141  and the second switching element  32152  in descriptions of the present embodiment, however, the present invention should not be limited to this example. 
     The switching unit  3214  comprises the first number of the first switching elements  32141 . In the embodiments of the disclosure, the first number is 6 for example. In other embodiments of the present invention, the first number could be set to be, for example, 3, 4, 9, 12 or other quantities, in accordance with actual requirements. 
     Each testing unit  3215  comprises the first number of the second switching elements  32152 , wherein, the second switching elements  32152  of each testing unit  3215  are corresponding to the first switching elements  32141  of the switching unit  3214  one by one, and each first switching element  32141  corresponds to a plurality of second switching elements  32152  in the plurality of testing units  3215 , respectively. The total number of the second switching element  32152  in the testing circuit  321  is the same as the number of the data lines  312  in the display area  31 . 
     Preferably, the number of the second switching elements  32152  corresponding to each first switching element  32141  is equal to the number of the testing units  3215  in the testing circuit  321 . For example, when there are ten testing units  3215  in the testing circuit  321 , each first switching element  32141  should be corresponding to ten second switching elements  32152 , that is, the second conducting terminal e 2  of each first switching element  32141  is connected to the second control terminals c 2  of ten second switching elements  32152 . In other words, each first switching element  32141  controls turning on or terminating of several second switching elements  32152  connected to the first switching element  32141 , thereby controls inputting of several data lines  312  connected to the several second switching elements  32152 , and thereby controls ending or performing of tests for pixel units  311  connected to the several data lines  312 . Through controlling the testing circuit to perform electric characteristics test on the array substrate, failures such as short-circuit could be repaired by using laser cutting apparatus and is beneficial for increasing yield rate of products. At the same time, through using the first switching elements  32141  with multiplexed control circuit structure, number of the TFTs between the test control circuit and pixel array can be reduced. Therefore, number of the failure resources in the testing circuit can be reduced and thereby failure probability and cost of the substrate can be reduced. 
     In the present embodiment, through parallelly arranging the first number of the first switching elements  32141  along the first direction F 1  and parallelly arranging the testing units  3215  along the second direction F 2  perpendicular to the first direction F 1 , the space in the first direction F 1  occupied by the testing circuit  321  can be effectively decreased, narrow border can be achieved while ensuring performance of substrate testing and it is helpful for improving watching experiences of users. 
     In a testing stage when the test switching control signal ATEN controls the array substrate  3  to be in a testing status, the testing units  3215  test the electric characteristics of corresponded data lines  312  and pixel units  311  in accordance with the test signal SW. 
     Preferably, the test switching control signal ATEN is input to the test switching control terminal  3211  in the testing stage, the first control terminal c 1  of the first switching element  32141  connected to the test switching control terminal  3211  receives the test switching control signal ATEN, and the test switching control signal ATEN is a low potential signal to control the first switching element  32141  to be terminated. Optionally, the test switching control signal ATEN could be an OFF signal or VGL signal in the testing stage, wherein the VGL signal is a terminating voltage signal for the gate IC of the display apparatus  1 . 
     Preferably, the test signal SW is input to the first number of the second test control terminals  3213  in the testing stage and the second control terminals c 2  of the first number of the second switching elements  32152  connected to the first number of the second test control terminals  3213  receives the test signal SW, wherein the test signal SW is used for controlling the first number of the second switching elements  32152  to be turned on in different time. 
     Preferably, in the testing stage, the voltage signal is input to the voltage input terminal  32151 , the third conducting terminal e 3  of the second switching element  32152  connected to the voltage input terminal  32151  receives the voltage signal, and the voltage signal is transmitted through the turned-on second switching element  32152  to the corresponded data line  312 . Please refer to  FIG. 4 , which is a control timing diagram of the testing circuit  321  shown in  FIG. 3 . It can be observed from  FIG. 4  that, in the testing stage, the test switching control signal ATEN input to the test switching control terminal  3211  is low potential, and, when one set of the test signal input to the first number of the second test control terminal  3213  is 100000 (in first time period), 010000 (in second time period), 001000 (in third time period), 000100 (in fourth time period), 000010 (in fifth time period) and 000001 (in sixth time period), the sixth second switching elements  32152  of the testing unit  3215  are controlled to receive in different time period the corresponded test signal (in sequence: SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 ). The test signal controls the six second switching elements  32152  to be turned on from the first time period to the sixth time period in sequence so that sixth data lines connected to the second switching elements  32152  could input data to corresponded pixel units  311  in different time periods to achieve test on pixel units  311 . It is noted that the control timing diagram of the testing circuit  321  shown in  FIG. 4  is only an example but not limitation of the present invention. 
     In the non-testing stage, the switching unit  3214  controls the array substrate  3  to be in a non-testing status in accordance with the test switching control signal ATEN. 
     Preferably, a low voltage level signal is input to the first test control terminal  3212 . When the first switching element  32141  connected to the first test control terminal  3212  is turned on, the low voltage level signal is used for controlling the second switching element  32152  corresponding to the turned-on first switching element  32141  to be terminated to cut off connection between the testing circuit  321  and the pixel array to prevent normal operation of the pixel array from being affected by the testing circuit in the non-testing stage. 
     Preferably, in the non-testing stage, the test switching control signal ATEN is input to the test switching control terminal  3211 , the first control terminal c 1  of the first switching element  32141  connected to the test switching control terminal  3211  receives the test switching control signal ATEN, and the test switching control signal ATEN is high potential to control the first switching element  32141  to be turned on. Optionally, in the non-testing stage, the test switching control signal ATEN could be an ON signal or VGH signal, wherein the VGH signal is a driving voltage signal for the gate IC of the display apparatus  1 . 
     Preferably, in the non-testing stage, the low voltage level signal input to the first test control terminal  3212  is transmitted through the turned-on first switching element  32141  to the corresponded second switching element  32152 , and the second control terminal c 2  of the second switching element  32152  receives the low voltage level signal to control the second switching element  32152  to be terminated to cut off the connections between the testing circuit  321  and the data lines  312 . 
     It is noted that, in the non-testing stage, the test signal SW could also be the OFF signal, the low potential signal, the VGL signal or a floating signal. Because the low voltage level signal input to the first test control terminal  3212  can be transmitted through the first number of the turned-on first switching  32141  to the second switching elements  32152  and is capable of terminating the second switching elements  32152 , the test signal SW input to the second test control terminal  3213  would not be transmitted to the second switching element  32152  and would not affect the testing procedure no matter what the test signal SW is. 
     As shown in  FIG. 4 , the second test control terminal is input by the floating signal in the non-testing stage and, when the test switching control signal ATEN input to the test switching control terminal  3211  is high potential to turn on the first number of the first switching elements  32141  connected to the test switching control terminal  3211 , the low voltage level signal input to the first test control terminal  3212  is transmitted through the turned-on first switching elements  32141  to the second control terminals c 2  of the second switching elements  32152  to terminate the second switching elements  32152  and cut off the connection between the testing circuit and the pixel array. Through this way, normal operations of the pixel array could be prevented from being affected by erroneously turning on the second switching elements  32152  connected to the second test control terminal  3213  due to floating of the second test control terminal  3213 . 
     Therefore, through implementing the present embodiment, narrow border can be achieved while ensuring performance of substrate testing, failure probability and cost of the substrate can be reduced, and it is helpful for improving watching experiences of users. 
     Please refer to  FIG. 5 , which is a flow chart of a testing method provided by one embodiment of the present invention. The testing method is used for testing pixel array in an array substrate, the array substrate comprises a display area and a non-display area formed around boundaries of the display area, the display area comprises a plurality of pixel units arranged in matrix for displaying an image and a plurality of data lines for connecting the pixel units, the data lines are used for providing data signals to the pixel units, the non-display area comprises a testing circuit, and the testing circuit comprises a test switching control terminal, a first test control terminal, a first number of a plurality of second test control terminals, a switching unit and a plurality of testing units. Wherein, the switching unit comprises the first number of a plurality of first switching elements parallelly arranged along a first direction, each of the first switching elements comprises a first control terminal, a first conducting terminal and a second conducting terminal, the testing units are parallelly arranged along a second direction perpendicular to the first direction, each of the testing units comprises a voltage input terminal and the first number of a plurality of second switching elements, the first switching elements are corresponding to the second switching elements one by one, and each of the second switching elements comprises a second control terminal, a third conducting terminal and a fourth conducting terminal. The testing method could comprise: 
     S 501 , in a non-testing stage, controlling the first number of the first switching elements to be turned on and controlling a low voltage level signal input to the first test control terminal to be transmitted through the first number of the turned-on first switching elements to the corresponded second switching elements to terminate the second switching elements to cut off connections between the testing circuit and the data lines. 
     S 502 , in a testing stage, controlling the first number of the first switching elements to be terminated and controlling the testing units in accordance with a test signal input to the first number of the second test control terminals to test electrical characteristics of the corresponded data lines and pixel units. 
     Preferably, the array substrate controls the low voltage level signal to be input to the first test control terminal, and, when the first switching element connected to the first test control terminal is turned-on, the low voltage level signal controls the second switching element corresponding to the first switching element to be terminated. 
     Preferably, in the non-testing stage, the array substrate controls a high potential signal to be input to the test switching control terminal so that the first control terminals of the first number of the first switching elements connected to the test switching control terminal receive the high potential signal, wherein the high potential signal controls the first number of the first switching elements to be turned on. 
     Preferably, in the non-testing stage, the array substrate controls the low voltage level signal input to the first test control terminal to be transmitted through the turned-on first switching elements to the corresponded second switching elements so that the low voltage level signal is received by the second control terminals of the second switching elements, wherein the low voltage level signal controls the second switching elements to be terminated to cut off connections between the testing circuit and the data lines. 
     Preferably, in the testing stage, the array substrate controls a low potential signal to be input to the test switching control terminal so that the first control terminals of the first number of the first switching elements connected to the test switching control terminal receive the low potential signal, wherein the low potential signal controls the first switching elements to be terminated. 
     Preferably, in the testing stage, the array substrate controls the test signal to be input to the first number of the second test control terminals so that the second control terminals of the first number of the second switching elements connected to the second test control terminal receive the test signal, wherein the test signal is used for controlling the first number of the second switching elements to be turned on in different time. 
     Preferably, in the testing stage, the array substrate controls a voltage signal to be input to the voltage input terminal so that the voltage signal is received by the third conducting terminals of the second switching elements connected to the voltage input terminal and the voltage signal is transmitted through the turned-on second switching elements to corresponded data lines. 
     The present embodiment and the embodiment shown in  FIG. 3 - FIG. 4  are based on the same concept and having the same technique effects. The specific principles can be referred to the descriptions of the embodiment shown in  FIG. 3 - FIG. 4  and are not described again here. 
     The descriptions of the embodiments mentioned above are addressed in different parts while describing different embodiments. Once there is something not described in detail in any embodiment, the related description could be found in descriptions of other embodiments. 
     The embodiments above are only for describing the technique solutions of but not limiting the present invention. Although the detailed descriptions are made in reference to the embodiments, it can be understood by those with ordinary skill in the art that the technique solutions described in the embodiments can still be modified, or a part or all of the technique features can be equivalently substituted. These modifications or substitutions would not make the essences of the technique solutions beyond the scope of the corresponded technique solutions of the embodiments of the present invention.