Patent Publication Number: US-8970311-B2

Title: Voltage-controlled oscillator with amplitude and frequency independent of process variations and temperature

Description:
TECHNICAL FIELD 
     The present invention relates generally to voltage controlled oscillators and more particularly to a voltage controlled oscillator having an amplitude and frequency that is independent of process variations and temperature. 
     BACKGROUND 
     Voltage controlled oscillators (VCOs) are an important and integral part of many electronics systems. VCO applications include carrier synthesis in cellular phones, phase locked loops in microprocessors and communication systems, and clock generations for optical communications. Although VCOs have been used in numerous electronic systems for more than a hundred years, none of the known architectures satisfy all of the following requirements: (i) providing a frequency of oscillation that is independent of semiconductor process corners, (ii) providing a frequency of oscillation that is independent of temperature, (iii) providing an amplitude of oscillation that is independent of semiconductor process corners, (iv) providing an amplitude of oscillation that is independent of temperature, and (v) providing an amplitude of oscillation that is independent of tuning or oscillation frequency. Because these requirements have not been met, the VCO amplitude and frequency varies in an undesirable fashion. 
     Accordingly, there is a need in the art for improved architectures. 
     SUMMARY 
     In one embodiment, a voltage-controlled oscillator (VCO) is provided having an output signal having a frequency responsive to a tuning signal. The VCO includes: a plurality of inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, each inverter stage including a plurality of switched-capacitor circuits configured to control a signal delay through the inverter stage response to the tuning signal so as to control the frequency of the output signal; and a bias circuit configured to generate the bias voltage responsive to a reference signal such that an amplitude of the output signal is substantially independent of the output signal frequency and depends upon the reference signal. 
     In another embodiment, a phase-locked-loop (PLL) is provided that includes: a phase detector configured to compare the phase between a divided signal and an input signal to provide a phase detector output signal; a loop filter configured to filter the phase detector output signal to provide a tuning signal; and a voltage-controlled oscillator (VCO) including a plurality of inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source transistor, the current source transistor sourcing the tail current responsive to a bias voltage, each inverter stage including a plurality of switched-capacitor circuits configured to control a signal delay through the inverter stage response to the tuning signal so as to control the frequency of the output signal; and a bias circuit configured to generate the bias voltage responsive to a reference signal such that an amplitude of an output signal for the PLL is substantially independent of its output signal frequency and depends upon the reference signal. 
     The invention will be more fully understood upon consideration of the following detailed description, taken together with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1   a  shows a conventional resistor. 
         FIG. 1   b  shows a switched-capacitor circuit having an equivalent resistance to the resistor of  FIG. 1   a.    
         FIG. 1   c  shows a parasitic-insensitive variation for the switched-capacitor circuit of  FIG. 1   b.    
         FIG. 1   d  shows a switched-capacitor circuit having a varactor providing a variable capacitance responsive to a control voltage. 
         FIG. 2   a  is a schematic illustration of a conventional inverter stage. 
         FIG. 2   b  is a schematic illustration of an inverter stage having an output frequency independent of temperature and process corner variations. 
         FIG. 3  is a schematic illustration of an embodiment for the inverter stage of  FIG. 2  that is parasitic insensitive. 
         FIG. 4  is a schematic illustration of an inverter stage biased by a bias circuit so that the output frequency and amplitude of oscillation is independent of temperature and process corner variations and so that the amplitude of oscillation is independent of tuning range. 
         FIG. 5  illustrates a VCO incorporating a plurality of the inverter stages of  FIG. 4 . 
         FIG. 6  illustrates a phase-locked loop (PLL) incorporating the VCO of  FIG. 5 . 
     
    
    
     Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. 
     DETAILED DESCRIPTION 
     Reference will now be made in detail to one or more embodiments of the invention. While the invention will be described with respect to these embodiments, it should be understood that the invention is not limited to any particular embodiment. On the contrary, the invention includes alternatives, modifications, and equivalents as may come within the spirit and scope of the appended claims. Furthermore, in the following description, numerous specific details are set forth to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known structures and principles of operation have not been described in detail to avoid obscuring the invention. 
     To meet the five requirements discussed above, a VCO is provided with a biasing circuit and switched-capacitor circuits. The switched-capacitor circuits are discussed first as follows. 
     Switched-Capacitor Circuits 
       FIG. 1  ( a ) shows a resistor having a resistance R connected between two nodes A and B. Under Ohm&#39;s law, if the voltage of node A is V A  and the voltage of node B is V B , the role of the resistor is to transfer (V A -V B )/R amps of charge every second from node A to node B. But the same function can also be performed by a switched-capacitor circuit including a capacitor C clk  as shown in  FIG. 1   b . Switches S 1  and S 2  are driven open and closed in a non-overlapping fashion according to a switching frequency f clk . Thus, when switch S 1  is closed, switch S 2  is open. Conversely, when switch S 2  is closed, switch S 1  is open. Suppose the same voltages exist for nodes A and B as discussed for  FIG. 1   a . The charge moved from node A to node B in one cycle of the switching frequency f clk  is equal to the average current I flowing between the two nodes, i.e., I=f clk C clk (V A −V B ) or 
     
       
         
           
             R 
             = 
             
               
                 1 
                 
                   
                     f 
                     clk 
                   
                   ⁢ 
                   
                     C 
                     clk 
                   
                 
               
               . 
             
           
         
       
     
     Therefore, a switched-capacitor circuit may be viewed as a resistor whose value is equal to 
               1       f   clk     ⁢     C   clk         .         
This equivalence of capacitors and resistors, which was first discovered by Maxwell, is the foundation of switched-capacitor circuits.
 
     The equivalence can be made more precise by using extra switches in order to make the switched-capacitor circuit parasitic-insensitive as shown in  FIG. 1   c . In this embodiment, the switched-capacitor circuit transfers pulses of charge that, over time, average to the same current flow I as follows. A switching cycle for the switched capacitor circuit includes a first phase in which a pair of switches S 1  and S 4  conduct while a pair of switches S 2  and S 3  are off. In a second phase, switches S 2  and S 3  conduct while switches S 1  and S 4  are off. As with the switched-capacitor circuit of  FIG. 1   b , the switching is performed in a non-overlapping fashion according to the switching frequency f clk . The equivalent resistance of a switched-capacitor circuit thus depends on the clocking rate f clk , or the capacitance C clk . Adjusting either factor adjusts the equivalent resistance.  FIG. 1   d  shows a switched-capacitor circuit in which the capacitance is made adjustable through the use a varactor as controlled by a control voltage V CNTL . The switched-capacitor circuit may be exploited in a VCO as follows. 
     Voltage Controlled Oscillator (VCO) 
     Like a ring oscillator, a VCO also includes a plurality of VCO stages coupled together into a loop. However, the stages for a VCO have a variable resistance so that the frequency of oscillation may be voltage controlled.  FIG. 2   a  shows a conventional inverter stage  200  using a differential pair of transistors M 1  and M 2  that steer a tail current through a current source transistor M 3  as controlled by a bias voltage V BIAS . A pair of capacitors C L  represent the parasitic capacitance between stage  200  and adjoining stages that form the VCO. A pair of variable resistors having a variable resistance R d  (e.g., PMOS transistors in the triode mode of operation as controlled by a control voltage V CTNL ) control the signal delay between a pair of inverter input nodes having voltages V in1  and V in2  and a pair of inverter output nodes having voltages V out1  and V out2 . It can be shown that the resulting frequency of operation (f VCO ) for a VCO incorporating a plurality of inverter stages  200  is proportional to 1/R d C L . The conventional VCO oscillation frequency is thus dependent on process corner and temperature variations that affect R d  and C l . 
     In contrast, a VCO inverter stage  250  as shown in  FIG. 2   b  obviates this frequency dependence on process corner variations by using variable switched-capacitor circuits  255  that vary their resistances responsive to a control voltage V CNTL  such as discussed with regard to  FIG. 1   d . The VCO output frequency is as discussed with regard to inverter  200 , namely 1/R d C L . But the variable resistance R d  for a switched-capacitor circuit is 1/f clk C clk  as discussed above. It thus follows that the frequency of oscillation f VCO  for a VCO using a plurality of stages  250  becomes 
     
       
         
           
             
               f 
               vco 
             
             ∝ 
             
               
                 
                   
                     f 
                     clk 
                   
                   ⁢ 
                   
                     C 
                     clk 
                   
                 
                 
                   C 
                   L 
                 
               
               . 
             
           
         
       
     
       FIG. 3  illustrates a parasitic-insensitive embodiment  300  for inverter stage  255 . In inverter  300 , the switched-capacitor circuits are implemented using the parasitic-insensitive switched-capacitor circuits such as discussed with regard to  FIG. 1   c . Variable capacitors C clk  may be implemented using varactors as discussed with regard to  FIG. 1   d . A first switched-capacitor circuit uses switches N 1  and N 2  whereas a second switched-capacitor circuit uses switches N 3  and N 4 . V clk1  and V clk2  are non-overlapping clock signals that cycle according to the clock frequency f clk . 
     Note the intrinsic self-compensation that is provided by inverters  250  and  300 : whatever process corner (fast or slow) that is used to construct an inverter stage  250  or  300  will affect C clk , and C L  in substantially the same fashion. Thus, any semiconductor process variation effect on the resulting f VCO  is inherently cancelled. Similarly, whatever temperature change effect that occurs to C clk  will occur in substantially the same fashion for C L . Thus, any temperature variation effect on f VCO  is also inherently cancelled. In this fashion, both temperature compensation and semiconductor process variation compensation is achieved without the use of any compensation circuitry, thereby leading to manufacturing cost and design efficiencies. The requirements discussed above with regard to factors (i) and (ii) are thus satisfied. 
     It remains to be shown how to achieve factors (iii) through (v) with regard to the VCO amplitude of oscillation. In that regard, one of the fundamental issues in voltage controlled oscillators is the significant variation of the output amplitude swing across the frequency tuning range. To eliminate this output amplitude swing, the bias voltage V BIAS  for inverters  250  or  300  is provided by a bias circuit.  FIG. 4  shows an example bias circuit  400  providing the bias voltage V BIAS  for an inverter stage. Bias circuit  400  includes a FET M 4  that is matched to current source M 3  in the inverter stage. A differential amplifier drives the gate of M 4  with a feedback voltage V feedback  generated in response to comparing a reference voltage V ref  (such as generated by a bandgap reference circuit or other stable reference voltage generating circuit) to a drain voltage for M 4 . Differential amplifier  405  will thus drive V feedback  so as to make the drain voltage for M 4  virtually equal to V ref . The drain of M 4  couples through a switch-capacitor circuit to a power supply node having a voltage V CC . This feedback operation therefore ensures that 
               V   ref     =         V   cc     -   IR     =       V   cc     -       I       f   clk     ⁢     C   clk         .               
where I is the current through M 4  and R is the resistance of the switched-capacitor circuit. Since M 3  and M 4  are matched and have the same gate voltage (V feedback  being the same as V BIAS ), M+ also sources current I. During oscillation in the inverter stage, the tail current I will swing between transistors M 1  and M 2 . In one extreme during an oscillation cycle, M 1  will conduct virtually all the current I whereas later in the same oscillation cycle, M 2  will conduct virtually all the current I. When either M 1  or M 2  is not conducting, its drain voltage will rise to V CC . In contrast, if either of M 1  or M 2  is conducting all the tail current I, the drain voltage will fall to V CC −IR, where R is the resistance for the switched-capacitor circuits. Thus the voltage at the drain of M 1  (and similarly M 2 ) varies between V CC  and
 
                 V   cc     -     I       f   clk     ⁢     C   clk           ,         
with the range of oscillation being
 
               I       f   clk     ⁢     C   clk         .         
It thus follows that the amplitude of oscillation (A osc ) of the resulting VCO is given by
 
     
       
         
           
             
               A 
               osc 
             
             = 
             
               
                 I 
                 
                   
                     f 
                     clk 
                   
                   ⁢ 
                   
                     C 
                     clk 
                   
                 
               
               = 
               
                 
                   V 
                   cc 
                 
                 - 
                 
                   
                     V 
                     ref 
                   
                   . 
                 
               
             
           
         
       
     
     Advantageously, as the tuning voltage changes for the inverter of  FIG. 4 , the amplitude of oscillation remains fixed at V cc −V ref . Furthermore, as the temperature and the process corners vary, the amplitude of oscillation also remains fixed at V cc −V ref . Thus, the inverter of  FIG. 4  satisfies all five requirements (i) through (v) discussed above. 
       FIG. 5  illustrates a VCO  500  incorporating a plurality of inverters  505  such as inverters  250  or  300  discussed above. Bias circuit  400  is shown separately as a single bias circuit may be common to all inverters  505  in lieu of repeating this circuit for each inverter. As the tuning voltage V CNTL  is varied the frequency of oscillation f VCO  for an output voltage V out  is varied accordingly. However, this tuning does not affect the output amplitude as discussed above. Moreover, the amplitude of V out  does not depend on temperature or process corner variations. Similarly, the output frequency f VCO  is independent of process corner and temperature variations. In general, VCO  500  requires an odd number of inverters. However, an even number of inverters may be used if one is implemented in a non-inverting configuration to prevent latch-up. 
     The robust properties of VCO  500  have many advantageous applications. For example, a phase-locked loop (PLL)  605  is shown in  FIG. 6  that incorporates VCO  500 . PLL  605  also includes a phase detector  610 , a loop filter  615 , and a loop divider  620  to produce an output signal with regard to an input clock signal. This PLL output signal will satisfy requirements (i) through (v) discussed above. 
     It will be appreciated that the techniques and concepts discussed herein are not limited to the specific disclosed embodiments but instead may be changed or modified. The appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention.