Patent Publication Number: US-2015071013-A1

Title: Semiconductor Device Having Level Shift Circuit

Description:
This application is a continuation of U.S. patent application Ser. No. 13/286,665, filed Nov. 1, 2011, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2010-266591, filed on Nov. 30, 2010, the contents of which prior applications are incorporated herein in their entirety by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device, and more particularly to a semiconductor device that includes a level shift circuit. 
     2. Description of Related Art 
     Semiconductor devices such as a dynamic random access memory (DRAM) include various types of peripheral circuits that operate on an internal power supply voltage lower than an external power supply voltage in order to reduce power consumption. In such a case, there is a difference in amplitude between an internal data signal and an external data signal. A level shift circuit therefore needs to be inserted into the signal path so that the amplitude of the internal data signal is converted into that of the external data signal before the data is output to outside. 
     Converting a level of an internal data signal by using a level shift circuit may change the duty ratio of the internal data signal. The reason is that there is a difference between the rising time and falling time of the level shift circuit. To solve the problem, Japanese Patent Application Laid-Open Nos. 2004-40262 and 2004-153689 propose methods of connecting a pair of level shift circuits, which are opposite each other in conductivity types, in parallel. 
     In the level shift circuits described in Japanese Patent Application Laid-Open Nos. 2004-40262 and 2004-153689, in-phase output signals output from the pair of level shift circuits are short-circuited. Therefore, a through current can flow depending on a difference in operating speed between the pair of the level shift circuits. A level shift circuit has thus been desired that resolves the difference between the rising time and failing time and prevents the occurrence of a through current. 
     SUMMARY 
     In one embodiment, there is provided a semiconductor device comprising a level shift circuit unit that includes: first and second level shift circuits; an input circuit that supplies complementary input signals to the first and second level shift circuits, respectively; and an output circuit that converts complementary output signals supplied from the first and second level shift circuits into in-phase signals and short-circuits the in-phase signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and the other features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram showing the configuration of a semiconductor device  10  according to an embodiment of the present invention; 
         FIG. 2  is a schematic sectional view for explaining the separation on a well level; 
         FIG. 3  is a circuit diagram of a clock dividing circuit  200  shown in  FIG. 1 ; 
         FIG. 4  is a detailed circuit diagram of the clock dividing circuit  200  shown in  FIG. 3 ; 
         FIG. 5  is a waveform chart for explaining the operation of the clock dividing circuit  200  shown in  FIG. 3 ; 
         FIG. 6  is a circuit diagram of a multiplexer  300  shown in  FIG. 1 ; 
         FIG. 7  is a block diagram of a level shift block  400  and a data input/output circuit  500  shown in  FIG. 1 ; 
         FIG. 8  is a block diagram showing the configuration of a level shift circuit unit  410  shown in  FIG. 7 ; 
         FIG. 9A  is a circuit diagram of a level shift circuit LV 1  shown in  FIG. 8 ; 
         FIG. 9B  is a circuit diagram of a level shift circuit LV 2  shown in  FIG. 8 ; 
         FIG. 10  is a waveform chart showing the operation of the level shift circuit unit  410 ; 
         FIG. 11  is a simulation result showing the relationship between a difference ΔtPD in delay time and the external power supply potential VDD when using the level shift circuit unit  410  shown in  FIG. 8 ; 
         FIG. 12  is a simulation result showing the relationship between the time difference ΔtPD and the external power supply potential VDD according to a comparative example; 
         FIG. 13  is a circuit diagram of an impedance control circuit  510  shown in  FIG. 7 ; 
         FIG. 14  is a circuit diagram of an output buffer  501  shown in  FIG. 7 ; 
         FIG. 15  is a circuit diagram of the level shift circuit LV 3  according to a modification; and 
         FIG. 16  is a circuit diagram of the level shin circuit LV 3  according to another modification. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. 
     Referring now to  FIG. 1 , a semiconductor device  10  according to the present embodiment is a DDR (Double Data Rate) SDRAM (Synchronous DRAM). The semiconductor device  10  has external terminals including clock terminals  11   a  and  11   b,  command terminals  12   a  to  12   e,  address terminals  13 , a data input/output terminal (data output terminal)  14 , power supply terminals  15   a  to  15   e,  and a calibration terminal  16 . The semiconductor device  10  also has other terminals such as a data strobe terminal and a reset terminal, which are omitted from the diagram. The terminals described above as well as circuit blocks constituting the DDR SDRAM are formed on a single semiconductor chip as the semiconductor device  10 , as surrounded by a dotted line in  FIG. 1 . Further, each of the terminals may be also called “a ad” formed on the chip. 
     The clock terminals  11   a  and  11   b  are supplied with external clock signals CK and CKB, respectively. The supplied external clock signals CK and CKB are supplied to a clock input circuit  21 . As employed herein, a signal having a signal name with a trailing “B” is either the inverted signal of a corresponding signal or a low-active signal. The external clock signals CK and CKB are thus mutually complementary signals. The clock input circuit  21  generates a single-phase internal clock signal PreCLK based on the external clock signals CK and CKB, and supplies the internal clock signal PreCLK to a DLL circuit  100 . The DLL circuit  100  generates a phase-controlled internal clock signal LCLK 1  based on the internal clock signal PreCLK, and supplies the internal clock signal LCLK 1  to a clock dividing circuit  200  through a clock tree circuit  110 . The clock dividing circuit  200  generates complementary internal clock signals LCLK 2  and LCLK 2 B from the single-phase internal clock signal LCLK 1 , and supplies the complementary internal clock signals LCLK 2  and LCLK 2 B to a multiplexer  300 . 
     The command terminal  12   a  to  12 e are supplied with a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, a chip select signal CSB, and an on-die termination signal ODT, respectively. Such command signals CMD are supplied to a command decoder  32  through a command input circuit  31 . The command decoder  32  generates various internal commands ICMD by holding, decoding, or counting the command signals. The internal commands ICMD are supplied to a row-system control circuit  51 , a column-system control circuit  52 , and a mode register  53 . 
     The address terminals  13  are supplied with address signals ADD. The address signals ADD input to the address terminals  13  are supplied to an address latch circuit  42  through an address input circuit  41  to be latched in the address latch circuit  42 . Among the address signals ADD latched in the address latch circuit  42 , row addresses are supplied to the row-system control circuit  51 . Column addresses are supplied to the column system control circuit  52 . When entering a mode register set operation, the address signals ADD are supplied to the mode register  53 , whereby contents of the mode register  53  are updated. 
     Output signals of the row-system control circuit  51  are supplied to a row decoder  61 . The row decoder  61  selects any of word lines WL included in a memory cell array  70 . The memory cell array  70  includes a plurality of word lines WL and a plurality of bit lines BL which intersect each other. Memory cells MC are arranged at the intersections ( FIG. 1  shows only one of the word lines WL, one of the bit lines BL, and one of the memory cells MC). The bit lines BL are connected to corresponding sense amplifiers SA in a sense circuit  63 . 
     The output signals of the column-system control circuit  52  are supplied to a column decoder  62 . The column decoder  62  selects any of the sense amplifiers SA included in the sense circuit  63 . The sense amplifiers SA selected by the column decoder  62  are connected to a data amplifier  64 . In a read operation, the data amplifier  64  further amplifies read data that is amplified by the sense amplifiers SA, and supplies the read data to a FIFO circuit  65  through a read/write bus RWBS. In a write operation, the data amplifier  64  amplifies write data that is supplied from the FIFO circuit  65  through the read/write bus RWBS, and supplies the write data to sense amplifiers SA. As shown in  FIG. 1 , the FIFO circuit  65  is connected to the multiplexer  300 . The FIFO circuit  65  constitutes a data transfer circuit for transferring data between the memory cell array  70  and the multiplexer  300 . 
     The data input/output terminal  14  is an external terminal for outputting read data DQ to outside and receiving write data DQ from outside. The data input/output terminal  14  is connected to a data input/output circuit  500 . The data input/output circuit  500  is connected to the multiplexer  300  through a level shift block  400 . In a read operation, the data input/output circuit  500  drives the data input/output terminal  14  based on read data DQ that is supplied from the multiplexer  300  through the level shift block  400 . While  FIG. 1  shows only one data input/output terminal  14 , the number of data input/output terminals  14  need not necessarily be one. There may be provided a plurality of data input/output terminals  14 . 
     The data input/output circuit  500  is also connected to a calibration circuit  66 . The calibration circuit  66  is connected to the calibration terminal  16 , and functions to adjust the impedance of an output buffer included in the data input/output circuit  500 . The calibration circuit  66  performs a calibration operation to generate an impedance code ZQCODE, and supplies the impedance code ZQCODE to the data input/output circuit  500 . The data input/output circuit  500  changes the impedance of the output buffer based on the impedance code ZQCODE. 
     The impedance adjusting operation by the calibration circuit  66  is intended to prevent the impedance of the output buffer from deviating from a set value due to temperature changes or voltage variations. The set value of the impedance itself can be changed by a set value of the mode register  53 . 
     The power supply terminals  15   a  and  15   b  are supplied with an external power supply potential VDD and a ground potential VSS, respectively. As employed herein, a voltage between the external power supply potential VDD and the ground potential VSS may be referred to simply as “external voltage VDD.” The external voltage VDD is supplied to an internal voltage generating circuit  80 . The internal voltage generating circuit  80  includes a plurality of power supply circuits  81  to  84 , which generate respective internal power supply potentials VPERI, VPERI 2 , VPERI 3 , and VPERDL lower than the external power supply potential VDD. The internal power supply potentials VPERI, VPERI 2 , VPERI 3 , and VPERDL have the same level. As employed herein,a voltage between the internal power supply potential VPERI and the ground potential VSS may be referred to simply as “internal voltage VPERI.” The same applies to VPERI 2 , VPERI 3 , and VPERDL. 
     The power supply terminals  15   c  and  15   d  are to be supplied with an external power supply potential VDDQ and a ground potential VSSQ, respectively. As employed herein, a voltage between the external power supply potential VDDQ and the ground potential VSSQ may be referred to simply as “external voltage VDDQ.” 
     In the present embodiment, the external power supply potential VDDQ has the same level as that of the external power supply potential VDD. The ground potential VSSQ has the same level as that of the ground potential VSS. It should be noted that the power supply terminal  15   a  and  15   c  are separate terminals on the chip. A VDD line (high-potential power supply line)  17   a  that is connected to the power supply terminal  15   a  and a VDDQ line (high-potential power supply line)  17   c  that is connected to the power supply terminal  15   c  are also separate from each other, not being connected to each other in the chip. Similarly, a VSS line (low-potential power supply line)  17   b  that is connected to the power supply terminal  15   b  and a VSSQ line (low-potential power supply line)  17   d  that is connected to the power supply terminal  15   d  are separated from each other, not being connected to each other in the chip. Such separation of the power supply lines is intended to prevent power supply noise occurring due to the operation of the data input/output circuit  500  from propagating to other circuits. Since the data input/output circuit  500  passes a relatively high current for switching, the VDDQ line  17   c  and the VSSQ line  17   d  are designed to be lower than the VDD line  17   a  and the VSS line  17   b  in impedance. The lower impedance can be obtained by making the numbers of power supply terminals  15   c  and  15   d  greater than those of power supply terminals  15   a  and  15   b.    
     The present embodiment also provides a power supply terminal  15   e  supplied with a ground potential VSS 2 . A VSS 2  line  17   e  connected to the power supply terminal  15   e  is separated from the VSS line  17   b  and the VSSQ line  17   d,  being connected to neither of the lines in the chip. 
     The internal power supply potentials VPERI, VPERI 2 , VPERI 3 , and VPERDL are identical in level. A VPERI line  18   a  for supplying the internal power supply potential VPERI, a VPERI 2  line  18   b  for supplying the internal power supply potential VPERI 2 , a VPERI 3  line  18   c  for supplying the internal power supply potential VPERI 3 , and a VPERDL line  18   d  for supplying the internal power supply potential VPERDL are separated from each other, not being connected to each other in the chip. Again, such separation is intended to prevent an interaction among noises through the power supply lines. As employed herein, “power supply lines being separated” means not only that such line is not short-circuited, but also that transistors using these internal power supply potentials are formed in respective different wells and are thereby separated on a well level. 
     Turning to  FIG. 2 , two mutually independent n-wells  2   a  and  2   b  are formed in a p-type silicon substrate  1 . P-channel MOS transistors  3   a  and  3   b  are formed in the n-wells  2   a  and  2   b,  respectively. A source of the transistor  3   a  is connected to a power supply line  5   a  through a contact conductor  4   a.  Similarly, a source of the transistor  3   b  is connected to a power supply line  5   b  through a contact conductor  4   b.  Here, the power supply line  5   a  is any one of the VPERI line  18   a,  VPERI 2  line  18   b,  VPERI 3  line  18   c,  and VPERDL line  18   d.  The power supply line  5   b  is any one of the VPERI line  18   a,  VPERI 2  line  18   b,  VPERI 3  line  18   c,  and VPERDL line  18   d  other than the power supply line  5   a.  The internal power supply potentials VPERI, VPERI 2 , VPERI 3 , and VPERDL hardly affect each other by such separation on the well level even if these lines have the same potential level. It will be understood that the power supply circuits  81  to  84  that generate the internal power supply potentials VPERI, VPERI 2 , VPERI 3 , and VPERDL, respectively, are independent of each other. The power supply circuits  81  to  84  are also separated even in the internal voltage generation circuit  80 . 
     As shown in  FIG. 1 , the VDD line  17   a  and the VSS line  17   b  are connected to the level shift block  400 . The VDDQ line  17   c  and the VSSQ line  17   d  are connected to the data input/output circuit  500 . Such connection means that the level shift block  400  operates on the voltage (external voltage VDD) between the external power supply potential VDD and the ground potential VSS, and the data input/output circuit  500  operates on the voltage (external voltage VDDQ) between the external power supply potential VDDQ and the ground potential VSSQ. 
     The VPERI 2  line  18   b  is connected to the clock tree circuit  110  and the clock dividing circuit  200 . The clock tree circuit  110  and the clock dividing circuit  200  thus operate on the internal power supply voltage VPERI 2 . The VPERI 3  line  18   c  is connected to the multiplexer  300 . The multiplexer  300  thus operates on the internal power supply voltage VPERI 3 . The VPERDL line  18   d  is connected to the DLL circuit  100 . A delay line  100   a  included in the DLL circuit  100  operates on the internal power supply voltage VPERDL. Most of the other peripheral circuits are connected with the VPERI line  18   a.  Most of the peripheral circuits thus operate on the internal power supply voltage VPERI. For an example,  FIG. 1  shows the internal power supply voltage VPERI being supplied to the FIFO circuit  65 . 
     Since various types of internal circuits are driven by the internal power supply voltages VPERI and the like which are lower than the external power supply voltage VDD, it is possible to reduce power consumption. Incidentally, the memory cell array  70  also uses an array voltage (VARAY), a high voltage (VPP) which exceeds the external voltage VDD, and even a negative voltage (VKK). Such voltages are not directly relevant to the gist of the present invention, and description thereof will thus be omitted. 
     Turning to  FIG. 3 , the clock dividing circuit  200  includes a signal path PASS 1  that generates the internal clock signal LCLK 2 B from the internal clock signal LCLK 1 . The clock dividing circuit  200  also includes a signal path PASS 2  that generates the internal clock signal LCLK 2  from the internal clock signal LCLK 1 . The signal path PASS 1  is to generate the internal clock signal LCLK 2 B which is reverse to the internal clock signal LCLK 1  in phase. The signal path PASS 1  includes three inverters  211 ,  212 , and  213 . The signal path PASS 2  generates the internal clock signal LCLK 2  which is in phase with the internal clock signal LCLK 1 . The signal path PASS 2  includes two inverters  221  and  222 . The number of stages of the logic circuits included in the signal path PASS 1  is greater than that of the logic circuits included in the signal path PASS 2  by one. 
     Among the inverters that constitute the clock dividing circuit  200 , the inverters  211  to  213  and  222  operate with a voltage between the internal power supply potential VPERI 2  and the ground potential VSS 2  as the power source. The inverter  221  operates with an output signal of the inverter  211 , or an inverted signal INB, as the power source. With such a configuration, a phase of an output signal of the inverter  212 , or an internal signal INTT, coincides with a phase of an output signal of the inverter  221 , or an internal signal INBB, even if the signal paths PASS 1  and PASS 2  have different numbers of logic stages. Hereinafter, the circuit configuration and operation of the clock dividing circuit  200  used in the present embodiment will be described in more detail. 
     Turning to  FIG. 4 , the inverters each include a series circuit of P- and N-channel MOS transistors. Each individual inverter will be described in detail below. 
     The inverter  211  includes a series circuit of transistors P 211  and N 211 . Sources of the transistors P 211  and N 211  are connected to the VPERI 2  line  18   b  and the VSS 2  line  17   e,  respectively. The internal clock signal LCLK 1  is supplied to gate electrodes of the transistors P 211  and N 211  in common. An inverted signal INB is output from a common drain of the transistors P 211  and N 211 . 
     The inverter  212  includes a series circuit of transistors P 212 - 1  and N 212 - 1 . The inverted signal INB is supplied in common to gate electrodes of the transistors P 212 - 1  and N 212 - 1 . The internal signal INTT is output from a common drain of the transistors P 212 - 1  and N 212 - 1 . A transistor P 212 - 2  is connected between a source of the transistor P 212 - 1  and the VPERI 2  line  18   b.  The ground potential VSS 2  is supplied to a gate electrode of the transistor P 212 - 2 , whereby the transistor P 212 - 2  is fixed to an ON state. A transistor N 212 - 2  is connected between a source of the transistor N 212 - 1  and the VSS 2  line  17   e.  The internal power supply potential VPERI 2  is supplied to a gate electrode of the transistor N 212 - 2 , whereby the transistor N 212 - 2  is fixed to an ON state. 
     The  213  includes a series circuit of transistors P 213  and N 213 . Sources of the transistors P 213  and N 213  are connected to the VPERI 2  line  18   b  and the VSS 2  line  17   e,  respectively. The internal signal INTT is supplied to gate electrodes of the transistors P 213  and N 213  in common. The internal clock signal LCLK 2 B is output from a common drain of the transistors P 213  and N 213 . The inverter  213  is to secure a fan-out. The provision of the inverter  213  is not indispensable in the present invention. 
     The inverter  221  includes a series circuit of transistors P 221  and N 221 . Both sources of the transistors P 221  and N 221  are connected to an output end (common drain) of the inverter  211 . The internal clock signal LCLK 1  is supplied to gate electrodes in common of the transistors P 221  and N 221 . The internal signal INBB is output from a common drain of the transistors P 221  and N 221 . 
     The  222  includes a series circuit of transistors P 222  and N 222 . Sources of the transistors P 222  and N 222  are connected to the VPERI 2  line  18   b  and the VSS 2  line  17   e,  respectively. The internal signal INBB is supplied to gate electrodes of the transistors P 222  and N 222  in common. The internal clock signal LCLK 2  is output from a common drain of the transistors P 222  and N 222 . The inverter  222  is to secure a fan-out. The provision of the inverter  222  is not indispensable in the present invention. 
     In the present embodiment, the N-channel MOS transistors N 211 , N 212 - 1 , N 212 - 2 , and N 221  are designed to have the same channel width. The N-channel MOS transistors N 211 , N 212 - 1 , N 212 - 2 , and N 221  therefore have the same ON resistance. Similarly, the P-channel MOS transistors P 211 , P 212 - 1 , P 212 - 2 , and P 221  are designed to have the same channel width. The P-channel MOS transistors P 211 , P 212 - 1 , P 212 - 2 , and P 221  therefore have the same ON resistance. Since the N-channel MOS transistor(s) and the P-channel MOS transistor(s) that constitute an identical inverter are designed to have the same ON resistance, the transistors N 211 , N 212 - 1 , N 212 - 2 , N 221 , P 211 , P 212 - 1 , P 212 - 2 , and P 221  have the same ON resistance. 
     Turning to  FIG. 5 , when the internal clock signal LCLK 1  changes from a low level to a high level at time t 10 , the inverters  211  and  221  that receive the internal clock signal LCLK 1  start to invert their outputs, the inverted signal INB and the internal signal INBB. Since the inverter  221  is powered by an output signal of the inverter  211 , or the inverted signal INB, the inverter  221  is not able to invert the internal signal INBB (i.e., change the internal signal INBB to a low level) until the internal signal INB changes from a high level to a low level. At time t 11 , the inverted signal INB changes from a high level to a low level. At time t 12 , the internal signal INBB then changes from a high level to a low level. 
     Time t 12  corresponds to a timing for respondent logic circuits in the next stage to make an inversion after the inverted signal INB changes from a high level to a low level. The output signal of the inverter  212 , or the internal signal INTT, therefore also changes at time t 12 . That is, the inverters  212  and  221  simultaneously make a change at time t 12 . As a result, an output signal of the inverter  213 , or the internal clock signal LCLK 2 B, and an output signal of the inverter  222 , or the internal clock signal LCLK 2 , simultaneously make a change at time t 13 . 
     The same holds for the operation when the internal clock signal LCLK 1  changes from a high level to a low level. The internal clock signals LCLK 2  and LCLK 2 B eventually make a change at the same time. 
     The principle of the simultaneous changes of the output signal of the inverter  212 , or the internal signal INTT, and the output signal of the inverter  221 , or the internal signal INBB, will be described in more detail. 
     Initially, consider the case where the internal clock signal LCLK 1  changes from a low level to a high level. In such a case, the transistor N 211  included in the inverter  211  turns ON to change the inverted signal INB from a high level to a low level. This change has the following effects on the logic circuits in the next stage: For the inverter  212 , the transistor P 212 - 1  turns ON and an output end, or common drain, is connected to the VPERI 2  line  18   b  through the transistors P 212 - 2  and P 212 - 1 . Meanwhile, in the inverter  221 , the transistor N 221  turns ON and an output end, or common drain, is connected to the VSS 2  line  17   e  through the transistors N 211  and N 221 . Consequently, the internal signal INTT and the internal signal INBB always change at the same time if the series resistance of the transistors P 212 - 2  and P 212 - 1  and series resistance of the transistors N 211  and N 221  are designed to be the same. 
     The same applies when the internal clock signal LCLK 1  changes from a high level to a low level. In such a case, the transistor P 211  included in the inverter  211  turns ON to change the inverted signal INB from a low level to a high level. This change has the following effects on the logic circuits in the next stage: For the inverter  212 , the transistor N 212 - 1  turns ON and an output end, or common drain, is connected to the VSS 2  line  17   e  through the transistors N 212 - 2  and N 212 - 1 . Meanwhile, in the inverter  221 , the transistor P 221  turns ON and an output end, or common drain, is connected to the VPERI 2  line  18   b  through the transistors P 211  and P 221 . Consequently, the internal signal INTT and the internal signal INBB always change at the same time if series resistance of the transistors N 212 - 2  and N 212 - 1  and series resistance of the transistors P 211  and P 221  are designed to be the same. 
     As described above, the clock dividing circuit  200  used in the present embodiment uses the signal on the signal path PASS 1  as the power source of the inverter  221  which is included in the other signal path PASS 2 . Such a configuration allows precise matching of the pair of internal clock signals LCLK 2  and LCLK 2 B in phase without adding a capacitor or resistor for adjustment. This eliminates the need to change masks repeatedly for the sake of modifying capacitance value or resistance value, thereby allowing a reduction in design cost. 
     Turning to  FIG. 6 , the multiplexer  300  includes clocked drivers  301  to  304 . The clocked drivers  301  and  303  output an internal data signal CD supplied from the FIFO circuit  65  in synchronization with a rising edge of the internal clock signal LCLK 2 . The clocked drivers  302  and  304  outputs an internal data signal CE supplied from the FIFO circuit  65  in synchronization with the rising edge of the internal clock signal LCLK 2 B. Output signals of the clocked drivers  301  and  302  are output as pull-up data DQP through an inverter  310 . Outputs of the clocked drivers  303  and  304  are output as pull-down data DQN through an inverter  320 . 
     All the clocked drivers  301  to  304  and the inverters  310  and  320  which constitute the multiplexer  300  operate on the internal power supply voltage VPERI 3 . That is, the high-level power supply nodes are connected to the VPERI 3  line  18   c.  The low-level power supply nodes are connected to the VSS line  17   b.    
     Turning to  FIG. 7 , the level shift block  400  includes level shift circuit units  410  and  420 . The level shift circuit unit  410  converts the amplitude of the pull-up data DQP from VPERI 3  to VDD. The level shift circuit unit  420  converts an amplitude of the pull-down data DQN from VPERI 3  to VDD. A level-converted pull-up data DQP 0  from the level shift circuit unit  410  is supplied to the data input/output circuit  500  as pull-up data DQP 1  through gate circuits  431  and  432 . Similarly, the level-converted pull-down data DQN 0  from the level shift circuit unit  420  is supplied to the data input/output circuit  500  as pull-down data DQN 1  through gate circuits  441  and  442 . Among the circuits that constitute the level shift block  400 , the ones subsequent to the level shift circuit units  410  and  420  operate on a voltage between the external power supply potential VDD and the ground potential VSS (external voltage VDD). 
     Turning to  FIG. 8 , the level shift circuit unit  410  includes two level shift circuits LV 1  and LV 2 , an inverter  401  which inverts the pull-up data DQP, and an inverter  402  which inverts an output signal of the level shift circuit LV 1 . The two level shift circuits LV 1  and LV 2  have the same circuit configuration. The pull-up data DQP without change of its logic is input to the level shift circuit LV 1 . An inverted signal of the pull-up data DQP, inverted by the inverter  401 , is input to the level shift circuit LV 2 . The output signal of the level shift circuit LV 1  inverted by the inverter  402  and an output signal of the level shift circuit LV 2  are short-circuited and output as the pull-up data DQP 0 . 
     In the example shown in  FIG. 8 , the pull-up data DQP is simply input to the level shift circuit LV 1 . However, input circuits with any circuit configuration may be arranged in the stage prior to the level shift circuits LV 1  and LV 2  as long as complementary input signals are supplied to the level shift circuits LV 1  and LV 2 . Similarly, in the example shown in  FIG. 8 , the output signal of the level shift circuit LV 2  is simply short-circuited with the output signal of the inverter  402 . However, output circuits with any circuit configuration may be arranged in the stage subsequent to the level shift circuits LV 1  and LV 2  as long as the complementary output signals output from the level shift circuits LV 1  and LV 2  are converted into in-phase signals before short-circuited. 
     Turning to  FIG. 9A , the level shift circuit LV 1  includes P-channel MOS transistors  411  and  412  and N-channel MOS transistors  413  and  414 . The transistors  411  and  412  are connected to the VDD line  17   a  at their sources and are cross-coupled with each other. The transistors  413  and  414  are connected to the VSS line  17   b  at their sources and are connected in series to the transistors  411  and  412 , respectively. The pull-up data DQP is simply supplied to a gate electrode of the transistor  413 . The pull-up data DQP is supplied to a gate electrode of the transistor  414  through an inverter  415 . The level-shifted output signal is taken out from a node between the transistors  412  and  414 , and output as the pull-up data DQP 0  through inverters  416  and  402 . 
     Turning to  FIG. 9B , the level shift circuit LV 2  has exactly the same circuit configuration as the level shift circuit LV 1 . More specifically, the level shift circuit LV 2  includes P-channel MOS transistors  421  and  422  and N-channel MOS transistors  423  and  424 . The transistors  421  and  422  are connected to the VDD line  17   a  at their sources and are cross-coupled with each other. The transistors  423  and  424  are connected to the VSS line  17   b  at their sources and are connected in series to the transistors  421  and  422 , respectively. The pull-up data DQP is supplied to a gate electrode of the transistor  423  through the inverter  401 . The pull-up data DQP is supplied to a gate electrode of the transistor  424  through the inverters  401  and  425 . The level-shifted output signal is taken out from the node between the transistors  422  and  424 , and output as the pull-up data DQP 0  through an inverter  426 . 
     As shown in  FIG. 8 , the output signal of the level shift circuit LV 2  and the output signal of the level shift circuit LV 1  through the inverter  402  are short-circuited. This synthesizes the output signals of the level shift circuits LV 1  and LV 2 , so that the pull-up data DQP 0  has a composite waveform. 
     Since the level shift circuit unit  410  includes the two level shift circuits LV 1  and LV 2 , the number of elements is twice that of an ordinary level shift circuit. Each element, however, need only have half the size in an ordinary level shift circuit because the two level shift circuits LV 1  and LV 2  operate in parallel. Despite twice the number of elements, the occupied area on the chip is almost the same as with an ordinary level shift circuit. 
     Turning to  FIG. 10 , signals A and B are internal signals of the level shift circuits LV 1  and LV 2 , respectively. As shown in  FIG. 9 , the signal A represents an output level of the inverter  416 . The signal B represents a level of a node between the transistors  422  and  424 . As shown in  FIG. 10 , when the pull-up data DQP changes from a high level to a low level, both the signals A and B change from a low level to a high level at slightly different slew rates. Specifically, the signal A rises more sharply than the signal B. 
     The signals A and B are passed through the inverters  402  and  426 , respectively, and then short-circuited. The two signals having different slew rates are thereby synthesized into a steeper waveform. Similar synthesis also takes place when the pull-up data DQP changes from a low level to a high level. The input pull-up data DQP and the output pull-up data DQP 0  therefore have almost the same duty cycles. Since the signals A and B having different slew rates are passed through the respective inverters  402  and  426  before short-circuited, no through current will flow if fan-out and other factors of the inverters  423  and  426  are appropriately designed. 
     Turning to  FIG. 11 , the difference ΔtPD represents a difference between a delay time at the rise and a delay time at the fall of the pull-up data DQP. 
     The condition C 1  shown in  FIG. 11  refers to a case where the ambient temperature is 110° C. and the transistor threshold is higher than a designed value due to process variations. That is, the transistor in condition C 1  operates slower speed compared with a typical speed. The condition C 2  refers to a case where the ambient temperature is 45° C. and the transistor threshold is higher than a designed value due to process variations. The condition C 3  refers to a case where the ambient temperature is 45° C. and the transistor threshold is as designed. That is, the transistor in condition C 3  operates at a typical speed. The condition C 4  refers to a case where the ambient temperature is 45° C. and the transistor threshold is lower than a designed value due to process variations. That is, the transistor in condition C 4  operates faster speed compared with a typical speed. The condition C 5  refers to a case where the ambient temperature is −5° C. and the transistor threshold is lower than a designed value due to process variations. The condition C 6  refers to a case where the ambient temperature is 45° C., the N-channel MOS transistors have a threshold higher than a designed value, and the P-channel MOS transistors have a threshold lower than a designed value due to process variations. The condition C 7  refers to a case where the ambient temperature is 45° C., the N-channel MOS transistors have a threshold lower than a designed value, and the P-channel MOS transistors have a threshold higher than a designed value due to process variations. 
     In each of the conditions C 1  to C 7 , the leftmost value is for a situation when the external power supply potential VDD is 1.2 V. The rightmost value is for a situation when the external power supply potential VDD is 2.0 V. The values therebetween are at potential pitches of 0.1 V. 
     As shown in  FIG. 11 , it can be seen that the use of the level shift circuit unit  410  according to the present embodiment brings the difference ΔtPD between the delay time at the rise and the delay time at the fall of the pull-up data DQP close to zero. The tendency is little affected by the level of the external power supply potential VDD, the temperature condition, or the process condition. 
     The simulation result shown in  FIG. 12  is for the case of using only one of the level shift circuits LV 1  and LV 2 . It should be noted that the transistor sizes are adjusted to approximately twice in order to provide the same measurement condition as in  FIG. 11 . In other respects, the measurement condition is the same as in  FIG. 11 . As shown in  FIG. 12 , it, can be seen that the time difference ΔtPD according to the comparative example has high VDD dependence. The tendency varies with the temperature condition and the process condition. 
     While the description has dealt with the level shift circuit unit  410 , the level shift circuit unit  420  can also provide the foregoing effect since the level shift circuit unit  420  has exactly the same circuit configuration as that of the level shift circuit unit  410 . As shown in  FIG. 7 , the pull-up data DQP 0  output from the level shift circuit units  410  is input to the impedance control circuit  510  as pull-up data DQP 1  through the gate circuits  431  and  432 . The pull-down data DQN 0  output from the level shift circuit units  420  is input to the impedance control circuit  510  as pull-down data DQN 1  through the inverters  441  and  442 . 
     Turning to  FIG. 13 , the impedance control circuit  510  includes five OR circuits  521  to  525  (pull-up logic circuits) and five AND circuits  531  to  535  (pull-down logic circuits). The pull-up data DQP 1  from the level shift circuit unit  410  is supplied to the OR circuits  521  to  525  in common. Bits DRZQP 1  to DRZQP 5  of a pull-up impedance adjustment code DRZQP are also supplied to the OR circuits  521  to  525 , respectively. The pull-down data DQN 1  from the level shift circuit unit  420  is supplied to the AND circuits  531  to  535  in common. Bits DRZQN 1  to DRZQN 5  of a pull-down impedance adjustment code DRZQN are also supplied to the AND circuits  531  to  535 , respectively. The pull-up impedance adjustment code DRZQP and the pull-down impedance adjustment code DRZQN are signals that constitute the impedance code ZQCODE. The pull-up impedance adjustment code DRZQP and the pull-down impedance adjustment code DRZQN are supplied from the calibration circuit  66  shown in  FIG. 1 . 
     Outputs signals of the OR circuits  521  to  525 , or pull-up data DQP 11  to DQP 15 , and output signals of the AND circuits  531  to  535 , or pull-down data DQN 11  to DQN 15 , are supplied to the output buffer  501 . 
     Turning to  FIG. 14 , the output buffer  501  includes five P-channel MOS transistors  541  to  545  which are connected in parallel, and five N-channel MOS transistors  551  to  555  which are connected in parallel. Sources of the P-channel MOS transistors  541  to  545  are connected to the VDDQ line  17   c.  Sources of the N-channel MOS transistors  551  to  555  are connected to the VSSQ line  17   d.  Resistors  561  and  562  are connected in series between the transistors  541  to  545  and the transistors  551  to  555 . A node between the resistors  561  and  562  is connected to the data input/output terminal  14 . 
     The pieces of pull-up data DQP 11  to DQP 15  are supplied to gates of the transistors  541  to  545 , respectively. The pieces of pull-down data DQN 11  to DQN 15  are supplied to gates of the transistors  551  to  555 , respectively. Consequently, the ten transistors included in the output buffer  501  are individually controlled ON/OFF by the ten pieces of data DQP 11  to DQP 15  and DQN 11  to DQN 15 . 
     The transistors  541  to  545  and the resistor  561  included in the output buffer  501  constitute a pull-up circuit PU. The transistors  551  to  555  and the resistor  562  included in the output buffer  501  constitute a pull-down circuit PD. The pull-up circuit PU and the pull-down circuit PD are designed to have a desired impedance when conducting. Transistors can vary in ON resistance depending on the manufacturing condition as well as ambient temperature and power supply voltage during operation. It is therefore not always possible to provide a desired impedance. To actually provide an impedance of desired value, the number of transistors to turn ON needs to be adjusted. The parallel circuits of the plurality of transistors are used for that purpose. 
     The impedance can be finely adjusted over a wide range by giving respective different W/L ratios (gate width/gate length ratios) to the plurality of transistors constituting a parallel circuit, with weights of powers of two in particular. In view of this, in the present embodiment, the transistors  542  to  545  are given W/L ratios of 2WLp, 4WLp, 8WLp, and 16WLp, respectively, where 1WLp is a W/L ratio of the transistor  541 . Using the pull-up impedance adjustment code DRZQP, the transistor(s) to turn ON can be appropriately selected to fix an ON resistance of the pull-up circuit PU to a desired impedance regardless of variations due to the manufacturing condition and changes in temperature. 
     As with the transistors  541  to  545 , it is also preferred hat the transistors  551  to  555  have W/L ratios with weights of powers of two in particular. Specifically, the transistors  552  to  555  are given W/L ratios of 2WLn, 4WLn, 8WLn, and 16WLn, respectively, where 1WLn is a W/L ratio of the transistor  551 . Using the pull-down impedance adjustment code DRZQN, the transistor(s) to turn ON can be appropriately selected to fix an ON resistance of the pull-down circuit PD to a desired impedance regardless of variations due to the manufacturing condition and changes in temperature. 
     The configuration of the semiconductor device  10  according to the present embodiment has been described so far. Since the semiconductor device  10  according to the present embodiment uses the level shift block  400  that has little difference between the rising and falling characteristics, the read data DQ and the strobe signal DQS can be output with improved signal quality. It is therefore possible to insert the level shift circuit units  410  and  420  into the paths of the signals that are adjusted in timing by the multiplexer  300  (pull-up data DQP and pull-down data DQN). This means that the circuits operating on the external voltage VDD can be reduced further to reduce power consumption and lessen the effect of variations in the external voltage VDD. 
     More specifically, if the signals adjusted in timing by the multiplexer  300  are subjected to level shifting to change in duty cycle, such a change is not able to be corrected by the DLL circuit  100 . Level shift circuits having a large difference between rising and falling characteristics therefore can only be arranged in a stage prior to the multiplexer. Such arrangement leads to increased power consumption. In contrast, in the semiconductor device  10  according to the present embodiment, the level shift circuits can be arranged in a stage subsequent to the multiplexer to achieve the foregoing effects. 
     In the present embodiment, the clock dividing circuit  200  operates on the internal power supply voltage VPERI 2 , and the multiplexer  300  operates on the internal power supply voltage VPERI 3 . Such configuration prevents the interaction of noise occurring from the circuit blocks. In addition, the internal power supply voltages VPERI 2  and VPERI 3  are separated from the internal power supply voltage VPERI which is used in other peripheral circuits such as the FIFO circuit  65 . Consequently, the effect of noise is also reduced between other peripheral circuits and the clock dividing circuit  200  and multiplexer  300 . 
     It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. 
     For example, the level shift circuits LV 1  and LV 2  are not limited to the circuit configuration shown in  FIGS. 9A and 9B , respectively. Other circuit configurations may be employed. For example, the circuit configuration shown in  FIG. 15  may be used. The circuit configuration shown in  FIG. 16  may be used. 
     The level shift circuit LV 3  shown in  FIG. 15  differs from the level shift circuit LV 1  shown in  FIG. 9A  in that there are additional N-channel MOS transistors  417  and  418 . The transistor  417  is connected in parallel with the transistor  411 . A gate electrode of the transistor  417  is connected to that of the transistor  414 . The transistor  418  is connected in parallel with the transistor  412 . A gate electrode of the transistor  418  is connected to that of the transistor  413 . The level shift circuit LV 3  having such a configuration can be used to further reduce the difference between the rising and falling characteristics. 
     The level shift circuit LV 4  shown in  FIG. 16  differs from the level shift circuit LV 1  shown in  FIG. 9A  in that there is an additional P-channel MOS transistor  419 . The transistor  419  is connected between the common source VDD of the transistors  411  and  412  and the VDD line  17   a.  A bias signal PBIAS is supplied to a gate electrode of the transistor  419 . The level shift circuit LV 4  having such a configuration can be used to improve the signal transition rate. 
     In the present invention, it is not absolutely necessary to use the respective different power supply circuits  81  to  84  to generate the internal power supply potentials VPERI, VPERI 2 , VPERI 3 , and VPERDL and separate the internal power supply potentials in the semiconductor device.