Patent Publication Number: US-7582519-B2

Title: Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
   This application is a division of U.S. application Ser. No. 10/288,982, filed Nov. 5, 2002, which is incorporated by reference in its entirety for all purposes. 

   BACKGROUND OF THE INVENTION 
   The present invention relates in general to semiconductor technology and in particular to high-voltage semiconductor structures and methods of manufacturing the same. 
     FIG. 1  shows a cross-section view of a portion of a conventional power MOSFET having a buried-gate structure. A highly-doped substrate  102  forms the drain contact for MOSFET  100 . An epitaxial layer  104  formed over substrate  102  includes source regions  124   a,b  formed in body regions  108   a,b . Body regions  108   a,b  are flanked on one side by gate trench  119 . P+ regions  126   a,b  form the areas through which contact is made to body regions  108   a,b . Gate trench  119  is filled with polysilicon forming the MOSFET gate  118 . When MOSFET  100  is turned on, current travels in a vertical direction from source regions  124   a,b  along a channel parallel to the sidewalls of gate trench  119  to the backside drain. 
     FIG. 2  shows a cross-section view of a conventional MOSFET  200  with planar gate structure. A highly doped substrate  202  forms the drain contact for MOSFET  200 . An epitaxial layer  204  formed over substrate  202  includes source regions  224   a,b  formed in body regions  208   a,b . P+ regions  226   a,b  form the areas through which contact is made to body regions  208   a,b . The MOSFET gate  218  is formed on top of the silicon surface instead of being recessed in a trench. When MOSFET  200  is turned on, current flows from source regions  224   a,b  along a channel beneath gate  118  and then vertically through drift region  206  to the backside drain. 
   The structures shown in  FIGS. 1 and 2  are typically repeated many times to form an array of cells. The array may be configured in various cellular or stripe layouts known to one skilled in this art. These and other types of power devices have long been known. Recent advances in semiconductor manufacturing have increased the density (i.e., the number of cells in a given silicon area) of devices. However, the higher density does not necessarily improve power loss in mid to high voltage range (e.g., 60 to 2000 volts) devices. In such devices, the power loss is primarily due to the high resistivity of the drift region (e.g., region  106  in  FIG. 1 ). Drift regions have high resistivity because in order for the device to sustain the high voltages during the blocking state, the drift region is lightly doped. The high resistivity of the drift region results in a higher on-resistance, which in turn results in high power loss. Since a high blocking voltage is a critical feature for mid to high voltage power devices, increasing the drift region doping is not an option. Similar issues are present in power diode devices. 
   Attempts have been made to improve the device power loss while maintaining a high blocking voltage. In one approach, columnar opposite polarity regions extending parallel to the current flow are formed between the body-gate structure at the top and the substrate at the bottom. The columnar opposite polarity regions prevent the electric field from decreasing linearly away from the base-drift junction, thus allowing the device to support higher blocking voltages. This technique however depends on charge balance between the conduction and opposite polarity regions and thus requires precise doping control of the opposite polarity regions. The opposite polarity regions are formed before the diffused base and source regions. When the base and source regions are annealed during a thermal cycle, the dopants in the opposite polarity regions undesirably diffuse into each other. This dopant inter-diffusion makes the thermal processing difficult and limits shrinking of the cell pitch. The inability to shrink the cell pitch is especially problematic in mid to low voltage devices in which the power loss occurs primarily in the channel region rather than in the drift region. In the mid to low voltage devices, the power loss in the channel region is typically countered by making the cell pitch as small as possible so that a large number of cells can be formed in the same silicon area. The columnar opposite polarity regions technique is thus unattractive for mid to low voltage devices as it can not be shrunk. 
   Thus, a technique which enables achieving a high device blocking capability, low on-resistance, and high current handling capability without preventing the cell pitch to be shrunk is desirable. 
   BRIEF SUMMARY OF THE INVENTION 
   In accordance with an embodiment of the present invention, a semiconductor structure is formed as follows. A semiconductor region is formed to have a P-type region and a N-type region forming a PN junction therebetween. A first trench extending in the semiconductor region is formed adjacent at least one of the P-type and N-type regions is formed. At least one diode is formed in the trench. 
   In one embodiment, an insulating layer extending along sidewalls of the first trench but being discontinuous along the bottom of the first trench is formed. 
   In one embodiment, the semiconductor region is an epitaxial layer which is formed over and in contact with a substrate. The epitaxial layer has the same conductivity type as the substrate. 
   In another embodiment, a body region is formed in the epitaxial layer. The body region is one of the P-type and N-type regions and the other one of the P-type and N-type regions forms a drift region. The diode is arranged in the first trench such that when the semiconductor structure is biased in a blocking state an electric field induced in the at least one diode influences an electric field in the drift region to thereby increase the blocking voltage of the semiconductor structure. 
   The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1 and 2  show cross-section views of two conventional MOSFET structures; 
       FIGS. 3A and 3B  show cross-section views of two embodiments of the trench structure in accordance with the present invention; 
       FIGS. 3C-3E  are top views of three exemplary layout designs of the structures shown in  FIGS. 3A and 3B ; 
       FIGS. 4-6  show cross-section views of three exemplary vertical MOSFET structures having diode trenches in accordance with the present invention; 
       FIGS. 7A ,  7 B, and  7 C respectively show a top view, a cross-section view along  7 B- 7 B line in  FIG. 7A , and a cross section view along  7 C- 7 C line in  FIG. 7A  of a lateral MOSFET structure having diode trenches in accordance with the present invention; 
       FIG. 8  shows a cross-section view of a rectifier having diode trenches in accordance with the present invention; and 
       FIGS. 9 and 10  are graphs respectively showing the electric field through diode trenches and drift regions of an exemplary embodiment of the  FIG. 4  MOSFET structure. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Embodiments of a trench having one or more diodes embedded therein and methods of forming the same are described in accordance with the invention. The diode trench structure can be used in semiconductor devices required to withstand high voltages. The diode trench helps achieve high current capability, high breakdown voltage, low forward voltage drop, and a small cell pitch. 
     FIG. 3A  shows a cross-section view of a semiconductor structure  300  having a trench  310  in accordance with one embodiment of the present invention. An epitaxial layer  304  is formed over and is of the same conductivity type as a substrate  302 . Regions  308   a,b  of opposite conductivity type to epitaxial layer  304  is formed along a top portion of epitaxial layer  304 . Trench  310  extends from a top surface of epitaxial layer  304  through to substrate  310 . Trench  310  may alternatively be terminated at a shallower depth (i.e., within regions  306   a,b  of epitaxial layer  304 .) Trench  310  includes a diode made up of opposite conductivity type regions  312  and  314  forming a PN junction  313  therebetween. Doped polysilicon or N-type and P-type silicon may be used to form regions  312  and  314 . Other material suitable for forming such diode (e.g., Silicon Carbide, Gallium Arsenide, Silicon Germanium) may also be used. 
   Insulating layer  316  extending along the trench sidewalls insulates the diode in the trench from regions  306   a,b  and P  308   a,b  in epitaxial layer  304 . Oxide may be used as insulating layer  316 . As shown, there is no insulating layer along the bottom of the trench thus allowing the bottom region  312  of the trench diode to be in electrical contact with the underlying substrate  302 . In one embodiment, similar considerations to those dictating the design and manufacture of the gate oxide of MOS transistors are applied in designing and forming insulating layer  316 . For example, as in gate oxide of MOS transistors, the thickness of insulating layer  316  is determined by such factors as the voltage that insulating layer  316  is required to sustain and the extent to which the electric field in the trench diode is to be induced in regions  306   a,b  (i.e., the extent of coupling through the insulating layer). 
   Although regions  312  and  314  in trench  310  are shown to be N-type and P-type respectively, their conductivity type may be reversed. Also, either of regions  312  and  314  may be independently biased if desired by, for example, extending one or both regions along the third dimension (i.e., perpendicular to the page) and then up to the silicon surface where contact can be made to them. Although only two regions of opposite conductivity is shown in trench  310 , three regions forming an NPN or PNP stack, or any number of regions of alternating conductivity may be formed in trench  310 . Further, multiple trenches may be used as needed. Substrate  302  and regions  306   a,b  are shown to be of N-type conductivity and regions  308   a,b  of P-type conductivity. Alternatively, these regions may be of opposite conductivity type as shown in the parentheses in  FIG. 3A . 
   Structure  300  may be incorporated in any power device such as a power MOSFET or a power diode. In any of these devices, when the device is biased to be in the blocking state (e.g., when a MOSFET is turned off, or a diode is reverse biased), PN junction  307  is reverse biased and is required to sustain high voltages. As is well-known in this art, under reverse-bias conditions, the electric field is highest at junction  307  and linearly reduces in N-type region  306   a,b  and P-type  308   a,b  in the direction away from junction  307  at a rate dictated by the doping concentration of the P-type and N-type regions. It is also well known that the larger the area under the electric field curve (i.e., the lower the rate at which the electric field reduces), the greater is the breakdown voltage. During operation, the diode embedded in trench  310 , similar to PN junction  307 , is reverse biased and thus the electric field is highest at the diode junction  313 . Through insulating layer  316 , the electric field in the trench diode induces a corresponding electric field in N-type regions  306   a,b . The induced field is manifested in N-type regions  306   a,b  in the form of an up-swing spike and a general increase in the electric field curve in N-type regions  306   a,b . This increase in the electric field results in a larger area under the electric field curve which in turn results in a higher breakdown voltage. 
   It can be seen that by using multiple diodes in trench  310 , multiple spikes can be induced along the depth of N-type regions  306   a,b  (this is explained in more detail in reference to  FIGS. 9 and 10  further below). This results in an electric field curve which tapers down from its highest level at junction  307  at a far lower rate than in conventional structures. An almost square-shaped area can thus be obtained under the electric field curve in N-type regions  306   a,b  as opposed to the conventional triangular shape. A far greater breakdown voltage can thus be obtained. 
   When structure  300  is biased in the conduction state (e.g., when a MOSFET is turned on or a diode device is forward biased) current passes through N-type regions  306   a,b . In conventional structures such as structure  100  in  FIG. 1 , during the conduction state, junction  107  is reverse biased and the amount of charge in the corresponding depletion region linearly decreases from junction  107  toward the edge of the depletion region in N-type region  106 . However, by introducing diode trench  310 , the electric filed across the reverse-biased trench diode influences the charge distribution in N-type regions  306   a,b  such that a more uniform charge spreading is obtained in N-type regions  306   a,b . That is, the amount of charge in the depletion region remains relatively uniform across N-type regions  306   a,b . By spreading the charge more uniformly in N-type regions  306   a,b , the silicon area taken up by N-type regions  306   a,b  is more efficiently used. Hence, for the same size N-type regions  306   a,b , the portion of the device on-resistance attributable to regions  306   a,b  is, in effect, reduced. This enables reducing the cell pitch for the same on-resistance. 
   Accordingly, diode trench  310  enables optimizing structure  300  to have higher breakdown voltage, lower on-resistance, and smaller cell pitch than can be achieved by conventional techniques. 
   A method of forming structure  300  in accordance with one embodiment of the invention is as follows. An epitaxial layer  304  is formed over substrate  302  using conventional methods. A blanket P-well implant is carried out in accordance with known implant techniques. An anneal step may be carried out to drive the P-well deeper into epitaxial layer  304  and to activate the P dopants. A trench mask defining a trench opening is then formed by depositing and patterning a photoresist layer. Silicon is removed from the defined trench opening to form trench  310 . The trench surfaces are then cleaned and a thin layer of thermal oxide is grown inside the deep trenches. A thicker (e.g. 200-600 nm) insulating layer (e.g., CVD oxide) is then deposited over the thin layer of thermal oxide. The sidewalls of the trench are thus coated with an insulating layer. The insulating material along the bottom of the trench is then removed. A suitable spacer material (e.g., nitride) may be used to protect the insulating material along the trench sidewalls during removal of insulation material at the trench bottom. In the embodiment wherein doped polysilicon is used to form the trench diode, the diode is formed by performing a two step process of polysilicon deposition followed by polysilicon etch for each region of the diode. In the embodiment wherein the trench diode is from silicon material, the diode is formed by performing silicon deposition for each diode region using conventional selective epitaxial growth techniques. The steps for forming the diode can be repeated to form additional diodes in the trench. If a large number of stacked polysilicon diodes is required, a cluster tool commonly used to combine the steps of polysilicon deposition and polysilicon etch may be used to speed up the processing time. 
   In an alternate embodiment, the process steps are reversed in that the diode trench is formed first (using the same steps outlined above) and then the P-well is formed (using the same process steps outlined above). 
   By properly designing the P-type and N-type regions of the trench diode, the trench diode&#39;s advantageous impact on charge spreading in N-type regions  306   a,b  can be enhanced. Two factors impacting the charge spreading are the avalanche breakdown voltage of the trench diode and the width of the depletion region in the trench diode. For example, by selecting proper doping concentration for each of the P-type and N-type regions of the trench diode, a high avalanche breakdown voltage can be obtained so that a maximum electric field of much greater magnitude than the conventional 2×10 5  V/cm can be obtained. The only limitation in obtaining the maximum electric field then becomes the ability of insulating layer  316  to withstand high voltages. This limitation can however be eliminated by the proper design of insulating layer  316 . Typical gate oxide layers have a maximum electric field exceeding 3.5×10 5 V/cm which suffices for many high voltage applications. 
   In another embodiment shown in  FIG. 3B , trench  310  is terminated at a shallower depth within (e.g., in the middle of) N-type region  306 . P-type region  314  fills the entire trench. In this embodiment, although a diode is not embedded within the trench, a diode is nevertheless formed by P-type region  314  and the underlying N-type region  306 . During operation, this diode influences N-type region  306  in a similar manner to the diode embedded in the  FIG. 3A  trench  310 . 
   The spacings and trench diode arrangement can be implemented in various stripe or cellular designs. A top view of three exemplary designs is shown in  FIGS. 3C ,  3 D, and  3 E. In  FIG. 3C , trenches  310   c  are offset from one another, while  FIG. 3E  shows trenches  310   e  to be aligned and arranged along rows and columns. In  FIG. 3D , horizontally-extending diode trenches  310   d  are arranged as parallel stripes. Diode regions  314   d  insulated from one another by insulating material  316   d  are laterally spaced from each other in each trench stripe  310   d . Although the trench regions and the diode regions embedded therein are shown as square or rectangular shaped regions, they may be designed as circular, oval, hexagonal, or any other geometric shape that is desired. Thus, many different designs, configurations, and geometric shapes can be envisioned by one skilled in the art in light of this disclosure. 
     FIG. 4  shows a cross-section view of a dual-trench MOSFET  400  in accordance with an embodiment of the present invention. A highly-doped substrate  402  forms the drain contact for MOSFET  400 . An epitaxial layer  404  formed over substrate  402  includes source regions  424   a,b  formed in body regions  408   a,b . Body regions  408   a,b  are flanked by gate trench  419  on one side and diode trenches  410   a,b  on the other. P+ regions  426   a,b  form the areas through which contact is made to body regions  408   a,b . The portion of epitaxial layer  404  bounded by diode trenches  410   a,b  along the sides, body regions  408   a,b  and gate trench  419  along the top, and substrate  402  along the bottom forms drift region  406 . The gate structure is similar to the gate structure in the prior art  FIG. 1  structure  100 . Metal layer  428  extends along the top and makes contact with sources  424   a,b , P+ regions  426   a,b , and the top of diode trenches  410   a,b , but is isolated from gate  418  by insulating layer  422 . Metal layer  430  makes contact to substrate  402  along the bottom and forms the drain electrode. 
   Diode trenches  410   a,b  extend from the top surface of epitaxial layer  404  to the bottom of drift region  406 . Diode trenches  410   a,b  include a stack of alternating P-type region  412  and N-type region  414  forming a number of serially-connected diodes  432 . The trench diodes are insulated from drift region  406  by an insulating layer  416  extending along the trench sidewalls. Insulating layer  416  however, is discontinuous along the bottom of diode trenches  410   a,b  to allow the bottom-most region in the diode trenches to make electrical contact with its underlying region (e.g., with drift region  406  or substrate  402 ). 
   The diodes in trenches  410   a,b  are reverse-biased during MOSFET operation. In the  FIG. 4  implementation, this is achieved by connecting the top-most region in trenches  410   a,b  to the source and the bottom-most region to the drain. Alternatively, the top-most region may be connected to a low potential (e.g., ground) separate from the source or even allowed to float, and the bottom-most region may be connected to a high potential separate from the drain. Generally, reverse biasing of the diodes can be achieved by connecting any of the N-type regions in the diode trenches to a high potential, or alternatively connecting any of the P-type regions in the trenches to a low potential. Any one or more of the P-type and N-type regions in the diode trenches can be independently biased by, for example, extending the one or more regions along the third dimension (i.e., perpendicular to the page) and then up to the silicon surface where contact can be made to them. 
   The operation of vertical MOSFET  400  is similar to that of the prior art  FIG. 1  and thus will not be described. However, the advantageous impact of diode trenches  410   a,b  on the performance characteristics of MOSFET  400  is described next using the graphs in  FIGS. 9 and 10 . The graphs in  FIGS. 9 and 10  are obtained from simulation results, and show the electric field curve through diode trenches  410   a,b  and drift zone  406  of an exemplary MOSFET similar in structure to MOSFET  400 , respectively. The vertical axis in  FIGS. 9 and 10  represents electric field and the horizontal axis represents dimension. In  FIG. 9 , the horizontal axis from left to right corresponds to the vertical dimension through the diode trench from top to bottom. In  FIG. 10 , the horizontal axis from left to right corresponds to the vertical dimension from body-drift junction  407  to the drift-substrate junction. The following table sets forth the values used for some of the simulation parameters. These values are merely exemplary and not intended to be limiting. 
   
     
       
         
             
             
             
           
             
                 
                 
             
             
                 
               Parameter 
               Value 
             
             
                 
                 
             
           
          
             
                 
             
          
         
         
             
             
             
             
          
             
                 
               Epi doping 
               2 × 10 15   
               cm −3   
             
             
                 
               Diode doping (N-type and P-type) 
               1 × 10 16   
               cm −3   
             
             
                 
               Thickness t 1  of each of the N-type and P- 
               0.5 
               μm 
             
             
                 
               type regions in diode trenches 
             
             
                 
               Thickness of oxide along trench sidewalls 
               500 
               Å 
             
             
                 
               Thickness of gate oxide 
               500 
               Å 
             
             
                 
                 
             
          
         
       
     
   
   As shown in the  FIG. 9  graph, the reverse-bias across the trench diodes results in an electric field peak at each diode junction (e.g., junction  413 ) as expected. Each of these electric field peaks induces a corresponding electric filed increase (peak) in a corresponding area of drift region  406  as shown in the  FIG. 10  graph. An almost square-shaped area under the electric field curve is thus obtained ( FIG. 10 ), which is substantially greater than the area under the triangular-shaped curve for conventional MOSFET structures. Thus, a substantial increase in the breakdown voltage is achieved. The larger the number of diodes embedded in the trench, the greater would be the number of peaks in the electric filed in the drift region, and thus the higher would be the area under the curve. The higher breakdown voltage enables the doping concentration of drift region  406  (conventionally kept low to obtain the necessary breakdown voltage) to be increased to reduce the on-resistance, if desired. 
   As described above in reference to the structure in  FIG. 3A , during the on state of MOSFET  400 , the electric field across the trench diodes influences the charge distribution in drift region  406  such that a more uniform charge spreading is obtained in drift region  406 . The uniform charge spreading results in a more efficient use of the drift region silicon area. Thus, for the same on-resistance of, for example, the prior art  FIG. 1  structure, the cell pitch of the  FIG. 4  structure can be made smaller. The width of the diode trenches can be made as small as the process technology allows to minimize its impact on the cell pitch. 
   A method of forming structure  400  in accordance with one embodiment of the invention is as follows. Conventional process steps are carried out to form the buried gate structure  419 , including source regions  424   a,b , body regions  408   a,b , and P+ regions  426   a,b , in epitaxial layer  404 . Alternatively, the process steps outlined in the above-referenced U.S. patent application (Ser. No. 08/970,221, titled “Field Effect Transistor and Method of its Manufacture”), commonly assigned, may be carried out to form the gate structure. Next, the same process steps and variations thereof described above in connection with forming trench  310  ( FIG. 3A ) and the diode embedded therein may be used to form deep trenches  410   a,b  and the multiple diodes embedded in them. 
   Generally, the order in which diode trenches  410   a,b , body regions  408   a,b , and gate trench  419  are formed is not limited to a particular sequence. For example, an alternate sequence to that described above is: form the diode trenches first, the body regions second, and the gate trench third. Another sequence is: form the gate trench first, the body regions second, and the diode trenches third. Accordingly, there are six possible sequence permutations, any one of which may be used. 
     FIG. 5  shows a cross-section view of a MOSFET structure  500  in accordance with another embodiment of the present invention. A highly-doped substrate  502  forms an ohmic drain contact. An epitaxial layer  504  formed over substrate  502  includes source regions  524   a,b  formed in body regions  508   a,b . Body regions  508   a,b  are each flanked on one side by diode trenches  510   a,b . P+ regions  526   a,b  form the areas through which contact is made to body regions  508   a,b . The portion of epitaxial layer  504  bounded by diode trenches  510   a,b  along the sides, body regions  508   a,b  and gate  518  along the top, and substrate  502  along the bottom forms drift region  506 . The gate structure is planar similar to that shown in the  FIG. 2  prior art structure  200 . Metal layer  528  extends along the top and makes contact with sources region  524   a,b , P+ regions  526   a,b , and the top of trenches  510   a,b , but is isolated from gate  518  by insulating layer  522 . Metal layer  530  makes contact to substrate  502  along the bottom, forming the drain electrode. 
   Trenches  510   a,b  extend from the top surface of epitaxial layer  504  to the bottom of drift region  506 . Diode trenches  510   a,b  are similar in structure to those in the  FIG. 4  structure, and as such the same discussions provided above in connection with the  FIG. 4  trench structure applies here. Briefly, in  FIG. 5 , the trench diodes are insulated from drift region  506  by insulating layer  516  extending along the trench sidewalls. Insulating layer  516  however, is discontinuous along the bottom of the diode trenches so that the bottom-most region in the trenches makes electrical contact with its underlying region. 
   Similar to the diodes in trenches  410   a,b  ( FIG. 4 ), the diodes in trenches  510   a,b  are reverse-biased during MOSFET operation. Any one of the same techniques for reverse biasing the diodes in trenches  410   a,b  outlined above may be used here. 
   The operation of MOSFET  500  is similar to that of the prior art  FIG. 2  structure and thus will not be described. Diode trenches  510   a,b  influence the electric field and the charge distribution in drift region  506  in a similar manner to diode trenches  410   a,b  ( FIG. 4 ) so that a higher breakdown voltage, lower on-resistance, and smaller cell pitch is obtained as compared to the prior art  FIG. 2  structure. 
   A method of forming structure  500  in accordance with one embodiment of the invention is as follows. Conventional process steps are carried out to form the planar gate structure. Deep trenches are then etched in the space between the planar gate structures. The same process steps and variations thereof described above in connection with forming deep trenches  410   a,b  ( FIG. 4 ) and the diodes embedded therein may then be carried out to form deep trenches  510   a,b  and the diodes embedded therein. In an alternative embodiment, the process steps are reversed in that the deep trenches are formed first (using the same steps outlined above), and then the planar gate structure is formed between the diode trenches (using the same process steps outlined above). 
     FIG. 6  shows a cross-section view of another MOSFET structure  600  in accordance with another embodiment of the present invention. As shown, MOSFET gate  618  and trench diodes  632  are advantageously embedded in one trench  610  rather than two as in the  FIG. 4  structure  400 . This yields a highly compact cell structure while the same breakdown voltage and on-resistance improvements of prior embodiments are maintained. 
   As shown, a highly-doped substrate  602  forms the drain contact. An epitaxial layer  604  formed over substrate  602  includes source regions  624   a,b  formed in body regions  608   a,b . P+ regions  626   a,b  form the areas through which contact is made to body regions  608   a,b . Body regions  608   a,b  are separated by trench  610 . The portions of epitaxial layer  604  bounded by body regions  608   a,b , substrate  602 , and trench  610  form drift regions  606   a,b . The structural relation between gate  618  and the source, body regions is similar to those in the  FIG. 4  structure. 
   Trench  610  extends from the top surface of epitaxial layer  604  to the bottom of drift regions  606   a,b . The lower section of trench  610  wherein the diodes are embedded is similar in structure to diode trenches  410   a,b  ( FIG. 4 ), and as such the same discussions provided above in connection with the structure of trenches  410   a,b  applies here. Briefly, in  FIG. 6 , the diodes embedded in trench  610  are insulated from drift regions  606   a,b  by insulating layer  616  extending along the trench sidewalls. Insulating layer  616  however, is discontinuous along the bottom of the trench to allow the bottom-most region in the trench to make contact with its underlying region. Insulating layer  616  may be the same as or different from gate oxide  620 . Generally, insulating layer  616  needs to withstand the high voltage between the trench diode regions and drift regions  606   a,b . Metal layer  628  extends along the top and makes contact to sources  624   a,b  and P+ regions  626   a,b , but is insulated from gate  618  by insulating layer  622 . 
   Similar to the diodes in trenches  410   a,b  ( FIG. 4 ), the diodes in trench  610  are reverse-biased during MOSFET operation. Any one of the same techniques for reverse biasing the diodes in trenches  410   a,b  outlined above may be used here. 
   The operation of MOSFET  600  is similar to that of the prior art  FIG. 1  structure and thus will not be described. Diode trench  610  influences the electric field and the charge distribution in drift regions  606   a,b  in a similar manner to diode trenches  410   a,b  ( FIG. 4 ) so that a high breakdown voltage, low on-resistance, and small cell pitch are obtained. 
   A method of forming structure  600  in accordance with one embodiment of the invention is as follows. An epitaxial layer  604  is formed over substrate  302  using conventional methods. A blanket P-well implant is carried out in accordance with known implant techniques to form a P-well. An anneal step may be carried out to drive the P-well deeper into epitaxial layer  604  and to activate the P dopants. A trench mask defining a trench opening is then formed by depositing and patterning a photoresist layer. Silicon is removed from the defined trench opening to form trench  610 . The trench surfaces are then cleaned and a thin layer of thermal oxide is grown inside the deep trenches. A thicker (e.g. 200-600 nm) insulating layer (e.g., CVD oxide) is then deposited over the thin layer of thermal oxide. The sidewalls of the trench are thus coated with an insulating layer. The insulating material along the bottom of the trench is them removed. A suitable spacer material (e.g., nitride) may be used to protect the insulating material along the trench sidewalls during removal of insulation material at the trench bottom. 
   Although the above process steps results in insulating layers  616  and  620  to be the same, modifying the process steps so that these two insulating layers are different would be obvious to one skilled in this art. Next, the same process steps and variations thereof described above in connection with forming the diode in trench  310  ( FIG. 3A ) may be used to form the multiple diodes shown in trench  610 . After forming the diodes, an insulating layer is formed over the top of the diode structure. Gate  618  is then embedded in trench  610  using conventional methods. In an alternative embodiment, the process steps are reversed in that the deep trench is formed first (using the same steps outlined above) and then body regions  608   a,b  are formed. 
     FIG. 7A  shows a top view partial-layout diagram of a lateral MOSFET structure having diode trenches in accordance with the present invention.  FIGS. 7B and 7C  show cross-section views across  7 B- 7 B and  7 C- 7 C lines in  FIG. 7A , and will be used together with the  FIG. 7A  top view to describe the structure of and method of forming the lateral MOSFET. As shown in these figures, both source region  724  and drain region  760  are formed along the same surface as opposed to two opposing surfaces as in the vertical structures. Thus, the current conduction occurs laterally along the top surface, hence “lateral MOSFET”. In  FIG. 7A , three trenches  710  are shown extending from drain region  760  to source region  724  through drift region  706  and body region  708 . A number of P-type and N-type regions are alternately arranged adjacent one another forming a number of serially-connected diodes in each trench  710 . The P-type and N-type regions are insulated from the drift region  706  and body region  706  by an insulating layer  716  extending along the bottom and sidewalls of trenches  710 . Insulating layer  716  however does not extend along the trench sidewalls at the lateral ends of the trenches where they terminate in drain region  760  and body region  708 . This allows the last diode region on each end of each trench to make electrical contact with its adjacent region (i.e., with drain region  760  on the right side and with source region  724  on the left side). 
   Line  7 B- 7 B extends through the channel region, and the corresponding cross-section view shown in  FIG. 7B  is similar to that for conventional lateral MOSFET structures. The operation of this structure is thus similar to conventional lateral MOSFETs. 
   Line  7 C- 7 C extends through one of the trenches  710 , and the corresponding cross-section view is shown in  FIG. 7C . An epitaxial layer  704  formed over substrate  702  includes body region  708  and drain region  760 . P+ region  726  (the area through which ohmic contact is made to body region  708 ) and source region  724  are formed in body region  708 . The portion of epitaxial layer  704  below and between body region  708  and drain region forms drift region  706 . The gate structure is planar and is similar to that in conventional lateral MOSFETs except that gate  718  also extends over portions of diode trenches  710  as shown in  FIG. 7A . Metal layer  728  makes contact with source region  724  and P+ region  726  but is isolated from gate  718  by insulating layer  722 . Metal layer  730  makes contact to drain region  760 . 
   The diodes in trenches  710  are reverse-biased during operation. This is achieved by having the right-most region in trenches  710  in contact with drain region  760  and the left-most region in contact with source region  724 . Alternatively, the left-most region may be insulated from source region  724  and then connected to a low potential (e.g., ground) or even allowed to float. Also, the right-most region may be connected to a high potential separate from the drain. Generally, reverse biasing of the diodes can be achieved by connecting any of the N-type regions in the diode trenches to a high potential, or alternatively connecting any of the P-type regions in the trenches to a low potential. 
   During operation, diode trenches  710  influence the electric field and the charge distribution in drift region  706  in a similar manner to diode trenches  410   a,b  ( FIG. 4 ) so that a higher breakdown voltage, lower on-resistance, and smaller cell pitch is obtained as compared to the conventional lateral MOSFET structures. 
   Although  FIGS. 7A-7C  show diode trenches  710  abutting source region  724 , these trenches may alternatively terminate in body region  708  near the body-drift junction. This however requires that the left-most diode region be of the same conductivity type as body region  708  to eliminate any breakdown issues at the junction between the body region and the left-most diode region. Alternatively, insulating layer  716  may be extended along the left-end sidewall of the trenches so that the left-most diode region in the trenches is insulated from the source and body regions. In yet another embodiment, insulating layer  716  may be formed along all four sidewalls of the trenches so that the diodes are completely insulated on all sides. This however requires that access be provided to at least one of the diode regions in each trench so that the diodes can be reverse biased during operation. Such access may be provided along the top side of the structure by creating one or more openings in the insulating layer  722  and electrically contacting one or more of the diode regions in the trench. 
   A method of forming the lateral MOSFET structure shown in  FIGS. 7A-7C  in accordance with one embodiment of the invention is as follows. An epitaxial layer  704  is formed over substrate  702  using conventional methods. A trench mask defining trench openings is then formed by depositing and patterning a photoresist layer. Silicon is removed from the defined trench openings to form trenches in the epitaxial layer. The trench surfaces are then cleaned and a thin layer of thermal oxide is grown inside the deep trenches. A thicker (e.g. 200-600 nm) insulating layer (e.g., CVD oxide) is then deposited over the thin layer of thermal oxide. The sidewalls and bottom of the trenches are thus coated with an insulating layer. The insulating material along two sidewalls (i.e., those closest to where the drain and source regions are later formed) are removed. A suitable spacer material (e.g., nitride) may be used to protect the insulating material along the other two sidewalls and the bottom of the trenches during removal of insulation material. 
   If polysilicon is to be used in forming the trench diodes, polysilicon is first deposited and then a planarization etch is carried out so that only those portions of the polysilicon filling the trenches remain. If the deposited polysilicon is doped polysilicon, a masking and implanting sequence of steps is carried out to form the diodes (i.e., to form alternating regions of opposite conductivity). If the deposited polysilicon is undoped, then the masking and implanting sequence of steps need to be carried out twice to create the regions of opposite conductivity. If silicon is to be used in forming the trench diodes, silicon is deposited in the trenches followed by one or two sets of masking and implanting sequence of steps (depending on whether the deposited silicon is doped) to create the alternating regions of opposite conductivity type. 
   Next the gate oxide and the overlying gate are formed in accordance with conventional methods. Using a mask, a blanket P-well implant is carried out in accordance with known implant techniques to form a P-well. An anneal step may be carried out to drive the P-well deeper into epitaxial layer  304  and to activate the P dopants. Source region  724 , drain region  760 , and P+ region  726 , insulating layer  722 , and metal layers  728  and  730  are then formed in accordance with conventional methods. 
   In one embodiment, a buried layer is formed between substrate  702  and drift region  706 , wherein the buried layer has a conductivity type opposite that of the substrate and drift region. In another embodiment, the lateral MOSFET structure is formed using silicon-on-insulator (SOI) technology. In this embodiment, an insulating layer would be present between drift region  706  and substrate  702 . 
     FIG. 8  shows a cross-section view of a power diode device  800  in accordance with an embodiment of the present invention. A highly-doped substrate  802  forms the cathode contact. An epitaxial layer  804  formed over substrate  802  includes P-well regions  808  each being flanked on the sides by trenches  810 . The regions of epitaxial layer  804  bounded by trenches  810  along the sides, P-well regions  808  along the top, and substrate  802  along the bottom form drift regions  806 . Metal layer  828  makes contact to P-well regions  808  and the top surface of trenches  810 , and forms the anode electrode. Metal layer  830  extends along the bottom and makes contact to substrate  802 , forming the cathode electrode. 
   Trenches  810  extend from the top surface of epitaxial layer  804  to the bottom of drift region  806 . Trenches  810  are similar in structure to trenches  410   a,b  ( FIG. 4 ), and as such the same discussions provided above in connection with trenches  410   a,b  apply here. Briefly, in  FIG. 8 , the diodes in trenches  810  are insulated from P-well regions  808  and drift regions  806  by insulating layer  816  extending along the trench sidewalls. Insulating layer  816  however, is discontinuous along the bottom of the trenches so that the bottom-most region in the trenches makes electrical contact with its underlying region. 
   Similar to the diodes in trenches  410   a,b  ( FIG. 4 ), the diodes in trenches  810  are reverse-biased during device operation. Any one of the same techniques for reverse biasing the diodes in trenches  410   a,b  outlined above may be used to ensure that the diodes in trenches  810  are reverse-biased during operation. 
   Trenches  810  influence the electric field and the charge distribution in drift regions  806  in a similar manner to diode trenches  410   a,b  ( FIG. 4 ) so that a higher breakdown voltage, lower on-resistance, and smaller cell pitch is obtained as compared to conventional power diodes. The same process steps and variations thereof described above in connection with forming structure  300  ( FIG. 3 ) may be used to form structure  800 . 
   Although the invention has been described using different NMOS power devices and a power diode, its implementation in other types of known power devices (e.g., lateral diodes, bipolar transistors, other MOS-gated devices such as IGBTs) would be obvious to one skilled in this art in view of this disclosure. Further, other than high voltage devices, the structure and method of the present invention can be used to implement mid to low voltage (e.g., &lt;200V) devices. As is well known in this art, in contrast to high-voltage power devices wherein the majority of the losses occur in the drift region, in mid to low voltage devices, the majority of losses occur in the channel region. The present invention lends itself well to implementing mid to low voltage devices in that the cell pitch can be substantially reduced (as described above) so that a larger number of cells can be formed in a give silicon area, and thus the losses in the channel region are reduced. 
   While the above is a complete description of the embodiments of the present invention, it is possible to use various alternatives, modifications and equivalents. For example, in an alternative implementation of the  FIGS. 4 ,  5 ,  7 , and  8  structures, only one region may be used in the portion of the diode trench(es) extending from the side of the trench closest to the source region to the vicinity of the edge of the drift-body junction. For example, in  FIGS. 4 ,  5 , and  8  the top three regions in the diode trench(es) may be replaced with one elongated P-type or N-type region. Alternatively, an insulating material (e.g., oxide) may be used in place of the elongated P-type region. In either case, the number of processing steps associated with forming the diodes in the trench(es) is reduced without adversely impacting the performance of the different structures. In yet another implementation of the diode trench(es) in  FIGS. 4-6  and  8  rather than extending the trench(es) clear through the drift region, they may be terminated at a shallower depth within (e.g., in the middle of) the drift region if desired. Similarly, in  FIG. 7C , the diode trenches may be terminated within epitaxial layer  706  rather than extend all the way to drain region  760 . The cross-section views of the different embodiments may not be to scale, and as such are not intended to limit the possible variations in the layout design of the corresponding structures. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claim, along with their full scope of equivalents.