Patent Publication Number: US-6709978-B2

Title: Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer

Description:
This application is a Divisional of U.S. application Ser. No. 09/009,791 now U.S. Pat. No. 6,198,168 filed Jan. 20, 1998. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates generally to the field of integrated circuits and, in particular, to integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits are used in a wide range of applications. Integrated circuits are conventionally formed on a wafer of semiconductor material. In order to function properly, the integrated circuit uses various electronic signals that are generated or provided from a source that is external to the integrated circuit, e.g., timing or “clock” signals, and power supply signals. 
     To connect to these signals, the integrated circuit includes a number of bond pads that are typically formed on the surface of the integrated circuit. The bond pads are coupled to nodes of the integrated circuit that need to receive the specified signals. Further, the bond pads are coupled to the external sources by leads. The leads are connected to the bond pads through bond wires. Conventionally, the bond wires have an arc-like shape that extends outwardly from the surface of the semiconductor substrate. The size, shape and length of these bond wires can hamper the operation of some integrated circuits due to the high resistance and high self inductance of the bond wires. 
     Mixed mode circuits are one type of circuit that can benefit from low impedance connections between bond pads and leads. A mixed mode circuit is a circuit that includes both an analog circuit and a digital circuit that are formed on the same semiconductor wafer. The mixed mode circuits can benefit from low impedance connections to a ground bus and a guard ring to suppress noise in the analog circuits that is caused by the high speed switching of the digital circuits. Such mixed mode circuits are now being used in microprocessors, memory devices, and other integrated circuits. 
     High inductance or high impedance connections between bond pads and leads can also introduce noise into the power distribution system of an integrated circuit. For example, high speed synchronous digital circuits require large switching currents. The large switching currents can introduce noise into the power distribution system of the digital circuit when the inductance or impedance of the connections to the power supply and ground busses is too high. 
     Similarly, circuits that include output drivers with large transient currents also can benefit from low resistance and low inductance connections to various power supply, ground, clock and guard ring busses. 
     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for low impedance, low inductance contacts or connections to power supply, ground, clock, or guard ring buses in integrated circuits. 
     SUMMARY OF THE INVENTION 
     The above mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Integrated circuits are described which use high aspect ratio vias through a substrate that are filled with a conductive material using a substitution technique so as to create low impedance, low inductance connections between various busses and selected leads. Advantageously, such high aspect ratio vias can be used to reduce problems such as ground bounce, substrate bounce, power supply noise, simultaneous switching noise, and cross talk between analog and digital circuits in mixed mode circuit by allowing the signals to be distributed on the back side of the substrate, away from the components of the integrated circuit. 
     In particular, an illustrative embodiment of the present invention includes an integrated circuit and a method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit. 
     In another embodiment, a method for forming an integrated circuit is provided. The method includes forming a functional circuit in a first surface of a semiconductor wafer. At least one high aspect ratio hole is formed through the semiconductor wafer from the first surface to a second, opposite surface. The at least one high aspect ratio hole is filled with polycrystalline semiconductor material and a layer of conductive material is deposited on the first and second surfaces of the semiconductor wafer. The semiconductor wafer is annealed such that the conductive material replaces the polycrystalline semiconductor material to form low resistance and low inductance conductors in the at least one high aspect ratio hole. At least one contact pad is formed on the second surface of the semiconductor wafer so as to provide a contact for the conductors in the at least one high aspect ratio hole. 
     In another embodiment, an integrated circuit is provided. The integrated circuit includes a semiconductor wafer. A functional circuit is formed in one surface of the semiconductor wafer. A number of high aspect ratio vias are formed through the thickness of the semiconductor wafer. A first end of each high aspect ratio via is coupled to a metallization layer on the first surface of the wafer. A second end of the high aspect ratio via is coupled to a bond pad on a second, opposite side of the semiconductor wafer. The integrated circuit also includes a chip carrier. The chip carrier has leads disposed on a surface of the chip carrier that are coupled to selected of the bond pads on the second surface of the semiconductor wafer when the semiconductor wafer is disposed on the chip carrier. 
     In another embodiment, a method for forming an integrated circuit is provided. The method includes forming a functional circuit in a first surface of a semiconductor wafer. A number of etch pits are formed in the first surface of the semiconductor wafer at selected locations in the functional circuit. An anodic etch of the semiconductor wafer is performed such that high aspect ratio holes are formed through the semiconductor wafer from the first surface to a second, opposite surface at the location of the etch pits. An insulating layer is formed on an inner surface of each high aspect ratio hole. The high aspect ratio holes are filled with polysilicon. A layer of aluminum is sputter deposited on the first and second surfaces of the semiconductor wafer and the semiconductor wafer is annealed at a temperature of approximately 500 degrees Celsius. The aluminum replaces the polysilicon to form conductors in the high aspect ratio holes. A number of contact pads are formed on the second surface of the semiconductor wafer so as to provide contacts for the conductors in the high aspect ratio holes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an elevational view of an embodiment of a semiconductor wafer having high aspect ratio vias and disposed on a chip carrier according to the teachings of the present invention. 
     FIGS. 2,  3 ,  4 ,  5 ,  6 ,  7  and  8  are elevational views of a semiconductor wafer at various points of an illustrative embodiment of a method for forming an integrated circuit with high aspect ratio vias according to the teachings of the present invention. 
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific illustrative embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense. 
     In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. 
     The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. 
     FIG. 1 is an elevational view of an embodiment of the present invention. The embodiment includes semiconductor wafer  100 . Semiconductor wafer  100  includes high aspect ratio vias  102  that provide low resistance, low inductance connections to leads  104  in chip carrier  106 . High aspect ratio vias  102  have an aspect ratio in the range of approximately 100 to 200. Conventionally, a semiconductor wafer used to form an integrated circuit has a thickness in the range of approximately 500 to 1000 microns. Thus, the high aspect ratio vias can be fabricated with a width that is in the range from approximately 2.5 microns up to as much as approximately 10 microns. 
     Leads  104  may be coupled to provide, for example, a ground bus, a guard bus, a power supply bus, clock signals, or other appropriate signals to functional circuit  108  in semiconductor wafer  100 . High aspect ratio vias  102  advantageously reduce the effect of problems such as ground bounce, substrate bounce, switching noise and power supply noise by providing low impedance and low inductance connections as compared with the much longer, arcing conventional bond wires. High aspect ratio vias  102  are also coupled to functional circuit  108  through metallization layer  110 . 
     High aspect ratio vias  102  allow a wide range of functional circuits to be fabricated on wafer  100 . For example, high aspect ratio vias  102  improve the operation of mixed mode circuits. Mixed-mode circuits include analog and digital circuitry that are formed on the same wafer or substrate. Using conventional design techniques, the switching noise caused by the digital circuits can interfere with the operation of the analog circuits. By incorporating high aspect ratio vias  102 , the effect of the switching noise from the digital portion of the functional circuit on the power distribution systems can be reduced. Further, high aspect ratio vias  102  also satisfy the need for low resistance, low inductance connections to power supply, ground, clock, and guard ring busses in other circuits. 
     High aspect ratio vias  102  can be added to circuits using a conventional layout for the circuit without adversely affecting the surface area requirements of the circuit. Conventional circuits typically include pads formed on the top surface of the semiconductor wafer that are used to connect to, for example, ground and power supply busses through bond wires. The bond wires of conventional circuits can be replaced by high aspect ratio vias  102  to achieve the advantages described above. 
     FIGS. 2,  3 ,  4 ,  5 ,  6 ,  7  and  8  are elevational views of semiconductor wafer  200  at various points of an illustrative embodiment of a method for forming an integrated circuit with high aspect ratio vias according to the teachings of the present invention. Functional circuit  202  is formed in an active region of semiconductor wafer  200 . In one embodiment, semiconductor wafer  200  comprises a monocrystalline silicon wafer. For purposes of clarity, the Figures only show the formation of two high aspect ratio vias through semiconductor wafer  200 . However, it is understood that with a particular functional circuit any appropriate number of vias can be formed to couple to a selected lead. For example, the number of vias needed for a conventional dynamic random access memory (DRAM) may be on the order of 100. Essentially, the vias are formed in the same space on the surface of semiconductor wafer  200  that is conventionally used to form bond pads to be connected to the same leads. The vias replace the conventional bond wires which couple the bond pads to the selected leads of a lead frame in the packaging of the semiconductor wafer. 
     As shown in FIG. 2, photo resist layer  204  is formed on surface  206  of semiconductor substrate  200 . Photo resist layer  204  is patterned to provide openings  208  at points on surface  206  where high aspect ratio holes are to be formed through semiconductor wafer  200 . 
     As shown in FIG. 3, etch pits  210  are formed by conventional alkaline etching through openings  208  in photo resist layer  204 . Photo resist layer  204  is then removed. 
     FIG. 4 is a schematic diagram that illustrates an embodiment of a layout of equipment used to carry out an anodic etch that is used to form high aspect ratio holes  250  of FIG.  5 . Typically, holes  250  have an aspect ratio in the range of 100 to 200. Bottom surface  262  of semiconductor wafer  200  is coupled to voltage source  234  by positive electrode  230 . Further, negative electrode  232  is coupled to voltage source  234  and is placed in a bath of 6% aqueous solution of hydrofluoric acid (HF) on surface  206  of semiconductor wafer  200 . 
     In this example, illumination equipment  236  is also included because semiconductor wafer  200  is n-type semiconductor material. When p-type semiconductor material is used, the illumination equipment is not required. Illumination equipment  236  assures that there is a sufficient concentration of holes in semiconductor wafer  200  as required by the anodic etching process. Illumination equipment  236  includes lamp  238 , IR filter  240 , and lens  242 . Illumination equipment  236  focuses light on surface  262  of semiconductor wafer  200 . 
     In operation, the anodic etch etches high aspect ratio holes through semiconductor wafer  200  at the location of etch pits  210 . Voltage source  234  is turned on and provides a voltage across positive and negative electrodes  230  and  232 . Etching current flows from positive electrode  230  to surface  206 . This current forms the high aspect ratio holes through semiconductor wafer  200 . Further, illumination equipment illuminates surface  262  of semiconductor wafer  200  so as to assure a sufficient concentration of holes for the anodic etching process. The size and shape of the high aspect ratio holes through semiconductor wafer  200  depends on, for example, the anodization parameters such as HF concentration, current density, and light illumination. An anodic etching process is described in V. Lehmann,  The Physics of Macropore Formation in Low Doped n - Type Silicon , J. Electrochem. Soc., Vol. 140, No. 10, pp. 2836-2843, October 1993, which is incorporated herein by reference. 
     FIG. 5 illustrates that electrical insulation can be formed on inner surface  252  of holes  250 . In this case, simple oxidation on the order of one micron or less is used to form insulator layer  254  on inner surface  252  or holes  250  to provide the electrical insulation. 
     FIGS. 6 and 7 illustrate a process of aluminum/polysilicon substitution that is used to fill holes  250  with aluminum. Such a process is described in H. Horie et al., Novel High Aspect Ratio Aluminum Plug for Logic/DRAM LSIs Using Polysilicon-Aluminum Substitute, Dig. IEEE Int. Electron Device Meeting, San Francisco, pp. 946-948, 1996, which is incorporated herein by reference. First, hole  250  is filled with a layer of polysilicon  256  by a process of chemical vapor deposition (CVD). It is noted that, conventionally, such a deep trench cannot be filled directly with aluminum using a direct chemical vapor deposition technique. However, conventionally, polysilicon has been deposited in holes with such high aspect ratios, e.g., deep trenches for trench capacitors. Once the holes are filled with polysilicon, excess polysilicon on surface  206  is removed by, for example, chemical/mechanical polishing. Aluminum layers  258  and  260  are deposited on surfaces  206  and  262  using, for example, a sputtering technique used to coat optical disks. Layers  258  and  260  have a thickness on the order of a few microns. The structure shown in FIG. 6 is then annealed at 500 degrees Celsius in Nitrogen ambient. This allows the aluminum material of layers  258  and  260  to be substituted for the polysilicon in holes  250 . The displaced polysilicon and any residual aluminum from layers  258  and  260  are removed by, for example, chemical/mechanical polishing. By depositing thin layers  259  and  261 , e.g., 0.1 μm, of titanium on top of layers  258  and  260 , respectively, the above mentioned anneal can be reduced from 500°Celsius to 450°Celsius. The structure is now as shown in FIG. 7 with high aspect ratio vias  264  extending through semiconductor wafer  200 . 
     As shown in FIG. 8, in one embodiment, pads  266  are formed, using conventional techniques on both first and second surfaces  206  and  262 , respectively, of semiconductor wafer  200 . On first surface  206 , the pads are used to connect a via to metallization layer  268 . On second surface  262 , the bond pads are used to connect a via to a lead  270 . Thus, a voltage on lead  270  can be passed through via  264  to functional circuit  202  without problems such as ground bounce, substrate bounce, and power supply noise, and simultaneous switching noise that can be introduced using conventional bond wires. Alternatively, pads  266  can be omitted and metallization layer  268  can be brought into contact with an end of a via. 
     CONCLUSION 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. For example, the high aspect ratio vias can be applied in a wide variety of circuits including but not limited to dynamic random access memory devices, dynamic logic circuits, and other multi-mode circuits. Further, other techniques can be used to form and fill the high aspect ratio holes to form the vias.