Patent Publication Number: US-4549927-A

Title: Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices

Description:
REFERENCE TO A COPENDING APPLICATION 
     The present application is related to patent application Ser. No. 626,278 filed concurrently by G. T. Goth, T. A. Hansen and R. T. Villetto for &#34;Metal silicide channel stoppers for integrated circuits and method for making the same&#34;. 
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a method for producing semiconductor devices and more particularly to a method for selectively exposing the sidewalls of a trench and its use in the formation of a metal silicide substrate contact for high density dielectric filled, deep trench isolated semiconductor devices. 
     2. Brief Description of the Prior Art 
     A reverse bias is commonly applied to the substrate in a semiconductor integrated chip for isolation purposes. In this case, the potential of the substrate is maintained at an appropriate value, so that the P-N junction of the isolation region and the substrate becomes reverse biased. 
     Conventional methods for forming a substrate contact for a semiconductor device are well known, such as a method for forming an electrode at the backside of the substrate to which is applied an external bias. With the development of large scale integration, thick and low doped substrates are widely used. Silicon wafers have lightly doped substrates in order to significantly reduce collector-substrate capacitances, which, in turn, increase the operating frequencies of the devices. Unfortunately, when the impurity concentration of the substrate is low, the electrical path between the electrode and the substrate becomes highly resistive, resulting in active devices, such as PNP lateral transistors having poor characteristics. This problem has been eliminated by contacting the substrate, through the N type epitaxial layer, with a highly doped P region. An example of this technique, in combination with standard recessed oxide isolation, may be found in European Patent application bearing the publication number 29552 assigned to VLSI Technology Research Association. 
     More recent trends in micro-electronics capitalize on a particular type of dielectric isolation where patterns of dielectrically filled trenches, extending from the surface of the integrated circuit to the interior thereof are used to isolate the devices (e.g. one bipolar transistor from another bipolar transistor) or portions (e.g. the base region from the collector region in a bipolar transistor) of the devices. 
     A method of forming a substrate contact for a trench structure is taught in an article of the IBM Technical Disclosure Bulletin, vol. 25 No. 12, May 1983, pages 6611 through 6614, authored by S. A. Abbas et al. This article describes the formation of a polysilicon buried conductor for reach through to the P substrate for ohmic electrical contact thereto. Once the trenches and channel stoppers have been formed, and trenches protected with an insulating layer, the bottom of the trench, where a contact is needed, is opened to expose the channel stopper. A thin polysilicon layer is CVD deposited, covering the sidewalls in totality and providing a contact with the substrate. It is obvious that with this technique, the P +  substrate contact reach through is highly resistive, not suitable for advanced bipolar devices. Also, a parasitic polysilicon-oxide-silicon capacitor is created which will degrade the circuit performance. 
     A variant is described in U.S. Pat. No. 4,256,514 assigned to the assignee of the present invention. According to this patent, a doped, polysilicon stud is used to provide the electrical contact with the substrate. However, although doped polysilicon still remains a relatively resistive material, and this solution is not completely satisfactory, because it implies the use of wide trenches, completely filled with polysilicon to reduce the resistance of the stud, which in turn results in lower integration density. 
     In addition, some other problems may result from this solution, due to, firstly different thermal coefficients between polysilicon and silicon, which may lead to undesired cracks in the filled trenches and, secondly, the resulting structure has very poor planarity. Planarity is a must when multilevel metallurgy (e.g. 4) is needed to assure the fan-in, and the fan-out functions of highly integrated circuits. 
     An other alternate solution is described in &#34;Plasma oxide filled deep dielectric isolation&#34;, J. S. Basi et al, IBM Technical Disclosure Bulletin, vol. 25 No. 8, Jan. 1983 pages 4405 and 4406. This article describes a method for forming a buried conductor for reach-through to the P -  silicon substrate of a chip from the surface of an epitaxial layer. The substrate contact is made by shorting the subcollector to the P channel stopper, at the bottom of the trenches and then to the top metallurgy via the collector reach through diffusion. The role of the metal is therefore to short the N -  epitaxy-P substrate/P +  channel stopper junction. 
     In this reference (and in the aforementioned U.S. Pat. No. 4,256,514 as well), a part of the electrical path, between the contact and the substrate is made of highly doped silicon material. Therefore, this solution cannot also be considered as fully satisfactory. 
     It is very important to remark that according to the teachings of this article, an isotropic etch is performed to expose all the sidewalls of a trench. Therefore, all devices adjacent to that trench, will have their N -  epitaxy-P -  substrate junction shorted by the Pt-Si contact. In others words, all these devices will be only devoted to provide substrate contact and therefore will be lost for logical implementation. This results in a non negligible waste of the silicon surface. 
     OBJECTS OF THE INVENTION 
     It is, therefore, a primary object of the invention to provide a method of selectively exposing the sidewalls of the trenches, to allow selective processing (etching, metal deposition . . . ) of the sidewalls which in turn will result in a significant saving of silicon room and therefore will allow a denser design than those obtained in the prior art. 
     It is another object of the invention to provide a method of selectively exposing the sidewalls of trenches and its use to the forming of a substrate contact for polyimide filled deep trench isolated devices compatible with very narrow trenches therefore considerably increasing integration density. 
     It is another object of the invention to provide a method of forming a substrate contact for high density polyimide filled deep trench isolated devices, comprised of a metal lining having very low resistance characteristics. 
     It is still another object of the invention to provide a method of forming a substrate contact for high density polyimide filled deep trench isolated devices which significantly improves the planarity of the structure. 
     SUMMARY OF THE PRESENT INVENTION 
     In accordance with the most general concept of the present invention, it is proposed thereafter, a broad method for selectively exposing the sidewalls of a trench. In others words, as a result, one sidewall will be exposed for further processing while the other will remain passivated. 
     In accordance with a more specific aspect of the present invention, said method will be described thereafter in connection with the forming of a platinum silicide lining by sputter deposition of platinum, on only a part of the sidewall and on the bottom of an isolation trench, for making contact from the surface of the epitaxial layer to the buried substrate. 
     Deep trenches according to the desired pattern are opened through the N epitaxial layer and N +  subcollector region into the P -  substrate of a silicon structure. Where a substrate contact is to be formed, the trenches delineate a central stud or mesa of silicon material. It is generally highly desirable that channel stop regions be formed, e.g. by ion implantation of boron atoms, at the bottom of trenches. SiO 2  and Si 3  N 4  layers are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose the sidewalls, the trenches which correspond to the stud, the bottom of the trenches adjacent thereto, and the top surface of the stud. The composite SiO 2  /Si 3  N 4  layer is etched to leave exposed said sidewalls of the stud, the bottom of the trenches adjacent thereto, and the top surface of the stud. Platinum is deposited preferably via sputter deposition, conformally coating all regions of the wafer. After sintering, the platinum in excess is removed using wet chemical etch (aqua regia). Platinum silicide is left in all opened contacts (bottom of the trenches and top surface of the stud) and on the trench sidewalls where it defines a metal silicide lining or cap, covering at least partly the stud. This lining connects the top surface of the stud with the channel stop implanted regions and thence forms the desired substrate contact. According to standard techniques, polyimide is then applied and appropriately etched to fill the trenches. It is an important point of the invention that the isolation trench provides two functions: first, the classic isolation of the device pocket containing the device (e.g. a NPN transistor) and second, through a continuous low resistive thin metal lining, an access to the buried substrate from the surface. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings forming a material part of the disclosure: 
     FIGS. 1-9 illustrate cross sectional view of an integrated structure undergoing fabrication according to the method of the present invention. 
    
    
     DISCLOSURE OF THE INVENTION 
     The present invention will be explained with reference to the attached figures. 
     In the following, the present invention which basically consists of a method of selectively exposing the sidewalls of a trench will be described in detail with reference to a method of forming a metal silicide substrate contact for high density dielectric filled deep trench isolated bipolar semiconductor devices. However, it should be understood that various other embodiments or uses may be set forth. Lastly, it is to be understood that while various dopant, coating and/or masking layers, processing conditions and the like are disclosed herein, the present invention is not limited thereto. 
     The usual bipolar semiconductor process is followed through the formation of trenches and passivation thereof with a composite Si 3  N 4  /SiO 2  layer. 
     With reference to FIG. 1, the initial structure 10 is comprised of a P -  silicon substrate 11, having a blanket N +  subcollector 12 and N -  epitaxial layer 13 thereon. 
     Deep narrow trenches 14 and 15 have been formed by etching through the N -  epitaxial layer 13 and the N +   subcollector 12, into the P -  substrate 11. Many well known etching techniques may be employed for the trench formation, such as illustrated in U.S. Pat. No. 4,381,953 to Ho et al or the improved technique subject to pending patent application Ser. No. 566,593 filed on Dec. 29, 1983 &#34;Trench etch process for dielectric isolation&#34;, to Goth et al and assigned to the same assignee as the present invention, both are incorporated herein by reference. Trenches are about 6 microns deep and 2 microns wide. The lay out design of the trenches is such that it delineates a square shaped central stud 16 or mesa between trenches 14 and 15, (the other trenches in the orthogonal direction are not represented). 
     Following trench formation, silicon dioxide is regrown by thermal oxidation, to provide a SiO 2  layer 17 of a thickness in the range of 50 to 300 nm. 
     Then, a standard ion implantation is conducted and boron is introduced at the bottom of the trenches to create channel stoppers 18. An additional layer 19 of Si 3  N 4  is CVD deposited of the order of 20 to 150 nm thick onto the whole structure. Of course, active devices such as bipolar transistors and/or passive devices have been previously formed in the different isolated epitaxial pockets such as 13a and 13b, but have not been represented for sake of clarity. 
     However, no devices have been formed in the epitaxial pocket 13c corresponding to the central stud (16). 
     As will be further apparent to the man skilled in the art, many more deep and narrow trenches forming an isolation pattern have been formed simultaneously with trenches 14 and 15 at the surface of the structure for isolation purposes. It is clear that the structure as shown in FIG. 1 results only from conventional manufacturing techniques. 
     Now, with reference to FIG. 2, an organic underlay material such as polyimide (2.0-4.0 μm thick) is first applied onto the Si 3  N 4  layer 19 by spin coating to form layer 20. An inorganic barrier layer 21, for example SiO x , with a thickness in the 100 to 300 nm range is subsequently deposited in a CVD plasma. Polyimide is preferred over photoresist because it fills trenches without voids, is optically transparent, therefore allowing precise mask alignment, and lastly is thermally stable during deposition of the barrier layer. This step is followed by the application of a conventional photoresist such AZ 1350J (a trade name of Shipley Company), by spin coating. The photoresist layer 22, is exposed according to a desired pattern to ultraviolet light through a mask (not represented) and subsequently developed, in a conventional manner. The imaging layer 22 of photoresist is typically 0.7-1.5 μm thick to optimize exposed image quality. It is important in our particular embodiment that the opening 23 in the imaging photoresist layer 22 be wider than the square shaped stud as apparent from FIG. 2. This will assure subsequently that the desired portions of the stud sidewalls, the bottom of the trenches adjacent thereto and the top surface of the stud be exposed. 
     The steps described with reference to FIGS. 3 to 5 following, are typically performed in-situ in a parallel plate reactive ion etch tool. 
     Etching of the exposed area of the inorganic barrier layer 21 is accomplished using CF 4 . Over-etch of 50-100% of the barrier layer is used to assure complete removal in the exposed regions. 
     
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Typical etch parameters are:                                              
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Power density    0.24   watts/cm.sup.2                                    
Flow (CF.sub.4)  30     Scc/min. (S stands for                            
                        Standard)                                         
Pressure         40     μm                                             
Etch rate SiO.sub.x                                                       
                 45     nm/min.                                           
Etch rate Polymide                                                        
                 32.5   nm/min.                                           
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     The resulting structure is shown in FIG. 3. The removed portion of the inorganic barrier layer correspond to opening 23 of the imaging photoresist layer 22. 
     The reactive ion etch of the organic underlay 20 is accomplished in an O 2  ambient in preferably a two step process for reasons explained thereafter. First the under lay material is etched to the bottom of the trench under complete anisotropic conditions as follows: 
     
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Power density       0.17   watts/cm.sup.2                                 
Pressure            3      μm                                          
Flow O.sub.2        100    Scc/min.                                       
Etch rate SiO.sub.x .7     nm/min.                                        
Etch rate Polymide  75     nm/min.                                        
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     Selectivity of ≈100:1 is achieved which permits full removal of 8-10 μm of polyimide with minor erosion (˜100 nm) of the SiO x  barrier layer 21. The second step of the process aims to perform a sidewall clean, to remove retained under lay material where trench sidewalls have negative slopes. Total layer removal is 100-300 nm thick. Etching conditions read as follows: 
     
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Power density       0.23   watts/cm.sup.2                                 
Pressure            50     μm                                          
Flow O.sub.2        30     Scc/min                                        
Etch rate Polymide  200    nm/min.                                        
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     The under-cut of the barrier layer 21 which defines now opening 23, is the result of the sidewall clean step. 
     The remaining portions of the resist layer 22 are eliminated, when the exposed organic underlay layer is RIE etched in the O 2  plasma, leaving unprotected only the central stud 16 and a significant portion of the bottom of the trenches, which is contiguous to the sidewalls of said central stud. 
     As previously mentioned, etching of the exposed portions of the Si 3  N 4  layer 19 is performed in-situ following the barrier and underlay etch steps. The etch process is &#34;semi isotropic&#34; when etched in a parallel plate reactive ion etch tool as follows: 
     
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Power density        0.23   watts/cm.sup.2                                
Pressure             200    μm                                         
Flow (CF.sub.4 + 10% O.sub.2)                                             
                     150    Scc/min.                                      
Etch rate Si.sub.3 N.sub.4                                                
                     70     nm/min.                                       
Etch rate SiO.sub.2  40     nm/min.                                       
Etch rate Polymide   45     nm/min.                                       
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     This process step is particularly important. Fully isotropic Si 3  N 4  etch processes are not workable in this structure because mechanical stresses in the organic underlay result in separation of the underlay from the Si 3  N 4  trench liner. Isotropic processes result in etch extensions beyond the defined image in the underlay. The underlying thermal SiO 2  layer serves as an etch stop to prevent attack of the silicon. The resulting structure is shown in FIG. 5. 
     Now turning to FIG. 6, the barrier layer 21 of SiO x  is stripped in a solution of 10:1 H 2  O:HF which removes SiO X  ˜5x faster than than thermally grown SiO 2  constituting layer 17. The underlay 20 is then stripped using conventional O 2  ash processes in a barrel type plasma etcher. The exposed portions of the thermal SiO 2  layer 17 are finally etched using a buffer HF solution while the remaining portions of the Si 3  N 4  over-coat layer 19 serve as a mask for this step. This completes the sidewall imaging process which selectively exposes the sidewalls and bottoms of trenches 14 and 15 encompassing the central stud. As a result, only the central stud sidewalls, the portions of the bottom of the trenches which are adjacent to it and the top surface of the stud, are now exposed and ready for further processing. 
     A thin layer 24 of an appropriate contact metal is blanket deposited on the whole structure by sputter deposition. A silicide forming metal selected in the group comprised of platinum, palladium and the like, is selected. The preferred metal with a thickness in the range of 30-100 nm is platinum. 
     Sputter deposition is the preferred method because unlike others techniques such vacuum evaporation, the metal is deposited on both horizontal and vertical surfaces of the structure. In others words, metal will coat conformally all the exposed regions of the structure. FIG. 7 illustrates the structure at this stage. 
     The structure is then heated at about 550° C. to produce a platinum silicide layer 25 by sintering wherever the platinum layer 24 contacts silicon. Unreacted platinum is removed by wet etching (in aqua regia). FIG. 8 shows the result of such a process wherein a platinum silicide contact is formed with the channel stoppers 18 at the bottom of the trenches, and with all the horizontal and vertical surfaces of the stud, forming a metallic lining or cap 25 which completely covers the silicon stud 16 and providing a buried ohmic contact with the P -  substrate 11 through channel stoppers 18. 
     Polymide material 26 is spin applied to fill the trenches. It is baked out at 400° C. and reactive ion etched in an O 2  plasma as seen in FIG. 9. The horizontal portion of the Pt-Si layer which remains exposed (see numeral reference 25a) will be used as the substrate contact for the subsequent metallization steps. 
     Electrical contacts are then made to the elements such as NPN transistors, diodes, resistors . . . in addition to that substrate contact by conventional deposition, lithography and etching techniques. 
     While there has been shown and described what is considered at present to be the preferred embodiment of the present invention, it will be appreciated by those skilled in the art that modifications of such embodiment may be made. It is therefore desired that the invention not be limited to this embodiment, and it is intended to cover in the appended claims all such modifications as fall within the true spirit and scope of the invention.