Patent Publication Number: US-2022231082-A1

Title: Method of fabricating led module

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application based on pending U.S. application Ser. No. 16/901,451, filed on Jun. 15, 2020, the entire contents of which is hereby incorporated by reference. Korean Patent Application No. 10-2019-0135447, filed on Oct. 29, 2019, in the Korean Intellectual Property Office, and entitled: “LED Module and Method of Fabricating the Same,” is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     Embodiments relate to a light emitting diode (LED) module and a method of fabricating the LED module. 
     2. Description of the Related Art 
     Semiconductor light emitting diodes (LEDs) are not only used as light sources for lighting devices but also as light sources for various electronic products. In detail, semiconductor LEDs are widely used as light sources for various display devices such as TVs, mobile phones, PCs, notebook PCs, PDA and the like. 
     Display devices may be composed of a display panel and a backlight composed of a liquid crystal display (LCD), but in recent years, LED devices have been used instead and have been developed in a form in which a backlight is not separately required. Such a display device may not only be compact, but also can implement a high brightness display device having excellent light efficiency compared to a related art LCD. Such a display device is composed of a plurality of display modules constituting each pixel. 
     SUMMARY 
     Embodiments are directed to a light emitting diode (LED) module, including: a substrate having a plurality of light emission windows; a plurality of LED cells disposed on the substrate to correspond to the plurality of light emission windows, respectively, the plurality of LED cells each including a lower light emitting structure and an upper light emitting structure, the lower light emitting structure having an upper surface divided into a first region and a second region and having at least a first conductivity-type semiconductor layer, the upper light emitting structure being disposed on the first region of the lower light emitting structure and having at least a second conductivity-type semiconductor layer, the plurality of LED cells including an active layer between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer; a protective insulating film disposed on a side surface of the lower light emitting structure and on the second region; a light blocking film disposed on the protective insulating film, between the plurality of LED cells; a gap-fill insulating film disposed on the protective insulating film to fill between the plurality of LED cells and in contact with a side surface of the upper light emitting structure; a first electrode connected to the first conductivity-type semiconductor layer of the lower light emitting structure; and a second electrode connected to the second conductivity-type semiconductor layer of the upper light emitting structure. 
     Embodiments are also directed to a light emitting diode (LED) module, including a first substrate structure including a substrate having a plurality of light emission windows, a plurality of LED cells disposed on the substrate to correspond to the plurality of light emission windows, respectively, a gap-fill insulating film filled between the plurality of LED cells and disposed on the plurality of LED cells, a first planarization insulating layer disposed on the gap-fill insulating film and having a first surface that is substantially flat, and connection electrodes connected to the plurality of LED cells through the first planarization insulating layer, respectively, and exposed to the first surface of the first planarization insulating layer; and a second substrate structure disposed on the first substrate structure, the second substrate structure including a second planarization insulating layer having a second surface that is substantially flat, the second surface being bonded to the first surface, the second substrate structure including a driving circuit having a plurality of TFT cells and metal wires connected to the driving circuit, exposed to the second surface of the second planarization insulating layer, and bonded to the connection electrodes, respectively. The plurality of LED cells may include a lower light emitting structure and an upper light emitting structure, the lower light emitting structure having an upper surface divided into a first region and a second region and having a first conductivity-type semiconductor layer, the upper light emitting structure being disposed on the first region of the lower light emitting structure and having an active layer and a second conductivity-type semiconductor layer. The first substrate structure may further include a protective insulating film disposed on a side surface of the lower light emitting structure and on the second region, and a light blocking film disposed on the protective insulating film, between the plurality of LED cells. The gap-fill insulating film may be disposed on the protective insulating film and surrounds the upper light emitting structure while being in contact with a side surface of the upper light emitting structure. 
     Embodiments are also directed to a light emitting diode (LED) module, including: a substrate having a plurality of light emission windows; a plurality of LED cells disposed on the substrate to correspond to the plurality of light emission windows, respectively, the plurality of LED cells each including a first conductivity-type semiconductor layer having an upper surface divided into a first region and a second region, and an active layer and a second conductivity-type semiconductor layer sequentially stacked on the first region; a protective insulating film disposed on a side surface of the first conductivity-type semiconductor layer and on the second region; a light blocking film disposed on the protective insulating film, between the plurality of LED cells; and a gap-fill insulating film disposed on the protective insulating film, the gap-fill insulating film filling between the plurality of LED cells and being in contact with side surfaces of the active layer and the second conductivity-type semiconductor layer. 
     Embodiments are also directed to a method of fabricating an LED module, including: forming a semiconductor structure having a first conductivity-type semiconductor layer on a substrate; dividing the semiconductor structure into a plurality of lower light emitting structures by forming an isolation region to which a surface of the substrate is exposed; forming a protective insulating film on upper and side surfaces of the plurality of lower light emitting structures and a surface of the substrate exposed to the isolation region; forming a light blocking film on the protective insulating film corresponding to the isolation region; forming a gap-fill insulating film on the protective insulating film to fill the isolation region; partially removing the gap-fill insulating film and the protective insulating film to expose a portion of an upper surface of each of the plurality of lower light emitting structures; forming an upper light emitting structure having an active layer and a second conductivity-type semiconductor layer in an exposed area of an upper surface of each of the plurality of lower light emitting structures; and forming a first electrode and a second electrode connected to the first conductivity-type semiconductor layer of the lower light emitting structure and the second conductivity-type semiconductor layer of the upper light emitting structure, respectively. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       Features will become apparent to those of skill in the art by describing in detail example embodiments with reference to the attached drawings in which: 
         FIG. 1  is a schematic perspective view of a display panel having an LED module according to an example embodiment; 
         FIG. 2  is an enlarged plan view of portion A of  FIG. 1 ; 
         FIG. 3  is a side cross-sectional view taken along line I-I′ of  FIG. 2 ; 
         FIG. 4  is a schematic of a driving circuit implemented in a display device according to an example embodiment; 
         FIGS. 5A to 12A  are plan views of stages in a method of fabricating an LED module according to an example embodiment; 
         FIGS. 5B to 12B  are cross-sectional views of stages in a method of fabricating an LED module according to an example embodiment; 
         FIGS. 13 to 15  are cross-sectional views of stages in a method of fabricating an LED module according to an example embodiment; 
         FIG. 16  is a schematic perspective view illustrating a bonding process of wafers (first and second substrate structures); 
         FIG. 17  is a cross-sectional view of an LED module for display according to an example embodiment; and 
         FIG. 18  is a schematic diagram illustrating a cross-sectional structure of a quantum dot (QD) as a wavelength conversion material usable in an LED module according to an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, example embodiments will be described with reference to the accompanying drawings. 
       FIG. 1  is a schematic perspective view of a display panel having an LED module according to an example embodiment,  FIG. 2  is an enlarged plan view of portion A of  FIG. 1 , and  FIG. 3  is a side cross-sectional view taken along line I-I′ of  FIG. 2 . 
     Referring to  FIGS. 1 and 2 , a display panel  10  (also be referred to as an “LED module for display”) according to an example embodiment may include a circuit board  200  (also, referred to as a “second substrate structure”) including a TFT cell, and an LED module  100  (also, referred to as a “first substrate structure”) disposed on the circuit board  200  and provided with a plurality of pixels PX arranged thereon. The display panel  10  may further include a frame  11  surrounding the circuit board  200  and the LED module  100 . 
     Each pixel PX may include first to fourth sub-pixels SP 1 , SP 2 , SP 3 , and SP 4 . The first to fourth sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  may include LED cells C 1 , C 2 , C 3 , and C 4  capable of emitting light having a specific wavelength, respectively. For example, the LED cells C 1 , C 2 , C 3 , and C 4  may include a light emitting structure LS that may emit blue light or ultraviolet light. 
     The first to fourth sub pixels SP 1 , SP 2 , SP 3 , and SP 4  may be configured such that at least a portion of the first to fourth sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  may emit light of different colors to display a color image. For example, the first to third sub-pixels SP 1 , SP 2 , and SP 3  may be configured to emit red light, green light, and blue light, respectively, and the fourth sub-pixel SP 4  may be configured to emit one of the three colors, for example, green light or white light. 
     In the present example embodiment, the pixel PX is illustrated in the form of four sub-pixels SP 1 , SP 2 , SP 3 , and SP 4 , but the pixel PX may include, for example, three sub-pixels that are configured to emit different colors, for example, red, green and blue light. The color of the light emitted from the first to fourth sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  may be determined by the LED cells C 1  to C 4  and/or wavelength conversion units  191 ,  192  and  193  (see  FIG. 3 ), which will be described in more detail with reference to  FIG. 3 . 
     As illustrated in  FIG. 1 , the pixel (PX) array in the present example embodiment is illustrated in the form of 15×15, but the array may be implemented as any appropriate number of columns and rows, for example, in the form of 1,024×768. The pixel array may have a different arrangement depending on a desired resolution. The LED module  100  illustrated in  FIG. 1  may be manufactured by preparing a block body of a pixel array of a relatively small unit (e.g., 5×5) and then transferring respective block bodies onto the circuit board  200  to arrange the block bodies. 
     The frame  11  may be disposed around the LED module  100  and serve as a guide defining an arrangement space of an array of pixels PX. The frame  11  may include one or more of, for example, a polymer, a ceramic, a semiconductor, or a metal. The frame  11  may include a black matrix, a white matrix, or other colored structure may be used depending on the use of the product. For example, the white matrix may include a reflective material or a light scattering material. 
     Although the display panel  10  illustrated in the present example embodiment is illustrated as having a flat structure having a quadrangular shape, the display panel  10  may have a structure having a different shape, for example, the display panel  10  may have a structure with a curved profile by forming the circuit board TFS using a flexible substrate. 
       FIG. 3  is a side cross-sectional view of the LED module illustrated in  FIG. 2  taken along line I-I′. 
     The cross-section illustrated in  FIG. 3  illustrates an LED structure constituting one pixel, and in detail, illustrates cross sections of the first to third LED cells C 1 , C 2 , and C 3  corresponding to the first to third sub pixels SP 1 , SP 2  and SP 3 , respectively. 
     In  FIG. 3 , the fourth LED cell C 4  is omitted, but the fourth LED cell C 4  may have a structure similar to that of the first to third LED cells C 1 , C 2 , and C 3 . The fourth LED cell C 4  may be configured to emit light of the same color as the light of another LED cell, and may be understood to have the same structure as the other LED cells. 
     Referring to  FIG. 3 , the display panel  10  may include the LED module  100  disposed on the circuit board  200 . The LED module  100  may be implemented as a first substrate structure having an LED array. The circuit board  200  may be implemented as a second substrate structure bonded to the first substrate structure. The first substrate structure and the second substrate structure may be integrally bonded to each other by a wafer bonding method such as fusion bonding or hybrid bonding at a wafer level (see  FIG. 16 ). 
     The LED module  100  may include a substrate  110  having a plurality of light emission windows W 1 , W 2 , and W 3 , and first to third LED cells C 1 , C 2 , and C 3  disposed on the substrate  110  to correspond to the plurality of light emission windows W 1 , W 2 , and W 3 , respectively. 
     The first to third LED cells C 1 , C 2 , and C 3  may include a light emitting structure LS configured to emit light of a specific wavelength. The light emitting structure LS may include a semiconductor stack obtained by the same growth process. The light emitting structure LS may be obtained by, for example, a divided growth process. 
     The light emitting structure LS may include a lower light emitting structure LS 1  having an upper surface divided into a first region and a second region, and an upper light emitting structure LS 2  disposed on the first region of the lower light emitting structure LS 1 . The lower light emitting structure LS 1  may include at least a first conductivity-type semiconductor layer  122 . The upper light emitting structure LS 2  may include at least a second conductivity-type semiconductor layer  127 . In the present example embodiment, the lower light emitting structure LS 1  further includes an undoped semiconductor layer  121  positioned between the first conductivity-type semiconductor layer  122  and the substrate  110 , and the upper light emitting structure LS 2  includes an active layer  125  and the second conductivity-type semiconductor layer  127 . In another example embodiment (see  FIG. 17 ), the upper light emitting structure LS 2  may further include a portion of the first conductivity-type semiconductor layer  122 , and in another example embodiment, the lower light emitting structure LS 1  may further include an active layer  125 . 
     In plan view, the second region may have a shape surrounding at least a portion of the first region. In the present example embodiment, the second region is illustrated as having a shape surrounding the entirety of the first region (see  FIG. 8A ). 
     The substrate  110  may be a growth substrate for growing the semiconductor layers  121 ,  122 ,  125 , and  127  for the light emitting structure LS. For example, the substrate  110  may include an insulating, conductive, or semiconductor substrate. In the present example embodiment, the substrate  110  may be a substrate capable of blocking light and a substrate to which processing for the light emission windows W 1 , W 2 , and W 3  may be easily applied. The substrate  110  may include a silicon substrate. 
     The undoped semiconductor layer  121  may include GaN, and the first conductivity-type semiconductor layer  122  may have a nitride semiconductor satisfying an n-type In x Al y Ga 1−x−y N (0≤x&lt;1, 0&lt;1, 0—&lt;x+y&lt;1), and in this case, the n-type impurity may include silicon (Si), germanium (Ge), selenium (Se), or tellurium (Te). The active layer  125  may have a multi-quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked. For example, the quantum well layer and the quantum barrier layer may be layers of In x Al y Ga 1−x−y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) having different compositions. The quantum well layer may be an In x Ga 1−x N (0&lt;x≤1) layer, and the quantum barrier layer may be a GaN or AlGaN layer. The active layer  125  may be configured to emit substantially the same light. For example, the active layer  125  may be configured to emit blue light (e.g., 440 nm to 460 nm) or ultraviolet light or near ultraviolet light (e.g., 380 nm to 440 nm). The second conductivity-type semiconductor layer  127  may include a nitride semiconductor layer satisfying p-type In x Al y Ga 1−x−y N (0≤x&lt;1, 0≤y&lt;1, 0≤x+y&lt;1), and in this case, the p-type impurity may include magnesium (Mg), zinc (Zn), or beryllium (Be). 
     As illustrated in  FIG. 3 , the substrate  110  may have a partition structure that provides a plurality of light emission windows W 1 , W 2 , and W 3 . As described above, the plurality of light emission windows W 1 , W 2 , and W 3  may be formed on the substrate  110  to correspond to the plurality of LED cells, respectively. 
     As illustrated in  FIG. 3 , a light adjusting unit may be disposed on at least a portion of the first to third light emission windows W 1 , W 2 , and W 3 . For example, first and second light adjusting units  191  and  192  may convert a portion of the light emitted from first and second LED cells C 1  and C 2  into light of different colors, respectively. For example, the first to third LED cells C 1 , C 2 , and C 3  may be configured to emit blue light, and the first and second wavelength conversion units  191   a  and  192   a  may be configured to convert red light and green light, respectively. The third light emission window W 3  may be filled with a protective transparent resin as the light adjusting unit  193  to emit blue light. 
     The first and second wavelength conversion units  191   b  and  192   b  may include first and second wavelength conversion materials P 1  and P 2 , respectively. The first and second wavelength conversion units  191   b  and  192   b  may be formed by, for example, dispensing a light-transmissive liquid resin mixed with a wavelength conversion material such as a phosphor or a quantum dot into the first and second light emission windows W 1  and W 2 , respectively. In another example embodiment, the first and second wavelength conversion units  191   b  and  192   b  may be provided in the form of a wavelength conversion film. 
     The first and second light adjusting units  191  and  192  may be disposed on the first and second wavelength conversion units  191   a  and  192   a , respectively, and may further include first and second light filter layers  191   a  and  192   a  that block unconverted blue light. The color purity of light emitted from the first and second light emission windows W 1  and W 2  may be increased by the first and second light filter layers  191   b  and  192   b.    
     A protective insulating film  131  may be disposed on a side surface of the lower light emitting structure LS 1 , and on the second region. The protective insulating film  131  may also extend to an area of the substrate  110  positioned between the lower light emitting structures LS 1  along the side surface of the lower light emitting structure LS 1 . The protective insulating film  131  may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. The protective insulating film  131  may be formed relatively conformally. 
     A light blocking film  135  may be disposed on an area of the protective insulating film  131  positioned between the plurality of LED cells C 1 , C 2 , and C 3 . The light blocking film  135  may partially extend to the area of the protective insulating film  131  disposed on the upper surface of the lower light emitting structure LS 1 . The light blocking film  135  may be employed to have a structure for preventing optical interference between the plurality of LED cells C 1 , C 2 , and C 3 . For example, the light blocking film  135  may include polysilicon. The light blocking film  135  may be formed of a light reflection layer. For example, the light blocking film  135  may include a reflective metal layer, a distributed Bragg reflection (DBR) layer, or an omni-directional reflection (ODR) layer. The reflective metal layer may include silver (Ag), nickel (Ni), or aluminum (Al). 
     The gap-fill insulating film  140  may be disposed on the protective insulating film  131  to fill gaps between the LED cells C 1 , C 2 , and C 3 . The gap-fill insulating film  140  may contact the side surface of the upper light emitting structure LS 2  and surround the upper light emitting structure LS 2 . The top surface of the gap-fill insulating film  140  may be the same as or higher than the top surface of the upper light emitting structure LS 2 . 
     The gap-fill insulating film  140  may be formed before the first and second electrodes  151  and  152  and the active layer  165  are formed. Thus, the gap-fill insulating film  140  may be formed at a relatively high temperature of 600° C. or higher, for example, 800° C. In addition, the space between the lower light emitting structures LS 1  may have a lower depth than the space between the entire light emitting structures LS. Thus, a relatively easy gap fill process may be performed. Therefore, generation of voids or seams in the gap-fill insulating film  140  may be suppressed, and mechanical reliability may be improved. 
     The gap-fill insulating film  140  may include, for example, a silicon oxide or a silicon oxide-based insulating material. For example, the gap-fill insulating film  140  may be formed of TetraEthyl Ortho Silicate (TEE), Undoped Silicate Glass (USG), or PhosphoSilicate Glass (PSG), Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), Fluoride Silicate Glass (FSG), Spin On Glass (SOG), Tonen SilaZene (TOSZ), or combinations thereof. 
     The LED module  100  may include the first electrode  151  disposed on the first conductivity-type semiconductor layer  122  of the lower light emitting structure LS 1 , and the second electrode  152  disposed on the second conductivity-type semiconductor layer  127  of the upper light emitting structure LS 2 . The first electrode  151  may be connected to the first conductivity-type semiconductor layer  122  by penetrating through at least a portion of the gap-fill insulating film  140  and the protective insulating film  131 . As such, the first electrode  151  may be formed after the gap-fill insulating film  140  is formed. 
     The first electrode  151  may include, for example, at least one of aluminum (Al), gold (Au), chromium (Cr), nickel (Ni), titanium (Ti), and tin (Sn). The second electrode  152  may be formed of, for example, a reflective metal. For example, the second electrode  142  may include a material such as Ag, Ni, Al, Cr, rhodium (Rh), palladium (Pd), iridium (Ir), ruthenium (Ru), Mg, zinc (Zn), platinum (Pt), Au, or the like. The second electrode  142  may have a single layer, or a structure of two or more layers. 
     The LED module  100  may include a planarization insulating layer  161  disposed on the gap-fill insulating film  140  and having a substantially flat surface. The planarization insulating layer  161  may be formed to cover the first and second electrodes  151  and  152 . The LED module  100  may include a reflective layer  175  disposed in the planarization insulating layer  161 . The planarization insulating layer  161  may include a first insulating layer  161   a  disposed on the gap-fill insulating film  140  and covering the first and second electrodes  151  and  152 , and a second insulating layer  161   b  disposed on the first insulating layer  161   a  and having a substantially flat surface. The reflective layer  175  may be disposed on the first insulating layer  161   a  and may be covered by the second insulating layer  161   b.    
     The LED module  100  may further include first and second connection electrodes  181  and  182  that are respectively connected to the first and second electrodes  151  and  152  through the planarization insulating layer  161 . 
     The first and second connection electrodes  181  and  182  may be exposed to the surface of the planarization insulating layer  161 . The first and second connection electrodes  181  and  182  may have pad portions  181 P and  182 P exposed on the surface of the planarization insulating layer  161 . Surfaces of the pad portions  181 P and  182 P may have substantially flat coplanar surfaces with the surfaces of the planarization insulating layer  161 . The reflective layer  175  disposed in the planarization insulating layer  161  may have an open area to be electrically insulated from the first and second connection electrodes  181  and  182  (see  FIGS. 11A and 11B ). The first and second connection electrodes  181  and  182  may include, for example, copper or a copper-containing alloy. The first and second connection electrodes  181  and  182  may be formed, for example, using a dual damascene process. 
     The circuit board  200  may include a wiring layer  280  bonded to the planarization insulating layer  161  of the LED module  100 , and a device layer  250  in which a driving circuit including a plurality of TFT cells  245  is implemented. 
     The device layer  250  may include a driving circuit including a semiconductor substrate  210  and a TFT cell  245  formed on the semiconductor substrate  210 , an interconnection portion  242  electrically connected to the TFT cell  245 , and an interlayer insulating film  241  disposed on the semiconductor substrate  210  to cover the driving circuit and the interconnection portion  242 . 
     The semiconductor substrate  210  may include, for example, a semiconductor such as Si, or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. 
     The wiring layer  280  may include a dielectric layer  281  disposed on the interlayer insulating film  241 , and a metal wire  285  disposed on the dielectric layer  281  and connected to the interconnection portion  242 . The metal wire  285  may be electrically connected to the driving circuit through the interconnection portion  242 . The dielectric layer  281  may have a substantially flat surface in contact with the surface of the planarization insulating layer  161 . The planarization insulating layer  161  of the LED module  100  may be referred to as a “first planarization layer”, and the dielectric layer  281  of the circuit board  200  may be referred to as a “second planarization layer”. 
     The metal wire  285  may have a bonding pad  185 P exposed on the surface of the dielectric layer  281 . The bonding pad  185 P may have a surface that is substantially coplanar with the surface of the dielectric layer  281 . The planar surface of the dielectric layer  281  may be bonded to the planar surface of the planarization insulating layer  161 , and the bonding pads  185 P may be bonded to the pad portions  181 P and  182 P of the first and second connection electrodes  181  and  182 , respectively. The bonding pads  185 P and the pad portions  181 P and  182 P of the first and second connection electrodes  181  and  182  may have substantially the same area at the same position. 
     The driving circuit including the plurality of TFT cells  245  implemented in the circuit board  200  may be a driving circuit controlling the driving of a pixel (or a sub pixel). The semiconductor substrate  210  may include a through electrode  263  such as a through-silicon via (TSV) connected to the driving circuit, and first and second wiring lines  261  and  262  connected to the through electrode. For example, drain regions of the TFT cells  245  may be connected to the first wiring line  261  through the through electrode  263 , and the first wiring line  261  may be connected to the data line. 
     Source regions of the plurality of TFT cells  245  may be connected to one side electrodes of the plurality of LED cells C 1 , C 2 , and C 3  through interconnection portions  242  and the metal wires  285 . Gate electrodes of the plurality of TFT cells  245  may be connected to the second wiring line  262  through the through electrode  263 , and the second wiring line  262  may be connected by a gate line. The circuit configuration and operations thereof will be described below with reference to  FIG. 4 . 
       FIG. 4  is a driving circuit diagram implemented in a display device according to an example embodiment. 
     Referring to  FIG. 4 , a circuit diagram of a display panel  10  in which n×n sub-pixels are arranged is illustrated. The first to fourth sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  may receive data signals through data lines D 1  to Dn, which are paths in a vertical direction (a row direction), respectively. The first to fourth sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  may receive a control signal (e.g., a gate signal) through gate lines G 1  to Gn that are horizontal paths (in a column direction). 
     The first to fourth sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  may be arranged in a rectangular arrangement or another form. A plurality of pixels PX including the first to fourth sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  respectively form an active area DA for display and serve as a display area for a user. An inactive area NA of the display panel  10  may be formed along one or more edges of the active area DA. The inactive area NA does not have the pixel PX along the outer circumference of the display panel  10  and may correspond to the frame  11  of the display panel  10 . 
     First and second driver circuits  12  and  13  may be employed to control the operation of the pixel PX, for example, the plurality of sub pixels SP 1 , SP 2 , SP 3 , and SP 4 . Some or all of the first and second driver circuits  12  and  13  may be implemented in a device layer  250  of the circuit board  200 . The first and second driver circuits  12  and  13  may be formed as integrated circuits, thin film transistor panel circuits, or other suitable circuits, and may be disposed in the inactive area NA of the display panel  10 . The first and second driver circuits  12  and  13  may include a microprocessor, a memory such as a storage, a processing circuit, and a communication circuit. During operation, the system control circuit may supply image information IS to be displayed on the display panel  10  to the first and second driver circuits  12 ,  13 . 
     To display an image on the pixel PX, the first driver circuit  12  may supply the image data to the data lines D 1  to Dn, and may send a clock signal and other control signals to the second driver circuit  13  (also referred to as a ‘gate driver circuit’). The second driver circuit  13  may be implemented using an integrated circuit and/or a thin film transistor circuit. Gate signals controlling the sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  arranged in the column direction may be transmitted through the gate lines G 1  to Gn of the display device. 
     The sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  may include TFT cells  245  (also referred to as a driving transistor) connected to the LED cells C 1 , C 2 , C 3 , and C 4  in series, respectively. The sub-pixels may be provided in a different circuit configuration of respective sub-pixels SP 1 , SP 2 , SP 3 , and SP 4 . Respective sub-pixel SP 1 , SP 2 , SP 3 , and SP 4  may be implemented in various circuits by further including other elements. For example, the respective sub-pixels SP 1 , SP 2 , SP 3 , and SP 4  may further include a capacitor used to store the loaded data between successive image frames, or one or more switching transistors to support data loading operations and other operations. 
       FIGS. 5A to 12A  are plan views of stages in a method of fabricating an LED module according to an example embodiment, and  FIGS. 5B to 12B  are cutaway cross-sectional views taken along line II-II′ of  FIGS. 5A to 12A . 
     Referring to  FIGS. 5A and 5B , in a method of fabricating an LED module according to an example embodiment, the undoped semiconductor layer  121  and a first conductivity-type semiconductor layer  122  may be sequentially grown on a growth substrate  110 . The undoped semiconductor layer  121  and the first conductivity-type semiconductor layer  122  may be divided into a plurality of lower light emitting structures LS 1  by forming an isolation region IS. 
     The growth substrate  110  may include, for example, an insulating, conductive, or semiconductor substrate, for example, a silicon substrate. The undoped semiconductor layer  121  and the first conductivity-type semiconductor layer  122  may include, for example, an undoped GaN layer and an n-type nitride layer, respectively. 
     The isolation region IS may be formed to expose the surface of the substrate  110 . In the process of forming the isolation region IS, a portion of the substrate  110  may also be etched. As illustrated in  FIG. 5A , the plurality of lower light emitting structures LS 1  may be disposed in a shape having a circular shape in a plan view. In other example embodiments the plurality of lower light emitting structures LS 1  may have various other shapes, such as a quadrangular or hexagonal shape. 
     Referring to  FIGS. 6A and 6B , a protective insulating film  131  may be formed on upper and side surfaces of the plurality of lower light emitting structures LS 1 , and then, a light blocking film  135  may be formed in the region of the protective insulating film  131  corresponding to the isolation region IS. 
     The protective insulating film  131  may extend to the surface area of the substrate  110  positioned between the lower light emitting structures LS 1  along the side surface of the lower light emitting structure LS 1 . The protective insulating film  131  may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. The protective insulating film  131  may be formed relatively conformally. 
     The light blocking film  135  may be employed to prevent optical interference between a plurality of LED cells. The light blocking film  135  may include, for example, polysilicon. The light blocking film  135  may be formed of a light reflection layer. For example, the light blocking film  135  may include a reflective metal layer, a DBR layer, or an ODR layer. The reflective metal layer may include Ag, Ni, or Al. 
     Referring to  FIGS. 7A and 7B , a gap-fill insulating film  140  may be formed on the protective insulating film  131  to fill the isolation region IS. The gap-fill insulating film  140  may be disposed to contact the side surface of the upper light emitting structure LS 2  and surround the upper light emitting structure LS 2 . The gap-fill insulating film  140  may include a silicon oxide or a silicon oxide-based insulating material, and may include, for example, TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or combinations thereof. 
     The gap-fill insulating film  140  may be formed before first and second electrodes  151  and  152  and an active layer  165  are formed. Thus, the gap-fill insulating film  140  may be formed at a relatively high temperature of 600° C. or higher, for example, 800° C. In addition, the space between the lower light emitting structures LS 1  may have a lower depth than that of the space between the entire light emitting structures LS. Thus, a relatively easy gap fill process may be performed. 
     Referring to  FIGS. 8A and 8B , an open area OP exposing a portion of the upper surface of each of the lower light emitting structures LS 1  may be formed by partially removing the gap-fill insulating film  140  and the protective insulating film  131 . 
     The upper region of the lower light emitting structure LS 1  exposed by the open area OP may be provided as a region in which an upper light emitting structure LS 2  of  FIGS. 9A and 9B  is to be formed in a subsequent process. In addition, the upper light emitting structure formed in a subsequent process may be defined by the open area OP. The position and area of the upper light emitting structure may be determined by the position and area of the open area OP. In addition, the side shape of the upper light emitting structure may be defined by the profile of the inner sidewall of the open area OP. For example, when the inner sidewall of the open area OP has a vertical or obtuse angle with respect to the upper surface of the lower light emitting structure LS 1 , the side surface of the upper light emitting structure may have the same inclination angle as the inner sidewall of the open area OP. 
     Referring to  FIGS. 9A and 9B , the upper light emitting structure LS 2  (having an active layer  125  and a second conductivity-type semiconductor layer  127 ) may be formed in an exposed area of the upper surface of the lower light emitting structure LS 1 . 
     The upper light emitting structure LS 2  may be formed by sequentially growing the active layer  125  and the second conductivity-type semiconductor layer  127  in the upper region of the lower light emitting structure LS 1  exposed by the open area OP. The upper light emitting structure LS 2  may be grown such that an upper surface thereof has a level equal to or lower than an upper surface of the gap-fill insulating film  140 . 
     As described above, the position, area, and sidewall shape of the upper light emitting structure LS 2  may be determined by the position, area, and sidewall shape of the open area OP. In the present example embodiment, although the upper light emitting structure LS 2  is illustrated as including the active layer  125  and the second conductivity-type semiconductor layer  127 , the upper light emitting structure LS 2  may also be formed by growing the active layer  125  and the second conductivity-type semiconductor layer  127  after further growing the first conductive semiconductor layer (see  FIG. 17 ). 
     Referring to  FIGS. 10A and 10B , the first electrode  151  and the second electrode  152 , respectively connected to the first conductivity-type semiconductor layer  122  and the second conductivity-type semiconductor layer  127 , may be formed. 
     The second electrode  152  may be formed on the second conductivity-type semiconductor layer  127  exposed by the open area OP, while the first electrode  151  may be formed by removing portions of the gap-fill insulating film  140  and the protective insulating film  131  to expose a portion of the first conductivity-type semiconductor layer  122 . The first electrode  151  is illustrated as a ring shape surrounding the upper light emitting structure LS 2 . In another implementation, the first electrode  151  may be formed to be limited to a portion of the first conductive semiconductor layer  122 . The first electrode  151  may include, for example, at least one of Al, Au, Cr, Ni, Ti, and Sn. The second electrode  152  may be formed of a reflective metal. For example, the second electrode  152  may include a material such as Ag, Ni, Al, Cr, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, or the like, and may have a single layer or a structure of two or more layers. 
     Next, a planarization insulating layer  161  having a substantially flat surface may be formed on the gap-fill insulating film  140 . As explained in detail below, the planarization insulating layer  161  may include first and second insulating layers  161   a  and  161   b  with a reflective layer  175  disposed between the first and second insulating layers  161   a  and  161   b.    
     Referring to  FIGS. 11A and 111B , the first insulating layer  161   a  may be formed on the gap-fill insulating film  140 , and the reflective layer  175  may be formed on the first insulating layer  161   a.    
     The first insulating layer  161   a  may be formed on the gap-fill insulating film  140  to cover the first and second electrodes  151  and  152 . The first insulating layer  161   a  may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. The reflective layer  175  may include a reflective metal layer, a distributed Bragg reflection (DBR) layer, or an omnidirectional reflection (ODR) layer. The reflective metal layer may include, for example, Ag, Ni, or Al. When the reflective layer  175  includes a conductive layer, the first and second open areas OPa and OPb may be formed in regions corresponding to the first and second electrodes  151  and  152 , respectively. 
     Referring to  FIGS. 12A and 12B , the second insulating layer  161   b  may be formed on the first insulating layer  161   a  to cover the reflective layer  175 , and then, the first and second connection electrodes  181  and  182  may be formed to be connected to the first and second electrodes  151  and  152 , respectively. 
     The first and second connection electrodes  181  and  182  may be formed using, for example, a dual damascene process. The first and second connection electrodes  181  and  182  may have pad portions  181 P and  182 P exposed on the surface of the planarization insulating layer  161 . The pad portions  181 P and  182 P may be configured such that contact areas of the first and second connection electrodes  181  and  182  may be extended. 
     After forming the first and second connection electrodes  181  and  182 , the surface of the second insulating layer  161   b  may be planarized using a chemical mechanical polishing process (CMP). In this process, the surfaces of the first and second connection electrodes  181  and  182  may also be made substantially coplanar with the planarized surface of the second insulating layer  161   b.    
       FIGS. 13 to 15  are cross-sectional views illustrating main processes of a bonding process and a wavelength conversion unit forming process in a method of fabricating an LED module according to an example embodiment. For convenience of description, a second sub-pixel SP 2  is illustrated, but first, third, and fourth sub-pixels SP 1 , SP 3 , and SP 4  may be formed in a similar manner. The configuration of the light emission window may be determined by the wavelength of the light of the first to fourth LED cells. 
     Referring to  FIGS. 13 and 16 , the LED module  100  and the circuit board  200  may be bonded such that the planarization insulating layer  161  of the LED module  100  and the dielectric layer  281  of the circuit board  200  face each other. The planarization insulating layer  161  and the dielectric layer  281  may be formed of the same material. For example, the planarization insulating layer  161  and the dielectric layer  281  may include silicon oxide. In the present example embodiment, the LED module  100  and the circuit board  200  are respectively formed of a wafer. 
     Referring to  FIG. 16 , wafer for the LED module  100  and the wafer for the circuit board  200  may be bonded to each other, i.e., wafer level bonding may be used to combine the LED module  100  with the circuit board  200 . This bonding process may be performed using a wafer bonding process such as fusion bonding or hybrid bonding. 
     For example, the LED module  100  (which is the first substrate structure) and the circuit board  200  (which is the second substrate structure) may be disposed such that the planarization insulating layer  161  and a planarized surface of the dielectric layer  281  face each other, and may be disposed such that the pad portions  181 P and  182 P of the connection electrodes  181  and  182  and bonding pads  285 P of the metal wire  285  correspond to each other, respectively. Subsequently, a high temperature annealing process may be performed while the planarization insulating layer  161  and the dielectric layer  281  are directly bonded to each other, and relatively stronger bond strength may be provided by covalent bonding. The insulating material forming the planarization insulating layer  161  and the dielectric layer  281  may include silicon oxide, or may include other suitable materials (e.g., SiCN) that may be bonded to each other. Also, in this process, the bonding pads  285 P and the pad portions  181 P and  182 P formed of a metal such as copper may also be mechanically/electrically bonded. 
     Referring to  FIG. 14 , regions of the growth substrate  110  corresponding to the second LED cell C 2  may be selectively etched to form a second light emission window W 2 . The process of forming the second light emission window W 2  may be performed after grinding the growth substrate  110  to a predetermined thickness. 
     Referring to  FIG. 15 , a second wavelength conversion unit  192   a  may be formed by dispensing a light transmissive liquid resin (in which the wavelength conversion material P 2  is mixed) into the second light emission window W 2 , respectively, and a second light adjusting unit  192  may be formed by adding a second filter layer  192   b . As described above with reference to  FIG. 3 , similarly, a first light adjusting unit  191  having a first wavelength conversion unit  191   a  and a first filter layer  191   b  may be formed in the first light emission window W 1 , and partially lighted. A portion of the emission windows, for example, the third light emission window W 3 , may be configured to directly emit light emitted from the LED cell. Subsequently, by cutting into module units including a plurality of pixels by using a blade, the LED module  10  for display illustrated in  FIGS. 1 and 2  may be manufactured. 
     As described above, the first substrate structure  100  providing the LED module and the circuit board  200  as the second substrate structure including the TFT cell  245  may be bonded to each other, and then, the bonded substrate structure may be cut into module units. Therefore, a display module including a plurality of pixels may be easily manufactured at the wafer level. In addition, a high resolution display module including a plurality of pixels may be provided. Thus, the time required for transferring a pixel unit in a manufacturing process of a display device using a micro LED may be significantly reduced. 
     Also, as described above, the gap-fill insulating film may effectively fill the space between the plurality of LED cells by forming a light emitting structure for the plurality of LED cells in a divided growth method, thereby significantly improving the reliability in the planarization process. 
       FIG. 17  is a cross-sectional view illustrating an LED module for display according to an example embodiment. 
     Referring to  FIG. 17 , an LED module for display (or a display panel) according to the present example embodiment may be similar to the LED module for display illustrated in  FIG. 3 , except that the cover insulating film  131   b  protecting the light blocking film  135  is provided while a separate reflective layer ( 175  in  FIG. 3 ) is not introduced, the divided growth process for the light emitting structure LS is changed, and respective sub-pixels SP 1 , SP 2  and SP 3  are configured to emit white light. In addition, the components of this embodiment may be understood with reference to the description of the same or similar components of the LED module for display illustrated in  FIG. 3  unless otherwise stated. 
     In the present example embodiment, the LED module  100  may include a cover insulating film  131   b  protecting the light blocking film  135  disposed in the protective insulating film ( 131   a ) region that is located in the space between the plurality of LED cells C 1 , C 2 , and C 3 , for example, in the isolation region. The cover insulating film  131   b  may prevent the elements of the light blocking film  135  from being diffused into the gap-fill insulating film in a subsequent process. The cover insulating film  131   b  may include the same material as the protective insulating film  131   a . For example, the cover insulating film  131   b  may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. 
     On the other hand, unlike the previous embodiment, a separate reflective layer  175  (see  FIG. 3 ) may not be introduced into the planarization insulating layer  161 . Also in the present example embodiment, the second electrode  152  and the light blocking film  135  may be configured to have light reflectivity, to replace a separate reflective layer. 
     In the present example embodiment, the light emitting structure LS may be grown by a divided growth process having conditions different from those described above. The lower light emitting structure LS 1  may include an undoped semiconductor layer  121  and a first conductivity-type lower semiconductor layer  122   a , while the upper light emitting structure LS 2 ′ may include a first conductivity-type upper semiconductor layer  122   b , an active layer  125 , and a second conductivity-type semiconductor layer  127 , sequentially formed in one region of an upper surface of the lower light emitting structure LS 1 . In the present example embodiment, the active layer  125  may be formed on the first conductivity-type upper semiconductor layer  122   b  to be regrown. Thus, relatively excellent crystallinity may be expected. 
     Respective sub-pixels SP 1 , SP 2 , and SP 3  employed in the present example embodiment may be configured to emit white light. The active layer  125  may be configured to emit blue light (e.g., of 440 nm to 460 nm) or ultraviolet or near ultraviolet light (e.g., of 380 nm to 440 nm), and a wavelength conversion unit  190  disposed in the respective light emission windows LW may be configured to emit white light by a light transmissive resin  195  and at least one or more wavelength conversion materials P 1  and P 2  mixed in the resin. 
     In another example embodiment, the active layer  125  may be configured to emit blue light, and first and second wavelength conversion materials P 1  and P 2  of the wavelength conversion unit  190  may include green and red phosphors, respectively. In this case, a color filter array may be introduced on an upper portion of the display LED module to emit blue, green and red colors from respective sub-pixels SP 1 , SP 2  and SP 3 . 
       FIG. 18  is a schematic diagram illustrating a cross-sectional structure of a quantum dot (QD) as a wavelength conversion material usable in an LED module according to an example embodiment. 
     Referring to  FIG. 18 , the quantum dot QD may have a core-shell structure using a III-V or II-VI compound semiconductor. For example, the quantum dot QD may have a core such as CdSe, InP or the like, and a shell such as ZnS or ZnSe. The quantum dot may include a ligand for stabilizing the core and the shell. 
     The core diameter may be, for example, 1 to 30 nm or 3 to 10 nm, and the shell thickness may be 0.1 to 20 nm or 0.5 to 2 nm. The quantum dot may implement various colors depending on the size. When used as a phosphor substitute material, the quantum dot may be used instead of a red or green phosphor. In the case of using a quantum dot, a narrow full-width at half-maximum (e.g., of about 35 nm) may be implemented. 
     As set forth above, by forming a light emitting structure for a plurality of LED cells in a divided growth method, a gap-fill insulating film may be effectively filled in the space between the plurality of LED cells, and the reliability of a planarization process may be improved. As a result, a circuit board (or a second substrate structure) having a TFT cell at a wafer level and a substrate (or a first substrate structure) on which a plurality of LED cells are formed may be firmly bonded. 
     As described above, embodiments may provide an LED module having a structure that may effectively fill the space between a plurality of LED cells. Embodiments may provide a method of fabricating an LED module, in which a space between a plurality of LED cells may be effectively filled to improve reliability of a planarization process. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.