Patent Publication Number: US-7902898-B2

Title: Delay circuit

Description:
BACKGROUND 
     1. Field of Invention 
     The present invention relates to a delay circuit. More particularly, the present invention relates to a delay circuit in a reset integrated circuit (IC). 
     2. Description of Related Art 
     For a conventional reset integrated circuit (IC) employed for circuit protection, a delay circuit therein is usually provided for preventing the reset IC from mis-operation caused by a power glitch, in which the delay time configured by the delay circuit can be correspondingly changed by using different extrinsic capacitors. However, it is not convenient to replace different extrinsic capacitors whenever various kinds of delay time are to be configured. 
     SUMMARY 
     In accordance with one embodiment of the present invention, a delay circuit is provided. The delay circuit includes a plurality of current sources, a plurality of switches, a transistor switch, a charging unit and a comparator. Each of the switches is provided for receiving an enable signal to activate and convey one of the current sources. The transistor switch is activated for pulling down voltage of an operating node coupled to the switches. The charging unit provides an operating voltage for the operating node based on one of the current sources when the transistor switch is deactivated and one of the switches is activated to convey one of the current sources to the charging unit. The comparator is provided for comparing the operating voltage with a reference voltage. 
     In accordance with another embodiment of the present invention, a delay circuit is provided. The delay circuit includes a plurality of current sources, a plurality of switches, a transistor switch, a charging unit and a comparator. Each of the switches has a first end and a second end, in which the first end of each of the switches is coupled to one of the current sources, and the second ends of the switches are coupled to an operating node. The transistor switch is coupled between the operating node and a low voltage and activated for pulling down voltage of the operating node. The charging unit is coupled between the operating node and the low voltage. The comparator has a first input coupled to the operating node and a second input coupled to a reference voltage. 
     It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the following detailed description of the embodiments, with reference to the accompanying drawings as follows: 
         FIG. 1  illustrates a general block diagram of a reset integrated circuit (IC) according to one embodiment of the present invention; 
         FIG. 2  illustrates the delay circuit as shown in  FIG. 1  according to one embodiment of the present invention; 
         FIG. 3  illustrates the delay circuit as shown in  FIG. 1  according to another embodiment of the present invention; and 
         FIG. 4  illustrates the tri-state logic gate as shown in  FIG. 3  according to one embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     In the following detailed description, the embodiments of the present invention have been shown and described. As will be realized, the invention is capable of modification in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive. 
       FIG. 1  illustrates a general block diagram of a reset integrated circuit (IC) according to one embodiment of the present invention. The reset integrated circuit  100  includes a voltage divider  102 , a comparator  104 , a delay circuit  110 , and a transistor switch  106 , in which the comparator  104  can be an operational amplifier OP 1  and the transistor switch  106  can be an NMOS transistor M 1 . The voltage divider  102  provides a dividing voltage for the comparator  104 . The comparator  104  compares the dividing voltage from the voltage divider  102  with a reference voltage VREF 1  and thus generates an output signal. The delay circuit  110  is provided for delaying the output signal from the comparator  104 . The transistor switch  106  operates with the delayed output signal and generates an output signal VOUT. Specifically, when the voltage divider  102  provides a dividing voltage larger than the reference voltage VREF 1 , due to a high power voltage, the comparator  104  generates a deactivation signal. Then, the delay circuit  110  delays the deactivation signal for deactivating the transistor switch  106 , and the output signal VOUT, being a reset signal or a protection signal, is accordingly generated. 
       FIG. 2  illustrates the delay circuit as shown in  FIG. 1  according to one embodiment of the present invention. The delay circuit includes a plurality of current sources (i.e. I 1 , I 2 , I 3 , etc.), a plurality of switches (i.e. S 1 , S 2 , S 3 , etc.), a transistor switch  202 , a charging unit  204  and a comparator  206 . The current sources I 1 , I 2 , I 3  . . . can be configured as a geometric sequence; that is, the current source I 1  has a current value of I 0 , the current source I 2  has a current value of I 0 ×2 1 , the current source I 3  has a current value of I 0 ×2 2 , and etc. Each of the switches S 1 , S 2 , S 3 , . . . , is provided for receiving an enable signal to activate and convey the corresponding current sources I 1 , I 2 , I 3 , . . . . The transistor switch  202  is activated for pulling down the voltage of an operating node Q coupled to the switches S 1 , S 2 , S 3 , . . . . The charging unit  204  provides an operating voltage for the operating node Q based on one of the current sources I 1 , I 2 , I 3 , . . . when the transistor switch  202  is deactivated and one of the switches S 1 , S 2 , S 3 , . . . is activated to convey one of the current sources I 1 , I 2 , I 3 , . . . to the charging unit  204 . The comparator  206  compares the operating voltage of the operating node Q with a reference voltage VREF 2  and outputs an output signal to, for example, the transistor M 1  as shown in  FIG. 1 . 
     As shown in  FIG. 2 , the transistor switch  202  can be an NMOS transistor M 2 , the charging unit  204  can be a capacitor C 1 , and the comparator  206  can be an operational amplifier OP 2 . The transistor M 2  has a gate coupled to, for example, the output of the operational amplifier OP 1  as shown in  FIG. 1 , a drain coupled to the operating node Q, and a source coupled to a ground voltage GND. The capacitor C 1  is coupled between the operating node Q and the ground voltage GND. The operational amplifier OP 2  has a first input coupled to the operating node Q and a second input coupled to the reference voltage VREF 2 . Moreover, each of the switches S 1 , S 2 , S 3 , . . . has a first end and a second end, in which the first ends of the switches S 1 , S 2 , S 3 , . . . are separately and correspondingly coupled to the current sources I 1 , I 2 , I 3 , . . . and the second ends of the switches S 1 , S 2 , S 3 , . . . are all coupled to the operating node Q. 
     In operation, when the transistor M 2  receives the deactivation signal from, for example, the operational amplifier OP 1  as shown in  FIG. 1 , to be deactivated and one of the switches S 1 , S 2 , S 3 , . . . is activated to convey one of the current sources I 1 , I 2 , I 3 , . . . to the capacitor C 1  such that the capacitor C 1  is charged by one of the current sources I 1 , I 2 , I 3 , . . . through one of the switches S 1 , S 2 , S 3 , . . . , the capacitor C 1  will provide an operating voltage for the operating node Q. After that, if the operating voltage of the operating node Q provided by the capacitor C 1  increases to be larger than the reference voltage VREF 2 , the operational amplifier OP 2  outputs the output signal, being the delayed deactivation signal, to the transistor M 1  as shown in  FIG. 1  and deactivates the transistor M 1 . 
       FIG. 3  illustrates the delay circuit as shown in  FIG. 1  according to another embodiment of the present invention. Compared to  FIG. 2 , the delay circuit  300  further includes a tri-state logic gate  310 . The tri-state logic gate  310  has a logic input IN and three logic outputs (i.e. VO 1 , VO 2 , VO 3 ), in which each of the logic outputs is provided for outputting the enable signal to activate one of the switches (e.g. S 1 , S 2 , S 3 ) based on the state of the logic input IN. For example, the logic output VO 1  outputs the enable signal to activate the switch S 1  if the logic input IN is at low level; the logic output VO 2  outputs the enable signal to activate the switch S 2  if the logic input IN is floated; and the logic output VO 3  outputs the enable signal to activate the switch S 3  if the logic input IN is at high level. In addition, the delay circuit  300  can further include multiple tri-state logic gates  310  for controlling even more switches. 
       FIG. 4  illustrates the tri-state logic gate as shown in  FIG. 3  according to one embodiment of the present invention. The tri-state logic gate  400  includes three parts separately corresponding to the logic output VO 1 , VO 2  and VO 3 . In regard to the logic output VO 1 , the tri-state logic gate  400  includes a pull-up unit  402  and an inverter  404 . The pull-up unit  402  is coupled to the logic input IN and generates a low-level signal when the logic input IN is at low level. The inverter  404  is coupled between the pull-up unit  402  and the logic output VO 1  and converts the low-level signal from the pull-up unit  402  into a high-level signal as the enable signal. In regard to the logic output VO 2 , the tri-state logic gate  400  includes a pull-down unit  406 , a pull-up unit  408 , an inverter  410  and a NAND logic unit  412 . The pull-down unit  406  is coupled to the logic input IN and generates a low-level signal when the logic input IN is floated or at low level. The pull-up unit  408  is coupled to the logic input IN and generates a high-level signal when the logic input IN is floated or at high level. The inverter  410  converts the high-level signal from the pull-up unit  408  into a low-level signal. The NAND logic unit  412  has an output coupled to the logic output VO 2  and performs NAND operation of the low-level signals from the pull-down unit  406  and the inverter  410  to generate a high-level signal as the enable signal. In regard to the logic output VO 3 , the tri-state logic gate  400  includes a pull-down unit  414  and inverters  416  and  418 . The pull-down unit  414  is coupled to the logic input IN and generates a high-level signal when the logic input is at high level. The inverter  416  converts the high-level signal from the pull-down unit  414  into a low-level signal. The inverter  418  has an output coupled to the logic output VO 3  and converts the low-level signal from the inverter  416  into a high-level signal as the enable signal. 
     In the present embodiment, the pull-up unit  402  includes a pull-up PMOS transistor MP 1  and an inverter consisting of a PMOS transistor MP 2  and an NMOS transistor MN 1 . The transistor MP 1  has a gate coupled to the logic input IN, a source coupled to the power voltage VDD, and a drain coupled to the ground voltage GND through a resistor R 1 . The inverter  404  and the inverter consisting of the transistors MP 2  and MN 1  are serially coupled between the drain of the transistor MP 1  and the logic output VO 1 . 
     Furthermore, the pull-down unit  406  includes a pull-down NMOS transistor MN 2  and an inverter consisting of a PMOS transistor MP 3  and an NMOS transistor MN 3 . The transistor MN 2  has a gate coupled to the logic input IN, a drain coupled to the power voltage VDD through a resistor R 2 , and a source coupled to the ground voltage GND. The inverter consisting of the transistors MP 3  and MN 3  is coupled between the drain of the transistor MN 2  and a first NAND input of the NAND logic unit  412 . The pull-up unit  408  includes a pull-up PMOS transistor MP 4  and an inverter consisting of a PMOS transistor MP 5  and an NMOS transistor MN 4 . The transistor MP 4  has a gate coupled to the logic input IN, a source coupled to the power voltage VDD, and a drain coupled to the ground voltage GND through a resistor R 3 . The inverter  410  and the inverter consisting of the transistors MP 5  and MN 4  are serially coupled between the drain of the transistor MP 4  and a second NAND input of the NAND logic unit  412 . 
     Moreover, the pull-down unit  414  includes a pull-down NMOS transistor MN 5  and an inverter consisting of a PMOS transistor MP 6  and an NMOS transistor MN 6 . The transistor MN 5  has a gate coupled to the logic input IN, a drain coupled to the power voltage VDD through a resistor R 4 , and a source coupled to the ground voltage GND. The inverters  418  and  416  and the inverter consisting of the transistors MP 6  and MN 6  are serially coupled between the drain of the transistor MN 5  and the logic output VO 3 . 
     In operation, the logic input IN has three different states which are “low” (logic 0), “high” (logic 1) and floating (unknown) at different moments. If the logic input IN is at low level, the node N 1  is at high level, the node N 2  is at low level, and the logic output VO 1  is then at high level. At that moment, the node N 3  is at high level such that the node N 4  is at low level, and the node N 5  is at high level such that the node N 6  is at low level and the output of the inverter  410  is at high level, thus causing the logic output VO 2  to be at low level. At the same time, the node N 7  is at high level such that the node N 8  is at low level, thus causing the logic output VO 3  to be at low level. 
     In another aspect, if the logic input IN is floated, the node N 1  is at low level such that the node N 2  is at high level, thus causing the logic output VO 1  to be at low level. At that moment, the node N 3  is at high level such that the node N 4  is at low level, and the node N 5  is at low level such that the node N 6  is at high level and the output of the inverter  410  is at low level, thus causing the logic output VO 2  to be at high level. At the same time, the node N 7  is at high level such that the node N 8  is at low level, thus causing the logic output VO 3  to be at low level. 
     In yet another aspect, if the logic input IN is at high level, the node N 1  is at low level such that the node N 2  is at high level, thus causing the logic output VO 1  to be at low level. At that moment, the node N 3  is at low level such that the node N 4  is at high level, and the node N 5  is at low level such that the node N 6  is at high level and the output of the inverter  410  is at low level, thus causing the logic output VO 2  to be at high level. At the same time, the node N 7  is at low level such that the node N 8  is at high level, thus causing the logic output VO 3  to be at high level. The states of the logic outputs VO 1 , VO 2  and VO 3  corresponding to different states of the logic input IN can be shown in Table I as follows. 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                 IN 
                 VO3 
                 VO2 
                 VO1 
               
               
                   
                   
               
             
            
               
                   
                 0 
                 0 
                 0 
                 1 
               
               
                   
                 NA 
                 0 
                 1 
                 0 
               
               
                   
                 1 
                 1 
                 0 
                 0 
               
               
                   
                   
               
            
           
         
       
     
     For the foregoing embodiments, the delay circuit can be employed to conveniently configure the delay time for the reset IC without replacing the capacitor. Moreover, there also can be multiple choices of configuring the delay time. 
     As is understood by a person skilled in the art, the foregoing embodiments of the present invention are illustrative of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.