Patent Publication Number: US-7221026-B2

Title: Computer systems containing resistors which include doped silicon/germanium

Description:
RELATED PATENT DATA 
   This patent resulted from a divisional application of U.S. patent application Ser. No. 10/263,608, which was filed Oct. 2, 2002, and which is now U.S. Pat. No. 6,873,015. 

   TECHNICAL FIELD 
   The invention pertains to semiconductor constructions comprising transistors and resistors; and also pertains to methods of forming semiconductor constructions. In particular aspects, the invention pertains to processes of forming resistor constructions. 
   BACKGROUND OF THE INVENTION 
   SOI technology differs from traditional bulk semiconductor technologies in that the active semiconductor material of SOI technologies is typically much thinner than that utilized in bulk technologies. The active semiconductor material of SOI technologies will typically be formed as a thin film over an insulating material (typically oxide), with exemplary thicknesses of the semiconductor film being less than or equal to 2000 Å. In contrast, bulk semiconductor material will typically have a thickness of at least about 200 microns. The thin semiconductor of SOI technology can allow higher performance and lower power consumption to be achieved in integrated circuits than can be achieved with similar circuits utilizing bulk materials. 
   An exemplary integrated circuit device that can be formed utilizing SOI technologies is a so-called thin film transistor (TFT), with the term “thin film” referring to the thin semiconductor film of the SOI construction. In particular aspects, the semiconductor material of the SOI construction can be silicon, and in such aspects the TFTs can be fabricated using recrystallized amorphous silicon or polycrystalline silicon. The silicon can be supported by an electrically insulative material (such as silicon dioxide), which in turn is supported by an appropriate substrate. Exemplary substrate materials include glass, bulk silicon and metal-oxides (such as, for example, Al 2 O 3 ). If the semiconductor material comprises silicon, the term SOI is occasionally utilized to refer to a silicon-on-insulator construction, rather than the more general concept of a semiconductor-on-insulator construction. However, it is to be understood that in the context of this disclosure the term SOI refers to semiconductor-on-insulator constructions. Accordingly, the semiconductor material of an SOI construction referred to in the context of this disclosure can comprise other semiconductive materials in addition to, or alternatively to, silicon; including, for example, germanium. 
   A problem associated with conventional TFT constructions is that grain boundaries and defects can limit carrier mobilities. Accordingly, carrier mobilities are frequently nearly an order of magnitude lower than they would be in bulk semiconductor devices. High voltage (and therefore high power consumption), and large areas are utilized for the TFTs, and the TFTs exhibit limited performance. TFTs thus have limited commercial application and currently are utilized primarily for large area electronics. 
   Various efforts have been made to improve carrier mobility of TFTs. Some improvement is obtained for devices in which silicon is the semiconductor material by utilizing a thermal anneal for grain growth following silicon ion implantation and hydrogen passivation of grain boundaries (see, for example, Yamauchi, N. et al., “Drastically Improved Performance in Poly-Si TFTs with Channel Dimensions Comparable to Grain Size”, IEDM Tech. Digest, 1989, pp. 353–356). Improvements have also been made in devices in which a combination of silicon and germanium is the semiconductor material by optimizing the germanium and hydrogen content of silicon/germanium films (see, for example, King, T. J. et al, “A Low-Temperature (&lt;=550° C.) Silicon-Germanium MOS TFT Technology for Large-Area Electronics”, IEDM Tech. Digest, 1991, pp. 567–570). 
   Investigations have shown that nucleation, direction of solidification, and grain growth of silicon crystals can be controlled selectively and preferentially by excimer laser annealing, as well as by lateral scanning continuous wave laser irradiation/anneal for recrystallization (see, for example, Kuriyama, H. et al., “High Mobility Poly-Si TFT by a New Excimer Laser Annealing Method for Large Area Electronics”, IEDM Tech. Digest, 1991, pp. 563–566; Jeon, J. H. et al., “A New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealing”, IEDM Tech. Digest, 2000, pp. 213–216; Kim, C. H. et al., “A New High-Performance Poly-Si TFT by Simple Excimer Laser Annealing on Selectively Floating a Si Layer”, IEDM Tech. Digest, 2001, pp. 753–756; Hara, A. et al, “Selective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Layer Irradiation”, IEDM Tech. Digest, 2000, pp. 209–212; and Hara, A. et al., “High Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallization”, IEDM Tech. Digest, 2001, pp. 747–750). Such techniques have allowed relatively defect-free large crystals to be grown, with resulting TFTs shown to exhibit carrier mobility over 300 cm 2 /V-second. 
   Another technique which has shown promise for improving carrier mobility is metal-induced lateral recrystallization (MILC), which can be utilized in conjunction with an appropriate high temperature anneal (see, for example, Jagar, S. et al., “Single Grain TFT with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization”, IEDM Tech. Digest, 1999, p. 293–296; and Gu, J. et al., “High Performance Sub-100 nm Si TFT by Pattern-Controlled Crystallization of Thin Channel Layer and High Temperature Annealing”, DRC Conference Digest, 2002, pp. 49–50). A suitable post-recrystallization anneal for improving the film quality within silicon recrystallized by MILC is accomplished by exposing recrystallized material to a temperature of from about 850° C. to about 900° C. under an inert ambient (with a suitable ambient comprising, for example, N 2 ). MILC can allow nearly single crystal silicon grains to be formed in predefined amorphous-silicon islands for device channel regions. Nickel-induced-lateral-recrystallization can allow device properties to approach those of single crystal silicon. 
   The carrier mobility of a transistor channel region can be significantly enhanced if the channel region is made of a semiconductor material having a strained crystalline lattice (such as, for example, a silicon/germanium material having a strained lattice, or a silicon material having a strained lattice) formed over a semiconductor material having a relaxed lattice (such as, for example, a silicon/germanium material having a relaxed crystalline lattice). (See, for example, Rim, K. et al., “Strained Si NMOSFETs for High Performance CMOS Technology”, VLSI Tech. Digest, 2001, p. 59–60; Cheng, Z. et al., “SiGe-On-Insulator (SGOI) Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” 2001 IEEE SOI Conference Digest, October 2001, pp. 13–14; Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57–58; and Mizuno, T. et al., “High Performance CMOS Operation of Strained-SOI MOSFETs Using Thin Film SiGe-on-Insulator Substrate”, VLSI Tech. Digest, 2002, p. 106–107.) 
   The terms “relaxed crystalline lattice” and “strained crystalline lattice” are utilized to refer to crystalline lattices which are within a defined lattice configuration for the semiconductor material, or perturbed from the defined lattice configuration, respectively. In applications in which the relaxed lattice material comprises silicon/germanium having a germanium concentration of from 10% to 60%, mobility enhancements of 110% for electrons and 60–80% for holes can be accomplished by utilizing a strained lattice material in combination with the relaxed lattice material (see for example, Rim, K. et al., “Characteristics and Device Design of Sub-100 nm Strained SiN and PMOSFETs”, VLSI Tech. Digest, 2002, 00. 98–99; and Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57–58). 
   Performance enhancements of standard field effect transistor devices are becoming limited with progressive lithographic scaling in conventional applications. Accordingly, strained-lattice-channeled-field effect transistors on relaxed silicon/germanium offers an opportunity to enhance device performance beyond that achieved through conventional lithographic scaling. IBM recently announced the world&#39;s fastest communications chip following the approach of utilizing a strained crystalline lattice over a relaxed crystalline lattice (see, for example, “IBM Builds World&#39;s Fastest Communications Microchip”, Reuters U.S. Company News, Feb. 25, 2002; and Markoff, J., “IBM Circuits are Now Faster and Reduce Use of Power”, The New York Times, Feb. 25, 2002). 
   Although various techniques have been developed for substantially controlling nucleation and grain growth processes of semiconductor materials, grain orientation control is lacking. Further, the post-anneal treatment utilized in conjunction with MILC can be unsuitable in applications in which a low thermal budget is desired. Among the advantages of the invention described below is that such can allow substantial control of crystal grain orientation within a semiconductor material, while lowering thermal budget requirements relative to conventional methods. Additionally, the quality of the grown crystal formed from a semiconductor material can be improved relative to that of conventional methods. 
   Field effect transistor devices can be utilized in various types of circuitry. For instance, field effect transistor devices can be incorporated into transistor/resistor constructions.  FIG. 1  shows a schematic diagram of a construction  2  comprising a transistor  4  and a resistor  6 . The transistor has one source/drain region extending through the resistor to V DD  potential, and has another source/drain region at ground potential. The gate of the transistor is tied to an electrical node  8  which controls potential and/or current flow at the gate. 
   Transistors and resistors are common components of semiconductor circuitry. A continuing goal in fabrication of semiconductor circuitry is to increase a density of the circuitry. Accordingly, there is a continuing goal to reduce the footprint associated with transistor/resistor constructions, while maintaining desired performance characteristics of the constructions. 
   SUMMARY OF THE INVENTION 
   In one aspect, the invention pertains to a semiconductor construction comprising a transistor device and a resistor. The transistor device includes a gate and an active region proximate the gate. The active region comprises a pair of source/drain regions. A resistor is in electrical connection with one of the source/drain regions. The resistor comprises a first crystalline layer and a second crystalline layer over the first crystalline layer. The second crystalline layer has a different composition than the first crystalline layer. The second crystalline layer comprises doped silicon/germanium and the first crystalline layer comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). 
   In another aspect, the invention encompasses a process of forming a resistor construction. A first crystalline layer is formed over a substrate. The first crystalline layer comprises one or more silicon seed crystals. A second crystalline layer is formed over the first crystalline layer. The second crystalline comprises Si/Ge. The first and second layers together are comprised by a resistor which extends between a first electrical node and a second electrical node. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Preferred embodiments of the invention are described below with reference to the following accompanying drawings. 
       FIG. 1  is a schematic diagram of a prior art construction comprising a transistor and resistor. 
       FIG. 2  is a diagrammatic, cross-sectional view of a fragment of a semiconductor construction shown at a preliminary stage of an exemplary process of the present invention 
       FIG. 3  is a view of the  FIG. 2  wafer shown at a processing stage subsequent to that of  FIG. 2 . 
       FIG. 4  is a view of the  FIG. 2  fragment shown at a processing stage subsequent to that of  FIG. 3 . 
       FIG. 5  is a view of the  FIG. 2  fragment shown at a processing stage subsequent to that of  FIG. 4 . 
       FIG. 6  is a view of the  FIG. 2  fragment shown at a processing stage subsequent to that of  FIG. 5 . 
       FIG. 7  is a view of the  FIG. 2  fragment shown at a processing stage subsequent to that of  FIG. 6 . 
       FIG. 8  is an expanded region of the  FIG. 7  fragment shown at a processing stage subsequent to that of  FIG. 7  in accordance with an exemplary embodiment of the present invention. 
       FIG. 9  is a view of the  FIG. 8  fragment shown at a processing stage subsequent to that of  FIG. 8 . 
       FIG. 10  is a view of an expanded region of  FIG. 7  shown at a processing stage subsequent to that of  FIG. 7  in accordance with an alternative embodiment relative to that of  FIG. 8 . 
       FIG. 11  is a diagrammatic, cross-sectional view of a semiconductor fragment illustrating an exemplary semiconductor construction comprising a transistor and resistor. 
       FIG. 12  is a top cross-sectional view along the line  12 — 12  of the construction comprising the  FIG. 11  fragment. The  FIG. 11  cross-section is along the line  11 — 11  of  FIG. 12 . 
       FIG. 13  is a diagrammatic view of a computer illustrating an exemplary application of the present invention. 
       FIG. 14  is a block diagram showing particular features of the motherboard of the  FIG. 13  computer. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   An exemplary method of forming an SOI construction in accordance with an aspect of the present invention is described with reference to  FIGS. 2–7 . 
   Referring initially to  FIG. 2 , a fragment of a semiconductor construction  10  is illustrated at a preliminary processing stage. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. 
   Construction  10  comprises a base (or substrate)  12  and an insulator layer  14  over the base. Base  12  can comprise, for example, one or more of glass, aluminum oxide, silicon dioxide, metal and plastic. Additionally, and/or alternatively, base  12  can comprise a semiconductor material, such as, for example, a silicon wafer. 
   Layer  14  comprises an electrically insulative material, and in particular applications can comprise, consist essentially of, or consist of silicon dioxide. In the shown construction, insulator layer  14  is in physical contact with base  12 . It is to be understood, however, that there can be intervening materials and layers provided between base  12  and layer  14  in other aspects of the invention (not shown). For example, a chemically passive thermally stable material, such as silicon nitride (Si 3 N 4 ), can be incorporated between base  12  and layer  14 . Layer  14  can have a thickness of, for example, from about 200 nanometers to about 500 nanometers, and can be referred to as a buffer layer. 
   Layer  14  preferably has a planarized upper surface. The planarized upper surface can be formed by, for example, chemical-mechanical polishing. 
   A layer  16  of semiconductive material is provided over insulator layer  14 . In the shown embodiment, semiconductive material layer  16  is formed in physical contact with insulator  14 . Layer  16  can have a thickness of, for example, from about 5 nanometers to about 10 nanometers. Layer  16  can, for example, comprise, consist essentially of, or consist of either doped or undoped silicon. If layer  16  comprises, consists essentially of, or consists of doped silicon, the dopant concentration can be from about 10 14  atoms/cm 3  to about 10 20  atoms/cm 3 . The dopant can be either n-type or p-type, or a combination of n-type and p-type. 
   The silicon utilized in layer  16  can be either polycrystalline silicon or amorphous silicon at the processing stage of  FIG. 2 . It can be advantageous to utilize amorphous silicon in that it is typically easier to deposit a uniform layer of amorphous silicon than to deposit a uniform layer of polycrystalline silicon. 
   Referring to  FIG. 3 , material  16  is patterned into a plurality of discrete islands (or blocks)  18 . Such can be accomplished utilizing, for example, photoresist (not shown) and photolithographic processing, together with an appropriate etch of material  16 . 
   A capping layer  20  is provided over islands  18  and over portions of layer  14  exposed between the islands. Layer  20  can, for example, comprise, consist essentially of, or consist of one or both of silicon dioxide and silicon. Layer  20  can also comprise multiple layers of silicon dioxide, stress-free silicon oxynitride, and silicon. 
   After formation of capping layer  20 , small voids (nanovoids) and small crystals are formed in the islands  18 . The formation of the voids and crystals can be accomplished by ion implanting helium  22  into material  16  and subsequently exposing material  16  to laser-emitted electromagnetic radiation. The helium can aid in formation of the nanovoids; and the nanovoids can in turn aid in crystallization and stress relief within the material  16  during exposure to the electromagnetic radiation. The helium can thus allow crystallization to occur at lower thermal budgets than can be achieved without the helium implantation. The helium is preferably implanted selectively into islands  18  and not into regions between the islands. The exposure of construction  10  to electromagnetic radiation can comprise subjecting the construction to scanned continuous wave laser irradiation while the construction is held at an appropriate elevated temperature (typically from about 300° C. to about 450° C.). The exposure to the electromagnetic radiation can complete formation of single crystal seeds within islands  18 . The laser irradiation is scanned along an axis  24  in the exemplary shown embodiment. 
   The capping layer  20  discussed previously is optional, but can beneficially assist in retaining helium within islands  18  and/or preventing undesirable impurity contamination during the treatment with the laser irradiation. 
   Referring to  FIG. 4 , islands  18  are illustrated after voids have been formed therein. Additionally, small crystals (not shown) have also been formed within islands  18  as discussed above. 
   Capping layer  20  ( FIG. 3 ) is removed, and subsequently a layer  26  of semiconductive material is formed over islands  18 . Layer  26  can comprise, consist essentially of, or consist of silicon and germanium; or alternatively can comprise, consist essentially of, or consist of doped silicon/germanium. The germanium concentration within layer  26  can be, for example, from about 10 atomic percent to about 60 atomic percent. In the shown embodiment, layer  26  physically contacts islands  18 , and also physically contacts insulator layer  14  in gaps between the islands. Layer  26  can be formed to a thickness of, for example, from about 50 nanometers to about 100 nanometers, and can be formed utilizing a suitable deposition method, such as, for example, plasma-assisted chemical vapor deposition. 
   A capping layer  28  is formed over semiconductor layer  26 . Capping layer  28  can comprise, for example, silicon dioxide. Alternatively, capping layer  28  can comprise, for example, a combination of silicon dioxide and stress-free silicon oxynitride. Capping layer  28  can protect a surface of layer  26  from particles and contaminants that could otherwise fall on layer  26 . If the processing of construction  10  occurs in an environment in which particle formation and/or incorporation of contaminants is unlikely (for example, an ultrahigh vacuum environment), layer  28  can be eliminated from the process. Layer  28  is utilized in the patterning of a metal (discussed below). If layer  28  is eliminated from the process, other methods besides those discussed specifically herein can be utilized for patterning the metal. 
   Referring to  FIG. 5 , openings  30  are extended through capping layer  28  and to an upper surface of semiconductive material  26 . Openings  30  can be formed by, for example, photolithographic processing to pattern a layer of photoresist (not shown) into a mask, followed by a suitable etch of layer  28  and subsequent removal of the photoresist mask. 
   A layer  32  of metal-containing material is provided within openings  30 , and in physical contact with an upper surface of semiconductive material  26 . Layer  32  can have a thickness of, for example, less than or equal to about 10 nanometers. The material of layer  32  can comprise, consist essentially of, or consist of, for example, nickel. Layer  32  can be formed by, for example, physical vapor deposition. Layer  32  can be formed to be within openings  30  and not over material  28  (as is illustrated in  FIG. 5 ) by utilizing deposition conditions which selectively form metal-containing layer  32  on a surface of material  26  relative to a surface of material  28 . Alternatively, material  32  can be deposited by a substantially non-selective process to form the material  32  over the surface of material  28  as well as over the surface of material  26  within openings  30 , and subsequently material  32  can be selectively removed from over surfaces of material  28  while remaining within openings  30 . Such selective removal can be accomplished by, for example, chemical-mechanical polishing, and/or by forming a photoresist mask (not shown) over the material  32  within openings  30 , while leaving other portions of material  32  exposed, and subsequently removing such other portions to leave only the segments of material  32  within openings  30 . The photoresist mask can then be removed. 
   Oxygen  34  is ion implanted through layers  26  and  28 , and into layer  16  to oxidize the material of layer  16 . For instance, if layer  16  consists of silicon, the oxygen can convert the silicon to silicon dioxide. Such swells the material of layer  16 , and accordingly fills the nanovoids that had been formed earlier. The oxygen preferably only partially oxidizes layer  16 , with the oxidation being sufficient to fill all, or at least substantially all, of the nanovoids; but leaving at least some of the seed crystals within layer  16  that had been formed with the laser irradiation discussed previously. In some aspects, the oxidation can convert a lower portion of material  16  to silicon dioxide while leaving an upper portion of material  16  as non-oxidized silicon. 
   The oxygen ion: utilized as implant  34  can comprise, for example, oxygen (O 2 ) or ozone (O 3 ). The oxygen ion implant can occur before or after formation of openings  30  and provision of metal-containing layer  32 . 
   Construction  10  is exposed to continuous wave laser irradiation while being held at an appropriate temperature (which can be, for example, from about 300° C. to about 450° C.; or in particular applications can be greater than or equal to 550° C.) to cause transformation of at least some of layer  26  to a crystalline form. The exposure to the laser irradiation comprises exposing the material of construction  10  to laser-emitted electromagnetic radiation scanned along a shown axis  36 . Preferably, the axis  36  along which the laser irradiation is scanned is the same axis that was utilized for scanning of laser irradiation in the processing stage of  FIG. 3 . 
   The crystallization of material  26  (which can also be referred to as a recrystallization of the material) is induced utilizing metal-containing layer  32 , and accordingly corresponds to an application of MILC. The MILC transforms material  26  to a crystalline form and the seed layer provides the crystallographic orientation while undergoing partial oxidation. 
   The crystal orientation within crystallized layer  26  can originate from the crystals initially formed in islands  18 . Accordingly, crystal orientations formed within layer  26  can be controlled through control of the crystal orientations formed within the semiconductive material  16  of islands  18 . 
   The oxidation of part of material  16  which was described previously can occur simultaneously with the MILC arising from continuous wave laser irradiation. Partial oxidation of seed layer  16  facilitates: (1) Ge enrichment into Si—Ge layer  26  (which improves carrier mobility); (2) stress-relief of Si—Ge layer  26 ; and (3) enhancement of recrystallization of Si—Ge layer  26 . The crystallization of material  26  can be followed by an anneal of material  26  at a temperature of, for example, about 900° C. for a time of about 30 minutes, or by an appropriate rapid thermal anneal, to further ensure relaxed, defect-free crystallization of material  26 . 
     FIG. 6  shows construction  10  after the processing described above with reference to  FIG. 5 . Specifically, the voids that had been in material  16  are absent due to the oxidation of material  16 . Also, semiconductive material  26  has been transformed into a crystalline material (illustrated diagrammatically by the cross-hatching of material  26  in  FIG. 6 ). Crystalline material  26  can consist of a single large crystal, and accordingly can be monocrystalline. Alternatively, crystalline material  26  can be polycrystalline. If crystalline material  26  is polycrystalline, the crystals of the material will preferably be equal in size or larger than the blocks  18 . In particular aspects, each crystal of the polycrystalline material can be about as large as one of the shown islands  18 . Accordingly, the islands can be associated in a one-to-one correspondence with crystals of the polycrystalline material. 
   The shown metal layers  32  are effectively in a one-to-one relationship with islands  18 , and such one-to-one correspondence of crystals to islands can occur during the MILC. Specifically, single crystals can be generated relative to each of islands  18  during the MILC process described with reference to  FIG. 5 . It is also noted, however, that although the metal layers  32  are shown in a one-to-one relationship with the islands in the cross-sectional views of  FIGS. 5 and 6 , the construction  10  comprising the shown fragment should be understood to extend three dimensionally. Accordingly, the islands  18  and metal layers  32  can extend in directions corresponding to locations into and out of the page relative to the shown cross-sectional view. There can be regions of the construction which are not shown where a metal layer overlaps with additional islands besides the shown islands. 
   Referring to  FIG. 7 , layers  28  and  32  ( FIG. 6 ) are removed, and subsequently a layer  40  of crystalline semiconductive material is formed over layer  26 . In typical applications, layer  26  will have a relaxed crystalline lattice and layer  40  will have a strained crystalline lattice. As discussed previously, layer  26  will typically comprise both silicon and germanium, with the germanium being present to a concentration of from about 10 atomic percent to about 60 atomic percent. Layer  40  can comprise, consist essentially of, or consist of either doped or undoped silicon; or alternatively can comprise, consist essentially of, or consist of either doped or undoped silicon/germanium. If layer  40  comprises silicon/germanium, the germanium content can be from about 10 atomic percent to about 60 atomic percent. 
   Strained lattice layer  40  can be formed by utilizing methods similar to those described in, for example, Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57–58; and Cheng, Z. et al., “SiGe-On-Insulator (SGOI) Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” 2001 IEEE SOI Conference Digest, October 2001, pp. 13–14. 
   Strained lattice layer  40  can be large polycrystalline or monocrystalline. If strained lattice layer  40  is polycrystalline, the crystals of layer  40  can be large and in a one-to-one relationship with the large crystals of a polycrystalline relaxed crystalline layer  26 . Strained lattice layer  40  is preferably monocrystalline over the individual blocks  18 . 
   The strained crystalline lattice of layer  40  can improve mobility of carriers relative to the material  26  having a relaxed crystalline lattice. However, it is to be understood that layer  40  is optional in various aspects of the invention. 
   Each of islands  18  can be considered to be associated with a separate active region  42 ,  44  and  46 . The active regions can be separated from one another by insulative material subsequently formed through layers  26  and  40  (not shown). For instance, a trenched isolation region can be formed through layers  26  and  40  by initially forming a trench extending through layers  26  and  40  to insulative material  14 , and subsequently filling the trench with an appropriate insulative material such as, for example, silicon dioxide. 
   As discussed previously, crystalline material  26  can be a single crystal extending across an entirety of the construction  10  comprising the shown fragment, and accordingly extending across all of the shown active regions. Alternatively, crystalline material  26  can be polycrystalline. If crystalline material  26  is polycrystalline, the single crystals of the polycrystalline material will preferably be large enough so that only one single crystal extends across a given active region. In other words, active region  42  will preferably comprise a single crystal of material  26 , active region  44  will comprise a single crystal of the material, and active region  46  will comprise a single crystal of the material, with the single crystals being separate and discrete relative to one another. 
     FIG. 8  shows an expanded view of active region  44  at a processing stage subsequent to that of  FIG. 7 , and specifically shows a transistor device  50  associated with active region  44  and supported by crystalline material  26 . 
   Transistor device  50  comprises a dielectric material  52  formed over strained lattice  40 , and a gate  54  formed over dielectric material  52 . Dielectric material  52  typically comprises silicon dioxide, and gate  54  typically comprises a stack including an appropriate conductive material, such as, for example, conductively-doped silicon and/or metal. 
   A channel region  56  is beneath gate  54 , and in the shown construction extends across strained crystalline lattice material  40 . The channel region may also extend into relaxed crystalline lattice material  26  (as shown). Channel region  56  is doped with a p-type dopant. 
   Transistor construction  50  additionally comprises source/drain regions  58  which are separated from one another by channel region  56 , and which are doped with n-type dopant to an n +  concentration (typically, a concentration of at least 10 21  atoms/cm 3 ). In the shown construction, source/drain regions  58  extend across strained lattice layer  40  and into relaxed lattice material  26 . Although source/drain regions  58  are shown extending only partially through relaxed lattice layer  26 , it is to be understood that the invention encompasses other embodiments (not shown) in which the source/drain regions extend all the way through relaxed material  26  and to material  16 . 
   Channel region  56  and source/drain regions  58  can be formed by implanting the appropriate dopants into crystalline materials  26  and  40 . The dopants can be activated by rapid thermal activation (RTA), which can aid in keeping the thermal budget low for fabrication of field effect transistor  50 . 
   An active region of transistor device  50  extends across source/drain regions  58  and channel region  56 . Preferably the portion of the active region within crystalline material  26  is associated with only one single crystal of material  26 . Such can be accomplished by having material  26  be entirely monocrystalline. Alternatively, material  26  can be polycrystalline and comprise an individual single grain which accommodates the entire portion of the active region that is within material  26 . The portion of strained lattice material  40  that is encompassed by the active region is preferably a single crystal, and can, in particular aspects, be considered an extension of the single crystal of the relaxed lattice material  26  of the active region. 
   Crystalline materials  40  and  26  can, together with any crystalline structures remaining in material  16 , have a total thickness of less than or equal to about 2000 Å. Accordingly the crystalline material can correspond to a thin film formed over an insulative material. The insulative material can be considered to be insulative layer  14  alone, or a combination of insulative layer  14  and oxidized portions of material  16 . 
   The transistor structure  50  of  FIG. 8  corresponds to an n-type field effect transistor (NFET), and in such construction it can be advantageous to have strained crystalline material  40  consist of a strained silicon material having appropriate dopants therein. The strained silicon material can improve mobility of electrons through channel region  56 , which can improve performance of the NFET device relative to a device lacking the strained silicon lattice. Although it can be preferred that strained lattice material  40  comprise silicon in an NFET device, it is to be understood that the strained lattice can also comprise other semiconductive materials. A strained silicon lattice can be formed by various methods. For instance, strained silicon could be developed by various means and lattice  40  could be created by lattice mismatch with other materials or by geometric conformal lattice straining on another substrate (mechanical stress). 
   As mentioned above, strained lattice  40  can comprise other materials alternatively to, or additionally to, silicon. The strained lattice can, for example, comprise a combination of silicon and germanium. There can be advantages to utilizing the strained crystalline lattice comprising silicon and germanium relative to structures lacking any strained lattice. However, it is generally most preferable if the strained lattice consists of silicon alone (or doped silicon), rather than a combination of silicon and germanium for an NFET device. 
   A pair of sidewall spacers  60  are shown formed along sidewalls of gate  54 , and an insulative mass  62  is shown extending over gate  54  and material  40 . Conductive interconnects  63  and  64  extend through the insulative mass  62  to electrically connect with source/drain regions  58 . Interconnects  63  and  64  can be utilized for electrically connecting transistor construction  50  with other circuitry external to transistor construction  50 . Such other circuitry can include, for example, a bitline and a capacitor in applications in which construction  50  is incorporated into dynamic random access memory (DRAM). 
     FIG. 9  shows construction  10  at a processing stage subsequent to that of  FIG. 8 , and shows a capacitor structure  100  formed over and in electrical contact with conductive interconnect  64 . The shown capacitor structure extends across gate  54  and interconnect  63 . 
   Capacitor construction  100  comprises a first capacitor electrode  102 , a second capacitor electrode  104 , and a dielectric material  106  between capacitor electrodes  102  and  104 . Capacitor electrodes  102  and  104  can comprise any appropriate conductive material, including, for example, conductively-doped silicon. In particular aspects, electrodes  102  and  104  will each comprise n-type doped silicon, such as, for example, polycrystalline silicon doped to a concentration of at least about 10 21  atoms/cm 3  with n-type dopant. In a particular aspect of the invention, electrode  102 , conductive interconnect  64  and the source/drain region  58  electrically connected with interconnect  64  comprise, or consist of, n-type doped semiconductive material. Accordingly, n-type doped semiconductive material extends from the source/drain region, through the interconnect, and through the capacitor electrode. 
   Dielectric material  106  can comprise any suitable material, or combination of materials. Exemplary materials suitable for dielectric  106  are high dielectric constant materials including, for example, silicon nitride, aluminum oxide, TiO 2 , Ta 2 O 5 , ZrO 2 , etc. 
   The conductive interconnect  63  is in electrical connection with a bitline  108 . Top capacitor electrode  104  is shown in electrical connection with an interconnect  110 , which in turn connects with a reference voltage  112 , which can, in particular aspects, be ground. The construction of  FIG. 9  can be considered a DRAM cell, and such can be incorporated into a computer system as a memory device. 
     FIG. 10  shows construction  10  at a processing stage subsequent to that of  FIG. 7  and alternative to that described previously with reference to  FIG. 8 . In referring to  FIG. 10 , similar numbering will be used as is used above in describing  FIG. 8 , where appropriate. 
   A transistor construction  70  is shown in  FIG. 10 , and such construction differs from the construction  50  described above with reference to  FIG. 8  in that construction  70  is a p-type field effect transistor (PFET) rather than the NFET of  FIG. 8 . Transistor device  70  comprises an n-type doped channel region  72  and p + -doped source/drain regions  74 . In other words, the channel region and source/drain regions of transistor device  70  are oppositely doped relative to the channel region and source/drain regions described above with reference to the NFET device  50  of  FIG. 8 . 
   The strained crystalline lattice material  40  of the PFET device  70  can consist of appropriately doped silicon, or consist of appropriately doped silicon/germanium. It can be most advantageous if the strained crystalline lattice material  40  comprises appropriately doped silicon/germanium in a PFET construction, in that silicon/germanium can be a more effective carrier of holes with higher mobility than is silicon without germanium. 
   The transistor devices discussed above (NFET device  50  of  FIG. 8 , and PFET device  70  of  FIG. 10 ) can be utilized in numerous constructions in addition to the construction described above with reference to  FIG. 9 . Another exemplary construction is described with reference to  FIGS. 11 and 12 . 
     FIGS. 11 and 12  show a semiconductor construction  100  comprising a substrate  102  having an insulative layer  104  formed thereover. Substrate  102  and insulative layer  104  can comprise, for example, the materials described previously with reference to substrate  12  and insulator layer  14 , respectively. Accordingly, substrate  102  can comprise, for example, one or more of glass, aluminum oxide, silicon dioxide, metal, semiconductor material and plastic. Layer  104  can comprise any suitable electrically insulative material, including, for example, silicon dioxide. Layer  104  can be formed physically against substrate  102 , or can be separated from substrate  102  by one or more intervening materials, including, for example, a chemically passive thermally stable material, such as silicon nitride. 
   A first crystalline layer  106 , second crystalline layer  108 , and third crystalline layer  110  are formed over insulative material  104 . Layers  106 ,  108  and  110  can correspond to a silicon seed layer, relaxed crystalline lattice layer, and strained crystalline lattice layer, respectively. In particular aspects, layers  106 ,  108  and  110  can comprise materials described previously for layers  16 ,  26  and  40 , respectively, of  FIGS. 2–7 . Accordingly, layer  108  can comprise relaxed silicon/germanium; with the germanium being present to from about 10 atomic % to about 60 atomic %. Layer  110  can comprise, consist essentially of, or consist of doped strained silicon; or alternatively can comprise, consist essentially of, or consist of doped strained or unstrained silicon/germanium. Layer  106  can comprise, consist essentially of, or consist of doped silicon. 
   A dielectric material  112  is over layer  110 , and a transistor gate  114  is over dielectric material  112 . Dielectric material  112  can comprise, consist essentially of, or consist of silicon dioxide. Transistor gate  114  can comprise, for example, one or more of metal and conductively-doped silicon; and can, for example, comprise materials described previously with reference to transistor gate  54  of  FIGS. 8–10 . 
   A pair of source/drain regions  116  extend through strained crystalline lattice layer  110  and into relaxed crystalline lattice layer  108 . The source/drain regions comprise a shallow portion  118 , and a deeper portion  120 . Such shape of the source/drain regions can be accomplished utilizing a first shallow implant, followed by formation of sidewall spacers (not shown) along sidewalls of gate  114 , and a subsequent deep implant of n-type material. The sidewall spacers can then be removed to leave the resulting structure shown in  FIG. 11 . Alternatively, the sidewall spacers can be left in place to form a structure similar to that of  FIG. 8  (with the sidewall spacers of  FIG. 8  being labeled as  60 ). 
   A channel region  122  extends beneath gate  114 , and between source/drain regions  116 . An NFET transistor device comprises gate  114 , source/drain regions  116  and channel region  122 . Although the shown transistor device is an NFET device, it is to be understood that the invention encompasses other aspects (not shown) in which the transistor device is a PFET device. 
   Source/drain regions  116  and channel region  122  define an active region of the transistor device. For reasons described previously, it can be advantageous to have the entirety of the portion of the active region within layer  108  contained within a single crystal of the crystalline material of layer  108 ; and it can also be advantageous to have the entirety of the portion of the active region within layer  110  contained within a single crystal of the material  110 . Also, although the source/drain regions are shown terminating above layer  106 , it is to be understood that the invention encompasses other aspects (not shown) in which the source/drain regions extend into layer  106 . In such aspects, it can be advantageous if the entirety of the portion of the active region within layer  106  is contained within a single crystal of material  106 . 
   The crystalline materials of layers  106 ,  108  and  110  can be monocrystalline in order that an entirety of the active region within such crystalline materials is within single crystals of the materials. Alternatively, the materials can be polycrystalline, with individual single crystals being large enough to accommodate an entirety of the portion of the active region extending within the various materials. In particular aspects, layers  108  and  110  will be extensions of a crystalline lattice defined by material  106 . In such aspects, an entirety of the active region of the transistor device will preferably extend within only a single crystal encompassing materials  106 ,  108  and  110 . 
   A conductive pillar  130  is formed in electrical connection with one of the source/drain regions  116 . In the shown embodiment, pillar  130  comprises n-type doped silicon, and is formed in physical contact with an upper surface of layer  110 . The material of pillar  130  can be formed by, for example, selective epitaxial growth of semiconductive material over layer  110 . The material of pillar  130  can subsequently be doped by out-diffusion of dopant from source/drain region  116  into the semiconductive material of pillar  130 , or alternatively by ion implantation. 
   A pair of crystalline materials  132  and  134  are formed over pillar  130 . In alternative embodiments, layers  132  and  134  can be replaced with a single layer (not shown). In aspects in which pillar  130  comprises a crystalline semiconductive material, layers  132  and  134  can be formed by epitaxial growth over the semiconductive material of pillar  130 , and/or by one or more techniques discussed previously with reference to  FIGS. 5–7 . In the shown aspect of the invention, pillar  130  comprises an upper surface  131 , and layer  132  is formed physically against such upper surface. 
   An electrical node  136  is formed at a location distant from conductive pillar  130 , and crystalline materials  132  and  134  extend between node  136  and pillar  130 . Crystalline materials  132  and  134  together define a resistor  135  extending between a first electrical node defined by pillar  130 , and a second electrical node defined by the shown node  136 . Node  136  can comprise any suitable conductive material, including, a suitably doped semiconductive material. In the shown embodiment, node  136  comprises n-type doped semiconductive material. Such semiconductive material can be, for example, silicon, and can be in a monocrystalline, polycrystalline, or amorphous form. 
   Crystalline materials  132  and  134  may or may not comprise different compositions from one another. Crystalline material  132  can comprise, consist essentially of, or consist of p-type doped silicon; and crystalline material  134  can comprise, consist essentially of, or consist of p-type doped silicon/germanium. Alternatively, the two layers can be replaced with a single layer of either p-doped silicon or p-doped silicon/germanium. 
   If crystalline material  134  comprises p-type doped silicon/germanium, the germanium content can be, for example, from about 10 atomic % to about 60 atomic %. Crystalline materials  132  and  134  can be polycrystalline, or monocrystalline. In particular aspects, crystalline material  132  can be considered to be a silicon seed layer, and crystalline material  134  can be considered to be a second crystalline layer epitaxially grown over the silicon seed layer. In particular aspects, crystalline material  130  can be considered to be a silicon seed layer and  132 / 134  can be replaced with a second crystalline layer. 
   Crystalline materials  132  and  134  are oppositely doped relative to source/drain regions  116 , and electrical nodes  130  and  136 ; and in the shown embodiment are doped with p-type dopant. Such doping of materials  132  and  134  can be accomplished by, for example, one or more suitable implants. Crystalline materials  132  and  134  can be doped simultaneously, or sequentially. In a particular aspect, crystalline material  132  is doped prior to formation of material  134 ; and crystalline material  134  is subsequently doped by out-diffusion from material  132 . 
   Resistor  135  is electrically connected with one of the source/drain regions  116  through conductive pillar  130 . In the shown embodiment, one of the crystalline layers  132  and  134  physically contacts conductive pillar  130 . It is to be understood, however, that the invention encompasses other aspects (not shown) in which an intervening conductive material is provided between crystalline materials  132  and  134  and conductive pillar  130 , as well as other aspects (not shown) in which both of crystalline materials  132  and  134  physically contact conductive pillar  130 . Also, it is to be understood that even though only two crystalline layers are shown within the illustrated resistor  135 , the invention encompasses other aspects (not shown) wherein more than two crystalline layers are incorporated into a resistor construction. 
   Both of crystalline materials  132  and  134  of resistor  135  contact electrical node  136 . It is to be understood, however, the invention encompasses other aspects (not shown) in which only one of crystalline materials  132  and  134  contacts electrical node  136 . 
   An insulative material (or mass)  140  is over gate  114 , and resistor  135  is separated from gate  114  by the insulative material. In the shown embodiment, resistor  135  extends across gate  114 , and accordingly a portion of resistor  135  is directly over gate  114 . In the shown aspect of the invention, both of crystalline layers  132  and  134  physically contact insulative mass  140 ; the mass being against an upper surface of material  134  and against a lower surface of material  132 . 
   Construction  100  includes a contact  166  extending from a source/drain region  116 , through an opening in resistor  135  (the opening has a periphery  142 ), and to an interconnect  152  which electrically connects with ground (not shown). Construction  100  also includes a contact  164  (shown in phantom view in  FIG. 11  as it is behind the cross-section of  FIG. 11 ). Contact  164  extends to node  136 . An interconnect  150  (shown in phantom view in the cross-section of  FIG. 11 ) extends between contact  164  and V DD  (not shown in  FIG. 11 ). In particular aspects, node  136  can be considered to be part of the electrical connection to V DD . 
     FIG. 12  illustrates a top view of construction  100 , with insulative mass  140  not being shown in  FIG. 12  to aid in clarity of the illustration. Gate  114  is part of a conductive line  160 , which is connected thorough an electrical stud  162  to other circuitry. 
   Resistor  135  is shown comprising a “L” shape having an opening extending therethrough for passage of contact  166 . Resistor  135  is shown to comprise an outer surface  144 , and an inner surface  142 . The inner surface  142  defines a periphery of the opening around the contact  166 . 
     FIG. 11  shows various different dopant levels, and utilizes the designations p+, p, p−, n−, n and n+ to distinguish the levels. The difference in dopant concentration between the regions identified as being p+, p, and p− are typically as follows. A p+ region has a dopant concentration of at least about 10 20  atoms/cm 3 , a p region has a dopant concentration of from about 10 14  to about 10 18  atoms/cm 3 , and a p− region has a dopant concentration in the order of or less than 10 16  atoms/cm 3 . It is noted that regions identified as being n−, n and n+ will have dopant concentrations similar to those described above relative to the p−, p and p+ regions respectively, except, of course, the n regions will have an opposite-type conductivity enhancing dopant therein than do the p regions. 
   The p+, p, and p− dopant levels are shown in the drawing only to illustrate differences in dopant concentration. It is noted that the term “p” is utilized herein to refer to both a dopant type and a relative dopant concentration. To aid in interpretation of this specification and the claims that follow, the term “p” is to be understood as referring only to dopant type, and not to a relative dopant concentration, except when it is explicitly stated that the term “p” refers to a relative dopant concentration. Accordingly, for purposes of interpreting this disclosure and the claims that follow, it is to be understood that the term “p-type doped” refers to a dopant type of a region and not a relative dopant level. Thus, a p-type doped region can be doped to any of the p+, p, and p− dopant levels discussed above. Similarly, an n-type doped region can be doped to any of the n+, n, and n− dopant levels discussed above. 
     FIG. 13  illustrates generally, by way of example, but not by way of limitation, an embodiment of a computer system  400  according to an aspect of the present invention. Computer system  400  includes a monitor  401  or other communication output device, a keyboard  402  or other communication input device, and a motherboard  404 . Motherboard  404  can carry a microprocessor  406  or other data processing unit, and at least one memory device  408 . Memory device  408  can comprise various aspects of the invention described above, including, for example, the DRAM unit cell described with reference to  FIG. 8 . Memory device  408  can comprise an array of memory cells, and such array can be coupled with addressing circuitry for accessing individual memory cells in the array. Further, the memory cell array can be coupled to a read circuit for reading data from the memory cells. The addressing and read circuitry can be utilized for conveying information between memory device  408  and processor  406 . Such is illustrated in the block diagram of the motherboard  404  shown in  FIG. 14 . In such block diagram, the addressing circuitry is illustrated as  410  and the read circuitry is illustrated as  412 . 
   In particular aspects of the invention, memory device  408  can correspond to a memory module. For example, single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs) may be used in the implementation which utilize the teachings of the present invention. The memory device can be incorporated into any of a variety of designs which provide different methods of reading from and writing to memory cells of the device. One such method is the page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell arrays and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. 
   An alternate type of device is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on a memory bus. Other alternative types of devices include SDRAM, DDR SDRAM, SLDRAM, VRAM and Direct RDRAM, as well as others such as SRAM or Flash memories. 
   Transistor/resistor constructions of, for example, the type described with reference to  FIGS. 11 and 12 , can be incorporated into the computer system  400 . For instance, a circuit within the computer system can be provided at V DD  potential and another circuit can be provided at ground potential. A source/drain region of the transistor can be electrically connected to the circuit at ground potential, and the other source/drain region can be electrically coupled to the resistor which in turn is electrically coupled to V DD  potential. 
   In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.