Patent Publication Number: US-2012033336-A1

Title: Debug interface circuit and electronic device using the same

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to electronic devices, and particularly to an electronic device using a debug interface circuit for preventing the electronic device from being damaged by electrostatic discharge (ESD). 
     2. Description of Related Art 
     Integrated circuits (IC) are widely used in different electronic devices for processing data or power management. The IC is tested after being installed on the electronic device by a debug device. The debug device electrically connects to the IC by a debug interface circuit of the electronic device. Usually, the debug interface circuit is a recommend standard 232 (RS-232) connector. The RS-232 connector includes some exposed conductive pins for connecting with the debug device. However, the exposed conductive pins can be accidentally touched by users, and static electricity accumulated on the user may discharge to the pins and damage the IC. Thus, the IC is easy to be damaged from electrostatic discharge (ESD) through the RS-232 connector. 
     Therefore, there is room for improvement in the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The components of the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiment of an electronic device with a debug interface circuit. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the views. 
         FIG. 1  is a schematic view of an electronic device including a debug interface circuit according to an exemplary embodiment. 
         FIG. 2  is a schematic view of an electronic device including a debug interface circuit according to another exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present disclosure will now be described in detail with reference to the drawings. 
     Referring to  FIG. 1 , an electronic device  100  according to an exemplary embodiment is illustrated. In this embodiment, the electronic device  100  is a DVD player. The electronic device  100  includes an integrated circuit (IC)  12  and a debug interface circuit  10  electrically connected to the IC  12 . The debug interface circuit  10  is used for electrically connecting the IC  12  to a debug device  200 . The debug device  200  is a computer used for debugging the IC  12 . 
     The IC  12  includes a first pin  122  for inputting external signals, and a second pin  124  for outputting internal signals. 
     The debug interface circuit  10  includes a connector  11 , a first electrostatic protection unit  14 , and a second electrostatic protection unit  16 . 
     In this embodiment, the connector  11  is a recommended standard 232 (RS-232) connector. The RS-232 is exposed out side of the electronic device  100  and is capable of electrically connecting to the debug device  200 . The RS-232 connector includes an output port  112 , an input port  114 , a power port Vcc for electrically connecting to a power Vcc of the electronic device  100 , and a ground port GND for being electrically grounded. The output port  112  is electrically connected to the first pin  122 , for outputting signals to the first pin  122 . The input port  114  is electrically connected to the second pin  124 , for inputting signals from the second pin  124 . 
     One end of the first electrostatic protection unit  14  is electrically connected to the first pin  122 , and the other end of the first electrostatic protection unit  14  is electrically grounded. The first electrostatic protection unit  14  is used for clamping a voltage of the first pin  122  at a predetermined value. The predetermined value is set lower than a threshold above which the IC  12  may be damaged. One end of the second electrostatic protection unit  16  is electrically connected to the second pin  124 , and the other end of the second electrostatic protection unit  16  is electrically grounded. The second electrostatic protection unit  16  is used for clamping a voltage of the second pin  124  at the predetermined value. Thus, the IC  12  is protected from the damage caused by ESD to the connector  11 . 
     Generally, during an ESD event, high voltage, such as 10 KV, is generated momentarily. When the debug device  200  turns on and electrically connects to the connector  11 , the first electrostatic protection unit  14  and the second electrostatic protection unit  16  respectively clamp the voltages of the first pin  122  and the second pin  124  at the predetermined value. In this embodiment, the first electrostatic protection unit  14  is a first voltage dependent resistor, and the second electrostatic protection unit  16  is a second voltage dependent resistor. When current through the first pin  122  and the second pin  124  are too great, the resistances of the first voltage dependent resistor and the second voltage dependent resistor become low to guide part of the current to ground. When current through the first pin  122  and the second pin  124  are safe, the resistances of the first voltage dependent resistor and the second voltage dependent resistor become high blocking the path to ground. 
     As discussed above, when the electronic device  100  is electrically connected to the debug device  200  for debugging the IC  12 , the IC  12  is protected from ESD damage. 
     Referring to  FIG. 2 , an electronic device  300  according to another exemplary embodiment is illustrated. The difference between the electronic device  100  and the electronic device  300  is that the electronic device  300  further includes a first current limiting unit  24  and a second current limiting unit  26 . 
     The first current limiting unit  24  is electrically connected between the first pin  122  of the IC  12  and the output port  112  of the connector  11 . The second current limiting unit  26  is electrically connected between the second pin  124  of the IC  12  and the input port  114  of the connector  11 . The first current limiting unit  24  limits an ESD current to a safe value, the ESD occurring on the output port  112  of the connector  11 . The second current limiting unit  26  is used for limiting an ESD current to a safe value, which the ESD occurred on the input port  114  of the connector  11 . In this embodiment, the first current limiting unit  24  is a first resistor, the second current limiting unit  26  is a second resistor. 
     The electronic device  300  has the same advantages as the electronic device  100 , but further has double electrostatic protections on the IC  12 . 
     While various exemplary and preferred embodiments have been described, it is to be understood that the disclosure is not limited thereto. To the contrary, various modifications and similar arrangements (as would be apparent to those skilled in the art) are intended to also be covered. Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.