Patent Publication Number: US-2023143049-A1

Title: Substrate processing apparatus and method of manufacturing semiconductor device using the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0153865 filed on Nov. 10, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     Aspects of the present inventive concept relate to a substrate processing apparatus and a method of manufacturing a semiconductor device using the same. 
     A deposition process or an etching process, among semiconductor processes for manufacturing a semiconductor device, have been performed with a substrate processing apparatus using plasma. With the trend for a large diameter of a semiconductor wafer and high integration of a semiconductor device, a process difficulty of a deposition process and an etching process has increased. 
     SUMMARY 
     An aspect of the present inventive concept is to provide a substrate processing apparatus capable of performing a uniform plasma process on a substrate. 
     An aspect of the present inventive concept is also to provide a substrate processing apparatus capable of controlling a plasma sheath region. 
     An aspect of the present inventive concept is also to provide a method of manufacturing a semiconductor device using the substrate processing apparatus. 
     According to an aspect of the present inventive concept, a substrate processing apparatus is provided. The substrate processing apparatus includes a substrate support configured to support a substrate, the substrate support including lower region and an upper region, the lower region including a central region and an outer region surrounding the central region, and the upper region disposed on the central region of the lower region, a coupling ring assembly surrounding a side surface of the lower region of the substrate support, an edge ring disposed on the coupling ring assembly and the outer region of the lower region of the substrate support and surrounding a side surface of the upper region of the substrate support, and at least one upper contact pad contacting a lower surface of the edge ring and contacting an upper surface of the outer region of the lower regions of the substrate support and an upper surface of the coupling ring assembly, the at least one upper contact pad being conductive. The coupling ring assembly includes a coupling ring and a conductive side contact pad in contact with a side surface of the substrate support and an inner surface of the coupling ring. 
     According to another aspect of the present inventive concept, a substrate processing apparatus is provided. The substrate processing apparatus includes a lower electrode assembly, an upper electrode assembly disposed on the lower electrode assembly, and a plasma processing region between the lower electrode assembly and the upper electrode assembly. The lower electrode assembly includes a substrate support configured to support a substrate; a coupling ring assembly surrounding the substrate support, an edge ring on the coupling ring assembly, and at least one upper contact pad contacting a lower surface of the edge ring and contacting at least one of the substrate support and the coupling ring assembly, the at least one upper contact pad being conductive. The coupling ring assembly includes a coupling ring and a conductive side contact pad in contact with a side surface of the substrate support and an inner surface of the coupling ring. 
     According to another aspect of the present inventive concept, a method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes: preparing a substrate processing apparatus including a lower electrode assembly, an upper electrode assembly disposed on the lower electrode assembly; and a plasma processing region between the lower electrode assembly and the upper electrode assembly, wherein the lower electrode assembly of the substrate processing apparatus includes a substrate support supporting a substrate, a coupling ring assembly surrounding the substrate support, an edge ring on the coupling ring assembly, and at least one conductive upper contact pad contacting at least one of the substrate support and the coupling ring assembly, while contacting a lower surface of the edge ring, and the coupling ring assembly includes a conductive side contact pad contacting a side surface of the substrate support and the coupling ring assembly and contacting an inner surface of the coupling ring assembly; loading the substrate onto the substrate support in the substrate processing apparatus; generating plasma in the plasma processing region to form a plasma region; and performing plasma processing, while heat generated in the plasma processing region on the edge ring is dissipated through the edge ring, the at least one upper contact pad, the coupling ring assembly, the side contact pad, and the substrate support of the substrate processing apparatus. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The above and other aspects, features, and advantages of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: 
         FIG.  1    is a conceptual diagram of a substrate processing apparatus according to embodiments of the present inventive concept. 
         FIG.  2 A  is a partially enlarged cross-sectional view schematically illustrating a substrate processing apparatus according to an example embodiment of the present inventive concept. 
         FIG.  2 B  is an exploded perspective view schematically illustrating some components of a substrate processing apparatus according to an embodiment of the present inventive concept. 
         FIG.  3    is a graph illustrating a relationship between a sheath size and a partial thickness of a coupling ring in order to describe some components of a substrate processing apparatus according to an embodiment of the present inventive concept. 
         FIG.  4 A  is a partially enlarged cross-sectional view schematically illustrating a modified example of a substrate processing apparatus according to an example embodiment of the present inventive concept. 
         FIG.  4 B  is a partially enlarged cross-sectional view schematically illustrating a modified example of a substrate processing apparatus according to an embodiment of the present inventive concept. 
         FIG.  4 C  is a partially enlarged cross-sectional view schematically illustrating a modified example of a substrate processing apparatus according to an example embodiment of the present inventive concept. 
         FIG.  4 D  is an exploded perspective view schematically illustrating a modified example of a substrate processing apparatus according to an embodiment of the present inventive concept. 
         FIG.  5 A  is a partially enlarged cross-sectional view schematically illustrating a modified example of a substrate processing apparatus according to an example embodiment of the present inventive concept. 
         FIG.  5 B  is a partially enlarged cross-sectional view schematically illustrating a modified example of a substrate processing apparatus according to an embodiment of the present inventive concept. 
         FIG.  5 C  is a partially enlarged cross-sectional view schematically illustrating a modified example of a substrate processing apparatus according to an embodiment of the present inventive concept. 
         FIG.  6    is a flowchart schematically illustrating a method of manufacturing a semiconductor device using a substrate processing apparatus according to embodiments of the present inventive concept. 
         FIGS.  7 A,  7 B,  8 A,  8 B,  8 C, and  9    are schematic views illustrating a method of manufacturing a semiconductor device using a substrate processing apparatus according to embodiments of the present inventive concept. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, example embodiments of the present inventive concept will be described with reference to the accompanying drawings. 
     First, a substrate processing apparatus according to embodiments of the present inventive concept will be described with reference to  FIGS.  1 ,  2 A,  2 B and  3   .  FIG.  1    is a conceptual view of a substrate processing apparatus according to embodiments of the present inventive concept,  FIG.  2 A  is a schematic partial enlarged cross-sectional view of a portion indicated by ‘A’ of  FIG.  1   ,  FIG.  2 B  is an exploded perspective view schematically illustrating some components of a substrate processing apparatus according to an embodiment, and  FIG.  3    is a graph illustrating a relationship between a sheath size and a partial thickness of a coupling ring in order to describe some components of a substrate processing apparatus according to an embodiment of the present inventive concepts. 
     Referring to  FIGS.  1 ,  2 A,  2 B and  3   , a substrate processing apparatus  1  according to an embodiment may include a plasma processing chamber  5 , a lower electrode assembly  10  disposed in the plasma processing chamber  5 , an upper electrode assembly  50  disposed on the lower electrode assembly  10 , a plasma processing region PLR between the lower electrode assembly  10  and the upper electrode assembly  50 , and a plasma confinement ring  60  defining a side of the plasma processing region PLR. 
     The lower electrode assembly  10  may include a substrate support  13  supporting a substrate WF, a coupling ring assembly  16  surrounding the substrate support  13 , an edge ring on the coupling ring assembly  16  and at least one conductive upper contact pad  28  in contact with at least one of the substrate support  13  and the coupling ring assembly  16 . 
     The substrate support  13  may be an electrostatic chuck (ESC) fixing the substrate WF by electrostatic force. 
     The substrate support  13  may include a lower region  13   c  and  13   o  and an upper region  13   u . The lower region  13   c  and  13   o  may have a central region  13   c  and an outer region  13   o  surrounding the central region  13   c . The upper region  13   u  may be disposed on the central region  13   c  of the lower region  13   c  and  13   o.    
     The upper region  13   u  of the substrate support  13  may include an upper support  13   u   1  protruding from the central region  13   c  of the lower region  13   c  and  13   o , a protective layer  13   u   2  surrounding a side surface of the upper support  13   u   1 , and a capping layer  13   u   3  covering an upper surface of the upper support  13   u   1  and an upper surface of the protective layer  13   u   2  and contacting the substrate WF. The capping layer  13   u   3  that contacts the substrate WF may extend in a first horizontal direction (“first direction”) and a second horizontal direction (“second direction”) perpendicular to the first horizontal direction. 
     In the substrate support  13 , the lower region  13   c  and  13   o  and the upper support  13   u   1  may include or may be formed of a conductive material such as aluminum or an aluminum alloy, and the protective layer  13   u   2  may include or may be formed of a material such as a rubber material or ceramic, and the capping layer  13   u   3  may include or may be formed of a material such as ceramic (e.g., Al 2 O 3 , etc.). 
     The coupling ring assembly  16  may include a coupling ring  18  and conductive side contact pad  30 . The side contact pad  30  may be in contact with a side surface of the outer region  13   o  of the lower region  13   c  and  13   o  of the substrate support  13  and an inner surface of the coupling ring  18 . The coupling ring  18  may have a lower opening  180 . 
     The side contact pad  30  may have a first side surface contacting the inner surface of the coupling ring  18  and a second side surface facing the first side surface. In the side contact pad  30 , the entire first side surface may be in contact with the inner surface of the coupling ring  18 , and part (e.g., a first portion) of the second side surface may be in contact with the substrate support  13 , and the remainder (e.g., a second portion) may be spaced apart from the substrate support  13 . As such, since part of the second side surface of the side contact pad  30  is in contact with the substrate support  13  and the remainder thereof is spaced apart from the substrate support  13 , impedance may be lowered. 
     The coupling ring assembly  16  may further include an electrode expansion ring  20  disposed in the coupling ring  18  and partially overlapping the lower opening  18   o  in a vertical direction (“third direction”), the vertical direction being perpendicular to the first and second horizontal directions. The coupling ring assembly  16  may further include an electrode structure  22  inserted into the lower opening  18   o  and contacting the electrode expansion ring  20 . 
     The coupling ring  18  may have inner surfaces  18   s   1  and  18   s   2  facing the outer region  13   o  of the lower region  13   c  and  13   o  of the substrate support  13  and spaced apart from the substrate support  13 . 
     The inner surfaces  18   s   1  and  18   s   2  of the coupling ring  18  may have a first inner surface  18   s   1 , perpendicular to an upper surface of the coupling ring  18  and a second inner surface  18   s   2  in a region recessed relative to the first inner surface  18   s   1 . 
     The side contact pad  30  may be attached to the second inner surface  18   s   2  of the recessed region to fill the recessed region and protrude relative to the first inner surface  18   s   1  to contact the substrate support  13 . 
     In the inner surfaces  18   s   1  and  18   s   2  of the coupling ring  18 , the second inner surface  18   s   2  of the recessed region may be inclined with respect to an upper surface of the coupling ring  18 . In the inner surfaces  18   s   1  and  18   s   2  of the coupling ring  18 , the recessed region may be recessed to be deeper in a direction toward the lower surface of the coupling ring  18 . 
     The coupling ring  18  may be formed of a dielectric material, for example, a ceramic such as Al 2 O 3 . 
     The electrode expansion ring  20  may be formed of a conductive material such as platinum (Pt) or tungsten (W). 
     A thickness, in the third direction, of the electrode expansion ring  20  may be within a range of about 5 μm to about 15 μm. 
     The electrode structure  22  may include a column-shaped electrode pillar  22   a  formed of a metal material such as Cu, a first connection material layer  22   b , as a conductive layer, covering an upper surface and upper side surface of the electrode pillar  22   a , contacting the electrode expansion ring  20 , and electrically connecting the electrode pillar  22   a  and the electrode expansion ring  20 , and a second connection material layer  22   c  surrounding a portion of the electrode pillar  22   a  below the first connection material layer  22   b  and contacting a side wall of the lower opening  18   a  to fix the electrode pillar  22   a  to the coupling ring  18 . 
     The edge ring  25  may include a body region  25   a  having a first upper surface  25   s   1 , an inner region  25   b  having a second upper surface  25   s   2  positioned at a level lower than a level of the first upper surface  25   s   1 , and a buffer region  25   c  disposed between the body region  25   a  and the inner region  25   b  and having an inclined surface  25   s   3  extending from the first upper surface  25   s   1  to the second upper surface  25   s   2 . 
     The inner region  25   b  of the edge ring  25  may have a side surface facing a side surface of the upper region  13   u  of the substrate support  13  and have a thickness, in the third direction, less than a thickness, in the third direction, of the upper region  13   u  of the substrate support  13 . The body region  25   a  of the edge ring  25  may have a thickness, in the third direction, greater than the thickness, in the third direction, of the upper region  13   u  of the substrate support  13 . 
     A lower surface of the edge ring  25  may be substantially flat (e.g., substantially planar). Terms such as “same,” “equal,” “flat,” “planar,” or “coplanar,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. 
     In the edge ring  25 , the first upper surface  25   s   1  may be disposed at a level higher than that of the second upper surface  25   s   2 , and the second upper surface  25   s   2  may be disposed at a level lower than that of the substrate WF supported by the upper region  13   u  of the substrate support  13 . 
     In the edge ring  25 , the body region  25   a  may cover the entire upper surface of the coupling ring  18  and cover a portion of the upper surface of the outer region  13   o  of the lower region  13   c  and  13   o  of the substrate support  13 . In the edge ring  25 , at least a portion of the inner region  25   b  may overlap, in the vertical direction, an edge region of the substrate WF supported by the substrate support  13 . 
     The at least one upper contact pad  28  may include a first upper contact pad  28   a  and a second upper contact pad  28   b  spaced apart from each other. The first upper contact pad  28   a  may contact a lower surface of the edge ring  25  and an upper surface of the outer region  13   o  of the lower region  13   c  and  13   o . The second upper contact pad  28   b  may contact a lower surface of the edge ring  25  and an upper surface of the coupling ring  18  of the coupling ring assembly  16 . 
     A width, in the first direction, of the second upper contact pad  28   b  may be less than a width, in the first direction, of the coupling ring  18 . 
     The lower electrode assembly  10  may include a buffer structure  35  surrounding an outer surface of the coupling ring assembly  16  and the edge ring  25  and a support structure  38  surrounding an outer surface of the buffer structure  35  and supporting the plasma confinement ring  60 . The buffer structure  35  may be formed of a material such as quartz or ceramic. 
     The upper electrode assembly  50  may include an upper electrode  56  and first and second portions  52  and  54  defining an upper surface of the plasma processing region PLR below the upper electrode  56 . The first and second portions  52  and  54  may include a first portion  52  facing the substrate WF supported by the substrate support  13  and a second portion  54  surrounding the first portion  52 . The upper electrode  56  may be formed of a conductive material such as aluminum or an aluminum alloy. The first and second portions  52  and  54  may be formed of a material such as silicon (Si) or silicon carbide (SiC). A lower surface of the first portion  52  may form a curved surface so that a uniform plasma process may be performed. For example, the first portion  52  may be downwardly convex in a central region and may be convex in an edge region. The first portion  52  may further protrude downwardly, relative to the edge region of the central region to be convex. 
     The upper electrode assembly  50  may have shower holes  58  for injecting a process gas into the plasma processing region PLR. 
     The plasma confinement ring  60  may contact the upper electrode assembly  50  and the lower electrode assembly  10 . 
     The substrate processing apparatus  1  according to an embodiment may further include an RF power controller  120  providing a plurality of RF power currents to the lower electrode assembly  10 , a temperature controller  130  controlling a temperature of the substrate support  13 , and an exhaust unit  160  adjusting internal pressure of the processing chamber  5  or discharging process gas in the processing chamber  5 . 
     The RF power controller  120  may further include a first RF power generating device  122  electrically connected to the substrate support  13  and used to generate plasma in the plasma processing region PL, a second RF power generating device  124  electrically connected to the substrate support  13  and accelerating radicals or ions from plasma positioned in a central region of the substrate WF supported by the substrate support  13  onto the substrate WF, and a third RF power generating device  126  electrically connected to the electrode pillar  22   a  of the electrode structure  22  of the coupling ring assembly  16  and accelerating radicals or ions from plasma positioned on an edge region WFe of the substrate WF supported by the substrate support  13  onto the edge region WFe, while controlling a thickness, in the third direction, of a sheath of the plasma positioned on the edge region WFe of the substrate WF supported by the substrate support  13 . 
     The substrate processing apparatus  1  according to an embodiment may further include an upper electrode controller  140  controlling temperature of the upper electrode assembly  50 , a process gas supply unit  150  supplying a process gas into the plasma processing region PLR through shower holes  58  of the upper electrode assembly  50 , and a grounding device  142  grounding the upper electrode controller  140 . 
     The substrate processing apparatus  1  according to an embodiment may further include a system controller  110  automatically performing a plasma process, while controlling the RF power controller  120 , the temperature controller  130 , the exhaust unit  160 , the upper electrode controller  140 , and the process gas supply unit  150  overall. 
     In an example, the plasma process may be a plasma etching process performed on the substrate WF supported by the substrate support  13 . 
     The side contact pad  30  and the at least one upper contact pad  28  may include or may be formed of the same material. 
     The side contact pad  30  and the at least one upper contact pad  28  may include or may be formed of silicone having conductive fillers  32 . The conductive fillers  32  may be carbon nanotubes. 
     At least one of the side contact pad  30  and the at least one upper contact pad  28  may have a resistivity of about 10 −3  Ω-m to about 10 4  Ω-m. 
     In the side contact pad  30  and the at least one upper contact pad  28 , a magnitude of the resistivity may be determined by the amount of the conductive fillers  32 . 
     In an example, the side contact pad  30  and the at least one upper contact pad  28  may have the same resistivity. 
     In another example, the side contact pad  30  and the at least one upper contact pad  28  may have different resistivities. 
     At least one of a thickness, in the first direction, of the side contact pad  30  and a thickness, in third direction, of the at least one upper contact pad  28  may be within a range of about 0.2 mm to about 1 mm. For example, the thickness, in the first direction, of the side contact pad  30  may be within a range of about 0.2 mm to about 1 mm, and the thickness, in the third direction, of at least one of the at least one upper contact pad  28  may be within a range of about 0.2 mm to about 1 mm. 
     A minimum distance L between the electrode expansion ring  20  and the inner surfaces  18   s   1  and  18   s   2  of the coupling ring  18  may be within a range of about 1 mm to about 5 mm. 
     A distance D between the upper surface of the coupling ring  18  and the electrode expansion ring  20  may be determined by Equation 1 below. 
     
       
         
           
             
               
                 
                   
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     In Equation 1 above, the variables are representative of the following: 
     d sh : sheath thickness 
     k B : Boltzmann constant 
     n e : electron density 
     e: basic charge amount 
     T e : electron temperature 
     V sh : sheath voltage 
     ∈ 0 : dielectric constant of dielectric of coupling ring. 
     Here, the electron density n e  may be a plasma density, the basic charge amount e may be a charge amount of one electron, and the electron temperature T e  may be an average kinetic energy in plasma. 
     In the graph of  FIG.  3   , D break  may be a thickness at which breakdown of plasma sheath region occurs, D min  may represent a minimum thickness capable of stably controlling a plasma sheath while maintaining breakdown, and D max  may represent a maximum thickness at which plasma sheath may be stably controlled. 
     In an example, the thickness D break  at which breakdown occurs may be about 0.2 mm, the minimum thickness D min  may be about 0.5 mm, and the maximum thickness D max  may be about 1.3 mm. 
     In an example, a distance D between the upper surface of the coupling ring  18  and the electrode expansion ring  20  may be within a range of about 0.5 mm to about 1.3 mm. The distance D may be the thickness of the graph of  FIG.  3   . As shown in the graph of  FIG.  3   , when the distance D between the upper surface of the coupling ring  18  and the electrode expansion ring  20  is within the range of about 0.5 mm to about 1.3 mm, a change in size of the sheath may be significant. Accordingly, when the distance D between the upper surface of the coupling ring  18  and the electrode expansion ring  20  is within the range of about 0.5 mm to about 1.3 mm, a transmission rate of power transmitted from the third RF power generating device  136  to the edge ring  25  may be improved. Accordingly, when the distance D between the upper surface of the coupling ring  18  and the electrode expansion ring  20  is within the range of about 0.5 mm to about 1.3 mm, a uniform plasma process may be performed. 
     Hereinafter, various modified examples of the substrate processing apparatus  1  described above will be described. Various modified examples of the substrate processing apparatus  1  to be described below will be mainly described based on a deformed component or a replaced component. 
     First, various modified examples of the side contact pad  30  will be described with reference to  FIGS.  4 A to  4 D . 
       FIGS.  4 A to  4 C  are views schematically illustrating modified examples of the side contact pad  30  in the partially enlarged view of  FIG.  2 A  in order to illustrate various modified examples of the side contact pad  30  in  FIG.  2 A , and  FIG.  4 D  is a schematic exploded perspective view illustrating a modified example of a shape of the side contact pad  30  in the exploded perspective view of  FIG.  3   . 
     In a modified example, referring to  FIG.  4 A , an upper end of a side contact pad  30   a  of a modified example may be disposed at a level lower than that of the electrode expansion ring  20 . 
     In a modified example, referring to  FIG.  4 B , an upper end of a side contact pad  30   b  of a modified example may be disposed at a level lower than that of the upper surface of the coupling ring  18  and at a level higher than that of the electrode expansion ring  20 , and a lower end of the side contact pad  30   b  may be disposed at a level lower than that of the electrode expansion ring  20 . 
     In a modified example, referring to  FIG.  4 C , an upper end of a side contact pad  30   c  of the modified example may be disposed at a level higher than that of the electrode expansion ring  20  and at a level substantially the same as that of the upper surface of the coupling ring  18 , and a lower end of the side contact pad  30   c  may be disposed at a level lower than that of the electrode expansion ring  20 . 
     In the inner surfaces  18   s   1  and  18   s   2  of the coupling ring  18  described above, the second inner surface  18   s   2  of the recessed region may extend to the upper surface of the coupling ring  18 . 
     In a modified example, referring to  FIG.  4 D , the ring-shaped side contact pad  30  as shown in  FIG.  3    may be replaced with a plurality of side contact pads  30   d  spaced apart from each other as in  FIG.  4 D . 
     Next, various modified examples of the at least one upper contact pad  28  will be described with reference to  FIGS.  5 A to  5 C , respectively. 
       FIGS.  5 A to  5 C  are views schematically illustrating modified examples of the at least one upper contact pad  28  in the partially enlarged view of  FIG.  2 A  to illustrate various modified examples of the upper contact pad  28  including the first upper contact pad  28   a  and the second upper contact pad  28   b  in  FIG.  2 A . 
     In a modified example, referring to  FIG.  5 A , the second upper contact pad  28   b   1  may cover the entire upper surface of the coupling ring  18  and contact the entire upper surface of the coupling ring  18 . 
     In a modified example, referring to  FIG.  5 B , the first upper contact pad  28   a  and the second upper contact pad  28   b  described above with reference to  FIG.  2 A  may be connected to each other, and the upper contact pad ( 28  of  FIG.  2 A ) including the first upper contact pad  28   a  and the second upper contact pad  28   b  spaced apart from each other in  FIG.  2 A  may be replaced with a single upper contact pad  28 ′ as shown in  FIG.  5 B . 
     The upper contact pad  28 ′ may cover at least a portion of an upper surface of the outer region  13   o  of the lower region  13   c  and  13   o  of the substrate support  13 , contact a portion of the upper surface of the coupling ring  18 , and overlap the electrode expansion ring  20 . The upper contact pad  28 ′ may have a ring shape. 
     In a modified example, referring to  FIG.  5 C , the upper contact pad  28 ′ in contact with the partial upper surface of the coupling ring  18  described above with reference to  FIG.  5 B  may be replaced with a single upper contact pad  28 ″ covering at least a portion of the upper surface of the outer region  13   o  of the lower region  13   c  and  13   o  of the substrate support  13  and covering the entire upper surface of the coupling ring  18 . 
     Next, a method of manufacturing a semiconductor device using a substrate processing apparatus according to embodiments of the present inventive concept will be described with reference to  FIGS.  6  to  9   . In  FIGS.  6  to  9   ,  FIG.  6    is a process flowchart schematically illustrating a method of manufacturing a semiconductor device using a substrate processing apparatus according to embodiments of the present inventive concept, and  FIGS.  7 A,  7 B,  8 A,  8 B,  8 C and  9    are schematic views illustrating a method of manufacturing a semiconductor device using a substrate processing apparatus according to embodiments of the present inventive concept. In  FIGS.  7 A,  7 B,  8 A,  8 B,  8 C, and  9   ,  FIGS.  7 A,  8 A,  8 B, and  8 C  are cross-sectional views illustrating a plasma etching process performed using the substrate processing apparatus  1  of  FIG.  2 A , and  FIG.  9    is a cross-sectional view schematically illustrating an example of a semiconductor device manufactured using a substrate processing apparatus according to embodiments of the present inventive concept. 
     First, referring to  FIGS.  1 ,  6 ,  7 A, and  7 B , the substrate processing apparatus  1  according to embodiments of the present inventive concept may be prepared (S 10 ). The substrate processing apparatus  1  may be a substrate processing apparatus according to any one of various embodiments of the substrate processing apparatus  1  described above with reference to  FIGS.  1  to  5 C . 
     The substrate WF may be loaded onto the substrate support  13  in the substrate processing apparatus  1  (S 20 ). 
     The substrate WF may include a lower structure  200  including a semiconductor substrate, a stack structure  206  including interlayer insulating layers  202  and gate layers  204  alternately and repeatedly stacked on the lower structure  200 , and a mask pattern  210  formed on the stack structure  206  and including openings  210   o.    
     Plasma may be generated in the plasma processing region (PLR of  FIG.  1   ) (S 30 ). Accordingly, a plasma region PL in which plasma is formed may be formed in the plasma processing region (PLR of  FIG.  1   ). For example, a process gas may be supplied from the process gas supply unit  150  into the plasma processing region PLR, and the first RF power generating device  122  of the RF power controller  120  may supply a plasma generating frequency of about 50 MHz to about 100 MHz to the substrate support  13 , which may be an electrostatic chuck ESC, to form the plasma region PL in which plasma is formed in the plasma processing region PLR. 
     Plasma sheath regions PLS 1  and PLS 2  that are simultaneously formed while plasma is formed may be formed between the generated plasma region PL and the substrate WF. The plasma sheath regions PLS 1  and PLS 2  may include a first sheath region PLS 1  on the central region P 1  of the substrate WF and a second sheath region PLS 2  having a thickness changing in a direction from the edge region P 2  of the substrate WF to the body region  25   a  of the edge ring  25 . For example, a distance between the substrate WF and the plasma region PL may change in the edge region P 2  of the substrate WF. The distance between the substrate WF and the plasma region PL may increase in the edge region P 2  of the substrate WF. 
     The plasma of the plasma region PL may be capacitively coupled plasma (CCP). The plasma region PL may include radicals or reactive ions Pi for an etching process. 
     Referring to  FIGS.  1 ,  6 ,  8 A and  8 B , the plasma process may be performed, while heat occurring in the plasma processing region PLR on the edge ring  25  is dissipated through the edge ring  25 , the upper contact pad  28 , the coupling ring  18 , the side contact pad  30 , and the substrate support  13  (S 40 ). Accordingly, in the plasma process, the upper contact pad  28  and the side contact pad  30  may serve to lower a temperature of the edge ring  25 . 
     While controlling a thickness of the second sheath region PLS 2  by supplying a frequency of about 200 kHz to about 2 MHz of first power to the substrate support  13  by the second RF power generating device  124  and supplying a frequency of about 200 kHz to about 2 MHz of second power weaker than the first power to the edge ring  25  by the third RF power generating device  126  through the coupling ring assembly  16 , radicals or ions Pi in the plasma PL may be accelerated toward the substrate WF to anisotropically etch the stack structure  206  exposed by the openings  210   o  of the mask pattern  210 . Accordingly, holes  206 H penetrating through the stack structure  206  may be formed. 
     An interface between the plasma region PL and the sheath regions PLS 1  and PLS 2  may be parallel to the entire upper surface of the substrate WF. Since radicals or ions Pi in the plasma region PL are accelerated in a direction, perpendicular to the interface between the plasma region PL and the sheath regions PLS 1  and PLS 2 , the holes  206 H may be uniformly formed over the entire area of the stack structure  206 . Accordingly, a uniform plasma process, for example, a plasma etching process, may be performed. 
     Referring to  FIGS.  1 ,  6 , and  9   , after the holes  206 H are formed, the plasma process may be terminated. Subsequently, the substrate WF may be unloaded (S 50 ). 
     After the substrate WF is unloaded from the substrate processing apparatus  1 , an additional semiconductor process may be performed. For example, after the substrate WF is unloaded from the substrate processing apparatus  1 , vertical structures  220  may be formed in the holes  206 H. While forming the vertical structures  220 , the mask patterns ( 210  of  FIG.  8 C ) may be removed. 
     In an embodiment, when the gate layers  204  are formed of a conductive material such as polysilicon, the gate layers  204  may remain. 
     In another embodiment, when the gate layers  204  are formed of an insulating material such as silicon nitride, a process of replacing the gate layers  204  with gate layers including a conductive material may be further performed. 
     Each of the vertical structures  220  may include an information storage layer and a channel layer. For example, each of the vertical structures  220  may include a charge trap layer capable of storing information by trapping a charge in a NAND flash memory device. 
     Accordingly, a semiconductor device  300  such as a NAND flash memory device including the vertical structures  220  may be manufactured. 
     In the embodiments described above, since the lower electrode assembly  10  includes the at least one upper contact pad  28  and the side contact pad  30  to implement a low impedance structure, a sheath voltage may be strengthened. 
     In addition, since the at least one upper contact pad  28  and the side contact pad  30  are included, the temperature of the edge ring  25  may be lowered during a plasma process. Accordingly, since a more uniform plasma process may be performed, defects that may occur as the holes  206 H formed in the edge region P 2  of the substrate WF, among the holes  206 H of the substrate WF, are not opened or are deformed may be prevented. 
     In the embodiments described above, since the temperature of the edge ring  25  may be lowered during the plasma process by including the at least one upper contact pad  28  and the side contact pad  30 , an etch rate of the edge ring  25  during the plasma process may be lowered. Accordingly, a replacement cycle of the edge ring  25  that occurs while repeatedly performing the plasma process may be longer. 
     In the embodiments described above, since the at least one upper contact pad  28  may be formed of silicone including conductive fillers such as carbon nanotubes, the at least one upper contact pad  28  may have elasticity. Thus, when the at least one upper contact pad  28  attached to the lower surface of the edge ring  25  may serve to alleviate an impact with the edge ring  25 , the substrate support  13 , and the coupling ring  18  when the edge ring is replaced. Accordingly, the at least one upper contact pad  28  may prevent defects such as cracks occurring when the edge ring  25  is replaced. 
     In the embodiments described above, since the temperature of the edge ring  25  may be lowered during the plasma process, a polymer, among etching byproducts occurring during the formation of the holes  206 H by etching the stacked structure  206 , may be deposited on the edge ring  25 , rather than being deposited on the surface of the substrate WF. Accordingly, a more uniform plasma etching process may be performed on the substrate WF. 
     As set forth above, according to embodiments of the present inventive concept, a substrate processing apparatus and a method for manufacturing a semiconductor device using the same may be provided. The substrate processing apparatus may include a coupling ring assembly surrounding a substrate support, an edge ring on the coupling ring assembly, and an upper contact pad in contact with a lower surface of the edge ring and in contact with at least an upper surface of the coupling ring assembly. The coupling ring assembly may include a coupling ring and a side contact pad contacting a side surface of the substrate support and an inner surface of the coupling ring. 
     Since the substrate processing apparatus includes the upper contact pad and the side contact pad, a uniform plasma process may be performed, while controlling a plasma sheath region. 
     Various and beneficial advantages and effects of embodiments of the present inventive concept are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present inventive concept. 
     While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.