Patent Publication Number: US-2003228750-A1

Title: Method for improving adhesion of a low k dielectric to a barrier layer

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The invention relates to the fabrication of semiconductor devices, and more particularly to a method for improving adhesion of a low k dielectric to a barrier layer in the damascene process.  
       [0003] 2. Description of the Related Art  
       [0004] As integrated circuit feature sizes continue to decrease, it has become advantageous to construct metal connections of copper instead of aluminum. Copper has a lower resistivity than aluminum, and therefore can form higher speed connections for a given line width.  
       [0005] Copper has disadvantages when compared to aluminum that must be overcome. For example, copper is much more susceptible to oxidation during processing. Copper also tends to diffuse into adjacent materials, including dielectrics. To use copper for interconnections, therefore, it is necessary to encapsulate the copper in barrier materials.  
       [0006] It is common in the art to deposit a barrier of a metal material after the copper layer is deposited, typically called a sealing layer. Typically in the art, this sealing layer (also called a cap layer, or an encapsulation layer) overlying the copper is composed of silicon nitride, though other materials are used.  
       [0007]FIG. 1 is a cross-section showing a dual damascene wiring according to the prior art. A semiconductor substrate  100  and an insulating layer  102  are depicted. Interconnection trenches are formed in the insulating layer  102 , and a copper layer  104  has been deposited overlying the insulating layer  102  and filling the trenches. The excess copper layer  104  is then polished back to the insulating layer  102  by chemical mechanical polishing (CMP). Thereafter, a sealing layer  106  is deposited. A low k dielectric layer  108  having dual damascene structures is formed on the sealing layer  106 .  
       [0008] Also, a copper layer  110  is deposited overlying the low k dielectric layer  108  and filling the dual damascene structures. Herein, the copper layer  110  in the dual damascene-structures is connected to the copper interconnect  104  through removal of part of the sealing layer  106 , as shown in FIG. 1. The excess copper layer  110  is then polished back to the low k dielectric layer  108  by CMP.  
       [0009] This sealing layer  106 , typically silicon nitride (SiN), serves as a metal barrier layer to prevent the copper atoms from the layers  104 , 110  diffusing into insulating layer  102  and the low k dielectric layer  108 . In addition, the sealing layer  106  can be used as an etch stop layer for a dual damascene process.  
       [0010] However, the sealing layer between the low k dielectric and copper interconnects creates reliability problems such as copper line-to-line electronic migration (EM) and time dependent dielectric breakdown (TDDB) between copper lines. For example, after being deposited onto the copper surface, an additional dielectric layer will be deposited over the sealing layer. The deposition of the dielectric layer produces stress, which can crack or break the sealing layer. Moreover, in the subsequent CMP of dual damascene process, poor adhesion between the sealing layer and dielectric layers causes the dielectric layer to peel from the sealing layer. The peeling of the dielectric layer creates a path for copper to diffuse outward and for moisture or other contaminates to diffuse inward.  
       SUMMARY OF THE INVENTION  
       [0011] Accordingly, it is an object of the present invention to perform a plasma treatment on a sealing layer to enhance adhesion between the low k dielectric layer and the sealing layer.  
       [0012] It is another object of the invention to form an adhesion layer between the low k dielectric layer and the sealing layer to prevent sealing layer damage during formation of the low k dielectric layer and peeling of the low k dielectric layer after subsequent CMP.  
       [0013] An aspect of this invention is to provide a method for forming a barrier layer between a low k dielectric and metal interconnects, comprising the steps of: providing a substrate covered by an insulating layer having the metal interconnects; forming a sealing layer on the metal interconnects and the insulating layer; performing a plasma treatment on the sealing layer by a reaction gas including at least one of CO 2 , NH 3 , NO 2 , SiH 4 , trimethylsilane (3MS), and tetramethylsilane (4MS); and forming a low k dielectric layer on the sealing layer. The sealing layer is composed of SiN, SiC, SiCH, SiCO or SiCN.  
       [0014] Another aspect of this invention is to provide a method for forming a barrier layer between a low k dielectric and metal interconnects, comprising the steps of: providing a substrate covered by an insulating layer having the metal interconnects; forming a sealing layer on the metal interconnects and the insulating layer; forming an adhesion layer on the sealing layer; and forming a low k dielectric layer on the adhesion layer. The sealing layer is composed of SiN, SiC, SiCH, SiCO or SiCN. Moreover, the adhesion layer is formed by chemical vapor deposition using a reaction gas including at least one of CO 2 , NH 3 , NO 2 , SiH 4 . 3MS, and 4MS or is formed by coating silicate solution. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0015] The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:  
     [0016]FIG. 1 is a sectional diagram showing a dual damascene wiring according to the prior art.  
     [0017]FIGS. 2 a - 2   d  are sectional diagrams showing a dual damascene wiring according to the first embodiment of the present invention.  
     [0018]FIGS. 3 a - 3   d  are sectional diagrams showing a dual damascene wiring according to the second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0019] Embodiments of the present invention are now described with FIGS. 2 a - 2   d  and FIGS. 3 a - 3   d.    
     [0020]FIGS. 2 a - 2   d  show a dual damascene wiring according to the first embodiment of the present invention. In FIG. 2 a , a substrate  200  is provided. The substrate  200  is understood to possibly include a semiconductor wafer, and active and passive devices formed within the wafer. Herein, a smooth substrate  200  is shown to simplify the diagram. An insulating layer  202  such as an oxide layer or organanosilicate glass (OSG) is deposited on the substrate  200 . Interconnection trenches are formed in the insulating layer  202 , and a metal layer  204  such as a copper layer has been deposited overlying the insulating layer  202  and filling the trenches. The excess copper layer  204  is then polished back to the insulating layer  102  by CMP to form copper interconnects  204  in the insulating layer  202 .  
     [0021] In FIG. 2 b , a sealing layer has been deposited on the copper interconnects  204  and the insulating layer  202 . In this embodiment, the sealing layer is SiN, and can be SiC, SiCH, SiCO or SiCN. Thereafter, a plasma treatment is performed on the sealing layer by a reaction gas including at least one of CO 2 , NH 3 , NO 2 , SiH 4 , trimethylsilane (3MS), and tetramethylsilane (4MS) to create active sites on the surface of the sealing layer as indicated  206   a . Herein, the flow rates of CO 2 , NH 3 , NO 2 , SiH 4 , 3MS, and 4MS are, respectively, 500˜1500 sccm, 1500˜3500 sccm, 500˜1500 sccm, 500˜1500 sccm, 500˜2500 sccm and 500˜2500 sccm.  
     [0022] In FIG. 2 c , a low k dielectric layer  208 , such as SilK, FLARE, and PAE2, having dual damascene structures is formed on the sealing layer  206   a.  Subsequently, a copper layer  210  is deposited overlying the low k dielectric layer  208  and filling the dual damascene structures. Herein, the copper layer  210  in the dual damascene structures is connected to the copper interconnects  204  through removal of part of the sealing layer  206   a.    
     [0023] In FIG. 2 d , the excess copper layer  210  is then polished back to the low k dielectric layer  208  by CMP to form the copper interconnect  210  in the low k dielectric layer  208 .  
     [0024] As mentioned above, the sealing layer  206   a  serves as a metal barrier layer to prevent the copper atoms from the layers  204 ,  210  diffusing into insulating layer  202  and the low k dielectric layer  208 , and can be used as an etch stop layer for a dual damascene process. Since the active sites on the surface of the sealing layer  206   a  react with the low k dielectric layer  208 , the adhesion of the low k dielectric layer  208  and sealing layer  206   a  can be improved. Thus, according to the invention, the low k dielectric layer peeling from the sealing after subsequent CMP can be prevented. That is, reliability problems due to the poor adhesion between the sealing layer and low k dielectric layer can be eliminated.  
     [0025]FIGS. 3 a - 3   d  show a dual damascene wiring according to the second embodiment of the present invention. Herein, the same parts with the FIGS. 2 a - 2   d  use the same symbols. In FIG. 3 a , a substrate  200  is provided. An insulating layer  202  such as an oxide layer or organanosilicate glass (OSG) is deposited on the substrate  200 . Interconnection trenches are formed in the insulating layer  202 , and a metal layer  204  such as a copper layer has been deposited overlying the insulating layer  202  and filling the trenches. The excess copper layer  204  is then polished back to the insulating layer  102  by CMP to form copper interconnects  204  in the insulating layer  202 .  
     [0026] In FIG. 3 b , a sealing layer  206 , such as SiN, SiC, SiCH, SiCO or SiCN, is deposited on the copper interconnects  204  and the insulating layer  202 . Thereafter, an adhesion layer  207  is deposited on the sealing layer  20 . In this embodiment, there are two approaches to form the adhesion layer  207 . One is to use chemical vapor deposition (CVD) by a reaction gas including at least one of CO 2 , NH 3 , NO 2 , SiH 4 , 3MS, and 4MS, and the other is to coat silicate solution (serves as an adhesion promoter) on the sealing layer. The thickness of the adhesion layer  207  formed by CVD is about 100˜200 angstroms, and that formed by coating silicate solution is about 1000˜2000 angstroms.  
     [0027] In FIG. 3 c , a low k dielectric layer  208 , such as SILK, FLARE, and PAE2, having dual damascene structures is formed on the adhesion layer  207 . Subsequently; a copper layer  210  is deposited overlying the low k dielectric layer  208  and filled the dual damascene structures. Also, the copper layer  210  in the dual damascene structures is connected to the copper interconnects  204  through removal of part of adhesion layer  207  and the underlying sealing layer  206 .  
     [0028] In FIG. 3 d , the excess copper layer  210  is then polished back to the low k dielectric layer  208  by CMP to form the copper interconnect  210  in the low k dielectric layer  208 .  
     [0029] In this embodiment, the adhesion layer  207  and the sealing layer  206  as a composite barrier layer, and can increase the adhesion with the low k dielectric layer. That is, it has advantages as well as the first embodiment of the invention. In addition, the adhesion layer can be used as a protective layer to prevent the sealing layer damage by stress during the low k dielectric layer is deposited.  
     [0030] The foregoing description has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.