Patent Publication Number: US-5254983-A

Title: Digitally synthesized gray scale for raster scan oscilloscope displays

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention pertains to raster scan displays and, more particularly, to digitally synthesizing a gray scale for raster scan oscilloscope displays. 
     2. Statement of the Problem 
     Signal waveforms when viewed on oscilloscope displays are not always stable, single valued functions. Rather, the signals may shift in amplitude and/or time from one sweep of the screen to the next sweep. The term &#34;sweep&#34; herein refers to the act of displacement of an electron beam across the phosphor coating on the inside of a cathode-ray tube display causing the phosphor to glow and to emit light. 
     The &#34;gray scale&#34; effect on an analog oscilloscope display refers to the condition of the most recently drawn waveform data being the brightest waveform on the display. Waveforms from the recent past sweeps show up in various &#34;shades of gray&#34; depending on how long the waveform has been on the screen. The term &#34;gray scale&#34; herein is defined as discrete steps of brightness between light and dark. The gray scale effect occurred in analog oscilloscopes due to the behavior of the phosphor coating. The phosphor would glow at full brightness when a waveform was initially drawn, and then would fade (unless redrawn again). 
     The gray scale effect on analog oscilloscopes conveyed useful information to a user of the oscilloscope. The user could determine both the current value of the waveform (i.e., from the current sweep) and values it had taken on during the prior sweeps. For example, in FIG. 1 a waveform being observed in the oscilloscope may undergo a minimum amplitude A min  (as shown in FIG. 1a) or a maximum amplitude A max  (as shown in FIG. 1b). The resultant combined image as seen on an analog oscilloscope display is shown in FIG. 1c. Waveform 10 is the waveform from the current sweep (hence, full brightness), waveform 20 was drawn during the last sweep (hence, almost full brightness), waveform 30 was drawn from a previous sweep (hence, dimly lit). The waveforms from other sweeps are also shown and all of these waveforms taken together result in a gray scale envelope 40 collectively placing the waveforms of varying degrees of brightness within a range of amplitude values (A min  -A  max ). 
     The useful information contained in FIG. 1 includes an indication to the user of the analog oscilloscope that the waveform has a current direction 50 of change as shown in FIG. 1c. The sweep frequency (i.e., the sweep repetition rate) and the oscillation by the waveform 100 between A min  and A max  determines what is viewed on the screen as shown by FIG. 1c. For example, if the oscillation between amplitude values occurred at a sufficiently high rate so that the phosphor did not fade to black between refreshes, the user could see the full range of values that the waveform took provided the sweep frequency was fast enough. On the other hand, if the oscillations occurred at an extremely high rate of repetition, the user would only see the most common amplitude values for the waveform. For example, if waveform 100 spent a larger percentage of its oscillation cycle time at A max  then at A min , the outer edges 60 of the gray scale envelope 40 would appear brighter to the user. This is simply due to the fact that the phosphor is excited more often at the outer edges 60 and therefore maintains a higher average level of light output. 
     While the above was a characteristic of analog oscilloscopes, modern digitizing oscilloscopes do not provide the user with the type of gray scale information described above. Rather, modern digitizing oscilloscopes digitize the waveform into a set of discrete values which are then written into a display memory. The display memory holds an image which is copied to the actual display. The image is copied repetitively to the display and continues to be refreshed until the image changes. This is illustrated in FIG. 2. 
     In FIG. 2, a display memory 200 contains the binary information in the form of ones and zeros. For example, in FIG. 2, the display memory 200 has bit pattern 210 which corresponds to a display pattern 220 on a screen 230. The binary one corresponds to an illuminated dot 240. This is graphically shown by arrows 250 and 260. Hence, individual display dots (or pixels) on screen 230 are either on or off and, to the human user, there is no intermediate brightness values which correspond to provide gray scale information. A need exists to provide corresponding gray scale information to the user of a digitizing oscilloscope. 
     One technique utilized in digitizing oscilloscopes is a feature called &#34;variable persistence&#34; which attempts to provide some gray scale information. This feature allows the user to specify how long a data point should stay on screen after it has been drawn. This is simply accomplished by having the microprocessor control determine how long a bit should stay set in display memory 200, with the length of time being controlled by the user. When the preset amount of time has passed, the microprocessor then clears the bit in the display memory which has the effect of erasing the dot from the display In digitizing oscilloscopes, because the phosphor fades from full brightness to off quickly, the data points appear to the user as either being full bright on or off. The &#34;variable persistence feature&#34; simply increases the density (i.e., quantity) of dots fully illuminated on the screen. Hence, there is a greater dot density at the more recent locations of the waveform and a lesser dot density at the less recent locations of the waveform. 
     There are clear disadvantages to the &#34;variable persistence feature. A major disadvantage is that all data points are illuminated to the same brightness under this technique. This actually hides information from the user in two ways. First, in order to see a display of the full range of values of the waveform (i.e., between A min  and A max ), the user of the oscilloscope generally may have to set the persistence time to a relatively long value depending on how fast the waveform changes. The result is that all data points in the waveform range are illuminated at the same level of brightness. It is not possible to visually determine the current value of the waveform or whether the waveform tends to spend more time at some locations than others. Secondly, if the user reduces the persistence time so that the current value of the waveform can be viewed, the user will not be able to view the full range of values the waveform may take. This depends on how quickly the waveform is changing. Hence, a short persistence time could eliminate part of the waveform envelope in favor of showing the current value. 
     Another major disadvantage of the variable persistence method is that the display tends to be covered with a spray of illuminated dots as the waveform changes shape. Because all of the waveform data points are plotted at the same light intensity, the true shape of the waveform may be difficult to determine. It is difficult to determine which set of illuminated dots relate to which trace of the waveform. A good example is a frequency modulated waveform. The waveform itself is a sine wave but its frequency changes. On current variable persistence oscilloscopes, the change from a minimum frequency sine wave to a maximum frequency sine wave creates a solid band of dots on the screen. While the envelope showing the full range of values is created, the waveform shape is difficult to determine in the band of dots. 
     A final disadvantage is that the waveform shown on a digital oscilloscope display does not qualitatively look like the waveform drawn on an analog oscilloscope display. It is difficult for a digital display user to extract the type of gray scale information therefrom. 
     A need, therefore, exists to provide digitizing oscilloscopes with the capability of providing gray scale information as found in analog oscilloscopes. 
     Prior Patented Approaches 
     U.S. Pat. No. 4,829,293 owned by the assignee of the present invention sets forth a method and apparatus for achieving variable and infinite persistence. This illustrates the conventional persistence discussed above. 
     U.S. Pat. No. 4,504,827 sets forth a dynamic synthetic persistence for raster scan displays In this approach, pseudorandom decrementation of the intensity of data which is displayed on a raster screen occurs. This is achieved by randomly selecting the data and randomly varying the times at which the data is decremented. The &#39;827 patent presents a three bit code per pixel. The decrement logic which is provided decrements by one each selected three bit pixel code. The partially decremented code is written back into the memory banks. The operator is able to manually select a desired rate of decay. This is a variation on the synthetic persistence approach discussed above and does not simulate the gray scale effect of an analog oscilloscope display because there is no correlation between the time the waveform is on screen and brightness. The &#39;827 approach is dynamic, in that, the random decrementing occurs as the data is being delivered for display. 
     A need exists to simulate the gray scale effect of an analog oscilloscope wherein all data for a waveform sweep drawn at a given time fades at a constant rate. In other words, the gray scale effect must be a time correlated fade. In the &#39;827 patent this does not occur since all data points are erased pseudorandomly. 
     A need also exists to uniformly fade the data but not to fade other portions of the display carrying graphics information such as scales (graticules), text, etc. A further need exists to provide decrementation to the data independently of the delivery of the data to the display. 
     Solution to the Problem 
     The present invention is a solution to the above problem by providing a digitally synthesized gray scale apparatus and method for digital oscilloscopes which cause the waveform data points to fade from the display as time passes. The fade rate is constant for all waveform points displayed based upon the historic sweep. Under the teachings of the present invention, the waveform data points for the current waveform are drawn on the oscilloscope display as full brightness dots. As time passes, the brightness of the dots having the same historic display time decrease until the dots are completely off or until they are redrawn at full brightness. The present invention provides its decrementation independently of the display of the data, but does not decrement graphics information (i.e., non-waveform) on the display. 
     SUMMARY OF THE INVENTION 
     The present invention constitutes an improvement to a digitizing oscilloscope. Digitizing oscilloscopes comprise two portions. The first portion obtains waveforms from a system or device under test and the second portion of the digitizing oscilloscope displays the current sampled waveform and a number of prior waveforms. The current and prior waveforms are formed by pixels illuminated on a display. The display, in addition to illuminating the sampled waveforms, also provides graphical information. 
     The present invention provides a gray scale binary field corresponding to each of the pixels on the display. Each gray scale binary field has a portion of its bits assigned to correspond to the graphical information and a portion of its bits assigned to correspond to the sampled current and prior waveform information. A decrementing state machine, in a predetermined cycle of operation, periodically reads all of the gray scale binary fields in the display memory of the oscilloscope, decrements each value by a predetermined amount such as the binary value of one, and re-writes the decremented binary values back into the display memory. As these decremented gray scale binary fields are displayed, the older waveforms become uniformly more faded with the oldest waveform having the dimmest illumination. In a typical mode of operation, the predetermined cycle of operation corresponds to the sampling of each new waveform from the system under test so that each subsequent prior waveform is decremented by the predetermined amount. 
     In order to minimize flicker, the first prior waveform is still illuminated at full brightness, along with the current waveform. However, the second prior waveform and all older prior waveforms, under the teachings of the present invention, linearly fade in illumination. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIGS. 1a-1c set forth prior art images as seen on an analog oscilloscope display; 
     FIG. 2 sets forth prior art digital images as represented in a display memory and as seen on a digital screen; 
     FIG. 3 sets forth the block diagram of the digitizing oscilloscope of the present invention; 
     FIG. 4 sets forth the block diagram of the interaction between the decrementer of the present invention and the display memory; 
     FIG. 5 illustrates the display memory of the present invention using a three bit code to drive the display; 
     FIG. 6 sets forth the data field layout of the present invention wherein the displayed waveform fades in time, but graphical information does not fade in time; 
     FIG. 7 is the block diagram of the decrementer of the present invention; 
     FIGS. 8 and 9 set forth the flow chart of the operation of the decrementer shown in FIG. 7; 
     FIG. 10 sets forth the operation of the host processor of the present invention; 
     FIG. 11 sets forth the operation of the graphics system processor of the present invention; 
     FIG. 12 illustrates a display of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In FIG. 3, the system components of the present invention are set forth to include a host microprocessor 300, a display memory 310, a display control (including a display controller 320A and a graphics system microprocessor 320B), a decrementer state machine 330, a priority encoding random access memory (RAM) 340, and a color palette 352 (including a color look-up table 352A and a video digital to analog converter 352B) connected to a display 350. 
     The digitizing oscilloscope of FIG. 3 obtains signals from a system or device under test 370 by inputting signals through a sampling circuit 380. Circuit 380 conventionally samples the signal appearing on lines 372 and delivers the sampled signal on line 382 to the analog to digital (A/D) converter 384 which then delivers the digital input signal for storage in a high speed memory 390 over lines 386. 
     The host microprocessor 300 obtains the digital input signal stored in the high speed memory 390 over the host system bus 362 for processing and updating the host memory 364. The host microprocessor 300 controls the display control 320 over bus 362. The host microprocessor 300 receives inputs from the user input 360 over the host system bus 362 and further stores/receives data in the host memory 364. 
     The graphics system microprocessor 320B enters new waveform data into the display memory 310 over the graphics system bus 332, and controls the decrementer 330 over the same bus. The graphics system microprocessor also accesses the priority encoding RAM 340 and the color palette 352 over bus 332. The display controller 320A controls the display memory 310, the priority encoding RAM 340 and the color palette 352 over lines 324. The display controller 320 also accesses the decrementer 330 over lines 324. 
     The information being displayed is delivered from the display memory 310 over bus 312 to the priority encoding RAM 340, thence to the color palette 352 over lines 342 and finally to the display 350 over lines 354. It is to be expressly understood that the system components of FIG. 3 are presented in a global fashion. In the conventional raster scan display system, the display control 320 continuously reads the display memory 310 to deliver the coded display information from the display memory 310 to the display 350. The display memory 310 is typically read and its contents redrawn on the screen 350 about sixty times per second (i.e., in the preferred embodiment the period is 16.680 milliseconds). 
     Also shown in FIG. 3 is the timebase circuit 302 and the trigger circuit 303. Both are connected to bus 362 and are under control of the host microprocessor 300. The timebase circuit 302 provides timing for the high speed memory 390, the A/D converter 384, and the sampling circuit 380 over lines 302A, 302B, and 302C respectively. The trigger circuit 303 is connected to the timebase 302 by line 303A and receives the signals from the system under test 370. The timebase 302 and trigger 303 actually control the sampling circuit 380, the A/D converter 384, and the high speed memory 390. The microprocessor 300 programs the timebase 302 and trigger 303 to acquire the desired waveform from the system under test 370. The input signal over line 372 is fed into the trigger circuit 303 as well as into the sampling circuit 380. When the signal meets certain conditions (as specified by the user and as programmed by the microprocessor 300) the trigger circuit 303 &#34;triggers&#34; the timebase circuit 302. This causes the timebase circuit 302 to run and control acquisition of the current waveform. The timebase 302 actually tells the sampler 380 to take a sample, tells the A/D converter 384 to digitize that sample, and causes the digitized sample value to be written into the high speed memory 390. The timebase causes samples to be taken at evenly spaced time intervals until the high speed memory is full. 
     In the preferred embodiment the host microprocessor 300 is a Motorola 68020 and the graphics system microprocessor 320B is a Texas Instruments Graphics System Processor Chip Model TMS34010. The color palette 352 is conventionally available from Brooktree, Part No. BT471. 
     DECREMENTER STATE MACHINE 330 OPERATION 
     Unlike the conventional display memory 200 of FIG. 2, the display memory 310 of the present invention provides a pixel data field 400 for each dot on the display 350. Under the teachings of the present invention, the pixel field 400 is at least two binary bits. Hence, as shown in FIG. 4, a separate pixel field 400 exists for each dot on the display 350. Each pixel field 400 could be greater than two binary bits depending upon the degree of greyness resolution desired. The present invention is not to be limited as to the size of the pixel field as long as it is equal to or greater than two binary bits. 
     The decrementer state machine 330 reads each pixel field 400 out from the display memory 310 over bus 332 and, if the pixel value is greater than zero, it decrements the pixel value by a given amount such as one. The decremented pixel value is then delivered over bus 332 back into the display memory 310 to replace the read pixel value and the state machine 330 proceeds to the next pixel field 400. Hence, in a sequential fashion, the state machine 330, pixel field by pixel field (i.e., PIXEL 0, PIXEL 1, . . . , PIXEL N), decrements each pixel value. 
     For example, in FIG. 5, the display memory 310 shows three pixels 500, 510, and 520. Each pixel corresponds to a pixel field 400 in the display memory 310. Pixel 1 is fully illuminated having a value of seven (111 binary) stored therein. Pixel 3 is off (i.e., dark) whereas pixel 2, having a value of three (011), is three sevenths brightness. Of course, if four binary digits are utilized, then 15 levels of brightness could be provided. Under the teachings of the present invention, the binary representation of the gray level is delivered over bus 312 to the priority encoding RAM 340. Hence, it can readily be appreciated that gray level information corresponding to the desired level of brightness can now be provided to the display 350. As will be discussed subsequently, a variation on this example will be made to eliminate flicker. 
     The decrementer state machine 330 is under control of the graphics system microprocessor 320B over the graphics system bus 332. The cycle time of the decrementer 330 can be selectively adjusted by the user through control of input 360 so as to speed up or slow down the period of decrementation (in the preferred embodiment the period ranges vary from a minimum of 50 milliseconds to a maximum of 1.4 seconds). For each period, the decrementer 330 reads each pixel field stored in the display memory 310 and if the value is greater than zero decrements it by a given amount such as one. Hence, the next time that pixel field is read by the display control 320 and displayed 350, the pixel would be drawn on the screen at the desired level of brightness. For example, a pixel whose initial value is seven would be decremented by state machine 330 to six. The next time the display memory 310 is read by the display control 320, the pixel would be redrawn at a gray level value of six. This process then would repeat for the next period. 
     In FIG. 7, the details of the decrementer 330 are shown. The decrementer 330 communicates directly with the graphics system bus 332 and is in communication with the graphics system microprocessor 320B. The decrementer 330 also communicates with the display memory 310. 
     As shown in FIG. 7, the decrementer 330 utilizes a set of decrementer control registers 700. This includes instruction, row address, row distance, column address and column distance registers. These registers are part of the address select and sequencing logic 700A and the read/write control logic 700B. Also included in the decrementer 330 is a decrementer look-through table 710. This is a conventional static RAM. The address select and sequencing logic provides the necessary addresses to the address inputs 310A of the display memory 310 over lines 702. The read/write control logic provides the necessary read/write inputs over line 704 to the read/write inputs 310B of the display memory 310 and to the read/write input 710A of the decrementer look-through table 710. The decrementer look-through table 710 receives address inputs at 710B over lines 706 and delivers data output from data port 710C over lines 708 to the graphics system bus 332. The decrementer address latch 720 is under control of the address select and sequence logic 700A over lines 712 and is interconnected over lines 714 to the graphics system bus 332. The look-through table 710 is initially programmed by delivering data into data port 710C from bus 332. 
     The display memory 310, as shown in FIG. 7, has address inputs 310A, read/write inputs 310B, a serial data port 310C, and a parallel data port 310D. The serial data port 310C delivers the pixel field 400 to be displayed over lines 312 to the priority encoding RAM 340. Hence, the display memory 310 is a dual port (serial-parallel) arrangement. 
     The operation of the decrementer 330 as set forth in the system of FIGS. 3 and 7 will be discussed subsequently. 
     It is to be expressly understood that any number of binary bits in the pixel field 400 (as long as it is greater than or equal to two bits) could be used to implement the levels of gray under the teachings of the present invention. It is also to be expressly understood that, although a separate physical decrementer state machine 330 is shown, the graphics system microprocessor 320B could be suitably programmed to implement the decrementation of the pixel fields in the display memory 310. 
     ADJUSTING FADE TIME 
     The present invention allows the user through manipulation of the user input 360 to specify fade time. The user input 360 delivers the user fade time signal over the host system bus 362 to the host microprocessor 300 to specify the rate of fade. The host microprocessor 300 based upon this input, selectively activates the decrementer state machine 330 to run more or less often. Running the decrementer 330 more often would cause a prior waveform on the screen 350 to fade more quickly from the display and running it less often would cause the dots to fade away more slowly. The user input in the preferred embodiment is a menu selection on screen 350. The user enters persistence time via the instrument&#39;s display menu via the front panel knob or keypad. The persistence time (fade time) control can be changed in the same manner as most other controls in the instrument. The user may use the numeric keypad to enter a desired persistence time directly. In this case, the user specified time will be rounded to the nearest supported time (i.e., 179 ms gets rounded to 200 ms). The user may also use the general purpose knob which will change the persistence time in discrete steps. All supported fade time settings are selectable via the knob. Finally, the user may use the increment and decrement keys which work in the same manner as the knob. Pushing the increment key, for example, has the same result as turning the knob clockwise one &#34;click.&#34; 
     PROCESSING OF GRAPHICAL INFORMATION 
     Since modern digitizing oscilloscope displays include text for such things as text, menus and measurement results as well as other graphical information such as graticules and markers, the gray scale features of the present invention are designed so as not to interfere with such graphics information. Such graphics information does not fade with time under the teachings of the present invention. 
     This is obtained by providing a non-fading field for such graphical information and a fading field for the waveform pixels as shown in the data format of FIG. 6. In FIG. 6, the waveform data field utilizes four binary bits. This field is subject to fading. For example, for pixel J, the lowermost two bits are set to one. This results in pixel J being lit at 3/15 of its maximum brightness. Hence, in the waveform data field of FIG. 6, comprising bits 0 through 3, fifteen levels of brightness can be obtained. The uppermost four bits (bits 4-7) comprise the non-fading field. If one of the upper four bits are set to 1 then the pixel always stays lit at some level of brightness regardless of the value, in the waveform data field. Hence, for pixel K shown in FIG. 6, bit 7 is set to a 1 and this results in pixel K being lit at high brightness. In this arrangement, the decrementer 330 reads and modifies each pixel field (bits 0 through 7), but only the lower four bits are decremented (i.e., bits 0 through 3). 
     In conclusion, it can be observed that under the teachings of the present invention, the user can use the digitized gray scale information on the display to determine characteristics of the waveform normally observed on analog oscilloscopes such as the range of values taken in the recent past, direction in which the waveform is currently changing (i.e., values for the most distant sweep are dimmest vs. most recent sweeps which are brighter), and the current or most frequent values of the waveform. Furthermore, the user of the present invention can easily see which dots on the screen make up individual waveforms due to the time correlated fade. That is, all dots which make up a given prior waveform trace are at the same brightness whereas older waveform traces are more dim and newer ones are brighter. Finally, the display of the present invention looks more like an analog oscilloscope display. Hence, individuals already trained on analog oscilloscopes can obtain the above mentioned information from the gray scale digitized display of the present invention without any additional training such as learning to interpret dot density, etc. These features will be discussed more fully in the following. 
     FLOW OF EVENTS DURING DECREMENT CYCLE 
     In FIG. 8, the method and operation of the decrementer 330 of the present invention will be explained with respect to a decrement cycle. 
     In stage 800, the graphics system microprocessor 320B programs the decrementer look-through table 710. In this stage the decrementer look-through table is properly programmed upon initialization. 
     The graphics processor in stage 810 then draws a current waveform in the display memory 310. In stage 820, a decision is made as to whether or not to run the decrementer 330. If the graphics processor decides not to run the decrementer, stage 810 is again entered and the waveforms are displayed. If the decrementer is to be run, the graphics processor programs the decrementer control registers 700 and stage 830 is entered. The graphics processor enables the decrementer 330 to commence decrementation. 
     Stage 840 is entered and the decrementer 330 requests access to the graphics system bus 332 from the graphics processor 320B. At stage 850, the graphics system microprocessor 320B decides whether or not to grant access to the bus and if granted stage 860 is entered. In stage 860, the decrementer takes control of the graphics system bus 332. The decrementer provides the address of the next display memory location over lines 702 to the address inputs 310A of the display memory 310 and specifies a READ operation over lines 704 for reading the pixel field at that memory location out over bus 714 from the parallel data port 310D. 
     Then stage 870 is entered. In stage 870, the data value for the pixel field is delivered on line 714 into the decrementer address latch 720. Once latched, the data is delivered over line 706 to the address input 710B of the decrementer look-through table 710. 
     At this point, as set forth in FIG. 8, the graphics processor has enabled the decrementer 330 and, the decrementer 330 has taken control of the graphics system bus 332 so as to have dedicated access to the display memory 310. At point A of FIG. 8, the first display data value for the first pixel field read from the display memory 310 at the first address has been loaded into the decrementer 330. 
     In FIG. 9, the decrementer read/write control logic 700B specifies a READ operation to the decrementer look-through table over bus 704. This occurs in stage 900. The decrementer 330, in stage 910, then specifies a WRITE operation to the display memory over bus 704 to the read/write input 310B. This occurs at the same address specified during the previous read operation in stage 870. In stage 920, the value read from the decrementer look-through table 710 is now delivered through the data output 710C onto the graphics system bus 332 to be written into the display memory 310 through the parallel port 310D to replace the original value in the pixel field. It is to be expressly understood that at this stage in the operation, the data value for the pixel field originally stored in the display memory 310 has been read out and suitably decremented and the new decremented value has been written back into the display memory 310 at the original location. 
     Stage 930 is then entered to ascertain whether or not the display memory 310 is fully decremented. If it is, stage 880 of FIG. 8 is entered as shown by B. The decrementer returns control of the graphics system address and data buses 332 to the graphics processor 320B. Stage 810 is then entered. If the display memory is not fully decremented in stage 930, stage 940 is entered. The decrementer checks to see if the display controller 320A has signalled over bus 324 that it needs to do a display refresh cycle or if, according to the decrementer&#39;s own internal timer, it is time for display controller 320A to do some memory refresh cycles. 
     If either type of refresh cycle is needed, stage 950 is entered. In stage 950, memory refresh cycles are done whether they are actually needed or not. Stage 965 is then entered. 
     In Stage 940, if there is not a need to refresh, stage 960 is entered. Again, the decrementer 330 ascertains whether or not the host 300 is waiting to write data into the display system. If it is not, &#34;C&#34; is entered and stage 860 is once again entered to decrement the next data value in the display memory 310. This process continues until all of the data in the display memory 310 is appropriately decremented. 
     In stage 960, if the host is waiting to write data into the display memory 310, then stage 965 is entered and the decrementer 330 gives up control of the graphics system bus 332 to the graphics system microprocessor 320B. Stage 970 is then entered wherein the decrementer 330 waits for several clock cycles before requesting the bus 332 to finish the decrement cycle. This allows time for one or more of the following to occur: memory refresh cycles, display refresh cycles, and the host microprocessor 300 passing data to the display memory 310. Stage 980 is then entered and the decrementer checks to see if the host 300 is still waiting to write data into the display memory 310. If not, stage 840 is entered wherein the decrementer requests the bus 332 in order to complete decrementing of the display memory 310. If the host 300 is still waiting, stage 970 is re-entered. 
     The above fully describes the operation of the decrementer 330 pertaining to the flow of events occurring during the decrement cycle. It is to be expressly understood that a number of different approaches to programming the system of the present invention could be utilized to accomplish the same goals as achieved by the operation set forth in FIGS. 8 and 9. 
     HOST PROCESSOR 300 OPERATION DURING ACQUISITION AND DISPLAY CYCLE 
     In FIG. 10, the operation of the host processor 300 is set forth. In stage 1000, the user of the present invention adjusts the user input 360 to select a time duration for the waveform on display 350 to fade from full brightness to black. The user sets the &#34;fade time.&#34; This is received by the host processor 300 over the host system bus 362. The host processor 300 then delivers the specified fade time to the graphics system microprocessor 320B. This occurs in stage 1010. The user can select a fade time varying, in the preferred embodiment, between 100 milliseconds and 10 seconds. 
     The user of the present invention in stage 1020 interconnects the system under test 370 to the sampling circuit 380 and trigger circuit 303. In stage 1030, the A/D converter digitizes samples of signals obtained from the system under test 370. These digitized samples are then passed from the A/D converter 384 over line 386 into the high speed memory 390 as set forth in stage 1040. 
     The host processor 300 copies the digitized samples representing the waveform from the high speed memory 390 into the normal host memory 364 as set forth in stage 1050. The host microprocessor then sends copies of the digitized waveform from the host memory 364 over host system bus 362 to the display memory 310 as set forth in stage 1060. As indicated in FIG. 10, this process continues as shown by loop 1070 to continually obtain samples of the waveform from the system under test 370. 
     It is to be expressly understood that this approach is conventional in the art and is set forth above for completeness of the disclosure for the present invention. 
     OPERATION OF GRAPHICS SYSTEM 320 DURING WAVEFORM DISPLAY AND GRAY SCALE SIMULATION 
     In FIG. 11, the general method and operation of the graphics system 320 during waveform display and gray scale simulation is set forth. In stage 1100 the graphics system microprocessor (GSP) 320B programs the decrementer look-through table 710 of FIG. 7. The following sets forth an example of how the processor 320B programs the decrementer look-through table. For example, assume that a four bit field is used for each pixel to be displayed on the screen 350. The lower most three bits correspond to the fading waveform field and the higher fourth bit corresponds to the bit field which is used for the display graticule and which is not subject to fading. This example is different from the example of FIG. 6 and is being used to represent a simplistic explanation of what occurs in stage 1100. It is to be expressly understood that the present invention is not limited to the number of bits in the pixel field which fades or to the number of bits which are utilized for the graphics information which does not fade. 
     Table 1 sets forth the contents of the decrement look-through table in this example: 
     
                       TABLE I                                                     
______________________________________                                    
Contents of Decrementer Look-Through Table                                
RAM ADDRESS    RAM CONTENTS                                               
______________________________________                                    
0000           0000                                                       
0001           0000                                                       
0010           0001                                                       
0011           0010                                                       
0100           0011                                                       
0101           0100                                                       
0110           0101                                                       
0111           0110                                                       
1000           1000                                                       
1001           1000                                                       
1010           1001                                                       
1011           1010                                                       
1100           1011                                                       
1101           1100                                                       
1110           1101                                                       
1111           1110                                                       
______________________________________                                    
 
    
     In Table I each RAM 710 address addresses a specific location in the look-through table. In the above it is to be noted that the first eight addresses are not addressed to graphics information such as graticules but rather are addressed to a waveform data value which will fade under the teachings of the present invention. That is, the first eight addresses have the fourth bit set to zero. The first address of &#34;0000&#34; addresses &#34;0000.&#34; The second address of &#34;0001&#34; also addresses &#34;0000&#34; indicating a decrement of one. The third pixel value of &#34;0010&#34; outputs &#34;0001&#34; causing a fade of one increment to occur. This linear fade occurs for the remaining five values. It is to be expressly understood that under the teachings of the present invention, any set of values could be utilized in the RAM 710 contents. For example, the decrementation could be by two rather than one or the first four values could be decremented by one and the second four could be decremented by two. Or, it may be desirable to decrement the first two by one, the next two by two, the third two by three, etc. The look-through table may be programmed in any suitable fashion. The remaining eight values in Table I pertain to graphical information having the fourth bit set to one. Again, the addresses follow the sequence set forth above. 
     Stage 1110 is now entered. In this stage the graphics system microprocessor 320B programs the priority encoding RAM 340 as shown in FIG. 3. This programming occurs over bus 332. The purpose of the priority encoding RAM 340 is to arbitrate when items of different colors overlap on the display 350 to include the same pixel. The priority encoding RAM, as set forth in Table II below, gives waveform data a higher priority than the graphical information. Therefore, if a graticule and a waveform both pass through the same pixel on the display 350, the pixel will be illuminated in the waveform color. The simplistic example set forth above for Table I is continued in Table II and it is to be expressly understood that the present invention is not to be limited by this example. 
     
                       TABLE II                                                    
______________________________________                                    
Priority Encoding RAM                                                     
RAM ADDRESS    RAM CONTENTS                                               
______________________________________                                    
0000           0000                                                       
0001           0001                                                       
0010           0010                                                       
0011           0011                                                       
0100           0100                                                       
0101           0101                                                       
0110           0110                                                       
0111           0111                                                       
1000           1000                                                       
1001           0001                                                       
1010           0010                                                       
1011           0011                                                       
1100           0100                                                       
1101           0101                                                       
1110           0110                                                       
1111           0111                                                       
______________________________________                                    
 
    
     In Table II, it is clear that when graphical information is present (i.e., indicated by the fourth bit of the RAM address being &#34;1&#34;) then the output of the priority encoding RAM contents will clearly produce the waveform information and not the graphical information. This assigns viewing priority to the waveforms on the screen. The only time the graphical information is displayed is when the address is &#34;1000&#34; (i.e., the waveform does not coincide does not coincide with the graphical information) and then the output of the priority encoding RAM contents is &#34;1000.&#34; At all other times, the waveform information is displayed giving priority over the graphical information for that particular pixel. It is to be expressly understood that if it is desired, the graphical information can have priority over the waveform. In this case, the last eight entries for the RAM contents would be &#34;1000.&#34; 
     In stage 1120, the graphics system processor 320B programs the color look-up table 352A of FIG. 3 over bus 332. Again, the example of Tables I and II will be utilized to explain the operation of the color look-up table 352A. This is set forth in Table III below: 
     
                       TABLE III                                                   
______________________________________                                    
Color Look-up Table Contents                                              
                        Color                                             
                        Specification                                     
            Look-up Table                                                 
                        Sent to Video                                     
Waveform    Address     DACs                                              
______________________________________                                    
T-7         0000        Background Color                                  
T-6         0001        1/6 Intensity                                     
T-5         0010        2/6 Intensity                                     
T-4         0011        3/6 Intensity                                     
T-3         0100        4/6 Intensity                                     
T-2         0101        5/6 Intensity                                     
T-1         0110        Full Intensity                                    
T           0111        Full Intensity                                    
            1000        Color-Gray                                        
______________________________________                                    
 
    
     In Table III, the look-up table address which is delivered from the priority encoding RAM 340 is again a four bit binary address. This format is used in this example and is not to limit the teachings of the present invention. In the example, each binary address corresponds to a particular color specification which is sent to the video DACs 352B. The binary &#34;0000&#34; corresponds to the background color --i.e., the pixel is unlit. The binary value &#34;1000&#34; corresponds to the graticule color which in the preferred embodiment is gray and is used for graphical information. The remaining binary values correspond to a particular value of intensity. 
     In the example shown in Table III, the binary values corresponding to &#34;0001&#34; through &#34;0101&#34; correspond to a gray scale analog range of 1/6 through 5/6 of the intensity of the waveform color. Binary values &#34;0110&#34; and &#34;0111&#34; correspond to the full analog intensity of the waveform color. 
     This is an important aspect of the present invention since these binary values produce the full intensity of the waveform color. Hence, as the waveform is displayed during the first cycle of decrementation, even though the pixel data field is decremented by the decrementer 330, the full intensity of the waveform color is maintained by the color lookup table 352A. It is only during the next cycle of decrementation that the pixel goes to 5/6 of the full intensity of the waveform color. This minimizes flicker from occurring under the teachings of the present invention. In other words, during the first period of decrementation, the pixel is maintained at full intensity in order to substantially prevent an annoying flicker which would otherwise occur. Flicker occurs as a result of all full intensity waveform pixels being faded to less than full intensity followed by a new waveform being drawn in illuminated full intensity. By drawing pixels with decimal values of 7 and 6 at full intensity, flicker is minimized (that is, the current and the first prior waveform both are at full brightness). This tends to maintain a constant level of brightness across the display with no perceptible flicker to the human user. 
     The present invention, however, is not limited to the first prior waveform (T-1) being illuminated at full brightness and the first prior waveform could be decremented to less than full brightness. Indeed, it is to be expressly understood that any suitable set of values can be programmed into the color look-up table 352A. For example, three addresses (0111, 0110, and 0101) could be programmed to be full intensity to maintain full brightness for the current and the two most recent prior waveforms. 
     In Table III, the current and first prior waveforms are illuminated at full brightness. Each of the next prior waveforms are illuminated at an intensity of brightness depending upon the age of the prior waveform. The dimmest illumination corresponds to the oldest waveform and the oldest waveform is uniformly the same level of brightness. In Table III, the first prior waveform (T-1) is illuminated at full brightness, the second (T-2) is illuminated at 5/6 intensity and the remaining waveforms (T-2, etc.) fade uniformly. Table III sets forth a specific dependency between age of waveform and intensity of illumination. This dependency is a matter of design choice. For example, the first prior waveform (T-1) could be illuminated at 6/7 intensity with the remaining waveforms (T-2, etc.) uniformly fading therefrom. 
     Stage 1130 of FIG. 11 is now entered. The GSP 320B draws the next waveform at full brightness. Stage 1140 is entered and the graphics system processor 320B determines whether the user specified fade time (÷seven) has elapsed. If not, stage 1130 is reentered. If so, stage 1150 is entered to allow the decrementer to operate. 
     In FIG. 12, a display 1200 appearing on screen 350 is shown based upon the examples of Tables I, II and III. In FIG. 12, waveform T is the most recently drawn waveform, waveform T-1 is the waveform drawn in time just prior to waveform T and waveform T-2 represents a waveform drawn in time just prior to waveform T-1. In the example of FIG. 12, it is assumed that the time required to draw the waveform is approximately equal to 1/7 of the user&#39;s specified waveform fade time. Hence, the decrementer 330 runs immediately after each waveform is drawn. Pixel 1210 corresponds to graphical information such as a graticule and has a code of &#34;1000.&#34; Pixel 1220 is at the intersection of a graticule and waveform T-2 and based upon the above discussion, waveform T-2 has priority and pixel 1220 has a code of &#34;0101.&#34; The most recent drawn waveform T is composed of pixels corresponding to pixel 1230 which has a code of &#34;0111.&#34; Waveform T-1 is composed of pixels 1240 and has a code of &#34;0110.&#34; Keep in mind that waveform T and T-1 have the same intensity as set forth in Table III above. Waveform T-2, however, corresponding to pixel 1250 has an intensity of &#34;0101&#34; which as set forth in Table III above is 5/6 the intensity of the waveform color. The user has the option to adjust the fade time to decrement after the first waveform, after the first two waveforms, etc. 
     It is to be expressly understood that the claimed invention is not to be limited to the description of the preferred embodiment but encompasses other modifications and alterations within the scope and spirit of the inventive concept. For example, while the preferred embodiment of the present invention is based upon an oscilloscope, the teachings of the present invention are useful for any raster scan display. In such applications, images rather than waveforms are drawn on the display 350 with the current and first prior image being drawn at full brightness and the earlier prior images being drawn according to the linear fade technique of the present invention.