Patent Publication Number: US-2023141117-A1

Title: Preparation method for leads of semiconductor structure, and semiconductor structure

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims the priority to Chinese Patent Application No. 202010303243.8, titled “Preparation method for leads of semiconductor structure, and semiconductor structure”, filed to China National Intellectual Property Administration on Apr. 17, 2020, which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present application relates to the field of semiconductors, and in particular, to a preparation method for leads of semiconductor structure and semiconductor structure. 
     BACKGROUND 
     Leads need to be laid in the semiconductor structure and the semiconductor structure needs to come into contact with the leads by contact pillars to realize the electrical connection between devices. At present, the leads are usually lines of equal width. With the improvement of device integration, the leads are required to have a smaller width. Correspondingly, the contact area between the contact pillars and the leads gets smaller, resulting in larger contact resistance. Meanwhile, when the width of the lines is too small, the width of the contact pillars is greater than the width of the lines. The contact pillars going beyond the lines may extend below the leads and may be electrically connected to the conductive region below the leads, causing a short circuit, which in turn affects the electrical performance of the device or even makes the device fail. 
     SUMMARY 
     According to various embodiments of the present application, a preparation method for leads of semiconductor structure and semiconductor structure are provided. 
     A preparation method for leads of semiconductor structure comprises:
     providing a substrate covered with a conductive layer, the substrate having a first region and a second region being connected with the first region at side surfaces;   sequentially forming, on the conductive layer, a second dielectric layer, a first dielectric layer and a mask layer which are superposed one upon the other, the first dielectric layer being in a strip shape, the first dielectric layer and the second dielectric layer extending into the first region from the second region, the mask layer covering the first region and exposing the second region;   etching the second dielectric layer for the first time;   removing the mask layer in the first region to expose the first region;   etching the second dielectric layer for the second time, forming, respectively in the first region and the second region, a first window and a second window exposing the conductive layer, the width of the bottom of the first window being less than the width of the bottom of the second window; and   etching the exposed conductive layer, forming leads, the leads comprising wide lines in the first region and narrow lines in the second region, the line width of the wide lines being greater than the line width of the narrow lines.   

     A semiconductor structure comprises:
     a substrate;   leads formed on the substrate, the leads comprising wide lines and narrow lines, the line width of the wide lines being greater than the line width of the narrow lines;   an interlayer dielectric layer covering the leads; and   contact pillars, penetrating the interlayer dielectric layer and being in contact with the wide lines.   

     In the semiconductor structure, the leads comprise narrow lines with a relatively small width and wide lines with a relatively large width. The narrow lines still meet the requirement on high integration, while the wide lines are in contact with the contact pillars. Thus, the contact resistance can be reduced, and the contact pillars can be prevented from extending below the leads to cause a short circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objectives, features and advantages of the present application will become apparent through the more detailed description of the preferred embodiments of the present application shown in the drawings. Throughout the figures, the same reference numerals indicate the same parts, and the figures are not necessarily drawn to scale. The focus is to show the gist of the present application. 
         FIG.  1   a    is a top view of the contact between the leads and the contact pillars in the traditional technology; 
         FIG.  1   b    is a side cross-sectional view at the section line AA′ of  FIG.  1   a   ; 
         FIG.  2    is a flowchart of steps of a preparation method for leads of semiconductor structure in the present application; 
         FIG.  3   a    is a top view of the structure after the mask layer is formed; 
         FIGS.  3   b  and  3   c    are respectively side cross-sectional views of the second region and the first region of  FIG.  3   a   ; 
         FIG.  4   a    is a top view of the structure after the exposed second dielectric layer is etched for the first time; 
         FIGS.  4   b  and  4   c    are respectively side cross-sectional views of the second region and the first region of  FIG.  4   a   ; 
         FIG.  5   a    is a top view of the structure after the mask layer in the first region is removed; 
         FIGS.  5   b  and  5   c    are respectively side cross-sectional views of the second region and the first region of  FIG.  5   a   ; 
         FIG.  6   a    is a top view of the structure after the exposed second dielectric layer is etched for the second time; 
         FIGS.  6   b  and  6   c    are respectively side cross-sectional views of the second region and the first region of  FIG.  6   a   ; 
         FIG.  7   a    is a top view of the structure after the exposed third dielectric layer is etched; 
         FIGS.  7   b  and  7   c    are respectively side cross-sectional views of the second region and the first region of  FIG.  7   a   ; 
         FIG.  8   a    is a top view of the structure after the exposed conductive layer is etched; 
         FIGS.  8   b  and  8   c    are respectively side cross-sectional views of the second region and the first region of  FIG.  8   a   ; 
         FIG.  9   a    is a schematic structure diagram of the formed leads; and 
         FIG.  9   b    is a side structure view in which the contact pillars are in contact with the leads. 
     
    
    
     DETAILED DESCRIPTION 
     In order to make the above objectives, features and advantages of the present application more obvious and understandable, the specific implementations of the present application will be described in detail below with reference to the accompanying drawings. In the following description, many specific details are provided in order to fully understand the present application. However, the present application may be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the spirit of the present application. Therefore, the present application is not limited by the specific implementations disclosed below. 
     Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the present application belongs. Here, terms used in the description of the present application are merely intended to describe specific embodiments, rather than limiting the present application. As used herein, the term “and/or” includes any or all of one or more associated listed items or combinations thereof. 
     In the traditional technology, as shown in  FIG.  1   a    and  FIG.  1   b   , the leads  210 ′ laid in the semiconductor structure are usually strips of equal width, and the contact pillars  600 ′ penetrate the interlayer dielectric layer to contact the end of the leads  210 ′ to realize the electric connection of the device. As the degree of integration increases, the width of the leads  210 ′ is getting smaller to meet the requirement on the degree of integration. However, as the width of the leads  210 ′ decreases, the contact area between the contact pillars  600 ′ and the leads  210 ′ decreases, which causes the contact resistance between the contact pillars  600 ′ and the leads  210 ′ to increase and thus weakens the electrical performance of the device. Meanwhile, the contact pillars  600 ′ are formed by forming contact holes above the leads  210 ′ and filling the contact holes with a conductive material. When the width of the leads  210 ′ is too small, the width of the formed contact holes is greater than the width of the leads  210 ′. During the formation of the contact holes, the part of the contact holes beyond the leads  210 ′ is not blocked by the leads  210 ′, which may cause the contact holes to be over-etched and extend to the conductive region  110 ′ below the leads. In this case, the contact pillars  600 ′ will cause a short circuit with the conductive region  110 ′ below the leads  210 ′ to make the device fail. 
     In order to solve the technical problems, the present application provides a preparation method for leads of semiconductor structure. As shown in  FIG.  2   , the preparation method for leads of semiconductor structure comprises at least the following steps. 
     S 100 : A substrate covered with a conductive layer is provided, the substrate having a first region and a second region being connected with the first region at side surfaces. 
     As shown in  FIGS.  3   a  to  3   c   , a substrate  100  is provided. The substrate  100  has a working region. The working region is divided into a first region B 1  and a second region B 2  being connected with the first region at side surfaces, that is, the first region B 1  and the second region B 2  adjoin each other and are arranged side by side on the same plane. The conductive layer  200  covers the substrate  100 , that is, the conductive layer  200  covers the first region B 1  and the second region B 2 . 
     It should be noted that an active region is formed in the substrate  100 , and the active region needs to be connected to electrical signals through leads. The specific structure of the substrate  100  is not limited herein. 
     S 200 : A second dielectric layer, a first dielectric layer and a mask layer which are superposed one upon the other are sequentially formed on the conductive layer, the first dielectric layer being in a strip shape, the first dielectric layer and the second dielectric layer extending into the first region from the second region, the mask layer covering the first region and exposing the second region. 
     Still referring to  FIGS.  3   a  to  3   c   , a second dielectric layer  320 , a first dielectric layer  310 , and a mask layer  400  which are superposed one upon the other are sequentially formed on the conductive layer  200 . The second dielectric layer  320  covers the entire conductive layer  200 . The first dielectric layer  310  is in a strip shape, specifically a strip shape of equal width, that is, the first dielectric layer  310  covers only part of the second dielectric layer  320  and exposes part of the second dielectric layer  320 . The first dielectric layer  310  and the second dielectric layer  320  are both in the second region B 2  and extend from the second region B 2  to the first region B 1 . The mask layer  400  covers the first region B 1  and exposes the second region B 2 . The side cross-sectional view of the second region B 2  where the mask layer  400  is not formed is shown in  FIG.  3   b   , and the side cross-sectional view of the first region B 1  where the mask layer  400  is formed is shown in  FIG.  3   c   . 
     In an embodiment, between the second dielectric layer  320  and the conductive layer  200 , more dielectric layers may be provided as needed. For example, as shown in  FIG.  3   b    or  FIG.  3   c   , a third dielectric layer  330  is further provided below the second dielectric layer  320 . 
     S 300 : The second dielectric layer is etched for the first time. 
     Still referring to  FIGS.  4   a  to  4   c   , the second dielectric layer  320  is etched for the first time. It may be understood that the first etching of the second dielectric layer  320  is to etch the exposed second dielectric layer  320  for the first time. In this case, since the first region B 1  is protected by the mask layer  400 , the second dielectric layer  320  in the first region B 1  is not affected by the first etching and the first etching etch only the exposed second dielectric layer  320  in the second region B 2 . 
     In an embodiment, after the first etching in the step S 300 , the whole second dielectric layer  320  exposed in the second region B 2  can be etched away. In another embodiment, since the exposed second dielectric layer  320  will be etched for the second time in the subsequent process, in the first etching in the step S 300 , only the top part of the exposed second dielectric layer  320  in the second region B 2  may be etched away, while the bottom part thereof is left. That is, only part of the exposed second dielectric layer  320  in the second region B 2  is etched away, and the remaining exposed second dielectric layer  320  in the second region B 2  is then etched away during the subsequent second etching of the exposed second dielectric layer  320 . This can save the etching cost.  FIGS.  4   a  to  4   c    are schematic diagrams after only part of the exposed second dielectric layer  320  in the second region B 2  is etched away, wherein  FIG.  4   b    is a side cross-sectional view of the second region B 2  where the mask layer  400  is not formed, and  FIG.  4   c    is a side cross-sectional view of the first region B 1  where the mask layer  400  is formed. 
     S 400 : The mask layer in the first region is removed to expose the first region. 
     As shown in  FIGS.  5   a  to  5   c   , the mask layer  400  in the first region B 1  is removed to expose the first region B 1 . That is, the first dielectric layer  310  and the second dielectric layer  320  in the first region are exposed.  FIG.  5   b    is a side cross-sectional view of the second region B 2 , and  FIG.  5   c    is a side cross-sectional view of the first region B 1 . In this case, the height of the second dielectric layer  320  exposed in the first region B 1  is higher than the height of the second dielectric layer  320  in the second region B 2 . 
     In an embodiment, the substrate  100  further has a peripheral region C which is located on a side of the first region B 1  away from the second region B 2 . In addition to covering the first region B 1 , the mask layer  400  also covers the peripheral region C to protect the peripheral region C. 
     In this case, the step S 400  specifically comprises: carrying out isotropic etching on the mask layer  400 , removing the mask layer  400  in the first region B 1  and reserving the mask layer  400  in the peripheral region C, to expose the first region B 1 . 
     Still referring to  FIGS.  5   a  to  5   c   , the mask layer  400  is etched by isotropic etching. According to the nature of the isotropic etching, the top and sides of the mask layer  400  will be etched, so that the thickness of the mask layer  400  is reduced and its coverage region is reduced from the sides to the middle. Therefore, through the isotropic etching, the mask layer  400  covering the first region B 1  can be etched away, reserving the mask layer  400  in the peripheral region C. The remaining mask layer  400  can continuously protect the peripheral region C. Specifically, the isotropic etching is isotropic dry etching. 
     S 500 : The second dielectric layer is etched for the second time to form, respectively in the first region and the second region, a first window and a second window exposing the conductive layer, the width of the bottom of the first window being less than the width of the bottom of the second window. 
     It may be understood that the second etching of the second dielectric layer  320  is to etch the exposed second dielectric layer  320  for the second time to form, respectively in the first region B 1  and the second region, a first window and a second window exposing the conductive layer  200 . 
     In this case, if the first etching in the step S 300  has etched away the whole second dielectric layer  320  exposed in the second region B 2 , the second etching in this step is to etch only the exposed second dielectric layer  320  in the first region B 1 . If, after the first etching in the step S 300 , there is still the exposed second dielectric layer  320  in the second region B 2 , the second etching in this step will remove both the remaining exposed second dielectric layer  320  in the second region B 2   320  and the exposed second dielectric layer  320  in the first region B 1 , thereby forming a window exposing the conductive layer  200 . 
     In an embodiment, a third dielectric layer  330  is further formed between the conductive layer  200  and the second dielectric layer  320 . In this case, the step S 500  comprises the following steps. 
     S 510 : The second dielectric layer is etched for the second time to form, respectively in the first region and the second region, a first groove and a second groove exposing the third dielectric layer, the width of the bottom of the first groove being less than the width of the bottom of the second groove. 
     As shown in  FIGS.  6   a  to  6   c   , the exposed second dielectric layer  320  is etched for the second time to form, respectively in the first region B 1  and the second region B 2 , a first groove  321  and a second groove  322  exposing the third dielectric layer  330 , the width c1 of the bottom of the first groove  321  in the first region B 1  being less than the width c2 of the bottom of the second groove  322  in the second region B 2 . That is, the width of the third dielectric layer  330  exposed through the first groove  321  in the first region B 1  is less than the width of the third dielectric layer  330  exposed through the second groove  322  in the second region B 2 . 
     In an embodiment, in the step S 300 , etching the second dielectric layer  320  for the first time specifically comprises etching the exposed second dielectric layer  320  in a vertical direction. At least the top part of the side cross-section of the second groove  322  is rectangular. In the step S 500 , etching the second dielectric layer  320  for the second time comprises etching the exposed second dielectric layer  320  in an inclined direction. The side cross-section of the first groove  321  is an inverted trapezoid. That is, the width of the top of the first groove  321  is greater than the width of the bottom. 
     Specifically, when the first etching in the step S 300  has etched away the whole second dielectric layer  320  exposed in the second region B 2 , a second groove  322  may be formed in the step S 300 . In this case, the side cross-section of the second groove  322  is rectangular, that is, the width of the top of the second groove  322  is the same as the width of the bottom; after the first etching in the step S 300 , there is still the exposed second dielectric layer  320  in the second region B 2 , that is, the second dielectric layer  320  exposed in the second region B 2  undergoes the first etching and the second etching. Then, the second groove  322  is formed in the step S 500 , and the second groove  322  formed after the second etching may have a slight slope on the bottom sidewall. In either case, it can be ensured that the width c1 of the bottom of the first groove  321  is less than the width c2 of the bottom of the second groove  322 . 
     In another embodiment, both the first etching in the step S 300  and the second etching in the step S 500  may be inclined etching. The width of the bottom of the first groove  321  is less than the width of the bottom of the second groove  322 , as long as it is ensured that the degree of inclination in the first etching is greater than that in the second etching. 
     S 520 : The exposed third dielectric layer is etched by anisotropic dry etching in a vertical direction to form, respectively in the first region and the second region, a first window and a second window exposing the conductive layer. 
     As shown in  FIGS.  7   a  to  7   c   , the exposed third dielectric layer  330  is etched by anisotropic dry etching in the vertical direction to respectively increase the depth of the first groove  321  and the second groove  322  to form, in the first region B 1  and the second region B 2 , a first window  331  and a second window  332  exposing the conductive layer  200 . 
     S 600 : The exposed conductive layer is etched to form leads, the leads comprising wide lines in the first region and narrow lines in the second region, the line width of the wide lines being greater than the line width of the narrow lines. 
     As shown in  FIGS.  8   a ,  8   b , and  8   c   , the exposed conductive layer  200  is removed, and the remaining conductive layer  200  forms the laid leads  210 . 
     In the above steps, the second dielectric layer  320  exposed in the second region B 2  and the first region B 1  is etched separately by the step S 300  and step S 500 ; and by controlling the etching conditions during the two etching processes, the topography of the first window  331  in the first region B 1  that exposes the conductive layer  200  and the second window  332  in the second region B 2  that exposes the conductive layer  200  may be controlled, so that the width of the bottom of the first window  331  is less than the width of the bottom of the second window  332 . Therefore, the width of the conductive layer  200  etched away in the first region B 1  is less than the width of the conductive layer  200  etched in the second region B 2 , and the conductive layer that is not etched away forms the leads. As shown in  FIG.  9   a   , wide lines  211  are formed in the first region B 1 , and narrow lines  212  are formed in the second region B 2 . The line width d1 of the wide lines  211  is greater than the line width d2 of the narrow lines  212 . In this case, as shown in  FIG.  9   b   , the wide lines  211  may be used to contact the contact pillars  600 , thereby increasing the contact area between the leads  210  and the contact pillars  600  and reducing the contact resistance between the leads  210  and the contact pillars  600 . Furthermore, the large width of the wide lines  211  can prevent the contact pillars  600  from extending into the substrate  100  below the leads  210  to cause a short circuit with the conductive region  110  below the leads  210 . 
     In an embodiment, after the step S 600 , the method further comprises: 
     S 700 : Contact pillars in contact with the wide lines are formed over the first region. 
     As shown in  FIG.  9   b   , an interlayer dielectric layer  500  is formed above the leads  210 , and contact pillars  600  penetrating the interlayer dielectric layer  500  and contacting the wide lines are formed over the first region B 1 . In this case, the contact area between the leads  210  and the contact pillars  600  is large, and the contact resistance between the leads  210  and the contact pillars  600  is low. Furthermore, the large width of the wide lines  211  can prevent the contact pillars  600  from extending into the substrate  100  below the leads  210  to cause a short circuit with the conductive region  110  below the leads  210 . 
     In an embodiment, a source region and a drain region are formed in the substrate  100 , and the narrow lines  212  of the leads  210  are electrically connected to the source region or the drain region. Specifically, the semiconductor structure may be a dynamic random access memory (DRAM). Further, the leads  210  may be bit lines of the DRAM. Of course, the leads  210  may be metal wires or any other wiring that improves electrical connection for semiconductor structure. 
     The etching rates for the first dielectric layer  310 , the second dielectric layer  320 , the third dielectric layer  330 , and the mask layer  400  are different. Specifically, the first dielectric layer  310  may comprise a silicon oxide layer, the second dielectric layer  320  may comprise a silicon oxynitride layer, and the third dielectric layer  330  may comprise an amorphous carbon layer. Specifically, the conductive layer  200  is a metal layer, and the formed leads  210  are metal leads  210 . It should be noted that the selection of materials for the layers is not limited to the materials listed above, and other materials may be used as long as the etching rates for the layers are different. 
     In the preparation method for leads of semiconductor structure, on the basis of the original process, it is unnecessary to change the stripe size of the first dielectric layer. By covering the mask layer in the first region, the second dielectric layer is etched twice by two different etching processes to form windows with different shapes in the first region and the second region, so the width of the conductive layer exposed in the first region and the second region is different. The width of the conductive layer exposed in the first region is less than the width of the conductive layer exposed in the second region. After the exposed conductive layer is etched, the width of the etched conductive layer in the first region is less than the width of the etched conductive layer in the second region, and the width of the non-etched conductive layer in the first region is greater than the width of the non-etched conductive layer in the second region. The non-etched conductive layer forms the leads. The leads obtained by the preparation method have wide lines in the first region and narrow lines in the second region. The narrow lines in the second region still meet the requirement on high integration, while the leads in the first region may be used for contact with the contact pillars. Thus, the contact resistance between the leads and the contact pillars is reduced, and the contact pillars are prevented from extending below the leads to cause a short circuit. 
     The present application further relates to semiconductor structure. As shown in  FIG.  9   a    and  FIG.  9   b   , the semiconductor structure comprises:
     a substrate  100 ;   leads  210  formed on the substrate  100 , the leads  210  comprising wide lines  211  and narrow lines  212 , the line width of the wide lines  211  being greater than the line width of the narrow lines  212 ;   an interlayer dielectric layer  500  covering the leads  210 ; and   contact pillars  600 , penetrating the interlayer dielectric layer  500  and being in contact with the wide lines  211 .   

     In the semiconductor structure, the laid leads  210  comprise narrow lines  212  with a relatively small width and wide lines  211  with a relatively large width. The narrow lines  212  still meet the requirement on high integration, while the wide lines  211  are in contact with the contact pillars  600 . Thus, the contact resistance can be reduced, and the contact pillars  600  can be prevented from extending below the leads  210  to cause a short circuit. 
     The wide lines  211  are located at the end of the leads  210 , that is, the contact pillars  600  are in contact with the end of the leads  210 . Further, an active region and a drain region are formed in the substrate  100 , and the narrow lines  212  are electrically connected to the source region or the drain region. Specifically, the semiconductor structure may be a dynamic random access memory (DRAM). The leads  210  may be bit lines of the DRAM. Of course, the leads  210  may be metal wires or any other wiring that improves electrical connection for semiconductor structure. 
     Various technical features of the above embodiments can be arbitrarily combined. For simplicity, all possible combinations of various technical features of the above embodiments are not described. However, all those technical features shall be included in the protection scope of the present application if not conflict. 
     The embodiments described above merely represent certain implementations of the present application. Although those embodiments are described in more specific details, it is not to be construed as any limitation to the scope of the present application. It should be noted that, for a person of ordinary skill in the art, a number of variations and improvements may be made without departing from the concept of the present application, and those variations and improvements should be regarded as falling into the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.