Patent Publication Number: US-2013254730-A1

Title: Layout system and method of creating differential pair on printed circuit board

Description:
BACKGROUND 
     1. Technical Field 
     The disclosure generally relates to layout systems and methods, and particularly to a layout system and method of creating a differential pair on a printed circuit board (PCB). 
     2. Description of Related Art 
     In PCB design, a differential pair is a pair of wires used for differential signaling, where two wires of the differential pair have a same length. However, in a breakout section of the differential pair, there is a non-parallel section that may cause the lengths of the two wires of the differential pair to be different. In addition, the differential pair should be arranged around electronic components on the PCB which may also cause lengths of the two wires to be different. If the lengths of the two wires are different, the differential pair may cause electromagnetic interference (EMI), which can damage circuits of the PCB. 
     Therefore, there is room for improvement within the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Many aspects of the embodiments can be better understood with reference to the drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the disclosure. 
         FIG. 1  shows a block diagram of one embodiment of a computing device comprising a layout system. 
         FIG. 2  shows a schematic diagram illustrating one embodiment of a layout of a differential pair. 
         FIG. 3  shows a block diagram of one embodiment of function modules of the layout system shown in  FIG. 1 . 
         FIG. 4  and  FIG. 5  cooperate to show a flowchart of one embodiment of a layout method of creating a differential pair. 
     
    
    
     DETAILED DESCRIPTION 
     In general, the word “module,” as used herein, refers to logic embodied in hardware or firmware, or to a collection of software instructions, written in a programming language, such as, for example, Java, C, or assembly. One or more software instructions in the modules may be embedded in firmware, such as in an EPROM. Modules may comprise connected logic units, such as gates and flip-flops, and may comprise programmable units, such as programmable gate arrays or processors. The modules described herein may be implemented as either software and/or hardware modules and may be stored in any type of non-transitory computer-readable medium or other computer storage device. Some non-limiting examples of non-transitory computer-readable mediums include DVDs, CDs, and hard disk drives. 
       FIG. 1  shows a block diagram of one embodiment of a computing device  1  comprising a layout system  10 . The computing device  1  includes a storage system  11 , and a graphical user interface (GUI)  12 . The storage system  11  stores a layout of a PCB (not shown) having a plurality of components. The layout of the PCB includes emulations of the components of the PCB. In some embodiments, the components may be negative parts, that is, via holes, or screw holes. The GUI  12  displays the layout of the PCB. 
     The layout system  10  can be used to design a layout of differential pairs on the PCB, e.g., the layout system  10  may be used to create a differential pair between a differential signal sender and a differential signal receiver on the PCB for transmitting differential signals from the differential signal sender to the differential signal receiver. The differential pair includes two wires. The two wires may be twisted-pair cables. The differential pair includes three sections, i.e., a package section, a breakout section, and a trace section. A section of the two wires sealed in the differential signal sender is defined as the package section. A section of the two wires, which are not sealed, around the differential signal sender is defined as the breakout section. The trace section is the remaining section of the two wires. 
       FIG. 2  is a schematic diagram illustrating one embodiment of a layout of a differential pair. The differential pair consists of wire D 1  and wire D 2 . A signal generation terminal T 1  and a signal generation terminal T 2  are the terminals of the sender in the package section. Pin 1  and pin 2  are pins of the sender in the breakout section. The differential pair around the terminal T 1  and the terminal T 2  is the package section. The section of the differential pair around the pin 1  and the pin 2  is the breakout section. The breakout section of the differential pair further includes a parallel section and a non-parallel section. The parallel section means that the two wires are parallel. Differential signals are generated at the terminals T 1  and T 2  in the package section, and are transmitted from the breakout section to the trace section. The two wires D 1  and D 2  of the differential pair in the trace section are also parallel. 
       FIG. 3  shows a block diagram of one embodiment of function modules of the layout system  10  shown in  FIG. 1 . In an exemplary embodiment, the computing device  1  further includes at least one processor  13 . The layout system  10  may include one or more modules. The one or more modules may comprise computerized code in the form of one or more programs that are stored in the storage system  11  (or memory). The computerized code includes instructions that are executed by the at least one processor  13  to provide functions for the one or more modules. 
     In the exemplary embodiment, the layout system  10  includes a creation module  100 , a searching module  101 , a detection module  102 , a regulation module  103 , and a simulation and testing module  104 . The creation module  100  establishes the differential pair (the two wires D 1  and D 2 ) between the differential signal sender and the differential signal receiver. The layout of the PCB further includes a plurality of components located in the trace section. 
     The searching module  101  searches for bends or curves or corner points (bend points) where one or both of the two wires deviate, and searches for components located in the trace section. For example, the searching module  10  can search for the bends, curves or corner point by using some special software or algorithm. The bend points include the junctions of the parallel section and the non-parallel section in the breakout section of the differential pair, and the remainder of the bend points are in the trace section. The creation module  100  creates a first vertical line at the junctions of the parallel section and the non-parallel section in the breakout section of the differential pair, creates a second vertical line at each bend point of an inner wire of the two wires at the bend, and creates a third vertical line at each component located in the trace section of the differential pair. Intersections of the vertical lines and the two wires, and intersections of the vertical lines and the two wires are separately defined as a pair of bend points. 
     In the exemplary embodiment, as shown in  FIG. 2 , D 1  and D 2  are the two wires of the differential pair. The searching module  101  searches for a point A and a point B which are the junctions of the parallel section and the non-parallel section in the breakout section. The creation module  100  creates the first vertical line that crosses the point A and the point B and is perpendicular to the parallel section of the differential pair. The point A and the point B are defined as a pair of bend points. The two wires D 1  and D 2  of the trace section include a bend point C and a bend point D. The wire D 2  is the inner wire of the two wires at the bend. The creation module  100  creates the second vertical line at the bend point D. The second vertical line is perpendicular to the parallel section connected to the bend point D of the differential pair. There is a component on the point E of the wire D 1  and a separate component on the point F of the wire D 2 . The creation module  100  creates the third vertical line through the point E and the point F. The third vertical line is perpendicular to the parallel section connected to the points E and F of the differential pair. 
     The detection module  102  calculates a first length between one terminal of the differential signal sender and a point of each pair of points on one wire, and calculates a second length between the other terminal of the differential signal sender and the other point of each pair of points on the other wire. For example, referring to  FIG. 2 , the point A and the point B are one pair of points. The first length between the terminal T 1  and the point A is “a”. The second length between the terminal T 2  and the point B is “b”. The detection module  102  further detects if there is any difference between the first length and the second length and if so, whether such difference falls within, an allowable range. Any difference between the first and second lengths is set as ΔS, and the allowable range of the difference ΔS is illustrated as follows: 
     A bit rate of the differential signals transmitted through the differential pair is set as X1 (bit/s), a transmission rate of the differential signals transmitted through the differential pair is set as X2 (mil/ns) (1 mil=1/1000 inch, 1 ns=1 nanosecond), that is X2*10 9  (mil/s). Thus, each bit of a differential signal is transmitted at 
     
       
         
           
             
               
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     A signal rise time Trise or a signal fall time Tfall of the differential pair is set to be equal to 1/N times of the time of transmission of one bit of a differential signal. Accordingly, the differential signals can be transmitted at 
     
       
         
           
             
               
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     within the signal rise time Trise or within the signal fall time Tfall. According to experimental verification, when the difference ΔS is lower than or equal to ⅕ (one fifth) of a transmission length of the differential signals within the signal rise time Trise or the signal fall time Tfall, the wires D 1  and D 2  can achieve an excellent electromagnetic coupling as a differential pair. Therefore, the allowable range of the difference ΔS can be from 0 mil to 
     
       
         
           
             
               
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     For example, if the bit rate X1 is 8 Gbit/s, the transmission rate X2 is 6000 mil/ns, and N=10, and the allowable range of the difference ΔS is from 0 mil to 15 mil. 
     If the difference between the first length and the second length falls outside of the allowable range, then the regulation module  103  adjusts the routes of two wires. D 1  and D 2  of the differential pair. For example, in one embodiment, the regulation module  103  inserts a twist or loop into the shorter one of the two wires D 1  and D 2  of the differential pair adjacent to the corresponding bend point. As shown in  FIG. 2 , the difference between the first length between the terminal T 1  and the bend point C is “c”, and the second length between the terminal T 2  and the bend point D is“d”. If the first length “c” is shorter than the second length “d”, and the difference between the first length “c” and the second length “d” is outside the allowable range, the regulation module  103  twists the wire D 2  adjacent to the bend point D, to form a protrusion section R, thereby lengthening the wire D 2 , so that the difference between the first and second length “c” and “d” is canceled. 
     The simulation and testing module  104  establishes a simulation model of the layout of the PCB, and tests functionality of the layout of the PCB. For example, the simulation and testing module  104  detects phases of the differential signals respectively transmitted by two wires D 1  and D 2 , and searches for a signal transmission capability by determining whether a difference between the phases of the differential, signals transmitted by the two wires D 1  and D 2  is 180°, and detects the EMI level of the layout by determining the coupling of the two wires D 1  and D 2 . If the simulation of the layout as tested does not match the requirement, the regulation module  103  adjusts the lengths of the two wires D 1  and D 2  again for further decreasing the difference ΔS (e.g. by limiting the difference ΔS to a narrower allowable range), until the layout of the PCB passes the simulation test. 
       FIG. 4  and  FIG. 5  cooperate to show a flowchart of one embodiment of a layout method of a differential pair. Depending on the embodiment, additional blocks may be added, others removed, and the ordering of the blocks may be changed. 
     Step S 0 , the creation module  100  establishes the differential pair (the two wires D 1  and D 2 ) between the differential signal sender and the differential signal receiver. 
     Step S 1 , the searching module  101  searches for bend points of the differential pair and components connected along the differential pair. The bend points include the junctions of the parallel section and the non-parallel section in the breakout section of the differential pair, and the remainder of the bend points are in the trace section. 
     Step S 2 , the creation module  100  creates a vertical line at the junctions of the parallel section and the non-parallel section in the breakout section of the differential pair, creates a vertical line at each bend point of an inner wire of the two wires at the bend, and creates a vertical line at the connection to each component located in the trace section of the differential pair. Intersections of the vertical lines and the two wires, and intersections of the vertical lines and the two wires are separately defined as a pair of bend points. 
     Step S 3 , the detection module  102  calculates a first length between one terminal of the differential signal sender and one point of each pair of points on one wire, and calculates a second length between the other terminal of the differential signal sender and the other point, of each pair of points on the other wire. 
     Step S 4 , the detection module  102  further detects whether there is a difference between the first length and the second length and if so whether the difference falls within an allowable range. If the difference falls within the allowable range, step S 6  is executed. If any difference does not fall within the allowable range, step S 5  is executed. 
     Step S 5 , the regulation module  103  adjusts the lengths of the two wires of the differential pair, and the procedure returns to step S 3 . In the exemplary embodiment, the regulation module  103  twists or loops the shorter one of the two wires of the differential pair adjacent to the bend point in question, to lengthen the shorter one of the two wires. 
     Step S 6 , the simulation and testing module  104  establishes a simulation model of the finished layout of the PCB, and tests the functionality of the layout of the PCB. If the layout of the PCB passes the test, the procedure ends. If the layout of the PCB does not pass the test, step S 7  is executed. When testing the layout of the PCB, a length between a test point P 1  (see  FIG. 2 ) on the wire D 1  and the terminal T 1  should equal a length between a test point P 2  on the wire D 2  and the terminal T 2 , to ensure the precision of the test. 
     Step S 7 , the regulation module  103  adjusts the lengths of the two wires again for further decreasing any difference between the first and second lengths. 
     Step S 8 , the detection module  102  calculates the difference between the first and second length to each pair of bend points, and determines whether any difference is within a narrower allowable range. If any difference falls within the narrower allowable range, step S 6  is executed. If one or more of the differences fall outside the narrower range, step S 7  is executed. 
     It is believed that the exemplary embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the disclosure.