Patent Publication Number: US-2023164925-A1

Title: Method for manufacturing printed wiring board

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to forming an electroless plating coating film on a solder resist layer. 
     Description of Background Art 
     Japanese Patent No. 5579160 describes that a palladium catalyst is formed in order to deposit electroless plating on a resin insulating layer. An adsorption amount of the palladium catalyst in Japanese Patent No. 5579160 is 5-1000 mg/m 2 , and a film thickness of the electroless plating is 0.2-2.0 μm. The entire contents of this publication are incorporated herein by reference. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, a method for manufacturing a printed wiring board includes forming an outermost conductor layer on an outermost resin insulating layer, forming a solder resist layer on the outermost resin insulating layer such that the solder resist layer covers the outermost conductor layer formed on the outermost resin insulating layer, irradiating plasma upon an exposed surface of the solder resist layer formed on the outermost conductor layer, forming a catalyst on the exposed surface of the solder resist layer formed on the outermost conductor layer, forming an electroless plating layer on the exposed surface of the solder resist layer via the catalyst formed on the exposed surface of the solder resist layer such that the electroless plating layer has a film thickness in the range of  0 . 05  μm to  0 . 70  μm, forming a plating resist on the electroless plating layer such that the plating resist has openings exposing portions of the electroless plating layer, applying electrolytic plating using the electroless plating layer as a seed layer such that metal posts including electrolytic plating material are formed in the openings of the plating resist, respectively, removing the plating resist from the electroless plating layer, and etching the electroless plating layer exposed from the metal posts such that the electroless plating layer exposed from the metal posts is removed. The forming of the solder resist layer includes forming the solder resist layer on the outermost resin insulating layer such that the solder resist layer has openings exposing portions of the outermost conductor layer, the forming of the electroless plating layer includes forming the electroless plating layer on the portions of the outermost conductor layer, and the forming of the plating resist includes forming the plating resist on the electroless plating layer such that the openings of the plating resist expose the portions of the electroless plating layer formed in the openings of the solder resist layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIGS.  1 A- 1 E  are manufacturing process diagrams of a printed wiring board according to an embodiment of the present invention; 
         FIGS.  2 A- 2 E  are the manufacturing process diagrams of a printed wiring board of the embodiment; 
         FIGS.  3 A- 3 D  are the manufacturing process diagrams of a printed wiring board of the embodiment; 
         FIGS.  4 A- 4 C  are schematic diagrams of palladium catalyst application; 
         FIG.  5    is a diagram of a printed wiring board according to an embodiment of the present invention; and 
         FIG.  6    is a diagram of a printed wiring board according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings. 
     A printed wiring board  10  according to an embodiment of the present invention is illustrated in  FIG.  3 D . In the printed wiring board  10 , metal posts  90  are formed on an outermost conductor layer ( 58 F). The metal posts  90  are formed of an electroless plating layer ( 82 F) and an electrolytic plating film  84  on the electroless plating layer ( 82 F). 
     The printed wiring board  10  of the embodiment may be a printed wiring board having a core substrate, or may be a coreless substrate. A printed wiring board having a core substrate and a method for manufacturing the printed wiring board are described, for example, in JP2007227512A. A coreless substrate and a manufacturing method thereof are described, for example, in JP2005236244A. 
     As illustrated in  FIGS.  1 A and  3 D , the printed wiring board  10  of the embodiment has a core substrate  30 . The core substrate  30  includes: an insulating substrate  20  having a first surface (F) and a second surface (S) on an opposite side with respect to the first surface (F); a first conductor layer ( 34 F) formed on the first surface (F) of the insulating substrate  20 ; and a second conductor layer ( 34 S) formed on the second surface of the insulating substrate  20 . The core substrate  30  further includes through holes  28  for through-hole conductors formed in the insulating substrate  20 . The through holes  28  are filled with a plating film to form through-hole conductors  36 . The through-hole conductors  36  connect the first conductor layer ( 34 F) and the second conductor layer ( 34 S) to each other. A first surface (F) of the core substrate  30  and the first surface (F) of the insulating substrate  20  are the same surface, and a second surface (S) of the core substrate  30  and the second surface (S) of the insulating substrate  20  are the same surface. 
     A resin insulating layer (outermost resin insulating layer) ( 50 F) is formed on the first surface (F) of the core substrate  30 . A conductor layer (outermost conductor layer) ( 58 F) is formed on the resin insulating layer ( 50 F). The conductor layer ( 58 F) and the first conductor layer ( 34 F) or the through-hole conductors  36  are connected to each other by via conductors ( 60 F) that penetrate the resin insulating layer ( 50 F). An upper side build-up layer ( 55 F) is formed by the resin insulating layer ( 50 F), the conductor layer ( 58 F) and the via conductors ( 60 F). In the embodiment, the upper side build-up layer is a single layer. 
     A resin insulating layer (outermost resin insulating layer) ( 50 S) is formed on the second surface (S) of the core substrate  30 . A conductor layer (outermost conductor layer) ( 58 S) is formed on the resin insulating layer ( 505 ). The conductor layer ( 58 S) and the second conductor layer ( 34 S) or the through-hole conductors are connected to each other by via conductors ( 60 S) that penetrate the resin insulating layer ( 505 ). A lower side build-up layer ( 55 S) is formed by the resin insulating layer ( 505 ), the conductor layer ( 58 S) and the via conductors ( 60 S). In the embodiment, the lower side build-up layer is a single layer. 
     An upper side solder resist layer ( 70 F) is formed on the upper build-up layer ( 55 F), and a lower side solder resist layer ( 70 S) is formed on the lower build-up layer ( 55 S). The solder resist layer ( 70 F) has openings ( 71 F) for exposing pads ( 75 F). The metal posts  90  protruding from the openings ( 71 F) are formed on the pads ( 75 F). The solder resist layer ( 70 S) has openings ( 71 S) exposing BGA pads ( 71 SP). A surface treatment film may be formed on the metal posts  90  and the BGA pads ( 71 SP). Examples of the surface treatment film include Ni/Au, Ni/Pd/Au, Pd/Au, Ni/Sn and OSP. 
     Manufacturing Method 
     A method for manufacturing the printed wiring board  10  according to the embodiment illustrated in  FIG.  3 D  is illustrated in  FIGS.  1 A- 1 E,  2 A- 2 E and  3 A- 3 D . 
     The core substrate  30  illustrated in  FIG.  1 A  is prepared. The core substrate  30  includes: the insulating substrate  20  having the first surface (F) and the second surface (S) on an opposite side with respect to the first surface (F); the first conductor layer ( 34 F) formed on the first surface (F) of the insulating substrate  20 ; and the second conductor layer ( 34 S) formed on the second surface of the insulating substrate  20 . The core substrate  30  further includes the through holes  28  for the through-hole conductors formed in the insulating substrate  20 . The through holes  28  are filled with a plating film to form the through-hole conductors  36 . 
     The resin insulating layer ( 50 F) is formed on the first surface (F) of the core substrate  30 , and the resin insulating layer ( 50 S) is formed on the second surface (S) of the core substrate  30 . The openings ( 51 F) are formed in the resin insulating layer ( 50 F), and the openings ( 51 S) are formed in the resin insulating layer ( 505 ) ( FIG.  1 B ). An electroless plating layer  52  is formed by an electroless plating treatment on a surface and in the openings ( 51 F) of the resin insulating layer ( 50 F) and on a surface and in the openings ( 51 S) of the resin insulating layer ( 50 S) ( FIG.  1 C ). The electroless plating layer  52  is formed of, for example, Cu. A plating resist pattern  54  is formed on the electroless plating layer  52  ( FIG.  1 D ). Using the electroless plating layer  52  as a seed layer, an electrolytic plating film  56  is formed by electrolytic plating on the electroless plating layer  52  exposed from the plating resist pattern  54 . In this case, the via conductors ( 60 F) are formed in the openings ( 51 F), and the via conductors ( 60 S) are formed in the openings ( 51 S) ( FIG.  1 E ). The electrolytic plating film  56  is formed of, for example, Cu. The plating resist pattern  54  is removed, the electroless plating layer  52  exposed from the electrolytic plating film  56  is removed, and the conductor layer ( 58 F) and the conductor layer ( 58 S) are formed ( FIG.  2 A ). The upper side solder resist layer ( 70 F) is formed on the resin insulating layer ( 50 F) and the conductor layer ( 58 F), and the lower side solder resist layer ( 70 S) is formed on the resin insulating layer ( 50 S) and the conductor layer ( 58 S). The lower side solder resist layer ( 70 S) has the openings ( 71 S) exposing the BGA pads ( 71 SP) ( FIG.  2 B ). The openings ( 71 F) for exposing the pads ( 75 F) are formed in the upper side solder resist layer ( 70 F) using laser ( FIG.  2 C ). Surfaces of the upper side solder resist layer ( 70 F) and the lower side solder resist layer ( 70 S) are irradiated with plasma, and the surfaces are treated to have an average roughness (Ra) of about 0.06 μm or more and 0.15 μm or less. 
     As a result, wettability of the surfaces is increased, and adhesion to an underfill material or the like is increased. A surface treatment film may be formed on the BGA pads ( 71 SP). Examples of the surface treatment film include Ni/Au, Ni/Pd/Au, Pd/Au, Ni/Sn and OSP. 
     A palladium catalyst is formed on the surfaces of the upper side solder resist layer ( 70 F) and the lower side solder resist layer ( 70 S) by a palladium catalyst chemical treatment. An adsorption amount of the palladium catalyst is 3.0 mg/m 2  or more and 6.0 mg/m 2  or less ( FIG.  2 D ). The adsorption amount of the palladium catalyst is adjusted by concentration, temperature, and immersion time of the palladium catalyst chemical solution. 
     The electroless plating layers ( 82 F,  82 S) each having a film thickness of 0.05 μm or more and 0.70 μm or less are respectively formed by an electroless plating treatment on the surface of the upper side solder resist layer ( 70 F), side walls of the openings ( 71 F), and the pads ( 75 F), and on the surface of the lower side solder resist layer ( 70 S), side walls of the openings ( 71 S), and the BGA pads ( 71 SP) ( FIG.  2 E ). The palladium catalyst is applied to the surfaces of the upper side solder resist layer ( 70 F) and the lower side solder resist layer ( 70 S) at 3.0 mg/m 2  or more and 6.0 mg/m 2  or less, and nuclei of plating deposition are uniformly dispersed. Therefore, the electroless plating layers ( 82 F,  82 S) each having a thin and uniform thickness and a film thickness of 0.05 μm or more and 0.70 μm or less are formed. The electroless plating layers ( 82 F,  82 S) are formed of, for example, Cu. 
     Since the film thickness of each of the electroless plating layers ( 82 F,  82 S) is in the range of 0.05 μm or more and 0.70 μm or less, each of the electroless plating layers can be etched efficiently in a short period of time, and the etching of the metal posts ( 90 ), particularly on the side surfaces of the metal posts ( 90 ), is suppressed. Thus, referring to  FIG.  6   , the metal posts ( 90 ) are formed at a pitch (P) that is narrower such as 60 μm or less more precisely without compromising their structures. 
     Furthermore, the film thickness of each of the electroless plating layers ( 82 F,  82 S) is preferably in the range of 0.05 μm or more and 0.25 μm or less, more preferably in the range of 0.05 μm or more and 0.20 μm or less. When the film thickness of each of the electroless plating layers ( 82 F,  82 S) is as thin as 0.25 μm or less, it is thought that internal stresses in the plating coating films are reduced. Therefore, it is thought that, even when the electroless plating layers ( 82 F,  82 S) are heated by an annealing treatment, peeling or swelling of the plating coating films is unlikely to occur, and adhesion of the electroless plating layers ( 82 F,  82 S) to the surfaces of the solder resist layers is improved. 
     A plating resist ( 86 F) having openings ( 86 A) for metal post formation is formed on the electroless plating layer ( 82 F). Since the film thickness of each of the electroless plating layers ( 82 F,  82 S) is in the range of 0.05 μm or more and 0.70 μm or less, and each of the electroless plating layers can be etched efficiently in a short period of time, the metal posts ( 90 ) are not excessively etched and can substantially maintain a width (W) of the plating resist ( 86 F) between adjacent metal posts ( 90 ) when the electroless plating layers are etched, keeping the plating resist ( 86 F) away from forming a portion with an excessively narrow width (W) between adjacent metal posts ( 90 ), and allowing the plating resist ( 86 F) between adjacent metal posts ( 90 ) to be formed with a width (W) sufficient to avoid problems such as dislocation, falling and leaning (see  FIG.  5   ). A plating resist ( 86 S) protecting the BGA pads ( 71 SP) is formed on the electroless plating layer ( 82 S) ( FIG.  3 A ). The metal posts  90  formed of the electrolytic plating film  84  is formed by electrolytic plating using the electroless plating layer ( 82 F) as a seed layer ( FIG.  3 B ). The electrolytic plating film  84  is formed of, for example, Cu. A protective film may be formed on the metal posts  90 . Examples of the protective film include Ni/Au, Ni/Pd/Au, Pd/Au, Ni/Sn and OSP. The plating resists ( 86 F,  86 S) are peeled off ( FIG.  3 C ). The electroless plating layer ( 82 F) exposed from metal posts  90 , and the electroless plating layer ( 82 S) on the surface of the lower side solder resist layer ( 70 S), the side walls of the openings ( 71 S) and the BGA pads ( 71 SP) are removed, and the printed wiring board  10  is completed ( FIG.  3 D ). 
       FIGS.  4 A- 4 C  are schematic diagrams of palladium catalyst application. 
       FIG.  4 A  illustrates a case where the palladium adsorption amount is small (the amount of the catalyst is less than 3.0 mg/m 2 ). In a region indicated by a chain line circle (C 1 ) in  FIG.  4 A , since intervals between particles of the palladium catalyst are large, a plating coating film cannot be formed and non-deposition occurs. 
       FIG.  4 B  illustrates a case where the palladium adsorption amount is appropriate (the amount of the catalyst is 3.0 mg/m 2  or more and 6.0 mg/m 2  or less). Since the palladium catalyst is uniformly dispersed, a uniform plating coating film having a small film thickness can be formed. 
       FIG.  4 C  illustrates a case where the palladium adsorption amount is excessive (the amount of the catalyst is more than 6.0 mg/m 2 ). In a region indicated by a chain line circle (C 2 ) in  FIG.  4 C , the palladium catalyst is concentrated. In the region indicated by the chain line circle (C 2 ), plating deposition becomes excessive and the plating coating film is partially increased in thickness. 
     When a plating coating film is formed on a solder resist layer having a low surface roughness, an anchor effect due to a concave-convex shape of the surface is difficult to be obtained, and thus, adhesion of the plating coating film to the solder resist layer is weakened. In this case, when the film thickness of the plating coating film on the solder resist layer is too large, it is thought that a stress generated during a heat treatment increases and thereby, peeling or swelling of the plating coating film is likely to occur. It is thought that, in Japanese Patent No. 5579160, it is difficult to form an electroless plating film with an appropriate film thickness and excellent adhesion on a solder resist layer. 
     A method for manufacturing a printed wiring board according to an embodiment of the present invention includes: forming an outermost conductor layer on an outermost resin insulating layer, forming a solder resist layer on the outermost resin insulating layer such that the solder resist layer covers the outermost conductor layer formed on the outermost resin insulating layer, irradiating plasma upon an exposed surface of the solder resist layer formed on the outermost conductor layer, forming a catalyst on the exposed surface of the solder resist layer formed on the outermost conductor layer, forming an electroless plating layer on the exposed surface of the solder resist layer via the catalyst formed on the exposed surface of the solder resist layer such that the electroless plating layer has a film thickness in the range of 0.05 μm to 0.70 μm, forming a plating resist on the electroless plating layer such that the plating resist has openings exposing portions of the electroless plating layer, applying electrolytic plating using the electroless plating layer as a seed layer such that metal posts including electrolytic plating material are formed in the openings of the plating resist, respectively, removing the plating resist from the electroless plating layer, and etching the electroless plating layer exposed from the metal posts such that the electroless plating layer exposed from the metal posts is removed. The forming of the solder resist layer includes forming the solder resist layer on the outermost resin insulating layer such that the solder resist layer has openings exposing portions of the outermost conductor layer, the forming of the electroless plating layer includes forming the electroless plating layer on the portions of the outermost conductor layer, and the forming of the plating resist includes forming the plating resist on the electroless plating layer such that the openings of the plating resist expose the portions of the electroless plating layer formed in the openings of the solder resist layer. 
     In a printed wiring board according to an embodiment of the present invention, since the film thickness of each of the electroless plating layers is in the range of 0.05 μm or more and 0.70 μm or less, each of the electroless plating layers can be etched efficiently in a short period of time, and excessive etching of the metal posts, particularly on the side surfaces of the metal posts is suppressed. Thus, the metal posts can be formed at a narrower pitch more precisely without compromising their structures. Also, when the film thickness of the electroless plating layer is in the range of 0.05 μm to 0.25 μm, more preferably in the range of 0.05 μm to 0.20 μm, it is thought that an internal stress in the plating coating film is reduced. Therefore, it is thought that peeling or swelling of the plating coating film is unlikely to occur and adhesion of the electroless plating layer to the surface of the solder resist layer is improved. 
     Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.