Patent Publication Number: US-11664431-B2

Title: Ring transistor structure

Description:
BACKGROUND 
     Modern day integrated chips comprise millions or billions of transistor devices formed on a semiconductor substrate (e.g., silicon). Integrated chips (ICs) may use many different types of transistor devices, depending on an application of an IC. In recent years, the increasing market for cellular and RF (radio frequency) devices has resulted in a significant increase in the use of high voltage transistor devices. For example, high voltage transistor devices are often used in power amplifiers for RF transmission/receiving chains due to their ability to handle high breakdown voltages (e.g., greater than about 50V) and high frequencies. High voltage devices are also used in power management integrated circuits, automotive electronics, sensor interfaces, flat panel display driver applications, etc. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A- 1 B  illustrate some embodiments of an integrated chip having a transistor device comprising a gate structure that is wrapped around a first source/drain contact to provide isolation between the first source/drain contact and a second source/drain contact. 
         FIGS.  2 A- 2 B  illustrate some additional embodiments of an integrated chip having a transistor device comprising gate structures wrapped around first source/drain contacts. 
         FIG.  3 A  illustrates a top-view of some embodiments of an integrated chip having a transistor device comprising gate structures wrapped around source contacts. 
         FIG.  3 B  illustrates a top-view of some embodiments of an integrated chip having a transistor device comprising gate structures wrapped around drain contacts. 
         FIG.  4    illustrates a graph showing some embodiments of a drain current as a function of gate voltage for a disclosed transistor device. 
         FIG.  5    illustrates a top-view of some embodiments of an integrated chip having a transistor device comprising gate structures wrapped around first source/drain contacts arranged in a two-dimensional array. 
         FIG.  6    illustrates a cross-sectional view of some embodiments of a HEMT (high electron mobility transistor) device comprising gate structures wrapped around first source/drain contacts. 
         FIG.  7    illustrates a cross-sectional view of some embodiments of a MISFET (metal-insulator-semiconductor field-effect-transistor) device comprising gate structures wrapped around first source/drain contacts. 
         FIGS.  8 A- 8 B  illustrate some embodiments of an integrated chip having a transistor device comprising gate structures wrapped around first source/drain contacts and surrounded by an isolation region. 
         FIG.  9    illustrates some additional embodiments of an integrated chip having a transistor device comprising gate structures wrapped around first source/drain contacts and surrounded by an isolation region. 
         FIGS.  10 A- 10 C  illustrate top-views of some alternative embodiments of integrated chips having transistor devices comprising gate structures and/or a second source/drain contact with different shapes. 
         FIGS.  11 A- 11 B  illustrate some embodiments of an integrated chip having a transistor device comprising field plates wrapped around first source/drain contacts. 
         FIGS.  12 A- 21    illustrate some embodiments of a method of forming an integrated chip having a HEMT device comprising gate structures wrapped around first source/drain contacts. 
         FIG.  22    illustrates a flow diagram of some embodiments of a method of forming an integrated chip having a HEMT device comprising gate structures wrapped around first source/drain contacts. 
         FIGS.  23 A- 29    illustrate some embodiments of a method of forming an integrated chip having a MISFET device comprising gate structures wrapped around first source/drain contacts. 
         FIG.  30    illustrates a flow diagram of some embodiments of a method of forming an integrated chip having a MISFET device comprising gate structures wrapped around first source/drain contacts. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     High-voltage transistor devices are used in many modern day electronic devices. As the size of semiconductor devices continues to shrink, there has been an increased interest in high voltage devices that utilize two-dimensional electron gases (2DEGs). Such high voltage devices are typically formed on stacked substrates comprising a plurality of semiconductor layers. The plurality of semiconductor layers include an active layer and a barrier layer that contacts an upper surface of the active layer to form a heterojunction at their interface. A 2DEG is inherently present at the heterojunction between the active layer and the barrier layer. Because a 2DEG is inherently present between the active layer and the barrier layer, electrons are able to move freely along the interface. 
     2DEG based transistor devices may comprise an active area surrounded by an isolation region. The isolation region has a damaged crystalline lattice that confines a 2DEG within the active area by disrupting the 2DEG and mitigating movement of electrons. A source contact and a drain contact are disposed over the active area. To prevent unwanted currents from flowing between the source contact and the drain contact (i.e., to form a device in a “normally off” mode), a gate structure comprising a doped semiconductor material (e.g., p-doped gallium nitride (GaN)) may be disposed within the active area between the source contact and the drain contact. The gate structure is able to interrupt the underlying 2DEG so as to prevent electrons from moving freely under the gate structure. 
     The gate structure may extend over an entire width of the active area as an elongated or rectangular shaped ‘gate finger.’ By having the gate structure extending over an entire width of the active area, the movement of electrons between the source contact and the drain contact can be blocked within the active area. However, it has been appreciated that the isolation region does not provide complete isolation, and that there may be unwanted leakage currents that flow around ends of a gate finger and through the isolation region. The unwanted leakage currents can result in a sub-threshold hump in a drain current vs. gate voltage relation of a transistor device. The sub-threshold hump has a number of negative consequences, such as higher power consumption and being difficult to model (e.g., in SPICE curve fitting and/or parameter extraction). 
     The present disclosure, in some embodiments, relates to an integrated chip that has a transistor device comprising a gate structure that is configured to provide improved isolation between source/drain contacts. The gate structure wraps around a first source/drain contact and a second source/drain contact that wraps around the gate structure. Because the gate structure is able to disrupt an underlying two-dimensional electron gas (2DEG) within the substrate, having the gate structure wrap around the first source/drain contact disrupts the 2DEG along a closed and unbroken path surrounding the first source/drain contact. Disrupting the 2DEG along a closed and unbroken path that surrounds the first source/drain contact improves performance of the transistor device (e.g., reduces a sub-threshold hump in the drain current vs. gate voltage relation of the transistor device) by mitigating leakage between the first source/drain contact and the second source/drain contact. 
       FIGS.  1 A- 1 B  illustrate some embodiments of an integrated chip having a transistor device comprising a gate structure that is wrapped around a source/drain contact.  FIG.  1 A  illustrates a top-view  100  of the integrated chip taken along line A-A′ of  FIG.  1 B .  FIG.  1 B  illustrates a cross-sectional view  114  of the integrated chip taken along line B-B′ of  FIG.  1 A . 
     As shown in top-view  100  of  FIG.  1 A , the integrated chip comprises a transistor device having a first source/drain contact  104 , a gate structure  106 , and a second source/drain contact  108  disposed over a stacked substrate  102 . The first source/drain contact  104  and the second source/drain contact  108  are separated by the gate structure  106  along a first direction  110  and along a second direction  112  that is perpendicular to the first direction  110 . In some embodiments, the first source/drain contact  104  may comprise a source contact and the second source/drain contact  108  may comprise a drain contact. In such embodiments, a source contact is surrounded by the gate structure  106  and the gate structure  106  is surrounded by a drain contact. In other embodiments, the first source/drain contact  104  may comprise a drain contact and the second source/drain contact  108  may comprise a source contact, so that a drain contact is surrounded by the gate structure  106  and the gate structure  106  is surrounded by a source contact. 
     As shown in cross-sectional view  114  of  FIG.  1 B , the stacked substrate  102  comprises a plurality of different layers stacked onto one another. In some embodiments, the stacked substrate  102  comprises an active layer  120  (e.g., a channel layer) disposed over a base substrate  116  and a barrier layer  122  disposed over the active layer  120 . In some embodiments, a buffer layer  118  may be disposed between the active layer  120  and the base substrate  116  to improve lattice matching between the base substrate  116  and the active layer  120 . The active layer  120  and the barrier layer  122  meet at an interface that defines a heterojunction in which a two-dimensional electron gas (2DEG)  121  is present. An inter-level dielectric (ILD) layer  124  is disposed over the stacked substrate  102 . A plurality of conductive contacts  126  extend through the ILD layer  124  to contact the first source/drain contact  104 , the gate structure  106 , and the second source/drain contact  108 . 
     As shown in top-view  100  of  FIG.  1 A , the gate structure  106  wraps around the first source/drain contact  104  along a first closed loop or a first closed path (e.g., a continuous and unbroken path). The second source/drain contact  108  wraps around the gate structure  106 . In some embodiments, the second source/drain contact  108  wraps around the gate structure  106  along a second closed loop or second closed path (e.g., a continuous and unbroken path). 
     The gate structure  106  is configured to disrupt the 2DEG  121  within the stacked substrate  102 . Because the gate structure  106  wraps around the first source/drain contact  104  along the first closed loop, the gate structure  106  is able to disrupt the 2DEG  121  along a continuous path that separates the first source/drain contact  104  and the second source/drain contact  108 . By disrupting the 2DEG  121  along a continuous path that separates the first source/drain contact  104  and the second source/drain contact  108 , currents are not able to leak around ends of the gate structure  106 . Therefore, the gate structure  106  is able to provide for good isolation between the first source/drain contact  104  and the second source/drain contact  108 . The isolation provided by the gate structure  106  may mitigate a sub-threshold hump in a drain current vs. gate voltage relation of the transistor device even without an isolation region. 
       FIGS.  2 A- 2 B  illustrate some embodiments of an integrated chip having a transistor device comprising gate structures wrapped around first source/drain contacts.  FIG.  2 A  illustrates a top-view  200  of the integrated chip taken along line A-A′ of  FIG.  2 B .  FIG.  2 B  illustrates a cross-sectional view  206  of the integrated chip taken along line B-B′ of  FIG.  2 A . 
     As shown in top-view  200  of  FIG.  2 A , the integrated chip comprises a transistor device having a plurality of first source/drain contacts  104   a - 104   c  that are separated from one another along a first direction  110 . A plurality of gate structures  106   a - 106   c  are disposed over the stacked substrate  102  and are interleaved between the plurality of first source/drain contacts  104   a - 104   c  along the first direction  110 . The plurality of gate structures  106   a - 106   c  are separated from one another along the first direction  110  and are separated from the plurality of first source/drain contacts  104   a - 104   c  along the first direction  110  and along a second direction  112  that is perpendicular to the first direction  110 . The plurality of gate structures  106   a - 106   c  wrap around respective ones of the plurality of first source/drain contacts  104   a - 104   c . For example, a first gate structure  106   a  wraps around first source/drain contact  104   a  and a second gate structure  106   b  wraps around first source/drain contact  104   b . Although top-view  200  is illustrated as having three gate structures and three first source/drain contacts it will be appreciated that in various embodiments, a disclosed transistor device may comprise tens, hundreds, or thousands of gate structures and first source/drain contacts. 
     A second source/drain contact  108  is also disposed over the stacked substrate  102 . The second source/drain contact  108  continuously extends in the first direction  110  past outermost ones of the plurality of first source/drain contacts  104   a - 104   c . In some embodiments, the second source/drain contact  108  continuously wraps around the plurality of gate structures  106   a - 106   c  and the plurality of first source/drain contacts  104   a - 104   c . The second source/drain contact  108  comprises a plurality of loops  202   a - 202   c  that are coupled together. For example, the second source/drain contact  108  may comprise a first loop  202   a , a second loop  202   b , and a third loop  202   c . In some embodiments, the plurality of loops  202   a - 202   c  are respectively defined by one or more curved sidewalls of the second source/drain contact  108 . 
     The plurality of loops  202   a - 202   c  comprise a plurality of interior sidewalls  108   i  that define a plurality of openings  204   a - 204   c  extending through the second source/drain contact  108 . In some embodiments, the plurality of openings  204   a - 204   c  are separated from one another along the first direction  110 . Respective ones of the plurality of gate structures  106   a - 106   c  and the plurality of first source/drain contacts  104   a - 104   c  are disposed within respective ones of the plurality of openings  204   a - 204   c . For example, first source/drain contact  104   a  and first gate structure  106   a  are disposed within a first opening  204   a , first source/drain contact  104   b  and second gate structure  106   b  are disposed within a second opening  204   b , etc. 
     In various embodiments, the plurality of first source/drain contacts  104   a - 104   c  respectively comprise a rectangular shape, a rounded rectangular shape, a square shape, a rounded square shape, or the like. In various embodiments, the plurality of gate structures  106   a - 106   c  and the second source/drain contact  108  may respectively comprise a circular shape, an oval shape, a rounded rectangular shape, a hexagonal shape, a racetrack shape, or the like. In some embodiments, the plurality of gate structures  106   a - 106   c  comprise line segments  107 L and end segments  107   e . The line segments  107 L extend in the second direction  112  along opposing sides of the plurality of first source/drain contacts  104   a - 104   c . In some embodiments, the line segments  107 L may extend past opposing ends of the plurality of first source/drain contacts  104   a - 104   c . The end segments  107   e  wrap around ends of the plurality of first source/drain contacts  104   a - 104   c  to couple together adjacent ones of the line segments  107 L. In various embodiments, the end segments  107   e  may have a curved sidewall that define a semi-circular shape, a semi-oval shape, a semi-hexagonal shape with rounded corners, or the like. In some embodiments, a rounded shape of the end segments  107   e  may reduce crowding of electric field lines generated by the plurality of gate structures  106   a - 106   c . In some embodiments, the line segments  107 L may define a central region of the plurality of openings  204   a - 204   c  having a substantially constant width, while the end segments  107   e  may define end regions of the openings  204   a - 204   c  that have widths that decrease as a distance from the central region increases. In some embodiments, the second source/drain contact  108  may also comprise line segments  109 L and end segments  109   e.    
     As shown in cross-sectional view  206  of  FIG.  2 B , the stacked substrate  102  comprises an active layer  120  disposed over a base substrate  116  and a barrier layer  122  disposed over the active layer  120 . In some embodiments, a buffer layer  118  may be disposed between the active layer  120  and the base substrate  116 . The active layer  120  and the barrier layer  122  meet at an interface that defines a heterojunction at which a two-dimensional electron gas (2DEG)  121  is present. In various embodiments, the base substrate  116  may comprise silicon, silicon carbide, sapphire, or the like. In some embodiments, the active layer  120  may comprise gallium nitride (GaN), gallium arsenide (GaAs), or the like. In some embodiments, the barrier layer  122  may comprise aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), or the like. In some embodiments, the buffer layer  118  may comprise GaN (having different concentrations of Ga and N than the active layer  120 ), GaAs (having a different concentrations of Ga and As than the active layer  120 ), or the like. 
     In some embodiments, the plurality of gate structures  106   a - 106   c  respectively comprise a lower gate layer  208  and a gate contact  210  over the lower gate layer  208 . Both the lower gate layer  208  and the gate contact  210  of the plurality of gate structures  106   a - 106   c  wrap around the plurality of first source/drain contacts  104   a - 104   c  in closed loops. In various embodiments, the gate contact  210  may comprise a metal, such as aluminum, cobalt, titanium, tungsten, or the like. In some embodiments, the transistor device is a high electron mobility transistor (HEMT) device and the lower gate layer  208  is a doped semiconductor material, such as p-doped gallium nitride, for example. The doped semiconductor material allows the plurality of gate structures  106   a - 106   c  to interrupt the underlying 2DEG  121  so as to form a “normally-off” device. In other embodiments, the transistor device is a metal-insulator-semiconductor field-effect-transistor (MISFET) device and the lower gate layer  208  is an insulating material, such as silicon dioxide, silicon nitride, or the like. 
     An ILD layer  124  is disposed over the stacked substrate  102 . Conductive contacts  126  extend through the ILD layer  124  to contact the plurality of first source/drain contacts  104   a - 104   c , the plurality of gate structures  106   a - 106   c , and the second source/drain contact  108 . In some embodiments (not shown), additional interconnect layers (e.g., interconnect wires and/or interconnect vias) may be disposed within additional ILD layers over the ILD layer  124 . The additional interconnect layers may comprise a plurality of conductive interconnects that are configured to electrically couple the plurality of first source/drain contacts  104   a - 104   c  and to electrically couple the plurality of gate structures  106   a - 106   c . Because the plurality of first source/drain contacts  104   a - 104   c  and the plurality of gate structures  106   a - 106   c  are respectively electrically coupled together, the plurality of first source/drain contacts  104   a - 104   c  and the plurality of gate structures  106   a - 106   c  operate as a single transistor device. 
     In various embodiments, the conductive contacts  126  may be disposed at different locations on the second source/drain contact  108 . For example, in some embodiments the conductive contacts  126  may be disposed on one of the line segments  109 L of the second source/drain contact  108 , while in other embodiments the conductive contacts  126  may be disposed on one of the end segments  109   e  of the second source/drain contact  108 . In some embodiments, multiple conductive contacts may be disposed on the second source/drain contact  108 . In other embodiments, a single conductive contact may be disposed on the second source/drain contact  108 . 
       FIG.  3 A  illustrates a top-view of some embodiments of an integrated chip having a transistor device comprising gate structures wrapped around source contacts. 
     The integrated chip  300  comprises a transistor device having a plurality of source contacts  302   a - 302   b  separated along a first direction  110 . A plurality of gate structures  106   a - 106   b  wrap around the plurality of source contacts  302   a - 302   b  and a drain contact  304  wraps around the plurality of gate structures  106   a - 106   b . Having the drain contact  304  wrap around the gate structures  106   a - 106   b  may improve device performance by allowing a high voltage that is applied to the drain contact  304  to be spread out over a relatively large area. 
     In some embodiments, the plurality of source contacts  302   a - 302   b  have a first width  306  and the drain contact  304  has a second width  308 . In some embodiments, the first width  306  and the second width  308  may be larger than a third width  310  of the plurality of gate structures  106   a - 106   b . In some embodiments, the first width  306  and/or the second width  308  may be between approximately 100% and approximately 200% larger than the third width  310 , between approximately 50% and approximately 250% larger than the third width  310 , or other suitable values. The greater widths of the plurality of source contacts  302   a - 302   b  and the drain contact  304  allows for overlying interconnects (e.g., conductive contacts) to form good electrical connections with the plurality of source contacts  302   a - 302   b  and the drain contact  304  at large voltages (e.g., greater than approximately 100V, greater than approximately 200V, or the like). 
     In some embodiments, the plurality of gate structures  106   a - 106   b  are separated from the plurality of source contacts  302   a - 302   b  by a first distance  312  and from the drain contact  304  by a second distance  314  that is larger than the first distance  312 . In some embodiments, the first distance  312  may be in a range of between approximately 1 μm and approximately 15 μm, between approximately 2 μm and approximately 10 μm, or other suitable values. In some embodiments, the second distance  314  may be in a range of between approximately 5 μm and approximately 150 μm, between approximately 10 μm and approximately 100 μm, or other suitable values. By having the second distance  314  larger than the first distance  312 , a breakdown voltage of a device can be increased. 
     Although the integrated chip  300  of  FIG.  3 A  illustrates a transistor device having a plurality of source contacts  302   a - 302   b  surrounded by a drain contact  304 , it will be appreciated that the isolation provided by the plurality of gate structures  106   a - 106   b  allows for positions of the plurality of source contacts  302   a - 302   b  and the drain contact  304  to be switched. For example,  FIG.  3 B  illustrates a top-view of some embodiments of an integrated chip  316  having a transistor device comprising a plurality of gate structures  106   a - 106   b  wrapped around a plurality of drain contacts  304   a - 304   b  and a source contact  302  wrapped around the plurality of gate structures  106   a - 106   b.    
       FIG.  4    illustrates a graph  400  showing some embodiments of a drain current as a function of a gate voltage for a disclosed transistor device. 
     Graph  400  illustrates a gate voltage V g  along an x-axis and a drain current (I d ) along a y-axis. The drain current of a transistor device having rectangular shaped gate fingers is shown by line  402 . The drain current of a transistor device having the disclosed gate structure (e.g., a gate structure that wraps around a first source/drain contact as illustrated, for example, in  FIG.  1   ) is shown by line  404 . As shown in graph  400 , the drain current shown by line  402  has a larger sub-threshold hump  406  than that of the drain current shown by line  404 . 
       FIG.  5    illustrates a top-view of some embodiments of an integrated chip  500  having a transistor device comprising gate structures wrapped around first source/drain contacts arranged in a two-dimensional array. 
     The integrated chip  500  comprises a transistor device having a plurality of first source/drain contacts  104   x , a plurality of gate structures  106   x , and a second source/drain contact  108  disposed over a stacked substrate  102 . The plurality of first source/drain contacts  104   x  and the plurality of gate structures  106   x  are separated along a first direction  110  and along a second direction  112  that is perpendicular to the first direction  110 . 
     The second source/drain contact  108  comprises a plurality of loops  202   a - 202   g  that are coupled together as a continuous structure that wraps around the plurality of first source/drain contacts  104   x  and the plurality of gate structures  106   x . In some embodiments, the plurality of loops  202   a - 202   g  are arranged in a two-dimensional array extending along the first direction  110  and the second direction  112 . For example, the plurality of loops  202   a - 202   g  may comprise a first plurality of loops  202   a - 202   d  arranged along a first row  502   a  and a second plurality of loops  202   e - 202   g  arranged along a second row  502   b  that is laterally offset from the first row  502   a . In some embodiments, one or more openings  504  may be present between the first plurality of loops  202   a - 202   d  and the second plurality of loops  202   e - 202   g . By arranging the plurality of loops  202   a - 202   g  in a two dimensional array, a design flexibility of the device can be increased. 
     It will be appreciated that in various embodiments, the disclosed transistor device may be any transistor device that utilizes a 2DEG.  FIGS.  5 - 6    illustrates some embodiments of integrated chips having different types of transistor devices.  FIGS.  5 - 6    are non-limiting examples of transistor devices that may utilize the disclosed gate structures and one of ordinary skill in the art will appreciate that other types of transistor devices may also be used. 
       FIG.  6    illustrates some embodiments of an integrated chip  600  having a high electron mobility transistor (HEMT) device comprising gate structures wrapped around first source/drain contacts. 
     The integrated chip  600  comprises a HEMT device having a plurality of first source/drain contacts  104   a - 104   b , a plurality of gate structures  106   a - 106   b , and a second source/drain contact  108  disposed over a stacked substrate  102 . The plurality of gate structures  106   a - 106   b  respectively comprise a doped semiconductor material  602  and a gate contact  210  over the doped semiconductor material  602 . In some embodiments, the doped semiconductor material  602  may comprise p-doped gallium nitride. In some embodiments, one or more sidewalls of the doped semiconductor material  602  may be laterally offset from one or more sidewalls of the gate contact  210 . 
     A passivation layer  604  extends over the plurality of first source/drain contacts  104   a - 104   b  and the second source/drain contact  108 . The passivation layer  604  also extends over the doped semiconductor material  602  of the plurality of gate structures  106   a - 106   b . The gate contact  210  extends through the passivation layer  604  to contact the doped semiconductor material  602 . In various embodiments, the passivation layer  604  may comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or the like. 
       FIG.  7    illustrates some additional embodiments of an integrated chip  700  having a MISFET (metal-insulator-semiconductor field effect transistor) device comprising gate structures wrapped around first source/drain contacts. 
     The integrated chip  700  comprises a MISFET device having a plurality of first source/drain contacts  104   a - 104   c , a plurality of gate structures  106   a - 106   c , and a second source/drain contact  108  disposed over a stacked substrate  102 . The plurality of gate structures  106   a - 106   c  respectively comprise an insulating material  702  and a gate contact  210  over the insulating material  702 . In some embodiments, the insulating material  702  may comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or the like. In some embodiments, sidewalls of the insulating material  702  may be substantially aligned with sidewalls of the gate contact  210 . 
       FIGS.  8 A- 8 B  illustrate some embodiments of an integrated chip having a transistor device comprising gate structures wrapped around first source/drain contacts and surrounded by an isolation region. 
     As shown in cross-sectional view  800  of  FIG.  8 A , the integrated chip comprises an active area  802  disposed within a stacked substrate  102 . The stacked substrate  102  comprises an active layer  120  disposed over a base substrate  116  and a barrier layer  122  disposed over the active layer  120 . In some embodiments, a buffer layer  118  may be disposed between the active layer  120  and the base substrate  116 . A 2DEG  121  is present at an interface of the active layer  120  and the barrier layer  122 . 
     The active area  802  is surrounded by an isolation region  804 . In some embodiments, the isolation region  804  may comprise a region of the stacked substrate  102  in which crystalline structures of one or more layers of the stacked substrate  102  are damaged (e.g., by way of an ion implantation process). The crystalline damage within the one or more layers disrupts the 2DEG  121 , so as to prevent the 2DEG  121  from extending into the isolation region  804 . 
     As shown in top-view  806  of  FIG.  8 B , the active area  802  is surrounded by the isolation region  804  along a first direction  110  and along a second direction  112  that is perpendicular to the first direction  110 . The active area  802  has a length  808  extending along the first direction  110  and a width  810  extending along the second direction  112 . In some embodiments, the length  808  is larger than the width  810 . 
     A plurality of first source/drain contacts  104   a - 104   c , a plurality of gate structures  106   a - 106   c , and a second source/drain contact  108  are disposed over the active area  802 . The second source/drain contact  108  continuously wraps around the plurality of gate structures  106   a - 106   c  and the plurality of first source/drain contacts  104   a - 104   c . In some embodiments, the active area  802  extends past outermost sidewalls of the second source/drain contact  108  along the first direction  110  and/or along the second direction  112 . In other embodiments (not shown), a part of the plurality of first source/drain contacts  104   a - 104   c  may extend to over the isolation region  804 . For example, the plurality of first source/drain contacts  104   a - 104   c  may extend along the second direction  112  over the isolation region  804 . 
       FIG.  9    illustrates a top-view of an integrated chip  900  having a transistor device comprising gate structures wrapped around first source/drain contacts and surrounded by an isolation region. 
     The integrated chip  900  comprises an active area  902  surrounded by an isolation region  804  along a first direction  110  and along a second direction  112 . A plurality of gate structures  106   x  are disposed over the active area  902  around a plurality of first source/drain contacts  104   x . The active area  902  has a first width  904  and a second width  906  that is larger than the first width  904 . In some embodiments, the active area  902  comprises a plurality of curved edges  908  that extend between the first width  904  and the second width  906 . In some embodiments, the plurality of curved edges  908  are substantially conformal to curved outer sidewalls of the second source/drain contact  108 . The curved edges  908  allow the isolation region  804  to provide for greater isolation over a smaller area. 
       FIG.  10 A  illustrates a top-view of some alternative embodiments of an integrated chip  1000  having a transistor device comprising gate structures and/or a second source/drain contact with different shapes. 
     The integrated chip  1000  comprises a transistor device having a plurality of gate structures  106   a - 106   d  disposed within an active area  802  of a substrate  102  and separated along a first direction  110 . The plurality of gate structures  106   a - 106   d  respectively surround one of a plurality of first source/drain contacts  104   a - 104   d  and are separated from one another by a second source/drain contact  108 . 
     The plurality of gate structures  106   a - 106   d  comprise a first gate structure  106   a  disposed along a first end of the active area  802  and a last gate structure  106   d  disposed along a second end of the active area  802  opposing the first end. The first gate structure  106   a  and the last gate structure  106   d  are outermost gate structures (i.e., are at opposing ends of a series of gate structures over the active area  802 ). The first gate structure  106   a  is separated from the last gate structure  106   d  by way of a plurality of central gate structures  106   b - 106   c . In some embodiments, the first gate structure  106   a  and the last gate structure  106   d  may have different shapes than the plurality of central gate structures  106   b - 106   c.    
     For example, in some embodiments the first gate structure  106   a  may wrap around first source/drain contact  104   a  along a continuous path that extends between a first end  1001   a  disposed along a first side of first source/drain contact  104   a  and a second end  1001   b  disposed along the first side of first source/drain contact  104   a . The first end  1001   a  is separated from the second end  1001   b  by a non-zero distance  1003  (e.g., so that the first gate structure  106   a  is in the shape of a “C”). In some embodiments, the first gate structure  106   a  and/or the last gate structure  106   d  may have ends comprising sidewalls that define a first opening  1002  along an outer edge of the first gate structure  106   a  and/or the last gate structure  106   d , which faces away from the active area  802 . Because there is a first opening  1002  along an outer edge of the first gate structure  106   a  and/or the last gate structure  106   d , the first gate structure  106   a  and/or the last gate structure  106   d  extend part way, but not completely, around a first source/drain contact  104   a  and/or a last source/drain contact  104   d , respectively. In contrast, the central gate structures  106   b - 106   c  extend completely around first source/drain contacts,  104   b  and  104   c , in closed and continuous loops. 
     In some embodiments, the second source/drain contact  108  may also have sidewalls that define a second opening  1004  along an outer edge of the second source/drain contact  108 , which faces away from the active area  802 . Because there is a second opening  1004  along an outer edge of the second source/drain contact  108 , the second source/drain contact  108  extends part way, but not completely, around the first source/drain contact  104   a  and/or the last source/drain contact  104   d . In contrast, the second source/drain contact  108  extends completely around first source/drain contacts,  104   b  and  104   c , in closed and continuous loops. 
     In some embodiments, the first opening  1002  and the second opening  1004  may have substantially equal sizes. In other embodiments, the plurality of gate structures  106   a - 106   d  and the second source/drain contact  108  may define openings that have different sizes. By having openings with different sizes, a size of the transistor device can be changed and a leakage of the transistor device can be varied. For example, as shown in top-view  1006  of  FIG.  10 B , the first gate structure  106   a  and the last gate structure  106   d  may have a first opening  1002  that is smaller than a second opening  1008  within the second source/drain contact  108 . By having the second opening  1008  larger than the first opening  1002 , leakage between the plurality of first source/drain contacts  104   a - 104   d  and the second source/drain contact  108  can be further reduced. In yet other embodiments, shown in top-view  1010  of  FIG.  10 C , the second source/drain contact  108  may have an opening  1012  along outer edges, while the first gate structure  106   a  and the last gate structure  106   d  extend in closed loops (i.e., so that the first gate structure and the last gate structure do not have an opening). 
       FIGS.  11 A- 11 B  illustrate some embodiments of integrated chips having a transistor device comprising field plates wrapped around source/drain contacts.  FIG.  11 A  illustrates a cross-sectional view  1100  of the integrated chip taken along line A-A′ of  FIG.  11 B .  FIG.  11 B  illustrates a top-view  1104  of the integrated chip taken along line B-B′ of  FIG.  11 A . For ease of illustration, the passivation layer  604  has been omitted from top-view  1104 . 
     As shown in cross-sectional view  1100  of  FIG.  11 A , the integrated chip comprises a transistor device having a plurality of first source/drain contacts  104   a - 104   c  and a plurality of gate structures  106   a - 106   c  disposed over a stacked substrate  102 . The plurality of gate structures  106   a - 106   c  are interleaved between the plurality of first source/drain contacts  104   a - 104   c  along the first direction  110 . A second source/drain contact  108  is disposed over the stacked substrate  102  and continuously wraps around the plurality of gate structures  106   a - 106   c  and the plurality of first source/drain contacts  104   a - 104   c.    
     A plurality of field plates  1102   a - 1102   c  are disposed over the stacked substrate  102  between the plurality of first source/drain contacts  104   a - 104   c  and the second source/drain contact  108 . In some embodiments, the plurality of field plates  1102   a - 1102   c  may be located between the plurality of first source/drain contacts  104   a - 104   c  and the plurality of gate structures  106   a - 106   c . In some such embodiments, the plurality of first source/drain contacts  104   a - 104   c  may comprise a plurality of drain contacts and the second source/drain contact  108  may comprise a source contact, so that the plurality of field plates  1102   a - 1102   c  are between the plurality of gate structures  106   a - 106   c  and the plurality of drain contacts. In other embodiments, the plurality of field plates  1102   a - 1102   c  may be located between the plurality of gate structures  106   a - 106   c  and the second source/drain contact  108 . In some such embodiments, the plurality of first source/drain contacts  104   a - 104   c  may comprise a plurality of source contacts and the second source/drain contact  108  may comprise a drain contact, so that the plurality of field plates  1102   a - 1102   c  are between the plurality of gate structures  106   a - 106   c  and the drain contact. 
     In some embodiments, the plurality of field plates  1102   a - 1102   c  may be electrically coupled to the plurality of gate structures  106   a - 106   c . In other embodiments (not shown), the plurality of field plates  1102   a - 1102   c  may be electrically coupled to the plurality of first source/drain contacts  104   a - 104   c  or the second source/drain contact  108 . In some embodiments, the plurality of field plates  1102   a - 1102   c  may be disposed laterally adjacent to the plurality of gate structures  106   a - 106   c  and/or the plurality of first source/drain contacts  104   a - 104   c . In other embodiments, the plurality of field plates  1102   a - 1102   c  may be located higher in a back-end of the line (BEOL) stack. For example, the plurality of field plates  1102   a - 1102   c  may be located on an interconnect layer that is over ILD layer  124 . 
     As shown in top-view  1104  of  FIG.  11 B , the plurality of field plates  1102   a - 1102   c  wrap around the plurality of first source/drain contacts  104   a - 104   c  so as to extend past opposing sides of the first source/drain contacts  104   a - 104   c  along the first direction  110  and along the second direction  112 . In some embodiments, the plurality of field plates  1102   a - 1102   c  wrap around the plurality of first source/drain contacts  104   a - 104   c  in closed loops. 
       FIGS.  12 A- 21    illustrate some embodiments of a method of forming an integrated chip having a high electron mobility (HEMT) device comprising gate structures wrapped around first source/drain contacts. Although  FIGS.  12 A- 21    are described in relation to a method, it will be appreciated that the structures disclosed in  FIGS.  12 A- 21    are not limited to such a method, but instead may stand alone as structures independent of the method. 
     As shown in cross-sectional view  1200  of  FIG.  12 A  and top-view  1206  of  FIG.  12 B , an epitaxial stack  1202  is formed over a base substrate  116  to define a stacked substrate  102 . In some embodiments, the epitaxial stack  1202  may comprise an active layer  120  formed over the base substrate  116 , a barrier layer  122  formed on the active layer  120 , and a doped semiconductor layer  1204  formed on the barrier layer  122 . In some embodiments, the epitaxial stack  1202  may further comprise a buffer layer  118  formed onto the base substrate  116  prior to the formation of the active layer  120 . 
     In various embodiments, the base substrate  116  may comprise silicon, silicon carbide, sapphire, or the like. In some embodiments, the active layer  120  may comprise gallium nitride (GaN), gallium arsenide (GaAs), or the like. In some embodiments, the barrier layer  122  may comprise aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), or the like. In some embodiments, the buffer layer  118  may comprise GaN (having different concentrations of Ga and N than the active layer  120 ), GaAs (having a different concentrations of Ga and As than the active layer  120 ), or the like. In some embodiments, the buffer layer  118 , the active layer  120 , the barrier layer  122 , and the doped semiconductor layer  1204  may be epitaxially grown onto the base substrate  116  by way of chemical vapor deposition processes, physical vapor deposition processes, and/or the like. 
     As shown in cross-sectional view  1300  of  FIG.  13 A  and top-view  1306  of  FIG.  13 B , the doped semiconductor layer ( 1204  of  FIGS.  12 A- 12 B ) may be selectively patterned according to a first masking layer  1302 . Patterning the doped semiconductor layer results in a doped semiconductor material  602  having a plurality of interior sidewalls that define a plurality of cavities  1308  that extends through the doped semiconductor material  602 . In some embodiments, the plurality of interior sidewalls extend along closed and unbroken paths that surrounds the plurality of cavities  1308 . In some embodiments, the doped semiconductor layer may be selectively patterned by exposing the doped semiconductor layer to a first etchant  1304  according to the first masking layer  1302 . In some embodiments, the first masking layer  1302  may comprise a photosensitive material (e.g., photoresist). In various embodiments, the first etchant  1304  may comprise a wet etchant or a dry etchant. 
     As shown in cross-sectional view  1400  of  FIG.  14 A  and top-view  1410  of  FIG.  14 B , the epitaxial stack  1202  may be selectively patterned according to a second masking layer  1402  to form a plurality of first source/drain recesses  1404  and a second source/drain recess  1406 . In some embodiments, the plurality of first source/drain recesses  1404  and the second source/drain recess  1406  may extend through the barrier layer  122  and into the active layer  120 . In some embodiments, the epitaxial stack  1202  may be selectively patterned by exposing the epitaxial stack  1202  to a second etchant  1408  according to the second masking layer  1402 . In some embodiments, the second masking layer  1402  may comprise a photosensitive material (e.g., photoresist). In various embodiments, the second etchant  1408  may comprise a wet etchant or a dry etchant. 
     As shown in cross-sectional view  1500  of  FIG.  15 A  and top-view  1502  of  FIG.  15 B , a conductive material is formed within the plurality of first source/drain recesses  1404  to define a plurality of first source/drain contacts  104   x  over the stacked substrate  102 . The conductive material is also formed within the second source/drain recess  1406  to define a second source/drain contact  108  over the stacked substrate  102 . The second source/drain contact  108  wraps around the plurality of first source/drain contacts  104   x  as a continuous structure. In various embodiments, the conductive material may comprise a metal, such as aluminum, tungsten, titanium, cobalt, or the like. In some embodiments, the conductive material may be formed by a deposition process (e.g., CVD, PVD, sputtering, PE-CVD, or the like) and/or a plating process (e.g., an electroplating process, an electro-less plating process, or the like). In some embodiments, a planarization process (e.g., a chemical mechanical planarization process) may be performed after forming the conductive material. 
     In some alternative embodiments (not shown), the plurality of first source/drain contacts  104   x  and the second source/drain contact  108  may be formed over a topmost surface of the barrier layer  122  without forming the plurality of first source/drain recesses and the second source/drain recess. In such embodiments, the plurality of first source/drain contacts  104   x  and the second source/drain contact  108  have bottommost surfaces that are over the barrier layer  122 . 
     As shown in cross-sectional view  1600  of  FIG.  16 A  and top-view  1602  of  FIG.  16 B , a passivation layer  604  is formed over the plurality of first source/drain contacts  104   x , the second source/drain contact  108 , and the stacked substrate  102 . In various embodiments, the passivation layer  604  may comprise an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. In some embodiments, the passivation layer  604  may be formed by a deposition process (e.g., CVD, PVD, sputtering, PE-CVD, or the like). 
     As shown in cross-sectional view  1700  of  FIG.  17 A  and top-view  1706  of  FIG.  17 B , in some embodiments, an active area  802  is defined within the stacked substrate  102  after depositing the passivation layer  604 . The active area  802  is defined to contain the plurality of first source/drain contacts  104   x  and the second source/drain contact  108 . In some embodiments, the active area  802  may be defined by selectively implanting ions  1702  into the stacked substrate  102  according to a third masking layer  1704 . The implanted ions damage the layers of the stacked substrate  102  to define an isolation region  804  that surrounds and defines the active area  802 . The damage to the layers prevents a 2DEG from extending into the isolation region  804 . In some embodiments, the third masking layer  1704  may comprise a photosensitive material (e.g., photoresist). 
     As shown in cross-sectional view  1800  of  FIG.  18 A  and top-view  1808  of  FIG.  18 B , the passivation layer  604  is selectively patterned to define openings  1802  extending through the passivation layer  604  and exposing the doped semiconductor material  602 . In some embodiments, the passivation layer  604  may be selectively patterned by exposing the passivation layer  604  to a third etchant  1806  according to a fourth masking layer  1804 . In some embodiments, the fourth masking layer  1804  may comprise a photosensitive material (e.g., photoresist). In various embodiments, the third etchant  1806  may comprise a wet etchant or a dry etchant. 
     As shown in cross-sectional view  1900  of  FIG.  19 A  and top-view  1904  of  FIG.  19 B , a gate contact material  1902  is formed in the openings  1802  in the passivation layer  604  and over the fourth masking layer  1804 . In some embodiments, the gate contact material  1902  may comprise a metal such as aluminum, tungsten, cobalt, titanium, or the like. In some embodiments, the gate contact material  1902  may be formed by a deposition process (e.g., CVD, PVD, sputtering, PE-CVD, or the like) and/or a plating process (e.g., an electroplating process, an electro-less plating process, or the like). In some embodiments, a planarization process (e.g., a chemical mechanical planarization process) may be performed after forming the gate contact material  1902 . 
     As shown in cross-sectional view  2000  of  FIG.  20 A  and top-view  2002  of  FIG.  20 B , the gate contact material ( 1902  of  FIGS.  19 A- 19 B ) is patterned to define a gate contact  210 . The gate contact  210  and the doped semiconductor material  602  collectively define a plurality of gate structures  106   x  that wrap around the plurality of first source/drain contacts  104   x . The second source/drain contact  108  wraps around the plurality of gate structures  106   x.    
     As shown in cross-sectional view  2100  of  FIG.  21   , plurality of conductive contacts  126  are formed within an inter-level dielectric (ILD) layer  124  over the stacked substrate  102 . In some embodiments, the plurality of conductive contacts  126  may be formed by way of a damascene process. In such embodiments, an ILD layer  124  is formed over the stacked substrate  102 . The ILD layer  124  is etched to form contacts holes, which are subsequently filled with a conductive material (e.g., tungsten, copper, and/or aluminum). A chemical mechanical planarization (CMP) process is subsequently performed to remove excess of the conductive material from over the ILD layer  124 . 
       FIG.  22    illustrates a flow diagram of some embodiments of a method  2200  of forming an integrated chip having a HEMT device comprising gate structures wrapped around first source/drain contacts. 
     While the disclosed methods (e.g., methods  2200  and  3000 ) are illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
     At  2202 , an epitaxial stack is formed over a base substrate. The epitaxial stack comprises an active layer over the base substrate, a barrier layer over the active layer, and a doped semiconductor layer over the barrier layer.  FIGS.  12 A- 12 B  illustrate a cross-sectional view  1200  and a top-view  1206  of some embodiments corresponding to act  2202 . 
     At act  2204 , the doped semiconductor layer within the epitaxial stack is patterned to define cavities extending through a doped semiconductor material.  FIGS.  13 A- 13 B  illustrate a cross-sectional view  1300  and a top-view  1306  of some embodiments corresponding to act  2204 . 
     At act  2206 , a plurality of first source/drain contacts are formed over the epitaxial stack and within the cavities.  FIGS.  14 A- 15 B  illustrate cross-sectional views,  1400  and  1500 , and top-views,  1410  and  1502 , of some embodiments corresponding to act  2206 . 
     At act  2208 , a second source/drain contact is formed over the epitaxial stack and continuously surrounding the plurality of first source/drain contacts.  FIGS.  14 A- 15 B  illustrate cross-sectional views,  1400  and  1500 , and top-views,  1410  and  1502 , of some embodiments corresponding to act  2208 . 
     At act  2210 , a passivation layer is formed over the plurality of first source/drain contacts, the second source/drain contact, and the epitaxial stack.  FIGS.  16 A- 16 B  illustrate a cross-sectional view  1600  and a top-view  1602  of some embodiments corresponding to act  2210 . 
     At act  2212 , an active area is defined in the epitaxial stack, in some embodiments. The active area surrounds the plurality of first source/drain contacts, the second source/drain contact, and the doped semiconductor material.  FIGS.  17 A- 17 B  illustrate a cross-sectional view  1700  and a top-view  1706  of some embodiments corresponding to act  2212 . 
     At act  2214 , the passivation layer is patterned to define openings exposing the doped semiconductor material.  FIGS.  18 A- 18 B  illustrate a cross-sectional view  1800  and a top-view  1808  of some embodiments corresponding to act  2214 . 
     At act  2216 , a gate contact material is formed in the openings in the passivation layer.  FIGS.  19 A- 19 B  illustrate a cross-sectional view  1900  and a top-view  1904  of some embodiments corresponding to act  2216 . 
     At act  2218 , the gate contact material is patterned to define a plurality of gate structures that wrap around the plurality of first source/drain contacts.  FIGS.  20 A- 20 B  illustrate a cross-sectional view  2000  and a top-view  2002  of some embodiments corresponding to act  2218 . 
     At act  2220 , one or more conductive contacts are formed within an inter-level dielectric (ILD) layer formed over the epitaxial stack.  FIG.  21    illustrates a cross-sectional view  2100  of some embodiments corresponding to act  2220 . 
       FIGS.  23 A- 29    illustrate some embodiments of a method of forming an integrated chip having a MISFET (metal-insulator-semiconductor field effect transistor) device comprising gate structures wrapped around first source/drain contacts. Although  FIGS.  23 A- 29    are described in relation to a method, it will be appreciated that the structures disclosed in  FIGS.  23 A- 29    are not limited to such a method, but instead may stand alone as structures independent of the method. 
     As shown in cross-sectional view  2300  of  FIG.  23 A  and top-view  2302  of  FIG.  23 B , an epitaxial stack  1202  is formed over a base substrate  116  to define a stacked substrate  102 . In some embodiments, the epitaxial stack  1202  may comprise an active layer  120  formed over the base substrate  116  and a barrier layer  122  formed on the active layer  120 . In some embodiments, the epitaxial stack  1202  may also comprise a buffer layer  118  formed onto the base substrate  116  prior to the formation of the active layer  120 . 
     As shown in cross-sectional view  2400  of  FIG.  24 A  and top-view  2406  of  FIG.  24 B , the epitaxial stack  1202  may be selectively patterned according to a first masking layer  2402  to form a plurality of first source/drain recesses  1404  and a second source/drain recess  1406 . In some embodiments, the plurality of first source/drain recesses  1404  and the second source/drain recess  1406  may extend through the barrier layer  122  and into the active layer  120 . In some embodiments, the epitaxial stack  1202  may be selectively patterned by exposing the epitaxial stack  1202  to a first etchant  2404  according to the first masking layer  2402 . In some embodiments, the first masking layer  2402  may comprise a photosensitive material (e.g., photoresist). In various embodiments, the first etchant  2404  may comprise a wet etchant or a dry etchant. 
     As shown in cross-sectional view  2500  of  FIG.  25 A  and top-view  2502  of  FIG.  25 B , a conductive material is formed within the plurality of first source/drain recesses  1404  and the second source/drain recess  1406  to define a plurality of first source/drain contacts  104   x  and a second source/drain contact  108 . In various embodiments, the conductive material may comprise a metal, such as aluminum, tungsten, titanium, cobalt, or the like. In some alternative embodiments (not shown), the plurality of first source/drain contacts  104   x  and the second source/drain contact  108  may be formed over the barrier layer  122  without forming the one or more source contact recesses and the drain contact recess. 
     As shown in cross-sectional view  2600  of  FIG.  26 A  and top-view  2604  of  FIG.  26 B , an active area  802  is defined within the stacked substrate  102 , in some embodiments. In some embodiments, the active area  802  may be defined by selectively implanting ions  1702  into the stacked substrate  102  according to a second masking layer  2602 . The implanted ions damage the layers of the stacked substrate  102  to define an isolation region  804  that surrounds and defines the active area  802 . The damage to the layers prevents a 2DEG from extending into the isolation region  804 . In some embodiments, the second masking layer  2602  may comprise a photosensitive material (e.g., photoresist). 
     As shown in cross-sectional view  2700  of  FIG.  27 A  and top-view  2704  of  FIG.  27 B , a gate dielectric layer  2702  and a gate contact material  1902  are formed over the stacked substrate  102 . In various embodiments, the gate dielectric layer  2702  may comprise an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), or the like. In various embodiments, the gate contact material  1902  may comprise doped polysilicon, a metal (e.g., aluminum, titanium, cobalt, tungsten, or the like), or the like. In some embodiments, the gate dielectric layer  2702  may be formed by deposition processes (e.g., CVD, PVD, sputtering, PE-CVD, or the like). In some embodiments, the gate contact material  1902  may be formed by deposition processes (e.g., CVD, PVD, sputtering, PE-CVD, or the like) and/or a plating process (e.g., an electroplating process, an electro-less plating process, or the like). 
     As shown in cross-sectional view  2800  of  FIG.  28 A  and top-view  2806  of  FIG.  28 B , the gate dielectric layer ( 2702  of  FIG.  27 A ) and the gate contact material ( 1902  of  FIG.  27 A ) are selectively patterned to define a plurality of gate structures  106   x  that wrap around the plurality of first source/drain contacts  104   x . The plurality of gate structures  106   x  respectively comprise an insulating material  702  and a gate contact  210  over the insulating material  702 . In some embodiments, the gate dielectric layer ( 2702  of  FIG.  27 A ) and the gate contact material ( 1902  of  FIG.  27 A ) may be selectively patterned by exposing the gate dielectric layer and the gate contact material to a second etchant  2804  according to a third masking layer  2802 . In some embodiments, the third masking layer  2802  may comprise a photosensitive material (e.g., photoresist). In various embodiments, the second etchant  2804  may comprise a wet etchant or a dry etchant. 
     As shown in cross-sectional view  2900  of  FIG.  29   , a plurality of conductive contacts  126  are formed within an inter-level dielectric (ILD) layer  124  formed over the stacked substrate  102 . In some embodiments, the plurality of conductive contacts  126  may respectively be formed by way of a damascene process. 
       FIG.  30    illustrates a flow diagram of some embodiments of a method  3000  of forming an integrated chip having a MISFET device comprising gate structures wrapped around first source/drain contacts. 
     At act  3002 , an epitaxial stack is formed over a substrate. The epitaxial stack comprises an active layer and a barrier layer over the active layer.  FIGS.  23 A- 23 B  illustrate a cross-sectional view  2300  and a top-view  2302  of some embodiments corresponding to act  3002 . 
     At act  3004 , a plurality of first source/drain contacts are formed over the epitaxial stack.  FIGS.  24 A- 25 B  illustrate cross-sectional views,  2400  and  2500 , and top-views,  2406  and  2502 , of some embodiments corresponding to act  3004 . 
     At act  3006 , a second source/drain contact is formed over the epitaxial stack and surrounding the plurality of first source/drain contacts.  FIGS.  24 A- 25 B  illustrate cross-sectional views,  2400  and  2500 , and top-views,  2406  and  2502 , of some embodiments corresponding to act  3006 . 
     At act  3008 , an active area is defined in the epitaxial stack and surrounding the plurality of first source/drain contacts and the second source/drain contact.  FIGS.  26 A- 26 B  illustrate a cross-sectional view  2600  and a top-view  2604  of some embodiments corresponding to act  3008 . 
     At act  3010 , a gate dielectric layer is formed over the epitaxial stack.  FIGS.  27 A- 27 B  illustrate a cross-sectional view  2700  and a top-view  2704  of some embodiments corresponding to act  3010 . 
     At act  3012 , a gate contact material is formed over the gate dielectric.  FIGS.  27 A- 27 B  illustrate a cross-sectional view  2700  and a top-view  2704  of some embodiments corresponding to act  3012 . 
     At act  3014 , the gate contact material and the gate dielectric layer are patterned to define a plurality of gate structures that wrap around the plurality of first source/drain contacts.  FIGS.  28 A- 28 B  illustrate a cross-sectional view  2800  and a top-view  2806  of some embodiments corresponding to act  3014 . 
     At act  3016 , one or more conductive contacts are formed within an inter-level dielectric (ILD) layer formed over the epitaxial stack.  FIG.  29    illustrates a cross-sectional view  2900  of some embodiments corresponding to act  3016 . 
     Accordingly, in some embodiments, the present disclosure relates to a high-voltage transistor device comprising a gate structure that is configured to provide for improved isolation between source/drain contacts. The gate structure wraps around a first source/drain contact and a second source/drain contact that wraps around the gate structure. Because the gate structure is able to disrupt an underlying two-dimensional electron gas (2DEG) within the substrate, having the gate structure wrap around the first source/drain contact disrupts the 2DEG along a closed and unbroken path surrounding the first source/drain contact. 
     In some embodiments, the present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate; a plurality of gate structures disposed over the substrate between the plurality of first source/drain contacts, the plurality of gate structures wrapping around the plurality of first source/drain contacts in a plurality of closed loops; and a second source/drain contact disposed over the substrate between the plurality of gate structures, the second source/drain contact continuously wrapping around the plurality of gate structures as a continuous structure. In some embodiments, the second source/drain contact includes a plurality of loops having interior sidewalls defining a plurality of openings that respectively surround one of the plurality of first source/drain contacts and one of the plurality of gate structures. In some embodiments, the second source/drain contact includes a plurality of loops respectively defined by a curved sidewall of the second source/drain contact. In some embodiments, the transistor device further includes an isolation region disposed within the substrate and defining an active area, the plurality of first source/drain contacts, the plurality of gate structures, and the second source/drain contact disposed directly over the active area. In some embodiments, the plurality of first source/drain contacts are separated along a first direction; and the active area has a first width and a second width larger than the first width, the first width and the second width measured along a second direction that is perpendicular to the first direction. In some embodiments, the plurality of gate structures are separated along a first direction; and the second source/drain contact continuously extends in the first direction past outermost ones of the plurality of gate structures. In some embodiments, the plurality of first source/drain contacts are source contacts and the second source/drain contact is a drain contact. In some embodiments, the plurality of gate structures include a first gate structure that wraps around a first source/drain contact of the plurality of first source/drain contacts; and the first gate structure continuously extends between a first end disposed along a first side of the first source/drain contact and a second end disposed along the first side of the first source/drain contact, the first end separated from the second end by a non-zero distance. In some embodiments, the substrate includes an active layer disposed over a base substrate; a barrier layer disposed over the active layer, a two-dimensional electron gas (2DEG) being present at an interface of the active layer and the barrier layer; and the plurality of gate structures are configured to disrupt the 2DEG along a plurality of closed paths extending around the plurality of first source/drain contacts. In some embodiments, the second source/drain contact includes a first closed loop surrounding a first gate structure of the plurality of gate structures and a second loop surrounding a second gate structure of the plurality of gate structures; and the second loop does not extend completely around the second gate structure. 
     In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a substrate having an active layer and a barrier layer over the active layer; a plurality of first source/drain contacts disposed over the active layer and separated along a first direction; a plurality of gate structures disposed over the active layer and extending around the plurality of first source/drain contacts along continuous and unbroken paths; and a second source/drain contact that is separated from the plurality of first source/drain contacts by the plurality of gate structures. In some embodiments, the plurality of gate structures include interior sidewalls defining a plurality of openings that extend through the plurality of gate structures and that surround the plurality of first source/drain contacts in closed loops. In some embodiments, the second source/drain contact extends as a continuous structure around the plurality of gate structures. In some embodiments, the second source/drain contact includes a first loop extending completely around a first gate structure of the plurality of gate structures and a second loop that extends part way, but not entirely, around a second gate structure of the plurality of gate structures. In some embodiments, the integrated chip further includes an isolation region disposed within the substrate and defining an active area, the active area having curved edges that are conformal to curved sidewalls of the second source/drain contact. In some embodiments, the active area has a length along the first direction and a width along a second direction that is perpendicular to the first direction, the length larger than the width. In some embodiments, the integrated chip further includes a field plate arranged between the second source/drain contact and a first source/drain contact of the plurality of first source/drain contacts, the field plate extending in a closed loop surrounding the first source/drain contact. In some embodiments, the second source/drain contact includes interior sidewalls defining a plurality of openings extending through the second source/drain contact, the plurality of openings disposed in a first row extending along the first direction and in a second row extending along the first direction and separated from the first row along a second direction that is perpendicular to the first direction. 
     In yet other embodiments, the present disclosure relates to a method of forming a transistor device. The method includes forming a plurality of first source/drain contacts over a stacked substrate; forming a second source/drain contact over the stacked substrate, the second source/drain contact continuously wrapping around the plurality of first source/drain contacts; and forming a plurality of gate structures over the stacked substrate, the plurality of gate structures laterally between the plurality of first source/drain contacts and the second source/drain contact. In some embodiments, the plurality of gate structures wrap around the plurality of first source/drain contacts along a plurality of continuous and unbroken paths; and the second source/drain contact wraps around the plurality of gate structures along a continuous and unbroken path. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.