Patent Publication Number: US-11380411-B2

Title: Threshold voltage drift tracking systems and methods

Description:
BACKGROUND 
     This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light and not as admissions of prior art. 
     Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. One or more memory devices may be used on a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuitry. For example, based on a user input to the computing system, the processing circuitry may request that a memory module retrieve data corresponding to the user input from its memory devices. In some instances, the retrieved data may include firmware, or instructions executable by the processing circuitry to perform an operation and/or may include data to be used as an input for the operation. In addition, in some cases, data output from the operation may be stored in memory, such as to enable subsequent retrieval of the data from the memory. 
     Some of the memory devices include memory cells that may be accessed by turning on a transistor that couples the memory cell (e.g., a capacitor) with a wordline or a bitline. In contrast, threshold-type memory devices include memory devices that are accessed by providing a voltage across a memory cell, where the data value is stored based on the threshold voltage of the memory cell. For example, the data value may be based on whether the threshold voltage of the memory cell is exceeded and, in response to a sense voltage provided across the memory cell, the memory cell conducts current, which may be measured to determine the logical state of the memory cell. The data value stored may be changed, such as by applying a voltage sufficient to change the physical/electrical properties of the memory cell (e.g., at or above the threshold corresponding to the desired state). Examples of a threshold-type memory cell may include, but are not limited to, cross-point memory cells or chalcogenide memory cells (e.g., phase change memory (PCM), programmable metallization cell (PMC) memory, etc.). 
     With threshold-type memories, the threshold voltage may shift over time (e.g., a time since the most recent read or write). As such, an approach that tracks the shift in threshold voltage and/or the time since the most recent read or write operation may be desired. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which: 
         FIG. 1  is a block diagram of a portion of a memory device, in accordance with an embodiment; 
         FIG. 2  is a diagram of the portion of the memory device of  FIG. 1 , in accordance with an embodiment; 
         FIG. 3  is a graph of example sense voltages in relation to Set and Reset threshold voltage distributions, in accordance with an embodiment; 
         FIG. 4  is a block diagram of example memory block assignments in a memory array, in accordance with an embodiment; 
         FIG. 5  is a block diagram of age tracking circuitry, in accordance with an embodiment; 
         FIG. 6  is a flowchart of an example process for writing new data to the memory array and assigning an age register to keep track of the age of the data, in accordance with an embodiment; and 
         FIG. 7  is a schematic diagram of a portion of the memory device of  FIG. 1  applying the age tracking circuitry of  FIG. 5  in read and/or write operations, in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. One or more specific embodiments of the present embodiments described herein will be described below. In an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. 
     Memories generally include an array of memory cells with each memory cell coupled to at least two access lines. For example, a memory cell may be coupled to a bitline and a wordline. As such, each access line may be coupled to a large number of memory cells. To select a memory cell, a decoder circuit associated with a first access line for the memory cell and a decoder circuit associated with a second access line for the memory cell may both provide a voltage and/or a current on the respective access lines. By applying voltages/currents to the respective access lines, the memory cell may be accessed, such as to write data to the memory cell and/or read data from the memory cell. 
     In some embodiments, a threshold-type memory may utilize materials (e.g., chalcogenide glass) that change properties based on an applied threshold voltage. In other words, threshold-type memory device materials may be “Set” or “Reset” by applying particular voltages. In some embodiments, phase-changing memory (PCM) may store the data value by altering a state of the memory material. For example, the Set of a memory cell may place the phase-changing material in a first state (e.g., a crystalline state), and the Reset of the memory cell may place the phase-changing material in another state (e.g., an amorphous state). As should be appreciated, the definition of Sets and Resets may vary by convention. Furthermore, the change in state may correspond to a change of electrical properties (e.g., resistivity) of the memory cell. The current state of the memory cell, and therefore the data value of the memory cell (e.g., a logic value such as “0” or “1”), may be determined by an application of a sense voltage across the memory cell. The differing electrical properties of the phase-change material in its respective states may yield different current flows across the memory cell in response to the applied voltage. For example, when the voltage differential across the memory cell (e.g., the sense voltage or demarcation voltage) is applied, the current flow may correspond to the Set or Reset resistivity of the memory cell, and, as such, the measured current flow may be used to determine the data value of the memory cell. 
     Moreover, threshold-type memory devices may utilize programmable metallization cells (PMC) that exhibit a change in electrical properties (e.g., resistivity) in response to different applied threshold voltages, which may be of opposite polarity. For example, a PMC may be programmed as a Set by applying a first voltage at or above a Set threshold voltage, and programmed as a Reset by applying a second voltage (corresponding to a Reset threshold voltage) with an opposite polarity (e.g., negative polarity) relative to the first voltage. Similar to PCM, PMCs may exhibit an increase or decrease in resistivity based on the applied voltages. For example, when the sense voltage is applied, the current flow may correspond to the Set or Reset resistivity of the memory cell, and, as such, the measured current flow may be used to determine the data value of the memory cell. 
     The threshold voltages may define reference voltages that, when a voltage is applied across a memory cell above (or below depending on circumstances and implementation) a respective threshold, cause a memory cell to be programmed as a Set or Reset. As should be appreciated, different materials may have different threshold voltages, and some Sets or Resets may have thresholds bound on either end, such as in some PCM. In some scenarios, Set and/or Reset threshold voltages (e.g., voltage differentials as taken across the memory cell) may vary from cell to cell, for example, due to non-uniformity in hardware, material, or previously applied voltages (e.g., during reads and/or writes). As such, the threshold voltages for each of the Sets and Resets may be considered as voltage distributions with the sense voltage (e.g., an applied voltage for reading a Set or Reset) generally between the voltage distributions and used to read the logical state of the memory cell. 
     Additionally, in some scenarios, the threshold voltage distributions for Sets and/or Resets may shift over time (e.g., a time since a previous read or write). For example, the electrical properties of the memory cell may change based on the time since a previous operation (e.g., a read or write), which may alter the threshold voltage. The shift in threshold voltage distributions means that the threshold voltage for some memory cells, when read, may have shifted to the point where the applied sense voltage changes the state of the memory cell, which may lead to an improperly interpreted data value. 
     In some embodiments, to compensate for the shift in threshold voltage distributions over time, the amount of time since the previous operation (e.g., a read or write) may be tracked (e.g., via multiple registers), and the sense voltage may be adjusted based on the amount of time elapsed. Moreover, the memory bank may be segmented into multiple blocks, each corresponding to a set of memory addresses. For example, a register may be assigned a memory block such that after the memory block is written, the register keeps track of the age of the data in the memory block. To read the memory cell, the register corresponding to the memory address of the memory cell may be referenced, and an appropriate sense voltage may be selected based on the age of the data. Furthermore, additional electrical parameters such as pre-read voltages, biasing currents, and selection/programming voltages may also be adjusted based on the age of the data. Although discussed above as relating to phase-change memory and programmable metallization cells, the techniques discussed herein may be applied to any suitable memory device where the threshold voltage shifts over time and/or where the time since a previous operation is of interest. 
     With the foregoing in mind,  FIG. 1  is a block diagram of a portion of a memory device  100 . The memory device  100  may be any suitable form of memory, such as non-volatile memory (e.g., a cross-point memory) and/or volatile memory. The memory device  100  may include one or more memory cells  102 , one or more bitlines  104  (e.g.,  104 - 0 ,  104 - 1 ,  104 - 2 ,  104 - 3 ), one or more wordlines  106  (e.g.,  106 - 0 ,  106 - 1 ,  106 - 2 ,  106 - 3 ), one or more wordline decoders  108  (e.g., wordline decoding circuitry), and one or more bitline decoders  110  (e.g., bitline decoding circuitry). The memory cells  102 , bitlines  104 , wordlines  106 , wordline decoders  108 , and bitline decoders  110  may form a memory array  112 . 
     Each of the memory cells  102  may include a selector and/or a storage element. When a voltage across a selector of a respective memory cell reaches a threshold, the storage element may be accessed to read a data value from and/or write a data value to the storage element. In some embodiments, each of the memory cells  102  may not include a separate selector and storage element, and have a configuration such that the memory cell nonetheless acts as having a selector and storage element (e.g., may include use of a material that behaves both like a selector material and a storage element material). When memory cells  102  have a single material that functions as a selector and storage element, these architectures may leverage single material (e.g., chalcogenide) process architectures and may have respective values set within each memory cell by leveraging positive signals (e.g., positive voltages, positive currents) to set a logic high value in the memory cell and by leveraging negative signals or lower voltage signals (e.g., negative voltages, negative currents) to clear a logic high value or set a logic low value in the memory cell. Single material process architectures may use bipolar decoders (e.g., driving circuitry) to access the memory cell during a memory operation. In some cases, unipolar decoders may be used, such as when a neutral mid-point between a positive signal level and a negative signal level is shifted to equal half a voltage difference between the bitlines  104  and wordlines  106 . 
     For ease of discussion,  FIG. 1  may be discussed in terms of bitlines  104 , wordlines  106 , wordline decoders  108 , and bitline decoders  110 , but these designations are non-limiting. The scope of the present disclosure should be understood to cover memory cells  102  that are coupled to multiple access lines and accessed through respective decoders, where an access line may be used to store data into a memory cell and read data from the memory cell. 
     The bitline decoders  110  may be organized in multiple groups of decoders. For example, the memory device  100  may include a first group of bitline decoders  114  (e.g., multiple bitline decoders  110 ) and/or a second group of bitline decoders  116  (e.g., different group of multiple bitline decoders  110 ′). Similarly, the wordline decoders  108  may also be arranged into groups of wordline decoders  108 , such as a first group of wordline decoders  118  and/or a second group of wordline decoders  120 . Decoders may be used in combination with each other to drive the memory cells  102  (e.g., such as in pairs and/or pairs of pairs on either side of the wordlines  106  and/or bitlines  104 ). For example, bitline decoder  110 - 3  may operate in conjunction with bitline decoder  110 ′- 3  and/or with wordline decoders  108 - 0 ,  108 ′- 0  to select the memory cell  102 A. As may be appreciated herein, decoder circuitry on either ends of the wordlines  106  and/or bitlines  104  may be different. Additionally, it is noted that the depicted components of the memory device  100  may include additional circuitry not shown and/or may be disposed in any suitable arrangement. For example, a subset of the wordline decoders  108  and/or bitline decoders  110  may be disposed on different sides of the memory array  112  and/or on a different physical side of any plane including the circuitries. 
     The memory device  100  may also include a control circuit  122 . The control circuit  122  may communicatively couple to respective wordline decoders  108  and/or bitline decoders  110  to perform memory operations by, for example, causing the decoding circuitry (e.g., a subset of the wordline decoders  108  and/or bitline decoders  110 ) to generate selection signals (e.g., selection voltage and/or selection currents) for programming a target of the memory cells. In some embodiments, a positive voltage and a negative voltage may be provided on one or more of the bitlines  104  and/or wordlines  106 , respectively, to a target of the memory cells  102 . In some embodiments, the decoder circuits may provide electrical pulses (e.g., voltage and/or current) to the access lines to access the memory cell. The electrical pulse may be a square pulse, or in other embodiments, other shaped pulses may be used. In some embodiments, a voltage provided to the access lines may be a constant voltage. 
     Activating the decoder circuits may enable the delivery of an applied voltage (e.g., an electrical pulse) to the target of the memory cells  102  such that the control circuit  122  is able to access data storage of the target memory cell, such as to read from or write to the memory cell. After a target of the memory cells  102  is accessed, data may be read or written. Writing to the target memory cell may include changing the data value stored by the target memory cell. As previously discussed, the data value stored by a memory cell may be based on a threshold voltage. In some embodiments, a memory cell may be Set to have a logical “0”, or may be Reset to have a logical “1” depending on convention. In some embodiments, a Set memory cell may have a lower threshold voltage than a Reset memory cell, however, as should be appreciated, convention of logical values and/or convention of how voltage polarity is determined (e.g., either positive or negative) may be implementation specific and does not limit the present disclosure. Regardless of convention, by Setting or Resetting a memory cell, different data values may be stored by the memory cell. Reading a target of the memory cells  102  may include determining whether the target memory cell was characterized by the first threshold voltage and/or by the second threshold voltage by sensing a current flow in response to an applied sense voltage across the memory cell  102 . During programming (e.g., writing), the threshold voltage for a particular memory cell (e.g., memory cell  102 A) may be reached by applying programming pulses with either positive or negative polarity to the memory cell  102 A and reading the memory cell  102 A using a signal with a given (e.g., known) fixed polarity. 
       FIG. 2  is a diagram illustrating a portion of a memory array  130  in accordance with an embodiment of the present disclosure. The memory array  130  may be a cross-point array including wordlines  106  (e.g.,  106 - 0 ,  106 - 1 , . . . ,  106 -N) and bitlines  104  (e.g.,  104 - 0 ,  104 - 1 , . . . ,  104 -M). A memory cell  102  may be located at each of the intersections of the wordlines  106  and bitlines  104 . The memory cells  102  may function in a two-terminal architecture (e.g., with a particular of the wordlines  106  and the bitlines  104  serving as the electrodes for a particular of the memory cells  102 ). 
     Each of the memory cells  102  may be resistance variable memory cells, such as resistive random-access memory (RRAM) cells, conductive-bridging random access memory (CBRAM) cells, phase-change memory (PCM) cells, and/or spin-transfer torque magnetic random-access memory (STT-RAM) cells, among other types of memory cells. Each of the memory cells  102  may include a memory element (e.g., memory material) and a selector element (e.g., a select/storage material (SD)) and/or a material layer that functionally replaces a separate memory element layer and selector element layer. The selector element (e.g., SD material) may be disposed between a wordline contact and a bitline contact associated with a wordline or bitline forming the memory cell. Electrical signals may transmit between the wordline contact and the bitline contact when reading or writing operations are performed to the memory cell. 
     The selector element may be a diode, a non-ohmic device (NOD), or a chalcogenide switching device, among others, or formed similar to the underlying cell structure. The selector element may include, in some examples, selector material, a first electrode material, and a second electrode material. The memory element of memory cell  102  may include a memory portion of the memory cell  102  (e.g., the portion programmable to different states). For instance, in resistance variable memory cells  102 , a memory element can include the portion of the memory cell having a resistance that is programmable to particular levels corresponding to particular states responsive to applied programming voltage and/or current pulses. In some embodiments, the memory cells  102  may be characterized as threshold-type memory cells that are selected (e.g., activated) based on a voltage and/or current crossing a threshold associated with the selector element and/or the memory element. Embodiments are not limited to a particular resistance variable material or materials associated with the memory elements of the memory cells  102 . For example, the resistance variable material may be a chalcogenide formed of various doped or undoped chalcogenide-based materials. Other examples of resistance variable materials that may be used to form storage elements include binary metal oxide materials, colossal magnetoresistive materials, and/or various polymer-based resistance variable materials, among others. 
     In operation, the memory cells  102  may be programmed by applying a voltage (e.g., a write voltage) across the memory cells  102  via selected wordlines  106  and bitlines  104 . A sensing (e.g., read) operation may be performed to determine a state of one or more memory cells  102  by sensing current or voltage. For example, the current/voltage may be sensed on one or more bitlines  104  corresponding to the respective memory cells  102  in response to a particular voltage applied to the selected of the wordlines  106  forming the respective memory cells  102 . 
     As illustrated, the memory array  130  may be arranged in a cross-point memory array architecture (e.g., a three-dimensional (3D) cross-point memory array architecture) that extends in any direction (e.g., x-axis, y-axis, z-axis). The multi-deck cross-point memory array  130  may include a number of successive memory cells (e.g.,  102 B,  102 C,  102 D) disposed between alternating (e.g., interleaved) decks of wordlines  106  and bitlines  104 . The number of decks may be expanded in number or may be reduced in number and should not be limited to the depicted volume or arrangement. Each of the memory cells  102  may be formed between wordlines  106  and bitlines  104  (e.g., between two access lines), such that a respective one of the memory cells  102  may be directly electrically coupled with (e.g., electrically coupled in series) with its respective pair of the bitlines  104  and wordlines  106  and/or formed from electrodes (e.g., contacts) made by a respective portion of metal of a respective pair of bitlines  104  and wordlines  106 . For example, the memory array  130  may include a three-dimensional matrix of individually-addressable (e.g., randomly accessible) memory cells  102  that may be accessed for data operations (e.g., sense and write) at a granularity as small as a single storage element and/or multiple storage elements. As should be appreciated, the memory array  130  may include more or less bitlines  104 , wordlines  106 , and/or memory cells  102  than shown in the examples of  FIG. 2 . 
     As discussed above, in some scenarios, Set and/or Reset threshold voltages may vary, for example, due to non-uniformity in hardware, the applied voltages (e.g., during reads and/or writes), and/or the material of the memory cell  102 . Additionally, the threshold voltage distributions for Sets and/or Resets may shift over time (e.g., a time since a previous read or write). To help illustrate,  FIG. 3  is a graph  140  of Set voltage distributions  142  and Reset voltage distributions  144  at three separate ages (e.g., Set voltage distributions  142 - 1 ,  142 - 2 , and  142 - 2  at times T 1 , T 2 , and T 3 , respectively, and Reset voltage distributions  144 - 1 ,  144 - 2 , and  144 - 3  at times T 1 , T 2 , and T 3 , respectively). The graph  140  includes voltage  146  on the x-axis and standard deviation  148  from a mean threshold voltage level  150  for a given time on the y-axis. 
     Continuing with  FIG. 3 , the mean threshold voltage level  150  may be representative of the mean threshold voltage for a Set or Reset for a given age (e.g., a time since the most recent write) of the data. In further illustration, the Set voltage distribution  142 - 1  for a memory cell  102  at a first time T 1  since the data was written to the memory cell  102  may have a mean voltage level  150 , represented as voltage V 1 , and vary between voltage V 2  and voltage V 3  for a given standard deviation  148  (e.g., a standard deviation between σ 1  and σ 2 ). Similarly, the Reset voltage distribution  144 - 1  at time T 1  may vary between voltage V 4  and voltage V 5  with a mean voltage level  150  at voltage V 6 . In general, the sense voltage (e.g., SV 1 ) may be disposed between the Set voltage distributions  142  (e.g., Set voltage distribution  142 - 1 ) and Reset voltage distributions  144  (e.g., Reset voltage distribution  144 - 1 ) for a given time (e.g., time T 1 ). 
     In some scenarios, the Set voltage distributions  142  and Reset voltage distributions  144  for may experience a voltage drift  152  over time (e.g., a time since a previous read or write), for example, as a result of the material properties of the memory cell  102 , temperature, and/or additional factors (e.g., environmental factors, manufacturing factors, etc.). In some scenarios, the voltage drift  152  in the Set voltage distributions  142  (e.g., from Set voltage distribution  142 - 1  at time T 1  to Set voltage distribution  142 - 3  at time T 3 ) may cause a portion  154  of the Set voltage distribution  142  to shift past the sense voltage (e.g., sense voltage SV 1 ). The portion  154  of the Set voltage distribution  142  shifted past the sense voltage (e.g., sense voltage SV 1 ) may statistically correspond to a portion of the memory cells  102  that, when read, may be improperly interpreted as a Reset instead of a Set. As such, in accordance with present embodiments, facilitating a sense voltage shift  156  based on the age of the data, may facilitate proper interpretation of the data in the memory cells  102 . 
     In some embodiments, to compensate for the shift in Set voltage distributions  142  and Reset voltage distributions  144  over time, the amount of time since a previous operation (e.g., a read or write) may be tracked (e.g., via registers, a processor, the control circuit  122 , or a combination thereof), and the sense voltage SV 1  may be adjusted based on the amount of time elapsed. For example, at time T 1  the first sense voltage SV 1  may be used, and at time T 3  a second sense voltage SV 2  may be used to minimize or eliminate the portion  154  of potentially improperly interpreted memory cells  102 . As should be appreciated, the graph  140  is depicted as an illustrative tool, and may not be to scale. Additionally, the mean voltage level  150 , Set voltage distributions  142 , and/or Reset voltage distributions  144  may be linear or non-linear and may vary based on implementation (e.g., material properties, applied voltages, ambient/operating temperature, etc.). 
     In addition to helping reduce the probability of improperly interpreting memory cells  102  (e.g., during read operations), keeping track of the age of the data and tracking the voltage drift  152  may also be used during write operations. For example, the voltage used for a pre-read may undergo sense voltage shift  156 , and may use the same or different sense voltages (e.g., SV 1  or SV 2 ) as those during read operations. Additionally, the age of the data may be used to determine increased or decreased selection voltages (e.g., for applying voltages at respective threshold voltages for a Set or Reset). For example, as time progresses and the voltage drift  152  increases, the memory cell may require a higher selection voltage in order to access or program the memory cell  102  due to the shifted threshold voltage. In some scenarios, this phenomenon may be more pronounced in the Reset case, as the Reset was programmed with a higher voltage than a Set or, in some embodiments, a positive voltage relative to a negative voltage for the Set. Additionally, if it is known that a very short period of time has elapsed since the previous operation (e.g., a read and/or write operation) the selection voltage may be decreased or held constant relative to the increased selection voltage for older data, which may provide power savings and/or generate less heat. 
     In some scenarios, it may not be feasible to track the age of the data for each memory cell  102  individually. As such, the memory array  130  may be divided into multiple memory blocks  160  that each include a subset of the memory addresses  162  of the memory array  130 , as shown in  FIG. 4 . Moreover, the memory blocks  160  may be of any suitable size and may vary in size from one memory block  160  to the next. Furthermore, memory blocks  160  may transcend other memory allotments such as partitions  164 . For example, the memory blocks  160  may make up a full partition  164  (e.g., Memory Block 1 and Partition 3 correspond to the same memory addresses  162 ), a portion of a partition  164  (e.g., Memory Block 0 is less than the full Partition 1), and/or span multiple partitions  164  (e.g., Memory Block 2 spans across Partition 1 and Partition 2). 
     Tracking of the age of the data may occur on the memory device  100  and/or a memory controller of a computing system interfacing with the memory device  100 . Moreover, as discussed herein, control circuitry governing and/or implementing the age tracking may be accomplished on-die (e.g., of the memory device  100 ), via a computing system coupled to the memory device  100  (e.g., via a processor or other circuitry), or a combination thereof. In some embodiments, implementing age tracking circuitry  170 , as in  FIG. 5 , on the memory device  100  may yield increased bandwidth between the memory device  100  and the computing system. Additionally, in some embodiments, streamlining the determination of what sense voltage (e.g., sense voltage SV 1  or SV 2 ) to use (e.g., using on-die age tracking circuitry) may increase operational efficiency and/or increased speed of the memory device  100  and/or a computing device coupled thereto. The age tracking circuitry  170  may include multiple age registers  172 , to track the age of the data for each memory block  160 , and clock circuitry  174  to increment the age stored in the age registers  172  as time progresses. Additionally, each age register  172  may have one or more corresponding shadow registers  176  to keep track of which memory addresses  162  correspond to which age registers  172 . As time progresses (e.g., periodically), time increments  178 , generated by the clock circuitry  174 , may update the age registers  172  to increase the tracked age of the data of the corresponding memory block  160 . 
     Furthermore, memory blocks  160  may be assigned and reassigned regardless of order. In other words, as different sections of the memory array  130  are written to, the age registers  172  may be assigned on-the-fly to maintain accurate data ages. For example, if data is written to a portion of the memory array  130 , the memory device  100  or the computing system interfaced therewith may assign an age register  172  to the memory addresses  162  corresponding to that portion of the memory array  130 . To keep track of which memory addresses  162  correspond to the age register  172 , the memory addresses  162 , or a representation thereof, may be stored in the shadow register  176  corresponding to the age register  172 . 
     In some embodiments, the memory addresses  162  of the corresponding memory block  160  may include a contiguous set of memory addresses  162  with a single start address  180  and a single end address  182 . As should be appreciated, however, in some embodiments, a memory block  160  may include multiple sub-blocks of memory addresses  162  that may be non-consecutive. For example, a memory block  160  corresponding to a single age register  172  may include a first set (e.g., sub-block) of consecutive memory addresses  162  and a second set of consecutive memory addresses  162  without including memory addresses  162  between the first set and the second set of memory addresses  162 . As such, multiple shadow registers  176 , corresponding to the age register  172  of the memory block  160 , may store the start addresses  180  and end addresses  182  of the sub-blocks. Additionally, the age registers  172  may be reassigned to maintain an accurate age of the data as new data is written and old data is no longer needed. Reassignment of the age registers  172  may include merging or splitting of memory blocks  160 . For example, when new data is to be written to the memory array  130 , the control circuit  122  of the memory device  100  or the computing system may assign a particular age register  172  memory addresses  162  that encompass or overlap one or more previously defined memory blocks  160  corresponding to the particular age register  172  and/or additional age registers  172 . As such, the start addresses  180  and end addresses  182  of the previously defined memory blocks  160  may be adjusted to make way for the new memory block  160  of the new data. If an age register  172  is not assigned a memory block  160  (e.g., its previous memory block  160  was overtaken by another memory block) it may enter an idle state and the corresponding shadow register(s)  176  may be reset or cleared. 
     The number of age registers may correspond to the size of the memory array  130  as well as other implementation factors (e.g., estimated size of the average write, estimated write frequency, etc.). Recycling/reassignment of the age registers  172  as discussed above, may help reduce the number of age registers  172  in a particular implementation. Additionally, if additional age registers  172  are desired, the control circuit  122  of the memory device  100  or the computing system may refresh (e.g., rewrite) the data of multiple consecutive memory blocks  160  into a single memory block  160  tracked by a single age register  172  and reassign the unused age registers  172 . Additionally or alternatively, multiple consecutive memory blocks  160  may be merged into a single memory block  160  tracked by a single age register  172  without refreshing the data by averaging the ages of the merged memory blocks  160 . The average may be weighted based on the age and/or the size of the corresponding memory blocks  160 . Additionally, in some embodiments, merging of the memory blocks  160  may be subject to qualifications such as a maximum age of either of memory blocks  160  to be merged and/or a maximum difference between the ages of the memory blocks  160  to be merged. 
     Additionally, when writing or refreshing (e.g., due to a rewrite or read) the data, the age register  172  may be reset or cleared (e.g., via the control circuit  122  of the memory device  100  or the computing system) upon a new assignment so that the age of the data starts at relative zero. From the relative zero age, the ages stored in the age registers  172  may be updated periodically (e.g., at set intervals) via the time increments  178  generated by the clock circuitry  174 . The time increments  178  may be of any suitable granularity (e.g., 1 μs, 1 millisecond (ms), 10 ms, 1 second, 1 minute, etc.) and may be predetermined based on implantation factors such as the material properties of the memory cells  102  and the operating temperature of the memory device  100 . Moreover, the clock circuitry  174  may be part of the age tracking circuitry  170  implemented on-die. Additionally or alternatively, a clock signal may be received from the computing system to form the time increments  178 . In the case of power shutdowns, either intentional or unexpected, the computing system may provide a supplemental time increment  178  based on how long the memory device  100  was without power to maintain accurate ages of the memory blocks  160 . Additionally or alternatively, the memory device  100  may have a supplemental power source (e.g., a battery, a capacitor, etc.) to maintain time increments  178  during power outages and shutdowns. Furthermore, in some embodiments, the memory device  100  or the computing system may periodically backup (e.g., store in memory) age information (e.g., an age value of the age register  172  and/or the memory addresses  162  associated with the age values) to prevent loss of the age information during unexpected power outages. 
       FIG. 6  is a flowchart of an example process  190  for writing new data to the memory array  130  and assigning an age register  172  to keep track of the age of the data. In some embodiments, the incoming data may be written to the memory array  130  (process block  192 ) in series or in parallel with defining a new memory block  160  by storing the memory addresses  162  (e.g., the start address  180  and the end address  182 ) corresponding to the incoming data in one or more shadow registers  176  (process block  194 ). The age register  172  associated with the memory block  160  and shadow registers  176  may be reset or cleared to a reference age (e.g., zero) (process block  196 ). As time progresses, the age register  172  may be updated with time increments (process block  198 ) to track how much time has passed since the data was written. Further, in response to a read and/or write requests, the age register  172  may be referenced to determine the age value of the age register  172  (process block  200 ). The memory device  100  may then perform the read or write operation adjusted based on the age value of the age register  172  (process block  202 ). For example, the sense voltages, pre-read voltages, biasing current of the memory cell  102 , and/or selection/programming voltages may be adjusted base on the age value of the age register. Although the above referenced flowchart is shown in a given order, in certain embodiments, process blocks may be reordered, altered, deleted, and/or occur simultaneously. Additionally, the referenced flowchart is given as an illustrative tool and further decision and process blocks may also be added depending on implementation. 
     As discussed above, during read and/or write operations, it may be advantageous to take into account when the memory cells  102  being accessed were last accessed (e.g., written, read, or refreshed) due to the voltage drift  152 . To help illustrate the application of the age tracking circuitry  170 ,  FIG. 7  is a schematic diagram of a portion  210  of the memory device  100  performing a read and/or write operation. A read/write request  212  to store or access data may be initiated by a computing system coupled to the memory device  100  or internally generated by the memory device  100 , for example, as part of a refresh operation. The requested memory address  214  of the read/write request  212  may be interpreted via memory address lookup circuitry  216  to determine to which memory block  160  the requested memory address  214  belongs. In some embodiments, the memory address lookup circuitry  216  may compare the requested memory address  214  with the memory addresses  162  (e.g., start address  180  and/or end address  182 ) of the shadow registers  176  and reference the corresponding age register  172  to obtain the age value  218  of the memory cell  102  at the requested memory address  214 . For example, if the requested memory address  214  falls between the start address  180  and the end address  182  of the shadow register  176  defining Memory Block 1  160 - 1 , Age Register 1  172 - 1  may be referenced for its stored age value  218 . 
     In some embodiments, the age value  218  obtained from the age register  172  corresponding to the read/write request  212  may be interpreted by drift index circuitry  220  to determine the extent of the operating adjustments to be made during the read/write operations. The drift index circuitry may reference one or more age windows  222  and compare the age value  218  to the age windows  222 . The age windows  222  may correspond to age brackets and relate the age values  218 , which may be bound or unbound, to a set number of discrete drift indices  224 . For example, if the age value  218  is representative of a relatively young age (e.g., 0-10 μs, 0-1 ms, etc.) the age value  218  may fall into a young age window  222 - 0 . The drift index circuitry  220  may output a drift index  224  corresponding to the young age window  222 - 0  utilized by read/write circuitry  226  to set the sense voltage (e.g., sense voltage SV 1 , sense voltage SV 2 , or other sense voltages) at an appropriate level for memory cells  102  with young data. Returning momentarily to  FIG. 3 , as the voltage drift  152  may be relatively minor for memory cells  102  with young data, a base sense voltage (e.g., sense voltage SV 1 ) may be utilized. Moreover, if the age value  218  is representative of a relatively old age (e.g., greater than a threshold age such as 1 hour (hr), 24 hr, 48 hr, etc.) the age value  218  may fall into an old age window  222 - 2 , and a drift index  224  corresponding to the old age window  222 - 2  may be utilized by read/write circuitry  226  to set the threshold voltage at an appropriate level for memory cells  102  with relatively old data. For example, as the voltage drift  152  for relatively old data may be more significant than that of the young data, the sense voltage may be shifted (e.g., to sense voltage SV 2  from sense voltage SV 1 ). Furthermore, any number of intermediate age windows (e.g., age window  222 - 1 ) with corresponding drift indices  224  and intermediate sense voltages (e.g., between sense voltages SV 1  and SV 2 ) may be utilized depending on the desired granularity and implementation. Furthermore, as should be appreciated, the time values discussed herein are given as examples and may depend on implementation (e.g., material properties, temperature, operating voltages, etc.) and/or desired granularity. 
     Additionally, in some embodiments, the memory device  100  and/or the computing system coupled to the memory device  100  may actively monitor the age values  218  for each of the memory blocks  160 . For example, if a particular age value  218  for a corresponding memory block  160  passes a threshold age value  218 , the memory device  100  may rewrite (e.g., refresh) the data stored in the memory block  160  and reset the associated age register  172 . 
     As discussed above, tracking of the voltage drift  152  may be used to adjust the sense voltages as well as pre-read voltages, biasing currents, and selection/programming voltages. As such, the read/write circuitry  226  may use the drift index  224  as input for any operation where the age of the data and/or age of the last access of the memory cell  102  may be a factor. Additionally or alternatively, the age value  218  may be directly referenced to determine a sense voltage (e.g., sense voltage SV 1 , sense voltage SV 2 , or other sense voltage), pre-read voltage, biasing current, and/or memory cell  102  selection voltage. For example, the age value  218  may be used as a drift index  224  without categorization into an age window  222  either directly, with a granularity corresponding to the time increment  178 , or indirectly, for example based on a formulaic algorithm. 
     With these technical effects in mind, multiple memory devices may be included on a memory module, thereby enabling the memory devices to be communicatively coupled to the processing circuitry as a unit. For example, a dual in-line memory module (DIMM) may include a printed circuit board (PCB) and multiple memory devices. Memory modules respond to commands from a memory controller communicatively coupled to a client device or a host device via a communication network. Or in some cases, a memory controller may be used on the host-side of a memory-host interface; for example, a processor, microcontroller, field programmable gate array (FPGA), application-specific integrated circuit (ASIC), or the like may each include a memory controller. This communication network may enable data communication there between and, thus, the client device to utilize hardware resources accessible through the memory controller. Based at least in part on user input to the client device, processing circuitry of the memory controller may perform one or more operations to facilitate the retrieval or transmission of data between the client device and the memory devices. Data communicated between the client device and the memory devices may be used for a variety of purposes including, but not limited to, presentation of a visualization to a user through a graphical user interface (GUI) at the client device, processing operations, calculations, or the like. Thus, with this in mind, the above-described improvements to memory controller operations and memory writing operations may manifest as improvements in visualization quality (e.g., speed of rendering, quality of rendering), improvements in processing operations, improvements in calculations, or the like. 
     The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure. 
     The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . ” or “step for [perform]ing [a function] . . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).