Patent Publication Number: US-11662627-B2

Title: Liquid crystal display

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of U.S. patent application Ser. No. 14/815,443 filed on Jul. 31, 2015, which claims priority under 35 USC § 119 to Korean Patent Application No. 10-2015-0003670 filed in the Korean Intellectual Property Office on Jan. 9, 2015, the entire contents of which are incorporated herein by reference. 
    
    
     BACKGROUND 
     (a) Field 
     The present disclosure relates to a liquid crystal display. 
     (b) Description of the Related Art 
     A liquid crystal display is a flat panel display that is widely used today, and generally includes two display panels in which electric field generating electrodes, such as a pixel electrode and a common electrode, are disposed, and a liquid crystal layer disposed between the two display panels. An image is displayed by applying a voltage to the electric field generating electrodes to generate an electric field in the liquid crystal layer, thereby determining the alignment of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light by the liquid crystal layer. 
     The liquid crystal display includes switching elements connected to respective pixel electrodes, a plurality of signal lines including gate lines and data lines, and a driver configured to apply a driving signal to the signal lines. By controlling the state of the switching elements through the gate lines, voltages may be applied to the pixel electrodes through the data lines. 
     The driver includes a gate driver for supplying a gate signal including a gate-on voltage Von and a gate-off voltage Voff to the gate lines of a display panel, a data driver for supplying a data signal to the data lines of the display panel, a signal controller for controlling the data driver and the gate driver, and the like. 
     Among liquid crystal displays, a liquid crystal display with a vertically aligned mode has proved to be popular because it provides a relatively large contrast ratio and a wide reference viewing angle. In a liquid crystal display with a vertically aligned mode, the major axis of the liquid crystal molecules are aligned to be perpendicular to a planar surface of the display panels when an electric field is not applied. 
     A method for forming cutouts, such as fine slits, in the field generating electrode is used to provide the wide viewing angle in the liquid crystal display with a vertically aligned mode. Since the cutouts and protrusions determine the direction in which the liquid crystal molecules are tilted (tilt direction), it is possible to increase a viewing angle by appropriately arranging the cutouts and protrusions so that the liquid crystal molecules are tilted in various directions. 
     The above information disclosed in this Background section is only for enhancement of understanding of the background of the system and method and therefore may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. 
     SUMMARY 
     The present system and method provide a liquid crystal display having advantages of minimizing optical loss and suppressing the occurrence of textures even when the display panels are misaligned with each other due to their curvature. 
     An exemplary embodiment of the present system and method provides a liquid crystal display including: a first insulation substrate, a thin film transistor disposed on the first insulation substrate, a pixel electrode connected to the thin film transistor, a protrusion disposed on the pixel electrode, a second insulation substrate facing the first insulation substrate, a common electrode disposed on the second insulation substrate, and a liquid crystal layer disposed between the pixel electrode and the common electrode, wherein one pixel includes a thin film transistor formation region where the thin film transistor is disposed and a display area where the pixel electrode is disposed, and the protrusion is disposed to overlay at least a portion of edges of the display area. 
     The pixel electrode may include a plurality of cross-shaped stems, and fine branches obliquely extending from the cross-shaped stems. The display area may comprise a plurality of sub-regions identified by the cross-shaped stems. 
     The protrusion may overlay at least a portion of edges of the sub-regions. 
     The protrusion may include an opening disposed at corners of the edges. 
     The protrusion may include an opening disposed at sides of the edges. 
     The pixel electrode may further include a plate part disposed as the center of the cross-shaped stem. 
     The plate part may have a diamond shape. 
     The liquid crystal display may further include a column spacer disposed on the pixel electrode. The column spacer and the protrusion may be disposed in the same layer and are made of the same material. 
     The protrusion may have a height lower than a height of the liquid crystal layer. 
     The common electrode may have a plate shape. 
     The liquid crystal display may further include alignment layers disposed on the pixel electrode and the common electrode, and the alignment layers disposed on the pixel electrode may further include reactive mesogen (RM). 
     The liquid crystal layer may exclude reactive mesogen (RM). 
     The liquid crystal display may have a curved shape. 
     As described above, according to the above-described liquid crystal display, it is possible to minimize optical loss and suppress occurrence of textures even when a display panel is curved and thus upper and lower panels are misaligned with each other. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram illustrating a display device according to an exemplary embodiment of the present system and method. 
         FIG.  2    is a schematic diagram of two adjacent pixels according to an exemplary embodiment of the present system and method. 
         FIG.  3    is a layout view illustrating a pixel electrode according to an exemplary embodiment of the present system and method. 
         FIG.  4    is a layout view of two adjacent pixels of a liquid crystal display according to an exemplary embodiment of the present system and method. 
         FIGS.  5 ,  6  and  7    are layout views of two adjacent pixels of a liquid crystal display according to another exemplary embodiment of the present system and method. 
         FIG.  8    is a liquid crystal molecule alignment image of a portion of one pixel according to an exemplary embodiment of the present system and method. 
         FIGS.  9 ,  10  and  11    are liquid crystal molecule alignment images of a portion of one pixel according to various exemplary embodiments of the present system and method. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The present system and method are described more fully hereinafter with reference to the accompanying drawings in which exemplary embodiments of the present system and method are shown. Those of ordinary skill in the art would realize that the described embodiments may be modified in various different ways without departing from the spirit or scope of the present system and method. 
     In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like elements throughout the specification. When an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. 
     Hereinafter, a display device according to an exemplary embodiment is described in detail with reference to  FIG.  1   . 
       FIG.  1    is a block diagram illustrating a display device according to an exemplary embodiment of the present system and method. 
     As shown in  FIG.  1   , the display device includes a display panel  300  configured to display an image, a data driver  500  configured to drive the display panel  300 , a gate driver  400 , and a signal controller  600  configured to control the data driver  500  and the gate driver  400 . 
     The display panel  300  includes a plurality of gate lines G 1  to Gn and a plurality of data lines D 1  to Dm+1. The plurality of gate lines G 1  to Gn extend in a horizontal direction, and the plurality of data lines D 1  to Dm+1, which are insulated from the plurality of gate lines G 1  to Gn, extend in a vertical direction to intersect with the plurality of gate lines G 1  to Gn. Also, reference voltage lines V 1  to Vm that extend in a vertical line are disposed between the plurality of data lines D 1  to Dm+1. The reference voltage lines V 1  to Vm are insulated from and intersect with the gate lines G 1  to Gn. 
     Each pixel of a plurality of pixels PX is connected to a corresponding one of the gate lines and a corresponding one of the data lines. The pixels PX are arranged in a matrix form and formed to extend lengthwise in the horizontal direction, which is also the extending direction of the gate lines G 1  to Gn. Each pixel PX may include a thin film transistor, a liquid crystal capacitor, and a storage capacitor. A control terminal of the thin film transistor may be connected to one of the gate lines G 1  to Gn, an input terminal of the thin film transistor may be connected to one of the data lines D 1  to Dm+1, and an output terminal of the thin film transistor may be connected to one terminal (pixel electrode) of the liquid crystal capacitor and one terminal of the storage capacitor. The other terminal of the liquid crystal capacitor may be connected to a common electrode and the other terminal of the storage capacitor may receive a storage voltage Vcst. In some exemplary embodiments, a channel layer of the thin film transistor may be amorphous silicon, polysilicon, or an oxide semiconductor. The reference voltage lines V 1  to Vm provide reference voltages to the pixels PX. The reference voltage has a voltage level that does not vary with time. However, in some exemplary embodiments, the reference voltage may have a voltage level that varies with time. 
     As the exemplary liquid crystal display device of the  FIG.  1    shows, one data line is alternately connected to pixels PX disposed to the right and the left of the data line. For example, when the data line is connected to a pixel PX disposed to its right in a first row, the data line is connected to a pixel PX disposed to its left in a second row, and is again connected to a pixel disposed to its right in a third row. On the other hand, one gate line is connected to all the pixels PX of one row. 
     In such a structure, an odd pixel and an even pixel, both belonging to one pixel column, are connected to different data lines. Thus, even when the data lines D 1  to Dm+1 apply data voltages having the same polarity during one frame, a polarity reversal appearing in a pixel (PX) is represented as a dot reversal. 
     The number of the data lines D 1  to Dm+1 may be one more than the number (m) of pixel columns. In the embodiment of  FIG.  1   , there is no pixel column on the left of a first data line D 1 , and therefore, the first data line D 1  may be alternately connected to the pixel column disposed on the right thereof. There is no pixel column on the right of an (m+1)-th data line Dm+1, and therefore, the (m+1)-th data line Dm+1 may be alternately connected to the pixel column disposed on the left thereof. 
     The signal controller  600  processes input data and control signals that are input from the outside, so as to make them suitable for the operating conditions of the liquid crystal panel  300 , in response to, for example, a vertical synchronization signal Vsync, a horizontal synchronizing signal Hsync, a main clock signal MCLK, a data enable signal DE or the like. Thereafter, the signal controller  600  generates and outputs image data DAT, a gate control signal CONT 1 , a data control signal CONT 2 , and a clock signal. 
     The gate control signal CONT 1  may include a scanning start signal STV that indicates the start of outputting of a gate-on voltage Von, a gate clock signal CPV that controls the output timing of the gate-on voltage Von, and the like. 
     The data control signal CONT 2  may include a horizontal synchronization start signal STH that indicates the start of inputting of image data DAT, a load signal TP that instructs application of the data voltages to the data lines D 1  to Dm+1. 
     The plurality of gate lines G 1  to Gn of the display panel  300  is connected to the gate driver  400 , and the gate driver  400  sequentially receives the gate-on voltage Von according to the gate control signal CONT 1  applied from the signal controller  600 . A gate-off voltage Voff is applied to the gate lines G 1  to Gn during a period in which the gate-on voltage Von is not applied. 
     The plurality of data lines D 1  to Dm+1 of the display panel  300  is connected to the data driver  500 , and the data driver  500  receives the data control signal CONT 2  and the image data DAT from the signal controller  600 . The data driver  500  converts the image data DAT into data voltages by using gray voltages generated by a gray voltage generator (not shown) and transfers the data voltages to the data lines D 1  to Dm+1. The data voltages include a positive-polarity data voltage and a negative-polarity data voltage. The positive-polarity data voltage and the negative-polarity data voltage are alternately applied based on frames, columns, or rows and are used for inversion driving. Such inversion driving is applied to either or both of the case in which a moving image is displayed and the case in which a still image is displayed. 
     In some exemplary embodiments, there may be provided various pixel connection structures that are not shown in  FIG.  1   . 
     A structure of two adjacent pixels PX is schematically described below with reference to  FIG.  2   . 
       FIG.  2    is a schematic diagram of two adjacent pixels according to an exemplary embodiment of the present system and method. 
     The pixel PX according to an exemplary embodiment of the present system and method is a horizontal pixel that is formed to extend in a horizontal direction. Also, the pixel PX mainly includes a thin film transistor formation region TA and a display area DA. A pixel electrode is disposed in the display area DA where an image is displayed through the liquid crystal molecules. An element, such as a thin film transistor that transfers a voltage to be applied to the pixel electrode in the display area DA, and wirings are formed in the thin film transistor formation region TA. 
     As  FIG.  2    shows, a reference voltage line V is disposed in a vertical direction along the center of the display area DA. Also, each of the two adjacent pixels PX 1  and PX 2  includes a first subpixel area PXa and a second subpixel area PXb that are arranged in two rows. 
     Each of the first subpixel area PXa and the second subpixel area PXb includes six sub-regions. The sub-regions are separate from each other by dotted lines in  FIG.  2   . That is, each of the two pixels PX 1  and PX 2  includes 12 sub-regions in total. Also, the reference voltage line V is disposed to divide the 12 sub-regions into two sets of 6 sub-regions. That is, the reference voltage line V is disposed to traverse the center of the first subpixel area PXa and the second subpixel area PXb. 
     Each of the sub-regions includes one cross-shaped stem, based on which the sub regions are identified. Although each of the pixels shown in the exemplary embodiment of  FIG.  2    is described as including 12 sub-regions, the present system and method are not limited thereto. Any number of sub-regions is possible. 
     Also, each of the first subpixel area PXa and the second subpixel area PXb includes six unit electrodes UP corresponding to the six sub-regions. The area of a unit electrode UP in the second subpixel area PXb may be equal to or larger than the area of a unit electrode in the first subpixel area PXa. Also, a voltage applied to the second subpixel area PXb may be lower than a voltage applied to the first subpixel area PXa. 
     Also, the gate line  121  extends between the two adjacent pixels PX 1  and PX 2  in the horizontal direction. Specifically, the gate line  121  extends between the second subpixel area PXb of pixel PX 1  and the first subpixel area PXa of adjacent pixel PX 2  in the horizontal direction. 
     A structure of a pixel electrode and a reference voltage line V in a pixel PX according to an exemplary embodiment of the present system and method is described below with reference to  FIG.  3   . 
       FIG.  3    is a layout view illustrating a pixel electrode according to an exemplary embodiment of the present system and method. 
     A pixel electrode disposed in one pixel PX includes a first subpixel electrode  191   a  disposed in the first subpixel area PXa and a second subpixel electrode  191   b  disposed in the second subpixel area PXb. 
     Each of the first subpixel electrode  191   a  and the second subpixel electrode  191   b  includes six unit pixel electrodes UP corresponding to six sub-regions. Each of the unit pixel electrodes UP includes a cross-shaped stem  198  and a plurality of fine branches  199  obliquely extending from the cross-shaped stem  198 . The plurality of fine branches  199  may be formed at an angle of 45 degrees, an angle equal to or larger than 40 degrees, or an angle equal to or smaller than 50 degrees with respect to the horizontal direction or the vertical direction. 
     The six unit pixel electrodes UP of the first subpixel electrode  191   a  are connected to each other through an extension part. Likewise, the six unit pixel electrodes UP of the second subpixel electrode  191   b  are connected to each other through an extension part. In the exemplary embodiment of  FIG.  3   , the cross-shaped stems  198  are formed to be in contact with sides of a region where the unit pixel electrodes are formed. 
     The extension part of the unit pixel electrodes UP may extend from the cross-shaped stem  198 . The six pixel electrodes UP that are connected by the extension part receive the same voltage. While the unit pixel electrodes of the same subpixel electrode are connected to one another through the extension part, unit pixel electrodes of different subpixel electrodes are separate from and not connected to each other. 
     An upper common electrode of one sub-region where the unit pixel electrodes UP are disposed is formed to have a plate shape, which is a plane shape that does not include an opening region. 
     The reference voltage line V is disposed to traverse the center of the first subpixel electrode  191   a  and the second subpixel electrode  191   b.    
     An overall structure of a pixel having a pixel electrode, a common electrode, and a reference voltage line is described with reference to  FIG.  4   . 
       FIG.  4    is a diagram showing a detailed structure of the pixel according to the exemplary embodiment of  FIG.  3   , and shows a layout view of two adjacent pixels of a liquid crystal display according to an exemplary embodiment of the present system and method. 
     Referring to  FIG.  4   , the liquid crystal display according to an exemplary embodiment of the present system and method includes a lower display panel and an upper display panel that face each other, and a liquid crystal layer disposed between the two panels. 
     First, as to the lower panel, a plurality of gate lines  121  is disposed on the lower panel. 
     The gate lines  121  extend among a plurality of pixel electrodes  191  in the horizontal direction, and include a first gate electrode  124   a , a second gate electrode  124   b , and a third gate electrode  124   c  that protrude upward (orientation as shown in  FIG.  4   ) and extend from the gate lines  121 . The first gate electrode  124   a , the second gate electrode  124   b , and the third gate electrode  124   c  are formed such that the third gate electrode  124   c  extends upward from the gate lines  121  and then expands, and the first gate electrode  124   a  and the second electrode  124   b  extend again from the third gate electrode  124   c . The first gate electrode  124   a  and the second gate electrode  124  may be formed in one expanded region. Also, the gate lines  121  may include a bent portion that is bent from a main line extending in a substantially horizontal direction at periodic intervals. 
     A gate insulating layer is disposed on the gate lines  121 . A first semiconductor  154   a , a second semiconductor  154   b , and a third semiconductor  154   c  are disposed respectively on the first gate electrode  124   a , the second gate electrode  124   b , and the third gate electrode  124   c.    
     A data conductor including a data line  171 , a first drain electrode  175   a , a second drain electrode  175   b , a third source electrode  173   c , a third drain electrode  175   c , and a reference voltage line  178  is disposed on the first semiconductor  154   a , the second semiconductor  154   b , and the third semiconductor  154   c , and the gate insulating layer. 
     The data line  171  transfers a data voltage, substantially extends in the vertical direction on a lower substrate, and intersects with the gate lines  121 . The data line  171  includes a source electrode  173   a  and a second source electrode  173   b  that respectively extend toward the first and second gate electrodes  124   a  and  124   b.    
     The reference voltage line  178  may include a main line  178   a  substantially parallel to the data line  171  and a branch portion  178   b  extending from the main line  178   a  and substantially parallel to the gate lines  121 . The branch portion  178   b  extends to the thin film formation region TA along the edges of the display area, and one end of the branch  178   b  forms the third drain electrode  175   c.    
     The first drain electrode  175   a  faces the first source electrode  173   a , the second drain electrode  175   b  faces the second source electrode  173   b , and the third drain electrode  175   c  faces the third source electrode  173   c . The third source electrode  173   c  is connected to the second drain electrode  175   b.    
     The first gate electrode  124   a , the first source electrode  173   a , the first drain electrode  175   a , and the first semiconductor  154   a  together form a first thin film transistor. The second gate electrode  124   b , the second source electrode  173   b , the second drain electrode  175   b , and the second semiconductor  154   b  together form a second thin film transistor. The third gate electrode  124   c , the third source electrode  173   c , the third drain electrode  175   c , and the third semiconductor  154   c  together form a third thin film transistor. That is, the first thin film transistor and the second thin film transistor receive a data voltage through their source electrodes, whereas the third thin film transistor receives a reference voltage through its source electrode. 
     A passivation layer is disposed on the data conductor, and a pixel electrode  191  is disposed on the passivation layer. 
     Each pixel electrode includes a first subpixel electrode  191   a  and a second subpixel electrode  191   b  as described with reference to  FIG.  3   . 
     The first drain electrode  175   a  of the first thin film transistor is connected to the first subpixel electrode  191   a  through a first contact hole  185   a.    
     The second drain electrode  175   b  of the second thin film transistor is connected to the second subpixel electrode  191   b  through a second contact hole  185   b.    
     A protrusion  260  is disposed on the subpixel electrodes  191   a  and  191   b . The protrusion  160  may be disposed along the edges of the display area, which are the edges of the subpixel electrodes  191   a  and  191   b , or may be disposed along the edges of the unit electrodes UP in one pixel. 
     The height of the protrusion  260  according to an exemplary embodiment of the present system and method may be formed to be lower than the height of the liquid crystal layer disposed between the upper panel and the lower panel. 
     The protrusion  260  formed along the edges of the display area and the unit electrodes controls the alignment of the liquid crystal molecules disposed in the display area and the unit electrodes, thereby providing improved controllability liquid crystal over the liquid crystal molecules. In particular, the protrusion  260  makes it possible to align the liquid crystal molecules in the same direction as the liquid crystal molecules aligned by the fine branches  199 . 
     Although the protrusion is shown as overlapping the edges of the display area and the reference voltage line in the exemplary embodiment of  FIG.  4   , the present system and method are not limited thereto, and the protrusion may be selectively formed at the edges of unit electrodes. 
     In some exemplary embodiments, a column spacer (not shown) may be disposed on the pixel electrodes  191   a  and  191   b . The column spacer may maintain a gap between the upper panel and the lower panel according to a height. The column spacer may be formed of the same material and through the same process as the protrusion  260 . Therefore, the column spacer and the protrusion may be disposed in the same layer. 
     Next, a color filter and a light blocking member may be disposed on the upper panel (not shown). 
     The light blocking member may be called a black matrix, and may block light leakage between the pixel electrodes  191 . The light blocking member may cover most of the data line  171 , the gate lines  121 , and the thin film transistors. 
     The color filter may display one of several primary colors, such as three primary colors of red, green, and blue. According to another exemplary embodiment of the present system and method, at least one of the light blocking member and the color filter may be disposed in the lower panel. 
     An overcoat is disposed on the color filter and the light blocking member, and an upper common electrode is disposed on the overcoat. The upper common electrode, which receives a common voltage Vcom, may be formed to have a plate shape as described with reference to  FIG.  3   . 
     The liquid crystal layer disposed between the lower panel and the upper panel includes liquid crystal molecules having negative dielectric anisotropy. That is, the liquid crystal molecules may be aligned such that a main axis thereof is substantially perpendicular to surfaces of the two panels when an electric field is not being applied. The liquid crystal layer may not include reactive mesogen (RM). 
     Although not shown, the liquid crystal display according to an exemplary embodiment of the present system and method includes a first alignment layer and a second alignment layer disposed on the pixel electrode and the common electrode. In this case, the first alignment layer and the second alignment layer may be different from each other. As an example, the alignment layer disposed on the pixel electrode may further include reactive mesogen (RM). 
     Although the color filter and the light blocking member are described above as being disposed in the upper panel, the present system and method are not limited thereto, and one of the color filter and the light blocking member may be disposed in the lower panel, or both of the color filter and the light blocking member may be disposed in the lower panel. 
     The liquid crystal display according to an exemplary embodiment of the present system and method may have a curved shape, and as a result, the upper and lower panels may be misaligned with each other. According to exemplary embodiments of the present system and method, the common electrode disposed on the upper panel is formed to have a plate shape and the protrusion, which assists the alignment of the liquid crystal molecules, is disposed in the lower panel. In this manner, the alignment of the liquid crystal molecules is easily controlled despite the misalignment. Therefore, exemplary embodiments of the present system and method make it possible to suppress texture generation and provide a display device having improved display quality. 
     Hereinafter, other embodiments of the present system and method are described with reference to  FIGS.  5  to  7   .  FIGS.  5  to  7    are layout views of two adjacent pixels of a liquid crystal display according to other exemplary embodiments of the present system and method. The liquid crystal display according to the exemplary embodiments of  FIGS.  5  and  6    is identical to the above-described exemplary embodiment of  FIG.  4    except for the shape and arrangement of the protrusion. The liquid crystal display according to the embodiment of  FIG.  7    differs from that of  FIG.  4    in the structure of the subpixel electrodes  191   a  and  192   b . To avoid redundancy of description, the description of the same or similar elements is omitted. 
     First, referring to  FIG.  5   , a protrusion  260  is disposed on subpixel electrodes  191   a  and  191   b . The protrusion  260  may be disposed along the edges of the display area, which are the edges of the subpixel electrodes  191   a  and  191   b , or may be disposed along the edges of the unit electrodes UP in one pixel. 
     The protrusion  260  according to another exemplary embodiment of the present system and method may include openings disposed at its corners. Specifically, the protrusion  260  formed along the edges of the display area or the unit electrodes may have a rectangular plane shape and may be formed such that portions of the protrusion  260  at the corners are removed or not formed in the rectangular shape. This protrusion structure allows the liquid crystal molecules to easily move through the openings during a process of manufacturing the liquid crystal display. 
     The height of the protrusion  260  according to an exemplary embodiment of the present system may be formed to be lower than the height of the liquid crystal layer disposed between the upper panel and the second panel. 
     The protrusion  260  formed along the edges of the display area and the unit electrodes controls the alignment of the liquid crystal molecules disposed in the display area and the unit electrodes, thereby providing improved controllability over the liquid crystal molecules. In particular, the protrusion makes it possible to align the liquid crystal molecules in the same direction as the liquid crystal molecules aligned by the fine branches  199 . 
     Although the protrusion is shown as overlapping the edges of the display area and the reference voltage line in the exemplary embodiment, the present system and method are not limited thereto, and the protrusion may be selectively formed at the edges of unit electrodes. 
     Referring to  FIG.  6   , unlike the exemplary embodiment of  FIG.  5   , the protrusion  260  may include openings disposed at its edges instead of its corners. 
     The protrusion  260  is formed along the edges of the display area or the sub-regions and may have a rectangular plane shape. In this case, portions of the sides of the rectangular plane shape may be removed or not formed so as to be opened. The openings make movement of the liquid crystal molecules easy during the process of manufacturing the liquid crystal display, while the protrusion  260  is still able to assist in controlling the alignment of the liquid crystal molecules. 
     Referring to  FIG.  7   , the pixel electrode  191  may include a first subpixel electrode  191   a  and a second subpixel electrode  191   b  that are disposed within one pixel PX. 
     Each of the first subpixel electrode  191   a  and the second subpixel electrode  191   b  includes six unit pixel electrodes UP corresponding to six sub-regions. Each of the unit pixel electrodes UP includes a plate part  197  and a plurality of fine branches  199  extending outward from the sides of the plate part  197 . The plurality of fine branches  199  may be formed at an angle of 45 degrees with respect to the horizontal direction or the vertical direction or may be formed at an angle equal to or larger than 40 degrees or an angle equal to or smaller than 50 degrees. Also, the fine branches  199  may extend perpendicularly from the sides of the plate part  197 . Controllability of the liquid crystal molecules is enhanced through fringe fields generated at the sides of the edges of the plate part  197 , thereby further increasing the transmittance of the liquid crystal display. 
     The six unit pixel electrodes of the first subpixel electrode  191   a  are connected to each other through an extension part. Similarly, the six unit pixel electrodes of the second subpixel electrode  191   b  are connected to each other through an extension part. Although the plate part  197  is illustrated as having a size in which the plate part  197  is in contact with the sides of a region where the unit pixel electrodes are formed, the plate part  197  may be formed to be smaller. In such case, the fine branches  199  may also be disposed at the corners of the plate part  197 . The extension part of the unit pixel electrodes UP may extend from the plate part  197  or may extend from the fine branches  199 . The six pixel electrodes UP that are connected by the extension part receive the same voltage. While the respective unit pixel electrodes of the same subpixel electrode are connected to one another through the extension part, unit pixel electrodes of different subpixel electrodes are separate from and not connected to each other. 
     The common electrode  270  according to another exemplary embodiment of the present system and method is formed to have a plate shape and does not include a separate pattern or slit. 
     The reference voltage line  178  is disposed to traverse the center of the first subpixel electrode  191   a  and the second subpixel electrode  191   b.    
     A protrusion  260  is disposed on the subpixel electrodes  191   a  and  191   b . The protrusion  260  may be disposed along the edges of the display area, which are edges of the subpixel electrodes  191   a  and  191   b , or may be disposed along the edges of the unit electrodes UP in one pixel. The protrusion  260  according to the various exemplary embodiments described above may be disposed without limitation, for example, in the embodiment of  FIG.  7   . 
     Although the shape of the pixel electrode is specified as illustrated in  FIG.  7   , the present system and method are not limited thereto, and various shapes of the pixel electrode are possible. 
     Hereinafter, liquid crystal alignment images according to embodiments of the present system and method are described with reference to  FIGS.  8  to  10   .  FIG.  8    is a liquid crystal molecule alignment image of a portion of one pixel according to an exemplary embodiment of the present system and method.  FIGS.  9  to  11    are liquid crystal molecule alignment images of a portion of one pixel according to various exemplary embodiment of the present system and method. 
     First, referring to  FIG.  8   , the liquid crystal molecule alignment image of a sub-region shows a cross-shaped stem, a plurality of fine branches extending therefrom, and a protrusion surrounding the edges of the fine branches, according to an exemplary embodiment. 
     As can be seen from  FIG.  9   , the liquid crystal molecules disposed over the fine branches are generally aligned in the direction in which the fine branches extend. Moreover, the liquid crystal molecules disposed around the protrusion are also aligned in the same direction as those liquid crystal molecules aligned by the fine branches. 
     That is, according to an exemplary embodiment of the present system and method, although the influence of the fine branches are weaker near the edges of the sub-regions, the protrusion helps to align the liquid crystal molecules near the edges of the sub-regions in the same direction as the liquid crystal molecules that are disposed over and aligned by the fine branches. 
       FIG.  9    is a liquid crystal molecule alignment image when the height of the protrusion according to an exemplary embodiment of the present system and method is 0.5 μm.  FIG.  10    is a liquid crystal molecule alignment image when the height of the protrusion is 1.0 μm.  FIG.  11    is a liquid crystal molecule alignment image when the height of the protrusion is 1.5 μm. 
     Referring to  FIGS.  9  to  11   , it can be seen that the liquid crystal molecules are aligned along the extension directions of the fine branches around the cross-shaped stem, and in particular, liquid crystal molecules disposed around the edges are aligned in the directions of the cross-shaped stem and the fine branches due to the protrusion disposed at the edges of the sub-regions. 
     That is, as shown in  FIGS.  9  to  11   , the liquid crystal molecules alignment directions due to the protrusion are identical to the liquid crystal molecules alignment directions due to the fine branches and the cross-shaped stem, and more effective liquid crystal control is possible at the edges of the sub-regions by means of the protrusion. 
     As described above, the liquid crystal display according to the exemplary embodiments of the present system and method is capable of effectively controlling liquid crystal molecules by means of the protrusion disposed in the lower panel even in a case in which the common electrode disposed in the upper panel is formed in a plate form. Therefore, it is possible to provide a liquid crystal display having an improved display quality. 
     While the present system and method are described in connection with exemplary embodiments, the present system and method are not limited to the disclosed embodiments. On the contrary, the present system and method cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. 
     
       
         
           
               
             
               
                   
               
               
                 &lt;Description of symbols&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                   
                 121: Gate line 
                 124: Gate electrode 
               
               
                   
                 154: Semiconductor 
                 171: Data line 
               
               
                   
                 173: Source electrode 
                 175: Drain electrode 
               
               
                   
                 178: Reference voltage line 
                 191: Pixel electrode 
               
               
                   
                 198: Cross-shaped stem 
                 199: Fine branch 
               
               
                   
                 400: Gate driver