Patent Publication Number: US-2023163060-A1

Title: Semiconductor package

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2021-0161354 filed on Nov. 22, 2021 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     The present inventive concepts relate to a semiconductor package, and more particularly, to a semiconductor package including bonding pads. 
     A semiconductor package is provided to implement an integrated circuit chip to qualify for use in electronic products. A semiconductor package may be fabricated by mounting a semiconductor chip on a package substrate, and then using bonding wires or bumps to electrically connect the semiconductor chip to the package substrate. For example, a printed circuit board (PCB) may be used as the package substrate. With the development of the electronics industry, various research has been conducted to improve reliability and durability of semiconductor packages. 
     SUMMARY 
     Some embodiments of the present inventive concepts provide a compact-sized semiconductor package. 
     Some embodiments of the present inventive concepts provide a semiconductor package with improved electrical properties and increased reliability. 
     According to some embodiments of the present inventive concepts, a semiconductor package may comprise: a substrate that includes an upper protection layer and a plurality of upper bonding pads; a semiconductor chip on the substrate; and a plurality of bonding wires connected to the semiconductor chip and the upper bonding pads. Each of the upper bonding pads may include: a first conductive pattern; a second conductive pattern that covers a top surface and a sidewall of the first conductive pattern and includes a metal element the same as a metal element of the first conductive pattern; and a bonding layer on the second conductive pattern. A width at the top surface of the first conductive pattern may be less than a width at a bottom surface of the first conductive pattern. The upper protection layer may cover sidewalls of the second conductive pattern. 
     According to some embodiments of the present inventive concepts, a semiconductor package may comprise a substrate that includes an upper protection layer and an upper bonding pad. The upper bonding pad may include: a first conductive pattern; a second conductive pattern on the first conductive pattern; and a bonding layer on the second conductive pattern. A width at a top surface of the first conductive pattern may be less than a width at a bottom surface of the first conductive pattern. The second conductive pattern may cover a sidewall and the top surface of the first conductive pattern. A width at a top surface of the second conductive pattern may be about 90% to about 110% of the width at the bottom surface of the first conductive pattern. The upper protection layer may cover sidewalls of the second conductive pattern. 
     According to some embodiments of the present inventive concepts, a semiconductor package may comprise: a substrate, wherein the substrate includes, a dielectric structure that includes a plurality of stacked dielectric layers, a wiring line between the dielectric layers, a lower pad disposed on a bottom surface of the dielectric structure and electrically connected to the wiring line, an upper bonding pad disposed on a top surface of the dielectric structure and electrically connected to the wiring line, and an upper protection layer on the top surface of the dielectric structure; a solder ball on a bottom surface of the lower pad; a semiconductor chip on a top surface of the substrate; a bonding wire connected to the semiconductor chip and the upper bonding pad; and a molding layer on the substrate, the molding layer covering the semiconductor chip and the bonding wire. The upper bonding pad may include: a first conductive pattern; a second conductive pattern on a top surface of the first conductive pattern, the second conductive pattern including a first metal element the same as a metal element of the first conductive pattern; an intermediate layer on a top surface of the second conductive pattern, the intermediate layer including a second metal element different from the first metal element; and a bonding layer on a top surface of the intermediate layer, the bonding layer including a third metal element different from the first metal element and different from the second metal element. A width at the top surface of the first conductive pattern may be less than a width at a bottom surface of the first conductive pattern. The upper protection layer may cover a sidewall of the second conductive pattern. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates a plan view showing a semiconductor package according to some embodiments. 
         FIG.  2 A  illustrates a cross-sectional view showing a substrate according to some embodiments. 
         FIG.  2 B  illustrates an enlarged view showing section III of  FIG.  2 A . 
         FIG.  2 C  illustrates a cross-sectional view showing upper bonding pads according to some embodiments. 
         FIG.  2 D  illustrates a cross-sectional view showing upper bonding pads and an upper protection layer according to some embodiments. 
         FIG.  2 E  illustrates a cross-sectional view showing upper bonding pads and an upper protection layer according to some embodiments. 
         FIG.  3 A  illustrates a cross-sectional view taken along I-I′ of  FIG.  1   , showing a semiconductor package according to some embodiments. 
         FIG.  3 B  illustrates a cross-sectional view taken along line II-II′ of  FIG.  1   . 
         FIGS.  4 A to  4 G  illustrate cross-sectional views showing a substrate fabrication method according to some embodiments. 
     
    
    
     DETAIL DESCRIPTION 
     In this description, like reference numerals may indicate like components. The following will describe a substrate, a semiconductor package including the same, and a substrate fabrication method according to embodiments of the present inventive concepts. 
       FIG.  1    illustrates a plan view showing a semiconductor package according to some embodiments. 
     Referring to  FIG.  1   , a semiconductor package  10  may include a substrate  100 , a semiconductor chip  200 , and bonding wires  300 . The substrate  100  may be a printed circuit board (PCB), but the present inventive concepts are not limited thereto. When viewed in plan view, the substrate  100  may have a central region and an edge region. The edge region of the substrate  100  may be provided between the central region of the substrate  100  and a lateral surface (e.g., four lateral surfaces) of the substrate  100 . The edge region of the substrate  100  may be between lateral side surfaces of the semiconductor chip  200  and respective lateral side surfaces of the substrate  100 . The substrate  100  may include upper bonding pads  150  and an upper protection layer  111 . When viewed in plan view, the upper bonding pads  150  may overlap the edge region of the substrate  100 . The upper protection layer  111  may expose top surfaces of the upper bonding pads  150 . The upper bonding pads  150  may be aligned along a first direction D 1  and spaced apart from each other in the first direction D 1 . The first direction D 1  may be parallel to a top surface of the upper protection layer  111 . A second direction D 2  may be parallel to the top surface of the upper protection layer  111  and substantially orthogonal to the first direction D 1 . A third direction D 3  may be substantially perpendicular to the top surface of the upper protection layer  111  and substantially vertical to the first and second directions D 1  and D 2 . Terms such as “parallel,” “perpendicular,” “same,” “equal,” “planar,” and “coplanar,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes that fall within allowable tolerances. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. A top surface of the substrate  100  may include the top surfaces of the upper bonding pads  150  and the top surface of the upper protection layer  111 . 
     The semiconductor chip  200  may be mounted on the top surface of the substrate  100 . For example, when viewed in plan view, the semiconductor chip  200  may overlap the central region of the substrate  100 . In some embodiments, the semiconductor chip  200  may be a memory chip, such as DRAM, SRAM, or NAND Flash. The semiconductor chip  200  may include chip pads  250 . The chip pads  250  may be provided on a top surface of the semiconductor chip  200 . The chip pads  250  may be electrically connected to integrated circuits of the semiconductor chip  200 . The phrase “a certain component is electrically connected to the semiconductor chip  200 ” may mean that “the certain component is electrically connected to the integrated circuits through the chip pads  250  of the semiconductor chip  200 .” The expression “two components are electrically connected to each other” may include the meaning that “two components are connected to pass electrical signals from one component to the other either by being directly physically connected to each other or by being indirectly physically connected to each other through other component(s).” The chip pads  250  may include or be formed of a conductive material, such as metal. Though only one chip  200  is shown, in some embodiments, the chip  200  may be part of a stack of chips electrically connected to the substrate  100 . 
     The bonding wires  300  may be provided on the semiconductor chip  200  and the substrate  100 . The bonding wires  300  may be electrically connected to the chip pads  250  and the upper bonding pads  150 . The semiconductor chip  200  may be electrically connected through the bonding wires  300  to the substrate  100 . The bonding wires  300  may include metal, such as gold (Au). 
     The following will describe in detail a substrate. 
       FIG.  2 A  illustrates a cross-sectional view taken along line I-I′ of  FIG.  1   , showing a substrate according to some embodiments.  FIG.  2 B  illustrates an enlarged view showing section III of  FIG.  2 A . 
     Referring to  FIGS.  1 ,  2 A, and  2 B , the substrate  100  may include a dielectric structure, wiring lines  131 , first conductive vias  135 , second conductive vias  136 , upper bonding pads  150 , a lower protection layer  112 , and lower pads  160 . The dielectric structure may include a plurality of stacked dielectric layers  110 . The dielectric layers  110  may include or be formed of, for example, prepreg. The wiring lines  131  may be provided between the dielectric layers  110 . The wiring line  131  may include or be formed of metal, such as copper. The first and second conductive vias  135  and  136  may penetrate the dielectric layers  110 . The first conductive vias  135  may be provided on top surfaces of the wiring lines  131 , for example, to contact the wiring lines  131  at a top surface of the wiring lines  131 . The second conductive vias  136  may be provided on bottom surfaces of the wiring lines  131 , for example, to contact the wiring lines  131  at a bottom surface of the wiring lines  131 . The first and second conductive vias  135  and  136  may include or be formed of metal, such as copper. It will be understood that when an element is referred to as being “on” or “connected” or “coupled” to another element, it can be directly on or connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). 
     The upper protection layer  111  may be provided on a top surface of an uppermost one of the dielectric layers  110 . The top surface of the uppermost dielectric layer  110  may be a top surface of the dielectric structure. The upper protection layer  111  may have first holes  119 , or openings, that penetrate therethrough. The first holes  119  may expose the first conductive vias  135 . The upper protection layer  111  may include or be formed of an organic dielectric material, such as a solder resist material. 
     The upper bonding pads  150  may be provided on the top surface of the uppermost dielectric layer  110 . The upper bonding pads  150  may be correspondingly provided in the first holes  119 . Each of the upper bonding pads  150  may include a first portion formed in the hole  119  and including a first conductive pattern  151  and a second conductive pattern  152 , and a second portion formed outside of the hole  119  and including an intermediate layer  155  and a bonding layer  157 . The first conductive pattern  151  may be provided on the uppermost dielectric layer  110  and the first conductive via  135  that corresponds to the first conductive pattern  151  (e.g., formed directly on the structure formed of the uppermost dielectric layer  110  and the first conductive via  135 . As illustrated in  FIG.  2 B , the first conductive pattern  151  may have a first width W 1 , e.g., in the D 1  direction, at a bottom surface thereof. The first width W 1  may be in range from about 17 μm to about 30 μm. Because the first width W 1  is equal to or less than about 30 μm, an electrical short may be prevented between the upper bonding pads  150 . The first conductive pattern  151  may have a trapezoidal shape. For example, the first conductive pattern  151  may have, at a top surface thereof, a width W 11  less than the first width W 1 . A sidewall of the first conductive pattern  151  may be inclined relative to the bottom surface of the first conductive pattern  151 . Though not shown from the direction depicted in  FIGS.  2 A and  2 B , the sidewall may have a curved shape (e.g., a circular shape), from a plan view, or may have four sides connected at edges (e.g., to have a square shape), from a plan view. The first conductive pattern  151  may include or be formed of a first metal element. The first metal element may include or may be, for example, copper. Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. For example, a range having ends of different orders of magnitude (e.g., from “about 0.1 to about 1”) may encompass a range such as a 0%-5% deviation around each end (e.g., a 0% to 5% deviation around 0.1 and a 0% to 5% deviation around 1), while a range having ends of the same order of magnitude (e.g., about 15 to about 30) may encompass a range such as a 0%-5% deviation around the smaller of the two ends, particularly where the above deviations maintain the same effect as the listed range. 
     The second conductive pattern  152  may be provided on the first conductive pattern  151 . For example, the second conductive pattern  152  may cover the top surface and the sidewall of the first conductive pattern  151 . Though not shown from the direction depicted in  FIGS.  2 A and  2 B , the sidewall may have a curved shape, from a plan view, or may have four sides connected at edges, from a plan view. The second conductive pattern  152 , as measured between opposite outer sidewalls in the D 1  direction, may have a uniform width. The second conductive pattern  152  may have the first width W 1 . The first width W 1  may be a width at a top surface  152   u  of the second conductive pattern  152 . The second conductive pattern  152  may have a sidewall that is substantially vertical. For example, a substantially right angle may be given as an angle between the sidewall of the second conductive pattern  152  and a bottom surface of the upper protection layer  111 . In this description, the term “vertical” may indicate the meaning of “parallel to the third direction.” The first and second conductive patterns  151  and  152  may be described as first and second conductive components or first and second conductive portions, respectively. 
     The width at the top surface  152   u  of the second conductive pattern  152  may be the same as or similar to the first width W 1 , for example, about 90% to about 110% of the first width W 1 . The width at the top surface  152   u  of the second conductive pattern  152  may be in a range, for example, from about 17 μm to about 30 μm. The top surface  152   u  of the second conductive pattern  152  may be located at substantially the same level as that of a top surface  111   u  of the upper protection layer  111  to be coplanar with the top surface  111   u  of the upper protection layer  111 , but the present inventive concepts are not limited thereto. A level of a certain component may indicate a vertical level. 
     The sidewall of the second conductive pattern  152  may be covered with the upper protection layer  111 . For example, the sidewall of the second conductive pattern  152  may contact the upper protection layer  111 . 
     The second conductive pattern  152  may include a first metal element the same as that of the first conductive pattern  151 . According to some embodiments, the second conductive pattern  152  may have a grain different from that of the first conductive pattern  151 , for example, such that a grain boundary is formed between the first conductive pattern  151  and the second conductive pattern  152 . For example, the grain of the second conductive pattern  152  may have a size different from that of the grain of the first conductive pattern  151 . For another example, the grain of the second conductive pattern  152  may have a shape different from that of the grain of the first conductive pattern  151 . For another example, the grain of the second conductive pattern  152  may have a crystal structure different from that of the grain of the first conductive pattern  151 . According to some embodiments, the second conductive pattern  152  may have the same grain as that of the first conductive pattern  151 . 
     The intermediate layer  155  may be provided on the top surface  152   u  of the second conductive pattern  152 . For example, the intermediate layer  155  may cover the top surface  152   u  of the second conductive pattern  152 . The intermediate layer  155  may include or be formed of a second metal element. The second metal element may be different from the first metal element. The second metal element may include or be, for example, nickel. A width of a the intermediate layer  155  may be, for example, W 2 , which may be greater than W 1  by, for example, up to about 20%. The width W 2  may be a width in the D 1  direction of both a bottom surface and a top surface of the intermediate layer  155 . The intermediate layer  155  may have sidewall surfaces that extend between top and bottom surfaces and are substantially vertical. 
     The bonding layer  157  may be provided on the intermediate layer  155 . The bonding layer  157  may cover a top surface and sidewalls of the intermediate layer  155 . The top surface of the bonding layer  157  may be a surface to which the bonding wire (see  300  of  FIG.  1  or  2 A ) is bonded. The bonding layer  157  may have a third width W 3 . The third width W 3  may be a width at the top surface of the bonding layer  157 . The third width W 3  may be in a range from about 20 μm to about 33 μm. When the third width W 3  is less than about 20 μm, the bonding wire  300  may be difficult to bond to the bonding layer  157 . According to some embodiments, because the third width W 3  is equal to or greater than about 20 μm, the bonding wire  300  may be adequately bonded to the bonding layer  157  even when process errors occur in a process for forming the bonding wire  300 . When the third width W 3  is greater than about 33 μm, a pitch P 1  of the upper bonding pads  150  may need to be increased, for example, to avoid short circuits between adjacent upper bonding pads  150 . According to some embodiments, because the third width W 3  is equal to or less than about 33 μm, the pitch P 1  of the upper bonding pads  150  may become reduced. Accordingly, the semiconductor package  10  may become high in integration and small in size. 
     The third width W 3  may be the same as or greater than the second width W 2 , and may be greater than the first width W 1 . For example, the third width W 3  may be about 100% to about 120% of the first width W 1  while being greater than the second width W 2 . If the second width W 2  and the third width W 3  are less than the first width W 1 , the second conductive pattern  152  may be exposed and damaged. According to some embodiments, because the third width W 3  is equal to or greater than about 100% of the first width W 1 , the bonding layer  157  combined with the intermediate layer  155  may completely cover the top surface  152   u  of the second conductive pattern  152 . Therefore, the second conductive pattern  152  may be prevented from being damaged. Because the third width W 3  is equal to or less than about 120% of the first width W 1 , the upper bonding pads  150  may have a fine pitch P 1 . 
     The bonding layer  157  may have a thickness (e.g., in a vertical direction on the top surface of the intermediate layer  155  and in a horizontal direction on the sidewall surface of the intermediate layer  155 ) of about 2 μm to about 5 μm. Because the thickness T of the bonding layer  157  is equal to or greater than about 2 μm, the bonding wire  300  may be adequately bonded to the bonding layer  157 . There may be an improvement in bonding reliability between the bonding layer  157  and the bonding wire  300 . Because the thickness T of the bonding layer  157  is equal to or less than about 5 μm, the upper bonding pads  150  may have a reduced interval D therebetween, and the upper bonding pads  150  may have a fine pitch P 1 . The bonding layer  157  may have a substantially uniform thickness T. For example, the thickness T of the bonding layer  157  on the top surface of the intermediate layer  155  may be substantially the same as the thickness T of the bonding layer  157  on the sidewalls of the intermediate layer  155 . The thickness T of the bonding layer  157  may have a deviation equal to or less than about 1.5 μm. Accordingly, an electrical short may be prevented between the upper bonding pads  150 . 
     The bonding layer  157  may include or be formed of a third metal element. The third metal element may be different from the first metal element and the second metal element. For example, the third metal element may include or may be gold (Au). In the formation of the bonding layer  157 , the intermediate layer  155  may assist in plating the bonding layer  157 . The intermediate layer  155  may serve as a metal adhesion layer to allow the bonding layer to adequately bond to the second conductive pattern  152 . The bonding layer  157  may further serve as a protection layer. For example, the bonding layer  157  may prevent damage (e.g., oxidation) of the intermediate layer  155  and second conductive pattern  152 . 
     The pitch P 1  in the D 1  direction of the upper bonding pads  150 , or distance between corresponding points of adjacent upper bonding pads  150 , may be a fine pitch. For example, the pitch P 1  of the upper bonding pads  150  may be in a range of about 40 μm to about 60 μm. Because the pitch P 1  of the upper bonding pads  150  is equal to or greater than about 40 μm, an electrical short may be prevented between the upper bonding pads  150  and/or between the bonding wires  300 . Because the pitch P 1  of the upper bonding pads  150  is equal to or less than about 60 μm, the semiconductor package  10  may become small in size and high in integration. 
     The upper bonding pads  150  may have an interval D, or closest distance between them, of about 10 μm to about 20 μm. The interval D between the upper bonding pads  150  may correspond to an interval between the bonding layers  157  that correspond to the upper bonding pads  150 . Because the interval D between the upper bonding pads  150  is equal to or greater than about 10 μm, an electrical short may be prevented between the upper bonding pads  150  and/or between the bonding wires  300 . Because the interval D between the upper bonding pads  150  is equal to or greater than about 20 μm, the semiconductor package  10  may become small in size and high in integration. 
     As the first and second conductive patterns  151  and  152  included in one upper bonding pad  150  are provided in corresponding first holes  119 , a plurality of neighboring second conductive patterns  152  may be disposed laterally spaced apart from each other. Accordingly an electrical short may be prevented between the plurality of neighboring second conductive patterns  152 . 
     When the upper bonding pads  150  do not include the second conductive patterns  152 , and do not include the intermediate layer  155  or bonding layer  157  as shown in  FIG.  2 B , the first conductive pattern  151  may be required to have an increased size (and the hole  119  may need to be bigger) to satisfy the condition that the third width W 3  of a bonding layer of upper bonding pads is in a range of about 20 μm to about 33 μm. In this case, the first conductive pattern  151  may have an increased width at the bottom surface thereof, and thus an electrical short may occur between the upper bonding pads  150 . Alternatively, there may need to be an increase in the pitch P 1  of the upper bonding pads  150 . According to some embodiments, because the upper bonding pads  150  include the second conductive patterns  152 , the first conductive pattern  151  may have a reduced size, and the second width W 2  may be relatively small. Therefore, an electric short may be prevented between the upper bonding pads  150 , and the interval D may be reduced between the upper bonding pads  150 . Accordingly, the pitch P 1  may be reduced between the upper bonding pads  150 . For brevity of description, the following will discuss a single second conductive pattern  152 . 
     Referring back to  FIG.  2 A , the lower protection layer  112  may be provided on a bottom surface of a lowermost one of the dielectric layers  110 . The bottom surface of the lowermost dielectric layer  110  may be a bottom surface of the dielectric structure. The lower protection layer  112  may have second holes  129  that penetrate therethrough. The second holes  129  may expose second conductive vias  136 . The lower protection layer  112  may include or be formed of a dielectric material, such as a solder resist material. 
     The lower pads  160  may be provided on the top surface of the lowermost dielectric layer  110 . The lower pads  160  may be provided in the second hole  129 . Each of the lower pads  160  may include a lower conductive pattern  161 , a lower intermediate layer  165 , and a lower bonding layer  167 . The lower conductive pattern  161  may be provided on the bottom surface of the lowermost dielectric layer  110  and a bottom surface of the second conductive via  136  that corresponds to the lower conductive pattern  161 . A shape of the second conductive pattern  152  may be variously changed. The second conductive pattern  152  may include or be formed of the first metal element. 
     The lower intermediate layer  165  may be provided on a bottom surface of the lower conductive pattern  161 . The lower intermediate layer  165  may have a width the same as or less than that of the lower conductive pattern  161 . The lower intermediate layer  165  may include or be formed of the second metal element. 
     The lower bonding layer  167  may be provided on the bottom surface of the lower intermediate layer  165 . The lower bonding layer  167  may have a bottom surface to which a solder ball (see  600  of  FIG.  3 A ) is bonded. The lower bonding layer  167  may include or be formed of the third metal element. The lower protection layer  112  may cover a sidewall of the lower conductive pattern  161 , a sidewall of the lower intermediate layer  165 , and a sidewall of the lower bonding layer  167 . 
     The lower pads  160  may have a pitch P 2  greater than the pitch P 1  of the upper bonding pads  150 . 
     Alternatively, each of the lower pads  160  may include neither the lower intermediate layer  165  nor the lower bonding layer  167 . In this case, each of solder balls (see  600  of  FIG.  3 A ) may be directly disposed on the bottom surface of a corresponding lower conductive pattern  161 . 
     The lower pads  160  may be electrically connected to the upper bonding pads  150  through the second conductive vias  136 , the wiring lines  131 , and the first conductive vias  135 . 
       FIG.  2 C  illustrates an enlarged view of section III depicted in  FIG.  2 A , showing upper bonding pads according to some embodiments. 
     Referring to  FIG.  2 C , each of the upper bonding pads  150  may include a seed pattern  153  in addition to the first conductive pattern  151 , the second conductive pattern  152 , the intermediate layer  155 , and the bonding layer  157 . The seed pattern  153  may be interposed between the first conductive pattern  151  and the second conductive pattern  152 . The seed pattern  153  may cover the top surface and the sidewalls of the first conductive pattern  151 . The second conductive pattern  152  may be formed by a plating process in which the seed pattern  153  is used as an electrode. The seed pattern  153  may include or be formed of metal the same as the first metal element. Alternatively, the seed pattern  153  may include metal different from the first metal element. For example, the seed pattern  153  may include or may be titanium, copper, or any alloy thereof. 
       FIGS.  2 D and  2 E  illustrate an enlarged view of section III depicted in  FIG.  2 A , showing upper bonding pads and an upper protection layer according to some embodiments. A duplicate description will be omitted below. 
     Referring to  FIG.  2 D , the top surface  152   u  of the second conductive pattern  152  may be located at a different level from that of the top surface  111   u  of the upper protection layer  111 . For example, the top surface  152   u  of the second conductive pattern  152  may be located at a lower level than that of the top surface  111   u  of the upper protection layer  111 . The intermediate layer  155  may be provided in an upper portion of the second hole  129 . 
     Referring to  FIG.  2 E , the top surface  152   u  of the second conductive pattern  152  may be located at a higher level than that of the top surface  111   u  of the upper protection layer  111 . 
     The following will now describe a semiconductor package according to some embodiments. 
       FIG.  3 A  illustrates a cross-sectional view taken along I-I′ of  FIG.  1   , showing a semiconductor package according to some embodiments.  FIG.  3 B  illustrates a cross-sectional view taken along line II-II′ of  FIG.  1   . 
     Referring to  FIGS.  1 ,  3 A, and  3 B , a semiconductor package  10  may include a substrate  100 , solder balls  600 , a semiconductor chip  200 , bonding wires  300 , and a molding layer  400 . The substrate  100  may be substantially the same as that discussed in the examples of  FIGS.  2 A to  2 E . 
     The solder balls  600  may be provided on a bottom surface of the substrate  100 . For example, the solder balls  600  may be correspondingly provided on bottom surfaces of the lower pads  160 . The solder balls  600  may include or be formed of metal, such as a solder material. The solder material may include or be one or more of tin (Sn), silver (Ag), zinc (Zn), and any alloy thereof. The substrate  100  may be electrically connected through the solder balls  600  to an external apparatus. The solder balls  600  therefore may be described as external connection terminals. 
     As illustrated in  FIGS.  1  and  3 B , the semiconductor chip  200  may be mounted on a top surface of the substrate  100 . The semiconductor chip  200  may include chip pads  250  on the top surface thereof. 
     According to some embodiments, the bonding wires  300  may be provided on a top surface of the semiconductor chip  200  to electrically connect to the chip pads  250 . The bonding wires  300  may be bonded to top surfaces of the upper bonding pads  150 . For example, the bonding wire  300  may be correspondingly coupled to the bonding layer  157 . As discussed above, because the third width W 3  is equal to or greater than about 20 μm, the bonding wire  300  may be adequately bonded to the bonding layer  157  even when process errors occur in a process for forming the bonding wire  300 . 
     It is illustrated that the bonding wires  300  are provided on opposite sidewalls of the semiconductor chip  200 , but alternately the bonding wires  300  may be provided on only one sidewall of the semiconductor chip  200 . In at least this manner, aspects of the invention may apply to chip stacks including at least a first chip and one or more chips stacked thereon, for example in a step-wise or zig-zag format. For another example, the bonding wires  300  may be provided on at least three sidewalls of the semiconductor chip  200 . 
     As shown in  FIG.  3 B , and referring back to  FIG.  2 A , according to some embodiments, upper bonding pads  150  may extend vertically from a lower surface of a single, uppermost insulating layer of a substrate  100  (e.g., a lower surface of upper protection layer  111 ) through the uppermost insulating layer (e.g., upper protection layer  111 ). The bottom surface of the bonding pads  150  may have a surface coplanar with a bottom surface of the uppermost insulating layer of the substrate  100  (e.g., upper protection layer  111 ). The top surface of the bonding pads  150  may have a surface above a top surface of the uppermost insulating layer of the substrate  100 . Each upper bonding pad may have a flat top surface and a flat bottom surface. The upper bonding pads  150  may be upper connection terminals, directly adjacent to and contacting bonding wires  300  that connect the substrate  100  to the semiconductor chip  200 . 
     An adhesion layer (not shown) may further be interposed between the semiconductor chip  200  and the substrate  100 . The adhesion layer may include or may be a die attach film (DAF). 
     The molding layer  400  may be provided on the top surface of the substrate  100  to cover the semiconductor chip  200  and the bonding wires  300 . The molding layer  400  may include a dielectric polymer, such as an epoxy-based polymer. 
     The following will describe a substrate fabrication method according to some embodiments. 
       FIGS.  4 A to  4 G  illustrate cross-sectional views taken along line I-I′ of  FIG.  1   , showing a substrate fabrication method according to some embodiments. 
     Referring to  FIG.  4 A , a temporary substrate  900  may be provided. The temporary substrate  900  may include a detachable core. The temporary substrate  900  may have a top surface and a bottom surface that are opposite to each other. 
     Second conductive layers  161 Z may be formed on the top and bottom surfaces of the temporary substrate  900 . Dielectric layers  110  may be correspondingly formed on and cover the second conductive layers  161 Z. The dielectric layers  110  may be first dielectric layers  110 A. Second conductive vias  136  may be formed in the first dielectric layers  110 A to electrically connect to the second conductive layers  161 Z. Wiring lines  131  may be correspondingly formed on the second conductive vias  136  and the first dielectric layers  110 A. The wiring lines  131  may be spaced apart from each other. The wiring lines  131  may be correspondingly coupled to the second conductive vias  136 . 
     Referring to  FIG.  4 B , the formation of the dielectric layers  110  may be repeatedly performed to form second dielectric layers  110 B. The second dielectric layers  110 B may be formed on and cover the first dielectric layers  110 A and the wiring lines  131 . First conductive vias  135  may be formed in the second dielectric layers  110 B and on the wiring lines  131 . The first conductive vias  135  may be electrically connected to the wiring lines  131 . 
     First conductive layers  151 Z may be formed on the second dielectric layers  110 B and the first conductive vias  135 . The formation of the first conductive layers  151 Z may include performing a plating process. The plating process may include an electroplating process or a chemical plating process. The chemical plating process may include an electroless plating process. The first conductive layers  151 Z may be coupled to the first conductive vias  135 . Therefore, preliminary substrates  20  may be fabricated. The preliminary substrates  20  may be correspondingly formed on the top and bottom surfaces of the temporary substrate  900 . Each of the preliminary substrates  20  may include a corresponding first dielectric layer  110 A, a corresponding second dielectric layer  110 B, a corresponding second conductive layer  161 Z, first conductive vias  135 , a corresponding first conductive layer  151 Z, and second conductive vias  136 . 
     Differently from the discussion of  FIGS.  4 A and  4 B , the first conductive layers  151 Z may be correspondingly formed on top and bottom surfaces of the temporary substrate  900 . Afterwards, a plurality of second dielectric layers  110 B, a plurality of first conductive vias  135 , a plurality of first dielectric layers  110 A, a plurality of second conductive vias  136 , a plurality of first dielectric layers  110 A, and a plurality of second conductive layers  161 Z may be sequentially formed to form the preliminary substrates  20 . 
     Referring to  FIG.  4 C , the preliminary substrates  20  may be separated from the temporary substrate  900 . 
     Referring to  FIG.  4 D , one of the separated preliminary substrates  20  is shown. 
     Referring to  FIG.  4 E , using one of the separated preliminary substrates  20  as an example, the first conductive layer  151 Z may undergo a patterning process, and the second conductive layer  161 Z may undergo a patterning process. The patterning process of the first conductive layer  151 Z and the patterning process of the second conductive layer  161 Z may be performed in a single or multiple steps. 
     The first conductive layer  151 Z may be patterned to form a plurality of first conductive patterns  151 . The patterning process of the first conductive layer  151 Z may include an etching process. The patterning process of the first conductive layer  151 Z may further include exposure and development processes. The etching process may include a wet etching process. An upper portion of each of the first conductive patterns  151  may be exposed to the etching process earlier than a lower portion of each of the first conductive patterns  151 , and thus each of the first conductive patterns  151  may have a trapezoidal shape. Therefore, each of the first conductive patterns  151  may have a width W 11  at its top surface less than a first width W 1  at its bottom surface. The first conductive patterns  151  may be correspondingly coupled to the first conductive vias  135 . The first conductive patterns  151  may be laterally spaced apart and electrically separated from each other. 
     The second conductive layer  161 Z may be patterned to form a plurality of lower conductive patterns  161 . The patterning process of the second conductive layer  161 Z may include an etching process. The patterning process of the second conductive layer  161 Z may further include exposure and development processes. The etching process may include a wet etching process. Differently from that shown, each of the lower conductive patterns  161  may have a width at its top surface greater than a width at its bottom surface. The lower conductive patterns  161  may be correspondingly coupled to the second conductive vias  136 . The lower conductive patterns  161  may be laterally spaced apart and electrically separated from each other. 
     Referring to  FIG.  4 F , an upper protection layer  111  may be formed on a top surface of an uppermost dielectric layer  110 . The formation of the upper protection layer  111  may include coating a solder resist material. First holes  119  may be formed in the upper protection layer  111  to expose the first conductive patterns  151 . 
     A lower protection layer  112  may be formed on a bottom surface of a lowermost dielectric layer  110 . The formation of the lower protection layer  112  may include coating a solder resist material. Second holes  129  may be formed on the lower protection layer  112  to expose the lower conductive patterns  161 . 
     Referring to  FIG.  4 G , the first conductive patterns  151  may undergo a plating process to form a plurality of second conductive patterns  152 . The second conductive patterns  152  may cover top and lateral surfaces of the first conductive patterns  151 . The plating process may include an electroplating process or a chemical plating process. 
     The lower conductive patterns  161  may not be exposed to the plating process. For another example, a plating process may further be processed on the lower conductive patterns  161 . In this case, additional lower conductive patterns (not shown) may further be formed on bottom surfaces of the lower conductive patterns  161 . 
     Referring back to  FIG.  2 A , a plurality of intermediate layers  155  may be correspondingly formed on the second conductive patterns  152 . The intermediate layers  155  may be laterally spaced apart from each other. A plurality of bonding layers  157  may be formed on the intermediate layers  155  to cover top surfaces and sidewalls of the intermediate layers  155 . A plating process may be performed to form the bonding layers  157 . The bonding layers  157  may be disposed laterally spaced apart from each other. Therefore, upper bonding pads  150  may be fabricated. The upper bonding pads  150  may include the first conductive patterns  151 , the second conductive patterns  152 , the intermediate layers  155 , and the bonding layers  157 . 
     A plurality of lower intermediate layers  165  may be formed on the lower conductive patterns  161  and in the second holes  129 . The lower intermediate layers  165  and the intermediate layers  155  may be formed in a single process or in individual processes. A plurality of lower bonding layers  167  may be formed on the lower intermediate layers  165  and in the second holes  129 . The lower bonding layers  167  and the bonding layers  157  may be formed in a single process or in individual processes. Therefore, lower pads  160  may be fabricated. The lower pads  160  may include the lower conductive patterns  161 , the lower intermediate layers  165 , and the lower bonding layers  167 . Through the aforementioned exemplary processes, a substrate  100  may be eventually fabricated. 
     Subsequently, as shown in  FIG.  3 B , a semiconductor chip  200  may be disposed on the substrate  100 , and bonding wires may be connected to the semiconductor chip  200  via chip pads  250  and may be connected to the substrate  100  via the upper bonding pads  150 . The bonding of wires to the pads may be performed using known bonding techniques, for example, using pressure, heat, ultrasonic energy, etc. Additional steps may be performed, as described previously, to result in the semiconductor package  10  shown in  FIG.  3 B . 
     According to the present inventive concepts, upper bonding pads may each include a first conductive pattern, a second conductive pattern, an intermediate layer, and a bonding layer. The presence of the second conductive pattern may cause the upper bonding pads to have a fine pitch. An upper protection layer may cover a sidewall of the second conductive pattern to prevent an electrical short between the upper bonding pads. Bonding wires may be prevented from an electrical short, and may each be adequately bonded to a corresponding bonding layer. 
     This detailed description of the present inventive concepts should not be construed as limited to the embodiments set forth herein, and it is intended that the present inventive concepts cover the various combinations, the modifications and variations of this invention without departing from the spirit and scope of the present inventive concepts. The appended claims should be construed to include other embodiments. 
     Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element&#39;s or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
     Ordinal numbers such as “first,” “second,” “third,” etc. may be used simply as labels of certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms that are not described using “first,” “second,” etc., in the specification, may still be referred to as “first” or “second” in a claim. In addition, a term that is referenced with a particular ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim).