Patent Publication Number: US-11031056-B2

Title: Clock generation circuitry for memory device to generate multi-phase clocks and output data clocks to sort and serialize output data

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0173971 filed on Dec. 31, 2018, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Exemplary embodiments relate to a memory device that sorts data based on a clock. 
     2. Discussion of the Related Art 
     Recently, with the increase in operation speed of memory systems, memory devices in the memory systems are required to have a high transfer rate. In order to satisfy a high data transfer rate or high-bandwidth data transfer, the memory devices apply prefetch to sort data. The prefetch refers to an operation of latching and deserializing data which are serially inputted. 
     In order to sort data in parallel or series, a memory device uses a method of dividing an internal clock. The memory device includes a clock generation circuit to generate multi-phase clocks having different phases by dividing the internal clock. The memory device sorts data based on the multi-phase clocks, and transfers the sorted data. 
     SUMMARY 
     Various embodiments are directed to a memory device capable of adjusting the order of sorting internal clocks divided from an external clock according to an input time point of a command, and thus secure a valid window of data which are sorted based on the internal clocks. 
     In an embodiment, a clock generation circuit may include: a clock dividing circuit suitable for generating a first internal clock, a second internal clock, a third internal clock and a fourth internal clock by dividing an external clock; a mode signal generation circuit suitable for generating a first mode signal and a second mode signal according to an input time point of a read command based on the first and third internal clocks; a first shifting circuit suitable for generating a plurality of first shifting signals by shifting the first mode signal in response to the first internal clock; a second shifting circuit suitable for generating a plurality of second shifting signals by shifting the second mode signal in response to the third internal clock; and a clock arranging circuit suitable for arranging the first to fourth internal clocks and outputting the arranged clocks as a first data output clock, a second data output clock, a third data output clock and a fourth data output clock, in response to the plurality of first and second shifting signals. 
     In an embodiment, a memory device may include: a clock dividing circuit suitable for generating a plurality of internal clocks by dividing an external clock; a mode decision circuit suitable for determining an operation mode according to an input time point of a read command based on the internal clocks; a clock arranging circuit suitable for arranging the internal clocks in an order determined according to the operation mode, and outputting the arranged clocks as a plurality of data output clocks; and a data arranging circuit suitable for arranging read data according to the operation mode, and outputting the arranged data in response to the data output clocks. 
     In an embodiment, a memory device may include: a clock generation circuit suitable for receiving an external clock, generating a plurality of internal clocks by dividing the external clock, and arranging the plurality of internal clocks according to an operation mode, which is determined based on an input timing of a read command, to generate a plurality of data output clocks; and a data arranging circuit suitable for receiving a plurality of data in parallel from a memory cell array, arranging the plurality of data according to the operation mode to generate arranged multiple data and serializing the arranged multiple data to output serialized data according to the plurality of data output clocks. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a memory device in accordance with an embodiment. 
         FIG. 2  is a block diagram illustrating a mode decision circuit illustrated in  FIG. 1 . 
         FIG. 3  is a block diagram illustrating a first shifting circuit illustrated in  FIG. 2 . 
         FIG. 4  is a circuit diagram illustrating a clock arranging circuit illustrated in  FIG. 1 . 
         FIG. 5  is a circuit diagram illustrating a clock pulse generation circuit illustrated in  FIG. 1 . 
         FIG. 6  is a circuit diagram illustrating a clock combination circuit illustrated in  FIG. 1 . 
         FIGS. 7A and 7B  are signal waveform diagrams illustrating an operation of a memory device in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments are described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and thus should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the present invention to those skilled in the art. Moreover, reference herein to “an embodiment,” “another embodiment,” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). Throughout the disclosure, like reference numerals refer to like parts in the figures and embodiments of the present invention. 
     The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a computer program product embodied on a computer-readable storage medium; and/or a processor, such as a processor suitable for executing instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other forms that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being suitable for performing a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ or the like refers to one or more devices, circuits, and/or processing cores suitable for processing data, such as computer program instructions. 
     A detailed description of embodiments of the invention is provided below along with accompanying figures that illustrate aspects of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims. The invention encompasses numerous alternatives, modifications and equivalents within the scope of the claims. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example; the invention may be practiced according to the claims without some or all of these specific details. For clarity, technical material that is known in technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured. 
       FIG. 1  is a block diagram illustrating a memory device  100  in accordance with an embodiment. 
     Referring to  FIG. 1 , the memory device  100  may include a clock generation circuit  110  and a data arranging circuit  120 . The clock generation circuit  110  may include a clock dividing circuit  111 , a mode decision circuit  112 , a clock arranging circuit  113 , a clock pulse generation circuit  114  and a clock combination circuit  115 . The data arranging circuit  120  may include a selection circuit  121  and a data serialization circuit  122 . The clock dividing circuit  111 , the mode decision circuit  112 , the clock arranging circuit  113 , the clock pulse generation circuit  114 , the clock combination circuit  115 , the selection circuit  121  and the data serialization circuit  122  include all circuits, systems, software, firmware and devices necessary for their respective operations and functions. 
     The clock dividing circuit  111  may generate a plurality of internal clocks ICLK&lt; 1 : 4 &gt; having different phases by dividing an external clock CLK. The external clock CLK may be set to a signal which is periodically toggled. The clock dividing circuit  111  may generate first to fourth internal clocks ICLK&lt; 1 : 4 &gt; having a phase difference of 90° at first rising/falling edges and second rising/falling edges of the external clock CLK. However, the present embodiment is not limited thereto, but may be implemented to generate various numbers of internal clocks. 
     The mode decision circuit  112  may determine an operation mode according to an input time point of a read command RD, based on the first and third internal clocks ICLK&lt; 1 &gt; and ICLK&lt; 3 &gt;. The mode decision circuit  112  may generate first and second mode signals LTOE_A and LTOE_B indicating the determined operation mode and a plurality of first and second shifting signals LTOE_A&lt; 1 : 5 &gt; and LTOE_B&lt; 1 : 5 &gt; corresponding to the first and second mode signals LTOE_A and LTOE_B, respectively. The operation of the mode decision circuit  112  will be described in more detail with reference to  FIG. 2 . 
     The clock arranging circuit  113  may arrange the first to fourth internal clocks ICLK&lt; 1 : 4 &gt; in an order which is decided according to the operation mode, and output the sorted clocks as first to fourth data output clocks DOCLK&lt; 1 : 4 &gt;. The clock arranging circuit  113  may sort the first to fourth internal clocks ICLK&lt; 1 : 4 &gt; in response to first to fourth first shifting signals LTOE_A&lt; 1 : 4 &gt; and first to fourth second shifting signals LTOE_B&lt; 1 : 4 &gt; among the plurality of first and second shifting signals LTOE_A&lt; 1 : 5 &gt; and LTOE_B&lt; 1 : 5 &gt;, and output the sorted clocks as the first to fourth data output clocks DOCLK&lt; 1 : 4 &gt;. 
     The clock pulse generation circuit  114  may generate first and second clock pulses CLK_PL&lt; 1 : 2 &gt; with the third and first internal clocks ICLK&lt; 3 &gt; and ICLK&lt; 1 &gt;. In particular, the clock pulse generation circuit  114  may generate the first and second clock pulses CLK_PL&lt; 1 : 2 &gt; in response to the first and last first shifting signals LTOE_A&lt; 1 &gt; and LTOE_&lt; 5 &gt; and the first and last second shifting signals LTOE_&lt; 1 &gt; and LTOE_B&lt; 5 &gt; among the plurality of first and second shifting signals LTOE_A&lt; 1 : 5 &gt; and LTOE_B&lt; 1 : 5 &gt;. 
     The clock combination circuit  115  may combine the first to fourth data output clocks DOCLK&lt; 1 : 4 &gt; and the first and second clock pulses CLK_PL&lt; 1 : 2 &gt;, and output the combined clocks as first to fourth final clocks CLK_FL&lt; 1 : 4 &gt;. The operation of the clock combination circuit  115  will be described in more detail with reference to  FIG. 6 . 
     The selection circuit  121  may sort data RDATA&lt; 1 : 4 &gt; read from a memory cell array (not illustrated) according to the operation mode decided by the mode decision circuit  112 . The selection circuit  121  may sort the data RDATA&lt; 1 : 4 &gt; inputted through first to fourth input nodes and output the sorted data DATA&lt; 1 : 4 &gt; to first to fourth output nodes, in response to the first and second mode signals LTOE_A/B. 
     When the first mode signal LTOE_A is activated, the selection circuit  121  may sort the data RDATA&lt; 1 : 4 &gt; inputted through the first to fourth input nodes for the third, fourth, first and second output nodes, respectively, and sequentially output the sorted data DATA&lt; 3 &gt;&lt; 4 &gt;&lt; 1 &gt;&lt; 2 &gt;. When the second mode signal LTOE_B is activated, the selection circuit  121  may sort the data RDATA&lt; 1 : 4 &gt; inputted through the first to fourth input nodes for the first to fourth output nodes, respectively, and sequentially output the sorted data DATA&lt; 1 : 4 &gt;. 
     The data serialization circuit  122  may output the sorted data DATA&lt; 1 : 4 &gt; to a data pad DQ in response to the first to fourth final clocks CLK_FL&lt; 1 : 4 &gt;. The data serialization circuit  122  may serialize the data DATA&lt; 1 : 4 &gt; inputted in parallel in response to the first to fourth final clocks CLK_FL&lt; 1 : 4 &gt;, and output the serialized data to the data pad DQ. 
       FIG. 2  is a block diagram illustrating the mode decision circuit  112  illustrated in  FIG. 1 . 
     Referring to  FIG. 2 , the mode decision circuit  112  may include a mode signal generation circuit  210 , a first shifting circuit  220 , and a second shifting circuit  230 . 
     The mode signal generation circuit  210  may generate the first and second mode signals LTOE_A/LTOE_B according to an input time point of the read command RD, based on the first and third internal docks ICLK&lt; 1 &gt; and ICLK&lt; 3 &gt;. When the read command RD is inputted in synchronization with the first internal clock ICLK&lt; 1 &gt;, the mode signal generation circuit  210  may activate the first mode signal LTOE_A. When the read command RD is inputted in synchronization with the third internal clock ICLK&lt; 3 &gt;, the mode signal generation circuit  210  may activate the second mode signal LTOE_B. 
     When the first mode signal LTOE_A is activated, the first shifting circuit  220  may generate the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; by shifting the first mode signal LTOE_A, in response to the first internal clock ICLK&lt; 1 &gt;. When the second mode signal LTOE_B is activated, the second shifting circuit  230  may generate the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt; by shifting the second mode signal LTOE_B, in response to the third internal clock ICLK&lt; 3 &gt;. 
       FIG. 3  is a block diagram illustrating the first shifting circuit  220  illustrated in  FIG. 2 . Since the first and second shifting circuits  220  and  230  have the same configuration except that input signals are different, the first shifting circuit  220  will be representatively described. 
     Referring to  FIG. 3 , the first shifting circuit  220  may include a plurality of first flip-flops (F/Fs)  310 , a plurality of multiplexers (MUXs)  320  and a plurality of second flip-flops (F/Fs)  330 . The first shifting circuit  220  may generate the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; by delaying the first mode signal LTOE_A by a time corresponding to read latency in synchronization with the first internal clock ICLK&lt; 1 &gt; and shifting the delayed signal LTOE_A&lt; 0 &gt;. 
     The plurality of first flip-flops  310  may shift the first mode signal LTOE_A in response to the first internal clock ICLK&lt; 1 &gt;. At this time, a signal RL&lt;X&gt; inputted to each of the multiplexers  320  may be activated in response to the read latency. Therefore, through the multiplexer  320  corresponding to the activated signal RL&lt;X&gt;, the first mode signal LTOE_A may be delayed by the time corresponding to the read latency and outputted as the delayed signal LTOE_A&lt; 0 &gt;. 
     The plurality of second flip-flops  330  may generate the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; by shifting the delayed signal LTOE_A&lt; 0 &gt; in response to the first internal clock ICLK&lt; 1 &gt;. The plurality of second flip-flops  330  may generate five first shifting signals LTOE_A&lt; 1 : 5 &gt; having a phase difference corresponding to 90° of the first internal clock ICLK&lt; 1 &gt;. However, the present embodiment is not limited thereto, but may be implemented to generate various numbers of shifting signals. 
     Similarly, the second shifting circuit  230  of  FIG. 2  may generate the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt; by delaying the second mode signal LTOE_B by the time corresponding to the read latency in synchronization with the third internal clock ICLK&lt; 3 &gt; and shifting the delayed signal. The second shifting circuit  230  may generate five second shifting signals LTOE_B&lt; 1 : 5 &gt; having a phase difference corresponding to 90° of the third internal clock ICLK&lt; 3 &gt;. 
       FIG. 4  is a circuit diagram illustrating the dock arranging circuit  113  illustrated in  FIG. 1 . 
     Referring to  FIG. 4 , the clock arranging circuit  113  may include first to fourth clock transfer circuits  410  to  440 . Each of the first to fourth clock transfer circuits  410  to  440  may include first and second NAND gates NAND 1  and NAND 2  and first and second inverters INV 1  and INV 2 . The first to fourth clock transfer circuits  410  to  440  include all circuits, systems, software, firmware and devices necessary for their respective operations and functions. 
     The first clock transfer circuit  410  may transfer the first internal clock ICLK&lt; 1 &gt; as the first data output clock DOCLK&lt; 1 &gt; in response to the third first shifting signal LTOE_A&lt; 3 &gt; of the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; and the first second shifting signal LTOE_B&lt; 1 &gt; of the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt;. At this time, the plurality of first and second shifting signals LTOE_A&lt; 1 : 5 &gt; and LTOE_B&lt; 1 : 5 &gt; may be signals which are activated to a logic low level. 
     Therefore, when the third first shifting signal LTOE_A&lt; 3 &gt; is activated to a logic low level, a signal inverted to a logic high level by the first inverter INV 1  may be inputted to the first NAND gate NAND 1 . Thus, the first NAND gate NAND 1  may turn on/turn off a PMOS transistor to output the first data output clock DOCLK&lt; 1 &gt;, in response to the first internal clock ICLK&lt; 1 &gt;. 
     When the first second shifting signal LTOE_B&lt; 1 &gt; is activated to a logic low level, a signal inverted to a logic high level by the second inverter INV 2  may be inputted to the second NAND gate NAND 2 . Therefore, the second NAND gate NAND 2  may turn on/turn off an NMOS transistor to output the first data output clock DOCLK&lt; 1 &gt;, in response to the first internal clock ICLK&lt; 1 &gt;. 
     Similarly, the second clock transfer circuit  420  may transfer the second internal clock ICLK&lt; 2 &gt; as the second data output clock DOCLK&lt; 2 &gt; in response to the fourth first shifting signal LTOE_A&lt; 4 &gt; of the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; and the second second shifting signal LTOE_B&lt; 2 &gt; of the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt;. The third clock transfer circuit  430  may transfer the third internal clock ICLK&lt; 3 &gt; as the third data output clock DOCLK&lt; 3 &gt; in response to the first first shifting signal LTOE_A&lt; 1 &gt; of the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; and the third second shifting signal LTOE_B&lt; 3 &gt; of the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt;. The fourth clock transfer circuit  440  may transfer the fourth internal clock ICLK&lt; 4 &gt; as the fourth data output clock DOCLK&lt; 4 &gt; in response to the second first shifting signal LTOE_A&lt; 2 &gt; of the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; and the fourth second shifting signal LTOE_B&lt; 4 &gt; of the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt;. 
     That is, the clock arranging circuit  113  may transfer the first to fourth internal clocks ICLK&lt; 1 : 4 &gt; as the first to fourth data output clocks DOCLK&lt; 1 : 4 &gt; in response to the third, fourth, first and second first shifting signals LTOE_A&lt; 3 &gt;, LTOE_A&lt; 4 &gt;, LTOE_A&lt; 1 &gt; and LTOE_A&lt; 2 &gt;, respectively, among the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt;. Furthermore, the clock arranging circuit  113  may transfer the first to fourth internal clocks ICLK&lt; 1 : 4 &gt; as the first to fourth data output clocks DOCLK&lt; 1 : 4 &gt; in response to the first to fourth second shifting signals LTOE_B&lt; 1 : 4 &gt;, respectively, among the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt;. 
       FIG. 5  is a circuit diagram illustrating the clock pulse generation circuit  114  illustrated in  FIG. 1 . 
     Referring to  FIG. 5 , the clock pulse generation circuit  114  may include first and second clock pulse generation circuits  510  and  520 . Each of the first and second clock pulse generation circuits  510  and  520  may include third and fourth NAND gates NAND 3  and NAND 4  and third and fourth inverters INV 3  and INV 4 . The first and second clock pulse generation circuits  510  and  520  include all circuits, systems, software, firmware and devices necessary for their respective operations and functions. 
     The first clock pulse generation circuit  510  may output the third internal clock ICLK&lt; 3 &gt; as the first clock pulse CLK_PL&lt; 1 &gt; in response to the first and fifth first shifting signals LTOE_A&lt; 1 &gt; and LTOE_A&lt; 5 &gt; among the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt;. In an interval where the first and fifth first shifting signals LTOE_A&lt; 1 &gt; and LTOE_A&lt; 5 &gt; among the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; have a logic high level and a logic low level, respectively, the first clock pulse generation circuit  510  may output the third internal clock ICLK&lt; 3 &gt; as the first clock pulse CLK_PL&lt; 1 &gt;. 
     Specifically, when the first and fifth first shifting signals LTOE_A&lt; 1 &gt; and LTOE_A&lt; 5 &gt; among the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; have a logic high level and a logic low level, respectively, the third NAND gate NAND 3  may output a logic low-level output signal. The fourth inverter INV 4  may invert the output signal of the third NAND gate NAND 3 , and input a logic high-level signal to the fourth NAND gate NAND 4 . 
     Therefore, in the interval where the first and fifth first shifting signals LTOE_A&lt; 1 &gt; and LTOE_A&lt; 5 &gt; among the plurality of first shifting signals LTOE_A&lt; 1 : 5 &gt; have a logic high level and a logic low level, respectively, the fourth NAND gate NAND 4  may turn on/turn off an NMOS transistor in response to the third internal clock ICLK&lt; 3 &gt;. In this interval, as the third internal clock ICLK&lt; 3 &gt; changes to a logic high/low level, the first clock pulse CLK_PL&lt; 1 &gt; may also change to a logic high/low level. 
     Similarly, the second clock pulse generation circuit  520  may output the first internal clock ICLK&lt; 1 &gt; as the second clock pulse CLK_PL&lt; 2 &gt; in response to the first and fifth second shifting signals LTOE_B&lt; 1 &gt; and LTOE_B&lt; 5 &gt; among the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt;. In an interval where the first and fifth second shifting signals LTOE_B&lt; 1 &gt; and LTOE_B&lt; 5 &gt; among the plurality of second shifting signals LTOE_B&lt; 1 : 5 &gt; have a logic high level and a logic low level, respectively, the second clock pulse generation circuit  520  may output the first internal clock ICLK&lt; 1 &gt; as the second clock pulse CLK_PL&lt; 2 &gt;. 
       FIG. 6  is a circuit diagram illustrating the clock combination circuit  115  illustrated in  FIG. 1 . 
     Referring to  FIG. 6 , the clock combination circuit  115  may include first to fourth clock combination circuits  610  to  640 . Each of the first and third clock combination circuits  610  and  630  may include fifth and sixth NAND gates NAND 5  and NAND 6 , fifth and sixth inverters INV 5  and INV 6  and a first NOR gate NOR 1 . Each of the second and fourth clock combination circuits  620  and  640  may include seventh and eighth NAND gates NAND 7  and NAND 8 , seventh and eighth inverters INV 7  and INV 8  and a second NOR gate NOR 2 . The first to fourth clock combination circuits  610  to  640  include all circuits, systems, software, firmware and devices necessary for their respective operations and functions. 
     The first clock combination circuit  610  may combine the first and second data output clocks DOCLK&lt; 1 : 2 &gt; and output the first final clock CLK_FL&lt; 1 &gt;. In an interval where the first and second data output clocks DOCLK&lt; 1 : 2 &gt; have a logic high level and a logic low level, respectively, the first clock combination circuit  610  may output the first final clock CLK_FL&lt; 1 &gt; at a logic high level. 
     At this time, an enable signal EN may be a signal which is activated during a read operation. When the first data output dock DOCLK&lt; 1 &gt; has a logic high level, the fifth NAND gate NAND 5  may output a logic low-level output signal. The fifth inverter INV 5  may invert the output signal of the fifth NAND gate NAND 5 , and input a logic high-level signal to the sixth NAND gate NAND 6 . 
     When the second data output clock DOCLK&lt; 2 &gt; has a logic low level, the first NOR gate NOR 1  may output a logic high-level output signal. Therefore, in an interval where the first and second data output clocks DOCLK&lt; 1 : 2 &gt; have a logic high level and a logic low level, respectively, the sixth NAND gate NAND 6  may output a logic low-level output signal, and the first final clock CLK_FL&lt; 1 &gt; may be activated to a logic high level. 
     Similarly, the third clock combination circuit  630  may combine the third and fourth data output clocks DOCLK&lt; 3 : 4 &gt; and output the third final clock CLKFL&lt; 3 &gt;. In an interval where the third and fourth data output clocks DOCLK&lt; 3 : 4 &gt; have a logic high level and a logic low level, respectively, the third clock combination circuit  630  may output the third final clock CLK_FL&lt; 3 &gt; at a logic high level. 
     The second clock combination circuit  620  may combine the second and third data output clocks DOCLK&lt; 2 : 3 &gt; and the first clock pulse CLK_PL&lt; 1 &gt;, and output the second final clock CLK_FL&lt; 2 &gt;. In an interval where the second data output clock DOCLK&lt; 2 &gt; has a logic high level and the third data output clock DOCLK&lt; 3 &gt; and the first dock pulse CLK_PL&lt; 1 &gt; have a logic low level, the second dock combination circuit  620  may output the second final clock CLK_FL&lt; 2 &gt; at a logic high level. 
     As described above, the enable signal EN may be a signal which is activated during a read operation. When the second data output clock DOCLK&lt; 2 &gt; has a logic high level, the seventh NAND gate NAND 7  may output a logic low-level output signal. The seventh inverter INV 7  may invert the output signal of the seventh NAND gate NAND 7 , and input a logic high-level signal to the eighth NAND gate NAND 8 . 
     When the third data output clock DOCLK&lt; 3 &gt; and the first clock pulse CLK_PL&lt; 1 &gt; have a logic low level, the second NOR gate NOR 2  may output a logic high-level output signal. Therefore, in an interval where the second data output clock DOCLK&lt; 2 &gt; has a logic high level, and the third data output clock DOCLK&lt; 3 &gt; and the first clock pulse CLK_PL&lt; 1 &gt; have a logic low level, the eighth NAND gate NAND 8  may output a logic low-level output signal, and the second final clock CLK_FL&lt; 2 &gt; may be activated to a logic high level. 
     Similarly, the fourth clock combination circuit  640  may combine the fourth data output clock DOCLK&lt; 4 &gt;, the first data output clock DOCLK&lt; 1 &gt; and the second clock pulse CLK_PL&lt; 2 &gt;, and output the fourth final clock CLK_FL&lt; 4 &gt;. In an interval where the fourth data output clock DOCLK&lt; 4 &gt; has a logic high level, and the first data output clock DOCLK&lt; 1 &gt; and the second clock pulse CLK_PL&lt; 2 &gt; have a logic low level, the fourth clock combination circuit  640  may output the fourth final clock CLK_FL&lt; 4 &gt; at a logic high level. 
       FIGS. 7A and 7B  are signal waveform diagrams illustrating an operation of the memory device  100  in accordance with an embodiment.  FIGS. 7A and 7B  illustrate signal waveforms of the memory device  100  of  FIGS. 1 to 6  at different input time points of the read command RD. 
     Referring to  FIG. 7A , the clock dividing circuit  111  may generate the first to fourth internal clocks ICLK&lt; 1 : 4 &gt; having a phase difference of 90° by dividing the external clock CLK. The mode decision circuit  112  may determine an operation mode according to an input time point of the read command RD, based on the first and third internal clocks ICLK&lt; 1 &gt; and ICLK&lt; 3 &gt; among the first to fourth internal clocks ICLK&lt; 1 : 4 &gt;. 
     When the read command RD is inputted in synchronization with the first internal clock ICLK&lt; 1 &gt; ({circumflex over (1)}), the mode decision circuit  112  may activate the first mode signal LTOE_A. The mode decision circuit  112  may generate the first shifting signals LTOE_A&lt; 1 : 5 &gt; by delaying the first mode signal LTOE_A by a time corresponding to read latency and shifting the delayed signal. 
     The first mode signal LTOE_A may be activated during an interval BL corresponding to a burst length. The first shifting signals LTOE_A&lt; 1 : 5 &gt; generated from the first mode signal LTOE_A may be used as output enable signals for enabling data output circuits according to a read operation. Although  FIG. 7A  illustrates five first shifting signals LTOE_A&lt; 1 : 5 &gt;, a plurality of shifting signals may be generated by shifting the first mode signal LTOE_A according to the positions of the data output circuits on a data path. 
     The clock arranging circuit  113  may transfer the third internal clock ICLK&lt; 3 &gt; as the third data output clock DOCLK&lt; 3 &gt; in response to the first first shifting signal LTOE_A&lt; 1 &gt;. Then, in response to the second to fourth first shifting signals LTOE_A&lt; 2 : 4 &gt; which are subsequently activated, the clock arranging circuit  113  may transfer the fourth, first and second internal clocks ICLK&lt; 4 &gt;, ICLK&lt; 1 &gt; and ICLK&lt; 2 &gt; as the fourth, first and second data output clocks DOCLK&lt; 4 &gt;, DOCLK&lt; 1 &gt; and DOCLK&lt; 2 &gt;, respectively. 
     The clock pulse generation circuit  114  may generate the first clock pulse CLK_PL&lt; 1 &gt; with the third internal clock ICLK&lt; 3 &gt; in response to the first and fifth first shifting signals LTOE_A&lt; 1 &gt; and LTOE_A&lt; 5 &gt;. The third internal clock ICLK&lt; 3 &gt; may be sorted as the third data output clock DOCLK&lt; 3 &gt; by the first first shifting signal LTOE_A&lt; 1 &gt; during an interval corresponding to the burst length. The clock pulse generation circuit  114  may combine the first and fifth first shifting signals LTOE_A&lt; 1 &gt; and LTOE_A&lt; 5 &gt;, and generate the first clock pulse CLK_PL&lt; 1 &gt; with a clock pulse ({circumflex over (2)}) of the third internal clock ICLK&lt; 3 &gt; which is activated after the interval corresponding to the burst length. 
     The clock combination circuit  115  may combine the first to fourth data output clocks DOCLK&lt; 1 : 4 &gt; and the first clock pulse CLK_PL&lt; 1 &gt;, and generate the first to fourth final clocks CLK_FL&lt; 1 : 4 &gt;. The clock combination circuit  115  may generate the first to fourth final clocks CLK_FL&lt; 1 : 4 &gt; by combining neighboring clocks among the first to fourth data output clocks DOCLK&lt; 1 : 4 &gt;. In particular, the clock combination circuit  115  may generate the second final clock CLK_FL&lt; 2 &gt; by combining the second and third data output clocks DOCLK&lt; 2 : 3 &gt; with the first clock pulse CLK_PL&lt; 1 &gt;. 
     When the first mode signal LTOE_A is activated, the selection circuit  121  may sort the data RDATA&lt; 1 : 4 &gt; inputted through the first to fourth input nodes to the third, fourth, first and second output nodes, respectively, and sequentially output the sorted data DATA&lt; 3 &gt;&lt; 4 &gt;&lt; 1 &gt;&lt; 2 &gt;. The data serialization circuit  122  may sequentially serialize the sorted data DATA&lt; 3 &gt;&lt; 4 &gt;&lt; 1 &gt;&lt; 2 &gt; in response to the third, fourth, first and second final clocks CLK_FL&lt; 3 &gt;, CLK_FL&lt; 4 &gt;, CLK_FL&lt; 1 &gt; and CLK_FL&lt; 2 &gt;, and output the serialized data to the data pad DQ. 
     Referring to  FIG. 7B , when the read command RD is inputted in synchronization with the third internal clock ICLK&lt; 3 &gt; ({circumflex over (1)}), the mode decision circuit  112  may activate the second mode signal LTOE_B. The mode decision circuit  112  may generate the second shifting signals LTOE_B&lt; 1 : 5 &gt; by delaying the second mode signal LTOE_B by a time corresponding to read latency and shifting the delayed signal. 
     The second mode signal LTOE_B may be activated during an interval BL corresponding to the burst length. The second shifting signals LTOE_B&lt; 1 : 5 &gt; generated from the second mode signal LTOE_B may be used as output enable signals for enabling data output circuits according to a read operation. Although  FIG. 7B  illustrates five second shifting signals LTOE_B&lt; 1 : 5 &gt;, a plurality of shifting signals may be generated by shifting the second mode signal LTOE_B according to the positions of the data output circuits on the data path. 
     The clock arranging circuit  113  may transfer the first internal clock ICLK&lt; 1 &gt; as the first data output clock DOCLK&lt; 1 &gt; in response to the first second shifting signal LTOE_B&lt; 1 &gt;. Then, in response to the second to fourth second shifting signals LTOE_B&lt; 2 : 4 &gt; which are subsequently activated, the clock arranging circuit  113  may transfer the second to fourth internal clocks ICLK&lt; 2 : 4 &gt; as the second to fourth data output clocks DOCLK&lt; 2 : 4 &gt;, respectively. 
     The clock pulse generation circuit  114  may generate the second clock pulse CLK_PL&lt; 2 &gt; with the first internal clock ICLK&lt; 1 &gt; in response to the first and fifth second shifting signals LTOE_B&lt; 1 &gt; and LTOE_B&lt; 5 &gt;. The first internal clock ICLK&lt; 1 &gt; may be sorted as the first data output clock DOCLK&lt; 1 &gt; by the first second shifting signal LTOE_B&lt; 1 &gt; during an interval corresponding to the burst length. The clock pulse generation circuit  114  may combine the first and fifth second shifting signals LTOE_B&lt; 1 &gt; and LTOE_B&lt; 5 &gt;, and generate the second clock pulse CLK_PL&lt; 2 &gt; with a clock pulse ({circumflex over (2)}) of the first internal clock ICLK&lt; 1 &gt; which is activated after the interval corresponding to the burst length. 
     The clock combination circuit  115  may generate the first to fourth final clocks CLK_FL&lt; 1 : 4 &gt; by combining the first to fourth data output clocks DOCLK&lt; 1 : 4 &gt; and the second clock pulse CLK_PL&lt; 2 &gt;. The clock combination circuit  115  may generate the first to fourth final clocks CLK_FL&lt; 1 : 4 &gt; by combining neighboring clocks among the first to fourth data output clocks DOCLK&lt; 1 : 4 &gt;. In particular, the clock combination circuit  115  may generate the fourth final clock CLK_FL&lt; 4 &gt; by combining the fourth and first data output clocks DOCLK&lt; 4 &gt; and DOCLK&lt; 1 &gt; with the second clock pulse CLK_PL&lt; 2 &gt;. 
     When the second mode signal LTOE_B is activated, the selection circuit  121  may sort the data RDATA&lt; 1 : 4 &gt; inputted through the first to fourth input nodes for the first to fourth output nodes, respectively, and sequentially output the sorted data DATA&lt; 1 : 4 &gt;. The data serialization circuit  122  may sequentially serialize the sorted data DATA&lt; 1 : 4 &gt; and output the serialized data to the data pad DQ in response to the first to fourth final clocks CLK_FL&lt; 1 : 4 &gt;. 
     In accordance with the present embodiments, the memory device may generate a clock pulse according to the burst length of data from an input time point of a command, and generate internal clocks by dividing an external clock using the generated clock pulse. Therefore, the memory device may minimize the number of clocks which are toggled to generate the internal docks, thereby reducing current consumption. 
     When generating the internal clocks by dividing the external clocks, the memory device may adjust the sorting order of the internal clocks according to the input time point of the command. Therefore, regardless of the input time point of the command, the memory device can secure a constant valid window of data which are sorted and inputted/outputted based on the internal clocks. 
     Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.