Patent Publication Number: US-11664292-B2

Title: Semiconductor package

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a Continuation of U.S. application Ser. No. 16/507,974, filed Jul. 10, 2019, which issued as U.S. Pat. No. 11,056,414 on Jul. 6, 2021, and a claim of priority under 35 USC § 119 is made to Korean Patent Application No. 10-2018-0125678, filed Oct. 22, 2018, in the Korean Intellectual Property Office (KIPO), the disclosures of which are herein incorporated by reference in their entireties. 
    
    
     BACKGROUND 
     Example embodiments relate to a semiconductor package. More particularly, example embodiments relate to a system-in package including memory chips and a logic chip. 
     A system in package (SiP or system-in-a-package) generally includes multiple integrated circuits included in a same chip carrier package. For example, the system in package may include a plurality of memory chips and a logic chip mounted within a same chip carrier package. In this case, the memory chips and the logic chip may be electrically connected to each other via an interposer located between the chips and a system substrate of the system in package. Separately, the chips of the system in package may have differing thicknesses. For example, one or more memory chips may have a multi-chip structure of stacked memory chips. Thus, these multi-chip memory chips may have a thickness that may be greater than that of the logic chip. 
     SUMMARY 
     According to example embodiments, a semiconductor package may include a package substrate, an interposer located over an upper surface of the package substrate and electrically connected to the package substrate, a logic chip located over an upper surface of the interposer and electrically connected to the interposer, a memory chip located over the upper surface of the interposer and electrically connected to the interposer and to the logic chip, and a heat sink in thermal contact with an upper surface of the logic chip to dissipate heat in the logic chip. 
     According to example embodiments, a semiconductor package may include a package substrate, an interposer located over an upper surface of the package substrate and electrically connected with the package substrate, a logic chip located over an upper surface of the interposer and electrically connected with the interposer, and a memory chip located over the upper surface of the interposer and electrically connected with the interposer and the logic chip, where the memory chip has an upper surface that is higher than an upper surface of the logic chip. The semiconductor package may further include a heat sink making thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip, the heat sink having an upper surface that is coplanar with the upper surface of the memory chip, and a main heat sink making contact with the upper surfaces of the memory chip and the heat sink to dissipate heat in the memory chip and the heat sink. 
     According to example embodiments, a semiconductor package may include a package substrate, an interposer located over an upper surface of the package substrate and electrically connected with the package substrate, a logic chip located over an upper surface of the interposer and electrically connected with the interposer, a memory chip located over the upper surface of the interposer and electrically connected with the interposer and the logic chip, where the memory chip has an upper surface that may be higher than an upper surface of the logic chip. The semiconductor package may further included a main heat sink including a first lower surface making thermal contact with the upper surface of the memory chip, and a second lower surface of a heat-transferring portion extended from the lower surface and making thermal contact with the upper surface of the logic chip to dissipate heat in the memory chip and the logic chip. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Example embodiments will be more clearly understood from the detailed description that follows taken in conjunction with the accompanying drawings.  FIGS.  1  to  5    represent non-limiting, example embodiments as described herein. 
         FIG.  1    is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments; 
         FIG.  2    is a schematic plan view illustrating the semiconductor package in  FIG.  1   ; 
         FIG.  3    is a schematic plan view illustrating an interposer with chips mounted thereon of the semiconductor package in  FIG.  1   ; 
         FIG.  4    is a cross-sectional view illustrating a semiconductor package in accordance with other example embodiments; and 
         FIG.  5    is a cross-sectional view illustrating a semiconductor package in accordance with still other example embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings. 
       FIG.  1    is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments,  FIG.  2    is a schematic plan view of the semiconductor package illustrated in  FIG.  1   , and  FIG.  3    is a schematic plan view of an interposer having chips mounted thereon of the semiconductor package illustrated in  FIG.  1   . It is noted that the drawings are schematic representations only, and that the illustrated relative dimensions of  FIG.  1    differ from those of  FIGS.  2  and  3   . 
     In the example of the embodiment of  FIG.  1   , a semiconductor package includes a package substrate  110 , an interposer  120 , a logic chip  130 , a plurality of memory chips  140 , a heat sink  150  and an encapsulating member  180 . The semiconductor package may, for example, be a system in package (SiP). 
     The package substrate  110  may include conductive lines (not shown). Each of the conductive lines may include a conductive trace extending along an upper and/or lower surface of the package substrate  110 , and/or a conductive via extending between the upper and lower surfaces of the package substrate  110 . However, the embodiments may not be limited to any particular configuration of conductive lines of the package substrate  110 . Further, each of the conductive lines may have opposite ends terminating at external terminals  160  and  164 . The external terminals  160  may, for example, be solder balls or bumps located between the interposer  120  and the package substrate  110 . The external terminals  164  may, for example, be solder balls or bumps located on the lower surface of the package substrate  110 . Again, however, the embodiments may not be limited to any particular configuration of the external terminals  160  and  164 . 
     In the example of  FIGS.  1  to  3   , the interposer  120  may be arranged over the upper surface of the package substrate  110 . 
     The interposer  120  may include an insulating substrate, a plurality of connecting vias  122  (shown in  FIG.  1    only) and a plurality of conductive patterns  124  (shown in  FIG.  3    only). The connecting vias  122  may vertically extend through the insulating substrate such that an upper end may be exposed at an upper surface of the interposer  120 , and a lower end may be exposed at a lower surface of the interposer  120 . The lower ends of the connecting vias  122  may be electrically connected with the conductive lines in the package substrate  110  through the external terminals  160 . In this way, the package substrate  110  and the interposer  120  may be electrically connected with each other via the external terminals  160 . As shown in  FIG.  3   , the conductive patterns  124  may be arranged on the upper surface of the interposer  120 . 
     The logic chip  130  may be arranged on the upper surface of the interposer  120 . In example embodiments, the logic chip  130  may be arranged on a central portion of the upper surface of the interposer  120 . Pads may be arranged on a lower surface of the logic chip  130 . Thus, the lower surface of the logic chip  130  may correspond to an active face of the logic chip  130 . The logic chip  130  may be electrically connected with the interposer  120  through conductive bumps  162 . That is, the pads of the logic chip  130  may be electrically connected with the upper ends of the connecting vias  122  in the interposer  120  via the conductive bumps  162 . 
     Referring to  FIGS.  1  and  3   , the memory chips  140  may be arranged on the upper surface of the interposer  120 . Each of the memory chips  140  may include pads. The pads may be arranged on a lower surface of each of the memory chips  140 . Thus, the lower surface of the memory chip  140  may correspond to an active face of the memory chip  140 . The memory chips  140  may be electrically connected with the interposer  120  through the conductive bumps  162 . That is, the pads of the memory chips  140  may be electrically connected with the upper ends of the connecting vias  122  in the interposer  120  via the conductive bumps  162 . In example embodiments, at least one of memory chips  140  may include a high bandwidth memory (HBM) chip. 
     In example embodiments, the memory chips  140  may be arranged to surround the logic chip  130 . The memory chips  140  may be electrically connected with the logic chip  130  through the conductive patterns  124  on the upper surface of the interposer  120 . 
     Further, one or more of the memory chips  140  may have a multi-chip structure in which two or more memory chips are vertically stacked relative to the horizontal surface of the package substrate  110 . The number of stacked chips of each of the memory chips  140  may not be limited and may be four, eight, twelve, sixteen, etc. The multi-chip structure of the memory chips  140  may have a thickness which may be greater than that of the logic chip  130 . Therefore, the upper surface of the logic chip  130  may be positioned on a plane lower than that on which an upper surface of the memory chip  140  may be positioned. 
     The heat sink  150  may be arranged on the upper surface of the logic chip  130 . The heat sink  150  may make thermal contact with the upper surface of the logic chip  130  to dissipate heat generated from the logic chip  130 . The heat sink  150  may have a width which may be substantially the same as that of the logic chip  130 . The heat sink  150  may have a length which may be substantially the same as that of the logic chip  130 . Thus, the heat sink  150  may have side surfaces coplanar with those of the logic chip  130 . 
     In example embodiments, the heat sink  150  may have an upper surface coplanar with that of the memory chips  140 . Because the upper surface of the heat sink  150  may be coplanar with the upper surface of the memory chips  140 , a structure may be readily formed over the memory chips  140  by following processes. For example, as is described in a subsequent embodiment, a main heat sink for dissipating heat in the memory chips  140  may be easily arranged on the upper surfaces of the memory chips  140 . A thickness of the heat sink  150  may be determined in accordance with a thickness of the stacked memory chips  140 . Alternatively, the upper surface of the heat sink  150  may be higher or lower than that of the memory chips  140 . 
     The heat sink  150  may be a dummy chip. For example, a dummy chip determined to be defective in semiconductor fabrication processes may be used as the heat sink  150 . Thus, the heat sink  150  may include silicon of the dummy chip. 
     The heat sink  150  may be attached to the upper surface of the logic chip  130  using a heat-transferring adhesive  170 . The heat-transferring adhesive  170  may function to transfer the heat in the logic chip  130  to the heat sink  150 . In example embodiments, the heat-transferring adhesive  170  may include a thermal interface material (TIM). 
     The encapsulating member  180  may, for example, be formed by supplying an encapsulant into a mold containing the semiconductor package. The encapsulating member  180  may be arranged in a space between the upper surface of the interpose  120  and the lower surfaces of the memory chips  140 , a space between inner side surfaces of the memory chips  140  and outer side surfaces of the logic chip  130  and the heat sink  150 , and on outer side surfaces of the memory chips  140 . The encapsulating member  180  may have an upper surface coplanar with the upper surfaces of the memory chips  140  and the heat sink  150 . 
       FIG.  4    is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments. 
     In the example of the embodiment of  FIG.  4   , a semiconductor package may include a package substrate  110 , an interposer  120 , a logic chip  130 , a plurality of memory chips  140 , a heat sink  150 , a main heat sink  155  and an encapsulating member  180 . 
     The package substrate  110 , the interposer  120 , the logic chip  130 , the memory chips  140 , the heat sink  150  and the encapsulating member  180  of  FIG.  4    may be the same or substantially the same as those of  FIGS.  1 - 3    described previously. As such, a detailed description of such elements is omitted here to avoid redundancy. 
     The example of  FIG.  4    differs from that of  FIGS.  1 - 3    by the additional provision of a main heat sink  155 . 
     Referring to  FIG.  4   , the main heat sink  155  may be arranged on the upper surfaces of the memory chips  140  and the heat sink  150 . The main heat sink  155  may dissipate the heat in the memory chips  140  and the heat in the heat sink  150 . That is, the main heat sink  155  may directly dissipate the heat in the memory chips  140 . Further, the main heat sink  155  may indirectly dissipate the heat in the logic chip  130  through the heat sink  150 . 
     In example embodiments, the main heat sink  155  may have a flat lower surface. As mentioned above, because the upper surfaces of the heat sink  150  and the memory chips  140  may be coplanar with each other, a contact area between the flat lower surface of the main heat sink  155  and the upper surfaces of the heat sink  150  and the memory chips  140  may be expanded. Therefore, heat transfer ratio from the heat sink  150  and the memory chips  140  to the main heat sink  155  may be enhanced. 
     The main heat sink  155  may be attached to the upper surfaces of the memory chips  140  and the heat sink  150  using a heat-transferring adhesive  172 . The heat-transferring adhesive  172  may transfer the heat in the memory chips  140  and the heat sink  150  to the main heat sink  155 . In example embodiments, the heat-transferring adhesive  172  may include a thermal interface material (TIM). 
     In example embodiments, the main heat sink  155  may have an outer side surface coplanar with the outer side surface of the encapsulating member  180 . Alternatively, the outer side surface of the main heat sink  155  may be horizontally protruded from the outer side surface of the encapsulating member  180  as in the example shown in  FIG.  4   . Further, the main heat sink  155  may include a metal. Alternatively, the main heat sink  155  may include silicon. 
       FIG.  5    is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments. 
     In the example of the embodiment of  FIG.  5   , a semiconductor package may include a package substrate  110 , an interposer  120 , a logic chip  130 , a plurality of memory chips  140 , an integrated heat sink  190  and an encapsulating member  180 . 
     The package substrate  110 , the interposer  120 , the logic chip  130 , the memory chips  140  and the encapsulating member  180  of  FIG.  5    may be the same or substantially the same as those of  FIGS.  1 - 3    described previously. As such, a detailed description of such elements is omitted here to avoid redundancy. 
     The example of  FIG.  5    differs from that of  FIG.  4    in that the heat sink  150  and the main heat sink  155  of  FIG.  4    are replaced with the integrated heat sink  190  of FIG.  5 . As shown in  FIG.  5   , the integrated heat sink  190  may be a one-piece heat sink located over the upper surfaces of the memory chips  140 , with a heat-transferring portion  192  centrally located and protruding downwardly over the upper surface of the logic chip  130 . That is, as in the example of  FIG.  5   , the integrated heat sink  190  may have a first lower surface configured to make thermal contact with the upper surfaces of the memory chips  140  using the heat-transferring adhesive  172 , and a second lower surface of the heat-transferring portion  192  surrounded by and lower than the first lower surface and configured to make thermal contact with the upper surface of the logic chip  130  using the heat-transferring adhesive  172 . The integrated heat sink  190  may, as examples, be formed of a metal or silicon. 
     In the example of  FIG.  5   , heat generated in the logic chip  130  may be dissipated through the central lower flat surface (i.e., the lower surface of the heat-transferring portion  192 ) of the integrated heat sink  190 , and heat generated in the memory chips  140  may be dissipated through the outer lower flat surface of the integrated heat sink  190 . 
     According to example embodiments, the heat sink may make contact with the upper surface of the logic chip to effectively dissipate the heat in the logic chip through the heat sink. Further, the upper surface of the heat sink may be coplanar with the upper surface of the memory chip to expand a contact area between the main heat sink and the memory chip, and between the main heat sink and the upper surface of the heat sink. As a result, the heat in the logic chip and the memory chip may be effectively dissipated through the main heat sink. 
     The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concepts. Accordingly, all such modifications are intended to be included within the scope of the present inventive concepts as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.