Patent Publication Number: US-11050250-B2

Title: Static transfer switch system with real time flux control

Description:
This application claims the benefit of and priority to U.S. Provisional Application No. 62/248,483 filed on Oct. 30, 2015, the content of which is hereby incorporated herein by reference in its entirety. 
    
    
     FIELD 
     The embodiment relates to transfer switches for toggling between two power sources and, more particularly, to an improved transfer switch system that utilizes real time flux control. 
     BACKGROUND 
     A static transfer switch is a device that is meant to toggle from a preferred voltage source to an alternate voltage source when the power quality of the preferred voltage source is deemed unacceptable for the load. The output of the static transfer switch connects to a preferred side of a delta-to-wye transformer as the load. Conventional static transfer switches have many shortcomings such as:
         1. High preferred inrush current can be produced and is capable of damaging and degrading electrical equipment. It may also cause unwanted behavior for an uninterruptable power supply upstream that feeds the static transfer switch,   2. Longer than expected transfer time beyond the tolerance of the critical load,   3. Performance is bound to a specific transformer and can degrade if other types are used.       

     Thus, there is a need to provide a static transfer switch system that overcomes the issues mentioned above. 
     SUMMARY 
     An object of the invention is to fulfill the need referred to above. In accordance with the principles of the embodiment, this objective is achieved by providing a static transfer switch assembly including a transfer switch constructed and arranged to be connected with a preferred power source and an alternate power source, and a load so that the transfer switch can selectively connect either of the preferred or alternate power sources to the load. A first digital signal processor circuit is associated with the preferred power source to detect a power quality event at the preferred power source. A second digital signal processor circuit is associated with the alternate power source to detect a power quality event at the alternate power source. A third digital signal processor circuit is in communication with each of the first and second digital signal processors and in communication with the transfer switch. The third digital signal processor circuit is constructed and arranged 1) to compute and balance flux in real time based on digitized sample voltages received from each of the preferred and alternate power sources, and 2) to control the transfer switch to transfer the load from one of the power sources to the other power source, based on one of the first or second digital signal processor circuits detecting a power quality event on the one power source. 
     In accordance with another aspect of an embodiment, a method is provided for transferring a load between two power sources. The method provides a transfer switch assembly including a transfer switch connected with a preferred power source and an alternate power source, and the load so that the transfer switch can selectively connect either of the preferred or alternate power sources to the load, a first digital signal processor circuit associated with the preferred power source to detect a power quality event at the preferred power source, a second digital signal processor circuit associated with the alternate power source to detect a power quality event at the alternate power source, and a third digital signal processor circuit in communication with each of the first and second digital signal processors and in communication with the transfer switch. A voltage of the preferred power source is sampled with the first digital signal processor circuit and a voltage of the alternate power source is sampled with the second digital signal processor circuit. The third digital signal processor circuit receives the sampled voltages from each of the first and second digital signal processor circuits in real time. The method determines if a power event was detected by first or second digital signal processor circuits based on the received sample voltages. The third digital signal processor circuit computes and balances flux in real time, and controls the transfer switch to transfer the load from one of the power sources to the other power source, based on one of the first or second digital signal processor circuits detecting a power quality event on the one power source. 
     Other objectives, features and characteristics of the embodiments, as well as the methods of operation and the functions of the related elements of the structure, the combination of parts and economics of manufacture will become more apparent upon consideration of the following detailed description and appended claims with reference to the accompanying drawings, all of which form a part of this specification. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will be better understood from the following detailed description of the preferred embodiments thereof, taken in conjunction with the accompanying drawings wherein like numbers indicate like parts, in which: 
         FIG. 1  is a schematic view of a static transfer switch system provided in accordance with an embodiment of the present invention. 
         FIG. 2  is a detailed view of the static transfer switch system of  FIG. 1 . 
         FIG. 3  is a flowchart of a method performed by the static transfer switch system of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     With reference to  FIGS. 1 and 2 , schematic view of a static transfer switch system, generally indicated at  10 , is shown provided in accordance with an embodiment. The system  10  includes a conventional transfer switch  12  constructed and arranged to selectively connect either a preferred power source  14  (Source1) or an alternate power source  16  (Source 2) to a load  18 , such as a delta-to-wye transformer. The power sources  14 ,  16  are AC power sources. The transfer switch  12  includes the conventional silicon controlled rectifier (SCR) associated with each phase, with one SCR  19  and an associated conventional gate drive  21  shown in  FIG. 1  as an example. The transfer switch  12  can be of the type as disclosed, for example, in U.S. Pat. No. 7,932,635, the content of which is hereby incorporated by reference into this specification. 
     The system  10  also includes a first digital signal processor circuit (DSP1)  20  associated with the preferred power source  14  to detect a power quality event at the preferred power source  14 . A second digital signal processor circuit (DSP2)  22  is associated with the alternate power source  16  to detect a power quality event at the alternate power source  16 . A third digital signal processor circuit (DSP3)  24  is in communication with each of the first and second digital signal processor circuits  20 ,  22 , respectively, and is also in communication with the transfer switch  12 . 
     The third digital signal processor circuit  24  integrates the voltages at  26  to compute a per unit flux in real time:
 
λ=∫ν· dt  
         where λ is the normalized flux and ν is the voltage at the power source.       

     The third digital signal processor circuit  24  computes the fluxes after receiving digitized sample voltages from both the preferred and alternate power sources  14  and  16  as monitored by the first and second digital signal processor circuits  20  and  22 , respectively. The third digital signal processor circuit  24  then determines the optimal time for operating the transfer switch  12  to transfer the critical load  18  to the alternate power source  16  if the first digital signal processor circuit  20  detect a power quality event (e.g., power outside a set range) at the preferred power source  14 . The algorithm of the embodiment also allows for an error margin so a tradeoff can be realized between the transformer inrush and transfer time: 
                   {             λ1   =     ∫     v   ⁢           ⁢   1   ⁢       (   t   )     ·   dt                     λ2   =     ∫     v   ⁢           ⁢   2   ⁢       (   t   )     ·   dt                 ⇔            λ1   -   λ2          ≤   ϵ               Equation   ⁢           ⁢   1               
where:
         λ1 is the normalized three phase fluxes of the preferred power source  14 .   λ2 is the normalized three phase fluxes of the alternate power source  16 .   ϵ is an arbitrary error value allowing the tradeoff between peak inrush current and transfer time.       

     The power sources  14  and  16  are preferably three-phase power sources (phases A, B, C). Thus, in particularly with reference to  FIG. 3 , the third digital signal processor circuit  24  continuously computes the three phase fluxes of the preferred power source  14  (Source 1) and the three phase fluxes of the alternate power source  16  (Source2). The third digital signal processor circuit  24  continuously computes the normalized fluxes as shown below: 
     
       
         
           
             { 
             
               
                 
                   
                     
                       λ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       A_primary 
                     
                   
                   
                     = 
                   
                   
                     
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                         vA_primary 
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                             ( 
                             t 
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                           · 
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                       λ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       B_primary 
                     
                   
                   
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                       λ 
                       ⁢ 
                       
                           
                       
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                       C_primary 
                     
                   
                   
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                           · 
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               ⁢ 
               
                 
 
               
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                         A_secondary 
                       
                     
                     
                       = 
                     
                     
                       
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                           ⁢ 
                           
                             
                               ( 
                               t 
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                         λ 
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                         B_secondary 
                       
                     
                     
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                           ⁢ 
                           
                             
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                               ( 
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     If the power quality of the preferred power source  14  is not within a range that the customer defines in the power quality limits settings due to an external power quality event, an emergency transfer is needed. In that case, the transfer switch  12  needs to transfer to the alternate power source  16  and the third digital signal processor circuit  24 , using summing circuits  27 , starts computing Equation 1 as: 
     
       
         
           
             
               
                 
                   { 
                   
                     
                       
                         
                           
                              
                             
                               
                                 λ 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 A_secondary 
                               
                               - 
                               
                                 λ 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 A_primary 
                               
                             
                              
                           
                           ≤ 
                           ϵ 
                         
                       
                     
                     
                       
                         
                           
                              
                             
                               
                                 λ 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 B_secondary 
                               
                               - 
                               
                                 λ 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 B_primary 
                               
                             
                              
                           
                           ≤ 
                           ϵ 
                         
                       
                     
                     
                       
                         
                           
                              
                             
                               
                                 λ 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 C_secondary 
                               
                               - 
                               
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                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 C_primary 
                               
                             
                              
                           
                           ≤ 
                           ϵ 
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
             
           
         
       
     
     The algorithm executed by the third digital signal processor circuit  24  determines the very first phase that satisfies Equation 1 and then automatically commands the associated gate drive  21  to fire that phase. This is repeated once again to complete firing all the SCRs  19 . Should there be an instance where all phases are satisfying the Equation 1 above, all of phases will be fired substantially simultaneously. 
     The error ϵ is kept as small as possible to completely eliminate inrush current. However, if one wants to tolerate some inrush and speed up the transfer, the algorithm executed by third digital signal processor circuit  24  will increase the value of the error as set by the software. 
     Thus, the third digital signal processor circuit  24  (DSP3) is constructed and arranged to compute and balance fluxes of the preferred power source  14  and alternate power source  16  in real time based on digitized sample voltages received from each of the preferred and alternate power sources. The third digital signal processor circuit  24  (DSP3) also is constructed and arranged to determine an optimal time to control the transfer switch  12  to cause the transfer switch  12  to switch power to the load  18  from the preferred power source  14  to the alternate power source  16 , based on the first digital signal processor circuit  20  detecting a power quality event on the preferred power source  14 . In this way, power to the load  18  is not interrupted and inrush current and transfer time are each minimized. 
     More specifically, with reference to  FIG. 3 , the steps or algorithm for performing a method of transferring a load  18  between the two power sources  14 ,  16  are shown where in step  30 , DSP1 samples the voltage of the preferred power source  14  while in step  32 , DSP2 samples the voltage of the alternate power source  16 . In step  34 , DSP1 sends the sample voltages which are received by DSP3 in step  36 . In addition, in step  38 , DSP2 sends the sample voltages which are received by DSP3 in step  36 . In the embodiment, the voltage samples are sent or received about every 130 μs (e.g., in real time). In step  40 , DSP3 determines if a power event (such as power outside a set range) was detected by DSP1 or DSP2 based on the received sample voltages. If not, the sampled voltages are continued to be monitored. If a power event was detected for example by DSP1, in step  42 , DSP3 computes the flux balancing equation (Equation 1 above). 
     DSP3 then computes the switching angles in step  44 . This done in the gate drives  21 . The communication link between the DSP3 and the gate drives  21  is so fast that the gate drives  21  are able to fire all phases at the same time if it is controlled to do so. This produces the appropriate waveform with the switching angle command by the DSP3. 
     It can be appreciated that instead of using integral calculations for flux determination, the flux can be determined in other manners such as using the Trapezoidal rule. Since the fluxes are normalized, the assembly  10  is tolerant to any type of transfers and is not bound to a specific KVA rating, making the method suitable for many load types. 
     The embodiment enables the customer to have flexibility to allow for a pre-determined amount of inrush current to speed up transfer time, making the method very customizable. The embodiment allows for firing any SCRs or all of them as deemed acceptable by the algorithm allowing the user to do super transfers if the fluxes of the alternate source are deemed satisfactory to equation 1. This is possible only under certain cases if the phase difference between the two sources allows for such a condition to happen. If a super transfer done, then the transfer is accomplish very quickly, with the transfer plus sense time occurring in less than 8 milliseconds. 
     It can be appreciated that instead of using integral calculations for flux determination, the flux can be determined in other manners such as using the Trapezoidal rule. Since the fluxes are normalized, the assembly  10  is tolerant to any type of transfers and is not bound to a specific KVA rating, making the method suitable for many load types. 
     The digital signal processor circuits disclosed herein can be of the type TMS320C6746, manufactured by Texas Instruments. 
     The operations and algorithms described herein can be implemented as executable code within the third digital signal processor circuit  24 , or stored on a standalone computer or machine readable non-transitory tangible storage medium that are completed based on execution of the code by a processor circuit implemented using one or more integrated circuits. Example implementations of the disclosed circuits include hardware logic that is implemented in a logic array such as a programmable logic array (PLA), a field programmable gate array (FPGA), or by mask programming of integrated circuits such as an application-specific integrated circuit (ASIC). Any of these circuits also can be implemented using a software-based executable resource that is executed by a corresponding internal processor circuit such as a microprocessor circuit (not shown) and implemented using one or more integrated circuits, where execution of executable code stored in an internal memory circuit (e.g., within the memory circuit  28 ) causes the integrated circuit(s) implementing the third digital signal processor circuit  24  to store application state variables in processor memory, creating an executable application resource (e.g., an application instance) that performs the operations of the circuit as described herein. Hence, use of the term “circuit” in this specification refers to both a hardware-based circuit implemented using one or more integrated circuits and that includes logic for performing the described operations, or a software-based circuit that includes a processor circuit (implemented using one or more integrated circuits), the processor circuit including a reserved portion of processor memory for storage of application state data and application variables that are modified by execution of the executable code by a processor circuit. The memory circuit  28  can be implemented, for example, using a non-volatile memory such as a programmable read only memory (PROM) or an EPROM, and/or a volatile memory such as a DRAM, etc. 
     The foregoing preferred embodiments have been shown and described for the purposes of illustrating the structural and functional principles of the present invention, as well as illustrating the methods of employing the preferred embodiments and are subject to change without departing from such principles. Therefore, this invention includes all modifications encompassed within the spirit of the following claims.