Patent Publication Number: US-2018047435-A1

Title: Semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2016-0103294 filed on Aug. 12, 2016 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     Embodiments of the present disclosure may generally relate to a semiconductor device which inputs and outputs data in synchronization with a strobe signal. 
     2. Related Art 
     In a synchronous semiconductor device, a command and an address are inputted in synchronization with a clock. In a DDR (double data rate) synchronous semiconductor device, a command and an address are inputted in synchronization with the rising edge and the falling edge of a clock. In an SDR (single data rate) synchronous semiconductor device, a command and an address are inputted in synchronization with the rising edge of a clock. 
     SUMMARY 
     In an embodiment, a semiconductor device may be provided. The semiconductor device may include a signal mixing circuit suitable for generating a strobe signal which toggles in synchronization with a divided clock. The semiconductor device may include a signal transfer circuit suitable for transmitting the strobe signal, and including at least one repeater which amplifies and transmits the strobe signal. 
     In an embodiment, a semiconductor device may be provided. The semiconductor device may include a signal mixing circuit configured for generating a strobe signal based on combining a divided clock and a preamble signal during a preamble period. The semiconductor device may include a signal transfer circuit suitable for transmitting the strobe signal, and including at least one repeater which amplifies and transmits the strobe signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a representation of an example of the configuration of a semiconductor device in accordance with an embodiment. 
         FIG. 2  is a circuit diagram illustrating a representation of an example of the internal configuration of the signal mixing circuit included in the semiconductor device illustrated in  FIG. 1 . 
         FIG. 3  is a representation of an example of a timing diagram to assist in the explanation of the operations of the control circuit and the signal mixing circuit included in the semiconductor device illustrated in  FIG. 1 . 
         FIG. 4  is a block diagram illustrating a representation of an example of the internal configuration of the first signal transfer circuit included in the semiconductor device illustrated in  FIG. 1 . 
         FIG. 5  is a circuit diagram illustrating a representation of an example of the internal configuration of the buffer circuit included in the first signal transfer circuit illustrated in  FIG. 4 . 
         FIG. 6  is a representation of an example of a timing diagram to assist in the explanation of the operation of the buffer circuit included in the first signal transfer circuit, illustrated in  FIG. 5 . 
         FIG. 7  is a diagram illustrating a representation of an example of the internal configuration of the first internal strobe signal generation circuit included in the semiconductor device illustrated in  FIG. 1 . 
         FIG. 8  is a representation of an example of a timing diagram to assist in the explanation of the operation of the first internal strobe signal generation circuit included in the semiconductor device, illustrated in  FIG. 7 . 
         FIG. 9  is a diagram illustrating a representation of an example of the configuration of an electronic system to which the semiconductor device illustrated in  FIGS. 1 to 8  is applied. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, a semiconductor device will be described below with reference to the accompanying drawings through various examples of embodiments. 
     Various embodiments may be directed to a semiconductor device which generates a strobe signal by mixing a divided clock and a preamble signal during a preamble period and outputs the strobe signal through a plurality of repeaters to a pad. 
     According to the embodiments, a strobe signal may be generated by mixing a divided clock and a preamble signal during a preamble period, and the strobe signal may be outputted through a plurality of repeaters to a pad. As a consequence, it may be possible to prevent a mismatch of the divided clock and the preamble signal due to a long transfer path. 
     Referring to  FIG. 1 , a semiconductor device in accordance with an embodiment may include a control circuit  10 , a signal mixing circuit  20 , a signal transfer circuit  30 , a first bank  40 , and a second bank  50 . 
     The control circuit  10  may generate first to fourth divided clocks DCLK&lt; 1 : 4 &gt; by dividing the frequency of an external clock CLK in response to a read command RD. The control circuit  10  may generate a first preamble signal PRE&lt; 1 &gt; and a second preamble signal PRE&lt; 2 &gt; which include pulses generated during a preamble period, in response to the read command RD. The first to fourth divided clocks DCLK&lt; 1 : 4 &gt; may be set to have a phase difference corresponding to the ¼ cycle of the external clock CLK. The pulse of the second preamble signal PRE&lt; 2 &gt; may be set to be generated after the ¼ cycle of the external clock CLK from the pulse generation time of the first preamble signal PRE&lt; 1 &gt;. The preamble period may be set as a period for the external clock CLK to be stabilized after the read command RD is inputted. 
     The signal mixing circuit  20  may generate first to fourth strobe signals DQS&lt; 1 : 4 &gt; by mixing the first to fourth divided clocks DCLK&lt; 1 : 4 &gt; and the first and second preamble signals PRE&lt; 1 : 2 &gt;. The signal mixing circuit  20  may generate the third and fourth strobe signals DQS&lt; 3 : 4 &gt; which toggle in synchronization with the first preamble signal PRE&lt; 1 &gt; and the second preamble signal PRE&lt; 2 &gt; during the preamble period. The signal mixing circuit  20  may generate the first to fourth strobe signals DQS&lt; 1 : 4 &gt; which toggle in synchronization with the first to fourth divided clocks DCLK&lt; 1 : 4 &gt; after the preamble period. 
     The signal transfer circuit  30  may include a first signal transfer circuit  31  and a second signal transfer circuit  32 . 
     The first signal transfer circuit  31  may be realized to include at least one repeater. The first signal transfer circuit  31  may generate first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; by amplifying the first to fourth strobe signals DQS&lt; 1 : 4 &gt; through at least one repeater. The first signal transfer circuit  31  may transmit the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; to a first pad  41 . The number of repeaters included in the first signal transfer circuit  31  may be set variously depending on the length of a path through which the first to fourth strobe signals DQS&lt; 1 : 4 &gt; are transmitted. For example, realization may be made such that the number of repeaters included in the first signal transfer circuit  31  increases as the length of a path through which the first to fourth strobe signals DQS&lt; 1 : 4 &gt; are transferred is lengthened. 
     The second signal transfer circuit  32  may be realized to include at least one repeater. The second signal transfer circuit  32  may generate fifth to eighth transfer strobe signals TDQS&lt; 5 : 8 &gt; by amplifying the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; through at least one repeater. The second signal transfer circuit  32  may transmit the fifth to eighth transfer strobe signals TDQS&lt; 5 : 8 &gt; to a third pad  51 . The number of repeaters included in the second signal transfer circuit  32  may be set variously depending on the length of a path through which the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; are transmitted. For example, realization may be made such that the number of repeaters included in the second signal transfer circuit  32  increases as the length of a path through which the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; are transferred is lengthened. 
     The signal transfer circuit  30  in accordance with an embodiment, configured as mentioned above, may include at least one repeater, and may amplify the first to fourth strobe signals DQS&lt; 1 : 4 &gt; through at least one repeater and transmit resultant signals to the first pad  41  and the third pad  51 . 
     The first bank  40  may include the first pad  41 , a second pad  42 , a first internal strobe signal generation circuit  43 , a first memory region  44 , and a first input/output circuit  45 . 
     The first internal strobe signal generation circuit  43  may generate a first internal strobe signal IDQS&lt; 1 &gt; by mixing the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; received from the first pad  41 . An operation of generating the first internal strobe signal IDQS&lt; 1 &gt; by mixing the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; will be explained later through a configuration which will be described later. 
     The first memory region  44  may store first internal data ID&lt; 1 &gt; in a write operation, and may output the stored first internal data ID&lt; 1 &gt; in a read operation. The first memory region  44  may be realized by a volatile memory device or a nonvolatile memory device which includes a plurality of memory cell arrays. 
     The first input/output circuit  45  may input/output the first internal data ID&lt; 1 &gt; through the second pad  42  in synchronization with the first internal strobe signal IDQS&lt; 1 &gt;. The first input/output circuit  45  may output data DQ inputted through the second pad  42  in the write operation, as the first internal data ID&lt; 1 &gt;, in synchronization with the first internal strobe signal IDQS&lt; 1 &gt;. The first input/output circuit  45  may output the first internal data ID&lt; 1 &gt; as data DQ through the second pad  42  in synchronization with the first internal strobe signal IDQS&lt; 1 &gt;, in the read operation. 
     The first bank  40  in accordance with an embodiment, configured as mentioned above, may store the data DQ inputted through the second pad  42 , as the first internal data ID&lt; 1 &gt;, in synchronization with the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; transmitted to the first pad  41 , in the write operation. The first bank  40  may output the first internal data ID&lt; 1 &gt; through the second pad  42 , as the data DQ, in synchronization with the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; transmitted to the first pad  41 , in the read operation. 
     The second bank  50  may include the third pad  51 , a fourth pad  52 , a second internal strobe signal generation circuit  53 , a second memory region  54 , and a second input/output circuit  55 . 
     The second internal strobe signal generation circuit  53  may generate a second internal strobe signal IDQS&lt; 2 &gt; by mixing the fifth to eighth transfer strobe signals TDQS&lt; 5 : 8 &gt; received from the third pad  51 . An operation of generating the second internal strobe signal IDQS&lt; 2 &gt; by mixing the fifth to eighth transfer strobe signals TDQS&lt; 5 : 8 &gt; may be the same or substantially the same as the operation of generating the first internal strobe signal IDQS&lt; 1 &gt;, and thus, will be explained in later through a configuration which will be described later. 
     The second memory region  54  may store second internal data ID&lt; 2 &gt; in a write operation, and may output the stored second internal data ID&lt; 2 &gt; in a read operation. The second memory region  54  may be realized by a volatile memory device or a nonvolatile memory device which includes a plurality of memory cell arrays. 
     The second input/output circuit  55  may input/output the second internal data ID&lt; 2 &gt; through the fourth pad  52  in synchronization with the second internal strobe signal IDQS&lt; 2 &gt;. The second input/output circuit  55  may output data DQ inputted through the fourth pad  52  in the write operation, as the second internal data ID&lt; 2 &gt;, in synchronization with the second internal strobe signal IDQS&lt; 2 &gt;. The second input/output circuit  55  may output the second internal data ID&lt; 2 &gt; as data DQ through the fourth pad  52  in synchronization with the second internal strobe signal IDQS&lt; 2 &gt;, in the read operation. 
     The second bank  50  in accordance with an embodiment, configured as mentioned above, may store the data DQ inputted through the fourth pad  52 , as the second internal data ID&lt; 2 &gt;, in synchronization with the fifth to eighth transfer strobe signals TDQS&lt; 5 : 8 &gt; transmitted to the third pad  51 , in the write operation. The second bank  50  may output the second internal data ID&lt; 2 &gt; through the fourth pad  52 , as the data DQ, in synchronization with the fifth to eighth transfer strobe signals TDQS&lt; 5 : 8 &gt; transmitted to the third pad  51 , in the read operation. 
     Referring to  FIG. 2 , the signal mixing circuit  20  in accordance with an embodiment may include a first mixing circuit  210 , a second mixing circuit  220 , a third mixing circuit  230 , and a fourth mixing circuit  240 . 
     The first mixing circuit  210  may be realized by a NAND gate ND 21  and an inverter IV 21 , and may generate the first strobe signal DQS&lt; 1 &gt; by buffering the first divided clock DCLK&lt; 1 &gt; in response to a power supply voltage VDD. The first mixing circuit  210  may generate the first strobe signal DQS&lt; 1 &gt; by performing an AND logic function on the power supply voltage VDD and the first divided clock DCLK&lt; 1 &gt;. The power supply voltage VDD may be set to a logic high level. 
     The second mixing circuit  220  may be realized by a NAND gate ND 22  and an inverter IV 22 , and may generate the second strobe signal DQS&lt; 2 &gt; by buffering the second divided clock DCLK&lt; 2 &gt; in response to the power supply voltage VDD. The second mixing circuit  220  may generate the second strobe signal DQS&lt; 2 &gt; by performing an AND logic function on the power supply voltage VDD and the second divided clock DCLK&lt; 2 &gt;. 
     The third mixing circuit  230  may be realized by a NAND gate ND 23  and an inverter IV 23 , and may generate the third strobe signal DQS&lt; 3 &gt; by mixing the pulse of the first preamble signal PRE&lt; 1 &gt; and the pulse of the third divided clock DCLK&lt; 3 &gt;. The third mixing circuit  230  may generate the third strobe signal DQS&lt; 3 &gt; by performing an AND logic function on the first preamble signal PRE&lt; 1 &gt; and the third divided clock DCLK&lt; 3 &gt;. 
     The fourth mixing circuit  240  may be realized by a NAND gate ND 24  and an inverter IV 24 , and may generate the fourth strobe signal DQS&lt; 4 &gt; by mixing the pulse of the second preamble signal PRE&lt; 2 &gt; and the pulse of the fourth divided clock DCLK&lt; 4 &gt;. The fourth mixing circuit  240  may generate the fourth strobe signal DQS&lt; 4 &gt; by performing an AND logic function on the second preamble signal PRE&lt; 2 &gt; and the fourth divided clock DCLK&lt; 4 &gt;. 
     The operation of the control circuit  10  in accordance with an embodiment will be described below with reference to  FIG. 3  by being divided into an operation during the preamble period and an operation after the preamble period. 
     Before making descriptions, a preamble period P is set to a period between times T 1  and T 3  as the ½ cycle of the external clock CLK. According to an embodiment, the preamble period P may be set to one or more cycles of the external clock CLK. 
     The control circuit  10  may generate the first preamble signal PRE&lt; 1 &gt; which includes a pulse generated between times T 1  and T 3  during the preamble period P. 
     The control circuit  10  may generate the second preamble signal PRE&lt; 2 &gt; which includes a pulse generated between times T 2  and T 4  during the preamble period P. 
     After the preamble period P, the control circuit  10  generates the first divided clock DCLK&lt; 1 &gt; which includes a first pulse between times T 3  and T 5  and a second pulse between times T 7  and T 9 , by dividing the frequency of the external clock CLK. 
     After the preamble period P, the control circuit  10  generates the second divided clock DCLK&lt; 2 &gt; which includes a first pulse between times T 4  and T 6  and a second pulse between times T 8  and T 10 , by dividing the frequency of the external clock CLK. 
     After the preamble period P, the control circuit  10  generates the third divided clock DCLK&lt; 3 &gt; which includes a first pulse between times T 5  and T 7  and a second pulse between times T 9  and T 11 , by dividing the frequency of the external clock CLK. 
     After the preamble period P, the control circuit  10  generates the fourth divided clock DCLK&lt; 4 &gt; which includes a first pulse between times T 6  and T 8  and a second pulse between times T 10  and T 12 , by dividing the frequency of the external clock CLK. 
     The pulses included in the first and second preamble signals PRE&lt; 1 : 2 &gt; and the first to fourth divided clocks DCLK&lt; 1 : 4 &gt; mean periods in which the pulses are generated at, for example but not limited to, a logic low level. Further, the logic levels of the signals may be different from or the opposite of those described. For example, a signal described as having a logic “high” level may alternatively have a logic “low” level, and a signal described as having a logic “low” level may alternatively have a logic “high” level. 
     In this way, the control circuit  10  in accordance with an embodiment generates the first preamble signal PRE&lt; 1 &gt; and the second preamble signal PRE&lt; 2 &gt; which include pulses generated during the preamble period. The control circuit  10  generates the pulse of the second preamble signal PRE&lt; 2 &gt; after the ¼ cycle of the external clock CLK from the pulse generation time of the first preamble signal PRE&lt; 1 &gt;. After the preamble period, the control circuit  10  generates the first to fourth divided clocks DCLK&lt; 1 : 4 &gt; which have the phase difference corresponding to the ¼ cycle of the external clock CLK, by dividing the frequency of the external clock CLK. 
     The operation of the signal mixing circuit  20  in accordance with an embodiment will be described below with reference to  FIG. 3 . 
     After the preamble period P, the first mixing circuit  210  generates the first strobe signal DQS&lt; 1 &gt; which includes a first pulse between times T 3  and T 5  and a second pulse between times T 7  and T 9 , by buffering the first divided clock DCLK&lt; 1 &gt; in response to the power supply voltage VDD. 
     After the preamble period P, the second mixing circuit  220  generates the second strobe signal DQS&lt; 2 &gt; which includes a first pulse between times T 4  and T 6  and a second pulse between times T 8  and T 10 , by buffering the second divided clock DCLK&lt; 2 &gt; in response to the power supply voltage VDD. 
     During the preamble period P, the third mixing circuit  230  generates the first pulse of the third strobe signal DQS&lt; 3 &gt; between times T 1  and T 3 , by mixing the pulse of the first preamble signal PRE&lt; 1 &gt; and the third divided clock DCLK&lt; 3 &gt;. After the preamble period P, the third mixing circuit  230  generates the second pulse of the third strobe signal DQS&lt; 3 &gt; between times T 5  and T 7 , by mixing the first preamble signal PRE&lt; 1 &gt; and the first pulse of the third divided clock DCLK&lt; 3 &gt;. After the preamble period P, the third mixing circuit  230  generates the third pulse of the third strobe signal DQS&lt; 3 &gt; between times T 9  and T 11 , by mixing the first preamble signal PRE&lt; 1 &gt; and the second pulse of the third divided clock DCLK&lt; 3 &gt;. 
     During the preamble period P, the fourth mixing circuit  240  generates the first pulse of the fourth strobe signal DQS&lt; 4 &gt; between times T 2  and T 4 , by mixing the pulse of the second preamble signal PRE&lt; 2 &gt; and the fourth divided clock DCLK&lt; 4 &gt;. After the preamble period P, the fourth mixing circuit  240  generates the second pulse of the fourth strobe signal DQS&lt; 4 &gt; between times T 6  and T 8 , by mixing the second preamble signal PRE&lt; 2 &gt; and the first pulse of the fourth divided clock DCLK&lt; 4 &gt;. After the preamble period P, the fourth mixing circuit  240  generates the third pulse of the fourth strobe signal DQS&lt; 4 &gt; between times T 10  and T 12 , by mixing the second preamble signal PRE&lt; 2 &gt; and the second pulse of the fourth divided clock DCLK&lt; 4 &gt;. 
     The pulses included in the first to fourth strobe signals DQS&lt; 1 : 4 &gt; mean periods in which the pulses are generated at, for example but not limited to, a logic low level. Further, the logic levels of the signals may be different from or the opposite of those described. For example, a signal described as having a logic “high” level may alternatively have a logic “low” level, and a signal described as having a logic “low” level may alternatively have a logic “high” level. 
     In this way, the signal mixing circuit  20  in accordance with an embodiment generates the first to fourth strobe signals DQS&lt; 1 : 4 &gt; by mixing the first to fourth divided clocks DCLK&lt; 1 : 4 &gt; and the first and second preamble signals PRE&lt; 1 : 2 &gt;. The signal mixing circuit  20  generates the third and fourth strobe signals DQS&lt; 3 : 4 &gt; which toggle in synchronization with the first preamble signal PRE&lt; 1 &gt; and the second preamble signal PRE&lt; 2 &gt; during the preamble period. The signal mixing circuit  20  generates the first to fourth strobe signals DQS&lt; 1 : 4 &gt; which toggle in synchronization with the first to fourth divided clocks DCLK&lt; 1 : 4 &gt; after the preamble period. 
     Referring to  FIG. 4 , the first signal transfer circuit  31  in accordance with an embodiment may include a buffer circuit  310 , a first repeater  320 , and a second repeater  330 . 
     The buffer circuit  310  may generate the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; by buffering the first to fourth strobe signals DQS&lt; 1 : 4 &gt;. The internal configuration of the buffer circuit  310  will be described later with reference to  FIG. 5 . The buffer circuit  310  may adjust the pulse width of the last pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; in response to a masking signal MS. The masking signal MS is a signal which is inputted from an exterior to adjust the pulse width of the last pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; depending on the burst length of data DQ. An operation of adjusting the pulse width of the last pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; will be described later with reference to  FIGS. 5 and 6 . 
     The first repeater  320  may amplify and output the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt;. The first repeater  320  may be realized by an inverter and a driver which are generally known in the art, and may amplify and output the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt;. 
     The second repeater  330  may amplify and output the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; outputted from the first repeater  320 . The second repeater  330  may amplify the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; and transmit them to the first pad  41 . The second repeater  330  may be realized by an inverter and a driver which are generally known in the art, and may amplify and output the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt;. 
     The first signal transfer circuit  31  in accordance with an embodiment, configured as mentioned above, may generate the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; by amplifying the first to fourth strobe signals DQS&lt; 1 : 4 &gt; through the first repeater  320  and the second repeater  330 . The first signal transfer circuit  31  may output the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; to the first pad  41 . 
     The second signal transfer circuit  32  illustrated in  FIG. 1  may be realized to include repeaters the same as the first repeater  320  and the second repeater  330  illustrated in  FIG. 4 , and may generate the fifth to eighth transfer strobe signals TDQS&lt; 5 : 8 &gt; by amplifying the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt;. The second signal transfer circuit  32  may transmit the amplified fifth to eighth transfer strobe signals TDQS&lt; 5 : 8 &gt; to the third pad  51 . 
     Referring to  FIG. 5 , the buffer circuit  310  in accordance with an embodiment may include a first logic circuit  311 , a second logic circuit  312 , a third logic circuit  313 , and a fourth logic circuit  314 . 
     The first logic circuit  311  may be realized by a NOR gate NR 31  and an inverter IV 31 , and may generate the first transfer strobe signal TDQS&lt; 1 &gt; by buffering the first strobe signal DQS&lt; 1 &gt; in response to a ground voltage VSS. The first logic circuit  311  may generate the first transfer strobe signal TDQS&lt; 1 &gt; by performing an OR logic function on the ground voltage VSS and the first strobe signal DQS&lt; 1 &gt;. 
     The second logic circuit  312  may be realized by a NOR gate NR 32  and an inverter IV 32 , and may generate the second transfer strobe signal TDQS&lt; 2 &gt; by buffering the second strobe signal DQS&lt; 2 &gt; in response to the ground voltage VSS. The second logic circuit  312  may generate the second transfer strobe signal TDQS&lt; 2 &gt; by performing an OR logic function on the ground voltage VSS and the second strobe signal DQS&lt; 2 &gt;. 
     The third logic circuit  313  may be realized by a NOR gate NR 33  and an inverter IV 33 , and may generate the third transfer strobe signal TDQS&lt; 3 &gt; by buffering the third strobe signal DQS&lt; 3 &gt; in response to the ground voltage VSS. The third logic circuit  313  may generate the third transfer strobe signal TDQS&lt; 3 &gt; by performing an OR logic function on the ground voltage VSS and the third strobe signal DQS&lt; 3 &gt;. 
     The fourth logic circuit  314  may be realized by a NOR gate NR 34  and an inverter IV 34 , and may generate the fourth transfer strobe signal TDQS&lt; 4 &gt; by buffering the fourth strobe signal DQS&lt; 4 &gt; in response to the masking signal MS. The fourth logic circuit  314  may generate the fourth transfer strobe signal TDQS&lt; 4 &gt; by performing an OR logic function on the masking signal MS and the fourth strobe signal DQS&lt; 4 &gt;. The fourth logic circuit  314  generates the fourth transfer strobe signal TDQS&lt; 4 &gt; of a logic high level at a time when the masking signal MS is inputted. 
     The buffer circuit  310  in accordance with an embodiment, configured as mentioned above, may generate the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; by buffering the first to fourth strobe signals DQS&lt; 1 : 4 &gt;. The buffer circuit  310  may adjust the pulse width of the last pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; in response to the masking signal MS. 
     The operation of the buffer circuit  310  in accordance with an embodiment will be described below with reference to  FIG. 6  by being divided into an operation during the preamble period and an operation after the preamble period. 
     Before making descriptions, a preamble period P is set to a period between times T 21  and T 23  as the ½ cycle of the external clock CLK. According to an embodiment, the preamble period P may be set to one or more cycles of the external clock CLK. Also, times T 21  to T 32  illustrated in  FIG. 6  may be set as times the same as times T 1  to T 12  illustrated in  FIG. 3 . 
     The first logic circuit  311  generates the first transfer strobe signal TDQS&lt; 1 &gt; of a logic high level by buffering the first strobe signal DQS&lt; 1 &gt; in response to the ground voltage VSS between times T 21  and T 23  as the preamble period P. The first logic circuit  311  generates the first pulse of the first transfer strobe signal TDQS&lt; 1 &gt; between times T 23  and T 25  by buffering the first strobe signal DQS&lt; 1 &gt; in response to the ground voltage VSS between times T 23  and T 25  after the preamble period P. The first logic circuit  311  generates the second pulse of the first transfer strobe signal TDQS&lt; 1 &gt; between times T 27  and T 29  by buffering the first strobe signal DQS&lt; 1 &gt; in response to the ground voltage VSS between times T 27  and T 29  after the preamble period P. 
     The second logic circuit  312  generates the second transfer strobe signal TDQS&lt; 2 &gt; of a logic high level by buffering the second strobe signal DQS&lt; 2 &gt; in response to the ground voltage VSS between times T 21  and T 23  as the preamble period P. The second logic circuit  312  generates the first pulse of the second transfer strobe signal TDQS&lt; 2 &gt; between times T 24  and T 26  by buffering the second strobe signal DQS&lt; 2 &gt; in response to the ground voltage VSS between times T 24  and T 26  after the preamble period P. The second logic circuit  312  generates the second pulse of the second transfer strobe signal TDQS&lt; 2 &gt; between times T 28  and T 30  by buffering the second strobe signal DQS&lt; 2 &gt; in response to the ground voltage VSS between times T 28  and T 30  after the preamble period P. 
     The third logic circuit  313  generates the first pulse of the third transfer strobe signal TDQS&lt; 3 &gt; between times T 21  and T 23  by buffering the third strobe signal DQS&lt; 3 &gt; in response to the ground voltage VSS between times T 21  and T 23  as the preamble period P. The third logic circuit  313  generates the second pulse of the third transfer strobe signal TDQS&lt; 3 &gt; between times T 25  and T 27  by buffering the third strobe signal DQS&lt; 3 &gt; in response to the ground voltage VSS between times T 25  and T 27  after the preamble period P. The third logic circuit  313  generates the third pulse of the third transfer strobe signal TDQS&lt; 3 &gt; between times T 29  and T 31  by buffering the third strobe signal DQS&lt; 3 &gt; in response to the ground voltage VSS between times T 29  and T 31  after the preamble period P. 
     The fourth logic circuit  314  generates the first pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; between times T 22  and T 24  by buffering the fourth strobe signal DQS&lt; 4 &gt; in response to the masking signal MS between times T 21  and T 23  as the preamble period P. The fourth logic circuit  314  generates the second pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; between times T 26  and T 28  by buffering the fourth strobe signal DQS&lt; 4 &gt; in response to the masking signal MS between times T 26  and T 28  after the preamble period P. The fourth logic circuit  314  generates the third pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; between times T 30  and T 31  by buffering the fourth strobe signal DQS&lt; 4 &gt; in response to the masking signal MS between times T 30  and T 31  after the preamble period P. The masking signal MS is inputted at time T 31 , and adjusts the pulse width of the last pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt;. 
     The pulses included in the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; mean the periods in which the pulses are generated at, for example but not limited to, a logic low level. 
     Referring to  FIG. 7 , the first internal strobe signal generation circuit  43  in accordance with an embodiment may include a fifth logic circuit  410 , a sixth logic circuit  420 , a seventh logic circuit  430 , an eighth logic circuit  440 , and a pulse sensing circuit  450 . 
     The fifth logic circuit  410  may be realized by an inverter IV 41  and NAND gates ND 41  and ND 42 , and may generate a first pre-internal strobe signal PIDQS&lt; 1 &gt; by buffering the second transfer strobe signal TDQS&lt; 2 &gt; during a period in which the pulse of the first transfer strobe signal TDQS&lt; 1 &gt; is generated. The fifth logic circuit  410  may generate the first pre-internal strobe signal PIDQS&lt; 1 &gt; of a logic low level during a period in which the pulse of the first transfer strobe signal TDQS&lt; 1 &gt; is not generated. 
     The sixth logic circuit  420  may be realized by an inverter IV 42  and NAND gates ND 43  and ND 44 , and may generate a second pre-internal strobe signal PIDQS&lt; 2 &gt; by buffering the third transfer strobe signal TDQS&lt; 3 &gt; during a period in which the pulse of the second transfer strobe signal TDQS&lt; 2 &gt; is generated. The sixth logic circuit  420  may generate the second pre-internal strobe signal PIDQS&lt; 2 &gt; of a logic low level during a period in which the pulse of the second transfer strobe signal TDQS&lt; 2 &gt; is not generated. 
     The seventh logic circuit  430  may be realized by an inverter IV 43  and NAND gates ND 45  and ND 46 , and may generate a third pre-internal strobe signal PIDQS&lt; 3 &gt; by buffering the fourth transfer strobe signal TDQS&lt; 4 &gt; during a period in which the pulse of the third transfer strobe signal TDQS&lt; 3 &gt; is generated. The seventh logic circuit  430  may generate the third pre-internal strobe signal PIDQS&lt; 3 &gt; of a logic low level during a period in which the pulse of the third transfer strobe signal TDQS&lt; 3 &gt; is not generated. 
     The eighth logic circuit  440  may be realized by an inverter IV 44  and NAND gates ND 47  and ND 48 , and may generate a fourth pre-internal strobe signal PIDQS&lt; 4 &gt; by buffering the first transfer strobe signal TDQS&lt; 1 &gt; during a period in which the pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; is generated. The eighth logic circuit  440  may generate the fourth pre-internal strobe signal PIDQS&lt; 4 &gt; of a logic low level during a period in which the pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; is not generated. 
     The pulse sensing circuit  450  may generate the first internal strobe signal IDQS&lt; 1 &gt; which transitions in its level at a time when any one among the pulses included in the first to fourth pre-internal strobe signals PIDQS&lt; 1 : 4 &gt; is inputted. 
     The first internal strobe signal generation circuit  43  in accordance with an embodiment, configured as mentioned above, may generate the first internal strobe signal IDQS&lt; 1 &gt; by mixing the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; received from the first pad  41 . 
     The second internal strobe signal generation circuit  53  illustrated in  FIG. 1  may be realized by a circuit the same as or substantially the same as the first internal strobe signal generation circuit  43  illustrated in  FIG. 7  except that signals inputted thereto and outputted therefrom are different. 
     The operation of the first internal strobe signal generation circuit  43  in accordance with the embodiment will be described below with reference to  FIG. 8  by being divided into an operation during the preamble period and an operation after the preamble period. 
     Before making descriptions, a preamble period P is set to a period between times T 41  and T 43  as the ½ cycle of the external clock CLK. According to an embodiment, the preamble period P may be set to one or more cycles of the external clock CLK. Also, times T 41  to T 52  illustrated in  FIG. 8  may be set, for example but not limited to, as times the same as times T 1  to T 12  illustrated in  FIG. 3  and times T 21  to T 32  illustrated in  FIG. 6 . 
     The fifth logic circuit  410  generates the first pre-internal strobe signal PIDQS&lt; 1 &gt; of the logic low level during the period in which the pulse of the first transfer strobe signal TDQS&lt; 1 &gt; is not generated, between times T 41  and T 43  as the preamble period P. The fifth logic circuit  410  generates the first pulse of the first pre-internal strobe signal PIDQS&lt; 1 &gt; between times T 43  and T 44  by buffering the second transfer strobe signal TDQS&lt; 2 &gt; during the period in which the pulse of the first transfer strobe signal TDQS&lt; 1 &gt; is generated, between times T 43  and T 45  after the preamble period P. The fifth logic circuit  410  generates the second pulse of the first pre-internal strobe signal PIDQS&lt; 1 &gt; between times T 47  and T 48  by buffering the second transfer strobe signal TDQS&lt; 2 &gt; during the period in which the pulse of the first transfer strobe signal TDQS&lt; 1 &gt; is generated, between times T 47  and T 49  after the preamble period P. 
     The sixth logic circuit  420  generates the second pre-internal strobe signal PIDQS&lt; 1 &gt; of the logic low level during the period in which the pulse of the second transfer strobe signal TDQS&lt; 2 &gt; is not generated, between times T 41  and T 43  as the preamble period P. The sixth logic circuit  420  generates the first pulse of the second pre-internal strobe signal PIDQS&lt; 2 &gt; between times T 44  and T 45  by buffering the third transfer strobe signal TDQS&lt; 3 &gt; during the period in which the pulse of the second transfer strobe signal TDQS&lt; 2 &gt; is generated, between times T 44  and T 46  after the preamble period P. The sixth logic circuit  420  generates the second pulse of the second pre-internal strobe signal PIDQS&lt; 2 &gt; between times T 48  and T 49  by buffering the third transfer strobe signal TDQS&lt; 3 &gt; during the period in which the pulse of the second transfer strobe signal TDQS&lt; 2 &gt; is generated, between times T 48  and T 50  after the preamble period P. 
     The seventh logic circuit  430  generates the first pulse of the third pre-internal strobe signal PIDQS&lt; 3 &gt; between times T 41  and T 42  by buffering the fourth transfer strobe signal TDQS&lt; 4 &gt; during the period in which the pulse of the third transfer strobe signal TDQS&lt; 3 &gt; is generated, between times T 41  and T 43  as the preamble period P. The seventh logic circuit  430  generates the second pulse of the third pre-internal strobe signal PIDQS&lt; 3 &gt; between times T 45  and T 46  by buffering the fourth transfer strobe signal TDQS&lt; 4 &gt; during the period in which the pulse of the third transfer strobe signal TDQS&lt; 3 &gt; is generated, between times T 45  and T 47  after the preamble period P. The seventh logic circuit  430  generates the third pulse of the third pre-internal strobe signal PIDQS&lt; 3 &gt; between times T 49  and T 50  by buffering the fourth transfer strobe signal TDQS&lt; 4 &gt; during the period in which the pulse of the third transfer strobe signal TDQS&lt; 3 &gt; is generated, between times T 49  and T 51  after the preamble period P. 
     The eighth logic circuit  440  generates the first pulse of the fourth pre-internal strobe signal PIDQS&lt; 4 &gt; between times T 42  and T 43  by buffering the first transfer strobe signal TDQS&lt; 1 &gt; during the period in which the pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; is generated, between times T 41  and T 43  as the preamble period P. The eighth logic circuit  440  generates the second pulse of the fourth pre-internal strobe signal PIDQS&lt; 4 &gt; between times T 46  and T 47  by buffering the first transfer strobe signal TDQS&lt; 1 &gt; during the period in which the pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; is generated, between times T 46  and T 48  after the preamble period P. The eighth logic circuit  440  generates the fourth pre-internal strobe signal PIDQS&lt; 4 &gt; of a logic high level between times T 50  and T 51  by buffering the first transfer strobe signal TDQS&lt; 1 &gt; during the period in which the pulse of the fourth transfer strobe signal TDQS&lt; 4 &gt; is generated, between times T 50  and T 51  after the preamble period P. 
     The pulses included in the first to fourth pre-internal transfer strobe signals PIDQS&lt; 1 : 4 &gt; mean periods in which the pulses are generated at, for example but not limited to, a logic high level. 
     The pulse sensing circuit  450  generates the first internal strobe signal IDQS&lt; 1 &gt; which transitions in its level in response to the pulses of the third and fourth pre-internal strobe signals PIDQS&lt; 3 : 4 &gt;, between times T 41  and T 43  as the preamble period P. The pulse sensing circuit  450  generates the first internal strobe signal IDQS&lt; 1 &gt; which transitions in its level in response to the pulses of the first to fourth pre-internal strobe signals PIDQS&lt; 1 : 4 &gt;, between times T 43  and T 50  after the preamble period P. 
     The operation of the semiconductor device in accordance with an embodiment will be described with reference to  FIGS. 1 to 8  by providing, for example, a read operation for the first bank  40 . 
     The control circuit  10  generates the first preamble signal PRE&lt; 1 &gt; and the second preamble signal PRE&lt; 2 &gt; which include pulses generated during the preamble period, in response to the read command RD. The control circuit  10  generates the first to fourth divided clocks DCLK&lt; 1 : 4 &gt; by dividing the frequency of the external clock CLK in response to the read command RD. 
     The signal mixing circuit  20  generates the third and fourth strobe signals DQS&lt; 3 : 4 &gt; which toggle in synchronization with the first preamble signal PRE&lt; 1 &gt; and the second preamble signal PRE&lt; 2 &gt; during the preamble period. The signal mixing circuit  20  generates the first to fourth strobe signals DQS&lt; 1 : 4 &gt; which toggle in synchronization with the first to fourth divided clocks DCLK&lt; 1 : 4 &gt; after the preamble period. 
     The buffer circuit  310  of the first signal transfer circuit  31  generates the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; by buffering the first to fourth strobe signals DQS&lt; 1 : 4 &gt;. The first repeater  320  amplifies and outputs the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt;. The second repeater  330  amplifies the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; outputted from the first repeater  320 , and transmits the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; to the first pad  41 . 
     The first internal strobe signal generation circuit  43  generates the first internal strobe signal IDQS&lt; 1 &gt; which toggles, by mixing the first to fourth transfer strobe signals TDQS&lt; 1 : 4 &gt; transmitted to the first pad  41  during the preamble period and after the preamble period. 
     The first memory region  44  outputs the first internal data ID&lt; 1 &gt; stored therein. 
     The first input/output circuit  45  outputs the first internal data ID&lt; 1 &gt; through the second pad  42  in synchronization with the rising edge and falling edge of the first internal strobe signal IDQS&lt; 1 &gt;. 
     As is apparent from the above descriptions, in a semiconductor device according to an embodiment, a strobe signal is generated by mixing a divided clock and a preamble signal during a preamble period, and the strobe signal is outputted through a plurality of repeaters to a pad. As a consequence, it may be possible to prevent a mismatch of the divided clock and the preamble signal due to a long transfer path. 
     The semiconductor devices described above with reference to  FIGS. 1 to 8  may be applied to an electronic system which includes a memory system, a graphic system, a computing system or a mobile system. For example, referring to  FIG. 9 , an electronic system  1000  in accordance with an embodiment may include a data storage  1001 , a memory controller  1002 , a buffer memory  1003 , and an input/output interface  1004 . 
     The data storage  1001  stores data applied from the memory controller  1002 , and reads out stored data and outputs the read-out data to the memory controller  1002 , according to control signals from the memory controller  1002 . The data storage  1001  may include the semiconductor devices illustrated in  FIG. 1 . The data storage  1001  may include a nonvolatile memory capable of not losing and continuously storing data even though power supply is interrupted. A nonvolatile memory may be realized as a flash memory such as a NOR flash memory and a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM) or a magnetic random access memory (MRAM). 
     The memory controller  1002  decodes commands applied through the input/output interface  1004  from an external device (a host), and controls input/output of data with respect to the data storage  1001  and the buffer memory  1003  according to decoding results. While the memory controller  1002  is illustrated as one block in  FIG. 9 , it is to be noted that, in the memory controller  1002 , a controller for controlling a nonvolatile memory and a controller for controlling the buffer memory  1003  as a volatile memory may be independently configured. 
     The buffer memory  1003  may temporarily store data to be processed in the memory controller  1002 , that is, data to be inputted and outputted to and from the data storage  1001 . The buffer memory  1003  may store data applied from the memory controller  1002  according to a control signal. The buffer memory  1003  reads out stored data and outputs the read-out data to the memory controller  1002 . The buffer memory  1003  may include a volatile memory such as a DRAM (dynamic random access memory), a mobile DRAM and an SRAM (static random access memory). 
     The input/output interface  1004  provides a physical coupling between the memory controller  1002  and the external device (the host) such that the memory controller  1002  may receive control signals for input/output of data from the external device and exchange data with the external device. The input/output interface  1004  may include one among various interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI and IDE. 
     The electronic system  1000  may be used as an auxiliary memory device or an external storage device of the host. The electronic system  1000  may include a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini-secure digital (mSD) card, a micro SD card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), or a compact flash (CF) card. 
     While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor device described herein should not be limited based on the described embodiments.