Patent Publication Number: US-11664319-B2

Title: Light engine based on silicon photonics TSV interposer

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of and claims priority to U.S. application Ser. No. 16/738,844, filed Jan. 9, 2020 which is a continuation application of and claims priority to U.S. application Ser. No. 15/887,758, filed Feb. 2, 2018, now U.S. Pat. No. 10,566,287, issued Feb. 18, 2020, commonly assigned and incorporated by reference herein for all purposes. 
    
    
     BACKGROUND OF THE INVENTION 
     The present disclosure is related to manufacture technique for integrated silicon photonics device, and particularly to a light engine based on a silicon photonics through-silicon via interposer and a method of making the same. 
     As science and technology are updated rapidly, processing speed and capacity of the computer increase correspondingly. The need for optical interconnect for high-performance computing and data center applications are indispensable with increasing demand. An optical communication system includes both electrical devices and optical devices, devices for converting electrical signal and optical signal back and forth, and devices for processing these signals. With the advances of optical communication technology and applications driven by the market demand on increasing bandwidth and decreasing package footprint, more intensive effort and progress have been seen in the development of electro-photonic integrated circuits on silicon-on-insulator (SOI) substrate for forming those communication devices including pluggable photonics modules. 
     With the increase data density of large data center switches, the pluggable optical module solution has seen bottle neck due to the electrical link performance between switch cores and optical transceivers. The technology trend to move the optical transceiver functions closer to switch core is becoming clear. With the linecard approaching to data-rate of 56 Gbaud or above, package solutions based on wire bonds no longer fulfill the system bandwidth requirement. It is desirable to have a compact optical engine that is provided as on-board module or co-integrated with switches in high data rate communication applications. 
     BRIEF SUMMARY OF THE INVENTION 
     The present disclosure is related to manufacture technique for integrated silicon photonics device. More particularly, the invention provides a light engine based on a silicon photonics through-silicon via interposer and a method of making the same. In certain embodiments, the invention is applied for high data rate optical communication, though other applications are possible. 
     In modern electrical interconnect systems, high-speed serial links have replaced parallel data buses, and serial link speed is rapidly increasing due to the evolution of CMOS technology. Internet bandwidth doubles almost every two years following Moore&#39;s Law. But Moore&#39;s Law is coming to an end in the next decade. Standard CMOS silicon transistors will stop scaling around 5 nm. And the internet bandwidth increasing due to process scaling will plateau. But Internet and mobile applications continuously demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files. This disclosure describes techniques and methods to improve the communication bandwidth beyond Moore&#39;s law. 
     In a specific embodiment, the present invention provides a method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes providing a silicon substrate including a front side and a back side and forming a plurality of vias into the silicon substrate in the front side. The method further includes filling a conductive material in the plurality of vias including a conductive pattern routed on the front side. Furthermore, the method includes defining primary structures associated with optical features in the front side and masking the front side including the conductive material in the plurality of vias and the primary structures associated with optical features. Additionally, the method includes bonding a first handle wafer to the front side of the silicon substrate and thinning down the silicon substrate from the back side and forming a plurality of conductive bumps to respectively couple with the conductive material in the plurality of vias at the back side. The method further includes bonding a second handle wafer to the back side including the plurality of conductive bumps and debonding the first handle wafer from the front side. Furthermore, the method includes forming secondary structures based on the primary structures associated with optical features and forming a plurality of conductive pads at the front side coupled respectively with the conductive material in the plurality of vias. The method further includes completing final structures based on the secondary structures in the front side. Moreover, the method includes debonding the second handle wafer from the back side. 
     In an alternative embodiment, the present invention provides a method of making an optical-electrical module based on silicon photonics TSV interposer. The method includes forming a silicon photonics TSV interposer using the method described herein. Then, the method further includes attaching a laser device to couple at least an electrode with a solder pad in a trench structure of the final structures in the front side of the silicon photonics TSV interposer. Additionally, the method includes fixing a fiber into a V-groove of the final structures with a lid. The fiber is coupled with the laser device. Furthermore, the method includes disposing a transimpedance amplifier (TIA) module chip that is flipped in orientation to have multiple electrodes of the TIA module chip coupled with some of the plurality of conductive pads. Moreover, the method includes disposing a driver chip that is flipped in orientation to have multiple electrodes of the driver chip coupled with some of the plurality of conductive pads. 
     In yet another alternative embodiment, the present disclosure provides an optical-electrical module based on silicon photonics TSV interposer. The optical-electrical module includes a silicon substrate including a front side and a back side and a plurality of through-silicon vias (TSVs) formed in a first region of the silicon substrate. Each TSV is configured to fill a conductor material ended with a pad at the front side and a bump at the back side. The optical-electrical module further includes a coupler suspended over a cavity in the front side. The cavity is formed in a second region isolated from the first region after the plurality of TSVs is formed. Additionally, the optical-electrical module includes a laser device disposed in a trench in the second region of the front side and a fiber installed in a V-groove in the second region of the front side. The fiber is configured to couple with the coupler and the laser device. Furthermore, the optical-electrical module includes one or more electrical IC chips having electrodes coupled directly with some pads at the front side that electrically connected to some bumps at the back side through the conductive material in the plurality of TSVs. 
     In still another alternative embodiment, the present disclosure provides a light engine including a switch module and the optical-electrical module described herein that is co-integrated on a printed circuit board coupled with an Ultra Short Reach (USR) or Extra Short Reach (XSR) electrical interface and connected to an optical connector via a fiber. 
     Many benefits are provided with the improvement according to the present invention. In certain embodiments, the present invention provides a replacement of wire bonds by “bump-TSV-trace-bump” or “bump-trace-TSV-trace-bump” in a chip scale package (CSP) with better RF performance. In some embodiments, the chip-scale-package using (through-silicon via) TSV silicon photonics interposer consumes less PCB space. In some other embodiments, with the TSV process, multilayer capacitors (MLCs) can be fabricated simultaneously to eliminate the use of stand-alone DC blocking capacitors and by-pass capacitors on PCB. The present invention achieves these benefits and others in the context of broadband communication technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following diagrams are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many other variations, modifications, and alternatives. It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this process and scope of the appended claims. 
         FIGS.  1  through  23    are schematic diagrams illustrating a method of fabricating a silicon photonics interposer having through-silicon vias (TSVs) according to an embodiment of the present invention. 
         FIG.  24    is a schematic sectional view of an optical-electrical module based on the silicon photonics TSV interposer according to an embodiment of the present invention. 
         FIG.  25    is a schematic sectional view of a light engine with a switch and co-integrated the optical-electrical module based on the silicon photonics TSV interposer according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present disclosure is related to manufacture technique for integrated silicon photonics device. More particularly, the invention provides a light engine based on a silicon photonics through-silicon via interposer and a method of making the same. In certain embodiments, the invention is applied for high data rate optical communication, though other applications are possible. 
     The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. 
     In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. 
     The reader&#39;s attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. 
     Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6. 
     Please note, if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise and counter clockwise have been used for convenience purposes only and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative locations and/or directions between various portions of an object. 
     Through-Silicon Via (TSV) wafer process has been introduced for making many electrical IC devices. After TSV is formed, the biggest challenging part is to reveal TSV from wafer backside and perform backside routing/bumping. A wafer for forming silicon photonics modules has to fabricate many optical packaging features including suspended coupler, and V-groove, and laser trench. The suspended coupler has a very fragile structure. The V-groove and laser trench both need deep topography processes. These optical packaging features introduce increased process complexity and challenge to achieve a robust backside processing on a bonded silicon photonics wafer. The present disclosure provides a novel method of fabricating a silicon photonics TSV interposer that overcomes the challenge associated with the fragile V-groove and suspended coupler. 
       FIGS.  1  through  23    are schematic diagrams illustrating a method of fabricating a silicon photonics interposer having through-silicon vias (TSVs) according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. Note that each figure shows a snapshot of one or more processes performed to fabricate a silicon photonics TSV interposer according to one or more embodiments of the disclosed method. Some processes may be performed in different orders. Some processes may be replaced by other processes to achieve substantially similar results. Some processes can be executed using different techniques without being fully listed in the specification. Some processes may be omitted without affecting the claimed feature of the method. 
     Referring to  FIG.  1   , a silicon photonics wafer is provided for making a through-silicon via (TSV) interposer. In the example, the silicon photonics wafer is a silicon substrate  100  having a front side  101  and a back side  102 . Optionally, the silicon substrate  100  is covered by a layer of silicon dioxide  110 . Optionally, the silicon dioxide is schematically referred to an optical layer  110  formed on the front side  101  for forming one or more optical features or waveguides. Optionally, at least a patterned metallization layer (not shown) is also formed in the front side  101 . Optionally, the method of making a silicon photonics TSV interposer starts after the optical layers and all metallization layers are completed. This is called TSV-last process. 
     Referring to  FIG.  2   , in an embodiment, the method includes a TSV process for forming a plurality of vias  121  by etching from the optical layer  110  in the front side  101 . Optionally, the etching process includes Bosch etching, which is a deep reactive-ion etching with highly anisotropic nature to create deep penetration, steep-sided holes with near 90° vertical walls. Optionally, via  121  is characterized by a lateral dimension of about 30 μm and a depth of about 250 μm down to a bottom  122 . Optionally, the plurality of vias  121  is formed in a first region of the front side  101  of the silicon substrate  100 . Optionally, the first region includes one or more sub-regions and the plurality of vias  121  in each sub-region may be arranged with different distributions, spacing, and numbers depended on applications. 
     Referring to  FIG.  3   , the method also includes another step of the TSV process to perform a liner oxide deposition at a temperature &lt;400° C. to form an oxide layer  111  overlying the bottom  122  and side wall of each via  121  as well as any top portion of the front side  101  without the vias. Techniques like PECVD and SACVD are choices for performing the liner oxide deposition. 
       FIG.  4    shows one or more steps of the TSV process for filling a conductive material  130  inside the plurality of vias  121 . In the example, a sputtering process is firstly employed to form a barrier layer (not explicitly shown in  FIG.  4   ) overlying the oxide layer  111 . The barrier layer is typically made by material selected from Ti, TiN, Ta, and TaN. Secondly, a conductive material  130  is filled in the vias  121 . Usually, the conductive material  130  is Cu. The barrier layer is configured to prevent Cu in the vias  121  from diffusing into its surrounding part in the silicon substrate  100 . 
       FIG.  5    is a schematic diagram of showing additional steps of the TSV process for removing extra residues of the conductive material  130  from top of the oxide layer  111  on the front side  101  by performing a planarization process according to an embodiment of the present invention. Optionally, the steps include annealing process and performing a chemical-mechanical planarization process. As shown, the steps lead to substantially removal of extra conductive material on the front side surface but to reveal a front end  131  of the conductive material  130  associated with each via within a surface of oxide layer  111 . Optionally, the TSV process described above can be accompanied with a process for forming one or more multi-layer capacitors  900  near the front side  101  of the silicon substrate  100 . Optionally, the multi-layer capacitors  900  are formed in a third region separated from the first region used for forming the TSVs. It is also executed by several etching steps, oxidation steps, metal plating steps, and planarization steps. 
     Referring to  FIG.  6   , the method includes a post-TSV metal routing process for forming a conductive pattern routed to connect some of the front ends  131  of the conductive material  130  filled in the plurality of vias. Optionally, an extended metallization structure  133  is formed that electrically couples with the conductive material  130  in a via  121 . The method then includes a post-TSV passivation process for forming a first passivation layer  112  to cover entire front side of the silicon substrate  100 . Optionally, the first passivation layer  112  at least covers the first region having extended metallization structure  133  over each front end of the conductive material  130  associated with the vias  121 . Optionally, the first passivation layer  112  also covers a second region separated from the first region without TSVs. Optionally, the first passivation layer  112  additionally covers the third region with the multi-layer capacitors  900 . Optionally, the first passivation layer  112  is also an oxide layer made by substantially the same material as the oxide layer  111 . Optionally, the first passivation layer  112  is a silicon dioxide (SiO 2 ) layer. 
       FIG.  7    is a schematic diagram illustrating a step of defining primary structures associated with optical features in the front side according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown, the step is several etching processes executed in a second region separated from the first region for forming the plurality of vias that have been turned to TSVs with filled conductive material  130 . Optionally, in a first sub-region of the second region, a first structure  160  of the primary structures is formed by performing a first etch to form a shallow wide trench into the first passivation layer  112  and performing a second etch further through the first passivation layer  112  at two separate locations in the shallow wide trench  160  to form two deep narrow trenches  161  and  162  stopped at silicon material of the front side  101 . Optionally, in a second sub-region of the second region, a second structure  150  is formed and configured to form a V-groove. In this step, the second structure  150  is a trench etched into the first passivation layer  112  with a bottom at the silicon material of the front side  101 . Optionally, in a third sub-region of the second region, a trench structure  140  is formed and configured to mount a laser device. The trench structure  140  is formed by etching through the first passivation layer  112  and further into a depth of the silicon material of the front side  101 . Optionally, the primary structures associated with optical features include a combination of the first structure  160 , the second structure  150 , and the trench structure  140 . Optionally, other structures associated with optical features can be formed in the second region separated from the first region. Of course, there can be other alternatives, variations, and modifications. 
     Referring to  FIG.  8   , the method includes forming a mask layer  170  of hard silicon nitride (Si 3 N 4 ) overlying the primary structures ( 140 ,  150 , and  160 ) associated with optical features as well as the remaining part of the first passivation layer  112 . The mask layer  170  is configured to protect the structures formed up to this stage on the entire front side of the silicon substrate  100 . Optionally, the hard silicon nitride (Si 3 N 4 ) layer of at least 1000 Angstroms is formed. Optionally, the hard silicon nitride (Si 3 N 4 ) layer of up to 2000 Angstroms is formed. Other thicknesses of the mask layer  170  made by alternative materials may be applicable. 
       FIG.  9    shows a step of bonding a first handle wafer  200  to the front side of the silicon substrate  100  via a thick layer of temporary adhesive material  181 . The adhesive material  181  is placed over the mask layer  170  which provides full protection of the structures formed on the front side of the silicon substrate  100 . Optionally, the first handle wafer  200  can be a silicon carrier wafer. Optionally, the first handle wafer  200  is a glass carrier wafer. Now, as the first handle wafer  200  is firmly yet temporarily attached with the front side of the silicon substrate  100 , the back side  102  of the silicon substrate is available for any backside processes. 
       FIG.  10    shows a first step of the backside process to reduce thickness of the silicon substrate  100  from the back side  102 . In particular, the first step is thinning down the silicon substrate  100  to transform original back side  102  to a new back side  102 ′ to just leave a few microns to the bottom  122  of the via  121 . Optionally, the thinning process is stopped at the new back side  102 ′ that is 2 to 5 microns away from the bottom  122  of the via  121 . Referring to  FIG.  10    and  FIG.  3   , the bottom  122  is an interface between the oxide layer  111  and the silicon material. 
       FIG.  11    shows a second step of the backside process to further reduce thickness of the silicon substrate  100  from the back side  102 ′ to another new back side  102 ″. In particular, the second step is a Si dry etch process that is able to make the bottom  122  of the TSV  121  protruded out of the back side  102 ″ by a few microns. The Si dry etch is characterized by a high selectivity of Si material over SiO 2  material in terms of a ratio 10:1. As the new back side  102 ″ is moved to below (or above as seen in  FIG.  11   ) the bottom  122  of the via  121 , the oxide layer  111  at the bottom  122  is still substantially retained to cover the back end  132  of the conductive material  130  in the vias  121 . Optionally, the back side  102 ″ is set to be below (or above as seen in  FIG.  11   ) the back end  132  of the conductive material  130 . 
       FIG.  12    shows a third step of the backside process to form a second passivation layer  113  overlying the new back side  102 ″. Optionally, the second passivation layer  113  is formed using a low temperature (&lt;200° C.) deposition of SiO 2  material of 2 to 3 microns in thickness. The low temperature deposition is designed to make sure that the temporary adhesive material  181  can sustain the heat to maintain a strong bonding between the first handle wafer  200  and the front side of the silicon substrate  100 . 
       FIG.  13    shows a fourth step of the backside process to planarize the back side and reveal the back end of the conductive material in the TSV. In particular, a CMP process is executed to obtain a planarized surface  114  of the second passivation layer  113 , which covers the new back side  102 ″. The CMP process is performed until the back end  132  of the conductive material  130  in each via  121  is just revealed within the planarized surface  114 . Again, this step is possible with the first handle wafer  200  is employed to temporarily attach with hard masked front side of the silicon substrate  100  to allow the backside process to be executed properly at the back side of the silicon substrate  100 . 
       FIG.  14    shows a final step of the backside process, in which a backside routing of conductive pattern and solder bump formation are performed. As shown, on the planarized surface  114 , the conductive pattern is routed with an under-bump metallization structure  134  formed to couple with each back end  132  of the conductive material  130  in the vias  121 . On the under-bump metallization structure  134  a solder bump  136  is formed, which is configured to form direct electrical connection with a circuit board when the silicon substrate  100  is used as a silicon photonics TSV interposer. 
       FIG.  15    shows a step of bonding a second handle wafer to the back side after the backside process. In particular, a temporary adhesive material  182  is coated over entire back side including the conductive pattern routed on the planarized surface  114  and all the solder bumps  136  that are electrically coupled with the conductive material  130  in all TSVs in the silicon substrate  100 . The second handle wafer  300  then is attached to the adhesive material  182  to be bonded temporarily with the silicon substrate  100 . Optionally, the second handle wafer is a silicon carrier wafer. Optionally, the second handle wafer is a glass carrier wafer. At this time, the first handle wafer  200  remains to bond with front side of the silicon substrate  100  via the temporary adhesive material  181 . 
     Referring to  FIG.  16   , the method includes a debonding process to remove the first handle wafer from the front side of the silicon substrate. As shown, the first handle wafer is removed while the temporary adhesive material coated on the front side is cleaned. The mask layer  170  now is revealed again at the front side, which still substantially covers the first passivation layer  112  as well as the primary structures associated with optical features. Now the second handle wafer  300  remains to be bonded with the back side of the silicon substrate  100 , allowing the front side being ready for further front side processes to form a silicon photonics TSV interposer. 
       FIG.  17    shows a step of the front side process to form secondary structures based on the primary structures associated with optical features. Referring to  FIG.  17   , a patterning and etching process is performed to specifically open up a window of the mask layer  170  the second structure  150 . The mask layer  170  is hard silicon nitride (Si 3 N 4 ). No silicon or silicon oxide etching is occurred at the same time. Afterward, a chemical bath process is performed to further etch down the silicon material from the bottom of the second structure  150  to form a V-groove  150 ′. Optionally, KOH chemical bath is a preferred process for forming the V-groove. Optionally, TMAH chemical bath is another preferred process for forming the V-groove. After V-groove is formed, the Si 3 N 4  hard mask  170  is removed via hot phosphorus acid. 
       FIG.  18    shows another step of the front side process to form secondary structures based on the primary structures associated with optical features. As shown, remaining portion of the mask layer  170  is fully removed in this step by hot phosphorus acid. Subsequently, an under-bump metallization (UBM) structure  141  is formed at the bottom of the trench structure  140  of the primary structures associated with optical features. Specifically, the UBM formation can be done by sputtering TiW and Au followed by a lift-off process. Optionally, the UBM formation can be done by electrochemical plating. Additionally, on top of the UBM structure  141 , a solder pad  142  is formed. In particular, the solder pad  142  is made by AuSn alloy material. Sputtering of AuSn alloy can be done and followed by a lift-off process to form the solder pad  142 . At this time, the trench structure  140  is updated to a new trench structure  140 ′. Overall, the two steps mentioned above lead to a formation of the secondary structures referred to the new trench structure  140 ′, the V-groove  150 ′, and the first structure  160 . Both steps are performed when the second handle wafer  300  is bonded to the back side of the silicon substrate  100  to allow the front side process to be done properly. 
       FIG.  19    shows another step of front side process with the support of the second handle wafer  300  bonded to the back side of the silicon substrate  100 . As shown, the first passivation layer  112  is patterned and etched to open up multiple windows  135  that each reveals a portion of an extended metallization structure  133  coupled to the conductive material  130  in TSVs. 
     Subsequently,  FIG.  20    shows that a step of placing a patterned photo-resist layer  190  over the secondary structures ( 140 ′,  150 ′, and  160 ) associated with optical features on the front side. A next step, as shown in  FIG.  21   , is to perform a metal plating process to form a plurality of conductive pads  137  respectively inside the multiple windows  135  opened up in the first passivation layer  112 . In particular, an electroless nickel electroless palladium immersion gold (ENEPIG) process is performed. Optionally, each conductive pad  137  is formed with its top part protruded above the first passivation layer  112 . With the protection of the patterned photo-resist layer  190 , the secondary structures associated with optical features on the front side will not subjected to any damage by the metal plating process. Referring to  FIG.  21   , a follow-up process is done to remove the patterned photo-resist layer  190  after the formation of the plurality of conductive pads  137  to complete the TSV process. In other words, the plurality of vias  121  formed in the silicon substrate  100  are transformed to a plurality of conductive TSVs with each TSV being an electrical conduction path from a conductive pad  137  at the front side through the conductive material  130  filled in the vias  121  to a solder bump  136  at the back side (which is still buried in the temporary adhesive material  182  bonded with the second handle wafer  300 ). 
       FIG.  22    shows a final step of the front side process for completing final structures associated with optical features. As the final structures associated with optical features involve some most fragile structures, the step for completing final structures associated with optical features is preferred to be done after all steps of the front side process finish. In other word, this step is performed lastly for forming the silicon photonics TSV interposer. In the example shown in  FIG.  22   , completing the final structures includes forming a suspended coupler in the first structure  160 . In particular, the forming a suspended coupler is to release Si material to form a cavity  163  inside the silicon substrate below a waveguide layer  164  (e.g., part of the silicon oxide material above the silicon material). The process includes a first isotropic Si etching through both the first deep narrow trench  161  and the second deep narrow trench  162  formed in the first structure  160  followed by a deep anisotropic Si etching to form the cavity  163 . The waveguide layer  164  suspended over the cavity  163  is configured to be an optical coupler for coupling light from fiber into Si photonics TSV interposer or coupling light from Si photonics TSV interposer out to optical fiber. 
       FIG.  23    shows a step of debonding the second handle wafer from the back side of the silicon substrate. As all steps of the front side process after the TSV formation are completed, the second handle wafer  300  is removed with all the temporary adhesive material  182  on the back side is cleaned. This again reveals the back side structure of the silicon substrate formed earlier, including all the solder bumps associated with the TSVs. In fact,  FIG.  23    shows that a silicon photonics TSV interposer  1000  is delivered with all TSVs being completed each with a full electrical conduction path from a conductive pad  137  at the front side through the conductive material  130  to a solder bump  136  at the back side as well as all final structures associated with optical features ready for plugging optical devices. 
     In another aspect, the present disclosure provides a method of making an optical-electrical module based on silicon photonics TSV interposer. The method includes forming a silicon photonics TSV interposer using the method described herein as illustrated in all figures from  FIG.  1    through  FIG.  23   . The method of making the optical-electrical module further includes attaching a laser device to couple at least an electrode with a solder pad in a trench structure of the final structures associated with optical features in a front side of the silicon photonics TSV interposer. Additionally, the method includes fixing a fiber into a V-groove of the final structures with a lid. The fiber is coupled at least with the laser device. Furthermore, the method includes disposing a transimpedance amplifier (TIA) module chip that is flipped in orientation to have multiple electrodes of the TIA module chip coupled with some of the plurality of conductive pads in the front side of the silicon photonics TSV interposer. Moreover, the method of making the optical-electrical module includes disposing a driver chip that is flipped in orientation to have multiple electrodes of the driver chip coupled with some of the plurality of conductive pads in the front side of the silicon photonics TSV interposer. 
     In yet another aspect, the present disclosure provides an optical-electrical module based on silicon photonics TSV interposer.  FIG.  24    is a schematic sectional view of an optical-electrical module based on the silicon photonics TSV interposer according to an embodiment of the present invention. As shown, the optical-electrical module  2000  includes a silicon substrate  100  including a front side and a back side and a plurality of through-silicon vias (TSVs)  130  formed in a first region of the silicon substrate  100 . Each TSV  130  is configured to fill a conductor material ended with a pad  137  at the front side and a bump  136  at the back side. The optical-electrical module  2000  further includes a coupler  164  suspended over a cavity  163  in the front side. The cavity  163  is formed in a second region isolated from the first region after the plurality of TSVs  130  including the pads  137  and the bumps  136  is formed. Additionally, the optical-electrical module  2000  includes a laser device  1030  disposed in a trench  140 ′ in the second region of the front side. Optionally, the laser device  1030  is a DFB laser having at least an electrode  1031  coupled directly with a solder pad  142  on an under-bump metallization structure  141  in the trench  140 ′. Furthermore, the optical-electrical module  2000  includes a fiber  1040  installed in a V-groove  150 ′ in the second region of the front side. The fiber  1040  is configured to couple with the coupler  164  and the laser device  1030 . Optionally, the fiber  1040  is fixed by a lid  1041 . Moreover, the optical-electrical module  2000  includes one or more electrical IC chips having electrodes coupled directly with some pads  137  at the front side of the silicon photonics TSV interposer that electrically connected to some bumps  136  at the back side through the conductive material in the plurality of TSVs  130 . Optionally, the one or more electrical IC chips include a transimpedance amplifier (TIA) module  1010 . Optionally, the TIA module is a flip chip having electrodes  1011  facing directly towards some conductive pads  137  on the front side of the silicon photonics TSV interposer to form direct electrical connection without any wirebonds. Optionally, the one or more electrical IC chips include a driver module  1020  configured as a flip chip with multiple electrodes  1021  facing directly towards some other conductive pads  130 ′ on the front side of the silicon photonics TSV interposer to form direct electrical connection without any wirebonds. Optionally, the optical-electrical module  2000  further includes multiple multi-layer capacitors formed in the front side of the silicon photonics TSV interposer. Optionally, the optical-electrical module  2000  can be applied as an on-board module coupled together with a gear box or retimer module. The on-board module is then mounted with a switch on a same PCB and connected to an optical connector via a fiber to connect to external optical network and very-short reach (VSR) electrical interface for communicating with electrical network for data center switch application. 
     In still another aspect, the present disclosure provides a light engine based on the silicon photonics TSV interposer.  FIG.  25    is a schematic sectional view of a light engine with a switch and co-integrated the optical-electrical module based on the silicon photonics TSV interposer according to an embodiment of the present invention. As shown, the light engine  3000  is provided with a switch  2050  co-integrated with the optical-electrical module  2000  based on the silicon photonics TSV interposer described herein. The light engine uses host FEC to draw control signals without using gear box and retimer module. The optical-electrical module  2000  is coupled to the optical connector via a fiber for connecting to external optical network and using Ultra-Short-Reach (USR) or Extra-Short-Reach (ESR) electrical interface to communicate with electrical network in data center switch application. 
     While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.