Patent Publication Number: US-10768646-B2

Title: Low dropout regulating device and operating method thereof

Description:
TECHNICAL FIELD 
     The present disclosure is directed to a low dropout (LDO) regulating device and an operating method thereof. 
     BACKGROUND 
     Low dropout (LDO) regulating devices have been widely used in various electronic products because of their advantages of low noise and low cost. The LDO regulating device can be used as a power supply circuit for providing a stable output voltage. For example, the LDO regulating device may provide DC power to a memory chip for operation. 
     However, an unstable, unpredictable output voltage may be generated during the transition between different operation states of the LDO regulating device, such that the load circuit fails to function properly. Therefore, there is a need to provide an improved LDO regulating device and an operating method thereof, to address the abovementioned issues. 
     SUMMARY 
     The present invention relates to a low dropout (LDO) regulating device and an operating method thereof, which is capable of accelerating the startup speed of the LDO regulating device, such that the time which the LDO regulating device is required to entering the normal operation can be shortened. 
     According to an embodiment of the present invention, a LDO regulating device is provided. The LDO regulating device includes a regulator and a pre-charger. The regulator is configured to adjust an output voltage provided to an output node in accordance with a voltage difference between a first reference voltage and a feedback voltage on a feedback node, wherein the feedback node is coupled to the output node, and the regulator includes a comparing circuit and an output transistor. The comparing circuit is configured to receive the first reference voltage and the feedback voltage, and generate a control voltage on a control node in accordance with the voltage difference between the first reference voltage and the feedback voltage. The output transistor includes a control terminal coupling to the control node a first terminal coupling to a supply voltage and a second terminal coupling to the output node, wherein the output transistor responds to the control voltage to generate the output voltage at the second terminal. The pre-charger is electrically connected to the regulator, the pre-charger being electrically connected to the feedback node for charge sharing. 
     According to another embodiment of the present invention, an operating method of a LDO regulating device is provided. The operating method includes steps of: configuring a regulator to adjust an output voltage provided to an output node in accordance with a voltage difference between a first reference voltage and a feedback voltage on a feedback node; configuring a pre-charger to electrically disconnect from the feedback node to accumulate charges in an OFF state of the regulator; and electrically connecting the pre-charger to the feedback node for charge sharing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  illustrates a circuit diagram of a LDO regulating device according to an embodiment of the present disclosure. 
         FIG. 1B  illustrates a circuit diagram of a LDO regulating device according to another embodiment of the present disclosure. 
         FIG. 2A  shows waveforms of signals related to the LDO regulating device. 
         FIG. 2B  shows another example of waveforms of signals related to the LDO regulating device. 
         FIG. 3A  illustrates a circuit diagram of a LDO regulating device according to another embodiment of the present disclosure. 
         FIG. 3B  illustrates a circuit diagram of a LDO regulating device according to another embodiment of the present disclosure. 
         FIG. 4A  illustrates a circuit diagram of a LDO regulating device according to yet another embodiment of the present disclosure. 
         FIG. 4B  illustrates a circuit diagram of a LDO regulating device according to yet another embodiment of the present disclosure. 
         FIG. 5A  shows an example of waveforms of signals related to the LDO regulating device. 
         FIG. 5B  shows another example of waveforms of signals related to the LDO regulating device. 
         FIG. 6  shows a flowchart of an operating method for a LDO regulating device according to an embodiment of the present invention. 
     
    
    
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
     DETAILED DESCRIPTION 
     A number of embodiments are disclosed below for elaborating the invention. However, the embodiments of the invention are for detailed descriptions only, not for limiting the scope of protection of the invention. Furthermore, secondary or unimportant elements are omitted in the accompanying diagrams of the embodiments for highlighting the technical features of the invention. 
       FIG. 1A  illustrates a circuit diagram of a LDO regulating device  10  according to an embodiment of the present disclosure. The LDO regulating device  10  can be used to provide a regulated output voltage Vout to an output node Nout, such as a NOR flash memory, a NAND flash memory, a dynamic random-access memory (DRAM), or a static random-access memory (SRAM). 
     The LDO regulating device  10  includes a regulator  102  and a pre-charger  104 , and optionally a maintain circuit  106  and a bias power supply  108 . 
     The regulator  102  is to adjust an output voltage Vout provided to an output node Nout in accordance with a voltage difference between a first reference voltage Vref 1  and a feedback voltage Vfb. 
     The regulator  102  includes a comparing circuit  1022 , an output transistor M 1  and a feedback circuit  1024 . In this embodiment, the output transistor M 1  is implemented as a P-type transistor, such as a PMOS. 
     The comparing circuit  1022  can be an operational amplifier (OPA) for example. The comparing circuit  1022  may receive the first reference voltage Vref 1  and the feedback voltage Vfb, and generate a control voltage Vc on a control node Nc in accordance with the voltage difference between the first reference voltage Vref 1  and the feedback voltage Vfb. 
     The output transistor M 1  can be turned on in response to the control voltage Vc, and provides the output voltage Vout to the output node Nout accordingly. As shown in  FIG. 1A , the output transistor M 1  includes a control terminal (e.g., gate terminal) coupling to the control node Nc, a first terminal (e.g., source/drain terminal) coupling to a supply voltage VDD and a second terminal (e.g., drain/source terminal) coupling to the output node Nout. When the output transistor M 1  is turned on, the supply voltage VDD is transferred to the output node Nout and taken as the output voltage Vout. 
     The feedback circuit  1024  couples between the output node Nout and the comparing circuit  1022 , configures to provide a voltage division path to form the feedback node Nfb, and to provide the feedback voltage Vfb on the feedback node Nfb to the comparing circuit  1022 . 
     As shown in  FIG. 1A , the feedback circuit  1024  including a first impedance component R 1  and a second impedance component R 2  forms a voltage division path for the output voltage Vout. The first impedance component R 1  is connected to the second impedance component R 2  in series, and the interconnection between them forms the feedback node Nfb. The first impedance component R 1  and the second impedance component R 2  can be implemented as registers or any other circuit components equivalent to registers. 
     During the period of time that the LDO regulating device  10  works, if the output voltage Vout varies, the feedback voltage Vfb also changes. In such situation, the comparing circuit  1022  may respond to the variation of the feedback voltage Vfb to adjust the control voltage Vc of the comparing circuit  1022 , so that the current outputted from the output transistor M 1  is changed by the adjusted control voltage Vc, thereby keeping the output voltage Vout at a certain level. 
     The regulator  102  can be turned on or turned off by a switching signal EN. When the switching signal EN is enabled, the regulator  102  is in the ON state, and when the switching signal EN is disabled, the regulator  102  is in the OFF state. As shown in  FIG. 1A , the comparing circuit  1022  can be turned on or turned off by the switching signal EN. 
     The regulator  102  may further include a control switch SWc. The control switch SWc couples between a setting voltage SET (e.g., supply voltage VDD) and the control node Nc, with a control terminal controlled by the switching signal EN. When the regulator  102  is in the ON state, the switching signal EN is enabled, and the control switch SWc is turned off, causing the setting voltage SET (which can be a supply voltage) to be electrically disconnected from the control node Nc. When the regulator  102  is in the OFF state, the switching signal EN is disabled, and the control switch SWc is turned on, causing the setting voltage SET to be passed to the control node Nc to turn off the output transistor M 1 . 
     In an embodiment, the regulator  102  further includes a feedback switch SWf controlled by the switching signal EN. The feedback switch SWf is disposed between the feedback circuit  1024  and the output node Nout. When the switching signal EN is enabled, the regulator  102  is in the ON state, the feedback switch SWf will be turned on to couple the output node Nout to the feedback circuit  1024 . Conversely, when the switching signal EN is disabled, i.e., the regulator  102  is in the OFF state, the feedback switch SWf will be turned off to electrically disconnect the output node Nout from the feedback circuit  1024 . 
     In an embodiment, the pre-charger  104  may per-charge the feedback voltage Vfb on the feedback node Nfb to a certain level. 
     The pre-charger  104  may electrically disconnect from the feedback node Nfb to accumulate charges when the regulator  102  is in the OFF state, and may temporarily electrically connect to the feedback node Nfb for charge sharing when the regulator  102  is in the ON state. 
     Generally, if without the pre-charger  104 , as the regulator  102  switches from the OFF state to the ON state, the feedback voltage Vfb on the feedback node Nfb often takes a certain period of time to reach a voltage level suitable for executing voltage regulation operations. However, such period of time may significantly affect the “startup speed” of the LDO regulating device  10 . To accelerate the startup speed of the LDO regulating device  10 , the pre-charger  104  may share the charges accumulated thereon with the feedback node Nfb as the regulator  102  enters the ON state, so as to rapidly raise the level of the feedback voltage Vfb. 
     In an embodiment, the pre-charger  104  includes a pre-charge power supply  1042 , a pre-charge capacitor Csas, a sampling switch SWa and a sharing switch SWb, which forms a charge sharing circuit configuration. The pre-charge power supply  1042  is to provide a second reference voltage Vref 2 . The sampling switch SWa couples between the pre-charge capacitor Csas and the pre-charge power supply  1042 , allowing the pre-charge power supply  1042  to charge the pre-charge capacitor Csas. The sharing switch SWb couples between the pre-charge capacitor Csas and the feedback node Nfb, allowing the pre-charge capacitor Csas to share charges with the feedback node Nfb. 
     For example, when the regulator  102  is in the OFF state, the sampling switch SWa is turned on to couple the pre-charge capacitor Csas to the pre-charge power supply  1042 , and the sharing switch SWb is turned off to electrically disconnect the pre-charge capacitor Csas from the feedback node Nfb. At this time, the pre-charge power supply  1042  charges the pre-charge capacitor Csas with the second reference voltage Vref 2 . 
     As the regulator  102  switches to the ON state, the sampling switch SWa may electrically disconnect the pre-charge capacitor Csas from the pre-charge power supply  1042  in a first period of time, and the sharing switch SWb may electrically connect the pre-charge capacitor Csas to the feedback node Nfb in a second period of time within the first period of time. In such situation, the accumulated charges on the pre-charge capacitor Csas will be shared to the parasitic capacitor on the feedback node Nfb, such that the feedback voltage Vfb rises rapidly. Because the capacitance of the parasitic capacitor on the feedback node Nfb is usually much smaller than that of the pre-charge capacitor Csas, a predetermined value of the feedback voltage Vfb after charge sharing can be determined by a properly designed pre-charge capacitor Csas, wherein the predetermined value is between a minimum voltage level of the feedback voltage Vfb and a stable state voltage level of the feedback voltage Vfb. 
     In an embodiment, the LDO regulating device  10  further includes a maintain circuit  106 . The maintain circuit  106  may power the output node Nout when the regulator  102  is in the OFF state. 
     For example, the maintain circuit  106  includes a standby power supply  1062  and a standby switch SWt. The standby power supply  1062  can be implemented by another LDO regulating device, and is to provide a third reference voltage Vref 3 . The standby switch SWt is disposed between the standby power supply  1062  and the output node Nout, and is controlled by an inversed switching signal ENB. The standby switch SWt may allow the standby power supply  1062  to power the output node Nout with the third reference voltage Vref 3  as the regulator  102  is in the OFF state. 
     For example, when the regulator  102  is in the ON state, the standby switch SWt is turned off to electrically disconnect the output power Nout from the standby power supply  1062 . Conversely, when the regulator  102  is in the OFF state, the standby switch SWt is turned on to couple the output power Nout to the standby power supply  1062 , such that the output power Nout can be powered by the standby power supply  1062 . 
     With the maintain circuit  106 , the output voltage Vout on the output node Nout can be kept at a certain level during the OFF state of the regulator  102 , so the startup time required for the LDO regulating device  10  can be further shortened. 
     In an embodiment, both the pre-charge power supply  1042  of the pre-charger  104  and the standby power supply  1062  of the maintain circuit  106  can be integrated together. In such situation, the second reference voltage Vref 2  is the same as the third reference voltage Vref 3 . 
     The LDO regulating device  10  may further include a bias power supply  108  coupled to the comparing circuit  1022 . The bias power supply  108  can be implemented by a current mirror circuit and/or registers for example. When the regulator  102  is in the ON state, the bias power supply  108  may provide a bias signal BST to the comparing circuit  1022  to increase the bias current of the comparing circuit  1022 , so as to accelerate the startup speed of the control node Nc. 
       FIG. 1B  illustrates a circuit diagram of a LDO regulating device  10 ′ according to another embodiment of the present disclosure. Compared to the LDO regulating device  10 , the LDO regulating device  10 ′ does not include the feedback circuit  1024 , so that one terminal of the output transistor M 1  is coupled directly to an input (e.g., negative (−) input terminal) of the comparing circuit  1022  through the feedback switch SWf (optionally). Understandably, the circuit configuration of the LDO regulating device  10 ′ which does not include the feedback circuit  1024 , is appropriate to be used in embodiments of the present invention. In such instance, the feedback node Nfb is defined at the junction where the output transistor M 1  is connected to the input of the comparing circuit  1022 . 
       FIG. 2A  shows waveforms of signals related to the LDO regulating device  10 . 
     During the period of time Toff, the switching signal EN is disabled (e.g., with low signal level) to turn off the regulator  102 , and the inversed switching signal ENB is enabled (e.g., with high signal level) to make the standby power supply  1062  power the output node Nout. Further, the sampling signal S 1  is enabled to turn on the sampling switch SWa, allowing the second reference voltage Vref 2  to charge the pre-charge capacitor Csas, and the sharing signal S 2  is disabled to turn off the sharing switch SWb, so as to electrically disconnect the pre-charge capacitor Csas from the feedback node Nfb. 
     During the period of time Ton, the switching signal EN is enabled to turn on the regulator  102 , and the inversed switching signal ENB is disabled to electrically disconnect the standby power supply  1062  from the output node Nout. Further, in the beginning of the time period Ton, the sampling signal S 1  is disabled to turn off the sampling switch SWa for a first period of time T 1 , such that the second reference voltage Vref 2  electrically disconnects from the pre-charge capacitor Csas. During a second period of time T 2  within the first period of time T 1 , the sharing switch SWb is turned on in response to the enabled sharing signal S 2 , such that the pre-charge capacitor Csas electrically connects the feedback node Nfb for charge sharing. 
     In an embodiment, to ensure that there is no extra charges (e.g., charges from the pre-charge power supply  1042 ) flow into the feedback node Nfb during the charge sharing and to make the feedback voltage Vfb predictable, the second period of time T 2  is shorter than the first period of time T 1 , i.e., the raising edge of the sharing signal S 2  lags the falling edge of the sampling signal S 1 , and the falling edge of the sharing signal S 2  leads the raising edge of the sampling signal S 1 , as shown in  FIG. 2A . 
     After the charge sharing is finished, the sampling switch SWa and the sharing switch SWb will turn back to be turned-on and turned-off, respectively, until the next time that the LDO regulating device  10  switches from the OFF state to the ON state again. As shown in  FIG. 2A , for each time the regulator  102  switches from the OFF state to the ON state, the pre-charger  104  may share its charges with the feedback node Nfb for only one time, to properly setup the feedback voltage Vfb in the initial stage of the ON state of the regulator  102 . 
     In the example of  FIG. 2A , the bias signal BST is an inversed version of the sampling signal S 1 . That is, the bias power supply  108  may increase the bias current of the comparing circuit  1022  during the first period of time T 1 , to further accelerate the startup speed of the control node Nc. 
       FIG. 2B  shows waveforms of signals related to the LDO regulating device  10 . Compared to the embodiment shown in  FIG. 2A , in this embodiment the pre-charger  104  is electrically connected to the feedback node Nfb to pre-charge the feedback node Nfb before the regulator  102  enters in the ON state (i.e., the regulator  102  is in the OFF state). As shown in  FIG. 2B , both the first period of time T 1  that the sampling signal S 1  is disabled and the second period of time T 2  that the sharing signal S 2  is enabled are located in the period of time (i.e., the period of time Toff) that the switching signal EN is disabled and the inversed switching signal ENB is enabled. It is understood that similar to the waveform operation shown in  FIG. 2A , the waveform operation shown in  FIG. 2B  is applicable for various embodiments of the present disclosure. 
       FIG. 3A  illustrates a circuit diagram of a LDO regulating device  30  according to an embodiment of the present disclosure. The signal operation of the LDO regulating device  30  is the same as that shown in  FIG. 2A . In this example, the output transistor M 1  and the control switch SWc of the regulator  302  of the LDO regulating device  30  are implemented as P-type transistors, such as PMOS. Moreover, in this embodiment, the setting voltage SET coupled to the control switch SWc has a high voltage level, e.g., supply voltage, and the control switch SWc is controlled by the switching signal EN. 
       FIG. 3B  illustrates a circuit diagram of a LDO regulating device  30 ′ according to another embodiment of the present disclosure. The signal operation of the LDO regulating device  30 ′ is the same as that shown in  FIG. 2A . In this example, the output transistor M 1  and the control switch SWc of the regulator  302  of the LDO regulating device  30  are implemented as N-type transistors, such as NMOS. Moreover, in this embodiment, the setting voltage SET coupled to the control switch SWc has a low voltage level, e.g., ground, and the control switch SWc is controlled by the inversed switching signal ENB. 
       FIG. 4A  illustrates a circuit diagram of a LDO regulating device  40  according to yet another embodiment of the present disclosure. The signal operation of the LDO regulating device  40  is the same as that shown in  FIG. 2A . The main difference between the LDO regulating device  40  and the LDO regulating device  30  shown in  FIG. 3A  is that the regulator  402  of the LDO regulating device  40  further includes a feedback capacitor Cf. As shown in  FIG. 4A , the feedback capacitor Cf couples between the output node Nout and the feedback node Nfb. During the period of time that the pre-charge capacitor Csas electrically connects to the feedback node Nfb (e.g., the second period of time T 2  shown in  FIG. 2A ), the pre-charge capacitor Csas shares charges with the feedback node Nfb, so the magnitude of the feedback voltage Vfb can be determined. 
     Because the capacitance loading on the output node Nout is quite large in most of applications, the feedback voltage Vfb after charge sharing can be estimated as: 
     
       
         
           
             Vfb 
             = 
             
               Vref 
               ⁢ 
               
                   
               
               ⁢ 
               2 
               × 
               
                 C_Csas 
                 
                   C_Csas 
                   + 
                   C_Cf 
                   + 
                   C_Cpar 
                 
               
             
           
         
       
     
     where C_Csas is the capacitance of the pre-charge capacitor Csas, C_Cf is the capacitance of the feedback capacitor Cf, and C_Cpar is the capacitance of the parasitic capacitor at the feedback node Nfb. 
     If C_Cpar is much smaller than C_Csas and C_Cf, the feedback voltage Vfb can be simplified as: 
     
       
         
           
             Vfb 
             = 
             
               Vref 
               ⁢ 
               
                   
               
               ⁢ 
               2 
               × 
               
                 C_Csas 
                 
                   C_Csas 
                   + 
                   C_Cf 
                 
               
             
           
         
       
     
     In this manner, as the pre-charge capacitor Csas and the feedback capacitor Cf are properly selected, the feedback voltage Vfb can be set to a required level after charge sharing. 
       FIG. 4B  illustrates a circuit diagram of a LDO regulating device  40 ′ according to yet another embodiment of the present disclosure. The signal operation of the LDO regulating device  50  is the same as that shown in  FIG. 2A . The main difference between the LDO regulating device  40 ′ and the LDO regulating device  40  shown in  FIG. 4A  is that the output transistor M 1  and the control switch SWc of the regulator  402 ′ of the LDO regulating device  40 ′ are implemented as N-type transistors, such as NMOS. Moreover, in this embodiment, the setting voltage SET coupled to the control switch SWc has a low voltage level, e.g., ground, and the control switch SWc is controlled by the inversed switching signal ENB. 
       FIG. 5A  shows an example of waveforms of signals related to the LDO regulating device  40 . The switching signal EN, the sampling signal S 1  and the sharing signal S 2  have waveforms the same as that shown in  FIG. 2A . In this example, the ratio of the pre-charge capacitor Csas and the feedback capacitor Cf are designed to meet the following equation: 
     
       
         
           
             
               
                 
                   
                     
                       Vref 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                       × 
                       Csas 
                     
                     
                       Csas 
                       + 
                       Cf 
                     
                   
                   &lt; 
                   
                     Vref 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
               
               
                 
                   ( 
                   
                     eq 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
     When (eq1) is satisfied, i.e., the feedback voltage Vfb is less than the first reference voltage Vref 1 , the output voltage Vout will present overshoot behaver in the beginning of the period of time Ton. 
     As shown in  FIG. 5A , in the beginning of the first period of time T 1  (e.g., the falling edge of the sampling signal S 1 ), the sampling signal S 1  is disabled to turned off the sampling switch SWa, such that the second reference voltage Vref 2  electrically disconnects from the pre-charge capacitor Csas and the output voltage Vout is temperately higher than the final stable value (overshoot). 
     In the beginning of the second period of time T 2  (e.g., the raising edge of the sharing signal S 2 ), the sharing switch SWb is turned on in response to the enabled sharing signal S 2 , such that the pre-charge capacitor Csas electrically connects the feedback node Nfb for charge sharing. Meanwhile, the feedback voltage Vfb increases to a level smaller than the first reference voltage Vref 1 , thereby forcing the comparing circuit  1022  to increase the overdrive of the output transistor M 1 . In the end of the first period of time T 1  (e.g., the raising edge of the sampling signal S 1 ), the feedback voltage Vfb has been pre-charged to a predetermined voltage level V 1  that is very close to the stable state voltage level V 2 . Therefore, the time interval required to charge the feedback voltage Vfb from a low voltage level (0V) to the stable state voltage V 2  is reduced. In contrast, if without the pre-charger  104 , the time interval required to charge the feedback voltage Vfb from a low voltage level (0V) to the stable state voltage V 2  only depends on the charging through the feedback path included in the regulator  102 , i.e., charging through the resistor-capacitor path. In such situation, compared to that the design that employing the pre-charger  104 , it takes more time for charging. 
       FIG. 5B  shows another example of waveforms of signals related to the LDO regulating device  40 . The main difference between embodiments of  FIGS. 5A and 5B  is that in this example, the ratio of the pre-charge capacitor Csas and the feedback capacitor Cf are designed to meet the following equation: 
     
       
         
           
             
               
                 
                   
                     
                       Vref 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                       × 
                       Csas 
                     
                     
                       Csas 
                       + 
                       Cf 
                     
                   
                   &gt; 
                   
                     Vref 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
               
               
                 
                   ( 
                   
                     eq 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
     When (eq2) is satisfied, i.e., the feedback voltage Vfb is greater than the first reference voltage Vref 1 , the output voltage Vout will present undershoot behaver in the beginning of the period of time Ton. 
     As shown in  FIG. 5B , in the beginning of the first period of time T 1 , the sampling signal S 1  is disabled to turn off the sampling switch SWa, such that the second reference voltage Vref 2  electrically disconnects from the pre-charge capacitor Csas and the output voltage Vout is temperately lower than the final stable value (undershoot). 
     In the beginning of the second period of time T 2 , the sharing switch SWb is turned on in response to the enabled sharing signal S 2 , such that the pre-charge capacitor Csas electrically connects the feedback node Nfb for charge sharing. Meanwhile, the feedback voltage Vfb boosts to a level larger than the first reference voltage Vref 1 , thereby forcing the comparing circuit  1022  to decrease the overdrive of the output transistor M 1 . In the end of the first period of time T 1 , the feedback voltage Vfb has been pre-charged to a predetermined voltage level V 1 ′ that is very close to the stable state voltage level V 2 ′. Therefore, the time interval required to charge the feedback voltage Vfb from a low voltage level (0V) to the stable state voltage V 2 ′ is reduced. 
     In circuit design, considering that when the regulator  102  is power on, the periphery circuit loads may share the current of the regulator  102 , causing the output waveform to drop rapidly. Therefore, assuming that the capacitors Csas and Cf have been set with predetermined values, the second reference voltage Vref 2  is usually designed as being larger than the first reference voltage Vref 1 , so as to overshoot the output transistor M 1  to compensate the current. In this manner, the output waveform can reach to the stable state voltage more quickly. 
       FIG. 6  shows a flowchart of an operating method for a LDO regulating device according to an embodiment of the present invention. For explanatory purposes, the operating method is described herein with reference to the LDO regulating device  10  shown in  FIG. 1A . However, the present invention is not limited thereto. The operating method can be adapted to each LDO regulating device of the abovementioned embodiments. 
     At step  602 , the regulator  102  is configured to adjust the output voltage Vout provided to the output node Nout in accordance with the voltage difference between the first reference voltage Vref 1  and the feedback voltage Vfb on the feedback node Nfb. 
     At step  604 , the pre-charger  104  is configured to electrically disconnect from the feedback node Nfb and accumulate charges by itself when the regulator  102  is in the OFF state. 
     At step  606 , the pre-charger  104  is configured to electrically connect to the feedback node Nfb for charge sharing with the feedback node Nfb. 
     With the proposed method, the feedback voltage Vout can be increased to a suitable level in a very short time, so the required startup time of the LDO regulating device can be effectively shortened. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.