Patent Publication Number: US-2023163869-A1

Title: Controller which adjusts clock frequency based on received symbol rate

Description:
FIELD 
     Certain embodiments relate to synchronization generally, and in particular to clock and/or frequency synchronization. 
     BACKGROUND 
     Known, e.g., from co-owned U.S. Pat. No. 10,778,406 to Gaist et al., is a “network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.” 
     SUMMARY OF THE DISCLOSURE 
     Certain embodiments seek to provide improved clock and/or frequency synchronization e.g., in network devices. 
     Certain embodiments seek to provide an improved system and method for disciplining a PHC (PTP Hardware Clock) or, generally, clock. 
     Certain embodiments seek to provide PHC frequency adjustments in at least one network device&#39;s PHC, based on the network&#39;s RX symbol rate, e.g., by updating the PHC&#39;s DPLL (digital phase-locked loop). 
     Certain embodiments seek to provide a system which assures accurate timing. 
     Certain embodiments seek to provide improved network devices such as improved NICs (Network Interface Cards) including improved smart NICs, and/or improved switches. 
     Certain embodiments seek to improve the PTP standard. 
     Certain embodiments seek to improve the SyncE standard. 
     Certain embodiments seek to maintain a PHC by maintaining accuracy and\or stability of the Precision Time Protocol (PTP) hardware clock&#39;s frequency. Providing the above controller is useful in maintaining accuracy and\or stability of the Precision Time Protocol (PTP) hardware clock&#39;s frequency. The term “clock accuracy” (or “clock frequency accuracy”) as used herein describes an extent to which a clock&#39;s actual frequency matches or is equal to a specified clock frequency. The term “clock stability” (or “clock frequency stability”) describes an extent to which a clock&#39;s oscillator frequency resists fluctuations. Variation in temperature is an example factor that may affect stability. Other factors that may affect stability include all or any subset of: aging of the clock&#39;s hardware, supply voltage to the clock, shock to or vibration of the clock, and capacitive load driven by the clock. 
     At least the following embodiments are included in the scope of the invention: Embodiment 1. A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system and which may or may not have a PTP Hardware Clock (PHC), the system comprising: a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and/or to adjust the PTP Hardware Clock&#39;s frequency responsive to the information characterizing the network peer oscillator frequency. 
     Embodiment 2. The system according to any of the preceding embodiments and also comprising apparatus which extracts the information characterizing a network peer oscillator frequency from the RX symbol rate. 
     Embodiment 3. The system according to any of the preceding embodiments wherein extraction of the information from the RX symbol rate is implemented in firmware and/or hardware, to mitigate software-to-firmware/hardware interface jitter. 
     Embodiment 4. The system according to any of the preceding embodiments wherein the controller is implemented at least partly in hardware. 
     Embodiment 5. The system according to any of the preceding embodiments wherein the controller is implemented at least partly in firmware. 
     Embodiment 6. The system according to any of the preceding embodiments and also comprising Time Source Selection functionality which selects a network port having an RX symbol rate known to a partner, from among plural network ports having an RX symbol rate known to the partner, from which the partner will extract the network peer oscillator frequency. 
     Embodiment 7. The system according to any of the preceding embodiments and also comprising a PTP hardware clock whose frequency is adjusted by the controller. 
     Embodiment 8. A method for providing clock and frequency synchronization among plural network devices wherein at least one network device from among the plural network devices has a Precision Time Protocol (PTP) hardware clock having a frequency, in a network having a network peer oscillator frequency and a received (RX) symbol rate, the method comprising extracting the network peer oscillator frequency from the RX symbol rate and/or using the network peer oscillator frequency thus extracted to adjust the frequency of the at least one network device&#39;s PTP Hardware Clock (PHC). 
     Embodiment 9. The system according to any of the preceding embodiments wherein the PTP Hardware Clock&#39;s update rate is updated as a function of an RX-PHC frequency ratio computed by extracting an RX frequency from an Ethernet physical layer over which clock signals are transferred. 
     Embodiment 10. The system according to any of the preceding embodiments wherein the PTP Hardware Clock&#39;s update rate is updated as a function of a ratio between RX frequency and TX frequency values extracted from an Ethernet physical layer over which clock signals are transferred. 
     Embodiment 11. The system according to any of the preceding embodiments wherein a “set status” command tells the network device whether or not to track one of the network device&#39;s network ports. 
     Embodiment 12. The system according to any of the preceding embodiments wherein at least one “set status” command tells the network device not to track any one of the network device&#39;s network ports, and, instead, to use an internal clock with default configuration. 
     Embodiment 13. The system according to any of the preceding embodiments wherein, responsive to a network node losing a link partner whose clock has higher accuracy than the network node itself, the network node goes into a “holdover” state in which incoming rate information from the network node&#39;s past is used. 
     Embodiment 14. The system according to any of the preceding embodiments wherein a software entity which owns the PTP Hardware Clock determines whether to perform phase adjustment and/or whether to perform frequency adjustment. 
     Embodiment 15. The system according to any of the preceding embodiments wherein a software entity which owns the PTP Hardware Clock selects, at least once, to perform frequency adjustment, and, wherein, responsively, the controller is activated. 
     Embodiment 16. The system according to any of the preceding embodiments wherein a frequency difference is periodically measured by the network device and wherein the PTP Hardware Clock&#39;s DPLL is updated accordingly. 
     Embodiment 17. The system according to any of the preceding embodiments and also comprising an active PTP which provides PTP daemon frequency updates and a DPLL for converting a core clock to a PTP Hardware Clock which is characterized by numerator and denominator parameters, one of which is allocated to the PTP daemon frequency updates, and the other of which is allocated to PTP Hardware Clock frequency adjustment. 
     Embodiment 18. The system according to any of the preceding embodiments wherein a protocol is used by the network device to communicate with at least one link partner to extract and then use frequency. 
     Embodiment 19. The system according to any of the preceding embodiments and wherein the protocol carries information regarding the at least one link partner&#39;s clock quality. 
     Embodiment 20. The system according to any of the preceding embodiments and wherein the link partner&#39;s clock quality is represented by at least one of SSM codes and ESSM codes. 
     Embodiment 21. The system according to any of the preceding embodiments and wherein the protocol carries information on the frequency stability of the link partner&#39;s clock. 
     Embodiment 22. The system according to any of the preceding embodiments wherein the network device has a symbol rate which is synchronized to an external frequency source. 
     Embodiment 23. The system according to any of the preceding embodiments wherein the external frequency source is based on GPS. 
     Embodiment 24. The system according to any of the preceding embodiments wherein the external frequency source is based on SyncE. 
     Embodiment 25. The system according to any of the preceding embodiments and wherein the protocol carries a unique bit sequence per each of plural available clocks, which is used by Time Source Selection functionality to identify each of the plural available clocks. 
     Embodiment 26. The system according to any of the preceding embodiments and wherein the protocol includes exchanging information between partners in a handshake procedure. 
     Embodiment 27. The system according to any of the preceding embodiments and wherein the protocol includes sending a heartbeat message periodically and also includes sending, each time a change occurs in a link partners&#39; clock&#39;s quality level, a message announcing the change. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates a HW (hardware) architecture in which data extracted from the symbol rate may be used for adjustments to the PHC. 
         FIG.  2    is a SyncE system level diagram. 
         FIG.  3    illustrates an embodiment which is applicable to existing or legacy HW, without any board modification which involves deploying a custom clock synchronizer on the board. 
         FIG.  4    is an example implementation of the embodiment of  FIG.  1    which typically includes a packet time-stamping path, through the PHC. 
         FIG.  5    is a simplified block diagram illustration of Time Source Selection functionality constructed and operative in accordance with an embodiment, which selects a network port having an RX symbol rate known to a partner, from among plural network ports having an RX symbol rate known to the partner, from which the partner will extract the network peer oscillator frequency.  FIG.  6    illustrates a system which serves plural PHCs. 
         FIGS.  7   a ,  7   b , and  7   c    each show graphs illustrating typical behavior of HW UTC Time using various synchronization methods. 
         FIG.  8    is a schematic block diagram view of a network device constructed and operative in accordance with an embodiment of the present invention. 
         FIG.  9    is a simplified block diagram illustration of a SyncE tree including one PRC (Primary Reference Clock) and plural EEC (Ethernet Equipment Clock) devices. The arrows indicate the timing flow; the tree&#39;s “leaves” are shown in in bold. 
         FIG.  10    is a block diagram depicting an architecture for constructing an ensemble time and for using an ensemble time to adjust a PHC and/or local clock. 
     
    
    
     DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS 
     Synchronous Ethernet, aka SyncE, is a standard for computer networking which may be used to facilitate transferal of clock signals over Ethernet&#39;s physical layer. Synchronous Ethernet is described for example in the following https link: albedotelecom.com/src/lib/WP-SynE-explained.pdf. In SyncE, synchronization and transport networks may be partially mixed, e.g., if some network elements transmit data and also distribute clock signals to other network elements. Networks with SyncE may be of different topologies such as, most typically, tree/s and/or forest/s, or, by way of non-limiting example, ring or meshed topologies. In any network, SyncE clock hierarchy typically has a “Tree” topology, or a “Forest” topology including a disjoint union of trees. The SyncE clock hierarchy typically relies on a reference (aka master) clock which may be distributed to “slave” or follower clocks. 
     IEEE Std 1588™-2008 (1588v2) is a standard that defines the Precision Time Protocol (PTP) which may be used to distribute frequency, phase and time over packet based networks. 
     Clock synchronization, useful for computing machines having PTP clients, is described in published US application 2020/0162234 to Almog et al. 
     Clock synchronizer technology (such as, by way of non-limiting example, TI—BAW-Texas Instruments Bulk Acoustic Wave technology) enables ultra-low jitter clocks for highspeed networks e.g., as described in the following online white paper: 
     ti.com/lit/wp/snoaa34/snoaa34.pdf?ts=1630651534227&amp;ref url=https %253A %252F %252Fww w.google.com %252F. 
     Time synchronization and frequency synchronization (aka syntonization) among network (e.g., connected via Ethernet, or any other appropriate network) devices may be used in many network applications. One application of using a synchronized clock value is for measuring latency between two devices. If the clocks are not synchronized, the resulting latency measurement will be inaccurate. 
     Two standards have been developed in view of the above: (a) PTP (Precision Time Protocol) and (b) SyncE (Synchronous Ethernet). The PTP is a standard targeting clock synchronization whereas SyncE is a standard to enhance the PTP stability and discipline the crystal oscillator (XO). 
     PTP provides a protocol that aligns the host time and frequency to an external clock (called PTP Master). Distribution of time and frequency over the network occurs by transmitting time-stamped packets. When using PTP, the adjustment of the local clock frequency does not have to be using a physical changing of the oscillator frequency (e.g., an analog implementation); it can use a fixed frequency local oscillator, compute the ratio of the PTP master and local rates, and multiply the fixed local clock by this ratio (e.g., a digital implementation). 
     SyncE is an International Telecommunication Union Telecommunication (ITU-T) Standardization Sector standard for computer networking that facilitates the transference of clock signals over the Ethernet physical layer. In particular, SyncE enables clock synchronization inside a network with respect to a SyncE master frequency source. Each network element (e.g., a switch, a network interface card (NIC), or router) needs to recover the master clock from highspeed data received from the master device clock source and use the recovered master clock for its data transmission in a manner such that the master clock spreads throughout the network. This typically requires analog implementation. 
     The SyncE synchronization hierarchy is typically managed over a dedicated Ethernet channel (ESMC— Ethernet Synchronization Messaging Channel). The messages in this channel typically carry information regarding the source clock this timing flow is spreading. This information, aka “timing source information”, typically includes the quality level (QL) of the source clock. 
     Problems when using PTP synchronization without SyncE may include the following: 
     1. In the interval between sync messages, the local oscillator may drift, resulting in a time offset between the device and the PTP master. 
     2. During the exchange of sync messages, the local oscillator may drift. If the device and the master are not syntonized during the exchange of sync messages, the PTP synchronization will be less accurate. 
     3. Typically, if PTP messages are not available (e.g., PTP holdover), the device quickly gets out of sync. 
     This can be improved by (a) increasing the rate of sync messages at the cost of wasting network resources and/or (b) by using a better, or more costly, local oscillator. 
     Embodiments herein are low-cost, and do not require a network load. In addition, typically, when using SyncE, each SyncE device may need dedicated, costly HW, such as a jitter attenuator PLL, to allow the SyncE device to spread the master frequency throughout the network using data transmission. In contrast, applying embodiments described herein for leaves in the SyncE tree (e.g., the tree of  FIG.  9   ) could yield similar performance at lower cost, even using legacy equipment. 
     In contrast, if HW board modifications are needed, e.g., to deploy a custom clock synchronizer on a board, this prevents applicability to existing deployments where a board with the custom clock synchronizer is not present. 
     The term “network peer oscillator frequency” is used herein to refer to the frequency of oscillation of an oscillator included in a “network peer”; the “network peer” is a network device serving as a local device&#39;s “peer” given that the network device is connected to the local device via a network. 
     According to certain embodiments, the network peer oscillator frequency is extracted from the RX symbol rate and the network peer oscillator frequency thus extracted is used to adjust the frequency of at least one network device&#39;s PHC (PTP Hardware Clock). It is appreciated that in contrast to PTP, frequency information is extracted from the RX symbol rate, rather than being encapsulated in packets, as in PTP. Extraction and adjustment may be implemented in firmware e.g., as described herein, however, alternatively, both (together or apart), or either, may be offloaded to hardware. 
     Even if this embodiment does not enable the device (e.g., a NIC as shown in  FIG.  1   , or a switch, or any other appropriate network device) to spread the master frequency throughout the network using data transmission, the embodiment is beneficial in various use-cases, such as but not limited to the following: 
     1. When the device is the last node in a SyncE timing flow (a leaf in the SyncE tree e.g., as shown in bold in  FIG.  9   ) 
     2. In the absence of SyncE, when: 
     2a. One or more of the device&#39;s peers have a better oscillator than the device&#39;s local (own) oscillator; and/or 
     2b. One or more of the device&#39;s peers have their local clock rate syntonized to the reference or PTP master, using PTP (using an analog implementation); and/or 
     2c. There is a need for relative syntonization (e.g., syntonization between nodes and not to an absolute reference frequency) in a flat system (for example, when all nodes are connected to one switch). 
       FIG.  7    shows graphs a, b, c illustrating typical behavior of HW UTC Time using different synchronization methods. In graph (a), the synchronization uses PTP. As shown, progress of the HW UTC Time is determined by the Free Running clock and is adjusted to the ideal time of the reference or master using PTP messages. Thus between messages, the HW UTC Time drifts, jittering around the ideal time of the reference or master. Graph (b) shows that in the case of a fault in the PTP, the HW UTC Time keeps on drifting. Graph (c) shows synchronization which uses both PTP and SyncE (or PTP and PHC frequency adjustments based on RX symbol rate). The frequency of the HW UTC Time is stable between PTP messages, thus less jittery. 
       FIG.  1    illustrates a HW architecture in which data extracted from the symbol rate may be used for adjustments to the PHC, as indicated by the arrow from the controller and the PHC in  FIG.  1   . 
     For example, the RX frequency and TX frequency (where RX and TX herein refer, respectively, to receipt by the local device, on which the embodiments herein may be implemented (such as the NIC illustrated, by way of non-limiting example, in  FIGS.  1 - 6   , or any other appropriate network device), and to transmission by that local device, e.g., from/to the local device&#39;s link partner/s) can be extracted from the physical layer (e.g., the Ethernet physical layer over which SyncE transfers clock signals). Then, based on—RX-TX frequency ratio and/or—RX-PHC frequency ratio, the PHC update rate can be updated. Typically, the internal Digital phase-locked loop (DPLL), which is internal to the local network device&#39;s PHC (e.g., that of  FIG.  1   ) and may be responsible for translating the native frequency into PHC consecutive time update commands, is thus updated. 
     The term “DPLL” as used herein may be replaced by a reference to any control system that generates an output signal whose phase is related to the phase of an input signal, or any appropriate device which allows a changing rate or clock frequency to be expressed with reference to (e.g., computed in real time relative to) an original rate or frequency of a device&#39;s clock, or any appropriate hardware which updates the PHC and/or updates the PHC&#39;s and/or translates an internal clock frequency to a PHC update frequency, the PHC itself then typically being updated accordingly. 
     An example digital phase-locked loop is described in U.S. Pat. No. 11,070,214 to Franck et al. 
     A “link” is what provides data communication between network (aka net) elements or nodes. A link partner is a net element aka peer aka network node aka network device on the other side of the cable, e.g., as shown in  FIGS.  1  and  4   , which may or may not be SyncE. 
     A possible SW— HW/FW interface is a “set status” command, which tells the HW whether to track one of its network ports, or to ignore and use, say, an internal clock with default configuration. 
     A possible addition to such a SW— HW/FW interface is going to “holdover state”, after a network node loses a high accuracy link partner (a partner whose clock has higher accuracy than the network node itself). This allows past information regarding the incoming rate to be used, in order to be more accurate than the default configuration of the system. 
     Generally, each PHC is typically owned by a specific software entity, such as, say, a container, process, or virtual machine. Thus, if a network device e.g., NIC has n PHC&#39;s, they are respectively owned by n software entities. Still with reference to  FIG.  1   , it is appreciated that according to certain embodiments, a given software entity or daemon which owns a given PHC determines or selects whether to perform phase adjustment (e.g., by activating or initiating the daemon) and/or whether to perform frequency adjustment (e.g., by activating or initiating a firmware or hardware controller implementing the frequency adjustment described herein. This decision may include a determination e.g., by the given software entity, of whether or not to act in accordance with received PTP messages. 
     It is appreciated that Precision Time Protocol (PTP) distributes frequency, phase and time over packet-based networks. 
     The term “daemon” e.g., in a multitasking computer operating system, is intended to include any computer program which runs as a background process, rather than being directly controlled by an interactive user. A daemon may, for example, be started at boot time and may perform task/s at scheduled times and/or responsive to certain network request/s and/or hardware activity and/or other programs. 
     The architecture of the PHC of  FIG.  1    may be as described in any of the embodiments in co-pending United States Patent Application 20200162234 to Almog et al. or in co-owned U.S. Pat. No. 10,778,406 to Gaist et al. 
     It is appreciated that extraction of the network peer oscillator frequency from the RX symbol rate may be implemented in any appropriate type of physical network (such as, by way of non-limiting example, Ethernet, InfiniBand, PCIe, NVlink). Extraction may be implemented in FW or HW, e.g., to avoid SW to FW/HW interface jitter. 
     It is appreciated that typically, the RX symbol rate comprises a number of symbols that a local network device&#39;s controller receives per unit of time e.g., 1 second, where the unit of time is measured according to the local network device&#39;s controller&#39;s own clock. 
     Alternatively, the frequency difference could be measured using the difference between the number of received symbols and transmitted ones on the same lane. Since the number of transmitted symbols/sec is a result of the local frequency multiplied by a constant value it can be concluded that receiving more symbols than transmitting in the same period of time indicates that the local frequency is slower than the nominal frequency and local frequency should be raised. On the other hand, it can be concluded that receiving fewer symbols than transmitting in the same period of time indicates that the local frequency is faster than the nominal frequency and the local frequency should be lowered. This is applicable when the PHC and the serdes PHY are fed from the same clock source. Extraction, and/or use of the network peer oscillator frequency thus extracted to adjust the frequency of at least one network device&#39;s PHC, may occur periodically. For example, dozens of corrections, or hundreds, or thousands, or more, or less, may be made per second. 
     The periodic extracting of the network peer oscillator frequency and/or using the network peer oscillator frequency to adjust PHC frequency, may be triggered, at a given link port, by a SW component, which may, for example, provide a message indicating availability of a clock link-partner, whose accuracy is higher than the local clock (and typically higher than at least one other, or most other, or all other link-partner/s that the network device may have). This message may trigger the “extract and use” mechanism shown and described herein, on the given link port. 
       FIG.  2    is a SyncE System level diagram. As shown, the NIC is connected to a PRC (Primary Reference Clock e.g., as defined in ITU-T G.811 or SyncE high quality SRC clock via the network ports; it is appreciated that clock quality level may be as defined as in ITU-G.781. Digital logic  320  measures the wander difference between the transmission symbol rate to the rate symbols which are being received from the SyncE SRC link. The wander difference is “translated” into frequency adjustment commands  202  to the external component on clock synchronizer board  210 . This board  210  can do fine-tuning of the reference clock  280 . Changes in the reference clock are typically translated into changes in the TX symbol rate, e.g., by the APLL+DPLL  310 . The Digital measurement  320  then closes the control loop with the sync wander. The Reference Clock typically adjusts the frequency of the PHC  350  and brings the PHC&#39;s frequency close to the nominal, assuming that the SRC clock in the sync is better than the local device&#39;s oscillator (aka the “local oscillator”), e.g., assuming that the local device&#39;s link partner&#39;s oscillator&#39;s quality is better than the quality of the local oscillator. 
     Responsively, the PTP SW need not send frequency adjustments  420  to the DPLL  301  of the PHC  350 ; the PTP SW may, instead, send only time adjustments  410 . This yields a generated SyncE signal ( 10 ) for the next in line network nodes and/or a more accurate PHC, whose frequency has been stabilized. 
     Example systems performing at least some of the above operations are presented in U.S. Pat. No. 10,778,406 to Gaist et al. 
     It is appreciated that HW board modifications may be needed, specifically deploying the clock synchronizer  210  on the board between the XO (e.g., crystal oscillator) and the NIC, which may double the product&#39;s SKUs (stock keeping units) of the product and may prevent applicability to existing deployments where a board with clock synchronizer  210  is not present. 
       FIG.  3    illustrates an embodiment which is applicable to existing or legacy HW, without any board modification which involves deploying a custom clock synchronizer on the board. In this embodiment, when generating a SyncE signal is not a requirement, the system takes advantage of the fact that a stable in frequency signal (e.g., SyncE signal) is arriving, and may (e.g., if the incoming source SyncE signal, represented in  FIG.  3    by a south-to-north arrow, is noisy) use filtering and/or measurements (e.g., by way of non-limiting example, either linear or non-linear filtering, such as but not limited to average (mean) and/or median and/or low-pass and/or band-pass filtering) to discipline, if and as needed, the local DPLL, which, in turn, controls the local PHC. This yields a more stable PHC clock, such that the PTP software stack (daemon e.g.,) need not be burdened with performing frequency adjustments. 
     The filter can be implemented as part of the FW logic (e.g., the “FW controller” block of  FIG.  4   ), or may use dedicated HW, if such exists. Common filters which can be used are average filter, median filter, low-pass filter, band-pass filter. 
     In the embodiment of  FIG.  3   , the frequency adjustments  202  are sent from the digital measuring circuitry  320  to the DPLL  301 , whereas in the embodiment of  FIG.  2    the frequency adjustments are sent to clock synchronizer  210 . The operations of digital measuring circuitry  320 , e.g., in  FIGS.  2  and  3   , relieve the PTP software stack (daemon e.g.,) of the burden of performing frequency adjustments. 
       FIG.  4    is an example implementation of the embodiment of  FIG.  1    which typically includes a packet time-stamping path, through the PHC. It is appreciated that the PTP daemon may comprise a PTP SW stack, the performance counter may be in the network port or in the physical layer, and the SW interface of  FIG.  4    may include a reference Time Source Selection algorithm e.g., as described herein, thereby to control the internal controller which adjusts the frequency of the PHC&#39;s DPLL. 
     In  FIG.  4   , the frequency diff (typically, the difference between (a) the clock frequency of a PHC whose network element is configured to use an embodiment of the present invention and the RX symbol rate received from the link partner; or (b) the TX symbol rate of the network element configured to use an embodiment of the present invention and the RX symbol rate received from the link partner), is measured, e.g., by digital measuring circuitry  320  of  FIGS.  2 ,  3   . Alternatively, a standard other than the clock frequency of the link partner, may be used to measure the clock frequency of the PHC whose network device is configured to use an embodiment of the present invention, thereby to determine whether the clock frequency f of the PHC whose network device is configured to use an embodiment of the present invention, is the same as the standard, or higher than the standard, in which case f may be reduced to the standard, or lower, in which case f may be increased to the standard. Accordingly, the PHC DPLL of  FIG.  4    (which may be identical to the DPLL  301  in  FIGS.  2 ,  3   ) is typically updated. It is appreciated that the digital PLL (DPLL)&#39;s configuration determines the frequency of the PHC, which in turn is derived from the core clock. Typically, the PHC frequency is the core clock frequency multiplied by a factor (scalar) extracted from the DPLL&#39;s current configuration. The Time Source Selection SW typically knows to activate the firmware/hardware controller implementing the frequency adjustment e.g., because the Time Source Selection SW at a given network device may receive packets with data on link-partners&#39; clock quality level; this data may indicate whether partners&#39; clocks&#39; accuracies are high or low, e.g., relative to one another and/or relative to the given network device&#39;s clock. The Time Source Selection SW may, alternatively or in addition, query the given network device for the local clock quality level. If there is/are link partner/s with better (e.g., higher accuracy) clock quality, the given network device typically locks to one of those link partner/s, typically to the best available partner (the partner with the most accurate clock) and/or starts using that frequency (e.g., using “set status”).It is appreciated that  FIG.  4    illustrates a HW/FW embodiment which uses an open loop approach. As shown, a frequency difference e.g., between the RX symbol rate and TX symbol rate or between the PHC frequency and TX symbol rate) is periodically measured by the network device&#39;s FW, and the PHC&#39;s DPLL is updated accordingly. For example, all or any subsets of the following operations may be performed (e.g., by the firmware controller of  FIG.  4   ), in any suitable order e.g., as follows: 
     Operation a: Set up or provide measurement HW for new frequency diff periodic measurement (e.g., reset the physical layer&#39;s performance counter). 
     Operation b: Start measurement and wait a period of a pre-defined window. 
     Operation c: After time has passed, collect data regarding RX and TX symbol during measurement window, and calculate frequency differences (e.g., 10.235 PPB). 
     Operation d: Update PHC DPLL according to the measured PPB diff. 
     Operation e: Repeat the process at least once e.g., periodically e.g., continuously, by returning to operation a above. The embodiment of  FIG.  4    may co-exist with an active PTP (which provides PTP daemon frequency updates). A DPLL implementation for converting the core clock to PHC may have numerator and denominator parameters, which may determine the current frequency. One of those parameters, e.g., the numerator, may be allocated to the PTP daemon frequency updates, and the other parameter may be allocated to implementing the embodiment of  FIG.  4   . This would reduce accumulated drift between PTP consecutive updates. 
     Alternatively, a closed-loop approach may be used, in which a control mechanism keeps accumulated RX symbols and PHC time in sync. 
     In the open loop approach, no feedback is typically generated regarding the adjustment of the PHC&#39;s frequency, between RX and TX (or between the RX rate and TX rate). In contrast, in the closed loop approach, rather than (or in addition to) measuring TX (or the TX rate), the PHC is typically measured directly; this yields feedback regarding adjustment of the PHC&#39;s frequency. Typically, the “closed loop” implementation has a sense of the time that has passed on the local PHC, starting from the initial time the local PHC locked on the current link partner. According to one possible embodiment, a PD (proportional derivative) controller may be provided in which case, the loop on the local device may then try to run at the same speed as the link partner, but also tries to pass the same distance, where distance is proportional to time (e.g., time* constant1). At any given link speed, distance may be computed as number of bits*constant2 number of “symbols” * constant3. the time/bits/symbols that passed on the link partner may be extracted or determined or estimated, e.g., by accumulating bits/“symbols” on the RX side, and trying to “track” this value on the TX/local side. 
     For example, RX symbols may be translated to time, yielding an output scalar, which may be compared to the time that has elapsed on the PHC. Suitable parameter/s (such as, by way of non-limiting example, (1) RX symbols translated to time; and/or (2) the time that has elapsed on the PHC and/or (3) whether or not to filter, to discipline the local DPLL, and/or if so, which filter to use) may be added to the HW/FW controller (e.g., provided as input to the controller) to ensure that the controller&#39;s operation takes these parameter/s into account. It is appreciated that PID (proportional—integral—derivative) controllers are a suitable type of programmable controllers which can use such parameters for their internal logic/calculations. By way of non-limiting example, PI (proportional integral) and PD (proportional derivative) controllers would be suitable to maintain a closed control loop e.g., as described herein. 
     According to certain embodiments, the RX-symbol rate is measured or extracted inside the physical layer of the network port e.g., by “perf count/s” (performance counters in the network device e.g., NIC, where performance counters refer generally to code that, in software, monitors and/or counts and/or measures events—such as receipt of symbols by the network device, which were sent by a link partner of the network device). 
     Typically, in the embodiment of  FIG.  4   , there are time adjustments only in the PTP; these are typically provided by the PTP daemon to the PHC. There are typically frequency adjustments provided by the FW controller to the PHC DPLL e.g., as per any embodiment described herein. In normal behavior, or conventionally, the PTP daemon also sends (typically small) frequency adjustments. In contrast, in the embodiment of  FIG.  4   , these frequency adjustments from the PTP daemon are no longer necessary. 
     Any of the illustrated embodiments may include Time Source Selection software which serves as a software interface to the controller, as exemplified in  FIG.  4   , in which a “software interface” block is indeed shown. Time Source Selection SW block typically selects a network port having an RX symbol rate known to a partner, from among plural network ports having an RX symbol rate known to the partner, from which the partner may extract the network peer oscillator frequency. An example implementation of this Time Source Selection block is shown in  FIG.  5   , interfacing with a “NIC” such as the MC of  FIG.  4   , or any other appropriate network device. The “Set status (Reference source)” and “Local clock quality” arrows of  FIG.  5    are, for simplicity, represented as a single arrow in  FIG.  4   , since both are directed to the network device, typically to the FW. The “send\receive management packets” arrow may be directed to the network port and the network link, typically using the device&#39;s network stack, as is conventional. 
     If, for example, the SW of  FIG.  5    selects a certain port x, the relevant partner typically remains locked onto port x until the SW decides otherwise (decides to change the port), e.g., because a message is received through port y which indicates higher QL, in which case there may be a decision to start following port y, or perhaps because a change in the quality level (aka QL) of port x may result in port x&#39;s quality level being lower than the local QL, in which case there may be a decision to go to Holdover. 
     More generally,  FIG.  5    illustrates a SW implemented architecture which may be provided stand-alone or as an example implementation for the time source selection functionality shown and described herein. The architecture of  FIG.  5    typically includes Time Provider/s e.g., at least one SW entity (typically plural such entities), associated with a port and selected to be the timing source, and a selector. Each such software entity may include a class or structure e.g., as is conventional in object oriented programming. 
     Each Time Provider (or “clock provider”) typically comprises a network module configured to perform all or any subset of the following operations, suitably ordered e.g., as follows: 
     Operation a. Open a socket for management packets on the Time Provider&#39;s associated port. The management packets may, for example, be ESMC PDUs (Ethernet Synchronization Messaging Channel protocol data units) as defined on ITU-T G.8264, a specification document developed by the International Telegraph Union (ITU)&#39;s Telecommunication Standardization Sector (ITU-T), which is available online e.g., at the following https www link: itu.int/rec/T-REC-G.8264, and specifies the Ethernet Synchronization Messaging Channel (ESMC). Or the management packets may comprise any packet that carries information regarding quality/ies of neighbors&#39; clock/s. 
     Operation b. Send management packets to update neighbors regarding quality of the local clock. 
     Operation c. Parse received management packets to extract the timing source information therefrom. Upon timing source information change (the timing source identified in the received and parsed packets differs from the current timing source), the network module initiates the selector to determine whether or not the reference timing source (the source of the signal to be followed) should be changed, and a new reference, or master, selected instead. 
     The selector may comprise a selection algorithm running on a hardware processor, for selecting the best timing source from among the set of available timing sources e.g., the Local Clock and any Time Provider. The selection algorithm typically compares the quality (and possibly other relevant features such as manually configurable priority) of plural timing sources, e.g., all timing sources, in the set of timing sources available to (e.g., in communication with or linked to) the local device. The selection algorithm output typically comprises a status and reference timing source that the HW block of  FIG.  5   , which represents the network device e.g., NIC or DPU or switch, should track (e.g., should use as a timing source according to which the PHC&#39;s frequency is adjusted). The term “status” as used herein is intended to include a Tracking or Holdover or Free running reference timing source, or a clock which is being tracked (for example, say, the clock behind the link of port  1 ). 
     It is appreciated that if a network device has plural PHCs, the system herein may serve only one of them, or some, or all. For example,  FIG.  6    illustrates a system which serves plural PHCs ( 2 , by way of example) instead of serving just one PHC as is shown, by way of example, in  FIG.  1   . 
     Reference is now made to  FIG.  8   , which is a schematic block diagram view of a network device  1100  constructed and operative in accordance with an embodiment of the present invention. The network device  1100  comprises frequency generation circuitry including a voltage-controlled oscillator  1104  which, under control of a controller  1034  (which may comprise the controller  34  of  FIG.  1   ) and using a control signal  1102 , generates the clock signal. 
     Prior to the master clock or reference clock being designated by the network management function, the controller  1034  is configured to control the voltage-controlled oscillator  1104  to generate a clock signal with any suitable frequency, e.g., 156 MHz. Once the master clock has been designated by the network management function, the controller  1034  is configured to adjust the clock signal generated by the voltage-controlled oscillator  1104  using the control signal  1102  based on RX symbol rate— TX symbol rate, or the clock differential  1040  between the recovered remote clock (designated as the master clock) and the local clock generated by the PLL  1026 . 
     The network device  1100  includes a switch core die  1012  and a satellite die  1014 . The switch core die  1012  includes multi-chip module (MCM) core logic  1016  and switching circuitry to perform switching functions. The satellite die  1014  includes MCM satellite logic  1024  to perform receiving and transmission functions of the switch. The satellite die  1014  may also include a PLL  1026  and a plurality of receivers  1028  and connections to a plurality of ports (not shown). The receivers  1028  have been labelled individually as  1028 - 1 ,  1028 - 2  and  1028 - 3  for the sake of simplified reference. The switch core die  1012  and the satellite die  1014  are generally connected using an MCM interconnect  1030 . 
     Although the network device  1010  has been described with reference to a multi-die network switch, embodiments of the present invention may be implemented on any suitable network switch, including one or more dies, or any suitable network device, for example, but not limited to, a network router with one or more dies. 
     The receivers  1028  are configured to receive and buffer (in a buffer  1044 ) respective data streams  1038  (labeled  1038 - 1  to  1038 - 3 ) from respective remote clock sources (not shown). For the sake of simplicity only, one of the buffers  1044  has been labeled with the reference numeral  1044 . Each receiver  1028  may be implemented using any suitable hardware such as a Serializer/Deserializer (SerDes), for example, but not limited to, an LR SerDes RX. The data in the data streams  1038  generally arrives from the remote clock sources without a clock value. Each receiver  1028  may include a clock and data recovery (CDR) process  1042  running therein to recover a remote clock from its received data stream (or RX symbol rate)  1038 , for example based on transitions in the data of the received data stream  1038 . For the sake of simplicity, only one of clock and data recovery (CDR) process  1042  has been labeled with the reference numeral  1042 . The CDR of each receiver  1028  may also compute a clock differential  1040  (labeled  1040 - 1  to  1040 - 3 ), which is a difference between its recovered remote clock and the local clock (generated by the PLL  1026 ) (e.g., the recovered remote clock less the local clock) of the network device  1010 , so that for each received data stream  1038 , a difference between the recovered remote clock of the data stream  1038  and the local clock is computed. The clock differential  1040  is stored in a register of the network device  1100 . In some embodiments, each clock differential  40  is stored in a register of the receiver  1028  that computed that clock differential  1040 . The clock recovery may be implemented based on any suitable process, including a non-CDR based process, for example, but not limited to, using a delay-locked loop and oversampling of the data stream. The data streams  1038 , apart from their use in recovery of the remote clocks, generally include data for forwarding to other devices in the network. Therefore, the data streams  1038  are generally forwarded via the MCM interconnect  1030  to the multi-chip module core logic  1016  to perform various switching functions (or routing functions when the network device  1010  is implemented as a router). The recovered clocks and the clock differentials  1040  are generally not forwarded to the multi-chip module core logic  1016  via the MCM interconnect  1030 . 
     The example of  FIG.  8    shows three receivers  28 . The number of receivers  1028  may be any suitable number of receivers, and is not limited to three. The example of  FIG.  1    shows three boxes for the PLL  1026 , one with a solid-line box and two with a dotted-line box. The three boxes represent the same PLL  1026 , which has been duplicated twice for the sake of clarity. 
       FIG.  8    shows that data stream  1038 - 1  received by the receiver  1028 - 1  has a recovered clock of 3.001 GHz. Therefore, the clock differential  1040 - 1  between the recovered clock of the received data stream  1038 - 1  of 3.001 GHz and the local clock of 3 GHz is +333 PPM (e.g., the master clock is faster than the local clock by 333 PPM). The data stream  1038 - 2  received by the receiver  1028 - 2  has a recovered clock of 3.002 GHz. Therefore, the clock differential  1040 - 2  between the recovered clock of the received data stream  1038 - 2  of 3.002 GHz and the local clock of 3 GHz is +666 PPM (e.g., the master clock is faster than the local clock by 666 PPM). The data stream  1038 - 3  received by the receiver  1028 - 3  has a recovered clock of 2.999 GHz. Therefore, the clock differential  1040 - 3  between the recovered clock of the received data stream  1038 - 3  of 2.999 GHz and the local clock of 3 GHz is −333 PPM (e.g., the master clock is slower than the local clock by 333 PPM). 
     It is appreciated that the embodiments herein improve the SyncE standard by doing only a subset of what the SyncE standard demands (e.g., not generating a SyncE signal in the output signal, and, optionally, not using and/or extracting the clock as accurately as defined in the SyncE standard), but providing a much more stable frequency clock for a network device (and/or other value absent from SyncE), e.g., by using the extracted data from the symbol rate for adjustments to the PHC, without adding hardware requirements (to the contrary, embodiments described herein have fewer hardware aka HW requirements, relative to SyncE). 
       FIG.  10    illustrates a system in which an ensemble time is calculated and then used to adjust one or both of a PHC and a local clock. In this example, the device, such as a switch, may include a FW/HW controller that receives data from a plurality of NICs. Each NIC (e.g., NIC1, NIC2, NIC3, NICN) may have a unique transmission symbol rate (e.g., NIC1 Tx, NIC2 Tx, NIC3 Tx, . . . , NICN Tx). The symbol rate for each NIC may be measured at the device&#39;s FW/HW controller. 
     In some embodiments, the FW/HW controller may measure the frequency of all peers (e.g., of each NIC) by measuring each NIC&#39;s Tx symbol rate. The frequency measured for each NIC may be used to calculate an ensemble time. Said another way, given two or more peer frequencies, the FW/HW controller may calculate or determine an ensemble time. In some embodiments, an ensemble time may correspond to a weighted average of each frequency measured for each NIC. The ensemble time may correspond to a weighted average of each frequency that is weighted based on a NIC&#39;s crystal oscillator&#39;s QL and/or based on a NIC&#39;s crystal oscillator&#39;s past performance. 
     The FW/HW controller may then utilize the ensemble time as part of determining an adjustment to make to the local clock and/or a PHC. As one example, the FW/HW controller may determine a difference between the local clock and the ensemble time. The difference between the local clock and ensemble time may be determine the difference in parts per million and/or per billion and/or per trillion (e.g., PPM/PPB/PPT). The PPM differences may then, for example, be used to adjust the frequency of the local clock and/or the PHC of the device. In some embodiments, changes to the device&#39;s local clock may be used to create other clock adjustments to peers connected with the device. In other words, an adjustment made to the local clock of the device may propagate to other clock changes in the network. In some embodiments, two or more of the peer devices (e.g., the NICs) may have a similar or identical type of crystal oscillator. Utilization of an ensemble time may help to achieve a low-cost and stable-in-frequency device. 
     As described above, the ensemble time may be determined based on frequencies measured by two or more peers (e.g., a Tx symbol rate of two or more NICs). In some embodiments, the FW/HW controller may also be configured to identify one or more measured frequencies as being an outlier frequency and selectively determine not to include that measured frequency in the set of measured frequencies used to calculate ensemble time. Said another way, the FW/HW controller may be configured to identify when one or more Tx symbol rates corresponding to an outlier Tx symbol rate. The outlier may then be excluded from consideration as part of the ensemble time. The capability to identify outlier frequencies may enable the FW/HW controller to detect and handle faulty clocks as part of determining ensemble time. In this way, the ensemble time may be determined using clocks of different peers that are operating properly. 
     In some embodiments, the approach of using ensemble time as depicted and described in connection with  FIG.  10    may be combined with other approaches depicted and described herein. For instance, a FW/HW controller may be configured to create a full solution for cluster syntonization using a local clock that has been updated based on a calculated ensemble time. In some embodiments, the device (switch) may have its local clock connected to PHCs of one or more NICs (e.g., NIC1, NIC2, NIC3, NICN). The PHC of the one or more NICs may be configured to follow the local clock of the device (switch) that is being adjusted based on an ensemble time calculated at the FW/HW controller of the device using the frequencies measured by the NICs. In other words, the device (switch) may be configured to use the symbol rate of multiple NICs to create a time ensemble and then adjust its Tx symbol rate accordingly. Then all NIC PHCs will follow the local clock of the device (switch) thereby providing each MC with the time ensemble quality frequency. As long as the NICs receive the appropriate clock signal from the device (switch), then the PHC drift will be sufficiently managed and minimized. 
     For example, if an Nvidia network device e.g., NIC without SyncE support is used in a SyncE network, embodiments herein would provide the NIC&#39;s PHC with a far more stable frequency clock. 
     It is appreciated that frequency adjustment may be either absolute or relative. For example, consider the controller of  FIG.  1    which may be implemented in firmware and may use the SyncE protocol. The FW may gather frequency related data from the HW and may compute, say, parts per million and/or per billion and/or per trillion (aka PPM/PPB/PPT) differences between RX and TX rates, to be used as a frequency diff value. For example, 1 PPB means 1 nano second of accumulated drift for each second, assuming one of the frequencies is perfect. A positive/negative number indicates which clock is faster/slower. Then the FW converts the frequency diff value, e.g., the PPB value, to a DPLL configuration related parameter (e.g., “TI BAW”) of the external clock device. The internal configuration may be of the following type: 
       FREQ_OUT=FREQ_IN*(INT+NUMERATOR/DENOMINATOR) 
     Typically, everything, except the numerator, is kept constant, such that the internal configuration can be “solved”, after which the relative PPB value is converted to a value to be added to/subtracted from the numerator to get the desired PPB. Alternatively, the PHC DPLL may be of type 
       FREQ_OUT=FREQ_IN*(NUMERATOR/DENOMINATOR) 
     which lacks the INT value of the DPLL configuration related parameter (clock synchronizer), in which case conversion from the relative PPM/PPB/PPT value to internal DPLL parameters changes accordingly. 
     PTP4L (an implementation of the Precision Time Protocol (PTP) according to IEEE standard 1588 for Linux which implements a Boundary Clock (BC) and an Ordinary Clock (OC)) uses absolute frequency updates and has a PPB value which is relative to 1 billion. This value is absolute, being relative to a constant. For example, is the value is +1 million=&gt;the original frequency of the device (as derived from the core clock frequency of the device) is increased by (1 billion+1 million)/(1 billion)=1.001. If the same value is obtained again, the original frequency of the device is increased by the same value again, e.g., the action is the same as the action after the previous update. In contrast, in a relative update mode (or embodiment), 1 million PPB update received twice in a row will result in an increase of 1.001*1.001=1.002001 the second time, e.g., in a relative update mode (or embodiment), the action the second time is not the same as the action after the previous update. 
     SyncE is an Ethernet protocol, but applicability of embodiments herein is not limited to Ethernet and may be implemented in (typically packet-based) networks other than Ethernet (such as InfiniBand, PCIe, NVlink, etc.). SyncE, specifically, is a standard which requires frequency information to be provided by a selected network port from among plural network ports, and then, the partner of the selected network port does the following with that frequency information: a. distributes the clock provided by the selected port, to other network ports; and b. adjusts its (the partner&#39;s) own PHC. This causes accurate clocks to be disseminated through the network. 
     Any suitable protocol may be used by net elements according to embodiments of the invention, when communicating with a link partner to extract and use frequency as described herein. As described elsewhere, the management packets may for example be ESMC PDUs (Ethernet Synchronization Messaging Channel protocol data units) as defined on ITU-T G.8264, a specification document developed by the International Telegraph Union (ITU)&#39;s Telecommunication Standardization Sector (ITU-T), which is available online e.g., at the following https www link: itu.int/rec/T-REC-G.8264, and specifies the Ethernet Synchronization Messaging Channel (ESMC). For example, if the network uses SyncE and a given net element aka network device is the last device in a SyncE chain, ESMC messages (e.g., as defined on ITU-T G.8264) may be sent from a SyncE device at least once a second, and may be used to declare the clock quality. If the SW receiving these messages recognizes that its link partner has a clock quality better than or more accurate than its own local clock quality—the software typically starts tracking this link partner frequency, extracting and using this link partner&#39;s frequency, as described herein. 
     However, embodiments herein may be used without a SyncE link partner, in which case the protocol may be similar to ESMC and may also be characterized as follows: 
     The protocol may carry information regarding neighbors&#39; (e.g., link partners&#39;) clock quality. This quality may for example be represented by SSM codes and Enhanced SSM codes (used in ESMC) or may, alternatively, use different codes. The protocol may, alternatively or in addition, carry other information on the frequency stability of the clock such as the expected frequency stability at different temperatures and/or over different periods (short/long term stability). The device symbol rate may be synchronized to an external frequency source, such as GPS or SyncE. 
     The protocol may, alternatively or in addition, carry a clock identifier (e.g., A unique bit sequence per clock), which may be used by the time source selection SW to identify each clock. 
     Messages may be sent by each network element to its link partners and may not be forwarded by any network element. Information may be exchanged in a handshake procedure or may be announced periodically (e.g., heartbeat message, periodically e.g., each second). In the event of a change in the quality level e.g., of link partners&#39; clock/s, a special message announcing the change may be transmitted. 
     It is appreciated that NICs are referred to herein, being an example a network device. However, the embodiments herein are not limited in their applicability, and, instead may be implemented in any network device such as, by way of non-limiting example, a NIC, data processing unit aka DPU (data processing unit), or switch. 
     The term “master” (or “reference”) is used herein to describe a network element which is followed by other (“follower” or “slave”) network elements. Typically, messages sent between network elements (such as periodic and/or special SyncE messages) affect each network element&#39;s decision of who to follow at any given time, e.g., as described herein. It is appreciated that given a network topology, some network elements (e.g., “leaves”) may not be followed by any other network element. Absence of messages may also affect each network element&#39;s decision of who to follow at any given time, e.g., if the network element expected a message from a given link partner within a given time period, and failed to receive same. 
     The term “Network device” (aka network element) as used herein, is intended to include, by way of non-limiting example, a switch, network interface card (NIC) such as a smart NIC, router, or DPU. 
     The terms “RX symbol rate” and “RX frequency” may be interchanged herein. 
     The terms “TX symbol rate” and “TX frequency” may be interchanged herein. 
     The term “all” is used herein for simplicity, to describe example embodiments. It is appreciated, however, that alternatively, whatever is said herein to be true of or to characterize or to pertain to, “all” members of, or “each” member of, or “every” member of, a certain set can also, in other embodiments, be true of, or characterize or pertain to, most but not all members of that set, or all but a few members of that set, or at least one (but less than all) member/s of the set. 
     For example, a selection algorithm may compare quality and/or manually configurable priority and/or other features of all sources in a set of available timing sources. But. alternatively, most, but not all sources, or all but a few sources, or at least one (but less than all) source in that set, may be compared. 
     The specific embodiments shown and described herein are not intended to be limiting. Any detail therewithin may for example be provided, or not provided, in conjunction with a general system which measures TX and/or RX on a local device and on the local device&#39;s link partner/s and, accordingly, generates an output which controls frequency adjustments in hardware, rather than, necessarily, using the local device&#39;s controller&#39;s firmware to facilitate the local device&#39;s PHC frequency adjustments. 
     It is appreciated that software components of the present invention may, if desired, be implemented in ROM (read only memory) form. The software components may, generally, be implemented in firmware or hardware, if desired, using conventional techniques. It is further appreciated that the software components may be instantiated, for example as a computer program product, or on a tangible medium. In some cases, it may be possible to instantiate the software components as a signal interpretable by an appropriate computer, although such an instantiation may be excluded in certain embodiments of the present invention. 
     It is appreciated that various features of the invention which are, for clarity, described in the contexts of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment, may also be provided separately, or in any suitable sub-combination. 
     It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather, the scope of the invention includes, inter alia, the appended claims and equivalents thereof.