Patent Publication Number: US-4734701-A

Title: Null processing receiver apparatus and method

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to apparatus for receiving and combining together a plurality of modulated signals, and, more particularly, to apparatus of this kind that controllably weight the various signals being combined so as to null out an interference signal superimposed on each one. 
     Null processing receivers of this kind are useful in numerous applications. One example is a system for processing signals received by a multi-element antenna array in the presence of an interference (e.g., jamming) signal received from an unspecified, variable direction. In such a system, the modulated rf signals supplied by the various antenna elements are typically summed together to produce a sum signal for subsequent down-converting, demodulation and baseband processing. Prior to summation, each rf signal is controllably adjusted in amplitude and phase angle (i.e., complex weighted) so as to null or cancel out the presence of the interference signal in the sum signal. This adaptive interference cancelation is usually performed in a way that minimizes the sum signal&#39;s power, since it is assumed that the power of the interference signal greatly exceeds that of the desired information signal. 
     Since the direction from which the interference signal is received by the antenna elements can vary, the complex weighting must be controllably adjustable in order to maintain continuous nulling. This adjustment actually steers the spatial nulls present in the composite antenna pattern, to align a particular spatial null with the detected interference signal direction. 
     The modulated antenna signals whose amplitudes and phase angles are being continuously adjusted are at radio frequencies, typically L-band. Circuitry for effecting this adjustment typically includes highly sensitive microstrips, strip lines, and minute coils of wire, all of which can require sensitive trimming. Not only is such circuitry considered not entirely reliable, but it also is considered excessive in size, weight, power consumption and cost. 
     It should therefore be appreciated that there is a definite need for a null processing receiver of the kind described above that not only provides improved reliability, but also a reduction in size, weight, power consumption and cost. The present invention fulfills this need. 
     SUMMARY OF THE INVENTION 
     The invention is embodied in a signal processing receiver apparatus that combines a plurality of received signals in a prescribed fashion, to null out an interference signal contained in each of them, the processing being effected without the need for an amplitude or phase angle adjustment of any rf signals. The apparatus is substantially reduced in size, weight, power consumption and cost, yet it provides equal if not improved effectiveness in nulling out the interference signal and it has a substantially improved reliability. 
     More particularly, the signal processing receiver apparatus of the invention receives and demodulates a plurality of signals, each for example received from a separate antenna element, to produce a primary information signal and one or more related auxiliary information signals. The interference signal is contained within all of these information signals. Weighting means operates on each of the auxiliary signals, to produce a corresponding number of weighted or intermediate signals, and summing means sums together the primary signal and the one or more intermediate signals to produce a sum signal in which the interference signal is substantially nulled out. The weighting means includes correlation means responsive to the one or more auxiliary signals, for producing a corresponding number of weighting signals, and multiplier means for multiplying the auxiliary signals by their corresponding weighting signals, to produce the intermediate signals. 
     In the preferred embodiment, the correlation means includes a plurality of multipliers or mixers and an equal number of integrators. Each mixer multiplies the sum signal by a separate one of the auxiliary information signals, to produce a product signal that is integrated by the corresponding integrator to produce one of the weighting signals. 
     The apparatus of the invention has particular utility where the signals received from the various antenna elements are carrier signals modulated by a predetermined digital code signal (e.g., a pseudorandom code). In such a system, the demodulator means down-converts each modulated signal using a common local oscillator signal and then multiplies each such down-converted signal by a common, locally-generated replica of the predeter mined digital code signal. This removes the digital code signal and ultimately yields the primary and auxiliary information signals. 
     The apparatus of the invention preferably operates at a predetermined duty cycle. In one part of the cycle, the apparatus functions as described above to null out the interference signal, while in another part of the cycle, the various weighting signals are maintained at their current levels. During the latter part of the cycle, the resulting sum signal is processed further, to extract certain data from it. To ensure that the apparatus does not null out the desired information signal, a bogey code can be substituted for the digital code replica during the former part of the cycle, when nulling is being effected. 
     In another aspect of the invention, the apparatus operates as quadrature receiver, with each received modulated signal being multiplied by a pair of orthogonal carrier signals. This produces a pair of primary information signals and one or more pairs of related auxiliary information signals. Each primary signal is summed with a different set of intermediate signals created based on the entire set of auxiliary signals, in substantially the same manner as described above. 
     Other aspects and advantages of the present invention will become apparent from the following description of the preferred embodiment, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram of the receiver portion of a Global Positioning System (GPS), which includes a null processing receiver embodying the present invention; and 
     FIG. 2 is a simplified block diagram depicting the multiple antenna elements and the null processing receiver circuit of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     With reference now to the drawings, and particularly to FIG. 1, there is shown a simplified block diagram of a portion of a Global Positioning System (GPS) that receives a number of modulated rf signals from an antenna array 11 and detects one or more binary codes originally transmitted from a corresponding number of orbiting satellites. The detected codes are supplied to a GPS navigation processor, which processes the codes to determine the receiver&#39;s precise geographic location. The modulated signals received from the antenna array can sometimes contain interference in the form of a jamming signal. A null processing receiver 13 and tracking and detection circuit 15 suitably processes the modulated signals to substantially eliminate this interference from the codes supplied to the GPS navigation processor. 
     As shown in FIG. 1, the antenna array 11 includes N elements, designated 17a-17n. The modulated antenna signals are supplied on lines 19a-19n to the null processing receiver 13, which demodulates and combines the signals in a prescribed fashion to produce quadrature I and Q data signals. These data signals are supplied on lines 21 and 23, respectively, to the tracking and detection circuit 15, which extracts certain information from the signals and supplies the information to the GPS navigation processor. The tracking and detection circuit, which is of conventional design, also generates various reference signals used by the null processing receiver to properly demodulate the incoming antenna signals. 
     In producing the quadrature I and Q data signals output on lines 21 and 23, the null processing receiver 13 combines the various antenna signals together in such a fashion that a strong interference signal (i.e., a jamming signal) contained in the antenna signals is substantially nulled out. In the past, receivers of this kind achieved this nulling by a complex weighting, i.e., amplitude and phase angle adjustment, of the received antenna signals prior to summation. This has necessarily required the use of controllably adjustable rf circuitry for gain and phase matching, which is usually highly sensitive and difficult to use and adjust. 
     In accordance with the invention, the null processing receiver 13 combines the information contained in the antenna signals received on lines 19a-19n without the need for any complex weighting of the rf signals. Rather, the receiver weights the various signals after demodulation and conversion to digital formats. This greatly simplifies the receiver and significantly reduces its cost, weight and power consumption. 
     More particularly, and with reference to FIG. 2, it will be observed that the null processing receiver 13 receives the N antenna signals on lines 19a-19n from the antenna array 11 and outputs on lines 21 and 23 the respective orthogonal I and Q data signals. In generating these I and Q signals, the receiver removes a spread spectrum pn code and any interference or jamming signal contained in the original antenna signals. The I and Q signals actually are substantially the same as those produced by prior receivers. The receiver of the invention, however, produces them in a substantially simpler and more reliable fashion. 
     The null processing receiver 13 contains both a hardware section and a software section, with a separate, identical hardware channel being provided for each antenna signal. Addressing first the hardware channel for the antenna signal supplied on line 19a from the first antenna element 17a, it will be observed that the signal is initially connected to a mixer 25a. A fixed local oscillator signal is also supplied to the mixer, via line 27 from a reference oscillator 29 (FIG. 1), to down-convert the antenna signal from L-band to approximately 60 MHz. The down-converted or intermediate-frequency (i.f.) signal is supplied on line 31a to a second mixer 33a, where it is multiplied by a locally-generated replica of the modulating pn code. This replica code, which is generated by the tracking and detection circuit 15 (FIG. 1), in a conventional fashion, is supplied to the second mixer on line 35. When the replica code and the incoming pn code are properly synchronized, the second mixer essentially strips the code from the modulated signal, leaving an i.f. carrier signal modulated only by lower data rate position information. Of course, random noise and any jamming signal in the same frequency band are superimposed on the demodulated carrier. The jamming signal can be derived , for example, from a CW jammer, a broadband jammer, a swept-fm jammer, or a pulsed jammer. 
     The demodulated carrier signal is output by the second mixer 33a on line 37a, for connection to both a third mixer 39a and a fourth mixer 41a. These latter two mixers multiply the carrier signal by orthogonal I and Q reference carrier signals supplied on lines 43 and 45, respectively, from the tracking and detection circuit 15 (FIG. 1). These reference signals are properly synchronized with the incoming carrier, tracking any doppler shift that might be present, such that the two mixers provide orthogonal, analog baseband data signals. For this first channel, these two signals are designated I 1  and Q 1 . 
     The respective baseband I 1  and Q 1  signals are supplied on lines 47a and 49a to a pair of low pass filters 5la and 53a and, in turn, on lines 55a and 57a to a pair of analog-to-digital converters 59a and 61a. The filtered and digitized I 1  and Q 1  signals are then output on lines 63a and 65a, respectively, for further processing in the software section of the null processing receiver 13. 
     As previously mentioned, the modulated antenna signals supplied on lines 19a-19n. from the antenna elements 17a-17n are each processed in a separate, identical hardware channel. The channels for the second through nth signals are identical to that for the first signal, described above. The various mixers, low pass filters, analog-to-digital converters, and signal lines in each channel are identified by the same reference numerals as the corresponding elements of the first channel, but followed by letters corresponding to the letter of the antenna signal. 
     The hardware section of the null processing receiver 13 thus produces n pairs of orthogonal, digitized I and Q data signals, designated I 1  -I n  and Q 1  -Q n . These data signals are supplied on lines 63a-63n and 65a-65n, respectively, to the software section of the receiver. 
     It will be appreciated that even with the filtering provided by the low-pass filters 51a-51n and 53a-53n, the digitized I 1  and Q 1  signals will contain significant amounts of noise, especially when a jamming signal is being received. Demodulation of the pn code provides a certain processing gain (about 40 db), but even considering this, the signal-to-noise ratio can still be as low as -20 to -30 db. By weighting the various I n  and Q n  signals and then summing the weighted signals, the software section of the null processing receiver 13 effectively eliminates the jamming signal component from the data and thereby improves the signal-to-noise ratio to about +10 to +20 db. By performing the nulling function after demodulation, the 40 db of processing gain sharply reduces the required dynamic range. 
     The digitized I n  and Q n  signals supplied on lines 63a-63n and 65a-65n, respectively, are further processed in a microprocessor, whose function is depicted schematically in the software section of the block diagram of FIG. 2. The function is depicted using conventional hardware elements, for ease of understanding. Those of ordinary skill in the art will be readily capable of implementing these equivalent hardware functions in a microprocessor. 
     More particularly, it will be observed that the software section of the block diagram of FIG. 2 can be divided into two identical sections. The upper section includes a summer 67 for producing a digital I null  signal in which the jamming signal has been nulled out, and the bottom section includes a summer 69 for producing an orthogonal Q null  signal in which the jamming signal likewise has been nulled out. Basically, each such section sums one digitized data signal derived from the first antenna element 17a with weighted versions of all of the digitized data signals derived from the remaining antenna elements 17b-17n. The former, non-weighted signals (i.e., I 1  and Q 1 ) can be termed primary information signals, and the latter, weighted signals (i.e., I 2  -I n  and Q 2  -Q n ) can be termed auxiliary information signals. 
     The weighted signals supplied to the summer 67 are produced by weighting networks 70 I2  -70 In  and 70 Q2  -72 Qn . Similarly, the weighted signals supplied to the summer 69 are produced by weighting networks 72 I2  -72 In  and 72 Q2  -72 Qn . These networks multiply each of the 2n-2 auxiliary signals by predetermined dc weighting signals, which are generated by correlating the auxiliary signals with the summer output signals, i.e., the I null  signal on line 21 and the Q null  signal on line 23. 
     Thus, the weighting network 70 I2  for the I 2  channel of the upper (i.e., I null ) section includes a mixer 71 I2  for multiplying together the I 2  auxiliary signal supplied on line 63b and the I null  signal supplied on line 21. The resulting product is supplied on line 73 I2  to a negative integrator 75 I2 , which integrates the signal to produce a dc weighting signal output on line 77 I2 . A multiplier 79 I2  multiplies this weighting signal by the I 2  auxiliary signal, to produce the weighted or intermediate signal. The latter is output by the network 70 I2  on line 81 I2  for coupling to the summer 67, which sums it with the I 1  primary signal and the weighted signals for the remaining auxiliary signal channels, to produce the I null  signal. 
     A corresponding mixer, negative integrator and multiplier for each of the remaining weighting networks 70 I3  -70 In  and 70 Q2  -70 Qn  provide corresponding weighted signals for each auxilliary channel. Thus, 2n-2 sets of elements are required to produce the I null  signal. In FIG. 2, only the elements for the I 2 , Q 2  and Q n  channels are shown. 
     The lower (i.e., Q null ) section of the right side of FIG. 2 is identical to the upper (i.e., I null ) section, except that the Q 1  primary signal on line 65a is substituted for the I 1  primary signal on line 63a. Thus, the summer 69 sums together the Q 1  primary signal with prescribed weighted signals for each of the auxiliary channels (i.e., I 2  -I n  and Q 2  -Q n ). In the specific case of the I 2  channel, the weighting network 72 I2  includes a mixer 83 I2  for multiplying together the I 2  auxiliary signal and Q null  signal, supplied on lines 63b and 23, respectively, to produce a product signal. An integrator 85 I2  receives this product signal on line 87 I2  and integrates it to produce a weighting signal that is then supplied on line 89 I2  to a multiplier 91 I2 , which appropriately weights the I 2  signal. The resulting weighted signal is supplied on line 93 I2  to the summer 69. Corresponding elements are provided for all of the auxiliary channels, FIG. 2 depicting only the I 2 , Q 2  and Q n  channels. 
     Operation of the software portion of the null processing receiver 13 will be better understood with reference to a particular example, in which a jamming signal is present in the I 1  and Q 1  primary signals and in all of the I 2  -I n  and Q 2  -Q n  auxiliary signals. If, for example, all n antenna elements 17a-17n are coplanar and the jamming signal is received from a direction normal to that plane and if the cable lengths and phase delays in the various channels all correspond exactly, then all of the I channel signals are equal to each other and all of the Q channel signals are equal to each other. In addition, the I channel signals are all uncorrelated with, i.e., orthogonal to, the Q channel signals. If we assume that the various weighting signals produced by the integrators 75 I2  -75 In  are all initially zero, then all of the weighted signals will likewise be zero and the I null  signal will be identical to the I 1  signal. Since the I null  and I 2  signals will then both contain the jamming signal, the product signal output by the mixer 71 I2  will be positive and the negative integrator 75 I2  will begin ramping negatively. The multiplier 79 I2  therefore produces a weighted signal that is the inverse of the I 2  auxiliary signal, progressively increasing in amplitude. The same progression occurs in the remaining I.sub. n channels, because the jamming signal is similarly present in the auxiliary signals for those channels. The weighted signals for the Q 2  -Q n  channels will remain at zero, because the auxiliary signals for these channels are uncorrelated with the I null  signal. 
     Eventually, contributions of the weighted signals will cancel out the jamming signal component of the I 1  primary signal such that it is completely eliminated from the I null  signal. When this occurs, the I null  signal will be uncorrelated with all of the auxiliary signals and the various mixers 71 I2  -71 In  will all produce product signals that are essentially zero. The weighting signals produced by the corresponding negative integrators 75 I2  -75 In  will therefore remain fixed at their current levels. 
     The same process is followed in the Q null  section of the null processing receiver 13. That is, the weighting of the auxiliary signals is controllably adjusted until the Q null  section is uncorrelated with each of the I 2  -I n  and Q 2  -Q n  auxiliary signals. 
     It should be noted that if the respective phase angles of the local oscillator signal or I and Q reference signals applied to the various channels are different (due to cable length variations, etc.), then the resulting magnitudes of the jamming signal components of the I 1  -I n  and Q 1  -Q n  signals also will be different. This has no effect on the receiver&#39;s performance, however, because the feedback control provided by the software implemented in the microprocessor will automatically correct for this. In addition, weighting could be provided for the I 1  and Q 1  signals, as well, with no real effect on the receiver&#39;s performance. 
     The separate elements 17a-17n of the antenna array 11 are arranged with respect to each other such that they provide a predetermined spatial gain, with a known pattern of lobes and nulls. That is, the antenna array&#39;s gain varies as a function of direction, with a substantially reduced gain occurring in particular directions. The weighting process performed by the microprocessor actually adjusts the antenna null pattern to align a given null or low-gain direction with the detected source of a jamming signal. 
     The receiver apparatus automatically nulls out a plurality of independent jamming signals. In particular, for an apparatus used with N antenna elements, up to N-1 separate jamming signals can be nulled out. The N-1 spatial nulls are all independently steerable, to track any relative movement of the sources of the jamming signals. 
     In situations where the direction to the source of the jamming signal continuously varies, the weighting of the various signals must vary correspondingly. The microprocessor must update the correlation between the I null  and Q null  signals and the various auxiliary information signals at a rate sufficiently fast to enable tracking of the jamming source direction. 
     As previously mentioned, the null processing receiver 13 operates to null out the strongest signal received within the frequency band of interest. This operating mode is desirable, because when a jamming signal is present it is ordinarily many times stronger than the satellite signal to be detected. When a jamming signal is not present, however, care must be taken to ensure that the receiver does not null out the desired satellite signal. 
     Preventing the nulling of the desired satellite signal is required only when the signal-to-noise ratio exceeds 0 db and no higher powered jamming signal is present. This can effectively be ensured by periodically substituting a non-replica of the incoming pn code, i.e., a bogey code, for the replica code ordinarily supplied to the receiver 13 on line 35. Each hardware channel therefore will be unable to properly demodulate the incoming signal and there is no risk that the receiver will inadvertently null it out. This periodic substitution of a non-replica code is preferably performed at a duty cycle of, for example, 50 percent. During alternate intervals, when the pn code replica is being supplied, the I null  and Q null  signals output by the receiver 13 on lines 21 and 23, respectively, will contain the desired satellite data. 
     The microprocessor whose function is represented by the hardware-equivalent elements depicted on the right side of FIG. 2 inherently implements a least mean-square error algorithm. This algorithm minimizes the power level of the I null  and Q null  signals. It will be appreciated that alternative schemes for weighting the various auxiliary signals can also be utilized. In addition, it will be appreciated that low-pass 
     filters can be substituted for the integrators 75 I2  -75 Qn  and 85 I2  -85 Qn , without a significant effect on performance, and that a dithering process can be substituted for the correlation process performed by the mixers 71 I2  -71 Qn  and 83 I2  -83 Qn . 
     As an alternative to the multiple feedback loops present in the software section of FIG. 2, the I null  and Q null  signals could be produced using computational techniques such as direct matrix inversion. Such techniques could minimize output power, and thus null out any jamming signals, simply by appropriately correlating the various auxiliary information signals. 
     It should be appreciated from the foregoing description that the present invention provides an improved null processing receiver apparatus that effectively nulls out an rf interference signal without the need for any complex weighting of rf signals. A plurality of L-band antenna signals are down converted, demodulated to baseband, and converted to corresponding digital signals in separate channels. The digital signals are then appropriately weighted and summed in such a fashion as to minimize output power and, thereby, null out any undesired interference signal. 
     Although the present invention has been described in detail with reference to the presently preferred embodiment, those of ordinary skill in the art will appreciate that various modifications can be made without departing from the invention. Accordingly, the invention is defined only by the following claims.