Patent Publication Number: US-2022230590-A1

Title: Pixel circuit, shift register unit, gate driving circuit and display device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. Non-Provisional patent application Ser. No. 16/927,789, entitled “PIXEL CIRCUIT, SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DISPLAY DEVICE”, filed Jul. 13, 2020, which claims priority to Chinese Patent Application No. 201911189210.9 filed on Nov. 28, 2019. The entire contents of the above-listed applications are hereby incorporated by reference for all purposes. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a shift register unit, a gate driving circuit and a display device. 
     BACKGROUND 
     Organic light-emitting diodes (OLEDs) have risen rapidly in recent years. Organic electroluminescence technology is considered as the most potential lighting and display technology to replace liquid crystal displays since it has the advantages of self-luminous characteristics, large screen visibility angle, high brightness, fast response, low driving voltage, and capability to resist shocks, and can work normally in a low temperature environment. In addition, the OLED can emit light autonomously, and its pixel circuit plays a vital role. Due to its process limitations and defects in the pixel circuit itself, bad light spots may occur. Generally, a T-aging (transistor aging) method is used to reduce current leakage of a TFT (thin film transistor). However, aging cannot solve the leakage problem of all TFTs. When an aging voltage or current is too high, it may cause the tunneling of the transistor in a GOA (Gate On Array) region or in the pixel region. 
     SUMMARY 
     In a first aspect, embodiments of the present disclosure provide a shift register unit, which is configured to generate a first gate drive signal and a second gate drive signal. The shift register unit includes: a first control circuit, configured to control a potential of a first node, a second control circuit, configured to control a potential of a second node, a first output circuit, configured to generate the first gate drive signal based on a first voltage signal provided by a first voltage terminal under the control of the potentials of the first and second nodes, and output the first gate drive signal through a first gate drive signal output terminal, wherein the first voltage signal provided by the first voltage terminal is a high level signal, and a second output circuit, configured to generate a second gate drive signal based on a second voltage signal provided by a second voltage terminal under the control of a potential of a control node, and output the second gate drive signal through a second gate drive signal output terminal. The first output circuit includes: a first output transistor, including a control electrode electrically connected to the first node, a first electrode electrically connected to the first voltage terminal, and a second electrode electrically connected to the first gate drive signal output terminal, a first output pull-down transistor, including a control electrode electrically connected to the control node, a first electrode electrically connected to the first gate drive signal output terminal, and a second electrode electrically connected to a first clock signal terminal, and an output pull-down capacitor, including a first terminal electrically connected to the second node, and a second terminal electrically connected to the first gate drive signal output terminal . Specifically, the second output circuit further includes a second output pull-down transistor having its gate electrode electrically connected to the control node; and the first voltage terminal and the second voltage terminal are provided with substantially different potential values. 
     In a second aspect, embodiments of the present disclosure further provide a gate driving circuit, including multiple stages of the shift register units as described in the first aspect. 
     In a third aspect, embodiments of the present disclosure further provide a pixel circuit, applied to the shift register unit as described in the first aspect. 
     In a fourth aspect, embodiments of the present disclosure further provide a display device as described in the third aspect. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to illustrate the technical solutions of the embodiments of the present disclosure more apparently, the accompanying drawings required in the description of the embodiments of the present disclosure will be briefly introduced below. It is evident that the drawings in the following description relate to only some embodiments of the present disclosure, and based on these drawings, the other drawings can be obtained by those of ordinary skill in the art without exercising any inventive work. 
         FIG. 1  shows a structural diagram of a pixel circuit according to an embodiment of the present disclosure; 
         FIG. 2  shows a structural diagram of a pixel circuit according to another embodiment of the present disclosure; 
         FIG. 3  shows a circuit diagram of a specific embodiment of the pixel circuit according to the present disclosure; 
         FIG. 4A  shows a schematic diagram of part of a layout of a gate metal layer; 
         FIG. 4B  shows a schematic diagram of part of a layout of an active layer; 
         FIG. 4C  shows a schematic diagram of the superposition of the gate metal layer shown in  FIG. 4A  and the active layer shown in  FIG. 4B ; 
         FIG. 5  shows a structural diagram of a shift register unit according to an embodiment of the present disclosure; 
         FIG. 6  shows a circuit diagram of a specific embodiment of a shift register unit according to the present disclosure; and 
         FIG. 7  shows waveform diagrams of first and second gate drive signals outputted in accordance with the specific embodiment of the shift register unit according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The technical solutions of the embodiments of the present disclosure will be clearly and completely described hereinafter with reference to the accompanying drawings for the embodiments of the present disclosure. Obviously, the described embodiments are a part, rather than all, of the embodiments of the present disclosure. All the other embodiments, obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without exercising any inventive work, shall fall within the protection scope of the present disclosure. 
     Transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors (TFTs), field-effect transistors, or other devices having identical characteristics. In the embodiment of the present disclosure, in order to distinguish two electrodes of the transistor other than a control electrode from each other, one of them is referred to as a first electrode, and the other as a second electrode. 
     In an actual operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; or, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second pole may be a collector electrode. 
     In an actual operation, when the transistor is a thin film transistor or a field-effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode. 
     As shown in  FIG. 1 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element EL, a driving circuit  11 , a data writing circuit  12 , and a compensation control circuit  13 . The driving circuit  11  is configured to drive the light-emitting element EL to emit light. The compensation control circuit  13  is electrically connected to a first gate line Gate  1 , a control electrode of the driving circuit  11  and a second terminal of the driving circuit  11  for controlling the control terminal of the driving circuit  11  to be connected with the second terminal of the driving circuit  11  under the control of a first gate drive signal provided by the first gate line Gatel. 
     The data writing circuit  12  is electrically connected to a second gate line Gate 2 , a data line, and a first terminal of the driving circuit  11  for controlling a data voltage Vdata to be provided to the first terminal of the driving circuit  11  under the control of a second gate drive signal provided by the second gate line Gate 2 . The data line is configured to provide the data voltage Vdata. 
     In  FIG. 1 , a first control node N 1  is a node coupled to the control terminal of the driving circuit  11 . 
     In the pixel circuit described in the embodiment of the present disclosure, the data writing circuit  12  is controlled by the second gate drive signal provided by the second gate line Gate 2 , and the compensation control circuit  13  is controlled by the first gate drive signal provided by the first gate line Gate 1 . The pixel circuit described in the embodiment of the present disclosure controls a data writing transistor included in the data writing circuit  12  and a compensation control transistor included in the compensation control circuit  13  through different gate drive signals, and can thus effectively reduce current leakage occurring when the pixel circuit emits light, thereby reducing a number of weak light spots generated when the display screen emits light and decreasing the occurance of the weak light spots. 
     In the pixel circuit described in the embodiment of the present disclosure, when the first and second gate drive signals are inactive, a voltage value of the first gate drive signal is different from a voltage value of the second gate drive signal. 
     In the embodiment of the present disclosure, the second gate drive signal being inactive means that a potential of the second gate drive signal is at an inactive level, so that the data writing transistor can be controlled to be turned off, that is, so that the data writing circuit  12  can control the data line to be disconnected from the first terminal of the driving circuit  11 . 
     In the embodiment of the present disclosure, the first gate drive signal being inactive means that a potential of the first gate drive signal is at an inactive level, so that the compensation control transistor can be controlled to be turned off, that is, so that the compensation control circuit  13  can control the control terminal of the driving circuit  11  to be disconnected from the second terminal of the driving circuit  11 . 
     For example, when the data writing transistor and the compensation control transistor are P-type transistors, the inactive level is a high level. For another example, when the data writing transistor and the compensation control transistor are N-type transistors, the inactive level is a low level. 
     In the related art, when the pixel circuit has its own defects due to the process limitations, bad light spots may occur. Aging of TFTs cannot solve the leakage problem of all transistors. When an aging voltage or current is too high, it may cause the tunneling of the transistor in a GOA (Gate On Array) region or in the pixel region. In the related  7 T 1 C pixel circuit, when the pixel circuit operates in a compensation phase, a data voltage is 6 volts, and a voltage written to the control terminal of the driving circuit  11  is Vdata+Vth, where Vth is a threshold voltage of a driving transistor included in the driving circuit  11 . When the driving transistor is a P-type transistor, Vth may be about −2.5 volts, and the voltage written to the control terminal of the driving circuit  11  may be then about 3.5 volts. Thus, according to transfer characteristic curves of the compensation control transistor and the data writing transistor, if a gate-source voltage of the transistor is about 3 V, a leakage current of the transistor is high. Therefore, when the pixel circuit is in a light-emitting phase, N 1  generates a higher leakage current through the compensation control transistor, resulting in bad light spots. 
     In the pixel circuit described in the embodiment of the present disclosure, if the compensation control transistor is a P-type transistor, when the potential of the first gate drive signal is at a high level, the potential of the first gate drive signal can be changed from 7 volts to 5 volts, but it is not limited thereto. When the pixel circuit described in the embodiment of the present disclosure works in the compensation phase, the data voltage is 6 V, and the voltage written to the control terminal of the driving circuit  11  is Vdata+Vth, where Vth is the threshold voltage of the driving transistor included in the driving circuit  11 . When the driving transistor is a P-type transistor, Vth may be about −2.5 V, and the voltage written to the control terminal of the driving circuit  11  may be then about 3.5 volts. When the pixel circuit described in the embodiment of the present disclosure is in the light-emitting phase, the gate-source voltage Vgs of the compensation control transistor is about 1.5 V. At this time, the leakage current of the compensation control transistor is low, which can effectively reduce the bad light spots generated at the time of light emission. 
     In the pixel circuit described in the embodiment of the present disclosure, if the data writing transistor is a P-type transistor, when a potential of the second gate drive signal is at a high level, the potential of the second gate drive signal may be set to 7 volts, but it is not limited thereto. At this time, the potential of the second gate drive signal needs to be maintained at 7 volts for the following reasons: since the data voltage is inputted into the first electrode of the data writing transistor, if the data voltage is 6 volts and the potential of the second gate drive signal is 5 volts, there is a risk that the data writing transistor will be turned on, resulting in poor display. 
     In the embodiments of the present disclosure, the description is made by taking each of the transistors as a P-type transistor for example, but in actual operations, each of the transistors may be an N-type transistor. For example, if the compensation control transistor is an N-type transistor, when the potentials of the first and second gate drive signals are at low levels, an absolute value of the potential of the first gate drive signal may be smaller than that of the potential of the second gate drive signal, but it is not limited thereto. 
     Specifically, the compensation control circuit may include a compensation control transistor. 
     A control electrode of the compensation control transistor is electrically connected to the first gate line, a first electrode of the compensation control transistor is electrically connected to the control terminal of the driving circuit, and a second electrode of the compensation control transistor is electrically connected to the second terminal of the driving circuit. 
     Specifically, the data writing circuit may include a data writing transistor. 
     A control electrode of the data writing transistor is electrically connected to the second gate line, a first electrode of the data writing transistor is electrically connected to a data line, and a second electrode of the data writing transistor is electrically connected to a first terminal of the driving circuit. The data line is configured to provide the data voltage. 
     In a specific implementation, the driving circuit may include a driving transistor. 
     A control electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit. 
     In an embodiment of the present disclosure, the pixel circuit described in the present disclosure further includes a storage capacitor, a first light emission control circuit, a second light emission control circuit, and a reset circuit. 
     A first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to a power supply voltage terminal. 
     The first light emission control circuit is electrically connected to a light emission control line, the power supply voltage terminal, and the first terminal of the driving circuit, and configured to control the power supply voltage terminal to be connected with the first terminal of the driving circuit under the control of a light emission control signal provided by the light emission control line. 
     The second light emission control circuit is electrically connected to the light emission control line, is electrically connected between the second terminal of the driving circuit and a first electrode of the light-emitting element, and is configured to control the second terminal of the driving circuit to be connected with the first electrode of the light-emitting element under the control of a light emission control signal provided by the light emission control line. 
     The reset circuit is configured to control an initial voltage to be written to the control terminal of the driving circuit and the first electrode of the light-emitting element under the control of a reset control signal provided by a reset control terminal. Moreover, a cathode voltage is inputted into a second electrode of the light-emitting element. 
     As shown in  FIG. 2 , the pixel circuit described in the embodiment of the present disclosure further includes a storage capacitor Cst, a first light emission control circuit  141 , a second light emission control circuit  142  and a reset circuit  15  on the basis of the embodiment of the pixel circuit shown in  FIG. 1 . 
     A first terminal of the storage capacitor Cst is electrically connected to the control terminal of the driving circuit  11 , and a second terminal of the storage capacitor Cst is electrically connected to a power supply voltage terminal ELVDD. 
     The first light emission control circuit  141  is electrically connected to a light emission control line EM, the power supply voltage terminal ELVDD, and the first terminal of the driving circuit  11 , and is configured to control the power supply voltage terminal ELVDD to be connected with the first terminal of the driving circuit  11  under the control of a light emission control signal provided by the light emission control line EM. 
     The second light emission control circuit  142  is electrically connected to the light emission control line EM, is electrically connected between the second terminal of the driving circuit  11  and the light-emitting element EL, and is configured to control the second terminal of the driving circuit  11  to be connected with a first electrode of the light-emitting element EL under the control of a light emission control signal provided by the light emission control line EM. 
     The reset circuit  15  is configured to control an initial voltage Vint to be written to the control terminal of the driving circuit  11  and the first electrode of the light-emitting element EL under the control of a reset control signal provided by a reset control terminal Reset. 
     A cathode voltage ELVSS is inputted into a second electrode of the light-emitting element EL. 
     In the embodiment of the pixel circuit shown in  FIG. 2 , the cathode voltage is a low voltage ELVSS, but it is not limited thereto. 
     When the embodiment of the pixel circuit shown in  FIG. 2  of the present disclosure is in operation, the reset circuit  15  is used to reset a potential of a first control node N 1  and a potential of the first electrode of the light-emitting element EL, the light emission control circuit  14  (the first light emission control circuit  141  and the second light-emission control circuit  142 ) is used to perform light emission control based on the light emission control signal, and the storage capacitor Cst is used to maintain the potential of the first control node N 1 . 
     In a specific implementation, the first light emission control circuit may include a first light emission control transistor, the second light emission control circuit may include a second light emission control transistor, and the reset circuit may include a first reset transistor and a second reset transistor. 
     A control electrode of the first light emission control transistor is electrically connected to the light emission control line, a first electrode of the first light emission control transistor is electrically connected to the power supply voltage terminal, and a second electrode of the first light emission control transistor is electrically connected to the first terminal of the driving circuit. 
     A control electrode of the second light emission control transistor is electrically connected to the light emission control line, a first electrode of the second light emission control transistor is electrically connected to the second terminal of the driving circuit, and a second electrode of the second light emission control transistor is electrically connected to the first electrode of the light-emitting element. 
     A control electrode of the first reset transistor is electrically connected to the reset control terminal, the initial voltage is inputted into a first electrode of the first reset transistor, and a second electrode of the first reset transistor is electrically connected to the control terminal of the driving circuit. 
     A control electrode of the second reset transistor is electrically connected to the reset control terminal, the initial voltage is inputted into a first electrode of the second reset transistor, and a second electrode of the second reset transistor is electrically connected to the first electrode of the light-emitting element. 
     In the embodiment of the present disclosure, the light-emitting element may be an organic light-emitting diode, the first electrode of the light-emitting element is an anode of the organic light-emitting diode, and the second electrode of the light-emitting element is a cathode of the organic light-emitting diode, but the present disclosure is not limited thereto. 
     In the embodiment of the present disclosure, when the light-emitting element is an organic light-emitting diode, the anode of the organic light-emitting diode is electrically connected to the light emission control circuit, and a low voltage is inputted into the cathode of the organic light-emitting diode, but the present disclosure is not limited thereto. 
     As shown in  FIG. 3 , a specific embodiment of the pixel circuit described in the present disclosure includes an organic light-emitting diode OLED, a driving circuit, a data writing circuit, a compensation control circuit, a storage capacitor Cst, a first light emission control circuit, a second light emission control circuit and a reset circuit. 
     The compensation control circuit includes a compensation control transistor T 2 . The driving circuit includes a driving transistor T 3 . The data writing circuit includes a data writing transistor T 4 . 
     A gate electrode of the compensation control transistor T 2  is electrically connected to the first gate line Gatel, a source electrode of the compensation control transistor T 2  is electrically connected to a gate electrode of the driving transistor T 3 , and a drain electrode of the compensation control transistor T 2  is electrically connected to a drain electrode of the driving transistor T 3 . 
     A gate electrode of the data writing transistor T 4  is electrically connected to the second gate line Gate 2 , a source electrode of the data writing transistor T 4  is electrically connected to a data line Data, and a drain electrode of the data writing transistor T 4  is electrically connected to a source electrode of the driving transistor T 3 . The data line Data is used to provide the data voltage. 
     A first terminal of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T 3 , and a second terminal of the storage capacitor Cst is electrically connected to a power supply voltage terminal ELVDD. 
     The first emission control circuit includes a first emission control transistor T 5 , the second emission control circuit includes a second emission control transistor T 6 , and the reset circuit includes a first reset transistor Ti and a second reset transistor T 7 . 
     A gate electrode of the first light emission control transistor T 5  is electrically connected to the light emission control line EM, a source electrode of the first light emission control transistor T 5  is electrically connected to the power supply voltage terminal ELVDD, and a drain electrode of the first light emission control transistor T 5  is electrically connected to the source electrode of the driving transistor T 3 . 
     A gate electrode of the second light emission control transistor T 6  is electrically connected to the light emission control line EM, a source electrode of the second light emission control transistor T 6  is electrically connected to the drain electrode of the driving transistor T 3 , and a drain electrode of the second light emission control transistor T 6  is electrically connected to the anode of the organic light-emitting diode OLED. 
     A gate electrode of the first reset transistor Ti is electrically connected to the reset control terminal Reset, the initial voltage Vint is inputted into a source electrode of the first reset transistor Ti, and a drain electrode of the first reset transistor Ti is electrically connected the gate electrode of the driving transistor T 3 . 
     A gate electrode of the second reset transistor T 7  is electrically connected to the reset control terminal Reset, the initial voltage Vint is inputted into a source electrode of the second reset transistor T 7 , and a drain electrode of the second reset transistor T 7  is electrically connected to the anode of the organic light-emitting diode OLED. 
     A low voltage ELVSS is inputted into the cathode of the organic light-emitting diode OLED. 
     In the specific embodiment of the pixel circuit shown in  FIG. 3 , the first control node N 1  is a node electrically connected to the gate electrode of T 3 . 
     In the specific embodiment of the pixel circuit shown in  FIG. 3 , all the transistors are P-type thin film transistors, but the present disclosure is not limited thereto. In an actual operation, the above transistors may be N-type transistors. 
     When the specific embodiment of the pixel circuit shown in  FIG. 3  of the present disclosure is in operation, a display period may include a reset phase, a compensation phase, and a light-emitting phase that are sequentially arranged. 
     In the reset phase, a reset control signal input by the reset control terminal Reset controls T 1  and T 7  to be turned on, and all of T 2 , T 3 , T 4 , T 5 , and T 6  to be turned off to write the initial voltage Vint to the first control node N 1  and the anode of the OLED, so that T 3  is turned off and the OLED does not emit light. 
     In the compensation phase, T 1 , T 7 , T 5  and T 6  are turned off, a first gate drive signal provided by the first gate line Gate 1  controls T 2  to be turned on, a second gate drive signal provided by the second gate line Gate 2  controls T 4  to be turned on, and the data line Data writes a voltage signal of 6 volts to the source electrode of T 3  such that T 3  is turned on to charge the storage capacitor Cst, thereby changing the potential of the first control node N 1  until T 3  is turned off If a threshold voltage of T 3  is −2.5 volts, then the potential of the first control node N 1  becomes 3.5 volts. 
     In the light-emitting phase, T 1 , T 7 , T 2 , and T 4  are turned off, a light emission control signal provided by the light emission control line EM controls T 5  and T 6  to be turned on, and T 3  to be turned on, so as to drive the OLED to emit light; at this time, T 2  is turned off, and the potential of the first gate drive signal provided by the first gate line Gatel is 5 volts, so that the gate-source voltage of T 2  is about 1.5 volts, and the leakage current of T 2  can be thus reduced; and the potential of the second gate drive signal provided by the second gate line Gate 2  is maintained at 7 volts to control T 4  not to be turned on by mistake. 
     In the light-emitting phase, if T 4  is turned on by mistake, the data voltage will be written to the power supply voltage terminal ELVDD, resulting in abnormal data writing in the pixel circuits of other rows. 
     In the embodiment of the present disclosure, the first gate line, the second gate line and the gate electrode of each transistor included in the pixel circuit may be made of a gate metal layer, a layout of which may be as shown in  FIG. 4A . As can be seen from  FIG. 4A , a gate electrode T 2   g  of T 2  is electrically connected to the first gate line Gatel, and a gate electrode T 4   g  of T 4  is electrically connected to the second gate line Gate 2 . 
     In  FIG. 4A , reference sign T 1   g  represents the gate electrode of T 1 , reference sign T 3   g  represents the electrode gate of T 3 , reference sign T 5   g  represents the gate electrode of T 5 , reference sign T 6   g  represents the gate electrode of T 6 , and reference sign T 7   g  represents the gate electrode of T 7 . 
       FIG. 4B  shows a schematic diagram of part of a layout of an active layer. In  FIG. 4B , reference numeral  40  represents a Chinese character ‘ ’ shaped channel (i.e., a channel with a convex shape in the middle). In an actual operation, an orthogonal projection of the character ‘ ’ shaped channel  40  on a display substrate may overlap with an orthogonal projection of the gate electrode T 3   g  on the display substrate, but the present disclosure is not limited thereto. 
       FIG. 4C  shows a schematic diagram of the superposition of the gate metal layer shown in  FIG. 4A  and the active layer shown in  FIG. 4B . 
     In a specific implementation, the display substrate may be an array substrate, but it is not limited thereto. 
     In addition, the shift register unit described in the embodiment of the present disclosure is applied to the pixel circuit described in the foregoing embodiment of the present disclosure to generate a first gate drive signal and a second gate drive signal. The shift register unit includes a first control circuit, a second control circuit, a first output circuit and a second output circuit. 
     The first control circuit is configured to control a potential of a first node. The second control circuit is configured to control a potential of a second node. The first output circuit is configured to generate a first gate drive signal based on a first voltage signal provided by a first voltage terminal under the control of the potentials of the first and second nodes, and output the first gate drive signal through a first gate drive signal output terminal. The second output circuit is configured to generate a second gate drive signal based on a second voltage signal provided by a second voltage terminal under the control of the potentials of the first and second nodes, and output the second gate drive signal through a second gate drive signal output terminal. 
     The shift register unit described in the embodiment of the present disclosure is used to provide the first gate drive signal and the second gate drive signal for the pixel circuit described in the embodiment of the present disclosure. 
     In the shift register unit described in the embodiment of the present disclosure, a voltage value of the first voltage signal provided by the first voltage terminal is different from a voltage value of the second voltage signal provided by the second voltage terminal, so that when the first and second gate drive signals are inactive, the potential of the first gate drive signal is different from the potential of the second gate drive signal. 
     In addition, in the shift register unit described in the embodiment of the present disclosure, the first output circuit may be further electrically connected to a first clock signal terminal, and the second output circuit may be also electrically connected to the first clock signal terminal. 
     When the shift register unit described in the embodiment of the present disclosure is in operation, in the compensation phase, the first output circuit controls the first gate drive signal output terminal to output a first clock signal, and the second output circuit controls the second gate drive signal output terminal to output the first clock signal; and in the light-emitting phase, the first output circuit controls the first gate drive signal output terminal to output a first voltage signal, and the second output circuit controls the second gate drive signal output terminal to output a second voltage signal. 
     In the embodiment of the present disclosure, a voltage value of the first voltage signal may be, for example, 5 volts, and a voltage value of the second voltage signal may be, for example, 7 volts, but the present disclosure is not limited thereto. 
     As shown in  FIG. 5 , the shift register unit described in the embodiment of the present disclosure is applied to the pixel circuit described in the embodiment of the present disclosure, and is used to generate a first gate drive signal and a second gate drive signal. The shift register unit may include a first control circuit  51 , a second control circuit  52 , a first output circuit  53 , and a second output circuit  54 . 
     The first control circuit  51  is electrically connected to the first node P 1  for controlling the potential of the first node P 1 . 
     The second control circuit  52  is electrically connected to the second node P 2  for controlling the potential of the second node P 2 . 
     The first output circuit  53  is electrically connected to the first node P 1 , the second node P 2 , the first voltage terminal Vt 1 , the first clock signal terminal CB, and the first gate drive signal output terminal G 1 , and is configured to generate a first gate drive signal based on a first voltage signal provided by the first voltage terminal Vt 1  and a first clock signal provided by the first clock signal terminal CB under the control of the potentials of the first and second nodes P 1  and P 2 , and output the first gate drive signal through the first gate drive signal output terminal Gl. 
     The second output circuit  54  is electrically connected to the first node P 1 , the second node P 2 , the second voltage terminal Vt 2 , the first clock signal terminal CB, and the second gate drive signal output terminal G 2 , and is configured to generate a second gate drive signal based on a second voltage signal provided by the second voltage terminal Vt 2  and the first clock signal provided by the first clock signal terminal CB under the control of the potentials of the first and second nodes P 1  and P 2 , and output the second gate drive signal through the second gate drive signal output terminal G 2 . 
     In the embodiment of the present disclosure, the first voltage signal provided by the first voltage terminal Vt 1  may be a first high voltage, and the second voltage signal provided by the second voltage terminal Vt 2  may be a second high voltage, but the present disclosure is not limited thereto. 
     Furthermore, in the embodiment of the present disclosure, in the compensation phase, the first clock signal provided by the first clock signal terminal CB may be at a low-level VGL, but the present disclosure is not limited thereto. 
     Specifically, the first output circuit may include a first output transistor, a first output pull-down transistor, a first output capacitor, and an output pull-down capacitor. 
     A control electrode of the first output transistor is electrically connected to the first node, a first electrode of the first output transistor is electrically connected to the first voltage terminal, and a second electrode of the first output transistor is electrically connected to the first gate drive signal output terminal. 
     A control electrode of the first output pull-down transistor is electrically connected to the second pull-down node, a first electrode of the first output pull-down transistor is electrically connected to the first gate drive signal output terminal, and a second electrode of the first output pull-down transistor is electrically connected to a first clock signal terminal. 
     A first terminal of the first output capacitor is electrically connected to the first node, and a second terminal of the first output capacitor is electrically connected to the first electrode of the first output transistor. 
     A first terminal of the output pull-down capacitor is electrically connected to the second node, and a second terminal of the output pull-down capacitor is electrically connected to the first gate drive signal output terminal. 
     Specifically, the second output circuit may include a second output transistor, a second output pull-down transistor, and a second output capacitor. 
     A control electrode of the second output transistor is electrically connected to the first node, a first electrode of the second output transistor is electrically connected to the second voltage terminal, and a second electrode of the second output transistor is electrically connected to the second gate drive signal output terminal. 
     A control electrode of the second output pull-down transistor is electrically connected to the second node, a first electrode of the second output pull-down transistor is electrically connected to the second gate drive signal output terminal, and a second electrode of the second output pull-down transistor is electrically connected to the first gate drive signal output terminal. 
     A first terminal of the second output capacitor is electrically connected to the first node, and a second terminal of the second output capacitor is electrically connected to the first electrode of the second output transistor. 
     Specifically, the first control circuit may include a first control transistor and a second control transistor, and the second control circuit may include a third control transistor, a fourth control transistor, a fifth control transistor, and a sixth control transistor. 
     A control electrode of the first control transistor is electrically connected to a second clock signal terminal, a low level is inputted into a first electrode of the first control transistor, and a second electrode of the first control transistor is electrically connected to the first node. 
     A control electrode of the second control transistor is electrically connected to a second electrode of the third control transistor, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the second clock signal terminal. 
     A control electrode of the third control transistor is electrically connected to the second clock signal terminal, and a starting voltage is inputted into a first electrode of the third control transistor. 
     A control electrode of the fourth control transistor is electrically connected to the first node, and a high level is inputted into a first electrode of the fourth control transistor. 
     A control electrode of the fifth control transistor is electrically connected to the first clock signal terminal, a first electrode of the fifth control transistor is electrically connected to a second electrode of the fourth control transistor, and a second electrode of the fifth control transistor is electrically connected to the second electrode of the third control transistor. 
     A low level is inputted into a control electrode of the sixth control transistor, a first electrode of the sixth control transistor is electrically connected to the second electrode of the third control transistor, and a second electrode of the sixth control transistor is electrically connected to the second node. 
     The shift register unit described in the present disclosure will be explained below through a specific embodiment. 
     As shown in  FIG. 6 , a specific embodiment of the shift register unit described in the present disclosure is applied to the pixel circuit described in the embodiment of the present disclosure, and is configured to generate a first gate drive signal and a second gate drive signal. The shift register unit may include a first control circuit, a second control circuit, a first output circuit, and a second output circuit. 
     The first control circuit includes a first control transistor M 3  and a second control transistor M 2 . The second control circuit includes a third control transistor M 1 , a fourth control transistor M 6 , a fifth control transistor M 7 , and a sixth control transistor M 8 . 
     A gate electrode of the first control transistor M 3  is electrically connected to a second clock signal terminal CK, a low level VGL is inputted into a source electrode of the first control transistor M 3 , and a drain electrode of the first control transistor M 3  is electrically connected to a first Node P 1 . 
     A gate electrode of the second control transistor M 2  is electrically connected to a drain electrode of the third control transistor M 1 , a source electrode of the second control transistor M 2  is electrically connected to the first node P 1 , and a drain electrode of the second control transistor M 2  is electrically connected to the second clock signal terminal CK. 
     A gate electrode of the third control transistor M 1  is electrically connected to the second clock signal terminal CK, and a starting voltage STV is inputted into a source electrode of the third control transistor Ml. 
     A gate electrode of the fourth control transistor M 6  is electrically connected to the first node P 1 , and a high level VGH is inputted into a source electrode of the fourth control transistor M 6 . 
     A gate electrode of the fifth control transistor M 7  is electrically connected to the first clock signal terminal CB, a source electrode of the fifth control transistor M 7  is electrically connected to a drain electrode of the fourth control transistor M 6 , and a drain electrode of the fifth control transistor M 7  is electrically connected to the drain electrode of the third control transistor M 1 . 
     A low level VGL is inputted into a gate electrode of the sixth control transistor M 8 , a source electrode of the sixth control transistor M 8  is electrically connected to the drain electrode of the third control transistor M 1 , and a drain electrode of the sixth control transistor M 8  is electrically connected to the second node P 2 . 
     The first output circuit includes a first output transistor M 4 , a first output pull-down transistor M 5 , a first output capacitor C 1 , and an output pull-down capacitor C 2 . 
     A gate electrode of the first output transistor M 4  is electrically connected to the first node P 1 , a first high voltage VGH 1  is inputted into a source electrode of the first output transistor M 4 , and a drain electrode of the first output transistor M 4  is electrically connected to the first gate drive signal output terminal Gl. 
     A gate electrode of the first output pull-down transistor M 5  is electrically connected to the second node P 2 , a source electrode of the first output pull-down transistor M 5  is electrically connected to the first gate drive signal output terminal Gl, and a drain electrode of the first output pull-down transistor M 5  is electrically connected to the first clock signal terminal CB. 
     A first terminal of the first output capacitor C 1  is electrically connected to the first node P 1 , and a second terminal of the first output capacitor C 1  is electrically connected to the source electrode of the first output transistor M 4 . 
     A first terminal of the output pull-down capacitor C 2  is electrically connected to the second node P 2 , and a second terminal of the output pull-down capacitor C 2  is electrically connected to the first gate drive signal output terminal Gl. 
     The second output circuit includes a second output transistor M 9 , a second output pull-down transistor M 10 , and a second output capacitor C 3 . 
     A gate electrode of the second output transistor M 9  is electrically connected to the first node P 1 , a second high voltage VGH 2  is inputted into a source electrode of the second output transistor M 9 , and a drain electrode of the second output transistor M 9  is electrically connected to the second gate drive signal output terminal G 2 . 
     A gate electrode of the second output pull-down transistor M 10  is electrically connected to the second node P 2 , a source electrode of the second output pull-down transistor M 10  is electrically connected to the second gate drive signal output terminal G 2 , and a drain electrode of the second output pull-down transistor M 10  is electrically connected to the first gate drive signal output terminal G 1 . 
     A first terminal of the second output capacitor C 3  is electrically connected to the first node P 1 , and a second terminal of the second output capacitor C 3  is electrically connected to the source electrode of the second output transistor M 9 . 
     Here, VGH, VGH 1  and VGH 2  are different from each other. Moreover, as shown in  FIG. 7 , an absolute value of VGH 1  is smaller than that of VGH 2 . 
     In the specific embodiment of the shift register unit shown in  FIG. 6  of the present disclosure, all the transistors are P-type thin film transistors, but the present disclosure is not limited thereto. In an actual operation, the above transistors can be replaced by N-type transistors. 
     When the specific embodiment of the shift register unit shown in  FIG. 6  of the present disclosure is in operation, as shown in  FIG. 7 , in the compensation phase S 2 , a potential of the first Node P 1  is at a high level, a potential of the second node P 2  is at a low level, a low level VGL is inputted into the first clock signal terminal CB, M 5  and M 10  are both turned on to control the first gate drive signal output terminal G 1  to output the low level VGL, and the second gate drive signal output terminal G 2  to output the low level VGL; in the light-emitting phase S 3 , the potential of the first Node P 1  is at a low level, the potential of the second node P 2  is at a high level, M 4  and M 9  are both turned on, the first gate line Gatel outputs VGH 1 , and the second gate line Gate 2  outputs VGH 2 . Here, as shown in  FIG. 7 , the absolute value of VGH 1  is smaller than that of VGH 2 . 
     In the specific embodiment of the shift register unit shown in  FIG. 6 , a second control node N 2  is a node electrically connected to the gate electrode of M 2 . 
       FIG. 7  shows a waveform diagram of a first gate drive signal output by the first gate drive signal output terminal G 1 , and a waveform diagram of a second gate drive signal output by the second gate drive signal output terminal G 2 . 
     When the specific embodiment of the shift register unit shown in  FIG. 6  of the present disclosure is in operation, in a first phase, M 2 , M 5 , M 10  and M 8  are all turned on, high levels are input to the second clock signal terminal CK and the first clock signal terminal CB, the potential of the first node P 1  is at a high level, the potentials of the second control node N 2  and the second node P 2  are at low levels, and the first and second gate drive signal output terminals G 1  and G 2  both output high levels; in a second phase, M 1 , M 3 , M 4 , M 9 , M 6  and M 8  are all turned on, a low level is inputted into the second clock signal terminal CK, a high level is inputted into the first clock signal terminal CB, the potential of the first node P 1  is at a low level, the starting voltage STV is at a high level, the potentials of the second control node N 2  and the second node P 2  are at high levels, and the first and second gate drive signal output terminals G 1  and G 2  both output high levels; in a third phase, M 6 , M 7 , M 8 , M 4  and M 9  are all turned on, a high level is inputted into the second clock signal terminal CK, a low level is inputted into the first clock signal terminal CB, the starting voltage STV is at a high level, the potential of the first node P 1  is at a low level, the potentials of the second control node N 2  and the second node P 2  are both at high levels, and the first and second gate drive signal output terminals G 1  and G 2  both output high levels; in a fourth phase, M 1 , M 2 , M 3 , M 4 , M 9 , M 5 , M 10 , M 6  and M 8  are all turned on, a low level is inputted into the second clock signal terminal CK, a high level is inputted into the first clock signal terminal CB, the starting voltage STV is at a low level, the potential of the first node P 1  is at a low Level, the potentials of the second control node N 2  and the second node P 2  are both at low levels, and the first and second gate drive signal output terminals G 1  and G 2  both output high levels; in a fifth phase, M 2 , M 7 , M 8 , M 5 , and M 10  are all turned on, the starting voltage STV is at a high level, a high level is inputted into the second clock signal terminal CK, a low level is inputted into the first clock signal terminal CB, the potential of the first node P 1  is at a high level, the potentials of the second control node N 2  and the second node P 2  are both at low levels, and the first and second gate drive signal output terminals G 1  and G 2  both output low levels; in a sixth phase, M 1 , M 3 , M 4 , M 6 , and M 8  are all turned on, the starting voltage STV is at a high level, a low level is inputted into the second clock signal terminal CK, a high level is inputted into the first clock signal terminal CB, the potential of the first node P 1  is at a low Level, the potentials of the second control node N 2  and the second node P 2  are both at high levels, and the first and second gate drive signal output terminals G 1  and G 2  both output high levels; in a seventh phase, M 4 , M 9 , M 6 , M 7 , and M 8  are all turned on, the starting voltage STV is at a high level, a high level is inputted into the second clock signal terminal CK, a low level is inputted into the first clock signal terminal CB, the potential of the first node P 1  is at a low level, the potentials of the second control node N 2  and the second node P 2  are both at high levels, and the first and second gate drive signal output terminals G 1  and G 2  both output high levels. 
     In addition, the gate driving circuit described in the embodiments of the present disclosure includes multiple stages of the shift register units as described above. 
     In addition, the display device described in the embodiments of the present disclosure includes the pixel circuit as described above and the gate driving circuit as described above. 
     The display device provided by the embodiments of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. 
     The above are some optional embodiments of the present disclosure. It should be noted that several improvements and modifications can be made by those of ordinary skill in the art, without departing from the principles described in the present disclosure. These improvements and modifications should also be considered as falling within the scope of this disclosure.