Patent Publication Number: US-5293369-A

Title: Asynchronous sampling digital detector system for magnetic and optical recording channels

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to data recording channel signal detectors and, more specifically, to a digital system for detecting waveform peaks or threshold-crossings in an asynchronously-sampled data signal. 
     2. Discussion of the Related Art 
     In the data storage arts, binary data is encoded and stored on optical or magnetic media as a series of optical or magnetic threshold-crossings. Retrieval of stored data requires a detecting and decoding system in the recording channel to reconstruct the original binary data and synchronous clock from the self-clocking analog signal waveform created by the magnetic or optical transducer adjacent to the storage medium. Practitioners in the art have proposed many solutions to the problems associated with extracting synchronous clock and data signals from a self-clocking data signal. These problems include discrimination between actual threshold-crossings and mere noise pulses and precise reconstruction of the synchronous data clock signal for decoding the phase-encoded data. 
     Analog pulse detectors known in the art suffer from the usual disadvantages of analog electronic apparatus. They are expensive, bulky and subject to calibration drift over time. Moreover, analog pulse detectors are generally suited to a narrow predetermined range of channel data rates, imposing severe channel data rate restrictions on storage media data retrieval systems. Digital implementations of data pulse or threshold-crossing phase detectors known in the art usually rely on discrete-signal embodiments of the well-known analog detection techniques. For instance, the analog signal waveform is first sampled and digitized using well-known phase-locked loop (PLL) techniques. These samples are then processed digitally to remove unwanted frequency components and to reconstruct the synchronous clock and data. 
     Such a discrete-signal equivalent of a phase-locked loop circuit is disclosed by Antonia C. Van Rens, et al in U.S. Pat. No. 4,912,729. Van Rens et al disclose a digital method for detecting data pulse transitions in an asynchronously-sampled signal waveform, but their technique is restricted to controlling estimated signal threshold-crossing phase errors using a discrete-time oscillator under the control of a digital sequential filter to hold the phase error to substantially zero. The Van Rens et al digital PLL method requires asynchronous sampling rates substantially higher than the expected channel data rate. Also, if the data signal threshold-crossings temporarily drop out, their discrete-time oscillator drifts off-clock very rapidly, creating relocking delays when the data signal resumes. This also limits the variety of Run-Length Limiting (RLL) codes suitable for their device. 
     There is a clearly felt need in the art for a fully digital implementation of a channel waveform threshold-crossing phase detector that can accurately detect self-clocking data pulses in a recording channel data signal over a wide range of data rates. The crucial need is for accurate synchronous data detection at moderate asynchronous sampling rates because high-speed sampling techniques are disadvantageously expensive. Although decimation and interpolation techniques are available for translating sampling rates from one level to another, these techniques alone do not facilitate detection at unrestricted data rates in a data recording channel. Moreover, such sampling rate translation overhead militates against rapid, efficient decoding of phase-encoded data signals. 
     Digital computer programs are known in the art for simulating the functions of analog recording channels but these techniques require high sampling rates, making implementation in real-time hardware expensive and difficult as discussed above. Many of the difficulties known for digital implementation can be overcome by reducing the asynchronous analog signal sampling rate. A practical method for accurate digital phase detection at low sampling rates has not been known until now. These and other unresolved problems and deficiencies are clearly felt in the art and are solved by this invention in the manner described below. 
     SUMMARY OF THE INVENTION 
     This invention is an Asynchronous Sampling Digital Detector (ASDD) signal processing technique that is entirely digital. It is applicable to recording channels and to other sampling systems. No analog equalizers, detectors or phase-locked oscillators are necessary. Waveform sampling is entirely asynchronous. 
     The ASDD method of this invention consists of several elements. First, the analog signal waveform is sampled at an asynchronous rate and each sample is converted to a digital word representing instantaneous waveform amplitude. 
     Secondly, this analog-to-digital (A/D) converter output is equalized and filtered by digital means, such as a Finite Impulse Response (FIR) digital filter, to remove high frequency components. 
     Thirdly, after sampling equalization and digital filtering, the asynchronous waveform peaks or threshold-crossings are detected by the &#34;modified linear interpolation&#34; technique of this invention. 
     Finally, these waveform threshold-crossing detections are tested for qualification as data signals. Waveform threshold-crossings that do not meet the qualification criteria are rejected as noise. The ASDD output includes a digital word representing the estimated threshold-crossing time as a fraction of concurrent asynchronous sampling clock interval and two pulse qualification flags. 
     These digital output signals may be further processed by any useful means to reconstruct both the synchronous data clock and channel data signals. One such means is the Discrete Time Control Loop (DTCL) technique disclosed by R. A. Hutchins et al in a copending patent application entitled &#34;Discrete Time Control Loop Method And Apparatus For Clocking, Data In An Asynchronous Channel&#34;, filed on Oct. 28, 1992, as application Ser. No. 07/967,588 and included herein in its entirety by this reference. The DTCL can be adapted to accept the output signals from the ASDD of this invention. Conventional phase-locked loop methods are also suitable for data reconstruction from ASDD output. 
     It is an object of this invention to achieve digital implementation of the entire waveform threshold-crossing phase detection function in a recording channel. It is a feature of this invention that the digital filtering and equalization functions are of increased accuracy over similar analog techniques. It is another feature of this invention that it is relatively insensitive to electronic noise. 
     It is an advantage of this invention that it can be entirely implemented in low-power high-density monolithic technology such as digital Complimentary Metal-Oxide-Semiconductor (CMOS). It is another advantage of this invention that CMOS implementation of this function is less costly than other alternatives. 
     It is another object of this invention to provide for zone recording adaptation where the channel detection function must follow changes in channel data rates over a wide range. It is an advantage of the ASDD of this invention that the self-clocking data rate can vary widely over the region below the ASDD asynchronous sampling clock frequency. This permits an ASDD channel to track for instance, data from a constant linear density optical disk played back on a mechanism that varies the linear speed according to radial location on the disk, and vice-versa. It also permits the channel to operate immediately upon startup of disk or tape drive motors, before attaining rated operating speed, thereby reducing storage media access delay. 
     It is another advantage of this invention that the digital hardware implementation of the ASDD can be shared by several parallel recording channels, leading to cost savings in parallel channel systems. 
     The foregoing together with other objects, features and advantages of this invention will become more apparent when referring to the following specification, claims and the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of this invention, reference is now made to the following detailed description of the embodiments as illustrated in the accompanying drawing, wherein: 
     FIG. 1 provides a block diagram of the ASDD system of this invention; 
     FIG. 2 provides an illustrative embodiment of the threshold-crossing detector element of this invention; 
     FIG. 3 provides an illustrative embodiment of the differentiator and zero-crossing detector elements of this invention; 
     FIG. 4 provides an illustrative embodiment of the peak amplitude estimator and cubic interpolator of this invention; 
     FIG. 5 provides an illustrative embodiment of the threshold-crossing qualification circuit of this invention for negative-going threshold-crossings; 
     FIG. 6 provides an illustrative embodiment of the zero-crossing position estimator of this invention; 
     FIG. 7 illustrates the estimated peak position function for the linear and nonlinear interpolation methods of this invention; 
     FIG. 8 provides an illustrative embodiment of an adaptive threshold follower for use with an optical Pulse-Width Modulated (PWM) recording channel; 
     FIG. 9 shows the experimental waveform threshold-crossing detection phase errors for six different RLL codes in a recording channel; and 
     FIG. 10 provides an illustrative embodiment of a Discrete Time Control Loop (DTCL) suitable for recovering the data and clock signals from the digital outputs of the ASDD of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates the relationship between the ASDD 20 of this invention and the optical or magnetic data storage medium 22. Magnetic or optical threshold-crossings in medium 22 are sensed by a transducer 24 in any useful manner known in the art. The transducer output signal 26 is presented to the usual plurality of analog functions 28. These functions include preamplification, Automatic Gain Control (AGC), and anti-aliasing (low-pass) filtering. The resultant analog data signal waveform 30 is presented to ASDD 20 for data pulse detection. 
     For well-known reasons, asynchronous sampling clock rate F s  must be at least twice the anti-aliasing filter cut-off frequency f c . Thus, the inverse of the channel code rate F d  must be greater than the Nyquist factor, defined as the ratio of the double filter bandwidth (2f c ) to the effective customer bit rate (channel information rate). This factor must exceed unity according to the sampling theorem. The channel code rate F d  is related to the channel information rate by the Run-Length Limiting (RLL) code rate used in the channel, as is well-known. Thus, the ASDD asynchronous sampling clock frequency F s , which controls the A/D sampling rate, must be at least equal to the synchronous channel code rate F d  buried in self-clocking waveform 30. In this invention, the ASDD asynchronous sampling clock frequency F s , can be varied to match the expected maximum synchronous channel code clock rate F d  and is typically set at 100% to 200% thereof. 
     The ASDD 20 embodiment shown in FIG. 1 embraces the Analog-To-Digital (A/D) converter 34, the Finite-Impulse-Response (FIR) digital filter 36, the asynchronous sampling clock function 38 and the threshold-crossing detector 40. Threshold-crossing detector 40 may be alternatively configured as a peak detector, as will be apparent from the discussion below. 
     In situations where medium 22 consists of the magnetic tape in a tape drive 31 or the magnetic disk surface in a Direct Access Storage Device (DASD) 33, the recovered data appear as peaks or pulses in waveform 30. Detection of such pulses requires differentiation in detector 40. However, where medium 22 is an optical medium such as in an optical disk drive 35, the signal may be Pulse-Width-Modulated (PWM) so that the recovered data are encoded as waveform transitions through a variable but predetermined threshold. For such applications, no signal differentiation is required in detector 40, as will be appreciated with reference to the discussion below. 
     A/D converter 34 operates in the usual manner known in the art by sampling data signal waveform 30 in response to the asynchronous sampling clock pulse on a line 42. This analog sample is then converted to an 8-bit digital signal on a sample bus 44. The stream of digital samples on the bus 44 is received in FIR filter 36 and processed in the usual manner known in the art for such digital filters. FIR 36 is synchronized with converter 34 by the asynchronous clocking signal F s  at a line 46 and generates a series of 8-bit digital signals on the filtered sample bus 48. FIR filter 36 is usually a low-pass filter having the cut-off frequency f c  discussed above. 
     In operation, ASDD 20 operates at an asynchronous sampling clock frequency F s  that is somewhat higher (or no lower) than the expected data signal waveform clock frequency F d  on line 30. The ASDD output flags are labelled QNTR on a line 50 and QPTR on a line 52. The ASDD output detection phase is labelled PKE on a line 54. 
     One method for recovering the binary data from the waveform on line 30 is to count the clock periods between consecutive peaks or threshold-crossings (zero-crossings) according to the digital information on lines 50-54. These counts are made by normalizing the timing detection in ASDD 20 to the normalized clock ratio T i  =T d  /T s . This interval T i  is determined externally in Discrete Time Control Loop (DTCL) 29 or from the synchronous data rate F d  (T i  =F s  /F d ) recovered in any useful manner known in the art. DTCL 29 is described in the above-cited copending Hutchins et al patent application. 
     After the timing between peaks is normalized, it is rounded to the nearest integer to yield an exact PKD code integer, which represents the number of data clock intervals T d  separating two sequential peaks (or differential zero-crossings) in the underlying RLL code. 
     Although FIG. 1 shows DTCL 29 as the external means for recovering synchronous data clock interval T d , such external functions may be performed by any useful means known in the art. for the purpose of this disclosure. 
     For optical data encoded by Pulse-Width-Modulation (PWM), the waveform features of interest are threshold-crossings. For magnetic domain transition data storage, the signal peaks are desired. Because peak detection can be accomplished by detecting the zero-crossings of the waveform derivative, detection becomes a waveform &#34;transition&#34; or threshold-crossing detection problem for either optical or magnetic media. 
     Threshold-crossing detector 40 can be configured to detect waveform crossings of an arbitrary threshold or waveform peaks. Peak detection is merely a combination of waveform differentiation and zero-crossing detection as is well-known. 
     FIG. 2 shows an illustrative embodiment of threshold-crossing detector 40 configured for peak detection in signals from magnetic media. The magnetic transition stored on the storage medium is sensed as a peak in data signal waveform 30. Upon differentiation, the signal peak becomes a waveform threshold-crossing where the threshold is zero. These differentiation and zero-crossing functions are performed in the differentiator and zero-crossing detector 60 shown in FIG. 2. 
     Detector 60 accepts the digitally filtered sample signals on bus 48 and produces four digital output signals. The first two of these digital output signals are transmitted on the 8-bit buses 62 and 64. Bus 62 carries the absolute value of the differentiated filtered digital sample taken in the immediately preceding (i-1) th  asynchronous sampling interval, written herein as |ΔS i-1  |. This absolute value is obtained by stripping the sign bit from the differential over the (i-1) th  sampling interval, (S i-2  -S i-1  ). Bus 64 provides the differential filtered sample obtained in the current i th  asynchronous sampling interval, written herein as |ΔS i  |. Again, this represents the change over the i th  sampling interval (S i-1  -S i ) stripped of its sign bit. 
     In the method of this invention, a waveform peak is detected if two adjacent differential sample values ΔS i-1  and ΔS i  have opposing signs. Opposing signs indicate an intervening zero-crossing of the differential signal. However, either or both such digital samples may be precisely zero under some circumstances, which may create errors. A more sophisticated logic is necessary to detect zero-crossings in cases where one or both samples are zero-valued (FIG. 3). 
     The other two digital outputs from detector 60 are provided on the lines 66 and 68. Line 66 provides a signal-bit flag (NTR flag) that is held positive for the entire sampling interval wherein a negative-slope threshold-crossing is detected. Similarly, line 68 carries a single-bit flag (PTR flag) that is held positive over the sampling interval wherein a positive-slope threshold-crossing is detected. In some simple embodiments, the NTR and PTR flags can be logically combined to form a single TR flag signifying the presence of either detection within the sampling interval. The polarity of the detected threshold-crossing is preserved in the ASDD of this invention to permit implementation of adaptive threshold-crossing detection for optical PWM signal processing (FIG. 8). 
     The ASDD of this invention qualifies the detection (discriminates between signal and noise peaks) by evaluating another signal parameter at the zero-crossing of the waveform derivative. For a zero-crossing of the waveform, the waveform slope is the qualifying parameter. For a zero-crossing of the derivative, the qualification parameter of interest is the peak amplitude, which is evaluated by the peak amplitude estimator 70 using either the &#34;quasi-cubic interpolation&#34; method of this invention or any other useful method. The estimated peak amplitude (SigAmp) is an 8-bit digital signal on the amplitude bus 72. 
     The modified linear interpolation method of this invention detects a waveform zero-crossing by first searching for a sampling interval (T i ) bounded by two consecutive digital differential samples (ΔS i-1 , ΔS i ) of opposing polarity. The zero-crossing time within the i th  interval (PKE ) is then estimated by interpolation, either linear interpolation assuming that the signal waveform traces a straight line between the two consecutive samples or some form of nonlinear interpolation. 
     At the low sampling frequencies of this invention, the linear assumption is not necessarily valid and can lead to significant errors in threshold-crossing phase estimates. Threshold-crossing phase may alternatively be estimated by assuming a nonlinear path between the two consecutive samples. Such a nonlinear path is embodied in a &#34;look-up&#34; table in the zero-crossing position estimator 74. 
     The modified linear interpolation method of this invention using a simple nonlinear look-up table reduces threshold-crossing detection phase errors to less than six percent (6%) of the sampling interval, T s  (FIG. 7). 
     Waveform threshold-crossing phase PKE is estimated by zero-crossing position estimator 74 in FIG. 2. Estimator 74 accepts the magnitudes of the two 8-bit differential samples on either side of the i th  asynchronous sampling interval (ΔS i-1  and ΔS i ). The phase PKE=t/T s  estimate is generated by interpolation at the 8-bit output bus 76. The PKE digital signal on bus 76 represents the fractional location within the i th  sampling interval T s  at which the data signal waveform peak or threshold-crossing occurs. PKE is valued between zero and unity. 
     Since not all asynchronous sampling intervals contain waveform threshold-crossings, threshold-crossing detector 40 must also provide a detection flag signalling the presence of a threshold-crossing within the i th  sampling interval. Also, to avoid &#34;false alarm&#34; threshold-crossing detections arising from spurious noise, each such detection flag is screened or &#34;qualified&#34; by the zero-crossing qualification circuit 78. Circuit 78 accepts the NTR and PTR threshold-crossing flags from detector 60 and the (SigAmp) value from estimator 70. After testing the 8-bit digital peak amplitude on bus 72 against an internal threshold (not shown), circuit 78 creates two one-bit output flags on the lines 80 and 82. The QNTR on line 80 is asserted for the entire duration of the sampling interval wherein a qualified negative threshold-crossing is detected. 
     Similarly, the QPTR flag on line 82 is asserted for the entire sampling interval wherein a qualified positive waveform threshold-crossing is detected. Both lines 80 and 82 are negatively-asserted for those sampling intervals wherein no threshold-crossings are detected. Thus, the flags on lines 80 and 82 &#34;enable&#34; the downstream logic (FIG. 1) to accept the 8-bit digital PKE signal on bus 76. 
     The individual elements of threshold-crossing detector 40 are further described in the drawing. FIG. 3 shows an illustrative embodiment of detector 60. Much of the complexity of detector 60 is necessitated by the unusual situations where both S i-1  and S i  on buses 62 and 64 are zero-valued. The output bus 62 provides the absolute value of the (i-1) th  sample of the differentiated waveform. Output bus 64 provides the i th  sample. The (i+2) th  sample of the undifferentiated signal is provided at the input on bus 48. Thus, it will be appreciated that detector 60 introduces a delay of two asynchronous sampling periods, 2T s . The digital differentiator 84 provides the (i+2) th  differential value of (S i+1  -S i+2 )=ΔS i+2  on the nine-bit differential bus 86. 
     Differential digital signal 86 is delayed by one sampling interval T s  at a delay device 88. After the delay, the nine-bit bus is separated into an 8-bit absolute value at the ABS truncation circuit 90 and a two-bit sign at the SGN truncation circuit 92. The two-bit output from circuit 92 codes the sign values of +1, 0 or -1. These signs are then progressively delayed to provide a series of three sign inputs into a zero-crossing logic circuit 94 at the lines 96, 98 and 100. These inputs are s i+1 , s i , and s i-1 , which are labeled in FIG. 3 as A, B and C, respectively. The Boolean relationship between the NTR and PTR flags on lines 66 and 68 and the signs A, B and C on lines 96-100 are specified in FIG. 3. The logic identifies any movement from zero as a zero-crossing. 
     FIG. 4 shows an illustrative embodiment of peak amplitude estimator 70 employing the &#34;cubic interpolator&#34; method of this invention. Estimator 70 accepts the undifferentiated sample values on bus 48 from FIR 36 and, using the series of delays 102, effects a comparison among four sequential samples of the data signal waveform amplitude. The samples are combined with the weighting coefficients 104 to develop a peak amplitude estimate. Coefficients 104 are selected to be simple binary fractions for ease of implementation. 
     The remainder of the logic in FIG. 4 consists of the multiplexers (MUXs) 105 and 106 with associated delay modules (D) and XOR logic. MUX 105 selects one of the values on the two 8-bit buses 108 and 110, switching the selected value to the output bus 112. 
     The signs of the adjacent values involved in this comparison are split off from the main buses on lines labeled &#34;s&#34; in FIG. 4. MUX 105 discriminates between the first and third samples, making a different selection when the earlier sample is positive than when the earlier sample is negative. Thus, MUX 105 selects the lower of the two digital signal values on buses 108 and 110 if the earlier value is negative and selects the higher of those two values if the earlier value is positive. The output bus 112 presents the selection between the first and third signals in the sequence to a second identical selection circuit associated with MUX 106. 
     MUX 106 compares the second of the three digital signals with the earlier selection between the first and third signals, selecting a final signal from the three sequential samples and putting it on bus 114, enforcing the same logic as was discussed above in connection with MUX 105. Finally, a delay 116 is provided to synchronize the estimated signal amplitude output (SigAmp) at bus 72 with the remaining elements of threshold-crossing detector 40. 
     Zero-crossing qualification circuit 78 in FIG. 2 includes logic for qualifying both negative-transiting detections and positive-transiting detections. Because the circuits are essentially identical in function, only the negative threshold-crossing qualifying circuit 118 illustrated in FIG. 5 is discussed herein. 
     The circuit in FIG. 5 will be recognized by practitioners in the art as a gated Infinite-Impulse-Response (IIR) digital filter operating as an envelope peak detector. The digital signal provided at the bus 120 represents the threshold qualification ratio T r . It is multiplied with the signal envelope value on the bus 122 at a multiplier 124. The output of multiplier 124 is the threshold level, which is fed back on a bus 126 to the comparator 128 where it is compared with the pulse amplitude (SigAmp) output on bus 72 from estimator 70. 
     Comparator 128 creates a qualification flag on the line 130 for the entire asynchronous sampling interval wherein a pulse amplitude on bus 72 is found to exceed the threshold on bus 126. This qualification flag is logically combined with the negative transition detection flag NTR on line 68, using the simple AND-gate 132. The output of AND-gate 132 is the QNTR flag on line 80 discussed above in connection with FIG. 2. 
     The QNTR flag also &#34;enables&#34; the delay register 134, clocking through the signal envelope value. The digital value on the bus 136 determines the tracking rate of the signal envelope by weighting the &#34;input&#34; component on the bus 138 relative to the fed-back &#34;output&#34; component on the bus 140. The logic essentially provides an envelope value &#34;OUTPUT&#34; at bus 122 described by the formula: 
     
         OUTPUT.sub.i+1 =(INPUT.sub.i *a+OUTPUT.sub.i *[1-a])*QNTR.sub.i+1, 
    
     where &#34;a&#34; is the weighting factor on bus 136. 
     The key element of threshold-crossing detector 40 is perhaps estimator 74, which is illustrated in FIG. 6. Estimator 74 receives two digital signals on buses 62 and 64 and generates on bus 76 the PKE i  signal representing the estimated threshold-crossing location within the present sampling interval. The shifters 144 and 146 reduce the necessary size of ROM 142 by deleting the three least significant bits (LSBs) in the digital input signals. The shift logic 148 avoids a full three-bit shift in cases where the most significant bit or bits (MSBs) are zero on both buses 62 and 64. 
     The distance from a threshold-crossing or zero-crossing to the previous sample S i-1  (that is, to the beginning of the present i th  sampling interval) is determined by the table look-up embodied in a Read-Only-Memory (ROM) 142. FIG. 7 illustrates the performance of two different interpolation formulas for a (1,7) RLL code. Either interpolation formula can be implemented in estimator 74 by changing the contents (look-up table) of ROM 142. 
     Simple linear interpolation error is greater than error arising from certain nonlinear assumptions of threshold-crossings between sample points. In the example shown in FIG. 7, nonlinear interpolation provides significantly less estimation error than linear interpolation, but is slower. The inventors have demonstrated that the improvement in overall performance is relatively modest and may not be worth the additional processing time. For instance, linear interpolation using a (1,7) RLL code signal sampled asynchronously at the data clock rate F d  provides worst-case errors of only 17% of the sampling interval T s . By adding a more sophisticated nonlinear interpolation table, this error can be reduced to 6% of a sampling interval. Overall channel Bit Error Rate (BER) performance may not be materially affected by the difference between the two errors. Moreover, simple linear interpolation is faster and easier to implement than the more sophisticated ROM 142 look-up table required for nonlinear interpolation. Linear interpolation does not necessarily require a look-up table. 
     In some applications, such as optical data recording using PWM encoding, the threshold-crossing detection cannot rely on zero-crossing techniques because the threshold level is set at a value other than zero. FIG. 8 provides an illustrative embodiment of an adaptive threshold follower for such non-zero threshold applications. This circuit requires an external digital input (from DTCL 29 or elsewhere) representing the phase error {E} determined from the data {D} and the reconstructed synchronous data clock F d . The QNTR flag is also required. A tracking rate weighting factor is included to modulate the damping of the follower circuit 150. The inputs are combined by an XOR-gate 158 and passed through a simple envelope detector to create an output threshold level at the line 160. Threshold 160 may then be input to threshold-crossing detector 40 to adjust the digital sample signals on filtered sample bus 48, thereby creating normalized digital samples suitable for zero-crossing transition testing. 
     FIG. 9 shows the ratio of two simulated consecutive opposite-polarity samples verses the known distance between the first sample and the zero-crossing detection for several peaks of a random (2,7) RLL waveform. The inventors simulated these examples on a large-scale computer and averaged results from twenty-two different sampling clock phases to generate the plot in FIG. 9. The worst-case error noted is about 4% of the sampling interval T s . In the simulation, third-order differencing was used to simulate differentiation and linear interpolation was used to estimate zero-crossing location within each sampling interval. If the first-order differencing discussed above is used for differentiation, the worst error exceeds 10% of the sampling interval. 
     FIG. 10 provides an illustrative embodiment of the DTCL 56 discussed above in connection with FIG. 1. The detailed operation of the DTCL in FIG. 10 is the subject of the above-cited Hutchins et al patent application. FIG. 10 is introduced herein only to show that the QNTR, QPTR and PKE outputs from ASDD 20 may be used directly to reconstruct the data signal at a bus 162, to provide a digital phase error signal at a bus 164, and to recreate synchronous data clock frequency F d  at a bus 166. Many other techniques can also be used to recreate data {D} and synchronous clock signal F d  from the outputs of ASDD 20. 
     The ASDD of this invention is also ideally suited for global clock recovery applications. High-end magnetic tape systems are usually multitrack systems with up to eighteen heads simultaneously reading the tape at one instant. Because tape recording is basically a longitudinal system, it is reasonable to assume that large variations in the tape velocity occur in the longitudinal direction, with velocity variations from track to track being relatively small. Thus, it is useful and desirable to have a clock recovery system that uses the information from all the tape tracks to drive phase and frequency information. The ASDD is ideally suited for such applications because a number of such ASDD channels can be embodied as a single monolithic integrated circuit, either physically or through high-speed digital multiplexing. Thus, eighteen such ASDDs can be embodied on a single chip for use in providing the plurality of parallel phase detections necessary for simultaneous clock recovery in a multitrack tape system. 
     The global clock recovery concept has been successfully used in existing tape recording systems. The advantages include improved SNR margin, better frequency/acceleration response, reduced error lengths, and a reduction in the average size of sync-slips. The primary advantage of a global clock recovery system over a single-track clock recovery system is noted during signal dropouts. When a dropout occurs on a given track and there is no phase information for the dropout period, the associated single-track clock recovery system loses synchronization. Thus, a single-track clock recovery scheme must switch over to an open-loop mode without any feedback until the tape moves past the dropout region. However, with a global clock recovery system, even though there may be phase information missing on one or more tracks during the dropout period, phase information can be provided by the remaining tracks in the system to maintain synchronization. This reduces the size and effect of dropout errors and synchronization losses. 
     Clearly, other embodiments and modifications of this invention will occur readily to those of ordinary skill in the art in view of these teachings. Therefore, this invention is to be limited only by the following claims, which include all such embodiments and modifications when viewed in conjunction with the above specification and accompanying drawing.