Patent Publication Number: US-9904752-B2

Title: Methods for distributing power in layout of IC

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This Application claims priority of U.S. Provisional Application No. 62/108,629, filed on Jan. 28, 2015, and U.S. Provisional Application No. 62/188,495, filed on Jul. 3, 2015, the entireties of which are incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a method for distributing power in the layout of an integrated circuit (IC), and more particularly, to a method for distributing power in the layout of an IC to manage power in macro blocks of the IC. 
     Description of the Related Art 
     In recent years, the developmental process of integrated circuits (ICs), such as very larger scale integrated circuit (VLSI) has generally utilized computer assisted design (CAD). According to a developmental process based on CAD, abstract circuit data, which corresponds to the functions of the integrated circuit to be developed, is defined by using a so-called hardware description language (HDL), and the defined circuit is used to form a concrete circuit structure to be mounted on a chip. 
     Before the IC chips are manufactured (or implemented), the floor plans and the layout areas of the IC chips are considered first so as to determine the die size of each IC chip. Furthermore, a power supply arrangement is also important in the placements and the floor plans of the IC chip. If the power supply arrangement is not appropriate, it will affect the normal operation of the IC chips after the IC chips are manufactured. 
     BRIEF SUMMARY OF THE INVENTION 
     Methods for distributing power in the layout of an integrated circuit and integrated circuits are provided. An embodiment of a method for distributing power in the layout of an integrated circuit is provided. The integrated circuit comprises at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block comprises a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further comprises a low drop out (LDO) regulator. 
     Furthermore, another embodiment is provided of a method for distributing power in the layout of an integrated circuit, wherein the integrated circuit comprises at least one macro block. The first physical layout of the macro block is obtained, wherein the macro block comprises a plurality of standard cells. The IR simulation result of the first physical layout is obtained. The first physical layout is divided into a plurality of partitions according to the IR simulation result. A plurality of low drop out (LDO) regulators are inserted into the respective partitions. The second physical layout is obtained according to the partitions and the LDO voltage regulators. The macro placement of the macro block is obtained according to the second physical layout. Each of the LDO voltage regulators provides an output voltage as a supply voltage of the standard cells of the corresponding partition, and the supply voltage of the standard cells of each of the partitions is independent. 
     Moreover, an embodiment of an integrated circuit is provided. The integrated circuit comprises at least one macro block comprising a plurality of standard cells formed in a physical layout. The physical layout is divided into a plurality of partitions according to an IR simulation result of the macro block. Each of the partitions further comprises a low drop out (LDO) regulator. Each of the LDO voltage regulators provides an output voltage as a supply voltage of the standard cells of the corresponding partition, and the output voltage of each of the LDO voltage regulators is independent. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows a flow chart illustrating a typical hierarchical design process of an integrated circuit (IC); 
         FIG. 2  shows a method for providing a macro placement of a macro block in an IC according to an embodiment of the invention, wherein the method of  FIG. 2  is performed by a computer capable of operating an electronic design automation (EDA) tool; 
         FIG. 3  shows a flowchart of the power distribution procedure of step S 230  of  FIG. 2  according to an embodiment of the invention; 
         FIG. 4  shows an example illustrating power domains of a macro block  400  in the power distribution procedure of step S 230  of  FIG. 2  according to an embodiment of the invention; 
         FIG. 5  shows an example illustrating a final physical layout of a macro block according to an embodiment of the invention; 
         FIG. 6  shows an example illustrating a final physical layout of a macro block according to another embodiment of the invention; 
         FIG. 7  shows a zoom-in diagram of the macro block of  FIG. 6  according to an embodiment of the invention; and 
         FIG. 8  shows a computer system according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1  shows a flow chart illustrating a typical hierarchical design process of an integrated circuit (IC). First, in step S 110 , a register-transfer-level (RTL) code describing the function performed by the IC is obtained. Next, in step S 120 , the RTL code is synthesized to generate gates for the IC. In general, the IC comprises a plurality of macro blocks, and each macro block provides a significant function for the IC, such as a specific processor (e.g. an application processor, a video processor, an audio processor, or a controller), a memory (e.g. a SRAM module) and so on. Furthermore, each macro block has a corresponding RTL code, and then the RTL codes of each macro block are synthesized to generate the gates of the macro block. Next, in step S 130 , according to a plurality of macro placements of the macro blocks, a whole chip placement procedure is performed to generate a placement of the gates within a chip area of the IC. For example, assuming that the IC comprises N macro blocks, N macro placements of the N macro blocks will be previously generated according to the RTL codes of the macro blocks by performing the individual macro placement procedures. Thus, according to the N macro placements of the N macro blocks and the gates that do not belong to the N macro blocks, the whole chip placement procedure is performed and a whole chip placement is obtained. Next, the routing paths are obtained according to the whole chip placement (step S 140 ), and then it is checked whether there is any congestion in the whole chip placement according to the routing paths (step S 150 ). If there is no congestion, the IC is implemented according to the whole chip placement and routing paths (step S 170 ). If there is congestion, the chip area of the IC must be modified to handle the congestion (step S 160 ), and then the automatic place and route (APR) procedure is performed again (steps S 130  and S 140 ) so as to generate a new whole chip placement of the gates with the corresponding routing paths within the increased chip area of the IC. 
       FIG. 2  shows a method for providing a macro placement of a macro block in an IC according to an embodiment of the invention, wherein the method of  FIG. 2  is performed by a computer capable of operating an electronic design automation (EDA) tool. First, in step S 210 , a processor of the computer obtains a plurality of gates of the macro block after RTL code of the macro block is synthesized. Next, in step S 220 , the processor performs an APR procedure on the gates of the macro block, to obtain an initial physical layout of the macro block. Next, in step S 230 , the processor performs a power distribution procedure on the initial physical layout of the macro block, so as to partition power domain of the initial physical layout and obtain a final physical layout with a flexible power management. For example, the initial physical layout comprises a single power group for providing a single power to supply the whole standard cells within the macro block, and the final physical layout comprises a plurality of power groups for providing various voltage signals to supply the standard cells of the macro block, so as to control power consumption of the macro block. Next, in step S 240 , the processor obtains the macro placement of the macro block according to the final physical layout. As described above, a whole chip APR is performed after obtaining the macro placements of the entire macro blocks of an IC, e.g. steps S 130  and S 140  of  FIG. 1 . 
       FIG. 3  shows a flowchart of the power distribution procedure of step S 230  of  FIG. 2  according to an embodiment of the invention. First, in step S 310 , the processor obtains the initial physical layout of the macro block, wherein the supply voltages of the gates are assigned to a single voltage signal in the initial physical layout, i.e. the supply voltages of the gates are coupled together in the initial physical layout of the macro block. In the embodiment, the initial physical layout of the macro block comprises a plurality of standard cells corresponding to the gates of the macro block, and the standard cells comprise the logic gates (e.g. inverter, AND, OR gates), delay cells, flip flops and clock cells etc. Next, in step S 320 , the processor performs a gate-level power analysis on the initial physical layout according to the single voltage signal, and then obtains an IR simulation result corresponding to the initial physical layout. Next, in step S 330 , the processor divides the initial physical layout into a plurality of partitions according to the IR simulation result, wherein each partition corresponds to a power group. Next, in step S 340 , the processor inserts a plurality of low drop out (LDO) regulators into the partitions, respectively. For example, each power group comprises an inserted LDO voltage regulator, and the inserted LDO voltage regulator is capable of outputting a voltage signal as a supply voltage of the standard cells of the partition corresponding to the power group. Furthermore, in each power group, output properties (e.g. a voltage level, a driving current, etc.) of the voltage signal are determined according to the IR simulation result regarding the partition corresponding to the power group. Simultaneously, the processor inserts a plurality of power isolation cells between the partitions, so as to provide isolation between the different power groups. Specifically, the power groups are separated by the power isolation cells in the macro block. Next, in step S 350 , the processor obtains the final physical layout according to the partitions, the LDO voltage regulators, and the power isolation cells. In one embodiment, each LDO voltage regulator provides the voltage signal according to the same power signal, e.g. the single voltage signal of the single power group. 
       FIG. 4  shows an example illustrating power domains of a macro block  400  in the power distribution procedure of step S 230  of  FIG. 2  according to an embodiment of the invention. After the power distribution procedure is performed, a plurality of power groups  410 _ 1  to  410 _n are formed in the macro block  400 . As described above, each power group corresponds to an individual partition in a final physical layout of the macro block  400 . Each of the power groups  410 _ 1  to  410 _n comprises a LDO voltage regulator, which is capable of providing a supply voltage according to a global voltage signal VDD G  to the standard cells of the corresponding partition, and the global voltage signal VDD G  is provided by a power source  430 , such as a power management unit. For example, in the power group  410 _ 1 , a LDO voltage regulator  420 _ 1  provides a voltage signal VDD 1  according to the global voltage signal VDD G  and an IR simulation result regarding the partition corresponding to the power group  410 _ 1 , the LDO voltage regulator  420 _ 2  provides a voltage signal VDD 2  according to the global voltage signal VDD G  and an IR simulation result regarding the partition corresponding to the power group  410 _ 2 , and so on. It should be noted that the voltage signals VDD 1  to VDD n  are independent from each other. In the embodiment, by inserting the LDO voltage regulators  420 _ 1  to  410 _n into the partitions of the macro block  400 , the power consumption of the macro block  400  is decreased due to each partition of the macro block  400  being operated with the suitable supply voltage. Compared with a conventional macro block that uses a single power group (e.g. the global voltage signal VDD G ) to provide a single voltage as a supply voltage of the total standard cells in the conventional macro block, no additional power is wasted in the macro block  400 . 
       FIG. 5  shows an example illustrating a final physical layout of a macro block  500  according to an embodiment of the invention. The macro block  500  comprises 9 partitions  510 - 590 , and each of the partitions  510 - 590  comprises a LDO voltage regulator. For example, the partition  510  comprises a LDO voltage regulator  515 , and the partition  520  comprises a LDO voltage regulator  525 . As described above, each LDO voltage regulator is capable of providing an output voltage as a supply voltage of the standard cells within the corresponding partition. In the embodiment, the layout areas of the partitions  510 - 590  have the same shape, i.e. the macro block  500  has a regular power domain partition. In some embodiments, the quantities of the standard cells of the partitions  510 - 590  are equal. It should be noted that the layout area of the partition, the quantity of the standard cells within the partition, and the shape of the partition are determined according an IR simulation result of the macro block  500 . As described above, the LDO voltage regulators of the final physical layout of the macro block  500  will be implemented in an integrated circuit (IC), so as to decrease power consumption of the macro block  500  in the IC. 
       FIG. 6  shows an example illustrating a final physical layout of a macro block  600  according to another embodiment of the invention. The macro block  600  comprises 8 partitions  610 - 680 , and each of the partitions  610 - 680  comprises a LDO voltage regulator. As described above, each LDO voltage regulator is capable of providing an output voltage as a supply voltage of the standard cells within the corresponding partition. In the embodiment, layout areas of the partitions  610 - 680  have different shapes, i.e. the macro block  600  has a non-regular power domain partition. It should be noted that the layout area of the partition, the quantity of the standard cells within the partition, and the shape of the partition are determined according an IR simulation result of the macro block  600 . Furthermore, the LDO voltage regulators of final physical layout of the macro block  600  will be implemented in an IC, so as to decrease power consumption of the macro block  600  in the IC. 
       FIG. 7  shows a zoom-in diagram  700  of the macro block  600  of  FIG. 6  according to an embodiment of the invention. The zoom-in diagram  700  shows a boundary between the partitions  610  and  620  of  FIG. 6 . In the embodiment, each of the partitions  610  and  620  comprises a plurality of standard cells  710  formed a standard cell array, and a plurality of power lines and plurality of ground lines form a mesh disposed on the standard cell array. In the partition  610 , a plurality of power lines VDD_R 1  and a plurality of ground lines GND_R are alternately disposed on the rows of the mesh, and a plurality of power lines VDD_C 1  and a plurality of ground lines GND_C are alternately disposed on the columns of the mesh. In the embodiment, the power lines VDD_R 1  and the ground lines GND_R are implemented by a first metal layer, and the power lines VDD_C 1  and the ground lines GND_C are implemented by a second metal layer below or above the first metal layer. In some embodiments, the power lines VDD_R 1  and VDD_C 1  and the ground lines GND_R and GND_C are implemented by different metal layers. Similarly, in the partition  620 , a plurality of power lines VDD_R 2  and a plurality of ground lines GND_R are alternately disposed on the rows of the mesh, and a plurality of power lines VDD_C 2  and a plurality of ground lines GND_C are alternately disposed on the columns of the mesh. In the embodiment, the power lines VDD_R 2  and the ground lines GND_R are implemented by the first metal layer, and the power lines VDD_C 2  and the ground lines GND_C are implemented by the second metal layer. In some embodiments, the power lines VDD_R 2  and VDD_C 2  and the ground lines GND_R and GND_C are implemented by different metal layers. It should be noted that the shape, size and type of the standard cells are used as an example, and not to limit the invention. Furthermore, for each standard cell  710  of the partitions  610  and  620 , the power lines and the ground lines completely pass across the standard cell. Moreover, the partitions  610  and  620  share the ground lines GND_R and GND_C, and the ground lines GND_R and GND_C will be connected to each other through a plurality of vias between the first and second metal layers. Referring to  FIGS. 6 and 7  together, the power lines VDD_R 1  and VDD_C 1  are coupled to the LDO voltage regulator  615  of the partition  610 . Thus, the output voltage of the LDO voltage regulator  615  is provides to the standard cells  710  of the partition  610  as a supply voltage. Similarly, the power lines VDD_R 2  and VDD_C 2  are coupled to the LDO voltage regulator  625  of the partition  620 . Thus, the output voltage of the LDO voltage regulator  625  is provides to the standard cells  710  of the partition  620  as a supply voltage. 
     In  FIG. 7 , a plurality of power isolation cells  720  are disposed between the partitions  610  and  620 . In the embodiment, only the ground lines GND_R and GND_C completely pass across the power isolation cell  720 . The power isolation cell  720  is used to separate the power lines of the partitions  610  and  620 , i.e. the power lines will not completely pass across the power isolation cell  710 . For example, the power lines VDD_R 1  and the power lines VDD_R 2  disposed on the same row are separated by the power isolation cells  720 , shown as label  730 . In one embodiment, the power lines VDD_C 1  and the power lines VDD_C 2  disposed on the same column are also separated by the power isolation cells  720 , shown as label  740 . In some embodiments, the power isolation cell  720  is a bypass capacitor. 
       FIG. 8  shows a computer system  100  according to an embodiment of the invention. The computer system  100  comprises a computer  110 , a display device  120  and a user input interface  130 , wherein the computer  110  comprises a processor  140 , a memory  150 , and a storage device  160 . The computer  110  is coupled to the display device  120  and the user input interface  130 , wherein the computer  110  is capable of operating an electronic design automation (EDA) tool. Furthermore, the computer  110  is capable of receiving input instruction from the user input interface  130  and displaying the physical layouts and the placements of macro blocks of the IC on the display device  120 . In one embodiment, the display device  120  is a GUI for the computer  110 . Furthermore, the display device  120  and the user input interface  130  can be implemented in the computer  110 . The user input interface  130  may be a keyboard, a mouse and so on. In the computer  110 , the storage device  160  can store the operating systems (OSs), applications, and data that comprise input required by the applications and/or output generated by applications. The processor  140  of the computer  110  can perform one or more operations (either automatically or with user input) in any method that is implicitly or explicitly described in this disclosure. For example, during operation, the processor  140  can load the applications of the storage device  160  into the memory  150 , and then the applications can be used by a user to create, view, and/or edit a placement, a floor plan and a physical layout for a circuit design. 
     The data structures and code described in this disclosure can be partially or fully stored on a computer-readable storage medium and/or a hardware module and/or hardware apparatus. A computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media, now known or later developed, that are capable of storing code and/or data. Hardware modules or apparatuses described in this disclosure include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and/or other hardware modules or apparatuses now known or later developed. 
     The methods and processes described in this disclosure can be partially or fully embodied as code and/or data stored in a computer-readable storage medium or device, so that when a computer system reads and executes the code and/or data, the computer system performs the associated methods and processes. The methods and processes can also be partially or fully embodied in hardware modules or apparatuses, so that when the hardware modules or apparatuses are activated, they perform the associated methods and processes. Note that the methods and processes can be embodied using a combination of code, data, and hardware modules or apparatuses. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.