Patent Publication Number: US-8542769-B2

Title: High output power digital TX

Description:
The invention disclosed herein generally relates to wireless transmitters, and more particularly relates to high output power digital transmitters. 
     BACKGROUND 
     Digital-to-analog converters may be used for a wide variety of applications, including wireless transmitters. Conventional wireless transmitters may first pass a digital signal through a digital-to-analog converter to convert the digital signal to an analog signal, and then pass the analog signal through filters, mixers, and amplification stages to generate a transmission signal at a desired radio frequency (RF). Recently, direct digital-to-RF converters have simplified wireless transmitters by combining digital-to-analog conversion with RF upconversion. Such direct digital-to-RF converters have significant advantages, e.g., fewer components, improved accuracy, smaller footprint, etc. When used in high power applications, however, direct digital-to-RF converters may have a high current consumption. Because current draw from the power supply converts to supply power voltage based on the corresponding resistance, and because the direct digital-to-RF converter transforms variations in the power supply to noise, the high current consumption and the corresponding resistance limits the maximum output power available with a direct digital-to-RF converter. Further, when the direct digital-to-RF converter has an IQ modulation structure, the In-phase (I) and Quadrature (Q) branches act as loads for each other, which limits the maximum signal level achievable by the direct digital-to-RF converter. For example, the I and Q branches deliver an out-of-phase signal, which reduces the maximum output power relative to in phase operation. Thus, there remains a need for improved direct digital-to-RF converters for high power and/or IQ applications. 
     SUMMARY 
     The disclosed digital-to-analog upconverter addresses the above-described problems by connecting first and second amplifiers to first and second balanced upconverters, respectively, to control the output power. The digital-to-analog upconverter further connects the amplifier outputs to a differential combiner to isolate the first and second upconverters. The first balanced upconverter converts an In-phase portion of a baseband digital value to a first In-phase analog component (I p ) at a radio frequency (RF) and a second In-phase analog component (I n ) at the RF, where the I n  is phase-shifted relative to I p . The second balanced upconverter converts a Quadrature portion of the baseband digital value to a first Quadrature analog component (Q p ) at the RF and a second Quadrature analog component (Q n ) at the RF, where Q n  is phase-shifted relative to Q p . The first amplifier amplifies I p  and I n  to generate amplified I p  and I n  signals at first and second In-phase amplifier outputs, while the second amplifier amplifies Q p  and Q n  to generate amplified Q p  and Q n  signals at first and second Quadrature amplifier outputs. The first and second amplifiers each operate at a 50% duty cycle and in an interleaved fashion such that only one of the first and second amplifiers is active at any time, and such that the first amplifier outputs the amplified I p  and amplified I n  signals for a first 25% of the cycle, the second amplifier outputs the amplified Q p  and amplified Q n  signals for a subsequent second 25% of the cycle, the first amplifier outputs the amplified I p  and amplified I n  signals for a subsequent third 25% of the cycle, and the second amplifier outputs the amplified Q p  and Q n  signals for a final 25% of the cycle. The differential combiner combines the amplified signals output by the first and second amplifiers during the cycle to generate the RF analog signal representative of the baseband digital value. 
     The invention disclosed herein also includes a method of converting a sequence of baseband digital values to an RF analog signal. The method includes converting an In-phase portion of a baseband digital value to a first (I p ) and second (I n ) In-phase analog component at a radio frequency (RF), and converting a Quadrature portion of the baseband digital value to a first (Q p ) and second (Q n ) Quadrature analog component at the RF. The method further includes amplifying I p  and I n  using a first amplifier to generate amplified I p  and I n  signals at first and second In-phase amplifier outputs, and amplifying Q p  and Q n  using a second amplifier to generate amplified Q p  and Q n  signals at first and second Quadrature amplifier outputs, where the amplifier outputs the amplified signals relative to the duty cycle as disclosed above. The amplified signals are combined to generate the RF analog signal representative of the baseband digital value. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a block diagram of a digital-to-analog upconverter according to one exemplary embodiment. 
         FIG. 2  depicts an exemplary method executed by the digital-to-analog upconverter of  FIG. 1 . 
         FIG. 3  depicts an exemplary upconversion module for the digital-to-analog upconverter of  FIG. 1 . 
         FIG. 4  depicts an exemplary conversion unit for the upconverter of  FIG. 6 . 
         FIG. 5  depicts an exemplary amplifier for the digital-to-analog upconverter of  FIG. 1 . 
         FIGS. 6A and 6B  depict exemplary signals for the amplifier of  FIG. 5 . 
         FIG. 7  depicts an exemplary differential combiner. 
         FIG. 8  depicts another exemplary differential combiner. 
         FIG. 9  depicts an optional pre-distortion module for the digital-to-analog upconverter. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1 and 2  respectively depict a block diagram of an exemplary digital-to-analog upconverter  100  and the corresponding upconversion method  200 . Digital-to-analog upconverter  100  comprises an upconversion module  110 , an amplifier module  140 , and a differential combiner  170 . The upconversion module  110  upconverts a digital baseband value D BB  to phase-shifted analog signals at a radio frequency (RF). The amplifier module  140  amplifies the upconverted analog signals to generate amplified analog signals. The differential combiner  170  combines the amplified analog signals to generate an RF analog signal representative of D BB . A single power supply may be used to power the upconversion module  110  and the amplifier module  140 . For some embodiments, however, it will be appreciated that the upconversion module  110  may be powered by a first power supply (PWR 1 ), while the amplifier module  140  may be powered by a separate second power supply (PWR 2 ). 
     Upconversion module  110  comprises an In-phase upconverter  120  and a Quadrature upconverter  130 . In-phase upconverter  120  converts the In-phase portion of D BB  (D BB-I ) to a first In-phase analog signal (I p ) and a second In-phase analog signal (I n ), both at the RF (block  210 ). I p  and I n  have the same magnitude but are phase-shifted, e.g., by 175°-185°, with respect to each other. Similarly, Quadrature upconverter  130  converts the Quadrature portion of D BB  (D BB-Q ) to a first Quadrature analog signal (Q p ) and a second Quadrature analog signal (Q n ), both at the RF (block  210 ). Q p  and Q n  have the same magnitude but are phase-shifted, e.g., by 175°-185°, with respect to each other. As understood by those skilled in the art, I p  and I n  are out of phase from Q p  and Q n , e.g., by 90°. 
     Amplifier module  140  comprises an In-phase amplifier  150  and a Quadrature amplifier  160 . In-phase amplifier  150  amplifies I n  and I p  to generate amplified In-phase signals I 1 , I 2  (block  220 ). I 1  and I 2  have the same magnitude but are phase-shifted, e.g., by 175°-185°, with respect to each other. Quadrature amplifier  160  amplifies Q p  and Q n  to generate amplified Quadrature signals Q 1 , Q 2  (block  220 ). Q 1  and Q 2  have the same magnitude but are phase-shifted, e.g., by 175°-185°, with respect to each other. As understood by those skilled in the art, I 1  and I 2  are out of phase from Q 1  and Q 2 , e.g., by 90°. Differential combiner  170  combines I 1  and I 2 , and Q 1  and Q 2  to generate an RF analog signal (RF Output) representative of D BB . 
     Amplifiers  150 ,  160  alternately output the amplified analog signals to interleave the amplification of the input signals (block  230 ). More particularly, amplifiers  150 ,  160  are enabled with an enable signal operating at a 50% duty cycle relative to a time period and having a fundamental frequency that is twice the RF of the input analog signals, where the enable signal for the In-phase amplifier  150  is 180° out of phase with the enable signal for the Quadrature amplifier. As a result, only one amplifier  150 ,  160  is active during any particular portion of the time period, causing the amplifiers  150 ,  160  to output signals I 1 , I 2 , Q 1 , and Q 2  in an interleaved fashion. For example, Table 1 shows the amplified signals at the different amplifier outputs during different quarters of the time period, where Î p , Î n , {circumflex over (Q)} p , and {circumflex over (Q)} n  respectively correspond to the amplified I p , amplified I n , amplified Q p , and amplified Q n  signals. 
                                         TABLE 1                       1 st  Quarter   2 nd  Quarter   3 rd  Quarter   4 th  Quarter                                                                I 1     Î p     Off   Î p     Off           I 2     Î n     Off   Î n     Off           Q 1     Off   {circumflex over (Q)} p     Off   {circumflex over (Q)} p             Q 2     Off   {circumflex over (Q)} n     Off   {circumflex over (Q)} n                          
As shown by Table 1, both amplifiers  150 ,  160  are active for 50% of the time period, and therefore, have a 50% duty cycle. However, due to the frequency and phase differences of the amplifiers&#39; input signals and the characteristics of the amplifiers&#39; enable signals, the specific signals affecting each amplifier output, e.g., D BB-I , D BB-Q , V bias , etc., are each available at the amplifier outputs for 25% of the time period, and therefore are unavailable for 75% of the time period. More particularly, because the amplifier input signals are at RF and the amplifier enable signals are at twice RF, because both amplifier input signals are amplified at the same time, and because the In-phase and Quadrature signals are out-of-phase, e.g., by 90°, each combination of amplifier output signals has a 25/75 duty cycle. Because I p  and (and Q p  and Q n ) are different during different quarters of time period, the amplified signals are also different during different quarters. For example, when I p  is derived from D BB-I  during the first quarter, it is derived from V bias  during the third quarter. Similar logic applies to I n  and the Quadrature signals. Table 2 shows the different amplifier outputs for this example.
 
                                         TABLE 2                       1 st  Quarter   2 nd  Quarter   3 rd  Quarter   4 th  Quarter                                                        I 1     Î p  ∝ D BB-I     Off   Î p  = V bias     Off       I 2     Î n  = V bias     Off   Î n  ∝ D BB-I     Off       Q 1     Off   {circumflex over (Q)} p  ∝ D BB-Q     Off   {circumflex over (Q)} p  = V bias         Q 2     Off   {circumflex over (Q)} n  = V bias     Off   {circumflex over (Q)} n  ∝ D BB-Q                      
As a result, D BB-I  is present in I 1  25% of the time, and is present in I 2  25% of the time. Similarly, D BB-Q  is present in Q 1  25% of the time, and is present in Q 2  25% of the time. Thus, the RF output of the differential combiner  170  is proportional to D BB-I −V bias  in the first quarter, proportional to D BB-Q −V bias  in the second quarter, proportional to V bias −D BB-I  in the third quarter, and proportional to V bias −D BB-Q  in the fourth quarter.
 
     While the amplifiers  150 ,  160  disclosed herein may be used with any direct digital-to-analog upconverter,  FIG. 3  depicts a block diagram of an exemplary In-phase upconverter  120  that upconverts an N-bit In-phase portion of the digital baseband value D BB  (D BB-I ). For simplicity, the In-phase upconverter  120  of  FIG. 3  only depicts one output, e.g., an In-phase output encompassing both I p  and I n . While details are only shown for In-phase upconverter  120 , it will be appreciated that Quadrature upconverter  130  generally comprises the same circuits as the In-phase upconverter  120 , where the Local Oscillator (LO) signals received by the Quadrature upconverter  130  are out of phase from the LO signals received by the In-phase upconverter  120 , e.g., by 90°. Further details for exemplary upconversion modules may be found in U.S. patent application Ser. No. 13/076,717 filed 31 Mar. 2011, which is incorporated by reference herein. 
     As depicted in  FIG. 3 , In-phase upconverter  120  comprises a plurality of conversion units  122   a - c  coupled at the output to a common node  128 . Each conversion unit  122  includes a logic unit  124  and a weighting unit  126 . The logic units  124  modulate or null the input oscillator signal (LO) responsive to the corresponding input digital bit to generate an RF signal. This may be performed, for example, by multiplying LO with the input digital bit using a NAND, AND, OR, NOR, XOR, or XNOR logic gate, inverter, three-state inverter, transmission gate, series switches, or any other suitable means. When a logic gate is used, e.g., an OR, NOR, NAND, or AND gate, the result is a signal which is substantially constant when the input bit is in a first state (e.g., a high or low state), and is an oscillating signal at RF when the input bit is in a second state (e.g., a low or high state). 
     Weighting units  126  convert the signal output by the corresponding logic unit  124  to a weighted analog RF signal  127 . The weighting applied by weighting units  126  depends on the weight of the respective input bits. For example, if D BB-I  represents a binary number, each weighting unit  126  applies the binary weighting associated with the corresponding input bit within the binary number. Alternatively, if D BB-I  represents a thermometer coded value, each weighting unit  126  applies equal weight. In this case, weighting units  126  may not be required, or may comprise units  126  with equal weights. The result is that the weighting units  126 , e.g., capacitors  126 , control the relative amplitudes of the upconverted signals output by the NAND gates  124  according to the binary weighting of the respective bits of the input digital value. In various embodiments, weighting units  126  may comprise capacitors, resistors, inductors or any other suitable means to control the relative amplitude of the individual upconverted signals output by the logic units  124 . 
     The weighted analog RF signals  127  are combined at junction  128  to produce a combined In-phase RF analog signal  129 , the amplitude of which is representative of D BB-I . For example, the combined In-phase RF analog signal comprises a weighted sum, or other suitable combination, of the individual weighted analog signals  127 . Each input data bit therefore contributes to the signal magnitude at the combining node  128  according to the bit value (e.g., 0 or 1), as well as according to the weight of the corresponding weighting unit  126 , which in turn depends on the weight of the corresponding bit. The resulting RF analog signal  129  generated at the common adding point  128  therefore has a magnitude that is proportional to D BB-I . 
       FIG. 4  depicts one embodiment of a conversion unit  122 . The circuit depicted in  FIG. 4  corresponds to one of the conversion units  122  of  FIG. 3 . Therefore, when the input digital baseband value has N bits, N copies of the conversion unit  122  of  FIG. 4  are used to implement the In-phase upconverter  120  and N copies are used to implement the Quadrature upconverter  130 . 
     Conversion unit  122  comprises a first unit  180  and a separate second unit  190 . The conversion unit  122  of  FIG. 4  simultaneously uses LO and an inverted LO signal (xLO) in both branches to generate I p  and I n , each of which comprise a weighted average of the LO and xLO signals. More particularly, inputs  181   a ,  191   c  connect to a reference voltage V REF , e.g., ground, inputs  181   b ,  191   b  connect to LO, and inputs  181   c ,  191   a  connect to xLO. The inputs  181   a - 181   c  are input to the first unit  180 , where they are connected to respective inverters  182   a - c , which invert the respective input signals  181   a - c . The inputs  191   a - 191   c  are input to the second unit  190 , where they are connected to respective inverters  192   a - c , which invert the respective input signals  191   a - c . The output of each inverter  182   a - c ,  192   a - c  connects to a respective switch unit  184 ,  194 , which may, for example, comprise a transistor switch  183   a - c ,  193   a - c  for each inverter output. 
     Each switch unit  184 ,  194  in conversion unit  122  is controlled using the same data bit so that, for example, when the input data bit equals 0, switch units  184 ,  194  pass the inverted ground signals but do not pass the inverted LO/xLO signals. When the input data bit equals 1, switch units  184 ,  194  pass the inverted LO/xLO signals but do not pass the inverted ground signals. In this latter case, switches  183   b ,  183   c ,  193   a ,  193   b  are also controlled by the sign bit of the value. Table 3 shows one exemplary logic table applicable when the input data bit equals 1 when the set of inverters  186  and the set of inverters  196  invert by different amounts. 
                                 TABLE 3                          Sign Bit                                 1   0                                             Switch Unit 184 Output   Inverted xLO   Inverted LO           Switch Unit 194 Output   Inverted xLO   Inverted LO                        
Table 4 shows another exemplary logic table applicable when the input data bit equals 1 when the sets of inverters  186 ,  196  provide the same amount of inversion.
 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 4 
               
             
            
               
                   
                   
               
               
                   
                 Sign Bit 
                   
               
            
           
           
               
               
               
            
               
                   
                 1 
                 0 
               
               
                   
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Switch Unit 184 Output 
                 Inverted xLO 
                 Inverted LO 
               
               
                   
                 Switch Unit 194 Output 
                 Inverted LO 
                 Inverted xLO 
               
               
                   
                   
               
            
           
         
       
     
     The outputs of switch units  184 ,  194  respectively connect to the set of inverters  186 ,  196  connected in series, which buffer the signals output by the switch units  184 ,  194 . The sets of inverters  186 ,  196  may comprise an odd or even number of inverters, and each set  186 ,  196  may comprise the same number or a different number of inverters. For example, when switch units  184 ,  194  output the inverted LO signal and the inverted xLO signal, respectively, set  186  and set  196  may each comprise the same number of inverters (and likewise correspond to Table 3). Alternatively, one set, e.g., set  196 , may have an even number of more inverters than the other set, e.g., set  186 , to generate more delay in the ground unit  190  while still maintaining the presence of LO and xLO in the output signals. This alternative embodiment also corresponds to Table 3. In another embodiment, e.g., when switch units  184 ,  194  both output the inverted LO signal or the inverted xLO signal, one set of inverters, e.g., set  196 , may have an odd number of more inverters that the other set, e.g., set  186 , which effectively implements an additional logic inversion in that set of inverters  196  relative to the other set of inverters  186  (corresponds to Table 2). This extra logic inversion facilitates, e.g., outputting xLO from the set of inverters  196  while simultaneously outputting LO from the other set of inverters  186 , depending on the sign. Generating the weighted analog RF signal  125  in this manner, e.g., by using xLO and LO at the same time, enables the phase accuracy requirements for the LO and xLO signals to be relaxed. 
     The output of the each set of inverters  186 ,  196  connects to one plate of respective capacitors  188 ,  198 . The other plates of the capacitors  188 ,  198  are decoupled to produce a differential embodiment with separate and isolated first and second outputs I p  and I n . In this embodiment, both branches  180 ,  190  are equal, because both are shut down the same way, e.g., both have an input connected to the same DC reference voltage (e.g., ground) to enable both to disconnect from the LO/xLO signals to shut down to the same reference voltage. In the embodiment of  FIG. 4 , both branches  180 ,  190  shut down to a reference voltage of ground. It will be appreciated, however, that any DC reference voltage may be used. 
     The embodiment of  FIG. 4  uses the LO and xLO signals all the time, regardless of the sign. For example, when the bit does not shut down the branches  180 ,  190 , the sign in combination with the number of inverters in the sets of inverters  186 ,  196  controls one of the first and second units  180 ,  190  to output the inverted version of the LO signal and controls the other of the first and second units  180 ,  190  to output the inverted version of the xLO signal. Thus, both branches  180 ,  190  in the conversion unit  122  of  FIG. 4  use LO and xLO signals, depending on the phase/sign of the signal to be transmitted. As a result, the conversion unit  122  of  FIG. 4  does not require propagation delay matching for LO and xLO signals. For example, if the phase of the LO signal is 0°, the phase of the xLO signal should be 180°. It will be appreciated that the differential implementation of  FIG. 4  suppresses noise resulting from propagation delay matching, and therefore, relaxes the propagation delay requirements. 
       FIG. 5  depicts one exemplary In-phase amplifier  150  comprising a differential common source amplifier. It will be appreciated that a similar amplifier circuit may be used for the Quadrature amplifier  160 . When the amplifiers  150 ,  160  are enabled by out-of-phase signals at twice the RF (2LO) and the amplifier input signals are influenced by both the RF frequency and an inverted version of the RF frequency, e.g., LO and xLO, the amplifiers  150 ,  160  are alternately active. As a result, the amplifiers  150 ,  160 , the amplifier input signals, the enable signals, the cascade voltages V casc , and the bias voltage V bias  work together to produce the amplifier outputs shown in Table 1. For example, V bias  sets the bias point of In-phase amplifier  150  through the MOS switch transistors  152  operated in sync with incoming signals I p  and I n . Alternatively, it will be appreciated that the MOS switch transistors  152  may be replaced with a resistor to provide a constant DC path to the amplifier input. The 2LO signal drives transistors  154  to either be fully open or closed. I p  and I n  connect to the gates of the amplifying transistors  156 , which convert the input voltage to output current. While not explicitly shown, additional resistors may be included at the source of transistors  156  to improve the linearity of the voltage-to-current conversion provided by transistors  156 . Cascade transistors  158  isolate the amplifying transistors  156  from the output, which enables a higher amplifier power voltage associated with PWR 2  and helps make the voltage-to-current conversion more linear and more independent of the output voltage. 
     To further illustrate the operation of the amplifiers  150 ,  160 ,  FIGS. 6A and 6B  depict an exemplary signal diagram for the signals associated with the In-phase and Quadrature amplifiers  150 ,  160 .  FIG. 6A  represents the In-phase signals, while  FIG. 6B  represents the Quadrature signals. The LO-I and LO-Q signals are the In-phase and Quadrature radio frequency signals, respectively. The xLO-I and xLO-Q signals are respectively the inverse of the LO-I and LO-Q signals. The 2LO and x2LO signals are the enable signals for the In-phase and Quadrature amplifiers, respectively. I p  and I n  represent the In-phase output voltages of the digital-to-analog converter showing LO-I as the base radio frequency, where the amplitude is modulated by the In-phase data, and where I p  and I n  are phase-shifted with respect to each other by 180°. I p  and I n  return to the same voltage, e.g., V bias , when low; when high the amplitude reflects the In-phase data. Similarly, Q p  and Q n  represent the Quadrature output voltages of the digital-to-analog converter showing LO-Q as the base radio frequency, where Q p  and Q n  are phase-shifted by 180° and return to the same voltage, e.g., V bias , when low and reflect the Quadrature data when high. It will be appreciated that I p  and I n  have different amplitudes than Q p  and Q n  because the Quadrature data differs from the In-phase data. 
     I 1  and I 2  represent the In-phase amplifier output signals, e.g., the first and second output signals. Mathematically speaking, I 1  and I 2  represent the product of I p  and I n  with 2LO. I 1  has a first value derived from the In-phase data, then zero, then V bias , and then zero again. I 2  has a first value derived from V bias , then zero, then the In-phase data, and then zero again. Similarly, Q 1  and Q 2  represent the In-phase amplifier output signals, e.g., the first and second output signals. Mathematically speaking, Q 1  and Q 2  represent the product of Q p  and Q n  with x2LO. Q 1  has a first value derived from zero, then the Quadrature data, then zero, then V bias ·Q 2  has a first value derived from zero, then V bias , then zero, then the Quadrature data. Differential combiner  170  combines I 1  and I 2 , e.g., by subtracting I 2  from I 1 , in a first time period, and then combines Q 1  and Q 2 , e.g., by subtracting Q 2  from Q 1 , in a second time period, etc. 
       FIG. 7  depicts one exemplary differential combiner  170  comprising a double winding balun. A first end of the first winding  172  connects to the In-phase and Quadrature amplifiers  150 ,  160  so as to receive I 1  and Q 1 , while a second end of the first winding  172  connects to the In-phase and Quadrature amplifiers  150 ,  160  so as to receive I 2  and Q 2 . A first end of the second winding  174  provides the RF analog signal, which may for example be applied to an antenna, while a second end of the second winding  174  connects to ground. 
     It will be appreciated that other differential combiners may be used in the digital-to-analog upconverter disclosed herein. For example,  FIG. 8  shows an alternate differential combiner  170  comprising first and second LC resonators  176 ,  178  coupled by mutual inductance. When feeding differential current to the first and second LC resonators  176 ,  178 , parallel resonance with inductors occurs, where the effective value equals the original inductance multiplied by 1+k. When feeding a common-mode signal, the inductance value is multiplied by 1−k, and the resonance frequency is at a different frequency, which results in a low impedance at the desired frequency. If mutual coupling between the inductances is good, the parameter k approaches 1, and the difference between the common-mode impedance and the differential-mode impedance increases. 
     As depicted in  FIG. 1  and mentioned above, the upconversion module  110  may be powered by a first power supply (PWR 1 ), while the amplifier module  140  may be powered by a separate second power supply (PWR 2 ). The use of separate power supplies enables the upconversion module  110  and the amplifier module  140  to be driven differently, and possibly into different levels of compression, e.g., due to saturation. While compression effects may improve some performance parameters, e.g., noise performance, such compression effects generally degrade linearity. To compensate, digital-to-analog upconverter  100  may further include a pre-distortion module  102  disposed before the upconversion module  110 . Based on an expected distortion, the pre-distortion module  102  generates a pre-distorted baseband value {circumflex over (D)} BB  using any known means. It will be appreciated that the In-phase and Quadrature portions of the digital baseband value D BB  may be compensated separately to produce a pre-distorted In-phase baseband value {circumflex over (D)} BB-I  and/or a pre-distorted Quadrature baseband value {circumflex over (D)} BB-Q , as shown in  FIG. 9 . In any event, {circumflex over (D)} BB  instead of DBB is then used by the above-described procedures and applied to the above-described apparatuses. 
     By including the amplifiers  150 ,  160  between the upconversion module  110  and the differential combiner  170 , embodiments disclosed herein enable increasing the output power of the digital-to-analog upconverter  100  without polluting power supplies, and therefore, without deteriorating the noise performance. The amplifiers  150   160  may also use a separate power supply (PWR 2 ) than the upconversion module  110  (PWR 1 ), which enables the digital-to-analog upconverter  100  to use higher supply voltages for a final stage of the upconversion module  110  than prior art solutions, while still increasing the output power capability. In particular, the separate power supplies enable the last inverter stage of the each upconversion unit  122  to be driven with a large signal, which pushes it into deep compression, and therefore, improves noise performance. The herein described pre-distortion unit  102  further enables the digital-to-analog upconverter  100  to meet the desired linearity performance regardless of the compression. Finally, the 25/75 duty cycle of the amplifier output signals provides very good power efficiency. 
     The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.