Patent Publication Number: US-8976593-B2

Title: Nonvolatile semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of Korean Patent Application No. 10-2011-0037185, filed on Apr. 21, 2011, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Exemplary embodiments of the present invention relate to a nonvolatile semiconductor device, and more particularly, to a circuit for controlling a global word line in a nonvolatile semiconductor device. 
     2. Description of the Related Art 
     A semiconductor memory device is classified as volatile memory and nonvolatile memory according to whether data is retained when power is not supplied. A nonvolatile memory such as a flash memory is capable of recording and deleting data freely and retaining stored data without the supply of power. Specifically, since a NAND flash memory has a high degree of integration, the NAND flash memory has been widely used in various application fields for high capacity data storage. 
     In such a nonvolatile memory, it is necessary to perform an electrical erase and reprogramming process with respect to a designated unit of memory cells in order to change previously programmed data, differently from a volatile memory such as a dynamic random access memory (DRAM). More specifically, in order to program data in a memory cell in an initialized state and then change the data, a designated number of memory cells including the selected memory cell may be reinitialized through an electrical erase operation and subsequently the selected memory cell may be reprogrammed with the changed content. In general, a unit of memory cells performing the electrical erase is called a block, and a unit of memory cells performing data record, or more specifically, program, is called a page. Here, the “page” indicates a set of memory cells connected to one word line, and one block includes a plurality of (for example, 64 or 128) pages. 
       FIG. 1A  is a diagram illustrating a part of a memory cell array of an NAND flash memory device. 
     Referring to  FIG. 1A , a cell array of the NAND flash memory includes a plurality of cell strings  100  and  110 , and the cell string  100  includes a plurality of memory cells serially connected to one another between a drain select transistor  101  and a source select transistor  103 , and the cell string  110  includes a plurality of memory cells serially connected to one another between a drain select transistor  111  and a source select transistor  113 . The drain select transistors  101  and  111  and the source select transistors  103  and  113  are connected to a drain select line DSL and a source select line SSL, respectively, and the memory cells in the cell strings  100  and  110  are connected to one another through a plurality of word lines WL&lt; 0 &gt; to WL&lt;n&gt;. The cell strings  100  and  110  are selectively connected to bit lines BL through the drain select transistors  101  and  111 , and are selectively connected to a common source line CSL, which is connected to a ground voltage terminal, through the source select transistors  103  and  113 . The cell strings  100  and  110  connected to the bit lines BL are connected in parallel to the common source line CSL, thereby forming one memory cell block. 
     To perform program, read, and erase operations in a NAND flash memory device, a bias voltage suitable is applied for each operation to a selected word line. For example, in a program operation, a program voltage (for example, 10 V or more) is applied to a word line selected by an input row address, and a pass voltage (for example, 10 V or less) is applied to remaining word lines. Meanwhile, as the capacity and integration degree of a memory device are increased, to reduce a disturbance phenomenon to an adjacent word line or a bit line (or a memory cell connected to the bit line), pass voltages at different voltage levels are applied to word lines within a designated distance from the word line selected in the program operation. The application of the pass voltages will be called a “boosting option.” 
       FIG. 1B  is a diagram illustrating voltages applied to the word lines of  FIG. 1A  in a program operation. 
     Referring to  FIG. 1B , a program voltage VPGM is applied to a word line WL&lt;A&gt; selected by an input row address A in the program operation, and different voltages VBST 1 , VBST 2  and VBST 3  are applied to word lines WL&lt;A+3&gt; to WL&lt;A+1&gt; and WL&lt;A−1&gt; to WL&lt;A−3&gt; within a designated distance from the selected word line WL&lt;A&gt; according to the distance to the selected word line WL&lt;A&gt; because the above-mentioned boosting option is applied the word lines. On the other hand, a pass voltage VPASS is applied to remaining word lines WL&lt;n&gt; to WL&lt;A+4&gt; and WL&lt;A−4&gt; to WL&lt; 0 &gt;. 
     Since the number of word lines of a NAND flash memory may be 32 to 128 (gradually increased) per one block, and one NAND flash memory includes 1000 or more blocks, the total number of word lines is 32,000 or more at minimum. In order to select one of the 32,000 or more word lines and directly apply a bias voltage to the selected word line, switches corresponding to the total 32,000*(the number of voltage to be generated) are required, which makes the configuration of a chip difficult. 
     In order to solve such a problem, a global word line (GWL) is used. In a NAND flash memory, while one block is operating, other blocks do not operate. In this regard, a two-stage configuration scheme is used where a global word line is generated as a sample set of word lines provided in one block, a voltage used for each operation is first applied to the global word line, and subsequently transferred to word lines in each block. 
       FIG. 2  is a diagram illustrating a word line control circuit of an NAND flash memory device according to the conventional art, and  FIGS. 3 and 4  are detailed diagrams illustrating the row selection unit  105  of  FIG. 2 . 
     Referring to  FIGS. 2 to 4 , the conventional NAND flash memory device includes global word lines GWL&lt; 0 : 127 &gt;, a voltage pump  101 , a row decoder unit  103 , a row selection unit  105 , a block decoder unit  107 , a block selection unit  109 , and a cell array area  111 . The cell array area  111  includes a plurality of memory blocks BLOCK_ 0  to BLOCK_n, and it is assumed that the number of word lines in one block is 128. Thus, the number of the global word lines GWL&lt; 0 : 127 &gt; is also 128. 
     The voltage pump  101  generates a plurality of voltages V&lt; 0 : 7 &gt; used for applying voltages at different levels to word lines in program and read operations and the like. It is assumed that the number of the different voltages generated by the voltage pump  101  is 8. 
     The row decoder unit  103  receives a row address RADD for each operation, and generates control signals SWCTRL 3 &lt; 0 : 127 &gt; for applying different voltages to a word line selected by the row address RADD, word lines employing the boosting operation, and remaining word lines. 
     Referring to  FIG. 3 , the selection unit  105  may include a plurality of switch units SW 0  to SW 127  for selecting one of the voltages V&lt; 0 : 7 &gt; generated by the voltage pump  101  and applying the selected voltage to the global word lines GWL&lt; 0 &gt; to GWL&lt; 127 &gt;. In detail, the switch units SW 0  to SW 127  select one of the eight voltages V&lt; 0 &gt; to V&lt; 7 &gt; in response to the control signals SWCTRL&lt; 0 &gt; to SWCTRL&lt; 127 &gt; generated by the row decoder unit  103  and apply the selected voltage to the global word lines GWL&lt; 0 &gt; to GWL&lt; 127 &gt;, which are connected to the switch units SW 0  to SW 127 , respectively. Thus, each switch unit includes eight switches, and a control signal (for example, the control signal SWCTRL&lt; 0 &gt; input to the switch unit SW 0 ) that controls each switch unit is represented by 3 bits or more. 
     The block decoder unit  107  receives a block address BLADD and generates block control signals BLCTRL&lt; 0 :n&gt; for selecting blocks corresponding to the block address BLADD, and the block selection unit  109  connects the blocks corresponding to the input block address BLADD to the global word lines GWL&lt; 0 &gt; to GWL&lt; 127 &gt; in response to the block control signals BLCTRL&lt; 0 :n&gt;. In this way, voltages applied to the global word lines GWL&lt; 0 &gt; to GWL&lt; 127 &gt; are transferred to word lines in the selected block. 
     However, referring to  FIG. 4 , one switch unit SW 0  connected to one global word line GWL&lt; 0 &gt; includes eight switches that select one of the eight different voltages V&lt; 0 &gt; to V&lt; 7 &gt;. Therefore, the 128 switch units SW 0  to SW 127  connected to the 128 global word lines GWL&lt; 0 : 127 &gt; include 1024 (=128*8) switches, and control signals of 384 (=128*3) bits are implemented to control the switches. The number of the switches is increased as the number of word lines in one block is increased or the number of bias voltages is increased. Furthermore, if the number of the switches is increased, since the number of the control signals for controlling the switches is also increased, they occupy a large area in a memory device as the memory device is highly integrated with high capacity. 
     SUMMARY 
     An embodiment of the present invention is directed to a nonvolatile semiconductor device capable of reducing the overall circuit area by reducing the number of switches included for selectively applying a plurality of voltages to global word lines. 
     In accordance with an embodiment of the present invention, a nonvolatile memory device includes: a plurality of global word lines; a voltage pump configured to generate a plurality of voltages having different voltage levels; a control unit configured to divide the plurality of global word lines into a first group and a second group in response to an input row address and generate at least first, second, and third control signals for applying voltages corresponding to the first and second groups; a first selection unit configured to output at least two different voltages among the plurality of voltages generated by the voltage pump that are to be applied to global word lines of the first group, in response to the first control signals; a second selection unit configured to output a voltage among the plurality of voltages generated by the voltage pump that is to be applied to global word lines of the second group, in response to the second control signal; and a third selection unit configured to apply output voltages of the first selection unit to the global word lines of the first group, and apply an output voltage of the second selection unit to the global word lines of the second group in response to the third control signals. 
     The control unit may set global word lines of the plurality of global word lines that are spaced within a distance from a global word line corresponding to the input row address, as the first group, and set remaining global word lines as the second group. 
     In accordance with an embodiment of the present invention, a nonvolatile memory device includes: a voltage pump configured to generate a plurality of voltages having different voltage levels; N first switch units configured to select one of the plurality of voltages generated by the voltage pump and output a selected voltage as a first group voltage in response to an input row address; a second switch unit configured to select one of the plurality of voltages generated by the voltage pump and output a selected voltage as a second group voltage; a plurality of switch groups including N third switch units, respectively; and a plurality of global word lines connected to the third switch units, respectively, wherein the N third switch units included in each of the plurality of switch groups correspond to the N first switch units respectively, select either the first group voltage or the second group voltage in response to the input row address, and apply a selected voltage to connected global word lines. 
     In accordance with an embodiment of the present invention, A nonvolatile memory device comprising: a plurality of global word lines; a control unit configured to generate first to third control signals in response to an inputted row address; a first selection unit configured to select one or more voltages among a plurality of voltages of different levels and transfer the selected voltages to one or more first lines in response to the first control signal; a second selection signal configured to select one voltage among the multiple voltages in response to the second control signal; and a third selection unit configured to select one or more global word lines among the multiple global word lines and transfer voltages of the one or more first lines and transfer a voltage of the second line to global word lines other than the selected one or more global word lines in response to the third control signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a diagram illustrating a part of a memory cell array of an NAND flash memory device. 
         FIG. 1B  is a diagram illustrating voltages applied to the word lines of  FIG. 1A  in a program operation. 
         FIG. 2  is a diagram illustrating a word line control circuit of an NAND flash memory device according to the conventional art. 
         FIGS. 3 and 4  are detailed diagrams illustrating the row selection unit  105  of  FIG. 2 . 
         FIG. 5  is a configuration diagram of a nonvolatile semiconductor device in accordance with an embodiment of the present invention. 
         FIG. 6  is a detailed configuration diagram illustrating the first selection unit  505  and the second selection unit  507  of  FIG. 5 . 
         FIG. 7  is a detailed configuration diagram illustrating the third selection unit  509  of  FIG. 5 . 
         FIG. 8  is a diagram illustrating a voltage switching operation of a global word line in a program operation of a nonvolatile semiconductor device in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
       FIG. 5  is a configuration diagram of a nonvolatile semiconductor device in accordance with an embodiment of the present invention. 
     Referring to  FIG. 5 , the nonvolatile semiconductor device in accordance with the embodiment of the present invention includes a plurality of global word lines GWL&lt; 0 : 127 &gt;, a voltage pump  501  configured to generate a plurality of voltages V&lt; 0 : 7 &gt; at different voltage levels, a control unit  503 , a first selection unit  505 , a second selection unit  507 , and a third selection unit  509 . The control unit  503  is configured to divide the plurality of global word lines GWL&lt; 0 : 127 &gt; into a first group and a second group in response to an input row address RADD, and generate control signals SWCTRL 1 &lt; 0 : 15 &gt;, SWCTRL 2 , and SWCTRL 3 &lt; 0 : 127 &gt; that apply voltages corresponding to the groups. The first selection unit  505  is configured to output two or more different voltages, which are to be applied to global word lines of the first group (hereinafter, referred to as first group of global word lines), among the plurality of voltages V&lt; 0 : 7 &gt; generated by the voltage pump  501  in response to the control signals SWCTRL 1 &lt; 0 : 15 &gt;. The second selection unit  507  is configured to output one voltage, which is to be applied to global word lines of the second group (hereinafter, referred to as second group of global word lines), among the plurality of voltages V&lt; 0 : 7 &gt; in response to the control signal SWCTRL 2 . The third selection unit  509  is configured to apply the output voltage of the first selection unit  505  to the first group of global word lines and apply the output voltage of the second selection unit  507  to the second group of global word lines in response to the control signals SWCTRL 3 &lt; 0 : 127 &gt;. 
     Furthermore, the nonvolatile semiconductor device in accordance with the present embodiment may further include a block decoder unit  107 , a block selection unit  109 , and a cell array area  111 . The block decoder unit  107  is configured to receive a block address BLADD and generate block control signals BLCTRL&lt; 0 :n&gt; that selects blocks corresponding to the block address BLADD. The block selection unit  109  is configured to connect the blocks corresponding to the input block address BLADD to the global word lines GWL&lt; 0 &gt; to GWL&lt; 127 &gt; in response to the block control signals BLCTRL&lt; 0 :n&gt;. The cell array area  111  includes a plurality of blocks BLOCK_ 0  to BLOCK_n. 
     Here, it is assumed that the number of word lines in one block is 128. Thus, the number of the global word lines GWL&lt; 0 : 127 &gt; is also 128. Furthermore, it is assumed that the voltage pump  501  generates eight voltages V&lt; 0 : 7 &gt; at different voltage levels. However, the number of word lines per one block and the number of the voltages generated by the voltage pump  501  may be changed according to different designs. 
     According to the conventional method (refer to  FIG. 2 ) for applying voltages to the global word lines GWL&lt; 0 : 127 &gt;, a word line selected by an input row address RADD, word lines adjacent to the word line employing the boosting option, and remaining word lines are controlled with the same switch structure. More specifically, since eight switches that selectively apply one of the eight different voltages generated by the voltage pump  101  are connected to all the global word lines GWL&lt; 0 : 127 &gt; in sets, respectively, a large number of switches and control signals for controlling the switches are included as described above. 
     However, in the present invention, a two-stage switch structure is provided between the voltage pump  501  and the global word lines GWL&lt; 0 : 127 &gt; to reduce the total number of switches. In detail, by means of the first selection unit  505  and the second selection unit  507 , all the global word lines GWL&lt; 0 : 127 &gt; are classified into a first group including a word line selected by the input row address RADD and word lines employing the boosting option and receiving different voltages, and a second group not employing the boosting option and receiving the same voltage. The third selection unit  509  is directly connected to the global word lines GWL&lt; 0 : 127 &gt; to apply a plurality of voltages output from the first selection unit  505  to the first group of global word lines while applying a voltage output from the second selection unit  507  to the second group of global word lines. 
       FIG. 6  is a detailed configuration diagram illustrating the first selection unit  505  and the second selection unit  507  of  FIG. 5 , and  FIG. 7  is a detailed configuration diagram illustrating the third selection unit  509  of  FIG. 5 . With reference to  FIGS. 6 and 7 , the above-mentioned two-stage switch structure will be described in detail. 
     Referring to  FIGS. 6 and 7 , the first selection unit  505  includes a plurality of first switch units SW 1 _ 0  to SW 1 _ 15  that provide voltages to the first group of global word lines, and the second selection unit  507  includes a second switch unit SW 2  that provides a voltage to the second group of global word lines. The third selection unit  509  includes a plurality of third switch units SW 3 _ 0  to SW 3 _ 127  connected to the global word lines GWL&lt; 0 : 127 &gt; to selectively apply one of the output voltages of the first switch units SW 1 _ 0  to SW 1 _ 15  or the output voltage of the second switch unit SW 2  to the global word lines GWL&lt; 0 : 127 &gt;. 
     Here, it is assumed that, among all the 128 global word lines GWL&lt; 0 : 127 &gt;, the number of global word lines belonging to the first group is 16 and the remaining 112 global word lines belong to the second group. Thus, the first selection unit  505  includes the 16 first switch units SW 1 _ 0  to SW 1 _ 15  that output voltages to be applied to the first group of global word lines, and the output voltages of the switch units are transferred to the third selection unit  509  through 16 selection voltage lines PSL&lt; 0 &gt; to PSL&lt; 15 &gt;. However, the number of the word lines of the first group and the number of the switch units in the first selection unit  505  may be changed according to different designs. 
     The same voltage is applied to the remaining 112 second group global word lines, and the voltage output from the second switch unit SW 2  is transferred to the third selection unit  509  through a non-selection voltage line PUL. 
     The control unit  503  generates the control signals SWCTRL 1 &lt; 0 : 15 &gt; that are applied to the first selection unit  505  and the control signal SWCTRL 2  that is applied to the second selection unit  507  in response to the input row address RADD. 
     The plurality of first switch units SW 1 _ 0  to SW 1 _ 15  in the first selection unit  505  and the second switch unit SW 2  in the second selection unit  507  receive the eight different voltages V&lt; 0 &gt; to V&lt; 7 &gt; generated by the voltage pump  501 , and the first switch units SW 1 _ 0  to SW 1 _ 15  select one of the eight voltages V&lt; 0 &gt; to V&lt; 7 &gt; to output the selected voltage to the selection voltage lines PSL&lt; 0 &gt; to PSL&lt; 15 &gt; in response to the control signals SWCTRL 1 &lt; 0 &gt; to SWCTRL 1 &lt; 15 &gt;, respectively, and the second switch unit SW 2  selects one of the eight voltages V&lt; 0 &gt; to V&lt; 7 &gt; to output the selected voltage to the non-selection voltage line PUL in response to the control signal SWCTRL 2 . 
     Referring to  FIG. 6 , the first switch units SW 1 _ 0  to SW 1 _ 15  and the second switch unit SW 2  may include eight switches, respectively, and a control signal (for example, control signal SWCTRL 1 &lt; 0 &gt; input to the switch unit SW 1 _ 0 ) input to each switch unit may be represented by 3 bits at minimum to control the eight switches. The control method of the first switch units SW 1 _ 0  to SW 1 _ 15  and the second switch unit SW 2  using the control signals SWCTRL 1 &lt; 0 &gt; to SWCTRL 1 &lt; 15 &gt; and SWCTRL 2  will be described in detail with reference to  FIG. 8 . 
     Referring to  FIG. 7 , the third selection unit  509  includes 128 third switch units SW 3 _ 0  to SW 3 _ 127  connected to the 128 global word lines GWL&lt; 0 : 127 &gt;, respectively. The 128 third switch units SW 3 _ 0  to SW 3 _ 127  are classified into eight switch groups  701  to  708 , and each of the eight switch groups  701  to  708  includes 16 third switch units SW 3 _ 0  to SW 3 _ 15 , SW 3 _ 16  to SW 3 _ 31 , and SW 3 _ 112  to SW 3 _ 127 . The 16 third switch units SW 3 _ 0  to SW 3 _ 15 , SW 3 _ 16  to SW 3 _ 31 , and SW 3 _ 112  to SW 3 _ 127  in each of the eight switch groups  701  to  708  correspond to the 16 first switch units SW 1 _ 0  to SW 1 _ 15  of the first selection unit  505  in a one-to-one manner. 
     In detail, the output voltage of the first switch unit SW 1 _ 0  of the first selection unit  505  is input to the third switch units SW 3 _ 0 , SW 3 _ 16 , . . . , SW 3 _ 112  of the switch groups  701  to  708  through the first selection voltage line PSL&lt; 0 &gt;, and the output voltage of the first switch unit SW 1 _ 1  of the first selection unit  505  is input to the third switch units SW 3 _ 1 , SW 3 _ 17 , . . . , SW 3 _ 113  of the switch groups  701  to  708  through the second selection voltage line PSL&lt; 1 &gt;. More specifically, the selection voltage line PSL&lt; 0 &gt; is connected to the switch units SW 3 _ 0 , SW 3 _ 16 , SW 3 _ 32 , . . . , SW 3 _ 112 , the selection voltage line PSL&lt; 1 &gt; is connected to the switch units SW 3 _ 1 , SW 3 _ 17 , SW 3 _ 33 , . . . , SW 3 _ 113 , and the selection voltage line PSL&lt; 2 &gt; is connected to the switch units SW 3 _ 2 , SW 3 _ 18 , SW 3 _ 34 , . . . , SW 3 _ 114  (the selection voltage lines PSL&lt; 3 &gt; to PSL&lt; 15 &gt; are connected in the same manner). The selection units  505  and  509  are connected to each other in such a manner that the first selection unit  505  is matched with the switch groups  701  to  708  of the third selection unit  509  in a one-to-one manner. 
     The output voltage of the second selection unit  507  is commonly input to the 128 third switch units SW 3 _ 0  to SW 3 _ 127  through the non-selection voltage line PUL. Thus, the third switch units SW 3 _ 0  to SW 3 _ 127  each receive two voltages: one of the output voltages of the first selection unit  505  and the output voltage of the second selection unit  507 . 
     The control method of the third selection unit  509  will be described below. The control unit  503  generates the control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 127 &gt; and inputs the control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 127 &gt; to the third switch units SW 3 _ 0  to SW 3 _ 127  in response to the input row address RADD. Each of the control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 127 &gt; may be a 1-bit signal having a logic ‘high’ or ‘low’ value. 
     The third switch units SW 3 _ 0  to SW 3 _ 127  select one of the two input voltages in response to the control signals SWCTRL 3 &lt; 0 : 127 &gt; and apply the selected voltage to the global word lines GWL&lt; 0 : 127 &gt; connected to the third switch units SW 3 _ 0  to SW 3 _ 127 . The third switch units SW 3 _ 0  to SW 3 _ 127  select the output voltages of the first selection unit  505  when the applied control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 127 &gt; have a ‘high’ value, and the third switch units SW 3 _ 0  to SW 3 _ 127  select the output voltage of the second selection unit  507  when the applied control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 127 &gt; have a ‘low’ value. The selected output voltage is applied to the global word lines GWL&lt; 0 : 127 &gt; for each of the third switch units SW 3 _ 0  to SW 3 _ 127 . 
     For example, when the global word line selected by the input row address RADD is GWL&lt; 10 &gt;, the control signals SWCTRL 3 &lt; 3 &gt; to SWCTRL 3 &lt; 18 &gt;, which are applied to the 16 third switch units SW 3 _ 3  to SW 3 _ 18  connected to the 16 global word lines GWL&lt; 3 &gt; to GWL&lt; 18 &gt; within a designated distance from the global word line GWL&lt; 10 &gt;, may have a ‘high’ value, and the remaining control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 2 &gt;, SWCTRL 3 &lt; 19 &gt; to SWCTRL 3 &lt; 127 &gt; may have a ‘low’ value. Hereafter, the control operation of the third selection unit  509  will be described in further detail with reference to  FIG. 8 . 
       FIG. 8  is a diagram illustrating a voltage switching operation of a global word line in the program operation of the nonvolatile semiconductor device in accordance with the present invention. 
     Referring to  FIG. 8 , when a global word line selected by the input row address RADD is GWL&lt; 7 &gt;, the global word lines GWL&lt; 0 &gt; to GWL&lt; 15 &gt; are respectively connected to the selection voltage lines PSL&lt; 0 &gt; to PSL&lt; 15 &gt; as a first group, and the remaining global word lines GWL&lt; 16 &gt; to GWL&lt; 127 &gt; are connected to the non-selection voltage line PUL as a second group. 
     At this time, the control signals SWCTRL 1 &lt; 0 &gt; to SWCTRL 1 &lt; 15 &gt; applied to the first switch units SW 1 _ 0  to SW 1 _ 15  are controlled such that the control signal SWCTRL 1 &lt; 7 &gt; selects a program voltage VPGM (for example, V&lt; 0 &gt;), the control signals SWCTRL 1 &lt; 5 &gt;, SWCTRL 1 &lt; 6 &gt;, SWCTRL 1 &lt; 8 &gt;, and SWCTRL 1 &lt; 9 &gt; select a first boosting voltage VBST 1  (for example, V&lt; 1 &gt;), the control signals SWCTRL 1 &lt; 2 &gt;, SWCTRL 1 &lt; 3 &gt;, SWCTRL 1 &lt; 4 &gt;, SWCTRL 1 &lt; 10 &gt;, SWCTRL 1 &lt; 11 &gt;, and SWCTRL 1 &lt; 12 &gt; select a second boosting voltage VBST 2  (for example, V&lt; 2 &gt;), and the control signals SWCTRL 1 &lt; 0 &gt;, SWCTRL 1 &lt; 1 &gt;, SWCTRL 1 &lt; 13 &gt;, SWCTRL 1 &lt; 14 &gt;, and SWCTRL 1 &lt; 15 &gt; select a third boosting voltage VBST 3  (for example, V&lt; 3 &gt;). The control signal SWCTRL 2  applied to the second switch unit SW 2  is controlled to select a pass voltage VPASS (for example, V&lt; 4 &gt;). The control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 127 &gt; applied to the third switch units SW 3 _ 0  to SW 3 _ 127  are controlled such that the control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 15 &gt; select the output voltages PSL&lt; 0 &gt; to PSL&lt; 15 &gt; of the first switch units SW 1 _ 0  to SW 1 _ 15 , and the control signals SWCTRL 3 &lt; 16 &gt; to SWCTRL 3 &lt; 127 &gt; select the output voltage PUL of the second switch unit SW 2 . Thus, the voltages of the selection voltage lines PSL&lt; 0 &gt; to PSL&lt; 15 &gt; are respectively applied to the global word lines GWL&lt; 0 &gt; to GWL&lt; 15 &gt;, and the voltage of the non-selection voltage line PUL is applied to the global word lines GWL&lt; 16 &gt; to GWL&lt; 127 &gt;. 
     When a global word line selected by the input row address RADD is GWL&lt; 8 &gt;, the global word lines GWL&lt; 1 &gt; to GWL&lt; 16 &gt; are respectively connected to the selection voltage lines PSL&lt; 1 &gt; to PSL&lt; 15 &gt; and PSL&lt; 0 &gt; as a first group, and the remaining global word lines GWL&lt; 0 &gt; and GWL&lt; 17 &gt; to GWL&lt; 127 &gt; are connected to the non-selection voltage line PUL as a second group. 
     At this time, the control signals SWCTRL 1 &lt; 0 &gt; to SWCTRL 1 &lt; 15 &gt; applied to the first switch units SW 1 _ 0  to SW 1 _ 15  are controlled such that the control signal SWCTRL 1 &lt; 8 &gt; selects the program voltage VPGM (for example, V&lt; 0 &gt;), the control signals SWCTRL 1 &lt; 6 &gt;, SWCTRL 1 &lt; 7 &gt;, SWCTRL 1 &lt; 9 &gt;, and SWCTRL 1 &lt; 10 &gt; select the first boosting voltage VBST 1  (for example, V&lt; 1 &gt;), the control signals SWCTRL 1 &lt; 3 &gt;, SWCTRL 1 &lt; 4 &gt;, SWCTRL 1 &lt; 5 &gt;, SWCTRL 1 &lt; 11 &gt;, SWCTRL 1 &lt; 12 &gt;, and SWCTRL 1 &lt; 13 &gt; select the second boosting voltage VBST 2  (for example, V&lt; 2 &gt;), and the control signals SWCTRL 1 &lt; 1 &gt;, SWCTRL 1 &lt; 2 &gt;, SWCTRL 1 &lt; 14 &gt;, SWCTRL 1 &lt; 15 &gt;, and SWCTRL 1 &lt; 0 &gt; select the third boosting voltage VBST 3  (for example, V&lt; 3 &gt;). The control signal SWCTRL 2  applied to the second switch unit SW 2  is controlled to select the pass voltage VPASS (for example, V&lt; 4 &gt;). The control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 127 &gt; applied to the third switch units SW 3 _ 0  to SW 3 _ 127  are controlled such that the control signals SWCTRL 3 &lt; 1 &gt; to SWCTRL 3 &lt; 16 &gt; sequentially select the output voltages PSL&lt; 1 &gt; to PSL&lt; 15 &gt;, and PSL&lt; 0 &gt; of the first switch units SW 1 _ 1  to SW 1 _ 15 , and SW 1 _ 0 , and the control signals SWCTRL 3 &lt; 0 &gt; and SWCTRL 3 &lt; 17 &gt; to SWCTRL 3 &lt; 127 &gt; select the output voltage PUL of the second switch unit SW 2 . Thus, the voltages of the selection voltage lines PSL&lt; 1 &gt; to PSL&lt; 15 &gt;, and PSL&lt; 0 &gt; are sequentially applied to the global word lines GWL&lt; 1 &gt; to GWL&lt; 16 &gt;, and the voltage of the non-selection voltage line PUL is applied to the global word lines GWL&lt; 0 &gt;, and GWL&lt; 16 &gt; to GWL&lt; 127 &gt;. 
     When a global word line selected by the input row address RADD is GWL&lt; 9 &gt;, the global word lines GWL&lt; 2 &gt; to GWL&lt; 17 &gt; are sequentially connected to the selection voltage lines PSL&lt; 2 &gt; to PSL&lt; 15 &gt;, PSL&lt; 0 &gt;, and PSL&lt; 1 &gt; as a first group, and the remaining global word lines GWL&lt; 0 &gt;, GWL&lt; 1 &gt;, and GWL&lt; 18 &gt; to GWL&lt; 127 &gt; are connected to the non-selection voltage line PUL as a second group. 
     At this time, the control signals SWCTRL 1 &lt; 0 &gt; to SWCTRL 1 &lt; 15 &gt; applied to the first switch units SW 1 _ 0  to SW 1 _ 15  are controlled such that the control signal SWCTRL 1 &lt; 9 &gt; selects the program voltage VPGM (for example, V&lt; 0 &gt;), the control signals SWCTRL 1 &lt; 7 &gt;, SWCTRL 1 &lt; 8 &gt;, SWCTRL 1 &lt; 10 &gt;, and SWCTRL 1 &lt; 11 &gt; select the first boosting voltage VBST 1  (for example, V&lt; 1 &gt;), the control signals SWCTRL 1 &lt; 4 &gt;, SWCTRL 1 &lt; 5 &gt;, SWCTRL 1 &lt; 6 &gt;, SWCTRL 1 &lt; 12 &gt;, SWCTRL 1 &lt; 13 &gt;, and SWCTRL 1 &lt; 14 &gt; select the second boosting voltage VBST 2  (for example, V&lt; 2 &gt;), and the control signals SWCTRL 1 &lt; 2 &gt;, SWCTRL 1 &lt; 3 &gt;, SWCTRL 1 &lt; 15 &gt;, SWCTRL 1 &lt; 0 &gt;, and SWCTRL 1 &lt; 1 &gt; select the third boosting voltage VBST 3  (for example, V&lt; 3 &gt;). The control signal SWCTRL 2  applied to the second switch unit SW 2  is controlled to select the pass voltage VPASS (for example, V&lt; 4 &gt;). The control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 127 &gt; applied to the third switch units SW 3 _ 0  to SW 3 _ 127  are controlled such that the control signals SWCTRL 3 &lt; 2 &gt; to SWCTRL 3 &lt; 17 &gt; sequentially select the output voltages PSL&lt; 2 &gt; to PSL&lt; 15 &gt;, PSL&lt; 0 &gt;, and PSL&lt; 1 &gt; of the first switch units SW 1 _ 2  to SW 1 _ 15 , SW 1 _ 0 , and SW 1 _ 1 , and the control signals SWCTRL 3 &lt; 0 &gt;, SWCTRL 3 &lt; 1 &gt;, and SWCTRL 3 &lt; 18 &gt; to SWCTRL 3 &lt; 127 &gt; select the output voltage PUL of the second switch unit SW 2 . Thus, the voltages of the selection voltage lines PSL&lt; 2 &gt; to PSL&lt; 15 &gt;, PSL&lt; 0 &gt;, and PSL&lt; 1 &gt; are sequentially applied to the global word lines GWL&lt; 2 &gt; to GWL&lt; 17 &gt;, and the voltage of the non-selection voltage line PUL is applied to the global word lines GWL&lt; 0 &gt;, GWL&lt; 1 &gt;, and GWL&lt; 16 &gt; to GWL&lt; 127 &gt;. 
     In this way, the above-mentioned two-stage switch structure can be achieved in such a manner that whenever the input row address RADD is increased by 1, global word lines receiving the output voltages PSL&lt; 0 &gt; to PSL&lt; 15 &gt; of the first selection unit  505  are rotated one by one from the top to the bottom. 
     In such a case, in relation to the total number of switches included in the first to third selection units  505 ,  507 , and  509 , 128 (16*8) switches, 8 (1*8) switches, and 256 (128*2) switches are respectively included in the first to third selection units  505 ,  507 , and  509 , more specifically, only the total 392 switches are included. Furthermore, in relation to the total bit number of control signals for controlling the switches, 48 (16*3) bits, 3 (1*3) bits, and 128 (128*1) bits are respectively included in the first to third selection units  505 ,  507 , and  509 , more specifically, only the total 179 bits are included. 
     Consequently, as compared with the conventional art (referring to  FIGS. 2 to 4 , the total 1024 switches and the total 384 bits are included), since the same function can be performed using a significantly reduced number of switches and control signals, the area and complexity of the nonvolatile memory device may be reduced. 
     Referring back to  FIGS. 5 to 7 , a nonvolatile memory device in accordance with another embodiment of the present invention is described. 
     Referring to  FIG. 5 , the nonvolatile memory device includes a plurality of global word lines GWL&lt; 0 : 127 &gt;, a control unit  503 , a first selection unit  505 , a second selection unit  507 , a third selection unit  509 , and a voltage pump  501 . The control unit  503  generates first to third control signals SWCTRL 1 &lt; 0 : 15 &gt;, SWCTRL 2  and SWCTRL 3 &lt; 0 : 127 &gt; in response to an inputted row address RADD. The first selection unit  505  selects one or more voltages among multiple voltages V&lt; 0 : 7 &gt; having different levels and transfers the selected voltages to one or more first lines PSL&lt; 0 : 15 &gt; in response to the first control signal SWCTRL 1 &lt; 0 : 15 &gt;. The second selection unit  507  selects one voltage among the multiple voltages V&lt; 0 : 7 &gt; and transfers the selected voltage to a second line PUL in response to the second control signal SWCTRL 2 . The third selection unit  509  selects one or more global lines among the multiple global word lines GWL&lt; 0 : 127 &gt; and transfers a voltage of the one or more first lines PSL&lt; 0 : 15 &gt; in response to the third control signal SWCTRL 3 &lt; 0 : 127 &gt;, and transfers the voltage of the second line PUL to the global word lines other than the selected one or more global word lines. The voltage pump  501  generates the multiple voltages V&lt; 0 : 7 &gt;. Here, the first lines PSL&lt; 0 : 15 &gt; correspond to the aforementioned selection voltage lines PSL&lt; 0 : 15 &gt;, and the second line PUL corresponds to the aforementioned non-selection voltage line PUL. 
     Also, the nonvolatile memory device in accordance with the embodiment of the present invention may further include a block decoder unit  107 , a block selection unit  109 , and a cell array area  111 . The block decoder unit  107  is configured to receive a block address BLADD and generate block control signals BLCTRL&lt; 0 :n&gt; that selects blocks corresponding to the block address BLADD. The block selection unit  109  is configured to connect the blocks corresponding to the input block address BLADD to the global word lines GWL&lt; 0 &gt; to GWL&lt; 127 &gt; in response to the block control signals BLCTRL&lt; 0 :n&gt;. The cell array area  111  includes a plurality of blocks BLOCK_ 0  to BLOCK_n. 
     Here, it is assumed that the number of word lines in one block is 128. Thus, the number of the global word lines GWL&lt; 0 : 127 &gt; is also 128. Also, it is assumed that the voltage pump  501  generates eight voltages V&lt; 0 : 7 &gt; at different voltage levels. However, the number of the word lines per block and the number of the voltages generated by the voltage pump  501  may be changed according to design. 
     In the embodiment of the present invention, a two-stage switch structure is provided between the voltage pump  501  and the global word lines GWL&lt; 0 : 127 &gt; to reduce the total number of switches. To be specific, the word line selected by an inputted row address RADD among the multiple global word lines GWL&lt; 0 : 127 &gt; and a boosting option are applied to the one or more first lines PSL&lt; 0 : 15 &gt;, and the first selection unit  505  transfers one or more voltages to be applied to the global word lines of different voltage levels. The second selection unit  507  transfers one voltage to be applied to the global word lines having the same voltage because no boosting option is applied among the multiple global word lines GWL&lt; 0 : 127 &gt; to the second line PUL. 
     Subsequently, the third selection unit  509  selects one or more global word lines to which the global word line corresponding to the inputted row address RADD and a boosting option are applied and transfers the voltages of the one or more first lines PSL&lt; 0 : 15 &gt;, and transfers the voltage of the second line PUL to the global word line other than the selected one or more global word lines. 
     Since one or more global word lines to which the boosting option is applied are global word lines that are closest to the global word line designated by the inputted row address RADD, the third selection unit  509  may select the global word line designated by the inputted row address RADD and the global word lines that are the global word line designated by the inputted row address RADD. 
     The first selection unit  505  includes one or more first switch units SW 1 _ 0  to SW 1 _ 15  that respectively correspond to the one or more first lines PSL&lt; 0 : 15 &gt;, and the second selection unit  507  includes a second switch unit SW 2  for selecting one voltage among the multiple voltages V&lt; 0 : 7 &gt; and transferring it to the second line PUL. The third selection unit  509  includes a plurality of third switch units SW 3 _ 0  to SW 3 _ 127  that respectively correspond to the multiple global word lines GWL&lt; 0 : 127 &gt;. 
     Here, it is assumed that the number of global word lines selected by the third selection unit  509  among the 128 global word lines GWL&lt; 0 : 127 &gt; is 16, and the other 116 are unselected global word lines. Therefore, the first selection unit  505  includes 16 first switch units SW 1 _ 0  to SW 1 _ 15  that respectively correspond to the 16 first lines PSL&lt; 0 : 15 &gt; for transferring voltages to be applied to the 16 global word lines selected by the third selection unit  509 , respectively. 
     The third selection unit  509  transfers voltages of the 16 first lines PSL&lt; 0 : 15 &gt; to the 16 global word lines selected among the global word lines GWL&lt; 0 : 127 &gt;. Here, the number of global word lines selected by the third selection unit  509  and the number of switch units inside the first selection unit  505  may be different according to design. An identical voltage is applied to the other 112 global word lines that are not selected by the third selection unit  509 , and the voltage to be applied to the 112 global word lines is selected by the second switch units SW 2  and transferred to the third selection unit  509  through the second line PUL. 
     The global word lines selected by the third selection unit  509  are global word lines employing the word line selected by the inputted row address RADD and a boosting option and having different voltages, and the global word lines that are not selected are global word lines that are not employing the boosting option and have the same voltage. 
     The control unit  503  generates the first control signals SWCTRL 1 &lt; 0 : 15 &gt; to be applied to the first selection unit  505 , the second control signal SWCTRL 2  to be applied to the second selection unit  507 , and the third control signals SWCTRL 3 &lt; 0 : 127 &gt; to be applied to the third selection unit  509  in response to the inputted row address RADD. 
     Each of the one or more first switch units SW 1 _ 0  to SW 1 _ 15  included in the first selection unit  505  selects one voltage among  8  different voltages V&lt; 0 : 7 &gt; generated in the voltage pump  501  and transfers it to a first line corresponding thereto in response to the first control signals SWCTRL 1 &lt; 0 : 15 &gt;. Here, the voltage selected by the first switch unit is decided based on the distance between the first line corresponding thereto and a first line that is to transfer a voltage to a global word line designated by the inputted row address RADD. 
     To be more specific, each of the one or more first switch units SW 1 _ 0  to SW 1 _ 15  selects one among a program voltage VPGM and one or more boosting voltages VBST 1  to VBST 3  based on the distance between the first line corresponding thereto among one or more first lines PSL&lt; 0 : 15 &gt; and the first line that is to transfer a voltage to a global word line designated by the inputted row address RADD, and transfers it to the first line corresponding thereto. 
     For example, referring to  FIG. 8 , when a global word line GWL&lt; 7 &gt; is selected based on the row address RADD (see  801 ), the voltage selected by the first switch units becomes different according to the distance of the first line which transfers a voltage to the global word line GWL&lt; 7 &gt;, that is, the distance between the first line PSL&lt; 7 &gt; and the first line corresponding to each of the first switch units. The first switch units SW 1 _ 5 , SW 1 _ 6 , SW 1 _ 8 , and SW 1 _ 9  select a first boosting voltage VBST 1 , e.g., V&lt; 1 &gt;, and the first switch units SW 1 _ 2 , SW 1 _ 3 , SW 1 _ 4 , SW 1 _ 10 , SW 1 _ 11 , and SW 1 _ 12  select a second boosting voltage VBST 2 , e.g., V&lt; 2 &gt;, and the first switch units SW 1 _ 0 , SW 1 _ 1 , SW 1 _ 13 , SW 1 _ 14 , and SW 1 _ 15  select a third boosting voltage VBST 3 , e.g., V&lt; 3 &gt;, and transfer them to the corresponding first lines. 
     The second switch unit SW 2  selects one voltage among the 8 different voltages V&lt; 0 : 7 &gt; that are generated in the voltage pump  501  and transfers it to the second line PUL in response to the second control signal SWCTRL 2 . Here, the voltage selected by the second switch unit SW 2  is a voltage to be commonly applied to the global word lines other than the one or more global word lines that receive voltages through one or more first lines PSL&lt; 0 : 15 &gt; among the global word lines GWL&lt; 0 : 127 &gt;. For example, the second switch unit SW 2  selects a pass voltage VPASS and transfers the pass voltage VPASS to the second line PUL. 
     Here, as illustrated in  FIG. 6 , the first switch units SW 1 _ 0  to SW 1 _ 15  and the second switch unit SW 2  include 8 switches individually, and the control signal (for example, a control signal SWCTRL 1 &lt; 0 &gt; inputted to the first switch unit SW 1 _ 0 ) inputted to each switch unit may be formed of at least 3 bits to control the 8 switches. A method for controlling the first switch units SW 1 _ 0  to SW 1 _ 15  and the second switch unit SW 2  based on the first and second control signals SWCTRL 1 &lt; 0 : 15 &gt; and SWCTRL 2  is the same as described with reference to  FIG. 8 . 
     The third selection unit  509  includes 128 third switch units SW 3 _ 0  to SW 3 _ 127  that are coupled with the 128 global word lines GWL&lt; 0 : 127 &gt;, respectively. The 128 third switch units SW 3 _ 0  to SW 3 _ 127  are divided into 8 switch groups  701  to  708 , and each of the 8 switch groups  701  to  708  includes 16 third switch units SW 3 _ 0  to SW 3 _ 15 , SW 3 _ 16  to SW 3 _ 31 , . . . , SW 3 _ 112  to SW 3 _ 127 . The 16 third switch units SW 3 _ 0  to SW 3 _ 15 , SW 3 _ 16  to SW 3 _ 31 , . . . , SW 3 _ 112  to SW 3 _ 127  inside of each of the 8 switch groups  701  to  708  correspond to the 16 first switch units SW 1 _ 0  to SW 1 _ 15  of the first selection unit  505  in one-to-one. 
     To be specific, an output voltage of the first first switch unit SW 1 _ 0  of the first selection unit  505  is inputted to the first third switch units SW 3 _ 0 , SW 3 _ 16 , . . . , SW 3 _ 112  of each of the 8 switch groups  701  to  708  through the first selection voltage line PSL&lt; 0 &gt;, and an output voltage of the second first switch unit SW 1 _ 1  of the first selection unit  505  is inputted to the second third switch units SW 3 _ 1 , SW 3 _ 17 , . . . , SW 3 _ 113  of each of the 8 switch groups  701  to  708  through the second selection voltage line PSL&lt; 1 &gt;. In short, the first selection voltage line PSL&lt; 0 &gt; is coupled with the third switch units SW 3 _ 0 , SW 3 _ 16 , SW 3 _ 32 , . . . , SW 3 _ 112 ; the second selection voltage line PSL&lt; 1 &gt; is coupled with the third switch units SW 3 _ 1 , SW 3 _ 17 , SW 3 _ 33 , . . . , SW 3 _ 113 ; and the third selection voltage line PSL&lt; 2 &gt; is coupled with the third switch units SW 3 _ 2 , SW 3 _ 18 , SW 3 _ 34 , . . . , SW 3 _ 114 , and the first selection unit  505  and the third selection unit  509  are coupled in such a manner that the first switch units of the first selection unit  505  are matched to the switch groups  701  to  708  of the third selection unit  509  in one-to-one. Here, the fourth to 16 th  third selection voltage line PSL&lt; 2 &gt; to PSL&lt; 15 &gt; are coupled with the third switch units in the same manner. 
     An output voltage of the second selection unit  507  is commonly inputted to the 128 third switch units SW 3 _ 0  to SW 3 _ 127  through the second line PUL. Therefore, the third switch units SW 3 _ 0  to SW 3 _ 127  receives two voltages: one is a voltage of the first line corresponding thereto among one or more first lines PSL&lt; 0 : 15 &gt;, and the other is a voltage of the second line PUL. 
     To have a look at the control method of the third selection unit  509 , the control unit  503  generates the third control signals SWCTRL 3 &lt; 0 : 127 &gt; that are respectively inputted to the 128 third switch units SW 3 _ 0  to SW 3 _ 127  in response to the inputted row address RADD. Herein, each of the third control signals SWCTRL 3 &lt; 0 : 127 &gt; may be a one-bit signal having a value of a logic high or low level. 
     The third switch units SW 3 _ 0  to SW 3 _ 127  select one between the two voltages that are inputted thereto and applies it to a global word lines GWL&lt; 0 : 127 &gt; corresponding thereto in response to the third control signals SWCTRL 3 &lt; 0 : 127 &gt;. Herein, the third switch units SW 3 _ 0  to SW 3 _ 127  may select the voltage of the first line corresponding thereto when the applied third control signals SWCTRL 3 &lt; 0 : 127 &gt; is in a logic high level, or the third switch units SW 3 _ 0  to SW 3 _ 127  may select the voltage of the second line when the applied third control signals SWCTRL 3 &lt; 0 : 127 &gt; is in a logic low level, and apply the selected voltage to the global word lines GWL&lt; 0 : 127 &gt; corresponding thereto. 
     For example, when a global word line GWL&lt; 10 &gt; is selected by the inputted row address RADD, the third control signals SWCTRL 3 &lt; 3 &gt; to SWCTRL 3 &lt; 18 &gt; that are applied to 16 third switch units SW 3 _ 3  to SW 3 _ 18  coupled with the 16 global word lines GWL&lt; 3 &gt; to GWL&lt; 18 &gt; within a predetermined distance from the global word line GWL&lt; 10 &gt; may have a value of logic high level, and the other third control signals SWCTRL 3 &lt; 0 &gt; to SWCTRL 3 &lt; 2 &gt; and SWCTRL 3 &lt; 19 &gt; to SWCTRL 3 &lt; 127 &gt; may have a value of logic low level. Detailed control operation is the same as described with reference to  FIG. 8 . 
     According to the present invention, a two-stage switch structure is provided between a voltage pump and global word lines to selectively apply a plurality of voltages to the global word lines. Through the embodiment of the present invention the number of switches included for an entire circuit and the number of control signals for controlling the switches is reduced. Consequently, the entire area and complexity of a highly integrated nonvolatile memory device is also reduced. 
     While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.