Patent Publication Number: US-11031909-B2

Title: Group delay optimization circuit and related apparatus

Description:
RELATED APPLICATIONS 
     This application claims the benefit of U.S. provisional patent application Ser. No. 62/775,231, filed on Dec. 4, 2018, which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE DISCLOSURE 
     The technology of the disclosure relates generally to envelope tracking (ET) power management in wireless communication devices. 
     BACKGROUND 
     Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences. 
     The redefined user experience requires higher data rates offered by wireless communication technologies, such as long-term evolution (LTE). To achieve the higher data rates in mobile communication devices, sophisticated power amplifiers (PAs) may be employed to increase output power of radio frequency (RF) signals (e.g., maintaining sufficient energy per bit) communicated by mobile communication devices. However, the increased output power of RF signals can lead to increased power consumption and thermal dissipation in mobile communication devices, thus compromising overall performance and user experiences. 
     Envelope tracking is a power management technology designed to improve efficiency levels of PAs to help reduce power consumption and thermal dissipation in mobile communication devices. As the name suggests, envelope tracking employs a system that keeps track of the amplitude envelope of the RF signals communicated by mobile communication devices. The envelope tracking system constantly adjusts supply voltages applied to the PAs to ensure that the PAs are operating at a higher efficiency for a given instantaneous output power requirement of the RF signals. 
     However, the envelope tracking system can only maintain good linearity and high efficiency up to an inherent bandwidth limit. In the advent of fifth-generation new radio (5G-NR) technology, the RF signals may be modulated with a higher bandwidth (e.g., &gt;100 MHz) than the inherent bandwidth limit of the envelope tracking system, thus reducing linearity and efficiency of the envelope tracking system. As such, it may be desirable to improve linearity and efficiency of the envelope tracking system to support the 5G-NR technology. 
     SUMMARY 
     Aspects disclosed in the detailed description include a group delay optimization circuit and related apparatus. In examples discussed herein, the group delay optimization circuit receives a first signal (e.g., a voltage signal) and a second signal (e.g., a current signal). Notably, the first signal and the second signal may experience different group delays that can cause the first signal and the second signal to misalign at an amplifier circuit configured to amplify a radio frequency (RF) signal. In this regard, the group delay optimization circuit is configured to determine a statistical indicator indicative of a group delay offset between the first signal and the second signal. Accordingly, the group delay optimization circuit may minimize the group delay offset by reducing the statistical indicator to below a defined threshold in one or more group delay optimization cycles. As a result, it may be possible to pre-compensate for the group delay offset in the RF signal, thus helping to improve efficiency and linearity of the amplifier circuit. 
     In one aspect, a group delay optimization circuit is provided. The group delay optimization circuit includes a first input node configured to receive a first signal. The group delay optimization circuit also includes a second input node configured to receive a second signal. The group delay optimization circuit also includes a control circuit. The control circuit is configured to sample a first selected signal among the first signal and the second signal in a delay estimation window corresponding to a second selected signal among the first signal and the second signal to generate a number of amplitude samples of the first selected signal. The control circuit is also configured to determine a statistical indicator indicative of a group delay offset between the first signal and the second signal based on the amplitude samples. The control circuit is also configured to reduce the statistical indicator to below a defined threshold in one or more group delay optimization cycles to minimize the group delay offset between the first signal and the second signal. 
     In another aspect, an ET apparatus is provided. The ET apparatus includes an amplifier circuit configured to receive a signal corresponding to a time-variant signal envelope from a coupled transceiver circuit and amplify the signal based on an ET voltage signal. The ET apparatus includes an ET integrated circuit (ETIC). The ETIC is configured to generate the ET voltage signal based on an ET target voltage signal. The ETIC is also configured to generate a sense current signal corresponding to a time-variant current envelope proportionally related to the time-variant signal envelope. The ET apparatus also includes a group delay optimization circuit. The group delay optimization circuit includes a first input node configured to receive a selected voltage signal among the ET target voltage signal and the ET voltage signal. The group delay optimization circuit also includes a second input node configured to receive the sense current signal. The group delay optimization circuit also includes a control circuit. The control circuit is configured to sample a first selected signal among the sense current signal and the selected voltage signal in a delay estimation window corresponding to a second selected signal among the sense current signal and the selected voltage signal to generate a number of amplitude samples of the first selected signal. The control circuit is also configured to determine a statistical indicator indicative of a group delay offset between the selected voltage signal and the sense current signal based on the amplitude samples. The control circuit is also configured to reduce the statistical indicator to below a defined threshold in one or more group delay optimization cycles to minimize the group delay offset between the selected voltage signal and the sense current signal. 
     Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG. 1A  is a schematic diagram of an exemplary existing envelope tracking (ET) amplifier apparatus that can experience degraded overall linearity performance as a result of inherent processing and/or propagation delays of the existing ET apparatus; 
         FIG. 1B  is a graphic diagram providing an exemplary illustration of a temporal misalignment between a time-variant voltage envelope and a time-variant signal envelope that can occur in the existing ET apparatus of  FIG. 1A ; 
         FIG. 1C  is a graphic diagram providing an exemplary illustration of how a temporal delay can affect adjacent channel leakage ratio (ACLR) of an amplifier circuit in the existing ET apparatus of  FIG. 1A ; 
         FIG. 2  is a graphical diagram providing an exemplary illustration of amplitude variations of an ET voltage and a load current as a result of group delay variations between a time-variant ET voltage envelope and a time-variant signal envelope in the existing ET apparatus of  FIG. 1A ; 
         FIG. 3  is a schematic diagram of an exemplary group delay optimization circuit configured according to an embodiment of the present disclosure to optimize a group delay offset between a voltage signal and a current signal by minimizing a statistical indicator indicative of a statistical distribution of the voltage signal and/or the current signal; 
         FIG. 4  is a schematic diagram of an exemplary group delay optimization circuit configured according to an alternative embodiment of the present disclosure; 
         FIG. 5  is a schematic diagram of an exemplary group delay optimization circuit configured according to another alternative embodiment of the present disclosure; 
         FIG. 6A  is a schematic diagram of an exemplary ET apparatus configured according to an embodiment of the present disclosure to incorporate the group delay optimization circuit of  FIGS. 3-5 ; and 
         FIG. 6B  is a schematic diagram of an exemplary ET apparatus configured according to another embodiment of the present disclosure to incorporate the group delay optimization circuit of  FIGS. 3-5 . 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     Aspects disclosed in the detailed description include a group delay optimization circuit and related apparatus. In examples discussed herein, the group delay optimization circuit receives a first signal (e.g., a voltage signal) and a second signal (e.g., a current signal). Notably, the first signal and the second signal may experience different group delays that can cause the first signal and the second signal to misalign at an amplifier circuit configured to amplify a radio frequency (RF) signal. In this regard, the group delay optimization circuit is configured to determine a statistical indicator indicative of a group delay offset between the first signal and the second signal. Accordingly, the group delay optimization circuit may minimize the group delay offset by reducing the statistical indicator to below a defined threshold in one or more group delay optimization cycles. As a result, it may be possible to pre-compensate for the group delay offset in the RF signal, thus helping to improve efficiency and linearity of the amplifier circuit. 
     Before discussing a group delay optimization circuit of the present disclosure, a brief overview of an existing ET apparatus that may experience degraded overall linearity performance as a result of inherent temporal delay associated with the existing ET apparatus is first provided with reference to  FIGS. 1A-1C . A discussion of how a group delay variation can affect amplitude variation of a voltage signal and a current signal is then provided with reference to  FIG. 2  to help establish a basis for using a statistical means to determine the optimized delay offset between the current signal and the voltage signal. The discussion of specific exemplary aspects of a group delay optimization circuit of the present disclosure starts below with reference to  FIG. 3 . 
       FIG. 1A  is a schematic diagram of an exemplary existing ET apparatus  10  that can experience a degraded overall linearity performance as a result of inherent processing and/or propagation delays of the existing ET apparatus  10 . The existing ET apparatus  10  includes a signal processing circuit  12 , an ET integrated circuit (ETIC)  14 , and an amplifier circuit  16 . The signal processing circuit  12  receives a digital signal  18  that includes a number of time-variant digital signal amplitudes  20  representing a time-variant digital signal envelope  22 . The phrase “time-variant” is used hereinafter to refer to a parameter (e.g., amplitude, voltage, power, etc.) that changes (e.g., increases or decreases) over time. 
     The signal processing circuit  12  is configured to convert the digital signal  18  into an RF signal  24  having a time-variant signal envelope  26  formed based on the time-variant digital signal envelope  22 . In this regard, the time-variant digital signal envelope  22 , which is defined by the time-variant digital signal amplitudes  20 , can be seen as a digital representation of the time-variant signal envelope  26 . 
     The digital signal  18  may be modulated to include a digital in-phase signal  281 , which has a number of time-variant in-phase amplitudes I, and a digital quadrature signal  28 Q, which has a number of time-variant quadrature amplitudes Q. In this regard, each of the time-variant digital signal amplitudes  20  of the digital signal  18  can be expressed as √{square root over (I 2 +Q 2 )}. 
     The existing ET apparatus  10  includes a mixer  30  that combines the time-variant digital signal amplitudes  20  with a digital voltage reference signal  32  to generate a digital target voltage reference signal  34 . In this regard, the digital target voltage reference signal  34  is associated with the time-variant digital signal envelope  22  and, therefore, the time-variant digital signal amplitudes  20 . 
     The existing ET apparatus  10  includes lookup table (LUT) circuitry  36  (denoted as “LUT” in  FIG. 1A ), which may store a number of predetermined target voltage amplitude values corresponding to the time-variant digital signal amplitudes  20 . In this regard, the LUT circuitry  36  converts the time-variant digital signal amplitudes  20  into a number of time-variant digital target voltage amplitudes  38  and associates the time-variant digital target voltage amplitudes  38  with a digital target voltage signal  40 . As a result of such digital conversion, the time-variant digital target voltage amplitudes  38  may be distorted. For example, the LUT circuitry  36  can be non-strictly monotonic. As a result, a digital target voltage amplitude among the time-variant digital target voltage amplitudes  38  can become higher or lower than a corresponding digital signal amplitude among the time-variant digital signal amplitudes  20 . 
     The existing ET apparatus  10  includes a voltage digital-to-analog converter (DAC)  42  configured to convert the digital target voltage signal  40  into a target voltage signal  44  having a time-variant target voltage envelope  46  formed based on the time-variant digital target voltage amplitudes  38 . The voltage DAC  42  is configured to provide the target voltage signal  44  to the ETIC  14 . 
     The ETIC  14  receives the target voltage signal  44  having the time-variant target voltage envelope  46 . The time-variant target voltage envelope  46  may represent an ET target voltage V TARGET  for the ETIC  14 . The ETIC  14  is configured to generate an ET voltage V CC  having a time-variant ET voltage envelope  48  that tracks the time-variant target voltage envelope  46 . The ET voltage V CC  is a time-variant ET voltage formed based on the ET target voltage V TARGET . Accordingly, the ET voltage V CC  tracks the ET target voltage V TARGET . 
     The amplifier circuit  16  is coupled to the signal processing circuit  12  to receive the RF signal  24  having the time-variant signal envelope  26 . The amplifier circuit  16  is also coupled to the ETIC  14  to receive the ET voltage V CC  corresponding to the time-variant ET voltage envelope  48 . The amplifier circuit  16  is configured to amplify the RF signal  24  based on the ET voltage V CC . The amplifier circuit  16  may appear to the ETIC  14  as a current source and induce a load current I LOAD  in response to receiving the ET voltage V CC . In case the time-variant signal envelope  26  corresponds to a higher peak-to-average ratio (PAR), the ETIC  14  may have to source at least a portion of the load current I LOAD  to keep track of the time-variant signal envelope  26 . In this regard, to avoid amplitude clipping in the RF signal  24 , the load current I LOAD  needs to rise and fall from time to time in accordance to the time-variant signal envelope  26  of the RF signal  24 . Further, to maintain linearity and efficiency in the amplifier circuit  16 , the time-variant ET voltage envelope  48  of the ET voltage V CC  also needs to align closely with the time-variant signal envelope  26  at the amplifier circuit  16 . 
     However, the signal processing circuit  12 , the LUT circuitry  36 , the voltage DAC  42 , and the ETIC  14  may each incur processing and/or propagation delays. In addition, the amplifier circuit  16  may be a multi-stage amplifier including a driver stage  50  and an output stage  52  that also incur respective processing and/or propagation delays. As a result, the time-variant ET voltage envelope  48  may be out of alignment with the time-variant signal envelope  26  at the amplifier circuit  16 . Hereinafter, the phrase “group delay” refers generally to a sum of all delays (processing and propagation) related to generating the ET voltage V CC  or providing the RF signal  24  to the amplifier circuit  16 . 
     In this regard,  FIG. 1B  is a graphic diagram providing an exemplary illustration of a temporal misalignment between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26  of  FIG. 1A . Elements of  FIG. 1A  are referenced in conjunction with  FIG. 1B  and will not be re-described herein. 
     If the time-variant signal envelope  26  and the time-variant ET voltage envelope  48  are perfectly aligned, an instantaneous amplitude of the RF signal  24  (not shown), which is represented by a voltage V S , would substantially equal the ET voltage V CC  at time t x . However, as shown in  FIG. 1B , the time-variant signal envelope  26  lags behind the time-variant ET voltage envelope  48  by a temporal delay Δt. As such, at time t x , the amplifier circuit  16  (not shown) receives a lower ET voltage V′ CC , instead of the ET voltage V CC . In this regard, the time-variant ET voltage envelope  48  deviates from the time-variant signal envelope  26  by a voltage differential Δv at time t x . Consequently, the amplifier circuit  16  may suffer degraded linearity performance. 
     In a non-limiting example, the linearity performance of the amplifier circuit  16  can be measured by an adjacent channel leakage ratio (ACLR). The ACLR represents a ratio between in-band power and out-of-band leakage power. In this regard, a higher ACLR indicates a better linearity performance of the amplifier circuit  16 .  FIG. 1C  is a graphic diagram providing an exemplary illustration of how the temporal delay Δt of  FIG. 1B  can affect the ACLR of the amplifier circuit  16  of  FIG. 1A . Elements of  FIGS. 1A and 1B  are referenced in conjunction with  FIG. 1C  and will not be re-described herein. 
       FIG. 1C  includes a first ACLR curve  54  and a second ACLR curve  56 . In a non-limiting example, the first ACLR curve  54  corresponds to an RF signal (e.g., the RF signal  24 ) modulated at 100 MHz bandwidth and the second ACLR curve  56  corresponds to an RF signal (e.g., the RF signal  24 ) modulated at 60 MHz bandwidth. As shown in  FIG. 1C , the first ACLR curve  54  has a steeper slope compared to the second ACLR curve  56 . In this regard, to achieve −32 dB ACLR, for example, the existing ET apparatus  10  is confined to a delay budget of approximately 1.0 nanosecond (ns) when the RF signal  24  is modulated at 100 MHz bandwidth. In contrast, the existing ET apparatus  10  would be subject to a more relaxed delay budget of approximately 1.3 ns for the same −32 dB ACLR when the RF signal  24  is modulated at 60 MHz bandwidth. 
     Notably, the RF signal  24  may be a long-term evolution (LTE) signal, which is typically modulated at up to 60 MHz modulation bandwidth or a fifth-generation new-radio (5G-NR) signal that is often modulated at more than 100 MHz modulation bandwidth. In this regard, the existing ET apparatus  10  must adhere to a more stringent delay budget to achieve a desirable ACLR at the amplifier circuit  16  for communicating the RF signal  24  in a 5G-NR system. 
     With reference back to  FIG. 1B , to mitigate linearity degradation and achieve the desirable ACLR at the amplifier circuit  16 , it is necessary to reduce the temporal delay Δt between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26 . However, it may be difficult to do so adequately in the existing ET apparatus  10  to satisfy the more stringent delay budget required for communicating a 5G-NR signal modulated at the higher modulation bandwidth (e.g., &gt;100 MHz). As such, it may be desirable to improve delay tolerance of the existing ET apparatus  10  to reduce linearity degradation caused by temporal misalignment between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26 . 
     Notably, the temporal delay Δt between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26  can cause fluctuations in the ET voltage V CC  and the load current I LOAD . In this regard,  FIG. 2  is a graphic diagram  58  providing an exemplary illustration of amplitude variations of the ET voltage V CC  and the load current I LOAD  as a result of group delay variations between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26  in the existing ET apparatus  10  of  FIG. 1A . Elements in  FIG. 1A  are referenced in conjunction with  FIG. 2  and will not be re-described herein. 
     In the graphic diagram  58 , a band region  60  represents distribution of the ET voltage V CC  and the load current I LOAD  when the time-variant ET voltage envelope  48  is aligned with the time-variant signal envelope  26 . The graphic diagram  58  includes a number of first dots  62  and a number of second dots  64 . The first dots  62  indicate distributions of the ET voltage V CC  and the load current I LOAD  when the time-variant ET voltage envelope  48  is ahead of the time-variant signal envelope  26 . The second dots  64  indicate distributions of the ET voltage V CC  and the load current I LOAD  when the time-variant ET voltage envelope  48  is behind the time-variant signal envelope  26 . 
     An important observation can be made from the graphic diagram  58 . When the time-variant ET voltage envelope  48  is aligned with the time-variant signal envelope  26 , the distribution of the ET voltage V CC  and the load current I LOAD  may be close to a statistical mean (e.g., in the band region  60 ). In contrast, when the time-variant ET voltage envelope  48  is misaligned from the time-variant signal envelope  26 , the distribution of the ET voltage V CC  and the load current I LOAD  may deviate from statistical mean, such as the first dots  62  or the second dots  64 . 
     In this regard, it may be possible to correlate a defined statistical indicator (e.g., standard deviation) indicative of the distribution of the ET voltage V CC  and/or the load current I LOAD  with a group delay offset between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26 . As discussed below in the exemplary aspects of the present disclosure, it may be possible to optimize the group delay offset between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26  by minimizing the defined statistical indicator. 
     In one non-limiting example, it is possible to define a current-related delay estimation window  66  based on a lower current threshold  68  and an upper current threshold  70  of the load current I LOAD . The current-related delay estimation window  66  may be determined (e.g., via simulation) to correspond to higher voltage sensitivity. Accordingly, it may be possible to sample the ET voltage V CC  in the current-related delay estimation window  66  to determine a voltage-related statistical indicator σ v  indicative of the distribution of the ET voltage V CC . Since the ET voltage V CC  is generated based on the ET target voltage V TARGET , it may also be possible to sample the ET target voltage V TARGET  in the current-related delay estimation window  66  to determine the voltage-related statistical indicator σ v  indicative of the distribution of the ET voltage V CC . Thus, by minimizing the voltage-related statistical indicator σ v  associated with the ET voltage V CC , it may be possible to optimize the group delay offset between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26 . 
     In another non-limiting example, it is possible to define a voltage-related delay estimation window  72  based on a lower voltage threshold  74  and an upper voltage threshold  76  of the ET voltage V CC  (or the ET target voltage V TARGET ). The voltage-related delay estimation window  72  may be determined (e.g., via simulation) to correspond to higher current sensitivity. Accordingly, it may be possible to sample the load current I LOAD  in the voltage-related delay estimation window  72  to determine a current-related statistical indicator σ i  indicative of the distribution of the load current I LOAD . Thus, by minimizing the current-related statistical indicator σ i  associated with the load current I LOAD , it may be possible to optimize the group delay offset between the time-variant ET voltage envelope  48  and the time-variant signal envelope  26 . 
     In this regard,  FIG. 3  is a schematic diagram of an exemplary group delay optimization circuit  78  configured according to an embodiment of the present disclosure to minimize a group delay offset between a voltage signal  80  (also referred to as “a first signal”) and a current signal  82  (also referred to as “a second signal”) by minimizing a statistical indicator σ indicative of a statistical distribution of the voltage signal  80  and/or the current signal  82 . Common elements between  FIGS. 2 and 3  are shown therein with common element numbers and will not be re-described herein. 
     The group delay optimization circuit  78  may include a first input node  83 A and a second input node  83 B configured to receive the voltage signal  80  and the current signal  82 , respectively. In a non-limiting example, the voltage signal  80  can be the ET voltage V CC  or the ET target voltage V TARGET  as illustrated in  FIG. 1A  and the current signal  82  can be the load current I LOAD  or a derivative signal proportionally related to the load current I LOAD . Notably, the voltage signal  80  may correspond to a voltage group delay T v  and the current signal  82  may correspond to a current group delay T i . Accordingly, the group delay offset between the voltage signal  80  and the current signal  82  corresponds to a differential between the voltage group delay T v  and the current group delay T i  (e.g., T v −T i  or T i −T v ). Thus, it may be possible to adjust (increase or decrease) the group delay offset by adjusting (increase or decrease) the voltage group delay T v  and/or the current group delay T i . 
     In one embodiment, the group delay optimization circuit  78  can be configured to sample the voltage signal  80  (also known as “a first selected signal among the voltage signal  80  and the current signal  82 ”) in the current-related delay estimation window  66 , which corresponds to the current signal  82  (also known as “a second selected signal among the voltage signal  80  and the current signal  82 ”), to generate a number of voltage amplitude samples of the voltage signal  80 . Accordingly, the group delay optimization circuit  78  can determine a voltage-related statistical indicator σ v  based on the voltage amplitude samples. The voltage-related statistical indicator σ v  may be determined based on any of the equations (Eq. 1.1-1.3) below. 
     
       
         
           
             
               
                 
                   
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                     1.3 
                   
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     In the equations (Eq. 1.1-1.3) above, “N” represents a count of the voltage amplitude samples, “x i ” represents any of the voltage amplitude samples, and “μ” represents a mean value of the voltage amplitude samples. The group delay optimization circuit  78  may be configured to perform one or more group delay optimization cycles to minimize the group delay offset σ. In a non-limiting example, in each of the group delay optimization cycles, the group delay optimization circuit  78  may adjust the group delay offset between the voltage signal  80  and the current signal  82 . Accordingly, the group delay optimization circuit  78  may re-sample the voltage signal  80  to generate the voltage amplitude samples and re-determine voltage-related statistical indicator σ v  based on the voltage amplitude samples. The group delay optimization circuit  78  may be configured to stop the group delay optimization cycles as soon as the voltage-related statistical indicator σ v  is below a defined threshold. Hereinafter, the group delay offset that causes the voltage-related statistical indicator σ v  to be below the defined threshold is referred to as an optimized group delay offset. Accordingly, the group delay optimization circuit  78  may output a group delay correction signal  84  indicative of the optimized group delay offset. 
     In another embodiment, the group delay optimization circuit  78  can be configured to sample the current signal  82  (also known as “a first selected signal among the voltage signal  80  and the current signal  82 ”) in the voltage-related delay estimation window  72 , which corresponds to the voltage signal  80  (also known as “a second selected signal among the voltage signal  80  and the current signal  82 ”), to generate a number of current amplitude samples of the current signal  82 . Accordingly, the group delay optimization circuit  78  can determine a current-related statistical indicator σ i  based on the current amplitude samples. The current-related statistical indicator σ i  may be determined based on any of the equations (Eq. 2.1-2.3) below. 
     
       
         
           
             
               
                 
                   
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                     2.1 
                   
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     Accordingly, the group delay optimization circuit  78  may perform the group delay optimization cycles to minimize the group delay offset to below the defined threshold and subsequently output the group delay correction signal  84  indicative of the optimized group delay offset. 
     The group delay optimization circuit  78  includes a comparator circuit  86  configured to receive the voltage signal  80  and the current signal  82 . The group delay optimization circuit  78  also includes a control circuit  88 . In a non-limiting example, the comparator circuit  86  is coupled to the control circuit  88  via a switch circuit  90 . Accordingly, the comparator circuit  86  can be configured to activate or deactivate the control circuit  88  via the switch circuit  90 . 
     In one embodiment, the comparator circuit  86  may be configured to compare the current signal  82  against the lower current threshold  68  and the upper current threshold  70  to determine whether the current signal  82  falls within the current-related delay estimation window  66 . If the comparator circuit  86  determines that the current signal  82  falls within the current-related delay estimation window  66 , the comparator circuit  86  may control the switch circuit  90  to activate the control circuit  88  to determine the optimized group delay offset between the voltage signal  80  and the current signal  82  by sampling the voltage signal  80 , determining the voltage-related statistical indicator σ v , and minimizing the voltage-related statistical indicator σ v  to below the defined threshold. 
     In another embodiment, the comparator circuit  86  may be configured to compare the voltage signal  80  against the lower voltage threshold  74  and the upper voltage threshold  76  to determine whether the voltage signal  80  falls within the voltage-related delay estimation window  72 . If the comparator circuit  86  determines that the voltage signal  80  falls within the voltage-related delay estimation window  72 , the comparator circuit  86  may control the switch circuit  90  to activate the control circuit  88  to determine the optimized group delay offset between the voltage signal  80  and the current signal  82  by sampling the current signal  82 , determining the current-related statistical indicator σ i , and minimizing the current-related statistical indicator σ i  to below the defined threshold. 
     In a non-limiting example, the control circuit  88  includes a statistical calculator circuit  92  and a delay optimizer circuit  94 . The statistical calculator circuit  92  may be configured to sample the voltage signal  80  and/or the current signal  82  in the current-related delay estimation window  66  and/or the voltage-related delay estimation window  72 . Accordingly, the statistical calculator circuit  92  may be configured to determine the voltage-related statistical indicator σ v  based on the voltage amplitude samples of the voltage signal  80  and/or the current-related statistical indicator σ i  based on the current amplitude samples of the current signal  82 . The delay optimizer circuit  94  may be configured to determine the optimized group delay offset between the voltage signal  80  and the current signal  82  by performing the group delay optimization cycles to reduce the voltage-related statistical indicator σ v  and/or the current-related statistical indicator σ i  to below the defined threshold. Notably, the delay optimizer circuit  94  may be configured to adjust (increase or decrease) the group delay offset in each of the group delay optimization cycles by adjusting the voltage group delay T v  and/or the current group delay T i . 
     The group delay optimization circuit  78  may further include a current subtraction circuit  96 . In a non-limiting example, the current subtraction circuit  96  can be configured to remote an unwanted current signal(s) from the current signal  82  prior to providing the current signal  82  to the comparator circuit  86 . 
       FIG. 4  is a schematic diagram of an exemplary group delay optimization circuit  78 A configured according to an alternative embodiment of the present disclosure. Common elements between  FIGS. 3 and 4  are shown therein with common element numbers and will not be re-described herein. 
     The group delay optimization circuit  78 A includes a second comparator circuit  86 A. The group delay optimization circuit  78 A also includes a control circuit  88 A that further includes a second statistical calculator circuit  92 A coupled to the second comparator circuit  86 A via a second switch circuit  90 A. In a non-limiting example, the comparator circuit  86  is configured to determine whether the current signal  82  falls within the current-related delay estimation window  66  and the second comparator circuit  86 A is configured to determine whether the voltage signal  80  falls within the voltage-related delay estimation window  72 . 
     When the comparator circuit  86  determines that the current signal  82  falls within the current-related delay estimation window  66 , the comparator circuit  86  activates the statistical calculator circuit  92  to sample the voltage signal  80  and determine the voltage-related statistical indicator σ v . Likewise, when the second comparator circuit  86 A determines that the voltage signal  80  falls within the voltage-related delay estimation window  72 , the second comparator circuit  86 A activates the second statistical calculator circuit  92 A to sample the current signal  82  and determine the current-related statistical indicator σ i . The control circuit  88 A includes a delay optimizer circuit  94 A configured to perform the delay optimization cycles based on the voltage-related statistical indicator σ v  and the current-related statistical indicator σ i  to determine the optimized group delay offset between the voltage signal  80  and the current signal  82 . 
       FIG. 5  is a schematic diagram of an exemplary group delay optimization circuit  78 B configured according to another alternative embodiment of the present disclosure. Common elements between  FIGS. 3 and 5  are shown therein with common element numbers and will not be re-described herein. 
     The group delay optimization circuit  78 B includes at least one second comparator circuit  86 B. The group delay optimization circuit  78 B also includes a control circuit  88 B that further includes at least one second statistical calculator circuit  92 B coupled to the second comparator circuit  86 B via at least one second switch circuit  90 B. The control circuit  88 B also includes a delay optimizer circuit  94 B. 
     In one embodiment, both the comparator circuit  86  and the second comparator circuit  86 B are configured to determine whether the current signal  82  falls with the current-related delay estimation window  66 . If the current signal  82  falls with the current-related delay estimation window  66 , the comparator circuit  86  and the second comparator circuit  86 B are configured to activate the statistical calculator circuit  92  and the second statistical calculator circuit  92 B, respectively. The statistical calculator circuit  92  and the second statistical calculator circuit  92 B may concurrently sample the voltage signal  80  to generate the voltage amplitude samples and determine the voltage-related statistical indicator σ v . The delay optimizer circuit  94 B may perform the delay optimization cycles to determine the optimized delay offset between the voltage signal  80  and the current signal  82 . In a non-limiting example, the delay optimizer circuit  94  can adjust at least one second delay offset between the voltage signal  80  and the current signal  82  in each of the delay optimization cycles. In this regard, the group delay optimization circuit  78 B may concurrently evaluate the voltage-related statistical indicator σ v  based on multiple group delay offsets. As a result, it may be possible to reduce the number of delay optimization cycles. 
     In another embodiment, both the comparator circuit  86  and the second comparator circuit  86 B are configured to determine whether the voltage signal  80  falls with the voltage-related delay estimation window  72 . If the voltage signal  80  falls with the voltage-related delay estimation window  72 , the comparator circuit  86  and the second comparator circuit  86 B are configured to activate the statistical calculator circuit  92  and the second statistical calculator circuit  92 B, respectively. The statistical calculator circuit  92  and the second statistical calculator circuit  92 B may concurrently sample the current signal  82  to generate the current amplitude samples and determine the current-related statistical indicator σ i . The delay optimizer circuit  94 B may perform the delay optimization cycles to determine the optimized delay offset between the voltage signal  80  and the current signal  82 . In a non-limiting example, the delay optimizer circuit  94  can adjust at least one second delay offset between the voltage signal  80  and the current signal  82  in each of the delay optimization cycles. In this regard, the group delay optimization circuit  78 B may concurrently evaluate the voltage-related statistical indicator σ v  based on multiple group delay offsets. As a result, it may be possible to reduce the number of delay optimization cycles. 
     The group delay optimization circuit  78  of  FIG. 3 , the group delay optimization circuit  78 A of  FIG. 4 , and the group delay optimization circuit  78 B of  FIG. 5  can be provided in an ET apparatus to help improve efficiency and/or linearity performance of an amplifier circuit(s). In this regard,  FIG. 6A  is a schematic diagram of an exemplary ET apparatus  98 A configured according to an embodiment of the present disclosure to incorporate the group delay optimization circuit  78  of  FIG. 3 , the group delay optimization circuit  78 A of  FIG. 4 , or the group delay optimization circuit  78 B of  FIG. 5 . Common elements between  FIGS. 3, 4, 5, and 6A  are shown therein with common element numbers and will not be re-described herein. 
     The ET apparatus  98 A includes an amplifier circuit  100  configured to amplify a signal  102  based on an ET voltage signal V CC . The signal  102 , which may be provided to the amplifier circuit  100  from a coupled transceiver circuit  104 , corresponds to a time-variant signal envelope  106  similar to the time-variant signal envelope  26  in  FIG. 1A . 
     The ET apparatus  98 A includes an ET integrated circuit (ETIC)  108 A configured to generate the ET voltage signal V CC  based on an ET target voltage signal V TARGET . In a non-limiting example, the ETIC  108 A includes a voltage amplifier(s)  110  configured to generate an initial ET voltage signal V′ CC  based on the ET target voltage signal V TARGET . The voltage amplifier(s)  110  may be coupled to an offset capacitor(s)  112  configured to convert the initial ET voltage signal V′ CC  to the ET voltage signal V CC . The ETIC  108 A may include a feedback loop  114  configured to provide a copy of the ET voltage signal V CC  back to the voltage amplifier(s)  110 . The ET target voltage signal V TARGET  may correspond to a time-variant target voltage envelope  116 , which is similar to the time-variant target voltage envelope  46  in  FIG. 1A . Accordingly, the ETIC  108 A is configured to generate the ET voltage signal V CC  having a time-variant ET voltage envelope  118  that tracks the time-variant target voltage envelope  116 . 
     Similar to the existing ET apparatus  10  of  FIG. 1A , the ET apparatus  98 A may cause the time-variant ET voltage envelope  118  to misalign with the time-variant signal envelope  106  at the amplifier circuit  100  due to similar reasons as previously described in  FIGS. 1A-1C . Hence, it may be desired to minimize the group delay offset between the time-variant ET voltage envelope  118  and the time-variant signal envelope  106  in the ET apparatus  98 A by incorporating the group delay optimization circuit  78  of  FIG. 3 , the group delay optimization circuit  78 A of  FIG. 4 , or the group delay optimization circuit  78 B of  FIG. 5 . Notably, the group delay optimization circuit  78 , the group delay optimization circuit  78 A, and the group delay optimization circuit  78 B may be integrated into the ETIC  108 A or coupled to the ETIC  108 A externally. 
     Similar to the amplifier circuit  16  in  FIG. 1A , the amplifier circuit  100  may appear to the ETIC  108 A as a current source and induce a load current I LOAD  in response to receiving the ET voltage signal V CC . In case the time-variant signal envelope  106  corresponds to a higher PAR, the voltage amplifier(s)  110  in the ETIC  108 A may be forced to source a current I AC  such that the load current I LOAD  can keep track of the time-variant signal envelope  106 . In this regard, the current I AC  may be proportionally related to the load current I LOAD . Given that the load current I LOAD  needs to rise and fall from time to time in accordance to the time-variant signal envelope  106  of the signal  102 , the current I AC  may likewise track the time-variant signal envelope  106  closely. 
     The voltage amplifier(s)  110  is configured to generate a sense current signal I SENSE  indicative of the current I AC  being sourced by the voltage amplifier(s)  110 . In a non-limiting example, the sense current signal I SENSE  is proportionally related to the current I AC  and thus the load current I LOAD . In this regard, the sense current signal I SENSE  may also track the time-variant signal envelope  106  closely. As such, the sense current signal I SENSE  may be provided to the group delay optimization circuit  78  as the current signal  82 . In addition, the ET target voltage signal V TARGET  (also referred to as “a selected voltage signal among the ET target voltage signal V TARGET  and the ET voltage signal V CC ”) may be provided to the group delay optimization circuit  78  as the voltage signal  80 . 
     The amplifier circuit  100  may be coupled to a load capacitor  120 , which can induce a capacitor current I CL . In this regard, the load current I LOAD  may include both the current I AC  and the capacitor current I CL  (I LOAD =I AC +I CL ). In this regard, the capacitor current I CL  can become an unwanted signal. Thus, according to the discussion in  FIG. 3 , the current subtraction circuit  96  may be configured to subtract the capacitor current I Cl  from the sense current signal I SENSE  prior to providing to the comparator circuit  86 . 
       FIG. 6B  is a schematic diagram of an exemplary ET apparatus  98 B configured according to another embodiment of the present disclosure to incorporate the group delay optimization circuit  78  of  FIG. 3 , the group delay optimization circuit  78 A of  FIG. 4 , or the group delay optimization circuit  78 B of  FIG. 5 . Common elements between  FIGS. 6A and 6B  are shown therein with common element numbers and will not be re-described herein. 
     The ET apparatus  98 B includes an ETIC  108 B. The ET apparatus  98 B differs from the ET apparatus  98 A of  FIG. 6A  in that the group delay optimization circuit  78  is configured to receive the ET voltage signal V CC  (also referred to as “a selected voltage signal among the ET target voltage signal V TARGET  and the ET voltage signal V CC ”) as the voltage signal  80 . 
     Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.