Patent Publication Number: US-6700160-B1

Title: Double-diffused MOS (DMOS) power transistor with a channel compensating implant

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor devices, and more particularly to a double-diffused MOS (DMOS) power transistor. 
     BACKGROUND OF THE INVENTION 
     In a conventional DMOS power transistor  10  formed with a single p-body implant  12 , as shown in FIG. 1, a trade-off exists between the threshold voltage (V T ) and the pinched-body sheet resistance. A low threshold voltage is attractive for ease of gate drive and low source-to-drain on-state resistance, necessitating a body region  14  with a low surface concentration and/or short channel. These attributes imply high body sheet resistance which makes the parasitic NPN bipolar transistor, shown at  16  with the p-body  12  as base, susceptible to easy turn-on. Activation of the parasitic bipolar transistor results in restricting the transistor safe operating area (SOA) of the power transistor  10 , and renders the power transistor unusable for simultaneous high current/high voltage application, when, for example, switching off an inductive load. 
     Other known ways of dealing with this trade-off are to use of a very deep p-type diffusion in addition to the p-body diffusion, and to use high energy MeV ion implantation to form a retrograde body. 
     SUMMARY OF THE INVENTION 
     The present invention achieves technical advantages as a double-diffused MOS (DMOS) power transistor having a channel compensating implant. A shallow n-type channel compensating implant (NCCI) is employed to decouple the p-body surface concentration and pinched body sheet resistance. The doping of the NCCI overcompensates the lighter doped portion of the graded p-body, making it n-type. This results in partial compensation of the heavy doped p-body near the transistor n+source, achieving a shorter, more lightly doped channel with the same heavy doped p-body beneath the n+transistor source. The power transistor of the present invention gives a more favorable trade-off between threshold voltage/on-state resistance and safe operating area. The NCCI allows a larger fraction of the transistor bias voltage to be supported on the thin gate oxide proximate the transistor gate. The present invention achieves further technical advantages as it can be fabricated using a self-aligned technique with a channel length that is insensitive to lithography techniques. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a side sectional view of a conventional DMOS power transistor formed with a single p-body implant and having a parasitic NPN bipolar transistor resulting in a restricted safe operating area (SOA); 
     FIG. 2 is a side sectional view of an improved DMOS power transistor according to the present invention including a shallow n-type channel compensating implant (NCCI); and 
     FIG. 3 is a numerical simulation showing the improved off-state breakdown voltage using the NCCI in the DMOS power transistor of FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 2, there is shown at  20  an improved power transistor suited for both high current/high voltage applications. In order to decouple the p-body surface concentration of the p-body well  12  and pinched body sheet resistance of channel region  22 , a shallow n-type channel compensating (NCCI) implant  24  is employed, as shown in FIG.  2 . The doping of the NCCI  24  is such that it overcompensates the lighter doped portion of the graded p-body, making it n-type. The heavy doped upper portion of the p-body  12  near the n+source is partially compensated. The result is a shorter, more lightly doped channel  22  while retaining the same heavy p-body doping beneath the n+transistor source. This gives the power transistor  20  a more favorable trade-off between threshold voltage V T /on-state resistance and safe operating area (SOA). 
     In one preferred embodiment, as shown in FIG. 2, the heavy doped p-body well  12  may have a doping of 1×10 17  to 5×10 18 /cm 3  and a depth of 0.7 to 2 um, a depth of 0.7 to 2 um, with the n+source well  26  having a doping of 0.1 to 0.5 um, and the n-well  28  having a doping of 8×10 15  to 2×10 17 /cm 3 . The NCCI  24  may preferably have a doping of 1×10 17  to 1×10 18 /cm 3 , a depth of 0.1 to 0.6 um, and a width of 0.5 to 5 um, with the NCCI  24  overlapping and overcompensating the upper shallow portion of the heavy doped p-body  12  as shown This example would have a pinched body resistance in the body region  12  of 1 to 5 kohm/sq. The transistor gate terminal is shown at  30  and may be formed of polysilicon. During the semiconductor fabrication process, the NCCI  24  is diffused after the FOX step, but before the deposition and etching of the polysilicon gate  30 . 
     Numerical simulation, displayed in FIG. 3, shows that the NCCI  24  also improves the off-state breakdown voltage BV DSS . The NCCI implant  24  allows a larger fraction of the gate bias voltage V T  to be supported on gate  30  on the thin gate oxide  32 . For a high NCCI dose, the region of maximum impact ionization shifts from the silicon/oxide surface to the body/well junction, which may be an advantage for robustness. 
     The present invention has an advantage over the use of a conventional very deep p-type diffusion because it can be fabricated using a self-aligned technique so the channel length is insensitive to lithography. In contrast, the conventional deep p-type diffusion must be offset from the p-body to avoid raising the surface (channel) concentration, and it is difficult to accurately put the deep p-type diffusion where it is needed (under the n+source) without influencing the surface concentration. Retrograde profiles require expensive MeV ion implanters. 
     Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications. For instance an NMOS transistor is shown and described in detail, but the principle of using a channel compensating implant could be employed in a PMOS transistor if desired using a p-type implant (PCCI).