Patent Publication Number: US-2016247902-A1

Title: Manufacturing method of oxide film and sputtering apparatus

Description:
TECHNICAL FIELD 
     One embodiment of the present invention relates to an oxide and a manufacturing method thereof. One embodiment of the present invention relates to a sputtering apparatus capable of depositing an oxide. 
     The present invention relates to, for example, an oxide, a transistor, a semiconductor device, and manufacturing methods thereof. The present invention relates to, for example, an oxide, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a processor, or an electronic device. The present invention relates to a manufacturing method of an oxide, a display device, a liquid crystal display device, a light-emitting device, a memory device, an imaging device, or an electronic device. The present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device. 
     Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. 
     In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an imaging device, an electro-optical device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases. 
     BACKGROUND ART 
     A technique for forming a transistor by using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is applied to a wide range of semiconductor devices such as an integrated circuit and a display device. Silicon is known as a semiconductor applicable to a transistor. 
     As silicon which is used as a semiconductor of a transistor, either amorphous silicon or polycrystalline silicon is used depending on the purpose. For example, in the case of a transistor included in a large display device, it is preferable to use amorphous silicon, which can be used to form a film on a large substrate with the established technique. In the case of a transistor included in a high-performance display device where a driver circuit and a pixel circuit are formed over the same substrate, it is preferred to use polycrystalline silicon, which can form a transistor having high field-effect mobility. It is known that polycrystalline silicon can be formed as a result of heat treatment at high temperatures or laser light treatment on amorphous silicon. 
     In recent years, transistors including oxide semiconductors (typified by an In—Ga—Zn oxide) have been actively developed. 
     Oxide semiconductors have been researched since early times. In 1988, it was disclosed to use an In—Ga—Zn oxide crystal for a semiconductor element (see Patent Document 1). In 1995, a transistor including an oxide semiconductor was invented, and its electrical characteristics were disclosed (see Patent Document 2). 
     In 2013, one group reported that an amorphous In—Ga—Zn oxide had an unstable structure in which crystallization is induced by irradiation with an electron beam (see Non-Patent Document 1). According to the report, no ordering was observed with a high-resolution transmission electron microscope in the amorphous In—Ga—Zn oxide formed by the group. 
     In 2014, a transistor including a crystalline In—Ga—Zn oxide that has more excellent electrical characteristics and higher reliability than a transistor including an amorphous In—Ga—Zn oxide was reported (see Non-Patent Document 2, Non-Patent Document 3, and Non-Patent Document 4). These documents reported that a grain boundary was not clearly observed in an In—Ga—Zn oxide including a c-axis aligned crystalline oxide semiconductor (CAAC-OS). 
     A crystalline In—Ga—Zn oxide can be deposited by a sputtering method. A sputtering method allows deposition on a large substrate. The in-plane variation in film thickness and film quality on a large substrate affects the yield of semiconductor devices, and therefore, techniques for reducing the variation in film thickness and film quality using a variety of methods have been proposed. For example, a sputtering apparatus in which a cathode can be swung is disclosed (see Patent Document 3). 
     REFERENCE 
     Patent Documents 
     
         
         [Patent Document 1] Japanese Published Patent Application No. S63-239117 
         [Patent Document 2] Japanese Translation of PCT International Application No. H11-505377 
         [Patent Document 3] Japanese Published Patent Application No. 2004-346388 
       
    
     Non-Patent Documents 
     
         
         [Non-Patent Document 1] T. Kamiya, K. Kimoto, N. Ohashi, K. Abe, Y. Hanyu, H. Kumomi, and H. Hosono, Proceedings of  The  20 th International Display Workshops,  2013, AMD2-5L 
         [Non-Patent Document 2] S. Yamazaki, H. Suzawa, K. Inoue, K. Kato, T. Hirohashi, K. Okazaki, and N. Kimizuka,  Japanese Journal of Applied Physics,  Vol. 53, 2014, 04ED18— 
         [Non-Patent Document 3] S. Yamazaki, T. Hirohashi, M. Takahashi, S. Adachi, M. Tsubuku, J. Koezuka, K. Okazaki, Y. Kanzaki, H. Matsukizono, S. Kaneko, S. Mori, and T. Matsuo,  Journal of the Society for Information Display,  Vol. 22, Issue 1, 2014, pp. 55-67 
         [Non-Patent Document 4] S. Yamazaki,  The Electrochemical Society Transactions,  Vol. 64(10), 2014, pp. 155-164 
       
    
     DISCLOSURE OF INVENTION 
     An object is to provide a film formation apparatus or a film formation method capable of forming a film on a large substrate. An object is to provide a film formation apparatus or a film formation method capable of forming a uniform film on a large substrate. An object is to provide a film formation apparatus or a film formation method capable of efficiently forming a film on a large substrate. An object is to provide a film formation apparatus or a film formation method capable of successively forming a plurality of kinds of films on a large substrate. An object is to provide an oxide having a novel crystal structure. An object is to provide an oxide having high crystallinity. An object is to provide an oxide having a low impurity concentration. An object is to provide a film formation apparatus capable of forming a film of the oxide. 
     Another object is to provide a semiconductor device using an oxide as a semiconductor. Another object is to provide a module including a semiconductor device using an oxide as a semiconductor. Another object is to provide an electronic device that includes a semiconductor device using an oxide as a semiconductor or includes a module including a semiconductor device using an oxide as a semiconductor. 
     Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor with high frequency characteristics. Another object is to provide a transistor having low off-state current. Another object is to provide a semiconductor device including any of the above transistors. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. 
     Note that the descriptions of these objects do not preclude the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the descriptions of the specification, the drawings, the claims, and the like. 
     (1) One embodiment of the present invention is a method for manufacturing an oxide using a sputtering apparatus including a target unit and a substrate holder. The target unit includes a first target, a second target, a first magnet, and a second magnet. The first magnet is located on a rear surface of the first target. The second magnet is located on a rear surface of the second target. The first target and the second target are located with a predetermined space therebetween so that front surfaces of the first target and the second target face each other. The substrate holder and a side of the target unit are located with a predetermined space therebetween. The method includes the steps of providing a substrate for the substrate holder, generating plasma including an ion between the first target and the second target by application of a potential to each of the first target and the second target, generating a sputtering particle including the oxide by a collision of the ion with the first target and the second target, and forming a film of the oxide (oxide film) by depositing the sputtering particle on the substrate while scanning (moving) is performed with the target unit in a direction parallel to a formation surface of the substrate. 
     (2) One embodiment of the present invention is a method for manufacturing an oxide using a sputtering apparatus including a first target unit, a second target unit, and a substrate holder. The first target unit includes a first target, a second target, a first magnet, and a second magnet. The second target unit includes a third target, a fourth target, a third magnet, and a fourth magnet. The first target and the second target are located with a predetermined space therebetween so that front surfaces of the first target and the second target face each other. The first magnet is located on a rear surface of the first target. The second magnet is located on a rear surface of the second target. The third magnet is located on a rear surface of the third target. The fourth magnet is located on a rear surface of the fourth target. The third target and the fourth target are located with a predetermined space therebetween so that front surfaces of the third target and the fourth target face each other. The substrate holder, a side of the first target unit, and a side of the second target unit are located with a predetermined space therebetween. The method includes the steps of providing a substrate for the substrate holder, generating plasma including an ion between the first target and the second target by application of a potential to each of the first target and the second target, generating a first sputtering particle including an oxide by a collision of the ion with the first target and the second target, generating plasma including an ion between the third target and the fourth target by application of a potential to each of the third target and the fourth target, generating a second sputtering particle including an oxide by a collision of the ion with the third target and the fourth target, and forming a film of the oxide by depositing the first sputtering particle and the second sputtering particle on the substrate while scanning (moving) is performed with the first target unit and the second target unit in a direction parallel to a formation surface of the substrate. 
     (3) One embodiment of the present invention is, in (2), the method for manufacturing an oxide in which the sputtering apparatus further includes a member having a slit and the member is located so that the slit is positioned between the first target unit and the substrate. 
     (4) One embodiment of the present invention is, in any one of (1) to (3), the method for manufacturing an oxide in which a surface temperature of the substrate during the step of forming the film of the oxide is higher than or equal to 100° C. and lower than 500° C. 
     (5) One embodiment of the present invention is a sputtering apparatus including a target unit and a substrate holder. The target unit includes a first target, a second target, a first magnet, and a second magnet. The first magnet is located on a rear surface of the first target. The second magnet is located on a rear surface of the second target. The first target and the second target are located with a predetermined space therebetween so that front surfaces of the first target and the second target face each other. The substrate holder and a side of the target unit are located with a predetermined space therebetween. The target unit is capable of moving in a direction parallel to the substrate holder. 
     (6) One embodiment of the present invention is a sputtering apparatus including a first target unit, a second target unit, and a substrate holder. The first target unit includes a first target, a second target, a first magnet, and a second magnet. The second target unit includes a third target, a fourth target, a third magnet, and a fourth magnet. The first target and the second target are located with a predetermined space therebetween so that front surfaces of the first target and the second target face each other. The first magnet is located on a rear surface of the first target. The second magnet is located on a rear surface of the second target. The third magnet is located on a rear surface of the third target. The fourth magnet is located on a rear surface of the fourth target. The third target and the fourth target are located with a predetermined space therebetween so that front surfaces of the third target and the fourth target face each other. The substrate holder, a side of the first target unit, and a side of the second target unit are located with a predetermined space therebetween. The first target unit and the second target unit are capable of moving in a direction parallel to the substrate holder. 
     (7) One embodiment of the present invention is, in (6), the sputtering apparatus further comprising a member having a slit and the member is located so that the slit is positioned between the first target unit and the substrate. 
     (8) One embodiment of the present invention is, in any one of (5) to (7), the sputtering apparatus further includes a heating mechanism on a rear surface of the substrate holder. 
     A film formation apparatus capable of forming a film on a large substrate can be provided. A film formation apparatus capable of forming a uniform film on a large substrate can be provided. A film formation apparatus capable of efficiently forming a film on a large substrate can be provided. A film formation apparatus capable of successively forming a plurality of kinds of films on a large substrate can be provided. An oxide having a novel crystal structure can be provided. An oxide having high crystallinity can be provided. An oxide having a low impurity concentration can be provided. A film formation apparatus capable of forming a film of the oxide can be provided. 
     A semiconductor device using an oxide as a semiconductor can be provided. A module including a semiconductor device using an oxide as a semiconductor can be provided. An electronic device that includes a semiconductor device using an oxide as a semiconductor or includes a module including a semiconductor device using an oxide as a semiconductor can be provided. 
     A transistor with favorable electrical characteristics can be provided. A transistor with stable electrical characteristics can be provided. A transistor with high frequency characteristics can be provided. A transistor having low off-state current can be provided. A semiconductor device including any of the above transistors can be provided. A module including the semiconductor device can be provided. An electronic device including the semiconductor device or the module can be provided. 
     Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  illustrates a deposition method of a CAAC-OS. 
         FIGS. 2A to 2C  illustrate an InMZnO 4  crystal and a pellet. 
         FIGS. 3A to 3D  illustrate a deposition method of a CAAC-OS. 
         FIGS. 4A to 4F  illustrate a deposition method of a CAAC-OS. 
         FIGS. 5A to 5G  illustrate positions to which particles can be attached in a pellet. 
         FIGS. 6A to 6G  illustrate positions to which particles can be attached in a pellet. 
         FIG. 7  is a triangular diagram for explaining composition of an In-M-Zn oxide. 
         FIG. 8  illustrates a sputtering apparatus. 
         FIG. 9  illustrates a sputtering apparatus. 
         FIG. 10  illustrates a sputtering apparatus. 
         FIG. 11  illustrates a sputtering apparatus. 
         FIGS. 12A and 12B  each illustrate a sputtering apparatus. 
         FIG. 13  illustrates a sputtering apparatus. 
         FIG. 14  illustrates a sputtering apparatus. 
         FIGS. 15A and 15B  each illustrate a sputtering apparatus. 
         FIG. 16  is a top view illustrating an example of a deposition apparatus. 
         FIGS. 17A to 17C  are cross-sectional views each illustrating an example of a deposition apparatus. 
         FIGS. 18A to 18C  are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention. 
         FIGS. 19A to 19F  are cross-sectional views illustrating transistors of one embodiment of the present invention. 
         FIGS. 20A to 20F  are cross-sectional views illustrating transistors of one embodiment of the present invention. 
         FIG. 21  is a band diagram of a region including an oxide semiconductor of one embodiment of the present invention. 
         FIGS. 22A to 22C  are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention. 
         FIGS. 23A to 23F  are cross-sectional views illustrating transistors of one embodiment of the present invention. 
         FIGS. 24A to 24F  are cross-sectional views illustrating transistors of one embodiment of the present invention. 
         FIGS. 25A to 25C  are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention. 
         FIGS. 26A to 26F  are cross-sectional views illustrating transistors of one embodiment of the present invention. 
         FIGS. 27A and 27B  are circuit diagrams each illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 28A to 28C  are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 29A to 29C  are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 30A to 30C  are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 31A and 31B  are circuit diagrams each illustrating a memory device of one embodiment of the present invention. 
         FIGS. 32A to 32C  are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 33A to 33C  are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 34A to 34C  are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 35A and 35B  are top views each illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 36A and 36B  are block diagrams each illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 37A and 37B  are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 38A and 38B  are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 39A and 39B  are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention. 
       FIGS.  40 A 1 ,  40 A 2 ,  40 A 3 ,  40 B 1 ,  40 B 2 , and  40 B 3  are perspective views and cross-sectional views illustrating semiconductor devices of one embodiment of the present invention. 
         FIG. 41  is a block diagram illustrating a semiconductor device of one embodiment of the present invention. 
         FIG. 42  is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 43A to 43C  are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 
         FIG. 44  is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 45A and 45B  are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 
         FIGS. 46A to 46F  are perspective views each illustrating an electronic device of one embodiment of the present invention. 
         FIGS. 47A to 47D  are Cs-corrected high-resolution TEM images of a cross section of a CAAC-OS and a cross-sectional schematic view of a CAAC-OS. 
         FIGS. 48A to 48D  are Cs-corrected high-resolution TEM images of a plane of a CAAC-OS. 
         FIGS. 49A to 49C  show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD. 
         FIGS. 50A and 50B  show electron diffraction patterns of a CAAC-OS. 
         FIG. 51  shows a change in crystal part of an In—Ga—Zn oxide induced by electron irradiation. 
     
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     Hereinafter, embodiments and examples of the present invention will be described in detail with the reference to the drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways. Furthermore, the present invention is not construed as being limited to description of the embodiments and the examples. In describing structures of the present invention with reference to the drawings, common reference numerals are used for the same portions in different drawings. Note that the same hatched pattern is applied to similar parts, and the similar parts are not denoted by reference numerals in some cases. In the case where the description of a component denoted by a different reference numeral is referred to, the description of the thickness, composition, structure, shape, or the like of the component can be used as appropriate. 
     Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity. 
     In this specification, the terms “film” and “layer” can be interchanged with each other. 
     A voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a source potential or a ground potential (GND)). A voltage can be referred to as a potential and vice versa. Note that in general, a potential (a voltage) is relative and is determined depending on the amount relative to a certain potential. Therefore, a potential which is represented as a “ground potential” or the like is not always 0 V. For example, the lowest potential in a circuit may be represented as a “ground potential.” Alternatively, a substantially intermediate potential in a circuit may be represented as a “ground potential.” In these cases, a positive potential and a negative potential are set using the potential as a reference. 
     The ordinal numbers such as “first” and “second” are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second,” “third,” or the like as appropriate. In addition, the ordinal numbers in this specification and the like do not correspond to the ordinal numbers which specify one embodiment of the present invention in some cases. 
     Note that an impurity in a semiconductor refers to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of lower than 0.1 atomic % is regarded as an impurity. When an impurity is contained, the density of states (DOS) may be formed in a semiconductor, the carrier mobility may be decreased, or the crystallinity may be decreased. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specifically, there are hydrogen (included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. In the case of an oxide semiconductor, oxygen vacancies may be formed by entry of impurities such as hydrogen. In the case where the semiconductor is a silicon layer, examples of an impurity which changes characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements. 
     Note that the channel length refers to, for example, a distance between a source (source region or source electrode) and a drain (drain region or drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed. 
     The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed. 
     Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width) in some cases. For example, in a transistor having a three-dimensional structure, an effective channel width is greater than an apparent channel width shown in a top view of the transistor, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel formation region formed in a side surface of a semiconductor is increased in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view. 
     In a transistor having a three-dimensional structure, an effective channel width is difficult to measure in some cases. For example, estimation of an effective channel width from a design value requires an assumption that the shape of a semiconductor is known. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately. 
     Therefore, in this specification, in a top view of a transistor, an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like. 
     Note that in the case where field-effect mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, the values may be different from those calculated using an effective channel width in some cases. 
     Note that in this specification, the description “A has a shape such that an end portion extends beyond an end portion of B” may indicate, for example, the case where at least one of end portions of A is positioned on an outer side than at least one of end portions of B in a top view or a cross-sectional view. Thus, the description “A has a shape such that an end portion extends beyond an end portion of B” can be read as the description “one end portion of A is positioned on an outer side than one end portion of B in a top view,” for example. 
     In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. A term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. A term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°. 
     In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system. 
     Note that in this specification, “oxide semiconductor” can be replaced with another semiconductor in some cases. For example, “oxide semiconductor” can be replaced with a Group 14 semiconductor such as silicon or germanium, a compound semiconductor such as silicon carbide, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, or cadmium sulfide; or an organic semiconductor can be used. 
     &lt;Deposition Method&gt; 
     An example of a deposition model of a CAAC-OS using a sputtering method will be described below. 
     A target  230  is provided in a deposition chamber as illustrated in  FIG. 1 . The target  230  is attached to a backing plate  210 . A magnet  250  is placed to overlap with the target  230  with the backing plate  210  positioned therebetween. The deposition chamber is mostly filled with a deposition gas (e.g., oxygen, argon, or a mixed gas containing oxygen at 5 volume % or higher) and the pressure in the deposition chamber is controlled to be higher than or equal to 0.01 Pa and lower than or equal to 100 Pa, and preferably higher than or equal to 0.1 Pa and lower than or equal to 10 Pa. Here, discharge starts by voltage application at a certain value or higher to the target  230 , and plasma can be observed. A magnetic field of the magnet  250  forms a high-density plasma region in the vicinity of the target  230 . In the high-density plasma region, the deposition gas is ionized, so that an ion  201  is generated. A sputtering method in which the deposition rate is increased by utilizing a magnetic field of a magnet is referred to as a magnetron sputtering method. Examples of the ion  201  include an oxygen cation (O + ) and an argon cation (Ar + ). 
     Here, the target  230  has a polycrystalline structure which includes a plurality of crystal grains. A cleavage plane exists in any of the crystal grains.  FIG. 2A  shows a crystal structure of InMZnO 4  (M is an element such as aluminum, gallium, yttrium, or tin) included in the target  230  as an example. Note that  FIG. 2A  illustrates the crystal structure of InMZnO 4  observed from a direction parallel to the b-axis. In the crystal of InMZnO 4 , oxygen atoms are negatively charged, whereby a repulsive force is generated between two adjacent M-Zn—O layers. Thus, the InMZnO 4  crystal has a cleavage plane between two adjacent M-Zn—O layers. 
     The ion  201  generated in the high-density plasma region is accelerated toward the target  230  side by an electric field, and then collides with the target  230 . At this time, a pellet  200 , which is a flat-plate-like or pellet-like sputtered particle, is separated from the cleavage plane. Note that along with the separation of the pellet  200 , particles  203  are sputtered from the target  230 . The particles  203  each have an atom or an aggregate of several atoms. Thus, the particles  203  can be referred to as atomic particles. 
     Cleavage at a surface of the target is described with reference to cross-sectional views in  FIGS. 3A to 3D .  FIG. 3A  is a cross-sectional view of the target  230  having a cleavage plane (indicated by a dashed line). When the ion  201  collides with the target  230 , bonds are sequentially cut from an end portion of the cleavage plane (see  FIG. 3B ). The cleaved surfaces repel each other because of the existence of charges with the same polarity. For this reason, rebinding does not occur once the bond is cut. As repellency due to charges proceeds, a region where bonds are cut gradually expands (see  FIG. 3C ). In the end, the pellet  200  is separated from the target  230  (see  FIG. 3D ). The pellet  200  corresponds to a portion between any two adjacent cleavage planes illustrated in  FIG. 2A . Thus, when the pellet  200  is observed, the cross-section thereof is as illustrated in  FIG. 2B , and the top surface thereof is as illustrated in  FIG. 2C . Note that the structure of the pellet  200  may be distorted by an impact of collision with the ion  201 . 
     The pellet  200  is a flat-plate-like (pellet-like) sputtered particle having a triangle plane, e.g., a regular triangle plane. Alternatively, the pellet  200  is a flat-plate-like (pellet-like) sputtered particle having a hexagon plane, e.g., regular hexagon plane. However, the shape of a flat plane of the pellet  200  is not limited to a triangle or a hexagon. 
     The thickness of the pellet  200  is determined in accordance with the kind of the deposition gas and the like. The thickness of the pellet  200  is, for example, greater than or equal to 0.4 nm and less than or equal to 1 nm, and preferably greater than or equal to 0.6 nm and less than or equal to 0.8 nm. In addition, the width of the pellet  200  is, for example, greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 1 nm and less than or equal to 50 nm, and further preferably greater than or equal to 1 nm and less than or equal to 30 nm, and still further preferably greater than or equal to 1 nm and less than or equal to 6 nm. 
     A surface of the pellet  200  might be negatively or positively charged when the pellet  200  receives a charge from plasma. In the case where the pellet  200  receives a negative charge from O 2−  in plasma, for example, an oxygen atom on the surface of the pellet  200  is negatively charged. A lateral growth might occur when the particles  203  are attached and bonded to a side surface of the pellet  200  in plasma. 
     The pellet  200  and the particles  203  that have passed through plasma reach a surface of a substrate  220 . Note that some of the particles  203  are discharged to the outside by a vacuum pump or the like because of their smallness in mass. 
     Here, deposition of the pellets  200  and the particles  203  on the surface of the substrate  220  will be described with reference to  FIGS. 4A to 4F . 
     First, a first pellet  200  is deposited on the substrate  220 . Since the pellet  200  has a flat-plate-like shape, it is deposited with its flat plane facing the surface of the substrate  220 . At this time, a charge on a surface of the pellet  200  on the substrate  220  side is lost through the substrate  220 . 
     Next, a second pellet  200  reaches the substrate  220 . Since a surface of the first pellet  200  and a surface of the second pellet  200  are charged, they repel each other. As a result, the second pellet  200  avoids being deposited over the first pellet  200 , and is deposited with its flat plane facing the surface of the substrate  220  so as to be a little distance away from the first pellet  200 . With repetition of this, millions of the pellets  200  are deposited on the surface of the substrate  220  to have a thickness of one layer. A region where no pellet  200  is deposited is generated between adjacent pellets  200  (see  FIG. 4A ). 
     Then, the particles  203  that have received energy from plasma reach the surface of the substrate  220 . The particles  203  cannot be deposited on an active region such as the surfaces of the pellets  200 . For this reason, the particles  203  move to regions where no pellet  200  is deposited and are attached to side surfaces of the pellets  200 . By energy received from plasma, available bonds of the particles  203  are brought into an active state where chemical bond is easily formed, so that the particles  203  are chemically bonded to the pellets  200  to form lateral growth portions  202  (see  FIG. 4B ). The lateral growth portions  202  then promote a lateral growth so that the pellets  200  are anchored to each other (see  FIG. 4C ). In this manner, the lateral growth portions  202  are formed until they fill regions where no pellet  200  is deposited. This mechanism is similar to a deposition mechanism for an atomic layer deposition (ALD) method. 
     Even when the deposited pellets  200  are oriented in different directions, the particles  203  cause a lateral growth to fill gaps between the pellets  200 ; thus, no clear grain boundary is formed. In addition, as the particles  203  make a smooth connection between the pellets  200 , a crystal structure different from single crystal and polycrystal structures is formed. In other words, a crystal structure including distortion between minute crystal regions (pellets  200 ) is formed. Regions filling the gaps between the crystal regions are distorted crystal regions, and thus, it will be not appropriate to say that the regions have an amorphous structure. 
     Next, new pellets  200  are deposited with their flat planes facing the surface of the substrate  220  (see  FIG. 4D ). After that, the particles  203  are deposited so as to fill regions where no pellet  200  is deposited, thereby forming the lateral growth portions  202  (see  FIG. 4E ). In such a manner, the particles  203  are attached to side surfaces of the pellets  200  and the lateral growth portions  202  cause a lateral growth so that the pellets  200  in the second layer are anchored to each other (see  FIG. 4F ). Deposition continues until the m-th layer (m is an integer of two or more) is formed; as a result, a stacked-layer thin film structure is formed. 
     A deposition way of the pellets  200  changes according to the surface temperature of the substrate  220  or the like. For example, if the surface temperature of the substrate  220  is high, migration of the pellets  200  occurs on the surface of the substrate  220 . As a result, a proportion of the pellets  200  that are directly connected to each other without the particles  203  increases, whereby a CAAC-OS with higher orientation is made. The surface temperature of the substrate  220  for deposition of the CAAC-OS is higher than or equal to 100° C. and lower than 500° C., preferably higher than or equal to 140° C. and lower than 450° C., and further preferably higher than or equal to 170° C. and lower than 400° C. Therefore, even when a large-sized substrate of the 8th generation or more is used as the substrate  220 , a warp or the like due to the deposition of the CAAC-OS hardly occurs. 
     In contrast, if the surface temperature of the substrate  220  is low, the migration of the pellets  200  does not easily occur on the substrate  220 . As a result, the pellets  200  are stacked to form a nanocrystalline oxide semiconductor (nc-OS) or the like with low orientation. In the nc-OS, the pellets  200  are possibly deposited with certain gaps because the pellets  200  are negatively charged. Therefore, the nc-OS has low orientation but some regularity, and thus has a denser structure than an amorphous oxide semiconductor. 
     When gaps between pellets are extremely small in a CAAC-OS, the pellets may form a large pellet. The inside of the large pellet has a single crystal structure. the size of the pellet when seen from the above may be, for example, greater than or equal to 10 nm and less than or equal to 200 nm, greater than or equal to 15 nm and less than or equal to 100 nm, or greater than or equal to 20 nm and less than or equal to 50 nm. 
     The pellets are considered to be deposited on a surface of a substrate according to such a deposition model. A CAAC-OS can be deposited even when a formation surface does not have a crystal structure. This indicates that the above-described deposition model, which is a growth mechanism different from an epitaxial growth, has high validity. In addition, with the above-described deposition model, a uniform film of a CAAC-OS or an nc-OS can be formed even over a large-sized glass substrate or the like. Even when the surface of the substrate (formation surface) has an amorphous structure (e.g., amorphous silicon oxide), for example, a CAAC-OS can be formed. 
     In addition, even when the surface of the substrate (formation surface) has an uneven shape, the pellets are aligned along the shape. 
     The above-described deposition model suggests that a CAAC-OS with high crystallinity can be formed in the following manner: deposition is performed in high vacuum to have a long mean free path, plasma energy is weakened to reduce damage around a substrate, and thermal energy is applied to a formation surface to repair damage due to plasma during deposition. 
     The above is the description of the case of a flat plate pellet. In contrast, in the case of a cubic pellet or a columnar pellet that has a small width, for example, pellets that reached a surface of a substrate are oriented in various directions. Then, particles are attached to side surfaces of the deposited pellets while the orientations of the pellets are varied, and lateral growth portions cause a lateral growth. The crystal orientation in the resulting thin film might not be uniform. 
     The above-described deposition model can be used not only for the case where a target has a polycrystalline structure of a composite oxide (such as an In-M-Zn oxide) with a plurality of crystal grains, and any of the crystal grains have a cleavage plane; but also for the case where, for example, a target of a mixture containing indium oxide, an oxide of the element M, and zinc oxide is used. 
     Since there is no cleavage plane in a target of a mixture, atomic particles are separated from the target by sputtering. During deposition, a high electric field region of plasma is formed around a target. Because of the high electric field region of plasma, atomic particles separated from the target are anchored to each other to cause a lateral growth. For example, indium atoms, which are atomic particles, are anchored to each other and cause a lateral growth to be a nanocrystal formed of an In—O layer, and then an M-Zn—O layer is bonded above and below the nanocrystalline In—O layer so as to complete the nanocrystalline In—O layer. In this manner, a pellet can be formed even when a target of a mixture is used. Accordingly, the above-described deposition model can also be applied to the case of using a target of a mixture. 
     Note that in the case where a high electric field region of plasma is not formed around a target, only atomic particles separated from the target are deposited on a substrate surface. In that case, a lateral growth of an atomic particle might occur on the substrate surface. However, since the orientations of atomic particles are not the same, the crystal orientation in the resulting thin film is not uniform. As a result, an nc-OS or the like is obtained. 
     &lt;Lateral Growth&gt; 
     The following description explains that a lateral growth occurs when the particles  203  are attached to (bonded to or adsorbed on) the pellet  200  laterally. 
       FIGS. 5A to 5E  each illustrate a structure of the pellet  200  and a position to which a metal ion can be attached. A model assumed as the pellet  200  is a cluster model with 84 atoms extracted from an InMZnO 4  crystal structure with a constant stoichiometric composition. Note that the following description is made on the assumption that the element M is gallium.  FIG. 5F  illustrates a structure of the pellet  200  seen in the direction parallel to the c-axis.  FIG. 5G  illustrates a structure of the pellet  200  seen in the direction parallel to the a-axis. 
     The positions to which metal ions can be attached are represented as a position A, a position B, a position a, a position b, and a position c. The position A is an upper part of an interstitial site surrounded by one gallium atom and two zinc atoms on the top surface of the pellet  200 . The position B is an upper part of an interstitial site surrounded by two gallium atoms and one zinc atom on the top surface of the pellet  200 . The position a is in an indium site on a side surface of the pellet  200 . The position b is in an interstitial site between an In—O layer and a Ga—Zn—O layer on a side surface of the pellet  200 . The position c is in a gallium site on a side surface of the pellet  200 . 
     The relative energy was estimated from first principles calculation in each case where a metal ion was located in the assumed position (the position A, the position B, the position a, the position b, or the position c). In the calculation, first principles calculation software VASP (Vienna Ab initio Simulation Package) was used. For the exchange-correlation potential, Perdew-Burke-Ernzerhof (PBE) type generalized gradient approximation (GGA) was used, and for the ion potential, a projector augmented wave (PAW) method was used. The cut-off energy was 400 eV, and F-only k-point sampling was used. The table below shows the relative energies in the case where an indium ion (In 3+ ), a gallium ion (Ga 3+ ), and a zinc ion (Zn 2+ ) are located at the position A, the position B, the position a, the position b, and the position c. Note that the relative energy is a relative value under the condition where the energy of the model with the lowest energy among the calculated models is set to 0 eV. 
     
       
         
           
               
               
             
               
                   
                 TABLE 1 
               
             
            
               
                   
                   
               
               
                   
                 Relative energy [eV] 
               
            
           
           
               
               
               
            
               
                   
                 Top surface of 
                   
               
               
                   
                 pellet 
                 Side surface of pellet 
               
            
           
           
               
               
               
               
               
               
               
            
               
                   
                 Ion 
                 A 
                 B 
                 a 
                 b 
                 c 
               
               
                   
                   
               
               
                   
                 In 3+   
                 2.1 
                 1.5 
                 0.0 
                 1.8 
                 1.9 
               
               
                   
                 Ga 3+   
                 3.7 
                 3.0 
                 0.6 
                 0.0 
                 3.5 
               
               
                   
                 Zn 2+   
                 2.3 
                 1.8 
                 0.0 
                 0.6 
                 2.9 
               
               
                   
                   
               
            
           
         
       
     
     It is found that any metal ion is more likely to be attached to the side surface of the pellet  200  than to the top surface thereof. It is also found that a zinc ion as well as an indium ion is most likely to be attached to the indium site at the position a. 
     Ease of oxygen ion (O 2− ) attachment to the pellet  200  was examined.  FIGS. 6A to 6E  each illustrate a structure of the pellet  200  and a position to which an oxygen ion can be attached.  FIG. 6F  illustrates a structure of the pellet  200  seen in the direction parallel to the c-axis.  FIG. 6G  illustrates a structure of the pellet  200  seen in the direction parallel to the b-axis. 
     The positions to which oxygen ions can be attached are represented as a position C, a position D, a position d, a position e, and a position f. In the position C, an oxygen ion is bonded to gallium on the top surface of the pellet  200 . In the position D, an oxygen ion is bonded to zinc on the top surface of the pellet  200 . In the position d, an oxygen ion is bonded to indium on a side surface of the pellet  200 . In the position e, an oxygen ion is bonded to gallium on a side surface of the pellet  200 . In the position f, an oxygen ion is bonded to zinc on a side surface of the pellet  200 . 
     The relative energy was estimated from first principles calculation in each case where an oxygen ion was located in the assumed position (the position C, the position D, the position d, the position e, or the position f). The table below shows the relative energies in the case where oxygen ions (O 2− ) are located at the position C, the position D, the position d, the position e, and the position f. 
     
       
         
           
               
               
             
               
                   
                 TABLE 2 
               
             
            
               
                   
                   
               
               
                   
                 Relative energy [eV] 
               
            
           
           
               
               
               
            
               
                   
                 Top surface of 
                   
               
               
                   
                 pellet 
                 Side surface of pellet 
               
            
           
           
               
               
               
               
               
               
               
            
               
                   
                 Ion 
                 C 
                 D 
                 d 
                 e 
                 f 
               
               
                   
                   
               
               
                   
                 O 2−   
                 3.9 
                 3.6 
                 0.0 
                 0.5 
                 1.5 
               
               
                   
                   
               
            
           
         
       
     
     It is found that the oxygen ion is also likely to be attached to the side surface of the pellet  200  than to the top surface thereof. 
     According to the above, the particle  203  that has approached the pellet  200  is preferentially attached to the side surface of the pellet  200 . This suggests that the deposition model in which a lateral growth of the pellet  200  occurs when the particles  203  are attached to the side surface of the pellet  200  has high validity. 
     &lt;Composition&gt; 
     The composition of an In-M-Zn oxide is described below. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements which can be used as the element M are boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like. 
       FIG. 7  is a ternary diagram whose vertices represent In, M, and Zn. In the diagram, [In] means the atomic concentration of In, [M] means the atomic concentration of the element M, and [Zn] means the atomic concentration of Zn. 
     A crystal of an In-M-Zn oxide is known to have a homologous structure and is represented by InMO 3 (ZnO) m  (m is a natural number). Since In and M can be interchanged, the crystal can also be represented by In 1+α M 1−α O 3 (ZnO) m . This composition is represented by any of the dashed lines denoted as [In]:[M]:[Zn]=1+α:1−α:1, [In]:[M]:[Zn]=1+α:1−α:2, [In]:[M]:[Zn]=1+α:1−α:3, [In]:[M]:[Zn]=1+α:1−α:4, and [In]:[M]:[Zn]=1+α:1−α:5. Note that the bold line on the dashed line represents, for example, the composition that allows an oxide as a raw material mixed and subjected to baking at 1350° C. to be a solid solution. 
     Thus, when an oxide has a composition close to the above composition that allows the oxide to be a solid solution, the crystallinity can be increased. When an In-M-Zn oxide is deposited by a sputtering method, the composition of a target might be different from the composition of a deposited film. For example, using an In-M-Zn oxide in which an atomic ratio is 1:1:1, 1:1:1.2, 3:1:2, 4:2:4.1, 1:3:2, 1:3:4, or 1:4:5 as a target results in a film having an atomic ratio of 1:1:0.7 (approximately 1:1:0.5 to 1:1:0.9), 1:1:0.9 (approximately 1:1:0.8 to 1:1:1.1), 3:1:1.5 (approximately 3:1:1 to 3:1:1.8), 4:2:3 (approximately 4:2:2.6 to 4:2:3.6), 1:3:1.5 (approximately 1:3:1 to 1:3:1.8), 1:3:3 (approximately 1:3:2.5 to 1:3:3.5), or 1:4:4 (approximately 1:4:3.4 to 1:4:4.4). Thus, in order to obtain a film with a desired composition, a composition of a target may be selected in consideration of a change in the composition. The sputtering apparatus described in this embodiment can reduce a difference between the composition of the target and the composition of the film to be deposited. 
     &lt;Sputtering Apparatus&gt; 
     A facing-targets sputtering apparatus of one embodiment of the present invention will be described below. As will be described later, deposition using a facing-targets sputtering apparatus causes less damage to a formation surface and thus facilitates the formation of a film with high crystallinity. For this reason, a facing-targets sputtering apparatus is preferably used for the deposition of the CAAC-OS in some cases. The following descriptions of the sputtering apparatuses are made for easy understanding or the explanation of the operation during deposition, on the assumption that a substrate, a target, and the like are provided. Note that the substrate, the target, and the like are provided by a user; thus, the sputtering apparatus of one embodiment of the present invention does not necessarily include the substrate and the target. 
     Deposition using a facing-targets sputtering apparatus can also be referred to as vapor deposition sputtering (VDSP). 
       FIG. 8  shows an example of a facing-targets sputtering apparatus. 
       FIG. 8  is a schematic cross-sectional view of a deposition chamber of the sputtering apparatus. In the deposition chamber illustrated in  FIG. 8 , a target  100   a,  a target  100   b,  a backing plate  110   a  for holding the target  100   a,  a backing plate  110   b  for holding the target  100   b,  a magnet unit  130   a  provided for a rear surface of the target  100   a  with the backing plate  110   a  positioned therebetween, and a magnet unit  130   b  provided for a rear surface of the target  100   b  with the backing plate  110   b  positioned therebetween are provided. When a substrate  160  is transferred into the deposition chamber, the substrate  160  is fixed by a substrate holder  170 . A heating mechanism  180  is provided for a rear surface of the substrate holder  170 . 
     As illustrated in  FIG. 8 , a power source  190  for applying potentials is connected to the backing plates  110   a  and  110   b.  It is preferable to use, as the power source  190 , an AC power source which inversely applies alternate high and low potentials between the backing plate  110   a  and the backing plate  110   b.  Although an AC power source is used as the power source  190  illustrated in  FIG. 8 , one embodiment of the present invention is not limited thereto. For example, an RF power source, a DC power source, or the like can be used as the power source  190 . 
     The substrate holder  170  is preferably connected to GND. The substrate holder  170  may be floating. 
     The target shields  122   a  and  122   b  are connected to the GND. That is, a difference is caused between a potential applied between the backing plates  110   a  and  110   b  supplied with a potential of the power source  190  and a potential applied between the target shields  122   a  and  122   b  supplied with GND, whereby plasma  140  is generated. 
     Note that the sputtering apparatus includes two target holders (not shown). One of the two target holders and one of the backing plates  110   a  and  110   b  are fixed to each other with a screw (e.g., a bolt) and have the same potential. The other target holder and the other backing plate are fixed to each other with a screw (e.g., a bolt) and have the same potential. The target holder has a function of supporting the target  100   a  ( 100   b ) with the backing plate  110   a  ( 110   b ) positioned therebetween. 
     The target  100   a  and the target  100   b  are fixed to the backing plate  110   a  and the backing plate  110   b,  respectively. The target  100   a  and the target  100   b  can be fixed to the backing plate  110   a  and the backing plate  110   b,  respectively, using a bonding material containing a low-melting-point metal such as indium, for example. 
     The deposition chamber may have a water channel inside or under the backing plate  110   a  and the backing plate  110   b.  Making fluid (air, nitrogen, a rare gas, water, oil, or the like) flow through the water channel can prevent discharge anomaly due to an increase in the temperature of the target  100 , damage to the deposition chamber due to deformation of a component, and the like in the sputtering. 
     The vertical distance between the target  100   a  and/or the target  100   b  and the substrate  160  is greater than or equal to 10 mm and less than or equal to 600 mm, preferably greater than or equal to 20 mm and less than or equal to 400 mm, further preferably greater than or equal to 30 mm and less than or equal to 200 mm, still further preferably greater than or equal to 40 mm and less than or equal to 100 mm. When the vertical distance between the target  100   a  and/or the target  100   b  and the substrate  160  is set small, a decrease in the energy of the sputtered particles until the sputtered particles reach the substrate  160  can be suppressed in some cases. When the vertical distance between the target  100   a  and/or the target  100   b  and the substrate  160  is set large, the incident direction of the sputtered particle can be approximately vertical to the substrate  160 , so that damage to the substrate  160  caused by collision of the sputtered particles can be reduced in some cases. 
     The facing-targets sputtering apparatus can stably generate plasma even in high vacuum. Thus, deposition can be performed at a pressure higher than or equal to 0.005 Pa and lower than or equal to 0.09 Pa, for example. As a result, the concentration of impurities contained during deposition can be reduced. 
     To further increase the crystallinity of the film to be formed, the temperature of the substrate  160  may be set high. By setting the temperature of the substrate  160  high, migration of sputtered particles at the substrate  160  can be promoted. Thus, a film with higher density and higher crystallinity can be deposited. Note that the temperature of the substrate  160  is, for example, higher than or equal to 100° C. and lower than or equal to 450° C., preferably higher than or equal to 150° C. and lower than or equal to 400° C., more preferably higher than or equal to 170° C. and lower than or equal to 350° C. 
     The use of the facing-targets sputtering apparatus allows deposition in high vacuum or deposition with less plasma damage and thus can provide a film with high crystallinity even when the temperature of the substrate  160  is low (e.g., higher than or equal to 10° C. and lower than 100° C.). 
     When the partial pressure of oxygen in the deposition gas is too high, a film including plural kinds of crystal phases is likely to be deposited; therefore, a mixed gas of oxygen and a rare gas such as argon (other examples of the rare gas are helium, neon, krypton, and xenon) is preferably used as the deposition gas. For example, the proportion of oxygen in the whole deposition gas is less than 50 vol %, preferably less than or equal to 33 vol %, further preferably less than or equal to 20 vol %, and still further preferably less than or equal to 15 vol %. 
     Note that the deposition is preferably performed while the plasma  140  completely reaches the surface of the substrate  160 . 
     In  FIG. 8 , the target  100   a  and the target  100   b  are placed parallel to each other such that the front surfaces thereof face laterally and opposite each other. At this time, the targets  100   a  and  100   b  can be collectively referred to as a pair of targets. Moreover, the magnet unit  130   a  and the magnet unit  130   b  are placed so that opposite poles face each other. At this time, a magnetic force line is from the magnet unit  130   b  toward the magnet unit  130   a.  Thus, a high-density region of the plasma  140  is confined by magnetic fields formed by the magnet unit  130   a  and the magnet unit  130   b  during deposition. The substrate holder  170  is placed above or below the target  100   a  and the target  100   b.  Note that although the substrate holder  170  and the substrate  160  are placed parallel to the direction in which the target  100   a  and the target  100   b  face each other in  FIG. 8 , the substrate holder  170  and the substrate  160  may be inclined to the direction. By inclination of the substrate holder  170  and the substrate  160  at 30° or more and 60° or less ( ) ypified by 45°), for example, the proportion of sputtered particles that perpendicularly reach the substrate  160  during deposition can be increased. 
     The structure illustrated in  FIG. 9  is different from that illustrated in  FIG. 8  in that the target  100   a  and the target  100   b  that face each other are not parallel but inclined to each other so that the distance between the upper sides of the targets is longer than that between the lower sides thereof (in a V shape). Thus, the description for  FIG. 8  is referred to for the description except for the positions of the targets. The magnet unit  130   a  and the magnet unit  130   b  are placed so that opposite poles face each other. The substrate holder  170  is placed above the target  100   a  and the target  100   b.  Note that the target  100   a  and the target  100   b  that face each other may be inclined to each other so that the distance between the lower sides of the targets is longer than that between the upper sides thereof (in an inverted V shape). In that case, the substrate holder  170  is placed below the target  100   a  and the target  100   b.    
     In the examples shown in  FIG. 8  and  FIG. 9 , the substrate holder is provided above or below a region between the targets. As another example, a substrate holder  170   a  and a substrate holder  170   b  may be provided above and below the region between the targets (see FIG.  10 ). A substrate  160   a  and a substrate  160   b  are fixed to the substrate holder  170   a  and the substrate holder  170   b,  respectively. A heating mechanism  180   a  is provided for a rear surface of the substrate holder  170   a,  and a heating mechanism  180   b  is provided for a rear surface of the substrate holder  170   b.  When the substrate holders are provided above and below the region, deposition on two or more substrates can be performed at once, leading to an increase in productivity. Note that the position above or below the region where the target  100   a  and the target  100   b  face each other can also be referred to as the side of the region where the target  100   a  and the target  100   b  face each other. 
     In the above-described facing-targets sputtering apparatuses, plasma is confined by magnetic fields between targets; thus, plasma damage to a substrate can be reduced. Furthermore, a deposited film can have improved step coverage because an incident angle of a sputtered particle to a substrate can be made smaller by the inclination of the target. Moreover, deposition in high vacuum enables the concentration of impurities contained in the film to be reduced. 
       FIG. 11  is a perspective view of a facing-targets sputtering apparatus of one embodiment of the present invention. Hereinafter, a group including a pair of targets (the target  100   a  and the target  100   b  here) and a pair of magnets (the magnet unit  130   a  and the magnet unit  130   b  here) is referred to as a target unit  150   a  for convenience. Other components of the target unit  150   a  are omitted in the figure for easy understanding. For components except the target unit  150   a,  the description of  FIG. 8 ,  FIG. 9 , and  FIG. 10  can be referred to as appropriate. In the sputtering apparatus shown in  FIG. 11 , deposition is performed by performing scanning with the target unit  150   a.  This allows deposition on an entire surface of the substrate even in the case where the size of the target is smaller than that of the substrate. Since the target is small, the size of the sputtering apparatus can be small. Accordingly, cost of manufacturing the sputtering apparatus can be reduced. Moreover, deposition by performing scanning with the target unit  150   a  can achieve a film uniform in thickness and quality even on a large substrate. Note that the scanning speed of the target unit  150   a  may be changed depending on the thickness of a film to be formed. The operation in which deposition is performed by scanning with the target unit  150   a  from a first end of the substrate  160  to a second end of the substrate  160  that faces the first end may be repeated. Alternatively, scanning for deposition is performed with the target unit  150   a  moved from the first end of the substrate  160  to the second end thereof and then returned to the first end of the substrate  160 . 
       FIG. 12A  shows a state of depositing a film  106   a  when scanning is performed with the target in the sputtering apparatus shown in  FIG. 11 .  FIG. 12B  shows a state of depositing the film  106   a,  a film  106   b,  and a film  106   c  when scanning is performed with the target unit  150   a,  a target unit  150   b,  and a target unit  150   c  moved in line. Note that for the target unit  150   b  and the target unit  150   c,  the description of the target unit  150   a  is referred to. Note that the targets may differ in composition, for example. The structures shown in  FIGS. 12A and 12B  are merely examples, and the number of pairs of target units is not limited to one or three. For example, the number of target units may be two, or four or more. 
     By performing scanning with a plurality of target units at the same time, stacked films can be formed at a time. As a result, stacked films can be deposited in a short time. Moreover, the time interval between deposition of a film and deposition of another film can be shortened, so that entry of an impurity at the interface between the films can be suppressed. In addition, in an active state immediately after deposition of a film, another film is deposited, whereby adhesion between the films can be increased. For example, stacked films that have conventionally been considered poor in adhesion therebetween can be formed in high yield. 
     In the case where a plurality of films is deposited by one-time scanning, film kinds of the films may differ partly or wholly, or film kinds of all of the films may be the same. The thicknesses of the films may differ partly or wholly, or the thicknesses of all of the films may be the same. The scanning speeds (moving speeds) of the target units may differ partly or wholly, or the scanning speeds (moving speeds) of all of the targets may be the same. Film formation conditions of the films may differ partly or wholly, or film formation conditions of all of the films may be the same. 
     Alternatively, the arrangement of a plurality of target units may be varied. For example, as shown in  FIG. 13 , the perpendicular distance between the target unit  150   a  and the substrate  160  may be different from the perpendicular distance between the target unit  150   b  and the substrate  160 . The thickness and quality of a film to be formed can be controlled by changing the perpendicular distance between the target unit and the substrate. 
     A member for preventing sputtering particles from being widely scattered may be placed between the target unit and the substrate. For example, a member having a slit may be placed so that a slit is located between the target unit and the substrate. Specifically, as shown in  FIG. 14 , a member  134   a  having a slit may be provided so as to surround the target unit  150   a,  and a member  134   b  having a slit may be provided so as to surround the target unit  150   b.  Since the member having a slit can prevent sputtering particles from being widely scattered, the formation of a film where the film  106   a  and the film  106   b  are mixed on the substrate  160  can be suppressed. The member having a slit may be referred to as a chimney. 
     The sputtering apparatus of one embodiment of the present invention may have a structure in which scanning is performed with the target unit  150   a  moved over the substrate  160  as shown in  FIG. 15A . Alternatively, a structure in which the substrate  160  is stood and scanning is performed with the target unit  150   a  along the substrate  160  as shown in  FIG. 15B  may be used. In the case where the substrate is stood, the installation area of the sputtering apparatus can be reduced as compared to the case where the substrate is laid down. 
     The sputtering apparatus of one embodiment of the present invention enables formation of a film with uniform thickness and quality on a large substrate, though the sputtering apparatus is a facing-targets sputtering apparatus. Moreover, time required for formation of stacked films can be reduced because a plurality of films can be formed successively by one-time scanning. 
     &lt;Deposition Apparatus&gt; 
     A deposition apparatus including a sputtering apparatus of one embodiment of the present invention will be described below. 
     First, a structure of a deposition apparatus which allows the entry of few impurities into a film at the time of the deposition or the like is described with reference to  FIG. 16  and  FIGS. 17A to 17C . 
       FIG. 16  is a top view schematically illustrating a single wafer multi-chamber deposition apparatus  2700 . The deposition apparatus  2700  includes an atmosphere-side substrate supply chamber  2701  including a cassette port  2761  for holding a substrate and an alignment port  2762  for performing alignment of a substrate, an atmosphere-side substrate transfer chamber  2702  through which a substrate is transferred from the atmosphere-side substrate supply chamber  2701 , a load lock chamber  2703   a  where a substrate is carried and the pressure inside the chamber is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber  2703   b  where a substrate is carried out and the pressure inside the chamber is switched from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber  2704  through which a substrate is transferred in a vacuum, a substrate heating chamber  2705  where a substrate is heated, and deposition chambers  2706   a,    2706   b,  and  2706   c  in each of which a target is placed for deposition. Note that the deposition chambers  2706   a,    2706   b,  and  2706   c  each have a structure similar to the structure of any of the above-described deposition chambers. 
     The atmosphere-side substrate transfer chamber  2702  is connected to the load lock chamber  2703   a  and the unload lock chamber  2703   b,  the load lock chamber  2703   a  and the unload lock chamber  2703   b  are connected to the transfer chamber  2704 , and the transfer chamber  2704  is connected to the substrate heating chamber  2705  and the deposition chambers  2706   a,    2706   b,  and  2706   c.    
     Gate valves  2764  are provided for connecting portions between chambers so that each chamber except the atmosphere-side substrate supply chamber  2701  and the atmosphere-side substrate transfer chamber  2702  can be independently kept under vacuum. Moreover, the atmosphere-side substrate transfer chamber  2702  and the transfer chamber  2704  each include a transfer robot  2763 , with which a substrate can be transferred. 
     Furthermore, it is preferable that the substrate heating chamber  2705  also serve as a plasma treatment chamber. In the deposition apparatus  2700 , it is possible to transfer a substrate without exposure to the air between treatment and treatment; therefore, adsorption of impurities on a substrate can be suppressed. In addition, the order of deposition, heat treatment, or the like can be freely determined. Note that the number of the transfer chambers, the number of the deposition chambers, the number of the load lock chambers, the number of the unload lock chambers, and the number of the substrate heating chambers are not limited to the above, and the numbers thereof can be set as appropriate depending on the space for placement or the process conditions. 
     Next,  FIG. 17A ,  FIG. 17B , and  FIG. 17C  are a cross-sectional view taken along dashed-dotted line X 1 -X 2 , a cross-sectional view taken along dashed-dotted line Y 1 -Y 2 , and a cross-sectional view taken along dashed-dotted line Y 2 -Y 3 , respectively, in the deposition apparatus  2700  illustrated in  FIG. 16 . 
       FIG. 17A  is a cross section of the substrate heating chamber  2705  and the transfer chamber  2704 , and the substrate heating chamber  2705  includes a plurality of heating stages  2765  which can hold a substrate. Furthermore, the substrate heating chamber  2705  is connected to a vacuum pump  2770  through a valve. As the vacuum pump  2770 , a dry pump and a mechanical booster pump can be used, for example. 
     As heating mechanism which can be used for the substrate heating chamber  2705 , a resistance heater may be used for heating, for example. Alternatively, heat conduction or heat radiation from a medium such as a heated gas may be used as the heating mechanism. For example, rapid thermal annealing (RTA) such as gas rapid thermal annealing (GRTA) or lamp rapid thermal annealing (LRTA) can be used. The LRTA is a method for heating an object by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. In the GRTA, heat treatment is performed using a high-temperature gas. An inert gas is used as the gas. 
     Moreover, the substrate heating chamber  2705  is connected to a refiner  2781  through a mass flow controller  2780 . Note that although the mass flow controller  2780  and the refiner  2781  can be provided for each of a plurality of kinds of gases, only one mass flow controller  2780  and one refiner  2781  are provided for easy understanding. As the gas introduced to the substrate heating chamber  2705 , a gas whose dew point is −80° C. or lower, preferably −100° C. or lower can be used; for example, an oxygen gas, a nitrogen gas, and a rare gas (e.g., an argon gas) are used. 
     The transfer chamber  2704  includes the transfer robot  2763 . The transfer robot  2763  can transfer a substrate to each chamber. Furthermore, the transfer chamber  2704  is connected to the vacuum pump  2770  through a valve and connected to a cryopump  2771  through another valve. Owing to such a structure, exhaust is performed using the vacuum pump  2770  until the pressure inside the transfer chamber  2704  becomes in the range of atmospheric pressure to low or medium vacuum (approximately 0.1 Pa to several hundred pascals) and then the valves are switched so that exhaust is performed using the cryopump  2771  until the pressure inside the transfer chamber  2704  becomes in the range of middle vacuum to high or ultra-high vacuum (0.1 Pa to 1×10 −7  Pa). 
     Alternatively, two or more cryopumps  2771  may be connected in parallel to the transfer chamber  2704 . With such a structure, even when one of the cryopumps is in regeneration, exhaust can be performed using any of the other cryopumps. Note that the above regeneration refers to treatment for discharging molecules (or atoms) entrapped in the cryopump. When molecules (or atoms) are entrapped too much in a cryopump, the exhaust capability of the cryopump is lowered; therefore, regeneration is performed regularly. 
       FIG. 17B  is a cross section of the deposition chamber  2706   b,  the transfer chamber  2704 , and the load lock chamber  2703   a.    
     Here, the details of the deposition chamber (a deposition chamber including a sputtering apparatus) are described with reference to  FIG. 17B . The deposition chamber  2706   b  illustrated in  FIG. 17B  includes a target unit  2766 , a substrate holder  2768 , and power sources  2791 . The power sources  2791  are electrically connected to the target unit  2766 . For the target unit  2766 , the description of the target unit  150   a  or the like is referred to. Note that here, a substrate  2769  is supported by the substrate holder  2768 . The substrate holder  2768  is fixed to the deposition chamber  2706   b  by an adjustment member  2784 . The adjustment member  2784  can change the distance between the target unit  2766  and the substrate holder  2768 . Although not illustrated, the substrate holder  2768  may include a substrate holding mechanism which holds the substrate  2769 , a rear heater which heats the substrate  2769  from the back surface, or the like. 
     The deposition chamber  2706   b  is connected to the mass flow controller  2780  through a gas heating system  2782 , and the gas heating system  2782  is connected to the refiner  2781  through the mass flow controller  2780 . With the gas heating system  2782 , a gas which is introduced to the deposition chamber  2706   b  can be heated to a temperature higher than or equal to 40° C. and lower than or equal to 400° C. Note that although the gas heating system  2782 , the mass flow controller  2780 , and the refiner  2781  can be provided for each of a plurality of kinds of gases, only one gas heating system  2782 , one mass flow controller  2780 , and one refiner  2781  are provided for easy understanding. As the gas introduced to the deposition chamber  2706   b,  a gas whose dew point is −80° C. or lower, preferably −100° C. or lower can be used; for example, an oxygen gas, a nitrogen gas, and a rare gas (e.g., an argon gas) are used. 
     In the case where the refiner is provided near a gas inlet, the length of a pipe between the refiner and the deposition chamber  2706   b  is less than or equal to 10 m, preferably less than or equal to 5 m, and further preferably less than or equal to 1 m. When the length of the pipe is less than or equal to 10 m, less than or equal to 5 m, or less than or equal to 1 m, the effect of the release of gas from the pipe can be reduced accordingly. As the pipe for the gas, a metal pipe the inside of which is covered with iron fluoride, aluminum oxide, chromium oxide, or the like can be used. With the above pipe, the amount of released gas containing impurities is made small and the entry of impurities into the gas can be reduced as compared with a SUS316L-EP pipe, for example. Furthermore, a high-performance ultra-compact metal gasket joint (UPG joint) may be used as a joint of the pipe. A structure where all the materials of the pipe are metals is preferable because the effect of the generated released gas or the external leakage can be reduced as compared with a structure where a resin or the like is used. 
     The deposition chamber  2706   b  is connected to a turbo molecular pump  2772  and the vacuum pump  2770  through a plurality of valves as shown in  FIG. 17B . 
     In addition, the deposition chamber  2706   b  is provided with a cryotrap  2751 . 
     The cryotrap  2751  is a mechanism which can adsorb a molecule (or an atom) having a relatively high melting point, such as water. The turbo molecular pump  2772  is capable of stably removing a large-sized molecule (or atom), needs low frequency of maintenance, and thus enables high productivity, whereas it has a low capability in removing hydrogen and water. Hence, the cryotrap  2751  is provided in the deposition chamber  2706   b  so as to have a high capability in removing water or the like. The temperature of a refrigerator of the cryotrap  2751  is set to be lower than or equal to 100 K, preferably lower than or equal to 80 K. In the case where the cryotrap  2751  includes a plurality of refrigerators, it is preferable to set the temperatures of the refrigerators at different temperatures because efficient exhaust is possible. For example, the temperature of a first-stage refrigerator may be set to be lower than or equal to 100 K and the temperature of a second-stage refrigerator may be set to be lower than or equal to 20 K. Note that when a titanium sublimation pump is used instead of the cryotrap, a higher vacuum can be achieved in some cases. Using an ion pump instead of a cryopump or a turbo molecular pump can also achieve higher vacuum in some cases. 
     Note that the exhaust method of the deposition chamber  2706   b  is not limited to the above, and a structure similar to that in the exhaust method described above for the transfer chamber  2704  (the exhaust method using the cryopump and the vacuum pump) may be employed. Needless to say, the exhaust method of the transfer chamber  2704  may have a structure similar to that of the deposition chamber  2706   b  (the exhaust method using the turbo molecular pump and the vacuum pump). 
     Note that in each of the transfer chamber  2704 , the substrate heating chamber  2705 , and the deposition chamber  2706   b  which are described above, the back pressure (total pressure) and the partial pressure of each gas molecule (atom) are preferably set as follows. In particular, the back pressure and the partial pressure of each gas molecule (atom) in the deposition chamber  2706   b  need to be noted because impurities might enter a film to be formed. 
     In each of the above chambers, the back pressure (total pressure) is less than or equal to 1×10 −4  Pa, preferably less than or equal to 3×10 −5  Pa, and further preferably less than or equal to 1×10 −5  Pa. In each of the above chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is less than or equal to 3×10 −5  Pa, preferably less than or equal to 1×10 −5  Pa, and further preferably less than or equal to 3×10 −6  Pa. Moreover, in each of the above chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28 is less than or equal to 3×10 −5  Pa, preferably less than or equal to 1×10 −5  Pa, and further preferably less than or equal to 3×10 −6  Pa. Furthermore, in each of the above chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44 is less than or equal to 3×10 −5  Pa, preferably less than or equal to 1×10 −5  Pa, and further preferably less than or equal to 3×10 −6  Pa. 
     Note that a total pressure and a partial pressure in a vacuum chamber can be measured using a mass analyzer. For example, Qulee CGM-051, a quadrupole mass analyzer (also referred to as Q-mass) manufactured by ULVAC, Inc. may be used. 
     Moreover, the transfer chamber  2704 , the substrate heating chamber  2705 , and the deposition chamber  2706   b  which are described above preferably have a small amount of external leakage or internal leakage. 
     For example, in each of the transfer chamber  2704 , the substrate heating chamber  2705 , and the deposition chamber  2706   b  which are described above, the leakage rate is less than or equal to 3×10 −6  Pa·m 3 /s, and preferably less than or equal to 1×10 −6  Pa·m 3 /s. The leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is less than or equal to 1×10 −7  Pa·m 3 /s, and preferably less than or equal to 3×10 −8  Pa·m 3 /s. The leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28 is less than or equal to 1×10 −5  Pa·m 3 /s, and preferably less than or equal to 1×10 −6  Pa·m 3 /s. The leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44 is less than or equal to 3×10 −6  Pa·m 3 /s, and preferably less than or equal to 1×10 −6  Pa·m 3 /s. 
     Note that a leakage rate can be derived from the total pressure and partial pressure measured using the mass analyzer. 
     The leakage rate depends on external leakage and internal leakage. The external leakage refers to inflow of gas from the outside of a vacuum system through a minute hole, a sealing defect, or the like. The internal leakage is due to leakage through a partition, such as a valve, in a vacuum system or due to released gas from an internal member. Measures need to be taken from both aspects of external leakage and internal leakage in order that the leakage rate can be set to be less than or equal to the above value. 
     For example, an open/close portion of the deposition chamber  2706   b  can be sealed with a metal gasket. For the metal gasket, metal covered with iron fluoride, aluminum oxide, or chromium oxide is preferably used. The metal gasket realizes higher adhesion than an O-ring, and can reduce the external leakage. Furthermore, with the use of the metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, which is in the passive state, the release of gas containing impurities released from the metal gasket is suppressed, so that the internal leakage can be reduced. 
     For a member of the deposition apparatus  2700 , aluminum, chromium, titanium, zirconium, nickel, or vanadium, which releases a smaller amount of gas containing impurities, is used. Alternatively, for the above member, an alloy containing iron, chromium, nickel, and the like covered with the above material may be used. The alloy containing iron, chromium, nickel, and the like is rigid, resistant to heat, and suitable for processing. Here, when surface unevenness of the member is decreased by polishing or the like to reduce the surface area, the release of gas can be reduced. 
     Alternatively, the above member of the deposition apparatus  2700  may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like. 
     The member of the deposition apparatus  2700  is preferably formed using only metal when possible. For example, in the case where a viewing window formed with quartz or the like is provided, it is preferable that the surface of the viewing window be thinly covered with iron fluoride, aluminum oxide, chromium oxide, or the like so as to suppress release of gas. 
     When an adsorbed substance is present in the deposition chamber, the adsorbed substance does not affect the pressure in the deposition chamber because it is adsorbed onto an inner wall or the like; however, the adsorbed substance causes gas to be released when the inside of the deposition chamber is evacuated. Therefore, although there is no correlation between the leakage rate and the exhaust rate, it is important that the adsorbed substance present in the deposition chamber be desorbed as much as possible and exhaust be performed in advance with the use of a pump with high exhaust capability. Note that the deposition chamber may be subjected to baking to promote desorption of the adsorbed substance. By the baking, the desorption rate of the adsorbed substance can be increased about tenfold. The baking can be performed at a temperature in the range of 100° C. to 450° C. At this time, when the adsorbed substance is removed while an inert gas is introduced to the deposition chamber, the desorption rate of water or the like, which is difficult to be desorbed simply by exhaust, can be further increased. Note that when the inert gas which is introduced is heated to substantially the same temperature as the baking temperature, the desorption rate of the adsorbed substance can be further increased. Here, a rare gas is preferably used as an inert gas. Depending on the kind of a film to be deposited, oxygen or the like may be used instead of an inert gas. For example, in deposition of an oxide, the use of oxygen which is the main component of the oxide is preferable in some cases. The baking is preferably performed using a lamp. 
     Alternatively, treatment for evacuating the inside of the deposition chamber is preferably performed a certain period of time after heated oxygen, a heated inert gas such as a heated rare gas, or the like is introduced to increase a pressure in the deposition chamber. The introduction of the heated gas can desorb the adsorbed substance in the deposition chamber, and the impurities present in the deposition chamber can be reduced. Note that an advantageous effect can be achieved when this treatment is repeated more than or equal to 2 times and less than or equal to 30 times, preferably more than or equal to 5 times and less than or equal to 15 times. Specifically, an inert gas, oxygen, or the like with a temperature higher than or equal to 40° C. and lower than or equal to 400° C., preferably higher than or equal to 50° C. and lower than or equal to 200° C. is introduced to the deposition chamber, so that the pressure therein can be kept to be greater than or equal to 0.1 Pa and less than or equal to 10 kPa, preferably greater than or equal to 1 Pa and less than or equal to 1 kPa, further preferably greater than or equal to 5 Pa and less than or equal to 100 Pa in the time range of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the inside of the deposition chamber is evacuated in the time range of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes. 
     The desorption rate of the adsorbed substance can be further increased also by dummy deposition. Here, the dummy deposition refers to deposition on a dummy substrate by a sputtering method or the like, in which a film is deposited on the dummy substrate and the inner wall of the deposition chamber so that impurities in the deposition chamber and an adsorbed substance on the inner wall of the deposition chamber are confined in the film. For a dummy substrate, a substrate which releases a smaller amount of gas is preferably used. By performing dummy deposition, the concentration of impurities in a film to be formed later can be reduced. Note that the dummy deposition may be performed at the same time as the baking of the deposition chamber. 
     Next, the details of the transfer chamber  2704  and the load lock chamber  2703   a  illustrated in  FIG. 17B  and the atmosphere-side substrate transfer chamber  2702  and the atmosphere-side substrate supply chamber  2701  illustrated in  FIG. 17C  are described. Note that  FIG. 17C  is a cross section of the atmosphere-side substrate transfer chamber  2702  and the atmosphere-side substrate supply chamber  2701 . 
     For the transfer chamber  2704  illustrated in  FIG. 17B , the description of the transfer chamber  2704  illustrated in  FIG. 17A  can be referred to. 
     The load lock chamber  2703   a  includes a substrate delivery stage  2752 . When a pressure in the load lock chamber  2703   a  becomes atmospheric pressure by being increased from reduced pressure, the substrate delivery stage  2752  receives a substrate from the transfer robot  2763  provided in the atmosphere-side substrate transfer chamber  2702 . After that, the load lock chamber  2703   a  is evacuated into vacuum so that the pressure therein becomes reduced pressure and then the transfer robot  2763  provided in the transfer chamber  2704  receives the substrate from the substrate delivery stage  2752 . 
     Furthermore, the load lock chamber  2703   a  is connected to the vacuum pump  2770  and the cryopump  2771  through valves. For a method for connecting exhaust systems such as the vacuum pump  2770  and the cryopump  2771 , the description of the method for connecting the transfer chamber  2704  can be referred to, and the description thereof is omitted here. Note that the unload lock chamber  2703   b  illustrated in  FIG. 16  can have a structure similar to that in the load lock chamber  2703   a.    
     The atmosphere-side substrate transfer chamber  2702  includes the transfer robot  2763 . The transfer robot  2763  can deliver a substrate from the cassette port  2761  to the load lock chamber  2703   a  or deliver a substrate from the load lock chamber  2703   a  to the cassette port  2761 . Furthermore, a mechanism for suppressing entry of dust or a particle, such as high efficiency particulate air (HEPA) filter, may be provided above the atmosphere-side substrate transfer chamber  2702  and the atmosphere-side substrate supply chamber  2701 . 
     The atmosphere-side substrate supply chamber  2701  includes a plurality of cassette ports  2761 . The cassette port  2761  can hold a plurality of substrates. 
     The surface temperature of the target is set to be lower than or equal to 100° C., preferably lower than or equal to 50° C., and further preferably about room temperature (typified by 25° C.). In a sputtering apparatus for a large substrate, a large target is often used. However, it is difficult to form a target for a large substrate without a juncture. In reality, a plurality of targets are tightly arranged to obtain a large target; however, a slight space inevitably exists. When the surface temperature of the target increases, in some cases, zinc or the like is volatilized from such a slight space and the space might gradually expand. When the space expands, a metal of a backing plate or a metal contained in a bonding agent used for adhesion of the backing plate to a target might be sputtered and might cause an increase in impurity concentration. Thus, it is preferable that the target be cooled sufficiently. 
     To efficiently cool the target, a metal having high conductivity and a high heat dissipation property (specifically copper) is used for the backing plate, or a sufficient amount of cooling water is made to flow through a water channel formed in the backing plate. 
     Note that in the case where the target contains zinc, plasma damage is alleviated by deposition in an oxygen gas atmosphere; thus, an oxide semiconductor in which zinc is unlikely to be volatilized can be obtained. 
     The above-described deposition apparatus enables deposition of an oxide semiconductor whose hydrogen concentration measured by secondary ion mass spectrometry (SIMS) is lower than or equal to 2×10 20  atoms/cm 3 , preferably lower than or equal to 5×10 19  atoms/cm 3 , further preferably lower than or equal to 1×10 19  atoms/cm 3 , and still further preferably lower than or equal to 5×10 18  atoms/cm 3 . 
     Furthermore, an oxide semiconductor whose nitrogen concentration measured by SIMS is lower than 5×10 19  atoms/cm 3 , preferably lower than or equal to 1×10 19  atoms/cm 3 , further preferably lower than or equal to 5×10 18  atoms/cm 3 , and still further preferably lower than or equal to 1×10 18  atoms/cm 3  can be deposited. 
     Moreover, an oxide semiconductor whose carbon concentration measured by SIMS is lower than 5×10 19  atoms/cm 3 , preferably lower than or equal to 5×10 18  atoms/cm 3 , further preferably lower than or equal to 1×10 18  atoms/cm 3 , and still further preferably lower than or equal to 5×10 17  atoms/cm 3  can be deposited. 
     The oxide semiconductor having small amounts of impurities and oxygen vacancies has low carrier density (specifically, lower than 8×10 11 /cm 3 , preferably lower than 1×10 11 /cm 3 , further preferably lower than 1×10 10 /cm 3 , and is higher than or equal to 1×10 −9 /cm 3 ). Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. In particular, a CAAC-OS that has a low impurity concentration and a low density of defect states can be referred to as a substantially highly purified intrinsic oxide semiconductor having stable characteristics. 
     Furthermore, an oxide semiconductor can be deposited in which the released amount of each of the following gas molecules (atoms) measured by thermal desorption spectroscopy (TDS) is less than or equal to 1×10 19 /cm 3  and preferably less than or equal to 1×10 18 /cm 3 : a gas molecule (atom) having a mass-to-charge ratio (m/z) of 2 (e.g., a hydrogen molecule), a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18, a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28, and a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44. 
     With the above deposition apparatus, entry of impurities into the oxide semiconductor can be suppressed. Furthermore, when a film in contact with the oxide semiconductor is formed with the use of the above deposition apparatus, the entry of impurities into the oxide semiconductor from the film in contact therewith can be suppressed. 
     &lt;Structure of Oxide Semiconductor&gt; 
     The structure of an oxide semiconductor is described below. 
     An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. 
     From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS. 
     It is known that an amorphous structure is generally defined as being metastable and unfixed, and being isotropic and having no non-uniform structure. In other words, an amorphous structure has a flexible bond angle and a short-range order but does not have a long-range order. 
     This means that an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. Note that an a-like OS has a periodic structure in a microscopic region, but at the same time has a void and has an unstable structure. For this reason, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor. 
     &lt;CAAC-OS&gt; 
     First, a CAAC-OS will be described. 
     The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets). 
     In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur. 
     A CAAC-OS observed with TEM will be described below.  FIG. 47A  shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. 
       FIG. 47B  is an enlarged Cs-corrected high-resolution TEM image of a region ( 1 ) in  FIG. 47A .  FIG. 47B  shows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration reflecting unevenness of a surface over which a CAAC-OS film is formed (hereinafter, the surface is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged parallel to the formation surface or the top surface of the CAAC-OS film. 
     As shown in  FIG. 47B , the CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is denoted by an auxiliary line in  FIG. 47C .  FIGS. 47B and 47C  prove that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). 
     Here, according to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets  5100  of a CAAC-OS over a substrate  5120  is illustrated by such a structure in which bricks or blocks are stacked (see  FIG. 47D ). The part in which the pellets are tilted as observed in  FIG. 47C  corresponds to a region  5161  shown in  FIG. 47D . 
       FIG. 48A  shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.  FIGS. 48B, 48C , and  48 D are enlarged Cs-corrected high-resolution TEM images of regions ( 1 ), ( 2 ), and ( 3 ) in  FIG. 48A , respectively.  FIGS. 48B, 48C, and 48D  indicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets. 
     Next, a CAAC-OS analyzed by X-ray diffraction (XRD) will be described. For example, when the structure of a CAAC-OS including an InGaZnO 4  crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in  FIG. 49A . This peak is derived from the (009) plane of the InGaZnO 4  crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. 
     Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when 2θ is around 36°, in addition to the peak at 28 of around 31°. The peak at 2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. It is preferable that in the CAAC-OS analyzed by an out-of-plane method, a peak appear when 2θ is around 31° and that a peak not appear when 2θ is around 36°. 
     On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray beam is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when 2θ is around 56°. This peak is attributed to the (110) plane of the InGaZnO 4  crystal. In the case of the CAAC-OS, when analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector of the sample surface as an axis (φ axis), as shown in  FIG. 49B , a peak is not clearly observed. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO 4 , when φ scan is performed with 2θ fixed at around 56°, as shown in  FIG. 49C , six peaks which are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS. 
     Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO 4  crystal in a direction parallel to the sample surface, a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shown in  FIG. 50A  can be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO 4  crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile,  FIG. 50B  shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in  FIG. 50B , a ring-like diffraction pattern is observed. Thus, the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring in  FIG. 50B  is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO 4  crystal. The second ring in  FIG. 50B  is considered to be derived from the (110) plane and the like. 
     As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies). 
     Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity. 
     The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. For example, impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources. Furthermore, oxygen vacancies in the oxide semiconductor serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein. 
     The CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with a low carrier density. Specifically, an oxide semiconductor with a carrier density of lower than 8×10 11 /cm 3 , preferably lower than 1×10 11 /cm 3 , further preferably lower than 1×10 10 /cm 3 , and higher than or equal to 1×10 −9 /cm 3  can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics. 
     &lt;nc-OS&gt; 
     Next, an nc-OS will be described. 
     An nc-OS has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary cannot be clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description. 
     In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. For example, when the nc-OS is analyzed by an out-of-plane method using an X-ray beam having a diameter larger than the size of a pellet, a peak indicating a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet. Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots is shown in a ring-like region in some cases. 
     Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC). 
     The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS. 
     &lt;a-like OS&gt; 
     An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor. 
     In a high-resolution TEM image of the a-like OS, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed. 
     The a-like OS has an unstable structure because it includes a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below. 
     An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In—Ga—Zn oxide. 
     First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts. 
     Note that which part is regarded as a crystal part is determined as follows. It is known that a unit cell of an InGaZnO 4  crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO 4 . Each of lattice fringes corresponds to the a-b plane of the InGaZnO 4  crystal. 
       FIG. 51  shows change in the average size of crystal parts (at 22 points to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe.  FIG. 51  indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by ( 1 ) in  FIG. 51 , a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2×10 8  e − /nm 2 . In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×10 8  e − /nm 2 . Specifically, as shown by ( 2 ) and ( 3 ) in  FIG. 51 , the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose. 
     In this manner, growth of the crystal part in the a-like OS might be induced by electron irradiation, for example. In contrast, in the nc-OS and the CAAC-OS, it is shown that growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS. 
     The a-like OS has a lower density than the nc-OS and the CAAC-OS because it includes a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor. 
     For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO 4  with a rhombohedral crystal structure is 6.357 g/cm 3 . Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm 3  and lower than 5.9 g/cm 3 . For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm 3  and lower than 6.3 g/cm 3 . 
     Note that there is a possibility that an oxide semiconductor having a certain composition cannot exist in a single crystal structure. In that case, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density. 
     As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more films of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example. 
     &lt;Transistor  1 &gt; 
       FIGS. 18A to 18C  are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention.  FIG. 18A  is a top view, and  FIGS. 18B and 18C  are cross-sectional views taken along dashed-dotted lines A 1 -A 2  and A 3 -A 4  in  FIG. 18A , respectively. Note that for simplification of the drawing, some components are not illustrated in the top view in  FIG. 18A . 
     The transistor illustrated in  FIGS. 18A to 18C  includes a conductor  413  over a substrate  400 , an insulator  402  over the substrate  400  and the conductor  413 , an insulator  406   a  over the insulator  402 , a semiconductor  406   b  over the insulator  406   a,  a conductor  416   a  and a conductor  416   b  which are arranged to be separated from each other while being in contact with top and side surfaces of the semiconductor  406   b,  an insulator  410  over the conductor  416   a  and the conductor  416   b,  an insulator  406   c  over the semiconductor  406   b  and the insulator  410 , an insulator  412  over the insulator  406   c,  a conductor  404  over the insulator  412 , and an insulator  408  over the conductor  404 . Although the conductor  413  is part of the transistor in this non-limiting example, the conductor  413  may be a component independent of the transistor, for example. Furthermore, the transistor does not necessarily include one or more of the insulator  408  and the insulator  410 . 
     In the cross-sectional views shown in  FIGS. 18B and 18C , a top surface of the insulator  410  is parallel to a rear surface of the substrate  400 ; however, it is not necessary that they are parallel to each other. For example, the top surface of the insulator  410  may have a shape along unevenness of the conductor  416   a  and the conductor  416   b.    
     The conductor  404  includes a region that faces the top surface and the side surface of the semiconductor  406   b  with the insulator  412  provided therebetween in the cross section taken along line A 3 -A 4 . The conductor  413  includes a region which faces the bottom surface of the semiconductor  406   b  with the insulator  402  provided therebetween. 
     The semiconductor  406   b  serves as a channel formation region of the transistor. The conductor  404  serves as a first gate electrode (also referred to as a front gate electrode) of the transistor. The conductor  413  serves as a second gate electrode (also referred to as a back gate electrode) of the transistor. The conductor  416   a  and the conductor  416   b  serve as a source electrode and a drain electrode of the transistor. 
     As illustrated in  FIG. 18C , the semiconductor  406   b  can be electrically surrounded by an electric field of the conductor  404  and/or the conductor  413  (a structure in which a semiconductor is electrically surrounded by an electric field of a conductor is referred to as a surrounded channel (s-channel) structure). Therefore, a channel is formed in the entire semiconductor  406   b  (the top, bottom, and side surfaces). In the s-channel structure, a large amount of current can flow between a source and a drain of the transistor, so that a high on-state current can be achieved. 
     In the case where the transistor has the s-channel structure, a channel is formed also in the side surface of the semiconductor  406   b.  Therefore, as the semiconductor  406   b  has a larger thickness, the channel formation region becomes larger. In other words, the thicker the semiconductor  406   b  is, the larger the on-state current of the transistor is. In addition, when the semiconductor  406   b  is thicker, the proportion of the region with a high carrier controllability increases, leading to a smaller subthreshold swing value. For example, the semiconductor  406   b  has a region with a thickness of greater than or equal to 10 nm, preferably greater than or equal to 20 nm, further preferably greater than or equal to 40 nm, still further preferably greater than or equal to 60 nm, and yet still further preferably greater than or equal to 100 nm. In addition, to prevent a decrease in the productivity of the semiconductor device, the semiconductor  406   b  has a region with a thickness of, for example, less than or equal to 300 nm, preferably less than or equal to 200 nm, and further preferably less than or equal to 150 nm. 
     The s-channel structure is suitable for a miniaturized transistor because a high on-state current can be achieved. A semiconductor device including the miniaturized transistor can have a high integration degree and high density. For example, the transistor includes a region having a channel length of preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, and still further preferably less than or equal to 20 nm and a region having a channel width of preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, and still further preferably less than or equal to 20 nm. 
     As the substrate  400 , an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), or a resin substrate is used, for example. As the semiconductor substrate, a single material semiconductor substrate of silicon, germanium, or the like or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like is used, for example. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate or the like is used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is used. A substrate including a metal nitride, a substrate including a metal oxide, or the like is used. An insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like is used. Alternatively, any of these substrates over which an element is provided may be used. As the element provided over the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like is used. 
     Alternatively, a flexible substrate may be used as the substrate  400 . As a method for providing a device over a flexible substrate, there is a method in which the device is formed over a non-flexible substrate and then the device is separated and transferred to the substrate  400  which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the device. As the substrate  400 , a sheet, a film, or a foil containing a fiber may be used. The substrate  400  may have elasticity. The substrate  400  may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate  400  may have a property of not returning to its original shape. The thickness of the substrate  400  is, for example, greater than or equal to 5 μm and less than or equal to 700 μm, preferably greater than or equal to 10 μm and less than or equal to 500 μm, and further preferably greater than or equal to 15 μm and less than or equal to 300 μm. When the substrate  400  has a small thickness, the weight of the semiconductor device can be reduced. When the substrate  400  has a small thickness, even in the case of using glass or the like, the substrate  400  may have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate  400 , which is caused by dropping or the like, can be reduced. That is, a durable semiconductor device can be provided. 
     For the substrate  400  which is a flexible substrate, metal, an alloy, resin, glass, or fiber thereof can be used, for example. The flexible substrate  400  preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate  400  is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10 −3 /K, lower than or equal to 5×10 −5 /K, or lower than or equal to 1×10 −5 /K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate  400  because of its low coefficient of linear expansion. 
     The conductor  413  may be formed to have a single-layer structure or a stacked-layer structure using a conductor containing, for example, one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. 
     The insulator  402  may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  402  may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     The insulator  402  preferably contains excess oxygen in the case where the semiconductor  406   b  is an oxide semiconductor. Note that excess oxygen means oxygen in an insulator or the like which does not bond with (which is liberated from) the insulator or the like or has low bonding energy with the insulator or the like. 
     Here, an insulator including excess oxygen may release oxygen, the amount of which is higher than or equal to 1×10 18  atoms/cm 3 , higher than or equal to 1×10 19  atoms/cm 3 , or higher than or equal to 1×10 20  atoms/cm 3  (converted into the number of oxygen atoms) in thermal desorption spectroscopy (TDS) analysis in the range of a surface temperature of 100° C. to 700° C. or 100° C. to 500° C. 
     The method of measuring the amount of released oxygen using TDS analysis is described below. 
     The total amount of released gas from a measurement sample in TDS analysis is proportional to the integral value of the ion intensity of the released gas. Then, comparison with a reference sample is made, whereby the total amount of released gas can be calculated. 
     For example, the number of released oxygen molecules (N O2 ) from a measurement sample can be calculated according to the following formula using the TDS results of a silicon substrate containing hydrogen at a predetermined density, which is a reference sample, and the TDS results of the measurement sample. Here, all gases having a mass-to-charge ratio of 32 which are obtained in the TDS analysis are assumed to originate from an oxygen molecule. Note that CH 3 OH, which is a gas having the mass-to-charge ratio of 32, is not taken into consideration because it is unlikely to be present. Furthermore, an oxygen molecule including an oxygen atom having a mass number of 17 or 18 which is an isotope of an oxygen atom is also not taken into consideration because the proportion of such a molecule in the natural world is minimal. 
       N O2 ═N H2 /S H2 ×S O2 ×α
 
     The value N H2  is obtained by conversion of the number of hydrogen molecules desorbed from the reference sample into densities. The value S H2  is the integral value of ion intensity in the case where the reference sample is subjected to the TDS analysis. Here, the reference value of the reference sample is set to N H2 /S H2 . The value S O2  is the integral value of ion intensity when the measurement sample is analyzed by TDS. The value α is a coefficient affecting the ion intensity in the TDS analysis. Refer to Japanese Published Patent Application No. H6-275697 for details of the above formula. The amount of released oxygen was measured with a thermal desorption spectroscopy apparatus produced by ESCO Ltd., EMD-WA1000S/W using a silicon substrate containing a certain amount of hydrogen atoms as the reference sample. 
     Furthermore, in the TDS analysis, oxygen is partly detected as an oxygen atom. The ratio between oxygen molecules and oxygen atoms can be calculated from the ionization rate of the oxygen molecules. Note that, since the above α includes the ionization rate of the oxygen molecules, the number of the released oxygen atoms can also be estimated through the evaluation of the number of the released oxygen molecules. 
     Note that N O2  is the number of the released oxygen molecules. The number of released oxygen in the case of being converted into oxygen atoms is twice the number of the released oxygen molecules. 
     Furthermore, the insulator from which oxygen is released by heat treatment may contain a peroxide radical. Specifically, the spin density of a signal attributed to the peroxide radical is greater than or equal to 5×10 17  spins/cm 3 . Note that the insulator containing a peroxide radical may have an asymmetric signal with a g factor of approximately 2.01 in electron spin resonance (ESR). 
     The conductor  416   a  and the conductor  416   b  may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. 
     The insulator  410  may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  410  may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     Note that the insulator  410  preferably includes an insulator with low relative permittivity. For example, the insulator  410  preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, resin, or the like. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. 
     The insulator  412  may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  402  may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     The insulator  412  preferably contains excess oxygen in the case where the semiconductor  406   b  is an oxide semiconductor. 
     The conductor  404  may be formed to have a single-layer structure or a stacked-layer structure using a conductor containing, for example, one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. 
     The insulator  408  is, for example, an insulator having a low hydrogen-transmitting property (i.e., a hydrogen barrier property). 
     Because of its small atomic radius or the like, hydrogen is likely to be diffused in an insulator (i.e., the diffusion coefficient of hydrogen is large). For example, a low-density insulator has a high hydrogen-transmitting property. In other words, a high-density insulator has a low hydrogen-transmitting property. The density of a low-density insulator is not always low throughout the insulator; an insulator including a low-density part is also referred to as a low-density insulator. This is because the low-density part serves as a hydrogen path. Although a density that allows hydrogen to be transmitted is not limited, it is typically lower than 2.6 g/cm 3 . Examples of a low-density insulator include an inorganic insulator such as silicon oxide or silicon oxynitride and an organic insulator such as polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, or acrylic. Examples of a high-density insulator include magnesium oxide, aluminum oxide, germanium oxide, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Note that a low-density insulator and a high-density insulator are not limited to these insulators. For example, the insulators may contain one or more of boron, nitrogen, fluorine, neon, phosphorus, chlorine, and argon. 
     An insulator having crystal grain boundaries can have a high hydrogen-transmitting property. In other words, hydrogen is less likely transmitted through an insulator having no grain boundaries or few grain boundaries. For example, a non-polycrystalline insulator (e.g., an amorphous insulator) has a lower hydrogen-transmitting property than a polycrystalline insulator. 
     An insulator having a high hydrogen-bonding energy has a low hydrogen-transmitting property in some cases. For example, when an insulator which forms a hydrogen compound by bonding with hydrogen has bonding energy at which hydrogen is not released at temperatures in fabrication and operation of a device, the insulator can be in the category of an insulator having a low hydrogen-transmitting property. For example, an insulator which forms a hydrogen compound at higher than or equal to 200° C. and lower than or equal to 1000° C., higher than or equal to 300° C. and lower than or equal to 1000° C., or higher than or equal to 400° C. and lower than or equal to 1000° C. has a low hydrogen-transmitting property in some cases. An insulator which forms a hydrogen compound and which releases hydrogen at higher than or equal to 200° C. and lower than or equal to 1000° C., higher than or equal to 300° C. and lower than or equal to 1000° C., or higher than or equal to 400° C. and lower than or equal to 1000° C. has a low hydrogen-transmitting property in some cases. An insulator which forms a hydrogen compound and which releases hydrogen at higher than or equal to 20° C. and lower than or equal to 400° C., higher than or equal to 20° C. and lower than or equal to 300° C., or higher than or equal to 20° C. and lower than or equal to 200° C. has a high hydrogen-transmitting property in some cases. Hydrogen which is released easily and liberated can be referred to as excess hydrogen. 
     The insulator  408  is, for example, an insulator having a low oxygen-transmitting property (i.e., an oxygen barrier property). 
     The insulator  408  is, for example, an insulator having a low water-transmitting property (i.e., a water barrier property). 
     Note that the conductor  413  is not necessarily formed (see  FIGS. 19A and 19B ). A shape in which the insulator  412  and the insulator  406   c  protrude from the conductor  404  may be employed (see  FIGS. 19C and 19D ). A shape in which the insulator  412  and the insulator  406   c  do not necessarily protrude from the conductor  404  may be employed (see  FIGS. 19E and 19F ). In the A 1 -A 2  cross section, the width of the conductor  413  may be larger than that of the semiconductor  406   b  (see  FIGS. 20A and 20B ). The conductor  413  may be in contact with the conductor  404  through an opening (see  FIGS. 20C and 20D ). The conductor  404  is not necessarily formed (see  FIGS. 20E and 20F ). 
     The insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  will be described. 
     Placing the insulator  406   a  under the semiconductor  406   b  and placing the insulator  406   c  over the semiconductor  406   b  can increase electrical characteristics of the transistor in some cases. 
     The insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  preferably include a CAAC-OS. 
     The semiconductor  406   b  is an oxide containing indium, for example. The oxide semiconductor  406   b  can have high carrier mobility (electron mobility) by containing indium, for example. The semiconductor  406   b  preferably contains an element M The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements which can be used as the element M are boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like. Note that two or more of the above elements may be used in combination as the element M The element M is an element having high bonding energy with oxygen, for example. The element M is an element whose bonding energy with oxygen is higher than that of indium. The element M is an element that can increase the energy gap of the oxide, for example. Furthermore, the semiconductor  406   b  preferably contains zinc. When the oxide contains zinc, the oxide semiconductor is easily crystallized, in some cases. 
     Note that the semiconductor  406   b  is not limited to the oxide containing indium. The semiconductor  406   b  may be, for example, an oxide which does not contain indium and contains zinc, an oxide which does not contain indium and contains gallium, or an oxide which does not contain indium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide. 
     For the semiconductor  406   b,  an oxide with a wide energy gap may be used, for example. For example, the energy gap of the semiconductor  406   b  is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, and further preferably greater than or equal to 3 eV and less than or equal to 3.5 eV. 
     For example, the insulator  406   a  and the insulator  406   c  are oxides including one or more elements, or two or more elements other than oxygen included in the semiconductor  406   b.  Since the insulator  406   a  and the insulator  406   c  each include one or more elements, or two or more elements other than oxygen included in the semiconductor  406   b,  a defect state is less likely to be formed at the interface between the insulator  406   a  and the semiconductor  406   b  and the interface between the semiconductor  406   b  and the insulator  406   c.    
     The insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  preferably include at least indium. In the case of using an In-M-Zn oxide as the insulator  406   a,  when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, further preferably less than 25 atomic % and greater than 75 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor  406   b,  when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be greater than 25 atomic % and less than 75 atomic %, respectively, and further preferably greater than 34 atomic % and less than 66 atomic %, respectively. In the case of using an In-M-Zn oxide as the insulator  406   c,  when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, and further preferably less than 25 atomic % and greater than 75 atomic %, respectively. Note that the insulator  406   c  may be an oxide that is of the same type as the oxide of the insulator  406   a.  Note that the insulator  406   a  and/or the insulator  406   c  do/does not necessarily contain indium in some cases. For example, the insulator  406   a  and/or the insulator  406   c  may be gallium oxide. Note that the atomic ratios of the elements included in the insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  are not necessarily simple ratios of integers. 
     As the semiconductor  406   b,  an oxide having an electron affinity higher than those of the insulators  406   a  and  406   c  is used. For example, as the semiconductor  406   b,  an oxide having an electron affinity higher than those of the insulators  406   a  and  406   c  by 0.07 eV or higher and 1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, further preferably 0.15 eV or higher and 0.4 eV or lower is used. Note that the electron affinity refers to an energy difference between the vacuum level and the conduction band minimum. 
     An indium gallium oxide has small electron affinity and a high oxygen-blocking property. Therefore, the insulator  406   c  preferably includes an indium gallium oxide. The fraction of gallium atoms [Ga/(In+Ga)] is, for example, higher than or equal to 70%, preferably higher than or equal to 80%, further preferably higher than or equal to 90%. 
     At this time, when gate voltage is applied, a channel is formed in the semiconductor  406   b  whose electron affinity is the highest among the insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c.    
     In some cases, there is a mixed region of the insulator  406   a  and the semiconductor  406   b  between the insulator  406   a  and the semiconductor  406   b.  Furthermore, in some cases, there is a mixed region of the semiconductor  406   b  and the insulator  406   c  between the semiconductor  406   b  and the insulator  406   c.  The mixed region has a low density of defect states. For that reason, in a band diagram of a stack including the insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  (see  FIG. 21 ), energy changes continuously at each interface and in the vicinity of the interface (continuous junction). Note that boundaries of the insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  are not clear in some cases. 
     At this time, electrons move mainly in the semiconductor  406   b,  not in the insulator  406   a  and the insulator  406   c.  Note that the insulator  406   a  and the insulator  406   c  can exhibit a property of any of a conductor, a semiconductor, and an insulator when existing alone. When the transistor operates, however, they each have a region where a channel is not formed. Specifically, a channel is formed only in a region near the interface between the insulator  406   a  and the semiconductor  406   b  and a region near the interface between the insulator  406   c  and the semiconductor  406   b,  whereas a channel is not formed in the other region. Therefore, the insulator  406   a  and the insulator  406   c  can be called insulators when the transistor operates, and are thus referred to as, not semiconductors or conductors, but insulators in this specification. The insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  are separately called semiconductor or insulator only because of the relative difference in physical property. Therefore, for example, an insulator that can be used as the insulator  406   a  or the insulator  406   c  can be used as the semiconductor  406   b  in some cases. As described above, when the density of defect states at the interface between the insulator  406   a  and the semiconductor  406   b  and the density of defect states at the interface between the semiconductor  406   b  and the insulator  406   c  are decreased, electron movement in the semiconductor  406   b  is less likely to be inhibited and the on-sate current of the transistor can be increased. 
     As factors of inhibiting electron movement are decreased, the on-state current of the transistor can be increased. For example, in the case where there is no factor of inhibiting electron movement, electrons are assumed to be efficiently moved. Electron movement is inhibited, for example, in the case where physical unevenness of the channel formation region is large. 
     To increase the on-state current of the transistor, for example, root mean square (RMS) roughness with a measurement area of 1 μm×1 μm of the top surface or the bottom surface of the semiconductor  406   b  (a formation surface; here, a top surface of the insulator  406   a ) is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) with the measurement area of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm. The maximum difference (P−V) with the measurement area of 1 μm×1 μm is less than 10 nm, preferably less than 9 nm, further preferably less than 8 nm, still further preferably less than 7 nm. RMS roughness, Ra, and P−V can be measured using a scanning probe microscope SPA-500 manufactured by SII Nano Technology Inc. 
     Moreover, the thickness of the insulator  406   c  is preferably as small as possible to increase the on-state current of the transistor. For example, the insulator  406   c  is formed to include a region with a thickness of less than 10 nm, preferably less than or equal to 5 nm, further preferably less than or equal to 3 nm. Meanwhile, the insulator  406   c  has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor  406   b  where a channel is formed. For this reason, it is preferable that the insulator  406   c  have a certain thickness. For example, the insulator  406   c  is formed to include a region with a thickness of greater than or equal to 0.3 nm, preferably greater than or equal to 1 nm, and further preferably greater than or equal to 2 nm. The insulator  406   c  preferably has an oxygen blocking property to suppress outward diffusion of oxygen released from the insulator  402  and the like. 
     To improve reliability, preferably, the thickness of the insulator  406   a  is large and the thickness of the insulator  406   c  is small. For example, the insulator  406   a  includes a region with a thickness of, for example, greater than or equal to 10 nm, preferably greater than or equal to 20 nm, further preferably greater than or equal to 40 nm, and still further preferably greater than or equal to 60 nm. When the thickness of the insulator  406   a  is made large, a distance from an interface between the adjacent insulator and the insulator  406   a  to the semiconductor  406   b  in which a channel is formed can be large. Since the productivity of the semiconductor device might be decreased, the insulator  406   a  has a region with a thickness of, for example, less than or equal to 200 nm, preferably less than or equal to 120 nm, and further preferably less than or equal to 80 nm. 
     A region with a silicon concentration measured by secondary ion mass spectrometry (SIMS) of higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 1×10 19  atoms/cm 3 , preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 , further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 2×10 18  atoms/cm 3  is provided between the semiconductor  406   b  and the insulator  406   a,  for example. A region with a silicon concentration measured by SIMS of higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 1×10 19  atoms/cm 3 , preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 , further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 2×10 18  atoms/cm 3  is provided between the semiconductor  406   b  and the insulator  406   c.    
     The semiconductor  406   b  includes a region with a hydrogen concentration measured by SIMS of higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 2×10 20  atoms/cm 3 , preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 19  atoms/cm 3 , further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 1×10 19  atoms/cm 3 , or still further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 . It is preferable to reduce the hydrogen concentration in the insulator  406   a  and the insulator  406   c  in order to reduce the hydrogen concentration in the semiconductor  406   b.  The insulator  406   a  and the insulator  406   c  each include a region with a hydrogen concentration measured by SIMS of higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 2×10 20  atoms/cm 3 , preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 19  atoms/cm 3 , further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 1×10 19  atoms/cm 3 , or still further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 . The semiconductor  406   b  includes a region with a nitrogen concentration measured by SIMS of higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 19  atoms/cm 3 , preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 , further preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 1×10 18  atoms/cm 3 , or still further preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 17  atoms/cm 3 . It is preferable to reduce the nitrogen concentration in the insulator  406   a  and the insulator  406   c  in order to reduce the nitrogen concentration in the semiconductor  406   b.  The insulator  406   a  and the insulator  406   c  each include a region with a nitrogen concentration measured by SIMS of higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 19  atoms/cm 3 , preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 , further preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 1×10 18  atoms/cm 3 , or still further preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 17  atoms/cm 3 . 
     The above three-layer structure is an example. For example, a two-layer structure without the insulator  406   a  or the insulator  406   c  may be employed. Alternatively, a four-layer structure in which any one of the semiconductors described as examples of the insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  is provided under or over the insulator  406   a  or under or over the insulator  406   c  may be employed. An n-layer structure (n is an integer of 5 or more) in which one of the semiconductors described as examples of the insulator  406   a,  the semiconductor  406   b,  and the insulator  406   c  is provided at two or more of the following positions: over the insulator  406   a,  under the insulator  406   a,  over the insulator  406   c,  and under the insulator  406   c  may be employed. 
     &lt;Transistor  2 &gt; 
       FIGS. 22A to 22C  are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention.  FIG. 22A  is a top view, and  FIGS. 22B and 22C  are cross-sectional views taken along dashed-dotted lines F 1 -F 2  and F 3 -F 4  in  FIG. 22A , respectively. Note that for simplification of the drawing, some components are not illustrated in the top view in  FIG. 22A . 
     A transistor illustrated in  FIGS. 22A to 22C  includes a conductor  513  over a substrate  500 ; an insulator  503  that is over the substrate  500  and is level with the conductor  513 ; an insulator  502  over the conductor  513  and the insulator  503 ; an insulator  506   a  over the insulator  502 ; a semiconductor  506   b  over the insulator  506   a;  a conductor  516   a  and a conductor  516   b  which are arranged to be separated from each other while being in contact with the top surface of the semiconductor  506   b;  an insulator  506   c  over the insulator  502 , the semiconductor  506   b,  the conductor  516   a,  and the conductor  516   b;  an insulator  512  over the insulator  506   c;  a conductor  504  over the insulator  512 ; and an insulator  508  over the conductor  504 . Note that although the conductor  513  is part of the transistor in this non-limiting example, the conductor  513  may be a component independent of the transistor, for example. Furthermore, the transistor does not necessarily include the insulator  508 . The transistor may include an insulator between the conductor  516   a  and the insulator  506   c  and/or between the conductor  516   b  and the insulator  506   c.  For the insulator, refer to the description of the insulator  410 . 
     For the substrate  500 , refer to the description of the substrate  400 ; for the conductor  513 , that of the conductor  413 ; for the insulator  502 , that of the insulator  402 ; for the insulator  506   a,  that of the insulator  406   a;  for the semiconductor  506   b,  that of the semiconductor  406   b;  for the conductor  516   a,  that of the conductor  416   a;  for the conductor  516   b,  that of the conductor  416   b;  for the insulator  506   c,  that of the insulator  406   c;  for the insulator  512 , that of the insulator  412 ; for the conductor  504 , that of the conductor  404 ; for the insulator  508 , that of the insulator  408 . 
     The insulator  503  may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  503  may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     As illustrated in  FIG. 22C , the transistor has an s-channel structure. The electric field from the conductor  504  and the conductor  513  is less likely to be inhibited by the conductor  516   a,  the conductor  516   b,  and the like at the side surface of the semiconductor  506   b.    
     Note that the conductor  513  is not necessarily formed (see  FIGS. 23A and 23B ). A shape in which the insulator  512  and the insulator  506   c  protrude from the conductor  504  may be employed (see  FIGS. 23C and 23D ). A shape in which the insulator  512  and the insulator  506   c  do not necessarily protrude from the conductor  504  may be employed (see  FIGS. 23E and 23F ). In the F 1 -F 2  cross section, the width of the conductor  513  may be larger than that of the semiconductor  506   b  (see  FIGS. 24A and 24B ). The conductor  513  may be in contact with the conductor  504  through an opening (see  FIGS. 24C and 24D ). The conductor  504  is not necessarily formed (see  FIGS. 24E and 24F ). 
     &lt;Transistor  3 &gt; 
       FIGS. 25A to 25C  are a top view and cross-sectional views of a transistor of one embodiment of the present invention.  FIG. 25A  is the top view.  FIG. 25B  and  FIG. 25C  are the cross-sectional views taken along the dashed-dotted line G 1 -G 2  and the dashed-dotted line G 3 -G 4 , respectively, in  FIG. 25A . Note that for simplification of the drawing, some components are not illustrated in the top view in  FIG. 25A . 
     The transistor shown in  FIGS. 25A to 25C  includes a conductor  613  over a substrate  600 ; an insulator  603  that is over the substrate  600  and is level with the conductor  613 ; an insulator  602  over the conductor  613  and the insulator  603 ; an insulator  606   a  over the insulator  602 ; a semiconductor  606   b  over the insulator  606   a;  an insulator  606   c  over the semiconductor  606   b;  an insulator  612  over the insulator  606   c;  a conductor  604  over the insulator  612 ; an insulator  620  including a region which is in contact with a side surface of the conductor  604  and a top surface of the semiconductor  606   b;  and an insulator  608  over the insulator  602 , the semiconductor  606   b,  the conductor  604 , and the insulator  620 . Although the conductor  613  is part of the transistor, a transistor structure of one embodiment of the present invention is not limited thereto. For example, the conductor  613  may be a component independent of the transistor. The transistor does not necessarily include the insulator  608 . 
     The semiconductor  606   b  includes a region  607   a  and a region  607   b.  A region overlapping with the conductor  604  in the semiconductor  606   b  is provided between the region  607   a  and the region  607   b.  The region  607   a  and the region  607   b  each include a region with a lower resistance than a region in the semiconductor  606   b  except the region  607   a  and the region  607   b.  The region  607   a  and the region  607   b  have a function as the source region and the drain region of the transistor. 
     An insulator  618  may be provided over the insulator  608 . The insulator  618  and the insulator  608  include two opening portions. The two opening portions reach the region  607   a  and the region  607   b.  The conductor  616   a  and the conductor  616   b  fill the two opening portions. At this time, the insulator  620  has a function of suppressing electrical connection of the conductor  616   a  and the conductor  616   b  to the conductor  604 . 
     For the substrate  600 , the description of the substrate  400  is referred to. For the conductor  613 , the description of the conductor  413  is referred to. For the insulator  602 , the description of the insulator  402  is referred to. For the insulator  603 , the description of the insulator  503  is referred to. For the insulator  606   a,  the description of the insulator  406   a  is referred to. For the semiconductor  606   b,  the description of the semiconductor  406   b  is referred to. For the conductor  616   a,  the description of the conductor  416   a  is referred to. For the conductor  616   b,  the description of the conductor  416   b  is referred to. For the insulator  606   c,  the description of the insulator  406   c  is referred to. For the insulator  612 , the description of the insulator  412  is referred to. For the conductor  604 , the description of the conductor  404  is referred to. For the insulator  608 , the description of the insulator  408  is referred to. 
     The insulator  620  may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  620  may be formed using, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     The insulator  618  may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  618  may be formed using, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     As illustrated in  FIG. 25C , the transistor has an s-channel structure. The electric field from the conductor  604  and the conductor  613  is less likely to be inhibited by the conductor  616   a,  the conductor  616   b,  and the like at the side surface of the semiconductor  606   b.    
     Note that the conductor  613  is not necessarily formed (see  FIGS. 26A and 26B ). The conductor  613  may be in contact with the conductor  604  through an opening portion (see  FIGS. 26C and 26D ). Instead of the insulator  602 , a stacked-layer film in which an insulator  602   a,  an insulator  602   b,  and an insulator  602   c  are stacked in the order presented may be used (see  FIGS. 26E and 26F ). 
     The insulators  602   a,    602   b,  and  602   c  may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator  602   a  and the insulator  602   c  are formed using silicon oxide or silicon oxynitride, and the insulator  602   b  is formed using aluminum oxide, magnesium oxide, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. The insulator  602   b  preferably has a carrier trap. In that case, when a potential is applied to the conductor  613 , an electron or the like is trapped by the carrier trap in the insulator  602   b,  so that the threshold voltage of the transistor can be shifted. For example, the threshold voltage of the transistor is shifted in the positive direction, whereby the transistor can have normally-off characteristics. 
     &lt;Circuit&gt; 
     An example of a circuit of the semiconductor device of one embodiment of the present invention will be described below. 
     &lt;CMOS Inverter&gt; 
     A circuit diagram in  FIG. 27A  shows a configuration of what is called a CMOS inverter in which a p-channel transistor  2200  and an n-channel transistor  2100  are connected to each other in series and in which gates of them are connected to each other. 
     &lt;Structure  1  of Semiconductor Device&gt; 
       FIGS. 28A to 28C  are cross-sectional views of the semiconductor device of  FIG. 27A . The semiconductor device illustrated in  FIGS. 28A to 28C  includes the transistor  2200  and the transistor  2100 . The transistor  2100  is placed above the transistor  2200 . Although an example where the transistor illustrated in  FIGS. 22A to 22C  is used as the transistor  2100  is shown, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, any of the transistors illustrated in  FIGS. 18A to 18C ,  FIGS. 19A to 19F ,  FIGS. 20A to 20F ,  FIGS. 23A to 23F ,  FIGS. 24A to 24F , and the like can be used as the transistor  2100 . Therefore, the description regarding the above-mentioned transistors is referred to for the transistor  2100  as appropriate. Note that  FIGS. 28A to 28C  are cross-sectional views of different portions. 
     The transistor  2200  illustrated in  FIGS. 28A to 28C  is a transistor using a semiconductor substrate  450 . The transistor  2200  includes a region  472   a  in the semiconductor substrate  450 , a region  472   b  in the semiconductor substrate  450 , an insulator  462 , and a conductor  454 . 
     In the transistor  2200 , the regions  472   a  and  472   b  have functions of a source region and a drain region. The insulator  462  has a function of a gate insulator. The conductor  454  has a function of a gate electrode. Thus, the resistance of a channel formation region can be controlled by a potential applied to the conductor  454 . In other words, conduction or non-conduction between the region  472   a  and the region  472   b  can be controlled by the potential applied to the conductor  454 . 
     For the semiconductor substrate  450 , a single-material semiconductor substrate of silicon, germanium, or the like or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like may be used, for example. A single crystal silicon substrate is preferably used as the semiconductor substrate  450 . 
     For the semiconductor substrate  450 , a semiconductor substrate including impurities imparting n-type conductivity is used. However, a semiconductor substrate including impurities imparting p-type conductivity may be used as the semiconductor substrate  450 . In that case, a well including impurities imparting the n-type conductivity may be provided in a region where the transistor  2200  is formed. Alternatively, the semiconductor substrate  450  may be an i-type semiconductor substrate. 
     The top surface of the semiconductor substrate  450  preferably has a (110) plane. Thus, on-state characteristics of the transistor  2200  can be improved. 
     The regions  472   a  and  472   b  are regions including impurities imparting the p-type conductivity. Accordingly, the transistor  2200  has a structure of a p-channel transistor. 
     Note that the transistor  2200  is apart from an adjacent transistor by a region  460  and the like. The region  460  is an insulating region. 
     The semiconductor device illustrated in  FIGS. 28A to 28C  includes an insulator  464 , an insulator  466 , an insulator  468 , an insulator  422 , a conductor  480   a,  a conductor  480   b,  a conductor  480   c,  a conductor  478   a,  a conductor  478   b,  a conductor  478   c,  a conductor  476   a,  a conductor  476   b,  a conductor  474   a,  a conductor  474   b,  a conductor  474   c,  a conductor  496   a,  a conductor  496   b,  a conductor  496   c,  a conductor  496   d,  a conductor  498   a,  a conductor  498   b,  a conductor  498   c,  an insulator  490 , the insulator  502 , an insulator  492 , an insulator  428 , an insulator  409 , and an insulator  494 . 
     The insulator  422 , the insulator  428 , and the insulator  409  have barrier properties. This means that the semiconductor device illustrated in  FIGS. 28A to 28C  has a structure in which the transistor  2100  is surrounded by insulators having barrier properties. Note that one or more of the insulator  422 , the insulator  428 , and the insulator  409  are not necessarily provided. 
     The insulator  464  is placed over the transistor  2200 . The insulator  466  is placed over the insulator  464 . The insulator  468  is placed over the insulator  466 . The insulator  490  is placed over the insulator  468 . The transistor  2100  is placed over the insulator  490 . The insulator  492  is placed over the transistor  2100 . The insulator  494  is placed over the insulator  492 . 
     The insulator  464  includes an opening reaching the region  472   a,  an opening reaching the region  472   b,  and an opening reaching the conductor  454 . In the openings, the conductor  480   a,  the conductor  480   b,  and the conductor  480   c  are embedded. 
     The insulator  466  includes an opening reaching the conductor  480   a,  an opening reaching the conductor  480   b,  and an opening reaching the conductor  480   c.  In the openings, the conductor  478   a,  the conductor  478   b,  and the conductor  478   c  are embedded. 
     The insulator  468  and the insulator  422  include an opening reaching the conductor  478   b  and an opening reaching the conductor  478   c.  In the openings, the conductor  476   a  and the conductor  476   b  are embedded. 
     The insulator  490  includes an opening overlapping a channel formation region of the transistor  2100 , an opening reaching the conductor  476   a,  and an opening reaching the conductor  476   b.  In the openings, the conductor  474   a,  the conductor  474   b,  and the conductor  474   c  are embedded. 
     The conductor  474   a  may have a function of a gate electrode of the transistor  2100 . The electrical characteristics of the transistor  2100 , such as the threshold voltage, may be controlled by application of a predetermined potential to the conductor  474   a,  for example. The conductor  474   a  may be electrically connected to the conductor  404  having a function of the gate electrode of the transistor  2100 , for example. In that case, on-state current of the transistor  2100  can be increased. Furthermore, a punch-through phenomenon can be suppressed; thus, the electrical characteristics of the transistor  2100  in a saturation region can be stable. 
     The insulator  409  and the insulator  492  include an opening reaching the conductor  474   b  through the conductor  516   b  that is one of a source electrode and a drain electrode of the transistor  2100 , an opening reaching the conductor  516   a  that is the other of the source electrode and the drain electrode of the transistor  2100 , an opening reaching the conductor  504  that is the gate electrode of the transistor  2100 , and an opening reaching the conductor  474   c.  In the openings, the conductor  496   a,  the conductor  496   b,  the conductor  496   c,  and the conductor  496   d  are embedded. Note that in some cases, the openings are provided through any of components of the transistor  2100  or the like. 
     The insulator  494  includes an opening reaching the conductor  496   a,  an opening reaching the conductor  496   b  and the conductor  496   d,  and an opening reaching the conductor  496   c.  In the openings, the conductor  498   a,  the conductor  498   b,  and the conductor  498   c  are embedded. 
     The insulators  464 ,  466 ,  468 ,  490 ,  492 , and  494  may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  401  may be formed using, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     At least one of the insulators  464 ,  466 ,  468 ,  490 ,  492 , and  494  preferably includes an insulator having a barrier property. 
     An insulator with a function of blocking oxygen and impurities such as hydrogen may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. 
     Each of the conductors  480   a,    480   b,    480   c,    478   a,    478   b,    478   c,    476   a,    476   b,    474   a,    474   b,    474   c,    496   a,    496   b,    496   c,    496   d,    498   a,    498   b,  and  498   c  may be formed to have, for example, a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds selected from boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound containing the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. At least one of the conductors  480   a,    480   b,    480   c,    478   a,    478   b,    478   c,    476   a,    476   b,    474   a,    474   b,    474   c,    496   a,    496   b,    496   c,    496   d,    498   a,    498   b,  and  498   c  preferably includes a conductor having a barrier property. 
     Note that a semiconductor device in  FIGS. 29A to 29C  is the same as the semiconductor device in  FIGS. 28A to 28C  except for the structure of the transistor  2200 . Therefore, the description of the semiconductor device in  FIGS. 28A to 28C  is referred to for the semiconductor device in  FIGS. 29A to 29C . In the semiconductor device in  FIGS. 29A to 29C , the transistor  2200  is a FIN-type transistor. The effective channel width is increased in the FIN-type transistor  2200 , whereby the on-state characteristics of the transistor  2200  can be improved. In addition, since contribution of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor  2200  can be improved. Note that  FIGS. 29A to 29C  are cross-sectional views of different portions. 
     Note that a semiconductor device in  FIGS. 30A to 30C  is the same as the semiconductor device in  FIGS. 28A to 28C  except for the structure of the transistor  2200 . Therefore, the description of the semiconductor device in  FIGS. 28A to 28C  is referred to for the semiconductor device in  FIGS. 30A to 30C . Specifically, in the semiconductor device in  FIGS. 30A to 30C , the transistor  2200  is formed using the semiconductor substrate  450 , which is an SOI substrate. In the structure in  FIGS. 30A to 30C , a region  456  is apart from the semiconductor substrate  450  with an insulator  452  provided therebetween. Since the SOI substrate is used as the semiconductor substrate  450 , a punch-through phenomenon and the like can be suppressed; thus, the off-state characteristics of the transistor  2200  can be improved. Note that the insulator  452  can be formed by turning the semiconductor substrate  450  into an insulator. For example, silicon oxide can be used as the insulator  452 . Note that  FIGS. 30A to 30C  are cross-sectional views of different portions. 
     In each of the semiconductor devices shown in  FIGS. 28A to 28C ,  FIGS. 29A to 29C , and  FIGS. 30A to 30C , a p-channel transistor is formed utilizing a semiconductor substrate, and an n-channel transistor is formed above that; therefore, an occupation area of the element can be reduced. That is, the integration degree of the semiconductor device can be improved. In addition, the manufacturing process can be simplified compared to the case where an n-channel transistor and a p-channel transistor are formed utilizing the same semiconductor substrate; therefore, the productivity of the semiconductor device can be increased. Moreover, the yield of the semiconductor device can be improved. For the p-channel transistor, some complicated steps such as formation of lightly doped drain (LDD) regions, formation of a shallow trench structure, or distortion design can be omitted in some cases. Therefore, the productivity and yield of the semiconductor device can be increased in some cases, compared to a semiconductor device where an n-channel transistor is formed utilizing the semiconductor substrate. 
     &lt;CMOS Analog Switch&gt; 
     A circuit diagram in  FIG. 27B  shows a configuration in which sources of the transistors  2100  and  2200  are connected to each other and drains of the transistors  2100  and  2200  are connected to each other. With such a configuration, the transistors can function as what is called a CMOS analog switch. 
     &lt;Memory Device  1 &gt; 
     An example of a semiconductor device (memory device) which includes the transistor of one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is shown in  FIGS. 31A and 31B . 
     The semiconductor device illustrated in  FIG. 31A  includes a transistor  3200  using a first semiconductor, a transistor  3300  using a second semiconductor, and a capacitor  3400 . Note that any of the above-described transistors can be used as the transistor  3300 . 
     Note that the transistor  3300  is preferably a transistor with a low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor  3300 . Since the off-state current of the transistor  3300  is low, stored data can be retained for a long period at a predetermined node of the semiconductor device. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. 
     In  FIG. 31A , a first wiring  3001  is electrically connected to a source of the transistor  3200 . A second wiring  3002  is electrically connected to a drain of the transistor  3200 . A third wiring  3003  is electrically connected to one of the source and the drain of the transistor  3300 . A fourth wiring  3004  is electrically connected to the gate of the transistor  3300 . The gate of the transistor  3200  and the other of the source and the drain of the transistor  3300  are electrically connected to the one electrode of the capacitor  3400 . A fifth wiring  3005  is electrically connected to the other electrode of the capacitor  3400 . 
     The semiconductor device in  FIG. 31A  has a feature that the potential of the gate of the transistor  3200  can be retained, and thus enables writing, retaining, and reading of data as follows. 
     Writing and retaining of data are described. First, the potential of the fourth wiring  3004  is set to a potential at which the transistor  3300  is on, so that the transistor  3300  is turned on. Accordingly, the potential of the third wiring  3003  is supplied to a node FG where the gate of the transistor  3200  and the one electrode of the capacitor  3400  are electrically connected to each other. That is, a predetermined charge is supplied to the gate of the transistor  3200  (writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the fourth wiring  3004  is set to a potential at which the transistor  3300  is off, so that the transistor  3300  is turned off. Thus, the charge is held at the node FG (retaining). 
     Since the off-state current of the transistor  3300  is low, the charge of the node FG is retained for a long time. 
     Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the fifth wiring  3005  while a predetermined potential (a constant potential) is supplied to the first wiring  3001 , whereby the potential of the second wiring  3002  varies depending on the amount of charge retained in the node FG. This is because in the case of using an n-channel transistor as the transistor  3200 , an apparent threshold voltage V th   _   H  at the time when the high-level charge is given to the gate of the transistor  3200  is lower than an apparent threshold voltage V th   _   L  at the time when the low-level charge is given to the gate of the transistor  3200 . Here, an apparent threshold voltage refers to the potential of the fifth wiring  3005  which is needed to make the transistor  3200  be in an “on state.” Thus, the potential of the fifth wiring  3005  is set to a potential V 0  which is between V th   _   H  and V th   _   L , whereby charge supplied to the node FG can be determined. For example, in the case where the high-level charge is supplied to the node FG in writing and the potential of the fifth wiring  3005  is V 0  (&gt;V th   _   H ), the transistor  3200  is brought into an “on state.” In the case where the low-level charge is supplied to the node FG in writing, even when the potential of the fifth wiring  3005  is V 0  (&lt;V th   _   L ), the transistor  3200  still remains in an “off state.” Thus, the data retained in the node FG can be read by determining the potential of the second wiring  3002 . 
     Note that in the case where memory cells are arrayed, it is necessary that data of a desired memory cell be read in read operation. A configuration in which only data of a desired memory cell can be read by supplying a potential at which the transistor  3200  is in “off state” regardless of the electric charge supplied to the node FG, that is, a potential lower than V th   _   H  to the fifth wiring  3005  of memory cells from which data is not read may be employed. Alternatively, a configuration in which only data of a desired memory cell can be read by supplying a potential at which the transistor  3200  is brought into “on state” regardless of the electric charge supplied to the node FG, that is, a potential higher than V th   _   L  to the fifth wiring  3005  of memory cells from which data is not read may be employed. 
     &lt;Structure  2  of Semiconductor Device&gt; 
       FIGS. 32A to 32C  are cross-sectional views of the semiconductor device of  FIG. 31A . The semiconductor device illustrated in  FIGS. 32A to 32C  includes the transistor  3200 , the transistor  3300 , and the capacitor  3400 . The transistor  3300  and the capacitor  3400  are placed above the transistor  3200 . Note that for the transistor  3300 , refer to the description of the above transistor  2100 . Furthermore, for the transistor  3200 , refer to the description of the transistor  2200  in  FIGS. 28A to 28C . Note that although the transistor  2200  is illustrated as a p-channel transistor in  FIGS. 28A to 28C , the transistor  3200  may be an n-channel transistor. Note that  FIGS. 32A to 32C  are cross-sectional views of different portions. 
     The transistor  2200  illustrated in  FIGS. 32A to 32C  is a transistor using a semiconductor substrate  450 . The transistor  2200  includes a region  472   a  in the semiconductor substrate  450 , a region  472   b  in the semiconductor substrate  450 , an insulator  462 , and a conductor  454 . 
     The semiconductor device  FIGS. 32A to 32C  includes the insulator  464 , the insulator  466 , the insulator  468 , the insulator  422 , the conductor  480   a,  the conductor  480   b,  the conductor  480   c,  the conductor  478   a,  the conductor  478   b,  the conductor  478   c,  the conductor  476   a,  the conductor  476   b,  the conductor  474   a,  the conductor  474   b,  the conductor  474   c,  the conductor  496   a,  the conductor  496   b,  the conductor  496   c,  the conductor  496   d,  the conductor  498   a,  the conductor  498   b,  the conductor  498   c,  a conductor  498   d,  the insulator  490 , the insulator  502 , the insulator  492 , the insulator  428 , the insulator  409 , and the insulator  494 . 
     The insulator  422 , the insulator  428 , and the insulator  409  have barrier properties. This means that the semiconductor device illustrated in  FIGS. 32A to 32C  has a structure in which the transistor  3300  is surrounded by insulators having barrier properties. Note that one or more of the insulator  422 , the insulator  428 , and the insulator  409  are not necessarily provided. 
     The insulator  464  is provided over the transistor  3200 . The insulator  466  is provided over the insulator  464 . The insulator  468  is provided over the insulator  466 . The insulator  490  is provided over the insulator  468 . The transistor  2100  is provided over the insulator  490 . The insulator  492  is provided over the transistor  2100 . The insulator  494  is provided over the insulator  492 . 
     The insulator  464  has an opening reaching the region  472   a,  an opening reaching the region  472   b,  and an opening reaching the conductor  454 . In the openings, the conductor  480   a,  the conductor  480   b,  and the conductor  480   c  are embedded. 
     The insulator  466  includes an opening reaching the conductor  480   a,  an opening reaching the conductor  480   b,  and an opening reaching the conductor  480   c.  In the openings, the conductor  478   a,  the conductor  478   b,  and the conductor  478   c  are embedded. 
     The insulator  468  and the insulator  422  include an opening reaching the conductor  478   b  and an opening reaching the conductor  478   c.  In the openings, the conductor  476   a  and the conductor  476   b  are embedded. 
     The insulator  490  includes an opening overlapping the channel formation region of the transistor  3300 , an opening reaching the conductor  476   a,  and an opening reaching the conductor  476   b.  In the openings, the conductor  474   a,  the conductor  474   b,  and the conductor  474   c  are embedded. 
     The conductor  474   a  may have a function as a bottom gate electrode of the transistor  3300 . Alternatively, for example, electric characteristics such as the threshold voltage of the transistor  3300  may be controlled by application of a predetermined potential to the conductor  474   a.  Further alternatively, for example, the conductor  474   a  and the conductor  404  that is the top gate electrode of the transistor  3300  may be electrically connected to each other. Thus, the on-state current of the transistor  3300  can be increased. A punch-through phenomenon can be suppressed; thus, stable electric characteristics in the saturation region of the transistor  3300  can be obtained. 
     The insulator  409  and the insulator  492  include an opening reaching the conductor  474   b  through the conductor  516   b  that is one of a source electrode and a drain electrode of the transistor  3300 , an opening reaching a conductor  514  that overlaps with the conductor  516   a  that is the other of the source electrode and the drain electrode of the transistor  3300 , with the insulator  512  positioned therebetween, an opening reaching the conductor  504  that is the gate electrode of the transistor  3300 , and an opening reaching the conductor  474   c  through the conductor  516   a  that is the other of the source electrode and the drain electrode of the transistor  3300 . In the openings, the conductor  496   a,  the conductor  496   b,  the conductor  496   c,  and the conductor  496   d  are embedded. Note that in some cases, a component of the transistor  3300  or the like is through other components. 
     The insulator  494  includes an opening reaching the conductor  496   a,  an opening reaching the conductor  496   b,  an opening reaching the conductor  496   c,  and an opening reaching the conductor  496   d.  In the openings, the conductors  498   a,    498   b,    498   c,  and  498   d  are embedded. 
     At least one of the insulators  464 ,  466 ,  468 ,  490 ,  492 , and  494  preferably includes an insulator having a barrier property. 
     The conductor  498   d  may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds selected from boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. Each of the conductors  498   a,    498   b,    498   c,  and  498   d  preferably includes a conductor having a barrier property. 
     The source or drain of the transistor  3200  is electrically connected to the conductor  516   b  that is one of a source electrode and a drain electrode of the transistor  3300  through the conductor  480   b,  the conductor  478   b,  the conductor  476   a,  the conductor  474   b,  and the conductor  496   c.  The conductor  454  that is the gate electrode of the transistor  3200  is electrically connected to the conductor  516   a  that is the other of the source electrode and the drain electrode of the transistor  3300  through the conductor  480   c,  the conductor  478   c,  the conductor  476   b,  the conductor  474   c,  and the conductor  496   d.    
     The capacitor  3400  includes an electrode electrically connected to the other of the source electrode and the drain electrode of the transistor  3300 , the conductor  514 , and the insulator  512 . The insulator  512  included in the capacitor  3400  has and can be formed in the same step as a region serving as a gate insulator of the transistor  3300 . Thus, productivity can be preferably increased in some cases. When a layer formed by the same step as the conductor  504  serving as a gate electrode of the transistor  3300  is used as the conductor  514 , productivity can be preferably increased in some cases. 
     For the structures of other components, the description of  FIGS. 28A to 28C  and the like can be referred to as appropriate. 
     A semiconductor device in  FIGS. 33A to 33C  is the same as the semiconductor device in  FIGS. 32A to 32C  except for the structure of the transistor  3200 . Therefore, the description of the semiconductor device in  FIGS. 32A to 32C  is referred to for the semiconductor device in  FIGS. 33A to 33C . Specifically, in the semiconductor device in  FIGS. 33A to 33C , the transistor  3200  is a FIN-type transistor. For the FIN-type transistor  3200 , refer to the description of the transistor  2200  in  FIGS. 29A to 29C . Note that although the transistor  2200  is illustrated as a p-channel transistor in  FIGS. 29A to 29C , the transistor  3200  may be an n-channel transistor. Note that  FIGS. 33A to 33C  are cross-sectional views of different portions. 
     A semiconductor device in  FIGS. 34A to 34C  is the same as the semiconductor device in  FIGS. 32A to 32C  except for the structure of the transistor  3200 . Therefore, the description of the semiconductor device in  FIGS. 32A to 32C  is referred to for the semiconductor device in  FIGS. 34A to 34C . Specifically, in the semiconductor device in  FIGS. 34A to 34C , the transistor  3200  is provided in the semiconductor substrate  450  that is an SOI substrate. For the transistor  3200 , which is provided in the semiconductor substrate  450  that is an SOI substrate, refer to the description of the transistor  2200  in  FIGS. 30A to 30C . Note that although the transistor  2200  is illustrated as a p-channel transistor in  FIGS. 30A to 30C , the transistor  3200  may be an n-channel transistor. Note that  FIGS. 34A to 34C  are cross-sectional views of different portions. 
     &lt;Memory Device  2 &gt; 
     The semiconductor device in  FIG. 31B  is different from the semiconductor device in  FIG. 31A  in that the transistor  3200  is not provided. Also in this case, data can be written and retained in a manner similar to that of the semiconductor device in  FIG. 31A . 
     Reading of data in the semiconductor device in  FIG. 31B  is described. When the transistor  3300  is brought into an on state, the third wiring  3003  which is in a floating state and the capacitor  3400  are brought into conduction, and the charge is redistributed between the third wiring  3003  and the capacitor  3400 . As a result, the potential of the third wiring  3003  is changed. The amount of change in the potential of the third wiring  3003  varies depending on the potential of the one electrode of the capacitor  3400  (or the charge accumulated in the capacitor  3400 ). 
     For example, the potential of the third wiring  3003  after the charge redistribution is (C B ×V B0 +C×V)/(C B +C), where V is the potential of the one electrode of the capacitor  3400 , C is the capacitance of the capacitor  3400 , C B  is the capacitance component of the third wiring  3003 , and V B0  is the potential of the third wiring  3003  before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the one electrode of the capacitor  3400  is V 1  and V 0  (V 1 &gt;V 0 ), the potential of the third wiring  3003  in the case of retaining the potential V 1  (=(C B ×V B0 +C×V 1 )/(C B +C)) is higher than the potential of the third wiring  3003  in the case of retaining the potential V 0  (=(C B ×V B0 +C×V 0 )/(C B +C)). 
     Then, by comparing the potential of the third wiring  3003  with a predetermined potential, data can be read. 
     In this case, a transistor including the first semiconductor may be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor may be stacked over the driver circuit as the transistor  3300 . 
     When including a transistor using an oxide semiconductor and having a low off-state current, the semiconductor device described above can retain stored data for a long time. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed). 
     In the semiconductor device, high voltage is not needed for writing data and deterioration of elements is less likely to occur. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, the semiconductor device of one embodiment of the present invention does not have a limit on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the on/off state of the transistor, whereby high-speed operation can be achieved. 
     &lt;Imaging Device&gt; 
     An imaging device of one embodiment of the present invention will be described below. 
       FIG. 35A  is a plan view illustrating an example of an imaging device  2000  of one embodiment of the present invention. The imaging device  2000  includes a pixel portion  2010  and peripheral circuits for driving the pixel portion  2010  (a peripheral circuit  2060 , a peripheral circuit  2070 , a peripheral circuit  2080 , and a peripheral circuit  2090 ). The pixel portion  2010  includes a plurality of pixels  2011  arranged in a matrix with p rows and q columns (p and q are each a natural number greater than or equal to 2). The peripheral circuit  2060 , the peripheral circuit  2070 , the peripheral circuit  2080 , and the peripheral circuit  2090  are each connected to the plurality of pixels  2011  and each have a function of supplying a signal for driving the plurality of pixels  2011 . In this specification and the like, in some cases, a “peripheral circuit” or a “driver circuit” indicates all of the peripheral circuits  2060 ,  2070 ,  2080 , and  2090 . For example, the peripheral circuit  2060  can be regarded as part of the peripheral circuit. 
     The imaging device  2000  preferably includes a light source  2091 . The light source  2091  can emit detection light P 1 . 
     The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a converter circuit. The peripheral circuit may be formed over a substrate where the pixel portion  2010  is formed. Alternatively, a semiconductor device such as an IC chip may be used as part or the whole of the peripheral circuit. Note that as the peripheral circuit, one or more of the peripheral circuits  2060 ,  2070 ,  2080 , and  2090  may be omitted. 
     As illustrated in  FIG. 35B , the pixels  2011  may be obliquely arranged in the pixel portion  2010  in the imaging device  2000 . When the pixels  2011  are obliquely arranged, the distance between pixels (pitch) can be shortened in the row direction and the column direction. Accordingly, the quality of an image taken by the imaging device  2000  can be improved. 
     &lt;Configuration Example 1 of Pixel&gt; 
     Each of the pixels  2011  included in the imaging device  2000  is formed with a plurality of subpixels  2012 , and each subpixel  2012  is combined with a filter (color filter) which transmits light with a specific wavelength band, whereby data for achieving color image display can be obtained. 
       FIG. 36A  is a plan view illustrating an example of the pixel  2011  with which a color image is obtained. The pixel  2011  illustrated in  FIG. 36A  includes the subpixel  2012  provided with a color filter transmitting light with a red (R) wavelength band (also referred to as a “subpixel  2012 R”), the subpixel  2012  provided with a color filter transmitting light with a green (G) wavelength band (also referred to as a “subpixel  2012 G”), and the subpixel  2012  provided with a color filter transmitting light with a blue (B) wavelength band (also referred to as a “subpixel  2012 B”). The subpixels  2012  can function as photosensors. 
     Each of the subpixels  2012  (the subpixel  2012 R, the subpixel  2012 G, and the subpixel  2012 B) is electrically connected to a wiring  2031 , a wiring  2047 , a wiring  2048 , a wiring  2049 , and a wiring  2050 . In addition, the subpixel  2012 R, the subpixel  2012 G, and the subpixel  2012 B are connected to respective wirings  2053  which are independent from one another. In this specification and the like, for example, the wiring  2048  and the wiring  2049  that are connected to the pixels  2011  in an n-th row are referred to as a wiring  2048 [ n ] and a wiring  2049 [ n ], respectively. Furthermore, for example, the wiring  2053  connected to the pixels  2011  in an m-th column is referred to as a wiring  2053 [ m ]. Note that in  FIG. 36A , the wirings  2053  connected to the subpixel  2012 R, the subpixel  2012 G, and the subpixel  2012 B in the pixel  2011  in the m-th column are referred to as a wiring  2053 [ m ]R, a wiring  2053 [ m ]G, and a wiring  2053 [ m ]B, respectively. The subpixels  2012  are electrically connected to the peripheral circuits through the above wirings. 
     In the imaging device  2000 , the subpixel  2012  is electrically connected to the subpixel  2012 , which is in an adjacent pixel  2011  and is provided with a color filter transmitting light with the same wavelength band, via a switch.  FIG. 36B  illustrates a connection example of the subpixels  2012 : the subpixel  2012  in the pixel  2011  arranged in the n-th (n is an integer greater than or equal to 1 and less than or equal to p) row and the m-th (m is an integer greater than or equal to 1 and less than or equal to q) column and the subpixel  2012  in the adjacent pixel  2011  arranged in an (n+1)-th row and the m-th column. In  FIG. 36B , the subpixel  2012 R arranged in the n-th row and the m-th column and the subpixel  2012 R arranged in the (n+1)-th row and the m-th column are connected to each other via a switch  2001 . The subpixel  2012 G arranged in the n-th row and the m-th column and the subpixel  2012 G arranged in the (n+1)-th row and the m-th column are connected to each other via a switch  2002 . The subpixel  2012 B arranged in the n-th row and the m-th column and the subpixel  2012 B arranged in the (n+1)-th row and the m-th column are connected to each other via a switch  2003 . 
     The color filters used in the subpixels  2012  are not limited to red (R), green (G), and blue (B) color filters, and color filters that transmit light of cyan (C), yellow (Y), and magenta (M) may be used. By provision of the subpixels  2012  that sense light with three different wavelength bands in one pixel  2011 , a full-color image can be obtained. 
     The pixel  2011  including the subpixel  2012  provided with a color filter transmitting yellow (Y) light may be provided, in addition to the subpixels  2012  provided with the color filters transmitting red (R), green (G), and blue (B) light. The pixel  2011  including the subpixel  2012  provided with a color filter transmitting blue (B) light may be provided, in addition to the subpixels  2012  provided with color filters transmitting cyan (C), yellow (Y), and magenta (M) light. When the subpixels  2012  sensing light with four different wavelength bands are provided in one pixel  2011 , the reproducibility of colors of an obtained image can be increased. 
     For example, in  FIG. 36A , in regard to the subpixel  2012  sensing a red wavelength band, the subpixel  2012  sensing a green wavelength band, and the subpixel  2012  sensing a blue wavelength band, the pixel number ratio (or the light receiving area ratio) thereof is not necessarily 1:1:1. For example, the Bayer arrangement in which the pixel number ratio (the light receiving area ratio) of red and green to blue is 1:2:1 may be employed. Alternatively, the pixel number ratio (the light receiving area ratio) of red and green to blue may be 1:6:1. 
     Although the number of subpixels  2012  provided in the pixel  2011  may be one, two or more subpixels are preferably provided. For example, when two or more subpixels  2012  sensing the same wavelength band are provided, the redundancy is increased, and the reliability of the imaging device  2000  can be increased. 
     When an infrared (IR) filter that transmits infrared light and absorbs or reflects visible light is used as the filter, the imaging device  2000  that senses infrared light can be achieved. 
     Furthermore, when a neutral density (ND) filter (dark filter) is used, output saturation which occurs when a large amount of light enters a photoelectric conversion element (light-receiving element) can be prevented. With a combination of ND filters with different dimming capabilities, the dynamic range of the imaging device can be increased. 
     Besides the above-described filter, the pixel  2011  may be provided with a lens. Arrangement examples of the pixel  2011 , filters  2054 , and a lens  2055  are described with cross-sectional views in  FIGS. 37A and 37B . With the lens  2055 , the photoelectric conversion element can efficiently receive incident light. Specifically, as illustrated in  FIG. 37A , light  2056  enters a photoelectric conversion element  2020  through the lens  2055 , the filters  2054  (a filter  2054 R, a filter  2054 G, and a filter  2054 B), a pixel circuit  2030 , and the like which are provided in the pixel  2011 . 
     However, as illustrated in a region surrounded by a two-dot chain line, part of the light  2056  indicated by arrows might be blocked by part of a wiring  2057 . Thus, a preferred structure is such that the lens  2055  and the filters  2054  are provided on the photoelectric conversion element  2020  side, so that the photoelectric conversion element  2020  can efficiently receive the light  2056  as illustrated in  FIG. 37B . When the light  2056  is incident on the photoelectric conversion element  2020  through the photoelectric conversion element  2020 , the imaging device  2000  with high sensitivity can be provided. 
     As each of the photoelectric conversion elements  2020  illustrated in  FIGS. 37A and 37B , a photoelectric conversion element in which a p-n junction or a p-i-n junction is formed may be used. 
     The photoelectric conversion element  2020  may be formed using a substance that has a function of absorbing a radiation and generating electric charges. Examples of the substance that has a function of absorbing radiation and generating electric charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and a cadmium zinc alloy. 
     The use of selenium for the photoelectric conversion element  2020  enables the photoelectric conversion element  2020  to have a light absorption coefficient over a wide wavelength range including X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared rays, for example. 
     One pixel  2011  included in the imaging device  2000  may include the subpixel  2012  with a first filter, in addition to the subpixels  2012  illustrated in  FIGS. 36A and 36B . 
     &lt;Configuration Example 2 of Pixel&gt; 
     An example of a pixel including a transistor using silicon and a transistor using an oxide semiconductor is described below. 
       FIGS. 38A and 38B  are each a cross-sectional view of an element included in an imaging device. The imaging device illustrated in  FIG. 38A  includes a transistor  2351  including silicon over a silicon substrate  2300 , transistors  2352  and  2353  which include an oxide semiconductor and are stacked over the transistor  2351 , and a photodiode  2360  provided in a silicon substrate  2300 . The transistors and the photodiode  2360  are electrically connected to various plugs  2370  and wirings  2371 . In addition, an anode  2361  of the photodiode  2360  is electrically connected to the plug  2370  through a low-resistance region  2363 . 
     The imaging device includes a layer  2310  including the transistor  2351  provided on the silicon substrate  2300  and the photodiode  2360  provided in the silicon substrate  2300 , a layer  2320  which is in contact with the layer  2310  and includes the wirings  2371 , a layer  2330  which is in contact with the layer  2320  and includes the transistors  2352  and  2353 , and a layer  2340  which is in contact with the layer  2330  and includes a wiring  2372  and a wiring  2373 . 
     In the example of cross-sectional view in  FIG. 38A , a light-receiving surface of the photodiode  2360  is provided on the side opposite to a surface of the silicon substrate  2300  where the transistor  2351  is formed. With this structure, a light path can be secured without an influence of the transistors and the wirings. Thus, a pixel with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode  2360  can be the same as the surface where the transistor  2351  is formed. 
     In the case where a pixel is formed with use of a transistor using an oxide semiconductor, the layer  2310  may include the transistor using an oxide semiconductor. Alternatively, the layer  2310  may be omitted, and the pixel may include only transistors using an oxide semiconductor. 
     In the case where a pixel is formed with use of a transistor using silicon, the layer  2330  may be omitted. An example of a cross-sectional view in which the layer  2330  is not provided is shown in  FIG. 38B . 
     Note that the silicon substrate  2300  may be an SOI substrate. Furthermore, the silicon substrate  2300  can be replaced with a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. 
     Here, an insulator  2422  is provided between the layer  2310  including the transistor  2351  and the photodiode  2360  and the layer  2330  including the transistors  2352  and  2353 . However, there is no limitation on the position of the insulator  2422 . 
     Hydrogen in an insulator provided in the vicinity of a channel formation region of the transistor  2351  terminates dangling bonds of silicon and thus can improve the reliability of the transistor  2351 . In contrast, hydrogen in an insulator provided in the vicinity of the transistor  2352 , the transistor  2353 , and the like becomes one of factors generating a carrier in the oxide semiconductor and thus may cause a reduction of the reliability of the transistor  2352 , the transistor  2353 , and the like. For this reason, in the case where the transistor using an oxide semiconductor is provided over the transistor using silicon, it is preferable that the insulator  2422  having a barrier property be provided between the transistors. Each of the transistor  2352  and the transistor  2353  is preferably surrounded by an insulator  2418  having a barrier property in all directions. In addition, an insulator  2409  having a barrier property is preferably provided over the transistor  2352  and the transistor  2353  to cover the transistors. When the hydrogen is confined below the insulator  2422 , the reliability of the transistor  2351  can be improved. In addition, the hydrogen can be prevented from being diffused from a part below the insulator  2422  to a part above the insulator  2422 ; thus, the reliability of the transistor  2352 , the transistor  2353 , and the like can be improved. 
     The semiconductor device illustrated in  FIGS. 38A and 38B  has a structure in which the transistor  2352  and the transistor  2353  are surrounded by insulators having barrier properties. Note that the transistor  2352  and the transistor  2353  are not necessarily surrounded by insulators having barrier properties. 
     In the cross-sectional view in  FIG. 38A , the photodiode  2360  in the layer  2310  and the transistor in the layer  2330  can be formed so as to overlap with each other. Thus, the degree of integration of pixels can be increased. In other words, the resolution of the imaging device can be increased. 
     A filter  2354  and/or a lens  2355  may be provided over or under the pixel as shown in  FIGS. 39A and 39B . For the filter  2354 , refer to the description of the filter  2054 . For the lens  2355 , refer to for the description of the lens  2055 . 
     As illustrated in FIG.  40 A 1  and FIG.  40 B 1 , part or the whole of the imaging device can be bent. FIG.  40 A 1  illustrates a state in which the imaging device is bent in the direction of a dashed-dotted line X 1 -X 2 . FIG.  40 A 2  is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X 1 -X 2  in FIG.  40 A 1 . FIG.  40 A 3  is a cross-sectional view illustrating a portion indicated by a dashed-dotted line Y 1 -Y 2  in FIG.  40 A 1 . 
     FIG.  40 B 1  illustrates a state where the imaging device is bent in the direction of a dashed-dotted line X 3 -X 4  and the direction of a dashed-dotted line Y 3 -Y 4 . FIG.  40 B 2  is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X 3 -X 4  in FIG.  40 B 1 . FIG.  40 B 3  is a cross-sectional view illustrating a portion indicated by the dashed-dotted line Y 3 -Y 4  in FIG.  40 B 1 . 
     The bent imaging device enables the curvature of field and astigmatism to be reduced. Thus, the optical design of lens and the like, which is used in combination of the imaging device, can be facilitated. For example, the number of lens used for aberration correction can be reduced; accordingly, a reduction of size or weight of electronic devices using the imaging device, and the like, can be achieved. In addition, the quality of a captured image can be improved. 
     &lt;CPU&gt; 
     A CPU including a semiconductor device such as any of the above-described transistors or the above-described memory device is described below. 
       FIG. 41  is a block diagram illustrating a configuration example of a CPU including any of the above-described transistors as a component. 
     The CPU illustrated in  FIG. 41  includes, over a substrate  1190 , an arithmetic logic unit (ALU)  1191 , an ALU controller  1192 , an instruction decoder  1193 , an interrupt controller  1194 , a timing controller  1195 , a register  1196 , a register controller  1197 , a bus interface  1198 , a rewritable ROM  1199 , and a ROM interface  1189 . A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate  1190 . The ROM  1199  and the ROM interface  1189  may be provided over a separate chip. Needless to say, the CPU in  FIG. 41  is just an example in which the configuration has been simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in  FIG. 41  or an arithmetic circuit is considered as one core; a plurality of such cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example. 
     An instruction that is input to the CPU through the bus interface  1198  is input to the instruction decoder  1193  and decoded therein, and then, input to the ALU controller  1192 , the interrupt controller  1194 , the register controller  1197 , and the timing controller  1195 . 
     The ALU controller  1192 , the interrupt controller  1194 , the register controller  1197 , and the timing controller  1195  conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller  1192  generates signals for controlling the operation of the ALU  1191 . While the CPU is executing a program, the interrupt controller  1194  judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller  1197  generates an address of the register  1196 , and reads/writes data from/to the register  1196  in accordance with the state of the CPU. 
     The timing controller  1195  generates signals for controlling operation timings of the ALU  1191 , the ALU controller  1192 , the instruction decoder  1193 , the interrupt controller  1194 , and the register controller  1197 . For example, the timing controller  1195  includes an internal clock generator for generating an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the above circuits. 
     In the CPU illustrated in  FIG. 41 , a memory cell is provided in the register  1196 . For the memory cell of the register  1196 , any of the above-described transistors, the above-described memory device, or the like can be used. 
     In the CPU illustrated in  FIG. 41 , the register controller  1197  selects operation of retaining data in the register  1196  in accordance with an instruction from the ALU  1191 . That is, the register controller  1197  selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register  1196 . When data retention by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register  1196 . When data retention by the capacitor is selected, the data is rewritten in the capacitor, and supply of a power supply voltage to the memory cell in the register  1196  can be stopped. 
       FIG. 42  is an example of a circuit diagram of a memory element  1200  that can be used as the register  1196 . The memory element  1200  includes a circuit  1201  in which stored data is volatile when power supply is stopped, a circuit  1202  in which stored data is nonvolatile even when power supply is stopped, a switch  1203 , a switch  1204 , a logic element  1206 , a capacitor  1207 , and a circuit  1220  having a selecting function. The circuit  1202  includes a capacitor  1208 , a transistor  1209 , and a transistor  1210 . Note that the memory element  1200  may further include another element such as a diode, a resistor, or an inductor, as needed. 
     Here, the above-described memory device can be used as the circuit  1202 . When supply of a power supply voltage to the memory element  1200  is stopped, GND (0 V) or a potential at which the transistor  1209  in the circuit  1202  is turned off continues to be input to a gate of the transistor  1209 . For example, the gate of the transistor  1209  is grounded through a load such as a resistor. 
     Shown here is an example in which the switch  1203  is a transistor  1213  having one conductivity type (e.g., an n-channel transistor) and the switch  1204  is a transistor  1214  having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor). A first terminal of the switch  1203  corresponds to one of a source and a drain of the transistor  1213 , a second terminal of the switch  1203  corresponds to the other of the source and the drain of the transistor  1213 , and conduction or non-conduction between the first terminal and the second terminal of the switch  1203  (i.e., the on/off state of the transistor  1213 ) is selected by a control signal RD input to a gate of the transistor  1213 . A first terminal of the switch  1204  corresponds to one of a source and a drain of the transistor  1214 , a second terminal of the switch  1204  corresponds to the other of the source and the drain of the transistor  1214 , and conduction or non-conduction between the first terminal and the second terminal of the switch  1204  (i.e., the on/off state of the transistor  1214 ) is selected by the control signal RD input to a gate of the transistor  1214 . 
     One of a source and a drain of the transistor  1209  is electrically connected to one of a pair of electrodes of the capacitor  1208  and a gate of the transistor  1210 . Here, the connection portion is referred to as a node M 2 . One of a source and a drain of the transistor  1210  is electrically connected to a line which can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch  1203  (the one of the source and the drain of the transistor  1213 ). The second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) is electrically connected to the first terminal of the switch  1204  (the one of the source and the drain of the transistor  1214 ). The second terminal of the switch  1204  (the other of the source and the drain of the transistor  1214 ) is electrically connected to a line which can supply a power supply potential VDD. The second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ), the first terminal of the switch  1204  (the one of the source and the drain of the transistor  1214 ), an input terminal of the logic element  1206 , and one of a pair of electrodes of the capacitor  1207  are electrically connected to each other. Here, the connection portion is referred to as a node M 1 . The other of the pair of electrodes of the capacitor  1207  can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor  1207  can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor  1207  is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor  1208  can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor  1208  can be supplied with the low power supply potential (e.g., GND) or the high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor  1208  is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). 
     The capacitor  1207  and the capacitor  1208  are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized. 
     A control signal WE is input to the gate of the transistor  1209 . As for each of the switch  1203  and the switch  1204 , a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state. 
     A signal corresponding to data retained in the circuit  1201  is input to the other of the source and the drain of the transistor  1209 .  FIG. 42  illustrates an example in which a signal output from the circuit  1201  is input to the other of the source and the drain of the transistor  1209 . The logic value of a signal output from the second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) is inverted by the logic element  1206 , and the inverted signal is input to the circuit  1201  through the circuit  1220 . 
     In the example of  FIG. 42 , a signal output from the second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) is input to the circuit  1201  through the logic element  1206  and the circuit  1220 ; however, one embodiment of the present invention is not limited thereto. The signal output from the second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) may be input to the circuit  1201  without its logic value being inverted. For example, in the case where the circuit  1201  includes a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained, the signal output from the second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) can be input to the node. 
     In  FIG. 42 , the transistors included in the memory element  1200  except for the transistor  1209  can each be a transistor in which a channel is formed in a film formed using a semiconductor other than an oxide semiconductor or in the substrate  1190 . For example, the transistor can be a transistor whose channel is formed in a silicon film or a silicon substrate. Alternatively, all the transistors in the memory element  1200  may be a transistor in which a channel is formed in an oxide semiconductor. Further alternatively, in the memory element  1200 , a transistor in which a channel is formed in an oxide semiconductor may be included besides the transistor  1209 , and a transistor in which a channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate  1190  can be used for the rest of the transistors. 
     As the circuit  1201  in  FIG. 42 , for example, a flip-flop circuit can be used. As the logic element  1206 , for example, an inverter or a clocked inverter can be used. 
     In a period during which the memory element  1200  is not supplied with the power supply voltage, the semiconductor device of one embodiment of the present invention can retain data stored in the circuit  1201  by the capacitor  1208  which is provided in the circuit  1202 . 
     The off-state current of a transistor in which a channel is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when the transistor is used as the transistor  1209 , a signal held in the capacitor  1208  is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element  1200 . The memory element  1200  can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped. 
     Since the above-described memory element performs pre-charge operation with the switch  1203  and the switch  1204 , the time required for the circuit  1201  to retain original data again after the supply of the power supply voltage is restarted can be shortened. 
     In the circuit  1202 , a signal retained by the capacitor  1208  is input to the gate of the transistor  1210 . Thus, after supply of the power supply voltage to the memory element  1200  is restarted, the signal retained by the capacitor  1208  can be converted into the one corresponding to the state (the on state or the off state) of the transistor  1210  to be read from the circuit  1202 . Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor  1208  varies to some degree. 
     By applying the above-described memory element  1200  to a memory device such as a register or a cache memory included in a processor, data in the memory device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Furthermore, shortly after the supply of the power supply voltage is restarted, the memory device can be returned to the same state as that before the power supply is stopped. Thus, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor, resulting in lower power consumption. 
     Although the memory element  1200  is used in a CPU, the memory element  1200  can also be used in an LSI such as a digital signal processor (DSP), a custom LSI, or a programmable logic device (PLD), and a radio frequency (RF) device. 
     &lt;Display Device&gt; 
     A display device of one embodiment of the present invention is described below with reference to  FIGS. 43A to 43C  and  FIGS. 45A and 45B . 
     Examples of a display element provided in the display device include a liquid crystal element (also referred to as a liquid crystal display element) and a light-emitting element (also referred to as a light-emitting display element). The light-emitting element includes, in its category, an element whose luminance is controlled by a current or voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like. A display device including an EL element (EL display device) and a display device including a liquid crystal element (liquid crystal display device) are described below as examples of the display device. 
     Note that the display device described below includes in its category a panel in which a display element is sealed and a module in which an IC such as a controller is mounted on the panel. 
     The display device described below refers to an image display device or a light source (including a lighting device). The display device includes any of the following modules: a module provided with a connector such as an FPC or TCP; a module in which a printed wiring board is provided at the end of TCP; and a module in which an integrated circuit (IC) is mounted directly on a display element by a COG method. 
       FIGS. 43A to 43C  illustrate an example of an EL display device of one embodiment of the present invention.  FIG. 43A  is a circuit diagram of a pixel in an EL display device.  FIG. 43B  is a plan view showing the whole of the EL display device.  FIG. 43C  is a cross-sectional view taken along part of dashed-dotted line M-N in  FIG. 43B . 
       FIG. 43A  illustrates an example of a circuit diagram of a pixel used in an EL display device. 
     Note that in this specification and the like, it might be possible for those skilled in the art to constitute one embodiment of the invention even when portions to which all the terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected are not specified. In other words, one embodiment of the invention can be clear even when connection portions are not specified. Further, in the case where a connection portion is disclosed in this specification and the like, it can be determined that one embodiment of the invention in which a connection portion is not specified is disclosed in this specification and the like, in some cases. Particularly in the case where the number of portions to which a terminal is connected might be more than one, it is not necessary to specify the portions to which the terminal is connected. Therefore, it might be possible to constitute one embodiment of the invention by specifying only portions to which some of terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected. 
     Note that in this specification and the like, it might be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it might be possible for those skilled in the art to specify the invention when at least a function of a circuit is specified. In other words, when a function of a circuit is specified, one embodiment of the present invention can be clear. Further, it can be determined that one embodiment of the present invention whose function is specified is disclosed in this specification and the like. Therefore, when a connection portion of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a function is not specified, and one embodiment of the invention can be constituted. Alternatively, when a function of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a connection portion is not specified, and one embodiment of the invention can be constituted. 
     The EL display device illustrated in  FIG. 43A  includes a switching element  743 , a transistor  741 , a capacitor  742 , and a light-emitting element  719 . 
     Note that  FIG. 43A  and the like each illustrate an example of a circuit structure; therefore, a transistor can be provided additionally. In contrast, for each node in  FIG. 43A  and the like, it is possible not to provide an additional transistor, switch, passive element, or the like. 
     A gate of the transistor  741  is electrically connected to one terminal of the switching element  743  and one electrode of the capacitor  742 . A source of the transistor  741  is electrically connected to the other electrode of the capacitor  742  and one electrode of the light-emitting element  719 . A drain of the transistor  741  is supplied with a power supply potential VDD. The other terminal of the switching element  743  is electrically connected to a signal line  744 . A constant potential is supplied to the other electrode of the light-emitting element  719 . The constant potential is a ground potential GND or a potential lower than the ground potential GND. 
     It is preferable to use a transistor as the switching element  743 . When the transistor is used as the switching element, the area of a pixel can be reduced, so that the EL display device can have high resolution. As the switching element  743 , a transistor formed through the same step as the transistor  741  can be used, so that EL display devices can be manufactured with high productivity. Note that as the transistor  741  and/or the switching element  743 , any of the above-described transistors can be used, for example. 
       FIG. 43B  is a plan view of the EL display device. The EL display device includes a substrate  700 , a substrate  2750 , the insulator  422 , the insulator  428 , the insulator  409 , a sealant  734 , a driver circuit  735 , a driver circuit  736 , a pixel  737 , and an FPC  732 . The sealant  734  is provided between the substrate  700  and the substrate  2750  so as to surround the pixel  737 , the driver circuit  735 , and the driver circuit  736 . Note that the driver circuit  735  and/or the driver circuit  736  may be provided outside the sealant  734 . 
       FIG. 43C  is a cross-sectional view of the EL display device taken along part of dashed-dotted line M-N in  FIG. 43B . 
       FIG. 43C  illustrates a structure of the transistor  741  including a conductor  704   a  over the substrate  700 ; an insulator  712   a  over the conductor  704   a;  an insulator  712   b  over the insulator  712   a;  a semiconductor  706   a  and a semiconductor  706   b  which are over the insulator  712   b  and overlaps with the conductor  704   a;  a conductor  716   a  and a conductor  716   b  in contact with the semiconductor  706   a  and the semiconductor  706   b;  an insulator  718   a  over the semiconductor  706   b,  the conductor  716   a,  and the conductor  716   b;  an insulator  718   b  over the insulator  718   a;  an insulator  718   c  over the insulator  718   b;  and a conductor  714   a  that is over the insulator  718   c  and overlaps with the semiconductor  706   b.  Note that the structure of the transistor  741  is just an example; the transistor  741  may have a structure different from that illustrated in  FIG. 43C . 
     Thus, in the transistor  741  illustrated in  FIG. 43C , the conductor  704   a  serves as a gate electrode, the insulator  712   a  and the insulator  712   b  serve as a gate insulator, the conductor  716   a  serves as a source electrode, the conductor  716   b  serves as a drain electrode, the insulator  718   a,  the insulator  718   b,  and the insulator  718   c  serve as a gate insulator, and the conductor  714   a  serves as a gate electrode. Note that in some cases, electrical characteristics of the semiconductor  706  change if light enters the semiconductor. To prevent this, it is preferable that one or more of the conductor  704   a,  the conductor  716   a,  the conductor  716   b,  and the conductor  714   a  have a light-blocking property. 
     Note that the interface between the insulator  718   a  and the insulator  718   b  is indicated by a broken line. This means that the boundary between them is not clear in some cases. For example, in the case where the insulator  718   a  and the insulator  718   b  are formed using insulators of the same kind, the insulator  718   a  and the insulator  718   b  are not distinguished from each other in some cases depending on an observation method. 
       FIG. 43C  illustrates a structure of the capacitor  742  including a conductor  704   b  over the substrate; the insulator  712   a  over the conductor  704   b;  the insulator  712   b  over the insulator  712   a;  the conductor  716   a  that is over the insulator  712   b  and overlaps with the conductor  704   b;  the insulator  718   a  over the conductor  716   a;  the insulator  718   b  over the insulator  718   a;  the insulator  718   c  over the insulator  718   b;  and a conductor  714   b  that is over the insulator  718   c  and overlaps with the conductor  716   a.  In this structure, part of the insulator  718   a  and part of the insulator  718   b  are removed in a region where the conductor  716   a  and the conductor  714   b  overlap with each other. 
     In the capacitor  742 , each of the conductor  704   b  and the conductor  714   b  serves as one electrode, and the conductor  716   a  serves as the other electrode. 
     Thus, the capacitor  742  can be formed using a film of the transistor  741 . The conductor  704   a  and the conductor  704   b  are preferably conductors of the same kind, in which case the conductor  704   a  and the conductor  704   b  can be formed through the same step. Furthermore, the conductor  714   a  and the conductor  714   b  are preferably conductors of the same kind, in which case the conductor  714   a  and the conductor  714   b  can be formed through the same step. 
     The capacitor  742  illustrated in  FIG. 43C  has a large capacitance per area occupied by the capacitor. Therefore, the EL display device illustrated in  FIG. 43C  has high display quality. Note that although the capacitor  742  illustrated in  FIG. 43C  has the structure in which the part of the insulator  718   a  and the part of the insulator  718   b  are removed to reduce the thickness of the region where the conductor  716   a  and the conductor  714   b  overlap with each other, the structure of the capacitor according to one embodiment of the present invention is not limited to the structure. For example, a structure in which a part of the insulator  718   c  is removed to reduce the thickness of the region where the conductor  716   a  and the conductor  714   b  overlap with each other may be used. 
     An insulator  720  is provided over the transistor  741  and the capacitor  742 . Here, the insulator  720  may have an opening reaching the conductor  716   a  that serves as the source electrode of the transistor  741 . A conductor  781  is provided over the insulator  720 . The conductor  781  may be electrically connected to the transistor  741  through the opening in the insulator  720 . 
     A partition wall  784  having an opening reaching the conductor  781  is provided over the conductor  781 . A light-emitting layer  782  in contact with the conductor  781  through the opening provided in the partition wall  784  is provided over the partition wall  784 . A conductor  783  is provided over the light-emitting layer  782 . A region where the conductor  781 , the light-emitting layer  782 , and the conductor  783  overlap with one another serves as the light-emitting element  719 . 
     The insulator  422 , the insulator  428 , and the insulator  409  have barrier properties. This means that the display device illustrated in  FIGS. 43A to 43C  has a structure in which the transistor  741  is surrounded by insulators having barrier properties. Note that one or more of the insulator  422 , the insulator  428 , and the insulator  409  are not necessarily provided. 
     Note that a transistor, a capacitor, a wiring layer, and the like may be stacked to make the EL display device highly integrated. 
       FIG. 44  is a cross-sectional view illustrating a pixel of an EL display device fabricated over a semiconductor substrate. 
     The EL display device shown in  FIG. 44  includes a semiconductor substrate  801 , a substrate  802 , an insulator  803 , an insulator  804 , an insulator  805 , an adhesive layer  806 , a filter  807 , a filter  808 , a filter  809 , an insulator  811 , an insulator  812 , an insulator  813 , an insulator  814 , an insulator  815 , an insulator  816 , an insulator  817 , an insulator  818 , an insulator  819 , an insulator  820 , an insulator  821 , a conductor  831 , a conductor  832 , a conductor  833 , a conductor  834 , a conductor  835 , a conductor  836 , a conductor  837 , a conductor  838 , a conductor  839 , a conductor  840 , a conductor  841 , a conductor  842 , a conductor  843 , a conductor  844 , a conductor  845 , a conductor  846 , a conductor  847 , a conductor  848 , a conductor  849 , a conductor  850 , a conductor  851 , a conductor  852 , a conductor  853 , a conductor  854 , a conductor  855 , a conductor  856 , a conductor  857 , a conductor  858 , a conductor  859 , a conductor  860 , a conductor  861 , a conductor  862 , an insulator  871 , a conductor  872 , an insulator  873 , an insulator  874 , a region  875 , a region  876 , an insulator  877 , an insulator  878 , an insulator  881 , a conductor  882 , an insulator  883 , an insulator  884 , a region  885 , a region  886 , a layer  887 , a layer  888 , and a light-emitting layer  893 . 
     A transistor  891  includes the semiconductor substrate  801 , the insulator  871 , the conductor  872 , the insulator  873 , the insulator  874 , and the region  875  and the region  876 . The semiconductor substrate  801  serves as a channel formation region. The insulator  871  has a function of a gate insulator. The conductor  872  has a function of a gate electrode. The insulator  873  has a function of a sidewall insulator. The insulator  874  has a function of a sidewall insulator. The region  875  has a function of a source region and/or a drain region. The region  876  has a function of a source region and/or a drain region. 
     The conductor  872  includes a region overlapping with part of the semiconductor substrate  801  with the insulator  871  therebetween. The region  875  and the region  876  are regions where impurities are added to the semiconductor substrate  801 . In the case where the semiconductor substrate  801  is a silicon substrate, the region  875  and the region  876  may each be a region including a silicide, such as tungsten silicide, titanium silicide, cobalt silicide, or nickel silicide. The region  875  and the region  876  can be formed in a self-aligned manner using the conductor  872 , the insulator  873 , the insulator  874 , and the like, and the region  875  and the region  876  are accordingly located in the semiconductor substrate  801  such that a channel formation region is provided between the region  875  and the region  876 . 
     Since the transistor  891  includes the insulator  873 , the region  875  can be distanced from the channel formation region. Owing to the insulator  873 , the transistor  891  can be prevented from being broken or degraded by an electric field generated in the region  875 . Since the transistor  891  includes the insulator  874 , the region  876  can be distanced from the channel formation region. Owing to the insulator  874 , the transistor  891  can be prevented from being broken or degraded by an electric field generated in the region  876 . Note that in the transistor  891 , the distance between the region  876  and a channel formation region is longer than the distance between the region  875  and a channel formation region. This structure can enable both high on-state current and high reliability in the case where a potential difference between the region  876  and a channel formation region is likely to be larger than a potential difference between the region  875  and a channel formation region in operation of the transistor  891 . 
     A transistor  892  includes the semiconductor substrate  801 , the insulator  881 , the conductor  882 , the insulator  883 , the insulator  884 , the region  885 , and the region  886 . The semiconductor substrate  801  has a function of a channel formation region. The insulator  881  has a function of a gate insulator. The conductor  882  has a function of a gate electrode. The insulator  883  has a function of a sidewall insulator. The insulator  884  has a function of a sidewall insulator. The region  885  has a function of a source region and/or a drain region. The region  886  has a function of a source and/or a drain region. 
     The conductor  882  includes a region overlapping with part of the semiconductor substrate  801  with the insulator  881  therebetween. The region  885  and the region  886  are regions where impurities are added to the semiconductor substrate  801 . In the case where the semiconductor substrate  801  is a silicon substrate, the region  885  and the region  886  are a region including a silicide. The region  885  and the region  886  can be formed in a self-aligned manner using the conductor  882 , the insulator  883 , the insulator  884 , and the like, and the region  885  and the region  886  are accordingly located in the semiconductor substrate  801  such that a channel formation region is provided between the region  885  and the region  886 . 
     Since the transistor  892  includes the insulator  883 , the region  885  can be distanced from the channel formation region. Owing to the insulator  883 , the transistor  892  can be prevented from being broken or degraded by an electric field generated in the region  885 . Since the transistor  892  includes the insulator  884 , the region  886  can be distanced from the channel formation region. Owing to the insulator  884 , the transistor  892  can be prevented from being broken or degraded by an electric field generated in the region  886 . Note that in the transistor  892 , the distance between the region  886  and a channel formation region is longer than the distance between the region  885  and a channel formation region. This structure can enable both high on-state current and high reliability in the case where a potential difference between the region  886  and a channel formation region is likely to be larger than a potential difference between the region  885  and a channel formation region in operation of the transistor  892 . 
     The insulator  877  is located so as to cover the transistor  891  and the transistor  892  and has a function of a protective film for the transistor  891  and the transistor  892 . The insulator  803 , the insulator  804 , and the insulator  805  have a function of separating elements. For example, the transistor  891  and the transistor  892  are isolated from each other with the insulator  803  and the insulator  804  therebetween. 
     Each of the conductor  851 , the conductor  852 , the conductor  853 , the conductor  854 , the conductor  855 , the conductor  856 , the conductor  857 , the conductor  858 , the conductor  859 , the conductor  860 , the conductor  861 , and the conductor  862  has a function of electrically connecting elements, an element and a wiring, and wirings, and these conductors can be referred to as a wiring or a plug. 
     Each of the conductor  831 , the conductor  832 , the conductor  833 , the conductor  834 , the conductor  835 , the conductor  836 , the conductor  837 , the conductor  838 , the conductor  839 , the conductor  840 , the conductor  841 , the conductor  842 , the conductor  843 , the conductor  844 , the conductor  845 , the conductor  846 , the conductor  847 , the conductor  849 , and the conductor  850  has a function of a wiring, an electrode, and/or a light-blocking layer. 
     For example, the conductor  836  and the conductor  844  each have a function of an electrode of a capacitor including the insulator  817 ; the conductor  838  and the conductor  845  each have a function of an electrode of a capacitor including the insulator  818 ; the conductor  840  and the conductor  846  each have a function of an electrode of a capacitor including the insulator  819 ; and the conductor  842  and the conductor  847  each have a function of an electrode of a capacitor including the insulator  820 . Note that the conductor  836  and the conductor  838  may be electrically connected to each other. The conductor  844  and the conductor  845  may be electrically connected to each other. The conductor  840  and the conductor  842  may be electrically connected to each other. The conductor  846  and the conductor  847  may be electrically connected to each other. 
     Each of the insulator  811 , the insulator  812 , the insulator  813 , the insulator  814 , the insulator  815 , and the insulator  816  has a function of an interlayer insulator. The top surfaces of the insulator  811 , the insulator  812 , the insulator  813 , the insulator  814 , the insulator  815 , and the insulator  816  are preferably planarized. 
     The conductor  831 , the conductor  832 , the conductor  833 , and the conductor  834  are provided over the insulator  811 . The conductor  851  is provided in an opening in the insulator  811  and electrically connects the conductor  831  and the region  875 . The conductor  852  is provided in an opening in the insulator  811  and electrically connects the conductor  833  and the region  885 . The conductor  853  is provided in an opening in the insulator  811  and electrically connects the conductor  834  and the region  886 . 
     The conductor  835 , the conductor  836 , the conductor  837 , and the conductor  838  are provided over the insulator  812 . The insulator  817  is provided over the conductor  836 . The conductor  844  is provided over the insulator  817 . The insulator  818  is provided over the conductor  838 . The conductor  845  is provided over the insulator  818 . The conductor  854  is provided in an opening in the insulator  812 . The conductor  854  electrically connects the conductor  835  and the conductor  831 . The conductor  855  is provided in an opening in the insulator  812 . The conductor  855  electrically connects the conductor  837  and the conductor  833 . 
     The conductor  839 , the conductor  840 , the conductor  841 , and the conductor  842  are provided over the insulator  813 . The insulator  819  is provided over the conductor  840 . The conductor  846  is provided over the insulator  819 . The insulator  820  is provided over the conductor  842 . The conductor  847  is provided over the insulator  820 . The conductor  856  is provided in an opening in the insulator  813 . The conductor  856  electrically connects the conductor  839  and the conductor  835 . The conductor  857  is provided in an opening in the insulator  813 . The conductor  857  electrically connects the conductor  840  and the conductor  844 . The conductor  858  is provided in an opening in the insulator  813 . The conductor  858  electrically connects the conductor  841  and the conductor  837 . The conductor  859  is provided in an opening in the insulator  813 . The conductor  859  electrically connects the conductor  842  and the conductor  845 . 
     The conductor  843  is provided over the insulator  814 . The conductor  860  is provided in an opening in the insulator  814 . The conductor  860  electrically connects the conductor  843  and the conductor  846 . The conductor  860  electrically connects the conductor  843  and the conductor  847 . 
     The conductor  848  is provided over the insulator  815  and may be electrically floating. Note that the conductor  848  is not limited to a conductor as long as it has a function of a light-blocking layer: for example, the conductor  848  may be an insulator or a semiconductor having a light-blocking property. 
     The conductor  849  is provided over the insulator  816 . The insulator  821  is provided over the insulator  816  and the conductor  849 . The insulator  821  includes an opening exposing the conductor  849 . The light-emitting layer  893  is provided over the conductor  849  and the insulator  821 . The conductor  850  is provided over the light-emitting layer  893 . 
     The light-emitting layer  893  emits light by a potential difference between the conductor  849  and the conductor  850 ; thus, the conductor  849 , the conductor  850 , and the light-emitting layer  893  form a light-emitting element. Note that the insulator  821  has a function of a partition wall. 
     The insulator  878  is provided over the conductor  850 . The insulator  878  covers the light-emitting element and has a function of a protective insulator. The insulator  878  may have a barrier property or may form a structure in which the light-emitting element is surrounded by insulators having barrier properties, for example. 
     A substrate having a light-transmitting property can be used as the substrate  802 . For example, the substrate  2750  can be referred to for the substrate  802 . The layer  887  and the layer  888  are provided on the substrate  802 . The layer  887  and the layer  888  each have a function of a light-blocking layer. A resin, a metal, or the like can be used for the light-blocking layer. The layer  887  and the layer  888  can improve the contrast and reduce color bleeding in the EL display device. 
     Each of the filter  807 , the filter  808 , and the filter  809  has a function of a color filter. The filter  2054  can be referred to for the filter  807 , the filter  808 , and the filter  809 , for example. The filter  808  has a region overlapping with the layer  888 , the substrate  802 , and the layer  887 . The filter  807  has a region overlapping with the filter  808  on the layer  888 . The filter  809  has a region overlapping with the filter  808  on the layer  887 . The filter  807 , the filter  808 , and the filter  809  may have different thicknesses, in which case light might be extracted more efficiently from the light-emitting element. 
     An adhesive layer  806  is provided between the insulator  878  and the filter  807 , the filter  808 , and the filter  809 . 
     Because the EL display device in  FIG. 44  has a stacked-layer structure of the transistor, the capacitor, the wiring layer, and the like, the pixel area can be reduced. A highly integrated EL display device can be provided. 
     So far, examples of the EL display device are described. Next, an example of a liquid crystal display device is described. 
       FIG. 45A  is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device. A pixel shown in  FIGS. 45A and 45B  includes a transistor  751 , a capacitor  752 , and an element (liquid crystal element)  753  in which a space between a pair of electrodes is filled with a liquid crystal. 
     One of a source and a drain of the transistor  751  is electrically connected to a signal line  755 , and a gate of the transistor  751  is electrically connected to a scan line  754 . 
     One electrode of the capacitor  752  is electrically connected to the other of the source and the drain of the transistor  751 , and the other electrode of the capacitor  752  is electrically connected to a wiring for supplying a common potential. 
     One electrode of the liquid crystal element  753  is electrically connected to the other of the source and the drain of the transistor  751 , and the other electrode of the liquid crystal element  753  is electrically connected to a wiring to which a common potential is supplied. The common potential supplied to the wiring electrically connected to the other electrode of the capacitor  752  may be different from that supplied to the other electrode of the liquid crystal element  753 . 
     Note that the description of the liquid crystal display device is made on the assumption that the plan view of the liquid crystal display device is similar to that of the EL display device.  FIG. 45B  is a cross-sectional view of the liquid crystal display device taken along dashed-dotted line M-N in  FIG. 43B . In  FIG. 45B , the FPC  732  is connected to the wiring  733   a  via the terminal  731 . Note that the wiring  733   a  may be formed using the same kind of conductor as the conductor of the transistor  751  or using the same kind of semiconductor as the semiconductor of the transistor  751 . 
     For the transistor  751 , refer to the description of the transistor  741 . For the capacitor  752 , refer to the description of the capacitor  742 . Note that the structure of the capacitor  752  in  FIG. 45B  corresponds to, but is not limited to, the structure of the capacitor  742  in  FIG. 43C . 
     Note that in the case where an oxide semiconductor is used as the semiconductor of the transistor  751 , the off-state current of the transistor  751  can be extremely small. Therefore, an electric charge held in the capacitor  752  is unlikely to leak, so that the voltage applied to the liquid crystal element  753  can be maintained for a long time. Accordingly, the transistor  751  can be kept off during a period in which moving images with few motions or a still image are/is displayed, whereby power for the operation of the transistor  751  can be saved in that period; accordingly a liquid crystal display device with low power consumption can be provided. Furthermore, the area occupied by the capacitor  752  can be reduced; thus, a liquid crystal display device with a high aperture ratio or a high-resolution liquid crystal display device can be provided. 
     An insulator  721  is provided over the transistor  751  and the capacitor  752 . The insulator  721  has an opening reaching the transistor  751 . A conductor  791  is provided over the insulator  721 . The conductor  791  is electrically connected to the transistor  751  through the opening in the insulator  721 . 
     The insulator  422 , the insulator  428 , and the insulator  409  have barrier properties. This means that the display device illustrated in  FIGS. 45A and 45B  has a structure in which the transistor  751  is surrounded by insulators having barrier properties. Note that one or more of the insulator  422 , the insulator  428 , and the insulator  409  are not necessarily provided. 
     An insulator  792  serving as an alignment film is provided over the conductor  791 . A liquid crystal layer  793  is provided over the insulator  792 . An insulator  794  serving as an alignment film is provided over the liquid crystal layer  793 . A spacer  795  is provided over the insulator  794 . A conductor  796  is provided over the spacer  795  and the insulator  794 . A substrate  2797  is provided over the conductor  796 . 
     Owing to the above-described structure, a display device including a capacitor occupying a small area, a display device with high display quality, or a high-resolution display device can be provided. 
     For example, in this specification and the like, a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element can employ various modes or can include various elements. For example, the display element, the display device, the light-emitting element, or the light-emitting device includes at least one of an EL element; a light-emitting diode (LED) for white, red, green, blue, or the like; a transistor (a transistor that emits light depending on current); an electron emitter; a liquid crystal element; electronic ink; an electrophoretic element; a plasma display panel (PDP); a display element using micro electro mechanical systems (MEMS) such as a grating light valve (GLV), a digital micromirror device (DMD), a digital micro shutter (DMS), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, or a piezoelectric ceramic display; an electrowetting element; a display element including a carbon nanotube; and quantum dots. Other than the above, display media whose contrast, luminance, reflectivity, transmittance, or the like is changed by electrical or magnetic effect may be included. 
     Examples of display devices including having EL elements include an EL display. Examples of display devices having electron emitters are a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of display devices containing quantum dots in each pixel include a quantum dot display. The quantum dots are placed in a display element, in a backlight, or between the backlight and the display element. With the use of the quantum dots, a display device with high color purity can be fabricated. Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of a display device having electronic ink or an electrophoretic element include electronic paper. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes. Thus, the power consumption can be further reduced. 
     Note that in the case of using an LED chip, graphene or graphite may be provided under an electrode or a nitride semiconductor of the LED chip. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. As described above, provision of graphene or graphite enables easy formation of a nitride semiconductor thereover, such as an n-type GaN semiconductor including crystals. Furthermore, a p-type GaN semiconductor including crystals or the like can be provided thereover, and thus the LED chip can be formed. Note that an AlN layer may be provided between the n-type GaN semiconductor including crystals and graphene or graphite. The GaN semiconductors included in the LED chip may be formed by MOCVD. Note that when the graphene is provided, the GaN semiconductors included in the LED chip can also be formed by a sputtering method. 
     In a display device including MEMS, a dry agent may be provided in a space where a display element is sealed (or between an element substrate over which the display element is placed and a counter substrate opposed to the element substrate, for example). The dry agent can remove moisture and thus can prevent malfunction or degradation of the MEMS or the like. 
     &lt;Electronic Device&gt; 
     The semiconductor device of one embodiment of the present invention can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices which reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Other examples of electronic devices that can be equipped with the semiconductor device of one embodiment of the present invention are mobile phones, game machines including portable game consoles, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines.  FIGS. 46A to 46F  illustrate specific examples of these electronic devices. 
       FIG. 46A  illustrates a portable game console including a housing  901 , a housing  902 , a display portion  903 , a display portion  904 , a microphone  905 , a speaker  906 , an operation key  907 , a stylus  908 , and the like. Although the portable game console in  FIG. 46A  has the two display portions  903  and  904 , the number of display portions included in a portable game console is not limited to this. 
       FIG. 46B  illustrates a portable data terminal including a first housing  911 , a second housing  912 , a first display portion  913 , a second display portion  914 , a joint  915 , an operation key  916 , and the like. The first display portion  913  is provided in the first housing  911 , and the second display portion  914  is provided in the second housing  912 . The first housing  911  and the second housing  912  are connected to each other with the joint  915 , and the angle between the first housing  911  and the second housing  912  can be changed with the joint  915 . An image on the first display portion  913  may be switched in accordance with the angle at the joint  915  between the first housing  911  and the second housing  912 . A display device with a position input function may be used as at least one of the first display portion  913  and the second display portion  914 . Note that the position input function can be added by providing a touch panel in a display device. Alternatively, the position input function can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device. 
       FIG. 46C  illustrates a notebook personal computer, which includes a housing  921 , a display portion  922 , a keyboard  923 , a pointing device  924 , and the like. 
       FIG. 46D  illustrates an electric refrigerator-freezer, which includes a housing  931 , a refrigerator door  932 , a freezer door  933 , and the like. 
       FIG. 46E  illustrates a video camera, which includes a first housing  941 , a second housing  942 , a display portion  943 , operation keys  944 , a lens  945 , a joint  946 , and the like. The operation keys  944  and the lens  945  are provided for the first housing  941 , and the display portion  943  is provided for the second housing  942 . The first housing  941  and the second housing  942  are connected to each other with the joint  946 , and the angle between the first housing  941  and the second housing  942  can be changed with the joint  946 . Images displayed on the display portion  943  may be switched in accordance with the angle at the joint  946  between the first housing  941  and the second housing  942 . 
       FIG. 46F  illustrates a car including a car body  951 , a wheel  952 , a dashboard  953 , a light  954 , and the like. 
     REFERENCE NUMERALS 
       100 : target,  100   a:  target,  100   b:  target,  106   a:  film,  106   b:  film,  106   c:  film,  110   a:  backing plate,  110   b:  backing plate,  122   a:  target shield,  122   b:  target shield,  130   a:  magnet unit,  130   b:  magnet unit,  134   a:  member,  134   b:  member,  140 : plasma,  150   a:  target unit,  150   b:  target unit,  150   c:  target unit,  160 : substrate,  160   a:  substrate,  160   b:  substrate,  170 : substrate holder,  170   a:  substrate holder,  170   b:  substrate holder,  180 : heating mechanism,  180   a:  heating mechanism,  180   b:  heating mechanism,  190 : power source,  200 : pellet,  201 : ion,  202 : lateral growth portion,  203 : particle,  210 : backing plate,  220 : substrate,  230 : target,  250 : magnet,  310 : layer,  400 : substrate,  401 : insulator,  402 : insulator,  404 : conductor,  406   a:  insulator,  406   b:  semiconductor,  406   c:  insulator,  408 : insulator,  409 : insulator,  410 : insulator,  412 : insulator,  413 : conductor,  416   a:  conductor,  416   b:  conductor,  422 : insulator,  428 : insulator,  450 : semiconductor substrate,  452 : insulator,  454 : conductor,  456 : region,  460 : region,  462 : insulator,  464 : insulator,  466 : insulator,  468 : insulator,  472   a:  region,  472   b:  region,  474   a:  conductor,  474   b:  conductor,  474   c:  conductor,  476   a:  conductor,  476   b:  conductor,  478   a:  conductor,  478   b:  conductor,  478   c:  conductor,  480   a:  conductor,  480   b:  conductor,  480   c:  conductor,  490 : insulator,  492 : insulator,  494 : insulator,  496   a:  conductor,  496   b:  conductor,  496   c:  conductor,  496   d:  conductor,  498 : conductor,  498   a:  conductor,  498   b:  conductor,  498   c:  conductor,  498   d:  conductor,  500 : substrate,  502 : insulator,  503 : insulator,  504 : conductor,  506   a:  insulator,  506   b:  semiconductor,  506   c:  insulator,  508 : insulator,  512 : insulator,  513 : conductor,  514 : conductor,  516   a:  conductor,  516   b:  conductor,  600 : substrate,  602 : insulator,  602   a:  insulator,  602   b:  insulator,  602   c:  insulator,  603 : insulator,  604 : conductor,  606   a:  insulator,  606   b:  semiconductor,  606   c:  insulator,  607   a:  region,  607   b:  region,  608 : insulator,  612 : insulator,  613 : conductor,  616   a:  conductor,  616   b:  conductor,  618 : insulator,  620 : insulator,  700 : substrate,  704   a:  conductor,  704   b:  conductor,  706 : semiconductor,  706   a:  semiconductor,  706   b:  semiconductor,  712   a:  insulator,  712   b:  insulator,  714   a:  conductor,  714   b:  conductor,  716   a:  conductor,  716   b:  conductor,  718   a:  insulator,  718   b:  insulator,  718   c:  insulator,  719 : light-emitting element,  720 : insulator,  721 : insulator,  731 : terminal,  732 : FPC,  733   a:  wiring,  734 : sealant,  735 : driver circuit,  736 : driver circuit,  737 : pixel,  741 : transistor,  742 : capacitor,  743 : switching element,  744 : signal line,  751 : transistor,  752 : capacitor,  753 : liquid crystal element,  754 : scan line,  755 : signal line,  781 : conductor,  782 : light-emitting layer,  783 : conductor,  784 : partition,  791 : conductor,  792 : insulator,  793 : liquid crystal layer,  794 : insulator,  795 : spacer,  796 : conductor,  801 : semiconductor substrate,  802 : substrate,  803 : insulator,  804 : insulator,  805 : insulator,  806 : adhesive layer,  807 : filter,  808 : filter,  809 : filter,  811 : insulator,  812 : insulator,  813 : insulator,  814 : insulator,  815 : insulator,  816 : insulator,  817 : insulator,  818 : insulator,  819 : insulator,  820 : insulator,  821 : insulator,  831 : conductor,  832 : conductor,  833 : conductor,  834 : conductor,  835 : conductor,  836 : conductor,  837 : conductor,  838 : conductor,  839 : conductor,  840 : conductor,  841 : conductor,  842 : conductor,  843 : conductor,  844 : conductor,  845 : conductor,  846 : conductor,  847 : conductor,  848 : conductor,  849 : conductor,  850 : conductor,  851 : conductor,  852 : conductor,  853 : conductor,  854 : conductor,  855 : conductor,  856 : conductor,  857 : conductor,  858 : conductor,  859 : conductor,  860 : conductor,  861 : conductor,  862 : conductor,  871 : insulator,  872 : conductor,  873 : insulator,  874 : insulator,  875 : region,  876 : region,  877 : insulator,  878 : insulator,  881 : insulator,  882 : conductor,  883 : insulator,  884 : insulator,  885 : region,  886 : region,  887 : layer,  888 : layer,  891 : transistor,  892 : transistor,  893 : light-emitting layer,  901 : housing,  902 : housing,  903 : display portion,  904 : display portion,  905 : microphone,  906 : speaker,  907 : operation key,  908 : stylus,  911 : housing,  912 : housing,  913 : display portion,  914 : display portion,  915 : connection portion,  916 : operation key,  921 : housing,  922 : display portion,  923 : keyboard,  924 : pointing device,  931 : housing,  932 : refrigerator door,  933 : freezer door,  941 : housing,  942 : housing,  943 : display portion,  944 : operation key,  945 : lens,  946 : connection portion,  951 : car body,  952 : wheel,  953 : dashboard,  954 : light,  1189 : ROM interface,  1190 : substrate,  1191 : ALU,  1192 : ALU controller,  1193 : instruction decoder,  1194 : interrupt controller,  1195 : timing controller,  1196 : register,  1197 : register controller,  1198 : bus interface,  1199 : ROM,  1200 : memory element,  1201 : circuit,  1202 : circuit,  1203 : switch,  1204 : switch,  1206 : logic element,  1207 : capacitor,  1208 : capacitor,  1209 : transistor,  1210 : transistor,  1213 : transistor,  1214 : transistor,  1220 : circuit,  2000 : imaging device,  2001 : switch,  2002 : switch,  2003 : switch,  2010 : pixel portion,  2011 : pixel,  2012 : subpixel,  2012 B: subpixel,  2012 G: subpixel,  2012 R: subpixel,  2020 : photoelectric conversion element,  2030 : pixel circuit,  2031 : wiring,  2047 : wiring,  2048 : wiring,  2049 : wiring,  2050 : wiring,  2053 : wiring,  2054 : filter,  2054 B: filter,  2054 G: filter,  2054 R: filter,  2055 : lens,  2056 : light,  2057 : wiring,  2060 : peripheral circuit,  2070 : peripheral circuit,  2080 : peripheral circuit,  2090 : peripheral circuit,  2091 : light source,  2100 : transistor,  2200 : transistor,  2300 : silicon substrate,  2310 : layer,  2320 : layer,  2330 : layer,  2340 : layer,  2351 : transistor,  2352 : transistor,  2353 : transistor,  2354 : filter,  2355 : lens,  2360 : photodiode,  2361 : anode,  2363 : low-resistance region,  2370 : plug,  2371 : wiring,  2372 : wiring,  2373 : wiring,  2409 : insulator,  2418 : insulator,  2422 : insulator,  2700 : deposition apparatus,  2701 : atmosphere-side substrate supply chamber,  2702 : atmosphere-side substrate transfer chamber,  2703   a:  load lock chamber,  2703   b:  unload lock chamber,  2704 : transfer chamber,  2705 : substrate heating chamber,  2706   a:  deposition chamber,  2706   b:  deposition chamber,  2706   c:  deposition chamber,  2750 : substrate;  2751 : cryotrap,  2752 : stage,  2761 : cassette port,  2762 : alignment port,  2763 : transfer robot,  2764 : gate valve,  2765 : heating stage,  2766 : target unit,  2768 : substrate holder,  2769 : substrate,  2770 : vacuum pump,  2771 : cryopump,  2772 : turbo molecular pump,  2780 : mass flow controller,  2781 : refiner,  2782 : gas heating system,  2784 : adjustment member,  2791 : power source,  2797 : substrate,  3001 : wiring,  3002 : wiring,  3003 : wiring,  3004 : wiring,  3005 : wiring,  3200 : transistor,  3300 : transistor,  3400 : capacitor,  5100 : pellet,  5120 : substrate, and  5161 : region. 
     This application is based on Japanese Patent Application serial no. 2015-031795 filed with Japan Patent Office on Feb. 20, 2015 and Japanese Patent Application serial no. 2015-031803 filed with Japan Patent Office on Feb. 20, 2015, the entire contents of which are hereby incorporated by reference.