Patent Publication Number: US-2023137944-A1

Title: Semiconductor device

Description:
BACKGROUND OF THE INVENTION 
     Field 
     The present disclosure relates to a semiconductor device that generates a power supply voltage for a driving circuit that drives a switching device. 
     Background 
     In an inverter, a driving circuit that drives a switching device such as an IGBT is used. In a semiconductor device of relate art, a power supply voltage for an N-side driving circuit is generated by a transformer and a power supply voltage for a P-side driving circuit is generated by a bootstrap circuit (see, for example, Japanese Patent Laid-Open No. 2013-191989 (FIG. 1)). 
     SUMMARY 
     In the semiconductor device of the related art, since the transformer and the bootstrap diode are necessary, a mounting area on a substrate increases in size and cost increases. 
     The present disclosure has been made in order to solve the problems described above and an object of the present disclosure is to obtain a semiconductor device that can reduce the mounting area in size and reduce the cost. 
     A semiconductor device according to the present disclosure includes: a P-side driving circuit and an N-side driving circuit respectively driving a P-side switching device and an N-side switching device which are connected to configure a half bridge; and a N-side power supply generation circuit generating a power supply voltage for the N-side driving circuit from a power supply voltage for the P-side switching device. 
     In the present disclosure, the power supply generation circuit generates a power supply voltage for the N-side driving circuit from a power supply voltage for the P-side switching device. Accordingly, it is possible to generate the power supply voltage for the N-side driving circuit without using a transformer having a large area. Therefore, it is possible to reduce a mounting area and reduce cost. 
     Other and further objects, features and advantages of the invention will appear more fully from the following description. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a diagram illustrating a semiconductor device according to a first embodiment. 
         FIG.  2    is a diagram illustrating a configuration example of a power supply generation circuit. 
         FIG.  3    is a diagram illustrating a semiconductor device according to a second embodiment. 
         FIG.  4    is a diagram illustrating a semiconductor device according to a third embodiment. 
         FIG.  5    is a time chart of voltages of the units of the semiconductor device according to the third embodiment. 
         FIG.  6    is a diagram illustrating a semiconductor device according to a fourth embodiment. 
         FIG.  7    is a diagram illustrating a modification  1  of the semiconductor device according to the fourth embodiment. 
         FIG.  8    is a diagram illustrating a modification  2  of the semiconductor device according to the fourth embodiment. 
     
    
    
     Description of Embodiments 
     A semiconductor device according to the embodiments of the present disclosure will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted. 
     First Embodiment 
       FIG.  1    is a diagram illustrating a semiconductor device according to a first embodiment. The semiconductor device is a three-phase inverter. P-side switching devices S P1 , S P2 , and S P3  and N-side switching devices S N1 , S N2 , and S N3  are connected to configure a half bridge. That is, a collector of the P-side switching device S P1  is connected to a P terminal, an emitter of the P-side switching device S P1  and a collector of the N-side switching device S N1  are connected to each other, and an emitter of the N-side switching device S N1  is connected to the GND. The other switching devices are connected in the same manner. The P-side switching devices S P1 , S P2 , and Spa and the N-side switching devices S N1 , S N2 , and S N3  are IGBTs (Insulated Gate Bipolar Transistors) but may be other power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Note that “P side” means a high side of the half bridge and “N side” means a low side of the half bridge. 
     P-side driving circuits DC P1 , DC P2 , and DC P3  respectively drive the P-side switching devices S P1 , S P2 , and S P3 . N-side driving circuits DC N1 , DC N2 , and DC N3  respectively drive the N-side switching devices S N1 , S N2 , and S N3 . A memory control unit  1  sends control signals respectively to the P-side driving circuits DC P1 , DC P2 , and DC P3  and the N-side driving circuits DC N1 , DC N2 , and DC N3  via photocouplers  2 . A P voltage applied to a P terminal is power supply voltages for the P-side switching devices S P1 , S P2 , and S P3 . 
     Since a voltage higher than the P voltage is necessary for gate driving for the P-side switching devices S P1 , S P2 , and S P3 , power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3  cannot be generated from the P voltage. Therefore, a power supply IC  3  generates, with a transformer  4 , the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3 . The power supply voltage for the P-side driving circuit DC P1  is a voltage VB 1 -VS 1  based on an emitter voltage VS 1  of the P-side switching device S P1 . Similarly, the power supply voltage for the P-side driving circuit DCp 2  is a voltage VB 2 -VS 2 . The power supply voltage for the P-side driving circuit DC P3  is a voltage VB 3 -VS 3 . 
     N-side power supply generation circuits PG N1 , PG N2 , and PG N3  respectively generate power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3  from the P voltage without using a transformer. The N-side driving circuit DC N1  and the N-side power supply generation circuit PG N1  are integrated in an N-side gate driver GD N1  of the same chip or the same package. Similarly, the N-side driving circuit DCN 2  and the N-side power supply generation circuit PG N2  are integrated in an N-side gate driver GD N2 . The N-side driving circuit DC N3  and the N-side power supply generation circuit PG N3  are integrated in an N-side gate driver GD N3 . The N-side gate drivers GD N1 , GD N2 , and GD N3  are integrated circuits. Power supply generation circuits are not provided in the P-side gate drivers GD P1 , GD P2 , and GD P3 . The P-side driving circuits DC P1 , DC P2 , and DC P3  are respectively provided in the P-side gate drivers GD P1 , GD P2 , and GD P3 . 
     The P-side switching devices S P1 , S P2 , and S P3 , the N-side switching devices S N1 , S N2 , and S N3 , the P-side gate drivers GD P1 , GD P2 , and GD P3 , the N-side gate drivers GD N1 , GD N2 , and GD N3 , an MCU  1 , the power supply IC  3 , the transformer  4 , and the like are mounted on a substrate. 
       FIG.  2    is a diagram illustrating a configuration example of a power supply generation circuit. The power supply generation circuit corresponds to the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 . Resistors R 1  and R 2  are connected in series between a P terminal and a grounding point. A gate of a high withstand voltage NMOS  5  is connected to a connection point of the resistors R 1  and R 2 , a drain of the high withstand voltage NMOS  5  is connected to the P terminal, and a source of the high withstand voltage NMOS  5  is connected to a constant current circuit  6 . The constant current circuit  6  outputs an electric current to a Vcc terminal. The Vcc terminal is an output terminal of the power supply generation circuit. A Vcc monitor circuit  7  monitors a voltage value of the Vcc terminal and controls ON and OFF of the constant current circuit  6 . In order to reduce heat generation of a gate driver, the high withstand voltage NMOS  5  may be externally attached without being incorporated in the gate driver. 
     When the P voltage is applied, a volage is applied to the gate of the high withstand voltage NMOS  5  and the high withstand voltage NMOS  5  is turned on. Consequently, an electric current flows from the P terminal to the drain and the source of the high withstand voltage NMOS  5 . The electric current flows into the Vcc terminal via the constant current circuit  6 . When a voltage at the Vcc terminal rises to a desired voltage, the Vcc monitor circuit  7  turns off the constant current circuit  6 . Consequently, the voltage at the Vcc terminal is prevented from rising to exceed the desired voltage. When the voltage at the Vcc terminal drops, the Vcc monitor circuit  7  turns on the constant current circuit  6 . In this way, the N-side power supply generation circuits PG N1 , PG N2  and PG N3  generate the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3  from the P voltage using the constant current circuit  6  without using a transformer. 
     As explained above, in this embodiment, the N-side power supply generation circuits PG N1 , PG N2 , and PG N3  generate the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3  from the P voltage. Accordingly, it is possible to generate the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3  without using a transformer having a large area. As a result, it is possible to reduce the number of times of power supply generation by the transformer  4  from six to three. Therefore, it is possible to reduce a mounting area and reduce cost. The N-side driving circuits DC N1 , DC N2 , and DC N3  and the N-side power supply generation circuits PG N1 , PG N2 , and PG N3  can be respectively integrated into the same chips or the same packages. This is advantageous for a reduction in size. Note that the N-side power supply generation circuits PG N1 , PG N2 , and PG N3  in the P-side gate drivers GD P1 , GD P2 , and GD P3  can also generate a power supply voltage for the photocouplers  2  connected to the P-side gate drivers GD P1 , GD P2 , and GD P3 . 
     Second Embodiment 
       FIG.  3    is a diagram illustrating a semiconductor device according to a second embodiment. In the first embodiment, the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3  are generated by the transformer  4 . In contrast, in this embodiment, P-side power supply generation circuits PG P1 , PG P2 , and PG P3  are respectively provided in the P-side gate drivers GD P1 , GD P2 , and GD P3 . The P-side power supply generation circuits PG P1 , PG P2 , and PG P3  have the configuration illustrated in  FIG.  2   . The P-side power supply generation circuits PG P1 , PG P2 , and PG P3  respectively generate the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3  using the constant current circuit  6  without using a transformer. The P-side driving circuit DC P1  and the P-side power supply generation circuit PG P1  are integrated in the P-side gate driver GD P1  of the same chip or the same package. Similarly, the P-side driving circuit DCp 2  and the P-side power supply generation circuit PG P2  are integrated in the P-side gate driver GD P2 . The P-side driving circuit DC P3  and the P-side power supply generation circuit PG P3  are integrated in the P-side gate driver GD P3 . 
     For gate driving of the P-side switching devices S P1 , S P2 , and S P3 , the P-side driving circuits DC P1 , DC P2 , and DC P3  need a power supply voltage higher than the P voltage. Therefore, the power supply IC  3  generates, with the transformer  4 , a P′ voltage higher than the P voltage. The P-side power supply generation circuits PG P1 , PG P2 , and PG P3  respectively generate power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3  from the P′ voltage. Consequently, whereas the number of times of power supply generation by the transformer  4  is three in the first embodiment, in this embodiment, the number of times of power supply generation by the transformer  4  can be reduced to one. Accordingly, it is possible to further reduce the mounting area and reduce the cost than in the first embodiment. 
     Third Embodiment 
       FIG.  4    is a diagram illustrating a semiconductor device according to a third embodiment. In this embodiment, the P-side power supply generation circuits PG P1 , PG P2 , and PG P3  are respectively provided in the P-side gate drivers GD P1 , GD P2 , and GD P3 . The P-side power supply generation circuits PG P1 , PG P2 , and PG P3  generate power supply voltages for the P-side driving circuit DC P1 , DC P2 , and DC P3  from the P voltage. 
       FIG.  5    is a time chart of voltages of the units of the semiconductor device according to the third embodiment. P represents a voltage at the P terminal, Vcc 1  represents a power supply voltage for the N-side driving circuit DC N1 , LO 1  represents an output voltage of the N-side driving circuit DC N1 , VS 1  represents an emitter voltage of the P-side switching device S P1 , and VB 1 -VS 1  represents a power supply voltage for the P-side driving circuit DC P1 . 
     For example, in the case of P-GND=600V and VS 1 -GND=600V, when the VB 1 -VS 1 =15V is generated, VB 1 -GND=615V. Therefore, P&lt;VB 1  and the power supply voltage VB 1 -VS 1  for the P-side driving circuit DC P1  cannot be generated from the P voltage. 
     Therefore, in this embodiment, at an initial start time of the semiconductor device, after the N-side driving circuit DC N1  changes the output voltage LO 1  to high to turn on the N-side switching device S N1 , the P-side power supply generation circuit PG P1  generates the power supply voltage VB 1 -VS 1  for the P-side driving circuit DC P1 . 
     When the N-side switching device S N1  is turned on, VS 1 -GND=0V. Therefore, since VB 1 -GND=15V, P&gt;VB 1 . Accordingly, the P-side power supply generation circuit PG P1  can generate the power supply voltage VB 1 -VS 1  for the P-side driving circuit DC P1  from the P voltage. Power supply voltages VB 2 -VS 2  and VB 3 -VS 3  for the P-side driving circuits DC P2  and DC P3  are generated by the same method. 
     Consequently, since power supply generation by a transformer is unnecessary, it is possible to further reduce the mounting area and reduce the cost than in the first embodiment. Note that, if the power supply voltages VB 1 -VS 1 , VB 2 -VS 2 , and VB 3 -VS 3  for the P-side driving circuits DC P1 , DC P2 , and DC P3  can be generated at the initial start time, thereafter, it is possible to cause the P-side driving circuits DC P1 , DC P2 , and DC P3  to operate without hindering original ON and OFF operations of the switching devices. 
     Fourth Embodiment 
       FIG.  6    is a diagram illustrating a semiconductor device according to a fourth embodiment. As in the first embodiment, the N-side power supply generation circuits PG N1 , PG N2 , and PG N3  are respectively provided in the N-side gate drivers GD N1 , GD N2 , and GD N3  and respectively generate power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3  from the P voltage. Whereas the N-side power supply generation circuits PG N1 , PG N2 , and PG N3  generate, with the transformer  4 , the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3  in the first embodiment, in this embodiment, bootstrap circuits BS 1 , BS 2 , and BS 3  respectively boost output voltages of the N-side power supply generation circuits PG N1 , PG N2 , and PG N3  to generate power supply voltages for the P-side driving circuit DC P1 , DC P2 , and DC P3 . The bootstrap circuit BS 1  includes a bootstrap diode D 1  and a bootstrap capacitor C 1 . An anode of the bootstrap diode D 1  is connected to an output terminal of the N-side power supply generation circuit PGN 1  and a cathode of the bootstrap diode D 1  is connected to a power supply terminal of the P-side driving circuit DC P1 . One end of the bootstrap capacitor C 1  is connected to an emitter of the P-side switching device S P1  and the other end of the bootstrap capacitor C 1  is connected to a power supply terminal of the P-side driving circuit DC P1 . Similarly, the bootstrap circuit BS 2  includes a bootstrap diode D 2  and a bootstrap capacitor C 2 . The bootstrap circuit BS 3  includes a bootstrap diode D 3  and a bootstrap capacitor C 3 . 
     In this embodiment, the N-side power supply generation circuits PG N1 , PG N2 , and PG N3  generate the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3  from the P voltage. Therefore, a transformer for generating the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3  can be omitted. The bootstrap circuits BS 1 , BS 2 , and BS 3  respectively boost the output voltages of the N-side power supply generation circuits PG N1 , PG N2 , and PG N3  to generate the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3 . Therefore, the transformer  4  in the first embodiment can be omitted. A mounting area of the bootstrap circuits BS 1 , BS 2 , and BS 3  is smaller than a mounting area of the transformer  4 . Accordingly, it is possible to further reduce the mounting area and reduce the cost than in the first embodiment. 
       FIG.  7    is a diagram illustrating a modification  1  of the semiconductor device according to the fourth embodiment. The P-side driving circuit DC P1  and the N-side driving circuit DC N1  are formed on one chip to configure a gate driver GD 1 . When the P-side driving circuit DC P1  and the N-side driving circuit DC N1  are formed on different chips, low-voltage internal power supplies that generate IC internal voltages from a power supply, power supply voltage drop protection circuits that detect a voltage drop of the power supply and interrupt a gate driving operation, and the like are necessary in the driving circuits. In contrast, by forming the P-side driving circuit DC P1  and the N-side driving circuit DC N1  on the one chip, a low voltage internal power supply, a power supply voltage drop protection circuit, and the like can be shared. Total chip cost can be reduced. Similarly, the P-side driving circuit DC P2  and the N-side driving circuit DC N2  configure a gate driver GD 2 . The P-side driving circuit DC P3  and the N-side driving circuit DC N3  configure a gate driver GD 3 . The gate drivers GD 1 , GD 2 , and GD 3  are HVICs (High Voltage ICs). 
       FIG.  8    is a diagram illustrating a modification  2  of the semiconductor device according to the fourth embodiment. The bootstrap diodes D 1 , D 2 , and D 3  are respectively incorporated in the gate drivers GD 1 , GD 2 , and GD 3 . Consequently, it is possible to further reduce a substrate area. The P-side switching devices S P1 , S P2 , and S P3  and N-side switching devices S N1 , S N2 , and S N3  are not limited to devices formed of silicon, but instead may be formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon. The wide-bandgap semiconductor is, for example, a silicon carbide, a gallium-nitride-based material, or diamond. A semiconductor chip formed of such a wide-bandgap semiconductor has a high voltage resistance and a high allowable current density, and thus can be miniaturized. The use of such a miniaturized semiconductor chip enables the miniaturization and high integration of the semiconductor device in which the semiconductor chip is incorporated. Further, since the semiconductor chip has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor device. Further, since the semiconductor chip has a low power loss and a high efficiency, a highly efficient semiconductor device can be achieved. 
     Obviously many modifications and variations of the present disclosure are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. 
     The entire disclosure of Japanese Patent Application No. 2021-180384, filed on Nov. 4, 2021 including specification, claims, drawings and summary, on which the convention priority of the present application is based, is incorporated herein by reference in its entirety.