Patent Publication Number: US-6035355-A

Title: PCI system and adapter requirements following reset

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to computer systems, and more specifically to a method of configuring a computer system having peripheral devices, particularly adapter devices (such as graphics adapters or network adapters) which require configuration after a system reset, and which are interconnected to the system&#39;s processor using a peripheral (local) bus. 
     2. Description of Related Art 
     A typical structure for a conventional computer system includes one or more processing units connected to a system memory device (random access memory or RAM) and to various peripheral, or input/output (I/O), devices such as a display monitor, a keyboard, a graphical pointer (mouse), and a permanent storage device (hard disk). The system memory device is used by a processing unit in carrying out program instructions, and stores those instructions as well as data values that are fed to or generated by the programs. A processing unit communicates with the other components by various means, including one or more interconnects (buses), or direct memory-access channels. A computer system may have many additional components, such as serial and parallel ports for connection to, e.g., printers, and network adapters. Other components might further be used in conjunction with the foregoing; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access the system memory, etc. 
     Several different bus designs have been developed for interconnecting the various computer components. The original personal computer (PCs) introduced by International Business Machines Corp. (IBM--assignee of the present invention) used an &#34;expansion&#34; bus referred to as the XT bus, which allowed a user to add various optional devices, such as additional memory (RAM), sound cards, telephone modems, etc. This early design was improved upon by adding more data and address lines, new interrupt lines, and direct memory-access (DMA) control lines, to create the well-known AT bus, which is also referred to as the Industry Standard Architecture (ISA) bus. The AT design allowed the microprocessor to run at a faster speed than the expansion bus. A 32-bit extension to this bus was later created, which is referred to as the Extended Industry Standard Architecture (EISA). Another 32-bit expansion bus developed by IBM is the Microchannel Architecture (MCA) bus. 
     In addition to the foregoing designs, several other bus designs have been developed allowing the use of a system bus which interconnects the processor and the system memory device(s), along with a separate, local bus which interconnects the peripheral devices to the system bus (using a bus bridge). Two well-known standards are the Video Electronics Standards Association (VL) bus, and the Peripheral Component Interconnect (PCI) bus. 
     The PCI specification allows up to four PCI-compliant expansion cards to be installed in &#34;slots&#34; constructed along the PCI bus (up to 10 loads can be placed on the bus, but each device requires two loads as a connector for a slot constitutes a load, so four devices can be added at most (8 loads), since the bridge also counts as a load). A PCI local bus system uses a PCI controller, which must be installed in one of the PCI-compliant slots. An expansion bus controller for a system&#39;s ISA, EISA, or MCA slots can optionally be installed as well, providing increased synchronization for all of the system&#39;s bus-installed resources. A PCI controller exchanges data with the microprocessor either 32 bits or 64 bits at a time, depending on the implementation, and allows certain &#34;intelligent&#34; PCI-compliant adapters to perform tasks concurrently with the microprocessor, using a technique called bus mastering. The PCI specification also allows for multiplexing, a technique that permits more than one electrical signal to be present on the bus at one time. 
     A typical PCI system 10 is illustrated in FIG. 1. System 10 includes a central processing unit (CPU) 12, firmware or read-only memory (ROM) 14, and a dynamic random access memory (DRAM) 16 which are all connected to a system bus 18. CPU 12, ROM 14 and DRAM 16 are also coupled to a PCI local bus 20 using a PCI host bridge 22. PCI host bridge 22 provides a low latency path through which processor 12 may access PCI devices mapped anywhere within bus memory or I/O address spaces. PCI host bridge 22 also provides a high bandwidth path to allow the PCI devices to access DRAM 16. 
     Attached to PCI local bus 20 are a local area network (LAN) adapter 24, a small computer system interface (SCSI) adapter 26, an expansion bus bridge 28, an audio adapter 30, and a graphics adapter 32. Lan adapter 24 is used to connect computer system 10 to an external computer network 34. SCSI adapter 26 is used to control high-speed SCSI disk drive 36. Expansion bus bridge 28 is used to couple an ISA expansion bus 38 to PCI local bus 20. As shown, several user input devices are connected to ISA bus 38, including a keyboard 40, a microphone 42, and a graphical pointing device (mouse) 44. Other devices may also be attached to ISA bus 38, such as a CD-ROM drive 46. Audio adapter 30 controls audio output to a speaker 48, and graphics adapter 32 controls visual output to a display monitor 50. 
     In earlier computer systems, all of the peripheral components had to be connected (inserted in the PCI or ISA slots) at the time that the computer was first turned on, in order to properly register (initialize) the devices with the computer&#39;s operating system. These devices are checked during the system&#39;s power-on self test (POST), which includes a set of routines stored in ROM 14 (also referred to as read-only storage, or ROS) that test the peripherals to see if they are properly connected and operating. If problems with any of the devices are detected, these routines alert the user by sounding a series of beeps or displaying a message, often accompanied by a diagnostic numeric value, to the standard output device or standard error device (usually the display screen). 
     In the earlier systems, if a device were simply not present during the POST, then it would not be recognized when it was later inserted in a slot (while the computer was still running). Instead, those systems were required to be &#34;rebooted&#34; in order to be able to communicate with and utilize the later-added devices. &#34;Rebooting&#34; refers to the restarting of a computer system by reloading its most basic program instructions, viz., the operating system. A system can be rebooted using the software itself (a warm boot) or by actuating the system&#39;s hardware, i.e., the reset or power buttons (a cold boot). After rebooting, the new device can be identified using various techniques. See, e.g., U.S. Pat. No. 5,594,873. 
     More recent computer systems have the ability to recognize devices which are added to a bus while the computer is operating, that is, without having to reboot the system. One example is the &#34;plug and play&#34; specification, which allows a PC to configure itself automatically to work with peripherals. A user can &#34;plug&#34; in a peripheral and &#34;play&#34; it without manually configuring the system. Plug and play operation requires both ROM that supports the specification, and a special expansion card. While this approach allows the system to recognize a newly added device, it is still often necessary to reset the system in order to properly initialize the device with the operating system. A further improvement in this area is the &#34;hot-plug&#34; specification, wherein separate reset lines are provided for each peripheral device, such that a device can be initialized with the operating system without requiring the entire system to be rebooted (this ability of the device/system is referred to as &#34;hot-pluggable&#34;). 
     One problem that persists in the initialization of peripheral devices is that, following a deactivation of the reset signal (RST#), there may be a long time before an adapter is prepared to respond to configuration cycles with even a RETRY response (which is used to indicate that the adapter is functioning, but it is currently too busy to respond to the initialization). As a result, following deactivation of RST#, a system may consider an adapter as not present or defective if it does not respond. If the device responds to configuration or regular (non-configuration) cycles with RETRY, the PCI bus and/or the system processor can stall, resulting in the requirement to reboot the system. 
     Previously, this problem has not been significant, but now there are a number of situations that may result in an adapter card and/or a group of adapters being reset while the processor and the rest of the I/O subsystem remains operational. One factor that contributes to this problem is the increased complexity of adapters, such as an adapter that must initialize a programmable logic array (PLA) following RST# deactivation before it can handle a configuration cycle or even respond with RETRY, or an adapter with an on-board processor that must load registers and complete other initialization steps before it can handle a configuration cycle or even respond with RETRY. Another factor is the provision of separate reset lines to the adapters, such as is provided in the hot-plug specification and similar PCI power management specifications, or in diagnostic analysis of an individual card while the rest of the system and PCI I/O subsystem remains operational. 
     In light of the foregoing, it would be desirable to devise a method of avoiding rebooting requirements associated with delayed initialization responses from peripheral devices. It would be further advantageous if, following configuration completion, the adapter were prepared to respond to normal (non-configuration) cycles without a RETRY response. 
     SUMMARY OF THE INVENTION 
     It is therefore one object of the present invention to provide an improved computer system having an expansion bus which allows the addition of peripheral devices to the system. 
     It is another object of the present invention to provide such a computer system wherein a reset signal can be applied to a peripheral device to allow initialization of the device with the computer&#39;s operating system, without requiring the entire system to be rebooted. 
     It is yet another object of the present invention to provide such a computer system which reduces delays in initialization responses from peripheral devices, to avoid initialization failures. 
     The foregoing objects are achieved in a method of registering a peripheral device with a computer, generally comprising the steps of isolating a slot from a bus of the computer, inserting the peripheral device into the slot, connecting the slot to the bus, deasserting a reset signal on the slot, responding with a status message from the peripheral device to the bus in response to an access attempt within a predetermined time period established by the computer, and initializing the peripheral device with an operating system of the computer in response to the responding step. If the status message is a retry response, the responding step occurs during an initial latency period which is less than the predetermined time period. The invention can also enable the peripheral device to respond to non-configuration cycles immediately following configuration completion. Internal logic of the peripheral device can be initialized after the responding step; in other words, part of the internal initialization can be moved to other operations, such as a diagnostic operation. 
     The invention also contemplates the use of device driver to peripheral device communications via the configuration space of the peripheral device, to prevent non-configuration access to the peripheral device until the peripheral device is ready to respond to such non-configuration access. This feature may be implemented by setting a bit (in the configuration space of the peripheral device. 
     The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a block diagram of a conventional computer system having a Peripheral Component Interconnect (PCI) bus which allows peripheral devices to be added to the computer system; and 
     FIG. 2 is a block diagram of one embodiment of a computer system constructed in accordance with the present invention, having a PCI bus with a plurality of slots for receiving peripheral devices, and a &#34;hot-plug&#34; controller used to initialize the devices while the remainder of the system is still running. 
    
    
     DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT 
     With reference now to the figures, and in particular with reference to FIG. 2, there is depicted one embodiment of a computer system 100 constructed in accordance with the present invention. System 100 includes a CPU or processor 102 connected to a system memory device 104 using a system bus 106. A Peripheral Component Interconnect (PCI) host bridge 108 is used to couple a PCI local bus 110 to system bus 106. Various peripheral devices may be removably connected to the system using a plurality of slots, three of which 112, 114 and 116 are shown. Each slot is connected to PCI bus 110 using respective hot-plug switches 118, 120 and 122, which can be used to isolate all the signals on a slot from bus 110 while the rest of the platform is running. Switches 118, 120 and 122 also remove all power from a slot while the remainder of the platform is still fully powered. A hot-plug controller 124 is also connected to PCI host bridge 108 and each of the hot-plug switches 118, 120 and 122. 
     In the depicted embodiment, computer system 100 is compliant with the hot-pluggable design set forth in the document &#34;PCI Hot-Plug Specification,&#34; revision 1.0, published by Intel Corp. (Oct. 6, 1997), which is hereby incorporated. As such, slots 112, 114 and 116 are designed for adapter cards that are 32-bits or 64-bits wide, operate at 33 MHz or 66 MHz, and use 3.3 volt or 5 volt signaling (the adapter cards have novel constructions as described further below). An adapter card could contain a single PCI device or multiple devices behind a PCI-to-PCI bridge. Each slot has a logical slot identifier that uniquely identifies a particular slot. 
     Hot-plug controller 124 controls the electrical aspects of powering up and down a PCI slot. More than one hot-plug controller can be used. A software driver (hot-plug system driver) is used to control and monitor hot-plug controller 124. If there is more than one hot-plug controller, then more than one hot-plug system driver can be used. Higher-level software (a hot-plug &#34;service&#34;) has overall control of the hot-plug operations. This service includes a user interface, and can issue requests to the operating system to quiesce adapter activity, and further issue requests (primitives) to the hot-plug system driver to turn the slots on or off, using switches 118, 120 and 122. 
     An adapter placed in one of the slots 112, 114 and 116 can be initialized with the operating system of computer system 100 without requiring rebooting of the entire system. A slot is powered down and isolated from PCI bus 110 prior to inserting an adapter card, using hot-plug controller 124. After inserting the card, the user notifies the hot-plug service, which turns on the slot containing the new adapter, by issuing a primitive to the hot-plug system driver. The hot-plug system driver then uses hot-plug controller 124 to power up the slot, connect the slot to PCI bus 110 using the appropriate hot-plug switch (slot-specific reset pins are independently controlled), and deassert the reset signal (RST#) on the slot. The hot-plug service thereafter notifies the operating system that the new adapter card is installed, so the operating system can initialize the adapter and prepare to use it (the user may also be notified that the card is ready with a message on the display monitor). 
     The present invention avoids the problem noted in the Background, of an adapter excessively delaying its response to the deactivation of the reset signal such that a reboot is required. A predetermined time (T x ) is established for the period of time from deactivation of RST# to the first configuration access attempted by processor 102, to allow an adapter&#39;s internal bus logic to be initialized (for example, one or two seconds). In order to reduce the likelihood that system 100 will consider the adapter as being not present or defective, the card is designed to handle configuration accesses, normally without RETRY responses, after this time period T x  has passed. In other words, the card conforms to the specification of being able to respond with a non-retry status message (or acknowledgement) within this time period. An occasional RETRY response is acceptable, provided it adheres to initial latency requirements of, e.g., 16 clock cycles. The adapter hardware and/or software are implemented to meet T x . An adapter constructed in accordance with the present invention is further preferably capable of responding to normal (non-configuration) cycles following configuration completion, i.e., immediately following the configuration space setup and the enablement of the adapter&#39;s address spaces (again normally without a RETRY response, and with any such response adhering to the initial latency requirements). 
     For more complicated adapter cards which may require lengthy internal initialization, one solution for complying with the T x  requirement is to move the functions that would cause long internal initialization times out of the initialization routine, and into to another operation, such as a built-in self-test (BIST) operation. Those functions can thereby be initiated during a later &#34;diagnostic&#34; operation via the BIST rather than as part of the initialization operation (that is, immediately following a reset). 
     For those very complex peripheral devices which still might not otherwise respond to normal cycles with something other than a long series of RETRY responses or wait states, an alternate solution is to implement an adapter driver which prevents normal (non-configuration) access to the adapter until the adapter is prepared to respond to the accesses. A bit in the adapter configuration space may be defined to allow configuration software or a device driver to check this bit to determine if the adapter (by setting that bit) has indicated that it is ready to respond to normal cycles. 
     Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. For example, the invention is applicable to similar reset responses, such as those generated by PCI power management services. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the present invention as defined in the appended claims.