Patent Publication Number: US-8526896-B2

Title: Feedback compensation detector for a direct conversion transmitter

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a continuation of U.S. application Ser. No. 12/785,607, filed May 24, 2010, which is a continuation of U.S. application Ser. No. 12/494,835, filed Jun. 30, 2009 (now U.S. Pat. No. 7,725,087), which is a continuation of U.S. application Ser. No. 11/274,581, filed Nov. 15, 2005, which is a continuation of U.S. application Ser. No. 10/145,930, filed May 15, 2002 (now U.S. Pat. No. 6,987,954), which claims priority from U.S. Provisional Application No. 60/291,239, filed May 15, 2001, all the above applications hereby incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     This application relates generally to the field of radio frequency (RF) signal transmission. More specifically, a feedback compensation detector for a direct conversion transmitter is provided that is particularly well-suited for use in a Quadrature Amplitude Modulated (QAM) transmitter, but may also provide utility in any transmitter that uses sufficiently independent modulation on the two quadrature axes (I and Q), such as a Code Division Multiple Access (CDMA) transmitter, a Wideband Direct Sequence CDMA (WCDMA) transmitter, or a Global System for Mobile Communications (GSM) transmitter. 
     BACKGROUND OF THE INVENTION 
     Direct conversion transmitters are known. In a typical direct conversion transmitter chain, baseband in-phase (I) and quadrature-phase (Q) digital signals are converted to analog signals, filtered, amplified and modulated to form an analog baseband signal. The analog baseband signal is then converted to a radio frequency (RF) signal at a carrier frequency, amplified, filtered, and transmitted via an antenna. Such transmitter chains, however, typically propagate signal impairments which are often resultant from channel delays, imbalances, and other signal distortions occurring within the transmitter chain. 
     SUMMARY 
     A feedback compensation detector for a direct conversion transmitter includes a baseband processor, a direct up-converter, an antenna, and an impairment detection and compensation feedback circuit. The baseband processor generates an in-phase (I) baseband signal and a quadrature-phase (Q) baseband signal. The direct up-converter is coupled to the baseband processor, and combines the I and Q baseband signals with an RF carrier signal to generate an RF output signal. The antenna is coupled to the direct up-converter, and transmits the RF output signal. The impairment detection and compensation feedback circuit is coupled to the RF output signal and the I and Q baseband signals. The impairment detection and compensation feedback circuit down-converts the RF output signal to generate an intermediate frequency (IF) signal, measures as least one signal impairment in the IF signal, and pre-distorts the I and Q baseband signals to compensate for the measured signal impairment. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a direct up-conversion transmitter chain with an impairment compensation feedback path; 
         FIG. 2  is a more detailed block diagram of the direct up-converter shown in  FIG. 1 ; 
         FIG. 3  is a block diagram of the direct up-conversion transmitter chain shown in  FIG. 1  with a more detailed illustration of the impairment detector; 
         FIG. 4  is a more detailed block diagram of the impairment compensator shown in  FIG. 1 ; 
         FIG. 5  is a block diagram of a timing estimator circuit for estimating the in-phase (I) component delay, T ie , shown in  FIG. 4 ; 
         FIG. 6  is a block diagram of a direct up-conversion transmitter chain having an automatic gain control (AGC) correction loop in the impairment compensation feedback path; 
         FIG. 7  is a block diagram of a direct up-conversion transmitter chain having a local oscillator (LO) leakage nulling loop in the impairment compensation feedback path; 
         FIG. 8  is a block diagram of a direct up-conversion transmitter chain having a quadrature imbalance compensation loop in the impairment compensation feedback path; 
         FIG. 9  is a block diagram of a direct up-conversion transmitter chain having a differential timing error compensation loop in the impairment compensation feedback path; 
         FIG. 10  is a block diagram of an exemplary temperature and supply voltage compensation circuit for the impairment detector shown in  FIGS. 1 ,  3 , and  6 - 9 ; 
         FIG. 11  is a flow diagram of a method for iteratively estimating the values of the ambient temperature T and battery supply voltage V d  shown in  FIG. 10 ; and 
         FIG. 12  is a flow diagram illustrating an exemplary method for operating the feedback compensation detector described above with reference to  FIGS. 1-9 . 
     
    
    
     DETAILED DESCRIPTION 
     Impairment Compensation Feedback Path 
     Referring now to the drawing figures,  FIG. 1  is a block diagram of a direct up-conversion transmitter chain  100  with an impairment compensation feedback path. The transmitter chain  100  includes a baseband processor  110 , an impairment compensator  112 , a direct up-converter  114 , and an impairment detector  116 . The baseband processor  110  may, for example, be a digital signal processor (DSP), a central processing unit (CPU), or some other type of processing device or logic circuitry. The transmitter chain also includes a pair of digital-to-analog converters DACs  118 , a frequency synthesizer  120 , a band pass filter  122 , and an antenna  124 . Operationally, the impairment detector  116  measures signal impairments in the direct up-converter output  121 , and generates a feedback signal  126  that is coupled to the impairment compensator  112 . Exemplary signal impairments which may be detected by the impairment detector  116  are described below with reference to  FIG. 3 . 
     The baseband processor  110  generates in-phase (I) and quadrature-phase (Q) digital baseband signals for RF transmission. The I and Q baseband signals are modified prior to analog conversion by the impairment compensator  112 , as described below. The modified baseband signals are then converted into the analog domain by the DACs  118  and are coupled to the direct up-converter  114  which combines the analog baseband signals with an RF carrier signal  119  from the frequency synthesizer  120 . An exemplary direct up-converter  114  is described below with reference to  FIG. 2 . The RF output signal  121  from the direct up-converter  114  is filtered by the band pass filter  122 , and is transmitted by the antenna  124 . In addition, the RF output signal  121  is coupled to the impairment detector  116  which measures signal impairments, as described below, and generates the feedback signal  126  that is coupled to the impairment compensator  112 . The feedback signal  126  is used by the impairment compensator  112  to pre-distort the I and Q baseband signals such that the pre-distortion cancels any actual distortion caused by impairments in the direct up-converter  114 . 
       FIG. 2  is a more detailed block diagram  200  of the direct up-converter  114  shown in  FIG. 1 . The direct up-converter  114  includes a pair of low pass filters  202 , a pair of amplifiers  204 , a quadrature up-converter  206 , an automatic gain control (AGC) amplifier  208 , a band pass filter  210 , and a power amplifier (PA)  212 . 
     The analog I and Q baseband signals from the DACs  118  are received as inputs to the direct up-converter  114 . The I and Q inputs are then filtered by the pair of low pass filters  202 , amplified by the pair of amplifiers  204 , and coupled as inputs to the quadrature up-converter  206 . The quadrature up-converter  206  also receives a carrier signal (F 1 ) from the frequency synthesizer  120 , and combines the analog baseband signals with the carrier signal (F 1 ) to generate a radio frequency (RF) signal having a carrier frequency of F 1 . The RF signal is amplified by the AGC amplifier  208  in order to provide the necessary gain to drive the power amplifier (PA)  212 . The PA  212  further amplifies the RF signal to generate the RF output signal  121 . 
       FIG. 3  is a block diagram  300  of the direct up-conversion transmitter chain  100  shown in  FIG. 1  with a more detailed illustration of the impairment detector  116 . The impairment detector  116  includes a variable attenuator  302 , a down-conversion mixer  304 , a band pass filter  306 , an analog-to-digital (A/D) converter  308 , and a impairment detector processor  310 . The impairment detector processor  310  may, for example, be a digital signal processor (DSP), a central processing unit (CPU), or some other type of processing device or logic circuitry. In one embodiment, the processing functions of the impairment detector processor  310  and the baseband processor  110  described above may be performed by the same processing device. 
     The RF output signal  121  from the direct up-converter  114  is sampled by the variable attenuator  302  which reduces the gain of the signal  121  to an appropriate power range for the down-conversion mixer  304 . The output from the variable attenuator  302  is coupled to the down-conversion mixer  304  along with a local oscillator (LO) signal  303  generated by the frequency synthesizer  120 , which has a different frequency (F 2 ) than the frequency (F 1 ) of the RF carrier signal  119 . The intermediate frequency (IF) output of the down-conversion mixer  304  thus has a center frequency that is substantially equal to the difference between the frequencies of the LO signal  303  and the RF carrier signal  119  (F 1 -F 2 ). 
     The band pass filter  306  is centered at the intermediate frequency (F 1 -F 2 ), and filters the IF output to a pre-determined passband to generate an analog impairment signal z(t), where z is a time domain function and t is time. The analog impairment signal z(t) is sampled by the A/D converter  308 , and the resulting digital signal is coupled to the impairment detector processor  310  and may also be stored in a memory device, such as a buffer memory, via the processor  310 . 
     The impairment detector processor  310  is configured to estimate one or more impairments present in the RF signal  121 . For instance, the impairment detector processor  310  may be configured to estimate the overall gain of the up-converter chain  100 , a leakage component from the LO signal  303 , a phase or amplitude imbalance in the quadrature up-converter  206 , a differential delay between the I and Q baseband channels, or some other signal impairment. The feedback signal  126  from the impairment detector  116  is generated by the impairment detector processor  310  based on the impairments detected in the RF signal  121  and is applied to the I and Q baseband signals in the impairment compensator  112 . In addition, the impairment detector processor  310  generates an attenuation control signal  312  that is fed back to control the negative gain applied by the variable attenuator  302 . The relationship between the operations of the impairment detector  116  and the impairment compensator  112 , including the estimation of signal impairments by the impairment detector processor  310 , is described below with reference to  FIGS. 5-9 . 
       FIG. 4  is a more detailed block diagram  400  of the impairment compensator  112  shown in  FIG. 1 . The impairment compensator  112  includes in-phase and quadrature-phase delay compensation blocks  402 ,  404 , in-phase and quadrature-phase bias compensation adders  406 ,  408 , a linear compensation block  410 , and in-phase and quadrature-phase gain multipliers  412 ,  414 . Also illustrated are the in-phase (I) and quadrature-phase (Q) digital baseband signals from the baseband processor  110 , denoted in the time domain as g i (t) and g q (t) respectively. 
     The in-phase and quadrature-phase baseband signals g i (t) and g q (t) are advanced by estimated I and Q component delay values, T ie  and T qe , in the delay compensation blocks  402 ,  404 . The estimated I and Q component delay values T ie  and T qe  compensate for 1 and Q component delays from the transmitter chain  100 , and are received as inputs from the impairment detector  116 . An exemplary method for estimating the I and Q component delay values, T ie  and T qe , is described below with reference to  FIG. 5 . 
     The in-phase and quadrature-phase outputs from the delay compensation blocks  402 ,  404  are coupled as positive inputs to the in-phase and quadrature-phase bias compensation adders  406 ,  408 . In addition, estimated in-phase and quadrature-phase bias offset values, b ie  and b qe , derived by the impairment detector  116 , are coupled as negative inputs to the in-phase and quadrature-phase bias compensation adders  406 ,  408 . The bias offset values, b ie  and b qe , compensate for direct-current (DC) bias caused, for example, by leakage of the LO signal  303  in the RF output signal  121  (see  FIG. 3 ). An exemplary method for estimating the bias offset values, b ie  and b qe , is described below. 
     The in-phase and quadrature-phase outputs from the bias compensation adders  406 ,  408  are coupled as inputs to the linear compensation block  410  along with estimated phase and amplitude imbalance parameters, e e  and f e , calculated by the impairment detector  116 . Using the estimated phase and amplitude imbalance parameters, e e  and f e , the linear compensation block  410  applies an inverse model of the phase and amplitude imbalance in the quadrature up-converter  206 , and outputs balanced in-phase and quadrature-phase signal components. An exemplary method for estimating the phase and amplitude imbalance parameters, e e  and f e , is described below. 
     The balanced outputs from the linear compensation block  410  are coupled as inputs to the in-phase and quadrature-phase gain multipliers  412 ,  414 . Also coupled as inputs to the gain multipliers  412 ,  414  is a scaling factor, G des /G oe , which adjusts the in-phase and quadrature-phase signals to compensate for gain imbalances. The numerator of the scaling factor, G des , represents the desired gain for the transmitter chain  100 , and the denominator, G oe , is the estimated actual gain. The desired gain G des  is pre-selected according to the desired characteristics of the transmitter chain  100 . The estimated actual gain G oe  may be calculated by the impairment detector  116 , as described below. The in-phase and quadrature-phase outputs from the gain multipliers  412 ,  414  are coupled to the DACs  118 , as described above with reference to  FIG. 1 . 
     In one alternative embodiment, the impairment detector  112  may be implemented as a software application executing on the baseband processor  110  or on some other processing device. 
     Estimating I and Q Component Delays (T ie  and T qe ) 
       FIG. 5  is a block diagram  500  of a timing estimator circuit for estimating the I component delay, T ie , shown in  FIG. 4 . The timing estimator circuit  500  may, for example, be implemented by the impairment detector processor  310 , and includes a first mixer  502 , a second mixer  504 , and an integrator  506 . 
     The analog impairment signal z(t), described above with reference to  FIG. 3 , is coupled as an input to the first mixer  502  along with a delayed in-phase baseband signal g i (t−T ie )  508 . The delayed in-phase baseband signal g i (t−T ie )  508  is delayed by an estimated value for the I component delay T ie . The output from the first mixer  504  is then coupled as an input to the second mixer  504  along with a sampling phase adjustment parameter  510 . The sampling phase adjustment parameter  510  may be calculated as: cos(2π(F 1 −F 2 )t+p); where (F 1 −F 2 ) is the frequency of the IF output from the down-conversion mixer  304  shown in  FIG. 3 , and p is a phase parameter. The output from the second mixer  504  is fed into the integrator  506 , which integrates the signal over a sampling epoch (M/(F 1 −F 2 )) to produce an output signal (Y)  512 , where M is an integer parameter corresponding to the number of integration cycles. 
     Operationally, the estimated I component delay, T ie , is calculated by varying the values of T ie  and p until a maximum value is obtained for the timing estimator output (Y)  512 . The maximum value for Y may be approximated, for example, by calculating Y  512  over a pre-determined range of the variables T ie  and p. The value of T ie  that results in the maximum timing estimator output (Y)  512  is an estimate of the total in-phase component delay. 
     The estimated Q component delay, T iq , may be calculated using a timing estimator circuit similar to the circuit  500  shown in  FIG. 5  in which the delayed in-phase baseband signal (g i (t−T ie )) is replaced with a delayed quadrature-phase baseband signal (g q (t−T iq )). 
     Estimating Phase, Amplitude, and Gain Imbalance (e e , f e  and G oe ) 
     Referring again to  FIG. 4 , the linear compensation block  410  uses the phase and amplitude parameters e e  and f e  to compensate for phase and amplitude imbalance in the quadrature up-converter  206 , and the in-phase and quadrature-phase gain multipliers  412 ,  414  use the scaling factor G des /G oe  to balance the gain. The phase and amplitude parameters e e  and f e  and the overall gain G oe  may be estimated from the analog impairment signal z(t) described above with reference to  FIG. 3 . The subscript “e” or “est” as used within this application denotes that the value for the given parameter is an estimated value. 
     The analog impairment signal z(t) may be expressed by the following equation:
 
 z ( t )=( C ( t ) a+S ( t ) c )* g   ieq ( t−T )+( C ( t ) b+S ( t ) d )* g   qeq ( t−T   q );
 
where:
         g ieq (t)=g i (t−T i )+b i ;   g qeq (t)=g q (t−T q )+b q ;   C(t)=cos(2π(F 1 −F 2 )t);   S(t)=sin(2π(F 1 −F 2 )t); and       

     
       
         
           
             
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     The estimated matrix coefficients {a e , b e , c e , d e } may then be used to estimate the phase, amplitude, and gain imbalance parameters, e e , f e , and G oe , as follows: 
                 e   e     =           d   e     ⁢     c   e       +       b   e     ⁢     a   e               a   e     ⁢     d   e       -       c   e     ⁢     b   e             ;                   f   e     =         d   e   2     +     b   e   2             a   e     ⁢     d   e       -       c   e     ⁢     b   e             ;   and                 G   oe     =             a   e     ⁢     d   e       -       c   e     ⁢     b   e               b   e   2     +     d   e   2           .           
Estimating Bias Offset (b ie  and b qe )
 
     With reference to  FIG. 4 , the in-phase and quadrature-phase delay compensation blocks  402 ,  404  offset the I and Q baseband signals by in-phase and quadrature-phase bias parameters b ie  and b qe . The bias parameters, b ie  and b qe , may be estimated from the analog impairment signal z(t) independently of the other impairment parameters e e , f e , and G oe . The analog impairment signal z(t)  126  may thus be expressed as: 
                 z   ⁡     (   t   )       =         [           cos   (     ϕ   ⁡     (   t   )               sin   ⁡     (     ϕ   ⁡     (   t   )       )             ]     ⁢         G   o     ⁡     [         1       0           e       f         ]       ⁡     [           b   i               b   q           ]         =         [         C       S         ]     ⁡     [         a       b           c       d         ]       ⁡     [           b   i               b   q           ]           ;         
such that:
 
 z ( t )=( Ca+Sc ) b   i +( Cb+Sd ) b   q .
 
The term (Ca+Sc) may be regarded as a vector in the two-dimensional Hilbert space of C(t) and S(t), and an orthogonal vector to (Ca+Sc) is (Cc−Sa). Consequently &lt;(Ca+Sc)(Cc−Sa)&gt;=0, which allows the parameters b i  and b q  to be extracted from the equation. Thus estimates of b i  and b q , denoted as b ie  and b qe , may be derived as:
 
                     b   ie     =       ⁢         ∑     n   =   0       N   -   1       ⁢       z   ⁡     (   n   )       ⁢     (         C   ⁡     (   n   )       ⁢     c   e       -       S   ⁡     (   n   )       ⁢     a   e         )             ∑     n   =   0       N   -   1       ⁢       (         C   ⁡     (   n   )       ⁢     c   e       -       S   ⁡     (   n   )       ⁢     a   e         )     ⁢     (         C   ⁡     (   n   )       ⁢     b   e       +       S   ⁡     (   n   )       ⁢     d   e         )                         =       ⁢       2   ⁢       ∑     n   =   0       N   -   1       ⁢       z   ⁡     (   n   )       ⁢     (         C   ⁡     (   n   )       ⁢     c   e       -       S   ⁡     (   n   )       ⁢     a   e         )                 a   e     ⁢     d   e       -       b   e     ⁢     c   e             ;                   and               b   qe     =           ∑     n   =   0       N   -   1       ⁢       z   ⁡     (   n   )       ⁢     (         C   ⁡     (   n   )       ⁢     d   e       -       S   ⁡     (   n   )       ⁢     b   e         )               a   e     ⁢     d   e       -       b   e     ⁢     c   e           .           
Automatic Gain Control Correction Loop
 
       FIG. 6  is a block diagram of a direct up-conversion transmitter chain  600  having an automatic gain control (AGC) correction loop in the impairment compensation feedback path. This transmitter chain  600  is similar to the transmitter chain  100  described above with reference to  FIGS. 1-5 , except the feedback path includes a comparator  602 , a mixer  604 , and a gain correction loop  606 . In operation, the AGC loop compensates for errors in the AGC amplifier  208  described above with reference to  FIG. 2 . 
     The comparator  602  has a positive input coupled to the estimated gain G oe  from the impairment detector  116  and a negative input coupled to the pre-selected desired gain G des . The comparator  602  subtracts the desired gain G des  from the estimated gain G oe  to generate a comparator output that is coupled as an input to the mixer  604 . The mixer  604  applies a pre-selected gain coefficient K G  to the comparator output, and generates a mixer output that is coupled as an input to the gain correction loop  606 . The gain correction loop  606  may, for example, be a first order correction loop that generates a gain-compensated output G comp  that may be expressed by the equation: G comp =G comp −K G (G oe −G des ). Accordingly, the speed at which the AGC correction loop  606  will track AGC errors may be increased by increasing the value of the gain coefficient K G . 
     The gain-compensated output, G comp , from the AGC correction loop  606  is coupled as the inputs to the gain multipliers  412 ,  414  in the impairment compensator  112 , as described above with reference to  FIG. 4 . It should be understood, that although the impairment compensator  112  illustrated in  FIG. 6  has been simplified to show only the gain multipliers  412 ,  414 , the impairment compensator  112  may include the additional elements described above with reference to  FIG. 4 . 
     Local Oscillator Leakage Nulling Loop 
       FIG. 7  is a block diagram of a direct up-conversion transmitter chain  700  having a local oscillator (LO) leakage nulling loop  702  in the impairment compensation feedback path. This transmitter chain  700  is similar to the transmitter chain  100  described above with reference to  FIGS. 1-5 , except for the inclusion of the LO leakage nulling loop  702  in the feedback path. In operation, the LO leakage nulling loop  702  corrects for corruption of the RF signal  121  caused by the LO signal  303 . 
     The LO signal  303  may be suppressed in the RF signal  121  by nulling the DC bias parameters b ie  and b qe . The LO leakage nulling loop  702  accomplishes this by implementing a first order correction loop that applies a pre-selected bias coefficient K b , and generates compensated in-phase and quadrature-phase bias offset parameters, b icomp  and b qcomp , according to the equations:
 
 b   icomp   =b   icomp   −K   b   b   ie ; and
 
 b   qcomp   =b   qcomp   −K   b   b   qe .
 
     The compensated in-phase and quadrature-phase bias offset parameters, b icomp  and b qcomp , are coupled as inputs to the in-phase and quadrature-phase bias compensation adders  406 ,  408 , as described above with reference to  FIG. 4 . It should be understood, that although the impairment compensator  112  illustrated in  FIG. 7  has been simplified to show only the bias compensation adders  406 ,  408 , the impairment compensator  112  may include the additional elements described above with reference to  FIG. 4 . 
     Quadrature Imbalance Compensation Tracking Loop 
       FIG. 8  is a block diagram of a direct up-conversion transmitter chain  800  having a quadrature imbalance compensation loop  802  in the impairment compensation feedback path. This transmitter chain  800  is similar to the transmitter chain  100  described above with reference to  FIGS. 1-5 , except for the inclusion of the quadrature imbalance compensation loop  802  in the feedback path. In operation, the quadrature imbalance compensation loop  802  further compensates for phase and amplitude imbalance in the quadrature up-converter  206 . 
     The phase and gain imbalance of the quadrature up-converter  206  is represented by the phase and amplitude parameters “e” and “f” as described above. In order to compensate for phase and amplitude imbalance, the I and Q components of the baseband signal are multiplied by: 
                   [         1       0           e       f         ]       -   1       =       [         1       0             -     e   f             1   f           ]     =     [         1       0             e   comp           f   comp           ]         ,         
where e comp  and f comp  are the desired compensation variables tracked by the quadrature imbalance compensation loop  802 . If values of the phase and amplitude parameters, e and f, where known, then the desired compensation variables could be calculated according to the equations:
 
     
       
         
           
             
               
                 e 
                 comp 
               
               = 
               
                 - 
                 
                   e 
                   f 
                 
               
             
             ; 
             and 
           
         
       
       
         
           
             
               f 
               comp 
             
             = 
             
               
                 1 
                 f 
               
               . 
             
           
         
       
     
     Since the impairment detector  116  only calculates estimated phase and amplitude parameters, e e  and f e , however, the quadrature imbalance compensation loop  802  applies a pre-selected quadrature balancing coefficient K Q  to calculate the desired compensation variables, e comp  and f comp . The quadrature imbalance compensation loop  802  may, for example, be a first order loop correction loop that generates the desired compensation variables, e comp  and f comp , according to the following equations: 
     
       
         
           
             
               
                 e 
                 comp 
               
               = 
               
                 
                   e 
                   comp 
                 
                 - 
                 
                   
                     K 
                     Q 
                   
                   ⁢ 
                   
                     
                       e 
                       e 
                     
                     
                       f 
                       e 
                     
                   
                 
               
             
             ; 
             and 
           
         
       
       
         
           
             
               f 
               comp 
             
             = 
             
               
                 f 
                 comp 
               
               + 
               
                 
                   
                     K 
                     Q 
                   
                   ⁡ 
                   
                     ( 
                     
                       
                         1 
                         
                           f 
                           e 
                         
                       
                       - 
                       1 
                     
                     ) 
                   
                 
                 . 
               
             
           
         
       
     
     The desired compensation variables, e comp  and f comp , are coupled as inputs to the linear compensation block  410  of the impairment compensator  112 , as described above with reference to  FIG. 4 . It should be understood, that although the impairment compensator  112  illustrated in  FIG. 8  has been simplified to show only the linear compensation block  410 , the impairment compensator  112  may include the additional elements described above with reference to  FIG. 4 . 
     Differential Timing Error Compensation Loop 
       FIG. 9  is a block diagram of a direct up-conversion transmitter chain  900  having a differential timing error compensation loop  902  in the impairment compensation feedback path. This transmitter chain  900  is similar to the transmitter chain  100  described above with reference to  FIGS. 1-5 , except for the inclusion of the differential timing error compensation loop  902  in the feedback path. In operation, the differential timing error compensation loop  902  adjusts the I and Q component delays, T ie  and T qe , to compensate for dynamic changes in the up-converter channel delays. 
     The differential timing error compensation loop  902  receives the in-phase and quadrature-phase component delays, T ie  and T qe , estimated by the impairment detector  116  as described above, and applies a pre-selected timing adjustment coefficient K T  to generate compensated in-phase and quadrature-phase component delays, T qc  and T ic . The differential timing error compensation loop  902  may, for example, be implemented as a first order correction loop that generates the compensated component delays, T qc  and T ic , according to the following equations:
 
 T   ic   −T   ic   +K   T ( T   ie   −T   o ); and
 
 T   qc   =T   qc   +K   T ( T   ie   −T   o ),
 
where T o  is a target common delay of the in-phase and quadrature-phase channels that is pre-selected such that the delay implemented by the impairment compensator  112  is always positive.
 
     The compensated component delays, T qc  and T ic , are coupled as inputs to the in-phase and quadrature-phase delay compensation blocks  402 ,  404  in the impairment compensator  112 , as described above with reference to  FIG. 4 . It should be understood, that although the impairment compensator  112  illustrated in  FIG. 9  has been simplified to show only the delay compensation blocks  402 ,  404 , the impairment compensator  112  may include the additional elements described above with reference to  FIG. 4 . 
     Detector Temperature and Supply Voltage Compensation 
       FIG. 10  is a block diagram of an exemplary temperature and supply voltage compensation circuit  1000  for the impairment detector  116  shown in  FIGS. 1 ,  3 , and  6 - 9 . Portions of the impairment detector  116  described above may be sensitive to fluctuations in temperature and supply voltage. These temperature and supply voltage sensitive components may, for example, include the variable attenuator  302 , the down-conversion mixer  304  and the A/D converter  308  described above with reference to  FIG. 3 . These and any other temperature and/or voltage sensitive components are represented in  FIG. 10  by the RF and IF component block  1010 . In addition, the temperature and supply voltage compensation circuit  1000  also includes a band gap voltage reference  1020 , a temperature sensor  1030 , a multiplexer  1040 , a first analog-to-digital (A/D) converter  1050 , a processor  310 , and a second analog-to-digital (A/D) converter  1070 . The temperature sensor  1030  may, for example, be a device that is sensitive to temperature and has a repeatable response and negligible hysteresis, such as a diode detector. The processor  310  may, for example, be the impairment detector processor  310  described above with reference to  FIG. 3 . 
     The band gap voltage reference  1020  generates a reference voltage V ref . Since the band gap voltage reference  1020  is not ideal, however, the reference voltage is a function of the ambient temperature T and the battery supply voltage V d . 
     The temperature sensor  1030  generates a temperature sensor voltage, V temp , which is proportional to the ambient temperature T. Since the temperature sensor  1030  is not ideal, however, its output, V temp , is also a function of the battery supply voltage V d . 
     The multiplexer  1040  is coupled to the reference voltage V ref , the temperature sensor voltage V temp , and the battery supply voltage V d . In addition, the multiplexer  1040  also receives a control input  1045  from the processor  310  which selects either V temp  or V d  as a selected input to the multiplexer  1040 . The multiplexer  1040  then divides the selected input, V temp  or V d , by the reference voltage V ref  to generate an analog ratio output R temp  or R vd , as follows:
 
 R   temp   =V   temp   /V   ref ; and
 
 R   vd   =V   d   /V   ref .
 
     The selected analog ratio output, R temp  or R vd , is sampled by the first A/D converter  1050  and coupled as an input to the processor  310 . The processor  310  may, for example, alternate between selecting V temp  and V d  as the selected input to the multiplexer  1040  in order to generate alternating sampled R temp  and R vd  inputs to the processor  310 . In addition, the analog intermediate frequency (IF) signal generated by the temperature and supply voltage sensitive components  1010  in the impairment detector is sampled by the second A/D converter  1070  and coupled as an additional input to the processor  310 . In operation, the processor  310  uses the sampled ratios, R temp  and R vd , to estimate the actual ambient temperature T and supply voltage V d  (the estimated values of T and V d  are designated herein as T est  and V dest  respectively). A method for estimating the values of T and V d  is described below with reference to  FIG. 11 . 
     The estimated temperature and supply voltage values, T est  and V dest , are used to estimate the overall gain G(T est , V dest ) of the analog portion of the impairment detector  116 , which is a function of both the ambient temperature T and the supply voltage V d . By comparing the estimated overall gain G(T est , V dest ) to the pre-selected desired gain of the impairment detector  116 , the processor  310  compensates for temperature- and supply voltage-related impairments in the analog IF signal by correcting one or more of the parameters in the feedback signal  126  described above. For instance, temperature- and supply voltage-related corrections in the analog IF signal may be implemented by adjusting the estimated gain G oe , described above with reference to  FIGS. 4 and 6 , by a factor of G(T est , V dest ). 
       FIG. 11  is a flow diagram that illustrates a method  1100  for iteratively estimating the values of the ambient temperature T and battery supply voltage V d  shown in  FIG. 10 . The method  1100  may, for example, be performed by the processor  310  described above with reference to  FIG. 10 . 
     The method  1100  begins in step  1110 . In step  1120 , the voltage value of the reference voltage output V ref  from the band gap voltage reference  1020  is estimated. The reference voltage V ref  may be calculated, for example, using the estimated values for the ambient temperature T est  and the supply voltage V dest , according to the following equation:
 
 V   ref   =C   1   +C   2   T   est   +C   3   V   dest ;
 
where C 1 , C 2  and C 3  are constants that may be derived as part of a calibration process. The initial values of T est  and V dest  may be pre-selected or otherwise initialized, and therefore should be in error. In successive iterations of the method  1100 , however, the values of T est  and V dest  should converge on their respective actual values, and thus the estimated value of V ref  should also converge on its actual value.
 
     In step  1130 , the estimated value of the battery supply voltage, V dest , is calculated. The value of V dest  may, for example, be calculated according to the equation:
 
 V   dest   =R   vd   V   ref ;
 
where R vd  is a sampled ratio output from the first multiplexer  1040  described above, and V ref  is the voltage reference output from the band gap voltage reference  1020 . Similarly, in step  1140 , the value of the temperature sensor voltage, V temp , as described above, is estimated according to the equation:
 
 V   test   =R   temp   V   ref ;
 
where R temp  is a sampled ratio output from the first multiplexer  1040 . Then, in step  1150 , the ambient temperature T is estimated according to the equation:
 
 T   est =( V   test   −C   4   −C   6   V   dest )/ C   5 ;
 
where C 4 , C 5  and C 6  are constants that may be derived as part of a calibration process.
 
     In step  1160 , the estimated values, V dest  and T est , for the ambient temperature T and supply voltage V d  are examined to determine if the values have sufficiently converged with their respective actual values. This step  1160  may be performed, for example, by saving the values of V dest  and T est  to a memory device at each iteration of the method  1100 , and comparing the current values with stored values. The estimated values, V dest  and T est , may be deemed to have sufficiently converged when the difference between values calculated at successive iterations reaches a pre-selected value. If it is determined in step  1160  that either of the estimated values, V dest  or T est , has not sufficiently converged with its actual value, then the method repeats at step  1120 . Otherwise, the method  1100  ends at step  1170 . 
     Method of Operating a Feedback Compensation Detector 
       FIG. 12  is a flow diagram illustrating an exemplary method  1200  for operating the feedback compensation detector described above with reference to  FIGS. 1-9 . The method begins in step  1210 . In step  1220 , the in-phase and quadrature-phase component delays T i  and T q  are estimated, as described above with reference to  FIG. 5 . In steps  1230 - 1250 , the matrix coefficients {a, b, c, d}, the phase, amplitude and gain imbalances (e e  f e , and G oe ), and the bias offset values (b ie  and b qe ) are estimated, as described above with reference to  FIG. 4 . Then, in step  1260 , the I and Q baseband signals are compensated using one or more of the estimated impairment parameters, as described above with reference to  FIGS. 4-9 . If control loops, such as those described above with reference to  FIGS. 6-9 , are utilized in the I and Q baseband signal compensation step  1260 , then the method  1280  may repeat at step  1270 . Otherwise, the method  1200  ends at step  1280 . 
     This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to make and use the invention. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art.