Patent Publication Number: US-6910196-B2

Title: Clocked and non-clocked repeater insertion in a circuit design

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention is related to the field of circuit design. In particular, the present invention is related to a method and apparatus to insert clocked and non-clocked repeaters in a circuit design. 
   2. Description of the Related Art 
   Interconnect optimization is a critical component of circuit design, and in particular, of Very Large Scale Integration (VLSI) circuit designs. As part of interconnect optimization of a VLSI circuit design, repeaters (e.g., buffers and inverters) are used to reduce interconnect delay and to meet transition time/noise constraints. However, merely using repeaters does not solve all timing requirements; for example, when wire delay is greater than a clock cycle, the addition of repeaters may not solve the timing constraints and the insertion of clocked repeaters (e.g. flip-flops and/or latches) is essential. In high-performance VLSI circuits a substantial number of interconnections are pipelined (spanning over more than one clock cycle), making the number of needed repeaters too large for manual design. Therefore, an automated tool to insert clocked repeaters, as well as non-clocked repeaters, in the circuit design is necessary to reduce the Register-Transfer-Level (RTL)-to-layout convergence time. This is important as current scaling trends indicate that the number of both clocked and non-clocked repeaters increases exponentially every process generation. 
   In pipelined interconnects at least two challenges are faced by circuit designers: a) The accurate prediction of the minimum latency that can be achieved between the blocks of a design, given the available routing resources of a semiconductor process, and b) The insertion of buffers and flip-flops in a large number of pipelined nets where interconnect and functional latency constraints are specified at-priori by the circuit designers. 

   
     BRIEF SUMMARY OF THE DRAWINGS 
     Example embodiments of the present invention are illustrated in the accompanying drawings. The accompanying drawings, however, do not limit the scope of the present invention. Similar references in the drawings indicate similar elements. 
       FIG. 1  illustrates a conventional routing tree topology. 
       FIG. 2  illustrates a routing grid and a clock domain grid according to one embodiment of the invention. 
       FIG. 3  illustrates a repeater assignment for the routing tree topology of  FIG. 1  according to one embodiment of the invention. 
       FIG. 4  illustrates the pseudo-code for operations used in cover computation according to one embodiment of the invention. 
       FIG. 5  illustrates the pseudo code for calculating the optimal set of covers Γ l  using the minimum latency (MiLa) algorithm according to one embodiment of the invention. 
       FIG. 6  illustrates pseudo-code for a merge function according to one embodiment of the invention. 
       FIG. 7  illustrates pseudo-code for the given latency (GiLa) algorithm according to one embodiment of the invention. 
       FIG. 8  illustrates the pseudo-code for inserting extra flip-flops in a branch rooted by a sub-tree according to one embodiment of the invention. 
       FIG. 9  illustrates a flow diagram for calculating the optimal set of covers using the MiLa algorithm of  FIG. 5  according to one embodiment of the invention. 
       FIG. 10  illustrates a computer system for computing optimal covers for minimum latency and for computing optimal covers for a given latency according to one embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   Described is a method and apparatus to obtain minimum time latency, i.e. minimum cycle latency and maximum required time, at a driver for at least a simultaneous assignment of clocked (e.g., flip-flops and/or latches) and non-clocked repeaters in a topology, traversed from one or more receivers to a driver, comprising, determining whether a node in the topology is a leaf, assigning covers if the node is a leaf, and eliminating inferior covers taking into account a difference in interconnect latency associated with the covers. Determining whether a node in the topology comprises a branch, assigning covers to the node if the node comprises a branch and eliminating inferior covers taking into account a difference in interconnect latency associated with the covers. Determining whether a node in the topology comprises a first branch and a second branch, assigning covers to the node by swapping covers of the two branches if maximum latency of a first branch is less than maximum latency of a second branch, merging covers of the first branch and the second branch to form a merged branch; and eliminating inferior covers of the merged branch taking into account a difference in interconnect latency associated with the covers. At the end of the traversal, the optimal solutions are found at the driver. The above method may be modified with a heuristic to insert repeaters in a topology for a given latency at each driver-receiver pair. 
   References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Parts of the description are presented using terminology commonly employed by those of ordinary skill in the art to convey the substance of their work to others of ordinary skill in the art. 
   In the following description and claims, the terms “coupled” and “connected”, along with derivatives such as “communicatively coupled” may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct physical contact with each other, but still co-operate or interact with each other. 
     FIG. 1  illustrates a conventional routing tree topology. As illustrated in  FIG. 1 , a conventional tree topology,  100 , Θ=(N, B) comprises a set N of nodes n i , where i=1 to n, and a set B of directed branches b u,v  connecting node pairs (u, v), with u&lt;v. The root and the leaves of the tree host the interconnect driver and receivers respectively. Other intermediate nodes are the candidate locations for the insertion of repeaters. Each node n i  can also be thought of as the root of a sub-tree Θ i   ⊂  composed of all nodes and branches of Θ that can be reached from n i , with Θ i ≡Θ at the root of Θ. At a branch point n i  of degree 2, Θ i,v  and Θ i,z  are sub-trees rooted at n i  composed of the portions of Θ i  departing from branches b i,v  and b i,z  respectively. In one embodiment of the invention, the routing tree structure of  FIG. 1  can be used to represent interconnects with branching points of degree greater than two by introducing zero-length branches. 
     FIG. 2  illustrates a routing grid and a clock domain grid according to one embodiment of the invention. As illustrated in  FIG. 2 , the routing grid  205  and clock domain grid  210  comprises a clock distribution network of a chip that may be modeled as a regular grid of n independent domains Δ i  distributed over the die of the chip. The clock skew may then be represented by an upper triangular matrix Σ where an element σ i,j  indicates the clock skew within domain Δ i  and an element σ i,j  indicates the clock skew between domains Δ i  and Δ j . The location of the nodes of every Θ is then constrained to the center of the tiles of a finer regular routing grid superimposed on the clock distribution network grid. In the clock distribution network grid the size l tile  of its tiles should be short enough to allow an effective insertion of repeaters. In particular, this is achieved by choosing a value two or more times shorter than a given process dependent repeater critical length l crit . In one embodiment of the invention, l crit  may be defined as the typical distance between the repeaters of a delay optimized two-pin interconnect routed over the most resistive metal layer used. Let 
         L   crit     =       l   crit       l   tile             
be such distance measured in terms of the clock distribution network grid tiles. The repeater delay is insensitive to local displacement, therefore, the center of a relatively small regular routing grid tile provides a good approximation for the real location of the repeater to be positioned anywhere within the tile.
 
     FIG. 3  illustrates repeater assignment for the routing tree topology of  FIG. 1  according to one embodiment of the invention. As illustrated in  FIG. 3 , repeater assignment  300  comprises interconnects, routed over a topology Θ, that may be designed by allocating in the nodes and branches of the topology Θ routing resources such as wires of given metal layer, length, width, and repeater gates of given size. However, for simplicity it is assumed that all branches b u,v  comprise wires of given length l u,v =l tile  having the same metal layer and fixed width. A repeater assignment A Θ  over topology Θ is then defined as a set of labels a u,v  and a u  where a value a u,v =g k  corresponds to the assignment of a repeater g k , from a given gate library G, to branch b u,v  after node n u . A value of a u,v =0 indicates that no repeater is inserted. For a node n u  branching to two children n v  and n z  through branches b u,v  and b u,z , a u ≡a u,v ∪a u,z , whereas if n u  has one child n v , a u ≡a u,v . Finally if n u  is a leaf, a u =0. This representation is also suitable for specifying a sizing solution of the interconnect driver and receivers. 
   In one embodiment of the invention, a wire of length l u,v  routed over branch b u,v  may be modeled with a resistance R u,v  connected between nodes n u  and n v , and two capacitances of value C u,v  connected between n u  and ground and n v  and ground respectively. If the wire has distributed resistance R l  and distributed capacitance C l , the lumped R u,v  and C u,v  can be calculated as R u,v =R l l u,v , and C u,v =0.5C l l u,v . 
   If a repeater assignment is given for a routing tree Θ along with timing constraints at its leaves in terms of input load capacitance and propagation required time, the timing at the root of each sub-tree Θ i  of Θ needed to satisfy the constraints may be expressed by a 4-tuple γ i =(c i ,r i ,λ i ,a i ). c i  is the input capacitance seen at the root, r i  is the required arrival time after the positive edge of a clock signal φ with period T φ , λ i  is the interconnect cycle latency defined as the maximum number of clocked repeaters crossed when going from the root of Θ i  to its leaves, and a i  is the repeater assignment at n i . A clocked repeater inserted at the root of Θ i  will increase its latency by one since the root is connected to the gate input. Since leaf n u  of Θ is also the elementary tree Θ u ≡({n u },φ), the interconnect constraints at the receivers are also specified using a 4-tuple γ u =(c u ,r u ,0,0). Since γ specifies the timing constraints and the allocated resources of an interconnect mapped onto the topology of sub-tree Θ, the γ interconnect is called the cover of Θ. In general sub-tree Θ i  has a multiple number of feasible covers specifying different timing and resource assignments. For convenience, these covers are grouped per latency in the ordered set Γ i ={Γ i   m , . . . , Γ i   n } with m, n≧0 and m&lt;n, where Γ i   k ={(c l ,r l ,k,a l )}, . . . (c n ,r n ,k,a n )} is a set of covers of Θ l  with same latency k. In the case of a sub-tree Θ u  rooted at a branching point of degree two, γ u,v  and γ u,z  may be used to denote the covers of the sub-tree components Θ u,v  and Θ u,z  respectively. 
   Covers may be computed as follows: If the covers at the leaves of Θ are given as constraints and if assignment A Θ  is given, the cover of the sub-trees Θ i  may be recursively determined. The covers may be computed by starting from the leaves and ending at the root, using a hierarchical delay model such as Elmore which is well known by one having ordinary skill in the art. The covers may be computed using the wire and gate delay models discussed above using three operations wire, repeat and join. 
     FIG. 4  illustrates the pseudo-code for operations used in cover computation according to one embodiment of the invention. As illustrated in  FIG. 4 , if a node n u  branches to node n v  with a given γ v  through branch b u,v  , cover γ u ≡γ u,v  is calculated through operation wire, where γ u,v  is back propagated to n u  inserting a wire on branch b u,v  using Elmore delay. The covers γ are constrained by a fixed given clock cycle T φ . Therefore, only covers with non-negative required time are generated. Next, if a gate is inserted at n u  operation repeat is called. A non-clocked repeater is inserted if the required time at its input is zero or positive. The new required time and the input capacitance of g are computed and stored in the cover while the latency remains unchanged. Similarly, a clocked repeater is inserted if the slack at its input is zero or positive. In particular, the slack is computed from the required time of the wire by subtracting the delay of the flip-flop and the term σ m,n  that models the skew of the clock signal φ as defined above. Here, Δ m  is the clock domain where the flip-flop g is located and Δ n  is chosen among the domains of the upstream flip-flop so as to consider the worst case value of σ m,n . If the slack is not negative, the required time at the input of the gate is set to the period of the clock minus the set-up time of gate g, and the latency of the new cover is increased by one. 
   When two covers γ u,v  and γ u,z  are back propagated to a branch node n u  of degree two via operations wire and repeat, cover γ u  is calculated by means of operation join. In join the input capacitance is the sum of the load seen at the two ranches and the required time is the minimum of the required time of γ u,v  and γ u,z  to account for the worst case. On the other hand, to propagate the correct value of latency to the root, the latency of the joined cover is the maximum of the latencies of the merging branches. 
   When multiple covers are computed for a sub-tree Θ, each one corresponding to a different assignment of repeaters at the candidate locations, those non-inferior covers that lead to optimal solutions at the root of Θ are saved. Thus, inferior covers are pruned in accordance with the pruning rules illustrated below as follows: ∀γεΓ, γ is inferior in Γ if ∃{dot over (γ)}εΓ such that at least one of the following is true: 
   a. λ={dot over (λ)},c≧ċ,r&lt;{dot over (r)} 
   b. λ={dot over (λ)},c&gt;ċ,r={dot over (r)} 
   c. λ={dot over (λ)},c=ċ,r={dot over (r)},cost(γ)&gt;cost({dot over (γ)}) 
   d. λ&gt;{dot over (λ)},c≧ċ,r≦{dot over (r)} 
   e. ∀λ, ∀c, r&lt;0 
   From a and b above noted that γ is an inferior cover since any gate driving a sub-tree Θ with cover γ has input required time that is worse than that of the same gate driving Θ with {dot over (γ)}, while having the same input capacitance and the same latency. When γ and {dot over (γ)} have identical input capacitance and required time, as in c above, γ is also inferior if the value of a user specified cost function associated with the routing resources allocated in Θ by γ, e.g., repeater area, is greater than that of {dot over (γ)}. When γ has latency higher than that of {dot over (γ)}, as seen in d above, γ is inferior for the same reasons as in a and b, and when it has identical input capacitance and required time, because γ covers sub-tree Θ with same timing as in {dot over (γ)} but wasting an extra clock cycle. Finally, when the required time is negative regardless of latency and input capacitance, as in rule e above, cover γ is inferior because it does not meet the basic timing constraint of a clocked system where the required time is bounded from zero to a maximum equal to the clock period. 
   A method to calculate an optimal set of covers Γ l  with minimum cycle latency and maximum required time at the driver of θ l ≡Θ, inserting clocked and non-clocked repeaters according to the pruning rules described above is now illustrated. Given an interconnect topology Θ mapped onto a routing grid and a clock grid with skew matrix Σ, timing constraints at the receivers in terms of γ u ≡(c u ,r u ,0,0), and a library G of clocked and non-clocked repeaters. 
     FIG. 5  illustrates the pseudo code for calculating the optimal set of covers Γ l  using the MiLa algorithm according to one embodiment of the invention.  FIG. 9  illustrates a flow diagram for calculating the optimal set of covers using the MiLa algorithm of  FIG. 5  according to one embodiment of the invention). As illustrated in  FIGS. 5 and 9 , minimizing the latency in Γ l  corresponds to minimizing the signal latency at the most latent receiver of the net. Also, the latency values λ u  at the receivers are set to zero for convenience. In practice, the operation of the MiLa algorithm is independent of the λ u  values, as they may be set to any arbitrary integer number different from each other. The real latency at each receiver is computed later by traversing the tree from root to leaves and computing the number of crossed flip-flops. The optimal covers at each node of the tree are computed recursively after multiple nested calls, starting from the leaves and ending at the root, traversing the tree in a depth first fashion. At any call of the MiLa algorithm, as illustrated in line  1  of  FIG. 5 and 910  of  FIG. 9 , a determination is made if θ u  is a leaf, and if so at  920  the given constraint at the corresponding receiver Γ u ={(c u ,r u ,0,0)} is returned. The process flows to  980  wherein the next node is examined. If the root of θ u  is connected to a single branch b u,v , as illustrated in line  2 . 1  and  930 , the algorithm is called again to compute the optimal covers Γ v  of the next sub-tree θ v . In section  2  and  960 , the covers are propagated in line  2 . 2  to node n u  inserting wires. Next, in loop  2 . 4  an additional cover is inserted in Γ u  for each repeater of library G. To do this, all the covers computed in line  2 . 2  are repeated using the same repeater gate g calling operation repeat thus generating the new set Γ. Inferior covers are then deleted according to the pruning rules discussed above leaving Γ with only one optimal cover for every available sub-set Γ k   ⊂  with latency k. Here |Γ| is equal to one, since all its covers prior to applying the pruning rules originated with the same repeater. At 2.5 in the pseudo-code of  FIG. 5 , Γ u  is updated by adding the repeated covers computed. Thereafter the process flows to  980  wherein the next node is examined. 
   Section  3  and  940  of  FIG. 9  of the MiLa algorithm computes the optimal covers of sub-tree θ u  when its root is connected to two branches b u,v  and b u,z .  FIG. 6  illustrates pseudo-code for a merge function according to one embodiment of the invention. The merge function merges the covers from the two branches b u,v  and b u,z  The merge function assumes that the covers in sets Γ u  and Γ v  are sorted by increased latency and within each latency, by increasing required time and capacitance. A cover not featuring a monotonic increasing behaviour is an inferior one according to the pruning rules and is deleted prior to the merge procedure of the pseudo-code of FIG.  6 . 
   At  970  of FIG.  9  and in the MiLa algorithm pseudo code, at line  3 . 1  the algorithm calls itself twice to compute the covers of sub-trees θ u,v  and θ u,z . At 3.2 in the MiLa algorithm pseudo code the corresponding sets Γ u,v  and Γ u,z  is composed of an arbitrary number of sub-sets Γ k  of different latency k, where k is equal to the max latency at the root of each branch. Similar to the cover latency λ defined in section  2  of the MiLa algorithm the signal latency at any node of an interconnect can be defined as the number of flip-flops crossed to reach the node starting from the driver where the signal latency is zero. While the algorithm minimizes the signal latency at the most latent receiver, it also determines the signal latency at other receivers such that optimal covers are obtained and propagated back to the driver. To do so, all combinations of the subsets Γ k ⊂Γ u,v  and Γ h ⊂Γ u,z  are joined so that for each couple (Γ k ,Γ h ) a new joined sub-set Γ q ⊂Γ u  is generated with function merge where q=max(k, h). For example, a value q=k corresponds to the case of joined covers of Γ u , with latency k where the h-latency covers of Γ u,z  have been shifted in time by latency k−h (i.e., by using a latency shift operation). The general case is implemented in loop  3 . 4  of the MiLa algorithm where shifts in latency are generated and the joined covers of Γ u,v  computed by function merge. Here, because of line  3 . 3  in the MiLa algorithm pseudo code, set Γ u,v  is the one that contains covers with maximum latency. Therefore, in line  3 . 4 . 1 , only the covers of Γ u,z  need to be shifted by latency k to consider all possible cases. After determining the optimal covers Γ u  for each case of branching degree at the root of θ u  in line  4 , set Γ u  is pruned of its inferior elements according to the pruning rules. In line  5  the optimal set Γ u  is returned. Thereafter, the process flows to  980  wherein the next node is examined. 
   After the first call to MiLa returns, the optimal cover set Γ l  of the whole interconnect is computed, and for each γ i εΓ l  with minimum latency the corresponding repeater assignment and the signal latency at receivers are found by traversing, from root on, all the component covers from which the γ i  at the driver was back propagated. At  990 , the process determines that the node being examined is a driver. The MiLa algorithm ends at  955 . 
   As mentioned above, a set Γ u  can be represented as Γ u ={Γ u   k , . . . , Γ u   k+n−1 }, where non-inferior covers are ordered in increasing λ identifying n latency subsets Γ u   i , with i=k, . . . , k+n−1. In practice, for a choice of tile size l tile , it can be experimentally verified that covers in subsets Γ u   k+m  with m≧2 do not participate in producing optimal solutions at the driver, suggesting that the covers in Γu k+1  have always enough high required time and low capacitance to provide for back-up solutions when covers in Γ u   k  cannot be propagated because of property  4 . 3 . In this context a practical solution to reduce the run-time without affecting optimality is that of avoiding the generation of covers Γ u   k+m  with m≧2 in any set Γu, therefore setting an upper bound of 2 to the number of latency subsets. In particular, this can be achieved in MiLa by allowing in line  2 . 4 . 1  the insertion of clocked repeaters only to the covers Γ u   k  with lowest latency in Γ u ={Γ u   k ,Γ u   k+1 }. 
   The optimality of the MiLa algorithm is proved by induction on the sequence of recursive computations of cover sets Γ u  generated by the depth first traversal induced by the first call to θ l . Therefore, assuming that the given covers Γ at the receivers are optimal, one only has to prove the optimality of the covers produced by one recursive call to section  2  or  3  of the MiLa algorithm. However, both sections  2  and  3  produce a cover set Γ u  containing among its elements possible optimal solutions according to the problem formulation. The optimality of all the covers of Γ u  is then ensured by the application of the pruning rules which eliminate inferior elements. 
   The MiLa algorithm solves the non-clocked repeater problem if no flip-flops are included in the repeater library G. In this case, the time complexity of the algorithm is O(L crit |G||B|), where L crit  is the repeater critical length defined with respect to  FIG. 2  above and |B| the number of branches in the routing tree, in contrast with the complexity O(|B| 2 ) illustrated in the van Ginneken algorithm, well known by one having ordinary skill in the art. In the van Ginneken algorithm only one buffer is used and L crit  is not considered. In practice, this quadratic complexity is mitigated in the method illustrated by the MiLa algorithm by the repeater critical length L crit  that effectively limits the size of the cover sets Γ to O(L crit |G|). Intuitively this is explained by considering the number of covers originated from a set Γ, back propagated through L crit  degree-1 branches, containing |G| covers each one corresponding to one element of library G. At every branch, line  2 . 4  of MiLa algorithm adds |G| extra covers until the last branch is reached after L crit  times. Here, a total number of (1+L crit )|G| covers collapse into a maximum of |G| distinct non-inferior covers since a repeater is always inserted after L crit  tiles. The same situation applies if the covers originated from γ are back propagated through a branch point with degree 2, since in this case the maximum size of set Γ is also limited to the sum of the sizes of its merging sets. In the case of latent interconnects, that is when |G| also contains flip-flops, the complexity does not increase even though the typical run-time is at least twice as much as that of the no latent interconnect case. Particularly, as explained above, this is due to the fact that the size of every cover set Γ u ={Γ k ,Γ k+1 } is still O(L crit |G|) as it is the size of its two component sub-sets Γ k  and Γ k+1 . Furthermore, in the case of branch points with degree two, the merging operation of section  3 . 4  of MiLa results in a cover set Γ u  with upper bound size |Γ u |=2(|Γ u,v |+|Γ u,z |). 
   The MiLa algorithm can also perform driver and receiver sizing concurrently to repeater insertion. Gate sizing at the receivers is achieved by specifying a constraint set of covers Γ u  for every receiver where each element γ i ≡(c i ,r i ,0,a i =g) corresponds to the selection of a gate g with given size. After running the MiLa algorithm, the repeater assignment of available optimal cover at the driver also includes labels a i  corresponding to the best choice of gates at the receivers. The best sizes of a driver gate is then selected if the covers of the optimal set Γ l  at the root of Θ are run once through loop  2 . 4  of the MiLa algorithm where each gate g in G corresponds to a different size of the driver gate. 
   After the micro architecture design is complete, all latencies are fixed and therefore all interconnects are designed so as to abide by given latency requirements. To this purpose the MiLa algorithm is modified into a new algorithm called GiLa algorithm to accept such given latency constraints and perform repeater insertion with the same underlying methodology, using a simple and effective heuristic to resolve latency mismatch occurrences at intermediate points. 
     FIG. 7  illustrates the GiLa algorithm according to one embodiment of the invention. As illustrated in  FIG. 7 , the formulation of the assignment for the given latency problem is as follows. Given an interconnect topology Θ mapped onto a routing grid and a clock grid with skew matrix Σ, timing constraints at the receivers in terms of γ u ≡(c u ,r u ,λ u ,0), a library G of clocked and non-clocked repeaters, find a set of covers Γ l  at the driver of θ l ≡Θ that satisfy timing constraints at driver and receivers. In addition to capacitance and required time constraints, as is seen in the case of the MiLa algorithm, each receiver is given a latency constraint λ u  corresponding to the latency between the receiver and the driver with inverted sign. The latency λ l  at the driver is set to be zero. For example, the latency constraints of the assignment of  FIG. 3  are λ l =0, λ 4 =0, and λ 7 =−1. Using negative numbers to express the latency at the receivers allows one to reuse operations join and repeat in GiLa without modification. As in the case of MiLa, the covers Γ l  solutions of the problem are computed calling GiLa with argument θ l . GiLa proceeds in the same way as MiLa except when branch points of degree two are reached in section  3  of the algorithm. In GiLa, if the computed sets Γ u,v  and Γ u,z  have covers with the same latency, then function merge is called in line  3 . 5  and the merged set Γ u  is returned after being pruned of inferior solutions. However, if no such covers exist, the difference in latency between the two branches is computed, and the sub-tree with lowest latency recomputed in line  3 . 3 . 1  for θ u,v  or  3 . 4 . 1  for θ u,z  by function ReFlop as illustrated in the pseudo code of  FIG. 8 , so that the latency of that branch is augmented by the corresponding difference. Function ReFlop implements a simple heuristic to insert the needed extra flip-flops in the processed branch. The effectiveness of function ReFlop relies on the following observation: if the covers Γ u  computed for minimum latency at the root of a sub-tree θ u  meet their timing constraints with less latency than requested, it is always possible to meet the same timing constraints also inserting extra flip-flop gates to increase the latency of the branch rooted at θ u . Furthermore, to avoid wasting unnecessary area, extra flip-flops are not inserted after a branching point of degree two as that would lead to the use of two flip-flops for the gain of a latency value of only one. After reaching the root of Θ, in section  2 . 6  GiLa also checks that the solution set Γ l  has covers with latency zero, corresponding to meeting the latency constraints specified at the receivers. If all covers have latency greater than 0, then the latency constraints are infeasible as no solution can be achieved with fewer flip-flops. However, if all covers have latency less than 0, ReFlop is called to insert the needed extra flip-flops. In essence, with the adoption of the ReFlop heuristic, assignment solutions meeting required latency constraints are built, starting from solutions with minimum latency produced by the underlying engine of MiLa in which latency mismatch instances at driver and branch points are resolved by inserting the minimum needed number of flip-flops to meet the given constraints. 
     FIG. 10  illustrates a computer system for computing optimal covers for minimum latency and for computing optimal covers for a given latency according to one embodiment of the invention. In general, the computer system  1000  may comprise a processing unit  1002  communicatively coupled through a bus  1001  to system memory  1013 , mass storage devices  1007 , Input devices  1006 , display device  1005  and network devices  1008 . 
   Bus  1001  may be any of several types of bus structures including a memory bus, a peripheral bus, and a local bus using any of a variety of bus architectures. System memory  1013  comprises a read only memory (ROM)  1004  and random access memory (RAM)  1003 . ROM  1004  comprises basic input output system (BIOS)  1016 . BIOS  1016  contain the basic routines, e.g., start up routines, that facilitate the transfer of information between elements within computer system  1000 . RAM  1003  includes cache memory and comprises operating system  1018 , application programs  1020 , and program data  1024 . Application programs  1020  include the program code for implementing the method to insert repeaters in a circuit design as described with respect to  FIGS. 2-9  above. Program data  1024  may include data generated by application programs  1020 . Mass storage device  1007  represents a persistent data storage device, such as a floppy disk drive, fixed disk drive (e.g., magnetic, optical, magneto-optical, or the like), or streaming tape drive. Mass storage device  10707  may store application programs  1028 , operating system  1026  for computer system  1000 , and program data  1030 . Application programs  1028  and program data  1030  stored on mass storage devices  1007  may include the application programs  1020  and program data  1024  stored in RAM  1003 . One embodiment of the invention may be stored entirely as a software product on mass storage device  1007 . Embodiments of the invention may be represented as a software product stored on a machine-readable medium (also referred to as a computer-accessible medium, a machine-accessible medium, or a processor-accessible medium). The machine-readable medium may be any type of magnetic, optical, or electrical storage medium including a diskette, CD-ROM, memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium may contain various sets of instructions, code sequences, configuration information, or other data. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described invention may also be stored on the machine-readable medium. One embodiment of the invention may be embedded in a hardware product, for example, in a printed circuit board, in a special purpose processor, or in a specifically programmed logic device communicatively coupled to bus  1001 . Processing unit  1002  may be any of a wide variety of general-purpose processors or microprocessors (such as the Pentium® processor family manufactured by Intel® Corporation), a special purpose processor, or a specifically programmed logic device. Processing unit  1002  is operable to receive instructions which, when executed by the processing unit cause the processing unit to execute application programs  1020 . 
   Display device  1005  is coupled to processing unit  1002  through bus  1001  and provides graphical output for computer system  1000 . Input devices  1006  such as a keyboard or mouse are coupled to bus  1001  for communicating information and command selections to processing unit  1002 . Other input devices may include a microphone, joystick, game pad, scanner, or the like. Also coupled to processing unit  1002  through bus  1001  is an input/output interface (not shown) which can be used to control and transfer data to electronic devices (printers, other computers, etc.) connected to computer system  1000 . Computer system  1000  includes network devices  1008  for connecting computer system  1000  to one or more remote devices (e.g., the receiving node)  1012  via network  1014 . Remote device  1012  may be another personal computer, a server, a router, a network PC, a wireless device or other common network node and typically includes one or more of the elements described above with respect to computer system  1000 . Network devices  1008 , may include a network interface for computer system  1000 , Ethernet devices, network adapters, phone jacks, modems, and satellite links. It will be apparent to one of ordinary skill in the art that other network devices may also be utilized. 
   Thus, a method and apparatus for inserting clocked and non-clocked repeaters in a circuit design has been disclosed. While there has been illustrated and described what are presently considered to be example embodiments of the present invention, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the invention. Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims.