Patent Publication Number: US-11399151-B2

Title: Signal conversion circuit and signal readout circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation application of U.S. application Ser. No. 16/784,923, filed on Feb. 7, 2020, which claims priority to Chinese patent application No. 201910118919.3, filed on Feb. 13, 2019, and the entire disclosure of which is incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present disclosure generally relates to an electric circuit field, and more particularly, to a signal conversion circuit and a signal readout circuit. 
     BACKGROUND 
     An image sensor is an important part of a digital camera. Image sensors are mainly used in digital cameras, and imaging apparatus applied in industrial, media, medical and consumer electronics fields. With the increasing demand for cameras, camcorders and multimedia mobile phones, an image sensor market is growing rapidly. A signal readout circuit is an important part of an image sensor. Complementary Metal-Oxide-Semiconductor Transistor (CMOS) integrated circuits have gradually become dominant technology of signal readout circuits due to their low power consumption, low operating voltage and high integration. 
     A sensing array in an image sensor is used to convert optical signals into electric signals. Currently, sensing arrays mainly have a passive pixel structure. Charge signals or current signals sensed by the sensing array are read by an external signal readout circuit without being amplified. In recent years, sensing arrays with an active pixel structure have also gradually increased. Charge signals or current signals sensed by a sensing array with the active pixel structure are processed by a pixel circuit in an image sensor, and an amplified voltage or current is used as an output signal. Output signals of different sensing arrays have different forms or ranges. 
     Therefore, a new signal readout circuit is required, to read output signals of different sensing arrays. 
     SUMMARY 
     In an embodiment of the present disclosure, a signal conversion circuit is provided, including: an operational amplifier, configured to amplify an electric signal output by a sensing array; an input switched capacitor, wherein an end of the input switched capacitor is configured to receive the electric signal output by the sensing array, and another end of the input switched capacitor is coupled with an input end of the operational amplifier; and a feedback switched capacitor, wherein an end of the feedback switched capacitor is coupled with the input end of the operational amplifier, and another end of the feedback switched capacitor is coupled with an output end of the operational amplifier. 
     Optionally, the signal conversion circuit further includes an input switch, configured to control the input switched capacitor to access the signal conversion circuit or not; and a feedback switch, configured to control the feedback switched capacitor to access the signal conversion circuit or not. 
     Optionally, an equivalent impedance of the input switched capacitor and/or an equivalent impedance of the feedback switched capacitor are related to an output characteristic of the sensing array. 
     Optionally, the signal output by the sensing array comprises an electric signal selected from different kinds of electric signal. 
     Optionally, the signal output by the sensing array comprises a charge signal, a current signal or a voltage signal. 
     Optionally, the input switched capacitor comprises a first switch and a first capacitor, the first switch is configured to adjust an equivalent impedance of the input switched capacitor. 
     Optionally, the feedback switched capacitor comprises a second capacitor and a second switch connected in parallel, and a third switch connected with the second capacitor and the second switch, the second switch and the third switch are configured to adjust an equivalent impedance of the feedback switched capacitor. 
     Optionally, the sensing array comprises a passive pixel structure and outputs a charge signal, the input switch is configured to control the input switched capacitor to be short-circuited, the feedback switch is turned off, the second switch is turned off, and the third switch is turned on. 
     Optionally, the sensing array comprises a passive pixel structure and outputs a current signal, the input switch is configured to control the input switched capacitor to be short-circuited, the feedback switch is turned off, the second switch and the third switch of the feedback switched capacitor are controlled by a clock pulse signal having a first frequency, and a phase of the clock pulse signal of the second switch is opposite to a phase of the clock pulse signal of the third switch. 
     Optionally, the sensing array comprises an active pixel structure and outputs a current signal, the input switch is configured to control the input switched capacitor to be short-circuited, the feedback switch is turned off, the second switch and the third switch of the feedback switched capacitor are controlled by a clock pulse signal having a second frequency, and a phase of the clock pulse signal of the second switch is opposite to a phase of the clock pulse signal of the third switch. 
     Optionally, the sensing array comprises an active pixel structure and outputs a voltage signal, the input switch is turned off and the first switch of the input switched capacitor is controlled by a clock pulse signal, the feedback switch is turned off and the second switch and the third switch of the feedback switched capacitor are controlled by a clock pulse signal, and a phase of the clock pulse signal of the second switch is opposite to a phase of the clock pulse signal of the third switch. 
     Optionally, the signal conversion circuit further includes a pulse signal module, wherein the pulse signal module is configured to generate the clock pulse signals. 
     Optionally, the signal conversion circuit further includes a pulse signal module, wherein the pulse signal module is configured to generate the clock pulse signals. 
     Optionally, the signal conversion circuit further includes a pulse signal module, wherein the pulse signal module is configured to generate the clock pulse signals. 
     In an embodiment of the present disclosure, a signal readout circuit is provided, including: a plurality of readout branches, wherein each of the plurality of readout branches includes: the above signal conversion circuit. 
     Optionally, the signal readout circuit further includes a multiplexer module, configured to multiplex and output a plurality of output signals of a sensing array. 
     Optionally, the signal readout circuit further includes a sampling module, configured to perform correlated double sampling on an output signal of the signal conversion circuits and output an analog sampled signal. 
     Optionally, the signal readout circuit further includes an analog-to-digital conversion module, configured to convert the analog sampled signal output by the sampling module into a digital signal. 
     Optionally, the signal readout circuit further includes a pulse signal module, configured to output clock pulse signals with different frequencies to the signal conversion circuits to adjust equivalent impedance of the signal conversion circuits. 
     Optionally, the sensing array is disposed in a TFT image sensor. 
     Compared with existing techniques, embodiments of the present disclosure have following advantages. 
     Embodiments of the present disclosure provide a signal conversion circuit, including: an operational amplifier, configured to amplify an electric signal output by a sensing array; an input switched capacitor, wherein an end of the input switched capacitor is configured to receive the electric signal output by the sensing array, and another end of the input switched capacitor is coupled to an input end of the operational amplifier; a feedback switched capacitor, wherein an end of the feedback switched capacitor is coupled to the input end of the operational amplifier, and another end of the feedback switched capacitor is coupled to an output end of the operational amplifier. The electric signal output by the sensing array may be various, for example, may include a charge signal, a current signal or a voltage signal, and an equivalent impedance of the input switched capacitor and/or an equivalent impedance of the feedback switched capacitor are related to output characteristics of the sensing array. The signal conversion circuit includes the switched capacitor with an equivalent impedance, and the signal conversion circuit may adopt different conversion modes according to different signals output by the sensing array, so that the signal readout circuit can be applied to different sensing arrays. Therefore, when the sensing array is replaced or different sensing arrays are developed in system applications, the signal readout circuit can use the same operational amplifier, and it is only necessary to adjust other circuit elements according to the different sensing arrays, without redesigning and manufacturing the signal readout circuit, which may greatly reduce development time and cost of system products. 
     Further, a signal readout circuit is provided according to embodiments, which includes the pulse signal module that outputs pulse signals with different frequencies to the signal conversion circuit to adjust equivalent impedance of the signal conversion circuit. Therefore, the signal readout circuit can change component values in a wide range without increasing area cost, so that signals within a large range output by the sensing array can be processed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically illustrates a structural diagram of a signal readout circuit in existing techniques; 
         FIG. 2  schematically illustrates a structural diagram of a signal readout circuit according to an embodiment; 
         FIG. 3  schematically illustrates a diagram of a signal conversion circuit in a first conversion mode according to an embodiment; 
         FIG. 4  schematically illustrates a diagram of a signal conversion circuit in a second conversion mode according to an embodiment; 
         FIG. 5  schematically illustrates a diagram of a signal conversion circuit in a third conversion mode according to an embodiment; and 
         FIG. 6  schematically illustrates a diagram of a signal conversion circuit in a fourth conversion mode according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 ,  FIG. 1  schematically illustrates a structural diagram of a signal readout circuit in existing techniques. 
     The signal readout circuit as shown in  FIG. 1  includes a plurality of readout branches which are configured to read signals output by a sensing array. Each readout branch includes a signal conversion module (structures in a dashed box in  FIG. 1 ) which includes an operational amplifier and a variable capacitor. The signal conversion module reads a charge signal output from the sensing array and a current signal within a certain time through the variable capacitor, and converts the charge signal and the current signal into a voltage for subsequent correlated double sampling and analog-to-digital conversion. 
     However, corresponding external signal readout circuits need to be designed to process signals output by different sensing arrays, as each signal readout circuit has a single purpose and cannot be used universally. If an output signal of the sensing array is a voltage signal, the signal readout circuit shown in  FIG. 1  cannot read the output signal. In addition, with the signal readout circuit shown in  FIG. 1 , although capacitance of capacitors in the signal conversion module can be adjusted, however, when a current changes by more than dozens of times, signals cannot be processed by using the same signal readout circuit, and different signal readout circuits need to be developed for different sensing arrays, which may increase cost in design, manufacturing and management. 
     Referring to  FIG. 2 ,  FIG. 2  schematically illustrates a structural diagram of a signal readout circuit according to an embodiment. 
     As shown in  FIG. 2 , the signal readout circuit  200  is configured to read an electric signal output by a sensing array  100 . The signal readout circuit  200  includes a plurality of readout branches for reading signals of rows and columns in the sensing array  100  respectively. Each readout branch includes a multiplexer module ( 11 - 1   n ), a signal conversion circuit ( 21 - 2   n ), a sampling module ( 31 - 3   n ) and an analog-to-digital conversion module ( 41 - 4   n ). In some embodiments, the signal readout circuit  200  further includes a pulse signal module  20 . 
     In some embodiments, the multiplexer modules ( 11 - 1   n ) are used to multiplex and output multiple output signals of the sensing array, thereby reducing the number of pins of a chip and design complexity of the chip. The signal conversion circuits ( 21 - 2   n ) are configured to convert charge signals, current signals or voltage signals output by the sensing array into voltage signals to be output. The sampling modules ( 31 - 3   n ) perform correlated double sampling on output signals of the signal conversion circuit, and output analog sampled signals. By performing correlated double sampling on the signals output from the sensing array, interference of reset noises may be eliminated, and low-frequency noises may be suppressed. Therefore, a signal-to-noise ratio may be significantly improved, and signal detection accuracy may be improved, thereby improving quality of images acquired by an image sensor. The analog-to-digital conversion modules ( 41 - 4   n ) are configured to convert the analog sampled signals into digital signals to facilitate subsequent image processing. 
     In some embodiments, the pulse signal module  20  is configured to output clock pulse signals with different frequencies to the signal conversion circuits ( 21 - 2   n ) to adjust equivalent impedance of the signal conversion circuits. In some embodiments, the pulse signal module  20  outputs clock pulse signals with different frequencies to the signal conversion circuits ( 21 - 2   n ) according to different signals output by the sensing array. 
     In some embodiments, the multiplexer modules ( 11 - 1   n ), the sampling modules ( 31 - 3   n ), the analog-to-digital conversion modules ( 41 - 4   n ) and the pulse signal modules  20  may adopt different structures, which is not limited in embodiments of the present disclosure. 
     It should be noted that  FIG. 2  is merely an example of the signal readout circuit. The signal readout circuit provided in embodiments of the present disclosure may not only include the above-mentioned modules as shown in  FIG. 2 . In some embodiments, the signal readout circuit  200  may further include other modules such as a shift register to perform corresponding data and signal processing. 
     In some embodiments, the sensing array is disposed in a Thin Film Transistor (TFT) sensor. The TFT sensor may be fabricated on a glass or a flexible plate, so that a relatively large fabrication area can be obtained. 
       FIG. 3  is taken as an example to specifically describe a structure of the signal conversion circuit. 
     The signal conversion circuit includes: an operational amplifier AMP, configured to amplify an electric signal output by a sensing array; an input switched capacitor  211 , wherein one end of the input switched capacitor  211  is configured to receive the electric signal output by the sensing array, and the other end of the input switched capacitor  211  is coupled to an input end of the operational amplifier AMP; a feedback switched capacitor  212 , wherein one end of the feedback switched capacitor  212  is coupled to the input end of the operational amplifier AMP, and the other end of the feedback switched capacitor  212  is coupled to an output end of the operational amplifier AMP; an input switch S 1 , configured to control the input switched capacitor  211  to access the signal conversion circuit or not; and a feedback switch S 3 , configured to control the feedback switched capacitor  212  to access the signal conversion circuit or not, wherein the electric signal output by the sensing array includes a charge signal, a current signal or a voltage signal, and equivalent impedance of the input switched capacitor  211  and/or the equivalent impedance of the feedback switched capacitor  212  are related to output characteristics of the sensing array. 
     In some embodiments, the input switch S 1  is connected in parallel with the input switched capacitor  211 , and the feedback switch S 3  is connected in parallel with the feedback switched capacitor  212 . 
     In some embodiments, the input switched capacitor  211  includes a first switch S 3  and a first capacitor C 1  connected in series. In some embodiments, the first switch S 3  receives clock pulse signals. The pulse signal module outputs pulse signals with different frequencies to adjust equivalent impedance of the input switched capacitor  211 . 
     In some embodiments, the feedback switched capacitor  212  includes a second capacitor C 2  and a second switch S 5  connected in parallel, and a third switch S 4  connected in series with the second capacitor C 2  and the second switch S 5  connected in parallel. In some embodiments, similar to the first switch S 3 , the second switch S 5  and the third switch S 4  receive clock pulse signals. The pulse signal module outputs pulse signals with different frequencies to adjust equivalent impedance of the feedback switched capacitor  212 . 
     Structures and states of the signal conversion circuit in different modes are described below with reference to  FIGS. 3 to 6 . 
     Referring to  FIG. 3 ,  FIG. 3  schematically illustrates a diagram of a signal conversion circuit in a first conversion mode according to an embodiment. 
     In some embodiments, the sensing array has a passive pixel structure and outputs a charge signal. In this case, the signal conversion circuit is in the first conversion mode. Under the first conversion mode, the input switch S 1  is turned on, to control the input switched capacitor  211  to be short-circuited; the feedback switch S 3  is turned off, the second switch S 5  is turned off, and the third switch S 4  is turned on. 
     When in the first conversion mode, the signal conversion circuit is equivalent to an integration circuit, and the second capacitor C 2  is a capacitor of a femtofarad (fF) to picofarad (pF) level. In some embodiments, the second capacitor C 2  receives a charge signal and outputs a voltage signal. 
     Referring to  FIG. 4 ,  FIG. 4  schematically illustrates a diagram of a signal conversion circuit in a second conversion mode according to an embodiment. 
     In some embodiments, the sensing array has a passive pixel structure and outputs a current signal. In this case, the signal conversion circuit is in the second conversion mode. Under the second conversion mode, the input switch S 1  is turned on to control the input switched capacitor  211  to be short-circuited; the feedback switch S 3  is turned off, the second switch S 5  and the third switch S 4  of the feedback switched capacitor  212  are controlled by a clock pulse signal CLK with a first frequency f 1 , and a phase of the clock pulse signal CLK of the second switch S 5  is opposite to a phase of the clock pulse signal CLK of the third switch S 4 . 
     When in the second conversion mode, the feedback switched capacitor  212  is equivalent to a resistor whose equivalent resistance is inversely proportional to a product of the first frequency f 1  and capacitance of the second capacitor C 2 . In some embodiments, the equivalent resistance is within a range from 1 kΩ to 100 MΩ. The second capacitor C 2  receives a current signal and outputs a voltage signal. 
     Referring to  FIG. 5 ,  FIG. 5  schematically illustrates a diagram of a signal conversion circuit in a third conversion mode according to an embodiment. 
     In some embodiments, the sensing array has an active pixel structure and outputs a current signal. In this case, the signal conversion circuit is in the third conversion mode. Under the third conversion mode, the input switch S 1  is turned on to control the input switched capacitor  211  to be short-circuited; the feedback switch S 3  is turned off, the second switch S 5  and the third switch S 4  of the feedback switched capacitor  212  are controlled by a clock pulse signal CLK with a second frequency f 2 , and a phase of the clock pulse signal CLK of the second switch S 5  is opposite to a phase of the clock pulse signal CLK of the third switch S 4 . 
     When in the third conversion mode, the feedback switched capacitor  212  is equivalent to a resistor whose equivalent resistance is inversely proportional to a product of the second frequency f 2  and capacitance of the second capacitor C 2 . In some embodiments, the equivalent resistance is within a range from 1 kΩ to 100 MΩ. The second capacitor C 2  receives a current signal and outputs a voltage signal. 
     Different from the second conversion mode, in the third conversion mode, the sensing array has an active pixel structure. Generally, the sensing array of the active pixel structure amplifies the output current signal. Therefore, compared with the signal conversion circuit in the second conversion mode, an amplitude of a current signal received by the signal conversion circuit in the third conversion mode is larger. Therefore, the second frequency f 2  is higher than the first frequency f 1 , and the feedback switched capacitor  212  in the third conversion mode can obtain higher equivalent resistance, so as to process a current signal with a larger amplitude. 
     Referring to  FIG. 6 ,  FIG. 6  schematically illustrates a diagram of a signal conversion circuit in a fourth conversion mode according to an embodiment. 
     In some embodiments, the sensing array includes a source follower. Therefore, an electric signal output by the sensing array is a voltage signal. In this case, the input switch S 1  is turned off, and the first switch S 2  of the input switched capacitor  211  is controlled by the clock pulse signal CLK; the feedback switch S 3  is turned off, the second switch S 5  and the third switch S 4  of the feedback switched capacitor  212  are controlled by the clock pulse signal CLK, and a phase of the clock pulse signal of the second switch is opposite to a phase of the clock pulse signal of the third switch. In some embodiments, the clock pulse signal applied to the first switch S 2  has a third frequency f 3 , and the clock pulse signal applied to the second switch S 5  and the third switch S 4  has a fourth frequency f 4 . 
     When in the fourth conversion mode, the input switched capacitor  211  and the feedback switched capacitor  212  are both equivalent to a resistor. Equivalent resistance R 1  of the input switched capacitor  211  is inversely proportional to a product of the third frequency f 3  and capacitance of the first capacitor C 1 , and equivalent resistance R 2  of the feedback switched capacitor  212  is inversely proportional to a product of the fourth frequency f 4  and capacitance of the second capacitor C 2 . In some embodiments, the equivalent resistance is within a range from 1 kΩ to 100 MΩ. In the fourth mode, the signal conversion circuit is equivalent to an inverting amplifier, receives a voltage signal, and outputs a voltage signal. 
     In some embodiments, a high-frequency clock pulse signal may be used as a fundamental frequency, and pulse signals with other frequencies may be generated by frequency division or by other means. The third frequency f 3  and the fourth frequency f 4  are controlled to adjust the first equivalent resistance R 1  and the second equivalent resistance R 2 , so as to adjust a gain of the signal conversion circuit. 
     Therefore, by controlling the on-off of the input switch S 1  and the feedback switch S 3  and the frequency of the clock pulse signal output by the pulse signal module, the conversion modes of the signal conversion circuit can be adjusted so that the signal readout circuit can be applied to different sensing arrays. In addition, different frequencies of the clock pulse signal can adjust the equivalent impedance of the input switched capacitor  211  and the equivalent impedance of the feedback switched capacitor  212 . Therefore, the signal readout circuit can change component values in a wide range without increasing area cost, so that signals within a large range output by the sensing array can be processed. 
     Although the present disclosure has been disclosed above with reference to preferred embodiments thereof, it should be understood that the disclosure is presented by way of example only, and not limitation. Those skilled in the art can modify and vary the embodiments without departing from the spirit and scope of the present disclosure.