Patent Publication Number: US-11641786-B2

Title: Memory device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application for patent Ser. No. 16/533,255, now U.S. Pat. No. 11,355,702, filed Aug. 6, 2019, which claims the priority benefit of French Application for Patent No. 1857389, filed on Aug. 8, 2018, the contents of which are hereby incorporated by reference in their entireties to the maximum extent allowable by law. 
    
    
     TECHNICAL FIELD 
     The present disclosure generally relates to memory devices, and more particularly to memories comprising a phase-change alloy made up of germanium, antimony, and tellurium. 
     BACKGROUND 
     Phase-change materials are materials which can switch, under the effect of heat, between a crystalline phase and an amorphous phase. Since the electric resistance of an amorphous material is significantly greater than the electric resistance of a crystalline material, such a phenomenon may be useful to define two memory states, for example, 0 and 1, differentiated by the resistance measured through the phase-change material. The most common phase-change materials in memories are alloys made up of germanium, antimony, and tellurium. 
     The usual phase-change memories are generally made of an alloy of germanium, of antimony and of tellurium in stoichiometric proportions, for example Ge 2 Sb 2 Te 5 . A problem is that such alloys are sensitive to temperature. Specifically, their crystallization temperature is too low to withstand the temperature range of the die soldering process, especially in the automotive industry. The welding temperature would cause the modification of the programmed data. 
     SUMMARY 
     An embodiment overcomes all or part of the disadvantages of known phase-change memories. 
     In an embodiment, a memory device comprises: a first phase-change memory cell; a second phase-change memory cell; wherein the first phase-change memory cell comprises a first alloy made up of germanium, antimony, and tellurium; and wherein the second phase-change memory cell comprises the first alloy and a second alloy made up of germanium, antimony, and tellurium 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which: 
         FIG.  1    shows a simplified cross-section view of an embodiment of a portion of a phase-change memory cell; 
         FIGS.  2 A- 2 B  show simplified cross-section views of two steps of manufacturing and potentially programming of the embodiment of  FIG.  1   ; 
         FIGS.  3 A- 3 B  schematically show cross-section views of an embodiment of a memory device before and after programming, respectively; 
         FIG.  4    schematically shows a cross-section view of another embodiment of a memory device; 
         FIG.  5    schematically shows an embodiment of a read-once memory. 
     
    
    
     DETAILED DESCRIPTION 
     Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties. 
     For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, the memory cells comprise elements which are not detailed, for example, selection elements, for example, transistors, or electric connections. 
     Throughout the present disclosure, the term “connected” is used to designate a direct electrical connection between circuit elements, whereas the term “coupled” is used to designate an electrical connection between circuit elements that may be direct, or may be via one or more intermediate elements. 
     In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., unless otherwise mentioned, it is referred to the orientation of the drawings. 
     The terms “approximately”, “substantially”, and “in the order of” are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question. The terms “close to” are used herein to designate a tolerance of plus or minus 35%. 
       FIG.  1    shows a simplified cross-section view of a portion of an embodiment of a phase-change memory cell  100 . 
     Memory cell  100  comprises a resistive element  102  connected to a selection element, for example, a transistor, not shown, via a conductive via  104 . Resistive element  102 , for example, has an L-shaped cross-section having its horizontal portion in contact with conductive via  104 . Resistive element  102  and conductive via  104  are surrounded with an insulating layer  106 . The thickness of layer  106  is such that the upper surface of the vertical portion of the resistive element is coplanar with the upper surface of insulating layer  106 . The selection element is located under layer  106 . 
     Memory cell  100  further comprises a stack  108  of layers resting on the upper surface of insulating layer  106  and on the upper surface of the vertical portion of resistive element  102 . A conductive layer  109  rests on stack  108 . Conductive layer  109  forms an electrode of the memory cell. 
     Stack  108  comprises layers  114  made of germanium or nitrogen doped germanium and layers  116  made of a first alloy of germanium, of antimony, and of tellurium. The layers of stack  108  are alternately layers  114  and layers  116 . 
     In the embodiment of  FIG.  1   , stack  108  comprises two germanium layers  114  and two layers  116  of the first alloy. The lower layer of stack  108  is, in this example, one of layers  116  and is located on the side of layer  106 . 
     The first alloy is a stable alloy, that is, the proportions of the various components are close to stoichiometric. The first alloy is for example Ge 2 Sb 2 Te 5 , Ge 4 Sb 4 Te 7  or an alloy made up of germanium, antimony and tellurium with atomic percentages close to the atomic percentages of Ge 2 Sb 2 Te 5  or Ge 4 Sb 4 Te 7 . The first alloy of layers  116  are preferably in a crystalline phase. Layers  114  are for example made of non-doped germanium or of germanium doped with nitrogen atoms. In the case of layers  114  in germanium doped with nitrogen atoms, the nitrogen content is preferably lower than 35% of the atomic count. The material of layers  114  is for example in an amorphous phase. 
     The layers of stack  108 , for example, have a thickness greater than approximately 4 nm, for example, in the range from 4 to 30 nm. Layers  114  and layers  116  may be of different thickness. 
     In some embodiment, the different layers  116  are made of different alloys of germanium, of antimony and of tellurium chosen among the example given previously for the first alloy. For example, the stack  108  may comprise a layer  114  of germanium situated between a layer  116  made of Ge 2 Sb 2 Te 5  and a layer  116  made of Ge 4 Sb 4 Te 7 . Those different alloys will nonetheless be referred to as the first alloy in the following description. 
     More generally, stack  108  comprises at least one germanium layer  114  and a layer  116  made of the first alloy, layer  116  covering layer  114 . Preferably, stack  108  comprises a layer  114  located between two layers  116  made of the first alloy. Stack  108  may comprise any number of layers, greater than two. The number of layers may be even or odd. Further, the lower layer of stack  108  may be a germanium layer  114  or a layer  116  made of the first alloy. 
       FIGS.  2 A- 2 B  show simplified cross-section views of two steps, respectively, illustrating the manufacturing and potentially the programming of the embodiment of  FIG.  1   . 
     Step a) shown in  FIG.  2 A  comprises the manufacturing steps executed in order to obtain the embodiment of  FIG.  1   . 
     Step a) comprises: —forming the selection element, not shown; —forming insulating layer  106 ; —forming conductive via  104 ; —forming resistive element  102 ; —forming stack  108  on the upper surface of insulating layer  106  and on the upper surface of the vertical portion of resistive element  102 . More specifically, layers  116  made of the first alloy and germanium layers  114  are alternately formed over the entire surface corresponding to the memory cell. In the embodiment of  FIG.  1   , the first layer, in contact with resistive element  102 , is a layer  116  made of the first alloy; and —forming conductive layer  109 , covering the upper layer of stack  108 . 
     As a variation, the layers of stack  108  may be by a different number and have a different layout, as described in relation with  FIG.  1   . However, stack  108  comprises at least one germanium layer  114  and one layer  116  made of the first alloy. 
     Step b) shown in  FIG.  2 B , following step a), can be considered either a manufacturing step or a programming step. Step b) comprises an electrical operation called “Forming”. During this operation, a high current pulse, typically higher than the pulses normally applied for programming memory cells, flows between conductive via  104  and conductive layer  109  and goes through resistive element  102  and stack  108 . 
     The resistive element  102  heats until a temperature, for example higher than 600° C., preferably higher than 900° C., able to melt a portion of the materials of layers  114  and  116 . This operation forms a portion  112  in a homogenous Ge-Rich alloy from the melted portions of layers  114  and  116 . Portion  112  is the active zone of the phase change memory. Preferably, the “Forming” operation is designed in such a way that portion  112  is in the crystalline phase at the end of the operation. 
     Second portion  112  rests on the upper surface of layer  106  and the upper surface of the vertical portion of resistive element  102 . Second portion  112  is thus in contact with resistive element  102 . Second portion  112  substantially has a cross-section in the shape of a half circle, or a circle portion, centered on the contact area between the second portion and resistive element  102 . 
     Portion  112  is made of a second alloy made of up germanium, antimony, and tellurium, the germanium concentration of the second alloy being greater than that of the first alloy. The second alloy is, like the first alloy, a phase-change material, such as what has been previously described. The proportions of the components of the second alloy are for example not stoichiometric. The proportion of germanium in the second alloy is for example between 1.5 times and 3.5 times the proportion of germanium in the first alloy. 
     The quantity of germanium in the second alloy depends on the quantity of germanium in the heated portions, that is, on the number and on the thickness of germanium layers  114 , as compared with the quantity of the first alloy. 
     The data written, or programmed, into the memory cell are determined by the amorphous or crystalline phase of at least part of second portion  112 . 
     The inventors have determined that the second alloy has a higher crystallization temperature of the amorphous phase than the first alloy. More specifically, the more germanium the second alloy comprises, the more the crystallization temperature increases. 
     The maximum welding temperatures (of the device of the integrated circuit chip) in its environment (generally on a printed circuit board) are approximately 150° C. and the maximum temperatures reached during the die soldering are approximately 260° C. Thus, memory cells having a crystallization temperature greater than 160° C. and the capacity to withstand temperatures greater than 200° C. for a few minutes, do not risk seeing their phase modified by the welding temperature. It is thus now possible to assemble programmed phase-change memory devices by welding, without losing the programmed data. 
     Another possibility would have been to directly deposit, during the manufacturing process, a layer of the second alloy instead of the stack  108 . However, as the second alloy does not correspond to any stable phase of the Ge—Sb—Te ternary phase diagram, it would tend to segregate into separate stable phases during the following steps of the manufacturing process. Indeed, during the manufacturing process, the second alloy would be exposed to thermal treatments, at relatively high temperatures, for example equal and above 380° C. Those temperatures would cause the crystallization and segregation of the second alloy. Consequently, although the second alloy is an amorphous and homogenous layer as deposited, at the end the end of the manufacturing process and before the “Forming” operation, it would be made of randomly distributed regions of separate stable phases. It would for example be regions of Ge and Ge 2 Sb 2 Te 7 , whose average sizes would depend on the thermal budget of the manufacturing process after the deposition of the layer made of the second alloy. 
     The “Forming” operation, as described in relation with  FIG.  2 B , would, afterward, create an active zone similar to the portion  112  shown in  FIG.  2 B . However, due to the random distribution, in location and size, of the regions, the local composition of the second alloy in the active zone would vary from cell to cell. This cell-to-cell variability of the alloy in the composition of the active zone would have a detectable impact on the distribution of cell parameters in the memory array. This impact would be all the more important that the cells have small critical dimensions. 
     An advantage of the embodiments described in relation with  FIGS.  1  and  2 A- 2 B  is that they do not face the segregation of the layer made of the second alloy, as the materials of the layers already have stoechiometric proportions. Consequently, all memory cells fabricated by the same method with the same number of layers having the same thicknesses, and exposed, simultaneously or separately, to the same current pulse during the “Forming” operation are substantially identical. Such memory cells thus have a substantially identical operation. This remains true when the dimensions of the memory cells decrease. 
       FIGS.  3 A- 3 B  schematically and partially show cross-section views of an embodiment of a memory device  300  before and after programming, respectively. 
     Before programming (structure shown in  FIG.  3 A ), memory device  300  only comprises cells  301  similar to the memory cells described in relation with  FIG.  1   . 
     After the programming of the memory cells (structure shown in  FIG.  3 B ), memory device  300  comprises cells  301  and cells  302  corresponding to the structures obtained after the programming method described in relation with  FIG.  2 B . Memory device  300  may comprise any number of memory cells  302  and any number of memory cells  301 , independently from the number of memory cells  302 . In the example of  FIGS.  3 A- 3 B , only one memory cell  302  and one memory cell  301  are shown after programming. 
     Cells  301  and  302  respectively correspond to a first and to a second logic state. For example, cells  301  correspond to state “0” and cells  302  correspond to state “1”. 
     The programming of the memory cells comprises the “Forming” operation. The memory cells  301  where the second logic state is desired to be stored receive a current sufficiently high to cause the “Forming” operation described in relation with  FIG.  2 B  and thus to form cells  302 . Typically, an array of memory cells  301 , some of which are heated to form cells  302 , is used. 
     The temperature of the “Forming” operation being for example selected to be greater than the welding temperature used, the welding will cause no modification in the values programmed in the memory. 
       FIG.  4    schematically shows a cross-section view of an embodiment of a memory device  400 . Device  400  comprises the same elements as device  300 , with the difference that device  400  comprises an insulating region  402  separating the stack  108  of adjacent cells from one another. Regions  402  enable to avoid for the state of a cell to interfere with the resistance measurement of the neighboring cells. 
     The previously-described memory devices  300  and  400  are one-time programmable (OTP) memory devices. Specifically, the “Forming” operation comprised in the programming of the embodiment of  FIGS.  3 A- 3 B and  4    is a one-time-only operation that modifies the structure of the memory cell  100  in an un-reversible way, locally destroying the layered structure. This one-time-only operation is used to pre-program, at wafer level before die assembly, a code in the whole phase change memory device or in part of it; this code will be retained after soldering. Furthermore, cells  302  are phase change memory cells and their phases can be switched between amorphous and crystalline to program a logic state. If needed, the cells  301  can go through the “Forming” operation after die assembly and soldering to become cells  302 . 
     Several types of memory devices can be made using the embodiments described: a) a read-only memory device, in which the programming is done by the “Forming” operation during the manufacturing process; b) a one-time-only memory device, in which the programming, meaning the “Forming” operation, is done after a packaging operation, for example by the user; c) a phase change memory device, in which the cells can be reprogrammed by the user by changing the phase of the active zone; and d) a memory device comprising a combination of devices as described above, formed on a same chip by the same manufacturing process, differentiated by the electrical operations. For example, a chip comprising a phase change memory may also comprise read-only memory cells for memory array repairing data, code ROM for the memory controller, manufacturing codes, boot memory, etc. 
     In the case of a phase change memory device (c), some data may be preprogrammed in the memory using the “Forming” operation, as in the case of read-only memory devices and of one-time-only memory device. The data that require to be programmed at wafer level are typically the repairing data, the manufactoring codes, the code ROM of the controller of the phase change memory, any engineering data that must be stored in the device for history tracking purposes. Such preprogrammation would allow the data stored in the memory device to withstand the soldering process. The cells of the phase change memory device (c), the ones used by the user as an erasable programmable memory, would all go through the “Forming” operation at wafer level, during the manufactoring process in order to become reprogrammable phase change memory cells. In summary, the cells that need to be preprogrammed to a logic “0” do not go through the “Forming” operation at wafer level. 
     In embodiments which are described, the crystallization temperature of the second alloy does not need to be as high as it would if the data was preprogrammed without using the “Forming” operation. Consequently, the second alloy may avantageously comprise less germanium than it would if the data was preprogrammed without using the “Forming” operation. Indeed, it has been discovered that increasing the proportion of germanium in an alloy of germanium, antimony and tellurium increases the crystallization temperature but also increases a “Set Drift” phenomenon. 
     The “Set Drift” phenomenon is the increase of the resistance of an alloy in a crystalline phase (set state), caused by high temperatures. The “set drift” phenomenon is negligible in alloys of germanium, of antimony and of tellurium having stoichiometric proportions, but has a significant impact in alloys rich in germanium, like the second alloy. The “Set Drift” phenomenon is detrimental in a phase change memory because it reduces the difference between the resistances of the two phases and can cause mistakes in the reading of the memory. A similar phenomenon exists for the amorphous phase (reset state), however the increase of the amorphous phase resistance is not detrimental because it widens the resistance difference between the two states of the cell. 
     Thus it is advantageous to be able to withstand die soldering while avoiding the “Set Drift” phenomenon. 
       FIG.  5    schematically shows an embodiment of a memory  500 . 
     Memory  500  comprises: one or a plurality of memory devices, such as devices a), b), c) or d) previously described, and shown in  FIG.  5    by a block  502  (OTP). Block  502  also includes a circuit for addressing the array of memory cells; a data processing unit, represented by a block  504  (PU), for example, a microprocessor; one or a plurality of memory devices, represented by a block  506  (MEM), and which may be memory devices different from those of block  502 . For example, it is possible for the memory devices of block  506  not to be phase-change memory devices but to be RAMs, reprogrammable volatile memories (EEPROM, flash, etc.), or to be phase-change memory devices which cannot be welded. The memory devices of block  506  are for example added to memory  500  after the welding steps; a block  508  (FCT) comprising other electronic functions, for example, sensors, load control circuits, etc.; and a data bus  510  enabling to transfer data between the different components. 
     As a variation, block  506  may be omitted. The memory devices of the memory are then only memory devices such as memory devices  300  and  400 . The memory is then entirely a read-only memory. 
     Various embodiments and variations have been described. It will readily occur to those skilled in the art that certain characteristics of these various embodiments and variations may be combined, and other various will occur to those skilled in the art. In particular, although the method described in relation with  FIG.  2    only concerns the forming of a memory cell, it should be understood that it is adapted to the simultaneous forming of a larger number of memory cells. 
     Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove.