Patent Publication Number: US-2019172841-A1

Title: Semiconductor integrated circuit device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of International Application No. PCT/JP2017/26298 filed on Jul. 20, 2017, which claims priority to Japanese Patent Application No. 2016-155878 filed on Aug. 8, 2016. The entire disclosures of these applications are incorporated by reference herein. 
     BACKGROUND 
     The present disclosure relates to a semiconductor integrated circuit device including a standard cell including a nanowire field effect transistor (FET). 
     A standard cell design has been known as a method of forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell design refers to a method of designing a large-scale integrated circuit (LSI) chip by providing in advance, as standard cells, unit logic elements having particular logical functions (for example, an inverter, a latch, a flip-flop, and a full adder), laying out those standard cells on a semiconductor substrate, and connecting those standard cells together through an interconnect. 
     Reducing a gate length (scaling) of transistors that are a basic element of the LSI have achieved more integrated transistors, reduced an operating voltage, and improved an operating rate. However, recently, off-current has been increased due to excessive scaling, and power has been consumed more and more due to the increase in off-current, which are problems. In order to solve such problems, three-dimensional transistors having a three-dimensional structure to which a change is made from a conventional two-dimensional structure have been actively researched. As one technique, nanowire FETs draw attention. 
     Examples of a method for manufacturing nanowire FETs are disclosed in S. Bangsaruntip, et al. “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling”, Electron Devices Meeting (IEDM), 2009 IEEE International and Isaac Laucer, et al. “Si Nanowire CMOS Fabricated with Minimal Deviation from RMG Fin FET Technology Showing Record Performance”, 2015 Symposium on VLSI Technology Digest of Technical Papers. 
     SUMMARY 
     So far, neither a structure of a standard cell with a nanowire FET nor a layout of a semiconductor integrated circuit device including such a nanowire FET has been specifically studied. 
     The present disclosure relates to a semiconductor integrated circuit device including a nanowire FET, and provides a layout configuration effective for making manufacturing the device easy. 
     According to a first aspect of the present disclosure, a semiconductor integrated circuit includes a standard cell including first and second transistors that are nanowire field effect transistors (FETs), the first and second transistors being connected in series through a connection node used only for mutual connection. The first and second transistors include: a first pad; Na (Na is an integer of one or more) first nanowires each having a first end that is connected to the first pad, each extending in a first direction from the first end, and each having a lower surface above a lower surface of the first pad; a first gate electrode surrounding peripheries of the first nanowires within predetermined ranges of the first nanowires in the first direction; a second pad connected to second ends of the first nanowires; Nb (Nb is an integer of one or more) second nanowires each having a first end that is connected to the second pad, each extending in the first direction from the first end, and each having a lower surface above a lower surface of the second pad; a second gate electrode surrounding peripheries of the second nanowires within predetermined ranges of the second nanowires in the first direction; and a third pad connected to second ends of the second nanowires. 
     In accordance with this aspect, the second pad is provided between the first and second nanowires each constituting the connection node used only for connection between the first and second transistors, and the first and second nanowires are connected to this second pad. This configuration allows the second pad to support the first and second nanowires, and can improve the structural strength of the nanowire FETs. Consequently, process-induced variations in the semiconductor integrated circuit device can be reduced, and yield and reliability can be improved. 
     According to a second aspect of the present disclosure, a semiconductor integrated circuit includes: a standard cell including first and second transistors that are nanowire field effect transistors (FETs). The first and second transistors include: a first pad; Na (Na is an integer of one or more) first nanowires each having a first end that is connected to the first pad, each extending in a first direction from the first end, and each having a lower surface above a lower surface of the first pad; a first gate electrode surrounding peripheries of the first nanowires within predetermined ranges of the first nanowires in the first direction; a second pad connected to second ends of the first nanowires; Nb (Nb is an integer of one or more) second nanowires each having a first end that is connected to the second pad, each extending in the first direction from the first end, and each having a lower surface above a lower surface of the second pad; a second gate electrode surrounding peripheries of the second nanowires within predetermined ranges of the second nanowires in the first direction; and a third pad connected to second ends of the second nanowires. The second pad is not connected to any interconnect other than the first and second nanowires. 
     In accordance with this aspect, the second pad that is not connected to any interconnect other than the first and second nanowires is provided between the first nanowires forming part of the first transistor and the second nanowires forming part of the second transistor. In other words, the second pad that is not required to allow the circuit to function is provided. Provision of such a second pad allows the first and second nanowires to be supported, and can improve the structural strength of the nanowire FETs. Consequently, process-induced variations in the semiconductor integrated circuit device can be reduced, and yield and reliability can be improved. 
     According to a third aspect of the present disclosure, a semiconductor integrated circuit includes: a standard cell that is a NAND gate or a NOR gate having a serial portion including M (M is an integer of two or more) nanowire field effect transistors (FETs). The M nanowire FETs include: M+1 pads arranged at a predetermined pitch in a first direction; M groups of nanowires each including L (L is an integer of 1 or more) nanowires that are each provided between adjacent ones of the pads, extend in the first direction to connect the adjacent ones of the pads together, and each have a lower surface above lower surfaces of the pads; and M gate electrodes surrounding peripheries of the associated nanowires within predetermined ranges of the associated nanowires in the first direction. 
     In accordance with this aspect, in the serial portion of the standard cell that is the NAND gate or the NOR gate, the pads are provided between the adjacent nanowire FETs. Provision of such pads allows the nanowires provided between the adjacent pads to be supported, and can improve the structural strength of the nanowire FETs. Consequently, process-induced variations in the semiconductor integrated circuit device can be reduced, and yield and reliability can be improved. 
     The present disclosure makes it easy to manufacture a semiconductor integrated circuit device including a nanowire FET, can reduce process-induced variations in the semiconductor integrated circuit device, and can improve yield. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan view of a configuration example of a standard cell including nanowire field effect transistors (FETs) according to a first embodiment; 
         FIG. 2  is a circuit diagram of the standard cell of  FIG. 1 ; 
         FIG. 3  is a cross-sectional view of the standard cell of  FIG. 1 ; 
         FIG. 4  is a cross-sectional view of the standard cell of  FIG. 1 ; 
         FIG. 5  is a plan view of another configuration example of the standard cell according to the first embodiment; 
         FIG. 6  is a circuit diagram of the standard cell of  FIG. 5 ; 
         FIG. 7  is a plan view of a configuration example of a standard cell including nanowire FETs according to a second embodiment; 
         FIG. 8  is a circuit diagram of the standard cell of  FIG. 7 ; 
         FIG. 9  is a plan view of another configuration example of the standard cell according to the second embodiment; 
         FIG. 10  is a plan view of still another configuration example of the standard cell according to the second embodiment; 
         FIG. 11  is a plan view of yet another configuration example of the standard cell according to the second embodiment; 
         FIG. 12  is a plan view of a further configuration example of the standard cell according to the second embodiment; 
         FIG. 13  is a plan view of a further configuration example of the standard cell according to the second embodiment; 
         FIG. 14  is a plan view of a further configuration example of the standard cell according to the second embodiment; 
         FIG. 15  shows a variation of the layout configuration of the standard cell of  FIG. 1 ; 
         FIG. 16  schematically illustrates a basic configuration for the nanowire FET; and 
         FIG. 17  schematically illustrates a basic configuration for the nanowire FET. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments will be described with reference to the drawings. In the following description of the embodiment, it is assumed that a semiconductor integrated circuit device includes a plurality of standard cells, at least some of which include a nanowire field effect transistor (FET). 
       FIG. 16  is a schematic diagram of a basic structure example of the nanowire FET (also referred to as a nanowire gate all around (GAA) FET). The nanowire FET is an FET including thin wires (nanowires) through each of which a current flows. The nanowires are made of, e.g., silicon. As illustrated in  FIG. 16 , the nanowires are formed so as to extend horizontally above a substrate, i.e., extend parallel to the substrate, and each have both ends respectively connected to elements serving as source and drain regions of the nanowire FET. In this specification, in a nanowire FET, elements connected to both ends of a nanowire and serving as source and drain regions of the nanowire FET are each called a pad. In  FIG. 16 , a shallow trench isolation (STI) is formed on a Si substrate. However, the Si substrate is exposed in an (hatched) area under the nanowire. The hatched area may actually be covered with, e.g., a thermal oxide film. In  FIG. 16 , such a film is omitted for the sake of simplicity. 
     The nanowire is surrounded by a gate electrode comprised of, e.g., polysilicon via an insulating film such as a silicon oxide film. The pads and the gate electrode are formed on the substrate surface. With this configuration, all of upper, lower, and both side portions of a channel region of the nanowire are surrounded by the gate electrode, and thus, the electric field is evenly applied to the channel region, thus improving switching characteristics of the FET. 
     Although at least portions of the pads connected to the nanowire serve as the source/drain regions, portions of the pads below the portions connected to the nanowire do not necessarily serve as the source/drain regions. Portions of the nanowire (portions thereof not surrounded by the gate electrode) may serve as the source/drain regions. 
     In  FIG. 16 , two nanowires are arranged in the vertical direction, i.e., a direction perpendicular to the substrate. However, the number of the nanowires arranged in the vertical direction is not limited to two. Alternatively, one, three, or more nanowires may be arranged in the vertical direction. In  FIG. 16 , the upper end of the uppermost nanowire is at the same height as the upper end of the pad. However, the upper ends of these components do not necessarily have to be at the height, and the upper ends of the pads may be situated above the upper end of the uppermost nanowire. 
     As shown in  FIG. 17 , in some cases, a buried oxide (BOX) is formed on the upper surface of the substrate, and the nanowire FET is formed on the BOX. 
     First Embodiment 
       FIG. 1  is a plan view of a layout configuration example of a standard cell included in a semiconductor integrated circuit device according to a first embodiment. The standard cell  1  shown in  FIG. 1  constitutes a 2-input NOR gate shown in the circuit diagram of  FIG. 2  using nanowire FETs. In  FIG. 1 , the lateral direction on the paper is an X direction (corresponding to a first direction), and the longitudinal direction on the paper is a Y direction (corresponding to a second direction). 
     The standard cell  1  shown in  FIG. 1  includes four nanowire FETs. That is to say, in the standard cell  1 , a p-type transistor region PA and an-n-type transistor region NA are arranged in the Y direction, the p-type transistor region PA is provided with p-type nanowire FETs P 11  and P 12 , and the n-type transistor region NA is provided with n-type nanowire FETs N 11  and N 12 . As shown in the circuit diagram of  FIG. 2 , the nanowire FET P 11  as a first transistor and the nanowire FET P 12  as a second transistor are connected in series, and the nanowire FETs N 11  and N 12  are connected in parallel. In the standard cell  1  shown in  FIG. 1 , the nanowire FETs P 11  and P 12  connected in series constitute a serial portion P 1 . 
     The nanowire FETs P 11 , P 12 , N 11 , and N 12  include a group of a plurality of parallelly arranged nanowires  11 , a group of a plurality of parallelly arranged nanowires  12 , a group of a plurality of parallelly arranged nanowires  13 , and a group of a plurality of parallelly arranged nanowires  14 , respectively. The nanowires  11 ,  12 ,  13 ,  14  extend in the X direction. Here, the groups of nanowires  11 ,  12 ,  13 ,  14  each include four nanowires arranged in the Y direction. As will be described below, the groups of nanowires  11 ,  12 ,  13 ,  14  further each include two nanowires arranged in the vertical direction, i.e., the direction perpendicular to the substrate, and each include eight nanowires in total. Each of the nanowires  11 ,  12 ,  13 ,  14  has a cylindrical shape, extends horizontally above the substrate, i.e., extends parallel to the substrate, and is comprised of, e.g., silicon. The standard cell  1  is provided with pads  21 ,  22 , . . . ,  26  each connected to associated ones of the nanowires  11 ,  12 ,  13 ,  14 . P-type impurities are introduced into at least portions of the pads  21 ,  22 ,  23  connected to the associated nanowires  11 ,  12  and serving as source/drain regions of the nanowire FETs P 11  and P 12 . N-type impurities are introduced into at least portions of the pads  24 ,  25 ,  26  connected to the associated nanowires  13 ,  14  and serving as source/drain regions of the nanowire FETs N 11  and N 12 . 
     Here, the groups of the pads  21 ,  22 ,  23 ,  24 ,  25 ,  26  each include four pads separately arranged in the Y direction. The pads  21  are each connected to an associated one of the four nanowires  11  arranged in the Y direction. The pads  22  are each connected to an associated one of the four nanowires  11  arranged in the Y direction, and are each connected to an associated one of the four nanowires  12  arranged in the Y direction. The pads  23  are each connected to an associated one of the four nanowires  12  arranged in the Y direction. The pads  24  are each connected to an associated one of the four nanowires  13  arranged in the Y direction. The pads  25  are each connected to an associated one of the four nanowires  13  arranged in the Y direction, and are each connected to an associated one of the four nanowires  14  arranged in the Y direction. The pads  26  are each connected to an associated one of the four nanowires  14  arranged in the Y direction. 
     The nanowire FETs P 11  and P 12  connected together in series share the pads  22 . That is to say, the nanowire FET P 11  includes the pads  21  as first pads and the pads  22  as second pads. These pads  21 ,  22  are connected to the associated nanowires  11  as first nanowires. Similarly, the nanowire FET P 12  includes the pads  22  and the pads  23  as third pads. These pads  22 ,  23  are connected to the associated nanowires  12  as second nanowires. The nanowire FETs N 11  and N 12  connected together in parallel share the pads  25 . That is to say, the nanowire FET N 11  includes the pads  24 ,  25  connected to the associated nanowires  13 , and the nanowire FET N 12  includes the pads  25 ,  26  connected to the associated nanowires  14 . 
     The standard cell  1  is provided with two gate lines  31  and  32  which extend linearly along the Y direction. The gate line  31  is comprised of, as the first gate electrodes, a gate electrode  31   p  of the nanowire FET P 11  and a gate electrode  31   n  of the nanowire FET N 11 , which are integrally formed with each other, and surrounds peripheries of the nanowires  11 ,  13  within predetermined ranges of the nanowires  11 ,  13  in the X direction. The gate line  32  is comprised of, as the second gate electrodes, a gate electrode  32   p  of the nanowire FET P 12  and a gate electrode  32   n  of the nanowire FET N 12 , which are integrally formed with each other, and surrounds peripheries of the nanowires  12 ,  14  within predetermined ranges of the nanowires  12 ,  14  in the X direction. Lateral sides of a cell frame CF of the standard cell  1  are respectively provided with dummy gate lines  35  and  36  extending along the Y direction. 
     A metal interconnect layer M 1  is formed above the nanowire FETs P 11 , P 12 , N 11 , and N 12 . The metal interconnect layer M 1  includes an interconnect VDD disposed on the upper side of the cell frame CF and supplying a power supply potential, and an interconnect VSS disposed on the lower side of the cell frame CF and supplying a ground potential. The metal interconnect layer M 1  further includes interconnects  41   a,    41   b,  . . . ,  41   f.  The interconnect  41   a  is formed so as to extend downward from the interconnect VDD along the Y direction, and is connected to the pads  21  through a local interconnect  45   a.  The interconnect  41   b  is formed so as to extend upward from the interconnect VSS along the Y direction, and is connected to the pads  24  through a local interconnect  45   b.  The interconnect  41   c  is formed so as to extend upward from the interconnect VSS along the Y direction, and is connected to the pads  26  through a local interconnect  45   c.  The interconnect  41   d  connects the pads  23 ,  25  together, and is connected to the pads  23  through a local interconnect  45   d,  and is connected to the pads  25  through a local interconnect  45   e.  The interconnect  41   e  is connected to the gate line  31  through a local interconnect  45   f.  The interconnect  41   f  is connected to the gate line  32  through a local interconnect  45   g.  The interconnects  41   d,    41   e,  and  41   f  respectively correspond to an output Y, an input A, and an input B in the  2 -input NOR circuit. A local interconnect  45   h  is disposed on the pads  22 . Although the local interconnect  45   h  is connected to the pads  22 , it is not connected to any interconnect of the metal interconnect layer M 1 . 
     The metallic interconnects  41   a  to  41   f  are each connected to an associated one or ones of the pads  21 ,  23 ,  24 ,  25 ,  26  and the gate lines  31  and  32  through associated ones of the local interconnects  45   a,    45   b,    45   c,    45   d,    45   e,    45   f,  and  45   g  and contacts  43 . Alternatively, the metallic interconnects may be connected to the pads and the gate lines only through the local interconnects, not through the contacts, or may be connected to the pads and the gate lines only through the contacts, not through the local interconnects. 
       FIG. 3  is a cross-sectional view taken along line D-D′ of the layout configuration of  FIG. 1 , and  FIG. 4  is a cross-sectional view taken along line E-E′ of the layout configuration of  FIG. 1 . As shown in  FIGS. 3 and 4 , the interconnects  41   a  to  41   f  of the metal interconnect layer M 1  are respectively connected to the local interconnects  45   a  to  45   g  through contacts  43 . 
     The contacts  43  are formed together with the interconnects  41   a  to  41   f  of the metal interconnect layer M 1  using a dual-damascene process. The contacts  43  may be formed separately from the interconnects  41   a  to  41   f  of the metal interconnect layer M 1 . The interconnects  41   a  to  41   f  of the metal interconnect layer M 1  are made of, e.g., Cu, and have a surface on which a barrier metal  48  including, e.g., tantalum or tantalum nitride is formed. The local interconnects  45   a  to  45   h  are made of, e.g., tungsten, and have a surface on which a glue film  47  including, e.g., titanium or titanium nitride is formed. The local interconnects  45   a  to  45   h  may be made of cobalt. In this case, the glue film  47  may be omitted. The pads  21  to  26  have a surface on which a silicide film  49  made of, e.g., nickel or cobalt is formed. 
     Interlayer insulating films  46   a  and  46   b  are each, e.g., a silicon oxide film. An interlayer insulating film  46   c  is a low dielectric constant film such as SiOC or a porous film. The interlayer insulating film  46   c  may have a multilayer structure including two or more layers. 
     The gate electrodes  31   p,    31   n,    32   p,  and  32   n  are made of, e.g., polysilicon. The gate electrodes  31   p,    31   n,    32   p,  and  32   n  may be made of a material including a metal such as titanium nitride. A gate insulating film is, e.g., a silicon oxide film, and is formed by, e.g., thermal oxidation. The gate insulating film may be formed of an oxide of hafnium, zirconium, lanthanum, yttrium, aluminum, titanium, or tantalum. 
     As can be seen from the cross-sectional views of  FIGS. 3 and 4 , the lower surfaces of the pads  21 ,  22 , . . . ,  26  are below those of the nanowires  11 ,  12 ,  13 ,  14 . The upper surfaces of the groups of the nanowires  11 ,  12 ,  13 ,  14  are at the same height as those of the pads  21 ,  22 , . . . ,  26 . The gate electrodes  31   p,    32   p,    31   n,  and  32   n  surround peripheries of the nanowires  11 ,  12 ,  13 ,  14 , respectively. That is to say, all of upper, lower, and both side surfaces of a channel region of each of the nanowires  11 ,  12 ,  13 ,  14  are surrounded by an associated one of the gate electrodes  31   p,    32   p,    31   n,  and  32   n  through the associated insulating film. The upper surfaces of the groups of the nanowires  11 ,  12 ,  13 ,  14  may be below the upper surfaces of the pads  21 ,  22 ,  23 ,  24 ,  25 ,  26 . A buried oxide (BOX) may be formed on the upper surface of the substrate. 
     In the standard cell  1  of  FIG. 1 , the pads are arranged at an equal pitch Pp in the X direction. That is to say, the pads  21 ,  22 ,  23  are arranged in the p-type transistor region PA at the pitch Pp, and the pads  24 ,  25 ,  26  are arranged in the n-type transistor region NA at the pitch Pp. The pads in the p-type transistor region PA and the associated pads in the n-type transistor region NA have the same position in the X direction. That is to say, the pads  21  and the associated pads  24  have the same position in the X direction. Similarly, the pads  22  and the pads  25  have the same position in the X direction, and the pads  23  and the pads  26  have the same position in the X direction. Dimensions in the X direction of the pads, i.e., the pad widths Wp, are all equal, and the intervals between the adjacent pads in the X direction, i.e., the pad intervals Sp, are all equal. Therefore, the following relation is satisfied: 
     
       
      
       Pp=Wp+Sp  
      
     
     In each of the p-type transistor region PA and the n-type transistor region NA, the pads are connected together in the X direction through the associated nanowires. Consequently, the length Wn of each of the nanowires is equal to the pad interval Sp. That is to say, the following relation is satisfied: 
     
       
      
       Wn=Sp  
      
     
     The lengths Wn of the nanowires  11 ,  12 ,  13 ,  14  are all equal. 
     An interval between the cell frame CF and the center line of each of the pads  21 ,  23 ,  24 ,  26  closest to the cell frame CF is ½ of the pitch Pp between the pads. As a result, the dimension in the X direction of the standard cell  1 , i.e., a cell width Wcell, is an integral multiple of the pitch Pp between the pads (in this embodiment, three times the pitch Pp). 
     In the standard cell  1  of  FIG. 1 , the gate lines (including the dummy gate lines) are arranged at an equal pitch Pg in the X direction. Dimensions in the X direction of the gate lines, i.e., the gate line widths Wg, are all equal, and the intervals between the gate lines in the X direction, i.e., the intervals Sg, are all equal. Therefore, the following relation is satisfied: 
     
       
      
       Pg=Wg+Sg  
      
     
     A pitch Pg between the gate lines is equal to the pitch Pp between the pads. That is to say, the following relation is satisfied: 
     
       
      
       Pp=Pg  
      
     
     The layout configuration of  FIG. 1  has the following features. 
     In the p-type transistor region PA, the nanowire FETs P 11  and P 12  constituting the serial portion P 1  are connected together through an intermediate node  10 . This intermediate node  10  is a node used only for connection between the nanowire FETs P 11  and P 12 . That is to say, elements, power supply interconnects, and signal interconnects other than the nanowire FETs P 11  and P 12  are not directly connected to the intermediate node  10 . Consequently, there is no need to provide pads between the nanowire FETs P 11  and P 12  (see the dot and dash line of  FIG. 3 ). 
     In the present embodiment, the pads  22  are provided at intermediate positions of the nanowires constituting the intermediate node  10 , i.e., positions corresponding to portions of the nanowires between the gate electrodes  31   p  and  32   p.  The nanowires  11 ,  12  forming part of the nanowire FETs P 11  and P 12  are connected to the associated pads  22 . This configuration can substantially prevent the nanowires within the standard cell from having different lengths. Further, the pads  22  can support the nanowires  11 ,  12 , and improve the structural strength of the nanowire FETs. This can reduce process-induced variations in the semiconductor integrated circuit device including the standard cell according to the present embodiment, and can improve yield and reliability. 
     Another Example 
       FIG. 5  is a plan view of a layout configuration example of the standard cell included in the semiconductor integrated circuit device according to the first embodiment. The standard cell  2  shown in  FIG. 5  constitutes a three-input NAND gate shown in the circuit diagram of  FIG. 6  using nanowire FETs. In  FIG. 5 , just like in  FIG. 1 , the lateral direction on the paper is the X direction (corresponding to the first direction), and the longitudinal direction on the paper is the Y direction (corresponding to the second direction). The cross-sectional structure of the standard cell is similar to that shown in  FIGS. 3 and 4 , and is not shown here. 
     The standard cell  2  shown in  FIG. 5  includes six nanowire FETs. That is to say, the standard cell  2  includes the p-type transistor region PA and the n-type transistor region NA arranged in the Y direction. The p-type transistor region PA is provided with p-type nanowire FETs P 21 , P 22 , and P 23 , and the n-type transistor region NA is provided with n-type nanowire FETs N 21 , N 22 , and N 23 . As shown in the circuit diagram of  FIG. 6 , the nanowire FETs P 21 , P 22 , and P 23  are connected in parallel, and the nanowire FETs N 21 , N 22 , and N 23  are connected in series. In the standard cell  2  shown in  FIG. 5 , the nanowire FETs N 21 , N 22 , and N 23  connected in series constitute a serial portion N 2 . 
     The nanowire FETs P 21 , P 22 , P 23 , N 21 , N 22 , and N 23  include a group of a plurality of parallelly arranged nanowires  51 , a group of a plurality of parallelly arranged nanowires  52 , . . . , and a group of a plurality of parallelly arranged nanowires  56 , respectively. The nanowires  51 ,  52 , . . . ,  56  extend in the X direction. Here, the groups of nanowires  51 ,  52 ,  53 ,  54 ,  55 ,  56  each include three nanowires arranged in the Y direction. The groups of nanowires  51 ,  52 ,  53 ,  54 ,  55 ,  56  further each include two nanowires arranged in the vertical direction, i.e., the direction perpendicular to the substrate. The groups of nanowires  51 ,  52 ,  53 ,  54 ,  55 ,  56  each include six nanowires in total. Each of the nanowires  51 ,  52 , . . . ,  56  has a cylindrical shape, extends horizontally above the substrate, i.e., extends parallel to the substrate, and is comprised of, e.g., silicon. The standard cell  2  is provided with pads  61 ,  62 , . . . ,  68  connected to associated ones of the nanowires  51 ,  52 , . . . ,  56 . P-type impurities are introduced into at least portions of the pads  61 ,  62 ,  63 ,  64  connected to the nanowires  51 ,  52 ,  53  and serving as source/drain regions of the nanowire FETs P 21 , P 22 , and P 23 . N-type impurities are introduced into at least portions of the pads  65 ,  66 ,  67 ,  68  connected to the nanowires  54 ,  55 ,  56  and serving as source/drain regions of the nanowire FETs N 21 , N 22 , and N 23 . 
     Here, the groups of the pads  61 ,  62 ,  63 ,  64 ,  65 ,  66 ,  67 ,  68  each include three pads separately arranged in the Y direction. The separately arranged three pads  61  are each connected to an associated one of the three nanowires  51  arranged in the Y direction. The separately arranged three pads  62  are each connected to an associated one of the three nanowires  51  arranged in the Y direction, and are each connected to an associated one of the three nanowires  52  arranged in the Y direction. The separately arranged three pads  63  are each connected to an associated one of the three nanowires  52  arranged in the Y direction, and are each connected to an associated one of the three nanowires  53  arranged in the Y direction. The separately arranged three pads  64  are each connected to an associated one of the three nanowires  53  arranged in the Y direction. The separately arranged three pads  65  are each connected to an associated one of the three nanowires  54  arranged in the Y direction. The separately arranged three pads  66  are each connected to an associated one of the three nanowires  54  arranged in the Y direction, and are each connected to an associated one of the three nanowires  55  arranged in the Y direction. The separately arranged three pads  67  are each connected to an associated one of the three nanowires  55  arranged in the Y direction, and are each connected to an associated one of the three nanowires  56  arranged in the Y direction. The separately arranged three pads  68  are each connected to an associated one of the three nanowires  56  arranged in the Y direction. 
     The nanowire FETs P 21  and P 22  connected in parallel share the pads  62 , and the nanowire FETs P 22  and P 23  connected in parallel share the pads  63 . That is to say, the nanowire FET P 21  includes the pads  61 ,  62  connected to the associated nanowires  51 , the nanowire FET P 22  includes the pads  62 ,  63  connected to the associated nanowires  52 , and the nanowire FET P 23  includes the pads  63 ,  64  connected to the associated nanowires  53 . The nanowire FETs N 21  and N 22  connected in series share the pads  66 , and the nanowire FETs N 22  and N 23  connected in series share the pads  67 . That is to say, the nanowire FET N 21  includes the pads  65 ,  66  connected to the associated nanowires  54 , the nanowire FET N 22  includes the pads  66 ,  67  connected to the associated nanowires  55 , and the nanowire FET N 23  includes the pads  67 ,  68  connected to the associated nanowires  56 . 
     The standard cell  2  is provided with three gate lines  71 ,  72 , and  73  extending in the Y direction. The gate line  71  is comprised of a gate electrode  71   p  of the nanowire FET P 21  and a gate electrode  71   n  of the nanowire FET N 21 , which are integrally formed with each other, and surrounds peripheries of the nanowires  51 ,  54  within predetermined ranges of the nanowires  51 ,  54  in the X direction. The gate line  72  is comprised of a gate electrode  72   p  of the nanowire FET P 22  and a gate electrode  72   n  of the nanowire FET N 22 , which are integrally formed with each other, and surrounds peripheries of the nanowires  52 ,  55  within predetermined ranges of the nanowires  52 ,  55  in the X direction. The gate line  73  is comprised of a gate electrode  73   p  of the nanowire FET P 23  and a gate electrode  73   n  of the nanowire FET N 23 , which are integrally formed with each other, and surrounds peripheries of the nanowires  53 ,  56  within predetermined ranges of the nanowires  53 ,  56  in the X direction. Lateral sides of a cell frame CF of the standard cell  2  are respectively provided with dummy gate lines  75  and  76  extending in the Y direction. 
     The metal interconnect layer M 1  is formed above the nanowire FETs P 21 , P 22 , P 23 , N 21 , N 22 , and N 23 . The metal interconnect layer M 1  includes an interconnect VDD disposed on the upper side of the cell frame CF and supplying a power supply potential, and an interconnect VSS disposed on the lower side of the cell frame CF and supplying a ground potential. The metal interconnect layer M 1  further includes interconnects  81   a  to  81   g.  The interconnect  81   a  is formed so as to extend downward from the interconnect VDD along the Y direction, and is connected to the pads  61  through a local interconnect  85   a.  The interconnect  81   b  is formed so as to extend downward from the interconnect VDD along the Y direction, and is connected to the pads  63  through a local interconnect  85   b.  The interconnect  81   c  is formed so as to extend upward from the interconnect VSS along the Y direction, and is connected to the pads  65  through a local interconnect  85   c.  The interconnect  81   d  connects the pads  62 ,  64 ,  68  together, and is connected to the pads  62  through a local interconnect  85   d,  is connected to the pads  64  through a local interconnect  85   e,  and is connected to the pads  68  through a local interconnect  85   f.  The interconnect  81   e  is connected to the gate line  71  through a local interconnect  85   g.  The interconnect  81   f  is connected to the gate line  72  through a local interconnect  85   h.  The interconnect  81   g  is connected to the gate line  73  through a local interconnect  85   i.  The interconnects  81   d,    81   e,    81   f,  and  81   g  respectively correspond to an output Y, an input A, an input B, and an input C in the three-input NAND circuit. A local interconnect  85   j  is disposed on the pads  66 , and a local interconnect  85   k  is disposed on the pads  67 . Although the local interconnect  85   j  is connected to the pads  66 , it is not connected to any interconnect of the metal interconnect layer M 1 . Although the local interconnect  85   k  is connected to the pads  67 , it is not connected to any interconnect of the metal interconnect layer M 1 . 
     The metallic interconnects  81   a,    81   b,    81   c,    81   d,    81   e,    81   f,  and  81   g  are each connected to an associated one or ones of the pads  61 ,  62 ,  63 ,  64 ,  65 ,  68  and the gate lines  71 ,  72 , and  73  through associated ones of the local interconnects  85   a,    85   b,    85   c,    85   d,    85   e,    85   f,    85   g,    85   h,  and  85   i  and contacts  83 . Alternatively, the metallic interconnects may be connected to the pads and the gate lines only through the local interconnects, not through the contacts, or may be connected to the pads and the gate lines only through the contacts, not through the local interconnects. 
     The cross-sectional structure of the standard cell  2  is similar to that of the standard cell  1 . That is to say, the lower surfaces of the pads  61 ,  62 , . . . ,  68  are below the lower surfaces of the nanowires  51 ,  52 , . . . ,  56 . The upper surfaces of the nanowires  51 ,  52 , . . . ,  56  are at the same height as the upper surfaces of the pads  61 ,  62 , . . . ,  68 . The gate electrodes  71   p ,  72   p,    73   p,    71   n,    72   n,  and  73   n  surround the peripheries of the nanowires  51 ,  52 , . . . ,  56 . That is to say, all of upper, both side, and lower surfaces of the channel regions of the nanowires  51 ,  52 , . . . ,  56  are each surrounded by an associated one of the gate electrodes  71   p,    72   p,    73   p,    71   n ,  72   n,  and  73   n  through an associated one of the insulating films. The upper surfaces of the nanowires  51 ,  52 , . . . ,  56  may be below the upper surfaces of the pads  61 ,  62 , . . . ,  68 . 
     In the standard cell  2  of  FIG. 5 , the pads are arranged at an equal pitch Pp in the X direction. That is to say, the pads  61 ,  62 ,  63 ,  64  are arranged in the p-type transistor region PA at the pitch Pp, and the pads  65 ,  66 ,  67 ,  68  are arranged in the n-type transistor region NA at the pitch Pp. The pads in the p-type transistor region PA and the associated pads in the n-type transistor region NA have the same position in the X direction. That is to say, the pads  61  and the associated pads  65  have the same position in the X direction. Similarly, the pads  62  and the pads  66  have the same position in the X direction, the pads  63  and the associated pads  67  have the same position in the X direction, and the pads  64  and the associated pads  68  have the same position in the X direction. The widths Wp of the pads are all equal, and the pad intervals Sp in the X direction are all equal. Therefore, the following relation is satisfied: 
     
       
      
       Pp=Wp+Sp  
      
     
     In each of the p-type transistor region PA and the n-type transistor region NA, the pads are connected together in the X direction through the associated nanowires. Consequently, the length Wn of the nanowires is equal to the pad interval Sp. That is to say, the following relation is satisfied: 
     
       
      
       Wn=Sp  
      
     
     The lengths Wn of the nanowires  51 ,  52 , . . . ,  56  are all equal. 
     An interval between the cell frame CF and the center line of each of the pads  61 ,  64 ,  65 ,  68  closest to the cell frame CF is ½ of the pitch Pp between the pads. As a result, the cell width Wcell of the standard cell  2  is an integral multiple of the pitch Pp between the pads (in this embodiment, four times the pitch Pp). 
     In the standard cell  2  of  FIG. 5 , the gate lines (including the dummy gate lines) are arranged at an equal pitch Pg in the X direction. The widths Wg of the gate lines are all equal, and the pad intervals Sg in the X direction are all equal. Therefore, the following relation is satisfied: 
     
       
      
       Pg=Wg+Sg  
      
     
     A pitch Pg between the gate lines is equal to the pitch Pp between the pads. That is to say, the following relation is satisfied: 
     
       
      
       Pp=Pg  
      
     
     In the configuration of  FIG. 5 , among the nanowire FETs N 21 , N 22 , and N 23  constituting the serial portion N 2  in the n-type transistor region NA, the nanowire FETs N 21  and N 22  are connected together through an intermediate node  20   a,  and the nanowire FETs N 22  and N 23  are connected together through an intermediate node  20   b.  The intermediate node  20   a  is a node used only for connection between the nanowire FETs N 21  and N 22 , and the intermediate node  20   b  is a node used only for connection between the nanowire FETs N 22  and N 23 . That is to say, elements, power supply interconnects, and signal interconnects other than the nanowire FETs N 21  and N 22  are not directly connected to the intermediate node  20   a . Similarly, elements, power supply interconnects, and signal interconnects other than the nanowire FETs N 22  and N 23  are not directly connected to the intermediate node  20   b . Consequently, there is no need to provide pads between the nanowire FETs N 21  and N 22  and between the nanowire FETs N 22  and N 23 . 
     In the configuration of  FIG. 5 , just like in the configuration of  FIG. 1 , the pads  66  are provided at intermediate positions of the nanowires constituting the intermediate node  20   a,  i.e., positions corresponding to portions of the nanowires between the gate electrodes  71   n  and  72   n . Similarly, the pads  67  are provided at intermediate positions of the nanowires constituting the intermediate node  20   b,  i.e., positions corresponding to portions of the nanowires between the gate electrodes  72   n  and  73   n.  The nanowires  54 ,  55  forming part of the nanowire FETs N 21  and N 22  are connected to the associated pads  66 . The nanowires  55 ,  56  forming part of the nanowire FETs N 22  and N 23  are connected to the associated pads  67 . 
     This configuration can substantially prevent the nanowires within the standard cell from having different lengths. Further, the pads  66 ,  67  can support the nanowires  54 ,  55 ,  56 , and improve structural strength of the nanowire FETs. This can reduce process-induced variations in the semiconductor integrated circuit device and can improve yield and reliability. 
     In the configuration of  FIG. 5 , in the standard cell of the three-input NAND gate of  FIG. 6 , M (M is an integer of 2 or more, M=3 in  FIG. 5 ) nanowire FETs N 21 , N 22 , and N 23  constituting the serial portion N 2  include (M+1) groups of pads  65 ,  66 ,  67 ,  68  arranged at a predetermined pitch in the X direction, M groups of nanowires  54 ,  55 ,  56  each provided between adjacent ones of the groups of the pads, and M gate electrodes  71   n,    72   n,  and  73   n  surrounding the peripheries of the groups of the nanowires. The M groups of the nanowires  54 ,  55 ,  56  each include a total of L (L is an integer of 1 or more, L=6 in  FIG. 5 ) nanowires that extend in the X direction to connect the adjacent pads together and have a lower surface above the lower surfaces of the pads. 
     Although, in the configuration of  FIG. 5 , M is equal to 3 and L is equal to 6, the values M and L do not have to be 3 and 6, respectively. A serial portion of a NOR gate may have a similar configuration. The M groups of the nanowires  54 ,  55 , and  56  may have the same length in the X direction. 
     Second Embodiment 
       FIG. 7  is a plan view illustrating a layout configuration example of a standard cell included in a semiconductor integrated circuit device according to the embodiment. The standard cell  3  shown in  FIG. 7  constitutes an inverter shown in the circuit diagram of  FIG. 8  using nanowire FETs. In  FIG. 7 , just like in  FIG. 1 , the lateral direction on the paper is an X direction (corresponding to a first direction), and the longitudinal direction on the paper is a Y direction (corresponding to a second direction). The cross-sectional structure of the standard cell is similar to that shown in  FIG. 3 , and is not shown here. 
     The standard cell  3  shown in  FIG. 7  includes four nanowire FETs. That is to say, in the standard cell  3 , a p-type transistor region PA and an n-type transistor region NA are arranged in the Y direction, the p-type transistor region PA is provided with p-type nanowire FETs P 31  and P 32 , and the n-type transistor region NA is provided with n-type nanowire FETs N 31  and N 32 . As shown in the circuit diagram of  FIG. 8 , the nanowire FETs P 31  and P 32  are connected in series, and the nanowire FETs N 31  and N 32  are connected in series. In the standard cell  3  shown in  FIG. 7 , the nanowire FETs P 31  and P 32  connected in series constitute a serial portion P 3 , and the nanowire FETs N 31  and N 32  connected in series constitute a serial portion N 3 . 
     The nanowire FETs P 31 , P 32 , N 31 , and N 32  include a group of a plurality of parallelly arranged nanowires  111 , a group of a plurality of parallelly arranged nanowires  112 , a group of a plurality of parallelly arranged nanowires  113 , and a group of a plurality of parallelly arranged nanowires  114 , respectively. The nanowires  111 ,  112 ,  113 ,  114  extend in the X direction. Here, the groups of nanowires  111 ,  112 ,  113 ,  114  each include four nanowires arranged in the Y direction. The groups of nanowires  111 ,  112 ,  113 ,  114  further each include two nanowires arranged in the vertical direction, i.e., the direction perpendicular to the substrate, and each include eight nanowires in total. Each of the nanowires  111 ,  112 ,  113 ,  114  has a cylindrical shape, extends horizontally above the substrate, i.e., parallel to the substrate, and is comprised of, e.g., silicon. The standard cell  3  is provided with pads  121 ,  122 , . . . ,  126  each connected to associated ones of the nanowires  111 ,  112 ,  113 ,  114 . P-type impurities are introduced into at least portions of the pads  121 ,  122 ,  123  connected to the associated nanowires  111 ,  112  and serving as source/drain regions of the nanowire FETs P 31  and P 32 . N-type impurities are introduced into at least portions of the pads  124 ,  125 ,  126  connected to the associated nanowires  113  and  114  and serving as source/drain regions of the nanowire FETs N 31  and N 32 . 
     Here, the groups of the pads  121 ,  122 ,  123 ,  124 ,  125 ,  126  each include four pads separately arranged in the Y direction. The pads  121  are each connected to an associated one of the four nanowires  111  arranged in the Y direction. The separately arranged four pads  122  are each connected to an associated one of the four nanowires  111  arranged in the Y direction, and are each connected to an associated one of the four nanowires  112  arranged in the Y direction. The separately arranged four pads  123  are each connected to an associated one of the four nanowires  112  arranged in the Y direction. The separately arranged four pads  124  are each connected to an associated one of the four nanowires  113  arranged in the Y direction. The separately arranged four pads  125  are each connected to an associated one of the four nanowires  113  arranged in the Y direction, and are each connected to an associated one of the four nanowires  114  arranged in the Y direction. The separately arranged four pads  126  are each connected to an associated one of the four nanowires  114  arranged in the Y direction. 
     The nanowire FETs P 31  and P 32  connected in series share the pads  122 , and the nanowire FETs N 31  and N 32  connected in series share the pads  125 . That is to say, the nanowire FET P 31  includes the pads  121  and  122  connected to the associated nanowires  111 , and the nanowire FET P 32  includes the pads  122  and  123  connected to the associated nanowires  112 . The nanowire FET N 31  includes the pads  124  and  125  connected to the associated nanowires  113 , and the nanowire FET N 32  includes the pads  125  and  126  connected to the associated nanowires  114 . 
     The standard cell  3  is provided with two gate lines  131  and  132  which extend linearly along the Y direction. The gate line  131  is comprised of a gate electrode  131   p  of the nanowire FET P 31  and a gate electrode  131   n  of the nanowire FET N 31 , which are integrally formed with each other, and surrounds peripheries of the nanowires  111 ,  113  within predetermined ranges of the nanowires  111 ,  113  in the X direction. The gate line  132  is comprised of a gate electrode  132   p  of the nanowire FET P 32  and a gate electrode  132   n  of the nanowire FET N 32 , which are integrally formed with each other, and surrounds peripheries of the nanowires  112 ,  114  within predetermined ranges of the nanowires  112 ,  114  in the X direction. Lateral sides of a cell frame CF of the standard cell  3  are respectively provided with dummy gate lines  135  and  136  extending along the Y direction. 
     The metal interconnect layer M 1  includes an interconnect VDD disposed on the upper side of the cell frame CF and supplying a power supply potential, and an interconnect VSS disposed on the lower side of the cell frame CF and supplying a ground potential. The metal interconnect layer M 1  further includes interconnects  141   a,    141   b,    141   c,  and  141   d.  The interconnect  141   a  is formed so as to extend downward from the interconnect VDD along the Y direction, and is connected to the pads  121  through a local interconnect  145   a.  The interconnect  141   b  connects the pads  123  and  126  together, is connected to the pads  123  through a local interconnect  145   b,  and is connected to the pads  126  through a local interconnect  145   c . The interconnect  141   c  is formed so as to extend upward from the interconnect VSS along the Y direction, and is connected to the pads  124  through a local interconnect  145   d.  The interconnect  141   d  connects the gate lines  131  and  132  together, is connected to the gate line  131  through a local interconnect  145   e,  and is connected to the gate line  132  through a local interconnect  145   f.  With this configuration, the same signal is input to the gate electrode  131   p  of the nanowire FET P 31  and the gate electrode  132   p  of the nanowire FET P 32 . Similarly, the same signal is input to the gate electrode  131   n  of the nanowire FET N 31  and the gate electrode  132   n  of the nanowire FET N 32 . The interconnects  141   b  and  141   d  respectively correspond to an output Y and an input A of the inverter constituted by the standard cell  3 . A local interconnect  145   g  is disposed on the pads  122 , and a local interconnect  145   h  is disposed on the pads  125 . Although the local interconnect  145   g  is connected to the pads  122 , it is not connected to any interconnect of the metal interconnect layer M 1 . Although the local interconnect  145   h  is connected to the pads  125 , it is not connected to any interconnect of the metal interconnect layer M 1 . 
     The metallic interconnects  141   a  to  141   d  are each connected to an associated one or ones of the pads  121 ,  123 ,  124 ,  126  and the gate lines  131  and  132  through associated ones of the local interconnects  145   a,    145   b,    145   c,    145   d,    145   e,  and  145   f  and contacts  143 . Alternatively, the metallic interconnects may be connected to the pads and the gate lines only through the local interconnects, not through the contacts, or may be connected to the pads and the gate lines only through the contacts, not through the local interconnects. 
     In the standard cell  3  of  FIG. 7 , just like in  FIG. 1 , the pads are arranged at the equal pitch Pp in the X direction. Dimensions in the X direction of the pads, i.e., the pad widths Wp, are all equal, and the intervals between the adjacent pads in the X direction, i.e., the pad intervals Sp, and the lengths Wn of the nanowires  111 ,  112 ,  113 ,  114  are all equal. 
     In the configuration of  FIG. 7 , in the p-type transistor region PA, the nanowire FETs P 31  and P 32  constituting the serial portion P 3  are connected together through an intermediate node  30   a.  This intermediate node  30   a  is a node used only for connection between the nanowire FETs P 31  and P 32 . That is to say, elements, power supply interconnects, and signal interconnects other than the nanowire FETs P 31  and P 32  are not directly connected to the intermediate node  30   a.  Consequently, there is no need to provide pads between the nanowire FETs P 31  and P 32 . Similarly, in the n-type transistor region NA, the nanowire FETs N 31  and N 32  constituting the serial portion N 3  are connected together through an intermediate node  30   b . This intermediate node  30   b  is a node used only for connection between the nanowire FETs N 31  and N 32 . That is to say, elements, power supply interconnects, and signal interconnects other than the nanowire FETs N 31  and N 32  are not directly connected to the intermediate node  30   b . Consequently, there is no need to provide pads between the nanowire FETs N 31  and N 32 . 
     In the present embodiment, the pads  122  are provided at intermediate positions of the nanowires constituting the intermediate node  30   a,  i.e., positions corresponding to portions of the nanowires between the gate electrodes  131   p  and  132   p.  The nanowires  111 ,  112  forming part of the nanowire FETs P 31  and P 32  are connected to the associated pads  122 . This configuration can substantially prevent the nanowires within the standard cell from having different lengths. Further, the pads  122  can support the nanowires  111 ,  112 , and improve the structural strength of the nanowire FETs. Similarly, the pads  125  are provided at intermediate positions of the nanowires constituting the intermediate node  30   b,  i.e., positions corresponding to portions of the nanowires between the gate electrodes  131   n  and  132   n.  The nanowires  113 ,  114  forming part of the nanowire FETs N 31  and N 32  are connected to the associated pads  125 . This configuration can substantially prevent the nanowires within the standard cell having different lengths. Further, the pads  125  can support the nanowires  113 ,  114 , and improve the structural strength of the nanowire FETs. This can reduce process-induced variations in the semiconductor integrated circuit device including the standard cell according to the present embodiment, and can improve yield and reliability. 
     Further, in the configuration of  FIG. 7 , in the p-type transistor region PA, the interconnect  141   d  is connected to the gate electrodes  131   p  and  132   p  of the nanowire FETs P 31  and P 32  constituting the serial portion P 3 , and the same input signal is given to these gate electrodes from the input A. The nanowire FETs P 31  and P 32  with the same input are thus connected in series, thus allowing the serial portion P 3  to achieve driving capability weaker than that of the nanowire FET P 31 . Similarly, in the n-type transistor region NA, the interconnect  141   d  is connected to the gate electrodes  131   n  and  132   n  of the nanowire FETs N 31  and N 32  constituting the serial portion N 3 , and the same input signal is given to these gate electrodes from the input A. This allows the serial portion N 3  to achieve driving capability weaker than that of the nanowire FET N 31 . 
     Although, in the configuration of  FIG. 7 , the number of the nanowires  111  constituting the nanowire FET P 31  and the number of the nanowires  112  constituting the nanowire FET P 32  are each eight, they are non-limiting examples, and may be each any number. For example, when the number of the nanowires  111  constituting the nanowire FET P 31  and the number of the nanowires  112  constituting the nanowire FET P 32  are each one, the configuration of  FIG. 7  can provide a transistor having driving capability still weaker than that of a nanowire FET having one nanowire, i.e., the least number of nanowires. Further, the configuration of  FIG. 7  allows the driving capability of the serial portion to be adjusted to a value unachievable by changing the number of the nanowires alone. For example, when the number of the nanowires  111  of the nanowire FET P 31  and the number of the nanowires  112  of the nanowire FET P 32  are both Nx (Nx is an odd number), the driving capability of the serial portion P 3  can be set to be about ½ of that of the nanowire FET P 31 . The same statement applies to the serial portion N 3 . 
     Although, in the configuration of  FIG. 7 , the p-type transistor region PA and the n-type transistor region NA are respectively provided with the serial portions P 3  and N 3  where the transistors with the same input are connected in series, this is a non-limiting example, and either one of the regions may be provided with the serial portion P 3  or N 3 . The number of the nanowire FETs with the same input connected in series and constituting the serial portion P 3  or N 3  is not limited to two, and three or more nanowire FETs with the same input may be connected in series. Further, the number of the nanowire FETs connected in series in the p-type transistor region PA may be different from that in the n-type transistor region NA. 
     Another Example 1 
       FIG. 9  shows another example of the standard cell in the present embodiment. The layout configuration of this standard cell  3 A of  FIG. 9  is basically similar to that of  FIG. 7 . Common components are denoted by the same reference characters, and a detailed description thereof may be omitted here. In  FIG. 9 , the number of the nanowires  113  of the nanowire FET N 31  is different from that of the nanowires  114  of the nanowire FET N 32   a,  where the nanowire FETs N 31  and N 32   a  constitute a serial portion N 3 , and the same input is given to the nanowire FETs N 31  and N 32   a.    
     In accordance with the configuration of  FIG. 7  described above, the number of the nanowires  113  of the nanowire FET N 31  and the number of the nanowires  114  of the nanowire FET N 32  are each eight, i.e., equal to each other. Consequently, the driving capability of the serial portion N 3  is set to be about 0.5 times the driving capability of the nanowire FET N 31 . Similarly, the number of the nanowires  111  of the nanowire FET P 31  and the number of the nanowires  112  of the nanowire FET P 32  are each eight, i.e., equal to each other, and the driving capability of the serial portion P 3  is set to be about 0.5 times the driving capability of the nanowire FET P 31 . 
     In the configuration of  FIG. 9 , the nanowire FET N 31  includes eight (four in the Y direction and two in the vertical direction) parallelly arranged nanowires  113  extending in the X direction, and the nanowire FET N 32   a  includes four (two in the Y direction and two in the vertical direction) parallelly arranged nanowires  114  extending in the X direction. Consequently, in accordance with the configuration of  FIG. 9 , the driving capability of the serial portion N 3  is set to be within a range of 0.25 to 0.5 times the driving capability of the nanowire FET N 31 . 
     As can be seen, in the configuration of  FIG. 9 , in the serial portion N 3 , the number of the nanowires  113  forming part of the nanowire FET N 31  and the number of the nanowires  114  forming part of the nanowire FET N 32   a  are made different from each other. Thus, if a plurality of nanowire FETs which are connected in series and to which the same input is given include different numbers of nanowires, the driving capability can be finely adjusted. 
     Although  FIG. 9  illustrates an example in which in the serial portion N 3 , the nanowire FETs include different numbers of nanowires, the number of the nanowires  111  forming part of the nanowire FET P 31  and the number of the nanowires  112  forming part of the nanowire FET P 32  may be made different from each other in the serial portion P 3 , in addition to the configuration of  FIG. 9  or in place of the modification from the configuration of  FIG. 7  to the configuration of  FIG. 9 . With this configuration, the driving capability of the serial portion P 3  can be finely adjusted. 
     Also in the configuration of  FIG. 9 , the number of the nanowire FETs constituting the serial portion, i.e., the nanowire FETs which are connected in series and to which the same input is given may be three or more, and some or all of these nanowire FETs connected in series may include different numbers of nanowires. In other words, in accordance with driving capability required for each of the serial portions N 3  and P 3 , the number of the nanowire FETs constituting the serial portion and the number of the nanowires constituting each of the nanowire FETs can each be set to be any number. 
     Another Example 2 
       FIG. 10  shows another example of the standard cell in the present embodiment. The layout configuration of this standard cell  3 B of  FIG. 10  is basically similar to that of each of  FIGS. 7 and 9 . Common components are denoted by the same reference characters, and a detailed description thereof may be omitted here. The standard cell  3 B of  FIG. 10  is provided with an n-type nanowire FET N 40  as a dummy transistor having no contribution to a logical operation of a circuit. 
     The nanowire FET N 40  includes dummy nanowires  114   a  and a dummy gate electrode  132   a.  The dummy nanowires  114   a  are provided between the group of the pads  125  and the group of the pads  126  so as to extend in the X direction in parallel with the nanowires  114 . The dummy gate electrode  132   a  surrounds peripheries of the dummy nanowires  114   a  within predetermined ranges of the dummy nanowires  114   a  in the X direction. Further, the dummy gate electrode  132   a  is connected to the interconnect VSS through the interconnect  141   c , an interconnect  141   e  extending in the X direction from an intermediate portion of the interconnect  141   c  in the Y direction, and the local interconnect  145   g.  That is to say, a gate of the nanowire FET N 40  is fixed to a ground potential. 
     The configuration of the standard cell  3 B is obtained by modifying the configuration of the standard cell  3  (refer to  FIG. 7 ) such that the gate electrode  132   n  of the nanowire FET N 32  is divided into two gate electrodes. The upper one of these two gate electrodes in the drawing is used as the gate electrode  132   n  of the nanowire FET N 32   a,  whereas the lower one of these two gate electrodes in the drawing is used as the dummy gate electrode  132   a,  which is fixed to a ground potential. That is to say, the dummy gate electrode  132   a  is arranged in the same straight line as, and on the lower side in the Y direction of, the gate electrode  132   n  of the nanowire FET N 32   a,  and is arranged separately from the gate electrode  132   n.    
     In accordance with the configuration of  FIG. 10 , for the nanowire FETs N 31  and N 32   a  arranged adjacent to each other on the same straight line in the X direction and including different numbers of nanowires, providing the nanowire FET N 40  as a dummy transistor allows the groups of pads  124 ,  125 ,  126  to have respective upper ends having the same position in the Y direction, and respective lower ends having the same position in the Y direction. Consequently, the semiconductor integrated circuit device is easily manufactured, and process-induced variations therein can be reduced, thus improving yield. 
     Although, in the configuration of  FIG. 10 , the pads  124 ,  125 ,  126  have respective upper ends having the same position in the Y direction, and respective lower ends having the same position in the Y direction, only either the upper or lower ends may have the same position, or neither of them may have the same position. 
     Another Example 3 
       FIG. 11  shows another example of the standard cell in the present embodiment. The layout configuration of this standard cell  3 C of  FIG. 11  is basically similar to that of the standard cell  3 A of  FIG. 9 . Common components are denoted by the same reference characters, and a detailed description thereof may be omitted here. In  FIG. 11 , the number of the nanowires  111  of the nanowire FET P 31  is different from that of the nanowires  112  of the nanowire FET P 32   a,  where the nanowire FETs P 31  and P 32   a  constitute a serial portion P 3 . 
     In the layout configuration of  FIG. 11 , the nanowire FET P 31  includes eight (four in the Y direction and two in the vertical direction) parallelly arranged nanowires  111  extending in the X direction, and the nanowire FET P 32   a  includes four (two in the Y direction and two in the vertical direction) parallelly arranged nanowires  112  extending in the X direction. Consequently, in accordance with the configuration of  FIG. 11 , the driving capability of the serial portion P 3  constituted by the nanowire FETs P 31  and P 32   a  is set to be within a range of 0.25 to 0.5 times the driving capability of the nanowire FET P 31 . 
     In the layout configuration of  FIG. 11 , in the nanowire FET P 32   a,  the arrangement range of the nanowires  112  is localized relative to the arrangement range of the pads  122  and  123  in the Y direction. Specifically, in  FIG. 11 , the nanowires  112  are localized on the lower side of the arrangement range of the pads  122 ,  123  in the Y direction, and the two nanowires  112  are aligned in the X direction with two lower ones of the nanowires  111  of the nanowire FET P 31  in the drawing. 
     As in  FIG. 9 , in the nanowire FET N 32   a,  the arrangement range of the nanowires  114  is localized relative to the arrangement range of the pads  125  and  126  in the Y direction. Specifically, in  FIG. 11 , the nanowires  114  are localized on the upper side of the arrangement range of the pads  125 ,  126  in the Y direction, and the two nanowires  114  are aligned in the X direction with two upper ones of the nanowires  113  of the nanowire FET N 31 . 
     Further, the nanowire FET P 32   a  includes a dummy gate electrode  132   b.  The dummy gate electrode  132   b  is disposed between the group of the pads  122  and the group of the pads  123  so as to be aligned with the gate electrode  132   p.  The dummy gate electrode  132   b  is separated from the gate electrode  132   p.  Similarly, the nanowire FET N 32   a  includes a dummy gate electrode  132   a.  The dummy gate electrode  132   a  is disposed between the group of the pads  125  and the group of the pads  126  so as to be as aligned with the gate electrode  132   n . The dummy gate electrode  132   a  is separated from the gate electrode  132   n.    
     In accordance with the configuration of  FIG. 11 , providing the dummy gate electrodes  132   a  and  132   b  allows, in the standard cell  3 C, the gate lines of the nanowire FETs arranged adjacent to each other on the same straight line in the X direction and including different numbers of nanowires to have respective upper ends aligned in the X direction, and respective lower ends aligned in the X direction. With this configuration, the semiconductor integrated circuit device is easily manufactured, and process-induced variations therein can be reduced, thus improving yield. 
     In the layout configuration of  FIG. 11 , the dummy gate electrodes  132   a  and  132   b  are not necessarily provided, or only either one of them may be provided. 
     Although, in the configuration of  FIG. 11 , the nanowire FETs P 31  and N 31  each include eight nanowires, and the nanowire FETs P 32   a  and N 32   a  each include four nanowires, this is a non-limiting example. The p-type nanowire FET and the n-type nanowire FET may include different numbers of nanowires. 
     Although, in the configuration of  FIG. 11 , the nanowires  112  of the nanowire FET P 32   a  are each aligned with an associated one of the nanowires  111  of the nanowire FET P 31  in the X direction, they are not necessarily aligned with each other. Although the nanowires  114  of the nanowire FET N 32   a  are each aligned with an associated one of the nanowires  113  of the nanowire FET N 31  in the X direction, they are not necessarily aligned with each other. 
     Another Example 4 
       FIG. 12  shows another example of the standard cell in the present embodiment. The layout configuration of this standard cell  3 D of  FIG. 12  is basically similar to that of  FIG. 7 . Common components are denoted by the same reference characters, and a detailed description thereof may be omitted here. In  FIG. 12 , a p-type nanowire FET P 41  and an n-type nanowire FET N 41  as dummy transistors having no contribution to a logical operation of the circuit are provided. 
     In the configuration of  FIG. 12 , nanowire FETs P 32   b  and N 32   b  each include six (three in the Y direction and two in the vertical direction) parallelly arranged nanowires  112 ,  114  extending in the X direction. With this configuration, the driving capability of the serial portion P 3  including the nanowire FETs P 31  and P 32   b  is set to be within a range of 0.25 to 0.5 times the driving capability of the nanowire FET P 31 , and is set to be different from that of the configurations shown in  FIGS. 1 to 11 . Similarly, the driving capability of the serial portion N 3  including the nanowire FETs N 31  and N 32   b  is set to be within a range of 0.25 to 0.5 times the driving capability of the nanowire FET N 31 , and is set to be different from that of the configurations shown in  FIGS. 1 to 11 . 
     The nanowire FET P 41  includes a group of dummy nanowires  112   b  and a dummy pad  123   a.  The dummy pad  123   a  is disposed adjacent to the upper side of the group of pads  123  in the Y direction. The group of dummy nanowires  112   b  includes two (one in the Y direction and two in the vertical direction) nanowires arranged between the group of the pads  122  and the dummy pad  123   a  in parallel with the nanowires  112  to extend in the X direction. The gate line  132  extends so as to cross the arrangement position of the dummy nanowire  112   b  in the Y direction and surrounds peripheries of the dummy nanowires  112   b.  That is to say, a dummy gate electrode  132   d  of the nanowire FET P 41  is formed integrally with the gate electrode  132   p  of the nanowire FET P 32   b.    
     The nanowire FET N 41  includes a group of dummy nanowires  114   b  and a dummy pad  126   a.  The dummy pad  126   a  is disposed adjacent to the lower side of the group of pads  126  in the Y direction. The group of dummy nanowires  114   b  includes two (one in the Y direction and two in the vertical direction) nanowires arranged between the group of the pads  125  and the dummy pad  126   a  in parallel with the nanowires  114  to extend in the X direction. The gate line  132  extends so as to cross the arrangement position of the dummy nanowires  114   b  in the Y direction and surrounds peripheries of the dummy nanowires  114   b.  That is to say, a dummy gate electrode  132   c  of the nanowire FET N 41  is formed integrally with the gate electrode  132   n  of the nanowire FET N 32   b.    
     That is to say, the configuration of the standard cell  3 D is obtained by modifying the configuration of the standard cell  3  (refer to  FIG. 7 ) such that the pads  123  are classified under two groups in the nanowire FET P 32 , and the pads  126  are classified under two groups in the nanowire FET N 32 . 
     In accordance with the configuration of  FIG. 12 , for the nanowire FETs P 31  and P 32   b  arranged adjacent to each other in the same straight line in the X direction and including different numbers of nanowires, providing the nanowire FET P 41  as a dummy transistor allows the groups of the pads  121 ,  122  of the nanowire FET P 31  to each have an upper end having the same position as that of a region surrounding the pads  123  of the nanowire FET P 32   b  and the pad  123   a  in the Y direction, and a lower end having the same position as that of this region in the Y direction. Similarly, for the nanowire FETs N 31  and N 32   b  arranged adjacent to each other in the same straight line in the X direction and including different numbers of nanowires, providing the nanowire FET N 41  as a dummy transistor allows the groups of pads  124 ,  125  of the nanowire FET N 31  to each have an upper end having the same position as that of a region surrounding the pads  126  of the nanowire FET N 32   b  and the pad  126   a  in the Y direction, and a lower end having the same position as that of this region in the Y direction. Consequently, the semiconductor integrated circuit device is easily manufactured, and process-induced variations therein can be reduced, thus improving yield. 
     Another Example 5 
       FIG. 13  shows another example of the standard cell in the present embodiment. The layout configuration of this standard cell  3 E of  FIG. 13  is basically similar to that of the standard cell  3 D of  FIG. 12 . Common components are denoted by the same reference characters, and a detailed description thereof may be omitted here. In  FIG. 13 , the nanowire FETs P 41  and N 41  as dummy transistors having no contribution to a logical operation of the circuit each include a dummy gate electrode separated from the gate line  132 . 
     That is to say, the nanowire FET P 41  includes a group of dummy nanowires  112   b  and a dummy pad  123   a.  A dummy gate electrode  132   d  is aligned with the gate line  132 , and surrounds peripheries of the dummy nanowires  112   b.  The dummy gate electrode  132   d  is separated from the gate electrode  132   p  of the nanowire FET P 32   b.  The nanowire FET N 41  includes a group of dummy nanowires  114   a  and a dummy pad  126   a.  A dummy gate electrode  132   c  is aligned with the gate line  132 , and surrounds peripheries of the dummy nanowires  114   a . The dummy gate electrode  132   c  is separated from the gate electrode  132   n  of the nanowire FET N 32   b.    
     Also in the embodiment shown in  FIG. 13 , just like the embodiment shown in  FIG. 12 , the groups of pads  121 ,  122  can each have an upper end having the same position as that of the region surrounding the pads  123  and  123   a,  and a lower end having the same position as that of this region. Similarly, the groups of pads  124 ,  125  can each have an upper end having the same position as that of the region surrounding the pads  126  and  126   a,  and a lower end having the same position as that of this region. Consequently, the semiconductor integrated circuit device is easily manufactured, and process-induced variations therein can be reduced, thus improving yield. 
     Another Example 6 
       FIG. 14  shows another example of the standard cell in the present embodiment. The layout configuration of this standard cell  3 F of  FIG. 14  is basically similar to the standard cell  3 D of  FIG. 12 . Common components are denoted by the same reference characters, and a detailed description thereof may be omitted here. In  FIG. 14 , in addition to the nanowire FETs P 41  and N 41 , a p-type nanowire transistor P 42  and an n-type nanowire transistor N 42  as dummy transistors having no contribution to a logical operation of the circuit are provided. 
     In  FIG. 14 , nanowire FETs P 31   b  and N 31   b  each include six (three in the Y direction and two in the vertical direction) parallelly arranged nanowires  111 ,  113  extending in the X direction. With this configuration, in  FIG. 14 , the driving capability of the serial portion P 3  including the nanowire FETs P 31   b  and P 32   b  is set to be within a range of 0.25 to 0.5 times the driving capability of the nanowire FET P 31  shown in  FIG. 7 , and is set to be different from that of the configurations shown in  FIGS. 1 to 13 . Similarly, the driving capability of the serial portion N 3  including the nanowire FETs N 31   b  and N 32   b  is set to be within a range of 0.25 to 0.5 times the driving capability of the nanowire FET N 31  shown in  FIG. 7 , and is set to be different from that of the configurations shown in  FIGS. 1 to 13 . 
     The nanowire FET P 42  includes a group of dummy nanowires  111   b  and a dummy pad  121   a.  The dummy pad  121   a  is disposed adjacent to the upper side of the group of pads  121  in the Y direction. The group of dummy nanowires  111   b  includes two (one in the Y direction and two in the vertical direction) nanowires arranged between the dummy pad  121   a  and the group of pads  122  in parallel with the nanowires  111  to extend in the X direction. The gate line  131  extends so as to cross the arrangement position of the dummy nanowires  111   b  in the Y direction, and surrounds peripheries of the dummy nanowires  111   b.  That is to say, a dummy gate electrode  131   d  of the nanowire FET P 42  is formed integrally with the gate electrode  131   p  of the nanowire FET P 31   b.    
     The nanowire FET N 42  includes a group of dummy nanowires  113   b  and a dummy pad  124   a.  The dummy pad  124   a  is disposed adjacent to the lower side of the group of pads  124  in the Y direction. The group of dummy nanowires  113   b  includes two (one in the Y direction and two in the vertical direction) nanowires arranged between the dummy pad  124   a  and the group of pads  125  in parallel with the nanowires  113  to extend in the X direction. The gate line  131  extends so as to cross the arrangement position of the dummy nanowires  113   b  in the Y direction, and surrounds peripheries of the dummy nanowires  113   b.  That is to say, a dummy gate electrode  131   c  of the nanowire FET N 42  is formed integrally with the gate electrode  131   n  of the nanowire FET N 31   b.    
     That is to say, the configuration of the standard cell  3 F is obtained by modifying the configuration of the standard cell  3 D of  FIG. 12  such that the pad  121  are classified under two groups in the nanowire FET P 31 , and the pads  124  are classified under two groups in the nanowire FET N 31 . 
     In accordance with the configuration of  FIG. 14 , for the nanowire FETs P 31   b  and P 32   b  each including six nanowires, providing the nanowire FETs P 41  and P 42  as dummy transistors allows respective upper ends of a region surrounding the pads  121 ,  121   a,  the group of pads  122 , and a region surrounding the pads  123 ,  123   a  to have the same position in the Y direction, and allows respective lower ends thereof to have the same position in the Y direction. Further, when a standard cell such as the cell shown in any one of  FIGS. 1 to 13  is adjacent to the standard cell of  FIG. 14  in the X direction, and these standard cells have the same height in the Y direction, the pads arranged in the p-type transistor region PA can have their upper ends having the same position, and have their lower ends having the same position. Similarly, for the nanowire FETs N 31   b  and N 32   b  each including six nanowires, providing the nanowire FETs N 41  and N 42  as dummy transistors allows respective upper ends of a region surrounding the pads  124 ,  124   a,  the group of pads  125 , and a region surrounding the pads  126 ,  126   a  to have the same position in the Y direction, and allows respective lower ends thereof to have the same position in the Y direction. Further, when a standard cell such as the cell shown in any one of  FIGS. 1 to 13  is adjacent to the standard cell of  FIG. 14  in the X direction, and these standard cells have the same height in the Y direction, the pads arranged in the n-type transistor region NA can have their upper ends having the same position, and have their lower ends having the same position. Consequently, the semiconductor integrated circuit device is easily manufactured, and process-induced variations therein can be reduced, thus improving yield. 
     Although, in the embodiment of  FIG. 14 , the nanowire FETs P 41 , P 42 , N 41 , and N 42  as dummy transistors each include one nanowire in the Y direction, this is a non-limiting example, and two or more nanowires may be provided in the Y direction. Although the p-type region and the n-type region are horizontally symmetric to each other, this is a non-limiting example. For example, only the p-type region may include a nanowire FET as a dummy transistor, or the manner of separation of pads, the number of nanowires, or any other feature may vary between the p-type region and the n-type region. 
     Although, in the layout configurations shown in the present disclosure, the intervals in the Y direction and thicknesses of the nanowires are illustrated to be equal, they are not necessarily equal. The number of the nanowires of each of the nanowire FETs shown in the present disclosure is only by way of example, and is a non-limiting example. 
     In the foregoing description, in the nanowire FET, the pads are separated from the nanowires arranged in the Y direction. However, pads may be integrated with the nanowires arranged in the Y direction.  FIG. 15  shows a variation of the layout configuration of  FIG. 1 . In  FIG. 15 , the pads  21 ,  22 ,  23 ,  24 ,  25 ,  26  are each integrated with associated ones of the groups of nanowires  11 ,  12 ,  13 ,  14  each including four nanowires arranged in the Y direction. 
     Although the present disclosure describes the standard cells constituting a NOR gate, a NAND gate, and an inverter, the present disclosure may be directed to a standard cell for other logical circuits having a serial portion including nanowire FETs connected in series. This also provides similar advantages. 
     The present disclosure provides a layout configuration of a semiconductor integrated circuit device including a nanowire FET, the layout configuration being effective for making manufacturing the device easy, and is useful for improving performance of the semiconductor integrated circuit device.