Patent Publication Number: US-9899079-B2

Title: Memory devices

Description:
RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 14/061,539, filed Oct. 23, 2013, the disclosure of which is hereby incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     Memory devices have been widely used in electronic products to provide high storage speed and low power consumption. For example, resistive random access memory (RRAM) device is one possible candidate for next generation non-volatile memory technology due to simple and complementary metal-oxide semiconductor (CMOS) logic compatible process. Each memory cell in a RRAM device is a metal oxide material sandwiched between top and bottom electrodes. By applying appropriate voltage, the state of each memory cell can be changed from high resistance state (HRS) to low resistance state (LRS) or from LRS to HRS. The above switching mechanism is related to oxygen vacancy migration. The low and high resistance states are utilized to indicate a logical data “1” or “0”, thereby allowing for data storage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure can be more fully understood by reading the following detailed description of various embodiments, with reference to the accompanying drawings as follows: 
         FIG. 1  is a schematic diagram of a memory device in accordance with various embodiments of the present disclosure; 
         FIGS. 2A-2B  show the setting and resetting state of the periphery circuit in  FIG. 1  in accordance with various embodiments of the present disclosure; 
         FIG. 3  is a circuit diagram of a memory cell in accordance with various embodiments of the present disclosure; 
         FIG. 4  is a schematic diagram of a memory device in accordance with various embodiments of the present disclosure; and 
         FIG. 5  is a flowchart showing a method for forming an I/O memory block in a memory device in accordance with various embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, specific details are presented to provide a thorough understanding of the embodiments of the present disclosure. Persons of ordinary skill in the art will recognize, however, that the present disclosure can be practiced without one or more of the specific details, or in combination with other components. Well-known implementations or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the present disclosure. 
     The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and is not meant to limit the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification. 
     It will be understood that, although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. 
     Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, uses of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments. 
       FIG. 1  is a schematic diagram of a memory device  100  in accordance with various embodiments of the present disclosure. In some embodiments, the memory device  100  is a resistive random access memory (RRAM, or ReRAM) device, dynamic random access memory (DRAM) device, static random access memory (SRAM) device, or the like. The memory device  100  includes an input/output (I/O) memory block  110  and a periphery circuit  120 . The I/O memory block  110  includes memory cells C 1,1 -C N,M  arranged in a matrix formed by bit lines BL 1 -BL M  and word lines WL 1 -WL N . Each one of the memory cells C 1,1 -C N,M  is electrically connected by one of the bit lines BL 1 -BL M  and one of the word lines WL 1 -WL N . For illustration, a memory cell C i,j  is electrically connected to a bit line BL j  and a word line WL i . The memory cells C 1,1 -C N,M  are located at respective intersections of the bit lines BL 1 -BL M  and word lines WL 1 -WL N . 
     The source line SL is electrically connected to the memory cells C 1,1 -C N,M  and the periphery circuit  120 . In detail, the source line SL has a main portion SM and branch portions SB 1 -SB N . The main portion SM is electrically connected to the periphery circuit  120 . The branch portions SB 1 -SB N  are electrically connected to the memory cells C 1,1 -C N,M . For illustration, the branch portion SB 1  is electrically connected to the memory cells C 1,1 -C 1,M , the branch portion SB 2  is electrically connected to the memory cells C 2,1 -C 2,M , the branch portion SB 3  is electrically connected to the memory cells C 3,1 -C 3,M , and so on. In some embodiments, a width of the main portion SM is greater than that of each of the branch portions SB 1 -SB N . 
     In some embodiments, the main portion SM of the source line SL is located outside the I/O memory block  110 . In some embodiments, the main portion SM of the source line SL is located between two of the bit lines BL 1 -BL M . 
     In some embodiments, the periphery circuit  120  includes a multiplexer  122  and a switch group  124 . The multiplexer  122  is electrically connected to the bit lines BL 1 -BL M  and configured to select one of the bit lines BL 1 -BL M . The switch group  124  is electrically connected to the multiplexer  122  and configured to allow a writing voltage V W  and a ground voltage V G  to be applied on the source line SL and a selected bit line. The switch group  124  includes switches T 1 -T 4  and a voltage source VS. The voltage source VS is configured to provide the writing voltage V w  for writing operations of the memory cells C 1,1 -C N,M  in the I/O memory block  110 . The voltage source VS has two terminals A and B, and the voltage level of the terminal A is higher than that of the terminal B. With operations of the switches T 1 -T 4 , one of the selected bit line and the source line SL is electrically connected to the voltage source VS, and the other one of the selected bit line and the source line SL is grounded. Moreover, the operations of the switches T 1 -T 4  are controlled by switching signals SW 1 -SW 4 , respectively. 
     In detail, the switch T 1  is electrically connected to the multiplexer  122  to allow the ground voltage V G  to be applied on the selected bit line in accordance with the switching signal SW 1 . The switch T 2  is electrically connected to the source line SL to allow the ground voltage V G  to be applied on the source line SL in accordance with the switching signal SW 2 . The switch T 3  is electrically connected between the multiplexer  122  and the terminal A of the voltage source VS, and is configured to electrically connect the selected bit line to the voltage source VS in accordance with the switching signal SW 3 . The switch T 4  is electrically connected between the source line SL and the terminal A of the voltage source VS, and is configured to electrically connect the source line SL to the voltage source VS in accordance with the switching signal SW 4 . 
     There are two transition states of the switch group  124 . One transition state is defined as a setting state, where the writing voltage V W  is input to the multiplexer  122  and the ground voltage V G  is input to the source line SL. In the setting state, the switching signals SW 1  and SW 4  respectively control the switches T 1  and T 4  to turn off, and the switching signals SW 2  and SW 3  respectively control the to switches T 2  and T 3  to turn on. The other transition state is defined as a resetting state, where the ground voltage V G  is input to the multiplexer  122  and the writing voltage V W  is input to the source line SL. In the resetting state, the switching signals SW 1  and SW 4  respectively control the switches T 1  and T 4  to turn on, and the switching signals SW 2  and SW 3  respectively control the to switches T 2  and T 3  to turn off. 
       FIG. 2A  shows the setting state of the periphery circuit  120  in  FIG. 1  in accordance with various embodiments of the present disclosure. When the switch group  124  switches to the setting state, the switches T 1  and T 4  are turned off, and the switches T 2  and T 3  are turned on, such that the voltage source VS is electrically connected to the selected bit line, and the source line SL is grounded. 
       FIG. 2B  shows the resetting state of the periphery circuit  120  in  FIG. 1  in accordance with various embodiments of the present disclosure. When the switch group  124  switches to the resetting state, the switches T 2  and T 3  are turned off, and the switches T 1  and T 4  are turned on, such that the voltage source VS is electrically connected to the source line SL, and the selected bit line is grounded. 
     In the operation of writing logical data to a memory cell of the I/O memory block  110 , the multiplexer  122  establishes connection between the switch group  124  and the bit line electrically connected to the memory cell. In such condition, the transition state of the switch group  124  switches to either the setting state as shown in  FIG. 2A  or the resetting state as shown in  FIG. 2B . 
     Reference is made back to  FIG. 1 . For illustration, if the logical data “1” is selected to be written into the memory cell C i,j  of the I/O memory block  110 , the multiplexer  122  selects the bit line BL j  to establish connection between the switch group  124  and the bit line BL j , and the transition state of the switch group  124  switches to the setting state. The word line WL i  is also applied with a voltage level which indicates writing logical data “0” to the memory cell C i,j . 
     On the other hand, if the logical data “0” is selected to be written into the memory cell C i,j  of the I/O memory block  110 , the multiplexer  122  selects the bit line BL j  to establish connection between the switch group  124  and the bit line BL j , and the transition state of the switch group  124  switches to the resetting state. The word line WL i  is also applied with a voltage level which indicates writing logical data “0” to the memory cell C i,j . 
     Based on the aforementioned embodiments in  FIG. 1 , a single multiplexer is required for selecting a bit line from bit lines in an I/O memory block. Since one main portion of a source line is connected to all memory cells of the I/O memory block, no additional multiplexer is required in a periphery circuit, compared to other approaches using an additional multiplexer for selecting one main portion from multiple main portions of the source line. Hence, the circuit area and manufacture cost are significantly reduced. 
     In some embodiments, the memory device  100  is a resistive random access memory (RRAM) device.  FIG. 3  is a circuit diagram of a memory cell  300  according to various embodiments of the present disclosure. The memory cell  300  is configured as one of the memory cells C 1,1 -C N,M  in  FIG. 1 . For illustration, the memory cell  300  is a 1T1R RRAM memory cell, which includes a MOS transistor T and a resistive memory unit R. The drain D of the MOS transistor T is electrically connected to the resistive memory unit R. The gate G of the MOS transistor T is electrically connected to a word line WL, which is one of the word lines WL 1 -WL N  shown in  FIG. 1 . The source S of the MOS transistor T is electrically connected to the branch portion SB, which is one of the branch portions SB 1 -SB N  shown in  FIG. 1 . One terminal of the resistive memory unit R is electrically connected to the drain D of the MOS transistor T, and the other terminal of the resistive memory unit R is electrically connected to the bit line BL, which is one of the bit lines BL 1 -BL M  shown in  FIG. 1 . 
     The resistive memory unit R has two states. One is defined as low resistance state (LRS), and the other is defined as high resistance state (HRS). The LRS state represents that logical data “1” is written into the memory cell  300 , and the HRS state represents that logical data “0” is written into the memory cell  300 . The resistance of the resistive memory unit R in the HRS state is relatively higher than that in the LRS state. The state of the resistive memory unit R changes in accordance with the current I 1  or I 2  flowing therethrough. For illustration, the current I 1  indicates the current flowing from the resistive memory unit R, and the current I 2  indicates the current flowing toward the resistive memory unit R. The state of the resistive memory unit R changes to the LRS state when the current I 1  flows through the resistive memory unit R. The state of the resistive memory unit R changes to the HRS state when the current I 2  flows through the resistive memory unit R. 
     For illustration, if the memory cell  300  needs to be written with logical data “1”, the voltage of the bit line BL changes to the writing voltage V w , the voltage of the branch portion SB changes to the ground voltage V G , and the voltage level of the word line WL changes to be higher than the writing voltage V w . As a result, the MOS transistor T is conducted, and the current I 1  flows through the MOS transistor T. Accordingly, the state of the resistive memory unit R is changed to the LRS state. 
     For another illustration, if the memory cell  300  needs to be written with logical data “0”, the voltage of the bit line BL changes to the ground voltage V G , the voltage of the branch portion SB changes to the writing voltage V w , and the voltage level of the word line WL changes to be higher than the writing voltage V w . As a result, the MOS transistor T is conducted, and the current I 2  flows through the MOS transistor T. Accordingly, the state of the resistive memory unit R is changed to the HRS state. 
     In some embodiments, the memory device of the present disclosure includes multiple I/O memory blocks. Moreover, the source line for controlling the memory cells in an I/O memory block is disposed between two adjacent I/O memory blocks.  FIG. 4  is a schematic diagram of a memory device  400  in accordance with various embodiments of the present disclosure. The memory device  400  includes I/O memory blocks  410 A and  410 B and periphery circuits  420 A and  420 B. Memory cells (not labeled) of the I/O memory block  410 A are controlled by the periphery circuit  420 A, bit lines BLA 1 -BLA M , word lines WL 1 -WL N , and a source line including a main portion SMA and branch portions SBA 1 -SBA N . Memory cells (not labeled) of the I/O memory block  410 B are controlled by the periphery circuit  420 B, bit lines BLB 1 -BLB M , the word lines WL 1 -WL N  and another source line including a main portion and branch portions (not shown in  FIG. 4 ). The word lines WL 1 -WL N  extend through the I/O memory blocks  410 A and  410 B to control the memory cells in the I/O memory blocks  410 A and  410 B. In some embodiments, the main portion SMA is located in a gap provided at one edge of the I/O memory block  410 A. For illustration, the gap is formed between the I/O memory blocks  410 A and  410 B. 
       FIG. 5  is a flowchart showing a method  500  for forming an I/O memory block in a memory device according to various embodiments of the present disclosure. The method  500  shown in  FIG. 5  is applied for forming the memory device  100  shown in  FIG. 1 . For illustration, the operations of forming the memory device  100  in  FIG. 1  are described below with reference to the method  500 . 
     The method  500  begins at operation  502 . In operation  502 , the memory cells C 1,1 -C N,M  of the I/O memory block  110  are formed and arranged in a matrix. Operation  504  is performed after operation  502 . In operation  504 , the bit lines BL 1 -BL M  are formed to electrically connect the memory cells C 1,1 -C N,M . In some embodiments, the number of the bit lines BL 1 -BL M  is at least 4 (i.e., M is greater than or equal to 4). Operation  506  is performed after operation  504 . In operation  506 , the source line SL is formed to electrically connect the memory cells C 1,1 -C N,M  of the I/O memory block  110  together. The formed source line SL has the main portion SM and the branch portions SB N . The branch portions SB N  are electrically connected to the memory cells C 1,1 -C N,M . In some embodiments, the branch portions SB N  are parallel to rows of the matrix, and the main portion SM is parallel to columns of the matrix. 
     In accordance with some embodiments, the present disclosure discloses a device. The device includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells. 
     In accordance with another embodiments, the present disclosure discloses a device including I/O memory blocks. A gap is provided at one edge of each of the I/O memory blocks. Each of the I/O memory blocks includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In each of the I/O memory blocks, the source line and the bit lines are configured to provide logical data to the memory cells. The source line has a main portion located in the gap and branch portions. 
     In accordance with yet another embodiments, the present disclosure discloses a method. In this method, memory cells of an I/O memory block are formed. Bit lines and a source line are formed to electrically connect the memory cells. 
     As is understood by one of ordinary skill in the art, the foregoing embodiments of the present disclosure are illustrative of the present disclosure rather than limiting of the present disclosure. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.