Patent Publication Number: US-2023157029-A1

Title: Semiconductor device and method for fabricating the same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method of fabricating a semiconductor device, and more particularly to a method for fabricating a ferroelectric random access memory (FeRAM). 
     2. Description of the Prior Art 
     In efforts to improve memory arrays, field effect transistors with ferroelectric gates or ferroelectric field effect transistors (FeFETs) have been recently in the focus of research. In general, ferroelectric materials have dielectric crystals which show a spontaneous electric polarization similar to ferromagnetic materials showing a spontaneous magnetization. Upon applying an appropriate external electric field to a ferroelectric material, the direction of polarization can be reoriented. The basic idea is to use the direction of spontaneous polarization in ferroelectric memories for storing digital bits. In FeFETs, the effect that one makes use of is the possibility to adjust the polarization state of a ferroelectric material on the basis of appropriate electrical fields which are applied to the ferroelectric material which, in a FeFET, is usually the gate oxide. Since the polarization state of a ferroelectric material is preserved unless it is exposed to a high, with regard to the polarization state, counter-oriented electrical field or a high temperature, it is possible to “program” a capacitor formed of ferroelectric material such that an induced polarization state reflects an information unit. Therefore, an induced polarization state is preserved, even upon removing an accordingly “programmed” device from a power supply. In this way, FeFETs allow the implementation of non-volatile electrically-switchable data storage devices. 
     On the basis of ferroelectric materials, it is possible to provide non-volatile memory devices, particularly random-access memory devices similar in construction to DRAM devices, but differing in using a ferroelectric layer instead of a dielectric layer such that non-volatility is achieved. For example, the 1T-1C storage cell design in a FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor--a linear dielectric is used in a DRAM cell capacitor, whereas, in a FeRAM cell capacitor, the dielectric structure includes a ferroelectric material. Other types of FeRAMs are realized as 1T storage cells which consist of a single FeFET employing a ferroelectric dielectric instead of the gate dielectric of common MOSFETs. The current-voltage characteristic between source and drain of a FeFET depends in general on the electric polarization of the ferroelectric dielectric, i.e., the FeFET is in the on- or off-state, depending on the orientation of the electric polarization state of the ferroelectric dielectric. Writing of a FeFET is achieved in applying a writing voltage to the gate relative to source, while a 1T-FeRAM is read out by measuring the current upon applying a voltage to source and drain. It is noted that reading out of a 1T-FeRAM is non-destructive. 
     A means of optimizing FeFETs and FeRAMs is to minimize the sizes of these elements, however, the complexity and cost for integrating and reducing the size of these elements also increases accordingly. Hence, how to lower cost while keeping performance of the device has become an important task in this field. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM). 
     According to another aspect of the present invention, a semiconductor device includes an inter-metal dielectric (IMD) layer on a substrate and a ferroelectric random access memory (FeRAM) on the ILD layer. Preferably, the FeRAM includes a first trench and a second trench in the IMD layer, a bottom electrode in the first trench and the second trench, a ferroelectric (FE) layer on the bottom electrode, and a top electrode on the FE layer. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 - 3    illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to ... ” The terms “connect”, “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     Referring to  FIGS.  1 - 3   ,  FIGS.  1 - 3    illustrate a method for fabricating a semiconductor device or more specifically a MRAM device according to an embodiment of the present invention. As shown in  FIG.  1   , a substrate  12  made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs). Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer could also be formed on top of the substrate  12 . More specifically, at least a planar MOS transistor or non-planar (such as FinFETs) MOS transistors could be formed on the substrate  12 , in which the MOS transistors could include transistor elements such as a gate dielectric layer  16 , a gate electrode (such as metal gate)  18 , source/drain regions  20 , spacers, epitaxial layers, and a contact etch stop layer (CESL). An ILD layer  22  could be formed on the substrate  12  to cover the MOS transistors, and a plurality of contact plugs  24  could be formed in the ILD layer  22  to electrically connect to the gate electrodes  18  and/or source/drain region  20  of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. 
     Next, at least a metal interconnect structure is formed on the ILD layer  22  to electrically connect the contact plugs  24 , in which the metal interconnect structure could include an inter-metal dielectric (IMD) layer  26  disposed on the ILD layer  22 , at least a metal interconnection  28  embedded in the IMD layer  26 , an IMD layer  30  disposed on the IMD layer  26 , at least a metal interconnection  32  such as via conductor embedded in the IMD layer  30 , an IMD layer  34  disposed on the IMD layer  30 , and at least a metal interconnection  36  embedded in the IMD layer  34 . Preferably, the metal interconnection  28  made of trench conductor could be referred as a first level metal interconnection and the metal interconnection  36  also made of trench conductor could be referred to as a second level metal interconnection. 
     Preferably, each of the metal interconnections  28 ,  32 ,  36  could be embedded within the IMD layers  26 ,  30 ,  34  according to a single damascene process or dual damascene process. For instance, each of the metal interconnections  28 ,  32 ,  36  could further includes a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. Moreover, the metal layer within the metal interconnections  28 ,  32 ,  36  preferably includes copper and the IMD layers  26 ,  30 ,  34  could include silicon oxide such as tetraethyl orthosilicate (TEOS) or ultra low-k (ULK) dielectric layers including but not limited to for example porous material or silicon oxycarbide (SiOC) or carbon doped silicon oxide (SiOCH). 
     Next, a stop layer  42  and an IMD layer  44  are formed on the IMD layer  34 , and a photo-etching process is conducted to remove part of the IMD layer  44  for forming at least two trenches including a trench  46  and a trench  48  in the IMD layer  44 . Next, a bottom electrode  50  is formed in the trenches  46 ,  48  without filling the trenches  46 ,  48  completely, a ferroelectric (FE) layer  52  is formed on the bottom electrode  50 , and a top electrode  54  is formed on the FE layer  52  to fill the trenches  46 ,  48  completely. Next, a selective anneal process such as a rapid thermal anneal (RTA) process could be conducted on the FE layer  52  for a phase change. Preferably, the anneal process is conducted at a temperature equal to or less than 400° C. and a duration of the anneal process  84  is between 25-35 seconds or most preferably at 30 seconds. 
     Next, as shown in  FIG.  2   , a pattern transfer process is conducted to pattern the top electrode  54  and the FE layer  52 . For instance, a patterned mask (not shown) such as a patterned resist could be formed on the top electrode  54 , and an etching process is conducted by using the patterned mask as mask to remove part of the top electrode  54  and part of the FE layer  52  but not removing any of the bottom electrode  50  so that sidewalls of the remaining top electrode  54  are aligned with sidewalls of the remaining FE layer  52  while the un-etched bottom electrode  50  still covers the surface of the IMD layer  44  entirely. At this stage the un-patterned bottom electrode  50  and the patterned FE layer  52  and top electrode  54  preferably constitute a FeRAM  56 . 
     In this embodiment, the bottom electrode  50  and the top electrode  54  are made of conductive material such as titanium nitride (TiN). The FE layer  52  preferably includes HfZrO 2 , nevertheless, according to other embodiments of the present invention, the FE layer  52  could also include a material selected from the group consisting of lead zirconate titanate (bZrTiO 3 , PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O 3 , PLZT), strontium bismuth tantalate (SrBiTa 2 O 9 , SBT), bismuth lanthanum titanate ((BiLa) 4 Ti 3 O 12 , BLT), and barium strontium titanate (BaSrTiO 3 , BST). 
     Moreover, in this embodiment, the bottom electrode  50  includes a thickness between 5-15 Angstroms or most preferably 10 Angstroms, the FE layer  52  includes a thickness between 5-15 Angstroms or most preferably 10 Angstroms, and the top electrode  54  includes a thickness between 30-40 Angstroms or most preferably 35 Angstroms. The IMD layer  44  could include silicon oxide such as tetraethyl orthosilicate (TEOS) or ultra low-k (ULK) dielectric layers including but not limited to for example porous material or silicon oxycarbide (SiOC) or carbon doped silicon oxide (SiOCH). 
     Next, as shown in  FIG.  3   , a selective photo-etching process could be conducted to remove part of the bottom electrode  50  for defining the area occupied by the FeRAM  56  so that the bottom electrode  50  does not extend throughout the entire stop layer  42 . Next, a hard mask  58  is formed on the FeRAM  56 , an IMD layer  60  is formed on the hard mask  58 , at least a metal interconnection  62  such as via conductors are formed in the IMD layer  60  to electrically connect to the bottom electrode  50  and the top electrode  54  of the FeRAM  56 , another IMD layer  64  is formed on the IMD layer  60 , and then metal interconnections  66  such as trench conductors are formed in the IMD layer  64  to electrically connect to the metal interconnections  62  underneath. Similar to the aforementioned embodiment, each of the metal interconnections  62 ,  66  could be interconnected to each other and embedded within the IMD layers  60 ,  64  according to a single damascene process or dual damascene process. Moreover, the metal interconnections  62 ,  66  preferably include copper and the IMD layers  60 ,  64  could include silicon oxide such as tetraethyl orthosilicate (TEOS) or ultra low-k (ULK) dielectric layers including but not limited to for example porous material or silicon oxycarbide (SiOC) or carbon doped silicon oxide (SiOCH). This completes the fabrication of a semiconductor device according to an embodiment of the present invention. 
     Referring again to  FIG.  3   ,  FIG.  3    further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown in  FIG.  3   , the semiconductor device preferably includes an IMD layer  44  disposed on the substrate  12  and at least a FeRAM  56  disposed on the IMD layer  44 , in which the FeRAM  56  includes at least two trenches such as the trenches  46 ,  48  in the IMD layer  44 , a bottom electrode  50  disposed in the trenches  46 ,  48 , a FE layer  52  disposed on the bottom electrode  50 , and a top electrode  54  disposed on the FE layer  52 . 
     Moreover, a hard mask  58  is disposed on the FeRAM  56 , IMD layers  60 ,  64  are disposed on the hard mask  56 , and metal interconnections  62 ,  66  are disposed in the IMD layers  60 ,  64  to connect the bottom electrode  50  and the top electrode  54  respectively, in which the metal interconnection  62  on the left contacts the bottom electrode  50  directly while the metal interconnection  62  on the right contacts the top electrode  54  directly. It should be noted that the bottom of the FeRAM  56  disposed in the two trenches  46 ,  48  preferably not contacting the lower level metal interconnection  36  directly as the bottom electrode  50  and the top electrode  54  are connected to external devices through the upper level or metal interconnections  62  on the top. 
     Overall, the present invention preferably discloses an improved FeRAM structure in that at least two trenches or more than two trenches are first formed in an IMD layer, and then elements including bottom electrode, FE layer, and top electrode are formed in the trenches and a patterning process is conducted to form a FeRAM. By following the aforementioned approach to fabricate FeRAM it would be desirable increase the capacitance of the device significantly and improve power distribution network (PDN) and spike noise of LC circuit at the same time. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.