Patent Publication Number: US-11659711-B2

Title: Three-dimensional memory device including discrete charge storage elements and methods of forming the same

Description:
RELATED APPLICATIONS 
     This application is a continuation-in-part application of U.S. application Ser. No. 16/849,600 filed on Apr. 15, 2020, the entire content of which is incorporated herein by reference. 
    
    
     FIELD 
     The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including discrete charge storage elements and methods of manufacturing the same. 
     BACKGROUND 
     Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. 
     SUMMARY 
     According to an aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory openings vertically extending through the alternating stack; and memory opening fill structures located in the memory openings, wherein: each of the memory opening fill structures comprises a vertical semiconductor channel and a memory film; and the memory film comprises a tunneling dielectric layer and a vertical stack of discrete charge storage elements that are vertically spaced apart from each other by lateral protrusion portions of a subset of the insulating layers. 
     According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an alternating stack of disposable material layers and silicon nitride layers over a substrate; forming memory openings through the alternating stack; forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel; forming laterally-extending cavities by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures; and forming insulating layers comprising silicon oxide by performing an oxidation process that oxidizes surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities, wherein remaining portions of the charge storage material layers form a vertical stack of discrete charge storage elements in each of the memory opening fill structures; and replacing remaining portions of the silicon nitride layers with replacement material portions that comprise electrically conductive layers. 
     According to an aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layer; forming a memory opening through the alternating stack; forming annular lateral recesses at levels of the insulating layers by laterally recessing sidewalls of the insulating layers relative to sidewalls of the spacer material layers around the memory opening; forming a vertical stack of discrete metal portions in the annular lateral recesses; forming a semiconductor material layer on the vertical stack of the metal portions; forming a vertical stack of metal-semiconductor alloy portions by reacting the vertical stack of metal portions with portions of the semiconductor material layer located at levels of the insulating layers; removing the vertical stack of metal-semiconductor alloy portions selective to unreacted portions of the semiconductor material layer, wherein unreacted portions of the semiconductor material layer remain at levels of the spacer material layers and comprise a vertical stack of discrete semiconductor material portions; and forming a tunneling dielectric layer and a vertical semiconductor channel in the memory opening. 
     According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at each level of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, charge storage structures comprising a vertical stack of discrete semiconductor material portions and at least one silicon nitride material portion in contact with the vertical stack, a tunneling dielectric layer in contact with the charge storage structures, and a vertical semiconductor channel. 
     According to yet another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at levels of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, a vertical stack of discrete charge storage material portions, a tunneling dielectric layer, and a vertical semiconductor channel, wherein each charge storage material portion comprises a tubular portion located at a level of a respective one of the electrically material layers, an upper flange portion laterally extending outward from an upper end of an outer sidewall of the tubular portion, and a lower flange portion laterally extending outward from a lower end of the outer sidewall of the tubular portion. 
     According to still another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layer; forming a memory opening through the alternating stack; forming annular lateral recesses at levels of the insulating layers by laterally recessing sidewalls of the insulating layers relative to sidewalls of the spacer material layers around the memory opening; forming a vertical stack of discrete metal portions in the annular lateral recesses; forming a semiconductor material layer on the vertical stack of the metal portions; removing the vertical stack of discrete metal portions and portions of the semiconductor material layer that are adjacent to the vertical stack of discrete metal portions, wherein remaining portions of the semiconductor material layer comprise a vertical stack of semiconductor material portions, and each of the semiconductor material portions comprises a tubular portion, an upper flange portion laterally extending outward from an upper end of an outer sidewall of the tubular portion, and a lower flange portion laterally extending outward from a lower end of the outer sidewall of the tubular portion; and forming a tunneling dielectric layer and a vertical semiconductor channel in the memory opening. 
     According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at levels of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, a vertical stack of charge storage material portions, a tunneling dielectric layer, and a vertical semiconductor channel, and a vertical stack of discrete annular insulating material portions located at the levels of the insulating layers between the blocking dielectric layer and the tunneling dielectric layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic vertical cross-sectional view of a first exemplary structure after formation of at least one peripheral device and a semiconductor material layer according to a first embodiment of the present disclosure. 
         FIG.  2    is a schematic vertical cross-sectional view of the first exemplary structure after formation of an alternating stack of insulating layers and sacrificial material layers according to a first embodiment of the present disclosure. 
         FIG.  3    is a schematic vertical cross-sectional view of the first exemplary structure after formation of stepped terraces and a retro-stepped dielectric material portion according to a first embodiment of the present disclosure. 
         FIG.  4 A  is a schematic vertical cross-sectional view of the first exemplary structure after formation of memory openings and support openings according to a first embodiment of the present disclosure. 
         FIG.  4 B  is a top-down view of the first exemplary structure of  FIG.  4 A . The vertical plane A-A′ is the plane of the cross-section for  FIG.  4 A . 
         FIGS.  5 A- 5 P  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a first exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  5 Q and  5 R  are sequential schematic vertical cross-sectional views of a memory opening during formation of an alternative configuration of the first exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  6 A- 6 J  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a second exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  6 K and  6 L  are sequential schematic vertical cross-sectional views of a memory opening during formation of an alternative configuration of the second exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  7 A- 7 N  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a third exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  7 O and  7 P  are sequential schematic vertical cross-sectional views of a memory opening during formation of an alternative configuration of the third exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  8 A- 8 F  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a fourth exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  8 G and  8 H  are sequential schematic vertical cross-sectional views of a memory opening during formation of an alternative configuration of the fourth exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  9 A- 9 F  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a fifth exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  9 G and  9 H  are sequential schematic vertical cross-sectional views of a memory opening during formation of an alternative configuration of the fifth exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  10 A- 10 M  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a sixth exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  10 N and  10 O  are sequential schematic vertical cross-sectional views of a memory opening during formation of an alternative configuration of the sixth exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  11 A- 11 G  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a seventh exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  11 H and  11 I  are sequential schematic vertical cross-sectional views of a memory opening during formation of an alternative configuration of the seventh exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  12 A- 12 G  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of an eighth exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIGS.  12 H and  12 I  are sequential schematic vertical cross-sectional views of a memory opening during formation of an alternative configuration of the eighth exemplary memory opening fill structure according to a first embodiment of the present disclosure. 
         FIG.  13    is a schematic vertical cross-sectional view of the first exemplary structure after formation of memory stack structures and support pillar structures according to a first embodiment of the present disclosure. 
         FIG.  14 A  is a schematic vertical cross-sectional view of the first exemplary structure after formation of backside trenches according to a first embodiment of the present disclosure. 
         FIG.  14 B  is a partial see-through top-down view of the first exemplary structure of  FIG.  14 A . The vertical plane A-A′ is the plane of the schematic vertical cross-sectional view of  FIG.  14 A . 
         FIG.  15    is a schematic vertical cross-sectional view of the first exemplary structure after formation of backside recesses according to a first embodiment of the present disclosure. 
         FIG.  16 A  is a schematic vertical cross-sectional view of the first exemplary structure after formation of electrically conductive layers in the backside recesses according to a first embodiment of the present disclosure. 
         FIG.  16 B  is a partial see-through top-down view of the first exemplary structure of  FIG.  16 A . The vertical plane A-A′ is the plane of the schematic vertical cross-sectional view of  FIG.  16 A . 
         FIG.  17    is a schematic vertical cross-sectional view of the first exemplary structure after formation of an insulating spacer and a backside contact structure according to a first embodiment of the present disclosure. 
         FIG.  18 A  is a schematic vertical cross-sectional view of the first exemplary structure after formation of additional contact via structures according to a first embodiment of the present disclosure. 
         FIG.  18 B  is a top-down view of the first exemplary structure of  FIG.  18 A . The vertical plane A-A′ is the plane of the schematic vertical cross-sectional view of  FIG.  18 A . 
         FIG.  19 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a first exemplary memory opening fill structure or a second exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  19 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the first exemplary memory opening fill structure or the second exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  20 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a third exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  20 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the third exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  21 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a fourth exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  21 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the fourth exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  22 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a fifth exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  22 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the fifth exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  23 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a sixth exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  23 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the sixth exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  24 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a seventh exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  24 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the seventh exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  25 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a eighth exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  25 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the eighth exemplary memory opening fill structure is present in the memory opening according to a first embodiment of the present disclosure. 
         FIG.  26    is a schematic vertical cross-sectional view of a second exemplary structure after formation of an alternating stack of disposable material layers and silicon nitride layers according to a second embodiment of the present disclosure. 
         FIG.  27    is a schematic vertical cross-sectional view of the second exemplary structure after formation of stepped terraces and a retro-stepped dielectric material portion according to a second embodiment of the present disclosure. 
         FIG.  28 A  is a schematic vertical cross-sectional view of the second exemplary structure after formation of memory openings and support openings according to a second embodiment of the present disclosure. 
         FIG.  28 B  is a top-down view of the second exemplary structure of  FIG.  28 A . The vertical plane A-A′ is the plane of the cross-section for  FIG.  28 A . 
         FIG.  28 C  is a schematic vertical cross-sectional view of the second exemplary structure after formation of support pillar structures according to a second embodiment of the present disclosure. 
         FIGS.  29 A- 29 H  are sequential schematic vertical cross-sectional views of a memory opening within the second exemplary structure during formation of a memory stack structure, an optional dielectric core, and a drain region therein according to a second embodiment of the present disclosure. 
         FIG.  30    is a schematic vertical cross-sectional view of the second exemplary structure after formation of memory stack structures according to a second embodiment of the present disclosure. 
         FIG.  31 A  is a schematic vertical cross-sectional view of the second exemplary structure after formation of backside trenches according to a second embodiment of the present disclosure. 
         FIG.  31 B  is a partial see-through top-down view of the second exemplary structure of  FIG.  31 A . The vertical plane A-A′ is the plane of the schematic vertical cross-sectional view of  FIG.  31 A . 
         FIG.  32    is a vertical cross-sectional view of the second exemplary structure after formation of laterally-extending cavities by removal of the disposable material layers according to a second embodiment of the present disclosure. 
         FIG.  33 A- 33 D  are sequential vertical cross-sectional views of a region of the second exemplary structure around a memory opening fill structure during formation of insulating layers according to a second embodiment of the present disclosure. 
         FIG.  34    is a schematic vertical cross-sectional view of the second exemplary structure after formation of the insulating layers according to a second embodiment of the present disclosure. 
         FIG.  35    is a schematic vertical cross-sectional view of the second exemplary structure after formation of backside recesses according to a second embodiment of the present disclosure. 
         FIGS.  36 A- 36 D  are sequential vertical cross-sectional views of a region of the second exemplary structure during formation of electrically conductive layers according to a second embodiment of the present disclosure. 
         FIG.  37 A  is a schematic vertical cross-sectional view of the second exemplary structure after removal of a deposited conductive material from within the backside trench according to a second embodiment of the present disclosure. 
         FIG.  37 B  is a partial see-through top-down view of the second exemplary structure of  FIG.  37 A . The vertical plane A-A′ is the plane of the schematic vertical cross-sectional view of  FIG.  37 A . 
         FIG.  38    is a schematic vertical cross-sectional view of the second exemplary structure after formation of an insulating spacer and a backside contact structure according to a second embodiment of the present disclosure. 
         FIG.  39 A  is a schematic vertical cross-sectional view of the second exemplary structure after formation of additional contact via structures according to a second embodiment of the present disclosure. 
         FIG.  39 B  is a top-down view of the second exemplary structure of  FIG.  39 A . The vertical plane A-A′ is the plane of the schematic vertical cross-sectional view of  FIG.  39 A . 
         FIG.  40    is a vertical cross-sectional view of a third exemplary structure according to a third embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     As discussed above, the present disclosure is directed to a three-dimensional memory device including discrete charge storage elements and methods of manufacturing the same, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various structures including a multilevel memory structure, non-limiting examples of which include semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings. 
     The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements. 
     The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein. 
     As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow. 
     As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction. 
     A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, with no intervening substrates. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In contrast, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and vertically stacking the memory levels, as described in U.S. Pat. No. 5,915,167 titled “Three-dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three-dimensional memory arrays. The various three-dimensional memory devices of the present disclosure include a monolithic three-dimensional NAND string memory device, and can be fabricated employing the various embodiments described herein. 
     Referring to  FIG.  1   , a first exemplary structure according to an embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The first exemplary structure includes a substrate ( 9 ,  10 ), which can be a semiconductor substrate. The substrate can include a lower substrate semiconductor layer  9  and an optional upper substrate semiconductor layer  10 . The lower substrate semiconductor layer  9  maybe a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface  7 , which can be, for example, a topmost surface of the lower substrate semiconductor layer  9 . The major surface  7  can be a semiconductor surface. In one embodiment, the major surface  7  can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface. 
     As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10 −5  S/m to 1.0×10 5  S/m. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10 −5  S/m to 1.0 S/m in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/m to 1.0×10 5  S/m upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×10 5  S/m. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10 −5  S/m. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to have electrical conductivity greater than 1.0×10 5  S/m. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10 −5  S/m to 1.0×10 5  S/m. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition. 
     At least one semiconductor device  700  for a peripheral circuitry can be formed on a portion of the lower substrate semiconductor layer  9 . The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure  720  can be formed by etching portions of the lower substrate semiconductor layer  9  and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the lower substrate semiconductor layer  9 , and can be subsequently patterned to form at least one gate structure ( 750 ,  752 ,  754 ,  758 ), each of which can include a gate dielectric  750 , a gate electrode ( 752 ,  754 ), and a gate cap dielectric  758 . The gate electrode ( 752 ,  754 ) may include a stack of a first gate electrode portion  752  and a second gate electrode portion  754 . At least one gate spacer  756  can be formed around the at least one gate structure ( 750 ,  752 ,  754 ,  758 ) by depositing and anisotropically etching a dielectric liner. Active regions  730  can be formed in upper portions of the lower substrate semiconductor layer  9 , for example, by introducing electrical dopants employing the at least one gate structure ( 750 ,  752 ,  754 ,  758 ) as masking structures. Additional masks may be employed as needed. The active region  730  can include source regions and drain regions of field effect transistors. A first dielectric liner  761  and a second dielectric liner  762  can be optionally formed. Each of the first and second dielectric liners ( 761 ,  762 ) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner  761  can be a silicon oxide layer, and the second dielectric liner  762  can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device. 
     A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer  770 . In one embodiment the planarized top surface of the planarization dielectric layer  770  can be coplanar with a top surface of the dielectric liners ( 761 ,  762 ). Subsequently, the planarization dielectric layer  770  and the dielectric liners ( 761 ,  762 ) can be removed from an area to physically expose a top surface of the lower substrate semiconductor layer  9 . As used herein, a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air). 
     The optional upper substrate semiconductor layer  10 , if present, can be formed on the top surface of the lower substrate semiconductor layer  9  prior to, or after, formation of the at least one semiconductor device  700  by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the lower substrate semiconductor layer  9 . The deposited semiconductor material can be any material that can be employed for the lower substrate semiconductor layer  9  as described above. The single crystalline semiconductor material of the upper substrate semiconductor layer  10  can be in epitaxial alignment with the single crystalline structure of the lower substrate semiconductor layer  9 . Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer  770  can be removed, for example, by chemical mechanical planarization (CMP). In this case, the upper substrate semiconductor layer  10  can have a top surface that is coplanar with the top surface of the planarization dielectric layer  770 . 
     The region (i.e., area) of the at least one semiconductor device  700  is herein referred to as a peripheral device region  200 . The region in which a memory array is subsequently formed is herein referred to as a memory array region  100 . A staircase region  300  for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region  100  and the peripheral device region  200 . 
     In one alternative embodiment, the peripheral device region  200  may be located under the memory array region  100  in a CMOS under array configuration. In another alternative embodiment, the peripheral device region  200  may be located on a separate substrate which is subsequently bonded to the memory array region  100 . 
     Referring to  FIG.  2   , a stack of an alternating plurality of insulating layers  32  and spacer material layers (which can be sacrificial material layers  42 ) is formed over the top surface of the substrate ( 9 ,  10 ). As used herein, a “material layer” refers to a layer including a material throughout the entirety thereof. As used herein, an alternating plurality of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the first elements on both ends. The first elements may have the same thickness thereamongst, or may have different thicknesses. The second elements may have the same thickness thereamongst, or may have different thicknesses. The alternating plurality of insulating layers  32  and spacer material layers may begin with a bottommost insulating layer  32  or with a bottommost spacer material layer, and may end with a topmost insulating layer  32  or with a topmost spacer material layer. In one embodiment, an instance of the first elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality. 
     Generally, the spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. In case the spacer material layers are subsequently replaced with the electrically conductive layers, the spacer material layers are formed as sacrificial material layers  42 . Alternatively, if the spacer material layers are formed as electrically conductive layers, replacement of the spacer material layers with other material layers is unnecessary. While the present disclosure is described employing an embodiment in which the spacer material layers are formed as sacrificial material layers  42  that are subsequently replaced with electrically conductive layers, embodiments are expressly contemplated herein in which the sacrificial material layers are formed as electrically conductive layers. In such cases, processing steps for replacing the sacrificial material layers  42  with electrically conductive layers are omitted. 
     The stack of the alternating plurality of the insulating layers  32  and the spacer material layers (such as the sacrificial material layers  42 ) is herein referred to as an alternating stack ( 32 ,  42 ). Insulating materials that can be employed for the insulating layers  32  include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the insulating material of the insulating layers  32  can be silicon oxide. 
     The spacer material of the sacrificial material layers  42  includes a sacrificial material that can be removed selective to the insulating material of the insulating layers  32 . As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material. 
     The sacrificial material layers  42  may comprise an insulating material, a semiconductor material, or a conductive material. The spacer material of the sacrificial material layers  42  can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. Non-limiting examples of the spacer material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers  42  can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium. 
     In one embodiment, the insulating layers  32  can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The insulating material of the insulating layers  32  can be deposited, for example, by plasma enhanced chemical vapor deposition (PECVD). For example, if silicon oxide is employed for the insulating layers  32 , tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the PECVD process. The spacer material of the sacrificial material layers  42  can be formed, for example, by thermal CVD or atomic layer deposition (ALD). 
     The sacrificial material layers  42  can be suitably patterned so that conductive material portions to be subsequently formed by replacement of the sacrificial material layers  42  can function as electrically conductive electrodes, such as the control gate electrodes of the monolithic three-dimensional NAND string memory devices to be subsequently formed. The sacrificial material layers  42  may comprise a portion having a strip shape extending substantially parallel to the major surface  7  of the substrate. 
     The thicknesses of the insulating layers  32  and the sacrificial material layers  42  can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer  32  and for each sacrificial material layer  42 . The number of repetitions of the pairs of an insulating layer  32  and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer)  42  can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer  42  in the alternating stack ( 32 ,  42 ) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer  42 . Optionally, an insulating cap layer  70  can be formed over the alternating stack ( 32 ,  42 ). The insulating cap layer  70  includes a dielectric material that is different from the material of the sacrificial material layers  42 . In one embodiment, the insulating cap layer  70  can include a dielectric material that can be employed for the insulating layers  32  as described above. The insulating cap layer  70  can have a greater thickness than each of the insulating layers  32 . The insulating cap layer  70  can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer  70  can be a silicon oxide layer. 
     Referring to  FIG.  3   , stepped surfaces are formed at a peripheral region of the alternating stack ( 32 ,  42 ), which is herein referred to as a terrace region. As used herein, “stepped surfaces” refer to a set of surfaces that include at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume from which portions of the alternating stack ( 32 ,  42 ) are removed through formation of the stepped surfaces. A “stepped cavity” refers to a cavity having stepped surfaces. 
     The terrace region is formed in the staircase region  300 , which is located between the memory array region  100  and the peripheral device region  200  containing the at least one semiconductor device for the peripheral circuitry. The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the substrate ( 9 ,  10 ). In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure. 
     Each sacrificial material layer  42  other than a topmost sacrificial material layer  42  within the alternating stack ( 32 ,  42 ) laterally extends farther than any overlying sacrificial material layer  42  within the alternating stack ( 32 ,  42 ) in the terrace region. The terrace region includes stepped surfaces of the alternating stack ( 32 ,  42 ) that continuously extend from a bottommost layer within the alternating stack ( 32 ,  42 ) to a topmost layer within the alternating stack ( 32 ,  42 ). 
     Each vertical step of the stepped surfaces can have the height of one or more pairs of an insulating layer  32  and a sacrificial material layer. In one embodiment, each vertical step can have the height of a single pair of an insulating layer  32  and a sacrificial material layer  42 . In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd 1  such that each vertical step has the height of a plurality of pairs of an insulating layer  32  and a sacrificial material layer  42 , and the number of columns can be at least the number of the plurality of pairs. Each column of staircase can be vertically offset among one another such that each of the sacrificial material layers  42  has a physically exposed top surface in a respective column of staircases. In the illustrative example, two columns of staircases are formed for each block of memory stack structures to be subsequently formed such that one column of staircases provide physically exposed top surfaces for odd-numbered sacrificial material layers  42  (as counted from the bottom) and another column of staircases provide physically exposed top surfaces for even-numbered sacrificial material layers (as counted from the bottom). Configurations employing three, four, or more columns of staircases with a respective set of vertical offsets among the physically exposed surfaces of the sacrificial material layers  42  may also be employed. Each sacrificial material layer  42  has a greater lateral extent, at least along one direction, than any overlying sacrificial material layers  42  such that each physically exposed surface of any sacrificial material layer  42  does not have an overhang. In one embodiment, the vertical steps within each column of staircases may be arranged along the first horizontal direction hd 1 , and the columns of staircases may be arranged along a second horizontal direction hd 2  that is perpendicular to the first horizontal direction hd 1 . In one embodiment, the first horizontal direction hd 1  may be perpendicular to the boundary between the memory array region  100  and the staircase region  300 . 
     A retro-stepped dielectric material portion  65  (i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulating cap layer  70 , for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the retro-stepped dielectric material portion  65 . As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the retro-stepped dielectric material portion  65 , the silicon oxide of the retro-stepped dielectric material portion  65  may, or may not, be doped with dopants such as B, P, and/or F. 
     Optionally, drain select level isolation structures  72  ( FIG.  4 A ) can be formed through the insulating cap layer  70  and a subset of the sacrificial material layers  42  located at drain select levels. The drain select level isolation structures  72  can be formed, for example, by forming drain select level isolation trenches and filling the drain select level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the insulating cap layer  70 . 
     Referring to  FIGS.  4 A and  4 B , a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer  70  and the retro-stepped dielectric material portion  65 , and can be lithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region  100  and a second set of openings formed over the staircase region  300 . The pattern in the lithographic material stack can be transferred through the insulating cap layer  70  or the retro-stepped dielectric material portion  65 , and through the alternating stack ( 32 ,  42 ) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the alternating stack ( 32 ,  42 ) underlying the openings in the patterned lithographic material stack are etched to form memory openings  49  and support openings  19 . As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, is subsequently formed. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings  49  are formed through the insulating cap layer  70  and the entirety of the alternating stack ( 32 ,  42 ) in the memory array region  100 . The support openings  19  are formed through the retro-stepped dielectric material portion  65  and the portion of the alternating stack ( 32 ,  42 ) that underlie the stepped surfaces in the staircase region  300 . 
     The memory openings  49  extend through the entirety of the alternating stack ( 32 ,  42 ). The support openings  19  extend through a subset of layers within the alternating stack ( 32 ,  42 ). The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack ( 32 ,  42 ) can alternate to optimize etching of the materials in the alternating stack ( 32 ,  42 ). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings  49  and the support openings  19  can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing. 
     The memory openings  49  and the support openings  19  can extend from the top surface of the alternating stack ( 32 ,  42 ) to at least the horizontal plane including the topmost surface of the upper substrate semiconductor layer  10 . In one embodiment, an overetch into the upper substrate semiconductor layer  10  may be optionally performed after the top surface of the upper substrate semiconductor layer  10  is physically exposed at a bottom of each memory opening  49  and each support opening  19 . The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the upper substrate semiconductor layer  10  may be vertically offset from the un-recessed top surfaces of the upper substrate semiconductor layer  10  by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings  49  and the support openings  19  can be coplanar with the topmost surface of the upper substrate semiconductor layer  10 . 
     Each of the memory openings  49  and the support openings  19  may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings  49  can be formed in the memory array region  100 . A two-dimensional array of support openings  19  can be formed in the staircase region  300 . The lower substrate semiconductor layer  9  and the upper substrate semiconductor layer  10  collectively constitutes a substrate ( 9 ,  10 ), which can be a semiconductor substrate. Alternatively, the upper substrate semiconductor layer  10  may be omitted, and the memory openings  49  and the support openings  19  can be extend to a top surface of the lower substrate semiconductor layer  9 . 
       FIGS.  5 A- 5 P  illustrate structural changes in a memory opening  49  during formation of a first exemplary memory opening fill structure. The same structural change occurs simultaneously in each of the other memory openings  49  and in each of the support openings  19 . 
     Referring to  FIG.  5 A , a memory opening  49  in the exemplary device structure of  FIGS.  4 A and  4 B  is illustrated. The memory opening  49  extends through the insulating cap layer  70 , the alternating stack ( 32 ,  42 ), and optionally into an upper portion of the upper substrate semiconductor layer  10 . At this processing step, each support opening  19  can extend through the retro-stepped dielectric material portion  65 , a subset of layers in the alternating stack ( 32 ,  42 ), and optionally through the upper portion of the upper substrate semiconductor layer  10 . The recess depth of the bottom surface of each memory opening with respect to the top surface of the upper substrate semiconductor layer  10  can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the sacrificial material layers  42  can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch. 
     Referring to  FIG.  5 B , an optional pedestal channel portion (e.g., an epitaxial pedestal)  11  can be formed at the bottom portion of each memory opening  49  and each support openings  19 , for example, by selective epitaxy. Each pedestal channel portion  11  comprises a single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the upper substrate semiconductor layer  10 . In one embodiment, the top surface of each pedestal channel portion  11  can be formed above a horizontal plane including the top surface of a bottommost sacrificial material layer  42 . In this case, a source select gate electrode can be subsequently formed by replacing the bottommost sacrificial material layer  42  with a conductive material layer. The pedestal channel portion  11  can be a portion of a transistor channel that extends between a source region to be subsequently formed in the substrate ( 9 ,  10 ) and a drain region to be subsequently formed in an upper portion of the memory opening  49 . A memory cavity  49 ′ ( FIG.  5 D ) is present in the unfilled portion of the memory opening  49  above the pedestal channel portion  11 . In one embodiment, the pedestal channel portion  11  can comprise single crystalline silicon. In one embodiment, the pedestal channel portion  11  can have a doping of the first conductivity type, which is the same as the conductivity type of the upper substrate semiconductor layer  10  that the pedestal channel portion contacts. If an upper substrate semiconductor layer  10  is not present, the pedestal channel portion  11  can be formed directly on the lower substrate semiconductor layer  9 , which can have a doping of the first conductivity type. 
     Referring to  FIG.  5 C , annular lateral recesses  149  can be formed at levels of the insulating layers  32  that are not masked by the pedestal channel portion  11 . An additional annular lateral recess can be formed at the level of the insulating cap layer  70  around the memory opening  49 . The annular lateral recesses  149  can be formed by laterally recessing sidewalls of the insulating layers  32  relative to sidewalls of the spacer material layers (such as the sacrificial material layers  42 ) around the memory opening  49 . An isotropic etch process that etches the material of the insulating layers  32  selective to the material of the spacer material layers can be performed to laterally recess the physically exposed sidewalls of the insulating layers  32  relative to sidewalls of the spacer material layers (such as the sacrificial material layers). In one embodiment, the physically exposed surfaces of the insulating cap layer  70  may be isotropically recessed concurrently with formation of the annular lateral recesses  149 . In an illustrative example, the insulating layers  32  include silicon oxide, the spacer material layers  42  include silicon nitride or a semiconductor material (such as polysilicon), and the isotropic etch process comprises a wet etch process employing dilute hydrofluoric acid. 
     The duration of the isotropic etch process can be selected such that the lateral recess distance of the annular lateral recesses  149  can be in a range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although lesser and greater lateral recess distances can also be employed. The lateral recess distance refers to the lateral distance between a recessed sidewall of an insulating layer  32  relative to a sidewall of an immediately overlying spacer material layer (such as an immediately overlying sacrificial material layer  42 ) or relative to a sidewall of an immediately underlying spacer material layer. Each annular lateral recess  149  can have a volume of an annular cylinder, and is a portion of the memory opening  49 . Thus, the memory opening  49  includes a vertical stack of annular lateral recesses  149  provided at levels of the insulating layers  32 . 
     Referring to  FIG.  5 D , a blocking dielectric layer  52  can be conformally deposited on physically exposed surfaces of the insulating layers  32  and the spacer material layers (such as the sacrificial material layers  42 ). The blocking dielectric layer  52  can be deposited on the sidewalls of the insulating layers  32 , annular horizontal surfaces of the insulating layers  32  overlying or underlying a respective one of the annular lateral recesses  149 , sidewalls of the sacrificial material layers  42 , a bottom surface of the memory opening  49  (which may be a top surface of a pedestal channel portion  11  or a top surface of the upper substrate semiconductor layer  10  if a pedestal channel portion is not employed), and physically exposed surfaces of the insulating cap layer  70 . 
     The blocking dielectric layer  52  can include a single dielectric material layer or a stack of a plurality of dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer  52  can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride. 
     Non-limiting examples of dielectric metal oxides include aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), lanthanum oxide (LaO 2 ), yttrium oxide (Y 2 O 3 ), tantalum oxide (Ta 2 O 5 ), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric metal oxide layer can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the blocking dielectric layer  52  includes aluminum oxide. In one embodiment, the blocking dielectric layer  52  can include multiple dielectric metal oxide layers having different material compositions. 
     Alternatively or additionally, the blocking dielectric layer  52  can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer  52  can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer  52  can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. 
     The blocking dielectric layer  52  has a laterally-undulating vertical cross-sectional profile, and comprises laterally-protruding portions that laterally extend into the annular lateral recesses  149 . The laterally-protruding portions of the blocking dielectric layer  52  can be located at the levels of the insulating layers  32 . Outer sidewalls of the laterally-protruding portions of the blocking dielectric layer  52  contact sidewalls of the insulating layers  32 , and annular horizontal surfaces of the laterally-protruding portions of the blocking dielectric layer  52  contact annular horizontal surfaces of the spacer material layers (such as the sacrificial material layers  42 ). 
     Referring to  FIG.  5 E , a metal layer  66 L can be conformally deposited on the inner sidewalls of the blocking dielectric layer. The metal layer  66 L can include any metal that can form a metal-semiconductor alloy such as a metal silicide. In one embodiment, the metal layer  66 L can include at least one transition metal that can form a metal silicide. For example, the metal layer  66 L can include tungsten, titanium, cobalt, molybdenum, platinum, nickel, and/or any other transition metal that forms a metal silicide upon reaction with silicon. The metal layer  66 L can be deposited by a conformal deposition method such as a chemical vapor deposition process or an atomic layer deposition process. The thickness of the metal layer  66 L can be in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed. The thickness of the metal layer  66 L may be less than, equal to, or greater than one half of the thickness of each insulating layer  32 . Thus, the annular lateral recesses  149  may, or may not, have unfilled volumes after formation of the metal layer  66 L. 
     Referring to  FIG.  5 F , an optional patterning film  47  can be anisotropically deposited to cover the insulating cap layer  70  and the topmost laterally-protruding portion of the metal layer  66 L that overlies the topmost spacer material layer (such as the topmost sacrificial material layer  42 ). The patterning film  47  is deposited with high directionality, and thus, has a significantly greater thickness above the insulating cap layer  70  than at the bottom horizontal surface of the memory opening  49  (which may be the top surface of the pedestal channel portion  11 ). The patterning film  47  may be a film including amorphous carbon as a predominant component. For example, Advanced Patterning Film™ by Applied Materials Inc.™ may be employed for the patterning film  47 . Alternatively, the patterning film  47  can be omitted. 
     Portions of the metal layer located  66 L outside the annular lateral recesses  149  can be anisotropically etched by performing an anisotropic etch process. The anisotropic etch process can employ an etch chemistry that etches the material of the metal layer  66 L selective to the patterning film  47  (if present), selective to the material of the spacer material layers  42 , and selective to the material of the blocking dielectric layer  52  and/or to the material of the pedestal channel portion  11 . The anisotropic etch process can employ a reactive ion etch process. Remaining portions of the metal layer  66 L comprise the vertical stack of discrete metal portions  66 . The discrete metal portions  66  can be formed within a respective one of the annular lateral recesses  149  of the memory opening  49 . Thus, the vertical stack of discrete metal portions  66  can be formed in the annular lateral recesses  149 . The vertical stack of discrete metal portions  66  is formed directly on portions of an inner sidewall of the blocking dielectric layer  52  located at levels of the insulating layers  32 . 
     The discrete metal portions  66  may have a C-shaped (e.g., clam shaped) vertical cross-sectional profile having vertical portion connecting two horizontal portions if the thickness of the metal layer  66 L is less than one half of the thickness of each insulating layer  32 , or may have a rectangular vertical cross-sectional profile if the thickness of the metal layer  66 L is greater than one half of the thickness of each insulating layer  32 . In one embodiment, the discrete metal portion  66  can comprise, and/or can consist essentially of, tungsten, titanium, cobalt, molybdenum, platinum, nickel, and/or any other transition metal that forms a metal silicide upon reaction with silicon. 
     Referring to  FIG.  5 G , the patterning film  47  (if present) can be subsequently removed, for example, by ashing. If the patterning film  47  is omitted, then the discrete metal portion  66  at the level of the insulating cap layer  70  is also not present because it would be removed during the anisotropic etch process shown in  FIG.  5 F . 
     Referring to  FIG.  5 H , a semiconductor material layer  54 L can be conformally deposited on the physically exposed surfaces of the vertical stack of the metal portions  66  and on the physically exposed surfaces of the blocking dielectric layer  52 . The semiconductor material layer  54 L includes a semiconductor material that can form a metal-semiconductor alloy with the material of the metal portions  66 . For example, the semiconductor material layer  54 L can include silicon and/or germanium. In one embodiment, the semiconductor material layer  54 L can include amorphous silicon, polysilicon, germanium, and/or a silicon-germanium alloy. The thickness of the semiconductor material layer  54 L can be selected such that the entirety of the vertical stack of discrete metal portions  66  can react with the semiconductor material of the semiconductor material layer  54 L during a subsequent anneal process. In one embodiment, the semiconductor material layer  54 L can have a thickness in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed. 
     Referring to  FIG.  5 J , an anisotropic etch process can be performed to remove horizontal portions of the semiconductor material layer  54 L and the metal layer  66 L (if present) that overlie the insulating cap layer  70 , and to remove a horizontal portion of the semiconductor material layer  54 L located at the bottom of the memory opening  49  (such as the horizontal portion of the semiconductor material layer  54 L located above the pedestal channel portion  11 ). 
     Referring to  FIG.  5 J , a thermal anneal process is performed at an elevated temperature that induces formation of a metal-semiconductor alloy between the material of the metal portions  66  and the material of the semiconductor material layer  54 L. The elevated temperature may be in a range from 400 degrees Celsius to 1,000 degrees Celsius, although lower and higher temperatures may also be employed depending on the composition of the metal-semiconductor alloy. It is not necessary to form a low-resistance phase metal-semiconductor alloy as required for typical semiconductor applications in this case. Even high-resistance intermediate phase metal-semiconductor alloys formed at a relatively low temperature are sufficient provided that such metal-semiconductor alloys can be subsequently removed selective to unreacted portions of the semiconductor material layer  54 L in a selective etch process. Generally, the thickness of the metal layer  66 L and the thickness of the semiconductor material layer  54 L can be selected to ensure that the entire volume of the metal portions  66  react with the semiconductor material layer  54 L to form metal-semiconductor alloy portions  67 . A vertical stack of metal-semiconductor alloy portions  67  can be formed by reacting the vertical stack of metal portions  66  with portions of the semiconductor material layer  54 L located at levels of the insulating layers  32 . Unreacted portions of the semiconductor material layer  54 L remain at each level of the sacrificial material layers  42  located over the top surface of the pedestal channel portion  11 . The set of unreacted portions of the semiconductor material layer  54 L in the memory opening  49  comprise a vertical stack of semiconductor material portions  54 S. 
     Referring to  FIG.  5 K , a selective isotropic etch process that etches the material of the metal-semiconductor alloy portions  67  selective to the material of the semiconductor material portions  54 S can be performed. The vertical stack of metal-semiconductor alloy portions  67  is removed selective to unreacted portions of the semiconductor material layer  54 L, i.e., the vertical stack of semiconductor material portions  54 S. The vertical stack of semiconductor material portions  54 S remain at levels of the spacer material layers (such as the sacrificial material layers  42 ). In one embodiment, each semiconductor portion  54 S can have a have a tubular shape. As used herein, a “tubular” element refers to an element having an inner cylindrical sidewall, an outer cylindrical sidewall, and a substantially uniform thickness between the inner sidewall and the outer sidewall. The vertical stack of semiconductor material portions  54 S can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the blocking dielectric layer  52  are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions  67 . 
     Referring to  FIG.  5 L , a tunneling dielectric layer  56  can be deposited employing a conformal deposition process such as a chemical vapor deposition process. The tunneling dielectric layer  56  includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The tunneling dielectric layer  56  can be formed directly on the portions of the inner sidewall of the blocking dielectric layer  52  that are physically exposed and located at the levels of the insulating layers  32 . The tunneling dielectric layer  56  can be formed directly on the vertical stack of discrete cylindrical semiconductor material portions  54 S. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer  56  can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer  56  can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer  56  can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer  56  can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. 
     An optional first semiconductor channel layer  601  can be subsequently deposited on the tunneling dielectric layer  56  by a conformal deposition process. The first semiconductor channel layer  601  includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer  601  includes amorphous silicon or polysilicon. The first semiconductor channel layer  601  can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer  601  can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. 
     Referring to  FIG.  5 M , an optional patterning film  77  can be anisotropically deposited to cover the insulating cap layer  70  and the topmost portion of the first semiconductor channel layer  601  that overlies the topmost spacer material layer (such as the topmost sacrificial material layer  42 ). The patterning film  77  is deposited with high directionality, and thus, has a significantly greater thickness above the insulating cap layer  70  than at the bottom horizontal surface of the memory opening  49  (which may be the top surface of the pedestal channel portion  11 ). The patterning film  77  may be a film including amorphous carbon as a predominant component. For example, Advanced Patterning Film™ by Applied Materials Inc.™ may be employed for the patterning film  77 . Alternatively, the patterning film  77  may be omitted. 
     An anisotropic etch process can be performed to remove the horizontal bottom portions of the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , and the blocking dielectric layer  52  located over the pedestal channel portion  11  (or located above the upper substrate semiconductor layer  10  in case a pedestal channel portion is not present) at the bottom of each memory opening  49 . A center portion of the top surface of the pedestal channel portion  11  can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion  11  is not present in the memory opening  49 , a portion of the horizontal surface of the upper substrate semiconductor layer  10  can be vertically recessed underneath the memory opening  49 . If present, the patterning film  77  can be subsequently removed, for example, by ashing. 
     A surface of the pedestal channel portion  11  (or a surface of the upper substrate semiconductor layer  10  in case the pedestal channel portions  11  are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , and the blocking dielectric layer  52 . Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity  49 ′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity  49 ′ is vertically offset from the topmost surface of the pedestal channel portion  11  (or of the upper substrate semiconductor layer  10  in case pedestal channel portions  11  are not employed) by a recess distance. The vertical stack of semiconductor material portions  54 S function as discrete charge storage elements that are floating gates. A set of the blocking dielectric layer  52 , the vertical stack of semiconductor material portions  54 S, and the tunneling dielectric layer  56  in a memory opening  49  constitutes a memory film  50 . In one embodiment, the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , and the blocking dielectric layer  52  can have vertically coincident sidewalls. 
     Referring to  FIG.  5 N , a second semiconductor channel layer  602  can be deposited directly on the semiconductor surface of the pedestal channel portion  11  or the upper substrate semiconductor layer  10  if the pedestal channel portion  11  is omitted, and directly on the first semiconductor channel layer  601  (if present). The second semiconductor channel layer  602  includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer  602  includes amorphous silicon or polysilicon. The second semiconductor channel layer  602  can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer  602  can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second semiconductor channel layer  602  may partially fill the memory cavity  49 ′ in each memory opening, or may fully fill the cavity in each memory opening. 
     The materials of the first semiconductor channel layer  601  and the second semiconductor channel layer  602  are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer  601  and the second semiconductor channel layer  602 . The combination of the blocking dielectric layer  52 , the tunneling dielectric layer  56 , the first semiconductor channel layer  601 , and the second semiconductor channel layer  602  can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers  32 . 
     Referring to  FIG.  5 O , in case the memory cavity  49 ′ in each memory opening is not completely filled by the second semiconductor channel layer  602 , a dielectric core layer can be deposited in the memory cavity  49 ′ to fill any remaining portion of the memory cavity  49 ′ within each memory opening. The dielectric core layer includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating. The horizontal portion of the dielectric core layer can be removed, for example, by a recess etch from above the top surface of the second semiconductor channel layer  602 . Further, the material of the dielectric core layer can be vertically recessed selective to the semiconductor material of the second semiconductor channel layer  602  into each memory opening  49  down to a depth between a first horizontal plane including the top surface of the insulating cap layer  70  and a second horizontal plane including the bottom surface of the insulating cap layer  70 . Each remaining portion of the dielectric core layer constitutes a dielectric core  62 . 
     Referring to  FIG.  5 P , a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores  62 . The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of the doped semiconductor material can be in a range from 5.0×10 18 /cm 3  to 2.0×10 21 /cm 3 , although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. 
     Excess portions of the deposited semiconductor material can be removed from above the top surface of the insulating cap layer  70 , for example, by chemical mechanical planarization (CMP) or a recess etch. Each remaining portion of the semiconductor material having a doping of the second conductively type comprises a doped semiconductor region having a p-n junction at an interface with the vertical semiconductor channel  60 . In one embodiment, the doped semiconductor region is employed as a drain region  63  for a vertical NAND string. The horizontal portion of the second semiconductor channel layer  602  located above the top surface of the insulating cap layer  70  can be concurrently removed by a planarization process. Each remaining portion of the second semiconductor channel layer  602  can be located entirety within a memory opening  49  or entirely within a support opening  19 . 
     Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region  63 . Each adjoining pair of the optional first semiconductor channel layer  601  and the second semiconductor channel layer  602  can collectively form a vertical semiconductor channel  60  through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel  60  is turned on. A tunneling dielectric layer  56  is surrounded by a vertical stack of semiconductor material portions  54 S, and laterally surrounds a portion of the vertical semiconductor channel  60 . Each adjoining set of a tunneling dielectric layer  56 , a vertical stack of semiconductor material portions  54 S, and a blocking dielectric layer  52  collectively constitute a memory film  50 , which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours. 
     Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . The memory stack structure  55  is a combination of a semiconductor channel  60 , a tunneling dielectric layer  56 , a plurality of memory elements comprising a vertical stack of discrete (i.e., vertically separated from each other) semiconductor material portions  54 S, and a blocking dielectric layer  52 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . Each combination of a pedestal channel portion  11  (if present), a memory film  50 , a vertical semiconductor channel  60 , a dielectric core  62 , and a drain region  63  within each support opening  19  fills the respective support openings  19 , and constitutes a support pillar structure. 
       FIGS.  5 Q and  5 R  illustrate an alternative configuration of the first exemplary memory opening fill structure. Referring to  FIG.  5 Q , the alternative configuration of the first exemplary memory opening fill structure can be derived from the structure illustrated in  FIG.  5 K  by filling the annular lateral recesses  149  with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses  149  after removal of the vertical stack of metal-semiconductor alloy portions  67 . In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer  52 . For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000. 
     Portions of the dielectric fill material can be removed from outside the annular lateral recesses  149  by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the semiconductor material portions  54 S and the material of the blocking dielectric layer  52 . Remaining portions of the dielectric fill material filling the annular lateral recesses  149  comprise a vertical stack of annular insulating material portions  57 . In case an anisotropic etch process is employed to pattern the annular insulating material portions  57 , inner sidewalls of the annular insulating material portions  57  may be vertically coincident with inner sidewalls of the semiconductor material portions  54 S. 
     Referring to  FIG.  5 R , the processing steps of  FIGS.  5 L- 5 P  can be performed to provide an alternative configuration of the second exemplary memory opening fill structure  58 . In this case, the tunneling dielectric layer  56  can be formed directly on the vertical stack of annular insulating material portions  57 . The memory film  50  can comprise the blocking dielectric layer  52 , the vertical stack of semiconductor material portions  54 S, the vertical stack of annular insulating material portions  57  (which can contact the vertical stack of semiconductor material portions  54 S), and the tunneling dielectric layer  56 . 
       FIGS.  6 A- 6 J  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a second exemplary memory opening fill structure according to an embodiment of the present disclosure. The second exemplary memory opening fill structure can be formed within each memory opening  49  in lieu of the first exemplary memory opening fill structure. 
     Referring to  FIG.  6 A , a memory opening  49  is illustrated during formation of the second exemplary memory opening fill structures in which the metal layer self-segregates into the annular lateral recesses  149  during an anneal. Specifically, the structure illustrated in  FIG.  6 A  can be derived from the structure illustrated in  FIG.  5 D  by conformally depositing a metal layer  166 L on the inner sidewalls of the blocking dielectric layer  52 . The metal layer  166 L can include any metal that can spontaneously segregate into the annular lateral recesses  149  in a subsequent anneal process. For example, the metal layer  166 L can include, and/or consist essentially of, cobalt. 
     Referring to  FIG.  6 B , a thermal anneal process is performed at an elevated temperature to induce thermal migration of the metal layer  166 L into the annular lateral recesses  149 . The metal layer  166 L self-segregates into the vertical stack of discrete metal portions  166  during the thermal anneal process in order to reduce the total surface area. The elevated temperature of the thermal anneal process can be in a range from 300 degrees Celsius to 1,000 degrees Celsius, although lower and higher temperatures may also be employed depending on the composition of the metal layer  166 L. The thickness of the metal layer  166 L as deposited at the processing steps of  FIG.  6 A  can be selected such that the discrete metal portions  166  are confined within a respective one of the annular lateral recesses  149 , and are not in direct contact with each other (i.e., vertically separated from each other). Inner sidewalls of the blocking dielectric layer  52  can be physically exposed at each level of the spacer material layers (such as the sacrificial material layers  42 ). 
     Referring to  FIG.  6 C , the processing steps of  FIG.  5 H  can be performed to form a semiconductor material layer  54 L. The semiconductor material layer  54 L can be conformally deposited over the physically exposed surfaces of the blocking dielectric layer  52  and the discrete metal portions  166 , each of which may have an annular configuration. 
     Referring to  FIG.  6 D , a thermal anneal process is performed at an elevated temperature that induces formation of a metal-semiconductor alloy between the material of the metal portions  166  and the material of the semiconductor material layer  54 L. The elevated temperature may be in a range from 400 degrees Celsius to 1,000 degrees Celsius, although lower and higher temperatures may also be employed depending on the composition of the metal-semiconductor alloy. Generally, the thickness of the metal layer  166 L and the thickness of the semiconductor material layer  54 L can be selected to ensure that the entire volume of the metal portions  166  react with the semiconductor material layer  54 L to form metal-semiconductor alloy portions  167 . A vertical stack of metal-semiconductor alloy portions  167  can be formed by reacting the vertical stack of metal portions  166  with portions of the semiconductor material layer  54 L located at levels of the insulating layers  32 . Unreacted portions of the semiconductor material layer  54 L remain at each level of the sacrificial material layers  42  located over the top surface of the pedestal channel portion  11 . The set of unreacted portions of the semiconductor material layer  54 L in the memory opening  49  comprise a vertical stack of semiconductor material portions  54 S. 
     Referring to  FIG.  6 E , a selective isotropic etch process that etches the material of the metal-semiconductor alloy portions  167  selective to the material of the semiconductor material portions  54 S can be performed. The vertical stack of metal-semiconductor alloy portions  167  is removed selective to unreacted portions of the semiconductor material layer  54 L, i.e., the vertical stack of semiconductor material portions  54 S. The vertical stack of semiconductor material portions  54 S remain at levels of the spacer material layers (such as the sacrificial material layers  42 ). In one embodiment, each semiconductor portion  54 S can have a have a tubular shape. The vertical stack of semiconductor material portions  54 S can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the blocking dielectric layer  52  are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions  167 . 
     Referring to  FIG.  6 F , the processing steps of  FIG.  5 L  can be performed to form a tunneling dielectric layer  56  and a first semiconductor channel layer  601 . 
     Referring to  FIG.  6 G , the processing steps of  FIG.  5 M  can be performed to deposit an optional patterning film  77 , and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , and the blocking dielectric layer  52  located over the pedestal channel portion  11  (or located above the upper substrate semiconductor layer  10  in case a pedestal channel portion is not present) at the bottom of each memory opening  49 . A center portion of the top surface of the pedestal channel portion  11  can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion  11  is not present in the memory opening  49 , a portion of the horizontal surface of the upper substrate semiconductor layer  10  can be vertically recessed underneath the memory opening  49 . The patterning film  77  (if present) can be subsequently removed, for example, by ashing. 
     Referring to  FIG.  6 H , the processing steps of  FIG.  5 N  can be performed to form a second semiconductor channel layer  602 . The materials of the first semiconductor channel layer  601  and the second semiconductor channel layer  602  are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer  52 , the tunneling dielectric layer  56 , the first semiconductor channel layer  601 , and the second semiconductor channel layer  602  can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers  32 . 
     Referring to  FIG.  6 I , the processing steps of  FIG.  5 O  can be performed to form a dielectric core  62  in each memory opening  49 . 
     Referring to  FIG.  6 J , the processing steps of  FIG.  5 P  can be performed to form a doped semiconductor portion such as a drain region  63  at an upper portion of each memory opening  49 . Each adjoining pair of a first semiconductor channel layer  601  (if present) and a second semiconductor channel layer  602  can collectively form a vertical semiconductor channel  60  through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel  60  is turned on. A tunneling dielectric layer  56  is surrounded by a vertical stack of semiconductor material portions  54 S, and laterally surrounds a portion of the vertical semiconductor channel  60 . Each adjoining set of a tunneling dielectric layer  56 , a vertical stack of semiconductor material portions  54 S, and a blocking dielectric layer  52  collectively constitute a memory film  50 , which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. 
     Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . The memory stack structure  55  is a combination of a semiconductor channel  60 , a tunneling dielectric layer  56 , a plurality of memory elements comprising a vertical stack of semiconductor material portions  54 S, and a blocking dielectric layer  52 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . Each combination of a pedestal channel portion  11  (if present), a memory film  50 , a vertical semiconductor channel  60 , a dielectric core  62 , and a drain region  63  within each support opening  19  fills the respective support openings  19 , and constitutes a support pillar structure. 
       FIGS.  6 K and  6 L  illustrate an alternative configuration of the second exemplary memory opening fill structure. Referring to  FIG.  6 K , the alternative configuration of the first exemplary memory opening fill structure can be derived from the structure illustrated in  FIG.  6 E  by filling the annular lateral recesses  149  with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses  149  after removal of the vertical stack of metal-semiconductor alloy portions  67 . In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer  52 . For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000. 
     Portions of the dielectric fill material can be removed from outside the annular lateral recesses  149  by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the semiconductor material portions  54 S and the material of the blocking dielectric layer  52 . Remaining portions of the dielectric fill material filling the annular lateral recesses  149  comprise a vertical stack of annular insulating material portions  57 . In case an anisotropic etch process is employed to pattern the annular insulating material portions  57 , inner sidewalls of the annular insulating material portions  57  may be vertically coincident with inner sidewalls of the semiconductor material portions  54 S. 
     Referring to  FIG.  6 L , the processing steps of  FIGS.  6 F- 6 J  can be performed to provide an alternative configuration of the second exemplary memory opening fill structure  58 . In this case, the tunneling dielectric layer  56  can be formed directly on the vertical stack of annular insulating material portions  57 . The memory film  50  can comprise the blocking dielectric layer  52 , the vertical stack of semiconductor material portions  54 S, the vertical stack of annular insulating material portions  57  (which can contact the vertical stack of semiconductor material portions  54 S), and the tunneling dielectric layer  56 . 
       FIGS.  7 A- 7 N  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a third exemplary memory opening fill structure containing a hybrid charge storage structures containing a continuous charge storage dielectric layer and discrete floating gates, according to an embodiment of the present disclosure. The third exemplary memory opening fill structure can be formed within each memory opening  49  in lieu of the first or second exemplary memory opening fill structure described above. 
     Referring to  FIG.  7 A , a memory opening  49  is illustrated after formation of annular lateral recesses  149  at levels of the insulating layers  32 . The first exemplary structure of  FIG.  7 A  may be the same as the first exemplary structure illustrated in  FIG.  5 C . 
     Referring to  FIG.  7 B , the processing steps of  FIG.  5 D  can be performed to form a blocking dielectric layer  52 . Subsequently, a continuous charge storage dielectric layer, such as a silicon nitride layer  53 , can be deposited on the physically exposed surfaces of the blocking dielectric layer  52  by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. The silicon nitride layer  53  can have a thickness in a range from 1 nm to 8 nm, such as from 2 nm to 6 nm, although lesser and greater thicknesses can also be employed. The silicon nitride layer  53  vertically extends through layers of the alternating stack ( 32 ,  42 ), and contacts an outer sidewall of each discrete tubular semiconductor material portion  54 S within the vertical stack of discrete tubular semiconductor material portions  54 S. The silicon nitride layer  53  can be in contact with the inner sidewall of the blocking dielectric layer  52 . 
     Referring to  FIG.  7 C , the processing steps of  FIG.  5 E  can be performed to form a metal layer  66 L directly on the silicon nitride layer  53 . 
     Referring to  FIG.  7 D , the processing steps of  FIG.  5 F  can optionally be performed to anisotropically deposit an optional patterning film  47 , and to anisotropically etch portions of the metal layer  66 L that are not masked by the patterning film  47 . Remaining portions of the metal layer  66 L after the anisotropic etch process include a vertical stack of discrete metal portions  66 . Alternatively, if the metal layer  66 L comprised cobalt, then it may be self-segregated into discrete metal portions  66  by an anneal as described with respect to  FIG.  6 B  above. 
     Referring to  FIG.  7 E , the patterning film  47  (if present) can be subsequently removed, for example, by ashing. 
     Referring to  FIG.  7 F , the processing steps of  FIG.  5 H  can be performed to conformally deposit a semiconductor material layer  54 L. 
     Referring to  FIG.  7 G , the processing steps of  FIG.  5 I  can be performed to anisotropically etch horizontal portions of the semiconductor material layer  54 L and the metal layer  66 L that overlie the insulating cap layer  70 , and to remove a horizontal portion of the semiconductor material layer  54 L located at the bottom of the memory opening  49  (such as the horizontal portion of the semiconductor material layer  54 L located above the pedestal channel portion  11 ). 
     Referring to  FIG.  7 H , the processing steps of  FIG.  5 J  can be performed. Specifically, a thermal anneal process is performed at an elevated temperature that induces formation of a metal-semiconductor alloy between the material of the metal portions  66  and the material of the semiconductor material layer  54 L. Generally, the thickness of the metal layer  66 L and the thickness of the semiconductor material layer  54 L can be selected to ensure that the entire volume of the metal portions  66  react with the semiconductor material layer  54 L to form metal-semiconductor alloy portions  67 . A vertical stack of metal-semiconductor alloy portions  67  can be formed by reacting the vertical stack of metal portions  66  with portions of the semiconductor material layer  54 L located at levels of the insulating layers  32 . Unreacted portions of the semiconductor material layer  54 L remain at each level of the sacrificial material layers  42  located over the top surface of the pedestal channel portion  11 . The set of unreacted portions of the semiconductor material layer  54 L in the memory opening  49  comprise a vertical stack of semiconductor material portions  54 S. 
     Referring to  FIG.  7 I , the processing steps of  5 K can be performed. Specifically, a selective isotropic etch process that etches the material of the metal-semiconductor alloy portions  67  selective to the material of the semiconductor material portions  54 S can be performed. The vertical stack of metal-semiconductor alloy portions  67  is removed selective to unreacted portions of the semiconductor material layer  54 L, i.e., the vertical stack of semiconductor material portions  54 S. The vertical stack of semiconductor material portions  54 S remain at levels of the spacer material layers (such as the sacrificial material layers  42 ). In one embodiment, each semiconductor portion  54 S can have a have a tubular shape. The vertical stack of semiconductor material portions  54 S can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the silicon nitride layer  53  are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions  67 . 
     Referring to  FIG.  7 J , the processing steps of  FIG.  5 L  can be performed to form the tunneling dielectric layer  56  and the optional first semiconductor channel layer  601 . 
     Referring to  FIG.  7 K , the processing steps of  FIG.  5 M  can optionally be performed to anisotropically deposit a patterning film  77  over the insulating cap layer  70  and the topmost portion of the first semiconductor channel layer  601  that overlies the topmost spacer material layer (such as the topmost sacrificial material layer  42 ). An anisotropic etch process can be performed to remove the horizontal bottom portions of the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , the silicon nitride layer  53 , and the blocking dielectric layer  52  located over the pedestal channel portion  11  (or located above the upper substrate semiconductor layer  10  in case a pedestal channel portion is not present) at the bottom of each memory opening  49 . A center portion of the top surface of the pedestal channel portion  11  can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion  11  is not present in the memory opening  49 , a portion of the horizontal surface of the upper substrate semiconductor layer  10  can be vertically recessed underneath the memory opening  49 . The patterning film  77  can be subsequently removed, for example, by ashing. 
     A surface of the pedestal channel portion  11  (or a surface of the upper substrate semiconductor layer  10  in case the pedestal channel portions  11  are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , and the blocking dielectric layer  52 . Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity  49 ′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity  49 ′ is vertically offset from the topmost surface of the pedestal channel portion  11  (or of the upper substrate semiconductor layer  10  in case pedestal channel portions  11  are not employed) by a recess distance. The vertical stack of semiconductor material portions  54 S function as discrete charge storage elements that are floating gates. The continuous silicon nitride layer  53  functions as an additional charge storage material portion that continuously extends through each layer of the alternating stack ( 32 ,  42 ) located above the horizontal plane including the top surface of the pedestal channel portion  11 . The combination of the silicon nitride layer  53  and the vertical stack of semiconductor material portions  54 S constitute a composite charge storage structure including charge storage elements at each level of the spacer material layers (such as the sacrificial material layers  42 ). A set of the blocking dielectric layer  52 , the silicon nitride layer  53 , the vertical stack of semiconductor material portions  54 S, and the tunneling dielectric layer  56  in a memory opening  49  constitutes a memory film  50 . In one embodiment, the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , the silicon nitride layer  53 , and the blocking dielectric layer  52  can have vertically coincident sidewalls. 
     Referring to  FIG.  7 L , the processing steps of  FIG.  5 N  can be performed to deposit a second semiconductor channel layer  602  directly on the semiconductor surface of the pedestal channel portion  11  or the upper substrate semiconductor layer  10  if the pedestal channel portion  11  is omitted, and directly on the first semiconductor channel layer  601 . The combination of the blocking dielectric layer  52 , the silicon nitride layer  53 , the tunneling dielectric layer  56 , the first semiconductor channel layer  601 , and the second semiconductor channel layer  602  can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers  32 . 
     Referring to  FIG.  7 M , the processing steps of  50  can be performed a dielectric core  62  in each memory opening  49 . 
     Referring to  FIG.  7 N , the processing steps of  FIG.  5 P  can be performed to form a doped semiconductor material portion such as a drain region  63 . Each adjoining pair of a first semiconductor channel layer  601  and a second semiconductor channel layer  602  can collectively form a vertical semiconductor channel  60  through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel  60  is turned on. Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . The memory stack structure  55  is a combination of a semiconductor channel  60 , a tunneling dielectric layer  56 , a plurality of memory elements comprising a vertical stack of semiconductor material portions  54 S and portions of the silicon nitride layer  53  located at the levels of the spacer material layers  42 , and a blocking dielectric layer  52 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . Each combination of a pedestal channel portion  11  (if present), a memory film  50 , a vertical semiconductor channel  60 , a dielectric core  62 , and a drain region  63  within each support opening  19  fills the respective support openings  19 , and constitutes a support pillar structure. 
     In one embodiment, the tunneling dielectric layer  56  has a laterally-undulating vertical cross-sectional profile, and comprises laterally-protruding portions located at levels of the insulating layers  32  and contacting horizontal annular surfaces of the blocking dielectric layer  52  and overlying or underlying portions of the spacer material layers (such as the sacrificial material layers  42 ) that are proximal to the vertical stack of discrete tubular semiconductor material portions  54 S. 
       FIGS.  7 O and  7 P  illustrate an alternative configuration of the third exemplary memory opening fill structure. Referring to  FIG.  7 O , the alternative configuration of the third exemplary memory opening fill structure can be derived from the structure illustrated in  FIG.  7 I  by filling the annular lateral recesses  149  with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses  149  after removal of the vertical stack of metal-semiconductor alloy portions  67 . In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer  52 . For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000. 
     Portions of the dielectric fill material can be removed from outside the annular lateral recesses  149  by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the semiconductor material portions  54 S and the material of the blocking dielectric layer  52 . Remaining portions of the dielectric fill material filling the annular lateral recesses  149  comprise a vertical stack of annular insulating material portions  57 . In case an anisotropic etch process is employed to pattern the annular insulating material portions  57 , inner sidewalls of the annular insulating material portions  57  may be vertically coincident with inner sidewalls of the semiconductor material portions  54 S. 
     Referring to  FIG.  7 P , the processing steps of  FIGS.  7 J- 7 N  can be performed to provide an alternative configuration of the third exemplary memory opening fill structure  58 . In this case, the tunneling dielectric layer  56  can be formed directly on the vertical stack of annular insulating material portions  57 . The memory film  50  can comprise the blocking dielectric layer  52 , the silicon nitride layer  53 , the vertical stack of semiconductor material portions  54 S, the vertical stack of annular insulating material portions  57  (which can contact the vertical stack of semiconductor material portions  54 S), and the tunneling dielectric layer  56 . 
     The memory opening fill structure of  FIG.  7 P  comprises a vertical stack of annular insulating material portions  57  located at each level of the insulating layers  32  between the blocking dielectric layer  52  and the tunneling dielectric layer  56 . The tunneling dielectric layer  56  comprises a straight outer sidewall contacting each annular insulating material portion  57  within the vertical stack of annular insulating material portions  57  and contacting the vertical stack of discrete tubular semiconductor material portions  54 S. 
     In the third exemplary memory opening fill structure  58  of  FIG.  7 N  and the alternative embodiment of  FIG.  7 P , all surfaces of the vertical stack of discrete tubular semiconductor material portions  54 S are in contact with a surface of the silicon nitride liner  53  or a surface of the tunneling dielectric layer  56 . 
     The combination of the silicon nitride layer  53  and the vertical stack of discrete tubular semiconductor material portions  54 S constitutes charge storage structures ( 53 ,  54 S). Generally, the charge storage structures ( 53 ,  54 S) comprises a vertical stack of discrete tubular semiconductor material portions  54 S and at least one continuous silicon nitride material portion in contact with the vertical stack of discrete tubular semiconductor material portions  54 S. In one embodiment, the at least one silicon nitride material portion comprises a silicon nitride layer  53  vertically extending through layers of the alternating stack ( 32 ,  42 ) and contacting an outer sidewall of each discrete tubular semiconductor material portion  54 S within the vertical stack of discrete tubular semiconductor material portions  54 S. In one embodiment shown in  FIG.  7 N , at the level of the insulating layers  32 , the silicon nitride layer  53  is in contact with an inner sidewall of the blocking dielectric layer  52  and the outer sidewall of the tunneling dielectric layer  56 . In one embodiment, all surfaces of the vertical stack of discrete tubular semiconductor material portions  54 S can be in contact with a surface of the silicon nitride liner  53  or a surface of the tunneling dielectric layer  56 . 
       FIGS.  8 A- 8 F  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a fourth exemplary memory opening fill structure containing discrete charge storage dielectric portions according to an embodiment of the present disclosure. The fourth exemplary memory opening fill structure can be formed within each memory opening  49  in lieu of the first, second, or third exemplary memory opening fill structure described above. 
     Referring to  FIG.  8 A , the structure for forming a fourth exemplary memory opening fill structure can be derived from the structure of  FIG.  5 K , the structure of  FIG.  6 E , or the structure of  FIG.  7 I  by nitriding the vertical stack of semiconductor material portions  54 S. The vertical stack of semiconductor material portions  54 S is at least partially converted into a vertical stack of silicon nitride material portions  54 N, which may be a vertical stack of discrete tubular silicon nitride material portions  54 N. In one embodiment, if the vertical stack of semiconductor material portions  54 S completely converted into a vertical stack of silicon nitride material portions  54 N, then each silicon nitride material portion  54 N may have a graded silicon-to-nitrogen ratio with a lower ratio at the inner portion facing the memory opening  49  than at the outer portion facing the spacer material layers  42 . In one embodiment, the thickness of each silicon nitride material portion  54 N can be in a range from 3 nm to 30 nm, such as from 5 nm to 15 nm, although lesser and greater thicknesses can also be employed. 
     Referring to  FIG.  8 B , the processing steps of  FIG.  5 L  can be performed to form the blocking dielectric layer  52  and an optional first semiconductor channel layer  601 . 
     Referring to  FIG.  8 C , the processing steps of  FIG.  5 M  can be performed to optionally deposit a patterning film  77 , and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer  601  (if present), the tunneling dielectric layer  56 , and the blocking dielectric layer  52  located over the pedestal channel portion  11  (or located above the upper substrate semiconductor layer  10  in case a pedestal channel portion is not present) at the bottom of each memory opening  49 . A center portion of the top surface of the pedestal channel portion  11  can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion  11  is not present in the memory opening  49 , a portion of the horizontal surface of the upper substrate semiconductor layer  10  can be vertically recessed underneath the memory opening  49 . The patterning film  77  can be subsequently removed, for example, by ashing. 
     Referring to  FIG.  8 D , the processing steps of  FIG.  5 N  can be performed to form a second semiconductor channel layer  602 . The materials of the first semiconductor channel layer  601  and the second semiconductor channel layer  602  are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer  52 , the tunneling dielectric layer  56 , the first semiconductor channel layer  601 , and the second semiconductor channel layer  602  can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers  32 . 
     Referring to  FIG.  8 E , the processing steps of  FIG.  5 O  can be performed to form a dielectric core  62  in each memory opening  49 . 
     Referring to  FIG.  8 F , the processing steps of  FIG.  5 P  can be performed to form a doped semiconductor portion such as a drain region  63  at an upper portion of each memory opening  49 . Each adjoining pair of a first semiconductor channel layer  601  and a second semiconductor channel layer  602  can collectively form a vertical semiconductor channel  60  through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel  60  is turned on. A tunneling dielectric layer  56  is surrounded by a vertical stack of silicon nitride material portions  54 N, and laterally surrounds a portion of the vertical semiconductor channel  60 . Each adjoining set of a tunneling dielectric layer  56 , a vertical stack of silicon nitride material portions  54 N, and a blocking dielectric layer  52  collectively constitute a memory film  50 , which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. 
     Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . The memory stack structure  55  is a combination of a semiconductor channel  60 , a tunneling dielectric layer  56 , a plurality of memory elements comprising a vertical stack of silicon nitride material portions  54 N, and a blocking dielectric layer  52 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . Each combination of a pedestal channel portion  11  (if present), a memory film  50 , a vertical semiconductor channel  60 , a dielectric core  62 , and a drain region  63  within each support opening  19  fills the respective support openings  19 , and constitutes a support pillar structure. 
       FIGS.  8 G and  8 H  illustrate an alternative configuration of the fourth exemplary memory opening fill structure. Referring to  FIG.  8 G , the alternative configuration of the fourth exemplary memory opening fill structure can be derived from the structure illustrated in  FIG.  8 A  by filling the annular lateral recesses  149  with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses  149  after removal of the vertical stack of metal-semiconductor alloy portions  67 . In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer  52 . For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000. 
     Portions of the dielectric fill material can be removed from outside the annular lateral recesses  149  by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the silicon nitride material portions  54 N and the material of the blocking dielectric layer  52 . Remaining portions of the dielectric fill material filling the annular lateral recesses  149  comprise a vertical stack of annular insulating material portions  57 . In case an anisotropic etch process is employed to pattern the annular insulating material portions  57 , inner sidewalls of the annular insulating material portions  57  may be vertically coincident with inner sidewalls of the silicon nitride material portions  54 N. 
     Referring to  FIG.  8 H , the processing steps of  FIGS.  8 B- 8 F  can be performed to provide an alternative configuration of the first exemplary memory opening fill structure  58 . In this case, the tunneling dielectric layer  56  can be formed directly on the vertical stack of annular insulating material portions  57 . The memory film  50  can comprise the blocking dielectric layer  52 , the vertical stack of silicon nitride material portions  54 N, the vertical stack of annular insulating material portions  57  (which can contact the vertical stack of silicon nitride material portions  54 N), and the tunneling dielectric layer  56 . 
       FIGS.  9 A- 9 F  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a fifth exemplary memory opening fill structure containing hybrid charge storage structures including discrete dielectric charge storage portions and floating gates, according to an embodiment of the present disclosure. The fifth exemplary memory opening fill structure can be formed within each memory opening  49  in lieu of the first, second, third, or fourth exemplary memory opening fill structure described above. 
     Referring to  FIG.  9 A , the structure for forming a fifth exemplary memory opening fill structure can be derived from the structure of  FIG.  5 K , the structure of  FIG.  6 E , or the structure of  FIG.  7 I  by partially nitriding the vertical stack of semiconductor material portions  54 S. A vertical stack of composite charge storage structures ( 54 S,  54 N) can be formed by converting surface portions of the vertical stack of discrete tubular semiconductor material portions  54 S into silicon nitride material portions  54 N. Each of the composite charge storage structures ( 54 S,  54 N) comprises a respective semiconductor material portion  54 S which is a remaining portion of a respective one of the discrete tubular semiconductor material portions  54 S and a respective silicon nitride material portion  54 N which is formed by nitridation of a surface portion of the respective one of the discrete tubular semiconductor material portions  54 S. In one embodiment, each silicon nitride material portion  54 N comprises an interfacial region located in proximity to a respective one of the semiconductor material portions  54 S and having a graded silicon-to-nitrogen ratio with decreases from portion  54 N toward portion  54 S. The thickness of each semiconductor material portion  54 S can be in a range from 1 nm to 30 nm, such as from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The thickness of each silicon nitride material portion  54 N can be in a range from 1 nm to 30 nm, such as from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The thickness of each composite charge storage structure ( 54 S,  54 N) can be in a range from 3 nm to 30 nm, such as from 5 nm to 15 nm, although lesser and greater thicknesses can also be employed. 
     Referring to  FIG.  9 B , the processing steps of  FIG.  5 L  can be performed to form the blocking dielectric layer  52  and optionally the first semiconductor channel layer  601 . 
     Referring to  FIG.  9 C , the processing steps of  FIG.  5 M  can be performed to deposit a patterning film  77 , and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , and the blocking dielectric layer  52  located over the pedestal channel portion  11  (or located above the upper substrate semiconductor layer  10  in case a pedestal channel portion is not present) at the bottom of each memory opening  49 . A center portion of the top surface of the pedestal channel portion  11  can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion  11  is not present in the memory opening  49 , a portion of the horizontal surface of the upper substrate semiconductor layer  10  can be vertically recessed underneath the memory opening  49 . The patterning film  77  can be subsequently removed, for example, by ashing. 
     Referring to  FIG.  9 D , the processing steps of  FIG.  5 N  can be performed to form a second semiconductor channel layer  602 . The materials of the first semiconductor channel layer  601  and the second semiconductor channel layer  602  are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer  52 , the tunneling dielectric layer  56 , the first semiconductor channel layer  601 , and the second semiconductor channel layer  602  can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers  32 . 
     Referring to  FIG.  9 E , the processing steps of  FIG.  5 O  can be performed to form a dielectric core  62  in each memory opening  49 . 
     Referring to  FIG.  9 F , the processing steps of  FIG.  5 P  can be performed to form a doped semiconductor portion such as a drain region  63  at an upper portion of each memory opening  49 . Each adjoining pair of a first semiconductor channel layer  601  and a second semiconductor channel layer  602  can collectively form a vertical semiconductor channel  60  through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel  60  is turned on. A tunneling dielectric layer  56  is surrounded by a vertical stack of composite charge storage structures ( 54 S,  54 N), and laterally surrounds a portion of the vertical semiconductor channel  60 . Each adjoining set of a tunneling dielectric layer  56 , a vertical stack of composite charge storage structures ( 54 S,  54 N), and a blocking dielectric layer  52  collectively constitute a memory film  50 , which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. 
     Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . The memory stack structure  55  is a combination of a semiconductor channel  60 , a tunneling dielectric layer  56 , a plurality of memory elements comprising a vertical stack of composite charge storage structures ( 54 S,  54 N), and a blocking dielectric layer  52 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . Each combination of a pedestal channel portion  11  (if present), a memory film  50 , a vertical semiconductor channel  60 , a dielectric core  62 , and a drain region  63  within each support opening  19  fills the respective support openings  19 , and constitutes a support pillar structure. 
       FIGS.  9 G and  9 H  illustrate an alternative configuration of the fourth exemplary memory opening fill structure. Referring to  FIG.  9 G , the alternative configuration of the fourth exemplary memory opening fill structure can be derived from the structure illustrated in  FIG.  9 A  by filling the annular lateral recesses  149  with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses  149  after removal of the vertical stack of metal-semiconductor alloy portions  67 . In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer  52 . For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000. 
     Portions of the dielectric fill material can be removed from outside the annular lateral recesses  149  by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the composite charge storage structures ( 54 S,  54 N) and the material of the blocking dielectric layer  52 . Remaining portions of the dielectric fill material filling the annular lateral recesses  149  comprise a vertical stack of annular insulating material portions  57 . In case an anisotropic etch process is employed to pattern the annular insulating material portions  57 , inner sidewalls of the annular insulating material portions  57  may be vertically coincident with inner sidewalls of the composite charge storage structures ( 54 S,  54 N). 
     Referring to  FIG.  9 H , the processing steps of  FIGS.  9 B- 9 F  can be performed to provide an alternative configuration of the first exemplary memory opening fill structure  58 . In this case, the tunneling dielectric layer  56  can be formed directly on the vertical stack of annular insulating material portions  57 . The memory film  50  can comprise the blocking dielectric layer  52 , the vertical stack of composite charge storage structures ( 54 S,  54 N), the vertical stack of annular insulating material portions  57  (which can contact the vertical stack of composite charge storage structures ( 54 S,  54 N)), and the tunneling dielectric layer  56 . 
       FIGS.  10 A- 10 M  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a sixth exemplary memory opening fill structure containing floating gates with flange portions according to an embodiment of the present disclosure. The sixth exemplary memory opening fill structure can be formed within each memory opening  49  in lieu of the first, second, third, fourth, or fifth exemplary memory opening fill structure described above. 
     Referring to  FIG.  10 A , a structure for forming a sixth exemplary memory opening fill structure is illustrated, which may be the same as the structure of  FIG.  5 D . 
     Referring to  FIG.  10 B , a metal layer  66 L can be conformally deposited on the inner sidewalls of the blocking dielectric layer. The metal layer  66 L can include any metal that can form a metal-semiconductor alloy such as a metal silicide. In one embodiment, the metal layer  66 L can include at least one transition metal that can form a metal silicide. For example, the metal layer  66 L can include tungsten, titanium, cobalt, molybdenum, platinum, nickel, and/or any other transition metal that forms a metal silicide upon reaction with silicon. The metal layer  66 L can be deposited by a conformal deposition method such as a chemical vapor deposition process or an atomic layer deposition process. The thickness of the metal layer  66 L may be greater than one half of the thickness of each insulating layer  32 . In one embodiment, the metal layer fills an entire volume of each cavity in the annular lateral recesses  149 . In one embodiment, the thickness of the metal layer  66 L over sidewalls of the spacer material layers (such as the sacrificial material layers  42 ) can be in a range from 10 nm to 50, such as from 20 nm to 25 nm, although lesser and greater thicknesses can also be employed. 
     Referring to  FIG.  10 C , an optional anisotropic deposition process, such as a physical vapor deposition process (e.g., sputtering), may be optionally performed to deposit additional portions of the metal on horizontal surfaces of the metal layer  66 L. Horizontal portions of the metal layer  66 L can be thickened. The anisotropic metal deposition process increases the thickness of horizontal portions of the metal layer  66 L so that removal of horizontal portions of a semiconductor material layer through formation of metal-semiconductor alloy portions is facilitated at a subsequent processing step. Alternatively, the step of  FIG.  10 C  may be omitted. 
     Referring to  FIG.  10 D , an isotropic etch process such as a wet etch process can be performed to thin the metal layer  66 L (i.e., to partially recess the metal layer  66 L). Alternatively, if the metal layer  66 L comprises cobalt, then the metal layer  66 L may self-segregate during an anneal as described above to form the structure shown in  FIG.  10 D . Remaining portions of the metal layer  66 L include vertical stack of discrete metal portions  66 . 
     The discrete metal portions  66  can be formed within but not completely filling a respective one of the annular lateral recesses  149  of the memory opening  49 . Each discrete metal portion  66  within the vertical stack of discrete metal portions  66  comprises an inner sidewall that is laterally offset outward from portions of an inner sidewall of the blocking dielectric layer  52  located at levels of the spacer material layers (such as the sacrificial material layers  42 ). 
     Thus, the vertical stack of discrete metal portions  66  can be formed in the annular lateral recesses  149 . The vertical stack of discrete metal portions  66  is formed directly on portions of an inner sidewall of the blocking dielectric layer  52  located at levels of the insulating layers  32 . 
     The discrete metal portions  66  may have a respective tubular shape. Each discrete metal portion  66  can have an inner sidewall that is laterally offset outward from sidewalls of the spacer material layers (such as the sacrificial material layers  42 ). In one embodiment, the discrete metal portion  66  can comprise, and/or can consist essentially of, tungsten, titanium, cobalt, molybdenum, platinum, nickel, and/or any other transition metal that forms a metal silicide upon reaction with silicon. In one embodiment, the discrete metal portions  66  can have a thickness in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed. Horizontal remaining portions of the metal layer  66 L may be present over the top surface of the pedestal channel portion  11  and over the top surface of the insulating cap layer  70 . 
     Referring to  FIG.  10 E , a semiconductor material layer  54 L can be conformally deposited on the physically exposed surfaces of the vertical stack of the metal portions  66  and on the physically exposed surfaces of the blocking dielectric layer  52 . The semiconductor material layer  54 L includes a semiconductor material that can form a metal-semiconductor alloy with the material of the metal portions  66 . For example, the semiconductor material layer  54 L can include silicon and/or germanium. In one embodiment, the semiconductor material layer  54 L can include amorphous silicon, polysilicon, germanium, and/or a silicon-germanium alloy. The thickness of the semiconductor material layer  54 L can be selected such that the entirety of the vertical stack of discrete metal portions  66  can react with the semiconductor material of the semiconductor material layer  54 L during a subsequent anneal process. In one embodiment, the semiconductor material layer  54 L can have a thickness in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed. 
     Referring to  FIG.  10 F , a thermal anneal process is performed at an elevated temperature that induces formation of a metal-semiconductor alloy between the material of the metal portions  66  and the material of the semiconductor material layer ML. The elevated temperature may be in a range from 400 degrees Celsius to 1,000 degrees Celsius, although lower and higher temperatures may also be employed depending on the composition of the metal-semiconductor alloy. It is not necessary to form a low-resistance phase metal-semiconductor alloy as required for typical semiconductor applications in this case. Even high-resistance intermediate phase metal-semiconductor alloys formed at a relatively low temperature is sufficient provided that such metal-semiconductor alloys can be subsequently removed selective to unreacted portions of the semiconductor material layer  54 L in a selective etch process. Generally, the thickness of the discrete metal portions  66  and the thickness of the semiconductor material layer  54 L can be selected to ensure that the entire volume of the metal portions  66  react with the semiconductor material layer  54 L to form metal-semiconductor alloy portions  67 . A vertical stack of metal-semiconductor alloy portions  67  can be formed by reacting the vertical stack of metal portions  66  with portions of the semiconductor material layer  54 L located at levels of the insulating layers  32 . Unreacted portions of the semiconductor material layer  54 L remain at each level of the sacrificial material layers  42  located over the top surface of the pedestal channel portion  11 . The set of unreacted portions of the semiconductor material layer  54 L in the memory opening  49  comprise a vertical stack of semiconductor material portions  54 S. 
     In one embodiment, the metal-semiconductor alloy portions  67  can be laterally offset outward from a cylindrical vertical plane including sidewalls of the spacer material layers (such as the sacrificial material layers  42 ) around the memory opening  49 , while parts of the semiconductor material portions  54 S protrude into the recesses  149 . Specifically, each of the semiconductor material portions  54 S comprises a tubular portion  54 T, an upper flange portion  54 U laterally extending outward into the recess  149  from an upper end of an outer sidewall of the tubular portion  54 T, and a lower flange portion  54 F laterally extending outward into the recess  149  from a lower end of the outer sidewall of the tubular portion  54 T. 
     Referring to  FIG.  10 G , a selective isotropic etch process that etches the material of the metal-semiconductor alloy portions  67  selective to the material of the semiconductor material portions  54 S can be performed. The vertical stack of metal-semiconductor alloy portions  67  is removed selective to unreacted portions of the semiconductor material layer  54 L, i.e., the vertical stack of semiconductor material portions  54 S. The vertical stack of semiconductor material portions  54 S remain at levels of the spacer material layers (such as the sacrificial material layers  42 ) and extends partially into the recesses  149 . In one embodiment, each of the semiconductor material portions  54 S comprises a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The upper flange portion  54 U and the lower flange portion  54 F of each semiconductor material portion  54 S are located in the recess  149  and provide increased charge trapping volume in additional to the charge trapping volume provided by the tubular portion  54 T. Thus, the thickness of the spacer material layers (such as the sacrificial material layers  42 ) can be reduced relative to conventional NAND devices in which charge storage elements do not include flange portions. The vertical stack of discrete semiconductor material portions  54 S can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the blocking dielectric layer  52  are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions  67 . The vertical stack of discrete metal portions  66  and portions of the semiconductor material layer  54 L that are adjacent to the vertical stack of discrete metal portions  66  are removed in the form of a vertical stack of metal-semiconductor alloy portions  67 . 
     Referring to  FIG.  10 H , a tunneling dielectric layer  56  can be deposited employing a conformal deposition process such as a chemical vapor deposition process, as described in the previous embodiments. The tunneling dielectric layer  56  can be formed directly on the portions of the inner sidewall of the blocking dielectric layer  52  that are physically exposed and located at the levels of the insulating layers  32 . The tunneling dielectric layer  56  can also be formed directly on the vertical stack of discrete cylindrical semiconductor material portions  54 S. The combination of the blocking dielectric layer  52 , the vertical stack of semiconductor material portions  54 S, and the tunneling dielectric layer  56  constitutes a memory film  50 . 
     Referring to  FIG.  10 I , the processing steps of  FIG.  5 L  can be performed to form the optional first semiconductor channel layer  601  on the tunneling dielectric layer  56 . 
     Referring to  FIG.  10 J , the processing steps of  FIG.  5 M  can optionally be performed to deposit an optional patterning film  77 . An anisotropic etch process can be performed to remove the horizontal bottom portions of the first semiconductor channel layer  601  (if present), the tunneling dielectric layer  56 , and the blocking dielectric layer  52  located over the pedestal channel portion  11  (or located above the upper substrate semiconductor layer  10  in case a pedestal channel portion is not present) at the bottom of each memory opening  49 . A set of the blocking dielectric layer  52 , the vertical stack of semiconductor material portions  54 S, and the tunneling dielectric layer  56  in a memory opening  49  constitutes a memory film  50 . In one embodiment, the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , and the blocking dielectric layer  52  can have vertically coincident sidewalls. The patterning film  77  (if present) can be subsequently removed, for example, by ashing. 
     Referring to  FIG.  10 K , the processing steps of  FIG.  5 N  can be performed to deposit a second semiconductor channel layer  602 . The materials of the first semiconductor channel layer  601  and the second semiconductor channel layer  602  are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer  601  and the second semiconductor channel layer  602 . The combination of flange portions of the semiconductor material portions  54 S, the blocking dielectric layer  52 , the tunneling dielectric layer  56 , the first semiconductor channel layer  601 , and the second semiconductor channel layer  602  can completely fill the volumes of the annular lateral recesses  149  provided at the levels of the insulating layers  32 . 
     Referring to  FIG.  10 L , the processing steps of  FIG.  5 O  can be performed to form a dielectric core  62 . 
     Referring to  FIG.  10 M , the processing steps of  FIG.  5 P  can be performed to form a doped semiconductor material portion such as a drain region  63 . Each adjoining set of a tunneling dielectric layer  56 , a vertical stack of semiconductor material portions  54 S, and a blocking dielectric layer  52  collectively constitute a memory film  50 , which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . The memory stack structure  55  is a combination of a semiconductor channel  60 , a tunneling dielectric layer  56 , a plurality of memory elements comprising a vertical stack of semiconductor material portions  54 S, and a blocking dielectric layer  52 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . Each combination of a pedestal channel portion  11  (if present), a memory film  50 , a vertical semiconductor channel  60 , a dielectric core  62 , and a drain region  63  within each support opening  19  fills the respective support openings  19 , and constitutes a support pillar structure. 
       FIGS.  10 N and  10 O  illustrate an alternative configuration of the first exemplary memory opening fill structure. Referring to  FIG.  10 N , the alternative configuration of the first exemplary memory opening fill structure can be derived from the structure illustrated in  FIG.  10 G  by filling the annular lateral recesses  149  with a dielectric fill material. Specifically, a dielectric fill material such as undoped silicate glass or a doped silicate glass can be deposited in the remaining volumes of the annular lateral recesses  149  after removal of the vertical stack of metal-semiconductor alloy portions  67 . In one embodiment, the dielectric fill material may have a higher etch rate than the material of the blocking dielectric layer  52 . For example, the dielectric fill material may include borosilicate glass, which can provide an etch rate in dilute hydrofluoric acid than the etch rate of undoped silicate glass by a factor in a range from 100 to 10,000. 
     Portions of the dielectric fill material can be removed from outside the annular lateral recesses  149  by etching back the dielectric fill material. An isotropic etch process or an anisotropic etch process may be employed. The chemistry of the etch process employed to etch the dielectric fill material can be selective to the material of the semiconductor material portions  54 S and the material of the blocking dielectric layer  52 . Remaining portions of the dielectric fill material filling the annular lateral recesses  149  comprise a vertical stack of annular insulating material portions  57 . In case an anisotropic etch process is employed to pattern the annular insulating material portions  57 , inner sidewalls of the annular insulating material portions  57  may be vertically coincident with inner sidewalls of the semiconductor material portions  54 S. 
     Referring to  FIG.  10 O , the processing steps of  FIGS.  10 H- 10 M  can be performed to provide an alternative configuration of the second exemplary memory opening fill structure  58 . In this case, the tunneling dielectric layer  56  can be formed directly on the vertical stack of annular insulating material portions  57 . The memory film  50  can comprise the blocking dielectric layer  52 , the vertical stack of semiconductor material portions  54 S, the vertical stack of annular insulating material portions  57  (which can contact the vertical stack of semiconductor material portions  54 S), and the tunneling dielectric layer  56 . 
       FIGS.  11 A- 11 G  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a seventh exemplary memory opening fill structure containing discrete dielectric charge storage elements with flange portions according to an embodiment of the present disclosure. The seventh exemplary memory opening fill structure can be formed within each memory opening  49  in lieu of the first, second, third, fourth, fifth, or sixth exemplary memory opening fill structure described above. 
     Referring to  FIG.  11 A , the structure for forming a seventh exemplary memory opening fill structure can be derived from the structure of  FIG.  10 G  by nitriding the vertical stack of semiconductor material portions  54 S. The vertical stack of semiconductor material portions  54 S is fully converted into a vertical stack of silicon nitride material portions  54 N. Each of the silicon nitride material portions  54 N comprises a tubular portion  54 T, an upper flange portion  54 U laterally extending into the recess  149  outward from an upper end of an outer sidewall of the tubular portion  54 T, and a lower flange portion  54 F laterally extending into the recess  149  outward from a lower end of the outer sidewall of the tubular portion  54 T. In one embodiment, each silicon nitride material portion  54 N has a graded silicon-to-nitrogen ratio, as described with respect to  FIG.  8 A  above. In one embodiment, the thickness of the tubular portion  54 T of each silicon nitride material portion  54 N can be in a range from 3 nm to 30 nm, such as from 5 nm to 15 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the tubular portion  54 T, the upper flange portion  54 U, and the lower flange portion  54 F can have substantially the same thickness. 
     The vertical stack of silicon nitride material portions  54 N is located at levels of the spacer material layers (such as the sacrificial material layers  42 ). In one embodiment, each of the silicon nitride material portions  54 N comprises a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The upper flange portion  54 U and the lower flange portion  54 F of each silicon nitride material portion  54 N provide increased charge trapping volume in additional to the charge trapping volume provided by the tubular portion  54 T. Thus, the thickness of the spacer material layers (such as the sacrificial material layers  42 ) can be reduced relative to conventional NAND devices in which charge storage elements do not include flange portions. The vertical stack of discrete silicon nitride material portions  54 N can be subsequently employed as a vertical stack of charge storage elements, which can function as floating gates of a NAND string. Portions of the inner sidewall of the blocking dielectric layer  52  are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions  67 . 
     Referring to  FIG.  11 B , the processing steps of  FIG.  10 H  can be performed to form a tunneling dielectric layer  56 . 
     Referring to  FIG.  11 C , the processing steps of  FIG.  10 I  can be performed to form a first semiconductor channel layer  601 . 
     Referring to  FIG.  11 D , the processing steps of  FIG.  10 J  can optionally be performed to deposit the optional patterning film  77 , and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer  601  (if present), the tunneling dielectric layer  56 , and the blocking dielectric layer  52  located over the pedestal channel portion  11  (or located above the upper substrate semiconductor layer  10  in case a pedestal channel portion is not present) at the bottom of each memory opening  49 . A center portion of the top surface of the pedestal channel portion  11  can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion  11  is not present in the memory opening  49 , a portion of the horizontal surface of the upper substrate semiconductor layer  10  can be vertically recessed underneath the memory opening  49 . The patterning film  77  (if present) can be subsequently removed, for example, by ashing. 
     Referring to  FIG.  11 E , the processing steps of  FIG.  10 K  can be performed to form a second semiconductor channel layer  602 . The materials of the first semiconductor channel layer  601  and the second semiconductor channel layer  602  are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer  52 , the tunneling dielectric layer  56 , the first semiconductor channel layer  601 , and the second semiconductor channel layer  602  can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers  32 . 
     Referring to  FIG.  11 F , the processing steps of  FIG.  10 L  can be performed to form a dielectric core  62  in each memory opening  49 . 
     Referring to  FIG.  11 G , the processing steps of  FIG.  10 M  can be performed to form a doped semiconductor portion such as a drain region  63  at an upper portion of each memory opening  49 . Each adjoining pair of a first semiconductor channel layer  601  and a second semiconductor channel layer  602  can collectively form a vertical semiconductor channel  60  through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel  60  is turned on. A tunneling dielectric layer  56  is surrounded by a vertical stack of silicon nitride material portions  54 N, and laterally surrounds a portion of the vertical semiconductor channel  60 . Each adjoining set of a tunneling dielectric layer  56 , a vertical stack of silicon nitride material portions  54 N, and a blocking dielectric layer  52  collectively constitute a memory film  50 , which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. 
     Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . The memory stack structure  55  is a combination of a semiconductor channel  60 , a tunneling dielectric layer  56 , a plurality of memory elements comprising a vertical stack of silicon nitride material portions  54 N, and a blocking dielectric layer  52 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . Each combination of a pedestal channel portion  11  (if present), a memory film  50 , a vertical semiconductor channel  60 , a dielectric core  62 , and a drain region  63  within each support opening  19  fills the respective support openings  19 , and constitutes a support pillar structure. 
       FIGS.  11 H and  11 I  illustrate an alternative configuration of the fourth exemplary memory opening fill structure. Referring to  FIG.  11 H , the alternative configuration of the seventh exemplary memory opening fill structure can be derived from the structure illustrated in  FIG.  10 G  by filling the annular lateral recesses  149  with a dielectric fill material. The processing steps of  FIG.  10 N  can be employed to form a vertical stack of annular insulating material portions  57  in unfilled volumes of the annular lateral recesses of each memory opening  49 . 
     Referring to  FIG.  11 I , the processing steps of  FIGS.  10 H- 10 M  can be performed to provide an alternative configuration of the first exemplary memory opening fill structure  58 . In this case, the tunneling dielectric layer  56  can be formed directly on the vertical stack of annular insulating material portions  57 . The memory film  50  can comprise the blocking dielectric layer  52 , the vertical stack of silicon nitride material portions  54 N, the vertical stack of annular insulating material portions  57  (which can contact the vertical stack of silicon nitride material portions  54 N), and the tunneling dielectric layer  56 . 
       FIGS.  12 A- 12 G  are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of an eighth exemplary memory opening fill structure containing hybrid discrete charge storage structures including discrete dielectric charge storage portions and floating gates with flange portions, according to an embodiment of the present disclosure. The eighth exemplary memory opening fill structure can be formed within each memory opening  49  in lieu of the first, second, third, fourth, fifth, sixth, or seventh exemplary memory opening fill structure described above. 
     Referring to  FIG.  12 A , the structure for forming the eight exemplary memory opening fill structure can be derived from the structure of  FIG.  10 G  by partially nitriding the vertical stack of semiconductor material portions  54 S. Surface portions of the semiconductor material portions  54 S that are physically exposed to the memory cavity  49 ′ are converted into silicon nitride material portions  54 N, while underlying portions of the semiconductor material portions  54 S that contact the blocking dielectric layer  52  remain as semiconductor material portions  54 S. Thus, a vertical stack of silicon nitride material portions  54 N is formed by the nitridation process, and the remaining vertical stack of semiconductor material portions  54 S has a lesser volume than the vertical stack of semiconductor material portions  54 S provided at the processing steps of  FIG.  10 G . A vertical stack of composite charge storage structures ( 54 S,  54 N) can be formed by converting surface portions of the vertical stack of discrete semiconductor material portions  54 S into the silicon nitride material portions  54 N. In one embodiment, each silicon nitride material portion  54 N comprises an interfacial region located in proximity to a respective one of the discrete semiconductor material portions  54 S and having a graded silicon-to-nitrogen ratio, as described above. Each of the composite charge storage structures ( 54 S,  54 N) comprises a respective semiconductor material portion  54 S (which is a remaining portion of a respective one of the discrete semiconductor material portions  54 S as provided at the processing steps of  FIG.  10 G ) and a respective silicon nitride material portion  54 N which is formed by nitridation of a surface portion of the respective one of the discrete semiconductor material portions  54 S. 
     Each of the composite charge storage structures ( 54 S,  54 N) comprises a tubular portion  54 T, an upper flange portion  54 U laterally extending outward into the recess  149  from an upper end of an outer sidewall of the tubular portion  54 T, and a lower flange portion  54 F laterally extending outward into the recess  149  from a lower end of the outer sidewall of the tubular portion  54 T. Each semiconductor material portion  54 S includes a respective tubular portion, a respective upper flange portion, and a respective lower flange portion. Each silicon nitride material portion  54 N includes a respective tubular portion, a respective upper flange portion, and a respective lower flange portion. The thickness of the tubular portion of each semiconductor material portion  54 S can be in a range from 1 nm to 30 nm, such as from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The thickness of the tubular portion of each silicon nitride material portion  54 N can be in a range from 1 nm to 30 nm, such as from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The thickness of each tubular portion of composite charge storage structure ( 54 S,  54 N) can be in a range from 3 nm to 30 nm, such as from 5 nm to 15 nm, although lesser and greater thicknesses can also be employed. The thickness of a tubular portion of a composite charge storage structure ( 54 S,  54 N) can be formed between an inner cylindrical sidewall and an outer cylindrical sidewall of the respective composite charge storage structure ( 54 S,  54 N). 
     The vertical stack composite charge storage structures ( 54 S,  54 N) is located at levels of the spacer material layers (such as the sacrificial material layers  42 ) and partially protrudes into the recesses  149 . In one embodiment, each of the composite charge storage structures ( 54 S,  54 N) comprises a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The upper flange portion  54 U and the lower flange portion  54 F of each composite charge storage structure ( 54 S,  54 N) provide increased charge trapping volume in additional to the charge trapping volume provided by the tubular portion  54 T. Thus, the thickness of the spacer material layers (such as the sacrificial material layers  42 ) can be reduced relative to conventional NAND devices in which charge storage elements do not include flange portions. The vertical stack of composite charge storage structures ( 54 S,  54 N) can be subsequently employed as a vertical stack of charge storage elements, which can function as hybrid floating gates and charge trapping dielectric elements of a NAND string. Portions of the inner sidewall of the blocking dielectric layer  52  are physically exposed after removal of the vertical stack of metal-semiconductor alloy portions  67 . 
     Referring to  FIG.  12 B , the processing steps of  FIG.  10 H  can be performed to form a tunneling dielectric layer  56 . 
     Referring to  FIG.  12 C , the processing steps of  FIG.  10 I  can be performed to form the optional first semiconductor channel layer  601 . 
     Referring to  FIG.  12 D , the processing steps of  FIG.  10 J  can optionally be performed to deposit the optional patterning film  77 , and to anisotropically etch horizontal bottom portions of the first semiconductor channel layer  601  (if present), the tunneling dielectric layer  56 , and the blocking dielectric layer  52  located over the pedestal channel portion  11  (or located above the upper substrate semiconductor layer  10  in case a pedestal channel portion is not present) at the bottom of each memory opening  49 . A center portion of the top surface of the pedestal channel portion  11  can be vertically recessed by the anisotropic etch process. In case a pedestal channel portion  11  is not present in the memory opening  49 , a portion of the horizontal surface of the upper substrate semiconductor layer  10  can be vertically recessed underneath the memory opening  49 . The patterning film  77  can be subsequently removed, for example, by ashing. 
     Referring to  FIG.  12 E , the processing steps of  FIG.  10 K  can be performed to form a second semiconductor channel layer  602 . The materials of the first semiconductor channel layer  601  and the second semiconductor channel layer  602  are collectively referred to as a semiconductor channel material. The combination of the blocking dielectric layer  52 , the tunneling dielectric layer  56 , the first semiconductor channel layer  601 , and the second semiconductor channel layer  602  can completely fill the volumes of the annular lateral recesses provided at the levels of the insulating layers  32 . 
     Referring to  FIG.  12 F , the processing steps of  FIG.  10 L  can be performed to form a dielectric core  62  in each memory opening  49 . 
     Referring to  FIG.  12 G , the processing steps of  FIG.  10 M  can be performed to form a doped semiconductor portion such as a drain region  63  at an upper portion of each memory opening  49 . Each adjoining pair of a first semiconductor channel layer  601  and a second semiconductor channel layer  602  can collectively form a vertical semiconductor channel  60  through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel  60  is turned on. A tunneling dielectric layer  56  is surrounded by a vertical stack of composite charge storage structures ( 54 S,  54 N), and laterally surrounds a portion of the vertical semiconductor channel  60 . Each adjoining set of a tunneling dielectric layer  56 , a vertical stack of composite charge storage structures ( 54 S,  54 N), and a blocking dielectric layer  52  collectively constitute a memory film  50 , which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. 
     Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . The memory stack structure  55  is a combination of a semiconductor channel  60 , a tunneling dielectric layer  56 , a plurality of memory elements comprising a vertical stack of composite charge storage structures ( 54 S,  54 N), and a blocking dielectric layer  52 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . Each combination of a pedestal channel portion  11  (if present), a memory film  50 , a vertical semiconductor channel  60 , a dielectric core  62 , and a drain region  63  within each support opening  19  fills the respective support openings  19 , and constitutes a support pillar structure. 
       FIGS.  12 H and  12 I  illustrate an alternative configuration of the fourth exemplary memory opening fill structure. Referring to  FIG.  12 H , the alternative configuration of the fourth exemplary memory opening fill structure can be derived from the structure illustrated in  FIG.  10 G  by filling the annular lateral recesses  149  with a dielectric fill material. The processing steps of  FIG.  10 N  can be employed to form a vertical stack of annular insulating material portions  57  in unfilled volumes of the annular lateral recesses of each memory opening  49 . 
     Referring to  FIG.  12 I , the processing steps of  FIGS.  10 H- 10 M  can be performed to provide an alternative configuration of the first exemplary memory opening fill structure  58 . In this case, the tunneling dielectric layer  56  can be formed directly on the vertical stack of annular insulating material portions  57 . The memory film  50  can comprise the blocking dielectric layer  52 , the vertical stack of composite charge storage structures ( 54 S,  54 N), the vertical stack of annular insulating material portions  57  (which can contact the vertical stack of silicon nitride material portions  54 N), and the tunneling dielectric layer  56 . 
     Referring to  FIG.  13   , the first exemplary structure is illustrated after formation of memory opening fill structures  58  and support pillar structure  20  within the memory openings  49  and the support openings  19 , respectively. An instance of a memory opening fill structure  58  can be formed within each memory opening  49  of the structure of  FIGS.  4 A and  4 B . An instance of the support pillar structure  20  can be formed within each support opening  19  of the structure of  FIGS.  4 A and  4 B . 
     Each memory stack structure  55  includes a vertical semiconductor channel  60 , which may comprise multiple semiconductor channel layers ( 601 ,  602 ), and a memory film  50 . The memory film  50  may comprise a tunneling dielectric layer  56  laterally surrounding the vertical semiconductor channel  60 , a vertical stack of charge storage regions (comprising a charge storage layer  54 ) laterally surrounding the tunneling dielectric layer  56 , and an optional blocking dielectric layer  52 . While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film  50  and/or for the vertical semiconductor channel  60 . 
     Referring to  FIGS.  14 A and  14 B , a contact-level dielectric layer  73  can be formed over the alternating stack ( 32 ,  42 ) of insulating layer  32  and sacrificial material layers  42 , and over the memory stack structures  55  and the support pillar structures  20 . The contact-level dielectric layer  73  includes a dielectric material that is different from the dielectric material of the sacrificial material layers  42 . For example, the contact-level dielectric layer  73  can include silicon oxide. The contact-level dielectric layer  73  can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed. 
     A photoresist layer (not shown) can be applied over the contact-level dielectric layer  73 , and is lithographically patterned to form openings in areas between clusters of memory stack structures  55 . The pattern in the photoresist layer can be transferred through the contact-level dielectric layer  73 , the alternating stack ( 32 ,  42 ) and/or the retro-stepped dielectric material portion  65  employing an anisotropic etch to form backside trenches  79 , which vertically extend from the top surface of the contact-level dielectric layer  73  at least to the top surface of the substrate ( 9 ,  10 ), and laterally extend through the memory array region  100  and the staircase region  300 . 
     In one embodiment, the backside trenches  79  can laterally extend along a first horizontal direction hd 1  and can be laterally spaced apart among one another along a second horizontal direction hd 2  that is perpendicular to the first horizontal direction hd 1 . The memory stack structures  55  can be arranged in rows that extend along the first horizontal direction hd 1 . The drain select level isolation structures  72  can laterally extend along the first horizontal direction hd 1 . Each backside trench  79  can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd 1 ). Each drain select level isolation structure  72  can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd 1  that is invariant with translation along the first horizontal direction hd 1 . Multiple rows of memory stack structures  55  can be located between a neighboring pair of a backside trench  79  and a drain select level isolation structure  72 , or between a neighboring pair of drain select level isolation structures  72 . In one embodiment, the backside trenches  79  can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing. 
     Dopants of the second conductivity type can be implanted into portions of the upper substrate semiconductor layer  10  that underlie the backside trenches  79  to form source regions  61 . The atomic concentration of the dopants of the second conductivity type in the source regions  61  can be in a range from 5.0×10 18 /cm 3  to 2.0×10 21 /cm 3 , although lesser and greater atomic concentrations can also be employed. Surface portions of the upper substrate semiconductor layer  10  that extend between each source region  61  and adjacent memory opening fill structures  58  comprise horizontal semiconductor channels  59 . 
     Referring to  FIG.  15   , an etchant that selectively etches the spacer material of the sacrificial material layers  42  with respect to the insulating material of the insulating layers  32  can be introduced into the backside trenches  79 , for example, employing an etch process. Backside recesses  43  are formed in volumes from which the sacrificial material layers  42  are removed. The removal of the spacer material of the sacrificial material layers  42  can be selective to the insulating material of the insulating layers  32 , the material of the retro-stepped dielectric material portion  65 , the semiconductor material of the upper substrate semiconductor layer  10 , and the material of the outermost layer of the memory films  50 . In one embodiment, the sacrificial material layers  42  can include silicon nitride, and the materials of the insulating layers  32  and the retro-stepped dielectric material portion  65  can be selected from silicon oxide and dielectric metal oxides. 
     The etch process that removes the spacer material selective to the insulating material and the outermost layer of the memory films  50  can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches  79 . For example, if the sacrificial material layers  42  include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structures  20 , the retro-stepped dielectric material portion  65 , and the memory stack structures  55  provide structural support while the backside recesses  43  are present within volumes previously occupied by the sacrificial material layers  42 . 
     Each backside recess  43  can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess  43  can be greater than the height of the backside recess  43 . A plurality of backside recesses  43  can be formed in the volumes from which the spacer material of the sacrificial material layers  42  is removed. The memory openings in which the memory stack structures  55  are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses  43 . In one embodiment, the memory array region  100  comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate ( 9 ,  10 ). In this case, each backside recess  43  can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings. 
     Each of the plurality of backside recesses  43  can extend substantially parallel to the top surface of the substrate ( 9 ,  10 ). A backside recess  43  can be vertically bounded by a top surface of an underlying insulating layer  32  and a bottom surface of an overlying insulating layer  32 . In one embodiment, each backside recess  43  can have a uniform height throughout. 
     Referring to  FIGS.  16 A and  16 B , physically exposed surface portions of the optional pedestal channel portions  11  and the upper substrate semiconductor layer  10  can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each pedestal channel portion  11  into a tubular dielectric spacer  116 , and to convert each physically exposed surface portion of the upper substrate semiconductor layer  10  into a planar dielectric portion (not illustrated). In one embodiment, each tubular dielectric spacer  116  can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying a hole or forming a new hole into the shape of a torus. The tubular dielectric spacers  116  include a dielectric material that includes the same semiconductor element as the pedestal channel portions  11  and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the tubular dielectric spacers  116  is a dielectric material. In one embodiment, the tubular dielectric spacers  116  can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the pedestal channel portions  11 . Dopants in the drain regions  63 , the source regions  61 , and the semiconductor channels  60  can be activated during the anneal process that forms the planar dielectric portions and the tubular dielectric spacers  116 . Alternatively, an additional anneal process may be performed to active the electrical dopants in the drain regions  63 , the source regions  61 , and the semiconductor channels  60 . 
     A backside blocking dielectric layer  44  can be optionally formed. The backside blocking dielectric layer  44 , if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses  43 . In case the blocking dielectric layer  52  is present within each memory opening, the backside blocking dielectric layer  44  is optional. In case the blocking dielectric layer  52  is omitted, the backside blocking dielectric layer  44  is present. 
     The backside blocking dielectric layer  44  can be formed in the backside recesses  43  and on a sidewall of the backside trench  79 . The backside blocking dielectric layer  44  can be formed directly on horizontal surfaces of the insulating layers  32  and sidewalls of the memory stack structures  55  within the backside recesses  43 . If the backside blocking dielectric layer  44  is formed, formation of the tubular dielectric spacers  116  and the planar dielectric portion prior to formation of the backside blocking dielectric layer  44  is optional. In one embodiment, the backside blocking dielectric layer  44  can be formed by a conformal deposition process such as atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD). The backside blocking dielectric layer  44  can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer  44  can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed. 
     The dielectric material of the backside blocking dielectric layer  44  can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer  44  can include a silicon oxide layer. The backside blocking dielectric layer  44  can be deposited by a conformal deposition method such as low pressure chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer  44  is formed on the sidewalls of the backside trenches  79 , horizontal surfaces and sidewalls of the insulating layers  32 , the portions of the sidewall surfaces of the memory stack structures  55  that are physically exposed to the backside recesses  43 , and a top surface of the planar dielectric portion. A backside cavity is present within the portion of each backside trench  79  that is not filled with the backside blocking dielectric layer  44 . 
     At least one metallic material can be deposited in the backside recesses  43 . For example, a combination of a metallic barrier layer and a metallic fill material can be deposited in the backside recesses  43 . The metallic barrier layer includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer can include a conductive metallic nitride material such as TiN, TaN, WN, MoN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer can consist essentially of a conductive metal nitride such as TiN. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, molybdenum, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer can be deposited employing a fluorine-containing precursor gas such as WF 6 . In one embodiment, the metallic fill material layer can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer is spaced from the insulating layers  32  and the memory stack structures  55  by the metallic barrier layer, which can block diffusion of fluorine atoms therethrough. 
     A plurality of electrically conductive layers  46  can be formed in the plurality of backside recesses  43 , and a continuous electrically conductive material layer (not shown) can be formed on the sidewalls of each backside trench  79  and over the contact-level dielectric layer  73 . Each electrically conductive layer  46  includes a portion of the metallic barrier layer  46 A and a portion of the metallic fill material layer  46 B that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers  32 . The continuous electrically conductive material layer includes a continuous portion of the at least one conductive material that is located in the backside trenches  79  or above the contact-level dielectric layer  73 . 
     Each sacrificial material layer  42  can be replaced with an electrically conductive layer  46 . A backside cavity is present in the portion of each backside trench  79  that is not filled with the backside blocking dielectric layer  44  and the continuous electrically conductive material layer. A tubular dielectric spacer  116  laterally surrounds a pedestal channel portion  11 . A bottommost electrically conductive layer  46  laterally surrounds each tubular dielectric spacer  116  upon formation of the electrically conductive layers  46 . 
     The deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each backside trench  79  and from above the contact-level dielectric layer  73 , for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses  43  constitutes an electrically conductive layer  46 . Each electrically conductive layer  46  can be a conductive line structure. Thus, the sacrificial material layers  42  are replaced with the electrically conductive layers  46 . 
     Each electrically conductive layer  46  can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer  46  are the control gate electrodes for the vertical memory devices including the memory stack structures  55 . In other words, each electrically conductive layer  46  can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices. 
     In one embodiment, the removal of the continuous electrically conductive material layer can be selective to the material of the backside blocking dielectric layer  44 . In this case, a horizontal portion of the backside blocking dielectric layer  44  can be present at the bottom of each backside trench  79 . In another embodiment, the removal of the continuous electrically conductive material layer may not be selective to the material of the backside blocking dielectric layer  44  or, the backside blocking dielectric layer  44  may not be employed. The planar dielectric portions can be removed during removal of the continuous electrically conductive material layer. A backside cavity is present within each backside trench  79 . 
     Referring to  FIG.  17   , an insulating material layer can be formed in the backside trenches  79  and over the contact-level dielectric layer  73  by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed. 
     If a backside blocking dielectric layer  44  is present, the insulating material layer can be formed directly on surfaces of the backside blocking dielectric layer  44  and directly on the sidewalls of the electrically conductive layers  46 . If a backside blocking dielectric layer  44  is not employed, the insulating material layer can be formed directly on sidewalls of the insulating layers  32  and directly on sidewalls of the electrically conductive layers  46 . 
     An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer  73  and at the bottom of each backside trench  79 . Each remaining portion of the insulating material layer constitutes an insulating spacer  74 . A backside cavity is present within a volume surrounded by each insulating spacer  74 . A top surface of the upper substrate semiconductor layer  10  can be physically exposed at the bottom of each backside trench  79 . 
     An upper portion of the upper substrate semiconductor layer  10  that extends between the source region  61  and the plurality of pedestal channel portions  11  constitutes a horizontal semiconductor channel  59  for a plurality of field effect transistors. The horizontal semiconductor channel  59  is connected to multiple vertical semiconductor channels  60  through respective pedestal channel portions  11 . The horizontal semiconductor channel  59  contacts the source region  61  and the plurality of pedestal channel portions  11 . A bottommost electrically conductive layer  46  provided upon formation of the electrically conductive layers  46  within the alternating stack ( 32 ,  46 ) can comprise a select gate electrode for the field effect transistors. Each source region  61  is formed in an upper portion of the substrate ( 9 ,  10 ). Semiconductor channels ( 59 ,  11 ,  60 ) extend between each source region  61  and a respective set of drain regions  63 . The semiconductor channels ( 59 ,  11 ,  60 ) include the vertical semiconductor channels  60  of the memory stack structures  55 . 
     A backside contact via structure  76  can be formed within each backside cavity. Each contact via structure  76  can fill a respective backside cavity. The contact via structures  76  can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside trench  79 . For example, the at least one conductive material can include a conductive liner  76 A and a conductive fill material portion  76 B. The conductive liner  76 A can include a conductive metallic liner such as TiN, TaN, WN, WC, TiC, TaC, MoN, an alloy thereof, or a stack thereof. The thickness of the conductive liner  76 A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion  76 B can include a metal or a metallic alloy. For example, the conductive fill material portion  76 B can include W, Mo, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof. 
     In an alternative embodiment, the contact via structure  76  may be omitted and a horizontal source line may contact a side of a bottom portion of the vertical semiconductor channel  60 . 
     The at least one conductive material can be planarized employing the contact-level dielectric layer  73  overlying the alternating stack ( 32 ,  46 ) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer  73  can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches  79  constitutes a backside contact via structure  76 . 
     The backside contact via structure  76  extends through the alternating stack ( 32 ,  46 ), and contacts a top surface of the source region  61 . If a backside blocking dielectric layer  44  is employed, the backside contact via structure  76  can contact a sidewall of the backside blocking dielectric layer  44 . 
     Referring to  FIGS.  18 A and  18 B , additional contact via structures ( 88 ,  86 ,  8 P) can be formed through the contact-level dielectric layer  73 , and optionally through the retro-stepped dielectric material portion  65 . For example, drain contact via structures  88  can be formed through the contact-level dielectric layer  73  on each drain region  63 . Word line contact via structures  86  can be formed on the electrically conductive layers  46  through the contact-level dielectric layer  73 , and through the retro-stepped dielectric material portion  65 . Peripheral device contact via structures  8 P can be formed through the retro-stepped dielectric material portion  65  directly on respective nodes of the peripheral devices. 
     The first exemplary structures can include a three-dimensional memory device. In one embodiment, the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device. The electrically conductive layers  46  can comprise, or can be electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device. The substrate ( 9 ,  10 ) can comprise a silicon substrate. The vertical NAND memory device can comprise an array of monolithic three-dimensional NAND strings over the silicon substrate. The silicon substrate can contain an integrated circuit comprising a driver circuit (comprising a subset of the least one semiconductor device  700 ) for the memory device located thereon. Alternatively, the driver circuit may be formed on a separate substrate and then bonded to the memory device. The electrically conductive layers  46  can comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate ( 9 ,  10 ), e.g., between a pair of backside trenches  79 . The plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. The array of monolithic three-dimensional NAND strings can comprise: a plurality of semiconductor channels ( 59 ,  11 ,  60 ), wherein at least one end portion  60  of each of the plurality of semiconductor channels ( 59 ,  11 ,  60 ) extends substantially perpendicular to a top surface of the substrate ( 9 ,  10 ) and comprising a respective one of the vertical semiconductor channels  60 , and a plurality of charge storage elements. Each charge storage element can be located adjacent to a respective one of the plurality of semiconductor channels ( 59 ,  11 ,  60 ). 
       FIG.  19 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a first exemplary memory opening fill structure or a second exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a semiconductor material portion  54 S, which may have a tubular configuration. The tunneling dielectric layer  56  is in direct contact with the blocking dielectric layer  52  at levels of the insulating layers  32 . 
       FIG.  19 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the first exemplary memory opening fill structure or the second exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a semiconductor material portion  54 S, which may have a tubular configuration. The tunneling dielectric layer  56  is in direct contact with inner sidewalls of the annular insulating material portions  57  at levels of the insulating layers  32 . 
       FIG.  20 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a third exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a combination of a semiconductor material portion  54 S (which may have a tubular configuration) and a portion of a silicon nitride layer  53  located at the level of the semiconductor material portion  54 S. The tunneling dielectric layer  56  is in direct contact with the blocking dielectric layer  52  at levels of the insulating layers  32 . 
       FIG.  20 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the third exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a combination of a semiconductor material portion  54 S (which may have a tubular configuration) and a portion of a silicon nitride layer  53  located at the level of the semiconductor material portion  54 S. The tunneling dielectric layer  56  is in direct contact with inner sidewalls of the annular insulating material portions  57  at levels of the insulating layers  32 . 
       FIG.  21 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a fourth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete silicon nitride material portion  54 N, which may have a tubular configuration. The tunneling dielectric layer  56  is in direct contact with the blocking dielectric layer  52  at levels of the insulating layers  32 . 
       FIG.  21 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the fourth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a silicon nitride material portion  54 N, which may have a tubular configuration. The tunneling dielectric layer  56  is in direct contact with inner sidewalls of the annular insulating material portions  57  at levels of the insulating layers  32 . 
       FIG.  22 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a fifth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete, composite charge storage structure ( 54 S,  54 N), which may have a tubular configuration. Each composite charge storage structure ( 54 S,  54 N) can include a stack of a semiconductor material portion  54 S and a silicon nitride material portion  54 N. The tunneling dielectric layer  56  is in direct contact with the blocking dielectric layer  52  at levels of the insulating layers  32 . 
       FIG.  22 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the fifth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a composite charge storage structure ( 54 S,  54 N), which may have a tubular configuration. Each composite charge storage structure ( 54 S,  54 N) can include a stack of a semiconductor material portion  54 S and a silicon nitride material portion  54 N. The tunneling dielectric layer  56  is in direct contact with inner sidewalls of the annular insulating material portions  57  at levels of the insulating layers  32 . 
       FIG.  23 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a sixth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete semiconductor material portion  54 S, which may have a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The tunneling dielectric layer  56  is in direct contact with the blocking dielectric layer  52  at levels of the insulating layers  32 . 
       FIG.  23 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the sixth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a semiconductor material portion  54 S, which may have a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The tunneling dielectric layer  56  is in direct contact with inner sidewalls of the annular insulating material portions  57  at levels of the insulating layers  32 . 
       FIG.  24 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a seventh exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete silicon nitride material portion  54 N, which may have a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The tunneling dielectric layer  56  is in direct contact with the blocking dielectric layer  52  at levels of the insulating layers  32 . 
       FIG.  24 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the seventh exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a silicon nitride material portion  54 N, which may have a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The tunneling dielectric layer  56  is in direct contact with inner sidewalls of the annular insulating material portions  57  at levels of the insulating layers  32 . 
       FIG.  25 A  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case a eighth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a discrete composite charge storage structure ( 54 S,  54 N), which includes a stack of a semiconductor material portion  54 S and a silicon nitride material portion  54 N. Each composite charge storage structure ( 54 S,  54 N) may have a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The tunneling dielectric layer  56  is in direct contact with the blocking dielectric layer  52  at levels of the insulating layers  32 . 
       FIG.  25 B  is a magnified view of a memory opening in the first exemplary structure of  FIGS.  18 A and  18 B  in case an alternative configuration of the eighth exemplary memory opening fill structure is present in the memory opening according to an embodiment of the present disclosure. In this case, each charge storage element may comprise a composite charge storage structure ( 54 S,  54 N), which includes a stack of a semiconductor material portion  54 S and a silicon nitride material portion  54 N. Each composite charge storage structure ( 54 S,  54 N) may have a tubular portion  54 T, an upper flange portion  54 U, and a lower flange portion  54 F. The tunneling dielectric layer  56  is in direct contact with inner sidewalls of the annular insulating material portions  57  at levels of the insulating layers  32 . 
     Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers  32  and electrically conductive layers  46  located over a substrate ( 9 ,  10 ); a memory opening  49  vertically extending through the alternating stack ( 32 ,  46 ), wherein the memory opening  49  has laterally-protruding portions (such as the annular lateral recesses  149 ) that extend outward at each level of the insulating layers  32 ; and a memory opening fill structure  58  located in the memory opening  49  and comprising, from outside to inside, a blocking dielectric layer  52 , charge storage structures {( 54 S,  54 N) or ( 54 S,  52 )} comprising a vertical stack of discrete semiconductor material portions  54 S and at least one silicon nitride material portion ( 54 N or  53 ) in contact with the vertical stack  54 S, a tunneling dielectric layer  56  in contact with the charge storage structures {( 54 S,  54 N) or ( 54 S,  52 )}, and a vertical semiconductor channel  60 . 
     In one embodiment, the at least one silicon nitride material portion  54 N comprises a vertical stack of discrete silicon nitride material portions  54 N in contact with a respective discrete semiconductor material portion  54 S within the vertical stack of discrete semiconductor material portions  54 S. 
     In one embodiment, each discrete silicon nitride material portion  54 N within the vertical stack of discrete silicon nitride material portions  54 N is in contact with the tunneling dielectric layer  56 ; and each discrete semiconductor material portion  54 S within the vertical stack of discrete semiconductor material portions  54 S is not in contact with the tunneling dielectric layer  56 , and is spaced from the tunneling dielectric layer  56  by the vertical stack of discrete silicon nitride material portions  54 N. 
     In one embodiment, each silicon nitride material portion  54 N comprises a tubular portion  54 T having a uniform thickness between an inner sidewall and an outer sidewall, an upper flange portion  54 U extending outward from an upper periphery of the inner sidewall of the tubular portion  54 T, and a lower flange portion  54 F extending outward from a lower periphery of the inner sidewall of the tubular portion  54 T. 
     In one embodiment, each silicon nitride material portion  54 N comprises an interfacial region located in proximity to a respective one of the discrete semiconductor material portions  54 S and having a graded silicon-to-nitrogen ratio. 
     In one embodiment, the at least one silicon nitride material portion comprises a silicon nitride layer  53  vertically extending through layers of the alternating stack ( 32 ,  46 ) and contacting an outer sidewall of each discrete semiconductor material portion  54 S within the vertical stack of discrete semiconductor material portions  54 S. In one embodiment, the silicon nitride layer  53  is in contact with an inner sidewall of the blocking dielectric layer  52  and an outer sidewall of the tunneling dielectric layer  56 . In one embodiment, all surfaces of the vertical stack of discrete semiconductor material portions  54 S are in contact with a surface of the silicon nitride liner  53  or a surface of the tunneling dielectric layer  56 . 
     In one embodiment, the tunneling dielectric layer  56  has a laterally-undulating vertical cross-sectional profile, and comprises laterally-protruding portions located at levels of the insulating layers  32  and contacting horizontal annular surfaces of the blocking dielectric layer  52  and overlying or underlying portions of the electrically conductive layers  46  that are proximal to the vertical stack of discrete semiconductor material portions  54 S. 
     In one embodiment, the memory opening fill structure  58  comprises a vertical stack of annular insulating material portions  57  located at each level of the insulating layers  32  between the blocking dielectric layer  52  and the tunneling dielectric layer  56 ; and the tunneling dielectric layer  56  comprises a straight outer sidewall contacting each annular insulating material portion  57  within the vertical stack of annular insulating material portions  57  and contacting the vertical stack of discrete semiconductor material portions  54 S. 
     According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers  32  and electrically conductive layers  46  located over a substrate ( 9 ,  10 ); a memory opening  49  vertically extending through the alternating stack ( 32 ,  46 ), wherein the memory opening  49  has laterally-protruding portions (such as the annular lateral recesses  149 ) that extend outward at levels of the insulating layers  32 ; and a memory opening fill structure  58  located in the memory opening  49  and comprising, from outside to inside, a blocking dielectric layer  52 , a vertical stack of discrete charge storage material portions { 54 S,  54 N, ( 54 S,  54 N)}, a tunneling dielectric layer  56 , and a vertical semiconductor channel  60 , wherein each charge storage material portion { 54 S,  54 N, ( 54 S,  54 N)} comprises a tubular portion  54 T located at a level of a respective one of the electrically material layers  46 , an upper flange portion  54 U laterally extending outward from an upper end of an outer sidewall of the tubular portion  54 T, and a lower flange portion  54 F laterally extending outward from a lower end of the outer sidewall of the tubular portion  54 T. 
     In one embodiment, each charge storage material portion comprises a respective semiconductor material portion  54 S. In one embodiment, each charge storage material portion comprises a respective silicon nitride material portion  54 N. In one embodiment, each charge storage material portion comprises a respective stack of a semiconductor material portion  54 S and a silicon nitride material portion  54 N. In one embodiment, the semiconductor material portion  54 S of each charge storage material portion ( 54 S,  54 N) does not contact the tunneling dielectric layer  56 , and is spaced from the tunneling dielectric layer  56  by a respective one of the silicon nitride material portions  54 N. 
     In one embodiment, the upper flange portion  54 U contacts a horizontal top surface of the blocking dielectric layer  52 ; and the lower flange portion  54 F comprises a horizontal bottom surface of the blocking dielectric layer  52 . 
     In one embodiment, the blocking dielectric layer  52  have a laterally-undulating vertical cross-sectional profile; first tubular portions of the blocking dielectric layer  52  located at levels of the insulating layers  32  are laterally offset outward from second tubular portions of the blocking dielectric layer  52  located at levels of the electrically conductive layers  46 ; and the first tubular portions of the blocking dielectric layer  52  are not in contact with (i.e., not in direct contact with) the vertical stack of charge storage material portions  54 . 
     In one embodiment, the vertical semiconductor channel  60  comprises: a tubular portion that vertically extends through a plurality of electrically conductive material layers  46  within the alternating stack ( 32 ,  46 ); and laterally-protruding portions that protrude outward from the tubular portion at the levels of the insulating layers  32  (as illustrated, for example, in  FIGS.  19 A,  20 A,  21 A,  22 A,  23 A,  24 A, and  25 A ). 
     In one embodiment, the memory opening fill structure  58  comprises a vertical stack of annular insulating material portions  57  located at the levels of the insulating layers  32  between the blocking dielectric layer  52  and the tunneling dielectric layer  56 ; and the tunneling dielectric layer  56  comprises a straight outer sidewall contacting each annular insulating material portion  57  within the vertical stack of annular insulating material portions  57  and contacting the vertical stack of charge storage material portions { 54 S,  54 N, ( 54 S,  54 N)} (as illustrated in  FIGS.  19 B,  20 B,  21 B,  22 B,  23 B,  24 B, and  25 B ). 
     In one embodiment, the memory opening fill structure  58  comprises a doped semiconductor material portion (such as a drain region  63 ) that overlies the vertical semiconductor channel  60  and forms a p-n junction at an interface with the vertical semiconductor channel  60 . 
     The various embodiments of the present disclosure can be employed to provide a vertical stack of discrete charge storage elements providing reduced charge leakage across vertical levels and/or increased charge storage capacity through use of flange portions for each charge storage element. The various embodiments of the present disclosure can facilitate device scaling along the vertical direction in a three-dimensional NAND memory device or other vertical memory devices. 
     Referring to  FIG.  26   , a second exemplary structure according to a second embodiment of the present disclosure can be derived from the first exemplary structure of  FIG.  1    by forming an alternating stack of disposable material layers  31  and silicon nitride layers  41 . The disposable material layers  31  include a material that can be removed selective to the silicon nitride layers  41  and the upper substrate semiconductor layer  10 . For example, the disposable material layer  31  may include undoped silicate glass (i.e., silicon oxide) doped silicate glass (such as borosilicate glass), organosilicate glass, amorous carbon, or a silicon-germanium alloy including germanium at an atomic concentration greater than 15% (such as from 15% to 99%). In one embodiment, the disposable material layers  31  can include doped or undoped silicon oxide. The silicon nitride layers  41  can consist essentially of silicon nitride. 
     The disposable material layers  31  can be deposited by chemical vapor deposition, and can have a thickness in a range from 1.5 nm to 10 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses may also be employed. The silicon nitride layers  41  can be deposited by chemical vapor deposition, and can have a thickness in a range from 6 nm to 40 nm, although lesser and greater thicknesses may also be employed. The sum of the thickness of a disposable material layer  31  and a silicon nitride layer  41  can be less than the sum of the thickness of an insulating layer  32  and a sacrificial material layer  42  in the first exemplary structure. Further, the silicon nitride layers  41  may be thicker than the disposable material layers  31 . In one embodiment, a ratio of the thickness of a silicon nitride layer  41  to the thickness of a disposable material layer  31  can be in a range from 1.5 to 10, such as from 2 to 5, although lesser and greater ratios may also be employed. Generally, a lesser thickness for the disposable material layers  31  is preferable as long as the material of the disposable material layers  31  can be subsequently removed by a lateral isotropic etch process selective to the silicon nitride layers  41 . An insulating cap layer  70  can be deposited in the same manner as in the processing steps of  FIG.  2   . 
     Referring to  FIG.  27   , the processing steps of  FIG.  3    can be performed to form stepped surfaces with any needed changes in view of the changes in the material compositions and thicknesses of the alternating stack of the disposable material layers  31  and the silicon nitride layers  41  relative to the alternating stack of the insulating layers  32  and the sacrificial material layers  42  in the first exemplary structure. A dielectric material can be deposited and planarized over the stepped surfaces to form a retro-stepped dielectric material portion  64 . The retro-stepped dielectric material portion  64  can include a dielectric material that provides a higher etch resistance to an etchant to be subsequently employed to remove the disposable material layers  31 . For example, if the disposable material layers  31  include a doped silicate glass or organosilicate glass, the retro-stepped dielectric material portion  64  can include silicon oxycarbide (e.g., carbon-doped silicate glass), which provides a significantly higher etch resistance to hydrofluoric acid than silicon oxide disposable material layers  31 . 
     Referring to  FIGS.  28 A and  28 B , the processing steps of  FIGS.  4 A and  4 B  can be performed with any needed changes to form memory openings  49  and support openings  19  in view of the changes in the material compositions and thicknesses of the alternating stack of the disposable material layers  31  and the silicon nitride layers  41  relative to the alternating stack of the insulating layers  32  and the sacrificial material layers  42  in the first exemplary structure. 
     Referring to  FIG.  28 C , support pillar structures  20  are formed in the support openings  19 . Each support pillar structure  20  comprises a dielectric (i.e., insulating) material at least in its outer surface. In other embodiment, the entire support pillar structure  20  may be formed from a dielectric material. For example, each support pillar structure  20  may comprise a silicon nitride liner  22  deposited into the support opening  19  surrounding a silicon oxide core  24  deposited over the silicon nitride liner  22 . The silicon nitride liner  22  and the silicon oxide core  24  may be planarized by chemical mechanical planarization (i.e., polishing) such that their top surface is even with the top surface of the insulating cap layer  70 . The memory opening  49  may be covered with a sacrificial mask (e.g., photoresist) or filled with a sacrificial fill material (e.g., amorphous silicon) during the deposition of the silicon nitride liner  22  and the silicon oxide core  24 , and which may be removed after deposition of the silicon nitride liner  22  and the silicon oxide core  24 . Alternatively, the silicon nitride liner  22  and the silicon oxide core  24  may be deposited into the memory openings  49  and the support openings  19  followed by masking the support openings  19  and removing the silicon nitride liner  22  and the silicon oxide core  24  located in the memory openings  49  by etching. 
       FIGS.  29 A- 29 H  are sequential schematic vertical cross-sectional views of a memory opening  49  within the second exemplary structure during formation of a memory stack structure  55 , an optional dielectric core  62 , and a drain region  63  therein according to an embodiment of the present disclosure. 
       FIG.  29 A  illustrates a memory opening  49  at the processing steps of  FIG.  28 C . 
     Referring to  FIG.  29 B , the processing steps of  FIG.  5 B  can be performed to form a pedestal channel portion  11  in each memory opening  49 . Alternatively, the pedestal channel portion  11  may be omitted if a lateral source contact structure (e.g., direct strap contact) will be formed in contact with a side of the vertical semiconductor channel  60  in a subsequent step as will be described below with respect to the third embodiment. 
     Referring to  FIG.  29 C , a stack of layers including a semiconductor liner  151 L, a charge storage material layer  154 L, a tunneling dielectric layer  56 , and an optional first semiconductor channel layer  601  can be sequentially deposited in the memory openings  49 . 
     The semiconductor liner  151 L can include a semiconductor material such as amorphous silicon, polysilicon, or a silicon-germanium alloy. The semiconductor liner  151 L includes a different material than the material of the disposable material layers  31 . In case the disposable material layers  31  include a silicon-germanium alloy, the semiconductor liner  151 L can include amorphous silicon or polysilicon so that the semiconductor liner  151 L functions as an etch stop structure. In case the disposable material layers  31  include undoped silicate glass, a doped silicate glass, or organosilicate glass, the semiconductor liner  151 L can include amorphous silicon, polysilicon, or a silicon-germanium alloy. The semiconductor liner  151 L may have a thickness in a range from 1 nm to 6 nm, such as from 2 nm to 4 nm, although lesser and greater thicknesses may also be employed. 
     Subsequently, the charge storage material layer  154 L can be formed. In one embodiment, the charge storage material layer  154 L can be a continuous layer that is deposited by a conformal deposition process. In one embodiment, the charge storage material layer  154 L can include a silicon nitride layer having a uniform thickness throughout. The thickness of the charge storage material layer  154 L can be in a range from 3 nm to 8 nm, although lesser and greater thicknesses may also be employed. 
     The tunneling dielectric layer  56  includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer  56  can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer  56  can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer  56  can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer  56  can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. 
     The optional first semiconductor channel layer  601  includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer  601  includes amorphous silicon or polysilicon. The first semiconductor channel layer  601  can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer  601  can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity  49 ′ is formed in the volume of each memory opening  49  that is not filled with the deposited material layers ( 52 ,  54 ,  56 ,  601 ). In an alternative embodiment, a sacrificial cover material layer may be employed in lieu of the first semiconductor channel layer  601 . In this case, the sacrificial cover material layer can include any cover material that can protect the charge storage material layer  154 L during a subsequent anisotropic etch process. 
     Referring to  FIG.  29 D , the optional first semiconductor channel layer  601 , the tunneling dielectric layer  56 , the charge storage material layer  154 L, the semiconductor liner  151 L are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , the charge storage material layer  154 L, and the semiconductor liner  151 L located above the top surface of the insulating cap layer  70  can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , the charge storage material layer  154 L, and the semiconductor liner  151 L at a bottom of each memory cavity  49 ′ can be removed to form openings in remaining portions thereof. Each of the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , the charge storage material layer  154 L, and the semiconductor liner  151 L can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may, or may not, be the same for the various material layers. 
     Each remaining portion of the first semiconductor channel layer  601  can have a tubular configuration. In one embodiment, the charge storage material layer  154 L can be a charge storage layer in which each portion adjacent to the silicon nitride layers  41  constitutes a charge storage region. 
     A surface of the pedestal channel portion  11  (or a surface of the upper substrate semiconductor layer  10  in case the pedestal channel portions  11  are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , the charge storage material layer  154 L, and the semiconductor liner  151 L. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity  49 ′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity  49 ′ is vertically offset from the topmost surface of the pedestal channel portion  11  (or of the upper substrate semiconductor layer  10  in case pedestal channel portions  11  are not employed) by a recess distance. A tunneling dielectric layer  56  is located over the charge storage material layer  154 L. A set of a semiconductor liner  151 L, a charge storage material layer  154 L, and a tunneling dielectric layer  56  in a memory opening  49  constitutes a memory film  50 , which includes a plurality of charge storage regions (as embodied as the charge storage material layer  154 L) that are insulated from surrounding materials by the semiconductor liner  151 L and the tunneling dielectric layer  56 . In one embodiment, the first semiconductor channel layer  601 , the tunneling dielectric layer  56 , the charge storage material layer  154 L, and the semiconductor liner  151 L can have vertically coincident sidewalls. In case a sacrificial cover material layer is employed in lieu of the first semiconductor channel layer  601 , the sacrificial cover material layer can be removed selective to the charge storage material layer  154 L. 
     Referring to  FIG.  29 E , a second semiconductor channel layer  602  can be deposited directly on the semiconductor surface of the pedestal channel portion  11  or the upper substrate semiconductor layer  10  if the pedestal channel portion  11  is omitted, and directly on the first semiconductor channel layer  601 . The second semiconductor channel layer  602  includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer  602  includes amorphous silicon or polysilicon. The second semiconductor channel layer  602  can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer  602  can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second semiconductor channel layer  602  may partially fill the memory cavity  49 ′ in each memory opening, or may fully fill the cavity in each memory opening. 
     The materials of the first semiconductor channel layer  601  and the second semiconductor channel layer  602  are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer  601  and the second semiconductor channel layer  602 . 
     Referring to  FIG.  29 F , in case the memory cavity  49 ′ in each memory opening is not completely filled by the second semiconductor channel layer  602 , a dielectric core layer  62 L can be deposited in the memory cavity  49 ′ to fill any remaining portion of the memory cavity  49 ′ within each memory opening. The dielectric core layer  62 L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer  62 L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating. 
     Referring to  FIG.  29 G , the horizontal portion of the dielectric core layer  62 L can be removed, for example, by a recess etch from above the top surface of the insulating cap layer  70 . The dielectric core layer  62 L can be vertically recessed until top surfaces of remaining portions of the dielectric core layer  62 L are recessed below the horizontal plane including the top surface of the insulating cap layer  70 . Each remaining portion of the dielectric core layer  62 L constitutes a dielectric core  62 . 
     Referring to  FIG.  29 H , a doped semiconductor material having a doping of a second conductivity type can be deposited to form a recess region overlying the dielectric core  62 . The second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the doped semiconductor material can be in a range from 5.0×10 18 /cm 3  to 2.0×10 21 /cm 3 , although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. 
     Excess portions of the deposited semiconductor material and horizontal portions of the second semiconductor channel layer  602  can be removed from above the top surface of the insulating cap layer  70 , for example, by chemical mechanical planarization (CMP). Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region  63 . Each remaining portion of the second semiconductor channel layer  602  can be located entirety within a memory opening  49 . Each adjoining pair of a first semiconductor channel layer  601  (if present) and a second semiconductor channel layer  602  can collectively form a vertical semiconductor channel  60  through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel  60  is turned on. A tunneling dielectric layer  56  is surrounded by a charge storage material layer  154 L, and laterally surrounds a portion of the vertical semiconductor channel  60 . The semiconductor liner  151 L laterally surrounds and contacts the charge storage material layer  154 L. Each adjoining set of a semiconductor liner  151 L, a charge storage material layer  154 L, and a tunneling dielectric layer  56  collectively constitute a memory film  50 . 
     Each combination of a memory film  50  and a vertical semiconductor channel  60  within a memory opening  49  constitutes a memory stack structure  55 . Each combination of a pedestal channel portion  11  (if present), a memory stack structure  55 , a dielectric core  62 , and a drain region  63  within a memory opening  49  is herein referred to as a memory opening fill structure  58 . 
     Referring to  FIG.  30   , the second exemplary structure is illustrated after formation of memory opening fill structures  58  and support pillar structure  20  within the memory openings  49  and the support openings  19 , respectively. An instance of a memory opening fill structure  58  can be formed within each memory opening  49 . An instance of the support pillar structure  20  can be formed within each support opening  19 . 
     Each memory stack structure  55  includes a vertical semiconductor channel  60 , which may comprise multiple semiconductor channel layers ( 601 ,  602 ) or a single semiconductor channel layer  602 , and a memory film  50 . The memory film  50  may comprise a tunneling dielectric layer  56  laterally surrounding the vertical semiconductor channel  60  and a vertical stack of charge storage regions laterally surrounding the tunneling dielectric layer  56  (as embodied as charge storage material layer  154 L) and an optional semiconductor liner  151 L. While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film  50  and/or for the vertical semiconductor channel  60 . 
     Referring to  FIGS.  31 A and  31 B , a contact-level dielectric layer  73  can be formed over the alternating stack ( 31 ,  41 ) of disposable material layer  31  and silicon nitride layers  41 , and over the memory stack structures  55  and the support pillar structures  20 . The contact-level dielectric layer  73  includes a dielectric material that is different from the dielectric material of the silicon nitride layers  41 . For example, the contact-level dielectric layer  73  can include carbon-doped silicon oxide (i.e., silicon oxycarbide). The contact-level dielectric layer  73  can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed. 
     A photoresist layer (not shown) can be applied over the contact-level dielectric layer  73 , and is lithographically patterned to form openings in areas between clusters of memory stack structures  55 . The pattern in the photoresist layer can be transferred through the contact-level dielectric layer  73 , the alternating stack ( 31 ,  41 ) and/or the retro-stepped dielectric material portion  65  employing an anisotropic etch to form backside trenches  79 , which vertically extend from the top surface of the contact-level dielectric layer  73  at least to the top surface of the substrate ( 9 ,  10 ), and laterally extend through the memory array region  100  and the contact region  300 . 
     In one embodiment, the backside trenches  79  can laterally extend along a first horizontal direction hd 1  (e.g., word line direction) and can be laterally spaced apart from each other along a second horizontal direction hd 2  (e.g., bit line direction) that is perpendicular to the first horizontal direction hd 1 . The memory stack structures  55  can be arranged in rows that extend along the first horizontal direction hd 1 . The drain select level isolation structures  72  can laterally extend along the first horizontal direction hd 1 . Each backside trench  79  can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd 1 ). Each drain select level isolation structure  72  can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd 1  that is invariant with translation along the first horizontal direction hd 1 . Multiple rows of memory stack structures  55  can be located between a neighboring pair of a backside trench  79  and a drain select level isolation structure  72 , or between a neighboring pair of drain select level isolation structures  72 . In one embodiment, the backside trenches  79  can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing. 
     An optional source region  61  can be formed at a surface portion of the upper substrate semiconductor layer  10  under each backside trench  79  by implantation of electrical dopants into physically exposed surface portions of the upper substrate semiconductor layer  10 . Each source region  61  is formed in a surface portion of the substrate ( 9 ,  10 ) that underlies a respective backside trench  79 . An upper portion of the upper substrate semiconductor layer  10  that extends between the source region  61  and the plurality of pedestal channel portions  11  constitutes a horizontal semiconductor channel  59  for a plurality of field effect transistors. The horizontal semiconductor channel  59  is connected to multiple vertical semiconductor channels  60  through respective pedestal channel portions  11 . The horizontal semiconductor channel  59  contacts the source region  61  and the plurality of pedestal channel portions  11 . Semiconductor channels ( 59 ,  11 ,  60 ) extend between each source region  61  and a respective set of drain regions  63 . The semiconductor channels ( 59 ,  11 ,  60 ) include the vertical semiconductor channels  60  of the memory stack structures  55 . Alternatively, a horizontal direct strap contact may be formed instead of the source region  61  as will be described below with respect to the third embodiment. 
     Referring to  FIGS.  32  and  33 A , laterally-extending cavities  33  can be formed by removal of the disposable material layers  31  selective to the silicon nitride layers  41 . An isotropic etch process can be employed to remove the disposable material layers  31  selective to the silicon nitride layers  41 . In case the disposable material layers  31  include undoped silicate glass, a doped silicate glass, or organosilicate glass, a wet etch process employing hydrofluoric acid may be employed. In this case, the retro-stepped dielectric material portion  64  and the contact-level dielectric layer  73  can include carbon doped silicate glass to minimize collateral etching. In case the disposable material layers  31  include a silicon-germanium alloy, an etchant employing a mixture of dilute hydrofluoric acid and hydrogen peroxide may be employed for the isotropic etch process. Generally, the laterally-extending cavities  33  can be formed by removing the disposable material layers  31  selective to the silicon nitride layers  41  and the memory opening fill structures  58 . 
     Referring to  FIG.  33 B , an oxidation process can be performed to oxidize portions of the semiconductor liner  151 L within each memory opening fill structure  58  that are physically exposed to the laterally-extending cavities  33 . Portions of the semiconductor liners  151 L that are proximal to the laterally-extending cavities  33  are oxidized to form annular semiconductor oxide portions  251 , which may be annular silicon oxide portions. A vertical stack of annular semiconductor oxide portions  251  can be formed in each memory opening fill structure  58  by oxidation of the physically exposed portions of the semiconductor liners  151 L. A semiconductor oxide liner  253  can be formed by oxidation of physically exposed surface portions of the upper substrate semiconductor layer  10  and the pedestal channel portions  11 . Each semiconductor liner  151 L can be converted into a vertical stack of annular semiconductor oxide portions  251  and a vertical stack of semiconductor portions  151 . The duration of the oxidation process that forms the vertical stacks of annular semiconductor oxide portions  251  can be selected such that each vertical stack of annular semiconductor oxide portions  251  contacts a respective charge storage material layer  154 L. 
     Referring to  FIG.  33 C , a selective isotropic etch process can be performed to etch the annular semiconductor oxide portions  251  selective to the materials of the silicon nitride layers  41 , the charges storage material layers  154 L, and the vertical stacks of semiconductor portions  151 . For example, a wet etch process employing dilute hydrofluoric acid can be performed to remove the annular semiconductor oxide portions  251 . A cylindrical surface segment of an outer sidewall of a charge storage material layer  154 L can be physically exposed at each level of the laterally-extending cavities  33 . Tapered and/or concave surfaces of the semiconductor portions  151  can be physically exposed to the laterally-extending cavities  33 . Each laterally-extending cavity  33  can have planar portion having a uniform height and vertically-protruding annular portions that laterally surround a respective one of the memory opening fill structures  58 . The vertically-protruding annular portions can have a greater height than the planar portion, and can be vertically bounded by tapered and/or concave surfaces of the semiconductor portions  151 . Thus, referring to  FIGS.  33 B and  33 C , each semiconductor liner  151 L can be divided into a vertical stack of semiconductor portions  151  by removing portions of the semiconductor liners  151 L from around the laterally-extending cavities  33 , for example, by oxidation and removal of portions of the oxidized semiconductor liner  151 L that are proximal to the laterally-extending cavities  33 . 
     Referring to  FIG.  33 D , an oxidation process can be performed to oxidize proximal segments of the charge storage material layer  154 L, proximal segments of the vertical stack of semiconductor portions  151 , and proximal portions of the silicon nitride layers  41 . The oxidation process may include a radical oxidation process in which atomic oxygen radicals are employed to provide a higher oxidation rate relative to the oxidation rates of wet or dry thermal oxidation processes. Exemplary radical oxidation processes include in-situ steam generation (ISSG) oxidation, ozone oxidation, and plasma oxidation. For example, the in-situ steam generation oxidation process utilizes oxygen and hydroxyl radicals generated through chemical reactions of hydrogen and oxygen. The in-situ steam generation oxidation process can be performed at low pressures to achieve a sufficiently long radical lifetime. A high volume of oxygen and hydrogen can be employed to reduce the chemical residence time. The reactants can be heated at the physically exposed surfaces of the charge storage material layer  154 L, the vertical stack of semiconductor portions  151 , and the silicon nitride layers  41  to convert surface portions of the charge storage material layer  154 L, the vertical stack of semiconductor portions  151 , and the silicon nitride layers  41  into a semiconductor oxide material, such as silicon oxide. The silicon nitride liner  22  is oxidized at the same time. This oxidation helps prevent or reduce etching of the oxidized silicon nitride liner  22  during a subsequent phosphoric acid etching step. 
     The oxidation process converts surface portions of the silicon nitride layers  41  into silicon oxide portions that are incorporated into insulating layers  132 . In one embodiment, the charge storage material layers  154 L comprise, and/or consists essentially of, silicon nitride, the oxidation process can convert physically exposed portions of the charge storage material layers  154 L into silicon oxide portions that are incorporated into insulating layers  132 . The unoxidized portion of each charge storage material layer  154 L constitutes a vertical stack of charge storage elements (e.g., discrete, vertically separated silicon nitride segments)  154 . In one embodiment, surface regions of the vertical stacks of semiconductor portions  151  that are physically exposed to the laterally-extending cavities  33  are oxidized during the oxidation process, and are incorporated into the insulating layers  132 . 
     An insulating layer  132  including silicon oxide can be formed within each laterally-extending cavity  33 . A subset of the insulating layers  132  is formed within laterally-extending cavities  33  that adjoin a pair of charge storage elements  154 . Each such insulating layer  132  comprises a respective lateral protrusion portion LPP incorporating an oxidized portion of a respective one of the charge storage material layers  154 L, and a respective upper lobe portion ULP and a respective lower lobe portion LLP that incorporate a respective oxidized surface region of the vertical stacks of semiconductor portions  151 . 
     Further, each insulating layer  132  that is formed between a vertically neighboring pair of silicon nitride layers  41  comprises an upper horizontally-extending portion formed by oxidation of an upper silicon nitride layer  41  within the vertically neighboring pair and a lower horizontally-extending portion formed by oxidation of a lower silicon nitride layer  41  within the vertically neighboring pair. In one embodiment, the oxidation process can be continued until the upper horizontally-extending portion adjoins the lower horizontally-extending portion at a horizontal seam  132 S. 
     Generally, insulating layers  132  comprising silicon oxide can be formed by performing an oxidation process that oxidizes surface portions of the silicon nitride layers  41  and portions of the charge storage material layers  154 L that are proximal to the laterally-extending cavities  33 . Remaining portions of the charge storage material layers  154 L form a vertical stack of discrete charge storage elements  154  in each of the memory opening fill structures  58 . In one embodiment, each memory film  50  comprises a tunneling dielectric layer  56  and a vertical stack of discrete charge storage elements  154  that are vertically spaced apart from each other by lateral protrusion portions LPP of a subset of the insulating layers  132 . 
     For the subset of the insulating layers  132  that are formed above the horizontal plane including the top surfaces of the pedestal channel portions  11 , each of the subset of the insulating layers  132  comprises an upper lobe portion ULP that contacts an outer sidewall of one of the discrete charge storage elements  154 , and a lower lobe portion LLP that contacts an outer sidewall of another of the discrete charge storage elements  154 . In one embodiment, each of the subset of the insulating layers  132  comprises a uniform thickness region having a respective uniform thickness and adjoined to the upper lobe portion ULP and to the lower lobe portion LLP, the upper lobe portion ULP protrudes upward above a horizontal plane including a top surface of the uniform thickness region, and the lower lobe portion LLP protrudes downward below a horizontal plane including a bottom surface of the uniform thickness region. 
     In one embodiment, the vertical stack of discrete charge storage elements  154  comprises, and/or consists essentially of, silicon nitride, the lateral protrusion portion LPP of each of the subset of the insulating layers  132  comprises silicon oxynitride at interfacial regions near the vertical stack of discrete charge storage elements  154  such that atomic concentration of nitrogen atoms decreases with a distance from the interfaces with the vertical stack of discrete charge storage elements  154 . 
     In one embodiment, the upper lobe portions ULP and the lower lobe portions LLP of the subset of insulating layers  132  can be formed by oxidation of a nitrogen-free semiconductor material (i.e., the material of the semiconductor liner  151 L), and can be free of nitrogen atoms or comprises nitrogen atoms at an average atomic concentration less than 10% of an average atomic concentration of nitrogen atomic within the lateral protrusion portions LPP. For example, the atomic concentration of nitrogen atoms in the upper lobe portions ULP and the lower lobe portions LLP of the subset of insulating layers  132  may be less than 1 part per million in atomic concentration. 
     In one embodiment, the insulating layers  132  comprise a respective horizontal seam  132 S that does not contact any of the memory opening fill structures  58 . In one embodiment, the insulating layers  132  comprise silicon oxide that is free of carbon atoms or comprise carbon atoms at an atomic concentration less than 1 part per million. 
     In one embodiment, each of the subset of the insulating layers  132  comprises silicon oxide and has a uniform thickness region having a respective uniform thickness, an upper surface portion of the uniform thickness region is doped nitrogen atoms such that atomic concentration of nitrogen atoms increases with a vertical distance from the substrate ( 9 ,  10 ) (due to the interfacial atomic concentration gradient of nitrogen atoms at an interface with unoxidized portions of an overlying silicon nitride layer  42 ), and a lower surface portion of the uniform thickness region is doped with nitrogen atomic such that atomic concentration of nitrogen atoms decreases with the vertical distance from the substrate ( 9 ,  10 ) (due to the interfacial atomic concentration gradient of nitrogen atoms at an interface with unoxidized portions of an underlying silicon nitride layer  42 ). 
     Within each memory opening fill structure  58 , the tunneling dielectric layer  56  has a straight outer sidewall that vertically extends through levels of the subset of the insulating layers  132 , the lateral protrusion portions LPP of a subset of the insulating layers  132  contacts the straight outer sidewall of the tunneling dielectric layer  56 . The lateral protruding portions LPP of the subset of the insulating layers  132  can have convex surfaces that contact a respective concave surface of the vertical stack of discrete charge storage elements  154 . 
     Referring to  FIG.  34   , an etch process (such as an anisotropic etch process or an isotropic etch process) can be performed to remove silicon oxide portions that are located at peripheral portions of the backside trenches  79 . Sidewalls of the silicon nitride layers  41  can be physically exposed around each backside trench  70 . 
     Referring to  FIGS.  35  and  36 A , backside recesses  43  can be formed by removing the remaining portions of the silicon nitride layers  41  selective to the insulating layers  132 . An etchant that selectively etches the second material of the silicon nitride layers  41  with respect to the silicon oxide material of the insulating layers  132  can be introduced into the backside trenches  79 , for example, employing an etch process. Backside recesses  43  are formed in volumes from which the silicon nitride layers  41  are removed. The removal of the second material of the silicon nitride layers  41  can be selective to the silicon oxide material of the insulating layers  132 , the material of the retro-stepped dielectric material portion  65 , the semiconductor material of the upper substrate semiconductor layer  10 , the material of the semiconductor portions  151  and the material of the oxidized silicon nitride liner  22 . 
     In one embodiment, the etch process can be a wet etch process in which the second exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structure  20 , the retro-stepped dielectric material portion  64 , and the memory opening fill structures  58  provide structural support while the backside recesses  43  are present within volumes previously occupied by the silicon nitride layers  41 . Thus, the oxidation of the silicon nitride liner  22  at the step of  FIG.  33 D  helps prevent or reduce etching of the oxidized silicon nitride liner  22  during the above described phosphoric acid etching step. 
     Each backside recess  43  can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess  43  can be greater than the height of the backside recess  43 . A plurality of backside recesses  43  can be formed in the volumes from which the second material of the silicon nitride layers  41  is removed. The memory openings in which the memory opening fill structures  58  are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses  43 . In one embodiment, the memory array region  100  comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate ( 9 ,  10 ). In this case, each backside recess  43  can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings. Each of the plurality of backside recesses  43  can extend substantially parallel to the top surface of the substrate ( 9 ,  10 ). A backside recess  43  can be vertically bounded by a top surface of an underlying insulating layer  132  and a bottom surface of an overlying insulating layer  132 . 
     Referring to  FIG.  36 B , an oxidation process (such as a thermal oxidation process or a plasma oxidation process) can be performed to oxide physically exposed portions of the semiconductor portions  151  and to oxidize physically exposed surface portions of the optional pedestal channel portions  11 . The oxidation process converts a surface portion of each pedestal channel portion  11  into a tubular dielectric spacer  116 , and converts physically exposed segments of the semiconductor portions  151  into a vertical stack of discrete semiconductor oxide portions  152 , such as silicon oxide portions. Within each memory opening fill structure  58 , a remaining segment of the semiconductor portions  151  may include an annular horizontal semiconductor portion  253  that contacts an annular top surface of a pedestal channel portion  11 . Generally, a vertical stack of discrete semiconductor oxide portions  152  can be formed by oxidizing a vertical stack of semiconductor portions  151  within each memory opening fill structure  58 . 
     In one embodiment, each tubular dielectric spacer  116  can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying a hole or forming a new hole into the shape of a torus. The tubular dielectric spacers  116  include a dielectric material that includes the same semiconductor element as the pedestal channel portions  11  and additionally includes oxygen atoms. The lateral thickness of the semiconductor oxide portions  152  may be in a range from 2 nm to 12 nm, such as from 4 nm to 8 nm, although lesser and greater thicknesses may also be employed. 
     Referring to  FIG.  36 C , a backside blocking dielectric layer  44  can be optionally formed. The backside blocking dielectric layer  44 , if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses  43 . The backside blocking dielectric layer  44  can be formed on the physically exposed surface of the semiconductor oxide portions  152  and the insulating layers  132 . In one embodiment, the backside blocking dielectric layer  44  can be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer  44  can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer  44  can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed. 
     The dielectric material of the backside blocking dielectric layer  44  can comprise, and/or can consist essentially of, a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer  44  can include a silicon oxide layer. The backside blocking dielectric layer  44  can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. A backside cavity is present within the portion of each backside trench  79  that is not filled with the backside blocking dielectric layer  44 . 
     Referring to  FIGS.  36 D,  37 A and  37 B , a metallic barrier layer  46 A can be deposited in the backside recesses  43 . The metallic barrier layer  46 A includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer  46 A can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer  46 A can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer  46 A can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer  46 A can consist essentially of a conductive metal nitride such as TiN. 
     A metal fill material is deposited in the plurality of backside recesses  43 , on the sidewalls of the at least one the backside trench  79 , and over the top surface of the contact level dielectric layer  73  to form a metallic fill material layer  46 B. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer  46 B can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer  46 B can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer  46 B can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer  46 B can be deposited employing a fluorine-containing precursor gas such as WF 6 . In one embodiment, the metallic fill material layer  46 B can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer  46 B is spaced from the insulating layers  132  and the memory stack structures  55  by the metallic barrier layer  46 A, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough. 
     A plurality of electrically conductive layers  46  can be formed in the plurality of backside recesses  43 , and a continuous metallic material layer can be formed on the sidewalls of each backside trench  79  and over the contact level dielectric layer  73 . Each electrically conductive layer  46  includes a portion of the metallic barrier layer  46 A and a portion of the metallic fill material layer  46 B that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers  132 . The continuous metallic material layer includes a continuous portion of the metallic barrier layer  46 A and a continuous portion of the metallic fill material layer  46 B that are located in the backside trenches  79  or above the contact level dielectric layer  73 . 
     Each silicon nitride layer  41  can be replaced with an electrically conductive layer  46 . A backside cavity is present in the portion of each backside trench  79  that is not filled with the backside blocking dielectric layer  44  and the continuous metallic material layer. An optional tubular dielectric spacer  116  laterally surrounds the optional pedestal channel portion  11 . A bottommost electrically conductive layer  46  laterally surrounds each tubular dielectric spacer  116  upon formation of the electrically conductive layers  46 . 
     The deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each backside trench  79  and from above the contact level dielectric layer  73 , for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses  43  constitutes an electrically conductive layer  46 . Each electrically conductive layer  46  can be a conductive line structure. Thus, the silicon nitride layers  41  are replaced with the electrically conductive layers  46 . 
     Each electrically conductive layer  46  can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer  46  are the control gate electrodes for the vertical memory devices including the memory stack structures  55 . In other words, each electrically conductive layer  46  can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices. 
     In one embodiment, the removal of the continuous electrically conductive material layer can be selective to the material of the backside blocking dielectric layer  44 . In this case, a horizontal portion of the backside blocking dielectric layer  44  can be present at the bottom of each backside trench  79 . In another embodiment, the removal of the continuous electrically conductive material layer may not be selective to the material of the backside blocking dielectric layer  44  or, the backside blocking dielectric layer  44  may not be employed. 
     In one embodiment, each of the memory opening fill structures  58  comprise a vertical stack of semiconductor oxide portions  152  that contact an outer sidewall of a respective one of the discrete charge storage elements  154 . The upper lobe portions ULP and the lower lobe portions LLP of the insulating layers  132  contact a respective one of the semiconductor oxide portions  152 . Backside blocking dielectric layers  44  can be located between, and can contact, a respective one of the electrically conductive layers  46  and a respective one of the semiconductor oxide portions  152 . 
     Referring to  FIG.  38   , an insulating material layer can be formed in the backside trenches  79  and over the contact level dielectric layer  73  by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed. 
     An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact level dielectric layer  73  and at the bottom of each backside trench  79 . Each remaining portion of the insulating material layer constitutes an insulating spacer  74 . A backside cavity is present within a volume surrounded by each insulating spacer  74 . A top surface of a source region  61  can be physically exposed at the bottom of each backside trench  79 . 
     A backside contact via structure  76  can be formed within each backside cavity. Each contact via structure  76  can fill a respective cavity. The contact via structures  76  can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside trench  79 . For example, the at least one conductive material can include a conductive liner  76 A and a conductive fill material portion  76 B. The conductive liner  76 A can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner  76 A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion  76 B can include a metal or a metallic alloy. For example, the conductive fill material portion  76 B can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof. 
     The at least one conductive material can be planarized employing the contact level dielectric layer  73  overlying the alternating stack ( 32 ,  46 ) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact level dielectric layer  73  can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches  79  constitutes a backside contact via structure  76 . 
     The backside contact via structure  76  extends through the alternating stack ( 32 ,  46 ), and contacts a top surface of the source region  61 . If a backside blocking dielectric layer  44  is employed, the backside contact via structure  76  can contact a sidewall of the backside blocking dielectric layer  44 . 
     Alternatively, at least one dielectric material, such as silicon oxide, may be conformally deposited in the backside trenches  79  by a conformal deposition process. Each portion of the deposited dielectric material that fills a backside trench  79  constitutes a backside trench fill structure. In this case, each backside trench fill structure may fill the entire volume of a backside trench  79  and may consist essentially of at least one dielectric material. In the third embodiment described below, the source region  61  may be omitted, and a lateral source contact structure (e.g., direct strap contact) may contact an side of the lower portion of the semiconductor channel  60 . 
     Referring to  FIGS.  39 A and  39 B , additional contact via structures ( 88 ,  86 ,  8 P) can be formed through the contact level dielectric layer  73 , and optionally through the retro-stepped dielectric material portion  65 . For example, drain contact via structures  88  can be formed through the contact level dielectric layer  73  on each drain region  63 . Word line contact via structures  86  can be formed on the electrically conductive layers  46  through the contact level dielectric layer  73 , and through the retro-stepped dielectric material portion  65 . Peripheral device contact via structures  8 P can be formed through the retro-stepped dielectric material portion  65  directly on respective nodes of the peripheral devices. 
     The method employed to form the second exemplary structure can be applied to other semiconductor structures such as a third semiconductor structure of the third embodiment illustrated in  FIG.  40   . In the third exemplary structure, semiconductor devices  700  may be formed over an entire area of a semiconductor die, and metal interconnect structures  780  embedded within interconnect-level dielectric material layers  760  can be formed over the semiconductor devices. 
     Source-level material layers  110  including at least source contact layer can be formed over the interconnect-level dielectric material layers, and at least one alternating stack of insulating layers  132  and electrically conductive layers  46  can be formed above the source-level material layers  110 . Intermediate-level dielectric material layers such as a first insulating cap layer  170 , an inter-level dielectric material layer  180 , and a second insulating cap layer  270  can be formed as needed. A first retro-stepped dielectric material portion  164  and a second retro-stepped dielectric material portion  264  may be formed, which can include the same type of dielectric material as the retro-stepped dielectric material portion  64  described above. Dielectric pillar portions  584  may be optionally formed through the alternating stacks of insulating layers  132  and electrically conductive layers  46 . A via-level dielectric layer  280  can be formed above the contact-level dielectric layer  73 , and various contact via structures ( 88 ,  86 ) can be formed. Through-memory-level connection via structures  488  can be formed through the retro-stepped dielectric material potions ( 164 ,  264 ) or through the dielectric pillar structures  584 . A line-level dielectric layer  290  can be formed above the via-level dielectric layer  280 , and metal line structures ( 96 ,  98 ) can be formed in the line-level dielectric layer  290 . In one embodiment, the metal line structures ( 96 ,  98 ) can include bit lines  98  that contact a respective one of the drain contact via structures  88  and interconnection metal lines  96  that contact the word line contact via structures  86  or the through-memory-level connection via structures  488 . 
     In the third embodiment, a sacrificial source layer is formed below the lower most disposable material layer  31  and the pedestal channel portions and the source regions  61  are omitted  11 . Instead, the backside trenches  79  are extend down by etching to expose the sacrificial source layer at the step shown in  FIG.  34   . The sacrificial source layer is then removed through the backside trenches  79  by selective etching to form a source cavity. The memory film  50  exposed in the source cavity is removed by selective etching to expose a sidewall of the vertical semiconductor channel  60 . A doped semiconductor direct strap contact is then formed in the source cavity in contact with the exposed sidewall of the vertical semiconductor channel  60 . 
     Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers  132  and electrically conductive layers  46  located over a substrate ( 9 ,  10 ); memory openings  49  vertically extending through the alternating stack ( 132 ,  46 ); and memory opening fill structures  58  located in the memory openings  49 , wherein: each of the memory opening fill structures  58  comprises a vertical semiconductor channel  60  and a memory film  50 ; and the memory film  50  comprises a tunneling dielectric layer  56  and a vertical stack of discrete charge storage elements  154  that are vertically spaced apart from each other by lateral protrusion portions LPP of a subset of the insulating layers  132 . 
     Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.