Patent Publication Number: US-11647626-B2

Title: Method for fabricating semiconductor device with tapering impurity region

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional application of U.S. Non-Provisional application Ser. No. 16/867,214 filed on May 5, 2020, which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a tapering impurity region. 
     DISCUSSION OF THE BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process, and such issues are continuously increasing. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity. 
     This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure. 
     SUMMARY 
     One aspect of the present disclosure provides a semiconductor device including a substrate, a word line structure positioned in the substrate, an impurity region including an upper portion positioned adjacent to the word line structure and a lower portion positioned below the upper portion. The upper portion has a tapering cross-sectional profile. 
     In some embodiments, the upper portion of the impurity region includes a top surface substantially coplanar with a top surface of the substrate and two tapering sidewalls connected to the top surface of the upper portion of the impurity region. An angle between one of the two tapering sidewalls and the top surface of the upper portion of the impurity region is between about 45 degree and about 60 degree. 
     In some embodiments, a thickness of the upper portion of the impurity region is equal to or less than one-fifth of a thickness of the impurity region. 
     In some embodiments, the word line structure includes a word line dielectric layer contacting the lower portion of the impurity region, a word line electrode positioned on the word line dielectric layer, and a word line capping layer positioned on the word line electrode. 
     In some embodiments, a top surface of the word line electrode is at a vertical level lower than a vertical level of the upper portion of the impurity region. 
     In some embodiments, the word line dielectric layer has a thickness between about 10 angstroms and about 30 angstroms. 
     In some embodiments, the semiconductor device includes a capacitor bottom contact positioned on the impurity region. A width of the capacitor bottom contact is less than a width of the top surface of the upper portion of the impurity region. 
     In some embodiments, the capacitor bottom contact includes a bottom contact barrier layer positioned on the impurity region and a bottom contact conductive layer positioned on the bottom contact barrier layer. 
     In some embodiments, the bottom contact barrier layer is a stacked layer including a bottom layer formed of titanium and a top layer formed of titanium nitride. 
     In some embodiments, the bottom contact conductive layer is a stacked layer including a bottom layer formed of tungsten nitride and a top layer formed of tungsten. 
     In some embodiments, the semiconductor device includes two bottom contact spacers positioned on two sides of the capacitor bottom contact. The two bottom contact spacers are formed of silicon nitride. 
     In some embodiments, the semiconductor device includes a capacitor top contact positioned on the capacitor bottom contact. 
     In some embodiments, the capacitor top contact includes a first conductive layer positioned on the capacitor bottom contact, a second conductive layer positioned on the first conductive layer, and a third conductive layer positioned on the second conductive layer. 
     In some embodiments, the first conductive layer is formed of doped polysilicon, the second conductive layer is formed of metal silicide and has a thickness between about 2 nm and about 20 nm, and the third conductive layer is formed of metal or metal nitride. 
     Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a substrate, forming a word line structure in the substrate, performing an isotropic etch process to form a first recess in the substrate, performing an anisotropic etch process to expand the first recess and form a second recess below the first recess, and forming an impurity region in the first recess and in the second recess and adjacent to the word line structure. The first recess includes tapering sidewalls. 
     In some embodiments, the impurity region is formed of silicon phosphide, phosphorus-doped silicon carbon, silicon carbide, silicon germanium, silicon-germanium-tin alloy, or silicon-germanium-boron alloy. 
     In some embodiments, the method for fabricating the semiconductor device includes a step of forming a capacitor bottom contact on the impurity region. 
     In some embodiments, the method for fabricating the semiconductor device includes a step of forming bottom contact spacers on two sides of the capacitor bottom contact. 
     In some embodiments, the step of forming the word line structure in the substrate includes sequentially forming a pad oxide layer and a pad nitride layer on the substrate, forming a word line trench so as to penetrate the pad oxide layer, the pad nitride layer, and extend to the substrate, forming a layer of first insulating material in the word line trench, forming a word line electrode on the layer of first insulating material and in the word line trench, and forming a layer of second insulating material on the word line electrode and filling the word line trench, and performing a planarization process to turn the layer of first insulating material into a word line dielectric layer and turn the layer of second insulating material into a word line capping layer. The word line dielectric layer, the word line electrode, and the word line capping layer together form the word line structure. 
     In some embodiments, the first insulating material is a high-k dielectric material. 
     Due to the design of the semiconductor device of the present disclosure, the wider (or greater) dimension of the upper portions of the impurity regions may provide an extra process tolerance for formation of contact thereon. As a result, the yield of fabrication of the semiconductor device may be improved. 
     The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    illustrates, in a flowchart diagram form, a method for fabricating a semiconductor device in accordance with one embodiment of the present disclosure; 
         FIG.  2    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure; 
         FIG.  3    is a schematic cross-sectional view diagram taken along a line A-A′ in  FIG.  1    illustrating part of a flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure; 
         FIG.  4    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure; 
         FIGS.  5  to  14    are schematic cross-sectional view diagrams taken along the line A-A′ in  FIG.  4    illustrating part of the flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure; 
         FIG.  15    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure; 
         FIGS.  16  to  19    are schematic cross-sectional view diagrams taken along the line A-A′ in  FIG.  15    illustrating part of the flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure; 
         FIG.  20    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure; 
         FIGS.  21  to  23    are schematic cross-sectional view diagrams taken along the line A-A′ in  FIG.  20    illustrating part of the flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure; 
         FIG.  24    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure; 
         FIGS.  25  to  28    are schematic cross-sectional view diagrams taken along the line A-A′ in  FIG.  24    illustrating part of the flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure; 
         FIG.  29    illustrates, in a schematic cross-sectional view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     It should be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer, or intervening elements or layers may be present. 
     It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless indicated otherwise, these terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure. 
     Unless the context indicates otherwise, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes. 
     It should be noted that, the term “about” modifying the quantity of an ingredient, component, or reactant of the present disclosure employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. Yet, in another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value. 
     In the present disclosure, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device. Specifically, semiconductor devices of embodiments of the present disclosure may be dynamic random-access memory devices. 
     It should be noted that, in the description of the present disclosure, above (or up) corresponds to the direction of the arrow of the direction Z, and below (or down) corresponds to the opposite direction of the arrow of the direction Z. 
     It should be noted that, in the description of the present disclosure, a surface of an element (or a feature) located at the highest vertical level along the direction Z is referred to as a top surface of the element (or the feature). A surface of an element (or a feature) located at the lowest vertical level along the direction Z is referred to as a bottom surface of the element (or the feature). 
     It should be noted that the terms “forming,” “formed” and “form” may mean and include any method of creating, building, patterning, implanting, or depositing an element, a dopant or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusing, depositing, growing, implantation, photolithography, dry etching and wet etching. 
       FIG.  1    illustrates, in a flowchart diagram form, a method  10  for fabricating a semiconductor device in accordance with one embodiment of the present disclosure.  FIG.  2    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure.  FIG.  3    is a schematic cross-sectional view diagram taken along a line A-A′ in  FIG.  1    illustrating part of a flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure. 
     With reference to  FIGS.  1  to  3   , at step S 11 , a substrate  101  may be provided and an isolation layer  103  may be formed in the substrate  101 . 
     The substrate  101  may be formed of, for example, silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, indium phosphorus or other IV-IV, III-V or II-VI semiconductor materials. The substrate  101  may have a first lattice constant. In some embodiments, the substrate  101  may include an organic semiconductor or a layered semiconductor such as silicon/silicon germanium, silicon-on-insulator or silicon germanium-on-insulator. 
     The isolation layer  103  may be formed of, for example, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. The isolation layer  103  may define an active area  105  of the substrate  101 . The active area  105  may be extended along a first direction S in a top-view perspective. It should be noted that, in the present disclosure, silicon oxynitride refers to a substance which contains silicon, nitrogen, and oxygen and in which a proportion of oxygen is greater than that of nitrogen. Silicon nitride oxide refers to a substance which contains silicon, oxygen, and nitrogen and in which a proportion of nitrogen is greater than that of oxygen. 
     It should be noted that the active area  105  may include a portion of the substrate  101  and a space above the portion of the substrate  101 . Describing an element as being disposed on the active area  105  means that the element is disposed on a top surface of the portion of the substrate  101 . Describing an element as being disposed above the active area  105  means that the element is disposed above the top surface of the portion of the substrate  101 . In some embodiments, describing an element as being disposed in the active area  105  means that the element is disposed in the portion of the substrate  101 ; however, a top surface of the element may be even with the top surface of the portion of the substrate  101 . In some embodiments, describing an element as being disposed in the active area  105  means that some portions of the element are disposed in the substrate  101  and other portions of the element are disposed on or above the substrate  101 . 
       FIG.  4    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure.  FIGS.  5  to  14    are schematic cross-sectional view diagrams taken along the line A-A′ in  FIG.  4    illustrating part of the flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure. 
     With reference to  FIG.  1    and  FIGS.  4  to  11   , at step S 13 , a plurality of word line structures  301  may be formed in the substrate  101 . 
     With reference to  FIGS.  4  and  5   , a pad oxide layer  905 , a pad nitride layer  907 , and a first mask layer  801  may be sequentially formed on the substrate  101 . The pad oxide layer  905  may be formed, for example, silicon oxide. The pad nitride layer  907  may be formed of, for example, silicon nitride. The first mask layer  801  may include a plurality of openings  801 WL. For convenience of description, only two adjacent openings  801 WL are described. In a top-view perspective, the two openings  801 WL may respectively extended along a second direction Y and parallel to each other. The second direction Y may be slanted with respective to the first direction S. The two openings  801 WL may intersect with the active area  105 . The openings  801 WL may define positions of the plurality of word line structures  301  as will be fabricated later. 
     With reference to  FIG.  6   , a first etch process may be performed to remove portions of the pad oxide layer  905  and portions of the pad nitride layer  907  and concurrently form a plurality of first openings  909 . The plurality of first openings  909  may be expanded from the openings  8031 L through the first etch process. 
     With reference to  FIG.  7   , a second etch process may be performed to remove portions of the substrate  101  and concurrently form a plurality of word line trenches  911 . The plurality of word line trenches  911  may be expanded from the plurality of first openings  909  through the second etch process. For convenience of description, only one word line trench  911  is described. After the second etch process, the first mask layer  801  may be removed. In some embodiments, the first mask layer  801  may be removed before the second etch process. 
     With reference to  FIG.  8   , a layer of first insulating material  913  may be formed on the top surface of the pad nitride layer  907  and in the word line trench  911 . In some embodiments, the first insulating material  913  may be, for example, silicon oxide. In some embodiments, the first insulating material  913  may be, for example, a high-k dielectric material such as metal oxide, metal nitride, metal silicate, transition metal-oxide, transition metal-nitride, transition metal-silicate, oxynitride of metal, metal aluminate, zirconium silicate, zirconium aluminate, or a combination thereof. Specifically, the first insulating material  913  may be formed of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, barium zirconium oxide, lanthanum silicon oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination thereof. 
     With reference to  FIG.  9   , a word line electrode  305  (for convenience of description, only one word line electrode  305  is described) may be formed in the word line trench  911  and on the layer of first insulating material  913 . The word line electrode  305  may be formed of, for example, a conductive material such as polysilicon, silicon germanium, metal, metal alloy, metal silicide, metal nitride, metal carbide, or a combination including multilayers thereof. The metal may be, for example, aluminum, copper, tungsten, or cobalt. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. In some embodiments, the word line electrode  305  may be formed by depositing the conductive material in the word line trench  911  and applying an etch back process to remove extra conductive material. 
     With reference to  FIG.  10   , a layer of second insulating material  915  may be formed on the top surface of the layer of first insulating material  913  and in the word line trench  911 . The word line trench  911  may be completely filled by the layer of second insulating material  915 . The second insulating material  915  may be formed of, for example, silicon oxide, a high-k dielectric material, or a combination thereof. 
     With reference to  FIG.  11   , a planarization process, such as chemical mechanical polishing, may be performed until the top surface of the substrate  101  is exposed to provide a substantially flat surface for subsequent processing steps. After the planarization process, the layer of first insulating material  913  may be turned into a word line dielectric layer  303  and the layer of second insulating material  915  may be turned into a word line capping layer  307 . Top surface of the word line capping layer  307  may be substantially coplanar with the top surface of the substrate  101 . The word line dielectric layer  303  may have a thickness between about 10 angstroms and about 30 angstroms. In some embodiments, the word line capping layer  307  may be a stacked layer including a bottom capping layer formed of high-k dielectric material and a top capping layer formed of silicon oxide. The top capping layer formed of silicon oxide may reduce electric field at the top surface of the substrate  101 ; therefore, leakage current may be reduced. In some embodiments, a liner layer may be formed between the word line dielectric layer  303  and the word line electrode  305 . The liner layer may be formed of, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, and combination thereof. The liner layer may be employed to prevent the word line electrode  305  from flaking or spalling from the word line dielectric layer  303 . 
     The word line dielectric layer  303 , the word line electrode  305 , and the word line capping layer  307  together form the word line structure  301 . 
     With reference to  FIG.  1    and  FIGS.  12  to  14   , at step S 15 , a plurality of impurity regions  201 B,  201 C may be formed in the substrate  101 . 
     With reference to  FIG.  12   , a first etch process may be performed to remove portions of the substrate  101 , portions of the word line dielectric layer  303 , and portions of the word line capping layer  307  and concurrently form a plurality of first recesses  901 . For convenience of description, only one first recess  901  is described. The first recess  901  may have two tapering sidewalls opposing to each other. Horizontal distances between the two tapering sidewalls may gradually decrease from top to bottom along the direction Z. An angle α between any one of the tapering sidewall and the main plane of the substrate  101  (i.e., the X-Y plane) may be between about 45 degree and about 60 degree. In some embodiments, the first etch process may be an isotropic plasma dry etch process. In some embodiments, the first etch process may be a wet etch process. 
     It should be noted that the selectivity of an etching process may be generally expressed as a ratio of etching rates. For example, if one material is etched 25 times faster than other materials, the etch process may be described as having a selectivity of 25:1 or simply 25. In this regard, higher ratios or values indicate more selective etching processes. 
     With reference to  FIG.  13   , a second etch process, such as an anisotropic plasma dry etch process, may be performed to remove portions of the substrate  101  and form a plurality of second recesses  903 . In some embodiments, in the second etch process, an etching rate for the substrate  101  may be greater than an etching rate of the word line dielectric layer  303  and an etching rate of the word line capping layer  307 . The selectivity of the second etch process may be greater than or equal to about 10, greater than or equal to about 12, greater than or equal to about 15, greater than or equal to about 20, or greater than or equal to about 25. 
     For convenience of description, only one second recess  903  is described. The second recess  903  may be expanded from the bottom surface of the first recess  901 . In some embodiments, the bottom surface of the second recess  903  may be curved. In some embodiments, the bottom surface of the second recess  903  may be flat. In some embodiments, the second recess  903  may have an U-shaped cross-sectional profile. Corner effects may be avoided if the second recess  903  have an U-shape cross-sectional profile. A depth D 1  of the first recess  901  may be equal to or less than one-fourth of a depth D 2  of the second recess  903 . In other words, the depth D 1  of the first recess  901  may be equal to or less than one-fifth of a total depth D 3  of sum of the first recess  901  and the second recess  903 . 
     With reference to  FIG.  14   , an epitaxial growth process may be performed to fill the plurality of first recesses  901  and the plurality of second recesses  903  and concurrently form the plurality of impurity regions  201 B,  201 C. The epitaxial growth process may be chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, a process temperature of the epitaxial growth process may be between about 700° C. and about 850° C. A process pressure of the epitaxial growth process may be between about 5 Torr to about 50 Torr. In some embodiments, a planarization process, such as chemical mechanical polishing, may be optionally performed to provide a substantially flat surface for subsequent processing steps. In some embodiments, the plurality of impurity regions  201 B,  201 C may be formed protruding from the top surface of the substrate  101 . 
     The shape (or structure) of the plurality of impurity regions  201 B,  201 C may be determined by the plurality of first recesses  901  and the plurality of second recesses  903 . The impurity region  201 B may be located between the two word line structures  301 . The impurity regions  201 C may be respectively correspondingly located opposite to the impurity region  201 B with the two word line structures  301  interposed therebetween. The plurality of impurity regions  201 B,  201 C may include upper portions  203  and lower portions  205 . The upper portions  203  of the plurality of impurity regions  201 B,  201 C may be located at where the plurality of first recesses  901  previously was. The lower portions  205  may be located at where the plurality of second recesses  903  previously was. 
     For convenience of description, only one upper portion  203  and one lower portion  205  are described. The upper portion  203  may include two tapering sidewalls  203 S. A horizontal distance between the two tapering sidewalls  203 S (i.e., a width of the upper portion  203 ) may gradually decrease from top to bottom along the direction Z. An angle α between any one of the tapering sidewall  203 S and the top surface  203 TS of the upper portion  203  may be between about 45 degree and about 60 degree. In other words, the upper portion  203  may have a tapering cross-sectional profile. The upper portion  203  may have bottommost points  203 B respectively located at the intersections between the tapering sidewalls  203 S and the lower portion  205 . A thickness T 1 (i.e., a vertical distance between the top surface  203 TS of the upper portion  203  and the bottommost point  203 B) of the upper portion  203  may be equal to or less than one-fourth of a thickness T 2  (i.e., a vertical distance between the bottom surface  205 BS of the lower portion  205  and the bottommost point  203 B) of the lower portion  205 . In other words, the thickness T 1  of the upper portion  203  may be equal to or less than one-fifth of a total thickness T 3  (i.e., a vertical distance between the top surface  203 TS of the upper portion  203  and the bottom surface  205 BS of the lower portion  205 ) of the impurity region  203 B/ 203 C. 
     In some embodiments, the plurality of impurity regions  201 B,  201 C may be formed of, for example, silicon phosphide (SiP), phosphorus-doped silicon carbon (SiCP), silicon carbide (SiC), silicon germanium (SiGe), silicon-germanium-tin alloy (SiGeSn), silicon-germanium-boron alloy (SiGeB), or other suitable semiconductor material. 
     In some embodiments, the impurity region  201 B/ 201 C may be doped with a dopant such as phosphorus or boron. The dopant concentration of the impurity region  201 B/ 201 C may be uniform. In some embodiments, the dopant concentration of the impurity region  201 B/ 201 C may be gradually increased from bottom to top. In some embodiments, the dopant concentration of the upper portion  203  may be greater than the dopant concentration of the lower portion  205 . In some embodiments, the dopant concentration of the upper portion  203  may be gradually increased from the bottommost points  203 B to the top surface  203 TS. The greater dopant concentration may reduce the resistance between the impurity region  201 B/ 201 C and contacts which will be formed later thereon. 
     In some embodiments, the top surface  305 TS of the word line electrode  305  may be at a vertical level higher than the vertical level of the bottommost points  203 B. In some embodiments, the top surface  305 TS of the word line electrode  305  and the bottommost points  203 B may be at a same vertical level. In some embodiments, the word line dielectric layer  303  may contact the lower portions  205  of the impurity regions  201 B/ 201 C. 
     In some embodiments, with reference to  FIG.  29   , the impurity region  201 B/ 201 C may include an outer layer  207  and an inner layer  209 . The outer layer  207  may be formed on the tapering sidewalls of the first recess  901  and the sidewalls and the bottom surface  205 BS of the second recess  903 . The outer layer  207  may have an U-shaped cross-sectional profile and may have an recessed portion. The inner layer  209  may be formed filling the recessed portion of the outer layer  207 . The dopant concentration of the outer layer  207  may be lower than the dopant concentration of the inner layer  209 . 
       FIG.  15    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure.  FIGS.  16  to  19    are schematic cross-sectional view diagrams taken along the line A-A′ in  FIG.  15    illustrating part of the flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure. 
     With reference to  FIG.  1    and  FIGS.  15  to  17   , at step S 17 , a bit line  401  and two capacitor bottom contacts  501  may be formed on the substrate  101 . 
     With reference to  FIGS.  15  and  16   , a layer of barrier material  917 , a layer of first conductive material  919 , a layer of mask material  921 , and a second mask layer  803  may be sequentially formed on the substrate  101 . The barrier material  917  may be, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, and combination thereof. The first conductive material  919  may be, for example, a conductive material such as doped polysilicon, metal, metal nitride, or metal silicide. The mask material  921  may be, for example, silicon nitride. 
     The second mask layer  803  may include a line portion  803 L and two circle portions  803 C. In a top-view perspective, the line portion  803 L may be line shape and may extend along a third direction X. The third direction X may be perpendicular to the second direction Y and be slanted with respect to the first direction S. The line portion  803 L may be formed intersecting the impurity region  201 B. The line portion  803 L may define the position of the bit line  401  as will be fabricated later. In a cross-sectional perspective, a line width W 1  of the line portion  803 L may be equal to or less than a width W 2  of the upper portion  203  of the impurity region  201 B. In a top-view perspective, the two circle portions  803 C may be round shape and may be respectively correspondingly formed on the impurity regions  201 C. The two circle portions  803 C may define positions of the two capacitor bottom contacts  501  as will be fabricated later. For convenience of description, only one circle portion  803 C is described. In a cross-sectional perspective, a width W 3  of the circle portion  803 C may be equal to or less than a width W 4  of the upper portion  203  of the impurity region  201 C. 
     With reference to  FIG.  17   , an etch process may be performed to remove portions of the layer of barrier material  917 , the layer of first conductive material  919 , and the layer of mask material  921 . After the etch process, the layer of barrier material  917  may be turned into a bit line barrier layer  403  and two bottom contact barrier layers  503 . The layer of first conductive material  919  may be turned into a bit line conductive layer  405  and two bottom contact conductive layers  505 . The layer of mask material  921  may be turned into a bit line mask layer  407  and two bottom contact mask layers  507 . In some embodiments, due to the lesser width of the line portion  803 L and the lesser width of the circle portion  803 C, portions of the impurity regions  201 B/ 201 C may be also removed by the etch process and a plurality of gaps  203 G may be formed adjacent to the tapering sidewalls  203 S. 
     The bit line barrier layer  403 , the bit line conductive layer  405 , and the bit line mask layer  407  together form the bit line  401 . The bottom contact barrier layers  503 , the bottom contact conductive layers  505 , and the bottom contact mask layers  507  together form the capacitor bottom contact  501 . The shapes and dimension of the third mask layer  805  may inherited by the bit line  401  and the two capacitor bottom contacts  501 . For example, in a cross-sectional perspective, the width W 3  of the capacitor bottom contact  501  may be equal to or less than the width W 4  of the top surface  203 TS of the upper portion  203  of the impurity region  201 C. 
     In some embodiments, the bit line barrier layer  403  and the bottom contact barrier layer  503  may be stacked layer including a bottom layer formed of titanium and a top layer formed of titanium nitride. In some embodiments, the bit line conductive layer  405  and the bottom contact conductive layers  505  may be stacked layer including a bottom layer formed of tungsten nitride and a top layer formed of tungsten. In some embodiments, a bit line contact (not shown) may be formed between the bit line  401  and the upper portion  203  of the impurity region  201 B. In some embodiments, the bit line contact may be buried in the upper portion  203  of the impurity region  201 B. 
     With reference to  FIGS.  1 ,  18 , and  19   , at step S 19 , two bit line spacers  409  may be formed on sides of the bit line  401  and a plurality of bottom contact spacers  509  may be formed on sides of the two capacitor bottom contacts  501 . 
     With reference to  FIG.  18   , the third mask layer  805  may be removed. A layer of spacer material  923  may be formed to cover the top surface of the substrate  101 , the bit line  401 , and the two capacitor bottom contacts  501 . The spacer material  923  may be, for example, silicon nitride. 
     With reference to  FIG.  19   , an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the layer of spacer material  923  and concurrently form the two bit line spacers  409  and the plurality of bottom contact spacers  509 . In some embodiments, the two bit line spacers  409  and the plurality of bottom contact spacers  509  may partially fill the plurality of gaps  203 G. In some embodiments, the two bit line spacers  409  and the plurality of bottom contact spacers  509  may completely fill the plurality of gaps  203 G. 
       FIG.  20    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure.  FIGS.  21  to  23    are schematic cross-sectional view diagrams taken along the line A-A′ in  FIG.  20    illustrating part of the flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure. 
     With reference to  FIG.  1    and  FIGS.  20  to  23   , at step S 21 , two capacitor top contacts  601  may be formed on the two capacitor bottom contacts  501 . 
     With reference to  FIGS.  20  and  21   , the first insulating layer  107  may be formed on the substrate  101  and cover the bit line  401  and the two capacitor bottom contacts  501 . The first insulating layer  107  may be silicon oxide, flowable oxide, undoped silica glass, borosilica glass, phosphosilica glass, borophosphosilica glass, fluoride silicate glass, carbon-doped silicon oxide, or a combination thereof. A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps. 
     With reference to  FIGS.  20  and  21   , a third mask layer  805  may be formed on the first insulating layer  107 . The third mask layer  805  may include two openings  805 C. In a top-view perspective, the two openings  805 C may have a round shape or an oval shape. The two openings  805 C may be respectively correspondingly formed on the two capacitor bottom contacts  501 . The two openings  805 C may define positions of the capacitor top contacts  601  as will be fabricated later. 
     With reference to  FIG.  22   , an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the first insulating layer  107 , the bottom contact mask layers  507 , and portions of the bottom contact spacers  509  and concurrently form second openings  925 . The top surfaces of the two bottom contact conductive layers  505  may be exposed through the second openings  925 . In some embodiments, a width W 5  of the second opening  925  may be greater than the width W 3  of the capacitor bottom contact  501 . In some embodiments, the width W 5  of the second opening  925  may be equal to or less than the width W 3  of the capacitor bottom contact  501 . 
     With reference to  FIG.  23   , the two capacitor top contacts  601  may be formed in the second openings  925 . For convenience of description, only one capacitor top contact  601  is described. In some embodiments, the capacitor top contact  601  may be a single layer including a conductive material such as doped polysilicon, metal, metal nitride, or metal silicide. The capacitor top contact  601  may be formed by depositing the conductive material into the second opening  925  and subsequently performing a planarization process to remove excess material and provide a substantially flat surface for subsequent processing steps. 
     In some embodiments, the capacitor top contact  601  may include a first conductive layer  603 , a second conductive layer  605 , and a third conductive layer  607  sequentially formed in the second opening  925 . The first conductive layer  603  may be formed of, for example, doped polysilicon. The first conductive layer  603  may be formed by performing a deposition process and a subsequent etch back process. 
     The second conductive layer  605  may be formed of, for example, titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The second conductive layer  605  may have a thickness between about 2 nm and about 20 nm. Firstly, a layer of conductive material may be formed filled the second opening  925 . The conductive material may include, for example, titanium, nickel, platinum, tantalum, or cobalt. A thermal treatment may be subsequently performed. During the thermal treatment, metal atoms of the metal layer may react chemically with silicon atoms of first conductive layer  603  to form the second conductive layer  605 . The thermal treatment may be a dynamic surface annealing process. After the thermal treatment, a cleaning process may be performed to remove the unreacted conductive material. The cleaning process may use etchant such as hydrogen peroxide and an SC-1 solution. 
     The third conductive layer  607  may be formed of, for example, metal or metal nitride. The third conductive layer  607  may be formed by performing a deposition process and a subsequent planarization process to remove excess material and provide a substantially flat surface for subsequent processing steps. 
       FIG.  24    illustrates, in a schematic top-view diagram, an intermediate semiconductor device in accordance with one embodiment of the present disclosure.  FIGS.  25  to  28    are schematic cross-sectional view diagrams taken along the line A-A′ in  FIG.  24    illustrating part of the flow for fabricating the semiconductor device in accordance with one embodiment of the present disclosure. 
     With reference to  FIG.  1    and  FIGS.  24  to  28   , at step S 23 , two capacitor structures  701  may be formed on the two capacitor top contacts  601 . 
     With reference to  FIGS.  24  and  25   , a second insulating layer  109  and a fourth mask layer  807  may be sequentially formed on the first insulating layer  107 . The second insulating layer  109  may be formed of, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, the like, or a combination thereof. The low-k dielectric materials may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric materials may have a dielectric constant less than 2.0. The fourth mask layer  807  may include a plurality of openings  807 C formed above the two capacitor top contacts  601 . The plurality of openings  807 C may define positions of the two capacitor structures  701  as will be fabricated later. 
     With reference to  FIG.  26   , an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the second insulating layer  109  and concurrently form a plurality of capacitor openings  927 . The top surface of the two capacitor top contacts  601  may be exposed through the plurality of capacitor openings  927 . A layer of second conductive material  929  may be formed in the plurality of capacitor openings  927  and on the top surface of the second insulating layer  109 . The second conductive material  929  may be, for example, doped polysilicon, metal silicide, copper, aluminum, or tungsten. 
     With reference to  FIG.  27   , a photoresist may be formed in the plurality of capacitor openings  927  to protect the layer of second conductive material  929  formed in the plurality of capacitor openings  927 . An etch process may be performed to remove the layer of second conductive material  929  formed on the top surface of the second insulating layer  109  and concurrently turn the layer of second conductive material  929  into two capacitor bottom electrodes  703 . After the etch process, the photoresist in the plurality of capacitor openings  927  may be removed. A capacitor dielectric layer  705  may be formed in the plurality of capacitor openings  927  and on the top surface of the second insulating layer  109 . In some embodiments, the capacitor dielectric layer  705  may be formed of a single layer including a high-k dielectric materials. The capacitor dielectric layer  705  may have a thickness between about 1 angstrom to about 100 angstroms. In some embodiments, the capacitor dielectric layer  705  may be formed of a stacked layer consisting of silicon oxide, silicon nitride, and silicon oxide. 
     With reference to  FIG.  28   , a capacitor top electrode  707  may be form on the capacitor dielectric layer  705  and completely fill the plurality of capacitor openings  927 . The capacitor top electrode  707  may be formed of doped polysilicon or metal. The capacitor bottom electrodes  703 , the capacitor dielectric layer  705 , and the capacitor top electrode  707  together form the capacitor structures  701 . 
     Due to the design of the semiconductor device of the present disclosure, the wider dimension of the upper portions  203  of the impurity regions  201 B,  201 C may provide an extra process tolerance for formation of contact thereon. As a result, the yield of fabrication of the semiconductor device may be improved. 
     Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof. 
     Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.