Patent Publication Number: US-RE43162-E

Title: Semiconductor memory module, electronic apparatus and method for operating thereof

Description:
TECHNICAL FIELD 
     The present invention relates to semiconductor memory modules and electronic apparatuses comprising a semiconductor memory module and more specifically to semiconductor memory modules consuming low power. 
     BACKGROUND 
     Computer systems typically have a processing unit and a memory system connected to it for storing data. The memory system includes a memory controller and one or more semiconductor memory modules. The processing unit is connected to the memory controller via a bus system and the memory controller is coupled to the semiconductor memory modules via a memory bus system. Each of the semiconductor memory modules comprises at least one register and a number of ranks of memory chips coupled to the register. The registers transmit command/address signals and chip select signals received from the memory controller to the ranks of memory chips. For selecting a specific rank of memory chips for a memory access, respective chip select signals are used to activate the respective rank. Typically, command/address inputs of memory chips of several ranks are coupled in parallel to one output of a single register. The register transmits command/address signals to the respective ranks of memory chips if at least one of the respective chip select signals is active. Therefore, command/address signals are transmitted unnecessarily to ranks of memory chips coupled to the register but not being addressed by a memory access. 
     Due to the capacitance of the memory chips and the lines coupling the memory chips with the register, power is consumed by the semiconductor memory module each time data signals are transmitted. Therefore, power is wasted during each memory access when transmitting command/address signals to a number of ranks of memory chips that are not addressed. 
     In addition, due to the increasing operating speed of the semiconductor memory modules, the power consumption further increases. 
     What is desired is a semiconductor memory module and an electronic apparatus comprising a memory module that consumes low power and a method of operating thereof. 
     SUMMARY OF THE INVENTION 
     One embodiment of the present invention provides a semiconductor memory module that includes a circuit substrate, a first, a second, a third and a fourth rank of memory chips each including a multiplicity of memory chips and each being disposed on the circuit substrate. The semiconductor memory module further includes a first register and a second register each disposed on the circuit substrate, wherein the first register and the second register each comprise a first input for receiving a respective chip select signal having one of an active and an inactive level, a second input for receiving a respective other chip select signal having one of an active and an inactive level, at least one third input for receiving command/address signals, a first output for transmitting the respective chip select signal to the memory chips of the first rank and the third rank, respectively, a second output for transmitting the respective other chip select signal to the memory chips of the second rank and the fourth rank, respectively, and at least one third output. 
     The at least one third output of the first register transmits the command/address signals to the memory chips of the first rank and to the memory chips of the second rank, if at least one of the chip select signal received at the first input of the first register and the other chip select signal received at the second input of the first register is active, and blocks a transmission/switching of the command/address signals to the memory chips of the first rank and to the memory chips of the second rank, if both the chip select signal received at the first input of the first register and the other chip select signal received at the second input of the first register are inactive. 
     The at least one third output of the second register transmits the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if at least one of the chip select signal received at the first input of the second register and the other chip select signal received at the second input of the second register is active, and blocks a transmission/switching of the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if both the chip select signal received at the first input of the second register and the other chip select signal received at the second input of the second register are inactive. 
     Another aspect of the present invention provides an electronic apparatus including a controller device, a bus system and at least one semiconductor memory module. The semiconductor memory module includes a circuit substrate, a first, a second, a third and a fourth rank of memory chips each including a multiplicity of memory chips and each being disposed on the circuit substrate. The semiconductor memory module further includes a first register and a second register each disposed on the circuit substrate, wherein the first register and the second register each include a first input coupled to the controller device for receiving a respective chip select signal having one of an active and an inactive level, a second input coupled to the controller device for receiving a respective other chip select signal having one of an active and an inactive level, at least one third input coupled to the controller device via the bus system for receiving command/address signals, a first output for transmitting the respective chip select signal to the memory chips of the first rank and the third rank, respectively, a second output for transmitting the respective other chip select signal to the memory chips of the second rank and the fourth rank, respectively, and at least one third output. 
     The at least one third output of the first register transmits the command/address signals to the memory chips of the first rank and to the memory chips of the second rank, if at least one of the chip select signal received at the first input of the first register and the other chip select signal received at the second input of the first register is active, and blocks a transmission/switching of the command/address signals to the memory chips of the first rank and to the memory chips of the second rank, if both the chip select signal received at the first input of the first register and the other chip select signal received at the second input of the first register are inactive. 
     The at least one third output of the second register transmits the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if at least one of the chip select signal received at the first input of the second register and the other chip select signal received at the second input of the second register is active, and blocks a transmission/switching of the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if both the chip select signal received at the first input of the second register and the other chip select signal received at the second input of the second register are inactive. 
     Another aspect of the present invention provides a method of operating a semiconductor memory module. The method includes providing a semiconductor memory module, wherein the semiconductor memory module includes a circuit substrate, a first, a second, a third and a fourth rank of memory chips, each including a multiplicity of memory chips and each being disposed on the circuit substrate. The semiconductor memory module further includes a first register and a second register each disposed on the circuit substrate, wherein the first register and the second register each include a first input for receiving a respective chip select signal having one of an active and an inactive level, a second input for receiving a respective other chip select signal having one of an active and an inactive level, at least one third input for receiving command/address signals, a first output for transmitting the respective chip select signal to the memory chips of the first rank and the third rank, respectively, a second output for transmitting the respective other chip select signal to the memory chips of the second rank and the fourth rank, respectively, and at least one third output. 
     The method further includes determining, if of one of the respective chip select signals and one of the respective other chip select signals is active, transmitting/switching the command/address signals to the memory chips of the first rank and to the memory chips of the second rank via the at least one third output of the first register, if at least one of the chip select signal received at the first input of the first register and the other chip select signal received at the second input of the first register is active, and blocking a transmission/switching of the command/address signals to the memory chips of the first rank and to the memory chips of the second rank, if both the chip select signal received at the first input of the first register and the other chip select signal received at the second input of the first register are inactive. 
     The method further includes transmitting/switching the command/address signals via the at least one third output of the second register to the memory chips of the third rank and to the memory chips of the fourth rank, if at least one of the chip select signal received at the first input of the second register and the other chip select signal received at the second input of the second register is active, and blocking a transmission/switching of the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if both the chip select signal received at the first input of the second register and the other chip select signal received at the second input of the second register are inactive. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which: 
         FIG. 1  depicts schematically a semiconductor memory module according to one embodiment of the present invention; 
         FIG. 2  depicts a plan view of the semiconductor memory module as depicted in  FIG. 1 ; 
         FIG. 3  depicts schematically an electronic apparatus according to one embodiment of the present invention; 
         FIG. 4  depicts schematically an electronic apparatus according to one embodiment of the present invention; and 
         FIG. 5  depicts schematically a cross-sectional view of the semiconductor memory module of the electronic apparatus depicted in  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
       FIG. 1  depicts schematically a semiconductor memory module  1  according to one embodiment of the present invention. The semiconductor memory module  1  comprises a circuit substrate  2  having a first surface S 1  and a second surface S 2 . The circuit substrate  2  is preferably a circuit board, e.g., a printed circuit board with conductive lines disposed thereon. 
     A first register  10 , a first rank  100  and a second rank  200  of memory chips  3  are disposed on the first surface S 1 . In  FIG. 1 , each of the first rank  100  and the second rank  200  of memory chips  3  includes nine memory chips  3 . However, the first rank  100  and the second rank  200  may each include eighteen memory chips  3 . Each of the first  100  and second  200  ranks of memory chips  3  comprises a multiplicity of memory chips  3 . In this embodiment, the memory chips  3  are stacked upon each other and more specifically, the memory chips  3  of the second rank  200  are stacked upon memory chips  3  of the first rank  100 . However, memory chips  3  of the first rank  100  and of the second rank  200  may be arranged in a single layer on the first surface S 1  of the circuit substrate  2 . 
     The first register  10  has a first input  11  for receiving a chip select signal CS 0 , a second input  12  for receiving a chip select signal CS 1 , at least one third input  13  for receiving command/address signals CA and a fourth input  17  for receiving a control signal CS GATE EN. The command/address signals CA may be transmitted by a bus system  60 . Furthermore, the first register has a first output  14 , a second output  15  and at least one third output  16 . Chip select inputs  101  of memory chips  3  of the first rank  100  are coupled in parallel to the first output  14  of the first register  10  for transmitting the chip select signal CS 0  from the first register  10  to the memory chips  3  of the first rank  100 . Chip select inputs  201  of the memory chips  3  of the second rank  200  are coupled in parallel to the second output  15  of the first register  10  for transmitting the chip select signal CS 1  from the first register  10  to the memory chips  3  of the second rank  200 . Command/address inputs  102 ,  202  of the memory chips  3  of the first rank  100  and of the second rank  200  are coupled in parallel to the at least one third output  16  of the first register  10  for transmitting/switching command/address signals CA from the first register  10  to the memory chips  3  of the first rank  100  and of the second rank  200 . In  FIG. 1 , a connection between the at least one third output  16  of the first register  10  with the memory chips  3  of the first rank  100  and with the memory chips  3  of the second rank  200  is illustrated by a single line for reasons of better clearness. However, the connection may be provided by a bus system. 
     A second register  20 , a third rank  300  and a fourth rank  400  of memory chips  3  are disposed on the second surface S 2 . In  FIG. 1 , each of the third rank  300  and the fourth rank  400  of memory chips  3  includes nine memory chips  3 . However, the third rank  300  and the fourth rank  400  may each include eighteen memory chips  3 . Each of the third  300  and fourth  400  ranks of memory chips  3  includes a multiplicity of memory chips  3 . In this embodiment, the memory chips  3  are stacked upon each other and more specifically, the memory chips  3  of the fourth rank  400  are stacked upon memory chips  3  of the third rank  300 . However, memory chips  3  of the third rank  300  and of the fourth rank  400  may be arranged in a single layer on the second surface S 2  of the circuit substrate  2 . 
     The second register  20  has a first input  21  for receiving a chip select signal CS 2 , a second input  22  for receiving a chip select signal CS 3 , at least one third input  23  for receiving command/address signals CA and a fourth input  27  for receiving a control signal CS GATE EN. Furthermore, the second register  20  has a first output  24 , a second output  25  and at least one third output  26 . Chip select inputs  301  of memory chips  3  of the third rank  300  are coupled in parallel to the first output  24  of the second register  20  for transmitting the chip select signal CS 2  from the second register  20  to the memory chips  3  of the third rank  300 . Chip select inputs  401  of memory chips  3  of the fourth rank  400  are coupled in parallel to the second output  25  of the second register  20  for transmitting the chip select signal CS 3  from the second register  20  to the memory chips  3  of the fourth rank  400 . Command/address inputs  302 ,  402  of the memory chips  3  of the third rank  300  and of the fourth rank  400  are coupled in parallel to the at least one third output  26  of the second register for transmitting/switching command/address signals to the memory chips  3  of the third rank  300  and of the fourth rank  400 . In  FIG. 1 , a connection between the at least one third output  26  of the second register  20  with the memory chips  3  of the third rank  300  and with the memory chips  3  of the fourth rank  400  is illustrated by a single line for reasons of better clearness. However, the connection may be provided by a bus system. 
     Preferably memory chips  3  are DRAM memory chips providing a dynamic random access. However, other memory chips such as SDRAM memory chips may be used. 
     A memory chip can be activated by applying an active chip select signal to the chip select input of the memory chip. To activate the memory chip, a value of 0 is sent to the chip select input of the memory chips. If a value of 1 is applied to the chip select input of the memory chip, the memory chip is inactive. The use of chip select signals allows selecting specific chips/ranks during a memory access for reading data from the memory chip or writing data to the memory chip. 
     The control signal CS GATE EN is coupled to the fourth input  17  of the first register  10  and to the fourth input  27  of the second register  20  in parallel and may be provided by a motherboard of a computer. 
     The control signal CS GATE EN has one of an active and an inactive level. The semiconductor memory module can be operated in a first mode relating to this signal being inactive and in a second mode relating to the control signal being active. 
     In the first mode of operation, an inactive level of the control signal CS GATE EN is applied to the fourth input  17  of the first register  10  and to the fourth input  27  of the second register  20 . The command/address signals CA applied to the at least one third input  13  of the first register  10  are transmitted via the at least one third output  16  of the first register  10  to the memory chips  3  of the first rank  100  and of the second rank  200 , and the command/address signals CA applied to the at least one third input  23  of the second register  20  are transmitted via the at least one third output  26  of the second register  20  to the memory chips  3  of the third rank  300  and of the fourth rank  400 . 
     In the second mode of operation, an active level of the control signal CS GATE EN is applied to the fourth input  17  of the first register  10 . The transmission of command/address signals CA applied to the at least one third input  13  to memory chips  3  via the at least one third output  16  is dependent on the level of the chip select signals CS 0  and CS 1 . If at least one of the chip select signals CS 0  and CS 1  is active, then the command/address signals CA are transmitted via the at least one third output  16  to the memory chips  3  of the first rank  100  and of the second rank  200 . If both chip select signals CS 0  and CS 1  are inactive, then the transmission of the command/address signals CA via the at least one third output  16  to the memory chips  3  of the first rank  100  and of the second rank  200  is blocked. 
     Furthermore, in the second mode of operation, an active level of the control signal CS GATE EN is applied to the fourth input  27  of the second register  20 . The transmission of command/address signals CA applied to the at least one third input  23  to memory chips  3  via the at least one third output  26  is dependent on the level of the chip select signals CS 2  and CS 3 . If at least one of the chip select signals CS 2  and CS 3  is active, then the command/address signals CA are transmitted via the at least one third output  26  to the memory chips  3  of the third rank  300  and of the fourth rank  400 . If both chip select signals CS 2  and CS 3  are inactive, then the transmission of the command/address signals CA via the at least one third output  26  to the memory chips  3  of the third rank  300  and of the fourth rank  400  is blocked. 
     Accordingly, in the second mode of operation, the respective at least one third output  16 ,  26  of each of the first  10  and second  20  registers drives the command/address signals CA only when the register  10 ,  20  receives a chip select signal that refers to a rank that is connected to the respective register  10 ,  20 . Therefore, the power consumed during a memory access in which only ranks connected to a single register are addressed, is reduced. This reduction of power consumption also reduces the heat generated in the semiconductor memory module  1  and, therefore, less cooling, e.g., provided by an air flow, of the semiconductor memory module is required. This advantageously reduces the cost of the semiconductor memory module and the maintenance costs. 
       FIG. 2  depicts a plan view of the semiconductor memory module  1  as depicted in  FIG. 1 . Memory chips  3  are mounted on a first surface S 1  of a circuit substrate  2 . In this embodiment, memory chips  3  are labeled U 1  to U 36 . Memory chips U 1  to U 36  are arranged in two levels. Memory chips U 1  to U 18  are mounted on the circuit substrate  2  and memory chips U 19  to U 36  are stacked upon memory chips U 1  to U 18 . By stacking the memory chips upon another, the density of memory chips on the circuit substrate  2  is increased. Memory chips U 1  to U 36  are grouped in ranks of memory chips. In this embodiment a first rank  100  comprises memory chips U 1  to U 18  and a second rank  200  of memory chips comprises memory chips U 19  to U 36 . However, other compositions of the first  100  and second ranks  200  are possible. It is also possible that U 1  to U 36  are thirty-six stacked chips, wherein U 1  to U 18  are placed on the first surface S 1  of the circuit substrate  2  and U 19  to U 36  are placed on a second surface (not shown in  FIG. 2 ) of the circuit substrate  2 . 
     An edge connector  8  having pins  9  is disposed at a long end of the circuit substrate  2 . The edge connector  8  provides a connection between the semiconductor memory module  1  and an external device such as a controller device by, for example, a bus system. One end of each of the pins  9  is coupled to register  10  by conductive lines (not shown) disposed on the circuit substrate  2  for the transmission of electrical signals. Another end of each of the pins  9  provides a connection to a socket of an external device. 
       FIG. 3  depicts schematically an electronic apparatus according to one embodiment of the present invention. The electronic apparatus includes a first semiconductor memory module  1 , a second semiconductor memory module  1 ′, a controller device  50  and a bus system  60 . 
     First  1  and second  1 ′ semiconductor memory modules are coupled to the controller device  50  via the bus system  60  for the transmission of electrical signals, e.g., command/address signals CA. First  1  and second  1 ′ semiconductor memory modules preferably include a connector such as an edge connector (not shown in  FIG. 3 ) for connecting to bus system  60 . Typically, the bus system  60  comprises sockets (not shown in  FIG. 3 ) in which first  1  and second  1 ′ semiconductor memory modules are plugged in. The bus system  60  may include a multiplicity of sockets for connecting a multiplicity of semiconductor memory modules to the controller device  50 . A bus termination  61  disposed at the end of the bus system  60  terminates the bus system  60 . 
     Each of the first  1  and second  1 ′ semiconductor memory modules includes a first register  10 ,  30 , a second register  20 ,  40 , a first  100 ,  500 , a second  200 ,  600 , a third  300 ,  700  and a fourth rank  400 ,  800  of memory chips (not shown in  FIG. 3 ). 
     Each of the first  10 ,  30  and second  20 ,  40  registers of the first  1  and second  1 ′ semiconductor memory modules have a first input  11 ,  21 ,  31 ,  41  coupled to the controller circuit  50  for receiving a respective chip select signal CS 0 , CS 2 , CS 4 , CS 6 , a second input  12 ,  22 ,  32 ,  42  coupled to the controller circuit  50  for receiving a respective other chip select signal CS 1 , CS 3 , CS 5 , CS 7  and at least one third input  13 ,  23 ,  33 ,  43  coupled to the controller circuit  50  for receiving command/address signals CA. 
     Each of the first  10 ,  30  and second  20 ,  40  registers of the first  1  and second  1 ′ semiconductor memory modules have a respective fourth input  17 ,  27 ,  37 ,  47  for receiving a control signal CS GATE EN. The control signal CS GATE EN is coupled to the fourth inputs  17 ,  27 ,  37 ,  47  in parallel and may be provided by a motherboard of a computer or may be wired on the semiconductor memory module  1  itself. 
     Furthermore, each of the first  10 ,  30  and second  20 ,  40  registers of the first  1  and second  1 ′ semiconductor memory modules have a first output  14 ,  24 ,  34 ,  44 , a second output  15 ,  25 ,  35 ,  45  and at least one third output  16 ,  26 ,  36 ,  46 . 
     Chip select inputs of memory chips (not shown in  FIG. 3 ) of the first rank  100  of the first semiconductor memory module  1  are coupled to the first output  14  of the first register  10  of the first semiconductor memory module  1  for the transmission of the chip select signal CS 0  to the memory chips (not shown in  FIG. 3 ) of the first rank  100  of the first semiconductor memory module  1 . 
     Chip select inputs of memory chips (not shown in  FIG. 3 ) of the second rank  200  of the first semiconductor memory module  1  are coupled to the second output  15  of the first register  10  of the first semiconductor memory module  1  for the transmission of the chip select signal CS 1  to the memory chips (not shown in  FIG. 3 ) of the second rank  200  of the first semiconductor memory module  1 . 
     Chip select inputs of memory chips (not shown in  FIG. 3 ) of the third rank  300  of the first semiconductor memory module  1  are coupled to the first output  24  of the second register  20  of the first semiconductor memory module  1  for the transmission of the chip select signal CS 2  to memory chips (not shown in  FIG. 3 ) of the third rank  300  of semiconductor the first memory module  1 . 
     Chip select inputs of memory chips (not shown in  FIG. 3 ) of the fourth rank  400  of the first semiconductor memory module  1  are coupled to the second output  25  of the second register  20  of the first semiconductor memory module  1  for the transmission of the chip select signal CS 3  to the memory chips (not shown in  FIG. 3 ) of the fourth rank  400  of first semiconductor memory module  1 . 
     Chip select inputs of memory chips (not shown in  FIG. 3 ) of the first rank  500  of the second semiconductor memory module  1 ′ are coupled to the first output  34  of the first register  30  of the second semiconductor memory module  1 ′ for the transmission of the chip select signal CS 4  to the memory chips (not shown in  FIG. 3 ) of the first rank  500  of the second semiconductor memory module  1 ′. 
     Chip select inputs of memory chips (not shown in  FIG. 3 ) of the second rank  600  of the second semiconductor memory module  1 ′ are coupled to the second output  35  of the first register  30  of the second semiconductor memory module  1 ′ for the transmission of the chip select signal CS 5  to the memory chips (not shown in  FIG. 3 ) of the second rank  600  of the second semiconductor memory module  1 ′. 
     Chip select inputs of memory chips (not shown in  FIG. 3 ) of the third rank  700  of the second semiconductor memory module  1 ′ are coupled to the first output  44  of the second register  40  of the second semiconductor memory module  1 ′ for the transmission of the chip select signal CS 6  to the memory chips (not shown in  FIG. 3 ) of the third rank  700  of the second semiconductor memory module  1 ′. 
     Chip select inputs of memory chips (not shown in  FIG. 3 ) of the fourth rank  800  of the second semiconductor memory module  1 ′ are coupled to the second output  45  of the second register  40  of the second semiconductor memory module  1 ′ for the transmission of the chip select signal CS 7  to the memory chips (not shown in  FIG. 3 ) of the fourth rank  800  of the second semiconductor memory module  1 ′. 
     Command/address inputs of memory chips (not shown in  FIG. 3 ) of the first rank  100  and of the second rank  200  of the first semiconductor memory module  1  are coupled in parallel to the at least one third output  16  of the first register  10  of the first semiconductor memory module  1  for the transmission of command/address signals to the memory chips (not shown in  FIG. 3 ) of the first rank  100  and of the second rank  200  of the first semiconductor memory module  1 . 
     Command/address inputs of memory chips (not shown in  FIG. 3 ) of the third rank  300  and of the fourth rank  400  of the first semiconductor memory module  1  are coupled in parallel to the at least one third output  26  of the second register  20  of the first semiconductor memory module  1  for the transmission of command/address signals to the memory chips (not shown in  FIG. 3 ) of the third rank  300  and of the fourth rank  400  of the first semiconductor memory module  1 . 
     Command/address inputs of memory chips (not shown in  FIG. 3 ) of the first rank  500  and of the second rank  600  of the second semiconductor memory module  1 ′ are coupled in parallel to the at least one third output  36  of the first register  30  of the second semiconductor memory module  1 ′ for the transmission of command/address signals to the memory chips (not shown in  FIG. 3 ) of the first rank  500  and of the second rank  600  of the second semiconductor memory module  1 ′. 
     Command/address inputs of memory chips (not shown in  FIG. 3 ) of the third rank  700  and of the fourth rank  800  of the second semiconductor memory module  1 ′ are coupled in parallel to the at least one third output  46  of the second register  40  of the second semiconductor memory module  1 ′ for the transmission of command/address signals to the memory chips (not shown in  FIG. 3 ) of the third rank  700  and of the fourth rank  800  of the second semiconductor memory module  1 ′. 
     If an inactive level of the control signal CS GATE EN is applied to each of the fourth inputs  17 ,  27 ,  37 ,  47  of the respective first  10 ,  30  and second  20 ,  40  registers of the respective first  1  and second  1 ′ semiconductor memory modules, then the command/address signals CA applied to the at least one third input  13  of the first register  10  of the first semiconductor memory module  1  are transmitted via the at least one third output  16  of the first register  10  of the first semiconductor memory module  1  to the memory chips  3  of the first rank  100  and of the second rank  200  of the first semiconductor memory module  1 , the command/address signals CA applied to the at least one third input  23  of the second register  20  of the first semiconductor memory module  1  are transmitted via the at least one third output  26  of the second register  20  of the first semiconductor memory module  1  to the memory chips  3  of the third rank  300  and of the fourth rank  400  of the first semiconductor memory module  1 , the command/address signals CA applied to the at least one third input  33  of the first register  30  of the second semiconductor memory module  1 ′ are transmitted via the at least one third output  36  of the first register  30  of the second semiconductor memory module  1 ′ to the memory chips  3  of the first rank  500  and of the second rank  600  of the second semiconductor memory module  1 ′, the command/address signals CA applied to the at least one third input  43  of the second register  40  of the second semiconductor memory module  1 ′ are transmitted via the at least one third output  46  of the second register  40  of the second semiconductor memory module  1 ′ to the memory chips  3  of the third rank  700  and of the fourth rank  800  of the second semiconductor memory module  1 ′. 
     If an active level of the control signal CS GATE EN is applied to each of the fourth input  17 ,  27 ,  37 ,  47  of the respective first  10 ,  30  and second  20 ,  40  registers of the respective first  1  and second  1 ′ semiconductor memory modules, then the transmission of command/address signals CA applied to respective at least one third inputs  13 ,  23 ,  33 ,  43  is dependent on the respective chip select signals CS 0  to CS 7 . 
     If at least one of the chip select signals CS 0  and CS 1  coupled respectively to the first input  11  and the second input  12  of the first register  10  of the first semiconductor memory module  1  is active, then the command/address signals CA are transmitted via the at least one third output  16  to the memory chips  3  of the first rank  100  and of the second rank  200  of the first semiconductor memory module  1 . If both chip select signals CS 0  and CS 1  are inactive, then the transmission of command/address signals CA via the at least one third output  16  to the memory chips  3  of the first rank  100  and of the second rank  200  is blocked. 
     If at least one of the chip select signals CS 2  and CS 3  coupled respectively to the first input  21  and the second input  22  of the second register  20  of the first semiconductor memory module  1  is active, then the command/address signals CA are transmitted via the at least one third output  26  to the memory chips  3  of the third rank  300  and of the fourth rank  400  of the first semiconductor memory module  1 . If both chip select signals CS 2  and CS 3  are inactive, then the transmission of command/address signals CA via the at least one third output  26  to the memory chips  3  of the third rank  300  and of the fourth rank  400  is blocked. 
     If at least one of the chip select signals CS 4  and CS 5  coupled respectively to the first input  31  and the second input  32  of the first register  30  of the second semiconductor memory module  1 ′ is active, then the command/address signals CA are transmitted via the at least one third output  36  to the memory chips  3  of the first rank  500  and of the second rank  600  of the second semiconductor memory module  1 ′. If both chip select signals CS 4  and CS 5  are inactive, then the transmission of command/address signals CA via the at least one third output  36  to the memory chips  3  of the first rank  500  and of the second rank  600  is blocked. 
     If at least one of the chip select signals CS 6  and CS 7  coupled to the respective first input  41  and the second input  42  of the second register  40  of the second semiconductor memory module  1 ′ is active, then the command/address signals CA are transmitted via the at least one third output  46  to the memory chips  3  of the third rank  700  and of the fourth rank  800  of the second semiconductor memory module  1 ′. If both chip select signals CS 6  and CS 7  are inactive, then the transmission of command/address signals CA via the at least one third output  46  to the memory chips  3  of the third rank  700  and of the fourth rank  800  is blocked. 
       FIG. 4  depicts schematically an electronic apparatus according to one embodiment of the invention. The electronic apparatus includes a semiconductor memory module  1 , a bus system  60  and a controller device  50  such as a memory controller. 
     The semiconductor memory module  1  includes a first  100 , a second  200 , a third  300 , a fourth  400 , a fifth  500 , a sixth  600 , a seventh  700  and an eighth  800  rank of memory chips disposed. Furthermore, the semiconductor memory module  1  includes a first  10 , a second  20 , a third  30  and a fourth  40  register. 
     Each of the first  10 , second  20 , third  30  and fourth  40  register has a respective first input  11 ,  21 ,  31 ,  41  coupled to the controller device  50  for receiving a respective chip select signal CS 0 , CS 2 , CS 4 , CS 6 , CS 8 , a respective second input  12 ,  22 ,  32 ,  42  coupled to the controller device  50  for receiving another respective chip select signal CS 1 , CS 3 , CS 5 , CS 7 , and at least one third input  13 ,  23 ,  33 ,  43  coupled to the controller device  50  for receiving command/address signals CA. 
     Each of the first  10 , second  20 , third  30  and fourth  40  register has a respective fourth input  17 ,  27 ,  37 ,  47  for receiving a control signal CS GATE EN, wherein the control signal CS GATE EN is coupled to the fourth inputs  17 ,  27 ,  37  and  47  in parallel. 
     Furthermore, each of the first  10 , second  20 , third  30  and fourth  40  register has a respective first output  14 ,  24 ,  34 ,  44 , a respective second output  15 ,  25 ,  35 ,  45  and at least one respective third output  16 ,  26 ,  36 ,  46 . Chip select inputs of memory chips (not shown in  FIG. 4 ) of the first rank  100  are coupled to the first output  14  of the first register  10  for the transmission of the chip select signal CS 0 , chip select inputs of the memory chips (not shown in  FIG. 4 ) of the second rank  200  are coupled to the second output  15  of the first register  10  for the transmission of the chip select signal CS 1 , chip select inputs of the memory chips of the third rank  300  are coupled to the first output  24  of the second register  20  for the transmission of the chip select signal CS 2 , chip select inputs of the memory chips (not shown in  FIG. 4 ) of the fourth rank  400  are coupled to the second output  25  of the second register  20  for the transmission of the chip select signal CS 3 , chip select inputs of the memory chips (not shown in  FIG. 4 ) of the fifth rank  500  are coupled to the first output  34  of the third register  30  for the transmission of the chip select signal CS 4 , chip select inputs of the memory chips (not shown in  FIG. 4 ) of the sixth rank  600  are coupled to the second output  35  of the third register  30  for the transmission of the chip select signal CS 5 , chip select inputs of the memory chips (not shown in  FIG. 4 ) of the seventh rank  700  are coupled to the first output  44  of the fourth register  40  for the transmission of the chip select signal CS 6 , and chip select inputs of the memory chips (not shown in  FIG. 4 ) of the eighth rank  800  are coupled to the second output  45  of the fourth register  40  for the transmission of the chip select signal CS 7 . 
     Command/address inputs of memory chips (not shown in  FIG. 4 ) of the first rank  100  and of the second rank  200  are coupled in parallel to the at least one third output  16  of the first register  10  for the transmission of command/address signals to the memory chips (not shown in  FIG. 4 ) of the first rank  100  and of the second rank  200 . 
     Command/address inputs of memory chips (not shown in  FIG. 4 ) of the third rank  300  and of the fourth rank  400  are coupled in parallel to the at least one third output  26  of the second register  20  for the transmission of command/address signals to the memory chips (not shown in  FIG. 4 ) of the third rank  300  and of the fourth rank  400 . 
     Command/address inputs of memory chips (not shown in  FIG. 4 ) of the first rank  500  and of the second rank  600  are coupled in parallel to the at least one third output  36  of the third register  30  for the transmission of command/address signals to the memory chips (not shown in  FIG. 4 ) of the fifth rank  500  and of the sixth rank  600 . 
     Command/address inputs of memory chips (not shown in  FIG. 4 ) of the seventh rank  700  and of the eighth rank  800  are coupled in parallel to the at least one third output  46  of the fourth register  40  for the transmission of command/address signals to the memory chips (not shown in  FIG. 4 ) of the seventh rank  700  and of the eighth rank  800 . 
     If an inactive level of the control signal CS GATE EN is applied to each of the fourth inputs  17 ,  27 ,  37 ,  47  of the respective first  10 , second  20 , third  30 , fourth  40 , fifth  50 , sixth  60 , seventh  70  and eighth  80  registers, then the command/address signals CA applied to the at least one third input  13  of the first register  10  are transmitted via the at least one third output  16  of the first register  10  to the memory chips  3  of the first rank  100  and of the second rank  200 , the command/address signals CA applied to the at least one third input  23  of the second register  20  are transmitted via the at least one third output  26  of the second register  20  to the memory chips  3  of the third rank  300  and of the fourth rank  400 , the command/address signals CA applied to the at least one third input  33  of the third register  30  are transmitted via the at least one third output  36  of the third register  30  to the memory chips  3  of the fifth rank  500  and of the sixth rank  600 , the command/address signals CA applied to the at least one third input  43  of the fourth register  40  are transmitted via the at least one third output  46  of the fourth register  40  to the memory chips  3  of the seventh rank  700  and of the eighth rank  800 . 
     If an active level of the control signal CS GATE EN is applied to each of the fourth input  17 ,  27 ,  37 ,  47  of the respective first  10 , second  20 , third  30 , fourth  40 , fifth  50 , sixth  60 , seventh  70  and eighth  80  registers, then the transmission of command/address signals CA applied to respective at least one third inputs  13 ,  23 ,  33 ,  43  is dependent on the respective chip select signals CS 0  to CS 7 . 
     If at least one of the chip select signals CS 0  and CS 1  coupled respectively to the first input  11  and the second input  12  of the first register  10  is active, then the command/address signals CA are transmitted via the at least one third output  16  to the memory chips  3  of the first rank  100  and of the second rank  200 . If both chip select signals CS 0  and CS 1  are inactive, then the transmission of command/address signals CA via the at least one third output  16  to the memory chips  3  of the first rank  100  and of the second rank  200  is blocked. 
     If at least one of the chip select signals CS 2  and CS 3  coupled respectively to the first input  21  and the second input  22  of the second register  20  is active, then the command/address signals CA are transmitted via the at least one third output  26  to the memory chips  3  of the third rank  300  and of the fourth rank  400 . If both chip select signals CS 2  and CS 3  are inactive, then the transmission of command/address signals CA via the at least one third output  26  to the memory chips  3  of the third rank  300  and of the fourth rank  400  is blocked. 
     If at least one of the chip select signals CS 4  and CS 5  coupled respectively to the first input  31  and the second input  32  of the third register  30  is active, then the command/address signals CA are transmitted via the at least one third output  36  to the memory chips  3  of the fifth rank  500  and of the sixth rank  600 . If both chip select signals CS 4  and CS 5  are inactive, then the transmission of command/address signals CA via the at least one third output  36  to the memory chips  3  of the fifth rank  500  and of the sixth rank  600  is blocked. 
     If at least one of the chip select signals CS 6  and CS 7  coupled to the respective first input  41  and the second input  42  of the fourth register  40  is active, then the command/address signals CA are transmitted via the at least one third output  46  to the memory chips  3  of the seventh rank  700  and of the eighth rank  800 . If both chip select signals CS 6  and CS 7  are inactive, then the transmission of command/address signals CA via the at least one third output  46  to the memory chips  3  of the seventh rank  700  and of the eighth rank  800  is blocked. 
       FIG. 5  depicts schematically a cross-sectional view of the semiconductor memory module  1  of the electronic apparatus of  FIG. 4 . The semiconductor memory module  1  includes a first circuit substrate  2  and a second circuit substrate  2 ′, each having a first surface S 1 , S 1 ′ and a second surface S 2 , S 2 ′. 
     A first register  10  is disposed on the first surface S 1  of the first circuit substrate  2 , a second register  20  is disposed on the second surface S 2  of the first circuit substrate  2 , a third register  30  is disposed on the first surface S 1 ′ of the second circuit substrate  2 ′ and a fourth register  40  is disposed on the second surface S 2 ′ of the second circuit substrate  2 ′. 
     A respective first rank  100 ,  500  and a respective second rank  200 ,  600  of memory chips (not shown in  FIG. 5 ) are disposed on the respective first surface S 1 , S 1 ′ of the respective circuit substrate  2 ,  2 ′. 
     A respective third rank  300 ,  700  and a respective fourth rank  400 ,  800  of memory chips (not shown in  FIG. 5 ) are disposed on the respective second surface S 2 , S 2 ′ of the respective circuit substrate  2 ,  2 ′. 
     Typically, memory chips (not shown in  FIG. 5 ) are coupled to respective circuit substrates by solder balls  80  to provide an electrical connection between the memory chips and the circuit substrates. 
     A connector  70  provides a connection between the first circuit substrate  2  and the second circuit substrate  2 ′ for the transmission of electrical signals. The connector  70  includes a plug  70 B disposed on the first surface S 1 ′ of the second circuit substrate  2 ′ and a socket  70 A disposed on the second surface S 2  of the first circuit substrate  2 . 
     An edge connector  8  disposed on one end of the first circuit substrate  2  provides electrical connection between the electronic apparatus and a bus system (not shown in  FIG. 5 ) for the transmission of electrical signals between an external device such as the controller device depicted in  FIG. 4  and the electronic apparatus via a bus system.