Patent Publication Number: US-9904751-B2

Title: Computer-implemented method of designing a modularized stacked integrated circuit

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 61/102,209, filed on Jan. 12, 2015, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a physical design of integrated circuits, and in particular to a physical design of 2.5-dimensional (2.5D) and/or three-dimensional (3D) integrated circuits. 
     Description of the Related Art 
     A 2.5-dimensional integrated circuit (2.5D IC) is a package with an active electronic component (e.g. a die or a chip) stacked on an interposer through conductive bumps. A three-dimensional integrated circuit (3D IC) is a package with a plurality of active electronic components stacked vertically through the use of through-silicon vias (TSVs) to form a single integrated circuit. The stacked die may be then packaged such that I/Os can provide connection to the 3D IC. 
     A 2.5D IC and/or 3D IC provides a solution for multi-functional, highest-margin, highest-volume designs with faster speeds. However, a 2.5D IC and/or 3D IC also faces challenges including complex designs of each active electronic component. Also, the integration of the stacked active electronic components or the integration of the active electronic component and the interposer generates design challenges. Conventional solutions implement the active electronic components (e.g. dies or chips), the interposer, and the TSVs separately. An assembly of the active electronic components, interposer, and TSVs is then fabricated to do physical verifications. In the interposer, however, the huge amount of digital, analog, and DDR connections makes it so that routings cannot be completed as automatic chip-level routings or manual substrate routings. Mismatched in the resulting 2.5D IC and/or 3D IC designs may occur, especially in the physical connections and the electrical connections between the active electronic component and the interposer. 
     Thus, a novel physical design of 2.5D IC and/or 3D IC is desirable. 
     BRIEF SUMMARY OF THE INVENTION 
     A method of designing an integrated circuit is provided. An exemplary embodiment of a method of designing an integrated circuit includes providing a physical layout group including a first layout corresponding to a first die having a first function. A second layout corresponds to an interposer configured for the first die connected thereon. The first physical layout group is partitioned into a first physical layout partition according to the first function. A first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. A first verification is performed on the first hierarchical layout. 
     Another exemplary embodiment of a method of designing an integrated circuit includes a lead frame including obtaining a first netlist corresponding to a first die. A second netlist corresponding to an interposer provided for the first die connected thereon is obtained. The first netlist is partitioned into a third netlist according to a first function. The second netlist is partitioned into a fourth netlist according to the first function. A first automatic place-and-route (APR) process according to the third netlist and the fourth netlist is performed to obtain a first hierarchical netlist. A first hierarchical netlist is verified. 
     Yet another exemplary embodiment of a method of designing an integrated circuit includes a lead frame including obtaining a first netlist corresponding to a first die having a first function and a second function. A second netlist corresponding to an interposer provided for the first die connected thereon is obtained. A third netlist is obtained by partitioning the first netlist and the second netlist according to the first function. A fourth netlist is obtained by partitioning the first netlist and the second netlist according to the second function. A first automatic place-and-route (APR) process according to the third netlist is performed to obtain a first hierarchical netlist. A second automatic place-and-route (APR) process according to the fourth netlist is performed to obtain a second hierarchical netlist. The first hierarchical netlist and the second hierarchical netlist are merged to obtain a merged hierarchical netlist. The merged hierarchical netlist is verified. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a cross-sectional view of a stacked integrated circuit in accordance with some embodiments of the disclosure. 
         FIGS. 2A and 2B  are enlarged views of  FIG. 1 , showing a 2.5D stacked integrated circuit module with a first function in accordance with some embodiments of the disclosure. 
         FIGS. 2C and 2D  are enlarge view of  FIG. 1 , showing a 3D stacked integrated circuit module with a second function in accordance with some embodiments of the disclosure. 
         FIGS. 3-5  are flowcharts illustrating a method of designing an integrated circuit in accordance with some embodiments of the disclosure. 
         FIG. 6  is a diagram illustrating the methods of designing an integrated circuit in accordance with some embodiments of  FIGS. 3-5 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is determined by reference to the appended claims. 
     The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention. 
     Embodiments provide a modularized stacked physical design framework for a stacked integrated circuit. The stacked integrated circuit may comprise a 2.5-dimensional (2.5D) and/or three-dimensional (3D) integrated circuit including at least one die mounted on an interposer. A module design can cut off to include a part of the interposer and corresponding through silicon vias (TSVs) to form a 2.5-dimensional (2.5D)/three-dimensional (3D) layout module to do independent implementation according to a designed function. 
       FIG. 1  is a cross-sectional view of a stacked integrated circuit  500  in accordance with some embodiments of the disclosure. The stacked integrated circuit  500  comprises an interposer  200  and a first die  300 . In some embodiments, the first die  300  comprises a single die, such as a system on chip (SoC) die. The interposer  200  is provided for the first die  300  to be disposed thereon using a flip-chip technology or through silicon via (TSV) technology. The stacked integrated circuit  500  further comprises a second die  400  disposed on the interposer  200  and beside to the interposer  200 . In some embodiments, the second die  400  comprises a memory die, for example, a SRAM die. The second die  400  may comprise a three-dimensional (3D) integrated circuit die. The second die  400  may comprise vertically stacked dies, for example, stacked dies  400   a ,  400   b  and  400   c . The die  400   a  is vertically stacked on the die  400   b , and the die  400   b  is vertically stacked on the die  400   c . The dies  400   a ,  400   b  and  400   c  may be individually disposed using a flip-chip technology or through silicon via (TSV) technology. 
     As shown in  FIG. 1 , the stacked integrated circuit  500  may comprise a 2.5D stacked integrated circuit module  350  (comprising a 2.5D stacked integrated circuit module  350   a  as shown in  FIG. 2A  and a 2.5D stacked integrated circuit module  350   b  as shown in  FIG. 2B ) and a 3D stacked integrated circuit module  450  (comprising a 3D stacked integrated circuit module  450   a  as shown in  FIG. 2C  and a 3D stacked integrated circuit module  350   b  as shown in  FIG. 2D ) with different functions. In some embodiments, the 2.5D stacked integrated circuit module  350  may be composed of a portion of the first die  300  and a corresponding portion of the interposer  200  having a first function, for example, a digital function, an analog function, a mixed-signal function or a radio-frequency (RF) function. The 3D stacked integrated circuit module  450  may be composed of a portion of the first die  300  and a corresponding portion of the interposer  200  having a second function that is different from the first function. The second function may comprise a memory function. 
       FIG. 2A  is an enlarge view of  FIG. 1 , showing the 2.5D stacked integrated circuit module  350   a  with the first function in accordance with some embodiments of the disclosure. As shown in  FIG. 2A , the 2.5D stacked integrated circuit module  350  may comprise a portion of the first die  300  and a corresponding portion of the interposer  200  having the same function. In this embodiment, the first die  300  is disposed on the interposer  200  using the flip-chip technology. The first die  300  is coupled to the corresponding portion of the interposer  200  through conductive bumps  304  on redistribution patterns  324 . The first die  300  comprises a semiconductor substrate  302 . At least one integrated circuit device  320  is formed on an active region  301  of the semiconductor substrate  300 . The integrated circuit device  320  may comprise active devices and passive devices, for example, transistors, diodes, bipolar junction diodes (BJTs), resistors, capacitors, inductors or a combination thereof. As shown in  FIG. 2A , the integrated circuit device  320  may be isolated from the other devices (not shown) by isolation features (for example, shallow trench isolation (STI) features)  305  formed in the semiconductor substrate  200 . Also, the active region  301  is defined by the isolation features  305 . Interconnect structures  322  may be formed on the semiconductor substrate  200 , in a dielectric layer laminating structure  308 . In some embodiments, the interconnect structures  322  are electrically connected the integrated circuit device  320 . In some embodiments, the interconnect structures  322  may be constructed by contacts, vias and metal layer patterns, and the metal layer patterns are disposed vertically between the contacts and via and/or vias in different layer levels. The number of metal layer patterns is defined by the design of the integrated circuit device  320 , and the scope of the invention is not limited thereto. The redistribution patterns  324  are formed on the dielectric layer laminating structure  308 , connecting terminals of the interconnect structures  322 , which is away from the semiconductor substrate  302 . Also, a solder mask layer  332  is formed covering the dielectric layer laminating structure  308 . The conductive bumps  304  are formed through the solder mask layer  332  to connect to the redistribution patterns  324 . 
     As shown in  FIG. 2A , the corresponding portion of the interposer  200  of the 2.5D stacked integrated circuit module  350  may comprise a resin-based core substrate  201  formed by laminated bismaleimide triazine (BT). Interconnect structures  206   a  may be formed on a surface the resin-based core substrate  201  close to the first die  300 . The interconnect structures  206   a  may be formed in a dielectric layer laminating structure  203 . A plurality of through silicon vias (TSVs)  202   a  are formed vertically to pass through the resin-based core substrate  201 . Conductive bumps  204   a  are formed on another surface of the resin-based core substrate  201  away from to the first die  300 . Each of the TSVs  202   a  may have two terminals respectively connected to the corresponding interconnect structure  206   a  and the corresponding conductive bumps  204   a . In some embodiments, each of the interconnect structures  206   a  may have two terminals respectively connect the corresponding conductive bump  304   a  of the first die  300  and the corresponding TSV  202   a.    
       FIG. 2B  is an enlarge view of  FIG. 1 , showing the 2.5D stacked integrated circuit module  350   b  with the first function in accordance with some embodiments of the disclosure. Elements of the embodiments hereinafter, that are similar to those previously described with reference to  FIGS. 1 and 2A , are not repeated for brevity. One of the differences between the 2.5D stacked integrated circuit modules  350   a  and  350   b  is that the first die  300  of the 2.5D stacked integrated circuit module  350   b  is disposed on the interposer  200  using the TSV technology. In this embodiment, the first die  300  is coupled to the corresponding portion of the interposer  200  through a through silicon via (TSV)  326  and the corresponding conductive bumps  304 . The TSV  326  is formed passing through the semiconductor substrate  302 . 
       FIG. 2C  is an enlarge view of  FIG. 1 , showing the 3D stacked integrated circuit module  450   a  with a second function, in accordance with some embodiments of the disclosure. Elements of the embodiments hereinafter, that are similar to those previously described with reference to  FIGS. 1, 2A and 2B , are not repeated for brevity. As shown in  FIG. 2C , the 3D stacked integrated circuit module  450   a  may comprise a portion of the second die  400  and another corresponding portion of the interposer  200  having the same function. The second die  400  is coupled to the corresponding portion of the interposer  200  through conductive bumps  404   c . The second die  400  is a 3D integrated circuit, for example, a memory die. The second die  400  may comprises dies  400   a ,  400   b  and  400   c . The die  400   a  is vertically stacked on the die  400   b , and the die  400   b  is vertically stacked on the die  400   c  using the flip-chip technology and the TSV technology. Similarly, the die  400   a / 400   b / 400   c  comprises a semiconductor substrate  402   a / 402   b / 402   c  including an active region  401   a / 401   b / 401   c  defined by the isolation features  405   a / 405   b / 405   c . At least one of the integrated circuit devices  420   a / 420   b / 420   c  is formed on the semiconductor substrate  402   a / 402   b / 402   c , in a dielectric layer laminating structure  408   a / 408   b / 408   c . Redistribution patterns  424   a / 424   b / 424   c  are formed on the dielectric layer laminating structure  408   a / 408   b / 408   c , connecting terminals of the interconnect structures  422   a / 422   b / 422   c , which is away from the semiconductor substrate  402   a / 402   b / 402   c . A solder mask layer  432   a / 432   b / 432   c  is formed covering the dielectric layer laminating structure  408   a / 408   b / 408   c . Conductive bumps  404   a / 404   b / 404   c  are formed through the solder mask layer  432   a / 432   b / 432   c  to connect to the redistribution patterns  424   a / 424   b / 424   c . Through silicon vias (TSVs)  426 / 248  are formed passing through the semiconductor substrate  402   b / 402   c  of the die  400   b / 400   c.    
     In this embodiment, the die  400   a  is coupled to the die  400   b  through the conductive bumps  404   a  on the redistribution patterns  424   a  of the die  400   a  and the corresponding TSVs  426 . The die  400   b  is coupled to the die  400   c  through the conductive bumps  404   b  on the redistribution patterns  424   b  of the die  400   b  and the corresponding TSVs  428 . The die  400   c  is coupled to the corresponding portion of the interposer  200  of the 3D stacked integrated circuit module  450   a  through conductive bumps  404   c  on redistribution patterns  424   c.    
     As shown in  FIG. 2C , the corresponding portion of the interposer  200  of the 3D stacked integrated circuit module  450   a  may comprise interconnect structures  206   b  formed on a surface the resin-based core substrate  201  close to the second die  400 . The interconnect structures  206   b  may be formed in a dielectric layer laminating structure  203 . Through silicon vias (TSVs)  202   b  are formed vertically pass through the resin-based core substrate  201 . Conductive bumps  204   b  are formed on another surface of the resin-based core substrate  201  away from to the first die  300 . Each of the TSV  202   b  may have two terminals respectively connect the corresponding interconnect structure  206   b  and the corresponding conductive bump  204   b . In some embodiments, each of the interconnect structures  206   b  may have two terminals respectively connecting the corresponding conductive bump  304   b  of the die  400   c  of the second die  400  and the corresponding TSV  202   b . It should be noted that the first die  300 , the second die  400  and the interposer  200  are exemplary only and not intended to be limiting in any manner, additional elements/layers may be present and/or omitted. 
       FIG. 2D  is an enlarge view of  FIG. 1 , showing the 3D stacked integrated circuit module  450   b  with the first function in accordance with some embodiments of the disclosure. Elements of the embodiments hereinafter, that are similar to those previously described with reference to  FIGS. 1 and 2A-2C , are not repeated for brevity. One of the differences between the 3D stacked integrated circuit modules  450   a  and  450   b  is that the dies  400   a - 400   c  of the 3D stacked integrated circuit module  450   b  are disposed on the interposer  200  using the TSV technology. In this embodiment, the die  400   a  is coupled to the die  400   b  through a TSV  416  and the conductive bumps  404   a  of the die  400   a  and the corresponding redistribution patterns  424   b  of the die  400   b . The die  400   b  is coupled to the die  400   c  through the TSVs  426  and the corresponding conductive bumps  404   b  of the die  400   b  and the corresponding redistribution patterns  424   c  of the die  400   c . Also, the die  400   c  is coupled to the corresponding portion of the interposer  200  of the 3D stacked integrated circuit module  450   b  die  400   c  is coupled to the corresponding portion of the interposer  200  of the 3D stacked integrated circuit module  450  through the TSVs  428  of the die  400   c . The TSV  416  is formed passing through the semiconductor substrate  402   a . Solder mask layers  432   a / 432   b / 432   c  are formed covering the dielectric layer laminating structure  408   a / 408   b / 408   c  and bottom surfaces of the semiconductor substrate  402   a / 402   b / 402   c.    
     In some embodiments, the first die  300  and the second die  400  may each be represented by several netlists. The netlists can be converted into corresponding physical layouts (also called “layouts”) using tools (such as CAD tools). The layouts may include definitions and placements of device features (e.g., transistors including gates, doped regions), isolation features, interconnect structures (including metal layer patterns, vias and contacts), redistribution patterns, solder mask layers, conductive bumps, and/or other physical elements that will be formed on a semiconductor substrate of the first die  300  and the second die  400  as shown in  FIGS. 1, 2A and 2B . The layouts of the first die  300  and the second die  400  may include a plurality of “layers” corresponding to each of a plurality of “physical layers” to be fabricated on a semiconductor substrate to form integrated circuits. A typical format for the layout is a GDS II file, however other formats are possible. 
     Similarly, the interposer  200  may be represented by several netlists. The layouts converted by the netlists may include definitions and placements of the interconnect structures the, TSVs and the conductive bumps of the interposer  200  as shown in  FIGS. 1, 2A and 2B . 
       FIGS. 3-5  are flowcharts illustrating methods  300 ,  400  and  500  of designing an integrated circuit in accordance with some embodiments of the disclosure. The methods  300 ,  400  and  500  are implemented and performed using a computer and illustrated as a physical layout on a display.  FIG. 6  is a diagram illustrating the methods  300 ,  400  and  500  of designing an integrated circuit in accordance with some embodiments of  FIGS. 3-5 .  FIG. 6  is performed using a computer and illustrated as a physical layout on a display. In some embodiments, the integrated circuit includes a stacked integrated circuit  500 , for example, a 2.5D/3D integrated circuit as shown in  FIG. 1 . 
     As shown in  FIG. 3 , the method  300  begins at step S 302  where a physical layout group is provided. As shown in  FIG. 6 , the physical layout group may comprise a first layout sub-group  300 L and a third layout sub-group  200 L. The first layout sub-group  300 L corresponds to layouts of the first die  300 , and the third layout sub-group  200 L corresponds to layouts of the interposer  200  as shown in  FIG. 1 . In some embodiments, the first layout sub-group  300 L may comprise several layouts, for example, layout  300 L-1 st , layout  300 L-2 nd , layout  300 L-3 rd , . . . to layout  300 L-N th , where N is an any positive number. The third layout sub-group  200 L may comprise several layouts, for example, layout  200 L-1 st , layout  200 L-2 nd , layout  200 L-3 rd , . . . to layout  200 L-L th , where L is an any positive number. As mentioned before, the layouts  300 L-1 st  to  300 L-N th  include definitions and placements of device features (e.g., transistors including gates, doped regions), isolation features, interconnect structures (including metal layer patterns, vias and contacts), redistribution patterns, solder mask layers, conductive bumps, and/or other physical elements that correspond to the first die  300  as shown in  FIG. 1 . Also, the layouts  200 L-1 st  to  200 L-L th  include the definitions and placements of the interconnect structures, the TSVs and the conductive bumps of the interposer  200 , which is configured to provide the first die  300  mounted thereon, as shown in  FIG. 1 . It should be noted that the first layout sub-group  300 L corresponding to layouts of the first die  300  and the third layout sub-group  200 L corresponding to layouts of the interposer  200  are planned in the same phase. 
     In some other embodiments as shown in  FIG. 6 , the physical layout group may further comprise a second layout sub-group  400 L. The second layout sub-group  400 L corresponds the layouts of to the second die  400  as shown in  FIG. 1 . The second layout sub-group  400 L may comprise several layouts, for example, layout  400 L-1 st , layout  400 L-2 nd , layout  400 L-3 rd , . . . to layout  400 L-M th , where M is an any positive number. The layouts  400 L-1 st  to  400 L-M th  include definitions and placements of device features (e.g., transistors including gates, doped regions), isolation features, interconnect structures (including metal layer patterns, vias and contacts), redistribution patterns, solder mask layers, conductive bumps, and/or other physical elements corresponding to the second die  400  as shown in  FIG. 1 . Also, the layouts  200 L-1 st  to  200 L-L th  include definitions and placements of the interconnect structures, the TSVs and the conductive bumps of the interposer  200 , which is configured to provide the second die  400  mounted thereon, as shown in  FIG. 1 . It should be noted that the first layout sub-group  300 L corresponding to layouts of the first die  300 , the second layout sub-group  400 L corresponding layouts of to the second die  400 , and the third layout sub-group  200 L corresponding to layouts of the interposer  200  are co-planed. 
     As shown in  FIG. 6 , in some embodiments, the first layout sub-group  300 L may comprise layouts of a SoC die. The first layout sub-group  300 L has several functions designed in each of the layouts  300 L-1 st  to  300 L-N th . For example, the first layout sub-group  300 L has at least a function A and a function B. Function A and function B are respectively designed in each of the layouts  300 L-1 st  to  300 L-N th . For example, the layouts  300 L-1 st  to  300 L-N th  of the first layout sub-group  300 L are respectively designed to include regions  1 A- 1  to  1 A-N corresponding to function A, and regions  1 B- 1  to  1 B-N corresponding to function B. Also, the third layout sub-group  200 L corresponding to layouts of the interposer  200  has several functions corresponding to the first layout sub-group  300 L. The functions are designed in each of the layouts  200 L-1 st  to  200 L-L th . For example, the layouts  200 L-1 st  to  200 L-L th  of the third layout sub-group  200 L are respectively designed to include regions  3 A″- 1  to  3 A″-L corresponding to function A, and regions  3 B″- 1  to  3 B″-L corresponding to function B. 
     In some other embodiments as shown in  FIG. 6 , the second layout sub-group  400 L may comprise layouts of a memory die. The second layout sub-group  400 L has several functions designed in each of the layouts of the second layout sub-group  400 L. For example, the layouts  400 L-1 st  to  400 L-M th  of the second layout sub-group  400 L are respectively designed to include regions  2 A′- 1  to  2 A′-M corresponding to function A′, and regions  2 B′- 1  to  2 B′-M corresponding to function B′. In some embodiments, the functions A′ and B′ of the second layout sub-group  400 L may be a sub-function of the functions A and B of the first layout sub-group  300 L, respectively. In some other embodiments, the functions A′ and B′ of the second layout sub-group  400 L may respectively be the same as of the functions A and B of the first layout sub-group  300 L. Therefore, the regions  2 A′- 1  to  2 A′-M and  2 B′- 1  to  2 B′-M of the layouts  400 L-1 st  to  400 L-M th  of the second layout sub-group  400 L can corresponds to the regions  1 A- 1  to  1 A-N and  1 B- 1  to  1 B-N of the layouts  300 L-1 st  to  300 L-N th  of the first layout sub-group  300 L, respectively. Also, the third layout sub-group  200 L corresponding to layouts of the interposer  200  has several functions corresponding to the second layout sub-group  400 L. The functions are designed in each of the layouts  200 L-1 st  to  200 L-L th . For example, the layouts  200 L-1 st  to  200 L-L th  of the third layout sub-group  200 L are respectively designed to include regions  3 A″- 1  to  3 A″-L corresponding to function A′, and regions  3 B″- 1  to  3 B″-L corresponding to function B′. 
     As shown in  FIG. 3 , the method  300  then proceeds to step S 304  where the physical layout group is partitioned into a first physical layout partition according to the first function (e.g. function A). As shown in  FIG. 6 , in some embodiments, the first layout sub-group  300 L of the physical layout group corresponding to layouts of the first die  300  and the third layout sub-group  200 L of the physical layout group corresponding to layouts of the interposer  200  are partitioned into a first physical layout partition according to the first function, for example, function A. The first physical layout partition may comprise a first layout sub-group partition  300 LA and a third layout sub-group partition  200 LA″. The first layout sub-group partition  300 LA includes the regions  1 A- 1  to  1 A-N corresponding to function A. The third layout sub-group partition  200 LA″ includes regions  3 A″- 1  to  3 A″-L corresponding to function A. Also, the third layout sub-group partition  200 LA″ corresponds to the first layout sub-group partition  300 LA. 
     In some other embodiments while the physical layout group may further comprises a second layout sub-group  400 L as shown in  FIG. 6 , the second layout sub-group  400 L of the physical layout group corresponding to layouts of the second die  400  is also partitioned into the first physical layout partition according to the first function, for example, function A′ corresponding to function A of the first layout sub-group  300 L. Therefore, the first physical layout partition may further comprise a second layout sub-group partition  400 LA′. The second layout sub-group partition  400 LA′ includes the regions  2 A′- 1  to  2 A′-M corresponding to function A′. Also, the third layout sub-group partition  200 LA″ corresponds to the second layout sub-group partition  400 LA′. For example, third layout sub-group partition  200 LA″ including regions  3 A″- 1  to  3 A″-L also corresponds to function A′. 
     In some other embodiments, the method  300  further comprises partitioning the physical layout group into a second physical layout partition according to the second function after performing step S 302 . As shown in  FIG. 6 , in some embodiments, the first layout sub-group  300 L of the physical layout group corresponding to layouts of the first die  300  and the third layout sub-group  200 L of the physical layout group corresponding to layouts of the interposer  200  are partitioned into a second physical layout partition according to the second function, for example, function B. The second physical layout partition may comprise a first layout sub-group partition  300 LB and a third layout sub-group partition  200 LB″. The first layout sub-group partition  300 LB includes the regions  1 B- 1  to  1 B-N corresponding to function B. The third layout sub-group partition  200 LB″ includes the  3 B″- 1  to  3 A″-B corresponding to function B. Also, the third layout sub-group partition  200 LB″ corresponds to the first layout sub-group partition  300 LB. For example, third layout sub-group partition  200 LB″ including regions  3 B″- 1  to  3 B″-L, also corresponding to function B′. 
     In some other embodiments while the physical layout group may further comprises a second layout sub-group  400 L as shown in  FIG. 6 , the second layout sub-group  400 L corresponding to layouts of the second die  400  is also partitioned into the second physical layout partition according to the second function, for example, function B′ corresponding to function B of the first layout sub-group  300 L. Therefore, the second physical layout partition may further comprise a second layout sub-group partition  400 LB′. The second layout sub-group partition  400 LB′ includes the regions  2 B′- 1  to  2 B′-M corresponding to function B′. Also, the third layout sub-group partition  200 LB″ corresponds to the second layout sub-group partition  400 LB′. 
     As shown in  FIG. 3 , the method  300  then proceeds to step S 306  where a first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. As shown in  FIG. 6 , for example, the first APR process APR 1  is performed on the first physical layout partition comprising the first layout sub-group partition  300 LA and the third layout sub-group partition  200 LA″ to obtain the first hierarchical layout corresponding to function A. In some other embodiments, the first APR process APR 1  is performed on the first physical layout partition comprising the first layout sub-group partition  300 LA, the second layout sub-group partition  400 LA′ and the third layout sub-group partition  200 LA″ to obtain the first hierarchical layout corresponding to function A. 
     As shown in  FIG. 6 , in some other embodiments, the method  300  further comprises performing a second automatic place-and-route (APR) process to obtain a second hierarchical layout according to the second physical layout partition after performing step S 304 . As shown in  FIG. 6 , for example, the second APR process APR 2  is performed on second physical layout partition comprising the first layout sub-group partition  300 LB and a third layout sub-group partition  200 LB″ to obtain the second hierarchical layout corresponding to function B. In some other embodiments, the second APR process APR 2  is performed on the second physical layout partition comprising the first layout sub-group partition  300 LB, the second layout sub-group partition  400 LB′ and the third layout sub-group partition  200 LB″ to obtain the second hierarchical layout corresponding to function B. 
     As shown in  FIG. 3 , afterwards, the method  300  proceeds to step S 308  where a first verification is performed on the first hierarchical layout. In some embodiments, the first verification comprises a design rule check (DRC) and/or a layout-versus-schematic (LVS). The DRC verification may ensure that the layout follows specific design rules of a process (e.g., geometric constraints). The LVS verification includes determining that the manipulation of the design from a netlist form to the physical layout (e.g., a GDS II file) form was properly executed. As shown in  FIG. 6 , for example, a design rule check DRC 1  and/or a layout-versus-schematic LVS 1  are performed on the first hierarchical layout. 
     As shown in  FIG. 6 , in some other embodiments, the method  300  further comprises performing a second verification on the second hierarchical layout. In some embodiments, the second verification comprises at least one of a design rule check (DRC) or a layout-versus-schematic (LVS). As shown in  FIG. 6 , for example, a design rule check DRC 2  and/or a layout-versus-schematic LVS 2  are performed on the second hierarchical layout. 
     As shown in  FIG. 6 , in some other embodiments, the method  300  further comprises merging the first hierarchical layout and the second hierarchical layout to obtain a single physical layout after performing the first and second verifications on the first and second hierarchical layout, respectively. The single physical layout corresponds to the layouts of a stacked integrated circuit device comprising the first die  300 , the second die  400  and the interposer  200  as shown in  FIG. 1 . The method  300  further comprises performing a third verification on the single physical layout after obtaining the single physical layout. In some embodiments, the third verification comprises at least one of a design rule check (DRC) or a layout-versus-schematic (LVS). As shown in  FIG. 6 , for example, a design rule check DRC 3  and/or a layout-versus-schematic LVS 3  are performed on the single physical layout. 
       FIG. 4  is a flowchart illustrating a method  400  of designing an integrated circuit in accordance with some embodiments of the disclosure. For example, the integrated circuit may comprise the stacked integrated circuit  500  as shown in  FIG. 1 . Also,  FIG. 6  is a diagram illustrating the method of designing an integrated circuit in accordance with some embodiments of  FIG. 4 . Elements of the embodiments hereinafter that are the same or similar to those previously described with reference to  FIGS. 1, 2A, 2B and 3 , are not repeated for brevity. 
     As shown in  FIG. 4 , the method  400  begins at step S 402  where a first netlist corresponding to a first die (e.g. the first die  300  as shown in  FIG. 1 ) is obtained. As shown in  FIG. 6 , in some embodiments, the first netlist can be converted into the corresponding first layout sub-group  300 L. The first layout sub-group  300 L corresponds to the layouts of the first die  300  as shown in  FIG. 1 . 
     As shown in  FIG. 4 , the method  400  then proceeds to step S 404  where a second netlist corresponding to an interposer provided for the first die connected thereon is obtained. As shown in  FIG. 6 , in some embodiments, the second netlist can be converted into the corresponding third layout sub-group  200 L. The third layout sub-group  200 L corresponds to the layouts of the interposer  200  as shown in  FIG. 1 . 
     As shown in  FIG. 4 , the method  400  Afterwards proceeds to step S 406  where the first netlist is partitioned into a third netlist according to a first function. As shown in  FIG. 6 , in some embodiments, the first netlist is partitioned into a third netlist according to a first function, for example, function A. The third netlist may be converted into the corresponding first layout sub-group partition  300 LA. 
     As shown in  FIG. 4 , the method  400  Afterwards proceeds to step S 408  where the second netlist is partitioned into a fourth netlist according to the first function. As shown in  FIG. 6 , in some embodiments, the second netlist is partitioned into a fourth netlist according to the first function, for example, function A. The fourth netlist also corresponds to the third netlist. The fourth netlist be converted into the corresponding third layout sub-group partition  200 LA″, which corresponds to function A. Also, the third layout sub-group partition  200 LA″ corresponds to the first layout sub-group partition  300 LA. 
     As shown in  FIG. 4 , afterwards, the method  400  proceeds to step S 410  where a first automatic place-and-route (APR) process is performed according to the third netlist and the fourth netlist to obtain a first hierarchical netlist. As shown in  FIG. 6 , for example, the first APR process APR 1  is performed on the first layout sub-group partition  300 LA, which is converted from the third netlist, and the third layout sub-group partition  200 LA″, which is converted from the fourth netlist, to obtain the first hierarchical layout corresponding to function A. 
     As shown in  FIG. 4 , afterwards, the method  400  proceeds to step S 412  where the first hierarchical layout is verified by using a first verification. In some embodiments, the first verification comprises at least one of a design rule check (DRC) or a layout-versus-schematic (LVS). The DRC verification may ensure that the layout follows specific design rules of a process (e.g., geometric constraints). The LVS verification includes determining that the manipulation of the design from a netlist form to the physical layout (e.g., a GDS II file) form was properly executed. As shown in  FIG. 6 , for example, a design rule check DRC 1  and/or a layout-versus-schematic LVS 1  are performed on the first hierarchical layout. 
     In some other embodiments, the first and second netlists may further comprise a second function (e.g. function B). In some other embodiments, the method  400  may further comprise partitioning the first netlist into a fifth netlist according to a second function different from the first function after performing step  406 . As shown in  FIG. 6 , in some embodiments, the first netlist can be partitioned into a fifth netlist according to the second function, for example, function B. The fifth netlist be converted into the corresponding first layout sub-group partition  300 LB. 
     In some other embodiments, the method  400  may further comprise partitioning the second netlist into a sixth netlist according to the second function after performing step  408 . As shown in  FIG. 6 , in some embodiments, the second netlist can be partitioned into a sixth netlist according to the second function, for example, function B. The sixth netlist also corresponds to the fifth netlist. The sixth netlist be converted into the corresponding third layout sub-group partition  200 LB″. Also, the third layout sub-group partition  200 LB″ corresponds to the first layout sub-group partition  300 LB. The third layout sub-group partition  200 LB″ and the first layout sub-group partition  300 LB may collectively compose as the second physical layout partition corresponding to the integrated circuit module  450  as shown in  FIG. 2B . 
     In some other embodiments, the method  400  may further comprise performing a second automatic place-and-route (APR) process according to the fifth netlist and the sixth netlist to obtain a second hierarchical netlist after performing step  410 . As shown in  FIG. 6 , for example, the second APR process APR 2  is performed on the first layout sub-group partition  300 LB, which is converted from the fifth netlist, and the third layout sub-group partition  200 LB″, which is converted from the sixth netlist, to obtain the second hierarchical layout corresponding to function B. 
     Afterwards, the method  400  may proceed to verify the second hierarchical netlist. As shown in  FIG. 6 , in some other embodiments, the method  400  further comprises performing a second verification on the second hierarchical layout. In some embodiments, the second verification comprises at least one of a design rule check (DRC) or a layout-versus-schematic (LVS). As shown in  FIG. 6 , for example, a design rule check DRC 2  and/or a layout-versus-schematic LVS 2  are performed on the second hierarchical layout. 
     Afterwards, the method  400  may further proceed to merge the first hierarchical netlist and the second hierarchical netlist to obtain a first merged hierarchical netlist after performing the first and second verifications on the first and second hierarchical layout, respectively. As shown in  FIG. 6 , in some embodiments, the first merged hierarchical netlist may correspond to the single physical layout. The first merged hierarchical netlist may correspond to a stacked integrated circuit (e.g. the 2.5D stacked integrated circuit module  350 ) comprising the first die  300  and the interposer  200  as shown in  FIG. 1 . 
     Afterwards, the method  400  may further proceed to verify the first merged hierarchical netlist. As shown in  FIG. 6 , in some other embodiments, the method  400  further comprises performing a third verification on the single physical layout after obtaining the single physical layout. In some embodiments, the third verification comprises at least one of a design rule check (DRC) or a layout-versus-schematic (LVS). As shown in  FIG. 6 , for example, a design rule check DRC 3  and/or a layout-versus-schematic LVS 3  are performed on the single physical layout. 
     In some other embodiments, the integrated circuit may further comprise a second die mounted on the interposer. In some other embodiments, the method  400  may further comprise obtaining a seventh netlist corresponding to a second die, for example, the second die  400  as shown  FIG. 1 . As shown in  FIG. 6 , in some embodiments, the seventh netlist can be converted into the corresponding second layout sub-group  400 L using tools (such as CAD tools). The second layout sub-group  400 L corresponds to the layouts of the second die  400 , for example, a memory die, as shown in  FIG. 1 . 
     Afterwards, the method  400  may further comprise partitioning the seventh netlist into an eighth netlist according to a second function (e.g. function B) different from the first function (e.g. function A) after obtaining the seventh netlist. As shown in  FIG. 6 , in some embodiments, the seventh netlist can be partitioned into an eighth netlist according to the second function, for example, function B. The eighth netlist also corresponds to the fifth netlist (e.g. the first layout sub-group partition  300 LB). The eighth netlist may be converted into the corresponding second layout sub-group partition  400 LB′. Also, the second layout sub-group partition  400 LB′ corresponds to the first layout sub-group partition  300 LB. 
     Afterwards, the method  400  may further comprise partitioning the second netlist into a ninth netlist according to the second function (e.g. function B) after obtaining the eighth netlist. As shown in  FIG. 6 , in some embodiments, the ninth netlist may be the same as the sixth netlist corresponding to the second function, for example, function B. The ninth netlist also corresponds to the fifth netlist (e.g. the first layout sub-group partition  300 LB). The ninth netlist be converted into the corresponding third layout sub-group partition  200 LB″. Also, the third layout sub-group partition  200 LB″ corresponds to the first layout sub-group partition  300 LB. The third layout sub-group partition  200 LB″ and the first layout sub-group partition  300 LB may collectively compose the second physical layout partition corresponding to the integrated circuit module  450  as shown in  FIG. 2B . 
     Afterwards, the method  400  may further comprise performing a third automatic place-and-route (APR) process according to the eighth netlist and the ninth netlist to obtain a third hierarchical netlist after obtaining the ninth netlist. As shown in  FIG. 6 , in some embodiments, the third APR process may be the same as the second APR process APR 2 , and the third hierarchical netlist may be the same as the second hierarchical layout. In some other embodiments, the third APR process is performed on the second physical layout partition comprising the second layout sub-group partition  400 LB′ and the third layout sub-group partition  200 LB″ to obtain the second hierarchical layout corresponding to function B. 
     Afterwards, the method  400  may further comprise verifying the third hierarchical netlist after obtaining the third hierarchical netlist. As shown in  FIG. 6 , in some other embodiments, a verification comprising the design rule check DRC 2  and/or the layout-versus-schematic LVS 2  is performed on the third hierarchical netlist. 
     Afterwards, the method  400  may further comprise merging the first hierarchical netlist and the third hierarchical netlist to obtain a second merged hierarchical netlist after performing the first and third verifications on the first and third hierarchical layout, respectively. As shown in  FIG. 6 , in some embodiments, the second merged hierarchical netlist may correspond to the single physical layout. In some embodiments, the second merged hierarchical netlist corresponds to a stacked integrated circuit  500  comprising the first die  300 , the second die  400  and the interposer  200  as shown in  FIG. 1 . 
     Afterwards, the method  400  may further proceed to verify the second merged hierarchical netlist after obtaining the second merged hierarchical netlist. As shown in  FIG. 6 , in some other embodiments, a verification comprising the design rule check DRC 3  and/or a layout-versus-schematic LVS 3  are performed on the second merged hierarchical netlist. 
       FIG. 5  is a flowchart illustrating a method  500  of designing an integrated circuit in accordance with some embodiments of the disclosure. For example, the integrated circuit may comprise the stacked integrated circuit  500  as shown in  FIG. 1 . Also,  FIG. 6  is a diagram illustrating the method  500  of designing an integrated circuit in accordance with some embodiments of  FIG. 5 . Elements of the embodiments hereinafter, that are the same or similar to those previously described with reference to  FIGS. 1, 2A, 2B, 3 and 4 , are not repeated for brevity. 
     As shown in  FIG. 5 , the method  500  begins at step S 502  where a first netlist corresponding to a first die having a first function (e.g. function A) and a second function (e.g. function B) is obtained. As shown in  FIG. 6 , in some embodiments, the first netlist can be converted into the corresponding first layout sub-group  300 L using tools (such as CAD tools). The first layout sub-group  300 L has function A and function B. The first layout sub-group  300 L corresponds to the layouts of the first die  300  as shown in  FIG. 1 . The first die (e.g. the first die  300  as shown in  FIG. 1 ) is a SoC die. Therefore, the first netlist comprises a placement design for bump structures of the SoC die. The bump structures connect the SoC die and the interposer (e.g. the interposer  200  as shown in  FIG. 1 ). 
     Afterwards, as shown in  FIG. 5 , the method  500  proceeds to step S 504  where a second netlist corresponding to an interposer provided for the first die (e.g. the first die  300  as shown in  FIG. 1 ) connected thereon is obtained. As shown in  FIG. 6 , in some embodiments, the second netlist can be converted into the corresponding third layout sub-group  200 L using tools (such as CAD tools). The third layout sub-group  200 L corresponds to the layouts of the interposer  200  as shown in  FIG. 1 . The second netlist may correspond to a placement design for through hole vias (TSVs) passing through the interposer  200  as shown in  FIG. 1 . 
     Afterwards, as shown in  FIG. 5 , the method  500  proceeds to step S 506  where a third netlist is obtained by partitioning the first netlist and the second netlist according to the first function (e.g. function A). As shown in  FIG. 6 , in some embodiments, the third netlist can be converted into the corresponding layout comprising the first layout sub-group partition  300 LA and the third layout sub-group partition  200 LA″. 
     Afterwards, as shown in  FIG. 5 , the method  500  proceeds to step S 508  where a fourth netlist is obtained by partitioning the first netlist and the second netlist according to the second function (e.g. function B). As shown in  FIG. 6 , in some embodiments, the fourth netlist can be converted into the corresponding layout comprising the first layout sub-group partition  300 LB and the third layout sub-group partition  200 LB″. 
     Afterwards, as shown in  FIG. 5 , the method  500  proceeds to step S 510  where a first automatic place-and-route (APR) process is performed according to the third netlist to obtain a first hierarchical netlist. As shown in  FIG. 6 , for example, the first APR process APR 1  is performed on the first layout sub-group partition  300 LA and the third layout sub-group partition  200 LA″, which is converted from the third netlist, to obtain the first hierarchical layout corresponding to function A. 
     In some other embodiments, the method  400  may then proceed to performing a first verification on the first hierarchical layout. In some embodiments, the first verification comprising the design rule check DRC 1  and/or the layout-versus-schematic LVS 1  are performed on the first hierarchical layout. 
     Afterwards, as shown in  FIG. 5 , the method  500  proceeds to step S 512  where a second automatic place-and-route (APR) process is performed according to the fourth netlist to obtain a second hierarchical netlist. As shown in  FIG. 6 , for example, the second APR process APR 2  is performed on the first layout sub-group partition  300 LB and the third layout sub-group partition  200 LB″, which is converted from the fourth netlist, to obtain the second hierarchical layout corresponding to function B. 
     In some other embodiments, the method  400  may then proceed to performing a second verification on the second hierarchical layout. In some embodiments, the second verification comprising the design rule check DRC 2  and/or the layout-versus-schematic LVS 2  are performed on the second hierarchical layout. 
     Afterwards, as shown in  FIG. 5 , the method  500  proceeds to step S 514  where the first hierarchical netlist and the second hierarchical netlist are merged to obtain a merged hierarchical netlist. As shown in  FIG. 6 , in some embodiments, the merged hierarchical netlist may correspond to the single physical layout. 
     In some other embodiments, the integrated circuit may further comprise a second die mounted on the interposer. In some other embodiments, the method  500  may further comprise obtaining a fifth netlist corresponding to a second die having the first function (e.g. function A) and the second function (e.g. function B) after step S 504 . As shown in  FIG. 6 , in some embodiments, the fifth netlist can be converted into the corresponding second layout sub-group  400 L using tools (such as CAD tools). The second layout sub-group  400 L corresponds to the layouts of the second die  400 , for example, a memory die, as shown in  FIG. 1 . 
     Afterwards, the method  500  may further comprise partitioning the fifth netlist according to the first function (e.g. function A) during step S 506 . As shown in  FIG. 6 , in some embodiments, the third netlist may be converted into the corresponding first layout sub-group partition  300 LA, the second layout sub-group partition  400 LA′ and the third layout sub-group partition  200 LA″. 
     Afterwards, the method  500  may further comprise partitioning the fifth netlist according to the second function (e.g. function B) during step S 508 . As shown in  FIG. 6 , in some embodiments, the fourth netlist be converted into the corresponding first layout sub-group partition  300 LB, the second layout sub-group partition  400 LB′ and the third layout sub-group partition  200 LB″. 
     Compared with the conventional physical design framework for a 2.5D/3D integrated circuit, embodiments of the method of designing an integrated circuit has the advantage of the simultaneously designing for the layouts of the dies with the interposer and the TSVs. The layouts of the dies with the interposer and the TSVs can be modularized by partitioning the layouts according to function. Therefore, each of the stacked integrated circuit layout modules can be verified in parallel. Embodiments of the method of designing an integrated circuit can handle complicated hierarchical designs. Therefore, the goals of the faster design cycle and the increased design quality can be achieved. 
     While the invention has been described by way of example and in terms of the embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.