Patent Publication Number: US-2004043640-A1

Title: High density interconnect

Description:
BACKGROUND OF THE INVENTION  
       [0001] Many test and measurement devices, including logic analysis systems and probes, require the use of a high density interconnect to interface with a device under test. In the case of a logic analysis probe that tests circuits secured by, for example a ball grid array, it is not unusual for a logic analysis probe to use an interconnect having a 49×49 array of connections to connect the probe to the board under test. Such interconnects have a total of 2,401 connections. Many current interconnects are of the so-called “bed of nails” variety that is clamped over a matrix of lands, for example to the rear of a ball grid array, formed on a board under test. In this configuration, the connections (e.g. the nails) match with the lands on the board. Known interconnects of this configuration require a clamping force of 40 to 60 grams per contact meaning that over 96 Kilograms (up to 144 Kilograms) of clamping force is required. Other known types of interconnects include socketing and a variety of board to board interconnects most of which have similar clamping requirements.  
       [0002] Examples of known interconnects include those produced by INTERCON SYSTEMS, SHINETSU, TYCO, TELADYNE, and PARACON for use with their respective probe offerings. The probes provided by such producers often include additional circuitry to perform specialized functions including: pin translation, termination, and compensation. In these probes, the additional circuitry is either added to the test and measurement unit or embedded in an additional structure associated with the cable. While useful, such additional circuitry would benefit from being integrated with the interconnect. Such integration would lead to decreased loads and reduced stub lengths.  
       [0003] Accordingly, the present inventors have recognized a need for interconnects that reduce the required clamping force while providing for integrated circuitry. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0004] An understanding of the present invention can be gained from the following detailed description of the invention, taken in conjunction with the accompanying drawings of which:  
     [0005]FIG. 1 is a cross-sectional view of a connection in accordance with a preferred embodiment of the present invention.  
     [0006]FIG. 2 is a cross-sectional view of a connection, as shown in FIG. 1, in situ in accordance with a preferred embodiment of the present invention  
     [0007]FIG. 3 is a plan view of an interconnect in accordance with a preferred embodiment of the present invention.  
     [0008]FIG. 4 is a cross-sectional view of a connection, in accordance with a preferred embodiment of the present invention, taken along line A-A in FIG. 3.  
     [0009]FIG. 5 is a cross-sectional view of an interconnect, in accordance with a preferred embodiment of the present invention, taken along line B-B in FIG. 3.  
     [0010]FIG. 6 is a cross-sectional view of a connection in accordance with another preferred embodiment of the present invention.  
    
    
     DETAILED DESCRIPTION  
     [0011] Reference will now be made in detail to the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.  
     [0012]FIG. 1 is a cross-sectional view of a connection  100  in accordance with a preferred embodiment of the present invention. It will be appreciated by those of ordinary skill in the relevant arts that the connection  100 , as illustrated in FIG. 1, and the operation thereof as described hereinafter is intended to be generally representative such connections and that any particular connection may differ significantly from that shown in FIG. 1, particularly in the details of construction of such interconnect, while still falling within the scope of the invention. As such, the connection  100  is to be regarded as illustrative and exemplary and not limiting as regards the invention described herein or the claims attached hereto.  
     [0013] The connection  100  is formed on a printed circuit board (PCB)  102 , comprising for example FR-4. Flexible layers  104  and  106  are bonded to a first and second side of the PCB  102 . The flexible layers are preferably formed of Capton and act, in effect, as flexible circuit boards. A pair of conductive bumps  108  and  110  are formed on the flexible layers  104  and  106 , respectively, over a hole  112  in the PCB  102 . The bumps  108  and  110  are preferably formed of gold, but any suitable conductive material may be used such as copper. The bumps  108  and  110  are connected using vias (not shown in FIG. 1) formed to electrically connect the flexible layers  104  and  106  through the PCB  102 . Usually, but not always, vias are formed by drilling a hole through the PCB  102  and the flexible layers  104  and  106  and depositing conductive material, such as gold or copper, into the hole.  
     [0014]FIG. 2 is a cross-sectional view of the connection  100 , as shown in FIG. 1, in situ in accordance with a preferred embodiment of the present invention. More specifically, FIG. 2, shows the connection  100  interposed between a first board  202  (for example a connector on a probe) and a second board  204  (for example a circuit under test). The flexible layers  104  and  106  are flexed toward the center of the PCB  102  into the hole  112 . It is anticipated that the clamping force required will be in the range of 20 to 25 grams per connector. Thus, in a 49×49 array of 2,401 connections no more that 60 Kilograms of clamping force should be required.  
     [0015]FIG. 3 is a plan view of an interconnect  300  in accordance with a preferred embodiment of the present invention. FIG. 3 shows an 11×11 array of connections  302   n . Each connection comprises conductive bumps  304   n  (along with opposing bumps on the other side of the interconnect  300 —not shown), vias  306   n , and vents  308   n . The vias  306   n  are connected to the bumps  304   n  by tracings  310   n  on the flexible layer  312 . The opposing bumps  320   n  (see FIGS. 4 and 5) are similarly connected with tracing on the flexible layer  318  (see FIGS. 4 and 5). The vias  306   n  are preferably placed at 45 degrees to the grid of bumps  302   n  to allow for more efficient packing. It should be noted that it is possible, and maybe even desirable, to coat the hole  314   n  (see FIG. 4) with a conductor thereby forgoing the need for a separate signal feed  306   n.    
     [0016] The vents  308   n  are provided to allow gas to escape the holes  112  during fabrication of the interconnect  300  and during compression in use. Depending on the fabrication method, the vent holes  308   n  may not be required.  
     [0017]FIG. 4 is a cross-sectional view of a connection  302 , in accordance with a preferred embodiment of the present invention, taken along line A-A in FIG. 3. As set forth above, the connection  302  is formed on a PCB  316  layered with flexible layers  312  and  318 . Bumps  304  and  320  are deposited on the flexible layers  312  &amp;  318 , respectively, over the hole  314 . A via  306  electrically connects the bumps  304  and  320 . A vent  308  (optional) is provided on the flexible layer  312  to permit gas to escape from the hole  314 . Those of ordinary skill in the art will recognize that FIG. 4 shows one possible orientation of via  306 , hole  314 , and vent  308 .  
     [0018]FIG. 5 is a cross-sectional view of the interconnect  300 , in accordance with a preferred embodiment of the present invention, taken along line B-B in FIG. 3. The pitch between adjacent bumps  604   n  and/or adjacent bumps  320   n  may be adjusted to match the circuit under test, but could be as close as 1.00 mm or less  
     [0019] One process for the creation of an interconnect in accordance with the preferred embodiments of the present invention is set forth hereinafter. The process uses the following materials: sheet adhesive (such as the Dupont AP series); Capton (such as the Dupont LF series); PCB (such as Isola FR4); Dry Film Resist; and Silver Halide Film.  
     [0020] 1. Shear adhesive, Capton and PCB materials relative to lamination plate dimensions.  
     [0021] 2. Clean materials from step #1.  
     [0022] 3. Set the adhesive and Capton materials aside in a desiccant chamber.  
     [0023] 4. Drill air gap vias and tooling in PCB to specifications.  
     [0024] 5. Coat Drilled PCB material with Dry Film Resist.  
     [0025] 6. Photoplot and develop to provide targeting coupon information relative to drilled holes on the PCB material.  
     [0026] 7. Using the Silver Halide Film, eye registered them to the drilling in the PCB material.  
     [0027] 8. Print resist coated PCB.  
     [0028] 9. Develop the resist coated PCB material.  
     [0029] 10. Etch resist coated PCB material.  
     [0030] 11. Strip resist coated PCB material.  
     [0031] 12. Punch tooling holes in adhesive and Capton materials.  
     [0032] 13. Place adhesive and PCB materials in Plasma Etch at 225° F. for 1 hour then plasma using Flex Press Prep Cycle.  
     [0033] 14. Layup adhesive, Capton and PCB materials along with all other pertinent pressing materials.  
     [0034] 15. Press at desired temperature followed by a 30 min cooling cycle under high pressure.  
     [0035] 16. Drill conduction vias in panel with respect to etched targeting pattern.  
     [0036] 17. Plate thru panel in conduction vias.  
     [0037] 18. Panel plate the plated thru panel to a copper deposition thickness in the conduction vias.  
     [0038] 19. Coat panel with Electrophoretic Resist.  
     [0039] 20. Photoplot and develop according to specified artwork to provide land pads relative to drilled holes on the PCB material.  
     [0040] 21. Using the Silver Halide Films, eye registered them to the drilling in the panel.  
     [0041] 22. Print resist coated panel with Silver Halide films.  
     [0042] 23. Develop resist-coated panel.  
     [0043] 24. Etch resist-coated panel.  
     [0044] 25. Strip resist coated panel.  
     [0045] 26. Coat panel with 3 layers of Dry Film Resist.  
     [0046] 27. Photoplot and develop according to specified artwork to provide plating image relative the land pads etched on the panel.  
     [0047] 28. Using the Silver Halide Films, eye registered them to the land pads on the panel.  
     [0048] 29. Print resist-coated panel.  
     [0049] 30. Develop resist-coated panel.  
     [0050] 31. Electroplate copper “Bumps” on the resist-coated panel at the relevant length of time, preferably at very low current.  
     [0051] 32. Strip resist coated panel.  
     [0052] 33. Coat panel with Dry Film Resist.  
     [0053] 34. Photoplot and develop according to specified artwork to provide a post gold etch resist relative to the etched land pads on the panel.  
     [0054] 35. Using the Silver Halide Films, eye registered them to the land pads.  
     [0055] 36. Print resist coated panel with Silver Halide films.  
     [0056] 37. Develop resist-coated panel.  
     [0057] 38. Electrolytic Gold/Nickel-plate (Subcontract) with 25 uin of Gold over 250 uin of Nickel.  
     [0058] 39. Strip resist coated panel.  
     [0059] 40. Etch panel.  
     [0060] 41. Final Route “Bump” boards from panel according to specified artwork and tolerances.  
     [0061] Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents. For example, the PCB  102  can be configured as a multi-layer circuit to facilitate pin translation. Also, while the printed circuit board  102  is described as having holes  112  which extend through the PCB  102 , those of ordinary skill in the art will recognize that the holes  112  need not extend through the board. The holes  112 , but need only be deep enough to contain the portions of the flexible layers ( 104  and  106 ) and the bumps ( 108  and  110 ) that are displaced when the interconnect  300  is in use. In such a configuration, it would be possible to use the non-perforated middle of the PCB as a signal layer for re-routing signals between bumps. It is also envisioned that other structures can be utilized instead of the PCB  102 . Most any stiff structure, such as any number of ceramics, capable of bonding to the flexible layers  104  and  106  could be utilized.  
     [0062] One advantage of the present invention is that it facilitates the embedding of additional circuit components, such as resistors and capacitors to perform specialized functions, including pin translation, termination, and compensation. Such components can be incorporated by embedding them in the signal paths  306   n  of PCB  102 , mounted on the flexible layers  312  and  318 , or mounted to the PCB  316 . Pin translation can be implemented by, for example, opening selected signal paths  306   n  or re-routing the tracings  310   n.    
     [0063]FIG. 6 is a cross-sectional view of a connector  602  in accordance with another preferred embodiment of the present invention taken along line A-A in FIG. 3. FIG. 6 illustrates the embedding of components, in this case a resistor  604 , in vias  306   n . The present invention is particularly suited for the embedding of networks comprising: resistors (R); capacitors (C); and inductors (L). R, RC, and RCR networks may be formed and embedded into PCB  316  or surface mounted onto the PCB  316 , the flexible layer  312  or the flexible layer  318 .  
     [0064] Components, such as the resistor  604 , can be embedded by placing the component, or components, into the holes used to form vias  306   n , as in the previous description, and then filing the hole with solder. It may be desirable to select the thickness of the PCB 102  to match that of the component to facilitate economical assembly. The use of a ceramic board instead of the PCB  316  may facilitate embedding.