Patent Publication Number: US-4649508-A

Title: Floating-point arithmetic operation system

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a floating-point arithmetic system, and mcre particularly to such a system formed of a semiconductor integrated circuit. 
     Processing of floating-point numbers has not been standardized, so that demand for execution of classification of floating-point numbers in terms of their attributes (zero, infinity, not-a-number, normalized number, and denormalized number) by hardware has not been strong. But recently, an IEEE (The Institute of Electrical and Electronics Engineers, Inc.) Standard concerning processing of floating-point numbers was proposed, and the need for processing in accordance with the classification of the floating-point numbers has arisen. 
     Conventional floating-point arithmetic units generally comprise a floating-point processor under microprogram control. The classification of the input operands is often done by a microprogram. Similarly, exception handling in accordance with the classification in terms of the attribute is often done by a microprogram. 
     Where the classification of the operands is done by a microprogram, at least one machine cycle is necessary to execute the classification. Moreover, a number of machine cycles are needed for the exception handling. As a result, the processing by the conventional system is slow. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to provide a floating-point arithmetic unit which can perform the classification of the input operand and the exception processing at a high speed. 
     According to the invention, there is provided a floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, comprising: 
     an X classification circuit receiving at least part of the bits representing the operand X to classify the operand X and producing at least one X class signal indicative of the result of the classification; 
     a Y classification circuit receiving at least part of the bits representing the operand Y to classify the operand Y and producing at least one Y class signal indicative of the result of the classification; and 
     adopting means responsive to the X class signal, and Y class signal for adopting, at least part of the bits of the operand X, at least part of the bits of the operand Y or a predetermined set of bits, as at least part of the result Z of the operation when the significances of the X class signal and the Y class signal form one of predetermined combinations. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings 
     FIG. 1 is a block diagram showing an embodiment of a floating-point arithmetic operation system according to the invention; 
     FIGS. 2A, 2B and 2C show formats of floating-point numbers as expressed at various part of the system; 
     FIG. 3 is a block diagram showing an example of a classification circuit; 
     FIG. 4 is a table showing the relationship between the combination of the kind of operation to be performed and the classes of the operands and the value of Z, i.e., the result of operation; 
     FIG. 5 shows in detail an example of a control PLA; 
     FIGS. 6 and 7 show in detail an example of a mantissa comparator; and 
     FIGS. 8-10 show in detail an example of a selector and a sign circuit. 
    
    
     DESCRIPTION OF THE EMBODIMENT 
     FIG. 1 shows a floating-point arithmetic operation system of an embodiment of the invention. 
     A first or X register 1 is a register receiving and storing a first operand X of 32 bits. A second or Y register 2 is a register receiving and storing a second operand Y of 32 bits. Each of the operands X, Y is represented by the format as shown in FIG. 2A according to the proposed IEEE Standard. In FIG. 2A, S is the sign bit, the field E is for 8-bit exponent whose value is biased by 127 (=2 7  -1), and the field F is for the 23-bit fraction, which, together with an implicit leading 1, yields the mantissa having a value 1.F. A normalized nonzero number as represented by the format of FIG. 2A has a value: 
     
         (-1).sup.S * 2.sup.E-127 * (1.F) 
    
     A first or X classification circuit 3 receives 31 bits in the fields E and F of the operand X from the X register 1 and determines the class of the operand X. The classification of the operands is made by attribute of the operands into five categories or classes, i.e., zero (ZERO), infinity (INF), not-a-number (NAN), normalized number (NML) and denormalized number (DNL). The X classification circuit 3 has six output lines, five of which are used to transmit signals ZERO, INF, NAN, NML and DNL, each of which is &#34;0&#34; when the operand X from the X register 1 is of the particular class. The remaining one output line is used to transmit a signal E0, which is &#34;1&#34; when the LSB in the field E is &#34;1&#34; or the operand X is DNL. 
     FIG. 3 shows in detail an example of the X classification circuit 3. As illustrated, it comprises a NOR gate 101 receiving 23 bits of the field F of the operand X. Its output is &#34;1&#34; when all the bits in the field F are &#34;0&#34;. A second NOR gate 105 receives 8 bits of the field E of the operand X. Its output is &#34;1&#34; when all the bits in the field E are &#34;0&#34;, i.e., E=0. An AND gate 107 also receives the 8 bits of the field E. Its output is &#34;1&#34; when the bits in the field E are all &#34;1&#34;, i.e., E=255. A NOT circuit 102 inverts the output of the NOR gate 101. A NAND gate 103 receives the outputs of NOR gates 101 and 105, and its output ZERO is &#34;0&#34; when the operand X is zero. A NAND gate 104 receives the outputs of the NOR gate 101 and the AND gate 107 and its output INF is &#34;0&#34; when the operand X is infinity. A NAND gate 108 receives the outputs of the NOT circuit 102 and the AND gate 107 and its output NAN is &#34;0&#34; when the operand X is not-a-number. A NAND gate 106 receives the outputs of the NOT circuit 102 and the NOR gate 105 and its output DNL is &#34;0&#34; when the operand X is a denormalized number. A NAND gate 111 receives the outputs of the NAND gates 103, 104, 106 and 108 and its output NML is &#34;0&#34; when the operand X is a normalized number. A NOT circuit 109 inverts the LSB XE0 of field E of the operand X. A NAND gate 110 receives the outputs of the NOT circuit 109 and the NAND gate 106 and its output E0 is &#34;1&#34; when the LSB of the field E of the operand X is &#34;1&#34; or the operand X is a denormalized number. The E0 is used as a substitute for the LSB of the exponent. 
     A second or Y classification circuit 4 receives 31 bits in the fields E and F of the operand Y from the Y register 2 and determine the class of the operand Y. The structure and function of the Y classification circuit 4 are similar to those of the X classification circuit 3. 
     A class bus 5 comprises 10 signal lines carrying the signals XZERO, XINF, XNML, XNAN, XDNL which are the same as ZERO, INF, NML, NAN, DNL from the X classification circuit 3 and the signals YZERO, YINF, YNML, YNAN, YDNL which are the same as ZERO, INF, NML, NAN, DNL from the Y classification circuit 4. 
     An X bus 6 comprises 33 signal lines, 31 of which carry the sign bit, all the bits in the field F and the bits in the field E, except the LSB, of the output of the X register 1. The remaining two signal lines carry the outputs DNL and E0 of the X classification circuit 3. The output E0 is used to constitute the exponent&#39;s LSB. The output DNL is used to constitute the implied &#34;1&#34; bit of the mantissa M. Thus, the operand X is represented on the bus 6 by the format shown in FIG. 2B. 
     A Y bus 7 has a similar composition, except that it receives signals from the Y register 2 and the Y classification circuit 4 instead of the X register 1 and the X classification circuit 3. 
     A command bus 8 comprises three signal lines carrying signals A, S and M which are used to command addition, subtraction and multiplication, respectively, by being set at &#34;1&#34;. 
     A multiplication section 20 comprises a normal or ordinary floating-point multiplication unit 20A, which comprises a sign processor 21, an exponent processor 22 and a mantissa processor 23. 
     The sign processor 21 comprises an Exclusive-OR gate receiving the sign bits from the X bus 6 and the Y bus 7. 
     The exponent processor 22 receives the 8-bit exponent from each of the X bus 6 and the Y bus 7, and comprises a circuit for adding the two exponents and making adjustment for normalization. It produces an 8-bit output signifying the exponent of the result Z of the multiplication (product). When the exponent field E becomes negative through the process of adjustment for normalization, an output signal SIGN becomes &#34;1&#34;. 
     The mantissa processor 23 comprises a circuit for performing a fixed point multiplication on the two mantissas and a normalization circuit for normalizing the result of the fixed point multiplication. The processor 23 receives the 24-bit mantissa from each of the X bus 6 and the Y bus 7, and produces a 23 bit fraction for the result Z. Its additional output LONGSHIFT becomes &#34;1&#34; when the normalization requires rightward shift of more than 24 bits, and its further output POV becomes &#34;1&#34;  when the exponent overflows. 
     A fraction selector 26 receives the 23 bit fraction signal from the mantissa processor 23 and the 23 bit output of a ROM 26A. The 23 bits from the ROM 26A are all &#34;0&#34;. 
     The fraction selector control circuit 27 receives the signals LONGSHIFT and POV from the mantissa processor 23 and the signals XZERO, YZERO, XDNL, and YDNL from the class bus 5, and determines MZERO by the following logical equation. 
     
         MZERO=XZERO+YZERO+XDNL·YDNL+POV+LONGSHIFT 
    
     The fraction selector 26 is controlled by the signals MZERO and MZERO from the control circuit 27 and selects the output of the ROM 26A when the signal MZERO is &#34;1&#34;, and selects the output of the processor 23 when MZERO is &#34;1&#34;. 
     An exponent selector 24 receives the 8 bit exponent signal from the exponent processor 22 and the 8 bit outputs of ROM&#39;s 24A and 24B. The 8 bits from the ROM 24A are all &#34;1&#34;, while the 8 bits from the ROM 24B are all &#34;0&#34;. 
     An exponent selector control circuit 25 receives the signal POV from the mantissa processor 23, the signal SIGN from the exponent processor 22 and the signals XZERO, YZERO, XDNL and YDNL from the class bus 5, and determines the signals EONE, EZERO and ENORMAL by the following logical equations: 
     
         EONE=POV 
    
     EZERO=XZERO+YZERO+XDNL·YDNL+SIGN 
     
         ENORMAL=EONE+EZERO 
    
     The exponent selector 24 is controlled by the exponent selector control circuit 25 and selects the output of the ROM 24A when the signal EONE is &#34;1&#34;, selects the output of the ROM 24B when the signal EZERO is &#34;1&#34;, and selects the output of the exponent when the signal ENORMAL is &#34;1&#34;. 
     When at least one of the operands X and Y is ZERO, the signals MZERO and EZERO are both &#34;1&#34;. When the operands X and Y are both DNL, the signals MZERO, EZERO are both &#34;1&#34;. The signal MZERO is also &#34;1&#34; when the signal POV or the signal LONGSHIFT is &#34;1&#34;. The signal EONE is &#34;1&#34; when the signal POV is 1, i.e., an exponent overflow occurs. The signal EZERO is &#34;1&#34; when the exponent underflow occurs. The signal ENORMAL becomes &#34;1&#34; when neither EONE nor EZERO is &#34;1&#34;. 
     The outputs of the exponent selector 24 and the fraction selector 26, together with the output of the sign circuit 21 form a 32 bit output of the multiplication section 20. 
     An addition/subtraction section 40 receives 33 bits from the X bus 6 and 33 bits from the Y bus 7. It also receives the signal S from the command bus 8 and the signals from the class bus 5. It comprises a normal or ordinary floating-point addition/subtraction unit 40A comprising an array of adders. The addition/subtraction unit 40A performs either addition or subtraction depending on the significance of the signal S. More particularly, it performs addition when the signal S is &#34;0&#34;, and it performs subtraction when the signal S is &#34;1&#34;. 
     The addition/subtraction section 40 has a further function of adopting a predetermined set of bits as at least part of the result of the operation, in place of the corresponding bits of the result of the operation performed by the unit 40A, when either operand is in a special class. 
     A selector 32 receives the outputs of the multiplication section 20 and the addition/subtraction section 40, and selects the output of the multiplication section 20 when the signal M is &#34;1&#34; and selects the output of the addition/subtraction section 40 when the signal M is &#34;0&#34;. 
     An exception handling section 10 comprises a mantissa comparator 11, a control PLA (programmable logic array) 12, a selector 13 and a sign circuit 14. 
     The mantissa comparator 11 reads the 24-bit mantissa from each of the X bus 6 and the Y bus 7. Its output (X&gt;Y) 0  becomes &#34;1&#34; when the mantissa of the operand X is found to be greater than the mantissa of the operand Y. 
     FIG. 6 shows in detail the mantissa comparator 11. As shown, it comprises 24 comparison units CMP0-CMP23, receiving respective bits XM0-XM23 and YM0-YM23 of the mantissas of the operand X and the operand Y. 
     FIG. 7 shows in detail one of the comparison units CMPi (i=0-23). It receives one each bit XMi, YMi of the operands X, Y. It also receives signals (X=Y) i+1  and (X&gt;Y) i+1  from a comparison unit CMP i+1  for the next higher bit. When the signal (X=Y) i+1  is &#34;1&#34;, it signifies that the higher order bits (down to the next higher bit (i+1)) at the mantissas of the operands are identical to each other. When the signal (X&gt;Y) i+1  is &#34;1&#34;, it signifies that the comparison down to the next higher bit (i+1) has revealed that the mantissa of X is greater than the mantissa of Y. How these signals (X=Y) i+1  and (X&gt;Y) i+1  are derived will be understood from the following description on how the signals (X=Y) i  and (X&gt;Y) i  are derived. The comparison unit CMP23 of the MSB always receives &#34;1&#34; for the (X=Y) i+1  signal, and &#34;0&#34; for the (X&gt;Y) i+1  signal. 
     As illustrated, the comparison unit CMP i  comprises NOT circuits 501, 502, 503, respectively receiving the signals (X=Y) i+1 ,(X&gt;Y) i+1 , XM i . An AND gate 504 and a NOR gate 505 receives the signals XM i  and YM i . A NOR gate 506 receives the outputs of the AND gate 504 and the NOR gate 505. An OR gate 507 receives the outputs of the NOT circuits 501, 503 and the signal YM i . A NOR gate 508 receives the outputs of the NOT circuit 501 and the NOR gate 506. A NAND gate 509 receives the outputs of the OR gate 507 and the NOT circuit 502. The output of the NOR gate 508 constitutes a signal (X=Y) i  and the output of the NAND gate constitutes a signal (X&gt;Y) i . The function of the logical network described can be represented by the following logical expressions. 
     
         (X=Y).sub.i =(X=Y).sub.i+1 ·(XM.sub.i ⊕YM.sub.i) 
    
     
         (X&gt;Y).sub.i =(X&gt;Y).sub.i+1 +XM.sub.i ·YM.sub.i ·)X=Y).sub.i+1 
    
     These signals (X=Y) i  and (X&gt;Y) i  are supplied to a comparison unit CMP i-1  for the next lower bit. The signal (X&gt;Y) 0  from the comparison circuit CMP 0  for the LSB indicates the ultimate result of the comparison between the mantissas of the operands X and Y and is used as the output of the mantissa comparator 11. 
     The control PLA 12 receives 6 bit signals XZERO, XINF, XNAN, YZERO, YINF, YNAN from the class bus 5. The control PLA 12 also receives the sign bit XS from the X bus 6, and the sign bit YS from the Y bus 7, and the signals A and S from the command bus 8 respectively commanding addition and subtraction. 
     FIG. 5 shows in detail the control PLA 12. As illustrated, it comprises NOT circuits 251-257 respectively receiving the signals XZERO, XINF, XNAN, YZERO, YINF, YNAN and (X&gt;Y) O . It also comprises an Exclusive-OR gate 258 receiving the signals XS and YS, an Exclusive-OR gate 259 receiving the output of the Exclusive-OR gate 258 and the signal S, a NOT circuit 260 receiving the output of the Exclusive-OR gate 259, a NOR gate receiving the signals A and S, a NOT circuit 262 receiving the output of the NOR gate and a NAND gate 263 receiving the signals XINF, XNAN, YINF, and YNAN. The output EX is therefore given by: 
     
         EX=XINF+XNAN+YINF+YNAN 
    
     The PLA 12 further comprises an AND circuit block 51 and an OR circuit block 52. The inputs to the AND circuit block 51 are those coupled to the upper ends of the vertical conductors or columns. The outputs of the AND circuit block 51 are derived from the horizontal conductors or rows 201-221. The output of each row is given as a product of inversions of those inputs of the columns whose intersections with the row in question are circled. 
     The inputs to the OR circuit 52 are placed on the horizontal conductors or rows connected to the outputs of the AND circuit 51. The outputs of the OR circuit 52 are derived from the vertical conductors or columns 222-225. The output of each column is given as the result of NOR operation of the inputs of the rows whose intersection with the column in quenstion are circled. 
     It will therefore be appreciated that the outputs on the respective conductors 201-225 or their inversions are given by the following expressions: 
     
         201=XINF·YZERO·YINF·YNAN 
    
     
         202=(A+S)·XINF·YZERO 
    
     
         203=(S⊕XS⊕YS)·XINF·YINF 
    
     
         204=XNAN·YZERO·YINF·YNAN 
    
     
         205=XNAN·YZERO 
    
     
         206=XNAN·YINF 
    
     
         207=XNAN·YNAN·(X&gt;Y).sub.0 
    
     
         208=(A+S)·XINF·YINF 
    
     
         209=XINF·YNAN 
    
     
         210=XNAN·YNAN·(X&gt;Y).sub.0 
    
     
         211=XZERO·XINF·XNAN·YINF 
    
     
         212=(A+S)·XZERO·YINF 
    
     
         213=XZERO·XINF·XNAN·YNAN 
    
     
         214=XZERO·YNAN 
    
     
         215=(S⊕XS⊕YS)·(A+S)·XINF·YINF 
    
     
         216=(A+S)·XINF·YZERO 
    
     
         217=(A+S)·XZERO·YINF 
    
     
         218=(A+S)·XINF·YZERO 
    
     
         219=(A+S)·XZERO·YINF 
    
     
         220=(A+S)·XINF·YZERO·YNAN 
    
     
         221=(A+S)·XZERO·XNAN·YINF 
    
     
         222=(S⊕XS⊕YS)·(A+S)·XINF·YINF +(A+S)·XINF·YZERO+(A+S)·XZERO·YINF 
    
     
         223=(A+S)·XINF·YZERO·YNAN +(A+S)·XZERO·XNAN·YINF ##EQU1## 
    
     The output on the conductors 222, 224, 225 are inverted by inverters 264, 265, 266 to become signals NAN, OX, OY, respectively, while the outputs on the conductors 218, 219, 223 constitute signals fNAN0, fNAN1, PS, respectively, so that these signals (or their inversions) are represented by the following expressions: ##EQU2## 
     Moreover, the output of the Exclusive-OR gate 258 is given by: 
     
         XS⊕YS 
    
     This signal is used as another output of the control PLA 12. 
     The selector 13 receives a 31 bit signal, which does not include the sign bit and the DNL bit in FIG. 2B, from each of the X bus 6 and the Y bus 7. It also receives a combination of 29 bits, which are all &#34;1&#34;, from a ROM 13A and two bits fNAN0, fNAN1 from the control PLA 12, the two bits fNAN0, fNAN1 forming the LSB and the second least significant bit. Thus, the bit array of the &#34;combination&#34; is as shown in FIG. 2C. 
     The selector 13 selects one of the three inputs in accordance with signals OX, OY, NAN supplied from the control PLA and acting as selection control signals. More specifically, when the signal OX is &#34;1&#34;, the input from the X bus 6 is selected. When the signal OY is &#34;1&#34;, the input from the Y bus 7 is selected. When the signal NAN is &#34;1&#34;, the &#34;combination&#34; is selected. 
     FIG. 8 shows in detail the selector 13 and the sign circuit 14. As illustrated, the selector 13 comprises 31 selection units SELC0-SELC30 receiving, at first input terminals XM0-XM22 and XE0-XE7 from the X bus 6, at second input terminals YM0-YM22 and YE0-YE7 from the Y bus 7, and, at third input terminals, fNAN0-fNAN1 from the control PLA 12 and &#34;1&#34;. . . &#34;1&#34; from the ROM 13A. The selection by each selection unit is in accordance with the signals OX, OY, NAN from the control PLA 12. 
     The sign circuit 14 receives the sign bit XS from the X bus 6, the sign bit YS from the Y bus 7, the signals XSγYS, PS, OX, OY from the control PLA 12, the signal YNAN from the class bus 5 and the signal S from the command bus 8, and determines the significance of the output EXH31, which forms the sign bit of Z, in accordance with the significance of the inputted signals. 
     The outputs EXH0-EXH31 of the selctor 13 and the sign circuit 14 form a 32 bit array of the proposed IEEE standard (FIG. 2A). 
     FIG. 9 shows in detail one of the selection units SELC0-SELC30. As illustrated this selection unit SELC i  comprises a transfer gate 301 receiving a data bit from the X bus, a transfer gate 302 receiving a data bit from the Y bus, and a transfer gate 303 receiving a data bit 303 from the ROM 13 or one of fNAN1 and fNAN0. The transfer gates 301, 302 and 303 are made open when the corresponding one of the signals OX, OY and NAN is &#34;1&#34;. An amplifier 304 amplifies the selected output of the transfer gates. The output of the amplifier 304 constitutes the output EXH i  of the selection unit SELC i . 
     FIG. 10 shows in detail the sign circuit 14. A NOT circuit 404 receives the signal PS. An AND gate 401 receives the signal XS⊕YS and the output of the NOT circuit 404. An AND gate 406 receives the signal S and the signal YNAN. An Exclusive-OR gate 407 receives the signal YS and the output of the AND gate 406. An AND gate 402 receives the output of the Exclusive-OR gate 407, the signal PS, and the signal OY. An AND gate 403 receives the signal XS, the signal PS and the signal OX. An OR gate 405 receives the outputs of the AND gates 401, 402 and 403. The output of the OR gate constitutes the output EXH31 of the sign circuit 14. The output EXH31 is therefore given by: 
     
         EXH31=(XS⊕YS)·PS+(YS⊕(S·YNAN))·PS.multidot.OY+XS·PS·OX 
    
     FIG. 4 shows the relationship between some of combinations of the inputs, i.e., the types of the given operands and the kinds of arithmetic operation commanded and the output, i.e., how the value of the output Z and its sign bit should be determined. The value in the columns ZERO, INF, NAN for the operand X is &#34;1&#34; or &#34;0&#34; depending on whether the operand X is ZERO, INF or NAN. The value in the columns ZERO, INF, NAN for the operand Y is &#34;1&#34;or &#34;0&#34; depending on whether the operand Y is ZERO, INF or NAN. The value in the column A+S (=M) is &#34;1&#34; when either addition or subtraction is commanded and is &#34;0&#34; when multiplication is commanded. &#34;X&#34; in the column Z(efZ) signifies that the Z=X, so that all the bits of X should be used, without change, as the bits of Z. &#34;(X)&#34; in the same column signifies that the exponent and the fraction of Z are equal to those of X, so that all the bits except the sign bit should be used, without change, as the bits of Z. &#34;Y&#34; and &#34;(Y)&#34; in the same column have similar significances. &#34;NAN&#34; in the column Z(efZ) indicates that exponent and fraction of Z should have a value of NAN, i.e., the exponent should be all &#34;1&#34; as prescribed by the proposed IEEE standard and the fraction should be one of the predetermined values. The value of the fraction for each case NAN(#1), NAN(#2), NAN(#3) is as indicated in the column fZ. The column ZS is provided to indicate the sign bit of Z where the column Z(efZ) does not specify the sign bit of Z or where Z is NAN. 
     The output of the selector 13 and the output of the sign circuit 14 form a 32 bit output of the exception handling section 10. 
     A selector 31 receives the output of the exception handling section 10 and the selector 32. It also receives the signal EX from the control PLA12. It selects the output of the exception handling section 10 when the signal EX is &#34;1&#34;, and selects the output of the selector 32 when the signal EX is &#34;0&#34;. 
     In operation, operands in the X register 1 and the Y register 2 are supplied to the X classification circuit 3 and the Y classification circuit 4, and classified into ZERO, INF, NAN, DNL and NML. The signals ZERO, INF, NAN, DNL and NML indicative of the results of the classification are transferred via the class bus 5 and delivered to the control PLA12, the exponent selector control circuit 25 and the fraction selector control circuit 27. Thus, the signals indicative of the results of the classification are used in the multiplication section 20 to directly produce the value for Z (the result of arithmetic operation) without recourse to a normal floating-point multiplication operation when either or both of the operands is of one of special classes (ZERO, DNL). Similar processing is performed in the addition/subtraction section 40 to directly produce the value of Z without recourse to normal floating-point addition/subtraction operation when either or both of the operands is of one of special classes. 
     When the combination of the kind of arithmetic operation to be performed and the classes of the operands X and Y is one of those shown in the table of FIG. 4, 32-bit value of Z, which is the result of exception handling, is produced by the exception handling section 10 and is supplied to the selector 31, which selects, responsive to the signal EX from the control PLA 12, the result of the exception handling. 
     As has been described, the invention provides a floating-point arithmetic operation system having hardware units for classifying the operands and performing exception handling. The system is therefore capable of attaining a higher processing speed than conventional systems with a microprogram for the exception handling.