Patent Publication Number: US-8970187-B2

Title: Voltage generator

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 101147281, filed on Dec. 13, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND 
     1. Technical Field 
     The invention relates to a voltage generator, and a more particularly to an asymmetric voltage generator. 
     2. Related Art 
       FIG. 1  is a circuit diagram of a conventional voltage tuner  100 . The voltage tuner  100  includes an operational amplifier  110 , a transistor MP, and the resistors Rf 1  and Rf 2 . The operational amplifier  110  has a positive input terminal receiving an input voltage Vref, and a negative input terminal receiving a feedback voltage Vf transmitted back between the resistors Rf 1  and Rf 2 . The transistor MP has a gate coupled to an output terminal of the operational amplifier  110 , a source receiving a reference voltage Vin, and a drain connected to a terminal of the resistor Rf 2  to generate an output voltage Vout. Another terminal of the resistor Rf 2  generates the feedback voltage Vf, and the resistor Rf 1  is connected in series between the terminal of resistor Rf 2  generating the feedback voltage Vf and a ground voltage GND serving as another reference voltage. 
     The voltage tuner  100  is referred as a low drop-out (LDO) voltage tuner. Under a condition in which the feedback voltage Vf is equal to the input voltage Vref, a current Ip is equal to Vf/Rf 1 , and the output voltage Vout is equal to a product of the current Ip and a sum of the resistors Rf 1  and Rf 2 . Therefore, in the voltage tuner  100 , when the output voltage Vout is being adjusted, only the resistance of the resistor Rf 2  needs to be altered. 
     It should be noted that, the voltage value of the output voltage Vout and the resistances of the resistors Rf 1  and Rf 2  are correlated. In order to ensure that the voltage value of the output voltage Vout is accurate, a layout of resistors Rf 1  and Rf 2  with stable resistances are required for the voltage tuner  100 . Therefore, resistors Rf 1  and Rf 2  with greater widths are needed. On the other hand, in order to reduce the electric energy consumed by the resistors Rf 1  and Rf 2 , these resistors are typically designed to have large resistances. Accordingly, the resistors Rf 1  and Rf 2  also require greater lengths. In other words, the circuit area occupied by the resistors Rf 1  and Rf 2  in the conventional voltage tuner  100  is very large which increases the circuit cost. 
     SUMMARY 
     The invention provides a voltage generator capable of effectively saving the required circuit area and reducing the electric energy consumed. 
     The invention provides a voltage generator, including an operational amplifier, an offset voltage tuner, and an output stage circuit. A first input terminal of the operational amplifier receives an input voltage. The operational amplifier receives and adjusts an offset voltage of the operational amplifier according to a control signal. The offset voltage tuner is coupled to the operational amplifier, and the offset voltage tuner provides the control signal. The output stage circuit is coupled to an output terminal and a second input terminal of the operational amplifier. The output stage circuit generates the output voltage according to a voltage on the output terminal of the operational amplifier, and provides the output voltage to the second input terminal of the operational amplifier. 
     According to an embodiment of the invention, the operational amplifier includes a differential input circuit and a load circuit. The differential input circuit is coupled to a first reference voltage, and the differential input circuit has a first input stage circuit and a second input stage circuit. The conductive resistors of the first and second input stage circuits are adjusted according to the control signal in order to adjust the offset voltage. The load circuit is coupled between the differential input circuit and a second reference voltage, in which a contact of one of the load circuit and the differential input circuit is coupled to the output terminal of the operational amplifier. 
     According to an embodiment of the invention, the first input stage circuit includes a first transistor and at least one first tuning transistor. The first transistor has a first terminal, a second terminal, and a control terminal. The control terminal of the first transistor receives the input voltage, the first terminal of the first transistor is coupled to the load circuit, and the second terminal of the first transistor is coupled to the second reference voltage. The first tuning transistor has a first terminal, a second terminal, and a control terminal. The control terminal of the first tuning transistor receives the control signal, the first terminal of the first tuning transistor is coupled to the first terminal of the first transistor, and the second terminal of the first tuning transistor is coupled to the second terminal of the first transistor. 
     According to an embodiment of the invention, the second input stage circuit includes a second transistor and at least one second tuning transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The control terminal of the second transistor receives the input voltage, the first terminal of the second transistor is coupled to the load circuit, and the second terminal of the second transistor is coupled to the second reference voltage. The second tuning transistor has a first terminal, a second terminal, and a control terminal. The control terminal of the second tuning transistor receives the control signal, the first terminal of the second tuning transistor is coupled to the first terminal of the second transistor, and the second terminal of the second tuning transistor is coupled to the second terminal of the second transistor. 
     According to an embodiment of the invention, the load circuit includes a first resistor and a second resistor, and the first resistor is connected in series between the first input stage circuit and the first reference voltage. The second resistor is connected in series between the second input stage circuit and the first reference voltage. 
     According to an embodiment of the invention, the load circuit includes a first transistor and a second transistor. The first transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor is coupled to the first reference voltage, and the second terminal of the first transistor is coupled to the first input stage circuit. The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the first reference voltage, the second terminal of the second transistor is coupled to the second input stage circuit and the control terminal of the second transistor, and the control terminal of the second transistor is coupled to the control terminal of the first transistor. 
     According to an embodiment of the invention, a channel width to length ratio of the first transistor and/or the second transistor is adjusted according to the control signal. 
     According to an embodiment of the invention, the offset voltage tuner includes a plurality of first and second voltage selectors. The first voltage selectors are coupled to the operational amplifier. The first voltage selectors generate a first control signal in the control signal according to a selection of the second reference voltage or the input voltage. The second voltage selectors are coupled to the operational amplifier. The second voltage selectors generate a second control signal in the control signal according to a selection of the second reference voltage or the output voltage. The first control signal is transmitted to the first input stage circuit, and the second control signal is transmitted to the second input stage circuit. 
     According to an embodiment of the invention, the operational amplifier includes a differential input circuit and a load circuit. The differential input circuit is coupled to a first reference voltage, and the differential input circuit has a first input stage circuit and a second input stage circuit. The load circuit is coupled between the differential input circuit and a second reference voltage. The load circuit respectively provides a first impedance and a second impedance to the first and second input stage circuits. The first and second impedances are respectively adjusted according to the control signal. 
     According to an embodiment of the invention, the load circuit includes a first transistor. The first transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor is coupled to the first reference voltage, and the second terminal of the first transistor is coupled to the first input stage circuit. A channel width to length ratio of the first transistor is adjusted according to the control signal. 
     According to an embodiment of the invention, the load circuit further includes a second transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the first reference voltage, the second terminal of the second transistor is coupled to the second input stage circuit and the control terminal of the second transistor, and the control terminal of the second transistor is coupled to the control terminal of the first transistor. A channel width to length ratio of the second transistor is adjusted according to the control signal. 
     According to an embodiment of the invention, the offset voltage tuner generates the control signal having at least one bit. 
     According to an embodiment of the invention, the operational amplifier is a transconductance amplifier. 
     According to an embodiment of the invention, the output stage circuit includes a first output stage transistor and a second output stage transistor. The first output stage transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the first output stage transistor receives the first reference voltage, the second terminal of the first output stage transistor generates the output voltage, and the control terminal of the first output stage transistor is coupled to the output terminal of the operational amplifier. The second output stage transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second output stage transistor generates the output voltage, the second terminal of the second output stage transistor is coupled to the second reference voltage, and the control terminal of the second output stage transistor receives an offset voltage. 
     In summary, by adjusting the offset voltage of the operational amplifier, embodiments of the invention can adjust the voltage value of the output voltage generated by the voltage generator. Therefore, the voltage generator can avoid the use of a large amount of voltage dividing resistors for voltage division. Moreover, the large layout area to compensate for resistance shift due to resistor manufacturing can be reduced. Accordingly, without affecting the accuracy of the output voltage generated by the voltage generator, embodiments of the invention can effectively save on the circuit cost and also reduce the electric energy consumed by the voltage dividing resistors. 
     Several exemplary embodiments accompanied with figures are described in detail below to further describe the disclosure in details. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings constituting a part of this specification are incorporated herein to provide a further understanding of the disclosure. Here, the drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG. 1  is a circuit diagram of a conventional voltage tuner  100 . 
         FIG. 2  is a schematic view of a voltage generator  200  according to an embodiment of the invention. 
         FIG. 3  is a schematic view of an implementation of an operational amplifier  210  according to an embodiment of the invention. 
         FIG. 4  is a schematic view of an offset voltage tuner  220  according to an embodiment of the invention. 
         FIG. 5  is a schematic view of a voltage generator  500  according to an embodiment of the invention. 
         FIG. 6A  is a schematic view of another implementation of an operational amplifier according to an embodiment of the invention. 
         FIG. 6B  is a schematic view of another implementation of an operational amplifier according to an embodiment of the invention. 
         FIGS. 7A-7C  are schematic views of an impedance adjustment for a load circuit according to an embodiment of the invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     With reference to  FIG. 2 , a schematic view of a voltage generator  200  according to an embodiment of the invention is depicted. The voltage generator  200  includes an operational amplifier  210 , an offset voltage tuner  220 , and an output stage circuit  230 . The operational amplifier  210  has an input terminal I 1  receiving an input voltage Vref, and another input terminal I 2  receiving an output voltage Vout. The operational amplifier  210  receives and adjusts an offset voltage Vos of the operational amplifier according to a control signal CTR. Moreover, an output terminal of the operational amplifier  210  is coupled to the output stage circuit  230 . The operational amplifier  210  may be a transconductance amplifier. 
     The offset voltage tuner  220  is coupled to the operational amplifier  210 . The offset voltage tuner  220  provides the control signal CTR. The control signal CTR may be formed by one or more of digital signals, and the control signal CTR may also be formed by one or more analog voltages. It should be appreciated that the control signal CTR may also be a hybrid signal formed by one or more analog voltages and digital signals. 
     The output stage circuit  230  is coupled to the output terminal and the input terminal I 2  of the operational amplifier  210 . The output stage circuit  230  generates the output voltage Vout according to a voltage on the output terminal of the operational amplifier  210 , and provides the output voltage Vout to the input terminal I 2  of the operational amplifier  210 . 
     During operation of the voltage generator  200 , when the output voltage Vout generated by the voltage generator  200  is adjusted, the offset voltage Vos of the operational amplifier  210  can be adjusted simply through the control signal CTR provided by the offset voltage tuner  220 . Accordingly, the voltage on the output terminal of the operational amplifier  210  is also correspondingly adjusted. That is to say, the output stage circuit  230  generating the output voltage Vout according to the voltage on the output terminal of the operational amplifier  210  can also adjust the voltage value of the generated output voltage Vout. 
     With reference to  FIG. 3 , a schematic view of an implementation of the operational amplifier  210  according to an embodiment of the invention is depicted. The operational amplifier  210  includes a differential input circuit  211  and a load circuit  212 . The differential input circuit  211  has an input stage circuit formed by a transistor M 1  and the tuning transistors Mm 0  and Mm 1 , and another input stage circuit formed by a transistor M 2  and the tuning transistors Mn 0  and Mn 1 . The load circuit  211  includes the resistors R 1  and R 2 . The resistor R 1  is connected in series between the reference voltage Vin and the input stage circuit formed by the transistor M 1  and the tuning transistors Mm 0  and Mm 1 . The resistor R 2  is connected in series between the reference voltage Vin and the input stage circuit formed by the transistor M 2  and the tuning transistors Mn 0  and Mn 1 . Moreover, the operational amplifier  210  further includes a current source Ib, which is connected in series between the ground voltage GND serving as the reference voltage and the input stage circuits. 
     When the offset voltage of the operational amplifier  210  is adjusted, the offset voltage tuner respectively transmits the control signals CTR&lt; 0 &gt;-CTR&lt; 3 &gt; to the control terminals (gates) of the tuning transistors Mm 0 , Mm 1 , Mn 0 , and Mn 1 . In the present embodiment, the control signals CTR&lt; 0 &gt;-CTR&lt; 1 &gt; may be equal to the ground voltage GND or equal to the input voltage Vref, and the control signals CTR&lt; 2 &gt;-CTR&lt; 3 &gt; may be equal to the ground voltage GND or equal to the input voltage Vout. Taking the tuning transistor Mm 0  as an example, when the control signal CTR&lt; 0 &gt; received by the control terminal of the tuning transistor Mm 0  is equal to the ground voltage GND, the tuning transistor Mm 0  is cut off. Moreover, taking the tuning transistor Mn 0  as an example, when the control signal CTR&lt; 2 &gt; received by the control terminal of the tuning transistor Mn 0  is equal to the ground voltage GND, the tuning transistor Mn 0  is cut off. 
     Referring to  FIG. 2  concurrently, in the present embodiment, when the tuning transistors Mm 0 , Mm 1 , Mn 0 , and Mn 1  are all cut off, the output voltage Vout is equal to the input voltage Vin. When the control signals CTR&lt; 1 &gt;-CTR&lt; 3 &gt; are all equal to the ground voltage GND, and the control signal CTR&lt; 0 &gt; is equal to the input voltage Vref, the tuning transistors Mm 1 , Mn 0 , and Mn 1  are cut off, and the output voltage Vout is equal to a sum of the input voltage Vref and an offset voltage Vosm&lt; 0 &gt;. The offset voltage Vosm&lt; 0 &gt; is a voltage difference between a source and a drain of the tuning transistor Mm 0 . When the control signals CTR&lt; 2 &gt;-CTR&lt; 3 &gt; are equal to the ground voltage GND, and the control signals CTR&lt; 0 &gt;-CTR&lt; 1 &gt; are equal to the input voltage Vref, the output voltage Vout is equal to a sum of the input voltage Vref, the offset voltage Vosm&lt; 0 &gt;, and an offset voltage Vosm&lt; 1 &gt; (Vout=Vref+Vosm&lt; 0 &gt;+Vosm&lt; 1 &gt;). The offset voltage Vosm&lt; 1 &gt; is a voltage difference between a source and a drain of the tuning transistor Mm 1 . 
     In comparison, when the control signals CTR&lt; 0 &gt;-CTR&lt; 2 &gt; are equal to the ground voltage GND, and the control signal CTR&lt; 3 &gt; is equal to the output voltage Vout, the output voltage Vout is equal to the input voltage Vref subtracted by the offset voltage Vosn&lt; 0 &gt;. The offset voltage Vosn&lt; 0 &gt; is a voltage difference between a source and a drain of the tuning transistor Mn 0 . When the control signals CTR&lt; 0 &gt;-CTR&lt; 1 &gt; are equal to the ground voltage GND, and the control signals CTR&lt; 2 &gt;-CTR&lt; 3 &gt; are equal to the output voltage Vout, the output voltage Vout is equal to the input voltage Vref subtracted by the offset voltage Vosn&lt; 0 &gt; and an offset voltage Vosn&lt; 1 &gt; (Vout=Vref−Vosn&lt; 0 &gt;−Vosn&lt; 1 &gt;). The offset voltage Vosn&lt; 1 &gt; is a voltage difference between a source and a drain of the tuning transistor Mn 1 . 
     The offset voltages Vsm&lt; 0 &gt;, Vsm&lt; 1 &gt;, Vsn&lt; 0 &gt;, and Vsn&lt; 1 &gt; can be configured by setting the conductive resistors of the tuning transistors Mm 0 , Mm 1 , Mn 0 , and Mn 1 . A designer may set suitable tuning transistors Mm 0 , Mm 1 , Mn 0 , and Mn 1  according to a required adjustable range of the output voltage Vout of the voltage generator  200 . 
     With reference to  FIG. 4 , a schematic view of the offset voltage tuner  220  according to an embodiment of the invention is depicted. The offset voltage tuner  220  includes a plurality of voltage selectors  221 - 224 . The voltage selectors  221  and  222  respectively selects the input voltage Vref or the ground voltage GND according to the select signals m&lt; 0 &gt; and m&lt; 1 &gt; to generate the control signals CTR&lt; 0 &gt; and CTR&lt; 1 &gt;. The voltage selectors  223  and  224  respectively selects the output voltage Vout or the ground voltage GND according to the select signals n&lt; 0 &gt; and n&lt; 1 &gt; to generate the control signals CTR&lt; 2 &gt; and CTR&lt; 3 &gt;. The select signals m&lt; 0 &gt;-m&lt; 1 &gt; and n&lt; 0 &gt;-n&lt; 1 &gt; may be provided by the circuit controlling the voltage generator  200 , or provided by a circuit external to the chip according to the pins of the chip. 
     With reference to  FIG. 5 , a schematic view of a voltage generator  500  according to an embodiment of the invention is depicted. The voltage generator  500  includes an operational amplifier  510 , an offset voltage tuner  520 , and an output stage circuit  530 . The output stage circuit  530  includes an output stage transistor MP and an output stage transistor MN. The output stage transistor MP has a first terminal receiving the reference voltage Vin, a second terminal generating the output voltage Vout, and a control terminal coupled to an output terminal of the operational amplifier  510 . A first terminal of the output stage transistor MN is coupled to the second terminal of the output stage transistor MP to generate the output voltage Vout. A second terminal of the output stage transistor MN is coupled to the ground voltage GND serving as the reference voltage. A control terminal of the output stage transistor MN receives an offset voltage VB. The offset voltage VB is a predetermined voltage set according to an actual requirement by design. 
     It should be noted that, the output stage circuit  530  in the present embodiment do not require voltage dividing resistors to provide the feedback voltage to the operational amplifier  510 . Therefore, the issue of resistors which occupy large areas can be resolved, which drastically reduces the circuit cost of the voltage generator  500 . 
     With reference to  FIG. 6A , a schematic view of another implementation of an operational amplifier according to an embodiment of the invention is depicted. In  FIG. 6A , the operational amplifier  600  includes a load circuit  610 , a differential input circuit  620 , and a current source Ib. The differential input circuit  620  is similar to the differential input circuit  211  embodied in  FIG. 3 , and therefore further elaboration thereof is omitted. It should be noted that, the load circuit  610  is an active load, and the load circuit  610  includes the transistors M 3  and M 4 . The transistor M 3  has a first terminal coupled to the reference voltage Vin, and a second terminal coupled to the differential input circuit  620 . The transistor M 4  has a control terminal coupled to a control terminal of the transistor M 3 , a first terminal coupled to the reference voltage Vin, and a second terminal coupled to the differential input circuit  620  and the control terminal of the transistor M 4 . 
     In the present embodiment, the transistors M 3  and M 4  respectively provide two resistances to the transistors M 1  and M 2 . It should be noted that, when the output voltage Vout is adjusted, besides tuning the differential input circuit  620 , the resistances provided by the transistors M 3  and M 4  can also be tuned to adjust the output voltage Vout. In the present embodiment, the transistors M 3  and M 4  respectively or simultaneously adjust their conductive resistors according to the control signals CTRA 1  and CTRA 2  (e.g., by adjusting the channel width to length ratio of the transistor (W/L)). 
     With reference to  FIG. 6B , a schematic view of another implementation of an operational amplifier according to an embodiment of the invention is depicted. In  FIG. 6B , the differential input circuit  620  does not provide a mechanism to adjust the offset voltage. In other words, in the embodiment of  FIG. 6B , the magnitude of the output voltage Vout can be determined solely by adjusting the impedances provided by the transistors M 3  and M 4 . 
     With reference to  FIGS. 7A-7C , schematic views of an impedance adjustment for a load circuit according to an embodiment of the invention are depicted. In  FIG. 7A , a load circuit  700  includes the transistors M 3 , M 4 , and M 31 -M 33 , and the switches SW 11 -SW 13 . The transistors M 31 -M 33  have control terminals (gates) coupled to a control terminal of the transistor M 3 , sources coupled to a source of the transistor M 3  through the switches SW 11 -SW 13 , and drains commonly coupled to a drain of the transistor M 3 . The switches SW 11 -SW 13  are respectively controlled by the control signals CTRA 11 -CTRA 13  to conduct or break off. As the number of conducting switches SW 11 -SW 13  increases, the equivalent channel width to length ratios of the transistor M 3  and the transistors M 31 -M 33  become larger, and the equivalent conductive impedances provided by the transistor M 3  and the transistors M 31 -M 33  are lowered. As the number of conducting switches SW 11 -SW 13  decreases, the equivalent channel width to length ratios of the transistor M 3  and the transistors M 31 -M 33  become smaller, and the equivalent conductive impedances provided by the transistor M 3  and the transistors M 31 -M 33  are increased. 
     In  FIG. 7B , the load circuit  700  includes the transistors M 3 , M 4 , and M 41 -M 43 , and the switches SW 21 -SW 23 . The transistors M 41 -M 43  have control terminals (gates) coupled to a control terminal of the transistor M 4 , sources respectively bridged to a source of the transistor M 4  through the switches SW 21 -SW 23 , and drains coupled to a drain of the transistor M 4 . The switches SW 21 -SW 23  are respectively controlled by the control signals CTRA 21 -CTRA 23  to conduct or break off. As the number of conducting switches SW 21 -SW 23  increases, the equivalent channel width to length ratios of the transistor M 4  and the transistors M 41 -M 43  become larger, and the equivalent conductive impedances provided by the transistor M 4  and the transistors M 41 -M 43  are lowered. By comparison, as the number of conducting switches SW 21 -SW 23  decreases, the equivalent channel width to length ratios of the transistor M 4  and the transistors M 41 -M 43  become smaller, and the equivalent conductive impedances provided by the transistor M 4  and the transistors M 41 -M 43  are increased. 
       FIG. 7C  is a combination of the embodiments shown in  FIGS. 7A and 7B . In other words, the equivalent width to length ratios of the transistor M 3  and the transistors M 31 -M 33  and the equivalent width to length ratios of the transistor M 4  and the transistors M 41 -M 43  can be simultaneously adjusted, respectively, such that the offset voltage of the operational amplifier can be more flexibly adjusted. 
     It should be noted that, the control signals CTRA 11 -CTRA 13  and CTRA 21 -CTRA 23  in  FIGS. 7A-7C  may be digital logic signals. 
     In view of the foregoing, by adjusting the offset voltage of the operational amplifier, embodiments of the invention can adjust the voltage value of the output voltage generated by the voltage generator. No variable resistors need to be constructed in the invention to serve as the basis for the adjustments. Accordingly, the voltage generator do not require large area resistors, and circuit cost can be saved effectively. 
     Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.