Patent Publication Number: US-6909140-B2

Title: Flash memory with protruded floating gate

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a division of 10/158,927 filed Jun. 3, 2002. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a flash memory, and more particularly, to a flash memory with a protruded floating gate. 
     2. Description of the Prior Art 
     High-density nonvolatile memory devices have been receiving much attention for application in many fields. One of the most important factors is the low cost of the reduced size of each memory cell. However, it is very difficult to shrink the cell size in the fabrication of nonvolatile memory cells when the conventional local oxidation (LOCOS) isolation technique is used. The isolation structure formed by this technique has a very large dimension and thus limits the miniaturization of the memory cells. 
     Another isolation technique called shallow trench isolation (STI) has been introduced to the fabrication of nonvolatile memory devices to reduce the cell size. The conventional field oxides are replaced by STI structures so that the device integration can be effectively improved. However, as component dimensions continue to shrink, the surface area of floating gates also shrinks. This leads directly to a decrease in capacitance of the effective capacitor formed between the floating gate layer and the control gate layer. This decrease in effective capacitance results in a reduction of the capacitive coupling ratio, which is a parameter that describes the coupling to floating gate of the voltage applied to control gate. The poorly-coupled voltage to floating gate limits the programming and accessing speed characteristics of the memory device. 
     The capacitive coupling ratio Cp is defined by: 
       Cp   =     Ccf     Ccf   +   Cfs           
         where Ccf is capacitance between the control gate and the floating gate; and Cfs is capacitance between the floating gate and the semiconductor substrate.       

     In order to improve programming and accessing speeds in nonvolatile memories, many attempts have been made to increase the coupling ratio. It can be understood from the above equation that when the capacitance Ccf between the control gate and the floating gate increases, the coupling ratio Cp increases. Therefore, the coupling ratio Cp is generally increased by increasing the capacitor area between the floating gate and control gate, which increases the capacitance Ccf, and therefore the coupling ratio Cp. For example, U.S. Pat. No. 6,171,909 discloses a method for forming a stacked gate of a flash memory cell. The coupling ratio of the stacked gate is increased by forming a conductive spacer. The conductive spacer, which is a portion of the floating gate, increases the capacitor area between the floating gate and control gate. 
     As shown in  FIG. 1   a , a conventional flash memory is comprised of a substrate  101 , a gate oxide  104  forming on the substrate  101 , a floating gate  105  forming on the gate oxide  104 , a inter-gate oxide  106  forming on the floating gate  105 , and a control gate  107  forming on the inter-gate oxide  106 , wherein the substrate  101  has a source  102  and a drain  103 . Traditionally, a high voltage is applied to the control gate  107  of the flash memory, and the electrons from the source  102  are injected into the floating gate  105  through the gate oxide  104 . This programs the flash memory, e.g. writing information the flash memory, as shown in  FIG. 1   a.    
     A erase is performed when a low voltage or no voltage is applied to the control gate  107  of the flash memory, and a high voltage is applied to the source  102 , so that the electrons are injected into the source  102  through the gate oxide  104  thus erasing the flash memory. 
     When the flash memory is both programmed and erased, the electrons tunnel through the gate oxide  104 . The gate oxide  104  is a thin layer, so that the gate oxide  104  is damaged after repeating several programming and erasing operations. 
     SUMMARY OF THE INVENTION 
     In the present invention, a nonvolatile semiconductor memory device with an increased coupling ratio is disclosed. This is accomplished by providing a reduced size floating gate which reduces the capacitance Cfs between the floating gate and the semiconductor substrate. The effect is the same as increasing the capacitance Ccf between the control gate and the floating gate. 
     Accordingly, the object of the present invention is to provide a flash memory with protruded floating gate and method for forming the same. This invention provides a novel way of erasing, and increases the access rate by improving the capacitive coupling ratio of the flash memory by increasing the surface area. 
     The present invention provides a method for forming a flash memory with a protruded floating gate. At first, a substrate is provided. An isolation area and a plurality of patterned conductive layers are sequentially formed on the substrate. The isolation area protrudes from the upper surface of the substrate to isolate the patterned conductive layers. A plurality of photo resist layer is formed on the patterned conductive layer. The surface areas of the photo resist layer are smaller than those of the patterned conductive layers. The patterned conductive layers are isotropically etched to form a protruded floating gate. The photo resist layer are removed. Then, an insulator and a control gate are sequentially formed on the substrate. 
     The present invention also provides a flash memory with protruded floating gate comprising a substrate, a plurality of protruded floating gates, an insulator, and a control gate. The substrate has an isolation area. The plurality of protruded floating gates is formed on the substrate and isolated by the isolation area. The insulator is formed on the surfaces of the substrate and the floating gate. The control gate is formed on the insulator. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description given herein and the accompanying drawings, given by way of illustration only and thus not intended to be limited of the present invention. 
         FIG. 1   a  depicts a conventional programming operation of the flash memory; 
         FIG. 1   b  depicts a conventional erasing operation of the flash memory; 
         FIGS. 2   a  to  2   d  depict the method of forming the flash memory with protruded floating gate of the present invention; 
         FIG. 3   a  depicts the programming operation of the flash memory of the present invention; 
         FIG. 3   b  depicts the erasing operation of the flash memory of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A detail description of the method of forming the flash memory with protruded floating gate of the present invention is given hereafter with reference to  FIGS. 2   a  to  2   b.    
     In  FIG. 2   a , a substrate  201  is provided. The substrate  201  has an isolation area  202 . A plurality of gate oxide  203  is formed on the substrate  201 . A plurality of patterned conductive layers  204  is formed on the gate oxide  203 , and the isolation area  202  protrudes from the upper surface of the substrate  201  to isolate the patterned conductive layers  204 . The isolation area  202  may be a Shallow Trench Isolation (STI). 
     With reference to  FIG. 2   b , the photo resist  205  is formed on the patterned conductive layers  204  after the patterned conductive layers  204  are formed on the substrate  201 . The surface area of the photo resist layer  205  is smaller than those of the patterned conductive layers  204 . 
     As shown in  FIG. 2   c , the patterned conductive layers  204  are isotropicaly etched with etchant using the photo resist layer  205  as a mask, and the photo resist layer  205  is removed to form the patterned conductive layers  204  is to a protruded floating gate  204   a . The protruded floating gate  204   a  is tip-shaped or plateau-shaped. 
     Then, as shown in  FIG. 2   d , an insulator  206  and a control gate  207  are sequentially formed on the substrate  201 , wherein the protruded floating gate  204   a  and insulation layer  202  are on the substrate  201 . For example, the insulator  206  is inter-gate oxide. Thereby, the flash memory with the protruded floating gate is formed. 
     Next, a detail description of the programming operation of a flash memory with a protruded floating gate of the present invention is given hereafter with reference to  FIG. 3   a.    
     As shown in  FIG. 3   a , a structure of the flash memory with a protruded floating gate of the present invention is comprised of a substrate  201 , a gate oxide  203  forming on the substrate  201 , a protruded floating gate  204   a  forming on the gate oxide  203 , a inter-gate oxide  206  forming on the protruded floating gate  204   a , and a control gate  207  forming on the inter-gate oxide. The substrate  201  has a source  201   a  and a drain  201   b.    
     When a high voltage is applied to the control gate  207  of the flash memory as shown in  FIG. 3   a  of the present invention, the electrons from the source  201   a  are injected into the protruded floating gate  204   a  through the gate oxide  203 , thereby programming the flash memory, e.g. information is written into the flash memory. 
     When a low voltage or no voltage is applied to the control gate  207  of the flash memory, and a high voltage is applied to the source  201   a , the electrons are injected into the control gate  207  through the inter-gate oxide  206 , thereby erasing the flash memory. 
     The protruded floating gate  204   a  is a tip-like or plateau-like, that is, the height of the center is higher than the edge of the floating gate  204   a . The floating gate  204   a  comprises a top portion T and a base portion B. The base portion B is connected to the gate oxide  203 , the top portion T is formed on the base portion B and protrude therefrom. 
     Because the electric field is more concentrated in the tip-shaped floating gate or the plateau-shaped floating gate, the electrons tunnel to the control gate  207  through the protruded floating  204   a , and the protruded floating gate  204   a  is returned to the original state, as shown in  FIG. 3   b.    
     While the present invention is described by preferred embodiments, it should be understood that the invention is not limited to these embodiments in any way. On the contrary, it is intended to cover all the modifications and arrangements as they would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be interpreted in the broadest sense so as to encompass all the modifications and arrangements.