Patent Publication Number: US-7917563-B1

Title: Read channel processor

Description:
BACKGROUND OF THE INVENTION 
     Adaptive equalization is used in a variety of applications, including in storage devices, such as magnetic or optical disk drives. The calibration of a typical equalization system can require a significant amount of resources during manufacture and test. For example, selecting an optimal target filter may involve batch processing of numerous potential target filter coefficients during manufacture. In addition, having an individual target for each disk is impractical. There is therefore a need for a more efficient method of target selection. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings. 
         FIG. 1  is a block diagram illustrating an embodiment of a data storage system. 
         FIG. 2  is a block diagram illustrating an embodiment of a system for determining an error. 
         FIG. 3  is a flowchart illustrating an embodiment of a process for recursively determining filter coefficients. 
         FIG. 4  is a block diagram illustrating an embodiment of a timing loop with a predetermined target filter. 
         FIG. 5  is a block diagram illustrating an embodiment of a timing loop without a predetermined target filter. 
         FIG. 6  is a diagram illustrating an example of a timing loop. 
         FIG. 7  is a diagram illustrating an example of sampling a recording signal. 
         FIG. 8  is a block diagram illustrating an example of a timing gradient. 
         FIG. 9  is a plot illustrating an example of the DFE and Viterbi detector sensitivity to incorrect sampling phase. 
         FIGS. 10A-10C  are s-curves illustrating examples of the mean and variance of the timing error detector for each of the three modes of operation. 
         FIG. 10D  illustrates an example of the timing function&#39;s sensitivity to gain error for the second mode. 
     
    
    
     DETAILED DESCRIPTION 
     The invention can be implemented in numerous ways, including as a process, an apparatus, a system, a composition of matter, a computer readable medium such as a computer readable storage medium or a computer network wherein program instructions are sent over optical or electronic communication links. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. A component such as a processor or a memory described as being configured to perform a task includes both a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. 
     A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured. 
       FIG. 1  is a block diagram illustrating an embodiment of a data storage system. In this example, data a(n) is provided to head or disk  102 . The output of disk heads  102  is provided to preamplifier  104 . The output of preamplifier  104  is provided to a read channel. Data y(n) is received from the read channel and provided to variable gain amplifier (VGA)  106 . The output of VGA  106  is provided to analog filter  108 . The output of analog filter  108  is provided to analog to digital converter (ADC)  110 . The output of ADC  110  is provided to finite impulse response (FIR) filter  112 . FIR filter  112  is used to perform equalization of y(n). Output z(n) of FIR filter  112  is provided to Viterbi Detector  114 . 
     In the example shown,
 
 z ( n )= c ( n )* y ( n )
 
     As used herein, the symbol * refers to convolution. Thus, 
     
       
         
           
             
               z 
               ⁡ 
               
                 ( 
                 n 
                 ) 
               
             
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     where N is the number of taps in FIR filter  112  and {c i } are the coefficients of FIR filter  112 . {c i } may be chosen such that an error is minimized, as more fully described below. 
       FIG. 2  is a block diagram illustrating an embodiment of a system for determining an error. In this example, received sequence y(n) is provided to FIR filter  202  to produce z(n). Known sequence a(n) is provided to target filter  204  to produce x(n). The output of target filter  204  x(n) is subtracted from the output of FIR filter  202  z(n) to produce error sequence e(n). In this example,
 
 e ( n )= z ( n )− x ( n )
 
     For example, target filter  204  may have coefficients T 1 , T 2 , T 3 , and T 4  associated with filter 1+T 1 D+T 2 D 2 T 3 D 3 +T 4 D 4 . T 1 , T 2 , T 3 , and T 4  are programmable and may be different for different physical media. T 1 , T 2 , T 3 , and T 4  are selected to optimize performance for a given head. For example, T 1 , T 2 , T 3 , and T 4  may be selected to optimize bit error rate (BER) performance for a given head. T 1 , T 2 , T 3 , and T 4  may be selected to shape the output to have a particular spectrum. In various embodiments, target filter  204  can have any number of coefficients. 
     For a given target, target filter  204  is used to train the coefficients of FIR filter  202 . This may be performed by inputting a known sequence a(n) and trying different coefficients of FIR filter  202  until e(n) is sufficiently small. 
     In some embodiments, the coefficients of the target filter are first determined. Then the coefficients of the FIR filter may be computed. In some embodiments, the coefficients of the FIR filter and target filter may be jointly computed on-chip. A recursive optimization method, such as Least Mean Squares (LMS), may be used to jointly compute the coefficients of the FIR filter and target filter on-chip. In this example,
 
 e ( n )= z ( n )− x ( n )
 
     where 
     
       
         
           
             
               
                 
                   
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     {c i } and {T i } may be chosen by minimizing Σe n   2 , subject to one of the following constraints:
 
T 0 =1  (1)
 
or:
 
ΣT i   2 =1  (2)
 
     N is the number of taps in FIR filter  202  and {c i } are the coefficients of FIR filter  202 . M is the number of taps in target filter  204  and {T i } are the coefficients of target filter  204 . The error is e(n). 
     The following updates can be computed:
 
Δ c   i   =e ( n ) y ( n−i )  Equation 1A
 
Δ T   i   =e ( n ) a ( n−i )  Equation 1B
 
     For each iteration, Δc i  and ΔT i  are the amounts that c i  and T i  are updated, respectfully. Using the above updates with a recursive optimization method, such as LMS, a joint optimization of target and FIR coefficients for an individual head or disk can be achieved. The amount that T i  changes during each iteration is proportional to the value of the error. The amount that c i  changes during each iteration is proportional to the value of the error. 
       FIG. 3  is a flowchart illustrating an embodiment of a process for recursively determining filter coefficients. In this example, at  302 , a target output of a target function is determined. For example, output x(n) of target filter  204  is determined. At  304 , a filter output of a programmable filter is determined. For example, filter output z(n) of programmable FIR filter  202  is determined. At  306 , the target output and filter output are compared. For example, the difference between z(n) and x(n) is computed. At  308 , it is determined whether an error criterion is satisfied. For example, when Σe n   2  is less than a predetermined value, the error criterion may be deemed satisfied. If the error criterion is satisfied, the process ends at  310 . If the error criterion is not satisfied, then the target function coefficients and programmable filter coefficients are updated. For example, the programmable filter coefficient may be updated according to Equation 1A. The target function coefficients may be updated according to Equation 1B. The process returns to  302 . 
     In some embodiments, this process is performed during manufacturing. In some embodiments, this process is performed online or post-manufacturing. For example, it may be determined that the performance of the storage device has deteriorated. An erasure or error condition could be detected and a recalibration performed. In some embodiments, a user interface could be used to request that a recalibration be performed. 
     Timing Loop 
       FIG. 4  is a block diagram illustrating an embodiment of a timing loop with a predetermined target filter. In this example, data is received from a read channel and provided to variable gain amplifier (VGA)  406 . The output of VGA  406  is provided to analog filter  408 . The output of analog filter  408  is provided to analog to digital converter (ADC)  410 . The output of ADC  410  is provided to finite impulse response (FIR) filter  412 . FIR filter  412  is used to perform equalization. The output of FIR filter  412  is provided to Viterbi Detector  414 . 
     As shown, the timing loop includes timing gradient  416  and loop filter  418 . The output of Viterbi Detector  414  is provided to timing gradient  416 . As used herein, a timing gradient may also be referred to as a timing error detector (TED). The output of FIR filter  412  is provided to timing gradient  416  via path  420 . Timing gradient  416  estimates a sampling phase error. The output of timing gradient  416  is provided to loop filter  418 . Loop filter  418  averages the values provided by timing gradient  416 . The output of loop filter  418  is provided to ADC  410  to adjust the sampling phase of ADC  410 . 
     In this example, a target filter is predetermined and FIR filter  412  is trained to match the target. FIR filter  412  is constrained to have a fixed time delay response. In other words, as the FIR varies, the phase response is constrained such that the time delay response is fixed (e.g., near 0 frequency). If FIR filter  412  does not have a fixed time delay response, it is capable of canceling out the effect of the timing loop. 
       FIG. 5  is a block diagram illustrating an embodiment of a timing loop without a predetermined target filter. In this example, data is received from a read channel and provided to variable gain amplifier (VGA)  406 . The output of VGA  406  is provided to analog filter  408 . The output of analog filter  408  is provided to analog to digital converter (ADC)  410 . The output of ADC  410  is provided to finite impulse response (FIR) filter  412 . FIR filter  412  is used to perform equalization. The output of FIR filter  412  is provided to Viterbi Detector  414 . 
     As shown, the timing loop includes timing gradient  416  and loop filter  418 . The output of Viterbi Detector  414  is provided to timing gradient  416 . The output of ADC  410  is provided to timing gradient  416  via path  502 . Timing gradient  416  estimates a sampling phase error. The output of timing gradient  416  is provided to loop filter  418 . Loop filter  418  averages the values provided by timing gradient  416 . The output of loop filter  418  is provided to ADC  410  to adjust the sampling phase of ADC  410 . 
     In this example, the timing gradient is decoupled from FIR filter  412 . Thus, as the target is optimized and FIR filter  412  is trained to match the target, the timing gradient is not affected. Phase error is not introduced to timing gradient  416  by FIR filter  412 . 
     In some embodiments, a decision feedback equalizer (DFE) provides decisions to timing gradient  416 . 
       FIG. 6  is a diagram illustrating an example of a timing loop. In this example, the timing loop is a decision-directed loop which drives an ADC sampling clock to a known signal phase. In some embodiments, it is active only during tracking and is driven by the ADC output and tentative data decisions. During acquisition, a frequency accumulator in the loop filter is effectively set to zero and ADC samples the timing loop open-loop. At the end of acquisition, the zero phase and frequency restart (ZPFR) estimation block initializes the loop filter with the estimated phase and frequency errors. 
     The timing loop may be implemented in various ways. In this example, the timing loop operates on a 4T clock. A change of 1 DAC LSB causes a (1/64)T VCO  change in sampling phase, where T VCO  is a clock period. The timing DAC uses 6-bit unsigned signal representation. 
     The timing loop may be driven by either the DFE decisions or early Viterbi decisions. For example, the early Viterbi decisions may use a truncated path memory of length  6 .  FIG. 9  shows the sensitivity of the DFE and Viterbi detector to incorrect sampling phase, as more fully described below. 
     In some embodiments, the timing error detector has three modes of operation for a magnetic recording channel: 
     1. Longitudinal Recording—Peak sampling of preamble (LP) 
     2. Perpendicular Recording—Side sampling of preamble (PS) 
     3. Perpendicular Recording—Peak sampling of preamble (PP) 
     For example, a switch or other input to the device could be used to identify which mode of operation to use. 
       FIG. 7  is a diagram illustrating an example of sampling a recording signal. A known preamble is used during phase acquisition. In this example, the preamble is a 4T sinewave. In other words, one period of the sinewave is four bit samples wide. Two types of sampling are shown. Peak sampling is indicated by the “O”s, and side sampling is indicated by the “X”s. 
     Different sampling phases may be used with different channels. To improve performance, a sampling phase appropriate for the channel may be chosen. For example, for perpendicular recording, side sampling of the preamble may be preferable to peak sampling. 
     In some embodiments, side sampling of a perpendicular recording signal yields improved results. The longitudinal channel includes a differentiator, such that the read head responds to changes in the signal. The differentiator introduces a 90 degree phase shift. Selecting a sampling phase determined such that the sampling would occur at the peak of a sine wave of period four times the bit period may be preferable for a longitudinal recording channel. This would mean that a sine wave at the Nyquist frequency (of period two times the bit period) would be sampled at its peaks. 
     In the case of a perpendicular recording channel, selecting a sampling phase determined such that the sampling would occur substantially at the side of a sine wave of period four times the bit period may be preferable. This would mean that a sine wave at the Nyquist frequency would be sampled substantially at its peaks. 
       FIG. 8  is a block diagram illustrating an example of a timing gradient. For example, timing gradient  416  may be implemented in this way. In this example, â is provided as input to channel model  802 . â is a decision from a DFE or Viterbi detector, such as Viterbi detector  414 . Channel model  802  has a channel response ĥ. In some embodiments, channel model  802  is optional. ĥ is an estimate of the channel response of the system between the input and the output of the ADC, including the write head, read channel, and analog filter. The output of channel model  802  is ŷ. ŷ is an estimate of the ADC output when â is input to the channel. Channel model  802  may be implemented as a lookup table, as more fully described below. 
     In some embodiments, analog filter  408  can be adjusted so that it equalizes to what the lookup table expects. This may improve performance of the system. 
     â is also provided as input to slope  804 . Given an ADC output of â, slope  804  is the slope of a curve of ADC output versus phase, when the ADC output is â. For example, the slope of the lower curve in  FIG. 10A  is the inverse of slope  804 . Slope  804  may be implemented as a lookup table, as more fully described below. 
     The difference between the actual ADC output y and ŷ is determined and multiplied by the output of slope  804  to produce the phase offset τ. 
     The timing gradient may be configured as shown in  FIG. 4  or may be configured as shown in  FIG. 5 . In the case of  FIG. 4 , an estimated FIR output {circumflex over (z)} is determined instead of ŷ and the difference z−{circumflex over (z)} is determined instead of y−ŷ. Channel response ĥ accounts for FIR filter  412  and slope  804  is the slope of a curve of FIR output versus phase. 
     Slope  804  may be determined as follows. 
     Consider the signal
 
 y ( t )= ŷ ( t )+ n ( t ),
 
     where ŷ(t) is the noiseless received signal and n(t) is the noise. y(t) is sampled at fixed intervals of T (one bit period) and with phase φ:
 
 y[i]=y ( iT +φ).
 
 ŷ[i]=ŷ ( iT +φ).
 
 n[i]=n ( iT +φ).
 
     A sampling phase error τ introduces a signal error
 
 e ( i ;τ)= y ( iT +φ+τ)− ŷ[i],  
 
     which has energy (squared error) gradient 
     
       
         
           
             
               
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     Given tentative decisions â[i], this gradient may be computed and used to drive the timing loop to a τ (in this case 0) that minimizes the mean squared error (MSE) E i [e 2 (i; τ)]. The variance of the phase estimation error may be lowered using a zero-forcing gradient 
     
       
         
           
             
               
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     The slope 
               [       δ   ⁢       y   ^     ⁡     (   t   )         δτ     ]       t   =       i   ⁢           ⁢   T     +   ϕ             
may be computed using the discrete derivative
 
     
       
         
           
             
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     In some embodiments, the slope may be pre-computed as a function of â[i]. A slope look-up table (SLT) may be used in the timing loop. 
     In the following examples, the channel model uses a fixed degree 5 polynomial to approximate the combination of a hard drive channel and continuous time filter (CTF). The CTF was assumed to have a 12 dB boost and F c =0.25F s . The hard disk channel (HDC) is modeled as 
     1. Windowed Lorenzian with PW 50 /T=3 for longitudinal recording mode. 
     2. Gaussian (pulse response) with PW 50 /T=2 for perpendicular recording modes. 
     The gain of the channel model is such that the response to a 4T sinewave has amplitude  16 . This results in the following channel responses:
 
   ŷ = ĥ     MODE   {circle around (x)} â   , where    â ε{− 1,1} N  
         1.  ĥ   LP =[4, 4, −4, −4]   2.  ĥ   PS =[−1.68, 2.57, 7.96, 2.57, −1.68]   3.  ĥ   PP =[−0.63, 7.37, 7.37, −0.63]       

     In this example, 4, 5, and 5 samples are used for the case of longitudinal peak ( ĥ   LP ), perpendicular side ( ĥ   PS ), and perpendicular peak ( ĥ   PP ) sampling, respectively. In various embodiments, any number of samples may be used. 
     The timing gradient functions for each mode are
         1. s LP =0.5*[1, −1, −1, 1]   2. s LP =0.5*[1, 2, 0−2, −1]   3. s PP =0.5*[1, 1, −1, −1]       

     The hardware lookup tables are formed by rounding the channel outputs and slope to integers and saturating the slopes to −2/+2. 
     The longitudinal, peak sampling lookup tables are 
     
       
         
           
               
             
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     For example, if the last four decisions â(i), â(i−1), â(i−2), â(i−3) are 0, 0, 0, and 1, respectively, then ŷ (the output of filter  802  with channel response ĥ) is −15. The slope s (the output of slope  804 ) is −1. If the actual ADC output y is −10, then the phase offset τ is s(y−ŷ)=−1(−10−−15)=−5. 
     The perpendicular, peak sampling lookup tables are 
     
       
         
         
             
             
         
       
     
     The perpendicular, side sampling lookup tables are 
     
       
         
           
               
             
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               ] 
             
           
         
       
     
     Loop filter  418  averages the estimated phase errors provided by the timing gradient. In some embodiments, loop filter  418  includes a first and second order accumulator in series having gains of K p  and K f , respectively. The timing loop bandwidth for various values of K p  and K f  is as follows. 
     
       
         
         
             
             
         
       
     
     The timing loop damping factor for various values of K p  and K f  is as follows. 
     
       
         
         
             
             
         
       
     
       FIG. 9  is a plot illustrating an example of the DFE and Viterbi detector sensitivity to incorrect sampling phase. The Viterbi performance is shown using decisions tapped off after a traceback of 4T and 6T. It can be seen that under these operating conditions the Viterbi with a path memory truncation of 6 can sustain +−25% T mis-sampling while maintaining &lt;1e−2 BER, which should be sufficient to keep the timing loop locked. 
       FIGS. 10A-10C  are s-curves illustrating examples of the mean and variance of the timing error detector for each of the three modes of operation. The s-curves were computed using DFE decisions. For example,  FIG. 10A  is obtained by holding the timing loop open and inputting signals with various phase offsets (shown as a fraction of a period T). As shown, the mean timing error detector output (the lower curve) is substantially linear with the phase offset. However, the standard deviation (the upper curve) increases for larger phase offset. 
       FIG. 10D  illustrates an example of the timing function&#39;s sensitivity to gain error for the second mode. As shown, the timing function&#39;s sensitivity to gain error is small. 
     Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.