Patent Publication Number: US-9839064-B2

Title: Sensor data collecting device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-081203, filed on Apr. 10, 2015; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a sensor data collecting device that is connectable to a plurality of sensors. 
     BACKGROUND 
     In a processor system executing acquisition of data of a plurality of sensors, in order to reduce power consumption, a processor is in a sleep state when the acquisition of data is not executed. 
     In such a processor system, in a case where data generation periods of the plurality of sensors are different from each other, there is a technique of causing the processor to transit from the sleep state to an active state when data of each sensor can be acquired. According to such a technique, the state transition of the processor frequently occurs, and power consumption according to the state transition increases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram that illustrates a processor system according to a first embodiment; 
         FIG. 2  is a diagram that illustrates a management table according to the first embodiment; 
         FIG. 3A  is a timing diagram that illustrates the operations of a sensor and a processor of a comparative example, and  FIG. 3B  is a timing diagram that illustrates the operations of a sensor and a processor according to first to third embodiments; 
         FIG. 4  is a flowchart that illustrates the operation sequence of an application program according to the first embodiment; 
         FIG. 5  is a flowchart that illustrates a management table registering routine according to the first embodiment; 
         FIG. 6  is a flowchart that illustrates a wakeup trigger setting routine according to the first embodiment; 
         FIG. 7  is a flowchart that illustrates the operation sequence of an interrupt handler according to the first embodiment; 
         FIG. 8  is a block diagram that illustrates a processor system according to a second embodiment; 
         FIG. 9  is a diagram that illustrates a management table according to the second embodiment; 
         FIG. 10  is a flowchart that illustrates the operation sequence of an application program according to the second embodiment; 
         FIG. 11  is a flowchart that illustrates a management table registering routine according to the second embodiment; 
         FIG. 12  is a flowchart that illustrates the operation sequence of an interrupt handler according to the second embodiment; 
         FIG. 13  is a flowchart that illustrates an internal timer synchronizing routine according to second to sixth embodiments; 
         FIG. 14  is a flowchart that illustrates a wakeup trigger setting routine according to the second embodiment; 
         FIG. 15  is a block diagram that illustrates a processor system according to a third embodiment; 
         FIG. 16  is a diagram that illustrates a management table according to the third embodiment; 
         FIG. 17  is a flowchart that illustrates the operation sequence of an application program according to the third embodiment; 
         FIG. 18  is a flowchart that illustrates a management table registering routine according to the third embodiment; 
         FIG. 19  is a flowchart that illustrates the operation sequence of an interrupt handler according to the third embodiment; 
         FIG. 20  is a flowchart that illustrates a wakeup trigger setting routine according to the third embodiment; 
         FIG. 21  is a timing diagram that illustrates the operations of sensors and a processor according to a comparative example; 
         FIG. 22  is a block diagram that illustrates a processor system according to a fourth embodiment; 
         FIG. 23  is a diagram that illustrates a management table according to fourth and fifth embodiments; 
         FIG. 24  is a timing diagram that illustrates the operations of a sensor and a processor according to fourth to sixth embodiments; 
         FIG. 25  is a flowchart that illustrates the operation sequence of an application program according to the fourth embodiment; 
         FIG. 26  is a flowchart that illustrates a management table registering routine according to the fourth embodiment; 
         FIG. 27  is a flowchart that illustrates the operation sequence of an interrupt handler according to the fourth embodiment; 
         FIG. 28  is a flowchart that illustrates a wakeup trigger setting routine according to the fourth embodiment; 
         FIG. 29  is a block diagram that illustrates a processor system according to a fifth embodiment; 
         FIG. 30  is a flowchart that illustrates the operation sequence of an application program according to the fifth embodiment; 
         FIG. 31  is a flowchart that illustrates the operation sequence of an interrupt handler according to the fifth embodiment; 
         FIG. 32  is a flowchart that illustrates a wakeup trigger setting routine according to the fifth embodiment; 
         FIG. 33  is a block diagram that illustrates a processor system according to a sixth embodiment; 
         FIG. 34  is a diagram that illustrates a management table according to the sixth embodiment; 
         FIG. 35  is a flowchart that illustrates the operation sequence of an application program according to the sixth embodiment; 
         FIG. 36  is a flowchart that illustrates a management table registering routine according to the sixth embodiment; 
         FIG. 37  is a flowchart that illustrates the operation sequence of an interrupt handler according to the sixth embodiment; 
         FIG. 38  is a flowchart that illustrates a wakeup trigger setting routine according to the sixth embodiment; 
         FIG. 39  is a timing diagram that illustrates the process according to the fourth embodiment in a case where a jitter is present; 
         FIG. 40  is a timing diagram that illustrates a seventh embodiment; 
         FIG. 41  is a flowchart that illustrates the operation sequence of an application program according to the seventh embodiment; 
         FIG. 42  is a flowchart that illustrates a management table registering routine according to the seventh embodiment; 
         FIG. 43  is a flowchart that illustrates a wakeup trigger setting routine according to the seventh embodiment; and 
         FIG. 44  is a timing diagram that illustrates the seventh embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a sensor data collecting device is connectable to a plurality of sensors. The plurality of sensors generate sensed data at a plurality of different data generation periods. The sensor data collecting device includes a first circuit and a controller. The controller has a first state and a second state and acquires data of one or a plurality of sensors in the second state. The first circuit includes a first register and causes the controller to transit from the first state to the second state based on a register value of the first register. The controller sets the first register based on a minimal data generation period among the plurality of data generation periods. 
     Exemplary embodiments of a sensor data collecting device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. 
     First Embodiment 
       FIG. 1  is a functional block diagram that illustrates a processor system  100  as a sensor data collecting device according to a first embodiment. The processor system  100  is connectable to a plurality of sensors A to C. In the case illustrated in  FIG. 1 , while three sensors are illustrated, the number of sensors may be an arbitrary number of two or more. The processor system  100  collects data detected by the sensors A to C. The processor system  100  includes: an interrupt controller (hereinafter, referred to as an INTC)  10 ; a power management unit (hereinafter, referred to as a PMU)  20 ; a processor  30 ; and a memory  40 . The processor  30  configures a controller of a sensor data collecting device. 
     The processor  30  executes a plurality of programs loaded into the memory  40 . When an interrupt request is received from the INTC  10 , the processor  30  executes an interrupt handler INTHL 1  that is software used for processing an interrupt. The processor  30  has two operation states. A first operation state has low power consumption and is a sleep state in which the process relating to the acquisition of sensor data is not executed. A second operation state has power consumption higher than that of the sleep state and is an active state in which the process relating to acquisition of sensor data is executed. A predetermined time is required for a transition between the active state and the sleep state. During the transition, power (that is the same as that of the active state or higher) higher than that of the sleep state is consumed. A certain amount of power is consumed during the transition. It is higher than that of the sleep state and can be the same as that of the active state or higher. Here, a transition of the processor  30  from the sleep state to the active state will be referred to as “wakeup”. 
     Each of the sensors A to C executes a sensing operation at a predetermined period by an application program AP 1 . When sensed sensor data can be acquired by the processor system  100 , each of the sensors A to C issues an interrupt request to the INTC  10 . In other words, each of the sensors A to C generates sensed data at a predetermined data generation period and issues an interrupt request to the INTC  10  when the data is generated. The data generation periods of the sensors A to C are different from each other. Sensor IDs that are individually identifiable are assigned to the sensors A to C. Here, the ID of the sensor A is set to “0”, the ID of the sensor B is set to “1”, and the ID of the sensor C is set to “2”. 
     The PMU  20  manages the supply of power to the INTC  10 , the processor  30 , the memory  40 , and the like. The PMU  20  wakes the processor  30  up according to a request from the INTC  10 . 
     The INTC  10  includes an interrupt notification register  11  and a wakeup trigger register  12 . The interrupt notification register  11  stores information representing the presence/no-presence of interrupt requests from the sensors A to C. The interrupt notification register  11  includes an entry for each sensor ID, and, in each entry, an interrupt flag representing presence/no-presence of an interrupt request from a sensor corresponding to the sensor ID is recorded. In the interrupt flag, “1” represents assert, and “0” represents negate. Hereinafter, it is assumed that register values of the interrupt notification register  11  represent interrupt flags in order of the sensors A, B, and C from the left side. Thus, “(000)” represents a state in which no interrupt request is generated from the sensors A to C. In addition, “(100)” represents a state in which an interrupt request is generated from the sensor A. “(101)” represents a state in which interrupt request are generated from the sensors A and C. When an interrupt request is received, The INTC  10  updates the corresponding entry. During a period in which at least one entry is “1”, the INTC  10  notifies the processor  30  of the interrupt request by using a level signal. After the execution of the process of acquiring sensor data, the processor  30  clears the entry of a corresponding sensor ID from “1” to “0”. 
     The wakeup trigger register  12  stores information used for identifying a sensor to be triggered for waking up the processor  30 . The wakeup trigger register  12  has an entry for each sensor ID. In each entry, a wakeup trigger flag is recorded. The wakeup trigger flag is a flag used for instructing the PMU  20  whether or not to notify the processor  30  of a wakeup request when an interrupt request is received from a sensor corresponding to the sensor ID. Hereinafter, it is assumed that the register values of the wakeup trigger register  12  represent wakeup trigger flags in order of the sensors A, B, and C from the left side. “(100)” represents that the PMU  20  is instructed to transmit a wakeup request only when an interrupt request is received from the sensor A. In addition, “(010)” represents that the PMU  20  is instructed to transmit a wakeup request only when an interrupt request is received from the sensor B. “(001)” represents that the PMU  20  is instructed to transmit a wakeup request only when an interrupt request is received from the sensor C. The setting of the wakeup trigger register  12  is executed by the processor  30 . 
     In the memory  40 , a management table  41  and a plurality of programs executed by the processor  30  are stored. An application program AP 1  is a program operated at the time of starting up the processor system  100  and executes initial setting for the acquisition of sensor data. A management table registering routine RT 11  is a program that is operated by being called by the application program AP 1  and executes the process of registering the management information in the management table  41 . A wakeup trigger setting routine RT 12  is a program that is operated by being called by the application program AP 1  and executes a setting process of the wakeup trigger register  12 . When the processor  30  transits from the sleep state to the active state, the interrupt handler INTHL 1  starts to operate and executes a sensor A data acquisition process RT 13 , a sensor B data acquisition process RT 14 , or a sensor C data acquisition process RT 15 , thereby executing a data acquisition processes for the sensors A to C. The sensor A data acquisition process RT 13  is a program having a function of acquiring data of the sensor A and storing the acquired data in a predetermined data storage area inside the memory  40 . The sensor B data acquisition process RT 14  is a program having a function of acquiring data of the sensor B and storing the acquired data in a predetermined data storage area inside the memory  40 . The sensor C data acquisition process RT 15  is a program having a function of acquiring data of the sensor C and storing the acquired data in a predetermined data storage area inside the memory  40 . 
       FIG. 2  is a diagram that illustrates the data structure of the management table  41 . The management table  41  includes management information having a set of a sensor ID, an entry address  41   a  of the data acquisition process, and a processing interval  41   b . The entry address  41   a  represents a physical address of the memory  40  where the sensor data acquisition processes RT 13  to RT 15  corresponding to the sensor ID are stored. The processing interval  41   b  represents a data generation period of each of the sensors A to C. The processor  30  executes the process of setting the management table  41  at the time of starting up the processor system  100 . 
     Hereinafter, the process according to the first embodiment of a case where three sensors A, B, and C are connected to the processor system  100  will be described. Here, as illustrated in  FIG. 2 , the sensor A generates sensed data at an interval of 80 msec. The processor  30  acquires data of the sensor A by executing the data acquisition process RT 13  (entry address 0x1100). Similarly, the sensor B generates sensed data at an interval of 100 msec. The processor  30  acquires data of the sensor A by executing the data acquisition process RT 14  (entry address 0x1200). The sensor C generates sensed data at an interval of 125 msec. The processor  30  acquires data of the sensor C by executing the data acquisition process RT 15  (entry address 0x1300). 
       FIGS. 3A and 3B  are timing diagrams that illustrate the sensor data acquisition processes.  FIG. 3A  illustrates a comparative example, and  FIG. 3B  illustrates the first embodiment. Each arrow represents timing at which sensor data is generated. The data acquisition period is at an interval of 80 msec for the sensor A, is at an interval of 100 msec for the sensor B, and is at an interval of 125 msec for the sensor C. In the comparative example, each time the acquisition period of one of the sensors A to C arrives, the processor  30  is woken up, data of a corresponding sensor is acquired, and then, the processor  30  enters the sleep state. For this reason, in the comparative example, from time 0 to time 500, the processor  30  is woken up 14 times. According to the first embodiment, the processor  30  is woken up at the minimum data acquisition interval (the acquisition interval of the sensor A). Thus, according to the first embodiment, from time 0 to time 500, the processor  30  is woken up seven times. As above, according to the first embodiment, it is possible to decrease the number of state transitions (the number of wake-ups) to be less than that of the comparative example. 
     Hereinafter, the operation according to the first embodiment will be described in detail.  FIG. 4  is a flowchart that illustrates the operation sequence of the application program AP 1 . When the processor system  100  is started up, the processor  30  executes the application program AP 1 . The application program AP 1  initializes the sensors A, B, and C (S 100 ). 
     Next, the processor  30  executes the management table registering routine RT 11  (S 101 ).  FIG. 5  is a flowchart that illustrates the management table registering routine RT 11 . First, ID=0, entry address=0x1100, and interval=80 are passed as arguments, and the management table registering routine RT 11  is executed. Accordingly, the management information of the sensor A is registered in the management table  41 . Similarly, the management information of the sensor B and the sensor C is registered in the management table  41  ( FIG. 5 : S 110 ). Accordingly, the management table  41  is formed as illustrated in  FIG. 2 . 
     Next, the processor  30  executes the wakeup trigger setting routine RT 12  ( FIG. 4 : S 102 ).  FIG. 6  is a flowchart that illustrates the wakeup trigger setting routine RT 12 . The processor  30  acquires a sensor ID having a minimal processing interval from the management table  41  (S 120 ). In this case, the sensor ID having the minimal processing interval is the sensor A (ID=0). The processor  30  sets the wakeup trigger register  12  such that a processor wakeup request is issued from the INTC  10  only when an interrupt processing request from the sensor having the acquired ID is issued (S 121 ). In other words, the processor  30  sets the wakeup trigger flag of the acquired sensor ID to “1”. In this case, the wakeup trigger register  12  becomes (100). 
     Next, the processor  30  sets an interrupt vector and the like such that the interrupt handler INTHL 1  is executed when an interrupt request is received from the INTC  10  ( FIG. 4 : S 103 ). Thereafter, the application program AP 1  causes the processor  30  to enter the sleep state (S 104 ). 
       FIG. 7  is a flowchart that illustrates the operation sequence of the interrupt handler INTHL 1 . The interrupt handler INTHL 1  is software that is executed when the processor  30  is notified of an interrupt request. The interrupt handler INTHL 1  checks whether or not an interrupt request from the sensor has occurred by referring to the interrupt notification register  11  (S 131 ). In a case where there is an interrupt request (Yes: S 131 ), the interrupt handler INTHL 1  acquires an entry address  41   a  corresponding to the sensor ID requesting the interrupt from the management table  41  (S 132 ) and executes a data acquisition process stored in the acquired entry address (S 133 ). When the data acquisition process ends, the interrupt handler INTHL 1  clears the interrupt flag of the corresponding sensor ID from “1” to “0” (S 134 ). The interrupt handler INTHL 1  determines whether or not the data acquisition process has been executed for all the sensor IDs of which the interrupt flags are “1” (S 135 ). In a case where a result of the determination is “No”, the process is returned to S 132 , and a similar process is executed for the sensor ID of which the interrupt flag is “1”. 
     Next, the operation of the processor system  100  will be described in detail by referring to the timing diagram illustrated in  FIG. 3B  and the like. When the sensing start time is time 0, during the sensing operation, the following operation is executed. At time 0, the sensors A, B, and C execute sensing operations, and data is generated by each of the sensors A, B, and C. Each of the sensors A to C issues an interrupt request to the INTC  10 . Accordingly, the INTC  10  sets the interrupt notification register  11  to “(111)”. Since any one of the interrupt flags is “1”, the INTC  10  issues an interrupt notification to the processor  30  by using a level signal. In addition, the INTC  10  compares the register value “(111)” of the interrupt notification register  11  with the register value “(100)” of the wakeup trigger register  12  and checks whether or not a bit having a value of “1” in the wakeup trigger register  12  has a value of “1” in the interrupt notification register  11 . A result of the determination is “Yes” in this case, and the INTC  10  requests the PMU  20  to wake the processor  30  up. When the processor wakeup request is received from the INTC  10 , the PMU  20  causes the processor  30  to transit from the sleep state to the active state. 
     In this way, the processor  30  wakes up. At this time, since the interrupt notification has been issued from the INTC  10 , the processor  30  executes the interrupt handler INTHL 1 . The interrupt handler INTHL 1  acquires the register value “(111)” of the interrupt notification register  11  ( FIG. 7 : S 130 ). Since there is a bit of “1” in the register value of the interrupt notification register  11 , the interrupt handler INTHL 1  executes the data acquisition process. First, the interrupt handler INTHL 1  specifies a sensor ID having an interrupt request based on the bit position. In this case, first, ID=0 is selected. The interrupt handler INTHL 1  acquires the entry address “0x1100” of the ID=0 from the management table  41  ( FIG. 7 : S 132 ) and executes the sensor A data acquisition process RT 13  stored at the entry address “0x1100” of the memory  40  ( FIG. 7 : S 133 ). Next, the interrupt handler INTHL 1  clears the interrupt flag of the ID=0 to “0” ( FIG. 7 : S 134 ). Similarly, ID=1 is specified, and the sensor B data acquisition process RT 14  is executed. In addition, ID=2 is specified, and the sensor C data acquisition process RT 15  is executed. Then, since the processes for all the requested sensor IDs have been executed, the process of the interrupt handler INTHL 1  ends, and the process is returned to the application program AP 1 . The application program AP 1  causes the processor  30  to enter the sleep state. 
     Next, at time 80, an interrupt request is issued from the sensor A. At this time, a register value of “(100)” is stored in the interrupt notification register  11 . The INTC  10  checks whether or not a bit having a value of “1” in the wakeup trigger register  12  is “1” in the interrupt notification register  11 . In this case, a result of the determination is “Yes”. For this reason, the processor  30  is woken up by the PMU  20 , and the sensor A data acquisition process is executed by the interrupt handler INTHL 1 . 
     Next, at time 100, an interrupt request is issued from the sensor B. At this time, a value of the interrupt notification register  11  is “(010)”. However, since a bit of the ID=1 corresponding to the sensor B is not “1” in both registers  11  and  12 , the INTC  10  does not issue a processor wakeup request to the PMU  20 . For this reason, the processor  30  remains in the sleep state, and the sensor B data acquisition process is not executed. 
     Next, at time 125, an interrupt request is issued from the sensor C. At this time, a value of the interrupt notification register  11  is “(011)”. However, since a bit of the ID=1 corresponding to the sensor B and a bit of the ID=2 corresponding to the sensor C are not “1” in both the registers  11  and  12 , the INTC  10  does not issue a processor wakeup request to the PMU  20 . For this reason, the processor  30  remains in the sleep state, and the sensor B data acquisition process and the sensor C data acquisition process are not executed. 
     Next, at time 160, an interrupt request is issued from the sensor A. At this time, a value of the interrupt notification register  11  is “(111)”. Since a bit of the ID=0 corresponding to the sensor A is “1” in both the registers  11  and  12 , the INTC  10  issues a wakeup request of the processor  30  to the PMU  20 . When the processor wakeup request is received from the INTC  10 , the PMU  20  wakes the processor  30  up. Accordingly, the interrupt handler INTHL 1  is executed, and the data acquisition processes for the sensors A, B, and C are executed. Thereafter, the processor  30  enters the sleep state. 
     Thereafter, similarly, the processor  30  wakes up only at time 240, time 320, time 400, and time 480, and a data acquisition processes for one or a plurality of sensors that have made interrupt requests until that time are executed at once. 
     As above, in the first embodiment, the processor  30  is woken up based on a minimal data acquisition interval among a plurality of data acquisition intervals, and the number of times of executing a transition between the sleep state and the active state of the processor  30  can be reduced. For this reason, the power consumption of the processor  30  can be reduced. In addition, the sensor data is not overwritten before the acquisition of the sensor data in the processor  30 , and accordingly, the sensor data is not lost. 
     Second Embodiment 
     According to the first embodiment, each of the sensors A to C issues an interrupt request at the time of generation of data. However, an interrupt request may not be issued depending on the sensor. In a second embodiment, a case is considered in which not all the sensors A to C have an interrupt request function. 
       FIG. 8  is a functional block that illustrates a processor system  110  according to the second embodiment. The processor system  110  is connected to sensors A to C. In the case illustrated in  FIG. 8 , the INTC  10  illustrated in  FIG. 1  is replaced with a real-time clock timer (hereinafter, referred to as an RTC timer)  50 . The RTC timer  50  includes a counter that counts a time. The RTC timer  50  is continued to operate constantly also in the sleep state of a processor  30 . The processor  30  includes an internal timer  31 . The internal timer  31  includes a counter that counts a time. The internal timer  31  stops time counting when the processor  30  is in the sleep state. 
     The RTC timer  50  includes an RTC trigger register  51 . The RTC trigger register  51  stores next processing time that is next data generation time of the sensor triggered for waking up the processor  30 . The RTC timer  50  has a function of issuing a processor wakeup request to the PMU  20  and notifying the processor  30  of an interrupt request when the counted value coincides with the register value of the RTC trigger register  51 . When the processor system  110  is started up, the processor  30  executes the process of setting the RTC trigger register  51 . The PMU  20  manages the supply of power to the RTC timer  50 , the processor  30 , the memory  40 , and the like included in the processor system  110 . The PMU  20  wakes the processor  30  up according to a request from the RTC timer  50 . 
     In the memory  40 , a management table  42  and an application program AP 2  and an interrupt handler INTHL 2  executed by the processor  30  are stored. The application program AP 2  is a program that is operated when the processor system  110  is started up and executes initial setting for the acquisition of sensor data. The management table registering routine RT 21  is a program that is operated by being called by the application program AP 2  and executes the process of registering management information in the management table  42 . When the processor  30  transits from the sleep state to the active state, the interrupt handler INTHL 2  is started up and executes a data acquisition process. The wakeup trigger setting routine RT 22  is a program that is operated by being called by the interrupt handler INTHL 2  and executes the process of setting the RTC trigger register  51 . In a sensor A data acquisition process RT 23 , data of a sensor A is acquired, and the data is stored in a predetermined data storage area inside the memory  40 . In a sensor B data acquisition process RT 24 , data of a sensor B is acquired, and the data is stored in a predetermined data storage area inside the memory  40 . In a sensor C data acquisition process RT 25 , data of a sensor C is acquired, and the data is stored in a predetermined data storage area inside the memory  40 . An internal timer synchronizing routine RT 26  is a program that is operated by being called by the interrupt handler INTHL 2  and executes the process of synchronizing internal timer  31 . 
       FIG. 9  is a diagram that illustrates the data structure of the management table  42 . The management table  42  includes management information having a set of a sensor ID and an entry address  42   a  of a data acquisition process, a processing interval  42   b  of the sensor data acquisition, and a next processing time (next_proc)  42   c . The entry address  42   a  represents the physical address of the memory  40  where the sensor data acquisition processes RT 23  to RT 25  for sensor data corresponding to the sensor ID is stored. The processing interval  42   b  represents a data generation period of each of the sensors A to C. The next processing time (next_proc)  42   c  represents next data generation time of each of the sensors A to C. The processor  30  executes the process of setting the management table  42  at the time of starting up the processor system  110 . 
     Hereinafter, the operation according to the second embodiment will be described in detail.  FIG. 10  is a flowchart that illustrates the operation sequence of the application program AP 2 . When the processor system  110  is started up, the processor  30  executes the application program AP 2 . The application program AP 2  initializes the sensors A, B, and C (S 200 ). 
     Next, the processor  30  executes the management table registering routine RT 21  (S 201 ).  FIG. 11  is a flowchart that illustrates the management table registering routine RT 21 . First, ID=0, entry address=0x1100, and interval=80 are passed as arguments, and the management table registering routine RT 21  is executed. Accordingly, the management information of the sensor A is registered in the management table  42 . Similarly, the management information of the sensor B and the sensor C is registered in the management table  42  ( FIG. 11 : S 210 ). Next, the processor  30  sets next processing time to the next processing time (next_proc)  42   c  of each sensor ID. When the management table registering routine RT 21  is executed, the processor  30  sets current time (time 0) acquired from the internal timer  31  to the next processing time  42   c  (S 211 ). 
     The processor  30  sets an interrupt vector and the like such that the interrupt handler INTHL 2  is executed when an interrupt request is received from the RTC timer  50  ( FIG. 10 : S 202 ). The processor  30  executes the interrupt handler INTHL 2  so as to execute a data acquisition process of the first time (S 203 ). Thereafter, the application program AP 2  causes the processor  30  to enter the sleep state (S 204 ). 
       FIG. 12  is a flowchart that illustrates the operation sequence of the interrupt handler INTHL 2 . The interrupt handler INTHL 2 , first, executes the internal timer synchronizing routine RT 26  (S 220 ).  FIG. 13  is a flowchart that illustrates the internal timer synchronizing routine RT 26 . The internal timer synchronizing routine RT 26  is the process of synchronizing the time of the internal timer  31 , which has been stopped, when the processor  30  wakes up. First, the processor  30  acquires the current time from the RTC timer  50  ( FIG. 13 : S 230 ) and synchronizes the internal timer  31  to the acquired current time (S 231 ). 
     Next, the interrupt handler INTHL 2  acquires the entry address  42   a  and the next processing time  42   c  of the ID=0 from the management table  42  (S 221 ). Next, the interrupt handler INTHL 2  compares the current time acquired from the internal timer  31  with the next processing time  42   c  of the ID=0 (S 222 ). In a case where the current time coincides with the next processing time of the ID=0 or in a case where the current time is after the next processing time of the ID=0 (S 222 : Yes), the interrupt handler INTHL 2  executes the sensor A data acquisition process RT 23  (S 223 ). Next, the interrupt handler INTHL 2  updates the next processing time  42   c  of the ID=0 with a value acquired by adding the processing interval  42   b  to the next processing time of the ID=0 (S 224 ). The interrupt handler INTHL 2  determines whether or not the process for all the sensor IDs registered in the management table  42  has ended (S 225 ). Then, in a case where a result of the determination is “No”, the interrupt handler INTHL 2  executes the process of S 221  to S 225  for all the sensor IDs. 
     When the sensor data acquisition process ends in this way, the interrupt handler INTHL 2  executes the wakeup trigger setting routine RT 22  (S 226 ).  FIG. 14  is a flowchart that illustrates the wakeup trigger setting routine RT 22 . The wakeup trigger setting routine RT 22  is a process for setting the next processing time of a sensor ID having a minimal processing interval into the RTC trigger register  51 . The processor  30  acquires the sensor ID having the minimal processing interval from the management table  42  (S 240 ). In this case, the sensor A (ID=0) corresponds to the sensor ID having the minimal processing interval. Next, the processor  30  sets the next processing time of the acquired sensor ID into the RTC trigger register  51  (S 241 ). 
     Next, the operation of the processor system  110  will be described in detail with reference to the timing diagram illustrated in  FIG. 3B . After the processor system  110  is started up, the application program AP 2  is executed. The processor  30  initializes the sensors A, B, and C ( FIG. 10 : S 200 ). Next, the processor  30  sets the management information of the sensors A to C in the management table  42  (S 201 ). In this step, time 0 is set to the next processing time  42   c  of each of the sensors A to C. Next, the processor  30  sets an interrupt vector and the like such that the interrupt handler INTHL 2  is executed when an interrupt request is received from the RTC timer  50  (S 202 ). Then, in order to execute the data acquisition process of the first time, the processor  30  executes the interrupt handler INTHL 2  (S 203 ). 
     At time 0, first, the internal timer  31  is synchronized to the current time of the RTC timer  50  ( FIG. 12 : S 220 ). At time 0, the value of the internal timer  31  is not changed but remains to be the time 0. Next, the processor  30  acquires the next processing time (0) of the ID=0 from the management table  42 , acquires the current time (0) from the internal timer  31 , and compares the current time (0) with the next processing time (0) (S 222 ). Since the current time (0) and the next processing time (0) coincide with each other, the determination executed in S 222  is “Yes”. For this reason, the processor  30  executes the sensor A data acquisition process RT 23  (S 223 ). Next, the processor  30  updates the next processing time of the ID=0 with “the next processing time (0)+the processing interval (80)”=80 (S 224 ). Also for ID=1 and ID=2, the processor  30 , similarly, executes the sensor B data acquisition process RT 24  and the sensor C data acquisition process RT 25  and updates the next processing time thereof. The state of the management table  42  when the processes of the sensors A to C end is illustrated in  FIG. 9 . Next, the processor  30  executes the wakeup trigger setting routine RT 22  (S 226 ). The next processing time=80 of the ID=0 of which the processing interval is minimum is set in the RTC trigger register  51 . Thereafter, when the process of the interrupt handler INTHL 2  ends, the process is returned to the application program AP 2 . The application program AP 2  causes the processor  30  to enter the sleep state. 
     Next, when it is time 80, the timer value of the RTC timer  50  coincides with the register value (=80) of the RTC trigger register  51 . Accordingly, a processor wakeup request is issued from the RTC timer  50  to the PMU  20 , and an interrupt request is notified from the RTC timer  50  to the processor  30 . Accordingly, the processor  30  enters the active state and executes the interrupt handler INTHL 2 . 
     The interrupt handler INTHL 2 , first, synchronizes the internal timer  31  to the current time=80 of the RTC timer  50  ( FIG. 12 : S 220 ). Thereafter, the processor  30  compares the next processing time (80) of the ID=0 with the current time (80) of the internal timer  31  (S 222 ). Since the current time (80) and the next processing time (80) coincide with each other (S 222 : Yes), the processor  30  executes the sensor A data acquisition process RT 23  (S 223 ). Next, the processor  30  updates the next processing time of the ID=0 with “the next processing time (80)+the processing interval (80)”=160 (S 224 ). Next, the processor  30  executes the process for the ID=1. At this time, the next processing time of the ID=1 is “100”. Since the next processing time (100) of the ID=1&gt;the current time (80) is satisfied (S 222 : No), the processor  30  does not execute the data acquisition process and the update of the next processing time for the ID=1. Similarly, the processor  30  does not execute the data acquisition process and the update of the next processing time for the ID=2. Next, the processor  30  executes the wakeup trigger setting routine RT 22  (S 226 ). The next processing time=160 of the ID=0 of which the processing interval is minimal is set in the RTC trigger register  51 . Thereafter, when the process of the interrupt handler INTHL 2  ends, the process is returned to the application program AP 2 . The application program AP 2  causes the processor  30  to enter the sleep state. 
     Next, when it is time 160, the timer value of the RTC timer  50  coincides with the register value (=160) of the RTC trigger register  51 . Accordingly, a processor wakeup request is issued from the RTC timer  50  to the PMU  20 , and an interrupt request is notified from the RTC timer  50  to the processor  30 . Accordingly, the processor  30  enters the active state and executes the interrupt handler INTHL 2 . 
     The interrupt handler INTHL 2 , first, synchronizes the internal timer  31  to the current time=160 of the RTC timer  50  ( FIG. 12 : S 220 ). Thereafter, the processor  30  compares the next processing time (160) of the ID=0 with the current time (160) of the internal timer  31  (S 222 ). Since the current time (160) and the next processing time (160) coincide with each other (S 222 : Yes), the processor  30  executes the sensor A data acquisition process RT 23  (S 223 ). Next, the processor  30  updates the next processing time of the ID=0 with “the next processing time (160)+the processing interval (80)”=240 (S 224 ). Next, the processor  30  executes the process for ID=1. At this time, the next processing time of the ID=1 is “100”, and “the current time (160)&gt;the next processing time (100)” is satisfied (S 222 : Yes). Accordingly, the processor  30  executes the sensor B data acquisition process RT 24  (S 223 ). Next, the processor  30  updates the next processing time of the ID=1 with “the next processing time (100)+the processing interval (100)”=200 (S 224 ). Also for ID=2, similarly, since the next processing time=125 is satisfied (S 222 : Yes), the sensor C data acquisition process RT 25  is executed, and the next processing time is updated with “the next processing time (125)+the processing interval (125)”=250 (S 224 ). Next, the processor  30  executes the wakeup trigger setting routine RT 22  (S 226 ). The next processing time=240 of the ID=0 of which the processing interval is minimal is set in the RTC trigger register  51 . Thereafter, when the process of the interrupt handler INTHL 2  ends, the process is returned to the application program AP 2 . The application program AP 2  causes the processor  30  to enter the sleep state. 
     Thereafter, similarly, the processor  30  is woken up only at time 240, time 320, time 400, and time 480, and, in a case where each time is the next processing time of each ID or after the next processing time, each data acquisition process is executed. 
     In this way, in the second embodiment, since the sensor data acquisition process is managed by the timer, also in a case where the sensor does not have an interrupt request function for a data processing request, the number of times of executing a transition of the processor  30  between the sleep state and the active state of the processor can be reduced. Accordingly, the power consumption of the processor  30  can be reduced. 
     Third Embodiment 
     In a third embodiment, a case is assumed in which sensors having an interrupt request function and a sensor not having an interrupt request function are mixed. 
       FIG. 15  is a functional block that illustrates a processor system  120  according to the third embodiment. Three sensors A, B, and C are connected to the processor system  120 . The sensor A has an interrupt request function and generates sensed data at an interval of 80 msec. The sensor B does not have an interrupt request function but generates sensed data at an interval of 100 msec. The sensor B sets a processing interval by using the timer function described in the second embodiment. The sensor C has an interrupt request function and generates sensed data at an interval of 125 msec. 
     The processor system  120  includes an INTC  10  and an RTC timer  50 . The functions of the INTC  10  and the RTC timer  50  are the same as those of the first embodiment or the second embodiment, and duplicate description will not be presented. A processor  30  includes an internal timer  31 . A PMU  20  manages the supply of power to the INTC  10 , the processor  30 , a memory  40 , the RTC timer  50 , and the like included in the processor system  120 . The PMU  20  wakes the processor  30  up according to a request from the INTC  10  or the RTC timer  50 . 
     In the memory  40 , a management table  43  and an application program AP 3 , an interrupt handler INTHL 3 , a management table registering routine RT 31 , a wakeup trigger setting routine RT 32 , a sensor A data acquisition process RT 33 , a sensor B data acquisition process RT 34 , a sensor C data acquisition process RT 35 , and an internal timer synchronizing routine RT 36 , which are executed by the processor  30 , are stored. 
       FIG. 16  is a diagram that illustrates the data structure of the management table  43 . The management table  43  includes management information having a set of a sensor ID, an entry address  43   a  of a data acquisition process, a processing interval  43   b , a next processing time (next_proc)  43   c , and a trigger type  43   d . The trigger type  43   d  is used for determining whether the data acquisition process is executed according to an interrupt request from the sensor (int) or is executed at a time interval managed by the timer (timer). The processor  30  executes the process of setting the management table  43  at the time of starting up the processor system  120 . 
     Hereinafter, the operation according to the third embodiment will be described in detail.  FIG. 17  is a flowchart that illustrates the operation sequence of the application program AP 3 . When the processor system  120  is started up, the processor  30  executes the application program AP 3 . The application program AP 3  initializes the sensors A, B, and C (S 300 ). 
     Next, the processor  30  executes the management table registering routine RT 31  (S 301 ).  FIG. 18  is a flowchart that illustrates the management table registering routine RT 31 . First, for each sensor ID, the entry address  43   a , the processing interval  43   b , and the trigger type  43   d  are set ( FIG. 18 : S 310 ). Next, the processor  30  sets next processing time to the next processing time (next_proc)  43   c  of each sensor ID. When the management table registering routine RT 31  is executed, the processor  30  sets current time (time 0) acquired from the internal timer  31  to the next processing time  43   c  (S 311 ). 
     The processor  30  sets an interrupt vector and the like such that the interrupt handler INTHL 3  is executed when an interrupt request from the INTC  10  or an interrupt request from the RTC timer  50  is received ( FIG. 17 : S 302 ). Next, the processor  30  executes the interrupt handler INTHL 3  (S 303 ). Thereafter, the application program AP 3  causes the processor  30  to enter the sleep state (S 304 ). 
       FIG. 19  is a flowchart that illustrates the operation sequence of the interrupt handler INTHL 3 . The interrupt handler INTHL 3 , first, executes the internal timer synchronizing routine RT 36  (S 320 ). The sequence of the internal timer synchronizing routine RT 36  is similar to the sequence illustrated in  FIG. 13 . Next, the interrupt handler INTHL 3  acquires the register value of the interrupt notification register  11  (S 321 ). The interrupt handler INTHL 3  checks whether or not an interrupt request from any one of the sensors A to C has occurred by referring to the acquired register value (S 322 ). In a case where there is an interrupt request (S 322 : Yes), the interrupt handler INTHL 3  acquires an entry address corresponding to the sensor ID issuing the interrupt request from the management table  43  (S 323 ) and executes the data acquisition process designated by the acquired entry address (S 324 ). Thereafter, the interrupt handler INTHL 3  clears the interrupt flag of the corresponding sensor ID from “1” to “0” (S 325 ). Next, the interrupt handler INTHL 3  updates the next processing time of the sensor ID with a value acquired by adding the processing interval  43   b  to the next processing time  43   c  of the sensor ID having the interrupt request (S 326 ). The interrupt handler INTHL 3  determines whether or not the data acquisition process has been executed for all the sensor IDs of sensors, of which the trigger type is the interrupt, each having an interrupt flag of “1” (S 327 ). In a case where a result of the determination is No, the same process as that described above is executed for all the sensor IDs each having an interrupt flag of “1”. 
     Next, the interrupt handler INTHL 3  acquires the entry address  43   a  and the next processing time  43   c  of the sensor ID of which the trigger type is the timer from the management table  43  (S 328 ). Next, the interrupt handler INTHL 3  compares the current time of the internal timer  31  with the next processing time  43   c  of the sensor ID, which has been acquired in S 328  (S 329 ). In a case where the next processing time  43   c  of the sensor ID is the current time or before the current time (S 329 : Yes), the interrupt handler INTHL 3  executes the data acquisition process designated by the entry address of the sensor ID (S 330 ). Next, the interrupt handler INTHL 3  updates the next processing time with a value acquired by adding the processing interval  43   b  to the next processing time of the sensor ID (S 331 ). The interrupt handler INTHL 3  determines whether or not the process for all the sensor IDs of which the trigger type is the timer has ended (S 332 ). Then, in a case where a result of the determination is “No”, the interrupt handler INTHL 3  executes the process of S 328  to S 332  for all the sensors of which the trigger type is the timer. Next, when the process ends for all the sensors of which the trigger type is the timer (S 332 : Yes), the interrupt handler INTHL 3  executes the wakeup trigger setting routine RT 32  (S 333 ). 
       FIG. 20  is a flowchart that illustrates the wakeup trigger setting routine RT 32 . The processor  30  acquires a sensor ID having a minimal processing interval from the management table  43  (S 340 ). In this case, the sensor ID having the minimal processing interval is the sensor A (ID=0). Next, the processor  30  determines whether the trigger type of the acquired sensor ID is the interrupt or the timer (S 341 ). In a case where the trigger type is the interrupt (S 341 : Yes), the processor  30  sets the wakeup trigger register  12  such that a processor wakeup request is issued from the INTC  10  to the PMU  20  only when there is an interrupt process request from the sensor having the acquired ID (S 342 ). In other words, the processor  30  sets the wakeup trigger flag of the acquired sensor ID to “1”. In addition, in a case where the trigger type is the timer (S 341 : No), the RTC trigger register  51  is set according to the next processing time of the acquired sensor ID (S 343 ). 
     Next, the operation of the processor system  120  will be described in more detail with reference to the timing diagram illustrated in  FIG. 3B  and the like. After the processor system  120  is started to operate, the application program AP 3  is executed. The processor  30  initializes the sensors A, B, and C ( FIG. 17 : S 300 ). Next, the processor  30  sets the management information of each of the sensors A to C in the management table  43  (S 301 ). For the sensor A, ID=0, entry address=0x1100, interval=80, trigger type=int, and next_proc=0 are set. For the sensor B, ID=1, entry address=0x1200, interval=100, trigger type=timer, and next_proc=0 are set. For the sensor C, ID=2, entry address=0x1300, interval=125, trigger type=int, next_proc=0 are set. Next, the processor  30  sets the interrupt vector and the like such that the interrupt handler INTHL 3  is executed when an interrupt request is received from the INTC  10  or the RTC timer  50  (S 302 ). Then, in order to execute the data acquisition process of a first time, the processor  30  executes the interrupt handler INTHL 3  (S 303 ). 
     At time 0 that is sensing starting time, sensing operations of the sensors A to C are executed, whereby data is generated. The interrupt handler INTHL 3  synchronizes the internal timer  31  ( FIG. 19 : S 320 ). At time 0, the value of the internal timer  31  is not changed but remains to be the time 0. Next, the processor  30  acquires the register value of the interrupt notification register  11  (S 321 ). At time 0, since there are interrupt requests from the sensors A and C, the register value is (101). Since there is “1” in the register value of the interrupt notification register  11 , the interrupt handler INTHL 3  executes the data acquisition process. First, the interrupt handler INTHL 3  specifies a sensor ID having the interrupt request based on a bit position. In this case, first, ID=0 is selected. The interrupt handler INTHL 3  acquires the entry address 0x1100 of the ID=0 from the management table  43  (S 323 ) and executes the sensor A data acquisition process RT 33  stored at the entry address 0x1100 of the memory  40  (S 324 ). Next, the interrupt handler INTHL 3  clears the interrupt flag of the ID=0 to “0” (S 325 ). In addition, the interrupt handler INTHL 3  updates the next processing time with 80 (=the next processing time (0)+the processing interval (80)) (S 326 ). Similarly, the ID=2 is specified, the sensor C data acquisition process RT 35  is executed, the interrupt flag of the ID=2 is further cleared to “0”, and the next processing time is further updated (updated with 0+125=125). 
     Next, the processor  30  acquires the management information of the ID=1 of which the trigger type is the timer (S 328 ). The processor  30  compares the next processing time (0) of the ID=1 with the current time (0) of the internal timer  31  (S 329 ). Since the current time (0) and the next processing time (0) coincide with each other (S 329 : Yes), the processor  30  executes the sensor B data acquisition process RT 34  (S 330 ). Thereafter, the processor  30  updates the next processing time of the ID=1 with “the next processing time (0)+the processing interval (100)”=100 (S 331 ). Then, since all the sensor IDs, of which the trigger type is the timer, have been processed as above, next, the processor  30  executes the wakeup trigger setting routine RT 32  (S 333 ). The processor  30  selects an ID=0 of which the processing interval is minimal ( FIG. 20 : S 340 ), checks that the trigger type of the ID=0 is the interrupt ( FIG. 20 : Yes: S 341 ), and sets the bit of the ID=0 of the wakeup trigger register  12  to “1” (S 342 ). Accordingly, the wakeup trigger register  12  is set as (100). 
     Next, at time 80, an interrupt request is issued from the sensor A. Accordingly, the register value of the interrupt notification register  11  becomes (100), and the INTC  10  issues an interrupt notification to the processor  30  by using a level signal. The INTC  10  checks whether or not a bit having a value of “1” in the wakeup trigger register  12  has a value of “1” in the interrupt notification register  11 . In this case, a result of the determination is “Yes”, and the INTC  10  requests the PMU  20  to wake the processor  30  up. When the processor wakeup request is received from the INTC  10 , the PMU  20  wakes the processor  30  up. When being woken up, the processor  30  receives an interrupt notification from the INTC  10 , and accordingly, the processor  30  executes the interrupt handler INTHL 3 . 
     The interrupt handler INTHL 3  synchronizes the internal timer  31 . Thereafter, the processor  30  executes the sensor A data acquisition process RT 33  based on the register value (100) of the interrupt notification register  11  and updates the next processing time of the ID=0 with 160 (=80+80). Next, the processor  30  acquires the management information of the ID=1. At time 80, since the current time (80) is not the next processing time (100) or after the next processing time, the processor  30  does not execute the data acquisition process. Thereafter, the wakeup trigger setting routine RT 32  is executed, and the processor  30  is caused to enter the sleep state. 
     Next, at time 125, an interrupt request is issued from the sensor C. Accordingly, the register value of the interrupt notification register  11  becomes (001). However, since a bit of the ID=2 that corresponds to the sensor C is not “1” in both registers  11  and  12 , the INTC  10  does not issue a processor wakeup request to the PMU  20 . Accordingly, the processor  30  is maintained to be in the sleep state, and the sensor C data acquisition process is not executed. 
     Next, at time 160, an interrupt request is issued from the sensor A. Accordingly, the register value of the interrupt notification register  11  becomes (101). Since a bit of the ID=0 that corresponds to the sensor A is “1” in both the registers  11  and  12 , the INTC  10  requests the PMU  20  to wake the processor  30  up. When the processor wakeup request is received from the INTC  10 , the PMU  20  wakes the processor  30  up. When being woken up, the processor  30  receives an interrupt notification from the INTC  10  and thus, executes the interrupt handler INTHL 3 . After the synchronizing of the internal timer  31 , the interrupt handler INTHL 3  executes the data acquisition processes and the update of the next processing time of the ID=0 and ID=2 based on the register value (101) of the interrupt notification register  11 . 
     Next, the processor  30  acquires the management information of the ID=1. The processor  30  compares the next processing time (100) of the ID=1 with the current time (160) of the internal timer  31 . Since a condition that the current time (160) is the next processing time (100) or after the next processing time is satisfied, the processor  30  executes the data acquisition process of the ID=1 and further updates the next processing time. Next, the processor  30  executes the wakeup trigger setting routine RT 32 , selects an ID=0 of which the processing interval is minimal, and sets the wakeup trigger register  12  as (100). Thereafter, the processor  30  transits to the sleep state. In the wakeup trigger setting routine RT 32 , in a case where the same register value is constantly set to be overwritten into the wakeup trigger register  12 , the process of S 330  of the second time and after that may be omitted. 
     Thereafter, similarly, the processor  30  is woken up only at time 240, time 320, time 400, and time 480, and, at each time, for sensors of which the trigger type is the interrupt, the data acquisition processes are executed based on the value of the interrupt notification register  11 , and, for sensors of which the trigger type is the timer, the data acquisition processes are executed based on the value of the next processing time. 
     Modified Example of Third Embodiment 
     In this modified example, a case will be considered in which a sensor having a minimal processing interval does not have an interrupt request function, but the processing interval is determined by the timer. A sensor A generates sensed data at a minimal interval of 80 msec and does not have the interrupt request function. A sensor B generates sensed data at an interval of 100 msec and does not have the interrupt request function. A sensor C generates sensed data at an interval of 125 msec and has the interrupt request function. 
     The operation of the processor system  120  will be described in more detail with reference to the timing diagram illustrated in  FIG. 3B  and the like. After the processor system  120  is started to operate, the application program AP 3  is executed. The processor  30  initializes the sensors A, B, and C ( FIG. 17 : S 300 ). Next, the processor  30  sets the management information of each of the sensors A to C in the management table  43  (S 301 ). For the sensor A, ID=0, entry address=0x1100, interval=80, trigger type=timer, and next_proc=0 are set. For the sensor B, ID=1, entry address=0x1200, interval=100, trigger type=timer, and next_proc=0 are set. For the sensor C, ID=2, entry address=0x1300, interval=125, trigger type=int, and next_proc=0 are set. Next, the processor  30  sets the interrupt vector and the like such that the interrupt handler INTHL 3  is executed when an interrupt request is received from the INTC  10  or the RTC timer  50  (S 302 ). Then, in order to execute the data acquisition process of a first time, the processor  30  executes the interrupt handler INTHL 3  (S 303 ). 
     At time 0, sensing operations of the sensors A to C are executed, whereby data is generated. The interrupt handler INTHL 3  synchronizes the internal timer  31  ( FIG. 19 : S 320 ). At time 0, the value of the internal timer  31  is not changed but remains to be the time 0. Next, the processor  30  acquires the register value of the interrupt notification register  11 . At time 0, since there is an interrupt request from the sensor C, the register value is (001). The interrupt handler INTHL 3  executes the data acquisition process of the ID=2. The interrupt handler INTHL 3  acquires the entry address 0x1300 of the ID=2 from the management table  43  (S 323 ) and executes the sensor C data acquisition process RT 35  designated by the entry address 0x1300 of the memory  40  (S 324 ). Next, the interrupt handler INTHL 3  clears the interrupt flag of the ID=2 to “0” (S 325 ). In addition, the interrupt handler INTHL 3  updates the next processing time with 125 (=the next processing time (0)+the processing interval (125)) (S 326 ). 
     Next, the processor  30  acquires the management information of the ID=0 of which the trigger type is the timer (S 328 ). The processor  30  compares the next processing time (0) of the ID=0 with the current time (0) of the internal timer  31  (S 329 ). Since the current time (0) and the next processing time (0) coincide with each other (S 329 : Yes), the processor  30  executes the sensor A data acquisition process RT 33  (S 330 ). Thereafter, the processor  30  updates the next processing time of the ID=0 with “the next processing time (0)+the processing interval (80)”=80 (S 331 ). 
     Next, the processor  30  acquires the management information of the ID=1 (S 328 ). The processor  30  compares the next processing time (0) of the ID=1 with the current time (0) of the internal timer  31  (S 329 ). Since the current time (0) and the next processing time (0) coincide with each other (S 329 : Yes), the processor  30  executes the sensor B data acquisition process RT 34  (S 330 ). Thereafter, the processor  30  updates the next processing time of the ID=1 with “the next processing time (0)+the processing interval (100)”=100 (S 331 ). As above, since all the sensor IDs, of which the trigger type is the timer, have been processed, next, the processor  30  executes the wakeup trigger setting routine RT 32  (S 333 ). Accordingly, the processor  30  selects an ID=0 of which the processing interval is minimal ( FIG. 20 : S 340 ) and sets the next processing time (80) of the ID=0 in the RTC trigger register  51  (S 343 ). 
     Next, at time 80, the RTC timer  50  issues a processor wakeup request to the PMU  20  and issues an interrupt request to the processor  30 . The PMU  20  wakes the processor  30  up. Accordingly, the processor  30  enters the active state and executes the interrupt handler INTHL 3  according to the interrupt request from the RTC timer  50 . 
     The interrupt handler INTHL 3  synchronizes the internal timer  31  to the current time=80 of the RTC timer  50  (S 320 ). Thereafter, the processor  30  acquires the value of the interrupt notification register  11 . At this time, the register value of the interrupt notification register  11  is (000), and an interrupt request has not been issued (S 322 : No). Accordingly, the processor  30  compares the next processing time (80) of the ID=0 acquired from the management table  43  with the current time (80) of the internal timer  31  (S 329 ). Since the current time (80) and the next processing time (80) coincide with each other (S 329 : Yes), the processor  30  executes the sensor A data acquisition process RT 33  (S 330 ). Then, the processor  30  updates the next processing time of the ID=0 with “the next processing time (80)+the processing interval (80)”=160 (S 331 ). Next, the processor  30  executes the process for the ID=1. At this time, the next processing time of the ID=1 is 100. Since the next processing time (100) of the ID=1 is not the current time (80) or before the current time (S 329 : No), the processor  30  does not execute the data acquisition process and the update of the next processing time for the ID=1. Next, the processor  30  executes the wakeup trigger setting routine RT 32  (S 333 ). The next processing time=160 of the ID=0 of which the processing interval is minimal is set in the RTC trigger register  51 . Thereafter, when the process of the interrupt handler INTHL 3  ends, the process is returned to the application program AP 3 . The application program AP 3  causes the processor  30  to enter the sleep state. 
     Next, at time 125, an interrupt request is issued from the sensor C. Accordingly, the register value of the interrupt notification register  11  becomes (001). Since a bit of the ID=2 corresponding to the sensor C is not “1” in both the registers  11  and  12 , the INTC  10  does not issue a processor wakeup request to the PMU  20 . For this reason, the processor  30  remains in the sleep state, and the sensor C data acquisition process is not executed. 
     At time 160, the RTC timer  50  issues a processor wakeup request to the PMU  20  and notifies the processor  30  of an interrupt request. The PMU  20  wakes the processor  30  up. Accordingly, the processor  30  remains in the active state and executes the interrupt handler INTHL 3  according to the interrupt request from the RTC timer  50 . 
     The interrupt handler INTHL 3  synchronizes the internal timer  31  to the current time=160 of the RTC timer  50  (S 320 ). Thereafter, the processor  30  acquires the value of the interrupt notification register  11 . At this time, the register value of the interrupt notification register  11  is (001). Accordingly, the interrupt handler INTHL 3  acquires the entry address 0x1300 of the ID=2 from the management table  43  (S 323 ) and executes the sensor C data acquisition process RT 35  designated by the entry address 0x1300 of the memory  40  (S 324 ). Then, the interrupt handler INTHL 3  clears the interrupt flag of the ID=2 to “0” (S 325 ). In addition, the interrupt handler INTHL 3  updates the next processing time (S 326 ). 
     Thereafter, the processor  30  compares the next processing time (160) of the ID=0 that is stored in the management table  43  with the current time (160) of the internal timer  31  (S 329 ). Since the current time (160) and the next processing time (160) coincide with each other, the processor  30  executes the sensor A data acquisition process RT 33  (S 330 ). Next, the processor  30  updates the next processing time of the ID=0 with “the next processing time (160)+the processing interval (80)”=240 (S 331 ). Next, the processor  30  executes the process for the ID=1. At this time, the next processing time of the ID=1 is “100”. Since the next processing time (100) of the ID=1 is the current time (160) or before the current time, the processor  30  executes the sensor B data acquisition process RT 34  (S 330 ). Then, the processor  30  updates the next processing time of the ID=1 with “the next processing time (100)+the processing interval (100)”=200 (S 331 ). Next, the processor  30  executes the wakeup trigger setting routine RT 32  (S 333 ). The next processing time=240 of the ID=0 of which the processing interval is minimal is set in the RTC trigger register  51 . Thereafter, when the process of the interrupt handler INTHL 3  ends, the process is returned to the application program AP 3 . The application program AP 3  causes the processor  30  to enter the sleep state. 
     Thereafter, similarly, the processor  30  is woken up only at time 240, time 320, time 400, and time 480, and, at each time, for sensors of which the trigger type is the interrupt, the data acquisition processes are executed based on the value of the interrupt notification register  11 , and, for sensors of which the trigger type is the timer, the data acquisition processes are executed based on the value of the next processing time. 
     As above, according to the third embodiment, also in a case where sensors having the function for issuing an interrupt request and sensors not having the above-described function are mixed, the processor  30  can be caused to enter the sleep state for a longer time, whereby the power consumption can be reduced. 
     Fourth Embodiment 
     In the sensors A to C according to the first to third embodiments, there is a premise that a data lifetime is the same as the data acquisition interval. In a case where such a premise is satisfied, the processor  30  is woken up based on a minimal data acquisition interval, whereby sensor data is not lost. However, in a case where there is a sensor in which the data lifetime is shorter than the data acquisition interval, according to a control method in which the processor  30  is woken up based on the minimal data acquisition interval, there is a possibility that data is lost. 
     For example, it is assumed that the sensor has a first-in first-out buffer (FIFO) for storing and accumulating sensor data therein. When the FIFO is filled with sensor data, the processor  30  acquires all the data of the FIFO. In such a case, a data acquisition interval is a period until the FIFO becomes full from a vacant state, and a data lifetime is a period until next data is generated and is stored in the FIFO after the FIFO is full. When data is acquired after the data lifetime, a part of the data of the FIFO is overwritten, and a data loss occurs. Fourth to sixth embodiments can be applied to also such a case. 
       FIG. 21  illustrates an example in which a data loss occurs in a case where the processor  30  is woken up based on a minimal data acquisition interval. Each upward arrow represents time at which sensed data is generated. Each downward arrow represents the deadline of sensed data. In the case illustrated in  FIG. 21 , a sensor B generates sensed data at an interval of 100 msec. The sensor B includes a FIFO therein, and a data lifetime is 25 msec and is shorter than the processing interval of 100 msec. Accordingly, for the sensor B, a period from the generation of data to the deadline of the data represents a data lifetime in the sensing period, and it is necessary to acquire data during the data lifetime. In the example illustrated in  FIG. 21 , the processor executes the data acquisition process based on the processing interval of 80 msec of the sensor A that is the minimal data acquisition interval, and accordingly, in each portion denoted by “miss”, a loss of the data of the sensor B occurs. 
       FIG. 22  is a functional block that illustrates a processor system  130  according to the fourth embodiment. Three sensors A, B, and C are connected to the processor system  130 . The sensor A generates sensed data at an interval of 80 msec, and the data lifetime thereof is 80 msec that is the same as the processing interval. The sensor B generates sensed data at an interval of 100 msec. The sensor B includes an FIFO therein, and the data lifetime thereof is 25 msec. The sensor C generates sensed data at an interval of 125 msec, and the data lifetime thereof is 125 msec that is the same as the processing interval. Each of the sensors A to C has an interrupt request function. 
     The processor system  130  includes an INTC  10  and an RTC timer  50 . The function of the INTC  10  is the same as that described in the previous embodiments, and duplicate description thereof will not be presented. The RTC timer  50  has a timer function but does not issue a processor wakeup request to the PMU  20 . The processor  30  includes an internal timer  31 . The PMU  20  manages the supply of power to the INTC  10 , the processor  30 , a memory  40 , the RTC timer  50 , and the like included in the processor system  130 . The PMU  20  wakes the processor  30  up according to a request from the INTC  10 . 
     In the memory  40 , a management table  44  and an application program AP 4 , an interrupt handler INTHL 4 , a management table registering routine RT 41 , a wakeup trigger setting routine RT 42 , a sensor A data acquisition process RT 43 , a sensor B data acquisition process RT 44 , a sensor C data acquisition process RT 45 , and an internal timer synchronizing routine RT 46 , which are executed by the processor  30 , are stored. 
       FIG. 23  is a diagram that illustrates the data structure of the management table  44 . The management table  44  includes management information having a set of a sensor ID and an entry address  44   a  of a data acquisition process, a processing interval  44   b , a next processing time (next_proc)  44   c , a data lifetime (lifetime)  44   e , and next deadline (next_deadline)  44   f . The data lifetime  44   e  represents a lifetime after the generation of sensor data in each sensing period. The next deadline  44   f  represents a deadline of the next sensor data. The processor  30  executes the process of setting the management table  44  at the time of starting up the processor system  130 . 
       FIG. 24  is a timing diagram that illustrates a comparative example and a sensor data acquisition process according to the fourth embodiment. In  FIG. 24 , the timing diagrams of the sensors A to C are similar to those illustrated in  FIG. 21 . In the comparative example, in addition to the minimal data acquisition interval (the acquisition interval of the sensor A), the processor is woken up at time 100 and time 200. In the comparative example, from time 0 to time 500, the processor is woken up nine times. According to the fourth embodiment, timing at which the processor is woken up is dynamically changed based on the processing interval and the data lifetime. According to the fourth embodiment, from time 0 to time 500, the processor  30  is woken up six times. As above, according to the fourth embodiment, the number of times of execution of a state transition (the number of times of waking up) can be decreased to be less than that of the comparative example. 
     Hereinafter, the operation according to the fourth embodiment will be described in detail.  FIG. 25  is a flowchart that illustrates the operation sequence of the application program AP 4 . When the processor system  130  is started to operate, the processor  30  executes the application program AP 4 . The application program AP 4  initializes the sensors A, B, and C (S 400 ). 
     Next, the processor  30  executes the management table registering routine RT 41  (S 401 ).  FIG. 26  is a flowchart that illustrates the management table registering routine RT 41 . First, for each sensor ID, the entry address  44   a , the processing interval  44   b , and the data lifetime  44   e  are set ( FIG. 26 : S 410 ). Next, the processor  30  sets next processing time to the next processing time  44   c  of each sensor ID. When the management table registering routine RT 41  is executed, the processor  30  sets current time (time 0) acquired from the internal timer  31  to the next processing time  44   c  (S 411 ). 
     The processor  30  sets an interrupt vector and the like such that the interrupt handler INTHL 4  is executed when an interrupt request from the INTC  10  is received ( FIG. 25 : S 402 ). Next, the processor  30  executes the interrupt handler INTHL 4  (S 403 ). Thereafter, the application program AP 4  causes the processor  30  to enter the sleep state (S 404 ). 
       FIG. 27  is a flowchart that illustrates the operation sequence of the interrupt handler INTHL 4 . The interrupt handler INTHL 4  executes the internal timer synchronizing routine RT 46  (S 420 ). The sequence of the internal timer synchronizing routine RT 46  is similar to the sequence illustrated in  FIG. 13 . The processor  30  sets the current time acquired from the RTC timer  50  as the time of the internal timer  31 . Next, the interrupt handler INTHL 4  acquires the register value of the interrupt notification register  11  (S 421 ). The interrupt handler INTHL 4  checks whether or not an interrupt request from any one of the sensors A to C has occurred by referring to the acquired register value (S 422 ). In a case where there is an interrupt request (S 422 : Yes), the interrupt handler INTHL 4  acquires an entry address of the data acquisition process that corresponds to the sensor ID issuing the interrupt request from the management table  44  (S 423 ) and executes the data acquisition process designated by the acquired entry address (S 424 ). Then, the interrupt handler INTHL 4  clears the interrupt flag of the corresponding sensor ID from “1” to “0” (S 425 ). The interrupt handler INTHL 4  determines whether or not the data acquisition process has been executed for all the sensor IDs each having an interrupt flag of “1” (S 426 ). In a case where a result of the determination is No, the same process as that described above is executed for all the sensor IDs each having an interrupt flag of “1”. Next, the interrupt handler INTHL 4  executes the wakeup trigger setting routine RT 42  (S 427 ). 
       FIG. 28  is a flowchart that illustrates the wakeup trigger setting routine RT 42 . The processor  30  acquires the processing interval  44   b , the next processing time  44   c , the data lifetime  44   e , and the next deadline  44   f  from the management table  44  (S 430 ). Next, the processor  30  acquires the current time from the internal timer  31  (S 431 ). Then, the processor  30  executes the following process for each sensor ID. The processor  30  determines whether or not the acquired current time is the next processing time or after the next processing time (S 432 ). In a case where a result of the determination is “Yes”, it represents that sensor data becomes available for the processor  30  during the sleep state. The sensor satisfying this condition has executed the data acquisition process in S 424  illustrated in  FIG. 27 . Thus, instead of the process of S 432 , a sensor of which sensor data becomes available during the sleep state may be specified by identifying a sensor for which the register value of the interrupt notification register  11  is “1”. 
     In a case where the result of S 432  is “Yes”, the processor  30  updates the next processing time  44   c  with a value acquired by adding the processing interval  44   b  to the pre-updated next processing time  44   c  (S 433 ). In addition, the processor  30  updates the next deadline  44   f  with a value acquired by adding the data lifetime  44   e  to the updated next processing time  44   c  (S 434 ). Such a process is repeatedly executed for all the sensor IDs (S 432  to S 435 ). Next, the processor  30  determines a minimum value of the next deadlines of all the sensor IDs and acquires a sensor ID having the largest (latest) next processing time from among the next processing time smaller than the minimum value (S 436 ). Next, the processor  30  sets the wakeup trigger register  12  such that a processor wakeup request is issued from the INTC  10  to the PMU  20  only when there is an interrupt request from the sensor having the acquired ID (S 437 ). In other words, the processor  30  sets the wakeup trigger flag of the acquired sensor ID to “1”. 
     In this way, according to the fourth embodiment, the wakeup trigger setting routine RT 42  is necessarily executed every time when the interrupt handler INTHL 4  is executed. Accordingly, in the fourth embodiment, the sensor ID set in the wakeup trigger register  12  is dynamically changed. 
     Next, the operation of the processor system  130  will be described in more detail with reference to the timing diagram illustrated in  FIG. 24  and the like. After the processor system  130  is started to operate, the application program AP 4  is executed. The processor  30  initializes the sensors A, B, and C ( FIG. 25 : S 400 ). Next, the processor  30  sets the management information of each of the sensors A to C in the management table  44  (S 401 ). For the sensor A, ID=0, entry address=0x1100, interval=80, next_proc=0, lifetime=80, and next_deadline=0 are set. For the sensor B, ID=1, entry address=0x1200, interval=100, next_proc=0, lifetime=25, and next_deadline=0 are set. For the sensor C, ID=2, entry address=0x1300, interval=125, next_proc=0, lifetime=125, and next_deadline=0 are set. Next, the processor  30  sets the interrupt vector and the like such that the interrupt handler INTHL 4  is executed when an interrupt request is received from the INTC  10  (S 402 ). Then, in order to execute the data acquisition process of a first time, the processor  30  executes the interrupt handler INTHL 4  (S 403 ). 
     At time 0, sensing operations of the sensors A to C are executed, whereby data is generated. The interrupt handler INTHL 4  synchronizes the internal timer  31  ( FIG. 27 : S 420 ). At time 0, the value of the internal timer  31  remains to be “0”. Next, the processor  30  acquires the register value of the interrupt notification register  11 . At time 0, since there are interrupt requests from the sensors A to C, the register value is (111). The interrupt handler INTHL 4  executes the data acquisition process. First, the interrupt handler INTHL 4  specifies sensor IDs having interrupt requests by using bit positions. First, ID=0 is selected. The interrupt handler INTHL 4  acquires the entry address 0x1100 of the ID=0 from the management table  44  (S 423 ) and executes the sensor A data acquisition process RT 43  stored by the entry address 0x1100 of the memory  40  (S 424 ). Next, the interrupt handler INTHL 4  clears the interrupt flag of the ID=0 to “0” (S 425 ). In addition, the interrupt handler INTHL 4  execute similar processes for ID=1 and ID=2. 
     Next, the processor  30  executes the wakeup trigger setting routine RT 42  (S 427 ). The processor  30  acquires the processing interval  44   b , the next processing time  44   c , the data lifetime  44   e , and the next deadline  44   f  from the management table  44  (S 430 ). Next, the processor  30  acquires the current time 0 from the internal timer  31  (S 431 ). Then, the processor  30  compares the current time (0) with the next processing time (0) of the ID=0 (S 432 ). Since the current time and the next processing time coincide with each other as a result of the comparison, the processor  30  updates the next processing time of the ID=0 with “the next processing time (0)+the processing interval (80)”=80 (S 434 ). In addition, the processor  30  updates the next deadline of the ID=0 with “the next processing time (80)+the data lifetime (80)”=160 (S 433 ). Similarly, the processor  30  updates the next processing time and the next deadline of each of the ID=1 and ID=2. For ID=1, the next processing time is updated with 100 (=0+100), and the next deadline is updated with 125 (=100+25). For ID=2, the next processing time is updated with 125 (=0+125), and the next deadline is updated with 250 (=125+125).  FIG. 23  illustrates the management table  44  after the update of the management information. In the current state of the management table  44 , a minimal next deadline is 125 msec of the sensor B (ID=1). In addition, among the next processing time before 125 msec, a maximal next processing time is 100 msec of the sensor B. The processor  30  acquires ID=1 as a sensor ID set in the wakeup trigger register  12  (S 436 ). The processor  30  sets the wakeup trigger register  12  to a register value (010) (S 437 ). When the process of the interrupt handler INTHL 4  ends, the process is returned to the application program AP 4 . The application program AP 4  causes the processor  30  to enter the sleep state ( FIG. 25 : S 404 ). 
     Next, at time 80, an interrupt request is issued from the sensor A, and the register value of the interrupt notification register  11  becomes (100). At this time, the register value of the wakeup trigger register  12  is (010). For this reason, the INTC  10  does not issue a processor wakeup request to the PMU  20 . Accordingly, the processor  30  remains to be in the sleep state and does not execute the data acquisition process. 
     Next, at time 100, an interrupt request is issued from the sensor B, and the register value of the interrupt notification register  11  becomes (110). At this time, the register value of the wakeup trigger register  12  is (010). For this reason, the INTC  10  issues a processor wakeup request to the PMU  20 . Accordingly, the processor  30  is woken up, and the sensor A data acquisition process and the sensor B data acquisition process are executed by the interrupt handler INTHL 4 . 
     After the execution of the data acquisition processes, the processor  30  executes the wakeup trigger setting routine RT 42 . The processor  30  compares the current time (100) with the next processing time (80) of the sensor A. Since the current time (100) is after the next processing time (80), the processor  30  updates the next processing time with “the next processing time (80)+the processing interval (80)”=160. In addition, the processor  30  updates the next deadline with “the next processing time (160)+the data lifetime (80)”=240. Similarly, the processor  30  compares the current time (100) with the next processing time (100) of the sensor B. Since the current time (100) is the next processing time (100) or after the next processing time, the processor  30  updates the next processing time with “the next processing time (100)+the processing interval (100)”=200 and updates the next deadline with “the next processing time (200)+the data lifetime (25)”=225. For the sensor C, since the next processing time (125) is after the current time (100), the current next processing time (125) and the current next deadline (250) are not updated. In the current state of the management table  44 , a minimal next deadline is 225 msec of the sensor B, and a maximum value of the next processing time before 225 msec is 200 msec of the sensor B. Accordingly, the processor  30  acquires ID=1 as a sensor ID set in the wakeup trigger register  12 . The processor  30  sets the wakeup trigger register  12  to a register value (010). When the process of the interrupt handler INTHL 4  ends, the process is returned to the application program AP 4 . The application program AP 4  causes the processor  30  to enter the sleep state. 
     Thereafter, similarly, the processor  30  is woken up only at time 200, time 300, time 375, and time 400, and, the data acquisition processes for a sensor having an interrupt request until each time are executed. 
     According to the fourth embodiment, based on the data generation period of the sensor and the data lifetime, the timing for waking up the processor is dynamically changed so as not to allow an occurrence of a data loss. For this reason, the number of times of execution of a transition of the processor  30  between the sleep state and the active state can be decreased, and the power consumption of the processor  30  can be reduced. In addition, since any data acquisition process is not executed by the processor  30  after the deadline of the data, there is no loss of the sensed data. 
     Fifth Embodiment 
     In a fifth embodiment, similar to the fourth embodiment, a case is considered in which a sensor of which the data lifetime is shorter than the data acquisition interval is present. In addition, similar to the second embodiment, a case is considered in which all the sensors A to C do not have the interrupt request function. Also in the fifth embodiment, the processor  30  is woken up at timing represented in the timing diagram illustrated on the lowermost side in  FIG. 24  and executes the data acquisition operation. 
       FIG. 29  is a functional block that illustrates a processor system  140  according to the fifth embodiment. Three sensors A, B, and C are connected to the processor system  140 . The sensor A generates sensed data at an interval of 80 msec, and the data lifetime thereof is 80 msec. The sensor B generates sensed data at an interval of 100 msec. The sensor B includes an FIFO therein, and the data lifetime thereof is 25 msec. The sensor C generates sensed data at an interval of 125 msec, and the data lifetime thereof is 125 msec. Each of the sensors A to C does not have an interrupt request function. 
     The processor system  140  includes an RTC timer  50 . The function of the RTC timer  50  is the same as that described in the second embodiment, and duplicate description thereof will not be presented. A processor  30  includes an internal timer  31 . A PMU  20  manages the supply of power to the processor  30 , a memory  40 , the RTC timer  50 , and the like included in the processor system  140 . The PMU  20  wakes the processor  30  up according to a request from the RTC timer  50 . 
     In the memory  40 , a management table  45  and an application program AP 5 , an interrupt handler INTHL 5 , a management table registering routine RT 51 , a wakeup trigger setting routine RT 52 , a sensor A data acquisition process RT 53 , a sensor B data acquisition process RT 54 , a sensor C data acquisition process RT 55 , and an internal timer synchronizing routine RT 56 , which are executed by the processor  30 , are stored. 
     The data structure of the management table  45  is the same as the management table  44  illustrated in  FIG. 23 . The management table  45  includes management information having a set of a sensor ID, an entry address  45   a , a processing interval  45   b , a next processing time (next_proc)  45   c , a data lifetime (lifetime)  45   e , and a next deadline (next_deadline)  45   f.    
     Hereinafter, the operation according to the fifth embodiment will be described in detail.  FIG. 30  is a flowchart that illustrates the operation sequence of the application program AP 5 . When the processor system  140  is started to operate, the processor  30  executes the application program AP 5 . The application program AP 5  initializes the sensors A, B, and C (S 500 ). 
     Next, the processor  30  executes the management table registering routine RT 51  (S 501 ). The management table registering routine RT 51  is the same as the management table registering routine RT 31  illustrated in  FIG. 26 . The processor  30  sets an interrupt vector and the like such that the interrupt handler INTHL 5  is executed when an interrupt request from the RTC timer  50  is received (S 502 ). Next, the processor  30  executes the interrupt handler INTHL 5  (S 503 ). Thereafter, the application program AP 5  causes the processor  30  to enter in the sleep state (S 504 ). 
       FIG. 31  is a flowchart that illustrates the operation sequence of the interrupt handler INTHL 5 . The interrupt handler INTHL 5  executes the internal timer synchronizing routine RT 56  (S 510 ). The sequence of the internal timer synchronizing routine RT 56  is similar to the sequence illustrated in  FIG. 13 . In other words, the processor  30  sets the current time acquired from the RTC timer  50  as the time of the internal timer  31 . Next, the interrupt handler INTHL 5  acquires the entry address  45   a  and the next processing time  45   c  of the ID=0 from the management table  45  (S 511 ). Next, the interrupt handler INTHL 5  compares the current time acquired from the internal timer  31  with the next processing time (next_proc)  45   c  of the ID=0 (S 512 ). In a case where the current time is the next processing time of the ID=0 or after the next processing time (S 512 : Yes), the interrupt handler INTHL 5  executes the sensor A data acquisition process RT 53  (S 513 ). Next, the interrupt handler INTHL 5  updates the next processing time of the ID=0 with a value acquired by adding the processing interval  45   b  to the next processing time of the ID=0 (S 514 ). The interrupt handler INTHL 5  determines whether or not the process for all the sensor IDs registered in the management table  45  has ended (S 515 ). Then, in a case where a result of the determination is “No”, the interrupt handler INTHL 5  executes the process of S 511  to S 515  for all the sensor IDs. Next, the interrupt handler INTHL 5  executes the wakeup trigger setting routine RT 52  (S 516 ). 
       FIG. 32  is a flowchart that illustrates the wakeup trigger setting routine RT 52 . The processor  30  acquires the processing interval  45   b , the next processing time  45   c , the data lifetime  45   e , and the next deadline  45   f  from the management table  45  (S 520 ). Next, the processor  30  acquires the current time from the internal timer  31  (S 521 ). Then, the processor  30  executes the following process for each sensor ID. The processor  30  updates the next deadline  45   f  with a value acquired by adding the data lifetime  45   e  to the next processing time  45   c , which has been updated in S 514  (S 522 ). Such a process is repeatedly executed for all the sensor IDs (S 522  to S 523 ). Next, the processor  30  determines a minimum value of the next deadlines of all the sensor IDs and acquires a sensor ID having a largest (latest) next processing time among the next processing time smaller than the minimum value (S 524 ). Next, the processor  30  sets the next processing time of the acquired sensor ID in the RTC trigger register  51  (S 525 ). 
     Next, the operation of the processor system  140  will be described in more detail with reference to the timing diagram illustrated in  FIG. 24  and the like. After the processor system  140  is started to operate, the application program AP 5  is executed. The processor  30  initializes the sensors A, B, and C ( FIG. 30 : S 500 ). Next, the processor  30  sets the management information of each of the sensors A to C in the management table  45  (S 501 ). For the sensor A, ID=0, entry address=0x1100, interval=80, next_proc=0, lifetime=80, and next_deadline=0 are set. For the sensor B, ID=1, entry address=0x1200, interval=100, next_proc=0, lifetime=25, and next_deadline=0 are set. For the sensor C, ID=2, entry address=0x1300, interval=125, next_proc=0, lifetime=125, and next_deadline=0 are set. Next, the processor  30  sets the interrupt vector and the like such that the interrupt handler INTHL 5  is executed when an interrupt request is received from the RTC timer  50  (S 502 ). Then, in order to execute the data acquisition process of a first time, the processor  30  executes the interrupt handler INTHL 5  (S 503 ). 
     At time 0, sensing operations of the sensors A to C are executed, whereby data is generated. The interrupt handler INTHL 5  synchronizes the internal timer  31  ( FIG. 31 : S 510 ). At time 0, the value of the internal timer  31  remains to be “0”. Next, the interrupt handler INTHL 5  acquires the entry address (0x1100) and the next processing time (0) of the ID=0 from the management table  45  (S 511 ). Next, the interrupt handler INTHL 5  compares the current time (0) acquired from the internal timer  31  with the next processing time (0) of the ID=0 (S 512 ). Since the condition of S 512  is satisfied, the interrupt handler INTHL 5  executes the sensor A data acquisition process RT 53  (S 513 ). Next, the interrupt handler INTHL 5  updates the next processing time with “the next processing time (0)+the processing interval (80)”=80 (S 514 ). In addition, the interrupt handler INTHL 5  executes a similar process for the ID=1 and the ID=2. 
     Next, the interrupt handler INTHL 5  executes the wakeup trigger setting routine RT 52  (S 516 ). The processor  30  acquires the processing interval  45   b , the next processing time  45   c , the data lifetime  45   e , and the next deadline  45   f  from the management table  45  (S 520 ). Next, the processor  30  acquires the current time 0 from the internal timer  31  in Step  521 . The processor  30  updates the next deadline of the ID=0 with “the next processing time (80) updated in S 514 +the data lifetime (80)”=160 (S 522 ). Similarly, the processor  30  updates the next deadline of the ID=1 with 125 (=100+25) and updates the next deadline of the ID=2 with 250 (=125+125). In the current state of the management table  45 , a minimal next deadline is 125 msec of the sensor B (ID=1). In addition, among the next processing time before 125 msec, a maximal next processing time is 100 msec of the sensor B. The processor  30  acquires ID=1 as a sensor ID set in the wakeup trigger register  12  (S 524 ). Next, the processor  30  sets the next processing time (=100) of the acquired sensor ID in the RTC trigger register  51  (S 525 ). When the process of the interrupt handler INTHL 5  ends, the process is returned to the application program AP 5 . The application program AP 5  causes the processor  30  to enter the sleep state ( FIG. 30 : S 504 ). 
     Next, when it is time 100, the timer value of the RTC timer  50  coincides with the register value (=100) of the RTC trigger register  51 . Accordingly, a processor wakeup request is issued from the RTC timer  50  to the PMU  20 , and an interrupt request is notified from the RTC timer  50  to the processor  30 . Accordingly, the processor  30  is in the active state and executes the interrupt handler INTHL 5 . 
     The interrupt handler INTHL 5  synchronizes the internal timer  31  to the current time=100 of the RTC timer  50  (S 510 ). The interrupt handler INTHL 5  acquires the next processing time (80) of the sensor A (ID=0) from the management table  45  (S 511 ) and compares the current time (100) with the next processing time (80) (S 512 ). At this time, since the condition of S 512  is satisfied, the processor  30  executes the sensor A data acquisition process RT 53  (S 513 ). Next, the interrupt handler INTHL 5  updates the next processing time of the ID=0 with “the next processing time (80)+the processing interval (80)”=160 (S 514 ). Next, the process is executed for the sensor B. Since the current time is (100), and the next processing time of the sensor B is (100), the condition of S 512  is satisfied. The processor  30  executes the sensor B data acquisition process RT 54 . Thereafter, the interrupt handler INTHL 5  updates the next processing time of the ID=1 with “the next processing time (100)+the processing interval (100)”=200. Since the next processing time of the sensor C is (125) and is after the current time (100), the condition of S 512  is not satisfied. For this reason, the data acquisition process and the update of the next processing time for the sensor C are not executed. Next, the processor  30  executes the wakeup trigger setting routine RT 52  (S 516 ). 
     The processor  30  acquires the processing interval  45   b , the next processing time  45   c , the data lifetime  45   e , and the next deadline  45   f  from the management table  45  (S 520 ). Next, the processor  30  acquires the current time (100) from the internal timer  31  (S 521 ). Then, the processor  30  executes the following process for each sensor ID. The processor  30  updates the next deadline  45   f  with a value acquired by adding the data lifetime  45   e  to the next processing time  45   c , which has been updated in S 514  (S 522 ). The next processing time of the ID=0 becomes 160, and the next deadline becomes 240. The next processing time of the ID=1 becomes 200, and the next deadline becomes 225. The next processing time of the ID=2 becomes 125, and the next deadline becomes 250. In the current state of the management table  45 , a minimal next deadline is 225 msec of the sensor B, and, among the next processing time before 225 msec, a maximal value is 200 msec of the sensor B. Accordingly, the processor  30  acquires ID=1 as a sensor ID of which the next processing time is set in the RTC trigger register  51  (S 524 ). The processor  30  sets the RTC trigger register  51  to 200 that is the next processing time of the sensor B (S 525 ). When the process of the interrupt handler INTHL 5  ends, the process is returned to the application program AP 5 . The application program AP 5  causes the processor  30  to enter the sleep state. 
     Thereafter, similarly, the processor  30  is woken up only at time 200, time 300, time 375, and time 400, and the data acquisition processes of which the next processing time is before the current time are executed each time. 
     According to the fifth embodiment, based on the data generation period of the sensor and the data lifetime, the timing for waking up the processor  30  is dynamically changed so as not to allow an occurrence of a data loss. In addition, the sensor data acquisition process is managed by the timer. For this reason, also in a case where a sensor does not have the interrupt request function, the number of times of execution of a transition of the processor  30  between the sleep state and the active state can be decreased. Accordingly, the power consumption of the processor  30  can be reduced. In addition, after the data deadline, the data acquisition process is not executed by the processor  30 , and accordingly, there is no loss of the sensed data. 
     Sixth Embodiment 
     In a sixth embodiment, similar to the fourth embodiment, a case is considered in which a sensor of which the data lifetime is shorter than the data acquisition interval is present. In addition, similar to the third embodiment, a case is considered in which sensors having the interrupt request function and a sensor not having the interrupt request function are mixed. 
       FIG. 33  is a functional block that illustrates a processor system  150  according to the sixth embodiment. Three sensors A, B, and C are connected to the processor system  150 . The sensor A generates sensed data at an interval of 80 msec, and the data lifetime thereof is 80 msec. The sensor B generates sensed data at an interval of 100 msec. The sensor B includes an FIFO therein, and the data lifetime thereof is 25 msec. The sensor C generates sensed data at an interval of 125 msec, and the data lifetime thereof is 125 msec. While the sensors A and C have the interrupt request function, the sensor B does not have the interrupt request function. 
     The processor system  150  illustrated in  FIG. 33  includes an INTC  10  and an RTC timer  50 . The functions of the INTC  10  and the RTC timer  50  are the same as those of the third embodiment described above, and duplicate description will not be presented. A processor  30  includes an internal timer  31 . A PMU  20  manages the supply of power to the INTC  10 , the processor  30 , a memory  40 , the RTC timer  50 , and the like included in the processor system  150 . The PMU  20  wakes the processor  30  up according to a request from the INTC  10  or the RTC timer  50 . 
     In the memory  40 , a management table  46  and an application program AP 6 , an interrupt handler INTHL 6 , a management table registering routine RT 61 , a wakeup trigger setting routine RT 62 , a sensor A data acquisition process RT 63 , a sensor B data acquisition process RT 64 , a sensor C data acquisition process RT 65 , and an internal timer synchronizing routine RT 66 , which are executed by the processor  30 , are stored. 
       FIG. 34  is a diagram that illustrates the data structure of the management table  46 . The management table  46  includes management information having a set of a sensor ID and an entry address  46   a  of a data acquisition process, a processing interval  46   b , a next processing time (next_proc)  46   c , a trigger type  46   d , a data lifetime (lifetime)  46   e , and next deadline (next_deadline)  46   f.    
     Hereinafter, the operation according to the sixth embodiment will be described in detail.  FIG. 35  is a flowchart that illustrates the operation sequence of the application program AP 6 . When the processor system  150  is started to operate, the processor  30  executes the application program AP 6 . The application program AP 6  initializes the sensors A, B, and C (S 600 ). 
     Next, the processor  30  executes the management table registering routine RT 61  (S 601 ).  FIG. 36  is a flowchart that illustrates the management table registering routine RT 61 . First, for each sensor ID, the entry address  46   a , the processing interval  46   b , the data lifetime  46   e , and the trigger type  46   d  are set ( FIG. 36 : S 610 ). Next, the processor  30  sets the current time (0) to the next processing time  46   c  of each sensor ID. 
     The processor  30  sets an interrupt vector and the like such that the interrupt handler INTHL 6  is executed when an interrupt request from the INTC  10  or the RTC timer  50  is received ( FIG. 35 : S 602 ). Next, the processor  30  executes the interrupt handler INTHL 6  (S 603 ). Thereafter, the application program AP 6  causes the processor  30  to be in the sleep state (S 604 ). 
       FIG. 37  is a flowchart that illustrates the operation sequence of the interrupt handler INTHL 6 . The interrupt handler INTHL 6  executes the internal timer synchronizing routine RT 66  (S 620 ). The sequence of the internal timer synchronizing routine RT 66  is similar to the sequence illustrated in  FIG. 13 . In other words, the processor  30  acquires the current time from the RTC timer  50  and sets the acquired current time as the time of the internal timer  31 . Next, the interrupt handler INTHL 6  acquires the register value of the interrupt notification register  11  (S 621 ). The interrupt handler INTHL 6  checks whether or not an interrupt request from any one of the sensors A to C has occurred by referring to the acquired register value (S 622 ). In a case where there is an interrupt request (S 622 : Yes), the interrupt handler INTHL 6  acquires an entry address of the data acquisition process that corresponds to the sensor ID issuing the interrupt request from the management table  46  (S 623 ) and executes the data acquisition process designated by the acquired entry address (S 624 ). Then, the interrupt handler INTHL 6  clears the interrupt flag of the corresponding sensor ID from “1” to “0” (S 625 ). Next, the interrupt handler INTHL 6  updates the next processing time of the sensor ID with a value acquired by adding the processing interval  46   b  to the next processing time of the sensor ID having an interrupt request (S 626 ). The interrupt handler INTHL 6  determines whether or not the data acquisition process has been executed for all the sensor IDs of the sensors, of which the trigger type is the interrupt, each having an interrupt flag of “1” (S 627 ). In a case where a result of the determination is “No”, the same process as that described above is executed for all the sensor IDs, of which the trigger type is the interrupt, each having an interrupt flag of “1”. 
     Next, the interrupt handler INTHL 6  acquires the entry address  46   a  and the next processing time  46   c  of the sensor ID of which the trigger type is the timer from the management table  46  (S 628 ). Next, the interrupt handler INTHL 6  compares the current time acquired from the internal timer  31  with the next processing time  46   c  of the sensor ID that is acquired in S 628  (S 629 ). In a case where the next processing time  46   c  of the sensor ID is the current time or before the current time (S 629 : Yes), the interrupt handler INTHL 6  executes the data acquisition process designated by the entry address of the sensor ID acquired in S 628  (S 630 ). Next, the interrupt handler INTHL 6  updates the next processing time of the sensor ID with a value acquired by adding the processing interval  46   b  to the next processing time of the sensor (S 631 ). The interrupt handler INTHL 6  determines whether or not the process for all the sensor IDs of which the trigger type is the timer has ended (S 632 ). In a case where a result of the determination is “No”, the process of S 628  to S 632  is executed for all the sensors of which the trigger type is the timer. Next, the interrupt handler INTHL 6  executes the wakeup trigger setting routine RT 62  (S 633 ). 
       FIG. 38  is a flowchart that illustrates the wakeup trigger setting routine RT 62 . The processor  30  acquires the processing interval  46   b , the next processing time  46   c , the data lifetime  46   e , and the next deadline  46   f  from the management table  46  (S 640 ). Next, the processor  30  acquires the current time from the internal timer  31  (S 641 ). Then, the processor  30  executes the following process for each sensor ID. The processor  30  updates the next deadline  46   f  with a value acquired by adding the data lifetime  46   e  to the next processing time  46   c , which has been updated in S 626  or S 631  (S 642 ). Such a process is repeatedly executed for all the sensor IDs (S 642  and S 643 ). Next, the processor  30  determines a minimum value of the next deadlines of all the sensor IDs and acquires a sensor ID having the largest (latest) next processing time from among the next processing time smaller than the minimum value (S 644 ). Next, the processor  30  determines whether the trigger type of the acquired sensor ID is the interrupt or the timer (S 645 ). In a case where the trigger type is the interrupt, the processor  30  sets the wakeup trigger register  12  such that a processor wakeup request is issued from the INTC  10  to the PMU  20  only when there is an interrupt processing request from the sensor having the acquired ID (S 646 ). In other words, the processor  30  sets the wakeup trigger flag of the acquired sensor ID to “1”. In addition, the processor  30  clears the RTC trigger register  51  (S 647 ). On the other hand, in a case where the trigger type is the timer (S 645 : No), the RTC trigger register  51  is set based on the next processing time of the acquired sensor ID (S 648 ). In addition, the processor  30  clears the wakeup trigger register  12  (S 649 ). 
     Next, the operation of the processor system  150  will be described in more detail with reference to the timing diagram illustrated in  FIG. 24  and the like. After the processor system  150  is started to operate, the application program AP 6  is executed. The processor  30  initializes the sensors A, B, and C ( FIG. 35 : S 600 ). Next, the processor  30  sets the management information of each of the sensors A to C in the management table  46  (S 601 ). For the sensor A, ID=0, entry address=0x1100, interval=80, next_proc=0, lifetime=80, next_deadline=0, and trigger type=int are set. For the sensor B, ID=1, entry address=0x1200, interval=100, next_proc=0, lifetime=25, next_deadline=0, and trigger type=timer are set. For the sensor C, ID=2, entry address=0x1300, interval=125, next_proc=0, lifetime=125, next_deadline=0, and trigger type=int are set. Next, the processor  30  sets the interrupt vector and the like such that the interrupt handler INTHL 6  is executed when an interrupt request is received from the INTC  10  or the RTC timer  50  (S 602 ). Then, in order to execute the data acquisition process of a first time, the processor  30  executes the interrupt handler INTHL 6  (S 603 ). 
     At time 0, sensing operations of the sensors A to C are executed, whereby data is generated. The interrupt handler INTHL 6  synchronizes the internal timer  31  ( FIG. 36 : S 620 ). At time 0, the value of the internal timer  31  remains to be “0”. Next, the processor  30  acquires the register value of the interrupt notification register  11  (S 621 ). At time 0, since there are interrupt requests from the sensors A and C, the register value is (101). In this case, first, ID=0 is selected. The interrupt handler INTHL 6  acquires the entry address 0x1100 of the ID=0 from the management table  46  (S 623 ) and executes the sensor A data acquisition process RT 63  stored at the entry address 0x1100 of the memory  40  (S 624 ). Then, the interrupt handler INTHL 6  clears the interrupt flag of the ID=0 to “0” (S 625 ). Next, the interrupt handler INTHL 6  updates the next processing time with 80 (=the next processing time (0)+the processing interval (80)) (S 626 ). In addition, a similar process is executed by the interrupt handler INTHL 6  for the ID=2. In addition, the next processing time of the sensor C is updated with 125 (=0+125). 
     Next, the interrupt handler INTHL 6  compares the current time (0) with the next processing time (0) for the sensor B of which the trigger type is the timer (S 629 ). Here, since the current time (0) is the next processing time (0) or after the next processing time, the interrupt handler INTHL 6 , similarly, executes the sensor B data acquisition process RT 64  (S 630 ). In addition, the interrupt handler INTHL 6  updates the next processing time of the sensor B with 100 (=0+100) (S 631 ). 
     Next, the processor  30  executes the wakeup trigger setting routine RT 62  (S 633 ). The processor  30  acquires the processing interval  46   b , the next processing time  46   c , the data lifetime  46   e , and the next deadline  46   f  from the management table  46  (S 640 ). Next, the processor  30  acquires the current time 0 from the internal timer  31  (S 641 ). The processor  30  updates the next deadline of the ID=0 with “the next processing time (80) updated in S 626 +the data lifetime (80)”=160 (S 642 ). Similarly, the processor  30  updates the next deadline of the ID=1 with 125 (=100+25) and updates the next deadline of the ID=2 with 250 (=125+125). In the current state of the management table  46 , a minimal next deadline is 125 msec of the sensor B (ID=1). In addition, among the next processing time before 125 msec, a maximal next processing time is 100 msec of the sensor B. The processor  30  acquires ID=1 as a sensor ID set in the wakeup trigger register  12  (S 645 ). Since the trigger type of the sensor B (ID=1) is the timer, the processor  30  sets the next processing time (=100) of the ID=1 in the RTC trigger register  51  (S 648 ). In addition, the processor  30  clears the wakeup trigger register  12  (S 649 ). When the process of the interrupt handler INTHL 6  ends, the process is returned to the application program AP 6 . The application program AP 6  causes the processor  30  to enter the sleep state ( FIG. 35 : S 604 ). 
     Next, at time 80, an interrupt request is issued from the sensor A, and the register value of the interrupt notification register  11  becomes (100). At this time, the register value of the wakeup trigger register  12  is (010). For this reason, the INTC  10  does not issue a processor wakeup request to the PMU  20 . Accordingly, the processor  30  remains to be in the sleep state and does not execute the data acquisition process. 
     Next, at time 100, the timer value of the RTC timer  50  coincides with the register value (=100) of the RTC trigger register  51 . Accordingly, a processor wakeup request is issued from the RTC timer  50  to the PMU  20 , and an interrupt request is notified from the RTC timer  50  to the processor  30 . Thus, the processor  30  enters the active state and executes the interrupt handler INTHL 6 . 
     The interrupt handler INTHL 6  synchronizes the internal timer  31  to the current time=100 of the RTC timer  50  (S 620 ). The interrupt handler INTHL 6  acquires the register value (100) of the interrupt notification register  11  (S 621 ). Based on this register value (100), the processor  30  executes the sensor A data acquisition process RT 63  (S 623  and S 624 ). Then, the interrupt handler INTHL 6  clears the interrupt flag of the ID=0 to “0” (S 625 ). In addition, the interrupt handler INTHL 6  updates the next processing time of the ID=0 with 160 (=80+80) (S 626 ). 
     Next, the interrupt handler INTHL 6  acquires the next processing time (100) of the sensor B (ID=1) from the management table  46  (S 628 ) and compares the acquired next processing time (100) with the current time (100) (S 629 ). At this time, since the current time (100) is the next processing time (100), the processor  30  executes the sensor B data acquisition process RT 64  (S 630 ). Then, the interrupt handler INTHL 6  updates the next processing time of the ID=1 with 200 (=100+100) (S 631 ). Next, the interrupt handler INTHL 6  calls the wakeup trigger setting routine RT 62 . 
     The processor  30  acquires the processing interval  46   b , the next processing time  46   c , the data lifetime  46   e , and the next deadline  46   f  from the management table  46  (S 640 ). Next, the processor  30  acquires the current time (100) from the internal timer  31  (S 641 ). Then, the processor  30  executes the following process for each sensor ID. The processor  30  updates the next deadline  46   f  with a value acquired by adding the data lifetime  46   e  to the latest next processing time  46   c , which is registered in the management table  46 , (S 642 ). The next processing time of the ID=0 becomes 160, and the next deadline thereof becomes 240 (=160+80). In addition, the next processing time of the ID=1 becomes 200, and the next deadline thereof becomes 225 (=200+25). The next processing time of the ID=2 becomes 125, and the next deadline thereof becomes 250 (=125+125). In the current state of the management table  46 , a minimal next deadline is 225 msec of the sensor B, and, a maximum value of the next processing time before 225 msec is 200 msec of the sensor B. Accordingly, the processor  30  acquires the ID=1 as the sensor ID (S 644 ). The processor  30  sets 200 that is the next processing time of the sensor B in the RTC trigger register  51  (S 648 ). In addition, the processor  30  clears the wakeup trigger register  12  (S 649 ). When the process of the interrupt handler INTHL 6  ends, the process is returned to the application program AP 6 . The application program AP 6  causes the processor  30  to enter the sleep state. 
     Thereafter, similarly, the processor  30  is woken up only at time 200, time 300, time 375, and time 400, and, at each time, for a sensor of which the trigger type is the interrupt, the data acquisition process is executed based on the value of the interrupt notification register  11 , and, for a sensor of which the trigger type is the timer, the data acquisition process is executed based on the value of the next processing time. 
     According to the sixth embodiment, based on the data generation period of the sensor and the data lifetime, the timing for waking up the processor  30  is dynamically changed so as not to allow an occurrence of a data loss. In addition, the sensor data acquisition process is managed by the interrupt control process and the timer. For this reason, also in a case where sensors having the interrupt request function and sensors not having the interrupt request function are mixed, the number of times of execution of a transition of the processor  30  between the sleep state and the active state can be decreased. Accordingly, the power consumption of the processor  30  can be reduced. In addition, since any data acquisition process is not executed by the processor  30  after the data deadline, there is no loss of the sensed data. 
     Seventh Embodiment 
     In a case where a jitter is present at the data generation time of a sensor, there is a possibility that a loss of data occurs due to the jitter.  FIG. 39  illustrates timing diagrams of sensors P, Q, and R and a processor. The sensors P, Q, and R have the interrupt request function. In  FIG. 39 , each upward arrow represents time at which sensor data is generated. In addition, each downward arrow represents a deadline of sensor data. A period from an upward arrow to a downward arrow represents a data lifetime. It is assumed that a jitter occurs in the sensor Q, and the data generation time of the sensor Q, as denoted by an arrow Z, deviates from normal time denoted by a broken line to a prior time point denoted by a solid line. 
     A case will be described in which data of the sensors P, Q, and R illustrated in  FIG. 39  is acquired under the control of the fourth embodiment. At a time point of time t 0 , the processor is woken up by using the sensor P as a wakeup trigger. Here, “by using the sensor P as a wakeup trigger” corresponds to a state in which both interrupt flag and wakeup trigger flag corresponding to the sensor P are “1”s. At the time t 0 , the processor acquires the data of the sensors P and Q. Next, in order to set the wakeup trigger flag for the next wakeup, the processor executes the process of S 436  represented in  FIG. 28 . At the time point t 0 , a minimal next deadline is time t 2 , and final next processing time among the next processing time before the next deadline t 2  is time t 1 . Accordingly, the processor sets the wakeup trigger flag of the sensor Q to “1”. However, at the time t 1 , since an interrupt request is not issued from the sensor Q due to the jitter, the processor is not woken up. The processor is woken up at time t 4  that is a further next period of the sensor Q by using the sensor Q as a wakeup trigger. At the time t 4 , the processor acquires the data of the sensors PQR. However, the data lifetime of the sensor R ends at time t 3 . As above, the sensor R acquisition process is delayed due to the jitter, and a loss of the data of the sensor R occurs. 
     The seventh embodiment can be applied to the control of the fourth embodiment. According to the seventh embodiment, the processing interval  44   b  registered in the management table  44  (see  FIG. 23 ) is registered as a value having a margin value Mz 1  that is the maximal value of the jitter being taken into account. In other words, a value acquired by subtracting the margin value Mz 1  from the processing interval is set as the processing interval  44   b . The margin value Mz 1  is a maximal value of the jitter in the direction of the advancement of time. By setting as such, the data generation time of each sensor necessarily deviates to the rear side, and accordingly, the loss of data according to the deviation of the data generation time to the front side as illustrated in  FIG. 39  does not occur. However, a case where a loss of data occurs also when such setting is executed is illustrated in  FIG. 40 . In other words, the case is a case where a jitter occurs at the data generation time of the sensor determined as a wakeup trigger. In the case illustrated in  FIG. 40 , the sensor P is selected as the wakeup trigger. The data generation time of the sensor P is delayed from time t 0  to time t 1 . For this reason, the processor  30  is woken up at the time t 1 . Between the time t 0  and the time t 1 , the lifetime of the data of the sensor Q ends. As above, in the case illustrated in  FIG. 40 , the acquisition process of the sensor Q is delayed due to the jitter, and a loss of the data of the sensor Q occurs. 
     As a solution for a case where the data generation time of the sensor selected as the wakeup trigger is shifted, according to the seventh embodiment, the data lifetime is used as a value having the margin value Mz 2  that is the maximal value of the jitter being taken into account in the calculation. In other words, a value acquired by subtracting the margin value Mz 2  from the data lifetime is used as the data lifetime in the calculation. The margin value Mz 2  is a maximal value of the jitter in the direction of the delay of time. Here, the margin values Mz 1  and Mz 2  may be the same value. In addition, in consideration of the accumulation of the jitter, according to the seventh embodiment, for the sensor selected as the wakeup trigger, the method of calculating the next processing time at the time of wakeup is changed. In other words, instead of adding the processing interval to the next processing time of the previous time, by adding the processing interval to the current time at the time of wakeup, the next processing time is acquired. In a case where a jitter occurs, by correcting the next processing time before the update to actual wakeup time at the wakeup of the processor and adding the processing interval to the corrected value, the accumulation of the jitter is prevented. 
       FIG. 41  is a flowchart that illustrates the operation sequence of an application program according to the seventh embodiment. Only a difference between the cases illustrated in  FIGS. 41 and 25  is that S 702  is added to the case illustrated in  FIG. 41 , and thus, duplicate description thereof will not be presented. In S 702 , the margin value Mz 2  is set and registered. 
       FIG. 42  is a flowchart that illustrates a management table registering routine according to the seventh embodiment. In the seventh embodiment, a value acquired by subtracting the margin value Mz 1  from the processing interval is set as the processing interval  44   b  (S 710 ). The other sequences are similar to those illustrated in  FIG. 26 , and thus, description thereof will not be presented. In the seventh embodiment, the processing sequence of the interrupt handler is the same as that illustrated in  FIG. 27 , and thus, duplicate description thereof will not be presented. 
       FIG. 43  is a flowchart that illustrates a wakeup trigger setting routine according to the seventh embodiment. Differences between the cases illustrated in  FIGS. 43 and 28  are S 722 , S 723 , S 725 , and S 728  represented in  FIG. 43 , and thus, duplicate description thereof will not be presented. The process of S 722  to S 727  is executed for each sensor ID. The processor determines whether or not both the interrupt flag and the wakeup trigger flag have “1” (S 722 ). In a case where a result of the determination is “Yes”, an interrupt request is generated from the sensor of which the wakeup trigger flag is set to “1”, and accordingly, the processor updates the next processing time with (the current time+the processing interval) (S 725 ). On the other hand, in a case where the result of the determination acquired in S 722  is “No”, it is determined whether or not an interrupt request is generated from this sensor ID by referring to the register value of the interrupt notification register  11  (S 723 ). In a case where a result of the determination acquired in S 723  is “Yes”, the processor updates the next processing time with (the next processing time+the processing interval) (S 724 ). While a sensor issuing an interrupt request is identified by comparing the current time with the next processing time in S 432  represented in  FIG. 28 , in the seventh embodiment, data acquisition control is executed in consideration of the jitter, and accordingly, the process of S 432  represented in  FIG. 28  is not employed. In S 728  represented in  FIG. 43 , the processor acquires a sensor ID having the largest next processing time among the next processing time that is smaller than a value acquired by subtracting the margin value Mz 2  from the minimal next deadline. Then, the processor sets the wakeup trigger flag of the acquired sensor ID to “1” (S 729 ). 
       FIG. 44  illustrates a timing diagram of the sensors P, Q, and R and the processor according to the seventh embodiment. Here, it is assumed that a jitter occurs in the sensor P. When the processor transits to the sleep state before the time t 0 , the sensor Q is selected as a sensor having the minimal next deadline. The reason for this is that the next deadline of the sensor Q is before the next deadline t 3  of the sensor P and the next deadline t 5  of the sensor R. While the sensor P is selected as the wakeup trigger in the case illustrated in  FIG. 40 , in the case illustrated in  FIG. 44 , the margin value Mz 2  is subtracted from the next deadline of the sensor Q, and accordingly, the sensor Q is selected as the wakeup trigger. Accordingly, at the time t 0 , the processor is woken up by using the sensor Q as the wakeup trigger and acquires the data of the sensor Q. As above, a loss of the data of the sensor Q, as in the case illustrated in  FIG. 40 , does not occur. In addition, since the sensor Q is the wakeup trigger sensor, the next processing time is updated by using the current time in the process of S 725 . However, a jitter does not occur in the sensor Q, and accordingly, a result of the update has no difference from that of the update process of S 724 . Next, in order to set the wakeup trigger flag for the next wakeup, the processor executes the process of S 728 . At the time point t 0 , the minimal next deadline is time t 2 , and the final next processing time among the next processing time before the next deadline t 2  is the time t 1 . Accordingly, the processor sets the wakeup trigger flag of the sensor Q to “1”. 
     At the time t 1 , the processor is woken up by using the sensor Q as a wakeup trigger. At the time t 1 , the processor acquires the data of the sensors P and Q. Since the sensor Q is the wakeup trigger sensor, the next processing time is updated by using the current time in the process of S 725 . However, since a jitter does not occur in the sensor Q, and a result of the update has no difference from that of the update process of S 724 . Next, in order to set the wakeup trigger flag for the next wakeup, the processor executes the process of S 728 . At the time point t 1 , the minimal next deadline is time t 5 , and the final next processing time among the next processing time before the next deadline t 5  is time t 3 . Accordingly, the processor sets the wakeup trigger flag of the sensor P to “1”. 
     The occurrence time of the interrupt request from the sensor P deviates from the time t 3  to time t 4  due to a jitter. For this reason, when it is the time t 4 , the processor is woken up by using the sensor P as a wakeup trigger and acquires the data of the sensors P and R. Since the sensor P is the wakeup trigger sensor, the next processing time is updated in the process of S 725 . In this update process, the next processing time t 3  before the update is corrected to the current time t 4  that is actual wakeup time, and the processing interval of the sensor P is added to the correction time t 4 . 
     According to the seventh embodiment, also in a case where a jitter occurs in the data generation period of the sensor, the number of times of execution of a transition of the processor between the sleep state and the active state can be decreased without any loss of the data, and the power consumption of the processor can be reduced. 
     Eighth Embodiment 
     According to an eighth embodiment, when the interrupt handlers INTHL 1  to INTHL 6  call the data acquisition processes RT 13  to RT 15  and RT 63  to RT 65 , by referring to the next processing time before the update in the data acquisition processes RT 13  to RT 15  and RT 63  to RT 65 , the data acquisition processes RT 13  to RT 15  and RT 63  to RT 65  can acquire the generation time of the sensor data. For this reason, the data generation time of each sensor can be presented to the user. 
     For example, in the timing diagram illustrated in  FIG. 3B , for the sensor A, the data generation time is time 0, time 80, time 160, time 240, time 320, and time 400, values stored in the next processing time before the execution of the data acquisition process are 0, 80, 160, 240, 320, and 400, and the data generation time and the next processing time coincide with each other. 
     For the sensor B, the data generation time is time 0, time 100, time 200, time 300, and time 400, and time at which the data acquisition process is executed is time 0, time 160, time 240, time 320, and time 400, which are different from the data generation time. In addition, values stored in the next processing time before the execution of the data acquisition process are 0, 100, 200, 300, and 400, which coincide with the data generation time. 
     For the sensor C, the data generation time is time 0, time 125, time 250, and time 375, and time at which the data acquisition process is executed is time 0, time 160, time 320, and time 400, which are different from the data generation time. In addition, values stored in the next processing time before the execution of the data acquisition process are 0, 125, 250, and 375, which coincide with the data generation time. 
     As above, the data acquisition time of each sensor coincides with the values stored in the next processing time of each sensor before the execution of the data acquisition process. For this reason, according to the eighth embodiment, at the time of calling the data acquisition processes RT 13  to RT 15  and RT 63  to RT 65 , the interrupt handlers INTHL 1  to INTHL 6  allows the registered next processing time of each sensor to be referred by or be provided for the data acquisition processes RT 13  to RT 15  and RT 63  to RT 65 . Accordingly, the data acquisition processes RT 13  to RT 15  and RT 63  to RT 65  can acquire the actual data generation time of each sensor. 
     According to the eighth embodiment, each of the data acquisition processes RT 13  to RT 15  and RT 63  to RT 65  can acquire the actual data generation time of each sensor. Accordingly, the actual data generation time of each sensor can be allowed to be acquired by the application program, and the actual data generation time of each sensor can be provided for the user. 
     Ninth Embodiment 
     In a ninth embodiment, a case is considered in which the processor  30  supports a plurality of stages of the sleep state. In addition, as in the fourth to sixth embodiments, a case is considered in which the wakeup intervals of the processor  30  are different between the plurality of stages. For example, a sleep state M 1  in which a transition time between the active state and the sleep state is short, but the power consumption is high and a sleep state M 2  in which the transition time is longer than that of the sleep state M 1 , but the power consumption is lower than that of the sleep state M 1  are supported. 
     When the processor  30  is caused to be in the sleep state, the application program determines one of the sleep states M 1  and M 2  for the transition based on a required time Tk until the next wakeup from time at which a transition to the sleep state is made. In a case where the required time Tk is shorter than a threshold Ct, the application program selects the sleep state M 1  having a shorter transition time. On the other hand, in a case where the required time Tk is the threshold Ct or more, the application program selects the sleep state M 2  having low power consumption. 
     In the fourth to sixth embodiments, the required time Tk is calculated by acquiring the next processing time  44   c ,  45   c , and  46   c  corresponding to the sensor ID acquired in Steps S 436 , S 524 , and S 644  and calculating a time from the current time to the acquired next processing time. 
     According to the ninth embodiment, the required time Tk from the time at which a transition to the sleep state is made to the next wakeup is calculated, and the sleep state is selected based on the time Tk. Accordingly, the power consumption is reduced, and the state transition of the processor can be efficiently executed. In addition, it may be configured such that two or more threshold values are set, and switching among three or more sleep states is executed. 
     Tenth Embodiment 
     In the first to ninth embodiments, while the wakeup trigger setting routine is realized by software, the wakeup trigger setting routine may be realized by hardware. For example, in the case of the wakeup trigger setting routine illustrated in  FIG. 6 , a plurality of registers storing the processing interval of each sensor and a comparator calculating a minimum value of the register values of the plurality of registers are included, and the wakeup trigger register  12  is set based on an output of the comparator. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.