Patent Publication Number: US-2010127754-A1

Title: Power measurement circuit

Description:
FIELD 
     The application describes an average power measurement circuit, and more particularly a circuit constructed to provide a signal representing the average power provided at its input. 
     BACKGROUND 
     In signal processing it is often desirable and sometimes even necessary to provide an indication of signal power. For example, in high frequency RF wireless applications the RF carrier can be envelope modulated with a signal having a high crest factor; and under these and similar circumstances, it may be desirable to provide an indication of the average power provided by this signal. One technique is to apply the signal to a power measurement circuit which is designed to provide a signal representing the square of the input as an indication of its average power, which is an accurate measure regardless of the signal&#39;s crest factor. Such as an approach is described in U.S. Published Application No. 2008/0136491 dated Jun. 12, 2008, based upon an application filed on Dec. 6, 2006 in the name of Min Z. Zou, and assigned to the present assignee, wherein a squaring cell (x 2 ) is coupled to an averaging RC filter in order to provide the power measurement based on a measure of the average power input. Other circuit power measurement implementations are shown and described in U.S. Pat. No. 4,639,623 issued to Pullen on Jan. 27, 1987, and U.S. Pat. No. 6,172,549 issued to Gilbert on Jan. 9, 2001 (the “Gilbert Patent”). 
     In some RF applications, RF signals routed on a circuit board are single-ended, and must interface with the differential input of a power measurement circuit through an interface in the form of a balun transformer, which increases the cost and complexity of the circuit. It is desirable to provide a power measurement circuit which is provided with a single-ended input eliminating the need for a balun transformer. 
     SUMMARY 
     A power measurement circuit comprises: a transconductance rectifier arrangement including an input and configured to receive a sinusoidal input voltage signal; and an averaging filter for producing a time averaged DC output signal proportional to the mean square of the voltage at the input of the transconductance rectifier arrangement and representative of the average power of the input voltage signal within a range of voltages at the input. 
    
    
     
       GENERAL DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a general diagram, partially in block form and partially in schematic form, of the power measurement circuit described herein; 
         FIG. 2  is a schematic diagram of a basic transconductance rectifier; 
         FIG. 3  is a schematic diagram of one embodiment of the transconductance rectifier arrangement; 
         FIG. 4  is a graphical illustration of the output current of a transconductance rectifier for a 10 MHz Sinusoidal Input;; 
         FIG. 5  is a graphical illustration of a time averaged output current vs. input sinusoidal amplitude; 
         FIG. 6  is a graphical illustration of an example of deviation in time average output current from an ideal square; 
         FIG. 7  is a schematic diagram of an example of a transconductance rectifier configuration having an extended range; 
         FIG. 8  is a schematic diagram of an embodiment of a transconductance rectifier with an extended range; 
         FIG. 9  is a schematic diagram of an example of deviation in time average output current from an ideal square for a transconductance rectifier having an extended range; 
         FIG. 10  is a schematic diagram of a transconductance rectifier having an extended range using n stages; 
         FIG. 11  is a schematic diagram of a common-base transconductance rectifier; 
         FIG. 12  is a schematic diagram of a common-base transconductance rectifier with an extended range; 
         FIG. 13  is a schematic diagram of an extended range common-base transconductance rectifier implementation; 
         FIG. 14  is a schematic diagram of a multiple stage common-base transconductance rectifier; 
         FIG. 15  is a schematic diagram of a PNP transconductance rectifier; 
         FIG. 16  is a schematic diagram of a PNP transconductance rectifier; 
         FIG. 17  is a schematic diagram of a P-Channel MOSFET transconductance rectifier; 
         FIG. 18  is a schematic diagram of a N-Channel MOSFET transconductance rectifier; and 
         FIG. 19  is a schematic diagram of a P-Channel JFET or MESFET transconductance rectifier. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     In the drawings,  FIG. 1  shows a general block diagram of the preferred embodiment of the power measurement circuit  30 . As shown an input voltage Vin is applied to the input of a transconductance rectifier arrangement  32  having a special transconductance rectifier function F(x). The output of arrangement  32  is applied in turn to the input of an averaging filter  34  for producing a time averaged DC output signal proportional to the mean square of the voltage Vin at the input of the arrangement  32 . 
     The transconductance rectifier arrangement can take many forms with one being shown in  FIG. 2 . In  FIG. 2 , the transistor  40  receives a bias current I x  and provides a rectified current I o  as a function of the input sinusoidal voltage V in  applied to the base of the transistor (where V cm  is a bias voltage). This results in current flowing through the resistor  42  coupled between the emitter of the transistor  40  and system ground. This arrangement provides a single-ended transconductance rectifier circuit that eliminates the need for an external balun transformer. When the collector of transistor  40  is coupled to an averaging filter (not shown in  FIG. 2 ), the resulting circuit produces a voltage at the filter output which is proportional to the average power of the input sinusoidal signal V in . The relationship is further understood from the following: 
     If I C40 ·R 42 &lt;&lt;V T , 
         I   C50   =I   S   ·e   (Vcm+Vin)/Vt   =Io·e   Vin/Vt    (1) 
     wherein: 
     I c50  is the collector current through transistor  40  (amps); 
     R 52  is the resistance value of the transistor (ohms); 
     V T  is the voltage across the resistor  42  (volts); 
     I s  is the current ______ (amps); 
     V in  is the input voltage at the base of the transistor  50  (volts); 
     V cm  is the bias voltage applied at the base-collector of transistor  50  (volts); and 
     V t  is the voltage ______ (volts). 
     If it is assumed that Vin is periodic and time symmetric with 50% duty cycle, such as a modulated sinusoidal RF carrier, then the amplitude of the carrier is practically the same one-half cycle later, given that the bandwidth of the modulation is small compared to the carrier frequency ω c . 
       Vin(ω c t)∝sin(ω c t+π)≈−sin(ω c t)   (2) 
     Then I OUT  for one half cycle can be written: 
     
       
         
           
             
               
                 
                   
                     I 
                     OUT 
                   
                   = 
                   
                     
                       1 
                       2 
                     
                     · 
                     Io 
                     · 
                     
                       { 
                       
                         1 
                         + 
                         
                           Vin 
                           Vt 
                         
                         + 
                         
                           
                             1 
                             2 
                           
                           · 
                           
                             
                               ( 
                               
                                 Vin 
                                 Vt 
                               
                               ) 
                             
                             2 
                           
                         
                         + 
                         
                           
                             1 
                             6 
                           
                           · 
                           
                             
                               ( 
                               
                                 Vin 
                                 Vt 
                               
                               ) 
                             
                             3 
                           
                         
                         + 
                         
                           
                             1 
                             24 
                           
                           · 
                           
                             
                               ( 
                               
                                 Vin 
                                 Vt 
                               
                               ) 
                             
                             4 
                           
                         
                         + 
                         
                           ( 
                           
                             Higher 
                              
                             
                                 
                             
                              
                             order 
                           
                           } 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     And I OUT  for the next half cycle can be written: 
     
       
         
           
             
               
                 
                   
                     I 
                     OUT 
                   
                   = 
                   
                     
                       1 
                       2 
                     
                     · 
                     Io 
                     · 
                     
                       { 
                       
                         1 
                         - 
                         
                           Vin 
                           Vt 
                         
                         + 
                         
                           
                             1 
                             2 
                           
                           · 
                           
                             
                               ( 
                               
                                 Vin 
                                 Vt 
                               
                               ) 
                             
                             2 
                           
                         
                         - 
                         
                           
                             1 
                             6 
                           
                           · 
                           
                             
                               ( 
                               
                                 Vin 
                                 Vt 
                               
                               ) 
                             
                             3 
                           
                         
                         + 
                         
                           
                             1 
                             24 
                           
                           · 
                           
                             
                               ( 
                               
                                 Vin 
                                 Vt 
                               
                               ) 
                             
                             4 
                           
                         
                         + 
                         
                           ( 
                           
                             Higher 
                              
                             
                                 
                             
                              
                             order 
                           
                           } 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     wherein I OUT  is ______. 
     Integrating these currents across one cycle, the odd order terms cancel, leaving the following: 
     
       
         
           
             
               
                 
                   
                     I 
                     OUT 
                   
                   = 
                   
                     Io 
                     · 
                     
                       { 
                       
                         1 
                         + 
                         
                           
                             1 
                             2 
                           
                           · 
                           
                             
                               ( 
                               
                                 Vin 
                                 Vt 
                               
                               ) 
                             
                             2 
                           
                         
                         + 
                         
                           
                             1 
                             24 
                           
                           · 
                           
                             
                               ( 
                               
                                 Vin 
                                 Vt 
                               
                               ) 
                             
                             4 
                           
                         
                         + 
                         
                           ( 
                           
                             Higher 
                              
                             
                                 
                             
                              
                             order 
                           
                           } 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   
                     I 
                     OUT 
                   
                   = 
                   
                     Io 
                     + 
                     Ix 
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
             
               
                 
                   
                     Ix 
                     ≈ 
                     
                       
                         1 
                         2 
                       
                       · 
                       Io 
                       · 
                       
                         
                           ( 
                           
                             Vin 
                             Vt 
                           
                           ) 
                         
                         2 
                       
                     
                   
                   , 
                   
                     
 
                   
                    
                   
                     and 
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                      
                     if 
                      
                     
                         
                     
                      
                     
                       
                         I 
                         
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                       R 
                     
                      
                     
                         
                     
                      
                     1 
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                      
                     
                         
                     
                      
                     
                       V 
                       T 
                     
                   
                   , 
                   
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                     ≈ 
                     
                       Vin 
                       
                         R 
                          
                         
                             
                         
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                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     A specific implementation of  FIG. 1  using the rectifier of  FIG. 2  is shown in  FIG. 3 . As shown, the sinusoidal voltage input V in  is applied to the input  50  of the circuit shown at  48 . The input  50  is applied through capacitor  52  to the base of transistor  20  so that capacitor  52  will block any DC component of the input voltage applied to the transistor base. The base of transistor  20  is also connected to resistor  54 , which in turn is applied to the junction of the emitter of transistor  58 , resistor  60 , and the capacitor  62 . The opposite end of resistor  60  is connected to the base of transistor  64 , with the emitter of transistor  64  being connected in turn to resistor  66 , while the collector of transistor  64  is connected to current source  68 . The other plate of capacitor  62  and other end of resistor  66  are connected together and to system ground shown at  70 , while the collector of transistor  58  and the current source  68  are both connected to the supply voltage Vcc input shown at  72 . The base of transistor  58  is connected to the collector of transistor  64 . Transistor  20  has its emitter connected through resistor  22  to system ground, while its collector is connected to the averaging filter  74 . Averaging filter  74  includes a load resistor  76  and capacitor  78  connected in parallel with one another between the collector of transistor  20  and the supply voltage input  72 . A second transistor shown at  80  has its base connected through resistor  82  to the junction formed between the emitter of transistor  58 , resistor  54  and capacitor  62 . The emitter of transistor  80  is connected through resistor  84  to system ground, while the collector is connected through load resistor  86  to the supply voltage input  72 . The circuit provides a differential output. i.e., the output of the circuit includes one output  90  provided at the junction of the load resistor  76  of the averaging filter  74  and the collector of transistor  20 , and a second output  92  provided at the junction between the load resistor  86  and the collector of transistor  80 . Thus, the output of the circuit is the difference between the signal levels at the two outputs  90  and  92 . 
     In the embodiment described, transistors  58  and  64  are connected form a current mirror. If transistors  64 ,  20  and  80  are identical and have the same emitter area, and the values of each of the resistors  66 ,  22  and  84  are the same, with the application of the supply voltage Vcc an identical reference or bias current Iref will flow in the collectors of each of the transistors  64 ,  20  and  80 . A DC bias current will also flow through for the resistors  60 ,  54  and  86 , and if all of these resistors are of the same value, the DC bias voltage generated across each of these resistors will be the same. This DC bias voltage across each resistor prevents shorting of the sinusoidal input signal. It should be appreciated that the reference currents flowing in the collectors of transistors  64 ,  20  and  80  can be scaled relative to one another by scaling the emitter areas of the transistors  58 ,  64 ,  20  and  80  and/or scaling the values of resistors  66 ,  22  and  84 . Similarly, the DC bias voltage applied across the resistors  60 ,  54  and  86  can also be scaled by scaling the values of the resistors. Of importance, the DC bias voltages should be set to insure that the entire sinusoidal signal applied at the input will always be processed as a single polarity signal throughout its entire cycle to ensure it is properly rectified by the transistor  20 . It should also be noted that the presence of transistor  58  also helps to keep the voltage V cm  appearing at the rectifier (transistor  20 ) stable. 
     The averaging filter  74  time averages the sinusoidal voltage applied across the filter. In one embodiment resistors  76  and  86  are preferably of equal value, resistors  22  and  84  are of equal value and the transistors  20  and  60  are identical with the same emitter areas, so that Iref though one leg of the circuit formed by transistor  20  and resistors  22  and  76  will be identical to the Iref flowing through the leg of the circuit formed by transistor  80  and resistors  84  and  86 . Similarly, the voltage Vref across each of the resistors  76  and  86  will be identical. The current though resistor  86  will only be this reference current. However, because of the presence of the capacitor  78  of the filter  74 , the current Ix will also be generated so as to create additional voltage Vsq across each of the filter elements representing the square of the input voltage. Thus, by comparing the difference between the two voltages at the outputs  90  and  92 , the Vref component of each is canceled leaving a signal representing Vsq. Finally, it should be noted that transistor  80  provided in the part of the circuit arrangement created by the resistors  84  and  86  compensates for temperature and process variations. 
       FIG. 4  is a graphical illustration showing an example of an output current waveform  100  of the transconductance amplifier in response to a 10 MHz sinusoidal input signal compared to the ideal square waveform of the input voltage  102 . It is important to note that although the output current waveform  104  does not look like the square of the input voltage, once it is time averaged by across the output filter (e.g., filter  74  in  FIG. 3 ), the result is a DC voltage proportional to the average of the square of the input signal voltage. 
       FIG. 5  is a graphical illustration of an example of an implementation of the circuit arrangement shown in  FIG. 3 , showing the response curve  200  plotting the time averaged output current I OUT  of the transconductance rectifier circuit arrangement in response to the input sinusoidal peak amplitude, compared to the ideal response  202  of the square of the input voltage in response to the same input.  FIG. 6  shows the deviation plot  300  of curve  200  from ideal square curve  202  using the data shown in the  FIG. 5  illustration. As can be seen the example, the circuit arrangement maintains square law conformance with a typical error of about ±0.5 db up to an input amplitude of about 250 mV. By choosing an optimal bias point and emitter resistance value for resistors  66 ,  22  and  84  (in  FIG. 3 ), the transition between the ideal square law and linear response is smoothed to give wider dynamic range. 
     It is possible to extend the input range of the circuit arrangement by replacing each of the transistors  20  and  80  and the corresponding emitter resistors  22  and  84  with two or more transistor stages and an offset voltage source, such as shown in  FIG. 7 . Specifically, in  FIG. 7 , the transistor  402  and  404  and their corresponding emitter resistors  406  and  408 , form a two stage arrangement  400  and would replace each of the transistors  20  and  80  and their corresponding emitter resistors  22  and  84 . The offset voltage source  410  is used to place different Vcm voltages on each of the transistors of each stage so that transistor  20  operates in one range, and transistor  64  operates in a different range. The offset voltage source  410  can be realized as shown in  FIG. 7  with a current source  412 , Ios, and a parallel RC connection (indicated at  414  and  416 ) allowing for both a DC path and low-loss RF path to the second stage of each arrangement. It should be clear that any number of stages can be used with a separate offset Referring to  FIG. 9 , an example of a deviation curve  500  in time average output current of an arrangement using two stages for each leg of the rectifier arrangement in  FIG. 8  shows that the circuit maintains square law performance with an error of ±0.5 db up to an input amplitude of about 500 mV, showing a 6 dB improvement over the deviation curve  300  (shown in  FIG. 6 ) of the single stage rectifier illustrated in  FIG. 3 . In principle this method of extending the input range can be accomplished with any number of transconductance rectifier stages having proper offset voltage sources and emitter degeneration resistors as illustrated at  600  in  FIG. 10 . 
     The input impedance of the rectifier circuit arrangement is very high and has a capacitive component from the base-emitter capacitance of the transistor used. It is possible to obtain a 50Ω input match to very high frequencies by using an equivalent shunt 50Ω resistance and a LC matching network to remove the base-emitter capacitive reactance. The input impedance is quite linear for the common-emitter rectifier circuit as shown in  FIG. 2 , typically achieving +16 dBm IIP3 (“third order intermodulation intercept point”). As shown in  FIG. 11 , it is also possible to substitute a common-base version of the rectifier for each of the transistors  44 ,  38 ,  20  and  60  of  FIG. 2 . As shown Vin is applied to the emitter of the rectifier  700 . In practice, the input would have a DC blocking capacitor so as not to disturb the bias point of the transistor replacing transistor  20 . One drawback of the common-base version is that the IIP3 is significantly lower at +2 dBm due to the non-linearity in the low emitter input impedance. 
     Similar to the common-emitter transconductance rectifier arrangement with an extended range, the range of the common-base version can also be extended in a similar manner with two or more common-base transconductance rectifiers with appropriate offset voltage sources (one being shown at  706  in  FIG. 12 ) replacing the transconductance rectifier of each leg referenced by the transistors  20  and  80  and corresponding emitter resistors  22  and  84  and in  FIG. 3 , respectfully.  FIG. 11  illustrates a two stage common-base transconductance rectifier with extended range, including the transistors  702  and  704  he base of both. An attenuation resistor  708  is connected between the two emitters of the two transistors. The emitter attenuation resistors  710  and  712  and the attenuation resistor  708  are chosen to simultaneously provide a  50  ohm input impedance matching to high frequency and proper scaling of the output currents such that the total current retains square law conformance over an extended range.  FIG. 13  shown an implementation of the  FIG. 12  arrangement, in which the resistor  720  is connected between the bases of transistors  702  and  704 , while a current source  722  is provided between the bases of transistors  702  and  704  and system ground. The arrangement  800  of more than two stages using the common-base arrangement is also possible as shown in  FIG. 14 . 
     In principle the transconductance rectifier concept can be extended to other transistor types provided with proper biasing.  FIG. 15  shows a PNP transistor used as a current sourcing transconductance rectifier arrangement  900 .  FIGS. 15-19  show the rectifier implemented with P and N channel enhancement MOSFET transistors  1002  and  1004 , and P and N channel enhancement JFET or MESFET transistors  1006  and  1008 , respectively. These devices have square-law dependence of the drain current with respect to the gate voltage and will thus produce a time averaged output current proportional to the square of the input gate voltage in like manner to the common-emitter and common-base rectifier arrangements. In addition, the transconductance rectifier arrangements using the other transistor types can be modified to extend the range of single stage arrangements for each leg, with two or more stages. It is clear to one skilled in the art that other transconductance devices can be substituted for each of the NPN transistors shown in  FIG. 3  to obtain similar function including depletion-mode devices with appropriate biasing circuits. 
     The foregoing provides a power measurement circuit designed to provide a measurement of average power, and capable of operating with a low supply voltage, making it ideal for battery operated devices. A further advantage is that the circuit does not require a balun transformer when a single-ended input signal is applied to the input of the circuit. Further, the circuit does not require a true square of input voltage to calculate average power of the input, as for example required by the circuit described in the Gilbert Patent. In addition, the added emitter resistance improves the detection range of the circuit, while the use of multiple detection stages further increases the detection range.