Patent Publication Number: US-10770130-B2

Title: Apparatuses and methods for maintaining a duty cycle error counter

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This application is a continuation of pending U.S. patent application Ser. No. 15/868,232, filed Jan. 11, 2018. The aforementioned application is incorporated herein by reference, in its entirety for any purpose. 
    
    
     BACKGROUND 
     Current and future generation DRAM and SDRAM applications utilize very high I/O speeds. As a result, the clock speeds are also very high. The high clock speeds may make aligning phases and setting duty cycles of clocks challenging, as timing windows and margin for error are both very narrow, and updates occurring quickly, leading to frequent counter updates and opportunities for introduction of errors in a counter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure. 
         FIG. 2  illustrates a schematic block diagram of a duty cycle correction (DCC) circuit in accordance with an embodiment of the disclosure. 
         FIG. 3  illustrates a schematic block diagram of a DCC circuit in accordance with an embodiment of the disclosure. 
         FIG. 4  illustrates a schematic block diagram of a counter circuit in accordance with an embodiment of the disclosure. 
         FIG. 5  illustrates a block diagram of a single bit cell of a counter circuit in accordance with an embodiment of the disclosure. 
         FIG. 6  illustrates a schematic block diagram of a single bit cell of a counter circuit in accordance with an embodiment of the disclosure. 
         FIG. 7  illustrates a flow diagram of a counter conversion from Gray code to binary code and from binary code to Gray code accordance with an embodiment of the disclosure. 
         FIGS. 8A-8C  include tables that compare Gray code and binary code counter changes in accordance with embodiments of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Certain details are set forth below to provide a sufficient understanding of embodiments of the disclosure. However, it will be clear to one having skill in the art that embodiments of the disclosure may be practiced without these particular details. Moreover, the particular embodiments of the present disclosure described herein are provided by way of example and should not be used to limit the scope of the disclosure to these particular embodiments. 
       FIG. 1  illustrates a schematic block diagram of a semiconductor device  100  in accordance with an embodiment of the present disclosure. The semiconductor device  100  includes a memory die. The memory die may include a command/address input circuit  105 , an address decoder  110 , a command decoder  115 , a clock input circuit  120 , internal clock generator  130 , row decoder  140 , column decoder  145 , memory arrays  150 , read/write amplifiers  155 , I/O circuit  160 , and power circuit  170 . 
     In some embodiments, the semiconductor device  100  may include, without limitation, a dynamic random-access memory (DRAM) device, such as double data rate (DDR) DDR4, DDR5, low power (LP) DDR, integrated into a single semiconductor chip, for example. The die may be mounted on an external substrate, for example, a memory module substrate, a mother board or the like. The semiconductor device  100  may further include a memory array  150 . The memory array  150  includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL and /BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by a row decoder  140  and the selection of the bit line BL is performed by a column decoder  145 . Sense amplifiers (SAMP) are located for their corresponding bit lines BL and /BL, and are connected to at least one respective local I/O line LIOT/B, which is in turn coupled to a respective one of at least two main I/O line pairs MIOT/B, via transfer gates (TG), which function as switches. 
     The semiconductor device  100  may employ a plurality of external terminals that include address and command terminals coupled to command/address bus (C/A), clock terminals CK and /CK, data terminals DQ, DQS, and DM, power supply terminals VDD, VSS, VDDQ, and VSSQ, and the ZQ calibration terminal (ZQ). 
     The command/address terminals may be supplied with an address signal and a bank address signal from outside. The address signal and the bank address signal supplied to the address terminals are transferred, via the command/address input circuit  105 , to an address decoder  110 . The address decoder  110  receives the address signal and supplies decoded address signals ADD to the row decoder  140  and the column decoder  145 . The decoded address signals ADD may include a decoded row address signal provided to the row decoder  140 , and a decoded column address signal provided to the column decoder  145 . The address decoder  110  also receives the bank address signal and supplies the bank address signal to the row decoder  140 , the column decoder  145 . 
     The command/address terminals may further be supplied with a command signal from outside, such as, for example, a memory controller. The command signal may be provided, via the C/A bus, to the command decoder  115  via the command/address input circuit  105 . The command decoder  115  decodes the command signal to generate various internal commands that include a row command signal ACT to select a word line and a column command signal, such as a read command or a write command Read/Write, to select a bit line, and a test mode signal. 
     Accordingly, when a read command is issued and a row address and a column address are timely supplied with the read command, read data is read from a memory cell in the memory array  150  designated by these row address and column address. The read data DQ is output to outside from the data terminals DQ (data), DQS (data strobe), and DM (data mask) via read/write amplifiers  155  and an input/output circuit  160 . Similarly, when the write command is issued and a row address and a column address are timely supplied with this command, and then write data is supplied to the data terminals DQ, DQS, DM, the write data is received by data receivers in the input/output circuit  160 , and supplied via the input/output circuit  160  and the read/write amplifiers  155  to the memory array  150  and written in the memory cell designated by the row address and the column address. 
     Turning to the explanation of the external terminals included in the semiconductor device  100 , the clock terminals CK and /CK are supplied with an external clock signal and a complementary external clock signal, respectively. The external clock signals (including complementary external clock signal) may be supplied to a clock input circuit  120 . The clock input circuit  120  may receive the external clock signals to generate an internal clock signal ICLK. The internal clock signal ICLK is supplied to an internal clock generator  130  and thus a phase controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK. Although not limited thereto, a delay-locked loop (DLL) circuit, a duty cycle correction (DCC) circuit, or a combination thereof may be used as the internal clock generator  130 . The phase controlled internal clock signal LCLK is supplied to the input/output circuit  160  and is used as a timing signal for determining an output timing of read data. In some examples, the clock generator  130  includes a DCC circuit configured to correct a duty cycle of the LCLK signal. The DCC circuit may include a counter that adjusts the duty cycle of the LCLK signal. The counter may include logic to store values using Gray code and logic that converts the Gray code to binary code prior to output and converts received binary code to Gray code. Storing values in the counter using Gray code may make the DCC circuit less susceptible to catastrophic failure events caused by corruption of one or more bits within the counter. One cause of bit corruption in a counter is situations where many bits within the counter transition in a single adjustment (e.g., decrement or increment). By using Gray code to encode bits in the counter, only a single bit is changed per adjustment of the counter. 
     For example,  FIGS. 8A-8C  include tables  801 - 806  that compare Gray code and binary code counter changes in accordance with embodiments of the disclosure. For example,  FIG. 8A  depicts a Gray code table  801  showing x1 value change and a binary code table  802  shows a corresponding x1 value change. For example, in the Gray code table  801  and the binary code table  802 , the counter value transitions from 127 to 128. In the Gray code table  801 , the transition  811  shows that only a single bit changes, while the binary code table  802  shows the transition includes every bit changing. Because of the number of bits changing in the binary code example, the chances that a catastrophic error could occur are increased, where if an error occurs in the Gray code example, the value merely stays at 128. 
       FIG. 8B  depicts a Gray code table  803  showing x4 value change and a binary code table  804  shows a corresponding x4 value change. In the Gray code table  803  and the binary code table  804 , the counter value can transition from a starting point  821   a  of 128 to 124 (e.g., decrement  821   b ) or 132 (e.g., increment  821   c ). The potential errors  823  in the two bits changing are 127, 131, or 135, none of which would be likely to cause a catastrophic error. Further, as shown in the binary code table  804 , even if the counter ended up being set to one of those three erroneous values, because the counter is in a x4 mode, the two lower bits could be masked, allowing the values to be reset to one of the expected values or the previous starting value (e.g., the error  824   a  would reset the erroneous 127 value to 124 at  822   b , the error  824   b  would reset the erroneous 131 to 128 at  822   a , the error  824   c  would reset the erroneous 135 value to 132 at  822   c ). 
       FIG. 8C  depicts a Gray code table  805  showing x8 value change and a binary code table  806  shows a corresponding x8 value change. In the Gray code table  805  and the binary code table  806 , the counter value can transition a starting point  831   a  of 128 to 120 (e.g., decrement  831   b ) or 136 (e.g., increment  831   c ). The potential errors  833  in the two bits changing are 127, 135, or 143, none of which would be likely to cause a catastrophic error. Further, as shown in the binary code table  804 , even if the counter ended up being set to one of those three erroneous values, because the counter is in a x8 mode, the three lower bits could be masked, allowing the values to be reset to one of the expected values or the previous starting value (e.g., the error  834   a  would reset the erroneous 127 value to 120 at  832   b , the error  834   b  would reset the erroneous 135 to 128 at  832   a , the error  834   c  would reset the erroneous 143 value to 136 at  832   c ). 
     The power supply terminals are supplied with power supply potentials VDD 2  and VSS. These power supply potentials VDD 2  and VSS are supplied to an internal voltage generator circuit  170 . The internal voltage generator circuit  170  generates various internal potentials VKK, VARY, VPERI, and the like based on the power supply potentials VDD 2  and VSS. The internal potential VKK is mainly used in the row decoder  140 , the internal potential VARY are mainly used in the sense amplifiers included in the memory array  150 , and the internal potential VPERI is used in many other circuit blocks. 
     The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are supplied to the input/output circuit  160 . The power supply potentials VDDQ and VSSQ are typically the same potentials as the power supply potentials VDD 2  and VSS, respectively. However, the dedicated power supply potentials VDDQ and VSSQ are used for the input/output circuit  160  so that power supply noise generated by the input/output circuit  160  does not propagate to the other circuit blocks. 
       FIG. 2  illustrates a schematic block diagram of a duty cycle correction DCC circuit  200  in accordance with an embodiment of the disclosure. The DCC circuit  200  includes a duty cycle adjust circuit DCA  210  and a duty cycle detect circuit DCD  220 . The internal clock generator  130  of  FIG. 1  may implement the DCC circuit  200 . 
     The DCA circuit  210  may receive the internal clock signal ICLK and a duty cycle error signal DCE from the DCD circuit  220 , and may adjust a duty cycle of the ICLK signal to provide a local clock LCLK. 
     The DCD circuit  220  may receive the LCLK signal and may detect a duty cycle error (DCE) and provide the DCE signal to the DCA circuit  210 . In some examples, the DCD circuit  220  may include a counter that is configured to store bits using Gray code. The counter may include binary-to-Gray code converters and Gray-to-binary code converters. In response to control signals to adjust (e.g., increment or decrement) the counter, the counter may encode and decode the individual bits stored in the counter using the binary-to-Gray code converters and the Gray-to-binary code converters. In some examples, the counter may also receive control signals to shift the counter in steps other than a x1 step, such as x4, x8, etc., steps. The DCD circuit  220  may determine the DCE signal value during a duty cycle detection operation. 
     In operation, DCC circuit  200  is configured to modify a duty cycle of the ICLK signal to provide the LCLK signal such that the duty cycle of the LCLK signal allows successful communication with connected devices. The DCA circuit  210  may adjust a duty cycle of the ICLK signal based on the DCE signal to provide the LCLK signal. 
     The DCD circuit  220  may analyze the LCLK to determine the duty cycle error and set the DCE signal based on the detected duty cycle error during a duty cycle detection operation. In some examples, a duty cycle detection operation may only take place during specific time periods, such as after a power up. The duty cycle detection operation may be set for a specific time period. In some examples, the duty cycle detection operation may be set for 6, 8, 10, or more clock cycles of the LCLK signal. In some examples, the DCD circuit  220  may include a duty cycle detector that detects a duty cycle of the LCLK signal. The detected duty detector may express a duty cycle error as a ratio of time the LCLK signal is high versus the time the LCLK signal is low during a single clock cycle. An ideal ratio is 1:1 or 50% to 50%. If the duty cycle error has a value other than a 1:1 ratio, the duty cycle may need to be adjusted. The DCD circuit  220  may include a shift register or counter that keeps track of a current duty cycle error. The counter may be adjusted (e.g., incremented or decremented) as a detected duty cycle error changes. The value of the counter may be used to set a value of the DCE signal. The binary-to-Gray code converters may encode bit values stored in the counters, and the Gray-to-binary code converters may provide bits between individual bit cells of the counter. In some examples, the counter adjust by one bit at a time. In other examples, the counter may adjust by larger step sizes, such as x4, x8, etc., steps based on control signals. Storing values in the counter using Gray code may make the DCC circuit  200  less susceptible to catastrophic failure events caused by corruption of one or more bits within the counter. One cause of bit corruption in a counter is situations where many bits within the counter transition in a single adjustment (e.g., decrement or increment), especially in the presence of a timing hazard, e.g., setup time violation or an unexpected clock glitch. By using Gray code to encode bits in the counter, only a single bit is changed per adjustment of the counter, mitigating a failure caused by improper bit switching. 
       FIG. 3  illustrates a schematic block diagram of a DCC circuit  300  in accordance with an embodiment of the disclosure. The DCC circuit  300  includes a duty cycle adjust circuit DCA  310  and a duty cycle detect circuit DCD  320 . The internal clock generator  130  of  FIG. 1  and/or the DCC circuit  200  of  FIG. 2  may implement the DCC circuit  300 . 
     The DCA circuit  310  may receive the internal clock signal ICLK and a duty cycle error signal DCE from the DCD circuit  320 , and may adjust a duty cycle of the ICLK signal to provide a local clock signal LCLK. 
     The DCD circuit  320  may include a duty cycle detector  322 , a control/filter circuit  324 , a counter  326 , and decode logic  328 . The duty cycle detector  322  may receive the LCLK signal and may detect a duty cycle error (DCE) and provide an increment/decrement signal INCREASE/DECREASE to the control/filter circuit  324  indicating whether the LCLK signal has a duty cycle error. The control/filter circuit  324  may provide control signals CONTROL to the counter  326  to initialize the counter  326  after a power up, and as well as cause the counter  326  to adjust (e.g., increment or decrement). The counter  326  is configured to store a count value COUNT indicating a duty cycle error. The counter  326  may include bit cells that each include binary-to-Gray code converters and Gray-to-binary code converters to store a respective bits using Gray code. In response to control signals from the control/filter circuit  324  to adjust (e.g., increment or decrement) the counter  326 , the counter  326  may encode and decode the individual bits using the binary-to-Gray code converters and the Gray-to-binary code converters. In some examples, the control/filter circuit  324  may also provide control signals to the counter to cause the counter  326  to adjust in steps other than a x1 bit step, such as x4 bit, x8 bit, etc., steps. The decode logic  328  may receive a count value COUNT provided by the counter  326  and may provide a value on the DCE signal. 
     In operation, DCC circuit  300  is configured to modify a duty cycle of the ICLK signal to provide the LCLK signal such that the duty cycle of the LCLK signal allows successful communication with connected devices. The DCA circuit  310  may adjust a duty cycle of the ICLK signal based on the DCE signal to provide the LCLK signal. 
     The duty cycle detector  322  may analyze the LCLK to determine the duty cycle error and set the increment/decrement signal INCREASE/DECREASE based on the detected duty cycle error during a duty cycle detection operation. In some examples, a duty cycle detection operation may only take place during specific time periods, such as after a power up. The duty cycle detection operation may be set for a specific time period. In some examples, the duty cycle detection operation may be set for 6, 8, 10, or more clock cycles of the LCLK signal. The duty cycle detector  322  may express a duty cycle error as a ratio of time the LCLK signal is high versus the time the LCLK signal is low during a single clock cycle. An ideal ratio is 1:1 or 50% to 50%. If the duty cycle error has a value other than a 1:1 ratio, the duty cycle may need to be adjusted. The control/filter circuit  324  may initialize the counter  326  using control signals after a power up or based on other predefined events, in some examples. In response to the increment/decrement signal from the duty cycle detector  322 , the control/filter circuit  324  may also provide control signals CONTROL that include an UP/DOWN signal to the counter  326  to cause the counter  326  to adjust. The binary-to-Gray code converters of the counter  326  may encode bit values stored in the counters, and the Gray-to-binary code converters may provide bits between individual bit cells of the counter  326 . The control/filter circuit  324  may also provide control signals to the counter  326  to control the adjustment step size of the counter  326 . In some examples, the counter  326  adjust by one bit at a time. In other examples, the counter  326  may adjust by larger step sizes, such as x4 bit, x8 bit, etc., steps. The decode logic  328  may receive the count value COUNT from the counter  326 , and may decode the count value to set a value on the DCE signal. The  310  may adjust the duty cycle of the ICLK signal based on the DCE signal value. By using Gray code to encode bits in the counter  326 , only a single bit is changed per adjustment of the counter  326 , mitigating a failure caused by improper bit switching, especially in the event of an unpredicted timing hazard. 
       FIG. 4  illustrates a schematic block diagram of a counter circuit  400  in accordance with an embodiment of the disclosure. The counter circuit  400  includes a bit cells  410 ( 0 )-( 7 ). The internal clock generator  130  of  FIG. 1 , the DCC circuit  200  of  FIG. 2 , and/or the counter  326  of  FIG. 3  may implement the counter circuit  400 . While the counter circuit  400  includes 8 bit cells  410 ( 0 )-( 7 ), it is appreciated that the number of bits in the count circuit  400  may be increased or decreased without departing from the scope of the disclosure. 
     Conversion from Gray to binary code and from binary to Gray code is depicted in the logic flows diagrams  710  and  720 , respectively, of  FIG. 7 . As shown in the flow diagram  710 , the bitwise conversion of each bit from Gray code G0:G7 to binary code B0:B7 is an XOR logic comparison between a same order bit of the Gray code G0:G7 with a next higher order bit of the binary code B0:B7, starting with the highest order bit of the binary code B7 equal to the highest order bit of the Gray code G7. For example, the B6 bit is based on the G6 bit compared with the B7 bit (equal to the G7 bit provided from the XOR7 logic) using XOR6 logic; the B5 bit is based on the G5 bit compared with the B6 bit using the XOR5 logic; the B4 bit is based on the G4 bit compared with the B5 bit using the XOR4 logic; and so on. Thus, the Gray-to-binary conversion, as shown in the flow chart  710 , is a sequential conversion starting with the highest order bit of the Gray code G7. As shown in the flow diagram  720 , the bitwise conversion of each bit from binary code B0:B7 to Gray code G0:G7 is an XOR logic comparison between a same order bit and a next higher order bit of the binary code B0:B7, starting with the highest order bit of the Gray code G7 equal to the highest order bit of the binary code B7. For example, the G6 bit is based on the B6 bit compared with the B7 bit using XOR6 logic; the G5 bit is based on the B5 bit compared with the B6 bit using XOR5 logic; the G4 bit is based on the B4 bit compared with the B5 bit using XOR4 logic; and so on. Thus, the binary-to-Gray conversion, as shown in the flow chart  720 , can be a simultaneous conversion of all binary code bits to Gray code bits. Therefore, as shown in  FIG. 7 , in order for the counter circuit  400  to be a synchronous counter that stores bit information using Gray code and outputs bit information using binary code, each of the bit cells  410 ( 0 )-( 7 ) may perform conversions based on information from adjacent bit cells, including projected binary bit values for a counter increment and for a counter decrement. 
     Thus, each of the bit cells  410 ( 0 )-( 7 ) may pass respective signals to adjacent bit cells, including a current bit value signal B&lt;1:7&gt;, a next state bit value up BUP&lt;1:7&gt; (e.g., indicates a next bit state value for the bit B&lt;1:7&gt;), a next state bit value down BDN&lt;1:7&gt; (e.g., indicates a next bit state value for the bit B&lt;0:7&gt; using active low logic), an active low increment count signal UPCF&lt;0:6&gt; (e.g., indicates whether a next bit value of the B&lt;0:7&gt; is a logical high or logical low value for the current bit cell), an active low decrement count signal DNCF&lt;0:6&gt; (e.g., indicates whether a next bit value of the B&lt;0:7&gt; is a logical high or logical low value for the current bit cell using active low logic), and an internal step size control signal CTRLIN&lt;1:7&gt;. Each of the bit cells  410 ( 0 )-( 7 ) may also receive a common an UP/DOWN signal to indicate an increment or decrement of the counter circuit  400 , and a common clock signal CLK to synchronize adjustment of each bit cell  410 ( 0 )-( 7 ) of the counter circuit  400 . Each of the bit cells  410 ( 0 )-( 7 ) may further include a control signal CTRL&lt;0:7&gt; signal to set a step size of the counter circuit  400 . A reset signal RST is also provided to each of the bit cells  410 ( 0 )-( 7 ) to reset the value of the bit cells, for example, to an initial value. The counter may provide an output signal OUT&lt;0:7&gt; indicating a count value. 
     In operation, each of the bit cells  410 ( 0 )-( 7 ) of the counter may receive the UP/DOWN signal and the CLK signal, and the counter circuit  400  may adjust (e.g., increment or decrement) the OUT&lt;0:7&gt; signal value based on the UP/DOWN signal and in response to the CLK signal. Each of the bit cells  410 ( 0 )-( 7 ) may store a count value using Gray code encoding, and may pass bit values between individual bit cells  410 ( 0 )-( 7 ) using binary code encoding. To covert between binary code encoding and Gray code encoding, and vice versa, each of the bit cells  410 ( 0 )-( 7 ) may include respective binary-to-Gray code converters and Gray-to-binary code converters. For a bit of a bit cell, a conversion between binary code and Gray code includes an exclusive OR XOR of a value of a next binary state value of the bit of the bit cell and a next state value of a bit of a subsequent bit cell (e.g., next higher order bit cell). Further, a conversion between Gray code and binary code includes an XOR of a value of a current Gray code bit of the bit cell and a binary bit value of a subsequent bit cell (e.g., next higher order bit cell). The B&lt;0:7&gt;, BUP&lt;0:7&gt;, BDN&lt;0:7&gt;, UPCF&lt;0:6&gt;, and DNCF&lt;0:6&gt; signals may be used to perform the Gray-to-binary conversions and the binary-to-Gray conversions. The CTRLIN&lt;0:7&gt; signals may be used to set a step size such that lower bits may be disabled during an adjustment of the counter circuit  400 . For example, the CTRL&lt;0:1&gt; signals may be set to disable the bit cells  410 ( 0 )-( 1 ) to implement a x4 bit step. Other step sizes may be implemented using other combinations of the CTRL&lt;0:7&gt; signals. The CTRLIN&lt;0:7&gt; signals may indicate whether a previous (e.g., next lower order) bit cell  410 ( 0 )-( 7 ) is disabled for the adjustment of the counter circuit  400 . By including logic in the bit cells  410 ( 0 )-( 7 ) to encode stored bits using Gray code, only a single bit in the counter  400  is changed per adjustment of the counter  400 , mitigating a failure caused by improper bit switching during an adjustment. 
       FIG. 5  illustrates a block diagram of a single bit cell  500  of a counter circuit in accordance with an embodiment of the disclosure. The bit cell  500  may include a binary-to-Gray code converter  510 , a flip-flop  520 , and a Gray-to-binary code converter  530 . The bit cell  500  may be implemented in any combination of the bit cells  410 ( 0 )-( 7 ) of  FIG. 4 . In the foregoing description, the &lt;X&gt; indicates a value from the current bit cell, the &lt;X−1&gt; indicates a value from a previous bit cell (e.g., next lower order bit cell), and &lt;X+1&gt; indicates a value from a subsequent bit cell (e.g., next higher order bit cell). If the bit cell is a first bit cell, the previous bit cell values may have logical zero values (e.g., a low value for an active high signal and a high value for an active low signal). If the bit cell is a last bit cell, the subsequent bit cell values may have logical zero values (e.g., a low value for an active high signal and a high value for an active low signal). 
     The binary-to-Gray code converter  510  may receive the UP/DOWN signal (e.g., indicating whether the counter adjustment is an increment or decrement), the UPCF&lt;X−1&gt; signal, the BUP&lt;X+1&gt; signal, the BDN&lt;X+1&gt; signal, the B&lt;X&gt; signal, the DNCF&lt;X−1&gt; signal, the CTRL&lt;X&gt; signal, and an output signal OUT&lt;X&gt; from the Gray-to-binary code converter  530 . Based on the received the UPCF&lt;X−1&gt;, BUP&lt;X+1&gt;, BDN&lt;X+1&gt;, DNCF&lt;X−1&gt;, OUT&lt;X&gt; signals, the binary-to-Gray code converter  510  may provide an active low next Gray code bit value signal GNXTF to the flip-flop  520 . The binary-to-Gray code converter  510  may also provide the UPCF&lt;X&gt; and DNCF&lt;X&gt; signals based on the UPCF&lt;X−1&gt; and DNCF &lt;X−1&gt; signals, respectively, and on the CTRL&lt;X&gt; signal. The UPCF&lt;X&gt; and DNCF&lt;X&gt; signals may be provided to a subsequent bit cell (e.g., next higher order bit cell). The binary-to-Gray code converter  510  may include logic circuitry to determine the value of the GNXTF signal, including XOR logic gates. 
     The flip-flop  520  may receive the GNXTF signal at a DF input and the CLK signal at a CLK input. In response to the CLK signal, the flip-flop  520  may provide a Gray code bit signal G from a Q output having a value based on a value of the GNXTF signal. The flip-flop  520  may be reset by the RST signal to an initial state, for example, when the bit cell  500  is initialized. 
     The Gray-to-binary code converter  530  may receive the G signal, the B&lt;X+1&gt; signal, and the CTRL&lt;X&gt; and CTRLIN&lt;X+1&gt; signals. Based on the G signal and the B&lt;X+1&gt; signal, the Gray-to-binary code converter  530  may set an output bit value B&lt;X&gt;. Based on the CTRL&lt;X&gt; and CTRLIN&lt;X+1&gt; signals and the B&lt;X&gt; signal, the Gray-to-binary code converter  530  may provide an output signal OUT&lt;X&gt;. The CTRL&lt;X&gt; and CTRLIN&lt;X+1&gt; signals may indicate whether the current bit cell is disabled. The Gray-to-binary code converter  530  may include logic circuitry to determine the value of the GNXTF signal, including XOR logic gates. By including the binary-to-Gray code converter  510  and the flip-flop  520 , along with the Gray-to-binary code converter  530 , in the bit cell  500  to store the G signal bit as a Gray code encoded bit, only a single bit in the counter is changed per adjustment of the counter, mitigating a failure caused by improper bit switching during an adjustment. 
       FIG. 6  illustrates a schematic block diagram of a single bit cell  600  of a counter circuit in accordance with an embodiment of the disclosure. The bit cell  600  may include a binary-to-Gray code converter  610 , a Gray-to-binary code converter  620 , and a flip-flop  650 . The bit cell  600  may be implemented in any combination of the bit cells binary-to-Gray code converter  610 ( 0 )-( 7 ) of  FIG. 4  and/or the bit cell  500  of  FIG. 5 . In the foregoing description, the &lt;X&gt; indicates a value from the current bit cell, the &lt;X−1&gt; indicates a value from a previous bit cell (e.g., next lower order bit cell), and &lt;X+1&gt; indicates a value from a subsequent bit cell (e.g., next higher order bit cell). 
     The binary-to-Gray code converter  610  may include an up logic circuit  630 , a binary-to-Gray code logic circuit  660 , and a down logic circuit  640 . The up logic circuit  630  may include a AND gate  631  coupled to a NOR gate  632 . The AND gate  631  may apply AND logic to the OUT&lt;X&gt; signal and the UPCF&lt;X−1&gt; signal inverted via the inverter  633  to provide an output signal. The NOR gate  632  may apply NOR logic to the CTRL&lt;X&gt; signal and the output of the AND gate  631  to provide the UPCF&lt;X&gt; signal. 
     The down logic circuit  640  may include a AND gate  641  coupled to a NOR gate  642 . The AND gate  641  may apply AND logic to the OUT&lt;X&gt; signal inverted via the inverter  618  and the DNCF&lt;X−1&gt; signal inverted via the inverter  643  to provide an output signal. The NOR gate  642  may apply NOR logic to the CTRL&lt;X&gt; signal and the output of the AND gate  641  to provide the DNCF&lt;X&gt; signal. The UPCF&lt;X−1&gt; and DNCF&lt;X−1&gt; signals may indicate to the bit cell  600  whether the previous (e.g., next lower order) bit cell binary bit value will increment or decrement during the next adjustment. The UPCF&lt;X&gt; and DNCF&lt;X&gt; signals may indicate to the subsequent bit cell whether the current bit cell binary bit value will increment or decrement during the next adjustment. 
     The binary-to-Gray code logic circuit  660  may include a multiplexer  611 , a multiplexer  612 , an inverter  613 , an inverter  614 , a XOR gate  615 , a XOR gate  616 , and a multiplexer  617 . The multiplexer  611 , inverter  613 , and XOR gate  615  may provide a next state Gray code bit value GUP should the next adjustment of the counter (e.g., via the UP/DOWN signal) indicate an increment. The multiplexer  612 , inverter  614 , and XOR gate  616  may provide a bit next state Gray code bit value GDN should the next adjustment of the counter indicate a decrement. The multiplexer  611  may provide one of the OUT&lt;X&gt; signal or the OUT&lt;X&gt; signal inverted by the inverter  618  based on a value of the UPC signal. The UPC signal may indicate whether the previous (e.g., next lower order) bit will increment if a next adjustment is an increment. The inverter  613  may invert the output of the multiplexer  611 , and the XOR gate  615  may apply XOR logic to the output of the inverter  613  and the next state increment binary bit value from the subsequent (e.g., next higher order) increment binary bit cell signal BUP&lt;X+1&gt; to provide the GUP signal. That is, if the output of the inverter  613  and the BUP&lt;X+1&gt; have different logical values, the GUP signal has a high logical value. Otherwise, the GUP signal has a low logical value. The multiplexer  612  may provide one of the OUT&lt;X&gt; signal or the OUT&lt;X&gt; signal inverted by the inverter  618  based on a value of the DNC signal. The DNC signal may indicate whether the previous (e.g., next lower order) bit will decrement if a next adjustment is a decrement. The inverter  614  may invert the output of the multiplexer  612 , and the XOR gate  616  may apply XOR logic to the output of the inverter  614  and the next state decrement binary bit value from the subsequent (e.g., next higher order) decrement binary bit cell signal BDN&lt;X+1&gt; to provide the GDN signal. That is, if the output of the inverter  614  and the BDN&lt;X+1&gt; have different logical values, the GDN signal has a high logical value. Otherwise, the GDN signal has a low logical value. The multiplexer  617  may provide one of the GUP or GDN signals at an output as an active low next state Gray code bit signal GNXTF to a DF input of the flip-flop  650  based on a value of the UP/DOWN signal. 
     The flip-flop  650  may provide the next state Gray code bit signal G at an output Q of the flip-flop  650  in response to the CLK signal received at the CLK input. The reset signal RST received at the RST input of the flip-flop  650  may reset the G signal provided from the Q output. 
     The Gray-to-binary code converter  620  may include a XOR gate  621 , a NAND gate  622 , an inverter  623 , a NOR gate  624 , and an inverter  625 . The XOR gate  621  may apply XOR logic to the G signal and the subsequent (e.g., next higher order) bit signal B&lt;X+I&gt; to provide a current binary bit signal B&lt;X&gt;. That is, if the G signal and the subsequent (e.g., next higher order) binary bit signal B&lt;X+1&gt; have different logical values, the B&lt;X&gt; signal has a high logical value. Otherwise, the B&lt;X&gt; signal has a low logical value. The NOR gate  624  may apply NOR logic to the CTRL&lt;X&gt; and CTRLIN&lt;X+1&gt; signals to generate the CTRLIN&lt;X&gt; signal via the inverter  625 . The NAND gate  622  may apply NAND logic to the B&lt;X&gt; signal and the output of the NOR gate  624  to provide the OUT&lt;X&gt; signal through inverter  623 . The CTRL&lt;X&gt; and CTRLIN&lt;X+1&gt; signals may be used to determine whether the bit cell  600  is disabled (e.g., prevented from toggling when larger step sizes are desired). 
     In operation, the bit cell  600  adjusts a Gray code bit value based on binary bit values of the bit cell  600  and bit values of adjacent bit cells. A bitwise conversion of a count value from Gray-to-binary code may involve a sequential conversion, wherein one bit conversion is used in a next lower order bit conversion (e.g., binary bit 7 is used with a Gray code bit 6 to determine binary bit 6, binary bit 6 is used with Gray code bit 5 to determine binary bit 5, etc.). To make the counter synchronous, the bit cell  600  may store the current Gray code bit value as the G signal, and may use next state binary bit values from adjacent bit cells to allow a synchronous increment and decrement of the counter. 
     The binary-to-Gray code converter  610  and the down logic circuit  640 , along with the multiplexer  611  and the multiplexer  612 , may provide the next bit state value of the B&lt;X&gt; signal as the BUP&lt;X&gt; (e.g., active high logic) and BDN&lt;X&gt; (e.g., active low logic) based on the UPCF&lt;X&gt;, DNCF&lt;X&gt;, and OUT&lt;X&gt; signals. 
     The inverter  613  and XOR gate  615  may provide next state Gray code bit value GUP should the next adjustment of the counter (e.g., via the UP/DOWN signal) indicate an increment based on the BUP&lt;X&gt; signal and the BUP&lt;X+1&gt; signal from the next higher order bit cell using XOR logic. The inverter  614  and XOR gate  616  may provide next state Gray code bit value GDN should the next adjustment of the counter (e.g., via the UP/DOWN signal) indicate a decrement based on the BDN&lt;X&gt; signal and the BDN&lt;X+1&gt; signal from the next higher order bit cell using XOR logic. The multiplexer  617  may provide one of the GUP or GDN signals at an output as an active low next state Gray code bit signal GNXTF to the flip-flop  650  based on a value of the UP/DOWN signal. 
     The flip-flop  650  may provide the next state Gray code bit signal G in response to the CLK signal. The XOR gate  621  may provide the B&lt;X&gt; signal based on the G signal and the subsequent (e.g., next higher order) bit signal B&lt;X+1&gt; using XOR logic. The NOR gate  624  and the NAND gate  622  may determine whether the B&lt;X&gt; signal is provided as the OUT&lt;X&gt; signal based on the CTRL&lt;X&gt; and CTRLIN&lt;X+1&gt; signals (e.g., determining whether the bit cell is enabled or disabled due to selection of step sizes other than 1× bit steps). 
     By including the binary-to-Gray code converter  610  and the Gray-to-binary code converter  620 , along with the flip-flop  650 , in the bit cell  600  to store the G signal bit as a Gray code encoded bit, only a single bit in the counter is changed per adjustment of the counter, mitigating a failure caused by improper bit switching during an adjustment, regardless of the selected increment size (e.g., x1, x4, x8, etc., step sizes). 
     From the foregoing it will be appreciated that, although specific embodiments of the disclosure have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Accordingly, the disclosure is not limited except as by the appended claims.