Patent Publication Number: US-11662755-B2

Title: Low-noise high efficiency bias generation circuits and method

Description:
CLAIMS OF PRIORITY—CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of commonly owned U.S. patent application Ser. No. 16/744,027 filed on Jan. 15, 2020, to issue on Nov. 30, 2021 as U.S. Pat. No. 11,188,106, incorporated herein by reference in its entirety; application Ser. No. 16/744,027 is a continuation of commonly owned U.S. patent application Ser. No. 16/143,142 filed on Sep. 26, 2018, now U.S. Pat. No. 10,571,940, issued Feb. 25, 2020, incorporated herein by reference in its entirety; application Ser. No. 16/142,142 is a continuation of commonly owned U.S. patent application Ser. No. 15/688,597 filed on Aug. 28, 2017, now U.S. Pat. No. 10,114,391, issued Oct. 30, 2018, incorporated herein by reference in its entirety; application Ser. No. 15/688,597 is a continuation of commonly owned U.S. patent application Ser. No. 15/059,206 filed on Mar. 2, 2016, now U.S. Pat. No. 9,778,669, issued Oct. 3, 2017, incorporated herein by reference in its entirety; application Ser. No. 15/059,206 is a continuation of commonly owned U.S. patent Ser. No. 14/462,193 filed on Aug. 18, 2014, now U.S. Pat. No. 9,429,969 issued Aug. 30, 2016, incorporated herein by reference in its entirety; application Ser. No. 14/462,193 is a continuation of commonly owned U.S. patent application Ser. No. 13/016,875 filed on Jan. 28, 2011, now U.S. Pat. No. 8,816,659 issued on Aug. 26, 2014, incorporated herein by reference in its entirety; application Ser. No. 13/016,875 claims the benefit under 35 U.S.C. § 119 (e) of U.S. Provisional Application No. 61/371,652, filed Aug. 6, 2010, entitled “Low-Noise High Efficiency Bias Generation Circuits and Method”, and U.S. Provisional Application No. 61/372,086, filed Aug. 9, 2010, entitled “Low-Noise High Efficiency Bias Generation Circuits and Method”; and the present continuation application is related to commonly-assigned U.S. application Ser. No. 13/054,781, filed Jan. 18, 2011, and entitled “Low-Noise High Efficiency Bias Generation Circuits and Method”, now U.S. Pat. No. 8,994,452, issued Mar. 31, 2015, said U.S. application Ser. No. 13/054,781 being the U.S. National Stage Filing pursuant to 35 U.S.C. § 371 of International Application Number PCT/US2009/004149 filed Jul. 17, 2009 (published by WIPO Jan. 21, 2010, as International Publication Number WO 2010/008586 A2), which application claims priority to U.S. application No. 61/135,279 filed Jul. 18, 2008 and entitled “Low Noise Charge Pump with Common-Mode Tuning Op Amp”, and the contents of all of the above-referenced provisional applications, publications, applications, and issued patents are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     Various embodiments described herein relate generally to bias signal generators and regulators including systems, and methods used in bias regulators. 
     BACKGROUND INFORMATION 
     It may be desirable to provide stable voltage and current signals to a variable load device, the present invention provides such signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a simplified block diagram of bias signal generation architecture according to various embodiments. 
         FIG.  2 A  is a simplified block diagram of a base bias signal generation module according to various embodiments. 
         FIG.  2 B  is a simplified diagram of a current source module according to various embodiments. 
         FIG.  2 C  is a simplified diagram of a current sink module according to various embodiments. 
         FIG.  3    is a block diagram of a positive voltage signal generation module according to various embodiments. 
         FIG.  4    is a block diagram of a negative voltage signal generation module according to various embodiments. 
         FIG.  5 A  is a block diagram of a voltage regulation module (VRM) according to various embodiments. 
         FIG.  5 B  is a simplified diagram of a voltage regulation module (VRM) according to various embodiments. 
         FIG.  6 A  is a block diagram of a bandgap reference module (BRM) according to various embodiments. 
         FIG.  6 B  is a simplified diagram of a bandgap reference module (BRM) according to various embodiments. 
         FIG.  7 A  is a block diagram of a reference voltage and current generator module (RVCGM) according to various embodiments. 
         FIG.  7 B  is a simplified diagram of a reference voltage and current generator module (RVCGM) according to various embodiments. 
         FIG.  8    is a simplified diagram of a start algorithm according to various embodiments. 
         FIG.  9 A  is simplified diagram of differential oscillator architecture according to various embodiments. 
         FIG.  9 B  is simplified diagram of a differential oscillator according to various embodiments. 
         FIG.  9 C  is simplified diagram of a differential oscillator buffer according to various embodiments. 
         FIG.  10    is simplified diagram of a symmetrical active resistor according to various embodiments. 
         FIG.  11 A  is simplified diagram of a P-bias voltage tracker according to various embodiments. 
         FIG.  11 B  is simplified diagram of a N-bias voltage tracker according to various embodiments. 
         FIG.  12    is simplified diagram of a positive voltage control signal generation module (VCSGM) according to various embodiments. 
         FIG.  13    is simplified diagram of a positive voltage charge pump generation module (PVCPGM) according to various embodiments. 
         FIGS.  14 A- 14 D  are simplified diagrams of a negative voltage control signal generation module (NCSGM)  410  according to various embodiments and the various components. 
         FIG.  15    is simplified diagram of a negative voltage charge pump generation module (NVCPGM)  440  according to various embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a simplified block diagram of bias signal generation architecture (“BSGA”)  10  according to various embodiments. The BSGA  10  includes a base bias signal generator module (“BBSGM”)  100 , a differential oscillator module (“DOM”)  200 , a positive voltage charge pump module (“PVCPM”)  300 , a negative voltage charge pump module (“NVCPM”)  400 , a positive voltage clamping module (“PVCM”)  15 , a negative voltage clamping module (“NVCM”)  17 , a power supply module  18 , and a switching module  22 . The power supply module  18  may provide a variable power supply signal VDD and the module  18  may include one or more batteries, capacitors or other electrical energy generation elements. The PSM  18  may be designed to supply a VDD signal having a predetermined voltage or current levels. The energy generation elements performance may vary as a function of temperature, load, age, and depletion level. For example, a single cell battery may initial provide a signal having a voltage level of about 4 volts and may degrade to less than 2 volts as the battery depletes and temperature or load fluctuates. 
     The BSGA  10  generates one or more signals VDD_LS, VSS for the switching module  22  where VDD_LS may be a positive rail supply signal and the VSS may be a negative rail supply signal. The load from the switching module  22  generally varies significantly as the module performs one or more switching events. For example, a switching module  22  including a radio frequency (RF) switch may have a nominal load between switching events and then a significant load with a quick rise time for the respective load, IN_SIGNAL. The BSGA  10  should be able to meet the load requirements of the switching module  22  while receiving a varying supply signal VDD from one or more power supply modules  18 . Further, the BSGA  10  should perform these functions using minimal energy (efficient power consumption) and provide little or no undesirable noise on the loads signals VDD_LS and VSS. 
     In an embodiment, the base bias signal generator module (“BBSGM”)  100 , the differential oscillator module (“DOM”)  200 , the positive voltage charge pump module (“PVCPM”)  300 , the negative voltage charge pump module (“NVCPM”)  400 , the positive voltage clamping module (“PVCM”)  15 , and the negative voltage clamping module (“NVCM”)  17  operate in whole or part to receive the VDD signal from the PSM  18  and efficiently generate the signals VDD_LS and VSS. The BBSGM  100  may receive a variable voltage signal VDD from PSM  18  and generate a plurality of stable bias signals BIASP 1 , BIASP 2 , BIASN 1 , BIASN 2 , and an internal, positive rail supply VDD_INT. In an embodiment, the BBSGM  100  may function with a received VDD signal having a voltage level from 2.3 volts to 5.5 volts. Accordingly, the BBSGM  100  may effectively regulate the power supply module  18  external supply signal VDD. 
     As shown in  FIG.  1   , the PVCM  15  may include several P-type diodes  11 A,  11 B, and resistors  12 A,  12 B,  12 C. In an embodiment, the signal VDD_LS is targeted to be about +3.4 Volts. Diode  11 A tightly couples the node VDD_LS to the node VPOS (the output of the positive voltage charge pump module  300 ) during a switching event. The diode  11 A may effectively bypass the resistors  12 A,  12 B,  12 C and any capacitance during a switching event. In an embodiment, the diode  11 A may have no voltage drop (0 volts across it) during steady state. VPOS provides the positive voltage signal to PVCM  15 . The resistors  12 A,  12 B, and  12 C may filter and limit the current draw from VPOS to VDD_LS. 
     The diode  11 A may be forward biased when the voltage level of VPOS is greater than the voltage level of VDD_LS. Diode  11 B is forward biased when the voltage level of the signal VDD_INT is greater than the voltage level of VDD_LS. Diode  11 B may effectively clamp or provides a floor value for VDD_LS given the voltage level of VDD_INT is nominally 2.3 Volts. In an embodiment, the diodes  11 A,  11 B may be CMOS field-effect transistor (FET)s. Diode  11 A may have a width of about 10 microns, a length of about 0.4 microns and number of channels (mt)=10, denoted as 10/0.4/mt=10. Using this nomenclature, Diode  11 B may be 10/0.4/mt=5 in an embodiment. Resistors  12 A,  12 B,  12 C may have a width/length/resultant resistance where length and width are in microns and resistance is in Kilo Ohms. Using this nomenclature in an embodiment resistors  12 A,  12 B,  12 C may be about 10.7/1.4/19.98, 5.3/1.4/9.982, 2.8/1.4/5.353, respectively. 
     As discussed below with reference to  FIG.  2 A , the BBSGM  100  may include a Voltage Regulator Module  110  (VRM), a Bandgap Reference Module  140  (BRM), a Reference Voltage and Current Generator Module  170  (RVCGM), and a Startup and Standby Module  190  (SSM). The VRM  110  may receive the variable voltage external signal VDD and generate a stable internal voltage signal VDD_INT_SB. The BRM  140  may receive the internal signal VDD_INT_SB and generate a stable reference signal (VBG). The Reference Voltage and Current Generator Module  170  (RVCGM) may receive the VBG and VDD_INT_SB signal and generate a first and second bias signal for P-type devices (BIASP 1 , BIASP 2 ) and a first and second bias signal for N-type devices (BIASN 1 , BIASN 2 ). 
     The DOM  200  may receive the stable bias signals BIASP 1 , BIASP 2 , BIASN 1 , BIASN 2 , and internal, positive rail supply VDD_INT generated by BBSGM  100  and generate one or more oscillation or clock signals OSC 1 , OSC 2 . In an embodiment, the DOM  200  may be a capacitively coupled three stage differential inverter ring as shown in  FIG.  9 A . In an embodiment, each stage  203 A may use coupling capacitors to separately drive P-MOS  204 E and N-MOS  204 F devices (as shown in  FIG.  9 B ). Other embodiments are also possible without differential inverters, by providing a single-ended to differential conversion in the output stage (not shown). 
     The PVCPM  300  may receive the stable bias signals BIASP 1 , BIASP 2 , VBG and internal, positive rail supply VDD_INT generated by BBSGM  100 , and OSC 1 , OSC 2  from the DOM. The PVPCM  300  provides a positive voltage signal output VPOS. In an embodiment, the switching module  22  may receive three voltage signals, a ground GND, a positive voltage signal VDD_LS, and a negative voltage signal VSS. The PVCPM VPOS signal provides for the regulated positive rail voltage VDD_LS. In an embodiment the signal VDD_LS is targeted to be about 3.4 volts. Switching modules  22  commonly include a large capacitance that must be driven within a strict time frame (within 5 us in an embodiment). 
     In an embodiment, the VSS signal recovery time (after a switching event) may affect the harmonic knee point (HKP) of a signal IN_SIGNAL switched by the switching module  22  to generate OUT_SIGNAL. In an embodiment, the VDD_LS signal recovery time after a switching event may affect the insertion loss of a signal IN_SIGNAL switched by the switching module  22  to generate OUT_SIGNAL. A VDD_LS signal fast settling time may reduce the switching module  22  switched signal IN_SIGNAL insertion loss. The NVCPM  400  generates a negative voltage signal VNEG. As noted, the NVCPM  400  ideally settles quickly (the VNEG voltage level is back to desired level(s)) after a load event (switching event in an embodiment)). As noted the signal settling time may affect the HKP of the switching module  22 . 
     As shown in  FIG.  1   , the NVCM  17  may include a P-type diode  11 C, and resistors  12 D,  12 E,  12 F. In an embodiment, the signal VSS is targeted to be about −3.4 Volts. Diode  11 C may tightly couple the node VSS to the node VNEG (the output of the negative voltage charge pump module  400 ) during a switching event. The diode  11 C may effectively bypass the resistors  12 D,  12 E,  12 F and any capacitance generated during a switching event. In an embodiment, the diode  11 C may have no voltage drop (0 volts across it) during steady state. VNEG provides the negative voltage signal to VSS. The resistors  12 D,  12 E, and  12 F may filter and limit the current draw from VNEG to VSS. The diode  11 C may be forward biased when the voltage level of VNEG is less than the voltage level of VSS. In an embodiment, the diode  11 C may be a CMOS field-effect transistor (FET). The Diode  11 C may be about 10/0.4/mt=10. Resistors  12 A,  12 B,  12 C may have a width/length/resultant resistance of about 10.7/1.4/19.98, 5.3/1.4/9.982, and 2.8/1.4/5.353, respectively. 
       FIG.  2 A  is a simplified block diagram of a Base Bias Signal Generation Module  100  according to various embodiments. As noted the BBSGM  100  may include a Voltage Regulator Module  110  (VRM), a Bandgap Reference Module  140  (BRM), a Reference Voltage and Current Generator Module  170  (RVCGM), and a Startup and Standby Module  190  (SSM). The VRM  110  receives the external, variable voltage signal VDD and regulates the voltage level to be about 2.3 volts in an embodiment. The VRM  110  provides the regulated voltage VDD_INT_SB to the BRM  140  and the RVCGM  170 . 
     The BRM  140  receives the reference voltage VDD_INT_SB signal and generates a VBG (bandgap voltage) signal of about 1.16V (in an embodiment) and passes the reference signal VBG to the RVCGM  170  and the VRM  110 . The VRM  110  may use the VBG signal to determine and set the level of the VDD_INT_SB. In an embodiment the VBG signal level is a function of physical diode element formation and resistor combination that comprises the BRM  140 . 
     The RVCGM  170  receives the VBG signal and the VDD_INT_SB signal and generates a reference current of about 1.2 uA (in an embodiment) and gate bias reference voltages BIASP 1 , BIASP 2 , BIASN 1 , and BIASN 2 .  FIG.  2 B  is a simplified diagram of a current source module  142  according to various embodiments. The current source CS-P  142  includes a plurality of cascaded P-type field-effect transistor (FET)s  141 A,  141 B. When the bias signals BIASP 1  and BIASP 2  are stable, the current generated by the cascaded FETs  141 A,  141 B is also stable, constant, and about 1.2 uA in an embodiment. In an embodiment, the bias gate signal BIASP 1  sets the level of the basis current. BIASP 2  provides higher output impedance to the CS-P  142 . In an embodiment, the P-FETs  141 A,  141 B may be about 4/2/mt=1, 4/2/mt=1 respectively. 
       FIG.  2 C  is a simplified diagram of a current sink module CS-N  172  according to various embodiments. The current source CS-N  172  includes a plurality of cascaded N-type field-effect transistor (FET)s  171 A,  171 B. When the bias signals BIASN 1  and BIASN 2  are stable, the current drawn by the cascaded FETs  171 A,  171 B may also be stable, constant, and about 1.2 uA. In an embodiment, the N-FETs  171 A,  171 B may be about 4/2/mt=1, 4/2/mt=1 respectively. The use of the CS-P and CS-N and respective gate bias signals BIASP 1 , BIASP 2 , BIASN 1 , BIASN 2  may reduce the usage of resistors and transistors to control current source and sink levels. 
     In an embodiment the CS-P  142  and the CS-N  172  are used in operational amplifiers (OPAMP) and operational trans-conductance amplifiers (OTA) in the VRM  110 , the BRM  140 , the DOM  200 , the PVCPM  300 , and the NVCPM  400 . The RVCGM  170  receives the VBG signal and may employ a known resistance to generate a signal with a known current, IREF. The RVCGM  170  also generates the gate bias voltages BIASP 1 , BIASP 2 , BIASN 1 , and BIASN 2 . 
     In an embodiment the BBSGM  100  may also include startup and standby components  190 ,  120 ,  150 ,  180 . As noted in an embodiment the VRM  110 , the BRM  140 , and the RVCGM  170  may provide reference signals to other modules DOM  200 , PVCPM  300 , NVCPM  400  Similarly the BRM  140  provides a reference signal to the VRM  110  and the RVCGM  170 . During a standby condition or startup, the SSM  190  may suppress the VDD_INT signal to stop operation of the DOM  200 , PVCPM  300 , NVCPM  400  modules. Such an interruption of the VDD_INT signal may reduce the power consumption of the architecture  10 . The BBSGM  100  may still operate in order to receive and process standby and wake signals. 
       FIG.  3    is a block diagram of a PVCPM  300  according to various embodiments. The PVCPM  300  may include a control module  310  and a charge pump module  340 . The control module  310  may receive the gate bias signals BIASP 1 , BIASP 2 , internal voltage signal VDD_INT, VBG and VDD_LS, and generate a control signal POS_CP_VDD representing a desired voltage signal level. The charge pump module  340  may receive the POS_CP_VDD signal and clock signals OSC 1 , OSC 2  and generate a positive voltage signal VPOS. 
       FIG.  4    is a block diagram of a NVCPM  400  according to various embodiments. The NVCPM  400  may include a control module  410  and a charge pump module  440 . The control module  410  may receive the gate bias signals BIASP 1 , BIASP 2 , BIASN 1 , BIASN 2 , internal voltage signal, VDD_INT, VBG and VSS and generate a control signal NEG_CP_VDD representing a desired voltage signal level. The charge pump  440  module may receive the NEG_CP_VDD signal, and clock signals OSC 1 , OSC 2 , and generate the negative voltage signal VNEG. 
       FIG.  5 A  is a block diagram of a voltage and current regulation module (VRM)  110  according to various embodiments. As shown in  FIG.  5 A , the VRM  110  may include an OTA  114 , an LDO  124 , a voltage divider  121 , a Schmitt trigger  112 , and a standby-startup module  130 . The voltage divider  121  may receive the internal voltage signal VDD_INT_SB as a feedback signal and generate a voltage signal about ½ the voltage signal VDD_INT_SB (½ VDD_INT) in one embodiment. The OTA  114  may receive the external voltage signal VDD, the internal bandgap reference signal VBG, and a voltage reference (½ VDD_INT) equal to half of the internal voltage VDD_INT_SB. The OTA  114  determines the differential between the signal VBG and ½ VDD_INT_SB. In an embodiment the VBG signal voltage level is about ½ the desired internal voltage of the signal VDD_INT_SB. Accordingly, the OTA differential signal represents the difference between the desired voltage level and the current voltage level of the VDD_INT_SB signal. 
     The OTA  114  generates an LDO control signal where the signal varies as a function of the determined voltage level differential signal. In an embodiment the low drop out (“LDO”) module  124  receives the VDD signal and generates the internal voltage signal VDD_INT_SB based on the LDO control signal generated by the OTA  114 . The Schmitt trigger  112  may be set to trip when the BIASP 1  signal reaches a desired voltage level. The BIASP 1  desired predetermined voltage level may indicate that the BB_SGM  100  is fully operational after a startup or standby event. The standby-startup module  130  may use the trigger  112  signal to determine the operational status of VRM  110  after a restart or standby event. 
       FIG.  5 B  is a simplified diagram of a voltage and current regulation module (VRM)  110  according to various embodiments. As shown in  FIG.  5 B , the VRM  110  may include an OTA  114 , a low drop out FET (LDO)  124 , a voltage divider  121 , and resistors  122 . The OTA  114  may include the CS-N  172  to create a current sink of about 1.2 uA in an embodiment. The OTA  114  also includes cascade intrinsic N-type FETs  117 A,  117 B, thicker film regular type P-type FETs (TRP)  118 A,  118 B, and regular type N-type FET (RN)  116 A,  116 B. The FETs  118 A,  118 B,  116 A,  116 B form a trans-impedance amplifier that determines the difference between the inputs at the gates of  116 A,  116 B. 
     The TINs  117 A,  117 B may be coupled at their respective gates. The reference signal VBG (about 1.16 V in an embodiment) may be received at gate  116 B. The other gate  116 A receives the divided voltage signal ½VDD_INT (half of the internal voltage signal VDD_INT_SB in an embodiment) from the voltage divider  121 . In an embodiment, the TRP-FETs  118 A,  118 B may be about 4/2/mt=1, 4/2/mt=1, respectively. The TIN-FETs  117 A,  117 B may be about 4/1/mt=1, 4/1/mt=1, respectively. The RN-FETs  116 A,  116 B may be about 4/2/mt=2, 4/2/mt=2, respectively. The cascade current sink N-FETs  115 A,  115 B may be about 4/2/mt=1, 4/2/mt=1, respectively as noted above. 
     The voltage divider  121  may include several resistors  123 A,  123 B. When the resistance of the resistors  123 A,  123 B are about equal, the gate of  116 A may be about ½ of the internal voltage signal VDD_INT_SB. In an embodiment the resistor  123 A may have a resistance of about 604 Kohms and may include multiple, coupled resistors including resistors that may be about 13.5/1.4/50.34/ms=2, and 13.5/1.4/553.7/ms=22, respectively. The resistor  123 B may have a resistance of about 604 Kohms and may include multiple, coupled resistors including resistors that may be about 13.5/1.4/25.17/ms=1, 13.5/1.4/75.51/ms=3, 13.5/1.4/302/ms=12, and 13.5/1.4/201.4/ms=8, respectively. 
     The LDO  124  is a TRP receiving its gate signal from the OTA  114 . The LDO  124  generates or regulates the internal voltage signal VDD_INT_SB based on the gate signal. In an embodiment, the LDO  124  TRP may be about 10/0.5/mt=8. Accordingly, the VRM  110  may receive an external signal VDD having a voltage range of 2.3 to 5.5V and provide an internal voltage signal that is about 2.3 volts in an embodiment. The cascaded TINs  117 A,  117 B, may break up the drain voltage of the differential pair  116 A,  116 B from the differential load  118 A,  118 B to develop output voltage on the OTA  114 . The TRP pair  118 A,  118 B may form a current mirror differential load. In an embodiment the OTA  114  may effectively be a differential pair with active load that may handle higher voltage given VDD may vary. The resistors  121 A,  121 B may be about 9.5/1.4/35.52/ms=2 and 50.9/1.4/377.7/ms=4, respectively. 
       FIG.  6 A  is a block diagram of a bandgap reference module (BRM)  140  and  FIG.  6 B  is a simplified diagram of the BRM  140  according to various embodiments. As shown in  FIGS.  6 A,  6 B , the BRM  140  may include an OTA module  150 , a bandgap module  160 , and a standby-startup module  164 . The bandgap module  160  may include resistors  161 A,  161 B, and  161 C and diodes  162 A,  162 B,  162 C having different channel widths to generate a voltage differential that is measured by the OTA  150 . The diodes  162 A,  162 B may be about 1.4/1.6/mp=1, 34.2/1.6/mp=6, and 14.4/1.6/mp=1 respectively in an embodiment. The OTA  150  may use the determined differential to generate the reference voltage signal VBG (about 1.16V in an embodiment). 
     In an embodiment the diodes  162 A,  162 B,  162 C may both be formed in a single CMOS wafer and due to similar channel lengths (1.6 um in an embodiment) operational variance due to temperature and wafer processing may not change the effective differential (bandgap) between the diodes  162 A,  162 B,  162 C. Accordingly, the related diode  162 A,  162 B,  162 C bandgap may be stable from wafer to wafer and temperature independent. In an embodiment, the resultant VBG level is thus known based on the known diode characteristics (as known by the diode formation process and materials). 
     The standby-startup module  164  may include an RN FET  153 C that bypasses the diodes  162 B,  162 C based on the state of the START_FLAG. RN FET  153 C may be about 4/1/mt=1 in an embodiment. As noted the bandgap module  160  may also include the resistors  161 A,  161 B, and  161 C as shown in  FIG.  6 B . The resistors  161 B,  161 C may be about 13.4/1.4/199.8/ms=8 and 13.4/1.4/224.8/ms=9, respectively. The resistor  161 A may include two resistors in series and the resistors may be about 13.4/1.4/424.7/ms=17 and 13.4/1.4/24.98/ms=1, respectively. 
     In an embodiment the OTA  150  may include two current sources CS-P  142  including cascaded FETs RP  151 A,  151 B and  151 C,  151 D. The FETs RP  151 A,  151 B,  151 C,  151 D may each be about 4/2/mt=1. In an embodiment, each CS-P  142  may provide a current source of about 1.2 uA. The RP pair  152 A,  152 B and RN pair  153 A,  153 B may form an amplifier. The amplifier may receive the constant current source from the CS-P (formed from RP pair  151 A,  151 B) and the differential signal from the diodes  162 A,  162 B and resistor  161 C. Cascaded FETs IN  153 F and RN  153 E may be coupled to the second current source CS-P  142 . The FETs  152 A,  152 B may each be about 10/2/mt=4, FETs  153 A,  153 B may each be 10/4/mt=2, FET  153 F may be about 7.5/0.5/mt=1, and FET  153 E may be about 10/0.9/mt=1. The OTA  150  also includes FET IN  153 D. The standby-startup module  164  may further include an RN FET  153 G that bypasses the RN FET  153 B based on the state of the START_FLAG. RN FET  153 G may be about 3/1/mt=1 in an embodiment. 
     The bandgap reference module  140  may also include a standby-startup module  164 . The startup module  164  may include cascaded FETs IN  166 A, FET RP  166 B where the gates of the respective FETs may receive the VDD_INT_SU and IREF_SU startup signals and FET IN  153 D which serves as an output buffer whose gate is coupled to the drain of the FET RP  166 B and the output of the second stage amplifier of the op-amp consisting of  153 E/F and  151 C/D. The FETs IN  166 A, RP  166 B, IN  153 D may be about 4/1/mt=1, 4/1/mt=1, and 14.6/0.5/mt=1, respectively. The startup module  164  ensures the VBG signal reaches the appropriate operational level. VDD_INT_SU is based on VDD_INT and IREF_SU is based on IREF. As noted the standby-startup module  164  also includes RN FETs  153 C and  153 G. 
       FIG.  7 A  is a block diagram of a reference voltage and current generator module (RVCGM)  170  and  FIG.  7 B  is a simplified diagram of the RVCGM  170  according to various embodiments. As shown in  FIGS.  7 A,  7 B , the RVCGM  170  may include an OTA module  180 , a current/bias voltage generation module (CBVGM)  192 , and standby-startup module  188 . The OTA  180  may include a current sink CS-N  172  including cascaded TRN  181 A,  181 B. The FETs TRN  181 A,  181 B may be about 4/2/mt=1, 4/2/mt=1, respectively. In an embodiment, the CS-N develops a current sink of about 1.2 uA. The RN pair  182 A,  182 B and TRP pair  183 A,  183 B form an amplifier coupled to the constant current sink of CS-N  172  (formed from TRN pair  181 A,  181 B). The FETs TRP  182 A,  182 B,  183 A,  183 B may each be about 4/2/mt=1, respectively. 
     In an embodiment the OTA  180  may determine the difference of the VBG signal and IVREF signal generated by the LDO  185  and resistor  186  (current across the resistor  186  where the LDO  185  is a current source). The LDO  185  includes cascaded TRP  184 A,  184 B. In an embodiment the FETs TRP  184 A,  184 B may be about 4/2/mt=2, and 4/2/mt=2 respectively (note that number of channels is 2—twice the number of the current source  142 ). Accordingly, the LDO  185  may generate a current source of about 2.4 uA in an embodiment when BIASP 1  and BIASP 2  are steady state. The resistor  186  may be about 494 K-ohms in an embodiment. Given the LDO  142  is generating a current of about 2.4 uA at steady state and the resistance of 494 Kohms, the voltage level of the signal or point IVREF may be about 1.16 Volts at steady state. The VBG signal voltage level may be about 1.16 volts at steady state and is generated by the BRM  140 . The OTA  180  regulates the generation of the IVREF signal using the VBG reference signal and effectively the four gate bias signals BIASN 1 , BIASN 2 , BIASP 1 , and BIASP 2 . 
     In an embodiment, the LDO  185  may provide current IREF to resistor  186  to generate the corresponding voltage signal IVREF. The CBVGM  192  generates the gate bias signals BIASP 1 , BIASP 2 , BIASN 1 , and BIASN 2 . At steady state (when IVREF voltage level is about 1.16 Volts (receiving 2.4 uA from  185 ), BIASN 1  is about the threshold level of the TRN  187 B (about 0.7 V in an embodiment). BIASN 2  is greater than BIASN 1  due to cascaded TRN  187 A and TRN  189  (about 200 mV greater in an embodiment or 0.9 V). BIASP 1  is about one threshold of the TRP  186 A below the supply rail VDD_INT (about 2.3V less 0.7V=1.6V). BIASP 2  is lower than BIASP 1  due to TRP  186 E (about 200 mV less in an embodiment, 1.4 V). It is noted that TRP  186 A and TRP  186 B form a current source  186 C that generates a constant current of 1.2 uA when the gate bias signals BIASP 1  and BIASP 2  are at steady state (1.6 Volts and 1.4 Volts in an embodiment). 
     It is noted that the TRP  186 A has a different Vgs (Voltage Gate to Source) than TRP  186 E due to their different physical configurations (TRP  186 A may be have a width/length of about 4/2 (microns), mt=1 and TRP  186 E may have a width/length of about 2/8 (microns), mt=1, and TRP  186 B may be have a width/length of about 4/2 (microns), mt=1. Similarly, the TRN  189  may have a different Vgs than TRN  187 B due to different physical configurations (TRN  187 B may be have a width/length of about 4/2 (microns) (mt=1), TRN  189  may have a width/length of about 2/8 (microns) (mt=1), and  187 A may be have a width/length of about 4/2 (microns) (mt=1). The CBVGM  192  also includes a current source  142  formed by TRP  186 C and TRP  186 D coupled to TRN  187 C and TRN  187 D where each may be about 4/2/1 in an embodiment. 
     In an embodiment the BBSGM  100  modules rely on the gate bias signals BIASN 1 , BIASN 2 , BIASP 1 , and BIASP 2  and reference signals (VBG) generated by the various modules  110 ,  140 , and  170  to operate at steady state. The remaining modules of the architecture  10  also need steady state gate bias signals BIASN 1 , BIASN 2 , BIASP 1 , and BIASP 2 . Given the interdependence between the BBSGM  100  modules  110 ,  140 ,  170 , a startup or standby wake method  142  ( FIG.  8   ) may be employed in an embodiment to enable the BBSGM  100  to reach steady state. Further, startup of BBSGM  100  (from a cold start or standby) may be controlled by additional startup/standby modules as noted above where the modules may employ the method or algorithm  142 .  FIG.  8    is a simplified diagram of a BBSGM  100  activate (from cold start or standby) algorithm  142  according to various embodiments that may be employed in the BBSGM  100 . During a cold start or standby, capacitors of the BSGA  10  may be discharged and external rail supply VDD may be rising. In the process  142 , VDD_INT_SB (internal voltage standby) may be pulled up as the external voltage VDD rises (activity  142 ). In an embodiment the VRM  110  of BBSGM  100  shown in  FIG.  5 B  may include resistors  121 A,  121 B of standup module  122  that pull up VDD_INT_SB as VDD rises (increase voltage level as current draw is increased in the OTA  114 ). 
     As VDD_INT_SB starts to rise, the RVCGM  170  starts to function and generate the gate bias signals BIASN 1 , BIASN 2 , BIASP 1 , BIASP 2 , which are used by the BRM  140 , the RVCGM  170 , and the VRM  110  (activity  143 ). In an embodiment the BRM  140  may not generate a steady state band-gap signal VBG until the internal voltage signal VDD_INT is greater than thresholds  166 A,  166 B of activate (standby-startup) module  164  (activities  144 ,  145 ). In particular, FETs IN  166 A, and RP  166 B form a valve that pulls up VBG to VDD_INT_SU during startup. VDD_INT_SU may be at ground (GND) at startup. As noted above the FETs IN  166 A, RP  166 B may be about 4/1/mt=1, 4/1/mt=1, and  166 A may have a lower threshold and thus lower voltage drop. At steady state, the voltage level of the signals VDD_INT_SU and IREF_SU are similar so the valves  166 A,  166 B may become closed or inactive. 
     Thereafter, the VBG signal may rise to its nominal level (about 1.16V in an embodiment) (activity  146 ) as the BRM  140  starts to operate (activity  145 ). The RVCGM  170  OTA  180  may operate and then generate the IREF signal (current level monitored) and corresponding IVREF signal (voltage level monitored) to be compared against the VBG signal voltage level (activity  147 ). In an embodiment, activate or startup valves  189 A,  189 B may pull up BIASP 1  and BIASP 2  during startup. In an embodiment the startup valves  189 A,  189 B may each include cascaded FETS TRN and IP where the FETS TRN and IP (intrinsic P-type) may be about 2/1/mt=1, 2/1/mt=1, respectively. The TRN gates of  189 A,  189 B may receive the VBG signal and the IP gates of modules  189 A,  189 B may be coupled to the signal IVREF. At steady state the voltage level of the signals IVREF and VBG are similar so the valves  189 A,  189 B may become closed or inactive. 
     The startup_flag used in the startup modules  190 ,  120 ,  150 ,  180  may be set to end operation of these modules (activity  148 ) when the RVCGM  170  reaches steady state (activity  147 ). When the gate bias signals BIASN 1 , BIASN 2 , BIASP 1 , and BIASP 2  and reference signal VBG are steady state, the VRM  110  may effectively generate a steady state signal VDD_INT from a variable voltage level input signal (VDD external) where the VDD_INT signal may be used by other BSGA  10  modules (activity  149 ). In an embodiment the Schmitt trigger  112  may receive the bias signals BIASP 1 , BIASP 2  and limit the operation of the OTA  114  operation and the LDO  124  until the trigger  112  is tripped. Then the VRM  110  may effectively generate the VDD_INT signal from a variable voltage external VDD signal. When process  142  is complete, the gate bias signals BIASN 1 , BIASN 2 , BIASP 1 , and BIASP 2 , the reference signal VBG, and the VDD_INT may have steady values that may be used by the other BSGA  10  modules. Given this configuration the other modules may be designed based on the availability of constant gate bias signals and voltage supply signals. 
     As noted the BSGA  10  may provide signals VDD_LS and VSS having known, steady voltage levels to a switching module  22 . BSGA  10  may be required to maintain the signals VDD_LS, VSS voltage levels during switching events. In an embodiment, BSGA  10  may employ charge pumps modules  300 ,  400  (positive and negative) to ensure the voltage levels of the signals VDD_LS and VSS remain constant during loading events. The BSGA  10  may employ a differential oscillator module  200  to control operation of the charge pump module  300 ,  400  in an embodiment. 
       FIG.  9 A  is simplified diagram of differential oscillator module (DOM)  200  according to various embodiments. As shown in  FIG.  9 A  the DOM  200  may include a plurality of ring oscillators  203 A and an oscillator output buffer  203 B, resistors  201 A,  201 B, and capacitors  202 A to  202 F. In an embodiment DOM  200  may receive gate bias signals BIASP 1 , BIASP 2 , BIASN 1 , BIASN 2 , and internal voltage signal VDD_INT (generated by BBSGM  100 ) and generates differential oscillator or clock signals OSC 1 , OSC 2 . In an embodiment DOM  200  may be a three stage, current starved, AC coupled oscillator. In an embodiment the resistors  201 A,  201 B may be about 96.2/1.4/356.6/ms=2 and 144.3/1.4/267.4/ms=1, respectively. The capacitors  202 A to  202 F may be about 18/8.9/941.6fF/mp=1, 24.1/8.9/1.259pF/mp=1, 0.800/6.9/37fF/mp=1, 0.500/6.25/22.73fF/mp=1, 17/9.6/958.7fF/mp=1, 22.7/9.6/1.278pF/mp=1, respectively. It is noted that during standby or startup, VDD_INT, BIASN 1 , BIASN 2 , BIASP 1 , and BIASP 2  are at GND so DOM  200  may not function during standby or startup. 
     In an embodiment, each ring oscillator stage  203 A contains single ended inverters, side-by-side coupled in anti-phase with other stage  203 As. In order to control oscillation frequency, a current starved scheme may be employed where the inverters are not directly coupled to supply rails but are coupled to the supply rails via current sources or sinks ( 205 A,  206 A in  FIG.  9 B ).  FIG.  9 B  is simplified diagram of a differential oscillator cell  203 A according to various embodiments. The cell  203 A includes an inverter  208 A formed by a TRP  204 E and TRN  204 F pair that are coupled by an anti-phase inverter  209  to another inverter  208 B also formed by a TRP  204 E and TRN  204 F pair. The anti-phase inverter  209  includes an inverter  209 A formed by a TRP  204 E and TRN  204 F pair and inverter  209 B also formed by A TRP  204 E and TRN  204 F pair. 
     The inverters  208 A,  208 B are each coupled to a current source CS-P  205 A (formed by TRP pair  204 B) and current sink CS-N  206 A (formed by TRN pair  204 A). The combination of the CS-P  205 A and CS-N  206 A on each side of the inverters  208 A,  208 B starves the inverters  208 A,  208 B of current. The anti-phase inverter  209  (formed from inverters  209 A,  209 B) is also coupled to a current source CS-P  205 B (formed by TRP pair  204 D) and current sink CS-N  206 B (formed by TRN pair  204 C). In an embodiment the CS-P  205 A and CS-N  206 A current draw is four times greater than the current draw of CS-P  205 B and the CS-N  206 B current, respectively. FETS TRP  204 B and TRN  204 A may be about 10/0.6/mt=1, in an embodiment. The current source  205 A may generate about 1.2 uA and the current drain  206 A may draw about 1.2 uA (similar to  141 A,  141 B). FETS TRP  204 E and TRN  204 F may be about 1.6/0.35/mt=1, in an embodiment. FETS TRP  204 D and TRN  204 C may be about 2.5/0.6/mt=1, in an embodiment. The current source  205 B may generate about 0.3 uA and the current drain  206 B may draw about 0.3 uA. 
     In an embodiment, the threshold of TRP  204 B is about 0.7V, which is about the difference between the rail, VDD_INT (2.3 V) and BIASP 1  (1.6V). In an embodiment a differential ring cell  203 A may not use the gate signals BIASN 2  and BIASP 2 . In operation, an AC component of a signal is passed to the inverter gates  208 A,  208 B via inputs INP, INN. When the gate bias shifts, the P and N type devices (TRN and TRP) may switch operation to create oscillation. In an embodiment, capacitors  211 A may be about 8.8/4.4/232.3fF/mp=1 so only an AC component of the signals INP, INN is passed to the inverters  208 A,  208 B gates. A DC bias signal is provided by BIASP 1  and BIASN 1  where any AC content on the BIASP 1 , BIASN 1  signals is removed by active resistors  207  (described below). 
     Further when one of CS-P  205 A is operating the TRP  204 B pair is active and the respective TRN  204 A pair and CS-N  206 A are not active, current is sourced to the respective output (OUTN or OUTP). Similarly, when one of CS-N  206 A is operating, the TRN  204 A pair is active and the respective TRP  204 B pair and the CS-P  205 A are not active, current is sinked to the respective output (OUTN or OUTP). Accordingly, a differential ring cell  203 A may create a trapezoidal waveform (linear incline and decline with flat tops). As noted, the anti-phase or anti-parallel inverters  209 A,  209 B are minor inverters compared to the inverter formed by  208 A,  208 B due to the ¼ current source and sink  205 B,  205 A. In an embodiment, the inverters  208 A may be coupled to the anti-parallel inverter complementary input. In an embodiment the oscillation frequency of the DOM  200  is about 8.2 MHz versus 3.6 MHz in other embodiments. The length of the FETs TRP  204 B,  204 D and TRN  204 A,  204 C may be 0.6 um in an embodiment to increase the DOM  200  frequency versus 1.0 um in another embodiment. The reduction of FET lengths from 1.0 um to 0.6 um increases the core bias current by approximately 66% in an embodiment. 
       FIG.  9 C  is simplified diagram of a differential oscillator buffer  203 B according to various embodiments. As show in  FIG.  9 C , the buffer  203 B includes an inverter formed from  209 C,  209 D, current source CS-P  205 C and current sink CS-N  206 C, active resistors  207 , and capacitors  211 B. Similar to differential ring cells  203 A, differential ring buffer  203 B is AC coupled where a received signal (on INN and INP) is split (between AC and DC). The ABR  207  create a DC bias to drive TRP  204 G and TRN  204 H devices from the BIASP 1  and BIASN 1  gate bias signals while not passing any AC content on these signals. The inverters formed by  209 C,  209 D perform current steering between the two current sources and the outputs. When INN is above INP, the CS-N  206 C sinks current from OUTP making it fall, and CS-P  205 C sources current to OUTN making it rise. When IPP is above INN, the CS-N  206 C sinks current from OUTN making it fall, and CS-P  205 C sources current to OUTP making it rise. 
     In an embodiment the current sinks CS-N  206 C and source CS-P  205 C pass three times the current of the CS-N  206 A and CS-P  205 A to prevent shoot through currents. The capacitors  202 A to  202 F shown in  FIG.  9 A  prevent possible feedback to the BB_SGM  100 . FETS TRP  204 J and TRN  204 I may be about 20/0.6/mt=2, in an embodiment. The current source  205 C may generate about 3.6 uA and the current drain  206 C may draw about 3.6 uA (three times the level of  205 A,  206 A). FETS TRP  204 G and TRN  204 H may be about 4/0.35/mt=1 and 2/0.35/mt=1 in an embodiment. In an embodiment, capacitors  211 B may be about 10/4.3/257.7fF/mp=1 so only an AC component of the signals INP, INN is passed to the inverters  209 C,  209 D gates. The length of the FETs TRP  204 J and TRN  204 I may be 0.6 um in an embodiment to increase the DOM  200  frequency versus 0.8 um in another embodiment. The reduction of FET lengths from 0.8 um to 0.6 um increases the core bias current by approximately 33% in an embodiment. 
       FIG.  10    is simplified diagram of a symmetrical active bias resistor (ABR)  207  according to various embodiments. The ABR  207  may be used in place of a large resistor to remove an AC component from the input signal and couple DC components of signals. In an embodiment, the ABR  207  is symmetrical and can operate in either direction. As shown in  FIG.  10   , an ABR  207  may include TIN  213 A,  213 B, TRN  214 A,  214 B,  215 A,  215 B,  216 A,  216 B, and TIN  217 A,  217 B. The TIN&#39;s  217 A,  217 B source and drain are coupled to effectively form a switchable capacitor. In an embodiment the TIN  213 A,  213 B may be about 1.4/0.5/mt=1, TRN  214 A,  214 B,  215 A,  215 B,  216 A,  216 B may be about 1.4/2/mt=1, and TIN  217 A,  217 B may also be about 1.4/2/mt=1. 
     In operation NODEA and NODEB may effectively switch operation as function of whether the voltage level of NODEB is less than or greater than the voltage level of NODEA. In an embodiment an ABR  207  may be used to bias a clock signal at a given DC bias. In this embodiment NODEA or NODEB is connected to a DC bias and the other of NODEA or NODEB is connected to a clock side. The clock side signal includes a capacitive coupled AC signal. For example, if an AC signal is coupled to NODEA and a DC bias is coupled to NODEB, then NODEA will have the same DC basis as NODEB. An ABR  207  may not affect the AC component of NODEA in the example, but only pass a DC component from a NODEB signal to NODEA. It is noted that the ABR  207  may very quickly track a DC bias between NODEA and NODEB given there is no RC time constant delay that may commonly exists when a resistor is employed to create a DC bias. 
     In operation when an AC signal on NODEA is rising and its potential is greater than NODEB the left side (A) of the ABR  207  is active or operates. However, when an AC signal on NODEA is falling and its potential is less than NODEB the right side (B) of the ABR  207  is active or operates. As noted  217 A,  217 B are capacitors. As NODEA rises displaced currents are passed to TRN  214 A and the gates of TRN  215 A, TIN  213 A are also pulled up by the displacement current through the capacitor  217 A. TIN  213 A is optional in an embodiment and provides additional impedance if needed. In this example an AC path is present from NODEA to NODEB via  214 A and  217 A. A DC path is formed from  213 A and  215 A (from NODEA to NODEB). The DC path formed by TIN  213 A and TRN  215 A enables the ABR  207  to track DC bias changes quickly. The capacitance of  217 A,  217 B adjusts the current tracking rate. 
     In an embodiment the ABR  207  is only affected by the respective potential levels of NODEA and NODEB. When the NODEA potential falls below the NODEB potential, the diode  216 A may operate to discharge the capacitor  217 A (the diode  216 A becomes forward biased). Accordingly it may be desirable to make the capacitance of  217 A,  217 B small to create small currents (losses) similar to a large resistor. 
       FIG.  11 A  is simplified diagram of a P-bias voltage tracker (P-VT)  349 A according to various embodiments.  FIG.  11 B  is simplified diagram of an N-bias voltage tracker (N-VT)  349 B according to various embodiments. The trackers  349 A,  349 B receive clock inputs CLK_N and CLK_P and act as a switched capacitor circuit that generates a DC offset from V+ (P-VT) or V− (N-VT) equivalent to the threshold voltage of the respective diode connected FETs  348 A,  351 A. As shown in  FIG.  11 A , P-VT  349 A includes a TRP diode  348 A, RP  348 B, RN  348 C, and capacitors  347 A,  347 B. The P-VT receives clock signals and passes a DC signal between V+ and V−. The capacitors  347 A,  347 B may be about 0.500/1.4/5.362fF/mp=1, 3.9/9/211.2fF/mp=1. TRP  348 A,  348 B may be about 5/0.5/mt=1, 1.4/0.5/mt=1, respectively. RN  348 C may be about 1.4/0.8/mt=1. RN  351 A,  351 C may be about 5/0.8/mt=1, 1.4/0.5/mt=1, respectively. TRP  351 B may be about 1.4/0.5/mt=1. 
     As shown in  FIG.  11 B , N-VT  349 B includes an RN diode connected FET  351 A, TRP  351 B, RN  351 C, and capacitors  347 A,  347 B. The N-VT receives clock signals and passes DC signal between V− and V+. The P-VT  349 A and N-VT  349 B operate as a diode. The remainder of the elements form switched capacitor elements to bias the respective diodes. In N-VT  349 B the DC bias is equal to V− plus the threshold of diode  351 A and in P-VT  349 A, the DC bias is equal to V+ minus the threshold of diode  348 A. 
       FIG.  12    is simplified diagram of a positive voltage control signal generation module (VCSGM)  310  according to various embodiments. As shown in  FIG.  12   , the VCSGM  310  includes an OTA  314 , a voltage divider  312 , an LDO  317 , and a capacitor  318 . The OTA includes a CS-N (current sink) formed by TRN  316 B pair and a differential amplifier formed by the TRP  315 A pair and the TRN  316 A pair. The OTA  314  may determine the difference between a reference signal VBG (the output of the BBSGM  100 ) and voltage divided VDD_LS. In an embodiment VDD_LS is about 3.4 V and VBG is about 1.16 V. The voltage divider  312  includes several resistors  311 A,  311 B where the resistance is selected to make the nominal value of VDD_LS about equal to VBG (ratio 1.16/3.4 in an embodiment). 
     In an embodiment the resistor  311 A may have a total resistance of about 1074.96Kohms and include at least three resistors in series about 13.4/1.4/49.96/ms=2, 13.4/1.4/499.6/ms=20, and 47.2/1.4/525.4/ms=6. The resistor  311 B may have a total resistance of about 562.37Kohms and include at least three resistors in series about 47.2/1.4/175.1/ms=2, 13.4/1.4/374.7/ms=15, and 3.3/1.4/6.278/ms=1. Accordingly the resistor divider may reduce the VDD_LS signal by about 65.65% (3.4 V reduced 65.65% equals about 1.16 V in an embodiment). The FET TRP  317  may be about 12/0.4/1. The capacitor  318  may be about 9.65/5.6/321.9F/mp=1. The FET TRP  315 A, TRN  316 A, and TRN  316 B may be about 4/2/2, 4/2/2, and 8/2/1, respectively. The current sink  316 C may draw about 2.4 uA in an embodiment. 
     The LDO (low drop out regulator) formed by the TRP  317  limits or sets a ceiling for the POS_CP_VDD control signal. In an embodiment the LDO TRP  317  drain can only be high as the source or supply or POS_CP_VDD voltage level can only be as great as the VDD_INT voltage level (or about 2.3 volts in an embodiment.) As noted below the PVCPGM  340  generates a signal VPOS having a voltage level twice the voltage level of POS_CP_VDD. Accordingly during a switching event the PVCPGM  340  VPOS signal voltage level may be twice the VDD_INT voltage level (or about 4.6 volts in an embodiment). Such configuration may enable the BBSGM  100  to recover more quickly after a switching event—lowering the potential insertion loss of the BBSGM  100 . The capacitor  318  may stabilize the POS_CP_VDD signal in embodiment. 
       FIG.  13    is simplified diagram of a positive voltage charge pump generation module (PVCPGM)  340  according to various embodiments. As shown in  FIG.  13   , the PVCPGM  340  includes P-type voltage trackers (P-VT)  349 A, N-type voltage trackers (N-VT)  349 B, ABR  207 , capacitors  341 A,  341 B,  341 C upper inverter formed from TRP  353 A pair and TRN  353 B pair, and lower inverter formed from TRP  353 C pair and TRN  353 D pair. The capacitors  341 A,  341 B,  341 C may be about 4.5/16.45/441fF/mp=1, 3.9/9.4/220.5fF/mp=1, 3.9/9.1/213.5fF/mp=1, respectively in an embodiment. The TRP  353 A,  353 C may be about 12/0.4/mt=1. The TRN  353 B,  353 D may be about 6/0.4/mt=1. The fly capacitors  302 A,  302 B may be about 30/30/5.226pF/mp=1, in an embodiment. 
     The PVCPGM  340  receives the clock signals OSC 1 , OSC 2 , and voltage signal POS_CP_VDD and alternatively charges and discharges capacitors  302 B,  302 A, respectively to generate signal VPOS. In an embodiment the bottom plate of each capacitor  302 A,  302 B is at about 1.7 volts (POS_CP_VDD) when discharging, and 0V when charging. During a discharge phase the voltage at the capacitor  302 A,  302 B top plate may be about twice the bottom plate voltage level (as supplied by signal POS_CP_VDD (about 1.7 volts in an embodiment)) or about 3.4 volts in an embodiment. During the charging phase these top plates will be at about 1.7 volts (POS_CP_VDD). It is noted that the capacitors  302 A,  302 B may be MOS capacitors where the polarity of the connections is relevant. It is also noted that the PVCPGM may be fully symmetric and the clock signal OSC 1 , OSC 2  may also be fully symmetric. As noted in  FIG.  13    the P-type voltage tracker  349 A DC basis signal B 1 A is shared by the differential pair  353 A through ABR  207 . Similarly, the N-type voltage tracker  349 B DC basis signal B 1 B is shared by the differential pair  353 B through ABR  207 . 
     Similarly on bottom inverter formed from the FET pairs  353 C,  353 D, the P-type voltage tracker  349 A DC basis signal B 2 A is shared by the differential pair  353 C through ABR  207 . Similarly, the N-type voltage tracker  349 B DC basis signal B 2 B is shared by the differential pair  353 D through ABR  207 . As noted nominally the voltage level of VPOS is equal to twice the voltage level of POS_CP_VDD. In operation when an input signal on OSC 1  is high and OSC 2  is low, TRP  353 A (right side), TRN  353 B (left side), TRP  353 C (left side), TRN  353 D (right side) are turned on and TRP  353 A (left side), TRN  353 B (right side), TRP  353 C (right side), TRN  353 D (left side), are turned off. Similarly, when an input signal on OSC 1  is low and OSC 2  is high, the opposite is true. The respective capacitors  302 A,  302 B get charged to the level of POS_CP_VDD. Accordingly VPOS is equal to 2×POS_CP_VDD. In an embodiment the PVCPGM  340  is symmetrical so clock (DOM  200 ) sees a fully symmetric and differential load. 
       FIGS.  14 A- 14 D  are simplified diagrams of a negative voltage control signal generation module (NCSGM)  410  according to various embodiments and the various components.  FIG.  15    is simplified diagram of a negative voltage charge pump generation module (NVCPGM)  440  according to various embodiments. The NCSGM  410  and NVCPGM  440  is described in, commonly assigned application PER-027-PCT, entitled, “LOW-NOISE HIGH EFFICIENCY BIAS GENERATION CIRCUITS AND METHOD”, filed Jul. 17, 2009 and assigned to application number PCT/US2009/004149. As shown in  FIG.  14 A , the VCSGM  310  includes a buffer  414 , a voltage divider  412 , an OTA  420 , a capacitor bank  416 , capacitors  418 A,  418 B,  418 C, a TRP (P-Type FETs) LDO  415 G, N-type FETs  416 A and  416 B, and a resistors  411 A-E. The buffer  414  includes a CS-P pair (current source) formed by pair of TRP  415 A,  415 C pair and TRP  415 B,  415 D pair and TRP  415 E and TRP  415 F matched pair. 
     In an embodiment the resistor  411 A may have a total resistance of about 587.53Kohms and include at least three resistors in series about 6.7/1.4/12.57/ms=1, 13.4/1.4/49.96/ms=2, and 94.4/1.4/525/ms=3. The resistor  411 B may have a total resistance of about 1700.87Kohms and include at least three resistors in series about 94.4/1.4/1575/ms=6, 13.5/1.4/100.7/ms=4, and 13.5/1.4/25.17/ms=1. The FETs TRP  415 A,  415 B,  415 C,  415 D,  415 E,  415 F may be about 8/4/2 in an embodiment. The FETs TRP  415 G,  415 H may be about 4/0.4/1 and 4/1/1, respectively. The FET TRN  416 A,  416 B may be about 4/1/1 in an embodiment. The FET TRN  417 A,  417 B, and  417 C may be about 20/19.2/1, 20/10/1, and 10/10/1, respectively. The capacitors  418 A,  418 B, and  418 C may be about 7/7/292fF/mp=1, 3/5.3/97.39fF/1, and 4/9.6/230.7fF/1, respectively. The resistors  411 C,  411 D, and  411 E may be about 62.6/1.4/232.2/ms=2, 62.6/1.4/232.2/ms=2, and 28.3/1.4/630.8/ms=12, respectively. 
     The capacitor bank  416  may include four TIN type capacitors  418 A,  418 B,  418 C, and  418 D. The capacitors  418 A,  418 B,  418 C, and  418 D may be about 20/19.2/mt=1, 20/10/mt=1, 10/10/mt=1, and 5/10/mt=1, respectively. The increased capacitor bank  416  may reduce the settling time of the signal VSS after a switching event. The switch  416 B may also prevent the capacitor bank  416  from discharging or limits its discharge during a switching event. The switch  416 B may also help reduce the settling time of the signal VSS after a switching event. 
       FIG.  14 B  is a simplified diagram of an OTA  420  according to various embodiments and the various components that may be employed in the NCSGM  410  shown in  FIG.  14 A . As shown in  FIG.  14 B , the OTA  420  may include an OTA Tune  460 , two OTA  430 , a clamp  422 A, a clamp  422 B, capacitors  427 A,  427 B, and resistors  428 A and  428 B. The clamp  422 A includes a CS-P (current source)  142  including a FET TRP pair  423 A,  423 B, a buffer formed by TRP  423 C, and diode connected FETs TRP  423 D and  423 E. The clamp  422 B includes a CS-N (current sink)  172  including a FET TRN pair  425 A,  425 B, a buffer formed by TRP  423 G, and diode connected FETs TRP  423 F and  423 H. 
     The FETs TRP  423 A,  423 B may be about 4/2/1 so the CS-P  142  may provide about 1.2 uA of current in an embodiment. The FETs TRP  423 C,  423 D,  423 H,  423 G may be about 4/1.8/1 in an embodiment. The FETs TRP  423 E,  423 F may be about 4/0.4/1 in an embodiment. The capacitors  427 A,  427 B may be about 10.5/4.9/307.1fF/mp=1. The resistors  428 A and  428 B may be about 26.9/1.4/99.96/ms=2 and 26.9/1.4/199.9/ms=4, respectively. 
       FIG.  14 C  is a simplified diagram of an OTA Tune  460  according to various embodiments and the various components that may be employed in the OTA  420  shown in  FIG.  14 B . As shown in  FIG.  14 C , the OTA Tune  460  may include a first differential OTA  462 A, a second differential OTA  462 B, a TRP pair  465 C,  465 D, and a TRP  465 G. The first differential OTA  462 A may include a CS-N (current sink)  172  including a FET TRN pair  463 A,  463 B (and receiving the gate bias signals BIASN 1 , BIASN 2 ), and amplifier formed by TRP pair  465 A,  465 B, TIN pair  464 A,  464 B, and a TIN pair  464 C,  464 D. The second differential OTA  462 B may include a CS-N (current sink)  172  including a FET TRN pair  463 C,  463 D (and receiving the gate bias signals BIASN 1 , BIASN 2 ), and an amplifier formed by TRP pair  465 E,  465 F, TIN pair  464 E,  464 G, and a TIN pair  464 F,  464 H. 
     Both differential OTAs  462 A,  462 B compare the signals INP_BIAS and INN_BIAS and INP and INN in opposite polarities. The first differential OTA  462 A generates the signal OUTP having a floor controlled by CM_TUNE and the TRP pair  465 C,  465 D. The second differential OTA  462 B generates the signal OUTN having a floor controlled by CM_TUNE and the TRP  465 C and  465 G. The FETs TRN  463 A,  463 B,  463 C,  463 D may be about 8/2/1 so each two CS-N  172  may draw about 2.4 uA of current in an embodiment. The FETs TIN  464 C,  464 D,  464 F,  464 H may be about 4/2/2 in an embodiment. The FETs TIN  464 A,  464 B,  464 E,  464 G may be about 4/1/1 in an embodiment. The FETs TRP  465 A,  465 E may be about 4/1/2 in an embodiment. The FETs TRP  465 B,  465 F may be about 4/1/1 in an embodiment. The FETs TRP  465 D,  465 G may be about 4/1/3 in an embodiment. The FET TRP  465 C may be about 4/0.5/1 in an embodiment. 
       FIG.  14 D  is a simplified diagram of an OTA  430  according to various embodiments and the various components that may be employed in the OTA  420  shown in  FIG.  14 B . As shown in  FIG.  14 D , the OTA  430  may be a differential OTA and include a CS-N (current sink)  172  including a FET TRN pair  434 C,  434 D (and receiving the gate bias signals BIASN 1 , BIASN 2 ), and an amplifier formed by TRP pair  432 A,  432 B, and a TRN pair  434 A,  434 B. The differential OTA  430  may compare the signals INP and INN and generate the signal OUT based on said differential. The FETs TRN  434 C,  434 D may be about 4/2/1 so the CS-N  172  may draw about 1.2 uA of current in an embodiment. The FETs TRN  434 A,  434 B may be about 4/2/1 in an embodiment. The FETs TRP  432 A,  432 B may be about 4/2/1 in an embodiment. 
       FIG.  15    is simplified diagram of a negative voltage charge pump generation module (NVCPGM)  440  according to various embodiments. As shown in  FIG.  15   , the NVCPGM  440  includes P-type voltage trackers (P-VT)  349 A, N-type voltage trackers (N-VT)  349 B, ABR  207 , capacitors  441 A,  441 B,  441 C,  441 D,  441 E,  441 F, upper inverter formed from TRP  453 A pair and TRN  453 B pair, lower inverter formed from TRP  453 C pair and TRN  453 D pair, TRP  453 E,  453 F,  453 G,  453 I, IP  453 H,  453 J. External fly capacitors  402 A,  402 B, and  403 C are coupled to the inverters. In an embodiment the capacitors  441 A,  441 B,  441 C,  441 D,  441 E,  441 F may be about 10/12/706.6fF/mp=1, 5.9/10.2/357.9fF/mp=1, 6.9/6/247.5F/mp=1, 6.9/6/247.5fF/mp=1, 14.8/12/2.084pF/mp=2, and 9.65/12/1.364pF/mp=2, respectively in an embodiment. The TRP  453 A,  453 C may be about 20/0.35/mt=1. The TRN  453 B,  453 D may be about 10/0.35/mt=1. The fly capacitors  402 A,  402 B,  402 C may be about 30/30/5.226pF/mp=1, in an embodiment. The TRP  453 E,  453 F,  453 G,  453 I may be about 1.4/0.8/mt=1. The IP  453 H,  453 J may be about 1.4/0.8/mt=1 in an embodiment. 
     The NVCPGM  440  receives the clock signals OSC 1 , OSC 2 , and voltage signal NEG_CP_VDD and alternatively charges and discharges capacitors  402 A and  402 B,  402 C pair, respectively to generate signal VNEG. In operation, when an input signal on OSC 1  is high and OSC 2  is low, TRN  453 B (left side),  453 D (right side), TRP  453 A (right side),  453 C (left side), are turned on and TRN  453 B (right side),  453 D (left side), TRP  453 A (left side),  453 C (right side) are turned off. Similarly, when an input signal on OSC 1  is low and OSC 2  is high, everything is reversed. The capacitors  402 A,  402 B and  402 C get charged to the level of NEG_CP_VDD. Accordingly VNEG is equal to −(2×NEG_CP_VDD) or about −3.4 Volts in an embodiment. In an embodiment the NVCPGM  440  is symmetrical so clock (DOM  200 ) sees a fully symmetric and differential load. 
     The length of the FET TRP  453 A,  453 C and TRN  453 B,  453 D may be about 0.35 um versus 0.4 um in another embodiment to reduce the drop across these devices. In an embodiment the capacitor  402 A may include 10 coupled 30/30/5.226pF/mp=1 capacitors, the capacitor  402 B may include 8 coupled 30/30/5.226pF/mp=1 capacitors, and the capacitor  402 C may include 8 coupled 30/30/5.226pF/mp=1. In another embodiment the embodiment the capacitor  402 A may include 4 coupled 30/30/5.226p/mp=1 capacitors, the capacitor  402 B may include 4 coupled 30/30/5.226pF/mp=1 capacitors, and the capacitor  402 C may include 4 coupled 30/30/5.226p/mp=1. Such configurations may reduce the VSS settling time after a switching event. 
     
       
         
           
               
             
               
                   
               
               
                 Reference Table for Specification: 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 BSGA 
                 Bias Signal Generation Architecture 10 
               
               
                 BBSGM 
                 Base Bias Signal Generation Module 100 
               
               
                 DOM 
                 Differential Oscillator Module 200 
               
               
                 PVCPM 
                 Positive Voltage Charge Pump Module 300 
               
               
                 NVCPM 
                 Negative Voltage Charge Pump Module 400 
               
               
                 PVCM 
                 Positive Voltage Clamping Module 15 
               
               
                 NVCM 
                 Negative Voltage Clamping Module 17 
               
               
                 PSM 
                 Power Supply Module 18 
               
               
                 VRM 
                 Voltage Regulator Module 110 
               
               
                 BRM 
                 Bandgap Reference Module 140 
               
               
                 RVCGM 
                 Reference Voltage and Current Generator Module 170 
               
               
                 SSM 
                 Startup and Standby Module 190 
               
               
                 VDD 
                 External power supply signal 
               
               
                 VDD_LS 
                 Positive Voltage Supply 
               
               
                 VNEG 
                 Negative Voltage Supply 
               
               
                 GND 
                 Ground 
               
               
                 BIASP1 
                 Bias Signal 1 for P-type devices 
               
               
                 BIASP2 
                 Bias Signal 2 for P-type devices 
               
               
                 BIASN1 
                 Bias Signal 1 for N-type devices 
               
               
                 BIASN2 
                 Bias Signal 2 for N-type devices 
               
               
                 VBG 
                 Bandgap voltage reference signal 
               
               
                 HKP 
                 Harmonic Knee Point 
               
               
                 FET 
                 field-effect transistor 
               
               
                 CS_P 
                 current source P-type 
               
               
                 CS_N 
                 current sink N-type 
               
               
                 OPAMP 
                 operational amplifiers 
               
               
                 OTA 
                 operational trans-conductance amplifiers 
               
               
                 POS_CP_VDD 
                 positive charge pump control signal 
               
               
                 NEG_CP_VDD 
                 negative charge pump control signal 
               
               
                 LDO 
                 low drop out 
               
               
                 TIN 
                 thicker film intrinsic N-type FET 
               
               
                 IN 
                 intrinsic N-type FET 
               
               
                 TRP 
                 thicker film regular type P-type FET 
               
               
                 TRN 
                 thicker film regular type N-type FET 
               
               
                 RP 
                 regular type P-type FET 
               
               
                 RN 
                 regular type N-type FET 
               
               
                 IREF 
                 reference current 
               
               
                 IVREF 
                 reference voltage based on reference current 
               
               
                 CBVGM 
                 current/bias voltage generation module 192 
               
               
                 ABR 
                 active bias resistor 207 
               
               
                 VCSGM 
                 positive voltage control signal generation module 310 
               
               
                 PVCPGM 
                 positive voltage charge pump generation module 340 
               
               
                 NCSGM 
                 negative control signal generation module 410 
               
               
                 NVCPGM 
                 negative voltage charge pump generation module 440 
               
               
                 P_VT 
                 P-type voltage tracker 349A 
               
               
                 N_VT 
                 N-type voltage tracker 349B 
               
               
                   
               
            
           
         
       
     
     The apparatus and systems of various embodiments may be useful in applications other than a sales architecture configuration. They are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein. It is noted that the bias signal generation architecture (“BSGA”)  10  may be formed in whole or part on silicon on insulator (SOI) wafer(s) including silicon on sapphire (SOS) according to various embodiments. Any or all of the base bias signal generator module (“BBSGM”)  100 , the differential oscillator module (“DOM”)  200 , the positive voltage charge pump module (“PVCPM”)  300 , the negative voltage charge pump module (“NVCPM”)  400 , the positive voltage clamping module (“PVCM”)  15 , the negative voltage clamping module (“NVCM”)  17 , and the switching module  22  may be formed in whole or part on silicon on insulator (SOI) wafer(s) including silicon on sapphire (SOS) according to various embodiments. 
     Applications that may include the novel apparatus and systems of various embodiments include electronic circuitry used in high-speed computers, communication and signal processing circuitry, modems, single or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules, including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.) and others. Some embodiments may include a number of methods. 
     It may be possible to execute the activities described herein in an order other than the order described. Various activities described with respect to the methods identified herein can be executed in repetitive, serial, or parallel fashion. 
     A software program may be launched from a computer-readable medium in a computer-based system to execute functions defined in the software program. Various programming languages may be employed to create software programs designed to implement and perform the methods disclosed herein. The programs may be structured in an object-orientated format using an object-oriented language such as Java or C++. Alternatively, the programs may be structured in a procedure-orientated format using a procedural language, such as assembly or C. The software components may communicate using a number of mechanisms well known to those skilled in the art, such as application program interfaces or inter-process communication techniques, including remote procedure calls. The teachings of various embodiments are not limited to any particular programming language or environment. 
     The accompanying drawings that form a part hereof show, by way of illustration and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived there-from, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. 
     Such embodiments of the inventive subject matter may be referred to herein individually or collectively by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept, if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. 
     The Abstract of the Disclosure is provided to comply with 37 C.F.R. § 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted to require more features than are expressly recited in each claim. Rather, inventive subject matter may be found in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.