Patent Publication Number: US-11663963-B1

Title: Pixel circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 111106396, filed on Feb. 22, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND 
     Technical Field 
     The disclosure relates to a pixel circuit; more particularly, the disclosure relates to a self-illuminating pixel circuit. 
     Description of Related Art 
     In recent years, due to the advantages of low power consumption, the reduced thickness of the display panel, bright colors, evident contrast, and the performance against motion blur, self-illuminating display technologies have become the mainstream choice of technology in display devices. 
     With the progress of the semiconductor manufacturing process, different light emitting elements are applied to the screen display, and the display panel is correspondingly equipped with different driving circuits. As to a light emitting element with both forward and reverse driving characteristics, a correspondingly designed driving circuit is required to constitute a self-illuminating pixel circuit. 
     SUMMARY 
     The disclosure provides a pixel circuit to which a light emitting element with forward and reverse driving characteristics is applied, so as to provide a novel driving circuit. 
     In an embodiment of the disclosure, a pixel circuit including a light emitting element, a first local light emitting switch, a second local light emitting switch, a common light emitting switch, and a driving block is provided. The light emitting element has one terminal coupled to a common terminal and has a first light emitting part and a second light emitting part, where a direction of a first driving current driving the first light emitting part is opposite to a direction of a second driving current driving the second light emitting part. The first local light emitting switch has a first terminal coupled to a first power terminal, a control terminal receiving a first frame light emitting signal, and a second terminal. The second local light emitting switch has a first terminal coupled to a second power terminal, a control terminal receiving a second frame light emitting signal, and a second terminal. A common light emitting switch has a first terminal, a control terminal receiving a common light emitting signal, and a second terminal coupled to the other terminal of the light emitting element. The driving block receives a data signal, a first frame gate signal, and a second frame gate signal and is coupled to the second terminal of the first local light emitting switch, the second terminal of the second local light emitting switch, and the first terminal of the common light emitting switch. The driving block generates one of a first current path and a second current path based on the first frame gate signal and the second frame gate signal, where the first current path is generated between the second terminal of the first local light emitting switch and the first terminal of the common light emitting switch, the first driving current is transmitted through the first current path; the second current path is generated between the second terminal of the second local light emitting switch and the first terminal of the common light emitting switch, and the second driving current is transmitted through the second current path. The data signal sets a current amplitude of the first driving current and the second driving current. 
     In view of the above, the pixel circuit provided in one or more embodiments of the disclosure may, by means of the well-designed driving block, provide the first driving current and the second driving current that flow in different direction and are required by the light emitting element with the bi-directional driving capability, so that the pixel circuit is applicable to the novel light emitting element and may operate smoothly. 
     To make the above more comprehensible, several embodiments accompanied with drawings are described in detail as follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles provided in the disclosure. 
         FIG.  1    is a schematic view illustrating a system of a pixel circuit according to an embodiment of the disclosure. 
         FIG.  2    is a schematic circuitry view illustrating a pixel circuit according to an embodiment of the disclosure. 
         FIG.  3    is a schematic view illustrating an operating timing of a pixel circuit according to an embodiment of the disclosure. 
         FIG.  4 A  is a schematic view illustrating an operation of a pixel circuit in a first reset period and a second reset period according to an embodiment of the disclosure. 
         FIG.  4 B  is a schematic view illustrating an operation of a pixel circuit in a first set period and a second set period according to an embodiment of the disclosure. 
         FIG.  4 C  is a schematic view illustrating an operation of a pixel circuit in a first light emitting period according to an embodiment of the disclosure. 
         FIG.  4 D  is a schematic view illustrating an operation of a pixel circuit in a second set period according to an embodiment of the disclosure. 
         FIG.  4 E  is a schematic view illustrating an operation of a pixel circuit in a second light emitting period according to an embodiment of the disclosure. 
         FIG.  5    is a schematic view illustrating a system of a pixel circuit according to another embodiment of the disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Unless otherwise defined, all terminologies (including technical and scientific terminologies) used herein have the same meanings commonly understood by those having ordinary skill in the art. It is understandable that these terminologies, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant technology and the background or context of this disclosure, rather than being interpreted in an idealized or overly formal way, unless specifically defined here. 
     It should be understood that terminologies such as “first”, “second”, “third”, etc. may serve to describe various elements, components, regions, layers, and/or parts, but these elements, components, regions, layers, and/or parts should not be limited by these terminologies. The terminologies are only intended to distinguish one element, component, region, layer, and/or part from another element, component, region, layer, and/or part in the specification. Accordingly, a first “element”, “component”, “region”, “layer”, and/or “part” may be referred to as a second “element”, “component”, “region”, “layer”, and/or “part” without departing from the scope of protection provided herein. 
     The terminologies used herein merely serve to describe particular embodiments and should not be construed as limitations. As provided herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms including “at least one” unless the content clearly indicates otherwise, and “or” means “and/or”. As provided herein, the terminologies “and/or” includes any and all combinations of one or more of the associated listed items. It should also be understood that the terminologies “comprising” and/or “including” indicate the presence of the stated feature, region, integer, step, operation, element and/or part but do not exclude one or more additional features, regions, integers, steps, elements, parts, and/or combinations thereof. 
       FIG.  1    is a schematic view illustrating a system of a pixel circuit according to an embodiment of the disclosure. With reference to  FIG.  1   , in this embodiment, a pixel circuit PIXa includes a light emitting element EMD, a first local light emitting switch FSW 1 , a second local light emitting switch FSW 2 , a common light emitting switch GSW, and a driving block DVBK. 
     The light emitting element EMD has one terminal coupled to a common terminal and has a first light emitting part PEM 1  and a second light emitting part PEM 2 . Here, the light emitting element EMD is a nanorod light emitting element, which should however not be construed as a limitation in the disclosure. The first local light emitting switch FSW 1  has a first terminal coupled to a first power terminal TP 1 , a control terminal receiving a first frame light emitting signal FRAME_A, and a second terminal. The second local light emitting switch FSW 2  has a first terminal coupled to a second power terminal TP 2 , a control terminal receiving a second frame light emitting signal FRAME_B, and a second terminal. 
     The common light emitting switch GSW has a first terminal, a control terminal receiving a common light emitting signal GEM, and a second terminal coupled to the other terminal of the light emitting element EMD. The driving block DVBK receives a data signal XDATA, a first frame gate signal GATE_A, and a second frame gate signal GATE_B and is coupled to the second terminal of the first local light emitting switch FSW 1 , the second terminal of the second local light emitting switch FSW 2 , and the first terminal of the common light emitting switch GSW. The driving block DVBK generates one of a first current path PATH_A and a second current path PATH_B based on the first frame gate signal GATE_A and the second frame gate signal GATE_B, the first current path PATH_A is generated between the second terminal of the first local light emitting switch FSW 1  and the first terminal of the common light emitting switch GSW, and a first driving current I 1  is transmitted through the first current path PATH_A; the second current path PATH_B is generated between the second terminal of the second local light emitting switch FSW 2  and the first terminal of the common light emitting switch GSW, and a second driving current I 2  is transmitted through the second current path PATH_B. 
     In this embodiment, the first driving current I 1  serves to drive the first light emitting part PEM 1 , and the second driving current I 2  serves to drive the second light emitting part PEM 2 , wherein a direction of the first driving current I 1  is opposite to a direction of the second driving current I 2 . That is, the first light emitting part PEM 1  may be considered as being driven in a forward manner, and the second light emitting part PEM 2  may be considered as being driven in a reverse manner. The data signal XDATA sets a current amplitude of the first driving current I 2  and the second driving current I 2 , so as to determine light emitting brightness of the first light emitting part PEM 1  and the second light emitting part. By means of the well-designed driving block, the forward current (e.g., the first driving current I 1 ) required by the light emitting element driven in a forward manner and the reverse current (e.g., the second driving current I 2 ) required by the light emitting element driven in a reverse manner may be provided, so that the pixel circuit may operate smoothly. 
     In this embodiment, the first local light emitting switch FSW 1 , the second local light emitting switch FSW 2 , and the common light emitting switch GSW are all p-type transistors, for instance, which should however not be construed as a limitation in the disclosure. 
     In this embodiment, a voltage of the first power terminal TP 1  is different from a voltage of the second power terminal TP 2 . For instance, the voltage of the first power terminal TP 1  may be greater than the voltage of the second power terminal TP 2 , and a voltage of the common terminal TPC ranges from the voltage of the first power terminal TP 1  and the voltage of the second power termina TP 2 . Hence, the first driving current I 1  transmitted through the first current path PATH_A is a forward current, and the second driving current I 2  transmitted through the second current path PATH_B is a reverse circuit. 
       FIG.  2    is a schematic circuitry view illustrating a pixel circuit according to an embodiment of the disclosure.  FIG.  2    is a schematic circuit view illustrating a pixel circuit according to an embodiment of the disclosure. With reference to  FIG.  1    and  FIG.  2   , the same or similar elements are marked by the same or similar reference numbers. In this embodiment, the driving block DVBK includes a first switch SW 1 , a second switch SW 2 , a third switch SW 3 , a fourth switch SW 4 , a fifth switch SW 5 , a sixth switch SW 6 , a seventh switch SW 7 , an eighth switch SW 8 , a ninth switch SW 9 , a tenth switch SW 10 , a first capacitor C 1 , and a second capacitor C 2 . 
     The first switch SW 1  has a first terminal coupled to the first power terminal TP 1 , a control terminal that receives the first frame light emitting signal FRAME_A, and a second terminal. The second switch SW 2  has a first terminal coupled to the second terminal of the first switch SW 1 , a control terminal that receives a set signal SET, and a second terminal that receives a first direct current level IR_DC. The third switch SW 3  has a first terminal that receives the data signal XDATA, a control terminal that receives the first frame gate signal GATE_A, and a second terminal that is coupled to the second terminal of the first local light emitting switch FSW 1 . 
     The fourth switch SW 4  has a first terminal coupled to the second terminal of the first local light emitting switch FSW 1 , a control terminal that receives the second frame gate signal GATE_B, and a second terminal. The first capacitor C 1  is coupled between the second terminal of the first switch SW 1  and the second terminal of the fourth switch SW 4 . The fifth switch SW 5  has a first terminal coupled to the second terminal of the fourth switch SW 4 , a control terminal that receives a reset signal RESET, and a second terminal that receives a second direct current level RES_DC. 
     The sixth switch SW 6  has a first terminal coupled to the second terminal of the first local light emitting switch FSW 1 , a control terminal coupled to the second terminal of the fourth switch SW 4 , and a second terminal. The seventh switch SW 7  has a first terminal that receives the data signal XDATA, a control terminal that receives the second frame gate signal GATE_B, and a second terminal coupled to the second terminal of the sixth switch SW 6 . The eighth switch SW 8  has a first terminal coupled to the second terminal of the seventh switch SW 7 , a control terminal that receives the first frame gate signal GATE_A, and a second terminal coupled to the second terminal of the fourth switch SW 4 . 
     The ninth switch SW 9  has a first terminal coupled to the other terminal of the light emitting element EMD, a control terminal receiving the second frame light emitting signal FRAME_B, and a second terminal. The second capacitor C 2  is coupled between the second terminal of the eighth switch SW 8  and the second terminal of the ninth switch SW 9 . The tenth switch SW 10  has a first terminal coupled to the second terminal of the ninth switch SW 9 , a control terminal that receives the set signal SET, and a second terminal that receives the first direct current level IR_DC. 
     In this embodiment, the first switch SW 1  to the tenth switch SW 10  are all p-type transistors, for instance, which should however not be construed as a limitation in the disclosure. Besides, the second direct current level RES_DC may be different from the first direct current level IR_DC. 
       FIG.  3    is a schematic view illustrating an operating timing of a pixel circuit according to an embodiment of the disclosure. With reference to  FIG.  2    and  FIG.  3   , in this embodiment, a first frame period Frame_ 1  and a second frame period Frame_ 2  are illustrated as an example, and the second frame period Frame_ 2  is shown as the next frame period of the first frame period Frame_ 1 ; that is, there is no time interval between the second frame period Frame_ 2  and the first frame period Frame_ 1 . However, the disclosure embodiment is not so limited. 
     In this embodiment, the first frame light emitting signal FRAME_A is enabled in a plurality of first light emitting periods PM 1  of the first frame period Frame_ 1 , the second frame light emitting signal FRAME_B is enabled in a plurality of second light emitting periods PM 2  of the second frame period Frame_ 2 , and the common light emitting signal GEM is enabled in the first light emitting periods PM 1  of the first frame period Frame_ 1  and the second light emitting periods PM 2  of the second frame period Frame_ 2 . 
     The reset signal RESET is enabled in a first reset period PR 1  of the first frame period Frame_ 1  and a second reset period PR 2  of the second frame period Frame_ 2 , the first frame gate signal GATE_A is enabled in a first set period PS 1  of the first frame period Frame_ 1 , the second frame gate signal GATE_B is enabled in a second set period PS 2  of the second frame period Frame_ 2 , and the set signal SET is enabled in the first reset period PR 1  and the first set period PS 1  of the first frame period Frame_ 1  and the second reset period PR 2  and the second set period PS 2  of the second frame period Frame_ 2 . 
     In this embodiment, the first set period PS 1  follows the first reset period PR 1 , and the second set period PS 2  follows the second reset period PR 2 . The first light emitting periods PM 1  are cyclically arranged in the first frame period Frame_ 1 , and the second light emitting periods PM 2  are cyclically arranged in the second frame period Frame_ 2 . The first set period PS 1  and the first reset period PR 1  do not overlap the first light emitting periods PM 1 , and the second set period PS 2  and the second reset period PR 2  do not overlap the second light emitting periods PM 2 . 
       FIG.  4 A  is a schematic view illustrating an operation of a pixel circuit in a first reset period and a second reset period according to an embodiment of the disclosure. With reference to  FIG.  2   ,  FIG.  3   , and  FIG.  4 A , in the first reset period PR 1  of the first frame period Frame_ 1  and the second reset period PR 2  of the second frame period Frame_ 2 , the reset signal RESET and the set signal SET are enabled, and the first frame gate signal GATE_A, the second frame gate signal GATE_B, the common light emitting signal GEM, the first frame light emitting signal FRAME_A, and the second frame light emitting signal FRAME_B are disabled. 
     At this time, the second switch SW 2 , the fifth switch SW 5 , and the tenth switch SW 10  are turned on, and the first local light emitting switch FSW 1 , the second local light emitting switch FSW 2 , the common light emitting switch GSW, the first switch SW 1 , the third switch SW 3 , the fourth switch SW 4 , the sixth switch SW 6 , the seventh switch SW 7 , the eighth switch SW 8 , and the ninth switch SW 9  are turned off. Therefore, the first capacitor C 1  and the second capacitor C 2  store the voltage difference between the first direct current level IR_DC and the second direct current level RES_DC. Here, the voltage difference between the first direct current level IR_DC and the second direct current level RES_DC may serve to compensate a threshold voltage of the transistor or adjust the displayed brightness, which should however not be construed as a limitation in the disclosure. 
       FIG.  4 B  is a schematic view illustrating an operation of a pixel circuit in a first set period and a second set period according to an embodiment of the disclosure. With reference to  FIG.  2   ,  FIG.  3   , and  FIG.  4 B , in the first set period PS 1  of the first frame period Frame_ 1 , the set signal SET and the first frame gate signal GATE_A are enabled, and the reset signal RESET, the second frame gate signal GATE_B, the common light emitting signal GEM, the first frame light emitting signal FRAME_A, and the second frame light emitting signal FRAME_B are disabled. 
     At this time, the second switch SW 2 , the third switch SW 3 , the sixth switch SW 6 , the eighth switch SW 8 , and the tenth switch SW 10  are turned on, and the first local light emitting switch FSW 1 , the second local light emitting switch FSW 2 , the common light emitting switch GSW, the first switch SW 1 , the fourth switch SW 4 , the fifth switch SW 5 , the seventh switch SW 7 , and the ninth switch SW 9  are turned off. Therefore, the first capacitor C 1  and the second capacitor C 2  store the sum of the voltage difference between the first direct current level IR_DC and the second direct current level RES_DC and the voltage level of the data signal XDATA. 
       FIG.  4 C  is a schematic view illustrating an operation of a pixel circuit in a first light emitting period according to an embodiment of the disclosure. With reference to  FIG.  2   ,  FIG.  3   , and  FIG.  4 C , in the first light emitting periods PM 1  of the first frame period Frame_ 1 , the common light emitting signal GEM and the first frame light emitting signal FRAME_A are enabled, and the set signal SET, the reset signal RESET, the first frame gate signal GATE_A, the second frame gate signal GATE_B, and the second frame light emitting signal FRAME_B are disabled. 
     At this time, the first local light emitting switch FSW 1 , the common light emitting switch GSW, the first switch SW 1 , and the sixth switch SW 6  are turned on, and the second local light emitting switch FSW 2 , the second switch SW 2 , the third switch SW 3 , the fourth switch SW 4 , the fifth switch SW 5 , the seventh switch SW 7 , the eighth switch SW 8 , the ninth switch SW 9 , and the tenth switch SW 10  are turned off. Besides, the first driving current I 1  is transmitted to the first light emitting part PEM 1  through the first local light emitting switch FSW 1 , the sixth switch SW 6 , and the common light emitting switch GSW that are turned on. Since the degree of conduction of the sixth switch SW 6  is associated with the voltage stored by the first capacitor C 1 , the current amplitude of the first driving current I 1  is associated with the data signal XDATA. 
       FIG.  4 D  is a schematic view illustrating an operation of a pixel circuit in a second set period according to an embodiment of the disclosure. With reference to  FIG.  2   ,  FIG.  3   , and  FIG.  4 D , in the second set period PS 2  of the second frame period Frame_ 2 , the set signal SET and the second frame gate signal GATE_B are enabled, and the reset signal RESET, the first frame gate signal GATE_A, the common light emitting signal GEM, the first frame light emitting signal FRAME_A, and the second frame light emitting signal FRAME_B are disabled. 
     At this time, the second switch SW 2 , the fourth switch SW 4 , the sixth switch SW 6 , the seventh switch SW 7 , and the tenth switch SW 10  are turned on, and the first local light emitting switch FSW 1 , the second local light emitting switch FSW 2 , the common light emitting switch GSW, the first switch SW 1 , the third switch SW 3 , the fifth switch SW 5 , the eighth switch SW 8 , and the ninth switch SW 9  are turned off. Therefore, the first capacitor C 1  and the second capacitor C 2  still store the sum of the voltage difference between the first direct current level IR_DC and the second direct current level RES_DC and the voltage level of the data signal XDATA. 
       FIG.  4 E  is a schematic view illustrating an operation of a pixel circuit in a second light emitting period according to an embodiment of the disclosure. With reference to  FIG.  2   ,  FIG.  3   , and  FIG.  4 E , in the second light emitting periods PM 2  of the first frame period Frame_ 2 , the common light emitting signal GEM and the second frame light emitting signal FRAME_B are enabled, and the set signal SET, the reset signal RESET, the first frame gate signal GATE_A, the second frame gate signal GATE_B, and the first frame light emitting signal FRAME_A are disabled. 
     At this time, the first local light emitting switch FSW 1 , the common light emitting switch GSW, the sixth switch SW 6 , and the ninth switch SW 9  are turned on, and the second local light emitting switch FSW 2 , the first switch SW 1 , the second switch SW 2 , the third switch SW 3 , the fourth switch SW 4 , the fifth switch SW 5 , the seventh switch SW 7 , the eighth switch SW 8 , and the tenth switch SW 10  are turned off. Besides, the second driving current I 2  is received from the second light emitting part PEM 1  through the second local light emitting switch FSW 2 , the sixth switch SW 6 , and the common light emitting switch GSW that are turned on. Since the degree of conduction of the sixth switch SW 6  is associated with the voltage stored by the second capacitor C 2 , the current amplitude of the second driving current I 2  is associated with the data signal XDATA. 
       FIG.  5    is a schematic view illustrating a system of a pixel circuit according to another embodiment of the disclosure. With reference to  FIG.  1    and  FIG.  5   , a pixel circuit PIXb is substantially the same as the pixel circuit PIXa, while the difference therebetween lies in that the pixel circuit PIXb further includes a pulse width control block PWBK, where the same or similar elements are marked by the same or similar reference numbers. In this embodiment, the pulse width control block PWBK is coupled to the control terminal of the common light emitting switch GSW and receives a time reference direct current level T_DC, a time voltage slope reference signal TVR, and a time data signal TDATA, so as to provide a common light emitting signal GEMX in replacement of the common light emitting signal GEM. Here, the common light emitting signal GEMX is adjusted based on the time data signal TDATA. 
     To sum up, the pixel circuit provided in one or more embodiments of the disclosure may, by means of the well-designed driving block, provide the first driving current and the second driving current that flow in different directions and are required by the light emitting element with the bi-directional driving capability, so that the pixel circuit may be applied to the novel light emitting element and may operate smoothly. 
     It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided they fall within the scope of the following claims and their equivalents.