Patent Publication Number: US-11662447-B2

Title: Trans-impedance amplifier (TIA) for ultrasound devices

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 62/758,453, filed Nov. 9, 2018, entitled “TRANS-IMPEDANCE AMPLIFIER (TIA) FOR ULTRASOUND DEVICES,” the entire contents of which is incorporated by reference herein. 
    
    
     BACKGROUND 
     Field 
     The present application relates to ultrasound devices having an amplifier for amplifying received ultrasound signals. 
     Related Art 
     Ultrasound probes often include one or more ultrasound sensors, which sense ultrasound signals and produce corresponding electrical signals. The electrical signals are processed in an analog or a digital domain. Sometimes, ultrasound images are generated from the processed electrical signals. 
     BRIEF SUMMARY 
     According to an aspect of the present technology described herein, an ultrasound apparatus is provided, comprising an ultrasound sensor and a variable-current trans-impedance amplifier (TIA). The variable current TIA is coupled to the ultrasound sensor and configured to receive and amplify an output signal from the ultrasound sensor. The variable-current TIA has a variable current source. 
     According to an aspect of the present technology, a method is provided, comprising acquiring an ultrasound signal with an ultrasound sensor during an acquisition period and outputting, from the ultrasound sensor, an analog electrical signal representing the ultrasound signal. The method further comprises amplifying the electrical signal with a variable-current trans-impedance amplifier (TIA), including varying a current of the variable-current TIA during the acquisition period. 
     According to an aspect of the present application, a method is provided, comprising acquiring an ultrasound signal with an ultrasound sensor during an acquisition period, and outputting, from the ultrasound sensor, an analog electrical signal representing the ultrasound signal. The method further comprises amplifying the electrical signal with a variable-current trans-impedance amplifier (TIA), including decreasing a noise floor of the variable current TIA during the acquisition period. 
     According to an aspect of the present technology, an ultrasound apparatus is provided, comprising a variable current trans-impedance amplifier (TIA) configured to receive and amplify an output signal from an ultrasound sensor and having a variable-current source and a differential input stage comprising two pairs of N-P transistors. 
     According to an aspect of the present technology, an ultrasound apparatus is provided, comprising an ultrasound sensor, a variable-current trans-impedance amplifier (TIA) coupled to the ultrasound sensor and configured to receive and amplify an output signal from the ultrasound sensor. The variable-current TIA has a variable current source with an input quadrature transistor arrangement with current sharing. 
     According to an aspect of the present technology, an ultrasound apparatus is provided, comprising an ultrasound sensor, and a variable-current trans-impedance amplifier (TIA) coupled to the ultrasound sensor and configured to receive and amplify an electrical signal representing an output signal from the ultrasound sensor. The variable-current TIA has an input stage with a first pair of N and P transistors each having a control terminal configured to receive the electrical signal and a second pair of N and P transistors each having a control terminal configured to receive a bias signal. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       Various aspects and embodiments of the application will be described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear. 
         FIG.  1    is a block diagram of an ultrasound device including an amplifier for amplifying an ultrasound signal, according to a non-limiting embodiment of the present application. 
         FIG.  2    is a block diagram showing the amplifier of  FIG.  1    in greater detail, according to a non-limiting embodiment of the present application. 
         FIG.  3 A  is a circuit diagram illustrating an implementation of the amplifier of  FIG.  2   , according to a non-limiting embodiment of the present application. 
         FIG.  3 B  is a circuit diagram of an implementation of one variable impedance circuit of  FIG.  3 A , according to a non-limiting embodiment of the present application. 
         FIG.  3 C  is a circuit diagram of an implementation of another variable impedance circuit of  FIG.  3 A , according to a non-limiting embodiment of the present application. 
         FIG.  3 D  is a circuit diagram of an alternative to a portion of the amplifier of  FIG.  3 A . 
         FIG.  4    is a graph illustrating a behavior of two variable current sources of an amplifier during an acquisition period, as may be implemented by the amplifier of  FIGS.  2  and  3 A , according to a non-limiting embodiment of the present application. 
         FIG.  5    is a graph illustrating an electrical signal representing an ultrasound signal, and a noise floor of an amplifier during an acquisition period, according to a non-limiting embodiment of the present application. 
     
    
    
     DETAILED DESCRIPTION 
     Aspects of the present technology described herein relate to amplification circuitry for an ultrasound device. An ultrasound device may include one or more ultrasonic transducers configured to receive ultrasound signals and produce electrical output signals. Thus, the ultrasonic transducers may be operated as ultrasound sensors. The ultrasound device may include one or more amplifiers for amplifying the electrical output signals. An amount of power consumed by an amplifier, a noise generated by the amplifier, and a linear signal-amplification quality provided by the amplifier may depend on an amount of current consumed by the amplifier. In some embodiments, the amplifier may have a variable current source. The variable current source may be adjusted during acquisition of an ultrasound signal to maintain the noise level of the amplifier below the amplifier&#39;s signal level and to maintain a linear amplification of the signal while at the same time reducing the amount of power consumed by the amplifier. In some embodiments, the amplifier may be a TIA. 
     According to an aspect of the present technology, a variable-current TIA is provided that exhibits beneficial power performance for a given noise level. The variable-current TIA may include an input stage configured to receive a signal at transistors of opposite polarities, such as N-type and P-type MOSFETs. The transistors of opposite polarities may be arranged in input pairs, as a quad input configuration, with an input pair representing two transistors of opposite polarities (e.g., one N-type MOSFET and one P-type MOSFET) configured to receive a same input voltage at control terminals thereof. Current through the input pairs of transistors may be controlled to be substantially equal, thus providing reduced noise for a given power consumption of the variable-current TIA. In this manner, improved performance may be provided. 
     The aspects and embodiments described above, as well as additional aspects and embodiments, are described further below. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the present technology described herein is not limited in this respect. 
       FIG.  1    illustrates a circuit  100  for processing received ultrasound signals, according to some non-limiting embodiments of the present technology. The circuit  100  comprises N ultrasonic transducers  102   a  . . .  102   n  (sometimes collectively denoted “ 102 ” herein), wherein N is an integer, and N=n. In some embodiments, the ultrasonic transducers  102  may be sensors that produce electrical signals representing received ultrasound signals. The ultrasonic transducers  102  may also transmit ultrasound signals in some embodiments. The ultrasonic transducers  102  may be capacitive micromachined ultrasonic transducers (CMUTs) in some embodiments. The ultrasonic transducers may be piezoelectric micromachined ultrasonic transducers (PMUTs) in some embodiments. As will be appreciated, alternative types of ultrasonic transducers may be used for the ultrasonic transducers  102  in other embodiments. 
     The circuit  100  further comprises N circuitry channels  104   a  . . .  104   n . The circuitry channels may correspond to respectively to the ultrasonic transducers  102   a  . . .  102   n . For example, there may be eight ultrasonic transducers  102   a  . . .  102   n  and eight corresponding circuitry channels  104   a  . . .  104   n . In some embodiments, the number of ultrasonic transducers  102   a  . . .  102   n  may be greater than the number of circuitry channels. 
     The circuitry channels  104   a  . . .  104   n  may include transmit circuitry, or receive circuitry, or both. The transmit circuitry may include transmit decoders  106   a  . . .  106   n  coupled to respectively to pulsers  108   a  . . .  108   n . The pulsers  108   a  . . .  108   n  may respectively control the ultrasonic transducers  102   a  . . .  102   n  to emit ultrasound signals. 
     The receive circuitry of the circuitry channels  104   a  . . .  104   n  may receive the electrical signals output respectively from the ultrasonic transducers  102   a  . . .  102   n . In the illustrated example, each circuitry channel  104   a  . . .  104   n  includes a respective receive switch  110   a  . . .  110   n  and a respective amplifier  112   a  . . .  112   n . The receive switches  110   a  . . .  110   n  may be controlled to activate/deactivate readout of respective electrical signals from the ultrasonic transducers  102   a  . . .  102   n . As will be appreciated, the receive switches  110   a  . . .  110   n  may be receive circuits, because alternative circuit structures, which may perform one or more function(s) of a switch, may be employed to perform a same or similar function as a switch. The amplifiers  112   a  . . .  112   n , as well as an amplifier  300  of  FIG.  3    (described below), may be TIAs in some embodiments. One or more of the amplifiers  112   a  . . .  112   n  may be variable-current amplifier(s). As will be described further below, a current of the amplifiers  112   a  . . .  112   n  may be varied during an acquisition period, thus enabling any one or any combination of: power consumption, noise level, and amplifier linearity to be adjusted. The amplifiers  112   a  . . .  112   n  may output analog signals. 
     The circuit  100  further comprises an averaging circuit  114 , which may also be referred to herein as a summer or a summing amplifier. In some embodiments, the averaging circuit  114  may be a buffer or an amplifier. The averaging circuit  114  may receive output signals from one or more of the amplifiers  112   a  . . .  112   n  and may output or provide an averaged output signal. The averaged output signal may be formed in part by adding or subtracting the signals from the various amplifiers  112   a  . . .  112   n . The averaging circuit  114  may include a variable feedback resistance. A value of the variable feedback resistance may be adjusted dynamically based upon a number of the amplifiers  112   a  . . .  112   n  from which the averaging circuit  114  receives signals. In some embodiments, the variable feedback resistance may include N resistance settings. That is, the variable feedback resistance may have a number of resistance settings corresponding to a number of the circuitry channels  104   a  . . .  104   n . Thus, the average output signal may also be formed in part by application of a selected resistance to a combined signal inputted to the averaging circuit  114 . 
     The averaging circuit  114  may be coupled to an auto-zero block  116 . The auto-zero block  116  may be coupled to a programmable gain amplifier  118 , which may include an attenuator  120  and a fixed gain amplifier  122 . The programmable gain amplifier  118  may be coupled to an ADC  126  via ADC drivers  124 . In the illustrated example, the ADC drivers  124  include a first ADC driver  125   a  and a second ADC driver  125   b . The ADC  126  may digitize the signal(s) from the averaging circuit  114 . 
     Although  FIG.  1    illustrates a number of components as part of a circuit of an ultrasound device, it should be appreciated that aspects of the present technology described herein are not limited to the exact components or configurations of components illustrated. For example, aspects of the present technology may relate to the amplifiers  112   a  . . .  112   n , and one or more component(s) illustrated downstream of the amplifiers  112   a  . . .  112   n  in the circuit  100  may be optional in some embodiments. 
     The components of  FIG.  1    may be located on a single substrate or on different substrates. For example, as illustrated, the ultrasonic transducers  102   a  . . .  102   n  may be on a first substrate  128   a  and the remaining illustrated components may be on a second substrate  128   b . The first and/or second substrates  128   a ,  128   b  may be semiconductor substrates, such as silicon substrates. In an alternative embodiment, the components of  FIG.  1    may be on a single substrate. For example, the ultrasonic transducers  102   a  . . .  102   n  and the other illustrated circuitry may be monolithically integrated on a same semiconductor die. Such integration may be facilitated by using CMUTs as the ultrasonic transducers  102   a  . . .  102   n.    
     According to an embodiment, the components of  FIG.  1    may form part of an ultrasound probe. The ultrasound probe may be sized and structured to be handheld. In some embodiments, the components of  FIG.  1    may form part of an ultrasound patch configured to be worn by a patient. 
       FIG.  2    illustrates a non-limiting example of the amplifier  112   a  of  FIG.  1    in greater detail. The same configuration may be used for the other amplifiers  112   a  . . .  112   n  of  FIG.  1   . For context, the ultrasonic transducer  102   a  and the averaging circuit  114  are also illustrated in  FIG.  2   , whereas for simplicity the receive switch  110   a  is omitted from  FIG.  2   . 
     In this non-limiting embodiment, the amplifier  112   a  is implemented as a two-stage operational amplifier (“op-amp” for short). A first stage  202  may be coupled to the ultrasonic transducer  102   a . The second stage  204  may be coupled between the first stage  202  and the averaging circuit  114 . The second stage  204  may provide an output signal of the amplifier  112   a , in this non-limiting example. 
     The first stage  202  and the second stage  204  may each have a variable current source  203 ,  205 . The variable current source  203  may be provided for the first stage  202  and may sink a current I 1 . The variable current source  205  may be provided for the second stage  204  and may sink a current I 2 . Although the variable current sources  203  and  205  are illustrated as distinct from the respective stages  202  and  204 , they may be considered part of the respective stages  202  and  204 . 
     With a two-stage amplifier construction as shown in  FIG.  2   , the noise and the linearity of the amplified signal may be controlled independently. The noise of the amplifier  112   a  may be impacted primarily by the first stage  202 . The linearity of the amplifier  112   a  may be impacted primarily by the second stage  204 . More generally, the same may be true for a multi-stage amplifier having two or more stages, such that the noise of the amplifier may be impacted primarily by the first stage and the linearity of the amplifier may be impacted primarily by the last stage. The inventors have appreciated that during acquisition of an ultrasound signal, referred to herein as an acquisition period, the noise and the linearity of the amplified signal may vary in importance. When the ultrasound signal is initially received, early in the acquisition period and corresponding to relatively shallower depths from which reflected ultrasound waves forming the ultrasound signal as a reflected signal, the noise associated with this early or initial acquisition period will be relatively lower in amplitude compared to the amplitude of the received signal, but the linearity of the amplified signal may be of relatively higher importance. However, later during the acquisition period and corresponding to relatively greater depths from which reflected ultrasound waves forming the ultrasound signal as a reflected signal, the ultrasound signal is likely to be relatively smaller in amplitude, and thus the noise of the signal is of increased importance. Thus, the amplifier  112   a  of  FIG.  2    is designed to allow for independent and variable control of noise and linearity. Such control may be provided via the variable current sources  203  and  205 . 
     Early during an acquisition period, the variable current source  203  may be controlled to sink a relatively small amount of current, while the current source  205  may be controlled to sink a relatively large amount of current. In such a scenario, the second stage  204  may operate to control the linearity of the amplified signal produced by the amplifier  112   a , while the first stage  202  may operate to control the noise of the amplified signal  202  to a lesser extent than that to which it is capable. Later in the acquisition period, the variable current source  203  may be controlled to sink an increased amount of current while the variable current source  205  may be controlled to sink a decreased amount of current. As the current sunk by the variable current source  203  is increased, the first stage  202  may operate to control the noise of the amplifier  112   a  to a greater extent. As the current sunk by the variable current source  205  is decreased, the second stage  204  may operate to control the linearity of the amplifier  112   a  to a lesser extent. Thus, dynamic current biasing of the amplifier  112   a , and more specifically the dynamic biasing of the first stage  202  and the second stage  204 , may be implemented to control power, noise, and linearity characteristics of the amplifier  112   a  during an acquisition period. 
     The dynamic control of the current sources  203  and  205  may be achieved using a digital controller  330 , in an example arrangement shown in  FIG.  3 A . The variable current sources  203  and  205  may each include two or more programmable current settings. The greater the number of settings, the greater the control over the current sunk by the current sources  203  and  205 . 
     The amplifier  112   a  also may include a variable feedback impedance  206 . In some embodiments, the variable feedback impedance  206  may be a variable RC feedback circuit. An example of such a variable RC feedback circuit is illustrated in  FIG.  3 A  and described in connection with that figure. Feedback impedance may determine a transimpedance gain of a transimpedance amplifier (TIA), such that an input current signal may be converted into an output voltage of varying amplitude. 
     It should be appreciated from  FIG.  2    and the foregoing description that an embodiment of the present technology may provide a multi-stage TIA having two or more independently controllable variable current sources, with a variable feedback impedance. The variable current sources may allow for dynamic current biasing of the TIA, for example during an acquisition period. Thus, the power consumption, noise, and linearity of the amplifier may be adjusted during the acquisition period. 
       FIG.  3 A  is a circuit diagram illustrating an implementation of the amplifier  112   a  of  FIG.  2   , according to a non-limiting embodiment of the present application. The amplifier  300  has an input  302  and an output  304 . The input  302  may be coupled to an ultrasonic transducer or a receive switch, as described previously in connection with  FIGS.  1  and  2   , and may receive an electrical signal representing an ultrasound signal received by the ultrasonic transducer. The output  304  may provide an amplified output signal of the amplifier  112   a , and may be coupled to an averaging circuit or other component to which it is desired to provide the amplified output signal. 
     The amplifier  300  includes a first stage  306  and a second stage  308 , which may be implementations of the first stage  202  and the second stage  204  of  FIG.  2   , respectively. The first stage  306  includes an NMOS transistor  310  having a gate configured to receive the signal at the input  302 . A PMOS transistor  312  and a PMOS transistor  314  may have their gates coupled, with the drain of the PMOS transistor  312  coupled to the drain of the NMOS transistor  310 . The gate of the transistor  312  may be coupled to its drain. The transistors  312  and  314  may also be configured to receive a power supply voltage VDDA. The first stage  306  may further comprise an NMOS transistor  316  having a gate configured to receive a bias voltage provided by an RC circuit. The RC circuit includes two resistors, of value R, with a capacitor C b  coupled in parallel with one of the two resistors; the other of the two resistors may receive the power supply voltage VDDA. The drain of the PMOS transistor  314  may be coupled to the drain of the NMOS transistor  316 . An example value for R is 50 kOhm and an example value for C b  is 10 pF, although alternatives for both are possible, such as +/−20% of those values listed, or any value or range of values within such ranges. 
     The second stage  308  includes a PMOS transistor  318  configured to receive the output of the first stage  306 . In particular, the gate of the PMOS transistor  318  is coupled to a node between the transistors  314  and  316  of the first stage  306 . The source of PMOS the transistor  318  receives the power supply voltage VDDA. A variable impedance circuit  320  is also provided in the second stage  308 . The variable impedance circuit  320  includes a variable capacitor C C  in series with a variable resistor R Z , and thus is a variable RC circuit in this embodiment. The variable impedance circuit  320  may provide stable operation of the amplifier  300  when a gain of the amplifier  300 , or when currents of variable current sources  321 ,  325 , are varied. Thus, the variable impedance circuit  320  may be provided to maintain a stable operation of the amplifier  300  for all magnitudes of currents sunk by the variable current sources  321  and  325 . That is, values of the variable capacitor C C  and the variable resistor R Z  may be adjusted during operation of the amplifier  300  to account for different current settings that may be programmed by the digital controller  330   
     More specifically, a variable current source is provided for each of the stages  306  and  308 . The variable current source  321  for the first stage  306  includes three parallel connected current sources  322   a ,  322   b , and  322   c . The current source  322   a  sinks a current I A , the current source  322   b  sinks a current 2I A , and the current source  322   c  sinks a current 4I A . The current sources  322   a - 322   c  are coupled to the first stage  306  by respective switches  324   a ,  324   b , and  324   c , which effectively provide 3 bits (8 states) of current control. The current I A  may equal 100 microAmps, or +/−20% of that value, or any value or range of values within such ranges, as examples. 
     The variable current source  325  for the second stage  308  includes three parallel connected current sources  326   a ,  326   b , and  326   c . The current source  326   a  sinks a current I B , the current source  326   b  sinks a current 2I B , and the current source  326   c  sinks a current 4I B . The current sources  326   a - 326   c  are coupled to the second stage  308  by respective switches  328   a ,  328   b , and  328   c , which effectively provide 3 bits (8 states) of current control. The current I B  may equal 50 microAmps, or +/−20% of that value, or any value or range of values within such ranges, as examples. 
     Although  FIG.  3 A  illustrates variable current sources each including three parallel-coupled current sources, it should be appreciated that not all aspects of the present technology are limited in this manner. That is, variable current sources may be implemented in various manners, including alternative manners to those illustrated. For example, more or fewer than three current sources may be coupled in parallel to create a variable current source. Also, the current sources may have magnitudes that may be different than those disclosed herein. Any suitable magnitude(s) may be provided to allow for operation over a desired range of currents. 
     The digital controller  330  may be configured to control operation of the variable current sources  321  and  325 . The digital controller  330  may provide control signals to (digitally) program the currents of the variable current sources  321 ,  325 . In the illustrated example of  FIG.  3 A , the digital controller  330  provides one or more switching signals S 1  to control operation of the switches  324   a - 324   c , and one or more switching signals S 2  to control operation of the switches  328   a - 328   c . In this manner, an amount of current sunk by the variable current sources  321 ,  325  may be varied independently during operation of the amplifier  300 , for example during an acquisition period. According to a non-limiting example, the digital controller  330  decreases an amount of current sunk by the variable current source  325  during the acquisition period and increases an amount of current sunk by the variable current source  321  during the acquisition period, through suitable operation of the switching signals S 1  and S 2 . 
     The digital controller  330  may be any suitable type of controller. The digital controller  330  may include integrated circuitry. In some embodiments, the digital controller  330  may include or be part of an application specific integrated circuit (ASIC). In some embodiments, the digital controller  330  may not be specific to the amplifier  300 . For example, the digital controller  300  may be configured to control more than one component of the circuit of  FIG.  1   , any of which may be the amplifiers  112   a  . . .  112   n.    
     The amplifier  300  further includes a variable feedback impedance  332  formed by a variable capacitor C f  and a variable resistor R f . The capacitor C f  and the resistor R f  may be coupled between the output  304  and the input  302 , and may be arranged in parallel with each other. The variable feedback impedance  332  may control a gain of the amplifier  300 . Thus, values of the capacitor C f  and the resistor R f  may be adjusted to vary the gain of the amplifier  300 . 
     The variable feedback impedance  332  and the variable impedance circuit  320  may be controlled in any suitable manner. In one embodiment, the digital controller  330  may set values of feedback impedances. However, alternative manners of control may be used. 
     It should be appreciated that the described groupings of components in connection with  FIG.  3 A  are not limiting. For example, while certain components illustrated in that figure are described as being part of a first stage or a second stage, the identification of the first and second stages is not limiting. The first and second stages may include more, fewer, or different components than those illustrated. 
       FIG.  3 B  is a circuit diagram of an implementation of the variable impedance circuit  320  of  FIG.  3 A , according to a non-limiting embodiment of the present technology. The variable impedance circuit  320  includes a number of switches  340   a  . . .  340   n  arranged in parallel and configured to receive respective control signals SWa . . . SWn. In some embodiments, the digital controller  330  may provide the control signals SWa . . . SWn, although alternatives may be used. Each of the switches  340   a  . . .  340   n  is coupled in series with a respective capacitor C C  and a respective resistor R Z . An impedance of the variable impedance circuit  320  may be adjusted during an acquisition period through suitable provision of the control signals SWa . . . SWn. Any suitable number of parallel signal paths may be provided, so that the illustrated example of two parallel signal paths is non-limiting. The number of parallel signal paths of the switches  340   a  . . .  340   n  and capacitance and resistance values of the capacitors C C  and the resistors R Z  provided in the signal paths may be selected to provide sufficient control of the variable feedback impedance  332 , to obtain variable operation of the amplifier  300  across a range of operating scenarios resulting from variation of the variable current sources  321 ,  325 . For example, for a given amplifier gain dictated by variable feedback impedance  332 , appropriate settings of variable impedance circuit  320  may be selected. In some embodiments, a lookup table may be utilized to determine the appropriate settings of the variable impedance circuit  320  based on a given gain set by the variable feedback impedance  332 . 
     In both  FIGS.  3 A and  3 B , the values of C C  and R Z  may be selected to provide desired operating characteristics. As examples, R Z  may be equal to 3 kOhms in some embodiments, and C C  may be equal to 300 fF. Alternatives for both are possible. For example, they may assume values within +/−20% of those values listed, or any value or range of values within such ranges. 
       FIG.  3 C  is a circuit diagram of an implementation of the variable impedance circuit  332  of  FIG.  3 A , according to a non-limiting embodiment of the present technology. The variable impedance circuit  332  includes a number of complementary switches  350   a ,  350   b , . . .  350   n . The complementary switches  350   a ,  350   b , . . .  350   n  receive respective control signals SLa, SLb . . . SLn and SHa, SHb . . . SHn. The control signals SLa, SLb . . . SLn and SHa, SHb . . . SHn may be provided by the digital controller  330  in some embodiments, although alternatives may be used. The complementary switches  350   a ,  350   b , . . .  350   n  are coupled to respective parallel-connected RC circuits C f , R f . While three complementary switches  350   a ,  350   b ,  350   n  are shown in  FIG.  3 C , any suitable number may be provided to allow for sufficient control of the gain of the amplifier  300 . 
     In both  FIGS.  3 A and  3 C , the values of C f  and R f  may be selected to provide desired operating characteristics. As examples, R f  may be equal to 180 kOhms in some embodiments, and C f  may be equal to 84 fF. Alternatives for both are possible. For example, they may assume values within +/−20% of those values listed, or any value or range of values within such ranges. 
     According to an aspect of the present technology, an alternative two-stage variable-current TIA is configured to provide an increased transimpedance gain in a first stage and a reduced noise for a given power consumption. The variable-current TIA may utilize input N-type and P-type transistors (referred to herein as “N type” and “P type” for short), which share a same current, thus leading to performance characteristics as described above.  FIG.  3 D  illustrates a non-limiting example. 
     More specifically,  FIG.  3 D  illustrates a circuit diagram of an alternative to a portion of the first stage  306  of the amplifier  300  of  FIG.  3 A . Specifically, a first stage  360  shown in  FIG.  3 D  is an alternative to the first stage  306  of  FIG.  3 A . The first stage  360  includes an amplification portion comprising transistors  362   a ,  362   b ,  362   c , and  362   d , a local feedback comprising a transistor  364 , a current source comprising transistors  366  and  368 , and the previously-described RC circuit including resistors having a resistance value R and a capacitance value C b . 
     Amplification components of the first stage  360  may include two N-P transistor pairs, which may be considered more generally to be pairs of opposite polarity transistors. Namely, PMOS transistor  362   a  and NMOS transistor  362   b  form a first N-P transistor pair, and PMOS transistor  362   c  and NMOS transistor  362   d  form a second N-P transistor pair. These four transistors may also be referred to as a differential input quad, or an input quad (quadrature) transistor arrangement with current sharing, since a same current conducts through the two transistor pairs. The illustrated configuration of four transistors may also be referred to as a current-reused differential pair. As a result of the transistor pairs conducting substantially the same current as each other, the noise of the first stage  360  may be reduced by half for a given current consumption compared to the configuration of the first stage  306  in  FIG.  3 A . Alternatively, for a given noise level, the first stage  360  may consume approximately half the power consumed by the first stage  306 . 
     As illustrated, an input signal InN is input to control terminals (e.g., gates) of the transistors  362   a  and  362   b . Control terminals (e.g., gates) of the transistors  362   c  and  362   d  are biased by the illustrated RC network. That is, the transistors  362   a  and  362   b  receive a same input signal, and the transistors  362   c  and  362   d  receive a same input signal (a bias signal). Arranging the transistors  362   a - 362   d  in this manner means that both N-type and P-type transistors of a given transistor pair are receiving a same input signal. 
     An amplified output signal V amp  of the first stage  360  may be provided to a gate of the PMOS transistor  318  and the variable impedance circuit  320 , as in  FIG.  3 A . 
     As described above, the first stage  360  includes a current source comprising transistors  366  and  368 . The illustrated current source represents an example of a variable current source. However, a variable current source structured like either of the variable current sources  321 ,  325  of  FIG.  3 A  may be implemented instead. That is, multiple switchable current sources may be coupled together in the manner shown in  FIG.  3 A  for current sources  322   a ,  322   b , and  322   c , and used as the variable current source of  FIG.  3 D  instead of the transistors  366 ,  368 . 
     As described above, the first stage  360  also includes local feedback in the form of the transistor  364 . In the non-limiting example illustrated, the transistor  364  is a PMOS transistor. The local feedback operates to ensure that current through the two N-P transistor pairs is substantially equal. In theory, the local feedback is not needed for such a function, but in practice manufacturing differences between the transistors  362   a - 362   d  of the two N-P transistor pairs may result in unequal currents through those N-P transistor pairs. The local feedback operates to correct that behavior. 
     The first stage  360  may be used with the other circuit components of  FIG.  3 A , in the same manner as the first stage  306 . 
     As with the amplifier  300  of  FIG.  3 A  generally, the polarity of the transistors  362   a - 362   d  in the first stage  360  of  FIG.  3 D  may be reversed. That is, the PMOS transistors may instead be NMOS transistors, and vice versa. Operation of such a polarity-reversed first stage would be substantially the same as that of the first stage  360 . Thus, it should be appreciated that the amplifiers illustrated and described herein are not limited to a particular polarity of transistors, and that a “reversed” polarity arrangement, in which the transistor polarities of a given circuit may be reversed, is contemplated as part of the present disclosure. 
       FIG.  4    is a graph illustrating the behavior of two variable current sources of a variable current amplifier during an acquisition period, as may be implemented by the amplifiers of  FIGS.  2  and  3 A , which again may be TIAs. For example, the illustrated behavior may be implemented by the variable current sources  203  and  205  of  FIG.  2   . The x-axis represents time during an acquisition period, ranging from t 0  to t 8 . The y-axis represents a current of the current source, having values ranging from I 0  to I 7 . The values of t 0 -t 8  and I 0 -I 7  may be any suitable values for operation of a given ultrasound system, as the various aspects described herein are not limited to implementation of any specific time or current values. Also, the number of time intervals during an acquisition period is non-limiting, as more or fewer may be implemented. The number of current values that may be implemented is non-limiting, as more or fewer may be implemented. 
     Curve  402  represents a current of a variable current source of a second stage of a variable current amplifier. Thus, the curve  402  may represent a current of the current source  205  of  FIG.  2   . Curve  404  represents a current of a variable current source of a first stage of the variable current amplifier. Thus, the curve  404  may represent a current of the current source  203  of  FIG.  2   . 
       FIG.  4    illustrates that the currents of the first and second stages of the variable current amplifier move in opposing directions during the acquisition period. That is, the curve  402  decreases moving from time t 0  to time t 8 , while the curve  404  increases during the same time span. As previously described in connection with  FIG.  2   , the first and second stages of the variable current amplifier may impact different operational characteristics of the variable current amplifier, such as noise and linearity. Thus, when operating in the manner illustrated in  FIG.  4   , the impact of the two stages of the variable current amplifier may vary during the acquisition period. That is, the impact of the second stage may be greater initially, up to time t 4 , while the impact of the first stage may be greater thereafter, from time t 4  to time t 8 . 
     As previously described in connection with  FIG.  3 A , the currents of the two stages of a two-stage amplifier (e.g., a two-stage op-amp) being used to implement a variable current amplifier may be controlled by digital codes. Thus, the current values I 0 -I 7  of  FIG.  4    may correspond to different digital codes set by a digital controller, such as digital controller  330  of  FIG.  3 A . 
     While  FIG.  4    illustrates that the currents in the first and second stages of the amplifier switch at the same times, not all embodiments are limited in this respect. For example, the current in the second stage could be adjusted at times offset from those at which the current in the first stage is adjusted. Likewise, the currents of the two stages need not be adjusted the same number of times during an acquisition period. 
     As described previously, an aspect of the present application provides an amplifier with a variable current source which is controlled to adjust the noise of the amplifier during an acquisition period.  FIG.  5    illustrates an example of such operation. 
     In  FIG.  5   , the voltage of an electrical signal  502  output by an ultrasonic transducer, and thus representing a detected ultrasound signal, is illustrated as a function of time. Dashed line  504  represents a noise floor of an amplifier used to amplify the electrical signal  502 , and may correspond to a noise floor of an amplifier of the types described herein, such as amplifier  112   a . It can be seen that during the acquisition period, the magnitude of the electrical signal decreases. Likewise, the noise floor of the amplifier is decreased. Such a decrease in the noise floor may be achieved by controlling the current sunk by a variable current source of the amplifier, in the manner described previously herein. For example, referring to  FIG.  2   , the variable current source  203  may be increased during the acquisition period to decrease the noise floor of the amplifier  112   a . The noise floor may be adjusted to a level that provides an acceptable signal-to-noise ratio (SNR). 
       FIG.  5    also illustrates a constant noise floor  506 . It can be seen that while the constant noise floor  506  is at the same level as dashed line  504  toward the end of the acquisition period, the constant noise floor  506  is lower than the value of the dashed line  504  up to that point. As has been described herein, the noise level of an amplifier may be dependent on the current consumed by the amplifier; in such situations it should be appreciated that operating with the constant noise floor  506  requires significantly more current (and therefore power) than operating according to the noise floor  504 . Thus, aspects of the present application enable a variable current amplifier to amplify ultrasound signals at substantial power savings compared to amplifiers operating with a constant noise level. 
     The amount of power savings may be significant. For example, in the circuit  100 , the amplifiers  112   a  . . .  112   n  may consume a significant amount of power. In some embodiments, the amplifiers  112   a  . . .  112   n  may consume more power than any other components of the circuit  100 . Accordingly, reducing the power consumption of the amplifiers  112   a  . . .  112   n  may provide a significant reduction in power consumed by the circuit  100 . In some embodiments, utilizing variable current amplifiers of the types described herein may provide up to a 25% power reduction, up to a 40% power reduction, up to a 50% power reduction, or any range or value within such ranges, in terms of the operation of the amplifier. The resulting power reduction for the circuit  100  may be up to 10%, up to 20%, up to 25%, or any range or value within such ranges. 
     Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. 
     As an example, certain embodiments described herein have focused on two-stage amplifiers. However, the techniques described herein may apply to multi-stage amplifiers having two or more stages. When more than two stages are used, the first stage may predominantly control the noise of the amplifier, while the last stage may predominantly control the linearity of the amplifier. 
     As described, some aspects may be embodied as one or more methods. The acts performed as part of the method(s) may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments. 
     All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms. 
     The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. 
     As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. 
     As used herein, the term “between” used in a numerical context is to be inclusive unless indicated otherwise. For example, “between A and B” includes A and B unless indicated otherwise. 
     In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively.