Patent Publication Number: US-8119474-B2

Title: High performance capacitors in planar back gates CMOS

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is a divisional application of U.S. patent application Ser. No. 11/160,999, filed on Jul. 19, 2005, the contents of which are incorporated by reference in its entirety herein. 
    
    
     FIELD OF THE INVENTION 
     The invention relates to semiconductor devices, and more particularly to ultra-thin SOI based dual-gate CMOS capacitors and method of manufacture. 
     BACKGROUND DESCRIPTION 
     A conventional MOS (metal-oxide semiconductor) capacitor can be modeled as a parallel plate capacitor. In this type of structure, one plate may be made from a metal or a heavily-doped polycrystalline silicon (“poly”) and one plate may be made from a semiconductor (e.g., the inversion layer formed when the MOS capacitor is under high forward bias). An insulator such as SiO 2  or “oxide”, for example, may be used to separate the two plates. In deeply scaled ultra-thin SOI (silicon on insulator) devices, the insulation layer, e.g., oxide, beneath the source and drain regions, is made thinner to improve MOS transistor performance. Although this results in a faster transistor, the thinner channel region and dopant solid solubility limits the amount of active dopants that can be placed in the channel. This results in the effective series resistance becoming quite large in the capacitor. This may pose many problems from a circuit standpoint. 
     More specifically, in ultra-thin SOI MOS devices, the n-channel FET of the nMOS transistor is made of p-type silicon, and the p-channel FET of the pMOS transistor is made of n-type silicon. Heavily-doped source and drain regions provide electrodes to contact the previously mentioned channel region. In an SOI MOS device, an oxide region is created beneath the channel. The oxide region electrically isolates the source, drain, and channel regions of device from the substrate. The MOS threshold voltage of the channel, i.e., the gate potential when charge carriers can flow through the channel from the source to the drain in significant quantities, is determined by factors such as the work function of the gate, any channel dopants, and the dimensions of the transistor structure. However, low mobile channel charge in a SOI MOS device can under certain conditions have large effective resistance (equivalent serial resistance (ESR)). This large ESR has a great influence on the performance of the capacitor. For example, an increase in the effective resistance of the capacitor will result in worsening frequency characteristics of the capacitor. 
     A more detailed model of the MOS structure decomposes the vertical gate-dielectric-substrate gate “stack” into two capacitors in series, e.g., a linear oxide capacitance and a nonlinear channel capacitance. By way of example, if the voltage on the gate is strongly negative on an N-type MOS structure, holes are attracted to the dielectric-substrate interface and accumulate there. In the accumulation regime, MOS capacitors act approximately as linear capacitors. On the other hand, if the gate voltage is made positive on an N-type MOS structure, the surface is depleted of mobile holes, creating a depleted region with exposed dopant ions. The depletion capacitance is nonlinear due to the approximately square root dependence of the depletion charge on potential under the gate dielectric. But, as the gate voltage is raised further, the potential barrier between the source terminal and the channel is lower electrostatically and the channel is flooded with mobile electrons from the source. It is the presence of electrons in channel that indicates the inversion of the silicon near the surface, e.g., an NFET channel becomes n-type and analogously a PFET channel becomes p-type. 
     In the ultra-thin SOI devices, the depth of the silicon region beneath the gate stack is made very thin due to transistor scaling rules, where the bottom of the silicon region beneath the gate is bounded by the buried oxide. Even at channel doping levels near the solid solubility limit, the depletion region induced by the gate can extend from the gate to the back oxide creating a region that is depleted of mobile carriers, (i.e., “fully depleted”). 
     Weak inversion results when the number of mobile electrons (the inversion charge) is much lower than the number of exposed dopant ions in the depletion region (the depletion charge). On the other hand, strong inversion results when the inversion charge greatly exceeds the depletion charge. Also, the transition between strong inversion to moderate inversion can be defined as the condition when the inversion charge and the depletion charge are comparable. When the channel area under the gate is strongly inverted, the gate charge is balanced out primarily by the inversion layer charge. The voltage at which inversion layer charge dominates is called the threshold voltage Vt and Vt 0  indicates the threshold voltage when the source voltage equals zero. 
     In SOI MOS technologies, there are several modes of operation depending on the application of an external bias to the SOI channel region (also referred to as the silicon body). The silicon body is isolated from the substrate by the buried back oxide. This case, the floating body case, the potential in the body is controlled by many physical factors including diode junction currents from the source and drain, impact ionization near the drain, gate leakage, bipolar effects, and capacitive coupling to the device&#39;s electrical terminals the gate, source, drain, and body. An SOI body potential can be defined relative to the source potential and the body potential can be significantly forward-biased with respect to the source potential during normal operation. If an external potential is applied to the SOI body (called a body contact), the body potential is constrained by the external potential and the resistance between the external body contact and the SOI body. Note however that in the case of an ultra-thin SOI device with a silicon body that has been scaled to the point where it is fully-depleted, the external resistance can be so high that the body contact is ineffective. 
     An extension of the ultra-thin SOI MOS device described above is the dual-gate SOI MOS transistor. In this structure, the back oxide have been thinned to the point that the region below the back oxide can exert non-negligible electrical field on the body and possibly form for an inversion layer or accumulation layer adjacent to the back oxide. 
     When a second gate electrode is placed in or beneath the back oxide, a dual-gate device SOI MOS transistor is formed. Furthermore the second gate electrode (the back gate) is typically isolated from other electrically conductive elements such as the substrate, source, drain, and top gate (front gate). 
     In conventional MOS process technologies such as SOI or bulk (non-SOI) intentional capacitor circuit elements can be created without significant extra process steps by using a regular MOS transistor that is biased in the inversion or accumulation regime. This gives a relative constant high value capacitor due to the usage of the regular MOS gate oxide. These capacitors can function as decoupling capacitors or as reactive elements in analog applications. However in dual gate ultra-thin SOI the intentional capacitive element formed in this manner can contain parasitic resistance that is dominated by the fully-depleted body in some ranges of operation, reducing it usefulness as a circuit design element. However, traditional and leading-edge circuit design techniques still have a need for intentional capacitive elements, since dual-gate SOI has certain performance advantages over ultra-thin single gate SOI technologies Therefore it is desirable to introduce intentional capacitive circuit elements into dual-gate technologies that are low in parasitic resistance, have high capacitance, and are easy to fabricate. 
     SUMMARY OF THE INVENTION 
     In a first aspect of the invention, a method of manufacturing a dual-gate CMOS structure includes forming a first plate in an insulating layer and forming a second plate above the insulating layer electrically corresponding to the first plate. The method further includes providing an isolation structure between the first plate and the second plate. 
     In another aspect of the invention, the method of manufacturing a dual-gate CMOS structure includes forming at least one back plate in an insulating layer and forming at least one front plate above the insulating layer corresponding to the at least one back plate. The method further includes providing a dielectric between the at least one back plate and the front plate. 
     In yet another aspect of the invention, a capacitor formed on a substrate having a buried insulator layer and a device layer on the insulator layer comprises a lower plate formed in a buried insulator layer. A portion of the buried insulator layer is formed on the lower plate to provide a first capacitor dielectric. A portion of a device layer is formed on the first capacitor dielectric and a second capacitor dielectric is formed on the portion of the device layer. An upper plate is formed on the second capacitor dielectric. 
     In another aspect, the invention includes a dual-gate capacitor having at least one back gate formed in a buried insulator layer and at least one front gate formed above the buried insulator layer. A dielectric layer is formed between the at least one front gate and back gate. Diffusion regions are doped adjacent to the at least one back gate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates steps in manufacturing a device in accordance with the invention; 
         FIG. 2  illustrates additional steps in manufacturing the device in accordance with the invention; 
         FIG. 3  illustrates additional steps in manufacturing the device in accordance with the invention; 
         FIG. 4  illustrates additional steps in manufacturing the device in accordance with the invention; 
         FIG. 5  illustrates additional steps in manufacturing the device in accordance with the invention; 
         FIGS. 6   a - 6   d  show top views or wiring schematics of the different structures of the invention, manufactured in accordance with the steps of the invention; and 
         FIG. 7  shows a side view of the respective structures of  FIGS. 6   a - 6   d.    
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION 
     The invention is directed to CMOS structures and more particularly to low resistance, high value capacitors in scaled dual-gate SOI and a method of manufacture. By using the dual-gate device and method of fabrication of the invention, ultra-thin SOI capacitors with enhanced functionality are achieved. By way of example, in one application series resistance can be lowered for high frequency operations; whereas, in other applications, high capacitance can be achieved per unit area. 
     In accordance with the invention, four distinct CMOS capacitor structures may be manufactured simultaneously, if desired, based on scaled dual-gate SOI technology; namely, the initial structures may be formed with substantially the same processes, with different wiring structures to obtain desired results. In one application, two structures are designed to provide high capacitance directly between front and back gates with negligible reduction in series resistance. In another structure, for example, higher capacitance is provided with reduced series resistance by using both front and back gates electrically tied together, with the active silicon neither inverted or accumulated, thus providing a capacitive element vertically between the two plates and through the fully-depleted channel region. 
       FIG. 1  shows a beginning structure in accordance with the invention. In this structure, an oxide or dielectric layer  100  may be formed on a substrate  102 , using any conventional methods. One such conventional method may include wafer bonding, where another wafer (not shown) with the oxide layer  100  is bonded to the substrate by van der Waals forces. The substrate wafer  102  may be comprised of silicon, germanium, or other readily known materials, and is preferably approximately 500 microns in thickness for purposes of manufacturing processes. A thin layer of silicon  104  is provided on the surface of the oxide layer  100 . The silicon layer  104 , in one embodiment, is approximately 50 Å to 400 Å thick, with other dimensions contemplated by the invention.  FIG. 1  displays all embodiments in close proximity however this is not a requirement for application and one or more embodiments can be placed in arbitrary locations around the chip area. 
     Prior to the bonding the layers  100 ,  102 , one or more back gates  106   a - 106   d  (also known as plates) are formed in the oxide layer. It should be understood that each back gate  106   a - 106   d  may be used to form a similar or different capacitor, depending on the wiring structure desired for a particular application. For example, in the embodiment shown in  FIG. 1 , the four back gates  106   a - 106   d  form structures in regions, a-d, respectively. Additionally, more or less than four back gates may also be formed, again depending on the desired application. Accordingly, it should be understood that the discussion of back gates  106   a - 106   d  are exemplary and should not be considered a limiting feature of the invention. 
     In forming the back gates  106   a - 106   d , process steps including conventional standard lithographic and etching processes may be utilized, all known to those of skill in the art. For example, the process may include block masks used in combination with Reactive Ion Etching (RIE), in certain applications. In implementation, the back gates  106   a - 106   d  may be polysilicon and conventionally doped, for example, using phosphorous, boron or arsenic. Also, in embodiments, the cross-section of the back gates  106   a - 106   d  are of such dimensions so as to minimize any significant gate resistance. For example, the height of the back gates  106   a - 106   d  may be approximately 1000 Å to 2000 Å, although other critical dimensions are also contemplated by the invention. A space of approximately 10 Å to 100 Å is provided between the top surface of the oxide layer  100  and the back gates  106   a - 106   d . This distance demarcates a region that can be referred to as the back gate oxide or dielectric layer, which can be sized to minimize any potential parasitic effects such as direct tunneling currents. 
       FIG. 2  represents further processing steps in accordance with the invention. In  FIG. 2 , the silicon layer  104  is etched away, using conventional processes. For example,  FIG. 2  is illustrative of an active area mask that is used to define each isolated capacitor element, which may include channel, drain, and source regions. In one application, the active area mask is placed over regions represented as “a”, “b” and “c”. The structure is then etched in a silicon isolation process, resulting in silicon bodies or islands  104   a ,  104   b  and  104   c . The silicon layer  104  may be completely etched in the region “d”. 
     Gate oxide or dielectric layers  108   a ,  108   b ,  108   c  are then thermally grown or deposited on the silicon bodies  104   a ,  104   b , and  104   c , respectively. In one embodiment, the gate oxide layers  108   a ,  108   b ,  108   c  are formed to a thickness of approximately 10 Å to 100 Å, similar to the spacing of the oxide layer  100  between the back gates  106   a - 106   d  and the silicon layer  104 . This oxide layer may be used to form the actual capacitor(s) of the invention. 
       FIG. 3  is representative of a gate material  110  (e.g., polysilicon) being deposited on the structure of  FIG. 2 . This material  110  is used to form the front gates, using subsequent steps described below. The gate material  110  may be heavily doped (e.g., 10 20  cm. −3 ) however not necessarily the same dopant species as was used with the back gates  106   a - 106   b . High dopant levels of species such as phosphorous, boron or arsenic are used to minimize polysilicon depletion effects. The considerations for the dimensions of the polysilicon material  110  are also substantially the same as that of the back gates  106   a - 106   c . For example, the cross section of the poly material  110  is of such dimensions so as to minimize any significant gate resistance, e.g., approximately 1000 Å to 2000 Å, although other critical dimensions are also contemplated by the invention. 
       FIG. 4  is illustrative of an exemplary patterning and etching process in order to form the front gates  110   a - 110   d . In one process, the formation of the front gate  110   d  of section “d” may be formed separately from that of the remaining front gates  110   a - 110   c . This is due to the front gate  110   d  being etched more deeply since the silicon layer  104  and subsequent oxide layer is not provided over this region. In one example, a protecting mask may be placed over region “d” during the processes forming the front gates  110   a - 110   c . Likewise, a protecting mask may be placed over regions “a”, “b” and “c”, during the formation of the front gate  110   d . These processes are well known in the art to those of skill such that further discussion is not required herein for a complete understanding of the invention. 
       FIG. 5  illustrates several processing steps including the formation of spacers, source and drain regions and silicide. In the illustration of  FIG. 5 , only the CMOS structure for region “a” is shown; however, it should be understood that the processes discussed with reference to section “a” are equally applicable for the formation of the structures in regions “b”, “c” and “d”. Accordingly, the exemplary illustration of  FIG. 5  can be used for the formation of the source, drain, sidewalls and silicide formations on any of the structures shown in  FIGS. 6   a - 7 . 
     By way of example, referring to region “a”, the source and drain regions  112   1  and  112   2 , are formed in the silicon body in any conventional manner. An isolation region  105  is adjacent the source and drain regions  112   1  and  112   2 . Spacers  114  are formed on the sidewalls of the front gate  110   a  and the front oxide layer  108   a , extending to the doped source and drain regions  112   1  and  112   2 , respectively. These regions can be doped using phosphorous, boron or arsenic, preferably resulting in the range of 1×10 20  particles/cm 3  for the source and drain, but typically lower levels for other doped regions such as halo or extension implants that may be part of the conventional transistor process into which the dual-gate MOS capacitor is being included. A silicide layer  116  is formed on the exposed silicon layer at the doped source and drain regions  112   1  and  112   2 , respectively, in addition to a top surface of the front gate  110   a . The formation of the silicide and spacers are well known in the art by those of skill in the art. 
       FIGS. 6   a - 6   d  show top views of wiring schematics of the different structures “a” through “d” described with reference to  FIGS. 1-5 . In  FIG. 6   a , a dual-gate FET capacitor is shown, corresponding to the manufacturing processes described for section “a”. In the FET capacitor of  FIG. 6   a , a first wire “A” contacts the front gate  110   a  and forms a first terminal of the capacitor. A second wire “B” contacts the back gate  106   a , in addition to both opposing sides of the silicon layer, and forms the second terminal of the capacitor. Thus, in this structure, the capacitor is formed from the “A” electrode, through the structure to the “B” electrode, which results in the source and drain shorted together. Alternatively, the roles of the back gate and the front gate can be reversed, with the “B” electrode consisting of the back gate and the “A” terminal consisting to the diffusion regions tied to the front gate. 
       FIG. 6   b  is a dual-gate capacitor using the structure formed in region “b” of  FIGS. 1-5 , with the wiring schematic shown herein. In the high-density capacitor of  FIG. 6   b , a first wire “A” contacts both sides of the silicon layer diffusion regions and forms a first terminal of the capacitor. A second wire “B” contacts the front gate  110   b  and the back gate  106   b  and forms the second terminal of the capacitor. Thus, in this structure, the wire “A” ties together the two sides of the silicon, while the wire “B” ties together the front gate  110   b  and the back gate  106   b . The device of  FIG. 6   b  provides increased capacitance as the device of  FIG. 6   a  due to the front and back channel charge regions functioning electrically together. 
     In the capacitor structure of  FIGS. 6   a  and  6   b , high capacitance is possible because of the thin dielectric layer (a process step that is potentially shared with the conventional MOS transistor process that includes these dual-gate capacitors) directly between the front and back gates  106   a  and  110   a , respectively. Also, since the outer edges (diffusions) of the silicon are connected together by wire “B”, the top portion of the structure looks similar to a conventional MOSFET. And, in this case, an inversion layer can be formed beneath the top oxide layer  108   a . That is, the dual-gate structure also allows both devices to have an inversion channel forms under the oxide layer  108   a.    
     Also, accumulation or diffusion effects can occur since the front gate is formed over the silicon and there are two diffusions wired out at an electrically different potential from the front gate. Thus, as should be understood by this wiring schematic, if the potential of the “B” wire goes above the front or back gate threshold voltage with respect to the diffusion, an inversion layer will form; whereas, if the potential of the wire “B” has low enough bias with respect to the diffusion potential, an accumulation layer will occur under one or both of the capacitor oxides. It is recognized that opposite biasing results occur in p-type and n-type devices. 
       FIG. 6   c  is a dual-gate capacitor using the structure formed in region “c” of  FIGS. 1-5 , with the wiring schematic shown herein. In the wiring structure of  FIG. 6   c , a first wire “A” contacts the front gate  110   c  and forms a first terminal of the capacitor. A second wire “B” contacts the back gate  106   c  and forms the second terminal of the capacitor. A high potential (for example Vdd) contacts both sides (diffusions) of the silicon layer. From an electrical standpoint, the thin-body structure of  FIG. 6   c  is fully-depleted and has field lines substantially penetrating the structure from “A” to “B”, e.g., the front gate  110   c  to the back gate  106   c . The dual-gate capacitor of  FIG. 6   c  offers low series resistance for high-frequency operation (similar to that of  FIG. 6   d ). 
     In the device of  FIG. 6   c , an inversion layer cannot form because the potential on the gate does not exceed the potential of the diffusion. An inversion layer may form when the gate potential, relative to one of the outside diffusion potentials, is above a MOS FET threshold and there is a source of carriers around, which is the source and drain. But, this is not desirable due to resistance issues. This phenomenon is eliminated in the device of  FIG. 6   c  since the potential on the diffusions is high and the potentials on “A” and “B” are operated below that potential. Also, an accumulation can occur if the gate terminal goes too low; however, the assumption is that the device of  FIG. 6   c  is operated so that this does not occur since there is roughly 1.2 volts (or the bandgap potential) between the high diffusion potential and the bias where accumulation would occur. 
       FIG. 6   d  is a gate capacitor using the structure formed in region “c” of  FIGS. 1-5 , with the wiring schematic shown herein. In the capacitor of  FIG. 6   d , a first wire “A” contacts the front gate  110   d  and forms a first terminal of the capacitor. A second wire “B” contacts the back gate  106   d  and forms the second terminal of the capacitor. The device of  FIG. 6   d  offers low series resistance for high-frequency operations and high capacitance per unit area based on scaling of the back oxide thickness. 
       FIG. 7  shows a side view of the respective structures of  FIGS. 6   a - 6   d . The first wire “A” and the second wire “B” are representative of the respective terminals of the devices shown in  FIGS. 6   a - 6   d .  FIG. 7  also clearly illustrates the regions “a”, “b”, “c” and “d” representative of the devices shown and described in  FIGS. 6   a - 6   d , respectively. In this illustration, two dielectric or oxide layers separate the front gates  110   a - 110   c  and the back gates  106   a - 106   c . A contribution to parasitic resistance, direct tunneling through either the front or back gate is controlled by selecting the appropriate oxide thickness such that leakage current is minimized. 
     While the invention has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.