Patent Publication Number: US-2023147567-A1

Title: Display device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of priority from Japanese Patent Application No. 2021-182121 filed on Nov. 8, 2021, the entire contents of which are incorporated herein by reference. 
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a display device. 
     2. Description of the Related Art 
     Recent years have seen a growing demand for display devices for use in mobile electronic apparatuses, such as mobile phones and electronic paper displays. For example, in electrophoretic displays (EPDs) used in the electronic paper displays, a pixel has a memory property to hold a potential at the time of rewriting, and holds the potential at the time of the rewriting until the rewriting is performed for the next frame after the rewriting is performed once for each frame. As a result, the EPDs can perform low power consumption driving. For example, a technology is disclosed to achieve the low power consumption by configuring a pixel transistor to have a complementary metal-oxide semiconductor (CMOS) configuration obtained by combining a p-channel transistor with an n-channel transistor (for example, Japanese Patent Application Laid-open Publication No. 2019-086544). 
     In a configuration where the potential of a holding capacitor is rewritten by turning on the pixel transistor and the potential is held by turning off the pixel transistor, the potential varies due to feedthrough or leakage of the holding capacitor that occurs when the pixel transistor is turned off, which may lead to reduction in display quality. 
     It is an object of the present disclosure to provide a display device capable of restraining the reduction in display quality caused by the potential variation. 
     SUMMARY 
     A display device according to an embodiment of the present disclosure has a write period of charging a holding capacitor included in each of pixels arranged in a first direction and a second direction different from the first direction in a display region, and has a hold period of holding capacitance of the holding capacitor charged during the write period. The display device comprises a potential maintenance circuit configured to maintain, during the hold period, one of three potential values of a positive-polarity potential, a ground (GND) potential, and a negative-polarity potential having charged the holding capacitor during the write period. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a sectional view illustrating a configuration example of a display device according to an embodiment of the present disclosure; 
         FIG.  2    is a block diagram illustrating a configuration example of the display device according to a comparative example; 
         FIG.  3    is a circuit diagram illustrating a configuration example of one pixel of the display device according to the comparative example; 
         FIG.  4 A  is a timing diagram for explaining an operation in the comparative example; 
         FIG.  4 B  is a timing diagram for explaining another operation in the comparative example; 
         FIG.  4 C  is a timing diagram for explaining still another operation in the comparative example; 
         FIG.  5    is a block diagram illustrating a configuration example of a display device according to a first embodiment of the present disclosure; 
         FIG.  6    is a diagram illustrating an exemplary configuration of one pixel and an exemplary internal configuration of a source driver in the display device according to the first embodiment; 
         FIG.  7    is a block diagram illustrating an exemplary circuit configuration of a source drive signal converter; 
         FIG.  8 A  is a conceptual diagram illustrating a specific example of an operation of the source drive signal converter; 
         FIG.  8 B  is a conceptual diagram illustrating another specific example of the operation of the source drive signal converter; 
         FIG.  8 C  is a conceptual diagram illustrating still another specific example of the operation of the source drive signal converter; 
         FIG.  9 A  is a timing diagram for explaining an operation in the first embodiment; 
         FIG.  9 B  is a timing diagram for explaining another operation in the first embodiment; 
         FIG.  9 C  is a timing diagram for explaining still another operation in the first embodiment; 
         FIG.  9 D  is a timing diagram for explaining still another operation in the first embodiment; 
         FIG.  9 E  is a timing diagram for explaining still another operation in the first embodiment; 
         FIG.  9 F  is a timing diagram for explaining still another operation in the first embodiment; 
         FIG.  10 A  is a conceptual diagram illustrating a specific example of an operation of a potential maintenance circuit according to the first embodiment; 
         FIG.  10 B  is a conceptual diagram illustrating another specific example of the operation of the potential maintenance circuit in the first embodiment; 
         FIG.  10 C  is a conceptual diagram illustrating still another specific example of the operation of the potential maintenance circuit according to the first embodiment; 
         FIG.  10 D  is a conceptual diagram illustrating still another specific example of the operation of the potential maintenance circuit according to the first embodiment; 
         FIG.  10 E  is a conceptual diagram illustrating still another specific example of the operation of the potential maintenance circuit in the first embodiment; 
         FIG.  10 F  is a conceptual diagram illustrating still another specific example of the operation of the potential maintenance circuit according to the first embodiment; 
         FIG.  11    is a block diagram illustrating a configuration example of a display device according to a second embodiment of the present disclosure; 
         FIG.  12    is a diagram illustrating an exemplary configuration of one pixel of the display device according to the second embodiment; 
         FIG.  13 A  is a timing diagram for explaining an operation in the second embodiment; 
         FIG.  13 B  is a timing diagram for explaining another operation in the second embodiment; 
         FIG.  13 C  is a timing diagram for explaining still another operation in the second embodiment; 
         FIG.  13 D  is a timing diagram for explaining still another operation in the second embodiment; 
         FIG.  13 E  is a timing diagram for explaining still another operation in the second embodiment; 
         FIG.  13 F  is a timing diagram for explaining still another operation in the second embodiment; 
         FIG.  14 A  is a conceptual diagram illustrating a specific example of an operation of a potential maintenance circuit according to the second embodiment; 
         FIG.  14 B  is a conceptual diagram illustrating another specific example of the operation of the potential maintenance circuit according to the second embodiment; 
         FIG.  14 C  is a conceptual diagram illustrating still another specific example of the operation of the potential maintenance circuit according to the second embodiment; 
         FIG.  15    is a block diagram illustrating a configuration example of a display device according to a third embodiment of the present disclosure; 
         FIG.  16    is a diagram illustrating an exemplary configuration of one pixel of the display device according to the third embodiment; 
         FIG.  17 A  is a timing diagram for explaining an operation in the third embodiment; 
         FIG.  17 B  is a timing diagram for explaining another operation in the third embodiment; 
         FIG.  17 C  is a timing diagram for explaining still another operation in the third embodiment; 
         FIG.  17 D  is a timing diagram for explaining still another operation in the third embodiment; 
         FIG.  17 E  is a timing diagram for explaining still another operation in the third embodiment; 
         FIG.  17 F  is a timing diagram for explaining still another operation in the third embodiment; 
         FIG.  18 A  is a conceptual diagram illustrating a specific example of an operation of a potential maintenance circuit according to the third embodiment; 
         FIG.  18 B  is a conceptual diagram illustrating another specific example of the operation of the potential maintenance circuit according to the third embodiment; 
         FIG.  18 C  is a conceptual diagram illustrating still another specific example of the operation of the potential maintenance circuit according to the third embodiment; 
         FIG.  19    is a block diagram illustrating a configuration example of a display device according to a fourth embodiment of the present disclosure; 
         FIG.  20    is a diagram illustrating an exemplary configuration of one pixel of the display device according to the fourth embodiment; 
         FIG.  21 A  is a timing diagram for explaining an operation in the fourth embodiment; 
         FIG.  21 B  is a timing diagram for explaining another operation in the fourth embodiment; and 
         FIG.  21 C  is a timing diagram for explaining another operation in the fourth embodiment; 
         FIG.  21 D  is a timing diagram for explaining still another operation in the fourth embodiment; 
         FIG.  21 E  is a timing diagram for explaining still another operation in the fourth embodiment; 
         FIG.  21 F  is a timing diagram for explaining still another operation in the fourth embodiment; 
         FIG.  22 A  is a conceptual diagram illustrating a specific example of an operation of a potential maintenance circuit according to the fourth embodiment; 
         FIG.  22 B  is a conceptual diagram illustrating another specific example of the operation of the potential maintenance circuit according to the fourth embodiment; 
         FIG.  22 C  is a conceptual diagram illustrating still another specific example of the operation of the potential maintenance circuit according to the fourth embodiment; and 
         FIG.  22 D  is a conceptual diagram illustrating still another specific example of the operation of the potential maintenance circuit according to the fourth embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The following describes modes (embodiments) for carrying out the present disclosure in detail with reference to the drawings. The present disclosure is not limited to the description of the embodiments given below. Components described below include those easily conceivable by those skilled in the art or those substantially identical thereto. Moreover, the components described below can be combined as appropriate. What is disclosed herein is merely an example, and the present disclosure naturally encompasses appropriate modifications easily conceivable by those skilled in the art while maintaining the gist of the present disclosure. To further clarify the description, the drawings may schematically illustrate, for example, widths, thicknesses, and shapes of various parts as compared with actual aspects thereof. However, they are merely examples, and interpretation of the present disclosure is not limited thereto. The same component as that described with reference to an already mentioned drawing is denoted by the same reference numeral through the present specification and the drawings, and detailed description thereof may not be repeated where appropriate. 
     First, a structure of a display device  10  according to an embodiment will be described.  FIG.  1    is a sectional view illustrating a configuration example of the display device according to the embodiment. 
     In the example illustrated in  FIG.  1   , the display device  10  is, for example, an electrophoretic device (electrophoretic display (EPD)) provided with an electrophoretic display panel having an electrophoretic layer. As illustrated in  FIG.  1   , the display device  10  according to the embodiment includes a thin-film transistor (TFT) substrate  100 , a counter substrate  130  disposed so as to face the TFT substrate  100 , an electrophoretic layer (functional layer)  160  disposed between the TFT substrate  100  and the counter substrate  130 , and a sealing part  152 . 
     The TFT substrate  100  is provided with pixel electrodes Pix and holding electrodes Base. In a comparative example described later, the holding electrodes Base are supplied with a common potential VCOM. 
     The counter substrate  130  includes a base material  131  and a counter electrode  133 . The base material  131  is a light-transmitting glass substrate, a light-transmitting resin substrate, or a light-transmitting resin film. The counter electrode  133  is provided on a surface side of the base material  131  facing the TFT substrate  100 . The counter electrode  133  is formed of indium tin oxide (ITO) serving as a light-transmitting conductive film. The counter electrode  133  faces the pixel electrodes Pix with the electrophoretic layer  160  interposed therebetween. The counter electrode  133  is supplied with the common potential VCOM. 
     The sealing part  152  is provided between the TFT substrate  100  and the counter substrate  130 . The electrophoretic layer  160  is sealed in an internal space surrounded by the TFT substrate  100 , the counter substrate  130 , and the sealing part  152 . 
     The electrophoretic layer  160  includes a plurality of microcapsules  163 . Each of the microcapsules  163  encapsulates a plurality of black particles  161 , a plurality of white particles  162 , and a dispersion liquid  165 . The black particles  161  and the white particles  162  are dispersed in the dispersion liquid  165 . The dispersion liquid  165  is a light-transmitting liquid, such as silicone oil. The black particles  161  are electrophoretic particles made using, for example, negatively charged graphite. The white particles  162  are electrophoretic particles made using, for example, positively charged titanium dioxide (TiO 2 ). 
     An electric field generated between each of the pixel electrodes Pix and the counter electrode  133  changes the dispersion state of the black particles  161  and the white particles  162 . The state of light transmission through the electrophoretic layer  160  changes according to the dispersion state of the black and the white particles  161  and  162 . Thus, an image is displayed on a display surface. For example, when the common potential VCOM (at, for example, a ground (GND) potential) is supplied to the counter electrode  133  and a negative potential is supplied to the pixel electrode Pix, the negatively charged black particles  161  move toward the counter substrate  130 , and the positively charged white particles  162  move toward the TFT substrate  100 . As a result, when the TFT substrate  100  is viewed from the counter substrate  130  side, an area (pixels) overlapping the pixel electrodes Pix in a plan view is displayed in black. 
     The display device  10  may be a monochrome display device, or may be a color display device using, for example, color filters in a plurality of colors. The display device  10  may employ a light-reflecting material as the pixel electrodes of pixels PX, or may have a configuration in which light-transmitting pixel electrodes are combined with a reflective film of, for example, a metal, and the reflective film reflects light. The display device  10  may be a flexible display such as a sheet display. In the present embodiment, the electrophoretic device (electrophoretic display (EPD)) provided with the electrophoretic display panel having the electrophoretic layer has been exemplified as the display device  10 . However, the present disclosure is also applicable to a case where the display device  10  is, for example, a liquid crystal display device (liquid crystal display) provided with a liquid crystal display panel having a liquid crystal layer. 
     Before describing a configuration of the display device  10  according to the embodiment, a configuration of the display device according to a comparative example will be described.  FIG.  2    is a block diagram illustrating a configuration example of the display device according to the comparative example. 
     The display device  10  is mounted on, for example, an electronic apparatus (not illustrated). The display device  10  receives various power supply voltages applied from, for example, a power supply circuit  200  of the electronic apparatus and displays images based on signals output from, for example, a control circuit  300  serving as a host processor of the electronic apparatus. Examples of the electronic apparatus on which the display device  10  is mounted include electronic paper display devices. 
     As illustrated in  FIG.  2   , the display device  10  is provided with a display region  11  and a display panel driver  20  on the TFT substrate  100 . In the display region  11 , the pixels PX are arranged in a two-dimensional matrix having a row-column configuration in a first direction (X-direction in  FIG.  2   ) and a second direction (Y-direction in  FIG.  2   ) orthogonal to the first direction. Hereafter, the first direction (X-direction in  FIG.  2   ) is also called a row direction, and the second direction (Y-direction in  FIG.  2   ) is also called a column direction. A row in which the pixels PX are arranged in the row direction is also called a pixel row, and a column in which the pixels PX are arranged in the column direction is also called a pixel column.  FIG.  1    illustrates an example in which N×M (N in the row direction and M in the column direction) of the pixels PX are arranged in a matrix. 
     The power supply circuit  200  is a power source generator that generates the various power supply voltages to be supplied to components of the display device  10  according to the present embodiment. The power supply circuit  200  is coupled to the display panel driver  20 . The various power supply voltages are supplied from the power supply circuit  200  to the display panel driver  20 . 
     The control circuit  300  is an arithmetic processor that controls operations of the display device  10  according to the present embodiment. The control circuit  300  is coupled to the display panel driver  20 . The control circuit  300  is constituted by a control integrated circuit (IC), for example. A video signal and various control signals are supplied from the control IC to the display panel driver  20 . 
     The display panel driver  20  includes a source driver  21  and a gate driver  22 . 
     The display panel driver  20  causes the source driver  21  to hold the video signal. The source driver  21  is electrically coupled to each of the pixels PX arranged in the Y-direction in the display region  11  through a source bus line (signal line) DTL(n) (where n is an integer from  1  to N), and transmits a source drive signal (pixel signal) SIG(n) to the source bus line (signal line) DTL(n) (refer to  FIG.  3   ). The source drive signal (pixel signal) SIG(n) is supplied to each of the pixels PX arranged in the Y-direction. 
     The display panel driver  20  causes the gate driver  22  to sequentially select the pixels PX arranged in the Y-direction in the display region  11 . Hereinafter, a period in one frame period in which the gate driver  22  selects the pixels PX arranged in the X-direction in the display region  11  is also called “write period (Write)”. In addition, a period except the write period in one frame period in which the gate driver  22  selects the pixels PX arranged in the X-direction in the display region  11  is also called “hold period (Hold)”. 
     The gate driver  22  is electrically coupled to each of the pixels PX arranged in the X-direction (first direction) in the display region  11  through a gate bus line (scan line) SCL(m) (where m is an integer from  1  to M), and sequentially selects each of the gate bus lines (scan lines) SCL(m) arranged in the Y-direction (second direction) to transmit thereto a gate drive signal (scan signal) Gate(m) (refer to  FIG.  3   ). The gate drive signal (scan signal) Gate(m) is supplied to each of the pixels PX coupled to the selected gate drive signal (scan signal) Gate(m). 
     The source driver  21  and the gate driver  22  may be provided on the TFT substrate  100  or on the counter substrate  130  (refer to  FIG.  1   ). The source driver  21  and the gate driver  22  may be mounted on a display IC mounted on another circuit board (such as a flexible substrate) coupled to the TFT substrate  100 . 
       FIG.  3    is a circuit diagram illustrating a configuration example of one pixel of the display device according to the comparative example. 
     As illustrated in  FIG.  3   , in the display device  10  according to the comparative example, each of the pixels PX of the TFT substrate  100  includes a pixel transistor TR. In the display device  10  according to the comparative example, the pixel transistor TR is an n-channel metal oxide semiconductor (NMOS) transistor. The gate of the pixel transistor TR is coupled to the gate bus line (scan line) SCL(m). The source of the pixel transistor TR is coupled to the source bus line (signal line) DTL(n). The drain of the pixel transistor TR is provided with the pixel electrode Pix. 
     Each of the pixels PX of the TFT substrate  100  includes a first holding capacitor C 1  and a second holding capacitor C 2 . The first holding capacitor C 1  is a capacitor generated between the pixel electrode Pix and each of the holding electrodes Base (refer to  FIG.  1   ). The second holding capacitor C 2  is a capacitor generated between the counter electrode  133  of the counter substrate  130  (refer to  FIG.  1   ) and the pixel electrode Pix. The first holding capacitor C 1  has capacitance of approximately 1 pF, for example. The second holding capacitor C 2  has capacitance of, for example, approximately 1/10 that of the first holding capacitor C 1 . 
     The pixel electrode Pix is supplied with the source drive signal (pixel signal) from the source bus line (signal line) DTL(n) through the pixel transistor TR. In the display device  10  according to the comparative example, the holding electrodes Base and the counter electrode  133  are supplied with the common potential VCOM. The potential of the source drive signal (pixel signal) supplied to the pixel electrode Pix is held by the first holding capacitor C 1  and the second holding capacitor C 2 . 
       FIGS.  4 A,  4 B, and  4 C  are timing diagrams for explaining operations in the comparative example. 
     As illustrated in  FIGS.  4 A,  4 B, and  4 C , the gate driver  22  supplies a positive-polarity gate potential VGH to the gate bus line (scan line) SCL(m) during the write period of each of the pixels PX in the mth row. The gate driver  22  supplies a negative-polarity gate potential VGL to the gate bus line (scan line) SCL(m) during the hold period except the write period. 
     As illustrated in  FIG.  4 A , when the source bus line (signal line) DTL(n) is supplied with a positive-polarity source potential VSH that is a lower potential than the positive-polarity gate potential VGH, that is, when the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH, supplying the positive-polarity gate potential VGH to the gate bus line (scan line) SCL(m) during the write period of the pixels PX in the mth row controls to turn on the pixel transistor TR of the pixel PX in the mth row (refer to  FIG.  3   ) to apply the positive-polarity source potential VSH as a potential Vpix(m, n) of the pixel electrode Pix of the pixel PX in the mth row and the nth column. During the hold period following the write period, the potential Vpix(m, n) of the pixel electrode Pix of the pixel PX in the mth row and the nth column is held at the positive-polarity source potential VSH by the first holding capacitor C 1  and the second holding capacitor C 2 . 
     As illustrated in  FIG.  4 B , when the source bus line (signal line) DTL(n) is supplied with the GND potential, that is, when the source drive signal (pixel signal) SIG(n) is set to the GND potential, supplying the GND potential to the gate bus line (scan line) SCL(m) during the write period of the pixels PX in the mth row controls to turn on the pixel transistor TR of the pixel PX in the mth row (refer to  FIG.  3   ) to apply the GND potential as the potential Vpix(m, n) of the pixel electrode Pix of the pixel PX in the mth row and the nth column. During the hold period following the write period, the potential Vpix(m, n) of the pixel electrode Pix of the pixel PX in the mth row and the nth column is held at the GND potential by the first holding capacitor C 1  and the second holding capacitor C 2 . 
     As illustrated in  FIG.  4 C , when the source bus line (signal line) DTL(n) is supplied with a negative-polarity source potential VSL that is a higher potential than the negative-polarity gate potential VGL, that is, when the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL, supplying the negative-polarity gate potential VGL to the gate bus line (scan line) SCL(m) during the write period of the pixels PX in the mth row controls to turn on the pixel transistor TR of the pixel PX in the mth row (refer to  FIG.  3   ) to apply the negative-polarity source potential VSL as the potential Vpix(m, n) of the pixel electrode Pix of the pixel PX in the mth row and the nth column. During the hold period following the write period, the potential Vpix(m, n) of the pixel electrode Pix of the pixel PX in the mth row and the nth column is held at the negative-polarity source potential VSL by the first holding capacitor C 1  and the second holding capacitor C 2 . 
     Specifically, in the pixel configuration illustrated in  FIG.  3   , the positive-polarity source potential VSH is set to +15 V, for example, and the negative-polarity source potential VSL is set to −15 V, for example. In order to control to turn on the pixel transistor TR (refer to  FIG.  3   ) during the write period, the positive-polarity gate potential VGH is set to, for example, +20 V that is a higher potential than the positive-polarity source potential VSH, and the negative-polarity gate potential VGL is set to, for example,−20 V that is a lower potential than the negative-polarity source potential VSL. 
     In the configuration of the comparative example described above, the potential Vpix(m, n) of the pixel electrode Pix is rewritten by controlling to turn on the pixel transistor TR in the write period, and the pixel transistor TR is controlled to be turned off in the hold period to cause the first holding capacitor C 1  and the second holding capacitor C 2  to hold the potential Vpix(m, n) of the pixel electrode Pix. However, with such a configuration, due to feedthrough or leakage of the first holding capacitor C 1  and the second holding capacitor C 2  that occurs when the pixel transistor TR is turned off, the potential Vpix(m, n) of the pixel electrode Pix may vary to cause reduction in display quality. 
     In the present disclosure, a potential maintenance circuit is provided to statically maintain, during the hold period, one of the three potential values of the positive-polarity source potential VSH, the GND potential, and the negative-polarity source potential VSL having charged the holding capacitors during the write period. This configuration reduces the potential variation of the potential Vpix(m, n) of the pixel electrode Pix to restrain the reduction in display quality associated with the potential variation of the potential Vpix(m, n) of the pixel electrode Pix. The following describes in detail a configuration including the potential maintenance circuit according to the embodiment. 
     First Embodiment 
       FIG.  5    is a block diagram illustrating a configuration example of a display device according to a first embodiment of the present disclosure.  FIG.  6    is a diagram illustrating an exemplary configuration of one pixel and an exemplary internal configuration of a source driver in the display device according to the first embodiment. 
     As illustrated in  FIG.  6   , in a display device  10   a  according to the first embodiment, a source driver  21   a  of a display panel driver  20   a  includes a source drive signal generator  211  and a source drive signal converter  212 . The source drive signal generator  211  and the source drive signal converter  212  are provided for each of the pixel columns. The source drive signal generator  211  is mounted on the display IC, for example. The source drive signal converter  212  is, for example, a thin-film transistor (TFT) circuit formed in a frame region  12  on the TFT substrate  100 . 
     According to the video signal supplied from the control circuit  300 , the source drive signal generator  211  generates a signal SIG(n) that can take the three values of the positive-polarity source potential VSH, the GND potential, and the negative-polarity source potential VSL. In the present embodiment, the positive-polarity source potential VSH is set to +15 V, for example. In the present embodiment, the negative-polarity source potential VSL is set to −15 V, for example. 
     The source drive signal converter  212  supplies a first source drive signal (first pixel signal) SIG 1 ( n ) obtained by converting the three-valued source drive signal (pixel signal) SIG(n) output from the source drive signal generator  211  to a first source bus line (first signal line) DTL 1 ( n ). The source drive signal converter  212  supplies a second source drive signal (second pixel signal) SIG 2 ( n ) obtained by converting the three-valued source drive signal SIG(n) output from the source drive signal generator  211  to a second source bus line (second signal line) DTL 2 ( n ). The following describes operations of the source drive signal converter  212  with reference to  FIGS.  7 ,  8 A,  8 B, and  8 C . 
       FIG.  7    is a block diagram illustrating an exemplary circuit configuration of the source drive signal converter.  FIGS.  8 A,  8 B, and  8 C  are conceptual diagrams illustrating specific examples of the operations of the source drive signal converter. 
     As illustrated in  FIG.  8 A , when the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH, the source drive signal converter  212  controls to turn off each of the transistors illustrated with dashed lines to output the GND potential as the first source drive signal SIG 1 ( n ) to the first source bus line DTL 1 ( n ) through a path indicated by a solid arrow, and output the negative-polarity source potential VSL as the second source drive signal SIG 2 ( n ) to the second source bus line DTL 2 ( n ) through a path indicated by a dashed arrow. 
     As illustrated in  FIG.  8 B , when the source drive signal (pixel signal) SIG(n) is set to the GND potential, the source drive signal converter  212  controls to turn off each of the transistors illustrated with dashed lines to output the GND potential as the first source drive signal SIG 1 ( n ) to the first source bus line DTL 1 ( n ) through a path indicated by a solid arrow, and output the negative-polarity source potential VSL as the second source drive signal SIG 2 ( n ) to the second source bus line DTL 2 ( n ) through a path indicated by a dashed arrow. 
     As illustrated in  FIG.  8 C , when the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL, the source drive signal converter  212  controls to turn off each of the transistors illustrated with dashed lines to output the positive-polarity source potential VSH as the first source drive signal SIG 1 ( n ) to the first source bus line DTL 1 ( n ) through a path indicated by a solid arrow, and output the GND potential as the second source drive signal SIG 2 ( n ) to the second source bus line DTL 2 ( n ) through a path indicated by a dashed arrow. 
     The configurations and the operations of the source drive signal converter  212  illustrated in  FIGS.  7 ,  8 A,  8 B , and  8 C are merely examples, and are not limited to the examples illustrated in  FIGS.  7 ,  8 A,  8 B, and  8 C . 
     In the display device  10   a  according to the first embodiment, a gate driver  22   a  is electrically coupled to the pixels PX arranged in the X-direction in the display region  11  through a first gate bus line (first scan line) SCL 1 ( m ), and transmits a first gate drive signal (first scan signal) Gate 1 ( m ) to the first gate bus line (first scan line) SCL 1 ( m ). The gate driver  22   a  supplies a first positive-polarity gate potential VGH 1  to the first gate bus line (first scan line) SCL 1 ( m ) during the write period. The gate driver  22   a  supplies a first negative-polarity gate potential VGL 1  to the first gate bus line (first scan line) SCL 1 ( m ) during the hold period. In the present embodiment, the first positive-polarity gate potential VGH 1  is set to +20 V, for example. In the present embodiment, the first negative-polarity gate potential VGL 1  is set to −5 V, for example. 
     The gate driver  22   a  is also electrically coupled to the pixels PX arranged in the X-direction in the display region  11  through a second gate bus line (second scan line) SCL 2 ( m ), and transmits a second gate drive signal (second scan signal) Gate 2 ( m ) to the second gate bus line (second scan line) SCL 2 ( m ). The gate driver  22   a  supplies a second positive-polarity gate potential VGH 2  to the second gate bus line (second scan line) SCL 2 ( m ) during the write period. The gate driver  22   a  supplies a second negative-polarity gate potential VGL 2  to the second gate bus line (second scan line) SCL 2 ( m ) during the hold period. In the present embodiment, the second positive-polarity gate potential VGH 2  is set to +5 V, for example. In the present embodiment, the second negative-polarity gate potential VGL 2  is set to −20 V, for example. 
     As illustrated in  FIG.  6   , a potential maintenance circuit  30  according to the first embodiment includes a high-potential-side first pixel transistor TR 1   a , a high-potential-side second pixel transistor TR 2   a , a high-potential-side third pixel transistor TR 3   a , a low-potential-side first pixel transistor TR 1   b , a low-potential-side second pixel transistor TR 2   b , and a low-potential-side third pixel transistor TR 3   b.    
     In the present embodiment, the high-potential-side first pixel transistor TR 1   a  and the low-potential-side first pixel transistor TR 1   b  are each an NMOS transistor corresponding to the pixel transistor TR in the comparative example described above. In the present embodiment, a high-potential-side first holding capacitor C 1   a  is coupled to the first source bus line (first signal line) DTL 1 ( n ) through the high-potential-side first pixel transistor TR 1   a . In the present embodiment, a low-potential-side first holding capacitor C 1   b  is coupled to the second source bus line (second signal line) DTL 2 ( n ) through the low-potential-side first pixel transistor TR 1   b.    
     The gate of the high-potential-side first pixel transistor TR 1   a  is coupled to the first gate bus line (first scan line) SCL 1 ( m ). With this configuration, when the first gate drive signal (first scan signal) Gate 1 ( m ) supplied to the first gate bus line (first scan line) SCL 1 ( m ) is set to the first positive-polarity gate potential VGH 1 , the high-potential-side first holding capacitor C 1   a  is coupled to the first source bus line (first signal line) DTL 1 ( n ) through the high-potential-side first pixel transistor TR 1   a.    
     The gate of the low-potential-side first pixel transistor TR 1   b  is coupled to the second gate bus line (second scan line) SCL 2 ( m ). With this configuration, when the second gate drive signal (second scan signal) Gate 2 ( m ) supplied to the second gate bus line (second scan line) SCL 2 ( m ) is set to the second positive-polarity gate potential VGH 2 , the low-potential-side first holding capacitor C 1   b  is coupled to the second source bus line (second signal line) DTL 2 ( n ) through the low-potential-side first pixel transistor TR 1   b.    
     The high-potential-side second pixel transistor TR 2   a  is a p-channel metal oxide semiconductor (PMOS) transistor, for example. The high-potential-side third pixel transistor TR 3   a  is an NMOS transistor, for example. The high-potential-side second pixel transistor TR 2   a  and the high-potential-side third pixel transistor TR 3   a  are coupled in series between the positive-polarity source potential VSH and the GND potential. The gates of the high-potential-side second pixel transistor TR 2   a  and the high-potential-side third pixel transistor TR 3   a  are supplied with a potential Va(m, n) of the high-potential-side first holding capacitor C 1   a.    
     The low-potential-side second pixel transistor TR 2   b  is a PMOS transistor, for example. The low-potential-side third pixel transistor TR 3   b  is an NMOS transistor, for example. The low-potential-side second pixel transistor TR 2   b  and the low-potential-side third pixel transistor TR 3   b  are coupled in series between a coupling point of the high-potential-side second pixel transistor TR 2   a  to the high-potential-side third pixel transistor TR 3   a  and the negative-polarity source potential VSL. The gates of the low-potential-side second pixel transistor TR 2   b  and the low-potential-side third pixel transistor TR 3   b  are supplied with a potential Vb(m, n) of the low-potential-side first holding capacitor C 1   b . In the present embodiment, the second holding capacitor C 2  is coupled to a coupling point of the low-potential-side second pixel transistor TR 2   b  to the low-potential-side third pixel transistor TR 3   b.    
       FIGS.  9 A,  9 B,  9 C,  9 D,  9 E, and  9 F  are timing diagrams for explaining operations in the first embodiment.  FIGS.  10 A,  10 B,  10 C,  10 D,  10 E, and  10 F  are conceptual diagrams illustrating specific examples of operations of the potential maintenance circuit according to the first embodiment. 
       FIG.  9 A  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the GND potential in the previous frame to the positive-polarity source potential VSH (at +15 V, for example).  FIG.  9 B  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the negative-polarity source potential VSL (at −15 V, for example) in the previous frame to the positive-polarity source potential VSH (at +15 V, for example).  FIG.  10 A  illustrates an operation example of the potential maintenance circuit  30  during the write period when the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example).  FIG.  10 B  illustrates an operation example of the potential maintenance circuit  30  during the hold period when the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example). 
       FIG.  9 C  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the positive-polarity source potential VSH (at +15 V, for example) in the previous frame to the GND potential.  FIG.  9 D  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the negative-polarity source potential VSL (at−15 V, for example) in the previous frame to the GND potential.  FIG.  10 C  illustrates an operation example of the potential maintenance circuit  30  during the write period when the source drive signal (pixel signal) SIG(n) is set to the GND potential.  FIG.  10 D  illustrates an operation example of the potential maintenance circuit  30  during the hold period when the source drive signal (pixel signal) SIG(n) is set to the GND potential. 
       FIG.  9 E  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the positive-polarity source potential VSH (at +15 V, for example) in the previous frame to the negative-polarity source potential VSL (at−15 V, for example).  FIG.  9 F  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the GND potential in the previous frame to the negative-polarity source potential VSL (at−15 V, for example).  FIG.  10 E  illustrates an operation example of the potential maintenance circuit  30  during the write period when the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL (at−15 V, for example).  FIG.  10 F  illustrates an operation example of the potential maintenance circuit  30  during the hold period when the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL (at−15 V, for example). 
     As illustrated in  FIGS.  9 A,  9 B,  9 C,  9 D,  9 E, and  9 F , during the write period of each of the pixels PX in the mth row, the gate driver  22   a  supplies the first positive-polarity gate potential VGH 1  to the first gate bus line (first scan line) SCL 1 ( m ), and supplies the second positive-polarity gate potential VGH 2  to the second gate bus line (second scan line) SCL 2 ( m ). During the hold period except the write period, the gate driver  22   a  supplies the first negative-polarity gate potential VGL 1  to the first gate bus line (first scan line) SCL 1 ( m ), and supplies the second negative-polarity gate potential VGL 2  to the second gate bus line (second scan line) SCL 2 ( m ). 
     As illustrated in  FIGS.  9 A and  9 B , when the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example), the GND potential is supplied to the first source bus line (first signal line) DTL 1 ( n ), and the negative-polarity source potential VSL (at−15 V, for example) is supplied to the second source bus line (second signal line) DTL 2 ( n ). That is, the first source drive signal (first pixel signal) SIG 1 ( n ) is set to the GND potential, and the second source drive signal (second pixel signal) SIG 2 ( n ) is set to the negative-polarity source potential VSL. 
     When the first positive-polarity gate potential VGH 1  (at +20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) during the write period, the high-potential-side first pixel transistor TR 1   a  is controlled to be turned on, and the potential Va(m, n) of the high-potential-side first holding capacitor C 1   a  is charged with the GND potential as illustrated in  FIG.  10 A . As a result, the high-potential-side second transistor TR 2   a  is controlled to be turned on, and the high-potential-side third transistor TR 3   a  is controlled to be turned off. 
     When the second positive-polarity gate potential VGH 2  (at +5 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) during the write period, the low-potential-side first pixel transistor TR 1   b  is controlled to be turned on, and the potential Vb(m, n) of the low-potential-side first holding capacitor C 1   b  is charged with the negative-polarity source potential VSL (at −15 V, for example) as illustrated in  FIG.  10 A . As a result, the low-potential-side second transistor TR 2   b  is controlled to be turned on, and the low-potential-side third transistor TR 3   b  is controlled to be turned off. 
     As a result, as illustrated in  FIG.  10 A , the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is charged with the positive-polarity source potential VSH (at +15 V, for example). 
     In the hold period following the write period, when the first negative-polarity gate potential VGL 1  (at−5 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) and the high-potential-side first pixel transistor TR 1   a  is controlled to be turned off, the on-control state of the high-potential-side second transistor TR 2   a  and the off-control state of the high-potential-side third transistor TR 3   a  are maintained by a potential (GND−α) obtained by subtracting a potential drop α caused by the feedthrough generated when the high-potential-side first pixel transistor TR 1   a  is turned off from the GND potential that has charged the high-potential-side first holding capacitor C 1   a  to the potential Va(m, n), as illustrated in  FIG.  10 B . 
     In the hold period, when the second negative-polarity gate potential VGL 2  (at −15 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) and the low-potential-side first pixel transistor TR 1   b  is controlled to be turned off, the on-control state of the low-potential-side second transistor TR 2   b  and the off-control state of the low-potential-side third transistor TR 3   b  are maintained by a potential (VSL−α) obtained by subtracting the potential drop α caused by the feedthrough generated when the low-potential-side first pixel transistor TR 1   b  is turned off from the negative-polarity source potential VSL (at −15 V, for example) that has charged the low-potential-side first holding capacitor C 1   b  to the potential Vb(m, n), as illustrated in  FIG.  10 B . 
     As a result, as illustrated in  FIG.  10 B , the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the positive-polarity source potential VSH (at +15 V, for example). 
     When the source drive signal (pixel signal) SIG 1 ( n ) is set to the GND potential as illustrated in  FIGS.  9 C and  9 D , the positive-polarity source potential VSH (at +15 V, for example) is supplied to the first source bus line (first signal line) DTL 1 ( n ), and the negative-polarity source potential VSL (at −15 V, for example) is supplied to the second source bus line (second signal line) DTL 2 ( n ). That is, the first source drive signal (first pixel signal) SIG 1 ( n ) is set to the positive-polarity source potential VSH, and the second source drive signal (second pixel signal) SIG 2 ( n ) is set to the negative-polarity source potential VSL. 
     When the first positive-polarity gate potential VGH 1  (at +20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) during the write period, the high-potential-side first pixel transistor TR 1   a  is controlled to be turned on, and the potential Va(m, n) of the high-potential-side first holding capacitor C 1   a  is charged with the positive-polarity source potential VSH as illustrated in  FIG.  10 C . As a result, the high-potential-side second transistor TR 2   a  is controlled to be turned off, and the high-potential-side third transistor TR 3   a  is controlled to be turned on. 
     When the second positive-polarity gate potential VGH 2  (at +5 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) during the write period, the low-potential-side first pixel transistor TR 1   b  is controlled to be turned on, and the potential Vb(m, n) of the low-potential-side first holding capacitor C 1   b  is charged with the negative-polarity source potential VSL (at −15 V, for example) as illustrated in  FIG.  10 C . As a result, the low-potential-side second transistor TR 2   b  is controlled to be turned on, and the low-potential-side third transistor TR 3   b  is controlled to be turned off. 
     As a result, as illustrated in  FIG.  10 C , the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is charged with the GND potential. 
     In the hold period following the write period, when the first negative-polarity gate potential VGL 1  (at −5 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) and the high-potential-side first pixel transistor TR 1   a  is controlled to be turned off, the off-control state of the high-potential-side second transistor TR 2   a  and the on-control state of the high-potential-side third transistor TR 3   a  are maintained by a potential (VSH−α) obtained by subtracting the potential drop α caused by the feedthrough generated when the high-potential-side first pixel transistor TR 1   a  is turned off from the positive-polarity source potential VSH (at +15 V, for example) that has charged the high-potential-side first holding capacitor C 1   a  to the potential Va(m, n), as illustrated in  FIG.  10 D . 
     In the hold period, when the second negative-polarity gate potential VGL 2  (at −15 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) and the low-potential-side first pixel transistor TR 1   b  is controlled to be turned off, the on-control state of the low-potential-side second transistor TR 2   b  and the off-control state of the low-potential-side third transistor TR 3   b  are maintained by the potential (VSL−α) obtained by subtracting the potential drop α caused by the feedthrough generated when the low-potential-side first pixel transistor TR 1   b  is turned off from the negative-polarity source potential VSL (at −15 V, for example) that has charged the low-potential-side first holding capacitor C 1   b  to the potential Vb(m, n), as illustrated in  FIG.  10 D . 
     As a result, as illustrated in  FIG.  10 D , the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the GND potential. 
     When the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL as illustrated in  FIGS.  9 E and  9 F , the positive-polarity source potential VSH (at +15 V, for example) is supplied to the first source bus line (first signal line) DTL 1 ( n ), and the GND potential is supplied to the second source bus line (second signal line) DTL 2 ( n ). That is, the first source drive signal (first pixel signal) SIG 1 ( n ) is set to the positive-polarity source potential VSH, and the second source drive signal (second pixel signal) SIG 2 ( n ) is set to the GND potential. 
     When the first positive-polarity gate potential VGH 1  (at +20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) during the write period, the high-potential-side first pixel transistor TR 1   a  is controlled to be turned on, and the potential Va(m, n) of the high-potential-side first holding capacitor C 1   a  is charged with the positive-polarity source potential VSH (at +15 V, for example) as illustrated in  FIG.  10 E . As a result, the high-potential-side second transistor TR 2   a  is controlled to be turned off, and the high-potential-side third transistor TR 3   a  is controlled to be turned on. 
     When the second positive-polarity gate potential VGH 2  (at +5 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) during the write period, the low-potential-side first pixel transistor TR 1   b  is controlled to be turned on, and the potential Vb(m, n) of the low-potential-side first holding capacitor C 1   b  is charged with the GND potential as illustrated in  FIG.  10 E . As a result, the low-potential-side second transistor TR 2   b  is controlled to be turned off, and the low-potential-side third transistor TR 3   b  is controlled to be turned on. 
     As a result, as illustrated in  FIG.  10 E , the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is charged with the negative-polarity source potential VSL (at −15 V, for example). 
     In the hold period following the write period, when the first negative-polarity gate potential VGL 1  (at −5 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) and the high-potential-side first pixel transistor TR 1   a  is controlled to be turned off, the off-control state of the high-potential-side second transistor TR 2   a  and the on-control state of the high-potential-side third transistor TR 3   a  are maintained by the potential (VSH−α) obtained by subtracting the potential drop α caused by the feedthrough generated when the high-potential-side first pixel transistor TR 1   a  is turned off from the positive-polarity source potential VSH (at +15 V, for example) that has charged the high-potential-side first holding capacitor C 1   a  to the potential Va(m, n), as illustrated in  FIG.  10 F . 
     In the hold period, when the second negative-polarity gate potential VGL 2  (at −15 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) and the low-potential-side first pixel transistor TR 1   b  is controlled to be turned off, the off-control state of the low-potential-side second transistor TR 2   b  and the on-control state of the low-potential-side third transistor TR 3   b  are maintained by the potential (GND−α) obtained by subtracting the potential drop α caused by the feedthrough generated when the low-potential-side first pixel transistor TR 1   b  is turned off from the GND potential that has charged the low-potential-side first holding capacitor C 1   b  to the potential Vb(m, n), as illustrated in  FIG.  10 F . 
     As a result, as illustrated in  FIG.  10 F , the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the negative-polarity source potential VSL (at −15 V, for example). 
     In the present embodiment, the high-potential-side first holding capacitor C 1   a  only needs to have capacitance required to maintain the control states of the high-potential-side second transistor TR 2   a  and the high-potential-side third transistor TR 3   a  during the hold period. The low-potential-side first holding capacitor C 1   b  also only needs to have capacitance required to maintain the control states of the low-potential-side second transistor TR 2   b  and the low-potential-side third transistor TR 3   b  during the hold period. Specifically, the high-potential-side first holding capacitor C 1   a  and the low-potential-side first holding capacitor C 1   b  have capacitance of approximately 0.1 pF, for example. This capacitance can reduce the potential drop α caused by the feedthrough that occurs when the high-potential-side first pixel transistor TR 1   a  is turned off and when the low-potential-side first pixel transistor TR 1   b  is turned off. 
     The potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the positive-polarity source potential VSH (at +15 V, for example), the GND potential, or the negative-polarity source potential VSL (at −15 V, for example) during the hold period. This operation can restrain the reduction in display quality caused by the potential variation. 
     Each of the positive-polarity source potential VSH, the GND potential, and the negative-polarity source potential VSL supplied to the pixel PX may be a value obtained by adding the potential drop α caused by the feedthrough that occurs when the high-potential-side first pixel transistor TR 1   a  is turned off and when the low-potential-side first pixel transistor TR 1   b  is turned off. This addition can offset the potential drop α caused by the feedthrough that occurs when the high-potential-side first pixel transistor TR 1   a  is turned off and when the low-potential-side first pixel transistor TR 1   b  is turned off. 
     Thus, with the configuration of the first embodiment, the potential of the pixel electrode Pix is statically held in the state of being supplied with any one of the three potential values supplied to the pixel PX. This operation reduces the potential variation of the pixel electrode Pix, and thus, can restrain the reduction in display quality. 
     With the configuration of the present embodiment, when the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example), a high potential of VSH−VSL (for example, +15 V−(−15 V)=30 V) is applied to the low-potential-side third transistor TR 3   b  interposed between the positive-polarity source potential VSH (at +15 V, for example) and the negative-polarity source potential VSL (at −15 V, for example) during the write period and the hold period, as illustrated in  FIGS.  10 A and  10 B . For this reason, for example, the low-potential-side third transistor TR 3   b  preferably has a double-gate configuration. Alternatively, in an aspect of the present disclosure, the low-potential-side third transistor TR 3   b  may have a larger L-length than that of the other transistors. 
     Second Embodiment 
       FIG.  11    is a block diagram illustrating a configuration example of a display device according to a second embodiment of the present disclosure.  FIG.  12    is a diagram illustrating an exemplary configuration of one pixel of the display device according to the second embodiment.  FIGS.  13 A,  13 B,  13 C,  13 D,  13 E, and  13 F  are timing diagrams for explaining operations in the second embodiment.  FIGS.  14 A,  14 B, and  14 C  are conceptual diagrams illustrating specific examples of operations of a potential maintenance circuit according to the second embodiment. In the following description, the same components as those described in the first embodiment above will be denoted by the same reference numerals without being described again, and only differences from the first embodiment will be described. 
     In a display device  10   b  according to the second embodiment, the source driver  21  (first driver) of a display panel driver  20   b  corresponds to the source driver  21  of the comparative example described above. A gate driver  22   b  (second driver) corresponds to the gate driver  22  of the comparative example described above. In the present embodiment, the positive-polarity gate potential VGH is set to +19 V, for example. In the present embodiment, the negative-polarity gate potential VGL is set to −17 V, for example. 
     As illustrated in  FIG.  12   , a potential maintenance circuit  30   a  according to the second embodiment includes a first pixel transistor TR 1 , a second pixel transistor TR 2 , a third pixel transistor TR 3 , and a fourth pixel transistor TR 4 . 
     In the present embodiment, the first pixel transistor TR 1  is an NMOS transistor corresponding to the pixel transistor TR of the comparative example described above. In the present embodiment, one end of the first holding capacitor C 1  is coupled to the source bus line (signal line) DTL(n) through the first pixel transistor TR 1 . In the present embodiment, the negative-polarity source potential VSL is applied to the other end of the first holding capacitor C 1 . 
     The second pixel transistor TR 2  is an NMOS transistor, for example. The third pixel transistor TR 3  is an NMOS transistor, for example. The second and the third pixel transistors TR 2  and TR 3  are coupled in series between the positive-polarity source potential VSH and a reset potential VRST. The reset potential VRST is set to −18 V, for example. 
     The second holding capacitor C 2  is coupled to a coupling point of the second pixel transistor TR 2  to the third pixel transistor TR 3 . The gate of the second pixel transistor TR 2  is supplied with a potential V(m, n) of the first holding capacitor C 1 . The gate of the third pixel transistor TR 3  is coupled to a gate bus line (scan line) SCL(m-1) coupled to the pixels PX in the (m-1)th row, that is, in a row before the mth row. This configuration resets the potential Vpix(m, n) of the second holding capacitor C 2  in each of the pixels PX in the mth row during the write period of each of the pixels PX in the (m-1)th row. 
     The fourth pixel transistor TR 4  is an NMOS transistor, for example. The fourth pixel transistor TR 4  is coupled between the second pixel transistor TR 2  and the negative-polarity source potential VSL. That is, the fourth pixel transistor TR 4  is coupled between both ends of the first holding capacitor C 1 . The gate of the fourth pixel transistor TR 4  is coupled to the gate bus line (scan line) SCL(m-1) coupled to each of the pixels PX in the (m-1)th row. This configuration resets the potential V(m, n) of the first holding capacitor C 1  in each of the pixels PX in the mth row during the write period of each of the pixels PX in the (m-1)th row. 
     That is, with the configuration of the second embodiment, a reset period of the first and the second holding capacitors C 1  and C 2  is provided before the write period of each of the pixels PX in the mth row. In the present embodiment, the reset period of each of the pixels PX in the mth row is defined as a period corresponding to the write period of each of the pixel PX in the (m-1)th row immediately before the write period of each of the pixels PX in the mth row. 
       FIG.  13 A  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the GND potential in the previous frame to the positive-polarity source potential VSH (at +15 V, for example).  FIG.  13 B  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the negative-polarity source potential VSL (at −15 V, for example) in the previous frame to the positive-polarity source potential VSH (at +15 V, for example). 
       FIG.  13 C  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the positive-polarity source potential VSH (at +15 V, for example) in the previous frame to the GND potential.  FIG.  13 D  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the negative-polarity source potential VSL (at −15 V, for example) in the previous frame to the GND potential. 
       FIG.  13 E  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the positive-polarity source potential VSH (at +15 V, for example) in the previous frame to the negative-polarity source potential VSL (at −15 V, for example).  FIG.  13 F  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the GND potential in the previous frame to the negative-polarity source potential VSL (at −15 V, for example). 
       FIG.  14 A  illustrates an operation example of the potential maintenance circuit  30   a  during the reset period.  FIG.  14 B  illustrates an operation example of the potential maintenance circuit  30   a  during the write period.  FIG.  14 C  illustrates an operation example of the potential maintenance circuit  30   a  during the hold period. 
     As illustrated in  FIGS.  13 A,  13 B,  13 C,  13 D,  13 E, and  13 F , the gate driver  22   b  supplies the positive-polarity gate potential VGH to the gate bus line (scan line) SCL(m) during the write period of each of the pixels PX in the mth row. The gate driver  22   b  supplies the negative-polarity gate potential VGL to the gate bus line (scan line) SCL(m) during the hold period except the write period. The gate driver  22   b  supplies the positive-polarity gate potential VGH to the gate bus line (scan line) SCL(m-1) during the reset period of each of the pixels PX in the mth row. The gate driver  22   b  supplies the negative-polarity gate potential VGL to the gate bus line (scan line) SCL(m-1) during the periods except the reset period of each of the pixels PX in the mth row. 
     In the present embodiment, the reset period of each of the pixels PX in the mth row is defined as the period corresponding to the write period of each of the pixel PX in the (m-1)th row. However, an aspect of the present disclosure may be such that a reset line(m) is provided in addition to the gate bus line (scan line) SCL(m), and the reset line(m) is supplied with the positive-polarity gate potential VGH during the reset period corresponding to the write period of each of the pixel PX in the (m-1)th row, and supplied with the negative-polarity gate potential VGL during the periods except the reset period. 
     First, the following describes the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example), with reference to  FIGS.  13 A and  13 B . 
     During the hold period before the reset period, the negative-polarity gate potential VGL (at−17 V, for example) is supplied to the gate bus lines (scan lines) SCL(m-1) and SCL(m). At this time, the first pixel transistor TR 1  and the fourth pixel transistor TR 4  illustrated with dashed lines in  FIG.  14 C  are controlled to be turned off. At this time, the third pixel transistor TR 3  illustrated with a long dashed short dashed line serves as a constant-current source driven by a gate-source potential Vgs (=VGL−VRST) (for example, −17 V−(−18 V)=1 V). 
     When the positive-polarity gate potential VGH (at +19 V, for example) is supplied to the gate bus line (scan line) SCL(m-1) during the subsequent holding period, the third and the fourth pixel transistors TR 3  and TR 4  are controlled to be turned on. This operation resets the potential V(m, n) of the first holding capacitor C 1  to the negative-polarity source potential VSL as illustrated in  FIG.  14 A , and as a result, the second pixel transistor TR 2  is controlled to be turned off to reset the potential Vpix(m, n) of the second holding capacitor C 2  to the reset potential VRST. 
     During the write period, when the negative-polarity gate potential VGL (at−17 V, for example) is supplied to the gate bus line (scan line) SCL(m-1) and the positive-polarity gate potential VGH (at +19 V, for example) is supplied to the gate bus line (scan line) SCL(m), the first pixel transistor TR 1  is controlled to be turned on, and the fourth pixel transistor TR 4  is controlled to be turned off. 
     As a result, as illustrated in  FIG.  14 B , the source drive signal (pixel signal) SIG(n) (at the positive-polarity source potential VSH (at +15 V, for example) in the examples illustrated in  FIGS.  13 A and  13 B ) is applied as the potential V(m, n) of the first holding capacitor C 1 . This operation charges the first holding capacitor C 1  with a difference between the potential of the source drive signal (pixel signal) SIG(n) and the negative-polarity source potential VSL (in this case, VSH−VSL=+15 V−(−15 V)=30 V), and as a result, the second pixel transistor TR 2  is controlled to be turned on. 
     At this time, the third pixel transistor TR 3  illustrated with a long dashed short dashed line serves as a constant-current source driven by the gate-source potential Vgs (=VGL−VRST) (for example,−17 V−(−18 V)=1 V), and a potential obtained by subtracting Vth of the second transistor TR 2  from the potential V(m, n) of the first holding capacitor C 1  (in this case, source drive signal (pixel signal) SIG(n)=positive-polarity source potential VSH (at +15 V, for example)) is applied as the potential Vpix(m, n) of the second holding capacitor C 2 , as illustrated in  FIG.  14 B . As a result, the second holding capacitor C 2  is charged with a potential (VSH−Vth) obtained by subtracting Vth of the second transistor TR 2  from the source drive signal (pixel signal) SIG(n)=the positive-polarity source potential VSH (at +15 V, for example). 
     During the hold period following the write period, when the negative-polarity gate potential VGL (at−17 V, for example) is supplied to the gate bus line (scan line) SCL(m), the first pixel transistor TR 1  is controlled to be turned off. As a result, as illustrated in  FIG.  14 C , the on-control state of the second transistor TR 2  is maintained by a potential (SIG(n)−α−Vth) obtained by subtracting the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off and Vth of the second transistor TR 2  from the potential of the source drive signal (pixel signal) SIG(n) (at the positive-polarity source potential VSH (at +15 V, for example) in the examples illustrated in  FIGS.  13 A and  13 B ) that has charged the first holding capacitor C 1  as the potential V(m, n). 
     As a result, the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with a potential (VSH−α−Vth) obtained by subtracting the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is tuned off and Vth of the second transistor TR 2  from the potential of the source drive signal (pixel signal) SIG(n) (in this case, the positive-polarity source potential VSH (at +15 V, for example)). 
     The following describes the case where the source drive signal (pixel signal) SIG(n) is set to the GND potential, with reference to  FIGS.  13 C and  13 D . The following describes differences from the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example) (refer to  FIGS.  13 A and  13 B ). 
     When the source drive signal (pixel signal) SIG(n) is set to the GND potential, the GND potential is applied as the potential V(m, n) of the first holding capacitor C 1  during the write period. This operation charges the first holding capacitor C 1  with a difference between the GND potential and the negative-polarity source potential VSL (GND−VSL=0−(−15 V)=15 V), and as a result, the second pixel transistor TR 2  is controlled to be turned on. 
     At this time, a potential obtained by subtracting Vth of the second transistor TR 2  from the GND potential is applied as the potential Vpix(m, n) of the second holding capacitor C 2 . This operation charges the second holding capacitor C 2  with a potential (GND−Vth) obtained by subtracting Vth of the second transistor TR 2  from the GND potential. 
     When the first pixel transistor TR 1  is controlled to be turned off during the hold period following the write period, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with a potential (GND−α−Vth) obtained by subtracting the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is tuned off and Vth of the second transistor TR 2  from the GND potential that has charged the first holding capacitor C 1  as the potential V(m, n). 
     The following describes the case where the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL (at −15 V, for example), with reference to  FIGS.  13 E and  13 F . The following describes differences from the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example) (refer to  FIGS.  13 A and  13 B ) and the case where the source drive signal (pixel signal) SIG(n) is set to the GND potential (refer to  FIGS.  13 C and  13 D ). 
     When the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL (at −15 V, for example), the negative-polarity source potential VSL (at −15 V, for example) is applied as the potential V(m, n) of the first holding capacitor C 1  during the write period. This operation controls to turn on the second pixel transistor TR 2 . 
     At this time, a potential obtained by subtracting Vth of the second transistor TR 2  from the negative-polarity source potential VSL (at −15 V, for example) is applied as the potential Vpix(m, n) of the second holding capacitor C 2 . This operation charges the second holding capacitor C 2  with a potential (VSL−Vth) obtained by subtracting Vth of the second transistor TR 2  from the negative-polarity source potential VSL (at −15 V, for example). 
     When the first pixel transistor TR 1  is controlled to be turned off during the hold period following the write period, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with a potential (VSL−α−Vth) obtained by subtracting the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off and Vth of the second transistor TR 2  from the negative-polarity source potential VSL (at −15 V, for example) that has charged the first holding capacitor C 1  as the potential V(m, n). 
     In the present embodiment, the first holding capacitor C 1  only needs to have capacitance required to maintain the on-state of the second transistor TR 2  during the hold period. Specifically, the first holding capacitor C 1  has capacitance of approximately 0.1 pF, for example. This capacitance can reduce the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off. 
     The potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the positive-polarity source potential VSH (at +15 V, for example), the GND potential, or the negative-polarity source potential VSL (at −15 V, for example) during the hold period. This operation can restrain the reduction in display quality caused by the potential variation. 
     Third Embodiment 
       FIG.  15    is a block diagram illustrating a configuration example of a display device according to a third embodiment of the present disclosure.  FIG.  16    is a diagram illustrating an exemplary configuration of one pixel of the display device according to the third embodiment.  FIGS.  17 A,  17 B,  17 C,  17 D,  17 E, and  17 F  are timing diagrams for explaining operations in the third embodiment.  FIGS.  18 A,  18 B, and  18 C  are conceptual diagrams illustrating specific examples of operations of a potential maintenance circuit according to the third embodiment. In the following description, the same components as those described in the second embodiment above will be denoted by the same reference numerals without being described again, and only differences from the second embodiment will be described. 
     In a display device  10   c  according to the third embodiment, a gate driver  22   c  (second driver) of a display panel driver  20   c  is electrically coupled to the pixels PX arranged in the X-direction in the display region  11  through the first gate bus line (first scan line) SCL 1 ( m ), and transmits the first gate drive signal (first scan signal) Gate 1 ( m ) to the first gate bus line (first scan line) SCL 1 ( m ). The gate driver  22   c  supplies the first positive-polarity gate potential VGH 1  to the first gate bus line (first scan line) SCL 1 ( m ) during the write period. The gate driver  22   c  supplies the first negative-polarity gate potential VGL 1  to the first gate bus line (first scan line) SCL 1 ( m ) during the hold period. In the present embodiment, the first positive-polarity gate potential VGH 1  is set to +19 V, for example. In the present embodiment, the first negative-polarity gate potential VGL 1  is set to −17 V, for example. 
     The gate driver  22   c  is also electrically coupled to the pixels PX arranged in the X-direction in the display region  11  through the second gate bus line (second scan line) SCL 2 ( m ), and transmits the second gate drive signal (second scan signal) Gate 2 ( m ) to the second gate bus line (second scan line) SCL 2 ( m ). The gate driver  22   c  supplies the second positive-polarity gate potential VGH 2  to the second gate bus line (second scan line) SCL 2 ( m ) during the write period. The gate driver  22   c  supplies the second negative-polarity gate potential VGL 2  to the second gate bus line (second scan line) SCL 2 ( m ) during the hold period. In the present embodiment, the second positive-polarity gate potential VGH 2  is set to −10 V, for example. In the present embodiment, the second negative-polarity gate potential VGL 2  is set to −14 V, for example. 
     In a potential maintenance circuit  30   b  according to the third embodiment, the second and the third pixel transistors TR 2  and TR 3  are coupled in series between the positive-polarity source potential VSH and the negative-polarity source potential VSL. The gate of the third pixel transistor TR 3  is coupled to a second gate bus line (second scan line) SCL 2 ( m -1) coupled to each of the pixels PX in the (m-1)th row, that is, in the row before the mth row. 
     In the pixel PX according to the third embodiment, the gate of the fourth pixel transistor TR 4  is coupled to a first gate bus line (first scan line) SCL 1 ( m -1) coupled to each of the pixels PX in the (m-1)th row. 
       FIG.  17 A  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the GND potential in the previous frame to the positive-polarity source potential VSH (at +15 V, for example).  FIG.  17 B  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the negative-polarity source potential VSL (at −15 V, for example) in the previous frame to the positive-polarity source potential VSH (at +15 V, for example). 
       FIG.  17 C  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the positive-polarity source potential VSH (at +15 V, for example) in the previous frame to the GND potential.  FIG.  17 D  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the negative-polarity source potential VSL (at −15 V, for example) in the previous frame to the GND potential. 
       FIG.  17 E  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the positive-polarity source potential VSH (at +15 V, for example) in the previous frame to the negative-polarity source potential VSL (at −15 V, for example).  FIG.  17 F  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the GND potential in the previous frame to the negative-polarity source potential VSL (at −15 V, for example). 
       FIG.  18 A  illustrates an operation example of the potential maintenance circuit  30   b  during the reset period.  FIG.  18 B  illustrates an operation example of the potential maintenance circuit  30   b  during the write period.  FIG.  18 C  illustrates an operation example of the potential maintenance circuit  30   b  during the hold period. 
     As illustrated in  FIGS.  17 A,  17 B,  17 C,  17 D,  17 E, and  17 F , during the write period of each of the pixels PX in the mth row, the gate driver  22   c  supplies the first positive-polarity gate potential VGH 1  to the first gate bus line (first scan line) SCL 1 ( m ), and supplies the second positive-polarity gate potential VGH 2  to the second gate bus line (second scan line) SCL 2 ( m ). During the hold period except the write period, the gate driver  22   c  supplies the negative-polarity gate potential VGL 1  to the first gate bus line (first scan line) SCL 1 ( m ), and supplies the negative-polarity gate potential VGL 2  to the second gate bus line (second scan line) SCL 2 ( m ). 
     During the reset period of each of the pixels PX in the mth row, the gate driver  22   c  supplies the first positive-polarity gate potential VGH 1  to the first gate bus line (first scan line) SCL 1 ( m -1), and supplies the second positive-polarity gate potential VGH 2  to the second gate bus line (second scan line) SCL 2 ( m -1). During the periods except the reset period of each of the pixels PX in the mth row, the gate driver  22   c  supplies the first negative-polarity gate potential VGL 1  to the first gate bus line (first scan line) SCL 1 ( m -1), and supplies the second negative-polarity gate potential VGL 2  to the second gate bus line (second scan line) SCL 2 ( m -1). 
     In the same manner as in the second embodiment, an aspect of the present disclosure may be such that a first reset line(m) and a second reset line(m) are provided in addition to the first gate bus line (first scan line) SCL 1 ( m ) and the second gate bus line (second scan line) SCL 2 ( m ), and such that the first reset line(m) is supplied with the gate driver  22   c  supplies the first positive-polarity gate potential VGH 1  and the second reset line(m) is supplied with the second positive-polarity gate potential VGH 2  during the reset period corresponding to the write period of each of the pixel PX in the (m-1)th row, and the first reset line(m) is supplied with the first negative-polarity gate potential VGL 1  and the second reset line(m) is supplied with the second negative-polarity gate potential VGL 2  during the periods except the reset period. 
     First, the following describes the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example), with reference to  FIGS.  17 A and  17 B . 
     During the hold period before the reset period, the first negative-polarity gate potential VGL 1  (at−17 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m -1) and the first gate bus line (first scan line) SCL 1 ( m ), and the first negative-polarity gate potential VGL 2  (at−14 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m -1). At this time, the first pixel transistor TR 1  and the fourth pixel transistor TR 4  illustrated with dashed lines in  FIG.  18 C  are controlled to be turned off. At this time, the third pixel transistor TR 3  illustrated with a long dashed short dashed line serves as a constant-current source driven by the gate-source potential Vgs (=VGL 2 −VSL) (for example, −14 V−(−15 V)=1 V). 
     During the subsequent reset period, when the first positive-polarity gate potential VGH 1  (at +19 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m -1) and the second positive-polarity gate potential VGH 2  (at−10 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m -1), the third and the fourth pixel transistors TR 3  and TR 4  are controlled to be turned on. This operation resets the potential V(m, n) of the first holding capacitor C 1  to the negative-polarity source potential VSL as illustrated in  FIG.  18 A , and as a result, the second pixel transistor TR 2  is controlled to be turned off to reset the potential Vpix(m, n) of the second holding capacitor C 2  to the negative-polarity source potential VSL. 
     In the write period, when the first negative-polarity gate potential VGL 1  (at−17 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m -1), the second negative-polarity gate potential VGL 2  (at−14 V, for example) to the second gate bus line (second scan line) SCL 2 ( m -1), and the first positive-polarity gate potential VGH 1  (at +19 V, for example) to the first gate bus line (first scan line) SCL 1 ( m ), the first pixel transistor TR 1  is controlled to be turned on, and the fourth pixel transistor TR 4  is controlled to be turned off. 
     As a result, as illustrated in  FIG.  18 B , the source drive signal (pixel signal) SIG(n) (at the positive-polarity source potential VSH (at +15 V, for example) in the examples illustrated in  FIGS.  17 A and  17 B ) is applied as the potential V(m, n) of the first holding capacitor C 1 . This operation charges the first holding capacitor C 1  with a difference between the potential of the source drive signal (pixel signal) SIG(n) and the negative-polarity source potential VSL (in this case, VSH−VSL=+15 V−(−15 V)=30 V), and as a result, the second pixel transistor TR 2  is controlled to be turned on. 
     At this time, the third pixel transistor TR 3  illustrated with a long dashed short dashed line serves as a constant-current source driven by the gate-source potential Vgs (=VGL 2 −VSL) (for example,−14 V−(−15 V)=1 V), and a potential obtained by subtracting Vth of the second transistor TR 2  from the potential V(m, n) of the first holding capacitor C 1  (in this case, source drive signal (pixel signal) SIG(n)=positive-polarity source potential VSH (at +15 V, for example)) is applied as the potential Vpix(m, n) of the second holding capacitor C 2 , as illustrated in  FIG.  18 B . As a result, the second holding capacitor C 2  is charged with the potential (VSH−Vth) obtained by subtracting Vth of the second transistor TR 2  from the source drive signal (pixel signal) SIG(n)=the positive-polarity source potential VSH (at +15 V, for example). 
     During the hold period following the write period, when the first negative-polarity gate potential VGL 1  (at −17 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ), the first pixel transistor TR 1  is controlled to be turned off. As a result, as illustrated in  FIG.  18 C , the on-control state of the second transistor TR 2  is maintained by a potential (SIG(n)−α−Vth) obtained by subtracting the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off and Vth of the second transistor TR 2  from the potential of the source drive signal (pixel signal) SIG(n) (at the positive-polarity source potential VSH (at +15 V, for example) in the examples illustrated in  FIGS.  17 A and  17 B ) that has charged the first holding capacitor C 1  as the potential V(m, n). 
     As a result, the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the potential (VSH−α−Vth) obtained by subtracting the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off and Vth of the second transistor TR 2  from the potential of the source drive signal (pixel signal) SIG(n) (in this case, the positive-polarity source potential VSH (at +15 V, for example)). 
     The following describes the case where the source drive signal (pixel signal) SIG(n) is set to the GND potential, with reference to  FIGS.  17 C and  17 D . The following describes differences from the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example) (refer to  FIGS.  17 A and  17 B ). 
     When the source drive signal (pixel signal) SIG(n) is set to the GND potential, the GND potential is applied as the potential V(m, n) of the first holding capacitor C 1  during the write period. This operation charges the first holding capacitor C 1  with the difference between the GND potential and the negative-polarity source potential VSL (GND−VSL=0−(−15 V)=15 V), and as a result, the second pixel transistor TR 2  is controlled to be turned on. 
     At this time, the potential obtained by subtracting Vth of the second transistor TR 2  from the GND potential is applied as the potential Vpix(m, n) of the second holding capacitor C 2 . This operation charges the second holding capacitor C 2  with the potential (GND−Vth) obtained by subtracting Vth of the second transistor TR 2  from the GND potential. 
     When the first pixel transistor TR 1  is controlled to be turned off during the hold period following the write period, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the potential (GND−α−Vth) obtained by subtracting the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off and Vth of the second transistor TR 2  from the GND potential that has charged the first holding capacitor C 1  as the potential V(m, n). 
     The following describes the case where the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL (at −15 V, for example), with reference to  FIGS.  17 E and  17 F . The following describes differences from the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example) (refer to  FIGS.  17 A and  17 B ) and the case where the source drive signal (pixel signal) SIG(n) is set to the GND potential (refer to  FIGS.  17 C and  17 D ). 
     When the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL (at −15 V, for example), the negative-polarity source potential VSL (at −15 V, for example) is applied as the potential V(m, n) of the first holding capacitor C 1  during the write period. This operation controls to turn on the second pixel transistor TR 2 . 
     At this time, the potential obtained by subtracting Vth of the second transistor TR 2  from the negative-polarity source potential VSL (at −15 V, for example) is applied as the potential Vpix(m, n) of the second holding capacitor C 2 . This operation charges the second holding capacitor C 2  with the potential (VSL−Vth) obtained by subtracting Vth of the second transistor TR 2  from the negative-polarity source potential VSL (at −15 V, for example). 
     When the first pixel transistor TR 1  is controlled to be turned off during the hold period following the write period, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with a potential (VSL−α−Vth) obtained by subtracting the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off and Vth of the second transistor TR 2  from the negative-polarity source potential VSL (at −15 V, for example) that has charged the first holding capacitor C 1  as the potential V(m, n). 
     In the present embodiment, in the same manner as in the second embodiment, the first holding capacitor C 1  only needs to have capacitance required to maintain the on-state of the second transistor TR 2  during the hold period. Specifically, the first holding capacitor C 1  has capacitance of approximately 0.1 pF, for example. This capacitance can reduce the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off. 
     The potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the positive-polarity source potential VSH (at +15 V, for example), the GND potential, or the negative-polarity source potential VSL (at −15 V, for example) during the hold period. This operation can restrain the reduction in display quality caused by the potential variation. 
     In the second embodiment, the second and the third pixel transistors TR 2  and TR 3  are coupled in series between the positive-polarity source potential VSH and the reset potential VRST. However, in the third embodiment, the second and the third pixel transistors TR 2  and TR 3  are coupled in series between the positive-polarity source potential VSH and the negative-polarity source potential VSL. This configuration can reduce the number of power supply potentials supplied to the pixel PX. 
     In the second embodiment, the gates of the third pixel transistor TR 3  and the fourth pixel transistor TR 4  are coupled to the first gate bus line (first scan line) SCL 1 ( m -1) coupled to each of the pixels PX in the (m-1)th row. However, in the third embodiment, the gate of the third pixel transistor TR 3  is coupled to the second gate bus line (second scan line) SCL 2 ( m -1) that is supplied with different potentials during the periods except the reset period. This configuration facilitates adjustment of the gate-source potential Vgs when operating the third pixel transistor TR 3  as the constant-current source during the periods except the reset period. Specifically, the gate-source potential Vgs when operating the third pixel transistor TR 3  as the constant-current source can be adjusted by adjusting the second negative-polarity gate potential VGL 2  (at, for example,−14 V in the present embodiment) supplied to the second gate bus line (second scan line) SCL 2 ( m -1) during the periods except the reset period, 
     Fourth Embodiment 
       FIG.  19    is a block diagram illustrating a configuration example of a display device according to a fourth embodiment of the present disclosure.  FIG.  20    is a diagram illustrating an exemplary configuration of one pixel of the display device according to the fourth embodiment.  FIGS.  21 A,  21 B,  21 C,  21 D,  21 E, and  21 F  are timing diagrams for explaining operations in the fourth embodiment.  FIGS.  22 A,  22 B,  22 C, and  22 D  are conceptual diagrams illustrating specific examples of operations of a potential maintenance circuit according to the fourth embodiment. In the following description, the same components as those described in any of the embodiments above will be denoted by the same reference numerals without being described again, and only differences from the embodiments described above will be described. 
     In a display device  10   d  according to the fourth embodiment, a gate driver  22   d  of a display panel driver  20   d  is electrically coupled to the pixels PX arranged in the X-direction in the display region  11  through the first gate bus line (first scan line) SCL 1 ( m ), and transmits the first gate drive signal (first scan signal) Gate 1 ( m ) to the first gate bus line (first scan line) SCL 1 ( m ). 
     The gate driver  22   d  is also electrically coupled to the pixels PX arranged in the X-direction in the display region  11  through the second gate bus line (second scan line) SCL 2 ( m ), and transmits the second gate drive signal (second scan signal) Gate 2 ( m ) to the second gate bus line (second scan line) SCL 2 ( m ). 
     The gate driver  22   d  is also electrically coupled to the pixels PX arranged in the X-direction in the display region  11  through a third gate bus line (third scan line) SCL 3 ( m ), and transmits a third gate drive signal (third scan signal) Gate 3 ( m ) to the third gate bus line (third scan line) SCL 3 ( m ). 
     The gate driver  22   d  is also electrically coupled to the pixels PX arranged in the X-direction in the display region  11  through a fourth gate bus line (fourth scan line) SCL 4 ( m ), and transmits a fourth gate drive signal (fourth scan signal) Gate 1 ( m ) to the fourth gate bus line (fourth scan line) SCL 4 ( m ). 
     As illustrated in  FIG.  20   , a potential maintenance circuit  30   c  according to the fourth embodiment includes the first pixel transistor TR 1 , the second pixel transistor TR 2 , the third pixel transistor TR 3 , the fourth pixel transistor TR 4 , a fifth pixel transistor TR 5 , and a sixth pixel transistor TR 6 . 
     In the present embodiment, the first pixel transistor TR 1  is an NMOS transistor corresponding to the pixel transistor TR of the comparative example described above. In the present embodiment, the second holding capacitor C 2  (pixel electrode Pix) is supplied with the source drive signal (pixel signal) SIG(n) from the source bus line (signal line) DTL(n) through the first pixel transistor TR 1  in the same manner as in the comparative example described above. 
     In the present embodiment, the second pixel transistor TR 2 , the third pixel transistor TR 3 , the fourth pixel transistor TR 4 , the fifth pixel transistor TR 5 , and the sixth pixel transistor TR 6  are NMOS transistors. 
     The second and the third pixel transistors TR 2  and TR 3  are coupled in series between the positive-polarity gate potential VGH and the second holding capacitor C 2  (pixel electrode Pix). The gate of the second pixel transistor TR 2  is coupled to the second gate bus line (second scan line) SCL 2 ( m ). The gate of the third pixel transistor TR 3  is supplied with a potential V2(m, n) of the high-potential-side first holding capacitor C 1   a.    
     The fourth pixel transistor TR 4  is coupled between a coupling point of the second pixel transistor TR 2  to the third pixel transistor TR 3  and the gate of the third pixel transistor TR 3 . The gate of the fourth pixel transistor TR 4  is coupled to the third gate bus line (third scan line) SCL 3 ( m ). 
     The fifth pixel transistor TR 5  is coupled between the second holding capacitor C 2  (pixel electrode Pix) and the negative-polarity gate potential VGL. The gate of the fifth pixel transistor TR 5  is supplied with a potential V3(m, n) of the low-potential-side first holding capacitor C 1   b.    
     The sixth pixel transistor TR 6  is coupled between the second holding capacitor C 2  (pixel electrode Pix) and the gate of the fifth pixel transistor TR 5 . The gate of the sixth pixel transistor TR 6  is coupled to the fourth gate bus line (fourth scan line) SCL 4 ( m ). 
       FIG.  21 A  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the GND potential in the previous frame to the positive-polarity source potential VSH (at +15 V, for example).  FIG.  21 B  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the negative-polarity source potential VSL (at −15 V, for example) in the previous frame to the positive-polarity source potential VSH (at +15 V, for example). 
       FIG.  21 C  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the positive-polarity source potential VSH (at +15 V, for example) in the previous frame to the GND potential.  FIG.  21 D  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the negative-polarity source potential VSL (at −15 V, for example) in the previous frame to the GND potential. 
       FIG.  21 E  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the positive-polarity source potential VSH (at +15 V, for example) in the previous frame to the negative-polarity source potential VSL (at −15 V, for example).  FIG.  21 F  illustrates a timing diagram when the potential of the source drive signal (pixel signal) SIG(n) has changed from the GND potential in the previous frame to the negative-polarity source potential VSL (at −15 V, for example). 
     As illustrated in  FIGS.  21 A,  21 B,  21 C,  21 D,  21 E, and  21 F , the configuration of the fourth embodiment is provided with an initialization period (Initialize) and an initial potential setting period (Set) before the write period (Write) of each of the pixels PX in the mth row. 
       FIG.  22 A  illustrates an operation example of the potential maintenance circuit  30   c  during the initialization period.  FIG.  22 B  illustrates an operation example of the potential maintenance circuit  30   c  during the initial potential setting period.  FIG.  22 C  illustrates an operation example of the potential maintenance circuit  30   c  during the write period.  FIG.  22 D  illustrates an operation example of the potential maintenance circuit  30   c  during the hold period. 
     During the initialization period of each of the pixels PX in the mth row, the gate driver  22   d  supplies the positive-polarity gate potential VGH to the fourth gate bus line (fourth scan line) SCL 4 ( m ), and supplies the negative-polarity gate potential VGL to the first gate bus line (first scan line) SCL 1 ( m ), the second gate bus line (second scan line) SCL 2 ( m ), and the third gate bus line (third scan line) SCL 3 ( m ). 
     During the initial potential setting period of each of the pixels PX in the mth row, the gate driver  22   d  supplies the positive-polarity gate potential VGH to the second gate bus line (second scan line) SCL 2 ( m ) and the third gate bus line (third scan line) SCL 3 ( m ), and supplies the negative-polarity gate potential VGL to the first gate bus line (first scan line) SCL 1 ( m ) and the fourth gate bus line (fourth scan line) SCL 4 ( m ). 
     During the write period of each of the pixels PX in the mth row, the gate driver  22   d  supplies the positive-polarity gate potential VGH to the first gate bus line (first scan line) SCL 1 ( m ) and the third gate bus line (third scan line) SCL 3 ( m ), and supplies the negative-polarity gate potential VGL to the second gate bus line (second scan line) SCL 2 ( m ) and the fourth gate bus line (fourth scan line) SCL 4 ( m ). 
     During the hold period except the initialization period, the initial potential setting period, and the write period of each of the pixels PX in the mth row, the gate driver  22   d  supplies the positive-polarity gate potential VGH to the second gate bus line (second scan line) SCL 2 ( m ), and supplies the negative-polarity gate potential VGL to the first gate bus line (first scan line) SCL 1 ( m ), the third gate bus line (third scan line) SCL 3 ( m ), and the fourth gate bus line (fourth scan line) SCL 4 ( m ). 
     In the present embodiment, the positive-polarity gate potential VGH (high-potential positive-polarity potential) is set to, for example, +20 V higher than the positive-polarity source potential VSH (at +15 V, for example). In the present embodiment, the negative gate potential VGL (low-potential negative-polarity potential) is set to, for example,−20 V lower than the negative-polarity source potential VSL (at −15 V, for example). 
     First, the following describes the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example), with reference to  FIGS.  21 A and  21 B . 
     During the hold period before the initialization period, the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ), and the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ), the third gate bus line (third scan line) SCL 3 ( m ), and the fourth gate bus line (fourth scan line) SCL 4 ( m ). At this time, the fourth and the sixth pixel transistors TR 4  and TR 6  illustrated with dashed lines in  FIG.  22 D  are controlled to be turned off. 
     When the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) before the initialization period, the second pixel transistor TR 2  is controlled to be turned off. When the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the fourth gate bus line (fourth scan line) SCL 4 ( m ) during the subsequent initialization period, the sixth pixel transistor TR 6  is controlled to be turned on. As a result, the fifth pixel transistor TR 5  is turned on, and the potential V3(m, n) of the low-potential-side first holding capacitor C 1   b  becomes equal to the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix), and at the same time, is initialized to a potential (VGL+Vth) obtained by adding Vth of the fifth pixel transistor TR 5  to the negative-polarity gate potential VGL. Accordingly, the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) is also initialized to the potential (VGL+Vth) ( FIG.  22 A ). 
     When the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the fourth gate bus line (fourth scan line) SCL 4 ( m ) before the initial potential setting period, the sixth pixel transistor TR 6  is controlled to be turned off. When the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) and the third gate bus line (third scan line) SCL 3 ( m ) during the subsequent initial potential setting period, the second and the fourth pixel transistors TR 2  and TR 4  are controlled to be turned on. As a result, the potential V2(m, n) of the high-potential-side first holding capacitor C 1   a  is initially set to a potential (VGH−Vth) that is a potential V1(m, n) of the coupling point of the second pixel transistor TR 2  to the third pixel transistor TR 3  obtained by subtracting Vth of the second transistor TR 2  from the positive-polarity gate potential VGH. Accordingly, the third pixel transistor TR 3  is controlled to be turned on, and the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) is initially set to a potential (VGH−Vth−Vgs) obtained by subtracting the gate-source potential Vgs of the third pixel transistor TR 3  from the potential (VGH−Vth) that is the potential V2(m, n) of the high-potential-side first holding capacitor C 1   a  ( FIG.  22 B ). 
     When the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) before the write period, the second pixel transistor TR 2  is controlled to be turned off. When the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) in the subsequent write period, the first pixel transistor TR 1  is controlled to be turned on. As a result, the source drive signal (pixel signal) SIG(n) is supplied to the second holding capacitor C 2 , and the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) is charged with the potential of the source drive signal (pixel signal) SIG(n) (positive-polarity source potential VSH (at +15 V, for example) in the examples illustrated in  FIGS.  21 A and  21 B ). At this time, the potential V2(m, n) of the high-potential-side first holding capacitor C 1   a  is charged with a potential (SIG(n)+Vth) (VSH+Vth in the examples illustrated in  FIGS.  21 A and  21 B ) obtained by adding Vth of the third pixel transistor TR 3  to the potential of the source drive signal (pixel signal) SIG(n) (positive-polarity source potential VSH (at +15 V, for example) in the examples illustrated in  FIGS.  21 A and  21 B ) that charges the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) ( FIG.  22 C ). 
     When the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) and the third gate bus line (third scan line) SCL 3 ( m ) before the shift to the hold period, the first and the fourth pixel transistors TR 1  and TR 4  are controlled to be turned off. In the subsequent hold period, when the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ), a current flows through the second pixel transistor TR 2 , the third pixel transistor TR 3 , and the fifth pixel transistor TR 5 . However, in the state where Vpix=SIG(n) when the gate-source potential Vgs of the third pixel transistor TR 3  is at the same Vth as the gate-source potential Vgs of the fifth pixel transistor TR 5 , currents flowing through the second pixel transistor TR 2 , the third pixel transistor TR 3 , and the fifth pixel transistor TR 5  are balanced. Therefore, the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) is statically held in the state where the potential SIG(n) (positive-polarity source potential VSH in the examples illustrated in  FIGS.  21 A and  21 B ) is supplied ( FIG.  22 D ). 
     The following describes the case where the source drive signal (pixel signal) SIG(n) is set to the GND potential, with reference to  FIGS.  21 C and  21 D . The following describes differences from the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example) (refer to  FIGS.  21 A and  21 B ). 
     After the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) before the write period, and the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) in the subsequent write period, the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) is charged with the GND potential serving as the potential of the source drive signal (pixel signal) SIG(n). At this time, the potential V2(m, n) of the high-potential-side first holding capacitor C 1   a  is charged with a potential (GND+Vth) obtained by adding Vth of the third pixel transistor TR 3  to the GND potential serving as the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix). 
     Then, after the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) and the third gate bus line (third scan line) SCL 3 ( m ) before the shift to the hold period, and the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) in the subsequent hold period, the currents flowing through the second pixel transistor TR 2 , the third pixel transistor TR 3 , and the fifth pixel transistor TR 5  are balanced, so that the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) is statically held in the state of being supplied with the GND potential. 
     The following describes the case where the source drive signal (pixel signal) SIG(n) is set to the negative-polarity source potential VSL (at −15 V, for example), with reference to  FIGS.  21 E and  21 F . The following describes differences from the case where the source drive signal (pixel signal) SIG(n) is set to the positive-polarity source potential VSH (at +15 V, for example) (refer to  FIGS.  21 A and  21 B ) and the case where the source drive signal (pixel signal) SIG(n) is set to the GND potential (refer to  FIGS.  21 C and  21 D ). 
     After the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) before the write period, and the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) in the subsequent write period, the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) is charged with the negative-polarity source potential VSL serving as the potential of the source drive signal (pixel signal) SIG(n). At this time, the potential V2(m, n) of the high-potential-side first holding capacitor C 1   a  is charged with a potential (VSL+Vth) obtained by adding Vth of the third pixel transistor TR 3  to the negative-polarity source potential VSL serving as the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix). 
     Then, after the negative-polarity gate potential VGL (at −20 V, for example) is supplied to the first gate bus line (first scan line) SCL 1 ( m ) and the third gate bus line (third scan line) SCL 3 ( m ) before the shift to the hold period, and the positive-polarity gate potential VGH (at +20 V, for example) is supplied to the second gate bus line (second scan line) SCL 2 ( m ) in the subsequent hold period, the currents flowing through the second pixel transistor TR 2 , the third pixel transistor TR 3 , and the fifth pixel transistor TR 5  are balanced, so that the potential Vpix(m, n) of the second holding capacitor C 2  (pixel electrode Pix) is statically held in the state of being supplied with the negative-polarity source potential VSL. 
     In the present embodiment, the high-potential-side first holding capacitor C 1   a  only needs to have capacitance required to maintain the control state of the third transistor TR 3 . The low-potential-side first holding capacitor C 1   b  only needs to have capacitance required to maintain the control state of the fifth transistor TR 5 . Specifically, the high-potential-side first holding capacitor C 1   a  and the low-potential-side first holding capacitor C 1   b  have capacitance of approximately 0.1 pF, for example. 
     In the present embodiment, the potential of the second holding capacitor C 2 , that is, the potential Vpix(m, n) of the pixel electrode Pix is statically held in the state of being supplied with the potential SIG(n) obtained by subtracting Vth of the third pixel transistor TR 3  from the potential (SIG(n)+Vth) that has charged the high-potential-side first holding capacitor C 1   a  before the shift to the hold period. This operation can eliminate the influence of the potential drop α caused by the feedthrough that occurs when the first pixel transistor TR 1  is turned off, and thus, can restrain the reduction in display quality caused by the potential variation. 
     Each of the embodiments described above can provide a display device capable of restraining the reduction in image quality caused by the potential variation. 
     The components in the embodiments described above can be combined as appropriate. Other operational advantages accruing from the aspects described in the embodiments of the present disclosure that are obvious from the description herein, or that are conceivable as appropriate by those skilled in the art will naturally be understood as accruing from the embodiments of the present disclosure.