Patent Publication Number: US-10763869-B2

Title: Apparatus for digital frequency synthesizers and associated methods

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to the following U.S. Patent Applications: U.S. patent application Ser. No. 16/221,430, filed on Dec. 14, 2018, titled “Apparatus for Time-to-Digital Converters and Associated Methods”; and U.S. patent application Ser. No. 16/221,436, filed on Dec. 14, 2018, titled “Apparatus for Digitally Controlled Oscillators and Associated Methods”. 
     TECHNICAL FIELD 
     The disclosure relates generally to signal generation apparatus and methods and, more particularly, to apparatus including digital frequency synthesizers (DFSs), and associated methods. 
     BACKGROUND 
     With the increasing proliferation of wireless technology, such as Wi-Fi, Bluetooth, and mobile or wireless Internet of things (IoT) devices, more devices or systems incorporate RF circuitry, such as receivers and/or transmitters. To reduce the cost, size, and bill of materials, and to increase the reliability of such devices or systems, various circuits or functions have been integrated into integrated circuits (ICs). For example, ICs typically include receiver and/or transmitter circuitry. Typically, receiver and/or transmitter circuitry use one or more signals to perform a variety of functions, such as clocking circuitry (e.g., analog-to-digital converters (ADCs)), image reject calibration, mixing radio frequency (RF) signals to baseband or an intermediate frequency (IF), mixing a baseband or IF signal to RF signals, and the like. 
     The description in this section and any corresponding figure(s) are included as background information materials. The materials in this section should not be considered as an admission that such materials constitute prior art to the present patent application. 
     SUMMARY 
     A variety of apparatus and associated methods are contemplated according to exemplary embodiments. According to one exemplary embodiment, an apparatus includes a DFS. The DFS includes a time-to-digital converter (TDC) to provide an output signal that represents a phase difference between a reference signal and a feedback signal. The DFS further includes a scaling circuit, which has an adaptively changed gain, to provide a scaled residue signal used to cancel an effect of the residue signal in the DFS. 
     According to another exemplary embodiment, an apparatus includes a DFS, which includes a TDC to provide an output signal in response to a phase difference between a reference signal and a feedback signal, and a sigma-delta modulator (SDM) that provides an output signal and a residue signal. The DFS further includes a scaling circuit, which has an adaptively changed gain, to scale the residue signal to provide a scaled residue signal, and a subtracter to subtract the scaled residue signal from the output signal of the TDC to generate a difference signal. 
     According to another exemplary embodiment, a method of generating a signal having a desired frequency by using a DFS includes converting, by using a TDC, a phase difference between a reference signal and a feedback signal to a digital signal. The method further includes scaling, by using an adaptively adjusted gain, a residue signal from a SDM to generate a scaled signal, and subtracting a scaled version of a residue signal from the digital signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The appended drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope of the application or the claims. Persons of ordinary skill in the art will appreciate that the disclosed concepts lend themselves to other equally effective embodiments. In the drawings, the same numeral designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks. 
         FIGS. 1A and 1B  show circuit arrangements for DFSs according to exemplary embodiments. 
         FIG. 2  shows a circuit arrangement for a TDC according to an exemplary embodiment. 
         FIG. 3  shows a timing diagram for a TDC according to an exemplary embodiment. 
         FIG. 4  shows a circuit arrangement for a coarse TDC (C-TDC or CTDC) according to an exemplary embodiment. 
         FIG. 5A  shows a circuit arrangement for a conventional TDC. 
         FIG. 5B  shows a circuit arrangement for a fine TDC (F-TDC or FTDC) according to an exemplary embodiment. 
         FIG. 6  shows a circuit arrangement for a digital loop filter according to an exemplary embodiment. 
         FIG. 7  shows a diagram of transfer functions of various circuit blocks of a DFS according to an exemplary embodiment. 
         FIG. 8  shows a diagram of transfer functions of various circuit blocks of a DFS according to another exemplary embodiment. 
         FIG. 9  shows a diagram of transfer functions of various circuit blocks of a DFS according to another exemplary embodiment. 
         FIG. 10  shows a diagram pertaining to a first mode of operation of a sigma-delta modulator (SDM) according to an exemplary embodiment. 
         FIG. 11  shows a diagram pertaining to another mode of operation of an SDM according to an exemplary embodiment. 
         FIG. 12  shows a diagram pertaining to another mode of operation of an SDM according to an exemplary embodiment. 
         FIG. 13  shows a circuit arrangement for the first mode of operation of an SDM according to an exemplary embodiment. 
         FIG. 14  shows a circuit arrangement for another mode of operation of an SDM according to an exemplary embodiment. 
         FIG. 15  shows a circuit arrangement for another mode of operation of an SDM according to an exemplary embodiment. 
         FIG. 16  shows a circuit arrangement of a conventional inductor-capacitor (LC) oscillator. 
         FIG. 17  shows a circuit arrangement of a single-ended digitally controlled inductor-capacitor (LC) oscillator (DCO) according to an exemplary embodiment. 
         FIG. 18  shows a circuit arrangement for control of a single-ended DCO according to an exemplary embodiment. 
         FIG. 19  shows a circuit arrangement of a differential mode DCO according to an exemplary embodiment. 
         FIG. 20  shows a circuit arrangement of a differential mode DCO according to another exemplary embodiment. 
         FIG. 21  shows a circuit arrangement for an RF receiver, including a DFS, according to an exemplary embodiment. 
         FIG. 22  shows a circuit arrangement for an RF receiver, including a DFS, according to an exemplary embodiment. 
         FIG. 23  shows a circuit arrangement for an RF receiver, including a DFS, according to an exemplary embodiment. 
         FIG. 24  shows a circuit arrangement for an RF transmitter, including a DFS, according to an exemplary embodiment. 
         FIG. 25  shows a circuit arrangement for an RF communication system according to an exemplary embodiment. 
         FIG. 26  shows a circuit arrangement for an IC, including a receiver that includes one or more DFSs, according to an exemplary embodiment. 
         FIG. 27  shows a circuit arrangement for an IC, including a transmitter that includes one or more DFSs, according to an exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     One aspect of the disclosure relates to DFSs. DFSs according to various embodiments may be used in a variety of apparatus, subsystems, systems, modules, ICs, and the like. Without limitation, examples include RF receivers, RF transmitters, and RF transceivers. 
     DFSs are beneficial from an area viewpoint, since the loop filter (charge pump, capacitor, and resistor in an analog implementation) is implemented digitally. A fewer number of circuits include strictly analog or mixed-signal components in the DFS, such as the TDC and the DCO. A DFS offers lower area, higher immunity to semiconductor fabrication process variations, easier programmability, and more rapid migration to new technology nodes than the conventional analog approach to frequency synthesizers. 
     DFSs according to exemplary embodiments employ fractional-N phase-locked loops (PLLs) with residue cancellation. The fractional divider control is realized with a sigma-delta modulator (SDM). The residue cancellation is performed with a digital subtracter at the output of the TDC. In contrast, an analog PLL typically uses a DAC to implement residue cancellation. In the analog system, the linearity and gain of the residue DAC, phase detector, and charge pump have relatively high influence on the performance of analog synthesizers. In DFSs according to various embodiments, fewer parameters, such as the gain and linearity of the TDC, have relatively high impact on DFS performance. Additionally, the gain error of the TDC can be compensated completely in the digital domain. As described below in detail, a measurement of the RMS phase error after the residue cancellation is used to digitally adjust the gain of the residue path to increase or maximize the residue cancellation and minimize the RMS phase error of the DFS. 
     As noted above, another aspect of the disclosure relates to TDCs. With a digital loop filter, as used in exemplary embodiments, the phase error between the reference input signal (refclk) and the feedback clock or signal is converted to a digital output, and used to lock the DFS. This conversion of the error signal to a digital signal is performed in exemplary embodiments by the TDC. 
     TDCs according to exemplary embodiments can be arbitrarily long loops because the delay line is implemented as a ring. The signal propagates down the line, but can wrap around multiple times so that much longer total delays can be realized. Each time the signal wraps around, another latch in a string of latches is set to keep count of how many complete cycles are made. Such TDCs can yield relatively fine steps, e.g. 22 ps in a 40-nm semiconductor fabrication node, even though such fine resolution is used near the locked position. On the other hand, larger phase errors can tolerate a coarser TDC. Accordingly, in exemplary embodiments, a CTDC is used together with a fine TDC (FTDC or F-TDC), which can span the entire 2π range. A vernier technique, which is known to persons of ordinary skill in the art, may be used, as desired, as an enhancement to such TDCs. 
     TDCs according to various embodiments provide a number of benefits. First, they use fully digital circuitry, which results in lower size/circuit area, and increased simplicity. Second, the use of a wrapping around architecture, described below in detail, saves area and clock signal power. In addition, the coarse TDC (CTDC or C-TDC) in exemplary embodiments saves size/circuit area, reduces power consumption, and reduces or minimizes jitter accumulation (versus a design that uses all fine steps to cover the entire 2π range). 
     As noted above, another aspect of the disclosure relates to DCOs. With a digital loop filter, as is used in DFSs according to exemplary embodiments, the digital output of the loop filter (or a signal derived from the output signal of the digital loop filter) controls the oscillator, typically an LC oscillator. In exemplary embodiments, a digital-to-analog converter (DAC) is included in the LC voltage-controlled oscillator (VCO) circuitry. Controlling the VCO&#39;s frequency is achieved by varying the capacitance of the LC tank by using the output signal of the DAC. In other words, the digital output signal of the digital loop filter is used to digitally program the value of the capacitance of the LC tank and, hence, the VCO&#39;s output frequency. 
     Conventional techniques to digitally control the frequency of an LC oscillator cannot achieve fine frequency resolution by capacitor selection since capacitors would be relatively small and difficult to implement, as noted above. In a conventional implementation, the capacitors that are switched (to vary the capacitance of the LC tank) would be on the order of aF (i.e., 10 −15  F) range to obtain relatively fine frequency resolution. As described below in detail, the DCO topology according to exemplary embodiments uses two inductors and two sets of capacitors. Such a topology offers relatively wide tuning range and relatively fine frequency steps which, together make reasonable sizes of DCO frequency control words feasible with realizable capacitor size selection. 
     Alternative conventional approach utilize a sigma-delta modulator to drive a switchable capacitor. The ones density of the modulator is then used to implement a fractional value of the capacitor from 0 to 1 times the actual capacitance. The sigma-delta modulation to achieve the effective value of the fractional capacitor uses digital hardware that consumes power, uses additional circuit area, and can introduce switching spurs in the clock output. DCOs according to exemplary embodiments do not employ sigma-delta modulators and, in the locked condition, infrequently toggle a capacitor, that is effectively relatively small (relatively low capacitance), to maintain phase lock of the DFS. 
       FIG. 1A  shows a circuit arrangement for a DFS  10  according to an exemplary embodiment. DFS  10  employs a negative feedback loop. More specifically, as noted above, TDC  1005  converts to a digital value the phase difference between reference clock refclk and feedback clock fbclk, provided by multi-modulus divider (MMD)  1045 . MMD  1045  divides the nominal (or desired) frequency of the output signal of DFS  10  (labeled as “LO”) by a number that can be an integer or integer plus fraction. The negative feedback loop causes the MMD output signal to have the same average frequency as the frequency of the reference signal. The negative feedback loop acts to minimize the frequency and phase errors in the output signal of DFS  10 . 
     The output signal of TDC  1005  is provided to subtracter  1015 . An output signal of scaling circuit  1055  (described below) is provided to another input of subtracter  1015 . The difference between the two signals, i.e., the output signal of subtracter  1015 , is provided to digital loop filter  1020 , which performs digital filtering on the output signal of subtracter  1015 . In exemplary embodiments, digital loop filter  1020  may have a desired order, such as first-order filter, second-order filter, etc., as persons of ordinary skill in the art understand. The choice of filter order and the resulting circuitry for a given implementation depends on a variety of factors, such as design specifications, performance specifications, cost, IC or device area, available technology (e.g., semiconductor fabrication technology), target markets, target end-users, etc., as persons of ordinary skill in the art will understand. The filtered signal at the output of digital loop filter  1020  drives DCO  1025 . DCO  1025  includes a DAC  1030 , which converts the output of digital loop filter  1020  to program an array of capacitors in the VCO circuitry of DCO  1025 . 
     The output signal of DCO  1025  is provided to divider  1035 . Divider  1035  divides the frequency of its input signal by a desired value, such as 2 (hence the label “Div 2”) in the example shown, although other values may be used, as desired. The output signal of divider  1035  constitutes the output signal of DFS  10 , labeled as “LO.” The output signal of DFS  10  drives MMD  1045 , as noted above. 
     Note that, depending on the desired frequency of the output signal of DFS  10  and the available frequency of refclk, divider  1035  may be omitted in some embodiments, as persons of ordinary skill in the art will understand. Furthermore, note that MMD  1045  may be optional in some embodiments. Specifically, if the desired output frequency of DFS  10  is equal (or nearly equal in a practical implementation) to the reference frequency, MMD  1045  may be omitted, and the output signal of DFS  10  fed back to the input of TDC  1005 . 
     The integer and fractional values for DFS  10  are provided to SDM  1060  (e.g., if an overall value of 64.3 is desired, then the integer (N) and fractional (n) values provided to SDM  1060  are N=64 and n=0.3, respectively). In response, SDM  1060  generates an output signal sdbits, and a residue signal. The output signal sdbits is provided to delay circuit  1050 , which delays sdbits by a desired delay value. The delayed signal is used to control MMD  1045 , i.e., select the desired modulus for MMD  1045 . In exemplary embodiments, the delay provided by delay circuit  1050  is selected to match the delay of scaling circuit  1055 . 
     The residue signal from SDM  1060  is provided to scaling circuit  1055 . Scaling circuit  1055  multiplies the residue signal by a value selected from of ×1 through ×4 (or other values and/or numbers of values, as desired), which represent scaling values. The scaling values scale the residue value to match the gain of TDC  1005 . The output of scaling circuit  1055  is provided to subtracter  1015 , as noted above. 
     The output of scaling circuit  1055  is also provided to least-mean-square (LMS) adaptation circuit  1040 . The output of TDC  1005  is also provided to LMS adaptation circuit  1040 . The output of LMS adaptation circuit  1040  is used to select a scaling value in scaling circuit  1055 , e.g., one of ×1 through ×4 in the example shown. As a result, a feedback loop is formed around LMS adaptation circuit  1040  and scaling circuit  1055 , where in response to the levels of phase error at the output of TDC  1005  and the scaled residue from scaling circuit  1055 , LMS adaptation circuit  1040  causes changes in the gain (scaling factor) of scaling circuit  1055  to reduce or minimize the impact of residue on DFS  10 , i.e., perform residue cancellation. In other words, the level of phase error at the output of TDC  1005  is used to select a gain (scaling factor) of scaling circuit  1055  to cause cancellation of the residue or effect of residue. Viewed another way, the gain or scaling factor of scaling circuit  1055  is selected or set so as to reduce or cancel the phase error attributable to the residue signal. 
     Under ideal locked conditions, the phase error from TDC  1005  will be exactly equal to the value predicted by the scaled residue, i.e., the output of scaling circuit  1055 , i.e., the output of TDC  1005  equals the output of scaling circuit  1055 , which results in a zero output for subtracter  1015 . However, in a practical implementation, gain errors in TDC  1005  cause the output of subtracter  1015  to be finite, i.e., non-zero. LMS adaptation circuit  1040  tracks the magnitude of the phase error from TDC  1005  (the output signal of TDC  1005 ) versus the scaled residue (the output of scaling circuit  1055 ) and in a relatively slow manner (to allow the changes to settle in various circuitry) increments or decrements the gain of scaling circuit  1055  to drive the difference between the scaled residue and the TDC phase error to zero (or near zero, in a practical implementation). Thus, LMS adaptation circuit uses least-mean-square techniques combined with feedback to drive the output of subtracter  1015  to zero (or near zero) by changing the gain of scaling circuit  1055 . In this manner, scaling circuit  1055  operates as an adapting or adaptive scaling circuit. 
     In some embodiments, the incremental gain change occurs once per phase measurement (i.e., once per cycle of the reference clock, refclk), and is chosen to be relatively small, for instance, less than 1% of the nominal scaling factor or gain of scaling circuit  1055 . In some embodiments, the adaptation or adaptive functionality of LMS adaptation circuit  1040  can be enabled or disabled during DFS operation. For example, in some embodiments, to prevent divergence of the LMS adaptation, LMS adaptation circuit  1040  may be disabled if the TDC phase error (output of TDC  1005 ) is relatively large, indicating that the DFS has not yet achieved phase lock. 
     The output of subtracter  1015  is provided to residue error circuit  1010 . When the feedback loop in DFS  10  is locked, the input to digital loop filter  1020  should have a zero value. Residue error circuit  1010  generates an output signal that represents roughly the variance of the jitter (sum of absolute values of the outputs of subtracter  1015 , obtained, for example, by using an integrate/dump technique), i.e., a measure of the gain match between the residue signal from SDM  1060  and the gain of TDC  1005 . The jitter represents quantized jitter of SDM  1060 . The output signal of residue error circuit  1010  is provided to jitter monitor circuit  1017 . By examining the jitter variance at the output of subtracter  1015 , as measured by residue circuit  1010  and monitored by jitter monitor circuit  1017 , a measure of the quality of the reference signal and/or the convergence of the LMS adaptation function, described above, can be obtained. Monitoring by jitter monitor circuit  1017  can be used by DFS  10  (or another block or circuit in a system or apparatus that includes DFS  10 ) to determine potential degradation in the LO phase noise without making direct phase noise measurements. Additionally, if DFS  10  does not implement the LMS adaptation functionality, then the monitored jitter may be used to calibrate residue calibration circuit  1005 , as described below in connection with  FIG. 1B . 
       FIG. 1B  shows a circuit arrangement for a DFS  10  according to another exemplary embodiment. DFS  10  in  FIG. 1B  is similar to DFS  10  in  FIG. 1A , but uses a different technique for residue cancellation. More specifically, referring again to  FIG. 1B , the output of residue error circuit  1010  is provided to calibration circuit  1065 . Calibration circuit  1065  uses the output of residue error circuit  1010  (roughly the variance of the jitter) to select a scale or gain for scaling circuit  1055  so as to cause residue cancellation (reduce or cancel or eliminate the effect of the residue on DFS  10 ). In some embodiments, calibration circuit  1065  may use information or data included or contained in firmware, such as information determined during design, manufacture, test, and/or operation of DFS  10  or a device (e.g., an IC) that includes DFS  10 . Such information or data is subsequently used during operation of DFS  10  for residue cancellation. 
       FIG. 2  shows a circuit arrangement for TDC  1005  according to an exemplary embodiment. TDC  1005  includes C-TDC  1100  and F-TDC  1105  which, together, cover the entire 2π range of phase error values. C-TDC  1100  covers a range over entire cycles of the reference clock, refclk. F-TDC  1105  implements a range centered around the lock position, such as SDM  1060 &#39;s quantized jitter remains within the range. The signal refclk drives an input of C-TDC  1100 . A signal fbdel from delay circuit  1110  in F-TDC  1105  drives another input of C-TDC  1100 . The delay generated by delay circuit  1110  is one half of the range of values of the output of F-TDC  1105 . The output of C-TDC  1100  includes a signal ctdc (having bits 2 through 7 in the example shown, although other values can be used as desired), and an early/late signal. Both output signals of C-TDC  1100  are provided to control circuit  1115 . 
     The signal refclk also drives an input of F-TDC  1105 . The signal fbclk (see  FIG. 1A or 1B ) drives delay circuit  1110 . A delayed version of signal fbclk is provided as signal fbdel, as noted above. The output of F-TDC  1105  includes a signal ftdc (having bits 0 through 5 in the example shown, although other values can be used as desired), which is provided to control circuit  1115 . Using signals ctdc and ftdc and the early/late signal, control circuit  1115  generates the output signals of TDC  1005 , which include a tdc signal and a sign bit signal, i.e., signbit. The tdc signal has bits 0 through 11 in the example shown, although other values can be used as desired). 
     The operation of control circuit  1115  may be better understood by reference to  FIG. 3 , which shows a timing diagram for a TDC according to an exemplary embodiment. More specifically, the diagram shows the ranges of the C-TDC and F-TDC output signals as they relate to the refclk, fbdel, and fbclk signals. The range of values corresponding to early and late are also indicated. The locked condition (or the ideal condition) is indicated at the boundary between the early and late ranges. 
     Thus,  FIG. 3  illustrates that the C-TDC causes a number of phase steps in the range indicated as “C-TDC range” to bring the frequency of the fbclk signal closer to the frequency of the refclk. The F-TDC causes a number of additional phase steps in the range indicated as “F-TDC range” to bring the frequency of the fbclk signal closer to the frequency of the refclk signal and eventually into phase lock. Note that the “C-TDC range” straddles the “F-TDC range.” In other words, the “C-TDC range” is divided into two ranges, one range that is below or before or preceding the “F-TDC range” and another range that is above or after or succeeding the “F-TDC range.” Furthermore, note that in various embodiments the C-TDC phase step or steps (phase step(s) taken by C-TDC  1100 ) are larger than the F-TDC phase steps or steps (phase step(s) taken by C-TDC  1105 ), hence the labels “coarse” TDC (C-TDC) and “fine” TDC (F-TDC), respectively. In some embodiments, the ratio of the C-TDC phase step(s) to the F-TDC phase step(s) is an integer. In some embodiments, the ratio of the C-TDC phase step(s) to the F-TDC phase step(s) is non-integer. 
       FIG. 4  shows a circuit arrangement for C-TDC  1100  according to an exemplary embodiment. The refclk and fbdel signals drive the D and clock inputs of D-type flip-flop  1210 . The output of flip-flop  1210  constitutes the early/late signal, described above (a binary logic value of 0 indicates that the fbdel signal is early, whereas a binary logic value of 1 indicates that the fbdel signal is late). The refclk and fbdel signals also drive the inputs of control circuit  1205 . In response, control circuit  1205  generates a reset signal, which is used to reset synchronous counter  1220  to an initial count value. Control circuit  1205  also generates an enable signal for oscillator  1215 . In response to the enable signal (i.e., when the enable signal is asserted), oscillator  1215  provides clock signals to synchronous counter  1220 . 
     More specifically, control circuit  1205  enables oscillator  1215  at the rising edge occurrence of refclk (or fbdel). Control circuit  1205  halts (de-asserts the enable signal) oscillator  1215  at the rising edge of fbdel (or refclk). The output of synchronous counter  1220  constitutes the ctdc signal, along with the early/late signal. 
       FIG. 5A  shows a circuit arrangement for a conventional TDC. The TDC includes a chain of delay circuits fed by an input signal (e.g., fbclk), a chain of flip-flops fed by a clock signal (e.g., refclk), and a thermometer to binary encoder. The operation of the circuit is known to persons of ordinary skill in the art. In the conventional approach to implementing the TDC shown in  FIG. 5A , the phase difference (or time difference) between two clock signals can be measured and quantized to a discrete value by passing one clock signal (CLK1) through a delay line and using the second clock signal (CLK2) to control the sampling action of the flip-flops. In essence, the transition in the second clock signal takes a snapshot of the delay element outputs and locates how far into the delay line the first clock signal has propagated. This position can then be encoded into a binary output that represents the relative time delay between the two clock signals. If a relatively large delay range is desired, the straightforward approach is simply to cascade more delay stages and add more flip-flops. Doing so, however, increases the chip area, entails driving more flip-flops by the second clock signal with corresponding extra capacitive loading increased power consumption, and more complicated clock skew management as the second clock signal is distributed to more flip-flops. 
     Instead of extending the length of the delay line and associated flip-flops, one can create a re-circulating delay line and associated flip-flops. Conceptually, when the first clock transition occurs, it is launched into a first delay element in a delay circuit or delay line that includes a number of delay cells or elements. The first clock signal propagates through the delay line and when it reaches the last delay element, an inverted version of the output signal of the last delay element is fed into the first delay element and, simultaneously, a wrap counter records that one round trip has occurred through the delay elements. The first clock signal continues to propagate and wrap around the delay line until the second clock simultaneously samples the wrap count value and all the states of the delay elements. An encoder circuit then combines the flip-flop samples and produces a binary output.  FIG. 5B  shows one implementation of this concept, as described below in detail. 
     More specifically, a single-ended embodiment of a re-circulating F-TDC is shown in  FIG. 5B . Initially, a multiplexer (MUX) is set to one position, say, position “0,” and the first clock signal (e.g., fbclk) transition enters the first delay cell. When the first clock signal reaches the last delay cell, the output signal of that delay cell signal is inverted, and the MUX is automatically reconfigured to select the re-circulated signal with another position, say, position “1.” The MUX stays in this position until a second clock signal (e.g., refclk) samples the outputs of the delay cells and the wrap counter. After sampling is completed, a reset signal clears the wrap counter, sets the MUX to position “0,” and sets all delay elements to their reset level (e.g., “0”). 
     Referring to  FIG. 5B , reference signal refclk drives the clock inputs of D-type flip-flops  1275 , which are coupled in a cascade fashion or chain. The outputs of flip-flops  1275  are provided to encoder logic circuit  1270 . The output of encoder logic circuit  1270  constitutes the output of F-TDC  1105 , i.e., the ftdc signal (see  FIG. 2 ). 
     Referring again to  FIG. 5B , the D inputs of flip-flops  1275  are driven by the output signal of MUX  1255 , and delayed versions of that signal. More specifically, the output signal of MUX  1255  is provided to the D input of the first flip-flop  1275 . The outputs of a set of delay circuits, coupled in a cascade or chain fashion, drive the respective D inputs of the remaining flip-flops  1275 . The output of the last delay circuit  1110  drives an input of inverter  1250 . The output of inverter  1250  drives one input of MUX  1255 , and also a clock input of wrap counter  1265 . In response, wrap counter  1265  counts the number of times a signal has propagated through delay circuits  1110 . The output of wrap counter  1265  is provided to encoder logic circuit  1270 . Encoder logic circuit  1270  combines the wrap count value (output of wrap counter  1265 ) with the states (Q outputs) of flip-flops  1275  to form a signed binary output word. The states of flip-flops  1275  are thermometer-to-binary encoded by encoder logic circuit  1270  if the wrap count is even. If the wrap count is odd, however, then the states of flip-flops  1275  are inverted in encoder logic circuit  1270  prior to the thermometer-to-binary conversion in encoder logic circuit  1270 . 
     The signal fbclk drives a second input of MUX  1255 . The select signal of MUX  1255  is provided by MUX control circuit  1260 . If the select signal of MUX  1255  has a binary logic 0 value, signal fbclk is provided as the output signal of MUX  1255 . Conversely, if the select signal has a binary logic 1 value, the output signal of inverter  1250  is provided as the output signal of MUX  1255 . MUX control circuit  1260  generates the select signal using the fbclk signal, the refclk signal, and the output signal of inverter  1250 . 
     In exemplary embodiments, such as the embodiment shown in  FIG. 5B , F-TDC  1105  is of a re-circulating type or operates in a re-circulating manner. The re-circulating operation of F-TDC  1105 , including the operation of MUX control circuit  1260 , occurs as follows: Initially, F-TDC  1105  is reset with the falling edge of refclk, and MUX  1255  provides the fbclk signal as the output signal (i.e., the select signal has a binary logic 0 value). Initially, the fbclk clock signal propagates through the delay blocks in delay circuit  1110  (all delay line outputs sequentially change from 0 to 1). When the signal reaches the last delay block, the following occurs: (a) inverter  1250  provides binary logic 0 to MUX  1255 ; (b) wrap counter  1265  increments to indicate that one trip through delay circuit  1110  has occurred; and (c) MUX  1255  switches to position 1 (provides the output signal of inverter  1250 ), and remains in that position until F-TDC  1105  is reset. The output of MUX  1255  then propagates a binary logic zero through delay circuit  1110 . If a second wrap condition occurs, then wrap counter  1265  increments, and MUX  1255  propagates a binary logic 1 value through delay circuit  1110 . Further wrapping causes wrap counter  1265  to increment, and binary logic values of 1 and 0 alternately propagate through delay circuit  1110 . 
     On the rising edge of refclk, all of flip-flops  1275  and the output value of wrap counter  1265  are sampled. Encoder logic circuit  1270  encodes the output value (or count) of wrap counter  1265  and the output signals of flip-flops  1275 , and produces a binary word that represents the time (or phase difference) between the two clock edges (fbclk and refclk). On the falling edge of refclk, the entire circuitry in F-TDC  1105  is reset, and the process continues as described above. 
       FIG. 6  shows a circuit arrangement for digital loop filter  1020  according to an exemplary embodiment. The input signal to loop filter  1020  consists of a signal “a” (which has bits 0 through 15, i.e., a 16-bit signal, although other values may be used, as desired), and the signbit signal (i.e., a signal that indicates the sign of the “a” signal), for instance, as provided by TDC  1005  (see  FIG. 2 ). Referring again to  FIG. 6 , the signal “a” and the “signbit” signal are provided to a one&#39;s complement circuit  1305 . The output of one&#39;s complement circuit  1305  drives a first input of adder  1310 , while the signbit signal constitutes the carry-in (ci) input of adder  1310 . An output of register  1325 , i.e., signal yout (which, in the example shown, as bits 0 through 15, although other sizes or values may be used, as desired) drives a second input of adder  1310 . 
     The sum of the inputs to adder  1310  is provided as signal xout which, in the example shown, has bits 0 through 15, although other sizes or values may be used, as desired. Signal xout drives the input of register  1325 , and signal refclk clocks register  1325 . The output of one&#39;s complement circuit  1305  is scaled by scaling circuit  1315 , which scales the signal by 2 N . The output signal of scaling circuit  1315  constitutes the proportional path signal, and is provided to adder  1320 . The signbit signal is provided as carry-in (ci) to adder  1320 . The signal xout (output of adder  1310 ) constitutes the integral path signal, and is also provided to adder  1320 . The sum output of adder  1320  drives the input of register  1330 , which is clocked by signal refclk. The output of register  1330  constitutes a digital control signal that is used to control DCO  1025  (see  FIG. 1A or 1B ). 
     Referring again to  FIG. 6 , a control circuit (not shown) detects overflow and underflow situations, and properly sets the output of register  1330 , as appropriate. More specifically, if the carry out signal for adder  1320  has a logic 1 signal and the carry in signal for adder  1320  has a binary logic 0 value, an overflow condition exists. Accordingly, the output of register  1330  is set to all ones (0xFFFF for the example shown). Conversely, if the carry in of adder  1320  has a binary logic 1 value, the previous most-significant bit (MSB) of the output of adder  1320  has a binary 0 logic value, and the new MSB of the output of adder  1320  has a binary logic value of 1, then an underflow condition (negative number) is detected. Accordingly, the output of register  1330  is set to all zeros (0x0000 for the example shown). 
       FIG. 7  shows a diagram of transfer functions of various circuit blocks of a DFS according to an exemplary embodiment. The transfer functions may be used to derive an overall transfer function for DFS  10 . In the exemplary embodiment shown, block  1375  represents the transfer function of TDC  1005 , block  1378  represents the integral path of the loop filter (digital loop filter  1020  in  FIG. 1 ), block  1380  represents the proportional path of the loop filter, block  1382  represents a summer or adder, block  1385  represents the VCO or DCO, and block  1388  represents the feedback-path circuitry. Using the transfer functions shown, the overall transfer function may be represented as: 
                 Θ   O       Θ   R       =         k   P     ⁢     k   D     ⁢     K   O     ⁢     z     -   1       ⁢     ⌊       (     1   +       k   I       k   P         )     -     z     -   1         ⌋         1   +       ⌊           (       k   I     +     k   P       )     ⁢     k   D     ⁢     K   O       N     -   2     ⌋     ⁢     z     -   1         +       ⌊     1   -         k   P     ⁢     k   D     ⁢     K   O       N       ⌋     ⁢     z     -   2                       where               K   O     =     2   ⁢   π   ⁢           ⁢     K   vco     ⁢     T   ref                 and               k   D     =       1     2   ⁢   π       ⁢       T   ref       Δ   TDC               
and where K vco  represents the DCO gain, K o  represents the DCO phase change, k D  represents the TDC gain, k P  represents the proportional path gain, k I  represents the integral path gain, T ref  represents the period of the reference clock signal, refclk (e.g., 26 ns in the BLE example), and Δ TDC  is the nominal phase step size of the F-TDC  1105  (e.g., 22 ps in the BLE example).
 
       FIG. 8  shows a diagram of transfer functions of various circuit blocks of a DFS according to another exemplary embodiment. More specifically, the figure shows the transfer functions of various blocks in a DFS that includes a SDM and residue cancellation (e.g., as shown in  FIG. 1A or 1B ). Referring again to  FIG. 8 , some of the blocks are the same as in  FIG. 7 , i.e.,  1375 ,  1378 ,  1380 ,  1382 , and  1385 . Block  1400  represents the MMD, block  1405  represents the SDM, and blocks  1408  and  1410  represent the processing of the SDM error output to produce the residue. The residue is scaled by block  1412 . Note that the LMS adaptation technique, which adapts the k DD  gain to compensate for the TDC gain variation with process and temperature, is not shown in this diagram to facilitate presentation. Blocks  1405 ,  1408 , and  1410  correspond to SDM  1060  and delay circuit  1050  in  FIGS. 1A and 1B . Using the transfer functions shown in  FIG. 8 , the overall transfer function may be represented as: 
                 Θ   O       Θ   R       =         k   P     ⁢     k   D     ⁢     K   O     ⁢     z     -   1       ⁢     ⌊       (     1   +       k   I       k   P         )     -     z     -   1         ⌋         1   +       ⌊           (       k   I     +     k   P       )     ⁢     k   D     ⁢     K   O       N     -   2     ⌋     ⁢     z     -   1         +       ⌊     1   -         k   P     ⁢     k   D     ⁢     K   O       N       ⌋     ⁢     z     -   2                   
Assuming k I =1; k P =32, 64, and 128; and refclk frequency of 38.4 MHz (e.g., an implementation of a DFS for a Bluetooth Low-Energy (BLE) application), the VCO or DCO frequency range (2·N·refclk) has a range of 4200-5700 MHz, which implies N values of 54-74. Using those values, and assuming K vco  is about 5 kHz/LSB, and given the above formula for k D , a TDC step size of 22.2 ps should be used.
 
       FIG. 9  shows a diagram of transfer functions of various circuit blocks of a DFS according to another exemplary embodiment. The DFS in this example uses a third-order PLL, as indicated by the addition of block  1390  (compare  FIGS. 7 and 9 ). Block  1390  is a first-order low-pass filter that is used to reduce the high-frequency ripple from the output of summing block  1382  to lower the resulting phase noise and spurs at the DCO output, i.e., block  1385 . The parameter β is varied to change the corner frequency of the low-pass filter, i.e., block  1390 . In  FIG. 9 , block  1378  implements the integral path, block  1380  implements the proportional path, and the two are combined with by summing block  1382 . Blocks  1378 ,  1380 ,  1382 , and  1390  as a group are represented as the loop filter, i.e., digital loop filter  1020  in  FIGS. 1A and 1B . Using the transfer functions shown, the overall transfer function may be represented as: 
     
       
         
           
             
               
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     In exemplary embodiments, second-order or third-order SDMs may be used, which may have 2, 3, 4, or other values of the number of output levels. As persons of ordinary skill in the art will understand, a number of trade-offs are made in the selection of the design and performance parameters of SDM  1060  in  FIGS. 1A and 1B . The choice of such parameters and the resulting circuitry for a given implementation depends on a variety of factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology, target markets, target end-users, etc. 
     For example, using a third-order SDM results in lower quantization noise below 6.7 MHz (e.g., using the BLE example above), but digital loop filter  1020  would use an extra pole in its transfer function to reject higher-frequency levels of quantization noise. Using a second-order SDM, on the other hand, would allow for a simpler and wider band-width digital loop filter  1020 . With respect to output levels, a higher number of output levels, say, 4, would accommodate relatively large dither rejection from SDM  1060 . Using a lower number, say, 2, on the other hand, would reduce the range of FTDC  1105  (see  FIG. 2 ), which results in reduced power consumption, reduced circuit area/size, and reduced accumulated jitter. 
     As an illustration, and merely by way of example, for an embodiment that accommodates the BLE parameters and specifications, a second-order SDM  1060  with a 1-bit output may be used. Such a choice would accommodate relatively high bandwidth for transmit modulation, would reduce or minimize toggling steps of MMD  1045  (see  FIG. 1A or 1B ), and would reduce or minimize the range of FTDC  1105  (as opposed to multi-bit SDMs). Such an SDM would have three modes, depending on the values of n (the fractional divide parameter of the DFS). The three modes are as follows:
         Mode 0: 0.25&lt;n&lt;0.75   Mode 1: n≤0.25   Mode 2: n≥0.75
 
Using the above modes keeps the fractional part (n) relatively close to the 50% level in order to reduce or minimize spurs and tonal outputs in the output signal (sdbits in  FIG. 1A  or  1 B) of SDM  1060 .  FIG. 10  shows operation in Mode 0. In this mode, output signal sdbits of SDM  1060  toggle between the values N and N+1.  FIG. 11  shows operation in Mode 1. In this mode, output signal sdbits of SDM  1060  toggle between the values N−1 and N+1.  FIG. 12  shows operation in Mode 2. In this mode, output signal sdbits of SDM  1060  toggle between the values N and N+2.
       

     In order to implement modes 0, 1, and 2, some changes are made to the circuitry and/or operating parameters of SDM  1060 .  FIG. 13  shows a circuit arrangement for an SDM  1060 , operating in mode 0, according to an exemplary embodiment. As noted above, SDM  1060  receives the values of n and N as input signals. The fractional value (n) is provided to adder  1060 A, which receives at a second input the constant −0.5. The sum at the output of adder  1060 A drives an input of adder  1060 B, while a second input of adder  1060 B receives the output of 1-bit digital-to-digital converter (DDC)  1060 K, multiplied by −0.5 by scaling circuit  1060 M. DDC  1060 K generates at its output the value of +1 or −1, depending on the value of its input signal. 
     The sum at the output of adder  1060 B drives the input of integrator  1060 C. The output of integrator  1060 C constitutes the residue output of SDM  1060 , and is also provided to adder  1060 D. The output of DDC  1060 K, multiplied by −1.0 by scaling circuit  1060 L, drives another input of adder  1060 D. The sum at the output adder  1060 D drives the input of integrator  1060 F, the output of which drives one input of adder  1060 G. Another input of adder  1060 G is driven by the output of pseudo-random binary sequence (PRBS) dither circuit  1060 E (used to break up periodic cycles or limit cycles in SDM  1060  to eliminate or reduce spurs or make the input signal of quantizer  1060 H appear more noise-like), as persons of ordinary skill in the art will understand). 
     The sum at the output of adder  1060 G drives the input of quantizer  1060 H (implemented, for example, by using a comparator, as persons of ordinary skill in the art will understand). The output of quantizer  1060 H is provided to DDC  1060 K as an input signal. The sum at the output of adder  1060 G is quantized to a single bit by quantizer  1060 H and then provided to delay circuit  1060 I. The delayed output of delay circuit  1060 I drives one input of adder  1060 J. The input value N drives a second input of adder  1060 J. The sum at the output of adder  1060 J is provided as the output of SDM  1060  and is used to drive MMD  1045 . In the case shown, i.e., mode 0, the output toggles between N and N+1, as noted above. 
       FIG. 14  shows a circuit arrangement for an SDM  1060 , operating in mode 1, according to an exemplary embodiment. In this mode, a scaling circuit  1060 N, with a gain of 0.5, is driven by input signal n, the output of which drives the input of adder  1060 A. The second input of adder  1060 A is driven by the value 0. In addition, a scaling circuit  1060 P scales the output of integrator  1060 C by 2.0, and the resulting scaled value is provided as the residue output. A scaling circuit  1060 Q scales the output of delay circuit  1060 I by 2.0 and provides the resulting value to adder  1060 J. A third input of adder  1060 J is provided the value of −1.0. 
       FIG. 15  shows a circuit arrangement for an SDM  1060 , operating in mode 2, according to an exemplary embodiment. In this mode, scaling circuit  1060 N has a gain of 0.5, as was the case with mode 1. The second input of adder  1060 A, however, is driven by the value −0.5. Similar to mode 1, scaling circuit  1060 P scales the output of integrator  1060 C by 2.0, and the resulting scaled value is provided as the residue output. Also, similar to mode 1, scaling circuit  1060 Q scales the output of delay circuit  1060 I by 2.0 and provides the resulting value to adder  1060 J. The third input of adder  1060 J is provided the value of 0. 
     As noted above, one aspect of the disclosure relates to DCOs. In exemplary embodiments, a DAC is included in the DCO (see  FIG. 1A or 1B ) to program (or set or configure or adjust) the effective capacitance of the LC tank used in the VCO.  FIG. 16  shows a circuit arrangement of a conventional LC oscillator  1600 , which includes inductor L, capacitor C, and back-to-back inverters  1605  and  1610 . Considering this simple LC tank oscillator in the context of the BLE example mentioned above, BLE modulation uses a frequency deviation of ±250 kHz, or about ±102 ppm. Assuming that 6 bits are used to control the value of capacitor C, a change in the value of the least-significant bit (LSB) would cause about a 7.8 kHz frequency change, i.e., about 3.2 ppm. A 3.2 ppm change in frequency means a ±6.4 ppm in capacitance. Assuming a nominal value of 1 pF for capacitor C, a ±6.4 ppm in capacitance implies a ±6.4 aF step, which is likely not feasible with current fabrication technologies. 
     DCOs according to exemplary embodiments use a different topology than do conventional VCOs (see  FIG. 16 ).  FIG. 17  shows a circuit arrangement of a single-ended DCO  1025  according to an exemplary embodiment (DAC  1030  is not shown). DCO  1025  includes capacitor C. In lieu of a simple inductor, however, DCO  1025  uses an inductor L coupled in series with capacitor C x  to realize an effective inductance L eff . In other words, the combination of inductor L and capacitor C x  provides an effective inductance of L eff  which, together with capacitor C, forms an LC tank. Inverter  1605  is back-to-back coupled to inverter  1610 . Inverter  1605  and inverter  1610  are coupled in parallel with capacitor C and with the series-coupled inductor L and capacitor C x . 
     By changing the values of capacitors C and C x , the frequency of oscillation of the LC tank can be changed. As noted above, the topology shown offers relatively wide tuning range and relatively fine frequency steps which, together make reasonable sizes of DAC control words for capacitor C x  feasible with realizable capacitor size selection. In DCO  1025 , the value of L eff  may be expressed as: 
               L   eff     ≃       L   ⁡     (     1   -     1       ω   o   2     ⁢     LC   x           )       ⁢           ⁢   or                   L   eff     ≃     L   ⁡     (     1   -     C     C   x         )             
The step change in capacitor C x  may be expressed as:
 
               Δ   ⁢           ⁢     C   x       =         Δ   ⁢           ⁢     L   eff         L   eff       ⁢       C   x     C     ⁢     (       C   x     -   C     )             
The step change in the output frequency is given by:
 
                 Δ   ⁢           ⁢   f       f   0       =         -   1     2     ⁢       Δ   ⁢           ⁢     L   eff         L   eff               
The step change in capacitor C x  may therefore be expressed as:
 
               Δ   ⁢           ⁢     C   x       =       -   2     ⁢       Δ   ⁢           ⁢   f       f   0       ⁢       C   x     C     ⁢     (       C   x     -   C     )             
Assuming that capacitor C has a capacitance of 1 pF and capacitor C x  has a capacitance of 20 pF, ΔC x  would have a value of about 1.52 fF, which is about 380 times larger than the corresponding step change in the circuit shown in  FIG. 17 . The DCO topology shown in  FIG. 17  would therefore be easier to implement.
 
       FIG. 18  shows a circuit arrangement for controlling the frequency of single-ended DCO  1025  according to an exemplary embodiment. More specifically, the figure shows DAC  1030  receiving a set of control signals (from digital loop filter  1020 , as shown in  FIG. 1A or 1B ), and using the set of control signals to vary the capacitances of capacitors C and C x . DAC  1030  can drive analog voltages to control or vary the capacitances of capacitors C and C x , assuming those capacitors are implemented as varactors. Alternatively, rather than using DAC  1030 , a control circuit that includes logic circuitry and switches to program discrete capacitance values of capacitors C and C x . In general, capacitors C and C x  can be realized with a combination of programmable (discrete capacitance step changes) and varactor capacitors in a number of ways, as persons of ordinary skill in the art will understand. The choice of realization for a given implementation depends on a variety of factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology, target markets, target end-users, etc. 
     Using the BLE example discussed above, assuming a frequency tuning range of ±10% (±100,000 ppm) and a DCO output signal frequency resolution (or step) of about 3.2 ppm, DAC  1030  would have to use about 16 bits of signals in the set of control signals. The total number of bits is partitioned between C and C x , i.e., some of the bits are used to vary the capacitance of capacitor C, and the remaining bits in the set of control bits are used to vary the capacitance of capacitor C x . 
     In exemplary embodiments, a discontinuity may exist in the overall capacitance provided by capacitors C and C x . Given that assumption, the capacitance values of capacitors C and C x  are designed to overlap (e.g., using capacitance values of capacitors C and C x  that are non-radix  2 ). In addition, capacitor C x  may be designed so that no fractional divide (as realized by MMD  1045  (see  FIG. 1A or 1B )) value of the fractional value (n) causes a change in capacitor C. Thus, for the BLE example, changes in capacitor C x  should cover the frequency range of at least 38.4 MHz out of 2.45 GHz, or 15,600 ppm. A 2 ppm resolution in the capacitance of capacitor C x  implies 7,800 steps in capacitance value. Thus, 13 bits would be allocated to varying the capacitance value of capacitor C x . An additional four bits would be allocated to varying the capacitance value of capacitor C.  FIG. 18  shows this configuration. 
     Note, however, that the choice of the total number of bits in the set of control bits, the allocation of bits to capacitor C and capacitor C x , and other such parameters and the resulting circuitry for a given implementation depends on a variety of factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology, target markets, target end-users, etc. Thus, the example shown in  FIG. 18  is merely illustrative, and other DCO realizations may be used, as desired. 
     Instead of single-ended DCOs, in some applications differential mode DCOs may be used, as desired.  FIG. 19  shows a circuit arrangement of a differential mode DCO  1025  according to an exemplary embodiment (DAC  1030  is not shown). In this topology, inductor L is realized by using two inductors L a  and L b , coupled in series, as shown. In addition, capacitor C x  is realized by using three capacitors coupled in a Π-configuration (or “pi-configuration” to denote the capital Greek letter pi), which includes capacitors C xa , C xb , and C xc . In the embodiment shown, capacitor C xb  has a fixed value, and the capacitances of capacitors C xa  and C xc  are varied by DAC  1030  (not shown), as described above. Note that the resistors represent the parasitic series resistances of inductors L a  and L b  and/or the effective series resistance of capacitors that realize capacitor C x  to model passive losses in DCO  1025 . In some situations, the resistors have relatively small values, and may be omitted from the circuit and/or design calculations, as persons of ordinary skill in the art will understand. 
     For the BLE example discussed above, the components have the values shown in  FIG. 19 . Note the dot-convention of the two inductors which, conceptually denotes the direction in which the turns of conductor in the inductors are “wound” (or realized in some manner in an IC, etc.). For the topology in  FIG. 19 , the dot-convention denotes that the turns of conductor in inductor L a  are “wound” in the opposite direction of the turns of conductor in inductor L b  (e.g., clockwise versus counterclockwise). Using this configuration, the effective inductance of inductor L a , L a-effective , may be represented as:
 
 L   a-effective =( L   a   −M )= L   a (1− k ),
 
where M represents the mutual inductance between inductors L a  and L b , and where k represents the coupling coefficient between inductors L a  and L b . Similarly, for inductor L b , the effective inductance of inductor L b , L b-effective , may be represented as
 
 L   b-effective =( L   b   −M )= L   b (1− k ).
 
     The dot-convention for inductors L a  and L b  may be changed to arrive an alternative exemplary embodiment for a differential mode DCO.  FIG. 20  shows a circuit arrangement for that topology (DAC  1030  is not shown). The circuit configuration is similar to the embodiment shown in  FIG. 19 , except that the dot-convention for inductors L a  and L b  signifies that the turns of conductor in inductor L a  are “wound” in the same direction as the turns of conductor in inductor L b . Using this configuration, the effective inductances of inductors L a  and L b  may be represented, respectively, as:
 
 L   a-effective =( L   a   +M )= L   a (1+ k ),
 
and
 
 L   b-effective =( L   b   +M )= L   b (1+ k ).
 
     From the above description, one may note that the inductance L in the DCO topology shown in  FIG. 19  has a lower value than it does in the DCO topology shown in  FIG. 20 . On the other hand, the DCO topology shown in  FIG. 20  is more immune to interfering signals that would appear as a common-mode signal to the circuitry in the VCO. The above factors may be considered in choosing the topology in  FIG. 19  versus the topology in  FIG. 20 . In addition or instead, however, the choice of topology may be predicated on other parameters or factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology, target markets, target end-users, etc., for a given implementation or situation. 
     As noted above, without limitation, DFSs (including TDCs and/or DCOs) according to exemplary embodiments may be used in a variety of applications. Examples include RF receivers, RF transmitters, and RF transceivers.  FIG. 21  shows a circuit arrangement for an RF receiver  100 , including DFS  10 , according to an exemplary embodiment. Receiver  100  receives RF signals via antenna  105 . The RF signals feed an input of low noise amplifier (LNA)  120 . LNA  120  provides low-noise amplification of the RF signals, and provides amplified RF signals to mixer  130 . 
     Mixer  130  performs frequency translation or shifting of the RF signals, using a reference or local oscillator (LO) frequency provided by LO  125 . For example, in some embodiments, mixer  30  translates the RF signal frequencies to baseband frequencies. As another example, in some embodiments, mixer  30  translates the RF signal frequencies to an intermediate frequency (IF). 
     Mixer  130  provides the translated output signal as a set of two signals, an in-phase (I) signal, and a quadrature (Q) signal. The I and Q signals are analog time-domain signals. Analog-to-digital converter (ADC)  135  converts the I and Q signals to digital I and Q signals. In exemplary embodiments, ADC  135  may use a variety of signal conversion techniques. For example, in some embodiments, ADC  135  may use delta-sigma (or sometimes called sigma-delta) analog-to-digital conversion. 
     ADC  135  provides the digital I and Q signals to signal processing circuitry  140 . Generally speaking, signal processing circuitry  140  performs processing on the digital I and Q signals, for example, digital signal processing (DSP). Signal processing circuitry  140  provides information, such as the demodulated data, to data processing circuitry  155  via link  150 . Data processing circuitry  155  may perform a variety of functions (e.g., logic, arithmetic, etc.). For example, data processing circuitry  155  may use the demodulated data in a program, routine, or algorithm (whether in software, firmware, hardware, or a combination) to perform desired control or data processing tasks. 
     In some embodiments, data processing circuitry  155  may perform control of other circuitry, sub-system, or systems (not shown). In some embodiments, data processing circuitry  155  may provide the data (after processing, as desired, for example, filtering) to another circuit (not shown), such as a transducer, display, etc. 
     In exemplary embodiments, link  150  may take a variety of forms. For example, in some embodiments, link  150  may constitute a number of conductors or coupling mechanisms, such as wires, cables, printed circuit board (PCB) traces, etc. Through link  150 , signal processing circuitry  140  and data processing circuitry  155  may exchange information, such as the demodulated data, control information or signals, status signals, etc., as desired. 
     Receiver  100  includes image reject (IR) calibration circuitry  165  that may be used to perform image reject calibration, as mentioned above. Receiver  100  further includes controller  160 . Controller  160  uses an output signal  160 A to control the operation of IR calibration circuitry  165 . Controller  160  further uses output signal  160 B to control the operation of DFS  10 , e.g., cause DFS  10  to provide an output signal  10 A as a test tone to the receiver. The test tone is typically injected into the receive path circuitry at a strategic location. In the exemplary embodiment shown in  FIG. 21 , the test tone output by DFS  10  is applied at the input of low-noise amplifier (LNA)  120 . IR calibration circuitry  165  residing after analog-to-digital converter (ADC)  135  utilizes the LMS technique (or an alternate the technique) to calibrate the image rejection of the receive path circuitry . . . . 
     As noted above, DFSs according to various embodiments may be used to clock ADC  135 .  FIG. 22  shows such an arrangement. In this scenario, DFS  10  provides output signal  10 A to ADC  135  in response to control signal  160 B from controller  160 . ADC  135  uses output signal  10 A of DFS  10  as a clock signal in order to perform analog-to-digital conversion. 
     As further noted above, DFSs according to various embodiments may be used to perform mixing operations.  FIG. 23  shows such an arrangement. In this embodiment, LO  125  (see  FIGS. 4-5 ) is omitted. Instead, output signal  10 A of DFS  10  is used as an LO signal. DFS  10  provides output signal  10 A to ADC  135  in response to control signal  160 B from controller  160 . Output signal  10 A is used by mixer  130  to mix an RF signal with output signal  10 A in order to generate the I and Q (in-phase and quadrature) signals that are provided to ADC  135 . 
     As noted above, DFSs according to various embodiments may be used in RF transmitters.  FIG. 24  shows a circuit arrangement for an RF transmitter (TX)  200 , including DFS  10 , according to an exemplary embodiment. Data processing circuitry  155  provides a digital signal to digital-to-analog converter (DAC)  202 . DAC  202  converts the digital signal to an analog signal and provides the analog signal to mixer  204 . 
     In response to control signal  160 B from controller  160 , DFS  10  generates output signal  10 A with a desired frequency (typically in the RF range). Mixer  204  mixes the output signal of DAC  202  with output signal  10 A of DFS  10 . The resulting output signal  204 A of mixer  204  may be provided to a power amplifier (not shown) or be further processed as part of the operations of transmitter  200 . 
     Note that RF receiver  100  and RF transmitter  200  shown in the figures and described above constitute mere examples. As persons of ordinary skill in the art will understand, DFSs according to various embodiments may be used in a variety of RF receivers (e.g., direct conversion, low-intermediate-frequency (low-IF), etc.) and RF transmitters (direct-conversion, offset-PLL, etc.), as desired. 
     Note further that DFSs according to various embodiments may also be used in RF transceivers. For example, by combining the functionality and/or circuitry of RF receivers that include one or more DFSs with the functionality and/or circuitry of RF transmitters that include one or more DFSs, RF transceivers may be realized, as persons of ordinary skill in the art will understand. In some embodiments, one or more DFSs may be shared between the RF receiver and the RF transmitter, as persons of ordinary skill in the art will understand. 
     Furthermore, RF receivers, RF transmitters, and/or RF transceivers including DFSs according to various embodiments may be used in a variety of communication arrangements, systems, sub-systems, networks, etc., as desired.  FIG. 25  shows a circuit arrangement for an RF communication system  300  according to an exemplary embodiment. 
     System  300  includes a transmitter  200 , coupled to antenna  105 A. Via antenna  105 A, transmitter  200  transmits RF signals. The RF signals may be received by receiver  100 , described above. In addition, or alternatively, transceiver  310 A and/or transceiver  310 B might receive (via receiver  100 ) the transmitted RF signals. 
     In addition to receive capability, transceiver  310 A and transceiver  310 B can also transmit RF signals. The transmitted RF signals might be received by receiver  100 , either in the stand-alone receiver, or via the receiver circuitry of the non-transmitting transceiver. 
     Other systems or sub-systems with varying configuration and/or capabilities are also contemplated. For example, in some exemplary embodiments, two or more transceivers (e.g., transceiver  310 A and transceiver  310 B) might form a network, such as an ad-hoc network, a mesh network, etc. As another example, in some exemplary embodiments, transceiver  310 A and transceiver  310 B might form part of a network, for example, in conjunction with transmitter  200 . 
     RF receivers and RF transmitters, such as RF receiver  100  and RF transmitter  200  described above, may be used in a variety of circuits, blocks, subsystems, and/or systems. For example, in some embodiments, such RF receivers may be integrated in an IC, such as an MCU.  FIG. 26  shows a circuit arrangement for an IC, including RF receiver  100  that includes one or more DFSs (e.g., as shown in  FIGS. 21-23 ), according to an exemplary embodiment. 
     The circuit arrangement includes an IC  550 , which constitutes or includes an MCU. IC  550  includes a number of blocks (e.g., processor(s)  565 , data converter  605 , I/O circuitry  585 , etc.) that communicate with one another using a link  560 . In exemplary embodiments, link  560  may constitute a coupling mechanism, such as a bus, a set of conductors or semiconductor elements (e.g., traces, devices, etc.) for communicating information, such as data, commands, status information, and the like. 
     IC  550  may include link  560  coupled to one or more processors  565 , clock circuitry  575 , and power management circuitry or power management unit (PMU)  580 . In some embodiments, processor(s)  565  may include circuitry or blocks for providing information processing (or data processing or computing) functions, such as central-processing units (CPUs), arithmetic-logic units (ALUs), and the like. In some embodiments, in addition, or as an alternative, processor(s)  565  may include one or more DSPs. The DSPs may provide a variety of signal processing functions, such as arithmetic functions, filtering, delay blocks, and the like, as desired. In some embodiments, functionality of parts of receiver  100 , such as those described above, may be implemented or realized using some of the circuitry in processor(s)  565 , as desired 
     Referring again to  FIG. 26 , clock circuitry  575  may generate one or more clock signals that facilitate or control the timing of operations of one or more blocks in IC  550 . Clock circuitry  575  may also control the timing of operations that use link  560 , as desired. In some embodiments, clock circuitry  575  may provide one or more clock signals via link  560  to other blocks in IC  550 . 
     In some embodiments, PMU  580  may reduce an apparatus&#39;s (e.g., IC  550 ) clock speed, turn off the clock, reduce power, turn off power, disable (or power down or place in a lower power consumption or sleep or inactive or idle state), enable (or power up or place in a higher power consumption or normal or active state) or any combination of the foregoing with respect to part of a circuit or all components of a circuit, such as one or more blocks in IC  550 . Further, PMU  580  may turn on a clock, increase a clock rate, turn on power, increase power, or any combination of the foregoing in response to a transition from an inactive state to an active state (including, without limitation, when processor(s)  565  make a transition from a low-power or idle or sleep state to a normal operating state). 
     Link  560  may couple to one or more circuits  600  through serial interface  595 . Through serial interface  595 , one or more circuits or blocks coupled to link  560  may communicate with circuits  600 . Circuits  600  may communicate using one or more serial protocols, e.g., SMBUS, I 2 C, SPI, and the like, as person of ordinary skill in the art will understand. 
     Link  560  may couple to one or more peripherals  590  through I/O circuitry  585 . Through I/O circuitry  585 , one or more peripherals  590  may couple to link  560  and may therefore communicate with one or more blocks coupled to link  560 , e.g., processor(s)  565 , memory circuit  625 , etc. 
     In exemplary embodiments, peripherals  590  may include a variety of circuitry, blocks, and the like. Examples include I/O devices (keypads, keyboards, speakers, display devices, storage devices, timers, sensors, etc.). Note that in some embodiments, some peripherals  590  may be external to IC  550 . Examples include keypads, speakers, and the like. 
     In some embodiments, with respect to some peripherals, I/O circuitry  585  may be bypassed. In such embodiments, some peripherals  590  may couple to and communicate with link  560  without using I/O circuitry  585 . In some embodiments, such peripherals may be external to IC  550 , as described above. 
     Link  560  may couple to analog circuitry  620  via data converter(s)  605 . Data converter(s)  605  may include one or more ADCs  605 A and/or one or more DACs  605 B. 
     ADC(s)  605 A receive analog signal(s) from analog circuitry  620 , and convert the analog signal(s) to a digital format, which they communicate to one or more blocks coupled to link  560 . Conversely, DAC(s)  605 B receive digital signal(s) from one or more blocks coupled to link  560 , and convert the digital signal(s) to analog format, which they communicate to analog circuitry  620 . 
     Analog circuitry  620  may include a wide variety of circuitry that provides and/or receives analog signals. Examples include sensors, transducers, and the like, as person of ordinary skill in the art will understand. In some embodiments, analog circuitry  620  may communicate with circuitry external to IC  550  to form more complex systems, sub-systems, control blocks or systems, feedback systems, and information processing blocks, as desired. 
     Control circuitry  570  couples to link  560 . Thus, control circuitry  570  may communicate with and/or control the operation of various blocks coupled to link  560  by providing control information or signals. In some embodiments, control circuitry  570  also receives status information or signals from various blocks coupled to link  560 . In addition, in some embodiments, control circuitry  570  facilitates (or controls or supervises) communication or cooperation between various blocks coupled to link  560 . 
     In some embodiments, control circuitry  570  may initiate or respond to a reset operation or signal. The reset operation may cause a reset of one or more blocks coupled to link  560 , of IC  550 , etc., as person of ordinary skill in the art will understand. For example, control circuitry  570  may cause PMU  580 , and circuitry such as RF receiver  10 , to reset to an initial or known state. 
     In exemplary embodiments, control circuitry  570  may include a variety of types and blocks of circuitry. In some embodiments, control circuitry  570  may include logic circuitry, finite-state machines (FSMs), or other circuitry to perform operations such as the operations described above. 
     Communication circuitry  640  couples to link  560  and also to circuitry or blocks (not shown) external to IC  550 . Through communication circuitry  640 , various blocks coupled to link  560  (or IC  550 , generally) can communicate with the external circuitry or blocks (not shown) via one or more communication protocols. Examples of communications include USB, Ethernet, and the like. In exemplary embodiments, other communication protocols may be used, depending on factors such as design or performance specifications for a given application, as person of ordinary skill in the art will understand. 
     As noted, memory circuit  625  couples to link  560 . Consequently, memory circuit  625  may communicate with one or more blocks coupled to link  560 , such as processor(s)  365 , control circuitry  570 , I/O circuitry  585 , etc. 
     Memory circuit  625  provides storage for various information or data in IC  550 , such as operands, flags, data, instructions, and the like, as persons of ordinary skill in the art will understand. Memory circuit  625  may support various protocols, such as double data rate (DDR), DDR2, DDR3, DDR4, and the like, as desired. 
     In some embodiments, memory read and/or write operations by memory circuit  625  involve the use of one or more blocks in IC  550 , such as processor(s)  565 . A direct memory access (DMA) arrangement (not shown) allows increased performance of memory operations in some situations. More specifically, DMA (not shown) provides a mechanism for performing memory read and write operations directly between the source or destination of the data and memory circuit  625 , rather than through blocks such as processor(s)  565 . 
     Memory circuit  625  may include a variety of memory circuits or blocks. In the embodiment shown, memory circuit  625  includes non-volatile (NV) memory  635 . In addition, or instead, memory circuit  625  may include volatile memory (not shown), such as random access memory (RAM). NV memory  635  may be used for storing information related to performance, control, or configuration of one or more blocks in IC  550 . For example, NV memory  635  may store configuration information related to RF receiver  100  and/or to initial or ongoing configuration or control of RF receiver  100  (including DFS(s) included in RF receiver  100 ), as desired. 
     As noted, DFSs according to various embodiments may also be used in RF transmitters. Such RF transmitters may be included in various electronic circuitry, such as ICs.  FIG. 27  shows a circuit arrangement for an IC  500 , including an RF transmitter  200  that includes one or more DFSs, according to an exemplary embodiment. RF transmitter  200  may be coupled to and operate in conjunction with various blocks and circuitry in IC  550 , as described above. 
     Various circuits and blocks described above and used in exemplary embodiments may be implemented in a variety of ways and using a variety of circuit elements or blocks. For example, DFS  10 , TDC  1005 , MMD  1045 , subtracter  1015 , scaling circuit  1055 , digital loop filter  1020 , DCO  1025 , DAC  1030 , divider  1035 , SDM  1060 , delay circuit  1050 , LMS adaptation circuit  1040 , residue error circuit  1010 , jitter monitor circuit  1017 , C-TDC  1100 , F-TDC  1105 , delay circuit  1110 , control circuit  1115 , flip-flop  1210 , control circuit  1205 , synchronous counter  1220 , oscillator  1215 , flip-flops  1275 , encoder logic circuit  1270 , MUX  1255 , inverter  1250 , wrap counter  1265 , MUX control circuit  1260 , one&#39;s complement circuit  1305 , adder  1310 , register  1325 , scaling circuit  1315 , adder  1320 , register  1330 , adder  1060 A, adder  1060 B, DDC  1060 K, integrator  1060 C, adder  1060 D, integrator  1060 F, adder  1060 G, PRBS dither circuit  1060 E, quantizer  1060 H, delay circuit  1060 I, adder  1060 J, scaling circuit  1060 N, scaling circuit  1060 P, scaling circuit  1060 Q, inverter  1605 , inverter  1610 , and various blocks shown in  FIGS. 21-27  that contain digital or mixed-signal circuitry may generally be implemented using gates, digital multiplexers (MUXs), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (e.g., field programmable gate arrays (FPGAs) or other types of programmable logic), arithmetic-logic units (ALUs), standard cells, custom cells, custom analog cells, etc., as desired, and as persons of ordinary skill in the art will understand. 
     In addition, analog circuitry or mixed-signal circuitry or both may be included, for instance, power converters, discrete devices (transistors, capacitors, resistors, inductors, diodes, etc.), and the like, as desired. The analog circuitry in the blocks and circuits above may be implemented using bias circuits, decoupling circuits, coupling circuits, supply circuits, current mirrors, current and/or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs and the like, as desired, and as persons of ordinary skill in the art will understand. The mixed-signal circuitry may include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc.) in addition to analog circuitry and digital circuitry, as described above, and as persons of ordinary skill in the art will understand. The choice of circuitry for a given implementation depends on a variety of factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology), target markets, target end-users, etc. 
     Referring to the figures, persons of ordinary skill in the art will note that the various blocks shown might depict mainly the conceptual functions and signal flow. The actual circuit implementation might or might not contain separately identifiable hardware for the various functional blocks and might or might not use the particular circuitry shown. For example, one may combine the functionality of various blocks into one circuit block, as desired. Furthermore, one may realize the functionality of a single block in several circuit blocks, as desired. The choice of circuit implementation depends on various factors, such as particular design and performance specifications for a given implementation. Other modifications and alternative embodiments in addition to the embodiments in the disclosure will be apparent to persons of ordinary skill in the art. Accordingly, the disclosure teaches those skilled in the art the manner of carrying out the disclosed concepts according to exemplary embodiments, and is to be construed as illustrative only. Where applicable, the figures might or might not be drawn to scale, as persons of ordinary skill in the art will understand. 
     The particular forms and embodiments shown and described constitute merely exemplary embodiments. Persons skilled in the art may make various changes in the shape, size and arrangement of parts without departing from the scope of the disclosure. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described. Moreover, persons skilled in the art may use certain features of the disclosed concepts independently of the use of other features, without departing from the scope of the disclosure.