Patent Publication Number: US-3969749-A

Title: Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide

Description:
This is a continuation of application Ser. No. 456,507 filed Apr. 1, 1974, now abandoned, which was a division of application Ser. No. 788,167 filed Dec. 31, 1968 now U.S. Pat. No. 3,844,858. 
    
    
     This invention relates to the process for making semiconductor devices and to a semiconductor substrate produced in such process, and more particularly, to an improved process for making semiconductor devices which permits control of the thickness of a layer of semiconductor material, a portion of which is to be removed. The invention also concerns semiconductor substrates within which have been formed a window having a predetermined depth. 
     At the present time there is great interest in that area of electronics commonly referred to as &#34;microelectronics.&#34; Within the semiconductor field in particular, this interest has been reflected by the rapid development of integrated circuitry. Generally speaking, the area of integrated circuits may be resolved in two broad classes. The first is referred to as the &#34;chip approach&#34; wherein individual components such as transistors, resistors and diodes are formed on separate pieces of semiconductor material. The separate components are thereafter mounted on an insulating substrate and interconnected in a single package to perform a circuit function. The second class, by far having the greater potential due to the greater reliability in performance and substantial savings in cost and space, involves having all of the individual active and/or passive components formed on a single piece of semiconductor material, the components being interconnected to form the desired circuit function. 
     The formation of all components in one single crystal semiconductor substrate, however, presents the problem of electrically isolating the circuit components from one another. In particular, when a number of transistors are formed within one portion of the substrate, with the substrate forming the collector region, it is necessary for many circuit applications to isolate the transistors to avoid having the collectors commoned. 
     One method known by those skilled in the art for electrically isolating the circuit components, which may be characterized as the &#34;single support layer&#34; technique, comprises etching a series of mesas upon one face of a monocrystalline semiconductor slice. These mesas are then coated with an insulating medium, such as silicon oxide. A &#34;support layer&#34; is then produced over the silicon oxide which serves to support the single crystal material during subsequent processing. The support layer is in many cases epitaxially deposited polycrystalline silicon. A portion of the single crystal semiconductor material is then removed by lapping and polishing to the extent necessary to expose mesa regions which are isolated from each other and electronically insulated by the silicon oxide layer. Circuit elements such as transistors, resistors or other appropriate devices are then formed in the unremoved monocrystalline portion of the mesa by the usual techniques. 
     A form of this single support layer technique is described in U.S. Pat. No. 3,290,753 issued Dec. 13, 1966. Generally in the single support layer technique described above, the mesa regions are comprised of a layer of N+ type silicon buried under an N type silicon layer which is removed by the lapping step. One of the disadvantages of the technique is that uniformity across the slice is difficult to obtain on the N layer since, in some instances, it is preferable for control of the properties of the semiconductor to be formed in the mesa that the thickness of the N layer be controlled to ± 1micron thickness. Further, in the mechanical polishing of the N layer there will be surface damage induced from the polishing, rendering it desirably to chemically etch the damage layer. 
     An alternate procedure for electrically insulating the semiconducting components which are to be formed on the single slice of semiconductor material may be generally described as the &#34;double support layer&#34; technique, one form of which is described in U.S. Pat. No. 3,332,137 issued July 25, 1967 and another form of which is described in Electronics Industries, Vol. 24, No. 6, pp. 38-42 (June 1965). Generally, in the double support layer technique a single crystal substrate of, for example, N+ type material has epitaxially deposited thereon an N- layer which is subsequently covered by silicon oxide. Following the formation of the electrically isolating layer of silicon dioxide, a first support layer is affixed to the oxide, as by depositing polycrystalline silicon over the surface of the oxide. The combined substrate structure is then lapped to remove a portion of the N+ type material to produce a desired thickness. Mesas are then formed through the N+ and N type layers by standard masking and etching techniques, following which the mesas are covered with a silicon oxide layer and a &#34; second supporting layer&#34; deposited over the mesas as by deposition of polycrystalline silicon around and over the mesas. The first support layer is then removed by lapping and polishing to expose the first formed layer of silicon dioxide through which openings may be made by conventional masking and etching techniques to permit formation of the semiconductoring portions of the device, the mesas being electrically insulated or isolated by the silicon dioxide formed therearound and the second supporting layer which is deposited between and over the mesas. As with the single support layer technique, thickness control across the single crystal layer to be lapped and polished is difficult to control during the lapping step. 
     The present invention is of particular utility in controlling the exact thickness of the layer to be lapped in the above described processes, as well as having utility in determining the thickness of layers to be lapped in other processes for producing semiconductor devices. 
     The present invention may be generally described as an improvement in the process of producing a plurality of semiconductor devices from a slice of semiconductor material during which a portion of one surface of the slice is to be removed, and is characterized by the steps of forming a slot of predetermined depth in the opposite surface of the slice so that the slot will be exposed during removal of material from the first mentioned surface should the thickness of the layer be less than the depth of the slot. 
     The invention also comprehends a novel semiconductor substrate such as could be formed by the above process and would comprise a single crystal slice of semiconductor material having a (100) oriented surface with a slot of predetermined depth formed in said surface, the slot having at least two sides bounded by {111} planes and a handle material covering the (100) oriented surface. 
    
    
     For a specific description of an embodiment of the invention, reference is made to the drawings, in which: 
     FIG. 1A is a cross-sectional view of a segment of a slice of semiconductor material; 
     FIG. 2A-12A are cross-sectional views of the semiconductor material of FIG. 1A in various stages of production, during which production the present invention is utilized; 
     FIGS. 1B, 2B and 5B-12B are cross-sectional views through a portion of a slice of semiconductor material in various stages of production utilizing a conventional double support layer technique for comparison with the process of the present invention. 
     FIG. 13 is a partial plan view of the semiconductor material at the state of production illustrated in FIG. 7A; 
     FIG. 14 is a top plan view of a semiconductor substrate prepared in accordance with one embodiment of the present invention; 
     FIG. 15 is an enlarged view of a portion of the semiconductor substrate illustrated in FIG. 14; and 
     FIG. 16 is an illustrative cross-sectional view through a slot formed by a preferred embodiment of the present invention. 
    
    
     To clearly define and point out the usefulness and importance of a preferred embodiment of the present invention, comparison will be made between FIGS. 1A-12A and FIGS. 1B, 2B and 5B-12B. FIGS. 1A-12A illustrate how one embodiment of the present invention may be incorporated into the double support layer process, one form of which is illustrated in FIGS. 1B, 2B and 5B-12B. 
     With reference to FIG. 1B, a single crystal slice of silicon 21, which may, for example, be N type silicon is provided with polished surfaces 22 and 23. On surface 22, as illustrated in FIG. 2B, is first epitaxially deposited an N+ silicon layer 24. Next, as illustrated in FIG. 5B, a layer of silicon oxide 26 is formed over the surface of layer 24 by thermal oxidation of layer 24 or in any other conventional manner to serve as a dielectric insulation medium. A first support layer 27 is then attached to the silicon oxide layer. First support layer 27, which may, for example, be formed by depositing polycrystalline silicon over silicon oxide layer 26, is relatively thick in order to serve as a support during subsequent processing of the substrate illustrated in FIG. 6B. Subsequent processing, for example, may comprise the removal of a portion of the N type layer 21 by lapping and polishing to form the structure illustrated in FIG. 7B, the structure illustrated in FIG. 7B being inverted from the position illustrated in FIG. 6B for ease of decription. As will be noted from examination of FIG. 7B, it is extremely difficult to determine during the lapping and polishing of the N type silicon layer 21 how much of the material has been removed during the lapping step and to control the thickness of layer 21 so that the thickness is uniform across the surface of the slice. Particularly is the uniformity of thickness a problem with slices which, due to thermal gradients created between layers 24, 26 and 21 during deposition of the support layer 27 become non-planar or warp. Lapping of bowed or warped slices causes removal of more material at some points along the surface than at other points due to non-planarity. 
     However, once layer 21 has been lapped to the desired thickness, or what is believed to be the desired thickness, a conventional photoresist mask 30 such as a KMER (Kodak Metal Etch Resist) mask or the like is used to produce a pattern on layer 21, which pattern is provided with openings 28, 29 and 31 by conventional exposure and development techniques to produce the composite of FIG. 8B. The composite illustrated in FIG. 8B is then etched to remove those portions of layers 21 and 24 accessible through openings or windows 28, 29, and 31 by use of vapor etching or by use of an acid etchant which will attack layers 21 and 24 but has little reactivity with the silicon oxide insulating layer 26. As illustrated in FIG. 9B, the etchant will form a series of mesas 32 which, after removal of the masking layer 30 are covered with a silicon oxide layer 33. Following formation of silicon oxide layer 33 over mesas 32, a second supporting layer 34, for example polycrystalline silicon, which due to its polycrystalline nature has a high resistivity, is deposited over silicon oxide layer 33. The first supporting layer 27 is then removed by lapping and polishing to expose silicon oxide layer 21 which, as well known to those skilled in the art, may be opened by masking and etching to permit the fabrication of various semiconducting components within each of the mesas 32. Mesas 32 are electrically insulated from each other by silicon oxide layers 33 and the second supporting layer 34. The individual mesas 32, after fabrication of transistors, diodes and/or passive elements such as resistors and P-N junction capacitors therein, may be interconnected by masking, etching and deposition techniques well known by those skilled in the art to form complete integrated circuits. 
     By way of contrast, reference is made to FIGS. 1A-12A, FIGS. 1A, 2A and 5A-12A of which correspond to FIGS. 1B, 2B and 5B-12B, respectively, but serve to illustrate the present invention. 
     In FIG. 1A the silicon slice 21&#39; which, for example, may be N type silicon has planar faces 22&#39; and 23&#39;, both of which have a (100) orientation. A layer 24&#39; of different conductivity silicon, for example N+ type is epitaxially deposited over surface 22&#39;, as illustrated in FIG. 2A. Over the epitaxially deposited layer 24&#39; is then formed a mask such as KMER photoresist mask 36 through which is opened, in a conventional manner, windows 37-40. Windows 37-40 are, if viewed from the top of FIG. 34, rectangular in shape. Window 38 defines an opening which is narrower than that defined by window 37. Window 39 is more narrow than window 38 and window 40 is still more narrow than window 39. Each of the windows 37-40 describe parallel lines 37&#39; and 37&#34; through 40&#39; and 40&#34;, respectively, on layer 24&#39; which are parallel to lines defined by the intersection of {111} planes with the (100) plane which forms the top surface of layer 24&#39;. 
     As a result of the alignment of windows 37-40, with the {111} planes, upon etching layers 24&#39; and 21&#39; through windows 37-40, there will be formed a plurality of slots 41-44 the walls of which, as illustrated in FIG. 4A, are bounded by {111} planes. The slots 41-44 may be formed with the sloped sides, as indicated in FIG. 4A, by use of preferential etch solutions, such as those described in Electrochem Society Journal (September, 1967) page 965. More specifically, by selection of an etchant solution which preferentially etches {110} and {100} planes rather than the {111} planes, the {110} and {100} planes will be etched faster than the {111} planes causing the sides of slots 41-44 to be bounded by {111} planes. The {111} planes intersect the surface of layers 21&#39;  and 24&#39;, both of which will have a (100) orientation at an angle of 54.74°, as illustrated in FIG. 16. A particular etching solution which has been found suitable for preferentially etching through windows 37-40 comprises a mixture of 88 ml water (61.20 mole %), 17 ml ethylene diamine (35.1 mole %) and 3gm pyrocatechol (3.7 mole %). This solution will etch {100} planes at about 50 micron per hour, {110} planes at about 30 micron per hour and the {111} planes at about 3 micron per hour. Thus, as explained before, by use of the preferential etching solution the geometry of slots 41-44 may be accurately controlled since they will be bounded by the slow etch {111} planes. The depth of the slots 37-40 is then a function of the period of etch as well as the width of windows 37-40. More specifically, the depth designated by d in FIG. 16 will, assuming that the etchant solution is permitted to contact the layers 24&#39; and 21&#39; for a sufficient period of time, be 0.707 times the width of the window through which it is formed, designated w. By control of the width of windows 37-40 the depth of slots 41-44 are controlled. As explained above, since the windows of 37-40 are progressively smaller in width, the resulting etched slots 41-44 are progressively more shallow. The depth of slot 41 is controlled by the duration of the etching period as window 37 is sufficiently wide that the walls of slot 41 will not converge as quickly as slots 42, 43, and 44. As illustrated in FIG. 4A, the period of etch is preferably limited so that the walls of slot 41 do not converge and slot 41 will have, for example, a depth between 1.8 and 2.0 mils. The width of windows 38, 39 and 40 may be so controlled that slots 42, 43 and 44 are respectively 1.25, 1.0 and 0.7 mils deep. Following the etching of slots 41-44 through layers 21&#39; and 24&#39;, a layer 26&#39; of silicon oxide is deposited or formed over the portion of layer 24&#39; remaining after the etching step described above as well as over the surfaces of slots 41-44. 
     Then, as illustrated in FIG. 6A, a first support layer 27&#39; is formed over the silicon dioxide layer 26&#39;, the handle being of any suitable material, such as polycrystalline, silicon, ceramic molten glass or the like. After forming of the first support layer 27&#39;, the original layer 21&#39; of N type silicon or the like is lapped to desired thickness. With the slots 41-44 being provided, the thickness to which the layer 21&#39; is lapped may be determined by visual inspecton as lapping to a depth of less than 1.8 to 2 mils will expose the silicon oxide layer 26&#39; and polycrystalline silicon 27&#39; formed in slot 41. If the desired thickness of layer 21&#39; is between 0.7 mil and 1.0 mil, layer 21&#39; is lapped until the bottoms of slots 41, 42 and 43 are exposed, such as illustrated in FIG. 13. With reference to FIG. 13, since the bottom of slot 44 has not yet appeared through the surface of layer 21&#39; it can be determined that the the thickness of the layer 21&#39; is between  0.7 and 1.0 mil. In order to determine if the thickness of layer 21&#39; is uniform over the entire surface of the slice, a series of the slots 41-44 may be formed at various points spaced about the slice 21&#39;, as illustrated in FIG. 14. In FIG. 14 there are provided five sets of slots 41-44 which are uniformly spaced about the surface of the slice so that upon lapping of layer 21&#39; the visual inspection of any one of the sites 45-49 will permit determination of the thickness of the layer 21&#39; at that location. Once layer 21&#39; has been lapped to the desired thickness, procedures described above in connection with FIGS. 8B-12B are followed. 
     More particularly, a photoresist layer 30&#39; is formed over the substrate illustrated in FIG. 7A and windows 28&#39; and 29&#39; and 31&#39; opened therethrough following which the layer 21&#39; and 24&#39; accessible through such windows may be removed by using a conventional etching solution, though the etching is preferably performed using the preferential etchant described above for reasons to be explained hereafter to produce mesas 32&#39;. A layer of silicon oxide 33&#39; is then formed over the top surface of the substrate illustrated in FIG. 9A following which a second support layer 34&#39;, as illustrated in FIG. 11A is deposited over the silicon oxide layer 26&#39;. The second support layer as described above, may comprise, for example, polycrystalline silicon. The polycrystalline silicon which served as the first support layer 27&#39; is then removed by lapping and polishing to expose the silicon dioxide layer 33&#39;. Windows may then be opened through layer 33&#39; for forming semiconducting devices in the mesas 32&#39;. These semiconducting devices may later be connected by techniques well known to those skilled in the art to form integrated circuits. 
     Each of the mesas 32&#39; is electrically insulated and isolated from each other by the silicon oxide layer 26&#39; as well as the high resistivity polycrystalline layer 34&#39;. 
     While the present invention is described in connection with the formation of electrically insulated semiconducting devices, it has utility also in the formation of semiconducting devices which are formed on a silicon slice and later separated by scribing and breaking since it can be used to control the thickness of the layer of the semiconductor material in which the semiconducting components are to be formed. Various other uses will appear to those skilled in the art after reading the above. 
     It can also be appreciated that the slots 41-44, which may be referred to as &#34;lap-stop indicators&#34; may be controlled to provide an indication of various depths by varying the width of the opening for the windows through which the slots are etched, since the depth of the slot is 0.7 times the width of the opening through which the slot is formed, due to the exact crystalgraphic orientation of the (111) planes relative of the (100) surface. 
     It is also obvious that one, two, three, four or more slots could be utilized depending upon the application. 
     The semiconductor substrates produced by the present invention, such as illustrated in FIG. 4A are extremely useful in various operations where the layer 21&#39; into which they are etched is to be lapped, and it will be observed that the procedure illustrated and described in connection with FIGS. 1A-12A may be varied to achieve the same results. For example, slots 41-44 could have been formed in the silicon slice 21&#39; before application of the N+ silicon layer 24&#39;. In which event, the epitaxially deposited layer 24&#39; would be applied after formation of the slots 41-44. It will also be obvious that the silicon dioxide electrically insulating layer 26&#39; could have been formed over the substrate illustrated in FIG. 2A before the slots 41-44 were formed therein, all of which is contemplated by the present invention. 
     While the preferred embodiment of the present invention is described above, it is not necessary to use the {111} planes in order to control the depth to which the depth indicator slots are etched. Due to various factors, the depth to which slots are etched in a single crystal slice of semiconductor material, regardless of the crystal orientation of the slice, may be controlled by control of the width of the window through which the etching is effected. Thus, by controlling the width of windows 37-40, for example, and the etch period, the depth of the slots formed through windows 37-40 may be controlled. A relationship between etch period and window width, once determined, can then be used to etch a single slot of known depth or several slots of known but different depths. 
     However, the use of converging crystallographic planes or the planes which serve to form the walls of the slots is preferred due to exactness of control which may be realized. 
     It will be appreciated by those skilled in the art that the invention is useful not only in permitting control of the thickness of the layer 21&#39; during lapping, but, with reference to FIGS. 11A and 12A may also be employed in controlling the thickness of the mesas 32&#39; during removal of the first support layer 27&#39;. More specifically, assuming that mesas 32&#39; are also formed by preferential etching along {111} planes, there can be simultaneously formed one or more slots adjacent the mesa regions which, due to the width of the windows through which they are formed terminate before reaching silicon oxide layer 26&#39;. Thus, in the removal of support layer 27&#39;, should these slots become exposed, it is apparent that the semiconductor material remaining in adjacent regions is of a thickness less than the depth of the slots. Of course, as explained above, the depth of these slots may be controlled by control of the width of the window through which they are formed and the etch period, without regard for the crystallographic orientation of the semiconductor material, though such a technique is not preferred. 
     One of the reasons that the depth indicator slots are preferably bounded by converging planes which intersect the surface of the semiconductor material at a known angle is the precision of control permitted by the use of such slots. With reference to FIG. 13, for example, and assuming only slot 41 had been etched in the substrate of FIG. 4A, it is possible to determine with reasonable accuracy that the semiconductor material remaining after lapping is less than the depth of slot 41 should it become exposed, and how much less the thickness is. This determination is possible since the geometry of the slot 41 is known due to precise angle which the walls of slot 41 make with the (110) surface of the semiconductor material. Knowing the angle, 54.74°, the width of the window 37 through which slot 41 was formed and the width of the opening formed by exposure of slot 41 during the lapping operation, the thickness of the semiconductor material can be calculated. This same principle can be employed to determine the thickness of mesas 32&#39; should the second lapping and polishing operation pass through silicon oxide layer 33&#39; . By measuring the width of mesas 32&#39; exposed during the lapping operation, the angle of the sides and width of the bottom of the mesa being known, the thickness of the mesas 32&#39; may be calculated. A gauging mask could be prepared having configurations thereon which geometrically conform to the configurations of mesas 32&#39;, except being of a predetermined minimum dimension could be superimposed over the surface of the substrate illustrated in FIG. 12A. If the portions of mesas 32&#39; exposed by the lapping operation fall within the minimum outline on the gauging mask then it is known that the mesas 32&#39; are too thin as the periphery of mesas 32&#39; will become less as they become thinner due to the angle of the walls of the mesas 32&#39;. 
     Thus, the invention may be used at a number of different stages of production to permit control of the thickness of teh semiconductor material, and other uses will appear to those skilled in the art after reading the above. 
     While rather specific terms have been used to describe an embodiment of the present invention, they are not intended, nor should they be construed as a limitation upon the invention defined in the following claims.