Patent Publication Number: US-7221919-B2

Title: Receiver circuit and radio communication terminal apparatus

Description:
TECHNICAL FIELD 
   The present invention relates to a wireless communication terminal apparatus and its reception circuit, and particularly, to a reception system RF chip for a digital wireless communication terminal. 
   BACKGROUND ART 
     FIG. 1  shows a configuration of a portion of a wireless communication terminal including a conventional direct conversion receiver (DCR) that relates to the present invention. In this configuration, especially, in a communication system using Code Division Multiple Access (CDMA) represented by a third generation mobile phone (3G), since a reception (RX) signal and a transmission (TX) signal having different frequencies are simultaneously input and output, the local TX signal is leaked to the RX side to degrade reception characteristics. To solve this problem, it is necessary to improve isolation characteristics from a transmission circuit  13  to a reception circuit (RX Chip)  14  in a duplexer (DUP)  12 , and it is necessary to insert a band pass filter (BPF)  15  between a low noise amplifier (LNA) and a quadrature demodulator (Quad_Mixer) to suppress a signal level in a TX band. 
   On the other hand, when a desired reception signal level is high, the interference due to the TX leakage mentioned above can be ignored, but on the contrary, circuit saturation caused by the desired signal presents a problem. Thus, it is necessary to reduce the level of a signal input to circuits after the quadrature demodulator by reducing the gain of the LNA only when the desired reception signal level is high or by passing through the LNA. 
   In the DCR system as described above, the BPF  15  must be inserted in order to prevent the TX signal from being leaked and input to the quadrature demodulator and thereafter. Typically, the reception circuit  14  is formed of an IC (Integrated Circuit) chip. In contrast, since a SAW filter is used for the BPF, the BPF  15  is an external part which conflicts with the needs for saved space and a reduced number of parts which the DCR intends to realize. To take advantage of merits of the DCR, degraded reception characteristics due to the leaked TX signal must be avoided without using this BPF. 
   More specifically, as shown in  FIG. 2A , when the TX signal is leaked and is input to the LNA and the quadrature demodulator, second-order distortion of a CDMA modulated signal directly lies on a baseband signal as shown in  FIG. 2B . Since this serves as noise for a desired signal, it leads to a reduced C/N. It should be noted that, in an expression of  FIG. 2C , f(t) represents a local TX modulated signal, sinω TX  represents a TX carrier, a 0  represents a DC offset, a 1  represents an LNA gain, a 2  . . . a n  represent coefficients of n-th order harmonic distortion, respectively, and g(t) represents an output signal of the LNA. 
   It is also contemplated that, in a case where a desired signal input is high, gain switching of the LNA is performed by a gain controlled differential LNA circuit as shown in  FIG. 3 . In this case, there is a problem that, although the level of a signal input to a later stage is reduced, high input tolerance of the LNA itself (such as IIP3 (3 order Input Intercept Point)) is not improved. 
   With an input/output through type LNA gain switching circuit as shown in  FIG. 4 , switches SW 1  to SW 4  can be switched in accordance with the intensity of a desired signal input to pass an input or an output of the LNA through when the desired signal input is high. However, in this circuit scheme, there is a problem that, since the input is only attenuated, a high gain is not provided and gain arrangement has no flexibility. Specifically, a through path in which the switches SW 3  and SW 4  are turned on includes an insertion loss of the switch and a mismatching loss of a matching circuit, and this configuration has no active circuit and thus a positive gain cannot be provided. 
   The present invention has been made in view of such a background, and it is an object thereof to provide a reception circuit which has favorable reception characteristics and high input tolerance of a low noise amplifier and can provide flexibility for gain arrangement of an LNA, and a wireless communication terminal using the same. 
   DISCLOSURE OF THE INVENTION 
   A reception circuit of the present invention is characterized by having a low noise amplifier having a low noise amplifying circuit with a low gain and a low noise amplifying circuit with a high gain which are capable of selective operation in accordance with control of a bias current, and a quadrature demodulator connected with a serial capacitance to an output of the above-mentioned low noise amplifying circuit with the high gain of the above-mentioned low noise amplifier and directly connected to an output of the above-mentioned low noise amplifying circuit with the low gain. 
   When the low noise amplifying circuit with the high gain is selected for operation, the output of the low noise amplifier with the high gain is connected with the serial capacitance to the quadrature demodulator, so that a second-order distortion component produced in the low noise amplifier is removed not to be input to the quadrature demodulator. 
   In this reception circuit, it is preferable that, during operation of the above-mentioned low noise amplifying circuit with the high gain, its DC bias current is passed independently of a DC bias current of the above-mentioned quadrature demodulator, and during operation of the above-mentioned low noise amplifying circuit with the low gain, its DC bias current is shared with a DC bias current of the above-mentioned quadrature demodulator. Thus, consumed power in the reception circuit is reduced when the low noise amplifying circuit with the low gain is selected for operation. 
   In the above-mentioned reception circuit, it is possible to provide a configuration in which each of the above-mentioned low noise amplifying circuit with the high gain and the above-mentioned low noise amplifying circuit with the low gain has a pair of differentially connected transistors, a first and a second inductive elements are connected in series between emitters of the pair of transistors in the above-mentioned low noise amplifying circuit with the low gain, and both ends thereof are connected to emitters of the pair of transistors in the above-mentioned low noise amplifying circuit with the high gain through a third and a fourth inductive elements, respectively. Thus, the differential inductive element of the one low noise amplifying circuit with a different gain can be shared as part of the inductive elements of the other low noise amplifying circuit. 
   It is possible to provide a configuration in which the above-mentioned first to fourth inductive elements are formed of a single inductor in which a spiral is smaller helically from a first terminal in an outermost portion and then the spiral is larger through gaps of the helicity, and returns to a second terminal in the outermost portion, and a third and a fourth terminals are drawn from two positions in the middle between an innermost portion of the inductor and the above-mentioned first and second terminals, a fifth terminal is drawn from a position in the innermost portion, the above-mentioned first and second terminals are connected to the emitters of the pair of transistors in the above-mentioned low noise amplifying circuit with the low gain, the above-mentioned third and fourth terminals are connected to the emitters of the pair of transistors in the above-mentioned low noise amplifying circuit with the high gain, and the above-mentioned fifth terminal is grounded through a resistance. Thus, the area occupied by the first to fourth inductive elements is reduced when the reception circuit is formed as an IC chip. 
   A wireless communication terminal apparatus of the present invention is characterized by having a low noise amplifier having a low noise amplifying circuit with a low gain and a low noise amplifying circuit with a high gain which are capable of selective operation in accordance with control of a bias current, a quadrature demodulator connected with a serial capacitance to an output of the above-mentioned low noise amplifying circuit with the high gain of the above-mentioned low noise amplifier and directly connected to an output of the above-mentioned low noise amplifying circuit with the low gain, a reception level detecting means for detecting a level of a reception signal, and a control means for performing control of the above-mentioned reception circuit in accordance with an output of the above-mentioned reception level detecting means, wherein the above-mentioned control means controls the above-mentioned low noise amplifier such that it operates the low noise amplifying circuit with the low gain when the above-mentioned reception signal level is high, and operates the low noise amplifying circuit with the high gain as the above-mentioned low noise amplifier when the above-mentioned reception signal level is low. 
   With this configuration, in a state in which it is close to a base station, that is, when a reception signal level is higher than a predetermined level, the LNA is set to the low gain to realize low power consumption. If the reception signal predetermined level with which the LNA is switched to the low gain is set to be equal to or lower than average reception power of the terminal, average power consumption of the terminal is reduced. In addition, in a state in which the wireless communication terminal is far from a base station, that is, when a reception signal level is lower than the predetermined level, the LNA is set to the high gain, and in this event, the LNA is coupled with a direct capacitance to the quadrature demodulator, thereby making it possible to remove a second-order distortion component produced in the LNA to prevent it from being input to the quadrature demodulator. 
   Since the LNA is at least AC direct coupled (DC direct coupled at the time of the low gain) to the quadrature demodulator, the whole reception circuit can be formed as an IC chip and the merits of the DCR can be used. 
   In addition, the first to fourth inductive elements in the two LNA with different gains are formed of the single symmetrical type inductor to allow saving of the area occupied by the inductive elements on the chip. As a result, a die size becomes reduced and a chip unit price becomes lower. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a block diagram showing the configuration of a portion of a wireless communication terminal including a conventional direct conversion receiver (DCR) that relates to the present invention; 
       FIGS. 2A to 2C  are diagrams for explaining degradation of reception characteristics due to second-order distortion in the conventional direct conversion receiver; 
       FIG. 3  is a circuit diagram showing an example of a gain controlled differential LNA circuit; 
       FIG. 4  is a circuit diagram showing an example of an LNA gain switching circuit of an input/output through type; 
       FIG. 5  is a block diagram showing a configuration example of a portion of a digital wireless communication terminal including a direct conversion receiver (DCR) according to an embodiment of the present invention that relates to the present invention; 
       FIGS. 6A and 6B  are diagrams showing extracted schematic configurations of a conventional direct conversion receiver and the direct conversion receiver of the embodiment, respectively; 
       FIG. 7  is a circuit diagram showing an example of the specific circuit configuration of a low noise amplifier (LNA) and a quadrature demodulator together with the block of a control section; 
       FIG. 8  is an explanatory diagram for a second-order distortion current produced in the LNA (especially an LNA  72 ) in the circuit of  FIG. 7 ; and 
       FIG. 9  is a diagram showing an example of inductors L 1  to L 4  shown in  FIG. 7  formed of a single inductor (coil). 
   

   BEST MODE FOR CARRYING OUT THE INVENTION 
   In the following, an embodiment of the present invention will be described in detail with reference to the drawings. 
     FIG. 5  shows an example of a configuration of a part of a digital wireless communication terminal containing a direct conversion receiver (DCR) suitable for a wireless communication system using Code Division Multiple Access (CDMA) that relates to the present invention. 
   This wireless communication terminal has a transmission circuit  63 , a reception circuit  64 , an antenna  61 , a duplexer  62  for sharing the antenna between transmission and reception, a reception level detection section  67  which detects a reception signal level, and a control section  66  which controls the operation of the reception circuit  64  based on an output from the reception level detection section  67 . 
   The reception circuit  64  is formed of an IC chip, and has two LNAs  71  and  72  having different gains, a capacitor  73  connected in series to an output of the LNA  72 , a quadrature demodulator  80  which demodulates an output of an LNA  70 , a local oscillator  77 , baseband filters (BBF)  81  and  84 , DC offset compensation circuits  82  and  83 , and amplifiers  85  and  86 . The quadrature demodulator  80  has mixers  74  and  75  for an I channel and a Q channel, respectively, and a phase shifter  76  which receives transmitted signals of the local oscillator  77  and supplies signals with a predetermined phase difference to the mixers  74  and  75 . 
     FIGS. 6A and 6B  show the extracted schematic configurations of a conventional direct conversion receiver and the direct conversion receiver of the embodiment, respectively. In the conventional configuration of  FIG. 6A , an LNA  51  is connected to a quadrature demodulator (including respective mixers  53  and  54  for I-ch and Q-ch) by an off-chip BPF. However, in the embodiment of  FIG. 6B , an off-chip BPF is not required, and the LNA (including the LNAs  71  and  72 ) is directly connected to the quadrature demodulator  80  (including the respective mixers  74  and  75  for I-ch and Q-ch) within the IC chip (however, capacitors  73   a  and  73   b  serving as serial capacitances are inserted between the quadrature demodulator  80  and the LNA  72 .) In addition, since a differential configuration is preferred for circuits within the reception circuit  14 , the LNA  71  and  72  are changed from a single configuration to the differential configuration. 
     FIG. 7  shows an example of the specific circuit configuration of the low noise amplifier (LNA)  70  and the quadrature demodulator  80  together with the block of the control section  66 . The control section  66  is a circuit block which performs DC bias creation and control of the LNA  70  and the quadrature demodulator  80 . 
   The LNA  70  is formed of the two differential amplifiers  71  and  72  controlled to selectively operate. The first differential amplifier  71  is formed of transistors Q 1  and Q 2 , inductors (inductive elements) L 1 , L 2 , L 3 , and L 4 , capacitors C 4  and C 6 , and resistors R 6  and R 8 . Collectors of the transistors Q 1  and Q 2  are directly connected to the quadrature demodulator  80 . The second differential amplifier  72  is formed of transistors Q 4  and Q 3 , inductors L 2  and L 3 , capacitors C 3  and C 5 , and resistors R 4  and R 7 . Collectors of the transistors Q 4  and Q 3  are connected to a power voltage Vcc through inductors L 5  and L 6 , respectively, and connected to the quadrature demodulator  80  through capacitors C 1  and C 2  (corresponding to  73   a  and  73   b  in  FIG. 6B ). A reception signal RFIN+ is applied to each of bases of the transistors Q 1  and Q 4  through the capacitors C 4  and C 3 , respectively, from a terminal P 1 . A reception signal RFIN− is applied to each of bases of the transistors Q 2  and Q 3  through the capacitors C 6  and C 5 , respectively, from a terminal P 2 . The inductors L 2  and L 3  are shared between both the differential amplifiers  71  and  72 , and a connection point between them is grounded through a resistor R 5 . The bases of the transistors Q 1 , Q 2 , Q 3 , and Q 4  are connected to bias terminals P 4 , P 5 , P 6 , and P 3  through the resistors R 6 , R 8 , R 7  and R 4 , respectively. The terminals P 3  and P 6  are connected to a terminal B 3  of the control section  66 , and the terminals P 4  and P 5  are connected to a terminal B 4  of the control section  66 . 
   The quadrature demodulator  80  has two Gilbert Cells  801  and  802  for an I channel and a Q channel, respectively. The quadrature demodulator  80  is divided into parts for the I channel and the Q channel on the left and right of  FIG. 7 . 
   The Gilbert Cell  801  has a first differential pair of transistors Q 11  and Q 12  and a second differential pair of transistors Q 10  and Q 9 . Emitters of the first differential pair of transistors Q 11  and Q 12  are directly coupled and connected to a collector of a transistor Q 13  forming a current source and a collector of the transistor Q 1  of the aforementioned LNA  70 . Emitters of the second differential pair of transistors Q 10  and Q 9  are directly coupled and connected to a collector of a transistor Q 14  forming a current source and a connector of the transistor Q 2  of the aforementioned LNA  70 . Bases of the first differential pair of transistors Q 9  and Q 12  are connected to a terminal P 11  through a resistor R 13 , and this terminal P 11  is connected to the terminal B 1  of the control section  66 . Bases of the second differential pair of transistors Q 10  and Q 11  are connected to the terminal P 11  through a resistor R 12 . Bases of the transistors Q 10  and Q 11  are connected to a terminal P 7  through a capacitor C 8 , and bases of the transistors Q 9  and Q 12  are connected to a terminal P 8  through a capacitor C 7 . A local transmission signal (I-ch Local IN) of the I channel is input to the terminals P 7  and P 8 . In addition, collectors of the transistors Q 10  and Q 12  are connected to the power voltage Vcc through a resistor R 1  and a capacitor C 14  connected in parallel. Collectors of the transistors Q 9  and Q 11  are connected to the power voltage Vcc through a resistor R 2  and a capacitor C 13  connected in parallel. The collectors of the transistors Q 10  and Q 12  are connected to a terminal P 13 , from which an IOUT+ signal is output. The collectors of the transistors Q 9  and Q 11  are connected to a terminal P 14 , from which an IOUT− signal is output. 
   Similarly, the Gilbert Cell  802  has a third differential pair of transistors Q 7  and Q 8  and a fourth differential pair of transistors Q 6  and Q 5 . Emitters of the third differential pair of transistors Q 7  and Q 8  are directly coupled and connected to a collector of a transistor Q 15  forming a current source and the collector of the transistor Q 1  of the aforementioned LNA  70 . Emitters of the fourth differential pair of transistors Q 6  and Q 5  are directly coupled and connected to a collector of a transistor Q 16  forming a current source and the collector of the transistor Q 2  of the aforementioned LNA  70 . Bases of the third differential pair of transistors Q 7  and Q 6  are connected to the terminal P 11  through the resistor R 10 , and this terminal P 12  is connected to the terminal B 1  of the control section  66 . Bases of the fourth differential pair of transistors Q 8  and Q 5  are connected to a terminal P 12  through a resistor R 11 . The bases of the transistors Q 6  and Q 7  are connected to a terminal P 10  through a capacitor C 9 , and the bases of the transistors Q 5  and Q 8  are connected to a terminal P 9  through a capacitor C 10 . A local transmission signal (Q-ch Local IN) for the Q channel is input to the terminals P 10  and P 9 . In addition, collectors of the transistors Q 6  and Q 8  are connected to the power voltage Vcc through a resistor R 9  and a capacitor C 11  connected in parallel. Collectors of the transistors Q 5  and Q 7  are connected to the power voltage Vcc through a resistor R 3  and a capacitor C 12  connected in parallel. The collectors of the transistors Q 6  and Q 8  are connected to a terminal P 15 , from which a QOUT+ signal is output. The collectors of the transistors Q 5  and Q 7  are connected to a terminal P 16 , from which a QOUT− signal is output. 
   Transistors Q 13 , Q 14 , Q 15 , and Q 16  each forming the current source constitute a current mirror circuit together with circuitry within the control section  66 , and the terminal P 13  connected to the bases of the respective transistors is connected to the terminal B 2  of the control section  66 . 
   Next, the operation of the circuits in  FIG. 7  is described. 
   [1] A Case Where a Desired Reception Signal Level is Low 
   The reception level detection section  67  ( FIG. 5 ) is performing signal level measurement with a baseband (BB). In response to an output from the reception level detection section  67 , the control section  66  outputs a control signal for increasing a gain to the LNA  70  in a case where the signal level is low. Specifically, a reference current source circuit (not shown) for a current mirror connected to the terminal B 3  within the control section  66  is turned on, and a reference current source circuit (not shown) for a current mirror connected to the terminal B 4  is turned off. As a result, the current mirror reference current source circuit within the control section  66  and the transistors Q 3  and Q 4  through the terminal B 3  and the terminals P 3  and P 6  constitute a current mirror circuit, and a desired bias current I H  passes through the LNA  72 . This current is supplied from the Vcc through the inductors L 5  and L 6 . (Direct current display in  FIG. 7  is only display of one channel of the differential.) The transistors Q 3  and Q 4  simultaneously operate as amplifying elements of the LNA, and convert an RF signal voltage input to the terminals P 1  and P 2  into a current and amplify it. 
   Similarly, in the case where the signal level is low, the reference current source circuit for a current mirror (not shown) connected to the terminal B 4  within the control section  66  is turned off, so that no current passes through the transistors Q 1  and Q 2  connected through the terminals P 4  and P 5 , and the LNA circuit  71  formed by these transistors does not operate. In addition, simultaneously, the reference current source circuit for a current mirror (not shown) connected to the terminal B 2  within the control section  66  connected to the terminal B 2  is turned on, and a current mirror formed by connecting this circuit to each transistor of the transistors Q 13  to Q 16  through the terminal P 13  operates, and the four transistors of the transistors Q 13  to Q 16  operate as constant current sources of the same configuration. On the other hand, since a constant voltage compensated for temperature is supplied from the terminal B 1  through the terminals P 11  and P 12 , a bias current 2I 0  passes through the two Gilbert Cell circuits formed by the transistors Q 5  to Q 12 . 
   In this state, the LNA  72  formed by the transistors Q 3  and Q 4  must have a high gain. Thus, voltage negative feedback inductors (degeneration inductors) L 2  and L 3  connected in series to emitters of the transistors Q 3  and Q 4  are set to values such that the LNA can maintain favorable third-order distortion characteristics and provide a high gain. In addition, the inductors L 5  and L 6  serve as loads in terms of AC, and form a resonance circuit together with a parallel capacitance formed by a capacitance Ccs on the collector side of the transistors Q 4  and Q 3  and an input capacitance of the quadrature demodulator. The values of the inductors L 5  and L 6  are determined such that the resonance frequency of the resonance circuit matches an RX reception frequency. 
   In addition, in this state, since a terminal is generally at a position far from a base station, local transmission power is set to be high such that up-channel information is sufficiently transmitted. In other words, it is in a state in which a desired RX signal shown in  FIG. 2B  is low and a local TX signal is high. Thus, it is expected that a ratio between folding noise of a second-order distortion component of TX to the BB band and a BB signal component of a desired signal (a power ratio of a 2 f 2 (t) and b 1 h(t)) is reduced. With  FIG. 8 , description is made for a second-order distortion current produced in the LNA (especially, the LNA  72  including Q 3  and Q 4 ). Here, the second-order distortion component of the local TX signal is represented by a square function of a BB signal of TX. Specifically, when Vin/2=f(t)sinω TX , the second-order distortion component I IM2  is as follows:
 
 I   IM2   =gm   2   f   2 ( t )
 
where gm 2  is equivalent to the aforementioned a 2 . Since f(t) is a base band signal and has a frequency sufficiently lower than an RF signal, it can be cut by the capacitors C 1  and C 2  in  FIG. 8 . Thus, the amount by which the second-order distortion noise of TX overlaps the reception BB signal is reduced. On the other hand, since the desired RX signal is a signal in an RF band, an RX signal amplified by the transistors Q 3  and Q 4  is supplied to the quadrature demodulation circuit  80  in the next stage through the capacitors C 1  and C 2 .
 
   It should be noted that, in this operation state, DC bias currents passing through the LNA  70  and the quadrature demodulator  80  are 2I H  and 4I 0 , and a total current is 2I H +4I 0 . 
   [2] A Case Where a Desired Reception Signal Level is at a High Level, Equal to or Higher than a Certain Level 
   In a case where a signal level is high equal to or higher than a certain predetermined value, in response to an output from the reception level detection section  67 , the control section  66  outputs a control signal for reducing the gain of the LNA  70  to the LNA  70 . Specifically, in the control section  66 , while the reference current source circuit for a current mirror inside connected to the terminal B 4  is turned on, the reference current source circuit for a current mirror connected to the terminal B 3  is turned off. As a result, the current mirror reference current source circuit within the control section  66  and circuitry formed of the transistors Q 1  and Q 2  through the terminals P 4  and P 5  from the B 4  terminal constitute a current mirror circuit, and a desired bias current, as later described, passes through it. On the other hand, at this point, in the quadrature demodulator  80 , a reference current source circuit for a current mirror inside connected to the terminal B 2  is turned off, and a current mirror circuit formed by connecting it to the transistors Q 13  to Q 16  through the terminal P 13  does not operate, so that the four transistors Q 13  to Q 16  are turned off, and no DC current passes through. However, the collectors of the transistors Q 1  and Q 2  of the LNA  71  in the operation state are connected as DC to the two Gilbert Cells  801  and  802  formed by the transistors Q 5  to Q 12  not through the capacitances of the capacitors C 1  and C 2 , respectively, so that a DC bias current passes through these Gilbert Cell circuits with the transistors Q 1  and Q 2  for the LNA  71  as constant current sources. If the current mirror circuit formed by the reference current source circuit within the control section  66  and the transistors Q 1  and Q 2  is set such that a current of 2I 0  passes through the transistors Q 1  and Q 2 , respectively, a bias current necessary for the Gilbert Cell circuits can be passed through. 
   In addition, the transistors Q 1  and Q 2  operate as differential LNAs driven by the DC bias current of 2I 0 , and convert an RF signal voltage input to the terminals P 1  and P 2  into a current and amplify it. At this point, the inductors L 5  and L 6  inserted between the collectors of the transistors Q 1  and Q 2  through the capacitors C 1  and C 2  serve loads in terms of AC similarly to the case where the transistors Q 3  and Q 4  operate as the high gain LNA  72 , and form a resonance circuit together with a parallel capacitance formed by the capacitance Ccs on the collector side and the input capacitance of the quadrature demodulator  80 . As described above, the values of the inductors L 5  and L 6  are determined such that the reference frequency of this resonance circuit matches an RF reception frequency. In this state, the gain of the LNA  70  needs to be reduced (set to a low gain) to the extent that the LNA and the circuit in the next stage do not come into a saturation state even when the wireless communication terminal comes closest to the base station and the desired RX signal level is at the maximum. For this reason, inductors connected to emitters of the transistors Q 1  and Q 2  respectively need to have higher inductance than at the time of a high gain. Thus, connection of the inductors L 1  and L 4  directly to the inductors L 2  and L 3  at the time of a high gain, respectively, satisfies this requirement. 
   In this state, since the current mirror reference current source circuit within the control section  66  connected to the terminal B 3  is turned off, no current passes through the transistors Q 3  and Q 4 , and the LNA circuit  72  formed by these transistors does not operate. 
   In addition, in this state, since the terminal is at a position relatively close to the base station, uplink channel information can be transmitted even when transmission power is not increased. Specifically, since it is in a state in which a desired RX signal shown in  FIG. 2B  is high and a local TX signal is low, the ratio of folding noise of a second-order distortion component of TX to the BB band to a BB signal component of a desired signal (the power ratio of a 2 f 2 (t) and b 1 h(t)) is increased. Thus, it is not necessary in the LNA  71  for a low gain including the transistors Q 1  and Q 2  to remove a second-order distortion signal produced in the LNA with the capacitance coupling as in the high gain LNA  72 , and the LNA  71  for a low gain can be directly connected to the quadrature demodulator  80  in a direct current manner. 
   In this operation state, DC bias currents passing through the LNA  70  and the quadrature demodulator  80  are 4I 0  and 4I 0 , respectively, and the collectors of the transistors Q 1  and Q 2  of the LNA  71  are directly connected in a DC manner to the emitter sides of the eight transistors in the two Gilbert Cells  801  and  802  forming the quadrature modulator  80 , so that a total current is 4I 0 . This is smaller than the setting at the time of a high gain by I H , and it is apparent that saving of consumed power is possible. 
   It should be noted that the inductors L 1  to L 4  can be formed of a single inductor (coil) as shown in  FIG. 9 . (In  FIG. 9 , a hatched line is for clearly showing the connection relationship with intersected lines, and has no meaning other than that.) In this inductor, a spiral is smaller helically from a terminal P 91  and then the spiral is larger through gaps of the helicity, and finally, returns to a terminal P 92  at a position adjacent to the terminal P 91 . This path is formed by a single helical conductive path which can be written in one stroke. A tap terminal is drawn from a predetermined position in such a path. Specifically, a tap terminal P 95  is drawn from a position n 5  at center of the innermost portion, and tap terminals P 93  and P 94  are drawn from positions (here, symmetrical positions n 3  and n 4  in a path immediately outside of to the center) in the middle between the position n 5  and the outermost terminals P 91  and P 95 , respectively. A portion from the terminal P 91  to n 3  serves as the inductor L 1 , a portion from n 3  to n 5  as the inductor L 2 , a portion from n 5  to n 4  as the inductor L 3 , and a portion from n 4  to the terminal P 92  as the inductor L 4 . Specifically, if the terminals P 91  and P 92  in  FIG. 9  are connected to the emitters of the transistors Q 1  and Q 2  in  FIG. 7 , and the terminals P 93  and P 94  in  FIG. 9  are connected to the emitters of the transistors Q 3  and Q 4  in  FIG. 7 , and P 95  in  FIG. 9  is connected to the hot side of the resistor R 5 , respectively, the four inductors L 1  to L 4  can be realized by the apparent signal inductor configuration. This reduces the area occupied by the inductors, and tapping from symmetrical positions of the horizontally symmetrical coil shape can easily match the paired inductor values (inductances). 
   While the preferred embodiment of the present invention has been described so far, various modifications and variations other than that described above are possible.