Patent Publication Number: US-2015076639-A1

Title: Optical shield in a pixel cell planarization layer for black level correction

Description:
BACKGROUND INFORMATION 
     1. Field of the Disclosure 
     This disclosure relates generally to photodetectors, and in particular but not exclusively, relates to black level correction in image sensors. 
     2. Background 
     As pixel size scales down and array resolution scales up, construction of black level correction (“BLC”) pixels, and color filters faces increasingly difficult technical hurdles to overcome in next generation optical devices. Conventional methods of fabricating BLC pixels and color filters result in undesirable electrical signals and mechanical stresses in pixel arrays. Changes in temperature, humidity, and voltage can increase the magnitude of these unwanted effects when employing a traditional architecture. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
         FIG. 1A  is a diagram illustrating one example of a cross-section of a portion of a pixel array where an optical shield layer is deposited on a planarization layer, in accordance with an embodiment of the disclosure. 
         FIG. 1B  is a diagram illustrating one example of a cross-section of a portion of a pixel array where an optical shield layer is deposited in a planarization layer, in accordance with an embodiment of the disclosure. 
         FIG. 1C  is a diagram illustrating one example of a cross-section of a portion of a pixel array where one or more lenses are formed on the planarization layer, in accordance with an embodiment of the disclosure. 
         FIG. 2  illustrates a top down view of one example of an imaging system, in accordance with an embodiment of the disclosure. 
         FIG. 3  is a flow chart illustrating one example of a method of forming a pixel array, in accordance with an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of a backside illuminated (“BSI”) imaging system with black reference pixels are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. 
     Reference throughout this specification to “one embodiment” or “an embodiment” or “one example” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “one example” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined or eliminated in any suitable manner in one or more embodiments. 
     Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. 
     Here, examples in accordance with the teachings of the present invention address contributing factors to diminished image sensor performance with respect to black level correction. As will be discussed, an improved BLC ratio is achieved with an optical shield layer that is deposited after a color filter layer in accordance with the teachings of the present invention, because BLC pixels experience a mechanical and electrical environment similar to pixels that receive light. Additionally, better color uniformity is achieved if color filters are not fabricated on a prior patterned metal topography. 
     To illustrate,  FIGS. 1A-1C  are cross-section views showing an example of a portion of a pixel array  101  at various stages during fabrication in accordance with the teachings of the present invention. In particular,  FIG. 1A  shows an example of a plurality of photodiodes  102  arranged in a pixel array  101  and disposed in a semiconductor layer  104 . In one example, the semiconductor layer  104  includes silicon. In one example, a color filter layer  106  is disposed proximate to the semiconductor layer  104  as shown, such that light  103  is to be directed to at least one of the plurality of photodiodes  102  through the color filter layer  106 . In the depicted example, light  103  is directed to the plurality of photodiodes  102  through a backside  105  of the pixel array  101  as shown. In one example, the color filter layer  106  includes a red color filter  120 , a green color filter  122 , and a blue color filter  124 . In one example, one or more interlayers  110  are disposed between the semiconductor layer  104  and color filter layer  106 . In one example, the one or more interlayers  110  include a silicon nitride layer  112  and a silicon carbide layer  114 . 
     As shown in the example depicted in  FIG. 1A , an optical shield layer  108  is disposed proximate to the color filter layer  106  such that the color filter layer  106  is disposed between the optical shield layer  108  and the semiconductor layer  104 . As such, the optical shield layer  108  shields at least one of the pluralities of photodiodes  102  from light  103  in accordance with the teachings of the present invention. In one example, the optical shield layer  108  includes a metal material such as for example but not limited to aluminum, copper or the like. In one example, a planarization layer  116  is disposed over the color filter layer  106  such that the planarization layer  116 , or at least a portion of the planarization layer  116 , is disposed between the optical shield layer  108  and the color filter layer  106  as shown in accordance with the teachings of the present invention. 
       FIG. 1B  illustrates the cross-section view of an example of the pixel array  101  of  FIG. 1A  with an additional portion of the planarization layer  116  deposited over the planarization layer  116 , as well as over the optical shield layer  108  on the backside  105  in accordance with the teachings of the present invention. As such, the optical shield layer  108  floats within, or in other words is encapsulated within the planarization layer  116  as illustrated in  FIG. 1B  in accordance with the teachings of the present invention. 
       FIG. 1C  illustrates the cross-section view of the example of the pixel array  101  of  FIG. 1B  with one or more lenses  118  fabricated on top of the planarization layer  116  on the backside  105  in accordance with the teachings of the present invention. 
     It should be noted that the examples shown in  FIGS. 1A-1C  share the similar trait of having the optical shield layer  108  located proximate to the color filter layer  106  (with the color filter layer  106  located between the optical shield layer  108  and the semiconductor layer  104 ). As such, the color filter layer  106  is coated onto the backside  105  of the pixel array  101  with no prior patterned metal topography from, for example, the optical shield  108  in accordance with the teachings of the present invention. In other words, the metal of the optical shield layer  108  is deposited after the color filters  120 ,  122 , and  124 , of the color filter layer  106  in accordance with the teachings of the present invention. This helps relieve various electro-mechanical stresses that would otherwise result as a consequence of locating the color filter layer  106  in the same plane as the optical shield layer  108  as is done in some conventional device architectures. 
       FIG. 2  is an illustration of an imaging system  202  including an example pixel array  201  (including individual pixels  212 ), control circuitry  206  coupled to the pixel array  201  to control operation of the pixel array  201 , readout circuitry  208  coupled to the pixel array  201  to readout image data from the pixel array  201 , and function logic  210  coupled to the readout circuitry  208  to store the image data readout from the pixel array  201 . 
     In one example, the pixel array  201  is a two-dimensional array of image sensors or pixels (e.g., pixels P1, P2, P3 . . . , Pn). It is noted that pixel array  201  may be an example of pixel array  101  of  FIGS. 1A-1C , and that similarly named and numbered elements referenced in  FIG. 2  may be coupled and function similar to as described above in  FIGS. 1A-1C . As illustrated, each pixel  212  can be arranged into a row (e.g., rows R1, R2, R3 . . . , Ry) and column (e.g., column C1, C2, C3 . . . , Cx) to acquire image data of an object, which can then be used to render an image of said object. 
     In one example, after each pixel  212  has acquired its image data or image charge, the image data is read out by readout circuitry  208  and then transferred to function logic  210 . In various examples, readout circuitry  208  may include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or otherwise. In one example, readout circuitry  208  may read out a row of image data at a time along readout column lines (illustrated) or may read out the image data using a variety of other techniques (not illustrated), such as a serial read out or a full parallel read out of all pixels simultaneously. Function logic  210  may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). 
     In one example, control circuitry  206  is coupled to pixel array  201  to control operational characteristics of pixel array  201 . For example, control circuitry  206  may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels  212  within pixel array  201  to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels  212  is sequentially enabled during consecutive acquisition windows. 
       FIG. 3  is a flow chart of one example of a method of fabricating a pixel array  300 . Process block  302  shows that a plurality of photodiodes disposed in a semiconductor layer is formed. One skilled in the art will recognize that there are many possible materials/structures available to achieve the properties necessary for the plurality of photodiodes disposed in a semiconductor layer to function properly with respect to the scope of the present invention. In one example, process blocks  304  and  306  show that silicon carbide and silicon nitride interlayers may then be deposited. Process block  308  shows that a color filter layer is then formed. In one example, as shown in  FIG. 1  above, the color filter layer may include red  120 , green  122 , and blue  124 , color filters. Process block  310  shows that a planarization layer is deposited. Process block  312  shows that the optical shield layer is deposited and patterned such that the color filter layer is formed onto the pixel array prior to the optical shield layer being deposited and patterned onto the pixel array, in accordance with the teachings of the present invention. In one example, the optical shield layer includes a metal material such as for example but not limited to aluminum, copper or the like. Process block  314  shows that an additional planarization layer, or at least a portion of the planarization layer, is deposited after the optical shield layer is deposited, such that the optical shield layer floats within, or in other words is encapsulated within the planarization layer, in accordance with the teachings of the present invention. Process block  316  shows that lenses are then formed after the planarization layer is deposited. It is noted that the method of fabricating a pixel array  300  contains steps to fabricate layers of device architecture shown above in  FIGS. 1A-1C  and  FIG. 2 , and that similarly named and numbered elements referenced in  FIG. 3  may be coupled and function similar to as described above in  FIGS. 1A-1C  and  FIG. 2 . 
     The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
     These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.