Patent Publication Number: US-2003224611-A1

Title: Manufacturing method of semiconductor devices by using dry etching technology

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-066293, filed Mar. 12, 1999, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002] The present invention relates to a manufacturing method of semiconductor devices by using a dry etching technology. More particularly, the present invention relates to a method of forming an interlayer insulating film of a dual trench metallization using an organic silicon film such as polysilane, a method of forming a contact hole and a trench, a method of forming a deep trench and a method of removing an anti-reflection film.  
       [0003] When a process for manufacturing semiconductor devices each having a multilayered metallization is performed, a step is frequently employed with which the pattern of a contact hole or the like is formed on a multilayered insulating film constituted by, for example, a silicon oxide film, silicon nitride film and the like, such that a resist serves as a mask.  
       [0004] Hitherto, when a selective etching step of the silicon oxide film and the silicon nitride film is performed by using dry etching technology such as RIE (abbreviation of Reactive Ion etching), the selective ratio (the ratio of etching speeds) between the resist and the silicon nitride film can be raised. The selective etching can easily be performed. Since the etching selective ratio between the resist and the silicon nitride film cannot be raised, selective etching of the silicon nitride film using the resist as a mask cannot easily be performed.  
       [0005] In recent years, integration of miniature trench capacitors at a high density is required to manufacture large scale semiconductor memory devices. Therefore, formation of trenches each having a great depth as compared with the size of the opening portion (hereinafter called a “high aspect ratio”) on a semiconductor substrate by using the anisotropic dry etching is one of important techniques.  
       [0006] When the trenches each having a high aspect ratio are formed on a semiconductor substrate, also opening portions each having a high aspect ratio must be formed in an insulating film mask by using anisotropic dry etching. Hitherto, a resist mask has been employed to form the opening portions in the insulating film mask. To form opening portions each having a high aspect ratio, gas plasma excited by high power and high frequency radiation must be applied to the resist for a long time.  
       [0007] It leads to a fact that the opening portions in the resist are unevenly deformed. Therefore, a multiplicity of trenches each having a smooth inner surface and exhibiting satisfactory accuracy cannot easily be formed in the semiconductor substrate with a high yield.  
       [0008] As the microfabrication technology progresses, the thickness of the resist must be reduced to raise the resolution of lithography. Since so-called film thinning occurs when the dry etching is performed, the trenches cannot easily be formed.  
       [0009] A usual method of manufacturing semiconductor devices incorporates a smoothing process having the steps of forming isolation trenches for isolating devices from one another are formed by using a silicon nitride film, the pattern of which has been formed on a semiconductor substrate, as an etching mask; forming a thick silicon oxide film for isolating the devices from each other such that the isolation trenches are buried; and polishing the surface such that the silicon nitride film serves as a stopper (a suppression layer) so that the isolation trenches are buried with the oxide film and the device region is smoothed.  
       [0010] Since a multiplicity of silicon nitride film stoppers present in portions in which device regions are present at high density, the process for smoothing the device region using polishing of the surface enables satisfactory smoothing of the surface to be performed such that the isolation trenches are filled with the silicon oxide film. In the portions in which the device regions are present at a low density, the number of silicon nitride film stoppers is insufficiently small. Thus, the silicon oxide film is excessively polished in the smoothing process. As a result, there arises a problem in that smoothing and formation of the device regions cannot uniformly be performed over the overall surface of the wafer.  
       [0011] Therefore, a countermeasure is taken with which polysilicon film is deposited on the overall surface, and then a smoothing process is performed and the polysilicon film is, as the etching mask, left in the low density portion. The smoothing step, however, sometimes encounters a crack of the silicon oxide film in the low density portion. When the silicon nitride film stoppers on the device region and the polysilicon mask are removed, there arises a problem in that the silicon substrate is scooped out excessively.  
       [0012] Hitherto, a gate electrode has been formed by a method comprising the steps of forming a silicon nitride film on a metallic film for forming the gate electrode; forming a resist in a gate electrode formation region on the silicon nitride film; using the resist as a mask to form a nitride film; and using the silicon nitride film having a pattern formed after the resist mask has been separated to machine the metallic film as the gate electrode.  
       [0013] If the surface of the wafer has an uneven portion, the projecting portions of the surface of the wafer are excessively etched when the pattern of the silicon nitride film is formed. As a result, the metallic film formed below the pattern is undesirably etched, causing a problem to arise in that a satisfactory gate electrode formation cannot be performed.  
       [0014] When an etching process is performed to form a self-aligned contact (hereinafter abbreviated as a “SAC”), opening of a contact hole in an interlayer insulating film for burying the space between the gate electrode is performed. At this time, an edge line along which the upper surface and the side surface of the gate electrode intersect is exposed in the lower portion of the opening portion of the contact hole.  
       [0015] Undesirable etching of the gate electrode during the etching process for opening the contact hole in the interlayer insulating film constituted by the silicon oxide film must be prevented. Therefore, the gate electrode is usually coated with a silicon nitride film (an etching stopper) which has a high etching selective ratio with respect to the silicon oxide film. Although a satisfactory high etching selective ratio of the silicon nitride film with respect to the oxide film can be obtained in a flat portion, the etching selective ratio is lowered to about ⅓ or lower of the flat portion in the edge line portion.  
       [0016] Therefore, the edge line portion of the gate electrode is undesirably etched when the contact hole is opened in the SAC formation step. Thus, the gate metal is exposed to outside, causing short-circuit fault to occur when the metallization metal is buried in the contact hole. As a result, a fact is known that the SAC cannot easily be formed in the process for manufacturing E 2  PROM in which the gate electrode has a high aspect ratio (the ratio of the length of the gate and the height of the gate).  
       [0017] Since the microfabrication technology has proceeded in recent years, etching of the interlayer insulating film at a high aspect ratio is required frequently. A fact is known that when dry etching of the silicon oxide film at a high aspect ratio is performed under condition that a high etching selective ratio with respect to the silicon nitride film is permitted, residues such as fluorocarbon are left in the opening portion during the progress of the etching operation. Thus, etching is interrupted.  
       [0018] As a technology for forming a multilayered metallization, double-trench metallization (called a “dual-damascene structure” in this industrial field) is employed frequently. When fabrication of the interlayer insulating film having the dual-damascene structure is performed, miniaturized dry etching process technology is required which is a combination of trench formation for burying two layered metallizations and contact hole formation for connecting the two layered metallizations to each other.  
       [0019] Hitherto, it is very difficult to control the depth of the trenches in the surface of the wafer when the trenches are formed in the interlayer insulating film. To realize the control, a method has been employed with which a silicon nitride film is inserted into the interlayer insulating film constituted by the silicon oxide film to use the silicon nitride film as the stopper for the dry etching. When the dual-damascene structure having a complicated shape is formed, the stopper constituted by the silicon nitride film is required to control the depth of the trench metallization of the upper layer after the contact hole has been formed.  
       [0020] In the foregoing case, the silicon nitride film having a dielectric constant higher than that of the silicon oxide film is contained adjacent to the metallization. Therefore, the wiring capacitance is enlarged excessively, causing the operation speed of the semiconductor device to be reduced. When the trenches are formed, partial etching of the interlayer insulating film constituted by the silicon oxide film occurs. Thus, ions are concentrated in the bottom corners of each trench, causing a shape called “trenching” to be formed in the corners of each trench. Therefore, the wiring metal cannot easily be buried in the trench.  
       [0021] Hitherto, an LSI of a type having a structure that a DRAM (Dynamic Random Access Memory) and a logic are mixedly mounted on one chip is structured such that the alignment margin (a fringe) in the logic portion is about ¼ opening portion of the alignment margin in the DRAM owing to the difference in the design rule between the DRAM section and the logic section.  
       [0022] In an example case in which a contact hole is formed in an interlayer insulating film having the dual-damascene structure, the following step is employed: a dry etching condition with which a high selectivity with respect to the etching stopper constituted by the silicon nitride film on the lower trench metallization is used to form the contact hole in the interlayer insulating film constituted by the silicon oxide film. Then, the silicon nitride film is removed, and then the wiring metal is buried in the contact hole and trenches of the upper metallization.  
       [0023] In the logic section having a small alignment margin, a portion of the opening of the contact hole is sometimes deviated to the outside of the stopper constituted by the silicon nitride film which covers the lower trench metallization. Therefore, the interlayer insulating film constituted by the silicon oxide film which buries the side surface of the lower trench metallization easily encounters borderless etching which is cut during the step of forming the contact hole. Therefore, there arises a problem in that a fault in burring and a short-circuit fault of the wiring metal occur.  
       [0024] Hitherto, polysilane anti-reflective film is formed below the resist in the lithography step. When the resist is removed by performing O 2  ashing after the pattern has been formed, a phenomenon undesirably occurs in that polysilane is oxidized. Thus, oxidized polysilane cannot easily be removed.  
       BRIEF SUMMARY OF THE INVENTION  
       [0025] As described above, the conventional manufacturing method of semiconductor devices by using dry etching technology suffers from problems that etching at a high aspect ratio cannot easily be performed, smoothing of the overall surface of the wafer cannot easily be performed when the device region has some deviation in density of devices, the surface roughness causes defective fabrication when a miniaturized gate electrode is formed and short-circuit fault easily occurs in the edge line portion of the gate electrode when the SAC contact hole is formed.  
       [0026] Moreover, there arises a problem in that etching is interrupted owing to residues produced in the dry etching step when etching of an interlayer insulating film at a high aspect ratio is performed. Another problem arises in that a necessity for stacking a silicon nitride film to serve as an etching stopper to uniform the depths of the formed trenches and to prevent borderless etching reduces the operation speed of the semiconductor device. In addition, trenching occurring when the trenches are formed causes a fault in burying of the wiring metal. Since the alignment margin in the logic section is too small, borderless etching easily occurs when a mixed memory logic LSI is manufactured. Another problem arises in that polysilane for use to form the reflection preventing film for the resist cannot easily be removed. Thus, the conventional manufacturing method of semiconductor devices by using dry etching technology suffers from a multiplicity of problems.  
       [0027] To overcome the above-mentioned problems, an object of the present invention is to provide a method of forming a multilayered insulating film by using an organic polysilicon film made of, for example, polysilane, a removing method and a method of forming an etching mask.  
       [0028] The manufacturing method of semiconductor devices by using dry etching technology uses an organic silicon film made of, for example, polysilane, which is able to easily form a smooth surface by a coating process and which can easily be dry-etched and smoothed. The organic silicon film is laminated with an insulating film such as silicon oxide film or a silicon nitride film, a metallic film for use in metallization or the like. Alternatively, the organic silicon film is formed on a semiconductor substrate such that the organic silicon film forms a portion of the foregoing element while using the obtained structure as a suppression layer or the like for improving the processing shape of the insulating film portion, the organic silicon film is microfabricated. Thus, a portion comprising an interlayer insulating film having a complicated dual-damascene structure is formed. Then, for example, oxygen is introduced into the organic silicon film so as to change the organic silicon film into an insulating film constituted by an organic silicon film oxide film and the like. Thus, a required constituting element of a semiconductor device is provided.  
       [0029] For example, some of the organic silicon film, which has the silicon and silicon bonds as the main chain thereof, has anti-reflective property. The organic silicon film cannot be, as it is, used as an insulating film of a semiconductor device. When a step of introducing oxygen or the like is performed, such organic silicon film can be employed as the insulating film of the semiconductor device.  
       [0030] As described above, according to the present invention, control of the shape and the depth of the metallization trench, formation of a contact hole having a high aspect ratio, prevention of borderless etching and improvement of problems occurring in a smoothing step which have been difficult for the conventional dry etching step can be performed. Moreover, a new method of removing polysilane employed as an anti-reflective film is provided.  
       [0031] Specifically, a manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprising the steps of: forming a organic silicon film on a semiconductor substrate; dry-etching the organic silicon film to form a portion which must be formed by the insulating film of the semiconductor device by using the organic silicon film; and changing the organic silicon film into an insulating film so that the portion of the semiconductor device constituted by the insulating film is formed.  
       [0032] It is preferable that the organic silicon film has silicon and silicon bonding as a main chain thereof.  
       [0033] It is preferable that the method of manufacturing semiconductor devices has a structure that at least any one of oxygen, nitrogen, hydrogen and carbon elements is introduced into the organic silicon film following dry etching of the organic silicon film so that the organic silicon film is changed to any one of organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film.  
       [0034] It is preferable that the step of introducing at least any one of oxygen, nitrogen, hydrogen and carbon elements into the organic silicon film is performed by using any one of a RIE method, an ashing method and an ion implanting method using ions of the elements or a mixture of the elements.  
       [0035] It is preferable that the step of introducing at least any one of oxygen, nitrogen, hydrogen and carbon elements into the organic silicon film is performed by performing heat treatment in a gas atmosphere composed of the element or a mixture of the elements.  
       [0036] It is preferable that the portion constituted by the insulating film of the semiconductor device is formed by at least any one of an interlayer insulating film between the surface of the semiconductor substrate and a lower metallization layer of a dual-damascene structure, an insulating film for burying the space between wiring metals formed in each metallization layer of the dual-damascene structure and an interlayer insulating film between upper and lower metallization layers of the dual-damascene structure.  
       [0037] It is preferable that the organic silicon film is laminated on the insulating film and the dry etching of the organic silicon film is performed such that the insulating film is employed as a suppression layer of the dry etching.  
       [0038] It is preferable that the portion constituted by the insulating film of the semiconductor device is formed by an interlayer insulating film including a contact hole of the dual-damascene structure formed on the semiconductor substrate and a trench in each of the upper and lower metallization layers of the dual-damascene structure.  
       [0039] It is preferable that the step of forming the contact hole incorporates the steps of: coating the overall upper surface of the lower metallization layer with the organic silicon film; providing the contact hole which reaches the upper surface of the wiring metal in the lower metallization layer for the organic silicon film by selectively dry-etching the organic silicon film; and changing the organic silicon film in which the contact hole has been formed into any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film.  
       [0040] It is preferable that the lower metallization layer is constituted by a trench metallization buried in the insulating film of the semiconductor substrate, and the upper surface of the insulating film suppresses borderless etching when the contact hole is formed.  
       [0041] It is preferable that the step of forming the trench includes the steps of: coating the overall upper surface of the insulating film on the semiconductor substrate with the organic silicon film; removing the portion of the organic silicon film in which the trench has been formed by selectively dry-etching the organic silicon film; and changing the organic silicon film subjected to the removal step into an insulating film constituted by any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film.  
       [0042] It is preferable that the step of forming the interlayer insulating film includes the steps of: forming the contact hole in the insulating film on the semiconductor substrate; coating the overall surface of the insulating film with the organic silicon film such that the contact hole is buried; removing a portion of the upper metallization layer including an opening portion of the contact hole in which the trench has been formed and the organic silicon film in the contact hole by selectively dry-etching the organic silicon film; and changing the organic silicon film subjected to the removal step into an insulating film constituted by any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film.  
       [0043] It is preferable that the manufacturing method of semiconductor devices has a structure that the step of removing the organic silicon film is performed such that the upper surface of the insulating film on the semiconductor substrate controls the dry etching so that the organic silicon film is selectively etched.  
       [0044] It is preferable that the step of forming the interlayer insulating film includes a step of coating the overall upper surface of a first insulating film on the semiconductor substrate on which the lower metallization layer has been formed with the organic silicon film, a first selective dry etching step of forming a contact hole which reaches the upper surface of the metallization of the lower metallization layer, a step of changing the organic silicon film having the contact hole into a second insulating film constituted by any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film, a step of coating the overall upper surface of the second insulating film with the organic silicon film, a second selective dry etching step of forming a trench in the upper metallization layer connected to the contact hole formed on the second insulating film by removing the organic silicon film in the portion of the upper metallization layer including the opening portion of the contact hole on which the trench has been formed and the inside portion of the contact hole and a step of changing the organic silicon film having the trench in the upper metallization layer into a third insulating film constituted by any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film.  
       [0045] It is preferable that the manufacturing method of semiconductor devices has a structure that the first insulating film suppresses borderless etching occurring in the periphery of the lower metallization layer in the first dry etching step, and the second insulating film controls the second selective dry etching step of forming the trench in the upper metallization layer.  
       [0046] It is preferable that the step of forming the interlayer insulating film includes the steps of: forming any one of a first organic silicon oxide film, an inorganic silicon oxide film and a silicon oxide film on the insulating film on the semiconductor substrate on which the lower metallization layer has been formed; forming a stopper for dry etching constituted by an organic silicon film on any one of the first organic silicon oxide film, the inorganic silicon oxide film or the silicon oxide film; providing an opening portion for forming the contact hole which reaches the lower metallization layer for the stopper; forming any one of a second organic silicon oxide film, an inorganic silicon oxide film or a silicon oxide film such that the stopper having the opening portion is buried; forming an etching mask for forming a trench of the metallization layer to correspond to the opening portion; and continuously and selectively dry-etching any one of the first and second organic silicon oxide film, the incorporate silicon oxide film or the silicon oxide film by using the etching mask and the stopper having the opening portion.  
       [0047] It is preferable that a step is included in which the stopper for dry etching constituted by the organic silicon film is subjected to the step of continuously and selectively dry-etching the first and second organic silicon oxide film, the inorganic silicon oxide film or the silicon oxide film and changed into an organic silicon oxide film so as to be integrated as a portion of the interlayer insulating film.  
       [0048] The manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprising: the steps of: forming an organic silicon film having bondings of silicon and silicon as the main chains thereof on a semiconductor substrate and selectively introducing any one of oxygen, nitrogen, hydrogen and carbon elements into at least the surface of the organic silicon film; forming a portion of the semiconductor device constituted by insulating material by performing selective dry etching such that the surface of the organic silicon film is used as a mask; and introducing at least any one of oxygen, nitrogen, hydrogen and carbon elements into the organic silicon film after the organic silicon film has been dry-etched to integrate both of the surface of the organic silicon film and the inside portion of the organic silicon film as any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film.  
       [0049] It is preferable that the manufacturing method of semiconductor devices is structured to perform selective dry etching such that the surface of the organic silicon film is used as a mask to process the edge in the periphery of the opening portion of the mask to be rounded.  
       [0050] The manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprising: the steps of: forming an organic silicon film having bondings of silicon and silicon as the main chains thereof on a semiconductor substrate and selectively introducing any one of oxygen, nitrogen, hydrogen and carbon elements into at least the surface of the organic silicon film; forming a portion of the semiconductor device constituted by insulating material by performing selective dry etching such that the surface of the organic silicon film is used as a mask; introducing at least any one of oxygen, nitrogen, hydrogen and carbon elements into the organic silicon film after the organic silicon film has been dry-etched to make the surface of the organic silicon film and the inside portion of the organic silicon film to be constituted by different type films which are an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film; and removing the mask by performing selective etching of the surface of the organic silicon film and the inside portion of the organic silicon film.  
       [0051] The manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprises: the steps of: using an organic silicon film to form an anti-reflective film for use in a photolithography step on the upper surface of the insulating film on a semiconductor substrate; introducing any one of oxygen, nitrogen, hydrogen and carbon elements into the organic silicon film after the photolithography step has been completed to constitute the anti-reflective film by any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film; and integrating the anti-reflective film with the insulating film.  
       [0052] The manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprises: the steps of: using an organic silicon film to form an anti-reflective film for use in a photolithography step on the upper surface of the insulating film on a semiconductor substrate; introducing any one of oxygen, nitrogen, hydrogen and carbon elements into the organic silicon film after the photolithography step has been completed to constitute the anti-reflective film by any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film; and removing the anti-reflective film by etching by using selective etching of the anti-reflective film and the insulating film subjected to the process.  
       [0053] A manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprises: the steps of: forming a thermal oxide film on a semiconductor substrate; forming a silicon oxide film on the organic silicon film by coating the thermal oxide film with an organic silicon film; forming an opening portion which reaches the surface of the semiconductor substrate on a multilayered film constituted by the silicon oxide film and the organic silicon film; changing the organic silicon film to a silicon nitride film by introducing nitrogen into the organic silicon film subjected to the step; and forming a trench on the semiconductor substrate by using a multilayered film constituted by the silicon oxide film and the silicon nitride film as a mask.  
       [0054] A manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprises: the steps of: coating a semiconductor substrate with an organic silicon film to form the pattern of the organic silicon film by using a resist as a mask such that a device region on the semiconductor substrate is covered; and forming an isolation trench in the semiconductor substrate by using the organic silicon film, the pattern of which has been formed, and the resist as masks and changing the organic silicon film to a silicon nitride film by introducing nitrogen into the organic silicon film.  
       [0055] It is preferable that the manufacturing method of semiconductor devices comprises the steps of: furthermore coating the overall upper surface of the semiconductor substrate, on which the isolation trench has been formed, with the organic silicon film such that the isolation trench is buried; smoothing the surface of the organic silicon film by using the semiconductor as a suppression layer; and changing the organic silicon film into any one of a silicon oxide film, an organic silicon oxide film and an inorganic silicon oxide film by introducing oxygen into the organic silicon film with which the isolation trench is buried.  
       [0056] A manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprises the steps of: forming a gate insulating film on a semiconductor substrate and forming at least one metallic film on the gate insulating film; forming the pattern of the organic silicon film in a region of the semiconductor substrate which has been covered with the mask and in which the gate electrode has been formed such that a resist is used as a mask; forming the pattern of a gate electrode constituted by the metallic film in the region in which the gate electrode has been formed such that the organic silicon film, the pattern of which has been formed, and the resist are used as masks; and changing the organic silicon film, the pattern of which has been formed, into a nitride film by introducing nitrogen into the organic silicon film.  
       [0057] A manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprises the steps of: forming a gate insulating film on a semiconductor substrate, forming at least one metallic film on the gate electrode insulating film and forming the pattern of a gate electrode constituted by the metallic film on a region of the semiconductor substrate which is covered with the metallic film and in which a gate electrode will be formed; covering the gate electrode with a silicon nitride film and depositing a first insulating film on the overall upper surface of the semiconductor substrate such that the gate electrode is buried; smoothing the surface of the first insulating film and coating the surface of the smoothed first insulating film with an organic silicon film; forming a contact hole which reaches the first insulating film in the organic silicon film by selectively removing the organic silicon film which covers adjacent to the gate electrode in which either of a source or a drain will be formed and a portion of the gate electrode adjacent to the source or the drain by performing dry etching using a resist as a mask; a step of exposing the silicon nitride film to the bottom portion of the contact hole by dry-etching the first insulating film by using the resist and the organic silicon film as masks; in a self-aligning manner, exposing the surface of either of region on the surface of the semiconductor substrate in which the source will be formed or a region in which the drain will be formed; and integrating the organic silicon film with the first insulating film and using the contact hole to connect metallizations by changing the organic silicon film into a second insulating film constituted by any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film.  
       [0058] A manufacturing method of semiconductor devices by using dry etching technology according to the present invention comprises the steps of: forming a gate insulating film on a semiconductor substrate, forming at least one metallic film on the gate insulating film and forming the pattern of a gate electrode constituted by the metallic film in a region of the semiconductor substrate which is covered with the metallic film and in which the gate electrode will be formed; furthermore covering the first silicon oxide film by covering the gate electrode with a silicon nitride film and depositing the gate electrode on the silicon nitride film; forming a contact hole which reaches the first silicon oxide film in the organic silicon film by coating the overall upper surface of the semiconductor substrate with the organic silicon film and by selectively removing the organic silicon film which covers a region adjacent to the gate electrode in which a source or a drain will be formed and a portion of the gate electrode adjacent to the portion in which the source or the drain will be formed by performing dry etching which uses a resist as a mask; removing the first silicon oxide film exposed to the bottom surface of the contact hole by introducing oxygen into the organic silicon film to change the organic silicon film into a second silicon oxide film and by performing dry etching such that the second silicon oxide film is used as a mask; and in a self-alignment manner, exposing the surface of the region which has been formed on the semiconductor substrate and in which the source or the drain will be formed and using the contact hole for connecting metallizations by further removing the silicon nitride film and gate insulating film exposed owing to removal of the first silicon oxide film.  
       [0059] A dry etching method according to the present invention comprises: a step of forming an organic silicon film having main chains thereof constituted by bondings of silicon and silicon on a semiconductor substrate and forming a portion of the semiconductor device constituted by insulating material dry-etching at least the organic silicon film; and a step of changing a portion of the organic silicon film into an insulating film constituted by any one of an organic silicon oxide film, an inorganic silicon oxide film, a silicon oxide film and a silicon nitride film by processing the processed organic silicon film by executing at least heat treatment which is performed in O 2 , N 2  or H 2  gas, heat treatment which is performed in O 2 , N 2  or H 2  plasma or implantation of O 2 , N 2  or H 2  ions and heat treatment.  
       [0060] Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter. 
     
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
     [0061] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.  
     [0062]FIGS. 1A to  1 F are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a first embodiment;  
     [0063]FIGS. 2A to  2 C are cross sectional views showing steps for describing effects of the manufacturing method of semiconductor devices according to the first embodiment;  
     [0064]FIGS. 3A and 3B are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a second embodiment;  
     [0065]FIGS. 4A and 4B are cross sectional views showing steps for describing effects of the manufacturing method of semiconductor devices according to the second embodiment;  
     [0066]FIGS. 5A to  5 D are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a third embodiment;  
     [0067]FIG. 6A to  6 I are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a fourth embodiment;  
     [0068]FIGS. 7A to  7 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a fifth embodiment;  
     [0069]FIGS. 8A to  8 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a sixth embodiment;  
     [0070]FIGS. 9A to  9 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a seventh embodiment;  
     [0071]FIGS. 10A to  10 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to an eighth embodiment;  
     [0072]FIGS. 11A to  11 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a ninth embodiment;  
     [0073]FIGS. 12A and 12B are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a tenth embodiment;  
     [0074]FIGS. 13A to  13 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to an eleventh embodiment;  
     [0075]FIGS. 14A to  14 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a twelfth embodiment;  
     [0076]FIGS. 15A to  15 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a thirteenth embodiment;  
     [0077]FIGS. 16A to  16 E are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a fourteenth embodiment;  
     [0078]FIGS. 17A to  17 D are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a fifteenth embodiment;  
     [0079]FIGS. 18A to  18 E are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a sixteenth embodiment;  
     [0080]FIGS. 19A to  19 D are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a seventeenth embodiment;  
     [0081]FIGS. 20A to  20 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to an eighteenth embodiment;  
     [0082]FIGS. 21A to  21 E are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a nineteenth embodiment;  
     [0083]FIGS. 22A to  22 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a twentieth embodiment;  
     [0084]FIGS. 23A to  23 C are cross sectional views showing steps of a manufacturing method of semiconductor devices according to a twenty-first embodiment; and  
     [0085]FIG. 24 is a diagram showing a dry etching apparatus for use in the manufacturing method of semiconductor devices according to the present invention.  
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0086] Referring to the drawings, embodiments of the present invention will now be described. Referring to FIGS. 1A to  1 F and FIGS. 2A to  2 C, a first embodiment of the present invention will now be described. FIGS. 1A to  1 F are diagrams showing the structure of an interlayer insulating film having a contact hole which is required to constitute a dual-damascene structure. FIGS. 2A to  2 C are diagrams showing a method of forming the dual-damascene structure by performing dry etching and problems experienced with the method.  
     [0087] The interlayer insulating film for forming the dual-damascene structure is subjected to first trench formation for forming a first trench metallization, second trench formation for forming a second trench metallization and formation of a contact hole for connecting the first and second trench portions to each other.  
     [0088] As shown in FIG. 1A, an insulating film  2  is formed on a silicon substrate  1 . To bury the first trench formed in the insulating film  2  a wiring metal  3  having the periphery coated with a silicon nitride film  4  is formed. The material of the insulating film  2  is usually a silicon oxide film. The surface of the insulating film  2  is smoothed by CMP by using the silicon nitride film  4  as a stopper (a suppression layer for use in a polishing step). Since the step of forming the trench metallization in the first layer shown in FIG. 1A is not directly related to the first embodiment, the step is omitted from description.  
     [0089] Then, an insulating film made of the same material as that of the smoothed insulating film  2  is stacked on the insulating film  2 , as shown in FIG. 1B. Then, anisotropic etching is performed by RIE so that a contact hole  5  is formed. At this time, the silicon nitride film  4  serves as an etching stopper (a suppression layer against etching).  
     [0090] Then, as shown in FIG. 1C, the overall surface is coated with polysilane  6 . The thickness of the polysilane  6  is made to be the same as the second trench. Since the polysilane  6  flows, the inside portion of the contact hole  5  is buried with the polysilane  6 . Moreover, the surface of the polysilane  6  is sufficiently smoothed in a coating step so that the depth of the second trench is uniformed over the surface of the wafer.  
     [0091] Then, a resist  7  is applied to form the second trench in the polysilane  6 . To form the second trench, an opening portion is formed. The resist  7  is used as a mask, the polysilane  6  is anisotropically etched by RIE under condition that the polysilane  6  has a high etching selective ratio with respect to the insulating film  2 . Thus, as shown in FIG. 1D, the second trench  8  can be formed by using the insulating film  2  and the silicon nitride film  4  as etching stoppers, the formation being enabled without any exertion of an influence on the shape of the contact hole  5 .  
     [0092] The RIE etching conditions were such that the pressure in a chamber was 75 mTor, the high frequency power was 300 W and flux ratio of mixed gas Cl 2 /O 2  was 75 sccm/10 sccm. Under the foregoing conditions, a high etching selective ratio of about 100 was realized between the insulating film  2  constituted by a silicon oxide film (SiO 2 ) and the polysilane  6 .  
     [0093] The polysilane  6  can easily and precisely be anisotropically etched by the RIE. Moreover, an etching selective ratio of about 50 can be realized with respect to the silicon nitride film  4 . Therefore, the polysilane  6  which buries the inside portion of the contact hole  5  can completely be removed such that the silicon nitride film  4  is left.  
     [0094] Then, an O 2  ashing step is performed to remove the resist  7 . At this time, the trench of the silicon substrate  1  is raise to about 250° C. so that oxygen is introduced into the polysilane  6  owing to thermal diffusion. Therefore, the polysilane  6  is changed to a silicon oxide film so as to be a portion of the insulating film  2 . The silicon oxide film changed from the polysilane  6  has a crystal structure near SiO 2  if the degree of oxidation is intense. Also from a viewpoint of electrical properties, the silicon oxide film can be considered as an insulating film constituted by SiO 2 .  
     [0095] Thus, the polysilane  6  is formed into a portion of the insulating film  2 , as shown in FIG. 1E. Thus, the interlayer insulating film  2  having the dual-damascene structure incorporating the contact hole  5  and the second trench  8  can precisely be formed.  
     [0096] Then, as shown in FIG. 1F, the silicon nitride film  4  covering the upper portion of the wiring metal  3  is removed by the RIE etching conditions with respect to a silicon nitride film. The material of the wiring metal is deposited to bury the contact hole  5  and the second trench  8 . The material of the wiring metal may be Al—Cu or Cu. Then, the insulating film  2  is used as a stopper to remove a metallization removal portion  3   a  deposed excessively by the CMP. Thus, an excellent dual-damascene structure having a shape which is controlled precisely can be formed.  
     [0097] Referring to FIGS. 2A to  2 C, other important advantages of the method of forming the interlayer insulating film having the dual-damascene structure will now be described. Referring to FIG. 2A, a situation in which misalignment of the etching mask takes place when the contact hole  5  of the insulating film  2  is formed will now be described.  
     [0098] If etching stoppers are unevenly distributed in the plane when the surface of the insulating film made of SiO 2  and the like is smoothed by the CMP, the overall surface of the wafer cannot uniformly be smoothed.  
     [0099] Therefore, the step of forming the contact hole  5  allowed to proceed to a state shown in FIG. 2A encounters a fact that the thickness of the insulating film  2  in a state before the contact hole is formed includes a somewhat dispersion.  
     [0100] To form the contact hole  5 , which is able to reliably reach the silicon nitride film  4  which covers the wiring metal  3 , in the insulating film encountered dispersion in the thickness, excessive anisotropic RIE must be performed to realize a thickness larger than a predetermined thickness by 20% to 30%.  
     [0101] If the etching mask encounters misalignment, the silicon nitride film  4  cannot serve as the etching stopper in the misaligned portion. Therefore, excessive etching occurs as shown in FIG. 2A, causing a fault in wiring. The above-mentioned excessive etching occurring in the bottom of the contact hole is called “borderless etching”.  
     [0102] Hitherto, the interlayer insulating film having the dual-damascene structure has been performed such that the thickness of the insulating film  2  is the thickness shown in FIG. 1E. Moreover, the contact hole  5  is formed by the anisotropic RIE until the silicon nitride film  4  is exposed to the outside. Then, the second trench  8  is formed by the anisotropic RIE.  
     [0103] Therefore, the thickness of the insulating film  2  when the contact hole  5  is formed is enlarged excessively. Thus, the anisotropic RIE which must be carried out excessively is performed in a large quantity. Since anisotropic RIE is furthermore performed when the second trench  8  is formed, the borderless etching is subjected to two times of anisotropic RIE operations. As a result, occurrence of the borderless etching is a critical problem which must be solved when the step of forming the interlayer insulating film having the dual-damascene structure is performed.  
     [0104] In the first embodiment, the second trench  8  is formed by using the polysilane  6 . Therefore, the thickness of the insulating film  2  when the contact hole  5  is formed is small. Hence it follows that borderless etching of the insulating film  2  shown in FIG. 2A can be prevented. Since the insulating film  2  is formed by using the polysilane which can easily be fabricated and a high etching selective ratio is realized with respect to the insulating film  2 , there is no apprehension that borderless etching further proceeds in the anisotropic RIE for removing the polysilane in the contact hole  5 , as shown in FIG. 2B.  
     [0105] Then, as shown in FIG. 2C, O 2  ashing is performed to remove the resist  7  and oxidation of the polysilane  6  are simultaneously be performed. Then, the wiring metal is buried and smoothing is performed so that dual-damascene structure free of excessive borderless etching is formed.  
     [0106] The organic silicon having the main chains thereof which are the bondings of silicon and silicon cannot be employed as the material of the interlayer insulating film as it is. If O 2  is introduced into the material by using a method such as O 2  ashing, the organic silicon such as polysilane is changed to an insulating material near SiO 2  from electrical and mechanical viewpoints. Therefore, the changed material can be used to form a required interlayer insulating film.  
     [0107] The first embodiment is effective as a method of manufacturing a mixed memory logic LSI incorporating a DRAM section and a logic section are mounted on one chip. Since the alignment margin in the logic section is smaller than that in the memory section as described above, borderless etching easily occurs in the logic section. When the structure according to the first embodiment is employed, the mixed memory logic LSI can be manufactured at a high manufacturing yield.  
     [0108] Referring to FIGS. 3A, 3B,  4 A and  4 B, a second embodiment of the present invention will now be described. As shown in FIG. 3A, a trench metallization in the first layer is formed in the insulating film  2 . The silicon nitride film  4  is used as a stopper to perform a smoothing step, and the overall surface is coated with the polysilane  6 . The resist  7  and the anisotropic RIE are employed to form the contact hole  5  in the polysilane  6 . Then, the resist  7  is removed by performing O 2  ashing. Simultaneously, the polysilane  6  is changed to the insulating film  2  constituted by the silicon oxide film. Thus, the shape of the insulating film  2  shown in FIG. 1B according to the first embodiment is formed. The foregoing insulating film  2  is used to perform the steps following the step shown in FIG. 1.  
     [0109] A situation in which misalignment has occurs when the resist mask  7  for the contact hole  5  is formed by the method according to the second embodiment is shown in FIGS. 4A and 4B. In the second embodiment, the contact hole  5  is formed in the polysilane  6  if the misalignment shown in FIG. 4A occurs. Therefore, a satisfactorily high etching selective ratio can be realized with respect to the insulating film  2 . Thus, the insulating film  2  serves as the etching stopper so that the controllability of the anisotropic RIE is improved. As a result, borderless etching can be prevented.  
     [0110] Then, as shown in FIG. 4B, the O 2  ashing step is performed to remove the resist  7 . Simultaneously, the polysilane  6  is changed to the silicon oxide film to make the silicon oxide film to be a portion of the insulating film  2 . Then, the silicon nitride film  4  covering the upper portion of the silicon nitride film  4  is removed. As a result, the steps for forming the dual-damascene structure following the step shown in FIG. 2C according to the first embodiment can be employed.  
     [0111]FIG. 4B shows a characteristic that any borderless etching as shown in FIG. 2C does not occur. Although the area of connection between the wiring metal for burying the contact hole  5  and the wiring metal  3  in the first layer is reduced, the defective wiring due to borderless etching can significantly be prevented.  
     [0112] When the structure according to the second embodiment is employed, the deterioration in the manufacturing yield of the logic section of the mixed memory logic LSI owing to the borderless etching can significantly be suppressed.  
     [0113] Although the second embodiment has been described as a method of forming the contact hole  5  having the dual-damascene structure, the present invention is not limited to the foregoing description. The structure may be applied to formation of a contact hole having a usual multilayered metallization.  
     [0114] Referring to FIGS. 5A to  5 D, a third embodiment of the present invention will now be described. The third embodiment is different from the second embodiment in the insulating film  2  shown in FIG. 3A is constituted by polysilane  6 .  
     [0115] As shown in FIG. 5A, the silicon substrate  1  is coated with the polysilane  6 . Since the silicon substrate  1  has been subjected to a wafer process, a variety of elements of the semiconductor device have been mounted. Therefore, the surface of the silicon substrate  1  usually has complicated step differences.  
     [0116] Since the polysilane  6  flows, the step differences are buried by coating. Moreover, any surface polishing is not required because the overall surface of the wafer has satisfactory flatness to permit execution of the dry etching process.  
     [0117] Then, the resist (not shown) is used as a mask to perform the anisotropic RIE to form the first trench in the polysilane  6 . As described above, the polysilane can easily be subjected to the anisotropic RIE and the surface of the polysilane is flat. Therefore, any etching stopper is not required to form the first groove having uniform depths from a viewpoint of practical use can be formed by only controlling the conditions of the RIE process.  
     [0118] The step of covering the wiring metal  3 , the step of burying the silicon nitride film  4  and the step of removing excess wiring metal and silicon nitride film left on the polysilane  6  are combined so that the first trench metallization shown in FIG. 5A is formed.  
     [0119] As shown in FIG. 5A, the polysilane  6  is changed to the silicon oxide film in the step of removing the resist (not shown) for use to form the first trench by O 2  ashing. To describe the difference from the second embodiment, the silicon oxide film is illustrated as the polysilane  6 .  
     [0120] Then, as shown in FIG. 5B, the wiring metal  3  covered with the insulating film  2  constituted by the silicon oxide film and the silicon nitride film  4  is coated with the polysilane  6 . Then, the pattern of the resist  7  is formed to align the opening position of the contact hole.  
     [0121] Then, as shown in FIG. 5C, the resist  7  is used as a mask to form the contact hole  5 , which reaches the silicon nitride film  4 , in the polysilane  6 . The resist  7  is removed by O 2  ashing. Simultaneously, the polysilane  6  is changed to the insulating film  2  constituted by the silicon oxide film. Moreover, the silicon nitride film  4  on the wiring metal  3  is removed. Thus, as shown in FIG. 5D, all of the structures of the insulating film  2  shown in FIG. 3B according to the second embodiment can be formed by using polysilane  6  as the material.  
     [0122] Since the polysilane  6  changed to the insulating film  2  has the material properties similar to those of the integrated insulating film  2 , the manufacturing process following the process shown in FIG. 1C according to the first embodiment can be employed.  
     [0123] The merit of the third embodiment obtainable from formation of the first trench metallization shown in FIG. 5A with polysilane lies in that a flat surface constituted by the polysilane can be obtained if the surface of the silicon substrate  1  has step differences. The conventional method with which the insulating film  2  is deposited cannot prevent formation of a stepped portion also on the surface of the insulating film  2 . Therefore, the first trench having a uniform width and depth cannot be formed.  
     [0124] When the insulating film  2  is deposited thick and the surface is smoothed by performing CMP, the shape of the first trench can be improved. However, the problem of uneven density of the stoppers for use in the polishing step remains to be solved. Therefore, the overall surface of the wafer cannot easily be smoothed in ordinary cases. When the polysilane  6  is applied, the foregoing problem can considerably easily be prevented. As a matter of course, the third embodiment attains a similar effect of preventing borderless etching to that obtainable from the second embodiment.  
     [0125] A fourth embodiment of the present invention will now be described with reference to FIGS. 6A to  6 I. Hitherto, formation of a contact hole having a high aspect ratio or formation of a trench encounters film thinning of the resist which is used as the mask for the anisotropic RIE step. As a result, there arises a problem the thickness of the residual film of the resist is excessively reduced to serve as the mask.  
     [0126] To prevent the foregoing problem, a method may be employed which has the steps of: forming a reversed pattern of the opening portion of the contact hole; changing the surface of the polysilane existing in the outer portion of the exposed opening portion to the insulating film constituted by the silicon oxide film by performing O 2  RIE or implantation of O 2  ions; opening the polysilane by using the insulating film as a mask. Thus, a satisfactory contact hole and the trench can be formed.  
     [0127] That is, as shown in FIG. 6A, the surface of the first trench metallization constituted by the insulating film  2  on the silicon substrate  1  and the wiring metal  3  covered with the silicon nitride film  4  is coated with the polysilane  6 . Then, the pattern of the resist  7  is formed to cover the portion in which the contact hole will be formed.  
     [0128] Then, the resist  7  is used as a mask to introduce O 2  ions into the surface of the polysilane  6  by using an O 2  RIE machine as indicated with an arrow shown in FIG. 6A. Then, O 2  ashing is performed to remove the resist  7 . Thus, as shown in FIG. 6B, the insulating film  2  constituted by the silicon oxide film is formed on the surface of the polysilane  6 . The ashing of the resist  7  is performed minimally in quantity to prevent change of the surface of the polysilane  6  covered with the lower portion of the resist  7  to the silicon oxide film.  
     [0129] Since the etching selective ratio of the polysilane  6  with respect to the insulating film  2  can be raised as described above, the resist  7  is removed and the anisotropic RIE step is performed by using the insulating film  2  as a mask as shown in FIG. 6C. Thus, the contact hole  5  can be formed in the polysilane  6  by using the silicon nitride film  4  as the etching stopper.  
     [0130] Then, treatment similar to the O 2  ashing step is performed in the same chamber in which RIE has been performed so that O 2  ions are introduced from the inner surface of the contact hole  5  opened in the polysilane  6 . As a result, the overall body of the polysilane  6  can be changed to the insulating film constituted by the silicon oxide film.  
     [0131] Thus, as shown in FIG. 6D, both of the insulating film  2  for use to form the first trench and the insulating film for performing formation of the contact hole  5  and used as the etching mask can be formed as the integrated insulating film  2  constituted by the silicon oxide film.  
     [0132] At this time, the edge of the periphery of the opening portion of the insulating film  2   a  used as the mask is rounded by the anisotropic RIE. When rounding is excessively occurs to raise a problem in the structure, the insulating film  2   a  is required to be removed by CMP, as shown in FIG. 6D.  
     [0133] Note that attention must be focused on a fact that the rounded portion of the edge adjacent to the opening portion has an effect of smoothing the burying step when the wiring metal is buried in the contact hole when the contact hole of the insulating film  2  shown in FIG. 6D has a high aspect ratio.  
     [0134] Then, as shown in FIG. 6E, the overall surface is coated with the polysilane  6  such that the contact hole is buried. Then, reversed patterning is performed to cover the opening portion of the second trench by using the resist  7 . The resist  7  is used as a mask to introduce oxygen into the surface of the polysilane  6  by using the O 2  RIE machine.  
     [0135] Then, the steps shown in FIGS. 6B and 6C are repeated as shown in FIGS. 6F and 6G so that a treatment similar to the O 2  ashing is continuously performed in the same chamber. The insulating film  2  completely constituted by the silicon oxide film and having the dual-damascene structure can be formed on the silicon substrate  1 , as shown in FIG. 6H.  
     [0136] Then, as shown in FIG. 6I, the silicon nitride film  4  on the upper portion of the wiring metal  3  is removed, and the wiring metal is depth to bury the contact hole  5  and the second trench  8 . The wiring metal may be Al—Cu or Cu. Then, the wiring metal removal portion  3   a  which has excessively be deposited is removed by CMP by using the insulating film  2  as a stopper. Thus, an excellent dual-damascene structure having a shape which is precisely controlled can be formed.  
     [0137] When the anisotropic RIE results in excessive rounded edge adjacent to the opening portion of the insulating film a used as the etching mask to cause a problem in term of the structure to arise, the CMP step is furthermore performed to remove the insulating film removal portion  2   a  by polishing.  
     [0138] When the second trench  8  shown in FIG. 6H has a high aspect ratio, attention must be focused on the fact that the insulating film removal portion  2   a  generated adjacent to the opening portion when the wiring metal is buried in the second trench  8  and shown in FIG. 6I has the effect of smoothing the burying step.  
     [0139] Referring to FIGS. 7A to  7 C, a fifth embodiment of the present invention will now be described. Referring to FIG. 7A, the step until the overall surface is coated with the polysilane  6  such that the contact hole is buried is similar to that according to the fourth embodiment shown in FIG. 6E.  
     [0140] In the fourth embodiment, the resist  7  is formed by performing reversed patterning such that the opening portion of the second trench  8  of the polysilane  6  is covered. The fifth embodiment is structured such that the overall surface is coated with the polysilane  6 . Then, the resist  7  is used to open the formation position of the second trench  8  by performing a usual patterning.  
     [0141] Since the insulating film  2  can be formed by using the polysilane  6  which can easily be fabricated, the film thinning of the resist mask can be reduced during the anisotropic RIE step. Therefore, as shown in FIG. 7B, the resist  7  can be used as the etching mask to perform the formation of the second trench  8  and remove the polysilane with which the contact hole  5  is filled.  
     [0142] As shown in FIG. 7C, the polysilane  6  is changed to the insulating film  2  constituted by the silicon oxide film simultaneously with the step of removing the resist  7  by O 2  ashing. Thus, the interlayer insulating film  2  having the dual-damascene structure on the silicon substrate  1  can be formed into the insulating film constituted by an integrated silicon oxide film.  
     [0143] Since the anisotropic RIE enables the rounded portion generated at the edge adjacent to the opening portion of the resist  7  to be removed together with the resist  7 , the foregoing method has a merit when the rounded portion is undesirable as the processed shape. When the step of burying the material of the metallization shown in FIG. 1F is added to be performed successively, a dual-damascene structure can be formed.  
     [0144] In the first to fifth embodiments, the RIE using the O 2  plasma or implantation of O 2  ions is employed to form the insulating film constituted by the silicon oxide film. The method is not limited to the foregoing methods.  
     [0145] Alternatively, any one of the following methods may be employed: thermal oxidation which is performed in an O 2  atmosphere, ashing which uses O3 plasma, irradiation with ultraviolet rays and dipping opening portions into section in which sulfuric acid and hydrogen peroxide are mixed. Also the method enables polysilane to be changed to the insulating film constituted by the silicon oxide film.  
     [0146] The organic silicon film such as polysilane, can be changed to an insulating film in various stages owing to the degree of oxidation which include: an organic silicon oxide film in which carbon is left in the oxide film; an inorganic silicon oxide film from which carbon has been removed, which has a crystal structure having irregularity as compared with SiO 2  and which contains OH groups; and a silicon oxide film subjected to further heat treatment to have the crystal structure similar to that of SiO 2 .  
     [0147] For example, the trench metallization in the first layer and the contact hole are formed by using organic silicon oxide film. Then, organic silicon is applied to form the second trench to performing ashing in a gas composed of only O 2 . In this case, carbon may be left in organic silicon by controlling the temperature. Alternatively, heat treatment may be performed in an atmosphere of mixed gas of O 2  and CO 2  to change the organic silicon constituting the second trench to an organic silicon oxide film having a dielectric constant similar to that of the organic silicon oxide film.  
     [0148] When organic silicon film such as polysilane, is subjected to heat treatment which is performed in a mixed gas atmosphere of O 2  and CO 2  or when the organic silicon is subjected to RIE using CO or when implantation of CO ions is performed, the organic silicon oxide film having a dielectric constant similar to that of the organic silicon oxide film can be formed.  
     [0149] When organic silicon film such as polysilane, is subjected to ashing using a gas containing only H 2  or a mixed gas of H 2  and O 2  of when RIE, implantation of ions or heat treatment is performed, the inorganic silicon oxide film can be formed.  
     [0150] When the organic silicon such as polysilane, is subjected heat treatment in a mixed gas atmosphere of N 2  and O 2  or when ashing, RIE or implantation of ions is performed by using the foregoing gas, the silicon oxide nitride film or a silicon nitride film can be formed.  
     [0151] The silicon oxide film, the silicon oxide nitride film and silicon nitride film may be employed to a dry etching process of the contact hole and the trench according to the present invention.  
     [0152] Referring to FIGS. 8A to  8 C, a sixth embodiment of the present invention will now be described. As shown in FIG. 8A, the sixth embodiment is structured such that formation of the interlayer insulating film having the dual-damascene structure is performed by using an organic silicon oxide film  2   b  until the step of formation of the trench metallization in the first layer and the contact hole. Since the organic silicon oxide film  2   b  is formed by a method similar to that at the third embodiment described with reference to FIGS. 5A to  5 D, detailed description of the method is omitted.  
     [0153] As shown in FIG. 8A, the surface of the organic silicon oxide film  2   b  is coated with the polysilane  6  to bury the contact hole. The resist  7  is used to open the portion in which the second trench will be formed. Then, as shown in FIG. 8B, the resist  7  is used as the etching mask to perform anisotropic RIE so as to form the second trench  8  in the polysilane  6 . Then, the polysilane  6  with which the contact hole  5  is filled is removed until the silicon nitride film  4  is exposed to the outside.  
     [0154] Then, as shown in FIG. 8, ashing is performed by using a mixed gas of O 2  and CO 2  to remove the resist  7 . Simultaneously, change is caused to occur such that the polysilane  6  has a dielectric constant which is the same as the organic silicon oxide film  2   b  so as to be portion of the organic silicon oxide film  2   b.  Thus, an interlayer insulating film having the dual-damascene structure, the overall body of which is made of the organic silicon oxide film, can be formed.  
     [0155] Referring to FIGS. 9A to  9 C, a seventh embodiment of the present invention will now be described. In the seventh embodiment, the overall body of the interlayer insulating film having the dual-damascene structure is formed by using the organic silicon oxide film  2   b  such that the polysilane  6   a  serving as the etching stopper for forming the second trench is buried.  
     [0156] As shown in FIG. 9A, an opening portion is previously formed in the etching stopper constituted by the polysilane  6   a  so as to also used as the etching mask for forming the contact hole. Moreover, the surface of the organic silicon oxide film  2   b  is coated with the polysilane  6  as the anti-reflective film. The resist  7  is used to form the opening portion in the region in which the second trench will be formed.  
     [0157] Then, as shown in FIG. 9B, RIE is performed to remove the anti-reflective film constituted by the polysilane  6 . Then, the RIE conditions for the organic silicon oxide film  2   b  are employed to perform anisotropic etching to reach the silicon nitride film  4 . Thus, only one RIE operation enables the contact hole  5  and the second trench  8  to be formed.  
     [0158] At this time, the anisotropic etching is performed under the RIE conditions that the flow ratio of mixed gas C 4 F 8 /CO/AR/O 2  is 10/50/200/8 sccm, the pressure is 40 mTorr, the high frequency electric power of 1400 W is applied. Thus, the etching selective ratio of the polysilane  6  with respect to the organic silicon oxide film can be made to be 10 or higher. Therefore, the polysilane  6  can be used as the etching mask for the contact hole  5  and the etching stopper when the second trench  8  is formed.  
     [0159] Then, as shown in FIG. 9C, the silicon nitride film  4  covering the upper portion of the wiring metal  3  is removed, and then a mixed gas of O 2  and CO 2  is used to perform ashing so that the resist  7  is removed. Simultaneously, the polysilane  6  and polysilane  6   a  are changed to have the same dielectric constant as that of the organic silicon oxide film  2   b  as the portion of the organic silicon oxide film  2   b.  Thus, the interlayer insulating film having the dual-damascene structure, the overall body of which is made of the integrated organic silicon oxide film, can be formed.  
     [0160] In the seventh embodiment, the organic silicon oxide film  2   b  must be formed to bury the polysilane  6   a.  That is, oxidation of the polysilane  6   a  during the process for forming the organic silicon oxide film  2   b  must be prevented. To prevent oxidation of the polysilane  6   a,  for example, a method may be employed with which an intermediate process is performed such that the surface of the polysilane  6   a  is covered with a thin plasma SiO 2  film and a barrier against introduction of O 2  is formed.  
     [0161] The thin SiO 2  film is removed from the surface of the polysilane  6   a  in the step show in FIG. 9B., Therefore, change of the polysilane  6   a  to a portion of the organic silicon oxide film in the step shown in FIG. 9C is not obstructed.  
     [0162] In the seventh embodiment, the material of the interlayer insulating film is organic silicon oxide film. Note that the material is not limited to the organic silicon oxide film. When the inorganic silicon oxide film or silicon oxide film is employed as the material of the interlayer insulating film, the polysilane  6   a  is similarly employed as the etching stopper and the etching mask.  
     [0163] At this time, polysilane is employed as the anti-reflective film  6 . Note that the material is not limited to polysilane. For example, an organic anti-reflective film may be employed. When the organic anti-reflective film is employed, also the anti-reflective film can be removed when the resist  7  is removed by ashing.  
     [0164] Referring to FIGS. 10A to  10 C, an eighth embodiment of the present invention will now be described. In the eighth embodiment, the polysilane is changed to the silicon nitride film so as to be used as a mask when a contact hole having a high aspect ratio is formed.  
     [0165] As shown in FIG. 10A, the trench metallization in the first layer is formed by using the insulating film  2 . Then, the insulating film  2  is again deposited on the first trench metallization to bury the first trench metallization with the thick insulating film  2  so that the surface is smoothed. Then, the polysilane  6  is applied, and then the pattern of the resist  7  for forming the opening portion of the contact hole having the high aspect ratio is formed. The polysilane  6  is an anti-reflective film in an exposing step in the lithography process for opening the resist  7 .  
     [0166] Then, the resist  7  is used as the etching mask when the contact hole  5  is formed in the insulating film  2  by anisotropic RIE. Thus, the silicon nitride film  4  covering the wiring metal  3  is exposed to the outside. At this time, the silicon nitride film  4  serves as a stopper for use in the anisotropic RIE step.  
     [0167] Then, as shown in FIG. 10B, the resist  7  is removed by N 2  ashing. Simultaneously, the anti-reflective film constituted by the polysilane  6  is changed to the silicon nitride film  4 . The silicon nitride film  4  and the silicon nitride film  4  covering the wiring metal  3 . are removed by hot phosphoric acid etching or by CDE (Chemical Dry Etching). Thus, as shown in FIG. 10C, the contact hole  5  having a high aspect ratio to reach the wiring metal  3  in the first layer can be formed.  
     [0168] The eight embodiment is characterized in that the anti-reflective film constituted by the polysilane  6 , which is left on the surface and which cannot therefore easily be removed by the O 2  ashing for removing the resist  7 , is changed to the silicon nitride film simultaneously with removal of the resist  7  by performing N 2  ashing. Thus, the removal can easily be performed by wet etching or the CDE.  
     [0169] Referring to FIGS. 11A to  11 C, a ninth embodiment of the present invention will now be described. The ninth embodiment is a modification of the eighth embodiment, in which a contact hole having a high aspect ratio is formed to directly reach the silicon substrate  1 .  
     [0170] As shown in FIG. 11A, a thick insulating film  2  is directly formed on the silicon substrate  1 . Then, an anti-reflective film constituted by the polysilane  6  is applied. Then, the pattern of a resist  7  having an opening portion of the contact hole is formed on the anti-reflective film.  
     [0171] The resist  7  is used as the etching mask to perform anisotropic RIE to form the contact hole  5  which reaches the surface of the silicon substrate  1 . Then, as shown in FIG. 11B, N 2  ashing is performed to remove the resist  7 . Simultaneously, the anti-reflective film constituted by the polysilane  6  is changed to the silicon nitride film  4 .  
     [0172] The anti-reflective film changed to the silicon nitride film  4  is removed by a hot phosphoric acid treatment. Thus, the contact hole having a high aspect ratio which reaches the surface of the silicon substrate shown in FIG. 11C can be formed.  
     [0173] Referring to FIGS. 12A and 12B, a tenth embodiment of the present invention will now be described. The tenth embodiment is different from the eighth embodiment in that the anti-reflective film constituted by the polysilane  6  is made to be a portion of the insulating film  2  after the contact hole  5  has been formed.  
     [0174] As shown in FIG. 12A, a thick insulating film  2  is directly formed on the silicon substrate  1 . Then, the anti-reflective film constituted by the polysilane  6  is applied. Then, the pattern of the resist  7  having an opening portion of the contact hole is formed on the anti-reflective film.  
     [0175] The resist  7  is used as the etching mask to perform anisotropic RIE to open the contact hole  5  which reaches the surface of the silicon substrate  1 . Then, as shown in FIG. 12B, O 2  ashing is performed to remove the resist  7 . Simultaneously, the polysilane  6  is changed to the silicon oxide film. Thus, the anti-reflective film can be formed to be a portion of the insulating film  2 .  
     [0176] In the tenth embodiment, the insulating film  2  which is first formed on the silicon substrate  1  is the insulating film obtained by oxidizing the polysilane. Thus, the contact hole which reaches the silicon substrate  1  as shown in FIG. 12B can be formed as the insulating film constituted by an integrated silicon oxide film including the anti-reflective film.  
     [0177] When a silicon nitride film changed from the polysilane is employed as the insulating film  2  which is formed on the silicon substrate  1  and the resist  7  is removed by N 2  ashing, the polysilane  6  employed as the anti-reflective film is changed to the silicon nitride film. Therefore, the contact hole can be formed as the insulating film constituted by the integrated silicon nitride film including the anti-reflective film.  
     [0178] Although the tenth embodiment has been described about formation of the contact hole which reaches the silicon substrate  1 , the contact hole for the trench metallization in the first layer can be formed by a similar process.  
     [0179] Referring to FIGS. 13A to  13 C, an eleventh embodiment of the present invention will now be described. As shown in FIG. 13A, the thick insulating film  2  is formed on the silicon substrate  1 . Then, an anti-reflective film constituted by the polysilane  6  is applied. Then, the pattern of the resist  7  having the opening portion of the contact hole is formed. Then, the resist  7  is used as a mask when the anisotropic RIE is performed to open the polysilane  6 . Then, as shown in FIG. 13B, N 2  ashing is performed to remove the resist  7 . Simultaneously, the polysilane  6  is changed to the silicon nitride film.  
     [0180] Then, as shown in FIG. 13C, the silicon nitride film  4  is used as the mask when the anisotropic RIE is performed to form the contact hole having a high aspect ratio which reaches the silicon substrate  1 .  
     [0181] When a resist mask is directly used to form the contact hole having the high aspect ratio by the anisotropic RIE, the film thinning of the resist mask occurs. On the other hand, the eleventh embodiment in which the silicon nitride film  4  is used as the mask when the anisotropic RIE is performed enables a high etching selective ratio to be realized with respect to the insulating film  2  constituted by SiO 2  or the like. Therefore, the problem of the film thinning can be prevented.  
     [0182] The silicon nitride film  4  on the insulating film  2  shown in FIG. 13C may be removed by the hot phosphoric acid. Alternatively, the insulating film  2  may be integrated with a portion of the insulating film  2  as a silicon nitride film changed from polysilane. The rounded portion formed adjacent to the opening portion of the silicon nitride film  4  enables the wiring metal to smoothly be buried in the contact hole  5 .  
     [0183] Referring to FIGS. 14A to  14 C, a twelfth embodiment of the present invention will now be described. As shown in FIG. 14A, the insulating film  2  constituted by the thick silicon oxide film is formed on the silicon substrate  1 . Then, the anti-reflective film constituted by the polysilane  6  is applied to the surface of the insulating film  2 . The resist  7  is used to form a reversed pattern of the resist  7  such that the opening portion of the contact hole is covered. Then, RIE using N 2  is performed to change the exposed surface of the silicon nitride film  4  is changed to the silicon nitride film  4 , and then the resist  7  is removed.  
     [0184] Then, as shown in FIG. 14B, the silicon nitride film  4  is used as a mask to perform the anisotropic RIE to open the contact hole, which reaches the silicon substrate  1 , in the insulating film  2  constituted by the polysilane  6  and the silicon oxide film.  
     [0185] Then, a treatment similar to the O 2  ashing step is performed to change the polysilane  6  to the silicon oxide film. Thus, the polysilane  6  is integrated as a portion of the insulating film  2 , as shown in FIG. 14C.  
     [0186] Then, hot phosphoric acid is used to remove the silicon nitride film  4  employed as the mask so that a contact hole having a high aspect ratio which reaches the silicon substrate  1  is formed in the insulating film  2  constituted by the silicon oxide film. Also the twelfth embodiment employs the silicon nitride film as the etching mask for forming the contact hole having the high aspect ratio. Therefore, the problem of the film thinning can be prevented.  
     [0187] Referring to FIGS. 15A to  15 C, a thirteenth embodiment of the present invention will now be described. As shown in FIG. 15A, a thick organic silicon oxide film  2   b  is formed on the silicon substrate  1 . Then, the anti-reflective film constituted by the polysilane  6  and the resist  7  having an opened portion for forming the contact hole  5  are provided. Then, the resist  7  is used as the mask when the anisotropic RIE is performed to form the contact hole which reaches the silicon substrate  1 . Then, as shown in FIG. 15B, O 2  ashing is performed to remove the resist  7 .  
     [0188] In the O 2  ashing step, the polysilane  6  is changed to the insulating film  2  constituted by the silicon oxide film. At this time, only the insulating film  2  constituted by the silicon oxide film changed from the polysilane  6  can easily be removed by using dilute hydrofluoric acid as shown in FIG. 15C because the portion between the organic silicon oxide film  2   b  and the insulating film  2  constituted by the silicon oxide film has etching selectivity with respect to dilute hydrofluoric acid.  
     [0189] In the eleventh to thirteenth embodiments, the contact hole which reaches the silicon substrate  1  is formed. As a matter of course, the contact hole for the trench metallization in the first layer can similarly be formed.  
     [0190] In the first to thirteenth embodiment, the method has mainly be described with which the organic silicon film is employed in the interlayer insulating film having the dual-damascene structure and the fabricated portion of the contact hole. The present invention is not limited to this. The organic silicon film such as polysilane, can widely be applied to a manufacturing method of semiconductor devices by using dry etching technology. The foregoing face will now be described as the following embodiments.  
     [0191] Referring to FIGS. 16A to  16 E, a fourteenth embodiment will now be described. The fourteenth embodiment is structured such that the device isolation region and the device region are smoothed by using polysilane.  
     [0192] As shown in FIG. 16A, the silicon substrate  1  is coated with the polysilane  6  to form the pattern of the resist  7  such that the device region for forming a MOS (Metal-Oxide-Semiconductor) transistor is covered. Then, a mixed gas of Cl 2 , the flow rate of which is 75 sccm, and O 2 , the flow rate of which is 10 sccm is used to perform anisotropic RIE by using the resist  7  as a mask as shown in FIG. 16B under conditions that the pressure is 75 mTorr and the high frequency electric power is 300 W. Thus, the polysilane  6  and the silicon substrate  1  are etched.  
     [0193] Then, as shown in FIG. 16C, N 2  ashing is performed to remove the resist  7 . Simultaneously, the polysilane  6  is changed to the silicon nitride film  4 . Then, as shown in FIG. 16D, the overall surface is coated with the polysilane  6  such that the isolation trench for isolating devices formed in the silicon substrate  1  is buried.  
     [0194] Since the polysilane  6  flows, the surface of the polysilane  6  is smoothed owing to coating. Moreover, CMP is performed to remove the excessive polysilane  6  on the silicon nitride film  4  by using the silicon nitride film  4  as the stopper. Thus, the opening portion of the isolation trench is filled with the polysilane  6  so as to be smoothed.  
     [0195] Then, as shown in FIG. 16E, a treatment similar to O 2  ashing is performed so that the polysilane  6  with which the isolation trench is filled is changed to the insulating film  2  constituted by the silicon oxide film. Although the foregoing embodiment has the structure that the polysilane is employed to bury the isolation trench, the present invention is not limited to this. Also an organic silicon oxide film or an inorganic silicon oxide film which can be formed by coating can be used to bury the isolation trench.  
     [0196] As described before, the conventional step of forming the isolation trench has been performed by thick depositing the insulating film constituted by SiO 2  which cannot easily be processed as compared with polysilane. Then, the surface of the insulating film having a great uneven surface along the isolation trench is smoothed by CMP by using the silicon nitride film constituted by Si 3 N 4  as the stopper. Therefore, there arises a problem according to the distribution of density of the device regions covered with the stoppers. That is, polishing proceeds excessively in a field region in which stoppers are distributed at a low density and thus the surface is formed into a concave shape.  
     [0197] On the other hand, the fourteenth embodiment has the structure that polysilane which can easily be polished is applied as a substitute for SiO 2 . Therefore, the surface can be smoothed from the initial stage. Since only polysilane in the form of a thin film left on the silicon nitride film in a small quantity is required to be removed by CMP, the surface smoothness realized after CMP has been completed can considerably be improved as compared with the conventional method.  
     [0198] Referring to FIGS. 17A to  17 D, a fifteenth embodiment of the present invention will now be described. The fifteenth embodiment has the structure that the polysilane according to the present invention is employed in a portion which is formed between gate electrodes of a MOS transistor formed on the silicon substrate  1  and in which dry etching of SAC is performed to form the contact hole which reaches the source/drain diffusion layer  9  in a self-alignment manner.  
     [0199] As shown in FIG. 17A, a gate oxide film  10  is formed on the silicon substrate  1  on which the source/drain diffusion layer  9  of the MOS transistor is formed. Then, polysilicon  11 , tungsten  12  and the silicon nitride film  4  are stacked on the gate oxide film  10 . Then, a pattern is formed so that the gate electrode of the MOS transistor is formed such that the portion around the gate electrode is covered with the silicon nitride film  4 .  
     [0200] Then, the insulating film  2  made of, for example, SiO 2  is deposited on the overall surface of the silicon substrate  1  on which the gate electrode has been formed. Then, CMP is performed to smooth the surface of the insulating film  2 . Then, polysilane  6  is further applied to the smoothed insulating film  2 , and then the pattern of resist  7  having an opening portion in which a self-aligned contact hole will be formed is formed.  
     [0201] Then, as shown in FIG. 17B, polysilane  6  serving as a mask is opened by anisotropic RIE. Then, as shown in FIG. 17C, the self-aligned contact hole  13  is formed by anisotropic RIE to reach the etching stopper constituted by the silicon nitride film  4  which covers the portion around the gate electrode.  
     [0202] At this time, the etching selective ratio of the silicon nitride film  4  covering the portion around the gate electrode with respect to the insulating film  2  is lowered in the edge line portion of the gate electrode exposed to the inside portion of the self-aligned contact hole  13 . Therefore, the corner of the edge line portion of the silicon nitride film  4  is, as shown in FIG. 17C, cut owing to the anisotropic RIE of the self-aligned contact hole  13 .  
     [0203] Since cutting of the corners of the gate electrode is protected by the silicon nitride film  4  in the uppermost layer of the gate electrode, there arises no problem when the depth of etching of the insulating film  2 , which cannot easily be fabricated as compared with the polysilane  6 , is small.  
     [0204] That is, the fifteenth embodiment has the structure that the thickness of the insulating film  2  is reduced to stack the polysilane  6  on the insulating film  2 . Thus, the depth of etching of the insulating film  2  can be minimized until the edge line portion of the gate electrode is exposed.  
     [0205] In the fifteenth embodiment, as shown in FIG. 17D, O 2  ashing is performed to remove the resist  7 . Simultaneously, the polysilane  6  is changed to be the silicon oxide film which forms a portion of the insulating film  2 . Then, the silicon nitride film  4  and the gate oxide film  10  covering the source/drain diffusion layer  9  are removed. Then, wiring metal is buried in the self-aligned contact hole  13 . Thus, a SAC connected to the source/drain diffusion layer  9  is formed.  
     [0206] When the thickness of the insulating film  2  shown in FIG. 17A is enlarged to the total thickness of the insulating film  2  and the polysilane  6  as employed by the conventional technology, further intense anisotropic RIE is required to etch the insulating film  2  as compared with the anisotropic RIE required to etch the polysilane  6 . Therefore, the amount of cutting of the edge line portion of the gate electrode is enlarged. If tungsten  12  of the gate electrode is exposed, the gate electrode and the source/drain diffusion layer  9  are short-circuited in the step of burying the wiring metal in the self-aligned contact hole  13 .  
     [0207] That is, the fifteenth embodiment is characterized in that the insulating film  2  and the polysilane  6  are stacked; and the polysilane  6  is changed to be a portion of the insulating film  2  to substantially reduce the amount of fabrication of the insulating film  2  by the anisotropic RIE so as to prevent short circuit between the gate electrode and the source/drain diffusion layer  9  so that the manufacturing yield of the semiconductor devices is improved.  
     [0208] Referring to FIGS. 18A to  18 E, a sixteenth embodiment of the present invention will now be described. As shown in FIG. 18A, a gate oxide film  10  is formed on the silicon substrate  1  having the source/drain diffusion layer  9 . The pattern of a gate electrode having the laminated polysilicon  11 , tungsten  12  and the silicon nitride film  4  is formed. Then, the portion around the gate electrode is coated with the silicon nitride film  4 . The foregoing steps are the same as those shown in FIG. 17A.  
     [0209] Then, as shown in FIG. 18B, the surface of the silicon nitride film  4  covering the gate electrode is covered with a silicon oxide film  10   a.  Then, the polysilane  6  is thick applied to the overall upper surface of the silicon substrate  1  subjected to the foregoing step. The sixteen embodiment is characterized in that the insulating film in which the gate electrode is buried is substantially constituted by the polysilane  6 .  
     [0210] The pattern of the opening portion in the resist  7  is formed at the position at which the self-aligned contact hole  13  will be formed. The resist  7  is used as a mask to open the self-aligned contact hole  13  in the thick polysilane film  6 . Since the polysilane  6  can easily be removed by anisotropic RIE, the silicon oxide film  10   a  covering the gate electrode serves as a stopper to completely prevent erosion of the edge line portion of the gate electrode and improve the manufacturing yield of the semiconductor devices.  
     [0211] Then, as shown in FIG. 18C, the polysilane  6  is changed to the silicon oxide film simultaneously with removal of the resist  7  by performing O 2  ashing.  
     [0212] Then, as shown in FIG. 18D, the silicon oxide film  10   a  covering the gate electrode is removed by etching. To maximally prevent erosion of the edge line portion of the silicon nitride film  4  covering the gate electrode, the silicon oxide film is etched under the RIE conditions with which the selective ratio with respect to the silicon nitride film can be raised. Since a satisfactorily high etching selective ratio can be realized between the insulating film  2  changed from the polysilane  6  and the silicon oxide film  10   a  covering the gate electrode, only the silicon oxide film  10   a  can be removed by etching.  
     [0213] Then, as shown in FIG. 18E, anisotropic RIE is performed to remove the silicon nitride film  4  covering the source/drain diffusion layer  9  and the gate oxide film  10 . At this time, the silicon nitride film  4  covering the edge line portion of the gate electrode is somewhat eroded. Since the amount of dry etching is very small, there is no apprehension that the short circuit occurs between the gate electrode and the source/drain diffusion layer  9 .  
     [0214] Referring to FIGS. 19A to  19 D, a seventeenth embodiment of the present invention will now be described. The seventeenth embodiment is a modification of the sixteenth embodiment. As shown in FIG. 19A, the gate electrode on the silicon substrate  1  subjected to the step shown in FIG. 18A is covered with a thicker oxide film  10   b.  As shown in FIG. 19B, anisotropic RIE is performed to carry out etching back so that an oxide film  10   b  of the gate sidewall is formed.  
     [0215] Then, as shown in FIG. 19C, a thick polysilane  6  is applied to form the pattern of the resist  7  having an opening corresponding to the self-aligned contact will be established. The resist  7  is used as a mask when the anisotropic RIE is performed to form the self-aligned contact hole  13  in the polysilane  6 . Since the oxide film  10   b  of the gate sidewall serves as an etching stopper in the anisotropic RIE step of the polysilane, erosion of the edge line portion of the gate electrode can be prevented.  
     [0216] Then, O 2  ashing is performed to remove the resist  7 . Simultaneously, the polysilane  6  is changed to the insulating film  2  constituted by the silicon oxide film. The following steps similar to the steps following the step shown in FIG. 18C are performed so that a SAC connected to the source/drain diffusion layer  9  is formed.  
     [0217] A step has been described with which the thick oxide film  10   b  covering the gate is etched back to be the oxide film  10   b  of the gate sidewall shown in FIG. 19B. The etching back is not always required. If the etching conditions are optimized, a similar effect can be obtained when the thick oxide film  10   b  is employed as it is.  
     [0218] Referring to FIGS. 20A to  20 C, an eighteenth embodiment of the present invention will now be described. In the eighteenth embodiment, polysilane is used to form the trench. As shown in FIG. 20A, the insulating film  2  constituted by the silicon oxide film is formed on the silicon substrate  1 . Then, the surface of the insulating film  2  is coated with the polysilane  6 .  
     [0219] The resist  7  is opened at the position on the polysilane  6  at which the metallization trench will be formed. The resist  7  is used as a mask to form the trench  8  by performing anisotropic RIE, as shown in FIG. 20B. Since the etching selective ratio of the polysilane  6  with respect to the insulating film  2  constituted by the silicon oxide film is very high, the insulating film  2  serves as the stopper in the. anisotropic RIE step. As a result, the depth of the second trench  8  can be uniformed.  
     [0220] Then, as shown in FIG. 20C, O 2  ashing is performed to remove the resist  7 . Simultaneously, the polysilane  6  is changed to a portion of the insulating film  2  constituted by the silicon oxide film. As described above, the polysilane  6  can be smoothed by coating. If the anisotropic RIE conditions are controlled, the etching stopper constituted by the insulating film  2  is not always required to form the trench  8  in the polysilane  6 .  
     [0221] In general, a furthermore precise trench metallization in the first layer is required. If an aspect ratio (the ratio of the width of the metallization and the height of the same) higher than a predetermined value is required, a furthermore satisfactory result can be realized when the insulating film  2  is employed as the etching stopper as described in the eighteenth embodiment.  
     [0222] Although the eighteenth embodiment has the structure that the silicon oxide film is employed as the etching stopper, a similar effect can be obtained when an organic silicon oxide film or an inorganic silicon oxide film is employed. When the type of the polysilane  6  is selected to correspond to the base material, a furthermore satisfactory result can be obtained.  
     [0223] Referring to FIGS. 21A to  21 E, a nineteenth embodiment of the present invention will now be described. In the nineteenth embodiment, a method of forming an opening portion in the insulating film mask having a high aspect ratio for use to form a deep silicon trench in the silicon substrate will now be described.  
     [0224] As shown in FIG. 21A, a thermal oxide film  10  serving as an etching stopper is formed on the silicon substrate  1 . Then, the polysilane  6  which is a lower layer is formed on the thermal oxide film  10 . Then, an insulating film  2  constituted by, for example, a silicon oxide film, is deposited on the polysilane  6  which is the lower layer. Then, the polysilane  6   a  which is an upper layer and which serves as an etching stopper is again applied. Thus, a reversed pattern of the resist  7  is formed to cover the position at which the deep trench will be formed. The resist  7  is used as a mask when N 2  RIE or implantation of N 2  ions is performed so that the exposed surface of the polysilane  6   a  which is the upper layer is changed to the silicon nitride film  4   a.    
     [0225] After the resist  7  has been removed, the silicon nitride film  4   a  is used as a mask when anisotropic RIE is performed under conditions that the flow rate ratio of Cl 2 /O 2  is 75/10 sccm, the pressure is 75 mTorr and the applied high frequency electric power is 300 W with which the etching selective ratio of the polysilane is high with respect to the silicon nitride film. Thus, the polysilane  6   a  which is the upper layer and which serves as the anti-reflective film is opened.  
     [0226] Then, anisotropic RIE of the silicon nitride film  4   a  is performed under conditions that the flow rate ratio of C 4 F 8 /CO/Ar is 10/50/200 sccm, the pressure is 40 mTorr and the applied high frequency electric power is 1400 W with which a high etching selective ratio of the insulating film  2  constituted by the silicon oxide film with respect to the silicon nitride film  4   a  can be realized. Thus, a trench  14   a  which reaches the lower polysilane  6  is formed, as shown in FIG. 21B.  
     [0227] Since a required etching selective ratio with respect to the polysilane  6  can be realized, the lower polysilane  6  serves as the etching stopper. Thus, the trench  14   a  can be formed with a satisfactory controllability.  
     [0228] Then, conditions under which a high etching selective ratio of the lower polysilane  6  with respect to the silicon nitride film  4   a  and the thermal oxide film  10  can be realized are employed to form the trench  14   b  such that the thermal oxide film  10  is used as an etching stopper, as shown in FIG. 21C.  
     [0229] Then, conditions under which a high etching selective ratio of the thermal oxide film  10  with respect to the silicon nitride film can be realized are employed to remove the thermal oxide film  10 , as shown in FIG. 21D. At this time, the surface of the silicon substrate  1  serves as a stopper to form the trench  14   c  which reaches the surface of the silicon with a satisfactory controllability.  
     [0230] Finally, as shown in FIG. 21E, heat treatment is performed in a N 2  atmosphere to change the upper and lower polysilane portions  6   a  and  6  into silicon nitride films  4   a  and  4 . Thus, a deep trench mask  14  can be formed in which a trench having a high aspect ratio is formed in the insulating film  2  vertically sandwiched by the silicon nitride films  4   a  and  4  through the silicon thermal oxide film  10 . Note that the final process may be performed before the thermal oxide film  10  is removed. The upper silicon nitride film  4   a  may be removed.  
     [0231] The method of forming the deep trench mask according to the nineteenth embodiment is characterized in that the process is controlled several times by the etching stopper during the anisotropic RIE step. The method enables the trench process of the etching mask to a depth which has been impossible for the conventional technology to be performed with a satisfactory accuracy.  
     [0232] As an alternative to the heat treatment which is performed finally in the N 2  atmosphere, the continuous process is performed in a conditions in which N 2  radicals are increased by changing the anisotropic RIE conditions to conditions that the flow rate of N 2  is 100 sccm, the pressure is 150 mTorr and the applied high frequency electric power is 100 W. Thus, the polysilane portions  6   a  and  6  are changed to the silicon nitride films. In the foregoing case, the number of processing steps can be reduced.  
     [0233] Referring to FIGS. 22A to  22 C, a twentieth embodiment of the present invention will now be described. As shown in FIG. 22A, the thermal oxide film  10  serving as the etching stopper is formed on the silicon substrate  1 . Then, the lower polysilane  6  is applied, and the insulating film  2  constituted by the silicon oxide film is deposited. Then, the upper polysilane  6   a  serving as the anti-reflective film is applied so that the pattern of the resist  7  having an opening corresponding to the portion in which the trench will be formed is formed. Then, the resist  7  is used as the etching mask so that the upper polysilane  6   a  which serves as the anti-reflective film is opened.  
     [0234] Then, as shown in FIG. 22B, N 2  ashing is performed to remove the resist  7 . Simultaneously, the upper polysilane  6   a  is changed to the silicon nitride film  4   a.  The silicon nitride film  4   a  is used as a mask when the anisotropic RIE step is performed to form the trench  14   a  which reaches the lower polysilane  6 .  
     [0235] Then, as shown in FIG. 22C, the conditions under which the anisotropic RIE is performed are changed to form the trench  14   b  in the lower polysilane  6  such that the thermal oxide film  10  is used as the etching stopper. Then, a process similar to the N 2  ashing is performed to change the lower polysilane  6  into the silicon nitride film. Finally, the thermal oxide film  10  is removed so that the deep trench mask which reaches the surface of the silicon substrate  1  is formed. Note that the N 2  ashing step may be performed after the thermal oxide film  10  has been removed.  
     [0236] The step of changing the dry etching conditions according to the twentieth embodiment may be performed by the method according to the nineteenth embodiment. Since each layer serves as the etching stopper, an etching mask exhibiting a satisfactory controllability and having a high aspect ratio can be formed similarly to the nineteenth embodiment.  
     [0237] Referring to FIGS. 23A to  23 C, a twenty-first embodiment will now be described. The twenty-first embodiment is structured such that the pattern of the gate electrode of the MOS transistor is formed on the silicon substrate  1  by using the polysilane  6 .  
     [0238] As shown in FIG. 23A, a gate insulating film constituted by the thermal oxide film  10  is formed on the surface of the silicon substrate  1 . Then, a film composed of the polysilicon  11  and tungsten  12  is, as the material of the gate electrode, formed on the gate insulating film. Then, the overall surface of the film is coated with the polysilane  6 . Then, the pattern of the resist  7  is formed to cover the portion in which the gate electrode will be formed.  
     [0239] Then, as shown in FIG. 23B, the resist  7  is used as the etching mask when the anisotropic RIE step is performed so that the pattern of a laminated film composed of the polysilicon  11 , the tungsten  12  and the polysilane  6  is formed as the gate electrode.  
     [0240] Then, as shown in FIG. 23C, N 2  ashing is performed to remove the resist  7 . Simultaneously, the polysilane  6 , the pattern of which has been formed on the uppermost layer of the gate electrode, is changed to the silicon nitride film  4 . The gate electrode having the silicon nitride film  4  is used as the mask of the gate electrode to form the source/drain diffusion layer  9  in a self-aligned manner by performing implantation of ions and hydrogen. As a result, a MOS transistor on the silicon substrate can be obtained. Note that the polysilicon  11  and the tungsten  12  of the gate electrode is made to be tungsten silicide owing to the heat treatment.  
     [0241] The conventional technology requires two steps of processes with which the resist is used as a mask to form the pattern of the silicon nitride film and the patterns of tungsten and polysilicon are formed by using the silicon nitride film as the mask to form the pattern of a laminated film composed of polysilicon, tungsten and the silicon nitride film as the gate electrode.  
     [0242] In the twenty-first embodiment, the conditions under which the polysilane  6  is etched are such that the flow rate ratio of Cl 2 /O 2  is 75 sccm/10 sccm, the pressure is 75 mTorr and the applied high frequency electric power is 300 W. Under the foregoing conditions, the patterns of the tungsten  12  and the polysilicon  11  can simultaneously be formed. As a result, the number of processing steps can be reduced and the gate electrode can be fabricated with satisfactory controllability. Note that the formation of the tungsten silicide may be performed first to simultaneously form the patterns of the polysilicon layer and the tungsten silicide.  
     [0243] The structure of a dry etching machine to perform the RIE and the ashing step in each embodiment is shown in FIG. 24. The dry etching machine incorporates a vacuum chamber  15 , a subject  16  such as silicon wafer, which must be processed, a retaining frame  17  on which the subject  16  is placed, an opposite electrode  18 , a gas introducing pipe  19 , an exhaust opening  20 , a high-frequency-wave source  21  and a magnet  22 .  
     [0244] The retaining frame  17  has a regulating mechanism to be capable of controlling the temperature of the subject  16  which must be processed. The gas introducing pipe  19  is connected to the upper inner wall of the vacuum chamber  15  serving as the opposite electrode  18 . Gas is introduced into the vacuum chamber  15  through the gas introducing pipe  19 . The valve at the exhaust opening  20  is operated to adjust the pressure.  
     [0245] After the pressure has been stabilized, high frequency waves are applied from the high-frequency-wave source  21  under the retaining frame  17  so that plasma is generated in the vacuum chamber  15 . The magnet  22  is joined to the vacuum chamber  15  to form a dense magnetic field in the vacuum. Simultaneously, anisotropic characteristic is imparted to ions in the plasma to etch the subject  16  which must be processed.  
     [0246] The dry etching machine shown in FIG. 29 is a magnetron RIE machine. Alternatively, another dry etching machine may be employed which is exemplified by a machine using ECR (Electron Cycroton Resonance), helicon or inductance coupled type plasma.  
     [0247] Finally, a method of forming an organic silicon film by performing a coating step using polysilane and the like will now be described. Initially, an organic silicon compound (generally called “organic silicon” in the claims) having the main chains, which are bondings of silicon and silicon, is dissolved in organic solvent so that material of the solution is prepared.  
     [0248] The organic silicon compound having the main chains which are bondings of silicon and silicon is exemplified by polysilane expressed by a general formula (SiR 11 R 12 ), where R11 and R12 is each a hydrogen atom or substituted or non-substituted aliphatic hydrocarbon or aromatic hydrocarbon or the like having 1 to 20 carbon atoms.  
     [0249] Polysilane may be in the form of a single polymer resist a copolymer. Alternatively, polysilane may have a structure that two or more types of polysilane materials are bonded to one another through an oxygen atom, a nitrogen atoms, a fatty acid group or an aromatic group. The organic silicon compound is exemplified by the following chemical formulas [1-1] to [1-114]:  
                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 
 
     [0250] where m and n are positive integers.  
     [0251] Although the weight average molecular weight of each compound is not limited, it is preferable that a range from 200 to 100,000 is satisfied. The reason for this will now be described. If the molecular weight is smaller than 200, the organic silicon film is dissolved by the solvent for the resist. If the molecular weight is larger than 100,000, dissolution in organic selective cannot satisfactorily be performed. Thus, formation of the material of the solution cannot easily be performed.  
     [0252] The organic silicon compound is not limited to one type. A plurality of types of compounds may be mixed. To improve preservation stability if necessary, addition of the following materials is permitted: thermal polarization inhibitor, an adhesion enhancing agent for improving adhesion to the silicon insulating film, ultraviolet absorbing dye which is effective to prevent reflected light from the silicon insulating film into the resist film, a polymer such as polysulfon or polybenzimidazole, for absorbing ultraviolet rays, a substance showing conductivity owing to a conductive substance, light or heat or a crosslinking material for crosslinking the organic silicon compound.  
     [0253] The conductive substance is exemplified by organic sulfonic acid, organic carboxylic acid, polyalcohol, polythiol (for example, iodine or bromine), SbF 5 , PF 5 , BF 5  and SnF 5 .  
     [0254] The substance showing the conductive owing to the energy of light or heat is exemplified by carbon cluster (C 60  or C 70 ), cyanoanthracene, dicyanoanthracene, triphenylpyryum, tetrafluoroborate, tetracyanoquinodimethane, tetracyanoethylene, futhalimidotriphrate, perchloropentacyclododecanel dicyanobenzen, benzotrynyl, trichloromethyltriazine, benzoilperoxide, benzophenon tetra carboxylic acid and t-butylperoxide. The substance is exemplified by the following compounds:  
                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 

                 
 
     [0255] The crosslinking material is exemplified by an organic silicon compound having a multiple bond and an acrylic unsaturated compound. The solvent may be a polar organic solvent or a non-polar organic solvent. Specifically, the solvent is exemplified by ethyl lactate (EL), ethyl-3-ethoxy propionate (EEP), propylene glycol monomethylether acetate (PGMEA), propylene glycol monomethylether (PGME), ketone such as cyclohexane, 2-heptane, 3-heptane, acetylacetone or cyclopentanone, ester such as propylene glycol monoethyl ether acetate, ethylcellosolve acetate, methylcellosolve acetate, methyl-3-methoxypropionate, ethyl-3-methoxypropionate, methyl-3-ethoxypropionate, methyl pyruvate or ethyl pyruvate, ether such as diethylene glycol dimethylether or propyleneglycol dimethylether, glycol ester derivative such as methyl lactate or ethyl glycolate. Note that the solvent is not limited to the foregoing materials.  
     [0256] The coating material is prepared by the foregoing method. Then, the surface of the silicon insulating film is coated with the material of the solution by a spin coating method or the like. Then, the temperature is raised to vaporize the solvent so that the organic silicon film is formed. A glass transition temperature with which a satisfactory etching selective ratio with respect to the resist can be realized is required in the foregoing state. If the satisfactory etching selective ratio with respect to the resist cannot be realized, the coated film is furthermore heated or irradiated with energy beams so crosslink the coated film.  
     [0257] The energy beam is exemplified by ultraviolet rays, X-rays, electron beams and ion beams. When, heating and irradiation with the energy beam are simultaneously performed, the crosslinking reaction is quickened. Thus, the glass transition temperature can significantly be raised in a practical range of process duration.  
     [0258] Note that heating or irradiation with the energy beam sometimes causes bondings between silicon and silicon which are the main chains in the organic silicon compound to be broken. Thus, bonding with oxygen causes oxidation to easily occur, thus resulting in reduction in the etching selective ratio between the resist and the organic silicon film. In the foregoing case, it is preferable that heating and irradiation with the energy beam are performed in an atmosphere in which the concentration of oxygen is lower than that in the air.  
     [0259] The present invention is not limited to the description about the embodiments. In the foregoing description, the structure has been formed such that the insulating film mainly constituted by the silicon oxide film and polysilane are stacked to change the polysilane to the silicon oxide film or the silicon nitride film. If similar methods are combined with each other, the insulating film constituted by the silicon nitride film and polysilane are stacked to change polysilane to the silicon oxide film or the silicon nitride film so as to be a portion of the insulating film constituted by the silicon nitride film. Alternatively, polysilane may be changed to the silicon oxide film so as to be removed from the insulating film constituted by the silicon nitride film.  
     [0260] In the first to sixth embodiments, the dry etching processing method is employed with which the interlayer film having the dual-damascene structure is formed by using polysilane. The present invention is not limited to the interlayer film having the dual-damascene structure. As a matter of course, the foregoing method may be applied to a usual multiple trench metallization. Moreover, a variety of modification may be permitted within the scope of the present invention.  
     [0261] In the device manufacturing process, the organic silicon film of the polysilicon group and the insulating film are stacked each other and oxygen, nitrogen or hydrogen are introduced into the organic silicon film to be changed as a portion of the insulating film as stated above.  
     [0262] In this case, a thin interlayer film containing the constituent organic silicon sometimes remains little at the interface between the organic silicon film and the insulating film.  
     [0263] Relating to the present invention, however, there occurs no problem concerning to the manufactured device operation caused by the existence of such a thin and little remaining interface film.  
     [0264] As described above, the manufacturing method of semiconductor devices by using dry etching technology according to the present invention has the structure that the organic silicon film constituted by polysilane and the like is used to form the insulating film of the semiconductor device or a portion of the same by dry etching. The portion constituted by the organic silicon film is changed to an oxide or a nitride so that the portion constituted by the organic silicon film is integrated with the insulating film of the semiconductor device or a portion of the same. If a similar method is employed, removal of the anti-reflective film which has been difficult for the conventional technology can easily be performed.  
     [0265] The surface region of the organic silicon film is selectively changed to an oxide or a nitride, and then dry etching is performed by using the oxide or the nitride. Then, the process is performed such that the organic silicon film is made to be a portion of the insulating film. A contact hole or the like having a higher aspect ratio as compared with that of the conventional resist mask can be formed.  
     [0266] When the dry etching method structured by combining the foregoing organic silicon films is applied, formation of the contact hole in the interlayer insulating film having the dual-damascene structure, the metallization trench and the dual-damascene structure metallization, which has been difficult, can be facilitated. Moreover, the etching mask incorporating the insulating film, having a high aspect ratio and required to form a deep trench in the silicon substrate can be formed.  
     [0267] Moreover, the present invention may widely be applied to the smoothing process of device region and the device isolation region, formation of a SAC and patterning of a precise gate electrode which are important factors to manufacture dense semiconductor integrated circuit at a satisfactorily high yield.  
     [0268] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.