Patent Publication Number: US-8537094-B2

Title: Shift register with low power consumption and liquid crystal display having the same

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to a shift register, and more particularly to a shift register having a plurality of stages connected in serial. Each stage utilizes a thin film transistor that is driven with a DC voltage signal to reduce the dynamical power consumption and improve the reliability of operation of the shift register. 
     BACKGROUND OF THE INVENTION 
     A liquid crystal display (LCD) includes an LCD panel formed with liquid crystal cells and pixel elements with each associating with a corresponding liquid crystal cell. These pixel elements are substantially arranged in the form of a matrix having gate lines in rows and data lines in columns. The LCD panel is driven by a driving circuit including a gate driver and a data driver. The gate driver generates a plurality of gate signals (scanning signals) sequentially applied to the gate lines for sequentially turning on the pixel elements row-by-row. The data driver generates a plurality of source signals (data signals), i.e., sequentially sampling image signals, simultaneously applied to the data lines in conjunction with the gate signals applied to the gate lines for aligning states of the liquid crystal cells on the LCD panel to control light transmittance therethrough, thereby displaying an image on the LCD. 
     In such a driving circuit, a shift register is utilized in the gate driver to generate the plurality of gate signals for sequentially driving the gate lines. To lower down costs, there have been efforts to integrate the shift register and the gate driver into an LCD panel. One of the efforts, for example, is to fabricate the shift register and the gate driver on a glass substrate of the LCD panel, namely, the gate on array (GOA) arrangement, using amorphous silicon (a-Si) thin film transistors (TFTs). 
     In order to effectively drive the gate lines of the LCD panel, the a-Si TFTs are usually designed with large (channel width) sizes since the mobility of carriers in the a-Si material is very low. However, the larger the a-Si TFTs are, the higher the parasitic capacitance in the a-Si TFTs is, which causes the power consumption in the data lines of the LCD panel to increase substantially. 
     Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies. 
     SUMMARY OF THE INVENTION 
     The present invention, in one aspect, relates to a shift register. In one embodiment, the shift register includes a plurality of stages, {S n }, n=1, 2, . . . , N, N being a positive integer. Each stage S n  comprises a first output for outputting a gate signal, G(n), a second output for outputting a stage carry signal, ST(n), a pull-up circuit electrically coupled between a node, Q(n), and the second output, a pull-up control circuit electrically coupled to the node Q(n), a pull-down circuit electrically coupled between the node Q(n) and the first output, a pull-down control circuit electrically coupled between the node Q(n) and the pull-down circuit, and a control circuit electrically coupled between the node Q(n) and the first output. The control circuit includes a transistor having a gate electrically coupled to the node Q(n), a source configured to receive a DC voltage signal, VGH, and a drain electrically coupled to the first output. The pull-up control circuit of the stage S n  is further electrically coupled to the node Q(n−1) and the second output of the stage S n−1 , and wherein the pull-down circuit of the stage S n  is further electrically coupled to the second output of the stage S n+1 . 
     In one embodiment, the pull-up circuit comprises a transistor T 21  having a gate electrically coupled to the node Q(n), a source configured to receive one of a plurality of control signals, {HCj}, j=1, 2, . . . , M, M being a positive integer, and a drain electrically coupled to the second output. The pull-up circuit may further comprise a capacitor electrically coupled between the gate and drain of the transistor T 21 . 
     In one embodiment, the pull-up control circuit comprises a first transistor T 11  having a gate, a source electrically coupled to the second output of the stage S n−1  for receiving the stage carry signal ST(n−1) therefrom and a drain electrically coupled to the input node Q(n), and a second transistor T 12  having gate electrically coupled to the node Q(n−1) of the stage S n−1 , a source configured to receive one of a plurality of control signals {HCj}, and a drain electrically coupled to the gate of the first transistor T 11 . 
     In one embodiment, the pull-down control circuit comprises a first pull-down control circuit and a second pull-down control circuit. Each of the first and second pull-down control circuits has a first transistor T 51 /T 61  having a gate configured to receive a first clock signal, LC 1  or a second clock signal, LC 2 , a source electrically coupled to the gate and a drain, a second transistor T 52 /T 62  having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the first transistor T 51 /T 61  and a drain configured to receive a supply voltage VSS, a third transistor T 53 /T 63  having a gate electrically coupled to the drain of the first transistor T 51 /T 61 , a source electrically coupled to the source of the first transistor T 51 /T 6  and a drain electrically coupled to a node P(n)/K(n), and a four transistor T 54 /T 64  having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the third transistor T 53 /T 63  and a drain configured to receive a supply voltage VSS. 
     In one embodiment, the pull-down circuit comprises having a first pull-down circuit and a second pull-down circuit. The first pull-down circuit includes a first transistor T 31  having a gate electrically coupled to the node P(n) of the first pull-down control circuit, a source electrically coupled to the node Q(n) and a drain electrically coupled to the first output; and a second transistor T 32  having a gate electrically coupled to the node P(n) of the first pull-down control circuit, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS. The second pull-down circuit includes a first transistor T 41  having a gate electrically coupled to the node K(n) of the second pull-down control circuit, a source electrically coupled to the node Q(n) and a drain electrically coupled to the first output, a second transistor T 42  having a gate electrically coupled to the node K(n) of the second pull-down control circuit, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS, a third transistor T 43  having a gate electrically coupled to the second output of the stage S n+1 , a source electrically coupled to the node Q(n) and a drain configured to receive the supply voltage VSS, and a fourth transistor T 44  having a gate electrically coupled to the second output of the stage S n+1 , a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS. 
     In another aspect, the present invention relates to a liquid crystal display (LCD) comprising a liquid crystal panel having a plurality of pixels spatially arranged in the form of a matrix, a plurality of scanning lines spatially arranged along a row direction, wherein each two neighboring scanning lines define a pixel row therebetween, and a gate driver adapted for generating a plurality of gate signals for driving the plurality of pixels. The gate driver comprises a shift register having a plurality of stages, {S n }, connected in serial, n=1, 2, . . . , N, N being a positive integer. 
     Each stage S n  comprises a first output electrically coupled a corresponding gate line for outputting a gate signal, G(n), thereto, a second output for outputting a stage carry signal, ST(n), a pull-up circuit electrically coupled between a node, Q(n), and the second output, a pull-up control circuit electrically coupled to the node Q(n), a pull-down circuit electrically coupled between the node Q(n) and the first output, a pull-down control circuit electrically coupled between the node Q(n) and the pull-down circuit, and a control circuit electrically coupled between the node Q(n) and the first output. The control circuit includes a transistor having a gate electrically coupled to the node Q(n), a source configured to receive a DC voltage signal, VGH, and a drain electrically coupled to the first output. The pull-up control circuit of the stage S n  is further electrically coupled to the node Q(n−1) and the second output of the stage S n−1 , and wherein the pull-down circuit of the stage S n  is further electrically coupled to the second output of the stage S n+1 . 
     In one embodiment, the pull-up circuit comprises a transistor T 21  having a gate electrically coupled to the node Q(n), a source configured to receive one of a plurality of control signals, {HCj}, j=1, 2, . . . , M, M being a positive integer, and a drain electrically coupled to the second output. The pull-up circuit may further comprise a capacitor electrically coupled between the gate and drain of the transistor T 21 . 
     In one embodiment, the pull-up control circuit comprises a first transistor T 11  having a gate, a source electrically coupled to the second output of the stage S n−1  for receiving the stage carry signal ST(n−1) therefrom and a drain electrically coupled to the input node Q(n), and a second transistor T 12  having gate electrically coupled to the node Q(n−1) of the stage S n−1 , a source configured to receive one of a plurality of control signals {HCj}, and a drain electrically coupled to the gate of the first transistor T 11 . 
     In one embodiment, the pull-down control circuit comprises a first pull-down control circuit and a second pull-down control circuit. Each of the first and second pull-down control circuits has a first transistor T 51 /T 61  having a gate configured to receive a first clock signal, LC 1  or a second clock signal, LC 2 , a source electrically coupled to the gate and a drain, a second transistor T 52 /T 62  having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the first transistor T 51 /T 61  and a drain configured to receive a supply voltage VSS, a third transistor T 53 /T 63  having a gate electrically coupled to the drain of the first transistor T 51 /T 61 , a source electrically coupled to the source of the first transistor T 51 /T 6  and a drain electrically coupled to a node P(n)/K(n), and a four transistor T 54 /T 64  having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the third transistor T 53 /T 63  and a drain configured to receive a supply voltage VSS. 
     In one embodiment, the pull-down circuit comprises having a first pull-down circuit and a second pull-down circuit. 
     The first pull-down circuit includes a first transistor T 31  having a gate electrically coupled to the node P(n) of the first pull-down control circuit, a source electrically coupled to the node Q(n) and a drain electrically coupled to the first output; and a second transistor T 32  having a gate electrically coupled to the node P(n) of the first pull-down control circuit, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS. 
     The second pull-down circuit includes a first transistor T 41  having a gate electrically coupled to the node K(n) of the second pull-down control circuit, a source electrically coupled to the node Q(n) and a drain electrically coupled to the first output, a second transistor T 42  having a gate electrically coupled to the node K(n) of the second pull-down control circuit, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS, a third transistor T 43  having a gate electrically coupled to the second output of the stage S n+1 , a source electrically coupled to the node Q(n) and a drain configured to receive the supply voltage VSS, and a fourth transistor T 44  having a gate electrically coupled to the second output of the stage S n+1 , a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS. 
     In one embodiment, the liquid crystal panel, the plurality of scanning lines and the gate driver are formed on a glass substrate such that the plurality of stage {S n } is located on at least one side of the liquid crystal panel. 
     These and other aspects of the present invention will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings illustrate one or more embodiments of the invention and, together with the written description, serve to explain the principles of the invention. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment, and wherein: 
         FIG. 1  shows a block diagram of a shift register according to one embodiments of the present invention; 
         FIG. 2  shows a circuit diagram of the stage S n  of the shift register shown in  FIG. 1 ; 
         FIG. 3  shows waveforms of signals of the shift register shown in  FIG. 1 ; 
         FIG. 4  shows simulated output signals of the shift register shown in  FIG. 1 ; and 
         FIG. 5  shows an RA result of output signals of the shift register shown in  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Various embodiments of the disclosure are now described in detail. Referring to the drawings, like numbers indicate like components throughout the views. As used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. 
     The terms used in this specification generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Certain terms that are used to describe the disclosure are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the disclosure. The use of examples anywhere in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the disclosure is not limited to various embodiments given in this specification. 
     As used herein, “around”, “about” or “approximately” shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about” or “approximately” can be inferred if not expressly stated. 
     As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. 
     The description will be made as to the embodiments of the present invention in conjunction with the accompanying drawings in  FIGS. 1-5 . In accordance with the purposes of this invention, as embodied and broadly described herein, this invention, in one aspect, relates to a shift register and an LCD using same. 
       FIG. 1  shows schematically a block diagram (or a GOA architectural layout) of a shift register  100  according to one embodiment of the present invention. The shift register  100  includes multiple stages {S n } connected in serial, n=1, 2, . . . , N, N being a positive integer. The multiple stages {S n } are deposited/formed on a glass substrate (not shown). In the exemplary embodiment shown in  FIG. 1 , only four stages S n , S n+1 , S n+2 , and S n+3  are shown in the shift register  100 . 
     Each stage S n , has a first output  111  for outputting a gate signal, G(n), and a second output  112  for outputting a stage carry signal, ST(n). The first output of each stage S n , is electrically coupled to a corresponding gate line of an LCD panel (not shown) for outputting the gate driving signal thereto. Each stage S n  also has a plurality of inputs for receiving corresponding one or more control/clock signals, such as LC 1 , LC 2 , HC 1 , HC 2 , HC 3 , HC 4  and a supply voltage VSS. 
     Further, each stage S n , has a pull-up control circuit  130 , a pull-up circuit  120 , a pull-down control circuit  150 , a pull-down circuit  140  and a control circuit including a transistor T 22  formed on the glass substrate adjacent to each other. For each stage S n , the pull-up circuit  120  is electrically coupled between a node, Q(n), and the second output  112 . The pull-up control circuit  130  is electrically coupled to the pull-up circuit  120  through the node Q(n). The pull-down circuit  140  is electrically coupled between the node Q(n) and the first output  111 . The pull-down control circuit  150  is electrically coupled between the node Q(n) and the pull-down circuit  140 . The pull-up circuit  120  is also configured to receive a corresponding control/clock signal HC 1 , HC 2 , HC 3  or HC 4 . For example, the pull-up circuits  120  of the stage S n , S n+1 , S n+2 , and S n+3  receives the control/clock signals HC 1 , HC 2 , HC 3  and HC 4 , respectively, as shown in  FIG. 1 . The pull-down control circuit  150  is also configured to receive both the control/clock signals LC 1  and LC 2 . The transistor T 22  has a gate electrically coupled to the node Q(n), a source configured to receive a DC voltage signal, VGH, and a drain electrically coupled to the first output  111 . Additionally, the pull-up control circuit  130  of the stage S n  is also electrically coupled to the node Q(n−1) and the second output  112  of the immediately prior stage S n−1 . The pull-down circuit  140  of the stage S n  is also electrically coupled to the second output  112  of the immediately next stage S n+1 . 
     Referring to  FIG. 2 , a circuit diagram of the stage S n , of the shift register  100  is shown according to one embodiment of the present invention. The pull-up circuit  120  includes a transistor T 21  having a gate electrically coupled to the node Q(n), a source configured to receive the control signals HC 1 , and a drain electrically coupled to the second output  112 . The pull-up circuit  120  further includes a capacitor C electrically coupled between the gate and drain of the transistor T 21 . 
     The pull-up control circuit  130  includes a first transistor T 11  and a second transistor T 12 . The first transistor T 11  has a gate, a source electrically coupled to the second output  112  of the stage S n−1  for receiving the stage carry signal ST(n−1) therefrom and a drain electrically coupled to the node Q(n). The second transistor T 12  has a gate electrically coupled to the node Q(n−1) of the stage S n−1 , a source configured to receive the control signal HC 4 , and a drain electrically coupled to the gate of the first transistor T 11 . 
     The pull-down control circuit  140  comprises a first pull-down control circuit  141  and a second pull-down control circuit  142 . 
     The first pull-down control circuits  141  has a first transistor T 51  having a gate configured to receive the first clock signal LC 1 , a source electrically coupled to the gate and a drain, a second transistor T 52  having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the first transistor T 51  and a drain configured to receive the supply voltage VSS, a third transistor T 53  having a gate electrically coupled to the drain of the first transistor T 51 , a source electrically coupled to the source of the first transistor T 51  and a drain electrically coupled to a node P(n), and a four transistor T 54  having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the third transistor T 53  and a drain configured to receive a supply voltage VSS. 
     The second pull-down control circuits  142  has a first transistor T 61  having a gate configured to receive the second clock signal LC 2 , a source electrically coupled to the gate and a drain, a second transistor T 62  having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the first transistor T 61  and a drain configured to receive the supply voltage VSS, a third transistor T 63  having a gate electrically coupled to the drain of the first transistor T 61 , a source electrically coupled to the source of the first transistor T 6  and a drain electrically coupled to a node K(n), and a four transistor T 64  having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the third transistor T 63  and a drain configured to receive the supply voltage VSS. 
     The pull-down circuit  150  includes a first pull-down circuit  151  and a second pull-down circuit  152 . 
     The first pull-down circuit  151  includes a first transistor T 31  having a gate electrically coupled to the node P(n) of the first pull-down control circuit, a source electrically coupled to the node Q(n) and a drain electrically coupled to the first output; and a second transistor T 32  having a gate electrically coupled to the node P(n) of the first pull-down control circuit, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS. 
     The second pull-down circuit  152  includes a first transistor T 41  having a gate electrically coupled to the node K(n) of the second pull-down control circuit, a source electrically coupled to the node Q(n) and a drain electrically coupled to the first output, a second transistor T 42  having a gate electrically coupled to the node K(n) of the second pull-down control circuit, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS, a third transistor T 43  having a gate electrically coupled to the second output of the stage S n+1 , a source electrically coupled to the node Q(n) and a drain configured to receive the supply voltage VSS, and a fourth transistor T 44  having a gate electrically coupled to the second output of the stage S n+1 , a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS. 
     The transistor T 22  has a gate electrically coupled to the node Q(n), a source electrically coupled to a DC power source for receiving a high voltage DC signal, VGH, and a drain electrically coupled to the first output  111  for outputting a gate signal to a corresponding gate line to drive pixels associated with the gate line. 
     The above-disclosed transistors including the transistor T 22  are thin film transistors (TFTs), preferably, a-Si TFTs. 
     For such a configuration of the shift register shown in  FIGS. 1 and 2 , the transistor T 21  of the pull-up circuit  120  is adapted only for pulling up a load potential of the immediately next stage. Thus, the channel width of the transistor T 21  can be designed to be very narrow, so that its dynamical power consumption can be negligibly small. Further, the input signal to the transistor T 22  is a DC voltage signal, which causes no dynamical power consumption thereof. Accordingly, the overall power consumption of the shift register is reduced substantially. 
       FIG. 3  shows waveforms of signals of the second stage S 2  (n=2) of the shift register shown in  FIGS. 1 and 2 , in operation. 
     During the time period of P 1 , the voltage (electric potential) of the node Q( 1 ) of the first stage S 1  is in a high voltage level, and the transistor T 12  is turned on responsively. Accordingly, the gate of the transistor T 11  is charged by the first clock signal HC 1  and turned on thereby. As a result, the node Q( 2 ) is charged by the stage carry signal ST( 1 ) of the immediately prior stage, S 1 . When the voltage of the node Q( 2 ) is charged (pulled up) to a high level, so that the transistors T 21  and T 22  are also turned on. However, during the time period of P 1 , there is no output of the stage carry signal ST( 2 ), since the second clock signal HC 2  coupled to the drain of the transistor T 21  is in the low voltage level, VGL. For the transistor T 22 , there is a current flow from its drain electrically connected to the high voltage level of the DC voltage signal VGH to its source electrically coupled the first output so as to charge the scanning line G( 2 ). 
     During the time period of P 2 , when the first clock signal HC 1  is in the low voltage level, the transistor T 11  is turned off and the node Q( 2 ) is a floating state. Meanwhile, the transistors T 21  and T 22  are still turned on. When the second clock signal HC 2  is in the high voltage level VGH, the stage carry signal ST( 2 ) is output via the transistor T 21 . The stage carry signal ST( 2 ) coupled with the capacitor C, in turn, charges the node Q( 2 ) to a further higher voltage level. Accordingly, there are a two step rise in the waveform of the node Q( 2 ). When the voltage of the node Q( 2 ) is in the further higher voltage level, the current flow/output from the transistor T 22  is larger than that during the time period of P 1 . Thus, the output voltage at the first output G( 2 ) is higher. 
     During the time period of P 3 , when the third clock signal HC 3  is in the high voltage level VGH, there is an output of the stage carry signal ST( 3 ) of the next stage S 3 , which, through the transistor T 43 , pulls down the voltage level of the node Q( 2 ) to the reference voltage VSS. Meanwhile, the stage carry signal ST( 3 ), through the transistor T 44 , pulls down the voltage level of the scanning line G( 2 ) to the reference voltage VSS. In the case, the nodes P( 2 )/K( 2 ) play the role of regulating the voltage level of the nodes Q( 2 )/G( 2 ). Generally, the voltage level of the nodes Q( 2 )/G( 2 ), through the transistors T 31 /T 32 /T 41 /T 42 , are regulated to the reference voltage VSS. However, when there is a contribution of the node Q( 2 ) in the output of this stage, the nodes P( 2 )/K( 2 ) are pulled down to the reference voltage VSS, so that the regulating circuit is turned off. 
     The operational principle disclosed above also applies to other stages of the shift register. 
       FIG. 4  shows the simulated waveforms of the output signals G(n), G(n+1) and G(n+2) generated from the stages S n , S n+1  and S N+2 , respectively, of the shift register shown in  FIGS. 1 and 2 . 
       FIG. 5  is an RA testing result for the output signal of the stage S n  of the shift register at the temperature about 100° C. for about 72 hours, where G(n) and G′(n) are corresponding to an initial stage output signal and the stage output signal after the RA testing, respectively. It is shown that according to the present invention, the stage output signal G′(n) after the RA testing is almost identical to the initial stage output signal G(n), indicating that the operation of the shift register is very reliable, and yet consumes much less. 
     The present invention in another aspect also relates to an LCD using the shift register as disclosed above. In one embodiment, the LCD has a liquid crystal panel having a plurality of pixels spatially arranged in the form of a matrix, a plurality of scanning lines spatially arranged along a row direction, wherein each two neighboring scanning lines define a pixel row therebetween, and a gate driver adapted for generating a plurality of gate signals for driving the plurality of pixels. The gate driver comprises the shift register having the plurality of stages, {S n }, connected in serial. The output of each stage S n , is electrically coupled a corresponding gate line for outputting a gate signal, G(n), thereto. 
     In one embodiment, the liquid crystal panel, the plurality of scanning lines and the gate driver are formed on a glass substrate such that the plurality of stage {S n } is located on one lateral side of the liquid crystal panel, or both lateral sides of the liquid crystal panel. Accordingly, it simplifies the GOA design and reduces the manufacturing cost of an LCD panel. Furthermore, it can reduce the power consumption and improves the reliability of operation of the LCD panel. 
     In sum, the present invention, among other things, discloses a shift register and an LCD using same. The shift register has plurality of stages connected in serial. Each stage utilizes a thin film transistor that is driven with a DC voltage signal to reduce the dynamical power consumption, and yet improve the reliability of operation. 
     The foregoing description of the exemplary embodiments of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. 
     The embodiments were chosen and described in order to explain the principles of the invention and their practical application so as to enable others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present invention pertains without departing from its spirit and scope. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.