Patent Publication Number: US-2023165012-A1

Title: Ferroelectric memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0164865, filed on Nov. 25, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     BACKGROUND 
     The inventive concept relates to a ferroelectric memory device, and more particularly, to a ferroelectric memory device having a spontaneous polarization characteristic. 
     Recently, along with the high processing speed and low power consumption of electronic products, a fast read/write operation and a low operating voltage have been desired for semiconductor devices embedded in electronic products. According to these requirements, research into a ferroelectric memory device having ferroelectricity to maintain spontaneous polarization by aligning internal electric dipole moments without applying an electric field from the outside has been conducted. In particular, a highly integrated ferroelectric memory device may perform a high-speed read operation and a high-speed write operation and has a nonvolatile property, and thus, the highly integrated ferroelectric memory device has emerged as a next-generation memory device. 
     SUMMARY 
     The inventive concept provides a ferroelectric memory device having improved reliability by disposing a high dielectric layer between an interface layer and a ferroelectric layer to mitigate electric field concentration in the interface layer. 
     The inventive concept is not limited to the problems mentioned above, and other problems which are not mentioned could be clearly understood by those of ordinary skill in the art from the description below. 
     According to some embodiments of the inventive concept, there is provided a ferroelectric memory device including a substrate having source/drain regions, an interface layer on the substrate, a high dielectric layer on the interface layer, a ferroelectric layer on the high dielectric layer, and a gate electrode layer on the ferroelectric layer. The high dielectric layer and the ferroelectric layer have phases of different crystal structures. 
     According to some embodiments of the inventive concept, there is provided a ferroelectric memory device including a substrate having source/drain regions, a first interface layer on the substrate, a high dielectric layer on the first interface layer, a second interface layer on the high dielectric layer, a ferroelectric layer on the second interface layer, and a gate electrode layer on the ferroelectric layer. The high dielectric layer and the ferroelectric layer have phases of different crystal structures. 
     According to some embodiments of the inventive concept, there is provided a ferroelectric memory device including a gate stack on a substrate and including a plurality of gate electrode layers and a plurality of mold insulating layers alternately stacked in a vertical direction, a trench passing through the gate stack, a gate dielectric layer on side walls of the plurality of gate electrode layers inside the trench and including a ferroelectric part and a non-ferroelectric part, and a channel layer covering the gate dielectric layer. The gate dielectric layer includes an interface layer, a high dielectric layer on the interface layer, and a ferroelectric layer on the high dielectric layer, wherein the high dielectric layer and the ferroelectric layer have phases of different crystal structures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG.  1    is a cross-sectional view illustrating main components of a ferroelectric memory device according to some embodiments of the inventive concept; 
         FIG.  2    is a graph illustrating a relationship between a permittivity and an applied voltage; 
         FIG.  3    is a cross-sectional view illustrating main components of a ferroelectric memory device according to some embodiments of the inventive concept; 
         FIG.  4    is a cross-sectional view illustrating main components of a ferroelectric memory device according to some embodiments of the inventive concept; 
         FIG.  5    is a flowchart illustrating a method of manufacturing a ferroelectric memory device, according to some embodiments of the inventive concept; 
         FIGS.  6  to  9    are cross-sectional views for describing, in a process order, a method of manufacturing a ferroelectric memory device, according to some embodiments of the inventive concept; 
         FIG.  10    is a flowchart illustrating a method of manufacturing a ferroelectric memory device, according to some embodiments of the inventive concept; 
         FIGS.  11  to  14    are cross-sectional views for describing, in a process order, a method of manufacturing a ferroelectric memory device, according to some embodiments of the inventive concept; and 
         FIG.  15    is a block diagram illustrating a system including a ferroelectric memory device, according to some embodiments of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings. 
       FIG.  1    is a cross-sectional view illustrating main components of a ferroelectric memory device  10  according to some embodiments of the inventive concept, and  FIG.  2    is a graph illustrating a relationship between a permittivity and an applied voltage ratio. 
     Referring to  FIGS.  1  and  2   , the ferroelectric memory device  10  may include a substrate  101  having source/drain regions  103 , an interface layer  110  on the substrate  101 , a high dielectric layer  120  on the interface layer  110 , a ferroelectric layer  130  on the high dielectric layer  120 , and a gate electrode layer  140  on the ferroelectric layer  130 . 
     Respective thicknesses of the substrate  101 , the interface layer  110 , the high dielectric layer  120 , the ferroelectric layer  130 , and the gate electrode layer  140  included in the ferroelectric memory device  10  are illustrative, and the inventive concept is not limited thereto. 
     The substrate  101  may include a semiconductor material, e.g., silicon (Si). In some embodiments, the substrate  101  may include a semiconductor element material, such as germanium (Ge), or a compound semiconductor material, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate  101  may have a silicon on insulator (SOI) structure. The substrate  101  may include a conductive region, e.g., an impurity-doped well or an impurity-doped structure. 
     The source/drain regions  103  and a channel region  105  between the source/drain regions  103  may be included in the substrate  101 . The substrate  101  may be doped with impurity ions to form the source/drain regions  103 . Although  FIG.  1    shows that the source/drain regions  103  are impurity regions formed inside the substrate  101 , the source/drain regions  103  are not limited thereto. The source/drain regions  103  may include an epitaxial layer formed on or inside the substrate  101 . The channel region  105  may be formed between the source/drain regions  103 . 
     The interface layer  110  may include an amorphous low-k material layer. For example, the interface layer  110  may include a material selected between silicon oxide (SiO) and silicon oxynitride (SiON) but is not limited thereto. The interface layer  110  may be on the substrate  101 . Particularly, the interface layer  110  may be in contact with the substrate  101  and on the channel region  105 . In addition, the thickness of the interface layer  110  may be about 3 Å to about 20 Å but is not limited thereto. 
     The high dielectric layer  120  may include a high-k material having a higher dielectric constant than SiO. That is, a permittivity of the high dielectric layer  120  may be greater than a permittivity of the interface layer  110 . For example, the high dielectric layer  120  may include a material selected from among hafnium oxide (HfO), doped HfO, zirconium oxide (ZrO), and/or hafnium silicon oxide (HfSiO, Si&gt;10%), i.e. HfSiO with at least 10% silicon. A dopant of the doped HfO may be a material selected from among zirconium (Zr), lanthanum (La), yttrium (Y), gadolinium (Gd), Si, aluminum (Al), and/or a combination thereof. In addition, the high dielectric layer  120  may have a composite layer structure, e.g., a single thin-film structure, a stacked thin-film structure, or a laminate structure. 
     In the ferroelectric memory device  10  according to some embodiments of the inventive concept, the high dielectric layer  120  may have an M-phase of a monoclinic crystal structure or a T-phase of a tetragonal crystal structure. That is, the high dielectric layer  120  may include a non-ferroelectric, which does not exhibit a spontaneous polarization characteristic. As described below, the high dielectric layer  120  may be crystallized to an M-phase or a T-phase by rapid thermal annealing (RTA). Particularly, in an annealing process of the high dielectric layer  120 , a process temperature of RTA may be about 400° C. to about 1200° C., and a process time at an RTA temperature may be about one second to about 200 seconds. In addition, the thickness of the high dielectric layer  120  may be about 3 Å to about 70 Å but is not limited thereto. 
     The ferroelectric layer  130  may include a high-k material having a higher dielectric constant than SiO. That is, a permittivity of the ferroelectric layer  130  may be greater than the permittivity of the interface layer  110 . For example, the ferroelectric layer  130  may include a material selected from among HfO, doped HfO, hafnium zirconium oxide (HfZrO), and/or HfSiO (2%&lt;Si&lt;10%), i.e. HfSiO with 2%-10% silicon. A dopant of the doped HfO may be a material selected from among Zr, La, Y, Gd, Si, Al, and/or a combination thereof. In addition, the ferroelectric layer  130  may have a composite layer structure, e.g., a single thin-film structure, a stacked thin-film structure, or a laminate structure. 
     In the ferroelectric memory device  10  according to some embodiments of the inventive concept, the ferroelectric layer  130  may have an O-phase of an orthorhombic crystal structure. That is, the ferroelectric layer  130  may include a ferroelectric, which exhibits a spontaneous polarization characteristic of a dipole moment. As described below, the ferroelectric layer  130  may be crystallized to an O-phase by laser annealing. Particularly, in an annealing process of the ferroelectric layer  130 , a process temperature of laser annealing may be about 500° C. to about 1200° C., and a process time at a peak temperature may be about 0.2 ms to about 20 ms. In addition, the thickness of the ferroelectric layer  130  may be about 3 Å to about 70 Å but is not limited thereto. Herein, the thickness of the ferroelectric layer  130  may be substantially the same as the thickness of the high dielectric layer  120 . 
     The gate electrode layer  140  may include a material selected from among titanium nitride (TiN), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), Si, Silicon germanium (SiGe), and/or a combination thereof but is not limited thereto. 
     In some embodiments of the inventive concept, the ferroelectric memory device  10  including the ferroelectric layer  130  is disclosed. Recently, research for a technique of securing a ferroelectric property from a paraelectric material has been briskly conducted. For example, the presence of a material having a ferroelectric property may be identified by transforming a lattice structure from an amorphous structure into an orthorhombic crystal structure by an annealing process. 
     In the ferroelectric memory device  10  according to the inventive concept, according to a polarity of a voltage applied to the gate electrode layer  140 , polarization having different polarities may be non-volatilely formed in the channel region  105  formed in the substrate  101  beneath the interface layer  110 . By differentiating densities of carriers conducted through the channel region  105  according to the polarities of the polarization, electrical information may be non-volatilely stored in the ferroelectric memory device  10 . 
     In general, the ferroelectric memory device  10  has vulnerable reliability in endurance. It may be analyzed that the reason why the endurance is vulnerable is because an applied voltage or a higher voltage than the applied voltage is applied to the interface layer  110  between the ferroelectric layer  130  and the substrate  101  in a switching process for a polarization characteristic of a ferroelectric. Therefore, an increase in a used frequency of a memory device may cause breakdown of the interface layer  110 . 
     To solve this problem, increasing the permittivity of the interface layer  110  is the most practical method. That is, as shown in  FIG.  2   , the higher the permittivity of the interface layer  110 , the lower an actual voltage applied to the interface layer  110 . In the ferroelectric memory device  10  according to some embodiments of the inventive concept, the high dielectric layer  120  having a high permittivity may be on the interface layer  110  to disperse a voltage applied to the interface layer  110  to the high dielectric layer  120 . Accordingly, the ferroelectric memory device  10  according to some embodiments of the inventive concept may have improved reliability in endurance and the like by mitigating electric field concentration in the interface layer  110 . 
       FIG.  3    is a cross-sectional view illustrating main components of a ferroelectric memory device  20  according to some embodiments of the inventive concept. 
     Most components included in the ferroelectric memory device  20  and materials of the components to be described below are substantially the same as or similar to those described above with reference to  FIGS.  1  and  2   . Therefore, for convenience of description, differences from the ferroelectric memory device  10  described above are mainly described. 
     Referring to  FIG.  3   , the ferroelectric memory device  20  may include the substrate  101  having the source/drain regions  103 , a first interface layer  111  on the substrate  101 , the high dielectric layer  120  on the first interface layer  111 , a second interface layer  112  on the high dielectric layer  120 , the ferroelectric layer  130  on the second interface layer  112 , and the gate electrode layer  140  on the ferroelectric layer  130 . 
     Respective thicknesses of the substrate  101 , the first interface layer  111 , the high dielectric layer  120 , the second interface layer  112 , the ferroelectric layer  130 , and the gate electrode layer  140  included in the ferroelectric memory device  20  are illustrative, and the inventive concept is not limited thereto. 
     Each of the first interface layer  111  and the second interface layer  112  may include an amorphous low-k material. For example, each of the first interface layer  111  and the second interface layer  112  may include a material selected between SiO and/or SiON but is not limited thereto. Herein, the first interface layer  111  and the second interface layer  112  may include substantially the same material. 
     The first interface layer  111  may be on the substrate  101 . Particularly, the first interface layer  111  may be in contact with the substrate  101  and on the channel region  105 . In addition, the thickness of the first interface layer  111  may be about 3 Å to about 20 Å but is not limited thereto. 
     The second interface layer  112  may be on the high dielectric layer  120 . Particularly, the second interface layer  112  may be in contact with the high dielectric layer  120  and beneath the ferroelectric layer  130 . In addition, the thickness of the second interface layer  112  may be about 3 Å to about 20 Å but is not limited thereto. Herein, the thickness of the first interface layer  111  may be substantially the same as the thickness of the second interface layer  112 . 
     In the ferroelectric memory device  20  according to some embodiments of the inventive concept, the high dielectric layer  120  may have an M-phase of a monoclinic crystal structure or a T-phase of a tetragonal crystal structure, and the ferroelectric layer  130  may have an O-phase of an orthorhombic crystal structure. The second interface layer  112  may function to clearly discriminate between the high dielectric layer  120  and the ferroelectric layer  130  having different crystal structures and different ferroelectric characteristics. 
       FIG.  4    is a cross-sectional view illustrating main components of a ferroelectric memory device  30  according to some embodiments of the inventive concept. 
     Most components included in the ferroelectric memory device  30  and materials of the components to be described below are substantially the same as or similar to those described above with reference to  FIGS.  1  and  2   . Therefore, for convenience of description, differences from the ferroelectric memory device  10  described above are mainly described. 
     Referring to  FIG.  4   , the ferroelectric memory device  30  may include a gate stack GS including a plurality of gate electrode layers  140  and a plurality of mold insulating layers  210  alternately stacked in a vertical direction, a gate dielectric layer GD including a ferroelectric part and a non-ferroelectric part, and a channel layer CH covering or overlapping the gate dielectric layer GD in the X direction. 
     A substrate  201  may include a semiconductor material, e.g., Si. The substrate  201  may correspond to the substrate  101  (see  FIG.  1   ) described above, and thus, a detailed description of the substrate  201  is omitted herein. 
     A base insulating layer  203  may be formed on the substrate  201 . The base insulating layer  203  may include a material including at least one of, for example, SiO, silicon nitride, and/or SiON. The base insulating layer  203  may include a single layer including one type of insulating layer, a dual layer including two types of insulating layers, or a multi-layer including a combination of at least three types of insulating layers. 
     An etch stop layer  205  may be formed on the base insulating layer  203 . An upper surface of the etch stop layer  205  may be uneven, and a lower surface of the etch stop layer  205  may be flat. The etch stop layer  205  may include, for example, silicon nitride or SiO. 
     The plurality of mold insulating layers  210  may be on the etch stop layer  205  at certain intervals therebetween in the vertical direction (Z direction). The plurality of mold insulating layers  210  may include at least one of SiO, silicon nitride, and/or SiON. In some embodiments, the plurality of mold insulating layers  210  and the etch stop layer  205  may include materials having etch selectivities for each other. For example, when the mold insulating layer  210  includes SiO, the etch stop layer  205  may include silicon nitride. 
     A buried insulating layer  250  may pass through the plurality of mold insulating layers  210 . For example, the etch stop layer  205  may be on a lower surface of the buried insulating layer  250 . In some embodiments, buried insulating layers  250  may be separated from each other in a first horizontal direction (X direction) and extend in a second horizontal direction (Y direction). The buried insulating layer  250  may include, for example, SiO, silicon nitride, or a combination thereof. 
     The channel layer CH may include the channel region  105  on an inner wall of a trench in the vertical direction (Z direction) and a channel buried layer  230  at least partially or completely filling the inside of the trench on the channel region  105 . 
     Channel layers CH may be separated above the substrate  201  from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction) and extend in the vertical direction (Z direction). In some embodiments, unlike shown in  FIG.  4   , each of the channel layers CH may have a tapered shape in which widths of each of the channel layers CH in the first and second horizontal directions (X and Y directions) gradually decrease toward the substrate  201 . 
     The channel region  105  may be on an inner wall of the channel buried layer  230  inside the vertical trench. Although  FIG.  4    shows that the channel region  105  extends to conformally surround the channel buried layer  230 , the channel region  105  is not limited thereto. 
     The gate dielectric layer GD may include a ferroelectric part and a non-ferroelectric part. Particularly, the gate dielectric layer GD may include the interface layer  110 , the high dielectric layer  120 , and the ferroelectric layer  130 . The interface layer  110 , the high dielectric layer  120 , and the ferroelectric layer  130  may be arranged in their order inside each of side opening parts extending in the first horizontal direction (X direction) by passing through the plurality of mold insulating layers  210 . 
     Particularly, interface layers  110  may be adjacent to one end of the channel region  105 , extend in the second horizontal direction (Y direction), and be separated from each other in the vertical direction (Z direction). The high dielectric layer  120  may be adjacent to one end of the interface layer  110  and extend in the second horizontal direction (Y direction), and high dielectric layers  120  may be separated from each other in the vertical direction (Z direction). The ferroelectric layer  130  may be adjacent to one end of the high dielectric layer  120  and extend in the second horizontal direction (Y direction), and ferroelectric layers  130  may be separated from each other in the vertical direction (Z direction). That is, the mold insulating layer  210  may be between two interface layers  110 , between two high dielectric layers  120 , and between two ferroelectric layers  130  respectively adjacent in the vertical direction (Z direction). 
     Gate electrode layers  140  may face each other with the channel layer CH therebetween. The gate electrode layer  140  may be adjacent to one end of the ferroelectric layer  130  and extend in the second horizontal direction (Y direction), and gate electrode layers  140  may be separated from each other in the vertical direction (Z direction). The mold insulating layer  210  may be between two gate electrode layers  140  adjacent in the vertical direction (Z direction). 
     In some embodiments, gate barrier layers  142  may be respectively inside the side opening parts extending in the first horizontal direction (X direction) by passing through the plurality of mold insulating layers  210 . The gate barrier layer  142  may be in contact with the mold insulating layer  210  and the gate electrode layer  140 , and the inside of the gate barrier layer  142  may be at least partially or completely filled with the gate electrode layer  140 . 
     In some embodiments, although not shown, a select transistor may be around a memory cell transistor. 
     The ferroelectric memory device  30  may operate in a similar manner to a tunneling field-effect transistor storing data in a memory cell by using a spontaneous polarization characteristic of the ferroelectric layer  130 . That is, the ferroelectric memory device  30  may function as dynamic random access memory (DRAM) on which a read/write operation of stored one-bit data may be performed even without using a capacitor. In this manner, the ferroelectric memory device  30  that is capacitorless DRAM may be implemented. 
     In addition, a three-dimensional transistor including the gate stack GS, as shown in  FIG.  4   , has been described as the ferroelectric memory device  30  according to the inventive concept, but the ferroelectric memory device  30  is not limited thereto. For example, the ferroelectric memory device  30  according to the inventive concept may include various types of transistors, such as fin-type field-effect transistor (FinFET), a transistor including nanowires, and a transistor including nanosheets (i.e., a multi bridge channel FET)(MBCFET®). 
       FIG.  5    is a flowchart illustrating a method S 10  of manufacturing a ferroelectric memory device, according to some embodiments of the inventive concept. 
     Referring to  FIG.  5   , the method S 10  of manufacturing a ferroelectric memory device may include a process order of first to fourth operations S 110  to S 140 . 
     When a certain embodiment is differently implemented, a particular process order may be differently performed from the order to be described below. For example, two continuous processes may be performed substantially at the same time or performed in an opposite order. 
     The method S 10  of manufacturing a ferroelectric memory device, according to the inventive concept, may include first operation S 110  of forming an interface layer on a substrate, second operation S 120  of forming a high-k material layer on the interface layer and performing a first annealing process, third operation S 130  of forming a ferroelectric material layer on a high dielectric layer and performing a second annealing process, and fourth operation S 140  of forming a gate electrode layer on a ferroelectric layer and performing a third annealing process. 
     A technical feature of each of first to fourth operations S 110  to S 140  is described below in detail with reference to  FIGS.  6  to  9   . 
       FIGS.  6  to  9    are cross-sectional views for describing, in a process order, a method of manufacturing a ferroelectric memory device, according to some embodiments of the inventive concept. 
     Referring to  FIG.  6   , the interface layer  110  may be formed on the substrate  101 . 
     The substrate  101  may include a semiconductor material, e.g., Si. In some embodiments, the substrate  101  may have an SOI structure. 
     In some embodiments, the source/drain regions  103  and the channel region  105  between the source/drain regions  103  may be included in the substrate  101 . The source/drain regions  103  may include an epitaxial layer formed on or inside the substrate  101 . The channel region  105  may be formed between the source/drain regions  103 . 
     In some embodiments, unlike shown in  FIG.  6   , the source/drain regions  103  and the channel region  105  may be formed in an impurity doping process after finally forming a gate structure. 
     The interface layer  110  may include an amorphous low-k material layer. For example, the interface layer  110  may include a material selected between SiO and/or SiON. The interface layer  110  may be in contact with the substrate  101  and on the channel region  105 . 
     Referring to  FIG.  7   , a high-k material layer  120 L may be formed on the interface layer  110 , and a first annealing process AP 1  may be performed. 
     The high-k material layer  120 L may include a high-k material having a higher dielectric constant than SiO. For example, the high-k material layer  120 L may include a material selected from among HfO, doped HfO, ZrO, and/or HfSiO (Si&gt;10%). A dopant of the doped HfO may be a material selected from among Zr, La, Y, Gd, Si, Al, and/or a combination thereof. 
     The first annealing process AP 1  may be performed on the high-k material layer  120 L. The first annealing process AP 1  may be an RTA process. For example, the RTA process may include a standby operation, a slow ramp operation, a fast ramp operation, an RTA operation, and a cooling operation. A process temperature in the first annealing process AP 1  may be about 400° C. to about 1200° C., and a process time in the RTA operation may be about one second to about 200 seconds. 
     As described above, by performing the first annealing process AP 1  with RTA in which annealing is performed at a high temperature for a relatively long time, the high-k material layer  120 L may be crystallized to an M-phase of a monoclinic crystal structure or a T-phase of a tetragonal crystal structure. That is, the high-k material layer  120 L may be crystallized to a high dielectric layer  120  (see  FIG.  8   ) including a non-ferroelectric, which does not exhibit a spontaneous polarization characteristic. 
     Referring to  FIG.  8   , a ferroelectric material layer  130 L may be formed on the high dielectric layer  120 , and a second annealing process AP 2  may be performed. 
     The ferroelectric material layer  130 L may include a high-k material having a higher dielectric constant than SiO. For example, the ferroelectric material layer  130 L may include a material selected from among HfO, doped HfO, HfZrO, and/or HfSiO (2%&lt;Si&lt;10%). A dopant of the doped HfO may be a material selected from among Zr, La, Y, Gd, Si, Al, and/or a combination thereof. 
     The second annealing process AP 2  may be performed on the ferroelectric material layer  130 L. The second annealing process AP 2  may be a laser annealing process. For example, the laser annealing process may include a standby operation and a peak operation. A process temperature in the second annealing process AP 2  may be about 500° C. to about 1200° C., and a process time in the peak operation may be about 0.2 ms to about 20 ms. 
     As described above, by performing the second annealing process AP 2  with laser annealing in which annealing is performed at a high temperature for a relatively short time, the ferroelectric material layer  130 L may be crystallized to an O-phase of an orthorhombic crystal structure. That is, the ferroelectric material layer  130 L may be crystallized to a ferroelectric layer  130  (see  FIG.  9   ) including a ferroelectric, which exhibits a spontaneous polarization characteristic. 
     Referring to  FIG.  9   , the gate electrode layer  140  may be formed on the ferroelectric layer  130 , and a third annealing process AP 3  may be performed. 
     The gate electrode layer  140  may include a material selected from among TiN, W, Mo, TaN, Ta, Ti, Si, SiGe, and/or a combination thereof but is not limited thereto. 
     The third annealing process AP 3  may be performed on the gate electrode layer  140 . The third annealing process AP 3  may be an RTA process or a laser annealing process. 
     In the method S 10  (see  FIG.  5   ) of manufacturing a ferroelectric memory device, according to the inventive concept, at least one process selected between the second annealing process AP 2  (see  FIG.  8   ) and the third annealing process AP 3  may be performed. That is, a first case in which both the second annealing process AP 2  (see  FIG.  8   ) and the third annealing process AP 3  are performed, a second case in which the second annealing process AP 2  (see  FIG.  8   ) is performed while the third annealing process AP 3  is not performed, and a third case in which the second annealing process AP 2  (see  FIG.  8   ) is not performed while the third annealing process AP 3  is performed may be considered. In all of the first to third cases, inventors may be aware through experiments that each of the high dielectric layer  120  and the ferroelectric layer  130  is crystallized to a phase of a desired crystal structure. 
       FIG.  10    is a flowchart illustrating a method S 20  of manufacturing a ferroelectric memory device, according to some embodiments of the inventive concept. 
     Referring to  FIG.  10   , the method S 20  of manufacturing a ferroelectric memory device may include a process order of first to fourth operations S 210  to S 240 . 
     When a certain embodiment is differently implemented, a particular process order may be differently performed from the order to be described below. For example, two continuous processes may be performed substantially at the same time or performed in an opposite order. 
     The method S 20  of manufacturing a ferroelectric memory device, according to the inventive concept, may include first operation S 210  of forming an interface layer on a substrate, second operation S 220  of forming a high-k material layer and a ferroelectric material layer on the interface layer, third operation S 230  of performing a first annealing process on the high-k material layer and the ferroelectric material layer, and fourth operation S 240  of forming a gate electrode layer on a ferroelectric layer and performing a second annealing process. 
     A technical feature of each of first to fourth operations S 210  to S 240  is described below in detail with reference to  FIGS.  11  to  14   . 
       FIGS.  11  to  14    are cross-sectional views for describing, in a process order, a method of manufacturing a ferroelectric memory device, according to some embodiments of the inventive concept. 
     Referring to  FIG.  11   , the interface layer  110  may be formed on the substrate  101 . 
     The substrate  101  may include a semiconductor material, e.g., Si. In some embodiments, the substrate  101  may have an SOI structure. 
     In some embodiments, the source/drain regions  103  and the channel region  105  between the source/drain regions  103  may be included in the substrate  101 . The source/drain regions  103  may include an epitaxial layer formed on or inside the substrate  101 . The channel region  105  may be formed between the source/drain regions  103 . 
     In other embodiments, unlike shown in  FIG.  11   , the source/drain regions  103  and the channel region  105  may be formed in an impurity doping process after finally forming a gate structure. 
     The interface layer  110  may include an amorphous low-k material layer. For example, the interface layer  110  may include a material selected between SiO and/or SiON. The interface layer  110  may be in contact with the substrate  101  and on the channel region  105 . 
     Referring to  FIG.  12   , the high-k material layer  120 L and the ferroelectric material layer  130 L may be formed on the interface layer  110 . 
     The high-k material layer  120 L may include a high-k material having a higher dielectric constant than SiO. For example, the high-k material layer  120 L may include a material selected from among HfO, doped HfO, ZrO, and/or HfSiO (Si&gt;10%). 
     The ferroelectric material layer  130 L may include a high-k material having a higher dielectric constant than SiO. For example, the ferroelectric material layer  130 L may include a material selected from among HfO, doped HfO, HfZrO, and/or HfSiO (2%&lt;Si&lt;10%). 
     A dopant of the doped HfO may be a material selected from among Zr, La, Y, Gd, Si, Al, and/or a combination thereof. Herein, the ferroelectric material layer  130 L may include a different material from a material of the high dielectric layer  120 . 
     The high-k material layer  120 L and the ferroelectric material layer  130 L may be formed by an in-situ scheme in the same process facility. The process facility may perform atomic layer deposition (ALD) but is not limited thereto. 
     Referring to  FIG.  13   , a first annealing process APA may be performed on the high-k material layer  120 L and the ferroelectric material layer  130 L. 
     The first annealing process APA may be performed on both the high-k material layer  120 L and the ferroelectric material layer  130 L. The first annealing process APA may be a laser annealing process. For example, the laser annealing process may include a standby operation and a peak operation. A process temperature in the first annealing process APA may be about 500° C. to about 1200° C., and a process time in the peak operation may be about 0.2 ms to about 20 ms. 
     As described above, by performing the first annealing process APA on different materials with laser annealing in which annealing is performed at a high temperature for a relatively short time, the high-k material layer  120 L may be crystallized to an M-phase of a monoclinic crystal structure or a T-phase of a tetragonal crystal structure, and the ferroelectric material layer  130 L may be crystallized to an O-phase of an orthorhombic crystal structure. That is, the high-k material layer  120 L may be crystallized to a high dielectric layer  120  (see  FIG.  14   ) including a non-ferroelectric, which does not exhibit a spontaneous polarization characteristic, and the ferroelectric material layer  130 L may be crystallized to a ferroelectric layer  130  (see  FIG.  14   ) including a ferroelectric, which exhibits the spontaneous polarization characteristic. 
     Referring to  FIG.  14   , the gate electrode layer  140  may be formed on the ferroelectric layer  130 , and a second annealing process APB may be performed. 
     The gate electrode layer  140  may include a material selected from among TiN, W, Mo, TaN, Ta, Ti, Si, SiGe, and/or a combination thereof but is not limited thereto. 
     The second annealing process APB may be performed on the gate electrode layer  140 . The second annealing process APB may be an RTA process or a laser annealing process. 
     In the method S 20  (see  FIG.  10   ) of manufacturing a ferroelectric memory device, according to the inventive concept, at least one process selected between the first annealing process APA (see  FIG.  13   ) and the second annealing process APB may be performed. 
     That is, a fourth case in which both the first annealing process APA (see  FIG.  13   ) and the second annealing process APB are performed, a fifth case in which the first annealing process APA (see  FIG.  13   ) is performed while the second annealing process APB is not performed, and a sixth case in which the first annealing process APA (see  FIG.  13   ) is not performed while the second annealing process APB is performed may be considered. In all of the fourth to sixth cases, inventors may be aware through experiments that each of the high dielectric layer  120  and the ferroelectric layer  130  is crystallized to a phase of a desired crystal structure. 
       FIG.  15    is a block diagram illustrating a system  1000  including a ferroelectric memory device, according to some embodiments of the inventive concept. 
     Referring to  FIG.  15   , the system  1000  may include a controller  1010 , an input/output device  1020 , a memory device  1030 , an interface  1040 , and a bus  1050 . 
     The system  1000  may be a mobile system or a system configured to transmit or receive information. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card. 
     The controller  1010  is to control an execution program in the system  1000  and may include a microprocessor, a digital signal processor, a microcontroller, or a similar device. 
     The input/output device  1020  may be used to input or output data to or from the system  1000 . The system  1000  may be connected to an external device, e.g., a personal computer or a network, and exchange data with the external device by using the input/output device  1020 . The input/output device  1020  may include, for example, a touch screen, a touch pad, a keyboard, or a display. 
     The memory device  1030  may store data for an operation of the controller  1010  or data processed by the controller  1010 . The memory device  1030  may include any one of the ferroelectric memory devices  10 ,  20 , and/or  30  according to the inventive concept, which have been described above. 
     The interface  1040  may be a data transport passageway between the system  1000  and an external device. The controller  1010 , the input/output device  1020 , the memory device  1030 , and the interface  1040  may communicate with each other via the bus  1050 . 
     While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.