Patent Publication Number: US-2023137013-A1

Title: Solid-state power interrupters

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Divisional of U.S. patent Ser. No. 17/115,753, filed on Dec. 8, 2020, which is a Continuation-in-Part of U.S. patent application Ser. No. 16/029,549, filed on Jul. 7, 2018, the disclosures of which are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to power control systems and devices and, in particular, solid-state power interrupter devices and for disrupting power to loads. 
     BACKGROUND 
     Electrical power interrupters are an essential component in electrical distribution systems and are often positioned between an incoming high-current utility supply circuit and lower current branch circuits within a given building or home structure to protect branch circuit conductors and electrical loads from being exposed to over-current conditions. There are several types of over current conditions including overload conditions and fault conditions. An overload condition is defined as operation of equipment in excess of its normal, full-load rating, or a branch circuit in excess of its ampacity which, when the overload persists for a sufficient period of time, would cause damage or dangerous overheating. Fault conditions comprise unintended or accidental load conditions that typically produce much higher over-current conditions than do overloads, depending on the impedance of the fault. A fault producing the maximum over-current condition is referred to as a short-circuit or a “bolted fault.” 
     Conventional power interrupters are electromechanical in nature and have electrical contacts that are physically separated by either manual intervention of an operator lever or automatically upon the occurrence of a fault condition or prolonged over current condition, in which cases the circuit interrupter is deemed to be “tripped.” The separation of the electrical contacts of a circuit breaker can be performed electromagnetically or mechanically, or a combination of both. A significant problem with conventional circuit interrupters is that they are slow to react to fault conditions due to their electromechanical construction, and exhibit large variations in both the time to trip and the current trip limit in response to a fault or prolonged over-current conditions. Conventional power interrupters typically require at least several milliseconds to isolate a fault condition. The slow reaction time is undesirable since it raises the risk of hazardous fire, damage to electrical equipment, and arc-flashes, which can occur at the short-circuit location when a bolted fault is not isolated quickly enough. 
     SUMMARY 
     Embodiments of the disclosure include solid-state power interrupter devices and methods for interrupting power from a source to a load. For example, an exemplary embodiment includes a power interrupter device which comprises a solid-state bidirectional switch and control circuitry. The solid-state bidirectional switch is connected between an input terminal and an output terminal of the power interrupter device. The control circuitry configured to control the solid-state bidirectional switch. The control circuitry comprises driver circuitry and fault detection circuitry. The driver circuitry is configured to generate a regulated direct current (DC) voltage using current drawn from an input power source applied to the input terminal of the power interrupter device, and apply the regulated DC voltage to a control input of the solid-state bidirectional switch. The fault detection circuitry is configured to (i) sense a level of load current flowing in an electrical path between the input terminal and the output terminal of the power interrupter device, (ii) detect an occurrence of a fault condition based on the sensed load current level, and (iii) short the control input of the solid-state bidirectional switch to place the solid-state bidirectional switch in a switched-off state, in response to detecting the occurrence of a fault condition. 
     Other embodiments will be described in the following detailed description of embodiments, which is to be read in conjunction with the accompanying figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    schematically illustrates a solid-state power interrupter according to an exemplary embodiment of the disclosure. 
         FIG.  2    schematically illustrates a solid-state power interrupter according to another exemplary embodiment of the disclosure. 
         FIG.  3    schematically illustrates a solid-state power interrupter according to another exemplary embodiment of the disclosure. 
         FIG.  4    schematically illustrates a solid-state power interrupter according to another exemplary embodiment of the disclosure. 
         FIG.  5    schematically illustrates a solid-state power interrupter according to another exemplary embodiment of the disclosure. 
         FIG.  6    schematically illustrates an AC-to-DC converter and regulator circuit according to an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Embodiments of the disclosure will now be described in further detail with regard to solid-state power interrupter devices and techniques for interrupting power from a source to a load based on, e.g., a detection of a fault condition (e.g., a short-circuit fault, an over-current fault, etc.) or in response to external control signals. It is to be understood that same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. The term “exemplary” as used herein means “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not to be construed as preferred or advantageous over other embodiments or designs. 
       FIG.  1    schematically illustrates a solid-state power interrupter according to an exemplary embodiment of the disclosure. In particular,  FIG.  1    illustrates a solid-state power interrupter  100  connected between a utility power supply  10  (referred to herein as AC mains  10 ) and a load  20  which is connected to a branch circuit that is protected by the solid-state power interrupter  100 . The solid-state power interrupter  100  has input terminals that are connected to a hot phase  11  (referred to as “line hot L”) and a neutral phase  12  (referred to as “line neutral N”) of the AC mains  10 , and output terminals that are connected a load hot line  21  and a load neutral line  22  of the load  20 . In particular, the solid-state power interrupter  100  comprises a line hot terminal  100 A, a line neutral terminal  100 B, a load hot terminal  100 C, a load neutral terminal  100 D (and optionally an earth ground terminal not shown). The line hot terminal  100 A is coupled to the line hot  11  of the AC mains  10 , the line neutral terminal  100 B is coupled to the line neutral  12  of the AC mains  10 , the load hot terminal  100 C is coupled to the load hot line  21  of the load  20 , and the load neutral terminal  100 D is coupled to the neutral line  22  of the load  20 . As further illustrated in  FIG.  1   , the line neutral  12  is shown bonded to earth ground  14  (GND), which provides added protection as is known in the art. The earth ground  14  is typically connected to a ground bar in a circuit breaker distribution panel, wherein the ground bar is bonded to a neutral bar in the circuit breaker distribution panel. 
     The solid-state power interrupter  100  comprises a double pole single throw (DPST) switch circuit which comprises a first solid-state switch  102 , a second solid-state switch  104 , and control circuitry  110  which comprises a first control circuit block  112 , and a second control circuit block  114 . In some embodiments, the first and second solid-state switches  102  and  104  comprise power MOSFET (metal-oxide semiconductor field-effect transistor) devices and, in particular, N-type enhancement MOSFET devices having gate terminals (G), drain terminals (D), and source terminals (S) as shown. The first and second solid-state switches  102  and  104  (alternatively MOSFET switches  102  and  104 ) comprise respective intrinsic body diodes  102 - 1  and  104 - 1 , which represent P-N junctions between a P-type substrate body and N-doped drain regions of the MOSFET devices. In this regard, the body diodes  102 - 1  and  104 - 1  are intrinsic elements of the MOSFET switches  102  and  104  (i.e., not discrete elements). It is to be noted that the intrinsic body-to-source diodes of the first and second solid-state switches  102  and  104  are not shown as it is assumed that they are shorted out by connections between the source regions and the substrate bodies (e.g., N+ source and P body junction are shorted through source metallization). 
     The first solid-state switch  102  is serially connected in an electrical path (referred to as “hot line path”) between the line hot terminal  100 A and the load hot terminal  100 C of the solid-state interrupter  100 . The second solid-state switch  104  is serially connected in an electrical path (referred to as “neutral line path”) between the line neutral terminal  100 B and the load neutral terminal  100 D of the solid-state interrupter  100 . The first control circuit block  112  controls a gate-to-source voltage (V GS ) that is applied to the first solid-state switch  102  to control the activation and deactivation of the first solid-state switch  102 . The second control circuit block  114  controls a gate-to-source voltage that is applied to the second solid-state switch  104  to control the activation and deactivation of the second solid-state switch  104 . The first and second solid-state switches  102  and  104  collectively comprise a solid-state bidirectional switch that is configured to enable bidirectional current flow between the AC mains  10  and the load  20  (i.e., conduct positive current or negative current) when the first and second solid-state switches  102  and  104  are in a switched-on state, and block current flow between the AC mains  10  and the load  20  when the first and second solid-state switches  102  and  104  are in a switched-off state. 
     More specifically, in normal operation of the solid-state power interrupter  100 , during a positive half cycle of an AC supply voltage waveform of the AC mains  10 , a positive current flows in the hot line path through the first solid-state switch  102 , through the load  20 , and then in the neutral line path through the forward biased body diode  104 - 1 , and back to the AC mains  10 . On the other hand, during a negative half cycle of the AC supply voltage waveform of the AC mains  10 , a negative current flows in the neutral line path through the second solid-state switch  104 , through the load  20 , and then in the hot line path through the forward biased body diode  102 - 1 , and back to the AC mains  10 . The exemplary configuration of simultaneously controlling AC switches on both the line and the neutral is referred to as double-pole switching and is applied to the two lines (hot and neural lines) of opposite phase from the single AC energy source. 
     The control circuitry  110  implements various functions for controlling the activation and deactivation of the first and second solid-state switches  102  and  104 . For example, in some embodiments, the control circuitry  110  comprises self-biasing driver circuitry which is configured to utilize AC power from the AC mains  10  to generate regulated DC voltages to drive the gate terminals of the first and second solid-state switches  102  and  104 . Further, in some embodiments, the control circuitry  110  comprises fault detection circuitry which is configured to sense an amount of load current flowing in the hot line path and/or the neutral line path through the solid-state interrupter  100 , and detect an occurrence of a fault condition, such as short-circuit fault, an over-current fault, etc., based on the sensed current level. In response to detecting a fault condition, the fault detection circuitry is configured to short the control input (e.g., gate terminal) of at least one of the solid-state switches  102  and  104  to interrupt power to the load  20 . 
     Furthermore, in some embodiments, the control circuitry  110  comprises a control switch to implement a forced turn-off control mode in which the solid-state power interrupter  100  is controlled by external control signals. For example, in some embodiments, the control circuitry  110  implements an optical switch which is configured to short the control inputs of the first and second solid-state switches  102  and  104  to place the first and second solid-state switches  102  and  104  in a switched-off state, in response to an optical control signal applied to the optical switch. In some embodiments, the control circuitry  110  implements a forced turn-off control mode in which the first and second solid-state switches  102  and  104  are turned-off in response to the detection of certain events including, but not limited to, detection of fault events, detection of hazardous environmental conditions, remote commands for circuit interruption, etc. As explained in further detail below, the forced turn-off control mode can be initiated on command by, e.g., direct hardware fault sensing and control, and/or through a galvanically isolated control input based on, but not limited to, optical, magnetic, capacitive, and RF isolation technologies. 
       FIG.  2    schematically illustrates a solid-state power interrupter according to another exemplary embodiment of the disclosure. In particular,  FIG.  2    schematically illustrates a solid-state power interrupter  200  which is similar to the solid-state power interrupter  100  of  FIG.  1   , except that the solid-state power interrupter  200  further comprises isolation circuitry  210  to provide galvanic isolation between the solid-state power interrupter  200  and the load  20  when the first and second solid-state switches  102  and  104  are turned off. In some embodiments, the isolation circuitry  210  is connected across the load hot terminal  100 C and the load neutral terminal  100 D. The isolation circuitry  210  is configured to shunt the load  20  from unwanted leakage current flow from the AC mains  10  though the switched-off solid-state switches  102  and  104 . When the first and second solid-state switches  102  and  104  are turned-off, the first and second solid-state switches  102  and  104  can generate a small amount of leakage current. For example, when the first and second solid-state switches  102  and  104  are in a switched-off state (e.g., cutoff mode), a small amount of leakage current (e.g.,  200  uA) can flow through the first and second solid-state switches  102  and  104  and generate a sizable voltage drop across the load  20  when the load  20  comprises a high impedance load. In this regard, when activated, the isolation circuitry  210  provides a short circuit between the load hot terminal  100 C and the load neutral terminal  100 D to shunt the load  20  from any unwanted leakage current flow though the switched-off solid-state switches  102  and  104 . 
     In some embodiments, the isolation circuitry  210  comprises a control circuit  220 , a solid-state bidirectional switch comprising MOSFET switches  222  and  224  and associated body diodes  222 - 1  and  224 - 1 . When the first and second solid-state switches  102  and  104  are turned off, the control circuit  220  generates gate control voltages to activate the MOSFET switches  222  and  224 , and thereby create a short circuit path between the load hot terminal  100 C and the load neutral terminal  100 D, which allows any leakage current from the deactivated first and second solid-state switches  102  and  104  to flow through the isolation circuitry  210 , and thereby shunt the unwanted leakage to prevent such leakage current from flowing into the load  20 . The effect of bypassing or shunting leakage current away from the load  20  serves to isolate (e.g., galvanically isolate) the load  120  from the solid-state power interrupter  200  when the first and second switches  102  and  104  are in a switched-off state in a way that is equivalent to a galvanic isolation technique which implements an air-gap between the AC mains  10  and the load  20 . In this configuration, the isolation circuitry  210  serves as a pseudo air-gap. 
       FIG.  3    schematically illustrates a solid-state power interrupter according to another exemplary embodiment of the disclosure. In particular,  FIG.  3    schematically illustrates a solid-state power interrupter  300  comprising a single pole single throw (SPST) switch framework in which the first solid-state switch  102  and the second solid-state switch  104  are serially connected in the hot line path between the line hot terminal  100 A and the load hot terminal  100 C, thereby providing a solid-state bidirectional switch disposed in the hot line path of the solid-state power interrupter  300 . The solid-state power interrupter  300  further comprises control circuitry  310  to implement an exemplary embodiment of the control circuitry  110  and associated functions (e.g., self-biasing driver circuitry, fault detection circuitry, force-turn off control circuitry) as discussed above in conjunction with  FIG.  1   . 
     For example, as schematically illustrated in  FIG.  3   , the control circuitry  310  comprises a current sense resistor  312 , an operational amplifier  314 , a first control switch  316 , a second control switch  318 , a first diode  320 , a second diode  322 , a first resistor  324 , a second resistor  326 , a third resistor  328 , a Zener diode  330 , and a capacitor  332 . In some embodiments, the first and second diodes  320  and  322 , the resistors  324 ,  326 , and  328 , the Zener diode  330 , and the capacitor  332  collectively implement self-biasing driver circuitry that is configured to utilize AC power from the AC mains  10  to generate a regulated DC voltage at an internal node N 1  to drive the control inputs (e.g., gate terminals) of the first and second solid-state switches  102  and  104  and thereby activate the first and second solid-state switches  102  and  104 . 
     As schematically illustrated in  FIG.  3   , the first diode  320  and the first resistor  324  are serially connected between the hot line path (e.g., the line hot terminal  100 A node) and the internal node N 1 . In addition, the second diode  322  and the second resistor  326  are serially connected between the neutral line path (e.g., the line neutral terminal  100 B node) and the internal node N 1 . In operation, during a negative half cycle of the AC supply voltage waveform of the AC mains  10 , the second diode  322  is activated, and current flows from the line neutral  12  to the line hot  11  through the second diode  322 , the second resistor  326 , the capacitor  332 , and the body diode  102 - 1  of the first solid-state switch  102 . This current flow causes a voltage across the capacitor  332  to increase until the capacitor voltage reaches a clamping voltage (i.e., Zener voltage) of the Zener diode  330 . In other words, the Zener voltage of the Zener diode  330  limits the maximum level of the self-bias turn-on threshold voltage (VGs) which is generated on the internal node N 1  to turn on the first and second solid-state switches  102  and  104 . 
     In this exemplary embodiment, the voltage level on the internal node N 1  is limited by the Zener voltage (i.e., reverse breakdown voltage) of the Zener diode  330  such that the Zener diode  330  serves as a solid-state clamp to limit the driving voltage on the internal node N 1  to drive the control inputs (e.g., gate terminals) of the first and second solid-state switches  102  and  104 . In this regard, the self-bias driving voltage is input-line voltage independent, as the level of the self-bias driving voltage is limited by the solid-state clamp. During a positive half cycle of AC supply voltage waveform of the AC mains  10 , the first diode  320  is activated, and current flows from the line hot  11  to the line neutral  12  through the first diode  320 , the first resistor  324 , the capacitor  332 , and the body diode  104 - 1  of the second solid-state switch  104 . This current flow causes charge to trickle across the Zener diode  330  to maintain the regulated DC voltage (i.e., the Zener voltage) on the internal node N 1  for driving the control terminal of the first and second solid-state switches  102  and  104 . 
     Further, in some embodiments, the current sense resistor  312 , the operational amplifier  314 , and the first control switch  316  collectively comprise a fault detection circuit of the control circuitry  310 . The fault detection circuit is configured to (i) sense an amount of load current flowing in the hot line path through the solid-state interrupter  300 , (ii) detect an occurrence of a fault condition, such as short-circuit fault, an over-current fault, etc., based on the sensed current level, and (iii) in response to detecting the fault condition, shunt the control inputs (e.g., gate terminals) of the first and second solid-state switches  102  and  104  to thereby deactivate the first and second solid-state switches  102  and  104  and interrupt power to the load  20 . 
     As schematically illustrated in  FIG.  3   , the sense resistor  312  is serially connected between the source terminals (S) (e.g., between nodes N 2  and N 3 ) of the first and second solid-state switches  102  and  104 . The operational amplifier  314  comprises first and second input terminals (e.g., differential input terminals) which are connected to the nodes N 2  and N 3  across the sense resistor  312 . The operational amplifier  314  comprises an output terminal that is connected to the first control switch  316 . In some embodiments, the first control switch  316  comprises a bipolar junction transistor (BJT) device having a base terminal connected to the output terminal of the operational amplifier  314 , an emitter terminal connected to the node N 3 , and a collector terminal connected to the gate terminals of the first and second solid-state switches  102  and  104 . 
     During operation, the sense resistor  312  generates a burden voltage or sense voltage as a result of load current flowing in the hot line path through the sense resistor  312 . The sense voltage is applied to the differential inputs of the operational amplifier  314 , and the operational amplifier  314  amplifies the sense voltage to generate an output voltage that is applied to the base terminal of the first control switch  316 . When the output voltage of operational amplifier  314  is high enough (e.g., base-emitter voltage VBE is about 0.7 V), the first control switch  316  will turn on, which shunts the gate and source terminals of the first and second solid-state switches  102  and  104 , and thereby causes the first and second solid-state switches  102  and  104  to turn off and interrupt power to the load  20 . 
     In some embodiments, the sense resistor  312  has a very small resistance value such as on the order of 1 milliohm or less (e.g., 10× less than 1 milliohm). In this regard, the sense voltage across the sense resistors  312  is negligible in terms of causing minimal power dissipation, but yet sufficient for current sensing. The operational amplifier  314  is configured to have sufficient gain to be able to drive the first control switch  316 , even with a relatively small voltage input corresponding to the voltage drop across the sense resistor  312 . In this regard, the resistance value of the sense resistor  312  and the gain of the operational amplifier  314  are selected for a target load current limit (e.g., 100 amperes) to ensure that the output of the operational amplifier  314  generates a sufficient voltage to turn on the first control switch  316  when the magnitude of load current that flows through the sense resistor  312  reaches or exceeds the target current limit. In other words, the sense resistor  312  can have a relatively small resistance value (e.g., 1 milliohm) which generates a relatively small sense voltage and minimizes power dissipation for normal circuit operation, but which is amplified by the operational amplifier  314  to enable over-current detection using the small sense voltage. Moreover, the resistance value of the sense resistor  312  can remain fixed (e.g., 1 milliohm) while the gain of the operational amplifier  314  is adjusted as desired to adjust the target load current level for over-current and short circuit detection. 
     Furthermore, in some embodiments, the control circuitry  310  includes the second control switch  318  to implement a forced turn-off control circuit in which the solid-state power interrupter  300  is controlled by a control signal  318 - s  (e.g., optical signal) which is generated by, e.g., an external control system or device. In particular, the second control switch  318  is activated in response to the control signal  318 - s , wherein activation of the second control switch  318  serves to shunt the gate and source terminals of the first and second solid-state switches  102  and  104 , which thereby causes the first and second solid-state switches  102  and  104  to turn off and interrupt power to the load  20 . 
     In some embodiments, the second control switch  318  comprises a phototransistor (e.g., an optical BJT device which includes a photodiode junction) or other types of optically controlled switches which receive optical signals from complementary light emitting diodes (LED) that are controlled by, e.g., a sensor device or a microcontroller. The control signal  318 - s  can be generated in response to remote commands (e.g., alarm signals) received from a local or a remote controller that is configured to detect fault conditions, or in response to remote commands received from an individual who can control operation of the solid-state power interrupter  300  through smart technologies implemented using, for example, an Internet-of-Things (IoT) wireless computing network, wherein the solid-state power interrupter  300  comprises a smart wireless IoT device. 
     In some embodiments, the control signal  318 - s  is generated in response to the detection of hazardous environmental conditions by one or more sensors that are configured to sense environmental conditions. For example, such sensors can include one or more of (i) a chemical sensitive detector that is configured to detect the presence of hazardous chemicals, (ii) a gas sensitive detector that is configured to detect the presence of hazardous gases, (iii) a temperature sensor that is configured to detect high temperatures indicative of, e.g., a fire, (iv) a piezoelectric detector that is configured to detect large vibrations associated with, e.g., explosions, earthquakes, etc., (v) a humidity sensor or water sensor that is configured to detect floods or damp conditions, and other types of sensors that are configured to detect for the presence or occurrence of hazardous environmental conditions that would warrant power interruption to the load  20 . 
     In some embodiments, the control signal  318 - s  comprises ambient light that is sensed by the second control switch  318  which operates as a light sensor when implemented as a phototransistor. In this instance, the solid-state power interrupter  300  can be a component of an electrical light switch device such that when the intensity of the ambient light (e.g., intensity of the optical signal  318 - 3 ) reaches a certain level, the second control switch  318  is activated to turn off the first and second solid-state switches  102  and  104  an interrupt power that is delivered to a lighting element. 
     The optical coupling between second control switch  318  and the external control system which control the generation of the control signal  318 - s  essentially provides galvanic isolation between the solid-state power interrupter  300  and the external control system. In other embodiments, galvanic isolation can be implemented using magnetic, capacitive, or radio frequency (RF) isolation technologies. 
       FIG.  4    schematically illustrates a solid-state power interrupter according to another exemplary embodiment of the disclosure. In particular,  FIG.  4    schematically illustrates a solid-state power interrupter  400  which is similar to the solid-state power interrupter  300  of  FIG.  3   , except the solid-state power interrupter  400  comprises the second solid-state switch  104  serially connected in the neutral line path between the line neutral terminal  100 B and the load neutral terminal  100 D of the solid-state interrupter  400  (similar to the exemplary embodiment of  FIG.  1   ). In addition, the solid-state power interrupter  400  comprises control circuitry  410  which is similar to the control circuitry  310  of the solid-state power interrupter  300  of  FIG.  3   , except that the control circuitry  410  further comprises an additional resistor  428 , Zener diode  430 , and capacitor  432  to implement a separate self-biasing driver circuit that is configured to utilize AC power from the AC mains  10  to generate a regulated DC voltage (e.g., turn-on threshold voltage) at an internal node N 4  to drive the gate terminal of second solid-state switch  104 . 
     Similar to the operation of the control circuitry  310  of  FIG.  3   , during a negative half cycle of the AC supply voltage waveform of the AC mains  10 , the second diode  322  is activated, and current flows from the line neutral  12  to the line hot  11  through the second diode  322 , the second resistor  326 , the capacitor  332 , and the body diode  102 - 1  of the first solid-state switch  102 . This current flow causes a voltage across the capacitor  332  to increase until the capacitor voltage reaches the Zener voltage of the Zener diode  330 , whereby the Zener diode  330  serves as a solid-state clamp to limit the level of the regulated DC voltage that is maintained on the internal node N 1  to drive the first solid-state switch  102 . 
     On the other hand, during a positive half cycle of AC supply voltage waveform of the AC mains  10 , the first diode  320  is activated, and current flows from the line hot  11  to the line neutral  12  through the first diode  320 , the first resistor  324 , the capacitor  432 , and the body diode  104 - 1  of the second solid-state switch  104 . This current flow causes a voltage across the capacitor  432  to increase until the capacitor voltage reaches the Zener voltage of the Zener diode  430 , whereby the Zener diode  430  serves as a solid-state clamp to limit the level of the regulated DC voltage that is maintained on the internal node N 4  to drive the second solid-state switch  104 . 
     Furthermore, while not specifically shown in  FIG.  4   , a second fault detection circuit block and a second forced turn-off control circuit block (which comprise the same components, circuit connections, and functionalities as the current sense resistor  312 , the operational amplifier  314 , and the first and second control switches  316  and  318 ) can be implemented on the neutral line path to provide a separate fault detection block for sensing load current flowing on the neutral line path, and to implement a forced turn-off control of the second solid-state switch  104 , using the same techniques as discussed above in conjunction with  FIG.  3   . 
       FIG.  5    schematically illustrates a solid-state power interrupter according to another exemplary embodiment of the disclosure. In particular,  FIG.  5    schematically illustrates a solid-state power interrupter  500  which is similar to the solid-state power interrupter  400  of  FIG.  4   , except that the solid-state power interrupter  500  implements a different circuit configuration of the fault detection circuitry. In particular, as schematically illustrated in  FIG.  5   , the fault detection circuitry comprises a current sense resistor  512  and the first control switch  316 , which are configured to (i) sense an amount of load current flowing in the hot line path through the solid-state interrupter  100 , (ii) detect an occurrence of a fault condition, such as short-circuit fault, an over-current fault, etc., based on the sensed current level, and (iii) in response to detecting a fault condition, shunt the control input of the first solid-state switch  102  to thereby deactivate the first solid-state switch  102  and interrupt power to the load  20 . 
     As schematically illustrated in  FIG.  5   , the sense resistor  512  is connected between nodes N 2  and N 3 . In addition, the base terminal of the first control switch  316  (BJT device) is connected to the node N 2 , and the emitter terminal of the first control switch  316  is connected to the node N 3 . In this configuration, during operation, the sense resistor  512  generates a burden voltage or sense voltage as a result of load current flowing in the hot line path through the sense resistor  512 . When the sense voltage is high enough (e.g., base-emitter voltage VBE is about 0.7 V), the first control switch  316  will turn on, which shunts the gate and source terminal of the first solid-state switch  102 , and thereby causes the first solid-state switch  102  to turn off and interrupt power to the load  20 . 
     In some embodiments, the sense resistor  512  has a resistance value that is selected for a target load current limit (e.g., 100 amperes) to ensure that the first control switch  316  is activated when the magnitude of the load current that flows through the sense resistor  512  reaches or exceeds the target load current limit. For example, assuming that the first control switch  316  is activated when the base-emitter voltage VBE reaches 0.7 V, and assuming that the load current limit is selected to be 100 amperes, the sense resistor would have a resistance of 0.007 ohms (i.e., V=IR, where 0.7 V=100 A×0.007 ohms). 
     Furthermore, while not specifically shown in  FIG.  5   , a second fault detection circuit block and a second forced turn-off control circuit block (which comprise the same components, circuit connections, and functionalities as the current sense resistor  512 , and the first and second control switches  316  and  318 ) can be implemented on the neutral line path to provide a separate fault detection block for sensing load current flowing on the neutral line path, and to implement a forced turn-off control of the second solid-state switch  104 , using the same techniques as discussed above. 
     As further shown in  FIG.  5   , the solid-state power interrupter  500  further comprises isolation circuitry  520 , which is connected across the load hot terminal  100 C and the load neutral terminal  100 D, to provide galvanic isolation between the solid-state power interrupter  500  and the load  20  when the solid-state switches  102  and  104  are turned off. In some embodiments, the isolation circuitry  520  implements the isolation circuitry  210  shown in  FIG.  2   . It is to be understood that the isolation circuitry  210  of  FIG.  2    can be implemented in the exemplary embodiments of the solid-state power interrupters  300  and  400  shown in  FIGS.  3  and  4   . 
       FIG.  6    schematically illustrates an AC-to-DC converter and regulator circuit according to an embodiment of the disclosure. In particular,  FIG.  6    schematically illustrates an AC-to-DC converter and regulator circuit  600  which has a circuit framework that is based on the self-biasing driver circuitry of the solid-state power interrupter  500  of  FIG.  5   . The AC-to-DC converter and regulator circuit  600  is configured to utilize AC power from the AC mains  10  to generate two regulated DC voltages V DC1  and V DC2  at nodes N 1  and N 2 , respectively. In  FIG.  5   , the regulated DC voltages V DC1  and V DC2  are utilized to drive the gate terminals of the respective first and second solid-state switches  102  and  104 . However, the AC-to-DC converter and regulator circuit  600  can be implemented in other applications to generate regulated DC voltages from AC power. 
     As shown in  FIG.  6   , the AC-to-DC converter and regulator circuit  600  comprises discrete diodes  602  and  604 , which correspond to the parasitic body diodes  102 - 1  and  104 - 1 , respectively, in  FIG.  5   . The AC-to-DC converter and regulator circuit  600  further comprises a first clamping circuit block comprising a first Zener diode  610  and a first capacitor  612  connected to the first node N 1 , and a second clamping circuit block comprising a second Zener diode  614  and a second capacitor  616  connected to the second node N 2 . The AC-to-DC converter and regulator circuit  600  further comprises a diode  620  and resistor  622  serially connected between an AC line input terminal  600 A and the second node N 2 , and a diode  624  and resistor  626  serially connected between an AC neutral line input terminal  600 B and the first node N 1 . 
     During a negative half cycle of an AC supply voltage waveform of the AC mains  10 , the diodes  624  and  602  are activated, and current flows from the line neutral  12  to the line hot  11  through the diode  624 , the resistor  626 , the first capacitor  612 , and the diode  602 . This current flow causes a voltage across the first capacitor  612  to increase until the capacitor voltage reaches a Zener voltage of the first Zener diode  610 . In this regard, the first Zener diode  610  serves as a solid-state clamp to limit the level of the regulated DC voltage V DC1  that is maintained on the first node N 1 . On the other hand, during a positive half cycle of AC supply voltage waveform of the AC mains  10 , the diodes  620  and  604  are activated, and current flows from the line hot  11  to the line neutral  12  through the diode  620 , the resistor  622 , the second capacitor  616 , and the diode  604 . This current flow causes a voltage across the second capacitor  616  to increase until the capacitor voltage reaches the Zener voltage of the second Zener diode  614 . In this regard, the second Zener diode  614  serves as a solid-state clamp to limit the level of the regulated DC voltage V DC2  that is maintained on the second node N 2 . 
     Exemplary embodiments of the disclosure as shown in  FIGS.  1 ,  2 ,  3 ,  4 , and  5    include novel architectures for solid-state power interrupter devices that can be disposed between an input energy source and an output load. While the exemplary solid-state power interrupters are generically depicted as connecting the AC mains  10  to a load  20 , it is to be understood that the exemplary power interrupters can be embodied in various devices and applications. For example, in some embodiments, the power interrupters shown in  FIGS.  1 - 5    can be implemented in an electrical circuit breaker device (e.g., intelligent circuit breaker device), which is disposed in a circuit breaker distribution panel. In addition, in some embodiments, the power interrupters shown in  FIGS.  1 - 5    can be implemented in an electrical receptacle device, or an electrical light switch (e.g., a wall-mounted light switch or a light switch implemented in a smart light fixture or smart ceiling light bulb socket, etc.). In other embodiments, the power interrupters shown in  FIGS.  1 - 5    may comprise standalone devices that can be disposed within a gang box in an electrical network of a home or building and configured to protect one or more electrical devices, appliances, loads, etc., that are connected in a branch circuit downstream of the standalone power interrupter device. 
     Although exemplary embodiments have been described herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.