Patent Publication Number: US-8970310-B2

Title: Monolithic band switched coupled push-push oscillator

Description:
BACKGROUND 
     1. Field of the Invention 
     Embodiments of the invention generally relate to electronics, and in particular, to voltage-controlled oscillators. 
     2. Description of the Related Technology 
     Voltage-controlled oscillators (including digitally-controlled oscillators) are widely used in electronic and communication applications, such as clock generation and distribution, carrier synthesis, and data-recovery. Voltage-controlled oscillators can include an oscillator core that generates an oscillating output signal and a resonator or LC tank that presents the oscillator core an electrical characteristic such a capacitance and inductance that causes the oscillatory response. The frequency of oscillation depends at least partly on the value of the electrical characteristics. Accordingly, voltage-controlled oscillators have LC tanks with variable electrical characteristics, thereby providing a way to control the frequency of oscillation of the output signal by adjusting or tuning the variable electrical characteristics. 
     Push-push oscillators are used in many applications due to their tunable bandwidth, low noise, and low frequency pulling. Push-push oscillators may also increase tuning frequency by a factor of two. Such an oscillator represents a balanced circuit, in which two bipolar junction transistors (BJTs) provide opposite phase oscillations at the fundamental frequency and odd harmonics and in-phase oscillations at even harmonics. Push-push oscillators can be coupled with a diode-based varactor for tuning of the frequency of oscillations. 
     SUMMARY 
     Various embodiments of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, some prominent features are described herein. After considering this discussion, and particularly after reading the section titled “Detailed Description” one will understand how the features of various embodiments are used to configure tunable oscillators that can be implemented on a monolithic integrated circuit die or chip, and achieves low phase noise, large swing voltage, band switching, and/or high frequency performance. 
     Prior art monolithic push-push oscillators designs are primarily limited to varactor-only tuning, which achieves relatively narrow-band tuning. Although wider-band tuning can be achieved by switching among several push-push oscillator IC dies or chips, such a system, however, does not provide a push-push oscillator with wide-band tuning on a single monolithic IC chip. Moreover, these prior art designs are largely unsatisfactory for many wide-band, high-frequency, and/or high-voltage applications. 
     In one embodiment, an apparatus having improved noise performance and wide-tuning-frequency and/or high-voltage capabilities is disclosed. The apparatus comprises a monolithic integrated circuit, an oscillator core of the monolithic integrated circuit, and one or more tuning units of the monolithic integrated circuit. The oscillator core includes a first oscillator configured to generate a first oscillating signal, the first oscillator having a transistor of a first structural type. The oscillator core further includes a second oscillator coupled to the first oscillator and configured to generate a second oscillating signal in anti-phase with the first oscillating signal at a fundamental harmonic and in phase with the first oscillating signal at even harmonics. The one or more tuning units of the monolithic integrated circuit are configured to present the oscillator core with a selectable electrical characteristic, wherein the one or more tuning units have one or more switching electrical devices of a second structural type that is different from the first structural type. The fundamental harmonic is based at least partly on the selected electrical characteristic presented by the one or more tuning units. 
     In another embodiment, the first oscillator and second oscillator of the oscillator core are in a push-push oscillator configuration. The first structural type can comprise a bipolar-junction-transistor structural type, and the second structural type can comprises a field-effect-transistor structural type. The first oscillator can have the transistor in a common collector configuration. The apparatus can further comprise a voltage-controlled capacitor operatively coupled to the oscillator core, the voltage-controlled capacitor having an adjustable capacitance. The fundamental harmonic can based at least partly on the selected electrical characteristic presented by the one or more tuning units and on the capacitance of the variable capacitor. The oscillator core can be configured to generate a third oscillating signal that has a frequency substantially twice the frequency of the fundamental harmonic. The selectable electrical characteristic can comprise a capacitance. 
     In another embodiment, the apparatus can comprise a control unit operatively coupled to the oscillator core and to the one or more tuning units, wherein the control unit is configured to adjust the selectable electrical characteristic to match one of the harmonics of the first oscillating signal to a reference frequency. 
     In some embodiment, at least one of the one or more tuning units is configured to selectively connect a capacitor to the oscillator core, the second structural type comprises a field-effect-transistor structural type, and the electrical characteristic comprises the capacitance of the capacitor connected to the oscillator. In some embodiments, at least one of the one or more tuning units is configured to selectively connect a capacitor to the oscillator core, the second structural type comprises a MEMS-switch structural type, and the electrical characteristic comprises the capacitance of the capacitor connected to the oscillator. 
     In some embodiments, at least one of the tuning units has a stack of two or more switching electrical devices, the stack being configured to selectively present the electrical characteristic associated with the at least one of the tuning units to the oscillator core. The monolithic integrated circuit can be provided a supply voltage, the two or more switching electrical devices of the stack can be field effect transistors, and the stack of the two or more field effect transistors can have an aggregate breakdown voltage greater than twice the supply voltage. 
     In yet another embodiment, a method for controlling oscillating electrical signals is disclosed. The method comprises generating a first oscillating electrical signal with a first circuit, the first circuit comprising a transistor of a first structural type. The method also comprises generating a second oscillating electrical signal with a second circuit that is coupled with the first circuit, the second oscillating electrical signal being in anti-phase with the first oscillating electrical signal at a fundamental harmonic and in phase with the first oscillating electrical signal at even harmonics. The method further comprises selectively changing an electrical characteristic of a third circuit coupled to at least one of the first circuit or the second circuit to control the fundamental harmonic. The third circuit comprises an electrical device of a second structural type that is different from the first structural type. The first circuit and second circuit can be in a push-push configuration, the first structural type can be a bipolar-junction-transistor structural type, and the second structural type can be a field-effect-transistor structural type. The push-push configuration of the first circuit and second circuit can be further configured to generate a third oscillating electrical signal having a frequency substantially twice the frequency of the fundamental harmonic. The method can further comprise selectively changing the electrical characteristic of the third circuit to perform a coarse frequency adjustment and controlling a control voltage to a varactor to perform a fine frequency adjustment. 
     In yet another embodiment, an apparatus is disclosed that comprises a monolithic integrated circuit, an oscillator core of the monolithic integrated circuit, and a means for adjusting a frequency of the fundamental harmonic. The oscillator core comprises a first oscillator configured to generate a first oscillating signal, the first oscillator having a transistor of a first structural type. The oscillator core further comprises a second oscillator coupled to the first oscillator and configured to generate a second oscillating signal in anti-phase with the first oscillating signal at a fundamental harmonic and in phase with the first oscillating signal at even harmonics. The adjusting means comprises an electrical device of a second structural type that is different from the first structural type. The first oscillator and second oscillator can be configured as a push-push oscillator, the first structural type is a bipolar-junction-transistor structural type, and the second structural type is a field-effect-transistor structural type. The oscillator core can be configured to generate a third oscillating signal, the third oscillating signal having a frequency substantially twice the frequency of a signal that is the difference between the first oscillating electrical signal and the second oscillating electrical signal. The electrical device of the means for adjusting the frequency of the fundamental harmonic can include a stack of two or more field effect transistors having deep trench isolation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These drawings and the associated description herein are provided to illustrate specific embodiments of the invention and are not intended to be limiting. 
         FIGS. 1   a  and  1   b  depict block diagrams of exemplary monolithic tunable oscillators including an oscillator core and one or more tuning units according to various illustrative embodiments of the invention. 
         FIGS. 2   a  and  2   b  illustrate various embodiments of the oscillator core of  FIGS. 1   a  and  1   b.    
         FIG. 3  illustrates an embodiment of one of the tunable units of  FIGS. 1   a  and  1   b.    
         FIG. 4  depicts a block diagram of an illustrative PLL circuit including the monolithic tunable oscillator of  FIGS. 1   a  and  1   b , as well as a control unit and a sensing circuit. 
         FIG. 5  depicts a block diagram of the control unit of  FIG. 4  according to an embodiment. 
         FIG. 6  shows a block diagram of the sensing unit of  FIG. 4  according to an embodiment. 
         FIG. 7   a  is an illustrative flow diagram of an example method for generating an oscillating signal. 
         FIG. 7   b  is an illustrative flow diagram of an example method for generating an oscillating signal in accordance with certain requirements. 
         FIG. 8  is an illustrative flow diagram of an example method for coarse and fine tuning the tuning units of  FIGS. 2   a  and  2   b  according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The various embodiments of systems, methods, and devices described herein each have several aspects, no single one of which is solely responsible for the desirable attributes described. Without limiting the scope of the claims, the more prominent features of various embodiments are described below. After considering the following one skilled in the art will understand how the features of the various embodiments provide advantages over previously available tunable oscillators. 
     Embodiments of the invention include, but are not limited to, monolithic oscillators with low-phase-noise and wide-tuning characteristics; monolithic oscillators with low-phase-noise and large-swing-voltage capabilities; and monolithic oscillators with low-phase-noise and high-frequency capabilities. 
       FIG. 1   a  depicts a block diagram of an exemplary monolithic tunable oscillator  100   a  including a monolithic integrated circuit (IC) die or chip  102 , an oscillator core  104 , an impedance Z(s)  106 , and one or more tuning units  108 ( 1 ), . . . ,  108 ( n ), according to various illustrative embodiments of the invention. The tuning units  108 ( 1 ), . . . ,  108 ( n ) are not conventional varactor circuits. 
     The oscillator core  104  is operatively coupled to the impedance Z(s)  106  and to the n tuning units  108 ( 1 ), . . . ,  108 ( n ) across nodes X and X′. As will be explained in further detail later in connection with  FIG. 2 , the oscillator core  104  uses a transistor  110  to generate an oscillating signal V O , and optionally a signal V 2F  that oscillates at twice the frequency of the oscillating signal V O . The frequency of oscillation of the oscillating signal V O  depends on the electrical characteristics of a resonator or LC tank formed by the impedance Z(s)  106  and the tuning units  108 ( 1 ), . . . ,  108 ( n ). The tuning units  108 ( 1 ), . . . ,  108 ( n ) use electrical devices  112 ( 1 ), . . . ,  112 ( n ), respectively, to adjust the electrical characteristics presented to the oscillator core  104  across nodes X and X′. The voltage across X and X′ is called the LC tank voltage. Based on their relationship with the oscillating signal V O , the tuning units  108 ( 1 ), . . . ,  108 ( n ) are ways of adjusting the frequency of the output of the oscillator core  104 . The transistor  110  should have a structural type that is different from the structural type of the electrical devices  112 ( 1 ), . . . ,  112 ( n ), as discussed below. 
     The oscillator core  104  can comprise a first oscillator operatively coupled with a second oscillator. The first oscillator can be configured to generate a first oscillating signal, and the second oscillator can be configured to generate a second oscillating signal. The first oscillator and the second oscillator are in anti-phase at a fundamental harmonic and odd harmonics and in phase at even harmonics. Thus, if the first and second oscillating signals are treated as a differential signal and are converted to a single ended signal V O , the resulting signal V O  is composed of the fundamental and odd harmonics, where the even harmonics and common mode noise have been suppressed. 
     In one embodiment of the invention, the monolithic IC chip  102  may be fabricated according to GaAs BiFet and/or SiGe Based BiCMOS silicon process technologies. In some embodiments, the monolithic IC chip  102  may be fabricated with a fully isolated thick silicon-on-insulator (SOI) CBiCMOS process with a high resistivity handle wafer to enable high Q factor passive components; deep trench isolated FET devices for enabling high performance FET switching devices (as discussed in connection with  FIG. 3 ); and/or dual thick metal back-end that includes copper for enabling high Q inductors. 
     In operation, the monolithic IC chip  102  receives a control signal V C , which can include a set of n control signals V C1 , . . . , V Cn  that control the electrical characteristics of the tuning units  108 ( 1 ), . . . ,  108 ( n ), respectively. Accordingly, the control signal V C  can control the frequency of oscillation of the oscillating signal V O . While  FIG. 1   a  shows the control signal V C  as being exogenous to the monolithic IC chip  102 , in an alternative embodiment, the control signal V C  is generated internally. 
     While  FIG. 1   a  shows the oscillating signals V O  and V 2F  as being outputs of the monolithic IC chip  102 , in an alternative embodiment, the oscillating signals V O  and V 2F  are internal signals of the monolithic IC chip  102 . In the example shown in  FIG. 1   a , the oscillating signals V O  and V 2F  are voltage signals. In another embodiment, the oscillating signals V O  and V 2F  can be current signals. 
     As described above, the oscillator core  104  uses the transistor  110  to generate the oscillating signal V O . The transistor  110  can have various structural types, including, but not limited to, BJT, JFET, MOSFET, IGFET, MESFET, pHEMT, HBT, and the like transistor structural types. The transistor  110  can also have various polarities, such as N-type, P-type, NPN-type, or PNP-type; and can include various semiconductor materials, such as GaAs, SiGe, and the like. 
     As stated, the LC tank includes the impedance Z(s)  106 , which is operatively coupled to the oscillator core  104 . The impedance Z(s)  106  presents the oscillator core  104  with an electrical characteristic that can be an inductance, capacitance, resistance, or a combination thereof. The impedance Z(s)  106  can be, for example, a metal-insulator-metal capacitor (MIMCap) and/or a spiral inductor implemented on the monolithic IC chip  102 . In one embodiment, the impedance Z(s)  106  is substantially fixed (for example, substantially time invariant). In another embodiment, the impedance Z(s)  106  can have a time varying component.  FIG. 1   a  shows impedance Z(s)  106  as being separate from the oscillator core  104 . In other embodiments, the impedance Z(s) can be included as a subcomponent of the oscillator core  104  or separate from the monolithic tunable oscillator  100   a.    
     As a tunable part of the resonator or LC tank, each of the tuning units  108 ( 1 ), . . . ,  108 ( n ) presents the oscillator core  104  with a variable or selectable electrical characteristic across nodes X and X′. The variable or selectable electrical characteristic can be a capacitance, inductance, resistance, or a combination thereof. As depicted in  FIG. 1   a , the tuning units  108 ( 1 ), . . . ,  108 ( n ) are organized in a one dimensional array. Another embodiment of the monolithic tunable oscillator  100   a  includes a multidimensional array (not shown) of tuning units. 
     The functionality of the tuning unit  108 ( n ) described herein can be distributed among any number of circuits. For example, in some embodiments, the tuning unit  108 ( n ) can comprise a circuit that is coupled with the first oscillator and the second oscillator of the oscillator core  104 . The circuit can present an electrical characteristic (for example, a capacitance) across nodes X and X′ to both the first oscillator and the second oscillator, thereby tuning or changing the fundamental harmonic. For another example, in some embodiments, the tuning unit  108 ( n ) can comprise one or more circuits that are coupled with at least one of the first oscillator or the second oscillator of the oscillator core  104 . For yet another example, in some embodiments, the tuning unit  108 ( n ) can comprise a first single-ended circuit and a second single-ended circuit. The first single-ended circuit is coupled to the first oscillator at, for example, node X. The first single-ended circuit can present the first oscillator an electrical characteristic across node X and ground. Similarly, the second single-ended circuit is coupled with the second oscillator at, for example, node X′. The second single-ended circuit can present the second oscillator an electrical characteristic across node X′ and ground. An example of such a single-ended circuit can be a switched capacitor similar to the tuning unit  108 ( n ) shown in  FIG. 3  but with one of the X or X′ nodes being ground instead of node X or X′. Thus, in combination, the first single-ended circuit and the second single-ended circuit present an electrical characteristic at nodes X and X′. Furthermore, in some embodiments a separate LC tank, not just a separate tuning unit  108 ( n ), can be coupled independently to each of the first oscillator and the second oscillator in a similar manner where the electrical characteristic is presented across the corresponding X node or X′ node to ground. 
     In operation, the tuning unit  108 ( n ) adjusts its electrical characteristic in accordance with its corresponding control signal V Cn . For example, the control signal V Cn  can be a switching signal that switches on or off the selectable electrical characteristics of the tuning unit  108 ( n ). In another embodiment, the control signal V Cn  variably adjusts the electrical characteristic of the tuning unit  108 ( n ) in a continuous manner. 
     In accordance with the control signal V Cn , the tuning unit  108 ( n ) uses the electrical device  112 ( n ) to adjust the variable or selectable electrical characteristic thereof presented to the oscillator core  104  across nodes X and X′. The electrical device  112 ( n ) should have a structural type that is different from the structural type of the transistor  110 . Examples of the structural type of the electrical device  112 ( n ) include, but are not limited to, BJT, JFET, MOSFET, IGFET, MESFET, pHEMT, HBT, MEMS-based switches, and the like structural types. The electrical device  112 ( n ) can also have various polarities, such as N-type, P-type, NPN-type, or PNP-type polarities; and can include various semiconductor materials, such as GaAs, SiGe, and the like. In one embodiment, the electrical device  112 ( n ) is a FET-type switch that switches a capacitance presented across nodes X and X′. In one embodiment, electrical device  112 ( n ) is a FET-type amplifier that modulates a capacitance presented across nodes X and X′ in a smooth manner. 
       FIG. 1   b  depicts a block diagram of a monolithic tunable oscillator  100   b  that further comprises a voltage-controlled variable capacitor or varactor  114  according to another embodiment. Elements common to both monolithic tunable oscillators  100   a ,  100   b  share common reference indicia, and only differences between the monolithic tunable oscillators  100   a ,  100   b  are described herein for the sake of brevity. 
     As part of the LC tank, the varactor  114  can present a variable capacitance to the oscillator core  104  across nodes X and X′ in accordance with a corresponding control signal V C(n+1) . In some embodiments, the varactor  114  is a P-N junction varactor with a doping profile that substantially maximizes its on-off capacitance ratio C on /C off  and has a reverse breakdown voltage greater than a maximum voltage of the control signal V C(n+1) . In some embodiments, the maximum voltage of the control signal V C(n+1)  can be approximately 12 volts (V) or greater. 
     In one example, during operation, the tuning units  108 ( 1 ), . . . ,  108 ( n ) can be used for coarse tuning or adjustment of the frequency of the oscillating signal V O , and the varactor  114  may be used for fine tuning or adjustment of the oscillating signal V O . In embodiments in which the tuning units  108 ( 1 ), . . . ,  108 ( n ) comprise switchable capacitances, the applicable individual capacitances of the tuning units  108 ( 1 ), . . . ,  108 ( n ) can vary in a very broad range, and can be higher or lower relative to the maximum achievable capacitance of the varactor  114 . Applicable values will be readily determined by one of ordinary skill in the art. 
     In some embodiments, where tuning units  108 ( 1 ), . . . ,  108 ( n ) can switch on and off, the frequency range of the oscillating signal V O  depends on the ratio C on /C off  of on-off capacitance of switchable tuning units  108 ( 1 ), . . . ,  108 ( n ). The frequency range can also depend on the tuning range of the capacitance of the varactor  114 . Increasing the frequency range of the oscillator, however, can degrade phase noise performance, resulting in a trade-off between frequency tuning range and phase noise performance. In order to mitigate the effects of this trade-off, some embodiments include multiple independent oscillators to extend the overall frequency range. In operation, one of the multiple independent oscillators can be selected based on the desired frequency of the oscillating signal V O . 
       FIG. 2   a  illustrates an embodiment of the oscillator core  104  of  FIGS. 1   a  and  1   b . The oscillator core  104  as shown in  FIG. 2   a  is implemented as a push-push oscillator core and includes NPN BJT transistors Q 1 , Q 2 ; capacitors C 1 , . . . , C 6 , C 9 ; resistors R 1 , R 2 ; and inductors L 1 , L 2 . As shown in  FIG. 2   a , transistors Q 1  and Q 2  are each in common collector configuration. In the illustrated embodiment, the two transistors Q 1 , Q 2  can each correspond to the transistor  110  ( FIGS. 1   a  and  1   b ). 
     A push-push oscillator represents a balanced circuit of two coupled oscillators. The first oscillator (“Q 1  Oscillator”) comprises transistor Q 1  in common collector configuration with resistor R 1 ; capacitors C 1 , C 3 ; and inductor L 1 . The second oscillator (“Q 2  Oscillator”) comprises transistor Q 2  in common collector configuration with resistor R 2 ; capacitors C 2 , C 4 ; and inductor L 2 . The Q 1  Oscillator and Q 1  Oscillator are coupled reactively by the two capacitors C 5 , C 6 , as described below. The two transistors Q 1 , Q 2  generate the differential signals V OP , V ON , respectively. In operation, the differential signals V OP , V ON  have anti-phase oscillations at the fundamental frequency and odd harmonics and in-phase oscillations at even harmonics. As a result, converting the differential signals V OP , V ON  to a single-ended signal—say, V O —can suppress the even harmonics of the Q 1  Oscillator and Q 1  Oscillator. A push-push oscillator can achieve up to a 9 dB improvement in phase noise over conventional oscillators. 
     Accordingly, the oscillating signal V O  of the oscillator core  104  shown in  FIGS. 1   a  and  1   b  can be the single ended output of the differential signals V OP , V ON , wherein the non-inverted signal V OP  is provided by the node at the emitter of the transistor Q 1  and the inverted signal V ON  is provided by the node at the emitter of the transistor Q 2 . 
     As part of a grounding network, the capacitor C 1  can be connected between the collector of the transistor Q 1  and a voltage reference, such as ground. Likewise, the capacitor C 2  can be connected between the collector of the transistor Q 2  and ground. This grounding network can also be a resonant network that provides a low impedance path to ground at either V O  or V 2F . In some embodiments, the values of the capacitances of the capacitors C 1 , C 2  can be approximately 10 picofarads (pF). Other values will be readily determined by one of ordinary skill in the art. 
     As part of an emitter biasing network, the resistor R 1  and the inductor L 1  are connected in series between the emitter of the transistor Q 1  and ground. Likewise, the resistor R 2  and the inductor L 2  are connected in series between the emitter of the transistor Q 2  and ground. In some embodiments, the resistances of the resistors R 1 , R 2  are each approximately 50 ohms (Ω), and the inductances of the inductances L 1 , L 2  are each approximately 2 nanohenries (nH). Other values will be readily determined by one of ordinary skill in the art. 
     The capacitor C 3  is connected between the base of the transistor Q 1  and the node X. Likewise, the capacitor C 4  is connected between the base of the transistor Q 1  and the node X′. In some embodiments, the capacitances of the capacitors C 3 , C 4  are each approximately 1-10 pF. 
     As stated, the Q 1  Oscillator and Q 2  Oscillator are coupled reactively by the two capacitors C 5 , C 6 . The capacitors C 5 , C 6  are connected in series between the emitter of the transistor Q 1  and the emitter of the transistor Q 2 . The capacitor C 9  is connected to the node between the capacitors C 5 , C 6  and to the V 2F  output node. Due to the symmetry of the oscillator core  104 , this node between capacitors C 5 , C 6  can be a virtual ground at which the fundamental harmonics of the Q 1  Oscillator and the Q 2  Oscillator are in anti-phase. As a result, the fundamental harmonic can be suppressed at that node and the second harmonic can be extracted at the V 2F  output node. In some embodiments, the capacitances of the capacitors C 5 , C 6  are each approximately 1-10 pF. In some embodiments, the capacitance of the capacitor C 9  is approximately 1-10 pF. 
     A supply voltage V DD  is connected to the collectors of the transistors Q 1  and Q 2 . In some embodiments, the supply voltage V DD  is approximately 1.8-8 V. Other values will be readily determined by one of ordinary skill in the art. 
     As stated above, the oscillator core  104  shown in  FIG. 2   a  has a push-push topology. Those skilled in the art will appreciate from the disclosure herein that in another embodiment can have a different oscillator topology, including a cross-connected oscillator topology. 
     The oscillator core  104  as shown in  FIG. 2   a  is in a common collector configuration. Other configurations such as common base and common emitter will be readily determined by one of ordinary skill in the art. For example,  FIG. 2   b  is a circuit diagram illustrating oscillator core  104  in accordance with another embodiment that utilizes a common base configuration. Elements common to both  FIG. 2   a  and  FIG. 2   b  share common reference indicia, and only differences between  FIG. 2   a  and  FIG. 2   b  are described herein for the sake of brevity. The oscillator core  104  shown  FIG. 2   b  includes two NPN BJT transistors Q 1b , Q 2b ; resistors R 1b , . . . , R 6b ; capacitors C 1b , . . . , C 7b ; and inductors L 1b , L 2b . Values of these components will be readily determined by one of ordinary skill in the art. 
     As shown in  FIG. 2   b , transistor Q 1b  is in a common base configuration with resistors R 1b , R 3b , and R 5b ; capacitors C 1b  and C 5b ; and inductor L 1b . This portion of the oscillator core  104  forms a first oscillator. Resistor R 1b  has a first end connected with a supply voltage V DD  and a second end connected with the base terminal of the transistor Q 1b . Resistor R 5b  and capacitor C 5b  are connected in parallel between the base of the transistor Q 1b  and ground. Resistor R 3b  and inductor L 1b  are connected in series between the emitter of transistor Q 1b  and ground. Capacitor C 1b  has a first end and a second end that are connected with the collector and emitter of transistor Q 1b , respectively. The collector of Q 1b  is also connected with node X. The emitter of Q 1b  provides the non-inverted signal V OP . 
     Transistor Q 2b  is similarly in a common base configuration, with resistors R 2b , R 4b , and R 6b ; capacitors C 2b  and C 6b ; and inductor L 1b . This portion of the circuit forms a second oscillator. Resistor R 2b  has a first end connected with a supply voltage V DD  and a second end connected with the base terminal of the transistor Q 2b . Resistor R 6b  and capacitor C 6b  are connected in parallel between the base of the transistor Q 2b  and ground. Resistor R 4b  and inductor L 2b  are connected in series between the emitter of transistor Q 2b  and ground. Capacitor C 2b  has a first end and a second end that are connected with the collector and emitter of transistor Q 2b , respectively. The collector of Q 2b  is also connected with node X′. The emitter of Q 2b  provides the inverted output signal V ON . 
     The transistors Q 1b  and Q 2b , and in turn the first and second oscillators, are electrically and/or reactively coupled. As shown in  FIG. 2   b , capacitors C 3b  and C 4b  are connected in series between the emitters of transistors Q 1b  and Q 2b . Additionally, capacitor C 7b  has a first end connected with the node between capacitors C 3b  and C 4b  and a second end that provides the second output signal V 2F . For the same reasons as discussed in connection with the oscillator core  104  of  FIG. 2   a , the output signal V 2F  is primarily the second harmonic signal of the first and second oscillators. The output signal V 2F  is therefore substantially twice the frequency of V O , which is primarily the fundamental harmonic. 
       FIG. 3  illustrates an embodiment of the tuning unit  108 ( n ) of  FIGS. 1   a  and  1   b . The tuning unit  108 ( n ) includes field effect transistors (FETs) M 1 , M 2 ; resistors R 3 , . . . , R 9 ; and capacitors C 7  and C 8 . The FETs M 1  and M 2  are configured as switches in a stacked configuration. In this embodiment, each of the FETs M 1 , M 2  can correspond to the electrical device  112 ( n ) of the oscillator core  104  shown in  FIGS. 1   a  and  1   b . The control signals V Cn,1 , V Cn,2  are complementary control signals that can switch the FETs M 1 , M 2  on or off to realize discrete frequency tuning. These controls are generated from a control unit, as discussed in connection with the illustrative example of  FIGS. 4 ,  5 , and  8 . When the FETs M 1 , M 2  are on, the capacitors C 7 , C 8  are operatively coupled to the oscillator core  104 , thereby increasing the capacitance of the LC tank coupled across nodes X and X′. When the FETs M 1 , M 2  are off, the capacitors C 7 , C 8  are not operatively coupled to the oscillator core  104  and do not contribute capacitance to the resonator tank. According, the switching of the capacitors C 7 , C 8  provides band switching capabilities. In some embodiments, the capacitances of the capacitors C 7 , C 8  are each approximately 25 to 1000 femtofarads (fF), and the sizes of the FETs M 1 , M 2  are each 50 to 1000 square micrometers (μm 2 ) with widths of 5-50 μm. Other values will be readily determined by one of ordinary skill in the art. 
     In some embodiments, an advantage of the tuning unit  108 ( n ) over previous existing tuning units of oscillators is that the tuning unit  108 ( n ) can have high-voltage and high-frequency capabilities. One problem associated with high-voltage and high-frequency oscillators is that the voltage across X and X′ may exceed the breakdown voltage of one transistor. Thus, switches or tuning units having only one transistor as a switch may not be practical. However, using more than one transistor in a switch or tuning unit may increase the amount of RF interference on the control signal lines V Cn , where the source of the RF interference is the high-frequency voltage oscillations across nodes X and X′. The increase in RF interference on the control lines is caused by the additional parasitic capacitance the control line V Cn  sees due to additional transistors. For example, with reference to  FIG. 3 , the two FETs M 1  and M 2  have parasitic capacitances C GS1 , C GD1 , C GS2 , and C GD2  (all parasitic capacitances not shown) that couple the X or X′ nodes with the control line V CN,2  Furthermore, using more than one transistor may increase the overall parasitic on-resistance r 0  (not shown) when the transistor are on, resulting in increased power loss. 
     Despite these obstacles, the tuning unit  108 ( n ) can provide switching and/or tuning capabilities for high-voltage and high-frequency oscillators. For these applications, it can be advantageous to arrange the FETs M 1 , M 1  by stacking them as shown in  FIG. 3  so that the voltage across X and X′ is spread across the two FETs M 1 , M 1 . For example, consider that the case where the FETs M 1 , M 1  individually have breakdown voltages of approximately 1.8 to 3 V. The FETs M 1 , M 2  arranged as shown in  FIG. 3  can thereby operate with resonator or tank voltages substantially greater than 3V. 
     Additionally, various features of the tuning unit  108 ( n ), individually or in combination, can mitigate some of the above-stated disadvantages of using multiple transistors for tuning high-voltage and high-frequency oscillators. The resistors R 3 , . . . , R 7  can act as RF blocks that can attenuate the parasitic leakage of RF signals (due to the high frequency operation of the oscillator core  104 ) of nodes X and X′ to the control lines that carry the control signal V Cn . These resistors R 3 , . . . , R 7  can additionally or alternatively act as DC-bias feeds to the gates of the FETs M 1 , M 2 . In some embodiments, the resistances of R 3 , . . . , R 7  are each approximately 5 to 50 kΩ. Other values will be readily determined by one of ordinary skill in the art. 
     Further, in some embodiments, the resistor R 8  is connected between the body of the FET M 1  and ground. Similarly, the resistor R 9  is connected between the body of the FET M 2  and ground. This network can be implemented on an SOI process with deep trench isolation that allows the resistors R 8 , R 9  to be tied to ground in a practical manner. As so configured, the network can block RF signals because R 8 , R 9  behave as high impedances to RF signals. Further, this network can also reduce power losses associated with transistor stacking by reducing the capacitances the FETs M 1 , M 1  see looking to ground. Further yet, the network can improve the linearity of the switch. In some embodiments, the resistances of the resistors R 8 , R 9  are each approximately 5 to 50 kΩ. Other values will be readily determined by one of ordinary skill in the art. 
       FIG. 4  depicts a block diagram of an exemplary PLL circuit  400  including the monolithic tunable oscillator  100  of  FIGS. 1   a  and  1   b , as well as a control unit  402  and an optional sensing circuit  404 . The PLL circuit  400  receives a reference signal V R  as an input and generates the oscillating signal V O  such that the oscillating signal V O  tracks the (optionally divided) frequency and phase of the reference signal V R . The control unit  402  receives as inputs the reference signal V R  and the feedback signal V FB , which is generated by the sensing circuit  404 . As explained below in connection with  FIG. 5 , the feedback signal V FB  is a processed version of the oscillating signal V O . As shown, the control unit  402  provides the control signal V C  to the tuning units  108 ( 1 ), . . . ,  108 ( n ) for control of the phase and/or frequency of the oscillating signal V O . As stated, in some embodiments, the control signal V C  comprises the signals V C1 , . . . , V Cn  as shown, for example, in  FIG. 1   a . In some embodiments, V C  comprises V C1 , . . . , V Cn , V C(n+1)  as shown in  FIG. 1   b . In some embodiments, the sensing circuit receives auxiliary signal(s) and the control signal V C . Generally, the auxiliary signal(s) can be any internal or external signal(s) of the control unit  402  that the sensing circuit  404  may use. 
       FIG. 5  illustrates further details of the control unit  402  of  FIG. 4  according to an embodiment. The control unit  402  includes an R-counter  502 , phase-frequency detector  504 , charge pump  506 , loop filter  508 , one-shot circuit  510 , frequency comparator  512 , and control logic unit  514 . The control unit  402  receives the reference signal V R  and the feedback signal V FB  as inputs, and generates the control signal V C  and auxiliary signals as outputs. In some embodiments, the control signal V C  controls fine and/or coarse adjustment of the frequency of the oscillating signal V O . For example, the control signals V C1 , . . . , V Cn  associated with the tuning units  108 ( 1 ), . . . ,  108 ( n ) can control coarse adjustments, and the control signal V C(n+1)  associated with the varactor  114  can control fine adjustments. As shown in  FIG. 4 , the control signals V C1 , . . . , V Cn  can be generated by the lower path comprising the one-shot circuit  510 , frequency comparator  512 , and control logic unit  514 . This path also provides the logical control signals “FINE” and “COARSE,” which are used to signal either fine or coarse adjustment mode. The control signal V C(n+1)  is generated by the upper path comprising the phase frequency detector  504 , charge pump  506 , and loop filter  508 . 
     Because it can be difficult to produce a reliable reference signal having many practical target frequency ranges, a stable, highly-reliable oscillator (not shown) can be used to generate the reference signal V R  at a frequency higher than the target frequency, and a frequency divider can be used to generate an internal reference signal having the target frequency. For example, in the embodiment illustrated in  FIG. 5 , the R-counter  502  performs frequency division. In one embodiment, the R-counter  502  can be a down counter initialized with R cycles. Alternatively, an up counter can be used. The R-counter  502  receives the high frequency reference signal V R  as an input and generates a reduced frequency signal F R  as an output. In one embodiment, the R-counter  502  operates as follows. The reference signal V R  accordingly decrements the R-counter  502  for every cycle of the reference signal V R . The reduced frequency signal F R  output of the R-counter  502  remains set as logic high as the R-counter  502  is counting down. When the R-counter  502  times out after R cycles of the reference signal V R , the R-counter  502  sets the reduced frequency signal F R  to logic low. Because the reduced frequency signal F R  is fed back to the “load” port of the R-counter  502 , timing out causes the R-counter  502  to reset its count to R cycles on the next cycle. 
     To generate the control signal V C(n+1)  for fine tuning, the phase frequency detector  504  receives the reduced frequency signal F R  and the feedback signal V FB  as inputs and provides the charge pump  506  an error signal E PF  that represents a measure of the phase error and/or frequency error between the reduced frequency signal F R  and the feedback signal V FB . The charge pump  506  receives the error signal E PF  as an input and provides the loop filter  508  with a charge pump error signal E CP . If the fine control signal is set logic high, the loop filter  508 , being an analog or digital filter, processes the charge pump error signal E CP  and generates the control signal V C(n+1) . In some embodiments, the loop filter  508  has a gain and a bandwidth selected to meet stability and bandwidth requirements. As stated above, in some embodiments the control signal V C(n+1)  adjusts the capacitance of the varactor  114  to provide fine tuning adjustments of the frequency of the oscillating signal V O . If the control signal FINE is set logic low, the loop filter  508  generates a constant control signal V C(n+1)  during coarse tuning. For example, in some embodiments a logic low FINE and a logic high COARSE cause the loop filter  508  to switch its output V C(n+1)  to a constant power supply (not shown), thereby producing a constant control signal V C(n+1) . 
     To generate the control signals V C1 , . . . , V Cn  for coarse tuning, the one-shot circuit  510  receives the reduced frequency signal F R  as an input and provides the frequency comparator  512  a pulse F RP . The frequency comparator  512  provides the control logic unit  514  with a frequency error signal E F  that indicates an approximate measure of the mismatch between frequencies of the reduced frequency signal F R  and the feedback signal V FB . The control logic unit  514  receives E F  as input and provides the control signals FINE and COARSE, as well as the control signals V C1 , . . . , V Cn . As stated, in some embodiments the control signals V C1 , . . . , V Cn  switch the n tuning units  108 ( 1 ), . . . ,  108 ( n ) on or off to provide coarse tuning and/or band switching. The control logic unit  514  may include a successive approximation register (SAR) (not shown) for performing a binary search through the possible quantization levels of the tuning unit control signals V C1 , . . . , V Cn . An exemplary method for generating the control signals FINE, COARSE, and V C1 , . . . , V Cn , V C(n+1)  is discussed further in connection with  FIGS. 7 and 8 . 
       FIG. 6  shows a block diagram of the optional sensing circuit  404  of  FIG. 4  according to an embodiment. The sensing circuit  404  includes a dual modulus prescaler  602 , A-counter  604 , B-counter  606 , and switches  608 ,  610 . The sensing circuit can be a digital and/or analog circuitry configured to frequency divide the oscillating signal V O . A dual modulus prescaler scheme comprising the dual modulus prescaler  602 , A-counter  604 , and B-counter  606  as shown in  FIG. 6  may improve output resolution for high frequency signals. 
     In operation, the oscillating signal V O  triggers the dual modulus prescaler  602 , which counts down from either P+1 or P according to the output F A  of the A-counter  604 . When the A-counter  604  is counting, its output F A  is set logic high and causes the dual modulus prescaler  602  count down from an initial count of P+1. When the A-counter  604  times out, its output F A  is set logic low and causes dual modulus prescaler  602  to count down from P. The A-counter  604  and B-counter  606  are down counters that are decremented by the output F P  of the dual modulus prescaler  602 . An initial count B of the B-counter  606  is greater than or equal to an initial count A of the A-counter  604  (for example, B≧A). Accordingly, after the A-counter  604  times out and causes the dual modulus prescaler  602  timer to be set at P, the B-counter  606  is decremented every P cycles of the oscillating signal V O . As a result, the B-counter  606  times out after A+PB cycles of the oscillating signal V O . 
     The load inputs of the A-counter  604  and the B-counter  606  cause the timer of each counter to be reset to an initial state. As shown in  FIG. 6 , the load input can either be the feedback signal V FB  or the reduced frequency signal F R , depending on whether the PLL  400  is in fine adjustment mode or in coarse adjustment mode. In fine adjustment mode, the switch  608  is open and the switch  610  is closed, so that the feedback signal V FB  is provided to the A-counter  604  and the B-Counter  606  as the load inputs. Accordingly, when the B-counter  606  times out after A+PB cycles, the A-counter  604  and the B-counter  606  reset their timers to A and B, respectively. In coarse adjustment mode, the switch  608  is closed and the switch  610  is opened, so that the reduced frequency signal F R  is provided to the A-counter  604  and the B-counter  606  as the load inputs. Accordingly, the A-counter  604  and B-counter  606  reset every R cycles of the reference signal V R . 
       FIG. 7   a  is an illustrative flow diagram of a method  700   a  for controlling oscillating electrical signals. At a block  702 , a first oscillating signal is generated. In some embodiments a first circuit can be used to generate the first oscillating signal. The first circuit can have a transistor. The Q 1  Oscillator of the oscillator core  104  of  FIG. 2   a  can, for example, be used to generate the first oscillating signal V OP . The method advances from the block  702  to a block  704 . 
     At the block  704 , a second oscillating signal is generated, where the second oscillating signal is in anti-phase with the first oscillating signal at the fundamental and odd harmonics and in phase with the first oscillating signal at even harmonics. In some embodiments a second circuit can be used to generate the second oscillating signal. The first circuit and second circuit can be coupled with each other. With reference to  FIG. 2   a , the Q 2  Oscillator, being coupled with the Q 1  Oscillator, can for example be used to generate the second oscillating signal V ON . As stated above in connection with  FIG. 2   a , the oscillating signals V OP  and V ON  are in anti-phase at the fundamental and odd harmonics and in phase at even harmonics. The method advances from the block  704  to a block  706 . 
     At block  706 , an electrical characteristic is presented to the first circuit and second circuit. The electrical characteristic can control a frequency of oscillation of the first oscillating signal and/or the second oscillating circuit. In some embodiments, a third circuit can be used to present the electrical characteristic to both the first circuit and the second circuit. The third circuit can have an electrical device having a structural type different from the structural type of transistor. A tuning unit  108 ( n ) can, for example, be used to present the electrical characteristic to the oscillator core  104 , and in turn to the Q 1  Oscillator and the Q 2  Oscillator. As stated, each of the tuning units  108 ( 1 ), . . . ,  108 ( n ) can control the frequency of oscillation of the oscillating signal V O  by controlling the frequency of oscillation of the oscillating signals V OP  and V ON . 
     In some embodiments, a third circuit can be used to present the electrical characteristic to at least one of the first circuit or the second circuit, as discussed in connection with  FIG. 1   a . For example, a tuning unit  108 ( n ) can include a first single-ended circuit and a second single-ended circuit, where the first single-ended circuit is coupled with the first circuit (for example, the first oscillator) and the second single-ended circuit is coupled with the second oscillator (for example, the second oscillator) of the oscillator core  104 . The first single-ended circuit and the second single-ended circuit can present electrical characteristics independently to the corresponding first circuit or second circuit. 
       FIG. 7   b  is an illustrative flow diagram of a method  700   b  for generating an oscillating signal in accordance with certain requirements. Examples of requirements include meeting the target frequency, phase, and amplitude within tolerances; and maintaining control signals V C  and/or electrical characteristics within design limits. The method  700   b  illustrated in  FIG. 7   b  is similar to and adapted from the method  700   a  illustrated in  FIG. 7   a . Elements common to both methods  700   a ,  700   b  share common reference indicia, and only differences between the methods  700   a ,  700   b  are described herein for the sake of brevity. The blocks  702 ,  704 ,  706  can be as described earlier in connection with  FIG. 7   a . The method advances from the block  706  to a decision block  708 . 
     As represented by the decision block  708 , the method  700   b  includes testing or checking whether the oscillating signal satisfies the requirements. If the requirements are satisfied, then the method  700   b  can return to the start of the decision block  708  to repeat testing of whether the requirements are satisfied at some later time. The requirements can be tested periodically and/or when triggered by an event or condition. The testing of the decision block  708  may be performed by, for example, the control logic unit  514  of  FIG. 5 . In some embodiments, the control logic unit  514  may receive the oscillating signal V O  (which can be generated by converting V OP  and V ON  to a single-ended output), the control signal V C(n+1) , and/or data from a separate module in addition to receiving the frequency error signal E F , the data comprising data related to the requirements. When the requirements are not satisfied, the method proceeds from the decision block  708  to a block  710 . As represented by the block  710 , the method  700   b  includes adjusting the electrical characteristics. The control logic unit  514  and the loop filter  508  of the PLL  400  can, for example, generate control signals V C1 , . . . , V Cn , V C(n+1)  so that transistors  112 ( 1 ), . . . ,  112 ( n ) adjust the electrical characteristics of the n tuning units  108 ( 1 ), . . . ,  108 ( n ) and/or the varactor  114 . The method can then return from the block  710  to the block  702 . 
     Generally described, in one embodiment, the tuning units  108 ( 1 ), . . . ,  108 ( n ) primarily make large or coarse frequency adjustments to bring the frequency of the oscillating signal V O  to within a neighborhood of the target frequency and/or phase. After the oscillating signal V O  is roughly near the target, the varactor  114  is used to align the frequency of oscillating signal V O  more closely with the target frequency and/or phase. One embodiment of a method for implementing the operation of the block  710  is described below in connection with  FIG. 8 . 
       FIG. 8  is an illustrative flow diagram of an example method  708  for coarse and fine tuning the tuning units  108 ( 1 ), . . . ,  108 ( n ) of  FIGS. 1   a  and  1   b  according to an embodiment. The method  708  starts at a block  802 . As represented by the block  802 , the method  708  includes determining the fine tuning signal(s). The loop filter  508 , for example, generates the control signal V C(n+1) , which controls the variable capacitance of the varactor  114 . As stated above, the varactor  114  can be used for fine tuning of the oscillating signal V O . In fine tuning mode, the control signal V C(n+1)  can be generated by the loop filter  508  based on the charge-pump error signal E CP . In coarse tuning mode, the control signal V C(n+1)  can be a predetermined signal such as a DC signal supplied by a power source or a voltage reference. The method  708  advances the block  802  to a decision block  804 . 
     As represented by the decision block  804 , the method  708  can include testing or checking whether the fine tuning signal is within a bound. The bound can include an upper bound and/or a lower bound. In some embodiments, the bound can be specified based on considerations with respect to one or more of the following aspects: the limits of the power source, swing voltage of the PLL  400 , the breakdown voltage of a component of the PLL  400 , and the like. In some embodiments, the control logic unit  514  performs the testing or checking of the decision block  804 . The method  708  proceeds from the decision block  804  to a block  808  when the fine tuning signal is not within the bound, and proceeds from the decision block  804  to a block  810  when the fine tuning signal is within the bound. As represented in the block  808 , the method  708  includes adjusting the coarse tuning signal(s). In some embodiments, when the fine tuning signal (for example, V C(n+1) ) exceeds the bounds (for example, |V C(n+1) |&gt;V MAX ), the control unit  402  goes into the coarse tuning mode. As stated earlier, in the coarse tuning mode the control signal V C(n+1)  can be set to a constant value. Additionally and/or alternatively, in some embodiments the control logic unit  514  may, for example, search sequentially for a control signal V C  that yields a frequency of oscillating signal V O  that is roughly near the target frequency. As represented by the block  810 , the method  708  includes determining the electrical characteristics of the n tuning units  108 ( 1 ), . . . ,  108 ( n ). The electrical characteristics can be based at least partly on the coarse tuning signal. 
     Numerous inventive principles have been described above, and each has independent utility. In some cases, additional benefits and advantages are realized when the principles are utilized in various combinations with one another. For example, various embodiments of oscillator and PLL arrangements have been described above. Elements of these individual embodiments, however, may be combined with any active circuit. Such an active circuit may be implemented according to the principles and advantages of the embodiments to provide a relatively more robust signal synthesis or synchronization arrangement for the active circuit. 
     Some of the embodiments disclosed herein have been described with specific signals implemented as current-mode or voltage mode signals, but the inventive principles also contemplate other types of signals, whether characterized as voltages or currents. Likewise, some semiconductor devices are described as being specifically NPN or PNP BJTs, but in many cases different polarities or different device and/or structural types such as J-FETs or CMOS transistors can also be utilized. 
     Moreover, the foregoing description and claims may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected). 
     Moreover, oscillator and PLL circuit arrangements employing the above described configurations can be implemented into various electronic devices or integrated circuits. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipments, etc. Examples of the electronic devices can also include memory chips, memory modules, circuits of optical networks or other communication networks, and disk driver circuits. The consumer electronic products can include, but are not limited to, a mobile phone, cellular base stations, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a copier, a facsimile machine, a scanner, a multi functional peripheral device, a wrist watch, a clock, etc. Further, the electronic device can include unfinished products. 
     Thus, the embodiments described herein can be modified in arrangement and detail without departing from the scope of the appended claims. So although specific embodiments have been described, other embodiments will be apparent to those of ordinary skill in the art from the disclosure herein. For example, a skilled artisan will recognize from the disclosure herein that various methods of manufacture, design, and materials can be used to make the various components described herein. Additionally, other combinations, omissions, substitutions and modifications will be apparent to the skilled artisan in view of the disclosure herein. It is contemplated that various aspects and features of the invention described can be practiced separately, combined together, or substituted for one another, and that a variety of combination and sub-combinations of the features and aspects can be made and still fall within the scope of the invention. Furthermore, the systems described above need not include all of the modules and functions described in the preferred embodiments. Accordingly, the present invention is not intended to be limited by the recitation of the specific embodiments described above, but is to be defined by reference to the appended claims.