Patent Publication Number: US-9412323-B2

Title: Power saving method and related waveform-shaping circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a power saving method and a related waveform-shaping circuit, and more particularly, to a power saving method and a related waveform-shaping circuit performing a time-division waveform-shaping function. 
     2. Description of the Prior Art 
     The advantages of a liquid crystal display (LCD) include lighter weight, less electrical consumption, and less radiation contamination. Thus, the LCD monitors have been widely applied to various portable information products, such as notebooks, PDAs, etc. The LCD monitor alters the alignment of liquid crystal molecules to control the corresponding light transmittance by changing the voltage difference between liquid crystals and provides images and produces gorgeous images with light provided by the backlight module. 
     Please refer to  FIG. 1 , which illustrates a schematic diagram of a prior art thin film transistor (TFT) LCD monitor  10 . The LCD monitor  10  includes an LCD panel  122 , a timing controller  102 , a source driver  104 , and a gate driver  106 . The LCD panel  122  is constructed by two parallel substrates, and the liquid crystal molecules are filled up between these two substrates. A plurality of data lines  110 , a plurality of scan lines  112  that are perpendicular to the data lines  110 , and a plurality of TFTs  114  are positioned on one of the substrates. There is a common electrode installed on another substrate, and the voltage generator  108  is electrically connected to the common electrode for outputting a common voltage Vcom via the common electrode. Please note that only four TFTs  114  are shown in  FIG. 1  for clarity. Actually, the LCD panel  122  has one TFT  114  installed in each intersection of the data lines  110  and scan lines  112 . In other words, the TFTs  114  are arranged in a matrix format on the LCD panel  122 . The data lines  110  correspond to different columns, and the scan lines  112  correspond to different rows. The LCD monitor  10  uses a specific column and a specific row to locate the associated TFT  114  that corresponds to a pixel. In addition, the two parallel substrates of the LCD panel  122  filled up with liquid crystal molecules can be considered as an equivalent capacitor  116 . 
     The operation of the prior art LCD monitor  10  is described as follows. First, the timing controller  102  generates data signals corresponding to the images and a timing control signal and a clock signal corresponding control signals for the LCD panel  122 . The source driver  104  and the gate driver  106  then drive different data lines  110  and scan lines  112  according to the signals sent by the timing controller  102 , thereby turning on the corresponding TFTs  114  and controlling the voltage differences in the equivalent capacitor  11 , and further changing the alignment of liquid crystal molecules and light transmittance. For example, the gate driver  106  outputs a pulse to the scan line  112  for turning on the TFT  114 . Therefore, the voltage of the input signal generated by the source driver  104  is inputted into the equivalent capacitor  116  through the data line  110  and the TFT  114 . The voltage difference kept by the equivalent capacitor  116  can then adjust a corresponding gray level of the related pixel through affecting the related alignment of liquid crystal molecules positioned between the two parallel substrates. In addition, the source driver  104  generates the input signals, and magnitude of each input signal inputted to the data line  110  is corresponding to different gray levels. 
     When the TFTs  114  is charged, the voltage drops from a high voltage level Vgh to a low voltage level Vgl on driving signals generated by the gate driver  106  causes a feed-through effect, which makes the voltage levels in pixels lower than it is supposed to be. If the voltage difference due to the feed-through effect is large, the flicker occurs while displaying. One solution to the flicker caused by the feed-through effect is to generate a shaped-waveform on the driving signals. The advantage of the shaped-waveform is that the feed-through effect can be reduced since the abrupt voltage drop from the high voltage level Vgh to the low voltage level Vgl becomes smaller. 
     However, the waveform-shaping circuit in the gate driver  106  works when the power supply thereof charges and discharges regulation capacitor in turns, which consumes a lot of power. Use of a power management chip to switch high voltage level on the driving signals would be an alternative. Still, the power consumption is inevitable since continuous charging and discharging the gate driver  106  is involved. 
     SUMMARY OF THE INVENTION 
     It&#39;s therefore an objective of the present invention to provide a power saving method for a liquid crystal display (LCD). 
     The present invention discloses a power saving method for a LCD comprising a plurality of scan lines. The power saving method comprises segregating the scan lines into a plurality of scan line groups; and individually performing a waveform-shaping function on each of the scan-line groups at different time points. 
     The present invention further discloses an LCD. The LCD comprises a plurality of scan-line groups, wherein each of the scan-line groups comprises a plurality of scan lines, a plurality of waveform-shaping circuits for individually performing a waveform-shaping function on each of the scan-line groups at different time points. Each of the waveform-shaping circuits is coupled to one of the scan-line groups and comprises a waveform-shaping unit for performing the waveform-shaping function; and a control logic unit coupled to the waveform-shaping unit, for controlling the waveform-shaping unit to perform the waveform-shaping function. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a schematic diagram of a prior art TFT LCD monitor. 
         FIG. 2  is an exemplary flow chart of a power saving process for an LCD. 
         FIG. 3  is an exemplary sequence diagram when the waveform-shaping function is enabled and disabled. 
         FIG. 4  is a schematic diagram of an exemplary time-division waveform-shaping circuit. 
         FIG. 5  is a schematic diagram of a time-division waveform-shaping circuit. 
         FIG. 6  is an implementation circuit with multiple gate drivers for the power saving process  20 . 
         FIG. 7  is another implementation circuit with multiple groups in one gate driver for the power saving process  20 . 
         FIG. 8  is an implementation circuit with multiple groups in one gate driver for the power saving process  20 . 
         FIG. 9(A)  is an implementation circuit for the power saving process  20 . 
         FIG. 9(B)  is a waveform diagram of  FIG. 9(A) . 
         FIG. 10(A)  is an implementation circuit for the power saving process  20 . 
         FIG. 10(B)  is a waveform diagram of  FIG. 9(A) . 
         FIG. 11(A)  is an implementation circuit for the power saving process  20 . 
         FIG. 11(B)  is a waveform diagram of  FIG. 9(A) . 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 2 , which is an exemplary flow chart of a power saving process  20  for a liquid crystal display (LCD). The LCD includes multiple scan lines. The power saving process  20  is used for reducing a feed-through effect and power consumption. The power saving process  20  includes the following steps: 
     Step  200 : Start. 
     Step  202 : Segregate multiple scan lines into multiple scan-line groups. 
     Step  204 : Individually perform a waveform-shaping function on each of the scan-line groups at different time points. 
     Step  206 : End. 
     According to the power saving process, each of the scan-line groups performs the waveform-shaping function at the different time points. In other words, only one scan-line group at a time is allowed to perform the waveform-shaping function. The waveform-shaping function is used for the LCD and allows the LCD to shape the waveform of the driving signals, reducing the flickers caused by the feed-through effect. Since the power saving process  20  makes each of the scan-line groups perform the waveform-shaping function in turn, this avoids the charge/discharge loading caused by more than one scan-line groups performing the waveform-shaping together. Further, the power consumption can be reduced. Therefore, the exemplary power saving process  20  can reduce the power consumption while the LCD is performing the waveform-shaping function. 
     The waveform-shaping function can be disabled or enabled according to an input start pulse STI, an output start pulse STO and a clock signal CK. Please refer to  FIG. 3 , which is an exemplary sequence diagram when the waveform-shaping function is enabled and disabled. As shown in  FIG. 3 , the waveform-shaping function is enabled at the falling edge of the clock signal CK when the input start pulse STI is coming. At that moment, the waveform edge of the driving signal V_gpulse is shaped. The waveform-shaping function is disabled when the output start pulse STO is coming. On the other hand, by using different clock signals each of the scan-line groups can perform the waveform-shaping function individually at the different time points. For example, a scan-line group G1 performs the waveform-shaping function according to the input start pulse STI and a clock signal CKD( 1 ) while a scan-line group G2 performs the waveform-shaping function according to the input start pulse and a clock signal CKD( 2 ). Namely, through different clock signals, each of the scan-line groups can perform the waveform-shaping function individually at the different time points. In an example of the present disclosure, the clock signals CKD( 1 ) and CKD( 2 ) are generated by dividing the clock signal CK. 
     Further, the way to segregate the scan lines into scan-line groups includes at least one of the follows: segregating the scan lines into the scan-lie groups according to the gate drivers, a scan-line order or a scan-line quantity. For example, the LCD includes the multiple scan lines, the scan lines are segregated into scan-line groups according to the gate drivers, each of the scan-line groups corresponding to one gate driver. Namely, at a certain time point only one single gate driver enables the waveform-shaping function. The waveform-shaping function is disabled for the other gate drivers so that each scan-line group takes turn to perform the waveform-shaping function, preventing all gate drivers from performing the waveform-shaping function at the same time. Thus, the power consumption can be achieved. In some examples, the power saving process  20  is not limited to multiple gate drivers. It also can be applied to a single gate driver with multiple scan lines. In this situation, the scan lines of the gate driver are segregated into different scan-line groups according to a scan-line order or a specific quantity of the scan lines. For example, a gate driver includes n scan lines g(1), g(2), g(3), . . . , g(n) and k adjacent scan lines can be grouped together. Thus, the scan lines g(1), g(2), g(3), . . . , g(n) are segregated into n/k groups (i.e. scan-line groups G_1, G_2, . . . G_n/k). The scan-line group G_1 includes the scan lines g(1), g(2), . . . , g(k); the scan-line group G_2 includes the scan lines g(k+1), g(k+2), g(k+3), . . . , g(2k), and so on. In some examples, the scan lines g(1), g(2), g(3), . . . , g(n) are grouped together every p scan lines. Namely, the scan-line group G1 includes the scan lines g(1), g(1+p), g(1+2p) . . . , and the scan-line group G_2 includes g(2), g(2+p), g(2+2p), . . . , and so on. When p=2, it represents the even scan lines are grouped together while the odd scan lines are grouped together. In addition, two grouping rules can be combined. The scan lines are segregated into m scan-line groups first and the scan lines in each scan-line group are segregated into an even sub-group and an odd sub-group. Or the scan lines are segregated into an even scan-line group and an scan-line odd group first. Then the scan lines in the odd group are segregated into m1 scan-line sub-groups and the scan lines in the even group are segregated into m2 scan-line sub-groups. 
     Please refer to  FIG. 4 , which is a schematic diagram of an exemplary time-division waveform-shaping circuit  40 . The time-division waveform-shaping circuit  40  can be used in a LCD for performing a waveform shaping function, thereby reducing power consumption. The time-division waveform-shaping circuit  40  includes a waveform-shaping unit  400  and a logic control unit  420 . The waveform-shaping unit  400  is used for performing the waveform-shaping function. The control logic  420  is coupled to the waveform-shaping unit  400  and used for enabling the waveform-shaping function. The implementation of the waveform shaping unit  400  and the logic control unit  420  can be referred to  FIG. 5 .  FIG. 5  is a schematic diagram of a time-division waveform-shaping circuit  50 . The time-division waveform-shaping circuit  50  can implement the time-division waveform-shaping circuit  40 . The time-division waveform-shaping circuit  50  includes a waveform-shaping unit  500  and a control logic unit  520 . The control logic unit  520  includes a flip-flop  521 , a AND gate  522  and a NAND gate  523 . The flip-flop  521  has a first input terminal for receiving an input start pulse STI, a second input terminal for receiving an output start pulse STO and an output terminal for outputting an enable signal EN. The input start pulse STI and the output start pulse are used for enabling and disabling the waveform-shaping function, respectively. The AND gate  522  has a first input terminal for receiving the enable signal EN, a second input terminal for receiving a clock signal CK and an output terminal for outputting a switching control signal C 1 . The NAND gate  523  has a first input terminal for receiving the enable signal EN, a second input terminal for receiving the clock signal CK and an output terminal for outputting a switching control signal C 2 . The switching control signals C 1  and C 2  are used for controlling the waveform-shaping unit  500  to perform the waveform-shaping function. Switches SW 1  and SW 2  are implemented by two transistors and the resistance element RE is implemented by a resistor. Besides, in other examples the resistance element RE can be replaced by a current source in implementation of the waveform-shaping unit  500 . 
     Please refer to  FIG. 6 , which is an implementation circuit  60  with multiple gate drivers for the power saving process  20 . For simplicity, only some essential elements are shown in the implementation circuit  60 . The implementation circuit  60  includes multiple waveform-shaping units  600  and multiple control logic units  620 . Each of the waveform-shaping units  600  includes switches SW 1  and SW 2  and shares a resistance element RE. The implementation circuit  60  segregates the multiple scan lines into scan-line groups G_1, G_2, . . . , G_m according to gate driver Gate(1), Gate(2), . . . , Gate(m). Each scan-line group is coupled to one of the control logic units  620  and one of the waveform-shaping units  600 . Each control logic unit has 3 input terminals for receiving an input start pulse STI, an output start pulse STO and a clock signal CK, respectively, and controls the switches SW 1  and SW 2  according to the input start pulse STI, the output start pulse STO and the clock signal CK. The waveform-shaping units  600  are coupled to a voltage source VGG and a target voltage level VGPM, and individually coupled to the scan lines in each of scan-lines groups to provide a high voltage level VGH(x) and a low voltage level VEE to each scan-line group, where, x=1, 2, 3, . . . , m. When the input start pulse is coming, the control logic units  620  enable the waveform-shaping function on the gate drivers Gate(1), Gate(2), . . . , Gate(m) sequentially. Only one gate driver performs the waveform-shaping function at a certain time point, preventing all the gate driver from performing the waveform-shaping functions at the same time, and further achieving power saving. 
     Please refer to  FIG. 7 , which is another implementation circuit  70  with multiple groups in one gate driver for the power saving process  20 . For simplicity, only essential elements are shown in the implementation circuit  70 . The implementation circuit  70  can be used in a single gate driver and includes multiple waveform-shaping units  700  and multiple control logic units  720 . Each of the waveform-shaping units  700  includes switches SW 1  and SW 2  and shares a resistance element RE. The implementation circuit  70  segregates the scan lines (not shown in  FIG. 7 ) into m scan-line groups (i.e. scan-line groups G_1, G_2, . . . , G_m) according to a specific quantity of the adjacent scan lines (e.g. k adjacent scan lines are grouped together). Each of the scan-line groups is coupled to one of the control logic units  720  and one of the waveform-shaping units  700 . Each control logic unit has 3 input terminals for receiving an input start pulse STI, an output start pulse STO and a clock signal CK, respectively, and controls the switches SW 1  and SW 2  according to the input start pulse STI, the output start pulse STO and the clock signal CK. The waveform-shaping units  700  are coupled to a voltage source VGG and a target voltage level VGPM, and each of the waveform-shaping units  700  is individually coupled to one of the scan-line groups to provide a high voltage level VGH (x) and a low voltage level VEE for each scan-line group, wherein x=1, 2, 3, . . . , m. When the input start pulse STI is coming, the control logic units  720  enable the waveform-shaping function on the scan-line groups G_1, G_2, . . . , G_m, in turn. This allows only one scan-line group at a time to perform the waveform-shaping function, preventing all the scan-line groups from performing the waveform-shaping function together. Further, power saving can be achieved. 
     Please refer to  FIG. 8 , which is an implementation circuit  80  with multiple groups in one gate driver for the power saving process  20 . For simplicity, only essential elements are shown in the implementation circuit  80 . The implementation circuit  80  can be used in a single gate driver and includes multiple waveform-shaping units  800  and multiple control logic units  820 . Each of the waveform-shaping units  800  includes switches SW 1  and SW 2  and shares a resistance element RE. The implementation circuit  80  segregates the scan lines (not shown in  FIG. 8 ) into m scan-line groups (i.e. scan-line groups G_1, G_2, . . . , G_m) according to a specific scan-line order (e.g. every k scan lines are grouped together). Each of the scan-line groups is coupled to one of the control logic units  820  and one of the waveform-shaping units  800 . Each control logic unit has 4 input terminals for receiving an input start pulse STI, an output start pulse STO, a clock signal CK and a clock signal CKD(x), respectively, where, x=1, 2, . . . , m. The waveform-shaping units  800  are coupled to a voltage source VGG and a target voltage level VGPM, and each of the waveform-shaping units  800  is individually coupled to one of the scan-line groups to provide a high voltage level VGH(x) and a low voltage level VEE for each scan-line group, wherein x=1, 2, 3, . . . , m. Via different the clock signals CKD(x), where x=1, 2, 3, . . . , m, the control logic units  820  staggers the times that scan-line groups G_1, G_2, . . . , G_m perform the waveform-shaping function, preventing all the scan-line groups from performing the waveform-shaping function together. Further, power saving can be achieved. 
     Please refer to  FIGS. 9(A) and 9(B) ,  FIG. 9(A)  is an implementation circuit  90  for the power saving process  20  and  FIG. 9(B)  is a waveform diagram of  FIG. 9(A) . The implementation circuit  90  can be used in an LCD for staggering the times that an odd scan-line group G_odd and an even scan-line group G_even perform the waveform-shaping function. The implementation  90  includes a first waveform-shaping unit  900 , a first control logic unit  920 , a second waveform-shaping unit  940  and a second control logic unit  960 . The first waveform-shaping unit  900  is coupled to a voltage source VGG, a target voltage level VGPM, and the scan lines in the even scan-line group G_even, to provide the even scan-line group a high voltage level VGH even. The first waveform-shaping unit  900  includes switches SW 1  and SW 2  and shares a resistance element RE with the second waveform-shaping unit  940 . The first control logic unit  920  includes a flip-flop  921 , an AND gate  922  and a NAND gate  923 . The flip-flop  921  has a first input terminal for receiving an input start pulse STI, a second input terminal for receiving an output start pulse STO and an output terminal for outputting an enable signal EN 1 . The AND gate  922  has a first input terminal for receiving the enable signal EN 1 , a second input terminal for receiving a first clock signal CK, a third input signal for receiving a second clock signal  CK/ 2    and an output terminal for turning on/off the switch SW 1 . The NAND gate  923  has a first input terminal for receiving the enable signal EN 1 , a second input terminal for receiving the first clock signal CK, a third input terminal for receiving the second clock signal  CK/ 2    and an output terminal for turning on/off the switch SW 2 . The second clock signal  CK/ 2    is generated by dividing the first clock signal CK and then reversing the divided clock signal. The second waveform-shaping unit  940  is coupled to the voltage source VGG, the target voltage level VGPM and the scan lines in the odd scan-line group G_odd, to provide the odd scan-line group a high voltage VGH_odd. The second waveform-shaping unit  940  includes switches SW 3  and SW 4  and shares the resistance element RE with the first waveform-shaping unit  900 . The second control logic unit  960  includes a flip-flop  961 , an AND gate  926  and a NAND gate  963 . The flip-flop  961  has a first input terminal for receiving the start input pulse STI, a second input terminal for receiving the output start pulse STO and an output terminal for outputting an enable signal EN 2 . The AND gate  962  has a first input terminal for receiving the enable signal EN 2 , a second input terminal for receiving the clock signal CK, a third input terminal for receiving a third clock signal CK/ 2  and an output terminal for turning on/off the switch SW 3 . The NAND gate  963  has a first input terminal for receiving the enable signal EN 2 , a second input terminal for receiving the clock signal CK, a third input signal for receiving the third clock signal CK/ 2  and an output terminal for turning on/off the switch SW 4 . The third clock signal CK/ 2  is generated by dividing the clock signal CK. When the input start pulse is coming, the waveform-shaping unit  900  and the waveform-shaping unit  940  perform the waveform-shaping function on the even scan-line group G_even and the odd scan-line group G_odd according to the second clock signal  CK/ 2    and the third clock signal CK/ 2 , respectively. 
     On the other hand, the waveform-shaping function can be performed on scan lines in an arbitrary order by controlling the second clock signal and the third clock signal. Please refer to  FIGS. 10(A) and 10(B) ,  FIG. 10(A)  is an exemplary schematic diagram of an implementation circuit  100  and  FIG. 10(B)  is a waveform diagram of  FIG. 10(A) . The implementation  100  is a variation of the implementation  90 . Basically, the circuit structure of the implementation  100  is similar to the one of the implementation  90  so that the same reference number indicates identical or functionally similar elements, and therefore the detailed description thereof is omitted herein. The only difference is a clock signal CKD in the implementation  100 . By controlling the clock signal CKD, the even scan-line group G_even and the odd scan-line group G_odd can perform the waveform-shaping function in turn. The waveform-shaping function is perform in the order: g(1), g(2), g4), g(3), g(5), g(6), g(8), g(7). 
     Please refer to  FIGS. 11(A) and 11(B) ,  FIG. 11(A)  is a schematic diagram of an implementation circuit  110  and  FIG. 11(B)  is a waveform diagram of  FIG. 11(A) . The implementation circuit  110  includes a flip-flop  1100 , NAND gates  1120 ,  1140  and  1160 , switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5  and SW 6 , and a resistance element RE. In the implementation circuit  110 , every 3 scan lines (not shown in  FIG. 11(A) ) are grouped together, forming the scan-line groups G_1, G_2 and G_3. The scan-line group G_1 includes the scan lines g(1), g(4), g(7), . . . ; the scan-line group G_2 includes the scan lines g(2), g(5), g(8), . . . ; the scan-line group G_3 includes the scan lines g(3), g(6), g(9), . . . . The flip-flop  1100  has a first input terminal for receiving a start input pulse, a second input terminal for receiving an output start pulse and an output terminal for outputting an enable signal EN. The NAND gate  1120  has a first input terminal for receiving the enable signal EN, a second input terminal for receiving a first clock signal CK, a third input signal for receiving a second clock signal CKD( 1 ) and an output terminal for turning on/off the switches SW 1  and SW 2 . The NAND gate  1140  has a first input terminal for receiving the enable signal EN, a second input terminal for receiving the first clock signal CK, a third input terminal for receiving a third clock signal CKD( 2 ) and an output terminal for turning on/off the switches SW 3  and SW 4 . The NAND gate  1160  has an first input terminal for receiving the enable signal EN, a second input terminal for receiving the first clock signal CK, a third input terminal for receiving a forth clock signal CKD( 3 ) and an output terminal for turning on/off the switches SW 5  and SW 6 . The switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5  and SW 6  are individually coupled to the scan-line groups G_1, G_2 and G_3. When the start input pulse STI is coming, the different clock signals CKD( 1 ), CKD( 2 ) and CKD( 3 ) are used to perform the waveform-shaping function on the scan-line groups G_1, G_2 and G_3 individually. 
     Please note that all the flip-flop abovementioned can be implemented by a D flip flop. 
     To sum up, the examples of the present disclosure segregate the scan lines in a LCD into different scan-line groups and perform the waveform-shaping function on each of the scan-line groups at different times. This prevents all the scan-line groups from performing the waveform-shaping function at the same time, achieving power saving. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.