Patent Publication Number: US-10783847-B2

Title: Display apparatus

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefits of U.S. provisional application Ser. No. 62/775,469, filed on Dec. 5, 2018, and Taiwan application serial no. 108121280, filed on Jun. 19, 2019. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     Technical Field 
     The disclosure relates to an electronic apparatus, and particularly to a display apparatus. 
     Description of Related Art 
     With the progress of display technologies, display apparatuses have been widely used in daily lives, such as home audio-visual entertainment, information display boards in public places, displays for electronic sports, and portable electronic products. 
     Generally, a display apparatus includes a pixel array substrate, an opposite substrate, and a display medium disposed between the pixel array substrate and the opposite substrate. The pixel array substrate has a plurality of pixels. In order to improve the resolution of the display apparatus, more pixels must be arranged in a unit area. That is, the distance between a pixel electrode and a data line of a pixel is reduced. When the distance between the pixel electrode and the data line is short, the coupling capacitance of the pixel electrode and the data line is large, which causes a vertical cross-talk phenomenon. 
     SUMMARY 
     The disclosure provides a display apparatus which is good in performance. 
     A display apparatus of an embodiment of the disclosure includes a substrate, pixels arranged on the substrate, and a gate driver. Each pixel includes a scan line, a data line, a first switching element and a first pixel electrode. The first switching element has a first end, a second end, and a control end. The first end of the first switching element is electrically connected to the data line. The control end of the first switching element is electrically connected with the scan line. The first pixel electrode is electrically connected with the second end of the first switching element. The pixels include N pixels arranged in order, N is a positive integer greater than or equal to 2, the N pixels include a p th  pixel and a q th  pixel, p is an odd number less than or equal to N, p is a positive integer, q is an even number less than or equal to N, and q is a positive integer. The gate driver is electrically connected to a scan line of the p th  pixel, where the gate driver receives a first start signal to generate a first gate pulse signal in a first sub-frame interval of a frame interval. The gate driver is electrically connected to a scan line of the q th  pixel, where the gate driver receives a second start signal to generate a second gate pulse signal in a second sub-frame interval of the frame interval following the first sub-frame interval. The first gate pulse signal has a first enabling time width, the second gate pulse signal has a second enabling time width, and the first enabling time width is different from the second enabling time width. 
     A display apparatus of an embodiment of the disclosure includes a substrate, pixels arranged on the substrate, and a gate driver. Each pixel includes a scan line, a data line, a first switching element, a first pixel electrode, a second switching element, a second pixel electrode, a third switching element, a control line and a charging updating capacitor. The first switching element has a first end, a second end, and a control end, where the first end of the first switching element is electrically connected to the data line, and the control end of the first switching element is electrically connected to the scan line. The first pixel electrode is electrically connected to the second end of the first switching element. The second switching element has a first end, a second end, and a control end. The first end of the second switching element is electrically connected to the data line. The control end of the second switching element is electrically connected to the scan line. The second end of the second switching element is electrically connected to the second pixel electrode. The third switching element has a first end, a second end, and a control end. The first end of the third switching element is electrically connected to the second end of the second switching element. The control end of the third switching element is electrically connected to the control line. The second end of the third switching element is electrically connected to the charging updating capacitor. The pixels include N pixels arranged in order, N is a positive integer greater than or equal to 2, the N pixels include a p th  pixel and a q th  pixel, p is an odd number less than or equal to N, p is a positive integer, q is an even number less than or equal to N, and q is a positive integer. The gate driver is electrically connected to a scan line of the p th  pixel, where the gate driver receives a first start signal to generate a first gate pulse signal in a first sub-frame interval of a frame interval. The gate driver is electrically connected to a scan line of the q th  pixel, where the gate driver receives a second start signal to generate a second gate pulse signal in a second sub-frame interval of the frame interval following the first sub-frame interval. 
     In order to make the aforementioned features and advantages of the disclosure comprehensible, embodiments accompanied with figures are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles described herein. 
         FIG. 1  is a schematic diagram of a display apparatus according to an embodiment of the disclosure. 
         FIG. 2  illustrates first gate pulse signals Vg 1 , Vg 3 , Vg 5  and Vg 7 , second gate pulse signals Vg 2 , Vg 4  and Vg 6 , a polarity signal Vpol, a first start signal Vst 1 , a second start signal Vst 2 , a first data signal Vd 11 , a second data signal Vd 12  and a signal Vpx of a pixel electrode according to an embodiment of the disclosure. 
         FIG. 3  is a layout diagram of a pixel PX according to an embodiment of the disclosure. 
         FIG. 4  is a schematic cross-sectional view of a display apparatus according to an embodiment of the disclosure. 
         FIG. 5  is a schematic layout diagram of a pixel PXA according to another embodiment of the disclosure. 
         FIG. 6A  is a circuit diagram of a pixel PXB according to yet another embodiment of the disclosure. 
         FIG. 6B  is a layout diagram of a pixel PXB according to yet another embodiment of the disclosure. 
         FIG. 7  is a layout diagram of a pixel PXC according to yet another embodiment of the disclosure. 
         FIG. 8  is a circuit diagram of a pixel PXD according to an embodiment of the disclosure. 
         FIG. 9  is a circuit diagram of a pixel PXE according to another embodiment of the disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     In the accompanying drawings, the thicknesses of layers, films, panels, regions, and the like are enlarged for clarity. Throughout the specification, same reference numerals indicate same components. It should be understood that when a component such as a layer, film, region or substrate is referred to as being “on” or “connected” to another component, it may be directly on or connected to the another component, or intervening components may also be present. In contrast, when a component is referred to as being “directly on” or “directly connected to” another component, there are no intervening assemblies present. As used herein, “connection” may refer to a physical and/or electrical connection. In addition, an “electrical connection” or “coupling” may be the another component between two components. 
     As used herein, “about”, “approximately”, or “substantially” is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Further, as used herein, “about”, “approximately”, or “substantially” may depend on optical properties, etch properties, or other properties to select a more acceptable range of deviations or standard deviations without one standard deviation for all properties. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  is a schematic diagram of a display apparatus according to an embodiment of the disclosure. 
       FIG. 2  illustrates first gate pulse signals Vg 1 , Vg 3 , Vg 5  and Vg 7 , second gate pulse signals Vg 2 , Vg 4  and Vg 6 , a polarity signal Vpol, a first start signal Vst 1 , a second start signal Vst 2 , a first data signal Vd 11 , a second data signal Vd 12 , and a signal Vpx of a pixel electrode according to an embodiment of the disclosure. 
       FIG. 3  is a diagram illustrating a layout of a pixel PX according to an embodiment of the disclosure.  FIG. 1  omits a depiction of a substrate  110  of  FIG. 3 . 
       FIG. 4  is a schematic cross-sectional view of a display apparatus according to an embodiment of the disclosure. The cross-section of a pixel array substrate  1  of  FIG. 4  corresponds to section lines A-A′ and B-B′ of  FIG. 3 . 
     Referring to  FIG. 1 ,  FIG. 3  and  FIG. 4 , a display apparatus  10  includes a pixel array substrate  1 , an opposite substrate  2  opposite to the pixel array substrate  1 , and a display medium  3  disposed between the pixel array substrate  1  and the opposite substrate  2 . 
     In the present embodiment, the opposite substrate  2  may optionally include a substrate  210 , a light blocking pattern  230 , and a color filter layer  220 . The light blocking pattern  230  is commonly referred to as a black matrix. The light blocking pattern  230  is arranged on the substrate  210  and has a plurality of openings  232 . The color filter layer  220  is arranged on the substrate  210  and is overlapped with the openings  232  of the light blocking pattern  230 . However, the disclosure is not limited thereto, and according to other embodiments, the color filter layer  220  and/or the light blocking pattern  230  may be arranged on the substrate  110  of the pixel array substrate  1  to form a structure of a color filter on array (COA) and/or a black matrix on array (BOA). 
     In the present embodiment, the display medium  3  may be a non-self-luminescent material, such as but not limited to: liquid crystal. However, the disclosure is not limited thereto, and according to other embodiments, the display medium  3  may also be a self-luminescent material, such as but not limited to: an organic electroluminescent material and a micro light emitting diode (μLED). 
     The pixel array substrate  1  includes a substrate  110  and a plurality of pixels PX arranged on the substrate  110 . Each pixel PX includes a scan line SL, a data line DL, a switching element T, and a pixel electrode  130 . The data line DL extends in a first direction d 1 , and the scan line SL extends in a second direction d 2 , where the first direction d 1  is staggered from the second direction d 2 . The switching element T includes a control end Tc, a gate insulating layer GI, a semiconductor pattern Td, a first end Ta and a second end Tb. The gate insulating layer GI is arranged between the control end Tc and the semiconductor pattern Td. The first end Ta and the second end Tb are electrically connected to two different regions of the semiconductor pattern Td, respectively. The first end Ta of the switching element T is electrically connected to the data line DL. The control end Tc of the switching element T is electrically connected to the scan line SL. A pixel electrode  130  is electrically connected to the second end Tb of the switching element T. 
     Referring to  FIG. 3 , in the present embodiment, at least one pixel PX includes a shielding conductive pattern  120 . The shielding conductive pattern  120  is arranged between the data line DL of the pixel PX and the pixel electrode  130  of the pixel PX. That is, at least a portion of the vertical projection of the shielding conductive pattern  120  on the substrate  110  is located between the vertical projection of the data line DL on the substrate  110  and the vertical projection of the pixel electrode  130  on the substrate  110 . 
     For example, in the present embodiment, the shielding conductive pattern  120  may include a first shielding conductive portion  120   a  and a second shielding conductive portion  120   b , the first shielding conductive portion  120   a  is arranged between the data line DL and the pixel electrode  130  of the same pixel PX 1 , and the second shielding conductive portion  120   b  is arranged between the pixel electrode  130  of one pixel PX 1  and the data line DL of another pixel PX 2 . In the present embodiment, the first shielding conductive portion  120   a  and the second shielding conductive portion  120   b  extend in the first direction d 1 . That is, in the present embodiment, the first shielding conductive portion  120   a , the second shielding conductive portion  120   b , and the data line DL may be parallel approximately, but the disclosure is not limited thereto. 
     In the present embodiment, the first shielding conductive portion  120   a  may be partially overlapped with the pixel electrode  130 , and the second shielding conductive portion  120   b  may be partially overlapped with the pixel electrode  130 . However, the disclosure is not limited thereto, and according to other embodiments, the first shielding conductive portion  120   a  and/or the second shielding conductive portion  120   b  may be not overlapped with the pixel electrode  130 . 
     Referring to  FIG. 3  and  FIG. 4 , in the present embodiment, the shielding conductive pattern  120  and the scan line SL may be manufactured together. That is, the shielding conductive pattern  120  and the scan line SL may be formed on the same conductive layer, and the material of the shielding conductive pattern  120  and the material of the scan line SL may be the same. 
     Based on consideration on conductivity, the scan line SL is generally made of a metallic material. However, the disclosure is not limited thereto, and according to other embodiments, the scan line SL may also be made of other conductive materials such as alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or stacked layers of metallic materials and other conductive materials. 
     In the present embodiment, the shielding conductive pattern  120  has a predetermined potential including a fixed potential (such as OV, ground or floating potential) or an adjustable non-zero potential. 
     In the present embodiment, the pixel PX further includes a common electrode  240  (drawn in  FIG. 4 ). The potential difference between the common electrode  240  and the pixel electrode  130  is used to drive the display medium  3 . 
     For example, in the present embodiment, the display apparatus  10  may be a multi-domain vertical alignment (MVA) type liquid crystal display, the pixel electrode  130  includes a first main portion  130   a  (drawn in  FIG. 3 ), a second main portion  130   b  (drawn in  FIG. 3 ) staggered from the first main portion  130   a , and a plurality of branch portions  130   c  (drawn in  FIG. 3 ) connected to the first main portion  130   a  and the second main portion  130   b , and the pixel electrode  130  and the common electrode  240  may be arranged on two substrates  110  and  210  which are opposite, respectively. However, the disclosure is not limited thereto, and according to other embodiments, the pixel electrode  130  may be in other shapes and/or the pixel electrode  130  and the common electrode  240  may be arranged on the same substrate. 
     In the present embodiment, the pixel PX may optionally include a shielding electrode  140  (drawn in  FIG. 3 ). The shielding electrode  140  is overlapped with the first main portion  130   a  and the second main portion  130   b  of the pixel electrode  130 . In the present embodiment, the shielding electrode  140  and the shielding conductive pattern  120  may be formed on the same conductive layer, and the shielding electrode  140  may be connected between the first shielding conductive portion  120   a  and the second shielding conductive portion  120   b , but the disclosure is not limited thereto. 
     Referring to  FIG. 1 , the display apparatus  10  further includes a drive system for driving a plurality of pixels PX. The drive system may include a timing control circuit  4 , a gate driver  5  and a data drive circuit  6 . The timing control circuit  4  is electrically connected with the gate driver  5  and the data drive circuit  6 . The gate driver  5  is electrically connected with the scan lines SL of the pixels PX. The data drive circuit  6  is electrically connected with the data lines DL of the pixels PX. 
     The pixels PX are arranged into a pixel array. In the embodiment of  FIG. 1 , the gate driver  5  may be selectively arranged on a single side of the pixel array. However, the disclosure is not limited thereto, and according to other embodiments, the gate drivers  5  may be arranged on two opposite sides of the pixel array. 
     The pixels PX include N pixels PX arranged in order in the first direction d 1 . N is a positive integer greater than or equal to 2. The N pixels include a p th  pixel PX and a q th  pixel PX, p is an odd number less than or equal to N, p is a positive integer, q is an even number less than or equal to N, and q is a positive integer. In brief, the N pixels PX arranged in order in the first direction d 1  include odd-numbered pixels PX and even-numbered pixels PX. 
     For example, the pixels PX arranged in order in the first direction d 1  include 1st, 3rd, 5th, 7th . . . pixels PX and 2nd, 4th, 6th . . . pixels PX, where the 1st, 3rd, 5th. 7th . . . pixels PX include scan lines SL 1 , SL 3 , SL 5 , SL 7  . . . , respectively, and 2nd, 4th and 6th pixels PX include scan lines SL 2 , SL 4 , SL 6  . . . respectively. 
     Referring to  FIG. 1  and  FIG. 2 , in a first sub-frame interval t1 of a frame interval t, the gate driver  5  receives a first start signal Vst 1  from the timing control circuit  4  to generate a plurality of first gate pulse signals Vg 1 , Vg 3 , Vg 5 , Vg 7  . . . . In the first sub-frame interval t1, the first gate pulse signals Vg 1 , Vg 3 , Vg 5 , Vg 7  . . . are transmitted to the scan lines SL 1 , SL 3 , SL 5 , SL 7  . . . of the odd-numbered pixels PX in a timing sequence. 
     In a second sub-frame interval t2 of the same frame interval t following the first sub-frame interval t1, the gate driver  5  receives a second start signal Vst 2  to generate a plurality of second gate pulse signals Vg 2 , Vg 4 , Vg 6  . . . , where the second gate pulse signals Vg 2 , Vg 4 , Vg 6  . . . are transmitted to the scan lines SL 2 , SL 4 , SL 6  . . . of the even-numbered pixels PX in a timing sequence. 
     In the first sub-frame interval t1 and the second sub-frame interval t2, the timing control circuit  4  outputs a polarity signal Vpol to the data drive circuit  6 . The polarity signal Vpol is switched from a first voltage level to a second voltage level after the scan lines SL 1 , SL 3 , SL 5 , SL 7  . . . of the odd-numbered pixels PX receive the first gate pulse signals Vg 1 , Vg 3 , Vg 5 , Vg 7  . . . and before the scan lines SL 2 , SL 4 , SL 6  . . . of the even-numbered pixels PX receive the second gate pulse signals Vg 2 , Vg 4 , Vg 6  . . . . 
     The data drive circuit  6  receives the polarity signal Vpol to respectively output a first data signal Vd 11  and a second data signal Vd 12  to the same data line DL in the first sub-frame interval t1 and the second sub-frame interval t2, where the polarity of the first data signal Vd 11  is opposite to that of the second data signal Vd 12 . For example, in the present embodiment, the pixel array includes a plurality of pixel rows R 1  and R 2  arranged in the second direction d 2 , and a plurality of pixels PX of each of the pixel rows R 1  and R 2  are sequentially arranged in the first direction d 1 ; the pixel rows R 1  and R 2  include a plurality of odd-numbered pixel rows R 1  and a plurality of even-numbered pixel rows R 2  which are alternately arranged in the second direction d 2 ; in the first sub-frame interval t1, the odd-numbered pixels PX of the odd-numbered pixel rows R 1  have a first polarity (such as a positive polarity), and the odd-numbered pixels PX of the even-numbered pixel rows R 2  have a second polarity (such as a negative polarity); in the second sub-frame interval t2, the even-numbered pixels PX of the odd-numbered pixel rows R 1  have the second polarity (such as the negative polarity), and the even-numbered pixels PX of the even-numbered pixel rows R 2  have the first polarity (such as the positive polarity); but the disclosure is not limited thereto. 
     Thus, the pixel electrode  130  is coupled to the data line DL, of which the polarity is opposite to that of the pixel electrode  130 , in the first sub-frame interval t1 and the second sub-frame interval t2, respectively. Voltage difference ΔV 1  and voltage difference ΔV 2  of a signal Vpx of the pixel electrode  130 , which are caused by capacitive coupling of the data line DL and the pixel electrode  130  in the first sub-frame interval t1 and the second sub-frame interval t2, respectively, compensate to each other, which relieves the vertical cross-talk phenomenon. 
     It is worth noting that, the first gate pulse signals Vg 1 , Vg 3 , Vg 5 , Vg 7  . . . have a first enabling time width W1 which refers to the length of time when the first gate pulse signals Vg 1 , Vg 3 , Vg 5 , Vg 7  . . . have gate switch-on potentials, and the second gate pulse signals Vg 2 , Vg 4 , Vg 6  . . . have a second enabling time width W2 which refers to the length of time when the second gate pulse signals Vg 2 , Vg 4 , Vg 6  . . . have gate switch-on potentials, and the first enabling time width W1 is different from the second enabling time width W2. 
     That is, the pixel electrode  130  of each pixel PX, the common electrode  240  and the display medium  3  may form a display capacitor, and the display capacitors of the odd-numbered pixels PX and the display capacitors of the even-numbered pixels PX are charged in the first sub-frame interval t1 and the second sub-frame interval t2 following the first sub-frame interval t1, respectively, and the charging time of the display capacitors of the odd-numbered pixels PX is different from the charging time of the display capacitors of the even-numbered pixels PX. Therefore, poor display caused by leakage of the switching elements T may be avoided. 
     For example, in the present embodiment, 0.05≤|W1−W2|/W1≤0.30 Specifically, the first enabling time width W1 and/or the second enabling time width W2 may be between 12 microseconds (μs) and 14 microseconds, but the disclosure is not limited thereto. 
       FIG. 5  is a layout diagram of a pixel PXA according to another embodiment of the disclosure. The pixel PXA of  FIG. 5  is similar to the pixel PX of  FIG. 3 , and the difference between the pixel PXA of  FIG. 5  and the pixel PX of  FIG. 3  is as follows: the pixel PXA of  FIG. 5  does not include the shielding conductive pattern  120  of the pixel PX of  FIG. 3 . That is, in the embodiment of  FIG. 5 , no shielding conductive pattern extending in the first direction d 1  is arranged between the data line DL and the pixel electrode  130 . 
     The pixels PXA of  FIG. 5  may be used in place of the pixels PX of  FIG. 1  to form another display apparatus  10 A. The display apparatus  10 A including a plurality of pixels PXA may also be driven by the foregoing drive system. In particular, the pixel PXA does not include the shielding conductive pattern  120  and the display apparatus  10 A has a high aperture ratio, and the vertical cross-talk phenomenon may be relieved on the premise of having the high aperture ratio by the display apparatus  10 A which is matched with the foregoing drive system. 
       FIG. 6A  is a circuit diagram of a pixel PXB according to yet another embodiment of the disclosure.  FIG. 6B  is a layout diagram of a pixel PXB according to yet another embodiment of the disclosure. The pixels PXB of  FIG. 6A  and the pixels PXB of  FIG. 6B  are similar to the pixels PX of  FIG. 3 , and the difference between the pixels PXB of  FIG. 6A  and  FIG. 6B  and the pixels PX of  FIG. 3  is stated as follows. 
     Referring to  FIG. 6A  and  FIG. 6B , in the present embodiment, each pixel PXB includes a scan line SL, a data line DL, a control line CL, a switching element T and a pixel electrode  130 . The switching element T includes a first switching element T 1 , a second switching element T 2  and a third switching element T 3 , and the pixel electrode  130  includes a first pixel electrode  131  and a second pixel electrode  132 . 
     The first switching element T 1  includes a control end Tc, a first end Ta and a second end Tb. The first end Ta of the first switching element T 1  is electrically connected to the data line DL. The control end Tc of the first switching element T 1  is electrically connected to the scan line SL. The first pixel electrode  131  is electrically connected to the second end Tb of the first switching element T 1 . 
     The second switching element T 2  has a first end Ta, a second end Tb and a control end Tc. The first end Ta of the second switching element T 2  is electrically connected to the data line DL. The control end Tc of the second switching element T 2  is electrically connected to the scan line SL. The second end Tb of the second switching element T 2  is electrically connected to the second pixel electrode  132 . 
     The third switching element T 3  has a first end Ta, a second end Tb and a control end Tc. The first end Ta of the third switching element T 3  is electrically connected to the second end Tb of the second switching element T 2 . The control end Tc of the third switching element T 3  is electrically connected to the control line CL. In the present embodiment, the control line CL may extend in the second direction d 2 , and the control line CL may be parallel to the scan line SL approximately, but the disclosure is not limited thereto. 
     In the present embodiment, the pixel PXB further includes a shielding electrode  140 . The shielding electrode  140  includes a first shielding electrode  141  and a second shielding electrode  142 . The first shielding electrode  141  is overlapped with the first main portion  130   a  and the second main portion  130   b  of the first pixel electrode  131 . The second shielding electrode  142  is overlapped with the first main portion  130   a  and the second main portion  130   b  of the second pixel electrode  132 . 
     The second shielding electrode  142  is overlapped with the second pixel electrode  132  to form a charging updating capacitor Cx. The second end Tb of the third switching element T 3  is electrically connected to one electrode (namely the second shielding electrode  142 ) of the charging updating capacitor Cx. 
     For example, in the present embodiment, the pixel PXB further includes a connection pattern  150 , where the connection pattern  150  and the pixel electrode  130  may be formed on the same film layer, and the second end Tb of the third switching element T 3  may be electrically connected to the second shielding electrode  142  through the connection pattern  150 , but the disclosure is not limited thereto. 
     In the present embodiment, the pixel PXB includes a shielding conductive pattern  120 . The shielding conductive pattern  120  is arranged between the data line DL of the pixel PX and the first pixel electrode  131  of the pixel PX. That is, at least a part of the vertical projection of the shielding conductive pattern  120  on the substrate  110  is located between the vertical projection of the data line DL on the substrate  110  and the vertical projection of the first pixel electrode  131  on the substrate  110 . 
     The pixels PXB include pixels PX 1  and pixels PX 2  which are arranged and adjacent to each other in the second direction d 2 . For example, in the present embodiment, the shielding conductive pattern  120  may include a first shielding conductive portion  120   a  and a second shielding conductive portion  120   b , the first shielding conductive portion  120   a  is arranged between the data line DL and the first pixel electrode  131  of the same pixel PX 1 , and the second shielding conductive portion  120   b  is arranged between the first pixel electrode  131  of one pixel PX 1  and the data line DL of another pixel PX 2 . 
     Pixels PXB may be used in place of the pixels PX of  FIG. 1  to form another display apparatus  10 B. The display apparatus  10 B including the pixels PXB may also be driven by the foregoing drive system. The vertical cross-talk phenomenon may be relieved by the display apparatus  10 B which includes the pixels PXB and is matched with the foregoing drive system. 
       FIG. 7  is a layout diagram of a pixel PXC according to yet another embodiment of the disclosure. Pixels PXC of  FIG. 7  are similar to the pixels PXB of  FIG. 6A  and  FIG. 6B , the difference between the pixels PXC of  FIG. 7  and the pixels PXB of  FIG. 6A  and  FIG. 6B  is as follows: the pixels PXC of  FIG. 7  do not include the shielding conductive patterns  120  of the pixels PXB of  FIG. 6A  and  FIG. 6B . That is, in the embodiment of  FIG. 7 , no shielding conductive pattern extending in the first direction d 1  is arranged between the data line DL and the first pixel electrode  131 . 
     Pixels PXC of  FIG. 7  may be used in place of pixels PX of  FIG. 1  to form another display apparatus  10 C. The display apparatus  10 C including a plurality of pixels PXC may also be driven by the foregoing drive system. In particular, the pixels PXC do not include the shielding conductive patterns  120  and the display apparatus  10 C has a high aperture ratio, and the vertical cross-talk phenomenon may be relieved on the premise of having the high aperture ratio by the display apparatus  10 C matched with the foregoing drive system. 
       FIG. 8  is a circuit diagram of a pixel PXD according to an embodiment of the disclosure. Pixels PXD of  FIG. 8  are similar to pixels PX of  FIG. 3 , and the difference between the pixels PXD of  FIG. 8  and the pixels PX of  FIG. 3  is as follows. 
     Referring to  FIG. 8 , in the present embodiment, each pixel PXD includes a scan line SL, a data line DL, a common line T 1 , a switching element T and a pixel electrode  130 . The switching element T includes a first switching element T 1 , a second switching element T 2  and a third switching element T 3 , and the pixel electrode  130  includes a first pixel electrode  131  and a second pixel electrode  132 . 
     The first switching element T 1  includes a control end Tc, a first end Ta and a second end Tb. The first end Ta of the first switching element T 1  is electrically connected to the data line DL. The control end Tc of the first switching element T 1  is electrically connected to the scan line SL. The first pixel electrode  131  is electrically connected to the second end Tb of the first switching element T 1 . 
     The second switching element T 2  has a first end Ta, a second end Tb and a control end Tc. The first end Ta of the second switching element T 2  is electrically connected to the data line DL. The control end Tc of the second switching element T 2  is electrically connected to the scan line SL. The second end Tb of the second switching element T 2  is electrically connected to the second pixel electrode  132 . 
     The third switching element T 3  has a first end Ta, a second end Tb and a control end Tc. The first end Ta of the third switching element T 3  is electrically connected to the second end Tb of the second switching element T 2 . The control end Tc of the third switching element T 3  is electrically connected to the scan line SL. The second end Tb of the third switching element T 3  is electrically connected to the common line TL. 
     In the present embodiment, the pixel PXD includes a shielding conductive pattern (not shown) on an actual layout. The shielding conductive pattern is arranged between the data line DL of the pixel PXD and the first pixel electrode  131  of the pixel PXD. That is, at least a part of the vertical projection of the shielding conductive pattern on the substrate (not shown) is located between the vertical projection of the data line DL on the substrate and the vertical projection of the first pixel electrode  131  on the substrate. 
     The pixels PXD include pixels PX 1  and pixels PX 2  which are arranged and adjacent to each other in the second direction d 2 . For example, in the present embodiment, on an actual layout, the shielding conductive pattern (not shown) may include a first shielding conductive portion (not shown) and a second shielding conductive portion (not shown), the first shielding conductive portion is arranged between the data line DL and the first pixel electrode  131  of the same pixel PX 1 , and the second shielding conductive portion is arranged between the first pixel electrode  131  of one pixel PX 1  and the data line DL of another pixel PX 2 . 
     Pixels PXD of  FIG. 8  may be used in place of pixels PX of  FIG. 1  to form another display apparatus  10 D. The display apparatus  10 D including a plurality of pixels PXD may also be driven by the foregoing drive system. The vertical cross-talk phenomenon may be relieved by the display apparatus  10 D which includes the pixels PXD and is matched with the foregoing drive system. 
       FIG. 9  is a circuit diagram of a pixel PXE according to another embodiment of the disclosure. Pixels PXE of  FIG. 9  are similar to pixels PXD of  FIG. 8 , and the difference between the pixels PXE of  FIG. 9  and the pixels PXD of  FIG. 8  is as follows: the pixels PXE of  FIG. 9  do not include the shielding conductive patterns of the pixels PXD of  FIG. 8 . That is, in the embodiment of  FIG. 9 , no shielding conductive pattern extending in the first direction d 1  is arranged between the data line DL and the first pixel electrode  131 . 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.