Patent Publication Number: US-10775870-B2

Title: System and method for maintaining cache coherency

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2017-099969, filed on May 19, 2017, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The embodiments discussed herein relate to a processing system and a control method of a processing system. 
     BACKGROUND 
     A processing system including multiple computing nodes is widely used. Each of the computing nodes in the processing system includes a processor core acting as a process execution part for performing arithmetic operations, and a cache memory that is more quickly accessible than a main memory for storing data. The cache memory is placed between the processor core and the main memory, and retains part of data stored in the main memory. Each computing node performs cache coherency control to maintain data consistency stored in each cache memory (e.g. cache coherency). 
     For instance, in a multiprocessor system including multiple main memories and multiple processors each containing cache memory, a method for performing cache coherency control is proposed by referring to tag information of the main memory (see Patent Document 1, for example). The tag information of the main memory is information indicating, for each data group corresponding to a cache line, if a dirty cache line exists in a processor other than a processor corresponding to the main memory, and is stored in a tag memory provided in each main memory. The “dirty” is a state of the cache memory whose data is updated but the data in the main memory has not been updated. For example, when data in the main memory, corresponding to certain tag information whose state is dirty, is to be read, a write-back operation to write a dirty cache line to the main memory is performed, and correct data is sent to a request source processer after completing the write-back operation. 
     Further, in a multiprocessor system including multiple processors sharing a main memory, a cache coherency control method is proposed to read correct data even when a read request is targeted to data in which a write-back operation is being performed (see Patent Document 2, for example). In such a cache coherency control method, when a read request targeted to data in which a write-back operation is being performed is issued, on receiving a completion notice from a main memory indicating that the write-back operation is completed, a read request is again issued to the main memory. 
     The following is a reference document:
     [Patent Document 1] Japanese Laid-Open Patent Publication No. 8-185359,   [Patent Document 2] Japanese Laid-Open Patent Publication No. 10-161930.   

     SUMMARY 
     According to an aspect of the embodiments, a processing device includes multiple processing units and multiple memory devices respectively assigned to the multiple processing units. Each of the multiple processing units includes a process execution unit configured to perform an arithmetic operation, and a cache memory configured to retain data stored in the memory device assigned to a same processing unit in which the cache memory resides, and to retain fetched data taken out from the memory device of the processing unit other than the same processing unit. The cache memory includes a determination unit and a response information generation unit. When an access request of the fetched data is received from a source processing unit from which the fetched data has been taken out, the determination unit determines occurrence of a crossing in which the access request is received after the cache memory issues write back information instructing to write back the fetched data to the memory device assigned to the source processing unit. If the crossing has occurred, the response information generation unit outputs crossing information indicating that the crossing has occurred, as a response to the access request, to the source processing unit. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a diagram illustrating one embodiment of a processing system and a control method of the processing system; 
         FIG. 2  is a diagram illustrating an example of an operation of the processing system illustrated in  FIG. 1 ; 
         FIG. 3  is a diagram illustrating another embodiment of a processing system and a control method of the processing system; 
         FIG. 4  is a diagram illustrating an example of a secondary cache illustrated in  FIG. 3 ; 
         FIG. 5  is a diagram illustrating an example of an operation of the processing system illustrated in  FIG. 3 ; 
         FIG. 6  is a diagram illustrating an example of an operation of the processing system when a request crossing has occurred; 
         FIG. 7  is a diagram illustrating a comparative example of the secondary cache illustrated in  FIG. 4 ; and 
         FIG. 8  is a diagram illustrating an example of an operation of a processing system including the secondary cache illustrated in  FIG. 7 . 
     
    
    
     DESCRIPTION OF EMBODIMENT 
     Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. 
     One way to reduce power consumption of a processing system is, to reduce an area of a circuit other than a processor core, which does not undesirably affect processing performance. For example, by reducing an area of a circuit implementing cache coherency control, power consumption of a processing system can be reduced. 
     In one aspect, the present disclosure aims at reducing an area of a circuit corresponding to cache coherency control in a processing system, to reduce power consumption of the processing system. 
       FIG. 1  is a diagram illustrating one embodiment of a processing system and a control method of the processing system. The processing system  10  illustrated in  FIG. 1  is a processor such as a CPU (Central Processing Unit). The processing system  10  includes multiple computing nodes  100  ( 100   a ,  100   b , and  100   c ), multiple memory devices  400  ( 400   a ,  400   b , and  400   c ) respectively assigned to the computing nodes  100  ( 100   a ,  100   b , and  100   c ), and a bus  120  connecting the computing nodes  100 . In the following, a given memory device  400  assigned to a given computing node  100  may be referred to as a “(given) memory device  400  of a (given) computing node  100 ”. The multiple computing nodes  100  are an example of multiple processing units to which multiple memory devices  400  are assigned respectively. Note that the number of the computing nodes  100  is not limited to 3. 
     In  FIG. 1 , to distinguish each of the multiple computing nodes  100  in describing the processing systems  10  or the like, a reference number followed by a lower case letter of an alphabetic character (such as a, b, or c) is used as a reference symbol for each of the multiple computing nodes  100 . Also, with respect to a reference symbol assigned to each element included in the computing node  100 , a same alphabetic character as the alphabetic character assigned to the computing node  100  is attached as a suffix of the reference symbol. 
     Each of the computing nodes  100  includes a processor core  200  such as a CPU core performing an arithmetic operation, a cache memory  300 , and a memory device  400  for storing information such as data used by the processor core  200 . The processor core  200  is an example of a process execution unit performing arithmetic operation. 
     The cache memory  300  is accessible faster than the memory device  400 , and stores data used by the processor core  200  of the same computing node  100  in which the cache memory  300  resides (hereinafter, to specify a computing node among multiple computing nodes  100 , a computing node in which the cache memory  300  resides may be referred to as a “resident computing node”). Further, the cache memory  300  included in each of the computing nodes  100  is connected to the bus  120 , and each of the cache memories  300  is communicable with each other. For example, data stored in the memory device  400  of each computing node  100  is taken out to at least one of the other computing nodes  100  via the cache memory  300  and the bus  120 . The cache memory  300  of each computing node  100  manages status of data stored in the memory device  400  of the resident computing node  100 . Data stored in the memory device  400  has one of the following states: an exclusive state in which data is taken out to only one of the other computing nodes  100 , a shared state in which data is taken out to one or more of the other computing nodes  100  and data is not updated, an invalid state in which data is not taken out to the other computing nodes  100 , and the like. Note that the exclusive state does not necessarily mean that data is not updated. 
     As described above, the cache memory  300  stores data in the memory device  400  of the resident computing node  100  and fetched data that is taken out from the memory device  400  of the other computing nodes  100  among the multiple computing nodes  100 . That is, the cache memory  300  retains data that is stored in one of the multiple memory devices  400 . 
     When a read request for reading out data is received from the processor core  200 , the cache memory  300  transmits data requested by the read request to the processor core  200 . When the data requested by the read request is not stored in the cache memory  300  (when cache miss has occurred in the cache memory  300 ), the cache memory  300  issues a read request to the memory device  400  or the like. 
     For example, when the cache memory  300   a  receives a read request for reading data in the memory device  400   b  of another computing node  100   b , the cache memory  300   a  issues a read request to the cache memory  300   b  of the computing node  100   b  via the bus  120 . Subsequently, if data requested by the read request from the computing node  100   a  is not in the cache memory  300   b , the cache memory  300   b  issues a read request to the memory device  400   b  of the computing node  100   b . As described above, the processor core  200   a  of the computing node  100   a  accesses the memory device  400   b  of the computing node  100   b  via the cache memory  300   a  of the computing node  100   a , the bus  120 , and the cache memory  300   b  of the computing node  100   b . In this case, data stored in the memory device  400   b  of the computing node  100   b  is transmitted to the processor core  200   a  of the computing node  100   a  via the cache memory  300   b  of the computing node  100   b , the bus  120 , and the cache memory  300   a  of the computing node  100   a.    
     Further, for example, when the cache memory  300   a  receives a read request for reading data that is taken out from the memory device  400   a  of the resident computing node  100   a  to only another computing node  100   c , the cache memory  300   a  issues a read request to the computing node  100   c  to which the requested data is taken out (hereinafter, a computing node to which requested data is taken out may be referred to as a “fetcher computing node”). For example, the cache memory  300   a  issues the read request to the cache memory  300   c  of the computing node  100   c  via the bus  120 . The data retained in the cache memory  300   c  of the computing node  100   c  is written back to the memory device  400   a  of the computing node  100   a  via the bus  120  and the cache memory  300   a  of the computing node  100   a . Also, the data written back to the memory device  400   a  of the computing node  100   a  is transmitted to the processor core  200   a  of the computing node  100   a.    
     When the cache memory  300  receives a read request for reading data that is not taken out from the memory device  400  of the resident computing node  100  to another computing node  100 , the cache memory  300  issues a read request to the memory device  400  of the resident computing node  100 . 
     As described above, a communication between multiple computing nodes  100  is performed via the cache memory  300  and the bus  120 . Further, data stored in any one of the memory devices  400  can be retained into any cache memories  300 . Therefore, each computing node  100  performs cache coherency control for maintaining data consistency (cache coherency) of data retained in each cache memory  300 . 
     For example, the cache memory  300  includes a determination unit  310  for determining if a request crossing occurs with respect to fetched data, and a response information generation unit  320  for generating crossing information based on a determination result of the determination unit  310 . An example of the request crossing includes the following case: after the cache memory  300  issues write back information instructing to write fetched data back to the memory device  400  of a computing node  100  from which the fetched data was taken out (hereinafter, the computing node from which the fetched data was taken out may be referred to as a “source computing node”), the cache memory  300  receives an access request for the fetched data. The access request mentioned here is a write request for writing data into the memory device  400 , or a read request. 
     For example, when the cache memory  300   a  receives, from the computing node  100   b , an access request for fetched data that is taken from the memory device  400   b  of the computing node  100   b , a determination unit  310   a  of the cache memory  300   a  determines if a request crossing has occurred or not. In this case, the determination unit  310   a  determines if the access request for the fetched data is received from the computing node  100   b  after write back information instructing to write the fetched data back to the memory device  400   b  of the computing node  100   b  has been issued to the computing node  100   b . For example, if the fetched data requested by the access request is not retained in the cache memory  300   a , the determination unit  310   a  determines that the request crossing has occurred. 
     As described above, when an access request for fetched data is received from a source computing node  100  of the fetched data, the determination unit  310  determines if a request crossing with respect to the fetched data has occurred. 
     When a request crossing with respect to fetched data has occurred, the response information generation unit  320  outputs crossing information indicating that the request crossing has occurred to a source computing node  100  of the fetched data, as a response to the access request. 
     For example, when the cache memory  300   b  receives, from the cache memory  300   a  of the computing node  100   a , the crossing information as a response to the access request with respect to fetched data that has been fetched to the computing node  100   a , the cache memory  300   b  recognizes that a request crossing has occurred. That is, the cache memory  300   b  of the computing node  100   b  recognizes that the latest data requested by the access request has been written back to the memory device  400   b  of the resident computing node  100   b . For example, in a case in which fetched data taken out from the memory device  400   b  to the computing node  100   a  is updated by the processor core  200   a , the fetched data stored in the memory device  400   b  does not match the latest fetched data retained by the cache memory  300   a . In this case, by writing the latest fetched data, which was updated by the processor core  200   a , back to the memory device  400   b , the memory device  400   b  stores the latest data updated by the processor core  200   a . Accordingly, the cache memory  300   b  of the computing node  100   b  reads the latest data (the data requested by the access request) written back from the computing node  100   a  from the memory device  400   b  of the resident computing node  100   b.    
     By performing the above process, the computing node  100  having received the crossing information reads out the fetched data (the data requested by the access request) that has been written back to the memory device  400  of the resident computing node  100 . Accordingly, even when a request crossing has occurred, cache coherency can be maintained. 
     As a possible approach for maintaining cache coherency without using crossing information, a configuration of a processing system having a replace buffer may exist. When fetched data is written back to a memory device  400  of a source computing node  100  of the fetched data, the fetched data to be written back and discarded from the cache memory is retained in the replace buffer. When a request crossing occurs with respect to the fetched data to be written back, the cache memory transmits the fetched data retained in the replace buffer to a computing node  100  of an access request source. Because of the above operation, even when a request crossing occurs, cache coherency can be maintained. In a configuration in which the replace buffer is added, a size of a circuit of the processing system becomes larger than the processing system  10  implementing cache coherency control without using a replace buffer. In other words, the processing system  10  implementing cache coherency control using crossing information can prevent a size of a circuit from increasing. Accordingly, the processing system  10  can reduce a size of the circuit. 
     Note that the configuration of the processinq system  10  is not limited to the configuration illustrated in  FIG. 1 . For example, the computing node  100  (processing unit) does not necessarily include the memory device  400 . That is, the multiple memory devices  400  that are to be assigned to the multiple computing nodes  100  respectively may be disposed outside the computing nodes  100  or the processing system  10 . Also, in each of the computing nodes  100 , another cache memory other than the cache memory  300  may be disposed between the processor core  200  and the cache memory  300 . 
       FIG. 2  is a diagram illustrating an example of an operation of the processing system  10  illustrated in  FIG. 1 . The operation illustrated in  FIG. 2  is an aspect of a control method of the processing system. The operation illustrated in  FIG. 2  is an example of an operation of a computing node  100  when accessing fetched data that is taken out to another computing node  100 .  FIG. 2  illustrates the operation of the computing nodes  100   a  and  100   b  in a case in which an access request, targeted to fetched data taken out from the computing node  100   b  to the computing node  100   a , is issued from the computing node  100   b  to the computing node  100   a . In this case, a computing node  100  acting as an access request receiver is the computing node  100   a , and a computing node  100  acting as an access request issuer is the computing node  100   b . First, the operation of the access request receiver, which is the computing node  100   a , will be described. 
     At step S 10 , the cache memory  300   a  of the computing node  100   a  receives an access request, targeted to fetched data taken out from the computing node  100   b , from the cache memory  300   b  of the source computing node  100   b  of the fetched data. 
     Next, at step S 12 , the determination unit  310   a  of the cache memory  300   a  determines if a request crossing has occurred. For example, when write back information instructing to write the fetched data back to the memory device  400   b  has been output to the computing node  100   b  before receiving the access request targeted to the fetched data from the computing node  100   b , the determination unit  310   a  determines that a request crossing has occurred. 
     As describe above, when the access request targeted to the fetched data is received from the computing node  100   b  from which the fetched data is taken out, the determination unit  310   a  determines if a request crossing has occurred. If a request crossing has occurred, that is, if the fetched data has already been discarded from the cache memory  300   a , the operation of the computing node  100   a  proceeds to step S 16 . If a request crossing has not occurred, that is, if the cache memory  300   a  retains the fetched data, the operation of the computing node  100   a  proceeds to step S 14 . 
     At step S 14 , the cache memory  300   a  outputs the fetched data that is retained in the cache memory  300   a  (which is a request data requested by the access request) to the source computing node  100   b , as a response to the access request of the fetched data. Next, the cache memory  300   a  discards the fetched data sent to the computing node  100   b , from the cache memory  300   a , and the process of the computing node  100   a  having received the access request targeted to the fetched data from the computing node  100   b  terminates. Because a request crossing has not occurred at step S 14 , cache coherency is maintained. 
     At step S 16 , the response information generation unit  320   a  of the cache memory  300   a  outputs crossing information indicating that a request crossing has occurred to the source computing node  100   b , as a response to the access request of the fetched data. And, the process of the computing node  100   a  having received the access request with respect to the fetched data from the computing node  100   b  terminates. Next, the operation of the access request issuer, which is the computing node  100   b , will be described. 
     At step S 20 , the cache memory  300   b  of the computing node  100   b  issues an access request, targeted to fetched data taken out from the resident computing node  100   b , to the fetcher computing node  100   a  to which the fetched data is taken out. 
     Next, at step S 22 , the cache memory  300   b  receives a response to the access request for the fetched data from the computing node  100   a  which is a destination of the access request. 
     Next, at step S 24 , the cache memory  300   b  determines if the response to the access request is crossing information or not. If the response to the access request is crossing information, the operation of the computing node  100   b  proceeds to step S 26 . If the response to the access request is not crossing information, that is, if the computing node  100   b  receives the fetched data (request data) as the response to the access request, the process of the computing node  100   b  with respect to the access request terminates. 
     At step S 26 , the cache memory  300   b  reads out the fetched data (the latest request data) that has been written back from the computing node  100   a  to the memory device  400   b  of the resident computing node  100   b . Accordingly, because the cache memory  300   b  of the computing node  100   b  can access correct data even when a request crossing has occurred, cache coherency can be maintained. Note that the operation of the processing system  10  is not limited to the example illustrated in  FIG. 2 . 
     As described above, in the embodiment illustrated in  FIG. 1  and  FIG. 2 , the determination unit  310  of the cache memory  300  determines if a request crossing with respect to fetched data has occurred. Also, the response information generation unit  320  of the cache memory  300  outputs crossing information indicating that a request crossing has occurred to a computing node  100  of an access request issuer (that is, a source computing node  100  of the fetched data). As the above operation is performed, the computing node  100  of an access request issuer can recognize that a request crossing has occurred with respect to data requested by the access request, and can read the latest data (correct data) from the memory device  400  of the same computing node  100 . As a result, cache coherency can be maintained even when a request crossing has occurred. 
     Further, by performing cache coherency control using crossing information, a size of a circuit for cache coherency control can be reduced as compared to a case in which a replace buffer is used for cache coherency control. That is, a size of a circuit of the processing system  10  supporting cache coherency control can be reduced. Also, because a size of a circuit for cache coherency control is reduced, power consumption of the processing system  10  can be reduced. Also, because a size of a circuit for cache coherency control is reduced, a manufacturing cost of the processing system  10  can be reduced. 
       FIG. 3  is a diagram illustrating another embodiment of a processing system and a control method of the processing system. With respect to the same element as that illustrated in  FIG. 1 , or with respect to the similar element to that illustrated in  FIG. 1 , the same or similar reference symbol is attached, and the detailed description of the element will be omitted. A processing system  12  illustrated in  FIG. 3  is a processor such as a CPU. The processing system  12  includes multiple computing nodes  102  ( 102   a ,  102   b , and  102   c ), multiple memory devices  400  ( 400   a ,  400   b , and  400   c ) respectively assigned to the computing nodes  102  ( 102   a ,  102   b , and  102   c ), a bus  120  connecting to the multiple computing nodes  102 , and a bus controller  122 . In the following, a given memory device  400  assigned to a given computing node  102  may be referred to as a “(given) memory device  400  of a (given) computing node  102 ”. The multiple computing nodes  102  are an example of multiple processing units to which multiple memory devices  400  are assigned respectively. Note that the number of the computing nodes  102  is not limited to 3. 
     In  FIG. 3 , similar to  FIG. 1 , to distinguish each of the multiple computing nodes  102  in describing the processing systems  12  or the like, a reference number followed by a lower case letter of an alphabetic character (such as a, b, or c) is used for each of the multiple computing nodes  102 . Also, with respect to a reference symbol assigned to each element included in the computing node  102 , a same alphabetic character as the alphabetic character assigned to the computing node  102  is attached as a suffix of the reference symbol. 
     Each of the computing nodes  102  includes a core  202  that includes a processor core  210  such as a CPU core performing an arithmetic operation and a primary cache  220 , a secondary cache  302 , and a memory device  400  for storing information such as data used by the processor core  210 . The processor core  210  is an example of a process execution unit performing arithmetic operation. The secondary cache  302  is an example of a cache memory retaining data stored in the memory device  400  of the resident computing node  102  and retaining fetched data that is taken out from the memory device  400  of the other computing nodes  102  among the multiple computing nodes  102 . 
     The primary cache  220  and the secondary cache  302  are accessible faster than the memory device  400 , and stores data used by the processor core  210  of the resident computing node  102 . For example, the primary cache  220  is accessible faster than the secondary cache  302 , and is placed between the processor core  210  and the secondary cache  302 . The primary cache  220  retains part of data retained in the secondary cache  302 , and transmits the data requested by an access request received from the processor core  210 . When the data requested by the access request is not retained in the primary cache  220  (when cache miss has occurred in the primary cache  220 ), the primary cache  220  transfers the access request to the secondary cache  302 . 
     The secondary cache  302  has a larger capacity than the primary cache  220 , and is placed between the primary cache  220  and the memory device  400 . Further, the secondary cache  302  included in each of the computing nodes  100  is connected to the bus  120 , and each of the secondary caches  302  is communicable with each other. For example, data stored in the memory device  400  of each computing node  102  is taken out to at least one of the other computing nodes  102  via the secondary cache  302  and the bus  120 . The secondary cache  302  of each computing node  102  manages status (such as an exclusive state, a shared state, or an invalid state) of data stored in the memory device  400  of the resident computing node  102 . 
     As described above, the secondary cache  302  retains data that is stored in one of the multiple memory devices  400 . An operation performed by the secondary cache  302  is the same as, or similar to, that of the cache memory  300  illustrated in  FIG. 1 . For example, in the above description of the cache memory  300  in  FIG. 1 , if the computing node  100 , the cache memory  300 , and the processor core  200  are respectively deemed to be replaced with the computing node  102 , the secondary cache  302 , and the core  202 , an outline of the operation of the secondary cache  302  can be described. Note that details of the secondary cache  302  will be described below with reference to  FIG. 4 . 
     The bus controller  122  controls transmission of information or the like via the bus  120  from each secondary cache  302  to another secondary cache  302 , by controlling the bus  120 . For example, the bus controller  122  controls the bus  120  such that write back information and crossing information that are directed to a source computing node  102  of fetched data can be delivered to the source computing node  102  in the same order as an order when the write back information and the crossing information are output. The write back information is information instructing to write fetched data back to the memory device  400  of a source computing node  102  of the fetched data, as explained in the description of  FIG. 1 . The crossing information is information indicating occurrence of a crossing in which the secondary cache  302  receives an access request to the fetched data after issuing write back information. 
     Note that the configuration of the processing system  12  is not limited to the configuration illustrated in  FIG. 3 . For example, the computing node  102  (processing unit) does not necessarily include the memory device  400 . That is, the multiple memory devices  400  that are to be assigned to the multiple computing nodes  102  respectively may be disposed outside the computing nodes  102  or the processing system  12 . Also, in each of the computing nodes  102 , another cache memory other than the primary cache  220  and the secondary cache  302  may be disposed between the primary cache  220  and the secondary cache  302 . Alternatively, the primary cache  220  may be omitted. 
       FIG. 4  is a diagram illustrating an example of the secondary cache  302  illustrated in  FIG. 3 . Also in  FIG. 4 , an example of a packet transmitted or received by the secondary cache  302  is illustrated in brackets. The secondary cache  302  includes a local port  330 , a remote port  340 , a selection unit  350 , a pipeline unit  360 , a data retention unit  370 , and tag units  380  and  390 . 
     The local port  330  receives a request such as an access request from a resident computing node  102 . The remote port  340  receives a request such as an access request from other computing nodes  102 . The selection unit  350  selects a request received from either the local port  330  or the remote port  340 , and passes the selected request to the pipeline unit  360 . 
     The pipeline unit  360  includes a pipeline processing unit  362  performing a pipeline processing, and a pipeline control unit  364  controlling the pipeline processing unit  362 . The pipeline processing unit  362  performs processes related to a request received from the selection unit  350  sequentially with multiple stages. 
     The pipeline control unit  364  includes a determination unit  310  and a response information generation unit  320 . The determination unit  310  and the response information generation unit  320  are the same as, or similar to, the determination unit  310  and the response information generation unit  320  illustrated in  FIG. 1 . For example, when the determination unit  310  receives an access request to fetched data from a source computing node  102  of the fetched data, the determination unit  310  determines if a request crossing with respect to the fetched data has occurred. The response information generation unit  320  outputs information representing a response to a request such as an access request, to an issuer of the request such as the computing node  102 . For example, when a request crossing with respect to fetched data has occurred, the response information generation unit  320  outputs crossing information indicating that a request crossing has occurred to a source computing node  102  of the fetched data, as a response to an access request. A symbol REQID in  FIG. 4  represents a request such as an access request, or information such as a response to a request (crossing information, or completion information representing a process completion of a process related to a request), and a symbol PA represents a target address of a target of a request (such as an address of request data). 
     The data retention unit  370  retains data used by the processor core  210  of a resident computing node  102 . For example, the data retention unit  370  retains data stored in one of the multiple memory devices  400 . A symbol DATA in  FIG. 4  represents data such as request data requested by an access request. The secondary cache  302  sends or receives a packet that includes the information REQID, the target address PA, and the data DATA, as illustrated in the brackets of  FIG. 4 . However, when the data DATA is not required to be sent, such as when a response is to be sent, the data DATA may be omitted from the packet. In the following, the packet that is sent or received by the secondary cache  302  may be called by a name of information specified by the information REQID (access request, crossing information, completion information, or the like). 
     The tag unit  380  retains information representing status of data retained in the data retention unit  370 . In MESI protocol, data is categorized into the following four states: “Modified”, “Exclusive”, “Shared”, and “Invalid”. For example, a state of dirty data updated by the processor core  210  or the like of a resident computing node  102  is categorized as “Modified”. Further, a state of clean data not having been updated that is retained in one of the multiple secondary caches  302  is categorized as “Exclusive”. Further, a state of clean data retained in the multiple secondary caches  302  is categorized as “Shared”. 
     The tag unit  390  retains information representing status (such as an exclusive state, a shared state, or an invalid state) of data stored in the memory device  400  of a resident computing node  102 . As mentioned in the description of  FIG. 1 , the exclusive state does not necessarily mean that data is not updated. That is, with respect to a state of data stored in the memory device  400 , the exclusive state includes the “Modified” state in MESI protocol. 
       FIG. 5  is a diagram illustrating an example of an operation of the processing system  12  illustrated in  FIG. 3 . The operation illustrated in  FIG. 5  is an aspect of a control method of the processing system. The operation illustrated in  FIG. 5  is an example of an operation of the secondary cache  302  that has received an access request from either a resident computing node  102  or one of the other computing nodes  102 . Every time the secondary cache  302  receives an access request, the secondary cache  302  performs step S 100  and thereafter. 
     At step S 100 , the pipeline unit  360  searches the tag unit  380  to determine if the data retention unit  370  retains request data requested by the access request. 
     Next, at step S 200 , the pipeline unit  360  determines if a cache hit occurs in the secondary cache  302 . If the cache hit occurs in the secondary cache  302 , that is, if the data retention unit  370  retains the request data, the operation of the secondary cache  302  proceeds to step S 210 . On the other hand, if a cache miss occurs in the secondary cache  302 , that is, if the data retention unit  370  does not retain the request data, the operation of the secondary cache  302  proceeds to step S 300 . 
     At step S 210 , the pipeline unit  360  determines if the access request to be processed is received from the local port  330  or not. If the access request to be processed is an access request received from the local port  330 , that is, if the access request to be processed is an access request received from the resident computing node  102 , the operation of the secondary cache  302  proceeds to step S 220 . If the access request to be processed is an access request received from the remote port  340 , that is, if the access request to be processed is an access request received from another computing node  102 , the operation of the secondary cache  302  proceeds to step S 230 . 
     At step S 220 , the secondary cache  302  issues completion information containing request data that is read out from the data retention unit  370 , to the resident computing node  102  (a computing node  102  that has issued the access request). Note that the completion information is a response to the access request, and indicates a completion of a process related to the access request. 
     As described above, the secondary cache  302  outputs the request data retained in the data retention unit  370  to the core  202  of the resident computing node  102  if the data retention unit  370  retains the request data requested by the access request from the resident computing node  102 , and terminates the process. 
     At step S 230 , the secondary cache  302  issues completion information containing the request data that is read out from the data retention unit  370 , to the computing node  102  which is a source of the access request (another computing node  102 ). If the access request is a read request or the like for exclusively reading data, the secondary cache  302  discards the request data from the data retention unit  370 . 
     When step S 230  is completed, the operation of the secondary cache  302 , in a case in which the data retention unit  370  retains request data requested by an access request from another computing node  102 , terminates. If request data is not retained in the data retention unit  370 , step S 300  is executed, as mentioned above. 
     At step S 300 , the pipeline unit  360  determines if the access request to be processed is received from the local port  330  or not. If the access request to be processed is an access request received from the local port  330 , that is, if the access request to be processed is an access request received from the resident computing node  102 , the operation of the secondary cache  302  proceeds to step S 310 . If the access request to be processed is an access request received from the remote port  340 , that is, if the access request to be processed is an access request received from another computing node  102 , the operation of the secondary cache  302  proceeds to step S 400 . 
     At step S 310 , the secondary cache  302  issues a read request for reading the request data requested by the access request, to the memory device  400  of the resident computing node  102  or to another computing node  102 . For example, the secondary cache  302  issues a read request for the request data to the memory device  400  of the resident computing node  102  if the request data is stored in the memory device  400  of the resident computing node  102 . However, if the request data is taken out from the memory device  400  of the resident computing node  102  to another computing node  102 , the secondary cache  302  issues a read request for the request data to the computing node  102  to which the request data is taken out. Further, if the request data is stored in the memory device  400  in another computing node  102 , the secondary cache  302  issues a read request for the request data to a computing node  102  managing the request data (another computing node  102 ). 
     The secondary cache  302  obtains the request data by performing step S 310 . Subsequently, the secondary cache  302  sends the obtained request data to the core  202  of the resident computing node  102 , and terminates the process. 
     At step S 400 , the secondary cache  302  (or more precisely, the determination unit  310 ) determines if a request crossing has occurred or not. For example, if the request data is data that should be stored in the memory device  400  of another computing node  102 , the request data is fetched data taken out from the memory device  400  of another computing node  102 . If the request data is not retained in the data retention unit  370  despite the request data being fetched data, it means that the request data is discarded from the secondary cache  302  before the secondary cache  302  receives the access request. That is, if the request data is not retained in the data retention unit  370  despite the request data being fetched data, it means that a request crossing has occurred. Therefore, if the request data is data that should be stored in the memory device  400  of another computing node  102 , the determination unit  310  determines that a request crossing has occurred. 
     When the request crossing has occurred, the operation of the computing node  102  proceeds to step S 420 . When the request crossing does not occur, the operation of the computing node  102  proceeds to step S 410 . 
     At step S 410 , the secondary cache  302  issues a read request for reading the request data requested by the access request, to the memory device  400  of the resident computing node  102 . That is, the secondary cache  302  reads out the request data from the memory device  400  of the resident computing node  102 . Subsequently, the secondary cache  302  outputs the request data that was read from the memory device  400  of the resident computing node  102  to the computing node  102  from which the access request was issued, and terminates the process. 
     At step S 420 , the secondary cache  302  (or more precisely, the response information generation unit  320 ) issues crossing information indicating that a request crossing has occurred, to the computing node  102  from which the access request was issued, and terminates the process. When a request crossing occurs, request data is fetched data. Accordingly, the computing node  102  from which the access request was issued is a source computing node  102  of the request data (fetched data). 
     The computing node  102  having received the crossing information reads out the fetched data (data requested by the access request) that was written back to the memory device  400  of the resident computing node  102 , as illustrated in  FIG. 6 . As a result, cache coherency can be maintained even when a request crossing has occurred. Note that the operation of the processing system  12  is not limited to the example illustrated in  FIG. 5 . 
       FIG. 6  is a diagram illustrating an example of an operation of the processing system  12  when a request crossing has occurred. In the example illustrated in  FIG. 6 , request data to be accessed is, data stored at address A of the memory device  400   a  of the computing node  102   a , and data stored at address B of the memory device  400   a  of the computing node  102   a . The computing node  102   a  storing the request data in the memory device  400  of the computing node  102   a  (memory device  400   a ) is a memory management node of the request data at address A and address B, and may be referred to as home. A computing node  102  including a secondary cache  302  from which a request such as an access request is issued may be referred to as local. Further, a computing node  102  which is not local may be referred to as remote. The local computing node  102  may serve as a home computing node  102 . Further, a remote computing node  102  may serve as a home computing node  102 . 
     First, the pipeline unit  360  of the computing node  102   b  (local) receives a read request READ[B] for reading data at address B, from the resident computing node  102   b . Next, the pipeline unit  360  of the computing node  102   b  requests the tag unit  380  of the resident computing node  102   b  to read data at address B ((P 10 ) in  FIG. 6 ). 
     Because the data retention unit  370  of the computing node  102   b  does not retain data at address B, a cache miss occurs in the secondary cache  302   b  of the computing node  102   b  ((P 11 ) in  FIG. 6 ). Therefore, the secondary cache  302   b  of the computing node  102   b  issues the read request READ[B] to the computing node  102   a  (home). 
     The pipeline unit  360  of the computing node  102   a  (home) receives the read request READ[B] from the computing node  102   b  ((P 12 ) in  FIG. 6 ). Subsequently, the pipeline unit  360  of the computing node  102   a  (home) performs data read at address B, and outputs read completion information including data at address B (RCPLT[B]) to the computing node  102   b.    
     The pipeline unit  360  of the computing node  102   b  stores the data at address B included in the read completion information RCPLT[B] into the data retention unit  370  of the resident computing node  102   b  ((P 13 ) in  FIG. 6 ). 
     When there is no free area for storing data in the data retention unit  370  of the computing node  102   b , the pipeline unit  360  of the computing node  102   b  performs write-back operation to write data back to the memory device  400  before receiving the read completion information RCPLT[B], in order to allocate free area. In the example illustrated in  FIG. 6 , the pipeline unit  360  of the computing node  102   b  issues write back information WRKB[A] to instruct to write data at address A back to the memory device  400   a  of the computing node  102   a  (home) ((P 20 ) in  FIG. 6 ). 
     In response to an issuance of the write back information, the tag unit  380  of the computing node  102   b  performs write-back operation of data at address A ((P 21 ) in  FIG. 6 ). As a result, the data at address A is discarded from the data retention unit  370  of the computing node  102   b  (local), and is written back to the memory device  400   a  of the computing node  102   a  (home) ((P 22 ) in  FIG. 6 ). For example, when the data at address A is in dirty state, write back information WRKB[A] including the data at address A is output from the computing node  102   b  to the computing node  102   a . When the data at address A is in clean state, write back information WRKB[A] not including the data at address A may be issued from the computing node  102   b  to the computing node  102   a.    
     Further, in the example illustrated in  FIG. 6 , the pipeline unit  360  of the computing node  102   a  receives a read request READ[A] for exclusively reading data at address A from the core  202   a  of the resident computing node  102   a , before receiving the write back information WRKB[A] from the computing node  102   b . Though the data at address A is discarded from the secondary cache  302   b  of the computing node  102   b , the write back information WRKB[A] has not arrived at the computing node  102   a . Therefore, the computing node  102   a  recognizes that the data at address A is retained in the secondary cache  302   b  of the computing node  102   b , and the pipeline unit  360  of the computing node  102   a  issues a read request READ[A] for exclusively reading the data at address A to the computing node  102   b  ((P 30 ) in  FIG. 6 ). 
     When the computing node  102   a  accesses the data at address A that was taken out to another computing node  102   b , in order to avoid occurrence of inconsistency, the pipeline unit  360  of the computing node  102   a  (home) prohibits update of a content at address A of the memory device  400   a  by acquiring lock, until a response is returned ((P 31 ) in  FIG. 6 ). However, data update by the write back information WRKB[A] is allowed even while the lock is being acquired. Accordingly, as mentioned above, the data at address A that was discarded from the data retention unit  370  of the computing node  102   b  (local) is written back to the memory device  400   a  of the computing node  102   a  (home) ((P 22 ) in  FIG. 6 ). 
     The pipeline unit  360  of the computing node  102   b  having received the read request READ[A] from the computing node  102   a  requests the tag unit  380  of the resident computing node  102   b  to read data at address A ((P 32 ) in  FIG. 6 ). However, because the data at address A has already been discarded from the data retention unit  370  of the computing node  102   b , by the write-back operation for writing the data at address A back to the memory device  400   a , a cache miss occurs in the secondary cache  302   b  of the computing node  102   b  ((P 32 ) in  FIG. 6 ). 
     Because the cache miss has occurred despite the request data requested by the read request READ[A] being fetched data taken out from the memory device  400   a  of the computing node  102   a , the secondary cache  302   b  of the computing node  102   b  determines that a request crossing has occurred. Accordingly, the secondary cache  302   b  of the computing node  102   b  issues, to the computing node  102   a , crossing information RCPLTcrs[A] indicating that a request crossing has occurred, as a response to the read request READ[A]. 
     As described above, when the secondary cache  302   b  receives the read request READ[A] from the computing node  102   a  after issuing the write back information WRKB[A] to the computing node  102   a , the secondary cache  302   b  issues the crossing information RCPLTcrs[A] to the computing node  102   a . The pipeline unit  360  of the computing node  102   a  (home) receives the crossing information RCPLTcrs[A] from the computing node  102   b  ((P 33 ) in  FIG. 6 ). By receiving this information, the lock for prohibiting data update of address A is released. 
     Further, the pipeline unit  360  of the computing node  102   a  having received the crossing information RCPLTcrs[A] recognizes that the latest data at address A requested by issuing the read request READ[A] has been written back to the memory device  400   a  of the resident computing node  102   a . Accordingly, the pipeline unit  360  of the computing node  102   a  reads the data at address A that was written back to the memory device  400   a  of the resident computing node  102   a . For example, the pipeline unit  360  of the computing node  102   a  issues the read request READ[A] to the memory device  400   a  of the resident computing node  102   a  ((P 34 ) in  FIG. 6 ). Next, the pipeline unit  360  of the computing node  102   a  receives read completion information RCPLT[A] including the data at address A ((P 35 ) in  FIG. 6 ). By this operation, the data at address A is stored in the secondary cache  302   a  of the computing node  102   a . Then, the secondary cache  302   a  of the computing node  102   a  transmits the data at address A to the core  202   a  of the resident computing node  102   a , and the process terminates. 
     As described above, even when a crossing, such as an event in which the secondary cache  302   b  receives a read request READ[A] after the secondary cache  302   b  issues write back information WRKB[A] to the computing node  102   a , has occurred, cache coherency can be maintained. That is, even when a request crossing has occurred, by using crossing information RCPLTcrs, cache coherency can be maintained without using a replace buffer  372 EX or the like illustrated in  FIG. 7 . 
     Suppose that the write back information WRKB[A] was overtaken by the crossing information RCPLTcrs[A]. In this case, after pre-updated data is read out from the memory device  400   a , the latest data that was updated by the computing node  102   b  is written back to the memory device  400   a , which means that cache coherency cannot be maintained. Therefore, the bus controller  122  prevents the write back information WRKB[A] from being overtaken by the crossing information RCPLTcrs[A], by controlling transmission of the write back information WRKB[A] and the crossing information RCPLTcrs[A] on the bus  120 . By this control, occurrence of an event, in which pre-updated data at address A is read out from the memory device  400   a  before the latest data at address A is written back to the memory device  400   a , can be prevented. That is, cache coherency can be maintained. 
     The read completion information RCPLT, the crossing information RCPLTcrs, and the like, are information of a type for sending a notification to a requestor that a process concerning a request such as read request READ has been completed. Though the write back information WRKB is information of a type for instructing to write back, the response information generation unit  320  generates the write back information WRKB as information of the same type as the crossing information RCPLTcrs. Since the write back information WRKB and the crossing information RCPLTcrs are in the same type, the bus controller  122  controls transmission of the above information such that the write back information WRKB[A] and the crossing information RCPLTcrs[A] are delivered in the same order as the order in which the write back information WRKB[A] and the crossing information RCPLTcrs[A] are issued. By this control, occurrence of an event in which the write back information WRKB[A] is overtaken by the crossing information RCPLTcrs[A] can be prevented, and therefore, cache coherency can be maintained. 
       FIG. 7  is a diagram illustrating a comparative example of the secondary cache  302  illustrated in  FIG. 4 . In  FIG. 7 , a replace buffer  372 EX is added to the secondary cache  302  illustrated in  FIG. 4 . Also, the secondary cache  302 EX includes a pipeline unit  360 EX, a data retention unit  370 EX, and tag unit  380 EX, instead of the pipeline unit  360 , the data retention unit  370 , and the tag unit  380 . Other configurations of the secondary cache  302 EX are the same as or similar to the configurations of the secondary cache  302  illustrated in  FIG. 4 . With respect to the elements same as or similar to those illustrated in  FIG. 4 , same or similar reference symbols are attached, and detailed description of those elements will be omitted. 
     The secondary cache  302 EX includes a local port  330 , a remote port  340 , a selection unit  350 , the pipeline unit  360 EX, the data retention unit  370 EX, the replace buffer  372 EX, the tag unit  380 EX, and a tag unit  390 . The local port  330  receives a request such as an access request from a resident computing node  102 . The remote port  340  receives a request such as an access request from other computing nodes  102 . The selection unit  350  selects a request received from either the local port  330  or the remote port  340 , and passes the selected request to the pipeline unit  360 EX. 
     The pipeline unit  360 EX includes a pipeline processing unit  362 EX performing a pipeline processing, a pipeline control unit  364 EX controlling the pipeline processing unit  362 EX, and a cancel flag FLG indicating whether write-back is cancelled or not. The pipeline processing unit  362 EX performs processes related to a request received from the selection unit  350  sequentially with multiple stages. 
     The pipeline control unit  364 EX does not include the determination unit  310  illustrated in  FIG. 4 . Further, the pipeline control unit  364 EX includes a response information generation unit  320 EX for outputting information (REQID, PA) representing a response to a request such as an access request, to a requestor such as the computing node  102 , instead of the response information generation unit  320  illustrated in  FIG. 4 . 
     The data retention unit  370 EX retains data used by the processor core  210  of a resident computing node  102 , and outputs data DATA requested by an access request or the like. 
     When fetched data in the data retention unit  370 EX is to be written back to the memory device  400  of a source computing node  102 , the replace buffer  372 EX retains the fetched data that is to be discarded from the data retention unit  370 EX until the fetched data is written back to the memory device  400 . 
     The tag unit  380 EX retains information representing status of data retained in the data retention unit  370 EX. The tag unit  390  retains information representing status of data stored in the memory device  400  of a resident computing node  102 . 
     If a write-back request of fetched data and an access request for the fetched data cross, the secondary cache  302 EX transmits the fetched data retained in the replace buffer  372 EX to a computing node  102  from which the access request was issued. Because of the operation, cache coherence can be maintained even when a request crossing has occurred. 
       FIG. 8  is a diagram illustrating an example of an operation of a processing system including the secondary cache  302 EX illustrated in  FIG. 7 . In the example illustrated in  FIG. 8 , data at address A and data at address B, which are data to be accessed, are data stored in the memory device  400   a  of the computing node  102   a , similar to  FIG. 6 . 
     Operations for reading data at address B based on a read request READ[B] are the same as or similar to the operations illustrated in  FIG. 6  ((P 10 ), (P 11 ), (P 12 ), and (P 13 ) in  FIG. 8 ). 
     To allocate free area, the pipeline unit  360 EX of the computing node  102   b  issues write back information WRKB[A] to instruct to write data at address A back to the memory device  400   a  of the computing node  102   a  (home) ((P 40 ) in  FIG. 8 ). In response to the operation, the tag unit  380 EX of the computing node  102   b  performs write-back operation of data at address A ((P 41 ) in  FIG. 8 ). As a result, the data at address A is discarded from the data retention unit  370 EX of the computing node  102   b  (local), and is written to the replace buffer  372 EX of the computing node  102   b  ((P 42 ) in  FIG. 8 ). 
     Further, when the data at address A is in dirty state, the computing node  102   a  receives write back information WRKB[A] including the data at address A from the computing node  102   b  to the computing node  102   a  ((P 43 ) in  FIG. 8 ). When the data at address A is in clean state, write back information WRKB[A] not including the data at address A may be issued from the computing node  102   b  to the computing node  102   a . In the example illustrated in  FIG. 8 , the write back information WRKB[A] is generated as a type of information for instructing to write back, which is categorized to a different type from information such as read completion information RCPLT[A] for notifying a requestor that a process concerning a request has been completed. 
     Further, similar to  FIG. 6 , the pipeline unit  360  of the computing node  102   a  receives a read request READ[A] for exclusively reading data at address A from the core  202   a  of the resident computing node  102   a , before receiving the write back information WRKB[A] from the computing node  102   b . Though the data at address A is discarded from the secondary cache  302 EX of the computing node  102   b , the write back information WRKB[A] has not arrived at the computing node  102   a . Accordingly, the computing node  102   a  recognizes that the data at address A is retained in the secondary cache  302 EX of the computing node  102   b.    
     Therefore, the pipeline unit  360 EX of the computing node  102   a  issues a read request READ[A] for exclusively reading the data at address A to the computing node  102   b  ((P 50 ) in  FIG. 8 ). Similar to  FIG. 6 , the pipeline unit  360 EX of the computing node  102   a  prohibits update of a content at address A by acquiring lock, until a response is returned ((P 51 ) in  FIG. 8 ). Further, the pipeline unit  360 EX of the computing node  102   a  receives the write back information WRKB[A] generated as a type of information for process instruction while the lock is acquired ((P 43 ) in  FIG. 8 ). Accordingly, the pipeline unit  360 EX of the computing node  102   a  does not perform write-back operation of the data at address A, and waits until the lock is released. 
     The pipeline unit  360 EX of the computing node  102   b  having received the read request READ[A] from the computing node  102   a  requests the tag unit  380 EX of the resident computing node  102   b  to read data at address A. Because the data at address A has already been discarded from the data retention unit  370 EX of the computing node  102   b , by the write-back operation for writing the data at address A, a cache miss occurs in the secondary cache  302 EX of the computing node  102   b  ((P 52 ) in  FIG. 8 ). 
     As described above, the data at address A has been written to the replace buffer  372 EX of the computing node  102   b  ((P 42 ) in  FIG. 8 ). Therefore, the secondary cache  302 EX of the computing node  102   b  outputs the data at address A, retained in the replace buffer  372 EX of the resident computing node  102   b , to the computing node  102   a  as read completion information RCPLT[A] ((P 53 ) in  FIG. 8 ). 
     The pipeline unit  360 EX of the computing node  102   a  having received the read completion information RCPLT[A] releases the lock for the data at address A ((P 54 ) in  FIG. 8 ). Further, the pipeline unit  360 EX of the computing node  102   a  sets a cancel flag FLG to “1” ((P 55 ) in  FIG. 8 ). 
     Because the cancel flag FLG is “1”, the pipeline unit  360 EX of the computing node  102   a  cancels the write-back operation (without performing the write-back operation) even if the lock is released ((P 44 ) in  FIG. 8 ). Further, the pipeline unit  360 EX of the computing node  102   a  sets a cancel flag FLG to “0” as the write-back operation was cancelled ((P 56 ) in  FIG. 8 ). The pipeline unit  360 EX of the computing node  102   a  also outputs, as a response to the write back information WRKB[A], write completion information WBCPLT[A] indicating that the write-back operation of the data at address A was cancelled, to the computing node  102   b.    
     The replace buffer  372 EX of the computing node  102   b  having received the write completion information WBCPLT[A] discards the data at address A. In response to the deletion, the operations of the computing nodes  102   a  and  102   b  terminate. 
     As described above, even when a request crossing had occurred, cache coherency can be maintained by transmitting request data from the replace buffer  372 EX to a requestor. On the other hand, if a secondary cache in which the replace buffer  372 EX is omitted from the secondary cache  302 EX were to be used, when a cache miss occurred in the secondary cache of the computing node  102   b  having received a read request READ[A], the secondary cache would not be able to return data to the computing node  102   a . Therefore in this case, a process flow concerning the read request READ[A] would stop, and cache coherency would not be maintained. Further, if a secondary cache in which the cancel flag FLG is omitted from the secondary cache  302 EX were to be used, a case might happen in which pre-update data at address is written-back after receiving read completion information RCPLT[A] including the latest data at address A. 
     If the secondary cache  302 EX having the replace buffer  372 EX and the cancel flag FLG is to be used, cache coherency can be maintained even when a request crossing has occurred. However, a size of a circuit of the secondary cache  302 EX becomes larger than the secondary cache  302  illustrated in  FIG. 4 . In other words, the processing system  12  implementing cache coherency control using crossing information RCPLTcrs can control against increase of a size of a circuit, as compared to the case in which the replace buffer  372 EX or the like is used. Accordingly, the processing system  12  can reduce a size of the circuit. 
     As described above, in the embodiment illustrated in  FIGS. 3 to 6 , effects similar to those described in the embodiment illustrated in  FIG. 1  and  FIG. 2  can be obtained. For example, the determination unit  310  of the secondary cache  302  determines if a request crossing with respect to fetched data has occurred. Also, the response information generation unit  320  of the secondary cache  302  outputs crossing information RCPLTcrs indicating that a request crossing has occurred to a computing node  102  of an access request source (that is, a source computing node  102  of the fetched data). As the above operation is performed, the computing node  102  of an access request source can recognize that a request crossing has occurred with respect to data requested by the access request, and can read the latest data (correct data) from the memory device  400  of its own computing node  102 . As a result, cache coherency can be maintained even when a request crossing has occurred. 
     Further, by performing cache coherency control using crossing information RCPLTcrs, a size of a circuit for cache coherency control can be reduced as compared to the case in which the replace buffer  372 EX is used for cache coherency control. That is, a size of a circuit of the processing system  12  supporting cache coherency control can be reduced. Also, because a size of a circuit for cache coherency control is reduced, power consumption of the processing system  12  can be reduced. Also, because a size of a circuit for cache coherency control is reduced, a manufacturing cost of the processing system  12  can be reduced. 
     Further, the bus controller  122  controls the bus  120  such that write back information WRKB and crossing information RCPLTcrs that are issued to a source computing node  102  (a computing node  102  from which fetched data is taken out) can be delivered to the source computing node  102  in the same order as an order when the write back information and the crossing information is output. By this control, occurrence of an event, in which pre-updated fetched data is read out from the memory device  400  before updated fetched data is written back to the memory device  400 , can be prevented. That is, cache coherency can be maintained. 
     According to the above detailed description, specific features and advantages of the embodiments will be made clear. This is intended so that claims extend to the above mentioned specific features and advantages of the embodiments without departing from the spirit and scope of the invention. Further, a person having ordinary skill in the art should be able to conceive various enhancements and alterations easily. Accordingly, the above embodiments are not intended to limit scope of inventive embodiments to the extent described in the above embodiments, but the scope may include an enhanced product or an equivalent product. 
     All examples and conditional language provided herein are intended for pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventors to further the art, and are not to be construed as limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.