Patent Publication Number: US-2023135424-A1

Title: Method of manufacturing semiconductor device

Description:
FIELD OF THE INVENTION 
     This invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device with improvement of solder joint reliability. 
     BACKGROUND OF THE INVENTION 
     In order to protect wires from oxidation, a surface treatment layer is usually provided on wires to isolate air surrounding the wires. Conventionally, the surface treatment layer is generated by electroless nickel immersion gold (ENIG) or electroless nickel electroless palladium immersion gold (ENEPIG) process. In ENIG process, nickel ions are reduced to metallic nickel by a reducing agent and the metallic nickel is deposited on copper wires to form a nickel layer, and then gold is deposited on the nickel layer by a displacement reaction, however, hydrogen bubble generated during nickel deposition may cause a problem of air pore. In ENEPIG process, metallic copper on surface of the wires is replaced by metallic palladium by chemical reaction, a nickel-phosphorus alloy layer is formed by electroless plating based on palladium core, and gold is deposited on the nickel-phosphorus alloy layer by displacement reaction. There is also a problem of air pore in the nickel layer after ENEPIG process, and the nickel-phosphorus alloy layer is usually over-etched during immersion gold plating to lower solder joint reliability. 
     SUMMARY 
     One object of the present invention is to provide a method of manufacturing a semiconductor device. A gold layer is coated on wires of package to protect the wires from oxidation and improve solder joint reliability. 
     A method of manufacturing a semiconductor device disclosed in the present invention includes the steps as follows. Firstly, a package including a first carrier, a seed layer, wires, a die and a molding material is provided, the seed layer is formed on the first carrier, the wires are formed on the seed layer, the die is bonded to the wires, the molding material is adapted to cover the die and the wires. Next, a second carrier is disposed on the molding material, the first carrier is removed to expose the seed layer, and the seed layer is removed to expose the wires. Finally, a gold layer is deposited on each of the wires by immersion gold plating. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a cross-section view diagram illustrating a package in accordance with a first embodiment of the present invention. 
         FIGS.  2  to  7    are cross-section view diagrams illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention. 
         FIGS.  8  and  9    are cross-section view diagrams illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. 
         FIGS.  10  and  11    are cross-section view diagrams illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention. 
         FIGS.  12  and  13    are cross-section view diagrams illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     With reference to  FIG.  1   , a package  100  is provided firstly in a method of manufacturing a semiconductor device of the present invention. The package  100  includes a first carrier  110  and a seed layer  120  which is formed on the first carrier  110 . Preferably, the first carrier  110  includes a first substrate  111  and a first release layer  112 , the first release layer  112  is formed on the surface of the first substrate  111 , and the seed layer  120  is formed on the first release layer  112 . The first substrate  111  may be a glass substrate, a silicon wafer or ceramic substrate, and the material of the first release layer  112  may be polyimide (PI) or inorganic release agent such as halogen-metal compound. The seed layer  120  may be a titanium-tungsten/copper (TiW/Cu) layer or a titanium/copper (Ti/Cu) layer, and preferably, the seed layer  120  is coated on the first release layer  112  by sputtering. 
     Referring to  FIG.  1    again, the package  100  further includes a plurality of wires  130 , at least one die  150  and a molding material  160 . The wires  130  are formed on the seed layer  120 , the die  150  is bonded to the wires  130 , and the molding material  160  covers the die  150  and the wires  130 . Preferably, the die  150  is bonded to the wires  130  through conventional flip-chip bonding technique, and the wires  130  are formed on the seed layer  120  using a patterned dielectric layer  140 . A dielectric layer is formed on the seed layer  120  and then etched to generate a plurality of openings which expose the seed layer  120 , and the wires  130  are formed in the openings. The material of the dielectric layer is polyimide, benzocyclobutene (BCB) or epoxy, and in this embodiment, the dielectric layer is made of polyimide. 
     In the first embodiment of the present invention, each of the wires  130  includes a nickel (Ni) layer  131  and a copper (Cu) layer  132 . The nickel layer  131  is formed on the seed layer  120  by pure nickel electroplating and is made of pure nickel without phosphorus (P), thus there is no issue of air pore-generation and phosphorus deposition in the nickel layer  131 , the porosity of the electroplated nickel layer  131  is lower than that of the electroless plated nickel layer, and the density of the electroplated nickel layer  131  is greater than that of the electroless plated nickel layer. The copper layer  132  is preferably a redistribution layer (RDL) formed on the nickel layer  131 . 
     With reference to  FIG.  2   , next, a carrier  200  is positioned on the molding material  160 . Preferably, the second carrier  200  includes a second substrate  210  and a second release layer  220 , the second substrate  210  is made of glass, silicon wafer, ceramic, stainless steel or silicon glue with glass fibers, and the second release layer  220  is made of pressure sensitive adhesive (PSA), epoxy or silicon glue. The first substrate  111  and the second substrate  210  can be made of the same or different materials. 
     With reference to  FIG.  3   , after positioning the second carrier  200  on the molding material  160 , the semiconductor device is turned upside down to allow the first carrier  110  to be located on the top of the semiconductor device and allow the second carrier  200  to be located on the bottom of the semiconductor device. Referring to  FIG.  4   , then, the first carrier  110  is removed to show the seed layer  120  located under the first carrier  110 . In the first embodiment, the first release layer  112  is separated from the seed layer  120  by mechanical debonding so as to remove the first substrate  111  and the first release layer  112  together. 
     With reference to  FIG.  5   , the seed layer  120  is removed to show the wires  130  after removing the first carrier  110 . Preferably, the seed layer  120  is removed by etching to expose a top surface  130   a  of each of the wires  130 . In the first embodiment, the seed layer  120  is removed by plasma etching to allow the nickel layer  131  of each of the wires  130  to be visible. 
     With reference to  FIG.  6   , after removing the seed layer  120 , a gold layer  300  is deposited on each of the wires  130  by immersion gold plating. The gold layer  300  is a surface treatment layer or passivation layer used to protect the wires  130  from oxidation. Compared to electroplated gold layer, the immersion plated gold layer  300  has better thickness uniformity and coverage. A thinner gold layer  300  formed by immersion gold plating has similar effect on anti-oxidation defense as a thicker electroplated gold layer, so the gold layer  300  formed by immersion gold plating has benefit in reducing cost. 
     In the first embodiment, the nickel layer  131  of each of the wires  130  is visible after removing the seed layer  120 , and then the gold layer  300  is deposited on the nickel layer  131  by immersion gold plating. Owing to the nickel layer  131  formed by pure nickel electroplating has no phosphorus and has high density, the nickel layer  131  will not be over-etched or generate black pads during the deposition of the gold layer  300 . As a result, the gold layer  300  has a better anti-oxidation defense effect to improve solder joint reliability significantly. 
     Referring to  FIG.  7   , if the semiconductor device is designed as a ball grid array (BGA), a solder ball  400  is disposed on the gold layer  300  after the deposition of the gold layer  300 , and then the conventional following processes, such as removing the second carrier  200 , cutting and EMI shielding, are proceeded to obtain a BGA. On the other hand, if the semiconductor device is designed as a land grid array (LGA), no solder ball is required to be disposed on the gold layer  300 , a LGA can be obtained after the conventional following processes as above-mentioned. 
     A second embodiment of the present invention is shown in  FIGS.  8  and  9   . As removing the seed layer  120 , plasma etching parameters can be adjusted to remove a top part of the patterned dielectric layer  140  together with the seed layer  120 , such that a top surface  130   a  and a lateral surface  130   b  of each of the wires  130  are visible after plasma etching. Thus, the gold layer  300  can be deposited on the top surface  130   a  and the lateral surface  130   b  of each of the wires  130  by immersion gold plating. The coverage area of the gold layer  300  on each of the wires  130  is increased to improve solder joint reliability. In the second embodiment, the top surface  130   a  and the lateral surface  130   b  of each of the wires  130 , which are exposed after removing the seed layer  120  and a part of the patterned dielectric layer  140  by plasma etching, are the top surface and the lateral surface of the nickel layer  131  of each of the wires  130 , and the gold layer  300  is deposited on the top surface and the lateral surface of the nickel layer  131 . 
     Preferably, during plasma etching of the seed layer  120  and a part of the patterned dielectric layer  140 , plasma etching parameters can be adjusted to control the removed thickness of the patterned dielectric layer  140  to be not greater than 1.5 μm, so that the top surface and the lateral surface of the nickel layer  131  can be visible and the patterned dielectric layer  140  after plasma etching has an appropriate thickness for the semiconductor devices. 
       FIGS.  10  and  11    are provided to show a third embodiment of the present invention. Different to the first embodiment, each of the wires  130  of the third embodiment includes a copper layer  132 , but not include a nickel layer. The copper layer  132  is a redistribution layer disposed on the seed layer  120 . After removing the seed layer  120 , the copper layer  132  is exposed, and the gold layer  300  is deposited on the copper layer  132  by immersion gold plating. 
     In a fourth embodiment of the present invention as shown in  FIGS.  12  and  13   , the seed layer  120  and a top part of the patterned dielectric layer  140  are removed by plasma etching, and the exposed top surface  130   a  and the exposed lateral surface  130   b  of each of the wires  130  are the top surface and the lateral surface of the copper layer  132 , respectively. Then, the gold layer  300  of the fourth embodiment is deposited on the top surface and the lateral surface of the copper layer  132 . 
     While this invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that is not limited to the specific features shown and described and various modified and changed in form and details may be made without departing from the scope of the claims.