Patent Publication Number: US-5896054-A

Title: Clock driver

Description:
FIELD OF THE INVENTION 
     The present invention pertains to clock drivers, and more particularly to an efficient clock signal driver. 
     BACKGROUND OF THE INVENTION 
     Power conservation is important in battery powered devices such as pagers, computers, personal digital assistants, radiotelephones, cellular radiotelephones, and the like. These devices typically include a clock driver circuit. Power dissipation is of particular concern for the clock circuit because it is always active, even in standby mode. 
     It is known to use a standard CMOS output stage as a clock driver because of the favorable current characteristics. The current dissipation due to the load is: 
     
         Vcc*CL*F=2.75*10 pF*13 MHz=358 uA                          (Equation 1) 
    
     where Vcc is the supply voltage; CL is the load capacitance; and F is the frequency of the clock signal. However, the output waveform is almost a square-wave and it can produce significant harmonics at critical frequencies. 
     Harmonic distortion is a problem in communication devices if the reference clock has harmonic frequency components that exactly equal certain receive channel frequencies. This situation creates the potential for the reference clock to produce noise signals that are communicated via radiation and circuit board parasitics and interfere with the desired signal being received. The typical strategy for minimizing the harmonic distortion is to filter the output of the clock driver, making the output waveform closer to a sine wave than a square wave. With conventional circuits, this requires an off-chip filter, physically close to the driver. However this solution is expensive and the addition of a filter increases power dissipation. 
     The duty cycle of the clock signal is also an important consideration. The output voltage duty cycle is preferably no worse than 45-55%. This is particularly important where the clock signal drives a circuit using both clock edges, such as a digital speech processor integrated circuit (IC). If the duty cycle is worse than 45-55%, the communication device employing the clock signal may fail to operate. 
     Accordingly, it is desirable to provide a clock driver having improved current characteristics while maintaining the duty cycle and reducing harmonics. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit schematic illustrating a reference clock driver. 
     FIG. 2 is a signal diagram illustrating signals in the circuit according to FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A novel reference clock diver circuit 100 (FIG. 1) has an input 102 for coupling to a reference clock signal generator 104. A pre-filter 106 is connected to the input to receive the reference signal and output a filtered signal. A complementary FET driver circuit 108 having a cross-over threshold is coupled to the pre-filter 106 to receive the filtered signal and output a conditioned clock signal. The pre-filter 106 can employ FET elements 122 and 124 instead of a resistor to control the duty cycle and compensate for CMOS process variations. The clock driver circuit has improved performance with respect to power dissipation, harmonic distortion and duty cycle relative to prior clock driver circuits. 
     The pre-filter 106 includes active elements, FET element 122 and FET element 124, and a capacitor 126. The gate of FET element 122 is connected to the high supply voltage OSC --  VCC by resistor 128. The voltage OSC --  VCC can be approximately 3 Volts, and may be 2.75 Volts relative to OSC --  GND. The gate of FET element 124 is connected to the low supply voltage OSC --  GND by resistor 130. Resistors 128 and 130 and they can be implemented using any suitable resistor type which provides electro-static discharge (ESD) protection for the gates of FET elements 122 and 124. 
     The output stage, the complementary FET driver circuit 108, is made up of a diode 117, FET element 116, FET element 118 and a diode 119. The diodes 117 and 119 serve to limit the output voltage relative to a high supply voltage, OSC --  VCC and a low supply voltage OSC --  GND. The oscillator supply voltage OSC --  VCC can for example be 2.75 Volts, as noted above. The low supply voltage, OSC --  GND can be circuit ground. The voltage drop across each diode can be approximately 0.75 Volts, reducing the peak-to-peak voltage drop by 1.5 Volts to 1.25 Volts. The diodes 117 and 119 can be implemented using bipolar junction transistors each having the base and collector connected, or any other suitable diode circuit. 
     The FET elements 116 and 118 can be implemented using any suitable FET. In the immediate implementation, CMOS elements are chosen and sized to produce the current levels required to drive the load, such as transceiver 120, and so that the waveform at output terminal 109 is symmetrical, responsive to signal 200 (FIG. 2) at input 110. Signal 200 is a curve with exponential characteristics. 
     The back-gate of FET element 116 is connected to its source, rather than Vcc, to minimize its switching threshold and thus minimize its size. The FET elements 122 and 118 are matched, and the FET elements 124 and 116 are matched, as they are made as part of a common IC. 
     In operation, FET element 116 and FET element 118 are switches, one of which conducts current from a voltage to the output terminal during a portion of a clock duty cycle and the other one of which conducts current from a voltage to the output terminal during another portion of the duty cycle. The transition from one element to the other element occurs at the cross-over threshold. 
     The output terminal is connected to load 120, which can be any device requiring a clock signal, such as a transmitter, a receiver or a transceiver of a device. The device can be modem, a radio telephone, a pager, or the like. 
     FET element 122 and FET element 124 provide a variable resistance impedance for filter 106. The charge-cycle resistance is mainly determined by the channel resistance of the P-channel FET element 124. Similarly, the discharge cycle resistance is set by the N-channel FET element 122. The FET elements 122 and 124 are chosen such that each half cycle is about 2.3 time constants. For example, a time constant of the filter is: 
     
         REQ*C=33K(0.5 pF)=16.7 nS 
    
     where REQ is the equivalent resistance of FET elements 122 and 124 assuming that the charge and discharge times are equal and C is the capacitance of capacitor 126. This limits the voltage excursion at the pre-filter output to about 80% of OSC --  VCC. 
     The circuit 100 is preferably manufactured on a single integrated circuit. FET elements 122 and 124 and capacitor 126 generate the signal 200 at input 110 responsive to a square wave at input 102. As shown in FIG. 2, if the cross-over threshold is TH1, the output driver circuit will produce a sinusoidal signal O1 having a 50% duty cycle. 
     However, if the P-channel FET element 116 is strong and the N-channel FET element 118 is weak, and no correction is provided, the cross-over threshold VTH2 is higher. The output signal O2 will thus have a stretched upward cycle and a shortened down cycle as shown in FIG. 2. Compensation is provided by FET elements 122 and 124. The charge cycle is faster for a strong P-channel FET element 124 whereas the discharge cycle through the weak N-channel FET element 122 is slower, producing the signal 202 in FIG. 2. Because the threshold VTH2 is higher, the quick charge allows the signal 202 to cross the threshold at around the same time as the signal 200 crosses threshold VTH1. The discharge rate through the weak N-channel is slower, such that the discharge curve crosses the higher threshold VTH2 at around the same time as signal 200 crosses VTH1. The duty cycle of the compensated output signal is thus about ideal. 
     When the N-channel FET is strong and the P-channel FET is weak, the cross-over threshold VTH3 of FET elements 116 and 118 is low. Without correction, the charge cycle is short and the discharge cycle is long, such that the distorted output signal O3 is produced. The N-channel FET element 122 and P-channel FET element 124 provide compensation. The strong N-channel FET element 122 causes a fast discharge cycle and the weak P-channel FET element 116 creates a slow charge cycle, producing signal 204. The charge cycle is thus slowed such that the signal 204 crosses the threshold VTH3 at about the same time as the signal 200 crosses the threshold VTH1. The quick discharge allows the signal 204 to cross the low threshold VTH3 at about the same time as the signal 200 crosses the threshold VTH1. Thus, the slow charge and fast discharge with the lower threshold voltage VTH3 produce an output signal at 109 which is minimally affected. 
     Using FET elements 122 and 124 as time-constant setting resistors for charging and discharging the capacitor 126 in this manner makes the circuit less sensitive to process variations experienced in manufacturing the integrated circuit having FET elements 116, 118, 122, 124. Of primary concern are cases in which the N-channel FET elements are stronger than typical, while the P-channel FET elements are weaker than typical, or vice-versa. This commonly occurs with CMOS processes that utilize a single implant to adjust both Vtn and Vtp. These processes change the input threshold voltage of the driver stage, which results in a poor duty cycle if a resistor is used with the capacitor 126. 
     Table 1, below shows some of the simulation results. The condition `StrN` indicates a strong NMOS model and a weak PMOS model. `StrP` indicates a strong PMOS model and a weak NMOS model. Columns 4 and 5 give the signal amplitudes at the critical harmonic frequencies, which correspond to receive channels. These amplitudes are normalized to the 13 MHz fundamental. 
     
                       TABLE 1
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Simulation results
Condition
         Icc, uA Duty Cycle
                           936 Mhz, dBc
                                    949 Mhz, dBc
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typical  181     51.1      -77.8    -78.7
StrN, 85° C.
         189     50.0      -86.6    -78.4
StrP, 85° C.
         188     48.8      -98.0    -89.8
StrN, -40° C.
         164     52.3      -85.2    -81.6
StrP, -40° C.
         165     53.9      -76.3    -80.8
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     This clock driver is connected to a capacitive load Cl, such that the supply current due to the load is: 
     
         Iccl=Vpp*Cl*f=Vpp*10 pF*13 Mhz=Vpp*130 uA/V 
    
     where Vpp is the peak-to-peak voltage. The output voltage swing of this circuit is about 1.3 Volts as noted above, so the supply current Iccl due to the load capacitance is equal to approximately 170 uA. The total current drawn by this circuit is about 180 uA. If employed in a cellular telephone for example, this helps bring the total standby current in the transceiver IC down to about 600 uA. This is a significant savings relative to prior circuits. 
     In conclusion, the clock driver topology satisfies the requirements of low harmonic distortion and well-controlled duty cycle. This clock driver draws a minimal amount of supply current and provides a clock signal to digital signal processing IC of a device such as a cellular telephone. Power reduction is particularly important in such applications since they are battery powered. It is desirable to extend the time between charging while reducing the size of batteries to keep the weight and size of cellular telephones to a minimum. This circuit contributes to the reduction of the current drain in such a device. 
     Thus it can be seen that an improved clock driver circuit is disclosed. The clock driver circuit has significantly lower current drain than prior driver circuits. Additionally, the circuit compensates for variations in the low current output elements using an input filter. The driver circuit thus produces an output signal having the desired duty cycle with minimized interference frequencies and having favorable current characteristics.