Patent Publication Number: US-7224187-B2

Title: CMOS buffer circuits and integrated circuits using the same

Description:
BACKGROUND 
   The invention relates to buffer circuits, and more particularly, to buffer circuits with a reduced short circuit current and integrated circuits and ring oscillation circuits using the same. 
   CMOS buffer circuits are widely applied to drive devices connected to an output stage thereof. Generally, the power consumption of CMOS circuit is dynamic power consumption or short circuit power consumption. Dynamic power consumption is inevitable due to electric characteristics of CMOS buffer circuits, but short circuit power consumption results in wasted power. With advance of process technology, the smaller gate length of MOS transistors reduces the threshold voltage of the MOS transistors, such that short circuit current often occurs. To reduce short circuit power consumption, it is reasonable to focus to reduce short circuit current of buffers with high switching rate, such as clock buffers. The short circuit current of CMOS buffers also causes electronmagnetic interference (EMI). Thus, it is very important to reduce short circuit current for CMOS buffer circuits. 
   Many conventional methods have been disclosed to reduce short circuit current for buffer circuits.  FIG. 1  shows a conventional CMOS buffer circuit  200  with reduced short circuit current. However, a short circuit current occurs not only in pre-driving stage  310  but also the output buffer driving stage  350 . For example, when input (IN) is low in the beginning, the nodes  20  and  30  are at high, such that the transistors M 36 –M 37  are turned on and transistor M 38  is turned off. When the input (IN) goes high from low, the transistor M 38  is turned on, the transistor M 36  is turned off and the transistor M 37  stays on until the voltage level at the node  20  goes low. Because gate terminals of the transistors M 36  and M 38  are connected, the transistors M 36  and M 38  are both turned on when the gate voltage crosses the middle range between the power voltage and the ground voltage, generating a short current through the transistors M 36 –M 38 . Further, as voltage levels at the nodes  20  and  30  go low from high, the PMOS transistors and NMOS transistors of inverters IN 3  and IN 4  are both turned on when the input terminals of cross the middle range between the power voltage and the ground voltage. Thus, there is a short circuit through the inverters IN 3  and IN 4 . Similarly, when the input (IN) goes low from high, there is a short circuit current through the transistor M 33 –M 35  and through the inverters IN 3  and IN 4 . 
     FIG. 2  shows another conventional CMOS buffer circuit  500  with reduced short circuit current. When the input terminal  501  goes high from low, the voltage level at node  582  stays high but the voltage level at node  594  goes low from high, such that transistors M 1  and M 3  are turned on at the same time until the voltage level of node  582  is discharged to low, generating a short circuit through the transistors M 1  and M 3 . Further, because the gate terminals of the transistors M 5  and M 6  are connected, one of the transistors M 5  and M 6  is always turned on, allowing a short circuit current through the transistors M 5  and M 6  when the input terminal  501  changes. 
   Namely, there is still a short circuit current through the output buffer driving stage  350  shown in  FIG. 1  and the output buffer driving stage  550  shown in  FIG. 2 . 
   SUMMARY 
   The invention provides a CMOS buffer circuit with reduced short circuit current. 
   The invention discloses embodiments of a CMOS buffer circuit, in which an output stage drives an output terminal and comprises a first output transistor of a first conductive type and a second output transistor of a second conductive type. An output driving unit produces a first signal to turn off the first output transistor according to a delay signal. A bidirectional delay unit is controlled by the input signal to turn on the second output transistor after the first output transistor is turned off. In the bidirectional delay unit, a bidirectional logic unit generates two logic signals according to an inversion signal of the input signal, the first and second bidirectional buffers are coupled to the output driving stage, generating a second signal to turn on the second output transistor according to the input signal and the two logic signals. 
   The invention also discloses embodiments of an integrated circuit, in which at least two stages of the disclosed CMOS buffer circuit are connected in series, and the output terminal of each stage is coupled to the output driving unit of the next stage. 
   The invention also discloses embodiments of a ring oscillation circuit, in which first and second CMOS buffer circuits as disclosed are connected in series, and the output terminal of first CMOS buffer circuit is coupled to the output driving unit of the second CMOS buffer circuit. An inverter comprises an input terminal coupled to the output terminal of the second CMOS buffer circuit and an output terminal coupled to the input terminal of the first CMOS buffer circuit. 

   
     DESCRIPTION OF THE DRAWINGS 
     The invention can be more fully understood by the subsequent detailed description and examples with reference made to the accompanying drawings, wherein: 
       FIG. 1  shows a conventional CMOS buffer circuit; 
       FIG. 2  shows another conventional CMOS buffer circuit; 
       FIG. 3  shows a CMOS buffer circuit according to the invention; 
       FIG. 4A  shows an embodiment of a bidirectional logic gate; 
       FIG. 4B  shows another embodiment of a bidirectional logic gate; 
       FIG. 5A  shows a first embodiment of a bidirectional buffer circuit; 
       FIG. 5B  shows a second embodiment of a bidirectional buffer circuit; 
       FIG. 5C  shows a third embodiment of a bidirectional buffer circuit; 
       FIG. 6  is a timing chart of the buffer circuit as shown in  FIG. 5A ; 
       FIG. 7  shows a long delay circuit using the invention; and 
       FIG. 8  shows a ring oscillation circuit using the invention. 
   

   DETAILED DESCRIPTION 
     FIG. 3  is a diagram of a CMOS buffer circuit. As shown, the CMOS buffer circuit  100  comprises an input terminal  101 , an output stage  110 , an output driving unit  120 , a bidirectional delay unit  130  and a delay circuit  140 . 
   The input terminal  101  receives an input signal SI, and the output stage  110  comprises a PMOS transistor M 13  and an NMOS transistor M 12 , driving an output terminal  102 . The PMOS transistor M 13  comprises a first terminal coupled to the first power source Vdd, a second terminal coupled to the output terminal  102 , and a control terminal coupled to the output driving unit  120 . The NMOS transistor M 12  comprises a first terminal coupled to the output terminal  102 , a second terminal coupled to the second power source GND, and a control terminal coupled to the output driving unit  120 . 
   The output driving unit  120  produces a first signal V 1 /V 2  to turn off the MOS transistor M 13 /M 12  according to a delay signal SD. The output driving unit  120  comprises a PMOS transistor M 11  and a NMOS transistor M 5 , the PMOS transistor M 11  comprising a first terminal coupled to the first power source Vdd, a second terminal coupled to the control terminal of the PMOS transistor M 13 , and a control terminal coupled to the delay signal SD. The NMOS transistor M 5  comprises a first terminal coupled to the control-terminal of the PMOS transistor M 12 , a second terminal coupled to the second power source GND, and a control terminal coupled to the delay signal SD. 
   The bidirectional delay unit  130  is controlled by the input signal SI to turn on the MOS transistor M 12 /M 13  after the MOS transistor M 13 /M 12  is turned off. The bidirectional delay unit  130  comprises a bidirectional logic unit  1310 , and first and second bidirectional buffers  1320  and  1330 . The bidirectional logic unit  1310  generates two logic signals (not shown) according to an inversion signal SV of the input signal SI. The bidirectional logic unit  1310  can be a bidirectional logic gate or a bidirectional logic chain comprising a plurality of bidirectional logic gates connected in series. The first and second bidirectional buffers  1320  and  1330  are coupled to the output driving unit  120 , generating a second signal V 2 /V 1  to turn on the MOS transistor M 12 /M 13  according to the input signal SI and the two logic signals. 
   For example, when the input signal SI goes low from high, the output driving unit  120  produces the first signal V 1  to turn off the MOS transistor M 13  according to the delay signal SD. The bidirectional delay unit  130  turns on the MOS transistor M 12  after the MOS transistor M 13  is turned off, according to the input signal SI. Alternately, when the input signal SD goes high from low, the output driving unit  120  produces the first signal V 2  to turn off the MOS transistor M 12  according to the delay signal SD. The bidirectional delay unit  130  turns on the MOS transistor M 13  after the MOS transistor M 12  is turned off, according to the input signal SI. Thus, the PMOS transistor M 13  and the NMOS transistor M 12  are not turned on simultaneously when the input signal SD goes low from high or goes high from low, thereby preventing short circuit current. 
     FIG. 4A  shows an embodiment of a bidirectional logic gate. As shown, the bidirectional logic gate  1310 A generates two logic signals OT 1  and OUT 2  according to a control signal CS and two input signals IT 1  and IT 2 , and comprises two NMOS transistors M 1  and M 2  and two PMOS transistor M 3  and M 4 . The NMOS transistor M 1  comprises a first terminal coupled to the second power source GND, a control terminal coupled to a control signal CS, and a second terminal. The NMOS transistor M 2  comprises a first terminal coupled to the second terminal of the NMOS transistor M 1 , a control terminal coupled to the input signal IT 1 , and a second terminal coupled to the node N 1 . The PMOS transistor M 3  comprises a first terminal coupled to the node N 1 , a control terminal coupled to the input signal IT 2 , and a second terminal. The PMOS transistor M 4  comprises a first terminal coupled to the second terminal of the PMOS transistor M 3 , a control terminal coupled to the control signal CS, and a second terminal coupled to the first power source Vdd. 
   When control signal CS is high, the transistors M 1  and M 4  are turned on and off respectively, and the voltage VL at the node N 1  goes low if the input signal IT 1  is high, otherwise the voltage VL stays high-impedance (Hiz). Thus, the bidirectional logic gate  1310 A generates the voltage VL with a low voltage level, serving as the two logic signals OT 1  and OT 2 , for output to the first and second bidirectional buffers  1320  and  1330 . Alternately, when control signal CS is low, the transistors M 1  and M 4  are turned off and on respectively, and the voltage VL at the node N 1  goes high if the input signal IT 2  is low, otherwise the voltage VL stays high-impedance (Hiz). Thus, the bidirectional logic gate  1310 A generates the voltage VL with a high voltage level, serving as the two logic signals OT 1  and OT 2 , for output to the first and second bidirectional buffers  1320  and  1330 . 
     FIG. 4B  shows another embodiment of a bidirectional logic gate. As shown, the bidirectional logic gate  1310 B is similar to the logic gate  1310 A shown in  FIG. 4A  with the exception of the NMOS transistors M 3 X and the PMOS transistor M 2 X. The NMOS transistor M 2 X is coupled between the node N 1  and the second terminal of the NMOS transistor M 1  and comprises a control terminal coupled to the input signal IT 1 . The PMOS transistor M 3 X is coupled between the node N 1  and the second terminal of the PMOS transistor M 4  and comprises a control terminal coupled to the input signal IT 2 . 
   When control signal CS is high, the transistors M 1  and M 4  are turned on and off respectively, and the voltage VL at the node N 1  goes low if the input signal IT 1  or the input signal IT 2  is high, otherwise the voltage VL stays high-impedance (Hiz). Thus, the bidirectional logic gate  1310 B generates the voltage VL with a low voltage level, serving as the two logic signals OT 1  and OT 2 , for output to the first and second bidirectional buffers  1320  and  1330 . Alternately, when control signal CS is low, the transistors M 1  and M 4  are turned off and on respectively, and the voltage VL at the node N 1  goes high if the input signal IT 1  or the input signal IT 2  is high, otherwise the voltage VL stays high-impedance (Hiz). Thus, the bidirectional logic gate  1310 A generates the voltage VL with low voltage level, serving as the two logic signals OT 1  and OT 2 , for output to the first and second bidirectional buffers  1320  and  1330 . 
   First Embodiment 
     FIG. 5A  shows a first embodiment of a buffer circuit. As shown, the buffer circuit  100 A comprises an input terminal  101 , an output stage  110 , an output driving unit  120 , a bidirectional delay unit  130  and a delay circuit  140 . The output stage  110  and output driving unit  120  are similar to those in the buffer circuit  100  shown in  FIG. 3 , and the bidirectional logic unit  1310  is similar to the bidirectional logic gate  1310 A shown in  FIG. 4A . 
   In the bidirectional logic unit  1310 , the control terminal of the PMOS transistor M 3  is coupled to the voltage V 2 , and the control terminal of the NMOS transistor M 2  is coupled to the voltage V 1 . The control terminals of the transistors M 1  and M 4  are coupled to the inversion signal SV from the delay circuit  140 . The voltage VL serves as the first and second logic signals and is coupled to the bidirectional buffers  1320  and  1330 . 
   The bidirectional buffer  1330  comprises two PMOS transistors M 6  and M 7  connected between the first power source Vdd and the voltage V 2 . The bidirectional buffer  1320  comprises two NMOS transistors M 9  and M 10  connected between the voltage V 1  and the second power source GND. Control terminals of the transistors M 7  and M 9  are coupled to the input signal SI, and control terminals of the transistors M 6  and M 10  are coupled to the voltage V 1 . 
   The delay circuit  140  comprises two inverters  510  and  520  connected in series, in which the inverter  510  generates an inversion signal SV of the input signal SI, and the inverter  520  generates the delay signal SD. 
   The operation of the buffer circuit  100 A is discussed with reference to the  FIGS. 5A and 6 . As shown in  FIG. 6 , the input signal SI stays high, the inversion signal SV stays low and the delay signal SD stays high in the beginning. Accordingly, the voltages V 1  and V 2  both stay low and the voltage VL stays high, and thus, the voltage VOUI at the output terminal  102  stays high. 
   At time t 1 , the input signal SI goes low, the transistors M 7  and M 9  are turned on and off respectively. Because the voltage VL still stays high, the transistor M 6  is maintained off and thus, there is no short circuit current through the transistors M 5 –M 7  in this transition. 
   At time t 2 , the inversion signal SV goes high, the transistors M 1  and M 4  are turned on and off respectively. Because the voltage V 1  still stays low, the transistor M 2  is maintained off, and thus, there is no short circuit current through the transistors M 1 –M 4  in this transition. At time t 3 , the delay signal SD goes low, the transistors M 5  and M 11  are turned off and on respectively. Because the transistor M 9  is turned off by the input signal SI, there is no short circuit current through the transistors M 9 –M 11  in this transition. 
   At time t 4 , the voltage V 1  goes high because the transistor M 11  is turned on at time t 3 . Due to V 1  high level, the transistor M 13  is turned off. Namely, the output driving unit  120  produces the voltage V 1  to turn off the transistor M 13  according to a delay signal SD. 
   At time t 5 , due to the V 1  high level, the transistor M 2  is turned on. The voltage VL goes low, because the transistors M 1  and M 2  are both turned on. Namely, the bidirectional logic unit  1310  generates the voltage VL (logic signals) according to the inversion signal SV of the input signal SI. Because the transistor M 4  is turned off, there is no short circuit current through the transistors M 1 –M 4  in this transition. 
   At time t 6 , due to the VL low level, the transistors M 6  and M 10  are turned on and off. The voltage V 2  goes high, because the transistors M 6 –M 7  are both turned on. Because the transistor M 5  is turned off, there is no short circuit current through the transistors M 5 –M 7  in this transition. 
   At time t 7 , due to the V 2  high level, the transistors M 12  is turned on to drive the output terminal  102 , and thus, the voltage VOUT at the output terminal  102  goes low. Namely, the first and second bidirectional buffers  1320  and  1330  generate the voltage V 2  to turn on the transistor M 12  according to the input signal SI and the voltage VL (the first logic signal and the second logic signal). Thus, transistor M 12  is turned on after the transistor M 13  is turned off. Namely, the transistors M 12  and M 13  are not turned on simultaneously, such that there is no short circuit current through transistors M 12  and M 13 . In view of this, there is no short circuit current in the output stage  110 , the output driving unit  120  and the bidirectional delay unit  130  when the input signal SI goes high from low. 
   Alternately, the input signal SI goes high at time t 8 , and the transistors M 7  and M 9  are turned off and on respectively. Because the voltage VL still stays low, the transistor M 10  is maintained off, and there is no short circuit current through the transistors M 9 –M 11  in this transition. 
   At time t 9 , the inversion signal SV goes low, the transistors M 1  and M 4  are turned off and on respectively. Because the voltage V 2  still stays high, the transistor M 3  is maintained off, and there is no short circuit current through the transistors M 1 –M 4  in this transition. 
   At time t 10 , the delay signal SD goes high, and the transistors M 5  and M 11  are turned on and off respectively. Because the transistor M 7  is turned off by the input signal SI, and there is no short circuit current through the transistors M 5 –M 7  in this transition. 
   At time t 11 , the voltage V 2  goes low because the transistor M 5  is turned on at time t 10 . Due to the V 2  low level, the transistor M 12  is turned off. Namely, the output driving unit  120  produces the voltage V 2  to turn off the transistor M 12  according to a delay signal SD. 
   At time t 12 , due to the V 2  low level, the transistor M 3  is turned on. The voltage VL goes high, because the transistors M 3  and M 4  are both turned on. Namely, the bidirectional logic unit  1310  generates the VL (logic signals) high level according to the inversion signal SV of the input signal SI. Because the transistor M 1  is turned off, there is no short circuit current through the transistors M 1 –M 4  in this transition. 
   At time t 13 , due to the VL high level, the transistors M 6  and M 10  are turned off and on. The voltage V 1  goes low, because the transistors M 9 –M 10  are both turned on. Because the transistor M 11  stays off, there is no short circuit current through the transistors M 9 –M 11  in this transition. 
   At time t 14 , due to the voltage V 1  of low level, the transistor M 13  is turned on to drive the output terminal  102 , and the voltage VOUT at the output terminal  102  goes high. Namely, the first and second bidirectional buffers  1320  and  1330  generate the voltage V 1  to turn on the transistor M 13  according to the input signal SI and the voltage VL (the first logic signal and the second logic signal). Thus, transistor M 13  is turned on after the transistor M 12  is turned off. Namely, the transistors M 12  and M 13  are not turned on simultaneously, such that there is no short circuit current through transistors M 12  and M 13 . In view of this, there is no short circuit current in the output stage  110 , the output driving unit  120  and the bidirectional delay unit  130  when the input signal SI goes low from high. 
   Because there is no short circuit current in the output stage  110 , the output driving unit  120  and the bidirectional delay unit  130  in the buffer circuits, the invention prevents short circuit current in output buffer driving stages shown in  FIGS. 1 and 2 , and thus provides a reduced power consumption and electronmagnetic interference (EMI) than conventional buffer circuits. 
   Second Embodiment 
     FIG. 5B  shows a second embodiment of a buffer circuit. As shown, the buffer circuit  100 B is similar to the buffer circuit  100 A shown in  FIG. 5A , with the exception of the first terminal of the transistor M 7  in the bidirectional buffer  1330  being coupled to the control terminal of the transistor M 13  rather than the first power source Vdd and the second terminal of the transistor M 9  in the bidirectional buffer  1320  being coupled to the control terminal of the transistor M 12  rather than the second power source GND. The operation of the buffer circuit  100 B is similar to that of the buffer circuit  100 A, and thus is omitted for simplicity. 
   Because the first terminal of the transistor M 7  in the bidirectional buffer  1330  is coupled to the control terminal of the transistor M 13  and the second terminal of the transistor M 9  in the bidirectional buffer  1320  is coupled to the control terminal of the transistor M 12 , the gate voltage of the transistor M 13  from exceeding the gate voltage of the transistor M 12  or the gate voltage of the transistor M 12  from exceeding the gate voltage of the transistor M 13  is automatically prevented. 
   Third Embodiment 
     FIG. 5C  shows a third embodiment of a buffer circuit. As shown, the buffer circuit  100 C is similar to the buffer circuit  100 A shown in  FIG. 5A , with the exception of the bidirectional logic unit  1310 C including three bidirectional logic gates connected in series rather than a single bidirectional logic gate. The operation of the buffer circuit  100 C is similar to that of the buffer circuit  100 A, and thus is omitted for simplicity. 
   In the buffer circuit  100 C, the delay time thereof can be increased by addition of the bidirectional logic gates, although the total short circuit current does not increase because there is no short circuit current in bidirectional logic gates. 
     FIG. 7  shows a long delay circuit using the invention. As shown, the long delay circuit  200  comprises two stages of buffer circuit  100 _ 1  and  100 _ 2  connected in series, in which the output terminal of the buffer circuit  100 _ 1  is coupled to the output driving unit of the buffer circuit  100 _ 2 . Each buffer circuit  100 _ 1  and  100 _ 2  is similar to that shown in  FIG. 5A . Thus, the short circuit current does not increase by addition of buffer circuits. 
     FIG. 8  shows a ring oscillation circuit using the invention. As shown, a ring oscillation circuit  300  comprises first and second buffer circuits  100 _ 1  and  100 _ 2  connected in series, and the output terminal of first buffer circuit  100 _ 1  is coupled to the output driving unit of the second buffer circuit  100 _ 2 . An inverter  530  comprises an input terminal coupled to the output terminal of the second buffer circuit  100 _ 2  and an output terminal coupled to the input terminal of the first buffer circuit  100 _ 1 . 
   Conventional ring oscillators comprise many inverters connected in series, and have short circuit in each inverter, such that short circuit current increases with the number of the inverters. In the ring oscillator circuit of the invention, the short circuit current does not increase with the number of stages because there is no short circuit current in the output stage  110 , the output driving unit  120  and the bidirectional delay unit  130  in each stage. 
   While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.