Patent Publication Number: US-11646735-B2

Title: Apparatus with electronic circuitry having reduced leakage current and associated methods

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This patent application is a continuation of U.S. patent application Ser. No. 15/634,716, titled ‘Apparatus with Electronic Circuitry Having Reduced Leakage Current and Associated Methods,’ filed on Jun. 27, 2017, which is hereby incorporated by reference in its entirety for all purposed. 
    
    
     TECHNICAL FIELD 
     The disclosure relates generally to electronic circuitry with improved power consumption and, more particularly, to integrated circuit (IC) apparatus with reduced power consumption, and associated methods. 
     BACKGROUND 
     Modern ICs have helped to integrate electronic circuitry to decrease size and cost. As a consequence, modern ICs can form complex circuitry and systems. For example, virtually all of the functionality of a system may be realized using one or a handful of ICs. Such circuitry and systems may receive and operate on both analog and digital signals, and may provide analog and digital signals. 
     The result has been a growing trend to produce circuitry and systems with increased numbers of transistors and similar devices. The increased number of devices has also coincided with increased power consumption of electronic circuits, such as ICs. Various mechanisms, such as device leakage, underlie the increased power consumption. Technologies such as metal oxide semiconductor (MOS) or complementary MOS (CMOS), which are used in a variety of IC devices, use devices such as transistors with leakage currents. 
     The description in this section and any corresponding figure(s) are included as background information materials. The materials in this section should not be considered as an admission that such materials constitute prior art to the present patent application. 
     SUMMARY 
     A variety of apparatus and associated methods are contemplated according to exemplary embodiments. According to one exemplary embodiment, an apparatus includes an IC, which includes CMOS circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native MOS transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor. 
     According to another exemplary embodiment, an apparatus includes an IC, which includes CMOS circuitry. The CMOS circuitry includes an n-channel transistor network that includes at least one n-channel transistor having a GIDL current. The IC further includes a native MOS transistor coupled to supply a bias voltage to the at least one n-channel transistor to reduce the GIDL current of the at least one n-channel transistor. 
     According to another exemplary embodiment, a method of reducing a GIDL current of at least one transistor in a CMOS circuit includes using a native MOS transistor to supply a bias voltage to a gate of at least one transistor in the CMOS circuit so as to reduce a voltage between a drain and the gate of the at least one transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The appended drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope of the application or the claims. Persons of ordinary skill in the art will appreciate that the disclosed concepts lend themselves to other equally effective embodiments. In the drawings, the same numeral designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks. 
         FIG.  1    illustrates a circuit arrangement for illustrating GIDL currents in n-channel and p-channel MOS transistors. 
         FIG.  2    depicts a circuit arrangement for illustrating GIDL currents in a CMOS circuit. 
         FIGS.  3 - 4    show circuit arrangements for reducing GIDL currents in CMOS circuits according to exemplary embodiments. 
         FIGS.  5 - 12    illustrate circuit arrangements for generating voltages used to reduce GIDL currents according to exemplary embodiments. 
         FIG.  13    depicts a plot of simulation results to illustrate GIDL-current reduction according to an exemplary embodiment. 
         FIG.  14    illustrates a circuit arrangement for improving the operation of a CMOS circuit according to an exemplary embodiment. 
         FIG.  15    depicts a plot of simulation results to illustrate GIDL-current reduction according to an exemplary embodiment. 
         FIG.  16    depicts a block diagram of an IC, including a microcontroller unit (MCU), according to an exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The disclosed concepts relate generally to improving the performance of electronic circuitry. More specifically, the disclosed concepts provide apparatus and methods for reducing the leakage and, thus, improving or reducing the power consumption of, electronic circuitry, such as ICs. Rather than modifying the semiconductor fabrication process, the techniques according to the disclosure use circuit-based approaches to reducing the leakage current of CMOS circuitry, as described below in detail. 
     In practical implementations, CMOS circuitry can have several leakage mechanisms. For example, the gates of p-channel transistors and the gates of n-channel transistors tend to leak current. In other words, the oxide layer used to construct the gates of the transistors is not a perfect insulator, which results in some leakage current. Generally, reverse-biased PN junctions will also leak a certain amount of current and therefore increase the overall leakage current of a CMOS circuit or IC. 
     CMOS circuits typically exhibit other leakage mechanisms. For instance, GIDL current may constitute a relatively large or substantial part of the total leakage current for CMOS circuits. GIDL may contribute a relatively large or substantial amount to the overall leakage of CMOS circuits employing lightly-doped drain (LDD) transistors designed for operation with relatively high supply voltages (V DD ), say, greater than 3 volts. Generally, the GIDL mechanism and the effects of LDD are known to, and understood by, persons of ordinary skill in the art. 
     Generally, GIDL currents increase the power consumption of CMOS circuits. In the normal mode (or high-power mode or active mode or powered) of operation, some transistors will undergo conditions that cause GIDL currents. The effects of GIDL currents are typically more pronounced in low-power mode (or sleep mode or hibernation mode or powered-down) modes of operation. 
     More specifically, the GIDL effect typically happens when an n-channel transistor is in the off condition, and its drain-gate voltage (V dg ) is relatively large. Conversely, in p-channel transistors, the GIDL effect typically happens when the transistor is in the off condition, and its gate-drain voltage (V gd ) is relatively large. 
     Note that a related phenomenon, gate-induced-source-leakage (GISL) current, exists if the source and drain of the transistor were switched around or swapped, either physically, or electrically (e.g., when the transistor is used as a sampler). Although the disclosure refers to GIDL currents, similar techniques may be used in exemplary embodiments to address and reduce GISL by making appropriate modifications to the techniques and exemplary embodiments described below, as persons of ordinary skill in the art will understand. 
     As  FIG.  1    illustrates, the GIDL current, I GIDL , flows from the drain of an n-channel MOS transistor (the left-side transistor in  FIG.  1   ) to its bulk when the drain voltage is relatively high compared to the gate voltage, which is relatively low. Conversely, for a p-channel MOS transistor (the right-side transistor in  FIG.  1   ), the GIDL current, I GIDL , flows from the bulk of the transistor to its drain when the gate voltage is relatively high compared to its drain voltage, which is relatively low. 
     The transistor configuration that gives rise to GIDL currents is relatively common in analog circuits in the low-power mode in which the transistor is turned off, while its gate-drain (or drain-gate) voltage is relatively high, e.g., the supply voltage, V DD .  FIG.  2    depicts a circuit arrangement  10  for illustrating the GIDL current in a CMOS current source circuit. 
     In the low-power mode, switches SW 1 , SW 2  and SW 3  are all on, and V bp  (shown on the figure) is the supply voltage while V bn  (shown on the figure) is the ground potential. Transistors M 1 -M 4  have gate-source voltages of zero. Consequently, transistors M 1 -M 4  are off, and the current source circuit operates in the low-power mode. 
     Transistors M 2  and M 4  have drain-bulk voltages of zero (by virtue of switches SW 2  and SW 3  being closed). Consequently, transistors M 2  and M 4  do not contribute much, if any, to the total GIDL current of the circuit. 
     Note, however, that while transistor M 1  is turned off, its drain-gate voltage is the supply voltage. Similarly, transistor M 3  is turned off, and its gate-drain voltage is the supply voltage. Such a configuration induces GIDL currents, which affect the total power consumption of the circuit in low-power mode. 
       FIG.  3    shows circuit arrangement  20  for reducing GIDL in CMOS circuits according to an exemplary embodiment. More specifically, the circuit in  FIG.  3    includes transistor M 5  and transistor M 6 , coupled respectively between transistors M 1 -M 2  and transistors M 3 -M 4 . 
     More specifically, the drain of n-channel transistor M 5  is coupled to the drain of transistor M 2 , and the source of transistor M 5  is coupled to the drain of transistor M 1 . The gate of transistor M 5  is coupled through switch SW 4 A to a bias voltage V casn . The gate of transistor M 5  is further coupled through switch SW 4 B to the supply voltage, V DD . 
     Similarly, the source of p-channel transistor M 6  is coupled to the drain of transistor M 3 , and the drain of transistor M 6  is coupled to the drain of transistor M 4 . The gate of transistor M 6  is coupled through switch SW 5 A to a bias voltage V casp . The gate of transistor M 6  is further coupled through switch SW 5 B to the ground voltage, V SS . 
     Thus, effectively, transistors M 5  and M 6  are coupled, respectively, in series with transistors M 1  and M 3  to reduce the voltages between the drains and gates of transistors M 1  and M 3 . During the normal mode of operation, transistors M 5  and M 6  are turned on, i.e., the enable signal EN is asserted (EN=1), hence, switches SW 4 B and SW 5 B are closed. As a consequence, the gate of transistor M 5  is coupled to the supply voltage, which turns it on. Similarly, the gate of transistor M 6  is coupled to the ground potential, which turns on the transistor. 
     During the low-power mode of operation, however, the enable signal is de-asserted (EN=0). Thus, switches SW 4 A and SW 5 A are closed. As a result, the gate of transistor M 5  is coupled to the bias voltage V casn , and the gate of transistor M 6  is coupled to the bias voltage V casp . Bias voltage V casn  is lower than V DD , and bias voltage V casp  is higher than V SS . Consequently, the voltages across the drains and gates of transistors M 1  and M 3  are reduced and, as a result, the GIDL currents attributable to transistors M 1  and M 3  are reduced or eliminated (or nearly eliminated, given a practical, real-life implementation). 
     Although the GIDL-current reduction technique is described above in the context of a current-mirror circuit, the concepts may be generalized to other analog circuitry.  FIG.  4    shows circuit arrangement  20  for reducing GIDL in a generalized analog CMOS circuit according to an exemplary embodiment. 
     More specifically, the CMOS circuit includes a p-channel transistor network  23 , which is coupled to the supply voltage, V DD . Network  23  includes one or more p-channel transistors to implement or realize a variety of functions. Examples include current sources, current mirrors, amplifiers, comparators, etc., as persons of ordinary skill in the art will understand. 
     Conversely, the CMOS circuit includes an n-channel transistor network  26 , which is coupled to the ground voltage, V SS . Network  26  includes one or more n-channel transistors to implement or realize a variety of functions, as described above. In some embodiments, network  26  is complementary to network  23 , i.e., it uses n-channel transistors instead of p-channel transistors, but has a similar topology. 
     Transistor M 5  is coupled between p-channel transistor network  23  and n-channel transistor network  26 . The gate of transistor M 5  is coupled to switches SW 4 A and SW 4 B, as described above. 
     Transistor M 6  is also coupled p-channel transistor network  23  and n-channel transistor network  26 . The gate of transistor M 6  is coupled to switches SW 5 A and SW 5 B, as described above. Switches SW 4 A-SW 4 B and SW 5 A-SW 5 B are operated as described above to reduce the GIDL currents attributable to at least one transistor in p-channel transistor network  23  (a transistor that is coupled to transistor M 5 ) and at least one transistor in n-channel transistor network  26  (a transistor that is coupled to transistor M 6 ). 
     Note that in some embodiments, more than one transistor M 5  and/or more than one transistor M 6  may be used, as desired. In other words, depending on the specific topology of the CMOS circuit realized by p-channel transistor network  23  and n-channel transistor network  26 , more than two circuit branches may exist between p-channel transistor network  23  and n-channel transistor network  26 . 
     In such cases, more than one transistor M 5  and/or more than one transistor M 6  may be used to reduce the GIDL currents attributable to transistor(s) in p-channel transistor network  23  (one or more transistors that are coupled to transistor(s) M 6 ) and transistor(s) in n-channel transistor network  26  (one or more transistors that are coupled to transistor(s) M 5 ). The addition of transistor(s) M 5  and transistor(s) M 6  reduces the GIDL-current contribution of one or more transistors in n-channel transistor network  26  and one or more transistors in p-channel transistor network  23 . 
     One aspect of the disclosure relates to the generation of bias voltage V casn  and V casp . In some embodiments for generating bias voltages, one or more native transistors are used, as described below in detail. Depending on the context and circuit in which a native transistor is used, the threshold voltage may be either the voltage that turns on the native transistor, or the voltage that causes the current flowing through the device to be zero (or nearly zero), as persons of ordinary skill in the art understand. 
     Thus, in some contexts, the threshold voltage of a native transistor refers to the voltage applied between the gate and the source that turns on the transistor. In other contexts, the threshold voltage of a native transistor refers to a voltage applied between the gate and source of the transistor that causes the current flowing through the device to equal zero (or nearly equal to zero in a practical implementation). Apparatus and methods according to the disclosure may be used in either context, as persons of ordinary skill in the art will understand. 
       FIG.  5    shows a circuit arrangement  30  for generating bias voltage V casp  used to reduce GIDL current according to an exemplary embodiment. In circuit arrangement  30 , a native transistor, n-channel or NMOS transistor Mn 1 , is used to generate bias voltage V casp . The source of transistor Mn 1  is coupled to the ground voltage via switches SW 6 A and SW 6 B, while its drain is coupled to the supply. 
     More specifically, the source of transistor Mn 1  is coupled to the output of the circuit (labeled “V casp ”) through switch SW 6 A. The output of the circuit (labeled “V casp ”) is coupled to ground via switch SW 6 B. 
     When the circuit is disabled, i.e., cas_en=0, switch SW 6 A is opened, and switch SW 6 B is closed. Conversely, switch SW 6 A is closed when the circuit is enabled, i.e., enable signal cas_en has a binary logic 1 value (cas_en=1). 
     The source voltage of transistor Mn 1  equals |V thn |, where V thn  denotes the threshold voltage of transistor Mn 1 . Thus, when the circuit is enabled, the bias voltage V casp  equals |V thn |. Conversely, when the circuit is disabled (i.e., cas_en=0 and switch SW 6 B is closed), the bias voltage V casp  is at the circuit-ground potential (V casp =V SS ). 
     By driving PMOS transistor M 6  in  FIG.  3    or  FIG.  4    using bias voltage V casp , the voltage across transistor M 3  in  FIG.  3    (or across one or more transistors in p-channel transistor network  23  in  FIG.  4   ) will be approximately V DD −V th6 −|V thn | (where V th6  denotes the threshold voltage of transistor M 6 ) instead of V DD , which reduces the GIDL current of the circuit. 
     A similar arrangement may be used, employing native p-channel or PMOS transistors, to generate bias voltage V casn , which is used to reduce the GIDL-current contribution of n-channel transistors.  FIG.  6    shows a circuit arrangement  40  that uses this scheme. 
     In circuit arrangement  40 , a native transistor, p-channel or PMOS transistor Mp 1 , is used to generate bias voltage V casn . The drain of transistor Mp 1  is coupled to the ground voltage, while its source is coupled to the supply voltage via switches SW 7 A and SW 7 B. More specifically, the source of transistor Mp 1  is coupled to the output of the circuit (labeled “V casn ”) through switch SW 7 B. The output of the circuit (labeled “V casn ”) is coupled to the supply voltage via switch SW 7 A. 
     When the circuit is disabled, i.e., cas_en=0, switch SW 7 B is opened, and switch SW 7 A is closed. Conversely, switch SW 7 B is closed when the circuit is enabled, i.e., enable signal cas_en has a binary logic 1 value (cas_en=1). 
     The gate of transistor MP 1  is coupled to the supply voltage. Consequently, the source voltage of transistor Mp 1  will be V DD −|V thp |, where V thp  denotes the threshold voltage of transistor Mp 1 . Thus, when the circuit is enabled, the bias voltage V casn  equals V DD -|V thp |. Conversely, when the circuit is disabled (i.e., cas_en=0 and switch SW 7 A is closed), the bias voltage V casn  is at the supply voltage (V casn =V DD ). 
     By driving NMOS transistor M 5  in  FIG.  3    or  FIG.  4    using bias voltage V casn , the voltage across transistor M 1  in  FIG.  3    (or across one or more transistors in n-channel transistor network  26  in  FIG.  4   ) will be V DD −V th5 −|V thp | (where V th5  denotes the threshold voltage of transistor M 5 ) instead of V DD , which reduces the GIDL current of transistor M 1  and, hence, of the overall circuit. 
     In some cases, larger bias voltages than the voltages provided by the circuits in  FIGS.  5 - 6    may be desired.  FIG.  7    shows a circuit arrangement  50  for generating bias voltage V casp  according to an exemplary embodiment to provide a larger bias voltage. 
     In circuit arrangement  50 , two stages of the circuit shown in  FIG.  5    are used. The first stage, similar to the circuit in  FIG.  5   , includes native transistor Mn 1 , and switches SW 6 A and SW 6 B. The second stage similarly includes native transistor Mn 2 , and switches SW 6 C and SW 6 D. The gate of transistor Mn 2 , however, is driven by the output voltage of the first stage, i.e., by the common node between switches SW 6 A and SW 6 B. 
     In other words, while the gate of transistor Mn 1  is coupled to the ground voltage, the gate of transistor Mn 2  is driven to the output of the first stage, rather than the ground voltage. As a consequence, the bias voltage at the output of circuit arrangement  50  is V casp =2|V thn |, or twice as large as the output of circuit arrangement  30  in  FIG.  5   . 
     A similar technique may be used to generate bias voltage V casn .  FIG.  8    shows a circuit arrangement  60  according to another exemplary embodiment, whose output, V casn , is V DD −2|V thp |. 
     In circuit arrangement  60 , two stages of the circuit shown in  FIG.  6    are used. The first stage, similar to the circuit in  FIG.  6   , includes native transistor Mp 1 , and switches SW 7 A and SW 7 B. The second stage similarly includes native transistor Mp 2 , and switches SW 7 C and SW 7 D. The gate of transistor Mp 2 , however, is driven by the output voltage of the first stage, i.e., by the common node between switches SW 7 A and SW 7 B. 
     Thus, although the gate of transistor Mp 1  is coupled to the supply voltage, the gate of transistor Mp 2  is driven to the output of the first stage, rather than the supply voltage. As a consequence, the bias voltage at the output of circuit arrangement  60  is V casn =V DD −λ|V thn |, or twice as large as the output of circuit arrangement  40  in  FIG.  6   . 
     The concept of employing more than one circuit stage using native transistors to generate bias voltages may be generalized. For instance, in some embodiments, based on the GIDL data for a given semiconductor fabrication technology and circuit/device characteristics, and the maximum expected supply voltage, the number of circuit stages using native transistors may be selected or optimized in order to minimize or reduce the circuit&#39;s overall GIDL current. 
     In general, N stages may be used, where N is selected as described above.  FIG.  9    shows an N-stage circuit arrangement  70  for generating bias voltage V casp  according to an exemplary embodiment. Circuit arrangement  70  uses N stages of the circuit shown in  FIG.  5   , where the output of each stage drives the gate of the native transistor in the succeeding stage. 
     In other words, circuit arrangement  70  includes N stages, each of which includes a native transistor and a pair of switches, similar to the circuit arrangement in  FIG.  5   . Thus, the first stage includes transistor Mn 1  and switches SW 6 A and SW 6 B. The output of the first stage drives the gate of transistor Mn 2  in the second stage, which includes switches SW 6 C and SW 6 D. The output of the second stage drives the gate of the transistor in the third stage, and so on. 
     The last stage includes transistor MnN and switches SW 6 N- 1  and SW 6 N. The gate of native transistor MnN is driven by the output of the preceding stage (i.e., stage N−1), as described above. Consequently, the bias voltage at the output of circuit arrangement  70  is V casp =N|V thn | (assuming transistors Mn 1  through MnN have the same threshold voltage, V thn ). 
     In some embodiments, the bias voltage V casp  may be selectable (or variable or programmable or configurable). More specifically, the bias voltage V casp  may be selected from among the output voltages of one of the stages in circuit arrangement  70 . For instance, in some embodiments, an analog multiplexer may be used to select the output voltage of one of the stages in circuit arrangement  70 , and to supply that output voltage as the bias voltage V casp . 
       FIG.  10    shows an N-stage circuit arrangement  80  for generating bias voltage V casn  according to an exemplary embodiment. Circuit arrangement  80  uses N stages of the circuit shown in  FIG.  6   , where the output of each stage drives the gate of the native transistor in the succeeding stage. 
     Thus, circuit arrangement  80  includes N stages, each of which includes a native transistor and a pair of switches, similar to the circuit arrangement in  FIG.  6   . The first stage includes transistor Mp 1  and switches SW 7 A and SW 7 B. The output of the first stage drives the gate of transistor Mp 2  in the second stage, which includes switches SW 7 C and SW 7 D. The output of the second stage drives the gate of the transistor in the third stage, and so on. 
     The last stage includes transistor MpN and switches SW 7 N- 1  and SW 7 N. The gate of native transistor MpN is driven by the output of the preceding stage (i.e., stage N−1), as described above. Consequently, the bias voltage at the output of circuit arrangement  80  is V casn =V DD −N|V thp | (assuming transistors Mp 1  through MpN have the same threshold voltage, V thp ). 
     In some embodiments, the bias voltage V casn  may be selectable (or variable or programmable or configurable). More specifically, the bias voltage V casn  may be selected from among the output voltages of the stages in circuit arrangement  80 . For instance, in some embodiments, an analog multiplexer may be used to select the output voltage of one of the stages in circuit arrangement  80 , and to supply that output voltage as the bias voltage V casn . 
     One aspect of the disclosure relates to generating bias voltages V casp  and V casn  in situations where native devices are not available, e.g., not supported by the semiconductor fabrication process for a given implementation. In such scenarios, circuit arrangements that do not use native transistors may be used. 
       FIG.  11    shows a circuit arrangement  90  for generating bias voltage V casp  according to an exemplary embodiment. In this embodiment, bias voltage V casp  is generated by biasing diode-connected transistor  96  with a current supplied by current source  93 . Because the gate and drain voltages of transistor  96  are the same, a voltage V dioden  develops at the drain of transistor  96 . 
     When the circuit is disabled, i.e., cas_en=0, switch SW 11 A is opened, and switch SW 11 B is closed. Conversely, switch SW 11 A is closed and switch SW 11 B is opened when the circuit is enabled, i.e., enable signal cas_en has a binary logic 1 value (cas_en=1). 
     When the circuit is enabled, the bias voltage V casp  equals V dioden . Conversely, when the circuit is disabled (i.e., cas_en=0 and switch SW 11 B is closed), the bias voltage V casp  is at the circuit-ground potential (V casp =V SS ). 
     The current supplied by current source  93  generally depends on factors such as device characteristics and the levels of current used in the overall circuit. In some embodiments, the current may be relatively small, for example, on the order of 1 nA. 
       FIG.  12    shows a circuit arrangement  100  for generating bias voltage V casn  according to an exemplary embodiment. In this embodiment, bias voltage V casn  is generated by biasing diode-connected transistor  103  with a current sunk by current source  106 . Because the gate and drain voltages of transistor  103  are the same, a voltage V DD -V diodep  develops at the drain of transistor  103 . 
     When the circuit is disabled, i.e., cas_en=0, switch SW 12 B is opened, and switch SW 12 A is closed. Conversely, switch SW 12 B is closed and switch SW 12 A is opened when the circuit is enabled, i.e., enable signal cas_en has a binary logic 1 value (cas_en=1). 
     When the circuit is enabled, the bias voltage V casn  equals V DD −V diodep . Conversely, when the circuit is disabled (i.e., cas_en=0 and switch SW 12 A is closed), the bias voltage V casn  is at the supply voltage (V casn =V DD ). 
     The current supplied by current source  106  generally depends on factors such as device characteristics and the levels of current used in the overall circuit. In some embodiments, the current may be relatively small, for example, on the order of 1 nA. 
     The circuit arrangements in  FIGS.  11 - 12    may be cascaded to generate larger bias voltages. Thus, similar to the arrangements shown in  FIG.  9   , in some embodiments, several (generally N) of the circuit arrangement in  FIG.  11    may be cascaded to generate a larger bias voltage V casp . Similarly, similar to the arrangements shown in  FIG.  10   , in some embodiments, several (generally N) of the circuit arrangement in  FIG.  12    may be cascaded to generate a smaller bias voltage V casn . 
     Furthermore, in some embodiments, several diode-connected transistors may be used to generate larger bias voltages. For example, in some embodiments, rather than using a single diode-connected transistor  96  (as shown in  FIG.  11   ), several (generally N) diode-connected transistors may be cascade-coupled, similar to series-coupled diodes. The entire cascade conducts the current supplied by current source  93 . The bias voltage at the output of the circuit is V casp =N V dioden . 
     Similarly, in some embodiments, rather than using a single diode-connected transistor  103  (as shown in  FIG.  12   ), several (generally N) diode-connected transistors may be cascade-coupled, similar to series-coupled diodes. The entire cascade is coupled to current source  106 . The bias voltage at the output of the circuit is V casn =V DD −N V diodep . 
     Furthermore, in some embodiments, one or both of the bias voltages (V casn  and/or V casp ) may be selectable (or variable or programmable or configurable). More specifically, the bias voltage(s) may be selected from among the output voltages of the various stages in the circuits described above, or from a tap in a plurality of diode-connected transistors, described above. For instance, in some embodiments, an analog multiplexer may be used to select the output voltage of one of the stages in the circuits described above, or from a tap in a plurality of diode-connected transistors, described above. Such an arrangement may be used with either or both bias voltages (V casn  and/or V casp ), as desired. 
     Note that compared to the embodiments using native transistors, the circuit arrangements in  FIGS.  11 - 12    consume some power. In other words, the current sourced by current source  93  (see  FIG.  11   ) and the current sunk by current source  106  flow through transistor  96  and transistor  103 , respectively. As a result, the circuit arrangements in  FIGS.  11 - 12    have a finite static power consumption that depends on the current sourced by current source  93  and sunk by current source  106 . 
     Note that bias voltages V casp  and V casn  drive the gates of various transistors (e.g., transistors in p-channel transistor network  23  and transistors in n-channel transistor network  26  in  FIG.  4   ). Given that gate leakage currents of MOSFETs is relatively small, the circuits described above for generating the bias voltages may drive a relatively large number (or even all) of MOSFETs in a circuit or IC in order to reduce GIDL currents. 
     Furthermore, note that any of the circuit arrangements for generating bias voltages may be used to bias either p-channel or n-channel transistors (e.g., transistors in p-channel transistor network  23  or transistors in n-channel transistor network  26  in  FIG.  4   ). Thus, any of the circuit arrangements for generating bias voltages may be used to generate V casp  or V casn . 
     For example, an NMOS native device whose gate is coupled to ground and its drain coupled to the supply voltage will have a source voltage of |V thn |. Cascading N replicas of such a circuit generates a bias voltage given by N·|V thn |. That bias voltage may be used to bias a NMOS transistor to reduce its GIDL-current contribution. 
     Furthermore, note that the magnitudes of the bias voltages may be somewhat inexact. In other words, reduced GIDL current by virtue of the application of the bias voltages is relatively insensitive to the exact value of the bias voltages. Consequently, semiconductor-fabrication process variations have relatively small impacts or effects on the GIDL-current reduction process. 
     Various modifications of the circuitry described in relation to exemplary embodiments are possible and contemplated. For example, in situations where variable or programmable output bias voltages (e.g., by using analog multipliers, as described above) are not used or desired, some or all of the switches shown in  FIGS.  7 - 12    may be omitted. 
     More specifically, in some embodiments, switches in the circuit stages preceding the final circuit stage may be omitted. For example, in the circuit in  FIG.  7   , switches SW 6 A and SW 6 B may be omitted, and the source of transistor Mn 1  would drive the gate of transistor Mn 2 . Switches SW 6 C and SW 6 D may be used with the cas_en signal to program the final output bias voltage, as described above. If programming the output bias voltage is not used or desired, switches SW 6 C and SW 6 D may be omitted, and the source of transistor Mn 2  would provide the output bias voltage. Similar techniques and modifications may be used in  FIGS.  8 - 12   , as desired, and as persons of ordinary skill in the art will understand. 
       FIG.  13    depicts a composite plot  120  of simulation results to illustrate GIDL-current reduction according to an exemplary embodiment. Specifically, plot  123  shows the GIDL current of transistors in circuit arrangement  10  in  FIG.  2   . Plot  126  shows the GIDL current of transistors in circuit arrangement  20  in  FIG.  3   . Plot  129  shows the ratio of the GIDL currents in plots  126  and  129 . Note that, at a supply voltage of about 4 volts, the ratio is 1.096u, or a GIDL-current reduction by a factor of about 912,409. 
     Various embodiments, such as the embodiments described above, relate to reducing the power consumption of CMOS circuits in the low-power mode of operation. One aspect of the disclosure relates to improve the operation of relatively low-power or ultra-low-power circuits in which the bias currents are in the range of, say, 1 nA or a few nA. 
       FIG.  14    illustrates a circuit arrangement  140  for improving the operation of a CMOS circuit according to an exemplary embodiment. Transistor M 1  and constant current source  143  form a current source. Transistor M 2  is a current mirror, and mirrors the current conducted by transistor M 1 . 
     Transistor M 3  is similarly a current mirror that mirrors the current conducted by transistor M 1 . Note that both current mirrors are supplied by the same supply voltage, labeled Vd. 
     Unlike transistor M 2 , however, transistor M 3  is coupled in series with transistor M 4 . The gate of transistor M 4  is biased by bias voltage V cas . Thus, transistor M 4  constitutes a GIDL-current-reduction transistor that reduces the GIDL current of transistor M 4 . 
     In order to quantify the effect of GIDL-current-reduction transistor M 4 , the drain voltage was swept in a simulation from 3 volts to 4 volts while, the GIDL currents of transistors M 2  and M 4  were monitored (the GIDL current of transistor M 3  is close to zero). In the simulation, V cas  was set to 1.5 volts. 
       FIG.  15    depicts a composite plot  150  of the simulation results. Plot  153  shows the GIDL current of transistor M 2 . Plot  156  shows the GIDL current of transistor M 4 . Plot  159  shows the ratio of the GIDL currents of transistor M 4  to the GIDL current of transistor M 2 . The maximum ratio (1.8 m) in plot  159  implies that the GIDL current in transistor M 4  is reduced by a factor of about 555. 
     In exemplary embodiments, switches (e.g., switches SW 4 A-B, SW 5 A-B, etc.) are used to control the operation of the GIDL-current reduction circuitry. The switches may be implemented using a variety of techniques or circuitry, as desired. In some embodiments, the switches may be implemented as MOS field-effect transistors (MOSFETs), for example, p-channel transistors and/or n-channel transistors. 
     The choice of circuitry for a given implementation of the switches depends on a variety of factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology), target markets, target end-users, etc. 
     Although the embodiments described above relate to GIDL-current reduction techniques for analog circuits, the same or similar techniques may be used in digital circuits. During normal operations of the analog/digital circuits, the transistors in the CMOS circuit are biased to be fully on, such that the circuit is not slowed down or affected adversely (e.g., the supply voltage and the ground voltage are used as bias voltages). 
     Once the circuit is turned off, however, the supply and ground bias voltages can be replaced by the bias voltages generated by exemplary embodiments, such as shown in  FIGS.  5 - 12   . This technique can thus maintain the speed of the digital (or mixed-signal) circuit during normal mode of operation, and yet reduce the leakage current in the low-power mode of operation. 
     As noted, GIDL-current-reduction techniques according to the disclosure may be used in a variety of circuits, blocks, subsystems, and/or systems. For example, in some embodiments, GIDL-current-reduction circuits may be integrated in an IC, such as an MCU.  FIG.  16    shows a block diagram of an IC  550 , including an MCU, according to an exemplary embodiment. 
     IC  550  includes a number of blocks and circuits that may constitute digital, analog, and/or mixed-signal circuitry. The leakage-reduction techniques described above may be included to one or more such blocks or circuitry, as desired. 
     IC  550  includes a number of blocks (e.g., processor(s)  565 , data converter  605 , I/O circuitry  585 , etc.) that communicate with one another using a link  560 . In exemplary embodiments, link  560  may constitute a coupling mechanism, such as a bus, a set of conductors or semiconductors for communicating information, such as data, commands, status information, and the like. 
     IC  550  may include link  560  coupled to one or more processors  565 , clock circuitry  575 , and power management circuitry or PMU  580 . In some embodiments, processor(s)  565  may include circuitry or blocks for providing computing functions, such as central-processing units (CPUs), arithmetic-logic units (ALUs), and the like. In some embodiments, in addition, or as an alternative, processor(s)  565  may include one or more DSPs. The DSPs may provide a variety of signal processing functions, such as arithmetic functions, filtering, delay blocks, and the like, as desired. 
     Clock circuitry  575  may generate one or more clock signals that facilitate or control the timing of operations of one or more blocks in IC  550 . Clock circuitry  575  may also control the timing of operations that use link  560 . In some embodiments, clock circuitry  575  may provide one or more clock signals via link  560  to other blocks in IC  550 . 
     In some embodiments, PMU  580  may reduce an apparatus&#39;s (e.g., IC  550 ) clock speed, turn off the clock, reduce power, turn off power, or any combination of the foregoing with respect to part of a circuit or all components of a circuit. Further, PMU  580  may turn on a clock, increase a clock rate, turn on power, increase power, or any combination of the foregoing in response to a transition from an inactive state to an active state (such as when processor(s)  565  make a transition from a low-power or idle or sleep state to a normal operating state). 
     Link  560  may couple to one or more circuits  600  through serial interface  595 . Through serial interface  595 , one or more circuits coupled to link  560  may communicate with circuits  600 . Circuits  600  may communicate using one or more serial protocols, e.g., SMBUS, I 2 C, SPI, and the like, as person of ordinary skill in the art will understand. 
     Link  560  may couple to one or more peripherals  590  through I/O circuitry  585 . Through I/O circuitry  585 , one or more peripherals  590  may couple to link  560  and may therefore communicate with other blocks coupled to link  560 , e.g., processor(s)  365 , memory circuit  625 , etc. 
     In exemplary embodiments, peripherals  590  may include a variety of circuitry, blocks, and the like. Examples include I/O devices (keypads, keyboards, speakers, display devices, storage devices, timers, etc.). Note that in some embodiments, some peripherals  590  may be external to IC  550 . Examples include keypads, speakers, and the like. 
     In some embodiments, with respect to some peripherals, I/O circuitry  585  may be bypassed. In such embodiments, some peripherals  590  may couple to and communicate with link  560  without using I/O circuitry  585 . Note that in some embodiments, such peripherals may be external to IC  550 , as described above. 
     Link  560  may couple to analog circuitry  620  via data converter  605 . Data converter  405  may include one or more ADCs  605 B and/or one or more DACs  605 A. The ADC(s)  615  receive analog signal(s) from analog circuitry  620 , and convert the analog signal(s) to a digital format, which they communicate to one or more blocks coupled to link  560 . 
     Analog circuitry  620  may include a wide variety of circuitry that provides and/or receives analog signals. Examples include sensors, transducers, and the like, as person of ordinary skill in the art will understand. In some embodiments, analog circuitry  620  may communicate with circuitry external to IC  550  to form more complex systems, sub-systems, control blocks, and information processing blocks, as desired. 
     Leakage-current reduction techniques according to exemplary embodiments may be applied to analog circuitry  620 , as desired. Furthermore, leakage-current reduction techniques according to exemplary embodiments may be applied to ADC  605 A and/or DAC  605 A, as desired. In some embodiments, leakage-current reduction techniques are applied to the analog circuitry, whereas in some embodiments leakage-current reduction techniques are applied to the digital circuitry, yet in some other embodiments, leakage-current reduction techniques are applied to the analog circuitry and the digital circuitry. 
     Control circuitry  570  couples to link  560 . Thus, control circuitry  570  may communicate with and/or control the operation of various blocks coupled to link  560 . In addition, control circuitry  570  may facilitate communication or cooperation between various blocks coupled to link  560 . 
     In some embodiments, control circuitry  570  may initiate or respond to a reset operation. The reset operation may cause a reset of one or more blocks coupled to link  560 , of IC  550 , etc., as person of ordinary skill in the art will understand. For example, control circuitry  570  may cause PMU  580  to reset to an initial state. 
     In exemplary embodiments, control circuitry  570  may include a variety of types and blocks of circuitry. In some embodiments, control circuitry  570  may include logic circuitry, finite-state machines (FSMs), or other circuitry to perform a variety of operations, such as the operations described above. 
     Communication circuitry  640  couples to link  560  and also to circuitry or blocks (not shown) external to IC  550 . Through communication circuitry  640 , various blocks coupled to link  560  (or IC  550 , generally) can communicate with the external circuitry or blocks (not shown) via one or more communication protocols. Examples include USB, Ethernet, and the like. In exemplary embodiments, other communication protocols may be used, depending on factors such as specifications for a given application, as person of ordinary skill in the art will understand. 
     As noted, memory circuit  625  couples to link  560 . Consequently, memory circuit  625  may communicate with one or more blocks coupled to link  560 , such as processor(s)  365 , control circuitry  570 , I/O circuitry  585 , etc. Memory circuit  625  provides storage for various information or data in IC  550 , such as operands, flags, data, instructions, and the like, as persons of ordinary skill in the art will understand. 
     Memory circuit  625  may support various protocols, such as double data rate (DDR), DDR2, DDR3, and the like, as desired. In some embodiments, the memory read and/or write operations involve the use of one or more blocks in IC  550 , such as processor(s)  565 . A direct memory access (DMA) arrangement (not shown) allows increased performance of memory operations in some situations. More specifically, the DMA (not shown) provides a mechanism for performing memory read and write operations directly between the source or destination of the data and memory circuit  625 , rather than through blocks such as processor(s)  565 . 
     Memory circuit  625  may include a variety of memory circuits or blocks. In the embodiment shown, memory circuit  625  includes non-volatile (NV) memory  635 . In addition, or instead, memory circuit  625  may include volatile memory (not shown). NV memory  635  may be used for storing information related to performance or configuration of one or more blocks in IC  550 . 
     Referring to the figures, persons of ordinary skill in the art will note that the various blocks shown might depict mainly the conceptual functions and signal flow. The actual circuit implementation might or might not contain separately identifiable hardware for the various functional blocks and might or might not use the particular circuitry shown. For example, one may combine the functionality of various blocks into one circuit block, as desired. Furthermore, one may realize the functionality of a single block in several circuit blocks, as desired. The choice of circuit implementation depends on various factors, such as particular design and performance specifications for a given implementation. Other modifications and alternative embodiments in addition to the embodiments in the disclosure will be apparent to persons of ordinary skill in the art. Accordingly, the disclosure teaches those skilled in the art the manner of carrying out the disclosed concepts according to exemplary embodiments, and is to be construed as illustrative only. Where applicable, the figures might or might not be drawn to scale, as persons of ordinary skill in the art will understand. 
     The particular forms and embodiments shown and described constitute merely exemplary embodiments. Persons skilled in the art may make various changes in the shape, size and arrangement of parts without departing from the scope of the disclosure. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described. Moreover, persons skilled in the art may use certain features of the disclosed concepts independently of the use of other features, without departing from the scope of the disclosure.