Patent Publication Number: US-2022230666-A1

Title: Memory device that includes a duty correction circuit, memory controller that includes a duty sensing circuit, and storage device that includes a memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0008911, filed on Jan. 21, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     Embodiments of the inventive concept relate to a memory device, a memory controller, and a storage device, and more particularly, to a memory device that includes a duty correction circuit, a memory controller that includes a duty sensing circuit, and a storage device that includes a memory device. 
     DISCUSSION OF RELATED ART 
     Non-volatile memory (NVM) is a type of memory that may retain stored information even without power. An electronic device may include a non-volatile memory device and a controller that may control the non-volatile memory. A non-volatile memory device may communicate with a controller at a relatively low frequency compared to a high-speed memory device such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device. 
     SUMMARY 
     Embodiments of the inventive concept provide a memory device, a memory controller, and a storage device that may reduce a duty correction circuit (DCC) training time and reduce duty cycle degradation due to memory chip variation and channel variation. 
     According to an embodiment of the inventive concept, a storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal and output the first signal, and a second memory chip configured to generate a second signal based on a second clock signal and output the second signal. The chip is configured to receive the first signal and generate and output a first comparison signal based on a duty cycle of the first signal and receive the second signal and generate and output a second comparison signal based on a duty cycle of the second signal. The first memory chip is further configured to receive the first comparison signal and generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to receive the second comparison signal and generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal. 
     According to an embodiment of the inventive concept, a memory device includes a clock pin, a plurality of memory chips, and a plurality of input/output pins commonly connected to the plurality of memory chips. The clock pin is configured to receive a clock signal from outside the memory device. The plurality of memory chips is configured to perform duty correction operations on a plurality of internal clock signals generated based on the clock signal. The plurality of memory chips is further configured to perform the duty correction operations in parallel and during a training period. The plurality of input/output pins commonly includes a first pin, a second pin, a third pin, and a fourth pin. The plurality of memory chips includes a first memory chip and a second memory chip. The first memory chip is configured to generate a first signal by adjusting a duty cycle of a first internal clock signal of the plurality of internal clock signals based on a first comparison signal received from the second pin and output the first signal through the first pin. The second memory chip is configured to generate a second signal by adjusting a duty cycle of a second internal clock signal of the plurality of internal clock signals based on a second comparison signal received from the fourth pin and output the second signal through the third pin. 
     According to an embodiment of the inventive concept, a memory controller includes a clock pin configured to output a clock signal, a plurality of input/output pins commonly connected to a plurality of memory chips that includes a first memory chip and a second memory chip, and a plurality of duty sensing circuits. The plurality of input/output pins includes a first pin, a second pin, a third pin, and a fourth pin. Each duty sensing circuit of the plurality of duty sensing circuits respectively corresponds to a memory chip of the plurality of memory chips. The plurality of duty sensing circuits includes a first duty sensing circuit and a second duty sensing circuit. The first duty sensing circuit is configured to receive a first signal from the first memory chip through the first pin and provide a first comparison signal based on a duty cycle of the first signal to the first memory chip through the second pin. The second duty sensing circuit is configured to receive a second signal from the second memory chip through the third pin and provide a second comparison signal according to a duty cycle of the second signal to the second memory chip through the fourth pin. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features of the inventive concept will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which: 
         FIG. 1  is a schematic block diagram of a storage device according to an embodiment of the inventive concept; 
         FIG. 2  is a diagram of the memory device of  FIG. 1  according to an embodiment of the inventive concept; 
         FIG. 3  is a block diagram of a storage device according to an embodiment of the inventive concept; 
         FIG. 4  is a timing diagram of signals according to a duty correction operation performed in the storage device of  FIG. 3 ; 
         FIG. 5  is a timing diagram of a duty correction sequence according to a comparative example and a duty correction sequence according to an embodiment of the inventive concept; 
         FIG. 6  is a detailed block diagram of the storage device of  FIG. 3  according to an embodiment of the inventive concept; 
         FIG. 7  is a block diagram of a controller according to an embodiment of the inventive concept; 
         FIG. 8  is a block diagram of a memory chip according to an embodiment of the inventive concept; 
         FIG. 9  is a circuit diagram of a duty cycle adjustment circuit according to an embodiment of the inventive concept; 
         FIG. 10  is a detailed block diagram of the storage device of  FIG. 6  according to an embodiment of the inventive concept; 
         FIG. 11  is a flowchart of operations of a controller and first and second memory chips according to an embodiment of the inventive concept; 
         FIG. 12  is a schematic block diagram of a storage device according to an embodiment of the inventive concept; 
         FIG. 13  is a schematic block diagram of a storage device according to an embodiment of the inventive concept; 
         FIG. 14  is a block diagram of a memory system according to an embodiment of the inventive concept; and 
         FIG. 15  is a cross-sectional view of a bonding VNAND (B-VNAND) structure that may be implemented in a memory device according to an embodiment of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings. 
     As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. 
     It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the embodiments. 
       FIG. 1  is a schematic block diagram of a storage device SD according to an embodiment of the inventive concept. 
     Referring to  FIG. 1 , the storage device SD may include a memory device  10  and a chip  50 . The memory device  10  may be a non-volatile memory device that includes a plurality of memory chips  100 . Each of the memory chips  100  may include a duty correction circuit (DCC) of a plurality of DCCs  120 , and the chip  50  may include a plurality of duty sensing circuits  200 , respectively corresponding to the memory chips  100 . In an embodiment, the chip  50  may correspond to a memory controller chip or a controller chip. In an embodiment, the chip  50  may correspond to a buffer chip between the memory device  10  and a memory controller. In an embodiment, the chip  50  may correspond to a separate sensing chip. 
     As the memory device  10  includes the plurality of memory chips  100 , the memory device  10  may be referred to as a “multi-chip memory”. For example, each memory chip of the plurality of memory chips  100  may include a dual die package (DDP), a quadruple die package (QDP), or an octuple die package (ODP). However, the plurality of memory chips  100  may alternatively or additionally correspond to a plurality of memory dies, and the memory device  10  may accordingly be referred to as a “multi-die package”. 
     In an embodiment, each memory chip of the plurality of memory chips  100  may include a non-volatile memory chip. For example, each memory chip of the plurality of memory chips  100  may include a NAND flash memory chip. For example, the plurality of memory chips  100  may include a vertical NAND (VNAND) flash memory chip. The VNAND flash memory chip may include a plurality of word lines vertically stacked on a substrate and a plurality of cell strings that respectively include a plurality of memory cells that are respectively connected to the word lines. However, the plurality of memory chips  100  may alternatively or additionally include resistive memory chips such as a resistive RAM (ReRAM) chip, a phase change RAM (PRAM) chip, or a magnetic RAM (MRAM) chip. 
     The memory device  10  and the chip  50  may communicate through a plurality of signal lines that include a clock signal line, a plurality of input/output signal lines, and a data strobe signal line. For example, the memory device  10  and the chip  50  may implement and/or follow a standard protocol such as Toggle or ONFI. The chip  50  may transmit a clock signal CLK to the memory device  10  through the clock signal line. In an embodiment, the clock signal CLK may toggle at a certain frequency in a specific interval, and accordingly, the storage device SD may be an asynchronous system. 
     For example, the clock signal CLK may toggle at a frequency corresponding to a data input/output speed. The chip  50  may transmit a command and an address to the memory device  10  through the input/output signal lines and data DQ between the chip  50  and the memory device  10  through input/output signal lines. Furthermore, a data strobe signal DQS may be transmitted between the chip  50  and the memory device  10  through the data strobe signal line. Signal lines through which the clock signal CLK, the data DQ, and the data strobe signal DQS are transmitted or received may form a channel. 
     The memory device  10  may include a clock pin P 1  connected to the clock signal line, a plurality of input/output pins P 2  respectively connected to the plurality of input/output signal lines, and a data strobe pin P 3  connected to the data strobe signal line. The plurality of memory chips  100  may be commonly connected to each of the clock pin P 1 , the plurality of input/output pins P 2 , and the data strobe pin P 3 . The chip  50  may include a clock pin P 1 ′, a plurality of input/output pins P 2 ′, and a data strobe pin P 3 ′, respectively connected to the clock signal line and the clock pin P 1 , the plurality of input/output signal lines and plurality of the input/output pins P 2 , and data strobe signal line and the data strobe pin P 3 . For example, the plurality of input/output pins P 2  may include eight input/output pins, but the disclosure is not necessarily limited thereto. 
     During a read operation of the memory device  10 , the memory device  10  may receive the clock signal CLK (e.g., a read enable signal nRE) from the chip  50  and may generate and output the data strobe signal DQS and the data DQ in response. In a double data rate (DDR) mode, the output of the data DQ may be synchronized with a rising edge and a falling edge of the data strobe signal DQS, and the memory device  10  may therefore sequentially output the data DQ. Thus, data windows of first and second data that are sequentially output may correspond to a logic high period and a logic low period of the data strobe signal DQS. As the data strobe signal DQS may be generated based on the clock signal CLK, the data windows of the first and second data may be determined based on a ratio of the logic high period and the logic low period of the clock signal CLK. 
     In a comparative example, a “duty mismatch” may be present in a clock signal when a logic high period and a logic low period of the clock signal are different from each other. In other words, a ratio between the logic high period and the logic low period (i.e., a duty ratio) that is not 1:1 may indicate a duty mismatch. When a clock signal includes a duty mismatch, first and second data of data that correspond to the clock signal may include data windows that are different from each other, and an effective data window of the first and second data may decrease. As a result, a memory device&#39;s read operation performance may degrade. Accordingly, there is an opportunity to remove a duty mismatch of a clock signal and secure an effective data window by performing a duty correction operation to the clock signal. 
     In contrast to the comparative example, in an embodiment, each memory chip of the plurality of memory chips  100  may include a DCC of the plurality of DCCs  120 , and the chip  50  may include the plurality of duty sensing circuits  200  respectively corresponding to the memory chips  100 . Each duty sensing circuit of the plurality of duty sensing circuits  200  may generate a comparison signal based on a duty cycle of a signal received from a corresponding memory chip of the plurality of memory chips  100 , and the DCC  120  of each memory chip of the plurality of memory chips  100  may correct a duty cycle of an internal clock signal based on the comparison signal. As such, the DCC  120  of each memory chip of the plurality of memory chips  100  and each corresponding duty sensing circuit of the plurality of duty sensing circuits  200  may form a duty correction loop (i.e., a DCC loop). 
     In a comparative example, a memory device implemented as an asynchronous system it may not have a frequency that always toggles, and so data correction circuits of the memory device may perform duty correction operations only in a period in which a clock signal is applied. For example, the memory device may perform a duty correction operation by using a read enable signal as a clock signal. When a duty correction operation is performed in a read-out period (in which read data is output) during a read period of a read operation of the memory device  10 , a clock duty may be changed for each clock cycle by the duty correction operation, and thus an effective data window of read data may decrease. 
     In contrast to the comparative example, in an embodiment, the plurality of DCCs  120  may perform a duty correction operation in a dedicated period rather than a read-out period. Hereinafter, this dedicated period may be referred to as a “DCC training period”, and an operation performed by the plurality of DCCs  120  during the DCC training period may be referred to as “DCC training”. In an embodiment, the DCC training period may include a predetermined number of clock cycles. During the DCC training period, the clock signal CLK (e.g., the read enable signal nRE) may toggle at a preset frequency. 
     In an embodiment, the DCC training may be performed in a read latency period before a read-out period of a read period. In an embodiment, the DCC training may be performed in a power-up period in which power is applied to the storage device SD. When the DCCs of the plurality of DCCs  120  sequentially perform the DCC training, the DCC training period becomes considerably longer. When the number of memory chips of the plurality of memory chips  100  included in the memory device  10  is m, and the DCC training period for each memory chip of the plurality of memory chips  100  is A, the total DCC training period of the memory device  10  corresponds to m×A (i.e., the product of m and A). 
     In a comparative example, as the number of memory chips of included in a memory device increases, a total DCC training period may become longer, and thus the performance of the memory device may degrade. However, in contrast to the comparative example, in an embodiment, even when the number of memory chips of the plurality of memory chips  100  included in the memory device  10  increases, the plurality of DCCs  120  may maintain a constant total DCC training period by performing the DCC training in parallel, and accordingly, performance degradation of the memory device  10  may be mitigated. 
     In a comparative example, each memory chip of a memory device may further include an output driver or a transmitting driver, and a duty corrected signal in a DCC of each of the memory chips may be output through the output driver. In this state, a mismatch of resistances of output drivers may be generated due to a variation of the memory chips (for example, a memory chip variation or a memory die variation), and accordingly, a duty mismatch may be generated again in a process in which a duty corrected signal is output through the output driver. Furthermore, duty cycle degradation may be generated in a process in which a signal output from the output driver is transmitted through a channel. Consequently, while a duty cycle of a duty corrected signal may be 50% in a DCC, due to memory die variation and channel variation, the duty cycle of a signal received from an input buffer of a controller may be degraded to about 45% to 55%. 
     However, in contrast to the comparative example, in an embodiment, the plurality of duty sensing circuits  200  of the chip  50  may perform a duty sensing operation on a signal received from an input buffer included in a controller, and duty cycle degradation due to the above-described memory die variation and channel variation may be corrected. In detail, each duty sensing circuit of the plurality of duty sensing circuits  200  may sense the duty cycle of an input signal and provide a comparison signal based on a sensing result to the plurality of DCCs  120 . Accordingly, as each DCC of the plurality of DCCs  120  may perform a duty correction operation on the clock signal CLK based on the comparison signal, duty cycle degradation due to memory die variation and channel variation may be corrected. Accordingly, a duty cycle of an output signal of each DCC of the plurality of DCCs  120  might not be 50%, and a duty cycle of a signal received by the memory device  10  from the input buffer of the chip  50  (i.e., a signal input to the duty sensing circuits  200 ) may be corrected to be 50%. 
     In some embodiments, the storage device SD may be an internal memory included in an electronic device. For example, the storage device SD may include a solid-state drive (SSD), an embedded universal flash storage (UFS) memory device, or an embedded multi-media card (eMMC). In some embodiments, the storage device SD may be an external memory that is detachable from an electronic device. For example, the storage device SD may include a UFS memory card, a compact flash (CF), a secure digital (SD), a micro secure digital (micro-SD), a mini secure digital (mini-SD), an extreme digital (xD), or a Memory Stick. 
       FIG. 2  is a diagram of the memory device  10  of  FIG. 1  according to an embodiment of the inventive concept. 
     Referring to  FIG. 2 , the memory device  10  may include a substrate SUB and first to n th  memory chips  100   a  to  100   n , where n is a positive integer. The first to n th  memory chips  100   a  to  100   n  may be vertically stacked on the substrate SUB. A plurality of input/output pins Pn may be arranged on the substrate SUB, and input/output nodes ND of the first to n th  memory chips  100   a  to  100   n  may be respectively connected to an input/output pin of the plurality of input/output pins Pn. For example, an input/output pin Pn and an input/output node ND may be connected to each other by wire bonding. In an embodiment in which the plurality of input/output pins Pn and the input/output nodes ND are connected by wire bonding, the first to n th  memory chips  100   a  to  100   n  may be stacked with a staircase skew in a horizontal direction, where a portion of an upper memory chip does not overlap a lower memory chip stacked beneath the upper memory chip. 
       FIG. 3  is a block diagram of a storage device SD 1  according to an embodiment of the inventive concept. 
     Referring to  FIG. 3 , the storage device SD 1  may include the memory device  10  and the controller  20 , and the memory device  10  may include first and second memory chips  100   a  and  100   b . In an embodiment, the number of memory chips of the plurality of memory chips included in the memory device  10  may be alternatively or additionally be three or more. The memory device  10  may include a plurality of input/output pins that include the clock pin P 1  and first to fourth pins P 2   a  to P 2   d . The first and second memory chips  100   a  and  100   b  may be commonly connected to each of the clock pin P 1  and the first to fourth pins P 2   a  to P 2   d . The controller  20  may include a clock pin P 1 ′ and first to fourth pins P 2   a ′ to P 2   d ′, and the clock pin P 1 ′ and the first to fourth pins P 2   a ′ to P 2   d ′ may be respectively connected to the clock pin P 1  and the first to fourth pins P 2   a  to P 2   d  of the memory device  10 . The controller  20  may correspond to a memory controller. For example, the memory device  10  and the controller  20  may implement and/or follow a standard protocol such as Toggle or ONFI. 
     The first memory chip  100   a  may include a first repeater  110   a  and a first DCC  120   a , and the second memory chip  100   b  may include a second repeater  110   b  and a second DCC  120   b . The controller  20  may include a plurality of duty sensing circuits that include a first duty sensing circuit  210  corresponding to the first memory chip  100   a  and a second duty sensing circuit  220  corresponding to the second memory chip  100   b . For example, in the DCC training period, the first and second pins P 2   a  and P 2   b  may be assigned to the first memory chip  100   a , and the third and fourth pins P 2   c  and P 2   d  may be assigned to the second memory chip  100   b . Accordingly, in the DCC training period, in the first memory chip  100   a , the input buffer and the output driver respectively connected to the third and fourth pins P 2   c  and P 2   d  may be disabled, and in the second memory chip  100   b , the input buffer and the output driver respectively connected to the first and second pins P 2   a  and P 2   b  may be disabled. 
     The first DCC  120   a  may be connected to the first and second pins P 2   a  and P 2   b , the first duty sensing circuit  210  may be connected to the first and second pins P 2   a ′ and P 2   b ′, and the first DCC  120   a  and the first duty sensing circuit  210  may form a first DCC loop DCC 1 . Accordingly, the first duty sensing circuit  210  may sense the duty cycle of a first signal received from the first memory chip  100   a  and generate a first comparison signal, and the first DCC  120   a  may perform a first duty correction operation on a clock signal CLK based on the first comparison signal and generate a first correction clock signal. 
     Furthermore, the second DCC  120   b  may be connected to the third and fourth pins P 2   c  and P 2   d , the second duty sensing circuit  220  may be connected to the third and fourth pins P 2   c ′ and P 2   d ′, and the second DCC  120   b  and the second duty sensing circuit  220  may form a second DCC loop DCC 2 . Accordingly, the second duty sensing circuit  220  may sense the duty cycle of a second signal received from the second memory chip  100   b  and generate a second comparison signal, and the second DCC  120   b  may perform a second duty correction operation on the clock signal CLK based on the second comparison signal and generate a second correction clock signal. 
       FIG. 4  is a timing diagram of signals according to the duty correction operation performed in the storage device SD 1  of  FIG. 3 . 
     In a comparative example, a memory device included in an asynchronous system might not have a frequency that always toggles, and DCCs in the memory device may therefore perform a duty correction operation only in a period in which a clock signal is applied. However, in contrast to the comparative example, in an embodiment shown by  FIGS. 3 and 4 , the memory device  10  may perform a duty correction operation by using a read enable signal nRE as a clock signal CLK. In an embodiment, the first and second DCCs  120   a  and  120   b  may perform a duty correction operation in a DCC training period DCC_PD. 
     In the DCC training period DCC_PD, the first memory chip  100   a  may provide a first signal SIG 1  to the first pin P 2   a , and the second memory chip  100   b  may provide a second signal SIG 2  to the third pin P 2   c . The duty cycle of each of the first and second signals SIG 1  and SIG 2  might not be 50%. 
     The first duty sensing circuit  210  may sense the duty cycle of the first signal SIG 1  and generate a first comparison signal, and the first DCC  120   a  may perform a duty correction operation on the read enable signal nRE based on the first comparison signal and correct the duty cycle of the first signal SIG 1  close to 50%. Likewise, the second duty sensing circuit  220  may sense the duty cycle of the second signal SIG 2  and generate a second comparison signal, and the second DCC  120   b  may perform a duty correction operation on the read enable signal nRE based on the second comparison signal and correct the second signal SIG 2  close to 50%. 
       FIG. 5  is a timing diagram of a duty correction sequence  51  according to a comparative example and a duty correction sequence  52  according to an embodiment of the inventive concept. 
     Referring to  FIGS. 3 and 5  together, according to a comparative example, a controller may sequentially and respectively perform DCC trainings on a plurality of memory chips. For example, the duty correction sequence  51  may include a first chip enable period  511  and a first DCC training period  512  for performing DCC training on a first memory chip. In the first chip enable period  511 , a controller may transmit a chip enable command CER CMD and an address ADDR (for example, 00h) to a memory device. 
     In the first DCC training period  512 , the controller may transmit a DCC training command DCC CMD and the address ADDR to the memory device, and then the controller may perform a duty correction operation on a signal received from the first memory chip during a toggle period of a preset read enable signal nRE. As the controller sequentially performs DCC operations on the plurality of memory chips, the duty correction sequence  51  may further include a second chip enable period  513  and a second DCC training period  514  for performing DCC training on a second memory chip. As such, a total DCC training period may be further increased based on the number of memory chips included in the memory device. 
     However, in contrast to the comparative example, according to an embodiment of the inventive concept, the first and second memory chips  100   a  and  100   b  included in the memory device  10  may perform DCC trainings in parallel. Accordingly, the duty correction sequence  52  may include a chip enable period  521  and a DCC training period  522  for performing DCC training on a plurality of memory chips that include the first and second memory chips  100   a  and  100   b . In the chip enable period  521 , the controller  20  may select the plurality of memory chips by transmitting the chip enable command CER CMD and the address ADDR (for example, 80h) to the memory device  10 . 
     The DCC training period  522  may include a first period  522   a , a second period  522   b , and a third period  522   c . In the first period  522   a , the controller  20  may transmit the DCC training command DCC CMD to the memory device  10 , and in the second period  522   b , the controller  20  may transmit the address ADDR to the memory device  10 . The third period  522   c  may correspond to a toggle period of the preset read enable signal nRE, and in the third period  522   c , each memory chip of the plurality of memory chips and a corresponding duty sensing circuit of the plurality of duty sensing circuits may perform a duty correction operation on the read enable signal nRE. In detail, in the third period  522   c , the first memory chip  100   a  and the first duty sensing circuit  210  may perform a first duty correction operation on the read enable signal nRE through the first DCC loop DCC 1 , and the second memory chip  100   b  and the second duty sensing circuit  220  may perform a second duty correction operation on the read enable signal nRE through the second DCC loop DCC 2 . Accordingly, the first and second duty correction operations may be substantially simultaneously performed. 
       FIG. 6  is a detailed block diagram of the storage device SD 1  of  FIG. 3  according to an embodiment of the inventive concept. 
     Referring to  FIG. 6 , the first memory chip  100   a  may include the first repeater  110   a  and the first DCC  120   a , and the first DCC  120   a  may include a first duty cycle adjustment (DCA) circuit  121   a  and a first up/down counter  122   a . The first duty sensing circuit  210  may include a first charge pump  211  and a first comparator  212 . The first DCA circuit  121   a , the first charge pump  211 , the first comparator  212 , and the first up/down counter  122   a  may form the first DCC loop DCC 1  Likewise, the second memory chip  100   b  may include the second repeater  110   b  and the second DCC  120   b , and the second DCC  120   b  may include a second DCA circuit  121   b  and a second up/down counter  122   b . The second duty sensing circuit  220  may include a second charge pump  221  and a second comparator  222 . The second DCA circuit  121   b , the second charge pump  221 , the second comparator  222 , and the second up/down counter  122   b  may form the second DCC loop DCC 2 . Hereinafter, the operation of the first DCC loop DCC 1  will be described in detail, and the description of the operation of the first DCC loop DCC 1  may also describe an operation of the second DCC loop DCC 2 . 
     The first DCA circuit  121   a  may generate a first signal SIG 1  based on a first internal clock signal CLK 1   i  included in a clock signal CLK, and may output the first signal SIG 1  through the first pin P 2   a . The first charge pump  211  may receive the first signal SIG 1  through the first pin P 2   a ′, and may generate a pair of charge pump signals by performing a charge pumping operation based on the first signal SIG 1 . The first comparator  212  may generate a first comparison signal CP 1  by comparing the pair of charge pump signals, and output the first comparison signal CP 1  through the second pin P 2   b ′. The first up/down counter  122   a  may receive the first comparison signal CP 1  through the second pin P 2   b , and generate a first control signal CS 1  based on the first comparison signal CP 1 . The first DCA circuit  121   a  may generate a first corrected signal having a corrected duty by adjusting the duty cycle of the first internal clock signal CLK 1   i  based on the first control signal CS 1 , and may output the first corrected signal having a corrected duty. 
     In some embodiments, the first comparator  212  may be included in the first DCC  120   a  of the first memory chip  100   a , and/or the second comparator  222  may be included in the second DCC  120   b  of the second memory chip  100   b . In some embodiments, the first up/down counter  122   a  may be included in the first duty sensing circuit  210 , and/or the second up/down counter  122   b  may be included in the second duty sensing circuit  220 . As such, detailed configurations of the first and second duty sensing circuits  210  and  220  and/or the first and second DCCs  120   a  and  120   b  may be freely changed according to an embodiment. 
       FIG. 7  is a block diagram of the controller  20  according to an embodiment of the inventive concept. 
     Referring to  FIG. 7 , the controller  20  may include the first charge pump  211 , the first comparator  212 , a read enable signal generator  230 , first and second output drivers  240  and  260 , an input buffer  250 , and first to third pads  201 ,  202 , and  203 . The first pad  201  may correspond to the clock pin P 1 ′ of  FIG. 6 , and the second and third pads  202  and  203  may respectively correspond to the first and second pins P 2   a ′ and P 2   b ′ of  FIG. 6 . The read enable signal generator  230  may generate the read enable signal nRE in the DCC training period  522  (refer to  FIG. 5 ), and the read enable signal nRE may be provided to the first pad  201  through the first output driver  240 . 
     The input buffer  250  may receive the first signal SIG 1  through the second pad  202 , and a first positive signal SIG 1 _P and a first negative signal SIG 1 _N may be output from the input buffer  250  in response. The first positive signal SIG 1 _P and the first negative signal SIG 1 _N may have a duty cycle based on the first signal SIG 1 , the first positive signal SIG 1 _P may have a normal phase corresponding to the first signal SIG 1 , and the first negative signal SIG 1 _N may have a reverse phase to a phase of the first signal SIG 1 . However, embodiments of the inventive concept are not necessarily limited thereto, and in some embodiments, a repeater may be further provided between the input buffer  250  and the first charge pump  211 . The repeater may receive the first signal SIG 1  from the input buffer  250  and may output the first positive signal SIG 1 _P and the first negative signal SIG 1 _N. Furthermore, in some embodiments, the repeater may output the first signal SIG 1  and a reference signal corresponding to the first signal SIG 1 . 
     The first charge pump  211  may generate first and second charge pump signals CPUMPP and CPUMPN respectively based on the first positive signal SIG 1 _P and the first negative signal SIG 1 _N. For example, an amplitude (e.g., a voltage) of the first charge pump signal CPUMPP may increase in a logic high period of the first positive signal SIG 1 _P, and may decrease in a logic low period of the first positive signal SIG 1 _P. Likewise, an amplitude (e.g., a voltage) of the second charge pump signal CPUMPN may increase in a logic high period of the first negative signal SIG 1 _N, and may decrease in a logic low period of the first negative signal SIG 1 _N. Accordingly, a duty mismatch may be generated in the first positive signal SIG 1 _P and the first negative signal SIG 1 _N, and thus a logic high period may be relatively long in the first positive signal SIG 1 _P and a logic high period may be relatively short in the first negative signal SIG 1 _N. After several clock cycles of the first positive signal SIG 1 _P and the first negative signal SIG 1 _N have elapsed, the amplitude of the first charge pump signal CPUMPP may increase, whereas the amplitude of the second charge pump signal CPUMPN may decrease. 
     The first comparator  212  may compare the first and second charge pump signals CPUMPP and CPUMPN, and may generate the first comparison signal CP 1  based on the comparison. For example, when the amplitude of the first charge pump signal CPUMPP is greater than the amplitude of the second charge pump signal CPUMPN, the first comparator  212  may generate the first comparison signal CP 1  to be logic high, and when the amplitude of the first charge pump signal CPUMPP is not greater than the amplitude of the second charge pump signal CPUMPN, the first comparator  212  may generate the first comparison signal CP 1  to be logic low. The first comparison signal CP 1 , generated from the first comparator  212 , may be output to the third pad  203  through the second output driver  260 . 
       FIG. 8  is a block diagram of a memory chip  100   j  according to an embodiment of the inventive concept. 
     Referring to  FIG. 8 , the memory chip  100   j  is a memory chip of the plurality of memory chips  100 , and the first and second memory chips  100   a  or  100   b  of  FIG. 6  may be implemented as the memory chip  100   j . The memory chip  100   j  may include a repeater  110 , a DCA circuit  121 , an up/down counter  122 , a timing controller  123 , a multiplexer  130 , an output driver  145 , an input buffer  150 , and first to third pads  101 ,  102 , and  103 . The first pad  101  may correspond to the clock pin P 1  of  FIG. 6 , and the second and third pads  102  and  103  may correspond to the first and second pins P 2   a  and P 2   b  of  FIG. 6 . 
     The repeater  110  may receive the read enable signal nRE from the controller  20  through the first pad  101 , and an internal read enable signal nREi may be generated from the received read enable signal nRE. When a duty mismatch is generated in the read enable signal nRE, a duty mismatch may be generated in the internal read enable signal nREi. When a duty mismatch is not generated in the read enable signal nRE, a duty mismatch may be generated in the internal read enable signal nREi while passing through the repeater  110 . 
     The DCA circuit  121  may generate a corrected read enable signal nREc (that is, a corrected clock signal) in response to the internal read enable signal nREi. The multiplexer  130  may receive first and second internal data D 1  and D 2 , and generate the first signal SIG 1  based on the first and second internal data D 1  and D 2  and the corrected read enable signal nREc. The generated first signal SIG 1  may be output to the second pad  102  through the output driver  145 . The multiplexer  130  may output the first internal data D 1  in a logic high period of the corrected read enable signal nREc, and may output the second internal data D 2  in a logic low period of the corrected read enable signal nREc, thereby generating a signal SIG. 
     In an embodiment, the memory chip  100   j  may include a random data generator, and the first and second internal data D 1  and D 2  may be generated by the random data generator. In an embodiment, the memory chip  100   j  may include a register, and the first and second internal data D 1  and D 2  may be data that is stored in the register. For example, the first internal data D 1  may be logic 1, and the second internal data D 2  may be logic 0. In an embodiment, in the DCC training period  522  (refer to  FIG. 5 ), the first internal data D 1  may be fixed to logic 1 (e.g., a power voltage VDD) and the second internal data D 2  may be fixed to logic 0 (e.g., a ground voltage GND). 
     The input buffer  150  may receive a comparison signal CP from the controller  20  through the third pad  103 , and may provide the received comparison signal CP to the up/down counter  122 . The up/down counter  122  may generate a control signal CS in response to the comparison signal CP. For example, the control signal CS may be generated as a 4-bit digital code. When the comparison signal CP is logic high, a value of the control signal CS may increase by 1, and when the comparison signal CP is logic low, the value of the control signal CS may decrease by 1. 
     The timing controller  123  may generate a plurality of timing control signals that are synchronized with the internal read enable signal nREi. For example, the timing controller  123  may enable the up/down counter  122  by generating and providing an enable signal EN_CNT to the up/down counter  122  Furthermore, for example, the timing controller  123  may activate a counting operation of the up/down counter  122  by generating an activation signal ACT_CNT and providing the activation signal ACT_CNT to the up/down counter  122 , and the up/down counter  122  may generate the control signal CS in response to the activation signal ACT_CNT. 
       FIG. 9  is a circuit diagram of the DCA circuit  121  according to an embodiment of the inventive concept. 
     Referring to  FIG. 9 , the DCA circuit  121  may include a first plurality of PMOS transistors PM 11  to PM 14 , a second plurality of PMOS transistors PM 21  to PM 25 , a first plurality of NMOS transistors NM 11  to NM 14 , and a second plurality of NMOS transistors NM 21  to NM 25 . The first plurality of PMOS transistors PM 11  to PM 14  may be commonly connected to a power voltage terminal VDD, the first plurality of NMOS transistors NM 11  to NM 14  may be commonly connected to a ground voltage terminal VSS, and the first plurality of PMOS transistors PM 11  to PM 14  and the first plurality of NMOS transistors NM 11  to NM 14  may be driven by the control signal CS. The second plurality of PMOS transistors PM 21  to PM 25  and the second plurality of NMOS transistors NM 21  to NM 25  may be driven by the internal read enable signal nREi. 
     For example, the control signal CS may be a 4-bit digital code. For example, when the value of the control signal CS increases by 1, some of the first plurality of PMOS transistors PM 11  to PM 14  may turn off, and some of the first plurality of NMOS transistors NM 11  to NM 14  may turn on. Accordingly, compared with the internal read signal nREi, a logic high period of an adjustment internal read signal nREc may be reduced. For example, when the value of the control signal CS decreases by 1, some of the first plurality of PMOS transistors PM 11  to PM 14  may turn on, and some of the first plurality of NMOS transistors NM 11  to NM 14  may turn off. Accordingly, compared with the internal read signal nREi, the logic high period of the adjustment internal read signal nREc may be increased. 
       FIG. 10  is a detailed block diagram of the storage device SD 1  of  FIG. 6  according to an embodiment of the inventive concept. 
     Referring to  FIGS. 6 and 10  together, first to fifth pads  101   a  to  105   a  of the first memory chip  100   a  may be respectively connected to sixth to tenth pads  101   b  to  105   b  of the second memory chip  100   b . For example, the first pads  101   a  and  101   b  may be commonly connected to the clock pin P 1  and may receive the read enable signal nRE from the controller  20 . For example, the second pads  102   a  and  102   b  may be commonly connected to the first pin P 2   a , the third pads  103   a  and  103   b  may be commonly connected to the second pin P 2   b , the fourth pads  104   a  and  104   b  may be commonly connected to the third pin P 2   c , and the fifth pads  105   a  and  105   b  may be commonly connected to the fourth pin P 2   d.    
     The first memory chip  100   a  may include the first repeater  110   a , the first DCA circuit  121   a , the first up/down counter  122   a , a first multiplexer  130   a , first to fourth input buffers  140   a ,  150   a ,  160   a , and  170   a , and first to fourth output drivers  145   a ,  155   a ,  165   a , and  175   a . Redundant descriptions of components already described with reference to  FIGS. 8 and 9  will be omitted. The first input buffer  140   a  and the first output driver  145   a  may be connected to the second pad  102   a , the second input buffer  150   a  and the second output driver  155   a  may be connected to the third pad  103   a , the third input buffer  160   a  and the third output driver  165   a  may be connected to the fourth pad  104   a , and the fourth input buffer  170   a  and the fourth output driver  175   a  may be connected to the fifth pad  105   a . Similarly to the first output driver  145   a , each of the second to fourth output drivers  155   a ,  165   a , and  175   a  may be connected to a corresponding multiplexer, and each of the second to fourth output drivers  155   a ,  165   a , and  175   a  may respectively output the output signals of the corresponding multiplexer to the third, fourth, and fifth pads  103   a ,  104   a , and  105   a.    
     For example, the first to fourth input buffers  140   a ,  150   a ,  160   a , and  170   a  and the first to fourth output drivers  145   a ,  155   a ,  165   a , and  175   a  included in the first memory chip  100   a  may be set in the chip enable period  521  and the first period  522   a  of the DCC training period  522  of the duty correction sequence  52  of  FIG. 5 . For example, the first, third, and fourth input buffers  140   a ,  160   a , and  170   a  and the second to fourth output drivers  155   a ,  165   a , and  175   a  may be disabled, and the second input buffer  150   a  and the first output driver  145   a  may be enabled. 
     The first repeater  110   a  may generate a first internal read enable signal nRE 1   i  based on the read enable signal nRE, and may provide the first internal read enable signal nRE 1   i  to the first DCA circuit  121   a . The first DCA circuit  121   a  may generate a first corrected read enable signal nRE 1   c  based on the first internal read enable signal nRE 1   i  and may provide the first corrected read enable signal nRR 1   c  to the first multiplexer  130   a  as a first selection signal. The first up/down counter  122   a  may generate the first control signal CS 1  based on the first comparison signal CP 1 , and provide the first control signal CS 1  to the first DCA circuit  121   a.    
     The first DCA circuit  121   a  may generate the first corrected read enable signal nRE 1   c  by performing a first duty correction operation on the first internal read enable signal nRE 1   i  based on the first control signal CS 1 , and may provide the generated first corrected read enable signal nRE 1   c  to the first multiplexer  130   a  as the first selection signal. The first multiplexer  130   a  may generate the first signal SIG 1  based on the first corrected read enable signal nRE 1   c , and may output the first signal SIG 1  to the second pad  102   a  of the first memory chip  100   a  through the output driver  145   a . In an embodiment, when the first duty correction operation on the first internal read enable signal nRE 1   i  is completed, the first memory chip  100   a  may output the first signal SIG 1  to the second pad  102   a  of the first memory chip  100   a.    
     The second memory chip  100   b  may include the second repeater  110   b , the second DCA circuit  121   b , the second up/down counter  122   b , a second multiplexer  130   b , fifth to eighth input buffers  140   b ,  150   b ,  160   b , and  170   b , and fifth to eighth output drivers  145   b ,  155   b ,  165   b , and  175   b . Redundant descriptions of components already described with reference to  FIGS. 8 and 9  will be omitted. The fifth input buffer  140   b  and the fifth output driver  145   b  may be connected to the second pad  102   b , the sixth input buffer  150   b  and the sixth output driver  155   b  may be connected to the third pad  103   b , the seventh input buffer  160   b  and the seventh output driver  165   b  may be connected to the fourth pad  104   b , and the eighth input buffer  170   b  and the eighth output driver  175   b  may be connected to the fifth pad  105   b . Similarly to the seventh output driver  165   b , each of the fifth, sixth, and eighth output drivers  145   b ,  155   b , and  175   b  may be connected to a corresponding multiplexer, and each of the fifth, sixth, and eighth output drivers  145   b ,  155   b , and  175   b  may respectively output the output signals of the corresponding multiplexer to the second, third, and fifth pads  102   b ,  103   b , and  105   b  of the second memory chip  100   b.    
     For example, the fifth to eighth input buffers  140   b ,  150   b ,  160   b , and  170   b  and the fifth to eighth output drivers  145   b ,  155   b ,  165   b , and  175   b  included in the second memory chip  100   b  may be set in the chip enable period  521  and the first period  522   a  of the DCC training period  522  of the duty correction sequence  52  of  FIG. 5 . For example, the fifth to seventh input buffers  140   b ,  150   b , and  160   b  and the fifth, sixth, and eighth output drivers  145   b ,  155   b , and  175   b  may be disabled, and the eighth input buffer  170   b  and the seventh output driver  165   b  may be enabled. 
     The second repeater  110   b  may generate a second internal read enable signal nRE 2   i  based on the read enable signal nRE, and may provide the second internal read enable signal nRE 2   i  to the second DCA circuit  121   b . The second DCA circuit  121   b  may generate a second corrected read enable signal nRE 2   c  based on the second internal read enable signal nRE 2   i  and may provide the second corrected read enable signal nRE 2   x  to the second multiplexer  130   b  as a second selection signal. The second up/down counter  122   b  may generate a second control signal CS 2  based on a second comparison signal CP 2 , and may provide the second control signal CS 2  to the second DCA circuit  121   b.    
     The second DCA circuit  121   b  may generate the second corrected read enable signal nRE 2   c  by performing a second duty correction operation on the second internal read enable signal nRE 2   i  based on the second control signal CS 2 , and may provide the generated second corrected read enable signal nRE 2   c  to the second multiplexer  130   b  as the second selection signal. The second multiplexer  130   b  may generate a second signal SIG 2  based on the second corrected read enable signal nRE 2   c , and may output the generated second signal SIG 2  to the fourth pad  104   b  of the second memory chip  100   b  through the seventh output driver  165   b . In an embodiment, when the second duty correction operation on the second internal read enable signal nRE 2   i  is completed, the second memory chip  100   b  may output the second signal SIG 2  to the fourth pad  104   b  of the second memory chip  100   b.    
       FIG. 11  is a flowchart of operations of the controller  20  and the first and second memory chips  100   a  and  100   b , according to an embodiment of the inventive concept. 
     Referring to  FIGS. 6 and 11  together, in operation S 110 , the controller  20  may issue a DCC command (DCC CMD) corresponding to an initiation of DCC training, and activate the clock signal CLK. For example, the DCC CMD may correspond to a set feature command or a DCC training command. For example, the clock signal CLK may include the read enable signal nRE. In operation S 120 , the controller  20  may transmit the DCC CMD and the clock signal CLK to the first and second memory chips  100   a  and  100   b . For example, the DCC CMD may be transmitted from the controller  20  to the first and second memory chips  100   a  and  100   b  through the first to fourth pins P 2   a ′ to P 2   d ′, and the controller  20  may transmit the clock signal CLK to the first and second memory chips  100   a  and  100   b  through the clock pin P 1 ′. 
     In operation S 130 , the first memory chip  100   a  may generate the first signal SIG 1  based on the clock signal CLK. In operation S 135 , the second memory chip  100   b  may generate the second signal SIG 2  based on the clock signal CLK. In an embodiment, operations S 130  and S 135  may be performed in parallel. In operation S 140 , the first memory chip  100   a  may transmit the first signal SIG 1  to the controller  20  through the first pins P 2   a  and P 2   a ′. For example, the first pins P 2   a  and P 2   a ′ may correspond to the input/output pins through which first data (i.e., the first signal SIG 1 ) may be transmitted and/or received. In operation S 145 , the second memory chip  100   b  may transmit the second signal SIG 2  to the controller  20  through the third pins P 2   c  and P 2   c ′. For example, the third pins P 2   c  and P 2   c ′ may correspond to the input/output pins through which second data (i.e., the second signal SIG 2 ) may be transmitted and/or received. In an embodiment, operations S 140  and S 145  may be performed in parallel. 
     In operation S 150 , the controller  20  may perform a duty sensing operation on the first signal SIG 1  and the second signal SIG 2 . In the duty sensing operation, the first duty sensing circuit  210  may generate the first comparison signal CP 1  based on the duty cycle of the first signal SIG 1 , and the second duty sensing circuit  220  may generate the second comparison signal CP 2  based on the duty cycle of the second signal SIG 2 . In operation S 160 , the controller  20  may transmit the first comparison signal CP 1  to the first memory chip  100   a  through the second pins P 2   b ′ and P 2   b . In operation S 165 , the controller  20  may transmit the second comparison signal CP 2  to the second memory chip  100   b  through the fourth pins P 2   d ′ and P 2   d . In an embodiment, operations S 160  and S 165  may be performed in parallel. 
     In operation S 170 , the first memory chip  100   a  may perform a duty correction operation on the clock signal CLK based on the first comparison signal CP 1 . In operation S 175 , the second memory chip  100   b  may perform a duty correction operation on the clock signal CLK based on the second comparison signal CP 2 . In an embodiment, operations S 170  and S 175  may be performed in parallel. In operation S 180 , the first memory chip  100   a  may generate a first corrected signal SIG 1 C based on the duty correction operation and may transmit the first corrected signal SIG 1 C to the controller  20  through the first pins P 2   a  and P 2   a ′. For example, the first pins P 2   a  and P 2   a ′ may correspond to the input/output pins through which first data (i.e., the first signal SIG 1 ) may be transmitted and/or received. In operation S 185 , the second memory chip  100   b  may generate a second corrected signal SIG 2 C based on the duty correction operation and may transmit the second corrected signal SIG 2 C to the controller  20  through the third pins P 2   c  and P 2   c ′. For example, the third pins P 2   c  and P 2   c ′ may correspond to the input/output pins through which second data (i.e., the second signal SIG 2 ) is transmitted and/or received. In an embodiment, operations S 180  and S 185  may be performed in parallel. 
       FIG. 12  is a schematic block diagram of the storage device SD 2  according to an embodiment of the inventive concept. 
     Referring to  FIG. 12 , the storage device SD 2  may include first and second memory devices  10   a  and  10   b  and a controller  20   a . The first memory device  10   a  may be connected to the controller  20   a  through a first channel CH 1 , and the second memory device  10   b  may be connected to the controller  20   a  through a second channel CH 2 . The first memory device  10   a  may include a first plurality of memory chips that include at least the first and second memory chips  100   a  and  100   b . Accordingly, the first plurality of memory chips that include the first and second memory chips  100   a  and  100   b  may communicate signals and data with the controller  20   a  through the first channel CH 1 . The second memory device  10   b  may include a second plurality of memory chips that include at least the third and fourth memory chips  100   a ′ and  100   b ′. Accordingly, the second plurality of memory chips that include the third and fourth memory chips  100   a ′ and  100   b ′ may communicate signals and data with the controller  20   a  through the second channel CH 2 . 
     The controller  20   a  may include a first plurality of duty sensing circuits  200  respectively corresponding to the first plurality of memory chips included in the first memory device  10   a , and a second plurality of duty sensing circuits  200 ′ respectively corresponding to the second plurality of memory chips included in the second memory device  10   b . The first plurality of duty sensing circuits  200  and the first plurality of memory chips included in the first memory device  10   a  may form a first plurality of DCC loops, and the second plurality of duty sensing circuits  200 ′ and the second plurality of memory chips included in the second memory device  10   b  may form a second plurality of DCC loops. 
     The descriptions of components and operations made with reference to  FIGS. 1 to 11  may also be applied to similar components and operations of  FIG. 12 , and redundant descriptions will be omitted. Accordingly, each duty sensing circuit of the first and second pluralities of duty sensing circuits  200  and  200 ′ may sense the duty cycle of a signal received from a corresponding memory chip, and may generate a comparison signal based on the sensed duty cycle. Each of the memory chips included in the first and second memory devices  10   a  and  10   b  may perform a duty correction operation on a clock signal based on a corresponding comparison signal, thereby generating a duty corrected signal, and may provide the duty corrected signal to the controller  20   a  through the first or second channels CH 1  or CH 2 , respectively. 
       FIG. 13  is a schematic block diagram of a storage device SD 3  according to an embodiment of the inventive concept. 
     Referring to  FIG. 13 , the storage device SD 3  may include the first and second memory devices  10   a  and  10   b , a buffer chip  30 , and a controller  20   b . In an embodiment, the storage device SD 3  may include the buffer chip  30 , as compared with the storage device SD 2  of  FIG. 12 . The buffer chip  30  may be connected between the controller  20   b  and the first and second memory devices  10   a  and  10   b , and may be referred to as a frequency boosting interface (FBI) circuit. In an embodiment, the first and second memory devices  10   a  and  10   b  and the buffer chip  30  may be implemented in a single package, and may be referred to as a memory device or a non-volatile memory device. 
     The first memory device  10   a  may be connected to the buffer chip  30  through the first channel CH 1 , the second memory device  10   b  may be connected to the buffer chip  30  through the second channel CH 2 , and the buffer chip  30  may be connected to the controller  20   b  through a third channel CH 3 . The first memory device  10   a  may include a first plurality of memory chips that include at least the first and second memory chips  100   a  and  100   b . Accordingly, the first plurality of memory chips that include the first and second memory chips  100   a  and  100   b  may communicate signals and data with the buffer chip  30  through the first channel CH 1 . The second memory device  10   b  may include a second plurality of memory chips that include the third and fourth memory chips  100   a ′ and  100   b ′. Accordingly, the second plurality of memory chips that include the third and fourth memory chips  100   a ′ and  100   b ′ may communicate signals and data with respect to the buffer chip  30  through the second channel CH 2 . 
     The buffer chip  30  may include the first plurality of duty sensing circuits  200  respectively corresponding to the first plurality of memory chips included in the first memory device  10   a  and the second plurality of duty sensing circuits  200 ′ respectively corresponding to the second plurality of memory chips included in the second memory device  10   b . The first plurality of duty sensing circuits  200  and the first plurality of memory chips included in the first memory device  10   a  may form a first plurality of DCC loops, and the second plurality of the duty sensing circuits  200 ′ and the second plurality of memory chips included in the second memory device  10   b  may form a second plurality of DCC loops. 
     The descriptions of components and operations made with reference to  FIGS. 1 to 11  may also be applied to similar components and operations of  FIG. 13 , and redundant descriptions will be omitted. Accordingly, each duty sensing circuit of the first and second plurality of duty sensing circuits  200  and  200 ′ may sense the duty cycle of a received signal in the corresponding memory chip, and may generate a comparison signal based on the sensed duty cycle. Each of the memory chips included in the first and second memory devices  10   a  and  10   b  may generate a duty corrected signal by performing a duty correction operation on a clock signal based on the corresponding comparison signal, and may provide a duty corrected signal to the buffer chip  30  through the first or second channels CH 1  or CH 2 , respectively. 
       FIG. 14  is a block diagram of a memory system  3000  according to an embodiment of the inventive concept. 
     Referring to  FIG. 14 , the memory system  3000  may include a memory device  3200  and a memory controller  3100 . The memory device  3200  may be implemented as a non-volatile memory (NVM) device. The memory device  3200  may communicate with the memory controller  3100  based on a channel of a plurality of channels. For example, the memory device  3200  may correspond to the memory device  10  in  FIG. 3 , and the memory controller  3100  may correspond to the controller  20  in  FIG. 3 . 
     The memory device  3200  may include first through eighth pins P 11  through P 18 , a memory interface circuit  3210 , a control logic circuit  3220 , and a memory cell array  3230 . The memory interface circuit  3210  may receive a chip enable signal nCE from the memory controller  3100  through the first pin P 11 . The memory interface circuit  3210  may exchange signals with the memory controller  3100  through the second through eighth pins P 12  through P 18  based on the chip enable signal nCE. For example, when the chip enable signal nCE is enabled (e.g., at a low level), the memory interface circuit  3210  may exchange signals with the memory controller  3100  through the second through eighth pins P 12  through P 18 . 
     The memory interface circuit  3210  may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller  3100  through the second through fourth pins P 12  through P 14 , respectively. The memory interface circuit  3210  may receive or transmit a data signal DQ from or to the memory controller  3100  through the seventh pin P 17 . The data signal DQ may include the command CMD, an address ADDR, and data DATA. For example, the data signal DQ may be transmitted through a plurality of data signal lines. In this case, the seventh pin P 17  may include a plurality of pins respectively corresponding to the data signal lines. 
     The memory interface circuit  3210  may receive the command CMD included in the data signal DQ in an enable period (e.g., a high-level state) of the command latch enable signal CLE based on toggle timings of the write enable signal nWE. The memory interface circuit  3210  may acquire the address ADDR included in the data signal DQ in an enable period (e.g., a high-level state) of the address latch enable signal ALE based on the toggle timings of the write enable signal nWE. 
     In an embodiment, the write enable signal nWE may remain in a static state (e.g., a high level or a low level) or may toggle between the high level and the low level. For example, the write enable signal nWE may toggle in a period in which the command CMD or the address ADDR is transmitted. Accordingly, the memory interface circuit  3210  may acquire the command CMD or the address ADDR based on toggle timings of the write enable signal nWE. 
     The memory interface circuit  3210  may receive a read enable signal nRE from the memory controller  3100  through the fifth pin P 15 . The memory interface circuit  3210  may receive or transmit a data strobe signal DQS from or to the memory controller  3100  through the sixth pin P 16 . 
     In a data output operation of the memory device  3200 , the memory interface circuit  3210  may receive the read enable signal nRE, which toggles, through the fifth pin P 15  before outputting the data DATA. The memory interface circuit  3210  may generate the data strobe signal DQS, which toggles, based on toggling of the read enable signal nRE. For example, the memory interface circuit  3210  may generate the data strobe signal DQS, which may begin toggling following a certain delay after a toggling start time of the read enable signal nRE. The memory interface circuit  3210  may transmit the data signal DQ that includes the data DATA based on toggle timings of the data strobe signal DQS. Accordingly, the data DATA may be transmitted to the memory controller  3100  in synchronization with the toggle timings of the data strobe signal DQS. 
     In a data input operation of the memory device  3200 , when the memory device  3200  receives the data signal DQ that includes the data DATA from the memory controller  3100 , the memory interface circuit  3210  may receive the data strobe signal DQS, which toggles, from the memory controller  3100  together with the data DATA. The memory interface circuit  3210  may acquire the data DATA from the data signal DQ based on the toggle timings of the data strobe signal DQS. For example, the memory interface circuit  3210  may acquire the data DATA by sampling the data signal DQ at rising and falling edges of the data strobe signal DQS. 
     The memory interface circuit  3210  may transmit a ready/busy output signal nR/B to the memory controller  3100  through the eighth pin P 18 . The memory interface circuit  3210  may transmit state information of the memory device  3200  to the memory controller  3100  through the ready/busy output signal nR/B. When the memory device  3200  is in a busy state (that is, when internal operations of the memory device  3200  are being performed), the memory interface circuit  3210  may transmit the ready/busy output signal nR/B indicating the busy state (e.g., the ready/busy output signal nR/B having a low level) to the memory controller  3100 . When the memory device  3200  is in a ready state (that is, when internal operations of the memory device  3200  are not performed or are completed), the memory interface circuit  3210  may transmit the ready/busy output signal nR/B indicating the ready state (e.g., the ready/busy output signal nR/B having a high level) to the memory controller  3100 . For example, while the memory device  3200  is reading the data DATA from the memory cell array  3230  in response to a read command, the memory interface circuit  3210  may transmit the ready/busy output signal nR/B indicating the busy state (e.g., by having a low level) to the memory controller  3100 . For example, while the memory device  3200  is programming the data DATA to the memory cell array  3230  in response to a program command, the memory interface circuit  3210  may transmit the ready/busy output signal nR/B indicating the busy state to the memory controller  3100 . 
     The control logic circuit  3220  may control various operations of the memory device  3200 . The control logic circuit  3220  may receive the command CMD and/or the address ADDR from the memory interface circuit  3210 . The control logic circuit  3220  may generate control signals for controlling other elements of the memory device  3200  based on the command CMD and/or the address ADDR. For example, the control logic circuit  3220  may generate various control signals for programming the data DATA to the memory cell array  3230  or reading the data DATA from the memory cell array  3230 . 
     The memory cell array  3230  may store data DATA received from the memory interface circuit  3210  in response to commands output by the control logic circuit  3220 . The memory cell array  3230  may output data DATA that has been stored in the memory cell array  3230  to the memory interface circuit  3210  in response to commands output by the control logic circuit  3220 . 
     The memory cell array  3230  may include a plurality of memory cells. For example, the plurality of memory cells may include flash memory cells. However, embodiments of the inventive concept are not necessarily limited thereto. For example, the memory cells may include RRAM cells, ferroelectric RAM (FRAM) cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, embodiments of the inventive concept will be described wherein the plurality of memory cells include NAND flash memory cells. 
     The memory controller  3100  may include ninth through sixteenth pins P 21  through P 28  and a controller interface circuit  3110 . The ninth through sixteenth pins P 21  through P 28  may respectively correspond to the first through eighth pins P 11  through P 18  of the memory device  3200 . The controller interface circuit  3110  may transmit the chip enable signal nCE to the memory device  3200  through the ninth pin P 21 . The controller interface circuit  3110  may exchange signals with the memory device  3200  through the tenth through sixteenth pins P 22  through P 28  based on the chip enable signal nCE. 
     The controller interface circuit  3110  may transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device  3200  through the tenth through eleventh pins P 22  through P 24 , respectively. The controller interface circuit  3110  may transmit or receive the data signal DQ to or from the memory device  3200  through the fifteenth pin P 27 . 
     The controller interface circuit  3110  may transmit the data signal DQ, which includes the command CMD or the address ADDR, to the memory device  3200  together with the write enable signal nWE, which toggles. The controller interface circuit  3110  may transmit the data signal DQ that includes the command CMD to the memory device  3200  by transmitting the command latch enable signal CLE, which is in the enable state, and may transmit the data signal DQ that includes the address ADDR to the memory device  3200  by transmitting the address latch enable signal ALE, which is in the enable state. 
     The controller interface circuit  3110  may transmit the read enable signal nRE to the memory device  3200  through the thirteenth pin P 25 . The controller interface circuit  3110  may receive or transmit the data strobe signal DQS from or to the memory device  3200  through the fourteenth pin P 26 . 
     In a data output operation of the memory device  3200 , the controller interface circuit  3110  may generate and transmit the read enable signal nRE, which toggles, to the memory device  3200 . For example, before the output of the data DATA, the controller interface circuit  3110  may generate the read enable signal nRE, which is converted from a static state (e.g., a high level or a low level) into a toggling state. Accordingly, the memory device  3200  may generate the data strobe signal DQS, which toggles, based on the read enable signal nRE. The controller interface circuit  3110  may receive the data signal DQ that includes the data DATA and the data strobe signal DQS, which toggles, from the memory device  3200 . The controller interface circuit  3110  may acquire the data DATA from the data signal DQ based on the toggle timings of the data strobe signal DQS. 
     In a data input operation of the memory device  3200 , the controller interface circuit  3110  may generate the data strobe signal DQS, which toggles. For example, before transmitting the data DATA, the controller interface circuit  3110  may generate the data strobe signal DQS, which may be converted from a static state (e.g., a high level or a low level) into a toggling state. The controller interface circuit  3110  may transmit the data signal DQ that includes the data DATA to the memory device  3200  based on the toggle timings of the data strobe signal DQS. 
     The controller interface circuit  3110  may receive the ready/busy output signal nR/B from the memory device  3200  through the sixteenth pin P 28 . The controller interface circuit  3110  may determine state information of the memory device  3200  based on the ready/busy output signal nR/B. 
       FIG. 15  is a cross-sectional view of a bonding VNAND (B-VNAND) structure that may be implemented in a memory device according to an embodiment of the inventive concept. In an embodiment, NVM included in a memory device may be implemented as B-VNAND type flash memory, and the NVM may have the structure illustrated in  FIG. 15 . 
     Referring to  FIG. 15 , a memory device  4000  may have a chip-to-chip (C2C) structure. In the C2C structure, an upper chip that includes a cell area CELL may be formed on a first wafer, a lower chip that includes a peripheral circuit area PERI may be formed on a second wafer that is different from the first wafer, and the upper chip may be connected to the lower chip by a bonding method. For example, the bonding method may include a method of electrically connecting a bonding metal formed in a topmost metal layer of the upper chip to a bonding metal formed in a topmost metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding method may include a Cu—Cu bonding method. The bonding metal may include aluminum or tungsten. 
     Each of the peripheral circuit area PERI and the cell area CELL of the memory device  4000  may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. 
     The peripheral circuit area PERI may include a first substrate  4110 , an interlayer insulating layer  4115 , a plurality of circuit devices  4120   a ,  4120   b , and  4120   c  formed in the first substrate  4110 , a first plurality of metal layers  4130   a ,  4130   b , and  4130   c  respectively connected to the plurality of circuit devices  4120   a ,  4120   b , and  4120   c , and a second plurality of metal layers  4140   a ,  4140   b , and  4140   c  respectively formed on the first plurality of metal layers  4130   a ,  4130   b , and  4130   c . In an embodiment, the first plurality of metal layers  4130   a ,  4130   b , and  4130   c  may include tungsten, as tungsten has a relatively higher resistance, and the second plurality of metal layers  4140   a ,  4140   b , and  4140   c  may include copper, as copper has a relatively lower resistance. 
     In this specification, only the first plurality of metal layers  4130   a ,  4130   b , and  4130   c  and the second plurality of metal layers  4140   a ,  4140   b , and  4140   c  are illustrated and described, but embodiments of the inventive concept are not necessarily limited thereto. For example, at least one metal layer may be further formed on the second plurality of metal layers  4140   a ,  4140   b , and  4140   c . At least a portion of the at least one metal layer formed on the second plurality of metal layers  4140   a ,  4140   b , and  4140   c  may include aluminum, which has a lower resistance than the copper included in the second plurality of metal layers  4140   a ,  4140   b , and  4140   c.    
     The interlayer insulating layer  4115  may be disposed on the first substrate  4110  and cover the plurality of circuit devices  4120   a ,  4120   b , and  4120   c , the first plurality of metal layers  4130   a ,  4130   b , and  4130   c , and the second plurality of metal layers  4140   a ,  4140   b , and  4140   c , and may include an insulating material such as silicon oxide or silicon nitride. 
     Lower bonding metals  4171   b  and  4172   b  may be formed on a fifth metal layer  4140   b  of the plurality of second metal layers  4140   a ,  4140   b , and  4140   c  in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals  4171   b  and  4172   b  of the peripheral circuit area PERI may be electrically connected to upper bonding metals  4271   b  and  4272   b  of the cell area CELL by a bonding method. The lower bonding metals  4171   b  and  4172   b  and the upper bonding metals  4271   b  and  4272   b  may include aluminum, copper, or tungsten. 
     The cell area CELL may include at least one memory block. The cell area CELL may include a second substrate  4210  and a common source line  4220 . A plurality of word lines  4231  through  4238  (collectively denoted by 4230) may be stacked on the second substrate  4210  in a first direction (e.g., a Z-axis direction) perpendicular to a top surface of the second substrate  4210 . A plurality of string selection lines may be arranged above the plurality of word lines  4230  and a ground selection line may be arranged below the plurality of word lines  4230 . The plurality of word lines  4230  may be interposed with the plurality of string selection lines and the ground selection line. 
     In the bit line bonding area BLBA, a channel structure CHS may extend in the first direction perpendicular to the top surface of the second substrate  4210  and pass through the plurality of word lines  4230 , the plurality of string selection lines, and the ground selection line. The channel structure CHS may include a data storage layer, a channel layer, and a buried insulating layer. The channel layer may be electrically connected to a first metal layer  4250   c  and a second metal layer  4260   c . For example, the first metal layer  4250   c  may correspond to a bit line contact, and the second metal layer  4260   c  may correspond to a bit line and may be referred to hereinafter as a bit line  4260   c . In an embodiment, the bit line  4260   c  may extend in a second direction (e.g., a Y-axis direction) parallel with the top surface of the second substrate  4210  and perpendicular to the first direction. 
     In an embodiment shown by  FIG. 15 , an area in which the channel structure CHS and the bit line  4260   c  are arranged may be defined as the bit line bonding area BLBA. The bit line  4260   c  may be electrically connected to a second plurality of circuit devices  4120   c  of the plurality of circuit devices  4120   a ,  4120   b , and  4120   c  to constitute a page buffer  4293  in the peripheral circuit area PERI and in the bit line bonding area BLBA. For example, the bit line  4260   c  may be connected to upper bonding metals  4271   c  and  4272   c  in the bit line bonding area BLBA, and the upper bonding metals  4271   c  and  4272   c  may be connected to lower bonding metals  4171   c  and  4172   c  connected to the second plurality of circuit devices  4120   c  of the page buffer  4293 . 
     In the word line bonding area WLBA, the plurality of word lines  4230  may extend in a third direction (e.g., an X-axis direction) parallel with the top surface of the second substrate  4210  and perpendicular to the first and second directions and may be connected to a plurality of cell contact plugs  4241  through  4247  (collectively denoted by 4240). The plurality of word lines  4230  may be connected to the plurality of cell contact plugs  4240  through a plurality of pads included in at least some word lines of the plurality of word lines  4230  extending in different lengths in the second direction. A first metal layer  4250   b  and a second metal layer  4260   b  may be sequentially stacked on each cell contact plug of the plurality of cell contact plugs  4240  connected to the plurality of word lines  4230 . The plurality of cell contact plugs  4240  in the word line bonding area WLBA may be connected to the peripheral circuit area PERI through the upper bonding metals  4271   b  and  4272   b  of the cell area CELL and the lower bonding metals  4171   b  and  4172   b  of the peripheral circuit area PERI. 
     The plurality of cell contact plugs  4240  may be electrically connected to a third plurality of circuit devices  4120   b  of the plurality of circuit devices  4120   a ,  4120   b , and  4120   c  to constitute a row decoder  4294  in the peripheral circuit area PERI. In an embodiment, operating voltages of the third plurality of circuit devices  4120   b  in the row decoder  4294  may be different from operating voltages of the second plurality of circuit devices  4120   c  in the page buffer  4293 . For example, the operating voltages of the second plurality of circuit devices  4120   c  in the page buffer  4293  may be greater than the operating voltages of the third plurality of circuit devices  4120   b  in the row decoder  4294 . 
     A common source line contact plug  4280  may be arranged in the external pad bonding area PA. The common source line contact plug  4280  may include a conductive material such as metal, a metal compound, or polysilicon, and may be electrically connected to the common source line  4220 . A first metal layer  4250   a  and a second metal layer  4260   a  may be sequentially stacked on the common source line contact plug  4280 . For example, an area in which the common source line contact plug  4280 , the first metal layer  4250   a , and the second metal layer  4260   a  are arranged may be referred to as the external pad bonding area PA. 
     First and second input/output pads  4105  and  4205  may be arranged in the external pad bonding area PA. Referring to  FIG. 15 , a lower insulating film  4101  covering a bottom surface of the first substrate  4110  may be formed below the first substrate  4110 , and the first input/output pad  4105  may be formed on the lower insulating film  4101 . The first input/output pad  4105  may be connected to at least one of the plurality of circuit devices  4120   a ,  4120   b , and  4120   c  of the peripheral circuit area PERI through a first input/output contact plug  4103 , and may be isolated from the first substrate  4110  by the lower insulating film  4101 . A side insulating film may be disposed between the first input/output contact plug  4103  and the first substrate  4110  and may electrically isolate the first input/output contact plug  4103  from the first substrate  4110 . 
     Referring to  FIG. 15 , an upper insulating film  4201  covering a top surface of the second substrate  4210  may be formed above the second substrate  4210 , and the second input/output pad  4205  may be arranged on the upper insulating film  4201 . The second input/output pad  4205  may be connected to at least one of the plurality of circuit devices  4120   a ,  4120   b , and  4120   c  of the peripheral circuit area PERI through a second input/output contact plug  4203 . For example, the second input-output contact plug  4203  may be connected to a circuit element  4120   a  of the plurality of circuit devices  4120   a ,  4120   b , and  4120   c  through lower bonding metals  4171   a  and  4172   a.    
     According to an embodiment, the second substrate  4210  and the common source line  4220  may be omitted from an area in which the second input/output contact plug  4203  is arranged. The second input/output pad  4205  might not overlap the word lines  4230  in the first direction (e.g., the Z-axis direction). Referring to  FIG. 15 , the second input/output contact plug  4203  may be separated from the second substrate  4210  in a direction parallel with the top surface of the second substrate  4210  and may pass through an interlayer insulating layer  4215  of the cell area CELL to connect to the second input/output pad  4205 . 
     According to an embodiment, the first input/output pad  4105  and the second input/output pad  4205  may be selectively formed. For example, the memory device  400  may include only the first input/output pad  4105  on the first substrate  4110  or only the second input/output pad  4205  on the second substrate  4210 . Alternatively, the memory device  4000  may include both the first input/output pad  4105  and the second input/output pad  4205 . 
     A metal pattern of a topmost metal layer may be provided as a dummy pattern in the external pad bonding area PA of each of the cell area CELL and the peripheral circuit area PERI, or the topmost metal layer may omit the metal pattern. 
     Corresponding to an upper metal pattern  4272   a  in the topmost metal layer of the cell area CELL, a lower metal pattern  4173   a  having the same shape as upper metal pattern  4272   a  of the cell area CELL may be formed in a topmost metal layer of the peripheral circuit area PERI in the external pad bonding area PA. The lower metal pattern  4173   a  in the topmost metal layer of the peripheral circuit area PERI may not be connected to a contact in the peripheral circuit area PERI. Similarly, in correspondence to a lower metal pattern in the topmost metal layer of the peripheral circuit area PERI in the external pad bonding area PA, an upper metal pattern having the same shape as lower metal pattern of the peripheral circuit area PERI may be formed in the topmost metal layer of the cell area CELL. 
     The lower bonding metals  4171   b  and  4172   b  may be formed on the second metal layer  4140   b  in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals  4171   b  and  4172   b  of the peripheral circuit area PERI may be electrically connected to the upper bonding metals  4271   b  and  4272   b  of the cell area CELL by a bonding method. 
     Corresponding to a lower metal pattern  4152  formed in the topmost metal layer of the peripheral circuit area PERI, an upper metal pattern  4292  having the same shape as the lower metal pattern  4152  of the peripheral circuit area PERI may be formed in the bit line bonding area BLBA on the topmost metal layer of the cell area CELL. A contact may be omitted on the upper metal pattern  4292  in the topmost metal layer of the cell area CELL. For example, the lower metal pattern  4152  may be connected to the circuit element  4120   c  through a lower bonding metal  4151 . 
     A memory device, a memory controller, and a storage device according to some embodiments described with reference to  FIGS. 1 to 15  may implement or follow a toggle protocol that may succeed Toggle DDR 4.0. 
     While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.