Patent Publication Number: US-2023162925-A1

Title: Multi-layer ceramic electronic component, multi-layer ceramic electronic component mounting substrate, and multi-layer ceramic electronic component package

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. Application No. 16/225,585, filed Dec. 19, 2018; which claims the benefit under 35 U.S.C. §119 of Japanese Application No. 2017-246104, filed Dec. 22, 2017, which is hereby incorporated in its entirety. 
    
    
     BACKGROUND 
     The present disclosure relates to a multi-layer ceramic electronic component such as a multi-layer ceramic capacitor, and a multi-layer ceramic electronic component mounting substrate and a multi-layer ceramic electronic component package that mount the multi-layer ceramic electronic component. 
     In the past, a multi-layer ceramic electronic component such as a multi-layer ceramic capacitor, in which a ceramic body includes a plurality of laminated internal electrodes, has been known. The multi-layer ceramic electronic component is mounted onto a circuit board of a personal digital assistant or another electronic device and widely used. 
     Japanese Patent Application Laid-open No. 2014-99589 (paragraph [0031], Fig. 6, etc.) discloses a method of mounting a multi-layer ceramic capacitor housed in a package onto a circuit board. Specifically, a cover tape is peeled off from a package including a plurality of accommodating sections in which the multi-layer ceramic capacitors are arranged such that internal electrodes thereof are oriented in a certain direction, and the multi-layer ceramic capacitors are subjected to suction and held one by one by a suction nozzle and then mounted at predetermined positions on the surface of the circuit board. 
     SUMMARY 
     In recent years, electronic devices such as personal digital assistants have increasingly achieved downsizing, and a mounting area for ceramic electronic components on a circuit board is limited. Meanwhile, there is a demand for improvement in electrical characteristics of multi-layer ceramic electronic components, such as increase in capacitance of multi-layer ceramic capacitors. 
     In view of the circumstances as described above, it is desirable to provide a multi-layer ceramic electronic component, a multi-layer ceramic electronic component mounting substrate, and a multi-layer ceramic electronic component package, which are capable of improving electrical characteristics without increasing a mounting area on a circuit board. 
     According to an embodiment of the present disclosure, there is provided a multi-layer ceramic electronic component including a ceramic body and a pair of external electrodes. 
     The ceramic body includes internal electrodes laminated in a first direction, and a pair of main surfaces including a center region facing in the first direction. 
     The pair of external electrodes are connected to the internal electrodes and face each other in a second direction orthogonal to the first direction. 
     A dimension of the ceramic body in the first direction is 1.1 times or more and 1.6 times or less a dimension of the ceramic body in a third direction orthogonal to the first direction and the second direction. 
     The center region is formed at a center portion of at least one of the pair of main surfaces in the second direction. 
     With this configuration, it is possible to increase the height of the ceramic body while maintaining the area of the main surface and to increase the number of lamination of the internal electrodes. Therefore, it is possible to achieve a multi-layer ceramic electronic component capable of improving electrical characteristics without increasing a mounting area on a circuit board. 
     Additionally, the ceramic body includes the center region formed at the center portion of at least one of the pair of main surfaces in the second direction. Accordingly, a suction nozzle for transferring the multi-layer ceramic electronic component at the time of mounting can come into close contact with the center region and can stably hold the center region. Therefore, it is possible to inhibit occurrence of a failure at the time of mounting in the multi-layer ceramic electronic component. 
     A dimension of the center region in the third direction may be 80% or more and less than 100% of the dimension of the ceramic body in the third direction. 
     The center region may include a flat region. 
     Accordingly, it is possible to further improve the stability of suction at the time of mounting in the multi-layer ceramic electronic component and to inhibit occurrence of a failure more reliably. 
     According to another embodiment of the present disclosure, there is provided a multi-layer ceramic electronic component mounting substrate including a circuit board and a multi-layer ceramic electronic component. 
     The multi-layer ceramic electronic component includes a ceramic body and a pair of external electrodes and is mounted onto the circuit board via the pair of external electrodes. 
     The ceramic body includes internal electrodes laminated in a first direction and a pair of main surfaces including a center region facing in the first direction. 
     The pair of external electrodes are connected to the internal electrodes and face each other in a second direction orthogonal to the first direction. 
     A dimension of the ceramic body in the first direction is 1.1 times or more and 1.6 times or less a dimension of the ceramic body in a third direction orthogonal to the first direction and the second direction. 
     The center region is formed at a center portion of at least one of the pair of main surfaces in the second direction. 
     The multi-layer ceramic electronic component is mounted onto the circuit board with the center region being faced outward in the first direction. 
     The multi-layer ceramic electronic component is placed onto the circuit board with the center region being held by suction by the suction nozzle in the first direction. Accordingly, in the multi-layer ceramic electronic component mounting substrate, the multi-layer ceramic electronic component is mounted onto the circuit board with the center region being faced outward in the first direction. 
     According to still another embodiment of the present disclosure, there is provided a multi-layer ceramic electronic component package including a multi-layer ceramic electronic component, a housing portion, and a sealing portion. 
     The multi-layer ceramic electronic component includes a ceramic body and a pair of external electrodes and is mounted onto a circuit board via the pair of external electrodes. 
     The ceramic body includes internal electrodes laminated in a first direction and a pair of main surfaces including a center region facing in the first direction. 
     The pair of external electrodes are connected to the internal electrodes and face each other in a second direction orthogonal to the first direction. 
     A dimension of the ceramic body in the first direction is 1.1 times or more and 1.6 times or less a dimension of the ceramic body in a third direction orthogonal to the first direction and the second direction. 
     The center region is formed at a center portion of at least one of the pair of main surfaces in the second direction. 
     The housing portion includes a recess that houses the multi-layer ceramic electronic component and includes a take-out opening. 
     The sealing portion covers the take-out opening of the recess. 
     The multi-layer ceramic electronic component is housed in the recess with the center region being faced to the take-out opening. 
     With this configuration, when the sealing portion is peeled off, the center region is to be exposed from the take-out opening. Therefore, it is possible to cause the suction nozzle to come into close contact with the center region without changing the posture of the multi-layer ceramic electronic component, and smoothly mount the multi-layer ceramic electronic component. 
     According to yet still another embodiment of the present disclosure, there is provided a method of producing a multi-layer ceramic electronic component, the method including: forming an internal electrode pattern having a predetermined thickness on an unsintered ceramic sheet; forming a dielectric pattern in an electrode non-formation region around the internal electrode pattern on the ceramic sheet such that the dielectric pattern occupies 75% or more and less than 100% of a space portion facing to the electrode non-formation region and having the predetermined thickness; laminating in a first direction the ceramic sheets on each of which the internal electrode pattern and the dielectric pattern are formed, and forming a ceramic body including a plurality of internal electrodes laminated in the first direction, a dimension of the ceramic body in the first direction being 1.1 times or more and 1.6 times or less a dimension of the ceramic body in a second direction orthogonal to the first direction; and forming a pair of external electrodes connected to the plurality of internal electrodes and facing each other in a third direction orthogonal to the first direction and the second direction. 
     Accordingly, not only the internal electrode pattern but also the dielectric pattern are formed on each ceramic sheet. When the dielectric pattern is formed to occupy 75% or more of the space portion, the laminated ceramic sheets can be inhibited from sinking down into gaps between the internal electrode patterns and the dielectric patterns. Accordingly, also in a ceramic body including a lot of laminated ceramic sheets, variations in height dimension for each region can be suppressed, and the center region can be formed on at least one of the main surfaces. Further, when the dielectric pattern is less than 100% of the space portion, it is possible to inhibit the dielectric pattern from overlapping with the internal electrode pattern if the dielectric pattern is slightly displaced from the internal electrode pattern. This can also suppress variations in height dimension in the ceramic body and form the center region. 
     As described above, according to the present disclosure, it is possbile to provide a multi-layer ceramic electronic component, a multi-layer ceramic electronic component mounting substrate, and a multi-layer ceramic electronic component package, which are capable of improving electrical characteristics without increasing a mounting area on a circuit board. 
     These and other objects, features and advantages of the present disclosure will become more apparent in light of the following detailed description of embodiments thereof, as illustrated in the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a perspective view of a multi-layer ceramic capacitor according to an embodiment of the present disclosure; 
         FIG.  2    is a cross-sectional view of the multi-layer ceramic capacitor taken along the A-A′ line in  FIG.  1   ; 
         FIG.  3    is a cross-sectional view of the multi-layer ceramic capacitor taken along the B-B′ line in  FIG.  1   ; 
         FIG.  4    is a diagram showing a microstructure of a cross section of the multi-layer ceramic capacitor; 
         FIG.  5    is a partially enlarged view of  FIG.  3   ; 
         FIG.  6    is a flowchart showing a method of producing the multi-layer ceramic capacitor; 
         FIGS.  7 A and  7 B  are each a plan view showing a production process of the multi-layer ceramic capacitor; 
         FIG.  8    is a partial cross-sectional view of the multi-layer ceramic capacitor taken along the C-C′ line of  FIG.  7 A ; 
         FIG.  9    is a partial cross-sectional view similar to  FIG.  8    and a view for describing Step S 02  of  FIG.  6   ; 
         FIG.  10    is a perspective view showing a production process of the multi-layer ceramic capacitor; 
         FIG.  11    is a perspective view showing a production process of the multi-layer ceramic capacitor; 
         FIG.  12    is a plan view of a multi-layer ceramic capacitor package according to the embodiment of the present disclosure; 
         FIG.  13    is a cross-sectional view of the package taken along the D-D′ line in  FIG.  12   ; 
         FIG.  14    is a cross-sectional view schematically showing a step of mounting the multi-layer ceramic capacitor; and 
         FIG.  15    is a cross-sectional view of a multi-layer ceramic capacitor mounting substrate according to the embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. 
     In the figures, an X axis, a Y axis, and a Z axis orthogonal to one another are shown as appropriate. The X axis, the Y axis, and the Z axis are common in all figures. 
     1. Basic Configuration of Multi-Layer Ceramic Capacitor  10   
       FIGS.  1  to  3    each show a multi-layer ceramic capacitor  10  according to an embodiment of the present disclosure.  FIG.  1    is a perspective view of the multi-layer ceramic capacitor  10 .  FIG.  2    is a cross-sectional view of the multi-layer ceramic capacitor  10  taken along the A-A′ line in  FIG.  1   .  FIG.  3    is a cross-sectional view of the multi-layer ceramic capacitor  10  taken along the B-B′ line in  FIG.  1   . 
     The multi-layer ceramic capacitor  10  includes a ceramic body  11 , a first external electrode  14 , and a second external electrode  15 . 
     Typically, the ceramic body  11  has two end surfaces  11   a  and  11   b  facing in an X-axis direction, two side surfaces  11   c  and  11   d  facing in a Y-axis direction, and two main surfaces  11   e  and  11   f  facing in a Z-axis direction. Ridges connecting the respective surfaces of the ceramic body  11  are chamfered. 
     It should be noted that the shape of the ceramic body  11  is not limited to the above shape. In other words, the ceramic body  11  does not need to have the rectangular shape as shown in  FIGS.  1  to  3   . 
     The first external electrode  14  and the second external electrode  15  are configured to face each other in the X-axis direction and to respectively cover both the end surfaces  11   a  and  11   b  of the ceramic body  11 . The first external electrode  14  and the second external electrode  15  extend to the four surfaces connected to both the end surfaces  11   a  and  11   b , i.e., the two main surfaces  11   e  and  11   f  and the two side surfaces  11   c  and  11   d . With this configuration, both of the first external electrode  14  and the second external electrode  15  have U-shaped cross sections parallel to the X-Z plane and the X-Y plane. 
     The ceramic body  11  includes a multi-layer unit  16  and covers  17 . The multi-layer unit  16  has a configuration in which first internal electrodes  12  and second internal electrodes  13  are alternately laminated in the Z-axis direction via ceramic layers  18 . The covers  17  cover an upper surface and a lower surface of the multi-layer unit  16  in the Z-axis direction. 
     The first internal electrodes  12  and the second internal electrodes  13  are alternately laminated in the Z-axis direction via the ceramic layers  18 . The first internal electrodes  12  are drawn to the end surface  11   a  to be connected to the first external electrode  14  and are apart from the second external electrode  15 . The second internal electrodes  13  are drawn to the end surface  11   b  to be connected to the second external electrode  15  and are apart from the first external electrode  14 . 
     Further, the first and second internal electrodes  12  and  13  are not drawn to the side surfaces  11   c  and  11   d . Accordingly, side margins made of dielectric ceramics are formed on the sides of the side surfaces  11   c  and  11   d  of the multi-layer unit  16 . 
     Typically, the first and second internal electrodes  12  and  13  mainly contain nickel (Ni) and function as internal electrodes of the multi-layer ceramic capacitor  10 . It should be noted that the first and second internal electrodes  12  and  13  may contain at least one of copper (Cu), silver (Ag), or palladium (Pd) as a main component, other than nickel. 
     Each of the ceramic layers  18  is disposed between the first internal electrode  12  and the second internal electrode  13  and is made of dielectric ceramics. In order to increase the capacitance of the multi-layer unit  16 , the ceramic layer  18  is made of dielectric ceramics having a high dielectric constant. 
     For the dielectric ceramics having a high dielectric constant, polycrystal of a barium titanate (BaTiO 3 ) based material, i.e., polycrystal having a Perovskite structure containing barium (Ba) and titanium (Ti) is used. This provides the multi-layer ceramic capacitor  10  with a large capacitance. 
     It should be noted that the ceramic layer  18  may be made of a strontium titanate (SrTiO 3 ) based material, a calcium titanate (CaTiO 3 ) based material, a magnesium titanate (MgTiO 3 ) based material, a calcium zirconate (CaZrO 3 ) based material, a calcium zirconate titanate (Ca(Zr,Ti)O 3 ) based material, a barium zirconate (BaZrO 3 ) based material, a titanium oxide (TiO 2 ) based material, or the like. 
     The covers  17  are also made of dielectric ceramics. The material of the covers  17  only needs to be insulating ceramics, but use of the dielectric ceramics similar to the dielectric ceramics of the ceramic layers  18  leads to suppression of internal stress in the ceramic body  11 . 
     With such a condiguration, when a voltage is applied between the first external electrode  14  and the second external electrode  15  in the multi-layer ceramic capacitor  10 , the voltage is applied to the plurality of ceramic layers  18  between the first internal electrodes  12  and the second internal electrodes  13 . Thus, the multi-layer ceramic capacitor  10  stores charge corresponding to the voltage applied between the first external electrode  14  and the second external electrode  15 . 
     It should be noted that the basic configuration of the multi-layer ceramic capacitor  10  according to this embodiment is not limited to the configuration shown in  FIGS.  1  to  3    and can be changed as appropriate. 
     2. Detailed Configuration of Ceramic Body 
     As shown in  FIG.  3   , the ceramic body  11  is characterized in that a height dimension T in the Z-axis direction is 1.1 times or more and 1.6 times or less a width dimension W in the Y-axis direction. This can increase the number of lamination of the first and second internal electrodes  12  and  13  and increase the capacitance of the multi-layer ceramic capacitor  10  without increasing a cross-sectional area of the ceramic body  11  in the X-Y plane. 
     Here, the height dimension T of the ceramic body  11  means a dimension along the Z-axis direction at the center portion of the ceramic body  11  in the Y-axis direction, on a Y-Z cross-section (see  FIG.  3   ) that is cut at the center portion of the multi-layer ceramic capacitor  10  in the X-axis direction. In this embodiment, the height dimension T can be defined by a relationship between the width dimension W and a length dimension L to be described later. 
     The width dimension W of the ceramic body  11  means a dimension along the Y-axis direction at the center portion of the ceramic body  11  in the Z-axis direction, on the Y-Z cross-section (see  FIG.  3   ) that is cut at the center portion of the multi-layer ceramic capacitor  10  in the X-axis direction. The width dimension W is not particularly limited and can be set to, for example, 0.10 mm or more and 1.50 mm or less. 
     The length dimension L of the ceramic body  11  may be larger than 1.0 times and equal to or smaller than 1.5 times the height dimension T. This can increase the height dimension T and increase the capacitance without increasing the mounting area for the multi-layer ceramic capacitor  10  and allows handling at the time of manufacturing or mounting to be described later to be smoothly performed. 
     The length dimension L of the ceramic body  11  means a dimension along the X-axis direction at the center portion of the ceramic body  11  in the Z-axis direction, on the Z-X cross-section (see  FIG.  2   ) that is cut at the center portion of the multi-layer ceramic capacitor  10  in the Y-axis direction. The length dimension L is not particularly limited and can be set to, for example, 0.20 mm or more and 2.00 mm or less. 
     In order to further increase the number of layers of the first and second internal electrodes  12  and  13  and increase the capacitance of the multi-layer ceramic capacitor  10 , the thickness of the cover  17  may be reduced. As an example, the dimension (thickness) of the cover  17  in the Z-axis direction may be 15 µm or less. 
     In order to further increase the capacitance of the multi-layer ceramic capacitor  10 , the thickness of each ceramic layer  18  between the first and second internal electrodes  12  and  13  may be reduced. For example, a mean dimension (mean thickness) of the ceramic layers  18  in the Z-axis direction may be set to, for example, 1.0 µm or less or further 0.5 µm or less. 
     It should be noted that the mean thickness of the ceramic layers  18  can be calculated as a mean value of the thicknesses measured at a plurality of sites of the ceramic layers  18 . A position at which the thickness of the ceramic layer  18  is to be measured or the number of positions may be optionally determined. Hereinafter, an example of a method of measuring a mean thickness T of the ceramic layers  18  will be described with reference to  FIG.  4   . 
       FIG.  4    is a diagram showing a microstructure of a cross section of the ceramic body  11 , which is observed in the visual field of 12.6 µm x 8.35 µm with a scanning electron microscope. For each of the six ceramic layers  18  within the visual field, the thickness is measured at five sites indicated by the arrows arranged at equal intervals of 2 µm. A mean value of the thicknesses obtained at the  30  sites can be set as a mean thickness. 
     In such a manner, in the multi-layer ceramic capacitor  10  of this embodiment, the height dimension T can be increased and a large number of first and second internal electrodes  12  and  13  can be laminated without increasing the mounting area, so that a large capacitance can be achieved. 
     Meanwhile, in the past, the multi-layer ceramic capacitor  10  has been difficult to handle at the time of mounting, and it has been difficult to achieve a multi-layer ceramic capacitor in which the height dimension T is larger than the width dimension W. 
     In this regard, in the multi-layer ceramic capacitor  10  of this embodiment, at least one of the main surface  11   e  or  11   f  has a center region F facing in the Z-axis direction. With this configuration, as will be described later, handleability at the time of mounting can be improved even if the height dimension T is larger than the width dimension W. 
     The center region F is a flat region that is formed at the center portion in the Y-axis direction of at least one of the main surface  11   e  or  11   f  and formed as a flat surface substantially parallel to the X-Y plane. In this embodiment, the center region F is formed on each of the main surfaces  11   e  and  11   f , but it may be formed on either one of the main surfaces  11   e  and  11   f . Peripheral portions of each of the main surfaces  11   e  and  11   f  in the Y-axis direction are positioned outward in the Y-axis direction of the center portion and have curved surfaces extending from the center region F. 
       FIG.  5    is a partially enlarged view of  FIG.  3   . The center region F will be described in detail with reference to  FIG.  5   . 
     It is assumed that a first imaginary line L1 and a second imaginary line L2 are defined on the Y-Z cross-section of the ceramic body  11 , the first imaginary line L1 passes through a center point C of the main surface  11   e   11   f ) in the Y-axis direction and orthogonally intersects with the Z-axis direction (the first imaginary line L1 is parallel to the Y-axis direction), and the second imaginary line L2 is parallel to the first imaginary line L1 and has an interval of 1% of the height dimension T of the ceramic body  11  (T*0.01) from the first imaginary line L1. In this case, the center region F means a region between two points at which the second imaginary line L2 and the main surface  11   e   11   f ) intersect with each other. “The center point C of the main surface  11   e   11   f ) in the Y-axis direction” described herein means the center of the width dimension of each of the main surfaces  11   e  and  11   f  along the Y-axis direction.  FIG.  5    shows the center point of the main surface  11   e  in the Y-axis direction by an arrow and shows the first imaginary line L1 and the second imaginary line L2 by thick chain lines. 
     When the center region F is defined as described above, a width dimension Wf of the center region F along the Y-axis direction corresponds to a distance along the Y-axis direction between the two points at which the second imaginary line L2 and the main surface  11   e   11   f ) intersect with each other. The width dimension Wf of the center region F can be set to be 80% or more and less than 100% of the widthdimension W of the ceramic body  11 . Accordingly, the width dimension Wf of the flat center region F can be sufficiently ensured and handleability at the time of mounting can be further improved. 
     The multi-layer ceramic capacitor  10  including the center region F can be produced by the following production method. 
     3. Method of Producing Multi-Layer Ceramic Capacitor  10   
       FIG.  6    is a flowchart showing a method of producing the multi-layer ceramic capacitor  10 .  FIGS.  7 A to  11    are views each showing a production process of the multi-layer ceramic capacitor  10 . Hereinafter, the method of producing the multi-layer ceramic capacitor  10  will be described along  FIG.  6    with reference to  FIGS.  7 A to  11    as appropriate. 
     3.1 Step S 01 : Formation of Internal Electrode Pattern 
     In Step S 01 , first internal electrode patterns  112  and second internal electrode patterns  113  are respectively formed on first ceramic sheets  101  and second ceramic sheets  102  for forming the multi-layer unit  16 . 
     The first and second ceramic sheets  101  and  102  are configured as unsintered dielectric green sheets mainly containing dielectric ceramics. For the dielectric ceramics, powder having a particle diameter of, for example, 20 nm to 200 nm can be used. The first and second ceramic sheets  101  and  102  are each formed into a sheet shape by using a roll coater or a doctor blade, for example. The thickness of each of the first and second ceramic sheets  101  and  102  is not limited, but it is adjusted to have 1.5 µm or less, for example. 
       FIGS.  7 A and  7 B  are plan views of the first ceramic sheet  101  and the second ceramic sheet  102 , respectively. At this stage, the first and second ceramic sheets  101  and  102  are each formed into a large-sized sheet that is not singulated.  FIGS.  7 A and  7 B  each show cutting lines Lx and Ly used when the sheets are singulated into the multi-layer ceramic capacitors  10 . The cutting lines Lx are parallel to the X axis, and the cutting lines Ly are parallel to the Y axis. 
     As shown in  FIGS.  7 A and  7 B , the unsintered first internal electrode patterns  112  corresponding to the first internal electrodes  12  are formed on the first ceramic sheet  101 , and the unsintered second internal electrode patterns  113  corresponding to the second internal electrodes  13  are formed on the second ceramic sheet  102 . 
     The first internal electrode patterns  112  and the second internal electrode patterns  113  can be formed by applying an optional electrical conductive paste to the first ceramic sheets  101  and the second ceramic sheets  102 , respectively. A method of applying the electrical conductive paste can be optionally selected from well-known techniques. For example, for the application of the electrical conductive paste, a screen printing method or a gravure printing method can be used. 
     Each of the first internal electrode patterns  112  on the first ceramic sheets  101  is formed in a substantially rectangular shape that crosses one cutting line Ly1or Ly2 and extends in the X-axis direction. The first internal electrode patterns  112  are cut on the cutting lines Ly1, Ly2, and Lx, thus forming the first internal electrodes  12  of the multi-layer ceramic capacitors  10 . The first internal electrode pattern  112  on the cutting line Ly1 or Ly2 corresponds to a drawn portion to be exposed at the end surface  11   a . 
     In the first ceramic sheet  101 , a first column including the first internal electrode patterns  112  that extend across the cutting lines Ly1and are disposed along the X-axis direction, and a second column including the first internal electrode patterns  112  that extend across the cutting lines Ly2 and are disposed along the X-axis direction are arranged alternately in the Y-axis direction. In the first column, the first internal electrode patterns  112  adjacent to each other in the X-axis direction face each other while sandwiching the cutting line Ly2 therebetween. In the second column, the first internal electrode patterns  112  adjacent to each other in the X-axis direction face each other while sandwiching the cutting line Ly1therebetween. In other words, the first internal electrode patterns  112  are displaced by one chip in the X-axis direction between the first column and the second column adjacent to each other in the Y-axis direction. 
     The second internal electrode patterns  113  on the second ceramic sheets  102  are configured to be similar to the first internal electrode patterns  112 . However, in the second ceramic sheet  102 , the second internal electrode patterns  113  in a column corresponding to the first column of the first ceramic sheet  101  extend across the cutting lines Ly2, and the second internal electrode patterns  113  in a column corresponding to the second column of the first ceramic sheet  101  extend across the cutting lines Ly1. In other words, the second internal electrode patterns  113  are displaced from the first internal electrode patterns  112  by one chip in the X-axis direction or the Y-axis direction. 
     An electrode non-formation region N is a region in which the first and second internal electrode patterns  112  and  113  are not formed on each of the first and second ceramic sheets  101  and  102 . In the first ceramic sheet  101 , the electrode non-formation region N includes a plurality of belt-like regions extending along the cutting lines Ly1 and Ly2 between the first internal electrode patterns  112  adjacent to each other in the X-axis direction, and a plurality of belt-like regions extending along the cutting lines Lx between the first internal electrode patterns  112  adjacent to each other in the Y-axis direction. The electrode non-formation region N is formed in a lattice pattern as a whole, in which those belt-like regions are alternately crossed. The electrode non-formation region N corresponds to side margins and end margins of the multi-layer ceramic capacitor  10 . 
     The electrode non-formation region N in the second ceramic sheet  102  is also formed in a similar manner. 
       FIG.  8    is a partially enlarged cross-sectional view of the electrode non-formation region N between the internal electrode patterns  112  ( 113 ) adjacent to each other on the cross section taken along the C-C′ line of  FIG.  7 A . It should be noted that the electrode non-formation region N between the second internal electrode patterns  113  shown in  FIG.  7 B  has a configuration similar to that of the electrode non-formation region N between the first internal electrode patterns  112 . Accordingly, the electrode non-formation region N of both the first and second ceramic sheets  101  and  102  will be described with reference to  FIGS.  8  and  9   . 
     In  FIG.  8   , the internal electrode patterns  112  ( 113 ) each having a predetermined thickness d1 are formed on the ceramic sheet  101  ( 102 ). The thickness d1 of the internal electrode patterns  112  ( 113 ) is a mean thickness of the internal electrode patterns  112  ( 113 ) and can be calculated as, for example, a mean value of the thicknesses measured at a plurality of sites as in the case of the mean thickness of the ceramic layers  18 . 
     A space portion S sandwiched between the adjacent internal electrode patterns  112  ( 113 ) is formed in the electrode non-formation region N. The space portion S is a space region having a thickness d1 and facing to the electrode non-formation region N. In other words, the space portion S has a volume obtained by multiplying the area of the electrode non-formation region N by the thickness d1.  FIGS.  8  and  9    each show the space portion S surrounded by a thick broken line. 
     3.2 Step S 02 : Formation of Dielectric Pattern 
     In Step S 02 , a dielectric pattern P is formed in the electrode non-formation region N around the first internal electrode patterns  112  on the first ceramic sheet  101  and around the second internal electrode patterns  113  on the second ceramic sheet  102 . 
       FIG.  9    is a cross-sectional view of the same position as that of  FIG.  8    and shows a state in which the dielectric pattern P is formed in the space portion S. 
     The dielectric pattern P can be formed by applying a ceramic paste to the electrode non-formation region N of the ceramic sheet  101  ( 102 ). The ceramic paste only needs to mainly contain dielectric ceramics, but use of dielectric ceramics similar to that of the first and second ceramic sheets  101  and  102  leads to suppression of internal stress at the time of sintering. For the application of the ceramic paste, a screen printing method or a gravure printing method can be used, for example. 
     In this embodiment, the dielectric pattern P is formed to occupy 75% or more and less than 100% of the space portion S. In other words, the volume of the dielectric pattern P is 75% or more and less than 100% of the volume of the space portion S, the volume of the space portion S being obtained by multiplying the area of the electrode non-formation region N by the thickness d1 of the internal electrode pattern  112  ( 113 ). 
     A mean thickness of the dielectric pattern P only needs to be equal to or smaller than the thickness d1 of the space portion S. For example, the mean thickness of the dielectric pattern P may be 80% or more and 100% or less when the thickness d1 is assumed as 100%. The mean thickness of the dielectric pattern P can be a mean value measured in a similar manner to the case where the thicknesses of the first and second internal electrode patterns  112  and  113  are measured. 
     The ceramic sheet  101  ( 102 ) may have gaps Q, in which the dielectric pattern P is not formed, around the internal electrode patterns  112  ( 113 ). When the gaps Q between the internal electrode patterns  112  ( 113 ) and the dielectric pattern P are provided, the dielectric pattern P can be inhibited from being formed on the internal electrode patterns  112  ( 113 ). 
     3.3 Step S 03 : Lamination 
     In Step S 03 , the first and second ceramic sheets  101  and  102  prepared in Steps S 01  and S 02  and third ceramic sheets  103  are laminated as shown in  FIG.  10   , to produce a multi-layer sheet  104 . The third ceramic sheet  103  is a ceramic sheet on which the first and second internal electrode patterns  112  and  113  and the dielectric pattern P are not formed. It should be noted that  FIG.  10    omits the illustration of the gaps Q. 
     The multi-layer sheet  104  includes a laminated electrode sheet  105  and two laminated cover sheets  106 . The first ceramic sheets  101  and the second ceramic sheets  102  are alternately laminated in the Z-axis direction in the laminated electrode sheet  105 . Only the third ceramic sheets  103  are laminated in the laminated cover sheet  106 . The two laminated cover sheets  106  are provided on the upper surface and the lower surface of the laminated electrode sheet  105  in the Z-axis direction. The laminated electrode sheet  105  corresponds to the multi-layer unit  16  after sintering. The laminated cover sheets  106  correspond to the covers  17  after sintering. 
     The number of lamination of the first and second ceramic sheets  101  and  102  in the laminated electrode sheet  105  is adjusted so as to obtain a desired capacitance and a desired height dimension T after sintering. 
     The number of lamination of the third ceramic sheets  103  in the laminated cover sheet  106  is not limited to the example shown in  FIG.  10    and is adjusted as appropriate. 
     The multi-layer sheet  104  is integrated by pressure-bonding the first, second, and third ceramic sheets  101 ,  102 , and  103 . For the pressure-bonding of the first, second, and third ceramic sheets  101 ,  102 , and  103 , for example, hydrostatic pressing or uniaxial pressing is favorably used. This makes it possible to obtain a high-density multi-layer sheet  104 . 
     3.4 Step S 04 : Cutting 
     In Step S 04 , the multi-layersheet  104  obtained in Step S 03  is cut along the cutting lines Lx and Ly, to produce an unsintered ceramic body  111 . 
       FIG.  11    is a perspective view of the ceramic body  111  obtained in Step S 04 . 
     As shown in  FIG.  11   , the unsintered ceramic body  111  has two end surfaces  111   a  and  111   b  facing in the X-axis direction, two side surfaces  111   c  and  111   d  facing in the Y-axis direction, and two main surfaces  111   e  and  111   f  facing in the Z-axis direction. A cut portion corresponding to the laminated electrode sheet  105  is formed as an unsintered multi-layer unit  116 . Cut portions corresponding to the laminated cover sheets  106  are formed as unsintered covers  117 . 
     The unsintered ceramic body  111  has such an outer shape that the height dimension T in the Z-axis direction is 1.1 times or more and 1.6 times or less the width dimension in the Y-axis direction after sintering. Further, the main surfaces  111   e  and  111   f  each include a center region F′ that is defined in a manner similar to the center region F. A width dimension of the center region F′ in the Y-axis direction can be set to 80% or more and less than 100% of the width dimension of the unsintered ceramic body  111 , as in the case of the center region F. It should be noted that the unsintered ceramic body  111  may be chamfered by barrel polishing or the like after the cutting. In such a case, barrel polishing is performed such that the width dimension of the center region F′ falls within the range described above. 
     3.5 Step S 05 : Sintering 
     In Step S 05 , the unsintered ceramic body  111  obtained in Step S 04  is sintered, to produce the ceramic body  11  shown in  FIGS.  1  to  3   . In other words, in Step S 05 , the multi-layer unit  116  becomes the multi-layer unit  16 , and the covers  117  become the covers  17 . Sintering can be performed in a reduction atmosphere or a low-oxygen partial pressure atmosphere, for example. 
     3.6 Step S 06 : Formation of External Electrode 
     In Step S 06 , the first external electrode  14  and the second external electrode  15  are formed on the ceramic body  11  obtained in Step S 05 , to produce the multi-layer ceramic capacitor  10  shown in  FIGS.  1  to  3   . 
     In Step S 06 , first, an unsintered electrode material is applied so as to cover one of the end surfaces of the ceramic body  11  that face in the X-axis direction, and then applied so as to cover the other end surface of the ceramic body  11  that faces in the X-axis direction. The unsintered electrode material applied to the ceramic body  11  is baked in a reduction atmosphere or a low-oxygen partial pressure atmosphere, for example, to form base films on the ceramic body  11 . On the base films baked onto the ceramic body  11 , intermediate films and surface films are formed by plating such as electrolytic plating, thus completing the first external electrode  14  and the second external electrode  15 . 
     It should be noted that part of the processing in Step S 06  described above may be performed before Step S 05 . For example, before Step S 05 , the unsintered electrode material may be applied to both the end surfaces of the unsintered ceramic body  111  that face in the X-axis direction, and in Step S 05 , the unsintered ceramic body  111  may be sintered and, simultaneously, the unsintered electrode material may be baked to form the base films of the first external electrode  14  and the second external electrode  15 . Alternatively, the unsintered electrode material may be applied to the ceramic body  111  that has been subjected to debinder processing, to simultaneously sinter the unsintered electrode material and the ceramic body  111 . 
     As shown in  FIGS.  1  to  3   , the ceramic body  11  thus produced has the height dimension T in the Z-axis direction, which is 1.1 times or more and 1.6 times or less the width dimension W in the Y-axis direction, and includes the flat center regions F. In Step S 02 , the center region F is formed by forming the dielectric pattern P that occupies 75% or more and less than 100% of the space portion S. 
     If the dielectric pattern is not formed, a capacitance forming portion in which the internal electrode patterns are laminated and a side margin portion in which the electrode non-formation regions are laminated have a difference in height dimension in the Z-axis direction due to the thicknesses of the internal electrode patterns. Additionally, as the number of lamination of the ceramic sheets becomes larger, that is, as the height dimension of the multi-layer ceramic capacitor becomes larger, the difference in height dimension in the Z-axis direction between the above-mentioned portions becomes larger. For that reason, in the ceramic body in which the laminated ceramic sheets are pressure-bonded and cut, the height dimension gradually increases from the peripheral portions in the Y-axis direction toward the center portion in the Y-axis direction, and the main surfaces are formed as curved surfaces protruding in the Z-axis direction. 
     Further, if the dielectric pattern is intended to be formed on the entire electrode non-formation region N (i.e., in a state of occupying 100% of the space portion), even with a slight displacement of the dielectric pattern, the dielectric pattern overlaps with the internal electrode patterns. Accordingly, the thickness of the overlapping portion increases, and the height of the ceramic body in the Z-axis direction becomes uneven. 
     Meanwhile, when the proportion of the dielectric pattern occupying the space portion is less than 75%, a gap between the internal electrode pattern and the dielectric pattern becomes larger. As a result, the laminated ceramic sheets sink down into the gaps at the time of pressure-bonding, and the height of the ceramic body in the Z-axis direction becomes uneven again. 
     In this embodiment, the dielectric pattern P is formed so as to occupy 75% or more of the space portion S, and thus the gaps Q can be made small to such an extent that the ceramic sheets laminated in Step S 03  do not sink down into the gaps Q. Accordingly, the height of the laminated electrode sheet  105  in the Z-axis direction can be formed to be uniform, and the center regions F′ are formed in the unsintered ceramic body  111 . Therefore, the center regions F are also formed in the sintered ceramic body  11 . 
     Further, the dielectric pattern P is formed so as to occupy a portion less than 100% of the space portion S, and thus narrow gaps Q can be provided in the electrode non-formation region N. Accordingly, even when the dielectric pattern P is slightly displaced with respect to the internal electrode patterns  112  ( 113 ), the displacement is mitigated by the gaps Q. Therefore, it is possible to reduce the risk of overlapping of the dielectric pattern P with the internal electrode patterns  112  ( 113 ). 
     Additionally, after the production, the multi-layer ceramic capacitor  10  is packaged as a package  100  with the center region F being faced upward in the Z-axis direction. Accordingly, a mounting step of taking the multi-layer ceramic capacitor  10  out of the package  100  and mounting the multi-layer ceramic capacitor  10  to an electronic device can be smoothly performed. 
     Hereinafter, the configuration of the package  100  and a method of mounting the multi-layer ceramic capacitor  10  will be described in detail. 
     4. Configuration of Package  100  for Multi-Layer Ceramic Capacitor  10   
       FIG.  12    is a plan view of the package  100  for the multi-layer ceramic capacitor  10 .  FIG.  13    is a cross-sectional view taken along the D-D′ line in  FIG.  12   . It should be noted that the configuration of the package  100  according to this embodiment is not limited to the configuration shown in  FIGS.  12  and  13   . 
     For example, the package  100  is long in the Y-axis direction, has a predetermined depth in the Z-axis direction, and houses a plurality of multi-layer ceramic capacitors  10 . 
     The package  100  includes a housing portion  110 , a sealing portion  120 , and a plurality of multi-layer ceramic capacitors  10 . 
     The housing portion  110  includes a plurality of recesses  110   a  formed at predetermined intervals along the Y-axis direction. 
     The housing portion  110  is typically a carrier tape, but it may be a chip tray in which the recesses  110   a  that house the multi-layer ceramic capacitors  10  are arranged in a lattice pattern, for example. Further, a material forming the housing portion  110  is also not particularly limited, and a synthetic resin, paper, or the like can be used therefor. 
     The recess  110   a  is formed downward from an upper surface  110   c  of the housing portion  110  in the Z-axis direction and has a size capable of housing each multi-layer ceramic capacitor  10 . A take-out opening  110   b  is formed on the upper surface  110   c  side of the recess  110   a . The take-out opening  110   b  is used when the multi-layer ceramic capacitor  10  is housed in the recess  110   a  and taken out of the recess  110   a . 
     The sealing portion  120  is disposed on the housing portion  110  so as to be capable of being peeled off. The sealing portion  120  is formed to cover the take-out openings  110   b  of the recesses  110   a  in the Z-axis direction. The sealing portion  120  is typically a cover tape, but it is not particularly limited as long as the sealing portion  120  is a member capable of being peeled off from the housing portion  110  and having a function of sealing the recesses  110   a . Further, the sealing portion  120  may be made of the same type of material as that of the housing portion  110  or may be made of a different material. 
     The multi-layer ceramic capacitor  10  is housed in the recess  110   a  with the flat center region F being faced to the take-out opening  110   b  side (upward in the Z-axis direction). It is favorable that the center region F on the take-out opening  110   b  side is formed such that the width dimension Wf is 80% or more and less than 100% of the width dimension W of the ceramic body  11 . 
     If the main surfaces  11   e  and  11   f  include the respective center regions F, one of the main surfaces  11   e  and  11   f  is faced upward in the Z-axis direction when the multi-layer ceramic capacitor  10  is housed. If one of the main surfaces  11   e  and  11   f  includes the center region F, the one of the main surfaces  11   e  and  11   f , which includes the center region F, is faced upward in the Z-axis direction when the multi-layer ceramic capacitor  10  is housed. 
     5. Method of Mounting Multi-Layer Ceramic Capacitor  10   
       FIG.  14    is a cross-sectional view schematically showing a step of mounting the multi-layer ceramic capacitor  10 , which shows a cross section corresponding to  FIG.  13   .  FIG.  15    is a cross-sectional view of a multi-layer ceramic capacitor mounting substrate (mounting substrate)  200 , onto which the multi-layer ceramic capacitor  10  is mounted, when viewed in the Y-axis direction. 
     The multi-layer ceramic capacitors  10  are taken out of the package  100  one by one and are mounted onto a circuit board  210  of an electronic device. Hereinafter, description will be given with reference to  FIGS.  14  and  15   . 
     First, the sealing portion  120  is peeled off from the housing portion  110 . Subsequently, as shown in  FIG.  14   , the multi-layer ceramic capacitor  10  is taken out through the take-out opening  110   b  of the package  100  by using a suction nozzle M of a chip mounter. The suction nozzle M holds the flat center region F by suction from above in the Z-axis direction, the flat center region F being faced to the take-out opening  110   b  side. 
     The suction nozzle M moves the multi-layer ceramic capacitor  10  onto the circuit board  210  while keeping suction of the center region F. The suction nozzle M disposes the multi-layer ceramic capacitor  10  at a predetermined position on the circuit board  210 , and then releases the suction. At that time as well, the center region F is faced upward in the Z-axis direction. 
     Subsequently, the first and second external electrodes  14  and  15  of the multi-layer ceramic capacitor  10  and the circuit board  210  are bonded to each other in the Z-axis direction by solder H or the like, and a mounting substrate  200  onto which the multi-layer ceramic electronic component  10  is mounted is formed as shown in  FIG.  15   . 
     Also in the mounting substrate  200 , the multi-layer ceramic capacitor  10  is mounted with the center region F being faced upward in the Z-axis direction. 
     Here, if the dielectric pattern is not formed to have the volume occupying 75% or more and less than 100% of the space portion, as described above, the center portion of the main surface of the ceramic body has a curved surface. In this case, a gap is generated between the tip of the suction nozzle M and the main surface of the ceramic body, and the suction by the suction nozzle M becomes insufficient. Therefore, there is a possibility that a failure, such as the difficulty of performing suction of the main surface of the multi-layer ceramic capacitor or the drop of the multi-layer ceramic capacitor in the process of transfer, occurs in the mounting step. 
     In this embodiment, the flat center region F is formed on at least one of the main surface  11   e  or  11   f  of the ceramic body  11 , and the multi-layer ceramic capacitor  10  is packaged with the center region F being faced upward in the Z-axis direction. Accordingly, the tip of the suction nozzle M and the center region F of the ceramic body  11  come into close contact with each other, so that the suction nozzle M can stably perform suction of the center region F. Therefore, it is possible to inhibit failures from occurring at the time of suction by the suction nozzle M and to smoothly mount the multi-layer ceramic capacitor  10 . 
     Further, in the multi-layer ceramic capacitor  10 , the height dimension T of the ceramic body  11  is set to be 1.1 times or more and 1.6 times or less the width dimension W thereof. Thus, the multi-layer ceramic capacitor  10  can keep the balance thereof even if the height dimension T is larger than the width dimension W. Accordingly, in the recess  110   a  of the package  100  or in the mounting step, the multi-layer ceramic capacitor  10  can be inhibited from falling down and can be handled at a posture at which the height direction of the multi-layer ceramic capacitor  10  coincides with the Z-axis direction. This also allows the multi-layer ceramic capacitor  10  to be smoothly mounted. 
     Additionally, setting the length dimension L of the ceramic body  11  to be larger than 1.0 times and equal to or smaller than 1.5 times the height dimension T also enables the balance of the ceramic body  11  to be kept. Therefore, handleability at the time of mounting of the multi-layer ceramic capacitor  10  can be more improved. 
     In such a manner, according to the multi-layer ceramic capacitor  10 , a failure caused at the time of mounting can be inhibited from occurring even if the number of lamination of the first and second internal electrodes  12  and  13  is increased, so that the capacitance can be increased without changing the mounting area. Therefore, it is possible to achieve the multi-layer ceramic capacitor  10  having a large capacitance and capable of contributing to reduction in size of the electronic device. 
     6. Examples and Comparative Examples 
     As Examples and Comparative examples of this embodiment, samples of the multi-layer ceramic capacitor  10  were produced by the production method described above, and the shape and a suction rate of the suction nozzle M were investigated. 
     irst, samples (Examples 1 to 3 and Comparative examples 1 and 2) of the multi-layer ceramic capacitor were produced. The samples had three sizes: a first size having a length dimension (L) of 0.69 mm, a width dimension (W) of 0.39 mm, and a height dimension (T) of 0.55 mm; a second size having a length dimension (L) of 1.15 mm, a width dimension (W) of 0.65 mm, and a height dimension (T) of 1.00 mm; and a third size having a length dimension (L) of 1.20 mm, a width dimension (W) of 0.75 mm, and a height dimension (T) of 0.85 mm. In other words, a ratio of the length dimension to the height dimension (L/T) was 1.15 to 1.41, and a ratio of the height dimension to the width dimension (T/W) was 1.13 to 1.54. Further, in the following evaluation, 100 samples for each of the three sizes for each of Examples and Comparative examples, i.e., 1,500 samples in total were used. 
     In each of the samples of Examples 1 to 3 and Comparative example 1, a dielectric pattern was formed. Table 1 shows a volume ratio of the dielectric pattern to the volume of the space portion (space occupancy rate), the volume of the space portion being obtained by multiplying the area of the electrode non-formation region by the thickness of the internal electrode pattern. It should be noted that a value of the space occupancy rate shown in Table 1 was a mean value of the 300 samples for each of Examples and Comparative examples. 
     The space occupancy rate was 95% in Example 1, 90% in Example 2, and 75% in Example 3, all of which were 75% or more and less than 100%. Meanwhile, in Comparative example 1, the space occupancy rate was 50%. In Comparative example 2, the space occupancy rate was 0% because the dielectric pattern was not formed.  
     
       
         
          TABLE 1
           
               
               
               
               
             
               
                   
                 Space occupancy rate 
                 Wf/W 
                 Suction rate 
               
             
            
               
                 Example 1 
                 95% 
                 85% 
                 99% 
               
               
                 Example 2 
                 90% 
                 83% 
                 99% 
               
               
                 Example 3 
                 75% 
                 82% 
                 99% 
               
               
                 Comparative example 1 
                 50% 
                 65% 
                 92% 
               
               
                 Comparative example 2 
                 0% 
                 35% 
                 85% 
               
            
           
         
       
     
     Further, a proportion (Wf/W) of the width dimension (Wf) of the flat center region to the width dimension (W) of the multi-layer ceramic capacitor was measured. Table 1 shows the results of the measurement. It should be noted that a value of the proportion of the width dimension shown in Table 1 was a mean value of the 300 samples for each of Examples and Comparative examples. Further, for a value of the proportion of the width dimension in each sample, one of the two main surfaces of each sample, which has a larger proportion of the width dimension of the center region, was employed. 
     The proportion of the width dimension was 85% in Example 1, 83% in Example 2, and 82% in Example 3, all of which were 80% or more in Examples 1 to 3. Meanwhile, the proportion of the width dimension was 65% in Comparative example 1, and 35% in Comparative example 2, all of which were less than 80%. 
     The proportion (Wf/W) of the width dimension showed a positive relationship with the space occupancy rate of the dielectric pattern. Specifically, in Examples 1 to 3 in which the space occupancy rate is 75% or more and less than 100%, the Wf/W was 80% or more in each example. However, in Comparative examples 1 and 2 in which the space occupancy rate was 50% or less, the Wf/W was 65% or less in each example. From those results, it was confirmed that when the space occupancy rate of the dielectric pattern is set to 75% or more and less than 100%, the center region can be formed such that the proportion of the width dimension is 80% or more. 
     Subsequently, a housing portion including recesses in a package was prepared, and each sample was held in the recess with a main surface being faced to the take-out opening side, the main surface including the center region having a larger proportion of the width dimension. The main surface of each sample on the take-out opening side was tried to be subjected to suction by a suction nozzle of a chip mounter. In the 300 samples of each of Examples and Comparative Examples, a proportion of the samples whose main surfaces could be subjected to suction was calculated as a “suction rate”. Table 1 shows the results thereof. 
     As shown in Table 1, it was confirmed that the suction rate is 99% in all of Examples 1 to 3, almost all of the samples can be subjected to suction, and the handleability at the time of mounting are optimal. Meanwhile, the suction rate was 92% in Comparative example 1 and 85% in Comparative example 2, in which the suction failed in approximately 10 to 20% of the samples. Accordingly, it was confirmed that the handleability at the time of mounting in Comparative examples 1 and 2 are inferior to those in Examples 1 to 3. 
     7. Other Embodiments 
     Hereinabobve, the embodiment of the present disclosure has been described, but the present disclosure is not limited to the embodiment described above, and it should be appreciated that the present disclosure may be variously modified without departing from the gist of the present disclosure. For example, the embodiment of the present disclosure can be an embodiment in which some embodiments are combined. 
     For example, in the multi-layer ceramic capacitor  10 , the multi-layer unit  16  may be divided into a plurality of multi-layer units  16  and then disposed in the Z-axis direction. In this case, in each multi-layer unit  16 , the first and second internal electrodes  12  and  13  only need to be alternately disposed along the Z-axis direction, and the first internal electrodes  12  or the second internal electrodes  13  may be consecutively disposed at portions where the multi-layer units  16  are adjacent to each other. 
     Further, in the embodiment described above, the multi-layer ceramic capacitor has been described as an example of a ceramic electronic component, but the present disclosure can be applied to any other multi-layer ceramic electronic components in which paired internal electrodes are alternately disposed. Examples of such multi-layer ceramic electronic components include a piezoelectric element.