Patent Publication Number: US-7899961-B2

Title: Multi-mode bus inversion method and apparatus

Description:
BACKGROUND OF THE INVENTION 
     Integrated circuits such as microprocessors, digital signal processors, memory devices, application-specific integrated circuits (ASICs) and the like typically have one or more buses for carrying data, address and/or control information. Driver circuitry is used to drive the information off-chip on the buses. The driver circuitry is typically inverter-type, i.e., when a bit is a logic one, there is no current path, and when a bit is a logic zero, there is a current path through the transmission medium. As such, current consumed by the driver circuitry varies over time as a function of bus voltage level, causing interference. 
     Data Bus Inversion for DC (DBIdc) is one conventional approach for reducing static or quiescent current draw by data bus driver circuitry. DBIdc involves counting the number of ones and zeros in a data word. If the number of zeros exceeds a predetermined count value, the data word is inverted and a flag is set to indicate the data word has been inverted. Otherwise, the data word is not inverted and the flag is not set. This way, fewer logic zeroes are transmitted and power consumption is correspondingly reduced. The entity that receives the data word interrogates the flag to determine whether the data word has been inverted. The receiver inverts each bit of the data word if the flag is set, else the word is taken as-is. 
     However, not all DBIdc schemes are the same. Take, for example, memory devices. Different DBIdc schemes are specified across various memory standards. For example, the GDDR4 (Graphics Double Data Rate, version 4) graphics memory standard employs a DBIdc scheme having a predetermined count value of four in a byte-wise DBIdc scheme (i.e., data words are 8 bits in length). A DBIdc flag is set to a logic high state when the number of zeros in a data word exceeds four, indicating bus inversion has occurred. According to the LPDDR2 (Low Power DDR2) DBIdc scheme, the predetermined count value is three and the flag is also set to a logic high state for indicating data bus inversion. The GDDR5 (Graphics Double Data Rate, version 5) DBIdc scheme uses a count value of four as in GDDR4, but the flag is set to a logic low state for indicating data bus inversion. Memory devices are conventionally designed to accommodate the DBIdc scheme associated with a singular application, e.g., GDDR4, GDDR5, LPDDR2, etc. This limits memory device use to a particular application or requires re-design or other alteration each time the device is used in a different application. 
     SUMMARY OF THE INVENTION 
     In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured. 
     Of course, the present invention is not limited to the above features and advantages. Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an embodiment of an integrated circuit including multi-mode bus inversion circuitry. 
         FIG. 2  is a logic flow diagram of an embodiment of program logic for performing bus inversion. 
         FIG. 3  is a block diagram of an embodiment of encoder logic included in or associated with the multi-mode bus inversion circuitry of  FIG. 1 . 
         FIG. 4  is a block diagram of an embodiment of bus inversion logic included in or associated with the encoder logic of  FIG. 3 . 
         FIG. 5  is a block diagram of an embodiment of decoder logic included in or associated with the multi-mode bus inversion circuitry of  FIG. 1 . 
         FIG. 6  is a block diagram of an embodiment of bus inversion logic included in or associated with the decoder logic of  FIG. 5 . 
         FIG. 7  is a block diagram of an embodiment of a memory device including multi-mode bus inversion circuitry. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  illustrates an embodiment of an integrated circuit (IC)  100  such as a microprocessor, digital signal processor, memory device, ASIC or the like. Logic  102  included in the IC  100  performs various functions for which the IC  100  is designed. Accordingly, the logic  102  may include analog, digital and/or mixed signal logic, registers, memory arrays, fuses, arithmetic logic units, floating point units, integer units, etc. or any combination thereof. One or more buses  104  included in the IC  100  carry words of information to (DATA IN ) and from (DATA OUT ) the logic  102 . The term “word” as used herein means any unit of information such as data, address and/or control information used by the IC  100 . The number of bits in a word (the word size or word length) depends on the structure and operation of the IC  100 . Many processor-based ICs typically have a word size of 32, 64 or 128 bits while memory-based ICs typically have a word size of 4, 8 or 16 bits. However, other sizes are also common, including 8, 9, 12, 18, 24, 36, 39, 40, 48, and 60 bits. Accordingly, the IC  100  can process words having any number of bits. 
     The IC  100  also has multi-mode bus inversion circuitry  106  for configuring the IC  100  to implement one of a plurality of bus inversion schemes each of which the IC  100  is capable of performing, e.g., as illustrated by Step  200  of  FIG. 2 . This way, the IC  100  can readily support different applications having disparate bus inversion schemes without re-design or other alteration. The bus inversion circuitry  106  includes mode selection logic  108  for determining which one of the supported bus inversion schemes should be implemented during IC operation. This determination is made based on bus inversion configuration information provided to the mode selection logic  108 . In one embodiment, the configuration information is hard-wired in that it can be stored in fuses (not shown) included in the IC  100 , or provided to the IC  100  via bonding wires, pins or other external hard-wired connections (also not shown). In another embodiment, the configuration information is programmable via software such as by the mode select feature available to many memory devices. This way, the IC  100  can be re-configured to implement different ones of the bus inversion schemes. 
     Either way, the mode selection logic  108  processes the configuration information to determine which one of the supported bus inversion schemes should be implemented by the IC  100 . The multi-mode bus inversion circuitry  106  processes data input to and output from the IC  100  based on the bus inversion scheme selected by the mode selection logic  108 , e.g., as illustrated by Step  202  of  FIG. 2 . To this end, the bus inversion circuitry  106  includes encoder and decoder logic  110 ,  112 . The mode selection logic  108  indicates to the encoder and decoder logic  110 ,  112  which bus inversion scheme has been selected, e.g., via a MODE indicator output by the mode selection logic  108  as shown in  FIG. 1 . The encoder logic  110  processes information output from the IC logic  102  based on the selected bus inversion scheme. The decoder logic  112  similarly processes information input to the IC  100  according to the present bus inversion scheme. 
     In more detail, the encoder logic  110  inverts each word of information (DATA OUT ) output by the IC logic  102  having a total number of zero bits exceeding a count value associated with the selected bus inversion scheme. In one embodiment, the count value is four for an 8-bit bus. In another embodiment, the count value is three for an 8-bit bus. Those skilled in the art will readily recognize that any count value may be used by the encoder logic  110  for determining when to perform bus inversion. The encoder logic  110  also sets an output flag (FLAG OUT ) in accordance with the selected bus inversion scheme to indicate when the IC  100  outputs an information word (DATA OUT     —     ENC ) which has been inverted. In one embodiment, the output flag is set when driven to a logic one state. In another embodiment, a logic low state indicates data inversion has been performed. Those skilled in the art will readily recognize that the encoder logic  110  may indicate bus inversion in various other ways. 
       FIG. 3  illustrates an embodiment of the encoder logic  110  included in or associated with the multi-mode bus inversion circuitry  106 . According to this embodiment, the encoder logic  110  includes counter logic  300  and bus inversion logic  302 . The counter logic  300  determines when an information word (DATA OUT ) output by the IC logic  102  should be inverted based on the bus inversion scheme selected by the mode selection logic  108 . In one embodiment, the MODE indicator output by the mode selection logic includes a count value parameter  304  and a flag type parameter  306 . The count value  304  indicates how many zeros should be in a word of information to warrant inversion. The flag type  306  determines how the IC  100  indicates when bus inversion has occurred, e.g., a logic high or logic zero indicator. In one embodiment, one or more register bits or latches  308  included in or associated with the multi-mode bus inversion circuitry  106  are set to indicate which one of the bus inversion schemes has been selected. In one embodiment, the register bits/latches  308  are set to indicate the count value and flag type associated with the bus inversion scheme currently implemented by the IC  100 . The register/latch state can be changed to indicate a newly selected bus inversion scheme. In another embodiment, a lookup table (not shown) is used to identify the count value and flag type associated with the selected bus inversion scheme. 
     Regardless, the counter logic  300  uses the count value  304  to determine when information words (DATA OUT ) output from the IC logic  102  should be inverted. In one embodiment, the counter logic  300  is a programmable counter initialized with the current count value  304 . In another embodiment, the counter logic  300  includes multiple counters each initialized to a different one of the count values  304  associated with the bus inversion schemes supported by the IC  100 . Regardless, the counter logic  300  examines information words to determine whether the total number of zero bits included in each word exceeds the current count value  304 . The output (INVERT) of the counter logic  300  is activated each time the count value  304  is exceeded and the bus inversion logic  302  inverts the corresponding word. The bus inversion logic  302  also sets the output flag (FLAG OUT ) in accordance with the current flag type parameter  306  for indicating that a word output by the IC  100  has been inverted. This way, an entity that receives the word is aware that it has been inverted. The bus inversion logic  302  does not invert information words nor does it set the output flag when the output of the counter logic  300  is not activated. 
       FIG. 4  illustrates an embodiment of the bus inversion logic  302 . Each bit (DATA OUT &lt;0:n&gt;) of an information word output by the IC logic  102  is input to a respective exclusive-OR (XOR) logic gate  400 . The other input of each XOR logic gate  400  is coupled to the output (INVERT) of the counter logic  300 . This way, when the counter logic output is activated at a logic high state to indicate the current count value has been exceeded, each bit of the corresponding word is inverted by the respective XOR logic gates  400  to form the information word (DATA OUT     —     ENC ) output by the IC  100 . 
     The bus inversion logic  302  also sets the output flag (FLAG OUT ) in accordance with the current flag type parameter  306  to indicate that the current word has been inverted. In one embodiment, the counter logic output (INVERT) is coupled to one input of a multiplexer  402 . The counter output is also provided to an inverter  404 , the output of which is coupled to another input of the multiplexer  402 . The current flag type parameter  306  determines which multiplexer input is selected for the flag output. If the current flag type  306  has a logic high polarity for indicating data inversion, the un-inverted counter logic output (INVERT) is selected as the flag output because it is driven to a logic high state when bus inversion occurs. Conversely, the inverted counter logic output (  INVERT ) is selected when the current flag type  306  has a logic low polarity for indicating data inversion because the output of the inverter  404  is at a logic low state when bus inversion occurs. 
     Regardless, the bus inversion logic  302  inverts outgoing information when the counter logic  300  determines that the current count value  306  has been exceeded and sets the output flag to indicate bus inversion has occurred. On the other hand, the XOR logic gates  400  of the bus inversion logic  302  pass the outgoing information un-inverted when the counter logic output is not activated. This way, the IC  100  can readily accommodate any desired bus inversion scheme for outputting information. The multi-mode bus inversion circuitry  106  ensures that the same holds true on the input-side of the IC  100  so that the IC  100  is fully compatible with multiple bus inversion schemes. To this end, the decoder logic  112  included in or associated with the multi-mode bus inversion circuitry  106  is similarly made aware of the selected bus inversion scheme and processes information input to the IC  100  according to the selected scheme. 
       FIG. 5  illustrates an embodiment of the decoder logic  112 . According to this embodiment, the decoder logic  112  includes bus inversion logic  500 . The bus inversion logic  500  compares a bus inversion flag (FLAG IN ) input to the IC  100  with the current flag type  306  to determine whether an information word (DATA IN     —ENC   ) input to the IC  100  has been inverted. If the flag is set, the bus inversion logic  500  inverts the word and passes it to the IC logic  102  for processing (DATA IN ). Otherwise, the received word is passed un-inverted to the IC logic  102 . 
       FIG. 6  illustrates an embodiment of the bus inversion logic  500  included in or associated with the decoder logic  112 . Each bit (DATA IN     —     ENC &lt;0:n&gt;) of an information word received by the IC  100  is input to a respective XOR logic gate  600 . The other input of each XOR logic gate  600  is coupled to the output of a multiplexer  602 . The multiplexer  602  has two inputs. One input is the flag input received by the IC  100 . The flag input is also provided to an inverter  604 , the output of which serves as the other multiplexer input. The current flag type  306  controls the multiplexer  602 . If the current flag type  306  has a logic high polarity for indicating bus inversion, the multiplexer  602  selects the un-inverted flag input (FLAG IN ). Otherwise, the inverted flag input is selected. This way, each bit (DATA IN     —     ENC &lt;0:n&gt;) of a received word is inverted by the respective XOR logic gates  600  when the input flag is set regardless of its polarity, i.e., regardless of whether the flag is set to a logic high or low state to indicate bus inversion has occurred. Thus, the multi-mode bus inversion circuitry  106  ensures that the IC  100  is readily compatible with a plurality of bus inversion schemes used to process information input to and output from the IC  100 . 
       FIG. 7  illustrates a memory device embodiment of the IC  100 . According to this embodiment, a memory device  700  includes one or more banks of memory arrays  702  for storing data. Each memory array bank  702  includes a plurality of memory cells (not shown) having a storage element located at the intersection of a word line (i.e., row) and bit line (i.e., column). Control logic  704  included in the memory device  700  receives input control signals such as chip select (CS), row address strobe (RAS), column address strobe (CAS), clock enable (CKE) and write enable (WE) signals in synchronization with a system clock (CK). 
     The control logic  704  decodes the input control signals into one or more commands. Each decoded command instructs the memory device  700  to perform a particular operation. In response to a decoded command, the control logic  704  enables, disables, or otherwise controls various functions of the memory device  700  in order to execute particular commands. Data input/output (I/O) circuitry  706  samples, or captures, input data signals during write operations and drives output data signals during read operations. An address register  708  stores a row, column and bank address (ROW/COL/BANK ADDR) associated with a particular array location at which data is to be read from or written to during a normal memory operation, i.e., a non-refresh operation. 
     The row and column addresses are provided to row and column latch and decoder circuits  710 ,  712 , respectively. Particularly, the address register  708  provides a row address (row_addr) to the row address latch and decoder circuit  710  for activating a corresponding word line (row_sel) in the memory array  702 . The address register  708  also provides a column address (col_addr) to the column address latch and decoder circuit  712  for activating a corresponding bit line (col_sel) in the memory array  702 . As such, a specific word and bit line of the memory array  702  can be selected, or activated, in response to an address associated with a particular command. 
     The data I/O circuitry  706  provides a data read/write gating mechanism by which data is either read from or written to the selected memory array location. This includes a plurality of sense amplifiers (not shown) and I/O gating circuits such as read latches and write drivers (not shown). The sense amplifiers and I/O gating circuits can be arranged in any suitable configuration such as local, sub-array, global or other shared or unshared configurations. The read latches provide data sampled by the sense amplifiers to the data I/O circuitry  706  for external transmission during a read operation. The write drivers provide data to the memory array  702  for storing the data during a write operation. The data I/O circuitry  706  enables specific I/O gating circuits associated with targeted memory cells during a particular operation. 
     The multi-mode bus inversion circuitry  106  is included in or associated with the data I/O circuitry  706  to enable data bus inversion. The memory device  700  obtains data bus inversion configuration information indicating one of a plurality of data bus inversion schemes each of which the memory device  700  is capable of performing. The multi-mode bus inversion circuitry  106  configures the memory device  700  to implement the data bus inversion scheme indicated by the configuration information and processes data written to and read from the memory device  700  based on the data bus inversion scheme for which the memory device  700  is configured as generally described above. This way, any one of a plurality of data bus inversion schemes supported by the memory device  700  can be selected for implementation by the memory device  700 . In one embodiment, the memory device  700  is capable of performing the data bus inversion schemes associated with at least the GDDR4, GDDR5 and/or LPDDR2 memory standards. The multi-mode bus inversion circuitry  106  generally permits the memory device  700  to be readily configured for different applications without requiring re-design or alteration. 
     With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.