Patent Publication Number: US-2022223623-A1

Title: Logic cell with small cell delay

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority of U.S. Provisional Application No. 63/135,766, filed on Jan. 11, 2021, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a logic cell, and more particularly to a logic cell with diffusion break (DB) structure. 
     Description of the Related Art 
     Integrated circuits (ICs) have become increasingly important. Applications using ICs are used by millions of people. These applications include cell phones, smartphones, tablets, laptops, notebook computers, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless web browsers. Integrated circuits increasingly include powerful and efficient on-board data storage and logic circuitry for signal control and processing. 
     With the increasing down-scaling of integrated circuits, the integrated circuits become more compact. For standard cells that are frequently used in integrated circuits, when the number of standard cells is increased, the chip area is increased. Therefore, a standard cell with a smaller area and better efficiency is desired. 
     BRIEF SUMMARY OF THE INVENTION 
     Semiconductor structures are provided. An embodiment of a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a logic cell with a logic function. The logic cell includes a plurality of first transistors in an active region over the semiconductor substrate, a second transistor in the active region, a third transistor in the active region, a first isolation structure and a second isolation structure on opposite edges of the active region and extending along the first direction. Each of the first transistors includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure. The first and second isolation structures and the first gate electrode have a first length in the first direction. The second and third gate electrodes have a second length in the first direction. The second length is shorter than the first length. 
     Furthermore, an embodiment of a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a logic cell with a first logic function and a second logic function. The logic cell includes at least one first transistor in an active region over the semiconductor substrate, at least one second transistor in the active region, a first isolation structure disposed on a first edge of the active region and extending along the first direction, and a second isolation structure disposed on a second edge of the active region and extending along the first direction. The first transistor includes a first gate electrode extending along the first direction, and the first transistor is configured to perform the first logic function. The second transistor includes a second gate electrode extending along the first direction, wherein the second transistor is configured to perform the second logic function. The first gate electrode is disposed between the first isolation structure and the second gate electrode, and the second gate electrode is disposed between the first gate electrode and the second isolation structure. The first edge of the active region is opposite the second edge of the active region. 
     Moreover, an embodiment of a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a logic cell with a logic function. The logic cell includes a plurality of P-type transistors in a first active region over the semiconductor substrate, a plurality of N-type transistors in a second active region over the semiconductor substrate, a first isolation structure and a second isolation structure on opposite edges of the first active region and opposite edges of the second active region, a first transistor in the first active region and between the first isolation structure and the P-type transistors, a second transistor in the first active region and between the second isolation structure and the P-type transistors, a third transistor in the second active region and between the first isolation structure and the N-type transistors, and a fourth transistor in the second active region and between the second isolation structure and the N-type transistors. Each of the P-type transistors includes a first gate electrode extending along the first direction. Each of the N-type transistors shares the first gate electrode with a respective P-type transistor. The first and second isolation structures extend along the first direction. The first transistor includes a second gate electrode extending along the first direction. The second transistor includes a third gate electrode extending along the first direction. The first and third transistors share the second gate electrode. The second and fourth transistors share the third gate electrode. The P-type transistors and the N-type transistors are configured to perform the logic function. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows a simplified diagram illustrating a cell array of an IC according to some embodiments of the invention. 
         FIG. 2  shows a simplified diagram illustrating a row in the cell array of  FIG. 1  according to some embodiments of the invention. 
         FIG. 3A  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 3B  shows a cross-sectional view of the semiconductor structure of the logic cell along line A-AA in  FIG. 3A  according to some embodiments of the invention. 
         FIG. 3C  shows a cross-sectional view of the semiconductor structure of the logic cell along line B-BB in  FIG. 3A  according to some embodiments of the invention. 
         FIG. 4  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 5  shows a diagram illustrating the relationship between cell delay and diffusion edge extension according to some embodiments of the invention. 
         FIG. 6  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 7A  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 7B  shows a cross-sectional view of the semiconductor structure of the logic cell along line C-CC in  FIG. 7A  according to some embodiments of the invention. 
         FIG. 7C  shows a cross-sectional view of the semiconductor structure of the logic cell along line D-DD in  FIG. 7A  according to some embodiments of the invention. 
         FIG. 8  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 9  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 10A  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 10B  shows a cross-sectional view of the semiconductor structure of the logic cell along line E-EE in  FIG. 10A  according to some embodiments of the invention. 
         FIG. 11  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 12  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 13A  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 13B  shows a cross-sectional view of the semiconductor structure of the logic cell along line F-FF in  FIG. 13A  according to some embodiments of the invention. 
         FIG. 14  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 15  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 16  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 17  shows a simplified diagram illustrating a logic cell according to some embodiments of the invention. 
         FIG. 18  shows a simplified diagram illustrating a grouping logic cell according to some embodiments of the invention. 
         FIG. 19  shows a simplified diagram illustrating a grouping logic cell according to some embodiments of the invention. 
         FIG. 20  shows a simplified diagram illustrating a grouping logic cell according to some embodiments of the invention. 
         FIG. 21  shows a simplified diagram illustrating a grouping logic cell according to some embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method. 
     Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. 
       FIG. 1  shows a simplified diagram illustrating a cell array  100  of an IC according to some embodiments of the invention. The cell array  100  includes multiple logic cells  10 . In some embodiments, the logic cells  10  are the standard cells (e.g., INV (inverter), AND, OR, NAND, NOR, Flip-Flop, SCAN, etc.), a combination thereof or specific logic functional cells. Furthermore, the logic functions of the logic cells  10  may be the same or different. Furthermore, each of the logic cells  10  includes a plurality of transistors. In some embodiments, the logic cells  10  corresponding to the same function or operation may have the same circuit configuration with different semiconductor structures and/or different layouts. In  FIG. 1 , the logic cells  10  have the same cell height H 1  (e.g., along the Y-direction) in the layout. Furthermore, the logic cells  10  may have the same or different cell widths (e.g., along X-direction) in the layout. It should be noted that the number and the configuration of the logic cells  10  are used as an example, and not to limit the invention. 
     In some embodiments, the transistors in the logic cells  10  are selected from a group consisting of planar transistors, fin field effect transistors (FinFETs), vertical gate all around (GAA), horizontal GAA, nano wire, nano sheet, or a combination thereof. 
       FIG. 2  shows a simplified diagram illustrating a row in the cell array  100  of  FIG. 1  according to some embodiments of the invention. The logic cells  10 _ 1 ,  10 _ 2  and  10 _ 3  are arranged in the same row and between a power line  20  (e.g., VDD line or a first power supply line) and a ground line  30  (e.g., VSS line or a second power supply line). Furthermore, the outer boundary of each of the logic cells  10 _ 1 ,  10 _ 2  and  10 _ 3  is illustrated using dashed lines. The logic cells  10 _ 1 ,  10 _ 2  and  10 _ 3  have the same cell height H 1 . In the cell array  100  of  FIG. 1 , the logic cells  10  in the same row are electrically isolated from each other by the isolation structures (or region). In other words, the active region of each logic cell  10  is separated from the active region of the adjacent logic cell  10  by the isolation structures. In some embodiments, the isolation structure may be the diffusion break (DB) structure. In some embodiment, the isolation structure may be the shallow trench isolation (STI). In some embodiments, the isolation structure may be the dielectric-base dummy gate. Compared with the continuous diffusion logic cell, the logic cells  10 _ 1 ,  10 _ 2  and  10 _ 3  have smaller cell area (e.g., reducing the area by 10%) due to the smaller cell height and the narrower power/ground line. 
     In the logic cell  10 _ 1 , the gate structures  210 _ 1  and  210 _ 2  extending in the Y-direction forms the P-type transistors P 11  and P 12  in the active region  110 _ 1  of the N-type well region NW and N-type transistors N 11  and N 12  in the active region  120 _ 1  of the P-type well region PW. In the logic cell  10 _ 2 , the gate structures  210 _ 3  through  210 _ 6  extending in the Y-direction forms the P-type transistors P 21  through P 24  in the active region  110 _ 2  of the N-type well region NW and N-type transistors N 21  through N 24  in the active region  120 _ 2  of the P-type well region PW. In the logic cell  10 _ 3 , the gate structures  210 _ 7  and  210 _ 8  extending in the Y-direction forms the P-type transistors P 31  and P 32  in the active region  110 _ 3  of the N-type well region NW and N-type transistors N 31  and N 32  in the active region  120 _ 3  of the P-type well region PW. In order to simplify the description, detail of the gate structures  210 _ 1  through  210 _ 8 , such as the gate dielectric, the gate electrode and so on, and corresponding source/drain regions, will be omitted. 
     The P-type transistors P 11  and P 12  and the N-type transistors N 11  and N 12  are configured to perform a first logic function for the logic cell  10 _ 1 . The P-type transistors P 21  through P 24  and the N-type transistors N 21  through N 24  are configured to perform a second logic function for the logic cell  10 _ 2 . The P-type transistors P 31  and P 32  and the N-type transistors N 31  and N 32  are configured to perform a third logic function for the logic cell  10 _ 3 . In some embodiments, the first, second and third logic functions are different. For example, the logic cell  10 _ 1  is an inverter (NOT gate), the logic cell  10 _ 2  is a NAND gate, and the logic cell  10 _ 3  is an NOR gate. In some embodiments, the first, second and third logic functions are the same. For example, the logic cells  10 _ 1 ,  10 _ 2  and  10 _ 3  are inverters with different driving strengths. 
     In  FIG. 2 , the isolation structures  215 _ 1  and  215 _ 2  are arranged in the boundary of the logic cell  10 _ 1 , the isolation structures  215 _ 2  and  215 _ 3  are arranged in the boundary of the logic cell  10 _ 2 , and the isolation structures  215 _ 3  and  215 _ 4  are arranged in the boundary of the logic cell  10 _ 3 . In other words, the active regions  110 _ 1  and  120 _ 1  of the logic cell  10 _ 1  are separated from the active regions  110 _ 2  and  120 _ 2  of logic cell  10 _ 2  by the isolation structure  215 _ 2 . Furthermore, the active regions  110 _ 2  and  120 _ 2  of logic cell  10 _ 2  are separated from the active regions  110 _ 3  and  120 _ 3  of logic cell  10 _ 2  by the isolation structure  215 _ 3 . 
     In the logic cells  10 _ 1  through  10 _ 3 , the gate structures are arranged between the isolation structures with a fixed pitch PH. For example, the gate structures  210 _ 3  through  210 _ 6  are arranged in sequence from the isolation structure  215 _ 2  to the isolation structure  215 _ 3  according to the pitch PH. Furthermore, the pitch between the isolation structure  215 _ 2  and the gate structure  210 _ 2  is equal to the isolation structure  215 _ 2  and the gate structure  210 _ 3 , i.e., the pitch PH. 
     In some embodiments, the gate structures  210 _ 1  through  210 _ 8  and the isolation structures  215 _ 1  through  215 _ 4  have the same length (e.g., H 1 ) in the Y-direction. In some embodiments, the gate structures  210 _ 1  through  210 _ 8  and the isolation structures  215 _ 1  through  215 _ 4  have the same width in the X-direction. Moreover, the gate structures  210 _ 1  through  210 _ 8  and the isolation structures  215 _ 1  through  215 _ 4  are formed under and partially covered by the power line  20  and the ground line  30 . 
     In some embodiments, each of the gate structures  210 _ 1  through  210 _ 8  may be the continuous poly, and each of the isolation structures  215 _ 1  through  215 _ 4  may be the continuous poly on diffusion edge. 
       FIG. 3A  shows a simplified diagram illustrating a logic cell  10 A according to some embodiments of the invention. The logic cell  10 A is capable of providing a specific logic function with small cell delay. The logic cell  10 A is arranged between the power line  20  and the ground line  30 , and has a cell height H 1 . Furthermore, the outer boundary of the logic cell  10 A is illustrated using dashed lines. 
     In the logic cell  10 A, the gate structures  210   a  through  210   d  extending in the Y-direction forms the P-type transistors P 1  through P 4  in the active region  110  of the N-type well region NW. Moreover, the gate structures  210   a  through  210   d  forms N-type transistors N 1  through N 4  in the active region  120  of the P-type well region PW. The P-type transistors P 1  through P 4  and the N-type transistors N 1  through N 4  are configured to perform the specific logic function for the logic cell  10 A. 
     Compared with the logic cells  10 _ 1 ,  10 _ 2  and  10 _ 3  of  FIG. 2 , the logic cell  10 A further includes the tie-gate transistors T 1  and T 2 . Each of the tie-gate transistors T 1  and T 2  is a dummy P-type transistor that has the source region and drain region both coupled to its gate. The gate structures  210   e  and  210   f  extending in the Y-direction form the tie-gate transistors T 1  and T 2  in the active region  110  of the N-type well region NW. It should be noted that the gate structures  210   e  and  210   f  only extends above the N-type well region NW, and does not extend above the P-type well region PW. Therefore, the gate structures  210   e  and  210   f  are shorter than the gate structures  210   a  through  210   d.    
     In  FIG. 3A , the connection features  220   a  through  220   g  extending in the Y-direction are positioned over the active region  110 . The connection features  220   a  through  220   g  are formed in the same layer over the active region  110 . In some embodiments, each of the connection features  220   a  through  220   g  is a contact for connecting the source/drain region of the transistor. Furthermore, the connection features  230   a  through  230   f  are positioned in the logic cell  10 A. The connection features  230   a  through  230   f  are formed over the connection features  220   a  through  220   g . In some embodiments, each of the connection features  230   a  through  230   f  is a via for connecting the corresponding contact. Moreover, the connection features  235   a  and  235   b  are positioned in the logic cell  10 A. The connection features  235   a  and  235   b  and the connection features  230   a  through  230   f  are formed in the same layer. In some embodiments, each of the connection features  235   a  and  235   b  is a via for connecting the corresponding gate structure. Furthermore, the materials of the connection features  235   a  and  235   b , the connection features  230   a  through  230   f  and the connection features  220   a  through  220   g  are selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, Ni, W, Al, Cu, or a combination thereof. In some embodiments, the connection features  235   a  and  235   b , the connection features  230   a  through  230   f  and the connection features  220   a  through  220   g  are formed by the same material. In some embodiments, the connection features  235   a  and  235   b , the connection features  230   a  through  230   f  and the connection features  220   a  through  220   g  are formed by different materials. 
     The isolation structures  215   a  and  215   b  extending in the Y-direction are arranged in the boundary of the logic cell  10 A. The gate structures  210   a  through  210   d  are surrounded (or sandwiched) by the isolation structures  215   a  and  215   b . The gate structure  210   e  is disposed (or inserted) between the isolation structure  215   a  and the gate structure  210   a , and the gate structure  210   f  is disposed (or inserted) between the isolation structure  215   b  and the gate structure  210   d.    
     In the logic cell  10 A, the gate structures  210   a  through  210   f  are arranged between the isolation structures  215   a  and  215   b  with a fixed pitch PH. For example, the gate structures  210   e ,  210   a  through  210   d  and  210   f  are arranged in sequence from the isolation structure  215   a  to the isolation structure  215   b  according to the pitch PH. 
     The active regions  110  and  120  of the logic unit  10 A are defined by the isolation structures  215   a  and  215   b  along the X-direction. For example, the isolation structure  215   a  is disposed on the left edges of the active regions  110  and  120 , and the isolation structure  215   b  is disposed on the right edges of the active regions  110  and  120 . In other words, the isolation structures  215   a  and  215   b  are arranged on the opposite edges of the active regions  110  and  120 . By inserting the gate structure  210   e  (i.e., the tie-gate transistor T 1 ), the gate structure  210   a  (i.e., the P-type transistor P 1 ) is far away from the left edge of the active region  110 . Therefore, it is avoided that the diffusion break stress at the left edge of the active region  110  will degrade the saturation drain current (Idsat) of the P-type transistor P 1 , especially the P-type transistor with SiGe channel. Moreover, by inserting the gate structure  210   f  (i.e., the tie-gate transistor T 2 ), the gate structure  210   d  (i.e., the P-type transistor P 4 ) is far away from the right edge of the active region  110 . Therefore, it is avoided that the diffusion break stress at the right edge of the active region  110  will degrade the saturation drain current (Idsat) of the P-type transistor P 4 , especially the P-type transistor with SiGe channel. 
     In the logic cell  10 A, a dielectric-base gate structure  217   a  extending in the Y-direction is disposed between the gate structure  210   a  and the isolation structure  215   a  and over the active region  120 . Moreover, a dielectric-base gate structure  217   b  extending in the Y-direction is disposed between the gate structure  210   d  and the isolation structure  215   b  and over the active region  120 . It should be noted that the dielectric-base gate structures  217   a  and  217   b  only extends above the P-type well region PW, and does not extend above the N-type well region NW. Therefore, the dielectric-base gate structures  217   a  and  217   b  are shorter than the gate structures  210   a  through  210   d . In some embodiments, the dielectric-base gate structures  217   a  and  217   b  and the gate structures  210   e  and  210   f  have the same length. 
     In some embodiments, on the interface between the N-type well region NW and the P-type well region PW, the dielectric-base gate structures  217   a  and  217   b  are formed by performing a cut metal gate (CMG) process or a cut poly (CPO) process on the gate structures  210   e  and  210   f  that have the same length as the gate structures  210   a  through  210   d . Next, the gate features of the gate structures  210   e  and  210   f  over the P-type well region are replaced with the dielectric-base material. 
       FIG. 3B  shows a cross-sectional view of the semiconductor structure of the logic cell  10 A along line A-AA in  FIG. 3A  according to some embodiments of the invention. Referring to  FIGS. 3A and 3B  together, the N-type well region NW is formed over a substrate (not shown). In some embodiments, the substrate is a Si substrate. In some embodiments, the material of the substrate is selected from a group consisting of bulk-Si, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-VI material, or a combination thereof. In some embodiments, the N-type well region NW is an N-type substrate. A semiconductor fin  200   a  is formed on the N-type well region NW. Furthermore, the isolation structures  215   a  and  215   b  are arranged upon the left edge and right edge of the semiconductor fin  200   a.    
     The connection feature  220   a  is formed between the isolation structure  215   a  and the gate structure  210   e , and the source region  205   a  of the tie-gate transistor T 1  is coupled to the power line  20  through the connection feature  220   a  and the connection feature  230   a . The connection feature  220   b  is formed between the gate structures  210   e  and  210   a , and the common source/drain region  205   b  of the tie-gate transistor T 1  and the P-type transistor P 1  is coupled to the power line  20  through the connection feature  220   b  and the connection feature  230   b . The connection feature  220   c  is formed between the gate structures  210   a  and  210   b , and the common source/drain region  205   c  of the P-type transistors P 1  and P 2  is coupled to the interconnect structure (not shown) through the connection feature  220   c.    
     The connection feature  220   g  is formed between the isolation structure  215   b  and the gate structure  210   f , and the source region  205   g  of the tie-gate transistor T 2  is coupled to the power line  20  through the connection feature  220   g  and the connection feature  230   e . The connection feature  220   f  is formed between the gate structures  210   d  and  210   f , and the common source/drain region  205   f  of the tie-gate transistor T 2  and the P-type transistor P 4  is coupled to the power line  20  through the connection feature  220   f  and the connection feature  230   d . The connection feature  220   e  is formed between the gate structures  210   c  and  210   d , and the common source/drain region  205   e  of the P-type transistors P 3  and P 4  is coupled to the interconnect structure (not shown) through the connection feature  220   e.    
     The connection feature  220   d  is formed between the gate structures  210   b  and  210   c , and the common source/drain region  205   d  of the P-type transistors P 2  and P 3  is coupled to the power line  20  through the connection feature  220   d  and the connection feature  230   c . Furthermore, the connection feature  220   d  is further coupled to the metal line  240  extending in the X-direction through the connection feature  230   f  The metal line  240  is coupled to the gate structures  210   e  and  210   f  through the connection feature  235   a  and  235   b , respectively. In some embodiments, the metal line  240 , the power line  20  and the ground line  30  are formed in the same metal line. 
     For the tie-gate transistor T 1 , the source region  205   a  is coupled to the power line  20  through the connection features  220   a  and  230   a . Moreover, the drain region  205   b  is coupled to the power line  20  through the connection features  220   b  and  230   b . Furthermore, the gate structure  210   e  is coupled to the power line  20  through the metal line  240  and the connection features  220   d ,  230   c ,  230   f  and  235   a . Similarly, for the tie-gate transistor T 2 , the source region  205   g  is coupled to the power line  20  through the connection features  220   g  and  230   e . Moreover, the drain region  205   f  is coupled to the power line  20  through the connection features  220   f  and  230   d . Furthermore, the gate structure  210   f  is coupled to the power line  20  through the metal line  240  and the connection features  220   d ,  230   c ,  230   f  and  235   b . Thus, the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through a first-type of interconnect structure formed by the metal line  240  and the corresponding connection features (e.g.,  235   a ,  235   b  and  230   f ). In other words, the tie-gate transistors T 1  and T 2  cannot provide the specific logic function for the logic unit  10 A. 
       FIG. 3C  shows a cross-sectional view of the semiconductor structure of the logic cell  10 A along line B-BB in  FIG. 3A  according to some embodiments of the invention. Referring to  FIGS. 3A and 3C  together, a semiconductor fin  200   b  is formed on the P-type well region PW. Furthermore, the isolation structures  215   a  and  215   b  are arranged upon the left edge and right edge of the semiconductor fin  200   b . In order to simplify the description, the connection features for connecting the source/drain regions of the N-type transistors N 1  through N 4  are omitted. 
     In  FIG. 3C , the dielectric-base dummy gate  217   a  is formed between the gate structure  210   a  and the isolation structure  215   a , and the dielectric-base dummy gate  217   b  is formed between the gate structure  210   d  and the isolation structure  215   b . The lower surfaces of the isolation structures  215   a  and  215   b  are lower than the lower surfaces of the dielectric-base dummy gates  217   a  and  217   b . Furthermore, the depth of the isolation structures  215   a  and  215   b  is greater than that of the dielectric-base dummy gates  217   a  and  217   b . In some embodiments, the upper surfaces of the dielectric-base dummy gates  217   a  and  217   b  are level with the upper surfaces of the isolation structures  215   a  and  215   b . In some embodiments, the isolation structures  215   a  and  215   b  are formed by the STI, and the upper surfaces of the isolation structures  215   a  and  215   b  are level with the lower surfaces of the dielectric-base dummy gates  217   a  and  217   b.    
       FIG. 4  shows a simplified diagram illustrating a logic cell  10 B according to some embodiments of the invention. The outer boundary of the logic cell  10 B is illustrated using dashed lines. The semiconductor structure of the logic cell  10 B is similar to the semiconductor structure of the logic cell  10 A of  FIG. 3A , and the differences between  FIG. 4  and  FIG. 3A  is that the logic cell  10 B includes more tie-gate transistors T 1 _ 1  through T 1 _ 3  and more tie-gate transistors T 2 _ 1  through T 2 _ 3 . In order to simplify the description, the connection features for connecting the source/drain regions of the transistors are omitted. 
     In  FIG. 4 , the gate structures  210   e _ 1  through  210   e _ 3  are disposed between the gate structure  210   a  and the isolation structure  215   a  over the active region  110 , and the gate structures  210   f _ 1  through  210   f _ 3  are disposed between the gate structure  210   d  and the isolation structure  215   b  over the active region  110 . Furthermore, the dielectric-base gate structures  217   a _ 1  through  217   a _ 3  are disposed between the gate structure  210   a  and the isolation structure  215   a  over the active region  120 , and the dielectric-base gate structures  217   b _ 1  through  217   b _ 3  are disposed between the gate structure  210   d  and the isolation structure  215   b  over the active region  120 . Moreover, the extended metal line  240  is coupled to the gate structures  210   e _ 1  through  210   e _ 3  and  210   f _ 1  through  210   f _ 1  via the connection feature  235   a _ 1  through  235   a _ 3  and  235   b _ 1  through  235   b _ 3 , respectively. 
     It should be noted that the number of gate structures  210   e _ 1  through  210   e _ 3  and  210   f _ 1  through  210   f _ 3  and the corresponding dielectric-base gate structures  217   a _ 1  through  217   a _ 3  and  217   b _ 1  through  217   b _ 3  are used as an example, and not to limit the disclosure. In some embodiments, the number of gate structures  210   e _ 1  through  210   e _ 3  or  210   f _ 1  through  210   f _ 3  is greater than the number of gate structures  210   a  through  210   d . In some embodiments, the number of gate structures  210   e _ 1  through  210   e _ 3  or  210   f _ 1  through  210   f _ 3  is equal to the number of gate structures  210   a  through  210   d . In some embodiments, the number of gate structures  210   e _ 1  through  210   e _ 3  or  210   f _ 1  through  210   f _ 3  is lower than the number of gate structures  210   a  through  210   d.    
     The logic cell  10 B is capable of providing the specific logic function of the logic cell  10 A with smaller cell delay since the distance between the P-type transistor P 1  and the isolation structure  215   a  and the distance between the P-type transistor P 4  and the isolation structure  215   b  are increased. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active region  110  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 A, especially the P-type transistors P 1  and P 4 . 
       FIG. 5  shows a diagram illustrating the relationship between cell delay and diffusion edge extension according to some embodiments of the invention. By inserting more tie-gate transistors, the cell delay (e.g., delay time from input terminal to output terminal) of the logic cell is decreased when the diffusion edge extension is increased (i.e., the gate structures of the tie-gate transistors are increased). 
       FIG. 6  shows a simplified diagram illustrating a logic cell  10 C according to some embodiments of the invention. The outer boundary of the logic cell  10 C is illustrated using dashed lines. The semiconductor structure of the logic cell  10 C is similar to the semiconductor structure of the logic cell  10 A of  FIG. 3A , and the differences between  FIG. 6  and  FIG. 3A  is that the logic cell  10 C further includes the tie-gate transistors T 3  and T 4  over the active region  120 . In order to simplify the description, the connection features for connecting the source/drain regions of the transistors are omitted. 
     In  FIG. 6 , the gate structure  210   g  is disposed between the gate structure  210   a  and the isolation structure  215   a  and the gate structure  210   h  is disposed between the gate structure  210   d  and the isolation structure  215   b  over the active region  120 . In other words, no dielectric-base gate structure is disposed in the logic cell  10 C. Furthermore, the metal line  242  is coupled to the gate structures  210   g  and  210   h  via the connection feature  235   c  and  235   d , respectively. Similarly, the metal line  242  is further coupled to the ground line  30  through the connection feature  230   g  and the corresponding connection feature (not shown), such as the contact of the common source/drain region of the N-type transistors N 2  and N 3 . Furthermore, the source regions and the drain regions of the tie-gate transistors T 3  and T 4  are coupled to the ground line  30  through the corresponding features (not shown). Thus, each of the tie-gate transistors T 3  and T 4  form a dummy N-type transistor that has the source region and drain region both coupled to its gate. 
     The logic cell  10 C is capable of providing the specific logic function of the logic cell  10 A with smaller cell delay since more tie-gate transistors (e.g., the transistors T 3  and T 4 ) are used. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active regions  110  and  120  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 C, especially the P-type transistors P 1  and P 4  and the N-type transistors N 1  and N 4 . 
       FIG. 7A  shows a simplified diagram illustrating a logic cell  10 D according to some embodiments of the invention. The outer boundary of the logic cell  10 D is illustrated using dashed lines. The logic cell  10 D is capable of providing a the specific logic function similar to that of the logic cell  10 A of  FIG. 3A . The semiconductor structure of the logic cell  10 D is similar to the semiconductor structure of the logic cell  10 A of  FIG. 3A , and the differences between  FIG. 7A  and  FIG. 3A  is that the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through a second-type of interconnect structures. In order to simplify the description, the connection features for connecting the source/drain regions of the transistors are omitted. 
       FIG. 7B  shows a cross-sectional view of the semiconductor structure of the logic cell  10 D along line C-CC in  FIG. 7A  according to some embodiments of the invention. Referring to  FIGS. 7A and 7B  together, the gate structure  210   e  of the tie-gate transistor T 1  is coupled to the metal line  240   a  extending in the X-direction through the connection feature  235   a , and the metal line  240   a  is further coupled to the metal line  320   a  extending in the Y-direction through the connection feature  310   a . Furthermore, the gate structure  210   f  of the tie-gate transistor T 2  is coupled to the metal line  240   b  extending in the X-direction through the connection feature  235   b , and the metal line  240   b  is further coupled to the metal line  320   b  extending in the Y-direction through the connection feature  310   c . The metal lines  240   a  and  240   b  are formed in a first metal layer, and the metal lines  320   a  and  320   b  are formed in a second metal layer over the first metal layer. Furthermore, the metal line  240   a  is separated from the metal line  240   b . Moreover, the length of the metal lines  240   a  and  240   b  is less than twice the pitch PH. 
       FIG. 7C  shows a cross-sectional view of the semiconductor structure of the logic cell  10 D along line D-DD in  FIG. 7A  according to some embodiments of the invention. Referring to  FIGS. 7A and 7C  together, the source region  205   a  of the tie-gate transistor T 1  is coupled to the metal line  244   a  extending in the X-direction through the connection features  220   a  and  230   j , and the drain region  205   b  of the tie-gate transistor T 1  is coupled to the metal line  244   a  through the connection features  220   b  and  230   h . Moreover, the source region  205   g  of the tie-gate transistor T 2  is coupled to the metal line  244   b  extending in the X-direction through the connection features  220   g  and  230   k , and the drain region  205   f  of the tie-gate transistor T 2  is coupled to the metal line  244   b  through the connection features  220   f  and  230   i.    
     In the logic cell  10 D, the metal line  244   a  is further coupled to the metal line  320   a  through the connection feature  310   b , and the metal line  244   b  is further coupled to the metal line  320   b  through the connection feature  310   d . Thus, the drain, gate and source regions of the tie-gate transistor T 1  are coupled to the power line  20  through the second-type of interconnect structure  50 D_ 1  formed by the metal lines  240   a ,  320   a  and  244   a  and the corresponding connection features. Moreover, the drain, gate and source regions of the tie-gate transistor T 2  are coupled to the power line  20  through the second-type of interconnect structure  50 D_ 2  formed by the metal lines  240   b ,  320   b  and  244   b  and the corresponding connection features. In some embodiments, the second-type of interconnect structures  50 D_ 1  and  50 D_ 2  are mirrored in the Y-direction in layout. 
       FIG. 8  shows a simplified diagram illustrating a logic cell  10 E according to some embodiments of the invention. The outer boundary of the logic cell  10 E is illustrated using dashed lines. The semiconductor structure of the logic cell  10 E is similar to the semiconductor structure of the logic cell  10 D of  FIG. 7A , and the differences between  FIG. 8  and  FIG. 7A  is that the logic cell  10 E includes more tie-gate transistors T 1 _ 1  through T 1 _ 3  and more tie-gate transistors T 2 _ 1  through T 2 _ 3 . 
     In  FIG. 8 , the extended metal line  240   a  is coupled to the gate structures  210   e _ 1  through  210   e _ 3  via the connection feature  235   a _ 1  through  235   a _ 3 , respectively. The extended metal line  240   b  is coupled to the gate structures  210   f _ 1  through  210   f _ 3  of the tie-gate transistors T 2 _ 1  through T 2 _ 3  via the connection feature  235   b _ 1  through  235   b _ 3 , respectively. Furthermore, the extended metal line  244   a  is coupled to the source/drain regions of the tie-gate transistors T 1 _ 1  through T 1 _ 3  via the connection feature  230   j _ 1  through  230   j _ 3  and  230   h . The extended metal line  244   b  is coupled to the source/drain regions of the tie-gate transistors T 2 _ 1  through T 2 _ 3  via the connection feature  230   k _ 1  through  230   k _ 3  and  230   i.    
     The logic cell  10 E is capable of providing the specific logic function of the logic cell  10 D with small cell delay since the distance between the P-type transistor P 1  and the isolation structure  215   a  and the distance between the P-type transistor P 4  and the isolation structure  215   b  are increased. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active region- 110  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 E, especially the P-type transistors P 1  and P 4 . 
       FIG. 9  shows a simplified diagram illustrating a logic cell  10 F according to some embodiments of the invention. The outer boundary of the logic cell  10 F is illustrated using dashed lines. The semiconductor structure of the logic cell  10 F is similar to the semiconductor structure of the logic cell  10 D of  FIG. 7A , and the differences between  FIG. 9  and  FIG. 7A  is that the logic cell  10 F further includes the tie-gate transistors T 3  and T 4  over the active region  120 . 
     In  FIG. 9 , the drain, gate and source regions of the tie-gate transistor T 3  are coupled to the ground line  30  through the second-type of interconnect structure  50 D_ 3 . Moreover, the drain, gate and source regions of the tie-gate transistor T 4  are coupled to the ground line  30  through the second-type of interconnect structure  50 D_ 4 . Thus, each of the tie-gate transistors T 3  and T 4  form a dummy N-type transistor that has the source region and drain region both coupled to its gate. In some embodiments, the second-type of interconnect structures  50 D_ 1  and  50 D_ 3  are mirrored in the X-direction, and the second-type of interconnect structures  50 D_ 2  and  50 D_ 4  are mirrored in the X-direction. 
     The logic cell  10 F is capable of providing the specific logic function of the logic cell  10 D with small cell delay since more tie-gate transistors (e.g., the transistors T 3  and T 4 ) are used. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active regions  110  and  120  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 F, especially the P-type transistors P 1  and P 4  and the N-type transistors N 1  and N 4 . 
       FIG. 10A  shows a simplified diagram illustrating a logic cell  10 G according to some embodiments of the invention. The outer boundary of the logic cell  10 G is illustrated using dashed lines. The logic cell  10 G is capable of providing a specific logic function similar to that of the logic cell  10 A of  FIG. 3A . The semiconductor structure of the logic cell  10 G is similar to the semiconductor structure of the logic cell  10 A of  FIG. 3A , and the differences between  FIG. 10A  and  FIG. 3A  is that the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through a third-type of interconnect structures. In order to simplify the description, the connection features for connecting the source/drain regions of the transistors are omitted. 
       FIG. 10B  shows a cross-sectional view of the semiconductor structure of the logic cell  10 G along line E-EE in  FIG. 10A  according to some embodiments of the invention. Referring to  FIGS. 10A and 10B  together, the gate structure  210   e  of the tie-gate transistor T 1  is coupled to the metal line  240   a  through the connection feature  235   a , and the gate structure  210   f  of the tie-gate transistor T 2  is coupled to the metal line  240   b  through the connection feature  235   b . The metal line  240   a  extends in the X-direction between the isolation structure  215   a  and the gate structure  210   a , and the metal line  240   b  extends in the X-direction between the isolation structure  215   b  and the gate structure  210   d . The source region  205   a  of the tie-gate transistor T 1  is coupled to the metal line  240   a  through the connection features  220   a  and  230   j , and the drain region  205   b  of the tie-gate transistor T 1  is coupled to the metal line  240   a  through the connection features  220   b  and  230   h . Moreover, the source region  205   g  of the tie-gate transistor T 2  is coupled to the metal line  240   b  through the connection features  220   g  and  230   k , and the drain region  205   f  of the tie-gate transistor T 2  is coupled to the metal line  240   b  through the connection features  220   f  and  230   i . Thus, the drain, gate and source regions of the tie-gate transistor T 1  are coupled to the power line  20  through the third-type of interconnect structure  50 G  1  formed by the metal line  240   a  and the corresponding connection features. The drain, gate and source regions of the tie-gate transistor T 2  are coupled to the power line  20  through the third-type of interconnect structure  50 G_ 2  formed by the metal line  240   b  and the corresponding connection features. 
     In some embodiments, the third-type of interconnect structures  50 G  1  and  50 G_ 2  are mirrored in the Y-direction. In some embodiments, the space between the connection features  230   b ,  230   j ,  230   i  and  230   k  and the connection features  235   a  and  235   b  are determined according to the process rules. 
       FIG. 11  shows a simplified diagram illustrating a logic cell  10 H according to some embodiments of the invention. The outer boundary of the logic cell  10 H is illustrated using dashed lines. The semiconductor structure of the logic cell  10 H is similar to the semiconductor structure of the logic cell  10 G of  FIG. 10A , and the differences between  FIG. 11  and  FIG. 10A  is that the logic cell  10 H includes more tie-gate transistors T 1 _ 1  through T 1 _ 3  and more tie-gate transistors T 2 _ 1  through T 2 _ 3 . 
     In  FIG. 11 , the extended metal line  240   a  is coupled to the gate structures  210   e _ 1  through  210   e _ 3  via the connection feature  235   a _ 1  through  235   a _ 3 , respectively. The extended metal line  240   b  is coupled to the gate structures  210   f _ 1  through  210   f _ 3  of the tie-gate transistors T 2 _ 1  through T 2 _ 3  via the connection feature  235   b _ 1  through  235   b _ 3 , respectively. Furthermore, the extended metal line  240   a  is further coupled to the source/drain regions of the tie-gate transistors T 1 _ 1  through T 1 _ 3  via the connection feature  230   j _ 1  through  230   j _ 3  and  230   h . The extended metal line  240   b  is further coupled to the source/drain regions of the tie-gate transistors T 2 _ 1  through T 2 _ 3  via the connection feature  230   k _ 1  through  230   k _ 3  and  230   i.    
     The logic cell  10 H is capable of providing the specific logic function of the logic cell  10 G with smaller cell delay since the distance between the P-type transistor P 1  and the isolation structure  215   a  and the distance between the P-type transistor P 4  and the isolation structure  215   b  are increased. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active region- 110  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 H, especially the P-type transistors P 1  and P 4 . 
       FIG. 12  shows a simplified diagram illustrating a logic cell  10 I according to some embodiments of the invention. The outer boundary of the logic cell  10 I is illustrated using dashed lines. The semiconductor structure of the logic cell  10 I is similar to the semiconductor structure of the logic cell  10 G of  FIG. 10A , and the differences between  FIG. 12  and  FIG. 10A  is that the logic cell  10 I further includes the tie-gate transistors T 3  and T 4  over the active region  120 . 
     In  FIG. 12 , the drain, gate and source regions of the tie-gate transistor T 3  are coupled to the ground line  30  through the third-type of interconnect structure  50 G  3 . Moreover, the drain, gate and source regions of the tie-gate transistor T 4  are coupled to the ground line  30  through the third-type of interconnect structure  50 G  4 . Thus, each of the tie-gate transistors T 3  and T 4  form a dummy N-type transistor that has the source region and drain region both coupled to its gate. In some embodiments, the third-type of interconnect structures  50 G  1  and  50 G  3  are mirrored in the X-direction, and the third-type of interconnect structures  50 G_ 2  and  50 G  4  are mirrored in the X-direction. 
     The logic cell  10 I is capable of providing the specific logic function of the logic cell  10 G with smaller cell delay since more tie-gate transistors (e.g., the transistors T 3  and T 4 ) are used. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active regions  110  and  120  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 I, especially the P-type transistors P 1  and P 4  and the N-type transistors N 1  and N 4 . 
       FIG. 13A  shows a simplified diagram illustrating a logic cell  10 J according to some embodiments of the invention. The outer boundary of the logic cell  10 J is illustrated using dashed lines. The logic cell  10 J is capable of providing a specific logic function similar to that of the logic cell  10 A of  FIG. 3A . The semiconductor structure of the logic cell  10 J is similar to the semiconductor structure of the logic cell  10 A of  FIG. 3A , and the differences between  FIG. 13A  and  FIG. 3A  is that the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through the fourth-type of interconnect structures. In order to simplify the description, the connection features for connecting the source/drain regions of the transistors are omitted. 
       FIG. 13B  shows a cross-sectional view of the semiconductor structure of the logic cell  10 J along line F-FF in  FIG. 13A  according to some embodiments of the invention. Referring to  FIGS. 13A and 13B  together, the source region  205   a  of the tie-gate transistor T 1  is coupled to the connection feature  220   a , and the drain region  205   b  of the tie-gate transistor T 1  is coupled to the connection feature  220   b . The gate structure  210   e  of the tie-gate transistor T 1  is coupled to the connection features  220   a  and  220   b  through the connection feature  330   a  extending in the X-direction. Moreover, the source region  205   g  of the tie-gate transistor T 2  is coupled to the connection feature  220   g , and the drain region  205   f  of the tie-gate transistor T 2  is coupled to the connection feature  220   f . The gate structure  210   f  of the tie-gate transistor T 2  is coupled to the connection features  220   f  and  220   g  through the connection feature  330   b  extending in the X-direction. In some embodiments, one or more process steps are used to form the connection feature  330   a  over the connection features  220   a  and  220   b  and the gate structure  210   e  and the connection feature  330   b  over the connection features  220   f  and  220   g  and the gate structure  210   f . Furthermore, the connection feature  330   a  is in contact with the connection features  220   a  and  220   b  and the gate structure  210   e , and the connection feature  330   b  is in contact with the connection features  220   f  and  220   g  and the gate structure  210   f  Thus, the drain, gate and source regions of the tie-gate transistor T 1  are coupled to the power line  20  through the fourth-type of interconnect structure  50 J_ 1  formed by single connection feature  330   a . The drain, gate and source regions of the tie-gate transistor T 2  are coupled to the power line  20  through the fourth-type of interconnect structure  50 J_ 2  formed by single connection feature  330   b . In some embodiments, the fourth-type of interconnect structures  50 J_ 1  and  50 J_ 2  are mirrored in the Y-direction. 
       FIG. 14  shows a simplified diagram illustrating a logic cell  10 K according to some embodiments of the invention. The outer boundary of the logic cell  10 K is illustrated using dashed lines. The semiconductor structure of the logic cell  10 K is similar to the semiconductor structure of the logic cell  10 J of  FIG. 13A , and the differences between  FIG. 14  and  FIG. 13A  is that the logic cell  10 K includes more tie-gate transistors T 1 _ 1  through T 1 _ 3  and more tie-gate transistors T 2 _ 1  through T 2 _ 3 . 
     In  FIG. 14 , the extended connection feature  330   a  is coupled to the gate structures  210   e _ 1  through  210   e _ 3  and the corresponding source/drain regions of the tie-gate transistors T 1 _ 1  through T 1 _ 3 . The extended metal line  330   b  is coupled to the gate structures  210   f _ 1  through  210   f _ 3  and the corresponding source/drain regions of the tie-gate transistors T 2 _ 1  through T 2 _ 3 . 
     The logic cell  10 K is capable of providing the specific logic function of the logic cell  10 G with smaller cell delay since the distance between the P-type transistor P 1  and the isolation structure  215   a  and the distance between the P-type transistor P 4  and the isolation structure  215   b  are increased. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active region- 110  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 K, especially the P-type transistors P 1  and P 4 . 
       FIG. 15  shows a simplified diagram illustrating a logic cell  10 L according to some embodiments of the invention. The outer boundary of the logic cell  10 L is illustrated using dashed lines. The semiconductor structure of the logic cell  10 L is similar to the semiconductor structure of the logic cell  10 J of  FIG. 13A , and the differences between  FIG. 15  and  FIG. 13A  is that the logic cell  10 L further includes the tie-gate transistors T 3  and T 4  over the active region  120 . 
     In  FIG. 15 , the drain, gate and source regions of the tie-gate transistor T 3  are coupled to the ground line  30  through the fourth-type of interconnect structure  50 J_ 3 . Moreover, the drain, gate and source regions of the tie-gate transistor T 4  are coupled to the ground line  30  through the fourth-type of interconnect structure  50 J_ 4 . Thus, each of the tie-gate transistors T 3  and T 4  form a dummy N-type transistor that has the source region and drain region both coupled to its gate. In some embodiments, the fourth-type of interconnect structures  50 J_ 1  and  50 J_ 3  are mirrored in the X-direction, and the fourth-type of interconnect structures  50 J_ 2  and  50 G  4  are mirrored in the X-direction. 
     The logic cell  10 L is capable of providing the specific logic function of the logic cell  10 J with smaller cell delay since more tie-gate transistors (e.g., the transistors T 3  and T 4 ) are used. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active regions  110  and  120  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 L, especially the P-type transistors P 1  and P 4  and the N-type transistors N 1  and N 4 . 
       FIG. 16  shows a simplified diagram illustrating a logic cell  10 M according to some embodiments of the invention. The outer boundary of the logic cell  10 M is illustrated using dashed lines. The logic cell  10 M is capable of providing a specific logic function similar to that of the logic cell  10 A of  FIG. 3A . The semiconductor structure of the logic cell  10 M is similar to the semiconductor structure of the logic cell  10 A of  FIG. 3A , and the differences between  FIG. 16  and  FIG. 3A  is that the gate structures  210   e  and  210   f  are replaced with the gate structures  210   g  and  210   h , respectively. 
     The gate structures  210   g  and  210   h  extending in the Y-direction form the tie-gate transistors T 1  and T 2  in the active region  110  of the N-type well region NW. Moreover, the gate structures  210   g  and  210   h  extending in the Y-direction form the transistors C 1  and C 2  in the active region  120  of the P-type well region PW. It should be noted that the gate structures  210   g  and  210   h  and the gate structures  210   a  through  210   d  have the same length (e.g., equal to the cell height H 1 ). In order to simplify the description, the connection features for connecting the source/drain regions of the transistors are omitted. 
     Compared with the gate structures  210   e  and  210   f  of the logic cell  10 A of  FIG. 3A , the gate structures  210   g  and  210   h  extend in the Y-direction and reach above the P-type well region PW. Thus, the logic cell  10 M further includes the transistors C 1  and C 2 . Each of the transistors C 1  and C 2  is a dummy N-type transistor that has the source region and drain region both coupled to the ground line  30 . Furthermore, the gate structures  210   g  and  210   h  are coupled to the power line  20  through a first-type of interconnect structure formed by the metal line  240  and the corresponding connection features (e.g.,  235   a  and  235   b ). Thus, each of the transistors C 1  and C 2  functions as a capacitor (e.g., a decoupling capacitor or a bypass capacitor) between the power line  20  and the ground line  30 , thereby providing a more stable power supply and decreasing noise for the logic cell  10 M. 
       FIG. 17  shows a simplified diagram illustrating a logic cell  10 N according to some embodiments of the invention. The outer boundary of the logic cell  10 N is illustrated using dashed lines. The semiconductor structure of the logic cell  10 N is similar to the semiconductor structure of the logic cell  10 M of  FIG. 16 , and the differences between  FIG. 17  and  FIG. 16  is that the logic cell  10 N includes more tie-gate transistors T 1 _ 1  through T 1 _ 3  and more tie-gate transistors T 2 _ 1  through T 2 _ 3  and more transistors C 1 _ 1  through C 1 _ 3  and more transistors C 2 _ 1  through C 2 _ 3 . 
     In  FIG. 17 , the gate structures  210   g _ 1  through  210   g _ 3  are disposed between the gate structure  210   a  and the isolation structure  215   a , and the gate structures  210   h _ 1  through  210   h _ 3  are disposed between the gate structure  210   d  and the isolation structure  215   b . Moreover, the extended connection feature  240  is coupled to the gate structures  210   g _ 1  through  210   g _ 3  and  210   h _ 1  through  210   h _ 3  via the corresponding connection feature  235   a _ 1  through  235   a _ 3  and  235   b _ 1  through  235   b _ 3 , respectively. It should be noted that the number of gate structures  210   g _ 1  through  210   g _ 3  and  210   h _ 1  through  210   h _ 3  are used as an example, and not to limit the disclosure. 
     The logic cell  10 N is capable of providing the specific logic function of the logic cell  10 M with smaller cell delay since the distance between the P-type transistor P 1  and the isolation structure  215   a  and the distance between the P-type transistor P 4  and the isolation structure  215   b  are increased. Therefore, it is more avoided that the diffusion break stress at the left and right edges of the active regions  110  and  120  will degrade the saturation drain current (Idsat) of the transistors in the logic cell  10 N, especially the P-type transistors P 1  and P 4  and the N-type transistors N 1  and N 4 . 
       FIG. 18  shows a simplified diagram illustrating a grouping logic cell  10 _GP 1  according to some embodiments of the invention. In  FIG. 18 , the logic cell  10 _ 4  includes the P-type transistor P 41  and the N-type transistor N 41  configured to perform a fourth logic function. The gate structure  210 _ 11  extending in the Y-direction forms the P-type transistor P 41  in the active region  110 _ 4  of the N-type well region NW and N-type transistor N 41  in the active region  120 _ 4  of the P-type well region PW. The logic cell  10 _ 5  includes the P-type transistors P 51  and P 52  and the N-type transistors N 51  and N 52  configured to perform a fifth logic function. The gate structures  210 _ 12  and  210 _ 13  extending in the Y-direction forms the P-type transistors P 51  and P 52  in the active region  110 _ 5  of the N-type well region NW and N-type transistors N 51  and N 52  in the active region  120 _ 5  of the P-type well region PW. In some embodiments, the fourth logic function is the same as the fifth logic function. In some embodiments, the fourth logic function is different from the fifth logic function. 
     In the logic cell  10 _ 4 , the isolation structures  215 _ 5  and  215 _ 6  are formed in the boundary of the logic cell  10 _ 4  to define the active regions  110 _ 4  and  120 _ 4 . In the logic cell  10 _ 5 , the isolation structures  215 _ 7  and  215 _ 8  are formed in the boundary of the logic cell  10 _ 5  to define the active regions  110 _ 5  and  120 _ 5 . The active regions  110 _ 4  and  120 _ 4  are separated from the active regions  110 _ 5  and  120 _ 5 . 
     In  FIG. 18 , the logic cell  10 _ 4  and the logic cell  10 _ 5  are merged into the grouping logic cell  10 _GP 1 . The grouping logic cell  10 _GP 1  is capable of providing the fourth and fifth logic function with smaller cell delay. The grouping logic cell  10 _GP 1  is arranged between the power line  20  and the ground line  30 , and has a cell height H 1 . Furthermore, the outer boundary of the grouping logic cell  10 _GP 1  is illustrated using dashed lines. 
     The grouping logic cell  10 _GP 1  is divided into a first sub-cell GP 1 _ 1  and a second sub-cell GP 1 _ 2 . In the first sub-cell GP 1 _ 1 , the gate structure  210   i  extending in the Y-direction forms the P-type transistor P 5  in the active region  110  and the N-type transistor N 5  in the active region  120 . The P-type transistor P 5  and the N-type transistor N 5  are configured to perform the fourth function. In other words, the first sub-cell GP 1 _ 1  functions as the logic cell  10 _ 4 . In the second sub-cell GP 1 _ 2 , the gate structures  210   k  and  210   l  extending in the Y-direction forms the P-type transistors P 6  and P 7  in the active region  110  and the N-type transistors N 6  and N 7  in the active region  120 . The P-type transistors P 6  and P 7  and the N-type transistors N 6  and N 7  are configured to perform the fifth logic function. In other words, the second sub-cell GP 1 _ 2  functions as the logic cell  10 _ 5 . 
     In the grouping logic cell  10 _GP 1 , the gate structures  210   j  and  210   m  extending in the Y-direction are arranged between the gate structures  210   i  and  210   k . Furthermore, the gate structures  210   j  and  210   m  are disposed at the interface between the first sub-cell GP 1 _ 1  and the second sub-cell GP 1 _ 2 . The gate structures  210   j  and  210   m  are shorter than the gate structures  210   i ,  210   k  and  210   l.    
     The gate structure  210   m  forms the P-type transistor B 1  in the active region  110 , and the gate structure  210   j  forms the N-type transistor B 2  in the active region  120 . In the grouping logic cell  10 _GP 1 , the drain region of the P-type transistor B 1  and the source region of the P-type transistor P 6  share the same common source/drain region, and the source region of the P-type transistor B 1  and the source region of the P-type transistor P 5  share the same common source/drain region. Furthermore, the drain region of the N-type transistor B 2  and the source region of the N-type transistor N 6  share the same common source/drain region, and the source region of the N-type transistor B 2  and the source region of the N-type transistor N 5  share the same common source/drain region. In some embodiments, the source and drain regions of the P-type transistor B 1  are coupled to the power line  20 . In some embodiments, the source and drain regions of the N-type transistor B 2  are coupled to the ground line  30 . As described above, the gate structures  210   i  through  210   l  are arranged between the isolation structures  215   a  and  215   b  with a fixed pitch PH. 
     In some embodiments, the gate structure  210   m  is coupled to the power line  20  through the connection feature  235   e . Thus, the P-type transistor B 1  is a dummy transistor that has the source region and drain region both coupled to its gate, i.e., the P-type transistor B 1  is independent of the fourth and fifth logic function. 
     In some embodiments, the gate structure  210   j  is coupled to the ground line  30  through the connection feature  235   f . Thus, the N-type transistor B 2  is a dummy transistor that has the source region and drain region both coupled to its gate, i.e., the N-type transistor B 2  is independent of the fourth and fifth logic function. 
     The first sub-cell GP 1 _ 1  in the grouping logic cell  10 _GP 1  is capable of providing the fourth logic function of the logic cell  10 _ 4  with smaller cell delay since the distance between the P-type transistor P 5  and the isolation structure  215   b  is increased (compared to the distance between the P-type transistor P 41  and the isolation structure  215 _ 6 ). Similarly, the second sub-cell GP 1 _ 2  in the grouping logic cell  10 _GP 1  is capable of providing the fifth logic function of the logic cell  10 _ 5  with smaller cell delay since the distance between the P-type transistor P 6  and the isolation structure  215   a  is increased (compared to the distance between the P-type transistor P 51  and the isolation structure  215 _ 7 ). It should be noted that the number of sub cells of the grouping logic cell  10 _GP 1  is used as an example, and not to limit the disclosure. 
       FIG. 19  shows a simplified diagram illustrating a grouping logic cell  10 _GP 2  according to some embodiments of the invention. The outer boundary of the grouping logic cell  10 _GP 2  is illustrated using dashed lines. The semiconductor structure of the grouping logic cell  10 _GP 2  is similar to the semiconductor structure of the grouping logic cell  10 _GP 1  of  FIG. 18 , and the differences between  FIG. 19  and  FIG. 18  is that the grouping logic cell  10 _GP 2  further includes the tie-gate transistor T 1  in the first sub-cell GP 2 _ 1  and the tie-gate transistor T 2  in the second sub-cell GP 2 _ 2 . 
     In  FIG. 19 , the gate structure  210   e  extending in the Y-direction form the tie-gate transistor T 1  in the active region  110 , and the gate structure  210   f  extending in the Y-direction form the tie-gate transistor T 2  in the active region  110 . It should be noted that the gate structures  210   e  and  210   f  only extends above the N-type well region NW, and does not extend above the P-type well region PW. Therefore, the gate structures  210   e  and  210   f  are shorter than the gate structures  210   i ,  210   k  and  210   l.    
     Moreover, the dielectric-base gate structure  217   a  extending in the Y-direction is disposed between the gate structure  210   i  and the isolation structure  215   a  and over the active region  120 . Moreover, the dielectric-base gate structure  217   b  extending in the Y-direction is disposed between the gate structure  210   i  and the isolation structure  215   b  and over the active region  120 . It should be noted that the dielectric-base gate structures  217   a  and  217   b  only extends above the P-type well region PW, and does not extend above the N-type well region NW. Therefore, the dielectric-base gate structures  217   a  and  217   b  are shorter than the gate structures  210   i ,  210   k  and  210   l.    
     In  FIG. 19 , the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through a first-type of interconnect structure formed by the metal line  240  and the corresponding connection features (e.g., the connection features  235   a ,  235   b  and  230   f ). In some embodiments, the N-type tie-gate transistors (e.g., the tie-gate transistors T 3  and T 4  of  FIG. 6 ) may be used in the grouping logic cell  10 _GP 2 . In some embodiments, the grouping logic cell  10 _GP 2  further includes the transistors C 1  and C 2  in the active region  120 , as shown in  FIG. 16 . In some embodiments, by inserting more tie-gate transistors (e.g., the tie-gate transistors T 1 _ 1  through T 1 _ 3  and the tie-gate transistors T 2 _ 1  through T 2 _ 3  of  FIG. 4 ) between the gate structure  210   e  and the isolation structure  215   a  and between the gate structure  210   f  and the isolation structure  215   b , the grouping logic cell  10 _GP 2  is capable of providing the fourth and fifth logic function with smaller cell delay. 
     In some embodiments, the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through the second-type of interconnect structure, as shown in  FIGS. 7A, 7B, 8 and 9 . 
     In some embodiments, the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through the third-type of interconnect structure, as shown in  FIGS. 10A, 10B, 11 and 12 . 
     In some embodiments, the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through the fourth-type of interconnect structure, as shown in  FIGS. 13A, 13B, 14 and 15 . 
       FIG. 20  shows a simplified diagram illustrating a grouping logic cell  10 _GP 3  according to some embodiments of the invention. In  FIG. 20 , the logic cell  10 _ 4  and the logic cell  10 _ 5  are merged into the grouping logic cell  10 _GP 3 . The grouping logic cell  10 _GP 3  is capable of providing the fourth and fifth logic function with small cell delay. Furthermore, the outer boundary of the grouping logic cell  10 _GP 3  is illustrated using dashed lines. 
     The grouping logic cell  10 _GP 3  is divided into a first sub-cell GP 3 _ 1  and a second sub-cell GP 3 _ 2 . The first sub-cell GP 3 _ 1  includes the P-type transistor P 5  and the N-type transistor N 5 , and the first sub-cell GP 3 _ 1  functions as the logic cell  10 _ 4 . The second sub-cell GP 3 _ 2  includes the P-type transistors P 6  and P 7  and the N-type transistors N 6  and N 7 , and the second sub-cell GP 3 _ 2  functions as the logic cell  10 _ 5 . 
     The semiconductor structure of the grouping logic cell  10 _GP 3  is similar to the semiconductor structure of the grouping logic cell  10 _GP 1  of  FIG. 18 , and the differences between  FIG. 20  and  FIG. 18  is that the grouping logic cell  10 _GP 3  does not include the gate structure  210   j . The source regions of the P-type transistors P 5  and P 6  share the common source/drain region, and the source regions of the N-type transistors N 5  and N 6  share the common source/drain region. Thus, compared with the grouping logic cell  10 _GP 1  of  FIG. 18 , the grouping logic cell  10 _GP 3  has smaller area. It should be noted that the number of sub cells of the grouping logic cell  10 _GP 3  is used as an example, and not to limit the disclosure. 
       FIG. 21  shows a simplified diagram illustrating a grouping logic cell  10 _GP 4  according to some embodiments of the invention. The outer boundary of the grouping logic cell  10 _GP 4  is illustrated using dashed lines. The semiconductor structure of the grouping logic cell  10 _GP 4  is similar to the semiconductor structure of the grouping logic cell  10 _GP 3  of  FIG. 20 , and the differences between  FIG. 21  and  FIG. 20  is that the grouping logic cell  10 _GP 4  further includes the tie-gate transistor T 1  in the first sub-cell GP 4 _ 1  and the tie-gate transistor T 2  in the second sub-cell GP 4 _ 2 . 
     In  FIG. 21 , the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through a first-type of interconnect structure formed by the metal line  240  and the corresponding connection features (e.g., the connection features  235   a ,  235   b  and  230   f ). In some embodiments, the N-type tie-gate transistors (e.g., the tie-gate transistors T 3  and T 4  of  FIG. 6 ) may be used in the grouping logic cell  10 _GP 4 . In some embodiments, the grouping logic cell  10 _GP 4  further includes the transistors C 1  and C 2  in the active region  120 , as shown in  FIG. 16 . In some embodiments, by inserting more tie-gate transistors (e.g., the tie-gate transistors T 1 _ 1  through T 1 _ 3  and the tie-gate transistors T 2 _ 1  through T 2 _ 3  of  FIG. 4 ) between the gate structure  210   e  and the isolation structure  215   a  and between the gate structure  210   f  and the isolation structure  215   b , the grouping logic cell  10 _GP 4  is capable of providing the fourth and fifth logic function with smaller cell delay. 
     In some embodiments, the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through the second-type of interconnect structure, as shown in  FIGS. 7A, 7B, 8 and 9 . 
     In some embodiments, the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through the third-type of interconnect structure, as shown in  FIGS. 10A, 10B, 11 and 12 . 
     In some embodiments, the drain, gate and source regions of the tie-gate transistors T 1  and T 2  are coupled to the power line  20  through the fourth-type of interconnect structure, as shown in  FIGS. 13A, 13B, 14 and 15 . 
     In the embodiments, the semiconductor structures of logic cells capable of reducing delay time are provided. By inserting the tie-gate transistors at the boundary of the logic cell that require high-speed operation, the diffusion edge is extended for diffusion break stress mitigation. Thus, the saturation drain current (Idsat) of the transistors in the logic cell will not be degraded, and then operation speed of the logic cell is increased. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.