Patent Publication Number: US-8994411-B2

Title: System and method for bootstrapping a switch driver

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application relates to the following co-pending and commonly assigned U.S. patent application Ser. No. 12/956,813, filed on Nov. 30, 2010 entitled “System and Method for Bootstrapping a Switch Driver,” Ser. No. 12/956,852, filed on Nov. 30, 2010 entitled “System and Method for Driving a Switch,” and Ser. No. 12/956,696, filed on Nov. 30, 2010 entitled “System and Method for Driving a Cascode Switch,” which applications are hereby incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to electronic circuits, and more particularly to a system and method for bootstrapping a switch driver. 
     BACKGROUND 
     Power supply systems are pervasive in many electronic applications from computers to automobiles. Generally, voltages within a power supply system are generated by performing a DC-DC, DC-AC, and/or AC-DC conversion by operating a switch loaded with an inductor or transformer. In some power supply systems, combinations of switches are arranged in a bridge configuration such as a half-bridge, full-bridge, or a multi-phase bridge. When very high voltages are generated by the power supply, it is beneficial to use switches, such as junction field effect transistor (JFET) devices, that have both a high breakdown voltage and a low on-resistance. The high breakdown voltage of a JFET allows for reliable operation even with output voltages of hundreds or even over a thousand volts. The low on-resistance of the JFET device allows for efficient operation of the power supply system. 
     JFET devices have the property that they are self-conducting or “normally on devices,” meaning that the devices conduct electricity when the gate-source voltage of the JFET is at about zero volts. Such a property poses difficulties because the switch transistors appear as short circuits before the power supply system is fully biased, thereby causing high currents to be generated at the startup of the power supply. In some high efficiency JFET devices used for power supply switching, this pinch-off voltage may be around negative 15 volts. Therefore, this negative voltage is generated before the power supply begins full operation when the JFET can be fully shut off. 
     In some power supplies, biasing voltages are developed at startup by using transformers. The use of transformers, however, is expensive. In other power supplies, voltages are developed at startup by using bootstrap techniques, in which the energy of switching nodes within the power supply circuit is used to charge capacitors that provide the local power supply for the switching transistors. When JFETs are used, however, such bootstrapping techniques are difficult to apply. For example, when the internal supply voltage of the power supply system is low at startup, the JFET switches may not operate because the voltages required to allow the JFETs to switch on and off has not yet been developed. If the JFET switches do not operate, then the internal supply voltages needed to make the switches operate cannot be generated. 
     SUMMARY OF THE INVENTION 
     In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch. 
     The foregoing has outlined rather broadly the features of an embodiment of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which: 
         FIGS. 1   a - 1   b  illustrate power supply systems according to embodiments of the present invention; 
         FIG. 2  illustrates an embodiment switch driver system. 
         FIGS. 3   a - 3   c  illustrate schematics of an embodiment driver; 
         FIGS. 4   a - 4   c  illustrate a timing diagram and schematics of an embodiment switch control circuit; 
         FIG. 5  illustrates a further embodiment switch driver system; 
         FIG. 6  illustrates an embodiment driver circuit; 
         FIGS. 7   a - 7   b  illustrate embodiment power supply systems using embodiment driver circuits; and 
         FIG. 8  illustrates an embodiment waveform diagram of an embodiment driver circuit. 
     
    
    
     Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. 
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. 
     The present invention will be described with respect to various embodiments in a specific context, namely switch drivers in switched mode power supply systems. Embodiments of the invention may also be applied to switch drivers in other electronic applications such as solar inverters, telecom, servers and uninterruptible power supplies. 
       FIG. 1   a  illustrates power supply system  100  according to an embodiment of the present invention. Input voltage Vin is applied across half-bridge  101  circuit having high-side switch  106  and low-side switch  108 . In an embodiment, each switch  106  and  108  is made of a JFET and a MOSFET coupled in series. Alternatively, other switch configurations can be used. During operation of power supply system, high-side driver  102  drives high-side switch  106  and low-side driver  104  drives low-side switch  108 . In an embodiment, high-side switch  106  and low side switch  108  are driven in an alternate manner such that only one switch is conducting at a particular time. In some embodiments, output voltage Vout is controlled according to the relative duty cycles of the conductive states of high-side switch  106  and low side switch  108 , and according to the turns ratio of transformer T 1 . 
     Output N 1  of half-bridge circuit  101  is coupled to the primary winding of transformer T 1 , the secondary winding of which is coupled to rectifying diodes D 4 A and D 4 B. Rectifying diodes D 4  and D 5  rectifies the output of the secondary winding of transformer T 1 , and capacitor C 5  filters the rectified output of diodes D 4  and D 5 . In an embodiment, voltage Vout is sensed by isolation/controller block  112 , which generates input signals for high-side driver  102  and low-side driver  104 . In an embodiment, isolation/controller provides electrical isolation between the primary and secondary sides of transformer T 1  using, for example, isolation circuits such as optoisolators, transformers, and other isolation devices known in the art. In an embodiment, isolation/controller block can be configured to provide a predetermined output voltage at Vout. 
     In an embodiment, power is provided to high-side driver  102  across terminal G, which is coupled to output N 1  of half-bridge circuit  101 , and terminal P, which is coupled to capacitor C 1  and diode D 1  at node  122 . When node N 1  experiences a positive voltage transition, node  122  is driven high until diode D 1  becomes forward biased at a Vin−V S1 +V DS1 , where V DS1  is the junction voltage of diode D 1  and V S1  is the voltage of power supply  110 . When node N 1  is at voltage Vin, a voltage of about V S1 −V DS  is across capacitor C 1 . When node N 1  begins to experience a negative voltage transition, diode D 1  becomes reversed biased, and a voltage of about V S1 −V DS1  is maintained across capacitor C 1 . In some embodiments, the voltage across capacitor C 1  will decay according to the size of capacitor C 1  and the current consumed by driver  102 . In an embodiment, V S1  is selected to be at least sufficient to shut off the JFET in high-side switch  106 . In embodiments where high-side switch includes a JFET, VS 1  is selected to be at least greater than the magnitude of the pinch-off voltage of the JFET, for example, between about 10 V and about 15 V. In alternative embodiments, other values can be used according to the application, its requirements, and the characteristics of the individual devices used in the circuit. 
     In an embodiment, power is provided to low-side driver  104  across terminal G, which is coupled to system ground  120 , and terminal P, which is coupled to capacitor C 2  and D 3 . When node N 1  experiences a positive voltage transition, node  128  is driven high until diode D 2  becomes forward biased at a Vin−V S1 +V DS2 , where V DS2  is the junction voltage of diode D 2 . When node N 1  is at voltage Vin, a voltage of about V S1 −V DS2  is across capacitor C 3 . When node N 1  begins to experience a negative voltage transition, diode D 2  becomes reversed biased and a voltage of about V S1 −V DS2  is maintained across capacitor C 3 . Node  128  follows node N 1  as it continues its negative voltage excursion. When node N 1  is at system ground  120 , node  128  is at a voltage of approximately VDS 2 −V S1 , and capacitor C 2  charges to a voltage of approximately V DS3 +V DS2 −V S1  if the effect of the discharge of C 2  and capacitive charge sharing between C 2  and C 3  is neglected, where V DS3  is the junction voltage of diode D 3 . In some embodiments, the voltage across capacitor C 2  will decay according to the size of capacitor C 2  and the current consumed by driver  104 . As the voltage decays across C 2 , however, more charge is introduced to capacitor C 2  via diode D 3  so that the voltage across terminals P and G of driver  104  are maintained at a sufficient voltage to operate a JFET within low-side switch  108 . 
     In an embodiment, values for C 1 , C 2  and C 3  are each between about 10 μF and about 100 μF, and VS 1  set to be between about 20V and about 30V. In one embodiment, Vin is about 400V and Vout is about 12V, 48V or 400V. In alternative embodiments, other component and voltage values can be used depending on the specific application and its specifications. 
     It should be appreciated that the circuit illustrated in  FIG. 1   a  is one example of how inventive concepts can be applied to a power supply system. In alternative embodiments, other power supply topologies can be used besides the topology shown in  FIG. 1   a . For example,  FIG. 1   b  illustrates alternative embodiment power supply system  140 , which is similar to power supply system  100  illustrated in  FIG. 1   a , with the exception that capacitor C 3  and diode D 2  are omitted, and diode D 3  is coupled between nodes  125  and  122 . Here, the embodiment of  FIG. 1   b  uses fewer components than the embodiment of  FIG. 1   a.    
     Further embodiments of the present invention can be applied to converters including, but not limited to buck converters, boost converters, and buck-boost converters. Alternative embodiment power supply topologies can also include power supplies using inductors instead of transformers, or topologies using both inductors and transformers. 
       FIG. 2  illustrates a low-side portion of a half-bridge circuit and its associated driving circuits according to another embodiment of the present invention. Here, the low-side switch is made of n-channel JFET  234  and PMOS device  236  and is driven by driver  204 . Alternatively, other device types, such as an NMOS device can be coupled in series with JFET  234  instead of PMOS device  236 . During nominal operation of the power supply system, PMOS device  236  is turned on persistently while JFET  234  is switched on and off, thereby charging capacitor C 2  as described hereinabove with respect to  FIG. 1   a . Switching data is input to driver  204  via signal Data. 
     During startup, PMOS  236  is shut off when node  224  does not have sufficient negative voltage to shut off JFET  234 . By shutting off PMOS  236 , a short circuit is prevented from occurring in the half-bridge circuit during startup. Assuming that node N 1  has a sufficiently high voltage at startup, for example, greater than 20V, and the gate of JFET  234  is coupled to system ground  240  at node  216 , the voltage at node  210  will be the pinch-off voltage of JFET  234 . In one embodiment, this is about 15V, however, in alternative embodiments this voltage will differ according to the device characteristics of JFET  234 . Here, the pinch-off voltage is stored on capacitor C 2 , which provides driver  204  a sufficient voltage to operate the internal logic of driver  204 . In an embodiment, diode D 10  is coupled between the gate of JFET  234  and system ground  240  to prevent the gate of JFET  234  from going significantly higher than system ground  240 . 
     In an embodiment, the driver switches PMOS device on and off along with JFET  234  when the voltage across capacitor C 2  exceeds a first predefined threshold, for example, about 8V. Here both devices are switched on and off together when there is a possibility that JFET  234  cannot be completely turned off while the internal power supply is low. In some embodiments, the driver switches PMOS device on and off along with JFET  234  when the voltage across an internal regulated node exceeds a threshold voltage. As the half-bridge begins to switch on and off, the voltage of node  227  is pumped farther and farther below system ground  240  via capacitors C 3  and diode D 3 . Once the voltage of node  227  is sufficiently below system ground  240 , for example, at about −18V, PMOS device  236  is persistently turned on and operation proceeds in a normal mode of operation. In an embodiment, the supply threshold at which PMOS device  236  is persistently turned on is determined by the pinch-off voltage of the JFET  234  and an additional margin, for example, about 18V, to ensure reliable operation. 
     In some embodiments, switching both JFET  234  and PMOS  236  is not as efficient as keeping PMOS device  236  on and switching JFET  234  because driver  204  needs to charge and discharge the gate capacitance of PMOS device  236 . In some embodiments, PMOS device  236  is made very large in order to reduce the series resistance to JFET  234 ; therefore, the gate-source capacitance of PMOS device  236  can be very high. During startup, however, switching both devices together allows both devices to operate safely without causing a short circuit in some embodiments. Once the full negative power supply voltage is developed at node  227 , however, the persistently on state of PMOS  236  allows more efficient operation because the JFET device has a lower input capacitance per given drive strength than PMOS device  236 . In further embodiments, concepts applied to the low-side driver circuit can also be applied to the high-side driver. 
       FIG. 3   a  illustrates a schematic of an embodiment driver circuit  300 . In an embodiment, driver circuit  300  can be used for the driver blocks in  FIGS. 1 and 2 . In driver circuit  300 , controller  306  drives JFET gate driver  304  and MOSFET gate driver  302 . Controller  306  determines the timing of the drive signals to drivers  302  and  304  according to a mode of operation. For example, in a first mode of operation when the device is starting up, the MOSFET gate is disabled by driving the MOSFET gate to a high potential and switching is also disabled for the JFET gate by driving the JFET gate to a low voltage. In a second mode of operation, while the power supply is charging, both the MOSFET gate and the JFET gates are switched on and off together according to input signal Din. In a third mode of operation corresponding to a case of nominal operation, the MOSFET gate is turned on persistently. In an embodiment, power control block  308  uses input JFS as a positive supply and node P 1  as a negative supply. In some embodiments, power control block  308  has a local voltage regulator and comparators used to determine the mode of operation. In the embodiment shown in  FIG. 3   a , power control block  308  outputs a MODE signal to controller  306 . In some embodiments, the MODE signal can be a digital signal made of one or more bits. In alternative embodiments, power control, mode control, and signal control can be implemented and partitioned differently. 
       FIG. 3   b  illustrates an embodiment schematic of power control block  308 , which has reference voltage generator  322  generating two voltages REF 1  and REF 2 . In an embodiment, REF 1  is about 8V and REF 2  is about 18V, however, in alternative embodiments, different voltages can be used. Comparators  324  and  326  compare voltages REF 1  and REF 2  to node JFS respectively. The results of the comparisons are processed by mode logic block  328 , which outputs the MODE signal representing an operation mode. In alternative embodiments, other circuits can be used. For example, instead of using voltage JFS directly, a scaled down version of JFS can be compared against lower reference voltages. For example, in one embodiment, JFS is scaled down by a factor of 10 via a resistor divider, and compared to 0.8V and 1.8V. In such a low-voltage embodiment, low voltage devices can be used and saturation effects can be prevented. 
       FIG. 3   c  illustrates alternative embodiment power control block  309 . Power control block  309  is similar to power control block  308  of  FIG. 3   b , but also has voltage regulator  330  producing regulated voltage P 2  from which reference voltages REF 1  and REF 2  are derived. In some embodiments, regulated voltage P 2  is used to power the switch drivers and/or other circuitry associated with the switch drivers. In some embodiments, voltage regulator  330  is used to power the switch drivers and associated circuitry, while primary power supply P 1  is used to derive reference voltages REF 1  and REF 2  via block  322  as configured in  FIG. 3   b.    
     In an embodiment, when the gates of the JFET and the MOSFET device are both being switched, for example, the JFET is turned on after the MOSFET device has been turned on, and the MOSFET is turned off after the JFET is turned off. This can happen, for example, in the second mode when the supply is charging after the power supply system has been started. In an embodiment, the MOSFET handles the pinch-off voltage of the JFET, therefore, a low-voltage MOSFET can be used when the JFET is a high voltage device. Accordingly, ensuring that the MOSFET is on when the JFET is on prevents device breakdown and the possible destruction of the MOSFET device.  FIG. 4   a  illustrates a timing diagram of controller  306  and drivers  302  and  304  of  FIG. 3   a  where a PMOS device is being used. Here, the JFET gate is driven high after the PMOS gate drive has gone low at time  402 . Similarly, the PMOS gate is driven high after the JFET gate is driven low at time  404 . In embodiments, where the MOSFET device is implemented using an NMOS device, the sense of signal PMOS GATE is inverted. 
       FIG. 4   b  illustrates a schematic of at least a portion controller  306  according to an embodiment of the present invention. Signal Din drives AND gate  406  directly, and AND gate  408  via inverter  410 . The output of AND gate  406  drives driver/sensor  412  and JFET gate driver  304  ( FIG. 3 ) and the output of AND gate  408  drives driver/sensor  414  and MOSFET driver  302  ( FIG. 3 ). Output C of driver/sensor is fed to AND gate  408  and output C of driver/sensor  414  is fed to AND gate  406 . In an embodiment, node C of driver/sensor  412  JFET does not go low until the JFET gate has gone low. Similarly, node C of driver sensor  414  does not go high until the MOSFET gate has gone low. Effectively, node C goes high if the driver/sensor senses that the associated node at input B has become low. By providing feedback from the actual gate driving nodes, the JFET is prevented from conducting when the MOSFET is turned off. 
       FIG. 4   c  illustrates an embodiment example of driver/sensor block  412  shown in  FIG. 4   b . The driver sensor has PMOS device  428  coupled to input A via inverter  420 . PMOS device is coupled between VDD and input  430  of a latch made of back-to-back inverters  422  and  424 . Gate feedback is also coupled to the latch via NMOS device  421 . In one embodiment, NMOS device  421  is a high voltage device, although NMOS device  421  can also be implemented as a low voltage device. In some embodiments, buffer  434  is coupled between node A and node B. During operation, when the node  432  at the gate of PMOS device  428  is high the input of the latch is driven by input B, which corresponds to the drive signal of the PMOS or JFET drive signal. In some embodiments, PMOS device  428  can be omitted if node B can force input  430  to high state via NMOS device  421 . The existence of PMOS device  428 , however, helps to obtain a clean reset condition. In an embodiment, inverter  424  is made with a weak PMOS and/or NMOS device in order to let devices  421  and  428  override the output of inverter  424 . In some embodiments, inverter  422  is also made with a weak PMOS and/or NMOS device to minimize cross-conduction during switching. In such an embodiment, inverter  422  can be followed by another buffer stage (not shown). 
     It should be appreciated that the circuit shown in  FIGS. 4   b  and  4   c  are example embodiments. In alternative embodiments, other circuits and logic can be used besides the circuit illustrated in  FIG. 4   b.    
       FIG. 5  illustrates another embodiment system  500  for driving half-bridge circuit  501 . A high-side switch made of JFET  506  and PMOS device  508  are driven by high-side driver  502 , and a low-side switch made of JFET  510  and  512  are driven by low-side driver  504 . Operation of drivers  502  and  504  is similar to the operation of driver  204  shown in  FIG. 2 , and drivers  102  and  104  shown in  FIG. 1   a . Each driver, however, has two power supply terminals P 1  and P 2  and each switch has a JFET and a MOSFET. In an embodiment, power supply terminal P 1  is used to supply the driver with a primary supply and power supply terminal P 2  is used to supply the driver with a regulated supply. In an embodiment, the regulated supply is generated from the primary supply with a voltage regulator within block  308  of  FIG. 3   a . In one embodiment, power supply terminal P 2  operates at between about −18V and about −19V, and power supply terminal P 1  operates at between about −24V and −26V. In alternative embodiments, other voltage ranges and/or additional supply terminals can be used. 
     In an embodiment, supply P 1  of high-side driver  502  is supplied via D 1 . Supply P 2  is supplied via an internal regulation circuit and decoupled to node  520  via capacitor C 1 . Similarly, supply P 1  of low-side driver  504  is supplied via C 3  and D 3 . Supply P 2  is supplied via an internal regulation circuit and decoupled to node  522  via capacitor C 2 . In some embodiments, power control block  309  shown in  FIG. 3   c  can be used. Resistors R 1  and R 2  limit the current peaks that otherwise might damage or destroy the diodes, especially at startup. Diodes D 5 , D 6 , D 7  and D 8  are reversed-biased during normal operation, but become forward biased when power supply nodes P 1  and P 2  have a voltage greater than a driver ground node in order to protect driver circuitry from latch-up, breakdown, and over voltage conditions. Diodes D 5 , D 6 , D 7  and D 8  also provide a charging path for capacitors C 1 , C 2 , C 8  and C 9  during startup when no bootstrap voltage is available. 
       FIG. 6  illustrates driver circuit  600  according to an embodiment of the present invention. Driver circuit  600  has low voltage section  601  coupled to high voltage section  603  via coreless transformer  620 . In alternative embodiments, low voltage section  601  can be coupled to high voltage section  603  via an optocoupler. Low voltage section  601  accepts driver data at pin IN, which is coupled to coreless transformer  620  via buffer  622 , input logic  604  and transformer driver  606 . In an embodiment, low voltage section  601  also accepts an enable signal at pin EN, which is coupled to input logic  604  via buffer  624 . Under Voltage Lock Out (UVLO) circuit  602  disables the output of input logic block  604  when power supply VCC 1  is below a minimum operating voltage. In some embodiments VCC 1  is about 5V, however, in alternative embodiments, other supply voltages can be used. In an embodiment, enable signal EN is used to enable operation of driver circuit  600 . In an embodiment, driver circuit  600  is implemented as a plurality of components within a single package, such as a system in package (SIP). In one embodiment, within the package, low voltage section  601  is partitioned on a first integrated circuit (IC), high voltage section  603  is partitioned on a second IC, and coreless transformer  620  is partitioned on the first IC or the second IC. Alternatively, driver circuit  600  can be implemented as an integrated circuit (IC) or within multiple packages. 
     High voltage section  603  has coreless transformer receiver  608 , driver logic  614 , JFET driver  616 , and MOSFET driver  618 . Linear regulator  612  provides regulated voltage VREG from power supply inputs VCC 2  and VEE 2 . In an embodiment, diode  628  and resistor  623  are coupled to input CLJFG to prevent the gate of the driven JFET from attaining a voltage significantly above the drain potential of the driven MOSFET. UVLO circuit  610  provides logic block  614  power supply status so that logic block  614  can derive a supply dependent mode of operation. In an embodiment, bootstrap enable signal BSEN is used to enable embodiment operation modes. In further embodiments, signal BSEN can be omitted. 
       FIG. 7   a  illustrates an embodiment full-bridge power supply  700  using embodiment drivers  702 ,  704 ,  706  and  708 . High-side driver  702  is coupled to JFET  710  and MOSFET  718 , high-side driver  704  is coupled to JFET  712  and MOSFET  720 , low-side driver  706  is coupled to JFET  714  and MOSFET  722 , and low-side driver  708  is coupled to JFET  716  and MOSFET  724 . In an embodiment, power is supplied to a load represented by inductor  750  and/or a load coupled to the terminals of inductor  750 . Transformer  726  charges nodes PM25V and PM25VH to provide a negative supply to terminals VEE 2  on drivers  702 ,  704 ,  706  and  708 . In an embodiment, nodes PM25V and PM25VH are charged to about −25V with respect to primary supply  730  and system ground  752 , respectively. Alternatively, nodes PM25V and PM25VH can be charged to other voltages. In one embodiment, the second mode of operation, in which both the JFET and the MOSFET switch at the same time, is not performed when pins VEE 2  in drivers  706  and  708  receive power at node PM25V. Primary supply  730  operates at about 800V. However, in other embodiments, different voltages can be used. Signals I 1 , I 2 , I 3  and I 4  control the switching of power supply drivers  702 ,  704 ,  706  and  708 . 
       FIG. 7   b  illustrates embodiment full-bridge power supply  701  in which supply pin VEE 2  in low-side drivers  706  and  708  receive power using embodiment bootstrapping methods instead of from a secondary winding of transformer  726  ( FIG. 7   a ). Here, transformer  770  provides power for node PM25VH. An advantage of such an embodiment includes cost savings gained from using a less expensive transformer. 
     In an alternative embodiment, with respect to high side drivers  702  and  704 , if the circuitry between nodes VCC 1  and GND 1  in the drivers can withstand 25V, for example between nodes  730  and PM25VH, and if the positive supply of controller system steering inputs I 1 -I 4  are connected to Vin (node  730 ) then PM25VH can be used as supply for both the high voltage and low voltage circuitry within the drivers. In such an embodiment, a diode is coupled between the supplies. Therefore, a common supply can be used for the controller and the high-side switch driver having a bootstrap diode in between. With respect to low side drivers  706  and  708 , a similar concept can be applied if the controller is referenced to the system ground instead of the high-side reference nodes. In such an embodiment, a diode does not need to be coupled between the supplies. Therefore, a common supply can be used for the controller and low-side switch drivers. 
       FIG. 8  illustrates a waveform diagram of the operation of an embodiment power supply driver. During phase  802 , high voltage system supply HV supply ramps up and powers up VEE 2 , VREG and JFDrv. (Note that these nodes are referenced to VCC 2  in  FIG. 8 .) During phase  802 , signal JFDrv is driven low and driver signal MDrv remains high, thereby keeping the driven MOSFET off. During phase  804 , MDrv and JFDrv are toggled together as described herein with respect to other embodiments of the present invention. Furthermore, in some embodiments, auxiliary supply VCC 1  and/or node PM25VH coupled to node VEE 2  ( FIG. 7   b ) becomes fully activated. 
     Once VREG reaches its fully regulated voltage and crosses threshold V VREGon , the driver begins operating in normal operation mode  806 . Here, signal MDrv is low with respect to VCC 2 , while JFDrv continues to toggle. This corresponds to a mode of operation where the MOSFET remains on while the JFET continues switching. During operation mode  806 , I_BSEN, which is driver circuit output pin indicating that normal operation mode  806  is active, goes high. In some embodiments, I_BSEN is implemented as a bidirectional pin that senses a voltage when used as an input and produces a current when used as an output. 
     If regulated voltage VREG crosses threshold V VREGoff , operation mode  804  is re-entered and signals MDrv and JFDrv are toggled together. In some embodiments, VREG crosses threshold V VREGoff  when VEE 2  drops, thereby causing a loss of power at VREG. This can also be caused, for example, by loss of supply  110  ( FIG. 1   a ). In some embodiments, hysteresis is applied by setting threshold V VREGon  different from threshold V VREGoff  in order to prevent excessive toggling between operation modes. 
     In an embodiment, the high-side driver and the low-side driver can be implemented on the same integrated circuit. Alternatively, each driver can be implemented on separate integrated circuits. In some embodiments, the half-bridge circuit can also be disposed on the same integrated circuit as one or both of the drivers. 
     In alternative embodiments, embodiment driver systems can also be used to drive other types of circuits such as full-bridge switches and motors. 
     In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch. 
     In an embodiment, the driver circuit also includes a high-side driver having a first output configured to be coupled to a control node of a second semiconductor switch, and a reference input configured to be coupled to an output node of the second semiconductor switch. The output node of the second semiconductor switch is coupled to the output node of the first semiconductor switch. The high-side driver also includes a third capacitor coupled between a first power input of the high-side driver and the reference input of the high side driver, a second diode coupled between a high-side reference potential node and the first power input of the high-side driver, and a third diode coupled between the first node and the high-side reference potential node. In an embodiment, the high-side driver and the low-side driver provide drive signals for an half-bridge circuit, where the half-bridge circuit includes the first semiconductor switch and the second semiconductor switch. In an embodiment, the driver circuit also includes a power supply coupled between a reference node of the second semiconductor switch and the high-side reference potential node. 
     In an embodiment, the first semiconductor switch is a JFET in series with a MOSFET. In some embodiments, the MOSGET is a PMOS and/or a NMOS device. In an embodiment, the low-side driver keeps the MOSFET off when a reference supply voltage is below a first threshold voltage, operates the MOSFET and the JFET together when the reference supply voltage is between the first threshold voltage and a second threshold voltage, and keeps the MOSFET on when the reference supply voltage is greater than the second threshold voltage. 
     In an embodiment, the reference supply voltage is comprises a voltage proportional to a voltage of the first power input of the low side driver. In some embodiments, the low-side driver comprises a voltage regulator coupled between the first power input of the low-side driver, such that the voltage regulator has an output, and the reference supply voltage comprises a voltage proportional to a voltage of the output of the voltage regulator. In an embodiment, the low-side driver operates the MOSFET and the JFET together by turning on the MOSFET before turning on the JFET, and turning off the JFET before turning off the MOSFET. 
     In accordance with another embodiment, a switch driver comprising a low-side driver coupled to a first switch. A method of operating the switch driver includes charging a supply node of the low-side driver with a first network coupled between an output of a first switch and a supply node of the low-side driver. The first network includes a capacitor in series with a first diode. In an embodiment, charging the supply node includes charging the supply node below ground potential. 
     In an embodiment, the switch driver further comprises a high-side driver coupled to a second switch, where the second switch coupled in series with the first switch, and the method further includes charging a supply node of the high-side driver with a second network coupled between an output of the second switch and supply node of the high side driver. The second network includes the capacitor in series with a second diode. 
     In an embodiment, the first switch includes a JFET device in series with a MOSFET device, and the method further includes operating the JFET device and the MOSFET device together when supply nodes of the switch driver are charging up after the switch driver has started up, and keeping the MOSFET device on while turning the JFET device on and off after the supply nodes of the switch driver are charged to a full operating state. In one embodiment, the method also includes keeping the MOSFET device off during startup of the switch driver. 
     In an embodiment, the first switch includes a JFET device in series with a MOSFET device, and the method also includes operating the JFET device and the MOSFET device together when a reference supply voltage is between a first threshold voltage and a second threshold voltage, and keeping the MOSFET device on while turning the JFET device on and off when the reference supply voltage is greater than the second threshold voltage. In an embodiment, the method also includes keeping the MOSFET device off when the reference supply voltage is below the first threshold voltage. In an embodiment, operating the JFET device and the MOSFET device together includes turning on the MOSFET device before turning on the JFET device, and turning off the JFET device before turning off the MOSFET device. 
     In accordance with a further embodiment, a system includes a first switch coupled in series with a second switch at a common node, a low-side driver coupled to the first switch, a high-side driver coupled to the second switch, and a bootstrap capacitor having a first end coupled to the common node. The system also includes a first diode coupled between a second end of the bootstrap capacitor and power supply node of the low-side driver, a first storage capacitor coupled between the power supply node of the low-side driver and a reference node of the low-side driver, a second diode coupled between the second end of the bootstrap capacitor and a power supply node of the high-side driver, and a second storage capacitor coupled between the power supply node of the high-side driver and a reference node of the high-side driver. 
     In an embodiment, the first switch includes a first JFET in series with a first MOSFET, the second switch includes a second JFET in series with a second MOSFET. In an embodiment, the low-side driver is configured to keep the first MOSFET off when a first reference supply voltage is below a first threshold voltage, operate the first MOSFET and the first JFET together when the first reference supply voltage is between the first threshold voltage and a second threshold voltage, and keep the first MOSFET on and operate the first JFET when the first reference supply voltage is greater than the second threshold voltage. In an embodiment, the high-side driver is configured to keep the second MOSFET off when a second reference supply voltage is below a third threshold voltage, operate the second MOSFET and the second JFET together when the second reference supply voltage is between the third threshold voltage and a fourth threshold voltage, and keep the second MOSFET on and operate the second JFET when the second reference supply voltage is greater than the fourth threshold voltage. 
     In an embodiment, the low-side driver is configured to operate the first MOSFET and the first JFET together by turning on the first MOSFET before turning on the first JFET, and turning off the first JFET before turning off the first MOSFET. Furthermore, the high-side driver is configured to operate the second MOSFET and the second JFET together by turning on the second MOSFET before turning on the second JFET, and turning off the second JFET before turning off the second MOSFET. 
     In an embodiment, the system also includes a transformer coupled to the common node, and a power supply controller coupled to the low-side driver and the high-side driver, wherein the power supply is configured to regulate a voltage of a power supply output node coupled to the transformer. 
     Advantages of embodiments of the present invention include the ability to bias a low-side driver without using additional transformers by pumping charge from an output of a half-bridge circuit. 
     Although present embodiments and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the features and functions discussed above can be implemented in software, hardware, or firmware, or a combination thereof. 
     Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.