Patent Publication Number: US-8115243-B2

Title: Surround gate access transistors with grown ultra-thin bodies

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. patent application Ser. No. 11/175,677, filed Jul. 6, 2005, entitled “SURROUND GATE ACCESS TRANSISTORS WITH GROWN ULTRA-THIN BODIES” (now U.S. Pat. No. 7,888,721). It is also related to U.S. patent application Ser. No. 11/557,224, filed Nov. 7, 2006, entitled “SURROUND GATE ACCESS TRANSISTORS WITH GROWN ULTRA-THIN BODIES” (now U.S. Pat. No. 7,601,595), and U.S. patent application Ser. No. 11/622,148, filed Jan. 11, 2007, entitled “SURROUND GATE ACCESS TRANSISTORS WITH GROWN ULTRA-THIN BODIES” (now U.S. Pat. No. 7,626,219). The entire disclosure of the above is hereby incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to the field of semiconductor memory arrays and, more particularly, to arrays with access transistors having grown ultra-thin bodies. 
     2. Description of the Related Art 
     Ongoing scaling of metal oxide semiconductor field effect transistor (MOSFET) technology to the deep sub-micron region where channel lengths are less than 0.1 micron (100 nanometers or 1,000 Å) causes significant problems in conventional transistor structures. Generally, junction depth should be much less than the channel length, and thus for a channel length of, for example 1,000 Å, this implies junction depths on the order of a few hundred Angstroms. Such shallow junctions are difficult to form by conventional implantation and diffusion techniques. 
       FIG. 1  illustrates general trends and relationships for a variety of device parameters with scaling by a factor k. As another example, with an aggressive scaling factor, extremely high levels of channel doping are required to suppress undesirable short channel effects, such as drain induced barrier lowering (DIBL), threshold voltage roll off, and sub-threshold conduction. Sub-threshold conduction is particularly problematic in dynamic random access memory (DRAM), as it significantly reduces the charge storage retention time of the capacitor cells. Extremely high doping level generally results in increased leakage and reduced carrier mobility. Thus making the channel shorter to improve performance is offset or negated by the lower carrier mobility and higher leakage. This leakage current is a significant concern and problem in low voltage and low power battery operated complimentary metal oxide semiconductor (CMOS) circuits and systems, particularly in DRAMs. 
       FIG. 2  shows that if low voltages are used for this low power operation, there is a problem with threshold voltages and standby leakage current being of large enough value to degrade overall circuit performance. For example, to achieve significant overdrive and reasonable system switching speeds, the threshold voltage magnitudes are desirably small, in this example near 0 volts. However the transistor, such as an access transistor, will always have a large sub-threshold leakage current. Various technologies have been employed to allow low voltage operation with deep sub-micron CMOS transistors that can have relatively large variations in threshold voltage, yet still have relatively low sub-threshold leakage currents at standby. 
     For example, one technique used in scaling down transistors is referred to as dual-gated or double-gated transistor structures. The terminology generally employed in the industry is “dual-gate” if the transistor has a front gate and a back gate which can be driven with separate and independent voltages and “double-gated” to describe structures where both gates are driven with the same potential. In certain aspects, a dual-gated and/or double-gated MOSFET offers better device characteristics than conventional bulk silicon MOSFETs. Because a gate electrode is present on both sides of the channel, rather than only on one side as in conventional planar MOSFETs, the electrical field generated by the drain electrode is better screened from the source end of the channel than in conventional planar MOSFETs, as illustrated schematically by the field lines in  FIG. 3 . 
     This can result in an improved sub-threshold leakage current characteristic, as illustrated schematically in  FIG. 4 . The dual-gate and/or double-gate MOSFET turns off and the sub-threshold current is reduced more quickly as the gate voltage is reduced. However, even though dual gate and/or double gate structures offer advantages over conventional bulk silicon MOSFETs, there remains a desire for continued improvement in device performance with continued aggressive scaling. More particularly, there is a need to provide very thin transistor bodies that can control short channel effects with reduced need for extremely high doping levels to avoid the aforementioned difficulties. There is also a need for devices that can be more easily and reliably fabricated. 
     SUMMARY OF THE INVENTION 
     The aforementioned needs are satisfied by the invention which in one embodiment comprises a transistor comprising a vertical annular semiconductive transistor body, a surround gate structure formed around the annular transistor body, a source region formed adjacent a lower portion of the body, and a drain region formed adjacent an upper portion of the body such that the transistor defines a field effect transistor. 
     Another embodiment comprises An access array for memory cells comprising a semiconductive substrate, a plurality of first conductors formed in a first direction along a surface of the substrate, a plurality of transistors formed on the surface of the substrate so as to be offset from associated first conductors and at least partially connected to the associated first conductors, and a plurality of second conductors formed in a second direction and electrically connected with associated transistors such that the transistors can be turned on and off by application of appropriate potentials to the second conductors. 
     Yet another embodiment comprises a method of forming transistor structures comprising forming a pillar vertically extending from a surface of a substrate, growing a single crystalline semiconductive transistor body to extend vertically around the pillar, forming a surround gate structure around the transistor body, forming a source region adjacent lower portions of the transistor body, and forming a drain region adjacent an upper portion of the transistor body. 
     Thus, various embodiments provide an annular, vertical transistor body having ultra-thin dimensions. The transistor body can be grown which avoids difficulties in sub-lithographic etching based process. The transistors can also be offset from alignment with buried data/bit lines which provides a continuous conductive path extending alongside source regions of the transistors. The continuous conductive path provides improved conductive characteristics for the data/bit lines, particularly over extended distances. These and other objects and advantages of the invention will be more apparent from the following description taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is schematic illustration of general relationships of various device parameters/characteristics for a scaling factor k; 
         FIG. 2  is a graph illustrating sub-threshold leakage in a conventional silicon MOSFET; 
         FIG. 3  is a schematic illustration of a known dual-gate MOSFET; 
         FIG. 4  is a graph illustrating sub-threshold conduction characteristics of conventional bulk silicon MOSFETs and of dual-gate and/or double gate MOSFETs; 
         FIG. 5  is a circuit schematic illustration of one embodiment of a memory array; 
         FIG. 6  is a top view of one embodiment of a memory access array with access transistors having grown ultra-thin bodies; 
         FIG. 7  is a perspective view of one embodiment of a memory access array with access transistors having grown ultra-thin bodies; 
         FIGS. 8A ,  8 B, and  8 C are top, front section, and rear section views respectively of one embodiment of an access transistor with a grown ultra-thin body; 
         FIGS. 9A ,  9 B, and  9 C are side, front, and rear views respectively of surface conduction channels arising in certain embodiments under appropriate applied potentials; 
         FIG. 10A  illustrates another embodiment of an ultra-thin body transistor wherein the body is configured generally as a solid pillar; 
         FIG. 10B  illustrates another embodiment of a grown ultra-thin body transistor wherein the body is configured generally as an annular structure encompassing a vertical pillar; and 
         FIGS. 11 through 14  illustrate embodiments of methods of fabrication of a memory array. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Description of various embodiments of the invention will now be described with respect to the drawings wherein like reference designators refer to like structures, elements, and/or processes throughout. It should be understood that the illustrations are schematic in nature and should not be interpreted as being to scale.  FIG. 5  is a schematic circuit diagram of one embodiment of a memory array  100 . The memory array  100  is configured for storage and retrieval of digital data in a plurality of memory cells  102  comprising the array  100 . In this embodiment, each memory cell  102  comprises an access transistor  104  connected to a charge storage device  106 . In one embodiment, the charge storage device  106  comprises a stacked storage capacitor which will be described in greater detail below. The charged storage devices  106  store the digital data wherein presence of a predetermined quantity of charge on a charge storage device  106  corresponds to a first data state and wherein absence of the predetermined charge corresponds to a second data state. The access transistors  104  are connected to corresponding charge storage devices  106 . This provides a selectable electrically conductive path to the charge storage device  106  to provide a path to the charge storage devices  106  for write operations, as well as to evaluate the quantity of charge stored on the charge storage devices  106  in read operations. 
     The array  100  also comprises one or more row decoder modules  110  which are connected to a plurality of word lines  112 . Each word line  112  is connected to a corresponding plurality of access transistors  104 . The word lines  112  with corresponding access transistors  104  are arranged in parallel in what is generally referred to as columns. The word lines  112  conduct electrical signals which turn on or turn off the corresponding column of access transistors  104  for read and write operations to the corresponding memory cells  102 . 
     The array  100  also comprises one or more column decoder modules  114  which comprise a plurality of sense amplifiers. The one or more column decoders  114  are connected to a plurality of data/bit lines  116 . The data/bit lines  116  are also connected to a plurality of access transistors  104 . The data/bit lines  116  with the associated access transistors  104  are arranged in parallel in what is generally referred to as a row configuration. Thus, the word lines  112  and data/bit lines  116  are arranged in intersecting directions and, in one particular embodiment, are arranged so as to define a generally rectangular array of the memory cells  102 . The data/bit lines  116  also conduct signals to the one or more column decoder modules  114  wherein the signals are indicative of the quantity of charge stored on the associated charge storage devices  106 . Similarly, the data/bit lines  116  can be utilized to provide the predetermined charge quantity to a charge storage device  106  or to drain the charge from the charge storage device  106  to affect write operations. Thus, activation of a selected word line  112  and a data bit line  116  provides access to the memory cell  102  at the intersection of these selected word line  112  and data/bit line  116 . 
     The one or more row decoder modules  110  and one or more column decoder modules  114  are also connected to an address buffer  120 . The address buffer  120  can provide electrical signals corresponding to particular data states to the individual memory cells  102  of the array  100  via the row decoder modules  110  and column decoder modules  114  for write operations. Similarly, the address buffer  120  can receive signals corresponding to the stored data state of the individual memory cells  102  again via the row decoders  110  and column decoders  114  in rad operations. The address buffer  120  is configured for interface with one or more other systems in manners well understood by those of ordinary skill. 
       FIG. 6  illustrates schematically in a top view one embodiment of access transistors  104  of an array  100 . In this embodiment, the access transistors  104  comprise a vertically extending central pillar  130  (see also  FIGS. 7 ,  8   b , and  8   c ). The central pillar  130  extends upward from an upper surface of a semi-conductive substrate  150 . In one particular embodiment, the central pillar  130  has a generally rectangular or square cross-section. However in other embodiments the pillar  130  describes a generally circular or oval cross-section, a triangular cross-section, or other shape appropriate to the requirements of particular applications. 
     In this embodiment, the access transistors  104  also comprise an annular transistor body  132  which substantially surrounds or encompasses the central pillar  130  along the vertical sides and top of the pillar  130 . In one embodiment, the annular transistor body  132  comprises silicon which is doped to approximately 5×10 17 /cm 2  with boron. The annular transistor body  132  provides an active transistor region for a field affect transistor structure which will be described in greater detail below. 
     In one particular embodiment, the central pillar  130  has a lateral or horizontal dimension D 1  of approximately 80 nm or 0.08 μm. The annular transistor body  132  has an outer lateral or horizontal dimension D 2  of approximately 100 nm or having an ultra-thin wall thickness T of approximately 20 nm. Thus, the annular transistor body  132  describes a generally vertical hollow annular structure having a wall thickness of approximately 20 nm. In one embodiment, the annular transistor body  132  also has a height H of approximately 100 nm. 
     The access transistors  104  also comprise a gate dielectric  134  surrounding the annular transistor body  132 . The gate dielectric  134  describes a generally annular vertically extending structure in contact with the body  132 . The gate dielectric  134  has similar cross-section to the annular transistor body  132 . The access transistors  104  also comprise a gate conductor  136  which surrounds or encompasses the gate dielectric  134 . In one embodiment, the gate conductor  136  comprises conductive doped polycrystalline silicon (polysilicon). The gate conductor  136  is connected at opposed vertical or faces S 1  and S 2  to corresponding word lines  112 . In one particular embodiment, each word line  112  comprises a separate first word line  112   a  and a second word line  112   b . In certain embodiments, the word lines  112   a  and  112   b  are driven at the same voltage to apply or remove potential from the corresponding gate conductors  136  in concert. In other embodiments, the word lines  112   a  and  112   b  can be independently driven. 
     A dielectric layer or region  140  is positioned between adjacent individual access transistors  104  to electrically isolate each access transistor  104  from adjacent neighboring access transistors  104 . In certain embodiments, the gate dielectric structures  134  and dielectric layers  140  comprise a single materially continuous layer or region and in other embodiments, the gate dielectric structures  134  and dielectric layer or regions  140  comprise separate structures. 
     As can also be seen in  FIGS. 6 ,  7 , and  8 C, in one embodiment the access transistors  104  are offset from overlying centered alignment with the data/bit lines  116 . In one particular embodiment, the access transistors  104  are offset laterally by a distance of approximately half the width of the access transistor  104  along the directions of the word lines  112  such that approximately half of the access transistor  104  overlies the corresponding data/bit line  116  with the remaining half extending beyond the edge or boundary of the corresponding data/bit line  116 . This provides a region of the data/bit line  116  substantially isolated from the transistor action of the access transistors  104  to improve the conduction characteristics of the data/bit lines  116  as will be described in greater detail below. 
       FIGS. 8A ,  8 B, and  8 C illustrate top, front, and side section views respectively of one embodiment of access transistor  104  in greater detail. As shown in  FIG. 8B , the annular transistor body  132 , in this embodiment, encompasses or surrounds the central pillar  130  along vertical sides thereof as well as along an upper surface thereof. In this embodiment, the annular transistor body  132  comprises a single crystalline body region  142  extending upwards from the upper surface of the substrate  150  along the sides or vertical surfaces of the central pillar  130 . In one embodiment described in greater detail below, the single crystalline body region  142  comprises a grown region of silicon which is grown along the sides of the vertically extending central pillar  130 . 
     The annular transistor body  132  also comprises a multiple grain region  144  positioned generally at the top or upper regions of the transistor body  132 . The multiple grain region  144  comprises a region of the transistor body  132  wherein multiple silicon crystalline structures merge to define a plurality of grain boundaries of a polycrystalline silicon region. Formation of a conduction channel for the transistors  104  occurs substantially in the single crystalline body region  142  rather than in the multiple grain region  144 . Thus, the grain boundaries have reduced negative effects on the operational performance of the access transistor  104  as the multiple grain region  144  is utilized to form the drain region  152  which contacts an overlying charge storage device  106  via a drain contact  154 . 
     The transistor body  132  as partially overlying the data/bit lines  116  also define source regions  146  positioned generally at the lower regions of the transistor body  132 . The drain regions  152  are positioned at upper regions of the transistor body  132  and in certain embodiments at least partially comprise the multiple grain region  144 . As can be seen in  FIG. 8C , as the access transistor  104  is offset from alignment atop the corresponding data/bit line  116 , the source region  146  extends along the lower extent of the transistor body  132  along one side  156  of the transistor body  132  and across approximately half of the adjacent sides. The source region  146  generally is defined by the portions of the lower regions of the transistor body  132  which overly the associated data/bit line  116 . Thus, the source region is present on a first side of the transistor body  132  and substantially absent on the opposite side and extends approximately halfway in-between. 
     A continuous conductive path  170  ( FIG. 8C ) is also defined in the data/bit lines  116  extending adjacent the source regions  146 . The continuous conductive path  170  provides conductive regions of the data/bit lines  116  that are not significantly involved in the transistor operation of the transistors  104 . This improves the conduction characteristics of the data/bit lines  116  and facilitates further aggressive scaling of the array  100 . 
     As illustrated schematically in  FIGS. 9A ,  9 B, and  9 C in side, front, and back views respectively, the source region  146  defines a relatively narrow region in lateral extent as compared to a relatively wide drain region  152 . Again, the source region  146  is generally defined by the overlap of the access transistor  104  and more particularly the transistor body  132  over the underlying data/bit line  116 . Under appropriate application of operating potentials by the word lines  112  and data/bit lines  116 , conduction channels  160  will form along the surface of the transistor body  132  and more particularly along the single crystalline body region  142 . Current will thus fan out from the source region configured generally as a U or C-shaped region at approximately one-half the perimeter of the lower extent of the transistor body  132  upwards to the generally larger and planar drain region  152 . The rearward or back side portion of the transistor body  132  does not overlap the underlying data/bit line  116  and thus has significantly less contribution to the formation of the conduction channels  160 . However, potential applied via the word lines  112  will be communicated by the surround gate structure  138  to more effectively control potential in the central pillar  130  for more reliable switching of the transistor  104  off and on. 
       FIGS. 10A and 10B  illustrate schematically two embodiments of access transistor  104  and illustrate generally electron potential distributions in the access transistor  104 . More particularly,  FIG. 10A  illustrates in side section view one embodiment of the access transistor  104  wherein the central pillar  130  comprises oxide and the transistor body  132  is configured as an annular vertically extending structure encompassing the central pillar  130 . In this embodiment, the annular transistor body  132  comprises doped silicon. The pillar  130  comprising silicon oxide has a lower dielectric constant than the silicon forming the transistor body  132 . In addition, there are substantially no ionized impurity dopant atoms in the oxide pillar  130  in contrast to the composition of the annular transistor body  132 . This leads to differences in the potential distributions and indicated gate potentials for the embodiments illustrated in  FIGS. 10A and 10B  as described below. 
       FIG. 10B  illustrates another embodiment of an access transistor  104 ′ wherein the central pillar  130  and transistor body  132  are merged into a single ultra thin pillar which also provides the transistor body  132  of the access transistor  104 ′. As can be seen in a comparison of  FIGS. 10   a  and  10   b , potential variations through the silicon pillar  130 ,  132  of the access transistor  104 ′ will be greater than in the separate transistor body  132  and central oxide pillar  130 . In both embodiments, however, transistor action of the access transistor  104  and  104 ′ will be similar and the conduction channels  160  will form at the surface of the transistor body  132  or combined pillar  130 ′ and transistor body  132 ′ underneath the adjacent gate dielectric structures  134 . The operational characteristics of the access transistor  104  will describe a generally steeper sub-threshold slope than for the access transistor  104 ′. 
     The combined pillar  130 ′ and transistor body  132 ′ of the access transistor  104 ′ will also typically exhibit more body charge than in the access transistor  104  wherein the central pillar  130  comprises oxide and the transistor body  132  is separate and comprises silicon. Thus, generally a lower gate voltage will be required for operation of the access transistor  104  as compared to the access transistor  104 ′. The difference in appropriate gate voltage to operate the access transistors  104 ,  104 ′ will vary depending on the specifics of particular applications. In one embodiment, approximately 30 percent lower gate voltages would be indicated for the embodiment of access transistor  104 , such as illustrated in  FIG. 10A  having a central pillar  130  comprising oxide with an annular transistor body  132  as compared to the appropriate gate voltages for the embodiment of access transistor  104 ′, such as illustrated in  FIG. 10B . The lower gate voltage typically required to operate the embodiment of access transistor  104 , such as illustrated in  FIG. 10A , is obtained at the expense of increased steps in the fabrication of this embodiment, as will be described in greater detail below. 
       FIGS. 11 through 14  illustrate embodiments of a method  200  of forming a memory array  100  including the access transistors  104  previously described. As shown in  FIG. 11 , an implant procedure  202  is performed to form the plurality of data/bit lines  116 . In one particular embodiment, the implant  202  is performed with implant parameters of approximately 1×10 15 /cm 2  of boron at approximately 20 keV. The pillars  130  are then formed to extend upwards from an upper surface of the substrate  150  and to at least partially overlie the underlying implanted data/bit lines  116 . In one particular embodiment, the pillars  130  are formed such that approximately one-half of the pillar  130  overlies the associated varied data/bit line  116 . Additional details of embodiments of forming the pillars  130  may be found in the co-pending application Ser. No. 11/129,502 filed May 13, 2005 which is incorporated herein by reference in its entirety. 
       FIG. 12  illustrates subsequent steps in one embodiment of the method  200  wherein a layer of amorphous silicon is deposited as indicated by the reference number  204  so as to overly the upper surface of the substrate  150  as well as the plurality of vertically extending pillars  130 . The thickness of amorphous silicon doped with boron  204  deposited will vary depending on the indications of particular applications, however, in one embodiment, comprises a deposition of approximately 20 nm. The amorphous silicon  204  is then recrystallized as indicated by the reference number  206  to form the single crystalline body region  142  by a solid phase epitaxial growth process  206 . In one embodiment, the solid phase epitaxial growth process  206  proceeds at parameters of approximately 750° C. Since the pillars  130  are relatively short, in certain embodiments having a height H of 100 nanometers or less, the solid phase epitaxial growth  206  can readily grow the single crystalline structure  142  over such relatively short distances. As previously noted, in certain embodiments at the upper regions of the transistor body  132 , a multiple grain region  144  is formed wherein the amorphous silicon  204  is transformed to a polycrystalline silicon structure having grain boundaries. However, this multi-grain region  144  will have relatively benign impact on the overall performance of the access transistor  104  as the drain contact  154  to an overlying charge storage device  106  is formed in this multiple grain region  144 . 
       FIG. 13  illustrates schematically in top view further steps of one embodiment of a method  200  for forming the array  100  comprising the plurality of access transistors  104 .  FIG. 13  illustrates that the previously deposited amorphous silicon  204  has been transformed via a solid phase epitaxial growth process  206  to define the transistor body  132  including the single crystalline body region  142 . Following this, a gate dielectric formation step  210  is performed wherein the gate dielectric  134  is grown or deposited in a well known manner to encompass the transistor body  132 . In a gate conductor formation step  212  is performed to define the gate conductor structure  136 . In one particular embodiment, the gate conductor formation  212  comprises depositing polysilicon and performing a directional or anisotropic edge, such that the gate dielectric  134  and overlying gate conductor  136  are formed on the sidewalls of the transistor body  132  to define the surround gate structure  138 . 
       FIG. 14  illustrates one embodiment of further steps in the method  200  of forming a memory array  100 . In this embodiment, an isolation step  214  is performed wherein dielectric material, such as silicon oxide, is filled in the interstitial spaces between adjacent access transistors  104 . Following the isolation step  214 , a planarization step  216  is performed in one embodiment by a chemical mechanical planarization/polishing (CMP) process. An implantation  218  of arsenic of approximately 1×10 15 /cm 2  is performed into the top of the pillars  130  to form the doped drain regions  152 . A trench formation step  220  is then performed to define a plurality of elongate trenches extending generally in the column direction between adjacent columns of the access transistors  104 . Then a word line formation step  222  is performed wherein polysilicon and/or metal is deposited and directionally etched to form the address or word lines  112  positioned along the side walls of the trenches and in contact with the surround gate structures  138 . The remainder of the structures for formation of the memory array  100 , for example, including formation of the overlying charge storage devices  106 , passivation, and formation of interconnect wiring then proceeds according to well known conventional techniques. 
     Thus, various embodiments provide an array of access transistors  104  which have a generally annular vertically extending transistor body having relatively thin side walls, in certain embodiments of a thickness of approximately 20 nm. This provides access transistors  104  which can accommodate continued aggressive scaling with reduced need for relatively high doping levels to suppress short channel effects. Certain embodiments also avoid the requirement for fabricating the access transistors  104  at sub-lithographic dimensions as the transistor body  132  is grown rather than etched. A solid phase epitaxial growth process can provide a single crystalline body region  142  of ultra-thin dimensions in a manner that is easier to fabricate than alternative processes and structures. 
     Although the foregoing description of the preferred embodiment of the present invention has shown, described, and pointed out the fundamental novel features of the invention, it will be understood that various omissions, substitutions, and changes in the form of the detail of the apparatus as illustrated, as well as the uses thereof, may be made by those skilled in the art without departing from the spirit of the present invention.