Patent Publication Number: US-10333499-B2

Title: Signal transmission circuit and vehicle

Description:
This nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 2016-141242 filed in Japan on Jul. 19, 2016, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a signal transmission circuit which uses an insulating element to transmit an input signal and to a vehicle which uses such a signal transmission circuit. 
     Description of Related Art 
     As an example of a signal transmission circuit which uses an insulating element to transmit a single input signal, there can be a signal transmission circuit which is disclosed in Japanese Unexamined Patent Application Publication No. 2014-7502. 
       FIG. 12  is a diagram showing the configuration of the signal transmission circuit disclosed in Japanese Unexamined Patent Application Publication No. 2014-7502.  FIG. 13  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 12 . 
     The signal transmission circuit shown in  FIG. 12  includes a pulse generation portion  101 , excitation circuits  102  and  103 , pulse transformers  104  and  105 , pulse detection portions  106  and  107  and a latch circuit  108 . 
     The pulse generation portion  101  generates and outputs transmission signals Str 101  and Str 102  corresponding to an input signal Sin. When the input signal Sin is switched from low to high, the pulse generation portion  101  generates a pulse and incorporates the pulse in the transmission signal Str 101 . On the other hand, when the input signal Sin is switched from high to low, the pulse generation portion  101  generates a pulse and incorporates the pulse in the transmission signal Str 102 . In Japanese Unexamined Patent Application Publication No. 2014-7502, each time the logic of the input signal Sin is switched, one pulse is generated whereas in  FIG. 13 , each time the logic of the input signal Sin is switched, three pulses are generated at a predetermined period. 
     The transmission signal Str 101  is transmitted by a first transmission portion to the set input terminal (S) of the latch circuit  108 . The first transmission portion is formed with the excitation circuit  102 , the pulse transformer  104  and the pulse detection portion  106 . 
     The transmission signal Str 102  is transmitted by a second transmission portion to the reset input terminal (R) of the latch circuit  108 . The second transmission portion is formed with the excitation circuit  103 , the pulse transformer  105  and the pulse detection portion  107 . 
     The latch circuit  108  outputs an output signal Sout from an output terminal (Q). When the pulse is input to the set input terminal (S), the latch circuit  108  turns the output signal Sout high. On the other hand, when the pulse is input to the reset input terminal (R), the latch circuit  108  turns the output signal Sout low. 
     When a plurality of input signals are transmitted, it can be considered that a plurality of signal transmission circuits described above and shown in  FIG. 12  are simply used. In the following discussion, a case where two input signals are transmitted will be described as an example.  FIG. 14  shows a signal transmission circuit which transmits two input signals.  FIG. 15  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 14 . 
     The signal transmission circuit shown in  FIG. 14  includes two signal transmission circuits of the same configuration as the signal transmission circuit described above and shown in  FIG. 12 . 
     When in the signal transmission circuit shown in  FIG. 14 , timings at which a pulse is generated in a plurality of transmission signals accidentally coincide with each other (see a period P 1  in  FIG. 15 ), a variation in power supply voltage supplied to the signal transmission circuit shown in  FIG. 14  is increased. Consequently, the signal transmission circuit shown in  FIG. 14  itself or another circuit which shares the power supply voltage with the signal transmission circuit shown in  FIG. 14  may be erroneously operated. 
     Moreover, when in the signal transmission circuit shown in  FIG. 14 , timings at which a pulse is generated in a plurality of transmission signals accidentally coincide with each other (see the period P 1  in  FIG. 15 ), a plurality of pulse transformers are simultaneously driven, and thus radiation noise from the signal transmission circuit shown in  FIG. 14  is increased. Consequently, the radiation noise from the signal transmission circuit shown in  FIG. 14  may exceed an allowable range. 
     In order to check whether an abnormality occurs in the transmission of an input signal, a feedback circuit which feeds back a signal indicating the input signal by the transmission of an output signal may be added to the signal transmission circuit shown in  FIG. 14 . When such an addition is performed, in order to check whether an abnormality occurs in the transmission of a plurality of input signals, it is necessary to prepare the same number of feedback circuits as the input signals in which whether an abnormality occurs in the transmission is checked, with the result that more serious problems are caused by increasing a variation in the power supply voltage and the radiation noise. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a signal transmission circuit which can transmit a plurality of input signals while reducing a variation in power supply voltage and the generation of radiation noise and a vehicle which uses such a signal transmission circuit. 
     A signal transmission circuit disclosed in the present specification transmits N (N is a natural number of 2 or more) input signals, and includes: a transmission signal generation portion arranged to generate 2 N  transmission signals according to the N input signals; 2 N  transmission portions arranged respectively to transmit the 2 N  transmission signals output from the transmission signal generation portion while performing electrical insulation; and an output portion arranged to generate and output, based on the 2 N  transmission signals transmitted by the 2 N  transmission portions, N output signals that respectively indicate the N input signals, and the transmission signal generation portion generates a pulse according to the N input signals and incorporates the pulse in only one of the 2 N  transmission signals at a same time. 
     A vehicle disclosed in the present specification includes the signal transmission circuit of the configuration described above. 
     The significance and effects of the present invention will become more obvious from the description of an embodiment discussed below. However, the embodiment discussed below is only one embodiment of the present invention, and the present invention and the significance of the terms of individual constituent requirements are not limited to the embodiment discussed below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing a first configuration example of a signal transmission circuit; 
         FIG. 2A  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 1 ; 
         FIG. 2B  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 1 ; 
         FIG. 3A  is a timing chart showing another example of the operation of the signal transmission circuit shown in  FIG. 1 ; 
         FIG. 3B  is a timing chart showing another example of the operation of the signal transmission circuit shown in  FIG. 1 ; 
         FIG. 4  is a diagram showing a second configuration example of the signal transmission circuit; 
         FIG. 5  is a diagram showing a third configuration example of the signal transmission circuit; 
         FIG. 6  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 5 ; 
         FIG. 7  is a diagram showing a relationship between a transmission signal and an output signal; 
         FIG. 8  is a diagram showing a fourth configuration example of the signal transmission circuit; 
         FIG. 9A  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9B  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9C  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9D  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9E  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9F  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9G  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9H  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9I  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9J  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9K  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 9L  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 8 ; 
         FIG. 10  is an external view of a vehicle; 
         FIG. 11  is a diagram showing an example of a schematic configuration example of a motor drive system incorporated in the vehicle; 
         FIG. 12  is a diagram showing the configuration of a signal transmission circuit disclosed in Japanese Unexamined Patent Application Publication No. 2014-7502; 
         FIG. 13  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 12 ; 
         FIG. 14  is a diagram showing the configuration of a signal transmission circuit which has two signal transmission circuits of the same configuration as the signal transmission circuit shown in  FIG. 12 ; and 
         FIG. 15  is a timing chart showing an example of the operation of the signal transmission circuit shown in  FIG. 14 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Configuration Example 
       FIG. 1  is a diagram showing a first configuration example of a signal transmission circuit.  FIGS. 2A, 2B, 3A and 3B  are timing charts showing examples of the operation of the signal transmission circuit in the present configuration example. 
     The signal transmission circuit of the present configuration example includes a pulse generation portion  1 , excitation circuits  2  to  5 , pulse transformers  6  to  9 , pulse detection portions  10  to  13 , OR gates  14  to  17  and latch circuits  18  and  19 . 
     The pulse generation portion  1  detects the switching of the logic of each of input signals Sin 1  and Sin 2 , and generates pulses according to the result of the detection. The pulse generation portion  1  incorporates the pulses in only one of four transmission signals Str 1  to Str 4  at the same time. 
     When the input signal Sin 2  is low, and the input signal Sin 1  is switched from low to high, the pulse generation portion  1  generates three pulses at a predetermined period and incorporates the three pulses in the transmission signal Str 1  (see  FIG. 2A ). On the other hand, when the input signal Sin 2  is low, and the input signal Sin 1  is switched from high to low, the pulse generation portion  1  generates three pulses at the predetermined period and incorporates the three pulses in the transmission signal Str 2  (see  FIG. 2A ). 
     When the input signal Sin 2  is high, and the input signal Sin 1  is switched from low to high, the pulse generation portion  1  generates three pulses at the predetermined period and incorporates the three pulses in the transmission signal Str 3  (see  FIG. 2A ). On the other hand, when the input signal Sin 2  is high, and the input signal Sin 1  is switched from high to low, the pulse generation portion  1  generates three pulses at the predetermined period and incorporates the three pulses in the transmission signal Str 4  (see  FIG. 2A ). 
     When the input signal Sin 1  is low, and the input signal Sin 2  is switched from low to high, the pulse generation portion  1  generates three pulses at the predetermined period and incorporates the three pulses in the transmission signal Str 4  (see  FIG. 2A ). On the other hand, when the input signal Sin 1  is low, and the input signal Sin 2  is switched from high to low, the pulse generation portion  1  generates three pulses at the predetermined period and incorporates the three pulses in the transmission signal Str 2  (see  FIG. 2A ). 
     When the input signal Sin 1  is high, and the input signal Sin 2  is switched from low to high, the pulse generation portion  1  generates three pulses at the predetermined period and incorporates the three pulses in the transmission signal Str 3  (see  FIG. 2A ). On the other hand, when the input signal Sin 1  is high, and the input signal Sin 2  is switched from high to low, the pulse generation portion  1  generates three pulses at the predetermined period and incorporates the three pulses in the transmission signal Str 1  (see  FIG. 2A ). 
     While the pulse generation portion  1  detects the switching of the logic of the input signal Sin 1 , and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the logic of the input signal Sin 2 , the pulse generation portion  1  stops the generation of the three pulses resulting from the former detection partway, and performs the generation of the three pulses resulting from the latter detection. In this way, even when the logic of the input signal Sin 2  is switched immediately after the switching of the logic of the input signal Sin 1 , it is possible to incorporate the pulses in only one of the four transmission signals Str 1  to Str 4  at the same time. 
       FIG. 2B  shows an operation while the pulse generation portion  1  detects the switching of the input signal Sin 1  from low to high, and generates three pulses at the predetermined period when the pulse generation portion  1  detects the switching of the input signal Sin 2  from low to high. In the operation shown in  FIG. 2B , three pulses are not incorporated in the transmission signal Str 1  but one pulse is incorporated therein. However, the one pulse incorporated in the transmission signal Str 1  is input to the set input terminal (S) of the latch circuit  18 , and then three pulses incorporated in the transmission signal Str 2  are input thereto. 
     The pulse generation portion  1  likewise stops the generation of the three pulses resulting from the former detection partway, and performs the generation of three pulses resulting from the latter detection even in the following cases of (1) to (7): 
     (1) while the pulse generation portion  1  detects the switching of the input signal Sin 2  from low to high, and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the input signal Sin 1  from low to high; 
     (2) while the pulse generation portion  1  detects the switching of the input signal Sin 1  from high to low, and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the input signal Sin 2  from high to low; 
     (3) while the pulse generation portion  1  detects the switching of the input signal Sin 2  from high to low, and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the input signal Sin 1  from high to low; 
     (4) while the pulse generation portion  1  detects the switching of the input signal Sin 1  from low to high, and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the input signal Sin 2  from high to low; 
     (5) while the pulse generation portion  1  detects the switching of the input signal Sin 2  from low to high, and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the input signal Sin 1  from high to low; 
     (6) while the pulse generation portion  1  detects the switching of the input signal Sin 1  from high to low, and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the input signal Sin 2  from low to high; and 
     (7) while the pulse generation portion  1  detects the switching of the input signal Sin 2  from high to low, and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the input signal Sin 1  from low to high. 
     The pulse generation portion  1  respectively outputs the four transmission signals Str 1  to Str 4  to first to fourth transmission portions. 
     The transmission signal Str 1  is transmitted by the first transmission portion to the first input terminal of the OR gate  14  and the first input terminal of the OR gate  16 . The first transmission portion is formed with the excitation circuit  2 , the pulse transformer  6  and the pulse detection portion  10 . 
     The transmission signal Str 2  is transmitted by the second transmission portion to the first input terminal of the OR gate  15  and the second input terminal of the OR gate  16 . The second transmission portion is formed with the excitation circuit  3 , the pulse transformer  7  and the pulse detection portion  11 . 
     The transmission signal Str 3  is transmitted by the third transmission portion to the second input terminal of the OR gate  14  and the first input terminal of the OR gate  17 . The third transmission portion is formed with the excitation circuit  4 , the pulse transformer  8  and the pulse detection portion  12 . 
     The transmission signal Str 4  is transmitted by the fourth transmission portion to the second input terminal of the OR gate  15  and the second input terminal of the OR gate  17 . The fourth transmission portion is formed with the excitation circuit  5 , the pulse transformer  9  and the pulse detection portion  13 . 
     The excitation circuits  2  to  5  respectively excite the pulse transformers  6  to  9  based on the transmission signals Str 1  to Str 4 . The pulse detection portions  10  to  13  respectively detect pulses output from the secondary sides of the pulse transformers  6  to  9 . The first to fourth transmission portions respectively transmit the transmission signals Str 1  to Str 4  while electrically insulating an input side and an output side with the pulse transformers  6  to  9 . 
     The output of the OR gate  14  is transmitted to the set input terminal (S) of the latch circuit  18 , and the output of the OR gate  15  is transmitted to the reset input terminal (R) of the latch circuit  18 . The latch circuit  18  outputs an output signal Sout 1  from an output terminal (Q). When the pulse is input to the set input terminal (S), the latch circuit  18  turns the output signal Sout 1  high. On the other hand, when the pulse is input to the reset input terminal (R), the latch circuit  18  turns the output signal Sout 1  low. The output signal Sout 1  becomes a signal which indicates the input signal Sin 1  (see  FIG. 2A ). 
     The output of the OR gate  16  is transmitted to the reset input terminal (R) of the latch circuit  19 , and the output of the OR gate  17  is transmitted to the set input terminal (S) of the latch circuit  19 . The latch circuit  19  outputs an output signal Sout 2  from the output terminal (Q). When the pulse is input to the set input terminal (S), the latch circuit  19  turns the output signal Sout 2  high. On the other hand, when the pulse is input to the reset input terminal (R), the latch circuit  19  turns the output signal Sout 2  low. The output signal Sout 2  becomes a signal which indicates the input signal Sin 2  (see  FIG. 2A ). 
     The signal transmission circuit shown in  FIG. 1  incorporates the pulses in only one of the four transmission signals Str 1  to Str 4  at the same time, and thus it is possible to reduce a variation in power supply voltage supplied to the signal transmission circuit shown in  FIG. 1 . In this way, the signal transmission circuit shown in  FIG. 1  itself or another circuit which shares the power supply voltage with the signal transmission circuit shown in  FIG. 1  can be prevented from being erroneously operated. 
     The signal transmission circuit shown in  FIG. 1  incorporates the pulses in only one of the four transmission signals Str 1  to Str 4  at the same time, and thus it is possible to reduce radiation noise from the signal transmission circuit shown in  FIG. 1 . In this way, the radiation noise from the signal transmission circuit shown in  FIG. 1  can be prevented from exceeding an allowable range. 
     Although in the present configuration example, when the logic of the input signal is switched, the pulse generation portion  1  generates, in principle, three pulses at the predetermined period, the number of pulses generated each time the logic of the input signal is switched may be at least one. When a plurality of pulses are generated each time the logic of the input signal is switched, the number of pulses generated is not limited to three, and may be two or four or more. Even when as in the present configuration example, a plurality of pulses are generated each time the logic of the input signal is switched, and thus the latch circuit cannot recognize the first pulse due to any failure, a failure is prevented from occurring in the signal transmission if the latch circuit can recognize any of the remaining pulses. 
     A configuration may be adopted in which a counter for the set input terminal (S) and a counter for the reset input terminal (R) are incorporated in each of the latch circuits  18  and  19 , and in which the signal transmission circuit shown in  FIG. 1  performs the operation shown in  FIG. 3A . 
     In the operation shown in  FIG. 3A , the latch circuit  18  turns the output signal Sout 1  high when two pulses are input to the set input terminal (S) whereas the latch circuit  18  turns the output signal Sout 1  low when two pulses are input to the reset input terminal (R). In the operation shown in  FIG. 3A , the latch circuit  19  turns the output signal Sout 2  high when two pulses are input to the set input terminal (S) whereas the latch circuit  19  turns the output signal Sout 2  low when two pulses are input to the reset input terminal (R) 
     As described previously, while the pulse generation portion  1  detects the switching of the logic of the input signal Sin 1 , and generates three pulses at the predetermined period, when the pulse generation portion  1  detects the switching of the logic of the input signal Sin 2 , the pulse generation portion  1  stops the generation of the three pulses resulting from the former detection partway, and performs the generation of the three pulses resulting from the latter detection. In this way, even when the logic of the input signal Sin 2  is switched immediately after the switching of the logic of the input signal Sin 1 , it is possible to incorporate the pulses in only one of the four transmission signals Str 1  to Str 4  at the same time. 
       FIG. 3B  shows an operation while the pulse generation portion  1  detects the switching of the input signal Sin 1  from low to high, and generates three pulses at the predetermined period when the pulse generation portion  1  detects the switching of the input signal Sin 2  from low to high. In the operation shown in  FIG. 3B , three pulses are not incorporated in the transmission signal Str 1  but one pulse is incorporated therein. However, the one pulse incorporated in the transmission signal Str 1  is input to the set input terminal (S) of the latch circuit  18 , and then three pulses incorporated in the transmission signal Str 2  are input thereto. Hence, when two pulses are input to the set input terminal (S) of the latch circuit  18 , the output signal Sout 1  is turned high. 
     When the counter for the set input terminal (S) and the counter for the reset input terminal (R) are incorporated in each of the latch circuits  18  and  19 , the number of pulses generated each time the logic of the input signal is switched may be at least two. However, the number of pulses generated each time the logic of the input signal is switched needs to be set equal to or more than the number of pulses necessary for setting and resetting the latch circuits  18  and  19 . When the number of pulses generated each time the logic of the input signal is switched is set more than the number of pulses necessary for setting and resetting the latch circuits  18  and  19 , even if the latch circuit cannot recognize any pulses due to any failure, a failure is prevented from occurring in the signal transmission if the latch circuit can recognize the number of pulses necessary for the setting and resetting. 
     Second Configuration Example 
       FIG. 4  is a diagram showing a second configuration example of the signal transmission circuit. In the signal transmission circuit of the present configuration example, a relay portion is added to the signal transmission circuit of the first configuration example. In the present configuration example, the description of the same portions as in the first configuration example will be omitted. 
     The relay portion is provided between the pulse detection portions  10  to  13  and the OR gates  14  to  17 . The relay portion is formed with NOR gates N 1  to N 4  and AND gates A 1  to A 4 . 
     The output of the pulse detection portion  11  is transmitted to the first input terminal of the NOR gate N 1 , the output of the pulse detection portion  12  is transmitted to the second input terminal of the NOR gate N 1  and the output of the pulse detection portion  13  is transmitted to the third input terminal of the NOR gate N 1 . The output of the pulse detection portion  10  is transmitted to the first input terminal of the AND gate A 1 , and the output of the NOR gate N 1  is transmitted to the second input terminal of the AND gate A 1 . The output of the AND gate A 1  is transmitted to the first input terminal of the OR gate  14  and the first input terminal of the OR gate  16 . Hence, when the pulses are incorporated in the transmission signal Str 1 , and at least one of the transmission signals Str 2  to Str 4  transmitted by the second to fourth transmission portions is turned high, the relay portion stops the transmission of the pulses incorporated in the transmission signal Str 1  to the OR gates  14  and  16 . 
     The output of the pulse detection portion  10  is transmitted to the first input terminal of the NOR gate N 2 , the output of the pulse detection portion  12  is transmitted to the second input terminal of the NOR gate N 2  and the output of the pulse detection portion  13  is transmitted to the third input terminal of the NOR gate N 2 . The output of the pulse detection portion  11  is transmitted to the first input terminal of the AND gate A 2 , and the output of the NOR gate N 2  is transmitted to the second input terminal of the AND gate A 2 . The output of the AND gate A 2  is transmitted to the first input terminal of the OR gate  15  and the second input terminal of the OR gate  16 . Hence, when the pulses are incorporated in the transmission signal Str 2 , and at least one of the transmission signals Str 1 , Str 3  and Str 4  respectively transmitted by the first, third and fourth transmission portions is turned high, the relay portion stops the transmission of the pulses incorporated in the transmission signal Str 2  to the OR gates  15  and  16 . 
     The output of the pulse detection portion  10  is transmitted to the first input terminal of the NOR gate N 3 , the output of the pulse detection portion  11  is transmitted to the second input terminal of the NOR gate N 3  and the output of the pulse detection portion  13  is transmitted to the third input terminal of the NOR gate N 3 . The output of the pulse detection portion  12  is transmitted to the first input terminal of the AND gate A 3 , and the output of the NOR gate N 3  is transmitted to the second input terminal of the AND gate A 3 . The output of the AND gate A 3  is transmitted to the first input terminal of the OR gate  14  and the first input terminal of the OR gate  17 . Hence, when the pulses are incorporated in the transmission signal Str 3 , and at least one of the transmission signals Str 1 , Str 2  and Str 4  respectively transmitted by the first, second and fourth transmission portions is turned high, the relay portion stops the transmission of the pulses incorporated in the transmission signal Str 3  to the OR gates  14  and  17 . 
     The output of the pulse detection portion  12  is transmitted to the first input terminal of the NOR gate N 4 , the output of the pulse detection portion  11  is transmitted to the second input terminal of the NOR gate N 4  and the output of the pulse detection portion  10  is transmitted to the third input terminal of the NOR gate N 4 . The output of the pulse detection portion  13  is transmitted to the first input terminal of the AND gate A 4 , and the output of the NOR gate N 4  is transmitted to the second input terminal of the AND gate A 4 . The output of the AND gate A 4  is transmitted to the second input terminal of the OR gate  15  and the second input terminal of the OR gate  17 . Hence, when the pulses are incorporated in the transmission signal Str 4 , and at least one of the transmission signals Str 1  to Str 3  respectively transmitted by the first to third transmission portions is turned high, the relay portion stops the transmission of the pulses incorporated in the transmission signal Str 4  to the OR gates  15  and  17 . 
     As described above, when at least one of the transmission signals Str 1  to Str 4  is erroneously turned high due to noise or the like, the relay portion stops the transmission of the pulses incorporated in the transmission signals Str 1  to Str 4 , with the result that an erroneous signal is prevented from being transmitted. A configuration in which the NOR gate N 1  is not provided and in which any one of the outputs of the pulse detection portions  11  to  13  is transmitted to the second input terminal of the AND gate A 1  or a configuration in which instead of the NOR gate N 1  that is a three-input NOR gate, a two-input NOR gate is provided and in which any two of the outputs of the pulse detection portions  11  to  13  are transmitted to the two-input NOR gate may be adopted. The same variation can be performed on each of the NOR gates N 2  to N 4 . 
     Third Configuration Example 
       FIG. 5  is a diagram showing a third configuration example of the signal transmission circuit. In the signal transmission circuit of the present configuration example, a feedback circuit is added to the signal transmission circuit of the first configuration example. In the present configuration example, the description of the same portions as in the first configuration example will be omitted. 
     The feedback circuit is formed with a pulse generation portion  20 , excitation circuits  21  and  22 , pulse transformers  23  and  24 , pulse detection circuits  25  and  26  and a latch circuit  27 . 
     The pulse generation portion  20  detects the switching of the logic of the output signal Sout 1 , and generates pulses according to the result of the detection. The pulse generation portion  20  incorporates the pulses in only one of two feedback transmission signals Str 5  and Str 6  at the same time. 
     When the output signal Sout 1  is switched from low to high, the pulse generation portion  20  generates three pulses at the predetermined period and incorporates the three pulses in the feedback transmission signal Str 5  (see  FIG. 6 ). On the other hand, when the output signal Sout 1  is switched from high to low, the pulse generation portion  20  generates three pulses at the predetermined period and incorporates the three pulses in the feedback transmission signal Str 6  (see  FIG. 6 ). 
     The pulse generation portion  20  respectively outputs the two feedback transmission signals Str 5  and Str 6  to first and second feedback transmission portions. 
     The feedback transmission signal Str 5  is transmitted by the first feedback transmission portion to the set input terminal (S) of the latch circuit  27 . The first feedback transmission portion is formed with the excitation circuit  21 , the pulse transformer  23  and the pulse detection portion  25 . 
     The feedback transmission signal Str 6  is transmitted by the second feedback transmission portion to the reset input terminal (R) of the latch circuit  27 . The second feedback transmission portion is formed with the excitation circuit  22 , the pulse transformer  24  and the pulse detection portion  26 . 
     The excitation circuits  21  and  22  respectively excite the pulse transformers  23  and  24  based on the feedback transmission signals Str 5  and Str 6 . The pulse detection portions  25  and  26  respectively detect pulses output from the secondary sides of the pulse transformers  23  and  24 . The first and second feedback transmission portions respectively transmit the feedback transmission signals Str 5  and Str 6  while electrically insulting an input side and an output side with the pulse transformers  23  and  24 . 
     The latch circuit  27  outputs a feedback signal Sfb from the output terminal (Q). When the pulse is input to the set input terminal (S), the latch circuit  27  turns the feedback signal Sfb high. On the other hand, when the pulse is input to the reset input terminal (R), the latch circuit  27  turns the feedback signal Sfb low. 
     When no abnormality occurs in the transmission of the input signal Sin 1  and in the feedback transmission of the output signal Sout 1 , the feedback signal Sfb becomes a signal which indicates the input signal Sin 1  (see  FIG. 6 ). Hence, in the signal transmission circuit of the present configuration example, on the primary side of the pulse transformers  6  to  9  and the secondary side of the pulse transformers  23  and  24 , a relationship between the input signal Sin 1  and the feedback signal Sfb is checked, and thus it is possible to determine whether or not an abnormality occurs in the transmission of the input signal Sin 1 . 
     Although the pulse which switches the logic of the output signal Sout 1  is incorporated in any of the transmission signals Str 1  to Str 4 , the pulse incorporated in the transmission signals Str 1  to Str 4  is also a pulse which switches the logic of the output signal Sout 2  (see  FIG. 7 ). Hence, when as shown in  FIG. 6 , the period of the input signal Sin 1  is sufficiently shorter than that of the input signal Sin 2 , the relationship between the input signal Sin 1  and the feedback signal Sfb is checked, and thus it is possible not only to determine whether or not an abnormality occurs in the transmission of the input signal Sin 1  but also to determine whether or not an abnormality occurs in the transmission of the input signal Sin 2 . 
     In the signal transmission circuit of the present configuration example, the number of feedback circuits is restricted to one, and thus it is possible to minimize an increase in the variation of the power supply voltage and an increase in the radiation noise caused by the addition of the feedback circuit. 
     Fourth Configuration Example 
     Although in the signal transmission circuits of the first to third configuration examples described above, the two input signals Sin 1  and Sin 2  are transmitted, the number of input signals transmitted may be three or more. 
       FIG. 8  is a diagram showing a fourth configuration example of the signal transmission circuit.  FIGS. 9A to 9L  are timing charts showing examples of the operation of the signal transmission circuit in the present configuration example. The signal transmission circuit of the present configuration example is a circuit for transmitting the input signals Sin 1  to Sin 3 . 
     When the signal transmission circuits of the first to fourth configuration examples are generalized, a signal transmission circuit is provided which transmits N (N is a natural number of 2 or more) input signals, which includes: a transmission signal generation portion arranged to generate 2 N  transmission signals according to the N input signals; 2 N  transmission portions arranged respectively to transmit the 2 N  transmission signals output from the transmission signal generation portion while performing electrical insulation; and an output portion arranged to generate and output, based on the 2 N  transmission signals transmitted by the 2 N  transmission portions, N output signals that respectively indicate the N input signals and in which the transmission signal generation portion generates a pulse according to the N input signals and incorporates the pulse in only one of the 2 N  transmission signals at the same time. 
     Application Example of Signal Transmission Circuit 
     The signal transmission circuit described above can be used as, for example, part of a motor drive system which is incorporated in a vehicle X 1  shown in  FIG. 10 .  FIG. 11  is a diagram showing an example of a schematic configuration of the motor drive system incorporated in the vehicle X 1 . 
     The motor drive system shown in  FIG. 11  includes a control device Y 1 , signal transmission portions Y 41  to Y 46 , drive portions Y 71  to Y 76  and a three-phase motor Y 2 . 
     The control device Y 1  generates drive signals DRV 1  to DRV 6  for driving the motor Y 2  and temperature select signals TSEL 1  to TSEL 6 . 
     The signal transmission portion Y 41  includes a two-input two-output signal transmission circuit Y 11 , a one-input one-output signal transmission circuit Y 21  and a switch Y 31 . As the two-input two-output signal transmission circuit Y 11 , for example, the signal transmission circuit of the first configuration example shown in  FIG. 1  can be used. As the one-input one-output signal transmission circuit Y 21 , for example, the signal transmission circuit shown in  FIG. 12  can be used. The two-input two-output signal transmission circuit Y 11  transmits the drive signal DRV 1  to the drive portion Y 71 , and transmits the temperature select signal TSEL 1  to the switch Y 31 . The switch Y 31  inputs pieces of temperature information TINF 1 A and TINF 1 B output from the drive portion Y 71 . The switch Y 31  supplies, to the one-input one-output signal transmission circuit Y 21 , as a temperature input signal TIN 1 , any one of the pieces of temperature information TINF 1 A and TINF 1 B according to the temperature select signal TSEL 1 . The one-input one-output signal transmission circuit Y 21  inputs the temperature input signal TIN 1  output from the switch Y 31 , and transmits it to the control device Y 1 . The signal transmission portions Y 42  to Y 46  also have the same configuration as the signal transmission portion Y 41 . 
     The drive portion Y 71  includes insulated gate bipolar transistors (hereinafter referred to as “transistors” in short) Y 51 A and Y 51 B and temperature sensors Y 61 A and Y 61 B. The temperature sensor Y 61 A is arranged in the vicinity of the transistor Y 51 A, and the temperature sensor Y 61 B is arranged in the vicinity of the transistor Y 51 B. The temperature sensor Y 61 A outputs the temperature information TINF 1 A which is the temperature information on the transistor Y 51 A, and the temperature sensor Y 61 B outputs the temperature information TINF 1 B which is the temperature information on the transistor Y 51 B. A constant voltage Vcc is applied to the collectors of the transistors Y 51 A and Y 51 B. The drive signal DRV 1  is supplied to the bases of the transistors Y 51 A and Y 51 B. The U-phase winding of the motor Y 2  is connected to the emitters of the transistors Y 51 A and Y 51 B. The drive portions Y 72  to Y 76  also have the same configuration as the drive portion Y 71 . The collectors and emitters of the drive portions Y 72  to Y 76  are in a connection state below. The constant voltage Vcc is applied to the collectors of the drive portions Y 73  and Y 75 . The emitters of the drive portions Y 72 , Y 74  and Y 76  are grounded. The U-phase winding of the motor Y 2  is connected to the collector of the drive portion Y 72 . The V-phase winding of the motor Y 2  is connected to the emitter of the drive portion Y 75  and the collector of the drive portion Y 74 . The W-phase winding of the motor Y 2  is connected to the emitter of the drive portion Y 75  and the collector of the drive portion Y 76 . 
     Preferably, for example, when as the signal transmission circuit Y 11 , the signal transmission circuit of the third configuration example shown in  FIG. 5  is used, the control device Y 1  checks a relationship between the drive signal DRV 1  and the feedback signal Sfb so as to determine whether or not an abnormality occurs in the transmission of the drive signal DRV 1  and the temperature select signal TSEL 1 . 
     Points of Attention 
     In various technical features disclosed in the present specification, in addition to the embodiment described above, various modifications can be added without departing from the spirit of its technical creation. 
     For example, although in the embodiment described above, as insulating elements provided in the transmission portions and the feedback transmission portions, the pulse transformers are used, insulting elements other than the pulse transformers may be used. For example, instead of the pulse transformers, photocouplers can be used. When photocouplers are used, the excitation circuits may be removed or may be replaced with amplification circuits or the like. For example, instead of the pulse transformers, capacitors can be used. When capacitors are used, instead of the excitation circuits, discharge circuits or the like are preferably provided. 
     For example, various types of variations in the first configuration example may be applied to the other configuration examples. The same modification as the modification from the first configuration example to the second configuration example may be performed on the third and fourth configuration examples. The same modification as the modification from the first configuration example to the third configuration example may be performed on the fourth configuration example. 
     In other words, the embodiment discussed above should be considered to be illustrative in all respects and not restrictive, the technical range of the present invention is indicated not by the description of the embodiment discussed above but by the scope of claims and it should be understood that meanings equivalent to the scope of claims and all modifications belonging to the scope are included. 
     Overview 
     The signal transmission circuit described above transmits N (N is a natural number of 2 or more) input signals, and includes: a transmission signal generation portion arranged to generate 2 N  transmission signals according to the N input signals; 2 N  transmission portions arranged respectively to transmit the 2 N  transmission signals output from the transmission signal generation portion while performing electrical insulation; and an output portion arranged to generate and output, based on the 2 N  transmission signals transmitted by the 2 N  transmission portions, N output signals that respectively indicate the N input signals, and the transmission signal generation portion generates a pulse according to the N input signals and incorporates the pulse in only one of the 2 N  transmission signals at the same time (first configuration). 
     In the signal transmission circuit of the first configuration, the output portion may include 2N OR gates having 2 N−1  input terminals and N latch circuits, and each of the N latch circuits may be operated based on the outputs of two of the OR gates which are connected to the input terminal of the latch circuit (second configuration). 
     In the signal transmission circuit of the first or second configuration, when the transmission signal generation portion detects the switching of the logic of one of the N input signals, the transmission signal generation portion may generate the pulse, and determine, according to the signal whose logic is switched, the direction of the switching of the logic and the logic of each of the (N−1) input signals other than the signal whose logic is switched, in which signal the pulse is incorporated (third configuration). 
     In the signal transmission circuit of any one of the first to third configurations, each time the transmission signal generation portion detects the switching of the logic of one of the N input signals, the transmission signal generation portion may generate the M (M is a natural number of 2 or more) pulses at a predetermined period (fourth configuration). 
     In the signal transmission circuit of the fourth configuration, while the transmission signal generation portion detects the switching of the logic of one of the N input signals, and generates the M (M is a natural number of 2 or more) pulses at the predetermined period, when the transmission signal generation portion detects the switching of the logic of one of the N input signals, the transmission signal generation portion may stop the generation of the M pulses resulting from the former detection partway, and perform generation of the M pulses resulting from the latter detection (fifth configuration). 
     The signal transmission circuit of any one of the first to fifth configurations may further include: a relay portion which is provided between the 2 N  transmission portions and the output portion, and when the pulse is incorporated in one of the 2 N  transmission signals transmitted by the 2 N  transmission portions, and at least one of the remaining signals among the 2 N  transmission signals transmitted by the 2 N  transmission portions has the same logic as the pulse, the relay portion may stop the transmission of the pulse to the output portion (sixth configuration). 
     The signal transmission circuit of any one of the first to sixth configurations may further include: only one feedback transmission signal generation portion arranged to generate two feedback transmission signals according to one of the N output signals; only two feedback transmission portions arranged respectively to transmit the two feedback transmission signals output from the feedback transmission signal generation portion while performing electrical insulation; and only one feedback output portion arranged to generate and output a feedback signal indicating one of the N output signals based on the two feedback transmission signals transmitted by the two feedback transmission portions (seventh configuration). 
     In the signal transmission circuit of the seventh configuration, the feedback transmission signal generation portion may generate the two feedback transmission signals according to the output signal indicating a signal among the N input signals whose period is shortest (eighth configuration). 
     The vehicle described above includes the signal transmission circuit of any one of the first to eighth configurations (ninth configuration).