Patent Publication Number: US-10325907-B2

Title: Substrate isolation for low-loss radio frequency (RF) circuits

Description:
RELATED APPLICATION 
     The present application is a divisional of U.S. patent application Ser. No. 15/658,252 entitled “Improved Substrate Isolation For Low-Los Radio Frequency (RF) Circuits”, filed on Jul. 24, 2017, which is a continuation-in-part of U.S. patent application Ser. No. 15/588,011, entitled “Linearity And Lateral Isolation In A BiCMOS Process Through Center-Doping Of Epitaxial Silicon Region”, filed on May 5, 2017. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the formation of a grid of deep trench isolation regions in a semiconductor process in order to improve performance of devices fabricated using this process. 
     RELATED ART 
       FIG. 1  is a block diagram of a conventional dual-band wireless communication device  100  that includes antenna  101 , diplexer  102 , front end module (FEM)  110  and wireless transceiver  130 . Front end module  110  includes radio frequency (RF) switches  111 - 112 , low-noise amplifiers (LNAs)  113 - 114 , power amplifiers  115 - 116 , output impedance matching networks (OMNs)  117 - 118  and bias/control circuits  121 - 123 . Wireless transceiver  130  includes a Bluetooth port  131 , 2.4 GHz receive port  132 , a 2.4 GHz transmit port  133 , a 5 GHz transmit port  134  and a 5GHz receive port  135 . RF switch  111  has a first position that couples antenna  101  to Bluetooth port  131 , a second position that couples antenna  101  to the 2.4 GHz receive port  132  (through LNA  113 ) and a third position that couples antenna  101  to the 2.4 GHz transmit port  133  (through power amplifier  115  and OMN  117 ). RF switch  112  has a first position that couples antenna  101  to the 5 GHz transmit port  134  (through power amplifier  116  and OMN  118 ) and a second position that couples antenna  101  to the 5 GHz receive port  135  (through LNA  114 ). LNAs  113  and  114  are controlled by bias/control circuits  121 - 122 , respectively. Power amplifiers  115 - 116  are controlled by bias/control circuit  123 . 
     It is desirable for all of the elements of FEM  110  to be integrated on a single chip in order to reduce system size, cost and complexity. However, this is difficult to accomplish due to the cost and performance requirements of the different elements of FEM  110 . For example, while a silicon-on-insulator (SOI) CMOS process technology allows for the fabrication of CMOS FETS that are well suited to implement RF switches  111 - 112 , LNAs  113 - 114  and the digital bias/control circuits  121 - 123 , these CMOS FETs are not capable of adequately implementing power amplifiers  115 - 116 . Conversely, a process technology that is well suited for the fabrication of power amplifiers  115 - 116  is not optimal for fabricating RF switches  111 - 112 , LNAs  113 - 114  and bias/control circuits  121 - 123 . As a result, FEM  110  is typically implemented as a multi-chip module that combines a plurality of integrated circuits fabricated using different process technologies. 
     SiGe BiCMOS process technology has been used to achieve higher levels of integration for FEM  110 . Heterojunction bipolar transistors (HBTs) fabricated using a SiGe BiCMOS process are well suited for implementing the power amplifiers  115 - 116  of FEM  110 . The SiGe BiCMOS process also allows for the fabrication of CMOS transistors and passive devices (e.g., metal-insulator-metal (MIM) devices) that can be used to implement RF switches  111 - 112 , LNAs  113 - 114 , OMNs  117 - 118  and bias/control circuits  121 - 123 . As a result, the entire FEM  110  can be integrated on a single chip. 
     As illustrated in  FIG. 1 , the RF switches  111 - 112  are in the signal path between the antenna  101  and the LNAs  113 - 114  and power amplifiers  115 - 116 . RF signal propagation to the semiconductor substrate will degrade all metrics of the RF switches  111 - 112 . More specifically, parasitic coupling to the substrate will: (a) increase insertion loss of the RF switches  111 - 112  (thereby reducing power transmitted to the antenna  101  and received at ports  132  and  135 ); (b) reduce isolation of the RF switches  111 - 112 ; (c) degrade the linearity of the RF switches; and (d) reduce the power handling capabilities of the RF switches  111 - 112  (by introducing voltage imbalances across the series-connected CMOS transistors of the RF switches  111 - 112 ). 
     A high-resistivity substrate has been used with the SiGe BiCMOS process to reduce substrate losses associated with RF switches  111 - 112  (and passive devices) fabricated on the same chip as the SiGe HBTs.  FIGS. 2A and 2B  are cross sectional views of a multi-finger field effect transistor  111 A used to implement the RF switch  111  of FEM  110 , when fabricated in accordance with a conventional SiGe BiCMOS process on a high-resistivity (HR) p-type substrate  201 . High-resistivity substrate  201  is monocrystalline silicon having a resistivity that is typically greater than 500 Ω-cm. 
     RF switch  111  includes a plurality of series-connected n-channel FET transistors  211 - 214 , which are fabricated in a p-well region  215 . P-well region  215  is laterally bounded by n-type regions  216 - 217 . A deep n-well (DNW)  220  is located below p-well region  215  (and is continuous with n-type regions  216 - 217 ). Thus, triple-well isolation is provided with the SiGe BiCMOS process to reduce substrate losses associated with RF switches  111 - 112  (and passive devices) fabricated on the same chip as the SiGe HBTs. In this triple-well structure, n-channel transistors  211 - 214  are formed within the p-type well region  215 , which in turn, is encompassed by the n-type regions  216 - 217  and deep n-well  220 . The n-type regions  216 - 217  and deep n-well  220  are surrounded by the p-type background doping of the starting silicon substrate  201 . This method electrically isolates the inner p-well region  215  from the p-type substrate  201  by design, since the p-n junctions formed with the intermediate n-well regions  216 - 217  and  220  are biased in a minimally conducting state. 
     Shallow trench isolation (STI) regions  231 - 235  and deep trench isolation (DTI) regions  241 - 242  provide electrical isolation to RF switch  111  (and other circuit elements fabricated in high-resistivity substrate  201 ). To form DTI regions  241 - 242 , deep trenches are etched into the silicon substrate  201 , extending at least several microns beyond the depth of the active devices. These deep trenches are filled with an insulating material, thereby forming DTI regions  241 - 242 . When a device is surrounded by DTI regions, the device is dielectrically isolated from neighboring devices. Signals can couple vertically down into the substrate and under the DTI regions, but the relatively large depth of the deep trench minimizes this effect. Additional isolation can be achieved by forming multiple rings of DTI regions. Passive elements such as inductors and transmission lines can also achieve higher quality factors by placing a grid of deep trench isolation regions underneath to impede eddy currents in the substrate. 
     In addition, the high-resistivity substrate  201  provides high-impedance paths  251 - 252 , which reduce substrate losses. 
     However, as illustrated in  FIGS. 2A and 2B , certain semiconductor regions located adjacent to RF switch  111  provide low resistance paths  253  and  254  near the upper surface of the substrate  201 . 
     For example, as illustrated by  FIG. 2A , a p-well region  260  (formed at the same time as p-well region  215  during the SiGe BiCMOS process) may be located at the upper surface of the substrate  201 . Note that other CMOS transistors (not shown) may be fabricated in the p-well region  260 , or p-well region  260  may simply represent a region that exists between devices. P-well region  260  provides a low resistance current path  253  at the upper surface of the substrate, which undesirably increases substrate losses, and degrades the performance of RF switch  111  in the manner described above. For example, p-well region  260  may have a resistivity of about 0.1 Ω-cm (corresponding to a lateral sheet resistance of about 1 KΩ/square), which is significantly lower than the resistivity of substrate  201 . The dashed line in  FIG. 2A  illustrates a current path associated with the substrate losses. 
     As illustrated by  FIG. 2B , an n-type epitaxial layer  270 , (which is used to form collector regions of NPN SiGe HBTs fabricated on substrate  201  in accordance with the SiGe BiCMOS process) may be located at the upper surface of the substrate. Note that this n-type epitaxial layer  270  may represent an inactive region that exists between devices. N-type epitaxial layer  270  provides a low resistance path  254  at the upper surface of the substrate, which undesirably increases substrate losses, and degrades the performance of RF switch  111  in the manner described above. For example, n-type epitaxial layer  270  may have a resistivity of about 0.4 Ω-cm (corresponding to a lateral sheet resistance of about 4 KΩ/square), which is significantly lower than the resistivity of HR substrate  201 . The dashed line in  FIG. 2B  illustrates a current path associated with the substrate losses. In addition, the non-linear p-n junction that exists between HR substrate  201  and n-type epitaxial layer  270  can contribute significantly to total RF circuit non-linearity (including adding non-linearity to the operation of RF switch  111 ). 
     It would therefore be desirable to have an improved structure and method for isolating devices in an integrated FEM fabricated using a SiGe BiCMOS process. It would further be desirable if one or more of these improved structures and methods were compatible with conventional CMOS processes. It would be further desirable for such a structure and method to reduce substrate losses and eliminate non-linearities present in conventional structures. 
     SUMMARY 
     Accordingly, the present invention provides a modified SiGe BiCMOS process (or alternately, a modified CMOS process), wherein an isolation region is formed in a semiconductor substrate. The isolation region includes one or more shallow trench isolation (STI) regions, wherein one or more dummy active semiconductor regions are exposed through the STI regions at an upper surface of the substrate. A grid of deep trench isolation (DTI) regions extends through the STI regions and into the semiconductor substrate. The grid of DTI regions includes a pattern having T-shaped or Y-shaped intersections (and not cross-shaped intersections), which enable the DTI regions to be reliably fabricated. In one embodiment, the grid of DTI regions includes a plurality of polygonal openings, wherein each of these openings laterally surrounds one of the dummy active semiconductor regions. The polygonal openings can be, for example, square or hexagonal. The layout area of the polygonal openings defined by the grid of DTI regions is substantially larger than the layout area of the corresponding dummy active semiconductor regions. In a particular embodiment, the layout area of each polygonal opening is about 100 times the layout area of each dummy active semiconductor region. 
     In accordance with another embodiment, the isolation region further includes silicide blocking structures located over the dummy active semiconductor regions. 
     The isolation region of the present invention can be used to isolate other active devices fabricated on the semiconductor substrate. Examples of such active devices include, but are not limited to a radio frequency (RF) switch that includes a plurality of series-connected CMOS transistors. Other isolation techniques, such as triple-well isolation and high-resistivity semiconductor regions, can be easily used in combination with the isolation region of the present invention. 
     The present invention also includes a method for forming an isolation region including: forming one or more shallow trench isolation (STI) regions in a first semiconductor region located over a semiconductor substrate, wherein dummy active regions of the first semiconductor region extend through the one or more STI regions to an upper surface of the first semiconductor region, and forming a grid of deep trench isolation (DTI) regions in the first semiconductor region, wherein the grid of DTI regions extends entirely through the first semiconductor region, and wherein the grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. In one embodiment, the pattern includes a plurality of polygonal openings, wherein each of the polygonal openings laterally surrounds one of the dummy active regions. 
     In accordance with another embodiment, the STI regions are formed by performing a chemical mechanical polishing (CMP) process that exposes the dummy active regions through the one or more STI regions. In another embodiment, a silicide blocking structure is formed over each of the dummy active regions, thereby preventing the formation of metal silicide over these regions. 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a conventional dual-band wireless communication device. 
         FIGS. 2A and 2B  are cross sectional views of a multi-finger field effect transistor used to implement a radio frequency (RF) switch of the front end module of  FIG. 1 , when fabricated in accordance with a conventional SiGe BiCMOS process on a high-resistivity (HR) p-type substrate. 
         FIG. 3A  is a cross sectional representation of a semiconductor structure fabricated using a modified SiGe BiCMOS process in accordance with one embodiment of the present invention. 
         FIG. 3B  is a top view of a portion of an isolation region of the semiconductor structure of  FIG. 3A  in accordance with one embodiment of the present invention. 
         FIG. 3C  is a cross sectional representation of a semiconductor structure fabricated using a modified SiGe BiCMOS process in accordance with an alternate embodiment of the present invention. 
         FIG. 3D  is a top view of a portion of an isolation region of the semiconductor structure of  FIG. 3C  in accordance with one embodiment of the present invention. 
         FIG. 3E  is a cross sectional representation of a semiconductor structure fabricated using a modified SiGe BiCMOS process in accordance with another embodiment of the present invention. 
         FIG. 3F  is a top view of a portion of an isolation region of the semiconductor structure of  FIG. 3F  in accordance with one embodiment of the present invention. 
         FIG. 4  is a graph illustrating insertion loss versus signal frequency for various isolation structures, including the isolation structure of  FIGS. 3A-3B . 
         FIGS. 5A, 5B, 5C, 5D, 5E, 5F and 5G  are cross sectional views of the semiconductor structure of  FIGS. 3A and 3B , during various stages of the modified SiGe BiCMOS process of the present invention. 
         FIG. 6A  is a cross sectional representation of a semiconductor structure fabricated using a modified SiGe BiCMOS process in accordance with an alternate embodiment of the present invention. 
         FIG. 6B  is a top view of a portion of an isolation region of the semiconductor structure of  FIG. 6A  in accordance with one embodiment of the present invention. 
         FIG. 6C  is a top view of a portion of an isolation region of the semiconductor structures of  FIGS. 3A and 6A  in accordance with an alternate embodiment of the present invention. 
         FIG. 6D  is a cross sectional representation of a semiconductor structure fabricated using a modified SiGe BiCMOS process in accordance with an alternate embodiment of the present invention. 
         FIG. 6E  is a top view of a portion of an isolation region of the semiconductor structure of  FIG. 6D  in accordance with one embodiment of the present invention. 
         FIG. 6F  is a cross sectional representation of a semiconductor structure fabricated using a modified SiGe BiCMOS process in accordance with another embodiment of the present invention. 
         FIG. 6G  is a top view of a portion of an isolation region of the semiconductor structure of  FIG. 3F  in accordance with one embodiment of the present invention. 
         FIGS. 7A, 7B, 7C and 7D  are cross sectional views of the semiconductor structure of  FIGS. 6A and 6B , during various stages of the modified SiGe BiCMOS process of the present invention. 
         FIG. 8  is a cross section representation of a semiconductor structure in accordance with an alternate embodiment of the present invention 
     
    
    
     DETAILED DESCRIPTION 
     In general, the present invention uses a grid of deep trench isolation (DTI) regions to isolate active devices fabricated in a semiconductor substrate. The grid of DTI regions also isolates the semiconductor substrate from passive devices fabricated over the semiconductor substrate. In one embodiment, the grid of DTI regions isolates active and passive devices fabricated in accordance with a CMOS process. In another embodiment, the grid of DTI regions isolates active and passive devices fabricated in accordance with a SiGe BiCMOS process. In this embodiment, isolation provided by the grid of DTI regions largely mitigates the parasitic low-impedance path normally provided by the epitaxial layer of the SiGe BiCMOS process, effectively restoring the benefits of the high-resistivity substrate. The present invention will now be described in more detail. 
       FIG. 3A  is a cross sectional representation of a semiconductor structure  300  in accordance with one embodiment of the present invention. Semiconductor structure  300  is fabricated in accordance with a modified SiGe BiCMOS process in a manner described in more detail below. Semiconductor structure  300  includes an RF switch transistor  310 , an isolation region  320 , a 1.8V/5V CMOS transistor region  330  and an HBT region  340 , which are fabricated on a high resistivity (HR) p-type semiconductor substrate  301 . In one embodiment, p-type substrate  301  has a resistivity of about 500 Ω-cm or more. In one embodiment of the present invention, semiconductor structure  300  is used to implement an integrated FEM, which includes elements similar to those described above for FEM  110  ( FIG. 1 ). That is, the RF switches  111 - 112  of FEM  110  can be implemented by structures corresponding with RF switch transistor  310 . LNAs  113 - 114  and bias/control circuits  121 - 123  can be implemented with 1.8V and/or 5V CMOS transistors corresponding with those found in CMOS transistor region  330 . Power amplifiers  115 - 116  can be implemented with SiGe HBTs corresponding with those found in HBT region  340 . Output impedance matching networks  117 - 118  can be implemented with resistors, capacitors, inductors and transmission lines (e.g., passive devices) fabricated over the structure of  FIG. 3A . Structures similar to that found in isolation region  320  can be used to electrically isolate the various devices fabricated in substrate  301 , as well as to electrically isolate the passive devices fabricated over the substrate  301  from the underlying substrate  301 . Note that the passive devices benefit from the presence of an underlying high impedance substrate, whereby eddy currents induced in the underlying substrate are reduced, thereby enabling higher quality (lower loss) passive devices. 
     RF switch transistor  310  includes n-channel CMOS transistor structures  311 - 314 , which are fabricated in a p-well  315 , which in turn, is located in a deep n-well (DNW)  318 . N-well regions  316 - 317  provide electrical contact from the upper surface to the deep n-well  318 , as well as providing lateral junction isolation. RF switch transistor  310  is electrically isolated from adjacent circuitry by shallow trench isolation (STI) regions  351 - 352  and deep trench isolation (DTI) regions  361 - 362 . Although RF switch transistor  310  is illustrated with four transistor structures  311 - 314 , it is understood that other numbers of transistor structures can be used to implement RF switch transistor  310  in other embodiments. Moreover, although one RF switch transistor  310  is illustrated, it is understood that a plurality of RF switch transistors, identical to RF switch transistor  310 , are typically connected in series to form an RF switch. In this case, each of the series-connected RF transistors can be completely separate and bordered by independent rings of deep trench isolation structures, or as adjacent transistors isolated by a common deep trench isolation structure. In addition, it is understood that other circuitry commonly associated with RF switch transistor  310  is not shown in  FIG. 3A  for clarity. 
     Isolation region  320  provides electrical isolation between various elements fabricated on high resistance substrate  301 . In the illustrated embodiment, isolation region  320  provides isolation between RF switch transistor  310  and other circuit elements of semiconductor structure  300 . Isolation region  320  includes shallow trench isolation regions  352 - 355 , deep trench isolation regions  362 - 365 , p−-type regions  554 - 556 , n-type epitaxial regions  573 - 575  and silicide blocking structures  583 - 585 .  FIG. 3B  is a top view of isolation region  320 , which shows that the deep trench isolation regions  362 - 365 , along with deep trench isolation regions  371 - 378 , are configured to form a staggered grid pattern  360 , when viewed from above. In this staggered grid pattern  360 , the deep trench isolation regions  362 - 365  and  371 - 378  are joined at T-shaped intersections, but no cross (+) shaped intersections. For example, T-shaped intersection  370  is formed at the intersection of ‘vertical’ DTI region  364  and ‘horizontal’ DTI region  372 . In one embodiment, each of the openings in the grid  360  defined by the deep trench isolation regions  362 - 365  and  371 - 378  has dimensions of about 10 microns by 10 microns. That is, each of the p−-type regions  555 - 556  has dimensions of about 10 microns by 10 microns. Although STI regions  352 - 355  are not explicitly shown in  FIG. 3B , it is understood that these STI regions exist everywhere within the grid of  FIG. 3B , except for where the n-epi regions  573 - 575  (e.g., dummy active regions) are exposed at the upper surface of the substrate. The openings in the STI regions  352 - 355  (where the n-epi regions  573 - 575  are located) exist to provide adequate structural strength to the isolation region  320  due to limitations in the fabrication process. More specifically, the dummy active regions  573 - 575  prevent the adjacent active regions (e.g., n-type epitaxial regions  572  and  576 - 580  in  FIG. 5E , below) from being over-polished and damaged during a chemical mechanical polishing (CMP) step used to form the STI regions  351 - 359 . A regular occurrence of active regions helps the CMP pad polish in a uniform manner over the entire upper surface of the semiconductor structure while forming the STI regions  351 - 359 . In one embodiment, each of the openings in the STI regions  352 - 355  (i.e., each of the dummy active regions  573 - 575 ) has dimensions of about 1 micron by 1 micron, such that the area of each of the n-type dummy active regions  573 - 575  is about 1/100 of the area of the associated DTI grid opening. In accordance with one embodiment, silicide blocking structures  583 - 585  (which may be formed by a dielectric material such as silicon nitride), are formed over the n-type dummy active regions  573 - 575 , thereby preventing the formation of metal silicide over these regions. 
     The 1.8V/5V CMOS transistor region  330  includes conventional CMOS transistors  331 - 332 , which can be designed to have operating voltages of either 1.8 Volts or 5 Volts. Although CMOS transistors having specific operating voltages are described in the present examples, it is understood that other embodiments can include CMOS transistors having other operating voltages (e.g., 2.5 Volts, 3.3 Volts) in various combinations. CMOS transistor  331  is an n-channel FET that is fabricated in p-well  333 . CMOS transistor  332  is a p-channel FET that is fabricated in n-well  334  (which is located in p-well  333 ). Transistor region  330  is isolated from devices in the other regions  310 ,  320  and  340  of semiconductor structure  300  by shallow trench isolation regions  355 - 357  and deep trench isolation regions  365 - 366 . Although only two transistors  331 - 332  are illustrated in transistor region  330 , it is understood that many more transistors may be fabricated in this region. In general, transistors fabricated in region  330  are used to implement the LNAs and bias/control circuits of the associated FEM. 
     Bipolar transistor region  340  includes a SiGe NPN heterojunction bipolar transistor (HBT)  341 . SiGe HBT  341  includes an n-type polysilicon emitter  342 , a p-type silicon-germanium base layer  343 , and a n-type silicon collector that includes n-type epitaxial silicon region  578 , N+ buried region  345  and N+ collector contact region  344 . As described in more detail below, p−-regions  560 - 562  (which are a byproduct of the creation of p−-regions  554 - 556 ) are located adjacent to the collector regions  344 - 345  and  578 . Note that p−-regions  560 - 562  do not significantly affect the operation of SiGe HBT  341 . SiGe HBT  341  is isolated from the other regions  310 ,  320 ,  330  of semiconductor structure  300  by shallow trench isolation regions  357 - 359  and deep trench isolation regions  366 - 367 . 
     Although only one SiGe HBT transistor  341  is shown in bipolar transistor region  340 , it is understood that additional transistors can be fabricated in this region  340  (or other similar regions), and that the operating voltages of these transistors can be selected by design. For example, different bipolar transistors in region  340  can be designed have operating voltages of 6 Volts or 8 Volts. In general, the transistors fabricated in bipolar transistor region  340  are used to implement power amplifiers of an associated FEM. 
     As illustrated by  FIGS. 3A and 3B , the p−-regions  554 - 556  provide a relatively high resistance path near the upper surface of the substrate in the isolation region  320 . The n-epi regions  573 - 575  have a relatively small layout area compared with the p−-regions  554 - 556 . In the example described above, each of the n-epi regions  573 - 575  has a layout area that is about 1% of the layout area of the corresponding surrounding p−-region. As described in more detail below, the p−-regions  554 - 556  are very lightly doped, and therefore exhibit a relatively high sheet resistance of about 50 KΩ/square. Silicide blocking structures  583 - 585  prevent the formation of low resistance silicide on the upper surfaces of n-epi regions  573 - 575 . As a result, the combination of p−-regions  554 - 556  and n-epi regions  573 - 575  have a high net resistance at the upper surface of the substrate. The combination of the deep trench isolation regions  362 - 365  and the high-resistivity p−-regions  554 - 556  advantageously reduces the substrate losses of the semiconductor structure  300  (including the insertion losses in the RF switch  310 ). 
     In accordance with the present embodiment, n-epi regions  573 - 575  are dummy active regions (i.e., these regions  573 - 575  are defined at the same time as the active regions of semiconductor structure  300 , but no devices are fabricated in these regions  573 - 575 ). 
     Although isolation region  320  includes a grid of deep trench isolation regions  362 - 365  and  371 - 378  in the embodiment illustrated by  FIGS. 3A and 3B , it is possible to eliminate this grid in alternate embodiments.  FIG. 3C  is a cross sectional representation of a semiconductor structure  300 A having an isolation region  320 A that does not include a grid of deep trench isolation regions. Similar elements in semiconductor structure  300  ( FIG. 3A ) and semiconductor structure  300 A ( FIG. 3C ) are labeled with similar reference numbers. In the illustrated embodiment, isolation region  320 A provides isolation between RF switch transistor  310  and other circuit elements of semiconductor structure  300 A. Isolation region  320 A includes shallow trench isolation regions  352 - 355 , deep trench isolation regions  362 A and  365 A, p−-type region  555 A, n-type epitaxial regions  573 - 575  and silicide blocking structures  583 - 585 .  FIG. 3D  is a top view of isolation region  320 A, which includes the discrete deep trench isolation regions  362 A and  365 A, when viewed from above. Although STI regions  352 - 355  are not explicitly shown in  FIG. 3D , it is understood that these STI regions exist between deep trench isolation regions  362 A and  365 A, except for where the n-epi regions  573 - 575  are exposed at the upper surface of the substrate. As described above, the openings in the STI regions  352 - 355  (where the n-epi regions  573 - 575  are located) exist to provide structural strength to the isolation region  320 A, preventing adjacent active regions from being over-polished and damaged during the CMP step used to form the STI regions  351 - 359 . P−-type region  555 A is formed in the same manner as p−-type regions  554 - 556  ( FIGS. 3A-3B ). As a result, the p−-region  555 A is very lightly doped, and exhibits a relatively high sheet resistance of about 50 KΩ/square. As a result, the combination of p−-region  555 A and n-epi regions  573 - 575  advantageously exhibit a high net resistance at the upper surface of the substrate. 
       FIGS. 3E and 3F  illustrate another embodiment that eliminates the grid of deep trench isolation regions  362 - 365 .  FIG. 3E  is a cross sectional representation of a semiconductor structure  300 B having an isolation region  320 B that does not include a grid of deep trench isolation regions. Similar elements in semiconductor structure  300  ( FIG. 3A ) and semiconductor structure  300 B ( FIG. 3E ) are labeled with similar reference numbers. In the illustrated embodiment, isolation region  320 B provides isolation between RF switch transistor  310  and other circuit elements of semiconductor structure  300 B. Isolation region  320 B includes shallow trench isolation regions  352 B,  353 B and  354 B, deep trench isolation regions  362 A and  365 A, p−-type regions  554 B,  555 B and  556 B, n-type epitaxial regions  573 B and  574 B, and silicide blocking structures  583 B and  584 B.  FIG. 3F  is a top view of isolation region  320 B, which includes the discrete deep trench isolation regions  362 A and  365 A, which have been described above in connection with  FIGS. 3C and 3D . P−-regions  554 B and  556 B laterally surround deep trench isolation regions  362 A and  365 A, respectively. N-type epitaxial regions  573 B and  574 B laterally surround p−-regions  554 B and  556 B, respectively. P−-region  555 B is located between the n-type epitaxial regions  573 B- 574 B. The n-type epitaxial regions  573 B and  574 B provide structural strength to the isolation region  320 B, preventing adjacent active regions from being over-polished and damaged during the CMP step used to form the STI regions  351 ,  352 B,  353 B,  354 B and  356 - 560 . Silicide blocking structures  583 B and  584 B prevent the formation of metal silicide over N-type epitaxial regions  573 B and  574 B. Although STI regions  352 B,  353 B and  354 B are not explicitly shown in  FIG. 3F , it is understood that these STI regions are generally located over the p−-type regions  554 B,  555 B and  556 B, respectively. P−-type regions  554 B- 556 B are formed in the same manner as p−-type regions  554 - 556  ( FIGS. 3A-3B ). As a result, the p−-regions  554 B- 556 B are very lightly doped, and exhibit a relatively high sheet resistance of about 50 KΩ/square. Thus, the combination of p−-regions  554 B- 556 B, n-type epitaxial regions  573 B- 574 B and silicide blocking structures  583 B- 584 B advantageously exhibit a high net resistance at the upper surface of the substrate. 
       FIG. 4  is a graph  400  illustrating insertion loss (dB) versus frequency (GHz) for a signal applied to a 2 mm transmission line located above three different isolation structures. The first isolation structure, represented by curve  401 , corresponds with the p-well  260 , STI regions  232 - 235  and high-resistivity substrate  201 , as illustrated by  FIG. 2A . The second isolation structure, represented by curve  402 , corresponds with the p−-region  555 A, n-type epi regions  573 - 575 , STI regions  352 - 355 , deep trench isolation regions  362 A and  365 A, and high-resistivity substrate  301 , as illustrated by  FIGS. 3C-3D . The third isolation structure, represented by curve  403 , corresponds with the p−-regions  554 - 556 , n-type epi regions  573 - 575 , STI regions  352 - 355 , deep trench isolation regions  362 - 365  and high-resistivity substrate  301 , as illustrated by  FIGS. 3A-3B . As illustrated by graph  400 , the inclusion of both the p−-regions  554 - 556  and deep trench isolation regions  362 - 365  in the isolation structure significantly reduces the insertion loss in the associated semiconductor structure  300 . 
       FIGS. 5A-5G  are cross-sectional views of semiconductor structure  300  during various stages of fabrication in accordance with one modified SiGe BiCMOS process of the present invention. As illustrated by  FIG. 5A , N+ region  345  is initially formed on the upper surface of high resistivity p-type substrate  301 . In one embodiment, p-type substrate  301  is monocrystalline silicon having a resistivity of about 500 Ω-cm or more. As described above, N+ region  345  eventually forms a portion of the collector region of SiGe HBT  341 . 
     As illustrated by  FIG. 5B , an n-type epitaxial silicon layer  502  is then grown over the upper surface of substrate  301 , using a method known to those of ordinary skill in the art. In one embodiment, n-type epitaxial layer  502  has a thickness of about 1.1 microns, and a dopant concentration of about 10 16  cm −3 . As a result, n-type epitaxial layer  502  is well suited to implement the collector region  578  of the SiGe HBT  341 . 
     As illustrated in  FIG. 5C , an active nitride hard mask  504  is formed over the upper surface of the resulting structure, wherein the mask  504  includes openings that define locations where shallow trench isolation (STI) regions  351 - 359  will be formed. In general, regions covered by mask  504  correspond with the active regions of the semiconductor structure  300  (i.e., regions where semiconductor devices will be fabricated). An etch is performed through the active nitride hard mask  504 , thereby forming shallow trenches  521 - 529 . In the described embodiment, each of the shallow trenches  521 - 529  has a depth of about 0.3 microns, such that the distance (D 1 ) from the bottom of the shallow trenches to the bottom of the n-type epitaxial layer  502  is about 0.8 microns. Note that in the embodiment of  FIGS. 3E and 3F , the active nitride hard mask  504  is modified to provide a pattern that includes openings where STI regions  351 ,  352 B,  353 B,  354 B and  356 - 359  are to be formed. 
     As illustrated in  FIG. 5D , a p-type (p-) counter-doping implant  530  is then performed through mask  504 . In accordance with one embodiment, boron is implanted at an energy of about 130 keV and a dosage of about 2×10 16  cm 2 . The energy of the counter-doping implant  530  is selected to target at about half the thickness of the exposed n-type epitaxial regions  511 - 518 . Thus, in the illustrated example, the energy of the counter-doping implant  530  is selected to target a depth of about 0.4 microns (i.e., 0.8/2 microns). Thus, p-type dopant is implanted into regions  531 - 539  within the n-type epitaxial layer  502 , as illustrated in  FIG. 5D . Note that the various regions  531 - 539  may be continuous outside the view of  FIG. 5D . The parameters of P-type implant  530  are selected to counter-dope the exposed portions of the n-type epitaxial layer  502 , with the goals of providing regions having a low net doping (and therefore a high resistivity), and providing regions that are slightly p-type. In other embodiments, other implant conditions can be used to counter-dope the n-type epitaxial layer  502 . For example, multiple implants at different energies and/or doses can be performed in series to achieve a flatter dopant profile over an extended range. Such multiple implants can beneficially tailor the p-type compensating dopant profile to match the dopant profile of the n-type epitaxial layer  502 . 
     As illustrated by  FIG. 5E , mask  504  is removed and a dielectric material (e.g., silicon oxide) is deposited over the resulting structure, and a CMP process is performed to remove the upper portions of the dielectric material, thereby forming shallow trench isolation regions  351 - 359  in shallow trenches  521 - 529 . The exposed portions of the n-type epitaxial regions  573 - 573  at the upper surface of the substrate provide structural rigidity that prevents the over-polishing of the adjacent active regions, such as n-type epitaxial regions  571 - 572  and  576 - 580 , during the CMP process. During this process (or during a subsequent process), the p-type impurities implanted in regions  531 - 539  are activated, thereby forming very lightly doped p−-regions  541 - 549 , and leaving n-type epitaxial regions  571 - 580 . Again, the p−-regions  541 - 549  may be continuous outside the view of  FIG. 5E . As mentioned above, the p-type dopant concentration of the p-type counter-doping implant  530  is selected to be slightly greater than the n-type dopant concentration of the n-type epitaxial layer  502 , such that resulting the p−-type regions  541 - 549  have a net dopant concentration that is only slightly greater than an undoped region. As a result, the sheet resistance of p−-regions  541 - 549  is relatively high (e.g., 50 KΩ/square or more). In one embodiment, the resistivity of p−-regions  541 - 549  is approximately the same as the resistivity of p-type substrate  301 . Note that while the substrate  301  has a uniform resistivity and the n-type epitaxial layer  502  has a fairly uniform resistivity, the counter-doped regions  541 - 549  may not exhibit a uniform resistivity due to the nature of the implant profiles. As a result, the resistivity of the counter-doped regions  541 - 549  may vary significantly with depth from the silicon surface. Thus, sheet resistance is used to provide the net lateral resistance of the entire region. 
     As illustrated by  FIG. 5F , deep trench isolation regions  361 - 367  are formed. Deep trench isolation regions  361 - 367  extend through shallow trench isolation regions  351 - 355 ,  357  and  359 , p−-regions  541 - 545 ,  547  and  549 , and into substrate  301 . In one embodiment, each of deep trench isolation regions  361 - 367  is polysilicon encased with silicon dioxide having a width of about 1 μm and a depth of about 8 μm. As described above in connection with  FIG. 3B , deep trench isolation regions  362 - 365  are configured in a staggered grid pattern in isolation region  320 . The T-shaped intersections of the staggered grid pattern (and the absence of cross-shaped intersections of the staggered grid pattern) make it easier to completely fill the deep trenches with dielectric material. In the alternate embodiments of  FIGS. 3C-3D and 3E-3F , the deep trench isolation regions  362 - 365  are replaced with distinct deep trench isolation regions  362 A and  365 A. Deep trench isolation regions  361 - 367  divide the p−-regions  541 - 549  to form p−-regions  551 - 563 , as illustrated. In general, deep trench isolation regions are fabricated using a process known to those of ordinary skill in the art. 
     As illustrated in  FIG. 5G , conventional SiGe BiCMOS process steps are then implemented to fabricate CMOS devices  311 - 314  and  331 - 332 , and to fabricate SiGe HBT device  341 . Note that the formation of p-well region  315 , n-well regions  316 - 317  and deep n-well region  318  effectively replaces n-type epitaxial region  572  and p−-regions  552 - 553 . Similarly, p-well region  333  and n-well region  334  effectively replace n-type epitaxial regions  576 - 577  and p−-regions  557 - 559 . In one embodiment, silicide blocking structures  583 - 585  are formed by depositing a thin silicon oxide layer having a thickness of about 100 Angstroms followed by a silicon nitride layer having a thickness of about 300 A. A silicide block mask (not shown) is formed over the nitride layer, wherein the silicide block mask includes openings in regions where silicide is to be eventually formed. The silicon nitride (and underlying silicon oxide) exposed through the openings in the silicide block mask is etched away completely to allow for subsequent silicide formation in the regions specified by the openings of the silicide block mask. Note that silicide blocking structures  583 - 585  prevent the formation of metal silicide regions over n-epi regions  573 - 575  during a conventional process used to form metal silicide over exposed silicon regions in RF transistor  310 , CMOS transistor region and HBT region  340 . Although silicide blocking structures  583 - 585  are illustrated as separate structures, it is understood that a continuous silicide blocking structure could alternately be formed over the entire isolation region  320 . 
       FIG. 6A  is a cross sectional representation of a semiconductor structure  600  in accordance with an alternate embodiment of the present invention. Semiconductor structure  600  is fabricated in accordance with a modified SiGe BiCMOS process in a manner described in more detail below. Because semiconductor structure  600  is similar to semiconductor structure  300 , similar elements in  FIGS. 6A and 3A  are labeled with similar reference numbers. Thus, semiconductor structure  600  includes RF switch transistor  310  and 1.8V/5V CMOS transistor region  330 , which are described above in connection with  FIG. 3A . 
     Semiconductor structure  600  also includes an isolation region  620  and an HBT region  640 , which are fabricated on the high resistivity (HR) p-type semiconductor substrate  301 . Isolation region  620  provides electrical isolation between various elements fabricated on high resistance substrate  301  (in a similar manner to isolation region  320  of  FIGS. 3A-3B ). Isolation region  620  includes shallow trench isolation regions  352 - 355 , deep trench isolation regions  362 - 365 , p−-regions  610 - 612  and silicide blocking structures  636 - 638 .  FIG. 6B  is a top view of isolation region  620 , which includes the deep trench isolation regions  362 - 365  (and  371 - 378 ) connected in a staggered grid pattern  360  in the manner described above in connection with  FIG. 3B . Although STI regions  352 - 355  are not explicitly shown in  FIG. 6B , it is understood that these STI regions exist everywhere within the grid, except for where the p−-regions  610 - 612  are exposed at the upper surface of the substrate (as illustrated by the squares labeled “STI openings  616 - 618 ” in  FIGS. 6A and 6B ). The openings  616 - 618  in the STI regions  352 - 355  exist to provide structural strength to the isolation region  620 , thereby preventing over-polishing of adjacent active regions during the STI CMP process. Silicide blocking structures  636 - 638  prevent the formation of metal silicide in the STI openings  616 - 618 , reducing the conductance of isolation region  620 . 
     As illustrated by  FIGS. 6A and 6B , the p−-regions  610 - 612  provide a relatively high resistance path at the upper surface of the substrate in the isolation region  620 . The combination of the deep trench isolation regions  362 - 365  and the high resistivity p−-regions  610 - 612  (along with the absence of silicide in the STI openings  616 - 618 ) advantageously reduces insertion losses in the RF switch  310 . Note that isolation region  620  (unlike isolation region  320 ) does not include any n-type epitaxial regions. As a result, isolation region  620  may provide improved isolation with respect to isolation region  320 . 
     Bipolar transistor region  640  includes a SiGe NPN heterojunction bipolar transistor (HBT)  641 . SiGe HBT  641  is similar to SiGe HBT  341  ( FIG. 3A ). However, SiGe HBT  641  includes an n-type epitaxial collector region  624 , which replaces the n-epi collector region  578  and p−-regions  560 - 562  of SiGe HBT  341 . 
     Although the isolation regions  320  and  620  illustrated by  FIGS. 3A-3B and 6A-6B  each includes a grid of deep trench isolation regions  362 - 365  and  371 - 378  arranged to define a plurality of rectangles/squares, it is understood that these deep trench isolation regions can be arranged to include a grid having other polygonal shapes in other embodiments. For example,  FIG. 6C  is a top view of an isolation region  650  that includes a deep trench isolation grid  651  arranged as a plurality of hexagons. In this grid pattern, the deep trench isolation regions define Y-shaped intersections (e.g., Y-shaped intersection  656 ), but no cross-shaped intersections. Advantageously, the Y-shaped intersections result in the associated deep trenches being easier to fill than deep trenches having cross-shaped intersections. Inadequate filling of the deep trench can lead to a higher defect rate and reduced yields. Moreover, the relatively wide corner angles of hexagonal DTI grid  651  (i.e., greater than 90 degrees) result in lower stress within the DTI grid  651  for improved manufacturability. 
     Deep trench isolation grid  651  includes exemplary deep trench isolation regions  652 - 655 , which may roughly correspond with deep trench isolation regions  362 - 365  of isolation regions  320  and  620 . Isolation region  650  includes STI openings  661 - 667 , through which underlying n-type epitaxial regions (like the n-type epi regions  573 - 575  of isolation region  320 ) may be exposed. In an alternate embodiment, STI openings  661 - 667  may roughly correspond with STI openings  616 - 618  of isolation region  620 . Thus, the dimensions of each of the square openings  661 - 667  is about 1 micron by 1 micron. In one embodiment, the each side of the hexagonal DTI grid  651  has a length of about 8 microns. The dimensions of the DTI grid are determined by the maximum density of deep trenches that are manufacturable by the process. As a result, the fabrication of the DTI mesh does not lead to increased defects or reduced yields in mass production. Shallow trench isolation region  670  is located everywhere within the isolation region  650 , except where the STI openings  661 - 667  are located. P−-regions  671 - 677 , which roughly correspond with p−-regions  554 - 556  of isolation region  320 , or p−-regions  610 - 612  of isolation region  620 , are isolated by the deep trench isolation grid  651 . Note that it is relatively easy to fabricate the isolation region  650  of  FIG. 6C , due to the absence of  90  degree angles in the layout of the deep trench isolation grid  651 . 
     Silicide blocking structures  681 - 687  are formed over the dummy active regions exposed through the STI openings  661 - 667 , respectively. Silicide blocking structures  681 - 687  may be formed in the same manner described above for silicide blocking structures  583 - 586 . As described above, dummy active regions are used to maintain a minimum local density of active regions to ensure well-controlled polishing during the CMP step of the shallow trench isolation (STI) process module. If dummy active regions were not present over a large area, nearby active devices may be damaged during the STI CMP process. By including the small (unsalicided) active dummy regions in the described embodiments, the STI process module behaves normally while the active density remains at a minimum. Because active regions contribute to lateral coupling of unwanted signals, minimizing the density of the active dummy regions reduces RF losses. 
     An additional benefit of including dummy active regions squares within the DTI grid is that no new design rule constraints are imposed on devices near the DTI grid. The DTI grid can be placed as close to adjacent active devices as allowed by the existing design rules of the process (e.g., DTI spacing to active). This DTI grid layout can therefore be employed extensively throughout the RF circuit, maximizing device-to-device isolation and reducing losses to back end of line (BEOL) passive elements. 
     Moreover, employing silicide block over the dummy active regions of the DTI grid ensures the least possible conductivity within the associated isolation region, thereby maximizing lateral substrate impedance. 
     In addition, the cell-based design of the DTI grid makes it well-suited for automated placement, which maximizes its effect and minimizes implementation time. For example, the DTI grid can be automatically inserted by an algorithm to fill all “empty” space in an RF circuit design (i.e., all space around and in between active device elements). To manually place a similar amount of DTI structure would be impractically slow and difficult due to the need to carefully respect all design rule requirements. Automatic placement of the DTI grid by algorithm can be accomplished quickly and independent of the circuit designer, similar to the way in which dummy active regions or metal fills are typically inserted after circuit design is complete. Alternately, the DTI grid can be filled automatically only within designated areas if a circuit designer would like to control wherein the DTI grid is (or is not) present. 
     The DTI grid design is constructed as an array of cells in the manners described above. The exact layout (dimensions and shape) can vary depending on design and process parameters. However, the DTI grid includes two key elements. First, the DTI grid is arranged in a staggered mesh, such that there are no ‘cross’ (+) intersections of DTI walls, only ‘T’ or ‘Y’ shaped intersections, as described above. Second, inside each DTI opening, there is a small polygon (e.g., square) of active device silicon encompassed by a silicide blocking structure. This provides a small but non-zero density of active silicon regions within the DTI grid. 
     Although square and hexagonal DTI grids have been described above, it is understood that other polygonal shapes can be used to define the openings of the DTI grid in other embodiments. 
     Although isolation region  620  includes a grid of deep trench isolation regions  362 - 365  in the embodiment illustrated by  FIGS. 6A and 6B , it is possible to eliminate this grid in the same manner described above in connection with  FIGS. 3C and 3D .  FIG. 6D  is a cross sectional representation of a semiconductor structure  600 A having an isolation region  620 A that does not include a grid of deep trench isolation regions, but rather, includes a continuous p−-type region  615  located between separate deep trench isolation regions  362 A and  365 A. Note that similar elements in semiconductor structure  600  ( FIG. 6A ) and semiconductor structure  600 A ( FIG. 6D ) are labeled with similar reference numbers.  FIG. 6E  is a top view of isolation region  620 A, which includes the discrete deep trench isolation regions  362 A and  365 A, when viewed from above. Although STI regions  352 - 355  are not explicitly shown in  FIG. 6E , it is understood that these STI regions exist between deep trench isolation regions  362 A and  365 A, except for where the STI openings  616 - 618  are located at the upper surface of the substrate. As described above, the openings  616 - 618  in the STI regions  352 - 355  prevent over-polishing (and damaging) of the adjacent active regions during CMP of the STI regions  351 - 359 . Silicide blocking regions  636 - 638  prevent the formation of metal silicide in the dummy active regions exposed through openings  616 - 618 , respectively. 
       FIGS. 6F and 6G  illustrate another embodiment that eliminates the grid of deep trench isolation regions  362 - 365 .  FIG. 6F  is a cross sectional representation of a semiconductor structure  600 B having an isolation region  620 B that does not include a grid of deep trench isolation regions. Similar elements in semiconductor structure  600  ( FIG. 6A ) and semiconductor structure  600 B ( FIG. 6F ) are labeled with similar reference numbers. In the illustrated embodiment, isolation region  620 B provides isolation between RF switch transistor  310  and other circuit elements of semiconductor structure  600 B. Isolation region  620 B includes shallow trench isolation regions  352 B,  353 B and  354 B, deep trench isolation regions  362 A and  365 A, p−-type region  615  and silicide blocking structures  636 B and  637 B.  FIG. 6G  is a top view of isolation region  620 B, which includes the discrete deep trench isolation regions  362 A and  365 A, which have been described above in connection with  FIG. 3F . P−-region  615  laterally surrounds deep trench isolation regions  362 A and  365 A. P−-region  615  is exposed through openings  616 B and  617 B of shallow trench isolation regions  352 B,  353 B and  354 B. Silicide blocking structures  636 B and  637 B cover the dummy active regions exposed through openings  616 B and  617 B. Edges of STI regions  352 B,  353 B and  354 B are illustrated by  FIG. 6G . Exposure of the P−-region  615  through openings  616 B and  617 B advantageously prevents over-polishing (and damaging) of the adjacent active regions during CMP of the STI regions  351 ,  352 B,  353 B,  354 B and  356 - 359 . P−-type region  615  advantageously exhibits a high net resistance at the upper surface of the substrate. 
       FIGS. 7A-7D  are cross sectional views of semiconductor structure  600  during various stages of fabrication. As illustrated by  FIG. 7A , N+ region  345  is initially formed on the upper surface of high resistivity p-type substrate  301 , and n-type epitaxial silicon layer  502  is then grown over the upper surface of substrate  301  (resulting in the structure described above in connection with  FIG. 5B ). A counter-doping implant mask  601  is formed over the n-type epitaxial layer  502 , wherein the mask  601  includes an opening that defines the location of isolation region  620 . Note that counter-doping implant mask  601  represents an extra mask with respect to a conventional SiGe BiCMOS process node. 
     A p-type (p-) counter-doping implant  602  is performed through the opening of mask  601 . In accordance with one embodiment, boron is implanted at an energy of about 180 keV and a dosage of about 2.5×10 16  cm −3 . The energy of the counter-doping implant  602  is selected to target at about half the thickness of the exposed n-type epitaxial layer  502 . Thus, in the illustrated example, the energy of implant  602  is selected to target a depth of about 0.55 microns (i.e., (1.1)/2 microns). Thus, p-type dopant is implanted into region  605  within the n-type epitaxial layer  502 , as illustrated in  FIG. 7A . The parameters of P-type implant  602  are selected to counter dope the exposed portions of the n-type epitaxial layer  502 , with the goals of providing regions having a low net doping (and therefore a high resistivity), and providing regions that are slightly p-type. In other embodiments, other implant conditions can be used to counter-dope the n-type epitaxial layer  502 . As described above in connection with the counter-doping implant  530  of  FIG. 5D , multiple implants at different energies and/or doses can be performed to tailor the p-type compensating dopant profile to match the dopant profile of the n-type epitaxial layer  502 . 
     As illustrated by  FIG. 7B , the p-type impurities implanted in region  605  are activated, thereby forming very lightly doped p−-region  609 . Although the activation of the p-type impurities is illustrated as an independent step in  FIG. 7B , it is understood that the activation of these p-type impurities may alternately occur later in the process (e.g., during anneals performed in accordance with the formation of subsequently formed structures). As mentioned above, the p-type dopant concentration of the p-type counter-doping implant  602  is selected to be slightly greater than the n-type dopant concentration of the n-type epitaxial layer  502 , such that the p−-type region  609  has a net dopant concentration that is only slightly greater than an undoped region. As a result, the sheet resistance of p−-region  609  is relatively high (e.g., 50 KΩ/square or greater). In one embodiment, the resistivity of p−-region  609  is approximately the same as the resistivity of p-type substrate  301 . 
     As illustrated in  FIG. 7C , shallow trench isolation regions  351 - 359  are fabricated by etching STI region trenches through a mask, removing the mask, depositing a dielectric material (e.g., silicon oxide) over the resulting structure, and performing a CMP process to remove the upper portions of the dielectric material. Again, portions of the p−-region  609  exposed at the upper surface of the resulting structure provide structural rigidity that prevents the over-polishing of adjacent active regions during the CMP process. Note that to implement the alternate embodiment of  FIGS. 6F-6G , the STI mask is modified to fabricate the STI regions  351 ,  352 B,  353 B,  354 B, and  356 - 359 . 
     Deep trench isolation regions  361 - 367  are formed through the shallow trench isolation regions  351 - 355 ,  357  and  359 , as illustrated. Deep trench isolation regions  361 - 367  extend through n-type epitaxial layer  502  and p−-region  609  and into substrate  301 , thereby dividing the non-counter-doped portions of n-type epitaxial layer  502  into n-type epitaxial regions  621 - 625 , and dividing the lightly doped p−-region  609  into p−-regions  610 - 612 . The structure of deep trench isolation regions  361 - 367  is described above in connection with  FIG. 5F . Note that to implement the alternate embodiments of  FIGS. 6D-6E and 6F-6G , the deep trench isolation regions  362 - 365  are replaced with the deep trench isolation regions  362 A and  365 A. 
     As illustrated in  FIG. 7D , conventional SiGe BiCMOS process steps are implemented to fabricate CMOS devices  311 - 314  and  331 - 332 , and to fabricate SiGe HBT device  641 . Note that the formation of p-well region  315 , n-well regions  316 - 317  and deep n-well region  318  effectively replaces n-type epitaxial region  622 . Similarly, p-well region  333  and n-well region  334  effectively replace n-type epitaxial region  623 . Silicide blocking structures  636 - 638  are formed over p−-regions  610 - 612  in the manner described above for silicide blocking structures  583 - 585 . 
     In the manner described above, the isolation regions  320 ,  320 A,  320 B,  620 ,  620 A and  620 B can be fabricated with only slight modifications to a conventional SiGe BiCMOS process node. The improved isolation regions  320 ,  320 A,  320 B,  620 ,  620 A and  620 B allow for improved operation of a FEM fabricated on a single integrated circuit chip. Specific advantages provided by the improved isolation regions  320 ,  320 A,  320 B,  620 ,  620 A and  620 B of the present invention include the following. For passive devices such as MIM capacitors, inductors and transmission lines, energy loss due to capacitive coupling to the substrate are significantly reduced, enabling the passive devices to realize higher Q factors. The isolation regions  320 ,  320 A,  320 B,  620 ,  620 A and  620 B increase the impedance between nearby signal paths, reducing both cross-talk and signal loss to ground. This greatly reduces the insertion loss of devices such as coplanar waveguides and RF switch branches biased in the on-state, while increasing isolation across RF switch branches biased in the off-state. 
     In addition, the silicon regions outside of the active devices (i.e., the silicon regions in isolation regions  320 ,  320 A,  320 B,  620 ,  620 A and  620 B) become more linear. Although the impedance of any signal path through these isolation regions has been increased, some RF signals will still couple laterally through the substrate between ports of a circuit. However, by eliminating (or minimizing) the p-n junction between the n-type epitaxial layer and the underlying high-resistivity silicon substrate in the isolation regions  320 ,  320 A,  320 B,  620 ,  620 A and  620 B, this will contribute much less non-linearity to the RF circuits. 
     The benefits described above extend the frequency range for which BiCMOS technologies can provide competitive performance, enabling the design of single-chip RF systems for certain applications (e.g., front end modules). 
     Although the grid of DTI regions of the present invention has been described in connection with a BiCMOS process, it is understood that a grid of DTI regions can also be used to isolate semiconductor devices fabricated using CMOS processes.  FIG. 8  is a cross sectional representation of a semiconductor structure  800  in accordance with an alternate embodiment of the present invention. Semiconductor structure  800  is fabricated in accordance with a modified CMOS process in a manner described in more detail below. Because semiconductor structure  800  is similar to semiconductor structure  300 , similar elements in  FIGS. 8 and 3A  are labeled with similar reference numbers. Thus, semiconductor structure  800  includes RF switch transistor  310  and 1.8V/5V CMOS transistor region  330 , which are described above in connection with  FIG. 3A . 
     Semiconductor structure  800  also includes an isolation region  820 , which is fabricated on the high resistivity (HR) p-type semiconductor substrate  301 . Isolation region  820  provides electrical isolation between various CMOS elements fabricated on high resistance substrate  301  (in a similar manner to isolation region  320  of  FIGS. 3A-3B ). Isolation region  820  includes shallow trench isolation regions  352 - 355 , deep trench isolation regions  362 - 365 , and silicide blocking structures  583 - 585 . 
     Notably, semiconductor structure  800  only includes CMOS devices, and does not include the HBT region  340  or the n-type epitaxial layer  502  included in semiconductor structure  300 . Because an n-type epitaxial layer is not included in semiconductor structure  800 , high resistivity substrate  301  extends all the way to the upper surface within isolation region  820 . Consequently, there is no need for counter doping an n-type epitaxial layer within isolation region  820  to provide a high resistivity at the upper surface of the isolation region  820 . Instead, the high resistivity substrate  301  exists within the active dummy region  873 - 875  of the isolation region  820 . Note that the grid of DTI regions  362 - 365  can be connected in a staggered grid pattern with square openings ( FIG. 3B ) or a staggered grid pattern with openings having other polygonal shapes (like  FIG. 6C ). Further note that the structure of isolation region  820  of  FIG. 8  can also be used to implement isolation regions similar to those illustrated in  FIGS. 3D, 3F, 6E and 6G . More specifically, the p−-counter doped region  555 A and n-epi regions  573 - 575  of isolation region  320 A may be eliminated (i.e., replaced with high resistivity substrate  301 ); the p−-counter doped regions  554 B,  555 B and  556 B and n-epi regions  573 B and  574 B of isolation region  320 B may be eliminated (i.e., replaced with high resistivity substrate  301 ); and the p−-counter doped region  615  of isolation regions  620 A and  620 B may be eliminated (i.e., replaced with high resistivity substrate  301 ). 
     Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. Thus, the invention is limited only by the following claims.