Patent Publication Number: US-2022231143-A1

Title: Gate structure and method of fabricating the same

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of and claims priority of U.S. Non-Provisional application Ser. No. 16/901,314, titled “GATE STRUCTURE AND METHOD OF FABRICATING THE SAME” and filed on Jun. 15, 2020, which claims priority of U.S. Non-Provisional application Ser. No. 16/429,616, titled “GATE STRUCTURE AND METHOD OF FABRICATING THE SAME” and filed on Jun. 3, 2019, which claims priority of U.S. Non-Provisional application Ser. No. 16/015,392, titled “GATE STRUCTURE AND METHOD OF FABRICATING THE SAME” and filed on Jun. 22, 2018, which claims priority of U.S. Non-Provisional application Ser. No. 15/293,259, titled “GATE STRUCTURE AND METHOD OF FABRICATING THE SAME” and filed on Oct. 13, 2016, which claims priority of U.S. Provisional Application Ser. No. 62/261,201, titled “APPROACH OF MG PULL BACK FOR MG MISSING” and filed on Nov. 30, 2015. U.S. Non-Provisional application Ser. No. 16/901,314, U.S. Non-Provisional application Ser. No. 16/429,616, U.S. Non-Provisional application Ser. No. 16/015,392, U.S. Non-Provisional application Ser. No. 15/293,259, and U.S. Provisional Application Ser. No. 62/261,201 are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     As technology nodes shrink, in some integrated circuit designs, replacing the polysilicon gate electrode with a metal gate electrode can improve device performance with the decreased feature sizes. Providing metal gate structures (e.g., including a metal gate electrode rather than polysilicon) offers one solution. One process of forming a metal gate stack is termed a “gate last” process in which the final gate stack is fabricated “last” which allows for a reduced number of subsequent processes, including high temperature processing, that are performed before formation of the gate stack. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide may be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high dielectric constant (high-k or HK) gate insulator layers are also used which allows to maintain the same effective thickness as would be provided by a typical gate oxide used in larger technology nodes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a flowchart of a method of fabricating a gate structure in accordance with some embodiments of the instant disclosure; 
         FIGS. 2 to 19  are cross-sectional views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure; 
         FIGS. 20 and 21  are zoom in view of dashed-line circles in  FIG. 17  respectively; and 
         FIG. 22  illustrates the cross-sectional view of an intermediate stage in the formation of a high-k metal gate stack in accordance with some embodiments of the instant disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
       FIG. 1  is a flowchart of a method  100  of fabricating a gate structure in accordance with some exemplary embodiments of the instant disclosure. The method begins with operation  101  in which a dummy gate layer stack is formed on a semiconductor substrate of a wafer. The method continues with operation  103  in which vertical dummy gate stacks are formed by patterning the dummy gate layer stack. Subsequently, operation  105 , lightly-doped drain and source (LDD) regions are formed in the semiconductor substrate. The method continues with operation  107  in which spacers are formed adjacent to the dummy gate stack. The method continues with operation  109  in which source and drain regions are formed in the semiconductor substrate. The method continues with operation  111  in which an inter-level dielectric (ILD) layer around the spacers. Next, operation  113 , the dummy gate stacks are removed to form recesses. The method continues with operation  115  in which work function metal layers are deposited in the recesses. Following that, operation  117 , a first portion of the work function metal layers from the sidewalls of the recesses is removed. In operation  119 , a remaining portion of the recesses is filled with a filling metal. The method continues with operation  121  in which portions of the filling metal and work function metal layer is removed. Next, in operation  123 , a remaining portion of the recesses is filled with a protection layer. In operation  125 , the protection layer, the spacers, and the ILD layer are planarized. 
       FIGS. 2 to 19  are cross-sectional views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure. In  FIGS. 2-19 , the wafer  300  is a semiconductor device at an intermediate stage of manufacture. The wafer  300  includes a semiconductor substrate  301 . Examples of semiconductors include silicon, silicon on insulator (SOI), Ge, SiC, GaAs, GaAlAs, InP, and GaNSiGe. The semiconductor substrate  301  may be doped of either n-type or p-type, or undoped. Metal oxide semiconductor field effect transistors (MOSFETs) are added to the wafer  300 . These can be of the n-type, the p-type or both types in a complementary metal oxide semiconductor (CMOS) process. In some embodiments, the wafer  300  includes n-well regions, p-well regions, or both. The method shown in  FIGS. 1-19  is applicable to form planar MOSFETs and/or fin field effect transistors (FinFETs). When the method shown in  FIGS. 2-19  is applied to form FinFETs, the semiconductor substrate  301  includes at least one fin structure. The portion of the semiconductor substrate  301  shown in  FIGS. 2-19  is a portion of the fin structure. 
     Reference is made to  FIG. 2 . An interfacial layer  303  and a high-k dielectric layer (gate dielectric)  305  are formed over the semiconductor substrate  301  (operation  101  of  FIG. 1 ). The interfacial layer  303  is the interface between the semiconductor substrate  301  and the high-k dielectric layer (gate dielectric)  305 . The interfacial layer  303  includes silicon oxide or silicon oxynitride. The interfacial layer  303  can form spontaneously as a result of wet cleans of the wafer  300  prior to the formation of the high-k dielectric layer  305  or as a result of interaction between the high-k dielectric layer  305  and the semiconductor substrate  301  during or subsequent to formation of the dielectric layer  305 . Intentionally forming the interfacial layer  303  can provide a higher quality interface. The interfacial layer  303  is made very thin to minimize the interfacial layer&#39;s contribution to the overall equivalent oxide thickness of the resulting gates. In some embodiments, the thickness of the interfacial layer  303  is in a range from about 1 to about 20 Angstroms. 
     The interfacial layer  303  of silicon oxide can be formed by a suitable process including chemical oxidation, for example, by treating the semiconductor substrate  301  with hydrofluoric acid (HF) immediately prior to depositing the high-k dielectric layer  305 . Another process for the silicon oxide interfacial layer  303  is to thermally grow the interfacial layer  303  followed by a controlled etch to provide the desired layer thickness. In some embodiments, the interfacial layer  303  can be formed after the high-k dielectric layer  305 . For example, a silicon oxynitride interfacial layer can be formed by annealing a wafer with a silicon semiconductor substrate and a hafnium-based high-k dielectric layer in an atmosphere of nitric oxide. This later process has advantages such as reduced queue time. 
     The high-k dielectric layer  305  includes one or more layers of one or more high-k dielectric materials. High-k dielectrics are expected to have a dielectric constant, k, of at least or equal to about 4.0. Examples of high-k dielectrics include hafnium-based materials such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and HfO 2 Al 2 O 3  alloy. Additional examples of high-k dielectrics include ZrO 2 , Ta 2 O 5 , Al 2 O 3 , Y 2 O 3 , La 2 O 3 , and SrTiO 3 . In some embodiments, the high-k dielectric layer  305  has a thickness in a range from about 5 to about 50 Angstroms. The high-k dielectric layer  305  can be formed by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). 
     Optionally, a capping layer may be formed over the high-k dielectric layer  305 . The capping layer can protect the high-k dielectric layer  305  during subsequent processing and provide an etch stop layer for when the dummy gate material layer  307  is later removed. The capping layer can include one or more layers of materials, which may include, for example, TiN and TaN. The capping layer can be formed by a deposition process, such as CVD, ALD, or electroplating to a specified thickness. 
     Still referring to  FIG. 2 , a dummy gate material layer  307  is formed over the high-k dielectric layer  305 . The dummy gate material layer  307  is made of polysilicon, although other materials can be used. The dummy gate material layer  307  can be formed by a semiconductor deposition process. For example, a polysilicon dummy gate material layer can be formed by pyrolyzing silane. After formation of the dummy gate material layer  307 , a dummy gate layer stack  310  is formed on the wafer  300  as shown in  FIG. 1 . The dummy gate layer stack  310  includes the interfacial layer  303 , the high-k dielectric layer  305  and the dummy gate material layer  307 . 
     Reference is made to  FIGS. 3-4 . The dummy gate layer stack  310  is patterned to form dummy gate stacks  318   a  and  318   b  (operation  103  of  FIG. 1 ). For forming the dummy gate stacks  318   a  and  318   b , the patterning can be accomplished by a photolithographic process. The photolithography process includes coating the wafer  300  with a photoresist, selectively exposing the photoresist according to a desired pattern, developing the photoresist, and using the patterned photoresist as an etch mask. The patterned photoresist can be used as a mask to etch the dummy gate layer stack  310 . Alternatively, the photoresist is used to pattern a hard mask layer. The hard mask layer, if used, is formed before the photoresist. The wafer  300  of  FIG. 1  includes a hard mask layer  309  before patterning. The wafer  300  of  FIG. 2  includes the patterned hard mask layers  309   a  and  309   b . The patterned hard mask layers  309   a  and  309   b  are used as masks to etch the dummy gate layer stack  310 . Any etch process or combination of etch processes can be used to etch the dummy gate layer stack  310 . 
     Reference is made to  FIG. 4 . After patterning the dummy gate layer stack  310 , the dummy gate stacks  318   a  and  318   b  are formed. The dummy gate  318   a  includes the interfacial layer  303   a , the high-k dielectric layer  305   a , the dummy gate material layer  307   a , and the patterned hard mask layer  309   a . Likewise, the dummy gate  318   b  includes the interfacial layer  303   b , the high-k dielectric layer  305   b , the dummy gate material layer  307   b , and the patterned hard mask layer  309   b . It should be understood that the dummy gate stacks  318   a  and  318   b  may not be adjacent to each other. For the sake of clarity and simplicity, the two dummy gate stacks  318   a  and  318   b  are put together for illustration purpose. The dummy gate stacks  318   a  and  318   b  may be separated apart by other features not shown in the figure. 
     A process for etching the dummy gate layer stack  310  includes a plasma etch. Reactive gases can interact with the wafer  300  during plasma etching to produce volatile by products that subsequently redeposit on nearby surfaces. This can result in the formation of an optional passivation layer (not shown) on sidewalls of the dummy gate stacks  318   a  and  318   b  respectively. The optional passivation layers can be silica or a similar material such as a silicate. 
     An ion implantation process is performed to form lightly doped drain (LDD) regions (operation  105  of  FIG. 1 ). The dummy gate stacks  318   a  and  318   b  are used as masks to help control the implant profile and distribution.  FIG. 5  shows the wafer  300  with the LDD regions  329   a  and  329   b  formed in the semiconductor substrate  301 . After the ion implantation process, spacers  320   a  and  320   b  are formed around the dummy gate stacks  318   a  and  318   b  (operation  107  of  FIG. 1 ). A spacer material is first deposited over the wafer  300  covering the dummy gate stacks  318   a  and  318   b  and the areas between the dummy gate stacks  318   a  and  318   b . The spacer material is then etched back to remove the portions over the dummy gate stacks  318   a  and  318   b  and in the areas between the dummy gate stacks  318   a ,  318   b . By tuning the etch process, selected portions  320   a  and  320   b  of the spacer material around the dummy gate stacks  318   a  and  318   b  remain after the etch back. 
     Before forming the spacers, optional spacer liners (not shown) may be formed. The spacer liners may be silica or silicate. The material of the spacer liners can be similar to the material of the passivation layers if both layers are present. The spacers  320   a  and  320   b  may be made of silicon nitride or another material that has the properties of conformal deposition, a large etch selectivity against the dummy gate material (harder to etch than the dummy gate material) and a passive material that can trap implanted dopants. 
     Still referring to  FIG. 5 , source/drain regions  327   a  and  327   b  are formed after the spacers  320   a  and  320   b  are formed (operation  109  of  FIG. 1 ). The source/drain regions  327   a  and  327   b  are formed in the semiconductor substrate  301 . In the embodiments where the dummy gate stack  318   a  and/or the dummy gate  318   b  is used to form a p-channel metal oxide semiconductor field effect transistor (pMOS) device, the source/drain regions  327   a  and/or the source/drain regions  327   b  are of p-type. In the embodiments where the dummy gate stack  318   a  and/or the dummy gate  318   b  is used to form an n-channel metal oxide semiconductor field effect transistor (nMOS) device, the source/drain regions  327   a  and/or the source/drain regions  327   b  are of n-type. The formation of source/drain regions  327   a  and  327   b  may be achieved by etching the semiconductor substrate  301  to form recesses therein, and then performing an epitaxy to grow the source/drain regions  327   a  and  327   b  in the recesses. 
     An inter-level dielectric (ILD) layer  319  is formed, as illustrated in  FIG. 6  (operation  111  of  FIG. 1 ). The ILD layer  319  adheres well to the spacers  320   a  and  320   b  and over the top of the hard mask layers  309   a  and  309   b.    
     Reference is made to  FIG. 7 . After the ILD layer  319  is formed, an upper surface of the wafer  300  is planarized to lower the surface to the level of the dummy gate material layers  307   a  and  307   b . The planarization is accomplished by, for example, chemical mechanical polishing (CMP). After planarizing, the patterned hard mask layers  309   a  and  309   b  are removed, and the dummy gate material layers  307   a  and  307   b , the spacers  320   a  and  320   b , and the ILD layer  319  all approximately have the same height. 
     Reference is made to  FIG. 8 . The dummy gate material layers  307   a  and  307   b  are removed to form recesses  312   a  and  312   b  (operation  113  of  FIG. 1 ). The dummy gate material layers  307   a  and  307   b  are removed in one or many etch operations including wet etch and dry etch. According to various embodiments, a hard mask is patterned over the wafer  300  to protect the ILD layer  319  and the spacers  320   a  and  320   b . In some embodiments, a first etch process breaks through native oxide layers on the dummy gate material layers  307   a  and  307   b , and a second etch process reduces the thickness of the dummy gate material layers  307   a  and  307   b . The dummy gate material layer etch may stop at the high-k dielectric layers  305   a  and  305   b  or continues to the interfacial layers  303   a  and  303   b  or the semiconductor substrate  301  below. In other embodiments, only the dummy gate material layers  307   a  and  307   b  are removed. However, the etch processes may remove some surrounding material such as a portion of the spacers  320   a  and  320   b . A recess  312   a  is formed between the spacers  320   a , and a recess  312   b  is formed between the spacers  320   b . As previously discussed, the high-k dielectric layers  305   a ,  305   b  may also be removed. If it is, then a high-k dielectric layer is formed in the recesses in a separate operation. 
     Attention is now invited to  FIG. 9 . A plurality of work function metal layers is deposited in the recesses  312   a  and  312   b  (operation  115  of  FIG. 1 ). Two gate structures are denoted as  300   a  and  300   b  respectively for ease of reference. A first work function metal layer  330  is formed in the recesses  312   a  and  312   b  and follows the contour created by bottom surfaces and sidewalls of the recesses  312   a  and  312   b  and top surfaces of the spacers  320   a  and  320   b  and the ILD layer  319 . A second work function metal layer  340  is deposited on the first work function metal layer  330  and conforms to the first work function metal layer  330 . The first work function metal layer  330  is in direct contact with the high-k dielectric layers  305   a  and  305   b . The second work function metal layer  340  inherits the configuration of the first work function metal layer  330 . 
     The first and second work function metal layers  330  and  340  may include Ti, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Co, Al, or any suitable materials. For example, the first and second work function metal layers  330  and  340  include at least one of TiN, Co, WN, or TaC when at least one of the gate structures  300   a  and  300   b  is a portion of a PMOS device. Alternatively, the first and second work function metal layers  330  and  340  include at least one of Ti, Al, or TiAl when at least one of the gate structures  330   a  and  300   b  is a portion of an NMOS device. The first and second work function metal layers  330  and  330  may be deposited by, for example, CVD, plasma-enhanced CVD (PECVD), sputtering, ion beam, spin on, physical vapor deposition (PVD), ALD or the like. 
     Attention is now invited to  FIGS. 10-13 . The second work function metal layer  340  is pulled back in two stages (operation  117  of  FIG. 1 ). As shown in  FIG. 10 , a mask layer  345  is deposited on the substrate  301 . In some embodiments, the mask layer  345  is, for example, a bottom anti-reflective coating (BARC) layer. The mask layer  345  fills in the recesses  312   a  and  312   b  and covers up the entire second work function meta layer  340  on the top surfaces of the spacers  320   a  and  320   b  and the ILD layer  319 . 
     Next, please refer to  FIG. 11 . A first etching, for example, dry etching, is performed to pattern the mask layer  345 . The patterned mask layers  345   a  and  345   b  retreats into the recesses  312   a  and  312   b  respectively. A surface level of the mask layers  345   a  and  345   b  is within the recesses  312   a  and  312   b.    
     Attention is now invited to  FIG. 12 . After the first etching, in which the mask layer  345  is patterned to form the mask layers  345   a  and  345   b , a second etching is performed. The second etching, for example, wet etching, targets at the second work function metal layer  340 . During the second etching, the patterned mask layers  345   a  and  345   b  protect the underlying second work function metal layer  340  in the recesses  312   a  and  312   b . After the second etching, the second work function metal layers  340   a  and  340   b  are lowered respectively into the recesses  312   a  and  312   b , and top edges of the second work function metal layers  340   a  and  340   b  are modified along the course of the second etching to form slanting edges  342   a  and  342   b . In some embodiments, the first work function metal layer  330  and the second work function metal layer  340  are made of different materials. The first work function metal layer  330  is made of a material that has an etch selectivity against the second work function metal layer  340  during the second etching. 
     Attention is now invited to  FIG. 13 . The pull-back process targets at the second work function metal layer  340 , while the first work function metal layer  330  retains its integrity at this stage because of etch selectivity. The patterned mask layers  345   a  and  345   b  are then removed from the wafer  300 . The slanting edges  342   a  and  342   b  have a slope descending inwardly toward the respective recesses  312   a  and  312   b  (away from the spacers  320   a  and  320   b ). The slope of the tapered, slanting edges  342   a  and  342   b  ranges from about 15 to about 45 degrees. In some embodiments, the slanting edges  342   a  and  342   b  are rounded corners. 
     Turning now to  FIG. 14 . A third work function metal layer  350  is deposited on the wafer  300 , and then a portion of the third work function metal layer  350  in the gate structure  300   a  is removed. In some embodiments, the gate structure  300   a  and the gate structure  300   b  are used to form transistors with different threshold voltages or transistors of different types, and, therefore, the gate structure  300   a  and the gate structure  300   b  have different numbers of work function metal layers. In some embodiments, the gate structure  300   a  does not include the third work function metal layer  350 , while the gate structure  300   b  includes the third work function metal layer  350 . In some embodiments, the gate structure  300   a  is a p-type gate electrode, and the gate structure  300   b  is an n-type gate electrode. A designed threshold voltage for n-type and p-type devices can be tuned through different combination of work function metal layers. Different patterns arise between the gate structures  300   a  and  300   b  because of different numbers or combination of work function metal layers so as to achieve desired threshold voltage. The third work function metal layer  350  conforms to the padded recess  312   b , where the first work function metal layer  330  and the second work function metal layer  340   b  line the bottom surface and the sidewalls of the recess  312   b . The third work function metal layer  350  overtakes the slanting edges  342   b  of the second work function metal layer  340   b  in the recess  312   b , and therefore both the second and third work function metal layers  340   b  and  350  are in contact with the first work function metal layer  330 . In addition, because the second work function metal layer  340   b  is modified at the edges, the third work function metal layer  350  follows the inverted, stepped, pyramid topology in the recess  312   b.    
     Turning now to  FIG. 15 , the third work function metal layer  350  is pulled back to yield slanting edges  352 . Similar to the second work function metal layers  340   a  and  340   b , the third work function metal layer  350  undergoes a series of etching. A mask layer is deposited, and the first etching defines a patterned mask layer over the third work function metal layer  350  in the recess  312   b . Subsequently, the second etching results in the receding of the third work function metal layer  350  within the recess  312   b  and formation of slanting edges  352 . The third work function metal layer  350  covers up the underlying second work function metal layer  340   b . After the second etching, the third work function metal layer  350  contributes another level to the slanting sidewalls of the recess  312   b . The slanting edges  342   b  are translated into the third work function metal layer  350 . Likewise, the pull-back process targets at specific work function metal layer because of etch selectivity, and the first work function metal layer  330  retains its integrity throughout the second and third work function metal layer pull-back. 
     Turning now to  FIG. 16 , a filling metal  360  is deposited over the wafer  300  (operation  119  of  FIG. 1 ). The filling metal  360  fills in the remaining portion of the recesses  312   a  and  312   b  and overfills the recesses  312   a  and  312   b  to cover up the first work function meta layer  330  on the top surfaces of the spacers  320   a  and  320   b  and the ILD layer  319 . A material of the filling metal  360  may include, for example, tungsten (W). The gate structures  300   a  and  300   b  have different patterns results from different numbers of work function metal layers. As shown in  FIG. 16 , after the deposition of filling metal  360 , the different contour of the recesses  312   a  and  312   b  is more pronounced. In the gate structure  300   a , a portion of the filling metal  360  is enclosed by the second work function metal layer  340   a , while the remaining portion of the filling metal  360  is in contact with the first work function metal layer  330 . In the gate structure  300   b , the filling metal  360  overfills the recess  312   b  and blankets the first work function metal layer  330  and the third work function metal layer  350 . The filling metal  360  in the recess  312   b  is not in direct contact with the second work function metal layer  340   b  because the second work function metal layer  340   b  underlies the third work function metal layer  350  and is unexposed. The second work function metal layer  340   b  still contributes to the topology of the stepped recess  312   b  and serves its intended function, voltage manipulation. The tripled work function metal layers  330 ,  340   b , and  350  collectively create tapered sidewalls in the recess  312   b  with an additional level in comparison with the doubled work function metal layers  330  and  340   a  in the recess  312   a.    
     Attention is now invited to  FIG. 17 . An etching back is performed to bring down the filling metal  360  and the first work function metal layer  330  within the recesses  312   a  and  312   b  (operation  121  of  FIG. 1 ). A universal etching back does not take different patterns in gate structures into consideration. When only filling metal  360  and the first work function metal layers  330  are the targets in the etching back process, variation between the gate structures is minimized. 
     Still referring to  FIG. 17 , the filling metal  360   a  is lowered to a level within the recesses  312   a  and  312   b  respectively, and the first work function metal layer  330  over the inter-level dielectric layer  319  is removed. The etching back continues until the first work function metal layers  330   a  and  330   b  retreat into the recess  312   a  and  312   b . Slanting edges  332   a  and  332   b  of the first work function metal layers  330   a  and  330   b  respectively are formed during the etching back. The filling metals  360   a  and  360   b  reach to the brim of the first work function metal layers  330   a  and  330   b  in the recesses  312   a  and  312   b . As a result, the filling metals  360   a  and  360   b  have surface areas that are both defined by the first work function metal layers  330   a  and  330   b . In the universal etching back, only the first work function metal layers  330  and the filling metal  360  are removed. Because the second and the third work function metal layers  340   a ,  340   b , and  350  are buried underneath in the recesses  312   a  and  312   b  respectively. When performing the etching back, the loading pattern arising from different numbers of work function metal layers can be omitted. 
     Turning now to  FIGS. 20 and 21 , illustrated zoom in view of the gate structures  300   a  and  300   b . When the universal etching back is performed to lower the surface level of the filling metal  360 , the filling metals  360   a  and  360   b  are brought to the same level within their respective recesses  312   a  and  312   b . Portions of the first work function metal layers  330  are removed in the etching back, while the second and third work function metal layers  340   a  and  350  retain their configuration and are unexposed. A lower portion of the filling metals  360   a  and  360   b  are in contact with the second work function metal layer  340   a  or the third work function metal layer  350 . The work function metal layers  330   a ,  330   b ,  340   a ,  340   b , and  350  serve their intended function, while the work function metal layers  340   a ,  340   b , and  350  is sealed behind the filling metals  360   a  and  360   b . Since the second and third work function metal layers  340   a ,  340   b , and  350  are buried under the filling metals  360   a  and  360   b , even if the loading patterns (i.e., numbers of work function metal layers) in the gate structures  300   a  and  300   b  are different, the topology from a top view is similar. 
     As shown in  FIG. 20 , the first and second work function metal layers  330   a  and  340   a  create tapered sidewalls in the recesses  312   a . The filling metal  360   a  fills in the recess  312   a  and resembles a two-level inverted pyramid. The first work function metal layer  330   a  defines a first width W 1  that is measured from one slanting edge  332  to the other slanting edge  332 . The second work function metal layer  340   a  defines a second width W 2  that is measured from one slanting edges  342   a  to the other slanting edge  342   a . The filling metal  360   a  fills in the tapered recess  312   a , and a first portion  361   a  of the filling metal  360   a  is between the semiconductor substrate  301  and a second portion  362   a  of the filling metal  360   a . The first portion  361   a  of the filling metal  360   a  has the second width W 2 , and a second portion  362   a  of the filling metal  360   a  has the first width W 1 . The filling metal  360   a  fans out from the bottom surface of the recess  312   a  because the second work function metal layer  340   a  is buried underneath. The broader first width W 1  is retained for the filling metal  360   a , and the second work function metal layer  340   a  along with its narrower second width W 2  is unexposed. 
     Likewise, as shown in  FIG. 21 , in addition to the first and second width W 1  and W 2  which are defined by the first and second work function metal layers  330   b  and  340   b  respectively, the third work function metal layer  350  defines a third width W 3  that is measured from one slanting edges  352  to the other slanting edge  352 . The third width W 3  is the narrowest among the three widths because the third work function metal layer  350  is further compressed within the space left out by the second work function metal layer  340   b . The filling metal  360   b  fills in the tapered recess  312   b , and from the bottom to the top are the first portion  361   b , the second portion  362   b  and a third portion  363   b . The third portion  363   b  of the filling metal  360   b  has the broadest first width W 1 . The filling metal  360   a  fans out from the bottom surface of the recess  312   b  because the second and the third work function metal layers  340   b  and  350  are buried under the filling metal  360   b . The broader third portion  363   b  of the filling metal, which has the first width W 1 , is retained, and the narrower first and second portions  361   b  and  362   b  of the filling metal  360   b  are buried underneath. 
     In practical, on top of the width of each of the work function metal layers, the work function metal layers have varied slopes along the sidewalls of the recess. In the recess  312   a  shown in  FIG. 20 , the first work function metal layer  330   a  has a milder slope in comparison with the second work function metal layer  340   a . The second work function metal layer  340   a  has a nearly vertical slope at the bottom of the recess  312   a . The first portion  361   a  of the filling metal  360   a , which fills in the bottom portion of the recess  312   a , has a steeper slope than the second portion  362   a  thereof. As shown in  FIG. 21 , the third work function metal layer  350  adds another level to the tapered sidewalls of the recess  312   b , and the slopes from the top to the bottom surface of the recess  312   b  increases gradually. The first portion  361   b  of the filling metal  360   b  has a nearly vertical slope at the bottom of the recess  312   b , and when it comes to the second portion  362   b  of the filling metal  360   b , the slope becomes milder. The third portion  363   b  of the filling metal  360   b , which is at the top portion of the recess  312   b , has the least steep slope in the recess  312   b.    
     Still referring to  FIGS. 20 and 21 , regardless the element arrangement within the recesses  312   a  and  312   b , a top view of the gate structures  300   a  and  300   b  is similar with only the filling metals  360   a  and  360   b  and the first work function metal layer  330   a  and  330   b  to be found. More than similar exposed elements in different gate structures, the configuration form the top view is uniform as well. The filling metals  360   a  and  360   b  have the same width which is defined by the lip portion of the first work function metal layers  330   a  and  330   b  respectively. The uniform topology of the gate structures  300   a  and  300   b  from the top view have advantageous effects to the subsequent process. 
     Turning now to  FIG. 18 , a protection layer  370 , for example, a nitride layer, fills in the remaining of the recesses  312   a  and  312   b . The protection layer  370  serves to protect the underlying components like the work function metal layers. In either the recess  312   a  or the recess  312   b , the protection layer  370  is held at the same level. In addition, the underlying element arrangement is uniform. The protection layer  370  is in contact with the slanting edges  332   a  and  332   b  of the first work function metal layer  330   a  and  330   b  and the filling metals  360   a  and  360   b . The slanting edges  332   a  and  332   b  of the first work function metal layer  330   a  and  330   b  are at the same height, and the filling metals  360   a  and  360   b  have the same surface area and dimension from a top view. 
     Turning now to  FIG. 19 , a polishing process, for example, CMP is performed, and the gate structures  300   a  and  300   b  are lowered to a level near to the slanting edges  332   a  and  332   b  of the first work function metal layers  330   a  and  330   b . Due to the same topology within the recesses  312   a  and  312   b , the position of the slanting edges  332   a  and  332   b  are taken into consideration. That is, regardless the number of work function metal layers, the protection layer  370  polishing is universally applied to the gate structures  300   a  and  300   b  with the same parameters because the interface topology between the protection layer  370  and in each of the gate structures  300   a  and  300   b  are similar, and the interface are located at the same level. In this case, edges of the work function metal layers are less likely to go through the protection layers  370   a  and  370   b  in the polishing process. 
     The protection layers  370   a  and  370   b  prevent aggressive invasion, for example, chemical agent like acid in the following etching process. In the case when defects are formed in the protection layer, foreign material can cause metal gate missing or compromising the function of other components. By having the same topology even with different loading patterns, when polishing the protection layer, attention is paid to the first work function metal layer and the filling metal without worrying the underlying work function metal layers in different gate structures. 
     Turning now to  FIG. 22 , a gate structure  300   c  is shown with four-layer of work function metal layers. The gate structure  300   c  includes the first, second, third work function metal layers  330   c ,  340   c , and  350   c . In addition, the gate structure  300   c  includes a fourth work function metal layer  380  formed over the third work function metal layer  350   c . Compared to the gate structure  300   b , the gate structure  300   c  goes through one more work function metal layer pull-back in the process. The fourth work function metal layer  380  blankets the third work function metal layer  350   c  within the recess  312   c , and the slanting edges  342   c  and  352   c  are translated into the fourth work function metal layer  380 . The sidewalls of the recess  312   c  show a four-level inverted pyramid with gradually reduced slope from the bottom to the top. The filling metal  360   c  still has the same surface area and topology with the filling metals  360   a  and  360   b  even if the number of work function metal layers increases to four. 
     Apart from the first work function metal layers, the remaining work function metal layers are buried under the filling metal. Etching back of the first work function metal layer and the filling metal will be much easier because other than the first work function metal layer the remaining work function metal layers are not etched during the etching back. The resulting configuration gives similar topology from a top view among different gate structures. 
     In some embodiments of the instant disclosure, a gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the substrate, and the second portion is wider than the first portion. 
     In some embodiments of the instant disclosure, a gate structure includes at least one spacer defining a gate region over a substrate, a gate dielectric layer disposed on the gate region over the substrate, a first work function metal layer disposed over the gate dielectric layer and lining portions of an inner sidewall of the spacer. The first work function metal layer has at least on slanting edge. The gate structure also includes a filling metal partially wrapped by the first work function metal layer. The slanting edge of the first work function metal layer is buried under the filling metal. 
     In some embodiments of the instant disclosure, a method includes forming at least one dummy gate stack including a gate dielectric layer and a dummy gate material layer overlying the gate dielectric layer. An inter-layer dielectric (ILD) layer is formed around the dummy gate stack. At least the dummy gate material layer is removed from the dummy gate stack to form at least one recess. At least one work function metal layer is formed on a bottom surface and at least one sidewall of the recess. A first portion of the work function metal layer is removed from the sidewall of the recess. A second portion of the work function metal layer remains on the sidewall of the recess after the removing. Then, a remaining portion of the recess is filled with a filling metal. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the instant disclosure. Those skilled in the art should appreciate that they may readily use the instant disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the instant disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the instant disclosure.