Patent Publication Number: US-8970605-B2

Title: Display driver with improved power consumption and operation method of improving power consumption of image data processing device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0107506 filed on Oct. 20, 2011 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. 
     BACKGROUND 
     Example embodiments relate to an image data processing scheme, and more particularly, to a display driver, which may reduce power consumption, and/or a method for operating an image data processing device. 
     As the display resolution of portable devices such as smart phones and tablet personal computers (PCs) increases, a memory bandwidth requirement is increased. 
     A large amount of image data is transmitted from an application processor to a display driver. That is, as display resolution increases, power consumed in the application processor and the display driver, which are included in the portable device, increases. 
     In addition, a user may want to display stereoscopic 3D image data by using a display of a portable device. The stereoscopic 3D image data has right and left image data alternately arranged vertically line by line, which may create cross-talk in the stereoscopic 3D image data. 
     SUMMARY 
     According to some example embodiments, there is provided a display driver, including a compressor configured to compress input data and configured to output first data, a first selection circuit configured to transmit the input data or the first data to a memory in response to a first selection signal, a de-compressor configured to output second data by de-compressing third data output from the memory, and a display interface configured to process the second data and create fourth data for transmitting to a display. 
     The display driver may include a control logic circuit configured to generate the first selection signal based on information indicating whether to compress the input data. 
     The display driver may further include a pin configured to receive the first selection signal. 
     The display driver may further include a second selection circuit configured to transmit the input data or the third data to the de-compressor based on a second selection signal. 
     The display driver may further include a control logic circuit configured to generate the first selection signal and the second selection signal based on the input data. 
     The display driver may further include a first pin configured to receive the first selection signal and a second pin configured to receive the second selection signal. 
     The display driver may further include a second selection circuit configured to transmit the input data or the third data to the de-compressor based on a second selection signal, and a third selection circuit configured to transmit the input data or the second data to the display interface based on a third selection signal. 
     The display driver may further include a control logic circuit configured to generate the first selection signal, the second selection signal and the third selection signal based on the input data. 
     The display driver may further include a first pin configured to receive the first selection signal, a second pin configured to receive the second selection signal and a third pin configured to receive the third selection signal. 
     The display driver may further include a second selection circuit configured to transmit the input data or the second data to the display interface based on a second selection signal. 
     If the input data are stereoscopic 3D image data in which right and left pixel data are alternately arranged vertically line by line, the compressor may generate the first data by re-arranging the stereoscopic 3D image data and compressing re-arranged stereoscopic 3D image data. 
     The re-arranged stereoscopic 3D image data may include a left frame and a right frame, the left frame including only left pixel data and the right frame including only right pixel data and being arranged adjacent to the left frame. 
     If the third data are compressed stereoscopic 3D image data, and the de-compressor rearranges the de-compressed stereoscopic 3D image data to generate and output the second data, the de-compressed stereoscopic 3D image data may include a left frame and a right frame. The left frame may include only left pixel data and the right frame may include only right pixel data and may be arranged adjacent to the left frame. The second data may be stereoscopic 3D image data where right and left pixel data are alternately arranged vertically line by line. 
     At least one example embodiment is directed to method for operating an image data processing device. The method may include receiving and rearranging stereoscopic 3D image data in which right and left pixel data are alternately arranged vertically line by line. The method may further include generating compressed stereoscopic 3D image data by compressing re-arranged stereoscopic 3D image data. The re-arranged stereoscopic 3D image data may include a left frame and a right frame. The left frame may include only left pixel data and the right frame may include only right pixel data and may be arranged adjacent to the left frame. 
     The image data processing device may be an application processor or a display driver. 
     The method may further include generating de-compressed stereoscopic 3D image data by de-compressing the compressed stereoscopic 3D image data. The method may further include outputting restored stereoscopic 3D image data where right and left pixel data are alternately arranged vertically line by line. 
     According to some example embodiments, there is provided an image processing device. The image processing device may include an image processing circuit and a compressor. The compressor may be configured to receive stereoscopic input data from the image processing circuit and to arrange the stereoscopic image data such that a left frame of the arranged stereoscopic image data includes only left pixel data of the received stereoscopic input data and a right frame of the arranged stereoscopic image data includes only right pixel data of the received stereoscopic input data. The image processing device may further include a transmission interface configured to transmit data output by the compressor. 
     The compressor may further be configured to compress the arranged stereoscopic image data for transmission by the transmission interface. 
     The compressor may further be configured to insert control information into the arranged stereoscopic image data for transmission by the transmission device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages of example embodiments will become more apparent by describing in detail example embodiments with reference to the attached drawings. The accompanying drawings are intended to depict example embodiments and should not be interpreted to limit the intended scope of the claims. The accompanying drawings are not to be considered as drawn to scale unless explicitly noted. 
         FIG. 1  is a block diagram of an image data processing system according to at least one example embodiment; 
         FIGS. 2-8  are block diagrams of the image data processing system according to example embodiments; 
         FIG. 9  is a flowchart for explaining an operation of the image data processing system illustrated in each of  FIGS. 1 to 8 ; 
         FIG. 10  is a conceptual diagram for explaining a format of general stereoscopic 3D image data; 
         FIG. 11  is a conceptual diagram for explaining a format and compression of stereoscopic 3D image data according to example embodiments; 
         FIG. 12  is a conceptual diagram for explaining a compressor of the display controller illustrated in each of  FIGS. 1 to 8  or an operation thereof; 
         FIG. 13  is a conceptual diagram for explaining an operation of a de-compressor of the display driver illustrated in each of  FIGS. 1 to 8 ; 
         FIG. 14  is a conceptual diagram for explaining an operation where the image data processing system illustrated in each of  FIGS. 1 to 8  processes stereoscopic 3D image data; 
         FIG. 15  is a flowchart for explaining a process where the image data processing system illustrated in each of  FIGS. 1 to 8  processes stereoscopic 3D image data; and 
         FIG. 16  is a block diagram of the image data processing system according to example embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. 
     It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the teachings of the disclosure. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  is a block diagram of an image data processing system according to at least one example embodiment. Referring to  FIG. 1 , the image data processing system  10 A includes an external memory  11 , a first image data processing device, e.g., an application processor  20 A, a second image data processing device, e.g., a display driver  40 A, and a display  60 . 
     An image data processing system ( 10 A to  10 H: collectively  10 ), which will be explained referring to  FIGS. 1 to 8 , may be used for a television (TV), a digital TV (DTV), an internet protocol television (IPTV), a computer or a portable device. 
     The portable device may be a device including a 2-dimensional (D) display  60  or a 3-D display  60 , and may be, for example, a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PDN), a handheld game console or an e-book. 
     The external memory  11  may be a volatile memory for example, a dynamic random access memory (DRAM). Moreover, the external memory  11  may be a non-volatile memory such as, for example, a flash memory, a resistive random access memory (RRAM) or a phase change random access memory (PRAM). 
     The application processor  20 A may control an operation of a display driver  40 A and may transmit data, e.g., image data, 3D image data or stereoscopic 3D image data, to the display driver  40 A. 
     The application processor  20 A may transmit compressed image data (CDATA) or uncompressed image data (DATA) to the display driver  40 A through a channel CH. 
     The application processor  20 A may include a graphics processing unit (GPU)  23 , a memory controller  25  and a display controller  30 A that may communicate with each other through a bus  21 . 
     The GPU  23  controls an operation of the application processor  20 A. For example, the GPU  23  may control a memory controller  25  and a display controller  30 A. According to example embodiments, the application processor  20 A may further include a central processing unit (CPU)  24  controlling an operation of the GPU  23 . Here, the CPU  24  may control an operation of the application processor  20 A overall, and control the memory controller  25  and the display controller  30 A. 
     The memory controller  25  may transmit image data, e.g., moving image data or still image data, output from the external memory  11  to the display controller  30 A through the bus  21 . 
     The display controller  30 A may transmit compressed, or encoded, image data CDATA or uncompressed, or raw, image data DATA to the display driver  40 A through a communication channel CH. For example, the display controller  30 A, in addition to image data DATA or CDATA, may transmit at least one control signal, e.g., a clock signal, a synchronization signal or a signal related to the synchronization signal, which the display driver  40 A may use to process the image data DATA or CDATA sent to the display driver  40 A. 
     The display controller  30 A includes an image processing logic circuit  31 A, a compressor  33 , a selection circuit  35  and a transmission interface  37 . 
     According to a control signal of the GPU  23  or the CPU  24 , the image processing logic circuit  31 A may process image data transmitted from the memory controller  25  and output processed image data. In addition, the image processing logic circuit  31 A may determine whether the image data needs compression and generate a selection signal SELA according to a determination result. 
     The compressor  33  may compress image data DATA output from the image processing logic circuit  31 A at predetermined compression ratio and output compressed image data CDATA. For example, the compressor  33  may be an encoder. The compressor  33  may be controlled by the image processing logic circuit  31 A. 
     The selection circuit  35  may transmit image data CDATA compressed by the compressor  33  or image data DATA output from the image processing logic circuit  31 A, i.e., uncompressed image data, to a transmission interface  37  in response to a selection signal SELA. For example, the selection circuit  35  may be a multiplexer. 
     For example, the application processor  20 A may compress image data to reduce the amount of image data transmitted to the display driver  40 A through a channel CH and/or to reduce the power consumed in each image data processing device  20 A or  40 A. A method of compressing stereoscopic 3D image data is to be explained in detail referring to  FIGS. 11 and 12 . 
     The transmission interface  37  may be, for example, a CPU interface, an RGB interface or a serial interface. According to example embodiments, the transmission interface  37  may be, for example, a mobile display digital interface (MDDI), a mobile industry processor interface (MIPI®), a serial peripheral interface (SPI), an inter IC (I 2 C) interface, an interface supporting a display port (DP), an interface supporting an embedded display port (eDP) or a high-definition multimedia interface (HDMI). 
     The display driver  40 A may receive image data CDATA compressed by the application processor  20 A and store it in the memory  51 , de-compress image data DATA 2  output from the memory  51 , process de-compressed image data DATA 2  and transmit processed image data DATA 4  to a display  60 . 
     In addition, the display driver  40 A may compress uncompressed image data DATA output from the application processor  20 A by using the compressor  43 , store compressed image data in the memory  51 , de-compress image data output from the memory  51  and transmit de-compressed image to the display  60 . 
     The display driver  40 A includes a receiving interface  41 , a compressor  43 , a control logic circuit  45 A, a first selection circuit  47 , a memory controller  49 , a memory  51 , a de-compressor  53  and a display interface  55 . 
     The receiving interface  41  may be the same interface as the transmission interface  37 . The compressor  43  may compress image data output from the receiving interface  41 , e.g., uncompressed image data DATA, and output compressed image data DATA 1 . For example, the compressor  43  which may be embodied in an encoder may be controlled by the control logic circuit  45 A. 
     The control logic circuit  45 A may generate a first selection signal SEL 1  and an access control signal ACC according to control information included in image data DATA or CDATA output from the receiving interface  41 . 
     For example, when uncompressed image data DATA are output from the receiving interface  41 , the control logic circuit  45 A may output a control signal for enabling the compressor  43  and a first selection signal SEL 1  having a first level, e.g., logic 0 or a low level, according to the control information. However, when compressed image data DATA are output from the receiving interface  41 , the control logic circuit  45 A may output a control signal for disabling the compressor  43  and a first selection signal SEL 1  having a second level, e.g., logic 1 or a high level, according to the control information. 
     According to a level of the first selection signal SEL 1 , the first selection circuit  47  may transmit compressed image data CDATA to the memory  51  or transmit image data DATA 1  compressed by the compressor  43  to the memory  51 . For example, when the first selection signal SEL 1  is at a first level, the first selection circuit  47  may transmit data DATA 1  compressed by the compressor  43  to the memory  51 . When the first selection signal SEL 1  is at a second level, the first selection circuit  47  may transmit compressed data CDATA to the memory  51 . 
     The memory controller  49  may control an access operation on the memory  51 , e.g., a write operation writing image data CDATA or DATA  1  to the memory  51  and a read operation reading image data DATA 2  from the memory  51 , according to an access control signal ACC. 
     The memory  51  may store or output image data CDATA or DATA 1  output from the first selection circuit  47  according to a control of the memory controller  49 . For example, the memory  51  may be, for example a frame memory or frame buffer. Accordingly, although resolution of the display  60  increases, a size of the frame memory  51  of the display driver  40 A, which may process compressed image data CDATA or DATA 1 , may be decreased. 
     The de-compressor  53  may receive and de-compress image data DATA 2  output from the memory  51 , and output de-compressed image data DATA 3 . For example, the de-compressor  53 , which may be a decoder, may be controlled by the control logic circuit  45 A. 
     The display interface  55  may process image data DATA 3  output from the de-compressor  53  and transmit processed image data DATA 4  to the display  60 . For example, a display interface  55  may convert image data DATA 3 , which is a digital signal, into an image signal DATA 4  which is an analog signal. 
     The display  60  may display image corresponding to the image signal DATA 4  output from the display driver  40 A. The display  60  may display a 2-D image or a stereoscopic 3D image. The display  60  may be, for example, a thin film transistor-liquid crystal display (FTF-LCD), a light emitting diode (LED) display, an organic LED (OLED) display or an active-matrix OLEC (AMOLED) display. 
       FIG. 2  is a block diagram of the image data processing system according to example embodiments. Referring to  FIG. 2 , the image data processing system  10 B includes the external memory  11 , a first image data processing device, e.g., an application processor  20 B, a second image data processing device e.g., a display driver  40 B, and the display  60 . 
     Referring to  FIGS. 1 and 2 , the application processor  20 B includes an external pin  20 - 1  for receiving a selection signal SELA for controlling an operation of the selection circuit  35 . For example, when the external pin  20 - 1  is connected to a power supply line supplying power or supply voltage Vdd through a switch  20 - 2 , the selection signal SELA is set to a second level. When the external pin  20 - 1  is connected to ground VSS through the switch  20 - 2 , the selection signal SELA is set to a first level. 
     Accordingly, the selection circuit  35  outputs image data CDATA compressed by the compressor  33  according to a selection signal SELA having a first level and outputs image data DATA output from an image processing logic circuit  31 B according to a selection signal SELA having a second level. 
     The display driver  40 B includes a first external pin  40 - 1  for receiving a first selection signal SEL 1  for controlling an operation of the first selection circuit  47 . That is, the control logic circuit  45 A of  FIG. 1  outputs a first selection SEL 1  and an access control signal ACC automatically according to control information. On the other hand, the control logic circuit  45 B of  FIG. 2  outputs an access control signal ACC according to control information and does not output a first selection SEL 1 . 
     For example, when the first external pin  40 - 1  is connected to a power supply line supplying power or supply voltage Vdd through the first switch  40 - 2 , a first selection signal SEL 1  is set to a second level. When the first external pin  40 - 1  is connected to ground VSS through the first switch  40 - 2 , the first selection signal SEL 1  is set to a first level. Accordingly, the first selection circuit  47  outputs image data DATA 1  compressed by the compressor  43  according to a first selection signal SEL 1  having a first level, and the first selection circuit  47  outputs image data DATA or CDATA output from the receiving interface  41  according to a first selection signal SEL 1  having a second level. 
       FIG. 3  is a block diagram of the image data processing system according to example embodiments. An image data processing system  10 C includes an external memory  11 , the application processor  20 A or  20 B, a display driver  40 C and the display  60 . 
     Except for a control logic circuit  45 C and a second selection circuit  54 , the display driver  40 A of  FIG. 1  has substantially the same structure as a display driver  40 C of  FIG. 3 . 
     The control logic circuit  45 C generates a first selection signal SEL 1 , a second selection signal SEL 2  and an access control signal ACC according to control information included in image data CDATA or DATA. 
     According to a second selection signal SEL 2 , the second selection circuit  54  may transmit image data DATA 2  output from the memory  51  or data DATA or CDATA output from the receiving interface  41  to the de-compressor  53 . For example, the second selection circuit  54  outputs image data output from the memory  51  according to a second selection signal SEL 2  having a first level and the second selection circuit  54  outputs image data DATA or CDATA output from the receiving interface  41  according to a second selection signal SEL 2  having a second level. 
     For example, when the control logic circuit  45 C outputs a first selection signal SEL 1  having a second level and a second selection signal SEL 2  having a first level according to the control information, compressed image data CDATA may be transmitted to the de-compressor  53  through the memory  51 . 
     In addition, when the control logic circuit  45 C outputs a first selection signal SEL 1  having a first level and a second selection signal SEL 2  having a second level and outputs a control signal that may disable the compressor  43 , compressed image data CDATA may bypass the memory  51  and be transmitted to the de-compressor  53 . When the control logic circuit  45 C outputs a first selection signal SEL 1  having a first level and a second selection signal having a first level and outputs a control signal that may enable the compressor  43 , uncompressed image data DATA may be transmitted to the de-compressor  53  through the first selection circuit  47 , the memory  51  and the second selection circuit  54  after being compressed by the compressor  43 . 
       FIG. 4  is a block diagram of the image data processing system according to example embodiments. An image data processing system  10 D includes the external memory  11 , the application processor  20 A or  20 B, the display driver  40 D and the display  60 . 
     Except for a second external pin  40 - 3  and the second selection circuit  54 , the display driver  40 B of  FIG. 2  has substantially the same structure as the display driver  40 D of  FIG. 4 . 
     When a second external pin  40 - 3  is connected to a power supply line supplying power Vdd through a second switch  40 - 4 , a second selection signal SEL 2  is set to a second level. When the second external pin  40 - 3  is connected to ground VSS through the second switch  40 - 4 , the second selection signal SEL 2  is set to a first level. Accordingly, the second selection circuit  54  outputs image data DATA 2  output from the memory  51  according to a second selection signal SEL 2  having a first level, and the second selection circuit  54  outputs image data DATA or CDATA output from the receiving interface  41  according to a second selection signal SEL 1  having a second level. 
       FIG. 5  is a block diagram of the image data processing system according to example embodiments. An image data processing system  10 E includes the external memory  11 , the application processor  20 A or  20 B, a display driver  40 E and the display  60 . 
     Except for a control logic circuit  45 E and a third selection circuit  56 , the display driver  40 C of  FIG. 3  has substantially the same structure as a display driver  40 E of  FIG. 5 . The control logic circuit  45 E generates a first selection signal SEL 1 , a second selection signal SEL 2 , a third selection signal SEL 3  and an access control signal ACC according to control information included in data DATA or CDATA output from the receiving interface  41 . 
     According to a third selection signal SEL 3 , the third selection circuit  56  may transmit image data DATA 3  output from the de-compressor  53  or image data CDATA output from the receiving interface  41  to the display interface  55 . For example, the third selection circuit  56  outputs image data DATA 3  output from the de-compressor  53  according to a third selection signal SEL 3  having a first level and the third selection circuit  56  outputs image data DATA or CDATA output from the receiving interface  41  according to a third selection signal SEL 3  having a second level. 
     According to a level of each selection signal SEL 1 , SEL 2  or SEL 3  output from the control logic circuit  45 E, uncompressed image data DATA output from the receiving interface  41  may be transmitted from the receiving interface  41  to the display interface  55  without intermediate transformation or storage. 
       FIG. 6  is a block diagram of the image data processing system according to example embodiments. An image data processing system  10 F includes the external memory  11 , the application processor  20 A or  20 B, a display driver  40 F and the display  60 . 
     Except for a third external pin  40 - 5  and the third selection circuit  56 , the display driver  40 D of  FIG. 4  has substantially the same structure as a display driver  40 F of  FIG. 6 . 
     When the third external pin  40 - 5  is connected to a power supply line supplying power Vdd through a third switch  40 - 6 , a third selection signal SEL 3  is set to a second level. When the third external pin  40 - 5  is connected to a ground VSS through the third switch  40 - 6 , the third selection signal SEL 3  is set to a first level. Accordingly, the third selection circuit  56  outputs image data DATA 3  output from the de-compressor  53  according to a third selection signal SEL 3  having a first level, and the third selection circuit  56  outputs image data DATA or CDATA output from the receiving interface  41  according to a third selection signal SEL 3  having a second level. 
       FIG. 7  is a block diagram of the image data processing system according to example embodiments. An image data processing system  10 G includes the external memory  11 , the application processor  20 A or  20 B, a display driver  40 G and the display  60 . 
     Except for a control logic circuit  45 G and a second selection circuit  56 ′, the display driver  40 A of  FIG. 1  has substantially the same structure as a display driver  40 G of  FIG. 7 . 
     The control logic circuit  45 G generates a first selection signal SEL 1 , a second selection signal SEL 2 ′ and an access control signal ACC according to control information included in image data DATA or CDATA output from the receiving interface  41 . 
     According to a second selection signal SEL 2 ′, the second selection circuit  56 ′ may transmit image data DATA 3  output from the de-compressor  53  or image data DATA or CDATA output from the receiving interface  41  to the display interface  55 . 
     For example, the second selection circuit  56 ′ outputs image data DATA 3  output from the de-compressor  53  according to a second selection signal SEL 2 ′ having a first level, and outputs image data DATA or CDATA output from the receiving interface  41  according to a second selection signal SEL 2 ′ having a second level. 
       FIG. 8  is a block diagram of the image data processing system according to example embodiments. An image data processing system  10 H includes the external memory  11 , the application processor  20 A or  20 B, a display driver  40 H and the display  60 . 
     Except for a second external pin  40 - 5 ′ and a second selection circuit  56 ′, the display driver  40 B of  FIG. 2  has substantially the same structure as a display driver  40 H of  FIG. 8 . 
     When the second external pin  40 - 5 ′ is connected to a power supply line supplying power Vdd through a second switch  40 - 6 ′, a second selection signal SEL 2 ′ is set to a second level. When the second external pin  40 - 5 ′ is connected to a ground VSS through the second switch  40 - 6 ′, the second selection signal SEL 2 ′ is set to a first level. 
     Accordingly, the second selection circuit  56 ′ outputs image data DATA 3  output from the de-compressor  53  according to a second selection signal SEL 2 ′ having a first level, and outputs image data DATA or CDATA output from the receiving interface  41  according to a second selection signal SEL 2 ′ having a second level. 
     In  FIGS. 2 ,  4 ,  6  and  8 , each switch  20 - 2 ,  40 - 2 ,  40 - 4 ,  40 - 6  or  40 - 6 ′ is connected to each external pin  20 - 1 ,  40 - 1 ,  40 - 3 ,  40 - 5  or  40 - 5 ′ as illustrated to set a level of each selection signal SELA, SEL 1 , SEL 2 , SEL 3  or SEL 2 ′. However, it will be understood that this is for illustration purposes only and that the level of a selection signal may be set by any other method that would be understood by one of ordinary skill. 
     Each switch  20 - 2 ,  40 - 2 ,  40 - 4 ,  40 - 6  or  40 - 6 ′ may be replaced with, for example, a fuse, an anti-fuse or an e-fuse. Additionally, a level of each selection signal SELA, SEL 1 , SEL 2 , SEL 3  or SEL 2 ′ may be set by, for example, a manufacturer of a display driver ( 40 A to  40 H: collectively  40 ) and a mode register set (MRS) may be used as a means for setting each level of the selection signal SELA, SEL 1 , SEL 2 , SEL 3  and SEL 2 ′. 
       FIG. 9  is a flowchart for explaining an operation of the image data processing system according to example embodiments illustrated in  FIGS. 1 to 8 . Referring to  FIGS. 1 to 9 , according to whether a level of each selection signal SELA, SEL 1 , SEL 2 , SEL 3  or SEL 2 ′ is set to a specific level, e.g., a first level or a second level, a channel or data path may be set through which image data output by the application processor  20 A or  20 B are processed. 
     The level of each selection signal SELA, SEL 1 , SEL 2 , SEL 3 , or SEL 2 ′ may be set by a control logic circuit  45 A,  45 C,  45 E or  45 G, illustrated in  FIG. 1 ,  3 ,  5  or  7 , or the level of each selection signal SELA, SEL 1 , SEL 2 , SEL 3 , or SEL 2 ′ may be set by at least an external pin  40 - 1 ,  40 - 3 ,  40 - 5  or  40 - 5 ′ as illustrated in  FIG. 2 ,  4 ,  6  or  8 . 
     When image data DATA output from the application processor ( 20 A or  20 B; collectively  20 ) are uncompressed image data, image data DATA output from the receiving interface  41  are compressed by the compressor  43  (S 20 ) and compressed image data DATA 1  are stored in the memory  51  (S 30 ). 
     The de-compressor  53  de-compresses image data DATA 2  output from the memory  51  (S 40 ). The display interface  55  processes de-compressed image data DATA 3  and transmits processed image data DATA 4  to the display  60  (S 50 ). However, when image data CDATA output from the application processor  20  are already compressed image data, compressed image data CDATA output from the receiving interface  41  are stored in the memory  51  through the first selection circuit  47  (S 32 ). 
     The de-compressor  53  de-compresses image data DATA 2  output from the memory  51  (S 42 ). The display interface  55  processes de-compressed image data DATA 3  and transmits processed image data DATA 4  to the display  60  (S 50 ). 
       FIG. 10  is a conceptual diagram for explaining a format of general stereoscopic 3D image data. Referring to  FIG. 10 , a conventional stereoscopic 3D image data format S 3 D includes odd-numbered vertical pixel data of right image data RI and even-numbered vertical pixel data of left image data LI, or the conventional stereoscopic 3D image data format S 3 D includes even-numbered vertical pixel data of right image data RI and odd-numbered vertical pixel data of left image data LI. That is, the conventional stereoscopic 3D image data format S 3 D has left pixel data and right pixel data alternately arranged vertically line-by-line. 
     The conventional stereoscopic 3D image data format S 3 D includes half of the right image data RI and half of the left image data RI, so that image-quality deterioration may occur. Moreover, a display displaying stereoscopic 3D image data, i.e., a parallax barrier included in a stereoscopic 3D image panel, is fixed, so that a horizontal stripe may be seen in the stereoscopic 3D image panel. For example, when resolution of each image data RI or LI is a wide extended graphics array (WXGA), resolution of the stereoscopic 3D image data format S 3 D may be WXGA. 
       FIG. 11  is a conceptual diagram for explaining a format and compression of stereoscopic 3D image data according to example embodiments. Referring to  FIG. 11 , in contrast to the conventional stereoscopic 3D image data format S 3 D, a re-arranged stereoscopic 3D image data format PS 3 D includes a left frame including only left pixel data and a right frame including only right pixel. The left frame and the right frame are arranged adjacent to each other. Accordingly, cross-talk which may be generated in the display  60  may be reduced or prevented. 
     Each compressor  33  or  43  illustrated in  FIGS. 1 to 8  may generate a compressed stereoscopic 3D image data format CDATA or DATA 1  by compressing the re-arranged stereoscopic 3D image data format PS 3 D. For example, compressed stereoscopic 3D image data C 1 , which are included in the compressed stereoscopic 3D image data format CDATA or DATA 1 , include only right pixel data R 1 , R 3 , R 11  and R 13 . Compressed stereoscopic 3D image data C 3  include right pixel data R 9  and R 19  and left pixel data L 2  and L 12 . 
     To prevent cross-talk that may have a visible effect on the data, the display driver  40  illustrated in  FIGS. 1 to 8  may not process compressed stereoscopic 3D image data CPM that includes pixel data located on a boundary line BD between a left frame and a right frame. 
       FIG. 12  is a conceptual diagram for explaining a compressor of the display controller illustrated in each of  FIGS. 1 to 8  or an operation thereof.  FIG. 12  illustrates a stereoscopic image data format for displaying full resolution stereoscopic image data, and each of S 3 D 1  and S 3 D 2  includes pixel data corresponding to half of full resolution. 
     When the application processor  20  outputs compressed stereoscopic image data CDATA, an operation of the compressor  33  of the display controller  30  according to example embodiments is as follows. 
     The compressor  33  generates re-arranged first stereoscopic image data PS 3 D 1  by re-arranging first stereoscopic image data S 3 D 1  output from the image processing logic circuit  31 . The compressor  33  generates compressed stereoscopic image data CD 1  by compressing the re-arranged first stereoscopic image data PS 3 D 1 . The re-arranged first stereoscopic image data PS 3 D 1  include a right frame including only right pixel data and a left frame including only left pixel data. 
     The compressor  33  generates re-arranged second stereoscopic image data PS 3 D 2  by re-arranging second stereoscopic image data S 3 D 2  output from the image processing logic circuit  31  and generates compressed second stereoscopic image data CD 2  by compressing the re-arranged second stereoscopic image data PS 3 D 2 . The re-arranged second stereoscopic image data PS 3 D 2  includes a right frame including only right pixel data and a left frame including only left pixel data. 
     When the compressor  43  of the display driver  40  outputs compressed data DATA 1  by compressing uncompressed data DATA, an operation of the compressor  43  of the display driver  40  is as follows. 
     The compressor  43  generates re-arranged first stereoscopic image data PS 3 D 1  by re-arranging first stereoscopic image data S 3 D 1  output through the receiving interface  41  and the compressor  43  generates compressed first stereoscopic image data CD 1  by compressing the re-arranged first stereoscopic image data PS 3 D 1 . In addition, the compressor  43  generates re-arranged second stereoscopic image data PS 3 D 2  by re-arranging second stereoscopic image data S 3 D 2  output through the receiving interface  41  and the compressor  43  generates compressed second stereoscopic image data CD 2  by compressing the re-arranged second stereoscopic image data PS 3 D 2 . 
       FIG. 13  is a conceptual diagram for explaining an operation of a de-compressor of the display driver in example embodiments illustrated in  FIGS. 1 to 8 . The de-compressor  53  of the display driver  40  generates re-arranged first stereoscopic image data PS 3 D 1  by de-compressing compressed first stereoscopic image data CD 1  and the de-compressor  53  generates restored first stereoscopic image data RS3D 1  by re-arranging the re-arranged first stereoscopic image data PS 3 D 1 . 
     In addition, the de-compressor  53  of the display driver  40  generates re-arranged second stereoscopic image data PS 3 D 2  by de-compressing compressed second stereoscopic image data CD 2  and the de-compressor  53  generates restored second stereoscopic image data RS3D 2  by re-arranging the re-arranged second stereoscopic image data PS 3 D 2 . 
       FIG. 14  is a conceptual diagram for explaining an operation in which the image data processing system in example embodiments illustrated in  FIGS. 1 to 8  processes stereoscopic 3D image data. 
     The compressor  33  of the display controller  30  transmits compressed stereoscopic image data to the display driver  40 , the de-compressor  53  of the display driver  40  de-compresses compressed stereoscopic image data, and the display  60  displays de-compressed stereoscopic image data output from the display driver  40 . 
     The display  60  includes a plurality of light sources and a plurality of parallax barriers. Each location of the plurality of parallax barriers included in the display  60 , which may display full-resolution stereoscopic 3D image data, may change to alternately display the right image and the left image. 
     While a conventional display displays half-resolution image at 60 Hz, the display  60  of example embodiments may display full-resolution image at 120 Hz. 
       FIG. 15  is a flow chart for explaining a process in which the image data processing system of example embodiments illustrated in  FIGS. 1 to 8  processes stereoscopic 3D image data. Referring to  FIGS. 11 to 15 , the compressor  33  of the application processor  20  receives stereoscopic 3D image data S 3 D 1  and S 3 D 2  (S 110 ), re-arranges received stereoscopic 3D image data S 3 D 1  and S 3 D 2  to have a format as illustrated in  FIG. 12  (S 120 ), compresses re-arranged stereoscopic 3D image data PS 3 D 1  and PS 3 D 2 , and transmits compressed stereoscopic 3D image data CDATA 1  and CDATA 2  to the display driver  40  through the transmission interface  37  and a channel CH. 
     However, when stereoscopic 3D image data output from the application processor  20  are uncompressed image data, the compressor  43  of the display driver  40  may receive stereoscopic 3D image data S 3 D 1  and S 3 D 2  output from the receiving interface  41  (S 110 ), re-arrange received stereoscopic 3D image data S 3 D 1  and S 3 D 2  to have a format as illustrated in  FIG. 12  (S 120 ), compress re-arranged stereoscopic 3D image data PS 3 D 1  and PS 3 D 2 , and transmit compressed stereoscopic 3D image data CDATA 1  and CDATA 2  to the memory  51  through the first selection circuit  47 . 
     That is, steps S 110  to S 130  may be performed by the compressor  33  of the application processor  20  or the compressor  43  of the display driver  40 . 
     The de-compressor  53  of the display driver  40  receives compressed stereoscopic 3D image data DATA 2  output from the memory  51  or compressed stereoscopic 3D image data CDATA from the second selection circuit  54 , de-compresses compressed stereoscopic 3D image data CDATA in the same manner as discussed above with regard to  FIG. 13  (S 140 ), re-arranges de-compressed stereoscopic 3D image data (S 150 ), and transmits re-arranged stereoscopic 3D image data to the display  60  (S 160 ). 
       FIG. 16  is a block diagram of the image data processing system according to at least one example embodiment. The image data processing system  200  of  FIG. 16  may be a device using or supporting a mobile industry processor interface (MIPI®), e.g., a mobile phone, a smart phone or a tablet personal computer. 
     The image data processing system  200  includes an application processor  210 , an image sensor  220  and a display  230 . The application processor  210  may include the display controller  30 A or  30 B illustrated in  FIG. 1  or  2 . 
     A camera serial interface (CSI) host  212  embodied in the application processor  210  may perform a serial communication with a CSI device  221  of the image sensor  220  through a camera serial interface (CSI). According to an example embodiment, a de-serializer DES may be embodied in the CSI host  212  and a serializer SER may be embodied in the CSI device  221 . 
     A display serial interface (DSI) host  211  of the application processor  210  may perform a serial communication with a DSI device  231  of the display  230  through a display serial interface. According to example embodiments, the DSI host  211  may include a serializer SER and the DSI device  231  may include a de-serializer DES. The DSI host  211  or the DSI device  231  may include one of display drivers  40 A to  40 H in example embodiments illustrated in  FIGS. 1 to 8 . 
     The image data processing system  200  may further include an RF chip  240  that may communicate with the application processor  210 . A PHY  213  of the application processor  210  and a PHY  241  of a RF chip  240  may transmit or receive data according to MIPI DigRF. 
     The application processor  210  may further include a GPS receiver  250 , a volatile memory  252  such as a dynamic random access memory (DRAM), a data storage device  254  including a non-volatile memory device such as a NAND flash memory, a microphone  256  or a speaker  258 . Moreover, the application processor  210  may communicate with an external device by using at least a communication protocol or a communication standard, e.g., ultra-wideband (UWB)  260 , Wireless LAN (WLAN)  262 , worldwide interoperability for microwave access (WiMAX)  264  or long-term evolution (LTE™). 
     An application processor according to example embodiments, to reduce transmission amount of image data, may compress the image data and transmit compressed image data at high speed. Power consumed in the application processor, which may transmit compressed image data, may be reduced. The application processor may also reduce a size of a frame memory embodied in a display driver that may process compressed image data. 
     An application processor, which may re-arrange stereoscopic 3D image data, compress re-arranged stereoscopic 3D image data and transmit compressed stereoscopic 3D image data, may reduce the amount of data transmitted to a display driver. The display driver, which may process re-arranged stereoscopic 3D image data, may display full resolution image to a display while also reducing cross-talk. 
     While example embodiments have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the example embodiments as defined by the following claims.