Patent Publication Number: US-2023154541-A1

Title: Soft erase process during programming of non-volatile memory

Description:
BACKGROUND 
     The present disclosure relates to non-volatile storage. 
     Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). One example of non-volatile memory is flash memory (e.g., NAND-type and NOR-type flash memory). 
     Users of non-volatile memory can program (i.e., write) data to the non-volatile memory and later read that data back. For example, a digital camera may take a photograph and store the photograph in non-volatile memory. Later, a user of the digital camera may view the photograph by having the digital camera read the photograph from the non-volatile memory. Because users often rely on the data they store, it is important to users of non-volatile memory to be able to store data reliably so that it can be read back successfully. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Like-numbered elements refer to common components in the different figures. 
         FIG.  1    is a block diagram depicting one embodiment of a storage system. 
         FIG.  2 A  is a block diagram of one embodiment of a memory die. 
         FIG.  2 B  is a block diagram of one embodiment of an integrated memory assembly. 
         FIGS.  3 A and  3 B  depict different embodiments of integrated memory assemblies. 
         FIG.  4    is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure. 
         FIG.  4 A  is a block diagram of one embodiment of a memory structure having two planes. 
         FIG.  4 B  depicts a top view of a portion of one embodiment of a block of memory cells. 
         FIG.  4 C  depicts a cross sectional view of a portion of one embodiment of a block of memory cells. 
         FIG.  4 D  depicts a cross sectional view of a portion of one embodiment of a block of memory cells. 
         FIG.  4 E  depicts a cross sectional view of a portion of one embodiment of a block of memory cells. 
         FIG.  4 F  is a cross sectional view of one embodiment of a vertical column of memory cells. 
         FIG.  4 G  depicts a cross section of as memory hole that implements a vertical NAND string. 
         FIG.  4 H  depicts a cross section of as memory hole that implements a vertical NAND string. 
         FIG.  4 I  depicts a cross section of as memory hole that implements a vertical NAND string. 
         FIG.  4 J  is a schematic of a plurality of NAND strings in multiple sub-blocks of a same block. 
         FIG.  5 A  depicts threshold voltage distributions. 
         FIG.  5 B  depicts threshold voltage distributions. 
         FIG.  5 C  depicts threshold voltage distributions. 
         FIG.  5 D  depicts threshold voltage distributions. 
         FIG.  5 E  depicts threshold voltage distributions. 
         FIG.  5 F  depicts threshold voltage distributions. 
         FIG.  6    is a flow chart describing one embodiment of a process for programming non-volatile memory. 
         FIGS.  7 A and  7 B  depict threshold voltage distributions and explain Foggy-Fine programming. 
         FIG.  8    is a flow chart describing one embodiment of a process for programming that includes a soft erase process. 
         FIG.  9    is a flow chart describing one embodiment of a process for programming that includes a soft erase process. 
         FIG.  10    is a flow chart describing one embodiment of a process for programming that includes a soft erase process. 
         FIG.  11    is a timing diagram that depicts one embodiment of the soft erase process. 
         FIG.  12    is a flow chart describing one embodiment of a process for programming that includes a soft erase process. 
         FIG.  13    is a flow chart describing one embodiment of a process for programming that includes a soft erase process. 
         FIG.  14    is a flow chart describing one embodiment of a process for programming that includes a soft erase process. 
     
    
    
     DETAILED DESCRIPTION 
     To increase capacity while keeping costs low, manufacturers of non-volatile memory have been trying to increase the number of bits stored in each memory cell. However, as the number of bits per memory cell increases, the number of threshold voltage distributions that need to be squeezed into the window of operation increases. The greater the number of threshold voltage distributions, the smaller the distance between threshold voltage distributions (or between peaks of threshold voltage distributions). With less distance between threshold voltage distributions, data retention issues can cause threshold voltage distributions to widen which may lead to errors when reading data. Therefore, to maintain narrow threshold voltage distributions and reduce errors when reading data due to data retention issues, it is proposed to perform a soft erase process during the programming of data. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging. The use of the soft programming process improves data retention properties of the memory, maintains the narrow widths of the programmed threshold voltage distributions, and reduces errors when reading data. 
       FIG.  1    is a block diagram of one embodiment of a storage system  100  that implements the proposed technology described herein. In one embodiment, storage system  100  is a solid state drive (“SSD”). Storage system  100  can also be a memory card, USB drive or other type of storage system. The proposed technology is not limited to any one type of memory system. Storage system  100  is connected to host  102 , which can be a computer, server, electronic device (e.g., smart phone, tablet or other mobile device), appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, host  102  is separate from, but connected to, storage system  100 . In other embodiments, storage system  100  is embedded within host  102 . 
     The components of storage system  100  depicted in  FIG.  1    are electrical circuits. Storage system  100  includes a memory controller  120  connected to non-volatile memory  130  and local high speed volatile memory  140  (e.g., DRAM). Local high speed volatile memory  140  is used by memory controller  120  to perform certain functions. For example, local high speed volatile memory  140  stores logical to physical address translation tables (“L2P tables”). 
     Memory controller  120  comprises a host interface  152  that is connected to and in communication with host  102 . In one embodiment, host interface  152  implements a NVM Express (NVMe) over PCI Express (PCIe). Other interfaces can also be used, such as SCSI, SATA, etc. Host interface  152  is also connected to a network-on-chip (NOC)  154 . A NOC is a communication subsystem on an integrated circuit. NOC&#39;s can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, NOC  154  can be replaced by a bus. Connected to and in communication with NOC  154  is processor  156 , ECC engine  158 , memory interface  160 , and DRAM controller  164 . DRAM controller  164  is used to operate and communicate with local high speed volatile memory  140  (e.g., DRAM). In other embodiments, local high speed volatile memory  140  can be SRAM or another type of volatile memory. 
     ECC engine  158  performs error correction services. For example, ECC engine  158  performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine  158  is an electrical circuit programmed by software. For example, ECC engine  158  can be a processor that can be programmed. In other embodiments, ECC engine  158  is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine  158  is implemented by processor  156 . 
     Processor  156  performs the various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor  156  is programmed by firmware. In other embodiments, processor  156  is a custom and dedicated hardware circuit without any software. Processor  156  also implements a translation module, as a software/firmware process or as a dedicated hardware circuit. In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die. To implement this system, memory controller  120  (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation is to maintain tables (i.e. the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that the local memory  140  cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in a memory die  130  and a subset of the L2P tables are cached (L2P cache) in the local high speed volatile memory  140 . 
     Memory interface  160  communicates with non-volatile memory  130 . In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface  160  (or another portion of controller  120 ) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die. 
     In one embodiment, non-volatile memory  130  comprises one or more memory die.  FIG.  2 A  is a functional block diagram of one embodiment of a memory die  200  that comprises non-volatile memory  130 . Each of the one or more memory die of non-volatile memory  130  can be implemented as memory die  200  of  FIG.  2 A . The components depicted in  FIG.  2 A  are electrical circuits. Memory die  200  includes a memory array  202  that can comprise non-volatile memory cells, as described in more detail below. The array terminal lines of memory array  202  include the various layer(s) of word lines organized as rows, and the various layer(s) of bit lines organized as columns. However, other orientations can also be implemented. Memory die  200  includes row control circuitry  220 , whose outputs  208  are connected to respective word lines of the memory array  202 . Row control circuitry  220  receives a group of M row address signals and one or more various control signals from System Control Logic circuit  206 , and typically may include such circuits as row decoders  222 , array terminal drivers  224 , and block select circuitry  226  for both reading and writing (programming) operations. Row control circuitry  220  may also include read/write circuitry. Memory die  200  also includes column control circuitry  210  including sense amplifier(s)  230  whose input/outputs  206  are connected to respective bit lines of the memory array  202 . Although only single block is shown for array  202 , a memory die can include multiple arrays that can be individually accessed. Column control circuitry  210  receives a group of N column address signals and one or more various control signals from System Control Logic  260 , and typically may include such circuits as column decoders  212 , array terminal receivers or driver circuits  214 , block select circuitry  216 , as well as read/write circuitry, and I/O multiplexers. 
     System control logic  260  receives data and commands from memory controller  120  and provides output data and status to the host. In some embodiments, the system control logic  260  (which comprises one or more electrical circuits) include state machine  262  that provides die-level control of memory operations. In one embodiment, the state machine  262  is programmable by software. In other embodiments, the state machine  262  does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine  262  is replaced by a micro-controller or microprocessor, either on or off the memory chip. System control logic  262  can also include a power control module  264  that controls the power and voltages supplied to the rows and columns of the memory structure  202  during memory operations and may include charge pumps and regulator circuit for creating regulating voltages. System control logic  262  includes storage  366  (e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating the memory array  202 . 
     Commands and data are transferred between memory controller  120  and memory die  200  via memory controller interface  268  (also referred to as a “communication interface”). Memory controller interface  268  is an electrical interface for communicating with memory controller  120 . Examples of memory controller interface  268  include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used. 
     In some embodiments, all the elements of memory die  200 , including the system control logic  260 , can be formed as part of a single die. In other embodiments, some or all of the system control logic  260  can be formed on a different die. 
     In one embodiment, memory structure  202  comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping layers. 
     In another embodiment, memory structure  202  comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used. 
     The exact type of memory array architecture or memory cell included in memory structure  202  is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure  202 . No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure  202  include ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure  202  include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like. 
     One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature. 
     Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer&#39;s magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below. 
     Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of “pulse” in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate. 
     A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art. 
     The elements of  FIG.  2 A  can be grouped into two parts: (1) memory structure  202  and (2) peripheral circuitry, which includes all the components depicted in  FIG.  2 A  other than memory structure  202 . An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory die of storage system  100  that is given over to the memory structure  202 ; however, this reduces the area of the memory die available for the peripheral circuitry. This can place quite severe restrictions on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to the system control logic  260 , reduced availability of area can limit the available functionalities that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory die for the storage system  100  is the amount of area to devote to the memory structure  202  and the amount of area to devote to the peripheral circuitry. 
     Another area in which the memory structure  202  and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure  202  is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic  260  often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies. 
     To improve upon these limitations, embodiments described below can separate the elements of  FIG.  2 A  onto separately formed dies that are then bonded together. More specifically, the memory structure  202  can be formed on one die (referred to as the memory die) and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on a separate die (referred to as the control die). For example, a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved on to a separate control die. This allows each of the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS based memory array structure, without worrying about the CMOS elements that have now been moved onto a control die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array. The two die can then be bonded together in a bonded multi-die memory circuit, with the array on the one die connected to the periphery elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more die, such as two memory die and one control die, for example. 
       FIG.  2 B  shows an alternative arrangement to that of  FIG.  2 A  which may be implemented using wafer-to-wafer bonding to provide a bonded die pair.  FIG.  2 B  depicts a functional block diagram of one embodiment of an integrated memory assembly  207 . One or more integrated memory assemblies  207  may be used to implement the non-volatile memory  130  of storage system  100 . The integrated memory assembly  207  includes two types of semiconductor die (or more succinctly, “die”). Memory die  201  includes memory structure  202 . Memory structure  202  includes non-volatile memory cells. Control die  211  includes control circuitry  260 ,  210 , and  220  (as described above). In some embodiments, control die  211  is configured to connect to the memory structure  202  in the memory die  201 . In some embodiments, the memory die  201  and the control die  211  are bonded together. 
       FIG.  2 B  shows an example of the peripheral circuitry, including control circuits, formed in a peripheral circuit or control die  211  coupled to memory structure  202  formed in memory die  201 . Common components are labelled similarly to  FIG.  2 A . System control logic  260 , row control circuitry  220 , and column control circuitry  210  are located in control die  211 . In some embodiments, all or a portion of the column control circuitry  210  and all or a portion of the row control circuitry  220  are located on the memory die  201 . In some embodiments, some of the circuitry in the system control logic  260  is located on the on the memory die  201 . 
     System control logic  260 , row control circuitry  220 , and column control circuitry  210  may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller  120  may require few or no additional process steps (i.e., the same process steps used to fabricate controller  120  may also be used to fabricate system control logic  260 , row control circuitry  220 , and column control circuitry  210 ). Thus, while moving such circuits from a die such as memory  2  die  201  may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die  211  may not require many additional process steps. The control die  211  could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry  260 ,  210 ,  220 . 
       FIG.  2 B  shows column control circuitry  210  including sense amplifier(s)  230  on the control die  211  coupled to memory structure  202  on the memory die  201  through electrical paths  206 . For example, electrical paths  206  may provide electrical connection between column decoder  212 , driver circuitry  214 , and block select  216  and bit lines of memory structure  202 . Electrical paths may extend from column control circuitry  210  in control die  211  through pads on control die  211  that are bonded to corresponding pads of the memory die  201 , which are connected to bit lines of memory structure  202 . Each bit line of memory structure  202  may have a corresponding electrical path in electrical paths  306 , including a pair of bond pads, which connects to column control circuitry  210 . Similarly, row control circuitry  220 , including row decoder  222 , array drivers  224 , and block select  226  are coupled to memory structure  202  through electrical paths  208 . Each of electrical path  208  may correspond to a word line, dummy word line, or select gate line. Additional electrical paths may also be provided between control die  211  and memory die  201 . 
     For purposes of this document, the phrases “a control circuit” or “one or more control circuits” can include any one of or any combination of memory controller  120 , state machine  262 , all or a portion of system control logic  260 , all or a portion of row control circuitry  220 , all or a portion of column control circuitry  210 , a microcontroller, a microprocessor, and/or other similar functioned circuits. The control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit, or other type of circuit. 
     In some embodiments, there is more than one control die  211  and more than one memory die  201  in an integrated memory assembly  207 . In some embodiments, the integrated memory assembly  207  includes a stack of multiple control die  211  and multiple memory die  201 .  FIG.  3 A  depicts a side view of an embodiment of an integrated memory assembly  207  stacked on a substrate  271  (e.g., a stack comprising control dies  211  and memory dies  201 ). The integrated memory assembly  207  has three control dies  211  and three memory dies  201 . In some embodiments, there are more than three memory dies  201  and more than three control die  211 . 
     Each control die  211  is affixed (e.g., bonded) to at least one of the memory dies  201 . Some of the bond pads  282 / 284  are depicted. There may be many more bond pads. A space between two dies  201 ,  211  that are bonded together is filled with a solid layer  280 , which may be formed from epoxy or other resin or polymer. This solid layer  280  protects the electrical connections between the dies  201 ,  211 , and further secures the dies together. Various materials may be used as solid layer  280 , but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA. 
     The integrated memory assembly  207  may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds  270  connected to the bond pads connect the control die  211  to the substrate  271 . A number of such wire bonds may be formed across the width of each control die  211  (i.e., into the page of  FIG.  3 A ). 
     A memory die through silicon via (TSV)  276  may be used to route signals through a memory die  201 . A control die through silicon via (TSV)  278  may be used to route signals through a control die  211 . The TSVs  276 ,  278  may be formed before, during or after formation of the integrated circuits in the semiconductor dies  201 ,  211 . The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used. 
     Solder balls  272  may optionally be affixed to contact pads  274  on a lower surface of substrate  271 . The solder balls  272  may be used to couple the integrated memory assembly  207  electrically and mechanically to a host device such as a printed circuit board. Solder balls  272  may be omitted where the integrated memory assembly  207  is to be used as an LGA package. The solder balls  272  may form a part of the interface between integrated memory assembly  207  and memory controller  120 . 
       FIG.  3 B  depicts a side view of another embodiment of an integrated memory assembly  207  stacked on a substrate  271 . The integrated memory assembly  207  of  FIG.  3 B  has three control die  211  and three memory die  201 . In some embodiments, there are many more than three memory dies  201  and many more than three control dies  211 . In this example, each control die  211  is bonded to at least one memory die  201 . Optionally, a control die  211  may be bonded to two or more memory die  201 . 
     Some of the bond pads  282 ,  284  are depicted. There may be many more bond pads. A space between two dies  201 ,  211  that are bonded together is filled with a solid layer  280 , which may be formed from epoxy or other resin or polymer. In contrast to the example in  FIG.  3 A , the integrated memory assembly  207  in  FIG.  3 B  does not have a stepped offset. A memory die through silicon via (TSV)  276  may be used to route signals through a memory die  201 . A control die through silicon via (TSV)  278  may be used to route signals through a control die  211 . 
     Solder balls  272  may optionally be affixed to contact pads  274  on a lower surface of substrate  271 . The solder balls  272  may be used to couple the integrated memory assembly  207  electrically and mechanically to a host device such as a printed circuit board. Solder balls  272  may be omitted where the integrated memory assembly  207  is to be used as an LGA package. 
     As has been briefly discussed above, the control die  211  and the memory die  201  may be bonded together. Bond pads on each die  201 ,  211  may be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 5 μm to 5 μm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu. 
     When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor dies including the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond to each other, and the film layers on the respective dies may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 1 μm to 5 μm. Bonding techniques may be used providing bond pads with even smaller sizes and pitches. 
     Some embodiments may include a film on surface of the dies  201 ,  211 . Where no such film is initially provided, a space between the dies may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies  201 ,  211 , and further secures the dies together. Various materials may be used as under-fill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA. 
       FIG.  4    is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array/structure that can comprise memory structure  202 , which includes a plurality non-volatile memory cells arranged as vertical NAND strings. For example,  FIG.  4    shows a portion  400  of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack  401  of alternating dielectric layers and conductive layers. For example, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. As will be explained below, in one embodiment the alternating dielectric layers and conductive layers are divided into six (or a different number of) regions (e.g., sub-blocks) by isolation regions IR.  FIG.  4    shows one isolation region IR separating two sub-blocks. Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in  FIG.  4   , the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three dimensional monolithic memory array that comprises memory structure  202  is provided below. 
       FIG.  4 A  is a block diagram explaining one example organization of memory structure  202 , which is divided into two planes  402  and  404 . Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In on embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, blocks can be divided into sub-blocks and the sub-blocks can be the unit of erase. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells as the memory cells of a block share a common set of word lines. For example, the word lines for a block are all connected to all the vertical NAND strings for that block. Although  FIG.  4 A  shows two planes  402 / 404 , more or less than two planes can be implemented. In some embodiments, memory structure  202  includes eight planes. 
       FIGS.  4 B- 4 J  depict an example three dimensional (“3D”) NAND structure that corresponds to the structure of  FIG.  4    and can be used to implement memory structure  202  of  FIGS.  2 A and  2 B .  FIG.  4 B  is a block diagram depicting a top view of a portion  406  of Block  2  of plane  402 . As can be seen from  FIG.  4 B , the block depicted in  FIG.  4 B  extends in the direction of  432 . In one embodiment, the memory array has many layers; however,  FIG.  4 B  only shows the top layer. 
       FIG.  4 B  depicts a plurality of circles that represent the vertical columns, which correspond to the memory holes. Each of the vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example,  FIG.  4 B  labels a subset of the vertical columns/NAND strings  426 ,  432 ,  436 ,  446 .  456 ,  462 ,  466 ,  472 ,  474  and  476 . 
       FIG.  4 B  also depicts a set of bit lines  415 , including bit lines  411 ,  412 ,  413 ,  414 , . . .  419 .  FIG.  4 B  shows twenty four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty four bit lines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line. For example, bit line  411  is connected to vertical columns  426 ,  436 ,  446 ,  456 ,  466  and  476 . 
     The block depicted in  FIG.  4 B  includes a set of isolation regions  480 ,  482 ,  484 ,  486  and  488 , which are formed of SiO 2 ; however, other dielectric materials can also be used. Isolation regions  480 ,  482 ,  484 ,  486  and  488  serve to divide the top layers of the block into six regions; for example, the top layer depicted in  FIG.  4 B  is divided into regions  420 ,  430 ,  440 ,  450 ,  460  and  470  all of which are referred to as sub-blocks. In one embodiment, the isolation regions only divide the layers used to implement select gates so that NAND strings in different sub-blocks can be independently selected. In one example implementation, a bit line only connects to one vertical column/NAND string in each of regions (sub-blocks)  420 ,  430 ,  440 ,  450 ,  460  and  470 . In that implementation, each block has twenty four rows of active columns and each bit line connects to six rows in each block. In one embodiment, all of the six vertical columns/NAND strings connected to a common bit line are connected to the same word line (or set of word lines); therefore, the system uses the drain side selection lines to choose one (or another subset) of the six to be subjected to a memory operation (program, verify, read, and/or erase). 
     Although  FIG.  4 B  shows each region  420 ,  430 ,  440 ,  450 ,  460  and  470  having four rows of vertical columns, six regions and twenty four rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region and more or less rows of vertical columns per block.  FIG.  4 B  also shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered. 
       FIG.  4 C  depicts a portion of one embodiment of a three dimensional memory structure  202  showing a cross-sectional view along line AA of  FIG.  4 B . This cross sectional view cuts through vertical columns (NAND strings)  472  and  474  of region  470  (see  FIG.  4 B ). The structure of  FIG.  4 C  includes three drain side select layers SGD 0 , SGD 1  and SGD 2 ; three source side select layers SGS 0 , SGS 1 , and SGS 2 ; three dummy word line layers DD 0 , DD 1 , and DDS; two hundred and forty word line layers WL 0 -WL 239  for connecting to data memory cells, and two hundred and fifty dielectric layers DL 0 -DL 249 . Other embodiments can implement more or less than the numbers described above for  FIG.  4 C . In one embodiment, SGD 0 , SGD 1  and SGD 2  are connected together; and SGDS0, SGS 1  and SGS 2  are connected together. 
     Vertical columns  472  and  474  are depicted protruding through the drain side select layers, source side select layers, dummy word line layers and word line layers. In one embodiment, each vertical column comprises a vertical NAND string. Below the vertical columns and the layers listed below is substrate  453 , an insulating film  454  on the substrate, and source line SL. The NAND string of vertical column  442  has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement with  FIG.  4 B ,  FIG.  4 C  show vertical column  442  connected to bit line  414  via connector  417 . 
     For ease of reference, drain side select layers; source side select layers, dummy word line layers and data word line layers collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten or metal silicide. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL 0 -DL 249 . For example, dielectric layers DL 240  is above word line layer WL 235  and below word line layer WL 236 . In one embodiment, the dielectric layers are made from SiO 2 . In other embodiments, other dielectric materials can be used to form the dielectric layers. 
     The non-volatile memory cells are formed along vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WL 0 -W 239  connect to memory cells (also called data memory cells). Dummy word line layers DD 0 , DD 1  and DS connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host or entity outside of the storage system  100 ), such as data from a user of the host), while a data memory cell is eligible to store host data. Host data can be contrasted with system data that is generated by memory system  100  (e.g., L2P tables). In some embodiments, data memory cells and dummy memory cells may have a same structure. Drain side select layers SGD 0 , SGD 1 , and SGD 2  are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS 0 , SGS 1 , and SGS 2  are used to electrically connect and disconnect NAND strings from the source line SL. 
     Note that the stack of word lines WL 0 -WL 239  include two edge word lines at the edges of the stack, including top edge word line WL 239  and bottom edge word line WL 0 . Word lines WL 1 -WL 238  are non-edge word lines. 
       FIG.  4 D  depicts a portion of one embodiment of a three dimensional memory structure  202  showing a cross-sectional view along line BB of  FIG.  4 B . This cross sectional view cuts through vertical columns (NAND strings)  432  and  434  of region  430  (see  FIG.  4 B ).  FIG.  4 D  shows the same alternating conductive and dielectric layers as  FIG.  4 C .  FIG.  4 D  also shows isolation region  482 . Isolation regions  480 ,  482 ,  484 ,  486  and  488 ) occupy space that would have been used for a portion of the memory holes/vertical columns/NAND stings. For example, isolation region  482  occupies space that would have been used for a portion of vertical column  434 . More specifically, a portion (e.g., half the diameter) of vertical column  434  has been removed in layers SDG 0 , SGD 1 , SGD 2 , and DD 0  to accommodate isolation region  482 . Thus, while most of the vertical column  434  is cylindrical (with a circular cross section), the portion of vertical column  434  in layers SDG 0 , SGD 1 , SGD 2 , and DD 0  has a semi-circular cross section. In one embodiment, after the stack of alternating conductive and dielectric layers is formed, the stack is etched to create space for the isolation region and that space is then filled in with SiO 2 . 
       FIG.  4 E  depicts a portion of one embodiment of a three dimensional memory structure  202  showing a cross-sectional view along line CC of  FIG.  4 B . This cross sectional view cuts through vertical columns (NAND strings)  452  and  4624  (see  FIG.  4 B ).  FIG.  4 E  shows the same alternating conductive and dielectric layers as  FIG.  4 C .  FIG.  4 E  also shows isolation region  486  cutting into vertical columns (NAND string)  452 . 
       FIG.  4 F  depicts a cross sectional view of region  429  of  FIG.  4 C  that includes a portion of vertical column  472 . In one embodiment, the vertical columns are round; however, in other embodiments other shapes can be used. In one embodiment, vertical column  472  includes an inner core layer  490  that is made of a dielectric, such as SiO 2 . Other materials can also be used. Surrounding inner core  490  is polysilicon channel  491 . Materials other than polysilicon can also be used. Note that it is the channel  491  that connects to the bit line and the source line. Surrounding channel  491  is a tunneling dielectric  492 . In one embodiment, tunneling dielectric  492  has an ONO structure. Surrounding tunneling dielectric  492  is charge trapping layer  493 , such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure. 
       FIG.  4 D  depicts dielectric layers DLL 239 , DLL 240 , DLL 241 , DLL 242  and DLL 243 , as well as word line layers WLL 234 , WLL 235 , WLL 236 , WLL 237 , and WLL 238 . Each of the word line layers includes a word line region  496  surrounded by an aluminum oxide layer  497 , which is surrounded by a blocking oxide layer  498 . In other embodiments, the blocking oxide layer can be a vertical layer parallel and adjacent to charge trapping layer  493 . The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel  491 , tunneling dielectric  492 , charge trapping layer  493 , blocking oxide layer  498 , aluminum oxide layer  497  and word line region  496 . For example, word line layer WLL 238  and a portion of vertical column  472  comprise a memory cell MC 1 . Word line layer WL 237  and a portion of vertical column  472  comprise a memory cell MC 2 . Word line layer WLL 236  and a portion of vertical column  472  comprise a memory cell MC 3 . Word line layer WLL 235  and a portion of vertical column  472  comprise a memory cell MC 4 . Word line layer WLL 234  and a portion of vertical column  472  comprise a memory cell MC 5 . In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit. 
     When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer  493  which is associated with (e.g. in) the memory cell. These electrons are drawn into the charge trapping layer  493  from the channel  491 , through the tunneling dielectric  492 , in response to an appropriate voltage on word line region  496 . The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL. 
       FIG.  4 G  shows a cross section of vertical column  472  of  FIG.  4 F , cut through MC 5 . Thus,  FIG.  4 G  depicts word line layer WL 234 , inner core  490 , channel  491 , tunneling dielectric  492 , charge trapping layer  493 , aluminum oxide layer  497 , and blocking oxide layer  498 . 
       FIG.  4 H  shows a cross section of vertical column  472  of  FIG.  4 F , cut through SGD 1  (a select gate layer implementing a select gate). Thus,  FIG.  4 H  depicts drain side select line layer SGD 1 , inner core  490 , channel  491 , tunneling dielectric  492 , charge trapping layer  493 , aluminum oxide layer  497 , and blocking oxide layer  498 . 
       FIG.  4 I  shows a cross section of vertical column  434  of  FIG.  4 D , cut through SGD 1 . Thus,  FIG.  4 I  depicts drain side select line layer SGD 1 , inner core  490 , channel  491 , tunneling dielectric  492 , charge trapping layer  493 , aluminum oxide layer  497 , and blocking oxide layer  498 .  FIG.  4 I  also shows a portion of isolation region  482 . As can be seen in  FIG.  4 I , the select gate (select gate layer and select line layer) of vertical column  434  is semicircular in shape (or partially circular in shape) due to vertical column (NAND string)  434  intersecting isolation region  482 . 
       FIG.  4 J  is a schematic diagram of a portion of the memory array  202  depicted in in  FIGS.  4 - 4 I .  FIG.  4 J  shows physical data word lines WL 0 -WL 239  running across the entire block. The structure of  FIG.  4 J  corresponds to a portion  306  in Block  2  of Figure A, including bit line  411 . Within the block, in one embodiment, each bit line is connected to six NAND strings. Thus,  FIG.  4 J  shows bit line connected to NAND string NS 0  (which corresponds to vertical column  426 ), NAND string NS 1  (which corresponds to vertical column  436 ), NAND string NS 2  (which corresponds to vertical column  446 ), NAND string NS 3  (which corresponds to vertical column  456 ), NAND string NS 4  (which corresponds to vertical column  466 ), and NAND string NS 5  (which corresponds to vertical column  476 ). As mentioned above, in one embodiment, SGD 0 , SGD 1  and SGD 2  are connected together to operate as a single logical select gate for each sub-block separated by isolation regions ( 480 ,  482 ,  484 ,  486  and  486 ) to form SGD-s 0 , SGD-s 1 , SGD-s 2 , SGD-s 3 , SGD-s 4 , and SGD-s 5 . SGS 0 , SG 1  and SGS 2  are also connected together to operate as a single logical select gate that is represented in  FIG.  4 E  as SGS. Although the select gates SGD-s 0 , SGD-s 1 , SGD-s 2 , SGD-s 3 , SGD-s 4 , and SGD-s 5  are isolated from each other due to the isolation regions, the data word lines WL 0 -WL 239  of each sub-block are connected together. 
     The isolation regions ( 480 ,  482 ,  484 ,  486  and  486 ) are used to allow for separate control of sub-blocks. A first sub-block corresponds to those vertical NAND strings controlled by SGD-s 0 . A second sub-block corresponds to those vertical NAND strings controlled by SGD-s 1 . A third sub-block corresponds to those vertical NAND strings controlled by SGD-s 2 . A fourth sub-block corresponds to those vertical NAND strings controlled by SGD-s 3 . A fifth sub-block corresponds to those vertical NAND strings controlled by SGD-s 4 . A sixth sub-block corresponds to those vertical NAND strings controlled by SGD-s 5 . 
       FIG.  4 J  only shows the NAND strings connected to bit line  411 . However, a full schematic of the block would show every bit line and six vertical NAND strings connected to each bit line. 
     Although the example memories of  FIGS.  4 - 4 J  are three dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein. 
     The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.  FIG.  5 A  is a graph of threshold voltage versus number of memory cells, and illustrates example threshold voltage distributions for the memory array when each memory cell stores one bit of data per memory cell. Memory cells that store one bit of data per memory cell data are referred to as single level cells (“SLC”). The data stored in SLC memory cells is referred to as SLC data; therefore, SLC data comprises one bit per memory cell. Data stored as one bit per memory cell is SLC data.  FIG.  5 A  shows two threshold voltage distributions: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Memory cells that have threshold voltages in threshold voltage distribution E are, therefore, in the erased data state (e.g., they are erased). Memory cells that have threshold voltages in threshold voltage distribution P are, therefore, in the programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data “1” and programmed memory cells store data “0.”  FIG.  5 A  depicts read reference voltage Vr. By testing (e.g., performing one or more sense operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine a memory cells is erased (state E) or programmed (state P).  FIG.  5 A  also depicts verify reference voltage Vv. In some embodiments, when programming memory cells to data state P, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv. 
       FIGS.  5 B-F  illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”). The data stored in MLC memory cells is referred to as MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. In the example embodiment of  FIG.  5 B , each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three, four, five or six bits of data per memory cell). 
       FIG.  5 B  shows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B and C for programmed memory cells are also depicted. In one embodiment, the threshold voltages in the distribution E are negative and the threshold voltages in distributions A, B and C are positive. Each distinct threshold voltage distribution of  FIG.  5 B  corresponds to predetermined values for the set of data bits. In one embodiment, each bit of data of the two bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all bits of data stored in a memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 1 provides an example encoding scheme. 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 E 
                 A 
                 B 
                 C 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
            
               
                   
                 LP 
                 1 
                 0 
                 0 
                 1 
               
               
                   
                 UP 
                 1 
                 1 
                 0 
                 0 
               
               
                   
                   
               
            
           
         
       
     
     In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state E directly to any of the programmed data states A, B or C using the process of  FIG.  6    (discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state E. Then, a programming process is used to program memory cells directly into data states A, B, and/or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and/or from data state E to data state C. The arrows of  FIG.  5 B  represent the full sequence programming. In some embodiments, data states A-C can overlap, with memory controller  120  (or control die  211 ) relying on error correction to identify the correct data being stored. 
       FIG.  5 C  depicts example threshold voltage distributions for memory cells where each memory cell stores three bits of data per memory cells (which is another example of MLC data).  FIG.  5 C  shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents memory cells that are erased. The other seven threshold voltage distributions (data states) A-G represent memory cells that are programmed and, therefore, are also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected. Table 2 provides an example of an encoding scheme for embodiments in which each bit of data of the three bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP) and an upper page (UP). 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Er 
                 A 
                 B 
                 C 
                 D 
                 E 
                 F 
                 G 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
               
            
               
                   
                 UP 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                   
                 MP 
                 1 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
               
               
                   
                 LP 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
               
               
                   
                   
               
            
           
         
       
     
       FIG.  5 C  shows seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., A, B, C, D, . . . ) a memory cell is in. 
       FIG.  5 C  also shows seven verify reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system will test whether those memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test whether the memory cells have threshold voltages greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether memory cells have their threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system will test whether those memory cells have a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system will test whether those memory cells have a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system will test whether those memory cells have a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system will test whether those memory cells have a threshold voltage greater than or equal to VvG.  FIG.  5 C  also shows Vev, which is a voltage level to test whether a memory cell has been properly erased. 
     In an embodiment that utilizes full sequence programming, memory cells can be programmed from the erased data state Er directly to any of the programmed data states A-G using the process of  FIG.  6    (discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state Er. Then, a programming process is used to program memory cells directly into data states A, B, C, D, E, F, and/or G. For example, while some memory cells are being programmed from data state ER to data state A, other memory cells are being programmed from data state ER to data state B and/or from data state ER to data state C, and so on. The arrows of  FIG.  5 C  represent the full sequence programming. In some embodiments, data states A-G can overlap, with control die  211  and/or memory controller  120  relying on error correction to identify the correct data being stored. Note that in some embodiments, rather than using full sequence programming, the system can use multi-pass programming processes known in the art. 
     In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read compare levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG, of  FIG.  5 C ) or verify operation (e.g. see verify target levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG of  FIG.  5 C ) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased). 
     There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used. 
       FIG.  5 D  depicts threshold voltage distributions when each memory cell stores four bits of data, which is another example of MLC data.  FIG.  5 D  depicts that there may be some overlap between the threshold voltage distributions (data states) S 0 -S 15 . The overlap may occur due to factors such as memory cells losing charge (and hence dropping in threshold voltage). Program disturb can unintentionally increase the threshold voltage of a memory cell. Likewise, read disturb can unintentionally increase the threshold voltage of a memory cell. Over time, the locations of the threshold voltage distributions may change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read reference voltages can help to mitigate such effects. Using ECC during the read process can fix errors and ambiguities. Note that in some embodiments, the threshold voltage distributions for a population of memory cells storing four bits of data per memory cell do not overlap and are separated from each other; for example, as depicted in  FIG.  5 E . The threshold voltage distributions of  FIG.  5 D  will include read reference voltages and verify reference voltages, as discussed above. 
     When using four bits per memory cell, the memory can be programmed using the full sequence programming discussed above, or multi-pass programming processes known in the art. Each threshold voltage distribution (data state) of  FIG.  5 D  corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 3 provides an example of an encoding scheme for embodiments in which each bit of data of the four bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP), an upper page (UP) and top page (TP). 
     
       
         
           
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                 S0 
                 S1 
                 S2 
                 S3 
                 S4 
                 S5 
                 S6 
                 S7 
                 S8 
                 S9 
                 S10 
                 S11 
                 S12 
                 S13 
                 S14 
                 S15 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
            
               
                 TP 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
                 0 
                 1 
               
               
                 UP 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 0 
               
               
                 MP 
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
               
               
                 LP 
                 1 
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                   
               
            
           
         
       
     
       FIG.  5 F  depicts threshold voltage distributions when each memory cell stores five bits of data, which is another example of MLC data. In one example implementation, when memory cells store five bits of data, the data is stored in any of thirty two data state (e.g., S 0 -S 31 ). 
       FIG.  6    is a flowchart describing one embodiment of a process for programming memory cells. For purposes of this document, the term program and programming are synonymous with write and writing. In one example embodiment, the process of  FIG.  6    is performed for memory array  202  using the one or more control circuits (e.g., system control logic  260 , column control circuitry  210 , row control circuitry  220 ) discussed above. In one example embodiment, the process of  FIG.  6    is performed by integrated memory assembly  207  using the one or more control circuits (e.g., system control logic  260 , column control circuitry  210 , row control circuitry  220 ) of control die  211  to program memory cells on memory die  201 . The process includes multiple loops, each of which includes a program phase and a verify phase. The process of  FIG.  6    is performed to implement the full sequence programming, as well as other programming schemes including multi-pass programming. When implementing multi-pass programming, the process of  FIG.  6    is used to implement any/each pass of the multi-pass programming process. 
     Typically, the program voltage applied to the control gates (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step  602  of  FIG.  6   , the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level) and a program counter PC maintained by state machine  262  is initialized at  1 . In one embodiment, the group of memory cells selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same word line (the selected word line). There will likely be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are supposed to be inhibited from programming. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming. Those NAND strings (e.g., unselected NAND strings) that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When a channel has a boosted voltage, the voltage differential between the channel and the word line is not large enough to cause programming. To assist in the boosting, in step  604  the control die will pre-charge channels of NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. In step  606 , NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as “unselected NAND strings.” In one embodiment, the unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts), also referred to as pass voltages, to perform boosting schemes. A program inhibit voltage is applied to the bit lines coupled the unselected NAND string. In one embodiment, for example, the channel is pre-charged to ˜2 volts in step  604  and then floated. In step  606 , the channel is boosted up from the 2 volts to a boosting voltage of approximately 8-10 volts. 
     In step  608 , a program voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage. In step  608 , the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they are inhibited from programming. 
     In step  610 , program verify is performed and memory cells that have reached their target states are locked out from further programming by the control die. Step  610  includes performing verification of programming by sensing at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. In step  610 , a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state. 
     If, in step  612 , it is determined that all of the memory cells have reached their target threshold voltages (pass), the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step  614 . Otherwise, if in step  612 , it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step  616 . 
     In step  616 , the number of memory cells that have not yet reached their respective target threshold voltage distribution are counted. That is, the number of memory cells that have, so far, failed to reach their target state are counted. This counting can be done by state machine  262 , memory controller  120 , or another circuit. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state. 
     In step  618 , it is determined whether the count from step  616  is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step  614 . In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step  618  is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allow for future/additional errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria. 
     If the number of failed memory cells is not less than the predetermined limit, than the programming process continues at step  620  and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 12, 16, 19, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step  624 . If the program counter PC is less than the program limit value PL, then the process continues at step  626  during which time the Program Counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1-1.0 volts). After step  626 , the process loops back to step  604  and another program pulse is applied to the selected word line (by the control die) so that another iteration (steps  604 - 626 ) of the programming process of  FIG.  6    is performed. 
     In some embodiments, memory cells are programmed in an order from the source side to the drain side. For example, first the process of  FIG.  6    is performed to program memory cells connected to WL 0 , followed by using the process of  FIG.  6    to program memory cells connected to WL 1 , followed by using the process of  FIG.  6    to program memory cells connected to WL 2 , followed by using the process of  FIG.  6    to program memory cells connected to WL 3 , . . . followed by using the process of  FIG.  6    to program memory cells connected to WL 239 . 
     In another embodiment, memory cells are programmed in an order from the drain side to the source side. For example, first the process of  FIG.  6    is performed to program memory cells connected to WL 239 , followed by using the process of  FIG.  6    to program memory cells connected to WL 238 , followed by using the process of  FIG.  6    to program memory cells connected to WL 237 , followed by using the process of  FIG.  6    to program memory cells connected to WL 236 , . . . followed by using the process of  FIG.  6    to program memory cells connected to WL 1 , followed by using the process of  FIG.  6    to program memory cells connected to WL 0 . 
     In one embodiment memory cells are erased prior to programming, and erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from state P to state E of  FIG.  5 A , from states A/B/C to state E of  FIG.  5 B , from states A-G to state Er of  FIG.  5 C  or from states S 1 -S 15  to state S 0  of  FIG.  5 D . 
     One technique to erase memory cells in some memory devices is to bias a p-well (or other types of) substrate to a high voltage to charge up a NAND channel. An erase enable voltage (e.g., a low voltage) is applied to control gates of memory cells while the NAND channel is at a high voltage to erase the non-volatile storage elements (memory cells). Herein, this is referred to as p-well erase. 
     Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the NAND string channel potential to erase the memory cells. Herein, this is referred to as GIDL erase. Both p-well erase and GIDL erase may be used to lower the threshold voltage (Vt) of memory cells. 
     In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a select transistor (e.g., SGD and/or SGS). A transistor drain-to-gate voltage that generates a GIDL current is referred to herein as a GIDL voltage. The GIDL current may result when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and/or trap-assisted generation. In one embodiment, GIDL current may result in one type of carriers, e.g., holes, predominantly moving into NAND channel, thereby raising potential of the channel. The other type of carriers, e.g., electrons, are extracted from the channel, in the direction of a bit line or in the direction of a source line, by an electric field. During erase, the holes may tunnel from the channel to a charge storage region of memory cells and recombine with electrons there, to lower the threshold voltage of the memory cells. 
     The GIDL current may be generated at either end of the NAND string. A first GIDL voltage may be created between two terminals of a select transistor (e.g., drain side select transistor) that is connected to or near a bit line to generate a first GIDL current. A second GIDL voltage may be created between two terminals of a select transistor (e.g., source side select transistor) that is connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of the NAND string is referred to as a one-sided GIDL erase. Erasing based on GIDL current at both ends of the NAND string is referred to as a two-sided GIDL erase. 
       FIGS.  7 A and  7 B  describe one example of a multi-pass programming process, referred to as Foggy-Fine Programming.  FIG.  7 A  depicts the first pass of the multi-pass programming process, which includes programming the memory cells from the erased state (Er) to any of the programmed data states A-G (e.g., for memory cells storing 3 bits of data per memory cell), similar to full sequence programming. However, rather than using the standard verify reference voltages (e.g., VvA, VvB, VvC, VvD, VvE, VvF, and VvG), the process of  FIG.  7 A  uses an alternate set of verify reference voltages (e.g., VvA′, VvB′, VvC′, VvD,′ VvE′, VvF′, and VvG′) that are each slightly lower than the corresponding standard verify reference voltage. Thus, the threshold voltage distributions of  FIG.  7 A  can be thought of as intermediate threshold voltage distributions (or intermediate data states) that are at lower voltages than the threshold voltages of  FIG.  5 C . 
       FIG.  7 B  depicts the second (and last) pass of the multi-pass programming process, which includes programming the memory cells to tighten the threshold distributions. Thus, the memory cells are programmed from the intermediate threshold voltage distributions (or intermediate data states) of  FIG.  7 A  to the final or target threshold voltage distributions (or data states) of  FIG.  7 B  using the standard verify reference voltages (e.g., VvA, VvB, VvC, VvD, VvE, VvF, and VvD).  FIG.  7 A  is referred to as the Foggy pass (or foggy programming) and  FIG.  7 B  as the Fine Pass (or fine programming). In one embodiment, the Foggy pass of  FIG.  7 A  is performed for a given word line, followed by the Foggy pass for the next word line. The Foggy pass for the next word line could give rise to interference for the given word line, thereby widening the intermediate threshold voltage distributions, which could lead to errors when reading the data. However, the Fine pass of  FIG.  7 B  is subsequently performed after Foggy pass for the next word line, removing or reducing the effects of interference from the next word line. Both passes of the multi-pass programming process of  FIGS.  7 A and  7 B  can be implemented using the process of  FIG.  6   . Although  FIGS.  7 A and  7 B  provide an example of Foggy-Fine Programming for three nits per memory cell, Foggy-Fine Programming can also be used for systems that store more or less than three bits per memory cell such that the programming is divided into a Foggy pass and a Fine pass, as illustrated in  FIGS.  7 A and  7 B . 
     To increase capacity while keeping costs low, manufacturers of non-volatile memory have been trying to increase the number of bits stored in each memory cell. For example,  FIGS.  5 B-F  illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. However, as the number of bits per memory cell increases, the number of threshold voltage distributions that need to be squeezed into the window of operation increases. The greater the number of threshold voltage distributions, the smaller the distance between threshold voltage distributions (or between peaks of threshold voltage distributions). With less distance between threshold voltage distributions, data retention issues that cause threshold voltage distributions to widen can lead to errors when reading data. Therefore, to maintain narrow threshold voltage distributions and reduce errors when reading data due to data retention issues, it is proposed to perform a soft erase process during the programming of data. 
     The use of the soft erase process improves data retention properties of the memory, which maintains the narrow widths of the programmed threshold voltage distributions, thereby reducing errors when reading data. As mentioned above, when programming memory cells, electrons are stored in a portion of the charge trapping layer  493 , These electrons are drawn into the charge trapping layer  493  from the channel  491 , through the tunneling dielectric  492 , in response to an appropriate voltage on a word line. The threshold voltage of a memory cell is increased in proportion to the amount of charge stored in charge trapping layer  493 . In many cases, electrons drawn into the charge trapping layer  493  become resident in deep traps and will stay in those deep traps over time. In some cases, however, some electrons drawn into the charge trapping layer  493  become resident in shallow traps and can leave those shallow traps after a short period of time, causing a change in the charge level of the respective portion of charge trapping layer  493 , which results in a change in threshold voltage of the associated memory cell. An unwanted change in threshold voltages of memory cells can lead to data retention errors. Performing a soft erase process during programming may cause some of the electrons in shallow traps to migrate back to the channel where they can be programmed again (in subsequent programming after the soft erase) into deeper traps. 
     For purposes of this document, a “soft erase process” is a process that performs some amount of erasing but not enough erasing to move the memory cells to an erased conditions. For example, a memory cell being programmed to data state B (see  FIG.  5 C ) receiving a soft erase process may have its threshold voltage reduces by a small amount but that memory cell will not revert back to the erased state Er. In one embodiment, a soft erase will include pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging. In one embodiment, the channels that are pre-charged are the channels of the NAND strings that include the memory cells being programmed. In some embodiments, the entire NAND string channel is pre-charged, while in other embodiments only a portion of the channel of the NAND string is pre-charged (e.g., the portion underneath the memory cell selected for programming). 
       FIG.  8    is a flow chart describing one embodiment of a process for programming that includes a soft erase process. In one example embodiment, the process of  FIG.  8    is performed by any of the embodiments of a control circuit discussed above. In one example embodiment, the process of  FIG.  8    is performed by integrated memory assembly  207  using any of the embodiments of a control circuits discussed above of control die  211  to program memory cells (e.g., NAND strings of memory structure  202 ) on memory die  201 . In one embodiment, the process of  FIG.  8    is performed at the direction of state machine  262  (or another processor). The control circuit is connected to the memory cells (e.g., via control lines such as word lines, bit lines, source line and select lines), as described above with respect to  FIGS.  1 - 4 J . 
     In step  802  of  FIG.  8   , the control circuit programs the memory cells. For example, the process of  FIG.  6    is performed to apply one or multiple voltage pulses to a selected word line to perform programming for the selected memory cells of the NAND strings that are connected to the selected word line. In step  804 , the control circuit performs a soft erase process on the memory cells during the programming of the memory cells. The soft erase process is performed during the programming because some programming is performed before the soft erase process and some programming is performed after the soft erase process. That is, the process of  FIG.  8    can include performing step  804  as part of step  802  or concurrently with step  802 . Parts of step  802  can be performed before and after performing step  804 . In one embodiment, the soft erase process includes pre-charging channels of the memory cells (step  812 ) and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging (step  814 ). In one example implementation, the plurality of non-volatile memory cells being programmed are part of NAND strings and the control circuit is configured to perform the pre-charging by pre-charging channels of the NAND strings from a source side of the NAND strings and from a drain side of the NAND strings. More details are explained below. 
       FIG.  9    is a flow chart describing another embodiment of a process for programming that includes a soft erase process. In one example embodiment, the process of  FIG.  9    is performed by any of the embodiments of a control circuit discussed above. In one example embodiment, the process of  FIG.  9    is performed by integrated memory assembly  207  using any of the embodiments of a control circuits discussed above of control die  211  to program memory cells (e.g., NAND strings of memory structure  202 ) on memory die  201 . In one embodiment, the process of  FIG.  9    is performed at the direction of state machine  262  (or another processor). The control circuit is connected to the memory cells (e.g., via control lines such as word lines, bit lines, source line and select lines), as described above with respect to  FIGS.  1 - 4 J . The process of  FIG.  9    is an example implementation of the process of  FIG.  8   . 
     In step  902  of  FIG.  9   , the control circuit performs a first amount of programming for a first set of data being programmed into a first set of memory cells. For example, the process of  FIG.  6    is performed to apply one or multiple voltage pulses to a selected word line to perform programming for the selected memory cells of the NAND strings that are connected to the selected word line. In step  904 , the control circuit performs a soft erase process for the first set of memory cells during the programming of the first set of memory cells, after the first amount of programming of step  902 . In one embodiment, the soft erase process includes pre-charging channels of the memory cells (step  912 ) and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging (step  914 ). In step  906 , the control circuit performs a second amount of programming for the first set of data being programmed into the first set of memory cells, after the soft erase process of step  904 . In some embodiments, the memory structure includes a plurality of word lines connected to the control circuit, the plurality of non-volatile memory cells are part of NAND strings connected to the word lines, the memory cells being programmed are connected to a selected word line of the plurality of word lines, the control circuit is configured to program the memory cells by performing initial programming on the plurality of non-volatile memory cells for the first set of data including applying one or more voltage pulses to the selected word line prior to the pre-charging and performing the second amount of programming for the first set of data including applying one or more voltage pulses to the selected word line subsequent to the pre-charging 
       FIG.  10    is a flow chart describing another embodiment of a process for programming that includes a soft erase process. In one example embodiment, the process of  FIG.  10    is performed by any of the embodiments of a control circuit discussed above. In one example embodiment, the process of  FIG.  10    is performed by integrated memory assembly  207  using any of the embodiments of a control circuits discussed above of control die  211  to program memory cells (e.g., NAND strings of memory structure  202 ) on memory die  201 . In one embodiment, the process of  FIG.  10    is performed at the direction of state machine  262  (or another processor). The control circuit is connected to the memory cells (e.g., via control lines such as word lines, bit lines, source line and select lines), as described above with respect to  FIGS.  1 - 4 J . The process of  FIG.  10    is an example implementation of the process of  FIG.  8    and/or the process of  FIG.  9   . 
     In step  1002 , the control circuit starts a programming process that includes performing initial programming on a plurality of non-volatile memory cells (e.g., one or more iterations of steps  604 - 626  are performed). In step  1004 , after performing the initial programming and prior to completing the programming process, the control circuit pre-charges channels associated with the non-volatile memory cells to one or more pre-charge voltages. In step  1006 , the control circuit boosts the pre-charged channels to a positive voltage above the one or more pre-charge voltages. Thus, the voltage in the channel after step  1006  is at a boosting voltage that was attained from the combination of pre-charging and boosting. In step  1008 , while the channels are boosted, the control circuit applies a negative erase voltage (e.g., negative voltage pulse) to the non-volatile memory cells to cause a partial erasing of the memory cells being programmed. For example, a negative voltage is applied to the word line selected for programming. Steps  1004 - 1008  of  FIG.  10    are example implementations of step  804  of  FIG.  8    and step  904  of  FIG.  9   . In step  1010 , the control circuit performs additional programming of the non-volatile memory after the applying of the negative erase voltage (e.g., one or more iterations of steps  604 - 626  are performed). In one example implementation, the plurality of non-volatile memory cells are part of NAND strings; the performing initial programming on the plurality of non-volatile memory cells includes applying multiple voltage pulses (e.g., step  608 ) to gate terminals of the plurality of non-volatile memory cells (e.g., via the selected word line); and the performing additional programming includes applying one or more voltage pulses (e.g., step  608 ) to gate terminals of the plurality of non-volatile memory cells (e.g., via the selected word line). 
       FIG.  11    is a timing diagram that depicts one embodiment of the soft erase process. Thus, the process depicted in  FIG.  11    is an example implementation of step  804  of  FIG.  8   , step  904  of  FIG.  9    and steps  1004 - 1008  of  FIG.  10   . In one embodiment, the signals depicted in  FIG.  11    are controlled by any of the embodiments of a control circuit discussed above.  FIG.  11    shows the behavior of seven signals: BL, SGD, Unselected WLs, Selected WLn, WL(n+1)/(n−1), SGS and SL. The signal BL is the voltage applied to the bit lines for the block (or sub-block). The signal SGD is the voltage applied to the drain side select lines (e.g., SGD 0 , SGD 1  and SGD 2 ). The signal Unselected WLs represents the voltage applied to the unselected word lines, other than WLn+1 and WLn−1. The signal Selected WLn is the voltage applied to the selected word line. The signal WL(n+1)/(n−1) represents the voltage applied to the unselected word lines WLn+1 and WLn−1. The unselected word lines WLn+1 and WLn−1 are the word lines adjacent to the selected word line WLn. For example, if WL 100  is selected for programming, then (in one embodiment that programs from source side to drain side) WLn=WL 100 , WLn-1=WL 99  and WLn+1=WL 101 . The signal SGS is the voltage applied to the source side select lines (e.g., SGS 0 , SGS 1  and SGS 2 ). The signal SL is the voltage applied to the source line. 
     Prior to time t 0 , all of the signals depicted in  FIG.  11    are at 0 volts. At time t 0 , the bit lines BL and the source line SL are raised to a voltage that enables pre-charging and boosting (e.g., 2-3 volts) and remain at that voltage until time t 3  when BL and SL are lowered back to 0 volts. Also at time t 0 , SGD and SGS are raised to a voltage that enables pre-charging (e.g., 2-3 volts), the Unselected WLs are raised to a low voltage (e.g., 1 volt or a positive voltage less than 1 volt), WLn is raised to a voltage that enables pre-charging (e.g., 1-3 volts) and WL(n+1)/(n−1) is raised to a voltage that enables pre-charging (e.g., 1-3 volts). The signals SGD, Selected WLn, and SGS are lowered to 0 volts at time t 1 . Also at t 1 , WL(n+1)/(n−1) is raised to a partial boosting voltage (e.g., 5-6 volts) that is designed to avoid hot carrier injection at t 1 . The Unselected WLs are raised to a boosting voltage (e.g., 8-10 volts) at t 1 . SGD and SGS are lowered to 0 volts at t 1 . The Selected WLn is lowered to a negative voltage (e.g., −2 to −4 volts) at time t 2 . BL, Unselected WLs, Selected WLn, WL(n+1)/(n−1), and SL are brought to 0 volts at t 3 . Thus, word lines that are not adjacent the selected word line receive a higher voltage than word lines that are adjacent the selected word line while applying the negative erase voltage to the selected word line. 
     During the period between t 0  and t 1 , the channel of the NAND strings are pre-charged to a pre-charge voltage, corresponding to steps  812 ,  912  and  1004 . In one embodiment, the channel of the NAND strings are pre-charged to the voltage applied to the bit lines and source line (e.g., 2-3 volts) as the pre-charging is from both the source side and drain side (e.g., bit lines). Thus, at time t 1 , the channel of all NAND strings of the block (or sub-block) have their channels boosted to the pre-charge voltage (e.g., 2-3 volts). The pre-charging serves to purge the channels of electrons and increase the channel voltage to enable the subsequent boosting to raise the channel voltage high enough as necessary for the erase operation. In some embodiments, as depicted in  FIG.  11   , the control circuit is configured to apply a positive voltage less than two volts to unselected word lines of the plurality of word lines while pre-charging the channels. Because the voltages on the unselected word lines are so low, the pre-charging can take longer (e.g., 50 us to 100 us). 
     At time t 2 , the channel gets cutoff from the bit lines and source line and the channels of the NAND strings will get boosted (e.g., step  1006 ) from the pre-charge voltage (e.g., 2-3 volts) to a boosted voltage (e.g., ˜10 volts). As depicted, the control circuit is configured to boost the pre-charged channels by turning off source side select gates and drain side select gates for the NAND strings. Since the Selected Word Line WLn is at a negative voltage (e.g., −2 to −4 volts) the voltage differential between the channel and the word line at the selected word line WLn is approximately 12-14 volts, which is enough to cause some erasing to occur for the memory cells connected to WLn. The erasing causes some electrons to move from the charge trapping layer back to the channel, thereby lowering the threshold voltage of the memory cells connected to WLn. The erasing performed between t 2  and t 3  is the erase operation of steps  814 ,  914  and  1008 . In some embodiments, as depicted in  FIG.  11   , the control circuit is configured to apply a source line voltage to the source line that is less than ten volts and one or more bit line voltages to the bit lines that are less than ten volts while performing the erase operation. Also note that in the embodiment depicted in  FIG.  11   , the boosting includes turning off source side select gates and drain side select gates for the NAND strings. 
       FIG.  12    is a flow chart describing another embodiment of a process for programming that includes a soft erase process. In one example embodiment, the process of  FIG.  12    is performed by any of the embodiments of a control circuit discussed above. In one example embodiment, the process of  FIG.  12    is performed by integrated memory assembly  207  using any of the embodiments of a control circuits discussed above of control die  211  to program memory cells (e.g., NAND strings of memory structure  202 ) on memory die  201 . In one embodiment, the process of  FIG.  12    is performed at the direction of state machine  262  (or another processor). The control circuit is connected to the memory cells (e.g., via control lines such as word lines, bit lines, source line and select lines), as described above with respect to  FIGS.  1 - 4 J . The process of  FIG.  12    is an example implementation of the processes of  FIG.  8   ,  FIG.  9    and/or  FIG.  10   . 
     In the embodiment of  FIG.  12   , Foggy-Fine Programming is used (see  FIGS.  7 A and  7 B ). In step  1202  of  FIG.  12   , the control circuit performs foggy programming (e.g., the Foggy pass of  FIG.  7 A ) for a first set of data being programmed into a first set of memory cells connected to the selected word line WLn. Step  1202  can be performed using the processes of  FIG.  6    and  FIG.  7 A . In some embodiments, step  1202  corresponds to and provides an example of steps  802 ,  902  and  1002 . In step  1204  of  FIG.  12   , the control circuit performs a soft erase process, such as the process depicted in  FIG.  11   . In some embodiments, step  1204  corresponds to and provides an example of steps  804 ,  904  and  1004 - 1008 . In step  1206  of  FIG.  12   , the control circuit perform fine programming (e.g., the Fine pass of  FIG.  7 B ) for the first set of data being programmed into the first set of memory cells connected to the selected word line WLn. Step  1206  is performed after the soft erase process of step  1204 . In some embodiments, step  1206  corresponds to and provides an example of steps  802 ,  906  and  1010 . Step  1206  can be performed using the processes of  FIG.  6    and  FIG.  7 B . In one embodiment, memory controller  120  instructs the memory  130  to perform the full sequence programming that includes the software erase process. In another embodiment, memory controller  120  sends separate instructions to memory  130  to perform the full sequence programming and to perform the software erase process. 
       FIG.  13    is a flow chart describing another embodiment of a process for programming that includes a soft erase process. In one example embodiment, the process of  FIG.  13    is performed by any of the embodiments of a control circuit discussed above. In one example embodiment, the process of  FIG.  13    is performed by integrated memory assembly  207  using any of the embodiments of a control circuits discussed above of control die  211  to program memory cells (e.g., NAND strings of memory structure  202 ) on memory die  201 . In one embodiment, the process of  FIG.  13    is performed at the direction of state machine  262  (or another processor). The control circuit is connected to the memory cells (e.g., via control lines such as word lines, bit lines, source line and select lines), as described above with respect to  FIGS.  1 - 4 J . The process of  FIG.  13    is an example implementation of the processes of  FIG.  8   ,  FIG.  9    and/or  FIG.  10   . 
     In step  1302  of  FIG.  13   , the control circuit performs full sequence programming (see e.g.,  FIG.  5 C ) to a set of target data states for a first set of data. Step  1302  can be performed using the process of  FIG.  6   . In some embodiments, step  1302  corresponds to and provides an example of steps  802 ,  902  and  1002 . In step  1304  of  FIG.  13   , the control circuit performs a soft erase process (e.g., the process of  FIG.  11   ) after the full sequence programming of step  1302 . In some embodiments, step  1304  corresponds to and provides an example of steps  804 ,  904  and  1004 - 1008 . In step  1306 , the control circuit performs additional programming for the first set of data and set of target data states after the soft erase process. For example, step  1306  can include performing one or more iterations of steps  604 - 626  of  FIG.  6   . In some embodiments, step  1306  corresponds to and provides an example of steps  802 ,  906  and  1010 . 
       FIG.  14    is a flow chart describing another embodiment of a process for programming that includes a soft erase process. In one example embodiment, the process of  FIG.  14    is performed by any of the embodiments of a control circuit discussed above. In one example embodiment, the process of  FIG.  14    is performed by integrated memory assembly  207  using any of the embodiments of a control circuits discussed above of control die  211  to program memory cells (e.g., NAND strings of memory structure  202 ) on memory die  201 . In one embodiment, the process of  FIG.  14    is performed at the direction of state machine  262  (or another processor). The control circuit is connected to the memory cells (e.g., via control lines such as word lines, bit lines, source line and select lines), as described above with respect to  FIGS.  1 - 4 J . The process of  FIG.  14    is an example implementation of the processes of  FIG.  8   ,  FIG.  9    and/or  FIG.  10   . 
     In step  1402  of  FIG.  14   , the control circuit performs full sequence programming (see e.g.,  FIG.  5 C ) to a set of target data states for a first set of data, including applying one or more voltage pulses (see e.g., step  608  of  FIG.  6   ) to the selected word line prior to the pre-charging. Step  1402  can be performed using the process of  FIG.  6   . In some embodiments, step  1402  corresponds to and provides an example of steps  802 ,  902  and  1002 . In step  1404  of  FIG.  13   , the control circuit performs a soft erase process (e.g., the process of  FIG.  11   ) after the full sequence programming of step  1402 . In some embodiments, step  1304  corresponds to and provides an example of steps  804 ,  904  and  1004 - 1008 . 
     In step  1406 , the control circuit performs additional programming for the first set of data and set of target data states after the soft erase process by applying one programming voltage pulse per data state (of the data states being programmed to by the programming process) to the memory cells. In the example of  FIG.  5 C  (8 states to store 3 bits of data per memory cell), those memory cells that are being programmed to state A will receive one programming voltage pulse (applied via WLn), those memory cells that are being programmed to state B will receive two programming voltage pulses (applied via WLn), those memory cells that are being programmed to state C will receive three programming voltage pulses (applied via WLn), those memory cells that are being programmed to state D will receive four programming voltage pulses (applied via WLn), those memory cells that are being programmed to state E will receive five programming voltage pulses (applied via WLn), those memory cells that are being programmed to state F will receive six programming voltage pulses (applied via WLn), and those memory cells that are being programmed to state G will receive seven programming voltage pulses (applied via WLn). In some embodiments, step  1406  corresponds to and provides an example of steps  802 ,  906  and  1010 . 
     A memory system has been described that includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging. The use of the soft programming process improves data retention properties of the memory, which maintains the narrow widths of the programmed threshold voltage distributions, thereby reducing errors when read programmed data. 
     One embodiment includes a non-volatile storage apparatus, comprising: a plurality of non-volatile memory cells; and a control circuit connected to the non-volatile memory cells. The control circuit is configured to program the memory cells including performing a soft erase process on the memory cells during the programming of the memory cells. The performing of the soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging. 
     In one example implementation, the plurality of non-volatile memory cells are part of NAND strings connected to word lines; the control circuit is configured to perform the pre-charging by pre-charging channels of the NAND strings to one or more positive pre-charge voltages; the control circuit is configured to boost the pre-charged channels to one or more positive boosted voltages above the one or more pre-charge voltages channels by turning off source side select gates and drain side select gates for the NAND strings, the erase operation is performed on the boosted channels; the memory cells being programmed are connected to a selected word line of the plurality of word lines, the control circuit is configured to perform the erase operation by applying a negative erase voltage to the selected word line; the control circuit is configured to apply a first voltage to one or more unselected word lines of the plurality of word lines that are adjacent the selected word line while applying the negative erase voltage; and the control circuit is configured to apply a second voltage to one or more unselected word lines of the plurality of word lines that are not adjacent the selected word line while applying the negative erase voltage, the first voltage is lower than the second voltage. 
     One embodiment includes a method for programming non-volatile storage, comprising: starting a programming process that includes performing initial programming on a plurality of non-volatile memory cells; after performing the initial programming and prior to completing the programming process, pre-charging channels associated with the non-volatile memory cells to one or more pre-charge voltages; boosting the pre-charged channels to a positive voltage above the one or more pre-charge voltages; while the channels are boosted, applying a negative erase voltage to the non-volatile memory cells to cause a partial erasing of the memory cells being programmed; and performing additional programming of the non-volatile memory after the applying of the negative erase voltage. 
     One embodiment (see  FIGS.  9 ,  12 ,  13  and  14   ) includes a non-volatile storage apparatus, comprising: a plurality of NAND strings, each of which includes multiple non-volatile memory cells; and a control circuit connected to the NAND strings. The control circuit is configured to: start a process to write data to the NAND strings by applying multiple voltage pulses to gate terminals of selected memory cells on the NAND strings to increase threshold voltages of the selected memory cells on the NAND strings; before completing the process to write the data to the NAND strings, pre-charge channels of the NAND strings to one or more positive pre-charge voltages; boost the pre-charged channels to one or more positive boosted voltages above the one or more positive pre-charge voltages; while the channels are boosted, applying a negative voltage pulse to the gate terminals of selected memory cells on the NAND strings to decrease threshold voltages of the selected memory cells on the NAND strings; and complete the process to write the data to the NAND strings by applying at least one additional voltage pulse to gate terminals of selected memory cells on the NAND strings to increase threshold voltages of the selected memory cells on the NAND strings. 
     In one example implementation, the control circuit is configured to pre-charge the channels of the NAND strings from a source side of the NAND strings and from a drain side of the NAND strings; the control circuit is configured to boost the pre-charged channels by turning off source side select gates and drain side select gates for the NAND strings; the control circuit is configured to apply a first voltage to gate terminals of unselected memory cells on the NAND strings that are adjacent to the selected memory cells while applying the negative voltage pulse to the gate terminals of selected memory cells on the NAND strings; and the control circuit is configured to apply a second voltage to gate terminals of unselected memory cells on the NAND strings that are not adjacent to the selected memory cells while applying the negative voltage pulse to the gate terminals of selected memory cells on the NAND strings, the first voltage is lower than the second voltage. 
     For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment. 
     For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them. 
     For purposes of this document, the term “based on” may be read as “based at least in part on.” 
     For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects. 
     For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects. 
     The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.