Patent Publication Number: US-7911437-B1

Title: Stacked amplifier with charge sharing

Description:
FIELD OF THE INVENTION 
     The present invention is generally related to column drivers for a graphics display. More particularly, the present invention relates to a column driver that includes stacked amplifiers with switching circuits coupled to their outputs, and arranged for improved performance with a charge sharing topology. 
     BACKGROUND 
     Graphics displays such as LCDs are organized according to rows and columns. A pixel in the LCD display is addressed by activating a column driver and a row selector. Separate buffer amplifiers (column drivers) are employed to drive each respective column of the LCD. Thus, a typical LCD requires hundreds of buffer amplifiers to drive all of the columns in the display. Each of the buffer amplifiers is generally required to drive a rail-to-rail signal to the respective one of the columns in the LCD. 
     Color LCDs typically include multiple color planes (e.g., RGB). Each pixel address typically includes a separate pixel for each color plane. Pixels in the LCD are arranged as charge storage elements that are represented as capacitors. Each row selector operates as a switch that couples the output of a column driver to pixel in the LCD array. The charge stored in the pixel is an analog quantity that determines the brightness associated with the pixel. For color pixel arrays, the color associated with a selected pixel is determined by the charge stored in each of the pixels associated with the color planes. A typical color LCD also requires hundreds of buffer amplifiers to drive all of the columns in the display. 
     Pixels in the LCD are susceptible to damage when a DC voltage is maintained across the LCD for long periods of time. The liquid crystal damage is a result of charge migration across the liquid crystal, possibly de-ionizing the material. The result of the charge migration is that the LCD material will stick to the surfaces and cause image retention issues such as a sticking image. To prevent damaging the LCD material, the polarity of the signal applied to the LCD pixel is periodically reversed, typically every frame. An example LCD display system uses an alternating pixel pattern referred to as pixel inversion. In a pixel inversion system, each LCD column must be operated about a common voltage such that the output for each odd column is operated in an opposite range (e.g., from VDD to VDD/2) as the output for the even columns (e.g., from VDD/2 to VSS). 
     A liquid crystal display (LCD) system is illustrated in  FIG. 1A . The LCD display system includes an LCD array that is organized according to rows and columns. A timing and control block receives video data and generates the necessary timing signals to selectively activate pixels in the LCD system. The timing and control signals activate a pixel by enabling a column driver and a row selector. Thin film transistor (TFT) type displays have a transistor array that is placed on top of liquid crystal array to operate as the row selectors. 
     The column drivers from  FIG. 1A  can be arranged as part of a charge share topology with the addition of extra switching circuits and capacitors as illustrated by  FIG. 1B . N column drivers (DRV 1 -DRVN) include corresponding inputs IN 1  through INN and outputs that are connected to column lines  1  through N. An array of switches (S 1 -SN) is used to connect all of the outputs of the column drivers. For example, just prior to the columns switching between voltage ranges (e.g., many LCD displays use line inversion, and often larger sized displays use pixel inversion) the switches are activated to couple the column outputs together to a charge storage capacitor (CSTORE). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. 
         FIGS. 1A and 1B  are schematic diagrams for a conventional LCD system. 
         FIG. 2  is a schematic diagram of a stacked amplifier column driver circuit using a charge share topology arranged in accordance with at least an aspect of the present invention. 
         FIG. 3  is a schematic diagram of another stacked amplifier column driver circuit using a charge share topology arranged in accordance with still another aspect of the present invention. 
         FIG. 4A  is a schematic diagram of yet another stacked amplifier column driver circuit using a charge share topology arranged in accordance with yet another aspect of the present invention. 
         FIG. 4B  is a schematic diagram of a common voltage reference generator that may be employed by a stacked amplifier column driver circuit that is arranged in accordance with at least some aspect of the present invention. 
         FIG. 4C  is a schematic diagram of addition amplifier configurations for a stacked amplifier column driver circuit that is arranged in accordance with at least some aspect of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention. 
     Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meanings identified below are not intended to limit the terms, but merely provide illustrative examples for use of the terms. The meaning of “a,” “an,” and “the” may include reference to both the singular and the plural. The meaning of “in” may include “in” and “on.” The term “connected” may mean a direct electrical, electro-magnetic, mechanical, logical, or other connection between the items connected, without any electrical, mechanical, logical or other intermediary therebetween. The term “coupled” can mean a direct connection between items, an indirect connection through one or more intermediaries, or communication between items in a manner that may not constitute a connection. The term “circuit” can mean a single component or a plurality of components, active and/or passive, discrete or integrated, that are coupled together to provide a desired function. The term “signal” can mean at least one current, voltage, charge, data, or other such identifiable quantity 
     Briefly stated, the present disclosure generally relates to column drivers for a graphics display. Column drivers for graphics displays can be arranged as stacked amplifiers with various switching circuits arranged in a charge sharing topology. The apparatus includes an upper and lower amplifier circuit, an input switching circuit, and an output switching circuit. The upper and lower amplifier circuits drive column lines can be swapped during operation by the input and output switching circuits. During a charge share operation, the outputs of the amplifiers are coupled to a common voltage via the output switching circuit, while the transistors from the output stage of each amplifier is reconfigured for charge sharing. Minimally sized transistors are utilized inside the output stage of the amplifiers for charge share configuration. Since the existing transistors from the output stage are utilized for the charge sharing operation, additional space savings and power reductions can be realized. 
       FIG. 2  is a schematic diagram of a stacked amplifier column driver circuit ( 200 ) using a charge share topology arranged in accordance with at least an aspect of the present invention. The stacked amplifier column driver circuit includes an upper amplifier circuit (X 1 ), a lower amplifier circuit (X 2 ), an input switching circuits (X 6 ), an output switching circuit (X 3 ), a reference circuit (X 4 ), and a control logic circuit (X 5 ). Circuit  200  can be configured as an integrated circuit where the various column line outputs (e.g., ODD_OUT and EVEN_OUT) can be coupled to bonding pads such that external connectivity to the column driver circuits is provided. 
     The upper amplifier circuit (X 1 ) includes an input that is coupled to a first node (N 1 ) and an output terminal that is coupled to a third node (N 3 ). The lower amplifier circuit (X 2 ) includes an input terminal that is coupled to a second node (N 2 ) and an output terminal that is coupled to a fourth node (N 4 ). The input switching circuit (X 6 ) is coupled to an odd column input terminal (ODD_IN), an even column input terminal (EVEN_IN), the first node (N 1 ), the second node (N 2 ), and an input switch control signal. Output switching circuit X 3  is coupled to an odd column line output terminal (ODD_OUT) at node N 5 , and even column line output terminal (EVEN_OUT) at node N 6 , the third node (N 3 ), the fourth node, and an output switch control signal. The reference circuit (x 4 ) is arranged to provide a common supply voltage (VCOM) at node N 7 . Various control signals can be provided by a control logic circuit (X 5 ) that is responsive to an input control signal such as a from a clock signal (CLK). 
     The upper amplifier circuit (X 1 ) also includes a high supply terminal that corresponds to VDD, and a low supply terminal that corresponds to VCOM. The lower amplifier circuit (X 2 ) includes a high supply terminal that corresponds to VCOM, and a low supply terminal that corresponds to VSS. Both amplifier circuits X 1  and X 2  share a common supply level at node N 7  that corresponds to VCOM. In one example, VSS corresponds to 0V and VCOM corresponds to VDD/2. In another example, VCOM corresponds to 0V and VDD and VSS are equidistant from 0V. Generally, VCOM can be designated as a middle supply voltage that such as [(VDD−VSS)/2+VSS]. 
     The input switching circuit (X 6 ) is arranged to couple the odd input terminal (ODD_IN) to either node N 1  or node N 2  in response to the input switch control signal. An example implementation of the input switching circuit is further illustrated in  FIG. 4A  by switching circuits SI 1  and SI 2 . The output switching circuit (X 3 ) is arranged to selectively couple or decouple nodes N 3  and N 4  from the odd column line (ODD_OUT) at node N 5  or the even column line (EVEN_OUT) at node N 6  in response to the output switch control signal. An example implantation of the output switching circuit X 3  that includes four switches (S 1 -S 4 ) is illustrated in  FIGS. 3 and 4A . 
     The upper amplifier circuit (X 1 ) and the lower amplifier circuit (X 2 ) each include a respective output stage (X 11  and X 21 ) that are configured for charge share operation via a charge share control signal that can be provided by the control logic circuit (X 5 ). During charge share operation, the transistors in the output stages that are normally used for driving the output of the amplifier are configured to couple the common node (N 7 ) to their respective outputs (N 3  and N 4 ). Since the transistors that are used for charge sharing in the output stages are pre-existing transistors from the output stage itself, minimal addition space is necessary for large transistors (e.g., on the order of 50 um in many processes) to implement the charge sharing topology. Die area is thus conserved as well as power consumption. See the discussion for  FIG. 3  for an example implementation of the output stage. 
     Each of the amplifier circuits (X 1 , X 2 ) operates over half of the total power supply range (e.g., VCOM-VDD and VSS-VCOM). The upper and lower amplifier circuits need not provide outputs levels that swing over the entire supply range (VSS through VDD). Each of the amplifier circuits can be optimized to operate over the limited supply range. For example, the differential input transistors in an input stage (X 10 ) of the upper amplifier circuit (X 1 ) can be implemented as n-type devices that operate over the upper supply range (VDD to VCOM), while the differential input transistors in an input stage (X 20 ) of the lower amplifier circuit (X 2 ) can be implemented as p-type devices that operate over the lower supply range (VCOM to VSS). The complexity of the amplifier circuits is simplified since the amplifiers need not operate over the full supply levels. Also, since the amplifier circuits only operate over half of the supply range, the amplifier circuits can employ devices (e.g., transistors, diodes, etc.) that have breakdown voltages that are less than the full supply voltage without the need for additional protection devices. Since additional protection devices would add parasitic capacitances to the circuits, additional protection devices would degrade the speed of the amplifier circuits. 
     An example display may have a resolution of 1024×768 pixels, requiring 1024 column driver amplifier circuits for a monochrome display, and 3072 column drives are required when there are three color planes. Since the number of column driver amplifier circuits is very large, any savings in power consumption for a column driver cell may have dramatic results in total power consumption. The limited range of operation for the amplifiers will result in a reduction in overall power that is consumed by each column drivers. The described charge sharing topology will further reduce power consumption. Also, since minimal additional devices are necessary in the output stage circuit of the amplifiers, the increase in die area for a large number of column drivers is also minimal. 
       FIG. 3  is a schematic diagram of another stacked amplifier column driver circuit ( 300 ) using a charge share topology arranged in accordance with still another aspect of the present invention. The stacked amplifier column driver circuit includes an upper amplifier circuit (AMP 1 , X 31 ), a lower amplifier circuit (AMP 2 , X 32 ), an output switching circuit (X 33 ), a control logic circuit (X 34 ), and an optional reference circuit (X 35 ). Stacked amplifier column driver circuit  300  is similar in operation to stacked amplifier column driver circuit  200  from  FIG. 2 . Circuit  300  can be configured as an integrated circuit where ODD_OUT and EVEN_OUT can be coupled to bonding pads such that external connectivity to the column driver circuit is provided. 
     The upper amplifier circuit (X 31 ) includes an input stage and an output stage. The output stage of the upper amplifier circuit (X 31 ) is illustrated as transistors MCSP, MPA 1  and MNA 1 . Transistors MCSP and MPA 1  are p-type transistors, while transistor MNA 1  is an n-type transistor. Transistor MCSP includes a gate that is coupled to the CSHARE control signal, a source that is coupled to the high power supply voltage (VDD), and a drain that is coupled to a first drive signal (NDRV 1 ). Transistor MPA 1  includes a gate that is coupled to a second drive signal (PDRV 1 ), a source that is coupled to the high power supply voltage (VDD), and a drain that is coupled to the output of the upper amplifier at node N 33 . Transistor MNA 1  includes a gate that is coupled to the first drive signal (NDRV 1 ), a source that is coupled to the common voltage (VCOM) at node N 37 , and a drain that is coupled to the output of the upper amplifier at node N 33 . 
     The lower amplifier circuit (X 32 ) also includes an input stage and an output stage. The output stage of the upper amplifier circuit (X 32 ) is illustrated as transistors MCSN, MPA 2  and MNA 2 . Transistor MPA 2  is a p-type transistor, while transistors MCSN and MNA 2  are n-type transistors. Transistor MCSN includes a gate that is coupled to the CSHAREB control signal, a source that is coupled to the low power supply voltage (VSS), and a drain that is coupled to a fourth drive signal (PDRV 2 ). Transistor MPA 2  includes a gate that is coupled to the fourth drive signal (PDRV 2 ), a source that is coupled to the common voltage (VCOM) at node N 37 , and a drain that is coupled to the output of the lower amplifier at node N 34 . Transistor MNA 2  includes a gate that is coupled to a third drive signal (NDRV 2 ), a source that is coupled to the low power supply voltage (VSS), and a drain that is coupled to the output of the lower amplifier at node N 34 . 
     Transistors MPA 1  and MNA 1  are arranged in a push-pull configuration that is responsive to drive signals PDRV 1  and NDRV 1  to drive a common output at node N 33  such that the upper amplifier is providing amplification in a non-charge sharing operational state. Similarly, transistors MPA 2  and MNA 2  are arranged in a push-pull configuration that is responsive to drive signals PDRV 2  and NDRV 2  to drive a common output at node N 34  when the lower amplifier is providing amplification in a non-charge sharing operational state. These drive signals (PDRV 1 , NDRV 1 ; and PDRV 2 , NDRV 2 ) are provided by a preceding stage of the amplifier to the output stage. For example, in a folded cascade design, the input stage is arranged to activate high impedance current sources that drive the output stage. 
     The output switching circuit (X 33 ) includes four switches (S 1 -S 4 ). Switches S 1  and S 3  are activated in response to control signal EN 1  to couple node N 33  to node N 35  via switch S 1 , and also couple node N 34  to node N 35  via switch S 3 . Switches S 2  and S 4  are activated in response to control signal EN 2  to couple node N 33  to node N 36  via switch S 2 , and also couple node N 34  to node N 35  via switch S 4 . Each of the switches can be implemented as a single transistor, two transistors arranged as a transmission gate, or any other transistor based switching circuit as will be understood to those of skill in the art. 
     Charge sharing is accomplished by actuation of the output switching circuit (X 33 ) together with the operation of transistors MCSP and MCSN in the output stage of the amplifier circuits. When transistor MCSP is activated in response to control signal CSHARE, transistor MNA 1  is activated and node N 37  is effectively coupled to node N 33 . Similarly, when transistor MCSN is activated in response to control signal CSHAREB, transistor MPA 2  is activated and node N 37  is effectively coupled to node N 34 . Switching circuits X 33  and X 34  are operated in a closed circuit position during charge sharing such that nodes N 33 , N 34 , N 35  and N 36  are also coupled together to node N 37 . Since all of the amplifier circuits in the driver array share a common connection to node N 37 , the switching arrangement provides effective charge sharing with the addition of minimal components. 
     Transistors MCSP and MCSN can be small switching transistors (e.g., on the order of 1 um in width for an example MOS device) since they don&#39;t conduct a significant amount of current (the current in the driver is provided by transistors MPA 1 , MNA 1 , MPA 2  and MNA 2 ). In contrast, the switching transistors used in conventional charge share circuits are external to the amplifiers, conduct a larger amount of current, and are larger in size (e.g., on the order of 50 um in width for an example MOS device) since the on-resistance needs to be relatively low. The area savings can be quite significant since a large number of output devices may be required for an example column driver array (e.g. in excess of 100 drivers in many applications). Also, the conventional charge share circuits present a significant capacitive load on their control signals since the gate area for these switching devices is increased to provide a nominally low on-resistance. In contrast, transistors MCSP and MCSN are very small devices that don&#39;t provide a significant capacitive load on the control signals (CSHARE, CSHAREB). The reduced drive requirements for MCSP and MCSN further reduced power consumption. 
     The control logic circuit (X 34 ) is arranged to provide the various control signals that are necessary for charge sharing, as well as any other output swapping functions that are necessary during amplification. The charge share control signals in this example are comprised of signals CSHARE and CSHAREB, which are simply inversely related to one another. The output switch control signals in this example are comprised of signals EN 1  and EN 2 . During amplification, either signal EN 1  is asserted or signal EN 2  is asserted such that nodes N 33  and N 34  are not shorted together. However, during charge share operation both signals EN 1  and EN 2  are asserted so that nodes N 33  and N 34  are effectively shorted together through the output switching circuit (X 33 ). 
     The optional reference circuit (X 35 ) is arranged to provide a reference voltage (VCOM) at node N 37 . The reference voltage can be provided as a temperature compensated voltage such as by a bandgap circuit, or a non-temperature compensated voltage. The reference voltage is provided from a voltage source that can either be an on-chip voltage generator or an off-chip voltage generator (e.g., a voltage regulator). In a common application, the reference voltage can be provided by a voltage divider circuit and a buffer, similar to that described with reference to  FIG. 4B . 
       FIG. 4A  is a schematic diagram of yet another stacked amplifier column driver circuit ( 400 ) using a charge share topology arranged in accordance with yet another aspect of the present invention. The stacked amplifier column driver circuit includes an upper amplifier circuit (X 41 ), a lower amplifier circuit (X 42 ), two input switching circuits (SI 1 , SI 1 ), and an output switching circuits (X 43 ). Stacked amplifier column driver circuit  400  is similar in operation to stacked amplifier column driver circuit  200  from  FIG. 3 , where the amplifier circuits are arranged as an inverting amplifier circuit. Circuit  400  can be configured as an integrated circuit where ODD_OUT and EVEN OUT can be coupled to bonding pads such that external connectivity to the column driver circuit is provided. 
     Similar to the schematic illustrated in  FIG. 3 , the upper amplifier circuit (X 41 ) includes a high supply terminal that corresponds to VDD, and a low supply terminal that corresponds to VCOM. The lower amplifier circuit (X 32 ) includes a high supply terminal that corresponds to VCOM, and a low supply terminal that corresponds to VSS. 
     Amplifier circuit X 41  includes an operation amplifier circuit (X 31 ) and two resistors (R 41 , R 42 ), and is arranged to operate as an inverting amplifier circuit that has a gain that is determined by a first feedback network (e.g., resistors R 41  and R 42 ). The upper amplifier circuit (X 41 ) also includes an upper common voltage (VCOMU) that is typically a middle-supply for the range from VCOM to VDD. In other words, VCOMU is determined by VCOM and VDD as: VCOMU=VCOM+(VDD−VCOM)/2. In operation, the inverting input of amplifier circuit X 41  will have the same DC level as the non-inverting input such that the DC voltage at node N 42  will be VCOMU. Amplifier X 41  need not operate over a rail-to-rail input range when configured as an inverting amplifier, and instead has a limited operating range that is centered on VCOMU. Operation amplifier circuit X 31  includes an output stage circuit as that previously described for  FIG. 3 , which is responsive to the control signal CSHARE. 
     Amplifier circuit X 42  includes an operation amplifier circuit (X 32 ) and two resistors (R 43  and R 44 ), and is arranged to operate as an inverting amplifier circuit that has a gain that is determined by a second feedback network (e.g., resistors R 43  and R 44 ). The lower amplifier circuit (X 42 ) also includes a lower common voltage (VCOML) that is typically a middle-supply for the range from VSS to VCOM. In other words, VCOML is determined by VCOM and VSS as: VCOML=VSS+(VCOM−VSS)/2. In operation, the inverting input of amplifier circuit X 42  will have the same DC level as the non-inverting input such that the DC voltage at node N 45  will be VCOML. Amplifier X 42  need not operate over a rail-to-rail input range when configured as an inverting amplifier, and instead has a limited operating range that is centered on VCOML. Operation amplifier circuit X 32  also includes an output stage circuit as that previously described for  FIG. 3 , which is responsive to the control signal CSHAREB. 
     The control logic circuit (X 44 ) is arranged to provide the various control signals that are necessary for charge sharing, as well as any other input or output swapping functions that are necessary during amplification. The charge share control signals in this example are comprised of signals CSHARE and CSHAREB, which are simply inversely related to one another. The output switch control signals in this example are comprised of signals EN 1  and EN 2 . During amplification, either signal EN 1  is asserted or signal EN 2  is asserted such that nodes N 33  and N 34  are not shorted together. Also during amplification, the input switch control signal is arranged to swap the input signals (ODD_IN and EVEN_IN) relative to nodes N 41  and N 44  to match the swapping operation of the output switch control circuit (X 43 ). However, during charge share operation both signals EN 1  and EN 2  are asserted so that nodes N 33  and N 34  are effectively shorted together through the output switching circuit (X 33 ). 
       FIG. 4B  is a schematic diagram of a common voltage reference generator ( 410 ) that may be employed by a stacked amplifier column driver circuit (e.g.,  200 ,  300  and  400 ) that is arranged in accordance with at least some aspect of the present invention. The voltage reference includes four equal value resistors (R) and a buffer circuit (X 45 ). The resistors (R) are arranged as a voltage divider network that is coupled between the upper power supply (VDD) and the lower power supply (VSS). The buffer circuit (X 45 ) is coupled to the center tap of the voltage divider such that VCOM is half way between VDD and VSS, or VCOM=VSS+(VDD−VSS)/2. VCOMU is coupled to the top tap of the resistor divider such that VCOMU is half way between VCOM and VDD, or VCOMU=VCOM+(VDD−VCOM)/2. VCOML is coupled to the VCOM, or VCOML=VSS+(VCOM−VSS)/2. The buffer circuit is provided such that currents from the amplifier circuits (see  FIGS. 2A ,  3  and  4 A) do not change the voltage associated with VCOM. 
     Voltage reference circuit  410  is an example of one possible voltage reference that may be employed by the various amplifier circuits. However, any other appropriate voltage reference circuit may be employed in place of the voltage reference circuit that is illustrated in  FIG. 4B . Other example voltage references include band-gap based voltage references (see e.g.,  FIG. 3 ), and non band-gap based voltage references, to name a few. 
     The switching circuits employed in the various amplifier circuits can be any circuit that is arranged to provide a switching function. In one example, the switching circuits are field effect transistors (FETs) such as metal-oxide semiconductor (MOS) devices. However, the same circuit configuration is equally applicable for bipolar junction transistors (BJTs), as well as others. Other example circuits that perform the switching functions described above are considered within the scope of the present invention. 
     The amplifier and buffer circuits employed in  FIGS. 2A through 4C  can be any circuit that is arranged to provide an amplifier function, where the upper and lower amplifiers are matched in overall quiescent current. Each of the amplifier circuits is a differential amplifier that includes a differential pair input stage and an output stage that is arranged for charge sharing operation. In one example, the upper amplifier circuit has N-type transistors in the differential pair input stage and the lower amplifier circuit has P-type transistors. The transistors can be field effect transistors (FETs) such as metal-oxide semiconductor (MOS) devices. However, the same circuit configuration is equally applicable for bipolar junction transistors (BJTs), as well as others. 
     Other example circuits that perform the amplifying/buffering functions described above are considered within the scope of the present invention.  FIG. 4C  is a schematic diagram that illustrates some addition example configurations for a stacked amplifier column driver circuit that is arranged in accordance with at least some aspect of the present invention. A first example configuration that is illustrated is for a buffer amplifier configuration ( 410 ), where the upper amplifier circuit (AMP 1 ) and the lower amplifier circuit (AMP 2 ) are arranged as a stacked amplifier that are responsive the charge share control signal for charge share operation. A second example configuration that is illustrated is for a non-inverting gain amplifier configuration ( 420 ), where the upper amplifier circuit (AMP 1 ) and the lower amplifier circuit (AMP 2 ) are arranged as a stacked amplifier that are responsive the charge share control signal for charge share operation, with the addition of a feedback network (Z 1  and Z 2 ) that is arranged to set the gain of the non-inverting amplifiers. The feedback networks used by the various amplifier configuration described herein may be passive or active components, including but not limited to resistors, capacitors, inductors, switched capacitors, and other components as will be understood by those of skill in the art. 
     Although the invention has been described herein by way of exemplary embodiments, variations in the structures and methods described herein may be made without departing from the spirit and scope of the invention. For example, the positioning of the various components may be varied. Individual components and arrangements of components may be substituted as known to the art. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention is not limited except as by the appended claims.