Patent Publication Number: US-11664787-B2

Title: CMOS laddered inverter ring oscillator

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. Provisional Application Ser. No. 63/156,610 filed Mar. 4, 2021, the contents of which are hereby incorporated by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to ring oscillator technology. 
     BACKGROUND 
     A ring oscillator is a device or circuit that includes an odd number of NOT gates or inverters in a ring whose output oscillates non-sinusoidally between output levels. A single inverter computes the logical NOT of its input, and thus the last output of a chain of an odd number of inverters is the logical NOT of the first input. The final output of the ring oscillator thereby becomes the input to the ring oscillator and, being the logical NOT to the first input, continues to drive the oscillation. 
     A ring oscillator typically only requires power to operate, and above a certain voltage, typically well below the threshold voltage of the MOSFETs used, oscillations begin spontaneously. To increase the frequency of oscillation, two methods are commonly used. First, making the ring from a smaller number of inverters results in a higher frequency of oscillation, with about the same power consumption. Second, the supply voltage may be increased. In circuits where this method can be applied, this reduces the propagation delay through the chain of stages. 
     In operation and in a device using MOSFETS, gate capacitance is charged before current can flow between the source and the drain, resulting in an oscillating output that changes after a period of time after the input is charged. Thus, there is a time delay between the output and the input, and since the amplifier in such a circuit has a negative gain, the output will change in a direction opposite that of the input—hence the NOT designation. 
     A time-delay of the typical ring oscillator may be effected by adding even numbers of inverters without affecting the “NOT” output. Rather than having a single time delay element, each inverter contributes to the delay of the signal around the ring, and adding pairs of inverters increases the delay, thereby decreasing the oscillator frequency. The delay may also be effected by changing the supply voltage. 
     The ring oscillator circuit has many uses in electronics and communications. Applications include edge internet-of-things (IoT) devices, start-up systems thermoelectric energy harvesting, time to digital circuits, time domain neural networks, voltage controlled ring oscillators for biomedical applications, and frequency locked loops, as examples. The ring oscillator may also be used in a battery saver circuit in a larger system aimed at extending battery life of portable devices. The speed of the inverter is typically in the 115 MHz-1.8 GHz range, but has the ability to give high time resolution owing to the laddered structure of the ring oscillator. In the CMOS inverter ring oscillator the number of phases is increased by increasing the number stages to another odd number. 
     Because the time delay in a typical ring oscillator is due, at least in part, to the gate capacitance and the time and energy to charge, the overall time delay of the oscillator can be increased by adding inverters in pairs—reducing the oscillation frequency. As indicated, adding in pairs maintains the same NOT status while impacting the frequency of operation. Typically, the oscillation period is equal to twice the sum of individual delays of all the stages. Use of inverters, however, can have its downside due to the increased power consumption by the use of many inverters. 
     As such, there is a need for an improved ring oscillator. 
     BRIEF SUMMARY 
     A ring oscillator includes a first set of at least three laddered inverter quantizer (LIQAF) circuits connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input creates a pair of phase shifted waveforms in the first of the at least three LIQAF circuits that propagate sequentially through the stages of the at least three LIQAF circuits. Each stage has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage. 
     A method of constructing a ring oscillator includes connecting a first set of at least three laddered inverter quantizer (LIQAF) circuits in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and providing a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input creates a pair of phase shifted waveforms in the first of the at least three LIQAF circuits that propagate sequentially through the stages of the at least three LIQAF circuits. Each stage has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage. 
     A ring oscillator includes a structure having a two level CMOS laddered inverter quantizer (LIQAF) and three horizontal LIQAF blocks, the three horizontal LIQAF blocks in each of the two levels connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input in the three horizontal LIQAF blocks in each of the two levels creates a pair of phase shifted waveforms in the first of the three horizontal LIQAF blocks that propagate sequentially through the stages of the three LIQAF blocks. Each stage of the three horizontal LIQAF blocks in each of the two levels has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       While the claims are not limited to a specific illustration, an appreciation of the various aspects is best gained through a discussion of various examples thereof. Although the drawings represent illustrations, the drawings are not necessarily to scale and certain features may be exaggerated to better illustrate and explain an innovative aspect of an example. Further, the exemplary illustrations described herein are not intended to be exhaustive or otherwise limiting or restricted to the precise form and configuration shown in the drawings and disclosed in the following detailed description. Exemplary illustrates are described in detail by referring to the drawings as follows: 
         FIG.  1 A  illustrates an exemplary a LIQAF circuit; 
         FIG.  1 B  illustrates the circuit of  FIG.  1 A  as a combination of two CMOS inverters that have different ratios of NMOS versus PMOS gate lengths; 
         FIG.  1 C  is an illustration of exemplary and simulated shifted direct current (DC) characteristics yielded from the exemplary circuit of  FIG.  1 A ; 
         FIG.  2 A  is an illustration of an exemplary LIQAF structure expanded out for three stages to form a ring oscillator (exemplary six output phase ring oscillator); 
         FIG.  2 B  illustrates an exemplary output of the exemplary structure of  FIG.  2 A . 
         FIG.  3    is an illustration of an exemplary general CMOS LIQAF topology having an arbitrary number of outputs; 
         FIG.  4    illustrates an exemplary oscillation frequency comparison between an exemplary CMOS inverter ring oscillator and an exemplary CMOS LIQAF ring oscillator; 
         FIG.  5    illustrates an exemplary power consumption comparison between an exemplary CMOS inverter ring oscillator and an exemplary CMOS LIQAF ring oscillator; 
         FIG.  6    illustrates an exemplary power consumption comparison robustness simulation; 
         FIG.  7    illustrates an exemplary oscillation frequency robustness simulation; 
         FIG.  8    illustrates exemplary multi-level CMOS LIQAF ring oscillator output plots for power consumption and oscillation frequency vs. supply voltage; 
         FIG.  9    illustrates an exemplary two (2) output pulse train having two (2) distinct outputs from a multiplexer (MUX) with each level having expanded duty cycle from the previous level; 
         FIG.  10    illustrates an exemplary four (4) output pulse train having four (4) distinct outputs from a MUX with each level having expanded duty cycle from the previous level; 
         FIG.  11    illustrates an exemplary eight (8) output pulse train having eight (8) distinct outputs from a MUX with each level having expanded duty cycle from the previous level; 
         FIG.  12    illustrates an exemplary sixteen (16) output pulse train having sixteen (16) distinct outputs from a MUX with each level having expanded duty cycle from the previous level; 
         FIG.  13    illustrates an exemplary thirty-two (32) output pulse train having thirty-two (32) distinct outputs from a MUX with each level having expanded duty cycle from the previous level; and 
         FIG.  14    illustrates an exemplary Monte Carlo analysis performed on an exemplary circuit with the variable being the output frequency. The exemplary Monte Carlo results agree with measured simulation results of 1.88 GHz at 1.2V, TT. 
     
    
    
     DETAILED DESCRIPTION 
     According to the disclosure, a V DD  controlled, ring oscillator provides several phase shifted outputs based on a laddered inverter quantizer (LIQAF) circuit. V DD  is the input and the outputs are the intermediate LIQAF outputs. The disclosed circuit achieves the several phase shifted waveforms by the use of the LIQAF circuit as a chain of parallelized inverters. These inverters each have their own propagation delay, which all yield a phase shifted version of the same waveform. Exemplary pre and post layout show simulation results for 2, 4, and 8-level versions of the ring oscillator circuit in a 65 nm CMOS process are disclosed. Exemplary results demonstrate that the disclosed circuit can operate at low-power consumption from a wide range of supply voltages with robust operation across process and temperature variations. The disclosed circuit has the potential to be integrated into, for example, a Time to Digital Converter along with other implementations. 
     The Laddered-Inverter Quantizer/Amplifier/Filter (LIQAF) may be considered as an inverter topology. The inverter in this case is two CMOS inverter laddered, see  FIG.  1 A . M 0  and M 1  form an inverter  104  while M 2  and M 3  form another inverter  106 . The operation of this circuit allows for two outputs that are unique in phase, generated from one input. As indicated in  FIG.  1 B , the circuit can be viewed as a combination of two CMOS inverters that have different ratios of n-channel metal oxide semiconductor (NMOS) versus p-channel metal oxide semiconductor (PMOS) gate lengths, which yields the exemplary shifted DC characteristics shown in  FIG.  1 C . 
     Referring to  FIGS.  1 A and  1 C , when V in  is generally low and both outputs are high, transistor M 1  is inactive such that V out0  transitions with increasing V in  according to a CMOS inverter characteristic with one NMOS device, M 0 , and two series PMOS devices, M 2  and M 3 . In contrast, when V in  is high and both outputs are low, M 2  is inactive such that V out1  transitions with decreasing V in  according to a CMOS inverter characteristic with two series NMOS, M 0  and M 1 , devices and one PMOS device, M 3 . Looking at V out1 , this inverter is pulled high by M 3  and pulled low by M 0  and M 1 . Looking at V out0 , this inverter is pulled high by M 2  and M 3  and pulled low by M 0 . This stacking generally causes the exemplary shifted DC characteristic  100 ,  102  shown in  FIG.  1 C . It follows that V out1  is high for V out0  to go high and V out0  is low for V out1  to go low. This fundamental characteristic is taken advantage of in the PWM generation shown in the exemplary measurement results. 
     Disclosed Ring Oscillator Circuit 
     Consider a simple three stage two level CMOS LIQAF Oscillator  200  expanded out for three stages to form a ring oscillator in  FIG.  2 A . In this implementation there are three exemplary horizontal LIQAF blocks,  202 ,  204 ,  206  which correspond to the number of stages, and there are two outputs for each stage, respectively,  208 / 209 ,  210 / 211 ,  212 / 213 . Each of the outputs feeds into the next stage. The three LIQAF pairs  202 ,  204 ,  206  in  FIG.  2 A  are M s1,3 /M s1,2 , M s2,3 /M s2,2 , and M s3,3 /M s3,2 . Each exemplary LIQAF block  202 ,  204 ,  206  has a pair of phase shifted waveforms, owing to the stacking effect discussed above. Each stage has another pair of outputs that are phase shifted from the previous stage due to the propagation delay of the LIQAF. The result is six distinct outputs  214 ,  216 ,  218 ,  220 ,  222 ,  224  because of the six intermediate outputs,  208 / 209 ,  210 / 211 ,  212 / 213  as illustrated in  FIG.  2 B . 
     The operation of this circuit of  FIG.  2 A  is as follows—first the initial condition of the feedback loop is V DD (HIGH STATE). Then, V s1,out2  and V s1,out1  will both react to this input by going low. From the previous discussion, it is known that V s1,out1  goes LOW before V s1,out2 , so that is the order in which that event will take place. After that, with little overlap the next stage will react to V s1,out2  and V s1,out1  because that is now the input to the next stage. Since, V s1,out2  and V s1,out1  are both low, V s2,out2  and V s2,out1  will both go high. V s2,out2  will go high before V s2,out1 . That will in turn drive feedback stage(s)  226  low and continue the oscillation. It is noted that each exemplary LIQAF stage  202 ,  204 ,  206  will react to its input before the next stage has a significant change. Assuming feedback is initialized to V DD , the order of excitation is as follows (shown in the bracketed region  228 ): V s1,out1 , V s1,out2 , V s2,out2 , V s2,out1 , V s3,out1 , and V s3,out2 . 
     In more general terms, the exemplary CMOS LIQAF ring oscillator can be expanded out an arbitrary number of outputs.  FIG.  3    illustrates an exemplary ring oscillator  300  with additional N series stages  302  and additional parallel LIQAF M stages  304 . It is noted that the number of columns, N ( 302 ), in  FIG.  3    are an odd number to maintain oscillation. In the CMOS inverter ring oscillator an odd number of phases are generated while the exemplary CMOS LIQAF ring oscillator can generate both an even and odd number of distinct phases. 
     Thus, the exemplary CMOS Laddered-Inverter Quantizer/Amplifier/Filter (LIQAF) ring oscillator can be increased by the number of stages and the number of outputs. Increasing the number of stages is a horizontal increase while increasing the number of outputs is a vertical increase. Up to 32 unique output waveforms are discussed herein, but this can be increased indefinitely vertically or horizontally (e.g., with an odd number of stages) for more phases if based on desired output frequency. 
     The exemplary ring oscillator can also be used as a digitally-controlled pulse-width modulation (PWM) generator if, for example, a multiplexer (MUX) is placed at the outputs. This mode of operation is suitable for usage in, for example, buck/boost converters. The duty cycle has a range of approximately 32% to 73% at approximately 1.2V. 
     Simulation Results 
     A comparison was desired between the exemplary CMOS inverter ring oscillator and the exemplary CMOS LIQAF ring oscillator. It was concluded that this would be done on the basis of the number of phases. Generally, the lowest number of phases that could be achieved between the two architectures that would be equal is nine phases. The exemplary nine phase CMOS inverter ring oscillator was created with nine CMOS inverter in series and the ninth inverter&#39;s output connected to the first inverter&#39;s input. The exemplary nine phase CMOS LIQAF ring oscillator was created with three output levels and three stages.  FIG.  4    illustrates an exemplary comparison of the oscillation frequency of the two topologies. Both topologies have a response that is almost linear with the exemplary LIQAF ring oscillator having a lower oscillation frequency due to the stacking effect.  FIG.  5    illustrates an exemplary power consumption comparison between the two topologies. Both topologies have dynamic power consumption as a generally dominant factor in the overall power consumption. In the case of the exemplary LIQAF, it has a lower oscillation frequency, thus lower power consumption. 
       FIG.  6    illustrates process, temperature, and exemplary voltage robustness performance of the power consumption.  FIG.  7    illustrates the process, temperature, and exemplary voltage robustness performance of the oscillation frequency, noting that the oscillation frequency is highly linear under any variation. In the figures, FF refers to the fast/fast process corner, TT is typical/typical or nominal process corner, and SS means the slow/slow process corner. 
     The exemplary CMOS LIQAF ring oscillator may be extended out in both dimensions—horizontal and vertical. As such, more levels can be created, resulting in more intermediate outputs and more stages. In the example, there are an odd number of stages. Illustrated in  FIG.  8    is exemplary power consumption and oscillation frequency of the exemplary 2, 4, 8, 16, and 32 level outputs, with three stage CMOS LIQAF ring oscillators. 
     The exemplary CMOS LIQAF ring oscillator can also function as, for example, a PWM generator if, for example, a MUX is placed at the output. For the sake of simulation, two series CMOS inverters (output buffer) were placed in parallel with the feedback of each stage to obtain a clean output. These exemplary plots illustrate operation of a PWM generator. In at least one implementation, the output buffers would, for example, be replaced with a MUX that would allow the specific input to be chosen with a digital word at the SEL lines. The duty cycle has an approximate exemplary maximum range of 33% to 76% in the exemplary 32 level CMOS LIQAF ring oscillator. In each simulation, the duty cycle is generally linearly spread across the output duty cycle range. 
       FIG.  9    illustrates an exemplary two (2) output pulse train having two (2) distinct outputs from a MUX with each level having expanded duty cycle from the previous level.  FIG.  10    illustrates an exemplary four (4) output pulse train having four (4) distinct outputs from a MUX with each level having expanded duty cycle from the previous level.  FIG.  11    illustrates an exemplary eight (8) output pulse train having eight (8) distinct outputs from a MUX with each level having expanded duty cycle from the previous level.  FIG.  12    illustrates an exemplary sixteen (16) output pulse train having sixteen (16) distinct outputs from a MUX with each level having expanded duty cycle from the previous level.  FIG.  13    illustrates an exemplary thirty-two (32) output pulse train having thirty-two (32) distinct outputs from a MUX with each level having expanded duty cycle from the previous level.  FIGS.  9 - 13    illustrate how, for increasing numbers of levels the cycle time increases while the range of the duty cycle correspondingly increases which increases the resolution. For Example,  FIG.  9    has two points between 60% and 40.5% while  FIG.  11    has 8 points between 71.1% and 33.3%. Applications that benefit from this increased range and resolution include Pulse Width Modulation(PWM) inside DC-DC converters. 
       FIG.  14    illustrates an exemplary Monte Carlo analysis performed on an exemplary circuit with the variable being the output frequency. The exemplary Monte Carlo results agree with measured simulation results of 1.88 GHz at 1.2V, TT. 
     At least an exemplary low-power, multi-phase ring oscillator circuit simulated in a 65 nm CMOS process has been presented herein. Compared to a CMOS inverter ring oscillator, the above-described exemplary CMOS LIQAF ring oscillator generally can generate more output phases at a lower power, and at the cost of lower oscillation frequency. Accordingly, the above-described exemplary CMOS LIQAF ring oscillator can be implemented on, for example, IoT edge devices, low power-low speed devices, and battery saving circuits to name just a few applications. The disclosed exemplary CMOS LIQAF ring oscillator circuit has robust performance across temperature and process variations. Furthermore, the disclosed exemplary CMOS LIQAF ring oscillator circuit has the possibility to be implemented in Time-to-Digital Converters, among many other applications. 
     At least one disclosed circuit is a voltage-controlled ring oscillator that provides several phase-shifted outputs based on the laddered inverter circuit. The disclosed circuit generally achieves the several phase-shifted waveforms by using a chain of laddered inverters. These inverters each have their propagation delay, which give a phase-shifted version of the same waveform. The circuit may also generate a PWM (pulse width modulation) output using a MUX. The circuit can be increased to have an arbitrary number of output waveforms. The power consumption can be in the nano-watt range, which allows this to be used in wearable devices, portable devices, and edge IoT devices. Further, other exemplary circuit implementations include clock generators, low power PWM generators, low power and high resolution time-to-digital converters, low power digital-to-time converters, and DC-DC converters to name a few. 
     According to the disclosure, a ring oscillator includes a first set of at least three laddered inverter quantizer (LIQAF) circuits connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input creates a pair of phase shifted waveforms in the first of the at least three LIQAF circuits that propagate sequentially through the stages of the at least three LIQAF circuits. Each stage has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage. 
     Also according to the disclosure, a method of constructing a ring oscillator includes connecting a first set of at least three laddered inverter quantizer (LIQAF) circuits in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and providing a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input creates a pair of phase shifted waveforms in the first of the at least three LIQAF circuits that propagate sequentially through the stages of the at least three LIQAF circuits. Each stage has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage. 
     A ring oscillator includes a structure having a two level CMOS laddered inverter quantizer (LIQAF) and three horizontal LIQAF blocks, the three horizontal LIQAF blocks in each of the two levels connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input in the three horizontal LIQAF blocks in each of the two levels creates a pair of phase shifted waveforms in the first of the three horizontal LIQAF blocks that propagate sequentially through the stages of the three LIQAF blocks. Each stage of the three horizontal LIQAF blocks in each of the two levels has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage. 
     With regard to the figures, processes, systems, methods, techniques, heuristics, etc. described herein, it should be understood that, although the steps of such processes, etc. have been described as occurring according to a certain ordered sequence, such processes could be practiced with the described steps performed in an order other than the order described herein. It further should be understood that certain steps could be performed simultaneously, that other steps could be added, or that certain steps described herein could be omitted. In other words, the descriptions of processes herein are provided for the purpose of illustrating certain embodiments, and should in no way be construed so as to limit the claims. 
     Accordingly, it is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments and applications other than the examples provided would be apparent upon reading the above description. The scope should be determined, not with reference to the above description or Abstract below, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. It is anticipated and intended that future developments will occur in the technologies discussed herein, and that the disclosed systems and methods will be incorporated into such future embodiments. In sum, it should be understood that the application is capable of modification and variation. 
     When introducing elements of various embodiments of the disclosed materials, the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Furthermore, any numerical examples in the following discussion are intended to be non-limiting, and thus additional numerical values, ranges, and percentages are within the scope of the disclosed embodiments. 
     While the preceding discussion is generally provided in the context of medical imaging, it should be appreciated that the present techniques are not limited to such medical contexts. The provision of examples and explanations in such a medical context is to facilitate explanation by providing instances of implementations and applications. The disclosed approaches may also be utilized in other contexts, such as the non-destructive inspection of manufactured parts or goods (i.e., quality control or quality review applications), and/or the non-invasive inspection or imaging techniques. 
     While the disclosed materials have been described in detail in connection with only a limited number of embodiments, it should be readily understood that the embodiments are not limited to such disclosed embodiments. Rather, that disclosed can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the disclosed materials. Additionally, while various embodiments have been described, it is to be understood that disclosed aspects may include only some of the described embodiments. Accordingly, that disclosed is not to be seen as limited by the foregoing description but is only limited by the scope of the appended claims.