Patent Publication Number: US-11640788-B2

Title: Stage and organic light emitting display device using the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/840,689 filed on Apr. 6, 2020, which is a continuation of U.S. application Ser. No. 16/429,228, filed on Jun. 3, 2019, now U.S. Pat. No. 10,614,754 issued on Apr. 7, 2020, which is a continuation of U.S. application Ser. No. 15/585,425 filed on May 3, 2017, now U.S. Pat. No. 10,311,781, issued on Jun. 4, 2019, which claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2016-0075527, filed on Jun. 17, 2016, in the Korean Intellectual Property Office, the disclosure of the above applications are incorporated by reference herein. 
    
    
     BACKGROUND 
     1. Field 
     One or more embodiments described herein relate to a stage and an organic light emitting display device including a stage. 
     2. Description of the Related Art 
     A variety of displays have been developed. Examples include liquid crystal displays and organic light emitting displays. An organic light emitting display generates an image based on light emitted from organic light emitting diodes (OLEDs). An OLED generates light based on a re-combination of electrons and holes in an emission layer. 
     One type of organic light emitting display includes a data driver for supplying data signals to data lines, a scan driver for supplying scan signals to scan lines, and an emission driver for supplying emission control signals to emission control lines. Pixels are connected to the data lines, the scan lines, and the emission control lines. 
     The pixels are selected when the scan signals are supplied to the scan lines. When selected, the pixels receive the data signals from the data lines. The pixels that receive the data signals emit light with predetermined brightness based on the data signals. Emission times of the pixels are controlled by the emission control signals supplied by the emission driver. 
     The emission driver includes stages respectively connected to the emission control lines. The stages generate the emission control signals based on clock signals and supply the generated emission control signals to the emission control lines. 
     Thus, the stages generate emission control signals to control emission times. When the emission control signals are unstable, the pixels may emit light components at undesired points of time. 
     SUMMARY 
     In accordance with one or more embodiments, a stage includes an output to supply a voltage of a first power source or a second power source to an output terminal based on voltages of a first node and a second node; an input to control voltages of a third node and a fourth node based on signals supplied to a first input terminal and a second input terminal; a first signal processor to control the voltage of the first node based on the voltage of the second node; a second signal processor, connected to a fifth node, to control the voltage of the first node based on a signal supplied to a third input terminal; a third signal processor to control the voltage of the fourth node based on the voltage of the third node and the signal supplied to the third input terminal; and a first stabilizer connected between the second signal processor and the input to control voltage drop widths of the third node and the fourth node. 
     The first power source may have a gate-off voltage and the second power source may have a gate-on voltage. The first input terminal may receive an output signal of a previous stage or a start pulse. The output signal of the previous stage or the start pulse may be supplied to the first input terminal overlaps a clock signal supplied to the second input terminal at least once. The second input terminal may receive a first clock signal, and the third input terminal may receive a second clock signal. The first clock signal and the second clock signal may have a same period, and the second clock signal may be shifted from the first clock signal by a half period. 
     The first stabilizer may include a first transistor connected between the third node and the fifth node and having a gate electrode connected to the second power source; and a second transistor connected between the second node and the fourth node and having a gate electrode connected to the second power source. 
     The input may include a seventh transistor connected between the first input terminal and the fourth node and having a gate electrode connected to the second input terminal; an eighth transistor connected between the third node and the second input terminal and having a gate electrode connected to the fourth node; and a ninth transistor connected between the third node and the second power source and having a gate electrode connected to the second input terminal. 
     The output may include a tenth transistor connected between the first power source and the output terminal and having a gate electrode connected to the first node; and an 11 th  transistor connected between the second power source and the output terminal and having a gate electrode connected to the second node. 
     The first signal processor may include a 12 th  transistor connected between the first power source and the first node and having a gate electrode connected to the second node; and a third capacitor connected between the first power source and the first node. 
     The second signal processor may include a first capacitor connected between the second node and third input terminal; a second capacitor having a first terminal connected to the fifth node; a fifth transistor connected between the second terminal of the second capacitor and the first node and having a gate electrode connected to the third input terminal; and a sixth transistor connected between the second terminal of the second capacitor and the third input terminal and having a gate electrode connected to the fifth node. 
     The third signal processor may include a 13 th  transistor and a 14 th  transistor serially connected between a first power source and the fourth node, a gate electrode of the 13 th  transistor may be connected to the third node, and a gate electrode of the 14 th  transistor may be connected to the third input terminal. 
     The stage may include a second stabilizer connected to the first power source, the first node, and the third input terminal to uniformly maintain the voltage of the second node in a period in which the voltage of the first power source is to be output to the output terminal. The second stabilizer may include a third transistor connected between the first power source and a sixth node and having a gate electrode connected to the first node; a fourth transistor connected between the sixth node and the third input terminal and having a gate electrode connected to the second node; and a first capacitor connected between the second node and the sixth node. 
     The second signal processor may include a second capacitor having a first terminal connected to the fifth node; a fifth transistor connected between the second terminal of the second capacitor and the first node and having a gate electrode connected to the third input terminal; and a sixth transistor connected between the second terminal of the first capacitor and the third input terminal and having a gate electrode connected to the fifth node. 
     In accordance with one or more other embodiments, an organic light emitting display device includes pixels connected to scan lines, data lines, and emission control lines; a scan driver to supply scan signals to the scan lines; a data driver to supply data signals to the data lines; and an emission driver including a plurality of stages to supply emission control signals to the emission control lines, wherein each of the stages includes: an output to supply a voltage of a first power source or a second power source to an output terminal based on voltages of a first node and a second node; an input to control voltages of a third node and a fourth node based on signals supplied to a first input terminal and a second input terminal; a first signal processor to control the voltage of the first node based on the voltage of the second node; a second signal processor, connected to a fifth node, to control the voltage of the first node based on a signal supplied to a third input terminal; a third signal processor to control the voltage of the fourth node based on the voltage of the third node and the signal supplied to the third input terminal; and a first stabilizer connected between the second signal processor and the input to control voltage drop widths of the third node and the fourth node. 
     The first power source may have a gate-off voltage, the second power source may have a gate-on voltage, and the voltage of the first power source supplied to the output terminal may be an emission control signal. The first input terminal may receive an output signal of a previous stage or a start pulse, the second input terminal of a jth (j is an odd number or an even number) stage may receive a first clock signal and the third input terminal of the jth stage is to receive a second clock signal, and the second input terminal of a (j+1)th stage may receive the second clock signal and the third input terminal of the (j+1)th stage is to receive the first clock signal. 
     The first stabilizer may include a first transistor connected between the third node and the fifth node and having a gate electrode connected to the second power source; and a second transistor connected between the second node and the fourth node and having a gate electrode connected to the second power source. 
     The organic light emitting display device may include a second stabilizer connected to the first power source, the first node, and the third input terminal to uniformly maintain the voltage of the second node in a period in which the voltage of the first power source is output to the output terminal, wherein the second stabilizer includes: a third transistor connected between the first power source and a sixth node and having a gate electrode connected to the first node; a fourth transistor connected between the sixth node and the third input terminal and having a gate electrode connected to the second node; and a first capacitor connected between the second node and the sixth node. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIG.  1    illustrates an embodiment of an organic light emitting display device; 
         FIG.  2    illustrates an embodiment of a pixel; 
         FIG.  3    illustrates an embodiment of an emission driver; 
         FIG.  4    illustrates an embodiment of a stage; 
         FIG.  5    illustrates an embodiment of a method for driving a stage; 
         FIG.  6    illustrates another embodiment of a stage; and 
         FIG.  7    illustrates another embodiment of a stage. 
     
    
    
     DETAILED DESCRIPTION 
     Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. The embodiments (or portions thereof) may be combined to form additional embodiments. 
     In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout. 
     When an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the another element or be indirectly connected or coupled to the another element with one or more intervening elements interposed therebetween. In addition, when an element is referred to as “including” a component, this indicates that the element may further include another component instead of excluding another component unless there is different disclosure. 
       FIG.  1    illustrates an embodiment of an organic light emitting display device which includes a scan driver  10 , a data driver  20 , an emission driver  30 , a pixel unit  40 , and a timing controller  60 . The timing controller  60  generates a data driving control signal DCS, a scan driving control signal SCS, and an emission driving control signal ECS based on synchronizing signals supplied from the outside. The data driving control signal DCS generated by the timing controller  60  is supplied to the data driver  20 . The scan driving control signal SCS generated by the timing controller  60  is supplied to the scan driver  10 . The emission driving control signal ECS generated by the timing controller  60  is supplied to the emission driver  30 . 
     The scan driving control signal SCS includes a start pulse and clock signals. The start pulse controls first timings of scan signals. The clock signals shift the start pulse. 
     The emission driving control signal ECS includes a start pulse and clock signals. The start pulse controls first timings of emission control signals. The clock signals shift the start pulse. 
     The data driving control signal DCS includes a source start pulse and clock signals. The source start pulse controls a sampling start point of time of data. The clock signals control a sampling operation. 
     The scan driver  10  receives the scan driving control signal SCS from the timing controller  60 . The scan driver  10  that receives the scan driving control signal SCS supplies the scan signals to scan lines S 1  through Sn. For example, the scan driver  10  may sequentially supply the scan signals to the scan lines S 1  through Sn. When the scan signals are sequentially supplied to the scan lines S 1  through Sn, pixels  50  are selected in units of horizontal lines. 
     The emission driver  30  receives the emission driving control signal ECS from the timing controller  60 . The emission driver  30  that receives the emission driving control signal ECS supplies the emission control signals to emission control lines E 1  through En. For example, the emission driver  30  may sequentially supply the emission control signals to the emission control lines E 1  through En. The emission control signals control emission times of the pixels  50 . For example, a specific pixel  50  that receives an emission control signal is set to be in a non-emission state in a period in which the emission control signal is supplied and may be set in an emission state in another period. 
     The emission control signals may have gate-off voltages (for example, high voltages) to turn off transistors in the pixels  50 . The scan signals may have gate-on voltages (for example, low voltages) to turn on the transistors in the pixels  50 . 
     The data driver  20  receives the data driving control signal DCS from the timing controller  60 . The data driver  20  that receives the data driving control signal DCS supplies data signals to data lines D 1  through Dm. The data signals supplied to the data lines D 1  through Dm are supplied to the pixels  50  selected by the scan signals. For this purpose, the data driver  20  may supply the data signals to the data lines D 1  through Dm in synchronization with the scan signals. 
     The pixel unit  40  includes the pixels  50  connected to the scan lines S 1  through Sn, the data lines D 1  through Dm, and the emission control lines E 1  through En. The pixel unit  40  receives a first driving power source ELVDD and a second driving power source ELVSS from an external source. 
     Each of the pixels  50  includes a driving transistor and an organic light emitting diode (OLED). The driving transistor controls an amount of current that flows from the first driving power source ELVDD to the second driving power source ELVSS, via the OLED, based on a data signal. 
     In  FIG.  1   , the n scan lines S 1  through Sn and the n emission control lines E 1  through En are illustrated. In another embodiment, no less than one dummy scan line and dummy emission control line may be additionally formed in the pixel unit  40  to correspond to circuit structures of the pixels  50 . 
       FIG.  2    illustrates an embodiment of a pixel, which, for example, may be representative of the pixels  50  in  FIG.  1   . For convenience sake, the pixel is one connected to the nth scan line Sn and the mth data line Dm. 
     Referring to  FIG.  2   , the pixel  50  includes an OLED a first transistor T 1  (a driving transistor), a second transistor T 2 , a third transistor T 3 , and a storage capacitor Cst. The OLED has an anode electrode connected to a second electrode of the third transistor T 3  and a cathode electrode connected to the second driving power source ELVSS. The OLED emits light with predetermined brightness based on an amount of current supplied from the first transistor T 1 . 
     The first transistor T 1  has a first electrode connected to the first driving power source ELVDD and a second electrode connected to a first electrode of the third transistor T 3 . A gate electrode of the first transistor T 1  is connected to a tenth node N 10 . The first transistor T 1  controls the amount of current supplied from the first driving power source ELVDD to the second driving power source ELVSS, via the third transistor T 3  and the OLED, based on the voltage of the tenth node N 10 . 
     The second transistor T 2  has a first electrode connected to the data line Dm and a second electrode connected to the tenth node N 10 . A gate electrode of the second transistor T 2  is connected to the scan line Sn. The second transistor T 2  is turned on when the scan signal is supplied to the scan line Sn and supplies the data signal from the data line Dm to the tenth node N 10 . 
     The third transistor T 3  has a first electrode connected to the second electrode of the first transistor T 1 , a second electrode connected to the anode electrode of the OLED, and a gate electrode connected to the emission control line En. The third transistor T 3  is turned off when the emission control signal is supplied to the emission control line En and is turned on when the emission control signal is not supplied. 
     When the third transistor T 3  is turned off, the first transistor t 1  and the OLED are electrically isolated so that the pixel  50  is set to be in a non-emission state. When the third transistor T 3  is turned on, the first transistor T 1  and the OLED are electrically connected so that the pixel  50  is set to be in an emission state. 
     The storage capacitor Cst is connected between the first driving power source ELVDD and the tenth node N 10 . The storage capacitor Cst charges the voltage of the tenth node N 10 . 
     In another embodiment, the pixel  50  may have a different configuration with a different number of transistors and/or capacitors and which is controlled in an emission period based on an emission control signal. 
       FIG.  3    illustrates an embodiment of the emission driver  30  of  FIG.  1   . Referring to  FIG.  3   , the emission driver  30  includes a plurality of stages ST 1  through ST 4 . Each of the stages ST 1  through ST 4  is connected to one of the emission control lines E 1  through E 4  and is driven based on clock signals CLK 1  and CLK 2 . The stages ST 1  through ST 4  may be implemented, for example, by the same circuit. 
     Each of the stages ST 1  through ST 4  includes a first input terminal  101 , a second input terminal  102 , a third input terminal  103 , and an output terminal  104 . The first input terminal  101  receives an output signal (that is, an emission control signal) of a previous stage or a start pulse SSP. For example, the first input terminal  101  of the first stage ST 1  receives the start pulse SSP and the first input terminals  101  of the remaining stages ST 2  through ST 4  may receive output signals of previous stages. 
     A second input terminal  102  of a jth (j is an odd number or an even number) stage STj receives the first clock signal CLK 1  and the third input terminal  103  of the jth stage STj receives the second clock signal CLK 2 . A second input terminal  102  of a (j+i)th stage STj+1 receives the second clock signal CLK 2  and the third input terminal  103  of the (j+i)th stage STj+1 receives the first clock signal CLK 1 . 
     The first clock signal CLK 1  and the second clock signal CLK 2  have the same period and do not have overlapping phases. For example, the second clock signal CLK 2  may be shifted from the first clock signal CLK 1 , for example, by a half period. 
     In addition, the stages ST 1  through ST 4  receive a first power source VDD and a second power source VSS. The first power source VDD may be set to a gate-off voltage. The second power source VSS may be set to a gate-on voltage. The first power source VDD supplied to the output terminal  104  may serve as an emission control signal. 
       FIG.  4    illustrates an embodiment of the stage of  FIG.  3   . In  FIG.  4   , for convenience sake, the first stage ST 1  and the second stage ST 2  are illustrated. 
     Referring to  FIG.  4   , the first stage ST 1  includes an input unit  210 , an output unit  220 , a first signal processing unit  230 , a second signal processing unit  240 , a third signal processing unit  250 , and a first stabilizing unit  260 . The output unit  220  supplies a voltage of the first power source VDD or the second power source VSS to the output terminal  104  based on voltages of a first node N 1  and a second node N 2 . For this purpose, the output unit  220  includes a tenth transistor M 10  and an 11 th  transistor M 11 . 
     The tenth transistor M 10  is connected between the first power source VDD and the output terminal  104 . A gate electrode of the tenth transistor M 10  is connected to the first node N 1 . The tenth transistor M 10  is turned on or off based on the voltage of the first node N 1 . The voltage of the first power source VDD supplied to the output terminal  104  when the tenth transistor M 10  is turned on may serve as the emission control signal of the first emission control line E 1 . 
     The 11 th  transistor M 11  is connected between the output terminal  104  and the second power source VSS. A gate electrode of the 11 th  transistor M 11  is connected to the second node N 2 . The 11 th  transistor M 11  is turned on or off based on the voltage of the second node N 2 . 
     The input unit  210  controls voltages of a third node N 3  and a fourth node N 4  based on the signals supplied to the first input terminal  101  and the second input terminal  102 . The input unit  210  includes seventh through ninth transistors M 7  through M 9 . 
     The seventh transistor M 7  is connected between the first input terminal  101  and the fourth node N 4 . A gate electrode of the seventh transistor M 7  is connected to the second input terminal  102 . The seventh transistor M 7  is turned on when the first clock signal CLK 1  is supplied to the second input terminal  102  and electrically connects the first input terminal  101  and the fourth node N 4 . 
     The eighth transistor M 8  is connected between the third node N 3  and the second input terminal  102 . A gate electrode of the eighth transistor M 8  is connected to the fourth node N 4 . The eighth transistor M 8  is turned on or off based on the voltage of the fourth node N 4 . 
     The ninth transistor M 9  is connected between the third node N 3  and the second power source VSS. A gate electrode of the ninth transistor M 9  is connected to the second input terminal  102 . The ninth transistor M 9  is turned on when the first clock signal CLK 1  is supplied to the second input terminal  102  and supplies the voltage of the second power source VSS to the third node N 3 . 
     The first signal processing unit  230  controls the voltage of the first node N 1  based on the voltage of the second node N 2 . For this purpose, the first signal processing unit  230  includes a 12 th  transistor M 12  and a third capacitor C 3 . 
     The 12 th  transistor M 12  is connected between the first power source VDD and the first node N 1 . A gate electrode of the 12 th  transistor M 12  is connected to the second node N 2 . The 12 th  transistor M 12  is turned on or off based on the voltage of the second node N 2 . 
     The third capacitor C 3  is connected between the first power source VDD and the first node N 1 . The third capacitor C 3  charges the voltage applied to the first node N. In addition, the third capacitor C 3  stably maintains the voltage of the first node N 1 . 
     The second signal processing unit  240  is connected to a fifth node N 5  and controls the voltage of the first node N 1  based on a signal supplied to the third input terminal  103 . For this purpose, the second signal processing unit  240  includes a fifth transistor M 5 , a sixth transistor M 6 , a first capacitor C 1 , and a second capacitor C 2 . 
     The first capacitor C 1  is connected between the second node N 2  and the third input terminal  103 . The first capacitor C 1  charges the voltage applied to the second node N 2 . In addition, the first capacitor C 1  controls the voltage of the second node N 2  based on the second clock signal CLK 2  supplied to the third input terminal  103 . 
     The second capacitor C 2  has a first terminal connected to the fifth node N 5  and a second terminal connected to the fifth transistor M 5 . 
     The fifth transistor M 5  is connected between a second terminal of the second capacitor C 2  and the first node N 1 . A gate electrode of the fifth transistor M 5  is connected to the third input terminal  103 . The fifth transistor M 5  is turned on when the second clock signal CLK 2  is supplied to the third input terminal  103  and electrically connects the second terminal of the second capacitor C 2  and the first node N 1 . 
     The sixth transistor M 6  is connected between the second terminal of the second capacitor C 2  and the third input terminal  103 . A gate electrode of the sixth transistor M 6  is connected to the fifth node N 5 . The sixth transistor M 6  is turned on or off based on a voltage of the fifth node N 5 . 
     The third signal processing unit  250  controls the voltage of the fourth node N 4  based on the voltage of the third node N 3  and the signal supplied to the third input terminal  103 . For this purpose, the third signal processing unit  250  includes a 13 th  transistor M 13  and a 14 th  transistor M 14 . 
     The 13 th  transistor M 13  and the 14 th  transistor M 14  are serially connected between the first power source VDD and the fourth node N 4 . A gate electrode of the 13 th  transistor M 13  is connected to the third node N 3 . The 13 th  transistor M 13  is turned on or off based on the voltage of the third node N 3 . In addition, a gate electrode of the 14 th  transistor M 14  is connected to the third input terminal  103 . The 14 th  transistor M 14  is turned on when the second clock signal CLK 2  is supplied to the third input terminal  103 . 
     The first stabilizing unit  260  is connected between the second signal processing unit  240  and the input unit  210 . The first stabilizing unit  260  limits voltage drop widths of the third node N 3  and the fourth node N 4 . For this purpose, the first stabilizing unit  260  includes a first transistor M 1  and a second transistor M 2 . 
     The first transistor M 1  is connected between the third node N 3  and the fifth node N 5 . A gate electrode of the first transistor M 1  is connected to the second power source VSS. The first transistor M 1  is set to be in a turn-on state. 
     The second transistor M 2  is connected between the second node N 2  and the fourth node N 4 . A gate electrode of the second transistor M 2  is connected to the second power source VSS. The second transistor M 2  is set to be in a turn-on state. 
     The second stage ST 2  may have the same configuration as the first stage ST 1  excluding signals supplied to first input terminal  101  through third input terminal  103 . 
       FIG.  5    illustrates an embodiment of a waveform diagram of a method for driving the stage of  FIG.  4   . In  FIG.  5   , for convenience sake, operation processes will be described using the first stage ST. 
     Referring to  FIG.  5   , the first clock signal CLK 1  and the second clock signal CLK 2  have periods of 2 horizontal periods  2 H and are supplied in different horizontal periods. The second clock signal CLK 2  is shifted from the first clock signal CLK 1 , for example, by a half period (that is, a 1 horizontal period  1 H). 
     When the start pulse SSP is supplied, the first input terminal  101  is set to have the voltage of the first power source VDD. When the start pulse SSP is not supplied, the first input terminal  101  may be set to have the voltage of the second power source VSS. 
     When the clock signals CLK 1  and CLK 2  are supplied, the second input terminal  102  and the third input terminal  103  are set to have the voltage of the second power source VSS. When the clock signals CLK 1  and CLK 2  are not supplied, the second input terminal  102  and the third input terminal  103  may be set to have the voltage of the first power source VDD. 
     In addition, the start pulse SSP supplied to the first input terminal  101  overlaps the first clock signal CLK 1  supplied to the second input terminal  102  at least once. The start pulse SSP may be supplied in a period with a greater width than the first clock signal CLK 1 , for example, in a four horizontal period  4 H. The first emission control signal supplied to the first input terminal  101  of the second stage ST 2  overlaps the second clock signal CLK 2  supplied to the second input terminal  102  of the second stage ST 2  at least once. 
     In describing the operation processes, first, the first clock signal CLK 1  is supplied to the second input terminal  102  at a first point of time t 1 . When the first clock signal CLK 1  is supplied to the second input terminal  102 , the seventh transistor M 7  and the ninth transistor M 9  are turned on. 
     When the seventh transistor M 7  is turned on, the first input terminal  101  and the fourth node N 4  are electrically connected. Since the second transistor M 2  maintains the turn-on state, the first input terminal  101  is electrically connected to the second node N 2  via the fourth node N 4 . At this time, the start pulse SSP is not supplied to the first input terminal  101  at the first point of time t 1 , so that a low voltage (for example, VSS) is supplied to the fourth node N 4  and the second node N 2 . 
     When the low voltage is supplied to the second node N 2  and the fourth node N 4 , the eighth transistor M 8 , the 11 th  transistor M 11 , and the 12 th  transistor M 12  are turned on. When the 12 th  transistor M 12  is turned on, the voltage of the first power source VDD is supplied to the first node N 1  so that the tenth transistor M 10  is turned off. At this time, a voltage corresponding to turning-off of the tenth transistor M 10  is charged in the third capacitor C 3 . 
     When the 11 th  transistor M 11  is turned on, the voltage of the second power source VSS is supplied to the output terminal  104 . Therefore, at the first point of time t 1 , the emission control signal is not supplied to the first emission control line E 1 . 
     When the eighth transistor M 8  is turned on, the first clock signal CLK 1  is supplied to the third node N 3 . Since the first transistor M 1  maintains the turn-on state, the first clock signal CLK 1  is supplied to the fifth node N 5  via the third node N 3 . 
     When the ninth transistor M 9  is turned on, the voltage of the second power source VSS is supplied to the third node N 3  and the fifth node N 5 . The first clock signal CLK 1  is set to have the voltage of the second power source VSS, so that the third node N 3  and the fifth node N 5  are stably set to have the voltage of second power source VSS. 
     When the third node N 3  and the fifth node N 5  are set to have the voltage of the second power source VSS, the 13 th  transistor M 13  and the sixth transistor M 6  are turned on. When the sixth transistor M 6  is turned on, a high voltage (for example, VDD) from the third input terminal  103  is supplied to the second terminal of the second capacitor C 2 . At this time, since the fifth transistor M 5  is set to be in a turn-off state, the first node N 1  maintains the voltage of the first power source VDD regardless of the voltage of the fifth node N 5  and a voltage of the second terminal of the second capacitor C 2 . 
     When the 13 th  transistor M 13  is turned on, the voltage of the first power source VDD is supplied to the 14 th  transistor M 14 . At this time, the 14 th  transistor M 14  is set to be in a turn-off state so that the fourth node N 4  maintains a low voltage. 
     At a second point of time t 2 , supply of the first clock signal CLK 1  to the second input terminal  102  is stopped. When the supply of the first clock signal CLK 1  is stopped, the seventh transistor M 7  and the ninth transistor M 9  are turned off. At this time, the second node N 2  and the first node N 1  maintain voltages in a previous period by the first capacitor C 1  and the third capacitor C 3 . 
     When the second node N 2  maintains a low voltage, the eighth transistor M 8 , the 11 th  transistor M 11 , and the 12 th  transistor m 12  are turned on. When the eighth transistor M 8  is turned on, a high voltage from the second input terminal  102  is supplied to the third node N 3  and the fifth node N 5 . Then, the 13 th  transistor M 13  and the sixth transistor M 6  are set to be in turn-off states. 
     When the 12 th  transistor M 12  is turned on, the voltage of the first power source VDD is supplied to the first node N 1  so that the tenth transistor M 10  maintains a turn-off state. When the 11 th  transistor M 11  is turned on, the output terminal  104  receives the voltage of the second power source VSS. 
     At a third point of time t 3 , the second clock signal CLK 2  is supplied to the third input terminal  103 . When the second clock signal CLK 2  is supplied to the third input terminal  103 , the 14 th  transistor M 14  and the fifth transistor M 5  are turned on. When the fifth transistor M 5  is turned on, the second terminal of the second capacitor C 2  and the first node N 1  are electrically connected. At this time, the first node N 1  maintains the voltage of the first power source VDD. 
     When the 14 th  transistor M 14  is turned on, a second electrode of the 13 th  transistor M 13  and the second node N 2  are electrically connected. At this time, since the 13 th  transistor M 13  is set to be in a turn-off state, the voltage of the first power source VDD is not supplied to the fourth node N 4  and the second node N 2 . 
     In addition, when the second clock signal CLK 2  is supplied to the third input terminal  103 , the voltage of the second node N 2  is reduced to a voltage lower than the voltage of the second power source VSS by coupling of the first capacitor C 1 . Then, a voltage applied to the 11 th  transistor M 11  and the gate electrode of the 12 th  transistor M 12  is reduced to a voltage lower than the voltage of the second power source VSS, so that driving characteristics of the transistors may be improved. 
     The fourth node N 4  maintains the voltage of the second power source VSS regardless of the drop in voltage of the second node N 2  by the second transistor M 2 . For example, since the voltage of the second power source VSS is applied to the gate electrode of the second transistor M 2 , the fourth node N 4  maintains the voltage of the second power source VSS regardless of the drop in voltage of the second node N 2 . In this case, a voltage difference between the first electrode and the second electrode (e.g., between a source electrode and a drain electrode of the seventh transistor M 7 ) is reduced or minimized. Thus, it is possible to prevent the characteristics of the seventh transistor M 7  from changing. 
     At a fourth point of time t 4 , the start pulse SSP is supplied to the first input terminal  101  and the first clock signal CLK 1  is supplied to the second input terminal  102 . When the first clock signal CLK 1  is supplied to the second input terminal  102 , the seventh transistor M 7  and the ninth transistor M 9  are turned on. When the seventh transistor M 7  is turned on, the first input terminal  101  is electrically connected to the fourth node N 4  and the second node N 2 . Then, the fourth node N 4  and the second node N 2  are set to have high voltages by the start pulse SSP supplied to the second input terminal  102 . When the fourth node N 4  and the second node N 2  are set to have the high voltages, the eighth transistor M 8 , the 11 th  transistor M 11 , and the 12 th  transistor M 12  are turned off. 
     When the ninth transistor M 9  is turned on, the voltage of the second power source VSS is supplied to the third node N 3  and the fifth node N 5 . When the voltage of the second power source VSS is supplied to the third node N 3  and the fifth node N 5 , the 13 th  transistor M 13  and the sixth transistor M 6  are turned on. At this time, although the 13 th  transistor M 13  is turned on, since the 14 th  transistor M 14  is set to be in a turn-off state, the voltage of the fourth node N 4  does not change. 
     When the sixth transistor M 6  is turned on, the second terminal of the second capacitor C 2  and the third input terminal  103  are electrically connected. At this time, since the fifth transistor M 5  is set to be in a turn-off state, the first node N 1  maintains a high voltage. 
     At a fifth point of time t 5 , the second clock signal CLK 2  is supplied to the second input terminal  103 . When the second clock signal CLK 2  is supplied to the second input terminal  103 , the 14 th  transistor M 14  and the fifth transistor M 5  are turned on. Since the third node N 3  and the fifth node N 5  are set to have the voltage of the second power source VSS at the fifth point of time t 5 , the 13 th  transistor M 13  and the sixth transistor M 6  maintain turn-on states. 
     When the fifth transistor M 5  and the sixth transistor M 6  are turned on, the second clock signal CLK 2  is supplied to the first node N 1 . When the second clock signal CLK 2  is supplied to the first node N 1 , the tenth transistor M 10  is turned on. When the tenth transistor M 10  is turned on, the voltage of the first power source VDD is supplied to the output terminal  104 . The voltage of the first power source VDD supplied to the output terminal  104  is supplied to the first emission control line E 1  as the emission control signal. 
     When the 13 th  transistor M 13  and the 14 th  transistor M 14  are turned on, the voltage of the second power source VDD is supplied to the fourth node N 4  and the second node N 2 . Then, the eighth transistor M 8  and the 11 th  transistor M 11  stably maintain turn-off states. 
     When the second clock signal CLK 2  is supplied to the second terminal of the second capacitor C 2 , the voltage of the fifth node N 5  is reduced to a voltage lower than the voltage of the second power source VSS by coupling of the second capacitor C 2 . Then, a voltage applied to the gate electrode of the sixth transistor M 6  is reduced to a voltage lower than the voltage of the second power source VSS, As a result, the driving characteristics of the sixth transistor M 6  may be improved. 
     In addition, the voltage of the third node N 3  maintains the voltage of the second power source VSS by the first transistor M 1  regardless of the voltage of the fifth node N 5 . For example, since the voltage of the second power source VSS is applied to the gate electrode of the first transistor M 1 , regardless of the drop in voltage of the fifth node N 5 , the third node N 3  maintains the voltage of the second power source VSS. In this case, a voltage difference between a source electrode and a drain electrode of the eighth transistor M 8  is reduced or minimized, and thus it is possible to prevent characteristics of the eighth transistor M 8  from changing. 
     At a sixth point of time t 6 , the first clock signal CLK 1  is supplied to the second input terminal  102 . When the first clock signal CLK 1  is supplied to the second input terminal  102 , the seventh transistor M 7  and the ninth transistor M 9  are turned on. When the seventh transistor M 7  is turned on, the fourth node N 4  and the second node N 2  are electrically connected to the first input terminal  101  so that a low voltage from the first input terminal  101  is supplied to the fourth node N 4  and the second node N 2 . When the fourth node N 4  and the second node N 2  are set to have low voltages, the eighth transistor M 8 , the 11 th  transistor M 11 , and the 12 th  transistor M 12  are turned on. 
     When the eighth transistor M 8  is turned on, the first clock signal CLK 1  is supplied to the third node N 3  and the fifth node N 5 . When the 12 th  transistor M 12  is turned on, the voltage of the first power source VDD is supplied to the first node N 1  so that the tenth transistor M 10  is turned off. When the 11 th  transistor M 11  is turned on, the voltage of the second power source VSS is supplied to the output terminal  104 . The voltage of the second power source VSS supplied to the output terminal  104  is supplied to the first emission control line E 1 . As a result, supply of the emission control signal to the first emission control line E 1  is stopped. 
     The second stage ST 2  that receives the emission control signal from the output terminal  104  of the first stage ST 1  supplies the emission control signal to the second emission control line E 2  while repeating the above-described processes. Thus, the emission stages ST according to the present embodiment may sequentially supply the emission control signals to the emission control lines E 1  through En while repeating the above-described processes. 
       FIG.  6    illustrates another embodiment of the stage of  FIG.  3   . Referring to  FIG.  6   , a first stage ST 1 ′ includes an input unit  210 ′, the output unit  220 , the first signal processing unit  230 , the second signal processing unit  240 , the third signal processing unit  250 , and the first stabilizing unit  260 . 
     The input unit  210 ′ controls the voltages of the third node N 3  and the fourth node N 4  based on the signals supplied to the first input terminal  101  and the second input terminal  102 . For this purpose, the input unit  210 ′ includes seventh through ninth transistors M 7  through M 9 . 
     The seventh transistor M 7  is connected between the first input terminal  101  and the fourth node N 4 . A gate electrode of the seventh transistor M 7  is connected to the second input terminal  102 . The seventh transistor M 7  is turned on when the first clock signal CLK 1  is supplied to the second input terminal  102  and electrically connects the first input terminal  101  and the fourth node N 4 . 
     The eighth transistors M 8 _ 1  and M 8 _ 2  are serially connected between the third node N 3  and the second input terminal  102 . Gate electrodes of the eighth transistors M 8 _ 1  and M 8 _ 2  are connected to the fourth node N 4 . The eighth transistors M 8 _ 1  and M 8 _ 2  are turned on or off based on the voltage of the fourth node N 4 . 
     The ninth transistor M 9  is connected between the third node N 3  and the second power source VSS. A gate electrode of the ninth transistor M 9  is connected to the second input terminal  102 . The ninth transistor M 9  is turned on when the first clock signal CLK 1  is supplied to the second input terminal  102  and supplies the voltage of the second power source VSS to the third node N 3 . 
     According to another embodiment, the configuration of the first stage ST 1 ′ is the same as in  FIG.  4    except that the eighth transistors M 8 _ 1  and M 8 _ 2  are formed in order to reduce or minimize leakage current. The configuration of the second stage ST 2 ′ may be the same as the first stage ST 1 ′ except the signals supplied to the input terminals  101 ,  102 , and  103 . 
       FIG.  7    illustrates another embodiment of the stage of  FIG.  3   . Referring to  FIG.  7   , the first stage ST 1 ″ includes the input unit  210 , the output unit  220 , the first signal processing unit  230 , a second signal processing unit  240 ′, the third signal processing unit  250 , the first stabilizing unit  260 , and a second stabilizing unit  270 . 
     The second stabilizing unit  270  is connected to the first power source VDD, the first node N 1 , and the third input terminal  103 . The second stabilizing unit  270  uniformly maintains the voltage of the second node N 2  in a period in which the emission control signal is supplied to the output terminal  104 . The second stabilizing unit  270  includes a third transistor M 3 , a fourth transistor M 4 , and a first capacitor C 1 ′. 
     The third transistor M 3  is connected between the first power source VDD and a sixth node N 6  and has a gate electrode connected to the first node N 1 . The third transistor M 3  is turned on or off based on the voltage of the first node N 1 . 
     The fourth transistor M 4  is connected between the sixth node N 6  and the third input terminal  103  and has a gate electrode connected to the second node N 2 . The fourth transistor M 4  is turned on or off based on the voltage of the second node N 2 . 
     The first capacitor C 1 ′ is connected between the sixth node N 6  and the second node N 2 . 
     The second signal processing unit  240 ′ is connected to the fifth node N 5  and controls the voltage of the first node N 1  based on the signal supplied to the third input terminal. The second signal processing unit  240 ′ includes a fifth transistor M 5 , a sixth transistor M 6 , and a second capacitor C 2 . 
     The second capacitor C 2  has a first terminal connected to the fifth node N 5  and a second terminal connected to the fifth transistor M 5 . 
     The fifth transistor M 5  is connected between the second terminal of the second capacitor C 2  and the first node N 1 . A gate electrode of the fifth transistor M 5  is connected to the third input terminal  103 . The fifth transistor M 5  is turned on when the second clock signal CLK 2  is supplied to the third input terminal  103  and electrically connects the second terminal of the second capacitor C 2  and the first node N 1 . 
     The sixth transistor M 6  is connected between the second terminal of the second capacitor C 2  and the third input terminal. A gate electrode of the sixth transistor M 6  is connected to the fifth node N 5 . The sixth transistor M 6  is turned on or off based on the voltage of the fifth node N 5 . 
     The second signal processing unit  240 ′ may have the same configuration as  FIG.  4    except for the first capacitor C 1 . 
     The stage according to the present embodiment may be driven, for example, by the driving waveform of  FIG.  5   . 
     The fourth transistor M 4  is turned on based on the voltage of the second node N 2 . For example, the fourth transistor M 4  maintains a turn-on state in a period in which the second node N 2  is set to have a low voltage. The fourth transistor M 4  may be in a turn-on state before the fourth point of time t 4  of  FIG.  5    and after the sixth point of time t 6  of  FIG.  5   . 
     When the fourth transistor M 4  is in the turn-on state, and when the second clock signal CLK 2  is supplied, the voltage of the second node N 2  is reduced to a voltage lower than the voltage of the second power source VSS by coupling of the first capacitor C 1 ′ (at the third point of time t 3 ). 
     On the other hand, the third transistor M 3  is turned on based on the voltage of the first node N 1 . For example, the third transistor M 3  maintains a turn-on state in a period in which the first node N 1  is set to have a low voltage. The third transistor M 3  maintains the turn-on state at the fifth point of time t 5  and the sixth point of time t 6  of  FIG.  5   . 
     When the third transistor M 3  is turned on, the voltage of the first power source VDD is supplied to the sixth node N 6 . For example, in a period in which the emission control signal is supplied to the emission control line E 1 , the sixth node N 6  maintains the voltage of the first power source VDD. When the sixth node N 6  maintains the voltage of the first power source VDD, the second node N 2  may stably maintain a high voltage. 
     In the stage of  FIG.  4   , the first capacitor C 1  receives the second clock signal CLK 2  supplied to the third input terminal  103  so that the voltage of the second node N 2  is changed by the second clock signal CLK 2 . In a period between the fifth point of time t 5  and the sixth point of time t 6 , the voltage of the second node N 2  is changed by the second clock signal CLK 2 . As a result, operation reliability may deteriorate. 
     In the stage of  FIG.  6   , at the point of time t 5  and the sixth point of time t 6  of  FIG.  5   , a voltage of a first terminal of the first capacitor C 1 ′ is maintained as the voltage of the first power source VDD. Thus, the voltage of the second node N 2  may be stably maintained. 
     The methods, processes, and/or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods herein. 
     The drivers, controllers, and other processing features described herein may be implemented in logic which, for example, may include hardware, software, or both. When implemented at least partially in hardware, the drivers, controllers, and other processing features may be, for example, any one of a variety of integrated circuits including but not limited to an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or another type of processing or control circuit. 
     When implemented in at least partially in software, the drivers, controllers, and other processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.