Patent Publication Number: US-6670939-B2

Title: Single-ended high-voltage level shifter for a TFT-LCD gate driver

Description:
FIELD OF THE INVENTION 
     The invention relates to a single-ended high-voltage level shifter for a TFT-LCD gate driver, and more particularly, to a single-ended high-voltage level shifter that minimizes the chip area of a TFT-LCD gate driver. 
     BACKGROUND OF THE INVENTION 
     A functional block diagram of a typical TFT-LCD gate driver with 256 output channels for XGA/SXGA display systems is shown in FIG.  1 . The gate driver includes a bidirection shift control register, an enable control, a level shifter and an output buffer. The bidirection shift control register, triggered synchronously by the rising edge of a shift clock (SCLK), is used to continuously shift the start pulses of the right data input/output (DIOR) or the left data input/output (DIOL) according to the right/left shift control signal (RL). Each output channel of the gate driver is gated asynchronously by the global-on control signal (XON) and the output-enabled signal (OE). Then the voltage level of each output channel of the gate driver is translated to drive the output buffer of the next stage. 
     A conventional implementation of the level shifter  21  and the output buffer  22  is shown in FIG.  2 . The level shifter  21  includes two high-voltage PMOS transistors M 1 , M 3  and two high-voltage NMOS transistors M 2 , M 4 . Herein, the high-voltage MOS transistor is different from the low-voltage MOS transistor in that the high-voltage MOS transistor withstands higher drain-to-source or gate-to-source voltage than that of the low-voltage MOS transistor, for example: 40V. The threshold voltage V T  of the high-voltage MOS transistor is also higher than the low-voltage MOS transistor. For example, the threshold voltage of the high-voltage PMOS transistor is 1.7V, and the threshold voltage of the high-voltage NMOS transistor is 2.7V. The input signal IN is used to drive the transistor M 2 , and the complementary input signal INB is used to drive the transistor M 4 . 
     When the gate of the transistor M 2  receives an input low signal V SS , the low-voltage power supply, for example: −5V. The transistor M 2  is OFF and the transistor M 4  is ON. The voltage of node B is pulled to V SS , and the transistor M 1  is ON. The voltage of node A is then pulled to the high-voltage power supply V DD , for example: 25V˜35V, then M 3  is OFF. As a result, the transistor M 6  is ON and the voltage of the output signal OUT is V SS . When the input signal IN applied at the gate of the transistor M 2  is changed from low to high, for example: −5V+3.3V=−1.7V, the transistor M 2  is ON, and the transistor M 4  is OFF. The voltage of node A is pulled to V SS  and the transistor M 3  is ON. The voltage of node B is pulled to V DD . Then the transistor M 1  is OFF. Because the voltage of node A is V SS , the transistor M 5  is ON and the voltage of the output signal OUT is pulled to V DD . 
     The advantage of this conventional circuitry is that there is no static power consumption in the level shifter  21 . However, the sizes of the high-voltage transistors M 2  and M 4  have to be designed much larger than those of the high-voltage transistors M 1  and M 3  as the high level of the input signal does not differ much from the threshold voltage of the high-voltage transistors M 2  and M 4 . The reason is that when the high-voltage transistor M 2  (or M 4 ) is ON, the voltage of node A (or B) should be pulled from the high-voltage power supply V DD  to the low-voltage power supply V SS  in a short period of time. Thus the sizes of the high-voltage transistors M 2  and M 4  have to be designed large enough to sustain the large current. In addition, the high level of the input signal is necessarily higher than the threshold voltage of the high-voltage transistors M 2  and M 4  (typical of 2.7V) in order to drive the level shifter shown in FIG.  2 . 
     FIG. 3 shows a circuit diagram having the level shifter  31  and the output buffer  32  connected together according to another prior art wherein the circuitry of the output buffer  32  is identical to that of the output buffer  22  shown in FIG.  2 . The low-voltage transistors M 7  and M 8  receive the input signal IN and the complementary input signal INB respectively. The source of the high-voltage transistor M 2  is connected to the drain of the low-voltage transistor M 7  and the source of the high-voltage transistor M 4  is connected to the drain of the low-voltage transistors M 8 . Both the gates of M 2  and M 4  are connected to a reference voltage V RL  to limit the voltage of the drains of M 7  and M 8  not to exceed V RL -V T , for example: 5V−2.7V=2.3V. This is to prevent M 7  (or M 8 ) from breakdown when the voltage of drain-to-source of M 7  (or M 8 ) is excessively high. The advantage of this conventional circuitry is that the sizes of the high-voltage transistors M 2  and M 4  are not necessarily designed much larger than those of the high-voltage transistors M 1  and M 3  like the circuitry shown in FIG.  2 . This is due to the employment of the low-voltage transistors M 7  and M 8 . As a result, the chip area of the level shifter  31  is smaller than that of the level shifter  21 . 
     Although the level shifter  31  occupies smaller chip area than the level shifter  21 , the level shifter  31  still uses 4 high-voltage transistors that occupy significant chip area. Therefore, this plays an important role in determining the cost of the gate driver IC. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing problems, the object of the invention is to provide a single-ended high-voltage level shifter for the TFT-LCD gate driver. Employing only two high-voltage transistors minimizes the chip area of the single-ended high-voltage level shifter. Implementing partial logic control circuitry in the level shifter further minifies the chip area of the TFT-LCD gate driver. Therefore, the total cost of the gate driver IC is significantly reduced. 
     The single-ended high-voltage level shifter for the TFT-LCD gate driver comprises (a) a high-voltage power supply and a low-voltage power supply; (b) a first low-voltage NMOS transistor, having its gate connected to an input signal and its source connected to the low-voltage power supply; (c) a high-voltage NMOS transistor, having its gate received a first reference voltage whose level is between the input-signal level and the high-voltage power supply, and having its source connected to the drain of the first low-voltage NMOS transistor; (d) a first high-voltage PMOS transistor, having its gate received a second reference voltage that keeps the first high-voltage PMOS transistor in ON-state and is at a level higher than the first reference voltage, and having its source connected to the high-voltage power supply, and having its drain connected to the drain of the high-voltage NMOS transistor and employed as the output end connected to an output driver of the next stage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a functional block diagram of a typical TFT-LCD gate driver with 256 output channels for XGA/SXGA display systems. 
     FIG. 2 shows an implementation of the level shifter and the output buffer according to the prior art. 
     FIG. 3 shows another implementation of the level shifter and the output buffer according to the prior art. 
     FIG. 4 shows a level shifter of the invention and an output buffer. 
     FIG. 5 shows a level shifter of the invention with partial logic control circuitry and an output buffer. 
     FIG. 6 shows the simplified circuitry of FIG.  5 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 4, the single-ended high-voltage level shifter for the TFT-LCD gate driver includes a high-voltage power supply V DD  and a low-voltage power supply V SS , a high-voltage PMOS transistor M 1 , a high-voltage NMOS transistor M 2 , and a low-voltage NMOS transistor M 7 . The high-voltage power supply V DD  is applied at the source of M 1 . The low-voltage power supply V SS  is applied at the source of M 7 . A first reference voltage V RL , whose level is between the input-signal level and the high-voltage power supply, is applied at the gate of M 2 . This is to limit the voltage of the drain of M 7  to be lower than V RL -V T  in order to prevent M 7  from breakdown. A second reference voltage V RH , whose level is higher than that of the first reference voltage, is applied at the gate of M 1  to ensure that M 1  is under operating state. For example: V DD =30V, V SS =−5V, V RL =5V, V T =2.7V, V RH =24V. The level of the aboriginal high signal V LH  is translated to V AA  and the level of the aboriginal low signal V LL  is translated to V SS , wherein V AA =V SS +(3.3V˜5.5V). 
     When an input high signal V AA  is applied at the gate of M 7 , M 7  is ON. The voltage of node B is pulled to V SS , M 2  is ON. The voltage of node A is pulled to V SS . M 5  is ON and M 6  is OFF. Then the voltage of the output signal OUT is V DD . When the input high signal V AA  is changed to an input low signal V SS , M 7  is OFF. During the transition state of M 2 , the voltage of node B gradually rises because of the charging current. When the voltage of node B rises up to V RL -V T , M 2  is OFF. M 1  is ON due to the fact that V Source-to-Gate &gt;V T  is satisfied. Then the voltage of node A rises up to V DD  because of the charging current. As a result, M 6  is ON and the voltage of the output signal OUT is pulled to V SS . For example: V AA =−1.7V, V SS =−5V, V DD =30V, V RL =5V, V RH =24V. 
     When the input high signal V AA  is applied at the gate of M 7 , there is static current in the level shifter  41  because M 1 , M 2  and M 7  are ON. However, because there is only one of the 256 output channels outputting static current all the time, this is not a crucial issue. 
     The chip area of the single-ended high-voltage level shifter  41  is minimized because the number of the high-voltage transistors is minimized. Moreover, by implementing partial logic control circuitry in the single-ended high-voltage level shifter  41 , the chip area of the TFT-LCD gate driver is further minified. Referring to FIG. 5, the partial circuitry  511  includes two low-voltage NMOS transistors M 9  and M 10 . Each level shifter of the 256 output channels has the same partial circuitry  511  independently. The gate of the NMOS transistor M 9  receives a first global-on control signal XON 1  while the gate of the NMOS transistor M 10  receives an output-enabled signal OE. The partial circuitry  512  includes two high-voltage PMOS transistors M 11  and M 12 . Each level shifter of the 256 output channels has the partial circuitry  512  in common. The gate of high-voltage PMOS transistor M 11  receives a second global-on control signal XON 2  while the gate of the high-voltage PMOS transistor M 12  receives a third global-on control signal XON 3 . 
     The global-on control signals XON 1 , XON 2  and XON 3  are employed to control the mode of gate driver. When the voltage V SS  is applied at XON 1  and XON 2 , and the voltage V DD  is applied at XON 3 , only one of the 256 output channels is in ON-state. This is the normal mode of the gate driver. When the voltage V AA  is applied at XON 1 , M 9  is ON. Then the voltage of nodes A and B is pulled to V SS . Now be careful that there is static current in the level shifter  51 . If all 256 output channels have static current at the same time, there will be very large static power consumption. To prevent this from happening, the voltage V DD  is applied at XON 2  and the voltage V SS  is applied at XON 3  so that M 11  is OFF and M 12  is ON. Then the voltage of node E is V DD , and thereby M 1  is OFF. Thus there is no static current in the level shifter  51 . In this case, the gate driver is in all-in-ON mode in which all of the 256 output channels are in ON-state. The output-enabled signal OE is employed to enable the output signal OUT. Whenever the voltage V AA  is applied at OE, the matching output channel enables the output signal OUT. When the voltage V SS  is applied at OE and the gate driver is in the normal mode, the voltage of the output signal OUT is pulled to V SS . 
     The above description according to the voltages V SS , V AA  and V DD  applied at XON 1 , XON 2 , XON 3  and OE is concluded in three cases. (1) The voltage V SS  is applied at XON 1  and XON 2 , the voltage V DD  is applied at XON 3 , and the voltage V AA  is applied at OE. In this case, only one of the 256 output channels is in ON-state. This is the normal mode of the gate driver. The circuitry of FIG. 6, being the simplified circuitry of FIG. 5, has the same function with the circuitry of FIG.  4 . (2) The voltage V SS  is applied at XON 1  and XON 2 , the voltage V DD  is applied at XON 3 , and the voltage V SS  is applied at OE. In this case, M 9  and M 10  are OFF. The voltage of the output signal OUT is pulled to V SS . (3) The voltage V AA  is applied at XON 1 , the voltage V DD  is applied at XON 2 , the voltage V SS  is applied at XON 3 , and either the voltage V AA  or the voltage V SS  is applied at OE. M 9  is ON and M 1  is OFF. The voltage of the output signal OUT is pulled to V DD . In this case, the gate driver is in all-in-ON mode in which all of the 256 output channels are in ON-state. The voltage of all 256 output channels is pulled to V DD . In addition, there is no static power consumption in this case because no static current exits. 
     While the invention has been described in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.