Patent Publication Number: US-7898330-B2

Title: Class AB amplifier systems

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of operational amplifiers. 
     2. Prior Art 
     Key performance specifications of operational amplifiers are its input referred offset and noise voltages. These are usually specified as single error sources at the input of the amplifier. 
       FIG. 1  shows a typical prior art folded cascode operational amplifier. Its input referred offset voltage Vos is mainly due to the offset voltages between matched transistor pairs M 1 -M 2 , M 3 -M 4  and M 6 -M 7 . These offset voltages can be calculated back to the input as 
     
       
         
           
             
               
                 
                   
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     Where ΔV and G m  are the offset voltages and transconductances of the indicated transistors. M 8 -M 9  and M 10 -M 11  are cascode devices and therefore do not contribute significantly to Vos. 
     The input referred RMS voltage noise Vn in  can be calculated from 
     
       
         
           
             
               
                 
                   
                     
                       
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     Where V n i is the RMS voltage noise of each contributing transistor. Similar to Vos, it can be assumed that the noise voltages from cascode devices M 8 -M 11  do not add to Vn in . 
     To minimize both Vos and V in , the transconductance of the input stage G m   1 , 2  should be maximized and the transconductances of the transistors in the folding stage M 3 -M 6  should be minimized. This is traditionally done by choosing the W/L ratios such that M 1  and M 2  operate in weak inversion and M 3 -M 6  operate in strong inversion. Further decreasing the transconductances of M 3 -M 6  by lowering their drain currents is usually not done as it deteriorates the slewrate of the amplifier. 
     In strong inversion the G m  of a MOS transistor is defined as 
                     G   m     =       2   ⁢     I   d         V     gs   ,   eff                 (   3   )               
where I d  is the drain current and V gs,eff  is the effective gate-source voltage or gate-source voltage V gs  minus threshold voltage V t . The transconductance in weak inversion is
 
                     G   m     =       I   d       nV   th               (   4   )               
where n is the weak inversion slope factor with an approximate value of 2 and V th  is the thermal voltage kT/q which is about 25 mV at room temperature.
 
     As an example, consider the offset voltages in the input transistor pair to be 5 mV and in transistor pairs M 3 -M 4  and M 5 -M 6  to be 10 mV. To maintain good bandwidth in the folding stage, transistors M 3 -M 6  have a much smaller area than M 1 -M 2  and therefore have larger offset voltages. V gs,eff  is in the order of 100 mV. Much more effective gate-source voltage is usually not allowed as it increases the minimum supply voltage the circuit can operate at and limits the common mode input voltage range. Vos is then 
     
       
         
           
             
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     It can be seen that the contributions to Vos from the offset voltages in transistor pairs M 3 -M 4  and M 5 -M 6  are in the same order as that from input pair M 1 -M 2 . 
     The noise of a MOS transistor is defined as 
                         Vn   2     _       Δ   ⁢           ⁢   f       =       4   ⁢   kT   ⁢     2   3     ⁢     1   Gm       +     K   ⁢           ⁢         I   a     ⁢   D       Gm     2   f                     (   5   )               
where k is the Boltzman constant, T is the temperature, K is a constant for a given device and a is a constant between 0.5 and 2. The first term on the right hand side of formula 5 is the thermal noise component, and the second term is the flicker noise component. The transconductance of an NMOS transistor is about 3 times that of a PMOS transistor when both operate under the same conditions. Also, flicker noise in NMOS devices is usually much larger than in PMOS devices. Substituting (5) into (2) for each individual transistor results in the noise sources from M 3  and M 4  to be dominant in the circuit.
 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a typical prior art folded cascode operational amplifier. 
         FIG. 2  shows an amplifier with reduced quiescent current in the folding stage. 
         FIG. 3  illustrates an amplifier similar to that of  FIG. 2 , but with current mirrors on both sides. 
         FIG. 4  illustrates an amplifier similar to that of  FIG. 3 , but with the current mirrors being combined. 
         FIG. 5  illustrates an amplifier similar to that of  FIG. 4 , but with the two current sources I 2  and I 3  being replaced by a current mirror and a floating current source I 2 , enabling the circuit to operate with either a PMOS and/or NMOS input stage for rail-to-rail operation. 
         FIG. 6   a - 6   h  illustrate embodiments having a folding stage as a bottom half containing 2 stacked mirrors and a top half containing 2 stacked mirrors, and further illustrating a class AB output stage with various output stage drivers. 
         FIG. 7   a - 7   d  illustrate further embodiments having a folding stage as a bottom half containing 2 stacked mirrors and a top half containing 2 stacked mirrors, and further illustrating a class AB output stage with various output stage drivers. 
         FIG. 8   a - 8   d  illustrate still further embodiments having a folding stage as a bottom half containing 2 stacked mirrors and a top half containing 2 stacked mirrors, and further illustrating a class AB output stage with various output stage drivers. 
         FIG. 9   a - 9   d  illustrate still further embodiments having a folding stage as a bottom half containing 2 stacked mirrors and a top half containing 2 stacked mirrors, and further illustrating a class AB output stage with various output stage drivers. 
         FIGS. 10   a  and  10   d  illustrate four basic pairs of upper and lower nested current mirrors of the present invention. 
         FIG. 11  illustrates the interconnection of the upper and lower nested mirrors for the embodiments of  FIGS. 6   a - 6   c ,  6   f ,  7   a ,  7   b ,  8   a ,  8   b ,  9   a  and  9   b.    
         FIGS. 12   a  and  12   b  illustrate the interconnection of upper and lower nested current mirrors having split output transistors. 
         FIGS. 13   a - 13   h  illustrate 8 embodiments having upper and lower nested current mirrors with split output transistors. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the description and in the claims to follow, the terms current inputs and current outputs are used generally without regard to current direction, but are used more in the context of cause and effect. 
     To further decrease the contribution of offset and noise from the transistors in the folding stage, its quiescent current should be reduced without affecting the large signal properties.  FIG. 2  shows an amplifier with reduced quiescent current in the folding stage. 
     Transistors M 3  and M 4  are connected as a current mirror while M 6  and M 7  are current sources. When I 2 &lt;&lt;I 1  and the mirror ratio M 5 -M 6  and M 5 -M 7  is 1, the transconductance of M 3 -M 7 , and thus their contributions to Vos and V in , are decreased. When the gate of M 1  is pulled below the gate of M 2  such that tail current I 1  flows completely through M 1  into M 3 , the current in M 4 , equal to the current in M 3 , will flow out of output node Vout. This output current does not depend on the quiescent current through M 7  and is only limited by tail current I 1 . 
     When I 1  flows completely through M 2  into M 4 , the current flowing into Vout is limited by the quiescent current in M 7  which is much smaller than I 1  thus limiting the slewrate of the amplifier. 
     The current mirror in  FIG. 2  only realizes the desired behavior of low quiescent current and maximum output current when this current flows into diode connected devices M 3  and M 10 . A next step would be to create current mirrors for both sides as is shown in  FIG. 3 . 
     When tail current I 1  flows through M 1  into M 3 , an equal current flows from Vout into M 4 . Likewise, when I 1  flows through M 2  into M 12 , it is copied in M 13 , mirrored by M 6 -M 7  and flows into Vout. 
       FIG. 3  shows the 2 mirrors at the bottom side of the folding stage having low quiescent current and good large signal properties. Disadvantages are the increased complexity compared to the circuit in  FIG. 1 , increase the supply current and contribute to noise and offset. 
     By combining the two mirrors as shown in  FIG. 4 , the complexity becomes as simple as that of a traditional folding cascade stage. 
     The two mirrors M 3 -M 4  and M 12 -M 13  at the bottom of the folding stage in  FIG. 3  are now placed anti parallel on top of each other. When tail current I 1  flows into M 3  through M 1 , it will be copied in M 4 , through M 6 M 7  into Vout. When I 1  flows through M 2 , the drain voltage of M 4  will increase. As M 12  is connected as diode with a fixed drain current, the gate of M 12  and thus the gate of M 13  will increase also. The voltage at the source of M 13  is fixed because of M 10  and I 2  and thus the current through M 13  will increase. This current is forced into M 3  by the loop formed by M 3  and M 10 . The current through M 4  will then also increase until the complete tail current flows through it and thus also through M 13 . 
     The two current sources I 2  and I 3  can be replaced by a current mirror and a floating current source I 2  as drawn in  FIG. 5 , enabling the circuit to operate with either a PMOS and/or NMOS input stage for rail-to-rail operation. 
     Floating current source I 2 , when implanted with a transistor, in series with diode connected devices M 3 /M 10  and M 14 /M 16  limit the minimum supply voltage the circuit can operate at to 2 Vt+3 Vdsat.  FIG. 6   b  shows the implementation of a low voltage floating current source, enabling a minimum supply voltage of Vt+3 Vdsat. M 8  is split into two transistors, of which both gates are connected together as well as both sources, forcing the drain currents to be equal. M 10  is also split and act as a differential pair. The “quiescent control circuitry” block forces M 10 B to have a defined drain current. Mirror M 8 A and M 8 B forces the current in M 10 A to be equal to the current in M 10 B. The two diodes M 3  and M 6  are not in series anymore but can operate next to each other. 
     Also, the two current mirrors M 6 M 7  and M 16 M 17  have been replaced by a similar low voltage stacked mirror structure as M 3 M 4 -M 10 -M 13  to lower the contribution of noise and offset.  FIGS. 6   b  and  6   g - 6   h  show the same amplifier with one implementation of the “quiescent control circuitry” block. 
     Mirrors M 16 M 17  and M 12 M 13  can also been seen as if the original cascode transistors M 10 , M 11 , M 8  and M 9  were split. One half of these transistors are still connected as cascodes, the other half form the mirrors. Transistors M 16 M 17  and M 12 M 13  therefore do not contribute to noise and offset in the amplifier. 
     Besides decreasing the amplifiers noise and offset voltages, the folding stage circuit has an increased output impedance comparable to a gainboosted amplifier and a higher bandwidth. The increased output impedance can be explained as follows: 
     When Vout decreases by a small amount ΔV, the current through M 13  decreases by ΔI=ΔV/Rout 13 . The ΔI difference in M 13  forces the same ΔI difference in M 3  and M 4  which is mirrored through M 16 M 17  back into Vout. The resulting current flowing into Vout as a result of the output impedance of M 13  is the difference between the ΔI currents in M 13  and M 16  thus increasing the output impedance. 
     The higher bandwidth is achieved by the signal current from M 1  and M 2  not going through mirrors M 3 M 4  and/or M 6 M 7  but having a direct path through the cascode devices M 13 , M 11 , M 17  and M 16 . As these devices are much smaller than current mirrors M 3 M 4  and M 6 M 7 , they have a wider bandwidth. 
     The folding stage in  FIG. 6   a  can be seen as a bottom half containing 2 stacked mirrors M 3 M 4 , M 12 M 13  and a top half containing 2 stacked mirrors M 6 M 7  and M 16 M 17 . As the mirrors operate independent from each other, 3 other circuit configurations are possible as drawn in  FIGS. 7   a ,  8   a  and  9   a . The quiescent control circuitry in all the circuits can be just a current source and mirroring transistor M 20 , as shown in  FIGS. 6   b  and  6   f - 6   h.    
       FIGS. 7   a ,  8   a  and  9   a  show the differential input stage and the intermediate stage of a class AB amplifier incorporating the invention. While these Figures suggest a single ended output of the intermediate stage,  FIGS. 6   c - 6   e ,  6   g ,  6   h ,  7   c - 7   d ,  8   c - 8   d  and  9   c - 9   d  illustrate the application of the present invention in embodiments having a pair of outputs for driving the pull-up and pull-down transistors M 22  and M 21 . The class AB control shown in these Figures is well known and not described in detail herein. 
     It will be noted that all embodiments utilize what has been referred to herein as upper and lower nested current mirrors. These basic circuits are shown in  FIGS. 10   a  and  10   b , and  10   c  and  10   d , respectively, and are labeled as in  FIGS. 6   a ,  7   a ,  8   a  and  9   a . While  FIGS. 10   a  and  10   b  appear slightly different than the Figures they are taken from, they are simply drawn slightly differently, but are the same circuits. 
     Referring first to  FIG. 10   a , it will be noted that Transistors M 6  and M 7  are connected as a mirror by way of their connection to transistors M 8 A and M 9 . Also because the cascode connection of transistors M 8 A and M 9 , the voltages on the drains of transistors M 6  and M 7 , and thus the voltages of the sources of M 16  and M 17 , are substantially equal, so that the current mirror M 16 ,M 17  operates substantially independent of current mirror M 6 ,M 7 . The same is true for the current mirrors M 3 M 4  and M 12 M 13 . These basic circuits are reflected also in  FIGS. 10   b - 10   d ,  FIGS. 10   c  and  10   d  being connected to the opposite power supply terminals, the upper current mirrors using transistors of the opposite conductivity type than the lower current mirrors. Vref in the Figures is a current mirror voltage to provide a bias current to the circuits. Also when one of the upper nested mirrors is used with one of the lower nested mirrors, one of the nested mirrors will be coupled to the differential input from the differential input stage, as in the earlier Figures. Also in these Figures, the drain current provided by Vref (the current mirroring voltage) through the drains of transistors M 12 B and M 10 B respectively, are labeled as OUTA 1 . These drain currents are mirrored by mirror transistors M 8 A or M 17 A on the opposite side (top or bottom) of the circuit to transistors M 8 B or M 17 B, respectively, which drain currents are also labeled OUTA 1 . Similarly, the drains of the diode connected transistors of the nested mirror that are adjacent the transistors M 8 B, M 10 B, M 12 B and M 17 B, namely transistors M 8 A, M 10 A, M 12 A and M 17 A, are labeled as INA, and the drain circuits of the transistors to which they mirror current are labeled OUTA 2 . The drain circuits of the diode connected transistors of the other nested mirror are labeled IN 2 , as the currents in these drain circuits are mirrored to their companion transistors M 16 , M 13 , M 9  AND M 11 , which drain circuits become OUT 2 . In all cases, OUTA 1  of the top nested mirrors is connected to INA of the bottom nested mirrors, and OUTA 1  of the bottom nested mirrors is connected to INA of the top nested mirrors. This then is the basic building block of the various embodiments of the present invention from which all embodiments are derived. Note that there are two variations of the upper pair of current mirrors ( FIGS. 10   a  and  10   c ) and two variations of the lower pair of current mirrors ( FIGS. 10   a  and  10   b ), thereby providing the four variations of  FIGS. 10   a - 10   d  in the basic embodiments of the invention. 
     Also in general, OUTA 2  of the top nested mirrors is connected to IN 2  of the bottom nested mirrors, and OUTA 2  of the bottom nested mirrors is connected to IN 2  of the top nested mirrors. OUT 2  then becomes the output, or one output, as shown in  FIG. 11 , from which the class AB control for the pull-up and pull-down transistors M 22  and M 21  of the output stage is derived, such as in  FIGS. 6   c ,  6   f ,  7   b ,  8   b  and  9   b.    
     Depending on the configuration and supply voltage, the proposed intermediate stages may require a start-up circuit to assist in finding their proper bias operating points. The start-up circuits will need to inject a small current into the intermediate stage, for example into any of the nodes labeled INA. Since such a one-sided current will cause some offset in the intermediate stage, the start-up circuit may include a detection function that shuts off the start-up current when the intermediate stage arrives at its desired operating point. Alternatively, the offset caused by the start-up current can be balanced out by injecting a current of identical magnitude into another node of the circuit, for example, any of the nodes labeled IN 2 . In one preferred embodiment, the equal currents are mirrored from the top rail into the INA and IN 2  nodes of the bottom circuit. 
     In some cases, depending on the class AB output transistor drive circuitry, some transistors have companion transistors, but still the basic building block of the invention is present in all embodiments. These companion transistors split the output OUT 2  of both the upper and lower nested mirrors into two current outputs, OUT 2 . 1  and OUT 2 . 2 . In this case, the upper and lower nested mirrors are connected as shown in  FIG. 12   a  or  12   b . Further, there are two different ways of driving these companion transistors, which expands the number of combinations to eight. In any case, the current outputs OUT 2 . 1  and OUT 2 . 2  are drain currents, and thus high impedance current sources capable of delivering the current outputs OUT 2 . 1  and OUT 2 . 2  to different voltages. The transistors providing the current outputs OUT 2 . 1  and OUT 2  may be connected to an internal node, such that the ratio of current outputs OUT 2 . 1  and OUT 2 . 2  is substantially fixed, which ratio may or may not be one. Alternatively, the companion transistors may be connected to a control voltage Vab such that the currents in OUT 2 . 1  and OUT 2 . 2  are not related. The number of combinations is eight, not sixteen, as one of the companion transistors must be controlled by a control voltage Vab as shown in  FIGS. 12   a  and  12   b , typically a current mirroring voltage. Note however, that the circuits of  FIGS. 12   a  and  12   b  may be turned over so to speak, using transistors of the opposite conductivity type. 
       FIGS. 13   a - 13   h  illustrate these variations. As can be seen therein, the companion transistors are companion to one of the diode connected transistors in each of the upper and lower nested current mirrors, with one of the companion transistors in each Figure being controlled by a control voltage Vab. 
     In the embodiments described herein, a PMOS transistor pair and associated current source form the differential input stage. Alternatively, an NMOS transistor pair and associated current source may be used, providing a differential current input to the upper nested mirrors. Also alternatively, both a PMOS transistor pair and associated current source and an NMOS transistor pair and associated current source may be used as the differential input stage, the gates of each PMOS transistor being coupled to the gate of a respective NMOS transistor, thereby enabling the circuit to operate with rail-to-rail common mode input capabilities. The embodiments described herein have been described with respect to CMOS transistors, though can be readily be realized with other active devices, such as, by way of example, bipolar junction transistors. Also, while the invention has been described with respect to operational amplifiers, it is also applicable to other amplifier systems, such as instrumentation amplifiers, audio amplifiers, weigh scale bridges, Hall effect sensors, high-side current sense circuits, voltage regulators, etc. Thus by using a low quiescent current, the present invention reduces power consumption almost to a theoretical minimum. Also the circuit will operate at an input of only 1.8V with a threshold voltage of 1V. The differential input stage and intermediate stage together provide a gain of over 100 dB. The resulting amplifiers have increased bandwidth, reduce input referred noise, reduced random input offset, reduced die area, increasing margin and allowing space saving packages, such as SC-70 packages. The class-AB operation of the intermediate stage lowers the power consumption, offset and noise. Also the intermediate stage can be optimized for both DC accuracy and high-speed performance. The intermediate stage creates high gain, due to the gain-boost effect. 
     While certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.