Patent Publication Number: US-11646738-B2

Title: Processor with adjustable operating frequency

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a processor with adjustable operating frequency. 
     2. Description of the Prior Art 
     When a central processing unit (CPU) or a graphics processing unit (GPU) is operating, its supply voltage may be greatly changed due to parasitic impedance of a printed circuit board, parasitic impedance of the package, a voltage drop of the die itself (IR drop), or the change in the drawn current caused by the change of the load. For example, if the load increases rapidly, the supply voltage of the processor will have a large voltage drop due to the rapid increase in the current drawn, which will cause problems in the operation of the processor. In order to solve the above problems, some methods are provided so that the supply voltage of the processor will not drop to a critical value and affect the operation of the processor. The first method is to increase an area of the decoupling capacitor inside the chip, but this method will increase the manufacturing cost of the chip. The second method is to increase the supply voltage of the processor to provide sufficient voltage drop buffer, however, this method will increase the power consumption of the chip and shorten the life of the chip. The third method is to reduce an operating frequency of the processor, however, reducing the operating frequency will affect the performance of the processor. Therefore, how to provide an effective method to solve the voltage drop issue is an important topic. 
     SUMMARY OF THE INVENTION 
     It is therefore an objective of the present invention to provide a method which can detect the level of the supply voltage of the processor in a real-time manner, and to select one of a plurality of clock signals to increase or decrease the operating frequency of the processor according to the detected level of the supply voltage, so that the processor can have the operating frequency that is most suitable for the current supply voltage, so as to solve the above-mentioned problems. 
     In one embodiment of the present invention, a processor comprising a first core circuit, a plurality of clock signal generation circuits, a multiplexer and a first detection circuit is disclosed. The first core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the first core circuit uses the output clock signal to serve as an operating clock. The first detection circuit is configured to detect a level of the supply voltage received by the first core circuit in a real-time manner, to generate the control signal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a diagram illustrating a processor according to one embodiment of the present invention. 
         FIG.  2    is diagram of the change of the level of the supply voltage provided to the core circuit. 
         FIG.  3    is a diagram illustrating a processor according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a diagram illustrating a processor  100  according to one embodiment of the present invention, where the processor  100  may be a CPU, a GPU or a processor with other functions. As shown in  FIG.  1   , the processor  100  includes a core circuit  110 , a multiplexer  120 , and a plurality of clock signal generation circuits  130 _ 1 - 130 _ 4 , wherein the core circuit  110  includes a detection circuit  112 . In this embodiment, the clock signal generation circuits  130 _ 1 - 130 _ 4  can be implemented by using a phase-locked loop, and the clock signal generation circuits  130 _ 1 - 130 _ 4  are used to generate clock signals CLK 1 -CLK 4  with different frequencies. In one embodiment, the clock signal CLK 1  is the clock signal used by the core circuit  110  in the steady state, and the frequencies of the clock signals CLK 2 -CLK 4  can be ( 31/32), ( 30/32) and ( 29/32) of the frequency of the clock signal CLK 1 , respectively, that is, if the frequency of the clock signal CLK 1  is 1.6 GHz, the frequencies of the clock signals CLK 2 -CLK 4  are 1.55 GHz, 1.5 GHz, 1.45 GHz, respectively. In another embodiment, the frequencies of the clock signals CLK 2 -CLK 4  can be ( 15/16), ( 14/16) and ( 13/16) of the frequency of the clock signal CLK 1 , respectively. In another embodiment, the frequencies of the clock signals CLK 2 -CLK 4  can be (⅞), ( 6/8) and (⅝) of the frequency of the clock signal CLK 1 , respectively. In another embodiment, the frequencies of the clock signals CLK 2 -CLK 4  may be ( 8/9), (⅘), (⅔) of the frequency of the clock signal CLK 1 , respectively. It is noted that the above-mentioned frequencies of the clock signals CLK 1 -CLK 4  are for illustrative purposes only, not a limitation of the present invention. 
       FIG.  1    shows four clock signal generation circuits  130 _ 1 - 130 _ 4 . However, the number of clock signal generation circuits may vary according to the designer&#39;s consideration. For example, the processor  100  may include eight clock signal generation circuits, and the frequencies of the generated clock signals are f, ( 31/32)*f, ( 30/32)*f, ( 29/32)*f, ( 28/32)*f, (27)/32)*f, ( 26/32)*f, ( 25/32)*f, respectively. As long as the number of clock signal generation circuits is equal to or greater than three, this alternative design should fall within the scope of the present invention. 
     In an embodiment, some of the clock signal generation circuits  130 _ 1 - 130 _ 4  may be shared. For example, the clock signal generation circuits  130 _ 1  and  130 _ 2  have some shared circuits, and/or the clock signal generation circuits  130 _ 3  and  130 _ 4  have some shared circuits. 
     In  FIG.  1   , the detection circuit  112  is positioned within the core circuit  110 , but this design is not a limitation of the present invention. In other embodiments, the detection circuit  112  can be positioned around the core circuit  110 , and this alternative design should fall within the scope of the present invention. 
     In the operation of the processor  100 , the detection circuit  112  detects a level (voltage level) of the supply voltage VDD of the core circuit  110  in a real-time manner, to generate a control signal Vc. For example, the possible variation range of the supply voltage VDD can be divided into 16 intervals, and the control signal Vc is used to indicate which interval the current supply voltage VDD is located, for controlling the operation of the multiplexer  120 . In one embodiment, the detection circuit  112  is an analog-to-digital converter (ADC), which is used to convert the supply voltage VDD into a digital signal to serve as the control signal Vc. The multiplexer  120  continuously receives the control signal Vc, and refers to the control signal Vc to determine which of the clock signals CLK 1  to CLK 4  is selected as the output clock signal CLK out serving as the operating clock of the core circuit  110 . For example, suppose that the frequencies of the clock signals CLK 1 -CLK 4  are 1.6 GHz, 1.55 GHz, 1.5 GHz, and 1.45 GHz, respectively, and the possible variation range of the supply voltage VDD can be divided into 16 intervals, for example, the interval ‘0’ to the interval ‘15’ are provided from low to high, and if the control signal Vc indicates that the supply voltage is in the range of interval ‘0’-interval ‘3’, it means that the level of the current supply voltage VDD is too low, at this time, the multiplexer  120  will select the clock signal CLK 4  to serve as the output clock signal CLK out, so that the core circuit  110  operates with a lower frequency. If the control signal Vc indicates that the supply voltage is in the range of interval ‘4’-interval ‘7’, the multiplexer  120  may select the clock signal CLK 3  to serve as the output clock signal CLK out. If the control signal Vc indicates that the supply voltage is in the range of interval ‘8’-interval ‘11’, the multiplexer  120  may select the clock signal CLK 2  to serve as the output clock signal CLK out. If the control signal Vc indicates that the supply voltage is in the range of interval ‘12’-interval ‘15’, it means that the current supply voltage VDD has a normal voltage level. At this time, the multiplexer  120  will select the clock signal CLK 1  to serve as the output clock signal CLK out to make the core circuit  110  operate with a normal frequency to have higher efficiency. 
     As described above, by using the operations of the above embodiments, the processor  100  can select the best clock signal as the operating clock when the level of the supply voltage VDD changes. In addition, because the processor  100  has many clock signal generation circuits  130 _ 1 - 130 _ 4 , the operating clock (operating frequency) of the processor  100  can change smoothly, and there will be no excessive frequency reduction or excessive frequency increase. Specifically, refer to  FIG.  2    which shows the change of the level of the supply voltage VDD, assuming that V 1  is the level of the supply voltage VDD in the steady state, and at the beginning, the multiplexer  120  will select the clock signal CLK 1  with the highest frequency as the output clock signal CLK out, so that the core circuit  110  has high efficiency. Then, at time t 1 , the core circuit  110  draws more current due to the increase of the load, which causes the supply voltage VDD to drop. At this time, the detection circuit  112  continuously detects the level of the supply voltage VDD to generate the control signal Vc to the multiplexer  120 , so that the multiplexer  120  can sequentially output the clock signals CLK 2 , CLK 3 , CLK 4  to the core circuit  110 , so as to reduce the operating frequency of the core circuit  110  slowly and smoothly. At time t 2 , the supply voltage VDD starts to rise, the detection circuit  112  continuously detects the level of the supply voltage VDD to generate the control signal Vc to the multiplexer  120 , so that the multiplexer  120  can sequentially output the clock signals CLK 4 , CLK 3 , CLK 2  and CLK 1  to the core circuit  110 , so as to increase the operating frequency of the core circuit  110  slowly and smoothly. 
     In the prior art, in order to prevent the core circuit  110  from crashing due to a sudden drop of the supply voltage VDD, the supply voltage VDD is designed to be higher at the beginning, for example, V 1  shown in  FIG.  2    will be designed with a higher level to cope with various possible situations. However, designing a high-level supply voltage VDD represents high power consumption and a short lifespan. Compared with the prior art, this embodiment can switch the clock signal when the supply voltage VDD changes slightly to avoid operational problems of the core circuit  110 . Therefore, this embodiment can design the supply voltage VDD to have a lower voltage level, that is, V 1  shown in  FIG.  2    has a lower level, to reduce the power consumption of the processor  100 . 
       FIG.  3    is a diagram illustrating a processor  300  according to another embodiment of the present invention, where the processor  300  may be a CPU, a GPU or a processor with other functions. As shown in  FIG.  3   , the processor  300  includes a plurality of core circuits  310 _ 1 - 310 _N, a multiplexer  320 , a plurality of clock signal generation circuits  330 _ 1 - 330 _ 4  and a selection circuit  340 , wherein N is any suitable positive integer greater than one, and each core circuit includes a detection circuit. For example, the core circuit  310 _ 1  includes a detection circuit  312 _ 1 , and the core circuit  310 _N includes a detection circuit  312 _N. In this embodiment, the clock signal generation circuits  330 _ 1 - 330 _ 4  can be implemented by using a phase-locked loop, and the clock signal generation circuits  330 _ 1 - 330 _ 4  are used to generate clock signals CLK 1 -CLK 4  with different frequencies. In one embodiment, the clock signal CLK 1  is the clock signal used by the core circuits  310 _ 1 - 310 _N in the steady state, and the frequencies of the clock signals CLK 2 -CLK 4  can be ( 31/32), ( 30/32) and ( 29/32) of the frequency of the clock signal CLK 1 , respectively, that is, if the frequency of the clock signal CLK 1  is 1.6 GHz, the frequencies of the clock signals CLK 2 -CLK 4  are 1.55 GHz, 1.5 GHz, 1.45 GHz, respectively. In another embodiment, the frequencies of the clock signals CLK 2 -CLK 4  can be ( 15/16), ( 14/16) and ( 13/16) of the frequency of the clock signal CLK 1 , respectively. In another embodiment, the frequencies of the clock signals CLK 2 -CLK 4  can be (⅞), ( 6/8) and (⅝) of the frequency of the clock signal CLK 1 , respectively. In another embodiment, the frequencies of the clock signals CLK 2 -CLK 4  may be ( 8/9), (⅘), (⅔) of the frequency of the clock signal CLK 1 , respectively. It is noted that the above-mentioned frequencies of the clock signals CLK 1 -CLK 4  are for illustrative purposes only, not a limitation of the present invention. 
       FIG.  3    shows four clock signal generation circuits  330 _ 1 - 330 _ 4 . However, the number of clock signal generation circuits may vary according to the designer&#39;s consideration. For example, the processor  300  may include eight clock signal generation circuits, and the frequencies of the generated clock signals are f, ( 31/32)*f, ( 30/32)*f, ( 29/32)*f, ( 28/32)*f, (27)/32)*f, ( 26/32)*f, ( 25/32)*f, respectively. As long as the number of clock signal generation circuits is equal to or greater than three, this alternative design should fall within the scope of the present invention. 
     In an embodiment, some of the clock signal generation circuits  330 _ 1 - 330 _ 4  may be shared. For example, the clock signal generation circuits  330 _ 1  and  330 _ 2  have some shared circuits, and/or the clock signal generation circuits  330 _ 3  and  330 _ 4  have some shared circuits. 
     In  FIG.  3   , the detection circuits  312 _ 1 - 312 _N are positioned within the core circuits  310 _ 1 - 310 _N, respectively, but this design is not a limitation of the present invention. In other embodiments, the detection circuits  312 _ 1 - 312 _N can be positioned around the core circuits  310 _ 1 - 310 _N, respectively, and this alternative design should fall within the scope of the present invention. 
     In the operation of the processor  300 , the detection circuits  312 _ 1 - 312 _N detect levels (voltage levels) of the supply voltages VDD 1 -VDDN of the core circuits  310 _ 1 - 310 _N in a real-time manner, to generate control signals Vc 1 -VcN. In this embodiment, the core circuits  310 _ 1 - 310 _N are powered by the same supply voltage VDD, but because the loads of the core circuit  310 _ 1 - 310 _N are different, VDD 1 -VDDN are the actual supply voltages received by the core circuits  310 _ 1 - 310 _N respectively. Then, the selection circuit  340  receives the control signals Vc 1 -VcN, and selects one of the control signals Vc 1 -VcN to serve as a control signal Vc, wherein the selected one the control signals Vc 1 -VcN corresponds to a lowest supply voltage among the supply voltages VDD 1 -VDDN. For example, the possible variation range of the supply voltage VDD 1 /VDDN can be divided into 16 intervals, and the control signals Vc 1 /VcN is used to indicate which interval the current supply voltage VDD 1 /VDDN belongs to. In one embodiment, each of the detection circuits  312 _ 1 - 312 _N is an ADC, which is used to convert the supply voltage VDD 1 /VDDN into a digital signal to serve as the control signal Vc 1 /VcN, for the selection circuit  340  to determine the control signal Vc. The multiplexer  320  continuously receives the control signal Vc, and refers to the control signal Vc to determine which of the clock signals CLK 1  to CLK 4  is selected as the output clock signal CLK out serving as the operating clock of the core circuit  310 _ 1 - 310 _ 4 . For example, suppose that the frequencies of the clock signals CLK 1 -CLK 4  are 1.6 GHz, 1.55 GHz, 1.5 GHz, and 1.45 GHz, respectively, and the possible variation range of the supply voltage VDD can be divided into 16 intervals, for example, from low to high the interval ‘0’ to the interval ‘15’, and if the control signal Vc indicates that the supply voltage VDD is in the range of interval ‘0’-interval ‘3’, it means that the level of the current supply voltage VDD is too low, at this time, the multiplexer  320  will select the clock signal CLK 4  to serve as the output clock signal CLK out, so that the core circuits  310 _ 1 - 310 _N operate with a lower frequency. If the control signal Vc indicates that the supply voltage VDD is in the range of interval ‘4’-interval ‘7’, the multiplexer  320  may select the clock signal CLK 3  to serve as the output clock signal CLK out. If the control signal Vc indicates that the supply voltage VDD is in the range of interval ‘8’-interval ‘11’, the multiplexer  320  may select the clock signal CLK 2  to serve as the output clock signal CLK out. If the control signal Vc indicates that the supply voltage is in the range of interval ‘12’-interval ‘15’, it means that the current supply voltage VDD has a normal voltage level. At this time, the multiplexer  320  will select the clock signal CLK 1  to serve as the output clock signal CLK out to make the core circuits  310 _ 1 - 310 _N operate with a normal frequency to have higher efficiency. 
     As described above, by using the operations of the above embodiments, the processor  300  can select the best clock signal as the operating clock when the level of the supply voltage VDD changes. In addition, because the processor  300  has many clock signal generation circuits  330 _ 1 - 330 _ 4 , the operating clock (operating frequency) of the processor  300  can change smoothly, and there will be no excessive frequency reduction or excessive frequency increase. In addition, compared with the prior art, this embodiment can switch the clock signal when the supply voltage VDD changes slightly to avoid operational problems of the core circuits  310 _ 1 - 310 _N. Therefore, this embodiment can design the supply voltage VDD to have a lower voltage level to reduce the power consumption of the processor  300 . 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.