Patent Publication Number: US-11640962-B2

Title: Semiconductor structure

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of U.S. application Ser. No. 16/881,804, filed on May 22, 2020, which is a Continuation of U.S. application Ser. No. 16/128,783, filed on Sep. 12, 2018, which claims priority of U.S. Provisional Application No. 62/718,815, filed on Aug. 14, 2018, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND 
     Integrated circuits (ICs) have become increasingly important. Applications using ICs are used by millions of people. These applications include cell phones, smartphones, tablets, laptops, notebook computers, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless web browsers. Integrated circuits increasingly include powerful and efficient on-board data storage and logic circuitry for signal control and processing. 
     Memories are commonly used in ICs. For example, a static random access memory (SRAM) is a volatile memory used in electronic applications where high speed, low power consumption, and simplicity of operation are needed. Embedded SRAM is particularly popular in high-speed communications, image processing, and system-on-chip (SOC) applications. SRAM has the advantage of being able to hold data without requiring a refresh. 
     The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., memory cells and standard cells). Therefore, metal routing efficiency is important for decreasing the complexity of IC designs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various nodes are not drawn to scale. In fact, the dimensions of the various nodes may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  is a simplified diagram of an IC, in accordance with some embodiments of the disclosure. 
         FIG.  1 B  is a simplified diagram of an IC, in accordance with some embodiments of the disclosure. 
         FIG.  1 C  is a simplified diagram of an IC, in accordance with some embodiments of the disclosure. 
         FIG.  2 A  illustrates a logic symbol of a standard cell. 
         FIG.  2 B  is a circuit diagram of the standard cell in  FIG.  2 A . 
         FIG.  3    illustrates the layout of the semiconductor structure of a first logic cell, in accordance with some embodiments of the disclosure. 
         FIG.  4 A  illustrates a cross-sectional view of the semiconductor structure of the first logic cell along line A-AA in  FIG.  3   , in accordance with some embodiments of the disclosure. 
         FIG.  4 B  illustrates a cross-sectional view of the semiconductor structure of the first logic cell along line B-BB in  FIG.  3   , in accordance with some embodiments of the disclosure. 
         FIG.  4 C  illustrates a cross-sectional view of the semiconductor structure of the first logic cell along line E-EE in  FIG.  3   , in accordance with some embodiments of the disclosure. 
         FIG.  5    illustrates the layout of the semiconductor structure of a second logic cell, in accordance with some embodiments of the disclosure. 
         FIG.  6 A  illustrates a cross-sectional view of the semiconductor structure of the second logic cell along line C-CC in  FIG.  5   , in accordance with some embodiments of the disclosure. 
         FIG.  6 B  illustrates a cross-sectional view of the semiconductor structure of the second logic cell along line D-DD in  FIG.  5   , in accordance with some embodiments of the disclosure. 
         FIG.  7 A  illustrates a memory cell, in accordance with some embodiments of the disclosure. 
         FIG.  7 B  is a simplified diagram of the memory cell in  FIG.  7 A , in accordance with some embodiments of the disclosure. 
         FIG.  8    illustrates the layout of the semiconductor structure of two memory cells, in accordance with some embodiments of the disclosure. 
         FIG.  9 A  illustrates a cross-sectional view of the semiconductor structure of the memory cell along line F-FF in  FIG.  8   , in accordance with some embodiments of the disclosure. 
         FIG.  9 B  illustrates a cross-sectional view of the semiconductor structure of the memory cells along line G-GG in  FIG.  8   , in accordance with some embodiments of the disclosure. 
         FIG.  9 C  illustrates a cross-sectional view of the semiconductor structure of the memory cells along line G-GG in  FIG.  8   , in accordance with some embodiments of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different nodes of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In some embodiments, the formation of a first node over or on a second node in the description that follows may include embodiments in which the first and second nodes are formed in direct contact, and may also include embodiments in which additional nodes may be formed between the first and second nodes, such that the first and second nodes may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method. 
     Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Various semiconductor structures of integrated circuits (ICs) are provided in accordance with various exemplary embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. 
       FIG.  1 A  is a simplified diagram of an IC  100 A, in accordance with some embodiments of the disclosure. The IC  100 A includes a first circuit  110  and a second circuit  120 . In some embodiments, the first circuit  110  and the second circuit  120  are configured to perform the same/similar functions or operations. For example, the first circuit  110  and the second circuit  120  may be the controllers for various memories. In some embodiments, the first circuit  110  and the second circuit  120  are configured to perform the different functions or operations. 
     The first circuit  110  includes a plurality of logic cells  10 . In some embodiments, the first logic cell  10  may be a standard cell. Furthermore, the logic functions of the logic cells  10  may be the same or different. For example, the logic cells  10  may be the standard cells corresponding to the same logic gates (e.g., INV, NAND, NOR logic gate and so on) or different logic gates. Similarly, the second circuit  120  includes a plurality of logic cells  20 . In some embodiments, the second logic cell  20  may be a standard cell. Furthermore, the logic functions of the logic cells  20  may be the same or different. In some embodiments, the logic cells  10  and  20  corresponding to the same function or operation have the same circuit configuration with different semiconductor structures. 
       FIG.  1 B  is a simplified diagram of an IC  100 B, in accordance with some embodiments of the disclosure. The IC  100 B includes a second circuit  120  and a memory  130 . In some embodiments, the second circuit  120  may be the controller for accessing the memory  130 . As described above, the second circuit  120  includes a plurality of logic cells  20 , and the logic functions of the logic cells  20  may be the same or different. The memory  130  includes a plurality of memory cells  30  arranged in rows and columns of a array. In some embodiments, the memory cells  30  have the same circuit configuration and the same semiconductor structure. In some embodiments, the memory cell  30  may be a bit cell of SRAM or DRAM. 
       FIG.  1 C  is a simplified diagram of an IC  100 C, in accordance with some embodiments of the disclosure. The IC  100 C includes a first circuit  110 , a second circuit  120  and a memory  130 . In some embodiments, the first circuit  110  and the second circuit  120  are configured to perform the same/similar functions or operations. For example, the first circuit  110  and the second circuit  120  may be the controllers for accessing the one or more memories  130 . In some embodiments, the first circuit  110  and the second circuit  120  are configured to perform the different functions or operations. As described above, the first circuit  110  includes a plurality of logic cells  10 , and the logic functions of the logic cells  10  may be the same or different. Furthermore, the second circuit  120  includes a plurality of logic cells  20 , and the logic functions of the logic cells  20  may be the same or different. Moreover, the memory  130  includes a plurality of memory cells  30  arranged in rows and columns of a array. In some embodiments, the memory cells  30  have the same circuit configuration and the same semiconductor structure. Furthermore, the logic cells  10  and  20  corresponding to the same function or operation have the same circuit configuration with different semiconductor structures. 
       FIG.  2 A  illustrates the logic symbol of a standard cell, and  FIG.  2 B  is a circuit diagram of the standard cell in  FIG.  2 A . The standard cell in  FIG.  2 A  is a NOR logic gate configured to provide an output signal OUT according two input signals IN 1  and IN 2 . The NOR logic gate includes two PMOS transistors P 1  and P 2  and two NMOS transistors N 1  and N 2 . The two PMOS transistors P 1  and P 2  and two NMOS transistors N 1  and N 2  may be planar MOS transistors or fin field effect transistors (FinFETs). 
     In the NOR logic gate, the PMOS transistor P 1  is coupled between a power supply VDD and the PMOS transistor P 2 , and the PMOS transistor P 2  is coupled between the PMOS transistor P 1  and a node  32 . The NMOS transistors N 1  and N 2  are coupled in parallel between the node  32  and a ground VSS. The input signal IN 1  is input to the gates of the PMOS transistor P 1  and the NMOS transistor N 1 , and the input signal IN 2  is input to the gates of the PMOS transistor P 2  and the NMOS transistor N 2 . Furthermore, the output signal OUT is provided at the node  32 . 
       FIG.  3    illustrates the layout of the semiconductor structure of a first logic cell  10 A, in accordance with some embodiments of the disclosure. In  FIG.  3   , the NOR logic gate of  FIGS.  2 A and  2 B  is implemented in the first logic cell  10 A, and the PMOS transistors P 1  and P 2  and the NMOS transistors N 1  and N 2  are dual-fin FETs. 
     In  FIG.  3   , the semiconductor fins  210   a  and  210   b  extending in the Y-direction are disposed over an N-type well region NW 1 , and the semiconductor fins  210   c  and  210   d  extending in the Y-direction are disposed over a P-type well region PW 1 . A gate electrode  220   b  extending in the X-direction forms the PMOS transistor P 1  with an underlying active region formed by the semiconductor fins  210   a  and  210   b  over the N-type well region NW 1 . Furthermore, the gate electrode  220   b  forms the NMOS transistor N 1  with an underlying active region formed by the semiconductor fins  210   c  and  210   d  in the P-type well region PW 1 . In other words, the gate electrode  220   b  is shared by the NMOS transistor N 1  and the PMOS transistor P 1 . The gate electrode  220   b  is coupled to a conductive line  230   c  extending in the Y-direction through a gate contact  245   b  and a via  255   b , and the conductive line  230   c  is configured to connect the gate electrode  220   b  to an overlying level for receiving the input signal IN 1 . 
     A gate electrode  220   c  extending in the X-direction forms the PMOS transistor P 2  with an underlying active region formed by the semiconductor fins  210   a  and  210   b  over the N-type well region NW 1 . Furthermore, the gate electrode  220   c  forms the NMOS transistor N 2  with an underlying active region formed by the semiconductor fins  210   c  and  210   d  in the P-type well region PW 1 . In other words, the gate electrode  220   c  is shared by the NMOS transistor N 2  and the PMOS transistor P 2 . The gate electrode  220   c  is coupled to a conductive line  230   b  extending in the Y-direction through a gate contact  245   a  and a via  255   a , and the conductive line  230   b  is configured to connect the gate electrode  220   c  to an overlying level for receiving the input signal IN 2 . 
     The gate electrodes  220   a  and  220   d  extending in the X-direction are dummy gate electrodes. The gate electrodes  220   b  and  220   c  are arranged between the gate electrodes  220   a  and  220   d , and the NMOS transistors N 1  and N 2  and the PMOS transistors P 1  and P 2  are surrounded by the gate electrodes  220   a  and  220   d.    
     In some embodiments, the structure of the gate electrodes  220   a  through  220   d  includes multiple material structure selected from a group consisting of poly gate/SiON structure, metals/high-K dielectric structure, Al/refractory metals/high-K dielectric structure, silicide/high-K dielectric structure, or a combination thereof. 
     A conductive line  230   a  extending in the Y-direction is coupled to the source region of the PMOS transistor P 1  through the contact  240   a  and the via  250   a , and the conductive line  230   a  is configured to connect the source region of the PMOS transistor P 1  to an overlying level for coupling the power supply VDD. 
     A conductive line  230   d  extending in the Y-direction is coupled to the source region of the NMOS transistor N 1  through the contact  240   d  and the via  250   c  and to the source region of the NMOS transistor N 2  through the contact  240   f  and the via  250   e . The conductive line  230   d  is configured to connect the source regions of the NMOS transistors N 1  and N 2  to an overlying level for coupling the ground VSS. 
     In some embodiments, each of the vias  250   a  through  250   e  and the vias  255   a  and  255   b  includes a metal plug made of the same material. In some embodiments, the material of the metal plug is purely W (Tungsten) or purely Ru (Ruthenium) without sidewall barrier layer. In some embodiments, the material of the metal plug is selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. 
     In some embodiments, each of the contacts  240   a  through  240   f  and the gate contacts  245   a  and  245   b  includes a metal plug made of the same material. In some embodiments, the material of the metal plug is selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. 
     In some embodiments, for the PMOS transistors P 1  and P 2  and the NMOS transistors N 1  and N 2 , the contact  240   a  through  240   f  corresponding to the source/drain regions and the contacts  245   a  and  245   b  corresponding to the gate regions have different shapes in the layout. For example, contacts  240   a  through  240   f  are slot-shaped, and contacts  245   a  and  245   b  have a round shape. 
     In some embodiments, the source/drain regions of the PMOS transistor P 1  and P 2  are formed by the P-type doping region including epitaxy material. The epitaxy material is selected from a group consisting of SiGe, or SiGeC, or Ge, or Si, or a combination thereof. 
     In some embodiments, the source/drain regions of the NMOS transistor N 1  and N 2  are formed by the N-type doping region including epitaxy material. The epitaxy material is selected from a group consisting of SiP content, or SiC content, or SiPC, or Si, or a combination thereof. 
       FIG.  4 A  illustrates a cross-sectional view of the semiconductor structure of the first logic cell  10 A along line A-AA in  FIG.  3   , in accordance with some embodiments of the disclosure. The P-type well region PW 1  and the N-type well region NW 1  are formed over a substrate  310 . In some embodiments, the substrate  310  is a Si substrate. In some embodiments, the material of the substrate  310  is selected from a group consisting of bulk-Si, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-VI material, or a combination thereof. 
     The semiconductor fins  210   a  and  210   b  are formed on the N-type well region NW 1 . In some embodiments, the semiconductor fins  210   a  and  210   b  include an appropriate concentration of n-type dopants (e.g., phosphorous (such as  31 P), arsenic, or a combination thereof). The semiconductor fins  210   a  and  210   b  are separated from each other by the shallow trench isolation (STI)  320 . 
     The semiconductor fins  210   c  and  210   d  are formed on the P-type well region PW 1 . In some embodiments, the semiconductor fins  210   c  and  210   d  include an appropriate concentration of P-type dopants (e.g., boron (such as 11B), boron, boron fluorine (BF 2 ), or a combination thereof). Furthermore, the semiconductor fins  210   c  and  210   d  are separated from each other by the STI  320 . 
     The gate electrode  220   b  is formed over the gate dielectrics  335  and is positioned over a top surface of the semiconductor fins  210   a  through  210   d . Each of the semiconductor fins  210   a  and  210   b  overlapping the gate electrode  220   b , may serve as a channel region CH_P 1  of the PMOS transistor P 1 . Thus, the gate electrode  220   b  and the gate dielectrics  335  over the semiconductor fins  210   a  and  210   b  form a gate structure for the PMOS transistor P 1 . Furthermore, each of the semiconductor fins  210   c  and  210   d  overlapping the gate electrode  220   b  may serve as a channel region CH_N 1  of the NMOS transistor N 1 . Thus, the gate electrode  220   b  and the gate dielectrics  335  over the semiconductor fins  210   c  and  210   d  form a gate structure for the NMOS transistor N 1 . In some embodiments, the spacers  330  are formed on opposite sides of the gate electrode  220   b.    
     Inter-Layer Dielectric (ILD) layer  340  is formed over the gate electrode  220   b  and the spacer  330 . The ILD layer  340  may be formed of an oxide such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like. 
     The contact  245   b  is formed in the ILD layer  340 . Furthermore, the contact  245   b  is disposed over the gate electrode  220   b  and does not overlap the semiconductor fins  210   a  through  210   d . In other words, projection of the contact  245   b  does not overlap the projections of the semiconductor fins  210   a  through  210   d  on the substrate  310 , i.e. the projections of the contact  245   b  and the semiconductor fins  210   a  through  210   d  are separated on the substrate  310 . 
     Inter-metallization dielectric (IMD) layer  350  is formed over the ILD layer  340 . The via  255   b  and the conductive lines  230   a  through  230   f  are formed in the IMD layer  350 . In some embodiments, the conductive lines  230   a  through  230   f  are metal lines formed in the same metal layer. The gate electrode  220   b  is electrically connected to the conductive line  230   c  through the contact  245   b  and the via  255   b , thus the gate regions of the PMOS transistor P 1  and the NMOS transistor N 1  are electrically connected to the conductive line  230   c.    
       FIG.  4 B  illustrates a cross-sectional view of the semiconductor structure of the first logic cell  10 A along line B-BB in  FIG.  3   , in accordance with some embodiments of the disclosure. The P-type well region PW 1  is formed over the substrate  310 . The semiconductor fin  210   c  is formed on the P-type well region PW 1 , and is surrounded by the STI  320 . 
     The ILD  340  is formed over the STI  320 . The N-type doping regions  360   a  through  360   c  form the source/drain regions on the semiconductor fin  210   c . The source/drain silicide regions  370   a  through  370   c  are formed on the N-type doping regions  360   a  through  360   c , respectively. The contacts  240   d  through  240   f  are formed on the source/drain silicide regions  370   a  through  370   c , respectively. Each of the contacts  240   d  through  240   f  includes a metal plug  385  and a high-K dielectric  380  formed on the sidewall of the metal plug  385 . In other words, the metal plug  385  is surrounded by the high-K dielectric  380 . 
     In some embodiments, the dielectric constant of the high-K dielectric  380  is greater than 4.9 or 5. In some embodiments, the thickness of the high-K dielectric  380  is within a range of 5 to 50 Å, where Å=10 10  m. In some embodiments, the material of the high-K dielectric  380  is selected from a group consisting of a nitride-based dielectric, a metal oxide dielectric, Hf oxide (HfO 2 ), Ta oxide (Ta 2 O 5 ), Ti oxide (TiO 2 ), Zr oxide (ZrO 2 ), Al oxide (Al 2 O 3 ), Y oxide (Y 2 O 3 ), or a combination thereof. In some embodiments, the material of the high-K dielectric  380  is selected from a group consisting of SiON, Ta 2 O 5 , Al 2 O 3 , a nitrogen-content oxide layer, nitrided oxide, a metal oxide dielectric, Hf-content oxide, Ta-content oxide, Ti-content oxide, Zr-content oxide, Al-content oxide, La-content oxide, or a combination thereof. 
     The via  250   d  and the conductive line  230   f  are formed in the ILD layer  350 . The N-type doping region  360   b  is electrically connected to the conductive line  230   f  through the via  250   d , the contact  240   e  and the source/drain silicide region  370   b , thus the drain regions of the NMOS transistors N 1  and N 2  are electrically connected to the conductive line  230   f.    
     For the NMOS transistor N 1 , the channel region CH-N 1  is formed between the N-type doping regions  360   a  and  360   b  and under the gate electrode  220   b . For the NMOS transistor N 2 , the channel region CH-N 2  is formed between the N-type doping regions  360   b  and  360   c  and under the gate electrode  220   c . Furthermore, the dummy gate electrodes  220   a  and  220   d  are located upon the edge of the semiconductor fin  210   c . For example, the dummy gate electrodes  220   a  is arranged upon the left edge of the semiconductor fin  210   c , and the dummy gate electrodes  220   d  is arranged upon the right edge of the semiconductor fin  210   c.    
       FIG.  4 C  illustrates a cross-sectional view of the semiconductor structure of the first logic cell  10 A along line E-EE in  FIG.  3   , in accordance with some embodiments of the disclosure. The P-type well region PW 1  and the N-type well region NW 1  are formed over the substrate  310 . The semiconductor fins  210   c  and  210   d  are formed on the P-type well region PW 1 , and the semiconductor fins  210   a  and  210   b  are formed on the N-type well region NW 1 . The semiconductor fins  210   a  through  210   d  are separated from each other by the STI  320 . 
     The ILD  340  is formed over the STI  320  and the semiconductor fins  210   a  through  210   d . The N-type doping region  360   c  forms the source/drain region of the NMOS transistor N 2  on the semiconductor fins  210   c  and  210   d . The source/drain silicide region  370   c  is formed on the N-type doping region  360   c . In some embodiments, the N-type doping region  360   c  is formed by epitaxy material, and the epitaxy material is selected from a group consisting of SiP content, or SiC content, or SiPC, or Si, or a combination thereof. 
     The P-type doping region  365   a  forms the source/drain region of the PMOS transistor P 2  on the semiconductor fins  210   a  and  210   b . The source/drain silicide region  370   g  is formed on the P-type doping region  365   a . In some embodiments, the P-type doping region  365   a  is formed by epitaxy material, and the epitaxy material is selected from a group consisting of SiGe, or SiGeC, or Ge, or Si, or a combination thereof. 
     The contact  240   f  is formed on the source/drain silicide regions  370   c , and the contact  240   c  is formed on the source/drain silicide regions  370   c . Each of the contacts  240   f  and  240   c  includes a metal plug  385  and a high-K dielectric  380  formed on the sidewall of the metal plug  385 . In other words, the metal plug  385  is surrounded by the high-K dielectric  380 . 
     In some embodiments, the dielectric constant of the high-K dielectric  380  is greater than 4.9 or 5. In some embodiments, the thickness of the high-K dielectric  380  is within a range of 5 to 50 Å. In some embodiments, the material of the high-K dielectric  380  is selected from a group consisting of a nitride-based dielectric, a metal oxide dielectric, Hf oxide (HfO 2 ), Ta oxide (Ta 2 O 5 ), Ti oxide (TiO 2 ), Zr oxide (ZrO 2 ), Al oxide (Al 2 O 3 ), Y oxide (Y 2 O 3 ), or a combination thereof. In some embodiments, the material of the high-K dielectric  380  is selected from a group consisting of SiON, Ta 2 O 5 , Al 2 O 3 , nitrogen-content oxide layer, nitrided oxide, metal oxide dielectric, Hf-content oxide, Ta-content oxide, Ti-content oxide, Zr-content oxide, Al-content oxide, La-content oxide or a combination thereof. 
     The vias  250   b  and  250   e  and the conductive lines  230   a  through  230   f  are formed in the ILD layer  350 . The N-type doping region  360   c  is electrically connected to the conductive line  230   d  through the via  250   e , the contact  240   f  and the source/drain silicide region  370   c , thus the source region of the NMOS transistor N 2  is electrically connected to a VSS line through the conductive line  230   d . Furthermore, the P-type doping region  365   a  is electrically connected to the conductive line  230   e  through the via  250   b , the contact  240   c  and the source/drain silicide region  370   g , thus the drain region of the PMOS transistor P 2  is electrically connected to the drain regions of the NMOS transistors N 1  and N 2  through the conductive line  230   e  and the overlying levels. In other words, the contact  240   c  corresponding to the drain region of the PMOS transistor P 2  is electrically connected to the contact  240   e  corresponding to the drain regions of the NMOS transistors N 1  and N 2  through the overlying levels of the conductive lines  230   a  through  230   f.    
       FIG.  5    illustrates the layout of the semiconductor structure of a second logic cell  20 A, in accordance with some embodiments of the disclosure. In  FIG.  5   , the NOR logic gate of  FIGS.  2 A and  2 B  is implemented in the second logic cell  20 A, and the PMOS transistors P 1  and P 2  and the NMOS transistors N 1  and N 2  are dual-fin FETs. For the NOR logic gate of  FIGS.  2 A and  2 B , the first logic cell  10 A in  FIG.  3    and the second logic cell  20 A in  FIG.  5    have the same circuit configuration and different layout configurations. 
     In  FIG.  5   , the semiconductor fins  210   e  and  210   f  extending in the Y-direction are disposed over an N-type well region NW 2 , and the semiconductor fins  210   g  and  210   h  extending in the Y-direction are disposed over a P-type well region PW 2 . A gate electrode  220   e  extending in the X-direction forms the PMOS transistor P 1  with an underlying active region formed by the semiconductor fins  210   e  and  210   f  over the N-type well region NW 2 . Furthermore, the gate electrode  220   e  forms the NMOS transistor N 1  with an underlying active region formed by the semiconductor fins  210   g  and  210   h  in the P-type well region PW 2 . In other words, the gate electrode  220   e  is shared by the NMOS transistor N 1  and the PMOS transistor P 1 . The gate electrode  220   e  is coupled to a conductive line  230   l  extending in the Y-direction through a gate contact  260   b , and the conductive line  230   l  is configured to connect the gate electrode  220   e  to an overlying level for receiving the input signal IN 1 . 
     A gate electrode  220   f  extending in the X-direction forms the PMOS transistor P 2  with an underlying active region formed by the semiconductor fins  210   e  and  210   f  over the N-type well region NW 2 . Furthermore, the gate electrode  220   f  forms the NMOS transistor N 2  with an underlying active region formed by the semiconductor fins  210   g  and  210   h  in the P-type well region PW 2 . In other words, the gate electrode  220   f  is shared by the NMOS transistor N 2  and the PMOS transistor P 2 . The gate electrode  220   f  is coupled to a conductive line  230   i  extending in the Y-direction through a gate contact  260   a , and the conductive line  230   i  is configured to connect the gate electrode  220   f  to an overlying level for receiving the input signal IN 2 . 
     In some embodiments, the structure of the gate electrodes  220   e  and  220   f  includes multiple material structure selected from a group consisting of poly gate/SiON structure, metals/high-K dielectric structure, Al/refractory metals/high-K dielectric structure, silicide/high-K dielectric structure, or a combination thereof. 
     The gate dielectrics  270   a  and  270   b  extending in the X-direction are dummy gate dielectrics. The gate electrodes  220   e  and  220   f  are arranged between the gate dielectrics  270   a  and  270   b , and the NMOS transistors N 1  and N 2  and the PMOS transistors P 1  and P 2  are surrounded by the gate dielectrics  270   a  and  270   b.    
     A conductive line  230   g  extending in the Y-direction is coupled to the source region of the PMOS transistor P 1  through the contact  240   g  and the via  250   f , and the conductive line  230   g  is configured to connect the source region of the PMOS transistor P 1  to an overlying level for coupling the power supply VDD. 
     A conductive line  230   m  extending in the Y-direction is coupled to the source region of the NMOS transistor N 1  through the contact  240   j  and the via  250   h  and to the source region of the NMOS transistor N 2  through the contact  240   l  and the via  250   j . The conductive line  230   m  is configured to connect the source regions of the NMOS transistors N 1  and N 2  to an overlying level for coupling the ground VSS. 
     In some embodiments, each of the vias  250   f  through  250   j  and the vias  260   a  and  260   b  includes a metal plug made of the same material. In some embodiments, the material of the metal plug is purely W (Tungsten) or purely Ru (Ruthenium) without sidewall barrier layer metal. In some embodiments, the material of the metal plug is selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. 
     In some embodiments, each of the contacts  240   g  through  2401  includes a metal plug made of the same material. In some embodiments, the material of the metal plug is selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. In some embodiments, contacts  240   g  through  2401  are slot-shaped. 
     In some embodiments, the source/drain regions of the PMOS transistor P 1  and P 2  are formed by the P-type doping region including epitaxy material. The epitaxy material is selected from a group consisting of SiGe, or SiGeC, or Ge, or Si, or a combination thereof. 
     In some embodiments, the source/drain regions of the NMOS transistor N 1  and N 2  are formed by the N-type doping region including epitaxy material. The epitaxy material is selected from a group consisting of SiP content, or SiC content, or SiPC, or Si, or a combination thereof. 
       FIG.  6 A  illustrates a cross-sectional view of the semiconductor structure of the second logic cell  20 A along line C-CC in  FIG.  5   , in accordance with some embodiments of the disclosure. The P-type well region PW 2  and the N-type well region NW 2  are formed over a substrate  310 . In some embodiments, the substrate  310  is a Si substrate. In some embodiments, the material of the substrate  310  is selected from a group consisting of bulk-Si, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-VI material, or a combination thereof. 
     The semiconductor fins  210   e  and  210   f  are formed on the N-type well region NW 2 . In some embodiments, the semiconductor fins  210   e  and  210   f  include an appropriate concentration of n-type dopants (e.g., phosphorous (such as  31 P), arsenic, or a combination thereof). The semiconductor fins  210   e  and  210   f  are separated from each other by the shallow trench isolation (STI)  320 . 
     The semiconductor fins  210   g  and  210   h  are formed on the P-type well region PW 2 . In some embodiments, the semiconductor fins  210   g  and  210   h  include an appropriate concentration of P-type dopants (e.g., boron (such as 11B), boron, boron fluorine (BF 2 ), or a combination thereof). Furthermore, the semiconductor fins  210   g  and  210   h  are separated from each other by the STI  320 . 
     The gate electrode  220   e  is formed over the gate dielectrics  335  and is positioned over a top surface of the semiconductor fins  210   e  through  210   h . Each of the semiconductor fins  210   e  and  210   f  overlapping the gate electrode  220   e  may serve as a channel region CH_P 1  of the PMOS transistor P 1 . Thus, the gate electrode  220   e  and the gate dielectrics  335  over the semiconductor fins  210   e  and  210   f  form a gate structure for the PMOS transistor P 1 . Furthermore, each of the semiconductor fins  210   g  and  210   h  overlapping the gate electrode  220   e  may serve as a channel region CH_N 1  of the NMOS transistor N 1 . Thus, the gate electrode  220   e  and the gate dielectrics  335  over the semiconductor fins  210   g  and  210   h  form a gate structure for the NMOS transistor N 1 . In some embodiments, the spacers  330  are formed on opposite sides of the gate electrode  220   e.    
     ILD layer  340  is formed over the gate electrode  220   e  and the spacer  330 . The ILD layer  340  may be formed of an oxide such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like. 
     IMD layer  350  is formed over the ILD layer  340 . The conductive lines  230   g  through  230   m  are formed in the IMD layer  350 . In some embodiments, the conductive lines  230   g  through  230   m  are metal lines formed in the same metal layer. The gate electrode  220   e  is electrically connected to the conductive line  230   l  through the via  260   b , thus the gate regions of the PMOS transistor P 1  and the NMOS transistor N 1  are electrically connected to the conductive line  230   l.    
     The via  260   b  is directly (physically) connected to the gate electrode  220   e  without through one contact. Unlike via  255   b  in  FIG.  4 A  formed in the IMD layer  350 , via  260   b  in  FIG.  6 A  is formed through the IMD layer  350  and the ILD layer  340 . In some embodiments, dimensions of via  260   b  in  FIGS.  5  and  6 A  are smaller than those of via  255   b  in  FIGS.  3  and  4 A  in layout. For example, via  260   b  in  FIG.  5    and via  255   b  in  FIG.  3    are round, and the radius of via  260   b  in  FIG.  5    is at least 20% smaller than the radius of via  255   b  in  FIG.  3   . 
     In  FIG.  5   , the layout and dimensions of vias  260   a  and  260   b , which are directly connected to the gate electrodes  220   e  and  220   f , are smaller than those of vias  250   f  through  250   j , which are connected to the contacts  240   g  through  240   l . For example, the vias  260   a  and  260   b  and vias  250   f  through  250   j  are round, and the radius of vias  260   a  and  260   b  is smaller than the radius of vias  250   f  through  250   j . In some embodiments, the radius of vias  260   a  and  260   b  is at least 20% smaller than the radius of vias  250   f  through  250   j.    
     The via  260   b  is disposed over the gate electrode  220   e  and overlaps the semiconductor fin  210   h . In other words, a projection of the via  260   b  overlaps the projection of the semiconductor fin  210   h  on the substrate  310 . In some embodiments, the via  260   b  is disposed over the gate electrode  220   e  and overlaps the semiconductor fin  210   g , therefore the projection of the via  260   b  overlaps the projection of the semiconductor fin  210   g  on the substrate  310 . 
     By using the gate electrode pickup layout that the via  260   b  is directly connecting the gate electrode  220   e , routing efficiency and logic circuit density improvement are increased for the standard cells. 
       FIG.  6 B  illustrates a cross-sectional view of the semiconductor structure of the second logic cell  20 A along line D-DD in  FIG.  5   , in accordance with some embodiments of the disclosure. The P-type well region PW 2  is formed over the substrate  310 . The semiconductor fin  210   h  is formed on the P-type well region PW 2 , and is surrounded by the STI  320 . 
     The ILD  340  is formed over the STI  320 . The N-type doping regions  360   d  through  360   f  form the source/drain regions on the semiconductor fin  210   h . The source/drain silicide regions  370   d  through  370   f  are formed on the N-type doping regions  360   d  through  360   f , respectively. The contacts  240   j  through  2401  are formed on the source/drain silicide regions  370   d  through  370   f , respectively. Each of the contacts  240   j  through  2401  includes a metal plug  385  and a high-K dielectric  380  formed on the sidewall of the metal plug  385 . In other words, the metal plug  385  is surrounded by the high-K dielectric  380 . 
     In some embodiments, the dielectric constant of the high-K dielectric  380  is greater than 4.9 or 5. In some embodiments, the thickness of the high-K dielectric  380  is within a range of 5 to 50 Å. In some embodiments, the material of the high-K dielectric  380  is selected from a group consisting of a nitride-based dielectric, a metal oxide dielectric, Hf oxide (HfO 2 ), Ta oxide (Ta 2 O 5 ), Ti oxide (TiO 2 ), Zr oxide (ZrO 2 ), Al oxide (Al 2 O 3 ), Y oxide (Y 2 O 3 ), or a combination thereof. In some embodiments, the material of the high-K dielectric  380  is selected from a group consisting of SiON, Ta 2 O 5 , Al 2 O 3 , nitrogen-content oxide layer, nitrided oxide, metal oxide dielectric, Hf-content oxide, Ta-content oxide, Ti-content oxide, Zr-content oxide, Al-content oxide, La-content oxide or a combination thereof. 
     The conductive line  230   l  is formed in the ILD layer  350 . The gate electrode  220   e  is electrically connected to the conductive line  230   l  through the via  260   b  without any contact, thus the gate region of the NMOS transistor N 1  is electrically connected to the conductive line  230   l.    
     For the NMOS transistor N 1 , the channel region CH-N 1  is formed between the N-type doping regions  360   d  and  360   e  and under the gate electrode  220   e . For the NMOS transistor N 2 , the channel region CH-N 2  is formed between the N-type doping regions  360   e  and  360   f  and under the gate electrode  220   f . Furthermore, the dummy gate dielectrics  270   a  and  270   b  are located upon the edge of the semiconductor fin  210   h . For example, the dummy gate dielectric  270   a  is arranged upon the left edge of the semiconductor fin  210   h , and the dummy gate dielectric  270   b  is arranged upon the right edge of the semiconductor fin  210   h.    
       FIG.  7 A  illustrates a memory cell  30 A, in accordance with some embodiments of the disclosure. In this embodiment, the memory cell  30 A is a single-port SRAM bit cell. The memory cell  30 A includes a pair of cross-coupled inverters Inverter- 1  and Inverter- 2 , and two pass-gate transistors PG- 1  and PG- 2 . The inverters Inverter- 1  and Inverter- 2  are cross-coupled between the nodes  712  and  710 , and form a latch circuit. The pass-gate transistor PG- 1  is coupled between a bit line BL and the node  712 , and the pass-gate transistor PG- 2  is coupled between a complementary bit line BLB and the node  710 , wherein the complementary bit line BLB is complementary to the bit line BL. The gates of the pass-gate transistors PG- 1  and PG- 2  are coupled to the same word-line WL. Furthermore, the pass-gate transistors PG- 1  and PG- 2  are NMOS transistors. 
       FIG.  7 B  is a simplified diagram of the memory cell  30 A in  FIG.  7 A , in accordance with some embodiments of the disclosure. The inverter Inverter- 1  includes a pull-up transistor PU- 1  and a pull-down transistor PD- 1 . The pull-up transistor PU- 1  is a PMOS transistor, and the pull-down transistor PD- 1  is an NMOS transistor. The drain of the pull-up transistor PU- 1  and the drain of the pull-down transistor PD- 1  are coupled to the node  712  connecting the pass-gate transistor PG- 1 . The gates of the pull-up transistor PU- 1  and the pull-down transistor PD- 1  are coupled to the node  710  connecting the pass-gate transistor PG- 2 . Furthermore, the source of the pull-up transistor PU- 1  is coupled to the power supply VDD, and the source of the pull-down transistor PD- 1  is coupled to a ground VSS. 
     Similarly, the inverter Inverter- 2  includes a pull-up transistor PU- 2  and a pull-down transistor PD- 2 . The pull-up transistor PU- 2  is a PMOS transistor, and the pull-down transistor PD- 2  is an NMOS transistor. The drains of the pull-up transistor PU- 2  and the pull-down transistor PD- 2  are coupled to the node  710  connecting the pass-gate transistor PG- 2 . The gates of the pull-up transistor PU- 2  and the pull-down transistor PD- 2  are coupled to the node  712  connecting the pass gate transistor PG- 1 . Furthermore, the source of the pull-up transistor PU- 2  is coupled to the power supply VDD, and the source of the pull-down transistor PD- 2  is coupled to the ground VSS. 
     In some embodiments, the pass-gate transistors PG- 1  and PG- 2 , the pull-up transistors PU- 1  and PU- 2 , and the pull-down transistors PD- 1  and PD- 2  of the SRAM cell  10  are fin field effect transistors (FinFETs). 
     In some embodiments, the pass-gate transistors PG- 1  and PG- 2 , the pull-up transistors PU- 1  and PU- 2 , and the pull-down transistors PD- 1  and PD- 2  of the SRAM cell  10  are planar MOS devices. 
       FIG.  8    illustrates the layout of the semiconductor structure of two memory cells  30 A_ 1  and  30 A_ 2 , in accordance with some embodiments of the disclosure. In this embodiment, the memory cells  30 A_ 1  and  30 A_ 2  are single-port SRAM bit cells of  FIGS.  7 A and  7 B . In this embodiment, the two adjacent memory cells  30 A_ 1  and  30 A_ 2  are arranged in mirror symmetry along the X-direction. In some embodiments, the two adjacent memory cells  30 A_ 1  and  30 A_ 2  are arranged in mirror symmetry along the Y-direction. 
     An N-type well region NW 3  is at the middle of memory cells  30 A_ 1  and  30 A_ 2 , and two P-type well regions PW 3  and PW 4  are on opposite sides of N-type well region NW 3 . A gate electrode  220 _ 1  forms the pull-up transistor PU- 1  with an underlying semiconductor fin  220 _ 2  over the N-type well region NW 3 . The gate electrode  2201  may be disposed over and extend along the sidewalls of the semiconductor fin  220 _ 2 . The gate electrode  220 _ 1  further forms the pull-down transistor PD- 1  with the underlying semiconductor fin  210 _ 1  in P-type well region PW 3  (e.g., on the left side of N-type well region NW 3 ). In other words, the gate electrode  220 _ 1  is shared by the pull-up transistor PU- 1  and the pull-down transistor PD- 1 . The gate electrode  220 _ 1  may be disposed over and extend along the sidewalls of the semiconductor fin  210 _ 1 . 
     The gate electrode  220 _ 2  forms the pass-gate transistor PG- 1  with the semiconductor fin  210 _ 1 . In other words, the semiconductor fin  210 _ 1  is shared by the pass-gate transistor PG- 1  and the pull-down transistor PD- 1 . In some embodiments, the gate electrode  220 _ 2  is disposed over and extends along the sidewalls of the semiconductor fin  210 _ 1 . 
     The gate electrode  220 _ 3  forms the pull-up transistor PU- 2  with an underlying semiconductor fin  210 _ 3  over the N-type well region NW 3 . The gate electrode  220 _ 3  further forms the pull-down transistor PD- 2  with an underlying semiconductor fin  210 _ 4  in the P-type well region PW 4  (e.g., on the right side of the N-type well region NW 3 ). In other words, the gate electrode  220 _ 3  is shared by the pull-up transistor PU- 2  and the pull-down transistor PD- 2 . The gate electrode  220 _ 3  may be disposed over and extend along the sidewalls of the semiconductor fin  210 _ 4 . 
     Gate electrode  220 _ 4  forms the pass-gate transistor PG- 2  with the underlying semiconductor fin  210 _ 4 . In other words, the semiconductor fin  210 _ 4  is shared by the pass-gate transistor PG- 2  and the pull-down transistor PD- 2 . In some embodiments, the gate electrode  220 _ 4  is disposed over and extends along the sidewalls of the semiconductor fin  210 _ 4 . 
     As described above, the pass-gate transistors PG- 1  and PG- 2 , the pull-up transistors PU- 1  and PU- 2 , and the pull-down transistors PD- 1  and PD- 2  are FinFETs, and the semiconductor fins  210 _ 1  through  2104  include one or more fin structures. In some embodiments, one or more of the pass-gate transistors PG- 1  and PG- 2 , the pull-up transistors PU- 1  and PU- 2 , and the pull-down transistors PD- 1  and PD- 2  are planar MOS devices having semiconductor fins doped in an upper surface of a semiconductor substrate. The semiconductor fins  210 _ 1  through  2104  provide source/drains of various transistors on opposing sides of a respective gate electrode. 
       FIG.  8    illustrates a single fin for each of the semiconductor fins  210 _ 1  through  210 _ 4 . In some embodiments, there may be a single fin, two fins, three fins, or more for the semiconductor fins  210 _ 1  through  2104 , and the number of fins in the semiconductor fins  210 _ 1  through  2104  may be the same or different as other semiconductor fins in the memory cells  30 A_ 1  and  30 A_ 2 . 
     In  FIG.  8   , the contact  240 _ 5  is a longer contact, and is elongated and has a longitudinal direction in the X direction, which is parallel to the extending directions of the gate electrodes  220 _ 1  and  220 _ 3 . The contact  242 _ 2  is a butt contact, and includes a portion over, and electrically connected to, the gate electrode  220 _ 1 . In some embodiments, the contact  242 _ 2  has a longitudinal direction in the Y direction, which is perpendicular to the X direction. In the manufacturing of the memory cell  30 A_ 1  on the semiconductor wafers, the contact  240 _ 5  and the contact  2422  may be formed as a single continuous butt contact. 
     The contact  240 _ 2  is a longer contact, and is elongated and has a longitudinal direction in the X direction. The contact  242 _ 1  is a butt contact, and includes a portion over, and electrically connected to, the gate electrode  220 _ 3 . In such embodiments, the details of the contact  242 _ 1  and the contact  240 _ 2  may be similar to the contact  242 _ 2  and the contact  240 _ 5 , respectively, and are not repeated herein for simplicity. 
     The gate contacts  245 _ 1  and  245 _ 2  are connected to the gate electrodes  220 _ 2  and  2204 , respectively. The gate contacts  245 _ 1  and  245 _ 2  may be used to electrically couple the gate electrodes  220 _ 2  and  220 _ 4  to one or more word-line WL as described in greater detail below. 
     The contacts  240 _ 1  and  240 _ 8  are used to connect to the source regions of the pull-down transistors PD- 1  and PD- 2  to the VSS lines (e.g., the electrical ground lines). The contacts  240 _ 1  and  240 _ 8  have lengthwise directions parallel to the X direction, and may be formed to overlap the corners of the memory cells  30 A_ 1  and  30 A_ 2 . Furthermore, the contacts  240 _ 1  and  2408  may further extend into neighboring memory cells  30 A in a different column adjacent the memory cell  30 A. The contacts  240 _ 1  and  240 _ 8  may further be shared between two neighboring memory cells  30 A in the adjacent rows. 
     The contacts  240 _ 3  and  240 _ 7  are used to connect to the source regions of pull-up transistors PU- 1  and PU- 2  to the VDD lines (e.g., supply voltage lines). The contacts  240 _ 3  and  2407  may further be shared between two neighboring memory cells  30 A in the adjacent rows. For example, the contact  240 _ 7  is shared between two neighboring memory cells  30 A_ 1  and  30 A_ 2  in the adjacent rows for the pull-up transistors PU- 2 . 
     Additionally, the contact  240 _ 6  is used to connect to the source/drain region of pass-gate transistor PG- 1  to a bit line BL through a via  250 _ 4 . The contact  240 _ 4  is used to connect to the source/drain region of pass-gate transistor PG- 2  to a complementary bit line BLB through a via  250 _ 3 . 
     The vias  255 _ 1  and  255 _ 2  are connected to the gate contacts  245 _ 1  and  245 _ 2  (e.g., the gate contacts for pass-gate transistors PG- 1  of PG- 2 ). The vias  255 _ 1  and  255 _ 2  are further connected to the conductive lines  230 _ 2  and  2306 , which may be used to electrically couple gate electrodes of the pass gate transistors PG- 1  and PG 2  to one or more word lines WL. The vias  255 _ 1  and  255 _ 2  and the conductive lines  230 _ 2  and  230 _ 6  may further extend into and shared with neighboring memory cells  30 A in the adjacent columns. 
     Furthermore, the vias  250 _ 1  and  250 _ 6  are connected to the source/drain contacts  240 _ 1  and  240 _ 8  (e.g., the source contacts of the pull-down transistors PD- 1  and PD- 2 ), respectively. The vias  250 _ 1  and  250 _ 6  are further connected to the conductive lines  230 _ 1  and  230 _ 7 , respectively, and the vias  250 _ 1  and  250 _ 6  may be used to electrically couple sources of the pull-down transistors PD- 1  and PD 2  to the VSS lines. Furthermore, the vias  250 _ 1  and  250 _ 6  and the conductive lines  230 _ 1  and  2307  may further extend into neighboring memory cells  30 A in the adjacent columns. The vias  250 _ 1  and  250 _ 6  and the conductive lines  230 _ 1  and  230 _ 7  may be shared between two neighboring memory cells  30 A in different rows. 
     In some embodiments, each of the vias  250 _ 1  through  2506  and the vias  255 _ 1  and  255 _ 2  includes a metal plug made of the same material. In some embodiments, the material of the metal plug is purely W (Tungsten) or purely Ru (Ruthenium) without sidewall barrier layer metal. In some embodiments, the material of the metal plug is selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. 
     In some embodiments, each of the contacts  250 _ 1  through  250 _ 6  and the vias  255 _ 1  and  255 _ 2  includes a metal plug made of the same material. In some embodiments, the material of the metal plug is selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. In some embodiments, the contacts  240   g  through  2401  are slot-shaped. 
       FIG.  9 A  illustrates a cross-sectional view of the semiconductor structure of the memory cell  30 A_ 1  along line F-FF in  FIG.  8   , in accordance with some embodiments of the disclosure. The P-type well regions PW 3  and PW 4  and the N-type well region NW 3  are formed over a substrate  310 . In some embodiments, the substrate  310  is a Si substrate. In some embodiments, the material of the substrate  310  is selected from a group consisting of bulk-Si, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-VI material, or a combination thereof. 
     The semiconductor fins  210 _ 2  and  210 _ 3  are formed on the N-type well region NW 3 . In some embodiments, the semiconductor fins  210 _ 2  and  210 _ 3  include an appropriate concentration of n-type dopants (e.g., phosphorous (such as  31 P), arsenic, or a combination thereof). The semiconductor fins  210 _ 2  and  210 _ 3  are separated from each other by the shallow trench isolation (STI)  320 . 
     The semiconductor fins  210 _ 1  and  210 _ 4  are formed on the P-type well regions PW 3  and PW 4 , respectively. In some embodiments, the semiconductor fins  210 _ 1  and  210 _ 4  include an appropriate concentration of P-type dopants (e.g., boron (such as 11B), boron, boron fluorine (BF2), or a combination thereof). Furthermore, the semiconductor fins  210 _ 1  and  210 _ 4  are separated from each other by the STI  320 . 
     The gate electrode  220 _ 2  is formed over the gate dielectrics  335  and is positioned over a top surface of the semiconductor fin  210 _ 1 . The semiconductor fin  210 _ 1  overlapping the gate electrode  2202  may serve as a channel region of the pass-gate transistor PG- 1 . Thus, the gate electrode  220 _ 2  and the gate dielectrics  335  over the semiconductor fin  210 _ 1  form a gate structure for the pass-gate transistor PG- 1 . The semiconductor fin  210 _ 3  overlapping the gate electrode  2203  may serve as a channel region of the pull-up transistor PU- 2 . Thus, the gate electrode  220 _ 3  and the gate dielectrics  335  over the semiconductor fin  210 _ 3  form a gate structure for the pull-up transistor PU- 2 . The semiconductor fin  210 _ 4  overlapping the gate electrode  2203  may serve as a channel region of the pull-down transistor PD- 2 . Thus, the gate electrode  220 _ 3  and the gate dielectrics  335  over the semiconductor fin  210 _ 4  form a gate structure for the pull-down transistor PD- 2 . In some embodiments, the spacers  330  are formed on opposite sides of the gate electrode  220 _ 3 . Furthermore, the gate electrode  220 _ 2  and  220 _ 3  are separated by the spacer  330 . 
     ILD layer  340  is formed over the gate electrodes  220 _ 2  and  220 _ 3  and the spacer  330 . The ILD layer  340  may be formed of an oxide such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like. 
     The contacts  245 _ 1  and  242 _ 1  are formed in the ILD layer  340 . Furthermore, the contact  245 _ 1  is disposed over the gate electrode  220 _ 2  and does not overlap the semiconductor fin  210 _ 1 . In other words, projection of the contact  245 _ 1  does not overlap the projections of the semiconductor fin  210 _ 1  on the substrate  310 , i.e. the projections of the contact  245 _ 1  and the semiconductor fin  210 _ 1  are separated on the substrate  310 . Moreover, the contact  2421  is disposed over the gate electrode  220 _ 3  and does not overlap the semiconductor fins  210 _ 3  and  210 _ 4 . In other words, projection of the contact  242 _ 1  does not overlap the projections of the semiconductor fins  210 _ 3  and  210 _ 4  on the substrate  310 , i.e. the projections of the contact  242 _ 1  and the semiconductor fins  210 _ 3  and  210 _ 4  are separated on the substrate  310 . 
     IMD layer  350  is formed over the ILD layer  340 . The via  255 _ 1  and the conductive lines  2302  through  230 _ 5  and  230 _ 7  are formed in the IMD layer  350 . In some embodiments, the conductive lines  230 _ 2  through  230 _ 5  and  230 _ 7  are metal lines formed in the same metal layer. The gate electrode  220 _ 2  is electrically connected to the conductive line  230 _ 2  through the contact  245 _ 1  and the via  255 _ 1 , thus the gate region of the pass-gate transistor PG- 1  is electrically connected to the conductive line  230 _ 2 . 
     In some embodiments, the via  255 _ 1  includes a metal plug made of the same material. In some embodiments, the material of the metal plug is purely W (Tungsten) or purely Ru (Ruthenium) without sidewall barrier layer metal. In some embodiments, the material of the metal plug is selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. 
     In some embodiments, the contacts  245 _ 1  and  242 _ 1  include a metal plug made of the same material. In some embodiments, the material of the metal plug is selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. 
       FIG.  9 B  illustrates a cross-sectional view of the semiconductor structure of the memory cells  30 A_ 1  and  30 A_ 2  along line G-GG in  FIG.  8   , in accordance with some embodiments of the disclosure. The N-type well region NW 3  is formed over the substrate  310 . The semiconductor fin  210 _ 3  is formed on the N-type well region NW 3 , and is surrounded by the STI  320 . 
     The ILD  340  is formed over the STI  320 . The P-type doping regions  365 _ 1  through  365 _ 3  form the source/drain regions on the semiconductor fin  210 _ 3 . The source/drain silicide regions  370 _ 1  through  3703  are formed on the P-type doping regions  365 _ 1  through  3653 , respectively. The contacts  240 _ 5  and  240 _ 7  of the memory cells  30 A_ 1  and  30 A_ 2  are formed on the source/drain silicide regions  370 _ 1  through  370 _ 3 , respectively. Each of the contacts  240 _ 5  and  240 _ 7  includes a metal plug  385  and a high-K dielectric  380  formed on the sidewall of the metal plug  385 . In other words, the metal plug  385  is surrounded by the high-K dielectric  380 . Furthermore, the contacts  240 _ 5  and the contact  2422  may be formed as a single continuous butt contact. 
     In some embodiments, the dielectric constant of the high-K dielectric  380  is greater than 4.9 or 5. In some embodiments, the thickness of the high-K dielectric  380  is within a range of 5 to 50 Å, where Å=10 −10  m. In some embodiments, the material of the high-K dielectric  380  is selected from a group consisting of a nitride-based dielectric, a metal oxide dielectric, Hf oxide (HfO 2 ), Ta oxide (Ta 2 O 5 ), Ti oxide (TiO 2 ), Zr oxide (ZrO 2 ), Al oxide (Al 2 O 3 ), Y oxide (Y 2 O 3 ), or a combination thereof. In some embodiments, the material of the high-K dielectric  380  is selected from a group consisting of SiON, Ta 2 O 5 , Al 2 O 3 , nitrogen-content oxide layer, nitrided oxide, metal oxide dielectric, Hf-content oxide, Ta-content oxide, Ti-content oxide, Zr-content oxide, Al-content oxide, La-content oxide or a combination thereof. 
     The via  250 _ 5  and the conductive line  230 _ 4  are formed in the ILD layer  350 . The P-type doping region  3652  is electrically connected to the conductive line  230 _ 4  through the via  250 _ 5 , the contact  240 _ 7  and the source/drain silicide region  370 _ 2 , thus the source regions of the pull-up transistors PU- 2  of the memory cells  30 A_ 1  and  30 A_ 2  are electrically connected to the conductive line  230 _ 4 . 
       FIG.  9 C  illustrates another cross-sectional view of the semiconductor structure of the memory cells  30 A_ 1  and  30 A_ 2  along line G-GG in  FIG.  8   , in accordance with some embodiments of the disclosure. Compared with contact  240 _ 5  and contact  242 _ 2  in  FIG.  9 B  that are formed as a single continuous butt contact, contact  240 _ 5  and contact  242 _ 2  in  FIG.  9 C  are formed in sequence. 
     Embodiments for semiconductor structures are provided. In an IC, various connection structures are used to connect the source and drain regions and the gate electrodes of the transistors to the conductive line (e.g., the first level metallization layer). By using the via to directly connect the gate electrode without the contact, routing efficiency and logic circuit density improvement are increased for the standard cells in the IC. 
     In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first logic cell and a second logic cell. The first logic cell includes a plurality of first transistors over a substrate. At least one of the first transistors includes a first gate electrode across a first channel region. The first gate electrode is electrically connected to a first conductive line in a first dielectric layer through a first contact in a second dielectric layer and a first via in the first dielectric layer. The second logic cell includes a plurality of second transistors over the substrate. At least one of the second transistors includes a second gate electrode across a second channel region, wherein the second gate electrode is electrically connected to a second conductive line in the first dielectric layer through a second via. The first dielectric layer is formed over the second dielectric layer, and the second via extends from the second conductive line to the second gate electrode and penetrates the first and second dielectric layers. 
     In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a logic cell and a memory cell. The logic cell includes a first transistor. The first transistor includes a first gate electrode across a first semiconductor fin over a first well region. The first gate electrode is electrically connected to a first conductive line of a metal layer through a first via. The memory cell includes a second transistor. The second transistor includes a second gate electrode across a second semiconductor fin over a second well region. The second gate electrode is electrically connected to a second conductive line through a first contact and a second via over the first contact. Thickness of the first via is greater than thicknesses of the first contact and the second via. 
     In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first circuit and a second circuit. The first circuit includes a plurality of first logic cells. A first transistor of each of the first logic cells includes a first gate electrode across a first semiconductor fin. The first gate electrode is electrically connected to a first conductive line of a metal layer through a first contact and a first via over the first contact. The second circuit includes a plurality of second logic cells. A second transistor of each of the second logic cells includes a second gate electrode across a second semiconductor fin. The second gate electrode is electrically connected to a second conductive line of the metal layer through a second via. The first and second logic cells have the same logic function. The second via is thicker than the first via and the first contact. 
     The foregoing outlines nodes of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.