Patent Publication Number: US-2003227039-A1

Title: Solid-state image pickup device

Description:
[0001] This application claims priority to Japanese Patent Application Number JP2002-058502 filed Mar. 5, 2002, which is incorporated herein by reference.  
       [0002] This invention relates to a solid-state image pickup device wherein each of a plurality of pixels which form an image pickup region includes a photoelectric conversion element and at least one or more transistors which form a readout circuit for signal charge of the photoelectric conversion element. More particularly, the present invention is directed to improvements in a gate portion of the transistors.  
       RELATED ART  
       [0003] A CMOS type solid-state image pickup device is conventionally known which has an image pickup region in which pixels are disposed two-dimensionally on a semiconductor substrate and includes, for each of the pixels, a photodiode (PD) serving as a photoelectric conversion element, a transfer transistor for transferring signal charge produced by the photodiode to a floating diffusion portion (hereinafter referred to as FD portion), an amplification transistor for detecting an amount of the signal charge transferred to the floating diffusion portion and converting the signal charge amount into an electric signal, a selection transistor for selectively signaling an output of the amplification transistor to an output signal line, a reset transistor for resetting the signal charge of the floating diffusion portion, and so forth.  
       [0004]FIG. 17 is a plan view showing an example (first conventional example) of an arrangement of elements around a photodiode in a pixel in such a conventional solid-state image pickup device as described above.  
       [0005] As shown in FIG. 17, a photodiode  10  and a FD portion  12  are disposed in parallel to each other with a transfer gate portion  14  interposed therebetween. A transfer electrode (TG)  14 A is disposed above the transfer gate portion  14 , and an end portion of the transfer electrode  14 A is connected to an upper wiring line (not shown) through a contact  14 B.  
       [0006] In such an element arrangement as described above, if a predetermined voltage is applied to the transfer electrode  14 A, then signal charge of the photodiode  10  is read out to the FD portion  12  side through a channel region of the transfer gate portion  14 .  
       [0007] Meanwhile, FIGS. 18A and 18B are sectional views showing an element structure in a semiconductor substrate in the element arrangement shown in FIG. 17.  
       [0008] As shown in FIGS. 18A and 18B, a P type well region  22  is formed on a semiconductor substrate (N type silicon substrate)  20 , and the photodiode  10  is formed from a P+ layer  10 A of an upper layer and an N layer  10 B of a lower layer.  
       [0009] Further, the FD portion  12  is formed as an N+ region at a position spaced by a predetermined distance from the photodiode  10 .  
       [0010] The P type region between the photodiode  10  and the FD portion  12  forms the transfer gate portion  14 , and the transfer electrode  14 A is disposed on an upper face of the transfer gate portion  14 .  
       [0011] It is to be noted that an element isolation region  16  formed from LOCOS or the like is provided around the pixel so that the pixel is electrically isolated from adjacent pixels.  
       [0012] Here, in a state wherein a Low voltage is applied to the transfer electrode  14 A to control the transfer gate portion  14  to an OFF state, no channel is formed below the transfer electrode  14 A as shown in FIG. 18A, but the portion below the transfer electrode  14 A remains as P type.  
       [0013] Then, when a power supply voltage is applied to the transfer electrode  14 A to turn the transfer gate portion  14  ON, signal charge  18  accumulates below the transfer electrode  14 A as shown in FIG. 17B to form an N type channel.  
       [0014]FIG. 19 is a plan view showing another example (second conventional example) of an arrangement of pixels around a photodiode in a pixel in a conventional solid-state image pickup device (refer to the paper “An Image Sensor with a Simple FPN-reduction Technology and a Hole Accumulated Diode”, ISSCC, (2000)).  
       [0015] In this example, a FD portion  32  is arranged at an oblique position with respect to a photodiode  30 , and a transfer gate portion  34  and a transfer gate  34 A are arranged in a right-angularly bent state in such a manner that it surrounds two side faces of the FD portion  32 .  
       [0016] It is to be noted that an end portion of the transfer gate  34 A is connected to an upper wiring line (not shown) through a contact  34 B.  
       [0017] Also in such an element arrangement as just described, if a predetermined voltage is applied to the transfer gate  34 A, then signal charge of the photodiode  30  is read out to the FD portion  32  side through a channel region of the transfer gate portion  34 .  
       [0018] Incidentally, in the first conventional example described above, the channel region of the transfer gate portion  14  has a single gate length (L shown in FIG. 17) (that is, the width in the gate lengthwise direction of the transfer electrode  14 A).  
       [0019] However, in the case of such a transfer electrode as described above, since the gate length by the transfer electrode  14 A is small, the modulation degree of the transfer electrode  14 A is low, and therefore, the potential in a region below the transfer electrode  14 A when an applied voltage is turned ON remains low.  
       [0020] Therefore, even if the transfer electrode  14 A is turned ON, since the potential in the region below the transfer electrode  14 A is lower than the potential of the photodiode, transfer residual wherein signal charge remains in the photodiode occurs.  
       [0021] In other words, full transfer of the signal charge from the photodiode to the FD portion is less likely to occur.  
       [0022] On the contrary if the gate length is great, then in light of the fact that the modulation degree is high, the potential in the region below the transfer electrode when the applied voltage is turned ON can be made high.  
       [0023] Thus, while it is possible to generally increase the width (L1) in the gate widthwise direction of the transfer electrode, only if the width is increased simply, then the numerical aperture of the photodiode decreases and also the saturation signal charge amount decreases (if it is tried to conversely keep the numerical aperture equal, then the device area increases). Particularly with a fine pixel size, a drop of the saturation signal charge amount is a significant problem.  
       [0024] Thus, a technique for increasing the degree of modulation of the transfer electrode while reduction of the area of the photodiode is suppressed has been demanded.  
       [0025] The conventional example shown in FIG. 19 solves such a goal as just described and increases the width in the gate lengthwise direction by forming the transfer electrode such that it has a graphic shape bent at the right angle. In such a transfer electrode as just described, the gate length is equal to {square root}2 times L1, from the theory of right-angled triangle.  
       [0026] However, it is estimated that, as a result of actual lithographic processing, the graphic shape of a corner portion is rounded and the gate length of the corner portion becomes substantially equal to L1.  
       [0027] Further, in the structure of the second conventional example, since the portion having the gate length L1′ is influenced by the opposite sides thereof, some width is required as the gate width of the portion of the increased gate length.  
       [0028] It is to be noted that a similar problem arises not only with a transfer gate but also with other transistors which form a readout circuit in the pixel, for example, a reset gate and so forth.  
       [0029] It is therefore an object of the present invention to provide a solid-state image pickup device which can suppress the influence upon the numerical aperture of a photoelectric conversion element to the minimum and effectively controls the potential at a gate portion of a transfer transistor or a reset transistor to eliminate residual charge by an insufficient degree of potential modulation. Other objects and advantages of the present invention will be apparent in light of the following summary and detailed description.  
       SUMMARY OF THE INVENTION  
       [0030] This invention relates to a solid-state image pickup device having a plurality of pixels comprised of a photoelectric conversion element, a transistor formed within said pixel, wherein a gate electrode of said transistor is comprised of structures having a plurality of different widths.  
       [0031] Furthermore, this invention relates to a solid-state image pickup device comprised of a photoelectric conversion portion, a first transistor connected to said photoelectric conversion portion, a second transistor connected to said first transistor, a third transistor connected to a node between said first and second transistors, and wherein at least a gate electrode of one of said first, second and third transistors has a convex or protruding portion.  
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0032]FIG. 1 is a circuit diagram showing an example of a pixel portion for an image pickup device;  
     [0033]FIG. 2 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a first exemplary embodiment of the present invention;  
     [0034]FIGS. 3A and 3B are sectional views showing an element structure in a semiconductor substrate in the element arrangement shown in FIG. 2;  
     [0035]FIG. 4 is a diagram illustrating the modulation degree of a solid-state image pickup device which has the element arrangement shown in FIG. 2 in comparison with that of a conventional example;  
     [0036]FIG. 5 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a second exemplary embodiment of the present invention;  
     [0037]FIG. 6 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a third exemplary embodiment of the present invention;  
     [0038]FIG. 7 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a fourth exemplary embodiment of the present invention;  
     [0039]FIG. 8 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a fifth exemplary embodiment of the present invention;  
     [0040]FIG. 9 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a sixth exemplary embodiment of the present invention;  
     [0041]FIG. 10 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a seventh exemplary embodiment of the present invention;  
     [0042]FIG. 11 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to an eighth exemplary embodiment of the present invention;  
     [0043]FIGS. 12A and 12B are sectional views showing an element structure in a semiconductor substrate in the element arrangement shown in FIG. 11;  
     [0044]FIG. 13 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a ninth exemplary embodiment of the present invention;  
     [0045]FIG. 14 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a tenth exemplary embodiment of the present invention;  
     [0046]FIG. 15 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to an eleventh exemplary embodiment of the present invention;  
     [0047]FIG. 16 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a twelfth exemplary embodiment of the present invention;  
     [0048]FIG. 17 is a plan view showing an example (first conventional example) of an arrangement of elements around a photodiode in a pixel in a conventional solid-state image pickup device;  
     [0049]FIGS. 18A and 18B are sectional views showing an element structure in a semiconductor substrate in a solid-state image pickup device having the element arrangement shown in FIG. 17; and  
     [0050]FIG. 19 is a plan view showing another example (second conventional example) of an arrangement of elements around a photodiode in a pixel in a conventional solid-state image pickup device. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EXEMPLARY EMBODIMENTS  
     [0051] Various exemplary embodiments of a solid-state image pickup device according to the present invention are described.  
     [0052] It is to be noted that, while the embodiments described below are preferred embodiments of the present invention and the description including various technical details, the scope of the present invention is not limited by the exemplary embodiments unless it is recited in the following description that the present invention is so limited.  
     [0053] As shown in FIG. 1, in the present embodiments, a CMOS type solid-state image pickup device wherein a semiconductor substrate has an image pickup region  11  in which unit pixels  10  are arranged two-dimensionally and each of the pixels has a photodiode  1  (PD) serving as a photoelectric conversion element, a transfer transistor  3  (transfer gate portion) for transferring signal charge produced by the photodiode to a floating diffusion portion  2  (hereinafter referred to as FD portion), an amplification transistor  4  for detecting an amount of the signal charge transferred to the FD portion and converting the signal charge amount into an electric signal, a selection transistor  5  for selectively signaling an output of the amplification transistor to an output signal line, a reset transistor  6  for resetting the signal charge of the FD portion and so forth is configured such that a transfer gate (TG) of the transfer gate portion provided in each of the pixels in the image pickup region is partially expanded in the gate lengthwise direction to increase the modulation degree by the transfer electrode and to increase the channel potential below the transfer electrode when the transfer is ON thereby to make it possible to read out the signal charge of the photodiode (PD) by complete transfer.  
     [0054]FIG. 2 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a first embodiment of the present invention.  
     [0055] As shown in FIG. 2, a photodiode  110  and a FD portion  112  are arranged in parallel to each other with a transfer gate portion  114  interposed therebetween. A transfer electrode  114 A formed from a polycrystalline silicon film is arranged above the transfer gate portion  114 , and an end portion of the transfer electrode  114 A is connected to an upper wiring line (not shown) through a contact  114 B.  
     [0056] The transfer electrode  114 A in the present example includes a body portion  114 A 1  and an expanded portion  114 A 2  extending to the photodiode  110  side and formed integrally with the body portion  114 A 1 .  
     [0057] Each of the body portion  114 A 1  and the expanded portion  114 A 2  is formed in a straight belt-like configuration, and the expanded portion  114 A 2  is provided at a portion approximately one half of the transfer electrode  114 A in the gate widthwise direction. The width of the transfer electrode  114 A in the gate lengthwise direction is, at a portion thereof at which the expanded portion  114 A 2  is not provided, L1 of the body portion  114 A 1 , but is expanded, at another portion at which the expanded portion  114 A 2  is provided, to L2.  
     [0058] It is to be noted that, while the body portion  114 A 1  and the expanded portion  114 A 2  are shown distinctly from each other in FIG. 1, actually they are formed from a polycrystalline silicon electrode film of the same layer and an equal driving voltage is applied to them.  
     [0059] In such an element arrangement as described above, if a predetermined voltage is applied to the transfer electrode  114 A, then signal charge of the photodiode  110  is read out to the FD portion  112  side through a channel region of the transfer gate portion  114 .  
     [0060]FIGS. 3A and 3B are sectional views showing an element structure in a semiconductor substrate in the element arrangement shown in FIG. 2.  
     [0061] As shown in FIGS. 3A and 3B, a P type well region  122  is formed on a semiconductor substrate (N type silicon substrate)  120 , and the photodiode  110  is formed from a P+ layer  110 A of an upper layer and an N layer  110 B of a lower layer.  
     [0062] Further, the FD portion  112  is formed as an N+ region at a position spaced by a predetermined distance from the photodiode  110 .  
     [0063] The P type region between the photodiode  110  and the FD portion  112  is formed as the transfer gate portion  114 , and the transfer electrode  114 A is arranged on an upper face of the transfer gate portion  114 .  
     [0064] It is to be noted that an element isolation region  116  made of LOCOS or the like is provided around the pixel so that the pixel is electrically isolated from adjacent pixels.  
     [0065] Here, in a state wherein a Low voltage is applied to the transfer electrode  114 A to place the transfer gate portion  114  to an OFF state, no channel is formed below the transfer electrode  114 A as shown in FIG. 3A, but the portion below the transfer electrode  114 A remains in the P type.  
     [0066] Then, if a power supply voltage is applied to the transfer electrode  114 A to turn the transfer gate portion  114  to an ON state, then signal charge  118  accumulates at a portion below the transfer electrode  114 A to form an N type channel as shown in FIG. 3B.  
     [0067] In the present example, the gate length is increased by such a transfer electrode  114 A which has the expanded portion  114 A 2  part thereof as described above.  
     [0068] Operation when the voltage is applied is described specifically herein.  
     [0069] 1. First, a power supply voltage is applied to the transfer electrode  114 A.  
     [0070] 2. Consequently, N type charge is produced at a surface portion (P type) of the FD portion  112  corresponding to the transfer electrode  114 A, that is, the transfer gate portion  114 .  
     [0071] 3. Signal charge accumulates at the surface portion (N type) corresponding to the transfer electrode  114 A.  
     [0072] 4. A modulation difference occurs simultaneously with the production of the N type and the accumulation of signal charge.  
     [0073] 5. Simultaneously when the modulation difference occurs, the signal charge having been in the photodiode (P type)  110  flows into the FD portion (N+ type)  112  through the transfer electrode  114 A (N− type).  
     [0074] In such operation as described above, where the partial expanded portion  114 A 2  is provided for the transfer electrode  114 A, it is possible to increase the modulation degree of the transfer electrode  114 A while decreasing the amount of reduction of the area of the light reception portion of the photodiode  110  (while increasing the numerical aperture). As a result, a solid-state image pickup device with which transfer residual is less likely to occur and which is suitable for full transfer can be configured.  
     [0075]FIG. 4 is a diagram illustrating the modulation degree by the solid-state image pickup device of the present embodiment having such a configuration as described above in comparison with that of the conventional example. The axis of abscissa indicates the gate voltage (V), and the axis of ordinate indicates the potential voltage (V).  
     [0076] As seen in FIG. 4, with the solid-state image pickup device of the present embodiment indicated by a solid line a, a steep potential variation can be obtained with a low gate voltage when compared with the conventional example indicated by a broken line b.  
     [0077]FIG. 5 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a second embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0078] The solid-state image pickup device of the present example is configured such that a FD portion  112  is arranged at an oblique position with respect to a photodiode  110  and a transfer electrode  130 A of a transfer electrode portion  130  is arranged in an oblique direction.  
     [0079] Further, the transfer electrode  130 A in the present example includes a body portion  130 A 1  and an expanded portion  130 A 2  each formed in a straight belt-like configuration and provided integrally with each other, and the expanded portion  130 A 2  is provided at a portion approximately one half of the body portion  130 A 1 . It is to be noted that an end portion of the body portion  130 A 1  of the transfer electrode  130 A is connected to an upper wiring line (not shown) through a contact  130 B.  
     [0080] Also in the present example, since the expanded portion  130 A 2  is provided, the width of the transfer electrode  114 A in the gate lengthwise direction is, at a portion thereof at which the expanded portion  130 A 2  is not provided, L1 of the body portion  130 A 1 , but is expanded, at another portion thereof at which the expanded portion  130 A 2  is provided, to L2 and the modulation degree by the transfer electrode  130 A is increased.  
     [0081]FIG. 6 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a third embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0082] The solid-state image pickup device of the present embodiment is configured such that a FD portion  112  is arranged at an oblique position with respect to a photodiode  110  and a transfer electrode  140 A of a transfer electrode portion  140  is arranged in a right-angularly bent state such that it surrounds two side faces of the FD portion  112 .  
     [0083] Also in the present example, the transfer electrode  140 A has a body portion  140 A 1  and an expanded portion  140 A 2 , and the expanded portion  140 A 2  is provided integrally at an outer side corner portion of the body portion  140 A 1  bent at the right angle of 90 degrees.  
     [0084] It is to be noted that an end portion of the body portion  140 A 1  of the transfer electrode  140 A is connected to an upper wiring line (not shown) through a contact  140 B.  
     [0085] By such a configuration as described above, the width of the corner portion of the transfer electrode  140 A is expanded from “2L1 to “2L2, and the modulation degree by the transfer electrode  140 A is increased.  
     [0086]FIG. 7 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a fourth embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0087] The solid-state image pickup device of the present embodiment is configured such that two transfer electrodes  152 A and  154 A of different layers are provided for one gate portion  150  between the photodiode  110  and the FD portion  112 . The transfer electrodes  152 A and  154 A extend to a location above the gate portion  150  from the opposite sides of the gate portion  150 , and the transfer electrode  152 A arranged on the lower layer is arranged over the overall gate width while the other transfer electrode  154 A disposed on the upper layer is arranged up to an intermediate position of the gate width.  
     [0088] It is to be noted that end portions of the transfer electrodes  152 A and  154 A are connected to upper wiring lines (not shown) through contacts  152 B and  154 B, respectively.  
     [0089] As the transfer electrodes  152 A and  154 A are arranged in a state wherein they are displayed by a fixed amount in the gate lengthwise direction, the width in the gate widthwise direction is expanded from L1 in the case wherein only the transfer electrode  152 A is involved to L2 in the case wherein the two transfer electrodes  152 A and  154 A are involved, and the modulation degree by the transfer electrodes  152 A and  154 A is increased.  
     [0090]FIG. 8 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a fifth embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG.  2  are denoted by like reference characters and description thereof is omitted.  
     [0091] The solid-state image pickup device of the present embodiment is configured such that two transfer electrodes  162 A and  164 A of different layers are provided similarly as in the example shown in FIG. 7, and while the transfer electrode  162 A (of the lower layer) is similar to the transfer electrode  152 A, the other transfer electrode  164 A (of the upper layer) has a shape wherein only part thereof extends to the photodiode  110  side.  
     [0092] It is to be noted that end portions of the transfer electrodes  162 A and  164 A are connected to upper wiring lines (not shown) through contacts  162 B and  164 B, respectively.  
     [0093] Also in such a configuration as described above, the width in the gate lengthwise direction is expanded from L1 where only the transfer electrode  162 A is involved to L2 where the two transfer electrodes  162 A and  164 A are involved, and the modulation degree by the transfer electrodes  162 A and  164 A is increased.  
     [0094]FIG. 9 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a sixth embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0095] The solid-state image pickup device of the present embodiment includes a photo-gate (PG)  170  in a state (indicated by slanting lines in FIG. 9) wherein it contains part of a photodiode  110 .  
     [0096] The photo-gate  170  has a function of binning the surface potential of the photodiode  110  to suppress generation of dark current.  
     [0097] Further, a transfer gate portion  180  is provided at a side portion of the photodiode  110  on which the photo-gate  170  is not provided, and a transfer electrode  180 A similar to, for example, that in the first embodiment described hereinabove is provided on the transfer gate portion  180 .  
     [0098] In particular, the transfer electrode  180 A has a body portion  180 A 1  and an expanded portion  180 A 2 , and an end portion of the body portion  180 A 1  is connected to an upper wiring line through a contact  180 B.  
     [0099] Also with such a configuration as described above, the width in the gate lengthwise direction is expanded from L1 to L2, and the modulation degree by the transfer electrode  180 A is increased and signal charge of the photodiode  110  and the photo-gate  170  can be transferred effectively.  
     [0100]FIG. 10 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a seventh embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0101] The solid-state image pickup device of the present embodiment is configured such that an entire photodiode  110  is arranged in a state wherein it is included in a photo-gate (PG)  172  and the photo-gate  172  is disposed in a state wherein part thereof covers a channel region of a transfer gate portion  190 .  
     [0102] Further, a transfer electrode  190 A similar to, for example, that in the first embodiment described hereinabove is provided on the transfer gate portion  190  in a state wherein it is disposed on the lower side of the photo-gate  172 .  
     [0103] In particular, the transfer electrode  190 A has a body portion  190 A 1  and an expanded portion  190 A 2 , and an end portion of the body portion  190 A 1  is connected to an upper wiring line through a contact  190 B.  
     [0104] Also in such a configuration as described above, the width in the gate lengthwise direction is expanded from L1 to L2, and the degree of modulation by the transfer electrode  190 A is increased and signal charge of the photodiode  110  and the photo-gate  172  can be transferred effectively.  
     [0105] In the following, eighth to twelfth embodiments of the present invention are described.  
     [0106] The assignee of the present application has proposed, for example, in Japanese Patent Application No. 2001-340440 and so forth, a solid-state image pickup device wherein two gate electrodes of a transfer transistor and a transfer selection transistor disposed in a neighboring relationship with each other in a pixel are formed from electrode films (polycrystalline silicon films) of different layers and the two gate electrode films are arranged in a partly overlapping relationship with each other.  
     [0107] In particular, the solid-state image pickup device includes a transfer transistor  3  which is controlled with a vertical selection signal and a transfer selection transistor formed between FD 2  and the transfer transistor  3  in FIG. 1, for controlling the transfer transistor with a horizontal selection signal, and totaling five transistors including the two transistors in addition to an amplification transistor, a reset transistor and a selection transistor described hereinabove are arranged in a pixel.  
     [0108] In such a pixel configuration as described above, the two gate electrodes of the transfer transistor and the transfer selection transistor are arranged in a partly overlapping relationship with each other and channels of the two gate portions are formed continuously while the gate potentials of them are set to negative potentials with respect to well regions in the lower layer to suppress depletion of them and decrease the leak current thereby to realize a solid-state image pickup device which is reduced in noise.  
     [0109] Particularly by setting the gate potential of the transfer transistor on the photodiode side to a negative potential, leak current which has an influence on the photodiode can be suppressed.  
     [0110] Thus, in the following embodiments, examples are described wherein the configuration described hereinabove wherein the gate portion has a belt-like configuration having a plurality of widths in the gate lengthwise direction is applied to such a configuration as just described wherein two gate electrodes are arranged in a partly overlapping relationship with each other such that the characteristics of them are combined to achieve further effective operation and effects.  
     [0111]FIG. 11 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to an eighth embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0112] The solid-state image pickup device of the present embodiment is configured such that, for example, the gate electrode shown in FIG. 2 which includes a body portion and an expanded portion is applied to a gate structure of a two-layer structure of a transfer transistor and a transfer selection transistor.  
     [0113] In particular, referring to FIG. 11, a photodiode  110  and a FD portion  112  are arranged in parallel to each other with a transfer gate portion  210  interposed therebetween. Transfer electrodes  211 A and  212 A of two layers are arranged above the transfer gate portion  210 , and end portions of the transfer electrodes  211 A and  212 A are connected to upper wiring lines (not shown) through contacts  211 B and  212 B, respectively.  
     [0114] The transfer electrodes  211 A and  212 A have a same shape (or similar shapes), and the transfer electrode  211 A has a body portion  211 A 1  and an expanded portion  211 A 2  provided integrally with each other while the transfer electrode  212 A has a body portion  212 A 1  and an expanded portion  212 A 2  provided integrally with each other.  
     [0115] Such transfer electrodes  211 A and  212 A as just described are arranged in a partly overlapping relationship with each other with an insulating film interposed therebetween, and the transfer electrode  211 A of the lower layer forms a gate portion of a transfer transistor while the transfer electrode  212 A of the upper layer forms a gate portion of a transfer selection transistor.  
     [0116]FIGS. 12A and 12B are sectional views showing an element structure in a semiconductor substrate in the element arrangement shown in FIG. 11. It is to be noted that elements common to those of the example shown in FIG. 3 are denoted by like reference characters and description thereof is omitted.  
     [0117] As shown in FIGS. 12A and 12B, a P type well region  122  is formed on a semiconductor substrate (N type silicon substrate)  120 , and a photodiode  110  is formed from a P+ layer  110 A of an upper layer and an N layer  110 B of a lower layer.  
     [0118] Further, a FD portion  112  is formed as an N+ region at a position spaced by a predetermined distance from the photodiode  110 .  
     [0119] The P type region between the photodiode  110  and the FD portion  112  forms a continuous gate portion  213  of a transfer transistor and a transfer selection transistor, and transfer electrodes  211 A and  212 A are arranged on an upper face of the gate portion  213 .  
     [0120] It is to be noted that, an element isolation region  116  made of LOCOS or the like is provided around the pixel so that the pixel is electrically isolated from adjacent pixels.  
     [0121] In a state wherein a Low voltage is applied to the transfer electrodes  211 A and  212 A to place the transfer gate portion  213  to an OFF state, no channel is formed below the transfer electrodes  211 A and  212 A as shown in FIG. 12A and the portion below the transfer electrodes  211 A and  212 A remains in the P type.  
     [0122] Then, if a power supply voltage is applied to both of the transfer electrodes  211 A and  212 A to turn ON the transfer gate  213 , signal charge  118  accumulates at portions below the transfer electrodes  211 A and  212 A as shown in FIG. 12B and an N type channel is formed there.  
     [0123] It is to be noted that, if a power supply voltage is applied to only one of the transfer electrodes  211 A and  212 A, then the gate portion  213  remains in an OFF state.  
     [0124] In the present example, the gate length is expanded by the transfer electrodes  211 A and  212 A having the transfer electrodes  211 A and  212 A at such portions thereof as described above, and consequently, a transfer gate portion whose potential modulation degree can be increased and with which suppression of leak current is realized can be implemented.  
     [0125]FIG. 13 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a ninth embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0126] In the solid-state image pickup device of the present embodiment, an oblique gate electrode which includes a body portion and an expanded portion as shown, for example, in FIG. 5 is applied to a gate electrode of a two-layer structure of a transfer transistor and a transfer selection transistor.  
     [0127] In the solid-state image pickup device of the present embodiment, a FD portion  112  is arranged at an oblique position with respect to a photodiode  110 , and transfer electrodes  231 A and  232 A of a transfer gate portion  230  are arranged in an oblique direction.  
     [0128] The transfer electrodes  231 A and  232 A are formed in a substantially same shape (or in similar shapes), and the transfer electrode  231 A includes a body portion  231 A 1  and an expanded portion  231 A 2  provided integrally with each other while the transfer electrode  232 A includes a body portion  232 A 1  and an expanded portion  232 A 2  provided integrally with each other.  
     [0129] It is to be noted that end portions of the body portions  231 A 1  and  232 A 1  of the transfer electrodes  231 A and  232 A are connected to upper wiring lines (not shown) through contacts  231 B and  232 B, respectively.  
     [0130]FIG. 14 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a tenth embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0131] In the solid-state image pickup device of the present embodiment, a gate electrode which a body portion and an expanded portion and has a bent portion as shown, for example, in FIG. 6 is applied to a gate electrode of a two-layer structure of a transfer transistor and a transfer selection transistor.  
     [0132] In the solid-state image pickup device of the present embodiment, a FD portion  112  is arranged at an oblique position with respect to a photodiode  110 , and transfer electrodes  241 A and  242 A of a transfer gate portion  240  are arranged in a right-angularly bent state such that they surround two side faces of the FD portion  112 .  
     [0133] The transfer electrodes  241 A and  242 A are formed in a same shape (or in similar shapes), and the transfer electrode  241 A has an expanded portion  241 A 2  provided integrally at an outer side corner portion of a body portion  241 A 1  thereof which is bent at the right angle of 90 degrees, and the transfer electrode  242 A includes an expanded portion  242 A 2  provided integrally at an outer side corner portion of a body portion  242 A 1  thereof which is bent at the right angle of 90 degrees.  
     [0134] It is to be noted that end portions of the body portions  241 A 1  and  242 A 1  of the transfer electrodes  241 A and  242 A are connected to upper wiring lines (not shown) through contacts  241 B and  242 B, respectively.  
     [0135]FIG. 15 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to an eleventh embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0136] In the solid-state image pickup device of the present embodiment, similarly as in the example shown, for example, in FIG. 9, a gate electrode where a photo-gate (PG)  170  is provided in a state (indicated by slanting lines in FIG. 14) wherein it includes part of a photodiode  110  is applied to a gate electrode of a two-layer structure of a transfer transistor and a transfer selection transistor.  
     [0137] Part of signal charge produced by the photodiode  110  is accumulated, and signal charge of the photo-gate  170  is read out together with signal charge of the photodiode  110  by operation of a transfer gate portion  250 .  
     [0138] The transfer gate portion  250  is provided on that side of the photodiode  110  on which the photo-gate  170  is not provided, and transfer electrodes  251 A and  252 A of a two-layer structure similar to that, for example, in the eighth embodiment are provided for the transfer gate portion  250 .  
     [0139] The transfer electrodes  251 A and  252 A are formed in a same shape (or in similar shapes), and the transfer electrode  251 A includes a body portion  251 A 1  and an expanded portion  251 A 2  provided integrally with each other while the transfer electrode  252 A includes a body portion  252 A 1  and an expanded portion  252 A 2  provided integrally with each other. Further, end portions of the body portions  251 A 1  and  252 A 1  of the transfer electrodes  251 A and  252 A are connected to upper wiring lines (not shown) through contacts  251 B and  252 B, respectively.  
     [0140]FIG. 16 is a plan view showing an example of an arrangement of elements around a photodiode in a pixel of a solid-state image pickup device according to a twelfth embodiment of the present invention. It is to be noted that elements common to those of the example shown in FIG. 2 are denoted by like reference characters and description thereof is omitted.  
     [0141] In the solid-state image pickup device of the present embodiment, similarly as in the embodiment shown, for example, in FIG. 10, a gate electrode where a photo-gate (PG)  172  is provided in a state wherein it includes an entire photodiode  110  is applied to a gate electrode of a two-layer structure of a transfer transistor and a transfer selection transistor.  
     [0142] In the solid-state image pickup device of the present embodiment, the photodiode  110  is arranged in a state wherein it is entirely included in the photo-gate (GP)  172 , and the photo-gate  172  is arranged in a state wherein part thereof overlaps with a channel region of a transfer gate portion  260 .  
     [0143] Further, transfer electrodes  261 A and  262 A are provided on the transfer gate portion  260  in a state wherein they are arranged on the lower side of the photo-gate  172 .  
     [0144] The transfer electrodes  261 A and  262 A are formed in a same shape (or in similar shapes), and the transfer electrode  261 A has a body portion  261 A 1  and an expanded portion  261 A 2  and an end portion of the body portion  261 A 1  is connected to an upper wiring line through a contact  261 B.  
     [0145] Meanwhile, the transfer electrode  262 A has a body portion  261 A 1  and an expanded portion  262 A 2 , and an end portion of the body portion  261 A 1  is connected to an upper wiring line through a contact  262 B.  
     [0146] It is to be noted that, while, in the embodiments described above, the present invention is applied to the shape of a gate portion of a transfer transistor, the present invention can be applied also to the shape of a gate portion of any other transistor such as, for example, a reset transistor, and also such a configuration as just described shall be included in the scope of the present invention.  
     [0147] Further, the configuration of the solid-state image pickup device to which the present invention is applied is not limit to the embodiments described hereinabove, but the present invention may be applied to any solid-state image pickup device only if a photoelectric conversion element and at least more than one transistor which form a readout circuit for the photoelectric conversion element are included in at least one pixel.  
     [0148] As described above, according to the solid-state image pickup device of the present invention, since a gate portion of a transistor in a pixel has a belt-shaped portion having a plurality of widths in the gate lengthwise direction, the gate length of the gate portion can be increased to increase the potential modulation degree thereby to eliminate residual charge, which arises from an insufficient potential modulation degree, without disturbing so much the numerical aperture of the photoelectric conversion element so much as in a case wherein the entire gate portion is formed in a greater size, and improvement in picture quality and so forth of the solid-state image pickup device can be achieved.