Patent Publication Number: US-4060737-A

Title: Charge coupled device shift registers having an improved regenerative charge detector

Description:
This is a division, of application Ser. No. 499,717, filed Aug. 22, 1976, now U.S. Pat. No. 3,979,603. 
    
    
     This invention relates to regenerative charge detectors for charge coupled devices (CCD) and, more specifically, to a flip-flop circuit capable of detecting very small charge levels accurately and amplifying them to a full logical level signal. 
     Charge coupled devices comprise a new class of sequential memory circuits wherein extreme structural simplicity offers a high data packing density. The high packing density is achieved by trading off voltage gain for a smaller bit size. Data is stored and transferred in the form of charge held in capacitive storage. Charge coupled devices are well known in the prior art and therefore will not be discussed in detail herein. The prior art has had a problem in detecting the output of CCD memory circuits. The problem which is encountered in reading out such CCD memory circuits is to recreate the full logic voltage levels by detecting the extremely small amount of charge available in the CCD bits. Furthermore, the detection process must be reliable. That is, it must not be critically dependent upon supply voltage, frequency, temperature and operating conditions of the CCD. 
     One prior art CCD charge detector has been shown as a resistively loaded diode detector. While this simple diode detector is an excellent research tool because it is easy to implement and can be used for analytical evaluation of both analog and digital circuits, it has displayed poor sensitivity and is therefore inapplicable for high production volume digital CCD products. A further type of prior art CCD detector is called a precharged detector because the output diode voltage is set or precharged to a fixed reference voltage prior to initiating the charge detection. This type of charge detector, however, has had a problem with gain. As the number of bits on a chip becomes greater, the bit size becomes steadily smaller. Thus, the available signal swing at the output diode becomes smaller due to capacitive loading. Simply increasing the gain of the amplifiers is not sufficient because that also results in a decrease in speed and stability. Therefore, this second type of prior art CCD detector also has shortcomings which cannot be tolerated. 
     In accordance with the present invention, there is provided a circuit which overcomes the above-noted problems and provides an improved detector for accomplishing the desired detection function in digital CCD applications. Briefly, the above is accomplished by providing a detector which comprises an IGFET flip-flop wherein the two nodes are precharged to a voltage v out  which is substantially 2V tx  (V tx  = IGFT gate threshold voltage). The two nodes are then isolated from each other and the charge on the output device of the CCD, which will be either higher or lower than the node voltages is transferred to one node. When gain is restored to the flip-flop on the next clock period, the slight imbalance is amplified, driving one node quickly toward logic level &#34;one&#34; and the other toward logic level &#34;zero&#34;. There is then provided an output from the flip-flop which is a recreation of the full voltage logic levels, regardless of the size of the charge on the CCD device. The invention thus features a regenerative detector circuit utilizing positive feedback to achieve extremely high gain. The signal to be detected initiates the start of the positive feedback voltage gain or regeneration. Such a regenerative detector is to be distinguished from a CCD regenerator, i.e., a circuit comprising a detector, amplifier, and input buffer used for refreshing or redigitizing the slowly decaying signal in a CCD, and which may or may not include a regenerative circuit as the detector and amplifier. 
     It is yet a further object of this invention to provide a regenerative charge detector for charge coupled devices which is capable of reconstructing logic levels from small charge storage in the presence of severe capacitive loading without sacrificing speed. 
    
    
     The above objects and still further objects of the invention will immediately become apparent to those skilled in the art after consideration of the following preferred embodiments thereof, which are provided by way of example and not by way of limitation wherein: 
     FIG. 1 is a circuit diagram of a first embodiment of the invention; 
     FIG. 2 is a timer diagram associated with the embodiment of FIG. 1; 
     FIG. 3 is a transfer characteristic curve showing determination of the precharge voltage; 
     FIG. 4 is a circuit diagram of a second embodiment of the invention for use in conjunction with a multiplexing system; 
     FIG. 5 is a circuit diagram of a CCD storage system; 
     FIG. 6 is a circuit diagram of a third embodiment of the present invention; and 
     FIG. 7 is a diagram to determine reference voltage for the embodiment of FIG. 6. 
    
    
     Referring now to FIG. 1, there is shown a schematic diagram of a regenerative detector in accordance with the present invention for use with a single three phase charge coupled device. The detector circuit is operated in accordance with the same clock signals which are used to operate the charge coupled device. Therefore, as can be seen, the enable (or gain) clock pulse is shown as φ 2  and the feedback clock pulse is shown as φ 3 . The sample signal is provided by an external clock. A portion of a data CCD 1 is shown wherein data is stored in the form of charge which can be transferred or shifted along by proper sequential operation of the clock pulses φ 1 , φ 2 , φ 3  as is well known in the art. The charge coupled device 1 includes an output diode 3 formed therein. The output diode 3 is coupled to node V j1  of the detector circuit 11. A dummy reference CCD device 5 with diodes 7 and 9 also provides a predetermined reference signal to node V j2  of the detector as shown in FIG. 1. 
     The detector 11 itself includes five IGFET&#39;s, for example MOS transistors, of which transistors Q 1 , Q 2 , Q 3  and Q 4  comprise two MOS ratio-type inverters interconnected to form a flip-flop. One node of the flip-flop, designated V j1  is connected to the output diode 3 of the CCD 1. The other node, V j2 , is a dummy node. It also contains a dummy gate with overlap capacitance C M2  such that CM1/C j1  = CM2/C j2  where C j1  and C j2  comprise the total capacitances connected to nodes V j1  and V j2 . A function of CM 1  and CM 2  is to insure that the node voltages V j1  and V j2  are equally affected by the turning on of clock signal φ 2 . The detector also includes a feedback signal (φ f ) which is operated by phase φ 3  of the clock and an enable clock pulse (φ e ) line which is operated by a signal from clock φ 2  to operate transistors Q 2  and Q 4 . 
     The circuit also includes a generator 13 which provides a surface potential of approximately 2V tx  in amplitude. This is shifted across reference CCD 5 simultaneously with the data bits in data CCD 1 as previously discussed. 
     The output from the detector 11 is sensed by the balanced gated load circuit 15 wherein, during a ψ timing signal, both transistors Q 6  and Q 7  will be energized. One of these transistors will transfer a &#34;0&#34; or ground signal and the other will transfer a &#34;1&#34; or positive signal, depending upon the states of the nodes V j1  and V j2 . Therefore, only one of transistors Q 8  and Q 9  will be energized to provide either a ground or a V DD  output during the φ 2  time period. 
     The operation of the circuit of FIG. 1 will now be explained with reference to the timing diagram of FIG. 2. The detector is initially precharged. This is accomplished when clock φ 2  is on. Hence the inverters in the flip-flop are on. When φ 3  turns on, each inverter output is connected to its input, establishing the condition on the transfer curve where V out  = V in  which is approximately 2V tx . The gain is turned off when φ 2  turns off, resulting in Q 2  and Q 4  being cut off due to their effective V gs  being 0. This action causes node V j1  and V j2  to be isolated after the feedback clock φ 3  turns off. At this time, data is still stored under the last φ 1  gate in the data CCD. 
     Charge detection is initiated when φ 2  turns on. The surface potential beneath the last φ 1  gate in the data CCD will be either higher or lower than the voltage on node V j1 , depending upon the state of the data at that point. Thus there will be a momentary current flow to equalize the surface potential under the last φ 1  gate with V j1 . This results in V j1  changing slightly with respect to its initial value and with respect to V j2 . The amount of change in V j1  is given by: ##EQU1## where Cg is the capacitance of the CCD clock gates. E is the clock signal voltage amplitude and V tx , = CCD gate threshold voltage (assumed equal to the IGFET threshold voltage). The capacitive loading factor (C g  /C j1 ) -1  may be as much as 10 or more. For 5 volt clocks, ΔV j1  will be in the 100 milivolt range. Regeneration is initiated when φ 2  turns on. This turns the gain back on the flip-flop and the positive feedback or regeneration augments the change in V j1 . Since the two nodes have been placed in an imbalance voltage condition by the charge detection process, the act of turning on the gain in the flip-flop will cause the imbalance to be amplified. It can be seen that as the difference is amplified, one node is driven toward ground and the other node is driven toward E-V t . The final state of V j1  and V j2  is determined by the initial bit of imbalance in voltage when φ 2  is first turned on. 
     The cycle is repeated when feedback is returned and resets the nodes to their precharge level. The determination of the precharge level is determined with reference to FIG. 3. The flip-flop consists of two MOS ratio type converters. With the gate and drain of the transistor load connected together, the operation is said to be in a saturated mode. The transfer characteristic of such an inverter is also shown in FIG. 3. When the flip-flop feedback gate is enabled, the outputs of the inverters are connected to their inputs. On the transfer characteristic, the intersection of a line of V out  = V in  and the inverter transfer characteristic will be the precharge voltage. In most cases, the precharge voltage will be approximately twice the threshold voltage of the MOS transistors unless special level shifting circuitry is used. The load transistor could also be operated in a non-saturated mode, in which case its drain would be connected to V DD  and its gate clocked by φ 2  pulses. 
     The regenerative cycle can also be explained as follows with reference to FIG. 2: at t 0 , the feedback clock turns on, and both node voltages V j1  and V j2  are set equal. At t 1 , the enable clock turns the flip-flop gain off; node voltages decay toward V tx . At t 2 , feedback is turned off, the nodes are now isolated, but they are at equal potentials. At t 3 , the enable gate turns on, turning the flip-flop gain back on. At the same time, the charge in the reference and data CCD&#39;s is conducted to the gates. Depending upon the ratio of the data current to the reference current, an imbalance is imposed upon the regenerating flip-flop. This initial imbalance is initiated at the same time that the gain is turned on, so that the correct logic level is regenerated at V j1 , and its inverse at V j2 . Regeneration can occur in less than 40ns. 
     At t 4 , the sample gate pulse turns on, connecting V j1  and V j2  to the driver and load of a ratioless driver pair. After forcing these devices into an on or off situation, the sample gate turns off at t 5 , and the data is held until the next cycle. The cycle is repeated when the feedback clock turns back on. 
     It is known that a direct tradeoff on MOS inverters is gain for speed. As the load device is made with longer channels the gain increases for an inverter but the rise time is slowed. In order for the regenerative detector to function, it is required only that the gain be slightly greater than unity. Thus, once the initial node imbalance occurs, a full logic swing of E-V tx  is achieved through regenerative action and not through brute force gain. Thus, the individual inverters can be quite fast. 
     Turning now to FIG. 4, there is shown a CCD storage system wherein a plurality of CCD storage devices 21 are provided, these devices being either on separate semiconductor slices or provided as a plurality of individual registers on the same semiconductor slice. As in the embodiment of FIG. 1, each of these devices 21 includes a regenerative charge detector 23, a reference CCD device 25 and a reference voltage source 27 as described above. The output of each of the regenerative charge detectors 23 will be fed through an associated output load device 29, there being one such output load device 29 for each of the regenerative charge detectors. These outputs will be derived from each of the junctions V j1  and V j2  of the regenerative charge detector. 
     Each of the regenerative charge detectors 23 is a tri-state output device and will provide either a logical one output, a logical zero output or no output, this depending upon whether that particular regenerative charge detector is to be utilized during this particular step of the multiplexing operation. Only one of the lines 31 and 33 will have a logical one and the other will automatically then have a logical zero. Therefore, if the regenerative charge detector 23 is being read out, a logical one will be read out by having a positive signal on line 33 and a ground signal on line 31. A logical zero will be read out by having a ground signal on line 33 and a positive signal on line 31. This signal will be read out through the output terminal 35. In the event the detector 23 is not the one being sampled during the present multiplexing step, both of the lines 31 and 33 will provide insufficient voltage to cause either the load transistors 37 or the driver transistor 39 to conduct. Therefore, the output at the output terminal 35 will be floating and will in no way affect the output signal. In this manner, it can be seen that so long as only one of this group of detectors 23 provides an actual zero and one signal on the output lines 31, 33 the remainder of the detectors 23 will be floating and will in no way affect the output. In this way, a single output circuit can be utilized for a plurality of storage devices. In this way, multiplexing can be accomplished with simple circuitry. 
     Referring now to FIG. 5, there is shown a CCD storage device utilized as a shift register with capability of either recirculating and/or reading and writing information. The storage device 41 would include each of the elements 21, 23, 25 and 27 as well as one of the output circuits 29. The output, whether it be a one or a zero, can be read through an external device and can also be fed back to the input of the device 41 or, in other words, to the input of the CCD storage device. Depending upon whether the circuit is to be in the read or write mode, and, first assuming a read mode, a ground signal will be placed on the line 43, turning off the transistor 45 and turning on the transistor 47 through the inverter 49. This will allow the output signal from the device 41 to travel through transistor 47 and recirculate back into device 41 at its input. In the event that a write signal is provided at the line 43, the transistor 47 will be turned off and the transistor 45 will be turned on. Therefore, the output signal from the device 41 will be blocked and inhibited from returning to the input terminal, whereas new information can be read in on the input line 51 and passed through transistor 45 which is now conducting and fed into the storage device 41. It can be seen that there is here provided a simple circuit for read, write, and recirculation which requires merely two transistors and an inverter. 
     Referring now to FIG. 6, there is shown a further embodiment of a regenerative detector in accordance with the present invention which does not require a reference CCD device. This can be accomplished at the expense of making the detector sensitive to voltage levels within the detector circuit itself. The transfer characteristic for the circuit inverters is shown in FIG. 3. The reference voltage as shown in FIG. 3 is the intersection of the locus of V out  = V in  and the stage transfer function. Thus, the data from the CCD is detected as a &#34;1&#34; and &#34;0&#34;, depending upon whether or not the surface potential of the bit being detected in the CCD is greater than or less than the reference voltage. 
     The detector operation of the circuit of FIG. 6 is similar to that of FIG. 1. The operating cycle starts with gain and feedback on. Then gain is turned off followed by feedback turned off. This sets all nodes, (input, output and inter-stage interconnects) at or near the reference voltage. Then the last CCD clock is turned on, this being φ 3 , and the gain is turned on. The unbalance at the detector input caused by the sense of data in the CCD will tip the balance of the detector toward a logical level &#34;1&#34; or &#34;0&#34; at the output, and the regenerative action will fully drive the output to the extreme &#34;1&#34; or &#34;0&#34; level. 
     Though the invention has been described with respect to specific preferred embodiments thereof, many variations and modifications thereof will immediately become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.