Patent Publication Number: US-7592831-B2

Title: Circuit to optimize charging of bootstrap capacitor with bootstrap diode emulator

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is a continuation-in-part of U.S. application Ser. No. 11/696,825 filed Apr. 5, 2007 and entitled CIRCUIT TO OPTIMIZE CHARGING OF BOOTSTRAP CAPACITOR WITH BOOTSTRAP DIODE EMULATOR, which is incorporated herein by reference. The entire contents of U.S. patent application Ser. No. 10/712,893, filed on Nov. 12, 2003 and entitled BOOTSTRAP DIODE EMULATOR WITH DYNAMIC BACK-GATE BIASING and of U.S. patent application Ser. No. 11/207,465, filed on Aug. 19, 2005 and entitled BOOTSTRAP DIODE EMULATOR WITH DYNAMIC BACK-GATE BIASING AND SHORT-CIRCUIT PROTECTION, are also incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   The present invention relates to optimizing charging of a bootstrap capacitor wherein a bootstrap capacitor is charged by a circuit emulating a bootstrap diode. 
   A common half bridge gate driver circuit  100  driving a load is illustrated in  FIG. 1 . The gate driver circuit  100  includes a high side and a low side driver circuits DRV 1  and DRV 2  for driving high side and low side transistors  105   a  and  105   b  in a complementary fashion. In the illustrated circuit  100 , it is necessary to provide voltage DC 1  for the high side driver circuit DRV 1 , which is referenced to a different reference level than voltage DC 2  provided for the low side driver circuit DRV 2 . 
   That is because the source of the high side transistor  105   a  is above the source of the low side transistor  105   b . The high side driver circuit DRV 1  is referenced to the source of the high side output transistor  105   a . Thus the powering voltage to the high side driver circuit DRV 1  must be above the powering voltage to the low side driver circuit DRV 2 . 
   To do this, a bootstrap circuit, illustrated in  FIG. 2 , has been employed including a bootstrap capacitor CBS and a diode DBS coupled to the voltage DC 2 . The diode DBS allows the bootstrap capacitor CBS to be charged to a high side floating supply voltage VBS above the source voltage at a switched node A while the low side transistor  105   b  is conducting and the high side transistor  105   a  is turned OFF. When the low side transistor  105   b  is turned OFF, the power supply voltage to the high side driver circuit DRV 1  is approximately at a level of the voltage DC 2  above the source voltage at the switched node A. That is because the capacitor CBS has been charged through the diode DBS from the supply voltage DC 2 . Accordingly, the high side floating supply voltage VBS for the high side driver has been increased above the level of DC 2  which powers the low side driver circuit DRV 2  using this bootstrap circuit. 
   In another circuit  300 , shown in  FIG. 3 , the bootstrap diode DBS ( FIG. 2 ) has been replaced by a bootstrap diode emulator circuit  302 , used for charging the bootstrap capacitor CBS. The advantage of circuit  300  over circuit  101  ( FIG. 2 ) is that the losses due to the diode are reduced. 
     FIG. 4  illustrates the bootstrap diode emulator circuit  302 . Typically, such circuit uses an FET  405  having lower forward losses than a diode. The bootstrap diode emulator circuit  302  further employs a gate control circuit  410  for accepting a low side input signal LIN and driving the FET  405  and a dynamic back-gate biasing circuit  415 . The dynamic back-gate biasing circuit  415  accepts the low side input signal LIN and is connected to the low side return node B (see  FIG. 3 ) and the bootstrap capacitor CBS. The FET  405  is also connected to the bootstrap capacitor CBS and to the low side supply voltage DC 2  V CC . 
   The gate control circuit  410  is shown in  FIG. 5 . It includes switches  520 ,  525 ,  530 ,  535 , and  545 ; inverter circuits  505  and  515 ; and a source  510 . The dynamic back-gate biasing circuit  415  is shown in  FIG. 6 . That circuit includes switches  620 ,  625 ,  630 , and  635 ; two current sources  610  and  615 ; and an inverter  605 . The circuit  700  of  FIG. 7  illustrates the components of the gate control circuit  410  and the dynamic back-gate biasing circuit  415  combined with the rest of the circuit  300  of  FIG. 3 . The circuit  700  is the subject of U.S. patent application Ser. No. 10/712,893, which is incorporated herein by reference. 
   The circuit  700  possesses limitations, including conditions when the bootstrap capacitor cannot be fully charged because the low side input signal LIN to the low side driver is low even though the voltage VS at the switched node A is still low. In this condition, when the low side input signal LIN is low, because the bootstrap diode emulator is off, it cannot charge the bootstrap capacitor CBS. This deficiency may cause development of insufficient voltage across the bootstrap capacitor CBS to properly power the high side driver. 
   SUMMARY OF THE INVENTION 
   It is an object of the present invention to provide a circuit that optimizes the charging of the bootstrap capacitor to allow the bootstrap capacitor to charge whenever the voltage VS at the switched node A is low, despite the level of the input drive signal. 
   According to the invention, provided is a circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having high- and low-side driver circuits for driving high- and low-side switches connected at the switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and the low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing the high-side floating supply voltage for the high-side driver circuit, the optimizing circuit comprising: a bootstrap diode emulator circuit comprising a bootstrap diode emulator driver circuit driving a first switch connected between the first terminal of the bootstrap capacitor and a supply voltage for the low side driver circuit; and a phase sense comparator circuit responsive to the voltage at the switched node and turning ON the first switch when the voltage at the switched node is LOW, whereby charging of the bootstrap capacitor is optimized when the phase sense comparator circuit is enabled,
         the phase sense comparator circuit turning OFF or keeping OFF the first switch when the first control voltage goes to a level adapted to turn ON the high side switch or remains at such level or the bootstrap capacitor supply voltage goes high or remains high such that it is a fixed amount above the low-side driver supply voltage;   further wherein the phase sense comparator circuit turns the first switch ON when:   the second control voltage is at a level adapted to turn ON the low-side switch and the bootstrap capacitor supply voltage is low such that it is below the fixed amount above the low-side driver supply voltage; or   the first and second control voltages are both at a level such that the high-side and low-side switches are OFF after the second control voltage transitions from an ON state to an OFF state and the bootstrap capacitor supply voltage (V BS ) goes below the fixed amount above the low-side driver supply voltage (V CC ); or   the first and second control voltages are both at a level such that the high-side and low-side switches are OFF after the first control voltage transitions from an ON state to an OFF state and the bootstrap capacitor supply voltage goes below the fixed amount above the low-side driver supply voltage.       

   Preferably, the bootstrap capacitor supply voltage (V BS ) must go below the fixed amount above the low side driver supply voltage (V CC ) before a delay time in order to turn the first switch ON. 
   Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram of a prior art gate driver circuit having a half bridge stage for driving a load; 
       FIG. 2  is a diagram of the gate driver circuit of  FIG. 1  using a bootstrap circuit instead of a voltage source for the supply of the high side driver circuit; 
       FIG. 3  is a diagram of another version of the gate driver circuit of  FIG. 2  having the bootstrap circuit using a bootstrap diode emulator circuit instead of the bootstrap diode; 
       FIG. 4  is a diagram of the bootstrap diode emulator circuit of  FIG. 3 ; 
       FIG. 5  is a diagram of the gate control circuit of  FIG. 4 ; 
       FIG. 6  is a diagram of the dynamic back-gate biasing circuit of  FIG. 4 ; 
       FIG. 7  is a combined diagram of the circuits described in  FIGS. 3-6 ; 
       FIG. 8  is a diagram of a bootstrap diode emulator controlled by a phase sense comparator of the present invention; 
       FIG. 9  is a graph indicating operational sequence of signals over time; 
       FIG. 9A  shows a timing waveform of a preferred implementation of the circuit of  FIG. 8 ; 
       FIG. 9B  shows the block diagram of the driver circuit; 
       FIG. 10  is a diagram of the phase sense comparator circuit; 
       FIG. 11  is a graph indicating operational sequence of signals of components of the phase sense comparator circuit of  FIG. 10  over time; and 
       FIG. 12  is a diagram of two output transistors connected in a half bridge for driving a motor. 
   

   DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION 
   In accordance with the present invention,  FIG. 8  shows a circuit  800  that optimizes the charging of the bootstrap capacitor CBS to allow it to charge whenever the voltage VS at switched a node A ( FIG. 7 ) is low. The circuit  800  includes a phase sense comparator  220 , the diode emulator, illustrated by the FET  405  (also see  FIG. 4 ), and a bootstrap diode emulator driver  200 . 
   The phase sense comparator  220  and the bootstrap diode emulator driver  200  are connected between the low side supply voltage V CC  and the ground V SS . The phase sense comparator  220  receives a signal from the bootstrap diode emulator driver  200  and an enabling signal LOPD generated by a low side output pre-driver from the low side input signal LIN and provides an output VSsense out to the bootstrap diode emulator. The diode emulator LDMOS  405  is connected between the low side supply voltage VCC and the high side floating supply voltage VBS. The high side floating supply voltage VBS is provided across a capacitor C BS , which is connected to the switched node (phase) VS. 
   According to the present invention, the high and low side input signals HIN and LIN are sensed. If the high side input signal HIN is HIGH, the phase sense comparator  220  is disabled. If the low side input signal LIN is HIGH and thus LOPD signal, generated from the low side input signal LIN, is HIGH, the phase sense comparator  220  is enabled. 
   When the high and low side input signals HIN or LIN go OFF, a timeout, e.g., one microsecond, is employed to keep the phase sense comparator  220  enabled. If during the timeout, the voltage VS stays OFF or goes to DC− level, the bootstrap diode emulator  405  is kept turned ON. If during the timeout, the switched node voltage VS stays at or goes to DC+, the bootstrap diode emulator  405  is turned OFF and the phase sense comparator  220  is disabled. Thus, the bootstrap diode emulator  405  is driven only by the phase sense comparator  220 . The bootstrap capacitor CBS is charged whenever the phase sense comparator  220  is enabled. 
   The phase sense comparator  220  thus senses the voltage VS. At the end of the timeout, if the voltage VS is low, the phase sense comparator  220  remains enabled. If the voltage VS goes HIGH, the phase sense comparator  220  goes OFF. 
   As shown in  FIG. 9 , the phase sense comparator  220  provides a high output at the voltage VS sense output when signal LOPD (LIN) is high and the voltage VS is low at DC−. There is thus a double enable. The bootstrap diode emulator  405  is turned ON by the phase sense comparator  220  if the low side driver input LIN is on and the voltage VS is low. Thus, according to the present invention, the bootstrap diode emulator  405  is turned ON every time the voltage VS at the switched node A is low, ensuring that the charging of the bootstrap capacitor CBS is optimized. 
   A circuit for the phase sense comparator circuit  220  is illustrated in  FIG. 10 . The circuit includes a current comparator  230  with hysteresis and two switches. The phase sense comparator circuit  220  uses an LDMOS device  210  and a low-voltage NMOS device  225  to compare the high side floating supply voltage VBS and low side supply voltage VCC. The high side floating supply voltage VBS approximately equals the combination of the voltage VS and VCC. The respective currents I A  and I B  through the LDMOS device  210  and the NMOS device  225  via resistors Ra and Rb are provided to the current comparator circuit  230  having a hysteresis characteristic. 
     FIG. 11  illustrates timing signals of the components of the circuit  220 . As illustrated, the high side floating supply voltage VBS represents the floating high side bootstrap voltage, a signal CMD is generated from signal LOPD, which, in turn, is generated form the low side input signal LIN and the gate control circuit. Signals A and B are voltages at points identified in  FIG. 10  and a signal OUT represents the output to the gate control circuit for the bootstrap diode emulator  405  from the current comparator  230  with hysteresis. 
   When the signal LOPD is turned ON, the current comparator  230  is enabled and a first gate control circuit provides a signal used to turn on the “Vssense” LDMOS device  210 . Then, as shown in  FIG. 11 , if VBS is ≦VCC+Vhysteresis, then the current comparator  230  enables the second gate control circuit to turn ON the diode emulator LDMOS  405  (VSsense OUT goes high). The diode emulator  405  stays turned ON until the signal LOPD is turned OFF, or until VBS becomes ≧VCC+Vhysteresis. 
     FIG. 12  shows two output transistors Q 1  and Q 2  connected in a half bridge stage for driving a phase of a load comprising a motor. When the high side input signal HIN is LOW, the phase sense comparator circuit  220  is enabled. When the high side input signal HIN is HIGH, the output transistors Q 1  is turned on to allow the current to flow to the motor load, as identified in the Figure by numeral  1 . Then, when the high side input signal HIN goes OFF, the output transistors Q 1  is turned off, as identified in the Figure by numeral  2 , and the time-out state is entered. When the output transistor Q 1  is fully OFF, but before the low side transistor Q 2  is turned ON, the current flows through the freewheeling diode to the motor, as identified in the Figure by numeral  3 . 
   At that point, the high side input signal HIN is OFF; the low side input signal LIN is also OFF; and the phase sense comparator circuit  220  is enabled for a time delay, e.g., one microsecond. During this time, voltage VS is monitored. 
   If the switched node voltage VS is at a DC− level, the bootstrap diode emulator is turned ON. If the voltage VS is greater than VCC, the bootstrap diode emulator is turned OFF and the phase comparator circuit  220  is disabled. 
     FIG. 9A  shows a timing diagram of a preferred implementation of the bootstrap diode emulator and phase comparator. According to this embodiment:
         A. The bootstrap diode emulator turns off immediately or stays off when at least one of the following conditions are met:
           1. HIN, and thus HO goes or is high (see  FIG. 9   a (A));   2. V BS  goes or is high (&gt;1.1*V CC ) (see  FIG. 9A  (H)).   
           B. The bootstrap diode emulator turns on when:
           1. LIN (and thus LO) is high (low side is on) and V BS  is low (&lt;1.1*V CC ) (see FIGS.  9 A(F) and  9 A(H)); or   2. LIN and HIN are low after a LIN transition from H to L (HB output is in tri-state) and V BS  goes low (&lt;1.1*V CC ) before a fixed time of 20 μs (see FIGS.  9 A(F) and  9 A(H)); or   3. LIN and HIN are low after an HIN transition from H to L (HB output is in tri-state) and V BS  goes low (&lt;1.1*V CC ) before a retriggerable time of 20 μs. See FIGS.  9 A(A), (A(B) and  9 A(D). In this case, the timer counter is kept in the reset state until V BS  goes high (&gt;1.1*V CC ).   
               
   Note that in the embodiment shown in the timing diagrams of  FIG. 9A , the time out delay has been increased from 1 to 20 μsecs. Compare to  FIG. 9 , where the time out is 1 μsec. 
     FIG. 9B  shows the driver circuit in greater detail. The bootstrap diode emulator circuit incorporating the phase sense comparator operating according to  FIG. 9A  is shown at  800 . The driver circuit employs low and high side control inputs LIN and HIN, that are sensed by comparator circuits  901  and  902  and filtered ( 903  and  904 ). 
   The low-side control signal is subject to a delay stage  905 , fed through logic circuitry  906  and provided to the low-side driver DRV 2  to drive the low-side switch. 
   The filtered high-side control signal is fed to a pulse generator  907 , then to the high-side level shift circuit  908 . The level shifted signals referenced to VS are then provided to a pulse filter  909  and to an S-R latch  910  before driving the high-side driver DRV 1  to drive the high-side switch. Under-voltage protection for the high-side supply is provided by circuit  911  while circuit  912  provides low-side UV protection. 
   Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention not be limited by the specific disclosure herein.