Patent Publication Number: US-2021175362-A1

Title: Semiconductor device, method for manufacturing semiconductor device, module, and electronic device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 14/949,959, filed Nov. 24, 2015, now pending, which claims the benefit of a foreign priority application filed in Japan as Serial No. 2014-244302 on Dec. 2, 2014, both of which are incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to, for example, a transistor and a semiconductor device. The present invention relates to, for example, a method for manufacturing a transistor and a semiconductor device. The present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a processor, and an electronic device. The present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, an imaging device, and an electronic device. The present invention relates to a driving method of a display device, a liquid crystal display device, a light-emitting device, a memory device, an imaging device, and an electronic device. 
     Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. 
     In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, a memory device, an imaging device, an electro-optical device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases. 
     2. Description of the Related Art 
     A technique for forming a transistor by using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is applied to a wide range of semiconductor devices such as an integrated circuit and a display device. Silicon is known as a semiconductor applicable to a transistor. 
     As silicon which is used as a semiconductor of a transistor, either amorphous silicon or polycrystalline silicon is used depending on the purpose. For example, for a transistor included in a large display device, it is preferable to use amorphous silicon, which can be used to form a film on a large substrate with the established technique. On the other hand, for a transistor included in a high-performance display device where driver circuits are formed over the same substrate, it is preferred to use polycrystalline silicon, which can form a transistor having high field-effect mobility. As a method for forming polycrystalline silicon, high-temperature heat treatment or laser light treatment which is performed on amorphous silicon has been known. 
     In recent years, transistors using oxide semiconductors (typically, In—Ga—Zn oxide) have been actively developed. 
     Oxide semiconductors have been researched since early times. In 1988, there was a disclosure of a crystal In—Ga—Zn oxide that can be used for a semiconductor element (see Patent Document 1). In 1995, a transistor including an oxide semiconductor was invented, and its electrical characteristics were disclosed (see Patent Document 2). 
     The transistors including oxide semiconductors have different features from the transistors including amorphous silicon or polycrystalline silicon. For example, a display device in which a transistor including an oxide semiconductor is used is known to have small power consumption. An oxide semiconductor film can be formed by a sputtering method or the like, and thus can be used in a transistor included in a large display device. A transistor including an oxide semiconductor has high field-effect mobility; therefore, a high-performance display device where driver circuits are formed over the same substrate can be obtained. In addition, there is an advantage that capital investment can be reduced because part of production equipment for a transistor including amorphous silicon can be retrofitted and utilized. 
     For example, for mass production of semiconductor devices such as display devices, stable electrical characteristics of transistors including an oxide semiconductor are required. 
     In a transistor including an oxide semiconductor, it is very important to control oxygen vacancies in the oxide semiconductor. In order to obtain stable transistor characteristics, oxygen vacancies are preferably reduced as much as possible. As a technique for reducing oxygen vacancies, a method for injecting oxygen into the oxide semiconductor (see Patent Document 3) can be used. 
     REFERENCE 
     Patent Documents 
     
         
         [Patent Document 1] Japanese Published Patent Application No. S63-239117 
         [Patent Document 2] Japanese Translation of PCT International Application No. H11-505377 
         [Patent Document 3] Japanese Published Patent Application No. 2012-238880 
       
    
     SUMMARY OF THE INVENTION 
     An object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor having normally-off electrical characteristics. Another object is to provide a transistor having a small subthreshold swing value. Another object is to provide a transistor having a small short-channel effect. Another object is to provide a transistor having a low leakage current in an off state. Another object is to provide a transistor having excellent electrical characteristics. Another object is to provide a transistor having high reliability. 
     Another object is to provide a transistor with high frequency characteristics. 
     Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including any of the above semiconductor devices. Another object is to provide an electronic device including any of the above semiconductor devices or the module. Another object is to provide a novel semiconductor device. Another object is to provide a novel module. Another object is to provide a novel electronic device. 
     Note that the descriptions of these objects do not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like. 
     As mentioned above, it is very important to control oxygen vacancies in the oxide semiconductor. In order to obtain stable transistor characteristics, oxygen vacancies are preferably reduced as much as possible. Moreover, it is also important to form a stable bond so that the filled oxygen vacancies are prevented from becoming oxygen vacancies again owing to damage in a manufacturing process of a transistor or the like. 
     Thus, in one embodiment of the present invention, fluorine is added to a channel formation region of a semiconductor, whereby oxygen vacancies in the semiconductor are filled, and the oxygen vacancies are filled with fluorine, which forms a stable bond, whereby a transistor having stable and favorable electrical characteristics is provided. 
     One embodiment of the present invention is a semiconductor device including a gate electrode, a gate insulator, and an oxide semiconductor. The oxide semiconductor contains fluorine in a channel formation region. 
     Another embodiment of the present invention is a semiconductor device in which a fluorine concentration in the channel formation region is higher than or equal to 1×10 20  atoms/cm 3  and lower than or equal to 1×10 22  atoms/cm 3 . 
     Another embodiment of the present invention is a semiconductor device in which, in the oxide semiconductor, a fluorine concentration in a region other than the channel formation region is lower than the fluorine concentration in the channel formation region. 
     Another embodiment of the present invention is a semiconductor device in which the oxide semiconductor contains at least one selected from indium, zinc, and an element M (an element M is aluminum, gallium, yttrium, or tin). 
     Another embodiment of the present invention is a module including the above-described semiconductor device and a printed board. 
     Another embodiment of the present invention is an electronic device including the above-described semiconductor device or the above-described module and a speaker, an operation key, or a battery. 
     Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming an oxide semiconductor over a substrate, forming a source electrode and a drain electrode which are in contact with the oxide semiconductor, adding fluorine to the oxide semiconductor, forming an insulator over the oxide semiconductor, the source electrode, and the drain electrode, and forming a gate electrode over the insulator. 
     Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming an oxide semiconductor over a substrate, adding fluorine to the oxide semiconductor, forming a source electrode and a drain electrode which are in contact with the oxide semiconductor, forming an insulator over the oxide semiconductor, the source electrode, and the drain electrode, and forming a gate electrode over the insulator. 
     Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming an oxide semiconductor over a substrate, forming a source electrode and a drain electrode which are in contact with the oxide semiconductor, forming an insulator over the oxide semiconductor, the source electrode, and the drain electrode, adding fluorine to the oxide semiconductor through the insulator, and forming a gate electrode over the insulator. 
     Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming a gate electrode over a substrate, forming an insulator over the gate electrode, forming an oxide semiconductor over the gate electrode with the insulator provided therebetween, adding fluorine to the oxide semiconductor, and forming a source electrode and a drain electrode which are in contact with the oxide semiconductor. 
     Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming a gate electrode over a substrate, forming an insulator over the gate electrode, forming an oxide semiconductor over the gate electrode with the insulator provided therebetween, forming a source electrode and a drain electrode which are in contact with the oxide semiconductor, and adding fluorine to the oxide semiconductor. 
     Another embodiment of the present invention is a method for manufacturing a semiconductor device in which the fluorine is added by an ion implantation method. 
     Another embodiment of the present invention is a method for manufacturing a semiconductor device in which the oxide semiconductor contains at least one selected from indium, zinc, and an element M (an element M is aluminum, gallium, yttrium, or tin). 
     A transistor with stable electrical characteristics can be provided. A transistor having normally-off electrical characteristics can be provided. A transistor having a small subthreshold swing value can be provided. A transistor having a small short-channel effect can be provided. A transistor having a low leakage current in an off state can be provided. A transistor having excellent electrical characteristics can be provided. A transistor having high reliability can be provided. A transistor with high frequency characteristics can be provided. 
     A semiconductor device including any of the transistors can be provided. A module including the semiconductor devices can be provided. An electronic device including the semiconductor device or the module can be provided. A novel semiconductor device can be provided. A novel module can be provided. A novel electronic device can be provided. 
     Note that the description of these effects does not disturb the existence of other effects. One embodiment of the present invention does not necessarily have all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the accompanying drawings: 
         FIGS. 1A and 1B  are a top view and a cross-sectional view illustrating a transistor of one embodiment of the present invention; 
         FIGS. 2A and 2B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 3A and 3B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 4A and 4B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 5A and 5B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 6A and 6B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 7A to 7C  are cross-sectional views each illustrating a transistor of one embodiment of the present invention; 
         FIGS. 8A to 8C  are cross-sectional views each illustrating a transistor of one embodiment of the present invention; 
         FIG. 9  is a band diagram illustrating one embodiment of the present invention; 
         FIGS. 10A to 10D  are Cs-corrected high-resolution TEM images of a cross section of a CAAC-OS and a cross-sectional schematic view of a CAAC-OS; 
         FIGS. 11A to 11D  are Cs-corrected high-resolution TEM images of a plane of a CAAC-OS; 
         FIGS. 12A to 12C  show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD; 
         FIGS. 13A and 13B  show electron diffraction patterns of a CAAC-OS; 
         FIG. 14  shows a change in crystal part of an In—Ga—Zn oxide induced by electron irradiation; 
         FIGS. 15A and 15B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 16A and 16B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 17A and 17B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 18A and 18B  are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 19A and 19B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 20A and 20B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 21A and 21B  are a top view and a cross-sectional view illustrating a method for manufacturing a transistor of one embodiment of the present invention; 
         FIGS. 22A to 22C  are cross-sectional views each illustrating a transistor of one embodiment of the present invention; 
         FIGS. 23A to 23C  are cross-sectional views each illustrating a transistor of one embodiment of the present invention; 
         FIGS. 24A and 24B  are circuit diagrams each illustrating a semiconductor device of one embodiment of the present invention; 
         FIG. 25  is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention; 
         FIG. 26  is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention; 
         FIG. 27  is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention; 
         FIGS. 28A and 28B  are circuit diagrams each illustrating a memory device of one embodiment of the present invention; 
         FIG. 29  is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention; 
         FIG. 30  is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention; 
         FIG. 31  is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention; 
         FIGS. 32A and 32B  are plan views each illustrating a semiconductor device of one embodiment of the present invention; 
         FIGS. 33A and 33B  are block diagrams each illustrating a semiconductor device of one embodiment of the present invention; 
         FIGS. 34A and 34B  are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention; 
         FIGS. 35A and 35B  are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention; 
       FIGS.  36 A 1  to  36 A 3  and  36 B 1  to  36 B 3  are perspective views and cross-sectional views illustrating semiconductor devices of one embodiment of the present invention; 
         FIG. 37  is a block diagram illustrating a semiconductor device of one embodiment of the present invention; 
         FIG. 38  is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention; 
         FIGS. 39A to 39C  are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention; 
         FIGS. 40A and 40B  are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention; 
         FIGS. 41A to 41F  are perspective views each illustrating an electronic device of one embodiment of the present invention; 
         FIG. 42  is a graph showing the amount of added fluorine in the depth direction; 
         FIG. 43  is a graph showing sheet resistance values of samples; and 
         FIGS. 44A and 44B  are graphs showing results of ESR measurement of samples. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, embodiments and examples of the present invention will be described in detail with the reference to the drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways. Further, the present invention is not construed as being limited to description of the embodiments and the examples. In describing structures of the present invention with reference to the drawings, common reference numerals are used for the same portions in different drawings. Note that the same hatched pattern is applied to similar parts, and the similar parts are not especially denoted by reference numerals in some cases. 
     Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity. 
     In this specification and the like, the terms “film” and “layer” can be interchanged with each other. 
     A voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a source potential or a ground potential (GND)). A voltage can be referred to as a potential and vice versa. Note that in general, a potential (a voltage) is relative and is determined depending on the amount relative to a certain potential. Therefore, a potential that is represented as a “ground potential” or the like is not always 0 V. For example, the lowest potential in a circuit may be represented as a “ground potential”. Alternatively, a substantially intermediate potential in a circuit may be represented as a “ground potential”. In these cases, a positive potential and a negative potential are set using the potential as a reference. 
     Note that the ordinal numbers such as “first” and “second” are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like do not correspond to the ordinal numbers which specify one embodiment of the present invention in some cases. 
     Note that a “semiconductor” has characteristics of an “insulator” in some cases when the conductivity is sufficiently low, for example. Further, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border therebetween is not clear. Accordingly, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases. 
     Further, a “semiconductor” has characteristics of a “conductor” in some cases when the conductivity is sufficiently high, for example. Further, a “semiconductor” and a “conductor” cannot be strictly distinguished from each other in some cases because a border therebetween is not clear. Accordingly, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases. 
     Note that impurities in a semiconductor refer to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of lower than 0.1 atomic % is an impurity. When an impurity is contained, the density of states (DOS) may be formed in a semiconductor, the carrier mobility may be decreased, or the crystallinity may be decreased. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specifically, there are hydrogen (included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. In the case of an oxide semiconductor, oxygen vacancies may be formed by entry of impurities such as hydrogen. In the case where the semiconductor is silicon, examples of an impurity which changes characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements. 
     Note that the channel length refers to, for example, the distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a plan view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed. 
     The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed. 
     Note that depending on transistor structures, a channel width in a region where a channel is formed actually (hereinafter referred to as an effective channel width) is different from a channel width shown in a plan view of a transistor (hereinafter referred to as an apparent channel width) in some cases. For example, in a transistor having a three-dimensional structure, an effective channel width is greater than an apparent channel width shown in a plan view of the transistor, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel formation region formed in a side surface of a semiconductor is high in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the plan view. 
     In a transistor having a three-dimensional structure, an effective channel width is difficult to measure in some cases. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known as an assumption condition. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately. 
     Therefore, in this specification, in a plan view of a transistor, an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Further, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like. 
     Note that in the case where electric field mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, the values might be different from those calculated by using an effective channel width. 
     Note that in this specification, the description “A has a shape such that an end portion extends beyond an end portion of B” may indicate, for example, the case where at least one of end portions of A is positioned on an outer side than at least one of end portions of B in a top view or a cross-sectional view. Thus, the description “A has a shape such that an end portion extends beyond an end portion of B” can be read as the description “one end portion of A is positioned on an outer side than one end portion of B in a top view,” for example. 
     In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. A term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. A term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°. 
     In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system. 
     In this specification, a term “semiconductor” can be referred to as an “oxide semiconductor”. As the semiconductor, a Group 14 semiconductor such as silicon or germanium; a compound semiconductor such as silicon carbide, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, or cadmium sulfide; or an organic semiconductor can be used. 
     Embodiment 1 
     In this embodiment, an example of a transistor of one embodiment of the present invention will be described. 
     &lt;Transistor  1 &gt; 
       FIGS. 1A and 1B  illustrate a transistor of one embodiment of the present invention.  FIG. 1A  is a top view of a transistor  100 , and  FIG. 1B  is a cross-sectional view taken along dashed-dotted lines A 1 -A 2  and A 3 -A 4  in  FIG. 1A . The transistor  100  includes a substrate  400 , a conductor  413 , an insulator  402 , a semiconductor  406   a , a semiconductor  406   b , a semiconductor  406   c , a conductor  416   a , a conductor  416   b , an insulator  412 , and a conductor  404 . 
     The semiconductors  406   a ,  406   b , or  406   c  of the transistor  100  can contain fluorine. All of the three layers may contain fluorine. Alternatively, any one or two of the three layers may contain fluorine. 
     In the case where a semiconductor of a transistor includes a plurality of layers as described in this embodiment, a semiconductor including a channel formation region preferably contains fluorine. For example, in the case where the semiconductor  406   b  includes a channel formation region, the semiconductor  406   b  preferably contains fluorine. 
     The conductor  404  functions as a first gate electrode (also referred to as a front gate electrode) of the transistor  100 . The conductor  413  functions as a second gate electrode (also referred to as a back gate electrode) of the transistor  100 . The conductor  416   a  and the conductor  416   b  function as a source electrode and a drain electrode of the transistor  100 . The insulator  412  functions as a gate insulator. 
     In this embodiment, the transistor  100  is a top-gate transistor including a back gate; however, the present invention is not limited thereto. For example, a back gate is not necessarily provided. Alternatively, a bottom-gate structure may be employed. In this case, the conductor  413  functions as a front gate, and the conductor  404  functions as a back gate. Alternatively, the conductor  404  is not necessarily provided. 
     A method for manufacturing the transistor  100  illustrated in  FIGS. 1A and 1B  is described with reference to  FIGS. 2A and 2B ,  FIGS. 3A and 3B ,  FIGS. 4A and 4B ,  FIGS. 5A and 5B , and  FIGS. 6A and 6B . 
       FIG. 2A ,  FIG. 3A ,  FIG. 4A ,  FIG. 5A , and  FIG. 6A  are top views illustrating a method for manufacturing the transistor  100  of one embodiment of the present invention.  FIG. 2B ,  FIG. 3B ,  FIG. 4B ,  FIG. 5B , and  FIG. 6B  are each a cross-sectional view taken along dashed-dotted lines A 1 -A 2  and A 3 -A 4  shown in the corresponding top view. 
     First, a substrate  400  is prepared. 
     As the substrate  400 , an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), or a resin substrate is used, for example. As the semiconductor substrate, a single material semiconductor substrate of silicon, germanium, or the like or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like is used, for example. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate or the like is used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is used. A substrate including a metal nitride, a substrate including a metal oxide, or the like is used. An insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like is used. Alternatively, any of these substrates over which an element is provided may be used. As the element provided over the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like is used. 
     Alternatively, a flexible substrate may be used as the substrate  400 . As a method for providing the transistor over a flexible substrate, there is a method in which the transistor is formed over a non-flexible substrate and then the transistor is separated and transferred to the substrate  400  which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. As the substrate  400 , a sheet containing a fiber, a film, or a foil may be used. The substrate  400  may have elasticity. The substrate  400  may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate  400  may have a property of not returning to its original shape. The thickness of the substrate  400  is, for example, greater than or equal to 5 μm and less than or equal to 1000 μm, preferably greater than or equal to 10 μm and less than or equal to 700 μm, or further preferably greater than or equal to 15 μm and less than or equal to 500 μm. When the substrate  400  has a small thickness, the weight of the semiconductor device can be reduced. When the substrate  400  has a small thickness, even in the case of using glass or the like, the substrate  400  may have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate  400 , which is caused by dropping or the like, can be reduced. That is, a durable semiconductor device can be provided. 
     For the substrate  400  which is a flexible substrate, metal, an alloy, resin, glass, or fiber thereof can be used, for example. The flexible substrate  400  preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate  400  is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10 −3 /K, lower than or equal to 5×10 −5 /K, or lower than or equal to 1×10 −5 /K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate  400  because of its low coefficient of linear expansion. 
     Next, a conductor is formed. The conductor may be formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. 
     CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD method can include a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas. 
     In the case of a PECVD method, a high quality film can be obtained at relatively low temperature. A TCVD method is a film formation method in which an object is not damaged by plasma because plasma is not used. For example, a wiring, an electrode, an element (e.g., transistor or capacitor), or the like included in a semiconductor device might be charged up by receiving charges from plasma. In that case, accumulated charges might break the wiring, electrode, element, or the like included in the semiconductor device. Such plasma damage is not caused in the case of using a TCVD method, and thus the yield of a semiconductor device can be increased. In addition, since plasma damage does not occur in the deposition by a TCVD method, a film with few defects is easily obtained. 
     An ALD method also causes less plasma damage to an object. An ALD method does not cause plasma damage during deposition, so that a film with few defects is easily obtained. 
     Unlike in a deposition method in which particles ejected from a target or the like are deposited, in a CVD method and an ALD method, a film is formed by reaction at a surface of an object. Thus, a CVD method and an ALD method enable favorable step coverage almost regardless of the shape of an object. In particular, an ALD method enables excellent step coverage and excellent thickness uniformity and can be favorably used for covering a surface of an opening portion with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate; thus, it is sometimes preferable to combine an ALD method with another deposition method with a high deposition rate such as a CVD method. 
     When a CVD method or an ALD method is used, composition of a film to be formed can be controlled with a flow rate ratio of the source gases. For example, by the CVD method or the ALD method, a film with a desired composition can be formed by adjusting the flow ratio of a source gas. Moreover, with a CVD method or an ALD method, by changing the flow rate ratio of the source gases while forming the film, a film whose composition is continuously changed can be formed. In the case where the film is formed while changing the flow rate ratio of the source gases, as compared to the case where the film is formed using a plurality of deposition chambers, time taken for the deposition can be reduced because time taken for transfer and pressure adjustment is omitted. Thus, semiconductor devices can be manufactured with improved productivity. 
     Next, a resist or the like is formed over the conductor and processing is performed using the resist, whereby a conductor  413  is formed. Note that the case where the resist is simply formed also includes the case where a BARC is formed below the resist. 
     The resist is removed after the object is processed by etching or the like. For the removal of the resist, plasma treatment and/or wet etching are/is used. Note that as the plasma treatment, plasma ashing is preferable. In the case where the removal of the resist or the like is not enough, the remaining resist or the like may be removed using ozone water and/or hydrofluoric acid at a concentration higher than or equal to 0.001 volume % and lower than or equal to 1 volume %, and the like. 
     The conductor to be the conductor  413  may be formed to have a single-layer structure or a stacked-layer structure using a conductor containing, for example, one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. 
     Then, an insulator  402  is formed (see  FIGS. 2A and 2B ). The insulator  402  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     The insulator  402  may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  402  may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     The insulator  402  preferably includes excess oxygen and/or a hydrogen trap. 
     Here, an insulator including excess oxygen may release oxygen, the amount of which is higher than or equal to 1×10 18  atoms/cm 3 , higher than or equal to 1×10 19  atoms/cm 3 , or higher than or equal to 1×10 20  atoms/cm 3  (converted into the number of oxygen atoms) in thermal desorption spectroscopy (TDS) analysis in the range of a film surface temperature of 100° C. to 700° C. or 100° C. to 500° C. 
     The method of measuring the amount of released oxygen using TDS analysis is described below. 
     The total amount of released gas from a measurement sample in TDS analysis is proportional to the integral value of the ion intensity of the released gas. Then, comparison with a reference sample is made, whereby the total amount of released gas can be calculated. 
     For example, the number of released oxygen molecules (N O2 ) from a measurement sample can be calculated according to the following formula using the TDS results of a silicon substrate containing hydrogen at a predetermined density, which is a reference sample, and the TDS results of the measurement sample. Here, all gases having a mass-to-charge ratio of 32 which are obtained in the TDS analysis are assumed to originate from an oxygen molecule. Note that CH 3 OH, which is a gas having the mass-to-charge ratio of 32, is not taken into consideration because it is unlikely to be present. Furthermore, an oxygen molecule including an oxygen atom having a mass number of 17 or 18 which is an isotope of an oxygen atom is also not taken into consideration because the proportion of such a molecule in the natural world is minimal. 
         N   O2   =N   H2   /S   H2   ×S   O2 ×α
 
     The value N H2  is obtained by conversion of the number of hydrogen molecules desorbed from the reference sample into densities. The value S H2  is the integral value of ion intensity in the case where the reference sample is subjected to the TDS analysis. Here, the reference value of the reference sample is set to N H2 /S H2 . The value Sot is the integral value of ion intensity when the measurement sample is analyzed by TDS. The value a is a coefficient affecting the ion intensity in the TDS analysis. Refer to Japanese Published Patent Application No. H6-275697 for details of the above formula. The amount of released oxygen was measured with a thermal desorption spectroscopy apparatus produced by ESCO Ltd., EMD-WA1000S/W using a silicon substrate containing a certain amount of hydrogen atoms as the reference sample. 
     Furthermore, in the TDS analysis, oxygen is partly detected as an oxygen atom. The ratio between oxygen molecules and oxygen atoms can be calculated from the ionization rate of the oxygen molecules. Note that, since the above a includes the ionization rate of the oxygen molecules, the number of the released oxygen atoms can also be estimated through the evaluation of the number of the released oxygen molecules. 
     Note that N O2  is the number of the released oxygen molecules. The number of released oxygen in the case of being converted into oxygen atoms is twice the number of the released oxygen molecules. 
     Furthermore, the insulator from which oxygen is released by heat treatment may contain a peroxide radical. Specifically, the spin density of a signal attributed to the peroxide radical is greater than or equal to 5×10 17  spins/cm 3 . Note that the insulator containing a peroxide radical may have an asymmetric signal with a g factor of approximately 2.01 in electron spin resonance (ESR). 
     The insulator  402  may have a function of preventing diffusion of impurities from the substrate  400  and the like. 
     Next, a semiconductor to be the semiconductor  406   a  is formed. The semiconductor to be the semiconductor  406   a  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     Next, oxygen may be added so that a semiconductor to be the semiconductor  406   a  contains excess oxygen. The addition of oxygen may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 2 kV and less than or equal to 10 kV at a dose of greater than or equal to 5×10 14  ions/cm 2  and less than or equal to 1×10 17  ions/cm 2 , for example. 
     Then, fluorine may be added to the semiconductor to be the semiconductor  406   a . Note that the addition of oxygen to the semiconductor to be the semiconductor  406   a  and the addition of fluorine to the semiconductor to be the semiconductor  406   a  may be performed in reverse order. 
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Next, a semiconductor to be the semiconductor  406   b  is formed. The semiconductor to be the semiconductor  406   b  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the semiconductor to be the semiconductor  406   a  and the semiconductor to be the semiconductor  406   b  are successively formed without being exposed to the air, in which case impurities can be prevented from entering the films and the interface therebetween. 
     Next, heat treatment is preferably performed. The heat treatment can reduce hydrogen concentration in the semiconductor to be the semiconductor  406   a  and in the semiconductor to be the semiconductor  406   b  in some cases. In addition, the heat treatment can reduce oxygen vacancies in the semiconductor to be the semiconductor  406   a  and in the semiconductor to be the semiconductor  406   b  in some cases. The heat treatment may be performed at higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 450° C. and lower than or equal to 600° C., more preferably higher than or equal to 520° C. and lower than or equal to 570° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to fill desorbed oxygen. By the heat treatment, crystallinity of the semiconductor to be the semiconductor  406   a  and crystallinity of the semiconductor to be the semiconductor  406   b  can be increased and impurities such as hydrogen and water can be removed. 
     Then, fluorine may be added to the semiconductor to be the semiconductor  406   a  and the semiconductor to be the semiconductor  406   b . Note that the heat treatment on the semiconductor to be the semiconductor  406   a  and the semiconductor to be the semiconductor  406   b  and the addition of fluorine to the semiconductor to be the semiconductor  406   a  and the semiconductor to be the semiconductor  406   b  may be performed in reverse order. 
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Then, a resist or the like is formed over the semiconductor to be the semiconductor  406   b  and processing is performed using the resist, whereby the semiconductor  406   a  and the semiconductor  406   b  are formed (see  FIGS. 3A and 3B ). 
     Next, a conductor is formed. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     The conductor may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. 
     Next, a resist or the like is formed over the conductor, and the conductor is processed into a conductor  416   a  and a conductor  416   b  using the resist (see  FIGS. 4A and 4B ). 
     Then, fluorine may be added to the semiconductor  406   a  and the semiconductor  406   b . The addition of fluorine can be performed using the conductor  416   a  and the conductor  416   b  as masks. Accordingly, in the semiconductors  406   a  and  406   b , fluorine can be selectively added to a region which does not overlap with the conductors  416   a  and  416   b.    
     When the thicknesses of the conductors  416   a  and  416   b  are reduced, for example, fluorine may also be added to regions overlapping with the conductors  416   a  and  416   b  in the semiconductors  406   a  and  406   b . Accordingly, the semiconductors  406   a  and  406   b  in which regions overlapping with the conductors  416   a  and  416   b  and a region not overlapping with the conductors  416   a  and  416   b  have different fluorine concentrations can be formed. For example, in the semiconductors  406   a  and  406   b , the fluorine concentration of the regions overlapping with the conductors  416   a  and  416   b  is lower than that of the region not overlapping with the conductors  416   a  and  416   b.    
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Here, for example, when the conductor  413 , the insulator  402 , the conductor  416   a , and the conductor  416   b  serve as a gate electrode, a gate insulator, a source electrode, and a drain electrode, respectively, a bottom-gate transistor may be obtained by completing the steps up to  FIGS. 4A and 4B . 
     Next, a semiconductor  436   c  is formed. The semiconductor  436   c  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Before the formation of the semiconductor  436   c , surfaces of the semiconductor  406   a , the semiconductor  406   b , the conductor  416   a , and the conductor  416   b  may be etched. For example, plasma containing a rare gas can be used for the etching. After that, the semiconductor  436   c  is successively formed without being exposed to the air, whereby impurities can be prevented from entering interfaces between the semiconductor  436   c  and the semiconductor  406   a , the semiconductor  406   b , the conductor  416   a , or the conductor  416   b . In some cases, impurities at an interface between films are diffused more easily than impurities in a film. For this reason, a reduction in impurity at the interfaces leads to stable electrical characteristics of a transistor. 
     Then, fluorine may be added to the semiconductor  406   a , the semiconductor  406   b , and the semiconductor  436   c . Note that fluorine is not necessarily added to all of the semiconductors  406   a ,  406   b , and  436   c , and fluorine may be added to any one or two of these layers. 
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Next, an insulator  442  is formed. The insulator  442  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the semiconductor  436   c  and the insulator  442  are successively formed without being exposed to the air, in which case impurities can be prevented from entering the films and the interface therebetween. 
     The insulator  442  may have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  442  may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     Then, fluorine may be added to the semiconductor  406   a , the semiconductor  406   b , and the semiconductor  436   c  through the insulator  442 . Note that fluorine is not necessarily added to all of the semiconductors  406   a ,  406   b , and  436   c , and fluorine may be added to any one or two of these layers. In addition, fluorine may be added to the insulator  442 . 
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Next, a conductor  434  is formed. The conductor  434  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulator  442  and the conductor  434  are successively formed without being exposed to the air, in which case impurities can be prevented from entering the films and the interface therebetween (see  FIGS. 5A and 5B ). 
     The conductor  434  may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. 
     Then, a resist or the like is formed over the conductor  434  and the conductor  434  is processed into a conductor  404  using the resist. The insulator  442  is processed into an insulator  412  using the resist or the conductor  404 . The semiconductor  436   c  is processed into a semiconductor  406   c  using the resist, the conductor  404 , or the insulator  412 . The semiconductor  406   c , the insulator  412 , and the conductor  404  have the same shape when seen from the above, but a transistor of one embodiment of the present invention is not limited to this shape. For example, the semiconductor  406   c , the insulator  412 , and the conductor  404  may be processed using different resists. For example, after the insulator  412  is formed, the conductor to be the conductor  404  may be formed; or after the conductor  404  is formed, a resist or the like may be formed over the insulator to be the insulator  412 . For example, the semiconductor  406   c  may be shared between adjacent transistors or the like (see  FIGS. 6A and 6B ). 
     Next, an insulator may be formed. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     The insulator may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, aluminum oxide, silicon nitride oxide, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     The insulator preferably has a function of a barrier layer. The insulator has, for example, a function of blocking oxygen and/or hydrogen. Alternatively, the insulator preferably has a higher capability of blocking oxygen and/or hydrogen than the insulator  402  and the insulator  412 , for example. 
     Through the above process, the transistor  100  of one embodiment of the present invention can be manufactured. 
     As described above, fluorine is added to a channel formation region of a semiconductor, whereby oxygen vacancies in the semiconductor can be filled. Oxygen vacancies are filled with fluorine, which forms a stable bond, whereby a transistor having stable and favorable electrical characteristics can be provided. 
     As illustrated in  FIG. 6B , the semiconductor  406   b  can be electrically surrounded by an electric field of the conductor  404  and the conductor  413  (a structure in which a semiconductor is electrically surrounded by an electric field of a conductor is referred to as a surrounded channel (s-channel) structure). Therefore, a channel is formed in the entire semiconductor  406   b  (the top, bottom, and side surfaces). In the s-channel structure, a large amount of current can flow between a source and a drain of the transistor, so that a high on-state current can be achieved. 
     In the case where the transistor has the s-channel structure, a channel is formed also in the side surface of the semiconductor  406   b . Therefore, as the semiconductor  406   b  has a larger thickness, the channel formation region becomes larger. In other words, the thicker the semiconductor  406   b  is, the larger the on-state current of the transistor is. In addition, when the semiconductor  406   b  is thicker, the proportion of the region with a high carrier controllability increases, leading to a smaller subthreshold swing value. For example, the semiconductor  406   b  has a region with a thickness greater than or equal to 10 nm, preferably greater than or equal to 20 nm, further preferably greater than or equal to 40 nm, still further preferably greater than or equal to 100 nm. In addition, to prevent a decrease in the productivity of the semiconductor device, the semiconductor  406   b  has a region with a thickness, for example, less than or equal to 300 nm, preferably less than or equal to 200 nm, further preferably less than or equal to 150 nm. 
     The s-channel structure is suitable for a miniaturized transistor because a high on-state current can be achieved. A semiconductor device including the miniaturized transistor can have a high integration degree and high density. For example, the transistor includes a region having a channel length of preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, still further preferably less than or equal to 20 nm and a region having a channel width of preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, still further preferably less than or equal to 20 nm. 
     Note that the conductor  413  is not necessarily formed (see  FIG. 7A ). Furthermore, an edge of the insulator  412  and an edge of the semiconductor  406   c  may extend beyond an edge of the conductor  404  (see  FIG. 7B ). The insulator  442  and the semiconductor  436   c  are not necessarily processed (see  FIG. 7C ). In the A 1 -A 2  cross section, the width of the conductor  413  may be larger than that of the semiconductor  406   b  (see  FIG. 8A ). The conductor  413  may be in contact with the conductor  404  through an opening (see  FIG. 8B ). The conductor  404  is not necessarily formed (see  FIG. 8C ). 
     &lt;Semiconductor&gt; 
     As described in this embodiment, by placing the semiconductor  406   a  over the semiconductor  406   b  and placing the semiconductor  406   c  under the semiconductor  406   b , electrical characteristics of the transistor can be increased in some cases. 
     The semiconductor  406   b  is an oxide semiconductor containing indium, for example. The oxide semiconductor  406   b  can have high carrier mobility (electron mobility) by containing indium, for example. The semiconductor  406   b  preferably contains an element M. The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements which can be used as the element M are boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like. Note that two or more of the above elements may be used in combination as the element M. The element M is an element having high bonding energy with oxygen, for example. The element M is an element whose bonding energy with oxygen is higher than that of indium. The element M is an element that can increase the energy gap of the oxide semiconductor, for example. Furthermore, the semiconductor  406   b  preferably contains zinc. When the oxide semiconductor contains zinc, the oxide semiconductor is easily crystallized, in some cases. 
     Note that the semiconductor  406   b  is not limited to the oxide semiconductor containing indium. The semiconductor  406   b  may be, for example, an oxide semiconductor which does not contain indium and contains zinc, an oxide semiconductor which does not contain indium and contains gallium, or an oxide semiconductor which does not contain indium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide. 
     For the semiconductor  406   b , an oxide with a wide energy gap may be used, for example. For example, the energy gap of the semiconductor  406   b  is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, further preferably greater than or equal to 3 eV and less than or equal to 3.5 eV. 
     For example, the semiconductor  406   a  and the semiconductor  406   c  are oxide semiconductors including one or more elements, or two or more elements other than oxygen included in the semiconductor  406   b . Since the semiconductor  406   a  and the semiconductor  406   c  each include one or more elements, or two or more elements other than oxygen included in the semiconductor  406   b , a defect state is less likely to be formed at the interface between the semiconductor  406   a  and the semiconductor  406   b  and the interface between the semiconductor  406   b  and the semiconductor  406   c.    
     The semiconductor  406   a , the semiconductor  406   b , and the semiconductor  406   c  preferably include at least indium. In the case of using an In-M-Zn oxide as the semiconductor  406   a , when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, further preferably less than 25 atomic % and greater than 75 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor  406   b , when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be greater than 25 atomic % and less than 75 atomic %, respectively, further preferably greater than 34 atomic % and less than 66 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor  406   c , when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, further preferably less than 25 atomic % and greater than 75 atomic %, respectively. Note that the semiconductor  406   c  may be an oxide that is of the same type as the oxide of the semiconductor  406   a . Note that the semiconductor  406   a  and/or the semiconductor  406   c  do/does not necessarily contain indium in some cases. For example, the semiconductor  406   a  and/or the semiconductor  406   c  may be gallium oxide. Note that the atomic ratios of the elements included in the semiconductor  406   a , the semiconductor  406   b , and the semiconductor  406   c  are not necessarily simple ratios of integers. 
     As the semiconductor  406   b , an oxide having an electron affinity higher than those of the semiconductors  406   a  and  406   c  is used. For example, as the semiconductor  406   b , an oxide having an electron affinity higher than those of the semiconductors  406   a  and  406   c  by 0.07 eV or higher and 1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, further preferably 0.15 eV or higher and 0.4 eV or lower is used. Note that the electron affinity refers to an energy difference between the vacuum level and the bottom of the conduction band. 
     An indium gallium oxide has small electron affinity and a high oxygen-blocking property. Therefore, the semiconductor  406   c  preferably includes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, higher than or equal to 70%, preferably higher than or equal to 80%, further preferably higher than or equal to 90%. 
     In the transistor in which the semiconductor  406   a  and the semiconductor  406   c  are placed over and under the semiconductor  406   b  as described above, when a gate voltage is applied, a channel is formed in the semiconductor  406   b  having the highest electron affinity in the semiconductors  406   a ,  406   b , and  406   c.    
     Here, in some cases, there is a mixed region of the semiconductor  406   a  and the semiconductor  406   b  between the semiconductor  406   a  and the semiconductor  406   b . Furthermore, in some cases, there is a mixed region of the semiconductor  406   b  and the semiconductor  406   c  between the semiconductor  406   b  and the semiconductor  406   c . The mixed region has a low density of defect states. For that reason, the stack including the semiconductor  406   a , the semiconductor  406   b , and the semiconductor  406   c  has a band structure where energy is changed continuously at each interface and in the vicinity of the interface (continuous junction) (see  FIG. 9 ). Note that boundaries of the semiconductor  406   a , the semiconductor  406   b , and the semiconductor  406   c  are not clear in some cases. 
     At this time, electrons move mainly in the semiconductor  406   b , not in the semiconductor  406   a  and the semiconductor  406   c . As described above, when the density of defect states at the interface between the semiconductor  406   a  and the semiconductor  406   b  and the density of defect states at the interface between the semiconductor  406   b  and the semiconductor  406   c  are decreased, electron movement in the semiconductor  406   b  is less likely to be inhibited and the on-sate current of the transistor can be increased. 
     As factors of inhibiting electron movement are decreased, the on-state current of the transistor can be increased. For example, in the case where there is no factor of inhibiting electron movement, electrons are assumed to be efficiently moved. Electron movement is inhibited, for example, in the case where physical unevenness of the channel formation region is large. 
     To increase the on-state current of the transistor, for example, root mean square (RMS) roughness with a measurement area of 1 μm×1 μm of a top surface or a bottom surface (a formation surface; here, the semiconductor  406   a ) of the semiconductor  406   b  is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) with the measurement area of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm. The maximum difference (P−V) with the measurement area of 1 μm×1 μm is less than 10 nm, preferably less than 9 nm, further preferably less than 8 nm, still further preferably less than 7 nm. RMS roughness, Ra, and P−V can be measured using a scanning probe microscope SPA-500 manufactured by SII Nano Technology Inc. 
     Moreover, the thickness of the semiconductor  406   c  is preferably as small as possible to increase the on-state current of the transistor. For example, the semiconductor  406   c  is formed to have a region with a thickness of less than 10 nm, preferably less than or equal to 5 nm, further preferably less than or equal to 3 nm. Meanwhile, the semiconductor  406   c  has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor  406   b  where a channel is formed. For this reason, it is preferable that the semiconductor  406   c  have a certain thickness. For example, the semiconductor  406   c  is formed to have a region with a thickness of greater than or equal to 0.3 nm, preferably greater than or equal to 1 nm, further preferably greater than or equal to 2 nm. The semiconductor  406   c  preferably has an oxygen blocking property to suppress outward diffusion of oxygen released from the insulator  402  and the like. 
     To improve reliability, preferably, the thickness of the semiconductor  406   a  is large and the thickness of the semiconductor  406   c  is small. For example, the semiconductor  406   a  has a region with a thickness of, for example, greater than or equal to 10 nm, preferably greater than or equal to 20 nm, further preferably greater than or equal to 40 nm, still further preferably greater than or equal to 60 nm. When the thickness of the semiconductor  406   a  is made large, a distance from an interface between the adjacent insulator and the semiconductor  406   a  to the semiconductor  406   b  in which a channel is formed can be large. Since the productivity of the semiconductor device might be decreased, the semiconductor  406   a  has a region with a thickness of, for example, less than or equal to 200 nm, preferably less than or equal to 120 nm, further preferably less than or equal to 80 nm. 
     For example, a region with a silicon concentration measured by secondary ion mass spectrometry (SIMS) of higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 1×10 19  atoms/cm 3 , preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 , further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 2×10 18  atoms/cm 3  is provided between the semiconductor  406   b  and the semiconductor  406   a . A region with a silicon concentration measured by SIMS of higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 1×10 19  atoms/cm 3 , preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 , further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 2×10 18  atoms/cm 3  is provided between the semiconductor  406   b  and the semiconductor  406   c.    
     It is preferable to reduce the hydrogen concentration in the semiconductor  406   a  and the semiconductor  406   c  in order to reduce the hydrogen concentration in the semiconductor  406   b . The semiconductor  406   a  and the semiconductor  406   c  each include a region with a hydrogen concentration measured by SIMS of higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 2×10 20  atoms/cm 3 , preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 19  atoms/cm 3 , further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 1×10 19  atoms/cm 3 , or still further preferably higher than or equal to 1×10 16  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 . It is preferable to reduce the nitrogen concentration in the semiconductor  406   a  and the semiconductor  406   c  in order to reduce the nitrogen concentration in the semiconductor  406   b . The semiconductor  406   a  and the semiconductor  406   c  includes a region with a nitrogen concentration measured by SIMS of higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 19  atoms/cm 3 , preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 18  atoms/cm 3 , further preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 1×10 18  atoms/cm 3 , or still further preferably higher than or equal to 1×10 15  atoms/cm 3  and lower than or equal to 5×10 17  atoms/cm 3 . 
     The above three-layer structure is an example. For example, a two-layer structure without the semiconductor  406   a  or the semiconductor  406   c  may be employed. Alternatively, a four-layer structure in which any one of the semiconductors described as examples of the semiconductor  406   a , the semiconductor  406   b , and the semiconductor  406   c  is provided under or over the semiconductor  406   a  or under or over the semiconductor  406   c  may be employed. An n-layer structure (n is an integer of 5 or more) in which one or more of the semiconductors described as examples of the semiconductor  406   a , the semiconductor  406   b , and the semiconductor  406   c  is provided at two or more of the following positions: over the semiconductor  406   a , under the semiconductor  406   a , over the semiconductor  406   c , and under the semiconductor  406   c.    
     &lt;Structure of Oxide Semiconductor&gt; 
     A structure of an oxide semiconductor is described below. 
     An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. 
     From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and a microcrystalline oxide semiconductor. 
     First, a CAAC-OS is described. Note that a CAAC-OS can be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). 
     A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets). 
     In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur. 
     A CAAC-OS observed with TEM is described below.  FIG. 10A  shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. 
       FIG. 10B  is an enlarged Cs-corrected high-resolution TEM image of a region (1) in  FIG. 10A .  FIG. 10B  shows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration reflecting unevenness of a surface over which the CAAC-OS is formed (hereinafter, the surface is referred to as a formation surface) or a top surface of the CAAC-OS, and is arranged parallel to the formation surface or the top surface of the CAAC-OS. 
     As shown in  FIG. 10B , the CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is denoted by an auxiliary line in  FIG. 10C .  FIGS. 10B and 10C  prove that the size of a pellet is approximately 1 nm to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). 
     Here, according to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets  5100  of a CAAC-OS over a substrate  5120  is illustrated by such a structure in which bricks or blocks are stacked (see  FIG. 10D ). The part in which the pellets are tilted as observed in  FIG. 10C  corresponds to a region  5161  shown in  FIG. 10D . 
       FIG. 11A  shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.  FIGS. 11B, 11C, and 11D  are enlarged Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in  FIG. 11A , respectively.  FIGS. 11B, 11C, and 11D  indicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets. 
     Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO 4  crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in  FIG. 12A . This peak is derived from the (009) plane of the InGaZnO 4  crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. 
     Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when 2θ is around 36°, in addition to the peak at 2θ of around 31°. The peak at 2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. It is preferable that in the CAAC-OS analyzed by an out-of-plane method, a peak appear when 2θ is around 31° and that a peak not appear when 2θ is around 36°. 
     On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when 2θ is around 56°. This peak is attributed to the (110) plane of the InGaZnO 4  crystal. In the case of the CAAC-OS, when analysis (ϕ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector of the sample surface as an axis (0 axis), as shown in  FIG. 12B , a peak is not clearly observed. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO 4 , when 0 scan is performed with 2θ fixed at around 56°, as shown in  FIG. 12C , six peaks which are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS. 
     Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO 4  crystal in a direction parallel to the sample surface, a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shown in  FIG. 13A  can be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO 4  crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile,  FIG. 13B  shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in  FIG. 13B , a ring-like diffraction pattern is observed. Thus, the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring in  FIG. 13B  is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO 4  crystal. The second ring in  FIG. 13B  is considered to be derived from the (110) plane and the like. 
     Moreover, the CAAC-OS is an oxide semiconductor having a low density of defect states. Defects in the oxide semiconductor are, for example, a defect due to impurities and oxygen vacancies. Therefore, the CAAC-OS can be regarded as an oxide semiconductor with a low impurity concentration, or an oxide semiconductor having a small number of oxygen vacancies. 
     The impurity contained in the oxide semiconductor might serve as a carrier trap or serve as a carrier generation source. Furthermore, oxygen vacancies in the oxide semiconductor serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein. 
     Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity. 
     An oxide semiconductor having a low density of defect states (a small number of oxygen vacancies) can have a low carrier density. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. That is, a CAAC-OS is likely to be highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Thus, a transistor including a CAAC-OS rarely has negative threshold voltage (is rarely normally on). The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier traps. An electric charge trapped by the carrier traps in the oxide semiconductor takes a long time to be released. The trapped electric charge may behave like a fixed electric charge. Thus, the transistor which includes the oxide semiconductor having a high impurity concentration and a high density of defect states might have unstable electrical characteristics. However, a transistor including a CAAC-OS has small variation in electrical characteristics and high reliability. 
     Since the CAAC-OS has a low density of defect states, carriers generated by light irradiation or the like are less likely to be trapped in defect states. Therefore, in a transistor using the CAAC-OS, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. 
     &lt;Microcrystalline Oxide Semiconductor&gt; 
     Next, a microcrystalline oxide semiconductor is described. 
     A microcrystalline oxide semiconductor has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the microcrystalline oxide semiconductor is greater than or equal to 1 nm and less than or equal to 100 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. An oxide semiconductor including a nanocrystal (nc) that is a microcrystal with a size greater than or equal to 1 nm and less than or equal to 10 nm, or a size greater than or equal to 1 nm and less than or equal to 3 nm is specifically referred to as a nanocrystalline oxide semiconductor (nc-OS). In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description. 
     In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an amorphous oxide semiconductor, depending on an analysis method. For example, when the nc-OS is subjected to structural analysis by an out-of-plane method with an XRD apparatus using an X-ray having a diameter larger than the size of a pellet, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet (the electron diffraction is also referred to as selected-area electron diffraction). Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots is shown in a ring-like region in some cases. 
     Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC). 
     The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS. 
     &lt;Amorphous Oxide Semiconductor&gt; 
     Next, an amorphous oxide semiconductor is described. 
     The amorphous oxide semiconductor is an oxide semiconductor having disordered atomic arrangement and no crystal part and exemplified by an oxide semiconductor which exists in an amorphous state as quartz. 
     In a high-resolution TEM image of the amorphous oxide semiconductor, crystal parts cannot be found. 
     When the amorphous oxide semiconductor is subjected to structural analysis by an out-of-plane method with an XRD apparatus, a peak which shows a crystal plane does not appear. A halo pattern is observed when the amorphous oxide semiconductor is subjected to electron diffraction. Furthermore, a spot is not observed and only a halo pattern appears when the amorphous oxide semiconductor is subjected to nanobeam electron diffraction. 
     There are various understandings of an amorphous structure. For example, a structure whose atomic arrangement does not have ordering at all is called a completely amorphous structure. Meanwhile, a structure which does not have long-range ordering but has ordering in a range from an atom to the nearest neighbor atoms or to the second-nearest neighbor atoms is also called an amorphous structure. Therefore, the strictest definition does not permit an oxide semiconductor to be called an amorphous oxide semiconductor as long as even a negligible degree of ordering is present in an atomic arrangement. At least an oxide semiconductor having long-term ordering cannot be called an amorphous oxide semiconductor. Accordingly, because of the presence of crystal part, for example, a CAAC-OS and an nc-OS cannot be called an amorphous oxide semiconductor or a completely amorphous oxide semiconductor. 
     &lt;Amorphous-Like Oxide Semiconductor&gt; 
     Note that an oxide semiconductor may have a structure intermediate between the nc-OS and the amorphous oxide semiconductor. The oxide semiconductor having such a structure is specifically referred to as an amorphous-like oxide semiconductor (a-like OS). 
     In a high-resolution TEM image of the a-like OS, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed. 
     The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below. 
     An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In-Ga—Zn oxide. 
     First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts. 
     Note that which part is regarded as a crystal part is determined as follows. It is known that a unit cell of an InGaZnO 4  crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO 4 . Each of lattice fringes corresponds to the a-b plane of the InGaZnO 4  crystal. 
       FIG. 14  shows change in the average size of crystal parts (at 22 points to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe.  FIG. 14  indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by (1) in  FIG. 14 , a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2×10 8  e − /nm 2 . In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×10 8  e − /nm 2 . Specifically, as shown by (2) and (3) in  FIG. 14 , the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose. 
     In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS. 
     The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor. 
     For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO 4  with a rhombohedral crystal structure is 6.357 g/cm 3 . Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm 3  and lower than 5.9 g/cm 3 . For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm 3  and lower than 6.3 g/cm 3 . 
     Note that there is a possibility that an oxide semiconductor having a certain composition cannot exist in a single crystal structure. In that case, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density. 
     As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more films of an amorphous oxide semiconductor, an a-like OS, a microcrystalline oxide semiconductor, and a CAAC-OS, for example. 
     Embodiment 2 
     In this embodiment, a method for manufacturing a transistor whose shape is partly different from that of the transistor in Embodiment 1 is described. 
     &lt;Transistor  2 &gt; 
       FIG. 15A ,  FIG. 16A ,  FIG. 17A ,  FIG. 18A ,  FIG. 19A ,  FIG. 20A , and  FIG. 21A  are top views illustrating a method for manufacturing a transistor.  FIG. 15B ,  FIG. 16B ,  FIG. 17B ,  FIG. 18B ,  FIG. 19B ,  FIG. 20B , and  FIG. 21B  are each a cross-sectional view taken along dashed dotted lines F 1 -F 2  and F 3 -F 4  shown in the corresponding top view. 
     First, a substrate  500  is prepared. For the substrate  500 , the description of the substrate  400  is referred to. 
     Next, a conductor is formed. The conductor may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     Next, a resist or the like is formed over the conductor and the conductor is processed into a conductor  513  using the resist. 
     Next, an insulator is formed. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     Next, etching is performed from the top surface of the insulator toward the bottom surface thereof such that the etched surface is parallel to the bottom surface of the substrate  500  and the conductor  513  is exposed, whereby an insulator  503  is formed (see  FIGS. 15A and 15B ). When the insulator  503  is formed in this way, the top surface of the conductor  513  can be positioned at substantially the same level as the top surface of the insulator  503 . Therefore, a defect in shape in a later step can be inhibited. 
     Then, an insulator  502  is formed (see  FIGS. 16A and 16B ). The insulator  502  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulator  502 , the description of the insulator  402  is referred to. 
     Next, a semiconductor  536   a  is formed. The semiconductor  536   a  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the semiconductor  536   a , the description of the semiconductor to be the semiconductor  406   a  is referred to. 
     Next, oxygen may be added so that the semiconductor  536   a  contains excess oxygen. The addition of oxygen may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 2 kV and less than or equal to 10 kV at a dose of greater than or equal to 5×10 14  ions/cm 2  and less than or equal to 1×10 17  ions/cm 2 , for example. 
     Then, fluorine may be added to the semiconductor  536   a . Note that the addition of oxygen to the semiconductor  536   a  and the addition of fluorine to the semiconductor  536   a  may be performed in reverse order. 
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Next, a semiconductor  536   b  is formed. The semiconductor  536   b  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the semiconductor  536   b , the description of the semiconductor to be the semiconductor  406   b  is referred to. Note that the semiconductor  536   a  and the semiconductor  536   b  are successively formed without being exposed to the air, in which case impurities can be prevented from entering the films and the interface therebetween. 
     Next, heat treatment is preferably performed. The heat treatment may be performed at higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 450° C. and lower than or equal to 600° C., more preferably higher than or equal to 520° C. and lower than or equal to 570° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to fill desorbed oxygen. By the heat treatment, crystallinity of the semiconductor  536   a  and crystallinity of the semiconductor  536   b  can be increased and impurities such as hydrogen and water can be removed. 
     Then, fluorine may be added to the semiconductor  536   a  and the semiconductor  536   b . Note that the heat treatment on the semiconductor  536   a  and the semiconductor  536   b  and the addition of fluorine to the semiconductor  536   a  and the semiconductor  536   b  may be performed in reverse order. 
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Next, a conductor is formed. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The description of the conductor to be the conductor  416   a  and the conductor  416   b  is referred to for the conductor. 
     Next, a resist or the like is formed over the conductor, and the conductor is processed into a conductor  516   a  and a conductor  516   b  using the resist (see  FIGS. 17A and 17B ). 
     Then, fluorine may be added to the semiconductor  536   a  and the semiconductor  536   b . The addition of fluorine can be performed using the conductor  516   a  and the conductor  516   b  as masks. Accordingly, in the semiconductors  536   a  and  536   b , fluorine can be selectively added to a region which does not overlap with the conductors  516   a  and  516   b.    
     When the thicknesses of the conductors  516   a  and  516   b  are reduced, for example, fluorine may also be added to regions overlapping with the conductors  516   a  and  516   b  in the semiconductors  536   a  and  536   b . Accordingly, the semiconductors  536   a  and  536   b  in which regions overlapping with the conductors  516   a  and  516   b  and a region not overlapping with the conductors  516   a  and  516   b  have different fluorine concentrations can be formed. For example, in the semiconductors  536   a  and  536   b , the fluorine concentration of the regions overlapping with the conductors  516   a  and  516   b  is lower than that of the region not overlapping with the conductors  516   a  and  516   b.    
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Then, a resist or the like is formed over the semiconductor  536   b  and processing is performed using the resist, the conductor  516   a , and the conductor  516   b , whereby a semiconductor  506   a  and a semiconductor  506   b  are formed (see  FIGS. 18A and 18B ). 
     Note that the conductor  516   a , the conductor  516   b , the semiconductor  506   a , and the semiconductor  506   b  may be formed in the following manner after the formation of the conductor. 
     First, a resist or the like is formed over the conductor, and processing is performed using the resist, whereby the conductor  516 , the semiconductor  506   b , and the semiconductor  506   a  are formed (see  FIGS. 21A and 21B ). At this time, the semiconductor  506   a  and the semiconductor  506   b  may be formed using the conductor  516  after the resist is removed. 
     Next, a resist or the like is formed over the conductor  516 , and the conductor is processed into the conductor  516   a  and the conductor  516   b  using the resist (see  FIGS. 18A and 18B ). 
     Next, a semiconductor  536   c  is formed. The semiconductor  536   c  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the semiconductor  536   c , the description of the semiconductor  436   c  is referred to. 
     Next, an insulator  542  is formed. The insulator  542  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulator  542 , the description of the insulator  442  is referred to. 
     Then, fluorine may be added to the semiconductor  506   a , the semiconductor  506   b , and the semiconductor  536   c  through the insulator  542 . Note that fluorine is not necessarily added to all of the semiconductors  506   a ,  506   b , and  536   c , and fluorine may be added to any one or two of these layers. In addition, fluorine may be added to the insulator  542 . 
     The addition of fluorine may be performed by an ion implantation method at an acceleration voltage of greater than or equal to 1 kV and less than or equal to 200 kV, preferably greater than or equal to 5 kV and less than or equal to 100 kV at a dose of greater than or equal to 5×10 19  ions/cm 3  and less than or equal to 5×10 22  ions/cm 3 , preferably greater than or equal to 1×10 20  ions/cm 3  and less than or equal to 1×10 22  ions/cm 3 , for example. 
     Next, a conductor  534  is formed (see  FIGS. 19A and 19B ). The conductor  534  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the conductor  534 , the description of the conductor  434  is referred to. 
     Then, a resist or the like is formed over the conductor  534  and the conductor  534  is processed into a conductor  504  using the resist. The insulator  542  is processed into an insulator  512  using the resist or the conductor  504 . The semiconductor  536   c  is processed into a semiconductor  506   c  using the resist, the conductor  504 , or the insulator  542  (see  FIGS. 20A and 20B ). Note that here, the semiconductor  506   c , the insulator  512 , and the conductor  504  have the same shape when seen from the above, but a transistor of one embodiment of the present invention is not limited to this shape. For example, the insulator  512  and the conductor  504  may be processed using different resists. For example, after the insulator  512  is formed, the conductor to be the conductor  504  may be formed; or after the conductor  504  is formed, a resist or the like may be formed over the insulator to be the insulator  512 . For example, the semiconductor  506   c  may be shared between adjacent transistors or the like. 
     Next, an insulator may be formed. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     The insulator may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator is preferably formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, aluminum oxide, silicon nitride oxide, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     The insulator preferably has a function of a barrier layer. The insulator has, for example, a function of blocking oxygen and/or hydrogen. Alternatively, the insulator preferably has a higher capability of blocking oxygen and/or hydrogen than the insulator  502  and the insulator  512 , for example. 
     Through the above process, the transistor of one embodiment of the present invention can be manufactured. 
     As described above, fluorine is added to a channel formation region of a semiconductor, whereby oxygen vacancies in the semiconductor can be filled. Oxygen vacancies are filled with fluorine, which forms a stable bond, whereby a transistor having stable and favorable electrical characteristics can be provided. 
     As illustrated in  FIG. 20B , the transistor has an s-channel structure. The electric field from the conductor  504  and the conductor  513  is less likely to be inhibited by the conductor  516   a , the conductor  516   b , and the like at the side surface of the semiconductor  506   b.    
     Note that the conductor  513  is not necessarily formed (see  FIG. 22A ). Furthermore, an edge of the insulator  512  and an edge of the semiconductor  506   c  may extend beyond an edge of the conductor  504  (see  FIG. 22B ). The insulator  542  and the semiconductor  536   c  are not necessarily processed (see  FIG. 22C ). In the F 1 -F 2  cross section, the width of the conductor  513  may be larger than that of the semiconductor  506   b  (see  FIG. 23A ). The conductor  513  may be in contact with the conductor  504  through an opening (see  FIG. 23B ). The conductor  504  is not necessarily formed (see  FIG. 23C ). 
     Embodiment 3 
     In this embodiment, an example of a circuit of a semiconductor device including a transistor or the like of one embodiment of the present invention is described. 
     &lt;CMOS Inverter&gt; 
     A circuit diagram in  FIG. 24A  illustrates a configuration of a so-called CMOS inverter in which a p-channel transistor  2200  and an n-channel transistor  2100  are connected to each other in series and gates of them are connected to each other. It is preferable that a transistor including an oxide semiconductor be used as the n-channel transistor  2100 . Thus, power consumption of the CMOS inverter circuit can be reduced. 
     &lt;CMOS Analog Switch&gt; 
     A circuit diagram in  FIG. 24B  illustrates a configuration in which sources of the transistors  2100  and  2200  are connected to each other and drains of the transistors  2100  and  2200  are connected to each other. With such a configuration, the transistors can function as a so-called CMOS analog switch. It is preferable that a transistor including an oxide semiconductor be used as the n-channel transistor  2100 . 
     &lt;Structure  1  of Semiconductor Device&gt; 
       FIG. 25  is a cross-sectional view of the semiconductor device of  FIG. 24A . The semiconductor device shown in  FIG. 25  includes the transistor  2200  and the transistor  2100 . The transistor  2100  is placed above the transistor  2200 . Although an example where the transistor shown in  FIGS. 20A and 20B  is used as the transistor  2100  is shown, a semiconductor device of one embodiment of the present invention is not limited thereto. For example, any of the transistors illustrated in  FIGS. 6A and 6B ,  FIGS. 7A to 7C ,  FIGS. 8A to 8C ,  FIGS. 22A to 22C , and  FIGS. 23A to 23C  can be used as the transistor  2100 . Therefore, the description regarding the above-mentioned transistors is referred to for the transistor  2100  as appropriate. 
     The transistor  2200  shown in  FIG. 25  is a transistor using a semiconductor substrate  450 . The transistor  2200  includes a region  472   a  in the semiconductor substrate  450 , a region  472   b  in the semiconductor substrate  450 , an insulator  462 , and a conductor  454 . 
     In the transistor  2200 , the regions  472   a  and  472   b  have functions of a source region and a drain region. The insulator  462  has a function of a gate insulator. The conductor  454  has a function of a gate electrode. Thus, the resistance of a channel formation region can be controlled by a potential applied to the conductor  454 . In other words, conduction or non-conduction between the region  472   a  and the region  472   b  can be controlled by the potential applied to the conductor  454 . 
     For the semiconductor substrate  450 , a single-material semiconductor substrate of silicon, germanium, or the like or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like may be used, for example. A single crystal silicon substrate is preferably used as the semiconductor substrate  450 . 
     For the semiconductor substrate  450 , a semiconductor substrate including impurities imparting n-type conductivity is used. However, a semiconductor substrate including impurities imparting p-type conductivity may be used as the semiconductor substrate  450 . In that case, a well including impurities imparting the n-type conductivity may be provided in a region where the transistor  2200  is formed. Alternatively, the semiconductor substrate  450  may be an i-type semiconductor substrate. 
     A top surface of the semiconductor substrate  450  preferably has a (110) plane. Thus, on-state characteristics of the transistor  2200  can be improved. 
     The regions  472   a  and  472   b  are regions including impurities imparting the p-type conductivity. Accordingly, the transistor  2200  has a structure of a p-channel transistor. 
     Note that the transistor  2200  is apart from an adjacent transistor by a region  460  and the like. The region  460  is an insulating region. 
     The semiconductor device shown in  FIG. 25  includes an insulator  464 , an insulator  466 , an insulator  468 , a conductor  480   a , a conductor  480   b , a conductor  480   c , a conductor  478   a , a conductor  478   b , a conductor  478   c , a conductor  476   a , a conductor  476   b , a conductor  474   a , a conductor  474   b , a conductor  474   c , a conductor  496   a , a conductor  496   b , a conductor  496   c , a conductor  496   d , a conductor  498   a , a conductor  498   b , a conductor  498   c , an insulator  490 , an insulator  492 , and an insulator  494 . 
     The insulator  464  is placed over the transistor  2200 . The insulator  466  is placed over the insulator  464 . The insulator  468  is placed over the insulator  466 . The insulator  490  is placed over the insulator  468 . The transistor  2100  is placed over the insulator  490 . The insulator  492  is placed over the transistor  2100 . The insulator  494  is placed over the insulator  492 . 
     The insulator  464  includes an opening reaching the region  472   a , an opening reaching the region  472   b , and an opening reaching the conductor  454 . In the openings, the conductor  480   a , the conductor  480   b , and the conductor  480   c  are embedded. 
     The insulator  466  includes an opening reaching the conductor  480   a , an opening reaching the conductor  480   b , and an opening reaching the conductor  480   c . In the openings, the conductor  478   a , the conductor  478   b , and the conductor  478   c  are embedded. 
     The insulator  468  includes an opening reaching the conductor  478   b  and an opening reaching the conductor  478   c . In the openings, the conductor  476   a  and the conductor  476   b  are embedded. 
     The insulator  490  includes an opening overlapping a channel formation region of the transistor  2100 , an opening reaching the conductor  476   a , and an opening reaching the conductor  476   b . In the openings, the conductor  474   a , the conductor  474   b , and the conductor  474   c  are embedded. 
     The conductor  474   a  may have a function of a gate electrode of the transistor  2100 . The electrical characteristics of the transistor  2100 , such as the threshold voltage, may be controlled by application of a predetermined potential to the conductor  474   a , for example. The conductor  474   a  may be electrically connected to the conductor  404  having a function of the gate electrode of the transistor  2100 , for example. In that case, on-state current of the transistor  2100  can be increased. Furthermore, a punch-through phenomenon can be suppressed; thus, the electrical characteristics of the transistor  2100  in a saturation region can be stable. 
     The insulator  492  includes an opening reaching the conductor  474   b  through the conductor  516   b  that is one of a source electrode and a drain electrode of the transistor  2100 , an opening reaching the conductor  516   a  that is the other of the source electrode and the drain electrode of the transistor  2100 , an opening reaching the conductor  504  that is the gate electrode of the transistor  2100 , and an opening reaching the conductor  474   c . In the openings, the conductor  496   a , the conductor  496   b , the conductor  496   c , and the conductor  496   d  are embedded. Note that in some cases, the openings are provided through any of components of the transistor  2100  or the like. 
     The insulator  494  includes an opening reaching the conductor  496   a , an opening reaching the conductor  496   b  and the conductor  496   d , and an opening reaching the conductor  496   c . In the openings, the conductor  498   a , the conductor  498   b , and the conductor  498   c  are embedded. 
     The insulators  464 ,  466 ,  468 ,  490 ,  492 , and  494  may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator  401  may be formed using, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. 
     The insulator that has a function of blocking oxygen and impurities such as hydrogen is preferably included in at least one of the insulators  464 ,  466 ,  468 ,  490 ,  492 , and  494 . When an insulator that has a function of blocking oxygen and impurities such as hydrogen is placed near the transistor  2100 , the electrical characteristics of the transistor  2100  can be stable. 
     An insulator with a function of blocking oxygen and impurities such as hydrogen may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. 
     Each of the conductor  480   a , the conductor  480   b , the conductor  480   c , the conductor  478   a , the conductor  478   b , the conductor  478   c , the conductor  476   a , the conductor  476   b , the conductor  474   a , the conductor  474   b , the conductor  474   c , the conductor  496   a , the conductor  496   b , the conductor  496   c , the conductor  496   d , the conductor  498   a , the conductor  498   b , and the conductor  498   c  may be formed to have, for example, a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds selected from boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound containing the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. 
     Note that a semiconductor device in  FIG. 26  is the same as the semiconductor device in  FIG. 25  except the structure of the transistor  2200 . Therefore, the description of the semiconductor device in  FIG. 25  is referred to for the semiconductor device in  FIG. 26 . In the semiconductor device in  FIG. 26 , the transistor  2200  is a FIN-type transistor. The effective channel width is increased in the FIN-type transistor  2200 , whereby the on-state characteristics of the transistor  2200  can be improved. In addition, since contribution of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor  2200  can be improved. 
     Note that a semiconductor device in  FIG. 27  is the same as the semiconductor device in  FIG. 25  except the structure of the transistor  2200 . Therefore, the description of the semiconductor device in  FIG. 25  is referred to for the semiconductor device in  FIG. 27 . Specifically, in the semiconductor device in  FIG. 27 , the transistor  2200  is formed using the semiconductor substrate  450  which is an SOI substrate. In the structure in  FIG. 27 , a region  456  is apart from the semiconductor substrate  450  with an insulator  452  provided therebetween. Since the SOI substrate is used as the semiconductor substrate  450 , a punch-through phenomenon and the like can be suppressed; thus, the off-state characteristics of the transistor  2200  can be improved. Note that the insulator  452  can be formed by turning part of the semiconductor substrate  450  into an insulator. For example, silicon oxide can be used as the insulator  452 . 
     In each of the semiconductor devices shown in  FIG. 25 ,  FIG. 26 , and  FIG. 27 , a p-channel transistor is formed utilizing a semiconductor substrate, and an n-channel transistor is formed above that; therefore, an occupation area of the element can be reduced. That is, the integration degree of the semiconductor device can be improved. In addition, the manufacturing process can be simplified compared to the case where an n-channel transistor and a p-channel transistor are formed utilizing the same semiconductor substrate; therefore, the productivity of the semiconductor device can be increased. Moreover, the yield of the semiconductor device can be improved. For the p-channel transistor, some complicated steps such as formation of lightly doped drain (LDD) regions, formation of a shallow trench structure, or distortion design can be omitted in some cases. Therefore, the productivity and yield of the semiconductor device can be increased in some cases, compared to a semiconductor device where an n-channel transistor is formed utilizing the semiconductor substrate. 
     &lt;Memory Device  1 &gt; 
     An example of a semiconductor device (memory device) which includes the transistor of one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is shown in  FIGS. 28A and 28B . 
     The semiconductor device illustrated in  FIG. 28A  includes a transistor  3200  using a first semiconductor, a transistor  3300  using a second semiconductor, and a capacitor  3400 . Note that any of the above-described transistors can be used as the transistor  3300 . 
     Note that the transistor  3300  is preferably a transistor with a low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor  3300 . Since the off-state current of the transistor  3300  is low, stored data can be retained for a long period at a predetermined node of the semiconductor device. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. 
     In  FIG. 28A , a first wiring  3001  is electrically connected to a source of the transistor  3200 . A second wiring  3002  is electrically connected to a drain of the transistor  3200 . A third wiring  3003  is electrically connected to one of the source and the drain of the transistor  3300 . A fourth wiring  3004  is electrically connected to the gate of the transistor  3300 . The gate of the transistor  3200  and the other of the source and the drain of the transistor  3300  are electrically connected to the one electrode of the capacitor  3400 . A fifth wiring  3005  is electrically connected to the other electrode of the capacitor  3400 . 
     The semiconductor device in  FIG. 28A  has a feature that the potential of the gate of the transistor  3200  can be retained, and thus enables writing, retaining, and reading of data as follows. 
     Writing and retaining of data are described. First, the potential of the fourth wiring  3004  is set to a potential at which the transistor  3300  is on, so that the transistor  3300  is turned on. Accordingly, the potential of the third wiring  3003  is supplied to a node FG where the gate of the transistor  3200  and the one electrode of the capacitor  3400  are electrically connected to each other. That is, a predetermined charge is supplied to the gate of the transistor  3200  (writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the fourth wiring  3004  is set to a potential at which the transistor  3300  is off, so that the transistor  3300  is turned off. Thus, the charge is held at the node FG (retaining). 
     Since the off-state current of the transistor  3300  is low, the charge of the node FG is retained for a long time. 
     Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the fifth wiring  3005  while a predetermined potential (a constant potential) is supplied to the first wiring  3001 , whereby the potential of the second wiring  3002  varies depending on the amount of charge retained in the node FG. This is because in the case of using an n-channel transistor as the transistor  3200 , an apparent threshold voltage V th_H  at the time when the high-level charge is given to the gate of the transistor  3200  is lower than an apparent threshold voltage V th_L  at the time when the low-level charge is given to the gate of the transistor  3200 . Here, an apparent threshold voltage refers to the potential of the fifth wiring  3005  which is needed to make the transistor  3200  be in “on state”. Thus, the potential of the fifth wiring  3005  is set to a potential V 0  which is between V th_H  and V th_L , whereby charge supplied to the node FG can be determined. For example, in the case where the high-level charge is supplied to the node FG in writing and the potential of the fifth wiring  3005  is V 0  (&gt;V th_H ), the transistor  3200  is brought into “on state”. In the case where the low-level charge is supplied to the node FG in writing, even when the potential of the fifth wiring  3005  is V 0  (&lt;V th_L ), the transistor  3200  still remains in “off state”. Thus, the data retained in the node FG can be read by determining the potential of the second wiring  3002 . 
     Note that in the case where memory cells are arrayed, it is necessary that data of a desired memory cell be read in read operation. In the case where data of the other memory cells is not read, the fifth wiring  3005  may be supplied with a potential at which the transistor  3200  is in “off state” regardless of the charge supplied to the node FG, that is, a potential lower than V th_H . Alternatively, the fifth wiring  3005  may be supplied with a potential at which the transistor  3200  is brought into “on state” regardless of the charge supplied to the node FG, that is, a potential higher than V th_L . 
     &lt;Memory Device  2 &gt; 
     The semiconductor device in  FIG. 28B  is different from the semiconductor device in  FIG. 28A  in that the transistor  3200  is not provided. Also in this case, data can be written and retained in a manner similar to that of the semiconductor device in  FIG. 28A . 
     Reading of data in the semiconductor device in  FIG. 28B  is described. When the transistor  3300  is brought into on state, the third wiring  3003  which is in a floating state and the capacitor  3400  are brought into conduction, and the charge is redistributed between the third wiring  3003  and the capacitor  3400 . As a result, the potential of the third wiring  3003  is changed. The amount of change in the potential of the third wiring  3003  varies depending on the potential of the one electrode of the capacitor  3400  (or the charge accumulated in the capacitor  3400 ). 
     For example, the potential of the third wiring  3003  after the charge redistribution is (C B ×V B0 +C×V)/(C B +C), where V is the potential of the one electrode of the capacitor  3400 , C is the capacitance of the capacitor  3400 , C B  is the capacitance component of the third wiring  3003 , and V B0  is the potential of the third wiring  3003  before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the one electrode of the capacitor  3400  is V 1  and V 0  (V 1 &gt;V 0 ), the potential of the third wiring  3003  in the case of retaining the potential V 1 (=(C B ×V B0 +C×V 1 )/(C B +C)) is higher than the potential of the third wiring  3003  in the case of retaining the potential V 0 (=(C B ×V B0 +C×V 0 )/(C B +C)). 
     Then, by comparing the potential of the third wiring  3003  with a predetermined potential, data can be read. 
     In this case, a transistor including the first semiconductor may be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor may be stacked over the driver circuit as the transistor  3300 . 
     When including a transistor using an oxide semiconductor and having a low off-state current, the semiconductor device described above can retain stored data for a long time. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed). 
     In the semiconductor device, high voltage is not needed for writing data and deterioration of elements is less likely to occur. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, the semiconductor device of one embodiment of the present invention does not have a limit on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the on/off state of the transistor, whereby high-speed operation can be achieved. 
     &lt;Structure  2  of Semiconductor Device&gt; 
       FIG. 29  is a cross-sectional view of the semiconductor device of  FIG. 28A . The semiconductor device shown in  FIG. 29  includes the transistor  3200 , the transistor  3300 , and the capacitor  3400 . The transistor  3300  and the capacitor  3400  are placed above the transistor  3200 . Note that for the transistor  3300 , the description of the above transistor  2100  is referred to. Furthermore, for the transistor  3200 , the description of the transistor  2200  in  FIG. 25  is referred to. Note that although the transistor  2200  is illustrated as a p-channel transistor in  FIG. 25 , the transistor  3200  may be an n-channel transistor. 
     The transistor  3200  illustrated in  FIG. 29  is a transistor using a semiconductor substrate  450 . The transistor  3200  includes a region  472   a  in the semiconductor substrate  450 , a region  472   b  in the semiconductor substrate  450 , an insulator  462 , and a conductor  454 . 
     The semiconductor device illustrated in  FIG. 29  includes insulators  464 ,  466 , and  468 , conductors  480   a ,  480   b ,  480   c ,  478   a ,  478   b ,  478   c ,  476   a ,  476   b ,  474   a ,  474   b ,  474   c ,  496   a ,  496   b ,  496   c ,  496   d ,  498   a ,  498   b ,  498   c , and  498   d , and insulators  490 ,  492 , and  494 . 
     The insulator  464  is provided over the transistor  3200 . The insulator  466  is provided over the insulator  464 . The insulator  468  is provided over the insulator  466 . The insulator  490  is provided over the insulator  468 . The transistor  3300  is provided over the insulator  490 . The insulator  492  is provided over the transistor  3300 . The insulator  494  is provided over the insulator  492 . 
     The insulator  464  has an opening reaching the region  472   a , an opening reaching the region  472   b , and an opening reaching the conductor  454 . In the openings, the conductor  480   a , the conductor  480   b , and the conductor  480   c  are embedded. 
     The insulator  466  includes an opening reaching the conductor  480   a , an opening reaching the conductor  480   b , and an opening reaching the conductor  480   c . In the openings, the conductor  478   a , the conductor  478   b , and the conductor  478   c  are embedded. 
     The insulator  468  includes an opening reaching the conductor  478   b  and an opening reaching the conductor  478   c . In the openings, the conductor  476   a  and the conductor  476   b  are embedded. 
     The insulator  490  includes an opening overlapping the channel formation region of the transistor  3300 , an opening reaching the conductor  476   a , and an opening reaching the conductor  476   b . In the openings, the conductors  474   a , the conductor  474   b , and the conductor  474   c  are embedded. 
     The conductor  474   a  may have a function as a bottom gate electrode of the transistor  3300 . Alternatively, for example, electric characteristics such as the threshold voltage of the transistor  3300  may be controlled by application of a predetermined potential to the conductor  474   a . Further alternatively, for example, the conductor  474   a  and the conductor  404  that is the top gate electrode of the transistor  3300  may be electrically connected to each other. Thus, the on-state current of the transistor  3300  can be increased. A punch-through phenomenon can be suppressed; thus, stable electric characteristics in the saturation region of the transistor  3300  can be obtained. 
     The insulator  492  includes an opening reaching the conductor  474   b  through the conductor  516   b  that is one of a source electrode and a drain electrode of the transistor  3300 , an opening reaching the conductor  514  that overlaps the conductor  516   a  that is the other of the source electrode and the drain electrode of the transistor  3300 , with the insulator  511  positioned therebetween, an opening reaching the conductor  504  that is the gate electrode of the transistor  3300 , and an opening reaching the conductor  474   c  through the conductor  516   a  that is the other of the source electrode and the drain electrode of the transistor  3300 . In the openings, the conductor  496   a , the conductor  496   b , the conductor  496   c , and the conductor  496   d  are embedded. Note that in some cases, a component of the transistor  3300  or the like is through other components. 
     The insulator  494  includes an opening reaching the conductor  496   a , an opening reaching the conductors  496   b , an opening reaching the conductor  496   c , and an opening reaching the conductor  496   d . In the openings, the conductors  498   a ,  498   b ,  498   c , and  498   d  are embedded. 
     At least one of the insulators  464 ,  466 ,  468 ,  490 ,  492 , and  494  preferably has a function of blocking oxygen and impurities such as hydrogen. When an insulator that has a function of blocking oxygen and impurities such as hydrogen is placed near the transistor  3300 , the electrical characteristics of the transistor  3300  can be stable. 
     The conductor  498   d  may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds selected from boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. 
     The source or drain of the transistor  3200  is electrically connected to the conductor  516   b  that is one of a source electrode and a drain electrode of the transistor  3300  through the conductor  480   b , the conductor  478   b , the conductor  476   a , the conductor  474   b , and the conductor  496   c . The conductor  454  that is the gate electrode of the transistor  3200  is electrically connected to the conductor  516   a  that is the other of the source electrode and the drain electrode of the transistor  3300  through the conductor  480   c , the conductor  478   c , the conductor  476   b , the conductor  474   c , and the conductor  496   d.    
     The capacitor  3400  includes an electrode electrically connected to the other of the source electrode and the drain electrode of the transistor  3300 , the conductor  514 , and an insulator  511 . Because the insulator  511  can be formed in the same step as the insulator  512  that functions as a gate insulator of the transistor  3300 , productivity can be preferably increased in some cases. When a layer formed in the same step as the conductor  504  that functions as a gate electrode of the transistor  3300  is used as the conductor  514 , productivity can be preferably increased in some cases. 
     For the structures of other components, the description of  FIG. 25  and the like can be referred to as appropriate. 
     A semiconductor device in  FIG. 30  is the same as the semiconductor device in  FIG. 29  except the structure of the transistor  3200 . Therefore, the description of the semiconductor device in  FIG. 29  is referred to for the semiconductor device in  FIG. 30 . Specifically, in the semiconductor device in  FIG. 30 , the transistor  3200  is a FIN-type transistor. For the FIN-type transistor  3200 , the description of the transistor  2200  in  FIG. 26  is referred to. Note that although the transistor  2200  is illustrated as a p-channel transistor in  FIG. 26 , the transistor  3200  may be an n-channel transistor. 
     A semiconductor device in  FIG. 31  is the same as the semiconductor device in  FIG. 29  except a structure of the transistor  3200 . Therefore, the description of the semiconductor device in  FIG. 29  is referred to for the semiconductor device in  FIG. 31 . Specifically, in the semiconductor device in  FIG. 31 , the transistor  3200  is provided in the semiconductor substrate  450  that is an SOI substrate. For the transistor  3200 , which is provided in the semiconductor substrate  450  that is an SOI substrate, the description of the transistor  2200  in  FIG. 27  is referred to. Note that although the transistor  2200  is illustrated as a p-channel transistor in  FIG. 27 , the transistor  3200  may be an n-channel transistor. 
     &lt;Imaging Device&gt; 
     An imaging device of one embodiment of the present invention is described below. 
       FIG. 32A  is a plan view illustrating an example of an imaging device  200  of one embodiment of the present invention. The imaging device  200  includes a pixel portion  210  and peripheral circuits for driving the pixel portion  210  (a peripheral circuit  260 , a peripheral circuit  270 , a peripheral circuit  280 , and a peripheral circuit  290 ). The pixel portion  210  includes a plurality of pixels  211  arranged in a matrix with p rows and q columns (p and q are each a natural number greater than or equal to 2). The peripheral circuit  260 , the peripheral circuit  270 , the peripheral circuit  280 , and the peripheral circuit  290  are each connected to a plurality of pixels  211 , and a signal for driving the plurality of pixels  211  is supplied. In this specification and the like, in some cases, “a peripheral circuit” or “a driver circuit” indicates all of the peripheral circuits  260 ,  270 ,  280 , and  290 . For example, the peripheral circuit  260  can be regarded as part of the peripheral circuit. 
     The imaging device  200  preferably includes a light source  291 . The light source  291  can emit detection light P 1 . 
     The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a converter circuit. The peripheral circuit may be provided over a substrate where the pixel portion  210  is formed. Part or the whole of the peripheral circuit may be mounted using a semiconductor device such as an IC. Note that as the peripheral circuit, one or more of the peripheral circuits  260 ,  270 ,  280 , and  290  may be omitted. 
     As illustrated in  FIG. 32B , the pixels  211  may be provided to be inclined in the pixel portion  210  included in the imaging device  200 . When the pixels  211  are obliquely arranged, the distance between pixels (pitch) can be shortened in the row direction and the column direction. Accordingly, the quality of an image taken with the imaging device  200  can be improved. 
     &lt;Configuration Example 1 of Pixel&gt; 
     The pixel  211  included in the imaging device  200  is formed with a plurality of subpixels  212 , and each subpixel  212  is combined with a filter which transmits light with a specific wavelength band (color filter), whereby data for achieving color image display can be obtained. 
       FIG. 33A  is a plan view showing an example of the pixel  211  with which a color image is obtained. The pixel  211  illustrated in  FIG. 33A  includes a subpixel  212  provided with a color filter transmitting light with a red (R) wavelength band (also referred to as a subpixel  212 R), a subpixel  212  provided with a color filter transmitting light with a green (G) wavelength band (also referred to as a subpixel  212 G), and a subpixel  212  provided with a color filter transmitting light with a blue (B) wavelength band (also referred to as a subpixel  212 B). The subpixel  212  can function as a photosensor. 
     The subpixel  212  (the subpixel  212 R, the subpixel  212 G, and the subpixel  212 B) is electrically connected to a wiring  231 , a wiring  247 , a wiring  248 , a wiring  249 , and a wiring  250 . In addition, the subpixel  212 R, the subpixel  212 G, and the subpixel  212 B are connected to respective wirings  253  which are independent from one another. In this specification and the like, for example, the wiring  248  and the wiring  249  that are connected to the pixel  211  in the n-th row (n is an integer greater than or equal to 1 and less than or equal top) are referred to as a wiring  248 [ n ] and a wiring  249 [ n ]. For example, the wiring  253  connected to the pixel  211  in the m-th column (m is an integer greater than or equal to 1 and less than or equal to q) is referred to as a wiring  253 [ m ]. Note that in  FIG. 33A , the wirings  253  connected to the subpixel  212 R, the subpixel  212 G, and the subpixel  212 B in the pixel  211  in the m-th column are referred to as a wiring  253 [ m ]R, a wiring  253 [ m ]G, and a wiring  253 [ m ]B. The subpixels  212  are electrically connected to the peripheral circuit through the above wirings. 
     The imaging device  200  has a structure in which the subpixel  212  is electrically connected to the subpixel  212  in an adjacent pixel  211  which is provided with a color filter transmitting light with the same wavelength band as the subpixel  212 , via a switch.  FIG. 33B  shows a connection example of the subpixels  212 : the subpixel  212  in the pixel  211  arranged in an n-th row and an m-th column and the subpixel  212  in the adjacent pixel  211  arranged in an (n+1)-th row and the m-th column. In  FIG. 33B , the subpixel  212 R arranged in the n-th row and the m-th column and the subpixel  212 R arranged in the (n+1)-th row and the m-th column are connected to each other via a switch  201 . The subpixel  212 G arranged in the n-th row and the m-th column and the subpixel  212 G arranged in the (n+1)-th row and the m-th column are connected to each other via a switch  202 . The subpixel  212 B arranged in the n-th row and the m-th column and the subpixel  212 B arranged in the (n+1)-th row and the m-th column are connected to each other via a switch  203 . 
     The color filter used in the subpixel  212  is not limited to red (R), green (G), and blue (B) color filters, and color filters that transmit light of cyan (C), yellow (Y), and magenta (M) may be used. By provision of the subpixels  212  that sense light with three different wavelength bands in one pixel  211 , a full-color image can be obtained. 
     The pixel  211  including the subpixel  212  provided with a color filter transmitting yellow (Y) light may be provided, in addition to the subpixels  212  provided with the color filters transmitting red (R), green (G), and blue (B) light. The pixel  211  including the subpixel  212  provided with a color filter transmitting blue (B) light may be provided, in addition to the subpixels  212  provided with the color filters transmitting cyan (C), yellow (Y), and magenta (M) light. When the subpixels  212  sensing light with four different wavelength bands are provided in one pixel  211 , the reproducibility of colors of an obtained image can be increased. 
     For example, in  FIG. 33A , in regard to the subpixel  212  sensing a red wavelength band, the subpixel  212  sensing a green wavelength band, and the subpixel  212  sensing a blue wavelength band, the pixel number ratio (or the light receiving area ratio) thereof is not necessarily  1 : 1 : 1 . For example, the Bayer arrangement in which the pixel number ratio (the light receiving area ratio) is set at red: green: blue=1:2:1 may be employed. Alternatively, the pixel number ratio (the light receiving area ratio) of red and green to blue may be 1:6:1. 
     Although the number of subpixels  212  provided in the pixel  211  may be one, two or more subpixels are preferably provided. For example, when two or more subpixels  212  sensing the same wavelength band are provided, the redundancy is increased, and the reliability of the imaging device  200  can be increased. 
     When an infrared (IR) filter that transmits infrared light and absorbs or reflects visible light is used as the filter, the imaging device  200  that senses infrared light can be achieved. 
     Furthermore, when a neutral density (ND) filter (dark filter) is used, output saturation which occurs when a large amount of light enters a photoelectric conversion element (light-receiving element) can be prevented. With a combination of ND filters with different dimming capabilities, the dynamic range of the imaging device can be increased. 
     Besides the above-described filter, the pixel  211  may be provided with a lens. An arrangement example of the pixel  211 , a filter  254 , and a lens  255  is described with cross-sectional views in  FIGS. 34A and 34B . With the lens  255 , the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in  FIG. 34A , light  256  enters a photoelectric conversion element  220  through the lens  255 , the filter  254  (a filter  254 R, a filter  254 G, and a filter  254 B), a pixel circuit  230 , and the like which are provided in the pixel  211 . 
     However, as indicated by a region surrounded with dashed-dotted lines, part of the light  256  indicated by arrows might be blocked by some wirings  257 . Thus, a preferable structure is that the lens  255  and the filter  254  are provided on the photoelectric conversion element  220  side, so that the photoelectric conversion element  220  can efficiently receive the light  256  as illustrated in  FIG. 34B . When the light  256  enters the photoelectric conversion element  220  from the photoelectric conversion element  220  side, the imaging device  200  with high sensitivity can be provided. 
     As the photoelectric conversion element  220  illustrated in  FIGS. 34A and 34B , a photoelectric conversion element in which a p-n junction or a p-i-n junction is formed may be used. 
     The photoelectric conversion element  220  may be formed using a substance that has a function of absorbing a radiation and generating electric charges. Examples of the substance that has a function of absorbing a radiation and generating electric charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy. 
     For example, when selenium is used for the photoelectric conversion element  220 , the photoelectric conversion element  220  can have a light absorption coefficient in a wide wavelength range, such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays. 
     One pixel  211  included in the imaging device  200  may include the subpixel  212  with a first filter in addition to the subpixel  212  illustrated in  FIGS. 33A and 33B . 
     &lt;Configuration Example 2 of Pixel&gt; 
     An example of a pixel including a transistor using silicon and a transistor using an oxide semiconductor is described below. 
       FIGS. 35A and 35B  are each a cross-sectional view of an element included in an imaging device. The imaging device illustrated in  FIG. 35A  includes a transistor  351  including silicon over a silicon substrate  300 , transistors  352  and  353  which include an oxide semiconductor and are stacked over the transistor  351 , and a photodiode  360  provided in a silicon substrate  300 . The transistors and the photodiode  360  are electrically connected to various plugs  370  and wirings  371 . In addition, an anode  361  of the photodiode  360  is electrically connected to the plug  370  through a low-resistance region  363 . 
     The imaging device includes a layer  310  including the transistor  351  provided on the silicon substrate  300  and the photodiode  360  provided in the silicon substrate  300 , a layer  320  which is in contact with the layer  310  and includes the wirings  371 , a layer  330  which is in contact with the layer  320  and includes the transistors  352  and  353 , and a layer  340  which is in contact with the layer  330  and includes a wiring  372  and a wiring  373 . 
     In the example of cross-sectional view in  FIG. 35A , a light-receiving surface of the photodiode  360  is provided on the side opposite to a surface of the silicon substrate  300  where the transistor  351  is formed. With this structure, a light path can be secured without an influence of the transistors and the wirings. Thus, a pixel with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode  360  can be the same as the surface where the transistor  351  is formed. 
     In the case where a pixel is formed with use of only transistors using an oxide semiconductor, the layer  310  may include the transistor using an oxide semiconductor. Alternatively, the layer  310  may be omitted, and the pixel may be formed with use of only transistors using an oxide semiconductor. 
     In the case where a pixel is formed with use of only transistors using silicon, the layer  330  may be omitted. An example of a cross-sectional view in which the layer  330  is not provided is shown in  FIG. 35B . 
     Note that the silicon substrate  300  may be an SOI substrate. Furthermore, the silicon substrate  300  can be replaced with a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. 
     Here, an insulator  380  is provided between the layer  310  including the transistor  351  and the photodiode  360  and the layer  330  including the transistors  352  and  353 . However, there is no limitation on the position of the insulator  380 . 
     Hydrogen in an insulator provided in the vicinity of a channel formation region of the transistor  351  terminates dangling bonds of silicon; accordingly, the reliability of the transistor  351  can be improved. In contrast, hydrogen in the insulator provided in the vicinity of the transistor  352 , the transistor  353 , and the like becomes one of factors generating a carrier in the oxide semiconductor. Thus, the hydrogen may cause a reduction of the reliability of the transistor  352 , the transistor  353 , and the like. Therefore, in the case where the transistor using an oxide semiconductor is provided over the transistor using a silicon-based semiconductor, it is preferable that the insulator  380  having a function of blocking hydrogen be provided between the transistors. When the hydrogen is confined below the insulator  380 , the reliability of the transistor  351  can be improved. In addition, the hydrogen can be prevented from being diffused from a part below the insulator  380  to a part above the insulator  380 ; thus, the reliability of the transistor  352 , the transistor  353 , and the like can be increased. 
     As the insulator  380 , an insulator having a function of blocking oxygen or hydrogen is used, for example. 
     In the cross-sectional view in  FIG. 35A , the photodiode  360  in the layer  310  and the transistor in the layer  330  can be formed so as to overlap each other. Thus, the degree of integration of pixels can be increased. In other words, the resolution of the imaging device can be increased. 
     As illustrated in FIG.  36 A 1  and FIG.  36 B 1 , part or the whole of the imaging device can be bent. FIG.  36 A 1  illustrates a state in which the imaging device is bent in the direction of a dashed-dotted line X 1 -X 2 . FIG.  36 A 2  is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X 1 -X 2  in FIG.  36 A 1 . FIG.  36 A 3  is a cross-sectional view illustrating a portion indicated by a dashed-dotted line Y 1 -Y 2  in FIG.  36 A 1 . 
     FIG.  36 B 1  illustrates a state where the imaging device is bent in the direction of a dashed-dotted chain X 3 -X 4  and the direction of a dashed-dotted line Y 3 -Y 4 . FIG.  36 B 2  is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X 3 -X 4  in FIG.  36 B 1 . FIG.  36 B 3  is a cross-sectional view illustrating a portion indicated by the dashed-dotted line Y 3 -Y 4  in FIG.  36 B 1 . 
     The bent imaging device enables the curvature of field and astigmatism to be reduced. Thus, the optical design of lens and the like, which is used in combination of the imaging device, can be facilitated. For example, the number of lens used for aberration correction can be reduced; accordingly, a reduction of size or weight of electronic devices using the imaging device, and the like, can be achieved. In addition, the quality of a captured image can be improved. 
     &lt;CPU&gt; 
     A CPU including a semiconductor device such as any of the above-described transistors or the above-described memory device is described below. 
       FIG. 37  is a block diagram illustrating a configuration example of a CPU including any of the above-described transistors as a component. 
     The CPU illustrated in  FIG. 37  includes, over a substrate  1190 , an arithmetic logic unit (ALU)  1191 , an ALU controller  1192 , an instruction decoder  1193 , an interrupt controller  1194 , a timing controller  1195 , a register  1196 , a register controller  1197 , a bus interface  1198 , a rewritable ROM  1199 , and a ROM interface  1189 . A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate  1190 . The ROM  1199  and the ROM interface  1189  may be provided over a separate chip. Needless to say, the CPU in  FIG. 37  is just an example in which the configuration has been simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in  FIG. 37  or an arithmetic circuit is considered as one core; a plurality of such cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example. 
     An instruction that is input to the CPU through the bus interface  1198  is input to the instruction decoder  1193  and decoded therein, and then, input to the ALU controller  1192 , the interrupt controller  1194 , the register controller  1197 , and the timing controller  1195 . 
     The ALU controller  1192 , the interrupt controller  1194 , the register controller  1197 , and the timing controller  1195  conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller  1192  generates signals for controlling the operation of the ALU  1191 . While the CPU is executing a program, the interrupt controller  1194  judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller  1197  generates an address of the register  1196 , and reads/writes data from/to the register  1196  in accordance with the state of the CPU. 
     The timing controller  1195  generates signals for controlling operation timings of the ALU  1191 , the ALU controller  1192 , the instruction decoder  1193 , the interrupt controller  1194 , and the register controller  1197 . For example, the timing controller  1195  includes an internal clock generator for generating an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the above circuits. 
     In the CPU illustrated in  FIG. 37 , a memory cell is provided in the register  1196 . For the memory cell of the register  1196 , any of the above-described transistors, the above-described memory device, or the like can be used. 
     In the CPU illustrated in  FIG. 37 , the register controller  1197  selects operation of retaining data in the register  1196  in accordance with an instruction from the ALU  1191 . That is, the register controller  1197  selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register  1196 . When data retention by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register  1196 . When data retention by the capacitor is selected, the data is rewritten in the capacitor, and supply of a power supply voltage to the memory cell in the register  1196  can be stopped. 
       FIG. 38  is an example of a circuit diagram of a memory element  1200  that can be used as the register  1196 . The memory element  1200  includes a circuit  1201  in which stored data is volatile when power supply is stopped, a circuit  1202  in which stored data is nonvolatile even when power supply is stopped, a switch  1203 , a switch  1204 , a logic element  1206 , a capacitor  1207 , and a circuit  1220  having a selecting function. The circuit  1202  includes a capacitor  1208 , a transistor  1209 , and a transistor  1210 . Note that the memory element  1200  may further include another element such as a diode, a resistor, or an inductor, as needed. 
     Here, the above-described memory device can be used as the circuit  1202 . When supply of a power supply voltage to the memory element  1200  is stopped, GND (0 V) or a potential at which the transistor  1209  in the circuit  1202  is turned off continues to be input to a gate of the transistor  1209 . For example, the gate of the transistor  1209  is grounded through a load such as a resistor. 
     Shown here is an example in which the switch  1203  is a transistor  1213  having one conductivity type (e.g., an n-channel transistor) and the switch  1204  is a transistor  1214  having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor). A first terminal of the switch  1203  corresponds to one of a source and a drain of the transistor  1213 , a second terminal of the switch  1203  corresponds to the other of the source and the drain of the transistor  1213 , and conduction or non-conduction between the first terminal and the second terminal of the switch  1203  (i.e., the on/off state of the transistor  1213 ) is selected by a control signal RD input to a gate of the transistor  1213 . A first terminal of the switch  1204  corresponds to one of a source and a drain of the transistor  1214 , a second terminal of the switch  1204  corresponds to the other of the source and the drain of the transistor  1214 , and conduction or non-conduction between the first terminal and the second terminal of the switch  1204  (i.e., the on/off state of the transistor  1214 ) is selected by the control signal RD input to a gate of the transistor  1214 . 
     One of a source and a drain of the transistor  1209  is electrically connected to one of a pair of electrodes of the capacitor  1208  and a gate of the transistor  1210 . Here, the connection portion is referred to as a node M 2 . One of a source and a drain of the transistor  1210  is electrically connected to a line which can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch  1203  (the one of the source and the drain of the transistor  1213 ). The second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) is electrically connected to the first terminal of the switch  1204  (the one of the source and the drain of the transistor  1214 ). The second terminal of the switch  1204  (the other of the source and the drain of the transistor  1214 ) is electrically connected to a line which can supply a power supply potential VDD. The second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ), the first terminal of the switch  1204  (the one of the source and the drain of the transistor  1214 ), an input terminal of the logic element  1206 , and one of a pair of electrodes of the capacitor  1207  are electrically connected to each other. Here, the connection portion is referred to as a node M 1 . The other of the pair of electrodes of the capacitor  1207  can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor  1207  can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor  1207  is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor  1208  can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor  1208  can be supplied with the low power supply potential (e.g., GND) or the high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor  1208  is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). 
     The capacitor  1207  and the capacitor  1208  are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized. 
     A control signal WE is input to the gate of the transistor  1209 . As for each of the switch  1203  and the switch  1204 , a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state. 
     A signal corresponding to data retained in the circuit  1201  is input to the other of the source and the drain of the transistor  1209 .  FIG. 38  illustrates an example in which a signal output from the circuit  1201  is input to the other of the source and the drain of the transistor  1209 . The logic value of a signal output from the second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) is inverted by the logic element  1206 , and the inverted signal is input to the circuit  1201  through the circuit  1220 . 
     In the example of  FIG. 38 , a signal output from the second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) is input to the circuit  1201  through the logic element  1206  and the circuit  1220 ; however, one embodiment of the present invention is not limited thereto. The signal output from the second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) may be input to the circuit  1201  without its logic value being inverted. For example, in the case where the circuit  1201  includes a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained, the signal output from the second terminal of the switch  1203  (the other of the source and the drain of the transistor  1213 ) can be input to the node. 
     In  FIG. 38 , the transistors included in the memory element  1200  except for the transistor  1209  can each be a transistor in which a channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate  1190 . For example, the transistor can be a transistor whose channel is formed in a silicon film or a silicon substrate. Alternatively, all the transistors in the memory element  1200  may be a transistor in which a channel is formed in an oxide semiconductor. Further alternatively, in the memory element  1200 , a transistor in which a channel is formed in an oxide semiconductor may be included besides the transistor  1209 , and a transistor in which a channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate  1190  can be used for the rest of the transistors. 
     As the circuit  1201  in  FIG. 38 , for example, a flip-flop circuit can be used. As the logic element  1206 , for example, an inverter or a clocked inverter can be used. 
     In a period during which the memory element  1200  is not supplied with the power supply voltage, the semiconductor device of one embodiment of the present invention can retain data stored in the circuit  1201  by the capacitor  1208  which is provided in the circuit  1202 . 
     The off-state current of a transistor in which a channel is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when the transistor is used as the transistor  1209 , a signal held in the capacitor  1208  is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element  1200 . The memory element  1200  can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped. 
     Since the above-described memory element performs pre-charge operation with the switch  1203  and the switch  1204 , the time required for the circuit  1201  to retain original data again after the supply of the power supply voltage is restarted can be shortened. 
     In the circuit  1202 , a signal retained by the capacitor  1208  is input to the gate of the transistor  1210 . Therefore, after supply of the power supply voltage to the memory element  1200  is restarted, the signal retained by the capacitor  1208  can be converted into the one corresponding to the state (the on state or the off state) of the transistor  1210  to be read from the circuit  1202 . Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor  1208  varies to some degree. 
     By applying the above-described memory element  1200  to a memory device such as a register or a cache memory included in a processor, data in the memory device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Furthermore, shortly after the supply of the power supply voltage is restarted, the memory device can be returned to the same state as that before the power supply is stopped. Therefore, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor, resulting in lower power consumption. 
     Although the memory element  1200  is used in a CPU, the memory element  1200  can also be used in an LSI such as a digital signal processor (DSP), a custom LSI, or a programmable logic device (PLD), and a radio frequency (RF) device. 
     &lt;Display Device&gt; 
     A display device of one embodiment of the present invention is described below with reference to  FIGS. 39A to 39C  and  FIGS. 40A and 40B . 
     Examples of a display element provided in the display device include a liquid crystal element (also referred to as a liquid crystal display element) and a light-emitting element (also referred to as a light-emitting display element). The light-emitting element includes, in its category, an element whose luminance is controlled by a current or voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like. A display device including an EL element (EL display device) and a display device including a liquid crystal element (liquid crystal display device) are described below as examples of the display device. 
     Note that the display device described below includes in its category a panel in which a display element is sealed and a module in which an IC such as a controller is mounted on the panel. 
     The display device described below refers to an image display device or a light source (including a lighting device). The display device includes any of the following modules: a module provided with a connector such as an FPC or TCP; a module in which a printed board is provided at the end of TCP; and a module in which an integrated circuit (IC) is mounted directly on a display element by a COG method. 
       FIGS. 39A to 39C  illustrate an example of an EL display device of one embodiment of the present invention.  FIG. 39A  is a circuit diagram of a pixel in an EL display device.  FIG. 39B  is a plan view showing the whole of the EL display device.  FIG. 39C  is a cross-sectional view taken along part of dashed-dotted line M-N in  FIG. 39B . 
       FIG. 39A  illustrates an example of a circuit diagram of a pixel used in an EL display device. 
     Note that in this specification and the like, it might be possible for those skilled in the art to constitute one embodiment of the invention even when portions to which all the terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected are not specified. In other words, one embodiment of the invention can be clear even when connection portions are not specified. Further, in the case where a connection portion is disclosed in this specification and the like, it can be determined that one embodiment of the invention in which a connection portion is not specified is disclosed in this specification and the like, in some cases. Particularly in the case where the number of portions to which a terminal is connected might be more than one, it is not necessary to specify the portions to which the terminal is connected. Therefore, it might be possible to constitute one embodiment of the invention by specifying only portions to which some of terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected. 
     Note that in this specification and the like, it might be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it might be possible for those skilled in the art to specify the invention when at least a function of a circuit is specified. In other words, when a function of a circuit is specified, one embodiment of the present invention can be clear. Further, it can be determined that one embodiment of the present invention whose function is specified is disclosed in this specification and the like. Therefore, when a connection portion of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a function is not specified, and one embodiment of the invention can be constituted. Alternatively, when a function of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a connection portion is not specified, and one embodiment of the invention can be constituted. 
     The EL display device illustrated in  FIG. 39A  includes a switching element  743 , a transistor  741 , a capacitor  742 , and a light-emitting element  719 . 
     Note that  FIG. 39A  and the like each illustrate an example of a circuit structure; therefore, a transistor can be provided additionally. In contrast, for each node in  FIG. 39A  and the like, it is possible not to provide an additional transistor, switch, passive element, or the like. 
     A gate of the transistor  741  is electrically connected to one terminal of the switching element  743  and one electrode of the capacitor  742 . A source of the transistor  741  is electrically connected to the other electrode of the capacitor  742  and one electrode of the light-emitting element  719 . A drain of the transistor  741  is supplied with a power supply potential VDD. The other terminal of the switching element  743  is electrically connected to a signal line  744 . A constant potential is supplied to the other electrode of the light-emitting element  719 . The constant potential is a ground potential GND or a potential lower than the ground potential GND. 
     It is preferable to use a transistor as the switching element  743 . When the transistor is used as the switching element, the area of a pixel can be reduced, so that the EL display device can have high resolution. As the switching element  743 , a transistor formed through the same step as the transistor  741  can be used, so that EL display devices can be manufactured with high productivity. Note that as the transistor  741  and/or the switching element  743 , any of the above-described transistors can be used, for example. 
       FIG. 39B  is a plan view of the EL display device. The EL display device includes a substrate  700 , a substrate  750 , a sealant  734 , a driver circuit  735 , a driver circuit  736 , a pixel  737 , and an FPC  732 . The sealant  734  is provided between the substrate  700  and the substrate  750  so as to surround the pixel  737 , the driver circuit  735 , and the driver circuit  736 . Note that the driver circuit  735  and/or the driver circuit  736  may be provided outside the sealant  734 . 
       FIG. 39C  is a cross-sectional view of the EL display device taken along part of dashed-dotted line M-N in  FIG. 39B . 
       FIG. 39C  illustrates a structure of the transistor  741  including a conductor  704   a  over the substrate  700 ; an insulator  712   a  over the conductor  704   a ; an insulator  712   b  over the insulator  712   a ; a semiconductor  706   a  and a semiconductor  706   b  which are over the insulator  712   b  and overlaps the conductor  704   a ; a conductor  716   a  and a conductor  716   b  in contact with the semiconductors  706   a  and  706   b ; an insulator  718   a  over the semiconductor  706   b , the conductor  716   a , and the conductor  716   b ; an insulator  718   b  over the insulator  718   a ; an insulator  718   c  over the insulator  718   b ; and a conductor  714   a  that is over the insulator  718   c  and overlaps the semiconductor  706   b . Note that the structure of the transistor  741  is just an example; the transistor  741  may have a structure different from that illustrated in  FIG. 39C . 
     Thus, in the transistor  741  illustrated in  FIG. 39C , the conductor  704   a  serves as a gate electrode, the insulator  712   a  and the insulator  712   b  serve as a gate insulator, the conductor  716   a  serves as a source electrode, the conductor  716   b  serves as a drain electrode, the insulator  718   a , the insulator  718   b , and the insulator  718   c  serve as a gate insulator, and the conductor  714   a  serves as a gate electrode. Note that in some cases, electrical characteristics of the semiconductors  706   a  and  706   b  change if light enters the semiconductor. To prevent this, it is preferable that one or more of the conductor  704   a , the conductor  716   a , the conductor  716   b , and the conductor  714   a  have a light-blocking property. 
     Note that the interface between the insulator  718   a  and the insulator  718   b  is indicated by a broken line. This means that the boundary between them is not clear in some cases. For example, in the case where the insulator  718   a  and the insulator  718   b  are formed using insulators of the same kind, the insulator  718   a  and the insulator  718   b  are not distinguished from each other in some cases depending on an observation method. 
       FIG. 39C  illustrates a structure of the capacitor  742  including a conductor  704   b  over the substrate; the insulator  712   a  over the conductor  704   b ; the insulator  712   b  over the insulator  712   a ; the conductor  716   a  that is over the insulator  712   b  and overlaps the conductor  704   b ; the insulator  718   a  over the conductor  716   a ; the insulator  718   b  over the insulator  718   a ; the insulator  718   c  over the insulator  718   b ; and a conductor  714   b  that is over the insulator  718   c  and overlaps the conductor  716   a . In this structure, part of the insulator  718   a  and part of the insulator  718   b  are removed in a region where the conductor  716   a  and the conductor  714   b  overlap each other. 
     In the capacitor  742 , each of the conductor  704   b  and the conductor  714   b  serves as one electrode, and the conductor  716   a  serves as the other electrode. 
     Thus, the capacitor  742  can be formed using a film of the transistor  741 . The conductor  704   a  and the conductor  704   b  are preferably conductors of the same kind, in which case the conductor  704   a  and the conductor  704   b  can be formed through the same step. Furthermore, the conductor  714   a  and the conductor  714   b  are preferably conductors of the same kind, in which case the conductor  714   a  and the conductor  714   b  can be formed through the same step. 
     The capacitor  742  illustrated in  FIG. 39C  has a large capacitance per area occupied by the capacitor. Therefore, the EL display device illustrated in  FIG. 39C  has high display quality. Note that although the capacitor  742  illustrated in  FIG. 39C  has the structure in which the part of the insulator  718   a  and the part of the insulator  718   b  are removed to reduce the thickness of the region where the conductor  716   a  and the conductor  714   b  overlap with each other, the structure of the capacitor according to one embodiment of the present invention is not limited to the structure. For example, a structure in which a part of the insulator  718   c  is removed to reduce the thickness of the region where the conductor  716   a  and the conductor  714   b  overlap with each other may be used. 
     An insulator  720  is provided over the transistor  741  and the capacitor  742 . Here, the insulator  720  may have an opening portion reaching the conductor  716   a  that serves as the source electrode of the transistor  741 . A conductor  781  is provided over the insulator  720 . The conductor  781  may be electrically connected to the transistor  741  through the opening portion in the insulator  720 . 
     A partition wall  784  having an opening portion reaching the conductor  781  is provided over the conductor  781 . A light-emitting layer  782  in contact with the conductor  781  through the opening portion provided in the partition wall  784  is provided over the partition wall  784 . A conductor  783  is provided over the light-emitting layer  782 . A region where the conductor  781 , the light-emitting layer  782 , and the conductor  783  overlap with one another serves as the light-emitting element  719 . 
     So far, examples of the EL display device are described. Next, an example of a liquid crystal display device is described. 
       FIG. 40A  is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device. A pixel shown in  FIGS. 40A and 40B  includes a transistor  751 , a capacitor  752 , and an element (liquid crystal element)  753  in which a space between a pair of electrodes is filled with a liquid crystal. 
     One of a source and a drain of the transistor  751  is electrically connected to a signal line  755 , and a gate of the transistor  751  is electrically connected to a scan line  754 . 
     One electrode of the capacitor  752  is electrically connected to the other of the source and the drain of the transistor  751 , and the other electrode of the capacitor  752  is electrically connected to a wiring for supplying a common potential. 
     One electrode of the liquid crystal element  753  is electrically connected to the other of the source and the drain of the transistor  751 , and the other electrode of the liquid crystal element  753  is electrically connected to a wiring to which a common potential is supplied. The common potential supplied to the wiring electrically connected to the other electrode of the capacitor  752  may be different from that supplied to the other electrode of the liquid crystal element  753 . 
     Note that the description of the liquid crystal display device is made on the assumption that the plan view of the liquid crystal display device is similar to that of the EL display device.  FIG. 40B  is a cross-sectional view of the liquid crystal display device taken along dashed-dotted line M-N in  FIG. 39B . In  FIG. 40B , the FPC  732  is connected to the wiring  733   a  via the terminal  731 . Note that the wiring  733   a  may be formed using the same kind of conductor as the conductor of the transistor  751  or using the same kind of semiconductor as the semiconductor of the transistor  751 . 
     For the transistor  751 , the description of the transistor  741  is referred to. For the capacitor  752 , the description of the capacitor  742  is referred to. Note that the structure of the capacitor  752  in  FIG. 40B  corresponds to, but is not limited to, the structure of the capacitor  742  in  FIG. 39C . 
     Note that in the case where an oxide semiconductor is used as the semiconductor of the transistor  751 , the off-state current of the transistor  751  can be extremely small. Therefore, an electric charge held in the capacitor  752  is unlikely to leak, so that the voltage applied to the liquid crystal element  753  can be maintained for a long time. Accordingly, the transistor  751  can be kept off during a period in which moving images with few motions or a still image are/is displayed, whereby power for the operation of the transistor  751  can be saved in that period; 
     accordingly a liquid crystal display device with low power consumption can be provided. Furthermore, the area occupied by the capacitor  752  can be reduced; thus, a liquid crystal display device with a high aperture ratio or a high-resolution liquid crystal display device can be provided. 
     An insulator  721  is provided over the transistor  751  and the capacitor  752 . The insulator  721  has an opening portion reaching the transistor  751 . A conductor  791  is provided over the insulator  721 . The conductor  791  is electrically connected to the transistor  751  through the opening portion in the insulator  721 . 
     An insulator  792  serving as an alignment film is provided over the conductor  791 . A liquid crystal layer  793  is provided over the insulator  792 . An insulator  794  serving as an alignment film is provided over the liquid crystal layer  793 . A spacer  795  is provided over the insulator  794 . A conductor  796  is provided over the spacer  795  and the insulator  794 . A substrate  797  is provided over the conductor  796 . 
     Owing to the above-described structure, a display device including a capacitor occupying a small area, a display device with high display quality, or a high-resolution display device can be provided. 
     For example, in this specification and the like, a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element can employ various modes or can include various elements. For example, the display element, the display device, the light-emitting element, or the light-emitting device includes at least one of a light-emitting diode (LED) for white, red, green, blue, or the like, a transistor (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using micro electro mechanical systems (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, and a display element including a carbon nanotube. Other than the above, display media whose contrast, luminance, reflectivity, transmittance, or the like is changed by electrical or magnetic effect may be included. 
     Note that examples of display devices having EL elements include an EL display. Examples of a display device including an electron emitter include a field emission display (FED), an SED-type flat panel display (SED: surface-conduction electron-emitter display), and the like. Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of a display device having electronic ink or an electrophoretic element include electronic paper. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes. Thus, the power consumption can be further reduced. 
     Note that in the case of using an LED, graphene or graphite may be provided under an electrode or a nitride semiconductor of the LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. As described above, provision of graphene or graphite enables easy formation of a nitride semiconductor thereover, such as an n-type GaN semiconductor including crystals. Furthermore, a p-type GaN semiconductor including crystals or the like can be provided thereover, and thus the LED can be formed. Note that an AIN layer may be provided between the n-type GaN semiconductor including crystals and graphene or graphite. The GaN semiconductors included in the LED may be formed by MOCVD. Note that when the graphene is provided, the GaN semiconductors included in the LED can also be formed by a sputtering method. 
     &lt;Electronic Device&gt; 
     The semiconductor device of one embodiment of the present invention can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices which reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Other examples of electronic devices that can be equipped with the semiconductor device of one embodiment of the present invention are mobile phones, game machines including portable game consoles, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines.  FIGS. 41A to 41F  illustrate specific examples of these electronic devices. 
       FIG. 41A  illustrates a portable game console including a housing  901 , a housing  902 , a display portion  903 , a display portion  904 , a microphone  905 , a speaker  906 , an operation key  907 , a stylus  908 , and the like. Although the portable game console in  FIG. 41A  has the two display portions  903  and  904 , the number of display portions included in a portable game console is not limited to this. 
       FIG. 41B  illustrates a portable data terminal including a first housing  911 , a second housing  912 , a first display portion  913 , a second display portion  914 , a joint  915 , an operation key  916 , and the like. The first display portion  913  is provided in the first housing  911 , and the second display portion  914  is provided in the second housing  912 . The first housing  911  and the second housing  912  are connected to each other with the joint  915 , and the angle between the first housing  911  and the second housing  912  can be changed with the joint  915 . An image on the first display portion  913  may be switched in accordance with the angle at the joint  915  between the first housing  911  and the second housing  912 . A display device with a position input function may be used as at least one of the first display portion  913  and the second display portion  914 . Note that the position input function can be added by providing a touch panel in a display device. Alternatively, the position input function can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device. 
       FIG. 41C  illustrates a laptop personal computer, which includes a housing  921 , a display portion  922 , a keyboard  923 , a pointing device  924 , and the like. 
       FIG. 41D  illustrates an electric refrigerator-freezer, which includes a housing  931 , a door for a refrigerator  932 , a door for a freezer  933 , and the like. 
       FIG. 41E  illustrates a video camera, which includes a first housing  941 , a second housing  942 , a display portion  943 , operation keys  944 , a lens  945 , a joint  946 , and the like. The operation keys  944  and the lens  945  are provided for the first housing  941 , and the display portion  943  is provided for the second housing  942 . The first housing  941  and the second housing  942  are connected to each other with the joint  946 , and the angle between the first housing  941  and the second housing  942  can be changed with the joint  946 . Images displayed on the display portion  943  may be switched in accordance with the angle at the joint  946  between the first housing  941  and the second housing  942 . 
       FIG. 41F  illustrates a car including a car body  951 , wheels  952 , a dashboard  953 , lights  954 , and the like. 
     Embodiments of the present invention are described above. Note that one embodiment of the present invention is not limited to the above description. For example, an example where a semiconductor such as the semiconductor  406   b  includes fluorine or hydrogen is described, but one embodiment of the present invention is not limited thereto. Depending on circumstances, the semiconductor such as the semiconductor  406   b  may include an element other than fluorine or an element other than hydrogen; alternatively, the semiconductor such as the semiconductor  406   b  does not necessarily include fluorine or hydrogen. 
     Example 1 
     In this example, the measurement results of fluorine concentrations in an oxide semiconductor film to which fluorine is added are shown. 
     A sample was fabricated in such a manner that a 100-nm-thick silicon oxide film was formed over a silicon substrate by a thermal oxidation method, and a 100-nm-thick IGZO film was formed thereon as an oxide semiconductor film by a sputtering method with the use of an In-Ga—Zn—O (In:Ga:Zn=1:1:1 in atomic ratio) target. 
     By an ion implantation method, fluorine ions ( 19 F+) with a dose of 1.0×10 15  ions/cm 2  and a dose of 1.0×10 16  ions/cm 2  were added to the samples. Note that the accelerating voltage was 20 kV.  FIG. 42  shows the measurement results of the amount of added fluorine in the depth direction by SIMS. 
     As shown in  FIG. 42 , in the case where fluorine with a dose of 1.0×10 15  ions/cm 2  is added, fluorine is contained in the IGZO film at a concentration of about 3.0×10 20  atoms/cm 3 . Furthermore, in the case where fluorine with a dose of 1.0×10 16  ions/cm 2  is added, fluorine is contained in the IGZO film at a concentration of about 3.0×10 21  atoms/cm 3 . 
     Example 2 
     In this example, the measurement results of sheet resistance values of an oxide semiconductor film to which fluorine is added are shown. 
     A sample was fabricated in such a manner that a 100-nm-thick IGZO film was formed on a quartz substrate as an oxide semiconductor film by a sputtering method with the use of an In-Ga—Zn—O (In:Ga:Zn=1:1:1 in atomic ratio) target. 
     By an ion implantation method, fluorine ions ( 19 F + ) with a dose of 1.0×10 14  ions/cm 2 , a dose of 1.0×10 15  ions/cm 2 , and a dose of 1.0×10 16  ions/cm 2  were added to the samples. Note that the accelerating voltage was 20 kV.  FIG. 43  shows measurement results of sheet resistance values of the samples fabricated as described above. Note that the measurement upper limit of a sheet resistance measurer is 1×10 6 Ω/□.    
     As shown in  FIG. 43 , as fluorine is added to the IGZO film, the sheet resistance value is increased. Furthermore, when fluorine with a dose of 1.0×10 16  ions/cm 2  is added, the sheet resistance value of the IGZO film becomes higher than or equal to 1×10 6  Ω/□. From this, it is found that by the addition of fluorine to the IGZO film, the carrier concentration of the IGZO film decreases and the IGZO film is close to an i-type semiconductor. 
     Example 3 
     In this example, the measurement results of defects in an oxide semiconductor film to which fluorine is added by ESR are shown. 
     A sample was fabricated in such a manner that a 100-nm-thick IGZO film was formed on a quartz substrate as an oxide semiconductor film by a sputtering method with the use of an In—Ga—Zn—O (In:Ga:Zn=1:1:1 in atomic ratio) target. 
     By an ion implantation method, fluorine ions ( 19 F + ) with a dose of 1.0×10 14  ions/cm 2 , a dose of 1.0×10 15  ions/cm 2 , and a dose of 1.0×10 16  ions/cm 2  were added to the samples. Note that the accelerating voltage was 20 kV.  FIGS. 44A and 44B  show the measurement results by ESR of the samples fabricated as described above. 
       FIG. 44A  shows ESR spectra. As shown in  FIG. 44A , as fluorine is added to the IGZO film, a signal at a g-factor of around 1.93 becomes smaller. In addition,  FIG. 44B  shows a comparison result between spin densities of signals that appear at a g-factor of around 1.93. As shown in  FIG. 44B , as fluorine is added to the IGZO film, the spin density of the signal that appears at a g-factor of around 1.93 decreases. 
     In an IGZO film, a signal that appears at a g-factor of around 1.93 is derived from an oxygen vacancy. Therefore, fluorine is added to the IGZO film, whereby oxygen vacancies in the IGZO film can be reduced. 
     This application is based on Japanese Patent Application serial no. 2014-244302 filed with Japan Patent Office on Dec. 2, 2014, the entire contents of which are hereby incorporated by reference.