Patent Publication Number: US-2023155496-A1

Title: Charge pump circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of U.S. provisional application Ser. No. 63/280,555, filed on Nov. 17, 2021, and Taiwan application serial no. 111102046, filed on Jan. 18, 2022. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGRO UN D 
     Technical Field 
     The disclosure relates to a charge pump circuit, and in particular, relates to a charge pump circuit exhibiting high efficiency. 
     Description of Related Art 
       FIG.  1    is a schematic diagram of an existing and common dual-phase charge pump circuit  10 . The dual-phase charge pump circuit  10  includes a dual-phase charge pump  11  and transfer transistors P 1  and P 2 . The dual-phase charge pump  11  includes power transistors M 1  and M 2  and capacitors C 3  and C 4 . A first terminal of the power transistor M 1  is coupled to a power source VDDA. A second terminal and a control terminal of the power transistor M 1  are coupled to a node ND 1 . A first terminal of the power transistor M 2  is coupled to the power source VDDA. A second terminal and a control terminal of the power transistor M 2  are coupled to a node ND 2 . A capacitor C 1  is coupled between the node ND 1  and the clock CK 1 . A capacitor C 2  is coupled. between the node ND 2  and the clock CK 2 . A first terminal and a control terminal of the transfer transistor P 1  are coupled to the node ND 2 . A second terminal of the transfer transistor P 1  is coupled to an output terminal. A first terminal and a control terminal of the transfer transistor P 2  are coupled to the ode ND 1 . A second terminal of the transfer transistor P 2  is coupled to the output terminal. 
     During operation, when the clock CK 1  transitions from a low voltage level to a high voltage level, the clock CK 2  transitions from a high voltage level to a low voltage level. The transfer transistor P 1  is turned off. The transfer transistor P 2  is turned on. Therefore, the transfer transistor P 2  may provide a pumping voltage at the node ND 1  to the output terminal. When the clock CK 1  transitions from the high voltage level to the low voltage level, the clock CK 2  transitions from the low voltage level to the high voltage level. The transfer transistor P 2  is turned off. The transfer transistor P 1  is turned on. Therefore, the transfer transistor P 1  may provide a pumping voltage at the node ND 2  to the output terminal. 
     However, the capacitors C 3  and C 4  may delay charging and discharging on the nodes ND 1  and ND 2 . The abovementioned delay may delay the turning-off time point of the transfer transistors P 1  and P 2 , and a reverse leakage current Irev is thereby generated. For instance, when the clock CK 1  transitions from the low voltage level to the high voltage level and the clock CK 2  transitions from the high voltage level to the low voltage level, the transfer transistor P 2  provides the pumping voltage located at the node ND 1  to the output terminal. The discharging of the node ND 2  is delayed. The transfer transistor P 1  is not turned off in time. As such, the power supplied to the pumping voltage of the output terminal may flow back to the power source VDDR via the transfer transistor P 1  and the turned-on power transistor M 2 , and the reverse leakage current Irev is thereby generated. Therefore, the dual-phase charge pump circuit  10  may exhibit low efficiency. 
     SUMMARY 
     The disclosure provides a charge pump circuit exhibiting high efficiency. 
     A charge pump circuit provided by the disclosure includes a dual-phase charge pump, a first load switch, a second load switch, and a control circuit. The dual-phase charge pump performs a voltage pumping operation on a power source in response to a first clock and a second clock to generate a first pumping voltage at a first node and a second pumping voltage at a second node. The first load switch is coupled between the second node and an output terminal of the dual-phase charge pump. The second load switch is coupled between the first node and the output terminal. The control circuit is coupled to the first load switch and the second load switch. The control circuit controls the first load switch in response to a third clock and controls the second load switch in response to a fourth clock. In a period during which the first load switch is turned off, the second load switch transfers the first pumping voltage to the output terminal. In a period during which the second load switch is turned off, the first load switch transfers the second pumping voltage to the output terminal. 
     To sum up, in the disclosure, the charge pump circuit controls the first load switch and the second load switch through the control circuit. Further, the control circuit controls the first load switch in response to the third clock and controls the second load switch in response to the fourth clock. In the period during which the second load switch is turned off, the first load switch transfers the first pumping voltage to the output terminal. In the period during which the first load switch is turned off, the second load switch transfers the second pumping voltage to the output terminal. In the disclosure, the reverse leakage current is not generated in the charge pump circuit. Therefore, the efficiency of the charge pump circuit may be improved. 
     To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG.  1    is a schematic diagram of an existing common dual-phase charge pump circuit. 
         FIG.  2    is a schematic diagram illustrating a charge pump circuit according to a first embodiment of the disclosure. 
         FIG.  3    is a graph illustrating signal waveforms according to an embodiment of the disclosure. 
         FIG.  4    is a schematic diagram illustrating a charge pump circuit according to a second embodiment of the disclosure. 
         FIG.  5    is a schematic diagram illustrating a charge pump circuit according to a third embodiment of the disclosure. 
         FIG.  6    is a schematic diagram illustrating a charge pump circuit according to a fourth embodiment of the disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Several embodiments of the disclosure are described in detail below accompanying with figures. In terms of the reference numerals used in the following descriptions, the same reference numerals in different figures should be considered as the same or the like elements. The embodiments are only a portion of the disclosure, which do not present all embodiments of the disclosure. More specifically, these embodiments are only examples in the scope of the patent application of the disclosure. 
     With reference to  FIG.  2   ,  FIG.  2    is a schematic diagram illustrating a charge pump circuit according to a first embodiment of the disclosure. In this embodiment, a charge pump circuit  100  includes a dual-phase charge pump  110 , load switches SW 1  and SW 2 , and a control circuit  120 . The dual-phase charge pump  110  performs a voltage pumping operation on a power source VDDA in response to clocks CK 1  and CK 2 . Therefore, the dual-phase charge pump  110  generates a pumping voltage VP 1  at a node ND 1  and generates a pumping voltage VP 2  at a node ND 2 . Voltage values of the pumping voltages VP 1  and VP 2  are greater than a voltage value of the power source VDDA. 
     In this embodiment, the dual-phase charge pump  110  includes power transistors M 1  and M 2  and capacitors C 1  and C 2 . A first terminal of the power transistor M 1  is coupled to the power source VDDA. A second terminal of the power transistor M 1  and a control terminal of the power transistor M 1  are coupled to the node ND 1 . A first terminal of the power transistor M 2  is coupled to the power source VDDA. A second terminal of the power transistor M 2  and a control terminal of the power transistor M 2  are coupled to the node ND 2 . The capacitor C 1  is coupled between the node ND 1  and the clock CK 1 . The capacitor C 2  is coupled between the node ND 2  and the clock CK 2 . In this embodiment, when the clock CK 1  is at a high voltage level and the clock CK 2  is at a low voltage level, a voltage at the node ND 1  is pumped up to generate a pumping voltage VP 1 . A voltage of the node ND 2  is restored to a voltage value substantially equal to a voltage value of the power source VDDA. When the clock CK 2  is at a high voltage level and the clock CK 1  is at a low voltage level, a voltage at the node ND 2  is pumped up to generate a. pumping voltage VP 2 . A voltage of the node ND 1  is restored to a voltage value substantially equal to the voltage value of the power source VDDA. 
     In this embodiment, the load switch SW 1  is coupled between the node ND 2  and an output terminal T 0  of the dual-phase charge pump circuit  100 . The load switch SW 2  is coupled between the node ND 1  and the output terminal T 0  of the dual-phase charge pump circuit  100 . The control circuit  120  is coupled to the load switches SW 1  and SW 2 . The control circuit  120  controls the load switch SW 1  in response to the clock CK 3  and controls the load switch SW 2  in response to the clock CK 4 . In a period during which the load switch SW 1  is turned off, the load switch SW 2  transfers the pumping voltage VP 1  to the output terminal T 0 . Therefore, the pumping voltage VP 1  transferred to the output terminal T 0  is treated as an output voltage VOUT. In a period during which the load switch SW 2  is turned off, the load switch SW 1  transfers the pumping voltage VP 2  to the output terminal T 0 . Therefore, the pumping voltage VP 2  transferred to the output terminal T 0  is treated as the output voltage VOUT. 
     It is worth noting that the control circuit  120  controls the load switches SW 1  and SW 2  based on the clocks CK 3  and CK 4 . In the period during which the load switch SW 1  is turned off the load switch SW 2  transfers the pumping voltage VP 1  to theoutput terminal T 0 . Power of the output voltage VOUT is not fed back to the power source VDDA through the turned-off load switch SW 1 . In the period during which the load switch SW 2  is turned off, the load switch SW 1  transfers the pumping voltage VP 2  to the output terminal T 0 . The power of the output voltage VOUT is not fed back to the power source VDDA through the turned-offload switch SW 2 . In operation, the dual-phase charge pump  110  is not provided with a reverse leakage current. In this way, efficiency of the charge pump circuit  100  may be improved. 
     Each of the load switches SW 1  and SW 2  is implemented by a transistor or a transfer gate in any form. Taking this embodiment as an example, each of the load switches SW 1  and SW 2  is implemented by a P-type metal-oxide-semiconductor field-effect transistor (MOSFET). 
     With reference to  FIG.  2    and  FIG.  3    together,  FIG.  3    is a graph illustrating signal waveforms according to an embodiment of the disclosure. The graph of signal waveforms shows a waveform of the output voltage VOUT, a waveform of an output current IOUT, a waveform of a voltage V_VDDA of the power source VDDA, a waveform of a current I_VDDA of the power source VDDA, and waveforms of the clocks CK 1  to CK 4 . The horizontal axis of the graph of signal waveforms is uniformly represented by time t. The unit of time t is micro seconds (μs). 
     At a time point t 1 , the clock CK 3  transitions from a low voltage level to a high voltage level. The load switch SW 1  is turned off in response to the high voltage level of the clock CK 3 . immediately after the time point t 1 , the clock CK 2  transitions from a high voltage level to a low voltage level at a time point t 2 . The clock CK 1  transitions from a low voltage level to a high voltage level at a time point t 3 . Therefore, the voltage at the node ND 1  may start to be pumped up at the time point t 3  to generate the pumping voltage VP 1 . A voltage value of the node ND 2  is restored to a voltage value substantially equal to the voltage value of the power source VDDA. In this embodiment, a transition time point (i.e., the time point t 3 ) at which the clock CK 1  transitions from the low voltage level to the high voltage level is later than the time point t 1 . That is, the time point (i.e., the time point t 3 ) at which the pumping voltage VP 1  starts to be generated is later than the time point at which the load switch SW 1  is turned off. 
     Next, at a time point t 4 , the clock CK 4  transitions from a high voltage level to a low voltage level. The load switch SW 2  is turned on in response to the low voltage level of the clock CK 4 . The time point t 4  at which the load switch SW 2  is turned on is later than the time point t 3 . That is, the control circuit  120  turns on the load switch SW 2  after the pumping voltage VP 1  is generated. 
     At a time point t 5 , the clock CK 4  transitions from the low voltage level to the high voltage level. The load switch SW 2  is turned off in response to the high voltage level of the clock CK 4 . Immediately after the time point t 5 , the clock CK 1  transitions from the high voltage level to the low voltage level at a time point t 6 . The clock CK 2  transitions from the low voltage level to the high voltage level at a time point t 7 . Therefore, the voltage at the node ND 2  may start to be pumped up at the time point t 7  to generate the pumping voltage VP 2 . The voltage value of the node ND 1  is restored to a voltage value substantially equal to the voltage value of the power source VDDA. In this embodiment, the transition time point (i.e., the time point t 7 ) at which the clock CK 2  transitions from the low voltage level to the high voltage level is later than the time point (i.e., the time point t 5 ) at which the load switch SW 2  is turned off. That is, the time point (i.e., the time point t 7 ) at which the pumping voltage VP 2  starts to be generated is later than the time point at which the load switch SW 2  is turned off. 
     Next, at a time point t 8 , the clock CK 3  transitions from the high voltage level to the low voltage level. The load switch SW 1  is turned on in response to the low voltage level of the clock CK 3 . The time point t 8  at which the load switch SW 2  is turned on is later than the time point t 7 . That is, the control circuit  120  turns on the load switch SW 1  after the pumping voltage VP 2  is generated. 
     In a time interval from the time point ti to the time point t 8 , the load switch SW 1  is in an off state. The pumping voltage VP 1  is generated only in the period during which the load switch SW 1  is determined to be in the off state. In addition, in the period during which the pumping voltage VP 1  is generated (i.e., a time interval from the time point t 3  to the time point t 6 ), the load switch SW 2  is turned on in a time interval from the time point t 4  to the time point t 5 . In this way, the reverse leakage current flowing through the load switch SW 1  may not be generated. 
     Similarly, the pumping voltage VP 2  is generated only in the period during which the load switch SW 2  is determined to be in the off state. In addition, in the period during which the pumping voltage VP 2  is generated, the load switch SW 1  is turned on. In this way, the reverse leakage current flowing through the load switch SW 2  may not be generated. 
     In this embodiment, the voltage value of the voltage V_VDDA of the power source VDDA is maintained at 1.1 volts. An absolute value of an average current value of the current I_VDDA of the power source VDDA is about 4.0007 mA. A voltage value of the output voltage VOUT is approximately 1.8944 volts. A current value of the output current IOUT is approximately 2,0018 mA. Therefore, the efficiency of the charge pump circuit  100  is 86.2%. It should be noted that the efficiency of the dual-phase charge pump circuit  10  shown in  FIG.  1    is approximately 56%. Therefore, the efficiency of the charge pump circuit  100  is significantly greater than that of the dual-phase charge pump circuit  10 . 
     With reference to  FIG.  4   ,  FIG.  4    is a schematic diagram illustrating a charge pump circuit according to a second embodiment of the disclosure. In this embodiment, a charge pump circuit  200  includes the dual-phase charge pump  110 , the load switches SW 1  and SW 2 , and a control circuit  220 . The implementation of the dual-phase charge pump  110  is clearly described in the first embodiment, so repeated description is not provided herein. In this embodiment, the control circuit  220  includes control transistors M 3  and M 4  and control capacitors C 3  and C 4 . A first terminal of the control transistor M 3  is coupled to the power source VDDA. A second terminal of the control transistor M 3  is coupled to the node ND 3 . A control terminal of the control transistor M 3  is coupled to the node ND 2 . A first terminal of the control transistor M 4  is coupled to the power source VDDA. A second terminal of the control transistor M 4  is coupled to the node ND 4 . A control terminal of the control transistor M 4  is coupled to the node ND 1 . The control capacitor C 3  is coupled between the node ND 3  and the clock CK 3 . The control capacitor C 4  is coupled between the node ND 4  and the clock CK 4 . 
     In this embodiment, a control terminal of the load switch SW 1  is coupled to the node ND 3 . A control terminal of the load switch SW 2  is coupled to the node ND 4 . The control circuit  220  provides a first control signal SC 1  in response to the clock CK 3 . The control circuit  220  controls the load switch SW 1  through the first control signal SC 1 . In addition, the control circuit  220  further provides a second control signal SC 2  in response to the clock CK 4 . The control circuit  220  controls the load switch SW 2  through the second control signal SC 2 . 
     With reference to  FIG.  3    and  FIG.  4    together, in this embodiment, in the period during which the pumping voltage VP 1  is generated (i.e., the time interval from the time point t 3  to the time point t 6 ), the pumping voltage VP 2  is not generated. Therefore, the control transistor M 3  is turned off. The control transistor M 4  is turned on. A voltage level of the node ND 3  is pumped up based on clock CK 3 . A voltage level of the node ND 4  is substantially equal to a voltage level of the power source VDDA. Since the time points t 1  and t 2  are considerably close, based on the delay of the control capacitor C 3 , the transition of the clock CK 3  may still cause the voltage level of the node ND 3  to be pumped up to generate the first control signal SC 1  with a first voltage level. The first voltage levels greater than the voltage level of the power source VDDA. Therefore, the load switch SW 1  is turned off in response to the first control signal SC 1  with the first voltage level. Therefore, the load switch SW 2  is turned on in response to the second control signal SC 2  with the voltage level of the power source VDDA. 
     In the time interval at which the pumping voltage VP 2  is generated, the pumping voltage VP 1  is not generated. Therefore, the control transistor M 4  is turned off. The control transistor M 3  is turned on. Since the time points t 5  and t 6  are considerably close, based on the delay of the control capacitor C 4 , the transition of the clock CK 4  may still cause the voltage level of the node ND 4  to be pumped up to generate the second control signal SC 2  with the first voltage level. Therefore, the load switch SW 2  is turned off in response to the second control signal SC 2  with the first voltage level. The voltage level of the node ND 3  is substantially equal to the voltage level of the power source VDDA. Therefore, the load switch SW 1  is turned on in response to the first control signal SC 1  with the voltage level of the power source VDDA. 
     In this embodiment, the charge pump circuit  200  further includes an adjustment circuit  230 . The adjustment circuit  230  is coupled to the control circuit  220  and the load switches SW 1  and SW 2 . The adjustment circuit  230  adjusts a base electrode biasing value of the load switches SW 1  and SW 2  in response to the pumping voltages VP 1  and VP 2 , the first control signal SC 1 , and the second control signal SC 2 . 
     In this embodiment, the adjustment circuit  230  includes adjustment transistors MA 1  and MA 2  and a charge storage circuit  231 . A first terminal of the adjustment transistor MA 1  is coupled to the node ND 2 . A second terminal of the adjustment transistor MA 1  and a base electrode of the adjustment transistor MA 1  are coupled to a based electrode of the load switch SW 1 . A control terminal of the adjustment transistor MA 1  is coupled to the ode ND 3 . A first terminal of the adjustment transistor MA 2  is coupled to the node ND 1 . A second terminal of the adjustment transistor MA 2  and a base electrode of the adjustment transistor MA 2  are coupled to a based electrode of the load switch SW 2 . A control terminal of the adjustment transistor MA 2  is coupled to the node ND 4 . The charge storage circuit  231  is coupled to the second terminal of the adjustment transistor MA 1  and the second terminal of the adjustment transistor MA 2 . The charge storage circuit  231  stores charges of the pumping voltages VP 1  and VP 2  to generate an auxiliary biasing value Vx for determining the base electrode biasing value. In this embodiment, the base electrode biasing value is adjusted based on the auxiliary biasing value Vx to be greater than a voltage value at the output terminal T 0 . In this way, the adjustment circuit  230  may prevent a latch-up effect from occurring in the load switches SW 1  and SW 2 . 
     It should be noted that the second terminal of the control transistor M 3  is coupled to the control terminal of the adjustment transistor MA 1  and the control terminal of the load switch SW 1 . The second terminal of the control transistor M 4  is coupled to the control terminal of the adjustment transistor MA 2  and the control terminal of the load switch SW 2 . The control transistors M 3  and M 4  do not become the flow paths of the reverse leakage current. In addition, the second terminals of the adjustment transistors MA 1  and MA 2  are commonly coupled to the base electrodes of the load switches SW 1  and SW 2 . Therefore, the adjustment transistors MA 1  and MA 2  do not become: the flow paths of the reverse leakage current. 
     In this embodiment, the control circuit  220  does not execute the transmission of the pumping voltages VP 1  and VP 2 , but controls the load switches SW 1  and SW 2  and the adjustment transistors MA 1  and MA 2 . Therefore, a layout area of the control transistors M 3  and M 4  may be allowed to be less than a layout area of the power transistors M 1  and M 2 . In some embodiments, a layout area of the control capacitors C 3  and C 4  may be allowed to be less than a layout area of the capacitors C 1  and C 2 . For instance, a layout area of the control circuit  220  may be 5% of a layout area of the dual-phase charge pump  110 , but the disclosure is not limited thereto. 
     In this embodiment, the charge storage circuit  231  includes a capacitor Cx. The capacitor Cx is coupled between a reference low voltage (e.g., a ground voltage) and the second ends of the adjustment transistors MA 1  and MA 2 . The capacitor Cx stores the charges of the pumping voltages VP 1  and VP 2 . 
     With reference to  FIG.  5   ,  FIG.  5    is a schematic diagram illustrating a charge pump circuit according to a third embodiment of the disclosure. The charge pump circuit  300  includes the dual-phase charge pump  110 , the load switches SW 1  and SW 2 , the control circuit  220 , an adjustment circuit  330 , and a voltage divider circuit  340 . The implementation of the dual-phase charge pump  110 , the load switches SWI and SW 2 , and the control circuit  220  is clearly described in the first embodiment and the second embodiment, so repeated description is not provided herein. In this embodiment, the adjustment circuit  330  includes the adjustment transistors MA 1  and MA 2  and a charge storage circuit  331 . The first terminal of the adjustment transistor MA 1  is coupled. to the node ND 2 . The second terminal of the adjustment transistor MA 1  and the base electrode of the adjustment transistor MA 1  are coupled to the based electrode of the load switch SW 1 . The control terminal of the adjustment transistor MA 1  is coupled to the node ND 3 . The first terminal of the adjustment transistor MA 2  is coupled to the node ND 1 . The second terminal of the adjustment transistor MA 2  and the base electrode of the adjustment transistor MA 2  are coupled to the based electrode of the load switch SW 2 . The control terminal of the adjustment transistor MA 2  is coupled to the node ND 4 . The charge storage circuit  331  is coupled to the second terminal of the adjustment transistor MA 1  and the second terminal of the adjustment transistor MA 2 . The charge storage circuit  331  stores the charges of the pumping voltages VP 1  and VP 2  to generate the auxiliary biasing value Vx. The voltage divider circuit  340  is coupled to the charge storage circuit  331  and the base electrodes of the load switches SW 1  and SW 2 . 
     In this embodiment, the charge storage circuit  331  stores the charges of the pumping voltages VP 1  and VP 2  to generate the auxiliary biasing value Vx. The voltage divider circuit  340  receives the auxiliary biasing value Vx from the charge storage circuit  331  and divides the auxiliary biasing value Vx to generate a base electrode biasing value Vy. Based on the voltage dividing operation of the voltage divider circuit  340 , in this way, threshold voltages of the load switches SW 1  and SW 2  are lowered, and on-resistance values of the load switches SW 1  and SW 2  are lowered. The load switches SW 1  and SW 2  may transmit a larger current value, such that the efficiency of the charge pump circuit  300  is improved. 
     In this embodiment, the voltage divider circuit  340  includes resistors R 1  and R 2  and a current source Ib. A first terminal of the resistor R 1  is coupled to the charge storage circuit  331  to receive the auxiliary biasing value Vx. A second terminal of the resistor R 1  is coupled to a voltage divider node. A first terminal of the resistor R 2  is coupled to the voltage divider node. The current source Ib is coupled to a second terminal of the resistor R 2 . The current source Ib is configured to limit an operating current of the voltage divider circuit  340  to control a voltage difference across the resistor R 1  and the base electrode biasing value Vy. 
     Further, the voltage difference across the resistor R 1  may be determined based on the operating current provided by the current source Ib. The voltage difference across the resistor R 1  is defined to be less than a forward biasing value of a parasitic diode. The voltage difference across the resistor R 1  is, for example, 0.5 volts to 0.6 volts. Therefore, the voltage divider circuit  340  may prevent a latch-up effect from occurring in the charge pump circuit  300 . 
     In some embodiments, at least one of the resistors R 1  and R 2  may be implemented by a variable resistance circuit. 
     With reference to  FIG.  6   ,  FIG.  6    is a schematic diagram illustrating a charge pump circuit according to a fourth embodiment of the disclosure. In this embodiment, a charge pump circuit  400  is disposed on a substrate. The charge pump circuit  400  may be an on-chip circuit. The charge pump circuit  400  includes a dual-phase charge pump  410 , the load switches SW 1  and SW 2 , the control circuit  220 , the adjustment circuit  330 , and the voltage divider circuit  340 . The implementation of the load switches SW 1  and SW 2 , the control circuit  220 , the adjustment circuit  330 , and the voltage divider circuit  340  is clearly described in the foregoing embodiments, so repeated description is not provided herein. In this embodiment, the dual-phase charge pump  410  includes the power transistors M 1  and M 2  and the capacitors C 1  and C 2 . The first terminal of the power transistor M 1  is coupled to the power source VDDA. The second terminal of the power transistor M 1  and the control terminal of the power transistor M 1  are coupled to the node ND 1 . The first terminal of the power transistor M 2  is coupled to the power source VDDA. The second terminal of the power transistor M 2  and the control terminal of the power transistor M 2  are coupled to the node ND 2 . 
     It should be noted that in this embodiment, a first terminal of the capacitor C 1  is coupled to the node ND 1 . A second terminal of the capacitor C 1  is coupled to a well W 1  of the substrate. The capacitor C 1  receives the clock CK 1  through the well W 1 . A first terminal of the capacitor C 2  is coupled to the node ND 2 . A second terminal of the capacitor C 2  is coupled to a well W 2  of the substrate. The capacitor C 2  receives the clock CK 2  through the well W 2 . 
     In this embodiment, when the capacitor C 1  receives the clock CK 1  through the well W 1 , the capacitor C 1  and the well W 1  are treated as being coupled to each other in series. The capacitor C 1  and the well W 1  are formed together to provide an equivalent capacitance value. Since the well W 1  of the substrate has a considerably low capacitance value (that is, a parasitic capacitance value), the equivalent capacitance value is significantly lower than a capacitance value of the capacitor C 1 . In this way, the node ND 1  may have a fast response speed. Both the charging time and the discharging time of the node ND 1  may be shortened. 
     Similarly, when the capacitor C 2  receives the clock CK 2  through the well W 2 , the capacitor C 2  and the well W 2  are treated as being coupled to each other in series. The capacitor C 2  and the well W 2  are formed together to provide an equivalent capacitance value. Since the well W 2  of the substrate has a considerably low capacitance value, the equivalent capacitance value is significantly lower than a capacitance value of the capacitor C 2 . In this way, the node ND 2  may have a fast response speed. Both the charging tine and the discharging time of the node ND 2  may be shortened. 
     In this embodiment, the wells W 1  and W 2  are N-type wells. In some embodiments, the wells W 1  and W 2  are N-type wells with heavy doping. 
     In view of the foregoing, in the disclosure, the control circuit of the charge pump circuit controls the first load switch in response to the third clock and controls the second load switch in response to the fourth clock. In the period during which the second load switch is turned off, the first load switch transfers the first pumping voltage to the output terminal. In the period during which the first load switch is turned off, the second load switch transfers the second pumping voltage to the output terminal. In the disclosure, the reverse leakage current is not generated in the charge pump circuit. In this way, the efficiency of the charge pump circuit may be improved. In some embodiments, through the adjustment circuit of the charge pump circuit, the base electrode biasing value of the first load switch and the second load switch may be adjusted to be greater than the voltage value located at the output terminal. In this way, the adjustment circuit may prevent a latch-up effect from occurring in the first load switch and the second load switch. Besides, in some embodiments, the first capacitor of the dual-phase charge pump receives the first clock through the first well. The second capacitor of the dual-phase charge pump receives the second clock through the second well. In this way, the first node and the second node may have fast response speeds. Both the charging time and the discharging time of the first node and the second node may be shortened. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.