Patent Publication Number: US-10790813-B2

Title: Drive circuit for power semiconductor element

Description:
TECHNICAL FIELD 
     The present disclosure relates to a drive circuit for a power semiconductor element, and more particularly to a drive circuit having functions of detecting a short-circuit state of a power semiconductor element and protecting the power semiconductor element. 
     BACKGROUND ART 
     When a short-circuit state occurs in a power semiconductor element such as an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET), a high current flows therethrough, which may cause thermal destruction of the power semiconductor element. Accordingly, there is a need to provide functions of detecting a short-circuit state of the power semiconductor element and protecting the power semiconductor element. 
     As a drive circuit having functions of detecting a short-circuit state of a power semiconductor element and protecting the power semiconductor element, for example, Japanese Patent Laying-Open No. 2015-53749 (PTL 1) discloses a configuration in which a turn-on command is output to a power semiconductor element, and subsequently, an amount of electric charge supplied to a gate terminal of the power semiconductor element and a gate voltage applied to the gate terminal are detected, to thereby determine based on the detected amount of electric charge and the detected gate voltage whether the power semiconductor element is in a short-circuit state or not. 
     CITATION LIST 
     Patent Literature 
     PTL 1: Japanese Patent Laying-Open No. 2015-53749 
     SUMMARY OF INVENTION 
     Technical Problem 
     The drive circuit disclosed in the above-mentioned PTL 1 employs a configuration in which the short-circuit state of the power semiconductor element is determined based on the detection values of the amount of electric charge and the gate voltage, thereby allowing an immediate detection of the short-circuit state of the power semiconductor element as compared with the conventional technique by which a determination operation is performed based on the detection value of the collector voltage in the power semiconductor element. 
     However, the drive circuit disclosed in PTL 1 is required to include: a gate voltage detection unit for detecting a gate voltage; and an electric charge amount detection unit for detecting the amount of electric charge. This electric charge amount detection unit is configured to detect the gate current flowing into the gate terminal or the voltage corresponding to the gate current, thereby calculating the amount of electric charge. This causes a problem that the configuration of the entire drive circuit becomes complicated, so that the device is increased in size and cost. 
     The present invention has been made to solve the above-described problems. An object of the present invention is to provide a drive circuit for a power semiconductor element, by which a short-circuit state of the power semiconductor element can be speedily detected in a simple configuration. 
     Solution to Problem 
     A drive circuit for a power semiconductor element according to the present disclosure is a drive circuit for a power semiconductor element having a first terminal, a second terminal, and a gate terminal. The drive circuit includes a control command unit, a gate voltage detection unit, a differentiator, and a determination unit. The control command unit outputs a turn-on command for the power semiconductor element. The gate voltage detection unit detects a gate voltage applied to the gate terminal after the control command unit outputs the turn-on command. The differentiator subjects the gate voltage detected by the gate voltage detection unit to time differentiation. The determination unit determines, based on the gate voltage detected by the gate voltage detection unit and a differential value by the differentiator, whether the power semiconductor element is in a short-circuit state or not. 
     Advantageous Effects of Invention 
     The present disclosure can provide a drive circuit for a power semiconductor element, by which a short-circuit state of the power semiconductor element can be speedily detected in a simple configuration. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a diagram showing the configuration of a power semiconductor element and a drive circuit therefor according to the first embodiment of the present invention. 
         FIG. 2  is a diagram showing a waveform of a gate voltage in a turn-on operation in an IGBT in each of a normal state and an arm short-circuit state. 
         FIG. 3  is a diagram showing the relation between the gate voltage and its differential value in the turn-on operation in the IGBT in each of the normal state and the arm short-circuit state. 
         FIG. 4  is a diagram showing a waveform of a gate voltage in a turn-on operation in an SiC-MOSFET in each of the normal state and the arm short-circuit state. 
         FIG. 5  is a diagram showing the relation between the gate voltage and its differential value in the turn-on operation in the SiC-MOSFET in each of the normal state and the arm short-circuit state. 
         FIG. 6  is a flowchart for illustrating the process procedure of the operation of determining whether the power semiconductor element is in a short-circuit state or not. 
         FIG. 7  is a diagram showing the configuration of a drive circuit for a power semiconductor element according to the second embodiment of the present invention. 
         FIG. 8  is a diagram showing the configuration of a drive circuit for a power semiconductor element according to the third embodiment of the present invention. 
         FIG. 9  is a diagram showing the configuration of a drive circuit for a power semiconductor element according to the fourth embodiment of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     The embodiments of the present invention will be hereinafter described in detail with reference to the accompanying drawings. In the following description, the same or corresponding components in the accompanying drawings will be designated by the same reference characters, and the description thereof will not be basically repeated. 
     First Embodiment 
       FIG. 1  is a diagram showing the configuration of a power semiconductor element and a drive circuit therefor according to the first embodiment of the present invention.  FIG. 1  shows an IGBT as a power semiconductor element  101 , which is however not necessarily limited to an IGBT but may be a self-arc-extinguishing type semiconductor element such as a MOSFET. Power semiconductor element  101  is included in a power converter such as an inverter for converting direct-current (DC) power into alternating-current (AC) power, and a rectifier for converting AC power into DC power. 
     Power semiconductor element  101  has a collector terminal  101   c , an emitter terminal  101   e , and a gate terminal  101   g . Collector terminal  101   c  corresponds to one example of the “first terminal” in the present invention while emitter terminal  101   e  corresponds to one example of the “second terminal”. The voltage applied to collector terminal  101   c  is higher than the voltage applied to emitter terminal  101   e.    
     Referring to  FIG. 1 , drive circuit  100  serves as a circuit that drives power semiconductor element  101 , and includes a control command unit  102 , a gate voltage detection unit  103 , a differentiator  104 , a first reference value generation circuit  105 , a second reference value generation circuit  106 , a first comparator  107 , a third reference value generation circuit  108 , a second comparator  109 , and a short-circuit determination unit  110 . 
     Upon reception of an ON command from outside, control command unit  102  outputs a gate command (turn-on command) to gate terminal  101   g  of power semiconductor element  101 . The gate command (turn-on command) serves to bring power semiconductor element  101  into a conductive state (an ON state) (hereinafter referred to as “turn on”). Thereby, power semiconductor element  101  is turned on and brought into a conductive state. 
     Upon reception of an OFF command from outside, control command unit  102  outputs a gate command (turn-off command) to gate terminal  101   g  of power semiconductor element  101 . The gate command (turn-off command) serves to bring power semiconductor element  101  into a cut-off state (an OFF state) (hereinafter referred to as “turn off”). Thereby, power semiconductor element  101  is turned off and brought into a cut-off state. 
     After reception of the turn-on command from control command unit  102 , gate voltage detection unit  103  detects the gate voltage applied to gate terminal  101   g  of power semiconductor element  101 . Gate voltage detection unit  103  outputs a signal showing a gate voltage E that has been detected. 
     First reference value generation circuit  105  generates a first reference value REF 1  (unit [V]). 
     Second reference value generation circuit  106  generates a second reference value REF 2  (unit [V]). Second reference value REF 2  is greater than first reference value REF 1  (REF 1 &lt;REF 2 ). 
     First comparator  107  compares gate voltage E detected by gate voltage detection unit  103  with each of first reference value REF 1  and second reference value REF 2 , and outputs a signal S 1  showing a comparison result. When gate voltage E is higher than first reference value REF 1  and lower than second reference value REF 2  (that is, REF 1 &lt;E&lt;REF 2 ), signal S 1  is at an “H (logic high)” level. On the other hand, when gate voltage E is equal to or less than first reference value REF 1  (that is, E≤REF 1 ) or when gate voltage E is equal to or greater than second reference value REF 2  (that is, E≥REF 2 ), signal S 1  is at an “L (logic low)” level. 
     Differentiator  104  subjects gate voltage E detected by gate voltage detection unit  103  to time differentiation and outputs a differential value D. Differential value D is represented by D=dE/dt using gate voltage E. 
     Third reference value generation circuit  108  generates a third reference value REF 3  (unit [V/s]). 
     Second comparator  109  compares differential value D by differentiator  104  with third reference value REF 3 , and outputs a signal S 2  showing a comparison result. When differential value D is greater than third reference value REF 3  (that is, D&gt;REF 3 ), signal S 2  is at an “H” level. When differential value D is equal to or less than third reference value REF 3  (that is, D≤REF 3 ), signal S 2  is at an “L” level. 
     Short-circuit determination unit  110  (a determination unit) computes a logical product of signal S 1  output from first comparator  107  and signal S 2  output from second comparator  109 , thereby determining whether power semiconductor element  101  is in a short-circuit state or not. Short-circuit determination unit  110  outputs a signal SS that shows the determination result to control command unit  102 . 
     When both signal S 1  and signal S 2  each are at an “H” level, signal SS is at an “H” level showing that power semiconductor element  101  is in a short-circuit state. In other words, when gate voltage E is higher than first reference value REF 1  and lower than second reference value REF 2  (REF 1 &lt;E&lt;REF 2 ) and when differential value D is greater than third reference value REF 3  (D&gt;REF 3 ), signal SS is at an “H” level. On the other hand, when one of signal S 1  and signal S 2  is at an “L” level, signal SS is at an “L” level showing that power semiconductor element  101  is in a normal state. 
     Upon reception of signal SS at an “H” level from short-circuit determination unit  110 , control command unit  102  outputs a turn-off command to power semiconductor element  101  in order to cut off power semiconductor element  101 . 
     In addition, when power semiconductor element  101  is turned off upon reception of the turn-off command from control command unit  102 , gate voltage E falls. In this case, when gate voltage E becomes equal to or less than first reference value REF 1 , signal S 1  output from first comparator  107  changes to an “L” level. Thus, signal SS that is a logical product of signal S 1  and signal S 2  also eventually changes to an “L” level. Thereby, short-circuit determination unit  110  erroneously determines that power semiconductor element  101  is not in a short-circuit state. Upon reception of signal SS at an “L” level from short-circuit determination unit  110 , control command unit  102  outputs a turn-on command again, thereby preventing cutting-off of power semiconductor element  101 . 
     In order to avoid such a problem, control command unit  102  has a function of holding signal SS of an “H” level upon reception of this signal SS from short-circuit determination unit  110 . Thereby, when it is determined that power semiconductor element  101  is in a short-circuit state, power semiconductor element  101  is cut off according to the turn-off command. Thus, also in the case where gate voltage E falls to be equal to or less than first reference value REF 1 , control command unit  102  continuously outputs a turn-off command. Therefore, protection against the arm short-circuit can be reliably ensured without interfering with the cut-off operation for protecting power semiconductor element  101 . 
     As described above, drive circuit  100  according to the first embodiment is configured to determine whether power semiconductor element  101  is in a short-circuit state or not based on gate voltage E and its differential value D in the turn-on operation of power semiconductor element  101 . Such a configuration can be implemented by utilizing the feature that the relation between the gate voltage and its differential value in the turn-on operation is different between the normal state and the arm short-circuit state in power semiconductor element  101 , as will be described below. 
       FIG. 2  is a diagram showing a waveform of a gate voltage V GE  in the turn-on operation in an IGBT in each of the normal state and the arm short-circuit state. In the figure, a solid line L 1  shows a waveform of gate voltage V GE  in the turn-on operation in the normal state while a dashed line L 2  shows a waveform of gate voltage V GE  in the turn-on operation in the arm short-circuit state. 
     As shown in  FIG. 2 , in the normal state, when a turn-on command is output to the gate terminal of the IGBT at time t 0 , gate voltage V GE  rises. In the IGBT, the capacitance occurring with respect to the gate terminal includes: a parasitic capacitance component that occurs between the gate terminal and the collector terminal (hereinafter referred to as a “gate-collector capacitance C GC ”); and a parasitic capacitance component that occurs between the gate terminal and the emitter terminal (hereinafter referred to as a “gate-emitter capacitance C GE ”). Gate-collector capacitance C GC  is equivalent to a feedback capacitance in the IGBT. Gate-collector capacitance C GC  and gate-emitter capacitance C GE  are connected in parallel with respect to the gate terminal. 
     When a voltage is applied to the gate terminal at time t 0 , gate-emitter capacitance C GE  is charged and gate voltage V GE  gradually rises. The time period from time t 0  to time t 1  corresponds to a charging time period of gate-emitter capacitance C GE . 
     Then, when gate voltage V GE  exceeds a threshold voltage V th  at time t 1 , the IGBT is started to be turned on. When the IGBT is turned on, a current starts to flow therethrough and the voltage at the collector terminal starts to decrease. In the time period between time t 1  and t 2 , most of the gate current flows through gate-collector capacitance C GC , but a current does not flow through gate-emitter capacitance C GE . Accordingly, gate voltage V GE  does not rise but is kept in a constant state. 
     The time period during which gate voltage V GE  is kept constant as in the time period between time t 1  and time t 2  is referred to as a “Miller period”. Also, this constant voltage value (equivalent to V m  in the figure) is referred to as a “Miller voltage”. The length of the Miller period is set in accordance with gate-collector capacitance C GC . In other words, when gate-collector capacitance C GC  becomes smaller, the Miller period becomes shorter. Also, when gate-collector capacitance C GC  becomes larger, the Miller period becomes longer. 
     After the end of the Miller period (at and after time t 2 ), gate voltage V GE  rises to a gate drive power supply voltage while charging gate-emitter capacitance C GE . The time period between time t 2  and time t 3  corresponds to the charging time period of gate-emitter capacitance C GE . 
     On the other hand, in the arm short-circuit state, collector-emitter voltage V CE  hardly changes while being kept in a high-voltage state, and the feedback capacitance (gate-collector capacitance C GC ) remains at an approximately constant value. As a result, no current flows through gate-collector capacitance C GC , so that no Miller period appears. Consequently, gate voltage V GE  rises all at once to the gate drive power supply voltage. 
     Thus, in the IGBT, between the normal state and the arm short-circuit state, there is a significant difference as to whether a Miller period appears or not in the waveform of gate voltage V GE  in the turn-on operation. Since gate voltage V GE  is kept at a constant value during a Miller period, a differential value (dV GE /dt) obtained by subjecting gate voltage V GE  to time differentiation is ideally zero. Therefore, as shown in  FIG. 3 , also in the relation between gate voltage V GE  and its differential value, a significant difference is to appear between the normal state and the arm short-circuit state. 
       FIG. 3  is a diagram showing the relation between gate voltage V GE  and its differential value (dV GE /dt) in the turn-on operation in the IGBT in each of the normal state and the arm short-circuit state. A solid line k 1  in the figure shows the relation between gate voltage V GE  and its differential value (a gate voltage-differential value curve) in the normal state. A dashed line k 2  in the figure shows the relation between gate voltage V GE  and its differential value (a gate voltage-differential value curve) in the arm short-circuit state. 
     In  FIG. 3 , the relation shown by solid line k 1  is derived using a differential value obtained by subjecting the waveform of gate voltage V GE  shown by solid line L 1  in  FIG. 2  to time differentiation. In addition, in gate voltage V GE =V m , Miller voltage V m  is set to have a fixed width (V m1 ≤V m ≤V m2 ). This is based on the feature that Miller voltage V m  varies depending on the current value flowing through the IGBT. When the current value is relatively small, Miller voltage V m  has a relatively low voltage value. When the current value is relatively large, Miller voltage V m  has a relatively high voltage value. 
     In the normal state, the differential value before and after the Miller period is a value close to a positive value X 1 . Also, the differential value during the Miller period is a value close to zero. Thus, in the relation shown by solid line k 1 , the differential value becomes a value close to zero when gate voltage V GE  is a Miller voltage V m . 
     On the other hand, the relation shown by dashed line k 2  is derived using a differential value obtained by subjecting the waveform of gate voltage V GE  shown by dashed line L 2  in  FIG. 2  to time differentiation. In the arm short-circuit state, gate voltage V GE  rises all at once to the gate drive power supply voltage. Accordingly, in the relation shown by dashed line k 2 , the differential value is kept in an approximately constant state with respect to gate voltage V GE . 
     In  FIGS. 2 and 3 , the IGBT has been described with regard to the relation between the gate voltage and its differential value in the turn-on operation. However, as will be described later with reference to  FIGS. 4 and 5 , the same tendency as that in the IGBT can be observed also in the SiC-MOSFET. 
       FIG. 4  is a diagram showing a waveform of a gate voltage V GS  in a turn-on operation in a SiC-MOSFET in each of the normal state and the arm short-circuit state. Solid line L 3  in the figure shows the waveform of gate voltage V GS  in the normal state while dashed line L 4  in the figure shows the waveform of gate voltage V GS  in the turn-on operation in the arm short-circuit state. 
     As shown in  FIG. 4 , in the normal state, when a turn-on command is output to the gate terminal of the SiC-MOSFET at time t 0 , gate voltage V GS  rises. In the SiC-MOSFET, the capacitance that occurs with respect to the gate terminal includes: a parasitic capacitance component that occurs between the gate terminal and the drain terminal (hereinafter referred to as a “gate-drain capacitance C GD ”); and a parasitic capacitance component that occurs between the gate terminal and the source terminal (hereinafter referred to as a “gate-source capacitance C GS ”). Gate-drain capacitance C GD  and gate-source capacitance C GS  are connected in parallel with respect to the gate terminal. 
     When a voltage is applied to the gate terminal at time t 0 , gate-source capacitance C GS  is first charged, and then, gate voltage V GS  gradually rises. The time period between time t 0  and time t 11  corresponds to the charging time period of gate-source capacitance C GS . When gate voltage V GE  exceeds a threshold voltage V th1 , the SiC-MOSFET is started to be turned on. When the SiC-MOSFET is turned on, a current starts to flow therethrough and the voltage at the drain terminal starts to decrease. In order to charge gate-drain capacitance C GD , a current starts to flow toward gate-drain capacitance C GD . The time period between time t 11  and time t 12  corresponds to a gate current propagation time period of gate-drain capacitance C GD . 
     In this time period, unlike the IGBT, most of the gate current flows into gate-drain capacitance C GD  and a part of the current flows also into gate-source capacitance C GS . Thus, gate-source capacitance C GS  is also charged concurrently with charging of gate-drain capacitance C GD , with the result that gate voltage V GS  gently rises. In the specification of the present application, the time period during which gate voltage V GS  gently rises from a Miller voltage V m11  to a Miller voltage V m12  as in the time period between time t 11  and time t 12  in  FIG. 4  is referred to as a Miller period of an SiC-MOSFET. 
     On the other hand, in the arm short-circuit state, drain-source voltage V DS  hardly changes while being kept in a high-voltage state. As a result, no Miller period appears, and gate voltage V GS  rises all at once to a gate drive power supply voltage. 
       FIG. 5  is a diagram showing the relation between gate voltage V GS  and its differential value (dV GS /dt) in the turn-on operation in the SiC-MOSFET in each of the normal state and the arm short-circuit state. A solid line k 3  in the figure shows the relation between gate voltage V GS  and its differential value in the normal state. A dashed line k 4  in the figure shows the relation between gate voltage V GS  and its differential value in the arm short-circuit state. 
     In  FIG. 5 , the relation shown by solid line k 3  is derived using a differential value obtained by subjecting the waveform of gate voltage V GS  shown by solid line L 3  in  FIG. 4  to time differentiation. As shown in  FIG. 4 , gate voltage V GS  rises gently in a Miller period in the normal state. Thus, in the relation shown by solid line k 3 , the differential value before and after the Miller period is a value close to a positive value X 2 , and the differential value in the Miller period is a positive value X 3  smaller than the differential value before and after the Miller period. 
     On the other hand, the relation shown by dashed line k 4  is derived using a differential value obtained by subjecting the waveform of gate voltage V GS  shown by dashed line L 4  in  FIG. 4  to time differentiation. In the arm short-circuit state, gate voltage V GS  rises all at once to a gate drive power supply voltage. Accordingly, in the relation shown by dashed line k 4 , the differential value is kept in an approximately constant state with respect to gate voltage V GS . 
     Also in the SiC-MOSFET, as in the IGBT, there is thus a significant difference between the normal state and the arm short-circuit state as to whether a Miller period appears or not in the waveform of gate voltage V GS . As a result, also in the relation between gate voltage V GS  and its differential value, a significant difference is to appear between the normal state and the arm short-circuit state. Therefore, using the relation between gate voltage V GS  and its differential value, it can be determined whether the SiC-MOSFET is in a short-circuit state or not. 
     The following is an explanation about first reference value REF 1 , second reference value REF 2  and third reference value REF 3  that are used for determining whether power semiconductor element  101  is in a short-circuit state or not, based on gate voltage E and its differential value D in the turn-on operation of power semiconductor element  101 . 
     In the case where power semiconductor element  101  is an IGBT, first reference value REF 1 , second reference value REF 2  and third reference value REF 3  can be set based on the relation between gate voltage V GE  and its differential value dV GE /dt as shown in  FIG. 3 . 
     Particularly, in the graph showing the relation between gate voltage V GE  and its differential value as shown in  FIG. 3 , reference values REF 1 , REF 2 , and REF 3  are set to be included in a region surrounded by a gate voltage-differential value curve in the normal state (corresponding to solid line k 1  in the figure) and a gate voltage-differential value curve in the arm short-circuit state (corresponding to dashed line k 2  in the figure). 
     Specifically,  FIG. 3  shows a trapezoidal region RGN 1  surrounded by the gate voltage-differential value curve in the normal state (solid line k 1 ) and the gate voltage-differential value curve in the arm short-circuit state (dashed line k 2 ). Reference values REF 1 , REF 2 , and REF 3  are set to be included in this region RGN 1 . In consideration of a detection error and the like, it is desirable that reference values REF 1 , REF 2 , and REF 3  each have a fixed margin with respect to the boundary of region RGN 1 . For example, first reference value REF 1  is set to be larger than a minimum value V m1  of Miller voltage V m  while second reference value REF 2  is set to be smaller than a maximum value V m2  of Miller voltage V m . Third reference value REF 3  is set to be larger than zero within region RGN 1 . 
     In this way, a region RGN 2  surrounded by reference values REF 1 , REF 2 , and REF 3  is set within region RGN 1 . In drive circuit  100 , when gate voltage V GE  and its differential value are included in this region RGN 2 , an output signal SS from short-circuit determination unit  110  is set at an “H” level. Thus, it can be determined that power semiconductor element  101  (IGBT) is in a short-circuit state. On the other hand, when gate voltage V GE  and its differential value are out of this region RGN 2 , output signal SS from short-circuit determination unit  110  is set at an “L” level. Thus, it can be determined that power semiconductor element  101  is in a normal state. 
     In contrast, in the case where power semiconductor element  101  is an SiC-MOSFET, first reference value REF 1 , second reference value REF 2  and third reference value REF 3  can be set based on the relation between gate voltage V GS  and its differential value dV GS /dt as shown in  FIG. 5 . 
     Particularly, in the graph showing the relation between gate voltage V GS  and its differential value as shown in  FIG. 5 , reference values REF 1 , REF 2 , and REF 3  are set to be included within a region surrounded by the gate voltage-differential value curve in the normal state (corresponding to solid line k 3  in the figure) and the gate voltage-differential value curve in the arm short-circuit state (corresponding to dashed line k 4  in the figure). 
     Specifically,  FIG. 5  shows a trapezoidal region RGN 3  surrounded by the gate voltage-differential value curve in the normal state (solid line k 3 ) and the gate voltage-differential value curve in the arm short-circuit state (dashed line k 4 ). Reference values REF 1 , REF 2 , and REF 3  are set to be included within this region RGN 3 . In consideration of a detection error and the like, it is desirable that reference values REF 1 , REF 2 , and REF 3  each have a fixed margin with respect to the boundary of region RGN 3 . For example, first reference value REF 1  is set to be larger than a Miller voltage V m11  while second reference value REF 2  is set to be smaller than a Miller voltage V m12 . Third reference value REF 3  is set to be larger than a positive value X 3  within region RGN 3 . 
     In this way, a region RGN 4  surrounded by reference values REF 1 , REF 2 , and REF 3  is set within region RGN 3 . In drive circuit  100 , when gate voltage V GS  and its differential value are included in this region RGN 4 , output signal SS from short-circuit determination unit  110  is set at an “H” level. Thus, it can be determined that power semiconductor element  101  (SiC-MOSFET) is in a short-circuit state. On the other hand, when gate voltage V GS  and its differential value are out of this region RGN 4 , output signal SS from short-circuit determination unit  110  is set at an “L” level. Thus, it can be determined that power semiconductor element  101  is in a normal state. 
       FIG. 6  is a flowchart for illustrating the process procedure of the operation of determining whether power semiconductor element  101  is in a short-circuit state or not. The flowchart in  FIG. 6  is executed by drive circuit  100  through hardware processing or software processing. 
     Referring to  FIG. 6 , in drive circuit  100 , first in step S 01 , gate voltage detection unit  103  receives a turn-on command from control command unit  102  and subsequently detects gate voltage E applied to gate terminal  101   g  of power semiconductor element  101 . 
     In step S 02 , differentiator  104  subjects gate voltage E detected by gate voltage detection unit  103  to time differentiation, to calculate differential value D. 
     First comparator  107  compares gate voltage E with each of first reference value REF 1  and second reference value REF 2 , and outputs a signal S 1  that shows a comparison result. Second comparator  109  compares differential value D with third reference value REF 3  and outputs a signal S 2  that shows a comparison result. Short-circuit determination unit  110  computes a logical product of signal S 1  output from first comparator  107  and signal S 2  output from second comparator  109 , thereby determining whether power semiconductor element  101  is in a short-circuit state or not. Then, short-circuit determination unit  110  outputs signal SS that shows the determination result to control command unit  102 . 
     When gate voltage E is higher than first reference value REF 1  and lower than second reference value REF 2  (determined as YES in S 03 ), and when differential value D is greater than third reference value REF 3  (determined as YES in S 04 ), short-circuit determination unit  110  determines in step S 04  that power semiconductor element  101  is in a short-circuit state, and then outputs signal SS at an “H” level. In step S 06 , short-circuit determination unit  110  holds signal SS at an “H” level. 
     Upon reception of signal SS at an “H” level from short-circuit determination unit  110 , control command unit  102  outputs a turn-off command to power semiconductor element  101  in order to cut off power semiconductor element  101  in step S 07 . 
     On the other hand, when gate voltage E is equal to or less than first reference value REF 1  or is equal to or greater than second reference value REF 2  (determined as NO in S 03 ), or when differential value D is equal to or less than third reference value REF 3  (determined as NO in S 04 ), short-circuit determination unit  110  determines in step S 08  that power semiconductor element  101  is in a normal state, and then, outputs signal SS at an “L” level. 
     As described above, according to drive circuit  100  in the first embodiment of the present invention, the short-circuit state of the power semiconductor element can be determined based on gate voltage E and its differential value D of the power semiconductor element in the turn-on operation. Accordingly, when only gate voltage E in the power semiconductor element is detected, the determination operation can be performed. Thus, the short-circuit state of the power semiconductor element can be detected in a simple configuration. 
     Furthermore, according to drive circuit  100  in the first embodiment, the determination operation can be performed during a time period until the gate voltage rises to a gate drive power supply voltage after reception of the turn-on operation command. Thus, the short-circuit state of the power semiconductor element can be speedily detected, so that the power semiconductor element can be protected. 
     Furthermore, in drive circuit  100  according to the first embodiment, reference values REF 1 , REF 2 , and REF 3  can be readily set also in the case where the power semiconductor element is an element having a gate voltage that is not constant in the Miller period in the same manner as with the SiC-MOSFET (see  FIG. 5 ). Thus, the short-circuit state of the power semiconductor element can be speedily detected in a simple configuration. 
     In addition, the power semiconductor element is not limited to a SiC-MOSFET, but the present invention is also applicable to a power semiconductor element formed of a wide band gap semiconductor material such as gallium nitride, gallium oxide, and diamond, for example. 
     Second Embodiment 
     In the configuration having been described in the first embodiment in which the short-circuit state of the power semiconductor element is determined based on the gate voltage and its differential value, it is important to detect a gate voltage with high accuracy in order to improve the determination accuracy. In the following second to fourth embodiments, an explanation will be given with regard to the configuration example of the gate voltage detection unit for detecting a gate voltage with high accuracy. 
       FIG. 7  is a diagram showing the configuration of a drive circuit  100 A for a power semiconductor element according to the second embodiment of the present invention. 
     Referring to  FIG. 7 , drive circuit  100 A according to the second embodiment is different from drive circuit  100  shown in  FIG. 1  in that it includes a gate voltage detection unit  402  in place of gate voltage detection unit  103 . Since the configurations of other portions in drive circuit  100 A are the same as those in drive circuit  100  in  FIG. 1 , the detailed description thereof will not be repeated. 
     Gate voltage detection unit  402  includes a current detector  403  and an integrator  404 . Current detector  403  detects a gate current ig that flows into gate terminal  101   g  of power semiconductor element  101 . Current detector  403  outputs a signal ig that shows the detected gate current. Integrator  404  subjects gate current ig detected by current detector  403  to time integration. 
     In this case, the relation represented by the following equation (1) is established between gate current ig that flows into gate terminal  101   g  of power semiconductor element  101  and gate voltage E that is applied to gate terminal  101   g . 
     
       
         
           
             
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   E 
                   = 
                   
                     
                       1 
                       C 
                     
                     ⁢ 
                     
                       ∫ 
                       
                           
                       
                       ⁢ 
                       
                         
                           ig 
                           ⁡ 
                           
                             ( 
                             t 
                             ) 
                           
                         
                         ⁢ 
                         dt 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     In this case, C represents a parasitic capacitance component that occurs between gate terminal  101   g  and emitter terminal  101   e  (that is, gate-emitter capacitance C GE ) of power semiconductor element  101 . 
     Using the above-mentioned equation (1), integrator  404  can calculate gate voltage E based on the integral value obtained by subjecting gate current ig to time integration. In addition, gate-emitter capacitance C GE  has a characteristic that depends on gate-emitter voltage V GE . Thus, as gate-emitter capacitance C GE  in the equation (1) is set at an arbitrary constant between the maximum value and the minimum value of the function of gate-emitter voltage V GE , gate voltage E can be calculated. Furthermore, by defining gate-emitter capacitance C GE  in the equation (1) as a function of gate-emitter voltage V GE , the accuracy of computing gate voltage E can be improved. 
     Gate voltage E computed by integrator  404  is output to first comparator  107  and differentiator  104 . Thus, in short-circuit determination unit  110 , the short-circuit state of power semiconductor element  101  is to be determined based on gate voltage E and its differential value D (=dE/dt). 
     As described above, according to drive circuit  100 A in the second embodiment of the present invention, gate voltage detection unit  402  detects gate voltage E based on the integral value that is obtained by subjecting gate current ig detected by current detector  403  to time integration. Thereby, gate voltage E can be detected with high accuracy. 
     Specifically, in the configuration in which gate voltage E is directly detected using a voltmeter, the voltage occurring in a parasitic inductance L included in power semiconductor element  101  is superimposed on the detection value of the voltmeter. This parasitic inductance is mainly an inductance component of the wire connected to emitter terminal  101   e  of power semiconductor element  101 . When a current variation occurs in parasitic inductance L, a voltage V represented by the following equation (2) is produced. 
     
       
         
           
             
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   V 
                   = 
                   
                     L 
                     ⁢ 
                     
                       di 
                       dt 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     In this case, di/dt represents a time differential of the current that flows through parasitic inductance L. 
     A voltmeter cannot be placed so as to bypass this parasitic inductance L. Accordingly, the voltmeter is to detect the voltage that is obtained by superimposing the voltage that occurs in parasitic inductance L on the gate voltage that is directly applied to gate terminal  101   g . Thus, the detection value of the voltmeter contains an error with respect to the gate voltage. 
     In contrast, in drive circuit  100 A according to the second embodiment, gate voltage E is detected using the integral value that is obtained by subjecting gate current ig flowing into gate-emitter capacitance C GE  to time integration. Thus, the above-mentioned error of the voltage caused by parasitic inductance L can be avoided, with the result that the accuracy of gate voltage E can be improved. Therefore, also when power semiconductor element  101  is switching-operated at high speed or is operated with a high current, gate voltage E can be detected with high accuracy. As a result, in the configuration in which the short-circuit state of power semiconductor element  101  is determined based on gate voltage E and its differential value D, the accuracy of determining the short-circuit state can be improved. 
     Third Embodiment 
       FIG. 8  is a diagram showing the configuration of a drive circuit  100 B for a power semiconductor element according to the third embodiment of the present invention. 
     Referring to  FIG. 8 , drive circuit  100 B according to the third embodiment is different from drive circuit  100  shown in  FIG. 1  in that it includes a gate voltage detection unit  502  in place of gate voltage detection unit  103 . Since the configurations of other portions in drive circuit  100 B are the same as those in drive circuit  100  in  FIG. 1 , the detailed description thereof will not be repeated. 
     Gate voltage detection unit  502  includes a voltage detector  5100 , a current detector  5201 , an integrator  5202 , and a gate voltage computing unit  5300 . 
     Voltage detector  5100  detects the gate voltage applied to gate terminal  101   g  of power semiconductor element  101 . A commonly used voltmeter can be used as voltage detector  5100 . Voltage detector  5100  outputs a signal E 1  that shows the detected gate voltage. 
     Current detector  5201  detects the gate current that flows into gate terminal  101   g  of power semiconductor element  101 . Current detector  5201  outputs a signal ig that shows the detected gate current. 
     Integrator  5202  subjects gate current ig detected by current detector  5201  to time integration. Using the above-mentioned equation (1), integrator  5202  calculates a gate voltage based on the integral value that is obtained by subjecting gate current ig to time integration. Integrator  5202  outputs a signal E 2  that shows the calculated gate voltage. By defining gate-emitter capacitance C GE  in the equation (1) as a function of gate-emitter voltage V GE , the accuracy of computing gate voltage E 2  can be improved. 
     Gate voltage computing unit  5300  performs computation using gate voltage E 1  detected by voltage detector  5100  and gate voltage E 2  calculated by integrator  5202 , to thereby calculate the gate voltage applied to gate terminal  101   g  of power semiconductor element  101 . Gate voltage computing unit  5300  outputs a signal E 3  that shows the calculated gate voltage. 
     Specifically, gate voltage computing unit  5300  computes the average value of gate voltage E 1  and gate voltage E 2  to thereby calculate gate voltage E 3 . Thereby, gate voltage detection unit  502  can output gate voltage E 3  having high accuracy. 
     Specifically, as described above, voltage detector  5100  (a voltmeter) is used to directly detect gate voltage E, which shows a detection value on which voltage V occurring in parasitic inductance L of power semiconductor element  101  (see the above-mentioned equation (2)) is superimposed. Therefore, gate voltage E 1  detected by voltage detector  5100  is to be higher than the gate voltage applied to gate terminal  101   g , and is to exhibit an excessively large error that is equivalent to voltage V occurring in parasitic inductance L. 
     On the other hand, in power semiconductor element  101 , gate current ig that flows into gate terminal  101   g  flows into gate-emitter capacitance C GE , so that gate-emitter capacitance C GE  is charged. In this case, the current with which gate-emitter capacitance C GE  is charged includes two types of currents including: a gate current ig that flows from gate terminal  101   g ; and a collector current ic that flows between collector terminal  101   c  and emitter terminal  101   e . However, current detector  5201  can detect gate current ig but cannot detect collector current ic. Accordingly, the detection value by current detector  5201  is smaller than the current with which gate-emitter capacitance C GE  is actually charged. As a result, gate voltage E 2  obtained by subjecting the detection value of gate current ig to time integration is smaller than the original gate voltage. In other words, gate voltage E 2  is to have an excessively small error equivalent to the charge voltage by collector current ic. 
     Thus, gate voltage computing unit  5300  computes the average value of gate voltage E 1  having an excessively large error and gate voltage E 2  having an excessively small error, thereby allowing the excessively large error and the excessively small error to substantially cancel out each other. Thereby, it becomes possible to obtain gate voltage E 3  having high accuracy, from which both the excessively large error and the excessively small error are reduced. 
     Gate voltage E 3  computed by gate voltage computing unit  5300  is output to first comparator  107  and differentiator  104 . Thus, in short-circuit determination unit  110 , the short-circuit state of power semiconductor element  101  is to be determined based on gate voltage E 3  and its differential value D (=dE 3 /dt). 
     In the process of computing the average value of gate voltage E 1  and gate voltage E 2  in gate voltage computing unit  5300 , gate voltage E 1  and gate voltage E 2  may be simply averaged or may be weight-averaged. Through weight-averaging, the weight applied to each of gate voltages E 1  and E 2  can be adjusted for each power semiconductor element. Thus, the accuracy of gate voltage E 3  can be further improved. 
     As described above, according to drive circuit  100 B in the third embodiment of the present invention, gate voltage E 1  detected by voltage detector  5100  and gate voltage E 2  calculated using the integral value of gate current ig detected by current detector  5201  are averaged to thereby calculate gate voltage E 3 , with the result that the gate voltage can be detected with high accuracy. Consequently, the accuracy of determining the short-circuit state can be improved in the configuration in which the short-circuit state of power semiconductor element  101  is determined based on gate voltage E 3  and its differential value D. 
     Fourth Embodiment 
       FIG. 9  is a diagram showing the configuration of a drive circuit  100 C for a power semiconductor element according to the fourth embodiment of the present invention. 
     Referring to  FIG. 9 , drive circuit  100 C according to the fourth embodiment is different from drive circuit  100  shown in  FIG. 1  in that it includes a gate voltage detection unit  602  in place of gate voltage detection unit  103 . Since the configurations of other portions in drive circuit  100 C are the same as those in drive circuit  100  in  FIG. 1 , the detailed description thereof will not be repeated. 
     Gate voltage detection unit  602  includes a voltage detector  6101 , a current detector  6201 , a voltage drop computing unit  6202 , a correction gate voltage computing unit  6102 , an integrator  6203 , and a gate voltage computing unit  6300 . 
     Voltage detector  6101  detects the gate voltage that is applied to gate terminal  101   g  of power semiconductor element  101 . A commonly used voltmeter can be used as voltage detector  6101 . Voltage detector  6101  outputs a signal E 1  that shows the detected gate voltage. 
     Current detector  6201  detects the gate current that flows into gate terminal  101   g  of power semiconductor element  101 . Current detector  6201  outputs a signal ig that shows the detected gate current. 
     Using detection value ig by current detector  6201 , voltage drop computing unit  6202  calculates the amount of voltage drop that occurs in a gate resistance  603 . Specifically, a resistance element referred to as a gate resistance may be connected to gate terminal  101   g  of power semiconductor element  101 . Thus, when gate current ig flows into gate terminal  101   g , a voltage drop occurs in gate resistance  603 . Assuming that this amount of voltage drop is defined as ΔE, and the resistance value of gate resistance  603  is defined as Rg, the amount of voltage drop ΔE is represented by ΔE=ig×Rg. Voltage drop computing unit  6202  outputs a signal ΔE that shows the calculated amount of voltage drop. Voltage drop computing unit  6202  corresponds to one example of the “first computing unit” in the present invention. 
     Correction gate voltage computing unit  6102  subtracts the amount of voltage drop ΔE from gate voltage E 1  detected by voltage detector  6101 , thereby calculating a gate voltage E 11  (E 11 =E 1 −ΔE). This gate voltage E 11  is equivalent to the gate voltage that is obtained by correcting the voltage drop in gate resistance  603 , and that is higher in accuracy than gate voltage E 1 . However, as having been described in the third embodiment, gate voltage E 11  has an excessively large error resulting from parasitic inductance L in power semiconductor element  101 . Correction gate voltage computing unit  6102  corresponds to one example of the “second computing unit” in the present invention. 
     Integrator  6203  subjects gate current ig detected by current detector  6201  to time integration. Using the above-mentioned equation (1), integrator  6203  calculates the gate voltage based on the integral value that is obtained by subjecting gate current ig to time integration. Integrator  6203  outputs a signal E 2  that shows the calculated gate voltage. As to gate-emitter capacitance C GE , by defining gate-emitter capacitance C GE  in the equation (1) as a function of gate-emitter voltage V GE , the accuracy of computing gate voltage E 2  can be improved. However, as having been described in the third embodiment, gate voltage E 2  has an excessively small error equivalent to the charge voltage by collector current ic. 
     Gate voltage computing unit  6300  performs computation using gate voltage E 11  calculated by correction gate voltage computing unit  6102  and gate voltage E 2  calculated by integrator  6203 , thereby calculating the gate voltage applied to gate terminal  101   g  of power semiconductor element  101 . Gate voltage computing unit  6300  outputs a signal E 3  that shows the calculated gate voltage. Gate voltage computing unit  6300  corresponds to one example of the “third computing unit” in the present invention. 
     Specifically, gate voltage computing unit  6300  has the same configuration as that of gate voltage computing unit  5300  in drive circuit  100 B shown in  FIG. 8 , and computes the average value of gate voltage E 11  and gate voltage E 2 , thereby calculating gate voltage E 3 . Thereby, the excessively large error included in gate voltage E 11  and the excessively small error included in gate voltage E 2  cancel out each other, so that gate voltage E 3  having high accuracy can be obtained. 
     Gate voltage E 3  computed by gate voltage computing unit  6300  is output to first comparator  107  and differentiator  104 . Thus, in short-circuit determination unit  110 , the short-circuit state of power semiconductor element  101  is to be determined based on gate voltage E 3  and its differential value D (=dE 3 /dt). 
     In the process of computing the average value of gate voltage E 11  and gate voltage E 2  in gate voltage computing unit  6300 , gate voltage E 11  and gate voltage E 2  may be simply averaged or may be weight-averaged. Through weight-averaging, the weight applied to each of gate voltages E 11  and E 2  can be adjusted for each power semiconductor element. Thus, the accuracy of gate voltage E 3  can be further improved. 
     As described above, according to drive circuit  100 C in the fourth embodiment of the present invention, the gate voltage is calculated by averaging: gate voltage E 11  detected by voltage detector  6101  and for which the amount of voltage drop ΔE resulting from the gate resistance is corrected; and gate voltage E 2  calculated using the integral value of gate current ig detected by current detector  6201 , with the result that the gate voltage can be detected with high accuracy. Consequently, the accuracy of determining the short-circuit state can be improved in the configuration in which the short-circuit state of power semiconductor element  101  is determined based on the gate voltage and its differential value. 
     It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the meaning and scope equivalent to the terms of the claims. 
     REFERENCE SIGNS LIST 
       101  power semiconductor element,  101   c  collector terminal,  101   e  emitter terminal,  101   g  gate terminal,  101   d  drain terminal,  101   s  source terminal,  100 ,  100 A to  100 C drive circuit,  102  control command unit,  103 ,  402 ,  502 ,  602  gate voltage detection unit,  104  differentiator,  105  first reference value generation circuit,  106  second reference value generation circuit,  107  first comparator,  108  third reference value generation circuit,  109  second comparator,  110  short-circuit determination unit,  403 ,  5201 ,  6201  current detector,  404 ,  5202 ,  6203  integrator,  603  gate resistance,  5100  voltage detector,  5300 ,  6300  gate voltage computing unit,  6101  voltage detector,  6202  voltage drop computing unit,  6102  correction gate voltage computing unit, REF 1  first reference value, REF 2  second reference value, REF 3  third reference value.