Patent Publication Number: US-4929854-A

Title: Clock circuit having a clocked output buffer

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a circuit which generates an internal clock signal used for outputting data to an external circuit through an output buffer. 
     Generally, data generated in a large scale integrated circuit device (hereafter simply referred to as an LSI device) such as a microcomputer is output to an external circuit through a built-in output buffer which is controlled by an internal clock signal generated in the LSI device. 
     Most of LSI devices such as a direct memory access controller have an internal clock generator, which generates internal clock signals from an external clock signal supplied thereto from an external device. The generated internal clock signals are used to define timing of operation in an internal logic circuit and input and output buffers which interface with external devices. Generally, internal clock generators generate two internal clock signals which do not overlap each other in view of timing. In order to generate the internal clock signals from the external clock signal, an internal clock generator includes a flip-flop and a delay line. Precision in timing of the internal clock signals depends on precision in the delay line. 
     Generally, one of the generated internal clock signals is used for defining operation timing of an output buffer. Therefore, the operation timing of the output buffer depends on precision in the delay line provided in the internal clock generator. It is noted that it is very difficult to form a stabilized delay line so as to always provide a fixed delay amount. In other words, actual delay lines have variations in electric characteristics. It follows that operation of the output buffer driven by the internal clock signal thus generated is unstable, and therefore the reliability thereof is not high. Additionally, with the above-mentioned structure, it is very difficult to obtain satisfactory alternating current characteristics (hereafter simply referred to as AC characteristics) with respect to signal transfer characteristics and the like. 
     SUMMARY OF THE INVENTION 
     It is therefore a general object of the present invention to provide a novel and useful semiconductor integrated circuit device in which the above-mentioned disadvantages are eliminated. 
     A more specific object of the present invention to provide a semiconductor integrated circuit device having an extremely stabilized output buffer by generating an internal clock signal by an improved internal clock generator. 
     The above objects of the present invention can be achieved by a semiconductor integrated circuit device comprising internal logic means for carrying out a logic operation and generating an output signal based on the logic operation; output buffer means, connected to the internal logic means, for outputting the output signal through an output terminal in synchronism with a clock signal; first means for generating a first internal clock signal which falls in synchronism with a falling edge of an external clock signal and for generating a second internal clock signal which falls in synchronism with a rising edge of the external clock signal, the internal logic means carrying out the logic operation in synchronism with the first and second internal clock signals; and second means, connected to the first means, for generating a third internal clock which rises in synchronism with the falling edge of the second internal clock signal and which falls in synchronism with the falling edge of the first internal clock signal, the third internal clock signal being supplied, as the clock signal, to the output buffer means. 
     The other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional output buffer provided in LSI devices; 
     FIG. 2 is a circuit diagram of a conventional internal clock generator; 
     FIG. 3 is a view illustrating waveforms of first and second internal clocks and an external clock; 
     FIG. 4 is a view illustrating problems encountered in the conventional output buffer shown in FIG. 1; 
     FIG. 5 is a circuit diagram of an essential part of a preferred embodiment of the present invention; 
     FIG. 6 is a view illustrating waveforms of signals observed in the embodiment of FIG. 5; 
     FIG. 7 is a schematic block diagram illustrating the entire structure of the embodiment; 
     FIG. 8 is a circuit diagram of a part of an output buffer block shown in FIG. 7; 
     FIG. 9 is a view illustrating waveforms of signals observed in the circuit of FIG. 8, compared with waveforms of signals observed in the conventional output buffer circuit controlled by an internal clock signal generated by the circuit of FIG. 2; 
     FIG. 10 is a variation of the configuration of FIG. 8; and 
     FIGS. 11A through 11C are views illustrating other variations of the configuration of FIG. 8. 
    
    
     DETAILED DESCRIPTION 
     A description is first given of a conventional output buffer and a conventional internal clock generator in order to facilitate the understanding of the present invention. 
     FIG. 1 illustrates an output buffer circuit BF formed on a semiconductor chip 100. The output buffer circuit BF includes a flip-flop 1, which connected to an internal logic circuit 105 and is made up of two AND gates 1a, 1b, and two NOR gates 1c, 1d. When an output set signal S SET  is applied to the flip-flop 1, it is set with a timing of the rising edge of a first internal clock signal φ 1  (or a second internal clock signal φ 2 ). Then, the flip-flop 1 drives an N-channel transistor 3b of an output buffer 3 through two inverters 2b and 2c connected in series. Thereby, an output terminal PO is set to a low level (hereafter simply referred to as &#34;L&#34; or &#34;L&#34; level). 
     On the other hand, when an output reset signal S RST  is applied to the flip-flop 1, it is reset with a timing of the rising edge of the first internal clock signal φ 1  (or the second internal clock signal φ 2 ). Then, the flip-flop 1 drives a P-channel transistor 3a of the output buffer 3 through the inverters 2b and 2c. Thereby, the output terminal PO is set to a high level (hereafter simply referred to as &#34;H&#34; or &#34;H&#34; level). 
     In this manner, the output set and reset signals S SET  and S RST  which are supplied to the flip-flop 1 with an arbitrary timing or a predetermined timing, are synchronized with the first internal clock signal φ 1  (or the second internal clock signal φ 2 ). Thereafter, the output set and reset signals S SET  and S RST  are output as output signals through the output terminal PO. In the case of FIG. 1, the output set and reset signals S SET  and S RST  are controlled with the same timing of the first internal clock signal φ 1  (or φ 2 ). In the alternative, it is possible to control the output set signal S SET  with the timing of the first internal clock signal φ 1  and control the output reset signal S RST  with the timing of the second internal clock signal φ 2 , or vice versa. 
     FIG. 2 illustrates a non-overlap internal clock generator (hereafter referred to as a non-overlap clock generator) 110. An external clock signal EXCP is applied to an NAND gate 5 through an external input terminal PI formed on the semiconductor chip 100. The external clock signal EXCP is also supplied to an NAND gate 7 through an inverter 6. An output signal of the NAND gate 5 is extracted as the aforementioned first internal clock signal φ 1  through inverters 8, 9 and 10. The output signal of the NAND gate 5 is also supplied to a first delay circuit 11 through the inverter 8. The delay circuit 11 has a function of delaying the output signal of the inverter 8 by a predetermined time Td1. The output signal of the delay circuit 11 is supplied to the NAND gate 7. On the other hand, an output signal of the NAND gate 7 is extracted as the aforementioned second clock signal φ 2  through inverters 12, 13 and 14. The output signal of the NAND gate 7 is also supplied to a second delay circuit 15 through the inverter 12. The second delay circuit 15 has a functions of the output signal of the inverter 12 by a predetermined time Td2. The output signal of the second delay circuit 15 is supplied to the NAND gate 5. 
     With the structure of FIG. 3, the rise (a) of the first internal clock signal φ 1  is delayed by the time Td2 from the rise (b) of the external clock signal EXCP, and the fall (c) of the first internal clock signal φ 1  is synchronized with the fall (d) of the external clock signal EXCP. On the other hand, the rise (e) of the second internal clock signal φ 2  is delayed by the time Td1 from the fall (d) of the external clock signal EXCP, and the fall (f) of the second internal clock signal φ 2  is synchronized with the rise (b&#39;) of the external clock signal EXCP. In the above description, delays resulting from the NAND gates 5 and 7, and the inverters 8 through 10, and 12 through 14 are neglected for convenience&#39;s sake. There is formed a non-overlap interval between the first and second internal clocks φ 1  and φ 2  due to the presence of the delays Td1 and Td2. 
     However, precision in determination of the output signal (corresponding to the output set signal S SET ) depends on precision in the delay time Td1 or Td2, because the output buffer circuit is synchronized with the first or second internal clock signal φ 1  or φ 2 , which is generated by use of the delay circuits 11 and 15. The above prevents an improvement in AC characteristics, particularly signal transfer characteristics. Additionally, it is not easy to design a system in case where the AC characteristics of devices determined based on the external clock are deteriorated. 
     The above is further described with reference to FIG. 4. Referring to FIG. 4, the output signal supplied from the internal logic circuit 105 is synchronized with the first internal clock signal φ 1  (or φ 2 ), and is output through the external terminal PO with the predetermined delay time depending on transfer characteristics of the inverters 2b, 2c and the output buffer 3. The rise of the first internal clock signal φ 1  is delayed by the delay time Td2 from the rise of the external clock signal EXCP (see FIG. 3). Therefore, if an error exists in characteristics of the second delay circuit 15, and the delay time Td2 is further delayed by a predetermined time Ta, the output signal is settled (determined) with a further delay due to the time Ta. As a result, AC characteristics of the output buffer circuit are deteriorated by the time Ta. It is conceivable to directly use the external clock signal EXCP in place of the first and second internal clock signals φ 1  and φ 2 . However, since the output set signal S SET  and output reset signal S RST  are generated by using the first and second internal clock signals φ 1  and φ 2 , there occurs the difference between the external clock signal EXCP and the internal clock signals φ 1  and φ 2 . Additionally, as the non-overlap period increases, the AC characteristics are deteriorated. Further, there is a possibility that the next internal clock signal is supplied to a logic circuit (not shown) used for generating the output set and reset signals S SET  and S RST , when conditions on determination of the signals S SET  and S RST  have not yet been determined due to a skew resulting from the number of logic elements which construct the logic circuit. In this time, if the external clock signal is supplied to the output buffer circuit, an error in operation occurs. Therefore, the direct use of the external clock signal is not appropriate in view of reliability of the output buffer circuit. 
     The present invention intends to overcome the above-mentioned disadvantages of the conventional art. 
     A description is given of a preferred embodiment of the present invention with reference to FIG. 5. FIG. 5 illustrates a third-internal-clock generator 20 (hereafter simply referred to as a third-clock generator), which generates a third internal clock signal φ F  from the aforementioned first and second internal clock signals φ 1  and φ 2 . The third-clock generator 20 includes inverters 21, 22, and 23, a P-channel MOS transistor (hereafter simply referred to as a PMOS transistor) Mp, an N-channel MOS transistor (hereafter simply referred to as an NMOS transistor) Mn, an OR gate 24, and a NAND gate 25. The inverter 21 inverts the first clock signal φ 1  and thereby generates an inverted first clock signal φ 1 . The PMOS transistor Mp conducts in an &#34;L&#34;-level interval of the inverted first clock signal φ 1  (corresponding to an &#34;H&#34;-level interval of the first clock signal φ 1 ). Two series-connected inverters 22 and 23 inverts the second internal clock signal φ 2  two times, and generates a clock signal φ 2  &#39;. The NMOS transistor Mn conducts in an &#34;H&#34;-level interval of the clock signal φ 2  &#39; (corresponding to an &#34;H&#34;-level interval of the second internal clock signal φ 2 ). The drains of the PMOS and NMOS transistors Mp and Mn are connected to the OR gate 24, to which the second internal clock signal φ 2  is supplied. The source of the PMOS transistor is connected to a positive power source V DD  and the source of the NMOS transistor Mn is connected to a negative power source V SS . The gate of the PMOS transistor Mp is connected to the NAND gate 25, which is also connected to the output of the OR gate 24. A composite gate 26 is constructed by the OR gate 24 and the NAND gate 25. 
     The PMOS transistor Mp charges a capacitive load C L  up to a voltage equal to V DD  -V TH ,P where V TH ,P is a threshold voltage of the PMOS transistor Mp, only when the PMOS transistor Mp conducts. On the other hand, only when the NMOS transistor Mn conducts, the capacitive load C L  is discharged down to almost the voltage V SS . The capacitive load C L  is a purely capacitive load such as input gate capacitance, stray capacitance and parasitic capacitance coupled to the OR gate 24. The composite gate 26 outputs a third internal clock signal φ F , when φ 1  =&#34;H&#34;, and φ 2  =&#34;H&#34; or V CL  =&#34;H&#34; where V CL  is the potential of the capacitive load C L . 
     A description is given of operation of the circuit of FIG. 5 with reference to FIG. 6. In the following description, it is assumed that a delay time occurring in each of the gates is zero for convenience&#39; sake. 
     At time t 0 , the first internal clock signal φ 1  is &#34;L&#34;, and the second internal clock signal φ 2   is &#34;H&#34;. Therefore, at this time, the PMOS Mp is OFF, and the NMOS transistor Mn is ON. Thereby, the capacitive load C L  is kept in the discharged state, and thus V CL  ≈V SS  (that is, V CL  =&#34;L&#34;). At this time, the composite gate 26 is supplied with the inverted first clock signal φ 1  held at &#34;H&#34; and the second internal clock signal φ 2  held at &#34;H&#34;. Therefore, the composite gate 26 outputs the third internal clock signal φ F  held at &#34;L&#34;. 
     At time t 1 , the second internal clock signal φ 2  is switched from &#34;H&#34; to &#34;L&#34;. The composite gate 26 is supplied with the inverted first clock signal φ 1  held at &#34;H&#34;, the potential signal V CL  held at &#34;L&#34;, and the second internal clock signal φ 2  switched to &#34;L&#34;. Therefore, the third internal clock signal φ F  derived from the composite gate 26 is switched from &#34;L&#34; to &#34;H&#34;. That is, the rising edge of the third internal clock signal φ F  is synchronized with the falling edge (&#34;H&#34; to &#34;L&#34;) of the second internal clock signal φ 2 . As described previously, the falling edges of the second internal clock signal φ 2  are generated in synchronism with the rising edges of the external clock signal EXCP without using the rising edges of the first and second internal clock signals φ 1  and φ 2 . Additionally, no specific delay circuit is used for generating the third internal clock signal φ F . For these reasons, it becomes possible to obtain, with high precision, the rising edges of the third internal clock signal φ F  occurring in synchronism with the falling edges of the second internal clock signal φ 2 . 
     At an interval between time t 1  and t 2 , during a time when φ 1  =&#34;L&#34;, and φ 2  =&#34;L&#34;, the PMOS transistor Mp is OFF, and the NMOS transistor Mn is OFF. Therefore, the composite gate 26 is supplied with the inverted first clock signal φ 1  held at &#34;H&#34;, the potential signal V CL  held at &#34;L&#34;, and the second internal clock signal φ 2  held at &#34;L&#34;. As a result, the composite gate 26 outputs the third internal clock signal held at &#34;H&#34;. When the first internal clock signal φ 1  is changed from &#34;L&#34; to &#34;H&#34; at time t 2 , the inverted first clock signal φ 1  is switched from &#34;H&#34; to &#34;L&#34;. Thereby, the PMCS transistor Mp is allowed to conduct. Then, the capacitive load C L  is charged up to approximately the potential V DD  so that V CL  =&#34;H&#34;. At this time, the inverted first clock signal φ 1  held at &#34;L&#34; is applied to the composite gate 26, which thus keeps the third internal clock signal at &#34;H&#34;. 
     At an interval between t 2  and t 3 , the third internal clock signal φ F  is kept at &#34;H&#34;, because the inverted first clock signal φ 1  is &#34;L&#34;. 
     At time t 3 , the first internal clock signal φ 1  is switched from &#34;H&#34; to &#34;L&#34;, and thereby the PMOS transistor Mp is turned OFF. At this time, since φ 2  =&#34;L&#34;, the NMOS transistor Mn is OFF, and the potential V CL  is kept at &#34;H&#34; level. Then, the composite gate 26 is supplied with the inverted first clock signal φ 1  held at &#34;H&#34; and the potential V CL  held at &#34;H&#34;. Therefore, the third internal clock signal φ F  is switched from &#34;H&#34; to &#34;L&#34;. That is, the falling edge of the third clock signal φ F  is synchronized with the falling edge of the first internal clock signal φ 1 . It is noted that the falling edges of the first internal clock signal φ 1  are generated in synchronism with the falling edges of the external clock signal EXCP without using the rising edges of the first and second internal clock signals φ 1  and φ 2 , and that no specific delay circuit is used for generating the third internal clock signal φ F . Therefore, the falling edges of the third internal clock φ F  depend on precision in the external clock signal EXCP. Thereby, it becomes possible to obtain the falling edge of the third internal clock signal φ F  occurring in synchronism with the falling edges of the first internal clock signal φ 1 . 
     At an interval between t 3  and t 4 , the second internal clock signal φ 2  is held at &#34;L&#34; level. Therefore, the NMOS transistor Mn is OFF. Thereby, the potential V CL  of the capacitive load is maintained at &#34;H&#34; level. During the time between t 3  and t 4 , since φ 1  =&#34;H&#34;, the third internal clock signal φ F  is kept &#34;L&#34;. 
     At an interval between time t 4  and t 0  &#39;, the second internal clock signal φ 2  is switched from &#34;L&#34; to &#34;H&#34;. Responsive to this level change, the NMOS transistor Mn is turned ON, and thereby the potential V CL  of the capacitive load C L  is switched to &#34;L&#34;. However, the second internal clock signal φ 2  held at &#34;H&#34; is supplied to the composite gate 26. Therefore, the third internal clock signal φ F  is maintained at &#34;L&#34;. Then the aforementioned operation which is made between time t 1  and time t 4 , is repetitively carried out. 
     In this manner, according to the aforementioned embodiment, the third internal clock signal φ F  is newly generated from the first and second internal clock signals φ 1  and φ 2 , which are used as timing signals in an internal logic circuit. Particularly, the rising and falling edges of the third internal clock φ F  are generated on the basis of falling edges of the external clock signal EXCP. As a result, precision in the third internal clock signal φ F  depends on precision in the external clock signal EXCP. Further, the third clock φ F  is hardly affected by unevenness of characteristics of devices occurring at the time of manufacturing LSI devices, since the third clock φ F  is defined by the fall of the clocks φ 1  &#39; and φ 2 . 
     FIG. 7 is a block diagram of an LSI device in which the third-clock generator 20 of FIG. 5 is formed. Referring to FIG. 7, on the semiconductor chip 100, there are formed the internal logic circuit 105, an output buffer block 120 including at least onc output buffer circuit BF as shown in FIG. 1), the non-overlap clock generator 110 and the third-clock generator 20. In FIG. 7, the output buffer block 120 and the third-clock generator 20 are separately depicted. However, it is also possible to form the third-clock generator 20 as a structural part of the output buffer block 120. 
     FIG. 8 illustrates a part of the output buffer block 120, together with the internal logic circuit 105 and the third-clock generator 20. In FIG. 8, those parts which are the same as those in FIG. 1 are given the same references. FIG. 9 is a timing chart illustrating operation of the circuit shown in FIG. 8, and illustrating operation of the conventional output buffer controlled by the internal clock signal φ 1  (or φ 2 ), for the purpose of comparison with the present embodiment. Signals indicated by (I) shown in FIG. 9 relate to the present embodiment, and signals indicated by (II) relate to the conventional art. In operation, it is now assumed that conditions for generating the output set signal S SET  are determined in an &#34;H&#34;-level interval of the second internal clock signal φ 2  (indicated by reference (p)). In view of AC characteristics, it is desired that the output signal extracted through the external terminal PO is determined immediately after the above-mentioned conditions for the output set signal S SET  are determined. In case where as in the case of the conventional art, the output buffer circuit BF is controlled in an &#34;H&#34;-level interval (o) of the first internal clock signal φ 1  which follows the interval (p) of the second internal clock signal φ 2 , the output signal is determined after a time T A  from the time when the above-mentioned conditions are determined. This is because there exists an non-overlap interval T A  between the first and second internal clock signals φ 1  and φ 2 . In the interval T A , both the first and second internal clock signals φ 1  and φ 2  are held at &#34;L&#34; level. The above deteriorates AC characteristics of the output buffer circuit BF. Additionally, since the rising edge of the first clock signal φ 1  depends on the delay circuit, it is liable to be affected by variations in characteristics of the delay circuit. If the delay is increased by time Ta, the output signal is determined with a timing of T A  +Ta. This leads to further deterioration of AC characteristics, particularly signal transfer characteristics. 
     On the other hand, in the case where the output buffer circuit BF is controlled by the third clock signal φ F , the output signal is determined immediately after the aforementioned conditions are determined. Therefore, AC characteristics obtained by the present invention can be improved by time T A  in the case where no delay occurs in the first internal clock signal φ 1 . Even if the first internal clock signal φ 1  is somewhat delayed, AC characteristics can be improved by Ta+T A . That is, the output signal is determined immediately after the conditions for generating the output set signal S SET  are determined in the interval (p) of the second internal clock signal φ 2 . As a result, it becomes possible to considerably improve AC characteristics of the output buffer circuit BF. 
     Actually, there are formed a plurality of output buffer circuits BF in the output buffer block 120. In such a case, the third-clock generator 20 may be provided for every predetermined number of output buffer circuits BFI through BFn, as shown in FIG. 10. Therefore, there are provided m×n output buffer circuits, m third-clock generators are provided. 
     FIGS. 11A through 11C illustrate variations of the embodiment of FIG. 8. In a variation of FIG. 11A, the third clock signal φ F  is supplied to the flip-flop 1 through an inverter INV1. In a variation of FIG. 11B, the third clock signal φ F  is directly supplied to the AND gate 1b of the flip-flop 1, and is supplied to the AND gate 1a thereof through an inverter INV2. In a variation of FIG. 11C, the third-clock signal φ F  is directly supplied to the AND gate 1a of the flip-flop 1, and is supplied to the AND gate 1b thereof through an inverter INV3. 
     The present invention is not limited to the above-mentioned embodiments, and variations and modifications may be made without departing from the scope of the present invention.