Patent Publication Number: US-11664375-B2

Title: Minimizing shorting between FinFET epitaxial regions

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This patent application is a continuation of and claims priority to U.S. patent application Ser. No. 16/296,433, filed Mar. 8, 2019, which is a continuation of U.S. patent application Ser. No. 15/923,097, filed Mar. 16, 2018, now U.S. Pat. No. 10,276,569, issued Apr. 30, 2019, which is a continuation of U.S. patent application Ser. No. 15/494,586, filed Apr. 24, 2017, now U.S. Pat. No. 9,985,024, issued May 29, 2018, which is a continuation of U.S. patent application Ser. No. 15/203,847, filed Jul. 7, 2016, now U.S. Pat. No. 9,704,753, issued Jul. 11, 2017, which is a divisional of U.S. patent application Ser. No. 14/680,099, filed Apr. 7, 2015, now U.S. Pat. No. 9,443,853, issued Sep. 13, 2016, which are fully incorporated herein by reference. 
    
    
     BACKGROUND 
     The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). 
     With recent advancement in semiconductor device manufacturing, and in particular with regard to FinFETs, epitaxially formed source/drain regions are increasingly becoming preferred to provide low resistance contacts to the FinFETs and other devices. Typically, a FinFET device will include one or more fins having a source epitaxy formed thereon separated, by a gate structure, from one or more fins having a drain epitaxy thereon. The gate structure of one FinFET device is typically separated from the gate structure of an adjacent FinFET device by a portion of an underlying substrate. However, as device size continues to shrink, problems may arise with shorting between small pitch structures. 
     SUMMARY 
     According to an embodiment, a method of physically separating epitaxial regions in fin field effect transistors (FinFETs) is disclosed. The method may include forming a dielectric region in a middle portion of a gate structure, wherein the gate structure is formed over a middle portion of a first fin group and a middle portion of a second fin group, and wherein the dielectric region is located in an intermediate region between the first set of fins and the second set of fins. 
     According to another embodiment, a method is disclosed. The method may include: forming a first fin group on a substrate; forming a second fin group on the substrate, the first fin group and the second fin group separated by an intermediate region of the substrate; forming a dummy gate layer on the first fin group, the second fin group, and the intermediate region; forming an opening in the dummy gate layer, the opening exposing an upper surface of the substrate in the intermediate region; forming a dielectric region in the opening; removing a portion of the dummy gate layer to form a dummy gate, wherein the dummy gate covers a middle portion of the first fin group and a middle portion of the second fin group; forming a spacer on an outer surface of the dummy gate; removing the dummy gate selective to the dielectric region; forming a gate on the first fin group, the intermediate region, and the second fin group, the gate surrounding the dielectric region and located within the spacer; forming one or more first epitaxial regions on the first fin group, the one or more first epitaxial regions separated from each other by the spacer, the gate, and the dielectric region; and forming one or more second epitaxial regions on the second fin group, the one or more second epitaxial regions separated from each other by the spacer, the gate, and the dielectric region, wherein the one or more first epitaxial regions are separated from the one or more second epitaxial regions by the spacer, the gate, the dielectric region, and a portion of the substrate in the intermediate region. 
     According to another embodiment, a structure is disclosed. The structure may include: a first fin group on a substrate; a second fin group on the substrate, the first fin group separated from the second fin group by an intermediate region of the substrate; a gate structure on a middle portion of the first fin group, a middle portion of the intermediate region, and a middle portion of the second fin group; a dielectric region in a middle portion of the gate structure, the dielectric region located in the intermediate region; one or more first epitaxial regions on the first fin group, the one or more first epitaxial regions separated from each other by the gate structure and the dielectric region; and one or more second epitaxial regions on the second fin group, the one or more second epitaxial regions separated from each other by the gate structure and the dielectric region, wherein the one or more first epitaxial regions are separated from the one or more second epitaxial regions by the gate structure, the dielectric region, and a portion of the substrate in the intermediate region. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which not all structures may be shown. 
         FIG.  1 A  is a top view and  FIG.  1 B  is a cross section view, both illustrating a preliminary structure including a substrate, according an embodiment of the present invention. 
         FIG.  2 A  is a top view and  FIG.  2 B  is a cross section view, both illustrating forming one or more fins on the substrate, according an embodiment of the present invention. 
         FIG.  3 A  is a top view and  FIG.  3 B  is a cross section view, both illustrating forming a dummy gate layer on the substrate and the fins, according an embodiment of the present invention. 
         FIG.  4 A  is a top view and  FIG.  4 B  is a cross section view, both illustrating forming an opening in the dummy gate layer, according an embodiment of the present invention. 
         FIG.  5 A  is a top view and  FIG.  5 B  is a cross section view, both illustrating forming a dielectric region in the opening, according an embodiment of the present invention. 
         FIG.  6 A  is a top view and  FIG.  6 B  is a cross section view, both illustrating removing a portion of the dummy gate layer to form a dummy gate, according an embodiment of the present invention. 
         FIG.  7 A  is a top view and  FIG.  7 B  is a cross section view, both illustrating forming epitaxial regions on the fins, according an embodiment of the present invention. 
         FIG.  8 A  is a top view and  FIG.  8 B  is a cross section view, both illustrating replacing the dummy gate with a gate to form a gate structure, according an embodiment of the present invention. 
         FIG.  9    is a cross section view illustrating the gate structure, according an embodiment of the present invention. 
     
    
    
     The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements. 
     DETAILED DESCRIPTION 
     Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. 
     For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. It will be understood that when an element such as a layer, region, or substrate is referred to as being “on”, “over”, “beneath”, “below”, or “under” another element, it may be present on or below the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on”, “directly over”, “directly beneath”, “directly below”, or “directly contacting” another element, there may be no intervening elements present. Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. 
     In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention. 
     The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” are used throughout the present application to denote the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of a semiconductor material with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material that is formed by an epitaxial deposition process has the same crystalline characteristics as the deposition surface on which it is formed. The temperature for epitaxial deposition typically ranges from 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. 
     The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxially regions in small pitch fin field effect transistors (FinFETs). As device size continues to scale down, especially below the 7 nm node, the close proximity of device structures may lead to problems caused by epitaxial overgrowth. In particular, in a device having multiple fins with a source epitaxy on one side of a gate structure and multiple fins with a drain epitaxy on the other side of the gate structure, shorting may occur if one or both of the source epitaxy and the drain epitaxy are overgrown. 
     In one scenario, excessive epitaxial growth on an outer portion of one side of a last fin may grow around the gate structure and encroach on epitaxial material grown on the other side of the gate structure. As the two different epitaxial regions encroach on one another around the gate structure, shorting may occur. In another scenario, excessive epitaxial growth from the last fin of one device may encroach on the epitaxial material of the last fin of an adjacent device, particularly when the devices are in close proximity to each other due to small pitches and tight groundrules. This encroachment may lead to the merging of epitaxial regions of two independent FinFETs, which may destroy the devices/circuit. Therefore, it may be desirable to form small pitch FinFET devices, especially those adjacent to one another, in such a way to minimize this epitaxial overgrowth and shorting. Embodiments by which a dielectric region may be formed in between adjacent gate structures to insulate the source epitaxy from the drain epitaxy are described below with reference to  FIGS.  1 A- 9   . 
     Referring now to  FIG.  1 A  and  FIG.  1 B , a top view and a cross section view along section line A-A′, respectively, illustrating a preliminary structure  100  are shown. In an embodiment, the structure  100  may include a substrate  102 . The substrate  102  may be composed of any semiconductor material including, but not limited to: Si, Ge, SiGe, SiC, SiGeC, GaAs, InAs, InP and all other III/V or II/VI compound semiconductors. The substrate  102  may also be a layered semiconductor such as Si/SiGe, a silicon-on-insulator (SOI), or a SiGe-on-insulator (SGOI). The substrate  102  may be doped, undoped or contain both doped and undoped regions therein. 
     Referring now to  FIG.  2 A  and  FIG.  2 B  a top view and a cross section view along section line A-A′, respectively, illustrating forming one or more fins  202  (hereinafter “fins”) on the substrate  102  is shown. The fins  202  may have a width ranging from approximately 4 nm to approximately 40 nm. The fins  202  may have a height ranging from approximately 5 nm to approximately 300 nm. The fins  202  may be separated from one another by a distance ranging from approximately 4 nm to approximately 100 nm. The fins  202  may be formed, for example, by removing material from the substrate  102  using a photolithography process followed by an anisotropic etching process such as reactive ion etching (RIE) or plasma etching. Other methods of forming fins known in the art may also be utilized, such as sidewall image transfer (SIT). 
     In an embodiment in which the substrate  102  is a bulk substrate, the material of the fins  202  may be the same as the substrate  102  and there may be no identifiable boundary between the fins  202  and the substrate  102 . Alternatively, the material of the fins  202  may be different from the substrate  102 . For example, the fins  202  may be made of silicon germanium, and the substrate  102  may comprise silicon. In an embodiment in which the substrate  102  is a SOI substrate, the fins  202  may be formed from a top semiconductor layer (not shown) separated from a base layer (not shown) by a buried insulator layer (not shown). The top semiconductor layer and the base layer may be made of the same or different semiconductor material. The buried insulator layer may have a thickness ranging from approximately 10 to approximately 500 nm. The buried insulating layer may be composed of an insulating material, such as, for example, silicon oxide, silicon nitride, oxynitride, high-k dielectric material, low-k dielectric material, or a combination of insulating materials. 
     In an embodiment, the fins  202  may be separated into two groups, a first fin group  204  and a second fin group  206 , which may be separated by a intermediate region  208 . In an embodiment, the intermediate region  208  may have a width W 208  ranging from approximately 40 nm to approximately 400 nm. The first fin group  204  may correspond to a subsequently formed first FinFET device, and the second fin group  206  may correspond to a subsequently formed second FinFET device. 
     Referring now to  FIG.  3 A  and  FIG.  3 B , a top view and a cross section view along section line A-A′, respectively, illustrating forming a dummy gate layer  302  on the substrate  102  and the fins  202  is shown. In an embodiment, the dummy gate layer  302  may be composed of a conventional dummy gate material, such as, for example, a dielectric material, or polysilicon that may or may not be doped. The dummy gate layer  302  may be formed using a conventional deposition process, such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), low-pressure vapor deposition (LPCVD), plasma enhanced vapor deposition (PECVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), plating, or sputtering. The dummy gate layer  302  may completely cover the fins  202 . In an embodiment, the dummy gate layer  302  may be planarized using a conventional planarization process, such as chemical mechanical planarization (CMP), such that an upper surface of the dummy gate layer  302  is substantially flush with an upper surface of the fins  202 . 
     Referring now to  FIG.  4 A  and  FIG.  4 B , a top view and a cross section view along section line A-A′, respectively, illustrating forming an opening  402  in a middle portion of the dummy gate layer  302  is shown. The opening may be formed in the intermediate region  208  ( FIG.  2 A ) between the first fin group  204  ( FIG.  2 A ) and the second fin group  206  ( FIG.  2 A ). The opening  402  may be formed by removing a portion of the dummy gate layer  302  using conventional patterning and etching techniques, such as, for example, reactive ion etching (RIE). The opening  402  may expose an upper surface of the substrate  102 . In an embodiment, the opening may have a width W 402  that is less than the width W 208  of the intermediate region  208 . 
     Referring now to  FIG.  5 A  and  FIG.  5 B , a top view and a cross section view along section line A-A′, respectively, illustrating forming a dielectric region  502  in the opening  402  ( FIG.  4 A ) is shown. In an embodiment, the dielectric region  502  may be composed of a dielectric material, such as, for example, an oxide, a nitride, or an oxynitride. The dielectric region  502  may be formed using a conventional deposition process, such as, for example, ALD, CVD, LPCVD, PECVD, PVD, MBD, PLD, LSMCD, plating, or sputtering. In an embodiment, a conventional planarization process, such as, for example, CMP, may be performed such that an upper surface of the dielectric region  502  is substantially flush with the upper surface of the dummy gate layer  302 . 
     Referring now to  FIG.  6 A  and  FIG.  6 B , a top view and a cross section view along section line A-A′, respectively, illustrating removing a portion of the dummy gate layer  302  to form a dummy gate  604  is shown. In an embodiment, the portion of the dummy gate layer  302  may be removed by conventional patterning and etching techniques, such as, for example, RIE. The dummy gate  604  may cover the fins  202  in the first fin group  204 , portions of the intermediate region  208  and the fins  202  in the second fin group  206 . The dummy gate  604  may have a first portion  606  covering the first fin group  204  and a second portion  608  covering the second fin group  206 . The first portion  606  may be separated, and electrically insulated, from the second portion  608  by the dielectric region  502 . In an embodiment, a spacer  602  may be formed on outer surfaces of the dummy gate  604  and outer surface of the dielectric region  502 . The spacer  602  may be formed using a conventional deposition process, such as, for example, ALD, CVD, LPCVD, PECVD, PVD, MBD, PLD, LSMCD, plating, or sputtering, and may then be etched so that only a portion remains on the outer surfaces of the dummy gate  604  and the dielectric region  502 , which may be in a middle portion of the dummy gate  604 . In an embodiment, the spacer  602  may be composed of an oxide, a nitride, or an oxynitride. 
     Referring now to  FIG.  7 A  and  FIG.  7 B , a top view and a cross section view along section line A-A′, respectively, illustrating forming epitaxial regions  702  on the fins  202  ( FIG.  6 A ) is shown. The epitaxial regions  702  may serve as source/drain regions for the first fin group  204  and the second fin group  206 . The epitaxial regions  702  may be composed of a semiconductor material such as, for example, Si, SiGe, Ge, Si:C, or a III-V compound semiconductor material such as InAs, InGaAs, or InP. In an embodiment in which the epitaxial regions  702  are composed of SiGe, the concentration of germanium may range from approximately 10% to approximately 99%, and preferably may range from approximately 15% to approximately 75%. The epitaxial regions  702  can be doped or undoped. 
     In an embodiment, the epitaxial growth process may include flowing a gaseous mixture of GeH 4  and SiH 4  (SiH 2 Cl 2 ) in an ambient hydrogen environment at a temperature ranging from approximately 500° C. to approximately 900° C., and under a pressure ranging from approximately 0.1 torr to approximately 100 torr. The epitaxial regions  702  may be in-situ doped, or implanted, with either a n-type or a p-type dopant. In an embodiment, the epitaxial regions  702  on the first fin group  204  may be separated into a source region having a first conductivity type on one side of the dummy gate  604  and the dielectric region  502  and a drain region having a second conductivity type on the opposite side of the dummy gate  604 . Likewise, the epitaxial regions  702  on the second fin group  206  may be separated into a source region having a first conductivity type on one side of the dummy gate  604  and the dielectric region  502  and a drain region having a second conductivity type on the opposite side of the dummy gate  604 . 
     Referring now to  FIG.  8 A  and  FIG.  8 B , a top view and a cross section view along section line A-A′, respectively, illustrating replacing the dummy gate  604  ( FIG.  7 A ) with a gate  802  to form a gate structure  804  is shown. In an embodiment, the dummy gate  604  may be removed selective to the spacer  602 , the fins  202  ( FIG.  6 A ), the substrate  102 , and the epitaxial regions  702  using a selective etching process, such as, for example a wet etch or RIE. After the dummy gate  604  is removed to create a recess (not shown), the gate  802  may be formed by depositing a conductive material in the recess. The gate  802  may be composed of one or more layers of conductive materials which may include, for example, polycrystalline silicon, or a conductive metal such as copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof. After the conductive material is deposited, a conventional planarization process, such as, for example, CMP, may be performed such that an upper surface of the  802  is substantially flush with an upper surface of the spacer  602 . Because of the location of the spacer  602  and the dielectric region  502  in a middle portion of the gate structure  804 , and their insulating properties, the epitaxial regions  702  may remain physically and electrically separated in the intermediate region  208 , preventing source-drain shorting in the first fin group  204  and the second fin group  206 . 
     Referring now to  FIG.  9   , a cross section view along section line B-B′ ( FIG.  8 A ) illustrating the gate structure  804  is shown. The gate structure  804  may include two portions of the gate  802  separated in the middle by the dielectric region  502 . Because of the location of the dielectric region  502 , and its insulating properties, the gate  802  formed on the first fin group  204  may be physically and electrically separated from the gate  802  formed on the second fin group  206 . This may allow for the formation of 2 adjacent devices using one fabrication process, and may prevent shorting between the adjacent devices during operation. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.