Patent Publication Number: US-6903537-B2

Title: Switching DC-to-DC converter with multiple output voltages

Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to a switching DC-to-DC converter and, More particularly, to a switching DC-to-DC converter provided with multiple power supply channels for supplying multiple output voltages, capable of improving transient noise caused by power switch transistors, in which the multiple power supply channels may all adopt voltage mode feedback control, or some of them adopt voltage mode feedback control and others adopt current mode feedback control. 
   2. Description of the Related Art 
   Typically, a switching DC-to-DC converter regulates a DC voltage source for supplying a DC output voltage with a desired voltage level by appropriately controlling a duty cycle of a power switch transistor. Where the DC output voltage is larger than the DC voltage source, the switching DC-to-DC converter is generally referred to as a boost converter or regulator. On the other hand, the switching DC-to-DC converter is generally referred to as a buck converter or regulator where the DC output voltage is smaller than the DC voltage source. In order to ensure the stability of the DC output voltage, the switching DC-to-DC converter is usually provided with a feedback circuit, which may be classified as either a voltage mode feedback or a current mode feedback. In regarding to the voltage mode feedback, the feedback circuit retrieves a certain ratio of the DC output voltage for generating a feedback signal. In regarding to the current mode feedback, the feedback circuit generates a feedback signal by using a current sense amplifier to detect an inductor current. Also, the current mode feedback circuit may further retrieve a certain ratio of the DC output voltage in order to perform slope compensation. 
   Many of today&#39;s electronic system products effectively perform systematic operations and provide desired results by combining a variety of functional modules. For example, a digital camera is made up of a liquid crystal display, a backlight module, an image sensor, a digital signal processor, and a memory, thereby achieving the display, capture, and storage of digital images. In this case, each of the liquid crystal display, backlight module, image sensor, digital signal processor, and memory needs a DC power supply for executing the respectively designated operation and function. Typically, the functional modules incorporated in one electronic system product adopt different DC power supplies, respectively. That is, they are designed to operate with different DC power supply voltages. Since the electronic system product usually has only one DC voltage source such as a battery, a plurality of switching DC-to-DC converters are necessary to provide a plurality of different DC output voltages. As a conventional practice, the plurality of switching DC-to-DC converters are integrally manufactured in a single semiconductor integrated circuit chip for avoiding unnecessary packaging and wiring processes, thereby achieving advantages of low cost and small size as well as reducing parasitic capacitances and inductances. In this case, the plurality of switching DC-to-DC converters are formed as multiple power supply channels of the single semiconductor integrated circuit chip, which are connected in parallel between a common DC voltage source and ground and have respective output terminals for providing a plurality of different DC output voltages. 
   FIG.  1 ( a ) is a circuit block diagram showing a conventional switching DC-to-DC converter  10  with multiple output voltages. Referring to FIG.  1 ( a ), the switching DC-to-DC converter  10  has four power supply channels  11 A to  11 D for converting a single DC voltage source V source , shown in FIG.  1 ( b ), into four DC output voltages V out1  to V out4 , respectively. The power supply channel  11 A includes a switching controller  12 A, a converting circuit  13 A provided with a power switch transistor  15 A, and a feedback circuit  14 A. The power switch transistor  15 A is driven by a pulse-width-modulated (PWM) control signal PWM 1  output from the switching controller  12 A. The PWM control signal PWM 1  uses its duty cycle to determine the voltage level converting relationship between the DC voltage source V source  and the DC output voltage V out1 . In other words, under a condition that the DC voltage source V source  is fixed, the voltage level of the DC output voltage V out1  can be manipulated by appropriately adjusting the duty cycle of the PWM control signal PWM 1 . In additional, the switching controller  12 A adjusts the duty cycle of the PWM control signal PWM 1  after receiving a feedback signal FB 1  generated by the feedback circuit  14 A in order to maintain the DC output voltage V out1  stable. 
   The power supply channel  11 B includes a switching controller  12 B, a converting circuit  13 B provided with a power switch transistor  15 B, and a feedback circuit  14 B. The power switch transistor  15 B is driven by a PWM control signal PWM 2  output from the switching controller  12 B. The PWM control signal PWM 2  uses its duty cycle to determine the voltage level converting relationship between the DC voltage source V source  and the DC output voltage V out2 . The switching controller  12 B adjusts the duty cycle of the PWM control signal PWM 2  after receiving a feedback signal FB 2  generated by the feedback circuit  14 B in order to maintain the DC output voltage V out2  stable. The power supply channel  11 C includes a switching controller  12 C, a converting circuit  13 C provided with a power switch transistor  15 C, and a feedback circuit  14 C. The power switch transistor  15 C is driven by a PWM control signal PWM 3  output from the switching controller  12 C. The PWM control signal PWM 3  uses its duty cycle to determine the voltage level converting relationship between the DC voltage source V source  and the DC output voltage V out3 . The switching controller  12 C adjusts the duty cycle of the PWM control signal PWM 3  after receiving a feedback signal FB 3  generated by the feedback circuit  14 C in order to maintain the DC output voltage V out3  stable. The power supply channel  11 D includes a switching controller  12 D, a converting circuit  13 D provided with a power switch transistor  15 D, and a feedback circuit  14 D. The power switch transistor  15 D. is driven by a PWM control signal PWM 4  output from the switching controller  12 D. The PWM control signal PWM 4  uses its duty cycle to determine the voltage level converting relationship between the DC voltage source V source  and the DC output voltage V out4 . The switching controller  12 D adjusts the duty cycle of the PWM control signal PWM 4  after receiving a feedback signal FB 4  generated by the feedback circuit  14 D in order to maintain the DC output voltage V out4  stable. 
   An oscillator  16  outputs a pulse signal PULSE 1  and a ramp signal RAMP 1  to the switching controller  12 A. Rising edges of the pulse signal PULSE 1  occur simultaneously with falling edges of the ramp signal RAMP 1 . The pulse signal PULSE 1  sets the switching controller  12 A to generate the rising edge of the PWM control signal PWM 1 , which is then used for turning on the power switch transistor  15 A. The ramp signal RAMP 1  and the feedback signal FB 1  determine the occurrence of the falling edge of the PWM control signal PWM 1 , which is then used for turning off the power switch transistor  15 A. The oscillator  16  further outputs a pulse signal PULSE 2  and a ramp signal RAMP 2  to the switching controller  12 B. Rising edges of the pulse signal PULSE 2  occur simultaneously with falling edges of the ramp signal RAMP 2 . The pulse signal PULSE 2  sets the switching controller  12 B to generate the rising edge of the PWM control signal PWM 2 , which is then used for turning on the power switch transistor  15 B. The ramp signal RAMP 2  and the feedback signal FB 2  determine the occurrence of the falling edge of the PWM control signal PWM 2 , which is then used for turning off the power switch transistor  15 B. The oscillator  16  still further outputs a pulse signal PULSE 3  and a ramp signal RAMP 3  to the switching controller  12 C. Rising edges of the pulse signal PULSE 3  occur simultaneously with falling edges of the ramp signal RAMP 3 . The pulse signal PULSE 3  sets the switching controller  12 C to generate the rising edge of the PWM control signal PWM 3 , which is then used for turning on the power switch transistor  15 C. The ramp signal RAMP 3  and the feedback signal FB 3  determine the occurrence of the falling edge of the PWM control signal PWM 3 , which is then used for turning off the power switch transistor  15 C. The oscillator  16  still further outputs a pulse signal PULSE 4  and a ramp signal RAMP 4  to the switching controller  12 D. Rising edges of the pulse signal PULSE 4  occur simultaneously with falling edges of the ramp signal RAMP 4 . The pulse signal PULSE 4  sets the switching controller  12 D to generate the rising edge of the PWM control signal PWM 4 , which is then used for turning on the power switch transistor  15 D. The ramp signal RAMP 4  and the feedback signal FB 4  determine the occurrence of the falling edge of the PWM control signal PWM 4 , which is then used for turning off the power switch transistor  15 D. 
   Referring to FIG.  1 ( b ), the power supply channels  11 A to  11 D are connected in parallel between the DC voltage source V source  and ground. More specifically, through bonding wires, the power supply channels  11 A to  11 D are connected in parallel between the DC voltage source V souce  and ground. As a result, a plurality of parasitic inductances L w  caused by the bonding wires exist between the DC voltage source V source  and the power supply channels  11 A to  11 D. Similarly, a plurality of parasitic inductances L w  caused by the bonding wires exist between the power supply channels  11 A to  11 D and ground. In the operation of the power supply channels  11 A to  11 D, the power switch transistors  15 A to  15 D of the converting circuits  13 A to  13 D are so periodically switched as to achieve the voltage converting functions. Due to the existence of the parasitic inductances L w , noise is caused by a transient spike generated each time when any of the power switch transistors  15 A to  15 D makes a switching transition. 
   FIG.  1 ( c ) is a waveform timing chart showing the pulse signals PULSE 1  to PULSE 4  and the ramp signals RAMP 1  to RAMP 4  generated by the conventional oscillator  16 . As shown in FIG.  1 ( c ), the pulse signals PULSE 1  to PULSE 4  are identical in waveform and in phase while the ramp signals RAMP 1  to RAMP 4  are identical in waveform and in phase. For this reason, what the oscillator  16  actually does is to generate a single pulse signal and a single ramp signal for simultaneously supplying to the switching controllers  12 A to  12 D of the power supply channels  11 A to  11 D. In the prior art, the oscillator  16  may have a simpler configuration with benefits of small size and low cost. However, the in-phase pulse signals PULSE 1  to PULSE 4  set the switching controllers  12 A to  12 D such simultaneously that the power switch transistors  15 A to  15 B then make switching transitions at the same time. As a result, the transient spikes caused by all of the power switch transistors  15 A to  15 B superpose together. Therefore, there is significantly large transient noise between the DC voltage source V source  and ground, deteriorating qualities of the DC outsource put voltages V out1  to V out4  and much likely damaging the power supply channels  11 A to  11 D. 
   SUMMARY OF INVENTION 
   In view of the above-mentioned problem, an object of the present invention is to provide a switching DC-to-DC converter with multiple output voltages, capable of preventing the transient spikes caused by the multiple power channels from superposing, thereby achieving an operation with relatively low noise. 
   Another object of the present invention is to provide a switching DC-to-DC converter with multiple output voltages, which achieves advantages of small size and low cost by using an oscillator with a simpler configuration. 
   According to one aspect of the present invention, a switching DC-to-DC converter includes a first power supply channel coupled between a DC voltage source and ground, for converting the DC voltage source to a first DC output voltage; a second power supply channel coupled between the DC voltage source and ground, for converting the DC voltage source to a second DC output voltage which is separate from the first DC output voltage; and an oscillator for outputting a first oscillating signal having a first period to the first power supply channel and for outputting a second oscillating signal having a second period to the second power supply channel. During each period of the first period the first oscillating signal presents a peak, a valley, a rising portion gradually increasing from the valley toward the peak, and a falling portion gradually decreasing from the peak toward the valley. At least one switching transition of the first power supply channel occurs during one selected from a group consisting of the rising portion and the falling portion. During each period of the second period the second oscillating signal presents an instantly transiting edge which simultaneously occurs with one selected from a group consisting of the peak and the valley. At least one switching transition of the second power supply channel simultaneously occurs with the instantly transiting edge. 
   Preferably, the first oscillating signal is a triangular wave signal. 
   Preferably, the second oscillating signal is a pulse wave signal which presents a rising edge, a pulse width, and a falling edge during each period of the second period. The instantly transiting edge of the second oscillating signal refers to the rising edge thereof. 
   Preferably, the oscillator further outputs a first auxiliary signal to the second power supply channel. The first auxiliary signal is a ramp wave signal presenting a rising portion and a falling edge such that the falling edge thereof simultaneously occurs with the instantly transiting edge of the second oscillating signal. 
   Preferably, the switching DC-to-DC converter further includes a third power supply channel coupled between the DC voltage source and ground, for converting the DC voltage source to a third DC output voltage which is separate from the first and second DC output voltages. The oscillator further outputs a third oscillating signal having a third period to the third power supply channel. During each period of the third period the third oscillating signal presents a peak, a valley, a rising portion gradually increasing from the valley toward the peak, and a falling portion gradually decreasing from the peak toward the valley. The peak of the third oscillating signal simultaneously occurs with the valley of the first oscillating signal while the valley of the third oscillating signal simultaneously occurs with the peak of the first oscillating signal. At least one switching transition of the third power supply channel occurs during one selected from a group consisting of the rising portion and the falling portion of the third oscillating signal. 
   Preferably, the third oscillating signal is a signal inverted from the first oscillating signal. 
   Preferably, the switching DC-to-DC converter further includes a fourth power supply channel coupled between the DC voltage source and ground, for converting the DC voltage source to a fourth DC output voltage which is separate from the first and second DC output voltages. The oscillator further outputs a fourth oscillating signal having a fourth period to the fourth power supply channel. During each period of the fourth period the fourth oscillating signal presents an instantly transiting edge which simultaneously occurs with one selected from a group consisting of the peak and the valley of the first oscillating signal. The instantly transiting edge of the fourth oscillating signal occurs after a predetermined delay with respect to the instantly transiting edge of the second oscillating signal. At least one switching transition of the fourth power supply channel simultaneously occurs with the instantly transiting edge of the fourth oscillating signal. 
   Preferably, the predetermined delay is a half of the second period. 
   Preferably, the fourth oscillating signal is a pulse wave signal which presents a rising edge, a pulse width, and a falling edge during each period of the fourth period. The instantly transiting edge of the fourth oscillating signal refers to the rising edge thereof. 
   Preferably, the oscillator further outputs a second auxiliary signal to the fourth power supply channel. The second auxiliary signal is a ramp wave signal presenting a rising portion and a falling edge such that the falling edge thereof simultaneously occurs with the instantly transiting edge of the fourth oscillating signal. 
   According to another aspect of the invention, aswitching DC-to-DC converter includes a plurality of power supply channels connected in parallel between a DC voltage source and ground; an oscillating signal generator; and an auxiliary signal generator. 
   The oscillating signal generator includes an oscillating output node coupled to a first power supply channel of the plurality of power supply channels; a peak comparator having a non-inverting terminal and an inverting terminal, the non-inverting terminal being coupled to a peak setting voltage and the inverting terminal being coupled to the oscillating output node; a valley comparator having an inverting terminal and a non-inverting terminal, the inverting terminal being coupled to a valley setting voltage and the non-inverting terminal being coupled to the oscillating output node; a latch having asetting input and a resetting input, the setting input being coupled to an output terminal of the peak comparator and the resetting input being coupled to an output terminal of the valley comparator; a first inverter having an input terminal coupled to a normal output of the latch; a first switching means controlled by the first inverter; a first current source for supplying a first current from the DC voltage source to the oscillating output node; a second current source, controlled by the first switching means, for flowing a second current from the oscillating output node to the ground; and a first output capacitor coupled between the oscillating output node and ground. 
   The auxiliary signal generator includes an auxiliary output node coupled to a second power supply channel of the plurality of power supply channels; a sample-and-hold amplifier, controlled by the oscillating signal generator, having a non-inverting terminal and an inverting terminal, the non-inverting terminal being coupled to a reference voltage and the inverting terminal being coupled to the auxiliary output node; a sample-and-hold capacitor coupled between an output terminal of the sample-and-hold amplifier and ground; a voltage-to-current converter having a voltage input terminal and a current output terminal, the voltage input terminal being coupled to the output terminal of the sample-and-hold amplifier and the current output terminal being coupled to the auxiliary output node; a second output capacitor coupled between the auxiliary output node and ground; and a second switching means controlled by the oscillating signal generator and coupled between the auxiliary output node and ground. 
   Preferably, the switching Dc-to-DC converter further includes a rising edge one shot generator having an input terminal coupled to the normal output of the latch, and a falling edge one shot generator having an input terminal coupled to the normal output of the latch. The sample-and-hold amplifier is controlled by one of the rising edge and the falling edge one shot generators while the second switching means is controlled by another of the rising edge and the falling edge one shot generators. 
   Preferably, the switching Dc-to-DC converter further includes a second inverter having an input terminal coupled to the resetting input of the latch, and a third inverter having an input terminal coupled to the settinginput of the latch. The sample-and-hold amplifier is controlled by one of the second and the third inverters while the second switching means is controlled by another of the second and the third inverters. 
   Preferably, the switching Dc-to-DC converter further includes an inverting means having an input terminal and an output terminal, the input terminal being coupled to the oscillating output node and the output terminal being coupled to a third power supply channel of the plurality of power supply channels. 
   According to still another aspect of the invention, an oscillator includes means for outputting a first oscillating signal having a first period, and means for outputting a second oscillating signal having a second period. During each period of the first period the first oscillating signal presents a peak, a valley, a rising portion gradually increasing from the valley toward the peak, and a falling portion gradually decreasing from the peak toward the valley. During each period of the second period the second oscillating signal presents an instantly transiting edge which simultaneously occurs with one selected from a group consisting of the peak and the valley. 
   Perferably, the oscillator further includes means for outputting a first auxiliary signal, which is a ramp wave signal presenting a rising portion and a falling edge such that the falling edge thereof simultaneously occurs with the instantly transiting edge of the second oscillating signal. 
   Preferably, the oscillator further includes means for outputting a third oscillating signal having a third period. During each period of the third period the third oscillating signal presents a peak, a valley, a rising portion gradually increasing from the valley toward the peak, and a falling portion gradually decreasing from the peak toward the valley. The peak of the third oscillating signal simultaneously occurs with the valley of the first oscillating signal while the valley of the third oscillating signal simultaneously occurs with the peak of the first oscillating signal. 
   Preferably, the oscillator further includes means for outputting a fourth oscillating signal having a fourth period. During each period of the fourth period the fourth oscillating signal presents an instantly transiting edge which simultaneously occurs with one selected from a group consisting of the peak and the valley of the first oscillating signal. The instantly transiting edge of the fourth oscillating signal occurs after a predetermined delay with respect to the instantly transiting edge of the second oscillating signal. 
   Preferably, the oscillator further includes means for outputting a second auxiliary signal, which is a ramp wave signal presenting a rising portion and a falling edge such that the falling edge thereof simultaneously occurs with the instantly transiting edge of the fourth oscillating signal. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following descriptions and accompanying drawings, wherein: 
     FIG.  1 ( a ) is a circuit block diagram showing a conventional switching DC-to-DC converter with multiple output voltages; 
     FIG.  1 ( b ) is a diagram showing parasitic inductances caused by bonding wires between a DC voltage source and ground; 
     FIG.  1 ( c ) is a waveform timing chart showing signals generated from a conventional oscillator; 
     FIG.  2 ( a ) is a circuit block diagram showing a switching DC-to-DC converter with multiple output voltages according to the present invention; 
     FIG.  2 ( b ) is a waveform timing chart showing signals output by a multi-phase multi-waveform synchronous oscillator according to the present invention; 
       FIG. 3  is a detailed circuit diagram showing multiple power supply channels according to the present invention; 
       FIG. 4  is a circuit block diagram showing a multi-phase multi-waveform synchronous oscillator according to the present invention; 
       FIG. 5  is a detailed circuit diagram showing a first example of a multi-phase multi-waveform synchronous oscillator according to the present invention1; and 
       FIG. 6  is a detailed circuit diagram showing a second example of a multi-phase multi-waveform synchronous oscillator according to the present invention. 
   

   DETAILED DESCRIPTION 
   The preferred embodiments according to the present invention will be described in detail with reference to the drawings. 
   For clear appreciation of features of the present invention, differences between the present invention and the prior art will be addressed before a detailed description of the preferred embodiments according to the present invention. A switching DC-to-DC converter with multiple output voltages according to the present invention is different from a multiphase or polyphase switching DC-to-DC converter disclosed in, for example, U.S. Pat. No. 5,959,441, U.S. Pat. No. 6,137,274, U.S. Pat. No. 6,144,194, and U.S. Pat. No. 6,246,222. More specifically, the prior art multiphase switching DC-to-DC converter is provided with only one output terminal for supplying a single regulated output voltage; however, the switching DC-to-DC converter according to the present invention is provided with a plurality of output terminals, which are separate from each other, for supplying a plurality of regulated output voltages. Furthermore, the prior art must work on balancing respective currents flowing through the plural power supply channels in order to prevent a harmful phenomenon called “hot channel effect.” However, in the switching DC-to-DC converter according to the present invention, a plurality of power supply channels separately supply a plurality of regulated output voltages. In addition, the prior art oscillator of the multiphase switching DC-to-DC converter is restricted to generation of identical pulse signals and identical ramp signals, which may be different in phase. However, in the switching DC-to-DC converter according to the present invention, an oscillator outputs a plurality of oscillating signals with different waveforms and phases to power supply channels operated independently. Moreover, each of the power supply channels in the prior art multiphase switching DC-to-DC converter must be configured in the same feedback control mode. However, in the switching DC-to-DC converter according to the present invention, each power supply channel is allowed to use a different feedback control mode. 
   A method of improving,transient noise of a switching DC-to-DC converter  20  with multiple output voltages according to the present invention will be described in detail with reference to FIGS.  2 ( a ) and  2 ( b ) and FIG.  3 . 
   FIG.  2 ( a ) is circuit block diagram showing a switching DC-to-DC converter  20  with multiple output voltages according to the present invention. For preventing the drawings from adverse complication and for promoting appreciation of features of the present invention, a switching DC-to-DC converter  20  with four output voltages V out1  to V out4  is shown in FIG.  2 ( a ) and other figures as one embodiment according to the present invention. It should be noted that the present invention is not limited to this embodiment, but may be applied to a switching DC-to-DC converter with any possible number of output voltages. Hereinafter will described in detail the differences of the switching DC-to-DC converter  20  according to the present invention from the prior art shown in FIG.  1 ( a ). 
   Referring to FIG.  2 ( a ), the switching DC-to-DC converter  20  is different from the conventional switching DC-to-DC converter  10  shown in FIG.  1 ( a ) in that the switching DC-to-DC converter  20  is provided with a multi-phase multi-waveform synchronous oscillator  26  for replacing the prior art oscillator  16 . More specifically, the multi-phase multi-waveform synchronous oscillator  26  may generate a plurality of synchronous signals with different phases and waveforms. In the embodiment shown in FIG.  2 ( a ), the multi-phase multi-waveform synchronous oscillator  26  outputs four synchronous oscillating signals TR 1 , TR 2 , PC 1 , and PC 2 , which are different in phase and in waveform, for delivering to switching controllers  22 A to  22 D of power supply channels  21 A to  21 D, respectively. In addition to the oscillating signal PC 1 , an auxiliary signal RM 1  is cooperatively input to the switching controller  22 C. In addition to the oscillating signal PC 2 , another auxiliary signal RM 2  is cooperatively input to the switching controller  22 D. Through the phase and waveform differences among the synchronous oscillating signals TR 1 , TR 2 , PC 1 , and PC 2 , the switching controllers  22 A to  22 D may cause power switch transistors  25 A to  25 D to make switching transitions at different times, thereby preventing the transient spikes from superposing together. 
   FIG.  2 ( b ) is a waveform timing chart showing the oscillating signals TR 1 , TR 2 , PC 1 , and PC 2  and the auxiliary signals RM 1  and RM 2 , for clearly explaining the phase relationships and waveform features among them. Referring to FIG.  2 ( b ), the oscillating signal TR 1  is a continuous triangular wave whose amplitude varies between a peak value V H  and a valley value V L . Similarly, the oscillating signal TR 2  is another continuous triangular wave whose amplitude also varies between the peak value V H  and the valley value V L . For describing the waveforms of the oscillating signals TR 1  and TR 2 , a term “peak” refers to a part of the waveform having an amplitude of the peak value V, a term “valley” refers to a part of the waveform having an amplitude of the valley value V L , a term “rising portion” refers to a part of the waveform having an amplitude gradually increasing from the valley value V L  toward the peak value V H , and a term “falling portion” refers to a part of the waveform having an amplitude gradually decreasing from the peak value V H  toward the valley value V L . The oscillating signals TR 1  and TR 2  have the same period but are 180 degrees out of phase with respect to each other such that the peak of the oscillating signal TR 1  is aligned in the time domain to the valley of the oscillating signal TR 2  while the valley of the oscillating signal TR 1  is aligned in the time domain to the peak of the oscillating signal TR 2 . As a result, the rising portions of the oscillating signals TR 1  and TR 2  are staggered in time without any overlapping. Similarly, the falling portions of the oscillating signals TR 1  and TR 2  are staggered in time without any overlapping. It should be noted that although the oscillating signals TR 1  and TR 2  shown in FIG.  2 ( b ) have the same peak value and the same valley value, the present invention is not limited to this embodiment and may be applied to another embodiment where the oscillating signals TR 1  and TR 2  have different peak values and different valley values. Moreover, although the oscillating signals TR 1  and TR 2  shown in FIG.  2 ( b ) are equilateral triangular waves, in which the duration of time that the rising portion is present is equal to that the falling portion is present, the present invention is not limited to this embodiment and may be applied to another embodiment where the oscillating signals TR 1  and TR 2  are non-equilateral triangular waves, in which the duration of time that the rising portion is present is different from that the falling portion is present. Moreover, although the rising portions of the oscillating signals TR 1  and TR 2  shown in FIG.  2 ( b ) are linearly increasing, the present invention is not limited to this embodiment and may be applied to another embodiment where the rising portions of the oscillating signals TR 1  and TR 2  are non-linearly increasing. Moreover, although the falling portions of the oscillating signals TR 1  and TR 2  shown in FIG.  2 ( b ) are linearly decreasing, the present invention is not limited to this embodiment and may be applied to another embodiment where the falling portions of the oscillating signals TR 1  and TR 2  are nonlinearly decreasing. 
   The oscillating signal PC 1  is a pulse signal, in which each pulse presents a rising edge instantly transiting from LOW to HIGH, a pulse width staying at HIGH, and a falling edge instantly transiting from HIGH to LOW. The auxiliary signal RM 1  is a continuous ramp wave presenting, in each period, a rising portion gradually increasing from 0 to a maximum V max  and a falling edge instantly transiting from the maximum V max  to 0. The rising edge of the oscillating signal PC 1  simultaneously occurs with the falling edge of the auxiliary signal RM 1 . The oscillating signal PC 2  is a pulse signal, in which each pulse presents a rising edge instantly transiting from LOW to HIGH, a pulse width staying at HIGH, and a falling edge instantly transiting from HIGH to LOW. The auxiliary signal RM 2  is a continuous ramp wave presenting, in each period, a rising portion gradually increasing from 0 to a maximum V max  and a falling edge instantly transiting from the maximum V max  to 0. The rising edge of the oscillating signal PC 2  simultaneously occurs with the falling edge of the auxiliary signal RM 2 . In addition, as shown in FIG.  2 ( b ), the oscillating signals PC 1  and PC 2  have the same period but are 180 degrees out of phase with respect to each other. It should be noted that although the oscillating signals PC 1  and PC 2  shown in FIG.  2 ( b ) have the same maximum V max , the present invention is not limited to this embodiment and may be applied to another embodiment where the oscillating signal PC 1  has a different maximum from the oscillating signal PC 2 . 
   In the embodiment shown in FIG.  2 ( b ), the peak value V H  is approximately 0.8 volts while the valley value V L  is approximately 0.3 volts. The oscillating signals TR 1 , TR 2 , PC 1 , and PC 2  and the auxiliary signals RM 1  and RM 2  all have the same period of 1 microsecond. The pulse width of each of the oscillating signals PC 1  and PC 2  is approximately 100 nanoseconds. The binary state HIGH is approximately 2.2 volts while the binary state LOW is approximately 0 volt. The maximum V max  of each of the auxiliary signals RM 1  and RM 2  is approximately 0.8 volts. 
   As clearly seen from FIG.  2 ( b ), the valley of the oscillating signal TR 1 , the peak of the oscillating signal TR 2 , the rising edge of the oscillating signal PC 1 , and the falling edge of the auxiliary signal RM 1  simultaneously occur with respect to each other. Furthermore, the peak of the oscillating signal TR 1 , the valley of the oscillating signal TR 2 , the rising edge of the oscillating signal PC 2 , and the falling edge of the auxiliary signal RM 2  simultaneously occur with respect to each other. 
     FIG. 3  is adetailed circuit diagram showing multiple power supply channels  21 A to  21 D according to the present: invention. Referring to  FIG. 3 , the power supply channel  21 A adopts voltage mode feedback control and converts a DC voltage source V source  to a DC output voltage V out1  in response to the oscillating signal TR 1 . The power supply channel  21 A includes a switching controller  22 A, a converting circuit  23 A, and a feedback circuit  24 A. The converting circuit  23 A is a buck type converting circuit, having a power switch transistor  25 A, an inductor L 1 , a capacitor C 1 , and a diode D 1 , coupled together as shown. The feedback circuit  24 A is a voltage divider consisting of resistors Ra 1  and Rb 1  for providing a feedback signal FB 1  indicative of the DC output voltage V out1 . An error amplifier EA 1  of the switching controller  22 A compares the feedback signal FB 1  with a reference voltage V ref1 . Thereafter, a PWM comparator PA 1  outputs to a driver DR 1  a resultant signal of the oscillating signal TR 1  compared with an error voltage output from the error amplifier EA 1 , such that the driver DR 1  generates a PWM control signal PWM 1  for driving the power switch transistor  25 A implemented by an NMOS transistor Q 1 . More specifically, at the moment when the amplitude of the oscillating signal TR 1  becomes equal to the error voltage due to its gradual decrease from the peak value V H , the PWM control signal PWM 1  output from the driver DR 1  is rendered enable, i.e. HIGH in this embodiment, under the control of the PWM comparator PA 1 , thereby turning on the NMOS transistor Q 1 . Subsequently, the PWM control signal PWM 1  output from the driver DR 1  is rendered disable, i.e. LOW in this embodiment, under the control of the PWM comparator PA 1  at the moment when the amplitude of the oscillating signal TR 1  becomes equal to the error voltage due to its gradual increase from the valley value V L , thereby turning off the NMOS transistor Q 1 . 
   The power supply channel  21 B adopts voltage mode feedback control and converts the DC voltage source V source  to a DC output voltage V out2  in response to the oscillating signal TR 2 . The power supply channel  21 B includes a switching controller  22 B, a converting circuit  23 B, and a feedback circuit  24 B. The converting circuit  23 B is a buck type converting circuit, having a power switch transistor  25 B, an inductor L 2 , a capacitor C 2 , and a diode D 2 , coupled together as shown. The feedback circuit  24 B is a voltage divider consisting of resistors Ra 2  and Rb 2  for providing a feedback signal FB 2  indicative of the DC output voltage V out2 . An error amplifier EA 2  of the switching controller  22 B compares the feedback signal FB 2  with a reference voltage V ref2 . Thereafter, a PWM comparator PA 2  outputs to a driver DR 2  a resultant signal of the oscillating signal TR 2  compared with an error voltage output from the error amplifier EA 2 , such that the driver DR 2  generates a PWM control signal PWM 2  for driving the power switch transistor  25 B implemented by an NMOS transistor Q 2 . More specifically, at the moment when the amplitude of the oscillating signal TR 2  becomes equal to the error voltage due to its gradual decrease from the peak value V H , the PWM control signal PWM 2  output from the driver DR 2  is rendered enable, i.e. HIGH in this embodiment, under the control of the PWM comparator PA 2 , thereby turning on the NMOS transistor Q 2 . Subsequently, the PWM control signal PWM 2  output from the driver DR 2  is rendered disable, i.e. LOW in this embodiment, under the control of the PWM comparator PA 2  at the moment when the amplitude of the oscillating signal TR 2  becomes equal to the error voltage due to its gradual increase from the valley value V L , thereby turning off the NMOS transistor Q 2 . 
   The power supply channel  21 C adopts voltage mode feedback control and converts the DC voltage source V source  to a DC output voltage V out3  in response to the oscillating signal PC 1  and the auxiliary signal RM 1 . The power supply channel  21 C includes a switching controller  22 C, a converting circuit  23 C, and a feedback circuit  24 C. The converting circuit  23 C is a buck type converting circuit, having a power switch transistor  25 C, an inductor L 3 , a capacitor C 3 , and a diode D 3 , coupled together as shown. The feedback circuit  24 C is a voltage divider consisting of resistors Ra 3  and Rb 3  for providing a feedback signal FB 3  indicative of the DC output voltage V out3 . An error amplifier EA 3  of the switching controller  22 C compares the feedback signal FB 3  with a reference voltage V ref3  and then outputs an error voltage to a PWM comparator PA 3 . More specifically, the oscillating signal PC 1  sets a latch LA 1  to render the PWM control signal PWM 3  output from the driver DR 3  enable, i.e. HIGH in this embodiment, for turning on the power switch transistor  25 C implemented by an NMOS transistor Q 3 . On the other hand, the falling edge of the auxiliary signal RM 1  occurs at the same time as the turn-on of the NMOS transistor Q 3  since the falling edge of the auxiliary signal RM 1  simultaneously occurs with the rising edge of the oscillating signal PC 1 . Subsequently, the PWM comparator PA 3  resets the latch LA 1  at the moment when the rising portion of the auxiliary signal RM 1  gradually increases to become equal to the error voltage, such that the PWM control signal PWM 3  output from the driver DR 3  is rendered disable, i.e. LOW in this embodiment, thereby turning off the NMOS transistor Q 3 . 
   The power supply channel  21 D adopts current mode feedback control and converts the DC voltage source V source  to a DC output voltage V out4  in response to the oscillating signal PC 2  and the auxiliary signal RM 2 . The power supply channel  21 D includes a switching controller  22 D, a converting circuit  23 D, and a feedback circuit  24 D. The converting circuit  23 D is a buck type converting circuit, having a power switch transistor  25 D, an inductor L 4 , a series resistor Rs, a capacitor C 4 , and a diode D 4 , coupled together as shown. The feedback circuit  24 D includes a current sense amplifier CA for providing a feedback signal FB 4  indicative of a voltage difference caused by an inductor current flowing through the series resistor Rs. In order to perform the slope compensation of the current mode feedback control, the feedback circuit  24 D may further include a voltage divider consisting of resistors Ra 4  and Rb 4  for providing a signal indicative of the DC output voltage V out4 . An error amplifier EA 4  compares the signal indicative of the DC output voltage V out4  with a reference voltage V ref4  and then outputs an error voltage. Through an analog operational circuit AD, the error voltage minus the auxiliary signal RM 2  is input to an inverting terminal of a PWM comparator PA 4 . The feedback signal FB 4  is input to a non-inverting terminal of the PWM comparator PA 4 . The oscillating signal PC 2  sets a latch LA 2  to render the PWM control signal PWM 4  output from the driver DR 4  enable, i.e. HIGH in this embodiment, for turning on the power switch transistor  25 D implemented by an NMOS transistor Q 4 . Since the falling edge of the auxiliary signal RM 2  simultaneously occurs with the rising edge of the oscillating signal PC 2 , the falling edge of the auxiliary signal RM 2  occurs at the same time as the turn-on of the NMOS transistor Q 4 . During the duration that the NMOS transistor Q 4  is on, i.e. conductive, the inductor current flowing through the inductor L 4  linearly increases, resulting in a linear increase of the feedback signal FB 4  output from the current sense amplifier CA. When the feedback signal FB 4  becomes equal to the voltage output from the analog operational circuit AD, the PWM comparator PA 4  resets the latch LA 2  to render the PWM control signal PWM 4  output from the driver DR 4  disable, i.e. LOW in this embodiment, thereby turning off the NMOS transistor Q 4 . 
   As clearly understood from the descriptions above, the power switch transistor  25 A makes a transition from off to on during the falling portion of the oscillating signal TR 1  while the power switch transistor  25 B makes a transition from off to on during the falling portion of the oscillating signal TR 2 . Since the falling portions of the oscillating signals TR 1  and TR 2  are staggered in time, as shown in FIG.  2 ( b ), the power switch transistors  25 A and  25 B are effectively prevented from simultaneously transiting from off to on. As a result, the transient spikes caused by the power switch transistors  25 A and  25 B do not superpose together. 
   On the other hand, the power switch transistor  25 C makes a transition from off to on simultaneously with the rising edge of the oscillating signal PC 1  while the power switch transistor  25 D makes a transition from off to on simultaneously with the rising edge of the oscillating signal PC 2 . Since the rising edges of the oscillating signals PC 1  and PC 2  are staggered in time, as shown in FIG.  2 ( b ), the power switch transistors  25 C and  25 D are effectively prevented from simultaneously transiting from off to on. As a result, the transient spikes caused by the power switch transistors  25 C and  25 D do not superpose together. 
   In addition, as clearly seen from FIG.  2 ( b ), the rising edge of the oscillating signal PC 1  locates in the time domain outside of the respective falling portions of the oscillating signals TR 1  and TR 2  since the rising edge of the oscillating signal PC 1  simultaneously occurs with the valley of the oscillating signal TR 1  and the peak of the oscillating signal TR 2 . As a result, the power switch transistor  25 C transits from off to on at a different time from when the power switch transistors  25 A and  25 B respectively do. Similarly, the rising edge of the oscillating signal PC 2  locates in the time domain outside of the respective falling portions of the oscillating signals TR 1  and TR 2  since the rising edge of the oscillating signal PC 2  simultaneously occurs with the peak of the oscillating signal TR 1  and the valley of the oscillating signal TR 2 . As a result, the power switch transistor  25 D transits from off to on at a different time from when the power switch transistors  25 A and  25 B respectively do. Therefore, in the switching DC-to-DC converter  20  according to the present invention, the transient spikes caused by the power switch transistors  25 A to  25 D are effectively prevented from superposing together. 
   It should be noted that although, in the embodiment shown in  FIG. 3 , the power supply channels  21 A to  21 C belong to the voltage mode feedback control and the power supply channel  21 D belongs to the current mode feedback control, the present invention is not limited to this embodiment and may be applied to another embodiment where all of the power supply channels  21 A to  21 D belong to the voltage mode feedback control or still another embodiment where the power supply channels  21 A and  21 B belong to the voltage mode feedback control while the power supply channels  21 C and  21 D belong to the current mode feedback control. 
   It should be noted that although, in the embodiment shown in  FIG. 3 , the power switch transistors  25 A to  25 D transit from off to on at different times with respect to each other, the present invention is not limited to this embodiment and may be applied to another embodiment where the power switch transistors  25 A to  25 D transit from on to off at different times with respect to each other. In other words, the power switch transistors  25 A to  25 D according to the present invention may make at least one switching transition at different times with respect to each other regardless of from off to on and from on to off. 
     FIG. 4  is a circuit block diagram showing a multi-phase multi-waveform synchronous oscillator  26  according to the present invention. Referring to  FIG. 4 , the multi-phase multi-waveform synchronous oscillator  26  includes an oscillating signal generator  41 , an inverter  42 , and an auxiliary signal generator  43 . More specifically, the oscillating signal  41  generates the oscillating signal TR 1 . Thereafter, the oscillating signal TR 2  is obtained from inverting the oscillating signal TR 1  through the inverter  42 . As a result, the oscillating signals TR 1  and TR 2  are 180 degrees out of phase with respect to each other. In addition to the oscillating signal TR 1 , the oscillating signal generator  41  further generates the oscillating signals PC 1  and PC 2 , which are 180 degrees out of phase with respect to each other. Finally, the auxiliary signal generator  43  outputs the auxiliary signals RM 1  and RM 2  in response to the oscillating signals PC 1  and PC 2 . Hereinafter are omitted the waveform features of the oscillating signals TR 1 , TR 2 , PC 1 , and PC 2  and the auxiliary signals RM 1  and RM 2  since they have been described in detail before. 
     FIG. 5  is a detailed circuit diagram showing a first example of the multi-phase multi-waveform synchronous oscillator  26  according to the present invention. Referring to  FIG. 5 , the oscillating signal generator  41  includes a peak comparator  411 , a valley comparator  412 , a latch  413 , three inverters  414 ,  419 S, and  419 R, a switching means  415 , a first current source  416 , a second current source  417 , and a capacitor  418 . A non-inverting terminal of the peak comparator  411 , designated by a symbol “+,” is coupled to a peak setting voltage V H  while an inverting terminal of the valley comparator  412 , designated by a symbol “−,” is coupled to a valley setting voltage V L . An inverting terminal of the peak comparator  411  and a noninverting terminal of the valley comparator  412  are coupled together and further to an output node N TR1 . An output terminal of the peak comparator  411  is coupled to a setting input S of the latch  413  while an output terminal of the valley comparator  412  is coupled to a resetting input R of the latch  413 . The first current source  416  is connected between the DC voltage source V source  and the output node N TR1  while the second current source  417  is connected between the output node N TR1  and ground through the switching means  415 . In the embodiment shown in  FIG. 5 , the second current source  417  supplies a current, which is twice in magnitude than that supplied by the first current source  416 . In this case, the oscillating signal generator  41  generates an equilateral triangular wave whose rising portion lasts the same length of time as its failing portion does. It should be noted that the present invention is not limited to this embodiment and may be applied to any case under a condition that the second current source  417  supplies a current larger in magnitude than that supplied by the first current source  416 , as described in more detail later. That is, the oscillating signal generator  41  according to the present invention may generate a non-equilateral triangular wave whose rising portion lasts a different length of time from that the falling portion does. The switching means  415  is controlled by one of the output signals from the latch  413 . In the embodiment shown in  FIG. 5 , the switching means  415  is controlled by a normal output Q of the latch  413  through the inverter  414 . It should be noted that in another embodiment of the present invention the switching means  415  may be directly coupled to an inverted output {overscore (Q)} of the latch  413  and causes no variations to the desired control effect since the inverted output {overscore (Q)} is essentially an inverted signal of the normal output Q. In the present invention, the switching means  415  may be implemented by a switch transistor such as an NMOS transistor, a PMOS transistor, or a bipolar transistor. The capacitor  418  connected between the output node N TR1  and ground. 
   Hereinafter will be described in detail how the oscillating signal generator  41  generates the oscillating signal TR 1  and the auxiliary signals PC 1  and PC 2  with reference to FIG.  5  and FIG.  2 ( b ). When the voltage at the output node N TR1  is lower than the valley setting voltage V L , the setting input S is HIGH and the resetting input R is LOW, resulting in that the normal output Q is HIGH. At this moment, the inverter  414  outputs a LOW to the switching means  415  to turn it off. As a result, the second current source  417  is rendered non-conductive while the first current source  416  charges the capacitor  418  and causes the voltage at the output node N TR1  to increase. When the voltage at the output node N TR1  increases to become higher than the valley setting voltage V L  but still lower than the peak setting voltage V H , the setting input S is HIGH and the resetting input R is HIGH, resulting in that the normal output Q is HIGH. At this moment, the inverter  414  outputs a LOW to the switching means  415  to turn it off. As a result, the second current source  417  still stays non-conductive while the first current source  416  still charges the capacitor  418  and causes the voltage at the output node N TR1  to continuously increase. When the voltage at the output node N TR1  increases to become higher than the peak setting voltage V H , the setting input S is LOW and the resetting input R is HIGH, resulting in that the normal output Q is LOW. At this moment, the inverter  414  outputs a HIGH to the switching means  415  to turn it on. As a result, the second current source  417  is rendered conductive. Because the current supplied by the second current source  417  is larger in magnitude than that supplied by the first current source  416 , the capacitor  418  discharges to the ground through the second current source  417  such that the voltage at the output node N TR1  decreases. When the voltage at the output node N TR1  decreases to become lower than the peak setting voltage V H  but still higher than the valley setting voltage V L  the setting input S is HIGH and the resetting input R is HIGH, resulting in that the normal output Q is LOW. At this moment, the inverter  414  outputs a HIGH to the switching means  415  to turn it on. As a result, the second current source  417  still stays conductive and the capacitor  418  still discharges to the ground through the second current source  417  such that the voltage at the output node N TR1  continuously decreases. In the embodiment shown in  FIG. 5 , the current supplied by the second current source  417  is twice in magnitude than that supplied by the first current source  416 , as described above. In this case, an equilateral triangular wave is generated since the discharging current is equal in magnitude to the charging current in regard to the capacitor  418 . When the voltage at the output node N TR1  decreases to become lower than the valley setting voltage V L , the oscillating signal generator  41  repeats the above-mentioned operations. Therefore, the desired oscillating signal TR 1  is obtained from the output node N TR1 . 
   The oscillating signal PC 1  is effectively obtained by inverting the resetting input R through the inverter  419 R. Similarly, the oscillating signal PC 2  is effectively obtained by inverting the setting input S through the inverter  419 S. 
   Referring again to  FIG. 5 , the auxiliary signal generator  43  includes two ramp wave generators  43   a  and  43   b  for generating the auxiliary signals RM 1  and RM 2 , respectively. The ramp wave generator  43   a  includes a sample-and-hold amplifier  431   a , a sample-and-hold capacitor  432   a , a voltage-to-current converter  433   a , an output capacitor  434   a , and a switching means  435   a . The sample-and-hold amplifier  431   a  has a non-inverting terminal coupled to a reference voltage V refa  and an output terminal coupled to a voltage input of the voltage-to-current converter  433   a . The voltage-to-current converter  433   a  has a current output coupled to an output node N RM1 . The output capacitor  434   a  and the switching means  435   a  are connected in parallel between the output node N RM1  and ground. The output node N RM1  is further coupled to an inverting terminal of the sample-and-hold amplifier  431   a  for forming a closed feedback loop. On the other hand, the ramp wave generator  43   b  includes a sample-and-hold amplifier  431   b , a sample-and-hold capacitor  432   b , a voltage-to-current converter  433   b , an output capacitor  434   b , and a switching means  435   b . The sample-and-hold amplifier  431   b  has a non-inverting terminal coupled to a reference voltage V refb  and an output terminal coupled to a voltage input of the voltage-to-current converter  433   b . The voltage-to-current converter  433   b  has a current output coupled to another output node N RM2 . The output capacitor  434   b  and the switching means  435   b  are connected in parallel between the output node N RM2  and ground. The output node N RM2  is further coupled to an inverting terminal of the sample-and-hold amplifier  431   b  for forming a closed feedback loop. 
   The output of the inverter  419 S of the oscillating signal generator  41 , i.e. the oscillating signal PC 2 , is adopted to control the sample-and-hold amplifier  431   a  and the switching means  435   b . On the other hand, the output of the inverter  419 R of the oscillating signal generator  41 , i.e. the oscillating signal PC 1 , is adopted to control the sample-and-hold amplifier  431   b  and the switching means  435   a . In the present invention, each of the switching means  435   a  and  435   b  may be implemented by a switch transistor such as an NMOS transistor, a PMOS transistor, or a bipolar transistor. 
   Hereinafter will be described in detail how the auxiliary signal generator  43  generates the auxiliary signals RM 1  and RM 2  with reference to FIG.  5  and FIG.  2 ( b ). At first is described a method of generating the auxiliary signal RM 1  by using the oscillating signals PC 1  and PC 2  to control the ramp wave generator  43   a . When the oscillating signals PC 1  and PC 2  are LOW, the sample-and-hold amplifier  431   a  and the switching means  435   a  are rendered nonconductive. In this case, a fixed voltage held by the sample-and-hold capacitor  432   a  is converted by using the voltage-to-current converter  433   a  to a fixed current for charging the output capacitor  434   a . As a result, the voltage at the output node N RM1  gradually increases. When the oscillating signal PC 1  is HIGH and the oscillating signal PC 2  is LOW, the switching means  435   a  is rendered conductive. In this case, through the conductive switching means  435   a , the output capacitor  434   a  discharges to the ground while the output node N RM1  is connected to the ground. As a result, the voltage at the output node N RM1  instantly decreases to the ground potential. Therefore, the desired auxiliary signal RM 1  is obtained from the output node N RM1 . For enhancing the stability of the thus-obtained auxiliary signal RM 1 , when the oscillating signal PC 1  is LOW and the oscillating signal PC 2  is HIGH, the sample-and-hold amplifier  431   a  is rendered conductive and then compares the voltage at the output node N RM1  with the reference voltage V refa  through the closed feedback loop, thereby outputting an error voltage for performing the feedback control on the voltage held by the sample-and-hold capacitor  432   a . Because the current for determining the rate of increase of the voltage at the output node N RM1  is converted from the voltage held by the sample-and-hold capacitor  432   a  through the voltage-to-current converter  433   a , the stability of the auxiliary signal RM 1  obtained from the output node N RM1  is enhanced through the feedback control. In the embodiment shown in FIG.  5  and FIG.  2 ( b ), the reference voltage V refa  may be selected as a half of the maximum V max  of the auxiliary signal RM 1  since the oscillating signal PC 2  becomes HIGH at the half period of the auxiliary signal RM 1 . It should be noted that the present invention is not limited to this embodiment and the reference voltage V refa  may be selected on the basis of the time when the oscillating signal PC 2  becomes HIGH and the relationship between the feedback voltage received by the non-inverting terminal of the sample-and-hold amplifier  431   a  and the voltage at the output node N RM1 . 
   Subsequently is described a method of generating the auxiliary signal RM 2  by using the oscillating signals PC 1  and PC 2  to control the ramp generator  43   b . When the oscillating signals PC 1  and PC 2  are LOW, the sample-and-hold amplifier  431   b  and the switching means  435   b  are rendered non-conductive. In this case, a fixed voltage held by the sample-and-hold capacitor  432   b  is converted by using the voltage-to-current converter  433   b  to a fixed current for charging the output capacitor  434   b . As a result, the voltage at the output node N RM2  gradually increases. When the oscillating signal PC 1  is LOW and the oscillating signal PC 2  is HIGH, the switching means  435   b  is rendered conductive. In this case, through the conductive switching means  435   b , the output capacitor  434   b  discharges to the ground while the output node N RM2  is connected to the ground. As a result, the voltage at the output node N RM2  instantly decreases to the ground potential. Therefore, the desired auxiliary signal RM 2  is obtained from the output node N RM2 . For enhancing the stability of the thus-obtained auxiliary signal RM 2 , when the oscillating signal PC 1  is HIGH and the oscillating signal PC 2  is LOW, the sample-and-hold amplifier  431   b  is rendered conductive and then compares the voltage at the output node N RM2  with the reference voltage V refb  through the closed feedback loop, thereby outputting an error voltage for performing the feedback control on the voltage held by the sample-and-hold capacitor  432   b . Because the current for determining the rate of increase of the voltage at the output node N RM2  is converted from the voltage held by the sample-and-hold capacitor  432   b  through the voltage-to-current converter  433   b , the stability of the auxiliary signal RM 2  obtained from the output node N RM2  is enhanced through the feedback control. In the embodiment shown in FIG.  5  and FIG.  2 ( b ), the reference voltage V refb  may be selected as a half of the maximum V max  of the auxiliary signal RM 2  since the oscillating signal PC 1  becomes HIGH at the half period of the auxiliary signal RM 2 . It should be noted that the present invention is not limited to this and the reference voltage V refb  may be selected on the basis of the time when the oscillating signal PC 1  becomes HIGH and the relationship between the feedback voltage received by the non-inverting terminal of the sample-and-hold amplifier  431   b  and the voltage at the output node N RM2 . 
     FIG. 6  is a detailed circuit diagram showing a second example of the multi-phase multi-waveform synchronous oscillator  26  according to the present invention. The second example shown in  FIG. 6  is identical to the first example shown in  FIG. 5  except for the circuit of generating the oscillating signals PC 1  and PC 2  and the method thereof. Therefore, similar elements of  FIG. 6  to those of  FIG. 5  are designated with the same reference numerals of FIG.  5 . For the sake of simplicity, only is described in the following the differences of the second example from the first example. 
   As shown in  FIG. 6 , the second example replaces the inverters  419 R and  419 S of the first example shown in  FIG. 5  with a first one shot generator  611  and a second one shot generator  612 , respectively. More specifically, the first one shot generator  611  is a rising edge one shot generator whose input terminal is coupled to the normal output Q of the latch  413 . Upon detecting a rising edge of the normal output Q, the first one shot generator  611  outputs a pulse with a predetermined width such as 100 nanoseconds. Since the rising edge of the normal output Q occurs at a time when the oscillating signal TR 1  reaches the valley, the first one shot generator  611  effectively generates the desired oscillating signal PC 1 . On the other hand, the second one shot generator  612  is a falling edge one shot generator whose output terminal is coupled to the normal output Q of the latch  413 . Upon detecting a falling edge of the normal output Q, the second one shot generator  612  outputs a pulse with a predetermined width such as 100 nanoseconds. Since the falling edge of the normal output Q occurs at a time when the oscillating signal TR 1  reaches the peak, the second one shot generator  612  effectively generates the desired oscillating signal PC 2 . 
   The second example shown in  FIG. 6  provides an additional advantage as described in the following. The pulses of each of the oscillating signals PC 1  and PC 2  have advantageously a fixed width because the oscillating signals PC 1  and PC 2  are generated by using the first and second one shot generators  611  and  612 , respectively. Since the oscillating signals PC 1  and PC 2  control the switching means  435   a  and  435   b  as described above, the fixed-width pulses ensure constant each discharging period of time of the output capacitors  434   a  and  434   b , as well as each charging period of time. As a result, the stabilities of the auxiliary signals RM 1  and RM 2  are further improved. 
   In one embodiment of the present invention, the switching controllers  22 A to  22 D, the feedback circuits  24 A to  24 D, and the multi-phase multi-waveform synchronous oscillator  26  are incorporated in a single semiconductor integrated circuit chip. The converting circuits  23 A to  23 D are formed as external circuits to the single semiconductor integrated circuit chip and may be implemented by buck type or boost type converting circuits depending on practical application. In another embodiment of the present invention, the power switch transistors  25 A to  25 D of the converting circuits  23 A to  23 D may also be incorporated in a single semiconductor integrated circuit chip with the switching controllers  22 A to  22 D, the feedback circuits  24 A to  24 D, and the multi-phase multi-waveform synchronous oscillator  26 . In this case, the remaining portions of the converting circuits  23 A to  23 D are formed as external circuits. 
   Moreover, the multi-phase multi-waveform synchronous oscillator  26  may be independently formed as a semiconductor integrated circuit chip and then coupled through bonding wires to another semiconductor integrated circuit chip provided with the power supply channels  22 A to  22 D. In addition, the multi-phase multi-waveform synchronous oscillator  26  may output a plurality of oscillating signals to plurality of semiconductor integrated circuit chips, each of which is provided with one power supply channel and packaged separately. 
   While the invention has been described by way of examples and in term of preferred embodiments, it is to be the understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claim should be accorded the broadest interpretation so as to encompass all such modifications.