Patent Publication Number: US-9905755-B2

Title: Semiconductor device and method for producing a semiconductor device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of copending patent application Ser. No. 14/937,357, filed Nov. 10, 2015, which was a continuation of international patent application PCT/JP2013/076031, filed Sep. 26, 2013; the entire contents of the prior applications are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a semiconductor device and a method for producing a semiconductor device. 
     Description of the Related Art 
     In recent years, phase-change memories have been developed (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404). Such a phase-change memory records changes in the resistances of information memory elements in memory cells to thereby store information. 
     The phase-change memory uses the following mechanism: turning on a cell transistor causes a current to pass between a bit line and a source line; this causes a high-resistance-element heater to generate heat; this melts chalcogenide glass (GST: Ge 2 Sb 2 Te 5 ) in contact with the heater to thereby cause a state transition. Chalcogenide glass that is melted at a high temperature (with a large current) and rapidly cooled (by stopping the current) is brought to an amorphous state (Reset operation). On the other hand, chalcogenide glass that is melted at a relatively-low high temperature (with a small current) and slowly cooled (with a gradual decrease in the current) is brought to crystallization (Set operation). Thus, at the time of reading information, the binary information (“0” or “1”) is determined on the basis of whether a large current passes between the bit line and the source line (a low resistance, that is, the crystalline state) or a small current passes (a high resistance, that is, the amorphous state) (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404). 
     In this case, for example, a very large reset current of 200 μA passes. In order to pass such a large reset current through cell transistors, the memory cells need to have a considerably large size. In order to pass such a large current, selection elements such as bipolar transistors and diodes can be used (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404). 
     A diode is a two-terminal element. Thus, when one source line is selected for the purpose of selecting a memory cell, the current of all the memory cells connected to the source line passes through the one source line. This results in a large IR drop, which is a voltage drop equal to the product of IR (current and resistance) based on the resistance of the source line. 
     On the other hand, a bipolar transistor is a three-terminal element. However, a current passes through the gate, which makes it difficult to connect a large number of transistors to the word line. 
     A Surrounding Gate Transistor (hereafter, referred to as an “SGT”) has been proposed that has a structure in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer. SGTs allow a larger current per unit gate width to pass than double-gate transistors (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-356314). In addition, SGTs have a structure in which the gate electrode surrounds the pillar-shaped semiconductor layer. Thus, the gate width per unit area can be increased, so that an even larger current can be passed. 
     In a phase-change memory, a large reset current is used and hence the resistance of the source line needs to be decreased. 
     In existing MOS transistors, in order to successfully perform a metal gate process and a high-temperature process, a metal gate-last process of forming a metal gate after a high-temperature process is used (for example, refer to IEDM2007 K. Mistry et. al, pp 247-250). In that process, a gate is formed of polysilicon; an interlayer insulating film is subsequently deposited; chemical mechanical polishing is then performed to expose the polysilicon gate; the polysilicon gate is etched; and metal is subsequently deposited. Thus, also in the production of an SGT, in order to successfully perform a metal gate process and a high-temperature process, a metal gate-last process of forming a metal gate after a high-temperature process needs to be used. 
     In the metal gate-last process, after a polysilicon gate is formed, a diffusion layer is formed by ion implantation. However, in an SGT, the upper portion of the pillar-shaped silicon layer is covered with a polysilicon gate. Accordingly, it is necessary to find a way to form the diffusion layer. 
     Silicon has a density of about 5×10 22  atoms/cm 3 . Accordingly, for narrow silicon pillars, it is difficult to make impurities be present within the silicon pillars. 
     Regarding existing SGTs, it has been proposed that, while the channel concentration is set to a low impurity concentration of 10 17  cm −3  or less, the work function of the gate material is changed to adjust the threshold voltage (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-356314). 
     A planar MOS transistor has been disclosed in which a sidewall on an LDD region is formed of a polycrystalline silicon of the same conductivity type as that of the lightly doped layer and the surface carriers of the LDD region are induced by the work-function difference between the sidewall and the LDD region, so that the impedance of the LDD region can be reduced, compared with oxide film sidewall LDD MOS transistors (for example, refer to Japanese Unexamined Patent Application Publication No. 11-297984). This publication states that the polycrystalline silicon sidewall is electrically insulated from the gate electrode. That publication also shows that, in a drawing, the polycrystalline silicon sidewall and the source-drain are insulated from each other with an interlayer insulating film. 
     SUMMARY OF THE INVENTION 
     In order to address the above-described problems, the present invention has been accomplished. An object of the present invention is to provide a memory structure that allows a large current to pass through a selected transistor and includes a variable-resistance memory element, and a method for producing the memory structure. 
     With the above and other objects in view there is provided, in accordance with a first embodiment of the invention, a semiconductor device which includes:
         a first pillar-shaped semiconductor layer,   a first gate insulating film formed around the first pillar-shaped semiconductor layer,   a gate electrode formed of metal and formed around the first gate insulating film,   a gate line formed of metal and connected to the gate electrode,   a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer,   a first contact formed of a first metal material and formed around the second gate insulating film,   a second contact formed of a second metal material and connecting an upper portion of the first contact and an upper portion of the first pillar-shaped semiconductor layer,   a diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, and   a variable-resistance memory element formed on the second contact.       

     The first metal material forming the first contact preferably has a work function of 4.0 to 4.2 eV. 
     The first metal material forming the first contact preferably has a work function of 5.0 to 5.2 eV. 
     The semiconductor device preferably further includes:
         a fin-shaped semiconductor layer formed on a semiconductor substrate so as to extend in one direction,   a first insulating film formed around the fin-shaped semiconductor layer,   the first pillar-shaped semiconductor layer formed on the fin-shaped semiconductor layer, and   the first gate insulating film formed around and below the gate electrode and the gate line,   wherein the gate line extends in a direction orthogonal to the fin-shaped semiconductor layer, and   the second diffusion layer is formed in the fin-shaped semiconductor layer.       

     The second diffusion layer formed in the fin-shaped semiconductor layer is preferably further formed in the semiconductor substrate. 
     The semiconductor device preferably further includes a contact line extending parallel with the gate line and connected to the second diffusion layer. 
     The semiconductor device preferably further includes
         the fin-shaped semiconductor layer formed on the semiconductor substrate,   the first insulating film formed around the fin-shaped semiconductor layer,   a second pillar-shaped semiconductor layer formed on the fin-shaped semiconductor layer,   a contact electrode formed of metal and formed around the second pillar-shaped semiconductor layer,   the contact line formed of metal, extending in a direction orthogonal to the fin-shaped semiconductor layer, and connected to the contact electrode, and   the second diffusion layer formed in the fin-shaped semiconductor layer and in a lower portion of the second pillar-shaped semiconductor layer,   wherein the contact electrode is connected to the second diffusion layer.       

     Preferably, an outer linewidth of the gate electrode is equal to a linewidth of the gate line, and a linewidth of the first pillar-shaped semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer is equal to a linewidth of the fin-shaped semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer. 
     A portion of the first gate insulating film is preferably formed between the second pillar-shaped semiconductor layer and the contact electrode. 
     A linewidth of the second pillar-shaped semiconductor layer extending in the direction orthogonal to the fin-shaped semiconductor layer is preferably equal to a linewidth of the fin-shaped semiconductor layer in a direction orthogonal to a direction in which the fin-shaped semiconductor layer extends. 
     A portion of the first gate insulating film is preferably formed around the contact electrode and around the contact line. 
     An outer linewidth of the contact electrode is preferably equal to a linewidth of the contact line. 
     The semiconductor device preferably further includes
         the first pillar-shaped semiconductor layer formed on a semiconductor substrate, and   the first gate insulating film formed around and below the gate electrode and the gate line,   wherein the second diffusion layer is formed in the semiconductor substrate.       

     The semiconductor device preferably further includes a contact line extending parallel with the gate line and connected to the second diffusion layer. 
     The semiconductor device preferably further includes
         a second pillar-shaped semiconductor layer formed on the semiconductor substrate,   a contact electrode formed of metal and formed around the second pillar-shaped semiconductor layer,   a contact line connected to the contact electrode, and   the second diffusion layer formed in a lower portion of the second pillar-shaped semiconductor layer,   wherein the contact electrode is connected to the second diffusion layer.       

     An outer linewidth of the gate electrode is preferably equal to a linewidth of the gate line. 
     A portion of the first gate insulating film is preferably formed between the second pillar-shaped semiconductor layer and the contact electrode. 
     A portion of the first gate insulating film is preferably formed around the contact electrode and around the contact line. 
     An outer linewidth of the contact electrode is preferably equal to a linewidth of the contact line. 
     With the above and other objects in view there is also provided, in accordance with the invention, a method for producing a semiconductor device according to a second aspect of the present invention includes
         a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate so as to extend in one direction and forming a first insulating film around the fin-shaped semiconductor layer,   a second step of, after the first step, forming a first pillar-shaped semiconductor layer, a first dummy gate derived from a first polysilicon, a second pillar-shaped semiconductor layer, and a second dummy gate derived from the first polysilicon,   a third step of, after the second step, forming a third dummy gate and a fourth dummy gate on side walls of the first dummy gate, the first pillar-shaped semiconductor layer, the second dummy gate, and the second pillar-shaped semiconductor layer,   a fourth step of, after the third step, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer,   a fifth step of, after the fourth step, depositing a first interlayer insulating film and performing chemical mechanical polishing to expose upper portions of the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate, removing the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate, forming a first gate insulating film around the first pillar-shaped semiconductor layer and around the second pillar-shaped semiconductor layer, removing the first gate insulating film from around a bottom portion of the second pillar-shaped semiconductor layer, depositing a first metal layer and performing etch back to expose an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the second pillar-shaped semiconductor layer, to form a gate electrode and a gate line around the first pillar-shaped semiconductor layer, and to form a contact electrode and a contact line around the second pillar-shaped semiconductor layer,   a sixth step of, after the fifth step, depositing a second gate insulating film around the first pillar-shaped semiconductor layer, on the gate electrode and the gate line, around the second pillar-shaped semiconductor layer, and on the contact electrode and the contact line, depositing a second metal layer and performing etch back to expose an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the second pillar-shaped semiconductor layer, removing the second gate insulating film on the first pillar-shaped semiconductor layer, depositing a third metal layer, partially etching the third metal layer and the second metal layer to form, from the second metal layer, a first contact surrounding an upper side wall of the first pillar-shaped semiconductor layer and to form, from the third metal layer, a second contact connecting an upper portion of the first contact and an upper portion of the first pillar-shaped semiconductor layer, and   a seventh step of, after the sixth step, depositing a second interlayer insulating film, performing planarization to expose an upper portion of the second contact, and   forming a variable-resistance memory element on the second contact.       

     Preferably, in the second step,
         a second insulating film is formed around the fin-shaped semiconductor layer,   the first polysilicon is deposited on the second insulating film and planarized,   a second resist for forming the gate line, the first pillar-shaped semiconductor layer, the contact line, and the second pillar-shaped semiconductor layer is formed in a direction orthogonal to a direction in which the fin-shaped semiconductor layer extends,   the second resist is used as a mask and the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer are etched to form the first pillar-shaped semiconductor layer, the first dummy gate derived from the first polysilicon, the second pillar-shaped semiconductor layer, and the second dummy gate derived from the first polysilicon.       

     After the first polysilicon is deposited on the second insulating film and planarized, a third insulating film is preferably formed on the first polysilicon. 
     The method for producing a semiconductor device preferably includes, as the third step, forming a fourth insulating film around the first pillar-shaped semiconductor layer, the second pillar-shaped semiconductor layer, the first dummy gate, and the second dummy gate, depositing a second polysilicon around the fourth insulating film and etching the second polysilicon so as to remain on side walls of the first dummy gate, the first pillar-shaped semiconductor layer, the second dummy gate, and the second pillar-shaped semiconductor layer to form the third dummy gate and the fourth dummy gate. 
     The method for producing a semiconductor device preferably includes, as the fourth step, forming the second diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer, forming a fifth insulating film around the third dummy gate and the fourth dummy gate and etching the fifth insulating film so as to have a sidewall shape to form sidewalls derived from the fifth insulating film, and forming a compound layer formed of metal and semiconductor on the second diffusion layer. 
     The method for producing a semiconductor device preferably includes, as the fifth step, depositing the first interlayer insulating film and performing chemical mechanical polishing to expose upper portions of the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate, removing the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate, removing the second insulating film and the fourth insulating film, forming the first gate insulating film around the first pillar-shaped semiconductor layer, around the second pillar-shaped semiconductor layer, and on inner sides of the fifth insulating film, forming a third resist for removing the first gate insulating film from around a bottom portion of the second pillar-shaped semiconductor layer, removing the first gate insulating film from around the bottom portion of the second pillar-shaped semiconductor layer, depositing a metal layer, and performing etch back to expose an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the second pillar-shaped semiconductor layer, to form the gate electrode and the gate line around the first pillar-shaped semiconductor layer and to form the contact electrode and the contact line around the second pillar-shaped semiconductor layer. 
     The present invention can provide a memory structure that allows a large current to pass through a selected transistor and includes a variable-resistance memory element. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a plan view of a semiconductor device according to an embodiment of the present invention;  FIG. 1B  is a sectional view taken along line X-X′ in  FIG. 1A ; and  FIG. 1C  is a sectional view taken along line Y-Y′ in  FIG. 1A . 
         FIG. 2A  is a plan view of a semiconductor device according to an embodiment of the present invention;  FIG. 2B  is a sectional view taken along line X-X′ in  FIG. 2A ; and  FIG. 2C  is a sectional view taken along line Y-Y′ in  FIG. 2A . 
         FIG. 3A  is a plan view of a semiconductor device according to an embodiment of the present invention;  FIG. 3B  is a sectional view taken along line X-X′ in  FIG. 3A ; and  FIG. 3C  is a sectional view taken along line Y-Y′ in  FIG. 3A . 
         FIG. 4A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 4B  is a sectional view taken along line X-X′ in  FIG. 4A ; and  FIG. 4C  is a sectional view taken along line Y-Y′ in  FIG. 4A . 
         FIG. 5A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 5B  is a sectional view taken along line X-X′ in  FIG. 5A ; and  FIG. 5C  is a sectional view taken along line Y-Y′ in  FIG. 5A . 
         FIG. 6A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 6B  is a sectional view taken along line X-X′ in  FIG. 6A ; and  FIG. 6C  is a sectional view taken along line Y-Y′ in  FIG. 6A . 
         FIG. 7A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 7B  is a sectional view taken along line X-X′ in  FIG. 7A ; and  FIG. 7C  is a sectional view taken along line Y-Y′ in  FIG. 7A . 
         FIG. 8A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 8B  is a sectional view taken along line X-X′ in  FIG. 8A ; and  FIG. 8C  is a sectional view taken along line Y-Y′ in  FIG. 8A . 
         FIG. 9A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 9B  is a sectional view taken along line X-X′ in  FIG. 9A ; and  FIG. 9C  is a sectional view taken along line Y-Y′ in  FIG. 9A . 
         FIG. 10A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 10B  is a sectional view taken along line X-X′ in  FIG. 10A ; and  FIG. 10C  is a sectional view taken along line Y-Y′ in  FIG. 10A . 
         FIG. 11A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 11B  is a sectional view taken along line X-X′ in  FIG. 11A ; and  FIG. 11C  is a sectional view taken along line Y-Y′ in  FIG. 11A . 
         FIG. 12A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 12B  is a sectional view taken along line X-X′ in  FIG. 12A ; and  FIG. 12C  is a sectional view taken along line Y-Y′ in  FIG. 12A . 
         FIG. 13A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 13B  is a sectional view taken along line X-X′ in  FIG. 13A ; and  FIG. 13C  is a sectional view taken along line Y-Y′ in  FIG. 13A . 
         FIG. 14A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 14B  is a sectional view taken along line X-X′ in  FIG. 14A ; and  FIG. 14C  is a sectional view taken along line Y-Y′ in  FIG. 14A . 
         FIG. 15A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 15B  is a sectional view taken along line X-X′ in  FIG. 15A ; and  FIG. 15C  is a sectional view taken along line Y-Y′ in  FIG. 15A . 
         FIG. 16A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 16B  is a sectional view taken along line X-X′ in  FIG. 16A ; and  FIG. 16C  is a sectional view taken along line Y-Y′ in  FIG. 16A . 
         FIG. 17A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 17B  is a sectional view taken along line X-X′ in  FIG. 17A ; and  FIG. 17C  is a sectional view taken along line Y-Y′ in  FIG. 17A . 
         FIG. 18A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 18B  is a sectional view taken along line X-X′ in  FIG. 18A ; and  FIG. 18C  is a sectional view taken along line Y-Y′ in  FIG. 18A . 
         FIG. 19A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 19B  is a sectional view taken along line X-X′ in  FIG. 19A ; and  FIG. 19C  is a sectional view taken along line Y-Y′ in  FIG. 19A . 
         FIG. 20A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 20B  is a sectional view taken along line X-X′ in  FIG. 20A ; and  FIG. 20C  is a sectional view taken along line Y-Y′ in  FIG. 20A . 
         FIG. 21A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention; FIG.  21 B is a sectional view taken along line X-X′ in  FIG. 21A ; and  FIG. 21C  is a sectional view taken along line Y-Y′ in  FIG. 21A . 
         FIG. 22A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 22B  is a sectional view taken along line X-X′ in  FIG. 22A ; and  FIG. 22C  is a sectional view taken along line Y-Y′ in  FIG. 22A . 
         FIG. 23A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 23B  is a sectional view taken along line X-X′ in  FIG. 23A ; and  FIG. 23C  is a sectional view taken along line Y-Y′ in  FIG. 23A . 
         FIG. 24A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 24B  is a sectional view taken along line X-X′ in  FIG. 24A ; and  FIG. 24C  is a sectional view taken along line Y-Y′ in  FIG. 24A . 
         FIG. 25A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 25B  is a sectional view taken along line X-X′ in  FIG. 25A ; and  FIG. 25C  is a sectional view taken along line Y-Y′ in  FIG. 25A . 
         FIG. 26A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 26B  is a sectional view taken along line X-X′ in  FIG. 26A ; and  FIG. 26C  is a sectional view taken along line Y-Y′ in  FIG. 26A . 
         FIG. 27A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 27B  is a sectional view taken along line X-X′ in  FIG. 27A ; and  FIG. 27C  is a sectional view taken along line Y-Y′ in  FIG. 27A . 
         FIG. 28A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 28B  is a sectional view taken along line X-X′ in  FIG. 28A ; and  FIG. 28C  is a sectional view taken along line Y-Y′ in  FIG. 28A . 
         FIG. 29A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 29B  is a sectional view taken along line X-X′ in  FIG. 29A ; and  FIG. 29C  is a sectional view taken along line Y-Y′ in  FIG. 29A . 
         FIG. 30A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 30B  is a sectional view taken along line X-X′ in  FIG. 30A ; and  FIG. 30C  is a sectional view taken along line Y-Y′ in  FIG. 30A . 
         FIG. 31A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 31B  is a sectional view taken along line X-X′ in  FIG. 31A ; and  FIG. 31C  is a sectional view taken along line Y-Y′ in  FIG. 31A . 
         FIG. 32A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 32B  is a sectional view taken along line X-X′ in  FIG. 32A ; and  FIG. 32C  is a sectional view taken along line Y-Y′ in  FIG. 32A . 
         FIG. 33A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 33B  is a sectional view taken along line X-X′ in  FIG. 33A ; and  FIG. 33C  is a sectional view taken along line Y-Y′ in  FIG. 33A . 
         FIG. 34A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 34B  is a sectional view taken along line X-X′ in  FIG. 34A ; and  FIG. 34C  is a sectional view taken along line Y-Y′ in  FIG. 34A . 
         FIG. 35A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 35B  is a sectional view taken along line X-X′ in  FIG. 35A ; and  FIG. 35C  is a sectional view taken along line Y-Y′ in  FIG. 35A . 
         FIG. 36A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 36B  is a sectional view taken along line X-X′ in  FIG. 36A ; and  FIG. 36C  is a sectional view taken along line Y-Y′ in  FIG. 36A . 
         FIG. 37A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 37B  is a sectional view taken along line X-X′ in  FIG. 37A ; and  FIG. 37C  is a sectional view taken along line Y-Y′ in  FIG. 37A . 
         FIG. 38A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 38B  is a sectional view taken along line X-X′ in  FIG. 38A ; and  FIG. 38C  is a sectional view taken along line Y-Y′ in  FIG. 38A . 
         FIG. 39A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 39B  is a sectional view taken along line X-X′ in  FIG. 39A ; and  FIG. 39C  is a sectional view taken along line Y-Y′ in  FIG. 39A . 
         FIG. 40A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 40B  is a sectional view taken along line X-X′ in  FIG. 40A ; and  FIG. 40C  is a sectional view taken along line Y-Y′ in  FIG. 40A . 
         FIG. 41A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention; FIG.  41 B is a sectional view taken along line X-X′ in  FIG. 41A ; and  FIG. 41C  is a sectional view taken along line Y-Y′ in  FIG. 41A . 
         FIG. 42A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 42B  is a sectional view taken along line X-X′ in  FIG. 42A ; and  FIG. 42C  is a sectional view taken along line Y-Y′ in  FIG. 42A . 
         FIG. 43A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 43B  is a sectional view taken along line X-X′ in  FIG. 43A ; and  FIG. 43C  is a sectional view taken along line Y-Y′ in  FIG. 43A . 
         FIG. 44A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 44B  is a sectional view taken along line X-X′ in  FIG. 44A ; and  FIG. 44C  is a sectional view taken along line Y-Y′ in  FIG. 44A . 
         FIG. 45A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 45B  is a sectional view taken along line X-X′ in  FIG. 45A ; and  FIG. 45C  is a sectional view taken along line Y-Y′ in  FIG. 45A . 
         FIG. 46A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 46B  is a sectional view taken along line X-X′ in  FIG. 46A ; and  FIG. 46C  is a sectional view taken along line Y-Y′ in  FIG. 46A . 
         FIG. 47A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 47B  is a sectional view taken along line X-X′ in  FIG. 47A ; and  FIG. 47C  is a sectional view taken along line Y-Y′ in  FIG. 47A . 
         FIG. 48A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 48B  is a sectional view taken along line X-X′ in  FIG. 48A ; and  FIG. 48C  is a sectional view taken along line Y-Y′ in  FIG. 48A . 
         FIG. 49A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 49B  is a sectional view taken along line X-X′ in  FIG. 49A ; and  FIG. 49C  is a sectional view taken along line Y-Y′ in  FIG. 49A . 
         FIG. 50A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 50B  is a sectional view taken along line X-X′ in  FIG. 50A ; and  FIG. 50C  is a sectional view taken along line Y-Y′ in  FIG. 50A . 
         FIG. 51A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 51B  is a sectional view taken along line X-X′ in  FIG. 51A ; and  FIG. 51C  is a sectional view taken along line Y-Y′ in  FIG. 51A . 
         FIG. 52A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 52B  is a sectional view taken along line X-X′ in  FIG. 52A ; and  FIG. 52C  is a sectional view taken along line Y-Y′ in  FIG. 52A . 
         FIG. 53A  is a plan view relating to a method for producing a semiconductor device according to an embodiment of the present invention;  FIG. 53B  is a sectional view taken along line X-X′ in  FIG. 53A ; and  FIG. 53C  is a sectional view taken along line Y-Y′ in  FIG. 53A . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the figures of the drawing in detail and first, particularly, to  FIGS. 1A to 1C  thereof, there is shown the structure of a semiconductor device according to an exemplary embodiment of the present invention. 
     As illustrated in  FIGS. 1A to 1C , in the 3×2 matrix cell arrangement, memory cells according to the embodiment are disposed in the first row and the first column, in the first row and the third column, in the second row and the first column, and in the second row and the third column. In the 3×2 matrix cell arrangement, contact devices that have a contact electrode and a contact line for connecting source lines to each other are disposed in the first row and the second column and in the second row and the second column. 
     The memory cell that is positioned in the second row and the first column includes a fin-shaped silicon layer  104  formed on a semiconductor substrate  101  so as to extend in the horizontal direction, a first insulating film  106  formed around the fin-shaped silicon layer  104 , a first pillar-shaped silicon layer  129  formed on the fin-shaped silicon layer  104 , a gate insulating film  162  formed around the first pillar-shaped silicon layer  129 , a gate electrode  168   a  formed of metal and formed around the gate insulating film  162 , and a gate line  168   b  formed of metal and connected to the gate electrode  168   a.  The gate line  168   b  extends in a direction orthogonal to the fin-shaped silicon layer  104 . 
     The memory cell that is positioned in the second row and the first column further includes the gate electrode  168   a,  a gate insulating film  162  formed around and below the gate electrode  168   a  and the gate line  168   b,  a gate insulating film  173  formed around an upper portion of the first pillar-shaped silicon layer  129 , a first contact  179   a  formed of a first metal material and formed around the gate insulating film  173 , a second contact  183   a  formed of a second metal material and connecting an upper portion of the first contact  179   a  and an upper portion of the first pillar-shaped silicon layer  129 , a second diffusion layer  143   a  formed in a lower portion of the first pillar-shaped silicon layer  129 , and a variable-resistance memory element  201   a  formed on the second contact  183   a.  The second diffusion layer  143   a  is formed in the fin-shaped silicon layer  104 . A heater  199   a  that is a high-resistance element is formed between the variable-resistance memory element  201   a  and the second contact  183   a.    
     The variable-resistance memory element  201   a  is preferably constituted by a phase-change film formed of chalcogenide glass (GST: Ge 2 Sb 2 Te 5 ), for example. The heater  199   a  is preferably formed of titanium nitride, for example. 
     The memory cell positioned in the second row and the third column includes a fin-shaped silicon layer  104  formed on a semiconductor substrate  101  so as to extend in the horizontal direction, a first insulating film  106  formed around the fin-shaped silicon layer  104 , a first pillar-shaped silicon layer  131  formed on the fin-shaped silicon layer  104 , a gate insulating film  163  formed around the first pillar-shaped silicon layer  131 , a gate electrode  170   a  formed of metal and formed around the gate insulating film  163 , and a gate line  170   b  formed of metal and connected to the gate electrode  170   a.  The gate line  170   b  extends in a direction orthogonal to the fin-shaped silicon layer  104 . 
     The memory cell positioned in the second row and the third column further includes the gate electrode  170   a,  the gate insulating film  163  formed around and below the gate line  170   b,  a gate insulating film  174  formed around an upper portion of the first pillar-shaped silicon layer  131 , a first contact  181   a  formed of a first metal material and formed around the gate insulating film  174 , a second contact  185   a  formed of a second metal material and connecting an upper portion of the first contact  181   a  and an upper portion of the first pillar-shaped silicon layer  131 , a second diffusion layer  143   a  formed in a lower portion of the first pillar-shaped silicon layer  131 , and a variable-resistance memory element  202   a  formed on the second contact  185   a.  The second diffusion layer  143   a  is formed in the fin-shaped silicon layer  104 . A heater  200   a  that is a high-resistance element is formed between the variable-resistance memory element  202   a  and the second contact  185   a.    
     The variable-resistance memory element  201   a  is connected to the variable-resistance memory element  202   a  via a bit line  207 . 
     The memory cell positioned in the first row and the first column includes a fin-shaped silicon layer  105  formed on a semiconductor substrate  101  so as to extend in the horizontal direction, a first insulating film  106  formed around the fin-shaped silicon layer  105 , a first pillar-shaped silicon layer  132  formed on the fin-shaped silicon layer  105 , a gate insulating film  162  formed around the first pillar-shaped silicon layer  132 , a gate electrode  168   a  formed of metal and formed around the gate insulating film  162 , and a gate line  168   b  formed of metal and connected to the gate electrode  168   a.  The gate line  168   b  extends in a direction orthogonal to the fin-shaped silicon layer  105 . 
     The memory cell positioned in the first row and the first column further includes the gate electrode  168   a,  the gate insulating film  162  formed around and below the gate line  168   b,  a gate insulating film  173  formed around an upper portion of the first pillar-shaped silicon layer  132 , a first contact  179   b  formed of a first metal material and formed around the gate insulating film  173 , a second contact  183   b  formed of a second metal material and connecting an upper portion of the first contact  179   b  and an upper portion of the first pillar-shaped silicon layer  132 , a second diffusion layer  143   b  formed in a lower portion of the first pillar-shaped silicon layer  132 , and a variable-resistance memory element  201   b  formed on the second contact  183   b.  The second diffusion layer  143   b  is formed in the fin-shaped silicon layer  105 . A heater  199   b  that is a high-resistance element is formed between the variable-resistance memory element  201   b  and the second contact  183   b.    
     The memory cell positioned in the first row and the third column includes a fin-shaped silicon layer  105  formed on a semiconductor substrate  101  so as to extend in the horizontal direction, a first insulating film  106  formed around the fin-shaped silicon layer  105 , a first pillar-shaped silicon layer  134  formed on the fin-shaped silicon layer  105 , a gate insulating film  163  formed around the first pillar-shaped silicon layer  134 , a gate electrode  170   a  formed of metal and formed around the gate insulating film  163 , and a gate line  170   b  formed of metal and connected to the gate electrode  170   a.  The gate line  170   b  extends in a direction orthogonal to the fin-shaped silicon layer  105 . 
     The memory cell positioned in the first row and the third column further includes the gate electrode  170   a,  the gate insulating film  163  formed around and below the gate line  170   b,  a gate insulating film  174  formed around an upper portion of the first pillar-shaped silicon layer  134 , a first contact  181   b  formed of a first metal material and formed around the gate insulating film  174 , a second contact  185   b  formed of a second metal material and connecting an upper portion of the first contact  181   b  and an upper portion of the first pillar-shaped silicon layer  134 , a second diffusion layer  143   b  formed in a lower portion of the first pillar-shaped silicon layer  134 , and a variable-resistance memory element  202   b  formed on the second contact  185   b.  The second diffusion layer  143   b  is formed in the fin-shaped silicon layer  105 . A heater  200   b  that is a high-resistance element is formed between the variable-resistance memory element  202   b  and the second contact  185   b.    
     The variable-resistance memory element  201   b  is connected to the variable-resistance memory element  202   b  via a bit line  208 . 
     SGTs allow a larger current per unit gate width to pass than double-gate transistors. In addition, SGTs have a structure in which the gate electrode surrounds the pillar-shaped semiconductor layer. Thus, the gate width per unit area can be increased, so that an even larger current can be passed. Thus, SGTs allow a large reset current to pass, so that phase-change films such as the variable-resistance memory elements  201   a  and  201   b  can be melted at a high temperature (with a large current). For the subthreshold swing (a gate voltage required to change by an order of magnitude a drain-source current of a MOSFET that operates in a weak inversion region) of SGTs, an ideal value can be achieved. Accordingly, off current can be decreased, so that phase-change films such as the variable-resistance memory elements  201   a  and  201   b  can be rapidly cooled (by stopping the current). 
     The gate electrodes  168   a  and  170   a  are formed of metal. The gate lines  168   b  and  170   b  are formed of metal. Furthermore, the first contacts  179   a,    179   b ,  181   a,  and  181   b  formed around the gate insulating films  173  and  174  and formed of a first metal material, and the second contacts  183   a,    183   b,    185   a,  and  185   b  connecting upper portions of the first contacts  179   a,    179   b,    181   a,  and  181   b  and upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and formed of a second metal material, are also formed of metal. Thus, a large amount of metal is used so that the heat dissipation effect of the metal can promote cooling of portions heated by a large reset current. In addition, a semiconductor device according to this embodiment includes the gate electrodes  168   a  and  170   a  and the gate insulating films  162  and  163  formed around and below the gate electrodes  168   a  and  170   a  and the gate lines  168   b  and  170   b.  Accordingly, a gate last process of forming metal gates at the final stage of the heat-treatment step is carried out to form the gate electrodes  168   a  and  170   a  that are metal gates. Thus, both of the metal gate process and the high-temperature process can be successfully performed. 
     The gate insulating films  162  and  163  are formed around and below the gate electrodes  168   a  and  170   a  and the gate lines  168   b  and  170   b.  The gate electrodes  168   a  and  170   a  and the gate lines  168   b  and  170   b  are formed of metal. The gate lines  168   b  and  170   b  extend in a direction orthogonal to the fin-shaped silicon layers  104  and  105 . The second diffusion layers  143   a  and  143   b  are formed in the fin-shaped silicon layers  104  and  105 . The gate electrodes  168   a  and  170   a  have outer linewidths equal to the linewidths of the gate lines  168   b  and  170   b.  Also, the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  have linewidths equal to the linewidths of the fin-shaped silicon layers  104  and  105 . Accordingly, in the semiconductor device according to this embodiment, the fin-shaped silicon layers  104  and  105 , the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the gate electrodes  168   a  and  170   a,  and the gate lines  168   b  and  170   b  are formed by self alignment with two masks. As a result, according to the embodiment, the number of steps required to produce the semiconductor device can be reduced. 
     The contact device positioned in the second row and the second column includes a fin-shaped silicon layer  104  formed on a semiconductor substrate  101  so as to extend in the horizontal direction, a first insulating film  106  formed around the fin-shaped silicon layer  104 , and a second pillar-shaped silicon layer  130  formed on the fin-shaped silicon layer  104 . A linewidth of the second pillar-shaped silicon layer  130  in a direction orthogonal to the fin-shaped silicon layer  104  is equal to a linewidth of the fin-shaped silicon layer  104  in the direction orthogonal to the fin-shaped silicon layer  104 . 
     The contact device positioned in the second row and the second column further includes a contact electrode  169   a  formed of metal and formed around the second pillar-shaped silicon layer  130 , a gate insulating film  165  formed between the second pillar-shaped silicon layer  130  and the contact electrode  169   a,  a contact line  169   b  formed of metal, extending in a direction orthogonal to the fin-shaped silicon layer  104 , and connected to the contact electrode  169   a,  and a gate insulating film  164  formed around the contact electrode  169   a  and the contact line  169   b.  The outer linewidth of the contact electrode  169   a  is equal to the linewidth of the contact line  169   b.  A second diffusion layer  143   a  is formed in the fin-shaped silicon layer  104  and in a lower portion of the second pillar-shaped silicon layer  130 . The contact electrode  169   a  is electrically connected to the second diffusion layer  143   a.    
     The contact device positioned in the second row and the second column further includes a gate insulating film  175  formed around an upper portion of the second pillar-shaped silicon layer  130 , a third contact  180   a  formed of a first metal material and formed around the gate insulating film  175 , and a fourth contact  184   a  formed of a second metal material and connecting an upper portion of the third contact  180   a  and an upper portion of the second pillar-shaped silicon layer  130 . The third contact  180   a  is electrically connected to the contact electrode  169   a.    
     Thus, the second diffusion layer  143   a,  the contact electrode  169   a,  the contact line  169   b,  the third contact  180   a,  and the fourth contact  184   a  are electrically interconnected. 
     The contact device positioned in the first row and the second column includes a fin-shaped silicon layer  105  formed on a semiconductor substrate  101  so as to extend in the horizontal direction, a first insulating film  106  formed around the fin-shaped silicon layer  105 , and a second pillar-shaped silicon layer  133  formed on the fin-shaped silicon layer  105 . A linewidth of the second pillar-shaped silicon layer  133  in a direction orthogonal to the fin-shaped silicon layer  105  is equal to a linewidth of the fin-shaped silicon layer  105  in the direction orthogonal to the fin-shaped silicon layer  105 . 
     The contact device positioned in the first row and the second column further includes a contact electrode  169   a  formed of metal and formed around the second pillar-shaped silicon layer  133 , a gate insulating film  166  formed between the second pillar-shaped silicon layer  133  and the contact electrode  169   a,  a contact line  169   b  formed of metal, extending in a direction orthogonal to the fin-shaped silicon layer  105 , and connected to the contact electrode  169   a,  a gate insulating film  164  formed around the contact electrode  169   a  and the contact line  169   b,  and a second diffusion layer  143   b  in the fin-shaped silicon layer  105  and in a lower portion of the second pillar-shaped silicon layer  133 . The outer linewidth of the contact electrode  169   a  is equal to the linewidth of the contact line  169   b.  The contact electrode  169   a  is electrically connected to the second diffusion layer  143   b.    
     The contact device positioned in the first row and the second column further includes a gate insulating film  176  formed around an upper portion of the second pillar-shaped silicon layer  133 , a third contact  180   b  formed around the gate insulating film  176  and formed of a first metal material, and a fourth contact  184   b  connecting an upper portion of the third contact  180   b  and an upper portion of the second pillar-shaped silicon layer  133  and formed of a second metal material. The third contact  180   b  is electrically connected to the contact electrode  169   a.    
     Thus, the second diffusion layer  143   b,  the contact electrode  169   a,  the contact line  169   b,  the third contact  180   b,  and the fourth contact  184   b  are electrically interconnected. 
     The semiconductor device according to this embodiment includes the contact line  169   b  extending parallel with the gate lines  168   b  and  170   b  and connected to the second diffusion layers  143   a  and  143   b.  Thus, the second diffusion layers  143   a  and  143   b  are connected to each other and the resistance of the source lines can be decreased. As a result, a large reset current can be passed through the source lines. The contact line  169   b  extending parallel with the gate lines  168   b  and  170   b  is preferably disposed such that, for example, a single contact line  169   b  is disposed every 2, 4, 8, 16, 32, or 64 memory cells arranged in a line in the direction in which the bit lines  207  and  208  extend. 
     In this embodiment, the structure including the second pillar-shaped silicon layers  130  and  133  and the contact electrode  169   a  and the contact line  169   b  formed around the second pillar-shaped silicon layers  130  and  133 , is the same as the transistor structure of the memory cell positioned, for example, in the first row and the first column except that the contact electrode  169   a  is connected to the second diffusion layers  143   a  and  143   b.  All the source lines constituted by the second diffusion layers  143   a  and  143   b  and extending parallel with the gate lines  168   b  and  170   b  are connected to the contact line  169   b.  As a result, the number of steps required to produce the semiconductor device can be reduced. 
       FIGS. 2A to 2C  illustrate a semiconductor device that has a structure in which, compared with the second diffusion layers  143   a  and  143   b  in  FIGS. 1A to 1C , a second diffusion layer  143   c  is formed to a deep level in the semiconductor substrate  101  and is formed in the fin-shaped silicon layers  104  and  105 , and is connected in the same manner as in the second diffusion layers  143   a  and  143   b  in  FIGS. 1A to 1C . This structure allows a further decrease in the source resistance. 
       FIGS. 3A to 3C  illustrate a semiconductor device that has a structure in which the fin-shaped silicon layer  105  and the first insulating film  106  formed around the fin-shaped silicon layer  105  in  FIGS. 2A to 2C  are not formed, and a second diffusion layer  143   d  is directly formed in the semiconductor substrate  101 . This structure allows a further decrease in the source resistance. 
     Hereinafter, steps for producing a semiconductor device according to an embodiment of the present invention will be described with reference to  FIGS. 4A to 53C . 
     First, a first step according to the embodiment will be described. The first step includes forming fin-shaped silicon layers  104  and  105  on a semiconductor substrate  101  and forming a first insulating film  106  around the fin-shaped silicon layers  104  and  105 . In this embodiment, a silicon substrate is used as the semiconductor substrate  101 . Alternatively, a substrate that is formed of another semiconductor material may be used. 
     First, as illustrated in  FIGS. 4A to 4C , first resists  102  and  103  for forming fin-shaped silicon layers  104  and  105  extending in the horizontal direction on a silicon substrate  101  are formed. 
     Subsequently, as illustrated in  FIGS. 5A to 5C , the silicon substrate  101  is etched to form the fin-shaped silicon layers  104  and  105 . Here, the fin-shaped silicon layers  104  and  105  are formed with the resists serving as masks. Alternatively, instead of the resists, hard masks such as oxide films and nitride films may be used. 
     Subsequently, as illustrated in  FIGS. 6A to 6C , the first resists  102  and  103  are removed. 
     Subsequently, as illustrated in  FIGS. 7A to 7C , a first insulating film  106  is deposited around the fin-shaped silicon layers  104  and  105 . The first insulating film  106  may be an oxide film formed with high-density plasma or an oxide film formed by low-pressure CVD (Chemical Vapor Deposition). 
     Subsequently, as illustrated in  FIGS. 8A to 8C , the first insulating film  106  is subjected to etch back to expose upper portions of the fin-shaped silicon layers  104  and  105 . 
     Thus, the first step according to the embodiment has been described, the first step including forming fin-shaped silicon layers  104  and  105  on a semiconductor substrate  101  and forming a first insulating film  106  around the fin-shaped silicon layers  104  and  105 . 
     Hereafter, a second step according to an embodiment of the present invention will be described. In the second step, after the first step, second insulating films  107  and  108  are formed around the fin-shaped silicon layers  104  and  105 , and a first polysilicon  109  is deposited on the second insulating films  107  and  108  and planarized. Subsequently, second resists  111 ,  112 , and  113  for forming gate lines  168   b  and  170   b,  first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , a contact line  169   b,  and second pillar-shaped silicon layers  130  and  133  are formed so as to extend in a direction orthogonal to a direction in which the fin-shaped silicon layers  104  and  105  extend. Subsequently, the first polysilicon  109 , the second insulating films  107  and  108 , and the fin-shaped silicon layers  104  and  105  are etched to form the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , first dummy gates  117  and  119  derived from the first polysilicon  109 , the second pillar-shaped silicon layers  130  and  133 , and a second dummy gate  118  derived from the first polysilicon  109 . 
     First, as illustrated in  FIGS. 9A to 9C , second insulating films  107  and  108  are formed around the fin-shaped silicon layers  104  and  105  and on the semiconductor substrate  101  so as to extend in the horizontal direction. The second insulating films  107  and  108  are preferably oxide films. 
     Subsequently, as illustrated in  FIGS. 10A to 10C , a first polysilicon  109  is deposited on the second insulating films  107  and  108  and planarized. 
     Subsequently, as illustrated in  FIGS. 11A to 11C , a third insulating film  110  is formed on the first polysilicon  109 . The third insulating film  110  is preferably a nitride film. 
     Subsequently, as illustrated in  FIGS. 12A to 12C , second resists  111 ,  112 , and  113  for forming gate lines  168   b  and  170   b,  first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , second pillar-shaped silicon layers  130  and  133 , and a contact line  169   b,  are formed in a direction orthogonal to a direction in which the fin-shaped silicon layers  104  and  105  extend. 
     Subsequently, as illustrated in  FIGS. 13A to 13C , while the second resists  111 ,  112 , and  113  are used as masks, the third insulating film  110 , the first polysilicon  109 , the second insulating films  107  and  108 , and the fin-shaped silicon layers  104  and  105  are etched to form the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , first dummy gates  117  and  119  derived from the first polysilicon  109 , the second pillar-shaped silicon layers  130  and  133 , and a second dummy gate  118  derived from the first polysilicon  109 . Here, the third insulating film  110  is divided into a plurality of portions to provide third insulating films  114 ,  115 , and  116  on the first dummy gates  117  and  119  and the second dummy gate  118 . The second insulating films  107  and  108  are divided into a plurality of portions to provide second insulating films  123 ,  124 ,  125 ,  126 ,  127 , and  128 . In a case where the second resists  111 ,  112 , and  113  are removed during this etching, the third insulating films  114 ,  115 , and  116  function as hard masks. On the other hand, in a case where the second resists  111 ,  112 , and  113  are not removed during the etching, it is not necessary to use the third insulating films  114 ,  115 , and  116  as masks. 
     Subsequently, as illustrated in  FIGS. 14A to 14C , the second resists  111 ,  112 , and  113  are removed. 
     Thus, the second step has been described. In the second step, after the first step, second insulating films  107  and  108  are formed around the fin-shaped silicon layers  104  and  105 , and a first polysilicon  109  is deposited on the second insulating films  107  and  108  and planarized. Subsequently, second resists  111 ,  112 , and  113  for forming gate lines  168   b  and  170   b,  first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , a contact line  169   b,  and second silicon layers  130  and  133  are formed so as to extend in a direction orthogonal to a direction in which the fin-shaped silicon layers  104  and  105  extend. Subsequently, the first polysilicon  109 , the second insulating films  107  and  108 , and the fin-shaped silicon layers  104  and  105  are etched to form the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , first dummy gates  117  and  119  derived from the first polysilicon  109 , the second pillar-shaped silicon layers  130  and  133 , and a second dummy gate  118  derived from the first polysilicon  109 . 
     Hereafter, a third step according to an embodiment of the present invention will be described. In the third step, after the second step, a fourth insulating film  135  is formed around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the second pillar-shaped silicon layers  130  and  133 , the first dummy gates  117  and  119 , and the second dummy gate  118 . Subsequently, a second polysilicon  136  is deposited around the fourth insulating film  135  and etched such that the second polysilicon  136  remains on side walls of the first dummy gates  117  and  119 , the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the second dummy gate  118 , and the second pillar-shaped silicon layers  130  and  133  to form third dummy gates  137  and  139  and a fourth dummy gate  138 . 
     Subsequently, as illustrated in  FIGS. 15A to 15C , a fourth insulating film  135  is formed around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the second pillar-shaped silicon layers  130  and  133 , the first dummy gates  117  and  119 , and the second dummy gate  118 . Subsequently, a second polysilicon  136  is deposited around the fourth insulating film  135 . 
     Subsequently, as illustrated in  FIGS. 16A to 16C , the second polysilicon  136  is etched such that the second polysilicon  136  remains on side walls of the first dummy gates  117  and  119 , the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the second dummy gate  118 , and the second pillar-shaped silicon layers  130  and  133 . As a result, third dummy gates  137  and  139  and a fourth dummy gate  138  are formed. At this time, the fourth insulating film  135  may be divided into a plurality of portions to provide fourth insulating films  140 ,  141 , and  142 . 
     Thus, the third step has been described. In the third step, after the second step, a fourth insulating film  135  is formed around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the second pillar-shaped silicon layers  130  and  133 , the first dummy gates  117  and  119 , and the second dummy gate  118 . Subsequently, a second polysilicon  136  is deposited around the fourth insulating film  135  and etched such that the second polysilicon  136  remains on side walls of the first dummy gates  117  and  119 , the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the second dummy gate  118 , and the second pillar-shaped silicon layers  130  and  133  to form third dummy gates  137  and  139  and a fourth dummy gate  138 . 
     Hereafter, a fourth step according to an embodiment of the present invention will be described. In the fourth step, after the third step, second diffusion layers  143   a  and  143   b  are formed in upper portions of the fin-shaped silicon layers  104  and  105 , lower portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , and lower portions of the second pillar-shaped silicon layers  130  and  133 . Subsequently, a fifth insulating film  144  is formed around the third dummy gates  137  and  139  and the fourth dummy gate  138  and etched so as to have a sidewall shape to form sidewalls  145 ,  146 , and  147  derived from the fifth insulating film  144 . Furthermore, compound layers  148 ,  149 ,  150 ,  151 ,  152 ,  153 ,  154 , and  155  formed of metal and semiconductor are formed on the second diffusion layers  143   a  and  143   b.    
     First, as illustrated in  FIGS. 17A to 17C , an impurity is introduced to form second diffusion layers  143   a  and  143   b  in lower portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and lower portions of the second pillar-shaped silicon layers  130  and  133 . In a case where the impurity is introduced to form n-type diffusion layers, arsenic or phosphorus is preferably introduced. On the other hand, in a case where the impurity is introduced to form p-type diffusion layers, boron is preferably introduced. The diffusion layers may be formed after formation of sidewalls  145 ,  146 , and  147  derived from a fifth insulating film  144  described below. 
     Subsequently, as illustrated in  FIGS. 18A to 18C , a fifth insulating film  144  is formed around the third dummy gates  137  and  139  and the fourth dummy gate  138 . The fifth insulating film  144  is preferably a nitride film. 
     Subsequently, as illustrated in  FIGS. 19A to 19C , the fifth insulating film  144  is etched so as to have a sidewall shape. As a result, sidewalls  145 ,  146 , and  147  are formed from the fifth insulating film  144 . 
     Subsequently, as illustrated in  FIGS. 20A to 20C , compound layers  148 ,  149 ,  150 ,  151 ,  152 ,  153 ,  154 , and  155  formed of metal and semiconductor are formed on the second diffusion layers  143   a  and  143   b.  At this time, compound layers  156 ,  158 , and  157  formed of metal and semiconductor are also formed in upper portions of the third dummy gates  137  and  139  and an upper portion of the fourth dummy gate  138 . 
     Thus, the fourth step has been described. In the fourth step, second diffusion layers  143   a  and  143   b  are formed in upper portions of the fin-shaped silicon layers  104  and  105 , lower portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , and lower portions of the second pillar-shaped silicon layers  130  and  133 . Subsequently, a fifth insulating film  144  is formed around the third dummy gates  137  and  139  and the fourth dummy gate  138  and etched so as to have a sidewall shape to form sidewalls  145 ,  146 , and  147  derived from the fifth insulating film  144 . Furthermore, compound layers  148 ,  149 ,  150 ,  151 ,  152 ,  153 ,  154 , and  155  formed metal and semiconductor are formed on the second diffusion layers  143   a  and  143   b.    
     Hereafter, a fifth step according to an embodiment of the present invention will be described. In the fifth step, after the fourth step, a first interlayer insulating film  159  is deposited and chemical mechanical polishing is performed to expose upper portions of the first dummy gates  117  and  119 , the second dummy gate  118 , the third dummy gates  137  and  139 , and the fourth dummy gate  138 ; and the first dummy gates  117  and  119 , the second dummy gate  118 , the third dummy gates  137  and  139 , and the fourth dummy gate  138  are removed. Subsequently, the second insulating films  123 ,  124 ,  125 ,  126 ,  127 , and  128  and the fourth insulating films  140 ,  141 , and  142  are removed; and a gate insulating film  160  is formed around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , around the second pillar-shaped silicon layers  130  and  133 , and on inner sides of the fifth insulating film  144 . Subsequently, a third resist  161  for removing the gate insulating film  160  from around the bottom portions of the second pillar-shaped silicon layers  130  and  133  is formed; the gate insulating film  160  is removed from around the bottom portions of the second pillar-shaped silicon layers  130  and  133 ; and a metal layer  167  is deposited. Subsequently, etch back is performed to expose upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and upper portions of the second pillar-shaped silicon layers  130  and  133 , so that gate electrodes  168   a  and  170   a  and gate lines  168   b  and  170   b  are formed around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 . After that, a contact electrode  169   a  and a contact line  169   b  are formed around the second pillar-shaped silicon layers  130  and  133 . 
     First, as illustrated in  FIGS. 21A to 21C , a first interlayer insulating film  159  is deposited. Here, a contact stopper film may be used. 
     Subsequently, as illustrated in  FIGS. 22A to 22C , chemical mechanical polishing (CMP) is performed to expose upper portions of the first dummy gates  117  and  119 , the second dummy gate  118 , the third dummy gates  137  and  139 , and the fourth dummy gate  138 . At this time, the compound layers  156 ,  158 , and  157  formed of metal and semiconductor and formed in the upper portions of the third dummy gates  137  and  139  and in the upper portion of the fourth dummy gate  138  are removed. 
     Subsequently, as illustrated in  FIGS. 23A to 23C , the first dummy gates  117  and  119 , the second dummy gate  118 , the third dummy gates  137  and  139 , and the fourth dummy gate  138  are removed. 
     Subsequently, as illustrated in  FIGS. 24A to 24C , the second insulating films  123 ,  124 ,  125 ,  126 ,  127 , and  128  and the fourth insulating films  140 ,  141 , and  142  are removed. 
     Subsequently, as illustrated in  FIGS. 25A to 25C , a gate insulating film  160  is formed around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , around the second pillar-shaped silicon layers  130  and  133 , and on inner sides of the fifth insulating films  145 ,  146 , and  147 . 
     Subsequently, as illustrated in  FIGS. 26A to 26C , a third resist  161  for removing the gate insulating film  160  from around the bottom portions of the second pillar-shaped silicon layers  130  and  133  is formed. 
     Subsequently, as illustrated in  FIGS. 27A to 27C , while the third resist  161  is used as a mask, the gate insulating film  160  is removed from around the bottom portions of the second pillar-shaped silicon layers  130  and  133 . At this time, the first gate insulating film  160  is divided into a plurality of portions to provide gate insulating films  162 ,  163 ,  164 ,  165 , and  166 . Incidentally, the gate insulating films  164 ,  165 , and  166  may be removed by isotropic etching. 
     Subsequently, as illustrated in  FIGS. 28A to 28C , the third resist  161  is removed. 
     Subsequently, as illustrated in  FIGS. 29A to 29C , a metal layer  167  is deposited. 
     Subsequently, as illustrated in  FIGS. 30A to 30C , the metal layer  167  is subjected to etch back to form gate electrodes  168   a  and  170   a  and gate lines  168   b  and  170   b  around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and to form a contact electrode  169   a  and a contact line  169   b  around the second pillar-shaped silicon layers  130  and  133 . 
     Thus, the fifth step has been described. In the fifth step, after the fourth step, a first interlayer insulating film  159  is deposited and chemical mechanical polishing is performed to expose upper portions of the first dummy gates  117  and  119 , the second dummy gate  118 , the third dummy gates  137  and  139 , and the fourth dummy gate  138 ; and the first dummy gates  117  and  119 , the second dummy gate  118 , the third dummy gates  137  and  139 , and the fourth dummy gate  138  are removed. Subsequently, the second insulating films  123 ,  124 ,  125 ,  126 ,  127 , and  128  and the fourth insulating films  140 ,  141 , and  142  are removed; and a gate insulating film  160  is formed around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , around the second pillar-shaped silicon layers  130  and  133 , and on inner sides of the fifth insulating film  144 . Subsequently, a third resist  161  for removing the gate insulating film  160  from around the bottom portions of the second pillar-shaped silicon layers  130  and  133  is formed; the gate insulating film  160  is removed from around the bottom portions of the second pillar-shaped silicon layers  130  and  133 ; and a metal layer  167  is deposited. Subsequently, etch back is performed to expose upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and upper portions of the second pillar-shaped silicon layers  130  and  133  to form gate electrodes  168   a  and  170   a  and gate lines  168   b  and  170   b  around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 . After that, a contact electrode  169   a  and a contact line  169   b  are formed around the second pillar-shaped silicon layers  130  and  133 . 
     Hereafter, a sixth step according to an embodiment of the present invention will be described. In the sixth step, gate insulating films  123 ,  124 ,  125 ,  126 ,  127 , and  128  are deposited around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , on the gate electrodes  168   a  and  170   a  and the gate lines  168   b  and  170   b,  around the second pillar-shaped silicon layers  130  and  133 , and on the contact electrode  169   a  and the contact line  169   b.  Subsequently, a metal layer  178  is deposited and etch back is performed to expose upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and upper portions of the second pillar-shaped silicon layers  130  and  133 . Subsequently, the gate insulating films  123 ,  124 ,  125 ,  126 ,  127 , and  128  on the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  are removed. Subsequently, a metal layer  182  is deposited and the metal layer  182  and the metal layer  178  are partially etched to form, from the metal layer  178 , first contacts  179   a,    179   b,    181   a,  and  181   b  surrounding upper side walls of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and to form, from the metal layer  182 , second contacts  183   a,    183   b,    185   a,  and  185   b  connecting upper portions of the first contacts  179   a,    179   b,    181   a,  and  181   b  and upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 . The first contacts  179   a ,  179   b,    181   a,  and  181   b  are formed of a first metal material forming the metal layer  178 . The second contacts  183   a,    183   b,    185   a,  and  185   b  are formed of a second metal material forming the metal layer  182 . 
     First, as illustrated in  FIGS. 31A to 31C , the exposed gate insulating films  162 ,  163 ,  164 ,  165 , and  166  are removed. 
     Subsequently, as illustrated in  FIGS. 32A to 32C , a gate insulating film  171  is deposited around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , on the gate electrodes  168   a  and  170   a  and the gate lines  168   b  and  170   b , around the second pillar-shaped silicon layers  130  and  133 , and on the contact electrode  169   a  and the contact line  169   b.    
     Subsequently, as illustrated in  FIGS. 33A to 33C , a fourth resist  172  for removing the gate insulating film  171  present on at least a portion of the contact electrode  169   a  and the contact line  169   b  is formed. 
     Subsequently, as illustrated in  FIGS. 34A to 34C , the gate insulating film  171  present on at least a portion of the contact electrode  169   a  and the contact line  169   b  is removed. Here, the gate insulating film  171  is divided into a plurality of portions to provide gate insulating films  173 ,  174 ,  175 ,  176 , and  177 . Incidentally, the gate insulating films  175 ,  176 , and  177  may be removed by isotropic etching. 
     As described above, contacts are formed by etching only for the thickness of the gate insulating film  160  and the thickness of the gate insulating film  171 . This eliminates the necessity of performing the steps of forming deep contact holes. 
     Subsequently, as illustrated in  FIGS. 35A to 35C , the fourth resist  172  is removed. 
     Subsequently, as illustrated in  FIGS. 36A to 36C , a metal layer  178  is deposited. In a case where the transistor to be formed is of an n-type, the first metal material forming the metal layer  178  preferably has a work function of 4.0 to 4.2 eV. In this case, examples of the first metal material include a compound (TaTi) formed of tantalum and titanium and tantalum nitride (TaN). On the other hand, in a case where the transistor to be formed is of a p-type, the first metal material forming the metal layer  178  preferably has a work function of 5.0 to 5.2 eV. In this case, examples of the first metal material include ruthenium (Ru) and titanium nitride (TiN). 
     Subsequently, as illustrated in  FIGS. 37A to 37C , the metal layer  178  is subjected to etch back to expose upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and upper portions of the second pillar-shaped silicon layers  130  and  133 . At this time, metal lines  179 ,  180 , and  181  are formed from the metal layer  178 . 
     Subsequently, as illustrated in  FIGS. 38A to 38C , the exposed gate insulating films  173  and  174  on the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  are removed. 
     Subsequently, as illustrated in  FIGS. 39A to 39C , a metal layer  182  is deposited. The metal layer  182  may be formed of the same metal material as that for the metal layer  178  and the type of the metal material is not particularly limited. 
     Subsequently, as illustrated in  FIGS. 40A to 40C , the metal layer  182  is subjected to etch back to form metal lines  183 ,  184 , and  185 . 
     Subsequently, as illustrated in  FIGS. 41A to 41C , fifth resists  186  and  187  are formed so as to be orthogonal to the direction in which the metal lines  179 ,  180 , and  181  and the metal lines  183 ,  184 , and  185  extend. 
     Subsequently, as illustrated in  FIGS. 42A to 42C , the metal lines  179 ,  180 , and  181  and the metal lines  183 ,  184 , and  185  are etched to form first contacts  179   a,    179   b,    181   a,  and  181   b,  second contacts  183   a,    183   b,    185   a,  and  185   b,  third contacts  180   a  and  180   b,  and fourth contacts  184   a  and  184   b.    
     Subsequently, as illustrated in  FIGS. 43A to 43C , the fifth resists  186  and  187  are removed. 
     Thus, the sixth step has been described. In the sixth step, after the fifth step, gate insulating films  123 ,  124 ,  125 ,  126 ,  127 , and  128  are deposited around the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , on the gate electrodes  168   a  and  170   a  and the gate lines  168   b  and  170   b,  around the second pillar-shaped silicon layers  130  and  133 , and on the contact electrode  169   a  and the contact line  169   b.  Subsequently, a metal layer  178  is deposited and etch back is performed to expose upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and upper portions of the second pillar-shaped silicon layers  130  and  133 . Subsequently, the gate insulating films  123 ,  124 ,  125 ,  126 ,  127 , and  128  on the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  are removed. Subsequently, a metal layer  182  is deposited and the metal layer  182  and the metal layer  178  are partially etched to form, from the metal layer  178 , first contacts  179   a ,  179   b,    181   a,  and  181   b  surrounding upper side walls of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and to form, from the metal layer  182 , second contacts  183   a,    183   b,    185   a,  and  185   b  connecting upper portions of the first contacts  179   a,    179   b,    181   a,  and  181   b  and upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 . 
     Hereafter, a seventh step will be described. In the seventh step, after the sixth step, a second interlayer insulating film  194  is deposited and planarized to expose upper portions of the second contacts  183   a,    183   b,    185   a,  and  185   b;  and variable-resistance memory elements  201   a,    201   b,    202   a,  and  202   b  are formed on the second contacts  183   a,    183   b,    185   a,  and  185   b.    
     First, as illustrated in  FIGS. 44A to 44C , a second interlayer insulating film  194  is deposited and planarized to expose upper portions of the second contacts  183   a,    183   b,    185   a,  and  185   b.  At this time, upper portions of the fourth contacts  184   a  and  184   b  may be exposed. 
     Subsequently, as illustrated in  FIGS. 45A to 45C , a metal layer  195  and a variable-resistance film  196  are deposited. 
     Subsequently, as illustrated in  FIGS. 46A to 46C , sixth resists  197  and  198  are formed in a direction orthogonal to the bit lines such that upper portions of the second contacts  183   a,    183   b,    185   a,  and  185   b  are connected to the metal layer  195 . 
     Subsequently, as illustrated in  FIGS. 47A to 47C , the metal layer  195  and the variable-resistance film  196  are etched. The metal layer  195  is divided into metal lines  199  and  200  and the variable-resistance film  196  is divided into variable-resistance film lines  201  and  202 . 
     Subsequently, as illustrated in  FIGS. 48A to 48C , the sixth resists  197  and  198  are removed. 
     Subsequently, as illustrated in  FIGS. 49A to 49C , a third interlayer insulating film  203  is deposited and etch back is performed to expose upper portions of the variable-resistance film lines  201  and  202 . 
     Subsequently, as illustrated in  FIGS. 50A to 50C , a metal layer  204  is deposited. 
     Subsequently, as illustrated in  FIGS. 51A to 51C , seventh resists  205  and  206  for forming bit lines are formed. The seventh resists  205  and  206  are preferably formed so as to extend in a direction orthogonal to the metal lines  199  and  200  and the variable-resistance film lines  201  and  202 . 
     Subsequently, as illustrated in  FIGS. 52A to 52C , the metal layer  204 , the metal lines  199  and  200 , and the variable-resistance film lines  201  and  202  are etched to form bit lines  207  and  208 . At this time, the metal lines  199  and  200  and the variable-resistance film lines  201  and  202  are divided to form heaters  199   a ,  199   b,    200   a,  and  200   b  that are high-resistance elements and variable-resistance memory elements  201   a,    201   b,    202   a,  and  202   b.    
     Subsequently, as illustrated in  FIGS. 53A to 53C , the seventh resists  205  and  206  are removed. 
     Thus, the seventh step has been described. In the seventh step, after the sixth step, a second interlayer insulating film  194  is deposited and planarized to expose upper portions of the second contacts  183   a,    183   b,    185   a,  and  185   b;  and variable-resistance memory elements  201   a,    201   b,    202   a,  and  202   b  are formed on the second contacts  183   a,    183   b,    185   a,  and  185   b.    
     Thus, steps for producing a semiconductor device according to an embodiment of the present invention have been described. According to this embodiment, all structures of the semiconductor device are formed with liner resists, which facilitates microprocessing. 
     SGTs allow a larger current per unit gate width to pass than double-gate transistors. In addition, SGTs have a structure in which the gate electrode surrounds the pillar-shaped semiconductor layer. Thus, the gate linewidth per unit area can be increased, so that an even larger current can be passed. Thus, SGTs allow a large reset current to pass, so that phase-change films such as the variable-resistance memory elements  201   a,    201   b,    202   a,  and  202   b  can be melted at a high temperature (with a large current). For the subthreshold swing of SGTs, an ideal value can be achieved. Accordingly, off current can be decreased, so that phase-change films can be rapidly cooled (by stopping the current). 
     The semiconductor device according to the embodiment includes the gate insulating film  194  formed around upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the first contacts  179   a,    179   b,    181   a,  and  181   b  formed around the gate insulating film  194  and derived from the metal layer  178 , and the second contacts  183   a,    183   b,    185   a,  and  185   b  connecting upper portions of the first contacts  179   a,    179   b,    181   a,  and  181   b  and upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  and derived from the metal layer  182 . This provides an SGT in which upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  function as n-type semiconductor layers or p-type semiconductor layers by using the work function difference between metal and semiconductor. This eliminates the necessity of performing the step of forming diffusion layers in upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 . 
     The gate electrode  168   a  and the gate line  168   b  are formed of metal. The first contacts  179   a,    179   b,    181   a,  and  181   b  formed around the gate insulating film  173  are formed of metal. The second contacts  183   a,    183   b,    185   a,  and  185   b  connecting upper portions of the first contacts  179   a,    179   b,    181   a,  and  181   b  and upper portions of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  are formed of metal. Thus, a large amount of metal is used, so that the heat dissipation effect of the metal can promote cooling of portions heated by a large reset current. In addition, the gate electrode  168   a  and the gate insulating film  162  formed around and below the gate electrode  168   a  and the gate line  168   b  are formed. Accordingly, a gate last process of forming metal gates at the final stage of the heat-treatment step is carried out to form the gate electrodes  168   a  and  170   a  that are metal gates. Thus, both of the metal gate process and the high-temperature process can be successfully performed. 
     The semiconductor device according to the embodiment includes the fin-shaped silicon layers  104  and  105  formed on the semiconductor substrate  101 , the first insulating film  106  formed around the fin-shaped silicon layers  104  and  105 , the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  formed on the fin-shaped silicon layers  104  and  105 , and the gate insulating films  162  and  163  formed around and below the gate electrodes  168   a  and  170   a  and the gate lines  168   b  and  170   b.  The gate electrodes  168   a  and  170   a  and the gate lines  168   b  and  170   b  are formed of metal. The gate lines  168   b  and  170   b  extend in a direction orthogonal to the fin-shaped silicon layers  104  and  105 . The second diffusion layers  143   a  and  143   b  are formed in the fin-shaped silicon layers  104  and  105 . The outer linewidths of the gate electrodes  168   a  and  170   a  are equal to the linewidths of the gate lines  168   b  and  170   b.  The linewidths of the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134  are equal to the linewidths of the fin-shaped silicon layers  104  and  105 . Thus, in the semiconductor device according to the embodiment, the fin-shaped silicon layers  104  and  105 , the first pillar-shaped silicon layers  129 ,  131 ,  132 , and  134 , the gate electrodes  168   a  and  170   a,  and the gate lines  168   b  and  170   b  are formed by self alignment with two masks. As a result, according to the embodiment, the number of steps required to produce the semiconductor device can be reduced. 
     The semiconductor device according to the embodiment includes the contact line  169   b  extending parallel with the gate lines  168   b  and  170   b  and connected to the second diffusion layers  143   a  and  143   b.  Thus, the second diffusion layers  143   a  and  143   b  are connected to each other and the resistance of the source lines can be decreased. As a result, a large reset current can be passed through the source lines. The contact line  169   b  extending parallel with the gate lines  168   b  and  170   b  is preferably disposed such that, for example, a single contact line  169   b  is disposed every 2, 4, 8, 16, 32, or 64 memory cells arranged in a line in the direction in which the bit lines  207  and  208  extend. 
     In the semiconductor device according to the embodiment, the structure including the second pillar-shaped silicon layers  130  and  133  and the contact electrode  169   a  and the contact line  169   b  formed around the second pillar-shaped silicon layers  130  and  133 , is the same as the transistor structure of the memory cell positioned, for example, in the first row and the first column except that the contact electrode  169   a  is connected to the second diffusion layers  143   a  and  143   b . All the source lines constituted by the second diffusion layers  143   a  and  143   b  and extending parallel with the gate lines  168   b  and  170   b  are connected to the contact line  169   b.  As a result, the number of steps required to produce the semiconductor device can be reduced. 
     Note that the present invention encompasses various embodiments and modifications without departing from the broad spirit and scope of the present invention. The above-described embodiments are used to describe examples of the present invention and do not limit the scope of the present invention. 
     For example, a method for producing a semiconductor device in which the p-type (including p +  type) and the n-type (including n +  type) in the above-described embodiment are changed to the opposite conductivity types and a semiconductor device produced by this method are obviously within the technical scope of the present invention.