Patent Publication Number: US-8980682-B2

Title: Methods for fabricating ZnOSe alloys

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. Provisional Application No. 61/778,876, filed on Mar. 13, 2013, which is herein incorporated by reference for all purposes. 
    
    
     FIELD OF THE DISCLOSURE 
     This invention relates to the use of metal oxy-chalcogenide material thin films and methods of forming the same. 
     BACKGROUND 
     Solar cells are photovoltaic (PV) devices that convert light into electrical energy. Solar cells have been developed as clean, renewable energy sources to meet growing demand. Solar cells have been implemented in a wide number of commercial markets including residential rooftops, commercial rooftops, utility-scale PV projects, building integrated PV (BIPV), building applied PV (BAPV), PV in electronic devices, PV in clothing, etc. Currently, crystalline silicon solar cells (both mono-crystalline and multi-crystalline) are the dominant technologies in the market. Crystalline silicon (cSi) solar cells must use a thick substrate (&gt;100 um) of silicon to absorb the sunlight since it has an indirect bandgap and low absorption coefficient. The use of a thick substrate also means that the crystalline silicon solar cells must use high quality material to provide long carrier lifetimes. Therefore, crystalline silicon solar cell technologies lead to increased costs. Thin film photovoltaic (TFPV) solar devices based on amorphous silicon (a-Si), CIGS, cadmium telluride (CdTe), copper zinc tin sulfide (CZTS), etc. provide an opportunity to increase the material utilization since only thin films (&lt;10 um) are generally required. The thin film solar cells may be formed from amorphous, nanocrystalline, micromorph, micro-crystalline, polycrystalline, or mono-crystalline materials. TFPV devices may include a single absorber layer for converting light into electricity, or multiple absorber layers with tuned absorption spectra for converting light into electricity in a tandem configuration. The tandem configuration might be a two-terminal device, or a multi-terminal (e.g. four-terminal) device structure. The multi-terminal device structure might be comprised of one stack of layers on one substrate, or involve different stacks of layers on multiple stacked substrates. 
     TFPV devices provide an opportunity to reduce energy payback time, and reduce water usage for solar panel manufacturing. Typical CdTe and CZTS films have bandgaps of about 1.5 eV and therefore, are an ideal match for the AM1.5G solar spectrum to allow for high efficiencies. The absorption coefficient for CdTe is about 10 5 /cm and the absorption coefficient for CZTS is about 10 4 /cm. CIGS films have bandgaps in the range of 1.0 eV (CIS) to 1.65 eV (CGS) and are also efficient absorbers across the entire solar spectrum. The absorption coefficient for CIGS is also about 10 5 /cm. Among the thin film solar technologies, CIGS has demonstrated the best lab cell efficiency (over 20%) and the best large area module efficiency (&gt;15%). 
     Two general classes of PV absorber films of special interest are formed as CIGS-type IB-IIIA-VIA multinary chalcogenide compounds from Groups IB, IIIA, and VIA of the periodic table or as CZTS-type multinary compounds from Groups IB-IVA-IIB-VIA of the periodic table. Group IB includes Cu, Ag, and Au. Group IIIA includes B, Al, Ga, In, and TI. Group VIA includes O, S, Se, Te, and Po. Additionally, the IB-MA-VIA materials can be doped with dopants from Groups VIII, IIB, IVA, VA, and VIIA of the periodic table. Group VIII includes Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, and Pt. Group IIB includes Zn, Cd, and Hg. Group IVA includes C, Si, Ge, Sn, and Pb. Group VA includes N, P, As, Sb, and Bi. Group VIIA includes F, CI, Br, I, and At. Other potential absorber materials of interest include kesterites like CZTS, cuprous oxide, iron sulfide, tungsten sulfide, calcium nitride, zinc phosphide, barium silicide, etc. 
     TFPV devices can be fabricated at the cell level or the panel level, thus further decreasing the manufacturing costs. As used herein, the cell level is understood to mean an individual unit that can be combined with other units to form a module. The cells may be rigid or flexible. As used herein, the panel level is understood to mean a large TFPV structure that is not composed of smaller units. Generally, the panels are similar in size to the aforementioned modules. For economy of language, the phrase “TFPV device” will be understood to refer to either a solar cell or a panel without distinction. Furthermore, TFPV devices may be fabricated on inexpensive substrates such as glass, plastics, and thin sheets of metal. Examples of suitable substrates comprise float glass, low-iron glass, borosilicate glass, flexible glass, flexible ceramics, specialty glass for high temperature processing, stainless steel, carbon steel, aluminum, cladded foils, copper, polyimide, plastics, etc. Furthermore, the substrates may be processed in many configurations such as single substrate processing, multiple substrate batch processing, in-line continuous processing, roll-to-roll processing, etc. 
     The increasing demand for environmentally friendly, sustainable and renewable energy sources is driving the development of large area, thin film photovoltaic devices. With a long-term goal of providing a significant percentage of global energy demand, there is a concomitant need for Earth-abundant, high conversion efficiency materials for use in photovoltaic devices. A number of Earth abundant, direct-bandgap semiconductor materials now seem to show evidence of the potential for both high efficiency and low cost in Very Large Scale (VLS) production (e.g. greater than 100 gigawatt (GW)), yet their development and characterization remains difficult because of the complexity of the materials systems involved. 
     Among the TFPV technologies, CIGS and CdTe are the two that have reached volume production with greater than 11% stabilized module efficiencies. However, the supply of In, Ga and Te may impact annual production of CIGS and CdTe solar panels. Moreover, price increases and supply constraints in Ga and In could result from the aggregate demand for these materials used in flat panel displays (FPD) and light-emitting diodes (LED) along with CIGS TFPV. Also, there are concerns about the toxicity of Cd throughout the lifecycle of the CdTe TFPV solar modules. Efforts to develop devices that leverage manufacturing and R&amp;D infrastructure related to these TFPV technologies but using more widely available and more environmentally friendly materials should be considered a top priority for research. The knowledge and infrastructure developed around CdTe and CIGS TFPV technologies can be leveraged to allow faster adoption of new TFPV materials systems. 
     The development of TFPV devices exploiting Earth abundant materials represents a daunting challenge in terms of the time-to-commercialization. That same development also suggests an enticing opportunity for breakthrough discoveries. A quaternary system such as CIGS requires management of multiple kinetic pathways, thermodynamic phase equilibrium considerations, defect chemistries, and interfacial control. The vast phase-space to be managed includes process parameters, source material choices, compositions, and overall integration schemes. The complexity of the intrinsically-doped, self-compensating, multinary, polycrystalline, queue-time-sensitive, thin-film absorber (CIGS), and its interfaces to up-, and down-stream processing, combined with the lack of knowledge on a device level to address efficiency losses effectively, makes it a highly empirical material system. The performance of any thin-film, (opto-)electronically-active device is extremely sensitive to its interfaces. Interface engineering for electronically-active devices is highly empirical. Traditional R&amp;D methods are ill-equipped to address such complexity, and the traditionally slow pace of R&amp;D could limit any new material from reaching industrial relevance when having to compete with the incrementally improving performance of already established TFPV fabrication lines, and continuously decreasing panel prices for more traditional cSi PV technologies. 
     Due to the complexity of the material, cell structure, and manufacturing process, both the fundamental scientific understanding and large scale manufacturability are yet to be realized for TFPV devices. As the photovoltaic industry pushes to achieve grid parity, much faster and broader investigation is needed to explore the material, device, and process windows for higher efficiency and a lower cost of manufacturing process. Efficient methods for forming different types of TFPV devices that can be evaluated are necessary. 
     In light of the above, there is a need in the art for an economical method of creating efficient absorber layers. 
     SUMMARY 
     The following summary of the disclosure is included in order to provide a basic understanding of some aspects and features of the invention. This summary is not an extensive overview of the invention and as such it is not intended to particularly identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented below. 
     In some embodiments, methods of forming absorber layers in a TFPV device are provided. Methods are described to provide the formation of metal oxide films and heating the metal oxide films in the presence of a chalcogen to form a metal-oxygen-chalcogen alloy. Methods are described to provide the formation of metal oxide films, forming a layer of elemental chalcogen on the metal oxide film, and heating the stack to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide film includes zinc oxide and the chalcogen includes selenium. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features of embodiments of the invention can be understood in detail, a more particular description of embodiments of the invention, briefly summarized above, may be had by reference to the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
         FIG. 1  is a schematic diagram for implementing combinatorial processing and evaluation. 
         FIG. 2  is a schematic diagram for illustrating various process sequences using combinatorial processing and evaluation. 
         FIG. 3  illustrates a schematic diagram of a simple substrate TFPV stack according to an embodiment described herein. 
         FIG. 4  illustrates a schematic diagram of a simple n-superstrate TFPV stack according to an embodiment described herein. 
         FIG. 5  illustrates a schematic diagram of a simple p-superstrate TFPV stack according to an embodiment described herein. 
         FIG. 6  presents a flow chart for methods for forming absorbers according to some embodiments. 
         FIG. 7  presents a flow chart for methods for forming absorbers according to some embodiments. 
         FIG. 8  presents data for optical transmittance (%) versus wavelength for a zinc oxide film both before and after selenization according to some embodiments. 
         FIG. 9  presents data for XRF intensity (a.u.) versus energy for a zinc oxide film both before and after selenization according to some embodiments. 
         FIG. 10  presents data for XRD intensity (a.u.) versus 2-theta angle (degrees) for a zinc oxide film both before and after selenization according to some embodiments. 
     
    
    
     For clarity, identical reference numbers have been used, where applicable, to designate identical elements that are common between figures. It is contemplated that features of one embodiment may be incorporated in other embodiments without further recitation. 
     DETAILED DESCRIPTION 
     A detailed description of one or more embodiments is provided below along with accompanying figures. The detailed description is provided in connection with such embodiments, but is not limited to any particular example. The scope is limited only by the claims and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided for the purpose of example and the described techniques may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the embodiments has not been described in detail to avoid unnecessarily obscuring the description. 
     It must be noted that as used herein and in the claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a layer” includes two or more layers, and so forth. 
     Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range, and any other stated or intervening value in that stated range, is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges, and are also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention. Where the modifier “about” or “approximately” is used, the stated quantity can vary by up to 10%. Where the modifier “substantially equal to” or “substantially the same” is used, the two quantities may vary from each other by no more than 5%. 
     The term “horizontal” as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term “vertical” will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above”, “below”, “bottom”, “top”, “side” (e.g. sidewall), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact between the elements. The term “above” will allow for intervening elements. 
     As used herein, the notation “(IIIA)” will be understood to represent the sum of the concentrations of all Group-IIIA elements. This notation will be used herein in calculations of the composition ratios of various elements. This notation will be understood to extend to each of the other Groups of the periodic table respectively (e.g. “(IA)”, “(IIA)”, “(IVA)”, “(VIA)”, “(IB)”, “(IIB)”, etc.). 
     As used herein, the notation “Zn—O—Se” and “Zn(O, Se)” will be understood to include a material containing these elements in any ratio. The notation is extendable to other materials and other elemental combinations. 
     As used herein, the notation “Zn x O y Se z ” will be understood to include a material containing these elements in a specific ratio given by x, y, and z (e.g. Zn 50 O 50  contains 50 atomic % Zn and 50 atomic % O). The notation is extendable to other materials and other elemental combinations. 
     As used herein, the notation “(Ag,Cu) x (In,Ga) y (Se,S,Te) z ” will be understood to include a material containing a total amount of Group-IB elements (i.e. Ag plus Cu, etc.) in a ratio given by “x”, a total amount of Group-IIIA elements (i.e. In plus Ga), etc. in a ratio given by “y”, and a total amount of Group-VIA elements (i.e. Se plus S plus Te, etc.) in a ratio given by “z”. The notation is extendable to other materials and other elemental combinations. 
     As used herein, “metal chalcogenide” or “chalcogenide” will be understood to represent the entire range of related compounds denoted by “MX” where M represents one or more metal elements and X represents one or more of the chalcogen elements (e.g. O, S, Se, or Te). 
     As used herein, “chalcogenize” and “chalcogenization” will be understood to represent the process by which one or more metals are converted to chalcogenide compounds by exposing the one or more metals to a chalcogen (e.g. O, S, Se, or Te) at elevated temperature (e.g. between 100 C and 700 C). Specifically, “selenization” will be understood to represent the process by which one or more metals are converted to selenide compounds by exposing the one or more metals to a Se source at elevated temperature (e.g. between 100 C and 700 C). Specifically, “sulfurization” will be understood to represent the process by which one or more metals are converted to sulfide compounds by exposing the one or more metals to a S source at elevated temperature (e.g. between 100 C and 700 C). In addition, “chalcogenize” or “chalcogenization” will be understood to represent the process by which a metal precursor is either partially or completely converted to the final multinary chalcogenide compound(s). Similarly, “chalcogenize” or “chalcogenization” will be understood to represent the process by which a precursor containing one or more chalcogenide materials with/without one or more elemental or alloy metals is converted to one or more dense, polycrystalline, desired multinary chalcogenide compound(s). It should be understood that the majority of the final film contains the desired multinary chalcogenide compound(s), yet a minority of the material might not be converted to the desired multinary chalcogenide compound(s). 
     As used herein, the terms “film” and “layer” will be understood to represent a portion of a stack. They will be understood to cover both a single layer as well as a multilayered structure (i.e. a nanolaminate). As used herein, these terms will be used synonymously and will be considered equivalent. 
     As used herein, “substrate configuration” will be understood to describe cases wherein the TFPV stack is built sequentially on top of a substrate and the light is assumed to be incident upon the top of the TFPV stack. As used herein, an “n-substrate”configuration will be used to denote that the n-type layer (i.e. buffer layer) is closest to the incident light. The n-substrate configuration is the most common. As used herein, a “p-substrate” configuration will be used to denote that the p-type layer (i.e. absorber layer) is closest to the incident light. 
     As used herein, “superstrate configuration” will be understood to describe cases wherein the substrate faces the incident sunlight. The convention will be used wherein light is assumed to be incident upon the substrate. As used herein, a “n-superstrate” configuration will be used to denote that the n-type layer (i.e. buffer layer) is closest to the incident light. As used herein, a “p-superstrate” configuration will be used to denote that the p-type layer (i.e. absorber layer) is closest to the incident light. 
     As used herein, “substrate” will be understood to generally be one of float glass, low-iron glass, borosilicate glass, flexible glass, specialty glass for high temperature processing, stainless steel, carbon steel, aluminum, copper, titanium, molybdenum, polyimide, plastics, cladded metal foils, etc. Furthermore, the substrates may be processed in many configurations such as single substrate processing, multiple substrate batch processing, in-line continuous processing, roll-to-roll processing, etc. in all of the methods and examples described herein. 
     As used herein, “precursor layer”, “precursor material”, “metal precursor layer”, “metal precursor material”, etc. will be understood to be equivalent and be understood to refer to a metal, metal alloy, metal chalcogenide, etc. layer and/or material that is first deposited and will ultimately become the absorber layer of the TFPV device after full chalcogenization and/or further processing. 
     As used herein, “absorber layer”, “absorber material”, etc. will be understood to be equivalent and be understood to refer to a layer and/or material that are responsible for the charge generation in the TFPV device after full chalcogenization and/or further processing. 
     As used herein, the notations “Al:ZnO” and “ZnO:Al” will be understood to be equivalent and will describe a material wherein the base material is the metal oxide and the element separated by the colon “:” is considered a dopant. In this example, Al is a dopant in a base material of zinc oxide. The notation is extendable to other materials and other elemental combinations. 
     In various FIGs. below, a TFPV material stack is illustrated using a simple planar structure. Those skilled in the art will appreciate that the description and teachings to follow can be readily applied to any simple or complex TFPV solar cell structure, (e.g. a stack with (non-)conformal non-planar layers for optimized photon management). The drawings are for illustrative purposes only and do not limit the application of the present invention. 
     The efficiency of TFPV devices depends on many properties of the absorber layer and the buffer layer such as crystallinity, grain size, composition uniformity, density, defect concentration, doping level, surface roughness, etc. 
     The manufacture of TFPV devices entails the integration and sequencing of many unit processing steps. As an example, TFPV manufacturing typically includes a series of processing steps such as cleaning, surface preparation, deposition, patterning, etching, thermal annealing, and other related unit processing steps. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as efficiency, power production, and reliability. 
     As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as TFPV devices. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing. 
     Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006, and U.S. Pat. No. 7,947,531 filed on Aug. 28, 2009, the entireties of which are all herein incorporated by reference. Systems and methods for HPC processing are further described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/419,174 filed on May 18, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/674,132 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005, and U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005, the entireties of which are all herein incorporated by reference. 
     HPC processing techniques have been successfully adapted to wet chemical processing such as etching, texturing, polishing, cleaning, etc. HPC processing techniques have also been successfully adapted to deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD). 
       FIG. 1  illustrates a schematic diagram,  100 , for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening. The schematic diagram,  100 , illustrates that the relative number of combinatorial processes run with a group of substrates decreases as certain materials and/or processes are selected. Generally, combinatorial processing includes performing a large number of processes during a primary screen, selecting promising candidates from those processes, performing the selected processing during a secondary screen, selecting promising candidates from the secondary screen for a tertiary screen, and so on. In addition, feedback from later stages to earlier stages can be used to refine the success criteria and provide better screening results. 
     For example, thousands of materials are evaluated during a materials discovery stage,  102 . Materials discovery stage,  102 , is also known as a primary screening stage performed using primary screening techniques. Primary screening techniques may include dividing substrates into coupons and depositing materials using varied processes. The materials are then evaluated, and promising candidates are advanced to the secondary screen, or materials and process development stage,  104 . Evaluation of the materials is performed using metrology tools such as electronic testers and imaging tools (i.e., microscopes). 
     The materials and process development stage,  104 , may evaluate hundreds of materials (i.e., a magnitude smaller than the primary stage) and may focus on the processes used to deposit or develop those materials. Promising materials and processes are again selected, and advanced to the tertiary screen or process integration stage,  106 , where tens of materials and/or processes and combinations are evaluated. The tertiary screen or process integration stage,  106 , may focus on integrating the selected processes and materials with other processes and materials. 
     The most promising materials and processes from the tertiary screen are advanced to device qualification,  108 . In device qualification, the materials and processes selected are evaluated for high volume manufacturing, which normally is conducted on full substrates within production tools, but need not be conducted in such a manner. The results are evaluated to determine the efficacy of the selected materials and processes. If successful, the use of the screened materials and processes can proceed to pilot manufacturing,  110 . 
     The schematic diagram,  100 , is an example of various techniques that may be used to evaluate and select materials and processes for the development of new materials and processes. The descriptions of primary, secondary, etc. screening and the various stages,  102 - 110 , are arbitrary and the stages may overlap, occur out of sequence, be described and be performed in many other ways. 
       FIG. 2  is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site isolated processing and/or conventional processing in accordance with one embodiment of the invention. In one embodiment, the substrate is initially processed using conventional process N. In one exemplary embodiment, the substrate is then processed using site isolated process N+1. During site isolated processing, an HPC module may be used, such as the HPC module described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006. The substrate can then be processed using site isolated process N+2, and thereafter processed using conventional process N+3. Testing is performed and the results are evaluated. The testing can include physical, chemical, acoustic, magnetic, electrical, optical, etc. tests. From this evaluation, a particular process from the various site isolated processes (e.g. from steps N+1 and N+2) may be selected and fixed so that additional combinatorial process sequence integration may be performed using site isolated processing for either process N or N+3. For example, a next process sequence can include processing the substrate using site isolated process N, conventional processing for processes N+1, N+2, and N+3, with testing performed thereafter. 
     It will be appreciated that various other combinations of conventional and combinatorial processes can be included in the processing sequence with regard to  FIG. 2 . That is, the combinatorial process sequence integration can be applied to any desired segments and/or portions of an overall process flow. Characterization, including physical, chemical, acoustic, magnetic, electrical, optical, etc. testing, can be performed after each process operation, and/or series of process operations within the process flow as desired. The feedback provided by the testing is used to select certain materials, processes, process conditions, and process sequences and eliminate others. Furthermore, the above flows can be applied to entire monolithic substrates, or portions of monolithic substrates such as coupons. 
     Under combinatorial processing operations the processing conditions at different regions can be controlled independently. Consequently, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, deposition order of process materials, process sequence steps, hardware details, etc., can be varied from region to region on the substrate. Thus, for example, when exploring materials, a processing material delivered to a first and second region can be the same or different. If the processing material delivered to the first region is the same as the processing material delivered to the second region, this processing material can be offered to the first and second regions on the substrate at different concentrations. In addition, the material can be deposited under different processing parameters. Parameters which can be varied include, but are not limited to, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, atmospheres in which the processes are conducted, an order in which materials are deposited, hardware details of the gas distribution assembly, etc. It will be appreciated that these process parameters are exemplary and not meant to be an exhaustive list as other process parameters commonly used in semiconductor manufacturing may be varied. 
     Simple substrate and superstrate configurations of CIGS-type TFPV devices will be described with respect to  FIGS. 3-5 . The purpose is to introduce the basic chalcogenide-based TFPV device stacks as well as discuss common materials and techniques used in their manufacture. Those skilled in the art will understand that many of these materials and techniques may be applied to the embodiments of the present disclosure. 
       FIG. 3  illustrates a schematic diagram of a simple TFPV device stack in the substrate configuration consistent with some embodiments of the present invention. The convention will be used wherein light is assumed to be incident upon the top of the material stack in the substrate configuration as illustrated. This generic diagram would be typical of either a CIGS TFPV device or a CZTS TFPV device. The difference being the choice of materials for the absorber layer. A back contact layer,  304 , is formed above a substrate,  302 . Examples of suitable substrates comprise float glass, low-iron glass, borosilicate glass, flexible glass, specialty glass for high temperature processing, stainless steel, carbon steel, aluminum, copper, titanium, molybdenum, polyimide, plastics, cladded metal foils, etc. Furthermore, the substrates may be processed in many configurations such as single substrate processing, multiple substrate batch processing, in-line continuous processing, in-line “stop and soak” processing, roll-to-roll processing, etc. As used herein, the phrase “back contact” will be understood to be the primary current conductor layer situated between the substrate and the absorber layer in a substrate configuration TFPV device. An example of a common back contact layer material is Mo for CIGS and CZTS. Other types of TFPV devices use different materials for the back contact. As an example, Cu alloys such as Cu/Au, Cu/graphite, Cu/Mo, Cu:ZnTe, etc. are typically used for CdTe TFPV devices and TCO materials such as ZnO, ITO, SnO 2 :F, etc. are typically used for a-Si TFPV devices. The back contact layer may be formed by any number of deposition technologies. Examples of suitable deposition technologies comprise PVD (sputtering), evaporation, chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, printing, wet coating, etc. The thickness of the back contact layer is typically between 0.3 um and 1.0 um. The back contact layer has a number of requirements such as high conductivity, good ohmic contact to the absorber layer, ease of bonding to tabs for external connectivity, ease of scribing or other removal, good thermo-mechanical stability, and chemical resistance during subsequent processing, among others. 
     Optionally, a diffusion barrier and/or adhesion-promotion layer (not shown) may be formed between the substrate and the back contact layer. When implemented, the diffusion barrier layer stops the diffusion of impurities from the substrate into the back contact layer, or alternatively, stops the diffusion and reaction of the back contact material with the substrate. Examples of common diffusion barrier and/or adhesion-promotion layers comprise chromium, vanadium, tungsten, nitrides such as tantalum nitride, tungsten nitride, titanium nitride, silicon nitride, zirconium nitride, hafnium nitride, oxy-nitrides such as tantalum oxy-nitride, tungsten oxy-nitride, titanium oxy-nitride, silicon oxy-nitride, zirconium oxy-nitride, hafnium oxy-nitride, oxides such as aluminum oxide, silicon oxide, carbides such as silicon carbide, binary and/or multinary compounds of tungsten, titanium, molybdenum, chromium, vanadium, tantalum, hafnium, zirconium, and/or niobium with/without the inclusion of nitrogen and/or oxygen. The diffusion barrier layer may be formed, partially or completely, from any well-known technique such as sputtering, ALD, CVD, evaporation, wet methods such as printing or spraying of inks, screen printing, inkjet printing, slot die coating, gravure printing, wet chemical depositions, or from sol-gel methods such as the coating, drying, and firing of polysilazanes. 
     A p-type absorber layer,  306 , of CIGS (CZTS or other material) is then deposited on top of the back contact layer. The absorber layer may be formed, partially or completely, using a variety of techniques such as PVD (sputtering), co-evaporation, in-line processing, plating, printing or spraying of inks, screen printing, inkjet printing, slot die coating, gravure printing, wet chemical depositions, CVD, etc. Advantageously, a small amount of Na is contained in the absorber present during the absorber growth. The Na may be added by out-diffusion from the SLG substrate or may be purposely added in the form of Na 2 Se NaF, sodium alloys of In and/or Ga, or another Na source, prior to, during, or after the deposition and/or growth of the absorber layer. Optionally, precursor and/or the absorber layer undergoes a selenization process after formation to convert the precursor to CIGS into a high-quality CIGS semiconductor film. The selenization process involves the exposure of the precursor and/or absorber layer to H 2 Se, H 2 S, Se vapor, S vapor, or diethylselenide (DESe) at temperatures most typically between 300 C and 700 C. It should be noted that the precursor to CIGS might already contain a chalcogen source (e.g. Se), either as a separate layer, or incorporated into the bulk of the precursor layer. The precursor film can be a stack of layers, or one layer. The precursor layer can be dense, or porous. The precursor film typically contains Cu, In, and Ga. The precursor layer is most commonly deposited by sputtering from e.g. binary copper-gallium and Indium sputter targets. Nevertheless, plating and printing to deposit the metal precursor film containing Cu, In, and/or Ga are used as well. During the selenization process, a layer of Mo(S,Se) 2  (not shown) forms at the back contact/absorber layer interface and forms a fairly good ohmic contact between the two layers. Alternatively, a layer of Mo(S,Se) 2  (not shown) can be deposited at the back contact/absorber layer interface using a variety of well known techniques such as PVD (sputtering), CBD, ALD, plating, etc. The thickness of the absorber layer is typically between 1.0 um and 3.0 um. The performance of the absorber layer is sensitive to materials properties such as crystallinity, grain size, surface roughness, composition, defect concentration, etc. as well as processing parameters such as temperature, deposition rate, thermal treatments, etc. 
     An n-type buffer layer,  308 , is then deposited on top of the absorber layer. Examples of suitable n-type buffer layers comprise CdS, ZnS, In 2 S 3 , In 2 (S,Se) 3 , CdZnS, ZnO, Zn(O,S), (Zn,Mg)O, etc. CdS is the material most often used as the n-type buffer layer in CIGS or CZTS TFPV devices. The buffer layer may be deposited using chemical bath deposition (CBD), chemical surface deposition (CSD), PVD (sputtering), printing, plating, ALD, Ion-Layer-Gas-Reaction (ILGAR), ultrasonic spraying, or evaporation. The thickness of the buffer layer is typically between 30 nm and 100 nm. The performance of the buffer layer is sensitive to materials properties such as crystallinity, grain size, surface roughness, composition, defect concentration, etc. as well as processing parameters such as temperature, deposition rate, thermal treatments, etc. 
     Optionally, an intrinsic ZnO (iZnO) layer,  310 , is then formed on top of the buffer layer. The iZnO layer is a high resistivity material and forms part of the transparent conductive oxide (TCO) stack that serves as part of the front contact structure. The TCO stack is formed from transparent conductive metal oxide materials and collects charge across the face of the TFPV solar cell and conducts the charge to tabs used to connect the solar cell to external loads. The iZnO layer makes the TFPV solar cell less sensitive to lateral non-uniformities caused by differences in composition or defect concentration in the absorber and/or buffer layers. The iZnO layer is typically between about 0 nm and 150 nm in thickness. The iZnO layer is typically formed using a (reactive) PVD (sputtering) technique or CVD technique, but can be deposited by plating or printing as well. A low resistivity top TCO layer,  312 , (examples include Al:ZnO (AZO), InSnO (ITO), InZnO, B:ZnO, Ga:ZnO, F:ZnO, F:SnO 2 , etc.) is formed on top of the iZnO layer. The top TCO layer is typically between 0.25 um and 1.0 um in thickness. The top TCO layer is typically formed using a (reactive) PVD (sputtering) technique or CVD technique. Optionally, the transparent top electrode can be printed or wet-coated from (e.g. silver) nano-wires, carbon nanotubes, and the like. 
       FIG. 4  illustrates a simple CIGS TFPV device material stack,  400 , consistent with some embodiments of the present invention. The CIGS TFPV device illustrated in  FIG. 4  is shown in a superstrate configuration wherein the glass substrate faces the incident sunlight. The convention will be used wherein light is assumed to be incident upon the substrate and material stack as illustrated. As used herein, this configuration will be labeled an “n-superstrate” configuration to denote that the n-type layer (i.e. buffer layer) is closest to the incident light. This label is to distinguish the configuration from an alternate configuration described with respect to  FIG. 5  below. The formation of the CIGS TFPV device will be described starting with the substrate. A similar structure and similar method would also be applicable to the formation of a CZTS TFPV solar cell fabricated with a superstrate configuration. Examples of suitable substrates comprise float glass, low-iron glass, borosilicate glass, flexible glass, specialty glass for high temperature processing, polyimide, plastics, etc. Furthermore, the substrates may be processed in many configurations such as single substrate processing, multiple substrate batch processing, in-line continuous processing, roll-to-roll processing, etc. 
     A low resistivity bottom TCO front contact layer,  404 , (examples include Al:ZnO (AZO), InSnO (ITO), InZnO, B:ZnO, Ga:ZnO, F:ZnO, F:SnO 2 , etc.) is formed on top of the substrate,  402 . As used herein, the phrase “front contact” will be understood to be the primary current conductor layer situated between the substrate and the buffer layer in a superstrate configuration TFPV device. The bottom TCO layer is typically between 0.3 um and 2.0 um in thickness. The bottom TCO layer is typically formed using a reactive PVD (sputtering) technique or CVD technique. 
     Optionally, a diffusion barrier and/or adhesion-promotion layer (not shown) may be formed between the substrate,  402 , and the front contact layer,  404 . When implemented, the diffusion barrier layer stops the diffusion of impurities from the substrate into the TCO, or alternatively, stops the diffusion and reaction of the TCO material and above layers with the substrate. Examples of common diffusion barrier and/or adhesion-promotion layers comprise chromium, vanadium, tungsten, nitrides such as tantalum nitride, tungsten nitride, titanium nitride, silicon nitride, zirconium nitride, hafnium nitride, oxy-nitrides such as tantalum oxy-nitride, tungsten oxy-nitride, titanium oxy-nitride, silicon oxy-nitride, zirconium oxy-nitride, hafnium oxy-nitride, oxides such as aluminum oxide, silicon oxide, carbides such as silicon carbide, binary and/or multinary compounds of tungsten, titanium, molybdenum, chromium, vanadium, tantalum, hafnium, zirconium, and/or niobium with/without the inclusion of nitrogen and/or oxygen. It should be understood that the diffusion barrier layer composition and thickness are optimized for optical transparency as necessary for the superstrate configuration. The diffusion barrier layer may be formed from any well known technique such as sputtering, ALD, CVD, evaporation, wet methods such as printing or spraying of inks, screen printing, inkjet printing, slot die coating, gravure printing, wet chemical depositions, or from sol-gel methods, such as the coating, drying, and firing of polysilazanes. 
     An intrinsic iZnO layer,  406 , is then formed on top of the TCO layer. The iZnO layer is a high resistivity material and forms part of the transparent conductive oxide (TCO) stack that serves as part of the front contact structure. The iZnO layer makes the TFPV device less sensitive to lateral non-uniformities caused by differences in composition or defect concentration in the absorber and/or buffer layers. The iZnO layer is typically between about 0 nm and 150 nm in thickness. The iZnO layer is typically formed using a reactive PVD (sputtering) technique or CVD technique. 
     An n-type buffer layer,  408 , is then deposited on top of the iZnO layer,  406 . Examples of suitable n-type buffer layers comprise CdS, ZnS, In 2 S 3 , In 2 (S,Se) 3 , CdZnS, ZnO, Zn(O,S), (Zn,Mg)O, etc. CdS is the material most often used as the n-type buffer layer in CIGS or CZTS TFPV devices. The buffer layer may be deposited using chemical bath deposition (CBD), chemical surface deposition (CSD), PVD (sputtering), printing, plating, ALD, Ion-Layer-Gas-Reaction (ILGAR), ultrasonic spraying, or evaporation. The thickness of the buffer layer is typically between 30 nm and 100 nm. The performance of the buffer layer is sensitive to materials properties such as crystallinity, grain size, surface roughness, composition, defect concentration, etc. as well as processing parameters such as temperature, deposition rate, thermal treatments, etc. 
     A p-type absorber layer,  410 , of CIGS (CZTS or other IB-IIIA-VIA material) is then deposited on top of the buffer layer. The absorber layer may be formed, partially or completely, using a variety of techniques such as PVD (sputtering), co-evaporation, in-line processing, plating, printing or spraying of inks, screen printing, inkjet printing, slot die coating, gravure printing, wet chemical depositions, CVD, etc. Advantageously, the absorber layer is deficient in Cu. The Cu deficiency may be controlled by managing the deposition conditions. Advantageously, a small amount of Na is present during the growth of the absorber. The Na may be purposely added in the form of Na 2 Se or another Na source, prior to, during, or after the deposition and/or growth of the absorber layer. Optionally, the precursor and/or absorber layer undergoes a selenization process after formation to convert the precursor to CIGS into a high-quality CIGS semiconductor film. The selenization process involves the exposure of the precursor and/or absorber layer to H 2 Se, H 2 S, Se vapor, S vapor, or diethylselenide (DESe) at temperatures most typically between 300 C and 700 C. It should be noted that the precursor to CIGS might already contain a chalcogen source (e.g. Se), either as a separate layer, or incorporated into the bulk of the precursor layer. The precursor film can be a stack of layers, or one layer. The precursor layer can be dense, or porous. The precursor film typically contains Cu, In, and Ga. The precursor layer is most commonly deposited by sputtering from e.g. binary Cu—Ga and In sputter targets. Nevertheless, plating and printing to deposit the metal precursor film containing Cu, In, and/or Ga are used as well. During subsequent processing, a layer of Mo(S,Se) 2  (not shown) is formed at the back contact/absorber layer interface and forms a fairly good ohmic contact between the two layers. The thickness of the absorber layer is typically between 1.0 um and 3.0 um. The performance of the absorber layer is sensitive to materials properties such as crystallinity, grain size, surface roughness, composition, defect concentration, etc. as well as processing parameters such as temperature, deposition rate, thermal treatments, etc. 
     A back contact layer,  412 , is formed on absorber layer,  410 . An example of a common back contact layer material is Mo for CIGS and CZTS. The back contact layer may be formed by any number of deposition technologies. Examples of suitable deposition technologies comprise PVD (sputtering), evaporation, chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, etc. The thickness of the back contact layer is typically between 0.3 um and 1.0 um. The back contact layer has a number of requirements such as high conductivity, good ohmic contact to the absorber layer, ease of bonding to tabs for external connectivity, ease of scribing or other removal, good thermo-mechanical stability, and chemical resistance during subsequent processing, among others. Other types of TFPV devices use different materials for the back contact. As an example, Cu alloys such as Cu/Au, Cu/graphite, Cu/Mo, Cu:ZnTe, etc. are typically used for CdTe TFPV devices and TCO materials such as ZnO, ITO, SnO 2 :F, etc. are typically used for a-Si TFPV devices. 
       FIG. 5  illustrates a simple CIGS TFPV device material stack,  500 , consistent with some embodiments of the present invention. The CIGS TFPV device illustrated in  FIG. 5  is shown in a superstrate configuration wherein the glass substrate faces the incident sunlight. The convention will be used wherein light is assumed to be incident upon the substrate and material stack as illustrated. As used herein, this configuration will be labeled a “p-superstrate” configuration to denote that the p-type layer (i.e. absorber layer) is closest to the incident light. This label is to distinguish the configuration from the alternate configuration described with respect to  FIG. 4  previously. The formation of the CIGS TFPV device will be described starting with the substrate. A similar structure and similar method would also be applicable to the formation of a CZTS TFPV solar cell fabricated with a superstrate configuration. Examples of suitable substrates comprise float glass, low-iron glass, borosilicate glass, flexible glass, specialty glass for high temperature processing, polyimide, plastics, etc. Furthermore, the substrates may be processed in many configurations such as single substrate processing, multiple substrate batch processing, in-line continuous processing, roll-to-roll processing, etc. 
     A low resistivity bottom TCO front contact layer,  504 , is formed on top of the substrate,  502 . As used herein, the phrase “front contact” will be understood to be the primary current conductor layer situated between the substrate and the absorber layer in a superstrate configuration TFPV device. The bottom TCO layer is typically between 0.3 um and 2.0 um in thickness. The bottom TCO layer is typically formed using a reactive PVD (sputtering) technique or CVD technique. The TCO can be a p-type TCO, (e.g. ternary-based oxide in the family of Co 3 O 4 -based spinels, like Co 2 ZnO 4  and Co 2 NiO 4 ). Nevertheless, it should be understood that an n-type TCO with an additional layer (e.g. of MoSe 2 ) between the TCO and the absorber can be used as well. Furthermore, the TCO might be a bi- or multi-layer of an n-type TCO in contact with the substrate, followed by an ultrathin metal layer, (e.g. like Ag), followed by a thin p-type TCO in contact with the absorber layer, with/without an additional MoSe 2  layer between the p-type TCO and the absorber layer. 
     Optionally, a diffusion barrier and/or adhesion-promotion layer (not shown) may be formed between the substrate,  502 , and the front contact layer,  504 . When implemented, the diffusion barrier and/or adhesion-promotion layer stops the diffusion of impurities from the substrate into the TCO, or alternatively, stops the diffusion and reaction of the TCO material and above layers with the substrate. Examples of common diffusion barrier and/or adhesion-promotion layers comprise chromium, vanadium, tungsten, nitrides such as tantalum nitride, tungsten nitride, titanium nitride, silicon nitride, zirconium nitride, hafnium nitride, oxy-nitrides such as tantalum oxy-nitride, tungsten oxy-nitride, titanium oxy-nitride, silicon oxy-nitride, zirconium oxy-nitride, hafnium oxy-nitride, oxides such as aluminum oxide, silicon oxide, carbides such as silicon carbide, binary and/or multinary compounds of tungsten, titanium, molybdenum, chromium, vanadium, tantalum, hafnium, zirconium, and/or niobium with/without the inclusion of nitrogen and/or oxygen. It should be understood that the diffusion barrier and/or adhesion-promotion layer composition and thickness are optimized for optical transparency as necessary for the superstrate configuration. The diffusion barrier and/or adhesion-promotion layer may be formed from any well known technique such as sputtering, ALD, CVD, evaporation, wet methods such as printing or spraying of inks, screen printing, inkjet printing, slot die coating, gravure printing, wet chemical depositions, or from sol-gel methods such as the coating, drying, and firing of polysilazanes. 
     A p-type absorber layer,  506 , of CIGS (CZTS or other absorber material) is then deposited on top of the front contact layer. The absorber layer may be formed, partially, or completely, using a variety of techniques such as PVD (sputtering), co-evaporation, in-line processing, plating, printing or spraying of inks, screen printing, inkjet printing, slot die coating, gravure printing, wet chemical depositions, CVD, etc. Advantageously, the absorber layer is deficient in Cu. The Cu deficiency may be controlled by managing the deposition conditions. Advantageously, a small amount of Na is present during the growth of the absorber. The Na may be purposely added in the form of Na 2 Se or another Na source, prior to, during, or after the deposition of the precursor and/or absorber layer. Typically, the precursor and/or absorber layer undergoes a chalcogenization (e.g. selenization) process after formation to convert the precursor to CIGS into a high-quality CIGS semiconductor film. The chalcogenization process involves the exposure of the precursor and/or absorber layer to H 2 Se, H 2 S, Se vapor, S vapor, or diethylselenide (DESe) at temperatures most typically between 300 C and 700 C. It should be noted that the precursor to CIGS might already contain a chalcogen source (e.g. Se), either as a separate layer, or incorporated into the bulk of the precursor layer. The precursor film can be a stack of layers, or one layer. The precursor layer can be dense, or porous. The precursor film typically contains Cu, In, and Ga. The precursor layer is most commonly deposited by sputtering from e.g. binary copper-gallium and Indium sputter targets. Nevertheless, plating and printing to deposit the metal precursor film containing Cu, In, and/or Ga are used as well. The thickness of the absorber layer is typically between 1.0 um and 3.0 um. The performance of the absorber layer is sensitive to materials properties such as crystallinity, grain size, surface roughness, composition, defect concentration, etc. as well as processing parameters such as temperature, deposition rate, thermal treatments, etc. 
     An n-type buffer layer,  508 , is then deposited on top of the absorber layer. Examples of suitable n-type buffer layers comprise CdS, ZnS, In 2 S 3 , In 2 (S,Se) 3 , CdZnS, ZnO, Zn(O,S), (Zn,Mg)O, etc. CdS is the material most often used as the n-type buffer layer in CIGS or CZTS TFPV devices. The buffer layer may be deposited using chemical bath deposition (CBD), chemical surface deposition (CSD), PVD (sputtering), printing, plating, ALD, Ion-Layer-Gas-Reaction (ILGAR), ultrasonic spraying, or evaporation. The thickness of the buffer layer is typically between 30 nm and 100 nm. The performance of the buffer layer is sensitive to materials properties such as crystallinity, grain size, surface roughness, composition, defect concentration, etc. as well as processing parameters such as temperature, deposition rate, thermal treatments, etc. 
     An intrinsic iZnO layer,  510 , is then formed on top of the buffer layer. The iZnO layer is a high resistivity material and forms part of the back contact structure. The iZnO layer makes the TFPV device less sensitive to lateral non-uniformities caused by differences in composition or defect concentration in the absorber and/or buffer layers. The iZnO layer is typically between about 0 nm and 150 nm in thickness. The iZnO layer is typically formed using a reactive PVD (sputtering) technique or CVD technique. 
     A back contact layer,  512 , is formed on intrinsic iZnO layer,  510 . An example of a suitable back contact layer material is a thin n-type TCO followed by Ni and/or Al. The back contact layer may be formed by any number of deposition technologies. Examples of suitable deposition technologies comprise PVD (sputtering), evaporation, chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, etc. The thickness of the back contact layer is typically between 0.3 um and 1.0 um. The back contact layer has a number of requirements such as high conductivity, good ohmic contact to the absorber layer, ease of bonding to tabs for external connectivity, ease of scribing or other removal, good thermo-mechanical stability, and chemical resistance during subsequent processing, among others. Other types of TFPV devices use different materials for the back contact. As an example, Cu alloys such as Cu/Au, Cu/graphite, Cu/Mo, Cu:ZnTe, etc. are typically used for CdTe TFPV devices and TCO materials such as ZnO, ITO, SnO 2 :F, etc. are typically used for a-Si TFPV devices. 
     The film stack described above is just one example of a film stack that can be used for TFPV devices. As an example, another substrate film stack (i.e. similar configuration as  FIG. 3 ) might be: substrate/AZO/Mo/“absorber”/CdS/iZnO/AZO. As an example, another p-superstrate film stack (i.e. similar configuration as  FIG. 5 ) might be: substrate/barrier/ZnO:Al/Mo/“absorber”/CdS/iZnO/ZnO:Al/Al. The detailed film stack configuration is not meant to be limiting, but simply serves as an example of the implementation of embodiments of the present disclosure. 
     The efficiency of a TFPV device depends on the bandgap of the absorber material. The goal is to have the bandgap tuned to the energy range of the photons incident on the device. The theoretical upper limit for a single p-n junction solar cell has been calculated to be about 33 to 34%. The peak in the efficiency occurs for values of the bandgap between 1.0 eV and 1.5 eV, and more specifically between 1.3 eV and 1.5 eV. 
     A wide variety of materials have been considered as candidates for absorbers used in TFPV devices. Metal oxide materials would be desirable due to their stability and abundant availability. However, metal oxide materials generally have a wide band gap and therefore, are poor absorbers in the visible range. This limits the efficiency of devices formed using metal oxides as absorbers. 
     Substituting the oxygen in the metal oxide with an isovalent anion (e.g. S, Se, or Te), can alter the band gap of the resulting alloy. As an example, zinc oxide has a band gap of about 3.3 eV while zinc selenide has a band gap of about 2.7 eV. However, work by Mayer et. al. (Applied Physics Letters, 97, 022104 (2010)), indicates that an alloy wherein 52 atomic % of the oxygen has been replaced by selenium would have a band gap of about 1.63 eV. Therefore, isovalent anions (e.g. S, Se, or Te), can be used to affect the band gap of metal oxides and improve their efficiency for absorption in the visible portion of the spectrum. 
       FIG. 6  presents a flow chart for methods,  600 , for forming absorbers according to some embodiments. In operation  602 , a metal oxide film is formed above a substrate. In some embodiments, the metal oxide film includes zinc oxide. The metal oxide film may be formed using any suitable deposition technique. Examples of suitable deposition techniques include PVD (e.g. sputtering), reactive sputtering (e.g. in the presence of a chalcogen), evaporation, CVD, spray coating, sol-gel techniques, printing of metal oxy-chalcogenide particles (and/or metal chalcogenide particles) followed by sintering, electroplating of metal oxide and/or metal chacogenide layers, or other known deposition techniques. In operation  604 , the metal oxide film is heated in the presence of a chalcogen (e.g. S, Se, or Te). The heating may occur in a batch furnace, an in-line furnace, or a rapid thermal process chamber. The chalcogen may be introduced as a gas (e.g. H 2 S, H 2 Se, H 2 Te, or other suitable gases). Alternatively, the chalcogen may be introduced as a vapor (e.g. elemental S, Se, or Te). The heating may occur in a temperature range between about 400 C and about 1000 C. The metal oxide may react with the chalcogen to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide is zinc oxide, the chalcogen source is H 2 Se, and the resulting alloy has a formula of ZnO x Se (1-x)  where x ranges from 0 to 1. 
     It is noted that the processes described for steps  602 - 604  may all be performed in a batch furnace or in-line furnace. Consequently, implementation of method  600  is substantially economical and less complex than other processes required for the formation of other absorber layers. It is further noted that embodiments of the invention may be performed using any technically feasible deposition techniques known in the art. For example, the TFPV device may be formed using single substrate processing equipment, multiple substrate batch-processing equipment, in-line processing, single chamber processing, roll-to-roll processing, and the like. In-line processing may include continuous processing of substrates while moving through an in-line furnace, or the performance of different processes on each substrate in multiple discrete reaction chambers. Such chambers may be isolated mechanically, by gas curtains, etc. 
       FIG. 7  presents a flow chart for methods,  700 , for forming absorbers according to some embodiments. In operation  702 , a metal oxide film is formed above a substrate. In some embodiments, the metal oxide film includes zinc oxide. Examples of suitable deposition techniques include PVD (e.g. sputtering), reactive sputtering (e.g. in the presence of a chalcogen), evaporation, CVD, spray coating, sol-gel techniques, printing of metal oxy-chalcogenide particles (and/or metal chalcogenide particles) followed by sintering, electroplating of metal oxide and/or metal chacogenide layers, or other known deposition techniques. In operation  704 , an elemental layer of the chalcogen (e.g. S, Se, or Te) is formed on the metal oxide film. The elemental layer of the chalcogen may be formed using any suitable deposition technique. Examples of suitable deposition techniques include PVD (e.g. sputtering), evaporation, CVD, spray coating, sol-gel techniques, or other known deposition techniques. Typical techniques would include e-beam or thermal evaporation. In operation  704 , the stack (e.g. substrate/zinc oxide/chalcogen) is heated to cause the metal oxide to react with the chalcogen to form a metal-oxygen-chalcogen alloy. The heating may occur in a temperature range between about 400 C and about 1000 C. In some embodiments, the metal oxide is zinc oxide, the elemental chalcogen film is Se, and the resulting alloy has a formula of ZnO x Se (1-x)  where x ranges from 0 to 1. 
     In some embodiments, zinc oxide films were deposited on glass using a sputtering technique. The zinc oxide films were heated in a batch furnace to a temperature of 600 C and exposed to a mixture of 1 volume % H 2 Se in Ar. The samples were heated in the presence of the gas mixture for 180 minutes. 
       FIG. 8  presents data for optical transmittance (%) versus wavelength for a zinc oxide film both before and after selenization according to some embodiments. The data represented by the square symbols indicates that the transmittance (%) of the film was about 80% in a wavelength range between about 400 nm and 700 nm. The appearance of the film before the selenization process was clear. The data represented by the diamond symbols indicates that the transmittance (%) of the film decreases in a wavelength range between about 400 nm and 700 nm. The decrease in transmittance corresponds to an increase in the absorbance of the film within this wavelength range. The appearance of the film after the selenization process was noticeably darker and slightly yellow in color. The data indicate that the band gap has decreased from about 3.4 eV to about 2.7 eV due to the formation of the ZnO x Se (1-x)  alloy where x ranges from 0 to 1. 
       FIG. 9  presents data for x-ray fluorescence (XRF) intensity (a.u.) versus energy for a zinc oxide film both before and after selenization according to some embodiments. The data represented by the “blue” line indicates that Se has been incorporated into the alloy. This is indicated by the appearance of the peak at about 11.2 KeV energy. This peak is known to correspond to the selenium Kα peak. 
       FIG. 10  presents data for x-ray diffraction (XRD) intensity (a.u.) versus 2-theta angle (degrees) for a zinc oxide film both before and after selenization according to some embodiments. The data represented by the “blue” line indicates that Se has been incorporated into the alloy. This is indicated by the appearance of the peak at about 28 degrees and the disappearance of the zinc oxide peak at about 35 degrees. 
     Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed examples are illustrative and not restrictive.