Patent Publication Number: US-8982584-B2

Title: Power supply regulation for ultra-low load and no-load operation

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. §119(e) from co-pending U.S. Provisional Patent Application No. 61/560,039, filed on Nov. 15, 2011, which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to controlling a switching power converter in more than one operation mode to increase the efficiency of the power converter at low-load or no-load conditions. 
     2. Description of the Related Arts 
     Increased efficiency demands placed on portable electronic devices create challenges for regulating power in low-load or no-load operation in a switching power converter. These challenges include consuming nearly no power in standby mode, while being able to quickly deliver power when the device is suddenly plugged-in. 
     In low-load or no-load operation, switching power converters operate at a low switching frequency represented by F SW . On the other hand, low switching frequencies make it difficult to satisfy the demands of fast dynamic load response (DLR) in switching power converters. The impact of these competing requirements may be even more apparent in the operation of a flyback power converter with a primary-side feedback switching power converter. In a primary-side feedback flyback power converter, the primary voltage feedback responds to the load change cycle-by-cycle. To regulate the output voltage switching cycle-by-switching cycle, the primary feedback voltage is typically sampled once per switching cycle. If the switching frequency becomes too low, the resulting switching period may be too long to sample information between consecutive switching cycles and result in a distorted waveform of the output voltage. On the other hand, an increase in switching frequency results in a proportional undesirable increase in power supply consumption. 
     SUMMARY 
     Embodiments include a dynamically adaptive switching power supply with a regulation scheme that improves low-load and no-load regulation to achieve ultra-low standby power in a switching power converter. Under ultra-low load conditions when a deep-deep pulse width modulation (DDPWM) mode is used to control the switching power converter, as the input power to the switching power converter is decreased, the actual on-time of the power switch of the switching power converter is reduced by decreasing the “on” duration of the control signal used to turn on or off the power switch, until the “on” duration of the control signal reaches a minimum value. When the “on” duration of the control signal reaches the minimum value, the “on” duration is not reduced any further even with the input power further decreasing, but rather maintained at the minimum value. Instead, the actual on-time of the power switch is further reduced by making the power switch turn on more slowly, e.g., by reducing the base current provided by the switch driver if a bipolar transistor is used as the power switch, or by increasing the on-resistance of the switch driver if a power MOSFET is used as the power switch. Thus, the switching power converter can further reduce the actual on-time of the power switch without further reducing the “on” duration of the control signal used to turn on or off the power switch lower than the minimum value. This allows the switching power converter to operate under ultra-low load conditions delivering very low power responsive to very low input power, while maintaining appropriate waveforms of the output voltage of the switching power converter to allow appropriate sensing and regulation of the output voltage. 
     The minimum value of the “on” duration of the control signal used to turn on or off the power switch may be determined dynamically, when the switching power converter is in use, toggling between an initial value and another increased value. When a distorted output voltage sensing waveform of the switching power converter is detected during use of the switching power converter, the minimum value of the “on” duration of the control signal used to turn on or off the power switch is increased from the initial value to the increased value, and a timer may be set. When the timer reaches a predetermined limit and the waveform of the output voltage of the switching power converter is not distorted, the minimum value of the “on” duration of the control signal used to turn on or off the power switch is decreased back to the initial value. The minimum base current for driving a bipolar transistor or maximum on-resistance for driving a power MOSFET can be dynamically adjusted in the same way as the minimum value of the “on” duration as described above. 
     The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings and specification. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The teachings of the embodiments of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. 
         FIG. 1  is a circuit diagram illustrating a switching power converter, according to one embodiment. 
         FIG. 2  illustrates the operation of the switching power converter of  FIG. 1  according to one embodiment. 
         FIG. 3A  is a graph illustrating the operation modes of a switching power converter, according to one embodiment. 
         FIG. 3B  is graph illustrating the operation modes of  FIG. 3A  at low-load and no-load conditions, according to one embodiment. 
         FIG. 3C  is a graph illustrating the operation modes of  FIG. 3B  at low-load and no-load conditions in more detail, according to one embodiment. 
         FIG. 3D  illustrates how the minimum T ON     —     min  is set, according to one embodiment. 
         FIG. 3E  illustrates how the minimum R DS     —     ON     —     max  is set, according to one embodiment. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The Figures (FIG.) and the following description relate to preferred embodiments of the present disclosure by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the present disclosure. 
     Reference will now be made in detail to several embodiments of the present disclosure, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the embodiments described herein. 
     Example Switching Power Converter Circuit 
       FIG. 1  is a circuit diagram illustrating a switching power converter  100 , according to one embodiment. Power converter  100  is a primary-side feedback flyback converter, and includes three principal sections, i.e., front end  104 , power stage, and secondary stage. Front end  104  is connected to an AC voltage source (not shown) at nodes L, N, and includes a bridge rectifier comprised of inductor L 1 , resistors R 1  and F 1 , diodes D 1 , D 2 , D 3 , and D 4 , and capacitor C 2 . The rectified input line voltage at node  105  is input to the supply voltage pin Vcc (pin  1 ) of controller IC  102  via resistors R 10  and R 11 . The line voltage at node  105  is also connected to the primary winding  106  of power transformer T 1 -A. Capacitor C 5  removes high frequency noise from the rectified line voltage. The output of front end  104  at node  105  is an unregulated DC input voltage. 
     The power stage is comprised of power transformer T 1 -A, BJT power switch Q 1 , and controller IC  102 . Power transformer T 1 -A includes primary winding  106 , secondary winding  107 , and auxiliary winding  108 . Controller IC  102  maintains output regulation via control of the ON and OFF states of BJT power switch Q 1 . The ON and OFF states of BJT power switch Q 1  are controlled via control signal  110  output from the OUTPUT pin (pin  5 ) of controller IC  102 . Control signal  110  drives the base (B) of BJT power switch Q 1 . The collector (C) of BJT power switch Q 1  is connected to the primary winding  106 , while the emitter (E) of BJT power switch Q 1  is connected to the I SENSE  pin (pin  4 ) of controller IC  102  and to ground via resistor R 12 . I SENSE  pin senses the current through the primary winding  106  and BJT switch Q 1  in the form of a voltage across sense resistor R 12 . Controller IC  102  employs the modulation technique as described below in detail with reference to  FIGS. 3A-3E  to control the ON and OFF states of power switch Q 1 , the duty cycles of control signal  110  and the amplitude of the BJT base current. The GND pin (pin  2 ) of controller IC  102  is connected to ground. While a BJT switch Q 1  is used as the power switch in the embodiment of  FIG. 1 , a power MOSFET may also be used as the power switch for the switching power converter  100  according to other embodiments herein. 
     The secondary stage is comprised of diode D 6  functioning as an output rectifier and capacitor C 10  functioning as an output filter. The resulting regulated output voltage Vout at node  109  is delivered to the load (not shown) and a pre-load R 14 . The pre-load R 14  stabilizes the output of the power converter at no load conditions. Also, ESD (Electrostatic Discharge) gap (ESDI) is coupled between primary winding  106  and diode D 6 . 
     The output voltage Vout at node  109  is reflected across auxiliary winding  108 , which is input to the V SENSE  pin (pin  3 ) of controller IC  102  via a resistive voltage divider comprised of resistors R 3  and R 4 . Also, although controller IC  102  is powered up by the line voltage  105  at start-up, controller IC  102  is powered up by the voltage across auxiliary winding  108  after start-up and in normal operation. Thus, diode D 5  and resistor R 2  form a rectifier for rectifying the voltage across auxiliary winding  108  for use as the supply voltage input to the V CC  pin (pin  1 ) of controller IC  102  after start-up during normal operation. Capacitor C 9  is used to hold power from the line voltage at node  105  at start-up or from the voltage across auxiliary winding  108  after start-up between switching cycles. 
       FIG. 2  illustrates an exemplary auxiliary winding voltage waveform (V SENSE ) segmented by states associated with the operation of the primary side feedback flyback power converter. The auxiliary winding voltage reflects the secondary winding voltage and is used for sensing the output voltage in primary side feedback flyback power converters. Referring to  FIGS. 1 and 2  together, in state  1 , the power transistor (Q 1 ) turns on, which is represented by the actual turn-on time (t ON ) of the power switch. In state  2 , the power switch (Q 1 ) is turned off, the secondary current (i SEC ) in the output diode (D 6 ) starts conducting, and ringing on the output voltage occurs due to the leakage inductance and the parasitic capacitance of the power switch. In state  3 , the output voltage drops due to the IR drop across the diode (D 6 ) and the equivalent series resistance (ESR) of the output capacitor (C 10 ). The magnitude of the voltage drop in state  3  is primarily a function of the rate of change of the secondary current (i SEC ), which is relatively constant. In state  4 , the secondary current (i SEC ) approaches zero and the voltage drop across the secondary diode (D 6 ) decreases. And in state  5 , oscillation of the output voltage occurs between the magnetizing inductance of the transformer T 1  and parasitic capacitance of the power switch Q 1 . To properly regulate the output voltage, the V SENSE  waveform should have a knee point that accurately reflects the output voltage, which typically occurs when the secondary current (i SEC ) reaches zero (i.e., when the output diode D 6  stops conducting). In cases where the power transistor actual “on time” (t ON ) is too small, the power transistor Q 1  may not be fully turned on or the energy delivered to the output may be too small. Consequently, the auxiliary winding waveform (V SENSE ) may become distorted and fail to accurately reflect the output voltage. 
     On other hand, in order to achieve very low power under low-load and no-load operating conditions, and maintain a relatively high switching frequency, it is desired to have very short actual “on time” for power switch Q 1 , such as 100 ns. Depending on the switching speed of the power transistor, however, the transistor may not always be able to achieve a good V SENSE  waveform for regulation when the power switch is driven by a control signal with too short an on-time. In one embodiment, to avoid the V SENSE  distortion caused by too short “on time” of the control signal used to turn on or off the power switch, a minimum “on time” (T ON     —     MIN ) may be set to generate V SENSE  waveform suitable for accurate sensing and regulation. Factors including line voltage and the power transistor type may be taken into consideration to determine the minimum on-time T ON     —     MIN  of the control signal used to turn on or off the power switch. Furthermore, the determination of T ON     —     MIN  is made dynamically, according to the embodiments herein as explained in more detail below. For example, at a high line voltage (input voltage), e.g. 230 V, T ON     —     MIN  of 150 ns may be sufficient to generate a V SENSE  waveform suitable for accurate sensing, while at a low line voltage (input voltage), e.g. 90 V, T ON     —     MIN  of 800 ns may be needed in order to generate a suitable V SENSE  waveform. Additionally, for a fast MOSFET used as the power switch, T ON     —     MIN  of 120 ns at a line voltage of 230 V may be sufficient to generate a V SENSE  waveform suitable for accurate sensing, while for a slow MOSFET used as the power switch, T ON     —     MIN  of 200 ns at a line voltage 230 V may be appropriate. 
     Adaptive Mode Transition 
       FIG. 3A  is a graph illustrating the operation of switching power converter  100 , according to one embodiment. Line J′-K′ represents the operation of switching power converter  100  in constant voltage (CV) mode. Line K′-L′ represents the operation of switching power converter  100  in constant current (CC) mode. 
     In one embodiment, switching power converter  100  operates in modes as indicated by lines M-A′, A′-B, B-C, and C-D. In high load conditions represented as a straight line M-A′, switching power converter  100  operates in first PWM mode to generate an output current Iout in the range above I 3  up to the maximum output current I 4 . If the output current Iout drops below I 3 , the power converter transitions from first PWM mode (represented by line M-A′) to first PFM mode (represented by line A′-B) followed by second PWM mode (hereinafter referred to as ‘deep’ PWM or DPWM, represented by line B-C) which is again followed by second PFM mode (hereinafter referred to as ‘deep’ PFM or DPFM, represented by line C-D). Contrast this with conventional power converters where a single PFM mode represented by line A′-D is used throughout the output current level below I 3 . 
     More specifically, as the output current Iout of switching power converter  100  drops to I 3 , switching power converter  100  switches to PFM mode represented by line A′-B. Worldwide energy standards specify the average efficiency of the power converter based on the averaging of the efficiencies at four loading points (25% load, 50% load, 75% load, and 100% load). In order to satisfy such standards, it is advantageous to set I 3  at a level substantially higher than 25% of the maximum load so that switching power converter  100  operates in PFM mode around the 25% load level. In one embodiment, I 3  is set around 50% of the maximum output current I 4 . 
     If the output current of switching power converter  100  drops further to I 2 , switching power converter  100  transitions to DPWM mode where the duty cycle of the switch is controlled by adjusting the duration of on-times of the switch in each switching cycle, as in any PWM mode. During DPWM mode, the switching frequency is maintained at F SW2 , which is higher than the audible frequency range. In one embodiment, the F SW2  is around 20 kHz, which is higher than the audible frequency range. Switching power converter  100  operates in DPWM mode as represented by line B-C where switching power converter  100  generates an output current Iout between I 1  and I 2 . In one embodiment, I 1  and I 2  are set around 5% and 20% of the maximum output current I 4 , respectively. 
     PWM Mode Operation in Light Load Conditions 
     In another embodiment, switching power converter  100  operates in a third PWM mode (hereinafter referred to as ‘deep-deep PWM’ or DDPWM) in very-light-load or no-load conditions to improve dynamic load response. When the load across the output of switching power converter  100  is abruptly increased (e.g., by initially connecting switching power converter  100  to an external output load while switching power converter  100  is in a low-load or no-load condition), the output voltage of switching power converter  100  may drop below a permissible level and also take an extended amount of time to recover back to the regulated output voltage due to low switching frequency in the low-load conditions. To enhance dynamic output regulation performance at the low-load or no-load conditions, switching power converter  100  according to one embodiment switches to operate in DDPWM mode at a predetermined switching frequency and then transitions to DDPFM mode or a third PFM mode (hereinafter referred to as referred to as ‘deep-deep PFM’ or DDPFM) as the load across the output of switching power converter  100  is decreased. 
       FIG. 3B  is a graph illustrating the operation modes of switching power converter  100  implementing DDPWM and DDPFM modes, according to one embodiment.  FIG. 3B  illustrates the region delineated by the dotted circle in  FIG. 3A  in more detail. The operation of switching power converter  100  above output current level I 1  ( FIG. 3A ) is essentially the same as the embodiment described above with reference to  FIG. 3A , and therefore, the detailed description thereof is omitted herein for the sake of brevity. In this embodiment, switching power converter  100  operates in two additional modes (DDPWM mode and DDPFM mode) at low-load and no-load conditions where the output current Iout is below level I 1  (I 1  in  FIG. 3A  corresponding to input power level P 1  in  FIG. 3B ) instead of operating in a single DPFM mode throughout these conditions. 
     In a scenario where the input power of switching power converter  100  is gradually decreased below P 1  (P 1  corresponds to the input power consumption of switching power consumption converter  100  when output current of switching power converter  100  is I 1  as illustrated in  FIG. 3A ), switching power converter  100  operates in DPFM mode represented by line C-E, as in the PFM mode. For example, P 1  may be about 2% of the maximum input power consumption of switching power converter  100 . When the input power of switching power converter  100  drops to P a , switching power converter  100  transitions and operates in DDPWM mode represented by the circled line E-F. Then, switching power converter  100  transitions and operates again in DDPFM mode when the input power of switching power converter  100  drops below P b , as represented by line F-D. 
       FIG. 3C  is a graph illustrating the DDPWM operation mode in more detail, according to another embodiment. Curve  302  indicates the switching frequency of switching power converter  100 , curve  304  indicates the duration of the on-time (T ON ) of control signal  110  turning on or off the power switch of switching power converter  100  in a switching cycle, curve  306  indicates the on-resistance (R DS     —     ON ) of the driver of the power switch of switching power converter  100  when a power MOSFET is used as the power switch, and curve  308  indicates the base current provided by the driver of the power switch of switching power converter of  100  when a bipolar transistor is used as the power switch. 
     In one embodiment, the circled line E-F normally corresponds to no-load operation during which the input of switching power converter  100  is connected to a power source but the output of switching power converter  100  is not connected to any load. In no-load conditions, the actual output current of switching power converter  100  is zero or close to zero but the input power is not zero due to power consumption by switching power converter  100 . P a  and P b  represent a level of the input power consumption of switching power converter  100 . For example, P a  may be about 1% of the maximum input power consumption of switching power converter  100 . In another example, P b  may be less than about 0.5% of the maximum input power consumption of switching power converter  100 . Note that the horizontal axis of  FIGS. 3B and 3C  represents input power of switching power converter  100  (unlike  FIG. 3A  where the horizontal axis represents output current of switching power converter  100 ). As the load decreases, the power consumed by switching power converter  100  becomes more dominant compared to the power consumed by the load, and can no longer be disregarded. Therefore, in  FIGS. 3B and 3C , the reference points P a  and P b  are indicated as a fraction of the maximum input power of switching power converter  100  instead of the maximum output current of switching power converter  100 . 
     Returning to  FIG. 3C , DDPWM mode may be divided into two control regions, T ON  control region and R DS     —     ON  control region. In the T ON  control region between input power P a  and P 2 , switching power converter  100  operates in DDPWM mode but controls the actual on-time of the power switch of switching power converter  100  by controlling the duration (T ON ) of control signal  110  directly and reducing T ON  as the input power is decreased. When T ON  reaches T ON     —     min , switching power converter  100  does not further reduce the on-duration (T ON ) of control signal  100  despite the input power decreasing further beyond P 2 , but rather maintains T ON  at T ON     —     min . Instead, when the input power further decreases beyond P 2 , switching power converter  100  decreases the actual on-time of the power switch of switching power converter  100  by turning on the power switch more slowly, i.e., by decreasing the base current (Ib) provided by the driver driving the power switch if a BJT power switch is used in the power converter  100 , or by increasing the on-resistance (R DS     —     ON ) of the driver if a power MOSFET power switch is used in switching power converter  100 . Thus, if the power switch of switching power converter  100  is a BJT, the base current (Ib) provided by the driver driving the BJT power switch is constant between input powers P a  and P 2 , but is decreased between input powers P 2  and P b  as the input power is decreased, until it reaches its minimum value, Ib min , at P b  as shown by curve  308 . On the other hand, if the power switch of switching power converter  100  is a power MOSFET, the on-resistance (R DS     —     ON ) of the driver driving the power MOSFET is constant between input powers P a  and P 2 , but is increased between input powers P 2  and P b  as the input power is decreased, until it reaches its maximum value, R DS     —     ON     —     max , at P b  as shown by curve  304 . Because the power switch is turned on more slowly as the input power is decreased from P 2  to P b , the actual on-time of the power switch (i.e., the actual duration while the power switch is in an on-state at each switching cycle) is decreased and less power is delivered by switching power converter  100  to the load, thereby appropriately responding to the decreasing input power to switching power converter  100 . 
     In one embodiment, T ON     —     min , R DS     —     ON     —     max , or Ib min  are determined dynamically in operation, such that the circuit parameters of switching power converter  100  as well as the operating condition of switching power converter  100  are taken into consideration when determining which values to use for T ON     —     min , R DS     —     ON     —     max , or Ib min .  FIG. 3D  illustrates an exemplary control algorithm for T ON     —     min  control. Referring to  FIG. 3D  together with  FIG. 1 , the pulse train illustrates a series of pulses output from controller IC  102  as control signal  110  to provide a switching input to the power transistor Q 1 . Bad V SENSE  signal  404  is a signal indicating whether the V SENSE  waveform is distorted (i.e. Bad V SENSE  is high) or not, due to the duration of the on-time of the pulses in the pulse train being too short to render a proper V SENSE  waveform. Timer signal  402  is a free running timer that functions as a lightly loaded spring tension that Bad V SENSE  signal  404  works against to keep the T ON     —     min  near the minimum amount of on-time that results in a suitably undistorted V SENSE  waveform. T ON     —     min  signal  406  indicates how the value of T ON     —     min  may be adjusted on a switching cycle-by-switching cycle basis according to the exemplary control algorithm. Initially, T ON     —     min  may be set to a predetermined value, which may be based on an estimated line voltage variation or other suitable system parameter. Alternatively, T ON     —     min  may be set initially by ramping the value from a low value (e.g., zero) to a value that allows obtaining an undistorted V SENSE  waveform (i.e., Bad V SENSE  waveform is at logic low). This value of T ON     —     min  is referred to as T 1  in  FIG. 3D . For example, controller IC  102  may ramp the value of T ON     —     min  incrementally (e.g., by a fraction of a clock cycle or an integer number of clock cycles) at a predetermined interval. The predetermined interval, in one example, may be associated with the occurrence of one or more edges of pluses in pulse train. In another example, the predetermined interval may be associated with a predetermined value, which may be based on estimated output power output of power converter  100 , estimated line voltage variation or other suitable system parameter. 
     In cases where the line voltage sags during a switching cycle, T 1  may deliver insufficient energy to produce a suitably undistorted V SENSE  waveform. In response, Bad V SENSE  signal  404  transitions from a low to a high, indicating a distorted V SENSE  waveform. The criteria for triggering a Bad V SENSE  signal  404  may be determined using a variety of waveform analysis techniques known to those of ordinary skill in the art. For example, a Bad V SENSE  signal  404  may transition from a low to a high (i) when the V SENSE  pulse is too narrow compared to a threshold value or compliance mask, (ii) when V SENSE  waveform rises to a predetermined value too early or falls to a predetermined value too late, (iii) when the V SENSE  waveform fails to rise to an expected maximum value, and/or (iv) when the next cycle of V SENSE  occurs earlier than expected, etc. When Bad V SENSE  signal  404  transitions from a low to a high, the value of T ON     —     min  increases by ΔT, from T 1  to T 1 +ΔT. Whenever there is an adjustment of the value of T ON     —     min , Timer  402  is reset to “0” and resumes counting. When Timer  402  reaches a pre-determined threshold, the value of T ON     —     MIN  is reduced by ΔT, from T 1 +ΔT to T 1 . To provide finer control granularity, ΔT represents a half-clock cycle of the switching cycle. For example, for a 20 MHz system clock, the clock period would be 50 ns and ΔT would be 25 ns. 
     The exemplary dynamic T ON     —     min  control algorithm operates as follows:
         1. At any switching cycle, if Bad V SENSE  signal  404  goes high, T ON     —     min  is increased by ΔT, to T 1 +ΔT.   2. At any switching cycle, if Timer  402  reaches the pre-set threshold, T ON     —     MIN  is decreased by ΔT back to T 1 .   3. At any switching cycle, if Bad V SENSE  signal  404  goes high or if Timer  402  reaches the pre-set threshold, Timer  402  is reset to zero. Otherwise, Timer  402  continues to count.
 
Accordingly, switching power converter  100  according to the embodiments herein searches for the ideal T ON     —     min , and then hysterically adjusts T ON     —     min  between two values with a ΔT difference.
       

       FIG. 3E  illustrates an exemplary algorithm for dynamic R DS     —     ON  control. As previously discussed, the actual on-time of the power switch may be reduced by adjusting the gate resistance (R DS     —     ON ) of the power switch if a power MOSFET is used as the power switch. In the R DS     —     ON  control region of DDPWM mode, the “on” duration of the pulses in the pulse train (T ON  time) is fixed at T ON     —     min  or at a value that is larger than T ON     —     min  as determined by the dynamic T ON     —     min  control algorithm described in  FIG. 3D . Generally, the exemplary algorithm for dynamic R DS     —     ON  control operates in a manner similar to the dynamic T ON     —     min  control algorithm, but instead is used to dynamically adjust the value R DS     —     ON . R DS     —     ON     —     max  signal  408  indicates how the value of R DS     —     ON  may be adjusted on a switching cycle-by-switching cycle basis according to the algorithm. Initially, R DS     —     ON  may be set to a predetermined value (e.g., 50 ohms), which may be based on the type of power transistor used in switching power converter  100  and/or other system parameters. In  FIG. 3E , R DS     —     ON     —     max  is set to R 1 . R 1  may be determined in a similar manner to the determination T 1  as previously described. When Bad V SENSE  signal  404  transitions from a low to a high, indicating a distorted V SENSE , the value of R DS     —     ON     —     max  is decreased by ΔR, from R 1  to R 1 −ΔR. The value of ΔR may be a predetermined value, which may be based on the type of power transistor used in switching power converter  100  and/or other system parameters. In one example, R DS     —     ON  may be set to 50 ohms, R DS     —     ON     —     max  may be set to 300 ohms, and ΔR may be set to 20 ohms. In another example, R DS     —     ON , R DS     —     ON     —     max , and ΔR may be set to other values suitable to enable controller  102  to dynamically adjust the values of R DS     —     ON  to maintain an undistorted V SENSE  while the “on” duration of the pulses in the pulse train (T ON  time) is fixed at T ON     —     min  or at a value that is larger than T ON     —     min  as determined by the dynamic T ON     —     min  control algorithm described in  FIG. 3D . Whenever there is an adjustment of the value of R DS     —     ON     —     max , Timer  402  is reset to “0” and resumes counting. When Timer  402  reaches a pre-determined threshold, the value of R DS     —     ON     —     max  is increased by ΔR, from R 1 −ΔR to R 1 . The exemplary dynamic R DS     —     ON     —     max  control algorithm operates as follows:
         1. At any switching cycle, if Bad V SENSE  signal  404  goes high, R DS     —     ON     —     max  is reduced by one step ΔR, to R 1 −ΔR.   2. At any switching cycle, if Timer  402  reaches the pre-set threshold, R DS     —     ON     —     max  is increased by one step ΔR back to R 1 .   3. At any switching cycle, if Bad V SENSE    404  signal goes high or if Timer  402  reaches the pre-set threshold, Timer  402  is reset to zero. Otherwise, Timer  402  continues to count.       

     The exemplary dynamic R DS     —     ON     —     max  control algorithm is just one way of controlling the power transistor driving strength, i.e., how rapidly the power switch of switching power converter  100  will be turned on. The same concept of dynamic R DS     —     ON  control and R DS     —     ON     —     max  control can be applied to control the base current (Ib) of a bipolar junction transistor (BJT) power switch as explained above. Applied to a BJT used as the switching device for the switching power converter, another exemplary dynamic minimum base current Ib min  control algorithm may operate as follows:
         1. At any switching cycle, if the Bad V SENSE  signal goes high, Ib min  is increased by one step ΔI from I 1  to I 1 +ΔI.   2. At any switching cycle, if the Timer reaches the pre-set threshold, Ib min  is decreased by one step ΔI, back to I 1 .   3. At any switching cycle, if the Bad V SENSE  signal goes high or if the Timer reaches the pre-set threshold, the Timer is reset to zero. Otherwise, the Timer continues to count.       

     Upon reading this disclosure, those of skill in the art will appreciate still additional alternative designs for switching power converters. For example, although controller IC  102  and its application circuit shown in  FIG. 2  are based on the primary-side feedback control, the same principles of this disclosure are also applicable to alternative designs based on the secondary-side feedback control. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and components disclosed herein and that various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure disclosed herein without departing from the spirit and scope of the present disclosure.