Patent Publication Number: US-9893122-B2

Title: Metal line connection for improved RRAM reliability, semiconductor arrangement comprising the same, and manufacture thereof

Description:
REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of U.S. application Ser. No. 14,967,697 filed on Dec. 14, 2015, which is a Continuation of U.S. application Ser. No. 14/152,244 filed on Jan. 10, 2014 (now U.S. Pat. No. 9,230,647 issued on Jan. 5, 2016), which claims priority to U.S. Provisional Application No. 61/921,148 filed on Dec. 27, 2013. The contents of the above referenced applications are hereby incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     The present disclosure relates to integrated circuit devices with resistive random access memory, methods of making such devices, and methods of operating such devices. 
     Resistive random access memory (RRAM) has a simple structure, low operating voltage, high-speed, good endurance, and CMOS process compatibility. RRAM is the most promising alternative to provide a downsized replacement for traditional flash memory and is finding wide application in devices such as optical disks and non-volatile memory arrays. 
     An RRAM cell stores data within a layer of material that can be induced to undergo a phase change. The phase change can be induced within all or part of the layer to switch between a high resistance state and a low resistance state. The resistance state can be queried and interpreted as representing either a “0” or a “1”. 
     In a typical RRAM cell, the data storage layer includes an amorphous metal oxide. Upon application of a sufficient voltage, a metallic bridge is induced to form across the data storage layer, which results in the low resistance state. The metallic bridge can be disrupted and the high resistance state restored by applying a short high current density pulse that melts or otherwise breaks down all or part of the metallic structure. The data storage layer quickly cools and remains in the high resistance state until the low resistance state is induced again. RRAM cells are typically formed after front-end-of line (FEOL) processing. In a typical design, an array of RRAM cells is formed between a pair of metal interconnect layers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  illustrates an RRAM device according to some embodiments of the present disclosure. 
         FIGS. 2A-2C  illustrates some exemplary wire sizes which are suitable for the RRAM device according to some embodiments of the present disclosure. 
         FIG. 3  is a flow chart illustrating a method of setting an RRAM cell according to some embodiments of the present disclosure. 
         FIG. 4  is a plot showing voltages across and currents through an RRAM cell as it undergoes a RRAM cell setting process according to some embodiments of the present disclosure. 
         FIG. 5  is a flow chart illustrating a method of resetting an RRAM cell according to some embodiments of the present disclosure. 
         FIG. 6  is a plot showing voltages across and currents through an RRAM cell as it undergoes an RRAM cell resetting process according to some embodiments of the present disclosure. 
         FIG. 7  is a flow chart illustrating an RRAM device manufacturing method according to some embodiments of the present disclosure. 
         FIGS. 8-10  illustrate cross-sectional views at various intermediate stages of manufacturing an RRAM device according to some embodiments of the present disclosure. 
         FIGS. 11-15  illustrate cross-sectional views at various intermediate stages of manufacturing an RRAM cell according to some embodiments of the present disclosure. 
         FIGS. 16-17  illustrate cross-sectional views at various intermediate stages of manufacturing an RRAM device according to some other embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     As densities of integrated circuits have increased, the resistance-capacitance (RC) delay of wires in metal interconnect layers has begun to have a significant effect on integrated circuit performance. Modern integrated circuits (ICs) reduce RC delay in metal interconnect layers by using copper in place of aluminum and low-k dielectrics in place of SiO 2 . RC delay is also reduced by scaling to use thicker wires to make lengthier connections. 
     Scaling is done by varying wire thickness and width among metal interconnect layers. The lowest metal interconnect layers, which are closest to the substrate, have the thinnest and narrowest wires. Wires in the lowest layers have the highest RC delay and are used to make local interconnections. Wire thicknesses, widths, and separations gradually increase as additional metal interconnect layers are added. The topmost metal interconnect layers have the thickest, widest, and most coarsely spaced wires. The uppermost layers have the lowest RC delay and are used for power and clock distribution and for global signal routing. 
     Modern integrate circuits typically include thousands of components having complex interrelationships. Due to this complexity, the placement and routing of wires among the metal interconnect layers is usually determined by computer in a process of electronic design automation (EDA). Typically, a very large number of different circuit designs can meet a functional specification provided to an EDA program. Aside from basic design constraints, there are a variety of different performance objectives relating to such matters as performance, power, signal integrity, reliability, and yield. Because of the large number of possibilities and the computational requirements of evaluating the constraints and objective functions, the problem of specifying an optimal design is mathematically intractable. Mathematically intractable means that an optimum exists but cannot be ascertained within a feasible period of time. Accordingly, although EDA seeks optimal solutions, the search for solutions must be constrained by design rules for solutions to be reached within practical time limits. 
     It has been determined that the durability of an RRAM device having the 1T1R architecture, which provides one transistor for each RRAM cell, is often limited by the lifetime of the transistors. It has been further determined that the transistors age primarily during the reset operation. Due to the body effect, the reset operation requires a considerably higher voltage on the transistor gates than the set operation. It has been found that reducing the sheet resistance of the source lines provides a surprisingly large increase in the reset speed. For example, by increasing the source lines from a conventional wire size, which is the size of a wire in the second metal interconnect layer (M 2 ), to the size of a wire in the sixth metal interconnect layer (M 6 ), the time required for a reset operation can be reduced by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device can be consequentially increased by approximately one order of magnitude. 
       FIG. 1  provides an illustration of an integrated circuit device  100  according to some embodiments of the present disclosure. The integrated circuit device  100  includes a semiconductor substrate  101  and a plurality of metal interconnect layers  131  (M 1 -M 6 ) formed over substrate  101 . An RRAM cell  125  can be formed in one of these metal interconnect layers  131 , between two of these layers, or in a higher layer. In most embodiments, RRAM cell  125  is formed above the fourth (M 4 ) metal interconnect layer  131  to satisfy restrictions on the thermal budget. In some embodiments, RRAM cell  125  is formed between the fourth (M 4 ) and fifth (M 5 ) metal interconnect layers  131  as shown in  FIG. 1 . 
     The RRAM cell  125  is one in an array of RRAM cells  125  forming a memory block. A bit line  133  for addressing RRAM cells  125  in the memory block is formed in a metal interconnect layer  131  above RRAM cell  125 . In the embodiment of  FIG. 1 , bit line  133  is formed in the fifth (M 5 ) metal interconnect layer  131 . In most embodiments, bit line  133  is connected to a top electrode  127  of RRAM cell  125  by a via  129 . 
     A switching device for selecting RRAM cell  125  is formed on substrate  101 . In the embodiment of  FIG. 1 , the switching device is transistor  105 . This is representative of embodiments having a 1T1R architecture. In some embodiments, the switching device is a diode and the architecture is 1D1R. In some embodiments, the switching device is a bipolar junction transistor and the architecture is 1BJT1R. In some embodiments, the switching device is a bipolar switch and the architecture is 1S1R. 
     In the embodiment of  FIG. 1 , transistor  105  is one in an array of transistors  105  separated by isolation regions  103 . Transistor  105  includes a source region  107 , a drain region  113 , a gate  111 , and a gate dielectric  109 . Drain region  113  is connected to a bottom electrode  123  of RRAM cell  125  through a contact plug  115 , vias  119  formed in the first through fourth (M 1 -M 4 ) metal interconnect layers  131 , and vias  117  formed between these metal interconnect layers  131 . A word line  135  for switching the transistor  105  is formed in the third (M 3 ) metal interconnect layer  131 . 
     A source line  137  supplies current pulses for resetting RRAM cell  125 . In device  100 , source line  137  is connected to source region  107  through a contact plug  145 , vias  143  formed in the first through fourth (M 1 -M 5 ) metal interconnect layers  131 , and vias  141  formed between these metal interconnect layers  131 . By conventional design rules, source line  137  would be located in the second (M 2 ) metal interconnect layer  131  and would have a lower cross-sectional area than bit line  133 . According to some embodiments of the present disclosure, source line  137  has a cross-sectional area that is greater than or equal to the cross-sectional area of bit line  133 . In most embodiments, source line  137  has a cross-sectional area that is greater than the cross-sectional area of bit line  133 . In most embodiments, source line  137  is formed in a metal interconnect layer  131  above RRAM cell  125 . In most embodiments, source line  137  is formed in a metal interconnect layer  131  above the metal interconnect layer  131  in which bit line  133  is formed. In the embodiment of  FIG. 1 , source line  137  is formed in the sixth (M 6 ) metal interconnect layer  131 . 
     In most embodiments, metal interconnect layers  131  are in a scaled arrangement. In a scaled arrangement the mean, mode, or maximum cross-sectional area of conductive lines within each metal interconnect layer  131  increases with increasing height above the substrate  101 . Conductive line widths are generally uniform within a metal interconnect layer  131 , whereby in most embodiments the mean, mode, and maximum cross-sectional areas for conductive lines within a particular metal interconnect layer  131  are all approximately equal. 
     In some embodiments, the mean, mode, and maximum cross-sectional areas of conductive lines of some adjacent metal interconnect layers  131  may be the same. In most embodiments, the mean, mode, or maximum cross-sectional areas of conductive lines of some metal interconnect layers  131  is greater than for other metal interconnect layers  131  and the metal interconnect layers  131  having the larger values for mean, mode, or maximum cross-sectional areas are above those for which the values are smaller. In some embodiments, conductive lines are approximately rectangular in cross-section, whereby cross-sectional area is the product of thickness and width. Thickness refers to a dimension perpendicular, or substantially perpendicular, to the substrate  101 . Width refers to a dimension parallel, or substantially parallel, to the substrate  101  and is, in some embodiments, distinguished from length in that length is much greater than width for structures referred to as conductive lines. An increase in cross-sectional area can be realized through an increase in width, an increase in thickness, or an increase in both. In most embodiments, sheet resistance is approximately inversely proportional to cross-sectional area. 
       FIG. 2A-2C  illustrate conductive lines  153 ,  155 , and  157  according to some embodiments of the present disclosure. Conductive lines  153 ,  155  and  156  have widths  153 W,  155 W, and  157 W and thicknesses  153 T,  155 T, and  157 T, respectively. In some embodiments, conductive line  153  is formed in the second (M 2 ) metal interconnect layer  131 . An EDA program of the prior art would be expected to place source lines in M 2 . In some embodiments, conductive line  153  is formed in the third (M 3 ) metal interconnect layer  131 . In some embodiments, conductive line  153  is word line (WL)  135 . In some embodiments, conductive line  155  is formed in the fifth (M 5 ) metal interconnect layer  131 . In some embodiments, conductive line  155  is bit line (BL)  133 . In some embodiments, conductive line  157  is formed in the sixth (M 6 ) metal interconnect layer  131 . In some embodiments, conductive line  157  is source line (SL)  137 . The following table provides ranges for the relative dimensions and cross-sectional areas of these conductive lines according to some embodiments of the present disclosure: 
     
       
         
           
               
               
               
               
               
             
               
                   
                   
               
               
                   
                 Levels 
                 Lines 
                 Dimension 
                 Ratio 
               
               
                   
                 Compared 
                 Compared 
                 Compared 
                 Range 
               
               
                   
                   
               
             
            
               
                   
                 M5 to M2 
                 BL to WL 
                 Thickness 
                 1.4 to 2.5 
               
               
                   
                 M5 to M2 
                 BL to WL 
                 Width 
                 1.5 to 3.0 
               
               
                   
                 M5 to M2 
                 BL to WL 
                 Cross-sectional area 
                 2.0 to 6.0 
               
               
                   
                 M6 to M5 
                 SL to BL 
                 Thickness 
                 1.1 to 1.4 
               
               
                   
                 M6 to M5 
                 SL to BL 
                 Width 
                 1.0 to 1.3 
               
               
                   
                 M6 to M5 
                 SL to BL 
                 Cross-sectional area 
                 1.1 to 1.8 
               
               
                   
                 M6 to M2 
                 SL to WL 
                 Thickness 
                 1.5 to 3.0 
               
               
                   
                 M6 to M2 
                 SL to WL 
                 Width 
                 1.5 to 4.0 
               
               
                   
                 M6 to M2 
                 SL to WL 
                 Cross-sectional area 
                 2.2 to 10.0 
               
               
                   
                   
               
            
           
         
       
     
     Placement of source line  137  above the fourth (M 4 ) metal interconnect layer  131 , in accordance with some embodiments of the present disclosure, increases its cross-sectional area and reduces its sheet resistance by a factor of two or more in comparison to the cross-sectional area and sheet resistance if source line  137  where configured or positioned according to conventional design rules. In some embodiments, the cross-sectional area of source line  137  is equal to that of bit line  133 . In most embodiments, the cross-sectional area of source line  137  is greater than that of bit line  133 . In some embodiments, bit line  133  and RRAM cell  125  are located or formed in layers located between the metal interconnect layers  131  containing source line  133  and word line  135 . In most embodiments, word line  135  is located below bit line  133  and RRAM cell  125 . 
     Bit line  133 , word line  135 , and source line  137  are used to set and reset RRAM cell  125 .  FIG. 3  provides an example of a process  300  for setting RRAM cell  125 . The process  300  includes act  301 , setting source line  137  to a reference voltage, which is typically ground, act  303 , setting word line  135  to a bias sufficient to turn on transistor  105 , and act  305 , pulsing bit line  133  to provide a voltage-current cycle as shown in  FIG. 4 . In most embodiments, a bias of 1.4 V is sufficient to turn on transistor  105  for the set operation  300 . 
       FIG. 5  provides an example of a process  310  for resetting RRAM cell  125 . The process  310  includes act  311 , setting bit line  133  to a reference voltage, which is typically ground, act  313 , setting word line  135  to a bias sufficient to turn on transistor  105 , and act  315 , pulsing source line  137  to provide a voltage-current cycle as shown in  FIG. 6 . In most embodiments, a bias over 2 V, e.g., 2.4 V, is required to turn on transistor  105  for the reset operation  310 . As shown by  FIGS. 4 and 6 , reset operation  310  requires a higher amplitude pulse than set operation  300 . The voltages shown are voltages across the cell  125 . Acts  303  and  313  pulse bit line  133  or source line  137  with somewhat higher voltages to overcome the parasitic resistances of these lines. Providing source line  137  with a lower sheet resistance than bit line  133  makes the pulse requirements of set and reset operations more nearly equal. 
       FIG. 7  provides a flow chart for a process  200  of forming an RRAM cell  125 , which is an example according to another embodiment of the present disclosure. The process  200  can form the RRAM device  100  according to some embodiments of the present disclosure.  FIGS. 8-10  and  16 - 17  illustrate the RRAM device  100  at intermediate stages of manufacture thereof according to some embodiments of the present disclosure.  FIGS. 11-15  illustrate cross-sectional views at various stages of forming an RRAM cell  125  and the structure within the area  126  identified in  FIG. 16  according to some embodiments of the present disclosure. 
     Process  200  begins with front-end-of-line (FEOL) processing  210 . FEOL processing  210  can include acts that form a switching device for selecting RRAM cell  125 . In the example of  FIG. 7 , FEOL processing  210  includes act  211 , forming isolation regions  103  in substrate  101 , act  213 , forming transistor  105  on substrate  101 , act  215 , saliciding source region  107  and drain region  113  of transistor  105 , and act  217 , forming source contact  145  and drain contact  115 .  FIG. 8  illustrates the device  100  immediately following FEOL processing  210 . 
     Process  200  continues with act  220 , forming the first through fourth (M 1 -M 4 ) metal interconnect layers  131  as shown in  FIG. 9  for the device  100 . Act  220  includes act  221 , forming word line  135 . In most embodiments, word line  135  is formed in one of the first (M 1 ) through third (M 3 ) metal interconnect layers  131 . In some embodiments, word line  135  is formed in the third (M 3 ) metal interconnect layer  131  as shown in  FIG. 9 . 
     Metal interconnect layers  131  include conductive lines and vias in matrices of dielectric  139 . The conductive lines and vias can be formed from any conductive material. In some embodiments, the conductive material is copper for all of the metal interconnect layer  131  above the first (M 1 ). The dielectric  139  can be any suitable dielectric and can include multiple layers of different dielectrics. In most embodiments, the dielectric  139  is a low-k dielectric. In some embodiments, the dielectric  139  is an extremely low-k dielectric. An extremely low-k dielectric is a material having a dielectric constant of about 2.1 or less. An extremely low-k dielectric is generally formed by a low dielectric material with 20% or more voids (pores or air gaps). In most embodiments, a dielectric etch stop layer  121  is formed over each of the first (M 1 ) through fourth (M 4 ) metal interconnect layers  131 . In most embodiments, metal interconnect layers  131  are formed by damascene or dual damascene processes. 
     Process  200  continues with a series of acts  230  that form RRAM cell  125 . The first of these acts is forming a hole  124  through which RRAM cell  125  can form a contact with a via  119  in the underlying metal interconnect layer  131  as shown in  FIGS. 10 and 11 . The hole  124  can be formed through dielectric  139 , or through just etch stop layer  121  as shown in the figures. 
     The series of acts  230  continues with act  233 , forming an RRAM stack  160  from which RRAM cell  125  is formed. In some embodiments, hole  124  is filled with conductive material to make a bottom electrode via prior to act  233 . In other embodiments, RRAM stack  160  is formed over hole  124  and fills hole  124  as shown in  FIG. 12 . In most embodiments, RRAM stack  160  includes a diffusion barrier layer  161 , a bottom electrode layer  163 , an RRAM dielectric layer  165 , a capping layer  167 , and a top electrode layer  169  as shown in  FIG. 12 . The order of these layers is for the case where bit line  133  is coupled to top electrode layer  169 . Where a capping layer  167  is included, the bit line can be identified as the addressing line coupled on the same side of RRAM dielectric layer  165  as capping layer  167 . 
     Diffusion barrier layer  161  is an optional layer. It can be included to prevent contamination of bottom electrode layer  163  by material from a bottom contact such as a via  119 . In some embodiments for which diffusion barrier layer  161  is included, the bottom contact is copper and bottom electrode  163  is a material susceptible to contamination by copper. In some of these embodiments, bottom electrode layer  163  is TiN. Diffusion barrier layer  161  can have any suitable composition and can be formed by any suitable process. In most embodiments, diffusion barrier layer  161  is a conductive oxide, nitride, or oxynitride of a metal selected from the group consisting of Al, Mn, Co, Ti, Ta, W, Ni, Sn, Mg. In some embodiments, diffusion barrier layer  161  is TaN. Diffusion barrier layer  161  can have any suitable thickness. A suitable thickness is large enough to provide an effective diffusion barrier while not being so large as to cause excessive resistance. In most embodiments, the thickness of diffusion barrier layer  161  is in the range from 20 Å to 300 Å. In some embodiments, the thickness of diffusion barrier layer  161  is in the range from 100 Å to 300 Å, for example, 200 Å. 
     Bottom electrode layer  163  can have any suitable composition and can be formed by any suitable process. Examples of suitable compositions include, without limitation, metals, metal nitrides, and doped polysilicon. In some embodiments, bottom electrode layer  163  is a metal. The metal could be, for example, Al, Ti, Ta, Au, Pt, W, Ni, Ir, or Cu. In some embodiments, bottom electrode layer  163  is a metal nitride. The metal nitride could be, for example, TaN. In some embodiments, bottom electrode layer  163  is a doped polysilicon. A doped polysilicon can be either a p+ doped polysilicon or an n+ doped polysilicon. In most embodiments, the thickness of bottom electrode layer  163  is in the range from 20 Å to 200 Å. In some embodiments, the thickness of bottom electrode layer  163  is in the range from 50 Å to 150 Å, for example, 100 Å. 
     RRAM dielectric  165  can be any material suitable for the data storage layer of an RRAM cell. A material suitable for the data storage layer of an RRAM cell is one that can be induced to undergo a reversible phase change between a high resistance state and a low resistance state. In some embodiments, the phase change is between an amorphous state and a metallic state. The phase change can be accompanied by or associated with a change in chemical composition. For example, an amorphous metal oxide may lose oxygen as it undergoes a phase change to a metallic state. The oxygen may be stored in a portion of RRAM dielectric  165  that remains in the amorphous state or in an adjacent layer. Although described as a dielectric, only the low resistance state need be a dielectric. In most embodiments, RRAM dielectric  165  is a high-k dielectric while in the low resistance state. In some embodiments, the RRAM dielectric  165  is a transitional metal oxide. Examples of materials that can be suitable for RRAM dielectric  165  include NiO X , Ta y O X , TiO X , HfO X , Ta y O X , WO X , ZrO X , Al y O X , and SrTiO X . In most embodiments, the thickness of RRAM dielectric  165  is in the range from 20 Å to 100 Å. In some embodiments, the thickness of RRAM dielectric  165  is in the range from 30 Å to 70 Å, for example, 50 Å. 
     Capping layer  167  is optional. In some embodiments, capping layer  167  provides an oxygen storage function that facilitates phase changes within the RRAM dielectric  165 . In some embodiments, capping layer  167  is a metal or a metal oxide that is relatively low in oxygen concentration. Examples of metals that can be suitable for capping layer  167  include Ti, Hf, Pt and Al. Examples of metal oxides that can be suitable for capping layer  167  include TiO X , HfO X , ZrO X , GeO X , CeO X . Capping layer  167  can have any suitable thickness. In most embodiments, the thickness of capping layer  167  is in the range from 20 Å to 100 Å. In some embodiments, the thickness of capping layer  167  is in the range from 30 Å to 70 Å, for example, 50 Å. Where capping layer  167  is provided, it is on the same side of RRAM dielectric  165  as the side to which bit line  133  is connected. 
     Top electrode layer  169  can have any of the compositions identified as suitable for bottom electrode layer  163 . Top electrode layer  169  can have any suitable thickness. In most embodiments, top electrode layer  169  has a thickness in the range from 100 Å to 400 Å. In typical embodiments, top electrode layer  169  has a thickness in the range from 150 Å to 300 Å, for example 250 Å. 
     The series of acts  230  that form RRAM cell  125  can continue with act  235 , patterning top electrode layer  169  and act  237 , forming spacers  171  as shown in  FIG. 13 . In most embodiments, act  235 , patterning top electrode layer  169  includes an etch that continues through capping layer  167 . In most embodiments, RRAM dielectric  165  provides an etch stop for patterning top electrode  169 . Act  237 , forming spacers  171 , includes depositing a layer of spacer material and etching to form spacers  171 . Spacer  171  can be formed of any suitable spacer material. Examples of materials suitable for spacers  171  include, without limitation, SiN, SiON and SiO 2 . 
     The series of acts  230  continues with act  239 , which is patterning bottom electrode layer  163  to form a structure as shown in  FIG. 14 . As shown in  FIG. 14 , patterning bottom electrode layer  163  can include patterning capping layer  161 . 
     Process  200  continues with act  240 , forming top electrode via  129  to form a structure as shown in  FIGS. 15 and 16 . In most embodiments, forming top electrode via  129  includes forming a layer of dielectric  139 , patterning a hole through the dielectric layer  139  for top electrode via  129 , and filling the hole with metal to form top electrode via  129  as shown in  FIGS. 15 and 16 . 
     Process  200  continues with act  250 , forming the fifth (M 5 ) metal interconnect layer  131  to form a structure as shown in  FIG. 17 . In this example, forming the fifth (M 5 ) metal interconnect layer  131  includes act  251 , forming bit line  133 . The sequence of process  200  places bit line  133  above RRAM cell  125 . 
     Process  200  continues with act  250 , forming the sixth (M 6 ) metal interconnect layer  131  to form a structure as shown in  FIG. 1 . In this example, forming the sixth (M 6 ) metal interconnect layer  131  includes act  261 , forming source line  137 . The sequence of process  200  places source line  137  above RRAM cell  125  and above bit line  133 . With conventional scaling of metal interconnect layers  131 , this makes the cross-sectional area of source line  137  greater than the cross-sectional area of bit line  133  and greater than the cross-sectional area of a source line formed before RRAM cell  125 . 
     Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area. 
     Another embodiment of the present disclosure is an integrated circuit (IC) device including an array of memory cells disposed above a substrate. The array of memory cells is located between first and second metal interconnect layers arranged over the substrate. A plurality of first metal lines, which correspond to the first metal interconnect layer, are connected to the memory cells of the array. Each of the plurality of first metal lines has a first cross-sectional area. A plurality of second metal lines, which correspond to the second metal interconnect layer, are operatively coupled to the memory cells of the array. Each of the plurality of second metal lines has a second cross-sectional area which is greater than the first cross-sectional area. 
     Another embodiment of the present disclosure is an integrated circuit (IC) device including a plurality of metal interconnect layers above a substrate. A memory cell is disposed above the substrate between two of the plurality of metal interconnect layers. The memory cell includes a top electrode, a bottom electrode, and a data storage element located between the top electrode and the bottom electrode. A first metal line is located in a first metal interconnect layer and is connected to the top electrode of the memory cell. The first metal line has a first cross-sectional area. A second metal line is located in a second metal interconnect layer which is higher above the substrate than the first metal interconnect layer. The second metal line has a second cross-sectional area greater than the first cross-sectional area. A transistor device is arranged within the substrate and has a first terminal connected to the bottom electrode of the memory cell and a second terminal connected to the second metal line. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.